Merge remote-tracking branch cros/main into firmware-fpmcu-dartmonkey-releasefirmware-fpmcu-dartmonkey-release

Generated by: ./util/update_release_branch.py --board dartmonkey --relevant_paths_file
./util/fingerprint-relevant-paths.txt firmware-fpmcu-dartmonkey-release

Relevant changes:

git log --oneline 6c1587ca70..28712dae9d -- board/nocturne_fp
board/dartmonkey common/fpsensor docs/fingerprint driver/fingerprint
util/getversion.sh

ded9307b79 util/getversion.sh: Fix version when not in a git repo
956055e692 board: change Google USB vendor info
71b2ef709d Update license boilerplate text in source code files
33e11afda0 Revert "fpsensor: Build fpsensor source file with C++"
c8d0360723 fpsensor: Build fpsensor source file with C++
bc113abd53 fpsensor: Fix g++ compiler error
150a58a0dc fpsensor: Fix fp_set_sensor_mode return type
b33b5ce85b fpsensor: Remove nested designators for C++ compatibility
2e864b2539 tree-wide: const-ify argv for console commands
56d8b360f9 test: Add test for get ikm failure when seed not set
3a3d6c3690 test: Add test for fpsensor trivial key failure
233e6bbd08 fpsensor_crypto: Abstract calls to hmac_SHA256
0a041b285b docs/fingerprint: Typo correction
c03fab67e2 docs/fingerprint: Fix the path of fputils.py
0b5d4baf5a util/getversion.sh: Fix empty file list handling
6e128fe760 FPMCU dev board environment with Satlab
3eb29b6aa5 builtin: Move ssize_t to sys/types.h
345d62ebd1 docs/fingerprint: Update power numbers for latest dartmonkey release
c25ffdb316 common: Conditionally support printf %l and %i modifiers
9a3c514b45 test: Add a test to check if the debugger is connected
54e603413f Move standard library tests to their own file
43fa6b4bf8 docs/fingerprint: Update power numbers for latest bloonchipper release
25536f9a84 driver/fingerprint/fpc/bep/fpc_sensor_spi.c: Format with clang-format
4face99efd driver/fingerprint/fpc/libfp/fpc_sensor_pal.h: Format with clang-format
738de2b575 trng: Rename rand to trng_rand
14b8270edd docs/fingerprint: Update dragonclaw power numbers
0b268f93d1 driver/fingerprint/fpc/libfp/fpc_private.c: Format with clang-format
f80da163f2 driver/fingerprint/fpc/libfp/fpc_private.h: Format with clang-format
a0751778f4 board/nocturne_fp/ro_workarounds.c: Format with clang-format
5e9c85c9b1 driver/fingerprint/fpc/libfp/fpc_sensor_pal.c: Format with clang-format
c1f9dd3cf8 driver/fingerprint/fpc/libfp/fpc_bio_algorithm.h: Format with clang-format
eb1e1bed8d driver/fingerprint/fpc/libfp/fpc1145_private.h: Format with clang-format
6e7b611821 driver/fingerprint/fpc/bep/fpc_bio_algorithm.h: Format with clang-format
e0589cd5e2 driver/fingerprint/fpc/bep/fpc1035_private.h: Format with clang-format
58f0246dbe board/nocturne_fp/board_ro.c: Format with clang-format
7905e556a0 common/fpsensor/fpsensor_crypto.c: Format with clang-format
21289d170c driver/fingerprint/fpc/bep/fpc1025_private.h: Format with clang-format
98a20f937e common/fpsensor/fpsensor_state.c: Format with clang-format
a2d255d8af common/fpsensor/fpsensor.c: Format with clang-format
84e53a65da board/nocturne_fp/board.h: Format with clang-format
73055eeb3f driver/fingerprint/fpc/bep/fpc_private.c: Format with clang-format
0f7b5cb509 common/fpsensor/fpsensor_private.h: Format with clang-format
1ceade6e65 driver/fingerprint/fpc/bep/fpc_private.h: Format with clang-format
dca9d74321 Revert "trng: Rename rand to trng_rand"
a6b0b3554f trng: Rename rand to trng_rand
28d0b75b70 third_party/boringssl: Remove unused header

BRANCH=None
BUG=b:244387210 b:242720240 b:215613183 b:242720910 b:236386294
BUG=b:234181908 b:244781166 b:234781655 b:234143158 b:234181908
BUG=b:237344361 b:236025198 b:234181908 b:180945056 chromium:1098010
BUG=b:246424843 b:234181908 b:131913998
TEST=`make -j buildall`
TEST=./util/run_device_tests.py --board dartmonkey
     Test "aes": PASSED
     Test "cec": PASSED
     Test "cortexm_fpu": PASSED
     Test "crc": PASSED
     Test "flash_physical": PASSED
     Test "flash_write_protect": PASSED
     Test "fpsensor_hw": PASSED
     Test "fpsensor_spi_ro": PASSED
     Test "fpsensor_spi_rw": PASSED
     Test "fpsensor_uart_ro": PASSED
     Test "fpsensor_uart_rw": PASSED
     Test "mpu_ro": PASSED
     Test "mpu_rw": PASSED
     Test "mutex": PASSED
     Test "pingpong": PASSED
     Test "printf": PASSED
     Test "queue": PASSED
     Test "rollback_region0": PASSED
     Test "rollback_region1": PASSED
     Test "rollback_entropy": PASSED
     Test "rtc": PASSED
     Test "sha256": PASSED
     Test "sha256_unrolled": PASSED
     Test "static_if": PASSED
     Test "stdlib": PASSED
     Test "system_is_locked_wp_on": PASSED
     Test "system_is_locked_wp_off": PASSED
     Test "timer_dos": PASSED
     Test "utils": PASSED
     Test "utils_str": PASSED
     Test "panic_data_dartmonkey_v2.0.2887": PASSED
     Test "panic_data_nocturne_fp_v2.2.64": PASSED
     Test "panic_data_nami_fp_v2.2.144": PASSED
Force-Relevant-Builds: all
Signed-off-by: Tom Hughes <tomhughes@chromium.org>

Change-Id: I2c312583a709fedae8fe11d92c22328c3b634bc7

5697 files changed, 198947 insertions, 164619 deletions

diff --git a/.checkpatch.conf b/.checkpatch.conf
index 28ccc0dbb9..511019b260 100644
--- a/.checkpatch.conf
+++ b/.checkpatch.conf
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -26,3 +26,6 @@
 # easier to upstream into the Zephyr tree, we should do the same.
 # Tell checkpatch to ignore Linux style here.
 --ignore BRACES
+
+# Zephyr uses ENOSYS to indicate unsupported API calls
+--ignore ENOSYS
diff --git a/zephyr/zmake/.flake8 b/.flake8
index 0a0a9c29ab..f5d6acc820 100644
--- a/zephyr/zmake/.flake8
+++ b/.flake8
@@ -1,5 +1,4 @@
 [flake8]
-max-line-length = 88
 extend-ignore = E203
 exclude =
     .hypothesis,
diff --git a/.gitignore b/.gitignore
index 49c5321a0c..f5c02e557a 100644
--- a/.gitignore
+++ b/.gitignore
@@ -31,3 +31,7 @@ zephyr/zmake/.coverage
 # Clangd language server
 .cache/clangd/index/*
 compile_commands.json
+
+# Twister test output directories
+twister-out*
+flash.bin
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index a6e7ad4d5a..b7025dc99b 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -1,90 +1,121 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
-image: sjg20/ubuntu-25feb22c
+image: jbettis/ubuntu-07sep22
 
 # You can update that image using this repo:
 #   https://gitlab.com/zephyr-ec/gitlab-ci-runner/-/tree/main
 
-# Change pip's cache directory to be inside the project directory since we can
-# only cache local items.
-variables:
-  PIP_CACHE_DIR: "$CI_PROJECT_DIR/.cache/pip"
-
-# Pip's cache doesn't store the python packages
-# https://pip.pypa.io/en/stable/reference/pip_install/#caching
-#
-# If you want to also cache the installed packages, you have to install
-# them in a virtualenv and cache it as well.
-cache:
-  key: ${CI_COMMIT_SHA}
-  policy: pull
-  paths:
-    - .cache/pip
-    - venv/
-    - modules/
-    - zephyr/
-
+# Only run on main and coverage branches
+workflow:
+  rules:
+    - if: ($CI_COMMIT_BRANCH == "main" || $CI_COMMIT_BRANCH == "coverage")
 
 # The directory structure is:
 #
-# /zephyr
-# /builds/zephyr-ec/ec       EC_DIR
+# ${CI_PROJECT_DIR}
+#    |_ ec_dir/           - EC repo (${EC_DIR})
+#        |_ build/        - make and zmake artifacts (${BUILD_DIR})
+#        |_ twister-out/  - Twister artifacts (${TWISTER_OUT_DIR})
+#    |_ modules/          - Additional Zephyr modules (${MODULES_DIR})
+#    |   |_ cmsis/
+#    |   |_ hal_stm32/
+#    |   |_ nanopb/
+#    |   |_ cryptoc/
+#    |_ zephyr/
+#        |_ main/         - Zephyr repo (${ZEPHYR_BASE})
+#
+# On Gitlab builds, ${CI_PROJECT_DIR} is at /builds/zephyr-ec/ec. On local
+# builds, it will be /builds/0/project-0.
+
 before_script:
+  - echo "CI_PROJECT_DIR is at ${CI_PROJECT_DIR}"
+  # Move freshly-checked out ec code to subdirectory
+  - cd ${CI_PROJECT_DIR}
+  - mkdir -p ec_dir
+  - find . -mindepth 1 -maxdepth 1 -name ec_dir -o -print0 | xargs -0 -I {} mv {} ec_dir
+  - export EC_DIR="${CI_PROJECT_DIR}/ec_dir"
   - export MODULES_DIR="$CI_PROJECT_DIR/modules"
-  - mkdir -p "${MODULES_DIR}"
   - export ZEPHYR_BASE="${CI_PROJECT_DIR}/zephyr/main"
-  - mkdir -p "${ZEPHYR_BASE}"
-  - test -d "${ZEPHYR_BASE}/.git" || git clone --depth 1 -b main https://chromium.googlesource.com/chromiumos/third_party/zephyr "${ZEPHYR_BASE}"
-  - test -d "${MODULES_DIR}/cmsis" || git clone --depth 1 -b chromeos-main https://chromium.googlesource.com/chromiumos/third_party/zephyr/cmsis "${MODULES_DIR}/cmsis"
-  - test -d "${MODULES_DIR}/hal_stm32" || git clone --depth 1 -b chromeos-main https://chromium.googlesource.com/chromiumos/third_party/zephyr/hal_stm32 "${MODULES_DIR}/hal_stm32"
-  - test -d "${MODULES_DIR}/nanopb" || git clone --depth 1 -b main https://chromium.googlesource.com/chromiumos/third_party/zephyr/nanopb "${MODULES_DIR}/nanopb"
-  - test -d "${MODULES_DIR}/cryptoc" || git clone --depth 1 -b main https://chromium.googlesource.com/chromiumos/third_party/cryptoc "${MODULES_DIR}/cryptoc"
-  - ln -s "$(pwd)" "${MODULES_DIR}/ec"
+  - git config --global --add safe.directory '*'
+  # Get Zephyr repo and modules
+  - checkout_at_date() {
+            local url="$1" ;
+            local branch="$2" ;
+            local path="$3" ;
+            local date="$4" ;
+            local retries=5 ;
+
+            while [ ${retries} -gt 0 ] ; do
+              rm -rf "${path}" ;
+              mkdir -p "${path}" ;
+              if git clone --depth 1 -b "${branch}" "${url}" "${path}"; then
+                break ;
+              else
+                echo "git clone failed will retry ${retries} times";
+              fi ;
+              retries="$(( ${retries} - 1 ))" ;
+            done ;
+            cd "${path}" ;
+            rev="$(git rev-list -n 1 --before="${date}" "${branch}")" ;
+            depth=1 ;
+            while [ -z "${rev}" ] ; do
+              depth="$(( ${depth} + 100 ))" ;
+              git fetch --depth="${depth}" ;
+              rev="$(git rev-list -n 1 --before="${date}" "${branch}")" ;
+            done ;
+            git checkout -d "${rev}" ;
+    }
+  - ec_commit_date="$(cd ${EC_DIR} ; git log -1 HEAD --format=%cd --date=iso)"
+  - checkout_at_date "https://chromium.googlesource.com/chromiumos/third_party/zephyr" "main" "${ZEPHYR_BASE}" "${ec_commit_date}"
+  - checkout_at_date "https://chromium.googlesource.com/chromiumos/third_party/zephyr/cmsis" "chromeos-main" "${MODULES_DIR}/cmsis" "${ec_commit_date}"
+  - checkout_at_date "https://chromium.googlesource.com/chromiumos/third_party/zephyr/hal_stm32" "chromeos-main" "${MODULES_DIR}/hal_stm32" "${ec_commit_date}"
+  - checkout_at_date "https://chromium.googlesource.com/chromiumos/third_party/zephyr/nanopb" "main" "${MODULES_DIR}/nanopb" "${ec_commit_date}"
+  - checkout_at_date "https://chromium.googlesource.com/chromiumos/third_party/cryptoc" "main" "${MODULES_DIR}/cryptoc" "${ec_commit_date}"
+  # Add a symlink so the ec appears in modules directory (hack to make zmake work)
+  - ln -s "${EC_DIR}" "${MODULES_DIR}/ec"
+  # Install Python and packages
   - python3 -V  # Print out python version for debugging
-  - python3 -m pip install 'zephyr/zmake[tests]' --user
-  - python3 -m pip install pyyaml packaging
-  - export BUILD_DIR=build
+  - python3 -m pip install "${EC_DIR}/zephyr/zmake[tests]" --user
+  - python3 -m pip install pyyaml packaging ply psutil 'pyelftools>=0.28'
   - export PATH="$PATH:$HOME/.local/bin"
   - export PYTHONIOENCODING=utf-8
-  - export EC_DIR=/builds/zephyr-ec/ec
-
-seed_cache:
-  stage: build
-  needs: []
-  cache:
-    key: ${CI_COMMIT_SHA}
-    paths:
-      - .cache/pip
-      - venv/
-      - modules/
-      - zephyr/
-    policy: push
-  script:
-    - ls "${MODULES_DIR}" "${ZEPHYR_BASE}"
+  # Build directory
+  - export BUILD_DIR=${EC_DIR}/build
+  - export TWISTER_OUT_DIR=${EC_DIR}/twister-out
+  # Set up Twister to use the "host" toolchain, as defined in upstream Zephyr
+  # repo, ultimately including ${ZEPHYR_BASE}/cmake/toolchain/host/generic.cmake
+  - export TOOLCHAIN_ROOT=${ZEPHYR_BASE}
+  - export ZEPHYR_TOOLCHAIN_VARIANT=host
 
 # Users of this template must set:
 # $PROJECT to the project to build. E.g., "lazor"
 .build_template: &build_template
   stage: build
-  needs: ["seed_cache"]
+  needs: []
   script:
     - zmake --zephyr-base "${ZEPHYR_BASE}"
       --modules-dir "${MODULES_DIR}" -l DEBUG build
       -B "${BUILD_DIR}" -t ${TOOLCHAIN:-zephyr}
       "${PROJECT}"
     - for b in "${BUILD_DIR}/${PROJECT}"/build-* ; do
-      bdir=$(basename ${b}) ;
-      ninja -C ${b} ram_report >"${BUILD_DIR}/${PROJECT}/output/${bdir}_ram_report.txt" ;
-      cp ${b}/ram.json "${BUILD_DIR}/${PROJECT}/output/${bdir}_ram.json" ;
-      ninja -C ${b} rom_report >"${BUILD_DIR}/${PROJECT}/output/${bdir}_rom_report.txt" ;
-      cp ${b}/rom.json "${BUILD_DIR}/${PROJECT}/output/${bdir}_rom.json" ;
+        bdir=$(basename ${b}) ;
+        if ninja -C ${b} ram_report >"${BUILD_DIR}/${PROJECT}/output/${bdir}_ram_report.txt" ; then
+          cp ${b}/ram.json "${BUILD_DIR}/${PROJECT}/output/${bdir}_ram.json" ;
+        else
+          echo "Ram report failed" ;
+        fi ;
+        if ninja -C ${b} rom_report >"${BUILD_DIR}/${PROJECT}/output/${bdir}_rom_report.txt" ; then
+          cp ${b}/rom.json "${BUILD_DIR}/${PROJECT}/output/${bdir}_rom.json" ;
+        else
+          echo "Rom report failed" ;
+        fi ;
       done
     - ls "${BUILD_DIR}/${PROJECT}" "${BUILD_DIR}/${PROJECT}/output"
   artifacts:
     paths:
-      - build/${PROJECT}/output/*
+      - ec_dir/build/${PROJECT}/output/*
     expire_in: 1 week
 
 # Users of this template must set:
@@ -98,6 +129,7 @@ seed_cache:
   stage: test
   needs: ["merged_coverage", "zephyr_coverage", "twister_coverage"]
   script:
+    - cd ${EC_DIR}
     - zmake --zephyr-base "${ZEPHYR_BASE}"
       --modules-dir "${MODULES_DIR}" -l DEBUG build --coverage
       -B "${BUILD_DIR}" -t ${TOOLCHAIN:-zephyr}
@@ -145,8 +177,8 @@ seed_cache:
       -s "${BUILD_DIR}/${PROJECT}/output/filtered_no_zephyr.info"
   artifacts:
     paths:
-      - build/${PROJECT}/output/*.info
-      - build/${PROJECT}/output/*_rpt
+      - ec_dir/build/${PROJECT}/output/*.info
+      - ec_dir/build/${PROJECT}/output/*_rpt
     expire_in: 1 week
     when: always
   coverage: '/lines\.*: \d+\.\d+%/'
@@ -191,12 +223,6 @@ lazor:
     PROJECT: "lazor"
   <<: *build_template
 
-native_posix:
-  variables:
-    PROJECT: "posix-ec"
-    TOOLCHAIN: "host"
-  <<: *build_template
-
 npcx7_evb:
   variables:
     PROJECT: "npcx7"
@@ -219,42 +245,48 @@ skyrim_coverage:
 
 ec_coverage:
   stage: test
-  needs: ["seed_cache"]
+  needs: []
   script:
-    - make -j8 CRYPTOC_DIR="${MODULES_DIR}/cryptoc"
-      HOSTGCOV='gcov'
+    - cd ${EC_DIR}
+    - make -j$(nproc) CRYPTOC_DIR="${MODULES_DIR}/cryptoc"
       CROSS_COMPILE_arm=/opt/zephyr-sdk/arm-zephyr-eabi/bin/arm-zephyr-eabi-
+      CROSS_COMPILE_host=/usr/bin/
       test-coverage
   artifacts:
     paths:
-      - build/coverage/coverage_rpt/*
-      - build/coverage/lcov.info
+      - ec_dir/build/coverage/coverage_rpt/*
+      - ec_dir/build/coverage/lcov.info
     expire_in: 1 week
   coverage: '/lines\.*: \d+\.\d+%/'
 
 zephyr_coverage:
   stage: test
-  needs: ["seed_cache"]
+  needs: []
   script:
-    - zmake --zephyr-base "${ZEPHYR_BASE}"
-      --modules-dir "${MODULES_DIR}" -l DEBUG test
-      --coverage --host-tests-only
+    - python3 ${EC_DIR}/twister --coverage --outdir "${TWISTER_OUT_DIR}"
+      -v -i --gcov-tool gcov -x=ALLOW_WARNINGS=ON
   artifacts:
     paths:
-      - build/zephyr/all_tests.info
+      - ec_dir/twister-out/coverage.info
     expire_in: 1 week
   coverage: '/lines\.*: \d+\.\d+%/'
 
 zephyr_boards_coverage:
   stage: build
-  needs: ["seed_cache"]
+  needs: []
+  parallel: 5
   script:
+    - cd ${EC_DIR}
+    - projects=( $(zmake --zephyr-base "${ZEPHYR_BASE}"
+      --modules-dir "${MODULES_DIR}" list-projects |
+      split -n r/"${CI_NODE_INDEX}"/"${CI_NODE_TOTAL}") )
     - zmake --zephyr-base "${ZEPHYR_BASE}"
       --modules-dir "${MODULES_DIR}" -l DEBUG build
-      --coverage -a
+      --coverage --delete-intermediates "${projects[@]}"
+    - mv build/zephyr/all_builds.info "build/zephyr/all_builds${CI_NODE_INDEX}.info"
   artifacts:
     paths:
-      - build/zephyr/all_builds.info
+      - ec_dir/build/zephyr/all_builds*.info
     expire_in: 1 week
   coverage: '/lines\.*: \d+\.\d+%/'
 
@@ -264,10 +296,10 @@ merged_coverage:
   stage: test
   needs: ["ec_coverage", "zephyr_coverage", "zephyr_boards_coverage"]
   script:
-    - lcov --rc lcov_branch_coverage=1 -o build/merged.info
-      -a build/coverage/lcov.info -a build/zephyr/all_tests.info
-    - lcov --rc lcov_branch_coverage=1 -o build/merged_no_zephyr.info
-      -r build/merged.info
+    - lcov --rc lcov_branch_coverage=1 -o ${BUILD_DIR}/merged.info
+      -a ${BUILD_DIR}/coverage/lcov.info -a "${TWISTER_OUT_DIR}/coverage.info"
+    - lcov --rc lcov_branch_coverage=1 -o ${BUILD_DIR}/merged_no_zephyr.info
+      -r ${BUILD_DIR}/merged.info
       "${ZEPHYR_BASE}/**" "${MODULES_DIR}/**"
       "${EC_DIR}/zephyr/drivers/**" "${EC_DIR}/zephyr/include/drivers/**"
       "${EC_DIR}/zephyr/shim/chip/**" "${EC_DIR}/zephyr/shim/core/**"
@@ -276,10 +308,10 @@ merged_coverage:
       "${EC_DIR}/zephyr/shim/chip/npcx/npcx_monitor/**"
       "${EC_DIR}/zephyr/emul/**" "${EC_DIR}/zephyr/test/**"
       "**/testsuite/**" "**/subsys/emul/**"
-    - lcov --rc lcov_branch_coverage=1 -o "build/all_builds_merged.info"
-      -a "build/zephyr/all_builds.info" -a build/merged.info
-    - lcov --rc lcov_branch_coverage=1 -o "build/all_builds_no_zephyr.info"
-      -r "build/all_builds_merged.info" "${ZEPHYR_BASE}/**"
+    - lcov --rc lcov_branch_coverage=1 -o "${BUILD_DIR}/all_builds_merged.info"
+      -a ${BUILD_DIR}/merged.info $(printf ' -a %s' ${BUILD_DIR}/zephyr/all_builds[0-9]*.info)
+    - lcov --rc lcov_branch_coverage=1 -o "${BUILD_DIR}/all_builds_no_zephyr.info"
+      -r "${BUILD_DIR}/all_builds_merged.info" "${ZEPHYR_BASE}/**"
       "${ZEPHYR_BASE}/**" "${MODULES_DIR}/**"
       "${EC_DIR}/zephyr/drivers/**" "${EC_DIR}/zephyr/include/drivers/**"
       "${EC_DIR}/zephyr/shim/chip/**" "${EC_DIR}/zephyr/shim/core/**"
@@ -288,66 +320,66 @@ merged_coverage:
       "${EC_DIR}/zephyr/shim/chip/npcx/npcx_monitor/**"
       "${EC_DIR}/zephyr/emul/**" "${EC_DIR}/zephyr/test/**"
       "**/testsuite/**" "**/subsys/emul/**"
-    - grep "SF:" "build/zephyr/all_builds.info" | sort -u |
+    - grep -h "SF:" ${BUILD_DIR}/zephyr/all_builds[0-9]*.info | sort -u |
       sed -e 's|^SF:||' | xargs lcov --rc lcov_branch_coverage=1
-      -o "build/all_builds_filtered.info"
-      -e "build/all_builds_no_zephyr.info"
+      -o "${BUILD_DIR}/all_builds_filtered.info"
+      -e "${BUILD_DIR}/all_builds_no_zephyr.info"
     - /usr/bin/genhtml --branch-coverage -q
-      -o "build/all_builds_filtered_rpt"
+      -o "${BUILD_DIR}/all_builds_filtered_rpt"
       -t "All boards coverage w/o zephyr"
       -p ${EC_DIR}
-      -s "build/all_builds_filtered.info"
+      -s "${BUILD_DIR}/all_builds_filtered.info"
   artifacts:
     paths:
-      - build/*.info
-      - build/*_rpt
+      - ec_dir/build/*.info
+      - ec_dir/build/*_rpt
     expire_in: 1 week
   coverage: '/lines\.*: \d+\.\d+%/'
 
 testall:
   stage: test
-  needs: ["seed_cache"]
+  needs: []
   script:
-    - zmake --zephyr-base "${ZEPHYR_BASE}"
-      --modules-dir "${MODULES_DIR}" -l DEBUG test --host-tests-only
+    - python3 ${EC_DIR}/twister --outdir "${TWISTER_OUT_DIR}" -v -i
+      -x=ALLOW_WARNINGS=ON
 
 twister_coverage:
   stage: test
-  needs: ["seed_cache"]
+  needs: []
   script:
-    - mkdir -p build/zephyr_codecov
+    - mkdir -p ${BUILD_DIR}/zephyr_codecov
     - for commitid in $(cd "${ZEPHYR_BASE}" ; git fetch --depth=100 ; git log | awk '/GitOrigin-RevId:/ {print $2}') ; do
         echo "COMMITID = ${commitid?}" ;
         if wget -O /tmp/coverage.html "https://codecov.io/gh/zephyrproject-rtos/zephyr/commit/${commitid?}/build" ; then
           downloadurl=$(sed -e '/download\/build/!d' -e 's|^.*href="|https://codecov.io|' -e 's|".*$||' /tmp/coverage.html | head -1) ;
           echo "DOWNLOADURL = ${downloadurl?}" ;
-          wget -O build/zephyr_codecov/merged.info.raw "${downloadurl?}" ;
-          sed <build/zephyr_codecov/merged.info.raw >build/zephyr_codecov/merged.info
+          wget -O ${BUILD_DIR}/zephyr_codecov/merged.info.raw "${downloadurl?}" ;
+          sed <${BUILD_DIR}/zephyr_codecov/merged.info.raw >${BUILD_DIR}/zephyr_codecov/merged.info
             -e '1,/<<<<<< network/d' -e '/<<<<<< EOF/,$d' ;
-          sed <build/zephyr_codecov/merged.info >build/zephyr_codecov/fixed.info
+          sed <${BUILD_DIR}/zephyr_codecov/merged.info >${BUILD_DIR}/zephyr_codecov/fixed.info
             -e "s|/__w/zephyr/zephyr|${ZEPHYR_BASE}|"
             -e "s|/__w/zephyr/modules/hal/cmsis|${MODULES_DIR}/cmsis|"
             -e "s|/__w/zephyr/modules|${MODULES_DIR}|" ;
           break ;
         fi ;
       done
-    - lcov --rc lcov_branch_coverage=1 --summary build/zephyr_codecov/fixed.info
+    - lcov --rc lcov_branch_coverage=1 --summary ${BUILD_DIR}/zephyr_codecov/fixed.info
   artifacts:
     paths:
-      - build/zephyr_codecov/fixed.info
+      - ec_dir/build/zephyr_codecov/fixed.info
     expire_in: 1 week
   coverage: '/lines\.*: \d+\.\d+%/'
 
 zmake_coverage:
   stage: test
-  needs: ["seed_cache"]
+  needs: []
   script:
-    - cd zephyr/zmake
+    - cd ${EC_DIR}/zephyr/zmake
     - coverage run --source=zmake -m pytest .
     - coverage report
     - coverage html
   artifacts:
     paths:
-      - zephyr/zmake/htmlcov/*
+      - ec_dir/zephyr/zmake/htmlcov/*
     expire_in: 1 week
   coverage: '/^TOTAL.+?(\d+\%)$/'
diff --git a/zephyr/zmake/.isort.cfg b/.isort.cfg
index b9fb3f3e8c..b9fb3f3e8c 100644
--- a/zephyr/zmake/.isort.cfg
+++ b/.isort.cfg
diff --git a/.vscode/settings.json.default b/.vscode/settings.json.default
index 1868e4f3af..2c9497413a 100644
--- a/.vscode/settings.json.default
+++ b/.vscode/settings.json.default
@@ -6,6 +6,7 @@
    /* C, Makefiles, ASM, Linkerfiles, Properties */
    "editor.insertSpaces": false,
    "editor.tabSize": 8,
+   "python.formatting.provider": "black",
    /* Some exceptions based on current trends */
    "[markdown]": {
       "editor.insertSpaces": true,
@@ -13,7 +14,7 @@
    },
    "[python]": {
       "editor.insertSpaces": true,
-      "editor.tabSize": 2
+      "editor.tabSize": 4
    },
    "[shellscript]": {
       "editor.insertSpaces": true,
diff --git a/DIR_METADATA b/DIR_METADATA
new file mode 100644
index 0000000000..526b1dd7ed
--- /dev/null
+++ b/DIR_METADATA
@@ -0,0 +1,17 @@
+# Metadata information for this directory.
+#
+# For more information on DIR_METADATA files, see:
+#   https://source.chromium.org/chromium/infra/infra/+/main:go/src/infra/tools/dirmd/README.md
+#
+# For the schema of this file, see Metadata message:
+#   https://source.chromium.org/chromium/infra/infra/+/main:go/src/infra/tools/dirmd/proto/dir_metadata.proto
+
+buganizer {
+  component_id: 167114  # ChromeOS > Platform > Enablement > Firmware > EC
+}
+
+buganizer_public {
+  component_id: 960650  # ChromeOS Public Tracker > Core Systems > Firmware > EC
+}
+
+team_email: "cros-ec@google.com"
diff --git a/LICENSE b/LICENSE
index da112abc64..a55bf15b9d 100644
--- a/LICENSE
+++ b/LICENSE
@@ -1,4 +1,4 @@
-// Copyright 2010 The Chromium OS Authors. All rights reserved.
+// Copyright 2010 The ChromiumOS Authors
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
@@ -10,7 +10,7 @@
 // copyright notice, this list of conditions and the following disclaimer
 // in the documentation and/or other materials provided with the
 // distribution.
-//    * Neither the name of Google Inc. nor the names of its
+//    * Neither the name of Google LLC nor the names of its
 // contributors may be used to endorse or promote products derived from
 // this software without specific prior written permission.
 //
diff --git a/Makefile b/Makefile
index 3a36b91125..5dc693c793 100644
--- a/Makefile
+++ b/Makefile
@@ -1,4 +1,4 @@
-# Copyright 2011 The Chromium OS Authors. All rights reserved.
+# Copyright 2011 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -115,6 +115,12 @@ CFLAGS_BASEBOARD=
 endif
 include chip/$(CHIP)/build.mk
 
+# The toolchain must be set before referencing any toolchain-related variables
+# (CC, CPP, CXX, etc.) so that the correct toolchain is used. The CORE variable
+# is set in the CHIP build file, so this include must come after including the
+# CHIP build file.
+include core/$(CORE)/toolchain.mk
+
 # Create uppercase config variants, to avoid mixed case constants.
 # Also translate '-' to '_', so 'cortex-m' turns into 'CORTEX_M'.  This must
 # be done before evaluating config.h.
@@ -260,6 +266,9 @@ include $(BASEDIR)/build.mk
 ifneq ($(BASEDIR),$(BDIR))
 include $(BDIR)/build.mk
 endif
+ifeq ($(USE_BUILTIN_STDLIB), 1)
+include builtin/build.mk
+endif
 include chip/$(CHIP)/build.mk
 include core/$(CORE)/build.mk
 include common/build.mk
@@ -299,6 +308,9 @@ ifneq ($(PBDIR),)
 all-obj-$(1)+=$(call objs_from_dir_p,$(PBDIR),board-private,$(1))
 endif
 all-obj-$(1)+=$(call objs_from_dir_p,common,common,$(1))
+ifeq ($(USE_BUILTIN_STDLIB), 1)
+all-obj-$(1)+=$(call objs_from_dir_p,builtin,builtin,$(1))
+endif
 all-obj-$(1)+=$(call objs_from_dir_p,driver,driver,$(1))
 all-obj-$(1)+=$(call objs_from_dir_p,power,power,$(1))
 ifdef CTS_MODULE
@@ -345,6 +357,9 @@ dirs=core/$(CORE) chip/$(CHIP) $(BASEDIR) $(BDIR) common fuzz power test \
 dirs+= private private-kandou $(PDIR) $(PBDIR)
 dirs+=$(shell find common -type d)
 dirs+=$(shell find driver -type d)
+ifeq ($(USE_BUILTIN_STDLIB), 1)
+dirs+=builtin
+endif
 common_dirs=util
 
 ifeq ($(custom-ro_objs-y),)
diff --git a/Makefile.ide b/Makefile.ide
new file mode 100644
index 0000000000..f8174f17df
--- /dev/null
+++ b/Makefile.ide
@@ -0,0 +1,75 @@
+# -*- makefile -*-
+# vim: set filetype=make :
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Embedded Controller firmware build system - IDE integration support
+#
+
+# If env EXTERNAL_TRUNK_PATH is defined, we use this to build the
+# absolute path to the ec directory. Otherwise, we just take the abspath of ".".
+ide_ec_path_ext = \
+	$(if $(EXTERNAL_TRUNK_PATH),$(EXTERNAL_TRUNK_PATH)/src/platform/ec)
+ide_ec_path_abs = $(abspath .)
+ide_ec_path = $(or $(ide_ec_path_ext),$(ide_ec_path_abs))
+
+# Clang doesn't support these GCC options.
+ide_cflags = $(filter-out -mno-sched-prolog -fconserve-stack,$(CFLAGS))
+
+# The all-ide-compile-cmds target takes about 2 minutes using 8 cores when all
+# work is replaced by the |true| command. Thus, the build system itself
+# takes 2m independent of the text manipulation.
+.PHONY: all-ide-compile-cmds
+all-ide-compile-cmds: $(foreach b, $(BOARDS), ide-compile-cmds-$(b))
+ide-compile-cmds-%:
+	$(MAKE) BOARD=$* V=$(V) ide-compile-cmds
+
+ide-compile-cmds-y                        = $(out)/RW/compile_commands.json
+ide-compile-cmds-$(CONFIG_FW_INCLUDE_RO) += $(out)/RO/compile_commands.json
+
+.PHONY: ide-compile-cmds
+ide-compile-cmds: $(ide-compile-cmds-y)
+
+# All but the last file/json-object need to have a trailing comma.
+#
+# The first sed line prepends 4 spaces to all lines and then adds a
+# comma + implicit-newline to the end of the last line of the file.
+# The second sed line prepends 4 spaces to all lines and then adds an
+# implicit new line.
+cmd_combine_compile_cmd_json =                                                 \
+	printf '[\n'                                                      >$@ ;\
+	echo $^ | xargs -n1 | head -n-1 | xargs -n1 sed 's/^/    /;$$s/$$/,/'  \
+									 >>$@ ;\
+	sed 's/^/    /' $(lastword $^)                                   >>$@ ;\
+	printf ']\n'                                                     >>$@ ;
+
+$(out)/RW/compile_commands.json: override BLD:=RW
+$(out)/RW/compile_commands.json: private objs := $(rw-objs:.o=.json)
+$(out)/RW/compile_commands.json: $(rw-objs:.o=.compile_cmd.json)
+	$(call quiet,combine_compile_cmd_json,COMBINE)
+$(out)/RO/compile_commands.json: override BLD:=RO
+$(out)/RO/compile_commands.json: private objs := $(ro-objs:.o=.json)
+$(out)/RO/compile_commands.json: $(ro-objs:.o=.compile_cmd.json)
+	$(call quiet,combine_compile_cmd_json,COMBINE)
+
+cmd_c_to_compile_cmd_json =                                                    \
+	printf '{\n'                                                     >$@  ;\
+	printf '    "arguments": [\n'                                   >>$@  ;\
+	printf '        "%s",\n' cc -c -std=gnu11 $(C_WARN) $(ide_cflags)      \
+		-o $(@D)/$(@F:.compile_cmd.json=.o)                     >>$@  ;\
+	printf '        "$<"\n'                                         >>$@  ;\
+	printf '    ],\n'                                               >>$@  ;\
+	printf '    "directory": "$(ide_ec_path)",\n'                   >>$@  ;\
+	printf '    "file": "$<"\n'                                     >>$@  ;\
+	printf '}\n'                                                    >>$@  ;
+
+$(out)/RO/%.compile_cmd.json:%.c
+	$(call quiet,c_to_compile_cmd_json,JSON   )
+$(out)/RW/%.compile_cmd.json:%.c
+	$(call quiet,c_to_compile_cmd_json,JSON   )
+
+$(out)/RO/%.compile_cmd.json:%.S
+	$(call quiet,c_to_compile_cmd_json,JSON   )
+$(out)/RW/%.compile_cmd.json:%.S
+	$(call quiet,c_to_compile_cmd_json,JSON   )
diff --git a/Makefile.rules b/Makefile.rules
index 3d79a5a65f..81be7812f8 100644
--- a/Makefile.rules
+++ b/Makefile.rules
@@ -1,6 +1,6 @@
 # -*- makefile -*-
 # vim: set filetype=make :
-# Copyright 2012 The Chromium OS Authors. All rights reserved.
+# Copyright 2012 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -101,7 +101,7 @@ cmd_run_fuzz = build/host/$*/$*.exe -seed=1 -runs=1 $(silent) \
 cmd_exe = $(CC) $(ro-objs) $(HOST_TEST_LDFLAGS) $(LDFLAGS_EXTRA) -o $@
 cmd_c_to_o = $(CC) -std=gnu11 $(C_WARN) $(CFLAGS) -MMD -MP -MF $@.d -c $< \
 		-MT $(@D)/$(@F) -o $(@D)/$(@F)
-cmd_cxx_to_o = $(CXX) -std=c++11 $(CFLAGS) $(CXXFLAGS) -MMD -MP -MF $@.d -c $< \
+cmd_cxx_to_o = $(CXX) -std=gnu++17 $(CFLAGS) $(CXXFLAGS) -MMD -MP -MF $@.d -c $< \
 		      -MT $(@D)/$(@F) -o $(@D)/$(@F)
 cmd_c_to_build = $(BUILDCC) $(BUILD_CFLAGS) \
 	         $(sort $(foreach c,$($(*F)-objs),util/$(c:%.o=%.c)) $(wildcard $*.c)) \
@@ -116,7 +116,7 @@ cmd_cxx_to_host = $(HOSTCXX) -std=gnu++17 $(HOST_CXXFLAGS) \
 		$(sort $(foreach c,$($(*F)-objs),util/$(c:%.o=%.cc)) $(wildcard $*.cc)) $(HOST_LDFLAGS)
 cmd_o_to_a = $(AR) rcs $@ $^
 cmd_host_test = $(MAKE) BOARD=host PROJECT=$* \
-	V=$(V) out=build/host/$* TEST_BUILD=y EMU_BUILD=y CROSS_COMPILE= \
+	V=$(V) out=build/host/$* TEST_BUILD=y EMU_BUILD=y \
 	$(if $(TEST_SCRIPT),TEST_SCRIPT=$(TEST_SCRIPT)) $(TEST_FLAG) \
 	build/host/$*/$*.exe
 cmd_coverage_test = $(subst build/host,build/coverage,$(cmd_host_test))
@@ -233,6 +233,11 @@ print-boards:
 	$(call cmd_pretty_print_list,\
 		$(sort $(boards)))
 
+# The zephyr path can be overridden on invocation, as in the following example:
+# $ make ZEPHYR_BASE=~/zephyr/main BOARD=dartmonkey
+ZEPHYR_BASE ?= $(abspath ../../../src/third_party/zephyr/main)
+export ZEPHYR_BASE
+
 ifeq ($(ALLOW_CONFIG),)
 
 # These are options defined by both ECOS and Zephyr. We need to tolerate this
@@ -243,12 +248,14 @@ ifeq ($(ALLOW_CONFIG),)
 # Zephyr upstream happens to add the same option, since we are requiring new
 # ECOS options to have a corresponding Kconfig anyway.
 conflicting_options := \
+	ADC \
 	AUDIO_CODEC \
 	DAC \
 	DMA \
 	EEPROM \
 	I2C_BITBANG \
 	INA219 \
+	MPU \
 	PECI \
 	PS2 \
 	SPI \
@@ -256,7 +263,7 @@ conflicting_options := \
 
 cmd_check_allowed = ./util/kconfig_check.py -c ${config} \
 	 -a util/config_allowed.txt -p PLATFORM_EC_ -s zephyr/ \
-	 -I $(abspath ../../../src/third_party/zephyr/main) \
+	 -I "${ZEPHYR_BASE}" \
 	 $(foreach opt,$(conflicting_options),-i $(opt)) check
 else
 cmd_check_allowed = true
@@ -368,8 +375,7 @@ run-fuzz-test-targets=$(foreach t,$(fuzz-test-list-host),run-$(t))
 
 $(fuzz-test-targets): TEST_FLAG=TEST_FUZZ=y TEST_ASAN=$(TEST_ASAN) \
 	TEST_MSAN=$(TEST_MSAN) TEST_UBSAN=$(TEST_UBSAN) \
-	CROSS_COMPILE=$(shell echo $(HOSTCC) | grep -v ccache | \
-		sed -e 's/[^-]*$$//')
+	CROSS_COMPILE=$(HOST_CROSS_COMPILE)
 $(fuzz-test-targets): host-%: | $(FAILED_BOARDS_DIR)
 	@touch $(FAILED_BOARDS_DIR)/test-$*
 	+$(call quiet,host_test,BUILD  )
@@ -443,8 +449,6 @@ cmd_merge_cov=lcov --rc lcov_branch_coverage=1 -o build/coverage/lcov.info \
 	$(foreach info,$^,-a ${info})
 cmd_report_cov=genhtml --branch-coverage -q -o build/coverage/coverage_rpt -t \
 	       "EC Unittest "$(bldversion) -s $^
-cmd_strip_lcov=sed -i build/coverage/lcov.info \
-	-e 's/\/mnt\/host\/source\/src\/platform\/ec\///'
 
 # Unless V is set to 0 we always want the 'size:' target to report its output,
 # there is no point in generating a short form command trace when calculating
@@ -492,7 +496,6 @@ coverage: TEST_FLAG=TEST_COVERAGE=y
 coverage: $(cov-test-targets) $(cov-initial-targets)
 	$(call quiet,merge_cov,MERGE  )
 	$(call quiet,report_cov,REPORT )
-	$(call quiet,strip_lcov,STRIP  )
 test-coverage: TEST_FLAG=TEST_COVERAGE=y
 test-coverage: $(cov-test-targets)
 	$(call quiet,merge_cov,MERGE  )
@@ -826,6 +829,8 @@ help:
 	@echo "  V=1                  - Show make output"
 	@echo "  BOARD=               - Set the board name to build (Default is $(BOARD))"
 	@echo "  STATIC_VERSION=1     - Force a constant version string for reproducable builds"
+	@echo "  BUILDCC_PREFIX=      - Set the compiler prefix for the system doing "
+	@echo "     the build (defaults to 'x86_64-pc-linux-gnu-')."
 	@echo "  CROSS_COMPILE=       - Set the compiler for the board"
 	@echo "  CROSS_COMPILE_arch=  - Set the compiler for arch"
 	@echo "     The board picks its CROSS_COMPILE_arch if CROSS_COMPILE is not set."
@@ -941,6 +946,9 @@ build_cros_ec_commands: $(out_cros_ec_commands)
 $(out_cros_ec_commands): include/ec_commands.h util/make_linux_ec_commands_h.sh
 	util/make_linux_ec_commands_h.sh $< $@
 
+# Include IDE configurations targets.
+include Makefile.ide
+
 # Pull in special rules/targets for third_party software
 -include third_party/rules.mk
 
diff --git a/Makefile.toolchain b/Makefile.toolchain
index c2e952d43b..e26bf2c8a2 100644
--- a/Makefile.toolchain
+++ b/Makefile.toolchain
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2012 The Chromium OS Authors. All rights reserved.
+# Copyright 2012 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -23,8 +23,25 @@ ifneq ($(TEST_FUZZ)$(TEST_ASAN)$(TEST_MSAN)$(TEST_UBSAN),)
 CC=clang
 endif
 
+# When set to 1, use the subset of the C standard library implemented in EC
+# (the "builtin" directory).
+# When set to 0, link against the toolchain's implementation of the C standard
+# library.
+USE_BUILTIN_STDLIB:=1
+
+# Set the prefix for the compiler if specified (e.g., "x86_64-pc-linux-gnu-").
+ifeq ($(origin BUILDCC_PREFIX),undefined)
+# If building with Portage use the environment variable it provides.
+# https://wiki.gentoo.org/wiki/Embedded_Handbook/General/Introduction#Environment_variables
+ifneq ($(CBUILD),)
+BUILDCC_PREFIX:=$(CBUILD)-
+else
+BUILDCC_PREFIX:=x86_64-pc-linux-gnu-
+endif
+endif
+
 # Extract cc-name
-cc-name:=$(shell $(CC) -v 2>&1 | grep -q "clang version" && echo clang || echo gcc)
+cc-name:=$(shell $(BUILDCC_PREFIX)$(CC) -v 2>&1 | grep -q "clang version" && echo clang || echo gcc)
 
 # Assume we want to use same compiler for both C and C++
 ifeq ($(cc-name),gcc)
@@ -36,8 +53,14 @@ endif
 # Try not to assume too much about optional tools and prefixes
 CCACHE:=$(shell which ccache 2>/dev/null)
 ifeq ($(origin HOST_CROSS_COMPILE),undefined)
+# If building with Portage use the environment variable it provides.
+# https://wiki.gentoo.org/wiki/Embedded_Handbook/General/Introduction#Environment_variables
+ifneq ($(CHOST),)
+HOST_CROSS_COMPILE:=$(CHOST)-
+else
 HOST_CROSS_COMPILE:=$(if $(shell which x86_64-pc-linux-gnu-$(cc-name) 2>/dev/null),x86_64-pc-linux-gnu-,)
 endif
+endif
 
 AR=$(CROSS_COMPILE)ar
 CC=$(CCACHE) $(CROSS_COMPILE)$(cc-name)
@@ -49,13 +72,17 @@ OBJCOPY=$(CROSS_COMPILE)objcopy
 OBJDUMP=$(CROSS_COMPILE)objdump
 ADDR2LINE=$(CROSS_COMPILE)addr2line
 PKG_CONFIG?=pkg-config
-BUILDCC?=$(CCACHE) $(cc-name)
+BUILDCC?=$(CCACHE) $(BUILDCC_PREFIX)$(cc-name)
 HOSTCC?=$(CCACHE) $(HOST_CROSS_COMPILE)$(cc-name)
 HOSTCXX?=$(CCACHE) $(HOST_CROSS_COMPILE)clang++
 HOST_PKG_CONFIG?=$(HOST_CROSS_COMPILE)pkg-config
 PROTOC?=protoc
 GCOV=$(CROSS_COMPILE)gcov
+ifeq ($(cc-name),gcc)
+HOSTGCOV=$(HOST_CROSS_COMPILE)gcov
+else
 HOSTGCOV=$(CURDIR)/util/llvm-gcov.sh
+endif
 
 C_WARN = -Wstrict-prototypes -Wdeclaration-after-statement -Wno-pointer-sign
 COMMON_WARN = -Wall -Wundef -Werror-implicit-function-declaration \
@@ -89,7 +116,7 @@ CFLAGS_WARN = $(COMMON_WARN) $(C_WARN)
 CXXFLAGS_WARN = $(COMMON_WARN)
 CFLAGS_DEBUG= -g
 CFLAGS_DEBUG+=$(CFLAGS_DEBUG_CHIP)
-CFLAGS_INCLUDE=$(foreach i,$(includes),-I$(i) ) -I.
+CFLAGS_INCLUDE=$(foreach i,$(filter-out builtin, $(includes)),-I$(i) ) -I.
 CFLAGS_TEST=$(if $(TEST_BUILD),-DTEST_BUILD=$(EMPTY) \
                                -DTEST_TASKFILE=$(PROJECT).tasklist,) \
             $(if $(CTS_MODULE), $(CFLAGS_CTS)) \
@@ -98,7 +125,8 @@ CFLAGS_TEST=$(if $(TEST_BUILD),-DTEST_BUILD=$(EMPTY) \
             $(if $(TEST_ASAN),-fsanitize=address) \
             $(if $(TEST_MSAN),-fsanitize=memory) \
             $(if $(TEST_UBSAN),$(UBSAN_FLAGS)) \
-            $(if $(TEST_FUZZ),-fsanitize=fuzzer-no-link -DTEST_FUZZ=$(EMPTY))
+            $(if $(TEST_FUZZ),-fsanitize=fuzzer-no-link -fno-PIE \
+		-DTEST_FUZZ=$(EMPTY))
 CFLAGS_COVERAGE=$(if $(TEST_COVERAGE),--coverage \
 				      -DTEST_COVERAGE=$(EMPTY),)
 CFLAGS_HOSTTEST=$(if $(TEST_HOSTTEST),-DTEST_HOSTTEST=$(EMPTY),) -Iinclude/driver
@@ -123,8 +151,11 @@ HOST_CPPFLAGS=$(CFLAGS_DEFINE) $(CFLAGS_INCLUDE) $(CFLAGS_TEST) \
 	 $(EXTRA_CFLAGS) $(CFLAGS_COVERAGE) $(CFLAGS_HOSTTEST) $(LATE_CFLAGS_DEFINE) \
 	 -DSECTION_IS_$(BLD)=$(EMPTY) -DSECTION=$(BLD) $(CPPFLAGS_$(BLD))
 ifneq ($(BOARD),host)
+CPPFLAGS+=-fno-PIC
+ifeq ($(USE_BUILTIN_STDLIB), 1)
 CPPFLAGS+=-ffreestanding -fno-builtin -nostdinc -nostdlib
 CPPFLAGS+=-Ibuiltin/
+endif
 else
 CPPFLAGS+=-Og
 endif
@@ -132,11 +163,15 @@ CPPFLAGS+= -DCHROMIUM_EC=$(EMPTY)
 CFLAGS=$(CPPFLAGS) $(CFLAGS_CPU) $(CFLAGS_DEBUG) $(COMMON_WARN) $(CFLAGS_y)
 CFLAGS+= -ffunction-sections -fshort-wchar
 CFLAGS+= -fno-delete-null-pointer-checks
+CFLAGS+= -fno-PIC
 ifneq ($(cc-name),clang)
 CFLAGS+= -ffat-lto-objects
 CFLAGS+= -fconserve-stack
 endif
 CXXFLAGS+=-DPROTOBUF_INLINE_NOT_IN_HEADERS=0
+ifeq ($(USE_BUILTIN_STDLIB), 1)
+CPPFLAGS+=-DUSE_BUILTIN_STDLIB
+endif
 
 ifeq ($(LIBFTDI_NAME),)
 FTDIVERSION:=$(shell $(PKG_CONFIG) --modversion libftdi1 2>/dev/null)
@@ -171,16 +206,24 @@ HOST_CXXFLAGS=$(HOST_CFLAGS)
 ifneq (${SYSROOT},)
   LDFLAGS_EXTRA+=--sysroot=${SYSROOT}
 endif
-LDFLAGS=-nostdlib -g -Wl,-X -Wl,--gc-sections -Wl,--build-id=none \
+LDFLAGS=-g -no-pie -Wl,-X -Wl,--gc-sections -Wl,--build-id=none \
 	$(LDFLAGS_EXTRA) $(CFLAGS_CPU)
+ifeq ($(USE_BUILTIN_STDLIB), 1)
+LDFLAGS+=-nostdlib
+else
+LDFLAGS+=-lnosys
+endif
 MEMSIZE_FLAGS=
 ifeq ($(cc-name),gcc)
 MEMSIZE_FLAGS+=-Wl,--print-memory-usage
 endif
 BUILD_LDFLAGS=$(LIBFTDIUSB_LDLIBS)
 HOST_LDFLAGS=$(LIBFTDIUSB_LDLIBS)
+ifneq (${HOST_SYSROOT},)
+  HOST_LDFLAGS+=--sysroot=${HOST_SYSROOT}
+endif
 HOST_TEST_LDFLAGS=-Wl,-T core/host/host_exe.lds -lrt -pthread -rdynamic -lm\
-		  -fuse-ld=bfd \
+		  -fuse-ld=bfd -no-pie \
 		  $(if $(TEST_COVERAGE), --coverage,) \
 		  $(if $(TEST_ASAN), -fsanitize=address) \
 		  $(if $(TEST_MSAN), -fsanitize=memory) \
diff --git a/PRESUBMIT.cfg b/PRESUBMIT.cfg
index eac83bb0c5..3aabbe3bb3 100644
--- a/PRESUBMIT.cfg
+++ b/PRESUBMIT.cfg
@@ -1,4 +1,6 @@
 [Hook Overrides]
+black_check: true
+clang_format_check: true
 branch_check: true
 checkpatch_check: true
 kerneldoc_check: true
@@ -9,6 +11,7 @@ signoff_check: true
 tab_check: false
 
 [Hook Overrides Options]
+black_check: --include_regex=^util/chargen$
 checkpatch_check: --no-tree --ignore=MSLEEP,VOLATILE,SPDX_LICENSE_TAG
 kerneldoc_check: --include_regex=\bec_commands\.h$
 
@@ -28,5 +31,4 @@ presubmit_check = util/presubmit_check.sh
 config_option_check = util/config_option_check.py
 host_command_check = util/host_command_check.sh
 ec_commands_h = util/linux_ec_commands_h_check.sh
-zmake_preupload = zephyr/zmake/pre-upload.sh ${PRESUBMIT_FILES}
 migrated_files = util/migrated_files.sh ${PRESUBMIT_FILES}
diff --git a/README.md b/README.md
index 0a10859b93..80c131e7c9 100644
--- a/README.md
+++ b/README.md
@@ -179,7 +179,7 @@ cd ~/trunk/src/platform/ec
 make -j BOARD=<boardname>
 ```
 
-Where **<boardname>** is replaced by the name of the board you want to build an
+Where `<boardname>` is replaced by the name of the board you want to build an
 EC binary for. For example, the boardname for the Chromebook Pixel is “link”.
 The make command will generate an EC binary at `build/<boardname>/ec.bin`. The
 `-j` tells make to build multi-threaded which can be much faster on a multi-core
@@ -489,7 +489,7 @@ Other style notes:
     all contributions to the Chromium project:
 
     ```
-    /* Copyright <year> The Chromium OS Authors. All rights reserved.
+    /* Copyright <year> The ChromiumOS Authors
      * Use of this source code is governed by a BSD-style license that can be
      * found in the LICENSE file.
      */
@@ -677,18 +677,3 @@ cat /tmp/artifact_bundle_metadata
 cat /tmp/metrics_build
 ls -l /tmp/artifact_bundles/
 ```
-
-### firmware-ec-cov-cq
-```
-rm -rf /tmp/artifact_bundles-cov /tmp/artifact_bundle_metadata-cov \
-  ~/chromiumos/src/platform/ec/build
-./firmware_builder.py --metrics /tmp/metrics_build_cov --code-coverage build && \
-./firmware_builder.py --metrics /tmp/metrics_test_cov --code-coverage test && \
-./firmware_builder.py --metrics /tmp/metrics_bundle_cov --code-coverage \
-  --output-dir=/tmp/artifact_bundles-cov \
-  --metadata=/tmp/artifact_bundle_metadata-cov bundle && \
-echo PASSED
-cat /tmp/artifact_bundle_metadata-cov
-ls -l /tmp/artifact_bundles-cov
-```
-
diff --git a/baseboard/asurada/baseboard.c b/baseboard/asurada/baseboard.c
index 1a86950281..3a881c275a 100644
--- a/baseboard/asurada/baseboard.c
+++ b/baseboard/asurada/baseboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -71,34 +71,26 @@ int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "bat_chg",
-		.port = IT83XX_I2C_CH_A,
-		.kbps = 100,
-		.scl  = GPIO_I2C_A_SCL,
-		.sda  = GPIO_I2C_A_SDA
-	},
-	{
-		.name = "sensor",
-		.port = IT83XX_I2C_CH_B,
-		.kbps = 400,
-		.scl = GPIO_I2C_B_SCL,
-		.sda = GPIO_I2C_B_SDA
-	},
-	{
-		.name = "usb0",
-		.port = IT83XX_I2C_CH_C,
-		.kbps = 400,
-		.scl = GPIO_I2C_C_SCL,
-		.sda = GPIO_I2C_C_SDA
-	},
-	{
-		.name = "usb1",
-		.port = IT83XX_I2C_CH_E,
-		.kbps = 400,
-		.scl = GPIO_I2C_E_SCL,
-		.sda = GPIO_I2C_E_SDA
-	},
+	{ .name = "bat_chg",
+	  .port = IT83XX_I2C_CH_A,
+	  .kbps = 100,
+	  .scl = GPIO_I2C_A_SCL,
+	  .sda = GPIO_I2C_A_SDA },
+	{ .name = "sensor",
+	  .port = IT83XX_I2C_CH_B,
+	  .kbps = 400,
+	  .scl = GPIO_I2C_B_SCL,
+	  .sda = GPIO_I2C_B_SDA },
+	{ .name = "usb0",
+	  .port = IT83XX_I2C_CH_C,
+	  .kbps = 400,
+	  .scl = GPIO_I2C_C_SCL,
+	  .sda = GPIO_I2C_C_SDA },
+	{ .name = "usb1",
+	  .port = IT83XX_I2C_CH_E,
+	  .kbps = 400,
+	  .scl = GPIO_I2C_E_SCL,
+	  .sda = GPIO_I2C_E_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -111,15 +103,19 @@ const struct cc_para_t *board_get_cc_tuning_parameter(enum usbpd_port port)
 {
 	const static struct cc_para_t
 		cc_parameter[CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT] = {
-		{
-			.rising_time = IT83XX_TX_PRE_DRIVING_TIME_1_UNIT,
-			.falling_time = IT83XX_TX_PRE_DRIVING_TIME_2_UNIT,
-		},
-		{
-			.rising_time = IT83XX_TX_PRE_DRIVING_TIME_1_UNIT,
-			.falling_time = IT83XX_TX_PRE_DRIVING_TIME_2_UNIT,
-		},
-	};
+			{
+				.rising_time =
+					IT83XX_TX_PRE_DRIVING_TIME_1_UNIT,
+				.falling_time =
+					IT83XX_TX_PRE_DRIVING_TIME_2_UNIT,
+			},
+			{
+				.rising_time =
+					IT83XX_TX_PRE_DRIVING_TIME_1_UNIT,
+				.falling_time =
+					IT83XX_TX_PRE_DRIVING_TIME_2_UNIT,
+			},
+		};
 
 	return &cc_parameter[port];
 }
diff --git a/baseboard/asurada/baseboard.h b/baseboard/asurada/baseboard.h
index 21a29cf942..62f74e1f57 100644
--- a/baseboard/asurada/baseboard.h
+++ b/baseboard/asurada/baseboard.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -83,10 +83,10 @@
 #define CONFIG_I2C_VIRTUAL_BATTERY
 #define I2C_PORT_CHARGER IT83XX_I2C_CH_A
 #define I2C_PORT_BATTERY IT83XX_I2C_CH_A
-#define I2C_PORT_POWER   IT83XX_I2C_CH_A
+#define I2C_PORT_POWER IT83XX_I2C_CH_A
 #define I2C_PORT_ACCEL IT83XX_I2C_CH_B
-#define I2C_PORT_PPC0  IT83XX_I2C_CH_C
-#define I2C_PORT_PPC1  IT83XX_I2C_CH_E
+#define I2C_PORT_PPC0 IT83XX_I2C_CH_C
+#define I2C_PORT_PPC1 IT83XX_I2C_CH_E
 #define I2C_PORT_USB_MUX0 IT83XX_I2C_CH_C
 #define I2C_PORT_USB_MUX1 IT83XX_I2C_CH_E
 #define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
@@ -171,13 +171,12 @@
 	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \
 	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |        \
 	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT) |     \
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |     \
 	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
 
 /* And the MKBP events */
 #define CONFIG_MKBP_EVENT_WAKEUP_MASK \
-		(BIT(EC_MKBP_EVENT_KEY_MATRIX) | \
-		 BIT(EC_MKBP_EVENT_HOST_EVENT))
+	(BIT(EC_MKBP_EVENT_KEY_MATRIX) | BIT(EC_MKBP_EVENT_HOST_EVENT))
 
 #include "baseboard_common.h"
 
diff --git a/baseboard/asurada/baseboard_common.h b/baseboard/asurada/baseboard_common.h
index 0245ae42bf..4b8892e5b7 100644
--- a/baseboard/asurada/baseboard_common.h
+++ b/baseboard/asurada/baseboard_common.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,12 +9,12 @@
 #define __CROS_EC_BASEBOARD_COMMON_H
 
 /* GPIO name remapping */
-#define GPIO_EN_HDMI_PWR        GPIO_EC_X_GPIO1
-#define GPIO_USB_C1_FRS_EN      GPIO_EC_X_GPIO1
+#define GPIO_EN_HDMI_PWR GPIO_EC_X_GPIO1
+#define GPIO_USB_C1_FRS_EN GPIO_EC_X_GPIO1
 #define GPIO_USB_C1_PPC_INT_ODL GPIO_X_EC_GPIO2
-#define GPIO_PS185_EC_DP_HPD    GPIO_X_EC_GPIO2
-#define GPIO_USB_C1_DP_IN_HPD   GPIO_EC_X_GPIO3
-#define GPIO_PS185_PWRDN_ODL    GPIO_EC_X_GPIO3
+#define GPIO_PS185_EC_DP_HPD GPIO_X_EC_GPIO2
+#define GPIO_USB_C1_DP_IN_HPD GPIO_EC_X_GPIO3
+#define GPIO_PS185_PWRDN_ODL GPIO_EC_X_GPIO3
 
 #ifndef __ASSEMBLER__
 
diff --git a/baseboard/asurada/board_chipset.c b/baseboard/asurada/board_chipset.c
index 4d12fb0334..24754f597f 100644
--- a/baseboard/asurada/board_chipset.c
+++ b/baseboard/asurada/board_chipset.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/baseboard/asurada/board_id.c b/baseboard/asurada/board_id.c
index 642785034c..9a316d8d40 100644
--- a/baseboard/asurada/board_id.c
+++ b/baseboard/asurada/board_id.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -34,21 +34,8 @@
  * 14 |   47 |  680 | 3086.7
  */
 const static int voltage_map[] = {
-	136,
-	388,
-	584,
-	785,
-	993,
-	1220,
-	1432,
-	1650,
-	1875,
-	2084,
-	2273,
-	2461,
-	2672,
-	2888,
-	3086,
+	136,  388,  584,  785,	993,  1220, 1432, 1650,
+	1875, 2084, 2273, 2461, 2672, 2888, 3086,
 };
 
 const int threshold_mv = 100;
diff --git a/baseboard/asurada/build.mk b/baseboard/asurada/build.mk
index ce7b7272bd..ac4f1489d2 100644
--- a/baseboard/asurada/build.mk
+++ b/baseboard/asurada/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/baseboard/asurada/hibernate.c b/baseboard/asurada/hibernate.c
index b26bd44adc..60b191d3e6 100644
--- a/baseboard/asurada/hibernate.c
+++ b/baseboard/asurada/hibernate.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,8 +23,8 @@ __override void board_hibernate_late(void)
 	 */
 	if (board_get_version() <= 1) {
 		if (IS_ENABLED(BOARD_ASURADA) ||
-			(IS_ENABLED(CONFIG_ZEPHYR) &&
-			IS_ENABLED(CONFIG_BOARD_ASURADA)))
+		    (IS_ENABLED(CONFIG_ZEPHYR) &&
+		     IS_ENABLED(CONFIG_BOARD_ASURADA)))
 			return;
 	}
 
diff --git a/baseboard/asurada/it5205_sbu.c b/baseboard/asurada/it5205_sbu.c
index 9ee59a5cc3..fc2cefd208 100644
--- a/baseboard/asurada/it5205_sbu.c
+++ b/baseboard/asurada/it5205_sbu.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -12,8 +12,8 @@
 #include "timer.h"
 #include "usb_mux.h"
 
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USB, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args)
 
 #define OVP_RETRY_DELAY_US_MIN (100 * MSEC)
 
diff --git a/baseboard/asurada/it5205_sbu.h b/baseboard/asurada/it5205_sbu.h
index 8dc59520dd..2a17506cad 100644
--- a/baseboard/asurada/it5205_sbu.h
+++ b/baseboard/asurada/it5205_sbu.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/baseboard/asurada/regulator.c b/baseboard/asurada/regulator.c
index 35670bda82..e2731c8385 100644
--- a/baseboard/asurada/regulator.c
+++ b/baseboard/asurada/regulator.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,13 +7,12 @@
 #include "bc12/mt6360_public.h"
 
 /* SD Card */
-int board_regulator_get_info(uint32_t index, char *name,
-			     uint16_t *num_voltages, uint16_t *voltages_mv)
+int board_regulator_get_info(uint32_t index, char *name, uint16_t *num_voltages,
+			     uint16_t *voltages_mv)
 {
 	enum mt6360_regulator_id id = index;
 
-	return mt6360_regulator_get_info(id, name, num_voltages,
-					 voltages_mv);
+	return mt6360_regulator_get_info(id, name, num_voltages, voltages_mv);
 }
 
 int board_regulator_enable(uint32_t index, uint8_t enable)
diff --git a/baseboard/asurada/usb_pd_policy.c b/baseboard/asurada/usb_pd_policy.c
index 03993fcbbe..afec537330 100644
--- a/baseboard/asurada/usb_pd_policy.c
+++ b/baseboard/asurada/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,8 +19,8 @@
 #error Asurada reference must have at least one 3.0 A port
 #endif
 
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
 
 int svdm_get_hpd_gpio(int port)
 {
@@ -79,8 +79,7 @@ __override int svdm_dp_attention(int port, uint32_t *payload)
 	if (lvl)
 		gpio_set_level_verbose(CC_USBPD, GPIO_DP_AUX_PATH_SEL, port);
 
-	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
-	    (irq || lvl))
+	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && (irq || lvl))
 		/*
 		 * Wake up the AP.  IRQ or level high indicates a DP sink is now
 		 * present.
@@ -147,7 +146,7 @@ __override void svdm_exit_dp_mode(int port)
 	svdm_set_hpd_gpio(port, 0);
 #endif /* CONFIG_USB_PD_DP_HPD_GPIO */
 	usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-				 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 
 #ifdef USB_PD_PORT_TCPC_MST
 	if (port == USB_PD_PORT_TCPC_MST)
diff --git a/baseboard/asurada/usbc_config.c b/baseboard/asurada/usbc_config.c
index 89cb24ff12..0be43d343a 100644
--- a/baseboard/asurada/usbc_config.c
+++ b/baseboard/asurada/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -37,9 +37,9 @@
 #include "usb_pd_tcpm.h"
 #include "usbc_ppc.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
 const struct charger_config_t chg_chips[] = {
 	{
@@ -56,7 +56,7 @@ static void baseboard_init(void)
 	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
 	gpio_enable_interrupt(GPIO_AP_XHCI_INIT_DONE);
 }
-DECLARE_HOOK(HOOK_INIT, baseboard_init, HOOK_PRIO_DEFAULT-1);
+DECLARE_HOOK(HOOK_INIT, baseboard_init, HOOK_PRIO_DEFAULT - 1);
 
 /* Sub-board */
 
@@ -193,14 +193,14 @@ BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
 void usb_a0_interrupt(enum gpio_signal signal)
 {
 	enum usb_charge_mode mode = gpio_get_level(signal) ?
-		USB_CHARGE_MODE_ENABLED : USB_CHARGE_MODE_DISABLED;
+					    USB_CHARGE_MODE_ENABLED :
+					    USB_CHARGE_MODE_DISABLED;
 
 	for (int i = 0; i < USB_PORT_COUNT; i++)
 		usb_charge_set_mode(i, mode, USB_ALLOW_SUSPEND_CHARGE);
 }
 
-static int board_ps8743_mux_set(const struct usb_mux *me,
-				mux_state_t mux_state)
+static int board_ps8743_mux_set(const struct usb_mux *me, mux_state_t mux_state)
 {
 	int rv = EC_SUCCESS;
 	int reg = 0;
@@ -227,33 +227,45 @@ static int board_ps8743_mux_set(const struct usb_mux *me,
 	return ps8743_write(me, PS8743_REG_MODE, reg);
 }
 
-const struct usb_mux usbc0_virtual_mux = {
-	.usb_port = 0,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+const struct usb_mux_chain usbc0_virtual_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = 0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
 
-const struct usb_mux usbc1_virtual_mux = {
-	.usb_port = 1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+const struct usb_mux_chain usbc1_virtual_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = 1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX0,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.next_mux = &usbc0_virtual_mux,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX0,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+			},
+		.next = &usbc0_virtual_mux,
 	},
 	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_USB_MUX1,
-		.i2c_addr_flags = PS8743_I2C_ADDR0_FLAG,
-		.driver = &ps8743_usb_mux_driver,
-		.next_mux = &usbc1_virtual_mux,
-		.board_set = &board_ps8743_mux_set,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_USB_MUX1,
+				.i2c_addr_flags = PS8743_I2C_ADDR0_FLAG,
+				.driver = &ps8743_usb_mux_driver,
+				.board_set = &board_ps8743_mux_set,
+			},
+		.next = &usbc1_virtual_mux,
 	},
 };
 
@@ -297,8 +309,8 @@ void board_reset_pd_mcu(void)
 	 */
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	charge_set_input_current_limit(
 		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
@@ -422,9 +434,9 @@ int ppc_get_alert_status(int port)
 enum adc_channel board_get_vbus_adc(int port)
 {
 	if (port == 0)
-		return  ADC_VBUS_C0;
+		return ADC_VBUS_C0;
 	if (port == 1)
-		return  ADC_VBUS_C1;
+		return ADC_VBUS_C1;
 	CPRINTSUSB("Unknown vbus adc port id: %d", port);
 	return ADC_VBUS_C0;
 }
diff --git a/baseboard/brask/baseboard.c b/baseboard/brask/baseboard.c
index 2e60b565f8..5a96ba49ca 100644
--- a/baseboard/brask/baseboard.c
+++ b/baseboard/brask/baseboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,6 +9,5 @@
 #include "gpio_signal.h"
 
 /* Wake up pins */
-const enum gpio_signal hibernate_wake_pins[] = {
-};
+const enum gpio_signal hibernate_wake_pins[] = {};
 const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
diff --git a/baseboard/brask/baseboard.h b/baseboard/brask/baseboard.h
index 15a451473d..83a02bec2e 100644
--- a/baseboard/brask/baseboard.h
+++ b/baseboard/brask/baseboard.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,16 +11,16 @@
 /*
  * By default, enable all console messages excepted HC
  */
-#define CC_DEFAULT     (CC_ALL & ~(BIT(CC_HOSTCMD)))
+#define CC_DEFAULT (CC_ALL & ~(BIT(CC_HOSTCMD)))
 
 /* NPCX9 config */
-#define NPCX9_PWM1_SEL    1  /* GPIO C2 is used as PWM1. */
+#define NPCX9_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */
 /*
  * This defines which pads (GPIO10/11 or GPIO64/65) are connected to
  * the "UART1" (NPCX_UART_PORT0) controller when used for
  * CONSOLE_UART.
  */
-#define NPCX_UART_MODULE2	1 /* 1:GPIO64/65 for UART1 */
+#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 for UART1 */
 
 /* CrOS Board Info */
 #define CONFIG_CBI_EEPROM
@@ -42,9 +42,9 @@
 
 /* Host communication */
 #define CONFIG_HOST_INTERFACE_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S5
-#define CONFIG_HOSTCMD_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S5
+#define CONFIG_HOST_INTERFACE_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST
 
 /* LED */
 #define CONFIG_LED_COMMON
@@ -59,7 +59,7 @@
 /* Support Barrel Jack */
 #undef CONFIG_DEDICATED_CHARGE_PORT_COUNT
 #define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON		45000
+#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 45000
 
 /* Chipset config */
 #define CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540
@@ -86,8 +86,8 @@
 
 /* ADL has new low-power features that requires extra-wide virtual wire
  * pulses. The EDS specifies 100 microseconds. */
-#undef CONFIG_ESPI_DEFAULT_VW_WIDTH_US
-#define CONFIG_ESPI_DEFAULT_VW_WIDTH_US	100
+#undef CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US
+#define CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US 100
 
 /* Buttons */
 #define CONFIG_DEDICATED_RECOVERY_BUTTON
@@ -137,7 +137,7 @@
 #define CONFIG_USB_PD_TCPM_NCT38XX
 
 #define CONFIG_USB_PD_TCPM_MUX
-#define CONFIG_HOSTCMD_PD_CONTROL		/* Needed for TCPC FW update */
+#define CONFIG_HOSTCMD_PD_CONTROL /* Needed for TCPC FW update */
 #define CONFIG_CMD_USB_PD_PE
 
 /*
@@ -145,7 +145,7 @@
  * with non-PD chargers.  Override the default low-power mode exit delay.
  */
 #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
-#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE	(50*MSEC)
+#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (50 * MSEC)
 
 /* Enable USB3.2 DRD */
 #define CONFIG_USB_PD_USB32_DRD
diff --git a/baseboard/brask/baseboard_usbc_config.h b/baseboard/brask/baseboard_usbc_config.h
index 1b3d9e5d3f..8ebf4f9b6a 100644
--- a/baseboard/brask/baseboard_usbc_config.h
+++ b/baseboard/brask/baseboard_usbc_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/baseboard/brask/build.mk b/baseboard/brask/build.mk
index e29bcaf4ac..4b540d94ad 100644
--- a/baseboard/brask/build.mk
+++ b/baseboard/brask/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/baseboard/brask/cbi.c b/baseboard/brask/cbi.c
index 038a491f05..0dcfcca253 100644
--- a/baseboard/brask/cbi.c
+++ b/baseboard/brask/cbi.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,8 +10,8 @@
 #include "cros_board_info.h"
 #include "hooks.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
 static uint8_t board_id;
 
diff --git a/baseboard/brask/cbi.h b/baseboard/brask/cbi.h
index 5fa41feadd..219718763f 100644
--- a/baseboard/brask/cbi.h
+++ b/baseboard/brask/cbi.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/baseboard/brask/usb_pd_policy.c b/baseboard/brask/usb_pd_policy.c
index ddff378ae2..0503415a9d 100644
--- a/baseboard/brask/usb_pd_policy.c
+++ b/baseboard/brask/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,6 +15,7 @@
 #include "console.h"
 #include "ec_commands.h"
 #include "gpio.h"
+#include "timer.h"
 #include "usbc_ppc.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
@@ -24,8 +25,8 @@
 #include "usb_pd_vdo.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
@@ -80,54 +81,44 @@ int board_vbus_source_enabled(int port)
 	return ppc_is_sourcing_vbus(port);
 }
 
+#ifdef CONFIG_USB_PD_TBT_COMPAT_MODE
 /* ----------------- Vendor Defined Messages ------------------ */
 /* Responses specifically for the enablement of TBT mode in the role of UFP */
 
 #define OPOS_TBT 1
 
-static const union tbt_mode_resp_device vdo_tbt_modes[1] = {
-		{
-			.tbt_alt_mode = 0x0001,
-			.tbt_adapter = TBT_ADAPTER_TBT3,
-			.intel_spec_b0 = 0,
-			.vendor_spec_b0 = 0,
-			.vendor_spec_b1 = 0,
-		}
-};
-
-static const uint32_t vdo_idh = VDO_IDH(
-				1, /* Data caps as USB host     */
-				0, /* Not a USB device   */
-				IDH_PTYPE_PERIPH,
-				1, /* Supports alt modes */
-				USB_VID_GOOGLE);
-
-static const uint32_t vdo_idh_rev30 = VDO_IDH_REV30(
-				 1, /* Data caps as USB host     */
-				 0, /* Not a USB device   */
-				 IDH_PTYPE_PERIPH,
-				 1, /* Supports alt modes */
-				 IDH_PTYPE_DFP_HOST,
-				 USB_TYPEC_RECEPTACLE,
-				 USB_VID_GOOGLE);
-
-static const uint32_t vdo_product = VDO_PRODUCT(CONFIG_USB_PID,
-						CONFIG_USB_BCD_DEV);
+static const union tbt_mode_resp_device vdo_tbt_modes[1] = { {
+	.tbt_alt_mode = 0x0001,
+	.tbt_adapter = TBT_ADAPTER_TBT3,
+	.intel_spec_b0 = 0,
+	.vendor_spec_b0 = 0,
+	.vendor_spec_b1 = 0,
+} };
+
+static const uint32_t vdo_idh = VDO_IDH(1, /* Data caps as USB host     */
+					0, /* Not a USB device   */
+					IDH_PTYPE_PERIPH, 1, /* Supports alt
+								modes */
+					USB_VID_GOOGLE);
+
+static const uint32_t vdo_idh_rev30 =
+	VDO_IDH_REV30(1, /* Data caps as USB host     */
+		      0, /* Not a USB device   */
+		      IDH_PTYPE_PERIPH, 1, /* Supports alt modes */
+		      IDH_PTYPE_DFP_HOST, USB_TYPEC_RECEPTACLE, USB_VID_GOOGLE);
+
+static const uint32_t vdo_product =
+	VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV);
 
 /* TODO(b/168890624): add USB4 to capability once USB4 response implemented */
 static const uint32_t vdo_ufp1 = VDO_UFP1(
-				   (VDO_UFP1_CAPABILITY_USB20
-				   | VDO_UFP1_CAPABILITY_USB32),
-				   USB_TYPEC_RECEPTACLE,
-				   VDO_UFP1_ALT_MODE_TBT3,
-				   USB_R30_SS_U40_GEN3);
-
-static const uint32_t vdo_dfp = VDO_DFP(
-				 (VDO_DFP_HOST_CAPABILITY_USB20
-				 | VDO_DFP_HOST_CAPABILITY_USB32
-				 | VDO_DFP_HOST_CAPABILITY_USB4),
-				 USB_TYPEC_RECEPTACLE,
-				 1  /* Port 1 */);
+	(VDO_UFP1_CAPABILITY_USB20 | VDO_UFP1_CAPABILITY_USB32),
+	USB_TYPEC_RECEPTACLE, VDO_UFP1_ALT_MODE_TBT3, USB_R30_SS_U40_GEN3);
+
+static const uint32_t vdo_dfp =
+	VDO_DFP((VDO_DFP_HOST_CAPABILITY_USB20 | VDO_DFP_HOST_CAPABILITY_USB32 |
+		 VDO_DFP_HOST_CAPABILITY_USB4),
+		USB_TYPEC_RECEPTACLE, 1 /* Port 1 */);
 
 static int svdm_tbt_compat_response_identity(int port, uint32_t *payload)
 {
@@ -166,8 +157,24 @@ static int svdm_tbt_compat_response_modes(int port, uint32_t *payload)
 	}
 }
 
-static int svdm_tbt_compat_response_enter_mode(
-	int port, uint32_t *payload)
+/* Track whether we've been enabled to ACK TBT EnterModes requests */
+static bool tbt_ufp_ack_allowed[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+__override enum ec_status
+board_set_tbt_ufp_reply(int port, enum typec_tbt_ufp_reply reply)
+{
+	/* Note: Host command has already bounds-checked port */
+	if (reply == TYPEC_TBT_UFP_REPLY_ACK)
+		tbt_ufp_ack_allowed[port] = true;
+	else if (reply == TYPEC_TBT_UFP_REPLY_NAK)
+		tbt_ufp_ack_allowed[port] = false;
+	else
+		return EC_RES_INVALID_PARAM;
+
+	return EC_RES_SUCCESS;
+}
+
+static int svdm_tbt_compat_response_enter_mode(int port, uint32_t *payload)
 {
 	mux_state_t mux_state = 0;
 
@@ -175,20 +182,34 @@ static int svdm_tbt_compat_response_enter_mode(
 	if (chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF))
 		return 0; /* NAK */
 
+	/* Do not enter mode while policy disallows it */
+	if (!tbt_ufp_ack_allowed[port])
+		return 0; /* NAK */
+
 	if ((PD_VDO_VID(payload[0]) != USB_VID_INTEL) ||
-		(PD_VDO_OPOS(payload[0]) != OPOS_TBT))
+	    (PD_VDO_OPOS(payload[0]) != OPOS_TBT))
 		return 0; /* NAK */
 
 	mux_state = usb_mux_get(port);
 	/*
 	 * Ref: USB PD 3.0 Spec figure 6-21 Successful Enter Mode sequence
-	 * UFP (responder) should be in USB mode or safe mode before sending
-	 * Enter Mode Command response.
+	 * UFP (responder) should be in USB mode or safe mode before entering a
+	 * Mode that requires the reconfiguring of any pins.
 	 */
 	if ((mux_state & USB_PD_MUX_USB_ENABLED) ||
-		(mux_state & USB_PD_MUX_SAFE_MODE)) {
+	    (mux_state & USB_PD_MUX_SAFE_MODE)) {
 		pd_ufp_set_enter_mode(port, payload);
 		set_tbt_compat_mode_ready(port);
+
+		/*
+		 * Ref: Above figure 6-21: UFP (responder) should be in the new
+		 * mode before sending the ACK.  However, our mux set sequence
+		 * may exceed tVDMEnterMode, so wait as long as we can
+		 * before sending the reply without violating that timer.
+		 */
+		if (!usb_mux_set_completed(port))
+			usleep(PD_T_VDM_E_MODE / 2);
+
 		CPRINTS("UFP Enter TBT mode");
 		return 1; /* ACK */
 	}
@@ -205,3 +226,4 @@ const struct svdm_response svdm_rsp = {
 	.amode = NULL,
 	.exit_mode = NULL,
 };
+#endif /* CONFIG_USB_PD_TBT_COMPAT_MODE */
diff --git a/baseboard/brya/baseboard.c b/baseboard/brya/baseboard.c
index 7b9e3c2e00..e65a384578 100644
--- a/baseboard/brya/baseboard.c
+++ b/baseboard/brya/baseboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -41,5 +41,5 @@ __override void lid_angle_peripheral_enable(int enable)
 		 */
 		if (!chipset_in_state(CHIPSET_STATE_ON))
 			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
-		}
+	}
 }
diff --git a/baseboard/brya/baseboard.h b/baseboard/brya/baseboard.h
index bc44a9d642..84fefa9b53 100644
--- a/baseboard/brya/baseboard.h
+++ b/baseboard/brya/baseboard.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,18 +12,18 @@
  * By default, enable all console messages excepted HC, ACPI and event:
  * The sensor stack is generating a lot of activity.
  */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
 #undef CONFIG_HOSTCMD_DEBUG_MODE
 #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
 
 /* NPCX9 config */
-#define NPCX9_PWM1_SEL    1  /* GPIO C2 is used as PWM1. */
+#define NPCX9_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */
 /*
  * This defines which pads (GPIO10/11 or GPIO64/65) are connected to
  * the "UART1" (NPCX_UART_PORT0) controller when used for
  * CONSOLE_UART.
  */
-#define NPCX_UART_MODULE2	1 /* 1:GPIO64/65 for UART1 */
+#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 for UART1 */
 
 /* EC Defines */
 #define CONFIG_LTO
@@ -46,8 +46,8 @@
 
 /* Host communication */
 #define CONFIG_HOST_INTERFACE_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S5
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S5
 
 /*
  * TODO(b/179648721): implement sensors
@@ -68,7 +68,7 @@
 #define CONFIG_CHARGE_MANAGER
 #define CONFIG_CHARGER
 #define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT		512
+#define CONFIG_CHARGER_INPUT_CURRENT 512
 
 #define CONFIG_CMD_CHARGER_DUMP
 
@@ -79,8 +79,8 @@
  * Don't allow the system to boot to S0 when the battery is low and unable to
  * communicate on locked systems (which haven't PD negotiated)
  */
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT	15000
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON		15001
+#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT 15000
+#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 15001
 
 /* Common battery defines */
 #define CONFIG_BATTERY_SMART
@@ -113,7 +113,7 @@
 #define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
 #define CONFIG_LOW_POWER_IDLE
 
-#define CONFIG_HOSTCMD_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST
+#define CONFIG_HOST_INTERFACE_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST
 
 #define CONFIG_BOARD_HAS_RTC_RESET
 #undef CONFIG_S5_EXIT_WAIT
@@ -124,8 +124,8 @@
 
 /* ADL has new lower-power features that require extra-wide virtual wire
  * pulses. The EDS specifies 100 microseconds. */
-#undef CONFIG_ESPI_DEFAULT_VW_WIDTH_US
-#define CONFIG_ESPI_DEFAULT_VW_WIDTH_US 100
+#undef CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US
+#define CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US 100
 
 /* Buttons / Switches */
 #define CONFIG_VOLUME_BUTTONS
@@ -181,7 +181,7 @@
 #define CONFIG_USB_PD_TCPM_NCT38XX
 
 #define CONFIG_USB_PD_TCPM_MUX
-#define CONFIG_HOSTCMD_PD_CONTROL		/* Needed for TCPC FW update */
+#define CONFIG_HOSTCMD_PD_CONTROL /* Needed for TCPC FW update */
 #define CONFIG_CMD_USB_PD_PE
 
 /*
@@ -189,7 +189,7 @@
  * with non-PD chargers.  Override the default low-power mode exit delay.
  */
 #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
-#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE	(50*MSEC)
+#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (50 * MSEC)
 
 /* Enable USB3.2 DRD */
 #define CONFIG_USB_PD_USB32_DRD
@@ -230,13 +230,13 @@
  * bytes. Task stack sizes not listed here use more generic values (see
  * ec.tasklist).
  */
-#define BASEBOARD_CHARGER_TASK_STACK_SIZE	1088
-#define BASEBOARD_CHG_RAMP_TASK_STACK_SIZE	1088
-#define BASEBOARD_CHIPSET_TASK_STACK_SIZE	1152
-#define BASEBOARD_PD_INT_TASK_STACK_SIZE	 800
-#define BASEBOARD_PD_TASK_STACK_SIZE		1216
-#define BASEBOARD_POWERBTN_TASK_STACK_SIZE	1088
-#define BASEBOARD_RGBKBD_TASK_STACK_SIZE	2048
+#define BASEBOARD_CHARGER_TASK_STACK_SIZE 1088
+#define BASEBOARD_CHG_RAMP_TASK_STACK_SIZE 1088
+#define BASEBOARD_CHIPSET_TASK_STACK_SIZE 1152
+#define BASEBOARD_PD_INT_TASK_STACK_SIZE 800
+#define BASEBOARD_PD_TASK_STACK_SIZE 1216
+#define BASEBOARD_POWERBTN_TASK_STACK_SIZE 1088
+#define BASEBOARD_RGBKBD_TASK_STACK_SIZE 2048
 
 #ifndef __ASSEMBLER__
 
@@ -248,7 +248,6 @@
 #include "baseboard_usbc_config.h"
 #include "extpower.h"
 
-
 /*
  * Check battery disconnect state.
  * This function will return if battery is initialized or not.
diff --git a/baseboard/brya/baseboard_usbc_config.h b/baseboard/brya/baseboard_usbc_config.h
index f8b9fab35c..6d0cf828a3 100644
--- a/baseboard/brya/baseboard_usbc_config.h
+++ b/baseboard/brya/baseboard_usbc_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/baseboard/brya/battery_presence.c b/baseboard/brya/battery_presence.c
index 94c9926820..1e4ab4ed44 100644
--- a/baseboard/brya/battery_presence.c
+++ b/baseboard/brya/battery_presence.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -18,8 +18,9 @@ __overridable bool board_battery_is_initialized(void)
 {
 	int batt_status;
 
-	return battery_status(&batt_status) != EC_SUCCESS ? false :
-		!!(batt_status & STATUS_INITIALIZED);
+	return battery_status(&batt_status) != EC_SUCCESS ?
+		       false :
+		       !!(batt_status & STATUS_INITIALIZED);
 }
 
 /*
diff --git a/baseboard/brya/build.mk b/baseboard/brya/build.mk
index 2ed0186242..c6e93c63f2 100644
--- a/baseboard/brya/build.mk
+++ b/baseboard/brya/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/baseboard/brya/cbi.c b/baseboard/brya/cbi.c
index ded310bffc..7bc8dad117 100644
--- a/baseboard/brya/cbi.c
+++ b/baseboard/brya/cbi.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,8 +10,8 @@
 #include "cros_board_info.h"
 #include "hooks.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
 static uint8_t board_id;
 
diff --git a/baseboard/brya/cbi.h b/baseboard/brya/cbi.h
index 2ad70aff96..37e02806bd 100644
--- a/baseboard/brya/cbi.h
+++ b/baseboard/brya/cbi.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/baseboard/brya/charger_bq25720.c b/baseboard/brya/charger_bq25720.c
index 184cc68eaa..a4fa209246 100644
--- a/baseboard/brya/charger_bq25720.c
+++ b/baseboard/brya/charger_bq25720.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,9 +15,8 @@
 #include "usb_pd.h"
 #include "util.h"
 
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 #ifndef CONFIG_ZEPHYR
 /* Charger Chip Configuration */
@@ -86,7 +85,6 @@ int board_set_active_charge_port(int port)
 __overridable void board_set_charge_limit(int port, int supplier, int charge_ma,
 					  int max_ma, int charge_mv)
 {
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
diff --git a/baseboard/brya/prochot.c b/baseboard/brya/prochot.c
index 666f2ca35b..f89ec5a263 100644
--- a/baseboard/brya/prochot.c
+++ b/baseboard/brya/prochot.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,10 +16,10 @@
 #include "task.h"
 
 /* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
-#define ADT_RATING_W  (PD_MAX_POWER_MW / 1000)
-#define PROCHOT_EVENT_200MS_TICK    TASK_EVENT_CUSTOM_BIT(0)
+#define ADT_RATING_W (PD_MAX_POWER_MW / 1000)
+#define PROCHOT_EVENT_200MS_TICK TASK_EVENT_CUSTOM_BIT(0)
 
 struct batt_para {
 	int battery_continuous_discharge_mw;
@@ -80,8 +80,9 @@ static int get_batt_parameter(void)
 
 	rv |= sb_read(SB_DESIGN_VOLTAGE, &battery_design_voltage_mv);
 	rv |= sb_read(SB_DESIGN_CAPACITY, &battery_design_capacity_mAh);
-	batt_params.battery_design_mWh = (battery_design_voltage_mv *
-		battery_design_capacity_mAh) / 1000;
+	batt_params.battery_design_mWh =
+		(battery_design_voltage_mv * battery_design_capacity_mAh) /
+		1000;
 
 	if (sb_read(SB_RELATIVE_STATE_OF_CHARGE, &batt_params.state_of_charge))
 		batt_params.flags |= BATT_FLAG_BAD_STATE_OF_CHARGE;
@@ -109,7 +110,7 @@ static int set_register_charge_option(void)
 	int rv;
 
 	rv = i2c_read16(I2C_PORT_CHARGER, BQ25710_SMBUS_ADDR1_FLAGS,
-		    BQ25710_REG_CHARGE_OPTION_0, &reg);
+			BQ25710_REG_CHARGE_OPTION_0, &reg);
 	if (rv == EC_SUCCESS) {
 		reg = SET_BQ_FIELD(BQ257X0, CHARGE_OPTION_0, IADP_GAIN, 1, reg);
 		/* if AC only, disable IDPM,
@@ -127,7 +128,7 @@ static int set_register_charge_option(void)
 	}
 
 	return i2c_write16(I2C_PORT_CHARGER, BQ25710_SMBUS_ADDR1_FLAGS,
-				BQ25710_REG_CHARGE_OPTION_0, reg);
+			   BQ25710_REG_CHARGE_OPTION_0, reg);
 }
 
 static void assert_prochot(void)
@@ -154,7 +155,7 @@ static void assert_prochot(void)
 	/* When battery is discharging, the battery current will be negative */
 	if (batt_params.battery_continuous_discharge_mw < 0) {
 		total_W = adpt_mw +
-			ABS(batt_params.battery_continuous_discharge_mw);
+			  ABS(batt_params.battery_continuous_discharge_mw);
 	} else {
 		/* we won't assert prochot when battery is charging. */
 		total_W = adpt_mw;
@@ -177,15 +178,18 @@ static void assert_prochot(void)
 		if (!battery_hw_present()) {
 			gpio_set_level(GPIO_EC_PROCHOT_ODL, 1);
 		} else {
-			batt_params.battery_continuous_discharge_mw =
-			ABS(batt_params.battery_continuous_discharge_mw);
+			batt_params.battery_continuous_discharge_mw = ABS(
+				batt_params.battery_continuous_discharge_mw);
 			if ((batt_params.battery_continuous_discharge_mw /
-			 1000) > BATT_MAX_CONTINUE_DISCHARGE_WATT *
-			 PROCHOT_ASSERTION_BATTERY_RATIO / 100)
+			     1000) > BATT_MAX_CONTINUE_DISCHARGE_WATT *
+					     PROCHOT_ASSERTION_BATTERY_RATIO /
+					     100)
 				gpio_set_level(GPIO_EC_PROCHOT_ODL, 0);
-			else if ((batt_params.battery_continuous_discharge_mw
-			 / 1000) < BATT_MAX_CONTINUE_DISCHARGE_WATT *
-			 PROCHOT_DEASSERTION_BATTERY_RATIO / 100)
+			else if ((batt_params.battery_continuous_discharge_mw /
+				  1000) <
+				 BATT_MAX_CONTINUE_DISCHARGE_WATT *
+					 PROCHOT_DEASSERTION_BATTERY_RATIO /
+					 100)
 				gpio_set_level(GPIO_EC_PROCHOT_ODL, 1);
 		}
 		return;
@@ -195,42 +199,48 @@ static void assert_prochot(void)
 		/* if adapter >= 60W */
 		/* if no battery or battery < 10% */
 		if (!battery_hw_present() ||
-		batt_params.state_of_charge <= 10) {
-			if (total_W > ADT_RATING_W *
-			PROCHOT_ASSERTION_PD_RATIO / 100)
+		    batt_params.state_of_charge <= 10) {
+			if (total_W >
+			    ADT_RATING_W * PROCHOT_ASSERTION_PD_RATIO / 100)
 				gpio_set_level(GPIO_EC_PROCHOT_ODL, 0);
-			else if (total_W <= ADT_RATING_W *
-			PROCHOT_DEASSERTION_PD_RATIO / 100)
+			else if (total_W <=
+				 ADT_RATING_W * PROCHOT_DEASSERTION_PD_RATIO /
+					 100)
 				gpio_set_level(GPIO_EC_PROCHOT_ODL, 1);
 		} else {
 			/* AC + battery */
-			if (total_W > (ADT_RATING_W +
-			BATT_MAX_CONTINUE_DISCHARGE_WATT))
+			if (total_W >
+			    (ADT_RATING_W + BATT_MAX_CONTINUE_DISCHARGE_WATT))
 				gpio_set_level(GPIO_EC_PROCHOT_ODL, 0);
-			else if (total_W < (ADT_RATING_W +
-			BATT_MAX_CONTINUE_DISCHARGE_WATT) *
-			PROCHOT_DEASSERTION_PD_BATTERY_RATIO / 100)
+			else if (total_W <
+				 (ADT_RATING_W +
+				  BATT_MAX_CONTINUE_DISCHARGE_WATT) *
+					 PROCHOT_DEASSERTION_PD_BATTERY_RATIO /
+					 100)
 				gpio_set_level(GPIO_EC_PROCHOT_ODL, 1);
 		}
 	} else {
 		/* if adapter < 60W */
 		/* if no battery or battery < 10% */
 		if (!battery_hw_present() ||
-		batt_params.state_of_charge <= 10) {
+		    batt_params.state_of_charge <= 10) {
 			if (total_W > (adapter_wattage *
-			PROCHOT_ASSERTION_ADAPTER_RATIO / 100))
+				       PROCHOT_ASSERTION_ADAPTER_RATIO / 100))
 				gpio_set_level(GPIO_EC_PROCHOT_ODL, 0);
-			else if (total_W <= (adapter_wattage *
-			PROCHOT_DEASSERTION_ADAPTER_RATIO / 100))
+			else if (total_W <=
+				 (adapter_wattage *
+				  PROCHOT_DEASSERTION_ADAPTER_RATIO / 100))
 				gpio_set_level(GPIO_EC_PROCHOT_ODL, 1);
 		} else {
 			/* AC + battery */
 			if (total_W > (adapter_wattage +
-				BATT_MAX_CONTINUE_DISCHARGE_WATT))
+				       BATT_MAX_CONTINUE_DISCHARGE_WATT))
 				gpio_set_level(GPIO_EC_PROCHOT_ODL, 0);
-			else if (total_W < (adapter_wattage +
-				(BATT_MAX_CONTINUE_DISCHARGE_WATT *
-				PROCHOT_DEASSERTION_ADAPTER_BATT_RATIO / 100)))
+			else if (total_W <
+				 (adapter_wattage +
+				  (BATT_MAX_CONTINUE_DISCHARGE_WATT *
+				   PROCHOT_DEASSERTION_ADAPTER_BATT_RATIO /
+				   100)))
 				gpio_set_level(GPIO_EC_PROCHOT_ODL, 1);
 		}
 	}
diff --git a/baseboard/brya/usb_pd_policy.c b/baseboard/brya/usb_pd_policy.c
index e3e85539bf..e902fbc4a6 100644
--- a/baseboard/brya/usb_pd_policy.c
+++ b/baseboard/brya/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,8 +25,8 @@
 #include "usb_pd_vdo.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
@@ -81,80 +81,86 @@ int board_vbus_source_enabled(int port)
 	return ppc_is_sourcing_vbus(port);
 }
 
+#ifdef CONFIG_USB_PD_TBT_COMPAT_MODE
 /* ----------------- Vendor Defined Messages ------------------ */
 /* Responses specifically for the enablement of TBT mode in the role of UFP */
 
 #define OPOS_TBT 1
 
-static const union tbt_mode_resp_device vdo_tbt_modes[1] = {
-		{
-			.tbt_alt_mode = 0x0001,
-			.tbt_adapter = TBT_ADAPTER_TBT3,
-			.intel_spec_b0 = 0,
-			.vendor_spec_b0 = 0,
-			.vendor_spec_b1 = 0,
-		}
-};
-
-static const uint32_t vdo_idh = VDO_IDH(
-				1, /* Data caps as USB host     */
-				0, /* Not a USB device   */
-				IDH_PTYPE_PERIPH,
-				1, /* Supports alt modes */
-				USB_VID_GOOGLE);
-
-static const uint32_t vdo_idh_rev30 = VDO_IDH_REV30(
-				 1, /* Data caps as USB host     */
-				 0, /* Not a USB device   */
-				 IDH_PTYPE_PERIPH,
-				 1, /* Supports alt modes */
-				 IDH_PTYPE_DFP_HOST,
-				 USB_TYPEC_RECEPTACLE,
-				 USB_VID_GOOGLE);
-
-static const uint32_t vdo_product = VDO_PRODUCT(CONFIG_USB_PID,
-						CONFIG_USB_BCD_DEV);
+static const union tbt_mode_resp_device vdo_tbt_modes[1] = { {
+	.tbt_alt_mode = 0x0001,
+	.tbt_adapter = TBT_ADAPTER_TBT3,
+	.intel_spec_b0 = 0,
+	.vendor_spec_b0 = 0,
+	.vendor_spec_b1 = 0,
+} };
+
+static const uint32_t vdo_idh = VDO_IDH(1, /* Data caps as USB host     */
+					0, /* Not a USB device   */
+					IDH_PTYPE_PERIPH, 1, /* Supports alt
+								modes */
+					USB_VID_GOOGLE);
+
+static const uint32_t vdo_idh_rev30 =
+	VDO_IDH_REV30(1, /* Data caps as USB host     */
+		      0, /* Not a USB device   */
+		      IDH_PTYPE_PERIPH, 1, /* Supports alt modes */
+		      IDH_PTYPE_DFP_HOST, USB_TYPEC_RECEPTACLE, USB_VID_GOOGLE);
+
+static const uint32_t vdo_product =
+	VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV);
 
 /* TODO(b/168890624): add USB4 to capability once USB4 response implemented */
 static const uint32_t vdo_ufp1 = VDO_UFP1(
-				   (VDO_UFP1_CAPABILITY_USB20
-				   | VDO_UFP1_CAPABILITY_USB32),
-				   USB_TYPEC_RECEPTACLE,
-				   VDO_UFP1_ALT_MODE_TBT3,
-				   USB_R30_SS_U40_GEN3);
-
-static const uint32_t vdo_dfp = VDO_DFP(
-				 (VDO_DFP_HOST_CAPABILITY_USB20
-				 | VDO_DFP_HOST_CAPABILITY_USB32
-				 | VDO_DFP_HOST_CAPABILITY_USB4),
-				 USB_TYPEC_RECEPTACLE,
-				 1  /* Port 1 */);
+	(VDO_UFP1_CAPABILITY_USB20 | VDO_UFP1_CAPABILITY_USB32),
+	USB_TYPEC_RECEPTACLE, VDO_UFP1_ALT_MODE_TBT3, USB_R30_SS_U40_GEN3);
+
+static const uint32_t vdo_dfp =
+	VDO_DFP((VDO_DFP_HOST_CAPABILITY_USB20 | VDO_DFP_HOST_CAPABILITY_USB32 |
+		 VDO_DFP_HOST_CAPABILITY_USB4),
+		USB_TYPEC_RECEPTACLE, 1 /* Port 1 */);
 
 static int svdm_tbt_compat_response_identity(int port, uint32_t *payload)
 {
-	/* TODO(b/154962766): Get an XID */
-	payload[VDO_I(CSTAT)] = VDO_CSTAT(0);
-	payload[VDO_I(PRODUCT)] = vdo_product;
-
-	if (pd_get_rev(port, TCPCI_MSG_SOP) == PD_REV30) {
-		/* PD Revision 3.0 */
-		payload[VDO_I(IDH)] = vdo_idh_rev30;
-		payload[VDO_I(PTYPE_UFP1_VDO)] = vdo_ufp1;
-		/* TODO(b/181620145): Customize for brya */
-		payload[VDO_I(PTYPE_UFP2_VDO)] = 0;
-		payload[VDO_I(PTYPE_DFP_VDO)] = vdo_dfp;
-		return VDO_I(PTYPE_DFP_VDO) + 1;
-	}
+	/*
+	 * For PD 3.1 compliance test TEST.PD.VDM.SRC.2,
+	 * we should return NAK if we cannot recognized the incoming SVID.
+	 */
+	if (PD_VDO_VID(payload[0]) == USB_SID_PD) {
+		/* TODO(b/154962766): Get an XID */
+		payload[VDO_I(CSTAT)] = VDO_CSTAT(0);
+		payload[VDO_I(PRODUCT)] = vdo_product;
+
+		if (pd_get_rev(port, TCPCI_MSG_SOP) == PD_REV30) {
+			/* PD Revision 3.0 */
+			payload[VDO_I(IDH)] = vdo_idh_rev30;
+			payload[VDO_I(PTYPE_UFP1_VDO)] = vdo_ufp1;
+			/* TODO(b/181620145): Customize for brya */
+			payload[VDO_I(PTYPE_UFP2_VDO)] = 0;
+			payload[VDO_I(PTYPE_DFP_VDO)] = vdo_dfp;
+			return VDO_I(PTYPE_DFP_VDO) + 1;
+		}
 
-	/* PD Revision 2.0 */
-	payload[VDO_I(IDH)] = vdo_idh;
-	return VDO_I(PRODUCT) + 1;
+		/* PD Revision 2.0 */
+		payload[VDO_I(IDH)] = vdo_idh;
+		return VDO_I(PRODUCT) + 1;
+	} else {
+		return 0; /* NAK */
+	}
 }
 
 static int svdm_tbt_compat_response_svids(int port, uint32_t *payload)
 {
-	payload[1] = VDO_SVID(USB_VID_INTEL, 0);
-	return 2;
+	/*
+	 * For PD 3.1 compliance test TEST.PD.VDM.SRC.2,
+	 * we should return NAK if we cannot recognized the incoming SVID.
+	 */
+	if (PD_VDO_VID(payload[0]) == USB_SID_PD) {
+		payload[1] = VDO_SVID(USB_VID_INTEL, 0);
+		return 2;
+	} else {
+		return 0; /* NAK */
+	}
 }
 
 static int svdm_tbt_compat_response_modes(int port, uint32_t *payload)
@@ -170,8 +176,8 @@ static int svdm_tbt_compat_response_modes(int port, uint32_t *payload)
 /* Track whether we've been enabled to ACK TBT EnterModes requests */
 static bool tbt_ufp_ack_allowed[CONFIG_USB_PD_PORT_MAX_COUNT];
 
-__override enum ec_status board_set_tbt_ufp_reply(int port,
-						 enum typec_tbt_ufp_reply reply)
+__override enum ec_status
+board_set_tbt_ufp_reply(int port, enum typec_tbt_ufp_reply reply)
 {
 	/* Note: Host command has already bounds-checked port */
 	if (reply == TYPEC_TBT_UFP_REPLY_ACK)
@@ -184,8 +190,7 @@ __override enum ec_status board_set_tbt_ufp_reply(int port,
 	return EC_RES_SUCCESS;
 }
 
-static int svdm_tbt_compat_response_enter_mode(
-	int port, uint32_t *payload)
+static int svdm_tbt_compat_response_enter_mode(int port, uint32_t *payload)
 {
 	mux_state_t mux_state = 0;
 
@@ -198,7 +203,7 @@ static int svdm_tbt_compat_response_enter_mode(
 		return 0; /* NAK */
 
 	if ((PD_VDO_VID(payload[0]) != USB_VID_INTEL) ||
-		(PD_VDO_OPOS(payload[0]) != OPOS_TBT))
+	    (PD_VDO_OPOS(payload[0]) != OPOS_TBT))
 		return 0; /* NAK */
 
 	mux_state = usb_mux_get(port);
@@ -208,7 +213,7 @@ static int svdm_tbt_compat_response_enter_mode(
 	 * Mode that requires the reconfiguring of any pins.
 	 */
 	if ((mux_state & USB_PD_MUX_USB_ENABLED) ||
-		(mux_state & USB_PD_MUX_SAFE_MODE)) {
+	    (mux_state & USB_PD_MUX_SAFE_MODE)) {
 		pd_ufp_set_enter_mode(port, payload);
 		set_tbt_compat_mode_ready(port);
 
@@ -237,3 +242,4 @@ const struct svdm_response svdm_rsp = {
 	.amode = NULL,
 	.exit_mode = NULL,
 };
+#endif /* CONFIG_USB_PD_TBT_COMPAT_MODE */
diff --git a/baseboard/cherry/baseboard.c b/baseboard/cherry/baseboard.c
index 83c169c636..3f5f5c0e64 100644
--- a/baseboard/cherry/baseboard.c
+++ b/baseboard/cherry/baseboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -52,8 +52,8 @@ static void xhci_init_done_interrupt(enum gpio_signal signal);
 
 #include "gpio_list.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
 /* Wake-up pins for hibernate */
 enum gpio_signal hibernate_wake_pins[] = {
@@ -76,10 +76,10 @@ static void baseboard_charger_init(void)
 {
 	/* b/198707662#comment9 */
 	int reg = (4096 / ISL9238_INPUT_VOLTAGE_REF_STEP)
-			<< ISL9238_INPUT_VOLTAGE_REF_SHIFT;
+		  << ISL9238_INPUT_VOLTAGE_REF_SHIFT;
 
 	i2c_write16(I2C_PORT_CHARGER, ISL923X_ADDR_FLAGS,
-			ISL9238_REG_INPUT_VOLTAGE, reg);
+		    ISL9238_REG_INPUT_VOLTAGE, reg);
 }
 DECLARE_HOOK(HOOK_INIT, baseboard_charger_init, HOOK_PRIO_DEFAULT + 2);
 
@@ -113,14 +113,14 @@ void rt1718s_tcpc_interrupt(enum gpio_signal signal)
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
 	/* Convert to mV (3000mV/1024). */
-	{"VBUS", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0, CHIP_ADC_CH0},
-	{"BOARD_ID_0", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH1},
-	{"BOARD_ID_1", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH2},
+	{ "VBUS", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0, CHIP_ADC_CH0 },
+	{ "BOARD_ID_0", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH1 },
+	{ "BOARD_ID_1", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH2 },
 	/* AMON/BMON gain = 17.97 */
-	{"CHARGER_AMON_R", ADC_MAX_MVOLT * 1000 / 17.97, ADC_READ_MAX + 1, 0,
-	 CHIP_ADC_CH3},
-	{"CHARGER_PMON", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH6},
-	{"TEMP_SENSOR_CHG", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH7},
+	{ "CHARGER_AMON_R", ADC_MAX_MVOLT * 1000 / 17.97, ADC_READ_MAX + 1, 0,
+	  CHIP_ADC_CH3 },
+	{ "CHARGER_PMON", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH6 },
+	{ "TEMP_SENSOR_CHG", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH7 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
@@ -210,7 +210,8 @@ BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
 __maybe_unused void xhci_init_done_interrupt(enum gpio_signal signal)
 {
 	enum usb_charge_mode mode = gpio_get_level(signal) ?
-		USB_CHARGE_MODE_ENABLED : USB_CHARGE_MODE_DISABLED;
+					    USB_CHARGE_MODE_ENABLED :
+					    USB_CHARGE_MODE_DISABLED;
 
 	for (int i = 0; i < USB_PORT_COUNT; i++)
 		usb_charge_set_mode(i, mode, USB_ALLOW_SUSPEND_CHARGE);
@@ -246,34 +247,26 @@ __maybe_unused void xhci_init_done_interrupt(enum gpio_signal signal)
 
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "bat_chg",
-		.port = IT83XX_I2C_CH_A,
-		.kbps = 100,
-		.scl  = GPIO_I2C_A_SCL,
-		.sda  = GPIO_I2C_A_SDA
-	},
-	{
-		.name = "sensor",
-		.port = IT83XX_I2C_CH_B,
-		.kbps = 400,
-		.scl  = GPIO_I2C_B_SCL,
-		.sda  = GPIO_I2C_B_SDA
-	},
-	{
-		.name = "usb0",
-		.port = IT83XX_I2C_CH_C,
-		.kbps = 400,
-		.scl  = GPIO_I2C_C_SCL,
-		.sda  = GPIO_I2C_C_SDA
-	},
-	{
-		.name = "usb1",
-		.port = IT83XX_I2C_CH_E,
-		.kbps = 1000,
-		.scl  = GPIO_I2C_E_SCL,
-		.sda  = GPIO_I2C_E_SDA
-	},
+	{ .name = "bat_chg",
+	  .port = IT83XX_I2C_CH_A,
+	  .kbps = 100,
+	  .scl = GPIO_I2C_A_SCL,
+	  .sda = GPIO_I2C_A_SDA },
+	{ .name = "sensor",
+	  .port = IT83XX_I2C_CH_B,
+	  .kbps = 400,
+	  .scl = GPIO_I2C_B_SCL,
+	  .sda = GPIO_I2C_B_SDA },
+	{ .name = "usb0",
+	  .port = IT83XX_I2C_CH_C,
+	  .kbps = 400,
+	  .scl = GPIO_I2C_C_SCL,
+	  .sda = GPIO_I2C_C_SDA },
+	{ .name = "usb1",
+	  .port = IT83XX_I2C_CH_E,
+	  .kbps = 1000,
+	  .scl = GPIO_I2C_E_SCL,
+	  .sda = GPIO_I2C_E_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -315,26 +308,30 @@ __override int board_rt1718s_init(int port)
 
 	/* gpio 1/2 output high when receiving frx signal */
 	RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_GPIO1_VBUS_CTRL,
-			RT1718S_GPIO1_VBUS_CTRL_FRS_RX_VBUS, 0xFF));
+					  RT1718S_GPIO1_VBUS_CTRL_FRS_RX_VBUS,
+					  0xFF));
 	RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_GPIO2_VBUS_CTRL,
-			RT1718S_GPIO2_VBUS_CTRL_FRS_RX_VBUS, 0xFF));
+					  RT1718S_GPIO2_VBUS_CTRL_FRS_RX_VBUS,
+					  0xFF));
 
 	/* Turn on SBU switch */
-	RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_RT2_SBU_CTRL_01,
-				RT1718S_RT2_SBU_CTRL_01_SBU_VIEN |
-				RT1718S_RT2_SBU_CTRL_01_SBU2_SWEN |
-				RT1718S_RT2_SBU_CTRL_01_SBU1_SWEN,
-				0xFF));
+	RETURN_ERROR(
+		rt1718s_update_bits8(port, RT1718S_RT2_SBU_CTRL_01,
+				     RT1718S_RT2_SBU_CTRL_01_SBU_VIEN |
+					     RT1718S_RT2_SBU_CTRL_01_SBU2_SWEN |
+					     RT1718S_RT2_SBU_CTRL_01_SBU1_SWEN,
+				     0xFF));
 	/* Trigger GPIO 1/2 change when FRS signal received */
-	RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_FRS_CTRL3,
-			RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO2 |
+	RETURN_ERROR(rt1718s_update_bits8(
+		port, RT1718S_FRS_CTRL3,
+		RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO2 |
 			RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO1,
-			RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO2 |
+		RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO2 |
 			RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO1));
 	/* Set FRS signal detect time to 46.875us */
 	RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_FRS_CTRL1,
-			RT1718S_FRS_CTRL1_FRSWAPRX_MASK,
-			0xFF));
+					  RT1718S_FRS_CTRL1_FRSWAPRX_MASK,
+					  0xFF));
 
 	return EC_SUCCESS;
 }
@@ -371,13 +368,6 @@ void board_reset_pd_mcu(void)
 	/* C1: Add code if TCPC chips need a reset */
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_set_input_current_limit(
-		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
-
 void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
 {
 	/*
@@ -452,13 +442,12 @@ int ppc_get_alert_status(int port)
 	return 0;
 }
 /* SD Card */
-int board_regulator_get_info(uint32_t index, char *name,
-			     uint16_t *num_voltages, uint16_t *voltages_mv)
+int board_regulator_get_info(uint32_t index, char *name, uint16_t *num_voltages,
+			     uint16_t *voltages_mv)
 {
 	enum mt6360_regulator_id id = index;
 
-	return mt6360_regulator_get_info(id, name, num_voltages,
-					 voltages_mv);
+	return mt6360_regulator_get_info(id, name, num_voltages, voltages_mv);
 }
 
 int board_regulator_enable(uint32_t index, uint8_t enable)
@@ -508,7 +497,7 @@ __override int board_rt1718s_set_frs_enable(int port, int enable)
 		 * FRS path.
 		 */
 		rt1718s_gpio_set_flags(port, GPIO_EN_USB_C1_FRS,
-				enable ? GPIO_OUT_HIGH : GPIO_OUT_LOW);
+				       enable ? GPIO_OUT_HIGH : GPIO_OUT_LOW);
 	return EC_SUCCESS;
 }
 
diff --git a/baseboard/cherry/baseboard.h b/baseboard/cherry/baseboard.h
index a03c5c5dbd..2b0d03a436 100644
--- a/baseboard/cherry/baseboard.h
+++ b/baseboard/cherry/baseboard.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -93,13 +93,13 @@
 #define CONFIG_I2C_CONTROLLER
 #define CONFIG_I2C_PASSTHRU_RESTRICTED
 #define CONFIG_I2C_VIRTUAL_BATTERY
-#define I2C_PORT_CHARGER  IT83XX_I2C_CH_A
-#define I2C_PORT_BATTERY  IT83XX_I2C_CH_A
-#define I2C_PORT_ACCEL    IT83XX_I2C_CH_B
-#define I2C_PORT_PPC0     IT83XX_I2C_CH_C
-#define I2C_PORT_PPC1     IT83XX_I2C_CH_E
-#define I2C_PORT_USB0     IT83XX_I2C_CH_C
-#define I2C_PORT_USB1     IT83XX_I2C_CH_E
+#define I2C_PORT_CHARGER IT83XX_I2C_CH_A
+#define I2C_PORT_BATTERY IT83XX_I2C_CH_A
+#define I2C_PORT_ACCEL IT83XX_I2C_CH_B
+#define I2C_PORT_PPC0 IT83XX_I2C_CH_C
+#define I2C_PORT_PPC1 IT83XX_I2C_CH_E
+#define I2C_PORT_USB0 IT83XX_I2C_CH_C
+#define I2C_PORT_USB1 IT83XX_I2C_CH_E
 #define I2C_PORT_USB_MUX0 IT83XX_I2C_CH_C
 #define I2C_PORT_USB_MUX1 IT83XX_I2C_CH_E
 #define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
@@ -155,7 +155,7 @@
 #define PD_MAX_VOLTAGE_MV 20000
 #define PD_OPERATING_POWER_MW 15000
 #define PD_MAX_POWER_MW 60000
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* USB-A */
@@ -202,13 +202,12 @@
 	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \
 	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |        \
 	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT) |     \
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |     \
 	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
 
 /* And the MKBP events */
 #define CONFIG_MKBP_EVENT_WAKEUP_MASK \
-		(BIT(EC_MKBP_EVENT_KEY_MATRIX) | \
-		 BIT(EC_MKBP_EVENT_HOST_EVENT))
+	(BIT(EC_MKBP_EVENT_KEY_MATRIX) | BIT(EC_MKBP_EVENT_HOST_EVENT))
 
 #ifndef __ASSEMBLER__
 
@@ -217,11 +216,11 @@
 #include "power/mt8192.h"
 
 enum adc_channel {
-	ADC_VBUS,                /* ADC 0 */
-	ADC_BOARD_ID,            /* ADC 1 */
-	ADC_SKU_ID,              /* ADC 2 */
-	ADC_CHARGER_AMON_R,      /* ADC 3 */
-	ADC_CHARGER_PMON,        /* ADC 6 */
+	ADC_VBUS, /* ADC 0 */
+	ADC_BOARD_ID, /* ADC 1 */
+	ADC_SKU_ID, /* ADC 2 */
+	ADC_CHARGER_AMON_R, /* ADC 3 */
+	ADC_CHARGER_PMON, /* ADC 6 */
 	ADC_TEMP_SENSOR_CHARGER, /* ADC 7 */
 
 	/* Number of ADC channels */
@@ -239,7 +238,7 @@ void rt1718s_tcpc_interrupt(enum gpio_signal signal);
 /* RT1718S gpio to pin name mapping */
 #define GPIO_EN_USB_C1_VBUS_L RT1718S_GPIO1
 #define GPIO_EN_USB_C1_5V_OUT RT1718S_GPIO2
-#define GPIO_EN_USB_C1_FRS    RT1718S_GPIO3
+#define GPIO_EN_USB_C1_FRS RT1718S_GPIO3
 
 #endif /* !__ASSEMBLER__ */
 #endif /* __CROS_EC_BASEBOARD_H */
diff --git a/baseboard/cherry/build.mk b/baseboard/cherry/build.mk
index ae82c1ca68..74609511c3 100644
--- a/baseboard/cherry/build.mk
+++ b/baseboard/cherry/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/baseboard/cherry/usb_pd_policy.c b/baseboard/cherry/usb_pd_policy.c
index 1e7664bab9..450f5c06d7 100644
--- a/baseboard/cherry/usb_pd_policy.c
+++ b/baseboard/cherry/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,8 +19,8 @@
 #error Cherry reference must have at least one 3.0 A port
 #endif
 
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
 
 /* The port that the aux channel is on. */
 static enum {
@@ -90,8 +90,7 @@ __override int svdm_dp_attention(int port, uint32_t *payload)
 
 	dp_status[port] = payload[1];
 
-	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
-	    (irq || lvl))
+	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && (irq || lvl))
 		/*
 		 * Wake up the AP.  IRQ or level high indicates a DP sink is now
 		 * present.
@@ -164,7 +163,7 @@ __override void svdm_exit_dp_mode(int port)
 		svdm_set_hpd_gpio(port, 0);
 #endif /* CONFIG_USB_PD_DP_HPD_GPIO */
 	usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-				 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 #ifdef USB_PD_PORT_TCPC_MST
 	if (port == USB_PD_PORT_TCPC_MST)
 		baseboard_mst_enable_control(port, 0);
@@ -204,16 +203,11 @@ int pd_snk_is_vbus_provided(int port)
 
 void pd_power_supply_reset(int port)
 {
-	int prev_en;
-
-	prev_en = ppc_is_sourcing_vbus(port);
-
 	/* Disable VBUS. */
 	ppc_vbus_source_enable(port, 0);
 
 	/* Enable discharge if we were previously sourcing 5V */
-	if (prev_en)
-		pd_set_vbus_discharge(port, 1);
+	pd_set_vbus_discharge(port, 1);
 
 	if (port == 1)
 		rt1718s_gpio_set_level(port, GPIO_EN_USB_C1_5V_OUT, 0);
diff --git a/baseboard/dedede/baseboard.c b/baseboard/dedede/baseboard.c
index 60b3949e93..cd55f37588 100644
--- a/baseboard/dedede/baseboard.c
+++ b/baseboard/dedede/baseboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,8 +23,8 @@
 #include "usb_pd.h"
 
 /* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 /******************************************************************************/
 /*
@@ -81,7 +81,6 @@ const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[] = {
 };
 const int pwrok_signal_deassert_count = ARRAY_SIZE(pwrok_signal_deassert_list);
 
-
 /*
  * Dedede does not use hibernate wake pins, but the super low power "Z-state"
  * instead in which the EC is powered off entirely.  Power will be restored to
@@ -149,8 +148,8 @@ __override int intel_x86_get_pg_ec_dsw_pwrok(void)
 }
 
 /* Store away PP300_A good status before sysjumps */
-#define BASEBOARD_SYSJUMP_TAG	0x4242 /* BB */
-#define BASEBOARD_HOOK_VERSION	1
+#define BASEBOARD_SYSJUMP_TAG 0x4242 /* BB */
+#define BASEBOARD_HOOK_VERSION 1
 
 static void pp3300_a_pgood_preserve(void)
 {
@@ -167,13 +166,13 @@ static void baseboard_prepare_power_signals(void)
 	stored = (const int *)system_get_jump_tag(BASEBOARD_SYSJUMP_TAG,
 						  &version, &size);
 	if (stored && (version == BASEBOARD_HOOK_VERSION) &&
-					(size == sizeof(pp3300_a_pgood)))
+	    (size == sizeof(pp3300_a_pgood)))
 		/* Valid PP3300 status found, restore before CHIPSET init */
 		pp3300_a_pgood = *stored;
 
 	/* Restore pull-up on PG_PP1050_ST_OD */
 	if (system_jumped_to_this_image() &&
-					gpio_get_level(GPIO_PG_EC_RSMRST_ODL))
+	    gpio_get_level(GPIO_PG_EC_RSMRST_ODL))
 		board_after_rsmrst(1);
 }
 DECLARE_HOOK(HOOK_INIT, baseboard_prepare_power_signals, HOOK_PRIO_FIRST);
@@ -191,8 +190,8 @@ __override int intel_x86_get_pg_ec_all_sys_pwrgd(void)
 	 * PGOOD.
 	 */
 	return gpio_get_level(GPIO_PG_PP1050_ST_OD) &&
-		gpio_get_level(GPIO_PG_DRAM_OD) &&
-		gpio_get_level(GPIO_PG_VCCIO_EXT_OD);
+	       gpio_get_level(GPIO_PG_DRAM_OD) &&
+	       gpio_get_level(GPIO_PG_VCCIO_EXT_OD);
 }
 
 __override int power_signal_get_level(enum gpio_signal signal)
@@ -209,7 +208,6 @@ __override int power_signal_get_level(enum gpio_signal signal)
 			return espi_vw_get_wire((enum espi_vw_signal)signal);
 	}
 	return gpio_get_level(signal);
-
 }
 
 void baseboard_all_sys_pgood_interrupt(enum gpio_signal signal)
@@ -220,8 +218,8 @@ void baseboard_all_sys_pgood_interrupt(enum gpio_signal signal)
 	 * driver to.
 	 * Early protos do not pull VCCST_PWRGD below Vil in hardware logic,
 	 * so we need to do the same for this signal.
-	 * Pull EN_VCCIO_EXT to LOW, which ensures VCCST_PWRGD remains LOW during
-	 * SLP_S3_L assertion.
+	 * Pull EN_VCCIO_EXT to LOW, which ensures VCCST_PWRGD remains LOW
+	 * during SLP_S3_L assertion.
 	 */
 	if (!gpio_get_level(GPIO_SLP_S3_L)) {
 		gpio_set_level(GPIO_ALL_SYS_PWRGD, 0);
@@ -259,9 +257,9 @@ void board_hibernate_late(void)
 
 	/* Disable any pull-ups on C0 and C1 interrupt lines */
 	gpio_set_flags(GPIO_USB_C0_INT_ODL, GPIO_INPUT);
-	#if CONFIG_USB_PD_PORT_MAX_COUNT > 1
-		gpio_set_flags(GPIO_USB_C1_INT_ODL, GPIO_INPUT);
-	#endif
+#if CONFIG_USB_PD_PORT_MAX_COUNT > 1
+	gpio_set_flags(GPIO_USB_C1_INT_ODL, GPIO_INPUT);
+#endif
 	/*
 	 * Turn on the Z state.  This will not return as it will cut power to
 	 * the EC.
@@ -296,7 +294,7 @@ int board_is_i2c_port_powered(int port)
 	return chipset_in_state(CHIPSET_STATE_ANY_OFF) ? 0 : 1;
 }
 
-int extpower_is_present(void)
+__overridable int extpower_is_present(void)
 {
 	int port;
 	int rv;
diff --git a/baseboard/dedede/baseboard.h b/baseboard/dedede/baseboard.h
index 0085c48ec3..e581a0e8d0 100644
--- a/baseboard/dedede/baseboard.h
+++ b/baseboard/dedede/baseboard.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,11 +8,13 @@
 #ifndef __CROS_EC_BASEBOARD_H
 #define __CROS_EC_BASEBOARD_H
 
+#define CONFIG_LTO
+
 /*
  * By default, enable all console messages excepted HC, ACPI and event:
  * The sensor stack is generating a lot of activity.
  */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
 #undef CONFIG_HOSTCMD_DEBUG_MODE
 #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
 
@@ -20,39 +22,37 @@
  * Variant EC defines. Pick one:
  * VARIANT_DEDEDE_EC_NPCX796FC
  */
-#if defined(VARIANT_DEDEDE_EC_NPCX796FC) || \
-	defined(VARIANT_KEEBY_EC_NPCX797FC)
-	/* NPCX7 config */
-	#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
-	#define NPCX_TACH_SEL2    0  /* No tach. */
-
-	/* Internal SPI flash on NPCX7 */
-	#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
-	#define CONFIG_SPI_FLASH_REGS
-	#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
-#elif defined(VARIANT_DEDEDE_EC_IT8320) || \
-	defined(VARIANT_KEEBY_EC_IT8320)
-	/* IT83XX config */
-	#define CONFIG_IT83XX_VCC_1P8V
-	/* I2C Bus Configuration */
-	#define I2C_PORT_EEPROM		IT83XX_I2C_CH_A
-	#define I2C_PORT_BATTERY	IT83XX_I2C_CH_B
-	#define I2C_PORT_SENSOR		IT83XX_I2C_CH_C
-	#define I2C_PORT_SUB_USB_C1	IT83XX_I2C_CH_E
-	#define I2C_PORT_USB_C0		IT83XX_I2C_CH_F
-
-	#define I2C_ADDR_EEPROM_FLAGS	0x50
-
-	#define CONFIG_ADC_VOLTAGE_COMPARATOR	/* ITE ADC thresholds */
-
-	#undef CONFIG_UART_TX_BUF_SIZE		/* UART */
-	#define CONFIG_UART_TX_BUF_SIZE 4096
-
-	/*
-	 * Limit maximal ODR to 125Hz, the EC is using ~5ms per sample at
-	 * 48MHz core cpu clock.
-	 */
-	#define CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ 125000
+#if defined(VARIANT_DEDEDE_EC_NPCX796FC) || defined(VARIANT_KEEBY_EC_NPCX797FC)
+/* NPCX7 config */
+#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */
+#define NPCX_TACH_SEL2 0 /* No tach. */
+
+/* Internal SPI flash on NPCX7 */
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
+#define CONFIG_SPI_FLASH_REGS
+#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
+#elif defined(VARIANT_DEDEDE_EC_IT8320) || defined(VARIANT_KEEBY_EC_IT8320)
+/* IT83XX config */
+#define CONFIG_IT83XX_VCC_1P8V
+/* I2C Bus Configuration */
+#define I2C_PORT_EEPROM IT83XX_I2C_CH_A
+#define I2C_PORT_BATTERY IT83XX_I2C_CH_B
+#define I2C_PORT_SENSOR IT83XX_I2C_CH_C
+#define I2C_PORT_SUB_USB_C1 IT83XX_I2C_CH_E
+#define I2C_PORT_USB_C0 IT83XX_I2C_CH_F
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+
+#define CONFIG_ADC_VOLTAGE_COMPARATOR /* ITE ADC thresholds */
+
+#undef CONFIG_UART_TX_BUF_SIZE /* UART */
+#define CONFIG_UART_TX_BUF_SIZE 4096
+
+/*
+ * Limit maximal ODR to 125Hz, the EC is using ~5ms per sample at
+ * 48MHz core cpu clock.
+ */
+#define CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ 125000
 #else
 #error "Must define a VARIANT_[DEDEDE|KEEBY]_EC!"
 #endif
@@ -71,36 +71,36 @@
  * Remapping of schematic GPIO names to common GPIO names expected (hardcoded)
  * in the EC code base.
  */
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_EC_INT_L		GPIO_EC_AP_MKBP_INT_L
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_U
-#define GPIO_ENTERING_RW	GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2		GPIO_EC_KSO_02_INV
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_AP_MKBP_INT_L
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_U
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
 #if !KEEBY_VARIANT
-#define GPIO_PACKET_MODE_EN	GPIO_ECH1_PACKET_MODE
+#define GPIO_PACKET_MODE_EN GPIO_ECH1_PACKET_MODE
 #endif
-#define GPIO_PCH_DSW_PWROK	GPIO_EC_AP_DPWROK
-#define GPIO_PCH_PWRBTN_L	GPIO_EC_AP_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L	GPIO_EC_AP_RSMRST_L
-#define GPIO_PCH_RTCRST		GPIO_EC_AP_RTCRST
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_PCH_WAKE_L		GPIO_EC_AP_WAKE_ODL
-#define GPIO_PG_EC_RSMRST_ODL	GPIO_RSMRST_PWRGD_L
+#define GPIO_PCH_DSW_PWROK GPIO_EC_AP_DPWROK
+#define GPIO_PCH_PWRBTN_L GPIO_EC_AP_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_AP_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_AP_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L
+#define GPIO_PCH_WAKE_L GPIO_EC_AP_WAKE_ODL
+#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_PWRGD_L
 #if KEEBY_VARIANT
-#define GPIO_POWER_BUTTON_L	GPIO_EC_PWR_BTN_ODL
+#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL
 #else
-#define GPIO_POWER_BUTTON_L	GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
 #endif
-#define GPIO_PG_EC_RSMRST_ODL	GPIO_RSMRST_PWRGD_L
-#define GPIO_SYS_RESET_L	GPIO_SYS_RST_ODL
-#define GPIO_USB_C0_DP_HPD	GPIO_EC_AP_USB_C0_HPD
-#define GPIO_USB_C1_DP_HPD	GPIO_EC_AP_USB_C1_HDMI_HPD
-#define GPIO_VOLUME_UP_L	GPIO_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L	GPIO_VOLDN_BTN_ODL
-#define GPIO_WP			GPIO_EC_WP_OD
-#define GPIO_TABLET_MODE_L	GPIO_LID_360_L
+#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_PWRGD_L
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_USB_C0_DP_HPD GPIO_EC_AP_USB_C0_HPD
+#define GPIO_USB_C1_DP_HPD GPIO_EC_AP_USB_C1_HDMI_HPD
+#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL
+#define GPIO_WP GPIO_EC_WP_OD
+#define GPIO_TABLET_MODE_L GPIO_LID_360_L
 
 /* Common EC defines */
 
@@ -175,7 +175,7 @@
 
 /* Backlight */
 #define CONFIG_BACKLIGHT_LID
-#define GPIO_ENABLE_BACKLIGHT   GPIO_EN_BL_OD
+#define GPIO_ENABLE_BACKLIGHT GPIO_EN_BL_OD
 
 /* LED */
 #define CONFIG_LED_COMMON
@@ -206,7 +206,7 @@
 
 /* Temp Sensor */
 #define CONFIG_TEMP_SENSOR_POWER
-#define GPIO_TEMP_SENSOR_POWER  GPIO_EN_PP3300_A
+#define GPIO_TEMP_SENSOR_POWER GPIO_EN_PP3300_A
 #define CONFIG_TEMP_SENSOR_FIRST_READ_DELAY_MS 500
 
 /* USB PD */
@@ -238,14 +238,13 @@
 #endif
 
 /* Define typical operating power and max power. */
-#define PD_MAX_VOLTAGE_MV     20000
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_POWER_MW       45000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_POWER_MW 45000
 #define PD_OPERATING_POWER_MW 15000
 
 /* TODO(b:147314141): Verify these timings */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000	/* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	250000	/* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 #ifndef __ASSEMBLER__
 
@@ -255,13 +254,8 @@
 
 /* Common enums */
 #if defined(VARIANT_DEDEDE_EC_NPCX796FC)
-#elif defined(VARIANT_DEDEDE_EC_IT8320) || \
-	defined(VARIANT_KEEBY_EC_IT8320)
-	enum board_vcmp {
-		VCMP_SNS_PP3300_LOW,
-		VCMP_SNS_PP3300_HIGH,
-		VCMP_COUNT
-	};
+#elif defined(VARIANT_DEDEDE_EC_IT8320) || defined(VARIANT_KEEBY_EC_IT8320)
+enum board_vcmp { VCMP_SNS_PP3300_LOW, VCMP_SNS_PP3300_HIGH, VCMP_COUNT };
 #endif
 
 /* Interrupt handler for signals that are used to generate ALL_SYS_PGOOD. */
diff --git a/baseboard/dedede/build.mk b/baseboard/dedede/build.mk
index 6d7452081e..af71eb2222 100644
--- a/baseboard/dedede/build.mk
+++ b/baseboard/dedede/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/baseboard/dedede/cbi_fw_config.c b/baseboard/dedede/cbi_fw_config.c
index 65a8cbaad9..612c51700d 100644
--- a/baseboard/dedede/cbi_fw_config.c
+++ b/baseboard/dedede/cbi_fw_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -35,36 +35,36 @@ enum fw_config_db get_cbi_fw_config_db(void)
 
 enum fw_config_stylus get_cbi_fw_config_stylus(void)
 {
-	return ((cached_fw_config & FW_CONFIG_STYLUS_MASK)
-			>> FW_CONFIG_STYLUS_OFFSET);
+	return ((cached_fw_config & FW_CONFIG_STYLUS_MASK) >>
+		FW_CONFIG_STYLUS_OFFSET);
 }
 
 enum fw_config_kblight_type get_cbi_fw_config_kblight(void)
 {
-	return ((cached_fw_config & FW_CONFIG_KB_BL_MASK)
-			>> FW_CONFIG_KB_BL_OFFSET);
+	return ((cached_fw_config & FW_CONFIG_KB_BL_MASK) >>
+		FW_CONFIG_KB_BL_OFFSET);
 }
 
 enum fw_config_tablet_mode_type get_cbi_fw_config_tablet_mode(void)
 {
-	return ((cached_fw_config & FW_CONFIG_TABLET_MODE_MASK)
-			>> FW_CONFIG_TABLET_MODE_OFFSET);
+	return ((cached_fw_config & FW_CONFIG_TABLET_MODE_MASK) >>
+		FW_CONFIG_TABLET_MODE_OFFSET);
 }
 
 int get_cbi_fw_config_keyboard(void)
 {
-	return ((cached_fw_config & FW_CONFIG_KB_LAYOUT_MASK)
-			>> FW_CONFIG_KB_LAYOUT_OFFSET);
+	return ((cached_fw_config & FW_CONFIG_KB_LAYOUT_MASK) >>
+		FW_CONFIG_KB_LAYOUT_OFFSET);
 }
 
 enum fw_config_numeric_pad_type get_cbi_fw_config_numeric_pad(void)
 {
-	return ((cached_fw_config & FW_CONFIG_KB_NUMPAD_MASK)
-		>> FW_CONFIG_KB_NUMPAD_OFFSET);
+	return ((cached_fw_config & FW_CONFIG_KB_NUMPAD_MASK) >>
+		FW_CONFIG_KB_NUMPAD_OFFSET);
 }
 
 enum fw_config_hdmi_type get_cbi_fw_config_hdmi(void)
 {
-	return ((cached_fw_config & FW_CONFIG_HDMI_MASK)
-		>> FW_CONFIG_HDMI_OFFSET);
+	return ((cached_fw_config & FW_CONFIG_HDMI_MASK) >>
+		FW_CONFIG_HDMI_OFFSET);
 }
diff --git a/baseboard/dedede/cbi_fw_config.h b/baseboard/dedede/cbi_fw_config.h
index 90cc5e5fbe..80712f2849 100644
--- a/baseboard/dedede/cbi_fw_config.h
+++ b/baseboard/dedede/cbi_fw_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,8 +24,8 @@ enum fw_config_db {
 	DB_1C,
 	DB_1A_HDMI_LTE,
 };
-#define FW_CONFIG_DB_OFFSET			0
-#define FW_CONFIG_DB_MASK			GENMASK(3, 0)
+#define FW_CONFIG_DB_OFFSET 0
+#define FW_CONFIG_DB_MASK GENMASK(3, 0)
 
 /*
  * Stylus (1 bit)
@@ -34,8 +34,8 @@ enum fw_config_stylus {
 	STYLUS_ABSENT = 0,
 	STYLUS_PRESENT = 1,
 };
-#define FW_CONFIG_STYLUS_OFFSET			4
-#define FW_CONFIG_STYLUS_MASK			GENMASK(4, 4)
+#define FW_CONFIG_STYLUS_OFFSET 4
+#define FW_CONFIG_STYLUS_MASK GENMASK(4, 4)
 
 /*
  * Keyboard backlight (1 bit)
@@ -44,8 +44,8 @@ enum fw_config_kblight_type {
 	KB_BL_ABSENT = 0,
 	KB_BL_PRESENT = 1,
 };
-#define FW_CONFIG_KB_BL_OFFSET			8
-#define FW_CONFIG_KB_BL_MASK			GENMASK(8, 8)
+#define FW_CONFIG_KB_BL_OFFSET 8
+#define FW_CONFIG_KB_BL_MASK GENMASK(8, 8)
 
 /*
  * Keyboard numeric pad (1 bit)
@@ -54,8 +54,8 @@ enum fw_config_numeric_pad_type {
 	NUMERIC_PAD_ABSENT = 0,
 	NUMERIC_PAD_PRESENT = 1,
 };
-#define FW_CONFIG_KB_NUMPAD_OFFSET		9
-#define FW_CONFIG_KB_NUMPAD_MASK		GENMASK(9, 9)
+#define FW_CONFIG_KB_NUMPAD_OFFSET 9
+#define FW_CONFIG_KB_NUMPAD_MASK GENMASK(9, 9)
 
 /*
  * Tablet Mode (1 bit)
@@ -64,11 +64,11 @@ enum fw_config_tablet_mode_type {
 	TABLET_MODE_ABSENT = 0,
 	TABLET_MODE_PRESENT = 1,
 };
-#define FW_CONFIG_TABLET_MODE_OFFSET		10
-#define FW_CONFIG_TABLET_MODE_MASK		GENMASK(10, 10)
+#define FW_CONFIG_TABLET_MODE_OFFSET 10
+#define FW_CONFIG_TABLET_MODE_MASK GENMASK(10, 10)
 
-#define FW_CONFIG_KB_LAYOUT_OFFSET		12
-#define FW_CONFIG_KB_LAYOUT_MASK		GENMASK(13, 12)
+#define FW_CONFIG_KB_LAYOUT_OFFSET 12
+#define FW_CONFIG_KB_LAYOUT_MASK GENMASK(13, 12)
 
 /*
  * Hdmi (1 bit)
@@ -77,8 +77,8 @@ enum fw_config_hdmi_type {
 	HDMI_ABSENT = 0,
 	HDMI_PRESENT = 1,
 };
-#define FW_CONFIG_HDMI_OFFSET			17
-#define FW_CONFIG_HDMI_MASK			GENMASK(17, 17)
+#define FW_CONFIG_HDMI_OFFSET 17
+#define FW_CONFIG_HDMI_MASK GENMASK(17, 17)
 
 enum fw_config_db get_cbi_fw_config_db(void);
 enum fw_config_stylus get_cbi_fw_config_stylus(void);
diff --git a/baseboard/dedede/variant_ec_it8320.c b/baseboard/dedede/variant_ec_it8320.c
index 29c7758c6a..37929ceb0b 100644
--- a/baseboard/dedede/variant_ec_it8320.c
+++ b/baseboard/dedede/variant_ec_it8320.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,7 @@
 #include "power.h"
 #include "registers.h"
 
-#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
 
 static void pp3300_a_pgood_low(void)
 {
@@ -75,47 +75,37 @@ BUILD_ASSERT(ARRAY_SIZE(vcmp_list) == VCMP_COUNT);
 
 /* I2C Ports */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_EEPROM_SCL,
-		.sda  = GPIO_EC_I2C_EEPROM_SDA
-	},
-
-	{
-		.name = "battery",
-		.port = I2C_PORT_BATTERY,
-		.kbps = 100,
-		.scl  = GPIO_EC_I2C_BATTERY_SCL,
-		.sda  = GPIO_EC_I2C_BATTERY_SDA
-	},
-#ifdef HAS_TASK_MOTIONSENSE
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_SENSOR_SCL,
-		.sda  = GPIO_EC_I2C_SENSOR_SDA
-	},
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_EEPROM_SCL,
+	  .sda = GPIO_EC_I2C_EEPROM_SDA },
+
+	{ .name = "battery",
+	  .port = I2C_PORT_BATTERY,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_BATTERY_SCL,
+	  .sda = GPIO_EC_I2C_BATTERY_SDA },
+#if defined(HAS_TASK_MOTIONSENSE) || defined(BOARD_SHOTZO)
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_SENSOR_SCL,
+	  .sda = GPIO_EC_I2C_SENSOR_SDA },
 #endif
 
 #if CONFIG_USB_PD_PORT_MAX_COUNT > 1
-	{
-		.name = "sub_usbc1",
-		.port = I2C_PORT_SUB_USB_C1,
-		.kbps = 1000,
-		.scl  = GPIO_EC_I2C_SUB_USB_C1_SCL,
-		.sda  = GPIO_EC_I2C_SUB_USB_C1_SDA
-	},
+	{ .name = "sub_usbc1",
+	  .port = I2C_PORT_SUB_USB_C1,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_SUB_USB_C1_SCL,
+	  .sda = GPIO_EC_I2C_SUB_USB_C1_SDA },
 #endif
 
-	{
-		.name = "usbc0",
-		.port = I2C_PORT_USB_C0,
-		.kbps = 1000,
-		.scl  = GPIO_EC_I2C_USB_C0_SCL,
-		.sda  = GPIO_EC_I2C_USB_C0_SDA
-	},
+	{ .name = "usbc0",
+	  .port = I2C_PORT_USB_C0,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C0_SCL,
+	  .sda = GPIO_EC_I2C_USB_C0_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/baseboard/dedede/variant_ec_npcx796fc.c b/baseboard/dedede/variant_ec_npcx796fc.c
index aa2709b33b..366fca878e 100644
--- a/baseboard/dedede/variant_ec_npcx796fc.c
+++ b/baseboard/dedede/variant_ec_npcx796fc.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,8 +21,8 @@
 #include "timer.h"
 
 /* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 void pp3300_a_pgood_high(void)
 {
@@ -79,7 +79,7 @@ static void set_up_adc_irqs(void)
 	npcx_adc_thresh_int_enable(NPCX_ADC_THRESH1, 1);
 	npcx_adc_thresh_int_enable(NPCX_ADC_THRESH2, 1);
 }
-DECLARE_HOOK(HOOK_INIT, set_up_adc_irqs, HOOK_PRIO_INIT_ADC+1);
+DECLARE_HOOK(HOOK_INIT, set_up_adc_irqs, HOOK_PRIO_INIT_ADC + 1);
 
 static void disable_adc_irqs_deferred(void)
 {
@@ -144,8 +144,8 @@ static void enable_adc_irqs(void)
 	if (chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF)) {
 		CPRINTS("%s", __func__);
 		hook_call_deferred(&disable_adc_irqs_deferred_data, -1);
-		npcx_set_adc_repetitive(adc_channels[ADC_VSNS_PP3300_A].input_ch,
-					1);
+		npcx_set_adc_repetitive(
+			adc_channels[ADC_VSNS_PP3300_A].input_ch, 1);
 		npcx_adc_thresh_int_enable(NPCX_ADC_THRESH1, 1);
 		npcx_adc_thresh_int_enable(NPCX_ADC_THRESH2, 1);
 	}
@@ -162,56 +162,44 @@ DECLARE_HOOK(HOOK_LID_CHANGE, enable_adc_irqs_via_lid, HOOK_PRIO_DEFAULT);
 
 /* I2C Ports */
 __attribute__((weak)) const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 1000,
-		.scl  = GPIO_EC_I2C_EEPROM_SCL,
-		.sda  = GPIO_EC_I2C_EEPROM_SDA
-	},
-
-	{
-		.name = "battery",
-		.port = I2C_PORT_BATTERY,
-		.kbps = 100,
-		.scl  = GPIO_EC_I2C_BATTERY_SCL,
-		.sda  = GPIO_EC_I2C_BATTERY_SDA
-	},
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_EEPROM_SCL,
+	  .sda = GPIO_EC_I2C_EEPROM_SDA },
+
+	{ .name = "battery",
+	  .port = I2C_PORT_BATTERY,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_BATTERY_SCL,
+	  .sda = GPIO_EC_I2C_BATTERY_SDA },
 
 #ifdef HAS_TASK_MOTIONSENSE
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_SENSOR_SCL,
-		.sda  = GPIO_EC_I2C_SENSOR_SDA
-	},
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_SENSOR_SCL,
+	  .sda = GPIO_EC_I2C_SENSOR_SDA },
 #endif
 
-	{
-		.name = "usbc0",
-		.port = I2C_PORT_USB_C0,
-		.kbps = 1000,
-		.scl  = GPIO_EC_I2C_USB_C0_SCL,
-		.sda  = GPIO_EC_I2C_USB_C0_SDA
-	},
+	{ .name = "usbc0",
+	  .port = I2C_PORT_USB_C0,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C0_SCL,
+	  .sda = GPIO_EC_I2C_USB_C0_SDA },
 #if CONFIG_USB_PD_PORT_MAX_COUNT > 1
-	{
-		.name = "sub_usbc1",
-		.port = I2C_PORT_SUB_USB_C1,
-		.kbps = 1000,
-		.scl  = GPIO_EC_I2C_SUB_USB_C1_SCL,
-		.sda  = GPIO_EC_I2C_SUB_USB_C1_SDA
-	},
+	{ .name = "sub_usbc1",
+	  .port = I2C_PORT_SUB_USB_C1,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_SUB_USB_C1_SCL,
+	  .sda = GPIO_EC_I2C_SUB_USB_C1_SDA },
 #endif
 #ifdef BOARD_BUGZZY
-	{
-		.name = "lcd",
-		.port = I2C_PORT_LCD,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_LCD_SCL,
-		.sda  = GPIO_EC_I2C_LCD_SDA
-	},
+	{ .name = "lcd",
+	  .port = I2C_PORT_LCD,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_LCD_SCL,
+	  .sda = GPIO_EC_I2C_LCD_SDA },
 #endif
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/baseboard/goroh/baseboard.c b/baseboard/goroh/baseboard.c
index d51b881753..f70f070fac 100644
--- a/baseboard/goroh/baseboard.c
+++ b/baseboard/goroh/baseboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -48,8 +48,8 @@
 
 #include "gpio_list.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
 /* Wake-up pins for hibernate */
 enum gpio_signal hibernate_wake_pins[] = {
@@ -68,11 +68,9 @@ const struct charger_config_t chg_chips[] = {
 };
 
 /* BC12 skeleton to make build happy. */
-struct bc12_config bc12_ports[CHARGE_PORT_COUNT] = {
-};
+struct bc12_config bc12_ports[CHARGE_PORT_COUNT] = {};
 
-const int usb_port_enable[USB_PORT_COUNT] = {
-};
+const int usb_port_enable[USB_PORT_COUNT] = {};
 
 /* Called on AP S3 -> S0 transition */
 static void board_chipset_resume(void)
@@ -109,34 +107,26 @@ DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
 
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "bat_chg",
-		.port = IT83XX_I2C_CH_A,
-		.kbps = 100,
-		.scl  = GPIO_I2C_A_SCL,
-		.sda  = GPIO_I2C_A_SDA
-	},
-	{
-		.name = "sensor",
-		.port = IT83XX_I2C_CH_B,
-		.kbps = 400,
-		.scl  = GPIO_I2C_B_SCL,
-		.sda  = GPIO_I2C_B_SDA
-	},
-	{
-		.name = "usb0",
-		.port = IT83XX_I2C_CH_C,
-		.kbps = 400,
-		.scl  = GPIO_I2C_C_SCL,
-		.sda  = GPIO_I2C_C_SDA
-	},
-	{
-		.name = "usb1",
-		.port = IT83XX_I2C_CH_E,
-		.kbps = 400,
-		.scl  = GPIO_I2C_E_SCL,
-		.sda  = GPIO_I2C_E_SDA
-	},
+	{ .name = "bat_chg",
+	  .port = IT83XX_I2C_CH_A,
+	  .kbps = 100,
+	  .scl = GPIO_I2C_A_SCL,
+	  .sda = GPIO_I2C_A_SDA },
+	{ .name = "sensor",
+	  .port = IT83XX_I2C_CH_B,
+	  .kbps = 400,
+	  .scl = GPIO_I2C_B_SCL,
+	  .sda = GPIO_I2C_B_SDA },
+	{ .name = "usb0",
+	  .port = IT83XX_I2C_CH_C,
+	  .kbps = 400,
+	  .scl = GPIO_I2C_C_SCL,
+	  .sda = GPIO_I2C_C_SDA },
+	{ .name = "usb1",
+	  .port = IT83XX_I2C_CH_E,
+	  .kbps = 400,
+	  .scl = GPIO_I2C_E_SCL,
+	  .sda = GPIO_I2C_E_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -145,7 +135,6 @@ int board_allow_i2c_passthru(const struct i2c_cmd_desc_t *cmd_desc)
 	return (cmd_desc->port == I2C_PORT_VIRTUAL_BATTERY);
 }
 
-
 void board_overcurrent_event(int port, int is_overcurrented)
 {
 	/* TODO: check correct operation for GOROH */
@@ -155,21 +144,25 @@ const struct cc_para_t *board_get_cc_tuning_parameter(enum usbpd_port port)
 {
 	const static struct cc_para_t
 		cc_parameter[CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT] = {
-		{
-			.rising_time = IT83XX_TX_PRE_DRIVING_TIME_1_UNIT,
-			.falling_time = IT83XX_TX_PRE_DRIVING_TIME_2_UNIT,
-		},
-		{
-			.rising_time = IT83XX_TX_PRE_DRIVING_TIME_1_UNIT,
-			.falling_time = IT83XX_TX_PRE_DRIVING_TIME_2_UNIT,
-		},
-	};
+			{
+				.rising_time =
+					IT83XX_TX_PRE_DRIVING_TIME_1_UNIT,
+				.falling_time =
+					IT83XX_TX_PRE_DRIVING_TIME_2_UNIT,
+			},
+			{
+				.rising_time =
+					IT83XX_TX_PRE_DRIVING_TIME_1_UNIT,
+				.falling_time =
+					IT83XX_TX_PRE_DRIVING_TIME_2_UNIT,
+			},
+		};
 
 	return &cc_parameter[port];
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	charge_set_input_current_limit(
 		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
diff --git a/baseboard/goroh/baseboard.h b/baseboard/goroh/baseboard.h
index c0246e9970..1488bb6fcf 100644
--- a/baseboard/goroh/baseboard.h
+++ b/baseboard/goroh/baseboard.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -73,20 +73,20 @@
 #define CONFIG_KEYBOARD_BACKLIGHT
 #define CONFIG_PWM_KBLIGHT
 #define CONFIG_KBLIGHT_ENABLE_PIN
-#define GPIO_EN_KEYBOARD_BACKLIGHT	GPIO_EN_PPVAR_KB_BL_X
+#define GPIO_EN_KEYBOARD_BACKLIGHT GPIO_EN_PPVAR_KB_BL_X
 
 /* I2C */
 #define CONFIG_I2C
 #define CONFIG_I2C_CONTROLLER
 #define CONFIG_I2C_PASSTHRU_RESTRICTED
 #define CONFIG_I2C_VIRTUAL_BATTERY
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 #define I2C_PORT_EEPROM IT83XX_I2C_CH_A
 #define I2C_PORT_CHARGER IT83XX_I2C_CH_A
 #define I2C_PORT_BATTERY IT83XX_I2C_CH_A
 #define I2C_PORT_ACCEL IT83XX_I2C_CH_B
-#define I2C_PORT_USB_C0  IT83XX_I2C_CH_C
-#define I2C_PORT_USB_C1  IT83XX_I2C_CH_E
+#define I2C_PORT_USB_C0 IT83XX_I2C_CH_C
+#define I2C_PORT_USB_C1 IT83XX_I2C_CH_E
 #define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
 #define CONFIG_SMBUS_PEC
 
@@ -128,14 +128,14 @@
 #define CONFIG_USB_PD_TCPMV2
 #define CONFIG_USB_PD_TRY_SRC
 #define CONFIG_USB_PD_VBUS_DETECT_PPC
-#define CONFIG_USB_PID 0x5566  /* TODO: update PID */
+#define CONFIG_USB_PID 0x5566 /* TODO: update PID */
 #define CONFIG_USB_POWER_DELIVERY
 
 #define PD_MAX_CURRENT_MA 3000
 #define PD_MAX_VOLTAGE_MV 20000
 #define PD_OPERATING_POWER_MW 15000
 #define PD_MAX_POWER_MW 60000
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* USB-A */
@@ -174,13 +174,13 @@
 	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |    \
 	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \
 	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |        \
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |     \
 	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
 
 /* GPIO name remapping */
-#define GPIO_VOLUME_UP_L        GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L      GPIO_EC_VOLDN_BTN_ODL
-#define GPIO_AC_PRESENT         GPIO_ACOK_OD
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
 
 #ifndef __ASSEMBLER__
 
diff --git a/baseboard/goroh/baseboard_usbc_config.h b/baseboard/goroh/baseboard_usbc_config.h
index b5e76644ee..7da00c17d6 100644
--- a/baseboard/goroh/baseboard_usbc_config.h
+++ b/baseboard/goroh/baseboard_usbc_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/baseboard/goroh/board_id.c b/baseboard/goroh/board_id.c
index fd2001d8a3..7bc77d5229 100644
--- a/baseboard/goroh/board_id.c
+++ b/baseboard/goroh/board_id.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -34,21 +34,8 @@
  * 14 |   47 |  680 | 3086.7
  */
 const static int voltage_map[] = {
-	136,
-	388,
-	584,
-	785,
-	993,
-	1220,
-	1432,
-	1650,
-	1875,
-	2084,
-	2273,
-	2461,
-	2672,
-	2888,
-	3086,
+	136,  388,  584,  785,	993,  1220, 1432, 1650,
+	1875, 2084, 2273, 2461, 2672, 2888, 3086,
 };
 
 const int threshold_mv = 100;
diff --git a/baseboard/goroh/build.mk b/baseboard/goroh/build.mk
index 4488c4b395..6a3a386efb 100644
--- a/baseboard/goroh/build.mk
+++ b/baseboard/goroh/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/baseboard/goroh/usb_pd_policy.c b/baseboard/goroh/usb_pd_policy.c
index 5030489ec8..e92ced5e89 100644
--- a/baseboard/goroh/usb_pd_policy.c
+++ b/baseboard/goroh/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,8 +15,8 @@
 #error Goroh reference must have at least one 3.0 A port
 #endif
 
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
 
 void svdm_set_hpd_gpio(int port, int en)
 {
diff --git a/baseboard/goroh/usbc_config.c b/baseboard/goroh/usbc_config.c
index 5a49d2ee2d..9d162ca783 100644
--- a/baseboard/goroh/usbc_config.c
+++ b/baseboard/goroh/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,14 +14,14 @@
 #include "hooks.h"
 #include "driver/tcpm/it8xxx2_pd_public.h"
 #include "driver/ppc/syv682x_public.h"
-#include "driver/retimer/ps8818.h"
+#include "driver/retimer/ps8818_public.h"
 #include "driver/tcpm/tcpci.h"
 #include "usb_pd.h"
 #include "usbc_ppc.h"
 #include "gpio.h"
 #include "gpio_signal.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 #ifdef CONFIG_BRINGUP
 #define GPIO_SET_LEVEL(pin, lvl) gpio_set_level_verbose(CC_USBPD, pin, lvl)
@@ -62,7 +62,6 @@ static int goroh_usb_c0_set_mux(const struct usb_mux *me, mux_state_t mux_state,
 	mux_state = mux_state ^ USB_PD_MUX_POLARITY_INVERTED;
 
 	return virtual_usb_mux_driver.set(me, mux_state, ack_required);
-
 }
 
 static int goroh_usb_c0_get_mux(const struct usb_mux *me,
@@ -77,25 +76,32 @@ static struct usb_mux_driver goroh_usb_c0_mux_driver = {
 	.get = goroh_usb_c0_get_mux,
 };
 
-static const struct usb_mux goroh_usb_c1_ps8818_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.i2c_port = I2C_PORT_USB_C1,
-	.i2c_addr_flags = PS8818_I2C_ADDR_FLAGS,
-	.driver = &ps8818_usb_retimer_driver,
-	.next_mux = NULL,
+static const struct usb_mux_chain goroh_usb_c1_ps8818_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.i2c_port = I2C_PORT_USB_C1,
+			.i2c_addr_flags = PS8818_I2C_ADDR_FLAGS,
+			.driver = &ps8818_usb_retimer_driver,
+		},
+	.next = NULL,
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &goroh_usb_c0_mux_driver,
-		.hpd_update = &virtual_hpd_update,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &goroh_usb_c0_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 	},
 	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &goroh_usb_c1_ps8818_retimer,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &goroh_usb_c1_ps8818_retimer,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
@@ -128,7 +134,6 @@ void ppc_interrupt(enum gpio_signal signal)
 		syv682x_interrupt(1);
 }
 
-
 static void board_tcpc_init(void)
 {
 	gpio_enable_interrupt(GPIO_USB_C0_FAULT_ODL);
diff --git a/baseboard/grunt/baseboard.c b/baseboard/grunt/baseboard.c
index b1f110033a..5fbf2823be 100644
--- a/baseboard/grunt/baseboard.c
+++ b/baseboard/grunt/baseboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -47,34 +47,29 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0
-	},
-	[ADC_TEMP_SENSOR_SOC] = {
-		"SOC", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0
-	},
-	[ADC_VBUS] = {
-		"VBUS", NPCX_ADC_CH8, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0
-	},
-	[ADC_SKU_ID1] = {
-		"SKU1", NPCX_ADC_CH9, ADC_MAX_VOLT, ADC_READ_MAX+1, 0
-	},
-	[ADC_SKU_ID2] = {
-		"SKU2", NPCX_ADC_CH4, ADC_MAX_VOLT, ADC_READ_MAX+1, 0
-	},
+	[ADC_TEMP_SENSOR_CHARGER] = { "CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				      ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_SOC] = { "SOC", NPCX_ADC_CH1, ADC_MAX_VOLT,
+				  ADC_READ_MAX + 1, 0 },
+	[ADC_VBUS] = { "VBUS", NPCX_ADC_CH8, ADC_MAX_VOLT * 10,
+		       ADC_READ_MAX + 1, 0 },
+	[ADC_SKU_ID1] = { "SKU1", NPCX_ADC_CH9, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+			  0 },
+	[ADC_SKU_ID2] = { "SKU2", NPCX_ADC_CH4, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+			  0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* Power signal list.  Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
-	{GPIO_PCH_SLP_S3_L,	POWER_SIGNAL_ACTIVE_HIGH, "SLP_S3_DEASSERTED"},
-	{GPIO_PCH_SLP_S5_L,	POWER_SIGNAL_ACTIVE_HIGH, "SLP_S5_DEASSERTED"},
-	{GPIO_S0_PGOOD,		POWER_SIGNAL_ACTIVE_HIGH, "S0_PGOOD"},
-	{GPIO_S5_PGOOD,		POWER_SIGNAL_ACTIVE_HIGH, "S5_PGOOD"},
+	{ GPIO_PCH_SLP_S3_L, POWER_SIGNAL_ACTIVE_HIGH, "SLP_S3_DEASSERTED" },
+	{ GPIO_PCH_SLP_S5_L, POWER_SIGNAL_ACTIVE_HIGH, "SLP_S5_DEASSERTED" },
+	{ GPIO_S0_PGOOD, POWER_SIGNAL_ACTIVE_HIGH, "S0_PGOOD" },
+	{ GPIO_S5_PGOOD, POWER_SIGNAL_ACTIVE_HIGH, "S5_PGOOD" },
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
@@ -156,7 +151,7 @@ void board_tcpc_init(void)
 	 */
 	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
 		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
 DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
 
@@ -278,46 +273,48 @@ static uint32_t sku_id;
 static int ps8751_tune_mux(const struct usb_mux *me)
 {
 	/* Tune USB mux registers for treeya's port 1 Rx measurement */
-	if (((sku_id >= 0xa0) && (sku_id <= 0xaf)) ||
-	   sku_id == 0xbe || sku_id == 0xbf)
+	if (((sku_id >= 0xa0) && (sku_id <= 0xaf)) || sku_id == 0xbe ||
+	    sku_id == 0xbf)
 		mux_write(me, PS8XXX_REG_MUX_USB_C2SS_EQ, 0x40);
 
 	return EC_SUCCESS;
 }
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 #ifdef VARIANT_GRUNT_TCPC_0_ANX3429
 	[USB_PD_PORT_ANX74XX] = {
-		.usb_port = USB_PD_PORT_ANX74XX,
-		.driver = &anx74xx_tcpm_usb_mux_driver,
-		.hpd_update = &anx74xx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_ANX74XX,
+			.driver = &anx74xx_tcpm_usb_mux_driver,
+			.hpd_update = &anx74xx_tcpc_update_hpd_status,
+		},
 	},
 #elif defined(VARIANT_GRUNT_TCPC_0_ANX3447)
 	[USB_PD_PORT_ANX74XX] = {
-		.usb_port = USB_PD_PORT_ANX74XX,
-		.driver = &anx7447_usb_mux_driver,
-		.hpd_update = &anx7447_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_ANX74XX,
+			.driver = &anx7447_usb_mux_driver,
+			.hpd_update = &anx7447_tcpc_update_hpd_status,
+		},
 	},
 #endif
 	[USB_PD_PORT_PS8751] = {
-		.usb_port = USB_PD_PORT_PS8751,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-		.board_init = &ps8751_tune_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_PS8751,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			.board_init = &ps8751_tune_mux,
+		},
 	}
 };
 
 struct ppc_config_t ppc_chips[] = {
-	{
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	{
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
+	{ .i2c_port = I2C_PORT_TCPC0,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
+	{ .i2c_port = I2C_PORT_TCPC1,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
 };
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
@@ -338,8 +335,8 @@ int ppc_get_alert_status(int port)
 
 void board_overcurrent_event(int port, int is_overcurrented)
 {
-	enum gpio_signal signal = (port == 0) ? GPIO_USB_C0_OC_L
-					      : GPIO_USB_C1_OC_L;
+	enum gpio_signal signal = (port == 0) ? GPIO_USB_C0_OC_L :
+						GPIO_USB_C1_OC_L;
 	/* Note that the levels are inverted because the pin is active low. */
 	int lvl = is_overcurrented ? 0 : 1;
 
@@ -371,7 +368,6 @@ const struct charger_config_t chg_chips[] = {
 	},
 };
 
-
 const int usb_port_enable[USB_PORT_COUNT] = {
 	GPIO_EN_USB_A0_5V,
 	GPIO_EN_USB_A1_5V,
@@ -393,7 +389,6 @@ static void baseboard_chipset_resume(void)
 {
 	/* Allow display backlight to turn on. See above backlight comment */
 	gpio_set_level(GPIO_ENABLE_BACKLIGHT_L, 0);
-
 }
 DECLARE_HOOK(HOOK_CHIPSET_RESUME, baseboard_chipset_resume, HOOK_PRIO_DEFAULT);
 
@@ -469,17 +464,16 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	/*
 	 * Limit the input current to 95% negotiated limit,
 	 * to account for the charger chip margin.
 	 */
 	charge_ma = charge_ma * 95 / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 /* Keyboard scan setting */
@@ -513,19 +507,19 @@ __override struct keyboard_scan_config keyscan_config = {
  * Murata page for part NCP15WB473F03RC. Vdd=3.3V, R=30.9Kohm.
  */
 static const struct thermistor_data_pair thermistor_data[] = {
-	{ 2761 / THERMISTOR_SCALING_FACTOR, 0},
-	{ 2492 / THERMISTOR_SCALING_FACTOR, 10},
-	{ 2167 / THERMISTOR_SCALING_FACTOR, 20},
-	{ 1812 / THERMISTOR_SCALING_FACTOR, 30},
-	{ 1462 / THERMISTOR_SCALING_FACTOR, 40},
-	{ 1146 / THERMISTOR_SCALING_FACTOR, 50},
-	{ 878 / THERMISTOR_SCALING_FACTOR, 60},
-	{ 665 / THERMISTOR_SCALING_FACTOR, 70},
-	{ 500 / THERMISTOR_SCALING_FACTOR, 80},
-	{ 434 / THERMISTOR_SCALING_FACTOR, 85},
-	{ 376 / THERMISTOR_SCALING_FACTOR, 90},
-	{ 326 / THERMISTOR_SCALING_FACTOR, 95},
-	{ 283 / THERMISTOR_SCALING_FACTOR, 100}
+	{ 2761 / THERMISTOR_SCALING_FACTOR, 0 },
+	{ 2492 / THERMISTOR_SCALING_FACTOR, 10 },
+	{ 2167 / THERMISTOR_SCALING_FACTOR, 20 },
+	{ 1812 / THERMISTOR_SCALING_FACTOR, 30 },
+	{ 1462 / THERMISTOR_SCALING_FACTOR, 40 },
+	{ 1146 / THERMISTOR_SCALING_FACTOR, 50 },
+	{ 878 / THERMISTOR_SCALING_FACTOR, 60 },
+	{ 665 / THERMISTOR_SCALING_FACTOR, 70 },
+	{ 500 / THERMISTOR_SCALING_FACTOR, 80 },
+	{ 434 / THERMISTOR_SCALING_FACTOR, 85 },
+	{ 376 / THERMISTOR_SCALING_FACTOR, 90 },
+	{ 326 / THERMISTOR_SCALING_FACTOR, 95 },
+	{ 283 / THERMISTOR_SCALING_FACTOR, 100 }
 };
 
 static const struct thermistor_info thermistor_info = {
@@ -537,8 +531,8 @@ static const struct thermistor_info thermistor_info = {
 static int board_get_temp(int idx, int *temp_k)
 {
 	/* idx is the sensor index set below in temp_sensors[] */
-	int mv = adc_read_channel(
-		idx ? ADC_TEMP_SENSOR_SOC : ADC_TEMP_SENSOR_CHARGER);
+	int mv = adc_read_channel(idx ? ADC_TEMP_SENSOR_SOC :
+					ADC_TEMP_SENSOR_CHARGER);
 	int temp_c;
 
 	if (mv < 0)
@@ -550,9 +544,9 @@ static int board_get_temp(int idx, int *temp_k)
 }
 
 const struct temp_sensor_t temp_sensors[] = {
-	{"Charger", TEMP_SENSOR_TYPE_BOARD, board_get_temp, 0},
-	{"SOC", TEMP_SENSOR_TYPE_BOARD, board_get_temp, 1},
-	{"CPU", TEMP_SENSOR_TYPE_CPU, sb_tsi_get_val, 0},
+	{ "Charger", TEMP_SENSOR_TYPE_BOARD, board_get_temp, 0 },
+	{ "SOC", TEMP_SENSOR_TYPE_BOARD, board_get_temp, 1 },
+	{ "CPU", TEMP_SENSOR_TYPE_CPU, sb_tsi_get_val, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -655,11 +649,11 @@ __override void lid_angle_peripheral_enable(int enable)
 static const int sku_thresh_mv[] = {
 	/* Vin = 3.3V, Ideal voltage, R2 values listed below */
 	/* R1 = 51.1 kOhm */
-	200,  /* 124 mV, 2.0 Kohm */
-	366,  /* 278 mV, 4.7 Kohm */
-	550,  /* 456 mV, 8.2  Kohm */
-	752,  /* 644 mV, 12.4 Kohm */
-	927,  /* 860 mV, 18.0 Kohm */
+	200, /* 124 mV, 2.0 Kohm */
+	366, /* 278 mV, 4.7 Kohm */
+	550, /* 456 mV, 8.2  Kohm */
+	752, /* 644 mV, 12.4 Kohm */
+	927, /* 860 mV, 18.0 Kohm */
 	1073, /* 993 mV, 22.0 Kohm */
 	1235, /* 1152 mV, 27.4 Kohm */
 	1386, /* 1318 mV, 34.0 Kohm */
@@ -706,10 +700,9 @@ static uint32_t board_get_adc_sku_id(void)
 
 static int board_get_gpio_board_version(void)
 {
-	return
-		(!!gpio_get_level(GPIO_BOARD_VERSION1) << 0) |
-		(!!gpio_get_level(GPIO_BOARD_VERSION2) << 1) |
-		(!!gpio_get_level(GPIO_BOARD_VERSION3) << 2);
+	return (!!gpio_get_level(GPIO_BOARD_VERSION1) << 0) |
+	       (!!gpio_get_level(GPIO_BOARD_VERSION2) << 1) |
+	       (!!gpio_get_level(GPIO_BOARD_VERSION3) << 2);
 }
 
 static int board_version;
@@ -767,8 +760,8 @@ int board_is_convertible(void)
 	/* Kasumi360: 82 */
 	/* Treeya360: a8-af, be, bf*/
 	return (sku_id == 6 || sku_id == 82 ||
-		((sku_id >= 0xa8) && (sku_id <= 0xaf)) ||
-		sku_id == 0xbe || sku_id == 0xbf);
+		((sku_id >= 0xa8) && (sku_id <= 0xaf)) || sku_id == 0xbe ||
+		sku_id == 0xbf);
 }
 
 int board_is_lid_angle_tablet_mode(void)
@@ -782,13 +775,11 @@ __override uint32_t board_override_feature_flags0(uint32_t flags0)
 	 * Remove keyboard backlight feature for devices that don't support it.
 	 * All Treeya and Treeya360 models do not support keyboard backlight.
 	 */
-	if (sku_id == 16 || sku_id == 17 ||
-	    sku_id == 20 || sku_id == 21 ||
-	    sku_id == 32 || sku_id == 33 ||
-	    sku_id == 40 || sku_id == 41 ||
+	if (sku_id == 16 || sku_id == 17 || sku_id == 20 || sku_id == 21 ||
+	    sku_id == 32 || sku_id == 33 || sku_id == 40 || sku_id == 41 ||
 	    sku_id == 44 || sku_id == 45 ||
-	    ((sku_id >= 0xa0) && (sku_id <= 0xaf)) ||
-		sku_id == 0xbe || sku_id == 0xbf)
+	    ((sku_id >= 0xa0) && (sku_id <= 0xaf)) || sku_id == 0xbe ||
+	    sku_id == 0xbf)
 		return (flags0 & ~EC_FEATURE_MASK_0(EC_FEATURE_PWM_KEYB));
 	else
 		return flags0;
diff --git a/baseboard/grunt/baseboard.h b/baseboard/grunt/baseboard.h
index 5a79c48c63..1c19c05330 100644
--- a/baseboard/grunt/baseboard.h
+++ b/baseboard/grunt/baseboard.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,15 +8,15 @@
 #ifndef __CROS_EC_BASEBOARD_H
 #define __CROS_EC_BASEBOARD_H
 
-#if (defined(VARIANT_GRUNT_TCPC_0_ANX3429) \
-	+ defined(VARIANT_GRUNT_TCPC_0_ANX3447)) != 1
+#if (defined(VARIANT_GRUNT_TCPC_0_ANX3429) + \
+     defined(VARIANT_GRUNT_TCPC_0_ANX3447)) != 1
 #error Must choose VARIANT_GRUNT_TCPC_0_ANX3429 or VARIANT_GRUNT_TCPC_0_ANX3447
 #endif
 
 /* NPCX7 config */
-#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
-#define NPCX_TACH_SEL2    0  /* No tach. */
-#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
+#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */
+#define NPCX_TACH_SEL2 0 /* No tach. */
+#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */
 
 /* Internal SPI flash on NPCX7 */
 /* Flash is 1MB but reserve half for future use. */
@@ -85,7 +85,7 @@
  * ACOK from ISL9238 sometimes has a negative pulse after connecting
  * USB-C power. We want to ignore it. b/77455171
  */
-#undef  CONFIG_EXTPOWER_DEBOUNCE_MS
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
 #define CONFIG_EXTPOWER_DEBOUNCE_MS 200
 #define CONFIG_EXTPOWER_GPIO
 #define CONFIG_POWER_COMMON
@@ -101,7 +101,6 @@
  */
 #define CONFIG_BOARD_RESET_AFTER_POWER_ON
 
-
 #define CONFIG_KEYBOARD_COL2_INVERTED
 #define CONFIG_KEYBOARD_PROTOCOL_8042
 
@@ -139,13 +138,13 @@
 #define CONFIG_USB_PORT_POWER_DUMB
 #define USB_PORT_COUNT 2
 
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
 
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		45000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 45000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /*
  * Require PD negotiation to be complete when we are in a low-battery condition
@@ -158,15 +157,15 @@
 #undef CONFIG_PORT80_HISTORY_LEN
 #define CONFIG_PORT80_HISTORY_LEN 256
 
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_POWER
-#define I2C_PORT_POWER		NPCX_I2C_PORT0_0
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT1_0
-#define I2C_PORT_TCPC1		NPCX_I2C_PORT2_0
-#define I2C_PORT_THERMAL_AP	NPCX_I2C_PORT3_0
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT7_0
+#define I2C_PORT_BATTERY I2C_PORT_POWER
+#define I2C_PORT_CHARGER I2C_PORT_POWER
+#define I2C_PORT_POWER NPCX_I2C_PORT0_0
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT1_0
+#define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0
+#define I2C_PORT_THERMAL_AP NPCX_I2C_PORT3_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT7_0
 /* Accelerometer and Gyroscope are the same device. */
-#define I2C_PORT_ACCEL		I2C_PORT_SENSOR
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
 
 /* Sensors */
 #define CONFIG_MKBP_EVENT
@@ -184,8 +183,8 @@
 #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
 #endif /* VARIANT_GRUNT_NO_SENSORS */
 
-#define USB_PD_PORT_ANX74XX	0
-#define USB_PD_PORT_PS8751	1
+#define USB_PD_PORT_ANX74XX 0
+#define USB_PD_PORT_PS8751 1
 
 #ifndef __ASSEMBLER__
 
diff --git a/baseboard/grunt/build.mk b/baseboard/grunt/build.mk
index cb9d607c36..c8a02aa85d 100644
--- a/baseboard/grunt/build.mk
+++ b/baseboard/grunt/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/baseboard/grunt/usb_pd_policy.c b/baseboard/grunt/usb_pd_policy.c
index 7c4fff953c..9cae485bc9 100644
--- a/baseboard/grunt/usb_pd_policy.c
+++ b/baseboard/grunt/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,11 +17,11 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
-#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\
-			 PDO_FIXED_COMM_CAP)
+#define PDO_FIXED_FLAGS \
+	(PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP | PDO_FIXED_COMM_CAP)
 
 int pd_check_vconn_swap(int port)
 {
@@ -118,11 +118,11 @@ __override int svdm_dp_config(int port, uint32_t *payload)
 		usb_mux_set(port, USB_PD_MUX_NONE, USB_SWITCH_CONNECT,
 			    polarity_rm_dts(pd_get_polarity(port)));
 
-	payload[0] = VDO(USB_SID_DISPLAYPORT, 1,
-			 CMD_DP_CONFIG | VDO_OPOS(opos));
-	payload[1] = VDO_DP_CFG(pin_mode,      /* pin mode */
-				1,             /* DPv1.3 signaling */
-				2);            /* UFP connected */
+	payload[0] =
+		VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_CONFIG | VDO_OPOS(opos));
+	payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */
+				1, /* DPv1.3 signaling */
+				2); /* UFP connected */
 	return 2;
 };
 
@@ -142,8 +142,8 @@ __override void svdm_dp_post_config(int port)
 
 	/* set the minimum time delay (2ms) for the next HPD IRQ */
 	svdm_hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
-	usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL |
-				 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+	usb_mux_hpd_update(port,
+			   USB_PD_MUX_HPD_LVL | USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
 
 #endif /* CONFIG_USB_PD_ALT_MODE_DFP */
diff --git a/baseboard/guybrush/base_fw_config.h b/baseboard/guybrush/base_fw_config.h
index 2eea7a158f..a9504a6b45 100644
--- a/baseboard/guybrush/base_fw_config.h
+++ b/baseboard/guybrush/base_fw_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/baseboard/guybrush/base_gpio.inc b/baseboard/guybrush/base_gpio.inc
index 6fd90ed0d3..82b042f890 100644
--- a/baseboard/guybrush/base_gpio.inc
+++ b/baseboard/guybrush/base_gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/baseboard/guybrush/baseboard.c b/baseboard/guybrush/baseboard.c
index 6a390b0a43..5d36f5be9a 100644
--- a/baseboard/guybrush/baseboard.c
+++ b/baseboard/guybrush/baseboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,11 +16,11 @@
 #include "chip/npcx/ps2_chip.h"
 #include "chip/npcx/pwm_chip.h"
 #include "chipset.h"
-#include "driver/ppc/aoz1380.h"
+#include "driver/ppc/aoz1380_public.h"
 #include "driver/ppc/nx20p348x.h"
 #include "driver/retimer/anx7491.h"
 #include "driver/retimer/ps8811.h"
-#include "driver/retimer/ps8818.h"
+#include "driver/retimer/ps8818_public.h"
 #include "driver/tcpm/nct38xx.h"
 #include "driver/usb_mux/anx7451.h"
 #include "driver/usb_mux/amd_fp6.h"
@@ -40,10 +40,10 @@
 #include "usb_pd_tcpm.h"
 #include "usbc_ppc.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define CPRINTSCHIP(format, args...) cprints(CC_CHIPSET, format ## args)
+#define CPRINTSCHIP(format, args...) cprints(CC_CHIPSET, format##args)
 
 static void reset_nct38xx_port(int port);
 
@@ -53,7 +53,7 @@ const enum gpio_signal hibernate_wake_pins[] = {
 	GPIO_AC_PRESENT,
 	GPIO_POWER_BUTTON_L,
 };
-const int hibernate_wake_pins_used =  ARRAY_SIZE(hibernate_wake_pins);
+const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 
 /* Power Signal Input List */
 const struct power_signal_info power_signal_list[] = {
@@ -145,8 +145,6 @@ const struct i2c_port_t i2c_ports[] = {
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
-
-
 const struct charger_config_t chg_chips[] = {
 	{
 		.i2c_port = I2C_PORT_CHARGER,
@@ -235,7 +233,7 @@ const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
 
-static int fsusb42umx_set_mux(const struct usb_mux*, mux_state_t);
+static int fsusb42umx_set_mux(const struct usb_mux *, mux_state_t);
 
 __overridable int board_c1_ps8818_mux_set(const struct usb_mux *me,
 					  mux_state_t mux_state)
@@ -244,7 +242,7 @@ __overridable int board_c1_ps8818_mux_set(const struct usb_mux *me,
 	return 0;
 }
 
-struct usb_mux usbc1_ps8818 = {
+const struct usb_mux usbc1_ps8818 = {
 	.usb_port = USBC_PORT_C1,
 	.i2c_port = I2C_PORT_TCPC1,
 	.flags = USB_MUX_FLAG_RESETS_IN_G3,
@@ -260,7 +258,7 @@ __overridable int board_c1_anx7451_mux_set(const struct usb_mux *me,
 	return 0;
 }
 
-struct usb_mux usbc1_anx7451 = {
+const struct usb_mux usbc1_anx7451 = {
 	.usb_port = USBC_PORT_C1,
 	.i2c_port = I2C_PORT_TCPC1,
 	.flags = USB_MUX_FLAG_RESETS_IN_G3,
@@ -269,20 +267,27 @@ struct usb_mux usbc1_anx7451 = {
 	.board_set = &board_c1_anx7451_mux_set,
 };
 
-struct usb_mux usb_muxes[] = {
+/* Filled in by setup_mux based on fw_config */
+struct usb_mux_chain usbc1_mux1;
+
+struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = AMD_FP6_C0_MUX_I2C_ADDR,
-		.driver = &amd_fp6_usb_mux_driver,
-		.board_set = &fsusb42umx_set_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.i2c_port = I2C_PORT_USB_MUX,
+			.i2c_addr_flags = AMD_FP6_C0_MUX_I2C_ADDR,
+			.driver = &amd_fp6_usb_mux_driver,
+			.board_set = &fsusb42umx_set_mux,
+		},
 	},
 	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = AMD_FP6_C4_MUX_I2C_ADDR,
-		.driver = &amd_fp6_usb_mux_driver,
-		/* .next_mux = filled in by setup_mux based on fw_config */
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.i2c_port = I2C_PORT_USB_MUX,
+			.i2c_addr_flags = AMD_FP6_C4_MUX_I2C_ADDR,
+			.driver = &amd_fp6_usb_mux_driver,
+		},
+		.next = &usbc1_mux1,
 	}
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
@@ -375,22 +380,22 @@ static void setup_mux(void)
 	switch (board_get_usb_c1_mux()) {
 	case USB_C1_MUX_PS8818:
 		CPRINTSUSB("C1: Setting PS8818 mux");
-		usb_muxes[USBC_PORT_C1].next_mux = &usbc1_ps8818;
+		usbc1_mux1.mux = &usbc1_ps8818;
 		break;
 	case USB_C1_MUX_ANX7451:
 		CPRINTSUSB("C1: Setting ANX7451 mux");
-		usb_muxes[USBC_PORT_C1].next_mux = &usbc1_anx7451;
+		usbc1_mux1.mux = &usbc1_anx7451;
 		break;
 	default:
 		CPRINTSUSB("C1: Mux is unknown");
+		usb_muxes[USBC_PORT_C1].next = NULL;
 	}
 }
 DECLARE_HOOK(HOOK_INIT, setup_mux, HOOK_PRIO_INIT_I2C);
 
 int board_set_active_charge_port(int port)
 {
-	int is_valid_port = (port >= 0 &&
-			     port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	int i;
 	int rv;
 
@@ -404,7 +409,7 @@ int board_set_active_charge_port(int port)
 			 * ahead and reset it so EN_SNK responds properly.
 			 */
 			if (nct38xx_get_boot_type(i) ==
-						NCT38XX_BOOT_DEAD_BATTERY) {
+			    NCT38XX_BOOT_DEAD_BATTERY) {
 				reset_nct38xx_port(i);
 				pd_set_error_recovery(i);
 			}
@@ -453,7 +458,7 @@ int board_set_active_charge_port(int port)
 				 * change because we'll brown out.
 				 */
 				if (nct38xx_get_boot_type(port) ==
-						NCT38XX_BOOT_DEAD_BATTERY) {
+				    NCT38XX_BOOT_DEAD_BATTERY) {
 					reset_nct38xx_port(i);
 					pd_set_error_recovery(i);
 				} else {
@@ -505,7 +510,9 @@ int board_is_i2c_port_powered(int port)
 	case I2C_PORT_THERMAL_AP:
 		/* SOC thermal i2c bus is unpowered in S0i3/S3/S5/Z1 */
 		return chipset_in_state(CHIPSET_STATE_ANY_OFF |
-					CHIPSET_STATE_ANY_SUSPEND) ? 0 : 1;
+					CHIPSET_STATE_ANY_SUSPEND) ?
+			       0 :
+			       1;
 	default:
 		return 1;
 	}
@@ -516,8 +523,7 @@ int board_is_i2c_port_powered(int port)
  * the attached NCT3807 to control a GPIO to indicate 1A5 or 3A0
  * current limits.
  */
-int board_aoz1380_set_vbus_source_current_limit(int port,
-						enum tcpc_rp_value rp)
+int board_aoz1380_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp)
 {
 	int rv;
 
@@ -528,12 +534,11 @@ int board_aoz1380_set_vbus_source_current_limit(int port,
 	return rv;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 void sbu_fault_interrupt(enum ioex_signal signal)
@@ -571,10 +576,10 @@ void tcpc_alert_event(enum gpio_signal signal)
 static void reset_nct38xx_port(int port)
 {
 	int rv;
-	int saved_state[IOEX_COUNT] = {0};
+	int saved_state[IOEX_COUNT] = { 0 };
 	enum gpio_signal reset_gpio_l = (port == USBC_PORT_C0) ?
-						      GPIO_USB_C0_TCPC_RST_L :
-						      GPIO_USB_C1_TCPC_RST_L;
+						GPIO_USB_C0_TCPC_RST_L :
+						GPIO_USB_C1_TCPC_RST_L;
 
 	if (port < 0 || port > USBC_PORT_COUNT) {
 		CPRINTSUSB("%s invalid port %d", __func__, port);
@@ -877,9 +882,9 @@ static void baseboard_set_en_pwr_pcore(void)
 	 * EN_PWR_S0_R.
 	 */
 	gpio_set_level(GPIO_EN_PWR_PCORE_S0_R,
-					gpio_get_level(GPIO_PG_LPDDR4X_S3_OD) &&
-					gpio_get_level(GPIO_PG_GROUPC_S0_OD) &&
-					gpio_get_level(GPIO_EN_PWR_S0_R));
+		       gpio_get_level(GPIO_PG_LPDDR4X_S3_OD) &&
+			       gpio_get_level(GPIO_PG_GROUPC_S0_OD) &&
+			       gpio_get_level(GPIO_EN_PWR_S0_R));
 }
 
 void baseboard_en_pwr_pcore_signal(enum gpio_signal signal)
@@ -891,19 +896,17 @@ static void baseboard_check_groupc_low(void)
 {
 	/* Warn if we see unexpected sequencing here */
 	if (!gpio_get_level(GPIO_EN_PWR_S0_R) &&
-					gpio_get_level(GPIO_PG_GROUPC_S0_OD))
+	    gpio_get_level(GPIO_PG_GROUPC_S0_OD))
 		CPRINTSCHIP("WARN: PG_GROUPC_S0_OD high while EN_PWR_S0_R low");
-
 }
 DECLARE_DEFERRED(baseboard_check_groupc_low);
 
 void baseboard_en_pwr_s0(enum gpio_signal signal)
 {
-
 	/* EC must AND signals SLP_S3_L and PG_PWR_S5 */
 	gpio_set_level(GPIO_EN_PWR_S0_R,
-					gpio_get_level(GPIO_SLP_S3_L) &&
-					gpio_get_level(GPIO_PG_PWR_S5));
+		       gpio_get_level(GPIO_SLP_S3_L) &&
+			       gpio_get_level(GPIO_PG_PWR_S5));
 
 	/*
 	 * If we set EN_PWR_S0_R low, then check PG_GROUPC_S0_OD went low as
@@ -973,7 +976,7 @@ __override void power_board_handle_sleep_hang(enum sleep_hang_type hang_type)
 		ccprints("Consecutive(%d) hard sleep hangs detected!",
 			 hard_sleep_hang_count);
 		ccprints("AP will be force shutdown in %dms if hang persists",
-			  HARD_SLEEP_HANG_TIMEOUT);
+			 HARD_SLEEP_HANG_TIMEOUT);
 	}
 
 	hook_call_deferred(&board_handle_hard_sleep_hang_data,
@@ -999,7 +1002,7 @@ static void board_handle_hard_sleep_hang(void)
 		/* If AP reset does not break hang, force a shutdown */
 		shutdown_on_hard_hang = true;
 		ccprints("AP will be shutdown in %dms if hang persists",
-			  HARD_SLEEP_HANG_TIMEOUT);
+			 HARD_SLEEP_HANG_TIMEOUT);
 		hook_call_deferred(&board_handle_hard_sleep_hang_data,
 				   HARD_SLEEP_HANG_TIMEOUT * MSEC);
 		chipset_reset(CHIPSET_RESET_HANG_REBOOT);
diff --git a/baseboard/guybrush/baseboard.h b/baseboard/guybrush/baseboard.h
index 2e30dfcc27..04b1e10c97 100644
--- a/baseboard/guybrush/baseboard.h
+++ b/baseboard/guybrush/baseboard.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,8 +10,8 @@
 
 /* NPCX9 config */
 #define CONFIG_PORT80_4_BYTE
-#define NPCX9_PWM1_SEL    1  /* GPIO C2 is used as PWM1. */
-#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
+#define NPCX9_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */
+#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */
 
 /* Optional features */
 #define CONFIG_ASSERT_CCD_MODE_ON_DTS_CONNECT
@@ -32,8 +32,8 @@
 #define CONFIG_VBOOT_HASH
 #define CONFIG_VSTORE
 #define CONFIG_VSTORE_SLOT_COUNT 1
-#define GPIO_ENTERING_RW	GPIO_EC_ENTERING_RW
-#define GPIO_PACKET_MODE_EN	GPIO_EC_GSC_PACKET_MODE
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
 
 /* CBI Config */
 #define CONFIG_CBI_EEPROM
@@ -41,7 +41,7 @@
 
 /* Power Config */
 #define CONFIG_CHIPSET_X86_RSMRST_DELAY
-#undef  CONFIG_EXTPOWER_DEBOUNCE_MS
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
 #define CONFIG_EXTPOWER_DEBOUNCE_MS 200
 #define CONFIG_EXTPOWER_GPIO
 #define CONFIG_HIBERNATE_PSL
@@ -54,19 +54,19 @@
 #define CONFIG_POWER_SLEEP_FAILURE_DETECTION
 #define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
 #define G3_TO_PWRBTN_DELAY_MS 16
-#define GPIO_AC_PRESENT		GPIO_ACOK_OD
-#define GPIO_EN_PWR_A		GPIO_EN_PWR_S5
-#define GPIO_PCH_PWRBTN_L	GPIO_EC_SOC_PWR_BTN_L
-#define GPIO_PCH_RSMRST_L	GPIO_EC_SOC_RSMRST_L
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S3_S0I3_L
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S5_L	GPIO_SLP_S5_L
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_SOC_PWR_GOOD
-#define GPIO_PCH_WAKE_L		GPIO_EC_SOC_WAKE_L
-#define GPIO_POWER_BUTTON_L	GPIO_MECH_PWR_BTN_ODL
-#define GPIO_S0_PGOOD		GPIO_PG_PCORE_S0_R_OD
-#define GPIO_S5_PGOOD		GPIO_PG_PWR_S5
-#define GPIO_SYS_RESET_L	GPIO_EC_SYS_RST_L
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_EN_PWR_A GPIO_EN_PWR_S5
+#define GPIO_PCH_PWRBTN_L GPIO_EC_SOC_PWR_BTN_L
+#define GPIO_PCH_RSMRST_L GPIO_EC_SOC_RSMRST_L
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S3_S0I3_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L
+#define GPIO_PCH_SYS_PWROK GPIO_EC_SOC_PWR_GOOD
+#define GPIO_PCH_WAKE_L GPIO_EC_SOC_WAKE_L
+#define GPIO_POWER_BUTTON_L GPIO_MECH_PWR_BTN_ODL
+#define GPIO_S0_PGOOD GPIO_PG_PCORE_S0_R_OD
+#define GPIO_S5_PGOOD GPIO_PG_PWR_S5
+#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L
 #define SAFE_RESET_VBUS_DELAY_MS 900
 #define SAFE_RESET_VBUS_MV 5000
 /*
@@ -86,12 +86,12 @@
 #define CONFIG_TEMP_SENSOR_SB_TSI
 #define CONFIG_THERMISTOR
 #define CONFIG_CPU_PROCHOT_ACTIVE_LOW
-#define GPIO_CPU_PROCHOT	GPIO_PROCHOT_ODL
+#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL
 
 /* Flash Config */
 /* See config_chip-npcx9.h for SPI flash configuration */
 #undef CONFIG_SPI_FLASH /* Don't enable external flash interface */
-#define GPIO_WP_L			GPIO_EC_WP_L
+#define GPIO_WP_L GPIO_EC_WP_L
 
 /* Host communication */
 #define CONFIG_CMD_APTHROTTLE
@@ -99,7 +99,7 @@
 #define CONFIG_HOST_INTERFACE_ESPI
 #define CONFIG_MKBP_EVENT
 #define CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT
-#define GPIO_EC_INT_L		GPIO_EC_SOC_INT_L
+#define GPIO_EC_INT_L GPIO_EC_SOC_INT_L
 
 /* Chipset config */
 #define CONFIG_CHIPSET_CEZANNE
@@ -114,15 +114,15 @@
 #define CONFIG_KEYBOARD_PROTOCOL_8042
 #define CONFIG_KEYBOARD_VIVALDI
 #define CONFIG_KBLIGHT_ENABLE_PIN
-#define GPIO_EN_KEYBOARD_BACKLIGHT	GPIO_EN_KB_BL
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
+#define GPIO_EN_KEYBOARD_BACKLIGHT GPIO_EN_KB_BL
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
 
 /* Sensors */
 #ifdef HAS_TASK_MOTIONSENSE
 
 #define CONFIG_TABLET_MODE
 #define CONFIG_GMR_TABLET_MODE
-#define GPIO_TABLET_MODE_L		GPIO_TABLET_MODE
+#define GPIO_TABLET_MODE_L GPIO_TABLET_MODE
 #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_UPDATE
@@ -138,7 +138,7 @@
 
 /* Sensors without hardware FIFO are in forced mode */
 #define CONFIG_ACCEL_FORCE_MODE_MASK (1 << LID_ACCEL)
-#endif  /* HAS_TASK_MOTIONSENSE */
+#endif /* HAS_TASK_MOTIONSENSE */
 
 /* Backlight config */
 #define CONFIG_BACKLIGHT_LID
@@ -146,7 +146,7 @@
 #define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_DISABLE_DISP_BL
 
 /* Battery Config */
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_EC_BATT_PRES_ODL
+#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL
 #define CONFIG_BATTERY_CUT_OFF
 #define CONFIG_BATTERY_FUEL_GAUGE
 #define CONFIG_BATTERY_REVIVE_DISCONNECT
@@ -172,7 +172,7 @@
  * CONFIG_CHARGER_LIMIT_* is not set, so there is no additional restriction on
  * Depthcharge to boot OS.
  */
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON		65000
+#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 65000
 
 /*
  * We would prefer to use CONFIG_CHARGE_RAMP_HW to enable legacy BC1.2 charging
@@ -226,8 +226,8 @@
 #define CONFIG_IO_EXPANDER_NCT38XX
 #define CONFIG_IO_EXPANDER_PORT_COUNT USBC_PORT_COUNT
 
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
 
 /* USB-A config */
 #define USB_PORT_COUNT USBA_PORT_COUNT
@@ -260,21 +260,21 @@
 #define CONFIG_I2C_BUS_MAY_BE_UNPOWERED
 #define CONFIG_I2C_CONTROLLER
 #define CONFIG_I2C_UPDATE_IF_CHANGED
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT0_0
-#define I2C_PORT_TCPC1		NPCX_I2C_PORT1_0
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_MUX	NPCX_I2C_PORT3_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT4_1
-#define I2C_PORT_CHARGER	I2C_PORT_POWER
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT5_0
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT6_1
-#define I2C_PORT_THERMAL_AP	NPCX_I2C_PORT7_0
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0
+#define I2C_PORT_TCPC1 NPCX_I2C_PORT1_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_MUX NPCX_I2C_PORT3_0
+#define I2C_PORT_POWER NPCX_I2C_PORT4_1
+#define I2C_PORT_CHARGER I2C_PORT_POWER
+#define I2C_PORT_EEPROM NPCX_I2C_PORT5_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT6_1
+#define I2C_PORT_THERMAL_AP NPCX_I2C_PORT7_0
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 
 /* Volume Button Config */
 #define CONFIG_VOLUME_BUTTONS
-#define GPIO_VOLUME_UP_L		GPIO_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL
 
 /* Fan Config */
 #define CONFIG_FANS FAN_CH_COUNT
@@ -290,30 +290,22 @@
 
 /* Power input signals */
 enum power_signal {
-	X86_SLP_S0_N,		/* SOC  -> SLP_S3_S0I3_L */
-	X86_SLP_S3_N,		/* SOC  -> SLP_S3_L */
-	X86_SLP_S5_N,		/* SOC  -> SLP_S5_L */
+	X86_SLP_S0_N, /* SOC  -> SLP_S3_S0I3_L */
+	X86_SLP_S3_N, /* SOC  -> SLP_S3_L */
+	X86_SLP_S5_N, /* SOC  -> SLP_S5_L */
 
-	X86_S0_PGOOD,		/* PMIC -> S0_PWROK_OD */
-	X86_S5_PGOOD,		/* PMIC -> S5_PWROK */
+	X86_S0_PGOOD, /* PMIC -> S0_PWROK_OD */
+	X86_S5_PGOOD, /* PMIC -> S5_PWROK */
 
 	/* Number of X86 signals */
 	POWER_SIGNAL_COUNT,
 };
 
 /* USB-C ports */
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 /* USB-A ports */
-enum usba_port {
-	USBA_PORT_A0 = 0,
-	USBA_PORT_A1,
-	USBA_PORT_COUNT
-};
+enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT };
 
 /* TMP112 sensors */
 enum tmp112_sensor {
@@ -322,12 +314,7 @@ enum tmp112_sensor {
 	TMP112_COUNT,
 };
 
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
 /* PWM Channels */
 enum pwm_channel {
diff --git a/baseboard/guybrush/build.mk b/baseboard/guybrush/build.mk
index dff52adc93..8110e6e6c4 100644
--- a/baseboard/guybrush/build.mk
+++ b/baseboard/guybrush/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/baseboard/guybrush/cbi.c b/baseboard/guybrush/cbi.c
index 6d66b826dc..6ce6fe0eb7 100644
--- a/baseboard/guybrush/cbi.c
+++ b/baseboard/guybrush/cbi.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -50,10 +50,9 @@ uint32_t get_fw_config(void)
 			return UNINITIALIZED_FW_CONFIG;
 		fw_config = val;
 	}
-	return  fw_config;
+	return fw_config;
 }
 
-
 int get_fw_config_field(uint8_t offset, uint8_t width)
 {
 	uint32_t fw_config = get_fw_config();
@@ -64,7 +63,6 @@ int get_fw_config_field(uint8_t offset, uint8_t width)
 	return (fw_config >> offset) & ((1 << width) - 1);
 }
 
-
 __overridable void board_cbi_init(void)
 {
 }
diff --git a/baseboard/guybrush/usb_pd_policy.c b/baseboard/guybrush/usb_pd_policy.c
index 79725e827a..8acb2c7a23 100644
--- a/baseboard/guybrush/usb_pd_policy.c
+++ b/baseboard/guybrush/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/baseboard/hatch/baseboard.c b/baseboard/hatch/baseboard.c
index bdbeb36a3c..f5376700c5 100644
--- a/baseboard/hatch/baseboard.c
+++ b/baseboard/hatch/baseboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -31,11 +31,11 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /******************************************************************************/
 /* Wake up pins */
@@ -52,85 +52,65 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 /* I2C port map configuration */
 const struct i2c_port_t i2c_ports[] = {
 #ifdef CONFIG_ACCEL_FIFO
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 100,
-		.scl  = GPIO_I2C0_SCL,
-		.sda  = GPIO_I2C0_SDA
-	},
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 100,
+	  .scl = GPIO_I2C0_SCL,
+	  .sda = GPIO_I2C0_SDA },
 #endif
-	{
-		.name = "ppc0",
-		.port = I2C_PORT_PPC0,
-		.kbps = 100,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	},
+	{ .name = "ppc0",
+	  .port = I2C_PORT_PPC0,
+	  .kbps = 100,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
 #if CONFIG_USB_PD_PORT_MAX_COUNT > 1
-	{
-		.name = "tcpc1",
-		.port = I2C_PORT_TCPC1,
-		.kbps = 400,
-		.scl  = GPIO_I2C2_SCL,
-		.sda  = GPIO_I2C2_SDA
-	},
+	{ .name = "tcpc1",
+	  .port = I2C_PORT_TCPC1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
 #endif
-	{
-		.name = "tcpc0",
-		.port = I2C_PORT_TCPC0,
-		.kbps = 400,
-		.scl  = GPIO_I2C3_SCL,
-		.sda  = GPIO_I2C3_SDA
-	},
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
 #ifdef BOARD_AKEMI
-	{
-		.name = "thermal",
-		.port = I2C_PORT_THERMAL,
-		.kbps = 400,
-		.scl  = GPIO_I2C4_SCL,
-		.sda  = GPIO_I2C4_SDA
-	},
+	{ .name = "thermal",
+	  .port = I2C_PORT_THERMAL,
+	  .kbps = 400,
+	  .scl = GPIO_I2C4_SCL,
+	  .sda = GPIO_I2C4_SDA },
 #endif
 #ifdef BOARD_JINLON
-	{
-		.name = "thermal",
-		.port = I2C_PORT_THERMAL,
-		.kbps = 100,
-		.scl  = GPIO_I2C4_SCL,
-		.sda  = GPIO_I2C4_SDA
-	},
+	{ .name = "thermal",
+	  .port = I2C_PORT_THERMAL,
+	  .kbps = 100,
+	  .scl = GPIO_I2C4_SCL,
+	  .sda = GPIO_I2C4_SDA },
 #endif
 #ifdef BOARD_MUSHU
-	{
-		.name = "f75303_temp",
-		.port = I2C_PORT_THERMAL,
-		.kbps = 100,
-		.scl  = GPIO_I2C0_SCL,
-		.sda  = GPIO_I2C0_SDA
-	},
-	{
-		.name = "gpu_temp",
-		.port = I2C_PORT_GPU,
-		.kbps = 100,
-		.scl  = GPIO_I2C4_SCL,
-		.sda  = GPIO_I2C4_SDA
-	},
+	{ .name = "f75303_temp",
+	  .port = I2C_PORT_THERMAL,
+	  .kbps = 100,
+	  .scl = GPIO_I2C0_SCL,
+	  .sda = GPIO_I2C0_SDA },
+	{ .name = "gpu_temp",
+	  .port = I2C_PORT_GPU,
+	  .kbps = 100,
+	  .scl = GPIO_I2C4_SCL,
+	  .sda = GPIO_I2C4_SDA },
 #endif
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl  = GPIO_I2C5_SCL,
-		.sda  = GPIO_I2C5_SDA
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 100,
-		.scl  = GPIO_I2C7_SCL,
-		.sda  = GPIO_I2C7_SDA
-	},
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_I2C5_SCL,
+	  .sda = GPIO_I2C5_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 100,
+	  .scl = GPIO_I2C7_SCL,
+	  .sda = GPIO_I2C7_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -202,17 +182,13 @@ void board_hibernate(void)
 /******************************************************************************/
 /* USB-C PPC Configuration */
 struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.i2c_port = I2C_PORT_PPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
+	[USB_PD_PORT_TCPC_0] = { .i2c_port = I2C_PORT_PPC0,
+				 .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+				 .drv = &sn5s330_drv },
 #if CONFIG_USB_PD_PORT_MAX_COUNT > 1
-	[USB_PD_PORT_TCPC_1] = {
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
+	[USB_PD_PORT_TCPC_1] = { .i2c_port = I2C_PORT_TCPC1,
+				 .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+				 .drv = &sn5s330_drv },
 #endif
 };
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
@@ -270,8 +246,8 @@ uint16_t tcpc_get_alert_status(void)
 	return status;
 }
 
-static void reset_pd_port(int port, enum gpio_signal reset_gpio,
-			  int hold_delay, int finish_delay)
+static void reset_pd_port(int port, enum gpio_signal reset_gpio, int hold_delay,
+			  int finish_delay)
 {
 	int level = !!(tcpc_config[port].flags & TCPC_FLAGS_RESET_ACTIVE_HIGH);
 
@@ -308,8 +284,7 @@ void board_reset_pd_mcu(void)
 
 int board_set_active_charge_port(int port)
 {
-	int is_valid_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	int i;
 
 	if (!is_valid_port && port != CHARGE_PORT_NONE)
@@ -365,20 +340,19 @@ int ppc_get_alert_status(int port)
 	if (port == USB_PD_PORT_TCPC_0)
 		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
 	return port == USB_PD_PORT_TCPC_0 ?
-		gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0 :
+		       gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0 :
 #if CONFIG_USB_PD_PORT_MAX_COUNT > 1
-		gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
+		       gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
 #else
-		EC_SUCCESS;
+		       EC_SUCCESS;
 #endif
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 #ifdef USB_PD_PORT_TCPC_MST
diff --git a/baseboard/hatch/baseboard.h b/baseboard/hatch/baseboard.h
index dc39fcf8ac..d5d680e7bf 100644
--- a/baseboard/hatch/baseboard.h
+++ b/baseboard/hatch/baseboard.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,13 +15,13 @@
  * By default, enable all console messages excepted HC, ACPI and event:
  * The sensor stack is generating a lot of activity.
  */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
 #undef CONFIG_HOSTCMD_DEBUG_MODE
 #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
 
 /* NPCX7 config */
-#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
-#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
+#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */
+#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */
 /* Internal SPI flash on NPCX796FC is 512 kB */
 #define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
 #define CONFIG_SPI_FLASH_REGS
@@ -111,14 +111,14 @@
 
 /* Common battery defines */
 #define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY  "LION"
+#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
 #define CONFIG_BATTERY_FUEL_GAUGE
 #define CONFIG_BATTERY_HW_PRESENT_CUSTOM
 #define CONFIG_BATTERY_PRESENT_CUSTOM
 #define CONFIG_BATTERY_REVIVE_DISCONNECT
 #define CONFIG_BATTERY_SMART
-#undef  CONFIG_BATT_HOST_FULL_FACTOR
-#define CONFIG_BATT_HOST_FULL_FACTOR	100
+#undef CONFIG_BATT_HOST_FULL_FACTOR
+#define CONFIG_BATT_HOST_FULL_FACTOR 100
 
 /* USB Type C and USB PD defines */
 #define CONFIG_USB_POWER_DELIVERY
@@ -153,9 +153,9 @@
 /* Include CLI command needed to support CCD testing. */
 #define CONFIG_CMD_CHARGEN
 
-#define USB_PD_PORT_TCPC_0	0
+#define USB_PD_PORT_TCPC_0 0
 #if CONFIG_USB_PD_PORT_MAX_COUNT > 1
-#define USB_PD_PORT_TCPC_1	1
+#define USB_PD_PORT_TCPC_1 1
 #endif
 
 /* BC 1.2 */
@@ -167,32 +167,32 @@
 #endif
 
 /* TODO(b/122273953): Use correct PD delay values */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000	/* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	250000	/* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* TODO(b/122273953): Use correct PD power values */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* I2C Bus Configuration */
 #define CONFIG_I2C
 #define CONFIG_I2C_CONTROLLER
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_PPC0		NPCX_I2C_PORT1_0
-#define I2C_PORT_TCPC1		NPCX_I2C_PORT2_0
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT3_0
-#define I2C_PORT_THERMAL	NPCX_I2C_PORT4_1
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_POWER
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_PPC0 NPCX_I2C_PORT1_0
+#define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT3_0
+#define I2C_PORT_THERMAL NPCX_I2C_PORT4_1
+#define I2C_PORT_POWER NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+#define I2C_PORT_BATTERY I2C_PORT_POWER
+#define I2C_PORT_CHARGER I2C_PORT_POWER
 
 /* Other common defines */
 #define CONFIG_BACKLIGHT_LID
-#define GPIO_ENABLE_BACKLIGHT   GPIO_EDP_BKLTEN_OD
+#define GPIO_ENABLE_BACKLIGHT GPIO_EDP_BKLTEN_OD
 
 #define PP5000_PGOOD_POWER_SIGNAL_MASK POWER_SIGNAL_MASK(X86_PP5000_A_PGOOD)
 
diff --git a/baseboard/hatch/battery.c b/baseboard/hatch/battery.c
index 063aa3721d..5ae92e8ec8 100644
--- a/baseboard/hatch/battery.c
+++ b/baseboard/hatch/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -32,8 +32,9 @@ static int battery_init(void)
 {
 	int batt_status;
 
-	return battery_status(&batt_status) ? 0 :
-		!!(batt_status & STATUS_INITIALIZED);
+	return battery_status(&batt_status) ?
+		       0 :
+		       !!(batt_status & STATUS_INITIALIZED);
 }
 
 /*
diff --git a/baseboard/hatch/build.mk b/baseboard/hatch/build.mk
index 864225f605..f98ffdcb3f 100644
--- a/baseboard/hatch/build.mk
+++ b/baseboard/hatch/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/baseboard/hatch/usb_pd_policy.c b/baseboard/hatch/usb_pd_policy.c
index a66bfefe87..6abb6e4454 100644
--- a/baseboard/hatch/usb_pd_policy.c
+++ b/baseboard/hatch/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,8 +19,8 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
diff --git a/baseboard/herobrine/baseboard.c b/baseboard/herobrine/baseboard.c
index 41d40dd7ae..fca6e9c66d 100644
--- a/baseboard/herobrine/baseboard.c
+++ b/baseboard/herobrine/baseboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/baseboard/herobrine/baseboard.h b/baseboard/herobrine/baseboard.h
index ae5b2a3d33..0782612cb8 100644
--- a/baseboard/herobrine/baseboard.h
+++ b/baseboard/herobrine/baseboard.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,12 +13,12 @@
  * The sensor stack is generating a lot of activity.
  * They can be enabled through the console command 'chan'.
  */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_HOSTCMD)))
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_HOSTCMD)))
 
 /* NPCX7 config */
-#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
-#define NPCX_TACH_SEL2    0  /* No tach. */
-#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
+#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */
+#define NPCX_TACH_SEL2 0 /* No tach. */
+#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */
 
 /* Internal SPI flash on NPCX7 */
 #define CONFIG_SPI_FLASH_REGS
@@ -140,13 +140,13 @@
 #define CONFIG_CMD_ACCEL_INFO
 
 /* PD */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY   30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY  250000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
-#define PD_OPERATING_POWER_MW   10000
-#define PD_MAX_POWER_MW         ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
-#define PD_MAX_CURRENT_MA       3000
-#define PD_MAX_VOLTAGE_MV       20000
+#define PD_OPERATING_POWER_MW 10000
+#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Chipset */
 #define CONFIG_CHIPSET_SC7280
@@ -163,56 +163,54 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_POWER_BUTTON_L	GPIO_EC_PWR_BTN_ODL
-#define GPIO_VOLUME_DOWN_L	GPIO_EC_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L	GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_LID_OPEN		GPIO_LID_OPEN_EC
-#define GPIO_SHI_CS_L		GPIO_AP_EC_SPI_CS_L
-#define GPIO_ENTERING_RW	GPIO_EC_ENTERING_RW
-#define GPIO_BATT_PRES_ODL	GPIO_EC_BATT_PRES_ODL
-#define GPIO_ENABLE_BACKLIGHT	GPIO_EC_BL_DISABLE_L
-#define GPIO_BOARD_VERSION1	GPIO_BRD_ID0
-#define GPIO_BOARD_VERSION2	GPIO_BRD_ID1
-#define GPIO_BOARD_VERSION3	GPIO_BRD_ID2
-#define GPIO_KBD_KSO2		GPIO_EC_KSO_02_INV
+#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_LID_OPEN GPIO_LID_OPEN_EC
+#define GPIO_SHI_CS_L GPIO_AP_EC_SPI_CS_L
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_BATT_PRES_ODL GPIO_EC_BATT_PRES_ODL
+#define GPIO_ENABLE_BACKLIGHT GPIO_EC_BL_DISABLE_L
+#define GPIO_BOARD_VERSION1 GPIO_BRD_ID0
+#define GPIO_BOARD_VERSION2 GPIO_BRD_ID1
+#define GPIO_BOARD_VERSION3 GPIO_BRD_ID2
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
 
 /* I2C Ports */
 #define I2C_PORT_BATTERY I2C_PORT_POWER
 #define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
 #define I2C_PORT_CHARGER I2C_PORT_POWER
-#define I2C_PORT_ACCEL   I2C_PORT_SENSOR
-#define I2C_PORT_POWER   NPCX_I2C_PORT0_0
-#define I2C_PORT_TCPC0   NPCX_I2C_PORT1_0
-#define I2C_PORT_TCPC1   NPCX_I2C_PORT2_0
-#define I2C_PORT_WLC     NPCX_I2C_PORT3_0
-#define I2C_PORT_RTC     NPCX_I2C_PORT4_1
-#define I2C_PORT_EEPROM  NPCX_I2C_PORT5_0
-#define I2C_PORT_SENSOR  NPCX_I2C_PORT7_0
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
+#define I2C_PORT_POWER NPCX_I2C_PORT0_0
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT1_0
+#define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0
+#define I2C_PORT_WLC NPCX_I2C_PORT3_0
+#define I2C_PORT_RTC NPCX_I2C_PORT4_1
+#define I2C_PORT_EEPROM NPCX_I2C_PORT5_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT7_0
 
 /* UART */
 #define CONFIG_CMD_CHARGEN
 
 /* Define the host events which are allowed to wake AP up from S3 */
-#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \
-		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) | \
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) | \
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT) | \
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC) | \
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_DEVICE))
+#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK                   \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |        \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |    \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |    \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT) |     \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC) |             \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |     \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_DEVICE))
 
 /* And the MKBP events */
 #ifdef HAS_TASK_KEYSCAN
-#define CONFIG_MKBP_EVENT_WAKEUP_MASK \
-		(BIT(EC_MKBP_EVENT_KEY_MATRIX) | \
-		 BIT(EC_MKBP_EVENT_HOST_EVENT) | \
-		 BIT(EC_MKBP_EVENT_SENSOR_FIFO))
+#define CONFIG_MKBP_EVENT_WAKEUP_MASK                                    \
+	(BIT(EC_MKBP_EVENT_KEY_MATRIX) | BIT(EC_MKBP_EVENT_HOST_EVENT) | \
+	 BIT(EC_MKBP_EVENT_SENSOR_FIFO))
 #else
 #define CONFIG_MKBP_EVENT_WAKEUP_MASK \
-		(BIT(EC_MKBP_EVENT_HOST_EVENT) | \
-		 BIT(EC_MKBP_EVENT_SENSOR_FIFO))
+	(BIT(EC_MKBP_EVENT_HOST_EVENT) | BIT(EC_MKBP_EVENT_SENSOR_FIFO))
 #endif
 
 #endif /* __CROS_EC_BASEBOARD_H */
diff --git a/baseboard/herobrine/build.mk b/baseboard/herobrine/build.mk
index f007fd7118..67c2e2143f 100644
--- a/baseboard/herobrine/build.mk
+++ b/baseboard/herobrine/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/baseboard/herobrine/usb_pd_policy.c b/baseboard/herobrine/usb_pd_policy.c
index 7ca2688aef..9fa725c845 100644
--- a/baseboard/herobrine/usb_pd_policy.c
+++ b/baseboard/herobrine/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,8 +12,8 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
@@ -23,10 +23,10 @@ int pd_check_vconn_swap(int port)
 
 static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT];
 #if CONFIG_USB_PD_PORT_MAX_COUNT == 1
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5};
+static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5 };
 #else
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5,
-							TYPEC_RP_1A5};
+static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5,
+							 TYPEC_RP_1A5 };
 #endif
 
 static void board_vbus_update_source_current(int port)
@@ -107,11 +107,11 @@ __override int svdm_dp_config(int port, uint32_t *payload)
 	 *  (3) plug a monitor to the port-1 dongle.
 	 */
 
-	payload[0] = VDO(USB_SID_DISPLAYPORT, 1,
-			 CMD_DP_CONFIG | VDO_OPOS(opos));
-	payload[1] = VDO_DP_CFG(pin_mode,      /* pin mode */
-				1,             /* DPv1.3 signaling */
-				2);            /* UFP connected */
+	payload[0] =
+		VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_CONFIG | VDO_OPOS(opos));
+	payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */
+				1, /* DPv1.3 signaling */
+				2); /* UFP connected */
 	return 2;
 };
 
@@ -187,8 +187,7 @@ __override int svdm_dp_attention(int port, uint32_t *payload)
 		 * because of the board USB-C topology (limited to 2
 		 * lanes DP).
 		 */
-		usb_mux_set(port, USB_PD_MUX_DOCK,
-			    USB_SWITCH_CONNECT,
+		usb_mux_set(port, USB_PD_MUX_DOCK, USB_SWITCH_CONNECT,
 			    polarity_rm_dts(pd_get_polarity(port)));
 	} else {
 		/* Disconnect the DP port selection mux. */
@@ -200,13 +199,11 @@ __override int svdm_dp_attention(int port, uint32_t *payload)
 			ppc_set_sbu(port, 0);
 
 		/* Disconnect the DP but keep the USB SS lines in TCPC chip. */
-		usb_mux_set(port, USB_PD_MUX_USB_ENABLED,
-			    USB_SWITCH_CONNECT,
+		usb_mux_set(port, USB_PD_MUX_USB_ENABLED, USB_SWITCH_CONNECT,
 			    polarity_rm_dts(pd_get_polarity(port)));
 	}
 
-	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
-	    (irq || lvl))
+	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && (irq || lvl))
 		/*
 		 * Wake up the AP.  IRQ or level high indicates a DP sink is now
 		 * present.
@@ -231,16 +228,16 @@ __override int svdm_dp_attention(int port, uint32_t *payload)
 		gpio_set_level(hpd, 1);
 
 		/* Set the minimum time delay (2ms) for the next HPD IRQ */
-		svdm_hpd_deadline[port] = get_time().val +
-			HPD_USTREAM_DEBOUNCE_LVL;
+		svdm_hpd_deadline[port] =
+			get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
 	} else if (irq & !lvl) {
 		CPRINTF("ERR:HPD:IRQ&LOW\n");
 		return 0;
 	} else {
 		gpio_set_level(hpd, lvl);
 		/* Set the minimum time delay (2ms) for the next HPD IRQ */
-		svdm_hpd_deadline[port] = get_time().val +
-			HPD_USTREAM_DEBOUNCE_LVL;
+		svdm_hpd_deadline[port] =
+			get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
 	}
 
 	return 1;
@@ -255,7 +252,7 @@ __override void svdm_exit_dp_mode(int port)
 
 		/* Signal AP for the HPD low event */
 		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 		gpio_set_level(GPIO_DP_HOT_PLUG_DET, 0);
 	}
 }
diff --git a/baseboard/herobrine/usbc_config.c b/baseboard/herobrine/usbc_config.c
index f5ee9c157d..2ebb8ae029 100644
--- a/baseboard/herobrine/usbc_config.c
+++ b/baseboard/herobrine/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,8 @@
 #include "console.h"
 #include "usb_pd.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 const struct charger_config_t chg_chips[] = {
 	{
diff --git a/baseboard/honeybuns/baseboard.c b/baseboard/honeybuns/baseboard.c
index e7df1b6ef4..506eb6f265 100644
--- a/baseboard/honeybuns/baseboard.c
+++ b/baseboard/honeybuns/baseboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,20 +18,17 @@
 #include "driver/tcpm/tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
 #define POWER_BUTTON_SHORT_USEC (300 * MSEC)
 #define POWER_BUTTON_LONG_USEC (5000 * MSEC)
 #define POWER_BUTTON_DEBOUNCE_USEC (30)
 
-#define BUTTON_EVT_CHANGE   BIT(0)
-#define BUTTON_EVT_INFO     BIT(1)
+#define BUTTON_EVT_CHANGE BIT(0)
+#define BUTTON_EVT_INFO BIT(1)
 
-enum power {
-	POWER_OFF,
-	POWER_ON
-};
+enum power { POWER_OFF, POWER_ON };
 
 enum button {
 	BUTTON_RELEASE,
@@ -66,7 +63,7 @@ __maybe_unused static void board_power_sequence(int enable)
 	int i;
 
 	if (enable) {
-		for(i = 0; i < board_power_seq_count; i++) {
+		for (i = 0; i < board_power_seq_count; i++) {
 			gpio_set_level(board_power_seq[i].signal,
 				       board_power_seq[i].level);
 			CPRINTS("power seq: rail = %d", i);
@@ -74,7 +71,7 @@ __maybe_unused static void board_power_sequence(int enable)
 				msleep(board_power_seq[i].delay_ms);
 		}
 	} else {
-		for(i = board_power_seq_count - 1; i >= 0; i--) {
+		for (i = board_power_seq_count - 1; i >= 0; i--) {
 			gpio_set_level(board_power_seq[i].signal,
 				       !board_power_seq[i].level);
 			CPRINTS("sequence[%d]: level = %d", i,
@@ -89,20 +86,16 @@ __maybe_unused static void board_power_sequence(int enable)
 /******************************************************************************/
 /* I2C port map configuration */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "i2c1",
-		.port = I2C_PORT_I2C1,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C1_SCL,
-		.sda  = GPIO_EC_I2C1_SDA
-	},
-	{
-		.name = "i2c3",
-		.port = I2C_PORT_I2C3,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C3_SCL,
-		.sda  = GPIO_EC_I2C3_SDA
-	},
+	{ .name = "i2c1",
+	  .port = I2C_PORT_I2C1,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C1_SCL,
+	  .sda = GPIO_EC_I2C1_SDA },
+	{ .name = "i2c3",
+	  .port = I2C_PORT_I2C3,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C3_SCL,
+	  .sda = GPIO_EC_I2C3_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -246,7 +239,7 @@ static void baseboard_init(void)
 
 #else
 	/* Set up host port usbc to present Rd on CC lines */
-	if(baseboard_usbc_init(USB_PD_PORT_HOST))
+	if (baseboard_usbc_init(USB_PD_PORT_HOST))
 		CPRINTS("usbc: Failed to set up sink path");
 	else
 		CPRINTS("usbc: sink path configure success!");
@@ -381,11 +374,11 @@ void power_button_task(void *u)
 			 * Default wait state: Only need to check if the button
 			 * is pressed and start the short press timer.
 			 */
-			if (evt & BUTTON_EVT_CHANGE && button_level ==
-			    BUTTON_PRESSED_LEVEL) {
+			if (evt & BUTTON_EVT_CHANGE &&
+			    button_level == BUTTON_PRESSED_LEVEL) {
 				state = BUTTON_PRESS;
 				timer_us = (POWER_BUTTON_SHORT_USEC -
-						 POWER_BUTTON_DEBOUNCE_USEC);
+					    POWER_BUTTON_DEBOUNCE_USEC);
 			}
 			break;
 		case BUTTON_PRESS:
@@ -399,7 +392,7 @@ void power_button_task(void *u)
 			} else {
 				/* Start long press timer */
 				timer_us = POWER_BUTTON_LONG_USEC -
-					POWER_BUTTON_SHORT_USEC;
+					   POWER_BUTTON_SHORT_USEC;
 				/*
 				 * If dock is currently off, then change to the
 				 * power on state. If dock is already on, then
@@ -407,7 +400,7 @@ void power_button_task(void *u)
 				 */
 				if (dock_state == POWER_OFF) {
 					baseboard_power_on();
-				        state = BUTTON_PRESS_POWER_ON;
+					state = BUTTON_PRESS_POWER_ON;
 				} else {
 					state = BUTTON_PRESS_SHORT;
 				}
@@ -474,9 +467,8 @@ void baseboard_power_button_evt(int level)
 			   POWER_BUTTON_DEBOUNCE_USEC);
 }
 
-static int command_pwr_btn(int argc, char **argv)
+static int command_pwr_btn(int argc, const char **argv)
 {
-
 	if (argc == 1) {
 		task_set_event(TASK_ID_POWER_BUTTON, BUTTON_EVT_INFO);
 		return EC_SUCCESS;
@@ -494,8 +486,7 @@ static int command_pwr_btn(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(pwr_btn, command_pwr_btn,
-			"<on|off|mf>",
+DECLARE_CONSOLE_COMMAND(pwr_btn, command_pwr_btn, "<on|off|mf>",
 			"Simulate Power Button Press");
 
 #endif
diff --git a/baseboard/honeybuns/baseboard.h b/baseboard/honeybuns/baseboard.h
index a22be156fe..4dd218f57d 100644
--- a/baseboard/honeybuns/baseboard.h
+++ b/baseboard/honeybuns/baseboard.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -40,30 +40,30 @@
 /* Do not use a dedicated PSTATE bank */
 #undef CONFIG_FLASH_PSTATE_BANK
 
-#define CONFIG_SHAREDLIB_SIZE	0
+#define CONFIG_SHAREDLIB_SIZE 0
 
-#define CONFIG_RO_MEM_OFF	0
-#define CONFIG_RO_STORAGE_OFF	0
-#define CONFIG_RO_SIZE		(64*1024)
+#define CONFIG_RO_MEM_OFF 0
+#define CONFIG_RO_STORAGE_OFF 0
+#define CONFIG_RO_SIZE (64 * 1024)
 
-#define CONFIG_RW_MEM_OFF	(CONFIG_RO_SIZE + CONFIG_RO_MEM_OFF)
-#define CONFIG_RW_STORAGE_OFF	0
-#define CONFIG_RW_SIZE		(CONFIG_FLASH_SIZE_BYTES - \
-				(CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF))
+#define CONFIG_RW_MEM_OFF (CONFIG_RO_SIZE + CONFIG_RO_MEM_OFF)
+#define CONFIG_RW_STORAGE_OFF 0
+#define CONFIG_RW_SIZE \
+	(CONFIG_FLASH_SIZE_BYTES - (CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF))
 
-#define CONFIG_EC_PROTECTED_STORAGE_OFF		CONFIG_RO_MEM_OFF
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE	CONFIG_RO_SIZE
-#define CONFIG_EC_WRITABLE_STORAGE_OFF		CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE		CONFIG_RW_SIZE
+#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF
+#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE
+#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE
 
-#define CONFIG_WP_STORAGE_OFF		CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE		CONFIG_EC_PROTECTED_STORAGE_SIZE
+#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
+#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
 
 /* 48 MHz SYSCLK clock frequency */
 #define CPU_CLOCK 48000000
 #define CONFIG_STM_HWTIMER32
 #define TIM_CLOCK32 2
-#define TIM_CLOCK_MSB  3
+#define TIM_CLOCK_MSB 3
 #define TIM_CLOCK_LSB 15
 #define TIM_WATCHDOG 7
 
@@ -80,7 +80,7 @@
 #define CONFIG_UART_TX_DMA_PH DMAMUX_REQ_USART3_TX
 
 /* CBI Configs */
-#define I2C_ADDR_EEPROM_FLAGS   0x50
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 #define CONFIG_CBI_EEPROM
 #define CONFIG_BOARD_VERSION_CBI
 #define CONFIG_CMD_CBI
@@ -101,12 +101,12 @@
 #define CONFIG_USB_MS_EXTENDED_COMPAT_ID_DESCRIPTOR
 
 /* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL		0
-#define USB_EP_UPDATE		1
-#define USB_EP_COUNT		2
+#define USB_EP_CONTROL 0
+#define USB_EP_UPDATE 1
+#define USB_EP_COUNT 2
 
-#define USB_IFACE_UPDATE	0
-#define USB_IFACE_COUNT		1
+#define USB_IFACE_UPDATE 0
+#define USB_IFACE_COUNT 1
 
 #ifndef __ASSEMBLER__
 /* USB string indexes */
@@ -197,14 +197,14 @@ enum usb_strings {
 #define CONFIG_SHA256
 
 /* Define typical operating power and max power. */
-#define PD_MAX_VOLTAGE_MV     5000
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_POWER_MW       15000
+#define PD_MAX_VOLTAGE_MV 5000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_POWER_MW 15000
 #define PD_OPERATING_POWER_MW 15000
 
 /* TODO(b:147314141): Verify these timings */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000	/* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	250000	/* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* I2C Bus Configuration */
 #define CONFIG_I2C
@@ -216,8 +216,8 @@ enum usb_strings {
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_ENTERING_RW	GPIO_EC_ENTERING_RW
-#define GPIO_WP_L		GPIO_EC_WP_L
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_WP_L GPIO_EC_WP_L
 
 #ifndef __ASSEMBLER__
 
@@ -226,8 +226,8 @@ enum usb_strings {
 
 struct power_seq {
 	enum gpio_signal signal; /* power/reset gpio_signal to control */
-	int level;               /* level to set in power sequence */
-	unsigned int delay_ms;   /* delay (in msec) after setting gpio_signal */
+	int level; /* level to set in power sequence */
+	unsigned int delay_ms; /* delay (in msec) after setting gpio_signal */
 };
 
 enum mf_preference {
@@ -239,9 +239,7 @@ enum mf_preference {
  * This is required as adc_channel is included in adc.h which ends up being
  * included when TCPMv2 functions are included
  */
-enum adc_channel {
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_CH_COUNT };
 
 extern const struct power_seq board_power_seq[];
 extern const size_t board_power_seq_count;
@@ -279,7 +277,6 @@ int baseboard_config_usbc_usb3_ppc(void);
  */
 void baseboard_usb3_check_state(void);
 
-
 /*
  * Set MST_LANE_CONTROL gpio to match the DP pin configuration selected
  * by the host in the DP Configure SVDM message.
@@ -323,7 +320,7 @@ int c1_ps8805_is_sourcing_vbus(int port);
  * @param port: The Type-C port number.
  * @param enable: 1: Turn on VBUS, 0: turn off VBUS.
  * @return EC_SUCCESS on success, error otherwise.
-	 */
+ */
 int c1_ps8805_vbus_source_enable(int port, int enable);
 
 #endif /* !__ASSEMBLER__ */
diff --git a/baseboard/honeybuns/build.mk b/baseboard/honeybuns/build.mk
index 2868911925..57e93b0587 100644
--- a/baseboard/honeybuns/build.mk
+++ b/baseboard/honeybuns/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/baseboard/honeybuns/usb_pd_policy.c b/baseboard/honeybuns/usb_pd_policy.c
index ab95a7f9b6..956a73e7fb 100644
--- a/baseboard/honeybuns/usb_pd_policy.c
+++ b/baseboard/honeybuns/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,45 +21,46 @@
 #include "usb_tc_sm.h"
 #include "usbc_ppc.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 #define MP4245_VOLTAGE_WINDOW BIT(2)
 #define MP4245_VOLTAGE_WINDOW_MASK (MP4245_VOLTAGE_WINDOW - 1)
 
-#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\
-			 PDO_FIXED_COMM_CAP | PDO_FIXED_UNCONSTRAINED)
+#define PDO_FIXED_FLAGS                                                   \
+	(PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP | PDO_FIXED_COMM_CAP | \
+	 PDO_FIXED_UNCONSTRAINED)
 
 /* Voltage indexes for the PDOs */
 enum volt_idx {
-	PDO_IDX_5V   = 0,
-	PDO_IDX_9V   = 1,
-	PDO_IDX_15V  = 2,
-	PDO_IDX_20V  = 3,
+	PDO_IDX_5V = 0,
+	PDO_IDX_9V = 1,
+	PDO_IDX_15V = 2,
+	PDO_IDX_20V = 3,
 	PDO_IDX_COUNT
 };
 
 /* PDOs */
 const uint32_t pd_src_host_pdo[] = {
-	[PDO_IDX_5V]  = PDO_FIXED(5000,   3000, PDO_FIXED_FLAGS),
-	[PDO_IDX_9V]  = PDO_FIXED(9000,   3000, 0),
-	[PDO_IDX_15V]  = PDO_FIXED(15000, 3000, 0),
-	[PDO_IDX_20V]  = PDO_FIXED(20000, 3000, 0),
+	[PDO_IDX_5V] = PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS),
+	[PDO_IDX_9V] = PDO_FIXED(9000, 3000, 0),
+	[PDO_IDX_15V] = PDO_FIXED(15000, 3000, 0),
+	[PDO_IDX_20V] = PDO_FIXED(20000, 3000, 0),
 };
 BUILD_ASSERT(ARRAY_SIZE(pd_src_host_pdo) == PDO_IDX_COUNT);
 
 #ifdef BOARD_C1_1A5_LIMIT
 const uint32_t pd_src_display_pdo[] = {
-	[PDO_IDX_5V]  = PDO_FIXED(5000,   1500, PDO_FIXED_FLAGS),
+	[PDO_IDX_5V] = PDO_FIXED(5000, 1500, PDO_FIXED_FLAGS),
 };
 #else
 const uint32_t pd_src_display_pdo[] = {
-	[PDO_IDX_5V]  = PDO_FIXED(5000,   3000, PDO_FIXED_FLAGS),
+	[PDO_IDX_5V] = PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS),
 };
 #endif
 
 const uint32_t pd_snk_pdo[] = {
-	[PDO_IDX_5V]  = PDO_FIXED(5000,   0, PDO_FIXED_FLAGS),
+	[PDO_IDX_5V] = PDO_FIXED(5000, 0, PDO_FIXED_FLAGS),
 };
 const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
 
@@ -68,13 +69,12 @@ static int src_host_pdo_cnt_override;
 #define PD_DR_SWAP_ATTEMPT_MAX 3
 static int pd_dr_swap_attempt_count[CONFIG_USB_PD_PORT_MAX_COUNT];
 
-static int command_hostpdo(int argc, char **argv)
+static int command_hostpdo(int argc, const char **argv)
 {
 	char *e;
 	int limit;
 
 	if (argc >= 2) {
-
 		limit = strtoi(argv[1], &e, 10);
 		if ((limit < 0) || (limit > PDO_IDX_COUNT))
 			return EC_ERROR_PARAM1;
@@ -85,8 +85,7 @@ static int command_hostpdo(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(hostpdo, command_hostpdo,
-			"<0|1|2|3|4>",
+DECLARE_CONSOLE_COMMAND(hostpdo, command_hostpdo, "<0|1|2|3|4>",
 			"Limit number of PDOs for C0");
 
 int dpm_get_source_pdo(const uint32_t **src_pdo, const int port)
@@ -94,7 +93,7 @@ int dpm_get_source_pdo(const uint32_t **src_pdo, const int port)
 	int pdo_cnt = 0;
 
 	if (port == USB_PD_PORT_HOST) {
-		*src_pdo =  pd_src_host_pdo;
+		*src_pdo = pd_src_host_pdo;
 		pdo_cnt = ARRAY_SIZE(pd_src_host_pdo);
 		/*
 		 * This override is only active via a console command. Only used
@@ -105,7 +104,7 @@ int dpm_get_source_pdo(const uint32_t **src_pdo, const int port)
 		if (src_host_pdo_cnt_override)
 			pdo_cnt = src_host_pdo_cnt_override;
 	} else {
-		*src_pdo =  pd_src_display_pdo;
+		*src_pdo = pd_src_display_pdo;
 		pdo_cnt = ARRAY_SIZE(pd_src_display_pdo);
 	}
 
@@ -118,15 +117,15 @@ int dpm_get_source_pdo(const uint32_t **src_pdo, const int port)
  * 1) If port == 0 and port data role is DFP, transition to pe_drs_send_swap
  * 2) If port == 1 and port data role is UFP, transition to pe_drs_send_swap
  */
-__override bool port_discovery_dr_swap_policy(int port,
-			enum pd_data_role dr, bool dr_swap_flag)
+__override bool port_discovery_dr_swap_policy(int port, enum pd_data_role dr,
+					      bool dr_swap_flag)
 {
 	/*
 	 * Port0: test if role is DFP
 	 * Port1: test if role is UFP
 	 */
-	enum pd_data_role role_test =
-		(port == USB_PD_PORT_HOST) ? PD_ROLE_DFP : PD_ROLE_UFP;
+	enum pd_data_role role_test = (port == USB_PD_PORT_HOST) ? PD_ROLE_DFP :
+								   PD_ROLE_UFP;
 
 	/*
 	 * Request data role swap if not in the port's desired data role and if
@@ -135,8 +134,8 @@ __override bool port_discovery_dr_swap_policy(int port,
 	 * rejects data role swap requests (eg compliance tester), want to limit
 	 * how many DR swap requests are attempted.
 	 */
-	if (dr == role_test && (pd_dr_swap_attempt_count[port]++ <
-				PD_DR_SWAP_ATTEMPT_MAX))
+	if (dr == role_test &&
+	    (pd_dr_swap_attempt_count[port]++ < PD_DR_SWAP_ATTEMPT_MAX))
 		return true;
 
 	/* Do not perform a DR swap */
@@ -148,8 +147,7 @@ __override bool port_discovery_dr_swap_policy(int port,
  *
  * 1) No need to Vconn swap.  This board does not require any cable information.
  */
-__override bool port_discovery_vconn_swap_policy(int port,
-			bool vconn_swap_flag)
+__override bool port_discovery_vconn_swap_policy(int port, bool vconn_swap_flag)
 {
 	return false;
 }
@@ -193,8 +191,7 @@ void pd_power_supply_reset(int port)
 		 * (fixed 5V SRC_CAP) so VBUS is ready to be applied at the next
 		 * attached.src condition.
 		 */
-		pd_extract_pdo_power(pd_src_host_pdo[0], &ma, &mv,
-				     &unused_mv);
+		pd_extract_pdo_power(pd_src_host_pdo[0], &ma, &mv, &unused_mv);
 		mp4245_set_voltage_out(mv);
 		/* Ensure voltage is back to 5V */
 		pd_transition_voltage(1);
@@ -243,8 +240,7 @@ void pd_transition_voltage(int idx)
 	 * by the PDO requested by sink. Note that USB PD uses idx = 1 for 1st
 	 * PDO of SRC_CAP which must always be 5V fixed supply.
 	 */
-	pd_extract_pdo_power(pd_src_host_pdo[idx - 1], &ma, &target_mv,
-			     &mv);
+	pd_extract_pdo_power(pd_src_host_pdo[idx - 1], &ma, &target_mv, &mv);
 
 	/* Initialize sample delay buffer */
 	for (i = 0; i < MP4245_VOLTAGE_WINDOW; i++)
@@ -327,11 +323,9 @@ int board_vbus_source_enabled(int port)
 void pd_set_input_current_limit(int port, uint32_t max_ma,
 				uint32_t supply_voltage)
 {
-
 }
 
-int pd_check_data_swap(int port,
-	enum pd_data_role data_role)
+int pd_check_data_swap(int port, enum pd_data_role data_role)
 {
 	int swap = 0;
 
@@ -345,7 +339,6 @@ int pd_check_data_swap(int port,
 
 int pd_check_power_swap(int port)
 {
-
 	if (pd_get_power_role(port) == PD_ROLE_SINK)
 		return 1;
 
@@ -394,7 +387,7 @@ static void usb_tc_disconnect(void)
 DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, usb_tc_disconnect, HOOK_PRIO_DEFAULT);
 
 __override bool pd_can_charge_from_device(int port, const int pdo_cnt,
-				      const uint32_t *pdos)
+					  const uint32_t *pdos)
 {
 	/*
 	 * This function is called to determine if this port can be charged by
@@ -421,22 +414,17 @@ const uint32_t vdo_idh = VDO_IDH(0, /* data caps as USB host */
 				 USB_VID_GOOGLE);
 
 static const uint32_t vdo_idh_rev30 = VDO_IDH_REV30(
-				 0, /* Data caps as USB host     */
-				 1, /* Data caps as USB device   */
-				 IDH_PTYPE_HUB,
-				 1, /* Supports alt modes */
-				 IDH_PTYPE_DFP_UNDEFINED,
-				 USB_TYPEC_RECEPTACLE,
-				 USB_VID_GOOGLE);
+	0, /* Data caps as USB host     */
+	1, /* Data caps as USB device   */
+	IDH_PTYPE_HUB, 1, /* Supports alt modes */
+	IDH_PTYPE_DFP_UNDEFINED, USB_TYPEC_RECEPTACLE, USB_VID_GOOGLE);
 
 const uint32_t vdo_product = VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV);
 
-static const uint32_t vdo_ufp1 = VDO_UFP1(
-				   (VDO_UFP1_CAPABILITY_USB20
-				   | VDO_UFP1_CAPABILITY_USB32),
-				   USB_TYPEC_RECEPTACLE,
-				   VDO_UFP1_ALT_MODE_RECONFIGURE,
-				   USB_R30_SS_U32_U40_GEN2);
+static const uint32_t vdo_ufp1 =
+	VDO_UFP1((VDO_UFP1_CAPABILITY_USB20 | VDO_UFP1_CAPABILITY_USB32),
+		 USB_TYPEC_RECEPTACLE, VDO_UFP1_ALT_MODE_RECONFIGURE,
+		 USB_R30_SS_U32_U40_GEN2);
 
 static int svdm_response_identity(int port, uint32_t *payload)
 {
@@ -479,14 +467,17 @@ static int svdm_response_svids(int port, uint32_t *payload)
 
 #define OPOS_DP 1
 
-const uint32_t vdo_dp_modes[1] =  {
+const uint32_t vdo_dp_modes[1] = {
 	VDO_MODE_DP(/* Must support C and E. D is required for 2 lanes */
 		    MODE_DP_PIN_C | MODE_DP_PIN_D | MODE_DP_PIN_E,
-		    0, /* DFP pin cfg supported */
-		    0,		   /* usb2.0 signalling in AMode may be req */
-		    CABLE_RECEPTACLE,	   /* its a receptacle */
-		    MODE_DP_V13,   /* DPv1.3 Support, no Gen2 */
-		    MODE_DP_SNK)   /* Its a sink only */
+		    0, /* DFP pin
+			  cfg
+			  supported
+			*/
+		    0, /* usb2.0 signalling in AMode may be req */
+		    CABLE_RECEPTACLE, /* its a receptacle */
+		    MODE_DP_V13, /* DPv1.3 Support, no Gen2 */
+		    MODE_DP_SNK) /* Its a sink only */
 };
 
 static int svdm_response_modes(int port, uint32_t *payload)
@@ -508,13 +499,12 @@ static int amode_dp_status(int port, uint32_t *payload)
 	if (opos != OPOS_DP)
 		return 0; /* nak */
 
-	payload[1] = VDO_DP_STATUS(0,		/* IRQ_HPD */
-				   (hpd == 1),	/* HPD_HI|LOW */
-				   0,		/* request exit DP */
-				   0,		/* request exit USB */
-				   mf,		/* MF pref */
-				   vdm_is_dp_enabled(port),
-				   0,		/* power low */
+	payload[1] = VDO_DP_STATUS(0, /* IRQ_HPD */
+				   (hpd == 1), /* HPD_HI|LOW */
+				   0, /* request exit DP */
+				   0, /* request exit USB */
+				   mf, /* MF pref */
+				   vdm_is_dp_enabled(port), 0, /* power low */
 				   0x2);
 	return 2;
 }
@@ -536,8 +526,8 @@ static void svdm_configure_demux(int port, int enable, int mf)
 		 * stored in bit 0 of CBI fw_config.
 		 */
 		baseboard_set_mst_lane_control(mf);
-		CPRINTS("DP[%d]: DFP-D selected pin config %s",
-			port, mf ? "D" : "C");
+		CPRINTS("DP[%d]: DFP-D selected pin config %s", port,
+			mf ? "D" : "C");
 	} else {
 		demux &= ~USB_PD_MUX_DP_ENABLED;
 		demux |= USB_PD_MUX_USB_ENABLED;
@@ -573,7 +563,6 @@ static int svdm_enter_mode(int port, uint32_t *payload)
 	/* SID & mode request is valid */
 	if ((PD_VDO_VID(payload[0]) == USB_SID_DISPLAYPORT) &&
 	    (PD_VDO_OPOS(payload[0]) == OPOS_DP)) {
-
 		/* Store valid object position to indicate mode is active */
 		pd_ufp_set_dp_opos(port, OPOS_DP);
 
@@ -623,8 +612,7 @@ const struct svdm_response svdm_rsp = {
 	.exit_mode = &svdm_exit_mode,
 };
 
-int pd_custom_vdm(int port, int cnt, uint32_t *payload,
-		  uint32_t **rpayload)
+int pd_custom_vdm(int port, int cnt, uint32_t *payload, uint32_t **rpayload)
 {
 	/* We don't support, so ignore this message */
 	return 0;
diff --git a/baseboard/honeybuns/usbc_support.c b/baseboard/honeybuns/usbc_support.c
index c03e94f076..db68ad527c 100644
--- a/baseboard/honeybuns/usbc_support.c
+++ b/baseboard/honeybuns/usbc_support.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,8 +23,8 @@
 #include "registers.h"
 #include "ucpd-stm32gx.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
 enum usbc_states {
 	UNATTACHED_SNK,
@@ -39,7 +39,7 @@ static int usbc_vbus;
 static enum tcpc_cc_voltage_status cc1_v;
 static enum tcpc_cc_voltage_status cc2_v;
 
-__maybe_unused static __const_data const char * const usbc_state_names[] = {
+__maybe_unused static __const_data const char *const usbc_state_names[] = {
 	[UNATTACHED_SNK] = "Unattached.SNK",
 	[ATTACH_WAIT_SNK] = "AttachWait.SNK",
 	[ATTACHED_SNK] = "Attached.SNK",
@@ -48,17 +48,13 @@ __maybe_unused static __const_data const char * const usbc_state_names[] = {
 static int read_reg(uint8_t port, int reg, int *regval)
 {
 	return i2c_read8(ppc_chips[port].i2c_port,
-			 ppc_chips[port].i2c_addr_flags,
-			 reg,
-			 regval);
+			 ppc_chips[port].i2c_addr_flags, reg, regval);
 }
 
 static int write_reg(uint8_t port, int reg, int regval)
 {
 	return i2c_write8(ppc_chips[port].i2c_port,
-			  ppc_chips[port].i2c_addr_flags,
-			  reg,
-			  regval);
+			  ppc_chips[port].i2c_addr_flags, reg, regval);
 }
 
 static int baseboard_ppc_enable_sink_path(int port)
@@ -126,9 +122,9 @@ static void baseboard_ucpd_apply_rd(int port)
 	 */
 
 	cfgr1_reg = STM32_UCPD_CFGR1_PSC_CLK_VAL(UCPD_PSC_DIV - 1) |
-		STM32_UCPD_CFGR1_TRANSWIN_VAL(UCPD_TRANSWIN_CNT - 1) |
-		STM32_UCPD_CFGR1_IFRGAP_VAL(UCPD_IFRGAP_CNT - 1) |
-		STM32_UCPD_CFGR1_HBITCLKD_VAL(UCPD_HBIT_DIV - 1);
+		    STM32_UCPD_CFGR1_TRANSWIN_VAL(UCPD_TRANSWIN_CNT - 1) |
+		    STM32_UCPD_CFGR1_IFRGAP_VAL(UCPD_IFRGAP_CNT - 1) |
+		    STM32_UCPD_CFGR1_HBITCLKD_VAL(UCPD_HBIT_DIV - 1);
 	STM32_UCPD_CFGR1(port) = cfgr1_reg;
 
 	/* Enable ucpd  */
@@ -147,9 +143,8 @@ static void baseboard_ucpd_apply_rd(int port)
 	STM32_PWR_CR3 |= STM32_PWR_CR3_UCPD1_DBDIS;
 }
 
-
 static void baseboard_ucpd_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2)
+				  enum tcpc_cc_voltage_status *cc2)
 {
 	int vstate_cc1;
 	int vstate_cc2;
@@ -163,7 +158,7 @@ static void baseboard_ucpd_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
 	 *
 	 * vstate_cc maps directly to cc_state from tcpci spec when ANAMODE = 1,
 	 * but needs to be modified slightly for case ANAMODE = 0.
-         *
+	 *
 	 * If presenting Rp (source), then need to to a circular shift of
 	 * vstate_ccx value:
 	 *     vstate_cc | cc_state
@@ -178,9 +173,9 @@ static void baseboard_ucpd_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
 	/* Get Rp or Rd active */
 	anamode = !!(STM32_UCPD_CR(port) & STM32_UCPD_CR_ANAMODE);
 	vstate_cc1 = (sr & STM32_UCPD_SR_VSTATE_CC1_MASK) >>
-		STM32_UCPD_SR_VSTATE_CC1_SHIFT;
+		     STM32_UCPD_SR_VSTATE_CC1_SHIFT;
 	vstate_cc2 = (sr & STM32_UCPD_SR_VSTATE_CC2_MASK) >>
-		STM32_UCPD_SR_VSTATE_CC2_SHIFT;
+		     STM32_UCPD_SR_VSTATE_CC2_SHIFT;
 
 	/* Do circular shift if port == source */
 	if (anamode) {
@@ -325,10 +320,8 @@ int c1_ps8805_is_sourcing_vbus(int port)
 	return level;
 }
 
-
 int c1_ps8805_vbus_source_enable(int port, int enable)
 {
-
 	return ps8805_gpio_set_level(port, PS8805_GPIO_1, enable);
 }
 
@@ -358,12 +351,13 @@ static void baseboard_usb3_manage_vbus(void)
 		ppc_ocp_count = 0;
 
 #ifdef GPIO_USB_HUB_OCP_NOTIFY
-	/*
-	 * In the case of an OCP event on this port, the usb hub should be
-	 * notified via a GPIO signal. Following, an OCP, the attached.src state
-	 * for the usb3 only port is checked again. If it's attached, then make
-	 * sure the OCP notify signal is reset.
-	 */
+		/*
+		 * In the case of an OCP event on this port, the usb hub should
+		 * be notified via a GPIO signal. Following, an OCP, the
+		 * attached.src state for the usb3 only port is checked again.
+		 * If it's attached, then make sure the OCP notify signal is
+		 * reset.
+		 */
 		gpio_set_level(GPIO_USB_HUB_OCP_NOTIFY, 1);
 #endif
 	}
@@ -436,8 +430,9 @@ static void baseboard_usbc_usb3_handle_interrupt(void)
 			CPRINTS("usb3_ppc: VBUS OC!");
 			gpio_set_level(GPIO_USB_HUB_OCP_NOTIFY, 0);
 			if (++ppc_ocp_count < 5)
-				hook_call_deferred(&baseboard_usb3_manage_vbus_data,
-						   USB_HUB_OCP_RESET_MSEC);
+				hook_call_deferred(
+					&baseboard_usb3_manage_vbus_data,
+					USB_HUB_OCP_RESET_MSEC);
 			else
 				CPRINTS("usb3_ppc: VBUS OC limit reached!");
 		}
@@ -466,7 +461,6 @@ static void baseboard_usbc_usb3_handle_interrupt(void)
 		/* Clear the interrupt sources. */
 		write_reg(port, SN5S330_INT_TRIP_RISE_REG2, rise);
 		write_reg(port, SN5S330_INT_TRIP_FALL_REG2, fall);
-
 	}
 }
 DECLARE_DEFERRED(baseboard_usbc_usb3_handle_interrupt);
diff --git a/baseboard/intelrvp/adlrvp.c b/baseboard/intelrvp/adlrvp.c
index 4d97418d23..6f301be986 100644
--- a/baseboard/intelrvp/adlrvp.c
+++ b/baseboard/intelrvp/adlrvp.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,8 +26,8 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ##args)
 
 /* TCPC AIC GPIO Configuration */
 const struct tcpc_aic_gpio_config_t tcpc_aic_gpios[] = {
@@ -93,94 +93,123 @@ BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == CONFIG_USB_PD_PORT_MAX_COUNT);
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
 /* USB-C retimer Configuration */
-struct usb_mux usbc0_tcss_usb_mux = {
+struct usb_mux bb_retimer0_usb_mux = {
 	.usb_port = TYPE_C_PORT_0,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+	.driver = &bb_usb_retimer,
+	.hpd_update = bb_retimer_hpd_update,
+	.i2c_port = I2C_PORT_TYPEC_0,
+	.i2c_addr_flags = I2C_PORT0_BB_RETIMER_ADDR,
+};
+struct usb_mux_chain usbc0_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = TYPE_C_PORT_0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
 #if defined(HAS_TASK_PD_C1)
-struct usb_mux usbc1_tcss_usb_mux = {
+struct usb_mux bb_retimer1_usb_mux = {
 	.usb_port = TYPE_C_PORT_1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+	.driver = &bb_usb_retimer,
+	.hpd_update = bb_retimer_hpd_update,
+	.i2c_port = I2C_PORT_TYPEC_1,
+	.i2c_addr_flags = I2C_PORT1_BB_RETIMER_ADDR,
+};
+struct usb_mux_chain usbc1_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = TYPE_C_PORT_1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
 #endif
 #if defined(HAS_TASK_PD_C2)
-struct usb_mux usbc2_tcss_usb_mux = {
+struct usb_mux bb_retimer2_usb_mux = {
 	.usb_port = TYPE_C_PORT_2,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+	.driver = &bb_usb_retimer,
+	.hpd_update = bb_retimer_hpd_update,
+	.i2c_port = I2C_PORT_TYPEC_2,
+	.i2c_addr_flags = I2C_PORT2_BB_RETIMER_ADDR,
+};
+struct usb_mux_chain usbc2_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = TYPE_C_PORT_2,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
 #endif
 #if defined(HAS_TASK_PD_C3)
-struct usb_mux usbc3_tcss_usb_mux = {
-	.usb_port = TYPE_C_PORT_3,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+struct usb_mux_chain usbc3_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = TYPE_C_PORT_3,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
 #endif
 
 /* USB muxes Configuration */
-struct usb_mux usb_muxes[] = {
+struct usb_mux_chain usb_muxes[] = {
 	[TYPE_C_PORT_0] = {
-		.usb_port = TYPE_C_PORT_0,
-		.next_mux = &usbc0_tcss_usb_mux,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_TYPEC_0,
-		.i2c_addr_flags = I2C_PORT0_BB_RETIMER_ADDR,
+		.mux = &bb_retimer0_usb_mux,
+		.next = &usbc0_tcss_usb_mux,
 	},
 #if defined(HAS_TASK_PD_C1)
 	[TYPE_C_PORT_1] = {
-		.usb_port = TYPE_C_PORT_1,
-		.next_mux = &usbc1_tcss_usb_mux,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_TYPEC_1,
-		.i2c_addr_flags = I2C_PORT1_BB_RETIMER_ADDR,
+		.mux = &bb_retimer1_usb_mux,
+		.next = &usbc1_tcss_usb_mux,
 	},
 #endif
 #if defined(HAS_TASK_PD_C2)
 	[TYPE_C_PORT_2] = {
-		.usb_port = TYPE_C_PORT_2,
-		.next_mux = &usbc2_tcss_usb_mux,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_TYPEC_2,
-		.i2c_addr_flags = I2C_PORT2_BB_RETIMER_ADDR,
+		.mux = &bb_retimer2_usb_mux,
+		.next = &usbc2_tcss_usb_mux,
 	},
 #endif
 #if defined(HAS_TASK_PD_C3)
 	[TYPE_C_PORT_3] = {
-		.usb_port = TYPE_C_PORT_3,
-		.next_mux = &usbc3_tcss_usb_mux,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_TYPEC_3,
-		.i2c_addr_flags = I2C_PORT3_BB_RETIMER_ADDR,
+		.mux = &(const struct usb_mux) {
+			.usb_port = TYPE_C_PORT_3,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_TYPEC_3,
+			.i2c_addr_flags = I2C_PORT3_BB_RETIMER_ADDR,
+		},
+		.next = &usbc3_tcss_usb_mux,
 	},
 #endif
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == CONFIG_USB_PD_PORT_MAX_COUNT);
 
 /* USB Mux Configuration for Soc side BB-Retimers for Dual retimer config */
-struct usb_mux soc_side_bb_retimer0_usb_mux = {
-	.usb_port = TYPE_C_PORT_0,
-	.next_mux = &usbc0_tcss_usb_mux,
-	.driver = &bb_usb_retimer,
-	.hpd_update = bb_retimer_hpd_update,
-	.i2c_port = I2C_PORT_TYPEC_0,
-	.i2c_addr_flags = I2C_PORT0_BB_RETIMER_SOC_ADDR,
+struct usb_mux_chain soc_side_bb_retimer0_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = TYPE_C_PORT_0,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_TYPEC_0,
+			.i2c_addr_flags = I2C_PORT0_BB_RETIMER_SOC_ADDR,
+		},
+	.next = &usbc0_tcss_usb_mux,
 };
 
 #if defined(HAS_TASK_PD_C1)
-struct usb_mux soc_side_bb_retimer1_usb_mux = {
-	.usb_port = TYPE_C_PORT_1,
-	.next_mux = &usbc1_tcss_usb_mux,
-	.driver = &bb_usb_retimer,
-	.hpd_update = bb_retimer_hpd_update,
-	.i2c_port = I2C_PORT_TYPEC_1,
-	.i2c_addr_flags = I2C_PORT1_BB_RETIMER_SOC_ADDR,
+struct usb_mux_chain soc_side_bb_retimer1_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = TYPE_C_PORT_1,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_TYPEC_1,
+			.i2c_addr_flags = I2C_PORT1_BB_RETIMER_SOC_ADDR,
+		},
+	.next = &usbc1_tcss_usb_mux,
 };
 #endif
 
@@ -253,8 +282,8 @@ void board_overcurrent_event(int port, int is_overcurrented)
 {
 	/* Port 0 & 1 and 2 & 3 share same line for over current indication */
 #if defined(HAS_TASK_PD_C2)
-	enum ioex_signal oc_signal = port < TYPE_C_PORT_2 ?
-				IOEX_USB_C0_C1_OC : IOEX_USB_C2_C3_OC;
+	enum ioex_signal oc_signal = port < TYPE_C_PORT_2 ? IOEX_USB_C0_C1_OC :
+							    IOEX_USB_C2_C3_OC;
 #else
 	enum ioex_signal oc_signal = IOEX_USB_C0_C1_OC;
 #endif
@@ -340,11 +369,11 @@ void set_charger_system_voltage(void)
 		 * on AC or AC+battery
 		 */
 		if (extpower_is_present() && battery_is_present()) {
-			bq25710_set_min_system_voltage(CHARGER_SOLO,
-				battery_get_info()->voltage_min);
+			bq25710_set_min_system_voltage(
+				CHARGER_SOLO, battery_get_info()->voltage_min);
 		} else {
-			bq25710_set_min_system_voltage(CHARGER_SOLO,
-				battery_get_info()->voltage_max);
+			bq25710_set_min_system_voltage(
+				CHARGER_SOLO, battery_get_info()->voltage_max);
 		}
 		break;
 
@@ -353,8 +382,7 @@ void set_charger_system_voltage(void)
 		break;
 	}
 }
-DECLARE_HOOK(HOOK_AC_CHANGE, set_charger_system_voltage,
-		HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_AC_CHANGE, set_charger_system_voltage, HOOK_PRIO_DEFAULT);
 
 static void configure_charger(void)
 {
@@ -379,22 +407,20 @@ static void configure_retimer_usbmux(void)
 	case ADLN_LP5_ERB_SKU_BOARD_ID:
 	case ADLN_LP5_RVP_SKU_BOARD_ID:
 		/* enable TUSB1044RNQR redriver on Port0  */
-		usb_muxes[TYPE_C_PORT_0].i2c_addr_flags =
-					TUSB1064_I2C_ADDR14_FLAGS;
-		usb_muxes[TYPE_C_PORT_0].driver =
-					&tusb1064_usb_mux_driver;
-		usb_muxes[TYPE_C_PORT_0].hpd_update = tusb1044_hpd_update;
+		bb_retimer0_usb_mux.i2c_addr_flags = TUSB1064_I2C_ADDR14_FLAGS;
+		bb_retimer0_usb_mux.driver = &tusb1064_usb_mux_driver;
+		bb_retimer0_usb_mux.hpd_update = tusb1044_hpd_update;
 
 #if defined(HAS_TASK_PD_C1)
-		usb_muxes[TYPE_C_PORT_1].driver = NULL;
-		usb_muxes[TYPE_C_PORT_1].hpd_update = NULL;
+		bb_retimer1_usb_mux.driver = NULL;
+		bb_retimer1_usb_mux.hpd_update = NULL;
 #endif
 		break;
 
 	case ADLP_LP5_T4_RVP_SKU_BOARD_ID:
 		/* No retimer on Port-2 */
 #if defined(HAS_TASK_PD_C2)
-		usb_muxes[TYPE_C_PORT_2].driver = NULL;
+		bb_retimer2_usb_mux.driver = NULL;
 #endif
 		break;
 
@@ -404,15 +430,13 @@ static void configure_retimer_usbmux(void)
 		 * Change the default usb mux config on runtime to support
 		 * dual retimer topology.
 		 */
-		usb_muxes[TYPE_C_PORT_0].next_mux
-			= &soc_side_bb_retimer0_usb_mux;
+		usb_muxes[TYPE_C_PORT_0].next = &soc_side_bb_retimer0_usb_mux;
 #if defined(HAS_TASK_PD_C1)
-		usb_muxes[TYPE_C_PORT_1].next_mux
-			= &soc_side_bb_retimer1_usb_mux;
+		usb_muxes[TYPE_C_PORT_1].next = &soc_side_bb_retimer1_usb_mux;
 #endif
 		break;
 
-	/* Add additional board SKUs */
+		/* Add additional board SKUs */
 
 	default:
 		break;
diff --git a/baseboard/intelrvp/adlrvp.h b/baseboard/intelrvp/adlrvp.h
index 9e7db0081c..3e062db223 100644
--- a/baseboard/intelrvp/adlrvp.h
+++ b/baseboard/intelrvp/adlrvp.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,14 +15,14 @@
 
 /* RVP Board ids */
 #define CONFIG_BOARD_VERSION_GPIO
-#define ADLM_LP4_RVP1_SKU_BOARD_ID	0x01
-#define ADLM_LP5_RVP2_SKU_BOARD_ID	0x02
-#define ADLM_LP5_RVP3_SKU_BOARD_ID	0x03
-#define ADLN_LP5_ERB_SKU_BOARD_ID	0x06
-#define ADLN_LP5_RVP_SKU_BOARD_ID	0x07
-#define ADLP_DDR5_RVP_SKU_BOARD_ID	0x12
-#define ADLP_LP5_T4_RVP_SKU_BOARD_ID	0x13
-#define ADL_RVP_BOARD_ID(id)		((id) & 0x3F)
+#define ADLM_LP4_RVP1_SKU_BOARD_ID 0x01
+#define ADLM_LP5_RVP2_SKU_BOARD_ID 0x02
+#define ADLM_LP5_RVP3_SKU_BOARD_ID 0x03
+#define ADLN_LP5_ERB_SKU_BOARD_ID 0x06
+#define ADLN_LP5_RVP_SKU_BOARD_ID 0x07
+#define ADLP_DDR5_RVP_SKU_BOARD_ID 0x12
+#define ADLP_LP5_T4_RVP_SKU_BOARD_ID 0x13
+#define ADL_RVP_BOARD_ID(id) ((id)&0x3F)
 
 /* MECC config */
 #define CONFIG_INTEL_RVP_MECC_VERSION_1_0
@@ -35,8 +35,8 @@
 
 /* ADL has new low-power features that require extra-wide virtual wire
  * pulses. The EDS specifies 100 microseconds. */
-#undef CONFIG_ESPI_DEFAULT_VW_WIDTH_US
-#define CONFIG_ESPI_DEFAULT_VW_WIDTH_US	100
+#undef CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US
+#define CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US 100
 
 /* USB PD config */
 #if defined(HAS_TASK_PD_C3)
@@ -50,7 +50,7 @@
 #endif
 #define CONFIG_USB_MUX_VIRTUAL
 #define CONFIG_USB_MUX_TUSB1044
-#define PD_MAX_POWER_MW              100000
+#define PD_MAX_POWER_MW 100000
 
 #define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
 
@@ -58,10 +58,10 @@
 /* Support NXP PCA9675 I/O expander. */
 #define CONFIG_IO_EXPANDER
 #define CONFIG_IO_EXPANDER_PCA9675
-#define I2C_ADDR_PCA9675_TCPC_AIC_IOEX	0x21
+#define I2C_ADDR_PCA9675_TCPC_AIC_IOEX 0x21
 
 /* DC Jack charge ports */
-#undef  CONFIG_DEDICATED_CHARGE_PORT_COUNT
+#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT
 #define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1
 #define DEDICATED_CHARGE_PORT CONFIG_USB_PD_PORT_MAX_COUNT
 
@@ -69,38 +69,38 @@
 #define CONFIG_USBC_PPC_SN5S330
 #define CONFIG_USB_PD_VBUS_DETECT_PPC
 #define CONFIG_USB_PD_DISCHARGE_PPC
-#define I2C_ADDR_SN5S330_TCPC_AIC_PPC	0x40
+#define I2C_ADDR_SN5S330_TCPC_AIC_PPC 0x40
 
 /* TCPC */
 #define CONFIG_USB_PD_DISCHARGE
 #define CONFIG_USB_PD_TCPM_FUSB302
-#define I2C_ADDR_FUSB302_TCPC_AIC	0x22
+#define I2C_ADDR_FUSB302_TCPC_AIC 0x22
 
 /* Config BB retimer */
 #define CONFIG_USBC_RETIMER_INTEL_BB
 #define CONFIG_USBC_RETIMER_FW_UPDATE
 
 /* Connector side BB retimers */
-#define I2C_PORT0_BB_RETIMER_ADDR	0x56
+#define I2C_PORT0_BB_RETIMER_ADDR 0x56
 #if defined(HAS_TASK_PD_C1)
-#define I2C_PORT1_BB_RETIMER_ADDR	0x57
+#define I2C_PORT1_BB_RETIMER_ADDR 0x57
 #endif
 #if defined(HAS_TASK_PD_C2)
-#define I2C_PORT2_BB_RETIMER_ADDR	0x58
+#define I2C_PORT2_BB_RETIMER_ADDR 0x58
 #endif
 #if defined(HAS_TASK_PD_C3)
-#define I2C_PORT3_BB_RETIMER_ADDR	0x59
+#define I2C_PORT3_BB_RETIMER_ADDR 0x59
 #endif
 
 /* SOC side BB retimers (dual retimer config) */
-#define I2C_PORT0_BB_RETIMER_SOC_ADDR	0x54
+#define I2C_PORT0_BB_RETIMER_SOC_ADDR 0x54
 #if defined(HAS_TASK_PD_C1)
-#define I2C_PORT1_BB_RETIMER_SOC_ADDR	0x55
+#define I2C_PORT1_BB_RETIMER_SOC_ADDR 0x55
 #endif
 
 /* I2C EEPROM */
-#define I2C_ADDR_EEPROM_FLAGS   0x50
-#define I2C_PORT_EEPROM         I2C_PORT_PCA9555_BOARD_ID_GPIO
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+#define I2C_PORT_EEPROM I2C_PORT_PCA9555_BOARD_ID_GPIO
 
 /* Enable CBI */
 #define CONFIG_CBI_EEPROM
@@ -122,9 +122,9 @@
 #define CONFIG_USB_PD_TCPC_LOW_POWER
 
 /* Config Fan */
-#define CONFIG_FANS		1
-#define BOARD_FAN_MIN_RPM	3000
-#define BOARD_FAN_MAX_RPM	10000
+#define CONFIG_FANS 1
+#define BOARD_FAN_MIN_RPM 3000
+#define BOARD_FAN_MAX_RPM 10000
 
 /* Charger Configs */
 #define CONFIG_CHARGER_RUNTIME_CONFIG
@@ -133,15 +133,15 @@
 /* Charger chip on ADL-N */
 #define CONFIG_CHARGER_BQ25720
 #define CONFIG_CHARGER_BQ25720_VSYS_TH2_CUSTOM
-#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV	70
-#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR	10
-#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV 70
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10
 
 /* Port 80 */
-#define PORT80_I2C_ADDR		MAX695X_I2C_ADDR1_FLAGS
+#define PORT80_I2C_ADDR MAX695X_I2C_ADDR1_FLAGS
 
 /* Board Id */
-#define I2C_ADDR_PCA9555_BOARD_ID_GPIO	0x22
+#define I2C_ADDR_PCA9555_BOARD_ID_GPIO 0x22
 
 /*
  * Frequent watchdog timer resets are seen, with the
@@ -160,7 +160,7 @@
  * Support for EC_CMD_BATTERY_GET_STATIC version 1.
  */
 #define CONFIG_BATTERY_V2
-#define CONFIG_BATTERY_COUNT	1
+#define CONFIG_BATTERY_COUNT 1
 #define CONFIG_HOSTCMD_BATTERY_V2
 
 /* Config to indicate battery type doesn't auto detect */
@@ -210,7 +210,7 @@ enum adlrvp_bitbang_i2c_channel {
 	I2C_BITBANG_CHAN_IOEX_0,
 	I2C_BITBANG_CHAN_COUNT
 };
-#define I2C_BITBANG_PORT_COUNT	I2C_BITBANG_CHAN_COUNT
+#define I2C_BITBANG_PORT_COUNT I2C_BITBANG_CHAN_COUNT
 
 void espi_reset_pin_asserted_interrupt(enum gpio_signal signal);
 void extpower_interrupt(enum gpio_signal signal);
diff --git a/baseboard/intelrvp/adlrvp_battery.c b/baseboard/intelrvp/adlrvp_battery.c
index e5bf95827e..f7107cb1a4 100644
--- a/baseboard/intelrvp/adlrvp_battery.c
+++ b/baseboard/intelrvp/adlrvp_battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/baseboard/intelrvp/adlrvp_ioex_gpio.inc b/baseboard/intelrvp/adlrvp_ioex_gpio.inc
index 4519d3d853..b62dcf53a3 100644
--- a/baseboard/intelrvp/adlrvp_ioex_gpio.inc
+++ b/baseboard/intelrvp/adlrvp_ioex_gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/baseboard/intelrvp/baseboard.c b/baseboard/intelrvp/baseboard.c
index 87b43f2297..e1e0a06943 100644
--- a/baseboard/intelrvp/baseboard.c
+++ b/baseboard/intelrvp/baseboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -86,14 +86,12 @@ const static struct ec_thermal_config thermal_a = {
 };
 
 struct ec_thermal_config thermal_params[] = {
-	[TEMP_SNS_AMBIENT] = thermal_a,
-	[TEMP_SNS_BATTERY] = thermal_a,
+	[TEMP_SNS_AMBIENT] = thermal_a, [TEMP_SNS_BATTERY] = thermal_a,
 	[TEMP_SNS_DDR] = thermal_a,
 #ifdef CONFIG_PECI
 	[TEMP_SNS_PECI] = thermal_a,
 #endif
-	[TEMP_SNS_SKIN] = thermal_a,
-	[TEMP_SNS_VR] = thermal_a,
+	[TEMP_SNS_SKIN] = thermal_a,	[TEMP_SNS_VR] = thermal_a,
 };
 BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
 #endif /* CONFIG_TEMP_SENSOR */
@@ -144,12 +142,12 @@ int ioexpander_read_intelrvp_version(int *port0, int *port1)
 
 	for (i = 0; i < RVP_VERSION_READ_RETRY_CNT; i++) {
 		rv = pca9555_read(I2C_PORT_PCA9555_BOARD_ID_GPIO,
-			I2C_ADDR_PCA9555_BOARD_ID_GPIO,
-			PCA9555_CMD_INPUT_PORT_0, port0);
+				  I2C_ADDR_PCA9555_BOARD_ID_GPIO,
+				  PCA9555_CMD_INPUT_PORT_0, port0);
 
 		if (!rv && !pca9555_read(I2C_PORT_PCA9555_BOARD_ID_GPIO,
-			I2C_ADDR_PCA9555_BOARD_ID_GPIO,
-			PCA9555_CMD_INPUT_PORT_1, port1))
+					 I2C_ADDR_PCA9555_BOARD_ID_GPIO,
+					 PCA9555_CMD_INPUT_PORT_1, port1))
 			return 0;
 
 		msleep(1);
diff --git a/baseboard/intelrvp/baseboard.h b/baseboard/intelrvp/baseboard.h
index 9b497568e7..b927632fc5 100644
--- a/baseboard/intelrvp/baseboard.h
+++ b/baseboard/intelrvp/baseboard.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,22 +12,27 @@
 #include "stdbool.h"
 
 #ifdef VARIANT_INTELRVP_EC_IT8320
-	#include "ite_ec.h"
+#include "ite_ec.h"
 #elif defined(VARIANT_INTELRVP_EC_MCHP)
-	#include "mchp_ec.h"
+#include "mchp_ec.h"
 #elif defined(VARIANT_INTELRVP_EC_NPCX)
-	#include "npcx_ec.h"
+#include "npcx_ec.h"
 #else
-	#error "Define EC chip variant"
+#error "Define EC chip variant"
 #endif
 
 /*
+ * TODO: b/241322365 - Watchdog error are observed if LTO is enabled
+ * hence disabled it. Enable LTO once the fix is found.
+ */
+
+/*
  * Allow dangerous commands.
  * TODO: Remove this config before production.
  */
 #define CONFIG_SYSTEM_UNLOCKED
 
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
 #undef CONFIG_HOSTCMD_DEBUG_MODE
 
 /*
@@ -51,7 +56,7 @@
 #define CONFIG_MAX695X_SEVEN_SEGMENT_DISPLAY
 
 /* RVP ID read retry count */
-#define RVP_VERSION_READ_RETRY_CNT	2
+#define RVP_VERSION_READ_RETRY_CNT 2
 
 /* Battery */
 #define CONFIG_BATTERY_CUT_OFF
@@ -66,7 +71,7 @@
 #define CONFIG_CHARGER_INPUT_CURRENT 512
 #define CONFIG_CHARGER_SENSE_RESISTOR 5
 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
-#undef  CONFIG_EXTPOWER_DEBOUNCE_MS
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
 #define CONFIG_EXTPOWER_DEBOUNCE_MS 200
 #define CONFIG_EXTPOWER_GPIO
 #define CONFIG_TRICKLE_CHARGING
@@ -75,8 +80,8 @@
  * Don't allow the system to boot to S0 when the battery is low and unable to
  * communicate on locked systems (which haven't PD negotiated)
  */
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT	15000
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON		15001
+#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT 15000
+#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 15001
 
 /* Keyboard */
 
@@ -109,16 +114,16 @@
 
 /* USB MUX */
 #ifdef CONFIG_USB_MUX_VIRTUAL
-	#define CONFIG_HOSTCMD_LOCATE_CHIP
+#define CONFIG_HOSTCMD_LOCATE_CHIP
 #endif
 #define CONFIG_USBC_SS_MUX
 
 /* SoC / PCH */
 #define CONFIG_CHIPSET_RESET_HOOK
 #define CONFIG_HOST_INTERFACE_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S5
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S5
 #define CONFIG_MKBP_EVENT
 #define CONFIG_MKBP_USE_HOST_EVENT
 #define CONFIG_POWER_BUTTON
@@ -152,13 +157,13 @@
 
 /* Temperature sensor */
 #ifdef CONFIG_TEMP_SENSOR
-	#define CONFIG_STEINHART_HART_3V0_22K6_47K_4050B
-	#define CONFIG_TEMP_SENSOR_POWER
-	#define GPIO_TEMP_SENSOR_POWER GPIO_EN_PP3300_A
-	#define CONFIG_THERMISTOR
-	#define CONFIG_THROTTLE_AP
+#define CONFIG_STEINHART_HART_3V0_22K6_47K_4050B
+#define CONFIG_TEMP_SENSOR_POWER
+#define GPIO_TEMP_SENSOR_POWER GPIO_EN_PP3300_A
+#define CONFIG_THERMISTOR
+#define CONFIG_THROTTLE_AP
 #ifdef CONFIG_PECI
-	#define CONFIG_PECI_COMMON
+#define CONFIG_PECI_COMMON
 #endif /* CONFIG_PECI */
 #endif /* CONFIG_TEMP_SENSOR */
 
@@ -177,10 +182,7 @@
 FORWARD_DECLARE_ENUM(tcpc_rp_value);
 
 /* PWM channels */
-enum pwm_channel {
-	PWM_CH_FAN,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_FAN, PWM_CH_COUNT };
 
 /* FAN channels */
 enum fan_channel {
@@ -211,13 +213,13 @@ enum temp_sensor_id {
 };
 
 /* TODO(b:132652892): Verify the below numbers. */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* Define typical operating power */
-#define PD_OPERATING_POWER_MW  15000
-#define PD_MAX_VOLTAGE_MV      20000
-#define PD_MAX_CURRENT_MA      ((PD_MAX_POWER_MW/PD_MAX_VOLTAGE_MV) * 1000)
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_VOLTAGE_MV 20000
+#define PD_MAX_CURRENT_MA ((PD_MAX_POWER_MW / PD_MAX_VOLTAGE_MV) * 1000)
 #define DC_JACK_MAX_VOLTAGE_MV 19000
 
 /* TCPC gpios */
diff --git a/baseboard/intelrvp/build.mk b/baseboard/intelrvp/build.mk
index 21b4a7b0ec..b4cacf4cc2 100644
--- a/baseboard/intelrvp/build.mk
+++ b/baseboard/intelrvp/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/baseboard/intelrvp/chg_usb_pd.c b/baseboard/intelrvp/chg_usb_pd.c
index 1eb82b6688..95aeea0441 100644
--- a/baseboard/intelrvp/chg_usb_pd.c
+++ b/baseboard/intelrvp/chg_usb_pd.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,8 +15,8 @@
 #include "intelrvp.h"
 #endif /* CONFIG_ZEPHYR */
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 bool is_typec_port(int port)
 {
@@ -43,8 +43,8 @@ static void board_dc_jack_handle(void)
 
 	/* System is booted from DC Jack */
 	if (board_dc_jack_present()) {
-		charge_dc_jack.current = (PD_MAX_POWER_MW * 1000) /
-					DC_JACK_MAX_VOLTAGE_MV;
+		charge_dc_jack.current =
+			(PD_MAX_POWER_MW * 1000) / DC_JACK_MAX_VOLTAGE_MV;
 		charge_dc_jack.voltage = DC_JACK_MAX_VOLTAGE_MV;
 	} else {
 		charge_dc_jack.current = 0;
@@ -52,7 +52,7 @@ static void board_dc_jack_handle(void)
 	}
 
 	charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED,
-				DEDICATED_CHARGE_PORT, &charge_dc_jack);
+				     DEDICATED_CHARGE_PORT, &charge_dc_jack);
 }
 #endif
 
@@ -75,7 +75,7 @@ static void board_charge_init(void)
 	for (port = 0; port < CHARGE_PORT_COUNT; port++) {
 		for (supplier = 0; supplier < CHARGE_SUPPLIER_COUNT; supplier++)
 			charge_manager_update_charge(supplier, port,
-				&charge_init);
+						     &charge_init);
 	}
 
 #if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
@@ -88,8 +88,7 @@ int board_set_active_charge_port(int port)
 {
 	int i;
 	/* charge port is a realy physical port */
-	int is_real_port = (port >= 0 &&
-			port < CHARGE_PORT_COUNT);
+	int is_real_port = (port >= 0 && port < CHARGE_PORT_COUNT);
 	/* check if we are source vbus on that port */
 	int source = board_vbus_source_enabled(port);
 
@@ -127,9 +126,9 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
-	charge_set_input_current_limit(MAX(charge_ma,
-				CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
diff --git a/baseboard/intelrvp/chg_usb_pd_mecc_1_0.c b/baseboard/intelrvp/chg_usb_pd_mecc_1_0.c
index 38bd3cef9e..cbc61e8402 100644
--- a/baseboard/intelrvp/chg_usb_pd_mecc_1_0.c
+++ b/baseboard/intelrvp/chg_usb_pd_mecc_1_0.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,8 +19,8 @@
 #include "intelrvp.h"
 #endif /* CONFIG_ZEPHYR */
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 /* Reset PD MCU */
 void board_reset_pd_mcu(void)
@@ -97,7 +97,7 @@ void ppc_interrupt(enum gpio_signal signal)
 
 	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
 		if (tcpc_aic_gpios[i].ppc_intr_handler &&
-			signal == tcpc_aic_gpios[i].ppc_alert) {
+		    signal == tcpc_aic_gpios[i].ppc_alert) {
 			tcpc_aic_gpios[i].ppc_intr_handler(i);
 			break;
 		}
@@ -107,6 +107,6 @@ void ppc_interrupt(enum gpio_signal signal)
 void board_charging_enable(int port, int enable)
 {
 	if (ppc_vbus_sink_enable(port, enable))
-		CPRINTS("C%d: sink path %s failed",
-				port, enable ? "en" : "dis");
+		CPRINTS("C%d: sink path %s failed", port,
+			enable ? "en" : "dis");
 }
diff --git a/baseboard/intelrvp/ite_ec.c b/baseboard/intelrvp/ite_ec.c
index bafddc5f9e..76703d4f82 100644
--- a/baseboard/intelrvp/ite_ec.c
+++ b/baseboard/intelrvp/ite_ec.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -139,15 +139,15 @@ void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
 	 * enabling the VCONN on respective CC line
 	 */
 	gpio_set_level(tcpc_gpios[port].vconn.cc1_pin,
-			!tcpc_gpios[port].vconn.pin_pol);
+		       !tcpc_gpios[port].vconn.pin_pol);
 	gpio_set_level(tcpc_gpios[port].vconn.cc2_pin,
-			!tcpc_gpios[port].vconn.pin_pol);
+		       !tcpc_gpios[port].vconn.pin_pol);
 
 	if (enabled)
 		gpio_set_level((cc_pin != USBPD_CC_PIN_1) ?
-				tcpc_gpios[port].vconn.cc2_pin :
-				tcpc_gpios[port].vconn.cc1_pin,
-				tcpc_gpios[port].vconn.pin_pol);
+				       tcpc_gpios[port].vconn.cc2_pin :
+				       tcpc_gpios[port].vconn.cc1_pin,
+			       tcpc_gpios[port].vconn.pin_pol);
 #endif
 }
 #endif
diff --git a/baseboard/intelrvp/ite_ec.h b/baseboard/intelrvp/ite_ec.h
index c773a48b21..7ad147a5f9 100644
--- a/baseboard/intelrvp/ite_ec.h
+++ b/baseboard/intelrvp/ite_ec.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,13 +13,13 @@
 #define CONFIG_IT83XX_VCC_1P8V
 
 /* ADC channels */
-#define ADC_TEMP_SNS_AMBIENT_CHANNEL	CHIP_ADC_CH13
-#define ADC_TEMP_SNS_DDR_CHANNEL	CHIP_ADC_CH15
-#define ADC_TEMP_SNS_SKIN_CHANNEL	CHIP_ADC_CH6
-#define ADC_TEMP_SNS_VR_CHANNEL		CHIP_ADC_CH1
+#define ADC_TEMP_SNS_AMBIENT_CHANNEL CHIP_ADC_CH13
+#define ADC_TEMP_SNS_DDR_CHANNEL CHIP_ADC_CH15
+#define ADC_TEMP_SNS_SKIN_CHANNEL CHIP_ADC_CH6
+#define ADC_TEMP_SNS_VR_CHANNEL CHIP_ADC_CH1
 
 #ifdef CONFIG_USBC_VCONN
-	#define CONFIG_USBC_VCONN_SWAP
-	/* delay to turn on/off vconn */
+#define CONFIG_USBC_VCONN_SWAP
+/* delay to turn on/off vconn */
 #endif
 #endif /* __CROS_EC_ITE_EC_H */
diff --git a/baseboard/intelrvp/led.c b/baseboard/intelrvp/led.c
index add2ebbe43..10e4e08e63 100644
--- a/baseboard/intelrvp/led.c
+++ b/baseboard/intelrvp/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,30 +19,30 @@ const int led_charge_lvl_1 = 5;
 const int led_charge_lvl_2 = 97;
 
 struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
+	[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED, LED_INDEFINITE } },
+	[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, LED_INDEFINITE } },
+	[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+					   LED_INDEFINITE } },
+	[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+	[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+	[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+	[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+				  { LED_OFF, 1 * LED_ONE_SEC } },
+	[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+				 { EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC } },
 };
 
 const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   1 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 1 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-	EC_LED_ID_BATTERY_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED,
+					     EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -51,15 +51,15 @@ void led_set_color_power(enum ec_led_colors color)
 	if (color == EC_LED_COLOR_WHITE)
 #ifdef CONFIG_ZEPHYR
 		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_white_l),
-							LED_ON_LVL);
+				LED_ON_LVL);
 #else
 		gpio_set_level(GPIO_PWR_LED_WHITE_L, LED_ON_LVL);
 #endif /* CONFIG_ZEPHYR */
 	else
-		/* LED_OFF and unsupported colors */
+	/* LED_OFF and unsupported colors */
 #ifdef CONFIG_ZEPHYR
 		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_white_l),
-							LED_OFF_LVL);
+				LED_OFF_LVL);
 #else
 		gpio_set_level(GPIO_PWR_LED_WHITE_L, LED_OFF_LVL);
 #endif /* CONFIG_ZEPHYR */
@@ -70,32 +70,28 @@ void led_set_color_battery(enum ec_led_colors color)
 	switch (color) {
 	case EC_LED_COLOR_RED:
 #ifdef CONFIG_ZEPHYR
-		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_red_l),
-							LED_ON_LVL);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_red_l), LED_ON_LVL);
 #else
 		gpio_set_level(GPIO_BAT_LED_RED_L, LED_ON_LVL);
 #endif /* CONFIG_ZEPHYR */
 		break;
 	case EC_LED_COLOR_AMBER:
 #ifdef CONFIG_ZEPHYR
-		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_red_l),
-							LED_ON_LVL);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_red_l), LED_ON_LVL);
 #else
 		gpio_set_level(GPIO_BAT_LED_RED_L, LED_ON_LVL);
 #endif /* CONFIG_ZEPHYR */
 		break;
 	case EC_LED_COLOR_GREEN:
 #ifdef CONFIG_ZEPHYR
-		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_red_l),
-							LED_OFF_LVL);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_red_l), LED_OFF_LVL);
 #else
 		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
 #endif /* CONFIG_ZEPHYR */
 		break;
 	default: /* LED_OFF and other unsupported colors */
 #ifdef CONFIG_ZEPHYR
-		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_red_l),
-							LED_OFF_LVL);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_red_l), LED_OFF_LVL);
 #else
 		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
 #endif /* CONFIG_ZEPHYR */
diff --git a/baseboard/intelrvp/led_states.c b/baseboard/intelrvp/led_states.c
index 5f8768bdd9..8629085c4f 100644
--- a/baseboard/intelrvp/led_states.c
+++ b/baseboard/intelrvp/led_states.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -15,11 +15,11 @@
 #include "led_common.h"
 #include "led_states.h"
 
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
 
 static enum led_states led_get_state(void)
 {
-	int  charge_lvl;
+	int charge_lvl;
 	enum led_states new_state = LED_NUM_STATES;
 
 	switch (charge_get_state()) {
@@ -55,10 +55,10 @@ static enum led_states led_get_state(void)
 		new_state = STATE_CHARGING_FULL_CHARGE;
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (charge_get_flags() & CHARGE_FLAG_FORCE_IDLE)
-			new_state = STATE_FACTORY_TEST;
-		else
-			new_state = STATE_DISCHARGE_S0;
+		new_state = STATE_DISCHARGE_S0;
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		new_state = STATE_FACTORY_TEST;
 		break;
 	default:
 		/* Other states don't alter LED behavior */
@@ -88,14 +88,14 @@ static void led_update_battery(void)
 		ticks = 0;
 
 		period = led_bat_state_table[led_state][LED_PHASE_0].time +
-			led_bat_state_table[led_state][LED_PHASE_1].time;
-
+			 led_bat_state_table[led_state][LED_PHASE_1].time;
 	}
 
 	/* If this state is undefined, turn the LED off */
 	if (period == 0) {
 		CPRINTS("Undefined LED behavior for battery state %d,"
-			"turning off LED", led_state);
+			"turning off LED",
+			led_state);
 		led_set_color_battery(LED_OFF);
 		return;
 	}
@@ -104,8 +104,8 @@ static void led_update_battery(void)
 	 * Determine which phase of the state table to use. The phase is
 	 * determined if it falls within first phase time duration.
 	 */
-	phase = ticks < led_bat_state_table[led_state][LED_PHASE_0].time ?
-									0 : 1;
+	phase = ticks < led_bat_state_table[led_state][LED_PHASE_0].time ? 0 :
+									   1;
 	ticks = (ticks + 1) % period;
 
 	/* Set the color for the given state and phase */
@@ -141,14 +141,14 @@ static void led_update_power(void)
 		ticks = 0;
 
 		period = led_pwr_state_table[led_state][LED_PHASE_0].time +
-			led_pwr_state_table[led_state][LED_PHASE_1].time;
-
+			 led_pwr_state_table[led_state][LED_PHASE_1].time;
 	}
 
 	/* If this state is undefined, turn the LED off */
 	if (period == 0) {
 		CPRINTS("Undefined LED behavior for power state %d,"
-			"turning off LED", led_state);
+			"turning off LED",
+			led_state);
 		led_set_color_power(LED_OFF);
 		return;
 	}
@@ -157,8 +157,8 @@ static void led_update_power(void)
 	 * Determine which phase of the state table to use. The phase is
 	 * determined if it falls within first phase time duration.
 	 */
-	phase = ticks < led_pwr_state_table[led_state][LED_PHASE_0].time ?
-									0 : 1;
+	phase = ticks < led_pwr_state_table[led_state][LED_PHASE_0].time ? 0 :
+									   1;
 	ticks = (ticks + 1) % period;
 
 	/* Set the color for the given state and phase */
diff --git a/baseboard/intelrvp/led_states.h b/baseboard/intelrvp/led_states.h
index 907ff5c8b8..3b584c6efc 100644
--- a/baseboard/intelrvp/led_states.h
+++ b/baseboard/intelrvp/led_states.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,19 +10,15 @@
 
 #include "ec_commands.h"
 
-#define LED_INDEFINITE	UINT8_MAX
-#define LED_ONE_SEC	(1000 / HOOK_TICK_INTERVAL_MS)
-#define LED_OFF         EC_LED_COLOR_COUNT
+#define LED_INDEFINITE UINT8_MAX
+#define LED_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS)
+#define LED_OFF EC_LED_COLOR_COUNT
 
 /*
  * All LED states should have one phase defined,
  * and an additional phase can be defined for blinking
  */
-enum led_phase {
-	LED_PHASE_0,
-	LED_PHASE_1,
-	LED_NUM_PHASES
-};
+enum led_phase { LED_PHASE_0, LED_PHASE_1, LED_NUM_PHASES };
 
 /*
  * STATE_CHARGING_LVL_1 is when 0 <= charge_percentage < led_charge_level_1
@@ -51,10 +47,8 @@ struct led_descriptor {
 	uint8_t time;
 };
 
-
 /* Charging LED state table - defined in board's led.c */
-extern struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES];
+extern struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES];
 
 /* Charging LED state level 1 - defined in board's led.c */
 extern const int led_charge_lvl_1;
@@ -71,8 +65,8 @@ enum pwr_led_states {
 };
 
 /* Power LED state table - defined in board's led.c */
-extern const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES];
+extern const struct led_descriptor led_pwr_state_table[PWR_LED_NUM_STATES]
+						      [LED_NUM_PHASES];
 
 /**
  * Set battery LED color - defined in board's led.c
diff --git a/baseboard/intelrvp/mchp_ec.c b/baseboard/intelrvp/mchp_ec.c
index f1eb4678c1..7ede17569b 100644
--- a/baseboard/intelrvp/mchp_ec.c
+++ b/baseboard/intelrvp/mchp_ec.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/baseboard/intelrvp/mchp_ec.h b/baseboard/intelrvp/mchp_ec.h
index 227ccaef6d..ec1e47c030 100644
--- a/baseboard/intelrvp/mchp_ec.h
+++ b/baseboard/intelrvp/mchp_ec.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,10 +9,10 @@
 #define __CROS_EC_MCHP_EC_H
 
 /* ADC channels */
-#define ADC_TEMP_SNS_AMBIENT_CHANNEL	CHIP_ADC_CH7
-#define ADC_TEMP_SNS_DDR_CHANNEL	CHIP_ADC_CH4
-#define ADC_TEMP_SNS_SKIN_CHANNEL	CHIP_ADC_CH3
-#define ADC_TEMP_SNS_VR_CHANNEL		CHIP_ADC_CH1
+#define ADC_TEMP_SNS_AMBIENT_CHANNEL CHIP_ADC_CH7
+#define ADC_TEMP_SNS_DDR_CHANNEL CHIP_ADC_CH4
+#define ADC_TEMP_SNS_SKIN_CHANNEL CHIP_ADC_CH3
+#define ADC_TEMP_SNS_VR_CHANNEL CHIP_ADC_CH1
 
 /*
  * ADC maximum voltage is a board level configuration.
diff --git a/baseboard/intelrvp/npcx_ec.c b/baseboard/intelrvp/npcx_ec.c
index d6eca2e55b..a90442e8b1 100644
--- a/baseboard/intelrvp/npcx_ec.c
+++ b/baseboard/intelrvp/npcx_ec.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/baseboard/intelrvp/npcx_ec.h b/baseboard/intelrvp/npcx_ec.h
index 52bcb2dae6..5fe6aa9786 100644
--- a/baseboard/intelrvp/npcx_ec.h
+++ b/baseboard/intelrvp/npcx_ec.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,20 +19,20 @@ enum mft_channel {
 #endif /* __ASSEMBLER__ */
 
 /* ADC channels */
-#define ADC_MAX_MVOLT			ADC_MAX_VOLT
-#define ADC_TEMP_SNS_AMBIENT_CHANNEL	NPCX_ADC_CH3
-#define ADC_TEMP_SNS_DDR_CHANNEL	NPCX_ADC_CH4
-#define ADC_TEMP_SNS_SKIN_CHANNEL	NPCX_ADC_CH2
-#define ADC_TEMP_SNS_VR_CHANNEL		NPCX_ADC_CH1
+#define ADC_MAX_MVOLT ADC_MAX_VOLT
+#define ADC_TEMP_SNS_AMBIENT_CHANNEL NPCX_ADC_CH3
+#define ADC_TEMP_SNS_DDR_CHANNEL NPCX_ADC_CH4
+#define ADC_TEMP_SNS_SKIN_CHANNEL NPCX_ADC_CH2
+#define ADC_TEMP_SNS_VR_CHANNEL NPCX_ADC_CH1
 
 /* KSO2 is inverted */
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
 
 /* Fan */
 #define CONFIG_PWM
-#define PWN_FAN_CHANNEL		3
+#define PWN_FAN_CHANNEL 3
 
 /* GPIO64/65 are used as UART pins. */
-#define NPCX_UART_MODULE2	1
+#define NPCX_UART_MODULE2 1
 
 #endif /* __CROS_EC_NPCX_EC_H */
diff --git a/baseboard/intelrvp/usb_pd_policy_mecc_1_0.c b/baseboard/intelrvp/usb_pd_policy_mecc_1_0.c
index 8e06c9f0b3..303d176405 100644
--- a/baseboard/intelrvp/usb_pd_policy_mecc_1_0.c
+++ b/baseboard/intelrvp/usb_pd_policy_mecc_1_0.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,8 +15,8 @@
 #include "intelrvp.h"
 #endif /* CONFIG_ZEPHYR */
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_set_power_supply_ready(int port)
 {
diff --git a/baseboard/ite_evb/baseboard.c b/baseboard/ite_evb/baseboard.c
index 00459b12bc..70f50f054b 100644
--- a/baseboard/ite_evb/baseboard.c
+++ b/baseboard/ite_evb/baseboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -42,8 +42,10 @@ const struct fan_rpm fan_rpm_0 = {
 };
 
 const struct fan_t fans[] = {
-	{ .conf = &fan_conf_0,
-	  .rpm = &fan_rpm_0, },
+	{
+		.conf = &fan_conf_0,
+		.rpm = &fan_rpm_0,
+	},
 };
 BUILD_ASSERT(ARRAY_SIZE(fans) == CONFIG_FANS);
 
@@ -123,11 +125,9 @@ __override struct keyboard_scan_config keyscan_config = {
 #if defined(CONFIG_SPI_FLASH_PORT)
 /* SPI devices */
 const struct spi_device_t spi_devices[] = {
-	[CONFIG_SPI_FLASH_PORT] = {
-		.port = CONFIG_SPI_FLASH_PORT,
-		.div = 0,
-		.gpio_cs = -1
-	},
+	[CONFIG_SPI_FLASH_PORT] = { .port = CONFIG_SPI_FLASH_PORT,
+				    .div = 0,
+				    .gpio_cs = -1 },
 };
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 #endif
@@ -139,9 +139,8 @@ static void board_init(void)
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
 /* Wake-up pins for hibernate */
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_POWER_BUTTON_L, GPIO_LID_OPEN
-};
+const enum gpio_signal hibernate_wake_pins[] = { GPIO_POWER_BUTTON_L,
+						 GPIO_LID_OPEN };
 const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 
 /*
diff --git a/baseboard/ite_evb/baseboard.h b/baseboard/ite_evb/baseboard.h
index 23b3f80fba..e16e708078 100644
--- a/baseboard/ite_evb/baseboard.h
+++ b/baseboard/ite_evb/baseboard.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/baseboard/ite_evb/build.mk b/baseboard/ite_evb/build.mk
index 507222e6b3..38a49ff8b6 100644
--- a/baseboard/ite_evb/build.mk
+++ b/baseboard/ite_evb/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/baseboard/ite_evb/usb_pd_pdo.c b/baseboard/ite_evb/usb_pd_pdo.c
index 24cbc8b996..0da735e458 100644
--- a/baseboard/ite_evb/usb_pd_pdo.c
+++ b/baseboard/ite_evb/usb_pd_pdo.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,8 +7,9 @@
 #include "usb_pd.h"
 #include "usb_pd_pdo.h"
 
-#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\
-			 PDO_FIXED_UNCONSTRAINED  | PDO_FIXED_COMM_CAP)
+#define PDO_FIXED_FLAGS                                                        \
+	(PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP | PDO_FIXED_UNCONSTRAINED | \
+	 PDO_FIXED_COMM_CAP)
 
 const uint32_t pd_src_pdo[] = {
 	PDO_FIXED(5000, 1500, PDO_FIXED_FLAGS),
diff --git a/baseboard/ite_evb/usb_pd_pdo.h b/baseboard/ite_evb/usb_pd_pdo.h
index ce3300cc7d..4b19ca32d3 100644
--- a/baseboard/ite_evb/usb_pd_pdo.h
+++ b/baseboard/ite_evb/usb_pd_pdo.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/baseboard/ite_evb/usb_pd_policy.c b/baseboard/ite_evb/usb_pd_policy.c
index b5462bd1e2..71af9d2b1c 100644
--- a/baseboard/ite_evb/usb_pd_policy.c
+++ b/baseboard/ite_evb/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,8 +20,8 @@
 #include "usb_mux.h"
 #include "usb_pd_pdo.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_is_max_request_allowed(void)
 {
@@ -62,7 +62,6 @@ void pd_power_supply_reset(int port)
 	board_pd_vbus_ctrl(port, 0);
 }
 
-
 __override int pd_check_data_swap(int port, enum pd_data_role data_role)
 {
 	/* Always allow data swap: we can be DFP or UFP for USB */
@@ -107,7 +106,7 @@ __override void svdm_exit_dp_mode(int port)
 }
 
 __override int pd_custom_vdm(int port, int cnt, uint32_t *payload,
-				uint32_t **rpayload)
+			     uint32_t **rpayload)
 {
 	/* Return length 0, means nothing needn't tx */
 	return 0;
diff --git a/baseboard/kalista/baseboard.c b/baseboard/kalista/baseboard.c
index b06547106a..e929e5449c 100644
--- a/baseboard/kalista/baseboard.c
+++ b/baseboard/kalista/baseboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -48,8 +48,8 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static uint8_t board_version;
 static uint32_t oem;
@@ -99,14 +99,15 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* Vbus sensing (1/10 voltage divider). */
-	[ADC_VBUS] = {"VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
+	[ADC_VBUS] = { "VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT * 10,
+		       ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* TODO: Verify fan control and mft */
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_FAN_PWR_EN,
 };
@@ -123,46 +124,36 @@ const struct fan_t fans[] = {
 BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
 
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN },
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
-const struct i2c_port_t i2c_ports[]  = {
-	{
-		.name = "tcpc",
-		.port = I2C_PORT_TCPC0,
-		.kbps = 400,
-		.scl  = GPIO_I2C0_0_SCL,
-		.sda  = GPIO_I2C0_0_SDA
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl  = GPIO_I2C0_1_SCL,
-		.sda  = GPIO_I2C0_1_SDA
-	},
-	{
-		.name = "backlight",
-		.port = I2C_PORT_BACKLIGHT,
-		.kbps = 100,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	},
-	{
-		.name = "pmic",
-		.port = I2C_PORT_PMIC,
-		.kbps = 400,
-		.scl  = GPIO_I2C2_SCL,
-		.sda  = GPIO_I2C2_SDA
-	},
-	{
-		.name = "thermal",
-		.port = I2C_PORT_THERMAL,
-		.kbps = 400,
-		.scl  = GPIO_I2C3_SCL,
-		.sda  = GPIO_I2C3_SDA
-	},
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "tcpc",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_0_SCL,
+	  .sda = GPIO_I2C0_0_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_1_SCL,
+	  .sda = GPIO_I2C0_1_SDA },
+	{ .name = "backlight",
+	  .port = I2C_PORT_BACKLIGHT,
+	  .kbps = 100,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "pmic",
+	  .port = I2C_PORT_PMIC,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "thermal",
+	  .port = I2C_PORT_THERMAL,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -186,12 +177,15 @@ static int ps8751_tune_mux(const struct usb_mux *me)
 	return EC_SUCCESS;
 }
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-		.board_init = &ps8751_tune_mux,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+				.board_init = &ps8751_tune_mux,
+			},
 	},
 };
 
@@ -234,14 +228,14 @@ void board_tcpc_init(void)
 	 */
 	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
 		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
 
 uint16_t tcpc_get_alert_status(void)
 {
 	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL) &&
-			gpio_get_level(GPIO_USB_C0_PD_RST_ODL))
+	    gpio_get_level(GPIO_USB_C0_PD_RST_ODL))
 		return PD_STATUS_TCPC_ALERT_0;
 	return 0;
 }
@@ -254,10 +248,10 @@ uint16_t tcpc_get_alert_status(void)
  *     src/mainboard/google/${board}/acpi/dptf.asl
  */
 const struct temp_sensor_t temp_sensors[] = {
-	{"TMP431_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-			TMP432_IDX_LOCAL},
-	{"TMP431_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-			TMP432_IDX_REMOTE1},
+	{ "TMP431_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
+	  TMP432_IDX_LOCAL },
+	{ "TMP431_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
+	  TMP432_IDX_REMOTE1 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -270,9 +264,11 @@ struct ec_thermal_config thermal_params[] = {
 	 * {Twarn, Thigh, X    }, <off>
 	 * fan_off, fan_max
 	 */
-	{{0, C_TO_K(80), C_TO_K(81)}, {0, C_TO_K(78), 0},
-		C_TO_K(4), C_TO_K(76)},	/* TMP431_Internal */
-	{{0, 0, 0}, {0, 0, 0}, 0, 0},	/* TMP431_Sensor_1 */
+	{ { 0, C_TO_K(80), C_TO_K(81) },
+	  { 0, C_TO_K(78), 0 },
+	  C_TO_K(4),
+	  C_TO_K(76) }, /* TMP431_Internal */
+	{ { 0, 0, 0 }, { 0, 0, 0 }, 0, 0 }, /* TMP431_Sensor_1 */
 };
 BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
 
@@ -441,9 +437,9 @@ int64_t get_time_dsw_pwrok(void)
 }
 
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED_RED]  = { 3, PWM_CONFIG_DSLEEP, 100 },
+	[PWM_CH_LED_RED] = { 3, PWM_CONFIG_DSLEEP, 100 },
 	[PWM_CH_LED_BLUE] = { 5, PWM_CONFIG_DSLEEP, 100 },
-	[PWM_CH_FAN] = {4, PWM_CONFIG_OPEN_DRAIN, 25000},
+	[PWM_CH_FAN] = { 4, PWM_CONFIG_OPEN_DRAIN, 25000 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
@@ -455,21 +451,20 @@ struct fan_step {
 
 /* Note: Do not make the fan on/off point equal to 0 or 100 */
 static const struct fan_step fan_table0[] = {
-	{.on =  0, .off =  5, .rpm = 0},
-	{.on = 30, .off =  5, .rpm = 2180},
-	{.on = 49, .off = 46, .rpm = 2680},
-	{.on = 53, .off = 50, .rpm = 3300},
-	{.on = 58, .off = 54, .rpm = 3760},
-	{.on = 63, .off = 59, .rpm = 4220},
-	{.on = 68, .off = 64, .rpm = 4660},
-	{.on = 75, .off = 70, .rpm = 4900},
+	{ .on = 0, .off = 5, .rpm = 0 },
+	{ .on = 30, .off = 5, .rpm = 2180 },
+	{ .on = 49, .off = 46, .rpm = 2680 },
+	{ .on = 53, .off = 50, .rpm = 3300 },
+	{ .on = 58, .off = 54, .rpm = 3760 },
+	{ .on = 63, .off = 59, .rpm = 4220 },
+	{ .on = 68, .off = 64, .rpm = 4660 },
+	{ .on = 75, .off = 70, .rpm = 4900 },
 };
 /* All fan tables must have the same number of levels */
 #define NUM_FAN_LEVELS ARRAY_SIZE(fan_table0)
 
 static const struct fan_step *fan_table = fan_table0;
 
-
 static void cbi_init(void)
 {
 	uint32_t val;
@@ -489,8 +484,8 @@ DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1);
 
 static void setup_bj(void)
 {
-	enum bj_adapter bj = (BJ_ADAPTER_135W_MASK & (1 << sku)) ?
-			BJ_135W_19V : BJ_90W_19V;
+	enum bj_adapter bj = (BJ_ADAPTER_135W_MASK & (1 << sku)) ? BJ_135W_19V :
+								   BJ_90W_19V;
 	gpio_set_level(GPIO_U22_90W, bj == BJ_90W_19V);
 }
 
@@ -537,8 +532,7 @@ int fan_percent_to_rpm(int fan, int pct)
 
 	previous_pct = pct;
 
-	if (fan_table[current_level].rpm !=
-		fan_get_rpm_target(FAN_CH(fan)))
+	if (fan_table[current_level].rpm != fan_get_rpm_target(FAN_CH(fan)))
 		cprints(CC_THERMAL, "Setting fan RPM to %d",
 			fan_table[current_level].rpm);
 
diff --git a/baseboard/kalista/baseboard.h b/baseboard/kalista/baseboard.h
index 717d26b313..e3696ae48d 100644
--- a/baseboard/kalista/baseboard.h
+++ b/baseboard/kalista/baseboard.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,7 +12,7 @@
  * Allow dangerous commands.
  * TODO: Remove this config before production.
  */
-#undef  CONFIG_SYSTEM_UNLOCKED
+#undef CONFIG_SYSTEM_UNLOCKED
 #define CONFIG_USB_PD_COMM_LOCKED
 
 /* EC */
@@ -32,7 +32,7 @@
 #define CONFIG_FPU
 #define CONFIG_I2C
 #define CONFIG_I2C_CONTROLLER
-#undef  CONFIG_LID_SWITCH
+#undef CONFIG_LID_SWITCH
 #define CONFIG_POWER_BUTTON_IGNORE_LID
 #define CONFIG_PWM
 #define CONFIG_LTO
@@ -47,7 +47,7 @@
 #define WIRELESS_GPIO_WLAN_POWER GPIO_PP3300_DX_WLAN
 #define WIRELESS_GPIO_WWAN GPIO_PP3300_DX_LTE
 #define CEC_GPIO_OUT GPIO_CEC_OUT
-#define CEC_GPIO_IN  GPIO_CEC_IN
+#define CEC_GPIO_IN GPIO_CEC_IN
 #define CEC_GPIO_PULL_UP GPIO_CEC_PULL_UP
 #define CONFIG_FANS 1
 #define CONFIG_FAN_RPM_CUSTOM
@@ -64,13 +64,13 @@
 #define CONFIG_CHIPSET_HAS_PRE_INIT_CALLBACK
 #define CONFIG_CHIPSET_RESET_HOOK
 #define CONFIG_HOST_INTERFACE_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 #define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD
 
 #define CONFIG_HOSTCMD_PD_CONTROL
 #define CONFIG_EXTPOWER_GPIO
-#undef  CONFIG_EXTPOWER_DEBOUNCE_MS
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
 #define CONFIG_EXTPOWER_DEBOUNCE_MS 1000
 #define CONFIG_POWER_BUTTON
 #define CONFIG_POWER_BUTTON_X86
@@ -105,20 +105,20 @@
 #define USB_PORT_COUNT 4
 
 /* Optional feature to configure npcx chip */
-#define NPCX_UART_MODULE2	1 /* 1:GPIO64/65 as UART */
-#define NPCX_JTAG_MODULE2	0 /* 0:GPIO21/17/16/20 as JTAG */
-#define NPCX_TACH_SEL2		1 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
+#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART */
+#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 as JTAG */
+#define NPCX_TACH_SEL2 1 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
 
 /* I2C ports */
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT0_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT0_1
-#define I2C_PORT_BACKLIGHT	NPCX_I2C_PORT1
-#define I2C_PORT_PMIC		NPCX_I2C_PORT2
-#define I2C_PORT_THERMAL	NPCX_I2C_PORT3
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT0_1
+#define I2C_PORT_BACKLIGHT NPCX_I2C_PORT1
+#define I2C_PORT_PMIC NPCX_I2C_PORT2
+#define I2C_PORT_THERMAL NPCX_I2C_PORT3
 
 /* I2C addresses */
-#define I2C_ADDR_TCPC0_FLAGS	0x0b
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_ADDR_TCPC0_FLAGS 0x0b
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 
 /* Verify and jump to RW image on boot */
 #define CONFIG_VBOOT_EFS
@@ -140,23 +140,22 @@
  * end of RW_A and RW_B, respectively.
  */
 #define CONFIG_RW_B
-#define CONFIG_RW_B_MEM_OFF		CONFIG_RO_MEM_OFF
-#undef  CONFIG_RO_SIZE
-#define CONFIG_RO_SIZE			(CONFIG_FLASH_SIZE_BYTES / 4)
-#undef  CONFIG_RW_SIZE
-#define CONFIG_RW_SIZE			CONFIG_RO_SIZE
-#define CONFIG_RW_A_STORAGE_OFF		CONFIG_RW_STORAGE_OFF
-#define CONFIG_RW_B_STORAGE_OFF		(CONFIG_RW_A_STORAGE_OFF + \
-					 CONFIG_RW_SIZE)
-#define CONFIG_RW_A_SIGN_STORAGE_OFF	(CONFIG_RW_A_STORAGE_OFF + \
-					 CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE)
-#define CONFIG_RW_B_SIGN_STORAGE_OFF	(CONFIG_RW_B_STORAGE_OFF + \
-					 CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE)
+#define CONFIG_RW_B_MEM_OFF CONFIG_RO_MEM_OFF
+#undef CONFIG_RO_SIZE
+#define CONFIG_RO_SIZE (CONFIG_FLASH_SIZE_BYTES / 4)
+#undef CONFIG_RW_SIZE
+#define CONFIG_RW_SIZE CONFIG_RO_SIZE
+#define CONFIG_RW_A_STORAGE_OFF CONFIG_RW_STORAGE_OFF
+#define CONFIG_RW_B_STORAGE_OFF (CONFIG_RW_A_STORAGE_OFF + CONFIG_RW_SIZE)
+#define CONFIG_RW_A_SIGN_STORAGE_OFF \
+	(CONFIG_RW_A_STORAGE_OFF + CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE)
+#define CONFIG_RW_B_SIGN_STORAGE_OFF \
+	(CONFIG_RW_B_STORAGE_OFF + CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE)
 
 #undef CONFIG_EC_PROTECTED_STORAGE_SIZE
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE	CONFIG_RO_SIZE
+#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE
 #undef CONFIG_EC_WRITABLE_STORAGE_SIZE
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE		CONFIG_RW_SIZE
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE
 
 #define CONFIG_RWSIG
 #define CONFIG_RWSIG_TYPE_RWSIG
@@ -182,15 +181,12 @@ enum charge_port {
 };
 
 enum temp_sensor_id {
-	TEMP_SENSOR_CHARGER,	/* BD99992GW SYSTHERM1 */
-	TEMP_SENSOR_DRAM,	/* BD99992GW SYSTHERM2 */
+	TEMP_SENSOR_CHARGER, /* BD99992GW SYSTHERM1 */
+	TEMP_SENSOR_DRAM, /* BD99992GW SYSTHERM2 */
 	TEMP_SENSOR_COUNT
 };
 
-enum adc_channel {
-	ADC_VBUS,
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_VBUS, ADC_CH_COUNT };
 
 enum pwm_channel {
 	PWM_CH_LED_RED,
@@ -223,8 +219,8 @@ enum OEM_ID {
  * delay to turn on the power supply max is ~16ms.
  * delay to turn off the power supply max is about ~180ms.
  */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	250000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* delay to turn on/off vconn */
 
diff --git a/baseboard/kalista/build.mk b/baseboard/kalista/build.mk
index fb844b19f1..6bb55b2023 100644
--- a/baseboard/kalista/build.mk
+++ b/baseboard/kalista/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/baseboard/kalista/led.c b/baseboard/kalista/led.c
index e04eecf5e3..c72ce84bb0 100644
--- a/baseboard/kalista/led.c
+++ b/baseboard/kalista/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -15,7 +15,7 @@
 #include "timer.h"
 #include "util.h"
 
-const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 enum led_color {
@@ -76,9 +76,9 @@ static int set_color(enum ec_led_id id, enum led_color color, int duty)
 	}
 }
 
-#define LED_PULSE_US		(2 * SECOND)
+#define LED_PULSE_US (2 * SECOND)
 /* 40 msec for nice and smooth transition. */
-#define LED_PULSE_TICK_US	(40 * MSEC)
+#define LED_PULSE_TICK_US (40 * MSEC)
 
 /* When pulsing is enabled, brightness is incremented by <duty_inc> every
  * <interval> usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented
@@ -181,7 +181,7 @@ void led_critical(void)
 		set_color(EC_LED_ID_POWER_LED, LED_RED, 100);
 }
 
-static int command_led(int argc, char **argv)
+static int command_led(int argc, const char **argv)
 {
 	enum ec_led_id id = EC_LED_ID_POWER_LED;
 
diff --git a/baseboard/kalista/usb_pd_pdo.c b/baseboard/kalista/usb_pd_pdo.c
index 0addbcc51c..067b8eb9e7 100644
--- a/baseboard/kalista/usb_pd_pdo.c
+++ b/baseboard/kalista/usb_pd_pdo.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,9 +7,8 @@
 #include "usb_pd.h"
 #include "usb_pd_pdo.h"
 
-#define PDO_FIXED_FLAGS (PDO_FIXED_UNCONSTRAINED | \
-			 PDO_FIXED_DATA_SWAP | \
-			 PDO_FIXED_COMM_CAP)
+#define PDO_FIXED_FLAGS \
+	(PDO_FIXED_UNCONSTRAINED | PDO_FIXED_DATA_SWAP | PDO_FIXED_COMM_CAP)
 
 const uint32_t pd_src_pdo[] = {
 	PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS),
diff --git a/baseboard/kalista/usb_pd_pdo.h b/baseboard/kalista/usb_pd_pdo.h
index 1dad035d3d..119658b8a5 100644
--- a/baseboard/kalista/usb_pd_pdo.h
+++ b/baseboard/kalista/usb_pd_pdo.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/baseboard/kalista/usb_pd_policy.c b/baseboard/kalista/usb_pd_policy.c
index 85b26aac76..017c340a1b 100644
--- a/baseboard/kalista/usb_pd_policy.c
+++ b/baseboard/kalista/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,8 +23,8 @@
 #include "usb_pd_pdo.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int board_vbus_source_enabled(int port)
 {
@@ -58,8 +58,7 @@ int pd_snk_is_vbus_provided(int port)
 	return !gpio_get_level(GPIO_USB_C0_VBUS_WAKE_L);
 }
 
-__override void pd_check_pr_role(int port,
-				 enum pd_power_role pr_role,
+__override void pd_check_pr_role(int port, enum pd_power_role pr_role,
 				 int flags)
 {
 }
diff --git a/baseboard/kukui/base_detect_kukui.c b/baseboard/kukui/base_detect_kukui.c
index 55da56f687..a3ccf4d507 100644
--- a/baseboard/kukui/base_detect_kukui.c
+++ b/baseboard/kukui/base_detect_kukui.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,7 +14,7 @@
 #include "usb_pd.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USB, format, ##args)
 
 /* Krane base detection code */
 
@@ -41,11 +41,11 @@ enum kukui_pogo_device_type {
 struct {
 	int mv_low, mv_high;
 } static const pogo_detect_table[] = {
-	[DEVICE_TYPE_DETACHED] = {2700, 3500}, /* 10K, NC, around 3.3V */
+	[DEVICE_TYPE_DETACHED] = { 2700, 3500 }, /* 10K, NC, around 3.3V */
 #ifdef VARIANT_KUKUI_POGO_DOCK
-	[DEVICE_TYPE_DOCK] = {141, 173},       /* 10K, 0.5K ohm */
+	[DEVICE_TYPE_DOCK] = { 141, 173 }, /* 10K, 0.5K ohm */
 #endif
-	[DEVICE_TYPE_KEYBOARD] = {270, 400},   /* 10K, 1K ohm */
+	[DEVICE_TYPE_KEYBOARD] = { 270, 400 }, /* 10K, 1K ohm */
 };
 BUILD_ASSERT(ARRAY_SIZE(pogo_detect_table) == DEVICE_TYPE_COUNT);
 
@@ -71,7 +71,7 @@ static enum kukui_pogo_device_type get_device_type(int mv)
 
 	for (i = 0; i < DEVICE_TYPE_COUNT; i++) {
 		if (pogo_detect_table[i].mv_low <= mv &&
-				mv <= pogo_detect_table[i].mv_high)
+		    mv <= pogo_detect_table[i].mv_high)
 			return i;
 	}
 
@@ -82,17 +82,17 @@ static void enable_charge(int enable)
 {
 #ifdef VARIANT_KUKUI_POGO_DOCK
 	if (enable) {
-		struct charge_port_info info = {
-			.voltage = 5000, .current = 1500};
+		struct charge_port_info info = { .voltage = 5000,
+						 .current = 1500 };
 		/*
 		 * Set supplier type to PD to have same priority as type c
 		 * port.
 		 */
-		charge_manager_update_charge(
-			CHARGE_SUPPLIER_DEDICATED, CHARGE_PORT_POGO, &info);
+		charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED,
+					     CHARGE_PORT_POGO, &info);
 	} else {
-		charge_manager_update_charge(
-			CHARGE_SUPPLIER_DEDICATED, CHARGE_PORT_POGO, NULL);
+		charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED,
+					     CHARGE_PORT_POGO, NULL);
 	}
 	pd_send_host_event(PD_EVENT_POWER_CHANGE);
 #endif
@@ -112,7 +112,7 @@ static void base_set_device_type(enum kukui_pogo_device_type device_type)
 	case DEVICE_TYPE_ERROR:
 	case DEVICE_TYPE_UNKNOWN:
 		hook_call_deferred(&base_detect_deferred_data,
-				BASE_DETECT_RETRY_US);
+				   BASE_DETECT_RETRY_US);
 		break;
 
 	case DEVICE_TYPE_DETACHED:
@@ -210,11 +210,11 @@ void base_force_state(enum ec_set_base_state_cmd state)
 
 	gpio_disable_interrupt(GPIO_POGO_ADC_INT_L);
 	pogo_type = (state == 1 ? DEVICE_TYPE_KEYBOARD : DEVICE_TYPE_DETACHED);
-	base_set_device_type(state == EC_SET_BASE_STATE_ATTACH
-					? DEVICE_TYPE_KEYBOARD
-					: DEVICE_TYPE_DETACHED);
-	CPRINTS("BD forced %sconnected", state == EC_SET_BASE_STATE_ATTACH ?
-						  "" : "dis");
+	base_set_device_type(state == EC_SET_BASE_STATE_ATTACH ?
+				     DEVICE_TYPE_KEYBOARD :
+				     DEVICE_TYPE_DETACHED);
+	CPRINTS("BD forced %sconnected",
+		state == EC_SET_BASE_STATE_ATTACH ? "" : "dis");
 }
 
 #ifdef VARIANT_KUKUI_POGO_DOCK
diff --git a/baseboard/kukui/baseboard.c b/baseboard/kukui/baseboard.c
index c9831ed300..04e444aad0 100644
--- a/baseboard/kukui/baseboard.c
+++ b/baseboard/kukui/baseboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,8 +14,8 @@
 #include "registers.h"
 #include "timer.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 #ifndef CONFIG_CHARGER_RUNTIME_CONFIG
 #if defined(VARIANT_KUKUI_CHARGER_MT6370)
@@ -54,11 +54,11 @@ void board_config_pre_init(void)
 	 * Ch4: USART1_TX / Ch5: USART1_RX (1000)
 	 * Ch6: SPI2_RX / Ch7: SPI2_TX (0011)
 	 */
-	STM32_DMA_CSELR(STM32_DMAC_CH4) = (8 << 12) | (8 << 16) |
-					  (3 << 20) | (3 << 24);
+	STM32_DMA_CSELR(STM32_DMAC_CH4) = (8 << 12) | (8 << 16) | (3 << 20) |
+					  (3 << 24);
 
 #elif defined(VARIANT_KUKUI_EC_STM32L431)
-#ifdef	CONFIG_DMA
+#ifdef CONFIG_DMA
 	dma_init();
 #endif
 	/*
@@ -102,43 +102,43 @@ enum kukui_board_version {
 /* map from kukui_board_version to board id voltage in mv */
 #ifdef VARIANT_KUKUI_EC_IT81202
 const int16_t kukui_board_id_map[] = {
-	136,   /* 51.1K , 2.2K(gru 3.3K) ohm */
-	388,   /* 51.1k , 6.8K ohm */
-	584,   /* 51.1K , 11K ohm */
-	785,   /* 56K   , 17.4K ohm */
-	993,   /* 51.1K , 22K ohm */
-	1221,  /* 51.1K , 30K ohm */
-	1433,  /* 51.1K , 39.2K ohm */
-	1650,  /* 56K   , 56K ohm */
-	1876,  /* 47K   , 61.9K ohm */
-	2084,  /* 47K   , 80.6K ohm */
-	2273,  /* 56K   , 124K ohm */
-	2461,  /* 51.1K , 150K ohm */
-	2672,  /* 47K   , 200K ohm */
-	2889,  /* 47K   , 330K ohm */
-	3086,  /* 47K   , 680K ohm */
-	3300,  /* 56K   , NC */
+	136, /* 51.1K , 2.2K(gru 3.3K) ohm */
+	388, /* 51.1k , 6.8K ohm */
+	584, /* 51.1K , 11K ohm */
+	785, /* 56K   , 17.4K ohm */
+	993, /* 51.1K , 22K ohm */
+	1221, /* 51.1K , 30K ohm */
+	1433, /* 51.1K , 39.2K ohm */
+	1650, /* 56K   , 56K ohm */
+	1876, /* 47K   , 61.9K ohm */
+	2084, /* 47K   , 80.6K ohm */
+	2273, /* 56K   , 124K ohm */
+	2461, /* 51.1K , 150K ohm */
+	2672, /* 47K   , 200K ohm */
+	2889, /* 47K   , 330K ohm */
+	3086, /* 47K   , 680K ohm */
+	3300, /* 56K   , NC */
 };
 
 #define THRESHOLD_MV 103 /* Simply assume 3300/16/2 */
 #else
 const int16_t kukui_board_id_map[] = {
-	109,   /* 51.1K , 2.2K(gru 3.3K) ohm */
-	211,   /* 51.1k , 6.8K ohm */
-	319,   /* 51.1K , 11K ohm */
-	427,   /* 56K   , 17.4K ohm */
-	542,   /* 51.1K , 22K ohm */
-	666,   /* 51.1K , 30K ohm */
-	781,   /* 51.1K , 39.2K ohm */
-	900,   /* 56K   , 56K ohm */
-	1023,  /* 47K   , 61.9K ohm */
-	1137,  /* 47K   , 80.6K ohm */
-	1240,  /* 56K   , 124K ohm */
-	1343,  /* 51.1K , 150K ohm */
-	1457,  /* 47K   , 200K ohm */
-	1576,  /* 47K   , 330K ohm */
-	1684,  /* 47K   , 680K ohm */
-	1800,  /* 56K   , NC */
+	109, /* 51.1K , 2.2K(gru 3.3K) ohm */
+	211, /* 51.1k , 6.8K ohm */
+	319, /* 51.1K , 11K ohm */
+	427, /* 56K   , 17.4K ohm */
+	542, /* 51.1K , 22K ohm */
+	666, /* 51.1K , 30K ohm */
+	781, /* 51.1K , 39.2K ohm */
+	900, /* 56K   , 56K ohm */
+	1023, /* 47K   , 61.9K ohm */
+	1137, /* 47K   , 80.6K ohm */
+	1240, /* 56K   , 124K ohm */
+	1343, /* 51.1K , 150K ohm */
+	1457, /* 47K   , 200K ohm */
+	1576, /* 47K   , 330K ohm */
+	1684, /* 47K   , 680K ohm */
+	1800, /* 56K   , NC */
 };
 
 #define THRESHOLD_MV 56 /* Simply assume 1800/16/2 */
@@ -178,7 +178,7 @@ int board_get_version(void)
 	 * for this board.
 	 */
 	if (CONFIG_DEDICATED_CHARGE_PORT_COUNT == 0 &&
-			version != BOARD_VERSION_UNKNOWN)
+	    version != BOARD_VERSION_UNKNOWN)
 		adc_disable();
 #endif
 
@@ -216,8 +216,7 @@ __override void lid_angle_peripheral_enable(int enable)
 		 * ignore input devices or not.
 		 */
 		if (!chipset_in_s0)
-			keyboard_scan_enable(0,
-					     KB_SCAN_DISABLE_LID_ANGLE);
+			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
 	}
 }
 #endif
diff --git a/baseboard/kukui/baseboard.h b/baseboard/kukui/baseboard.h
index 59e161571f..fc87b3441b 100644
--- a/baseboard/kukui/baseboard.h
+++ b/baseboard/kukui/baseboard.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,7 +18,7 @@
 #if defined(VARIANT_KUKUI_BATTERY_MAX17055)
 #define CONFIG_BATTERY_MAX17055
 #define CONFIG_BATTERY_MAX17055_ALERT
-#define BATTERY_MAX17055_RSENSE             5     /* m-ohm */
+#define BATTERY_MAX17055_RSENSE 5 /* m-ohm */
 #elif defined(VARIANT_KUKUI_BATTERY_MM8013)
 #define CONFIG_BATTERY_MM8013
 #elif defined(VARIANT_KUKUI_BATTERY_BQ27541)
@@ -47,7 +47,7 @@
 #define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
 
 /* TCPC MT6370 */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /*
@@ -64,7 +64,7 @@
 #define CONFIG_CHARGE_RAMP_HW
 
 /* TCPC FUSB302 */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  160000  /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 160000 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* b/2230219: 15V has better charging performance than 20V */
@@ -115,16 +115,16 @@
 
 #define PD_OPERATING_POWER_MW 30000
 
-#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \
-		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK            \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
 
 #else /* !VARIANT_KUKUI_JACUZZI */
 
-#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \
-		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
+#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK                \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |     \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
 
 #endif /* VARIANT_KUKUI_JACUZZI */
 
@@ -144,9 +144,9 @@
 
 /* Optional modules */
 #define CONFIG_ADC
-#undef  CONFIG_ADC_WATCHDOG
+#undef CONFIG_ADC_WATCHDOG
 #define CONFIG_CHIPSET_MT8183
-#undef  CONFIG_CMD_ACCELS
+#undef CONFIG_CMD_ACCELS
 #define CONFIG_EMULATED_SYSRQ
 #define CONFIG_I2C
 #define CONFIG_I2C_CONTROLLER
@@ -207,8 +207,8 @@
 #undef CONFIG_UART_TX_BUF_SIZE
 #define CONFIG_UART_TX_BUF_SIZE 4096
 
-#define GPIO_LID_OPEN		GPIO_HALL_INT_L
-#define GPIO_KB_DISCRETE_INT	GPIO_IT8801_SMB_INT
+#define GPIO_LID_OPEN GPIO_HALL_INT_L
+#define GPIO_KB_DISCRETE_INT GPIO_IT8801_SMB_INT
 
 #ifndef VARIANT_KUKUI_NO_SENSORS
 #define CONFIG_ACCEL_FIFO
@@ -241,11 +241,11 @@
 #define CONFIG_BATTERY_PRESENT_CUSTOM
 #define CONFIG_BATTERY_REVIVE_DISCONNECT
 
-#define PD_MAX_POWER_MW       ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
+#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
 #ifdef BOARD_KODAMA
-#define PD_MAX_CURRENT_MA     2000
+#define PD_MAX_CURRENT_MA 2000
 #else
-#define PD_MAX_CURRENT_MA     3000
+#define PD_MAX_CURRENT_MA 3000
 #endif
 
 /* Optional for testing */
@@ -263,7 +263,7 @@
  */
 #if defined(VARIANT_KUKUI_EC_STM32F098) || defined(VARIANT_KUKUI_EC_STM32L431)
 /* Timer selection */
-#define TIM_CLOCK32  2
+#define TIM_CLOCK32 2
 #define TIM_WATCHDOG 7
 
 /* 48 MHz SYSCLK clock frequency */
@@ -273,11 +273,11 @@
 #define CPU_CLOCK 48000000
 #endif
 
-#undef  CONFIG_HIBERNATE
+#undef CONFIG_HIBERNATE
 #define CONFIG_SPI_CONTROLLER
 #define CONFIG_STM_HWTIMER32
 #define CONFIG_WATCHDOG_HELP
-#undef  CONFIG_UART_CONSOLE
+#undef CONFIG_UART_CONSOLE
 #define CONFIG_UART_CONSOLE 1
 #define CONFIG_UART_RX_DMA
 
diff --git a/baseboard/kukui/battery_bq27541.c b/baseboard/kukui/battery_bq27541.c
index 94f46b3326..453d5e984f 100644
--- a/baseboard/kukui/battery_bq27541.c
+++ b/baseboard/kukui/battery_bq27541.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -6,6 +6,7 @@
  */
 
 #include "battery.h"
+#include "builtin/assert.h"
 #include "charge_state.h"
 #include "charger_mt6370.h"
 #include "console.h"
@@ -25,12 +26,9 @@
 
 #define BAT_LEVEL_PD_LIMIT 85
 
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
-enum battery_type {
-	BATTERY_CPT = 0,
-	BATTERY_COUNT
-};
+enum battery_type { BATTERY_CPT = 0, BATTERY_COUNT };
 
 static const struct battery_info info[] = {
 	[BATTERY_CPT] = {
@@ -105,7 +103,7 @@ int charger_profile_override(struct charge_state_data *curr)
 	else {
 		for (temp_zone = 0; temp_zone < TEMP_ZONE_COUNT; temp_zone++) {
 			if (bat_temp_c <
-				temp_zones[BATT_ID][temp_zone].temp_max)
+			    temp_zones[BATT_ID][temp_zone].temp_max)
 				break;
 		}
 	}
@@ -143,7 +141,7 @@ int charger_profile_override(struct charge_state_data *curr)
 		rcv_cycle = 150;
 	/* Check SOH to decrease charging voltage. */
 	if (!battery_full_charge_capacity(&full_cap) &&
-		!battery_design_capacity(&design_cap))
+	    !battery_design_capacity(&design_cap))
 		soh = ((full_cap * 100) / design_cap);
 	if (soh > 70 && soh <= 75)
 		rcv_soh = 50;
@@ -159,15 +157,13 @@ int charger_profile_override(struct charge_state_data *curr)
 	curr->requested_voltage -= rcv;
 
 	/* Should not keep charging voltage > 4250mV for 48hrs. */
-	if ((curr->state == ST_DISCHARGE) ||
-		curr->chg.voltage < 4250) {
+	if ((curr->state == ST_DISCHARGE) || curr->chg.voltage < 4250) {
 		deadline_48.val = 0;
-	/* Starting count 48hours */
-	} else if (curr->state == ST_CHARGE ||
-		curr->state == ST_PRECHARGE) {
+		/* Starting count 48hours */
+	} else if (curr->state == ST_CHARGE || curr->state == ST_PRECHARGE) {
 		if (deadline_48.val == 0)
 			deadline_48.val = get_time().val +
-				CHARGER_LIMIT_TIMEOUT_HOURS * HOUR;
+					  CHARGER_LIMIT_TIMEOUT_HOURS * HOUR;
 		/* If charging voltage keep > 4250 for 48hrs,
 		 * set charging voltage = 4250
 		 */
@@ -177,14 +173,13 @@ int charger_profile_override(struct charge_state_data *curr)
 	/* Should not keeep battery voltage > 4100mV and
 	 * battery temperature > 45C for two hour
 	 */
-	if (curr->state == ST_DISCHARGE ||
-		curr->batt.voltage < 4100 ||
-		bat_temp_c < 450) {
+	if (curr->state == ST_DISCHARGE || curr->batt.voltage < 4100 ||
+	    bat_temp_c < 450) {
 		deadline_2.val = 0;
-	} else if (curr->state == ST_CHARGE ||
-		curr->state == ST_PRECHARGE) {
+	} else if (curr->state == ST_CHARGE || curr->state == ST_PRECHARGE) {
 		if (deadline_2.val == 0)
-			deadline_2.val = get_time().val +
+			deadline_2.val =
+				get_time().val +
 				CHARGER_LIMIT_TIMEOUT_HOURS_TEMP * HOUR;
 		else if (timestamp_expired(deadline_2, NULL)) {
 			/* Set discharge and charging voltage = 4100mV */
@@ -216,7 +211,7 @@ enum ec_status charger_profile_override_set_param(uint32_t param,
 
 int get_battery_manufacturer_name(char *dest, int size)
 {
-	static const char * const name[] = {
+	static const char *const name[] = {
 		[BATTERY_CPT] = "AS1XXXD3Ka",
 	};
 	ASSERT(dest);
diff --git a/baseboard/kukui/battery_max17055.c b/baseboard/kukui/battery_max17055.c
index 53e72766a7..5ebb220b0c 100644
--- a/baseboard/kukui/battery_max17055.c
+++ b/baseboard/kukui/battery_max17055.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -6,6 +6,7 @@
  */
 
 #include "battery.h"
+#include "builtin/assert.h"
 #include "charge_state.h"
 #include "charger_mt6370.h"
 #include "console.h"
@@ -20,12 +21,9 @@
 #define BATTERY_SIMPLO_CHARGE_MIN_TEMP 0
 #define BATTERY_SIMPLO_CHARGE_MAX_TEMP 60
 
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
-enum battery_type {
-	BATTERY_SIMPLO = 0,
-	BATTERY_COUNT
-};
+enum battery_type { BATTERY_SIMPLO = 0, BATTERY_COUNT };
 
 static const struct battery_info info[] = {
 	[BATTERY_SIMPLO] = {
@@ -132,7 +130,7 @@ int charger_profile_override(struct charge_state_data *curr)
 	else {
 		for (temp_zone = 0; temp_zone < TEMP_ZONE_COUNT; temp_zone++) {
 			if (bat_temp_c <
-				temp_zones[BATT_ID][temp_zone].temp_max)
+			    temp_zones[BATT_ID][temp_zone].temp_max)
 				break;
 		}
 	}
@@ -178,7 +176,7 @@ enum ec_status charger_profile_override_set_param(uint32_t param,
 
 int get_battery_manufacturer_name(char *dest, int size)
 {
-	static const char * const name[] = {
+	static const char *const name[] = {
 		[BATTERY_SIMPLO] = "SIMPLO",
 	};
 	ASSERT(dest);
diff --git a/baseboard/kukui/battery_mm8013.c b/baseboard/kukui/battery_mm8013.c
index e7f422e561..26507d5915 100644
--- a/baseboard/kukui/battery_mm8013.c
+++ b/baseboard/kukui/battery_mm8013.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -22,12 +22,9 @@
 
 #define BAT_LEVEL_PD_LIMIT 85
 
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
-enum battery_type {
-	BATTERY_SCUD = 0,
-	BATTERY_COUNT
-};
+enum battery_type { BATTERY_SCUD = 0, BATTERY_COUNT };
 
 static const struct battery_info info[] = {
 	[BATTERY_SCUD] = {
@@ -100,7 +97,7 @@ int charger_profile_override(struct charge_state_data *curr)
 	else {
 		for (temp_zone = 0; temp_zone < TEMP_ZONE_COUNT; temp_zone++) {
 			if (bat_temp_c <
-				temp_zones[BATT_ID][temp_zone].temp_max)
+			    temp_zones[BATT_ID][temp_zone].temp_max)
 				break;
 		}
 	}
diff --git a/baseboard/kukui/battery_smart.c b/baseboard/kukui/battery_smart.c
index ba2af17443..b924b2e3a9 100644
--- a/baseboard/kukui/battery_smart.c
+++ b/baseboard/kukui/battery_smart.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -98,39 +98,30 @@ __override void board_battery_compensate_params(struct batt_params *batt)
 
 	/* return cached values for at most CACHE_INVALIDATION_TIME_US */
 	fix_single_param(batt->flags & BATT_FLAG_BAD_STATE_OF_CHARGE,
-			&batt_cache.state_of_charge,
-			&batt->state_of_charge);
+			 &batt_cache.state_of_charge, &batt->state_of_charge);
 	fix_single_param(batt->flags & BATT_FLAG_BAD_VOLTAGE,
-			&batt_cache.voltage,
-			&batt->voltage);
+			 &batt_cache.voltage, &batt->voltage);
 	fix_single_param(batt->flags & BATT_FLAG_BAD_CURRENT,
-			&batt_cache.current,
-			&batt->current);
+			 &batt_cache.current, &batt->current);
 	fix_single_param(batt->flags & BATT_FLAG_BAD_DESIRED_VOLTAGE,
-			&batt_cache.desired_voltage,
-			&batt->desired_voltage);
+			 &batt_cache.desired_voltage, &batt->desired_voltage);
 	fix_single_param(batt->flags & BATT_FLAG_BAD_DESIRED_CURRENT,
-			&batt_cache.desired_current,
-			&batt->desired_current);
+			 &batt_cache.desired_current, &batt->desired_current);
 	fix_single_param(batt->flags & BATT_FLAG_BAD_REMAINING_CAPACITY,
-			&batt_cache.remaining_capacity,
-			&batt->remaining_capacity);
+			 &batt_cache.remaining_capacity,
+			 &batt->remaining_capacity);
 	fix_single_param(batt->flags & BATT_FLAG_BAD_FULL_CAPACITY,
-			&batt_cache.full_capacity,
-			&batt->full_capacity);
-	fix_single_param(batt->flags & BATT_FLAG_BAD_STATUS,
-			&batt_cache.status,
-			&batt->status);
+			 &batt_cache.full_capacity, &batt->full_capacity);
+	fix_single_param(batt->flags & BATT_FLAG_BAD_STATUS, &batt_cache.status,
+			 &batt->status);
 	fix_single_param(batt->flags & BATT_FLAG_BAD_TEMPERATURE,
-			&batt_cache.temperature,
-			&batt->temperature);
+			 &batt_cache.temperature, &batt->temperature);
 	/*
 	 * If battery_compensate_params() didn't calculate display_charge
 	 * for us, also update it with last good value.
 	 */
-	fix_single_param(batt->display_charge == 0,
-			&batt_cache.display_charge,
-			&batt->display_charge);
+	fix_single_param(batt->display_charge == 0, &batt_cache.display_charge,
+			 &batt->display_charge);
 
 	/* remove bad flags after applying cached values */
 	batt->flags &= ~BATT_FLAG_BAD_ANY;
diff --git a/baseboard/kukui/build.mk b/baseboard/kukui/build.mk
index c64f6978c8..f35ed1f4ce 100644
--- a/baseboard/kukui/build.mk
+++ b/baseboard/kukui/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/baseboard/kukui/charger_mt6370.c b/baseboard/kukui/charger_mt6370.c
index 99e51aead2..398473bfc8 100644
--- a/baseboard/kukui/charger_mt6370.c
+++ b/baseboard/kukui/charger_mt6370.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -51,7 +51,7 @@ static void update_plt_resume(void)
 }
 DECLARE_HOOK(HOOK_CHIPSET_RESUME, update_plt_resume, HOOK_PRIO_DEFAULT);
 
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 /* wait time to evaluate charger thermal status */
 static timestamp_t thermal_wait_until;
@@ -155,7 +155,7 @@ thermal_exit:
 	thermal_wait_until.val = get_time().val + (3 * SECOND);
 }
 
-static int command_jc(int argc, char **argv)
+static int command_jc(int argc, const char **argv)
 {
 	static int prev_jc_temp;
 	int jc_temp;
@@ -304,8 +304,8 @@ void mt6370_charger_profile_override(struct charge_state_data *curr)
 				 * and TE function.
 				 */
 				hook_call_deferred(
-						&charge_enable_eoc_and_te_data,
-						(4.5 * SECOND));
+					&charge_enable_eoc_and_te_data,
+					(4.5 * SECOND));
 			}
 		}
 	}
@@ -339,7 +339,6 @@ void mt6370_charger_profile_override(struct charge_state_data *curr)
 		curr->batt.state_of_charge = MAX(BATTERY_LEVEL_NEAR_FULL,
 						 curr->batt.state_of_charge);
 	}
-
 }
 
 #ifndef CONFIG_BATTERY_SMART
@@ -352,13 +351,12 @@ static void board_charge_termination(void)
 			te = 1;
 	}
 }
-DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE,
-	     board_charge_termination,
+DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, board_charge_termination,
 	     HOOK_PRIO_DEFAULT);
 #endif
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	prev_charge_limit = charge_ma;
 	prev_charge_mv = charge_mv;
diff --git a/baseboard/kukui/charger_mt6370.h b/baseboard/kukui/charger_mt6370.h
index 880b00a1a8..1de4e66b0b 100644
--- a/baseboard/kukui/charger_mt6370.h
+++ b/baseboard/kukui/charger_mt6370.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/baseboard/kukui/emmc.c b/baseboard/kukui/emmc.c
index 68953d8923..8731d7259c 100644
--- a/baseboard/kukui/emmc.c
+++ b/baseboard/kukui/emmc.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -43,8 +43,8 @@
 
 #include "bootblock_data.h"
 
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SPI, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SPI, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SPI, format, ##args)
 
 #if EMMC_SPI_PORT == 1
 #define STM32_SPI_EMMC_REGS STM32_SPI1_REGS
@@ -68,7 +68,7 @@ static timestamp_t boot_deadline;
 
 /* 1024 bytes circular buffer is enough for ~0.6ms @ 13Mhz. */
 #define SPI_RX_BUF_BYTES 1024
-#define SPI_RX_BUF_WORDS (SPI_RX_BUF_BYTES/4)
+#define SPI_RX_BUF_WORDS (SPI_RX_BUF_BYTES / 4)
 static uint32_t in_msg[SPI_RX_BUF_WORDS];
 
 /* Macros to advance in the circular buffer. */
@@ -92,7 +92,7 @@ static const struct dma_option dma_tx_option = {
 static const struct dma_option dma_rx_option = {
 	STM32_DMAC_SPI_EMMC_RX, (void *)&STM32_SPI_EMMC_REGS->dr,
 	STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
-	STM32_DMA_CCR_CIRC
+		STM32_DMA_CCR_CIRC
 };
 
 /* Setup DMA to transfer bootblock. */
@@ -123,7 +123,7 @@ static void bootblock_stop(void)
 	 */
 	start = __hw_clock_source_read();
 	while (STM32_SPI_EMMC_REGS->sr & STM32_SPI_SR_FTLVL &&
-			__hw_clock_source_read() - start < timeout)
+	       __hw_clock_source_read() - start < timeout)
 		;
 
 	/* Then flush SPI FIFO, and make sure DAT line stays idle (high). */
@@ -152,8 +152,8 @@ static enum emmc_cmd emmc_parse_command(int index)
 	/* Number of leading ones. */
 	shift0 = __builtin_clz(~data[0]);
 
-	data[0] = (data[0] << shift0) | (data[1] >> (32-shift0));
-	data[1] = (data[1] << shift0) | (data[2] >> (32-shift0));
+	data[0] = (data[0] << shift0) | (data[1] >> (32 - shift0));
+	data[1] = (data[1] << shift0) | (data[2] >> (32 - shift0));
 
 	if (data[0] == 0x40000000 && data[1] == 0x0095ffff) {
 		/* 400000000095 GO_IDLE_STATE */
@@ -177,7 +177,6 @@ static enum emmc_cmd emmc_parse_command(int index)
 	return EMMC_ERROR;
 }
 
-
 /*
  * Wake the EMMC task when there is a falling edge on the CMD line, so that we
  * can capture the command.
diff --git a/baseboard/kukui/emmc_ite.c b/baseboard/kukui/emmc_ite.c
index b0e1f6b3de..2767199be0 100644
--- a/baseboard/kukui/emmc_ite.c
+++ b/baseboard/kukui/emmc_ite.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,7 +17,7 @@
 
 #include "bootblock_data.h"
 
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SPI, format, ##args)
 
 enum emmc_cmd {
 	EMMC_ERROR = -1,
@@ -129,7 +129,7 @@ static void emmc_bootblock_transfer(void)
 		/* Wait for FIFO1 or FIFO2 have been transmitted */
 		start = __hw_clock_source_read();
 		while (!(IT83XX_SPI_TXFSR & BIT(0)) &&
-			(__hw_clock_source_read() - start < timeout_us))
+		       (__hw_clock_source_read() - start < timeout_us))
 			;
 		/* Abort an ongoing transfer due to a command is received. */
 		if (IT83XX_SPI_ISR & IT83XX_SPI_RX_FIFO_FULL)
@@ -147,16 +147,16 @@ static enum emmc_cmd emmc_parse_command(int index, uint32_t *cmd0)
 	uint32_t data[3];
 
 	data[0] = htobe32(cmd0[index]);
-	data[1] = htobe32(cmd0[index+1]);
-	data[2] = htobe32(cmd0[index+2]);
+	data[1] = htobe32(cmd0[index + 1]);
+	data[2] = htobe32(cmd0[index + 2]);
 
 	if ((data[0] & 0xff000000) != 0x40000000) {
 		/* Figure out alignment (cmd starts with 01) */
 		/* Number of leading ones. */
 		shift0 = __builtin_clz(~data[0]);
 
-		data[0] = (data[0] << shift0) | (data[1] >> (32-shift0));
-		data[1] = (data[1] << shift0) | (data[2] >> (32-shift0));
+		data[0] = (data[0] << shift0) | (data[1] >> (32 - shift0));
+		data[1] = (data[1] << shift0) | (data[2] >> (32 - shift0));
 	}
 
 	if (data[0] == 0x40000000 && data[1] == 0x0095ffff) {
diff --git a/baseboard/kukui/usb_pd_policy.c b/baseboard/kukui/usb_pd_policy.c
index 28ef005ee8..2f2c141510 100644
--- a/baseboard/kukui/usb_pd_policy.c
+++ b/baseboard/kukui/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,8 +16,8 @@
 #include "usb_pd_policy.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 static int board_get_polarity(int port)
 {
@@ -30,8 +30,8 @@ static int board_get_polarity(int port)
 
 static uint8_t vbus_en;
 
-#define VBUS_EN_SYSJUMP_TAG		0x5645 /* VE */
-#define VBUS_EN_HOOK_VERSION	1
+#define VBUS_EN_SYSJUMP_TAG 0x5645 /* VE */
+#define VBUS_EN_HOOK_VERSION 1
 
 static void vbus_en_preserve_state(void)
 {
@@ -45,11 +45,11 @@ static void vbus_en_restore_state(void)
 	const uint8_t *prev_vbus_en;
 	int size, version;
 
-	prev_vbus_en = (const uint8_t *)system_get_jump_tag(
-		VBUS_EN_SYSJUMP_TAG, &version, &size);
+	prev_vbus_en = (const uint8_t *)system_get_jump_tag(VBUS_EN_SYSJUMP_TAG,
+							    &version, &size);
 
 	if (prev_vbus_en && version == VBUS_EN_HOOK_VERSION &&
-		size == sizeof(*prev_vbus_en)) {
+	    size == sizeof(*prev_vbus_en)) {
 		memcpy(&vbus_en, prev_vbus_en, sizeof(vbus_en));
 	}
 }
@@ -89,7 +89,8 @@ int pd_set_power_supply_ready(int port)
 
 	gpio_set_level(GPIO_EN_USBC_CHARGE_L, 1);
 	gpio_set_level(GPIO_EN_PP5000_USBC, 1);
-	if (IS_ENABLED(CONFIG_CHARGER_OTG) && IS_ENABLED(CONFIG_CHARGER_ISL9238C))
+	if (IS_ENABLED(CONFIG_CHARGER_OTG) &&
+	    IS_ENABLED(CONFIG_CHARGER_ISL9238C))
 		charger_set_current(CHARGER_SOLO, 0);
 
 	/* notify host of power info change */
@@ -142,7 +143,7 @@ __overridable int board_has_virtual_mux(void)
 }
 
 static void board_usb_mux_set(int port, mux_state_t mux_mode,
-		 enum usb_switch usb_mode, int polarity)
+			      enum usb_switch usb_mode, int polarity)
 {
 	usb_mux_set(port, mux_mode, usb_mode, polarity);
 
@@ -163,8 +164,9 @@ __override void svdm_safe_dp_mode(int port)
 __override int svdm_enter_dp_mode(int port, uint32_t mode_caps)
 {
 	/* Kukui/Krane doesn't support superspeed lanes. */
-	const uint32_t support_pin_mode = board_has_virtual_mux() ?
-		(MODE_DP_PIN_C | MODE_DP_PIN_E) : MODE_DP_PIN_ALL;
+	const uint32_t support_pin_mode =
+		board_has_virtual_mux() ? (MODE_DP_PIN_C | MODE_DP_PIN_E) :
+					  MODE_DP_PIN_ALL;
 
 	/**
 	 * Only enter mode if device is DFP_D (and PIN_C/E for Kukui/Krane)
@@ -205,11 +207,11 @@ __override int svdm_dp_config(int port, uint32_t *payload)
 			port, mf_pref ? USB_PD_MUX_DOCK : USB_PD_MUX_DP_ENABLED,
 			USB_SWITCH_CONNECT, board_get_polarity(port));
 
-	payload[0] = VDO(USB_SID_DISPLAYPORT, 1,
-			 CMD_DP_CONFIG | VDO_OPOS(opos));
-	payload[1] = VDO_DP_CFG(pin_mode,      /* pin mode */
-				1,             /* DPv1.3 signaling */
-				2);            /* UFP connected */
+	payload[0] =
+		VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_CONFIG | VDO_OPOS(opos));
+	payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */
+				1, /* DPv1.3 signaling */
+				2); /* UFP connected */
 	return 2;
 };
 
@@ -227,8 +229,8 @@ __override void svdm_dp_post_config(int port)
 	/* set the minimum time delay (2ms) for the next HPD IRQ */
 	svdm_hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
 
-	usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL |
-				 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+	usb_mux_hpd_update(port,
+			   USB_PD_MUX_HPD_LVL | USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
 
 __override int svdm_dp_attention(int port, uint32_t *payload)
@@ -267,8 +269,8 @@ __override int svdm_dp_attention(int port, uint32_t *payload)
 #endif
 
 		/* set the minimum time delay (2ms) for the next HPD IRQ */
-		svdm_hpd_deadline[port] = get_time().val +
-			HPD_USTREAM_DEBOUNCE_LVL;
+		svdm_hpd_deadline[port] =
+			get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
 	} else if (irq & !lvl) {
 		CPRINTF("ERR:HPD:IRQ&LOW\n");
 		return 0; /* nak */
@@ -278,8 +280,8 @@ __override int svdm_dp_attention(int port, uint32_t *payload)
 		board_set_dp_mux_control(lvl, board_get_polarity(port));
 #endif
 		/* set the minimum time delay (2ms) for the next HPD IRQ */
-		svdm_hpd_deadline[port] = get_time().val +
-			HPD_USTREAM_DEBOUNCE_LVL;
+		svdm_hpd_deadline[port] =
+			get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
 	}
 
 	/* ack */
@@ -293,6 +295,6 @@ __override void svdm_exit_dp_mode(int port)
 	board_set_dp_mux_control(0, 0);
 #endif
 	usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-				 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
 #endif /* CONFIG_USB_PD_ALT_MODE_DFP */
diff --git a/baseboard/kukui/usb_pd_policy.h b/baseboard/kukui/usb_pd_policy.h
index 78e0213f53..62d6bda062 100644
--- a/baseboard/kukui/usb_pd_policy.h
+++ b/baseboard/kukui/usb_pd_policy.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/baseboard/mtscp-rv32i/baseboard.c b/baseboard/mtscp-rv32i/baseboard.c
index ac261c3aa8..c86ef15ad7 100644
--- a/baseboard/mtscp-rv32i/baseboard.c
+++ b/baseboard/mtscp-rv32i/baseboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,28 +7,31 @@
 #include "cache.h"
 #include "csr.h"
 #include "hooks.h"
+#include "panic.h"
 #include "registers.h"
 
 #define SCP_SRAM_END (CONFIG_IPC_SHARED_OBJ_ADDR & (~(0x400 - 1)))
 
 struct mpu_entry mpu_entries[NR_MPU_ENTRIES] = {
 	/* SRAM (for most code, data) */
-	{0, SCP_SRAM_END, MPU_ATTR_C | MPU_ATTR_W | MPU_ATTR_R},
+	{ 0, SCP_SRAM_END, MPU_ATTR_C | MPU_ATTR_W | MPU_ATTR_R },
 	/* SRAM (for IPI shared buffer) */
-	{SCP_SRAM_END, SCP_FW_END, MPU_ATTR_W | MPU_ATTR_R},
-	/* For AP domain */
+	{ SCP_SRAM_END, SCP_FW_END, MPU_ATTR_W | MPU_ATTR_R },
+/* For AP domain */
 #ifdef CHIP_VARIANT_MT8195
-	{0x60000000, 0x70000000, MPU_ATTR_W | MPU_ATTR_R | MPU_ATTR_P},
+	{ 0x60000000, 0x70000000, MPU_ATTR_W | MPU_ATTR_R | MPU_ATTR_P },
 #else
-	{0x60000000, 0x70000000, MPU_ATTR_W | MPU_ATTR_R},
+	{ 0x60000000, 0x70000000, MPU_ATTR_W | MPU_ATTR_R },
 #endif
 	/* For SCP sys */
-	{0x70000000, 0x80000000, MPU_ATTR_W | MPU_ATTR_R},
+	{ 0x70000000, 0x80000000, MPU_ATTR_W | MPU_ATTR_R },
 #ifdef CHIP_VARIANT_MT8195
-	{0x10000000, 0x11400000, MPU_ATTR_C | MPU_ATTR_W | MPU_ATTR_R},
-	{CONFIG_PANIC_DRAM_BASE, CONFIG_PANIC_DRAM_BASE + CONFIG_PANIC_DRAM_SIZE, MPU_ATTR_W | MPU_ATTR_R},
+	{ 0x10000000, 0x11400000, MPU_ATTR_C | MPU_ATTR_W | MPU_ATTR_R },
+	{ CONFIG_PANIC_DRAM_BASE,
+	  CONFIG_PANIC_DRAM_BASE + CONFIG_PANIC_DRAM_SIZE,
+	  MPU_ATTR_W | MPU_ATTR_R },
 #else
-	{0x10000000, 0x11400000, MPU_ATTR_W | MPU_ATTR_R},
+	{ 0x10000000, 0x11400000, MPU_ATTR_W | MPU_ATTR_R },
 #endif
 };
 
@@ -37,7 +40,7 @@ struct mpu_entry mpu_entries[NR_MPU_ENTRIES] = {
 #ifdef CONFIG_PANIC_CONSOLE_OUTPUT
 static void report_previous_panic(void)
 {
-	struct panic_data * panic = panic_get_data();
+	struct panic_data *panic = panic_get_data();
 
 	if (panic == NULL && SCP_CORE0_MON_PC_LATCH == 0)
 		return;
@@ -48,11 +51,8 @@ static void report_previous_panic(void)
 	} else {
 		ccprintf("No panic data\n");
 	}
-	ccprintf("Latch PC:%x LR:%x SP:%x\n",
-		SCP_CORE0_MON_PC_LATCH,
-		SCP_CORE0_MON_LR_LATCH,
-		SCP_CORE0_MON_SP_LATCH);
-
+	ccprintf("Latch PC:%x LR:%x SP:%x\n", SCP_CORE0_MON_PC_LATCH,
+		 SCP_CORE0_MON_LR_LATCH, SCP_CORE0_MON_SP_LATCH);
 }
 DECLARE_HOOK(HOOK_INIT, report_previous_panic, HOOK_PRIO_DEFAULT);
 #endif
diff --git a/baseboard/mtscp-rv32i/baseboard.h b/baseboard/mtscp-rv32i/baseboard.h
index 3af9fe1af9..49a18c8d9d 100644
--- a/baseboard/mtscp-rv32i/baseboard.h
+++ b/baseboard/mtscp-rv32i/baseboard.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,8 +21,8 @@
 
 /* IPI configs */
 #define CONFIG_IPC_SHARED_OBJ_BUF_SIZE 288
-#define CONFIG_IPC_SHARED_OBJ_ADDR                                             \
-	(SCP_FW_END -                                                         \
+#define CONFIG_IPC_SHARED_OBJ_ADDR \
+	(SCP_FW_END -              \
 	 (CONFIG_IPC_SHARED_OBJ_BUF_SIZE + 2 * 4 /* int32_t */) * 2)
 #define CONFIG_IPI
 #define CONFIG_RPMSG_NAME_SERVICE
@@ -62,7 +62,8 @@
 #define CONFIG_PANIC_BASE_OFFSET 0x100 /* reserved for jump data */
 
 #ifdef CHIP_VARIANT_MT8195
-#define CONFIG_PANIC_DATA_BASE (CONFIG_PANIC_DRAM_BASE + CONFIG_PANIC_BASE_OFFSET)
+#define CONFIG_PANIC_DATA_BASE \
+	(CONFIG_PANIC_DRAM_BASE + CONFIG_PANIC_BASE_OFFSET)
 #endif
 
 /* MPU settings */
diff --git a/baseboard/mtscp-rv32i/build.mk b/baseboard/mtscp-rv32i/build.mk
index 420a3a4e08..90b8ded4a1 100644
--- a/baseboard/mtscp-rv32i/build.mk
+++ b/baseboard/mtscp-rv32i/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/baseboard/mtscp-rv32i/mdp.c b/baseboard/mtscp-rv32i/mdp.c
index b0756a797a..4c054dc029 100644
--- a/baseboard/mtscp-rv32i/mdp.c
+++ b/baseboard/mtscp-rv32i/mdp.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,19 +19,23 @@ static void event_mdp_written(struct consumer const *consumer, size_t count)
 	task_wake(TASK_ID_MDP_SERVICE);
 }
 static struct consumer const event_mdp_consumer;
-static struct queue const event_mdp_queue = QUEUE_DIRECT(4,
-	struct mdp_msg_service, null_producer, event_mdp_consumer);
+static struct queue const event_mdp_queue = QUEUE_DIRECT(
+	4, struct mdp_msg_service, null_producer, event_mdp_consumer);
 static struct consumer const event_mdp_consumer = {
 	.queue = &event_mdp_queue,
-	.ops = &((struct consumer_ops const) {
+	.ops = &((struct consumer_ops const){
 		.written = event_mdp_written,
 	}),
 };
 
 /* Stub functions only provided by private overlays. */
 #ifndef HAVE_PRIVATE_MT_SCP
-void mdp_common_init(void) {}
-void mdp_ipi_task_handler(void *pvParameters) {}
+void mdp_common_init(void)
+{
+}
+void mdp_ipi_task_handler(void *pvParameters)
+{
+}
 #endif
 
 static void mdp_ipi_handler(int id, void *data, unsigned int len)
diff --git a/baseboard/mtscp-rv32i/mdp.h b/baseboard/mtscp-rv32i/mdp.h
index eea3ffb289..48f4937ace 100644
--- a/baseboard/mtscp-rv32i/mdp.h
+++ b/baseboard/mtscp-rv32i/mdp.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,10 +11,10 @@ struct mdp_msg_service {
 	unsigned char msg[20];
 };
 BUILD_ASSERT(member_size(struct mdp_msg_service, msg) <=
-		CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
+	     CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
 
 /* Functions provided by private overlay. */
 void mdp_common_init(void);
 void mdp_ipi_task_handler(void *pvParameters);
 
-#endif  /* __CROS_EC_SCP_MDP_H */
+#endif /* __CROS_EC_SCP_MDP_H */
diff --git a/baseboard/mtscp-rv32i/vdec.c b/baseboard/mtscp-rv32i/vdec.c
index c3f5f5a9cf..7ff98fff10 100644
--- a/baseboard/mtscp-rv32i/vdec.c
+++ b/baseboard/mtscp-rv32i/vdec.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,11 +21,11 @@ static void event_vdec_written(struct consumer const *consumer, size_t count)
 	task_wake(TASK_ID_VDEC_SERVICE);
 }
 static struct consumer const event_vdec_consumer;
-static struct queue const event_vdec_queue = QUEUE_DIRECT(8,
-	struct vdec_msg, null_producer, event_vdec_consumer);
+static struct queue const event_vdec_queue =
+	QUEUE_DIRECT(8, struct vdec_msg, null_producer, event_vdec_consumer);
 static struct consumer const event_vdec_consumer = {
 	.queue = &event_vdec_queue,
-	.ops = &((struct consumer_ops const) {
+	.ops = &((struct consumer_ops const){
 		.written = event_vdec_written,
 	}),
 };
@@ -36,19 +36,23 @@ static void event_vdec_core_written(struct consumer const *consumer,
 	task_wake(TASK_ID_VDEC_CORE_SERVICE);
 }
 static struct consumer const event_vdec_core_consumer;
-static struct queue const event_vdec_core_queue = QUEUE_DIRECT(8,
-	struct vdec_msg, null_producer, event_vdec_core_consumer);
+static struct queue const event_vdec_core_queue = QUEUE_DIRECT(
+	8, struct vdec_msg, null_producer, event_vdec_core_consumer);
 static struct consumer const event_vdec_core_consumer = {
 	.queue = &event_vdec_core_queue,
-	.ops = &((struct consumer_ops const) {
+	.ops = &((struct consumer_ops const){
 		.written = event_vdec_core_written,
 	}),
 };
 
 /* Stub functions only provided by private overlays. */
 #ifndef HAVE_PRIVATE_MT_SCP
-void vdec_msg_handler(void *data) {}
-void vdec_core_msg_handler(void *data) {}
+void vdec_msg_handler(void *data)
+{
+}
+void vdec_core_msg_handler(void *data)
+{
+}
 #endif
 
 static void vdec_h264_ipi_handler(int id, void *data, uint32_t len)
diff --git a/baseboard/mtscp-rv32i/vdec.h b/baseboard/mtscp-rv32i/vdec.h
index cdc16ba9e0..c203c09fae 100644
--- a/baseboard/mtscp-rv32i/vdec.h
+++ b/baseboard/mtscp-rv32i/vdec.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,7 +19,7 @@ struct vdec_msg {
 	unsigned char msg[48];
 };
 BUILD_ASSERT(member_size(struct vdec_msg, msg) <=
-		CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
+	     CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
 
 /* Functions provided by private overlay. */
 void vdec_core_msg_handler(void *msg);
diff --git a/baseboard/mtscp-rv32i/venc.c b/baseboard/mtscp-rv32i/venc.c
index 09bb0cbd39..bed2a2dbc6 100644
--- a/baseboard/mtscp-rv32i/venc.c
+++ b/baseboard/mtscp-rv32i/venc.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,18 +21,20 @@ static void event_venc_written(struct consumer const *consumer, size_t count)
 	task_wake(TASK_ID_VENC_SERVICE);
 }
 static struct consumer const event_venc_consumer;
-static struct queue const event_venc_queue = QUEUE_DIRECT(8,
-	struct venc_msg, null_producer, event_venc_consumer);
+static struct queue const event_venc_queue =
+	QUEUE_DIRECT(8, struct venc_msg, null_producer, event_venc_consumer);
 static struct consumer const event_venc_consumer = {
 	.queue = &event_venc_queue,
-	.ops = &((struct consumer_ops const) {
+	.ops = &((struct consumer_ops const){
 		.written = event_venc_written,
 	}),
 };
 
 /* Stub functions only provided by private overlays. */
 #ifndef HAVE_PRIVATE_MT_SCP
-void venc_h264_msg_handler(void *data) {}
+void venc_h264_msg_handler(void *data)
+{
+}
 #endif
 
 static void venc_h264_ipi_handler(int id, void *data, uint32_t len)
diff --git a/baseboard/mtscp-rv32i/venc.h b/baseboard/mtscp-rv32i/venc.h
index 47454c4507..c5c7df3883 100644
--- a/baseboard/mtscp-rv32i/venc.h
+++ b/baseboard/mtscp-rv32i/venc.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,7 +18,7 @@ struct venc_msg {
 	unsigned char msg[288];
 };
 BUILD_ASSERT(member_size(struct venc_msg, msg) <=
-		CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
+	     CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
 
 /* Functions provided by private overlay. */
 void venc_h264_msg_handler(void *data);
diff --git a/baseboard/nucleo-f412zg/base-board.c b/baseboard/nucleo-f412zg/base-board.c
index 15e46f006e..53c42e5a26 100644
--- a/baseboard/nucleo-f412zg/base-board.c
+++ b/baseboard/nucleo-f412zg/base-board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/baseboard/nucleo-f412zg/base-board.h b/baseboard/nucleo-f412zg/base-board.h
index d41cdfd207..0ce6c226e2 100644
--- a/baseboard/nucleo-f412zg/base-board.h
+++ b/baseboard/nucleo-f412zg/base-board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -50,28 +50,28 @@
 
 #define CONFIG_FLASH_WRITE_SIZE STM32_FLASH_WRITE_SIZE_3300
 
-#define CONFIG_SHAREDLIB_SIZE   0
+#define CONFIG_SHAREDLIB_SIZE 0
 
-#define CONFIG_RO_MEM_OFF       0
-#define CONFIG_RO_STORAGE_OFF   0
-#define CONFIG_RO_SIZE          (128 * 1024)
+#define CONFIG_RO_MEM_OFF 0
+#define CONFIG_RO_STORAGE_OFF 0
+#define CONFIG_RO_SIZE (128 * 1024)
 
 /* EC rollback protection block */
 #define CONFIG_ROLLBACK_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
 #define CONFIG_ROLLBACK_SIZE (128 * 1024 * 2) /* 2 blocks of 128KB each */
 
-#define CONFIG_RW_MEM_OFF	(CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE)
-#define CONFIG_RW_STORAGE_OFF	0
-#define CONFIG_RW_SIZE		(CONFIG_FLASH_SIZE_BYTES -		\
-				(CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF))
+#define CONFIG_RW_MEM_OFF (CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE)
+#define CONFIG_RW_STORAGE_OFF 0
+#define CONFIG_RW_SIZE \
+	(CONFIG_FLASH_SIZE_BYTES - (CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF))
 
-#define CONFIG_EC_PROTECTED_STORAGE_OFF         CONFIG_RO_MEM_OFF
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE        CONFIG_RO_SIZE
-#define CONFIG_EC_WRITABLE_STORAGE_OFF          CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE         CONFIG_RW_SIZE
+#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF
+#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE
+#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE
 
-#define CONFIG_WP_STORAGE_OFF           CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE          CONFIG_EC_PROTECTED_STORAGE_SIZE
+#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
+#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
 
 /*
  * We want to prevent flash readout, and use it as indicator of protection
@@ -116,7 +116,7 @@
  */
 #undef CONFIG_ROLLBACK_SECRET_LOCAL_ENTROPY_SIZE
 #ifdef SECTION_IS_RW
-	#undef CONFIG_ROLLBACK_UPDATE
+#undef CONFIG_ROLLBACK_UPDATE
 #endif
 
 /*-------------------------------------------------------------------------*
@@ -124,9 +124,9 @@
  *-------------------------------------------------------------------------*/
 
 #ifdef SECTION_IS_RO
-	/* RO verifies the RW partition signature */
-	#define CONFIG_RSA
-	#define CONFIG_RWSIG
+/* RO verifies the RW partition signature */
+#define CONFIG_RSA
+#define CONFIG_RWSIG
 #endif /* SECTION_IS_RO */
 #define CONFIG_RSA_KEY_SIZE 3072
 #define CONFIG_RSA_EXPONENT_3
@@ -164,7 +164,7 @@
 #define CONFIG_HOST_COMMAND_STATUS
 #define CONFIG_MKBP_EVENT
 #define CONFIG_MKBP_USE_GPIO
-#define CONFIG_PRINTF_LEGACY_LI_FORMAT
+#define CONFIG_PRINTF_LONG_IS_32BITS
 #define CONFIG_RNG
 #define CONFIG_SHA256
 #define CONFIG_SHA256_UNROLLED
@@ -172,27 +172,27 @@
 #define CONFIG_WP_ACTIVE_HIGH
 
 #ifndef TEST_BUILD
-	/* TODO(hesling): Fix the illogical dependency between spi.c
-	 *                and host_command.c
-	 *
-	 * Currently, the chip/stm32/spi.c depends on functions defined in
-	 * common/host_command.c. When unit test builds use their own tasklist
-	 * without the HOSTCMD task, host_command.c is excluded from the build,
-	 * but chip/stm32/spi.c remains (because of CONFIG_SPI).
-	 * This triggers an undefined reference linker error.
-	 * The reproduce case:
-	 * - Allow CONFIG_SPI in TEST_BUILDs
-	 * - make BOARD=nucleo-h743zi tests
-	 */
-	#define CONFIG_SPI
+/* TODO(hesling): Fix the illogical dependency between spi.c
+ *                and host_command.c
+ *
+ * Currently, the chip/stm32/spi.c depends on functions defined in
+ * common/host_command.c. When unit test builds use their own tasklist
+ * without the HOSTCMD task, host_command.c is excluded from the build,
+ * but chip/stm32/spi.c remains (because of CONFIG_SPI).
+ * This triggers an undefined reference linker error.
+ * The reproduce case:
+ * - Allow CONFIG_SPI in TEST_BUILDs
+ * - make BOARD=nucleo-h743zi tests
+ */
+#define CONFIG_SPI
 #endif
 
 #ifndef __ASSEMBLER__
-	/* Timer selection */
-	#define TIM_CLOCK32 2
-	#define TIM_WATCHDOG 16
-	#include "gpio_signal.h"
-	void button_event(enum gpio_signal signal);
+/* Timer selection */
+#define TIM_CLOCK32 2
+#define TIM_WATCHDOG 16
+#include "gpio_signal.h"
+void button_event(enum gpio_signal signal);
 #endif /* !__ASSEMBLER__ */
 
 #endif /* __CROS_EC_BASE_BOARD_H */
diff --git a/baseboard/nucleo-f412zg/base-gpio.inc b/baseboard/nucleo-f412zg/base-gpio.inc
index 4ebd99f91f..d0c48a46e5 100644
--- a/baseboard/nucleo-f412zg/base-gpio.inc
+++ b/baseboard/nucleo-f412zg/base-gpio.inc
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/baseboard/nucleo-f412zg/build.mk b/baseboard/nucleo-f412zg/build.mk
index 1456331fec..d38a618d8c 100644
--- a/baseboard/nucleo-f412zg/build.mk
+++ b/baseboard/nucleo-f412zg/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/baseboard/nucleo-f412zg/openocd-flash.cfg b/baseboard/nucleo-f412zg/openocd-flash.cfg
index 3333d1163a..cbc9fe0218 100644
--- a/baseboard/nucleo-f412zg/openocd-flash.cfg
+++ b/baseboard/nucleo-f412zg/openocd-flash.cfg
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/baseboard/nucleo-f412zg/openocd.cfg b/baseboard/nucleo-f412zg/openocd.cfg
index 589d4400f4..3b286a4ebc 100644
--- a/baseboard/nucleo-f412zg/openocd.cfg
+++ b/baseboard/nucleo-f412zg/openocd.cfg
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/baseboard/nucleo-h743zi/base-board.c b/baseboard/nucleo-h743zi/base-board.c
index 15e46f006e..53c42e5a26 100644
--- a/baseboard/nucleo-h743zi/base-board.c
+++ b/baseboard/nucleo-h743zi/base-board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/baseboard/nucleo-h743zi/base-board.h b/baseboard/nucleo-h743zi/base-board.h
index df5e4bfa8c..eb4b8ac1fa 100644
--- a/baseboard/nucleo-h743zi/base-board.h
+++ b/baseboard/nucleo-h743zi/base-board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -53,25 +53,25 @@
  *
  * We need 2 independently erasable blocks, at a minimum.
  */
-#define CONFIG_ROLLBACK_SIZE   (2 * CONFIG_FLASH_BANK_SIZE)
-#define CONFIG_ROLLBACK_OFF    ((CONFIG_FLASH_SIZE_BYTES / 2) - \
-				CONFIG_ROLLBACK_SIZE)
+#define CONFIG_ROLLBACK_SIZE (2 * CONFIG_FLASH_BANK_SIZE)
+#define CONFIG_ROLLBACK_OFF \
+	((CONFIG_FLASH_SIZE_BYTES / 2) - CONFIG_ROLLBACK_SIZE)
 
-#define CONFIG_RO_MEM_OFF      0
-#define CONFIG_RO_SIZE         CONFIG_ROLLBACK_OFF
-#define CONFIG_RW_MEM_OFF      (CONFIG_FLASH_SIZE_BYTES / 2)
-#define CONFIG_RW_SIZE         (CONFIG_FLASH_SIZE_BYTES / 2)
+#define CONFIG_RO_MEM_OFF 0
+#define CONFIG_RO_SIZE CONFIG_ROLLBACK_OFF
+#define CONFIG_RW_MEM_OFF (CONFIG_FLASH_SIZE_BYTES / 2)
+#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE_BYTES / 2)
 
-#define CONFIG_RO_STORAGE_OFF  0
-#define CONFIG_RW_STORAGE_OFF  0
+#define CONFIG_RO_STORAGE_OFF 0
+#define CONFIG_RW_STORAGE_OFF 0
 
-#define CONFIG_EC_PROTECTED_STORAGE_OFF   CONFIG_RO_MEM_OFF
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE  CONFIG_RO_SIZE
-#define CONFIG_EC_WRITABLE_STORAGE_OFF    CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE   CONFIG_RW_SIZE
+#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF
+#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE
+#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE
 
-#define CONFIG_WP_STORAGE_OFF             CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE            CONFIG_EC_PROTECTED_STORAGE_SIZE
+#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
+#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
 
 /* Disabled features */
 
@@ -92,31 +92,31 @@
 #define CONFIG_LOW_POWER_IDLE
 #define CONFIG_MKBP_EVENT
 #define CONFIG_MKBP_USE_GPIO
-#define CONFIG_PRINTF_LEGACY_LI_FORMAT
+#define CONFIG_PRINTF_LONG_IS_32BITS
 #define CONFIG_RNG
 #define CONFIG_RWSIG_TYPE_RWSIG
 #define CONFIG_SHA256
 #define CONFIG_SHA256_UNROLLED
 #undef CONFIG_SHAREDLIB_SIZE
-#define CONFIG_SHAREDLIB_SIZE   0
+#define CONFIG_SHAREDLIB_SIZE 0
 #define CONFIG_STM_HWTIMER32
 #define CONFIG_WATCHDOG_HELP
 #define CONFIG_WP_ACTIVE_HIGH
 
 #ifndef TEST_BUILD
-	/* TODO(hesling): Fix the illogical dependency between spi.c
-	 *                and host_command.c
-	 *
-	 * Currently, the chip/stm32/spi.c depends on functions defined in
-	 * common/host_command.c. When unit test builds use their own tasklist
-	 * without the HOSTCMD task, host_command.c is excluded from the build,
-	 * but chip/stm32/spi.c remains (because of CONFIG_SPI).
-	 * This triggers an undefined reference linker error.
-	 * The reproduce case:
-	 * - Allow CONFIG_SPI in TEST_BUILDs
-	 * - make BOARD=nucleo-h743zi tests
-	 */
-#	define CONFIG_SPI
+/* TODO(hesling): Fix the illogical dependency between spi.c
+ *                and host_command.c
+ *
+ * Currently, the chip/stm32/spi.c depends on functions defined in
+ * common/host_command.c. When unit test builds use their own tasklist
+ * without the HOSTCMD task, host_command.c is excluded from the build,
+ * but chip/stm32/spi.c remains (because of CONFIG_SPI).
+ * This triggers an undefined reference linker error.
+ * The reproduce case:
+ * - Allow CONFIG_SPI in TEST_BUILDs
+ * - make BOARD=nucleo-h743zi tests
+ */
+#define CONFIG_SPI
 #endif
 
 /*
@@ -146,10 +146,10 @@
 #define CONFIG_CMD_IDLE_STATS
 
 #ifdef SECTION_IS_RO
-	/* RO verifies the RW partition signature */
-#	define CONFIG_RSA
-#	define CONFIG_RWSIG
-#endif  /* SECTION_IS_RO */
+/* RO verifies the RW partition signature */
+#define CONFIG_RSA
+#define CONFIG_RWSIG
+#endif /* SECTION_IS_RO */
 
 #define CONFIG_RSA_KEY_SIZE 3072
 #define CONFIG_RSA_EXPONENT_3
@@ -160,7 +160,7 @@
  */
 #undef CONFIG_ROLLBACK_SECRET_LOCAL_ENTROPY_SIZE
 #ifdef SECTION_IS_RW
-#	undef CONFIG_ROLLBACK_UPDATE
+#undef CONFIG_ROLLBACK_UPDATE
 #endif
 /*
  * Add rollback protection
@@ -169,11 +169,11 @@
 #define CONFIG_ROLLBACK_MPU_PROTECT
 
 #ifndef __ASSEMBLER__
-	/* Timer selection */
-#	define TIM_CLOCK32 2
-#	define TIM_WATCHDOG 16
-#	include "gpio_signal.h"
-	void button_event(enum gpio_signal signal);
+/* Timer selection */
+#define TIM_CLOCK32 2
+#define TIM_WATCHDOG 16
+#include "gpio_signal.h"
+void button_event(enum gpio_signal signal);
 #endif /* !__ASSEMBLER__ */
 
 #endif /* __CROS_EC_BASE_BOARD_H */
diff --git a/baseboard/nucleo-h743zi/base-ec.tasklist b/baseboard/nucleo-h743zi/base-ec.tasklist
index fae8952113..e8e752aa4e 100644
--- a/baseboard/nucleo-h743zi/base-ec.tasklist
+++ b/baseboard/nucleo-h743zi/base-ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/baseboard/nucleo-h743zi/base-gpio.inc b/baseboard/nucleo-h743zi/base-gpio.inc
index ef224cbaf1..ad7d313328 100644
--- a/baseboard/nucleo-h743zi/base-gpio.inc
+++ b/baseboard/nucleo-h743zi/base-gpio.inc
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/baseboard/nucleo-h743zi/build.mk b/baseboard/nucleo-h743zi/build.mk
index 470214aabc..36c0cfdf50 100644
--- a/baseboard/nucleo-h743zi/build.mk
+++ b/baseboard/nucleo-h743zi/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/baseboard/nucleo-h743zi/openocd-flash.cfg b/baseboard/nucleo-h743zi/openocd-flash.cfg
index 4517266d7b..8ee5dd6707 100644
--- a/baseboard/nucleo-h743zi/openocd-flash.cfg
+++ b/baseboard/nucleo-h743zi/openocd-flash.cfg
@@ -1,4 +1,4 @@
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/baseboard/nucleo-h743zi/openocd.cfg b/baseboard/nucleo-h743zi/openocd.cfg
index 528e8d6cab..9fa8aa89a9 100644
--- a/baseboard/nucleo-h743zi/openocd.cfg
+++ b/baseboard/nucleo-h743zi/openocd.cfg
@@ -1,4 +1,4 @@
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/baseboard/octopus/baseboard.c b/baseboard/octopus/baseboard.c
index 4f338ab131..0f012d1352 100644
--- a/baseboard/octopus/baseboard.c
+++ b/baseboard/octopus/baseboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,8 +27,8 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /******************************************************************************/
 /* Keyboard scan setting */
@@ -218,9 +218,9 @@ int board_is_i2c_port_powered(int port)
 enum adc_channel board_get_vbus_adc(int port)
 {
 	if (port == 0)
-		return  ADC_VBUS_C0;
+		return ADC_VBUS_C0;
 	if (port == 1)
-		return  ADC_VBUS_C1;
+		return ADC_VBUS_C1;
 	CPRINTSUSB("Unknown vbus adc port id: %d", port);
 	return ADC_VBUS_C0;
 }
@@ -238,27 +238,26 @@ void baseboard_tcpc_init(void)
 	 */
 	for (int port = 0; port < board_get_usb_pd_port_count(); ++port)
 		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
 /* Called after the cbi_init (via +2) */
 DECLARE_HOOK(HOOK_INIT, baseboard_tcpc_init, HOOK_PRIO_INIT_I2C + 2);
 
 int board_set_active_charge_port(int port)
 {
-	int is_valid_port = (port >= 0 &&
-			    port < board_get_usb_pd_port_count());
+	int is_valid_port = (port >= 0 && port < board_get_usb_pd_port_count());
 	int i;
 
 	if (!is_valid_port && port != CHARGE_PORT_NONE)
 		return EC_ERROR_INVAL;
 
-
 	if (port == CHARGE_PORT_NONE) {
 		CPRINTSUSB("Disabling all charger ports");
 
 		/* Disable all ports. */
-		for (i = 0; (i < ppc_cnt) &&
-		    (i < board_get_usb_pd_port_count()); i++) {
+		for (i = 0;
+		     (i < ppc_cnt) && (i < board_get_usb_pd_port_count());
+		     i++) {
 			/*
 			 * Do not return early if one fails otherwise we can
 			 * get into a boot loop assertion failure.
@@ -282,8 +281,7 @@ int board_set_active_charge_port(int port)
 	 * Turn off the other ports' sink path FETs, before enabling the
 	 * requested charge port.
 	 */
-	for (i = 0; (i < ppc_cnt) &&
-	    (i < board_get_usb_pd_port_count()); i++) {
+	for (i = 0; (i < ppc_cnt) && (i < board_get_usb_pd_port_count()); i++) {
 		if (i == port)
 			continue;
 
@@ -300,8 +298,8 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	/*
 	 * Empirically, the charger seems to draw a little more current that
@@ -310,9 +308,8 @@ void board_set_charge_limit(int port, int supplier, int charge_ma,
 #if defined(CONFIG_CHARGER_BQ25710) || defined(CONFIG_CHARGER_ISL9238)
 	charge_ma = (charge_ma * 95) / 100;
 #endif
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 void board_hibernate(void)
diff --git a/baseboard/octopus/baseboard.h b/baseboard/octopus/baseboard.h
index da564f5056..724540d0f0 100644
--- a/baseboard/octopus/baseboard.h
+++ b/baseboard/octopus/baseboard.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,11 +12,13 @@
  * EC Config
  */
 
+#define CONFIG_LTO
+
 /*
  * By default, enable all console messages excepted HC, ACPI and event:
  * The sensor stack is generating a lot of activity.
  */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
 
 /*
  * Variant EC defines. Pick one:
@@ -24,59 +26,59 @@
  * VARIANT_OCTOPUS_EC_ITE8320
  */
 #if defined(VARIANT_OCTOPUS_EC_NPCX796FB)
-	/* NPCX7 config */
-	#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
-	#define NPCX_TACH_SEL2    0  /* [0:GPIO40/73, 1:GPIO93/A6] as TACH */
-	#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
-
-	/* Internal SPI flash on NPCX7 */
-	/* Flash is 1MB but reserve half for future use. */
-	#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
-
-	#define CONFIG_SPI_FLASH_REGS
-	#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
-
-	/* I2C Bus Configuration */
-	#define I2C_PORT_BATTERY	NPCX_I2C_PORT0_0
-	#define I2C_PORT_TCPC0		NPCX_I2C_PORT1_0
-	#define I2C_PORT_TCPC1		NPCX_I2C_PORT2_0
-	#define I2C_PORT_EEPROM		NPCX_I2C_PORT3_0
-	#define I2C_PORT_CHARGER	NPCX_I2C_PORT4_1
-	#define I2C_PORT_SENSOR		NPCX_I2C_PORT7_0
-	#define I2C_ADDR_EEPROM_FLAGS	0x50
-
-	/* Enable PSL hibernate mode. */
-	#define CONFIG_HIBERNATE_PSL
-
-	/* EC variant determines USB-C variant */
-	#define VARIANT_OCTOPUS_USBC_STANDALONE_TCPCS
-
-	/* Allow the EC to enter deep sleep in S0 */
-	#define CONFIG_LOW_POWER_S0
+/* NPCX7 config */
+#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */
+#define NPCX_TACH_SEL2 0 /* [0:GPIO40/73, 1:GPIO93/A6] as TACH */
+#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */
+
+/* Internal SPI flash on NPCX7 */
+/* Flash is 1MB but reserve half for future use. */
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
+
+#define CONFIG_SPI_FLASH_REGS
+#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
+
+/* I2C Bus Configuration */
+#define I2C_PORT_BATTERY NPCX_I2C_PORT0_0
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT1_0
+#define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT3_0
+#define I2C_PORT_CHARGER NPCX_I2C_PORT4_1
+#define I2C_PORT_SENSOR NPCX_I2C_PORT7_0
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+
+/* Enable PSL hibernate mode. */
+#define CONFIG_HIBERNATE_PSL
+
+/* EC variant determines USB-C variant */
+#define VARIANT_OCTOPUS_USBC_STANDALONE_TCPCS
+
+/* Allow the EC to enter deep sleep in S0 */
+#define CONFIG_LOW_POWER_S0
 #elif defined(VARIANT_OCTOPUS_EC_ITE8320)
-	/* IT83XX config */
-	#define CONFIG_IT83XX_VCC_1P8V
-	/* I2C Bus Configuration */
-	#define I2C_PORT_BATTERY	IT83XX_I2C_CH_A	/* Shared bus */
-	#define I2C_PORT_CHARGER	IT83XX_I2C_CH_A	/* Shared bus */
-	#define I2C_PORT_SENSOR		IT83XX_I2C_CH_B
-	#define I2C_PORT_USBC0		IT83XX_I2C_CH_C
-	#define I2C_PORT_USBC1		IT83XX_I2C_CH_E
-	#define I2C_PORT_USB_MUX	I2C_PORT_USBC0	/* For MUX driver */
-	#define I2C_PORT_EEPROM		IT83XX_I2C_CH_F
-	#define I2C_ADDR_EEPROM_FLAGS	0x50
-	#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 2
-
-	/* EC variant determines USB-C variant */
-	#define VARIANT_OCTOPUS_USBC_ITE_EC_TCPCS
-
-	/*
-	 * Limit maximal ODR to 125Hz, the EC is using ~5ms per sample at
-	 * 48MHz core cpu clock.
-	 */
-	#define CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ 125000
+/* IT83XX config */
+#define CONFIG_IT83XX_VCC_1P8V
+/* I2C Bus Configuration */
+#define I2C_PORT_BATTERY IT83XX_I2C_CH_A /* Shared bus */
+#define I2C_PORT_CHARGER IT83XX_I2C_CH_A /* Shared bus */
+#define I2C_PORT_SENSOR IT83XX_I2C_CH_B
+#define I2C_PORT_USBC0 IT83XX_I2C_CH_C
+#define I2C_PORT_USBC1 IT83XX_I2C_CH_E
+#define I2C_PORT_USB_MUX I2C_PORT_USBC0 /* For MUX driver */
+#define I2C_PORT_EEPROM IT83XX_I2C_CH_F
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 2
+
+/* EC variant determines USB-C variant */
+#define VARIANT_OCTOPUS_USBC_ITE_EC_TCPCS
+
+/*
+ * Limit maximal ODR to 125Hz, the EC is using ~5ms per sample at
+ * 48MHz core cpu clock.
+ */
+#define CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ 125000
 #else
-	#error Must define a VARIANT_OCTOPUS_EC
+#error Must define a VARIANT_OCTOPUS_EC
 #endif /* VARIANT_OCTOPUS_EC */
 
 /* Common EC defines */
@@ -115,33 +117,33 @@
  * VARIANT_OCTOPUS_CHARGER_BQ25703
  */
 #if defined(VARIANT_OCTOPUS_CHARGER_ISL9238)
-	#define CONFIG_CHARGER_ISL9238
-	#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20
-	/*
-	 * ISL923x driver sets "Adapter insertion to Switching Debounce"
-	 * CONTROL2 REG 0x3DH <Bit 11> to 1 which is 150 ms
-	 */
-	#undef	CONFIG_EXTPOWER_DEBOUNCE_MS
-	#define	CONFIG_EXTPOWER_DEBOUNCE_MS 200
+#define CONFIG_CHARGER_ISL9238
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20
+/*
+ * ISL923x driver sets "Adapter insertion to Switching Debounce"
+ * CONTROL2 REG 0x3DH <Bit 11> to 1 which is 150 ms
+ */
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
+#define CONFIG_EXTPOWER_DEBOUNCE_MS 200
 #elif defined(VARIANT_OCTOPUS_CHARGER_BQ25703)
-	#define CONFIG_CHARGER_BQ25703
-	#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
-	/*
-	 * From BQ25703: CHRG_OK is HIGH after 50ms deglitch time.
-	 */
-	#undef	CONFIG_EXTPOWER_DEBOUNCE_MS
-	#define	CONFIG_EXTPOWER_DEBOUNCE_MS 50
+#define CONFIG_CHARGER_BQ25703
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+/*
+ * From BQ25703: CHRG_OK is HIGH after 50ms deglitch time.
+ */
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
+#define CONFIG_EXTPOWER_DEBOUNCE_MS 50
 #elif defined(CONFIG_CHARGER_RUNTIME_CONFIG)
-	#define CONFIG_CHARGER_ISL9238
-	#define CONFIG_CHARGER_BQ25710
-	#define CONFIG_CHARGER_SENSE_RESISTOR_AC_ISL9238 20
-	#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10
-	#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10
-
-	#undef CONFIG_EXTPOWER_DEBOUNCE_MS
-	#define CONFIG_EXTPOWER_DEBOUNCE_MS 200
+#define CONFIG_CHARGER_ISL9238
+#define CONFIG_CHARGER_BQ25710
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC_ISL9238 20
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10
+
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
+#define CONFIG_EXTPOWER_DEBOUNCE_MS 200
 #else
-	#error Must define a VARIANT_OCTOPUS_CHARGER
+#error Must define a VARIANT_OCTOPUS_CHARGER
 #endif /* VARIANT_OCTOPUS_CHARGER */
 
 /* Common charger defines */
@@ -155,7 +157,7 @@
 
 /* Common battery defines */
 #define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY  "LION"
+#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
 #define CONFIG_BATTERY_FUEL_GAUGE
 #define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_L
 #define CONFIG_BATTERY_REVIVE_DISCONNECT
@@ -166,38 +168,38 @@
  * Automatically defined by VARIANT_OCTOPUS_EC_ variant.
  */
 
- /*
-  * Variant USBC defines. Pick one:
-  * VARIANT_OCTOPUS_USBC_STANDALONE_TCPCS
-  * VARIANT_OCTOPUS_USBC_ITE_EC_TCPCS (requires)
-  */
+/*
+ * Variant USBC defines. Pick one:
+ * VARIANT_OCTOPUS_USBC_STANDALONE_TCPCS
+ * VARIANT_OCTOPUS_USBC_ITE_EC_TCPCS (requires)
+ */
 #if defined(VARIANT_OCTOPUS_USBC_STANDALONE_TCPCS)
-	#define CONFIG_USB_PD_TCPC_LOW_POWER
-	#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+#define CONFIG_USB_PD_TCPC_LOW_POWER
+#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
 #if !defined(VARIANT_OCTOPUS_TCPC_0_PS8751)
-	#define CONFIG_USB_PD_TCPM_ANX7447	/* C0 TCPC: ANX7447QN */
+#define CONFIG_USB_PD_TCPM_ANX7447 /* C0 TCPC: ANX7447QN */
 #endif
-	#define CONFIG_USB_PD_TCPM_PS8751	/* C1 TCPC: PS8751 */
-	#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-	#define CONFIG_USBC_PPC_NX20P3483
+#define CONFIG_USB_PD_TCPM_PS8751 /* C1 TCPC: PS8751 */
+#define CONFIG_USB_PD_VBUS_DETECT_TCPC
+#define CONFIG_USBC_PPC_NX20P3483
 #elif defined(VARIANT_OCTOPUS_USBC_ITE_EC_TCPCS)
-	#undef CONFIG_USB_PD_TCPC_LOW_POWER
-	#undef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-	#define CONFIG_USB_PD_VBUS_DETECT_PPC
-	#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP	/* C0 & C1 TCPC: ITE EC */
-	#define CONFIG_USB_MUX_IT5205		/* C0 MUX: IT5205 */
-	#define CONFIG_USB_PD_TCPM_PS8751	/* C1 Mux: PS8751 */
-	#define CONFIG_USB_PD_TCPM_PS8751_CUSTOM_MUX_DRIVER
-	#define CONFIG_USBC_PPC_SN5S330		/* C0 & C1 PPC: each SN5S330 */
-	#define CONFIG_USBC_PPC_VCONN
-	#define CONFIG_USBC_PPC_DEDICATED_INT
+#undef CONFIG_USB_PD_TCPC_LOW_POWER
+#undef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+#define CONFIG_USB_PD_VBUS_DETECT_PPC
+#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0 & C1 TCPC: ITE EC */
+#define CONFIG_USB_MUX_IT5205 /* C0 MUX: IT5205 */
+#define CONFIG_USB_PD_TCPM_PS8751 /* C1 Mux: PS8751 */
+#define CONFIG_USB_PD_TCPM_PS8751_CUSTOM_MUX_DRIVER
+#define CONFIG_USBC_PPC_SN5S330 /* C0 & C1 PPC: each SN5S330 */
+#define CONFIG_USBC_PPC_VCONN
+#define CONFIG_USBC_PPC_DEDICATED_INT
 #else
-	#error Must define a VARIANT_OCTOPUS_USBC
+#error Must define a VARIANT_OCTOPUS_USBC
 #endif /* VARIANT_OCTOPUS_USBC */
 
 /* Common USB-C defines */
-#define USB_PD_PORT_TCPC_0	0
-#define USB_PD_PORT_TCPC_1	1
+#define USB_PD_PORT_TCPC_0 0
+#define USB_PD_PORT_TCPC_1 1
 #define CONFIG_USB_PID 0x5046
 
 #define CONFIG_USB_DRP_ACC_TRYSRC
@@ -226,14 +228,14 @@
 #define CONFIG_CMD_PPC_DUMP
 
 /* TODO(b/76218141): Use correct PD delay values */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000	/* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	250000	/* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* TODO(b/76218141): Use correct PD power values */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		45000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 45000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /*******************************************************************************
  * USB-A Configs
@@ -252,7 +254,7 @@
  * SoC / PCH Config
  */
 
- /* Common SoC / PCH defines */
+/* Common SoC / PCH defines */
 #define CONFIG_CHIPSET_GEMINILAKE
 #define CONFIG_CHIPSET_RESET_HOOK
 #define CONFIG_HOST_INTERFACE_ESPI
@@ -275,7 +277,7 @@
 #define CONFIG_KEYBOARD_PROTOCOL_8042
 #define CONFIG_KEYBOARD_COL2_INVERTED
 #define CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2
-#undef  CONFIG_KEYBOARD_VIVALDI
+#undef CONFIG_KEYBOARD_VIVALDI
 
 /*******************************************************************************
  * Sensor Config
@@ -287,7 +289,7 @@
 /*
  * Slew rate on the PP1800_SENSOR load switch requires a short delay on startup.
  */
-#undef  CONFIG_MOTION_SENSE_RESUME_DELAY_US
+#undef CONFIG_MOTION_SENSE_RESUME_DELAY_US
 #define CONFIG_MOTION_SENSE_RESUME_DELAY_US (10 * MSEC)
 
 #ifndef VARIANT_OCTOPUS_NO_SENSORS
diff --git a/baseboard/octopus/build.mk b/baseboard/octopus/build.mk
index bb8a6f8267..696f60d42e 100644
--- a/baseboard/octopus/build.mk
+++ b/baseboard/octopus/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/baseboard/octopus/cbi_ssfc.c b/baseboard/octopus/cbi_ssfc.c
index 80d8614eb5..827d2e045e 100644
--- a/baseboard/octopus/cbi_ssfc.c
+++ b/baseboard/octopus/cbi_ssfc.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/baseboard/octopus/cbi_ssfc.h b/baseboard/octopus/cbi_ssfc.h
index 0b9eafc888..570c240da1 100644
--- a/baseboard/octopus/cbi_ssfc.h
+++ b/baseboard/octopus/cbi_ssfc.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,8 +18,8 @@ enum ssfc_tcpc_p1 {
 	SSFC_TCPC_P1_PS8751,
 	SSFC_TCPC_P1_PS8755,
 };
-#define SSFC_TCPC_P1_OFFSET		0
-#define SSFC_TCPC_P1_MASK		GENMASK(2, 0)
+#define SSFC_TCPC_P1_OFFSET 0
+#define SSFC_TCPC_P1_MASK GENMASK(2, 0)
 
 /*
  * PPC Port 1 (Bits 3-5)
@@ -29,8 +29,8 @@ enum ssfc_ppc_p1 {
 	SSFC_PPC_P1_NX20P348X,
 	SSFC_PPC_P1_SYV682X,
 };
-#define SSFC_PPC_P1_OFFSET		3
-#define SSFC_PPC_P1_MASK		GENMASK(5, 3)
+#define SSFC_PPC_P1_OFFSET 3
+#define SSFC_PPC_P1_MASK GENMASK(5, 3)
 
 /*
  * Charger (Bits 8-6)
@@ -40,8 +40,8 @@ enum ssfc_charger {
 	SSFC_CHARGER_ISL9238,
 	SSFC_CHARGER_BQ25710,
 };
-#define SSFC_CHARGER_OFFSET		6
-#define SSFC_CHARGER_MASK		GENMASK(8, 6)
+#define SSFC_CHARGER_OFFSET 6
+#define SSFC_CHARGER_MASK GENMASK(8, 6)
 
 /*
  * Audio (Bits 11-9)
@@ -56,8 +56,8 @@ enum ssfc_sensor {
 	SSFC_SENSOR_ICM426XX,
 	SSFC_SENSOR_BMI260,
 };
-#define SSFC_SENSOR_OFFSET		12
-#define SSFC_SENSOR_MASK		GENMASK(14, 12)
+#define SSFC_SENSOR_OFFSET 12
+#define SSFC_SENSOR_MASK GENMASK(14, 12)
 
 enum ssfc_tcpc_p1 get_cbi_ssfc_tcpc_p1(void);
 enum ssfc_ppc_p1 get_cbi_ssfc_ppc_p1(void);
diff --git a/baseboard/octopus/usb_pd_policy.c b/baseboard/octopus/usb_pd_policy.c
index 3dd6ad29f5..c8b8b96d3a 100644
--- a/baseboard/octopus/usb_pd_policy.c
+++ b/baseboard/octopus/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,8 +17,8 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
diff --git a/baseboard/octopus/variant_ec_ite8320.c b/baseboard/octopus/variant_ec_ite8320.c
index 72c0021e89..e79f4cdb01 100644
--- a/baseboard/octopus/variant_ec_ite8320.c
+++ b/baseboard/octopus/variant_ec_ite8320.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -28,40 +28,30 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 /******************************************************************************/
 /* I2C port map configuration */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "power",
-		.port = IT83XX_I2C_CH_A,
-		.kbps = 100,
-		.scl  = GPIO_I2C0_SCL,
-		.sda  = GPIO_I2C0_SDA
-	},
-	{
-		.name = "sensor",
-		.port = IT83XX_I2C_CH_B,
-		.kbps = 100,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	},
-	{
-		.name = "usbc0",
-		.port = IT83XX_I2C_CH_C,
-		.kbps = 400,
-		.scl  = GPIO_I2C2_SCL,
-		.sda  = GPIO_I2C2_SDA
-	},
-	{
-		.name = "usbc1",
-		.port = IT83XX_I2C_CH_E,
-		.kbps = 400,
-		.scl  = GPIO_I2C4_SCL,
-		.sda  = GPIO_I2C4_SDA
-	},
-	{
-		.name = "eeprom",
-		.port = IT83XX_I2C_CH_F,
-		.kbps = 100,
-		.scl  = GPIO_I2C5_SCL,
-		.sda  = GPIO_I2C5_SDA
-	},
+	{ .name = "power",
+	  .port = IT83XX_I2C_CH_A,
+	  .kbps = 100,
+	  .scl = GPIO_I2C0_SCL,
+	  .sda = GPIO_I2C0_SDA },
+	{ .name = "sensor",
+	  .port = IT83XX_I2C_CH_B,
+	  .kbps = 100,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "usbc0",
+	  .port = IT83XX_I2C_CH_C,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "usbc1",
+	  .port = IT83XX_I2C_CH_E,
+	  .kbps = 400,
+	  .scl = GPIO_I2C4_SCL,
+	  .sda = GPIO_I2C4_SDA },
+	{ .name = "eeprom",
+	  .port = IT83XX_I2C_CH_F,
+	  .kbps = 100,
+	  .scl = GPIO_I2C5_SCL,
+	  .sda = GPIO_I2C5_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/baseboard/octopus/variant_ec_npcx796fb.c b/baseboard/octopus/variant_ec_npcx796fb.c
index 8c3cbd2460..23a4f58bae 100644
--- a/baseboard/octopus/variant_ec_npcx796fb.c
+++ b/baseboard/octopus/variant_ec_npcx796fb.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -31,49 +31,37 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 /******************************************************************************/
 /* I2C port map configuration */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "battery",
-		.port = I2C_PORT_BATTERY,
-		.kbps = 100,
-		.scl  = GPIO_I2C0_SCL,
-		.sda  = GPIO_I2C0_SDA
-	},
-	{
-		.name = "tcpc0",
-		.port = I2C_PORT_TCPC0,
-		.kbps = 400,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	},
-	{
-		.name = "tcpc1",
-		.port = I2C_PORT_TCPC1,
-		.kbps = 400,
-		.scl  = GPIO_I2C2_SCL,
-		.sda  = GPIO_I2C2_SDA
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 100,
-		.scl  = GPIO_I2C3_SCL,
-		.sda  = GPIO_I2C3_SDA
-	},
-	{
-		.name = "charger",
-		.port = I2C_PORT_CHARGER,
-		.kbps = 100,
-		.scl  = GPIO_I2C4_SCL,
-		.sda  = GPIO_I2C4_SDA
-	},
+	{ .name = "battery",
+	  .port = I2C_PORT_BATTERY,
+	  .kbps = 100,
+	  .scl = GPIO_I2C0_SCL,
+	  .sda = GPIO_I2C0_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "tcpc1",
+	  .port = I2C_PORT_TCPC1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 100,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
+	{ .name = "charger",
+	  .port = I2C_PORT_CHARGER,
+	  .kbps = 100,
+	  .scl = GPIO_I2C4_SCL,
+	  .sda = GPIO_I2C4_SDA },
 #ifndef VARIANT_OCTOPUS_NO_SENSORS
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 100,
-		.scl  = GPIO_I2C7_SCL,
-		.sda  = GPIO_I2C7_SDA
-	},
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 100,
+	  .scl = GPIO_I2C7_SCL,
+	  .sda = GPIO_I2C7_SDA },
 #endif
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
@@ -82,8 +70,9 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 /******************************************************************************/
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = { .channel = 3, .flags = PWM_CONFIG_DSLEEP,
-								.freq = 100 },
+	[PWM_CH_KBLIGHT] = { .channel = 3,
+			     .flags = PWM_CONFIG_DSLEEP,
+			     .freq = 100 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 #endif
diff --git a/baseboard/octopus/variant_usbc_ec_tcpcs.c b/baseboard/octopus/variant_usbc_ec_tcpcs.c
index 00640168cf..983887bc08 100644
--- a/baseboard/octopus/variant_usbc_ec_tcpcs.c
+++ b/baseboard/octopus/variant_usbc_ec_tcpcs.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,8 +22,8 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define USB_PD_PORT_ITE_0	0
-#define USB_PD_PORT_ITE_1	1
+#define USB_PD_PORT_ITE_0 0
+#define USB_PD_PORT_ITE_1 1
 
 /******************************************************************************/
 /* USB-C TPCP Configuration */
@@ -49,13 +49,12 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 
 /* TODO(crbug.com/826441): Consolidate this logic with other impls */
 static void board_it83xx_hpd_status(const struct usb_mux *me,
-				    mux_state_t mux_state,
-				    bool *ack_required)
+				    mux_state_t mux_state, bool *ack_required)
 {
 	int hpd_lvl = (mux_state & USB_PD_MUX_HPD_LVL) ? 1 : 0;
 	int hpd_irq = (mux_state & USB_PD_MUX_HPD_IRQ) ? 1 : 0;
-	enum gpio_signal gpio = me->usb_port ?
-		GPIO_USB_C1_HPD_1V8_ODL : GPIO_USB_C0_HPD_1V8_ODL;
+	enum gpio_signal gpio = me->usb_port ? GPIO_USB_C1_HPD_1V8_ODL :
+					       GPIO_USB_C0_HPD_1V8_ODL;
 
 	/* This driver does not use host command ACKs */
 	*ack_required = false;
@@ -72,38 +71,38 @@ static void board_it83xx_hpd_status(const struct usb_mux *me,
 }
 
 /* This configuration might be override by each boards */
-struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_ITE_0] = {
-		.usb_port = USB_PD_PORT_ITE_0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_it83xx_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_ITE_0,
+			.i2c_port = I2C_PORT_USB_MUX,
+			.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+			.driver = &it5205_usb_mux_driver,
+			.hpd_update = &board_it83xx_hpd_status,
+		},
 	},
 	[USB_PD_PORT_ITE_1] = {
-		.usb_port = USB_PD_PORT_ITE_1,
-		/* Use PS8751 as mux only */
-		.i2c_port = I2C_PORT_USBC1,
-		.i2c_addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
-		.flags = USB_MUX_FLAG_NOT_TCPC,
-		.driver = &ps8xxx_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_ITE_1,
+			/* Use PS8751 as mux only */
+			.i2c_port = I2C_PORT_USBC1,
+			.i2c_addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+			.flags = USB_MUX_FLAG_NOT_TCPC,
+			.driver = &ps8xxx_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 	}
 };
 
 /******************************************************************************/
 /* USB-C PPC Configuration */
 struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_ITE_0] = {
-		.i2c_port = I2C_PORT_USBC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	[USB_PD_PORT_ITE_1] = {
-		.i2c_port = I2C_PORT_USBC1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
+	[USB_PD_PORT_ITE_0] = { .i2c_port = I2C_PORT_USBC0,
+				.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+				.drv = &sn5s330_drv },
+	[USB_PD_PORT_ITE_1] = { .i2c_port = I2C_PORT_USBC1,
+				.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+				.drv = &sn5s330_drv },
 };
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
@@ -158,6 +157,6 @@ void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
 	 * correctly in the PPC driver via the pd state machine.
 	 */
 	if (ppc_set_vconn(port, enabled) != EC_SUCCESS)
-		cprints(CC_USBPD, "C%d: Failed %sabling vconn",
-			port, enabled ? "en" : "dis");
+		cprints(CC_USBPD, "C%d: Failed %sabling vconn", port,
+			enabled ? "en" : "dis");
 }
diff --git a/baseboard/octopus/variant_usbc_standalone_tcpcs.c b/baseboard/octopus/variant_usbc_standalone_tcpcs.c
index d26e234c4b..abc325dfa3 100644
--- a/baseboard/octopus/variant_usbc_standalone_tcpcs.c
+++ b/baseboard/octopus/variant_usbc_standalone_tcpcs.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,8 +21,8 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
 
 /******************************************************************************/
 /* USB-C TPCP Configuration */
@@ -66,22 +66,26 @@ static int ps8751_tune_mux(const struct usb_mux *me)
 }
 #endif
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_TCPC_0] = {
-		.usb_port = USB_PD_PORT_TCPC_0,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_0,
 #if defined(VARIANT_OCTOPUS_TCPC_0_PS8751)
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-		.board_init = &ps8751_tune_mux,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			.board_init = &ps8751_tune_mux,
 #else
-		.driver = &anx7447_usb_mux_driver,
-		.hpd_update = &anx7447_tcpc_update_hpd_status,
+			.driver = &anx7447_usb_mux_driver,
+			.hpd_update = &anx7447_tcpc_update_hpd_status,
 #endif
+		},
 	},
 	[USB_PD_PORT_TCPC_1] = {
-		.usb_port = USB_PD_PORT_TCPC_1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 	}
 };
 
diff --git a/baseboard/trogdor/baseboard.c b/baseboard/trogdor/baseboard.c
index 6f49ecb4ae..3f3c778ea5 100644
--- a/baseboard/trogdor/baseboard.c
+++ b/baseboard/trogdor/baseboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/baseboard/trogdor/baseboard.h b/baseboard/trogdor/baseboard.h
index d65fb2dc1e..63813c89a0 100644
--- a/baseboard/trogdor/baseboard.h
+++ b/baseboard/trogdor/baseboard.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,12 +13,12 @@
  * The sensor stack is generating a lot of activity.
  * They can be enabled through the console command 'chan'.
  */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_HOSTCMD)))
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_HOSTCMD)))
 
 /* NPCX7 config */
-#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
-#define NPCX_TACH_SEL2    0  /* No tach. */
-#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
+#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */
+#define NPCX_TACH_SEL2 0 /* No tach. */
+#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */
 
 /* Internal SPI flash on NPCX7 */
 #define CONFIG_SPI_FLASH_REGS
@@ -142,13 +142,13 @@
 #define CONFIG_CMD_ACCEL_INFO
 
 /* PD */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY   30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY  250000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
-#define PD_OPERATING_POWER_MW   10000
-#define PD_MAX_POWER_MW         ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
-#define PD_MAX_CURRENT_MA       3000
-#define PD_MAX_VOLTAGE_MV       20000
+#define PD_OPERATING_POWER_MW 10000
+#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Chipset */
 #define CONFIG_CHIPSET_SC7180
@@ -166,56 +166,54 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_POWER_BUTTON_L	GPIO_EC_PWR_BTN_ODL
-#define GPIO_VOLUME_DOWN_L	GPIO_EC_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L	GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_LID_OPEN		GPIO_LID_OPEN_EC
-#define GPIO_SHI_CS_L		GPIO_AP_EC_SPI_CS_L
-#define GPIO_ENTERING_RW	GPIO_EC_ENTERING_RW
-#define GPIO_BATT_PRES_ODL	GPIO_EC_BATT_PRES_ODL
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
-#define GPIO_ENABLE_BACKLIGHT	GPIO_EC_BL_DISABLE_L
-#define GPIO_BOARD_VERSION1	GPIO_BRD_ID0
-#define GPIO_BOARD_VERSION2	GPIO_BRD_ID1
-#define GPIO_BOARD_VERSION3	GPIO_BRD_ID2
-#define GPIO_KBD_KSO2		GPIO_EC_KSO_02_INV
+#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_LID_OPEN GPIO_LID_OPEN_EC
+#define GPIO_SHI_CS_L GPIO_AP_EC_SPI_CS_L
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_BATT_PRES_ODL GPIO_EC_BATT_PRES_ODL
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
+#define GPIO_ENABLE_BACKLIGHT GPIO_EC_BL_DISABLE_L
+#define GPIO_BOARD_VERSION1 GPIO_BRD_ID0
+#define GPIO_BOARD_VERSION2 GPIO_BRD_ID1
+#define GPIO_BOARD_VERSION3 GPIO_BRD_ID2
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
 
 /* I2C Ports */
 #define I2C_PORT_BATTERY I2C_PORT_POWER
 #define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
 #define I2C_PORT_CHARGER I2C_PORT_POWER
-#define I2C_PORT_ACCEL   I2C_PORT_SENSOR
-#define I2C_PORT_POWER   NPCX_I2C_PORT0_0
-#define I2C_PORT_TCPC0   NPCX_I2C_PORT1_0
-#define I2C_PORT_TCPC1   NPCX_I2C_PORT2_0
-#define I2C_PORT_WLC     NPCX_I2C_PORT3_0
-#define I2C_PORT_EEPROM  NPCX_I2C_PORT5_0
-#define I2C_PORT_SENSOR  NPCX_I2C_PORT7_0
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
+#define I2C_PORT_POWER NPCX_I2C_PORT0_0
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT1_0
+#define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0
+#define I2C_PORT_WLC NPCX_I2C_PORT3_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT5_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT7_0
 
 /* UART */
 #define CONFIG_CMD_CHARGEN
 
 /* Define the host events which are allowed to wake AP up from S3 */
-#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \
-		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) | \
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) | \
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT) | \
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC) | \
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_DEVICE))
+#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK                   \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |        \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |    \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |    \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT) |     \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC) |             \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |     \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_DEVICE))
 
 /* And the MKBP events */
 #ifdef HAS_TASK_KEYSCAN
-#define CONFIG_MKBP_EVENT_WAKEUP_MASK \
-		(BIT(EC_MKBP_EVENT_KEY_MATRIX) | \
-		 BIT(EC_MKBP_EVENT_HOST_EVENT) | \
-		 BIT(EC_MKBP_EVENT_SENSOR_FIFO))
+#define CONFIG_MKBP_EVENT_WAKEUP_MASK                                    \
+	(BIT(EC_MKBP_EVENT_KEY_MATRIX) | BIT(EC_MKBP_EVENT_HOST_EVENT) | \
+	 BIT(EC_MKBP_EVENT_SENSOR_FIFO))
 #else
 #define CONFIG_MKBP_EVENT_WAKEUP_MASK \
-		(BIT(EC_MKBP_EVENT_HOST_EVENT) | \
-		 BIT(EC_MKBP_EVENT_SENSOR_FIFO))
+	(BIT(EC_MKBP_EVENT_HOST_EVENT) | BIT(EC_MKBP_EVENT_SENSOR_FIFO))
 #endif
 
 #endif /* __CROS_EC_BASEBOARD_H */
diff --git a/baseboard/trogdor/build.mk b/baseboard/trogdor/build.mk
index a51c7c7e17..02ed466d2b 100644
--- a/baseboard/trogdor/build.mk
+++ b/baseboard/trogdor/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/baseboard/trogdor/hibernate.c b/baseboard/trogdor/hibernate.c
index c28082e75d..19af7cfe2e 100644
--- a/baseboard/trogdor/hibernate.c
+++ b/baseboard/trogdor/hibernate.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/baseboard/trogdor/power.c b/baseboard/trogdor/power.c
index b539539c98..a8076d0ed5 100644
--- a/baseboard/trogdor/power.c
+++ b/baseboard/trogdor/power.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -35,4 +35,4 @@ void board_chipset_shutdown_complete(void)
 	gpio_set_level(GPIO_EN_PP3300_A, 0);
 }
 DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN_COMPLETE, board_chipset_shutdown_complete,
-		HOOK_PRIO_DEFAULT);
+	     HOOK_PRIO_DEFAULT);
diff --git a/baseboard/trogdor/usb_pd_policy.c b/baseboard/trogdor/usb_pd_policy.c
index 56ca4514d5..7954d0a352 100644
--- a/baseboard/trogdor/usb_pd_policy.c
+++ b/baseboard/trogdor/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,8 +12,8 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
@@ -23,10 +23,10 @@ int pd_check_vconn_swap(int port)
 
 static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT];
 #if CONFIG_USB_PD_PORT_MAX_COUNT == 1
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5};
+static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5 };
 #else
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5,
-							TYPEC_RP_1A5};
+static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5,
+							 TYPEC_RP_1A5 };
 #endif
 
 static void board_vbus_update_source_current(int port)
@@ -107,11 +107,11 @@ __override int svdm_dp_config(int port, uint32_t *payload)
 	 *  (3) plug a monitor to the port-1 dongle.
 	 */
 
-	payload[0] = VDO(USB_SID_DISPLAYPORT, 1,
-			 CMD_DP_CONFIG | VDO_OPOS(opos));
-	payload[1] = VDO_DP_CFG(pin_mode,      /* pin mode */
-				1,             /* DPv1.3 signaling */
-				2);            /* UFP connected */
+	payload[0] =
+		VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_CONFIG | VDO_OPOS(opos));
+	payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */
+				1, /* DPv1.3 signaling */
+				2); /* UFP connected */
 	return 2;
 };
 
@@ -187,8 +187,7 @@ __override int svdm_dp_attention(int port, uint32_t *payload)
 		 * because of the board USB-C topology (limited to 2
 		 * lanes DP).
 		 */
-		usb_mux_set(port, USB_PD_MUX_DOCK,
-			    USB_SWITCH_CONNECT,
+		usb_mux_set(port, USB_PD_MUX_DOCK, USB_SWITCH_CONNECT,
 			    polarity_rm_dts(pd_get_polarity(port)));
 	} else {
 		/* Disconnect the DP port selection mux. */
@@ -200,13 +199,11 @@ __override int svdm_dp_attention(int port, uint32_t *payload)
 			ppc_set_sbu(port, 0);
 
 		/* Disconnect the DP but keep the USB SS lines in TCPC chip. */
-		usb_mux_set(port, USB_PD_MUX_USB_ENABLED,
-			    USB_SWITCH_CONNECT,
+		usb_mux_set(port, USB_PD_MUX_USB_ENABLED, USB_SWITCH_CONNECT,
 			    polarity_rm_dts(pd_get_polarity(port)));
 	}
 
-	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
-	    (irq || lvl))
+	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && (irq || lvl))
 		/*
 		 * Wake up the AP.  IRQ or level high indicates a DP sink is now
 		 * present.
@@ -233,8 +230,8 @@ __override int svdm_dp_attention(int port, uint32_t *payload)
 		CPRINTS("C%d: Recv IRQ. HPD->1", port);
 
 		/* Set the minimum time delay (2ms) for the next HPD IRQ */
-		svdm_hpd_deadline[port] = get_time().val +
-			HPD_USTREAM_DEBOUNCE_LVL;
+		svdm_hpd_deadline[port] =
+			get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
 	} else if (irq & !lvl) {
 		CPRINTF("ERR:HPD:IRQ&LOW\n");
 		return 0;
@@ -242,8 +239,8 @@ __override int svdm_dp_attention(int port, uint32_t *payload)
 		CPRINTS("C%d: Recv lvl. HPD->%d", port, lvl);
 		gpio_set_level(hpd, lvl);
 		/* Set the minimum time delay (2ms) for the next HPD IRQ */
-		svdm_hpd_deadline[port] = get_time().val +
-			HPD_USTREAM_DEBOUNCE_LVL;
+		svdm_hpd_deadline[port] =
+			get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
 	}
 
 	return 1;
@@ -259,7 +256,7 @@ __override void svdm_exit_dp_mode(int port)
 
 		/* Signal AP for the HPD low event */
 		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 		CPRINTS("C%d: DP exit. HPD->0", port);
 		gpio_set_level(GPIO_DP_HOT_PLUG_DET, 0);
 	}
diff --git a/baseboard/volteer/baseboard.c b/baseboard/volteer/baseboard.c
index 6b3ad33a35..fd36aef81f 100644
--- a/baseboard/volteer/baseboard.c
+++ b/baseboard/volteer/baseboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,8 +23,8 @@
 #include "usbc_config.h"
 #endif
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ##args)
 
 /******************************************************************************/
 /* ADC configuration */
@@ -73,21 +73,21 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 /******************************************************************************/
 /* Temperature sensor configuration */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_1_CHARGER},
-	[TEMP_SENSOR_2_PP3300_REGULATOR] = {.name = "PP3300 Regulator",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_2_PP3300_REGULATOR},
-	[TEMP_SENSOR_3_DDR_SOC] = {.name = "DDR and SOC",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_3_DDR_SOC},
-	[TEMP_SENSOR_4_FAN] = {.name = "Fan",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_4_FAN},
+	[TEMP_SENSOR_1_CHARGER] = { .name = "Charger",
+				    .type = TEMP_SENSOR_TYPE_BOARD,
+				    .read = get_temp_3v3_30k9_47k_4050b,
+				    .idx = ADC_TEMP_SENSOR_1_CHARGER },
+	[TEMP_SENSOR_2_PP3300_REGULATOR] = { .name = "PP3300 Regulator",
+					     .type = TEMP_SENSOR_TYPE_BOARD,
+					     .read = get_temp_3v3_30k9_47k_4050b,
+					     .idx = ADC_TEMP_SENSOR_2_PP3300_REGULATOR },
+	[TEMP_SENSOR_3_DDR_SOC] = { .name = "DDR and SOC",
+				    .type = TEMP_SENSOR_TYPE_BOARD,
+				    .read = get_temp_3v3_30k9_47k_4050b,
+				    .idx = ADC_TEMP_SENSOR_3_DDR_SOC },
+	[TEMP_SENSOR_4_FAN] = { .name = "Fan",
+				.type = TEMP_SENSOR_TYPE_BOARD,
+				.read = get_temp_3v3_30k9_47k_4050b,
+				.idx = ADC_TEMP_SENSOR_4_FAN },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
diff --git a/baseboard/volteer/baseboard.h b/baseboard/volteer/baseboard.h
index c7f7c0d047..3b8e475fe5 100644
--- a/baseboard/volteer/baseboard.h
+++ b/baseboard/volteer/baseboard.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,11 +13,11 @@
 /*
  * By default, enable all console messages excepted HC
  */
-#define CC_DEFAULT     (CC_ALL & ~(BIT(CC_HOSTCMD)))
+#define CC_DEFAULT (CC_ALL & ~(BIT(CC_HOSTCMD)))
 
 /* NPCX7 config */
-#define NPCX7_PWM1_SEL    1  /* GPIO C2 is used as PWM1. */
-#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
+#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */
+#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */
 /* Internal SPI flash on NPCX796FC is 512 kB */
 #define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
 #define CONFIG_SPI_FLASH_REGS
@@ -44,8 +44,8 @@
 
 /* Host communication */
 #define CONFIG_HOST_INTERFACE_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S5
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S5
 
 /* Chipset config */
 #define CONFIG_CHIPSET_TIGERLAKE
@@ -94,10 +94,10 @@
 #define CONFIG_CMD_ACCEL_INFO
 
 /* Thermal features */
-#define CONFIG_FANS			FAN_CH_COUNT
+#define CONFIG_FANS FAN_CH_COUNT
 #define CONFIG_TEMP_SENSOR
 #define CONFIG_TEMP_SENSOR_POWER
-#define GPIO_TEMP_SENSOR_POWER		GPIO_PG_EC_DSW_PWROK
+#define GPIO_TEMP_SENSOR_POWER GPIO_PG_EC_DSW_PWROK
 #define CONFIG_THERMISTOR
 #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
 #define CONFIG_THROTTLE_AP
@@ -107,7 +107,7 @@
 #define CONFIG_CHARGE_MANAGER
 #define CONFIG_CHARGER
 #define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT		512
+#define CONFIG_CHARGER_INPUT_CURRENT 512
 
 /*
  * Hardware based charge ramp is broken in the ISL9241 (b/169350714).
@@ -115,7 +115,7 @@
 #define CONFIG_CHARGE_RAMP_SW
 #define CONFIG_CHARGER_ISL9241
 /* Setting ISL9241 Register Control1 switching frequency to 724kHz. */
-#define CONFIG_ISL9241_SWITCHING_FREQ	ISL9241_CONTROL1_SWITCHING_FREQ_724KHZ
+#define CONFIG_ISL9241_SWITCHING_FREQ ISL9241_CONTROL1_SWITCHING_FREQ_724KHZ
 
 #define CONFIG_USB_CHARGER
 #define CONFIG_BC12_DETECT_PI3USB9201
@@ -124,8 +124,8 @@
  * Don't allow the system to boot to S0 when the battery is low and unable to
  * communicate on locked systems (which haven't PD negotiated)
  */
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT	15000
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON		15001
+#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT 15000
+#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 15001
 
 /* Common battery defines */
 #define CONFIG_BATTERY_SMART
@@ -140,7 +140,7 @@
 
 /* EDP back-light control defines */
 #define CONFIG_BACKLIGHT_LID
-#define GPIO_ENABLE_BACKLIGHT   GPIO_EC_EDP_BL_EN
+#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EDP_BL_EN
 
 /* USB Type C and USB PD defines */
 /* Enable the new USB-C PD stack */
@@ -169,11 +169,11 @@
 #define CONFIG_USB_PD_TCPC_LOW_POWER
 #define CONFIG_USB_PD_TCPM_TCPCI
 #define CONFIG_USB_PD_TCPM_RT1715
-#define CONFIG_USB_PD_TCPM_TUSB422	/* USBC port C0 */
-#define CONFIG_USB_PD_TCPM_PS8815	/* USBC port USB3 DB */
+#define CONFIG_USB_PD_TCPM_TUSB422 /* USBC port C0 */
+#define CONFIG_USB_PD_TCPM_PS8815 /* USBC port USB3 DB */
 #define CONFIG_USB_PD_TCPM_PS8815_FORCE_DID
 #define CONFIG_USB_PD_TCPM_MUX
-#define CONFIG_HOSTCMD_PD_CONTROL		/* Needed for TCPC FW update */
+#define CONFIG_HOSTCMD_PD_CONTROL /* Needed for TCPC FW update */
 #define CONFIG_CMD_USB_PD_PE
 
 /*
@@ -190,7 +190,7 @@
  * with non-PD chargers.  Override the default low-power mode exit delay.
  */
 #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
-#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE	(50*MSEC)
+#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (50 * MSEC)
 
 /* Enable USB3.2 DRD */
 #define CONFIG_USB_PD_USB32_DRD
diff --git a/baseboard/volteer/baseboard_usbc_config.h b/baseboard/volteer/baseboard_usbc_config.h
index bf02b1cb34..db5e296d46 100644
--- a/baseboard/volteer/baseboard_usbc_config.h
+++ b/baseboard/volteer/baseboard_usbc_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/baseboard/volteer/battery_presence.c b/baseboard/volteer/battery_presence.c
index 4953d7a49e..f143b67c91 100644
--- a/baseboard/volteer/battery_presence.c
+++ b/baseboard/volteer/battery_presence.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -24,8 +24,9 @@ static bool battery_init(void)
 {
 	int batt_status;
 
-	return battery_status(&batt_status) ? 0 :
-		!!(batt_status & STATUS_INITIALIZED);
+	return battery_status(&batt_status) ?
+		       0 :
+		       !!(batt_status & STATUS_INITIALIZED);
 }
 
 __overridable bool board_battery_is_initialized(void)
diff --git a/baseboard/volteer/build.mk b/baseboard/volteer/build.mk
index 08b68c5816..2b2f4e97b1 100644
--- a/baseboard/volteer/build.mk
+++ b/baseboard/volteer/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/baseboard/volteer/cbi.c b/baseboard/volteer/cbi.c
index ea446acc4e..28606d7eaf 100644
--- a/baseboard/volteer/cbi.c
+++ b/baseboard/volteer/cbi.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,8 @@
 #include "hooks.h"
 #include "system.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ##args)
 
 static uint8_t board_id;
 
diff --git a/baseboard/volteer/cbi.h b/baseboard/volteer/cbi.h
index 049c0f65e2..dc940f1edc 100644
--- a/baseboard/volteer/cbi.h
+++ b/baseboard/volteer/cbi.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/baseboard/volteer/cbi_ec_fw_config.c b/baseboard/volteer/cbi_ec_fw_config.c
index e602691aeb..7506278e16 100644
--- a/baseboard/volteer/cbi_ec_fw_config.c
+++ b/baseboard/volteer/cbi_ec_fw_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,7 +8,7 @@
 #include "cbi_ec_fw_config.h"
 #include "cros_board_info.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 static union volteer_cbi_fw_config fw_config;
 BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
diff --git a/baseboard/volteer/cbi_ec_fw_config.h b/baseboard/volteer/cbi_ec_fw_config.h
index 0a44e1f9e4..da91dff27b 100644
--- a/baseboard/volteer/cbi_ec_fw_config.h
+++ b/baseboard/volteer/cbi_ec_fw_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -43,23 +43,20 @@ enum ec_cfg_numeric_pad_type {
 	NUMERIC_PAD_ENABLED = 1
 };
 
-enum ec_cfg_keyboard_layout {
-	KB_LAYOUT_DEFAULT = 0,
-	KB_LAYOUT_1 = 1
-};
+enum ec_cfg_keyboard_layout { KB_LAYOUT_DEFAULT = 0, KB_LAYOUT_1 = 1 };
 
 union volteer_cbi_fw_config {
 	struct {
-		enum ec_cfg_usb_db_type			usb_db : 4;
-		uint32_t				thermal : 4;
-		uint32_t				audio : 3;
-		enum ec_cfg_tabletmode_type		tabletmode : 1;
-		uint32_t				lte_db : 2;
-		enum ec_cfg_keyboard_backlight_type	kb_bl : 1;
-		enum ec_cfg_numeric_pad_type		num_pad : 1;
-		uint32_t				sd_db : 4;
-		enum ec_cfg_keyboard_layout		kb_layout : 2;
-		uint32_t				reserved_2 : 10;
+		enum ec_cfg_usb_db_type usb_db : 4;
+		uint32_t thermal : 4;
+		uint32_t audio : 3;
+		enum ec_cfg_tabletmode_type tabletmode : 1;
+		uint32_t lte_db : 2;
+		enum ec_cfg_keyboard_backlight_type kb_bl : 1;
+		enum ec_cfg_numeric_pad_type num_pad : 1;
+		uint32_t sd_db : 4;
+		enum ec_cfg_keyboard_layout kb_layout : 2;
+		uint32_t reserved_2 : 10;
 	};
 	uint32_t raw_value;
 };
diff --git a/baseboard/volteer/cbi_ssfc.c b/baseboard/volteer/cbi_ssfc.c
index 42b11c4a1c..f68602b558 100644
--- a/baseboard/volteer/cbi_ssfc.c
+++ b/baseboard/volteer/cbi_ssfc.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -39,3 +39,8 @@ enum ec_ssfc_lightbar get_cbi_ssfc_lightbar(void)
 {
 	return cached_ssfc.lightbar;
 }
+
+enum ec_ssfc_keyboard get_cbi_ssfc_keyboard(void)
+{
+	return cached_ssfc.keyboard;
+}
diff --git a/baseboard/volteer/cbi_ssfc.h b/baseboard/volteer/cbi_ssfc.h
index e3431129bc..225ff8670e 100644
--- a/baseboard/volteer/cbi_ssfc.h
+++ b/baseboard/volteer/cbi_ssfc.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -40,12 +40,19 @@ enum ec_ssfc_lightbar {
 	SSFC_LIGHTBAR_12_LED = 2
 };
 
+/*
+ * Keyboard Type (Bit 12)
+ */
+enum ec_ssfc_keyboard { SSFC_KEYBOARD_DEFAULT = 0, SSFC_KEYBOARD_GAMING = 1 };
+
 union volteer_cbi_ssfc {
 	struct {
 		enum ec_ssfc_base_sensor base_sensor : 3;
 		enum ec_ssfc_lid_sensor lid_sensor : 3;
 		enum ec_ssfc_lightbar lightbar : 2;
-		uint32_t reserved_2 : 24;
+		uint32_t reserved_2 : 4;
+		enum ec_ssfc_keyboard keyboard : 1;
+		uint32_t reserved_3 : 19;
 	};
 	uint32_t raw_value;
 };
@@ -71,4 +78,11 @@ enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
  */
 enum ec_ssfc_lightbar get_cbi_ssfc_lightbar(void);
 
+/**
+ * Get keyboard type from SSFC_CONFIG.
+ *
+ * @return the keyboard type.
+ */
+enum ec_ssfc_keyboard get_cbi_ssfc_keyboard(void);
+
 #endif /* _Volteer_CBI_SSFC__H_ */
diff --git a/baseboard/volteer/charger.c b/baseboard/volteer/charger.c
index a674b98f41..84fa4e037c 100644
--- a/baseboard/volteer/charger.c
+++ b/baseboard/volteer/charger.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,8 +16,8 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* Charger Chip Configuration */
 const struct charger_config_t chg_chips[] = {
@@ -30,8 +30,7 @@ const struct charger_config_t chg_chips[] = {
 
 int board_set_active_charge_port(int port)
 {
-	int is_valid_port = (port >= 0 &&
-			     port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	int i;
 
 	if (port == CHARGE_PORT_NONE) {
@@ -52,7 +51,6 @@ int board_set_active_charge_port(int port)
 		return EC_ERROR_INVAL;
 	}
 
-
 	/* Check if the port is sourcing VBUS. */
 	if (ppc_is_sourcing_vbus(port)) {
 		CPRINTFUSB("Skip enable C%d", port);
@@ -83,11 +81,10 @@ int board_set_active_charge_port(int port)
 }
 
 __overridable void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+					  int max_ma, int charge_mv)
 {
-	charge_set_input_current_limit(MAX(charge_ma,
-					CONFIG_CHARGER_INPUT_CURRENT),
-					charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 void board_overcurrent_event(int port, int is_overcurrented)
diff --git a/baseboard/volteer/power.c b/baseboard/volteer/power.c
index b0d6b847ce..882c067b6d 100644
--- a/baseboard/volteer/power.c
+++ b/baseboard/volteer/power.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/baseboard/volteer/usb_pd_policy.c b/baseboard/volteer/usb_pd_policy.c
index 5b9000b3f7..81e02b769f 100644
--- a/baseboard/volteer/usb_pd_policy.c
+++ b/baseboard/volteer/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,8 +14,8 @@
 #include "usb_pd.h"
 #include "system.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
@@ -74,54 +74,44 @@ int board_vbus_source_enabled(int port)
 	return ppc_is_sourcing_vbus(port);
 }
 
+#ifdef CONFIG_USB_PD_TBT_COMPAT_MODE
 /* ----------------- Vendor Defined Messages ------------------ */
 /* Responses specifically for the enablement of TBT mode in the role of UFP */
 
 #define OPOS_TBT 1
 
-static const union tbt_mode_resp_device vdo_tbt_modes[1] = {
-		{
-			.tbt_alt_mode = 0x0001,
-			.tbt_adapter = TBT_ADAPTER_TBT3,
-			.intel_spec_b0 = 0,
-			.vendor_spec_b0 = 0,
-			.vendor_spec_b1 = 0,
-		}
-};
-
-static const uint32_t vdo_idh = VDO_IDH(
-				1, /* Data caps as USB host     */
-				0, /* Not a USB device   */
-				IDH_PTYPE_PERIPH,
-				1, /* Supports alt modes */
-				USB_VID_GOOGLE);
-
-static const uint32_t vdo_idh_rev30 = VDO_IDH_REV30(
-				 1, /* Data caps as USB host     */
-				 0, /* Not a USB device   */
-				 IDH_PTYPE_PERIPH,
-				 1, /* Supports alt modes */
-				 IDH_PTYPE_DFP_HOST,
-				 USB_TYPEC_RECEPTACLE,
-				 USB_VID_GOOGLE);
-
-static const uint32_t vdo_product = VDO_PRODUCT(
-				CONFIG_USB_PID, CONFIG_USB_BCD_DEV);
+static const union tbt_mode_resp_device vdo_tbt_modes[1] = { {
+	.tbt_alt_mode = 0x0001,
+	.tbt_adapter = TBT_ADAPTER_TBT3,
+	.intel_spec_b0 = 0,
+	.vendor_spec_b0 = 0,
+	.vendor_spec_b1 = 0,
+} };
+
+static const uint32_t vdo_idh = VDO_IDH(1, /* Data caps as USB host     */
+					0, /* Not a USB device   */
+					IDH_PTYPE_PERIPH, 1, /* Supports alt
+								modes */
+					USB_VID_GOOGLE);
+
+static const uint32_t vdo_idh_rev30 =
+	VDO_IDH_REV30(1, /* Data caps as USB host     */
+		      0, /* Not a USB device   */
+		      IDH_PTYPE_PERIPH, 1, /* Supports alt modes */
+		      IDH_PTYPE_DFP_HOST, USB_TYPEC_RECEPTACLE, USB_VID_GOOGLE);
+
+static const uint32_t vdo_product =
+	VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV);
 
 /* TODO(b/168890624): add USB4 to capability once USB4 response implemented */
 static const uint32_t vdo_ufp1 = VDO_UFP1(
-				   (VDO_UFP1_CAPABILITY_USB20
-				   | VDO_UFP1_CAPABILITY_USB32),
-				   USB_TYPEC_RECEPTACLE,
-				   VDO_UFP1_ALT_MODE_TBT3,
-				   USB_R30_SS_U40_GEN3);
-
-static const uint32_t vdo_dfp = VDO_DFP(
-				 (VDO_DFP_HOST_CAPABILITY_USB20
-				 | VDO_DFP_HOST_CAPABILITY_USB32
-				 | VDO_DFP_HOST_CAPABILITY_USB4),
-				 USB_TYPEC_RECEPTACLE,
-				 1  /* Port 1 */);
+	(VDO_UFP1_CAPABILITY_USB20 | VDO_UFP1_CAPABILITY_USB32),
+	USB_TYPEC_RECEPTACLE, VDO_UFP1_ALT_MODE_TBT3, USB_R30_SS_U40_GEN3);
+
+static const uint32_t vdo_dfp =
+	VDO_DFP((VDO_DFP_HOST_CAPABILITY_USB20 | VDO_DFP_HOST_CAPABILITY_USB32 |
+		 VDO_DFP_HOST_CAPABILITY_USB4),
+		USB_TYPEC_RECEPTACLE, 1 /* Port 1 */);
 
 static int svdm_tbt_compat_response_identity(int port, uint32_t *payload)
 {
@@ -163,8 +153,8 @@ static int svdm_tbt_compat_response_modes(int port, uint32_t *payload)
 /* Track whether we've been enabled to ACK TBT EnterModes requests */
 static bool tbt_ufp_ack_allowed[CONFIG_USB_PD_PORT_MAX_COUNT];
 
-__override enum ec_status board_set_tbt_ufp_reply(int port,
-						 enum typec_tbt_ufp_reply reply)
+__override enum ec_status
+board_set_tbt_ufp_reply(int port, enum typec_tbt_ufp_reply reply)
 {
 	/* Note: Host command has already bounds-checked port */
 	if (reply == TYPEC_TBT_UFP_REPLY_ACK)
@@ -177,8 +167,7 @@ __override enum ec_status board_set_tbt_ufp_reply(int port,
 	return EC_RES_SUCCESS;
 }
 
-static int svdm_tbt_compat_response_enter_mode(
-	int port, uint32_t *payload)
+static int svdm_tbt_compat_response_enter_mode(int port, uint32_t *payload)
 {
 	mux_state_t mux_state = 0;
 
@@ -191,7 +180,7 @@ static int svdm_tbt_compat_response_enter_mode(
 		return 0; /* NAK */
 
 	if ((PD_VDO_VID(payload[0]) != USB_VID_INTEL) ||
-		(PD_VDO_OPOS(payload[0]) != OPOS_TBT))
+	    (PD_VDO_OPOS(payload[0]) != OPOS_TBT))
 		return 0; /* NAK */
 
 	mux_state = usb_mux_get(port);
@@ -201,7 +190,7 @@ static int svdm_tbt_compat_response_enter_mode(
 	 * Mode that requires the reconfiguring of any pins.
 	 */
 	if ((mux_state & USB_PD_MUX_USB_ENABLED) ||
-		(mux_state & USB_PD_MUX_SAFE_MODE)) {
+	    (mux_state & USB_PD_MUX_SAFE_MODE)) {
 		pd_ufp_set_enter_mode(port, payload);
 		set_tbt_compat_mode_ready(port);
 
@@ -230,3 +219,4 @@ const struct svdm_response svdm_rsp = {
 	.amode = NULL,
 	.exit_mode = NULL,
 };
+#endif /* CONFIG_USB_PD_TBT_COMPAT_MODE */
diff --git a/baseboard/volteer/usbc_config.c b/baseboard/volteer/usbc_config.c
index 36ca78d513..001f47e45f 100644
--- a/baseboard/volteer/usbc_config.c
+++ b/baseboard/volteer/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/baseboard/zork/baseboard.c b/baseboard/zork/baseboard.c
index 0b48d1075b..593bcf1168 100644
--- a/baseboard/zork/baseboard.c
+++ b/baseboard/zork/baseboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -31,6 +31,7 @@
 #include "motion_sense.h"
 #include "power.h"
 #include "power_button.h"
+#include "printf.h"
 #include "pwm.h"
 #include "pwm_chip.h"
 #include "registers.h"
@@ -59,15 +60,15 @@ const enum gpio_signal hibernate_wake_pins[] = {
 	GPIO_POWER_BUTTON_L,
 	GPIO_EC_RST_ODL,
 };
-const int hibernate_wake_pins_used =  ARRAY_SIZE(hibernate_wake_pins);
+const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 
 /*
  * In the AOZ1380 PPC, there are no programmable features.  We use
  * the attached NCT3807 to control a GPIO to indicate 1A5 or 3A0
  * current limits.
  */
-__overridable int board_aoz1380_set_vbus_source_current_limit(int port,
-						enum tcpc_rp_value rp)
+__overridable int
+board_aoz1380_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp)
 {
 	int rv;
 
@@ -96,11 +97,10 @@ static void baseboard_chipset_resume(void)
 DECLARE_HOOK(HOOK_CHIPSET_RESUME, baseboard_chipset_resume, HOOK_PRIO_DEFAULT);
 
 __overridable void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+					  int max_ma, int charge_mv)
 {
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 /* Keyboard scan setting */
@@ -134,19 +134,19 @@ __override struct keyboard_scan_config keyscan_config = {
  * Murata page for part NCP15WB473F03RC. Vdd=3.3V, R=30.9Kohm.
  */
 const struct thermistor_data_pair thermistor_data[] = {
-	{ 2761 / THERMISTOR_SCALING_FACTOR, 0},
-	{ 2492 / THERMISTOR_SCALING_FACTOR, 10},
-	{ 2167 / THERMISTOR_SCALING_FACTOR, 20},
-	{ 1812 / THERMISTOR_SCALING_FACTOR, 30},
-	{ 1462 / THERMISTOR_SCALING_FACTOR, 40},
-	{ 1146 / THERMISTOR_SCALING_FACTOR, 50},
-	{ 878 / THERMISTOR_SCALING_FACTOR, 60},
-	{ 665 / THERMISTOR_SCALING_FACTOR, 70},
-	{ 500 / THERMISTOR_SCALING_FACTOR, 80},
-	{ 434 / THERMISTOR_SCALING_FACTOR, 85},
-	{ 376 / THERMISTOR_SCALING_FACTOR, 90},
-	{ 326 / THERMISTOR_SCALING_FACTOR, 95},
-	{ 283 / THERMISTOR_SCALING_FACTOR, 100}
+	{ 2761 / THERMISTOR_SCALING_FACTOR, 0 },
+	{ 2492 / THERMISTOR_SCALING_FACTOR, 10 },
+	{ 2167 / THERMISTOR_SCALING_FACTOR, 20 },
+	{ 1812 / THERMISTOR_SCALING_FACTOR, 30 },
+	{ 1462 / THERMISTOR_SCALING_FACTOR, 40 },
+	{ 1146 / THERMISTOR_SCALING_FACTOR, 50 },
+	{ 878 / THERMISTOR_SCALING_FACTOR, 60 },
+	{ 665 / THERMISTOR_SCALING_FACTOR, 70 },
+	{ 500 / THERMISTOR_SCALING_FACTOR, 80 },
+	{ 434 / THERMISTOR_SCALING_FACTOR, 85 },
+	{ 376 / THERMISTOR_SCALING_FACTOR, 90 },
+	{ 326 / THERMISTOR_SCALING_FACTOR, 95 },
+	{ 283 / THERMISTOR_SCALING_FACTOR, 100 }
 };
 
 const struct thermistor_info thermistor_info = {
@@ -263,8 +263,10 @@ void board_print_temps(void)
 {
 	int t, i;
 	int rv;
+	char ts_str[PRINTF_TIMESTAMP_BUF_SIZE];
 
-	cprintf(CC_THERMAL, "[%pT ", PRINTF_TIMESTAMP_NOW);
+	snprintf_timestamp_now(ts_str, sizeof(ts_str));
+	cprintf(CC_THERMAL, "[%s ", ts_str);
 	for (i = 0; i < TEMP_SENSOR_COUNT; ++i) {
 		rv = temp_sensor_read(i, &t);
 		if (rv == EC_SUCCESS)
@@ -278,7 +280,7 @@ void board_print_temps(void)
 				   temps_interval * SECOND);
 }
 
-static int command_temps_log(int argc, char **argv)
+static int command_temps_log(int argc, const char **argv)
 {
 	char *e = NULL;
 
@@ -293,8 +295,7 @@ static int command_temps_log(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(tempslog, command_temps_log,
-			"seconds",
+DECLARE_CONSOLE_COMMAND(tempslog, command_temps_log, "seconds",
 			"Print temp sensors periodically");
 
 /*
diff --git a/baseboard/zork/baseboard.h b/baseboard/zork/baseboard.h
index e97bcb4e45..2289c1891b 100644
--- a/baseboard/zork/baseboard.h
+++ b/baseboard/zork/baseboard.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,22 +8,21 @@
 #ifndef __CROS_EC_BASEBOARD_H
 #define __CROS_EC_BASEBOARD_H
 
-#if (defined(VARIANT_ZORK_TREMBYLE) \
-	+ defined(VARIANT_ZORK_DALBOZ)) != 1
+#if (defined(VARIANT_ZORK_TREMBYLE) + defined(VARIANT_ZORK_DALBOZ)) != 1
 #error Must choose VARIANT_ZORK_TREMBYLE or VARIANT_ZORK_DALBOZ
 #endif
 
 /* NPCX7 config */
-#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
-#define NPCX_TACH_SEL2    0  /* No tach. */
-#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
+#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */
+#define NPCX_TACH_SEL2 0 /* No tach. */
+#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */
 
 /* Internal SPI flash on NPCX7 */
 #define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
 #define CONFIG_SPI_FLASH_REGS
 #define CONFIG_SPI_FLASH_W25Q40 /* Internal SPI flash type. */
 
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_HOSTCMD) | CC_MASK(CC_LPC)))
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_HOSTCMD) | CC_MASK(CC_LPC)))
 
 /*
  * Enable 1 slot of secure temporary storage to support
@@ -92,7 +91,7 @@
 #define CONFIG_CHIPSET_CAN_THROTTLE
 #define CONFIG_CHIPSET_RESET_HOOK
 
-#undef  CONFIG_EXTPOWER_DEBOUNCE_MS
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
 #define CONFIG_EXTPOWER_DEBOUNCE_MS 200
 #define CONFIG_EXTPOWER_GPIO
 #define CONFIG_POWER_COMMON
@@ -102,9 +101,9 @@
 #define CONFIG_THROTTLE_AP
 
 #ifdef VARIANT_ZORK_TREMBYLE
-	#define CONFIG_FANS FAN_CH_COUNT
-	#undef CONFIG_FAN_INIT_SPEED
-	#define CONFIG_FAN_INIT_SPEED 50
+#define CONFIG_FANS FAN_CH_COUNT
+#undef CONFIG_FAN_INIT_SPEED
+#define CONFIG_FAN_INIT_SPEED 50
 #endif
 
 #define CONFIG_LED_COMMON
@@ -122,10 +121,9 @@
 #define CONFIG_IO_EXPANDER
 #define CONFIG_IO_EXPANDER_NCT38XX
 
-
 #define CONFIG_KEYBOARD_COL2_INVERTED
 #define CONFIG_KEYBOARD_PROTOCOL_8042
-#undef  CONFIG_KEYBOARD_VIVALDI
+#undef CONFIG_KEYBOARD_VIVALDI
 
 /*
  * USB ID
@@ -141,14 +139,14 @@
 #define CONFIG_USB_PD_TCPMV2
 
 #ifndef CONFIG_USB_PD_TCPMV2
-	#define CONFIG_USB_PD_TCPMV1
+#define CONFIG_USB_PD_TCPMV1
 #else
-	#define CONFIG_USB_PD_DECODE_SOP
-	#define CONFIG_USB_DRP_ACC_TRYSRC
+#define CONFIG_USB_PD_DECODE_SOP
+#define CONFIG_USB_DRP_ACC_TRYSRC
 
-	 /* Enable TCPMv2 Fast Role Swap */
-	 /* Turn off until FRSwap is working */
-	#undef CONFIG_USB_PD_FRS_TCPC
+/* Enable TCPMv2 Fast Role Swap */
+/* Turn off until FRSwap is working */
+#undef CONFIG_USB_PD_FRS_TCPC
 #endif
 
 #define CONFIG_HOSTCMD_PD_CONTROL
@@ -165,7 +163,7 @@
  * Use a custom HPD function that supports HPD on IO expander.
  * TODO(b/165622386) remove this when HPD is on EC GPIO.
  */
-#	define CONFIG_USB_PD_DP_HPD_GPIO_CUSTOM
+#define CONFIG_USB_PD_DP_HPD_GPIO_CUSTOM
 #endif
 #define CONFIG_USB_PD_DUAL_ROLE
 #define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
@@ -187,19 +185,19 @@
 #define CONFIG_USB_MUX_AMD_FP5
 
 #if defined(VARIANT_ZORK_TREMBYLE)
-	#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-	#define CONFIG_USBC_PPC_NX20P3483
-	#define CONFIG_USBC_RETIMER_PS8802
-	#define CONFIG_USBC_RETIMER_PS8818
-	#define CONFIG_IO_EXPANDER_PORT_COUNT USBC_PORT_COUNT
-	#define CONFIG_USB_MUX_RUNTIME_CONFIG
-	/* USB-A config */
-	#define GPIO_USB1_ILIM_SEL IOEX_USB_A0_CHARGE_EN_L
-	#define GPIO_USB2_ILIM_SEL IOEX_USB_A1_CHARGE_EN_DB_L
-	/* PS8818 RX Input Termination - default value */
-	#define ZORK_PS8818_RX_INPUT_TERM PS8818_RX_INPUT_TERM_112_OHM
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#define CONFIG_USBC_PPC_NX20P3483
+#define CONFIG_USBC_RETIMER_PS8802
+#define CONFIG_USBC_RETIMER_PS8818
+#define CONFIG_IO_EXPANDER_PORT_COUNT USBC_PORT_COUNT
+#define CONFIG_USB_MUX_RUNTIME_CONFIG
+/* USB-A config */
+#define GPIO_USB1_ILIM_SEL IOEX_USB_A0_CHARGE_EN_L
+#define GPIO_USB2_ILIM_SEL IOEX_USB_A1_CHARGE_EN_DB_L
+/* PS8818 RX Input Termination - default value */
+#define ZORK_PS8818_RX_INPUT_TERM PS8818_RX_INPUT_TERM_112_OHM
 #elif defined(VARIANT_ZORK_DALBOZ)
-	#define CONFIG_IO_EXPANDER_PORT_COUNT IOEX_PORT_COUNT
+#define CONFIG_IO_EXPANDER_PORT_COUNT IOEX_PORT_COUNT
 #endif
 
 /* USB-A config */
@@ -209,13 +207,13 @@
 #define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_CDP
 #define CONFIG_USB_PORT_POWER_SMART_INVERTED
 
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
 
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		65000
-#define PD_MAX_CURRENT_MA	3250
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 65000
+#define PD_MAX_CURRENT_MA 3250
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Round up 3250 max current to multiple of 128mA for ISL9241 AC prochot. */
 #define ZORK_AC_PROCHOT_CURRENT_MA 3328
@@ -225,7 +223,7 @@
  * CONFIG_CHARGER_LIMIT_* is not set, so there is no additional restriction on
  * Depthcharge to boot OS.
  */
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON		50000
+#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 50000
 
 /* Increase length of history buffer for port80 messages. */
 #undef CONFIG_PORT80_HISTORY_LEN
@@ -235,30 +233,30 @@
 #undef CONFIG_UART_TX_BUF_SIZE
 #define CONFIG_UART_TX_BUF_SIZE 4096
 
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT0_0
-#define I2C_PORT_USBA0		NPCX_I2C_PORT0_0
-#define I2C_PORT_TCPC1		NPCX_I2C_PORT1_0
-#define I2C_PORT_USBA1		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_AP_MUX	NPCX_I2C_PORT3_0
-#define I2C_PORT_THERMAL_AP	NPCX_I2C_PORT4_1
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT5_0
-#define I2C_PORT_ACCEL		I2C_PORT_SENSOR
-#define I2C_PORT_EEPROM		I2C_PORT_SENSOR
-#define I2C_PORT_AP_AUDIO	NPCX_I2C_PORT6_1
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0
+#define I2C_PORT_USBA0 NPCX_I2C_PORT0_0
+#define I2C_PORT_TCPC1 NPCX_I2C_PORT1_0
+#define I2C_PORT_USBA1 NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_AP_MUX NPCX_I2C_PORT3_0
+#define I2C_PORT_THERMAL_AP NPCX_I2C_PORT4_1
+#define I2C_PORT_SENSOR NPCX_I2C_PORT5_0
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
+#define I2C_PORT_EEPROM I2C_PORT_SENSOR
+#define I2C_PORT_AP_AUDIO NPCX_I2C_PORT6_1
 
 #if defined(VARIANT_ZORK_TREMBYLE)
-	#define CONFIG_CHARGER_RUNTIME_CONFIG
-	#define I2C_PORT_BATTERY	NPCX_I2C_PORT2_0
-	#define I2C_PORT_CHARGER_V0	NPCX_I2C_PORT2_0
-	#define I2C_PORT_CHARGER_V1	NPCX_I2C_PORT4_1
-	#define I2C_PORT_AP_HDMI	NPCX_I2C_PORT7_0
+#define CONFIG_CHARGER_RUNTIME_CONFIG
+#define I2C_PORT_BATTERY NPCX_I2C_PORT2_0
+#define I2C_PORT_CHARGER_V0 NPCX_I2C_PORT2_0
+#define I2C_PORT_CHARGER_V1 NPCX_I2C_PORT4_1
+#define I2C_PORT_AP_HDMI NPCX_I2C_PORT7_0
 #elif defined(VARIANT_ZORK_DALBOZ)
-	#define I2C_PORT_BATTERY_V0	NPCX_I2C_PORT2_0
-	#define I2C_PORT_BATTERY_V1	NPCX_I2C_PORT7_0
-	#define I2C_PORT_CHARGER	NPCX_I2C_PORT2_0
+#define I2C_PORT_BATTERY_V0 NPCX_I2C_PORT2_0
+#define I2C_PORT_BATTERY_V1 NPCX_I2C_PORT7_0
+#define I2C_PORT_CHARGER NPCX_I2C_PORT2_0
 #endif
 
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 
 #define CONFIG_MKBP_EVENT
 /* Host event is required to wake from sleep */
@@ -310,11 +308,7 @@ enum fan_channel {
 };
 
 #ifdef VARIANT_ZORK_TREMBYLE
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 #endif
 
 enum sensor_id {
diff --git a/baseboard/zork/build.mk b/baseboard/zork/build.mk
index e79d60cc91..6cf67a1a39 100644
--- a/baseboard/zork/build.mk
+++ b/baseboard/zork/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/baseboard/zork/cbi_ec_fw_config.c b/baseboard/zork/cbi_ec_fw_config.c
index 50a29d3634..4482a5cf40 100644
--- a/baseboard/zork/cbi_ec_fw_config.c
+++ b/baseboard/zork/cbi_ec_fw_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -28,8 +28,7 @@ uint32_t get_cbi_fw_config(void)
  */
 enum ec_cfg_usb_db_type ec_config_get_usb_db(void)
 {
-	return ((get_cbi_fw_config() & EC_CFG_USB_DB_MASK)
-			>> EC_CFG_USB_DB_L);
+	return ((get_cbi_fw_config() & EC_CFG_USB_DB_MASK) >> EC_CFG_USB_DB_L);
 }
 
 /*
@@ -37,8 +36,7 @@ enum ec_cfg_usb_db_type ec_config_get_usb_db(void)
  */
 enum ec_cfg_usb_mb_type ec_config_get_usb_mb(void)
 {
-	return ((get_cbi_fw_config() & EC_CFG_USB_MB_MASK)
-			>> EC_CFG_USB_MB_L);
+	return ((get_cbi_fw_config() & EC_CFG_USB_MB_MASK) >> EC_CFG_USB_MB_L);
 }
 
 /*
@@ -46,8 +44,8 @@ enum ec_cfg_usb_mb_type ec_config_get_usb_mb(void)
  */
 enum ec_cfg_lid_accel_sensor_type ec_config_has_lid_accel_sensor(void)
 {
-	return ((get_cbi_fw_config() & EC_CFG_LID_ACCEL_SENSOR_MASK)
-			>> EC_CFG_LID_ACCEL_SENSOR_L);
+	return ((get_cbi_fw_config() & EC_CFG_LID_ACCEL_SENSOR_MASK) >>
+		EC_CFG_LID_ACCEL_SENSOR_L);
 }
 
 /*
@@ -55,28 +53,27 @@ enum ec_cfg_lid_accel_sensor_type ec_config_has_lid_accel_sensor(void)
  */
 enum ec_ssfc_base_gyro_sensor ec_config_has_base_gyro_sensor(void)
 {
-	return ((get_cbi_fw_config() & EC_CFG_BASE_GYRO_SENSOR_MASK)
-			>> EC_CFG_BASE_GYRO_SENSOR_L);
+	return ((get_cbi_fw_config() & EC_CFG_BASE_GYRO_SENSOR_MASK) >>
+		EC_CFG_BASE_GYRO_SENSOR_L);
 }
 
 /*
  * ec_config_has_pwm_keyboard_backlight() will return 1 is present or 0
  */
-enum ec_cfg_pwm_keyboard_backlight_type ec_config_has_pwm_keyboard_backlight(
-									void)
+enum ec_cfg_pwm_keyboard_backlight_type
+ec_config_has_pwm_keyboard_backlight(void)
 {
-	return ((get_cbi_fw_config() & EC_CFG_PWM_KEYBOARD_BACKLIGHT_MASK)
-			>> EC_CFG_PWM_KEYBOARD_BACKLIGHT_L);
+	return ((get_cbi_fw_config() & EC_CFG_PWM_KEYBOARD_BACKLIGHT_MASK) >>
+		EC_CFG_PWM_KEYBOARD_BACKLIGHT_L);
 }
 
 /*
  * ec_config_has_lid_angle_tablet_mode() will return 1 is present or 0
  */
-enum ec_cfg_lid_angle_tablet_mode_type ec_config_has_lid_angle_tablet_mode(
-									void)
+enum ec_cfg_lid_angle_tablet_mode_type ec_config_has_lid_angle_tablet_mode(void)
 {
-	return ((get_cbi_fw_config() & EC_CFG_LID_ANGLE_TABLET_MODE_MASK)
-			>> EC_CFG_LID_ANGLE_TABLET_MODE_L);
+	return ((get_cbi_fw_config() & EC_CFG_LID_ANGLE_TABLET_MODE_MASK) >>
+		EC_CFG_LID_ANGLE_TABLET_MODE_L);
 }
 
 /*
@@ -84,8 +81,8 @@ enum ec_cfg_lid_angle_tablet_mode_type ec_config_has_lid_angle_tablet_mode(
  */
 enum ec_cfg_lte_present_type ec_config_lte_present(void)
 {
-	return ((get_cbi_fw_config() & EC_CFG_LTE_PRESENT_MASK)
-			>> EC_CFG_LTE_PRESENT_L);
+	return ((get_cbi_fw_config() & EC_CFG_LTE_PRESENT_MASK) >>
+		EC_CFG_LTE_PRESENT_L);
 }
 
 /*
@@ -93,6 +90,6 @@ enum ec_cfg_lte_present_type ec_config_lte_present(void)
  */
 enum ec_cfg_keyboard_layout_type ec_config_keyboard_layout(void)
 {
-	return ((get_cbi_fw_config() & EC_CFG_KEYBOARD_LAYOUT_MASK)
-			>> EC_CFG_KEYBOARD_LAYOUT_L);
+	return ((get_cbi_fw_config() & EC_CFG_KEYBOARD_LAYOUT_MASK) >>
+		EC_CFG_KEYBOARD_LAYOUT_L);
 }
diff --git a/baseboard/zork/cbi_ec_fw_config.h b/baseboard/zork/cbi_ec_fw_config.h
index c3ed5b654c..a73e4504bb 100644
--- a/baseboard/zork/cbi_ec_fw_config.h
+++ b/baseboard/zork/cbi_ec_fw_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,11 +19,9 @@
  * get_cbi_ec_cfg_usb_db() will return the DB option number.
  * The option number will be defined in a variant or board level enumeration
  */
-#define EC_CFG_USB_DB_L				0
-#define EC_CFG_USB_DB_H				3
-#define EC_CFG_USB_DB_MASK \
-				GENMASK(EC_CFG_USB_DB_H,\
-					EC_CFG_USB_DB_L)
+#define EC_CFG_USB_DB_L 0
+#define EC_CFG_USB_DB_H 3
+#define EC_CFG_USB_DB_MASK GENMASK(EC_CFG_USB_DB_H, EC_CFG_USB_DB_L)
 
 /*
  * USB Main Board (4 bits)
@@ -31,11 +29,9 @@
  * get_cbi_ec_cfg_usb_mb() will return the MB option number.
  * The option number will be defined in a variant or board level enumeration
  */
-#define EC_CFG_USB_MB_L				4
-#define EC_CFG_USB_MB_H				7
-#define EC_CFG_USB_MB_MASK \
-				GENMASK(EC_CFG_USB_MB_H,\
-					EC_CFG_USB_MB_L)
+#define EC_CFG_USB_MB_L 4
+#define EC_CFG_USB_MB_H 7
+#define EC_CFG_USB_MB_MASK GENMASK(EC_CFG_USB_MB_H, EC_CFG_USB_MB_L)
 
 /*
  * Lid Accelerometer Sensor (3 bits)
@@ -47,22 +43,20 @@ enum ec_cfg_lid_accel_sensor_type {
 	LID_ACCEL_KX022 = 1,
 	LID_ACCEL_LIS2DWL = 2,
 };
-#define EC_CFG_LID_ACCEL_SENSOR_L		8
-#define EC_CFG_LID_ACCEL_SENSOR_H		10
-#define EC_CFG_LID_ACCEL_SENSOR_MASK	\
-				GENMASK(EC_CFG_LID_ACCEL_SENSOR_H,\
-					EC_CFG_LID_ACCEL_SENSOR_L)
+#define EC_CFG_LID_ACCEL_SENSOR_L 8
+#define EC_CFG_LID_ACCEL_SENSOR_H 10
+#define EC_CFG_LID_ACCEL_SENSOR_MASK \
+	GENMASK(EC_CFG_LID_ACCEL_SENSOR_H, EC_CFG_LID_ACCEL_SENSOR_L)
 
 /*
  * Base Gyro Sensor (3 bits)
  *
  * ec_config_has_base_gyro_sensor() will return ec_cfg_base_gyro_sensor_type
  */
-#define EC_CFG_BASE_GYRO_SENSOR_L		11
-#define EC_CFG_BASE_GYRO_SENSOR_H		13
-#define EC_CFG_BASE_GYRO_SENSOR_MASK	\
-				GENMASK(EC_CFG_BASE_GYRO_SENSOR_H,\
-					EC_CFG_BASE_GYRO_SENSOR_L)
+#define EC_CFG_BASE_GYRO_SENSOR_L 11
+#define EC_CFG_BASE_GYRO_SENSOR_H 13
+#define EC_CFG_BASE_GYRO_SENSOR_MASK \
+	GENMASK(EC_CFG_BASE_GYRO_SENSOR_H, EC_CFG_BASE_GYRO_SENSOR_L)
 
 /*
  * PWM Keyboard Backlight (1 bit)
@@ -73,11 +67,11 @@ enum ec_cfg_pwm_keyboard_backlight_type {
 	PWM_KEYBOARD_BACKLIGHT_NO = 0,
 	PWM_KEYBOARD_BACKLIGHT_YES = 1,
 };
-#define EC_CFG_PWM_KEYBOARD_BACKLIGHT_L		14
-#define EC_CFG_PWM_KEYBOARD_BACKLIGHT_H		14
-#define EC_CFG_PWM_KEYBOARD_BACKLIGHT_MASK \
-				GENMASK(EC_CFG_PWM_KEYBOARD_BACKLIGHT_H,\
-					EC_CFG_PWM_KEYBOARD_BACKLIGHT_L)
+#define EC_CFG_PWM_KEYBOARD_BACKLIGHT_L 14
+#define EC_CFG_PWM_KEYBOARD_BACKLIGHT_H 14
+#define EC_CFG_PWM_KEYBOARD_BACKLIGHT_MASK       \
+	GENMASK(EC_CFG_PWM_KEYBOARD_BACKLIGHT_H, \
+		EC_CFG_PWM_KEYBOARD_BACKLIGHT_L)
 
 /*
  * Lid Angle Tablet Mode (1 bit)
@@ -88,11 +82,10 @@ enum ec_cfg_lid_angle_tablet_mode_type {
 	LID_ANGLE_TABLET_MODE_NO = 0,
 	LID_ANGLE_TABLET_MODE_YES = 1,
 };
-#define EC_CFG_LID_ANGLE_TABLET_MODE_L		15
-#define EC_CFG_LID_ANGLE_TABLET_MODE_H		15
+#define EC_CFG_LID_ANGLE_TABLET_MODE_L 15
+#define EC_CFG_LID_ANGLE_TABLET_MODE_H 15
 #define EC_CFG_LID_ANGLE_TABLET_MODE_MASK \
-				GENMASK(EC_CFG_LID_ANGLE_TABLET_MODE_H,\
-					EC_CFG_LID_ANGLE_TABLET_MODE_L)
+	GENMASK(EC_CFG_LID_ANGLE_TABLET_MODE_H, EC_CFG_LID_ANGLE_TABLET_MODE_L)
 
 /*
  * LTE Modem Present (1 bit)
@@ -103,11 +96,10 @@ enum ec_cfg_lte_present_type {
 	LTE_NONE = 0,
 	LTE_PRESENT = 1,
 };
-#define EC_CFG_LTE_PRESENT_L		29
-#define EC_CFG_LTE_PRESENT_H		29
+#define EC_CFG_LTE_PRESENT_L 29
+#define EC_CFG_LTE_PRESENT_H 29
 #define EC_CFG_LTE_PRESENT_MASK \
-				GENMASK(EC_CFG_LTE_PRESENT_H,\
-					EC_CFG_LTE_PRESENT_L)
+	GENMASK(EC_CFG_LTE_PRESENT_H, EC_CFG_LTE_PRESENT_L)
 
 /*
  * Keyboard Layout (2 bit)
@@ -118,22 +110,20 @@ enum ec_cfg_keyboard_layout_type {
 	KB_LAYOUT_DEFAULT = 0,
 	KB_LAYOUT_1 = 1,
 };
-#define EC_CFG_KEYBOARD_LAYOUT_L		30
-#define EC_CFG_KEYBOARD_LAYOUT_H		31
+#define EC_CFG_KEYBOARD_LAYOUT_L 30
+#define EC_CFG_KEYBOARD_LAYOUT_H 31
 #define EC_CFG_KEYBOARD_LAYOUT_MASK \
-				GENMASK(EC_CFG_KEYBOARD_LAYOUT_H,\
-					EC_CFG_KEYBOARD_LAYOUT_L)
-
+	GENMASK(EC_CFG_KEYBOARD_LAYOUT_H, EC_CFG_KEYBOARD_LAYOUT_L)
 
 uint32_t get_cbi_fw_config(void);
 enum ec_cfg_usb_db_type ec_config_get_usb_db(void);
 enum ec_cfg_usb_mb_type ec_config_get_usb_mb(void);
 enum ec_cfg_lid_accel_sensor_type ec_config_has_lid_accel_sensor(void);
 enum ec_ssfc_base_gyro_sensor ec_config_has_base_gyro_sensor(void);
-enum ec_cfg_pwm_keyboard_backlight_type ec_config_has_pwm_keyboard_backlight(
-									void);
-enum ec_cfg_lid_angle_tablet_mode_type ec_config_has_lid_angle_tablet_mode(
-									void);
+enum ec_cfg_pwm_keyboard_backlight_type
+ec_config_has_pwm_keyboard_backlight(void);
+enum ec_cfg_lid_angle_tablet_mode_type
+ec_config_has_lid_angle_tablet_mode(void);
 enum ec_cfg_lte_present_type ec_config_lte_present(void);
 enum ec_cfg_keyboard_layout_type ec_config_keyboard_layout(void);
 
diff --git a/baseboard/zork/cbi_ssfc.c b/baseboard/zork/cbi_ssfc.c
index 1078ec6486..9cc2fdcef3 100644
--- a/baseboard/zork/cbi_ssfc.c
+++ b/baseboard/zork/cbi_ssfc.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -38,11 +38,10 @@ enum ec_ssfc_spkr_auto_mode get_cbi_ssfc_spkr_auto_mode(void)
 enum ec_ssfc_edp_phy_alt_tuning get_cbi_ssfc_edp_phy_alt_tuning(void)
 {
 	return (cached_ssfc & SSFC_EDP_PHY_ALT_TUNING_MASK) >>
-		SSFC_EDP_PHY_ALT_TUNING_OFFSET;
+	       SSFC_EDP_PHY_ALT_TUNING_OFFSET;
 }
 
 enum ec_ssfc_c1_mux get_cbi_ssfc_c1_mux(void)
 {
-	return (cached_ssfc & SSFC_C1_MUX_MASK) >>
-		SSFC_C1_MUX_OFFSET;
+	return (cached_ssfc & SSFC_C1_MUX_MASK) >> SSFC_C1_MUX_OFFSET;
 }
diff --git a/baseboard/zork/cbi_ssfc.h b/baseboard/zork/cbi_ssfc.h
index 1d201594b0..95bf5ba6e4 100644
--- a/baseboard/zork/cbi_ssfc.h
+++ b/baseboard/zork/cbi_ssfc.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/baseboard/zork/usb_pd_policy.c b/baseboard/zork/usb_pd_policy.c
index 8dcdfa7635..aeca706eb2 100644
--- a/baseboard/zork/usb_pd_policy.c
+++ b/baseboard/zork/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,8 +18,8 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
diff --git a/baseboard/zork/variant_dalboz.c b/baseboard/zork/variant_dalboz.c
index 10058bb8bc..599f29618b 100644
--- a/baseboard/zork/variant_dalboz.c
+++ b/baseboard/zork/variant_dalboz.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -58,7 +58,7 @@ int board_get_temp(int idx, int *temp_k)
 
 		/* adc power not ready when transition to S5 */
 		if (chipset_in_or_transitioning_to_state(
-			CHIPSET_STATE_SOFT_OFF))
+			    CHIPSET_STATE_SOFT_OFF))
 			return EC_ERROR_NOT_POWERED;
 
 		channel = ADC_TEMP_SENSOR_SOC;
diff --git a/baseboard/zork/variant_trembyle.c b/baseboard/zork/variant_trembyle.c
index f9173df05a..9c29e057cc 100644
--- a/baseboard/zork/variant_trembyle.c
+++ b/baseboard/zork/variant_trembyle.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,10 +9,10 @@
 #include "console.h"
 #include "driver/bc12/pi3usb9201.h"
 #include "driver/charger/isl9241.h"
-#include "driver/ppc/aoz1380.h"
+#include "driver/ppc/aoz1380_public.h"
 #include "driver/ppc/nx20p348x.h"
 #include "driver/retimer/ps8802.h"
-#include "driver/retimer/ps8818.h"
+#include "driver/retimer/ps8818_public.h"
 #include "driver/retimer/tusb544.h"
 #include "driver/tcpm/nct38xx.h"
 #include "driver/usb_mux/amd_fp5.h"
@@ -28,8 +28,8 @@
 #include "usb_pd_tcpm.h"
 #include "usbc_ppc.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 const struct i2c_port_t i2c_ports[] = {
 	{
@@ -160,8 +160,7 @@ __overridable void ppc_interrupt(enum gpio_signal signal)
 
 int board_set_active_charge_port(int port)
 {
-	int is_valid_port = (port >= 0 &&
-			     port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	int i;
 
 	if (port == CHARGE_PORT_NONE) {
@@ -182,7 +181,6 @@ int board_set_active_charge_port(int port)
 		return EC_ERROR_INVAL;
 	}
 
-
 	/* Check if the port is sourcing VBUS. */
 	if (ppc_is_sourcing_vbus(port)) {
 		CPRINTFUSB("Skip enable C%d", port);
@@ -284,7 +282,6 @@ static void reset_nct38xx_port(int port)
 		msleep(NCT3807_RESET_POST_DELAY_MS);
 }
 
-
 void board_reset_pd_mcu(void)
 {
 	/* Reset TCPC0 */
@@ -333,18 +330,15 @@ void tcpc_alert_event(enum gpio_signal signal)
 	schedule_deferred_pd_interrupt(port);
 }
 
-
 int board_pd_set_frs_enable(int port, int enable)
 {
 	int rv = EC_SUCCESS;
 
 	/* Use the TCPC to enable fast switch when FRS included */
 	if (port == USBC_PORT_C0) {
-		rv = ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN,
-				    !!enable);
+		rv = ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN, !!enable);
 	} else {
-		rv = ioex_set_level(IOEX_USB_C1_TCPC_FASTSW_CTL_EN,
-				    !!enable);
+		rv = ioex_set_level(IOEX_USB_C1_TCPC_FASTSW_CTL_EN, !!enable);
 	}
 
 	return rv;
@@ -393,8 +387,7 @@ BUILD_ASSERT(CONFIG_IO_EXPANDER_PORT_COUNT == USBC_PORT_COUNT);
  * PS8802 set mux board tuning.
  * Adds in board specific gain and DP lane count configuration
  */
-static int board_ps8802_mux_set(const struct usb_mux *me,
-				mux_state_t mux_state)
+static int board_ps8802_mux_set(const struct usb_mux *me, mux_state_t mux_state)
 {
 	int rv = EC_SUCCESS;
 
@@ -406,11 +399,10 @@ static int board_ps8802_mux_set(const struct usb_mux *me,
 	/* USB specific config */
 	if (mux_state & USB_PD_MUX_USB_ENABLED) {
 		/* Boost the USB gain */
-		rv = ps8802_i2c_field_update16(me,
-					PS8802_REG_PAGE2,
-					PS8802_REG2_USB_SSEQ_LEVEL,
-					PS8802_USBEQ_LEVEL_UP_MASK,
-					PS8802_USBEQ_LEVEL_UP_19DB);
+		rv = ps8802_i2c_field_update16(me, PS8802_REG_PAGE2,
+					       PS8802_REG2_USB_SSEQ_LEVEL,
+					       PS8802_USBEQ_LEVEL_UP_MASK,
+					       PS8802_USBEQ_LEVEL_UP_19DB);
 		if (rv)
 			return rv;
 	}
@@ -418,11 +410,10 @@ static int board_ps8802_mux_set(const struct usb_mux *me,
 	/* DP specific config */
 	if (mux_state & USB_PD_MUX_DP_ENABLED) {
 		/* Boost the DP gain */
-		rv = ps8802_i2c_field_update8(me,
-					PS8802_REG_PAGE2,
-					PS8802_REG2_DPEQ_LEVEL,
-					PS8802_DPEQ_LEVEL_UP_MASK,
-					PS8802_DPEQ_LEVEL_UP_19DB);
+		rv = ps8802_i2c_field_update8(me, PS8802_REG_PAGE2,
+					      PS8802_REG2_DPEQ_LEVEL,
+					      PS8802_DPEQ_LEVEL_UP_MASK,
+					      PS8802_DPEQ_LEVEL_UP_19DB);
 		if (rv)
 			return rv;
 	}
@@ -434,52 +425,46 @@ static int board_ps8802_mux_set(const struct usb_mux *me,
  * PS8818 set mux board tuning.
  * Adds in board specific gain and DP lane count configuration
  */
-static int board_ps8818_mux_set(const struct usb_mux *me,
-				mux_state_t mux_state)
+static int board_ps8818_mux_set(const struct usb_mux *me, mux_state_t mux_state)
 {
 	int rv = EC_SUCCESS;
 
 	/* USB specific config */
 	if (mux_state & USB_PD_MUX_USB_ENABLED) {
 		/* Boost the USB gain */
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX1EQ_10G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_19DB);
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_APTX1EQ_10G_LEVEL,
+					      PS8818_EQ_LEVEL_UP_MASK,
+					      PS8818_EQ_LEVEL_UP_19DB);
 		if (rv)
 			return rv;
 
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX2EQ_10G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_19DB);
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_APTX2EQ_10G_LEVEL,
+					      PS8818_EQ_LEVEL_UP_MASK,
+					      PS8818_EQ_LEVEL_UP_19DB);
 		if (rv)
 			return rv;
 
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX1EQ_5G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_19DB);
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_APTX1EQ_5G_LEVEL,
+					      PS8818_EQ_LEVEL_UP_MASK,
+					      PS8818_EQ_LEVEL_UP_19DB);
 		if (rv)
 			return rv;
 
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX2EQ_5G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_19DB);
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_APTX2EQ_5G_LEVEL,
+					      PS8818_EQ_LEVEL_UP_MASK,
+					      PS8818_EQ_LEVEL_UP_19DB);
 		if (rv)
 			return rv;
 
 		/* Set the RX input termination */
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_RX_PHY,
-					PS8818_RX_INPUT_TERM_MASK,
-					ZORK_PS8818_RX_INPUT_TERM);
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_RX_PHY,
+					      PS8818_RX_INPUT_TERM_MASK,
+					      ZORK_PS8818_RX_INPUT_TERM);
 		if (rv)
 			return rv;
 	}
@@ -487,11 +472,10 @@ static int board_ps8818_mux_set(const struct usb_mux *me,
 	/* DP specific config */
 	if (mux_state & USB_PD_MUX_DP_ENABLED) {
 		/* Boost the DP gain */
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_DPEQ_LEVEL,
-					PS8818_DPEQ_LEVEL_UP_MASK,
-					PS8818_DPEQ_LEVEL_UP_19DB);
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_DPEQ_LEVEL,
+					      PS8818_DPEQ_LEVEL_UP_MASK,
+					      PS8818_DPEQ_LEVEL_UP_19DB);
 		if (rv)
 			return rv;
 
@@ -505,7 +489,7 @@ static int board_ps8818_mux_set(const struct usb_mux *me,
 	return rv;
 }
 
-const struct usb_mux usbc1_ps8802 = {
+struct usb_mux usbc1_ps8802 = {
 	.usb_port = USBC_PORT_C1,
 	.i2c_port = I2C_PORT_TCPC1,
 	.i2c_addr_flags = PS8802_I2C_ADDR_FLAGS,
diff --git a/board/adlrvpm_ite/board.h b/board/adlrvpm_ite/board.h
index 2c75a3883c..37662a5d52 120000..100644
--- a/board/adlrvpm_ite/board.h
+++ b/board/adlrvpm_ite/board.h
@@ -1 +1,102 @@
-../adlrvpp_ite/board.h
\ No newline at end of file
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel ADL-P-RVP-ITE board-specific configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* ITE EC variant */
+#define VARIANT_INTELRVP_EC_IT8320
+
+#include "adlrvp.h"
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+#define GPIO_AC_PRESENT GPIO_BC_ACOK_EC
+#define GPIO_EC_INT_L GPIO_EC_PCH_MKBP_INT_ODL_EC
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW_EC
+#define GPIO_LID_OPEN GPIO_SMC_LID
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE_EC
+#define GPIO_PCH_WAKE_L GPIO_PCH_WAKE_N
+#define GPIO_PCH_PWRBTN_L GPIO_PM_PWRBTN_N_EC
+#define GPIO_PCH_RSMRST_L GPIO_PM_RSMRST_EC
+#define GPIO_PCH_SLP_S0_L GPIO_PCH_SLP_S0_N
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_R_L
+#define GPIO_PG_EC_DSW_PWROK GPIO_VCCPDSW_3P3_EC
+#define GPIO_POWER_BUTTON_L GPIO_MECH_PWR_BTN_ODL
+#define GPIO_CPU_PROCHOT GPIO_PROCHOT_EC
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL_EC
+#define GPIO_WP_L GPIO_EC_WP_ODL
+#define GPIO_VOLUME_UP_L GPIO_VOLUME_UP
+#define GPIO_VOLUME_DOWN_L GPIO_VOL_DN_EC_R
+#define GPIO_DC_JACK_PRESENT GPIO_STD_ADP_PRSNT
+#define GPIO_ESPI_RESET_L GPIO_ESPI_RST_R
+#define GPIO_UART1_RX GPIO_UART_SERVO_TX_EC_RX
+#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BAT_DET_EC
+#define GPIO_BAT_LED_RED_L GPIO_LED_1_L_EC
+#define GPIO_PWR_LED_WHITE_L GPIO_LED_2_L_EC
+#define GPIO_SLP_SUS_L GPIO_PM_SLP_SUS_EC
+#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_PWRGD_EC
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_ALL_SYS_PWRGD_EC
+#define GPIO_PCH_DSW_PWROK GPIO_DSW_PWROK_EC
+#define GPIO_EN_PP3300_A GPIO_EC_DS3
+#define GPIO_TABLET_MODE_L GPIO_SLATE_MODE_INDICATION
+
+/* I2C ports & Configs */
+#define CONFIG_IT83XX_SMCLK2_ON_GPC7
+
+#define I2C_PORT_CHARGER IT83XX_I2C_CH_B
+
+/* Battery */
+#define I2C_PORT_BATTERY IT83XX_I2C_CH_B
+
+/* Board ID */
+#define I2C_PORT_PCA9555_BOARD_ID_GPIO IT83XX_I2C_CH_B
+
+/* Port 80 */
+#define I2C_PORT_PORT80 IT83XX_I2C_CH_B
+
+/* USB-C I2C */
+#define I2C_PORT_TYPEC_0 IT83XX_I2C_CH_C
+#define I2C_PORT_TYPEC_1 IT83XX_I2C_CH_F
+#if defined(HAS_TASK_PD_C2)
+#define I2C_PORT_TYPEC_2 IT83XX_I2C_CH_E
+#define I2C_PORT_TYPEC_3 IT83XX_I2C_CH_D
+#endif
+
+/* TCPC */
+#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP
+#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1
+
+/* Config Fan */
+#define GPIO_FAN_POWER_EN GPIO_EC_THRM_SEN_PWRGATE_N
+#define GPIO_ALL_SYS_PWRGD GPIO_ALL_SYS_PWRGD_EC
+
+/* Increase EC speed */
+#undef PLL_CLOCK
+#define PLL_CLOCK 96000000
+
+#ifndef __ASSEMBLER__
+
+enum adlrvp_i2c_channel {
+	I2C_CHAN_FLASH,
+	I2C_CHAN_BATT_CHG,
+	I2C_CHAN_TYPEC_0,
+	I2C_CHAN_TYPEC_1,
+#if defined(HAS_TASK_PD_C2)
+	I2C_CHAN_TYPEC_2,
+	I2C_CHAN_TYPEC_3,
+#endif
+	I2C_CHAN_COUNT,
+};
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/adlrvpm_ite/ec.tasklist b/board/adlrvpm_ite/ec.tasklist
index 48c033d14c..b0afc9e9a7 100644
--- a/board/adlrvpm_ite/ec.tasklist
+++ b/board/adlrvpm_ite/ec.tasklist
@@ -1,5 +1,5 @@
 /*
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/adlrvpp_ite/board.c b/board/adlrvpp_ite/board.c
index 15aa1c46d7..aa2764f823 100644
--- a/board/adlrvpp_ite/board.c
+++ b/board/adlrvpp_ite/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/adlrvpp_ite/board.h b/board/adlrvpp_ite/board.h
index 55b56854ea..37662a5d52 100644
--- a/board/adlrvpp_ite/board.h
+++ b/board/adlrvpp_ite/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,56 +19,56 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_AC_PRESENT			GPIO_BC_ACOK_EC
-#define GPIO_EC_INT_L			GPIO_EC_PCH_MKBP_INT_ODL_EC
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW_EC
-#define GPIO_LID_OPEN			GPIO_SMC_LID
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE_EC
-#define GPIO_PCH_WAKE_L			GPIO_PCH_WAKE_N
-#define GPIO_PCH_PWRBTN_L		GPIO_PM_PWRBTN_N_EC
-#define GPIO_PCH_RSMRST_L		GPIO_PM_RSMRST_EC
-#define GPIO_PCH_SLP_S0_L		GPIO_PCH_SLP_S0_N
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_R_L
-#define GPIO_PG_EC_DSW_PWROK		GPIO_VCCPDSW_3P3_EC
-#define GPIO_POWER_BUTTON_L		GPIO_MECH_PWR_BTN_ODL
-#define GPIO_CPU_PROCHOT		GPIO_PROCHOT_EC
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL_EC
-#define GPIO_WP_L			GPIO_EC_WP_ODL
-#define GPIO_VOLUME_UP_L		GPIO_VOLUME_UP
-#define GPIO_VOLUME_DOWN_L		GPIO_VOL_DN_EC_R
-#define GPIO_DC_JACK_PRESENT		GPIO_STD_ADP_PRSNT
-#define GPIO_ESPI_RESET_L		GPIO_ESPI_RST_R
-#define GPIO_UART1_RX			GPIO_UART_SERVO_TX_EC_RX
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_BAT_DET_EC
-#define GPIO_BAT_LED_RED_L		GPIO_LED_1_L_EC
-#define GPIO_PWR_LED_WHITE_L		GPIO_LED_2_L_EC
-#define GPIO_SLP_SUS_L			GPIO_PM_SLP_SUS_EC
-#define GPIO_PG_EC_RSMRST_ODL		GPIO_RSMRST_PWRGD_EC
-#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_ALL_SYS_PWRGD_EC
-#define GPIO_PCH_DSW_PWROK		GPIO_DSW_PWROK_EC
-#define GPIO_EN_PP3300_A		GPIO_EC_DS3
-#define GPIO_TABLET_MODE_L		GPIO_SLATE_MODE_INDICATION
+#define GPIO_AC_PRESENT GPIO_BC_ACOK_EC
+#define GPIO_EC_INT_L GPIO_EC_PCH_MKBP_INT_ODL_EC
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW_EC
+#define GPIO_LID_OPEN GPIO_SMC_LID
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE_EC
+#define GPIO_PCH_WAKE_L GPIO_PCH_WAKE_N
+#define GPIO_PCH_PWRBTN_L GPIO_PM_PWRBTN_N_EC
+#define GPIO_PCH_RSMRST_L GPIO_PM_RSMRST_EC
+#define GPIO_PCH_SLP_S0_L GPIO_PCH_SLP_S0_N
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_R_L
+#define GPIO_PG_EC_DSW_PWROK GPIO_VCCPDSW_3P3_EC
+#define GPIO_POWER_BUTTON_L GPIO_MECH_PWR_BTN_ODL
+#define GPIO_CPU_PROCHOT GPIO_PROCHOT_EC
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL_EC
+#define GPIO_WP_L GPIO_EC_WP_ODL
+#define GPIO_VOLUME_UP_L GPIO_VOLUME_UP
+#define GPIO_VOLUME_DOWN_L GPIO_VOL_DN_EC_R
+#define GPIO_DC_JACK_PRESENT GPIO_STD_ADP_PRSNT
+#define GPIO_ESPI_RESET_L GPIO_ESPI_RST_R
+#define GPIO_UART1_RX GPIO_UART_SERVO_TX_EC_RX
+#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BAT_DET_EC
+#define GPIO_BAT_LED_RED_L GPIO_LED_1_L_EC
+#define GPIO_PWR_LED_WHITE_L GPIO_LED_2_L_EC
+#define GPIO_SLP_SUS_L GPIO_PM_SLP_SUS_EC
+#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_PWRGD_EC
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_ALL_SYS_PWRGD_EC
+#define GPIO_PCH_DSW_PWROK GPIO_DSW_PWROK_EC
+#define GPIO_EN_PP3300_A GPIO_EC_DS3
+#define GPIO_TABLET_MODE_L GPIO_SLATE_MODE_INDICATION
 
 /* I2C ports & Configs */
 #define CONFIG_IT83XX_SMCLK2_ON_GPC7
 
-#define I2C_PORT_CHARGER	IT83XX_I2C_CH_B
+#define I2C_PORT_CHARGER IT83XX_I2C_CH_B
 
 /* Battery */
-#define I2C_PORT_BATTERY	IT83XX_I2C_CH_B
+#define I2C_PORT_BATTERY IT83XX_I2C_CH_B
 
 /* Board ID */
-#define I2C_PORT_PCA9555_BOARD_ID_GPIO	IT83XX_I2C_CH_B
+#define I2C_PORT_PCA9555_BOARD_ID_GPIO IT83XX_I2C_CH_B
 
 /* Port 80 */
-#define I2C_PORT_PORT80		IT83XX_I2C_CH_B
+#define I2C_PORT_PORT80 IT83XX_I2C_CH_B
 
 /* USB-C I2C */
-#define I2C_PORT_TYPEC_0		IT83XX_I2C_CH_C
-#define I2C_PORT_TYPEC_1		IT83XX_I2C_CH_F
+#define I2C_PORT_TYPEC_0 IT83XX_I2C_CH_C
+#define I2C_PORT_TYPEC_1 IT83XX_I2C_CH_F
 #if defined(HAS_TASK_PD_C2)
-#define I2C_PORT_TYPEC_2		IT83XX_I2C_CH_E
-#define I2C_PORT_TYPEC_3		IT83XX_I2C_CH_D
+#define I2C_PORT_TYPEC_2 IT83XX_I2C_CH_E
+#define I2C_PORT_TYPEC_3 IT83XX_I2C_CH_D
 #endif
 
 /* TCPC */
@@ -76,12 +76,12 @@
 #define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1
 
 /* Config Fan */
-#define GPIO_FAN_POWER_EN	GPIO_EC_THRM_SEN_PWRGATE_N
-#define GPIO_ALL_SYS_PWRGD	GPIO_ALL_SYS_PWRGD_EC
+#define GPIO_FAN_POWER_EN GPIO_EC_THRM_SEN_PWRGATE_N
+#define GPIO_ALL_SYS_PWRGD GPIO_ALL_SYS_PWRGD_EC
 
 /* Increase EC speed */
 #undef PLL_CLOCK
-#define PLL_CLOCK	96000000
+#define PLL_CLOCK 96000000
 
 #ifndef __ASSEMBLER__
 
diff --git a/board/adlrvpp_ite/build.mk b/board/adlrvpp_ite/build.mk
index fe5f548324..9da9f60561 100644
--- a/board/adlrvpp_ite/build.mk
+++ b/board/adlrvpp_ite/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/adlrvpp_ite/ec.tasklist b/board/adlrvpp_ite/ec.tasklist
index c110617d6b..8bd63b1730 100644
--- a/board/adlrvpp_ite/ec.tasklist
+++ b/board/adlrvpp_ite/ec.tasklist
@@ -1,5 +1,5 @@
 /*
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/adlrvpp_ite/gpio.inc b/board/adlrvpp_ite/gpio.inc
index f7cb8ea19c..22b97a7eff 100644
--- a/board/adlrvpp_ite/gpio.inc
+++ b/board/adlrvpp_ite/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,10 +21,10 @@ GPIO_INT(PCH_SLP_S0_N,		PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
 GPIO_INT(VCCPDSW_3P3_EC,	PIN(I, 3), GPIO_INT_BOTH, power_signal_interrupt)
 GPIO_INT(VCCST_PWRGD,		PIN(I, 5), GPIO_INT_BOTH, power_signal_interrupt)
 GPIO_INT(PM_SLP_SUS_EC, 	PIN(K, 2), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_R_L,		PIN(F, 2), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 GPIO_INT(SLP_S4_R_L,		PIN(F, 3), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 
diff --git a/board/adlrvpp_mchp1521/board.c b/board/adlrvpp_mchp1521/board.c
index 7a51d0cbd9..a65a3ec60e 100644
--- a/board/adlrvpp_mchp1521/board.c
+++ b/board/adlrvpp_mchp1521/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -105,6 +105,6 @@ BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == CONFIG_USB_PD_PORT_MAX_COUNT);
 
 /* SPI devices */
 const struct spi_device_t spi_devices[] = {
-	{ QMSPI0_PORT, 4, GPIO_QMSPI_CS0},
+	{ QMSPI0_PORT, 4, GPIO_QMSPI_CS0 },
 };
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
diff --git a/board/adlrvpp_mchp1521/board.h b/board/adlrvpp_mchp1521/board.h
index a76fbd87df..bcd46acf25 100644
--- a/board/adlrvpp_mchp1521/board.h
+++ b/board/adlrvpp_mchp1521/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,6 +17,14 @@
 
 #include "adlrvp.h"
 
+#undef CONFIG_CMD_ADC
+#undef CONFIG_CMD_APTHROTTLE
+#undef CONFIG_CMD_BATTFAKE
+#undef CONFIG_CMD_GETTIME
+
+/* Enable LTO */
+#define CONFIG_LTO
+
 /*
  * Macros for GPIO signals used in common code that don't match the
  * schematic names. Signal names in gpio.inc match the schematic and are
@@ -24,77 +32,76 @@
  * which purpose.
  */
 /* Power sequencing */
-#define GPIO_EC_SPI_OE_N		GPIO_EC_PCH_SPI_OE_N
-#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_ALL_SYS_PWRGD
-#define GPIO_PG_EC_RSMRST_ODL		GPIO_RSMRST_PWRGD_EC_N
-#define GPIO_PCH_SLP_S0_L		GPIO_PM_SLP_S0_R_N
-#define GPIO_PG_EC_DSW_PWROK		GPIO_EC_TRACE_DATA_2
-#define GPIO_VCCST_PWRGD		GPIO_EC_TRACE_DATA_3
-#define GPIO_SLP_SUS_L			GPIO_PM_SLP_SUS_N
-#define GPIO_SYS_RESET_L		GPIO_DG2_PRESENT
-#define GPIO_PCH_RSMRST_L		GPIO_PM_RSMRST_R
-#define GPIO_PCH_PWRBTN_L		GPIO_PM_PWRBTN_N_R
-#define GPIO_EN_PP3300_A		GPIO_EC_DS3_R
-#define GPIO_SYS_PWROK_EC		GPIO_SYS_PWROK_EC_R
-#define GPIO_PCH_DSW_PWROK		GPIO_EC_TRACE_DATA_1
+#define GPIO_EC_SPI_OE_N GPIO_EC_PCH_SPI_OE_N
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_ALL_SYS_PWRGD
+#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_PWRGD_EC_N
+#define GPIO_PCH_SLP_S0_L GPIO_PM_SLP_S0_R_N
+#define GPIO_PG_EC_DSW_PWROK GPIO_EC_TRACE_DATA_2
+#define GPIO_VCCST_PWRGD GPIO_EC_TRACE_DATA_3
+#define GPIO_SLP_SUS_L GPIO_PM_SLP_SUS_N
+#define GPIO_SYS_RESET_L GPIO_DG2_PRESENT
+#define GPIO_PCH_RSMRST_L GPIO_PM_RSMRST_R
+#define GPIO_PCH_PWRBTN_L GPIO_PM_PWRBTN_N_R
+#define GPIO_EN_PP3300_A GPIO_EC_DS3_R
+#define GPIO_SYS_PWROK_EC GPIO_SYS_PWROK_EC_R
+#define GPIO_PCH_DSW_PWROK GPIO_EC_TRACE_DATA_1
 
 /* Buttons */
-#define GPIO_LID_OPEN			GPIO_SMC_LID
-#define GPIO_VOLUME_UP_L		GPIO_VOL_UP_EC
-#define GPIO_VOLUME_DOWN_L		GPIO_VOL_DOWN_EC
-#define GPIO_POWER_BUTTON_L		GPIO_PWRBTN_EC_IN_N
+#define GPIO_LID_OPEN GPIO_SMC_LID
+#define GPIO_VOLUME_UP_L GPIO_VOL_UP_EC
+#define GPIO_VOLUME_DOWN_L GPIO_VOL_DOWN_EC
+#define GPIO_POWER_BUTTON_L GPIO_PWRBTN_EC_IN_N
 
 /* Sensors */
-#define GPIO_TABLET_MODE_L		GPIO_EC_SLATEMODE_HALLOUT_SNSR_R
-#define GPIO_CPU_PROCHOT		GPIO_PROCHOT_EC_R
+#define GPIO_TABLET_MODE_L GPIO_EC_SLATEMODE_HALLOUT_SNSR_R
+#define GPIO_CPU_PROCHOT GPIO_PROCHOT_EC_R
 
 /* AC & Battery */
-#define GPIO_DC_JACK_PRESENT		GPIO_STD_ADP_PRSNT_EC
-#define GPIO_AC_PRESENT			GPIO_BC_ACOK_EC_IN
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_BATT_ID_R
+#define GPIO_DC_JACK_PRESENT GPIO_STD_ADP_PRSNT_EC
+#define GPIO_AC_PRESENT GPIO_BC_ACOK_EC_IN
+#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BATT_ID_R
 
 /* eSPI/Host communication */
-#define GPIO_ESPI_RESET_L		GPIO_ESPI_RST_EC_R_N
-#define GPIO_PCH_WAKE_L			GPIO_SMC_WAKE_SCI_N
-#define GPIO_EC_INT_L			GPIO_EC_TRACE_DATA_0
+#define GPIO_ESPI_RESET_L GPIO_ESPI_RST_EC_R_N
+#define GPIO_PCH_WAKE_L GPIO_SMC_WAKE_SCI_N
+#define GPIO_EC_INT_L GPIO_EC_TRACE_DATA_0
 
 /* H1 */
-#define GPIO_WP_L			GPIO_EC_WAKE_CLK_R
-#define GPIO_PACKET_MODE_EN		GPIO_EC_TRACE_CLK
-#define GPIO_ENTERING_RW		GPIO_DNX_FORCE_RELOAD_EC_R
+#define GPIO_WP_L GPIO_EC_WAKE_CLK_R
+#define GPIO_PACKET_MODE_EN GPIO_EC_TRACE_CLK
+#define GPIO_ENTERING_RW GPIO_DNX_FORCE_RELOAD_EC_R
 
 /* FAN */
-#define GPIO_FAN_POWER_EN		GPIO_FAN_PWR_DISABLE
+#define GPIO_FAN_POWER_EN GPIO_FAN_PWR_DISABLE
 
 /* LEDs */
-#define GPIO_BAT_LED_RED_L		GPIO_PM_BAT_STATUS_LED2
-#define GPIO_PWR_LED_WHITE_L		GPIO_PM_PWRBTN_LED
+#define GPIO_BAT_LED_RED_L GPIO_PM_BAT_STATUS_LED2
+#define GPIO_PWR_LED_WHITE_L GPIO_PM_PWRBTN_LED
 
 /* Uart */
-#define GPIO_UART2_RX			GPIO_EC_UART_RX
+#define GPIO_UART2_RX GPIO_EC_UART_RX
 
 /* Case Closed Debug Mode interrupt */
-#define GPIO_CCD_MODE_ODL		GPIO_KBC_NUMLOCK
+#define GPIO_CCD_MODE_ODL GPIO_KBC_NUMLOCK
 
 /* USB-C interrupts */
-#define GPIO_USBC_TCPC_ALRT_P0		GPIO_TYPEC_EC_SMBUS_ALERT_0_R
-#define GPIO_USBC_TCPC_ALRT_P1		GPIO_TYPEC_EC_SMBUS_ALERT_1_R
-#define GPIO_USBC_TCPC_PPC_ALRT_P0	GPIO_KBC_SCANOUT_15
-#define GPIO_USBC_TCPC_PPC_ALRT_P1	GPIO_KBC_CAPSLOCK
-
+#define GPIO_USBC_TCPC_ALRT_P0 GPIO_TYPEC_EC_SMBUS_ALERT_0_R
+#define GPIO_USBC_TCPC_ALRT_P1 GPIO_TYPEC_EC_SMBUS_ALERT_1_R
+#define GPIO_USBC_TCPC_PPC_ALRT_P0 GPIO_KBC_SCANOUT_15
+#define GPIO_USBC_TCPC_PPC_ALRT_P1 GPIO_KBC_CAPSLOCK
 
 /* I2C ports & Configs */
 /* Charger */
-#define I2C_PORT_CHARGER		MCHP_I2C_PORT0
+#define I2C_PORT_CHARGER MCHP_I2C_PORT0
 /* Port 80 */
-#define I2C_PORT_PORT80			MCHP_I2C_PORT0
+#define I2C_PORT_PORT80 MCHP_I2C_PORT0
 /* Board ID */
-#define I2C_PORT_PCA9555_BOARD_ID_GPIO	MCHP_I2C_PORT0
+#define I2C_PORT_PCA9555_BOARD_ID_GPIO MCHP_I2C_PORT0
 /* Battery */
-#define I2C_PORT_BATTERY		MCHP_I2C_PORT0
+#define I2C_PORT_BATTERY MCHP_I2C_PORT0
 /* USB-C I2C */
-#define I2C_PORT_TYPEC_0		MCHP_I2C_PORT1
-#define I2C_PORT_TYPEC_1		MCHP_I2C_PORT5
+#define I2C_PORT_TYPEC_0 MCHP_I2C_PORT1
+#define I2C_PORT_TYPEC_1 MCHP_I2C_PORT5
 
 /*
  * MEC1521H loads firmware using QMSPI controller
@@ -109,8 +116,8 @@
  * is of size 512KB. This bin is then later appended with 0xFF to become 32MB
  * binary for flashing purpose.
  */
-#define CONFIG_FLASH_SIZE_BYTES	(512 * 1024)
-#define CONFIG_SPI_FLASH_W25X40	/* TODO: change to W25R256 */
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
+#define CONFIG_SPI_FLASH_W25X40 /* TODO: change to W25R256 */
 
 /* ADC channels */
 /*
@@ -122,10 +129,10 @@
 #undef ADC_TEMP_SNS_DDR_CHANNEL
 #undef ADC_TEMP_SNS_SKIN_CHANNEL
 
-#define ADC_TEMP_SNS_AMBIENT_CHANNEL	CHIP_ADC_CH4
-#define ADC_TEMP_SNS_VR_CHANNEL		CHIP_ADC_CH5
-#define ADC_TEMP_SNS_DDR_CHANNEL	CHIP_ADC_CH6
-#define ADC_TEMP_SNS_SKIN_CHANNEL	CHIP_ADC_CH7
+#define ADC_TEMP_SNS_AMBIENT_CHANNEL CHIP_ADC_CH4
+#define ADC_TEMP_SNS_VR_CHANNEL CHIP_ADC_CH5
+#define ADC_TEMP_SNS_DDR_CHANNEL CHIP_ADC_CH6
+#define ADC_TEMP_SNS_SKIN_CHANNEL CHIP_ADC_CH7
 
 /* To do: Remove once fan register details are added in mchp/fan.c */
 #undef CONFIG_FANS
diff --git a/board/adlrvpp_mchp1521/build.mk b/board/adlrvpp_mchp1521/build.mk
index b53a3bb479..5bc76c4429 100644
--- a/board/adlrvpp_mchp1521/build.mk
+++ b/board/adlrvpp_mchp1521/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/adlrvpp_mchp1521/ec.tasklist b/board/adlrvpp_mchp1521/ec.tasklist
index 6d30fe3312..0019755448 100644
--- a/board/adlrvpp_mchp1521/ec.tasklist
+++ b/board/adlrvpp_mchp1521/ec.tasklist
@@ -1,5 +1,5 @@
 /*
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/adlrvpp_mchp1521/gpio.inc b/board/adlrvpp_mchp1521/gpio.inc
index ce6d2de65f..848253fa17 100644
--- a/board/adlrvpp_mchp1521/gpio.inc
+++ b/board/adlrvpp_mchp1521/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/adlrvpp_mchp1727/board.c b/board/adlrvpp_mchp1727/board.c
index 5d850c8e10..46092b91e3 100644
--- a/board/adlrvpp_mchp1727/board.c
+++ b/board/adlrvpp_mchp1727/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -133,6 +133,6 @@ BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == CONFIG_USB_PD_PORT_MAX_COUNT);
 
 /* SPI devices */
 const struct spi_device_t spi_devices[] = {
-	{ QMSPI0_PORT, 4, GPIO_QMSPI_CS0},
+	{ QMSPI0_PORT, 4, GPIO_QMSPI_CS0 },
 };
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
diff --git a/board/adlrvpp_mchp1727/board.h b/board/adlrvpp_mchp1727/board.h
index d806c92314..ad4d189b42 100644
--- a/board/adlrvpp_mchp1727/board.h
+++ b/board/adlrvpp_mchp1727/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -32,7 +32,7 @@
  *   #undef CONFIG_CLOCK_SRC_EXTERNAL
  *   CONFIG_CLOCK_CRYSTAL is a don't care
  */
-#undef	CONFIG_CLOCK_SRC_EXTERNAL
+#undef CONFIG_CLOCK_SRC_EXTERNAL
 
 /* MEC1727 integrated SPI chip 512KB SST25PF040C */
 #define CONFIG_SPI_FLASH_W25X40
@@ -52,10 +52,10 @@
 #undef ADC_TEMP_SNS_DDR_CHANNEL
 #undef ADC_TEMP_SNS_SKIN_CHANNEL
 #undef ADC_TEMP_SNS_VR_CHANNEL
-#define ADC_TEMP_SNS_AMBIENT_CHANNEL	CHIP_ADC_CH3
-#define ADC_TEMP_SNS_DDR_CHANNEL	CHIP_ADC_CH5
-#define ADC_TEMP_SNS_SKIN_CHANNEL	CHIP_ADC_CH4
-#define ADC_TEMP_SNS_VR_CHANNEL		CHIP_ADC_CH0
+#define ADC_TEMP_SNS_AMBIENT_CHANNEL CHIP_ADC_CH3
+#define ADC_TEMP_SNS_DDR_CHANNEL CHIP_ADC_CH5
+#define ADC_TEMP_SNS_SKIN_CHANNEL CHIP_ADC_CH4
+#define ADC_TEMP_SNS_VR_CHANNEL CHIP_ADC_CH0
 
 /*
  * ADC maximum voltage is a board level configuration.
@@ -74,73 +74,73 @@
  * which purpose.
  */
 /* Power sequencing */
-#define GPIO_EC_SPI_OE_N		GPIO_EC_SPI_OE_MECC
-#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_ALL_SYS_PWRGD
-#define GPIO_PG_EC_RSMRST_ODL		GPIO_RSMRST_PWRGD
-#define GPIO_PCH_SLP_S0_L		GPIO_PCH_SLP_S0_N
-#define GPIO_PG_EC_DSW_PWROK		GPIO_VCCPDSW_3P3
-#define GPIO_SLP_SUS_L			GPIO_PM_SLP_SUS_EC_N
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_PM_RSMRST_N
-#define GPIO_PCH_PWRBTN_L		GPIO_PM_PWRBTN_N
-#define GPIO_EN_PP3300_A		GPIO_EC_DS3
-#define GPIO_SYS_PWROK_EC		GPIO_SYS_PWROK
-#define GPIO_PCH_DSW_PWROK		GPIO_EC_DSW_PWROK
+#define GPIO_EC_SPI_OE_N GPIO_EC_SPI_OE_MECC
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_ALL_SYS_PWRGD
+#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_PWRGD
+#define GPIO_PCH_SLP_S0_L GPIO_PCH_SLP_S0_N
+#define GPIO_PG_EC_DSW_PWROK GPIO_VCCPDSW_3P3
+#define GPIO_SLP_SUS_L GPIO_PM_SLP_SUS_EC_N
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_PCH_RSMRST_L GPIO_PM_RSMRST_N
+#define GPIO_PCH_PWRBTN_L GPIO_PM_PWRBTN_N
+#define GPIO_EN_PP3300_A GPIO_EC_DS3
+#define GPIO_SYS_PWROK_EC GPIO_SYS_PWROK
+#define GPIO_PCH_DSW_PWROK GPIO_EC_DSW_PWROK
 
 /* Sensors */
-#define GPIO_TABLET_MODE_L		GPIO_SLATE_MODE_INDICATION
-#define GPIO_CPU_PROCHOT		GPIO_PROCHOT_EC_N
+#define GPIO_TABLET_MODE_L GPIO_SLATE_MODE_INDICATION
+#define GPIO_CPU_PROCHOT GPIO_PROCHOT_EC_N
 
 /* Buttons */
-#define GPIO_LID_OPEN			GPIO_SMC_LID
-#define GPIO_VOLUME_UP_L		GPIO_VOLUME_UP
-#define GPIO_VOLUME_DOWN_L		GPIO_VOL_DN_EC
-#define GPIO_POWER_BUTTON_L		GPIO_MECH_PWR_BTN_ODL
+#define GPIO_LID_OPEN GPIO_SMC_LID
+#define GPIO_VOLUME_UP_L GPIO_VOLUME_UP
+#define GPIO_VOLUME_DOWN_L GPIO_VOL_DN_EC
+#define GPIO_POWER_BUTTON_L GPIO_MECH_PWR_BTN_ODL
 
 /* H1 */
-#define GPIO_WP_L			GPIO_EC_FLASH_WP_ODL
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
+#define GPIO_WP_L GPIO_EC_FLASH_WP_ODL
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
 
 /* AC & Battery */
-#define GPIO_DC_JACK_PRESENT		GPIO_STD_ADP_PRSNT
-#define GPIO_AC_PRESENT			GPIO_BC_ACOK
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_BAT_DET
+#define GPIO_DC_JACK_PRESENT GPIO_STD_ADP_PRSNT
+#define GPIO_AC_PRESENT GPIO_BC_ACOK
+#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BAT_DET
 
 /* eSPI/Host communication */
-#define GPIO_ESPI_RESET_L		GPIO_LPC_ESPI_RST_N
-#define GPIO_PCH_WAKE_L			GPIO_SMC_WAKE_SCI_N_MECC
-#define GPIO_EC_INT_L			GPIO_EC_PCH_MKBP_INT_ODL
+#define GPIO_ESPI_RESET_L GPIO_LPC_ESPI_RST_N
+#define GPIO_PCH_WAKE_L GPIO_SMC_WAKE_SCI_N_MECC
+#define GPIO_EC_INT_L GPIO_EC_PCH_MKBP_INT_ODL
 
 /* LED */
-#define GPIO_BAT_LED_RED_L		GPIO_LED_1_L
-#define GPIO_PWR_LED_WHITE_L		GPIO_LED_2_L
+#define GPIO_BAT_LED_RED_L GPIO_LED_1_L
+#define GPIO_PWR_LED_WHITE_L GPIO_LED_2_L
 
 /* FAN */
-#define GPIO_FAN_POWER_EN		GPIO_THERM_SEN_MECC
+#define GPIO_FAN_POWER_EN GPIO_THERM_SEN_MECC
 
 /* Charger */
-#define I2C_PORT_CHARGER	MCHP_I2C_PORT0
+#define I2C_PORT_CHARGER MCHP_I2C_PORT0
 
 /* Battery */
-#define I2C_PORT_BATTERY	MCHP_I2C_PORT0
+#define I2C_PORT_BATTERY MCHP_I2C_PORT0
 
 /* Board ID */
-#define I2C_PORT_PCA9555_BOARD_ID_GPIO	MCHP_I2C_PORT0
+#define I2C_PORT_PCA9555_BOARD_ID_GPIO MCHP_I2C_PORT0
 
 /* Port 80 */
-#define I2C_PORT_PORT80		MCHP_I2C_PORT0
+#define I2C_PORT_PORT80 MCHP_I2C_PORT0
 
 /* USB-C I2C */
-#define I2C_PORT_TYPEC_0	MCHP_I2C_PORT6
+#define I2C_PORT_TYPEC_0 MCHP_I2C_PORT6
 /*
  * Note: I2C for Type-C Port-1 is swapped with Type-C Port-2
  *       on the RVP to reduce BOM stuffing options.
  */
-#define I2C_PORT_TYPEC_1	MCHP_I2C_PORT3
+#define I2C_PORT_TYPEC_1 MCHP_I2C_PORT3
 #if defined(HAS_TASK_PD_C2)
-#define I2C_PORT_TYPEC_2	MCHP_I2C_PORT7
-#define I2C_PORT_TYPEC_3	MCHP_I2C_PORT2
+#define I2C_PORT_TYPEC_2 MCHP_I2C_PORT7
+#define I2C_PORT_TYPEC_3 MCHP_I2C_PORT2
 #endif
 
 #ifndef __ASSEMBLER__
diff --git a/board/adlrvpp_mchp1727/build.mk b/board/adlrvpp_mchp1727/build.mk
index 2a056943d4..0527f50d24 100644
--- a/board/adlrvpp_mchp1727/build.mk
+++ b/board/adlrvpp_mchp1727/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/adlrvpp_mchp1727/ec.tasklist b/board/adlrvpp_mchp1727/ec.tasklist
index 8c3776ccad..3ae4784397 100644
--- a/board/adlrvpp_mchp1727/ec.tasklist
+++ b/board/adlrvpp_mchp1727/ec.tasklist
@@ -1,5 +1,5 @@
 /*
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/adlrvpp_mchp1727/gpio.inc b/board/adlrvpp_mchp1727/gpio.inc
index 42973648b4..582da4c46a 100644
--- a/board/adlrvpp_mchp1727/gpio.inc
+++ b/board/adlrvpp_mchp1727/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,12 +18,12 @@ GPIO_INT(PCH_SLP_S0_N,		PIN(0243), GPIO_INT_BOTH, power_signal_interrupt)
 GPIO_INT(VCCPDSW_3P3,		PIN(0201), GPIO_INT_BOTH, power_signal_interrupt)
 /* TODO: GPIO_INT(VCCST_PWRGD_MECC,	PIN(0207), GPIO_INT_BOTH, power_signal_interrupt) */
 GPIO_INT(PM_SLP_SUS_EC_N, 	PIN(0227), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(PM_SLP_S3_N,		PIN(0161), GPIO_INT_BOTH, power_signal_interrupt)
 #else
 GPIO(PM_SLP_S3_N,		PIN(0161), GPIO_INPUT)
 #endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 GPIO_INT(PM_SLP_S4_N,		PIN(0162), GPIO_INT_BOTH, power_signal_interrupt)
 #else
 GPIO(PM_SLP_S4_N,		PIN(0162), GPIO_INPUT)
diff --git a/board/adlrvpp_npcx/board.c b/board/adlrvpp_npcx/board.c
index 412cebdb9a..f0b2a4408d 100644
--- a/board/adlrvpp_npcx/board.c
+++ b/board/adlrvpp_npcx/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/adlrvpp_npcx/board.h b/board/adlrvpp_npcx/board.h
index c787beea84..ff214ddec2 100644
--- a/board/adlrvpp_npcx/board.h
+++ b/board/adlrvpp_npcx/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,76 +20,76 @@
  * which purpose.
  */
 /* Power sequencing */
-#define GPIO_EC_SPI_OE_N		GPIO_EC_SPI_OE_MECC
-#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_ALL_SYS_PWRGD
-#define GPIO_PG_EC_RSMRST_ODL		GPIO_RSMRST_PWRGD
-#define GPIO_PCH_SLP_S0_L		GPIO_PCH_SLP_S0_N
-#define GPIO_PG_EC_DSW_PWROK		GPIO_VCCPDSW_3P3
-#define GPIO_SLP_SUS_L			GPIO_PM_SLP_SUS_EC_N
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_PM_RSMRST_N
-#define GPIO_PCH_PWRBTN_L		GPIO_PM_PWRBTN_N
-#define GPIO_EN_PP3300_A		GPIO_EC_DS3
-#define GPIO_SYS_PWROK_EC		GPIO_SYS_PWROK
-#define GPIO_PCH_DSW_PWROK		GPIO_EC_DSW_PWROK
+#define GPIO_EC_SPI_OE_N GPIO_EC_SPI_OE_MECC
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_ALL_SYS_PWRGD
+#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_PWRGD
+#define GPIO_PCH_SLP_S0_L GPIO_PCH_SLP_S0_N
+#define GPIO_PG_EC_DSW_PWROK GPIO_VCCPDSW_3P3
+#define GPIO_SLP_SUS_L GPIO_PM_SLP_SUS_EC_N
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_PCH_RSMRST_L GPIO_PM_RSMRST_N
+#define GPIO_PCH_PWRBTN_L GPIO_PM_PWRBTN_N
+#define GPIO_EN_PP3300_A GPIO_EC_DS3
+#define GPIO_SYS_PWROK_EC GPIO_SYS_PWROK
+#define GPIO_PCH_DSW_PWROK GPIO_EC_DSW_PWROK
 
 /* Sensors */
-#define GPIO_TABLET_MODE_L		GPIO_SLATE_MODE_INDICATION
-#define GPIO_CPU_PROCHOT		GPIO_PROCHOT_EC_N
+#define GPIO_TABLET_MODE_L GPIO_SLATE_MODE_INDICATION
+#define GPIO_CPU_PROCHOT GPIO_PROCHOT_EC_N
 
 /* Buttons */
-#define GPIO_LID_OPEN			GPIO_SMC_LID
-#define GPIO_VOLUME_UP_L		GPIO_VOLUME_UP
-#define GPIO_VOLUME_DOWN_L		GPIO_VOL_DN_EC
-#define GPIO_POWER_BUTTON_L		GPIO_MECH_PWR_BTN_ODL
+#define GPIO_LID_OPEN GPIO_SMC_LID
+#define GPIO_VOLUME_UP_L GPIO_VOLUME_UP
+#define GPIO_VOLUME_DOWN_L GPIO_VOL_DN_EC
+#define GPIO_POWER_BUTTON_L GPIO_MECH_PWR_BTN_ODL
 
 /* H1 */
-#define GPIO_WP_L			GPIO_EC_FLASH_WP_ODL
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
+#define GPIO_WP_L GPIO_EC_FLASH_WP_ODL
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
 
 /* AC & Battery */
-#define GPIO_DC_JACK_PRESENT		GPIO_STD_ADP_PRSNT
-#define GPIO_AC_PRESENT			GPIO_BC_ACOK
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_BAT_DET
+#define GPIO_DC_JACK_PRESENT GPIO_STD_ADP_PRSNT
+#define GPIO_AC_PRESENT GPIO_BC_ACOK
+#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BAT_DET
 
 /* eSPI/Host communication */
-#define GPIO_ESPI_RESET_L		GPIO_LPC_ESPI_RST_N
-#define GPIO_PCH_WAKE_L			GPIO_SMC_WAKE_SCI_N_MECC
-#define GPIO_EC_INT_L			GPIO_EC_PCH_MKBP_INT_ODL
+#define GPIO_ESPI_RESET_L GPIO_LPC_ESPI_RST_N
+#define GPIO_PCH_WAKE_L GPIO_SMC_WAKE_SCI_N_MECC
+#define GPIO_EC_INT_L GPIO_EC_PCH_MKBP_INT_ODL
 
 /* LED */
-#define GPIO_BAT_LED_RED_L		GPIO_LED_1_L
-#define GPIO_PWR_LED_WHITE_L		GPIO_LED_2_L
+#define GPIO_BAT_LED_RED_L GPIO_LED_1_L
+#define GPIO_PWR_LED_WHITE_L GPIO_LED_2_L
 
 /* FAN */
-#define GPIO_FAN_POWER_EN		GPIO_THERM_SEN_MECC
+#define GPIO_FAN_POWER_EN GPIO_THERM_SEN_MECC
 
 /* I2C ports & Configs */
 /* Charger */
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT7_0
+#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0
 
 /* Battery */
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT7_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT7_0
 
 /* Board ID */
-#define I2C_PORT_PCA9555_BOARD_ID_GPIO	NPCX_I2C_PORT7_0
+#define I2C_PORT_PCA9555_BOARD_ID_GPIO NPCX_I2C_PORT7_0
 
 /* Port 80 */
-#define I2C_PORT_PORT80		NPCX_I2C_PORT7_0
+#define I2C_PORT_PORT80 NPCX_I2C_PORT7_0
 
 /* USB-C I2C */
-#define I2C_PORT_TYPEC_0	NPCX_I2C_PORT0_0
+#define I2C_PORT_TYPEC_0 NPCX_I2C_PORT0_0
 /*
  * Note: I2C for Type-C Port-1 is swapped with Type-C Port-2
  *       on the RVP to reduce BOM stuffing options.
  */
-#define I2C_PORT_TYPEC_1	NPCX_I2C_PORT2_0
+#define I2C_PORT_TYPEC_1 NPCX_I2C_PORT2_0
 #if defined(HAS_TASK_PD_C2)
-#define I2C_PORT_TYPEC_2	NPCX_I2C_PORT1_0
+#define I2C_PORT_TYPEC_2 NPCX_I2C_PORT1_0
 #endif
 #if defined(HAS_TASK_PD_C3)
-#define I2C_PORT_TYPEC_3	NPCX_I2C_PORT3_0
+#define I2C_PORT_TYPEC_3 NPCX_I2C_PORT3_0
 #endif
 
 #ifndef __ASSEMBLER__
diff --git a/board/adlrvpp_npcx/build.mk b/board/adlrvpp_npcx/build.mk
index ec3450ee7e..db43110a34 100644
--- a/board/adlrvpp_npcx/build.mk
+++ b/board/adlrvpp_npcx/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/adlrvpp_npcx/ec.tasklist b/board/adlrvpp_npcx/ec.tasklist
index 08521ac10e..df3dc2c67d 100644
--- a/board/adlrvpp_npcx/ec.tasklist
+++ b/board/adlrvpp_npcx/ec.tasklist
@@ -1,5 +1,5 @@
 /*
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/adlrvpp_npcx/gpio.inc b/board/adlrvpp_npcx/gpio.inc
index 4a696e4c09..ebc04045bf 100644
--- a/board/adlrvpp_npcx/gpio.inc
+++ b/board/adlrvpp_npcx/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,12 +16,12 @@ GPIO_INT(PCH_SLP_S0_N,		PIN(A, 1), GPIO_INT_BOTH, power_signal_interrupt)
 GPIO_INT(VCCPDSW_3P3,		PIN(4, 5), GPIO_INT_BOTH, power_signal_interrupt)
 /* TODO: GPIO_INT(VCCST_PWRGD_MECC,	PIN(7, 1), GPIO_INT_BOTH, power_signal_interrupt) */
 GPIO_INT(PM_SLP_SUS_EC_N, 	PIN(8, 6), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(PM_SLP_S3_N,		PIN(B, 0), GPIO_INT_BOTH, power_signal_interrupt)
 #else
 GPIO(PM_SLP_S3_N,		PIN(B, 0), GPIO_INPUT)
 #endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 GPIO_INT(PM_SLP_S4_N,		PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #else
 GPIO(PM_SLP_S4_N,		PIN(A, 5), GPIO_INPUT)
diff --git a/board/agah/battery.c b/board/agah/battery.c
index b9adcb4db9..92e2ad4b07 100644
--- a/board/agah/battery.c
+++ b/board/agah/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/agah/board.c b/board/agah/board.c
index d1cc519402..c8c98621d3 100644
--- a/board/agah/board.c
+++ b/board/agah/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,19 +15,32 @@
 #include "hooks.h"
 #include "fw_config.h"
 #include "hooks.h"
+#include "keyboard_scan.h"
 #include "lid_switch.h"
 #include "power_button.h"
 #include "power.h"
 #include "registers.h"
 #include "switch.h"
+#include "system.h"
 #include "throttle_ap.h"
 #include "usbc_config.h"
+#include "util.h"
+
+#include "driver/nvidia_gpu.h"
 
 #include "gpio_list.h" /* Must come after other header files. */
 
 /* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+
+static int block_sequence;
+
+struct d_notify_policy d_notify_policies[] = {
+	AC_ATLEAST_W(100),  AC_ATLEAST_W(65),  AC_DC,
+	DC_ATLEAST_SOC(20), DC_ATLEAST_SOC(5),
+};
+BUILD_ASSERT(ARRAY_SIZE(d_notify_policies) == D_NOTIFY_COUNT);
 
 __override void board_cbi_init(void)
 {
@@ -51,8 +64,15 @@ DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
 
 static void board_init(void)
 {
+	if ((system_get_reset_flags() & EC_RESET_FLAG_AP_OFF) ||
+	    (keyboard_scan_get_boot_keys() & BOOT_KEY_DOWN_ARROW)) {
+		CPRINTS("PG_PP3300_S5_OD block is enabled");
+		block_sequence = 1;
+	}
 	gpio_enable_interrupt(GPIO_PG_PP3300_S5_OD);
 	gpio_enable_interrupt(GPIO_BJ_ADP_PRESENT_ODL);
+
+	nvidia_gpu_init_policy(d_notify_policies);
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
@@ -61,9 +81,13 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
  */
 static void bypass_pp3300_s5_deferred(void)
 {
-	int pg_pp3300_s5 = gpio_get_level(GPIO_PG_PP3300_S5_OD);
+	if (block_sequence) {
+		CPRINTS("PG_PP3300_S5_OD is blocked.");
+		return;
+	}
 
-	gpio_set_level(GPIO_PG_PP3300_S5_EC_SEQ_OD, pg_pp3300_s5);
+	gpio_set_level(GPIO_PG_PP3300_S5_EC_SEQ_OD,
+		       gpio_get_level(GPIO_PG_PP3300_S5_OD));
 }
 DECLARE_DEFERRED(bypass_pp3300_s5_deferred);
 
@@ -72,3 +96,23 @@ void board_power_interrupt(enum gpio_signal signal)
 	/* Trigger deferred notification of gpio PG_PP3300_S5_OD change */
 	hook_call_deferred(&bypass_pp3300_s5_deferred_data, 0);
 }
+
+static int cc_blockseq(int argc, const char *argv[])
+{
+	if (argc > 1) {
+		if (!parse_bool(argv[1], &block_sequence)) {
+			ccprintf("Invalid argument: %s\n", argv[1]);
+			return EC_ERROR_INVAL;
+		}
+	}
+
+	ccprintf("PG_PP3300_S5_OD block is %s\n",
+		 block_sequence ? "enabled" : "disabled");
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(blockseq, cc_blockseq, "[on/off]", NULL);
+
+void gpu_overt_interrupt(enum gpio_signal signal)
+{
+	nvidia_gpu_over_temp(gpio_get_level(signal));
+}
diff --git a/board/agah/board.h b/board/agah/board.h
index 7655f9a4fe..0622e33df3 100644
--- a/board/agah/board.h
+++ b/board/agah/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,6 +14,11 @@
 #include "baseboard.h"
 
 /*
+ * Nvidia GPU
+ */
+#define CONFIG_GPU_NVIDIA
+
+/*
  * This will happen automatically on NPCX9 ES2 and later. Do not remove
  * until we can confirm all earlier chips are out of service.
  */
@@ -24,18 +29,6 @@
  */
 #undef CONFIG_CHIPSET_X86_RSMRST_AFTER_S5
 
-/* LED */
-#define CONFIG_LED_PWM
-#define CONFIG_LED_PWM_COUNT 1
-#undef CONFIG_LED_PWM_NEAR_FULL_COLOR
-#undef CONFIG_LED_PWM_SOC_ON_COLOR
-#undef CONFIG_LED_PWM_SOC_SUSPEND_COLOR
-#undef CONFIG_LED_PWM_LOW_BATT_COLOR
-#define CONFIG_LED_PWM_NEAR_FULL_COLOR EC_LED_COLOR_WHITE
-#define CONFIG_LED_PWM_SOC_ON_COLOR EC_LED_COLOR_WHITE
-#define CONFIG_LED_PWM_SOC_SUSPEND_COLOR EC_LED_COLOR_WHITE
-#define CONFIG_LED_PWM_LOW_BATT_COLOR EC_LED_COLOR_AMBER
-
 /* Sensors */
 #undef CONFIG_TABLET_MODE
 #undef CONFIG_TABLET_MODE_SWITCH
@@ -45,7 +38,7 @@
 #undef CONFIG_VOLUME_BUTTONS
 
 /* USB Type A Features */
-#define USB_PORT_COUNT			1
+#define USB_PORT_COUNT 1
 #define CONFIG_USB_PORT_POWER_DUMB
 
 /* USB Type C and USB PD defines */
@@ -61,18 +54,20 @@
 
 #define CONFIG_USBC_PPC_SYV682X
 #define CONFIG_USB_PD_FRS_PPC
+#undef CONFIG_SYV682X_HV_ILIM
+#define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_5_50
 
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
 
-/*
- * Passive USB-C cables only support up to 60W.
- */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 100000
+#define PD_MAX_CURRENT_MA 5000
+#define PD_MAX_VOLTAGE_MV 20000
+
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
+#define CONFIG_EXTPOWER_DEBOUNCE_MS 500
 
 /*
  * Macros for GPIO signals used in common code that don't match the
@@ -80,73 +75,77 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT		GPIO_EC_EN_EDP_BL
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_GSC_PACKET_MODE
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SYS_SLP_S0IX_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
 
 /*
  * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
  * signal.
  */
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_SEQ_EC_ALL_SYS_PG
-#define GPIO_PG_EC_DSW_PWROK		GPIO_SEQ_EC_DSW_PWROK
-#define GPIO_PG_EC_RSMRST_ODL		GPIO_SEQ_EC_RSMRST_ODL
-#define GPIO_POWER_BUTTON_L		GPIO_GSC_EC_PWR_BTN_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_ODL
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
 
 /* System has back-lit keyboard */
 #define CONFIG_PWM_KBLIGHT
 
 /* I2C Bus Configuration */
 
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
 
-#define I2C_PORT_USB_C0_TCPC	NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C2_TCPC	NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C0_TCPC NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C2_TCPC NPCX_I2C_PORT2_0
 
-#define I2C_PORT_USB_C0_PPC	NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C2_PPC	NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C0_PPC NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C2_PPC NPCX_I2C_PORT2_0
 
-#define I2C_PORT_USB_C0_BC12	NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C2_BC12	NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C0_BC12 NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C2_BC12 NPCX_I2C_PORT2_0
 
-#define I2C_PORT_USBA1_RT	NPCX_I2C_PORT6_1
+#define I2C_PORT_USBA1_RT NPCX_I2C_PORT6_1
 
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT5_0
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT7_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
 
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 
 /* Thermal features */
 #define CONFIG_THERMISTOR
 #define CONFIG_TEMP_SENSOR
-#define CONFIG_TEMP_SENSOR_POWER_GPIO	GPIO_SEQ_EC_DSW_PWROK
+#define CONFIG_TEMP_SENSOR_POWER
+#define CONFIG_TEMP_SENSOR_FIRST_READ_DELAY_MS 500
 #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
 
-#define CONFIG_FANS			FAN_CH_COUNT
+#define CONFIG_FANS FAN_CH_COUNT
 
 /* Charger defines */
 #define CONFIG_CHARGER_ISL9241
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+/* Round down 7700 max current to multiple of 128mA for ISL9241 AC prochot. */
+#define AGAH_AC_PROCHOT_CURRENT_MA 7680
 
 /* Barrel jack adapter settings */
-#undef  CONFIG_DEDICATED_CHARGE_PORT_COUNT
-#define CONFIG_DEDICATED_CHARGE_PORT_COUNT	1
+#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT
+#define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1
 /* This is the next available port # after USB-C ports. */
-#define DEDICATED_CHARGE_PORT			2
+#define DEDICATED_CHARGE_PORT 2
 
 /*
  * Older boards have a different ADC assignment.
@@ -156,23 +155,23 @@
 
 #ifndef __ASSEMBLER__
 
-#include "gpio_signal.h"	/* needed by registers.h */
+#include "gpio_signal.h" /* needed by registers.h */
 #include "registers.h"
 #include "usbc_config.h"
 
 enum adc_channel {
 	ADC_TEMP_SENSOR_1_DDR_SOC,
-	ADC_TEMP_SENSOR_2_AMBIENT,
+	ADC_TEMP_SENSOR_2_GPU,
 	ADC_TEMP_SENSOR_3_CHARGER,
-	ADC_TEMP_SENSOR_4_WWAN,
+	ADC_CHARGER_IADP,
+	ADC_ADP_TYP,
 	ADC_CH_COUNT
 };
 
 enum temp_sensor_id {
 	TEMP_SENSOR_1_DDR_SOC,
-	TEMP_SENSOR_2_AMBIENT,
+	TEMP_SENSOR_2_GPU,
 	TEMP_SENSOR_3_CHARGER,
-	TEMP_SENSOR_4_WWAN,
 	TEMP_SENSOR_COUNT
 };
 
@@ -183,25 +182,15 @@ enum battery_type {
 };
 
 enum pwm_channel {
-	PWM_CH_LED2 = 0,		/* PWM0 (white charger) */
-	PWM_CH_LED1,			/* PWM2 (orange charger) */
-	PWM_CH_KBLIGHT,			/* PWM3 */
-	PWM_CH_FAN,			/* PWM5 */
-	PWM_CH_FAN2,			/* PWM4 */
+	PWM_CH_KBLIGHT = 0, /* PWM3 */
+	PWM_CH_FAN, /* PWM5 */
+	PWM_CH_FAN2, /* PWM4 */
 	PWM_CH_COUNT
 };
 
-enum fan_channel {
-	FAN_CH_0 = 0,
-	FAN_CH_1,
-	FAN_CH_COUNT
-};
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_1, FAN_CH_COUNT };
 
-enum mft_channel {
-	MFT_CH_0 = 0,
-	MFT_CH_1,
-	MFT_CH_COUNT
-};
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_1, MFT_CH_COUNT };
 
 enum charge_port {
 	CHARGE_PORT_TYPEC0,
@@ -219,6 +208,9 @@ void board_power_interrupt(enum gpio_signal signal);
 /* IRQ for BJ plug/unplug. */
 void bj_present_interrupt(enum gpio_signal signal);
 
+/* IRQ for over temperature. */
+void gpu_overt_interrupt(enum gpio_signal signal);
+
 #endif /* !__ASSEMBLER__ */
 
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/agah/build.mk b/board/agah/build.mk
index fbdd503bc4..d2f2db68df 100644
--- a/board/agah/build.mk
+++ b/board/agah/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/agah/charger_isl9241.c b/board/agah/charger_isl9241.c
index 6f041a7455..47e8261f78 100644
--- a/board/agah/charger_isl9241.c
+++ b/board/agah/charger_isl9241.c
@@ -1,8 +1,38 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+/*
+ *
+ * We need to deal with plug / unplug of AC chargers:
+ *
+ *  +---------+    +USB     +---------+
+ *  | BATTERY |------------>| BATTERY |
+ *  |         |<------------|    +USB |
+ *  +---------+    -USB     +---------+
+ *      | ^                     | ^
+ *  +BJ | | -BJ             +BJ | | -BJ
+ *      v |                     v |
+ *  +---------+    +USB     +---------+
+ *  | BATTERY |------------>| BATTERY |
+ *  |     +BJ |<------------| +BJ+USB |
+ *  +---------+    -USB     +---------+
+ *
+ * Depending on available battery charge, power rating of the new charger, and
+ * the system power state, transition/throttling may or may not occur but
+ * switching chargers is handled as follows:
+ *
+ * 1. Detects a new charger or removal of an existing charger.
+ * 2. charge_manager_update_charge is called with new charger's info.
+ * 3. board_set_active_charge_port is called.
+ *    3.1 It triggers hard & soft throttling for AP & GPU.
+ *    3.2 It disable active port then enables the new port.
+ * 4. HOOK_POWER_SUPPLY_CHANGE is called. We disables hard throttling.
+ * 5. charger task wakes up on HOOK_POWER_SUPPLY_CHANGE, enables (or disables)
+ *    bypass mode.
+ */
+
 #include "common.h"
 
 #include "charge_manager.h"
@@ -15,12 +45,13 @@
 #include "gpio.h"
 #include "hooks.h"
 #include "stdbool.h"
+#include "throttle_ap.h"
 #include "usbc_ppc.h"
 #include "usb_pd.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 /* Charger Chip Configuration */
 const struct charger_config_t chg_chips[] = {
@@ -32,71 +63,42 @@ const struct charger_config_t chg_chips[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CHARGER_NUM);
 
-static int board_disable_bj_port(void)
+static int board_enable_bj_port(bool enable)
 {
-	gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 1);
-	/* If the current port is BJ, disable bypass mode. */
-	if (charge_manager_get_supplier() == CHARGE_SUPPLIER_DEDICATED)
-		return charger_enable_bypass_mode(0, 0);
+	if (enable) {
+		if (gpio_get_level(GPIO_BJ_ADP_PRESENT_ODL))
+			return EC_ERROR_INVAL;
+		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 0);
+	} else {
+		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 1);
+	}
 
-	CPRINTS("BJ power is disabled");
+	CPRINTS("BJ power is %sabled", enable ? "en" : "dis");
 
 	return EC_SUCCESS;
 }
 
-static int board_enable_bj_port(void)
-{
-	if (gpio_get_level(GPIO_BJ_ADP_PRESENT_ODL))
-		return EC_ERROR_INVAL;
-	gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 0);
-
-	CPRINTS("BJ power is enabled");
-
-	return charger_enable_bypass_mode(0, 1);
-}
-
-/*
- * TODO:
- *
- * When AC is being plugged in (including switching source port),
- *   1. Deassert NVIDIA_GPU_ACOFF_ODL.
- *   2. Call evaluate_d_notify.
- *
- * When AC is being lost,
- *   1. Assert NVIDIA_GPU_ACOFF_ODL.
- *   2. Set D-Notify to D5.
- *   3. Differ-call
- *      a. Deassert NVIDIA_GPU_ACOFF_ODL.
- *      b. evaluate_d_notify
- */
-static int board_throttle_ap_gpu(bool enable)
+static void board_throttle_ap_gpu(void)
 {
-	int rv = EC_SUCCESS;
-
-	if (!chipset_in_state(CHIPSET_STATE_ON))
-		return EC_SUCCESS;
-
-	CPRINTS("TODO: %s to %s AP & GPU (%d)", rv ? "Failed" : "Succeeded",
-		enable ? "throttle" : "unthrottle", rv);
-
-	return rv;
+	throttle_ap(THROTTLE_ON, THROTTLE_HARD, THROTTLE_SRC_AC);
+	throttle_gpu(THROTTLE_ON, THROTTLE_HARD, THROTTLE_SRC_AC);
 }
 
 /* Disable all VBUS sink ports except <port>. <port> = -1 disables all ports. */
-static int board_disable_vbus_sink(int port)
+static int board_disable_other_vbus_sink(int except_port)
 {
 	int i, r, rv = EC_SUCCESS;
 
 	for (i = 0; i < ppc_cnt; i++) {
-		if (i == port)
+		if (i == except_port)
 			continue;
 		/*
 		 * Do not return early if one fails otherwise we can get into a
 		 * boot loop assertion failure.
 		 */
 		r = ppc_vbus_sink_enable(i, 0);
-		CPRINTS("%s to disable sink path C%d (%d).",
-			r ? "Failed" : "Succeeded", i,  r);
+		if (r)
+			CPRINTS("Failed to disable sink path C%d (%d)", i, r);
 		rv |= r;
 	}
 
@@ -104,77 +106,74 @@ static int board_disable_vbus_sink(int port)
 }
 
 /* Minimum battery SoC required for switching source port. */
-#define MIN_BATT_FOR_SWITCHING_SOURCE_PORT	1
+#define MIN_BATT_FOR_SWITCHING_SOURCE_PORT 1
 
 /*
- * It should also work on POR with/without a battery:
- *
- * 1. EC gathers power info of all ports.
- * 2. Identify the highest power port.
- * 3. If
- *    1. battery soc = 0% --> Exit
- *    2. BJ_ADP_PRESENT_ODL = 1 --> Exit
- *    3. highest power port == active port --> Exit
- * 4. If
- *    1. in S0, throttle AP & GPU to the DC rating.
- * 5. Turn off the current active port.
- * 6. Turn on the highest power port.
- * 7. If
- *    1. in S0, throttle AP & GPU back.
- *
- * TODO: Are the following cases covered?
- * 1. Two AC adapters are plugged. Then, the active adapter is removed.
- *
  * TODO: Recover from incomplete execution:
- * 1. Failed to turn on/off PPC.
  */
 int board_set_active_charge_port(int port)
 {
-	enum charge_supplier supplier = charge_manager_get_supplier();
+	enum charge_supplier active_supplier = charge_manager_get_supplier();
 	int active_port = charge_manager_get_active_charge_port();
 
-	CPRINTS("Changing charge port to %d (current port=%d supplier=%d)",
-		port, active_port, supplier);
+	CPRINTS("Switching charger from P%d (supplier=%d) to P%d", active_port,
+		active_supplier, port);
 
 	if (port == CHARGE_PORT_NONE) {
 		CPRINTS("Disabling all charger ports");
 
-		board_throttle_ap_gpu(1);
-
-		board_disable_bj_port();
-		board_disable_vbus_sink(-1);
+		board_enable_bj_port(false);
+		board_disable_other_vbus_sink(-1);
 
 		return EC_SUCCESS;
 	}
 
+	/* Return on invalid or no-op call. */
 	if (port < 0 || CHARGE_PORT_COUNT <= port) {
 		return EC_ERROR_INVAL;
 	} else if (port == active_port) {
 		return EC_SUCCESS;
 	} else if (board_vbus_source_enabled(port)) {
 		/* Don't charge from a USBC source port */
-		CPRINTS("Don't enable C%d. It's sourcing.", port);
+		CPRINTS("Don't enable P%d. It's sourcing.", port);
 		return EC_ERROR_INVAL;
 	}
 
 	/*
+	 * If we're in S0, throttle AP and GPU. They'll be unthrottled when
+	 * a port/supply switch completes (via HOOK_POWER_SUPPLY_CHANGE).
+	 *
+	 * If we're running currently on a battery (active_supplier == NONE), we
+	 * don't need to throttle because we're not disabling any port.
+	 */
+	if (chipset_in_state(CHIPSET_STATE_ON) &&
+	    active_supplier != CHARGE_SUPPLIER_NONE)
+		board_throttle_ap_gpu();
+
+	/*
+	 * We're here for the two cases:
+	 * 1. A new charger was connected.
+	 * 2. One charger was disconnected and we're switching to another.
+	 */
+
+	/*
 	 * We need to check the battery if we're switching a source port. If
 	 * we're just starting up or no AC was previously plugged, we shouldn't
 	 * check the battery. Both cases can be caught by supplier == NONE.
 	 */
-	if (supplier != CHARGE_SUPPLIER_NONE) {
+	if (active_supplier != CHARGE_SUPPLIER_NONE) {
 		if (charge_get_percent() < MIN_BATT_FOR_SWITCHING_SOURCE_PORT)
 			return EC_ERROR_NOT_POWERED;
 	}
 
 	/* Turn off other ports' sink paths before enabling requested port. */
-	if (port == CHARGE_PORT_TYPEC0 || port == CHARGE_PORT_TYPEC1) {
+	if (is_pd_port(port)) {
 		/*
-		 * BJ port is on POR. So, we need to turn it off even if we're
-		 * not previously on BJ.
+		 * BJ port is enabled on start-up. So, we need to turn it off
+		 * even if we were not previously on BJ.
 		 */
-		board_disable_bj_port();
-		if (board_disable_vbus_sink(port))
+		board_enable_bj_port(false);
+		if (board_disable_other_vbus_sink(port))
 			return EC_ERROR_UNCHANGED;
 
 		/* Enable requested USBC charge port. */
@@ -187,26 +186,21 @@ int board_set_active_charge_port(int port)
 		 * We can't proceed unless both ports are successfully
 		 * disconnected as sources.
 		 */
-		if (board_disable_vbus_sink(-1))
+		if (board_disable_other_vbus_sink(-1))
 			return EC_ERROR_UNKNOWN;
-		board_enable_bj_port();
+		board_enable_bj_port(true);
 	}
 
-	/* Switching port is complete. Turn off throttling. */
-	if (supplier != CHARGE_SUPPLIER_NONE)
-		board_throttle_ap_gpu(0);
-
-	CPRINTS("New charger p%d", port);
+	CPRINTS("New charger P%d", port);
 
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 static const struct charge_port_info bj_power = {
@@ -216,32 +210,62 @@ static const struct charge_port_info bj_power = {
 };
 
 /* Debounce time for BJ plug/unplug */
-#define BJ_DEBOUNCE_MS		1000
+#define BJ_DEBOUNCE_MS CONFIG_EXTPOWER_DEBOUNCE_MS
+
+int board_should_charger_bypass(void)
+{
+	return charge_manager_get_active_charge_port() == DEDICATED_CHARGE_PORT;
+}
 
-static void bj_connect_deferred(void)
+static void bj_connect(void)
 {
 	static int8_t bj_connected = -1;
-	const struct charge_port_info *pi = NULL;
 	int connected = !gpio_get_level(GPIO_BJ_ADP_PRESENT_ODL);
 
+	/* Debounce */
 	if (connected == bj_connected)
 		return;
 
-	if (connected)
-		pi = &bj_power;
+	bj_connected = connected;
+	CPRINTS("BJ %sconnected", connected ? "" : "dis");
 
 	charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED,
-				     DEDICATED_CHARGE_PORT, pi);
-	bj_connected = connected;
-	CPRINTS("BJ %s", connected ? "connected" : "disconnected");
+				     DEDICATED_CHARGE_PORT,
+				     connected ? &bj_power : NULL);
 }
-DECLARE_DEFERRED(bj_connect_deferred);
+DECLARE_DEFERRED(bj_connect);
 
+/* This handler shouldn't be needed if ACOK from isl9241 is working. */
 void bj_present_interrupt(enum gpio_signal signal)
 {
-	hook_call_deferred(&bj_connect_deferred_data, BJ_DEBOUNCE_MS * MSEC);
+	hook_call_deferred(&bj_connect_data, BJ_DEBOUNCE_MS * MSEC);
 }
 
+void ac_change(void)
+{
+	/*
+	 * Serialize. We don't handle USB-C here because we'll get a
+	 * notification from TCPC.
+	 */
+	hook_call_deferred(&bj_connect_data, 0);
+}
+DECLARE_HOOK(HOOK_AC_CHANGE, ac_change, HOOK_PRIO_DEFAULT);
+
+static void power_supply_changed(void)
+{
+	/*
+	 * We've switched to a new charge port (or no port). Hardware throttles
+	 * can be removed now. Software throttles may stay enabled and change
+	 * as the situation changes.
+	 */
+	throttle_ap(THROTTLE_OFF, THROTTLE_HARD, THROTTLE_SRC_AC);
+	/*
+	 * Unthrottling GPU is done through a deferred call scheduled when it
+	 * was throttled.
+	 */
+}
+DECLARE_HOOK(HOOK_POWER_SUPPLY_CHANGE, power_supply_changed, HOOK_PRIO_DEFAULT);
+
 static void bj_state_init(void)
 {
 	/*
@@ -253,6 +277,8 @@ static void bj_state_init(void)
 			charge_manager_update_charge(j, i, NULL);
 	}
 
-	bj_connect_deferred();
+	bj_connect();
+
+	isl9241_set_ac_prochot(CHARGER_SOLO, AGAH_AC_PROCHOT_CURRENT_MA);
 }
 DECLARE_HOOK(HOOK_INIT, bj_state_init, HOOK_PRIO_INIT_CHARGE_MANAGER + 1);
diff --git a/board/agah/ec.tasklist b/board/agah/ec.tasklist
index 7286caf6c6..ebbfd239f9 100644
--- a/board/agah/ec.tasklist
+++ b/board/agah/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,6 +12,7 @@
 
 #define CONFIG_TASK_LIST \
 	TASK_ALWAYS(HOOKS, hook_task, NULL, HOOKS_TASK_STACK_SIZE) \
+	TASK_ALWAYS(LED, led_task, NULL, TASK_STACK_SIZE) \
 	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
 	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
 	TASK_ALWAYS(CHARGER, charger_task, NULL, BASEBOARD_CHARGER_TASK_STACK_SIZE) \
diff --git a/board/agah/fans.c b/board/agah/fans.c
index df6102b460..45533d9e8c 100644
--- a/board/agah/fans.c
+++ b/board/agah/fans.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -30,14 +30,14 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 static const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
 
 static const struct fan_conf fan_conf_1 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_1,	/* Use MFT id to control fan */
+	.ch = MFT_CH_1, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
diff --git a/board/agah/fw_config.c b/board/agah/fw_config.c
index 7a08e187a6..a16cf10d5a 100644
--- a/board/agah/fw_config.c
+++ b/board/agah/fw_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,7 +10,7 @@
 #include "cros_board_info.h"
 #include "fw_config.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 static union agah_cbi_fw_config fw_config;
 BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
diff --git a/board/agah/fw_config.h b/board/agah/fw_config.h
index fe9fa24135..7efdae51ac 100644
--- a/board/agah/fw_config.h
+++ b/board/agah/fw_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,9 +21,9 @@ enum ec_cfg_keyboard_backlight_type {
 
 union agah_cbi_fw_config {
 	struct {
-		enum ec_cfg_keyboard_backlight_type	kb_bl : 1;
-		uint32_t				audio : 3;
-		uint32_t				reserved_1 : 21;
+		enum ec_cfg_keyboard_backlight_type kb_bl : 1;
+		uint32_t audio : 3;
+		uint32_t reserved_1 : 21;
 	};
 	uint32_t raw_value;
 };
diff --git a/board/agah/gpio.inc b/board/agah/gpio.inc
index 41a8f2a4d8..a3a6610ac8 100644
--- a/board/agah/gpio.inc
+++ b/board/agah/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,6 +27,7 @@ GPIO_INT(USB_C2_BC12_INT_ODL,            PIN(8, 3), GPIO_INT_FALLING, bc12_inter
 GPIO_INT(USB_C2_TCPC_INT_ODL,            PIN(A, 7), GPIO_INT_FALLING, tcpc_alert_event)
 GPIO_INT(USB_C2_PPC_INT_ODL,             PIN(7, 0), GPIO_INT_FALLING, ppc_interrupt)
 GPIO_INT(BJ_ADP_PRESENT_ODL,             PIN(5, 6), GPIO_INT_BOTH | GPIO_PULL_UP, bj_present_interrupt)
+GPIO_INT(GPU_OVERT_ODL,                  PIN(5, 0), GPIO_INT_BOTH, gpu_overt_interrupt)
 
 /* USED GPIOs: */
 GPIO(CCD_MODE_ODL,                   PIN(E, 5), GPIO_INPUT)
@@ -54,7 +55,7 @@ GPIO(EC_PCH_RTCRST,                  PIN(7, 6), GPIO_OUT_LOW)
 GPIO(EC_PCH_SYS_PWROK,               PIN(3, 7), GPIO_OUT_LOW)
 GPIO(EC_PCH_WAKE_R_ODL,              PIN(C, 0), GPIO_ODR_HIGH)
 GPIO(EC_PROCHOT_ODL,                 PIN(6, 3), GPIO_ODR_HIGH)
-GPIO(EN_PP5000_FAN,                  PIN(6, 1), GPIO_OUT_HIGH)
+GPIO(EN_PP5000_FAN,                  PIN(6, 1), GPIO_OUT_LOW)
 GPIO(EN_PP5000_USBA_R,               PIN(D, 7), GPIO_OUT_LOW)
 GPIO(EN_S5_RAILS,                    PIN(9, 6), GPIO_OUT_LOW)
 GPIO(IMVP9_VRRDY_OD,                 PIN(4, 3), GPIO_INPUT)
@@ -67,8 +68,15 @@ GPIO(VCCST_PWRGD_OD,                 PIN(A, 4), GPIO_ODR_LOW)
 GPIO(EN_USB_A_LOW_POWER,             PIN(9, 3), GPIO_OUT_LOW)
 GPIO(PG_PP3300_S5_EC_SEQ_OD,         PIN(B, 5), GPIO_OUT_LOW)
 GPIO(USB_C2_FRS_EN,                  PIN(D, 4), GPIO_OUT_LOW)
+GPIO(NVIDIA_GPU_ACOFF_ODL,           PIN(9, 5), GPIO_ODR_HIGH)
+GPIO(LED_2_L,                        PIN(C, 3), GPIO_OUT_LOW)
+GPIO(LED_1_L,                        PIN(C, 4), GPIO_OUT_LOW)
 
-/* Barreljack */
+/*
+ * Barrel-jack adapter enable switch. When starting up on a depleted battery,
+ * we'll be powered by either BJ or USB-C but not both. The EC will detect BJ
+ * or USBC and disable the other ports.
+ */
 GPIO(EN_PPVAR_BJ_ADP_L,              PIN(A, 2), GPIO_OUT_LOW)
 
 /*
@@ -95,12 +103,10 @@ ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0)               /* GPIO40/TA1 */
 ALTERNATE(PIN_MASK(7, 0x08), 0, MODULE_PWM, 0)               /* GPIO73/TA2 */
 ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)               /* GPIO80/PWM3 */
 ALTERNATE(PIN_MASK(B, 0xC0), 0, MODULE_PWM, 0)               /* GPIOB7/PWM5, GPIOB6/PWM4 */
-ALTERNATE(PIN_MASK(C, 0x18), 0, MODULE_PWM, 0)               /* GPIOC4/PWM2, GPIOC3/PWM0 */
 
 /* ADC alternate functions */
 ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0)               /* GPIO34/PS2_DAT2/ADC6 */
-ALTERNATE(PIN_MASK(4, 0x34), 0, MODULE_ADC, 0)               /* GPIO42/ADC3/RI_L, GPIO45/ADC0, GPIO44/ADC1 */
-ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0)               /* GPIOE1/ADC7 */
+ALTERNATE(PIN_MASK(4, 0x36), 0, MODULE_ADC, 0)               /* GPIO42/ADC3/RI_L, GPIO45/ADC0, GPIO44/ADC1, GPIO41/ADC4 */
 
 /* KB alternate functions */
 ALTERNATE(PIN_MASK(0, 0xf0), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO10&P80_CLK/GPIO07, KSO11&P80_DAT/GPIO06, KSO12/GPIO05, KSO13/GPIO04 */
@@ -123,9 +129,6 @@ UNUSED(PIN(0, 2))       /* GPIO02 */
 UNUSED(PIN(6, 6))       /* GPIO66 */
 UNUSED(PIN(5, 7))       /* GPIO57/SER_IRQ/ESPI_ALERT_L */
 UNUSED(PIN(8, 1))       /* GPIO81 */
-UNUSED(PIN(9, 5))       /* GPIO95 */
-UNUSED(PIN(7, 3))       /* GPIO73 */
-UNUSED(PIN(4, 1))       /* GPIO41 */
-UNUSED(PIN(5, 0))       /* GPIO50 */
 UNUSED(PIN(6, 0))       /* GPIO60 */
 UNUSED(PIN(C, 2))       /* GPIOC2 */
+UNUSED(PIN(E, 1))       /* GPIOE1 */
diff --git a/board/agah/i2c.c b/board/agah/i2c.c
index dedf3b4c4f..5bdf6936c1 100644
--- a/board/agah/i2c.c
+++ b/board/agah/i2c.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,7 +8,7 @@
 #include "hooks.h"
 #include "i2c.h"
 
-#define BOARD_ID_FAST_PLUS_CAPABLE	2
+#define BOARD_ID_FAST_PLUS_CAPABLE 2
 
 /* I2C port map configuration */
 const struct i2c_port_t i2c_ports[] = {
diff --git a/board/agah/keyboard.c b/board/agah/keyboard.c
index d234dfd64e..cb34543db8 100644
--- a/board/agah/keyboard.c
+++ b/board/agah/keyboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -45,7 +45,6 @@ static const struct ec_response_keybd_config keybd = {
 	.capabilities = KEYBD_CAP_NUMERIC_KEYPAD,
 };
 
-
 __override const struct ec_response_keybd_config *
 board_vivaldi_keybd_config(void)
 {
diff --git a/board/agah/led.c b/board/agah/led.c
index 12a7c3e09f..e16b3df5d6 100644
--- a/board/agah/led.c
+++ b/board/agah/led.c
@@ -1,83 +1,192 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
- */
-
-/* Agah specific PWM LED settings: there are 2 LEDs on each side of the board,
- * each one can be controlled separately. The LED colors are white or amber,
- * and the default behavior is tied to the charging process: both sides are
- * amber while charging the battery and white when the battery is charged.
+ *
+ * Battery LED control for Agah
  */
 
 #include <stdint.h>
 
-#include "common.h"
-#include "compile_time_macros.h"
+#include "battery.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "chipset.h"
 #include "ec_commands.h"
-#include "led_pwm.h"
-#include "pwm.h"
-#include "util.h"
+#include "gpio.h"
+#include "host_command.h"
+#include "led_common.h"
+#include "task.h"
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_LEFT_LED,
-	EC_LED_ID_RIGHT_LED,
-};
+#define BAT_LED_ON 0
+#define BAT_LED_OFF 1
+
+#define BATT_LOW_BCT 10
+
+#define LED_TICK_INTERVAL_MS (500 * MSEC)
+#define LED_CYCLE_TIME_MS (2000 * MSEC)
+#define LED_TICKS_PER_CYCLE (LED_CYCLE_TIME_MS / LED_TICK_INTERVAL_MS)
+#define LED_ON_TIME_MS (1000 * MSEC)
+#define LED_ON_TICKS (LED_ON_TIME_MS / LED_TICK_INTERVAL_MS)
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-/*
- * We only have a white and an amber LED, so setting any other color results in
- * both LEDs being off. Cap at 50% to save power.
- */
-struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = {
-				/* Amber, White */
-	[EC_LED_COLOR_RED]    = {   0,   0 },
-	[EC_LED_COLOR_GREEN]  = {   0,   0 },
-	[EC_LED_COLOR_BLUE]   = {   0,   0 },
-	[EC_LED_COLOR_YELLOW] = {   0,   0 },
-	[EC_LED_COLOR_WHITE]  = {   0,  50 },
-	[EC_LED_COLOR_AMBER]  = {  50,   0 },
+enum led_color {
+	LED_OFF = 0,
+	LED_AMBER,
+	LED_WHITE,
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
-/* Two logical LEDs with amber and white channels. */
-struct pwm_led pwm_leds[CONFIG_LED_PWM_COUNT] = {
-	{
-		.ch0 = PWM_CH_LED1,
-		.ch1 = PWM_CH_LED2,
-		.ch2 = PWM_LED_NO_CHANNEL,
-		.enable = &pwm_enable,
-		.set_duty = &pwm_set_duty,
-	},
-};
+static void led_set_color_battery(enum led_color color)
+{
+	enum gpio_signal amber_led, white_led;
+
+	amber_led = GPIO_LED_1_L;
+	white_led = GPIO_LED_2_L;
+
+	switch (color) {
+	case LED_WHITE:
+		gpio_set_level(white_led, BAT_LED_ON);
+		gpio_set_level(amber_led, BAT_LED_OFF);
+		break;
+	case LED_AMBER:
+		gpio_set_level(white_led, BAT_LED_OFF);
+		gpio_set_level(amber_led, BAT_LED_ON);
+		break;
+	case LED_OFF:
+		gpio_set_level(white_led, BAT_LED_OFF);
+		gpio_set_level(amber_led, BAT_LED_OFF);
+		break;
+	default:
+		break;
+	}
+}
 
 void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
 {
-	memset(brightness_range, '\0',
-	       sizeof(*brightness_range) * EC_LED_COLOR_COUNT);
-	brightness_range[EC_LED_COLOR_AMBER] = 100;
-	brightness_range[EC_LED_COLOR_WHITE] = 100;
+	switch (led_id) {
+	case EC_LED_ID_BATTERY_LED:
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		break;
+	default:
+		break;
+	}
 }
 
 int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 {
-	enum pwm_led_id pwm_id;
-
-	/* Convert ec_led_id to pwm_led_id. */
 	switch (led_id) {
-	case EC_LED_ID_LEFT_LED:
-		pwm_id = PWM_LED0;
+	case EC_LED_ID_BATTERY_LED:
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_battery(LED_WHITE);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(LED_AMBER);
+		else
+			led_set_color_battery(LED_OFF);
 		break;
 	default:
-		return EC_ERROR_UNKNOWN;
+		return EC_ERROR_PARAM1;
 	}
 
-	if (brightness[EC_LED_COLOR_WHITE])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_WHITE);
-	else if (brightness[EC_LED_COLOR_AMBER])
-		set_pwm_led_color(pwm_id, EC_LED_COLOR_AMBER);
-	else
-		/* Otherwise, the "color" is "off". */
-		set_pwm_led_color(pwm_id, -1);
-
 	return EC_SUCCESS;
 }
+
+/*
+ * Set active charge port color to the parameter, turn off all others.
+ * If no port is active (-1), turn off all LEDs.
+ */
+static void set_active_port_color(enum led_color color)
+{
+	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
+		led_set_color_battery(color);
+}
+
+static void led_set_battery(void)
+{
+	static unsigned int battery_ticks;
+	static unsigned int suspend_ticks;
+
+	battery_ticks++;
+
+	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
+	    charge_get_state() != PWR_STATE_CHARGE) {
+		suspend_ticks++;
+
+		led_set_color_battery(
+			(suspend_ticks % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
+				LED_WHITE :
+				LED_OFF);
+
+		return;
+	}
+
+	switch (charge_get_state()) {
+	case PWR_STATE_CHARGE:
+		/* Always indicate when charging, even in suspend. */
+		set_active_port_color(LED_AMBER);
+		break;
+	case PWR_STATE_DISCHARGE:
+		/*
+		 * Blinking amber LEDs slowly if battery is lower 10
+		 * percentage.
+		 */
+		if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
+			if (charge_get_percent() < BATT_LOW_BCT)
+				led_set_color_battery(
+					(battery_ticks % LED_TICKS_PER_CYCLE <
+					 LED_ON_TICKS) ?
+						LED_AMBER :
+						LED_OFF);
+			else
+				led_set_color_battery(LED_OFF);
+		}
+
+		break;
+	case PWR_STATE_ERROR:
+		if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
+			led_set_color_battery(
+				(battery_ticks & 0x1) ? LED_AMBER : LED_OFF);
+		}
+
+		break;
+	case PWR_STATE_CHARGE_NEAR_FULL:
+		set_active_port_color(LED_WHITE);
+		break;
+	case PWR_STATE_IDLE: /* External power connected in IDLE */
+		set_active_port_color(LED_WHITE);
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		set_active_port_color(
+			(battery_ticks % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
+				LED_AMBER :
+				LED_OFF);
+		break;
+	default:
+		/* Other states don't alter LED behavior */
+		break;
+	}
+}
+
+void led_task(void *u)
+{
+	uint32_t start_time;
+	uint32_t task_duration;
+
+	while (1) {
+		start_time = get_time().le.lo;
+
+		led_set_battery();
+
+		/* Compute time for this iteration */
+		task_duration = get_time().le.lo - start_time;
+		/*
+		 * Compute wait time required to for next desired LED tick. If
+		 * the duration exceeds the tick time, then don't sleep.
+		 */
+		if (task_duration < LED_TICK_INTERVAL_MS)
+			usleep(LED_TICK_INTERVAL_MS - task_duration);
+	}
+}
diff --git a/board/agah/pwm.c b/board/agah/pwm.c
index 1b704bc71e..9fa0f41eff 100644
--- a/board/agah/pwm.c
+++ b/board/agah/pwm.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,16 +11,6 @@
 #include "pwm_chip.h"
 
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED2] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 4800,
-	},
-	[PWM_CH_LED1] = {
-		.channel = 2,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 4800,
-	},
 	[PWM_CH_KBLIGHT] = {
 		.channel = 3,
 		.flags = 0,
@@ -51,10 +41,6 @@ static void board_pwm_init(void)
 	 * Turn off all the LEDs.
 	 * Turn on the fan at 100%.
 	 */
-	pwm_enable(PWM_CH_LED1, 1);
-	pwm_set_duty(PWM_CH_LED1, 0);
-	pwm_enable(PWM_CH_LED2, 1);
-	pwm_set_duty(PWM_CH_LED2, 0);
 
 	pwm_enable(PWM_CH_KBLIGHT, 1);
 	pwm_set_duty(PWM_CH_KBLIGHT, 50);
diff --git a/board/agah/sensors.c b/board/agah/sensors.c
index b68984c95c..046787872d 100644
--- a/board/agah/sensors.c
+++ b/board/agah/sensors.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,8 +19,8 @@ struct adc_t adc_channels[] = {
 		.factor_div = ADC_READ_MAX + 1,
 		.shift = 0,
 	},
-	[ADC_TEMP_SENSOR_2_AMBIENT] = {
-		.name = "TEMP_AMBIENT",
+	[ADC_TEMP_SENSOR_2_GPU] = {
+		.name = "TEMP_GPU",
 		.input_ch = NPCX_ADC_CH1,
 		.factor_mul = ADC_MAX_VOLT,
 		.factor_div = ADC_READ_MAX + 1,
@@ -33,9 +33,16 @@ struct adc_t adc_channels[] = {
 		.factor_div = ADC_READ_MAX + 1,
 		.shift = 0,
 	},
-	[ADC_TEMP_SENSOR_4_WWAN] = {
-		.name = "TEMP_WWAN",
-		.input_ch = NPCX_ADC_CH7,
+	[ADC_CHARGER_IADP] = {
+		.name = "CHARGER_IADP",
+		.input_ch = NPCX_ADC_CH3,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_ADP_TYP] = {
+		.name = "ADP_TYP",
+		.input_ch = NPCX_ADC_CH4,
 		.factor_mul = ADC_MAX_VOLT,
 		.factor_div = ADC_READ_MAX + 1,
 		.shift = 0,
@@ -51,11 +58,11 @@ const struct temp_sensor_t temp_sensors[] = {
 		.read = get_temp_3v3_30k9_47k_4050b,
 		.idx = ADC_TEMP_SENSOR_1_DDR_SOC,
 	},
-	[TEMP_SENSOR_2_AMBIENT] = {
-		.name = "Ambient",
+	[TEMP_SENSOR_2_GPU] = {
+		.name = "GPU",
 		.type = TEMP_SENSOR_TYPE_BOARD,
 		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_2_AMBIENT,
+		.idx = ADC_TEMP_SENSOR_2_GPU,
 	},
 	[TEMP_SENSOR_3_CHARGER] = {
 		.name = "Charger",
@@ -63,17 +70,11 @@ const struct temp_sensor_t temp_sensors[] = {
 		.read = get_temp_3v3_30k9_47k_4050b,
 		.idx = ADC_TEMP_SENSOR_3_CHARGER,
 	},
-	[TEMP_SENSOR_4_WWAN] = {
-		.name = "WWAN",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_4_WWAN,
-	},
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
-#define THERMAL_CPU \
-	{ \
+#define THERMAL_CPU              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(85), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(90), \
@@ -86,8 +87,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 	}
 __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 
-#define THERMAL_AMBIENT \
-	{ \
+#define THERMAL_GPU              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(85), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(90), \
@@ -98,8 +99,7 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 		.temp_fan_off = C_TO_K(35), \
 		.temp_fan_max = C_TO_K(60), \
 	}
-__maybe_unused static const struct ec_thermal_config thermal_ambient =
-	THERMAL_AMBIENT;
+__maybe_unused static const struct ec_thermal_config thermal_gpu = THERMAL_GPU;
 
 /*
  * Inductor limits - used for both charger and PP3300 regulator
@@ -112,8 +112,8 @@ __maybe_unused static const struct ec_thermal_config thermal_ambient =
  * Inductors: limit of 125c
  * PCB: limit is 80c
  */
-#define THERMAL_CHARGER \
-	{ \
+#define THERMAL_CHARGER          \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(105), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(120), \
@@ -127,25 +127,9 @@ __maybe_unused static const struct ec_thermal_config thermal_ambient =
 __maybe_unused static const struct ec_thermal_config thermal_charger =
 	THERMAL_CHARGER;
 
-#define THERMAL_WWAN \
-	{ \
-		.temp_host = { \
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(130), \
-			[EC_TEMP_THRESH_HALT] = C_TO_K(130), \
-		}, \
-		.temp_host_release = { \
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(100), \
-		}, \
-		.temp_fan_off = C_TO_K(35), \
-		.temp_fan_max = C_TO_K(60), \
-	}
-__maybe_unused static const struct ec_thermal_config thermal_wwan =
-	THERMAL_WWAN;
-
 struct ec_thermal_config thermal_params[] = {
 	[TEMP_SENSOR_1_DDR_SOC] = THERMAL_CPU,
-	[TEMP_SENSOR_2_AMBIENT] = THERMAL_AMBIENT,
+	[TEMP_SENSOR_2_GPU] = THERMAL_GPU,
 	[TEMP_SENSOR_3_CHARGER] = THERMAL_CHARGER,
-	[TEMP_SENSOR_4_WWAN] = THERMAL_WWAN,
 };
 BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
diff --git a/board/agah/usbc_config.c b/board/agah/usbc_config.c
index 0902f2f799..a8bad0f121 100644
--- a/board/agah/usbc_config.c
+++ b/board/agah/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,7 +14,7 @@
 #include "console.h"
 #include "driver/bc12/pi3usb9201_public.h"
 #include "driver/ppc/syv682x_public.h"
-#include "driver/retimer/ps8818.h"
+#include "driver/retimer/ps8818_public.h"
 #include "driver/tcpm/rt1715.h"
 #include "driver/tcpm/tcpci.h"
 #include "ec_commands.h"
@@ -33,8 +33,8 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 /* USBC TCPC configuration */
 const struct tcpc_config_t tcpc_config[] = {
@@ -116,18 +116,17 @@ const static struct ps8818_reg_val equalizer_default_table[] = {
 
 #define NUM_EQ_DEFAULT_ARRAY ARRAY_SIZE(equalizer_default_table)
 
-int board_ps8818_mux_set(const struct usb_mux *me,
-				    mux_state_t mux_state)
+int board_ps8818_mux_set(const struct usb_mux *me, mux_state_t mux_state)
 {
 	int rv = EC_SUCCESS;
 	int i;
 
 	/* USB specific config */
 	if (mux_state & USB_PD_MUX_USB_ENABLED) {
-
 		/* Boost the USB gain */
 		for (i = 0; i < NUM_EQ_DEFAULT_ARRAY; i++)
-			rv |= ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+			rv |= ps8818_i2c_field_update8(
+				me, PS8818_REG_PAGE1,
 				equalizer_default_table[i].reg,
 				equalizer_default_table[i].mask,
 				equalizer_default_table[i].val);
@@ -136,36 +135,42 @@ int board_ps8818_mux_set(const struct usb_mux *me,
 	/* DP specific config */
 	if (mux_state & USB_PD_MUX_DP_ENABLED) {
 		/* Boost the DP gain */
-		rv |= ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_DPEQ_LEVEL,
-					PS8818_DPEQ_LEVEL_UP_MASK,
-					PS8818_DPEQ_LEVEL_UP_19DB);
+		rv |= ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					       PS8818_REG1_DPEQ_LEVEL,
+					       PS8818_DPEQ_LEVEL_UP_MASK,
+					       PS8818_DPEQ_LEVEL_UP_19DB);
 	}
 
 	return rv;
 }
 
-const static struct usb_mux usbc2_ps8818 = {
-	.usb_port = USBC_PORT_C2,
-	.i2c_port = I2C_PORT_USB_C2_TCPC,
-	.i2c_addr_flags = PS8818_I2C_ADDR_FLAGS,
-	.driver = &ps8818_usb_retimer_driver,
-	.board_set = &board_ps8818_mux_set,
+const static struct usb_mux_chain usbc2_ps8818 = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C2,
+			.i2c_port = I2C_PORT_USB_C2_TCPC,
+			.i2c_addr_flags = PS8818_I2C_ADDR_FLAGS,
+			.driver = &ps8818_usb_retimer_driver,
+			.board_set = &board_ps8818_mux_set,
+		},
 };
 
 /* USBC mux configuration - Alder Lake includes internal mux */
-const struct usb_mux usb_muxes[] = {
+const struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 	},
 	[USBC_PORT_C2] = {
-		.usb_port = USBC_PORT_C2,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc2_ps8818,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C2,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc2_ps8818,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
@@ -203,8 +208,8 @@ int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
 	}
 
 	if (voltage < BC12_MIN_VOLTAGE) {
-		CPRINTS("%s: port %d: vbus %d lower than %d", __func__,
-			port, voltage, BC12_MIN_VOLTAGE);
+		CPRINTS("%s: port %d: vbus %d lower than %d", __func__, port,
+			voltage, BC12_MIN_VOLTAGE);
 		return 1;
 	}
 
@@ -215,7 +220,7 @@ int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
 
 void board_reset_pd_mcu(void)
 {
- /* There's no reset pin on TCPC */
+	/* There's no reset pin on TCPC */
 }
 
 static void board_tcpc_init(void)
diff --git a/board/agah/usbc_config.h b/board/agah/usbc_config.h
index e5b7576d72..e353263f5f 100644
--- a/board/agah/usbc_config.h
+++ b/board/agah/usbc_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,13 +8,9 @@
 #ifndef __CROS_EC_USBC_CONFIG_H
 #define __CROS_EC_USBC_CONFIG_H
 
-#define CONFIG_USB_PD_PORT_MAX_COUNT	2
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C2,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C2, USBC_PORT_COUNT };
 
 struct ps8818_reg_val {
 	uint8_t reg;
diff --git a/board/akemi/battery.c b/board/akemi/battery.c
index 238716b116..de380ac01c 100644
--- a/board/akemi/battery.c
+++ b/board/akemi/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/akemi/board.c b/board/akemi/board.c
index de5438344e..7d480b1268 100644
--- a/board/akemi/board.c
+++ b/board/akemi/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -43,8 +43,8 @@
 #include "util.h"
 #include "battery_smart.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* GPIO to enable/disable the USB Type-A port. */
 const int usb_port_enable[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT] = {
@@ -105,16 +105,16 @@ static void bc12_interrupt(enum gpio_signal signal)
 
 /******************************************************************************/
 /* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
+const struct spi_device_t spi_devices[] = {};
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
 /******************************************************************************/
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT]   = { .channel = 3, .flags = 0, .freq = 10000 },
-	[PWM_CH_FAN] = {.channel = 5, .flags = PWM_CONFIG_OPEN_DRAIN,
-			.freq = 25000},
+	[PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 },
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
@@ -140,16 +140,20 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_TCPC_0] = {
-		.usb_port = USB_PD_PORT_TCPC_0,
-		.driver = &anx7447_usb_mux_driver,
-		.hpd_update = &anx7447_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_0,
+			.driver = &anx7447_usb_mux_driver,
+			.hpd_update = &anx7447_tcpc_update_hpd_status,
+		},
 	},
 	[USB_PD_PORT_TCPC_1] = {
-		.usb_port = USB_PD_PORT_TCPC_1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 	}
 };
 
@@ -177,17 +181,13 @@ static struct stprivate_data g_lis2dwl_data;
 static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
 
 /* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, FLOAT_TO_FP(1), 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
 
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+					     { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
@@ -267,13 +267,12 @@ struct motion_sensor_t motion_sensors[] = {
 };
 unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
-
 /******************************************************************************/
 /* Physical fans. These are logically separate from pwm_channels. */
 
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
@@ -292,36 +291,35 @@ const struct fan_t fans[FAN_CH_COUNT] = {
 /******************************************************************************/
 /* MFT channels. These are logically separate from pwm_channels. */
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN },
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_2] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_1] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_2] = { "TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Temp1",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Temp2",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "Temp3",
-				 .type = TEMP_SENSOR_TYPE_CPU,
-				 .read = g753_get_val,
-				 .idx = 0},
+	[TEMP_SENSOR_1] = { .name = "Temp1",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Temp2",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "Temp3",
+			    .type = TEMP_SENSOR_TYPE_CPU,
+			    .read = g753_get_val,
+			    .idx = 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
-
 /* Hatch Temperature sensors */
 /*
  * TODO(b/124316213): These setting need to be reviewed and set appropriately
@@ -331,8 +329,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_A \
-	{ \
+#define THERMAL_A                \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = 0, \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
@@ -391,12 +389,12 @@ __override uint32_t board_override_feature_flags0(uint32_t flags0)
 }
 
 /* Battery functions */
-#define SB_OPTIONALMFG_FUNCTION2        0x26
-#define QUICK_CHARGE_SUPPORT            0x01
-#define QUICK_CHARGE_ENABLE             0x02
+#define SB_OPTIONALMFG_FUNCTION2 0x26
+#define QUICK_CHARGE_SUPPORT 0x01
+#define QUICK_CHARGE_ENABLE 0x02
 
-#define SB_QUICK_CHARGE_ENABLE          1
-#define SB_QUICK_CHARGE_DISABLE         0
+#define SB_QUICK_CHARGE_ENABLE 1
+#define SB_QUICK_CHARGE_DISABLE 0
 
 static void sb_quick_charge_mode(int enable)
 {
@@ -422,7 +420,8 @@ static void board_chipset_startup(void)
 	/* Normal charge current */
 	sb_quick_charge_mode(SB_QUICK_CHARGE_DISABLE);
 }
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_INIT_I2C+1);
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup,
+	     HOOK_PRIO_INIT_I2C + 1);
 
 /* Called on AP S0 -> S5 transition */
 static void board_chipset_shutdown(void)
@@ -437,5 +436,5 @@ bool board_is_convertible(void)
 	const uint8_t sku = get_board_sku();
 
 	return (sku == 255) || (sku == 1) || (sku == 2) || (sku == 3) ||
-		(sku == 4);
+	       (sku == 4);
 }
diff --git a/board/akemi/board.h b/board/akemi/board.h
index caf1a39147..bdc18638f8 100644
--- a/board/akemi/board.h
+++ b/board/akemi/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -102,16 +102,16 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_PG_EC_RSMRST_ODL	GPIO_PG_EC_RSMRST_L
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_AC_PRESENT		GPIO_ACOK_OD
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_TEMP_SENSOR_POWER	GPIO_EN_A_RAILS
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
+#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
 
 #ifndef __ASSEMBLER__
 
@@ -119,8 +119,8 @@
 #include "registers.h"
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_1,	/* ADC0 */
-	ADC_TEMP_SENSOR_2,	/* ADC1 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
 	ADC_CH_COUNT
 };
 
@@ -131,11 +131,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_FAN,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_FAN, PWM_CH_COUNT };
 
 enum fan_channel {
 	FAN_CH_0 = 0,
diff --git a/board/akemi/build.mk b/board/akemi/build.mk
index 733912454f..13153c1526 100644
--- a/board/akemi/build.mk
+++ b/board/akemi/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/akemi/ec.tasklist b/board/akemi/ec.tasklist
index 4a1024a091..829be2b7c8 100644
--- a/board/akemi/ec.tasklist
+++ b/board/akemi/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/akemi/gpio.inc b/board/akemi/gpio.inc
index 1ea8cca58a..05466078c7 100644
--- a/board/akemi/gpio.inc
+++ b/board/akemi/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,10 +16,10 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(PG_EC_RSMRST_L,       PIN(E, 2), GPIO_INT_BOTH, intel_x86_rsmrst_signal_interrupt)
diff --git a/board/akemi/led.c b/board/akemi/led.c
index 80d52f7cc2..49f767a28e 100644
--- a/board/akemi/led.c
+++ b/board/akemi/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,33 +19,35 @@ __override const int led_charge_lvl_1 = 5;
 __override const int led_charge_lvl_2 = 97;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
 
 __override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-					{LED_OFF,          0.5 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 3 * LED_ONE_SEC },
+					       { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-	EC_LED_ID_BATTERY_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED,
+					     EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -58,7 +60,6 @@ __override void led_set_color_power(enum ec_led_colors color)
 		gpio_set_level(GPIO_LED_3_L, LED_OFF_LVL);
 }
 
-
 __override void led_set_color_battery(enum ec_led_colors color)
 {
 	switch (color) {
diff --git a/board/aleena/battery.c b/board/aleena/battery.c
index b3abae7f73..0862ba209f 100644
--- a/board/aleena/battery.c
+++ b/board/aleena/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/aleena/board.c b/board/aleena/board.c
index 460c73fcdd..0970a7513c 100644
--- a/board/aleena/board.c
+++ b/board/aleena/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -31,52 +31,40 @@ const enum gpio_signal hibernate_wake_pins[] = {
 	GPIO_POWER_BUTTON_L,
 	GPIO_EC_RST_ODL,
 };
-const int hibernate_wake_pins_used =  ARRAY_SIZE(hibernate_wake_pins);
+const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 
 /* I2C port map. */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl  = GPIO_I2C0_SCL,
-		.sda  = GPIO_I2C0_SDA
-	},
-	{
-		.name = "tcpc0",
-		.port = I2C_PORT_TCPC0,
-		.kbps = 400,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	},
-	{
-		.name = "tcpc1",
-		.port = I2C_PORT_TCPC1,
-		.kbps = 400,
-		.scl  = GPIO_I2C2_SCL,
-		.sda  = GPIO_I2C2_SDA
-	},
-	{
-		.name = "thermal",
-		.port = I2C_PORT_THERMAL_AP,
-		.kbps = 400,
-		.scl  = GPIO_I2C3_SCL,
-		.sda  = GPIO_I2C3_SDA
-	},
-	{
-		.name = "kblight",
-		.port = I2C_PORT_KBLIGHT,
-		.kbps = 100,
-		.scl  = GPIO_I2C5_SCL,
-		.sda  = GPIO_I2C5_SDA
-	},
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl  = GPIO_I2C7_SCL,
-		.sda  = GPIO_I2C7_SDA
-	},
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_I2C0_SCL,
+	  .sda = GPIO_I2C0_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "tcpc1",
+	  .port = I2C_PORT_TCPC1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "thermal",
+	  .port = I2C_PORT_THERMAL_AP,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
+	{ .name = "kblight",
+	  .port = I2C_PORT_KBLIGHT,
+	  .kbps = 100,
+	  .scl = GPIO_I2C5_SCL,
+	  .sda = GPIO_I2C5_SDA },
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_I2C7_SCL,
+	  .sda = GPIO_I2C7_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -101,11 +89,9 @@ enum base_accelgyro_type {
 	BASE_GYRO_ICM426XX = 2,
 };
 
-const mat33_fp_t base_standard_ref_icm426xx = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_standard_ref_icm426xx = { { 0, FLOAT_TO_FP(-1), 0 },
+						{ FLOAT_TO_FP(1), 0, 0 },
+						{ 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t icm426xx_base_accel = {
 	 .name = "Base Accel",
@@ -136,20 +122,20 @@ struct motion_sensor_t icm426xx_base_accel = {
 };
 
 struct motion_sensor_t icm426xx_base_gyro = {
-	 .name = "Base Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_ICM426XX,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &icm426xx_drv,
-	 .mutex = &icm426xx_mutex,
-	 .drv_data = &g_icm426xx_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &base_standard_ref_icm426xx,
-	 .min_frequency = ICM426XX_GYRO_MIN_FREQ,
-	 .max_frequency = ICM426XX_GYRO_MAX_FREQ,
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &icm426xx_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &base_standard_ref_icm426xx,
+	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
+	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
 };
 
 static enum base_accelgyro_type base_accelgyro_config;
@@ -179,18 +165,20 @@ static void board_detect_motionsensor(void)
 
 	if (board_is_convertible()) {
 		/* Check base accelgyro chip */
-		ret = icm_read8(&icm426xx_base_accel,
-				 ICM426XX_REG_WHO_AM_I, &val);
+		ret = icm_read8(&icm426xx_base_accel, ICM426XX_REG_WHO_AM_I,
+				&val);
 		if (ret)
 			ccprints("Get ICM fail.");
 		if (val == ICM426XX_CHIP_ICM40608) {
 			motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
 			motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
 		}
-		base_accelgyro_config = (val == ICM426XX_CHIP_ICM40608)
-			 ? BASE_GYRO_ICM426XX : BASE_GYRO_BMI160;
-		ccprints("Base Accelgyro: %s", (val == ICM426XX_CHIP_ICM40608)
-			 ? "ICM40608" : "BMI160");
+		base_accelgyro_config = (val == ICM426XX_CHIP_ICM40608) ?
+						BASE_GYRO_ICM426XX :
+						BASE_GYRO_BMI160;
+		ccprints("Base Accelgyro: %s", (val == ICM426XX_CHIP_ICM40608) ?
+						       "ICM40608" :
+						       "BMI160");
 	}
 }
 DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_detect_motionsensor,
@@ -207,8 +195,7 @@ void board_update_sensor_config_from_sku(void)
 		/* Device is clamshell only */
 		tablet_set_mode(0, TABLET_TRIGGER_LID);
 		/* Gyro is not present, don't allow line to float */
-		gpio_set_flags(GPIO_6AXIS_INT_L,
-			       GPIO_INPUT | GPIO_PULL_DOWN);
+		gpio_set_flags(GPIO_6AXIS_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
 	}
 }
 
@@ -230,15 +217,14 @@ DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_kblight_init, HOOK_PRIO_DEFAULT);
  * The connector has 30 pins total, and there is no pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-		{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-		{0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3},
-		{-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0},
-		{1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4},
-		{2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0},
-		{-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1},
-		{-1, -1},
+	{ -1, -1 }, { 0, 5 },	{ 1, 1 }, { 1, 0 },   { 0, 6 },	  { 0, 7 },
+	{ -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 },   { -1, -1 }, { 1, 6 },
+	{ 1, 7 },   { 3, 1 },	{ 2, 0 }, { 1, 5 },   { 2, 6 },	  { 2, 7 },
+	{ 2, 1 },   { 2, 4 },	{ 2, 5 }, { 1, 2 },   { 2, 3 },	  { 2, 2 },
+	{ 3, 0 },   { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 },	  { -1, -1 },
+	{ -1, -1 },
 };
 
 const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 #endif
diff --git a/board/aleena/board.h b/board/aleena/board.h
index dab6f3de3a..f51b7b3e16 100644
--- a/board/aleena/board.h
+++ b/board/aleena/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,7 @@
  * By default, enable all console messages excepted HC, ACPI and event:
  * The sensor stack is generating a lot of activity.
  */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
 #undef CONFIG_HOSTCMD_DEBUG_MODE
 #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
 
@@ -37,7 +37,7 @@
 #define CONFIG_ACCELGYRO_BMI160
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCELGYRO_ICM426XX	/* Base accel second source*/
+#define CONFIG_ACCELGYRO_ICM426XX /* Base accel second source*/
 #define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 #define CONFIG_ACCEL_KX022
@@ -51,17 +51,14 @@
 /*
  * Slew rate on the PP1800_SENSOR load switch requires a short delay on startup.
  */
-#undef  CONFIG_MOTION_SENSE_RESUME_DELAY_US
+#undef CONFIG_MOTION_SENSE_RESUME_DELAY_US
 #define CONFIG_MOTION_SENSE_RESUME_DELAY_US (10 * MSEC)
 
 #define CONFIG_KEYBOARD_FACTORY_TEST
 
 #ifndef __ASSEMBLER__
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_COUNT };
 
 enum battery_type {
 	BATTERY_PANASONIC,
diff --git a/board/aleena/build.mk b/board/aleena/build.mk
index c808e65aed..d24127ddae 100644
--- a/board/aleena/build.mk
+++ b/board/aleena/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/aleena/ec.tasklist b/board/aleena/ec.tasklist
index dc898c4502..9572d61c8f 100644
--- a/board/aleena/ec.tasklist
+++ b/board/aleena/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/aleena/gpio.inc b/board/aleena/gpio.inc
index 6fefcf88f1..669c833e56 100644
--- a/board/aleena/gpio.inc
+++ b/board/aleena/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/aleena/led.c b/board/aleena/led.c
index 4774a39045..c24bc404cc 100644
--- a/board/aleena/led.c
+++ b/board/aleena/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,10 +10,10 @@
 #include "hooks.h"
 #include "console.h"
 
-#define CPRINTS(format, args...) cprints(CC_HOOK, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_HOOK, format, ##args)
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
 __override const int led_charge_lvl_1;
 
@@ -29,18 +29,24 @@ static enum gpio_signal led_blue = GPIO_BAT_LED_2_L;
 
 /* Note there is only LED for charge / power */
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,  2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
 const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
@@ -48,10 +54,9 @@ const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 static void board_led_init(void)
 {
-	int board_id =
-		(gpio_get_level(GPIO_BOARD_VERSION3) << 2) |
-		(gpio_get_level(GPIO_BOARD_VERSION2) << 1) |
-		(gpio_get_level(GPIO_BOARD_VERSION1) << 0);
+	int board_id = (gpio_get_level(GPIO_BOARD_VERSION3) << 2) |
+		       (gpio_get_level(GPIO_BOARD_VERSION2) << 1) |
+		       (gpio_get_level(GPIO_BOARD_VERSION1) << 0);
 
 	CPRINTS("board_id=%d", board_id);
 
@@ -60,7 +65,6 @@ static void board_led_init(void)
 		led_blue = GPIO_BAT_LED_1_L;
 		CPRINTS("LED: switch LED");
 	}
-
 }
 DECLARE_HOOK(HOOK_INIT, board_led_init, HOOK_PRIO_DEFAULT);
 
diff --git a/board/ambassador/board.c b/board/ambassador/board.c
index 5cf319bc79..f2bc7557ec 100644
--- a/board/ambassador/board.c
+++ b/board/ambassador/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -45,8 +45,8 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void power_monitor(void);
 DECLARE_DEFERRED(power_monitor);
@@ -88,8 +88,8 @@ uint16_t tcpc_get_alert_status(void)
 }
 
 /* Called when the charge manager has switched to a new port. */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	/* Blink alert if insufficient power per system_can_boot_ap(). */
 	int insufficient_power =
@@ -105,14 +105,14 @@ static int32_t base_5v_power;
  * Power usage for each port as measured or estimated.
  * Units are milliwatts (5v x ma current)
  */
-#define PWR_BASE_LOAD	(5*1335)
-#define PWR_FRONT_HIGH	(5*1603)
-#define PWR_FRONT_LOW	(5*963)
-#define PWR_REAR	(5*1075)
-#define PWR_HDMI	(5*562)
-#define PWR_C_HIGH	(5*3740)
-#define PWR_C_LOW	(5*2090)
-#define PWR_MAX		(5*10000)
+#define PWR_BASE_LOAD (5 * 1335)
+#define PWR_FRONT_HIGH (5 * 1603)
+#define PWR_FRONT_LOW (5 * 963)
+#define PWR_REAR (5 * 1075)
+#define PWR_HDMI (5 * 562)
+#define PWR_C_HIGH (5 * 3740)
+#define PWR_C_LOW (5 * 2090)
+#define PWR_MAX (5 * 10000)
 
 /*
  * Update the 5V power usage, assuming no throttling,
@@ -185,16 +185,14 @@ static const struct {
 	int current;
 } bj_power[] = {
 	{ /* 0 - 65W (also default) */
-	.voltage = 19000,
-	.current = 3420
-	},
+	  .voltage = 19000,
+	  .current = 3420 },
 	{ /* 1 - 90W */
-	.voltage = 19000,
-	.current = 4740
-	},
+	  .voltage = 19000,
+	  .current = 4740 },
 };
 
-#define ADP_DEBOUNCE_MS		1000  /* Debounce time for BJ plug/unplug */
+#define ADP_DEBOUNCE_MS 1000 /* Debounce time for BJ plug/unplug */
 /* Debounced connection state of the barrel jack */
 static int8_t adp_connected = -1;
 static void adp_connect_deferred(void)
@@ -239,27 +237,25 @@ static void adp_state_init(void)
 }
 DECLARE_HOOK(HOOK_INIT, adp_state_init, HOOK_PRIO_INIT_CHARGE_MANAGER + 1);
 
-
 #include "gpio_list.h" /* Must come after other header files. */
 
 /******************************************************************************/
 /* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
+const struct spi_device_t spi_devices[] = {};
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
 /******************************************************************************/
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN]        = { .channel = 5,
-				.flags = PWM_CONFIG_OPEN_DRAIN,
-				.freq = 25000},
-	[PWM_CH_LED_RED]    = { .channel = 0,
-				.flags = PWM_CONFIG_DSLEEP,
-				.freq = 2000 },
-	[PWM_CH_LED_WHITE]  = { .channel = 2,
-				.flags = PWM_CONFIG_DSLEEP,
-				.freq = 2000 },
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
+	[PWM_CH_LED_RED] = { .channel = 0,
+			     .flags = PWM_CONFIG_DSLEEP,
+			     .freq = 2000 },
+	[PWM_CH_LED_WHITE] = { .channel = 2,
+			       .flags = PWM_CONFIG_DSLEEP,
+			       .freq = 2000 },
 };
 
 /******************************************************************************/
@@ -275,52 +271,44 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.flags = TCPC_FLAGS_RESET_ACTIVE_HIGH,
 	},
 };
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_TCPC_0] = {
-		.usb_port = USB_PD_PORT_TCPC_0,
-		.driver = &anx7447_usb_mux_driver,
-		.hpd_update = &anx7447_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_0,
+			.driver = &anx7447_usb_mux_driver,
+			.hpd_update = &anx7447_tcpc_update_hpd_status,
+		},
 	},
 };
 
 /******************************************************************************/
 /* I2C port map configuration */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "ina",
-		.port = I2C_PORT_INA,
-		.kbps = 400,
-		.scl  = GPIO_I2C0_SCL,
-		.sda  = GPIO_I2C0_SDA
-	},
-	{
-		.name = "ppc0",
-		.port = I2C_PORT_PPC0,
-		.kbps = 400,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	},
-	{
-		.name = "tcpc0",
-		.port = I2C_PORT_TCPC0,
-		.kbps = 400,
-		.scl  = GPIO_I2C3_SCL,
-		.sda  = GPIO_I2C3_SDA
-	},
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 400,
-		.scl  = GPIO_I2C5_SCL,
-		.sda  = GPIO_I2C5_SDA
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl  = GPIO_I2C7_SCL,
-		.sda  = GPIO_I2C7_SDA
-	},
+	{ .name = "ina",
+	  .port = I2C_PORT_INA,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_SCL,
+	  .sda = GPIO_I2C0_SDA },
+	{ .name = "ppc0",
+	  .port = I2C_PORT_PPC0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 400,
+	  .scl = GPIO_I2C5_SCL,
+	  .sda = GPIO_I2C5_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_I2C7_SCL,
+	  .sda = GPIO_I2C7_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -376,15 +364,14 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
 /******************************************************************************/
 /* Wake up pins */
-const enum gpio_signal hibernate_wake_pins[] = {
-};
+const enum gpio_signal hibernate_wake_pins[] = {};
 const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 
 /******************************************************************************/
 /* Physical fans. These are logically separate from pwm_channels. */
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = -1,
 };
@@ -403,7 +390,7 @@ BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
 /******************************************************************************/
 /* MFT channels. These are logically separate from pwm_channels. */
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN },
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
@@ -412,8 +399,8 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_A \
-	{ \
+#define THERMAL_A                \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = 0, \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(78), \
@@ -432,8 +419,8 @@ __maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_B \
-	{ \
+#define THERMAL_B                \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = 0, \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(78), \
@@ -535,16 +522,13 @@ static void board_chipset_startup(void)
 	if (ppc_is_sourcing_vbus(0))
 		ppc_vbus_source_enable(0, 1);
 }
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup,
-	     HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
 /******************************************************************************/
 /* USB-C PPC Configuration */
 struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.i2c_port = I2C_PORT_PPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
+	[USB_PD_PORT_TCPC_0] = { .i2c_port = I2C_PORT_PPC0,
+				 .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+				 .drv = &sn5s330_drv },
 };
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
@@ -577,14 +561,12 @@ static void board_tcpc_init(void)
 		/*
 		 * By default configured as output low.
 		 */
-		gpio_set_flags(GPIO_USB_A4_OC_ODL,
-			       GPIO_INPUT | GPIO_INT_BOTH);
+		gpio_set_flags(GPIO_USB_A4_OC_ODL, GPIO_INPUT | GPIO_INT_BOTH);
 		gpio_enable_interrupt(GPIO_USB_A4_OC_ODL);
 	} else {
 		/* Ensure no interrupts from pin */
 		gpio_disable_interrupt(GPIO_USB_A4_OC_ODL);
 	}
-
 }
 /* Make sure this is called after fw_config is initialised */
 DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 2);
@@ -703,8 +685,8 @@ void board_enable_s0_rails(int enable)
 
 unsigned int ec_config_get_bj_power(void)
 {
-	unsigned int bj =
-		(fw_config & EC_CFG_BJ_POWER_MASK) >> EC_CFG_BJ_POWER_L;
+	unsigned int bj = (fw_config & EC_CFG_BJ_POWER_MASK) >>
+			  EC_CFG_BJ_POWER_L;
 	/* Out of range value defaults to 0 */
 	if (bj >= ARRAY_SIZE(bj_power))
 		bj = 0;
@@ -779,23 +761,23 @@ DECLARE_HOOK(HOOK_INIT, setup_thermal, HOOK_PRIO_DEFAULT - 1);
  *
  *  All measurements are in milliwatts.
  */
-#define THROT_TYPE_A		BIT(0)
-#define THROT_TYPE_C		BIT(1)
-#define THROT_PROCHOT		BIT(2)
+#define THROT_TYPE_A BIT(0)
+#define THROT_TYPE_C BIT(1)
+#define THROT_PROCHOT BIT(2)
 
 /*
  * Power gain if front USB A ports are limited.
  */
-#define POWER_GAIN_TYPE_A	3200
+#define POWER_GAIN_TYPE_A 3200
 /*
  * Power gain if Type C port is limited.
  */
-#define POWER_GAIN_TYPE_C	8800
+#define POWER_GAIN_TYPE_C 8800
 /*
  * Power is averaged over 10 ms, with a reading every 2 ms.
  */
-#define POWER_DELAY_MS		2
-#define POWER_READINGS		(10/POWER_DELAY_MS)
+#define POWER_DELAY_MS 2
+#define POWER_READINGS (10 / POWER_DELAY_MS)
 
 static void power_monitor(void)
 {
@@ -810,8 +792,7 @@ static void power_monitor(void)
 	 * If CPU is off or suspended, no need to throttle
 	 * or restrict power.
 	 */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF |
-			     CHIPSET_STATE_SUSPEND)) {
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF | CHIPSET_STATE_SUSPEND)) {
 		/*
 		 * Slow down monitoring, assume no throttling required.
 		 */
@@ -839,7 +820,7 @@ static void power_monitor(void)
 			 */
 			power = (adc_read_channel(ADC_VBUS) *
 				 adc_read_channel(ADC_PPVAR_IMON)) /
-				 1000;
+				1000;
 			/* Init power table */
 			if (history[0] == 0) {
 				for (i = 0; i < POWER_READINGS; i++)
@@ -866,8 +847,7 @@ static void power_monitor(void)
 			 * For barrel-jack supplies, the rating can be
 			 * exceeded briefly, so use the average.
 			 */
-			if (charge_manager_get_supplier() ==
-			    CHARGE_SUPPLIER_PD)
+			if (charge_manager_get_supplier() == CHARGE_SUPPLIER_PD)
 				power = max;
 			else
 				power = total / POWER_READINGS;
@@ -959,8 +939,9 @@ static void power_monitor(void)
 		gpio_set_level(GPIO_EC_PROCHOT_ODL, prochot);
 	}
 	if (diff & THROT_TYPE_C) {
-		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C)
-			? TYPEC_RP_1A5 : TYPEC_RP_3A0;
+		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C) ?
+						TYPEC_RP_1A5 :
+						TYPEC_RP_3A0;
 
 		ppc_set_vbus_source_current_limit(0, rp);
 		tcpm_select_rp_value(0, rp);
diff --git a/board/ambassador/board.h b/board/ambassador/board.h
index c6aac262c5..fb9659bda7 100644
--- a/board/ambassador/board.h
+++ b/board/ambassador/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,8 +12,8 @@
 #define CONFIG_UART_TX_BUF_SIZE 4096
 
 /* NPCX7 config */
-#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
-#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
+#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */
+#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */
 
 /* Internal SPI flash on NPCX796FC is 512 kB */
 #define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
@@ -40,7 +40,7 @@
 #undef CONFIG_HIBERNATE
 #define CONFIG_HOST_INTERFACE_ESPI
 #define CONFIG_LED_COMMON
-#undef  CONFIG_LID_SWITCH
+#undef CONFIG_LID_SWITCH
 #define CONFIG_LTO
 #define CONFIG_PWM
 #define CONFIG_VBOOT_EFS2
@@ -85,7 +85,7 @@
 #define CONFIG_CPU_PROCHOT_ACTIVE_LOW
 
 /* Dedicated barreljack charger port */
-#undef  CONFIG_DEDICATED_CHARGE_PORT_COUNT
+#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT
 #define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1
 #define DEDICATED_CHARGE_PORT 1
 
@@ -104,15 +104,15 @@
 #define CONFIG_INA3221
 
 /* b/143501304 */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	4000	/* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	2000	/* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 4000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 2000 /* us */
 #undef CONFIG_USBC_VCONN_SWAP_DELAY_US
-#define CONFIG_USBC_VCONN_SWAP_DELAY_US		8000	/* us */
+#define CONFIG_USBC_VCONN_SWAP_DELAY_US 8000 /* us */
 
-#define PD_OPERATING_POWER_MW	CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
-#define PD_MAX_POWER_MW		100000
-#define PD_MAX_CURRENT_MA	5000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
+#define PD_MAX_POWER_MW 100000
+#define PD_MAX_CURRENT_MA 5000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Fan and temp. */
 #define CONFIG_FANS 1
@@ -136,7 +136,7 @@
 #define CONFIG_USB_PD_DECODE_SOP
 #undef CONFIG_USB_CHARGER
 #define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PID		0x5040
+#define CONFIG_USB_PID 0x5040
 #define CONFIG_USB_PD_ALT_MODE
 #define CONFIG_USB_PD_ALT_MODE_DFP
 #define CONFIG_USB_PD_DISCHARGE_PPC
@@ -156,7 +156,7 @@
 #define CONFIG_USBC_VCONN
 #define CONFIG_USBC_VCONN_SWAP
 
-#define USB_PD_PORT_TCPC_0	0
+#define USB_PD_PORT_TCPC_0 0
 #define BOARD_TCPC_C0_RESET_HOLD_DELAY ANX74XX_RESET_HOLD_MS
 #define BOARD_TCPC_C0_RESET_POST_DELAY ANX74XX_RESET_HOLD_MS
 
@@ -168,12 +168,12 @@
 /* I2C Bus Configuration */
 #define CONFIG_I2C
 #define CONFIG_I2C_CONTROLLER
-#define I2C_PORT_INA		NPCX_I2C_PORT0_0
-#define I2C_PORT_PPC0		NPCX_I2C_PORT1_0
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT3_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_PORT_INA NPCX_I2C_PORT0_0
+#define I2C_PORT_PPC0 NPCX_I2C_PORT1_0
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT3_0
+#define I2C_PORT_POWER NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 
 #define PP5000_PGOOD_POWER_SIGNAL_MASK POWER_SIGNAL_MASK(PP5000_A_PGOOD)
 
@@ -191,11 +191,11 @@ enum charge_port {
 };
 
 enum adc_channel {
-	ADC_SNS_PP3300,     /* ADC2 */
-	ADC_SNS_PP1050,     /* ADC7 */
-	ADC_VBUS,           /* ADC4 */
-	ADC_PPVAR_IMON,     /* ADC9 */
-	ADC_TEMP_SENSOR_1,  /* ADC0 */
+	ADC_SNS_PP3300, /* ADC2 */
+	ADC_SNS_PP1050, /* ADC7 */
+	ADC_VBUS, /* ADC4 */
+	ADC_PPVAR_IMON, /* ADC9 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
 	/* Number of ADC channels */
 	ADC_CH_COUNT
 };
@@ -220,11 +220,7 @@ enum mft_channel {
 	MFT_CH_COUNT,
 };
 
-enum temp_sensor_id {
-	TEMP_SENSOR_CORE,
-	TEMP_SENSOR_COUNT
-};
-
+enum temp_sensor_id { TEMP_SENSOR_CORE, TEMP_SENSOR_COUNT };
 
 /* Board specific handlers */
 void board_reset_pd_mcu(void);
@@ -238,20 +234,20 @@ void show_critical_error(void);
 /*
  * Barrel-jack power (4 bits).
  */
-#define EC_CFG_BJ_POWER_L		0
-#define EC_CFG_BJ_POWER_H		3
+#define EC_CFG_BJ_POWER_L 0
+#define EC_CFG_BJ_POWER_H 3
 #define EC_CFG_BJ_POWER_MASK GENMASK(EC_CFG_BJ_POWER_H, EC_CFG_BJ_POWER_L)
 /*
  * USB Connector 4 not present (1 bit).
  */
-#define EC_CFG_NO_USB4_L		4
-#define EC_CFG_NO_USB4_H		4
+#define EC_CFG_NO_USB4_L 4
+#define EC_CFG_NO_USB4_H 4
 #define EC_CFG_NO_USB4_MASK GENMASK(EC_CFG_NO_USB4_H, EC_CFG_NO_USB4_L)
 /*
  * Thermal solution config (3 bits).
  */
-#define EC_CFG_THERMAL_L		5
-#define EC_CFG_THERMAL_H		7
+#define EC_CFG_THERMAL_L 5
+#define EC_CFG_THERMAL_H 7
 #define EC_CFG_THERMAL_MASK GENMASK(EC_CFG_THERMAL_H, EC_CFG_THERMAL_L)
 
 unsigned int ec_config_get_bj_power(void);
@@ -261,30 +257,30 @@ unsigned int ec_config_get_thermal_solution(void);
 #endif /* !__ASSEMBLER__ */
 
 /* Pin renaming */
-#define GPIO_WP_L               GPIO_EC_WP_ODL
-#define GPIO_PP5000_A_PG_OD     GPIO_PG_PP5000_A_OD
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
-#define GPIO_RECOVERY_L         GPIO_EC_RECOVERY_BTN_ODL
-#define GPIO_RECOVERY_L_2       GPIO_H1_EC_RECOVERY_BTN_ODL
-#define GPIO_POWER_BUTTON_L	GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_PCH_WAKE_L		GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L	GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_ENTERING_RW	GPIO_EC_ENTERING_RW
-#define GPIO_SYS_RESET_L	GPIO_SYS_RST_ODL
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_PCH_RTCRST		GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_TEMP_SENSOR_POWER	GPIO_EN_ROA_RAILS
-#define GPIO_AC_PRESENT		GPIO_BJ_ADP_PRESENT_L
+#define GPIO_WP_L GPIO_EC_WP_ODL
+#define GPIO_PP5000_A_PG_OD GPIO_PG_PP5000_A_OD
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
+#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_ODL
+#define GPIO_RECOVERY_L_2 GPIO_H1_EC_RECOVERY_BTN_ODL
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_EN_ROA_RAILS
+#define GPIO_AC_PRESENT GPIO_BJ_ADP_PRESENT_L
 
 /*
  * There is no RSMRST input, so alias it to the output. This short-circuits
  * common_intel_x86_handle_rsmrst.
  */
-#define GPIO_PG_EC_RSMRST_ODL	GPIO_PCH_RSMRST_L
+#define GPIO_PG_EC_RSMRST_ODL GPIO_PCH_RSMRST_L
 
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/ambassador/build.mk b/board/ambassador/build.mk
index 0f55c45f77..f9096c64ff 100644
--- a/board/ambassador/build.mk
+++ b/board/ambassador/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/ambassador/ec.tasklist b/board/ambassador/ec.tasklist
index f820cf903c..42b9542d96 100644
--- a/board/ambassador/ec.tasklist
+++ b/board/ambassador/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/ambassador/gpio.inc b/board/ambassador/gpio.inc
index 871031ebf9..46b6118ce2 100644
--- a/board/ambassador/gpio.inc
+++ b/board/ambassador/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,12 +25,12 @@ GPIO_INT(PG_VPRIM_CORE_A_OD,   PIN(2, 3), GPIO_INT_BOTH, power_signal_interrupt)
 GPIO_INT(PG_PP1050_A_OD,       PIN(2, 2), GPIO_INT_BOTH, power_signal_interrupt)
 /* EC output, but also interrupt so this can be polled as a power signal */
 GPIO_INT(EC_PCH_RSMRST_L,      PIN(A, 6), GPIO_OUTPUT | GPIO_INT_F_RISING | GPIO_INT_F_FALLING, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(PG_PP2500_DRAM_U_OD,  PIN(2, 0), GPIO_INT_BOTH, power_signal_interrupt)
 GPIO_INT(PG_PP1200_U_OD,       PIN(2, 1), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, slp_s3_interrupt)
 #endif
 GPIO_INT(PG_PP950_VCCIO_OD,    PIN(1, 7), GPIO_INT_BOTH, power_signal_interrupt)
diff --git a/board/ambassador/led.c b/board/ambassador/led.c
index 659a63a483..3baf867580 100644
--- a/board/ambassador/led.c
+++ b/board/ambassador/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,16 +19,16 @@
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
 
 /*
  * Due to the CSME-Lite processing, upon startup the CPU transitions through
  * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so
  * delay turning off the LED during suspend/shutdown.
  */
-#define LED_CPU_DELAY_MS	(2000 * MSEC)
+#define LED_CPU_DELAY_MS (2000 * MSEC)
 
-const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 enum led_color {
@@ -89,9 +89,9 @@ static int set_color(enum ec_led_id id, enum led_color color, int duty)
 	}
 }
 
-#define LED_PULSE_US		(2 * SECOND)
+#define LED_PULSE_US (2 * SECOND)
 /* 40 msec for nice and smooth transition. */
-#define LED_PULSE_TICK_US	(40 * MSEC)
+#define LED_PULSE_TICK_US (40 * MSEC)
 
 /* When pulsing is enabled, brightness is incremented by <duty_inc> every
  * <interval> usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented
@@ -216,7 +216,7 @@ void show_critical_error(void)
 		set_color(EC_LED_ID_POWER_LED, LED_RED, 100);
 }
 
-static int command_led(int argc, char **argv)
+static int command_led(int argc, const char **argv)
 {
 	enum ec_led_id id = EC_LED_ID_POWER_LED;
 
diff --git a/board/ambassador/usb_pd_policy.c b/board/ambassador/usb_pd_policy.c
index 5bc754453a..fbb4edf23e 100644
--- a/board/ambassador/usb_pd_policy.c
+++ b/board/ambassador/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,9 +19,8 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
diff --git a/board/ampton/battery.c b/board/ampton/battery.c
index f52f0d5d7a..18bf4e591a 100644
--- a/board/ampton/battery.c
+++ b/board/ampton/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/ampton/board.c b/board/ampton/board.c
index 3e7bee1993..f1346a6b07 100644
--- a/board/ampton/board.c
+++ b/board/ampton/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -65,8 +65,8 @@ int ppc_get_alert_status(int port)
 /******************************************************************************/
 /* USB-C MUX Configuration */
 
-#define USB_PD_PORT_ITE_0      0
-#define USB_PD_PORT_ITE_1      1
+#define USB_PD_PORT_ITE_0 0
+#define USB_PD_PORT_ITE_1 1
 
 static int tune_mux(const struct usb_mux *me);
 
@@ -101,8 +101,8 @@ static int tune_mux(const struct usb_mux *me)
 	/* Auto EQ disabled, compensate for channel lost up to 3.6dB */
 	RETURN_ERROR(mux_write(me, PS8XXX_REG_MUX_DP_EQ_CONFIGURATION, 0x98));
 	/* DP output swing adjustment +15% */
-	RETURN_ERROR(mux_write(me, PS8XXX_REG_MUX_DP_OUTPUT_CONFIGURATION,
-			       0xc0));
+	RETURN_ERROR(
+		mux_write(me, PS8XXX_REG_MUX_DP_OUTPUT_CONFIGURATION, 0xc0));
 
 	return EC_SUCCESS;
 }
@@ -110,44 +110,44 @@ static int tune_mux(const struct usb_mux *me)
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* Vbus C0 sensing (10x voltage divider). PPVAR_USB_C0_VBUS */
-	[ADC_VBUS_C0] = {.name = "VBUS_C0",
-			 .factor_mul = 10 * ADC_MAX_MVOLT,
-			 .factor_div = ADC_READ_MAX + 1,
-			 .shift = 0,
-			 .channel = CHIP_ADC_CH13},
+	[ADC_VBUS_C0] = { .name = "VBUS_C0",
+			  .factor_mul = 10 * ADC_MAX_MVOLT,
+			  .factor_div = ADC_READ_MAX + 1,
+			  .shift = 0,
+			  .channel = CHIP_ADC_CH13 },
 	/* Vbus C1 sensing (10x voltage divider). SUB_EC_ADC */
-	[ADC_VBUS_C1] = {.name = "VBUS_C1",
-			 .factor_mul = 10 * ADC_MAX_MVOLT,
-			 .factor_div = ADC_READ_MAX + 1,
-			 .shift = 0,
-			 .channel = CHIP_ADC_CH14},
+	[ADC_VBUS_C1] = { .name = "VBUS_C1",
+			  .factor_mul = 10 * ADC_MAX_MVOLT,
+			  .factor_div = ADC_READ_MAX + 1,
+			  .shift = 0,
+			  .channel = CHIP_ADC_CH14 },
 	/* Convert to raw mV for thermistor table lookup */
-	[ADC_TEMP_SENSOR_AMB] = {.name = "TEMP_AMB",
-			 .factor_mul = ADC_MAX_MVOLT,
-			 .factor_div = ADC_READ_MAX + 1,
-			 .shift = 0,
-			 .channel = CHIP_ADC_CH3},
+	[ADC_TEMP_SENSOR_AMB] = { .name = "TEMP_AMB",
+				  .factor_mul = ADC_MAX_MVOLT,
+				  .factor_div = ADC_READ_MAX + 1,
+				  .shift = 0,
+				  .channel = CHIP_ADC_CH3 },
 	/* Convert to raw mV for thermistor table lookup */
-	[ADC_TEMP_SENSOR_CHARGER] = {.name = "TEMP_CHARGER",
-			 .factor_mul = ADC_MAX_MVOLT,
-			 .factor_div = ADC_READ_MAX + 1,
-			 .shift = 0,
-			 .channel = CHIP_ADC_CH5},
+	[ADC_TEMP_SENSOR_CHARGER] = { .name = "TEMP_CHARGER",
+				      .factor_mul = ADC_MAX_MVOLT,
+				      .factor_div = ADC_READ_MAX + 1,
+				      .shift = 0,
+				      .channel = CHIP_ADC_CH5 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
+	[TEMP_SENSOR_BATTERY] = { .name = "Battery",
+				  .type = TEMP_SENSOR_TYPE_BATTERY,
+				  .read = charge_get_battery_temp },
+	[TEMP_SENSOR_AMBIENT] = { .name = "Ambient",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_51k1_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_AMB },
+	[TEMP_SENSOR_CHARGER] = { .name = "Charger",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_13k7_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_CHARGER },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -156,35 +156,25 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
-const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+				      { FLOAT_TO_FP(1), 0, 0 },
+				      { 0, 0, FLOAT_TO_FP(1) } };
 
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+				       { FLOAT_TO_FP(1), 0, 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
 
-const mat33_fp_t gyro_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t gyro_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+				       { FLOAT_TO_FP(1), 0, 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
 
-const mat33_fp_t base_standard_ref_icm42607 = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t base_standard_ref_icm42607 = { { 0, FLOAT_TO_FP(1), 0 },
+						{ FLOAT_TO_FP(1), 0, 0 },
+						{ 0, 0, FLOAT_TO_FP(-1) } };
 
-const mat33_fp_t lid_standard_ref_sku57 = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t lid_standard_ref_sku57 = { { FLOAT_TO_FP(1), 0, 0 },
+					    { 0, FLOAT_TO_FP(-1), 0 },
+					    { 0, 0, FLOAT_TO_FP(-1) } };
 /* sensor private data */
 static struct kionix_accel_data g_kx022_data;
 static struct bmi_drv_data_t g_bmi160_data;
@@ -355,9 +345,9 @@ unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 static int board_is_convertible(void)
 {
 	/* SKU IDs of Ampton & unprovisioned: 1, 2, 3, 4, 255 */
-	return sku_id == 1 || sku_id == 2 || sku_id == 3 || sku_id == 4
-		|| sku_id == 57 || sku_id == 255;
-	}
+	return sku_id == 1 || sku_id == 2 || sku_id == 3 || sku_id == 4 ||
+	       sku_id == 57 || sku_id == 255;
+}
 
 static int board_with_sensor_bma253(void)
 {
@@ -389,13 +379,12 @@ static void board_update_sensor_config_from_sku(void)
 		if (board_with_sensor_icm42607()) {
 			motion_sensors[BASE_ACCEL] =
 				motion_sensor_accel_icm42607;
-			motion_sensors[BASE_GYRO] =
-				motion_sensor_gyro_icm42607;
+			motion_sensors[BASE_GYRO] = motion_sensor_gyro_icm42607;
 			ccprints("Gyro sensor: ICM-42607");
 		}
 		if (sku_id == 57)
 			motion_sensors[LID_ACCEL].rot_standard_ref =
-					&lid_standard_ref_sku57;
+				&lid_standard_ref_sku57;
 
 		/* Enable Base Accel interrupt */
 		gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
diff --git a/board/ampton/board.h b/board/ampton/board.h
index d0a3cf5bc0..4a00f82cd2 100644
--- a/board/ampton/board.h
+++ b/board/ampton/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,7 @@
 #define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD
 
 /* I2C bus configuraiton */
-#define I2C_PORT_ACCEL	I2C_PORT_SENSOR
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
 
 /* EC console commands  */
 #define CONFIG_CMD_ACCELS
@@ -28,7 +28,7 @@
 
 #define CONFIG_LED_COMMON
 
-#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV	5000
+#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV 5000
 
 /* Sensors */
 #define CONFIG_TEMP_SENSOR
@@ -38,11 +38,11 @@
 #define CONFIG_TEMP_SENSOR_POWER
 #define GPIO_TEMP_SENSOR_POWER GPIO_EN_PP3300
 
-#define CONFIG_ACCEL_BMA255	/* Lid accel */
-#define CONFIG_ACCEL_KX022	/* Lid accel */
-#define CONFIG_ACCELGYRO_BMI160	/* Base accel */
+#define CONFIG_ACCEL_BMA255 /* Lid accel */
+#define CONFIG_ACCEL_KX022 /* Lid accel */
+#define CONFIG_ACCELGYRO_BMI160 /* Base accel */
 #define CONFIG_ACCELGYRO_ICM42607 /* Base accel */
-#define CONFIG_SYNC		/* Camera VSYNC */
+#define CONFIG_SYNC /* Camera VSYNC */
 
 #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
 /* Sensors without hardware FIFO are in forced mode */
@@ -57,8 +57,7 @@
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 #define CONFIG_ACCELGYRO_ICM42607_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_SYNC_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
+#define CONFIG_SYNC_INT_EVENT TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
 
 /* Keyboard backlight is unimplemented in hardware */
 #undef CONFIG_PWM
@@ -90,13 +89,7 @@ enum temp_sensor_id {
 };
 
 /* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	VSYNC,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, VSYNC, SENSOR_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
diff --git a/board/ampton/build.mk b/board/ampton/build.mk
index cc6b73093e..daf4529f19 100644
--- a/board/ampton/build.mk
+++ b/board/ampton/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/ampton/ec.tasklist b/board/ampton/ec.tasklist
index 2703dd0b5c..466dd4c60f 100644
--- a/board/ampton/ec.tasklist
+++ b/board/ampton/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/ampton/gpio.inc b/board/ampton/gpio.inc
index 854a28655d..c1d7769668 100644
--- a/board/ampton/gpio.inc
+++ b/board/ampton/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/ampton/led.c b/board/ampton/led.c
index 40b0acdd9c..02bafec4e0 100644
--- a/board/ampton/led.c
+++ b/board/ampton/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,8 +10,8 @@
 #include "led_common.h"
 #include "led_onoff_states.h"
 
-#define LED_OFF_LVL	0
-#define LED_ON_LVL	1
+#define LED_OFF_LVL 0
+#define LED_ON_LVL 1
 
 __override const int led_charge_lvl_1;
 
@@ -19,19 +19,27 @@ __override const int led_charge_lvl_2 = 94;
 
 /* Ampton: Note there is only LED for charge / power */
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]       = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 BUILD_ASSERT(ARRAY_SIZE(led_bat_state_table) == LED_NUM_STATES);
 
 const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
diff --git a/board/anahera/battery.c b/board/anahera/battery.c
index 95ca9be206..f7b0b6f43f 100644
--- a/board/anahera/battery.c
+++ b/board/anahera/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/anahera/board.c b/board/anahera/board.c
index b7110951ce..e087d629a7 100644
--- a/board/anahera/board.c
+++ b/board/anahera/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -28,8 +28,8 @@
 #include "gpio_list.h" /* Must come after other header files. */
 
 /* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 /******************************************************************************/
 /* USB-A charging control */
@@ -66,14 +66,13 @@ enum battery_present battery_hw_present(void)
 }
 
 __override void board_set_charge_limit(int port, int supplier, int charge_ma,
-					  int max_ma, int charge_mv)
+				       int max_ma, int charge_mv)
 {
 	/*
 	 * Limit the input current to 95% negotiated limit,
 	 * to account for the charger chip margin.
 	 */
 	charge_ma = charge_ma * 95 / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
diff --git a/board/anahera/board.h b/board/anahera/board.h
index 4730eba213..18360171e3 100644
--- a/board/anahera/board.h
+++ b/board/anahera/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -29,7 +29,7 @@
 #undef CONFIG_VOLUME_BUTTONS
 
 /* USB Type A Features */
-#define USB_PORT_COUNT			1
+#define USB_PORT_COUNT 1
 #define CONFIG_USB_PORT_POWER_DUMB
 #define CONFIG_USBC_RETIMER_PS8811
 
@@ -38,7 +38,7 @@
 
 #define CONFIG_IO_EXPANDER
 #define CONFIG_IO_EXPANDER_NCT38XX
-#define CONFIG_IO_EXPANDER_PORT_COUNT		2
+#define CONFIG_IO_EXPANDER_PORT_COUNT 2
 
 #define CONFIG_USB_PD_FRS_PPC
 
@@ -48,17 +48,17 @@
 #define CONFIG_USBC_PPC_NX20P3483
 
 /* TODO: b/193452481 - measure and check these values on redrix */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
 
 /*
  * Passive USB-C cables only support up to 60W.
  */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /*
  * Macros for GPIO signals used in common code that don't match the
@@ -66,64 +66,64 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT		GPIO_EC_EN_EDP_BL
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_GSC_PACKET_MODE
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SYS_SLP_S0IX_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_TEMP_SENSOR_POWER		GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
 
 /*
  * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
  * signal.
  */
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_SEQ_EC_ALL_SYS_PG
-#define GPIO_PG_EC_DSW_PWROK		GPIO_SEQ_EC_DSW_PWROK
-#define GPIO_PG_EC_RSMRST_ODL		GPIO_SEQ_EC_RSMRST_ODL
-#define GPIO_POWER_BUTTON_L		GPIO_GSC_EC_PWR_BTN_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_ODL
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
 
 /* System has back-lit keyboard */
 #define CONFIG_PWM_KBLIGHT
 
 /* I2C Bus Configuration */
-#define I2C_PORT_USB_C0_TCPC	NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1_TCPC	NPCX_I2C_PORT4_1
+#define I2C_PORT_USB_C0_TCPC NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1
 
-#define I2C_PORT_USB_C0_PPC	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_PPC	NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C0_PPC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1
 
-#define I2C_PORT_USB_C0_BC12	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_BC12	NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C0_BC12 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1
 
-#define I2C_PORT_USB_C0_MUX	NPCX_I2C_PORT3_0
-#define I2C_PORT_USB_C1_MUX	NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C0_MUX NPCX_I2C_PORT3_0
+#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1
 
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT5_0
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT7_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
 
-#define I2C_PORT_USB_A0_RETIMER	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_A1_RETIMER	NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_A0_RETIMER NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_A1_RETIMER NPCX_I2C_PORT6_1
 
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 
 /*
  * see b/174768555#comment22
  */
-#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR	0x56
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x58
+#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x56
+#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x58
 
 /* Enabling Thunderbolt-compatible mode */
 #define CONFIG_USB_PD_TBT_COMPAT_MODE
@@ -141,17 +141,17 @@
 #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
 
 /* Fan features */
-#define CONFIG_FANS		FAN_CH_COUNT
+#define CONFIG_FANS FAN_CH_COUNT
 #define CONFIG_CUSTOM_FAN_CONTROL
-#define RPM_DEVIATION	1
+#define RPM_DEVIATION 1
 
 /* Charger defines */
 #define CONFIG_CHARGER_BQ25720
 #define CONFIG_CHARGER_BQ25720_VSYS_TH2_CUSTOM
-#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV	70
+#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV 70
 #define CONFIG_CHARGE_RAMP_HW
-#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10
 
 /* Keyboard features */
 #define CONFIG_KEYBOARD_FACTORY_TEST
@@ -160,7 +160,7 @@
 
 #ifndef __ASSEMBLER__
 
-#include "gpio_signal.h"	/* needed by registers.h */
+#include "gpio_signal.h" /* needed by registers.h */
 #include "registers.h"
 #include "usbc_config.h"
 
@@ -180,11 +180,7 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum ioex_port {
-	IOEX_C0_NCT38XX = 0,
-	IOEX_C1_NCT38XX,
-	IOEX_PORT_COUNT
-};
+enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_C1_NCT38XX, IOEX_PORT_COUNT };
 
 enum battery_type {
 	BATTERY_SIMPLO_HIGHPOWER,
@@ -193,20 +189,14 @@ enum battery_type {
 };
 
 enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,		/* PWM3 */
-	PWM_CH_FAN,			/* PWM5 */
+	PWM_CH_KBLIGHT = 0, /* PWM3 */
+	PWM_CH_FAN, /* PWM5 */
 	PWM_CH_COUNT
 };
 
-enum fan_channel {
-	FAN_CH_0 = 0,
-	FAN_CH_COUNT
-};
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT };
 
-enum mft_channel {
-	MFT_CH_0 = 0,
-	MFT_CH_COUNT
-};
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT };
 
 #ifdef CONFIG_KEYBOARD_FACTORY_TEST
 extern const int keyboard_factory_scan_pins[][2];
diff --git a/board/anahera/build.mk b/board/anahera/build.mk
index b3aef429a6..dda59fdd82 100644
--- a/board/anahera/build.mk
+++ b/board/anahera/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/anahera/charger.c b/board/anahera/charger.c
index 476ce97df2..a4fa209246 120000..100644
--- a/board/anahera/charger.c
+++ b/board/anahera/charger.c
@@ -1 +1,90 @@
-../../baseboard/brya/charger_bq25720.c
\ No newline at end of file
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+
+#include "charge_manager.h"
+#include "charge_state_v2.h"
+#include "charger.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/charger/bq25710.h"
+#include "usbc_ppc.h"
+#include "usb_pd.h"
+#include "util.h"
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+#ifndef CONFIG_ZEPHYR
+/* Charger Chip Configuration */
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = BQ25710_SMBUS_ADDR1_FLAGS,
+		.drv = &bq25710_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CHARGER_NUM);
+#endif
+
+int board_set_active_charge_port(int port)
+{
+	int is_valid_port = board_is_usb_pd_port_present(port);
+	int i;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTSUSB("Disabling all charger ports");
+
+		/* Disable all ports. */
+		for (i = 0; i < ppc_cnt; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (ppc_vbus_sink_enable(i, 0))
+				CPRINTSUSB("Disabling C%d as sink failed.", i);
+		}
+
+		return EC_SUCCESS;
+	} else if (!is_valid_port) {
+		return EC_ERROR_INVAL;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (ppc_is_sourcing_vbus(port)) {
+		CPRINTFUSB("Skip enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTSUSB("New charge port: C%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < ppc_cnt; i++) {
+		if (i == port)
+			continue;
+
+		if (ppc_vbus_sink_enable(i, 0))
+			CPRINTSUSB("C%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTSUSB("C%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+__overridable void board_set_charge_limit(int port, int supplier, int charge_ma,
+					  int max_ma, int charge_mv)
+{
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+}
diff --git a/board/anahera/ec.tasklist b/board/anahera/ec.tasklist
index 187609f36e..ebbfd239f9 100644
--- a/board/anahera/ec.tasklist
+++ b/board/anahera/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/anahera/fans.c b/board/anahera/fans.c
index 61671fd0a7..7d08701dc0 100644
--- a/board/anahera/fans.c
+++ b/board/anahera/fans.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,7 +25,7 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 static const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
diff --git a/board/anahera/fw_config.c b/board/anahera/fw_config.c
index 3c64f055f6..6073384f53 100644
--- a/board/anahera/fw_config.c
+++ b/board/anahera/fw_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,7 +9,7 @@
 #include "cros_board_info.h"
 #include "fw_config.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 static union anahera_cbi_fw_config fw_config;
 BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
diff --git a/board/anahera/fw_config.h b/board/anahera/fw_config.h
index 92bc9e55e7..32787c1e4f 100644
--- a/board/anahera/fw_config.h
+++ b/board/anahera/fw_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,10 +19,7 @@ enum ec_cfg_keyboard_backlight_type {
 	KEYBOARD_BACKLIGHT_ENABLED = 1
 };
 
-enum ec_cfg_eps_type {
-	EPS_DISABLED = 0,
-	EPS_ENABLED = 1
-};
+enum ec_cfg_eps_type { EPS_DISABLED = 0, EPS_ENABLED = 1 };
 
 enum ec_cfg_ite_type {
 	LTE_NOT_PRESENT = 0,
@@ -31,14 +28,14 @@ enum ec_cfg_ite_type {
 
 union anahera_cbi_fw_config {
 	struct {
-		uint32_t				sd_db : 2;
-		enum ec_cfg_keyboard_backlight_type	kb_bl : 1;
-		uint32_t				audio : 3;
-		enum ec_cfg_ite_type			lte_db : 2;
-		uint32_t				ufc : 2;
-		enum ec_cfg_eps_type			eps : 1;
-		uint32_t				boot_device : 2;
-		uint32_t				reserved_1 : 19;
+		uint32_t sd_db : 2;
+		enum ec_cfg_keyboard_backlight_type kb_bl : 1;
+		uint32_t audio : 3;
+		enum ec_cfg_ite_type lte_db : 2;
+		uint32_t ufc : 2;
+		enum ec_cfg_eps_type eps : 1;
+		uint32_t boot_device : 2;
+		uint32_t reserved_1 : 19;
 	};
 	uint32_t raw_value;
 };
diff --git a/board/anahera/gpio.inc b/board/anahera/gpio.inc
index 794e8750b4..5cce74abff 100644
--- a/board/anahera/gpio.inc
+++ b/board/anahera/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/anahera/i2c.c b/board/anahera/i2c.c
index 7748066514..7e7993b4d5 100644
--- a/board/anahera/i2c.c
+++ b/board/anahera/i2c.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/anahera/keyboard.c b/board/anahera/keyboard.c
index 782ba0d0db..8588191460 100644
--- a/board/anahera/keyboard.c
+++ b/board/anahera/keyboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -154,13 +154,13 @@ board_vivaldi_keybd_config(void)
  * The connector has 24 pins total, and there is no pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-		{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-		{0, 7}, {1, 4}, {1, 3}, {1, 6}, {1, 7},
-		{3, 1}, {2, 0}, {1, 5}, {2, 6}, {2, 7},
-		{2, 1}, {2, 4}, {2, 5}, {1, 2}, {2, 3},
-		{2, 2}, {3, 0}, {-1, -1}, {-1, -1}, {-1, -1},
+	{ -1, -1 }, { 0, 5 }, { 1, 1 },	  { 1, 0 },   { 0, 6 },
+	{ 0, 7 },   { 1, 4 }, { 1, 3 },	  { 1, 6 },   { 1, 7 },
+	{ 3, 1 },   { 2, 0 }, { 1, 5 },	  { 2, 6 },   { 2, 7 },
+	{ 2, 1 },   { 2, 4 }, { 2, 5 },	  { 1, 2 },   { 2, 3 },
+	{ 2, 2 },   { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 },
 };
 
 const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 #endif
diff --git a/board/anahera/led.c b/board/anahera/led.c
index ce172c7b1e..d7a3d07efc 100644
--- a/board/anahera/led.c
+++ b/board/anahera/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -26,15 +26,13 @@
 #define BATT_LOW_BCT 10
 
 #define LED_TICK_INTERVAL_MS (500 * MSEC)
-#define LED_CYCLE_TIME_MS    (2000 * MSEC)
-#define LED_TICKS_PER_CYCLE  (LED_CYCLE_TIME_MS / LED_TICK_INTERVAL_MS)
-#define LED_ON_TIME_MS       (1000 * MSEC)
-#define LED_ON_TICKS         (LED_ON_TIME_MS / LED_TICK_INTERVAL_MS)
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_LEFT_LED,
-	EC_LED_ID_RIGHT_LED
-};
+#define LED_CYCLE_TIME_MS (2000 * MSEC)
+#define LED_TICKS_PER_CYCLE (LED_CYCLE_TIME_MS / LED_TICK_INTERVAL_MS)
+#define LED_ON_TIME_MS (1000 * MSEC)
+#define LED_ON_TICKS (LED_ON_TIME_MS / LED_TICK_INTERVAL_MS)
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_LEFT_LED,
+					     EC_LED_ID_RIGHT_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -42,22 +40,19 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
-enum led_port {
-	LEFT_PORT = 0,
-	RIGHT_PORT
-};
+enum led_port { LEFT_PORT = 0, RIGHT_PORT };
 
 static void led_set_color_battery(int port, enum led_color color)
 {
 	enum gpio_signal amber_led, white_led;
 
 	amber_led = (port == RIGHT_PORT ? GPIO_C1_CHARGE_LED_AMBER_L :
-				 GPIO_C0_CHARGE_LED_AMBER_L);
+					  GPIO_C0_CHARGE_LED_AMBER_L);
 	white_led = (port == RIGHT_PORT ? GPIO_C1_CHARGE_LED_WHITE_L :
-				 GPIO_C0_CHARGE_LED_WHITE_L);
+					  GPIO_C0_CHARGE_LED_WHITE_L);
 
 	switch (color) {
 	case LED_WHITE:
@@ -129,18 +124,16 @@ static void set_active_port_color(enum led_color color)
 
 	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
 		led_set_color_battery(RIGHT_PORT,
-				(port == RIGHT_PORT) ? color : LED_OFF);
+				      (port == RIGHT_PORT) ? color : LED_OFF);
 	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
 		led_set_color_battery(LEFT_PORT,
-				(port == LEFT_PORT) ? color : LED_OFF);
+				      (port == LEFT_PORT) ? color : LED_OFF);
 }
 
 static void led_set_battery(void)
 {
 	static unsigned int battery_ticks;
 
-	uint32_t chflags = charge_get_flags();
-
 	battery_ticks++;
 
 	switch (charge_get_state()) {
@@ -155,43 +148,52 @@ static void led_set_battery(void)
 		 */
 		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
 			if (charge_get_percent() < BATT_LOW_BCT)
-				led_set_color_battery(RIGHT_PORT,
-					(battery_ticks % LED_TICKS_PER_CYCLE
-					 < LED_ON_TICKS) ? LED_AMBER : LED_OFF);
+				led_set_color_battery(
+					RIGHT_PORT,
+					(battery_ticks % LED_TICKS_PER_CYCLE <
+					 LED_ON_TICKS) ?
+						LED_AMBER :
+						LED_OFF);
 			else
 				led_set_color_battery(RIGHT_PORT, LED_OFF);
 		}
 
 		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) {
 			if (charge_get_percent() < BATT_LOW_BCT)
-				led_set_color_battery(LEFT_PORT,
-					(battery_ticks % LED_TICKS_PER_CYCLE
-					 < LED_ON_TICKS) ? LED_AMBER : LED_OFF);
+				led_set_color_battery(
+					LEFT_PORT,
+					(battery_ticks % LED_TICKS_PER_CYCLE <
+					 LED_ON_TICKS) ?
+						LED_AMBER :
+						LED_OFF);
 			else
 				led_set_color_battery(LEFT_PORT, LED_OFF);
 		}
 		break;
 	case PWR_STATE_ERROR:
 		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
-			led_set_color_battery(RIGHT_PORT, (battery_ticks & 0x1)
-				? LED_AMBER : LED_OFF);
+			led_set_color_battery(
+				RIGHT_PORT,
+				(battery_ticks & 0x1) ? LED_AMBER : LED_OFF);
 		}
 
 		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) {
-			led_set_color_battery(LEFT_PORT, (battery_ticks & 0x1)
-				? LED_AMBER : LED_OFF);
+			led_set_color_battery(LEFT_PORT, (battery_ticks & 0x1) ?
+								 LED_AMBER :
+								 LED_OFF);
 		}
 		break;
 	case PWR_STATE_CHARGE_NEAR_FULL:
 		set_active_port_color(LED_WHITE);
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			set_active_port_color((battery_ticks %
-				LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-				LED_AMBER : LED_OFF);
-		else
-			set_active_port_color(LED_WHITE);
+		set_active_port_color(LED_WHITE);
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		set_active_port_color(
+			(battery_ticks % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
+				LED_AMBER :
+				LED_OFF);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
diff --git a/board/anahera/pwm.c b/board/anahera/pwm.c
index 54d0d05afb..b242683306 100644
--- a/board/anahera/pwm.c
+++ b/board/anahera/pwm.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/anahera/sensors.c b/board/anahera/sensors.c
index 851930d1d3..05d9a9080b 100644
--- a/board/anahera/sensors.c
+++ b/board/anahera/sensors.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -44,38 +44,30 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* Temperature sensor configuration */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1_FAN] = {
-		.name = "Fan",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_1_FAN
-	},
-	[TEMP_SENSOR_2_SOC] = {
-		.name = "SOC",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_2_SOC
-	},
-	[TEMP_SENSOR_3_CHARGER] = {
-		.name = "Charger",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_3_CHARGER
-	},
-	[TEMP_SENSOR_4_REGULATOR] = {
-		.name = "Regulator",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_4_REGULATOR
-	},
+	[TEMP_SENSOR_1_FAN] = { .name = "Fan",
+				.type = TEMP_SENSOR_TYPE_BOARD,
+				.read = get_temp_3v3_30k9_47k_4050b,
+				.idx = ADC_TEMP_SENSOR_1_FAN },
+	[TEMP_SENSOR_2_SOC] = { .name = "SOC",
+				.type = TEMP_SENSOR_TYPE_BOARD,
+				.read = get_temp_3v3_30k9_47k_4050b,
+				.idx = ADC_TEMP_SENSOR_2_SOC },
+	[TEMP_SENSOR_3_CHARGER] = { .name = "Charger",
+				    .type = TEMP_SENSOR_TYPE_BOARD,
+				    .read = get_temp_3v3_30k9_47k_4050b,
+				    .idx = ADC_TEMP_SENSOR_3_CHARGER },
+	[TEMP_SENSOR_4_REGULATOR] = { .name = "Regulator",
+				      .type = TEMP_SENSOR_TYPE_BOARD,
+				      .read = get_temp_3v3_30k9_47k_4050b,
+				      .idx = ADC_TEMP_SENSOR_4_REGULATOR },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_FAN \
-	{ \
+#define THERMAL_FAN              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
@@ -94,8 +86,8 @@ __maybe_unused static const struct ec_thermal_config thermal_fan = THERMAL_FAN;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CPU \
-	{ \
+#define THERMAL_CPU              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
@@ -109,8 +101,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CHARGER \
-	{ \
+#define THERMAL_CHARGER          \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(80), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(85), \
@@ -125,8 +117,8 @@ __maybe_unused static const struct ec_thermal_config thermal_charger =
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_REGULATOR \
-	{ \
+#define THERMAL_REGULATOR        \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(55), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(60), \
diff --git a/board/anahera/thermal.c b/board/anahera/thermal.c
index 8bd670c22a..b5b5a0c1cc 100644
--- a/board/anahera/thermal.c
+++ b/board/anahera/thermal.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,7 +15,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_THERMAL, outstr)
-#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
 
 struct fan_step {
 	/*
@@ -37,45 +37,45 @@ struct fan_step {
 static const struct fan_step fan_table[] = {
 	{
 		/* level 0 */
-		.on = {53, 51, 0, -1},
-		.off = {99, 99, 99, -1},
-		.rpm = {0},
+		.on = { 53, 51, 0, -1 },
+		.off = { 99, 99, 99, -1 },
+		.rpm = { 0 },
 	},
 	{
 		/* level 1 */
-		.on = {54, 52, 0, -1},
-		.off = {52, 50, 99, -1},
-		.rpm = {3000},
+		.on = { 54, 52, 0, -1 },
+		.off = { 52, 50, 99, -1 },
+		.rpm = { 3000 },
 	},
 	{
 		/* level 2 */
-		.on = {55, 53, 0, -1},
-		.off = {53, 51, 99, -1},
-		.rpm = {3400},
+		.on = { 55, 53, 0, -1 },
+		.off = { 53, 51, 99, -1 },
+		.rpm = { 3400 },
 	},
 	{
 		/* level 3 */
-		.on = {56, 54, 0, -1},
-		.off = {54, 52, 99, -1},
-		.rpm = {3800},
+		.on = { 56, 54, 0, -1 },
+		.off = { 54, 52, 99, -1 },
+		.rpm = { 3800 },
 	},
 	{
 		/* level 4 */
-		.on = {57, 55, 54, -1},
-		.off = {55, 53, 51, -1},
-		.rpm = {4100},
+		.on = { 57, 55, 54, -1 },
+		.off = { 55, 53, 51, -1 },
+		.rpm = { 4100 },
 	},
 	{
 		/* level 5 */
-		.on = {58, 56, 60, -1},
-		.off = {56, 54, 52, -1},
-		.rpm = {4400},
+		.on = { 58, 56, 60, -1 },
+		.off = { 56, 54, 52, -1 },
+		.rpm = { 4400 },
 	},
 	{
 		/* level 6 */
-		.on = {100, 100, 100, -1},
-		.off = {57, 59, 58, -1},
-		.rpm = {4900},
+		.on = { 100, 100, 100, -1 },
+		.off = { 57, 59, 58, -1 },
+		.rpm = { 4900 },
 	},
 };
 
@@ -99,11 +99,11 @@ int fan_table_to_rpm(int fan, int *temp)
 	    temp[TEMP_SENSOR_3_CHARGER] < prev_tmp[TEMP_SENSOR_3_CHARGER]) {
 		for (i = current_level; i > 0; i--) {
 			if (temp[TEMP_SENSOR_1_FAN] <
-				fan_table[i].off[TEMP_SENSOR_1_FAN] &&
+				    fan_table[i].off[TEMP_SENSOR_1_FAN] &&
 			    temp[TEMP_SENSOR_3_CHARGER] <
-				fan_table[i].off[TEMP_SENSOR_3_CHARGER] &&
+				    fan_table[i].off[TEMP_SENSOR_3_CHARGER] &&
 			    temp[TEMP_SENSOR_2_SOC] <
-				fan_table[i].off[TEMP_SENSOR_2_SOC])
+				    fan_table[i].off[TEMP_SENSOR_2_SOC])
 				current_level = i - 1;
 			else
 				break;
@@ -111,14 +111,14 @@ int fan_table_to_rpm(int fan, int *temp)
 	} else if (temp[TEMP_SENSOR_1_FAN] > prev_tmp[TEMP_SENSOR_1_FAN] ||
 		   temp[TEMP_SENSOR_2_SOC] > prev_tmp[TEMP_SENSOR_2_SOC] ||
 		   temp[TEMP_SENSOR_3_CHARGER] >
-			prev_tmp[TEMP_SENSOR_3_CHARGER]) {
+			   prev_tmp[TEMP_SENSOR_3_CHARGER]) {
 		for (i = current_level; i < NUM_FAN_LEVELS; i++) {
 			if ((temp[TEMP_SENSOR_1_FAN] >
-				fan_table[i].on[TEMP_SENSOR_1_FAN] &&
-			    temp[TEMP_SENSOR_3_CHARGER] >
-				fan_table[i].on[TEMP_SENSOR_3_CHARGER]) ||
+				     fan_table[i].on[TEMP_SENSOR_1_FAN] &&
+			     temp[TEMP_SENSOR_3_CHARGER] >
+				     fan_table[i].on[TEMP_SENSOR_3_CHARGER]) ||
 			    temp[TEMP_SENSOR_2_SOC] >
-				fan_table[i].on[TEMP_SENSOR_2_SOC])
+				    fan_table[i].on[TEMP_SENSOR_2_SOC])
 				current_level = i + 1;
 			else
 				break;
@@ -139,10 +139,8 @@ int fan_table_to_rpm(int fan, int *temp)
 
 void board_override_fan_control(int fan, int *tmp)
 {
-	if (chipset_in_state(CHIPSET_STATE_ON |
-		CHIPSET_STATE_ANY_SUSPEND)) {
+	if (chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND)) {
 		fan_set_rpm_mode(FAN_CH(fan), 1);
-		fan_set_rpm_target(FAN_CH(fan),
-			fan_table_to_rpm(fan, tmp));
+		fan_set_rpm_target(FAN_CH(fan), fan_table_to_rpm(fan, tmp));
 	}
 }
diff --git a/board/anahera/usbc_config.c b/board/anahera/usbc_config.c
index 52b6b498f0..b0fd5551d9 100644
--- a/board/anahera/usbc_config.c
+++ b/board/anahera/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -32,8 +32,8 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 /* USBC TCPC configuration */
 const struct tcpc_config_t tcpc_config[] = {
@@ -79,33 +79,43 @@ BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
 /* USBC mux configuration - Alder Lake includes internal mux */
-static const struct usb_mux usbc0_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+static const struct usb_mux_chain usbc0_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
-static const struct usb_mux usbc1_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+static const struct usb_mux_chain usbc1_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
 
-const struct usb_mux usb_muxes[] = {
+const struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C0_MUX,
-		.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc0_tcss_usb_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C0_MUX,
+			.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc0_tcss_usb_mux,
 	},
 	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C1_MUX,
-		.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc1_tcss_usb_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C1_MUX,
+			.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc1_tcss_usb_mux,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
@@ -321,33 +331,33 @@ const static struct ps8811_reg_val equalizer_wwan_table[] = {
 	{
 		/* Set channel A EQ setting */
 		.reg = PS8811_REG1_USB_AEQ_LEVEL,
-		.val = (PS8811_AEQ_I2C_LEVEL_UP_13DB <<
-			PS8811_AEQ_I2C_LEVEL_UP_SHIFT) |
-			(PS8811_AEQ_PIN_LEVEL_UP_18DB <<
-			PS8811_AEQ_PIN_LEVEL_UP_SHIFT),
+		.val = (PS8811_AEQ_I2C_LEVEL_UP_13DB
+			<< PS8811_AEQ_I2C_LEVEL_UP_SHIFT) |
+		       (PS8811_AEQ_PIN_LEVEL_UP_18DB
+			<< PS8811_AEQ_PIN_LEVEL_UP_SHIFT),
 	},
 	{
 		/* Set ADE pin setting */
 		.reg = PS8811_REG1_USB_ADE_CONFIG,
-		.val = (PS8811_ADE_PIN_MID_LEVEL_3DB <<
-			PS8811_ADE_PIN_MID_LEVEL_SHIFT) |
-			PS8811_AEQ_CONFIG_REG_ENABLE |
-			PS8811_AEQ_ADAPTIVE_REG_ENABLE,
+		.val = (PS8811_ADE_PIN_MID_LEVEL_3DB
+			<< PS8811_ADE_PIN_MID_LEVEL_SHIFT) |
+		       PS8811_AEQ_CONFIG_REG_ENABLE |
+		       PS8811_AEQ_ADAPTIVE_REG_ENABLE,
 	},
 	{
 		/* Set channel B EQ setting */
 		.reg = PS8811_REG1_USB_BEQ_LEVEL,
-		.val = (PS8811_BEQ_I2C_LEVEL_UP_10P5DB <<
-			PS8811_BEQ_I2C_LEVEL_UP_SHIFT) |
-			(PS8811_BEQ_PIN_LEVEL_UP_18DB <<
-			PS8811_BEQ_PIN_LEVEL_UP_SHIFT),
+		.val = (PS8811_BEQ_I2C_LEVEL_UP_10P5DB
+			<< PS8811_BEQ_I2C_LEVEL_UP_SHIFT) |
+		       (PS8811_BEQ_PIN_LEVEL_UP_18DB
+			<< PS8811_BEQ_PIN_LEVEL_UP_SHIFT),
 	},
 	{
 		/* Set BDE pin setting */
 		.reg = PS8811_REG1_USB_BDE_CONFIG,
-		.val = (PS8811_BDE_PIN_MID_LEVEL_3DB <<
-			PS8811_BDE_PIN_MID_LEVEL_SHIFT) |
-			PS8811_BEQ_CONFIG_REG_ENABLE,
+		.val = (PS8811_BDE_PIN_MID_LEVEL_3DB
+			<< PS8811_BDE_PIN_MID_LEVEL_SHIFT) |
+		       PS8811_BEQ_CONFIG_REG_ENABLE,
 	},
 };
 
@@ -357,8 +367,8 @@ const static struct ps8811_reg_val equalizer_wlan_table[] = {
 	{
 		/* Set 50ohm adjust for B channel */
 		.reg = PS8811_REG1_50OHM_ADJUST_CHAN_B,
-		.val = (PS8811_50OHM_ADJUST_CHAN_B_MINUS_9PCT <<
-			PS8811_50OHM_ADJUST_CHAN_B_SHIFT),
+		.val = (PS8811_50OHM_ADJUST_CHAN_B_MINUS_9PCT
+			<< PS8811_50OHM_ADJUST_CHAN_B_SHIFT),
 	},
 };
 
@@ -371,16 +381,16 @@ static int usba_retimer_init(int port)
 	int i;
 	const struct usb_mux *me = &usba_ps8811[port];
 
-	rv = ps8811_i2c_read(me, PS8811_REG_PAGE1,
-			     PS8811_REG1_USB_BEQ_LEVEL, &val);
+	rv = ps8811_i2c_read(me, PS8811_REG_PAGE1, PS8811_REG1_USB_BEQ_LEVEL,
+			     &val);
 
 	switch (port) {
 	case USBA_PORT_A0:
 		/* Set channel A output swing */
-		rv = ps8811_i2c_field_update(
-			me, PS8811_REG_PAGE1, PS8811_REG1_USB_CHAN_A_SWING,
-			PS8811_CHAN_A_SWING_MASK,
-			0x2 << PS8811_CHAN_A_SWING_SHIFT);
+		rv = ps8811_i2c_field_update(me, PS8811_REG_PAGE1,
+					     PS8811_REG1_USB_CHAN_A_SWING,
+					     PS8811_CHAN_A_SWING_MASK,
+					     0x2 << PS8811_CHAN_A_SWING_SHIFT);
 		break;
 	case USBA_PORT_A1:
 		if (ec_cfg_has_lte()) {
@@ -403,9 +413,9 @@ static int usba_retimer_init(int port)
 				PS8811_REG1_USB_CHAN_B_DE_PS_MSB,
 				PS8811_CHAN_B_DE_PS_MSB_MASK, 0x16);
 
-
 			for (i = 0; i < NUM_EQ_WWAN_ARRAY; i++)
-				rv |= ps8811_i2c_write(me, PS8811_REG_PAGE1,
+				rv |= ps8811_i2c_write(
+					me, PS8811_REG_PAGE1,
 					equalizer_wwan_table[i].reg,
 					equalizer_wwan_table[i].val);
 		} else {
@@ -416,9 +426,9 @@ static int usba_retimer_init(int port)
 				PS8811_CHAN_A_SWING_MASK,
 				0x2 << PS8811_CHAN_A_SWING_SHIFT);
 
-
 			for (i = 0; i < NUM_EQ_WLAN_ARRAY; i++)
-				rv |= ps8811_i2c_write(me, PS8811_REG_PAGE1,
+				rv |= ps8811_i2c_write(
+					me, PS8811_REG_PAGE1,
 					equalizer_wlan_table[i].reg,
 					equalizer_wlan_table[i].val);
 		}
diff --git a/board/anahera/usbc_config.h b/board/anahera/usbc_config.h
index b42c0f59fe..c476919027 100644
--- a/board/anahera/usbc_config.h
+++ b/board/anahera/usbc_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,21 +8,13 @@
 #ifndef __CROS_EC_USBC_CONFIG_H
 #define __CROS_EC_USBC_CONFIG_H
 
-#define CONFIG_USB_PD_PORT_MAX_COUNT	2
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
 
 /* USB-A ports */
-enum usba_port {
-	USBA_PORT_A0 = 0,
-	USBA_PORT_A1,
-	USBA_PORT_COUNT
-};
+enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT };
 
 /* USB-C ports */
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 struct ps8811_reg_val {
 	uint8_t reg;
diff --git a/board/arcada_ish/board.c b/board/arcada_ish/board.c
index b23784cd38..d340f61251 100644
--- a/board/arcada_ish/board.c
+++ b/board/arcada_ish/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -42,11 +42,9 @@ static struct stprivate_data g_lis2dh_data;
 static struct lis2mdl_private_data lis2mdl_a_data;
 
 /* Matrix to rotate lid sensor into standard reference frame */
-const mat33_fp_t lid_rot_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
+const mat33_fp_t lid_rot_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				 { 0, FLOAT_TO_FP(-1), 0 },
+				 { 0, 0, FLOAT_TO_FP(1) } };
 
 /* Drivers */
 struct motion_sensor_t motion_sensors[] = {
@@ -155,8 +153,7 @@ int board_sensor_at_360(void)
 	 * closed at 0 degrees. Ignore the hall sensor when the lid close is
 	 * also active.
 	 */
-	return lid_is_open() &&
-	       !gpio_get_level(GPIO_TABLET_MODE_L);
+	return lid_is_open() && !gpio_get_level(GPIO_TABLET_MODE_L);
 }
 
 /* Initialize board. */
diff --git a/board/arcada_ish/board.h b/board/arcada_ish/board.h
index bf05a48697..129640d60f 100644
--- a/board/arcada_ish/board.h
+++ b/board/arcada_ish/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,7 @@
 #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
 
 /* ISH specific*/
-#undef  CONFIG_DEBUG_ASSERT
+#undef CONFIG_DEBUG_ASSERT
 #define CONFIG_CLOCK_CRYSTAL
 /* EC */
 #define CONFIG_FLASH_SIZE_BYTES 0x80000
@@ -24,13 +24,13 @@
 #define CONFIG_I2C
 #define CONFIG_I2C_CONTROLLER
 
-#define CONFIG_ACCEL_LNG2DM		/* Base sensor: LNG2DM
-					 * (uses LIS2DH driver)
-					 */
-#define CONFIG_ACCELGYRO_LSM6DSM	/* Lid sensor: LSM6DS3
-					 * (uses LSM6DSM driver)
-					 */
-#define CONFIG_MAG_LIS2MDL		/* Lid sensor: LIS2DML */
+#define CONFIG_ACCEL_LNG2DM /* Base sensor: LNG2DM  \
+			     * (uses LIS2DH driver) \
+			     */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Lid sensor: LSM6DS3   \
+				  * (uses LSM6DSM driver) \
+				  */
+#define CONFIG_MAG_LIS2MDL /* Lid sensor: LIS2DML */
 #define CONFIG_MAG_CALIBRATE
 
 /* Enable sensor fifo, must also define the _SIZE and _THRES */
@@ -40,7 +40,7 @@
 /* Depends on how fast the AP boots and typical ODRs. */
 #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
 /* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK  (BIT(BASE_ACCEL) | BIT(LID_MAG))
+#define CONFIG_ACCEL_FORCE_MODE_MASK (BIT(BASE_ACCEL) | BIT(LID_MAG))
 
 #define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
@@ -99,8 +99,8 @@
 #define CONFIG_ISH_PM_D3
 #define CONFIG_ISH_PM_RESET_PREP
 
-#define CONFIG_ISH_D0I2_MIN_USEC        (15*MSEC)	/* need final tune */
-#define CONFIG_ISH_D0I3_MIN_USEC        (100*MSEC)	/* need final tune */
+#define CONFIG_ISH_D0I2_MIN_USEC (15 * MSEC) /* need final tune */
+#define CONFIG_ISH_D0I3_MIN_USEC (100 * MSEC) /* need final tune */
 
 #ifndef __ASSEMBLER__
 
@@ -112,13 +112,7 @@
  * Note: Since we aren't using LPC memory map to transmit sensor data, the
  * order of this enum does not need to be accel, accel, gyro
  */
-enum sensor_id {
-	LID_ACCEL,
-	LID_GYRO,
-	BASE_ACCEL,
-	LID_MAG,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, LID_GYRO, BASE_ACCEL, LID_MAG, SENSOR_COUNT };
 
 #endif /* !__ASSEMBLER__ */
 
diff --git a/board/arcada_ish/build.mk b/board/arcada_ish/build.mk
index a57c08e6ba..80cf4886eb 100644
--- a/board/arcada_ish/build.mk
+++ b/board/arcada_ish/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/arcada_ish/ec.tasklist b/board/arcada_ish/ec.tasklist
index d72fdf309e..81d3c5dc20 100644
--- a/board/arcada_ish/ec.tasklist
+++ b/board/arcada_ish/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/arcada_ish/gpio.inc b/board/arcada_ish/gpio.inc
index 336f807269..6a577d0efe 100644
--- a/board/arcada_ish/gpio.inc
+++ b/board/arcada_ish/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/asurada/battery.c b/board/asurada/battery.c
index 6237a5058c..ad49477366 100644
--- a/board/asurada/battery.c
+++ b/board/asurada/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/asurada/board.c b/board/asurada/board.c
index 83c95722ef..4e4aede76d 100644
--- a/board/asurada/board.c
+++ b/board/asurada/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -66,17 +66,15 @@ static enum base_accelgyro_type base_accelgyro_config;
 /* Matrix to rotate accelerometer into standard reference frame */
 /* for rev 0 */
 static const mat33_fp_t base_standard_ref_rev0 = {
-	{FLOAT_TO_FP(-1), 0, 0},
-	{0, FLOAT_TO_FP(1), 0},
-	{0, 0, FLOAT_TO_FP(-1)},
+	{ FLOAT_TO_FP(-1), 0, 0 },
+	{ 0, FLOAT_TO_FP(1), 0 },
+	{ 0, 0, FLOAT_TO_FP(-1) },
 };
 
 static void update_rotation_matrix(void)
 {
-	motion_sensors[BASE_ACCEL].rot_standard_ref =
-		&base_standard_ref_rev0;
-	motion_sensors[BASE_GYRO].rot_standard_ref =
-		&base_standard_ref_rev0;
+	motion_sensors[BASE_ACCEL].rot_standard_ref = &base_standard_ref_rev0;
+	motion_sensors[BASE_GYRO].rot_standard_ref = &base_standard_ref_rev0;
 }
 DECLARE_HOOK(HOOK_INIT, update_rotation_matrix, HOOK_PRIO_INIT_ADC + 2);
 
@@ -138,9 +136,9 @@ static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
 /* Matrix to rotate accelerometer into standard reference frame */
 /* for Hayato */
 static const mat33_fp_t base_standard_ref = {
-	{0, FLOAT_TO_FP(1), 0},
-	{FLOAT_TO_FP(-1), 0 , 0},
-	{0, 0, FLOAT_TO_FP(1)},
+	{ 0, FLOAT_TO_FP(1), 0 },
+	{ FLOAT_TO_FP(-1), 0, 0 },
+	{ 0, 0, FLOAT_TO_FP(1) },
 };
 
 static void update_rotation_matrix(void)
@@ -151,8 +149,7 @@ static void update_rotation_matrix(void)
 	if (board_get_version() >= 2) {
 		motion_sensors[BASE_ACCEL].rot_standard_ref =
 			&base_standard_ref;
-		motion_sensors[BASE_GYRO].rot_standard_ref =
-			&base_standard_ref;
+		motion_sensors[BASE_GYRO].rot_standard_ref = &base_standard_ref;
 	}
 }
 DECLARE_HOOK(HOOK_INIT, update_rotation_matrix, HOOK_PRIO_INIT_ADC + 2);
@@ -340,28 +337,27 @@ static void board_detect_motionsense(void)
 	if (val == ICM426XX_CHIP_ICM40608) {
 		motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
 		motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
-		base_accelgyro_config =  BASE_GYRO_ICM426XX;
+		base_accelgyro_config = BASE_GYRO_ICM426XX;
 		ccprints("Base Accelgyro: ICM426XX");
 	} else {
 		base_accelgyro_config = BASE_GYRO_BMI160;
 		ccprints("Base Accelgyro: BMI160");
 	}
 }
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_detect_motionsense,
-	     HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_detect_motionsense, HOOK_PRIO_DEFAULT);
 DECLARE_HOOK(HOOK_INIT, board_detect_motionsense, HOOK_PRIO_DEFAULT);
 
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
 	/* Convert to mV (3000mV/1024). */
-	{"VBUS_C0", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0, CHIP_ADC_CH0},
-	{"BOARD_ID_0", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH1},
-	{"BOARD_ID_1", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH2},
+	{ "VBUS_C0", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0, CHIP_ADC_CH0 },
+	{ "BOARD_ID_0", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH1 },
+	{ "BOARD_ID_1", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH2 },
 	/* AMON/BMON gain = 17.97 */
-	{"CHARGER_AMON_R", ADC_MAX_MVOLT * 1000 / 17.97, ADC_READ_MAX + 1, 0,
-	 CHIP_ADC_CH3},
-	{"VBUS_C1", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0, CHIP_ADC_CH5},
-	{"CHARGER_PMON", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH6},
+	{ "CHARGER_AMON_R", ADC_MAX_MVOLT * 1000 / 17.97, ADC_READ_MAX + 1, 0,
+	  CHIP_ADC_CH3 },
+	{ "VBUS_C1", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0, CHIP_ADC_CH5 },
+	{ "CHARGER_PMON", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH6 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
@@ -374,24 +370,18 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
  * number of pwm channel greater than three.
  */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED1] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
-		.freq_hz = 324, /* maximum supported frequency */
-		.pcfsr_sel = PWM_PRESCALER_C4
-	},
-	[PWM_CH_LED2] = {
-		.channel = 1,
-		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
-		.freq_hz = 324, /* maximum supported frequency */
-		.pcfsr_sel = PWM_PRESCALER_C4
-	},
-	[PWM_CH_LED3] = {
-		.channel = 2,
-		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
-		.freq_hz = 324, /* maximum supported frequency */
-		.pcfsr_sel = PWM_PRESCALER_C4
-	},
+	[PWM_CH_LED1] = { .channel = 0,
+			  .flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
+			  .freq_hz = 324, /* maximum supported frequency */
+			  .pcfsr_sel = PWM_PRESCALER_C4 },
+	[PWM_CH_LED2] = { .channel = 1,
+			  .flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
+			  .freq_hz = 324, /* maximum supported frequency */
+			  .pcfsr_sel = PWM_PRESCALER_C4 },
+	[PWM_CH_LED3] = { .channel = 2,
+			  .flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW,
+			  .freq_hz = 324, /* maximum supported frequency */
+			  .pcfsr_sel = PWM_PRESCALER_C4 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
diff --git a/board/asurada/board.h b/board/asurada/board.h
index 85b10e69b3..6d9a19b884 100644
--- a/board/asurada/board.h
+++ b/board/asurada/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -41,7 +41,7 @@
 #define PD_MAX_VOLTAGE_MV 20000
 #define PD_MAX_POWER_MW 60000
 #endif
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* Optional console commands */
@@ -49,7 +49,7 @@
 #define CONFIG_CMD_SCRATCHPAD
 #define CONFIG_CMD_STACKOVERFLOW
 
-#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV	9000
+#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV 9000
 
 /* Sensor */
 #define CONFIG_GMR_TABLET_MODE
@@ -118,12 +118,12 @@ enum sensor_id {
 };
 
 enum adc_channel {
-	ADC_VBUS_C0,             /* ADC 0 */
-	ADC_BOARD_ID_0,          /* ADC 1 */
-	ADC_BOARD_ID_1,          /* ADC 2 */
-	ADC_CHARGER_AMON_R,      /* ADC 3 */
-	ADC_VBUS_C1,             /* ADC 5 */
-	ADC_CHARGER_PMON,        /* ADC 6 */
+	ADC_VBUS_C0, /* ADC 0 */
+	ADC_BOARD_ID_0, /* ADC 1 */
+	ADC_BOARD_ID_1, /* ADC 2 */
+	ADC_CHARGER_AMON_R, /* ADC 3 */
+	ADC_VBUS_C1, /* ADC 5 */
+	ADC_CHARGER_PMON, /* ADC 6 */
 
 	/* Number of ADC channels */
 	ADC_CH_COUNT,
diff --git a/board/asurada/build.mk b/board/asurada/build.mk
index d6866f8568..72015fba95 100644
--- a/board/asurada/build.mk
+++ b/board/asurada/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/asurada/ec.tasklist b/board/asurada/ec.tasklist
index ff47718bae..c8e234a412 100644
--- a/board/asurada/ec.tasklist
+++ b/board/asurada/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/asurada/gpio.inc b/board/asurada/gpio.inc
index 75d1fbafa5..46700a7749 100644
--- a/board/asurada/gpio.inc
+++ b/board/asurada/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/asurada/led.c b/board/asurada/led.c
index 166ece92e9..ca29f0be45 100644
--- a/board/asurada/led.c
+++ b/board/asurada/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -15,18 +15,16 @@
 #include "stdbool.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_PWM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_PWM, format, ##args)
 
 #define LED_OFF EC_LED_COLOR_COUNT
 
 const enum ec_led_id supported_led_ids[] = {
 	/* Main LED */
-	EC_LED_ID_LEFT_LED,
-	EC_LED_ID_RIGHT_LED,
+	EC_LED_ID_LEFT_LED, EC_LED_ID_RIGHT_LED,
 
 	/* Not used, give them some random name for testing */
-	EC_LED_ID_POWER_LED,
-	EC_LED_ID_BATTERY_LED
+	EC_LED_ID_POWER_LED, EC_LED_ID_BATTERY_LED
 };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -85,8 +83,7 @@ static void led_set_color_battery(enum ec_led_colors color, int duty)
 }
 
 static enum ec_error_list set_color(enum ec_led_id led_id,
-				    enum ec_led_colors color,
-				    int duty)
+				    enum ec_led_colors color, int duty)
 {
 	switch (led_id) {
 	case EC_LED_ID_LEFT_LED:
@@ -174,13 +171,11 @@ static void update_led(enum ec_led_id led_id, bool is_active_charge_port,
 		if (chipset_in_state(CHIPSET_STATE_ON))
 			set_color(led_id, EC_LED_COLOR_WHITE, duty);
 		else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-			set_color(
-				led_id,
-				(tick % 8 < 6) ? EC_LED_COLOR_AMBER : LED_OFF,
-				duty);
+			set_color(led_id,
+				  (tick % 8 < 6) ? EC_LED_COLOR_AMBER : LED_OFF,
+				  duty);
 		else
 			set_color(led_id, LED_OFF, 0);
-
 	}
 }
 
diff --git a/board/asurada/led_hayato.c b/board/asurada/led_hayato.c
index 1d3108c47b..be1a352289 100644
--- a/board/asurada/led_hayato.c
+++ b/board/asurada/led_hayato.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,31 +14,40 @@ __override const int led_charge_lvl_1 = 5;
 __override const int led_charge_lvl_2 = 95;
 
 __override struct led_descriptor
-		led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
 __override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	     3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	     3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    1 * LED_ONE_SEC },
+						  { LED_OFF,
+						    3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
 const enum ec_led_id supported_led_ids[] = {
 	EC_LED_ID_BATTERY_LED,
@@ -78,12 +87,12 @@ void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
 {
 	if (led_id == EC_LED_ID_BATTERY_LED) {
 		brightness_range[EC_LED_COLOR_AMBER] =
-				MT6360_LED_BRIGHTNESS_MAX;
+			MT6360_LED_BRIGHTNESS_MAX;
 		brightness_range[EC_LED_COLOR_WHITE] =
-				MT6360_LED_BRIGHTNESS_MAX;
+			MT6360_LED_BRIGHTNESS_MAX;
 	} else if (led_id == EC_LED_ID_POWER_LED) {
 		brightness_range[EC_LED_COLOR_WHITE] =
-				MT6360_LED_BRIGHTNESS_MAX;
+			MT6360_LED_BRIGHTNESS_MAX;
 	}
 }
 
diff --git a/board/asurada/usbc_config.c b/board/asurada/usbc_config.c
index 63552980c3..ba6461b0f8 100644
--- a/board/asurada/usbc_config.c
+++ b/board/asurada/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,16 +17,13 @@ __override int syv682x_board_is_syv682c(int port)
 void board_usb_mux_init(void)
 {
 	if (board_get_sub_board() == SUB_BOARD_TYPEC) {
-		ps8743_tune_usb_eq(&usb_muxes[1],
-				   PS8743_USB_EQ_TX_12_8_DB,
+		ps8743_tune_usb_eq(usb_muxes[1].mux, PS8743_USB_EQ_TX_12_8_DB,
 				   PS8743_USB_EQ_RX_12_8_DB);
-		ps8743_write(&usb_muxes[1],
-				   PS8743_REG_HS_DET_THRESHOLD,
-				   PS8743_USB_HS_THRESH_NEG_10);
-		ps8743_field_update(&usb_muxes[1],
-				   PS8743_REG_DCI_CONFIG_2,
-				   PS8743_AUTO_DCI_MODE_MASK,
-				   PS8743_AUTO_DCI_MODE_FORCE_USB);
+		ps8743_write(usb_muxes[1].mux, PS8743_REG_HS_DET_THRESHOLD,
+			     PS8743_USB_HS_THRESH_NEG_10);
+		ps8743_field_update(usb_muxes[1].mux, PS8743_REG_DCI_CONFIG_2,
+				    PS8743_AUTO_DCI_MODE_MASK,
+				    PS8743_AUTO_DCI_MODE_FORCE_USB);
 	}
 }
 DECLARE_HOOK(HOOK_INIT, board_usb_mux_init, HOOK_PRIO_INIT_I2C + 1);
diff --git a/board/asurada_scp/board.h b/board/asurada_scp/board.h
index e25a26dec0..b70a39d20d 100644
--- a/board/asurada_scp/board.h
+++ b/board/asurada_scp/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,8 +25,8 @@
 #define CONFIG_ROM_BASE 0x0
 #define CONFIG_RAM_BASE 0x58000
 #define CONFIG_ROM_SIZE (CONFIG_RAM_BASE - CONFIG_ROM_BASE)
-#define CONFIG_RAM_SIZE ((CONFIG_IPC_SHARED_OBJ_ADDR & (~(0x400 - 1))) - \
-			 CONFIG_RAM_BASE)
+#define CONFIG_RAM_SIZE \
+	((CONFIG_IPC_SHARED_OBJ_ADDR & (~(0x400 - 1))) - CONFIG_RAM_BASE)
 
 #define SCP_FW_END 0x100000
 
diff --git a/board/asurada_scp/build.mk b/board/asurada_scp/build.mk
index f3c4a82a10..94efa82a6f 100644
--- a/board/asurada_scp/build.mk
+++ b/board/asurada_scp/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/asurada_scp/ec.tasklist b/board/asurada_scp/ec.tasklist
index 6e2f613c6d..1e43d6d30d 100644
--- a/board/asurada_scp/ec.tasklist
+++ b/board/asurada_scp/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/asurada_scp/gpio.inc b/board/asurada_scp/gpio.inc
index 3222a34e08..efc5675875 100644
--- a/board/asurada_scp/gpio.inc
+++ b/board/asurada_scp/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/atlas/battery.c b/board/atlas/battery.c
index fb2fba18be..78b3be16a4 100644
--- a/board/atlas/battery.c
+++ b/board/atlas/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -18,10 +18,10 @@
 #include "i2c.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 /* Shutdown mode parameter to write to manufacturer access register */
-#define SB_SHUTDOWN_DATA	0x0010
+#define SB_SHUTDOWN_DATA 0x0010
 
 enum battery_type {
 	BATTERY_LG,
@@ -52,16 +52,16 @@ static int battery_report_present = 1;
  * limits are given by discharging_min/max_c.
  */
 static const struct battery_info batt_info_lg = {
-	.voltage_max		= TARGET_WITH_MARGIN(8800, 5), /* mV */
-	.voltage_normal		= 7700,
-	.voltage_min		= 6100, /* Add 100mV for charger accuracy */
-	.precharge_current	= 256,	/* mA */
-	.start_charging_min_c	= 0,
-	.start_charging_max_c	= 46,
-	.charging_min_c		= 10,
-	.charging_max_c		= 50,
-	.discharging_min_c	= 0,
-	.discharging_max_c	= 60,
+	.voltage_max = TARGET_WITH_MARGIN(8800, 5), /* mV */
+	.voltage_normal = 7700,
+	.voltage_min = 6100, /* Add 100mV for charger accuracy */
+	.precharge_current = 256, /* mA */
+	.start_charging_min_c = 0,
+	.start_charging_max_c = 46,
+	.charging_min_c = 10,
+	.charging_max_c = 50,
+	.discharging_min_c = 0,
+	.discharging_max_c = 60,
 };
 
 /*
@@ -70,16 +70,16 @@ static const struct battery_info batt_info_lg = {
  * limits are given by discharging_min/max_c.
  */
 static const struct battery_info batt_info_lishen = {
-	.voltage_max		= TARGET_WITH_MARGIN(8800, 5), /* mV */
-	.voltage_normal		= 7700,
-	.voltage_min		= 6100, /* Add 100mV for charger accuracy */
-	.precharge_current	= 256,	/* mA */
-	.start_charging_min_c	= 0,
-	.start_charging_max_c	= 46,
-	.charging_min_c		= 10,
-	.charging_max_c		= 50,
-	.discharging_min_c	= 0,
-	.discharging_max_c	= 60,
+	.voltage_max = TARGET_WITH_MARGIN(8800, 5), /* mV */
+	.voltage_normal = 7700,
+	.voltage_min = 6100, /* Add 100mV for charger accuracy */
+	.precharge_current = 256, /* mA */
+	.start_charging_min_c = 0,
+	.start_charging_max_c = 46,
+	.charging_min_c = 10,
+	.charging_max_c = 50,
+	.discharging_min_c = 0,
+	.discharging_max_c = 60,
 };
 
 static const struct board_batt_params info[] = {
@@ -110,7 +110,7 @@ static int board_get_battery_type(void)
 	if (!battery_manufacturer_name(name, sizeof(name))) {
 		for (i = 0; i < BATTERY_TYPE_COUNT; i++) {
 			if (!strncasecmp(name, info[i].manuf_name,
-					 ARRAY_SIZE(name)-1)) {
+					 ARRAY_SIZE(name) - 1)) {
 				board_battery_type = i;
 				break;
 			}
@@ -139,7 +139,9 @@ DECLARE_HOOK(HOOK_INIT, board_init_battery_type, HOOK_PRIO_INIT_I2C + 1);
 const struct battery_info *battery_get_info(void)
 {
 	return info[board_battery_type == BATTERY_TYPE_COUNT ?
-		    DEFAULT_BATTERY_TYPE : board_battery_type].batt_info;
+			    DEFAULT_BATTERY_TYPE :
+			    board_battery_type]
+		.batt_info;
 }
 
 int board_cut_off_battery(void)
@@ -183,7 +185,7 @@ static int charger_should_discharge_on_ac(struct charge_state_data *curr)
 	 */
 	if (!battery_is_cut_off() &&
 	    !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
-		(curr->batt.status & STATUS_FULLY_CHARGED))
+	    (curr->batt.status & STATUS_FULLY_CHARGED))
 		return 1;
 
 	return 0;
diff --git a/board/atlas/board.c b/board/atlas/board.c
index 64d0789dd9..6fbbb64b16 100644
--- a/board/atlas/board.c
+++ b/board/atlas/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -29,6 +29,7 @@
 #include "keyboard_scan.h"
 #include "lid_switch.h"
 #include "motion_sense.h"
+#include "panic.h"
 #include "power_button.h"
 #include "power.h"
 #include "pwm_chip.h"
@@ -46,8 +47,8 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
@@ -85,19 +86,19 @@ __override struct keyboard_scan_config keyscan_config = {
 
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT]       = { 3, 0, 10000 },
-	[PWM_CH_DB0_LED_BLUE]  = {
-		0, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, 2400 },
-	[PWM_CH_DB0_LED_RED]   = {
-		2, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, 2400 },
-	[PWM_CH_DB0_LED_GREEN] = {
-		6, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, 2400 },
-	[PWM_CH_DB1_LED_BLUE]  = {
-		1, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, 2400 },
-	[PWM_CH_DB1_LED_RED]   = {
-		7, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, 2400 },
-	[PWM_CH_DB1_LED_GREEN] = {
-		5, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, 2400 },
+	[PWM_CH_KBLIGHT] = { 3, 0, 10000 },
+	[PWM_CH_DB0_LED_BLUE] = { 0, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+				  2400 },
+	[PWM_CH_DB0_LED_RED] = { 2, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+				 2400 },
+	[PWM_CH_DB0_LED_GREEN] = { 6, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+				   2400 },
+	[PWM_CH_DB1_LED_BLUE] = { 1, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+				  2400 },
+	[PWM_CH_DB1_LED_RED] = { 7, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+				 2400 },
+	[PWM_CH_DB1_LED_GREEN] = { 5, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+				   2400 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
@@ -114,66 +115,46 @@ const struct adc_t adc_channels[] = {
 	 * Adapter current output or battery charging/discharging current (uV)
 	 * 18x amplification on charger side.
 	 */
-	[ADC_AMON_BMON] = {
-		"AMON_BMON",
-		NPCX_ADC_CH2,
-		ADC_MAX_VOLT*1000/18,
-		ADC_READ_MAX+1,
-		0
-	},
+	[ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH2, ADC_MAX_VOLT * 1000 / 18,
+			    ADC_READ_MAX + 1, 0 },
 	/*
 	 * ISL9238 PSYS output is 1.44 uA/W over 12.4K resistor, to read
 	 * 0.8V @ 45 W, i.e. 56250 uW/mV. Using ADC_MAX_VOLT*56250 and
 	 * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we
 	 * only divide by 2 (enough to avoid precision issues).
 	 */
-	[ADC_PSYS] = {
-		"PSYS",
-		NPCX_ADC_CH3,
-		ADC_MAX_VOLT*56250*2/(ADC_READ_MAX+1),
-		2,
-		0
-	},
+	[ADC_PSYS] = { "PSYS", NPCX_ADC_CH3,
+		       ADC_MAX_VOLT * 56250 * 2 / (ADC_READ_MAX + 1), 2, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* I2C port map */
-const struct i2c_port_t i2c_ports[]  = {
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl  = GPIO_EC_I2C0_POWER_SCL,
-		.sda  = GPIO_EC_I2C0_POWER_SDA
-	},
-	{
-		.name = "tcpc0",
-		.port = I2C_PORT_TCPC0,
-		.kbps = 1000,
-		.scl  = GPIO_EC_I2C1_USB_C0_SCL,
-		.sda  = GPIO_EC_I2C1_USB_C0_SDA
-	},
-	{
-		.name = "tcpc1",
-		.port = I2C_PORT_TCPC1,
-		.kbps = 1000,
-		.scl  = GPIO_EC_I2C2_USB_C1_SCL,
-		.sda  = GPIO_EC_I2C2_USB_C1_SDA
-	},
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 100,
-		.scl  = GPIO_EC_I2C3_SENSOR_3V3_SCL,
-		.sda  = GPIO_EC_I2C3_SENSOR_3V3_SDA
-	},
-	{
-		.name = "battery",
-		.port = I2C_PORT_BATTERY,
-		.kbps = 100,
-		.scl  = GPIO_EC_I2C4_BATTERY_SCL,
-		.sda  = GPIO_EC_I2C4_BATTERY_SDA
-	},
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C0_POWER_SCL,
+	  .sda = GPIO_EC_I2C0_POWER_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C1_USB_C0_SCL,
+	  .sda = GPIO_EC_I2C1_USB_C0_SDA },
+	{ .name = "tcpc1",
+	  .port = I2C_PORT_TCPC1,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C2_USB_C1_SCL,
+	  .sda = GPIO_EC_I2C2_USB_C1_SDA },
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C3_SENSOR_3V3_SCL,
+	  .sda = GPIO_EC_I2C3_SENSOR_3V3_SDA },
+	{ .name = "battery",
+	  .port = I2C_PORT_BATTERY,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C4_BATTERY_SCL,
+	  .sda = GPIO_EC_I2C4_BATTERY_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -212,16 +193,22 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	},
 	{
-		.usb_port = 1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	},
 };
 
@@ -247,9 +234,9 @@ void board_tcpc_init(void)
 	 */
 	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
 		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
 
 uint16_t tcpc_get_alert_status(void)
 {
@@ -269,16 +256,16 @@ uint16_t tcpc_get_alert_status(void)
 }
 
 const struct temp_sensor_t temp_sensors[] = {
-	{"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0},
+	{ "Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0 },
 	/* BD99992GW temp sensors are only readable in S0 */
-	{"Ambient", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM0},
-	{"Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM1},
-	{"DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM2},
-	{"eMMC", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM3},
+	{ "Ambient", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM0 },
+	{ "Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM1 },
+	{ "DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM2 },
+	{ "eMMC", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM3 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -304,12 +291,12 @@ static void board_report_pmic_fault(const char *str)
 	/* VRFAULT has occurred, print VRFAULT status bits. */
 
 	/* PWRSTAT1 */
-	i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS,
-		  BD99992GW_REG_PWRSTAT1, &pwrstat1);
+	i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, BD99992GW_REG_PWRSTAT1,
+		  &pwrstat1);
 
 	/* PWRSTAT2 */
-	i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS,
-		  BD99992GW_REG_PWRSTAT2, &pwrstat2);
+	i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, BD99992GW_REG_PWRSTAT2,
+		  &pwrstat2);
 
 	CPRINTS("PMIC VRFAULT: %s", str);
 	CPRINTS("PMIC VRFAULT: PWRSTAT1=0x%02x PWRSTAT2=0x%02x", pwrstat1,
@@ -350,8 +337,8 @@ static void board_pmic_disable_slp_s0_vr_decay(void)
 	 * Bits 3:2 (10) - VR set to AUTO on SLP_S0# de-assertion
 	 * Bits 1:0 (10) - VR set to AUTO operating mode
 	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS,
-		   BD99992GW_REG_V18ACNT, 0x2a);
+	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, BD99992GW_REG_V18ACNT,
+		   0x2a);
 
 	/*
 	 * V085ACNT:
@@ -383,8 +370,8 @@ static void board_pmic_enable_slp_s0_vr_decay(void)
 	 * Bits 3:2 (10) - VR set to AUTO on SLP_S0# de-assertion
 	 * Bits 1:0 (10) - VR set to AUTO operating mode
 	 */
-	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS,
-		   BD99992GW_REG_V18ACNT, 0x6a);
+	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, BD99992GW_REG_V18ACNT,
+		   0x6a);
 
 	/*
 	 * V085ACNT:
@@ -397,8 +384,7 @@ static void board_pmic_enable_slp_s0_vr_decay(void)
 		   BD99992GW_REG_V085ACNT, 0x6a);
 }
 
-__override void power_board_handle_host_sleep_event(
-		enum host_sleep_event state)
+__override void power_board_handle_host_sleep_event(enum host_sleep_event state)
 {
 	if (state == HOST_SLEEP_EVENT_S0IX_SUSPEND)
 		board_pmic_enable_slp_s0_vr_decay();
@@ -517,8 +503,8 @@ int board_set_active_charge_port(int charge_port)
 	int is_real_port = (charge_port >= 0 &&
 			    charge_port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	/* check if we are sourcing VBUS on the port */
-	int is_source = gpio_get_level(charge_port == 0 ?
-			GPIO_USB_C0_5V_EN : GPIO_USB_C1_5V_EN);
+	int is_source = gpio_get_level(charge_port == 0 ? GPIO_USB_C0_5V_EN :
+							  GPIO_USB_C1_5V_EN);
 
 	if (is_real_port && is_source) {
 		CPRINTS("No charging from p%d", charge_port);
@@ -534,10 +520,12 @@ int board_set_active_charge_port(int charge_port)
 	} else {
 		/* Make sure non-charging port is disabled */
 		gpio_set_level(charge_port ? GPIO_EN_USB_C0_CHARGE_L :
-					     GPIO_EN_USB_C1_CHARGE_L, 1);
+					     GPIO_EN_USB_C1_CHARGE_L,
+			       1);
 		/* Enable charging port */
 		gpio_set_level(charge_port ? GPIO_EN_USB_C1_CHARGE_L :
-					     GPIO_EN_USB_C0_CHARGE_L, 0);
+					     GPIO_EN_USB_C0_CHARGE_L,
+			       0);
 	}
 
 	return EC_SUCCESS;
@@ -568,12 +556,12 @@ DECLARE_HOOK(HOOK_INIT, board_charger_init, HOOK_PRIO_DEFAULT);
  * @param charge_ma     Desired charge limit (mA).
  * @param charge_mv     Negotiated charge voltage (mV).
  */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	charge_ma = charger_derate(charge_ma);
-	charge_set_input_current_limit(MAX(charge_ma,
-				   CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 static void board_chipset_suspend(void)
diff --git a/board/atlas/board.h b/board/atlas/board.h
index c3ddafe2cb..0882b5742e 100644
--- a/board/atlas/board.h
+++ b/board/atlas/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,7 +12,7 @@
  * By default, enable all console messages excepted HC, ACPI and event:
  * The sensor stack is generating a lot of activity.
  */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
 #undef CONFIG_HOSTCMD_DEBUG_MODE
 #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
 
@@ -55,8 +55,8 @@
 #define CONFIG_CHIPSET_RESET_HOOK
 #define CONFIG_CPU_PROCHOT_ACTIVE_LOW
 #define CONFIG_HOST_INTERFACE_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 
 #define CONFIG_KEYBOARD_COL2_INVERTED
 #define CONFIG_KEYBOARD_PROTOCOL_8042
@@ -147,29 +147,29 @@
 #define CONFIG_USBC_VCONN_SWAP
 
 /* Optional feature to configure npcx chip */
-#define NPCX_UART_MODULE2	1 /* 1:GPIO64/65 as UART */
-#define NPCX_JTAG_MODULE2	0 /* 0:GPIO21/17/16/20 as JTAG */
-#define NPCX_TACH_SEL2		0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
-#define NPCX7_PWM1_SEL		1 /* GPIO C2 is used as PWM1. */
-#define CONFIG_HIBERNATE_PSL	/* Enable PSL pins for wakeup */
+#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART */
+#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 as JTAG */
+#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
+#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */
+#define CONFIG_HIBERNATE_PSL /* Enable PSL pins for wakeup */
 
 /* I2C ports */
-#define I2C_PORT_POWER		NPCX_I2C_PORT0_0	/* pmic/charger */
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT1_0
-#define I2C_PORT_TCPC1		NPCX_I2C_PORT2_0
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT3_0	/* als */
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT4_1
-#define I2C_PORT_GYRO		NPCX_I2C_PORT5_0	/* accel/gyro */
-
-#define I2C_PORT_ACCEL		I2C_PORT_GYRO
-#define I2C_PORT_CHARGER	I2C_PORT_POWER
-#define I2C_PORT_PMIC		I2C_PORT_POWER
-#define I2C_PORT_THERMAL	I2C_PORT_POWER
+#define I2C_PORT_POWER NPCX_I2C_PORT0_0 /* pmic/charger */
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT1_0
+#define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT3_0 /* als */
+#define I2C_PORT_BATTERY NPCX_I2C_PORT4_1
+#define I2C_PORT_GYRO NPCX_I2C_PORT5_0 /* accel/gyro */
+
+#define I2C_PORT_ACCEL I2C_PORT_GYRO
+#define I2C_PORT_CHARGER I2C_PORT_POWER
+#define I2C_PORT_PMIC I2C_PORT_POWER
+#define I2C_PORT_THERMAL I2C_PORT_POWER
 
 /* I2C addresses */
-#define I2C_ADDR_TCPC_FLAGS	0x0B
-#define I2C_ADDR_MP2949_FLAGS	0x20
-#define I2C_ADDR_BD99992_FLAGS	0x30
+#define I2C_ADDR_TCPC_FLAGS 0x0B
+#define I2C_ADDR_MP2949_FLAGS 0x20
+#define I2C_ADDR_BD99992_FLAGS 0x30
 
 #ifndef __ASSEMBLER__
 
@@ -177,11 +177,11 @@
 #include "registers.h"
 
 enum temp_sensor_id {
-	TEMP_SENSOR_BATTERY,	/* BD99956GW TSENSE */
-	TEMP_SENSOR_SYSTHERM0,	/* BD99992GW SYSTHERM0 */
-	TEMP_SENSOR_SYSTHERM1,	/* BD99992GW SYSTHERM1 */
-	TEMP_SENSOR_SYSTHERM2,	/* BD99992GW SYSTHERM2 */
-	TEMP_SENSOR_SYSTHERM3,	/* BD99992GW SYSTHERM3 */
+	TEMP_SENSOR_BATTERY, /* BD99956GW TSENSE */
+	TEMP_SENSOR_SYSTHERM0, /* BD99992GW SYSTHERM0 */
+	TEMP_SENSOR_SYSTHERM1, /* BD99992GW SYSTHERM1 */
+	TEMP_SENSOR_SYSTHERM2, /* BD99992GW SYSTHERM2 */
+	TEMP_SENSOR_SYSTHERM3, /* BD99992GW SYSTHERM3 */
 	TEMP_SENSOR_COUNT
 };
 
@@ -202,28 +202,24 @@ enum sensor_id {
 };
 
 /* LID_ALS needs to be polled */
-#define CONFIG_ACCEL_FORCE_MODE_MASK	BIT(LID_ALS)
+#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ALS)
 
-enum adc_channel {
-	ADC_AMON_BMON,
-	ADC_PSYS,
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_AMON_BMON, ADC_PSYS, ADC_CH_COUNT };
 
 /*
  * delay to turn on the power supply max is ~16ms.
  * delay to turn off the power supply max is about ~180ms.
  */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	250000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* delay to turn on/off vconn */
 
 /* Define typical operating power and max power */
-#define PD_OPERATING_POWER_MW		15000
-#define PD_MAX_POWER_MW			60000
-#define PD_MAX_CURRENT_MA		3000
-#define PD_MAX_VOLTAGE_MV		20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Board specific handlers */
 int board_get_version(void);
@@ -236,33 +232,33 @@ void board_reset_pd_mcu(void);
  * vs. names hard-coded in various parts of the EC codebase.
  */
 
-#define GPIO_AC_PRESENT		GPIO_ROP_EC_ACOK
-#define GPIO_BATTERY_PRESENT_L	GPIO_EC_BATT_PRES_L
-#define GPIO_BOARD_VERSION1	GPIO_EC_BRD_ID1
-#define GPIO_BOARD_VERSION2	GPIO_EC_BRD_ID2
-#define GPIO_BOARD_VERSION3	GPIO_EC_BRD_ID3
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_ENTERING_RW	GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2		GPIO_EC_KB_ROW02_INV
-#define GPIO_PCH_ACOK		GPIO_EC_PCH_ACPRESENT
-#define GPIO_PCH_PWRBTN_L	GPIO_EC_PCH_PWR_BTN_L
-#define GPIO_PCH_RSMRST_L	GPIO_RSMRST_L
-#define GPIO_PCH_SLP_SUS_L	GPIO_SLP_SUS_L_PCH
-#define GPIO_PCH_WAKE_L		GPIO_EC_PCH_WAKE_L
-#define GPIO_PMIC_DPWROK	GPIO_ROP_DSW_PWROK_EC
-#define GPIO_PMIC_SLP_SUS_L	GPIO_SLP_SUS_L_PMIC
-#define GPIO_POWER_BUTTON_L	GPIO_MECH_PWR_BTN_ODL
-#define GPIO_PG_EC_RSMRST_ODL	GPIO_ROP_EC_RSMRST_L
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_USB_C0_5V_EN	GPIO_EN_USB_C0_5V_OUT
-#define GPIO_USB_C0_PD_RST_L	GPIO_USB_PD_RST_L
-#define GPIO_USB_C1_5V_EN	GPIO_EN_USB_C1_5V_OUT
-#define GPIO_USB_C1_PD_RST_L	GPIO_USB_PD_RST_L
-#define GPIO_WP_L		GPIO_EC_WP_L
+#define GPIO_AC_PRESENT GPIO_ROP_EC_ACOK
+#define GPIO_BATTERY_PRESENT_L GPIO_EC_BATT_PRES_L
+#define GPIO_BOARD_VERSION1 GPIO_EC_BRD_ID1
+#define GPIO_BOARD_VERSION2 GPIO_EC_BRD_ID2
+#define GPIO_BOARD_VERSION3 GPIO_EC_BRD_ID3
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KB_ROW02_INV
+#define GPIO_PCH_ACOK GPIO_EC_PCH_ACPRESENT
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_L
+#define GPIO_PCH_RSMRST_L GPIO_RSMRST_L
+#define GPIO_PCH_SLP_SUS_L GPIO_SLP_SUS_L_PCH
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_L
+#define GPIO_PMIC_DPWROK GPIO_ROP_DSW_PWROK_EC
+#define GPIO_PMIC_SLP_SUS_L GPIO_SLP_SUS_L_PMIC
+#define GPIO_POWER_BUTTON_L GPIO_MECH_PWR_BTN_ODL
+#define GPIO_PG_EC_RSMRST_ODL GPIO_ROP_EC_RSMRST_L
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_USB_C0_5V_EN GPIO_EN_USB_C0_5V_OUT
+#define GPIO_USB_C0_PD_RST_L GPIO_USB_PD_RST_L
+#define GPIO_USB_C1_5V_EN GPIO_EN_USB_C1_5V_OUT
+#define GPIO_USB_C1_PD_RST_L GPIO_USB_PD_RST_L
+#define GPIO_WP_L GPIO_EC_WP_L
 
 /* ps8751 requires 1ms reset down assertion */
-#define PS8XXX_RST_L_RST_H_DELAY_MS	1
+#define PS8XXX_RST_L_RST_H_DELAY_MS 1
 
-#define ATLAS_REV_FIXED_EC_WP	4
+#define ATLAS_REV_FIXED_EC_WP 4
 
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/atlas/build.mk b/board/atlas/build.mk
index f1619f73cd..b7eeeb0a61 100644
--- a/board/atlas/build.mk
+++ b/board/atlas/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/atlas/ec.tasklist b/board/atlas/ec.tasklist
index 33e3cccb16..b0bf043717 100644
--- a/board/atlas/ec.tasklist
+++ b/board/atlas/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/atlas/gpio.inc b/board/atlas/gpio.inc
index 4ce44cc130..ea76ab8841 100644
--- a/board/atlas/gpio.inc
+++ b/board/atlas/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/atlas/led.c b/board/atlas/led.c
index 9cb4dabfd3..2a297848e3 100644
--- a/board/atlas/led.c
+++ b/board/atlas/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,13 +18,13 @@ const enum ec_led_id supported_led_ids[] = {
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = {
-				/* Red, Green, Blue */
-	[EC_LED_COLOR_RED]    = {  70,   0,   0 },
-	[EC_LED_COLOR_GREEN]  = {   0,  35,   0 },
-	[EC_LED_COLOR_BLUE]   = {   0,   0, 100 },
-	[EC_LED_COLOR_YELLOW] = {  55,  15,   0 },
-	[EC_LED_COLOR_WHITE]  = {  62, 100,  31 },
-	[EC_LED_COLOR_AMBER]  = { 100,  31,   0 },
+	/* Red, Green, Blue */
+	[EC_LED_COLOR_RED] = { 70, 0, 0 },
+	[EC_LED_COLOR_GREEN] = { 0, 35, 0 },
+	[EC_LED_COLOR_BLUE] = { 0, 0, 100 },
+	[EC_LED_COLOR_YELLOW] = { 55, 15, 0 },
+	[EC_LED_COLOR_WHITE] = { 62, 100, 31 },
+	[EC_LED_COLOR_AMBER] = { 100, 31, 0 },
 };
 
 /*
diff --git a/board/atlas/usb_pd_policy.c b/board/atlas/usb_pd_policy.c
index 77a4941a9a..fc7a2141f5 100644
--- a/board/atlas/usb_pd_policy.c
+++ b/board/atlas/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,12 +23,12 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT];
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5,
-							TYPEC_RP_1A5};
+static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5,
+							 TYPEC_RP_1A5 };
 
 int board_vbus_source_enabled(int port)
 {
@@ -38,9 +38,9 @@ int board_vbus_source_enabled(int port)
 static void board_vbus_update_source_current(int port)
 {
 	enum gpio_signal gpio_5v_en = port ? GPIO_USB_C1_5V_EN :
-		GPIO_USB_C0_5V_EN;
+					     GPIO_USB_C0_5V_EN;
 	enum gpio_signal gpio_3a_en = port ? GPIO_EN_USB_C1_3A :
-		GPIO_EN_USB_C0_3A;
+					     GPIO_EN_USB_C0_3A;
 
 	/*
 	 * 1.5 vs 3.0 A limit is controlled by a dedicated gpio where
@@ -67,8 +67,8 @@ int pd_snk_is_vbus_provided(int port)
 int pd_set_power_supply_ready(int port)
 {
 	/* Disable charging */
-	gpio_set_level(port ? GPIO_EN_USB_C1_CHARGE_L :
-			      GPIO_EN_USB_C0_CHARGE_L, 1);
+	gpio_set_level(port ? GPIO_EN_USB_C1_CHARGE_L : GPIO_EN_USB_C0_CHARGE_L,
+		       1);
 
 	/* Ensure we advertise the proper available current quota */
 	charge_manager_source_port(port, 1);
@@ -111,15 +111,12 @@ int pd_check_vconn_swap(int port)
 	return gpio_get_level(GPIO_PMIC_SLP_SUS_L);
 }
 
-__override void pd_execute_data_swap(int port,
-				     enum pd_data_role data_role)
+__override void pd_execute_data_swap(int port, enum pd_data_role data_role)
 {
 	/* Only port 0 supports device mode. */
 	if (port != 0)
 		return;
 
-	gpio_set_level(GPIO_USB2_ID,
-		      (data_role == PD_ROLE_UFP) ? 1 : 0);
-	gpio_set_level(GPIO_USB2_VBUSSENSE,
-		      (data_role == PD_ROLE_UFP) ? 1 : 0);
+	gpio_set_level(GPIO_USB2_ID, (data_role == PD_ROLE_UFP) ? 1 : 0);
+	gpio_set_level(GPIO_USB2_VBUSSENSE, (data_role == PD_ROLE_UFP) ? 1 : 0);
 }
diff --git a/board/baklava/board.c b/board/baklava/board.c
index 12365e0ff6..dc0b3a952a 100644
--- a/board/baklava/board.c
+++ b/board/baklava/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -28,8 +28,8 @@
 #include "usb_tc_sm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
 #define QUICHE_PD_DEBUG_LVL 1
 
@@ -84,25 +84,25 @@ static void board_usbc_usb3_interrupt(enum gpio_signal signal)
  * signals is driven by USB/MST hub power sequencing requirements.
  */
 const struct power_seq board_power_seq[] = {
-	{GPIO_EN_AC_JACK,               1, 20},
-	{GPIO_EC_DFU_MUX_CTRL,          0, 0},
-	{GPIO_EN_PP5000_A,              1, 31},
-	{GPIO_MST_LP_CTL_L,             1, 0},
-	{GPIO_EN_PP3300_B,              1, 1},
-	{GPIO_EN_PP1100_A,              1, 100+30},
-	{GPIO_EN_BB,                    1, 30},
-	{GPIO_EN_PP1050_A,              1, 30},
-	{GPIO_EN_PP1200_A,              1, 20},
-	{GPIO_EN_PP5000_C,              1, 20},
-	{GPIO_EN_PP5000_HSPORT,         1, 31},
-	{GPIO_EN_DP_SINK,               1, 80},
-	{GPIO_MST_RST_L,                1, 61},
-	{GPIO_EC_HUB2_RESET_L,          1, 41},
-	{GPIO_EC_HUB3_RESET_L,          1, 33},
-	{GPIO_DP_SINK_RESET,            1, 100},
-	{GPIO_USBC_UF_RESET_L,          1, 33},
-	{GPIO_DEMUX_DP_HDMI_PD_N,       1, 10},
-	{GPIO_DEMUX_DP_HDMI_MODE,       1, 5},
+	{ GPIO_EN_AC_JACK, 1, 20 },
+	{ GPIO_EC_DFU_MUX_CTRL, 0, 0 },
+	{ GPIO_EN_PP5000_A, 1, 31 },
+	{ GPIO_MST_LP_CTL_L, 1, 0 },
+	{ GPIO_EN_PP3300_B, 1, 1 },
+	{ GPIO_EN_PP1100_A, 1, 100 + 30 },
+	{ GPIO_EN_BB, 1, 30 },
+	{ GPIO_EN_PP1050_A, 1, 30 },
+	{ GPIO_EN_PP1200_A, 1, 20 },
+	{ GPIO_EN_PP5000_C, 1, 20 },
+	{ GPIO_EN_PP5000_HSPORT, 1, 31 },
+	{ GPIO_EN_DP_SINK, 1, 80 },
+	{ GPIO_MST_RST_L, 1, 61 },
+	{ GPIO_EC_HUB2_RESET_L, 1, 41 },
+	{ GPIO_EC_HUB3_RESET_L, 1, 33 },
+	{ GPIO_DP_SINK_RESET, 1, 100 },
+	{ GPIO_USBC_UF_RESET_L, 1, 33 },
+	{ GPIO_DEMUX_DP_HDMI_PD_N, 1, 10 },
+	{ GPIO_DEMUX_DP_HDMI_MODE, 1, 5 },
 };
 const size_t board_power_seq_count = ARRAY_SIZE(board_power_seq);
 
@@ -110,13 +110,13 @@ const size_t board_power_seq_count = ARRAY_SIZE(board_power_seq);
  * Define the strings used in our USB descriptors.
  */
 const void *const usb_strings[] = {
-	[USB_STR_DESC]         = usb_string_desc,
-	[USB_STR_VENDOR]       = USB_STRING_DESC("Acer"),
-	[USB_STR_PRODUCT]      = USB_STRING_DESC("D501"),
-	[USB_STR_SERIALNO]     = 0,
-	[USB_STR_VERSION]      =
-			USB_STRING_DESC(CROS_EC_SECTION ":" CROS_EC_VERSION32),
-	[USB_STR_UPDATE_NAME]  = USB_STRING_DESC("Firmware update"),
+	[USB_STR_DESC] = usb_string_desc,
+	[USB_STR_VENDOR] = USB_STRING_DESC("Acer"),
+	[USB_STR_PRODUCT] = USB_STRING_DESC("D501"),
+	[USB_STR_SERIALNO] = 0,
+	[USB_STR_VERSION] =
+		USB_STRING_DESC(CROS_EC_SECTION ":" CROS_EC_VERSION32),
+	[USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"),
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
 
@@ -135,8 +135,7 @@ struct ppc_config_t ppc_chips[] = {
  * PS8802 set mux board tuning.
  * Adds in board specific gain and DP lane count configuration
  */
-static int board_ps8822_mux_set(const struct usb_mux *me,
-				mux_state_t mux_state)
+static int board_ps8822_mux_set(const struct usb_mux *me, mux_state_t mux_state)
 {
 	int rv = EC_SUCCESS;
 
@@ -155,28 +154,26 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_HOST] = {
-		.usb_port = USB_PD_PORT_HOST,
-		.i2c_port = I2C_PORT_I2C1,
-		.i2c_addr_flags = PS8822_I2C_ADDR3_FLAG,
-		.driver = &ps8822_usb_mux_driver,
-		.board_set = &board_ps8822_mux_set,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_HOST,
+			.i2c_port = I2C_PORT_I2C1,
+			.i2c_addr_flags = PS8822_I2C_ADDR3_FLAG,
+			.driver = &ps8822_usb_mux_driver,
+			.board_set = &board_ps8822_mux_set,
+		},
 	},
 };
 
 /* USB-C PPC Configuration */
 struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_HOST] = {
-		.i2c_port = I2C_PORT_I2C1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	[USB_PD_PORT_USB3] = {
-		.i2c_port = I2C_PORT_I2C3,
-		.i2c_addr_flags = SN5S330_ADDR1_FLAGS,
-		.drv = &sn5s330_drv
-	},
+	[USB_PD_PORT_HOST] = { .i2c_port = I2C_PORT_I2C1,
+			       .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+			       .drv = &sn5s330_drv },
+	[USB_PD_PORT_USB3] = { .i2c_port = I2C_PORT_I2C3,
+			       .i2c_addr_flags = SN5S330_ADDR1_FLAGS,
+			       .drv = &sn5s330_drv },
 };
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
@@ -284,14 +281,13 @@ static void board_usb_tc_disconnect(void)
 	if (port == USB_PD_PORT_HOST)
 		gpio_set_level(GPIO_UFP_PLUG_DET, 1);
 }
-DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, board_usb_tc_disconnect, \
+DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, board_usb_tc_disconnect,
 	     HOOK_PRIO_DEFAULT);
 
 #endif /* SECTION_IS_RW */
 
 static void board_init(void)
 {
-
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
@@ -328,7 +324,7 @@ void board_debug_gpio(enum debug_gpio trigger, int level, int pulse_usec)
 	}
 }
 
-static int command_dplane(int argc, char **argv)
+static int command_dplane(int argc, const char **argv)
 {
 	char *e;
 	int lane;
@@ -356,6 +352,4 @@ static int command_dplane(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(dplane, command_dplane,
-			"<2 | 4>",
-			"MST lane control.");
+DECLARE_CONSOLE_COMMAND(dplane, command_dplane, "<2 | 4>", "MST lane control.");
diff --git a/board/baklava/board.h b/board/baklava/board.h
index e061d2342d..8cbe1cdc76 100644
--- a/board/baklava/board.h
+++ b/board/baklava/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,8 +21,8 @@
 #undef CONFIG_FLASH_PSTATE_LOCKED
 
 /* USB Type C and USB PD defines */
-#define USB_PD_PORT_HOST   0
-#define USB_PD_PORT_USB3   1
+#define USB_PD_PORT_HOST 0
+#define USB_PD_PORT_USB3 1
 
 /*
  * Only the host and display usbc ports are usb-pd capable. There is a 2nd usbc
@@ -40,9 +40,9 @@
 #define CONFIG_USB_PD_IDENTITY_SW_VERS 1
 
 /* I2C port names */
-#define I2C_PORT_I2C1	0
-#define I2C_PORT_I2C2	1
-#define I2C_PORT_I2C3	2
+#define I2C_PORT_I2C1 0
+#define I2C_PORT_I2C2 1
+#define I2C_PORT_I2C3 2
 
 /* Required symbolic I2C port names */
 #define I2C_PORT_MP4245 I2C_PORT_I2C3
@@ -68,7 +68,7 @@
 #define GPIO_TRIGGER_1 GPIO_USB3_A5_CDP_EN
 #define GPIO_TRIGGER_2 GPIO_USB3_A6_CDP_EN
 
-enum  debug_gpio {
+enum debug_gpio {
 	TRIGGER_1 = 0,
 	TRIGGER_2,
 };
diff --git a/board/baklava/build.mk b/board/baklava/build.mk
index 7e3e1240fd..258bafe87d 100644
--- a/board/baklava/build.mk
+++ b/board/baklava/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/baklava/ec.tasklist b/board/baklava/ec.tasklist
index 14c2c31393..a478fbe2e0 100644
--- a/board/baklava/ec.tasklist
+++ b/board/baklava/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/baklava/gpio.inc b/board/baklava/gpio.inc
index 144a5e3f8c..2745ae7caf 100644
--- a/board/baklava/gpio.inc
+++ b/board/baklava/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/banshee/battery.c b/board/banshee/battery.c
index 8143e6cec8..35d6a7a935 100644
--- a/board/banshee/battery.c
+++ b/board/banshee/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/banshee/board.c b/board/banshee/board.c
index 8f1d8bb811..611686f88d 100644
--- a/board/banshee/board.c
+++ b/board/banshee/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,14 +10,17 @@
 #include "common.h"
 #include "compile_time_macros.h"
 #include "console.h"
+#include "cros_board_info.h"
 #include "gpio.h"
 #include "gpio_signal.h"
 #include "hooks.h"
 #include "driver/als_tcs3400.h"
 #include "driver/charger/isl9241.h"
+#include "driver/retimer/bb_retimer.h"
 #include "fw_config.h"
 #include "hooks.h"
 #include "keyboard_customization.h"
+#include "keyboard_scan.h"
 #include "lid_switch.h"
 #include "power_button.h"
 #include "power.h"
@@ -25,22 +28,47 @@
 #include "switch.h"
 #include "throttle_ap.h"
 #include "usbc_config.h"
+#include "watchdog.h"
 
 #include "gpio_list.h" /* Must come after other header files. */
 
 /* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+
+/*
+ * USBA card connect to chromebook the USB_3_CONNECTION
+ * bit would be enable.
+ * It will increase BBR power consumption, so clear
+ * USB3_Connection bit in S0ix and enable when return S0.
+ */
+void set_bb_retimer_usb3_state(bool enable)
+{
+	mux_state_t mux_state = 0;
+
+	for (int i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		const struct usb_mux *mux = usb_muxes[i].mux;
+
+		mux_state = usb_mux_get(i);
+
+		if ((mux_state & USB_PD_MUX_USB_ENABLED)) {
+			bb_retimer_set_usb3(mux, enable);
+		}
+	}
+}
 
 /* Called on AP S3 -> S0 transition */
 static void board_chipset_resume(void)
 {
+	if (chipset_in_state(CHIPSET_STATE_ON))
+		set_bb_retimer_usb3_state(true);
 }
 DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
 
 /* Called on AP S0 -> S3 transition */
 static void board_chipset_suspend(void)
 {
+	set_bb_retimer_usb3_state(false);
 }
 DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
 
@@ -50,58 +78,97 @@ void board_set_charger_current_limit_deferred(void)
 	int rv;
 
 	if (extpower_is_present() &&
-		(battery_get_disconnect_state() != BATTERY_NOT_DISCONNECTED))
+	    (battery_get_disconnect_state() != BATTERY_NOT_DISCONNECTED))
 		/* AC only or AC+DC but battery is disconnect */
 		action = MASK_SET;
 	else
 		action = MASK_CLR;
 
 	rv = i2c_update16(chg_chips[CHARGER_SOLO].i2c_port,
-				chg_chips[CHARGER_SOLO].i2c_addr_flags,
-				ISL9241_REG_CONTROL3,
-				ISL9241_CONTROL3_INPUT_CURRENT_LIMIT, action);
+			  chg_chips[CHARGER_SOLO].i2c_addr_flags,
+			  ISL9241_REG_CONTROL3,
+			  ISL9241_CONTROL3_INPUT_CURRENT_LIMIT, action);
 
 	if (rv)
-		CPRINTF("Could not set charger input current limit! Error: %d\n"
-		, rv);
+		CPRINTF("Could not set charger input current limit! Error: %d\n",
+			rv);
 }
 
 DECLARE_DEFERRED(board_set_charger_current_limit_deferred);
 DECLARE_HOOK(HOOK_SECOND, board_set_charger_current_limit_deferred,
-	HOOK_PRIO_DEFAULT);
+	     HOOK_PRIO_DEFAULT);
 
 void battery_present_interrupt(enum gpio_signal signal)
 {
 	hook_call_deferred(&board_set_charger_current_limit_deferred_data, 0);
 }
 
-void board_init(void)
+static uint32_t board_id;
+static void configure_keyboard(void)
 {
-	int board_id = get_board_id();
+	uint32_t cbi_val;
 
-	gpio_enable_interrupt(GPIO_EC_BATT_PRES_ODL);
-	hook_call_deferred(&board_set_charger_current_limit_deferred_data, 0);
+	/* Board ID */
+	if (cbi_get_board_version(&cbi_val) != EC_SUCCESS ||
+	    cbi_val > UINT8_MAX)
+		CPRINTS("CBI: Read Board ID failed");
+	else
+		board_id = cbi_val;
+
+	CPRINTS("Read Board ID: %d", board_id);
 
 	if (board_id == 0) {
 		/* keyboard_col2_inverted on board id 0 */
 		gpio_set_flags(GPIO_EC_KSO_04_INV, GPIO_ODR_HIGH);
 		gpio_set_flags(GPIO_EC_KSO_05_INV, GPIO_ODR_HIGH);
 		gpio_set_alternate_function(GPIO_PORT_1, (BIT(4) | BIT(5)),
-			GPIO_ALT_FUNC_DEFAULT);
+					    GPIO_ALT_FUNC_DEFAULT);
 	} else if (board_id == 1) {
 		/* keyboard_col4_inverted on board id 1 */
 		gpio_set_flags(GPIO_EC_KSO_02_INV, GPIO_ODR_HIGH);
 		gpio_set_flags(GPIO_EC_KSO_05_INV, GPIO_ODR_HIGH);
 		gpio_set_alternate_function(GPIO_PORT_1, (BIT(4) | BIT(7)),
-			GPIO_ALT_FUNC_DEFAULT);
+					    GPIO_ALT_FUNC_DEFAULT);
 	} else {
 		/* keyboard_col5_inverted on board id 2 and later */
 		gpio_set_flags(GPIO_EC_KSO_02_INV, GPIO_ODR_HIGH);
 		gpio_set_flags(GPIO_EC_KSO_04_INV, GPIO_ODR_HIGH);
 		gpio_set_alternate_function(GPIO_PORT_1, (BIT(5) | BIT(7)),
-			GPIO_ALT_FUNC_DEFAULT);
+					    GPIO_ALT_FUNC_DEFAULT);
+		key_typ.col_refresh = KEYBOARD_COL_ID2_REFRESH;
+		key_typ.row_refresh = KEYBOARD_ROW_ID2_REFRESH;
 	}
 
-	board_id_keyboard_col_inverted(board_id);
+	board_id_keyboard_col_inverted((int)board_id);
+}
+
+void board_init(void)
+{
+	gpio_enable_interrupt(GPIO_EC_BATT_PRES_ODL);
+	hook_call_deferred(&board_set_charger_current_limit_deferred_data, 0);
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+__override void board_pre_task_i2c_peripheral_init(void)
+{
+	/* Configure board specific keyboard */
+	configure_keyboard();
+
+	/* Workaround for b:238683420 with board id >= 2 */
+
+#ifdef SECTION_IS_RO
+	if (board_id >= 2) {
+		udelay(500 * MSEC);
+		watchdog_reload();
+		CPRINTS("Add delay to check boot key");
+	}
+#endif
+}
+
+__override uint8_t board_keyboard_row_refresh(void)
+{
+	if (board_id < 2)
+		return KEYBOARD_ROW_ID1_REFRESH;
+	else
+		return KEYBOARD_ROW_ID2_REFRESH;
+}
diff --git a/board/banshee/board.h b/board/banshee/board.h
index e412fcc7d2..c456a17e68 100644
--- a/board/banshee/board.h
+++ b/board/banshee/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -35,6 +35,7 @@
 #define CONFIG_MP2964
 
 /* KEYBOARD */
+#define CONFIG_KEYBOARD_MULTIPLE
 #define CONFIG_KEYBOARD_CUSTOMIZATION
 #define CONFIG_KEYBOARD_VIVALDI
 
@@ -58,13 +59,12 @@
 /* Sensors without hardware FIFO are in forced mode */
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(CLEAR_ALS)
 
-
 /* USB Type C and USB PD defines */
 #define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
 
 #define CONFIG_IO_EXPANDER
 #define CONFIG_IO_EXPANDER_NCT38XX
-#define CONFIG_IO_EXPANDER_PORT_COUNT		4
+#define CONFIG_IO_EXPANDER_PORT_COUNT 4
 
 #define CONFIG_USB_PD_FRS_PPC
 
@@ -79,17 +79,17 @@
 #define CONFIG_USBC_PPC_SYV682X
 #define CONFIG_USB_PD_PPC
 
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
 
 /*
  * Passive USB-C cables only support up to 60W.
  */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /*
  * Macros for GPIO signals used in common code that don't match the
@@ -97,67 +97,68 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT		GPIO_EC_EN_EDP_BL
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_PACKET_MODE_EN		GPIO_EC_GSC_PACKET_MODE
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SYS_SLP_S0IX_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_TEMP_SENSOR_POWER		GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
 
 /*
  * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
  * signal.
  */
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_SEQ_EC_ALL_SYS_PG
-#define GPIO_PG_EC_DSW_PWROK		GPIO_SEQ_EC_DSW_PWROK
-#define GPIO_PG_EC_RSMRST_ODL		GPIO_SEQ_EC_RSMRST_ODL
-#define GPIO_POWER_BUTTON_L		GPIO_GSC_EC_PWR_BTN_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_ODL
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
 
-#define GPIO_ID_1_EC_KB_BL_EN		GPIO_EC_BATT_PRES_ODL
+#define GPIO_ID_1_EC_KB_BL_EN GPIO_EC_BATT_PRES_ODL
 
 /* System has back-lit keyboard */
 #define CONFIG_PWM_KBLIGHT
 
 /* I2C Bus Configuration */
 
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
 
-#define I2C_PORT_USB_C0_C1_TCPC	NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C2_C3_TCPC	NPCX_I2C_PORT4_1
+#define I2C_PORT_USB_C0_C1_TCPC NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C2_C3_TCPC NPCX_I2C_PORT4_1
 
-#define I2C_PORT_USB_PPC_BC12	NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_PPC_BC12 NPCX_I2C_PORT2_0
 
-#define I2C_PORT_USB_C0_C1_MUX	NPCX_I2C_PORT3_0
-#define I2C_PORT_USB_C2_C3_MUX	NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C0_C1_MUX NPCX_I2C_PORT3_0
+#define I2C_PORT_USB_C2_C3_MUX NPCX_I2C_PORT6_1
 
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT5_0
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT7_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-#define I2C_PORT_MP2964		NPCX_I2C_PORT7_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0
 
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 
-#define I2C_ADDR_MP2964_FLAGS	0x20
+#define I2C_ADDR_MP2964_FLAGS 0x20
 
-#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR	0x56
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x57
-#define USBC_PORT_C2_BB_RETIMER_I2C_ADDR	0x58
-#define USBC_PORT_C3_BB_RETIMER_I2C_ADDR	0x59
+#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x56
+#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x57
+#define USBC_PORT_C2_BB_RETIMER_I2C_ADDR 0x58
+#define USBC_PORT_C3_BB_RETIMER_I2C_ADDR 0x59
 
 /* Enabling Thunderbolt-compatible mode */
 #define CONFIG_USB_PD_TBT_COMPAT_MODE
 
 /* Enabling USB4 mode */
 #define CONFIG_USB_PD_USB4
+#define CONFIG_USB_PD_DATA_RESET_MSG
 
 /*
  * TODO: Disable BBR firmware update temporally,
@@ -175,13 +176,13 @@
 #define CONFIG_TEMP_SENSOR_POWER
 #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
 
-#define CONFIG_FANS			FAN_CH_COUNT
+#define CONFIG_FANS FAN_CH_COUNT
 
 /* Charger defines */
 #define CONFIG_CHARGER_ISL9241
 #define CONFIG_CHARGE_RAMP_SW
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	20
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20
 
 /*
  * Older boards have a different ADC assignment.
@@ -191,10 +192,19 @@
 
 #ifndef __ASSEMBLER__
 
-#include "gpio_signal.h"	/* needed by registers.h */
+#include "gpio_signal.h" /* needed by registers.h */
 #include "registers.h"
 #include "usbc_config.h"
 
+/* I2C access in polling mode before task is initialized */
+#define CONFIG_I2C_BITBANG
+
+enum banshee_bitbang_i2c_channel {
+	I2C_BITBANG_CHAN_BRD_ID,
+	I2C_BITBANG_CHAN_COUNT
+};
+#define I2C_BITBANG_PORT_COUNT I2C_BITBANG_CHAN_COUNT
+
 enum adc_channel {
 	ADC_TEMP_SENSOR_1_DDR_SOC,
 	ADC_TEMP_SENSOR_2_AMBIENT,
@@ -209,10 +219,7 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum sensor_id {
-	CLEAR_ALS = 0,
-	SENSOR_COUNT
-};
+enum sensor_id { CLEAR_ALS = 0, SENSOR_COUNT };
 
 enum ioex_port {
 	IOEX_C0_NCT38XX = 0,
@@ -222,30 +229,21 @@ enum ioex_port {
 	IOEX_PORT_COUNT
 };
 
-enum battery_type {
-	BATTERY_NVT,
-	BATTERY_TYPE_COUNT
-};
+enum battery_type { BATTERY_NVT, BATTERY_TYPE_COUNT };
 
 enum pwm_channel {
-	PWM_CH_SIDE_LED_R = 0,		/* PWM0 (Red charger) */
-	PWM_CH_SIDE_LED_G,			/* PWM1 (Green charger) */
-	PWM_CH_SIDE_LED_B,			/* PWM2 (Blue charger) */
-	PWM_CH_KBLIGHT,				/* PWM3 */
-	PWM_CH_FAN,					/* PWM5 */
-	PWM_CH_POWER_LED_W,			/* PWM7 (white LED) */
+	PWM_CH_SIDE_LED_R = 0, /* PWM0 (Red charger) */
+	PWM_CH_SIDE_LED_G, /* PWM1 (Green charger) */
+	PWM_CH_SIDE_LED_B, /* PWM2 (Blue charger) */
+	PWM_CH_KBLIGHT, /* PWM3 */
+	PWM_CH_FAN, /* PWM5 */
+	PWM_CH_POWER_LED_W, /* PWM7 (white LED) */
 	PWM_CH_COUNT
 };
 
-enum fan_channel {
-	FAN_CH_0 = 0,
-	FAN_CH_COUNT
-};
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT };
 
-enum mft_channel {
-	MFT_CH_0 = 0,
-	MFT_CH_COUNT
-};
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT };
 
 void battery_present_interrupt(enum gpio_signal signal);
 
diff --git a/board/banshee/build.mk b/board/banshee/build.mk
index 88621dd44b..78c675a67a 100644
--- a/board/banshee/build.mk
+++ b/board/banshee/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -22,6 +22,5 @@ board-y+=keyboard.o
 board-y+=led.o
 board-y+=pwm.o
 board-y+=sensors.o
-board-y+=tune_mp2964.o
 board-y+=usbc_config.o
 board-y+=keyboard_customization.o
diff --git a/board/banshee/charger.c b/board/banshee/charger.c
index 85e0de90fe..88f5b85a41 100644
--- a/board/banshee/charger.c
+++ b/board/banshee/charger.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,9 +15,8 @@
 #include "usb_pd.h"
 #include "util.h"
 
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* Charger Chip Configuration */
 const struct charger_config_t chg_chips[] = {
@@ -84,7 +83,6 @@ int board_set_active_charge_port(int port)
 __overridable void board_set_charge_limit(int port, int supplier, int charge_ma,
 					  int max_ma, int charge_mv)
 {
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
diff --git a/board/banshee/ec.tasklist b/board/banshee/ec.tasklist
index 0b8d0e412b..b193da8f9f 100644
--- a/board/banshee/ec.tasklist
+++ b/board/banshee/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/banshee/fans.c b/board/banshee/fans.c
index 73bd0dcd77..0658dc8859 100644
--- a/board/banshee/fans.c
+++ b/board/banshee/fans.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,7 +25,7 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 static const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
diff --git a/board/banshee/fw_config.c b/board/banshee/fw_config.c
index 2ce200cc4f..dc7fe7ca2a 100644
--- a/board/banshee/fw_config.c
+++ b/board/banshee/fw_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,7 +10,7 @@
 #include "cros_board_info.h"
 #include "fw_config.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 static union banshee_cbi_fw_config fw_config;
 BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
diff --git a/board/banshee/fw_config.h b/board/banshee/fw_config.h
index 6800c492ad..912aebca7e 100644
--- a/board/banshee/fw_config.h
+++ b/board/banshee/fw_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,7 +14,6 @@
  * Source of truth is the project/brya/brya/config.star configuration file.
  */
 
-
 enum ec_cfg_keyboard_backlight_type {
 	KEYBOARD_BACKLIGHT_DISABLED = 0,
 	KEYBOARD_BACKLIGHT_ENABLED = 1
@@ -22,11 +21,11 @@ enum ec_cfg_keyboard_backlight_type {
 
 union banshee_cbi_fw_config {
 	struct {
-		uint32_t				sd_db : 2;
-		uint32_t				lte_db : 1;
-		enum ec_cfg_keyboard_backlight_type	kb_bl : 1;
-		uint32_t				audio : 3;
-		uint32_t				reserved_1 : 21;
+		uint32_t sd_db : 2;
+		uint32_t lte_db : 1;
+		enum ec_cfg_keyboard_backlight_type kb_bl : 1;
+		uint32_t audio : 3;
+		uint32_t reserved_1 : 21;
 	};
 	uint32_t raw_value;
 };
diff --git a/board/banshee/gpio.inc b/board/banshee/gpio.inc
index 2a0e90e675..e33fa5ec06 100644
--- a/board/banshee/gpio.inc
+++ b/board/banshee/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2022 The Chromium OS Authors. All rights reserved.
+ * Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/banshee/i2c.c b/board/banshee/i2c.c
index ed92cfbf82..ea3fd38e62 100644
--- a/board/banshee/i2c.c
+++ b/board/banshee/i2c.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,8 +7,9 @@
 #include "compile_time_macros.h"
 #include "hooks.h"
 #include "i2c.h"
+#include "i2c_bitbang.h"
 
-#define BOARD_ID_FAST_PLUS_CAPABLE	2
+#define BOARD_ID_FAST_PLUS_CAPABLE 2
 
 /* I2C port map configuration */
 const struct i2c_port_t i2c_ports[] = {
@@ -40,7 +41,7 @@ const struct i2c_port_t i2c_ports[] = {
 		/* I2C3 */
 		.name = "retimer0,1",
 		.port = I2C_PORT_USB_C0_C1_MUX,
-		.kbps = 1000,
+		.kbps = 400,
 		.scl = GPIO_EC_I2C_USB_C0_C1_RT_SCL,
 		.sda = GPIO_EC_I2C_USB_C0_C1_RT_SDA,
 	},
@@ -64,7 +65,7 @@ const struct i2c_port_t i2c_ports[] = {
 		/* I2C6 */
 		.name = "retimer2,3",
 		.port = I2C_PORT_USB_C2_C3_MUX,
-		.kbps = 1000,
+		.kbps = 400,
 		.scl = GPIO_EC_I2C_USB_C2_C3_RT_SCL,
 		.sda = GPIO_EC_I2C_USB_C2_C3_RT_SDA,
 	},
@@ -78,3 +79,16 @@ const struct i2c_port_t i2c_ports[] = {
 	},
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+const struct i2c_port_t i2c_bitbang_ports[] = {
+	[I2C_BITBANG_CHAN_BRD_ID] = {
+		.name = "bitbang_brd_id",
+		.port = I2C_PORT_EEPROM,
+		.kbps = 100,
+		.scl = GPIO_EC_I2C_MISC_SCL_R,
+		.sda = GPIO_EC_I2C_MISC_SDA_R,
+		.drv = &bitbang_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(i2c_bitbang_ports) == I2C_BITBANG_CHAN_COUNT);
+const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
diff --git a/board/banshee/keyboard.c b/board/banshee/keyboard.c
index 3891955b46..928f02e025 100644
--- a/board/banshee/keyboard.c
+++ b/board/banshee/keyboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -63,8 +63,8 @@ static const struct ec_response_keybd_config banshee_kb_id2 = {
 	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
 };
 
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	if (get_board_id() <= 1)
 		return &banshee_kb_id1;
@@ -81,20 +81,20 @@ __override const struct key {
 	uint8_t row;
 	uint8_t col;
 } vivaldi_keys[] = {
-	{.row = 3, .col = 5},	/* T1 */
-	{.row = 2, .col = 5},	/* T2 */
-	{.row = 6, .col = 4},	/* T3 */
-	{.row = 3, .col = 4},	/* T4 */
-	{.row = 4, .col = 10},	/* T5 */
-	{.row = 3, .col = 10},	/* T6 */
-	{.row = 2, .col = 10},	/* T7 */
-	{.row = 1, .col = 15},	/* T8 */
-	{.row = 3, .col = 11},	/* T9 */
-	{.row = 4, .col = 8},	/* T10 */
-	{.row = 6, .col = 8},	/* T11 */
-	{.row = 3, .col = 13},	/* T12 */
-	{.row = 3, .col = 5},	/* T13 */
-	{.row = 0, .col = 9},	/* T14 */
-	{.row = 0, .col = 11},	/* T15 */
+	{ .row = 3, .col = 5 }, /* T1 */
+	{ .row = 2, .col = 5 }, /* T2 */
+	{ .row = 6, .col = 4 }, /* T3 */
+	{ .row = 3, .col = 4 }, /* T4 */
+	{ .row = 4, .col = 10 }, /* T5 */
+	{ .row = 3, .col = 10 }, /* T6 */
+	{ .row = 2, .col = 10 }, /* T7 */
+	{ .row = 1, .col = 15 }, /* T8 */
+	{ .row = 3, .col = 11 }, /* T9 */
+	{ .row = 4, .col = 8 }, /* T10 */
+	{ .row = 6, .col = 8 }, /* T11 */
+	{ .row = 3, .col = 13 }, /* T12 */
+	{ .row = 3, .col = 5 }, /* T13 */
+	{ .row = 0, .col = 9 }, /* T14 */
+	{ .row = 0, .col = 11 }, /* T15 */
 };
 BUILD_ASSERT(ARRAY_SIZE(vivaldi_keys) == MAX_TOP_ROW_KEYS);
diff --git a/board/banshee/keyboard_customization.c b/board/banshee/keyboard_customization.c
index cf6904cb37..dfec873343 100644
--- a/board/banshee/keyboard_customization.c
+++ b/board/banshee/keyboard_customization.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,30 +10,30 @@
 #include "keyboard_config.h"
 #include "keyboard_protocol.h"
 #include "keyboard_raw.h"
+#include "keyboard_scan.h"
 
 enum gpio_signal signal;
 static int colinv;
 
 static uint16_t scancode_set2[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = {
-	{0x0021, 0x007B, 0x0079, 0x0072, 0x007A, 0x0071, 0x0069, 0xe04A},
-	{0x002f, 0xe070, 0x007D, 0xe01f, 0x006c, 0xe06c, 0xe07d, 0x0077},
-	{0x0015, 0x0070, 0x00ff, 0x000D, 0x000E, 0x0016, 0x0067, 0x001c},
-	{0xe011, 0x0011, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
-	{0xe05a, 0x0029, 0x0024, 0xe01d, 0xe01f, 0x0026, 0xe020, 0xe07a},
-	{0x0022, 0x001a, 0xe030, 0xe038, 0x001b, 0x001e, 0x001d, 0x0076},
-	{0x002A, 0x0032, 0x0034, 0x002c, 0x002e, 0x0025, 0x002d, 0x002b},
-	{0x003a, 0x0031, 0x0033, 0x0035, 0x0036, 0x003d, 0x003c, 0x003b},
-	{0x0049, 0xe072, 0x005d, 0x0044, 0xe023, 0x0046, 0xe021, 0x004b},
-	{0x0059, 0x0012, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
-	{0x0041, 0x007c, 0xe02c, 0xe02d, 0xe024, 0x003e, 0x0043, 0x0042},
-	{0x0013, 0x0064, 0x0075, 0xe054, 0x0051, 0x0061, 0xe06b, 0xe02f},
-	{0xe014, 0x0014, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
-	{0x004a, 0xe075, 0x004e, 0xe032, 0x0045, 0x004d, 0x0054, 0x004c},
-	{0x0052, 0x005a, 0xe03c, 0xe069, 0x0055, 0x0066, 0x005b, 0x0023},
-	{0x006a, 0xe035, 0xe074, 0xe054, 0x0000, 0x006b, 0x0073, 0x0074},
+	{ 0x0021, 0x007B, 0x0079, 0x0072, 0x007A, 0x0071, 0x0069, 0xe04A },
+	{ 0x002f, 0xe070, 0x007D, 0xe01f, 0x006c, 0xe06c, 0xe07d, 0x0077 },
+	{ 0x0015, 0x0070, 0x00ff, 0x000D, 0x000E, 0x0016, 0x0067, 0x001c },
+	{ 0xe011, 0x0011, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 },
+	{ 0xe05a, 0x0029, 0x0024, 0xe01d, 0xe01f, 0x0026, 0xe020, 0xe07a },
+	{ 0x0022, 0x001a, 0xe030, 0xe038, 0x001b, 0x001e, 0x001d, 0x0076 },
+	{ 0x002A, 0x0032, 0x0034, 0x002c, 0x002e, 0x0025, 0x002d, 0x002b },
+	{ 0x003a, 0x0031, 0x0033, 0x0035, 0x0036, 0x003d, 0x003c, 0x003b },
+	{ 0x0049, 0xe072, 0x005d, 0x0044, 0xe023, 0x0046, 0xe021, 0x004b },
+	{ 0x0059, 0x0012, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 },
+	{ 0x0041, 0x007c, 0xe02c, 0xe02d, 0xe024, 0x003e, 0x0043, 0x0042 },
+	{ 0x0013, 0x0064, 0x0075, 0xe054, 0x0051, 0x0061, 0xe06b, 0xe02f },
+	{ 0xe014, 0x0014, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 },
+	{ 0x004a, 0xe075, 0x004e, 0xe032, 0x0045, 0x004d, 0x0054, 0x004c },
+	{ 0x0052, 0x005a, 0xe03c, 0xe069, 0x0055, 0x0066, 0x005b, 0x0023 },
+	{ 0x006a, 0xe035, 0xe074, 0xe054, 0x0000, 0x006b, 0x0073, 0x0074 },
 };
 
-
 uint16_t get_scancode_set2(uint8_t row, uint8_t col)
 {
 	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS)
@@ -47,6 +47,25 @@ void set_scancode_set2(uint8_t row, uint8_t col, uint16_t val)
 		scancode_set2[col][row] = val;
 }
 
+struct keyboard_type key_typ = {
+	.col_esc = KEYBOARD_COL_ESC,
+	.row_esc = KEYBOARD_ROW_ESC,
+	.col_down = KEYBOARD_COL_DOWN,
+	.row_down = KEYBOARD_ROW_DOWN,
+	.col_left_shift = KEYBOARD_COL_LEFT_SHIFT,
+	.row_left_shift = KEYBOARD_ROW_LEFT_SHIFT,
+	.col_refresh = KEYBOARD_COL_ID1_REFRESH,
+	.row_refresh = KEYBOARD_ROW_ID1_REFRESH,
+	.col_right_alt = KEYBOARD_COL_RIGHT_ALT,
+	.row_right_alt = KEYBOARD_ROW_RIGHT_ALT,
+	.col_left_alt = KEYBOARD_COL_LEFT_ALT,
+	.row_left_alt = KEYBOARD_ROW_LEFT_ALT,
+	.col_key_r = KEYBOARD_COL_KEY_R,
+	.row_key_r = KEYBOARD_ROW_KEY_R,
+	.col_key_h = KEYBOARD_COL_KEY_H,
+	.row_key_h = KEYBOARD_ROW_KEY_H,
+};
+
 void board_id_keyboard_col_inverted(int board_id)
 {
 	if (board_id == 0) {
@@ -85,38 +104,30 @@ void board_keyboard_drive_col(int col)
 
 #ifdef CONFIG_KEYBOARD_DEBUG
 static char keycap_label[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = {
-	{'c',        KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
-		KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO},
-	{KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
-		KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO},
-	{'q',        KLLI_UNKNO, KLLI_UNKNO, KLLI_TAB,   '`',
-		'1',        KLLI_UNKNO, 'a'},
-	{KLLI_R_ALT, KLLI_L_ALT, KLLI_UNKNO, KLLI_UNKNO,
-		KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO},
-	{KLLI_UNKNO, KLLI_SPACE, 'e',        KLLI_F4,
-		KLLI_SEARC, '3',        KLLI_F3,    KLLI_UNKNO},
-	{'x',        'z',        KLLI_F2,    KLLI_F1,
-		's',        '2',        'w',        KLLI_ESC},
-	{'v',        'b',        'g',        't',
-		'5',        '4',        'r',        'f'},
-	{'m',        'n',        'h',        'y',
-		'6',        '7',        'u',        'j'},
-	{'.',        KLLI_DOWN,  '\\',       'o',
-		KLLI_F10,   '9',        KLLI_UNKNO, 'l'},
-	{KLLI_R_SHT, KLLI_L_SHT, KLLI_UNKNO, KLLI_UNKNO,
-		KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO},
-	{',',        KLLI_UNKNO, KLLI_F7,    KLLI_F6,
-		KLLI_F5,    '8',        'i',        'k'},
-	{KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_F9,
-		KLLI_UNKNO, KLLI_UNKNO, KLLI_LEFT,  KLLI_UNKNO},
-	{KLLI_R_CTR, KLLI_L_CTR, KLLI_UNKNO, KLLI_UNKNO,
-		KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO},
-	{'/',        KLLI_UP,    '-',        KLLI_UNKNO,
-		'0',        'p',        '[',        ';'},
-	{'\'',       KLLI_ENTER, KLLI_UNKNO, KLLI_UNKNO,
-		'=',        KLLI_B_SPC, ']',        'd'},
-	{KLLI_UNKNO, KLLI_F8,    KLLI_RIGHT, KLLI_UNKNO,
-		KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO},
+	{ 'c', KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO },
+	{ KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO },
+	{ 'q', KLLI_UNKNO, KLLI_UNKNO, KLLI_TAB, '`', '1', KLLI_UNKNO, 'a' },
+	{ KLLI_R_ALT, KLLI_L_ALT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO },
+	{ KLLI_UNKNO, KLLI_SPACE, 'e', KLLI_F4, KLLI_SEARC, '3', KLLI_F3,
+	  KLLI_UNKNO },
+	{ 'x', 'z', KLLI_F2, KLLI_F1, 's', '2', 'w', KLLI_ESC },
+	{ 'v', 'b', 'g', 't', '5', '4', 'r', 'f' },
+	{ 'm', 'n', 'h', 'y', '6', '7', 'u', 'j' },
+	{ '.', KLLI_DOWN, '\\', 'o', KLLI_F10, '9', KLLI_UNKNO, 'l' },
+	{ KLLI_R_SHT, KLLI_L_SHT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO },
+	{ ',', KLLI_UNKNO, KLLI_F7, KLLI_F6, KLLI_F5, '8', 'i', 'k' },
+	{ KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_F9, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_LEFT, KLLI_UNKNO },
+	{ KLLI_R_CTR, KLLI_L_CTR, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO },
+	{ '/', KLLI_UP, '-', KLLI_UNKNO, '0', 'p', '[', ';' },
+	{ '\'', KLLI_ENTER, KLLI_UNKNO, KLLI_UNKNO, '=', KLLI_B_SPC, ']', 'd' },
+	{ KLLI_UNKNO, KLLI_F8, KLLI_RIGHT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO },
 };
 
 char get_keycap_label(uint8_t row, uint8_t col)
diff --git a/board/banshee/keyboard_customization.h b/board/banshee/keyboard_customization.h
index 18043d7453..1b4994ded0 100644
--- a/board/banshee/keyboard_customization.h
+++ b/board/banshee/keyboard_customization.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,52 +25,53 @@ extern uint8_t keyboard_cols;
 #define KEYBOARD_ROW_TO_MASK(r) (1 << (r))
 
 /* Columns and masks for keys we particularly care about */
-#define KEYBOARD_COL_DOWN	8
-#define KEYBOARD_ROW_DOWN	1
-#define KEYBOARD_MASK_DOWN	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_DOWN)
-#define KEYBOARD_COL_ESC	5
-#define KEYBOARD_ROW_ESC	7
-#define KEYBOARD_MASK_ESC	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_ESC)
-#define KEYBOARD_COL_KEY_H	7
-#define KEYBOARD_ROW_KEY_H	2
-#define KEYBOARD_MASK_KEY_H	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_H)
-#define KEYBOARD_COL_KEY_R	6
-#define KEYBOARD_ROW_KEY_R	6
-#define KEYBOARD_MASK_KEY_R	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_R)
-#define KEYBOARD_COL_LEFT_ALT	3
-#define KEYBOARD_ROW_LEFT_ALT	1
-#define KEYBOARD_MASK_LEFT_ALT	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_ALT)
-#define KEYBOARD_COL_REFRESH	4
-#define KEYBOARD_ROW_REFRESH	6
-#define KEYBOARD_MASK_REFRESH	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_REFRESH)
-#define KEYBOARD_COL_RIGHT_ALT	3
-#define KEYBOARD_ROW_RIGHT_ALT	0
-#define KEYBOARD_MASK_RIGHT_ALT	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_ALT)
-#define KEYBOARD_DEFAULT_COL_VOL_UP	13
-#define KEYBOARD_DEFAULT_ROW_VOL_UP	3
-#define KEYBOARD_COL_LEFT_CTRL  12
-#define KEYBOARD_ROW_LEFT_CTRL  1
+#define KEYBOARD_COL_DOWN 8
+#define KEYBOARD_ROW_DOWN 1
+#define KEYBOARD_MASK_DOWN KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_DOWN)
+#define KEYBOARD_COL_ESC 5
+#define KEYBOARD_ROW_ESC 7
+#define KEYBOARD_MASK_ESC KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_ESC)
+#define KEYBOARD_COL_KEY_H 7
+#define KEYBOARD_ROW_KEY_H 2
+#define KEYBOARD_MASK_KEY_H KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_H)
+#define KEYBOARD_COL_KEY_R 6
+#define KEYBOARD_ROW_KEY_R 6
+#define KEYBOARD_MASK_KEY_R KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_R)
+#define KEYBOARD_COL_LEFT_ALT 3
+#define KEYBOARD_ROW_LEFT_ALT 1
+#define KEYBOARD_MASK_LEFT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_ALT)
+#define KEYBOARD_COL_ID1_REFRESH 4
+#define KEYBOARD_ROW_ID1_REFRESH 6
+#define KEYBOARD_COL_ID2_REFRESH 5
+#define KEYBOARD_ROW_ID2_REFRESH 2
+#define KEYBOARD_MASK_REFRESH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_ID1_REFRESH)
+#define KEYBOARD_COL_RIGHT_ALT 3
+#define KEYBOARD_ROW_RIGHT_ALT 0
+#define KEYBOARD_MASK_RIGHT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_ALT)
+#define KEYBOARD_DEFAULT_COL_VOL_UP 13
+#define KEYBOARD_DEFAULT_ROW_VOL_UP 3
+#define KEYBOARD_COL_LEFT_CTRL 12
+#define KEYBOARD_ROW_LEFT_CTRL 1
 #define KEYBOARD_MASK_LEFT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_CTRL)
 #define KEYBOARD_COL_RIGHT_CTRL 12
 #define KEYBOARD_ROW_RIGHT_CTRL 0
 #define KEYBOARD_MASK_RIGHT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_CTRL)
-#define KEYBOARD_COL_SEARCH     4
-#define KEYBOARD_ROW_SEARCH     4
-#define KEYBOARD_MASK_SEARCH    KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_SEARCH)
-#define KEYBOARD_COL_KEY_0      13
-#define KEYBOARD_ROW_KEY_0      4
-#define KEYBOARD_MASK_KEY_0     KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_0)
-#define KEYBOARD_COL_KEY_1      2
-#define KEYBOARD_ROW_KEY_1      5
-#define KEYBOARD_MASK_KEY_1     KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_1)
-#define KEYBOARD_COL_KEY_2      5
-#define KEYBOARD_ROW_KEY_2      5
-#define KEYBOARD_MASK_KEY_2     KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_2)
+#define KEYBOARD_COL_SEARCH 4
+#define KEYBOARD_ROW_SEARCH 4
+#define KEYBOARD_MASK_SEARCH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_SEARCH)
+#define KEYBOARD_COL_KEY_0 13
+#define KEYBOARD_ROW_KEY_0 4
+#define KEYBOARD_MASK_KEY_0 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_0)
+#define KEYBOARD_COL_KEY_1 2
+#define KEYBOARD_ROW_KEY_1 5
+#define KEYBOARD_MASK_KEY_1 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_1)
+#define KEYBOARD_COL_KEY_2 5
+#define KEYBOARD_ROW_KEY_2 5
+#define KEYBOARD_MASK_KEY_2 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_2)
 #define KEYBOARD_COL_LEFT_SHIFT 9
 #define KEYBOARD_ROW_LEFT_SHIFT 1
 #define KEYBOARD_MASK_LEFT_SHIFT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_SHIFT)
 
 void board_id_keyboard_col_inverted(int board_id);
 
-
 #endif /* __KEYBOARD_CUSTOMIZATION_H */
diff --git a/board/banshee/led.c b/board/banshee/led.c
index b1c6a6445f..1471388085 100644
--- a/board/banshee/led.c
+++ b/board/banshee/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -28,16 +28,15 @@
 #define LED_TICKS_PER_CYCLE 10
 #define LED_ON_TICKS 5
 
-#define BREATH_LIGHT_LENGTH	55
-#define BREATH_HOLD_LENGTH	50
-#define BREATH_OFF_LENGTH	200
+#define BREATH_LIGHT_LENGTH 100
+#define BREATH_HOLD_LENGTH 50
+#define BREATH_OFF_LENGTH 200
 
 const enum ec_led_id supported_led_ids[] = {
 	EC_LED_ID_BATTERY_LED,
 	EC_LED_ID_POWER_LED,
 };
 
-
 enum breath_status {
 	BREATH_LIGHT_UP = 0,
 	BREATH_LIGHT_DOWN,
@@ -45,26 +44,23 @@ enum breath_status {
 	BREATH_OFF,
 };
 
-enum led_port {
-	RIGHT_PORT = 1,
-	LEFT_PORT
-};
+enum led_port { RIGHT_PORT = 1, LEFT_PORT };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = {
-				/* Red, Green, Blue */
-	[EC_LED_COLOR_RED]    = {  50,   0,   0 },
-	[EC_LED_COLOR_GREEN]  = {   0,  50,   0 },
-	[EC_LED_COLOR_BLUE]   = {   0,   0,   8 },
-	[EC_LED_COLOR_YELLOW] = {  40,  50,   0 },
-	[EC_LED_COLOR_WHITE]  = {  20,  50,  25 },
-	[EC_LED_COLOR_AMBER]  = {  45,  5,    0 },
+	/* Red, Green, Blue */
+	[EC_LED_COLOR_RED] = { 50, 0, 0 },
+	[EC_LED_COLOR_GREEN] = { 0, 50, 0 },
+	[EC_LED_COLOR_BLUE] = { 0, 0, 8 },
+	[EC_LED_COLOR_YELLOW] = { 40, 50, 0 },
+	[EC_LED_COLOR_WHITE] = { 4, 10, 5 },
+	[EC_LED_COLOR_AMBER] = { 45, 5, 0 },
 };
 
 struct pwm_led_color_map pwr_led_color_map[EC_LED_COLOR_COUNT] = {
-				/* White, Green, Red */
-	[EC_LED_COLOR_WHITE]  = {  BREATH_LIGHT_LENGTH,   0,   0 },
+	/* White, Green, Red */
+	[EC_LED_COLOR_WHITE] = { BREATH_LIGHT_LENGTH, 0, 0 },
 };
 
 /*
@@ -88,13 +84,11 @@ struct pwm_led pwm_leds[CONFIG_LED_PWM_COUNT] = {
 	},
 };
 
-
 uint8_t breath_led_light_up;
 uint8_t breath_led_light_down;
 uint8_t breath_led_hold;
 uint8_t breath_led_off;
 
-
 int breath_pwm_enable;
 int breath_led_status;
 static void breath_led_pwm_deferred(void);
@@ -102,21 +96,19 @@ DECLARE_DEFERRED(breath_led_pwm_deferred);
 
 /*
  *	Breath LED API
- *	Max duty (percentage) = BREATH_LIGHT_LENGTH (55%)
- *	Fade time (second) = 550ms(In) / 550ms(Out)
+ *	Max duty (percentage) = BREATH_LIGHT_LENGTH (100%)
+ *	Fade time (second) = 1000ms(In) / 1000ms(Out)
  *	Duration time (second) = BREATH_HOLD_LENGTH(500ms)
  *	Interval time (second) = BREATH_OFF_LENGTH(2000ms)
  */
 
 static void breath_led_pwm_deferred(void)
 {
-
 	switch (breath_led_status) {
 	case BREATH_LIGHT_UP:
 
-		if (breath_led_light_up <=  BREATH_LIGHT_LENGTH)
-			pwm_set_duty(PWM_CH_POWER_LED_W,
-					breath_led_light_up++);
+		if (breath_led_light_up <= BREATH_LIGHT_LENGTH)
+			pwm_set_duty(PWM_CH_POWER_LED_W, breath_led_light_up++);
 		else {
 			breath_led_light_up = 0;
 			breath_led_light_down = BREATH_LIGHT_LENGTH;
@@ -126,7 +118,7 @@ static void breath_led_pwm_deferred(void)
 		break;
 	case BREATH_HOLD:
 
-		if (breath_led_hold <=  BREATH_HOLD_LENGTH)
+		if (breath_led_hold <= BREATH_HOLD_LENGTH)
 			breath_led_hold++;
 		else {
 			breath_led_hold = 0;
@@ -138,7 +130,7 @@ static void breath_led_pwm_deferred(void)
 
 		if (breath_led_light_down != 0)
 			pwm_set_duty(PWM_CH_POWER_LED_W,
-					breath_led_light_down--);
+				     breath_led_light_down--);
 		else {
 			breath_led_light_down = BREATH_LIGHT_LENGTH;
 			breath_led_status = BREATH_OFF;
@@ -147,7 +139,7 @@ static void breath_led_pwm_deferred(void)
 		break;
 	case BREATH_OFF:
 
-		if (breath_led_off <=  BREATH_OFF_LENGTH)
+		if (breath_led_off <= BREATH_OFF_LENGTH)
 			breath_led_off++;
 		else {
 			breath_led_off = 0;
@@ -157,12 +149,10 @@ static void breath_led_pwm_deferred(void)
 		break;
 	}
 
-
 	if (breath_pwm_enable)
 		hook_call_deferred(&breath_led_pwm_deferred_data, 10 * MSEC);
 }
 
-
 void breath_led_run(uint8_t enable)
 {
 	if (enable && !breath_pwm_enable) {
@@ -180,7 +170,6 @@ void breath_led_run(uint8_t enable)
 	}
 }
 
-
 void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
 {
 	if (led_id == EC_LED_ID_BATTERY_LED) {
@@ -192,7 +181,6 @@ void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
 		brightness_range[EC_LED_COLOR_WHITE] = 100;
 	} else if (led_id == EC_LED_ID_POWER_LED)
 		brightness_range[EC_LED_COLOR_WHITE] = 100;
-
 }
 
 void set_pwr_led_color(enum pwm_led_id id, int color)
@@ -265,8 +253,8 @@ static int led_get_charge_percent(void)
 static void select_active_port_led(int port)
 {
 	if ((charge_get_state() == PWR_STATE_DISCHARGE &&
-			 led_get_charge_percent() < 10) ||
-			 charge_get_state() == PWR_STATE_ERROR) {
+	     led_get_charge_percent() < 10) ||
+	    charge_get_state() == PWR_STATE_ERROR) {
 		gpio_set_level(GPIO_LEFT_SIDE, 1);
 		gpio_set_level(GPIO_RIGHT_SIDE, 1);
 	} else if (port == RIGHT_PORT) {
@@ -283,8 +271,7 @@ static void select_active_port_led(int port)
 
 static int led_power_enable(void)
 {
-	if (gpio_get_level(GPIO_LEFT_SIDE) ||
-		gpio_get_level(GPIO_RIGHT_SIDE))
+	if (gpio_get_level(GPIO_LEFT_SIDE) || gpio_get_level(GPIO_RIGHT_SIDE))
 		return true;
 
 	return false;
@@ -309,7 +296,6 @@ static void set_active_port_color(int color)
 static void led_set_battery(void)
 {
 	static int battery_ticks;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
@@ -322,38 +308,43 @@ static void led_set_battery(void)
 		if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
 			if (led_get_charge_percent() < 10)
 				set_active_port_color((battery_ticks & 0x2) ?
-					EC_LED_COLOR_RED : -1);
+							      EC_LED_COLOR_RED :
+							      -1);
 			else
 				set_active_port_color(-1);
 		}
 		break;
 	case PWR_STATE_ERROR:
-		set_active_port_color((battery_ticks & 0x2) ?
-				EC_LED_COLOR_RED : -1);
+		set_active_port_color((battery_ticks & 0x2) ? EC_LED_COLOR_RED :
+							      -1);
 		break;
 	case PWR_STATE_CHARGE_NEAR_FULL:
-		set_active_port_color(EC_LED_COLOR_GREEN);
+		set_active_port_color(EC_LED_COLOR_WHITE);
 		break;
 	case PWR_STATE_IDLE:
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			set_active_port_color((battery_ticks & 0x4) ?
-					EC_LED_COLOR_AMBER : -1);
-		else
-			set_active_port_color(EC_LED_COLOR_AMBER);
+		set_active_port_color(EC_LED_COLOR_AMBER);
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		set_active_port_color(
+			(battery_ticks & 0x4) ? EC_LED_COLOR_AMBER : -1);
 		break;
 	default:
 		break;
 	}
-
 }
 
 static void led_set_power(void)
 {
+	/* turn off led when lid is close*/
+	if (!lid_is_open()) {
+		set_pwr_led_color(PWM_LED1, -1);
+		return;
+	}
+
 	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
 		breath_led_run(1);
 		return;
-	}
-	else
+	} else
 		breath_led_run(0);
 
 	if (chipset_in_state(CHIPSET_STATE_ON)) {
@@ -369,6 +360,5 @@ static void led_tick(void)
 		led_set_battery();
 	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
 		led_set_power();
-
 }
 DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
diff --git a/board/banshee/pwm.c b/board/banshee/pwm.c
index e02d19064d..bfe5071eca 100644
--- a/board/banshee/pwm.c
+++ b/board/banshee/pwm.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/banshee/sensors.c b/board/banshee/sensors.c
index b4b6360984..57b81b2af8 100644
--- a/board/banshee/sensors.c
+++ b/board/banshee/sensors.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -40,15 +40,14 @@ struct adc_t adc_channels[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
-
 /* CM32183 private data */
 static struct als_drv_data_t g_cm32183_data = {
 	/**
 	 * adjusted_value = raw_value * scale + raw_value * uscale / 10000
-	 * the coeficient we need is 3.8
+	 * the coeficient we need is 3.2
 	 */
 	.als_cal.scale = 3,
-	.als_cal.uscale = 8000,
+	.als_cal.uscale = 2000,
 	.als_cal.offset = 0,
 	.als_cal.channel_scale = {
 		/* TODO(b/219424210):  Calibrate ALS CM32183A3OP */
@@ -120,8 +119,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CPU \
-	{ \
+#define THERMAL_CPU              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = C_TO_K(80), \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(90), \
@@ -131,7 +130,7 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 			[EC_TEMP_THRESH_WARN] = C_TO_K(75), \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(81), \
 		}, \
-		.temp_fan_off = C_TO_K(40), \
+		.temp_fan_off = C_TO_K(50), \
 		.temp_fan_max = C_TO_K(58), \
 	}
 __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
@@ -152,8 +151,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_AMBIENT \
-	{ \
+#define THERMAL_AMBIENT          \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = C_TO_K(85), \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(95), \
@@ -163,7 +162,7 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 			[EC_TEMP_THRESH_WARN] = C_TO_K(70), \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(86), \
 		}, \
-		.temp_fan_off = C_TO_K(40), \
+		.temp_fan_off = C_TO_K(50), \
 		.temp_fan_max = C_TO_K(58), \
 	}
 __maybe_unused static const struct ec_thermal_config thermal_ambient =
@@ -183,8 +182,8 @@ __maybe_unused static const struct ec_thermal_config thermal_ambient =
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CHARGER \
-	{ \
+#define THERMAL_CHARGER          \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = C_TO_K(90), \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(100), \
@@ -194,7 +193,7 @@ __maybe_unused static const struct ec_thermal_config thermal_ambient =
 			[EC_TEMP_THRESH_WARN] = C_TO_K(85), \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(91), \
 		}, \
-		.temp_fan_off = C_TO_K(40), \
+		.temp_fan_off = C_TO_K(50), \
 		.temp_fan_max = C_TO_K(58), \
 	}
 __maybe_unused static const struct ec_thermal_config thermal_charger =
@@ -206,8 +205,8 @@ __maybe_unused static const struct ec_thermal_config thermal_charger =
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_WWAN \
-	{ \
+#define THERMAL_WWAN             \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(130), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(130), \
diff --git a/board/banshee/tune_mp2964.c b/board/banshee/tune_mp2964.c
deleted file mode 100644
index f67caa587e..0000000000
--- a/board/banshee/tune_mp2964.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Tune the MP2964 IMVP9.1 parameters for brya */
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "hooks.h"
-#include "mp2964.h"
-
-const static struct mp2964_reg_val rail_a[] = {
-	{ MP2964_MFR_ALT_SET,     0xe081 },	/* ALERT_DELAY = 200ns */
-};
-const static struct mp2964_reg_val rail_b[] = {
-	{ MP2964_MFR_ALT_SET,     0xe081 },	/* ALERT_DELAY = 200ns */
-};
-
-static void mp2964_on_startup(void)
-{
-	static int chip_updated;
-	int status;
-
-	if (get_board_id() != 1)
-		return;
-
-	if (chip_updated)
-		return;
-
-	chip_updated = 1;
-
-	ccprintf("%s: attempting to tune PMIC\n", __func__);
-
-	status = mp2964_tune(rail_a, ARRAY_SIZE(rail_a),
-			     rail_b, ARRAY_SIZE(rail_b));
-	if (status != EC_SUCCESS)
-		ccprintf("%s: could not update all settings\n", __func__);
-}
-
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, mp2964_on_startup,
-	     HOOK_PRIO_FIRST);
diff --git a/board/banshee/usbc_config.c b/board/banshee/usbc_config.c
index 93292873bc..7840b865ab 100644
--- a/board/banshee/usbc_config.c
+++ b/board/banshee/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -36,8 +36,8 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 /* USBC TCPC configuration */
 const struct tcpc_config_t tcpc_config[] = {
@@ -113,59 +113,79 @@ BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
 /* USBC mux configuration - Alder Lake includes internal mux */
-static const struct usb_mux usbc0_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+static const struct usb_mux_chain usbc0_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
-static const struct usb_mux usbc1_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+static const struct usb_mux_chain usbc1_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
-static const struct usb_mux usbc2_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C2,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+static const struct usb_mux_chain usbc2_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C2,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
-static const struct usb_mux usbc3_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C3,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+static const struct usb_mux_chain usbc3_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C3,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
 
-const struct usb_mux usb_muxes[] = {
+const struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C0_C1_MUX,
-		.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc0_tcss_usb_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C0_C1_MUX,
+			.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc0_tcss_usb_mux,
 	},
 	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C0_C1_MUX,
-		.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc1_tcss_usb_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C0_C1_MUX,
+			.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc1_tcss_usb_mux,
 	},
 	[USBC_PORT_C2] = {
-		.usb_port = USBC_PORT_C2,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C2_C3_MUX,
-		.i2c_addr_flags = USBC_PORT_C2_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc2_tcss_usb_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C2,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C2_C3_MUX,
+			.i2c_addr_flags = USBC_PORT_C2_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc2_tcss_usb_mux,
 	},
 	[USBC_PORT_C3] = {
-		.usb_port = USBC_PORT_C3,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C2_C3_MUX,
-		.i2c_addr_flags = USBC_PORT_C3_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc3_tcss_usb_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C3,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C2_C3_MUX,
+			.i2c_addr_flags = USBC_PORT_C3_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc3_tcss_usb_mux,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
@@ -252,8 +272,8 @@ int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
 	}
 
 	if (voltage < BC12_MIN_VOLTAGE) {
-		CPRINTS("%s: port %d: vbus %d lower than %d", __func__,
-			port, voltage, BC12_MIN_VOLTAGE);
+		CPRINTS("%s: port %d: vbus %d lower than %d", __func__, port,
+			voltage, BC12_MIN_VOLTAGE);
 		return 1;
 	}
 
@@ -294,7 +314,7 @@ __override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
 		 * which powers I2C controller within retimer
 		 */
 		msleep(1);
-	} else{
+	} else {
 		ioex_set_level(rst_signal, 0);
 		msleep(1);
 	}
diff --git a/board/banshee/usbc_config.h b/board/banshee/usbc_config.h
index 9a7cf4caca..5085b28bec 100644
--- a/board/banshee/usbc_config.h
+++ b/board/banshee/usbc_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,7 +8,7 @@
 #ifndef __CROS_EC_USBC_CONFIG_H
 #define __CROS_EC_USBC_CONFIG_H
 
-#define CONFIG_USB_PD_PORT_MAX_COUNT	4
+#define CONFIG_USB_PD_PORT_MAX_COUNT 4
 
 enum usbc_port {
 	USBC_PORT_C0 = 0,
diff --git a/board/beadrix/battery.c b/board/beadrix/battery.c
index 8ebdaf466d..48defc0481 100644
--- a/board/beadrix/battery.c
+++ b/board/beadrix/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/beadrix/board.c b/board/beadrix/board.c
index 0fb2f9773b..5cea32f90c 100644
--- a/board/beadrix/board.c
+++ b/board/beadrix/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -39,8 +39,8 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
 
 #define INT_RECHECK_US 5000
 
@@ -142,34 +142,26 @@ __override void board_pulse_entering_rw(void)
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH0
-	},
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH2
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH3
-	},
-	[ADC_SUB_ANALOG] = {
-		.name = "SUB_ANALOG",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH13
-	},
+	[ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH0 },
+	[ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH2 },
+	[ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH3 },
+	[ADC_SUB_ANALOG] = { .name = "SUB_ANALOG",
+			     .factor_mul = ADC_MAX_MVOLT,
+			     .factor_div = ADC_READ_MAX + 1,
+			     .shift = 0,
+			     .channel = CHIP_ADC_CH13 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
@@ -224,38 +216,48 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 };
 
 static int board_nb7v904m_mux_set(const struct usb_mux *me,
-						mux_state_t mux_state);
+				  mux_state_t mux_state);
 
 /* USB Retimer */
-const struct usb_mux usbc1_retimer = {
-	.usb_port = 1,
-	.i2c_port = I2C_PORT_SUB_USB_C1,
-	.i2c_addr_flags = NB7V904M_I2C_ADDR0,
-	.driver = &nb7v904m_usb_redriver_drv,
-	.board_set = &board_nb7v904m_mux_set,
+const struct usb_mux_chain usbc1_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = 1,
+			.i2c_port = I2C_PORT_SUB_USB_C1,
+			.i2c_addr_flags = NB7V904M_I2C_ADDR0,
+			.driver = &nb7v904m_usb_redriver_drv,
+			.board_set = &board_nb7v904m_mux_set,
+		},
 };
 
 /* USB Muxes */
-struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+			},
 	},
-	{	/* Used as MUX only*/
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = AN7447_TCPC0_I2C_ADDR_FLAGS,
-		.flags = USB_MUX_FLAG_NOT_TCPC,
-		.driver = &anx7447_usb_mux_driver,
-		.next_mux = &usbc1_retimer,
+	{
+		/* Used as MUX only*/
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_SUB_USB_C1,
+				.i2c_addr_flags = AN7447_TCPC0_I2C_ADDR_FLAGS,
+				.flags = USB_MUX_FLAG_NOT_TCPC,
+				.driver = &anx7447_usb_mux_driver,
+			},
+		.next = &usbc1_retimer,
 	},
 };
 
 /* USB Mux */
 static int board_nb7v904m_mux_set(const struct usb_mux *me,
-						mux_state_t mux_state)
+				  mux_state_t mux_state)
 {
 	int rv = EC_SUCCESS;
 	int flipped = !!(mux_state & USB_PD_MUX_POLARITY_INVERTED);
@@ -264,75 +266,71 @@ static int board_nb7v904m_mux_set(const struct usb_mux *me,
 		/* USB with DP */
 		if (mux_state & USB_PD_MUX_DP_ENABLED) {
 			if (flipped) { /* CC2 */
-				rv |= nb7v904m_tune_usb_set_eq(me,
-						NB7V904M_CH_A_EQ_0_DB,
-						NB7V904M_CH_B_EQ_4_DB,
-						NB7V904M_CH_C_EQ_0_DB,
-						NB7V904M_CH_D_EQ_0_DB);
-				rv |= nb7v904m_tune_usb_flat_gain(me,
-						NB7V904M_CH_A_GAIN_0_DB,
-						NB7V904M_CH_B_GAIN_3P5_DB,
-						NB7V904M_CH_C_GAIN_0_DB,
-						NB7V904M_CH_D_GAIN_0_DB);
-				rv |= nb7v904m_set_loss_profile_match(me,
-						NB7V904M_LOSS_PROFILE_A,
-						NB7V904M_LOSS_PROFILE_A,
-						NB7V904M_LOSS_PROFILE_D,
-						NB7V904M_LOSS_PROFILE_D);
+				rv |= nb7v904m_tune_usb_set_eq(
+					me, NB7V904M_CH_A_EQ_0_DB,
+					NB7V904M_CH_B_EQ_4_DB,
+					NB7V904M_CH_C_EQ_0_DB,
+					NB7V904M_CH_D_EQ_0_DB);
+				rv |= nb7v904m_tune_usb_flat_gain(
+					me, NB7V904M_CH_A_GAIN_0_DB,
+					NB7V904M_CH_B_GAIN_3P5_DB,
+					NB7V904M_CH_C_GAIN_0_DB,
+					NB7V904M_CH_D_GAIN_0_DB);
+				rv |= nb7v904m_set_loss_profile_match(
+					me, NB7V904M_LOSS_PROFILE_A,
+					NB7V904M_LOSS_PROFILE_A,
+					NB7V904M_LOSS_PROFILE_D,
+					NB7V904M_LOSS_PROFILE_D);
 			} /* CC1 */
 			else {
-				rv |= nb7v904m_tune_usb_set_eq(me,
-						NB7V904M_CH_A_EQ_0_DB,
-						NB7V904M_CH_B_EQ_0_DB,
-						NB7V904M_CH_C_EQ_4_DB,
-						NB7V904M_CH_D_EQ_0_DB);
-				rv |= nb7v904m_tune_usb_flat_gain(me,
-						NB7V904M_CH_A_GAIN_0_DB,
-						NB7V904M_CH_B_GAIN_0_DB,
-						NB7V904M_CH_C_GAIN_3P5_DB,
-						NB7V904M_CH_D_GAIN_0_DB);
-				rv |= nb7v904m_set_loss_profile_match(me,
-						NB7V904M_LOSS_PROFILE_D,
-						NB7V904M_LOSS_PROFILE_D,
-						NB7V904M_LOSS_PROFILE_A,
-						NB7V904M_LOSS_PROFILE_A);
-			}
-		} else {
-			/* USB only */
-			rv |= nb7v904m_tune_usb_set_eq(me,
-					NB7V904M_CH_A_EQ_0_DB,
-					NB7V904M_CH_B_EQ_4_DB,
+				rv |= nb7v904m_tune_usb_set_eq(
+					me, NB7V904M_CH_A_EQ_0_DB,
+					NB7V904M_CH_B_EQ_0_DB,
 					NB7V904M_CH_C_EQ_4_DB,
 					NB7V904M_CH_D_EQ_0_DB);
-			rv |= nb7v904m_tune_usb_flat_gain(me,
-					NB7V904M_CH_A_GAIN_0_DB,
-					NB7V904M_CH_B_GAIN_3P5_DB,
+				rv |= nb7v904m_tune_usb_flat_gain(
+					me, NB7V904M_CH_A_GAIN_0_DB,
+					NB7V904M_CH_B_GAIN_0_DB,
 					NB7V904M_CH_C_GAIN_3P5_DB,
 					NB7V904M_CH_D_GAIN_0_DB);
-			rv |= nb7v904m_set_loss_profile_match(me,
-					NB7V904M_LOSS_PROFILE_A,
-					NB7V904M_LOSS_PROFILE_A,
+				rv |= nb7v904m_set_loss_profile_match(
+					me, NB7V904M_LOSS_PROFILE_D,
+					NB7V904M_LOSS_PROFILE_D,
 					NB7V904M_LOSS_PROFILE_A,
 					NB7V904M_LOSS_PROFILE_A);
+			}
+		} else {
+			/* USB only */
+			rv |= nb7v904m_tune_usb_set_eq(me,
+						       NB7V904M_CH_A_EQ_0_DB,
+						       NB7V904M_CH_B_EQ_4_DB,
+						       NB7V904M_CH_C_EQ_4_DB,
+						       NB7V904M_CH_D_EQ_0_DB);
+			rv |= nb7v904m_tune_usb_flat_gain(
+				me, NB7V904M_CH_A_GAIN_0_DB,
+				NB7V904M_CH_B_GAIN_3P5_DB,
+				NB7V904M_CH_C_GAIN_3P5_DB,
+				NB7V904M_CH_D_GAIN_0_DB);
+			rv |= nb7v904m_set_loss_profile_match(
+				me, NB7V904M_LOSS_PROFILE_A,
+				NB7V904M_LOSS_PROFILE_A,
+				NB7V904M_LOSS_PROFILE_A,
+				NB7V904M_LOSS_PROFILE_A);
 		}
 
 	} else if (mux_state & USB_PD_MUX_DP_ENABLED) {
 		/* 4 lanes DP */
-		rv |= nb7v904m_tune_usb_set_eq(me,
-				NB7V904M_CH_A_EQ_0_DB,
-				NB7V904M_CH_B_EQ_0_DB,
-				NB7V904M_CH_C_EQ_0_DB,
-				NB7V904M_CH_D_EQ_0_DB);
-		rv |= nb7v904m_tune_usb_flat_gain(me,
-				NB7V904M_CH_A_GAIN_0_DB,
-				NB7V904M_CH_B_GAIN_0_DB,
-				NB7V904M_CH_C_GAIN_0_DB,
-				NB7V904M_CH_D_GAIN_0_DB);
-		rv |= nb7v904m_set_loss_profile_match(me,
-				NB7V904M_LOSS_PROFILE_D,
-				NB7V904M_LOSS_PROFILE_D,
-				NB7V904M_LOSS_PROFILE_D,
-				NB7V904M_LOSS_PROFILE_D);
+		rv |= nb7v904m_tune_usb_set_eq(me, NB7V904M_CH_A_EQ_0_DB,
+					       NB7V904M_CH_B_EQ_0_DB,
+					       NB7V904M_CH_C_EQ_0_DB,
+					       NB7V904M_CH_D_EQ_0_DB);
+		rv |= nb7v904m_tune_usb_flat_gain(me, NB7V904M_CH_A_GAIN_0_DB,
+						  NB7V904M_CH_B_GAIN_0_DB,
+						  NB7V904M_CH_C_GAIN_0_DB,
+						  NB7V904M_CH_D_GAIN_0_DB);
+		rv |= nb7v904m_set_loss_profile_match(
+			me, NB7V904M_LOSS_PROFILE_D, NB7V904M_LOSS_PROFILE_D,
+			NB7V904M_LOSS_PROFILE_D, NB7V904M_LOSS_PROFILE_D);
 	}
 
 	return rv;
@@ -406,8 +404,7 @@ int board_is_sourcing_vbus(int port)
 
 int board_set_active_charge_port(int port)
 {
-	int is_real_port = (port >= 0 &&
-			    port < board_get_usb_pd_port_count());
+	int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count());
 	int i;
 	int old_port;
 
@@ -443,22 +440,24 @@ int board_set_active_charge_port(int port)
 	 * Turn off the other ports' sink path FETs, before enabling the
 	 * requested charge port.
 	 */
-	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
-		if (i == port)
-			continue;
-
-		if (tcpc_write(i, TCPC_REG_COMMAND,
-			       TCPC_REG_COMMAND_SNK_CTRL_LOW))
-			CPRINTS("p%d: sink path disable failed.", i);
-		raa489000_enable_asgate(i, false);
-	}
+	if (old_port != CHARGE_PORT_NONE && old_port != port) {
+		for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+			if (i == port)
+				continue;
 
-	/*
-	 * Stop the charger IC from switching while changing ports.  Otherwise,
-	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
-	 */
-	if (old_port != CHARGE_PORT_NONE)
+			if (tcpc_write(i, TCPC_REG_COMMAND,
+				       TCPC_REG_COMMAND_SNK_CTRL_LOW))
+				CPRINTS("p%d: sink path disable failed.", i);
+			raa489000_enable_asgate(i, false);
+		}
+
+		/*
+		 * Stop the charger IC from switching while changing ports.
+		 * Otherwise, we can overcurrent the adapter we're switching to.
+		 * (crbug.com/926056)
+		 */
 		charger_discharge_on_ac(1);
+	}
 
 	/* Enable requested charge port. */
 	if (raa489000_enable_asgate(port, true) ||
@@ -476,8 +475,8 @@ int board_set_active_charge_port(int port)
 }
 
 /* Vconn control for integrated ITE TCPC */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-				int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
 
@@ -518,7 +517,7 @@ uint16_t tcpc_get_alert_status(void)
 	}
 
 	if (board_get_usb_pd_port_count() > 1 &&
-				!gpio_get_level(GPIO_USB_C1_INT_V1_ODL)) {
+	    !gpio_get_level(GPIO_USB_C1_INT_V1_ODL)) {
 		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
 			/* TCPCI spec Rev 1.0 says to ignore bits 14:12. */
 			if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0))
@@ -532,9 +531,8 @@ uint16_t tcpc_get_alert_status(void)
 	return status;
 }
 
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
+__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+				       int *ki_div, int *kd, int *kd_div)
 {
 	*kp = 1;
 	*kp_div = 20;
@@ -550,25 +548,23 @@ int pd_snk_is_vbus_provided(int port)
 }
 
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq_hz = 10000,
-	}
-};
+const struct pwm_t pwm_channels[] = { [PWM_CH_KBLIGHT] = {
+					      .channel = 0,
+					      .flags = PWM_CONFIG_DSLEEP,
+					      .freq_hz = 10000,
+				      } };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
 /* Thermistors */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -589,8 +585,8 @@ static const struct ec_response_keybd_config keybd1 = {
 	/* No function keys, no numeric keypad and no screenlock key */
 };
 
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	/*
 	 * Future boards should use fw_config if needed.
diff --git a/board/beadrix/board.h b/board/beadrix/board.h
index 6e7975fd14..82a7802445 100644
--- a/board/beadrix/board.h
+++ b/board/beadrix/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,8 +12,7 @@
 #define VARIANT_DEDEDE_EC_IT8320
 #include "baseboard.h"
 
-/* System unlocked in early development */
-#define CONFIG_SYSTEM_UNLOCKED
+#undef CONFIG_I2C_DEBUG
 
 /* EC console commands */
 #define CONFIG_CMD_CHARGER_DUMP
@@ -27,12 +26,15 @@
 
 /* Charger */
 #define CONFIG_CHARGER_RAA489000
+#define PD_MAX_VOLTAGE_MV 20000
 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 #define CONFIG_CHARGER_SENSE_RESISTOR 10
 #define CONFIG_CHARGE_RAMP_HW
-#undef  CONFIG_CHARGER_SINGLE_CHIP
+#undef CONFIG_CHARGER_SINGLE_CHIP
 #define CONFIG_OCPC
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */
+#define CONFIG_OCPC_DEF_RBATT_MOHMS               \
+	22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \
+	    */
 
 /*
  * GPIO for C1 interrupts, for baseboard use
@@ -45,7 +47,7 @@
 #define CONFIG_PWM
 
 /* TCPC */
-#define CONFIG_USB_PD_TCPM_ANX7447	/* C1: MUX  only*/
+#define CONFIG_USB_PD_TCPM_ANX7447 /* C1: MUX  only*/
 #define CONFIG_USB_PD_TCPM_MUX
 #define CONFIG_USB_PD_TCPM_ANX7447_AUX_PU_PD
 
@@ -57,7 +59,7 @@
 /* USB */
 #define CONFIG_BC12_DETECT_PI3USB9201
 #define CONFIG_USB_MUX_RUNTIME_CONFIG
-#define CONFIG_USB_MUX_IT5205	/* C0: ITE MUX */
+#define CONFIG_USB_MUX_IT5205 /* C0: ITE MUX */
 
 /* USB PD */
 #define CONFIG_USB_PD_PORT_MAX_COUNT 2
@@ -67,7 +69,7 @@
 
 /* USB Mux and Retimer */
 #define CONFIG_USB_MUX_RUNTIME_CONFIG
-#define CONFIG_USB_MUX_IT5205			/* C1: ITE Mux */
+#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */
 #define CONFIG_USBC_RETIMER_NB7V904M
 
 /* USB defines specific to external TCPCs */
@@ -82,8 +84,8 @@
 #undef PD_POWER_SUPPLY_TURN_ON_DELAY
 #undef PD_POWER_SUPPLY_TURN_OFF_DELAY
 /* 20% margin added for these timings */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	13080	/* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	16080	/* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 13080 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 16080 /* us */
 
 #ifndef __ASSEMBLER__
 
@@ -103,18 +105,14 @@ enum pwm_channel {
 
 /* ADC channels */
 enum adc_channel {
-	ADC_VSNS_PP3300_A,     /* ADC0 */
-	ADC_TEMP_SENSOR_1,     /* ADC2 */
-	ADC_TEMP_SENSOR_2,     /* ADC3 */
-	ADC_SUB_ANALOG,        /* ADC13 */
+	ADC_VSNS_PP3300_A, /* ADC0 */
+	ADC_TEMP_SENSOR_1, /* ADC2 */
+	ADC_TEMP_SENSOR_2, /* ADC3 */
+	ADC_SUB_ANALOG, /* ADC13 */
 	ADC_CH_COUNT
 };
 
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_COUNT
-};
+enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
diff --git a/board/beadrix/build.mk b/board/beadrix/build.mk
index 8167ca9966..01b890bf29 100644
--- a/board/beadrix/build.mk
+++ b/board/beadrix/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/beadrix/cbi_ssfc.c b/board/beadrix/cbi_ssfc.c
index c4b859f133..81f3ee0dad 100644
--- a/board/beadrix/cbi_ssfc.c
+++ b/board/beadrix/cbi_ssfc.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
 
 enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
 {
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
 }
 
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
 {
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
 }
diff --git a/board/beadrix/cbi_ssfc.h b/board/beadrix/cbi_ssfc.h
index 935049b6ae..bf8853a43a 100644
--- a/board/beadrix/cbi_ssfc.h
+++ b/board/beadrix/cbi_ssfc.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -56,5 +56,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
  */
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
 
-
 #endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/beadrix/ec.tasklist b/board/beadrix/ec.tasklist
index 74b7663d69..253501100e 100644
--- a/board/beadrix/ec.tasklist
+++ b/board/beadrix/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/beadrix/gpio.inc b/board/beadrix/gpio.inc
index b5e557f01f..b450c520e8 100644
--- a/board/beadrix/gpio.inc
+++ b/board/beadrix/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/beadrix/led.c b/board/beadrix/led.c
index ab011d49d4..8bef7c0bd9 100644
--- a/board/beadrix/led.c
+++ b/board/beadrix/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,27 +19,25 @@
 #include "util.h"
 
 #define LED_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS)
-#define BAT_LED_ON	0
-#define BAT_LED_OFF	1
+#define BAT_LED_ON 0
+#define BAT_LED_OFF 1
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 enum led_color {
 	LED_OFF = 0,
 	LED_RED,
 	LED_BLUE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static void led_set_color(enum led_color color)
 {
 	gpio_set_level(GPIO_EC_LED_R_ODL,
-		(color == LED_RED) ? BAT_LED_ON : BAT_LED_OFF);
+		       (color == LED_RED) ? BAT_LED_ON : BAT_LED_OFF);
 	gpio_set_level(GPIO_EC_LED_B_ODL,
-		(color == LED_BLUE) ? BAT_LED_ON : BAT_LED_OFF);
+		       (color == LED_BLUE) ? BAT_LED_ON : BAT_LED_OFF);
 }
 
 void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
@@ -65,7 +63,6 @@ static void board_led_set_battery(void)
 	static int battery_ticks;
 	enum led_color color = LED_OFF;
 	int period = 0;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
@@ -105,16 +102,16 @@ static void board_led_set_battery(void)
 		color = LED_BLUE;
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE) {
-			/* Factory mode: Blue 2 sec, Red 2 sec */
-			period = (2 + 2) * LED_ONE_SEC;
-			battery_ticks = battery_ticks % period;
-			if (battery_ticks < 2 * LED_ONE_SEC)
-				color = LED_BLUE;
-			else
-				color = LED_RED;
-		} else
+		color = LED_BLUE;
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		/* Factory mode: Blue 2 sec, Red 2 sec */
+		period = (2 + 2) * LED_ONE_SEC;
+		battery_ticks = battery_ticks % period;
+		if (battery_ticks < 2 * LED_ONE_SEC)
 			color = LED_BLUE;
+		else
+			color = LED_RED;
 		break;
 	default:
 		/* Other states don't alter LED behavior */
diff --git a/board/beadrix/usb_pd_policy.c b/board/beadrix/usb_pd_policy.c
index a50ef8cfa9..c22c68d224 100644
--- a/board/beadrix/usb_pd_policy.c
+++ b/board/beadrix/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,8 +13,8 @@
 #include "driver/tcpm/tcpci.h"
 #include "usb_pd.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
diff --git a/board/beetley/battery.c b/board/beetley/battery.c
index 94f5dbb630..0402ef33fd 100644
--- a/board/beetley/battery.c
+++ b/board/beetley/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/beetley/board.c b/board/beetley/board.c
index 0e6c88b24b..f6b1f1008c 100644
--- a/board/beetley/board.c
+++ b/board/beetley/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -43,7 +43,7 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
 #define INT_RECHECK_US 5000
 
 __override struct keyboard_scan_config keyscan_config = {
@@ -100,7 +100,6 @@ static void usb_c0_interrupt(enum gpio_signal s)
 
 	/* Check the line again in 5ms */
 	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-
 }
 
 static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
@@ -114,34 +113,26 @@ static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH0
-	},
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH2
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH3
-	},
-	[ADC_TEMP_SENSOR_3] = {
-		.name = "TEMP_SENSOR3",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH15
-	},
+	[ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH0 },
+	[ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH2 },
+	[ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH3 },
+	[ADC_TEMP_SENSOR_3] = { .name = "TEMP_SENSOR3",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH15 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
@@ -177,12 +168,15 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 };
 
 /* USB Muxes */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+			},
 	},
 };
 
@@ -203,27 +197,23 @@ static const struct ec_response_keybd_config beetley_keybd = {
 	.capabilities = KEYBD_CAP_SCRNLOCK_KEY | KEYBD_CAP_NUMERIC_KEYPAD,
 };
 
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	return &beetley_keybd;
 }
 
 /* USB-A charging control */
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_USB_A0_VBUS
-};
+const int usb_port_enable[USB_PORT_COUNT] = { GPIO_EN_USB_A0_VBUS };
 
 /* Sensors */
 static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrices to rotate accelerometers into the standard reference. */
-static const mat33_fp_t base_lsm6dsm_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t base_lsm6dsm_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					     { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
 
 static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
 
@@ -331,7 +321,6 @@ void board_init(void)
 	keyscan_config.actual_key_mask[12] = 0xff;
 	keyscan_config.actual_key_mask[13] = 0xff;
 	keyscan_config.actual_key_mask[14] = 0xff;
-
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
@@ -422,7 +411,6 @@ int board_is_sourcing_vbus(int port)
 
 	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
 	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
-
 }
 
 int board_set_active_charge_port(int port)
@@ -434,8 +422,7 @@ int board_set_active_charge_port(int port)
 
 	/* Disable all ports. */
 	if (port == CHARGE_PORT_NONE) {
-		tcpc_write(0, TCPC_REG_COMMAND,
-				TCPC_REG_COMMAND_SNK_CTRL_LOW);
+		tcpc_write(0, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
 		raa489000_enable_asgate(0, false);
 		return EC_SUCCESS;
 	}
@@ -448,8 +435,7 @@ int board_set_active_charge_port(int port)
 
 	/* Enable requested charge port. */
 	if (raa489000_enable_asgate(port, true) ||
-	    tcpc_write(0, TCPC_REG_COMMAND,
-		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
+	    tcpc_write(0, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
 		CPRINTUSB("p%d: sink path enable failed.", port);
 		return EC_ERROR_UNKNOWN;
 	}
@@ -481,18 +467,18 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
 /* Thermistors */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Charge",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "5V_Inductor",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_3},
+	[TEMP_SENSOR_1] = { .name = "Charge",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "5V_Inductor",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
diff --git a/board/beetley/board.h b/board/beetley/board.h
index 15eac0d3f8..a70ee73ebb 100644
--- a/board/beetley/board.h
+++ b/board/beetley/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,6 +27,7 @@
 /* Charger */
 #define CONFIG_CHARGE_RAMP_HW
 #define CONFIG_CHARGER_RAA489000
+#define PD_MAX_VOLTAGE_MV 20000
 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 #define CONFIG_CHARGER_SENSE_RESISTOR 10
 #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
@@ -42,13 +43,13 @@
 #define CONFIG_CMD_ACCELS
 #define CONFIG_CMD_ACCEL_INFO
 
-#define CONFIG_ACCEL_LIS2DWL		/* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM    /* Base accel */
+#define CONFIG_ACCEL_LIS2DWL /* Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
 
 /* Lid operates in forced mode, base in FIFO */
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
 #define CONFIG_ACCEL_FIFO
-#define CONFIG_ACCEL_FIFO_SIZE 256	/* Must be a power of 2 */
+#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */
 #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
 
 #define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
@@ -112,12 +113,7 @@ enum pwm_channel {
 };
 
 /* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
 /* ADC channels */
 enum adc_channel {
diff --git a/board/beetley/build.mk b/board/beetley/build.mk
index 8167ca9966..01b890bf29 100644
--- a/board/beetley/build.mk
+++ b/board/beetley/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/beetley/cbi_ssfc.c b/board/beetley/cbi_ssfc.c
index c4b859f133..81f3ee0dad 100644
--- a/board/beetley/cbi_ssfc.c
+++ b/board/beetley/cbi_ssfc.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
 
 enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
 {
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
 }
 
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
 {
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
 }
diff --git a/board/beetley/cbi_ssfc.h b/board/beetley/cbi_ssfc.h
index 935049b6ae..bf8853a43a 100644
--- a/board/beetley/cbi_ssfc.h
+++ b/board/beetley/cbi_ssfc.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -56,5 +56,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
  */
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
 
-
 #endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/beetley/ec.tasklist b/board/beetley/ec.tasklist
index bdcbcdf074..8ccdfc81b2 100644
--- a/board/beetley/ec.tasklist
+++ b/board/beetley/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/beetley/gpio.inc b/board/beetley/gpio.inc
index bbb793ee44..0677e5a2ac 100644
--- a/board/beetley/gpio.inc
+++ b/board/beetley/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/beetley/led.c b/board/beetley/led.c
index bf64b33dcf..e3d4eb543e 100644
--- a/board/beetley/led.c
+++ b/board/beetley/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,42 +11,46 @@
 #include "gpio.h"
 #include "pwm.h"
 
-#define LED_OFF_LVL	0
-#define LED_ON_LVL	1
+#define LED_OFF_LVL 0
+#define LED_ON_LVL 1
 
 __override const int led_charge_lvl_1 = 5;
 
 __override const int led_charge_lvl_2 = 97;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED,   LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,   1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
 
 __override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    1 * LED_ONE_SEC },
+						  { LED_OFF,
+						    3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 __override void led_set_color_battery(enum ec_led_colors color)
diff --git a/board/beetley/usb_pd_policy.c b/board/beetley/usb_pd_policy.c
index b7c0ca21df..a7633b73ac 100644
--- a/board/beetley/usb_pd_policy.c
+++ b/board/beetley/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,8 +13,8 @@
 #include "driver/tcpm/tcpci.h"
 #include "usb_pd.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
diff --git a/board/bellis/battery.c b/board/bellis/battery.c
index 7c086fb8e2..d74876ec27 100644
--- a/board/bellis/battery.c
+++ b/board/bellis/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/bellis/board.c b/board/bellis/board.c
index 7c7392e4d5..e03ae1c36c 100644
--- a/board/bellis/board.c
+++ b/board/bellis/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -31,6 +31,7 @@
 #include "keyboard_scan.h"
 #include "keyboard_backlight.h"
 #include "lid_switch.h"
+#include "panic.h"
 #include "power.h"
 #include "power_button.h"
 #include "registers.h"
@@ -44,8 +45,8 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
@@ -57,42 +58,36 @@ static void tcpc_alert_event(enum gpio_signal signal)
 /******************************************************************************/
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] = {"BOARD_ID", 3300, 4096, 0, STM32_AIN(5),
-			   STM32_RANK(1)},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(15),
-			    STM32_RANK(2)},
+	[ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(5),
+			   STM32_RANK(1) },
+	[ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(15),
+			    STM32_RANK(2) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /******************************************************************************/
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "typec",
-		.port = 0,
-		.kbps = 400,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	},
-	{
-		.name = "other",
-		.port = 2,
-		.kbps = 400,
-		.scl  = GPIO_I2C3_SCL,
-		.sda  = GPIO_I2C3_SDA
-	},
+	{ .name = "typec",
+	  .port = 0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "other",
+	  .port = 2,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
 const struct i2c_port_t i2c_bitbang_ports[] = {
-	{
-		.name = "battery",
-		.port = 3,
-		.kbps = 100,
-		.scl = GPIO_I2C4_SCL,
-		.sda = GPIO_I2C4_SDA,
-		.drv = &bitbang_drv
-	},
+	{ .name = "battery",
+	  .port = 3,
+	  .kbps = 100,
+	  .scl = GPIO_I2C4_SCL,
+	  .sda = GPIO_I2C4_SDA,
+	  .drv = &bitbang_drv },
 };
 const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
 
@@ -100,8 +95,8 @@ const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
 
 /* power signal list.  Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
+	{ GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" },
+	{ GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" },
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
@@ -157,8 +152,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-static void board_hpd_status(const struct usb_mux *me,
-			     mux_state_t mux_state,
+static void board_hpd_status(const struct usb_mux *me, mux_state_t mux_state,
 			     bool *ack_required)
 {
 	/* This driver does not use host command ACKs */
@@ -171,13 +165,16 @@ static void board_hpd_status(const struct usb_mux *me,
 	host_set_single_event(EC_HOST_EVENT_USB_MUX);
 }
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+				.hpd_update = &board_hpd_status,
+			},
 	},
 };
 
@@ -239,12 +236,12 @@ int board_set_active_charge_port(int charge_port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-			       CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 int board_discharge_on_ac(int enable)
@@ -314,8 +311,7 @@ static void board_spi_enable(void)
 	/* Pin mux spi peripheral toward the sensor. */
 	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
 }
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP,
-	     board_spi_enable,
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_spi_enable,
 	     MOTION_SENSE_HOOK_PRIO - 1);
 
 static void board_spi_disable(void)
@@ -333,8 +329,7 @@ static void board_spi_disable(void)
 	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
 #endif
 }
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN,
-	     board_spi_disable,
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_spi_disable,
 	     MOTION_SENSE_HOOK_PRIO + 1);
 #endif /* !VARIANT_KUKUI_NO_SENSORS */
 
@@ -373,17 +368,13 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Rotation matrixes */
-static const mat33_fp_t base_standard_ref = {
-	{0, FLOAT_TO_FP(1), 0},
-	{FLOAT_TO_FP(-1), 0, 0},
-	{0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					      { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
 
-static const mat33_fp_t lid_standard_ref = {
-	{FLOAT_TO_FP(-1), 0, 0},
-	{0, FLOAT_TO_FP(1), 0},
-	{0, 0, FLOAT_TO_FP(-1) }
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, FLOAT_TO_FP(1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
 /* sensor private data */
 /* Lid accel private data */
@@ -471,7 +462,7 @@ struct motion_sensor_t motion_sensors[] = {
 const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
 const struct it8801_pwm_t it8801_pwm_channels[] = {
-	[IT8801_PWM_CH_KBLIGHT] = {.index = 4},
+	[IT8801_PWM_CH_KBLIGHT] = { .index = 4 },
 };
 
 void board_kblight_init(void)
@@ -487,11 +478,11 @@ bool board_has_kb_backlight(void)
 #endif /* !VARIANT_KUKUI_NO_SENSORS */
 
 /* Battery functions */
-#define SB_SMARTCHARGE				0x26
+#define SB_SMARTCHARGE 0x26
 /* Quick charge enable bit */
-#define SMART_QUICK_CHARGE			0x02
+#define SMART_QUICK_CHARGE 0x02
 /* Quick charge support bit */
-#define MODE_QUICK_CHARGE_SUPPORT		0x01
+#define MODE_QUICK_CHARGE_SUPPORT 0x01
 
 static void sb_quick_charge_mode(int enable)
 {
@@ -562,8 +553,8 @@ int board_get_battery_i2c(void)
 }
 
 #ifdef SECTION_IS_RW
-static int it8801_get_target_channel(enum pwm_channel *channel,
-				     int type, int index)
+static int it8801_get_target_channel(enum pwm_channel *channel, int type,
+				     int index)
 {
 	switch (type) {
 	case EC_PWM_TYPE_GENERIC:
@@ -586,14 +577,13 @@ host_command_pwm_set_duty(struct host_cmd_handler_args *args)
 	if (it8801_get_target_channel(&channel, p->pwm_type, p->index))
 		return EC_RES_INVALID_PARAM;
 
-	duty = (uint32_t) p->duty * 255 / 65535;
+	duty = (uint32_t)p->duty * 255 / 65535;
 	it8801_pwm_set_raw_duty(channel, duty);
 	it8801_pwm_enable(channel, p->duty > 0);
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_DUTY,
-		     host_command_pwm_set_duty,
+DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_DUTY, host_command_pwm_set_duty,
 		     EC_VER_MASK(0));
 
 static enum ec_status
@@ -607,12 +597,11 @@ host_command_pwm_get_duty(struct host_cmd_handler_args *args)
 	if (it8801_get_target_channel(&channel, p->pwm_type, p->index))
 		return EC_RES_INVALID_PARAM;
 
-	r->duty = (uint32_t) it8801_pwm_get_raw_duty(channel) * 65535 / 255;
+	r->duty = (uint32_t)it8801_pwm_get_raw_duty(channel) * 65535 / 255;
 	args->response_size = sizeof(*r);
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_DUTY,
-		     host_command_pwm_get_duty,
+DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_DUTY, host_command_pwm_get_duty,
 		     EC_VER_MASK(0));
 #endif
diff --git a/board/bellis/board.h b/board/bellis/board.h
index 76f70f47c1..d502c4c5ef 100644
--- a/board/bellis/board.h
+++ b/board/bellis/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,13 +27,13 @@
 #undef STM32_PLLM
 #undef STM32_PLLN
 #undef STM32_PLLR
-#define STM32_PLLM	1
+#define STM32_PLLM 1
 #ifdef STM32_HSE_CLOCK
-#define STM32_PLLN	12
+#define STM32_PLLN 12
 #else
-#define STM32_PLLN	10
+#define STM32_PLLN 10
 #endif
-#define STM32_PLLR	2
+#define STM32_PLLR 2
 
 #define STM32_USE_PLL
 
@@ -65,13 +65,12 @@
 #define CONFIG_LED_ONOFF_STATES
 #define CONFIG_LED_POWER_LED
 
-#undef	CONFIG_WATCHDOG_PERIOD_MS
+#undef CONFIG_WATCHDOG_PERIOD_MS
 #define CONFIG_WATCHDOG_PERIOD_MS 4000
 
-
 /* Motion Sensors */
 #ifndef VARIANT_KUKUI_NO_SENSORS
-#define CONFIG_ACCEL_LIS2DWL    /* Lid accel */
+#define CONFIG_ACCEL_LIS2DWL /* Lid accel */
 #define CONFIG_ACCELGYRO_BMI160 /* Base accel */
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
@@ -93,34 +92,34 @@
 #endif /* VARIANT_KUKUI_NO_SENSORS */
 
 /* I2C ports */
-#define I2C_PORT_BC12               0
-#define I2C_PORT_TCPC0              0
-#define I2C_PORT_USB_MUX            0
-#define I2C_PORT_CHARGER            2
-#define I2C_PORT_SENSORS            2
-#define I2C_PORT_KB_DISCRETE        2
-#define I2C_PORT_VIRTUAL_BATTERY    I2C_PORT_BATTERY
-#define I2C_PORT_BATTERY            3
-#define I2C_PORT_TCPC0              0
+#define I2C_PORT_BC12 0
+#define I2C_PORT_TCPC0 0
+#define I2C_PORT_USB_MUX 0
+#define I2C_PORT_CHARGER 2
+#define I2C_PORT_SENSORS 2
+#define I2C_PORT_KB_DISCRETE 2
+#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
+#define I2C_PORT_BATTERY 3
+#define I2C_PORT_TCPC0 0
 
 #undef I2C_CONTROLLER_COUNT
 #undef I2C_PORT_COUNT
-#define I2C_CONTROLLER_COUNT        3
-#define I2C_PORT_COUNT              3
+#define I2C_CONTROLLER_COUNT 3
+#define I2C_PORT_COUNT 3
 
 /* IT8801 I2C address */
-#define KB_DISCRETE_I2C_ADDR_FLAGS  IT8801_I2C_ADDR1
+#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1
 
 /* Enable Accel over SPI */
-#define CONFIG_SPI_ACCEL_PORT    0  /* The first SPI controller port (SPI2) */
+#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */
 
 #define CONFIG_KEYBOARD_PROTOCOL_MKBP
 #define CONFIG_MKBP_EVENT
 #define CONFIG_MKBP_USE_GPIO
 /* Define the MKBP events which are allowed to wakeup AP in S3. */
-#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \
-		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK            \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
 
 #undef CONFIG_GMR_TABLET_MODE
 #undef GPIO_TABLET_MODE_L
diff --git a/board/bellis/build.mk b/board/bellis/build.mk
index f88dde8da8..604790d66c 100644
--- a/board/bellis/build.mk
+++ b/board/bellis/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/bellis/ec.tasklist b/board/bellis/ec.tasklist
index faecc9d405..2d69c1b113 100644
--- a/board/bellis/ec.tasklist
+++ b/board/bellis/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/bellis/gpio.inc b/board/bellis/gpio.inc
index 5fa1383483..a80ef27c97 100644
--- a/board/bellis/gpio.inc
+++ b/board/bellis/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2022 The Chromium OS Authors. All rights reserved.
+ * Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/bellis/led.c b/board/bellis/led.c
index a6a926a958..658533d075 100644
--- a/board/bellis/led.c
+++ b/board/bellis/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -18,33 +18,38 @@ __override const int led_charge_lvl_1 = 5;
 __override const int led_charge_lvl_2 = 97;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED,    LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER,  LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
 
 __override const struct led_descriptor
-led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    1 * LED_ONE_SEC },
+						  { LED_OFF,
+						    3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 __override void led_set_color_battery(enum ec_led_colors color)
diff --git a/board/berknip/battery.c b/board/berknip/battery.c
index 526375c0db..d024e710c3 100644
--- a/board/berknip/battery.c
+++ b/board/berknip/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/berknip/board.c b/board/berknip/board.c
index 36b6b4f68f..cade20a3c7 100644
--- a/board/berknip/board.c
+++ b/board/berknip/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -40,8 +40,8 @@ static void hdmi_hpd_interrupt(enum gpio_signal signal);
 
 #include "gpio_list.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 const struct pwm_t pwm_channels[] = {
 	[PWM_CH_KBLIGHT] = {
@@ -95,8 +95,7 @@ static void board_chipset_resume(void)
 	if (ec_config_has_hdmi_retimer_pi3hdx1204()) {
 		ioex_set_level(IOEX_HDMI_POWER_EN_DB, 1);
 		msleep(PI3HDX1204_POWER_ON_DELAY_MS);
-		pi3hdx1204_enable(I2C_PORT_TCPC1,
-				  PI3HDX1204_I2C_ADDR_FLAGS,
+		pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS,
 				  check_hdmi_hpd_status());
 	}
 }
@@ -105,9 +104,7 @@ DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
 static void board_chipset_suspend(void)
 {
 	if (ec_config_has_hdmi_retimer_pi3hdx1204()) {
-		pi3hdx1204_enable(I2C_PORT_TCPC1,
-				  PI3HDX1204_I2C_ADDR_FLAGS,
-				  0);
+		pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS, 0);
 		ioex_set_level(IOEX_HDMI_POWER_EN_DB, 0);
 	}
 
@@ -145,14 +142,21 @@ const struct usb_mux_driver usbc0_sbu_mux_driver = {
  * Since PI3USB221 is not a i2c device, .i2c_port and
  * .i2c_addr_flags are not required here.
  */
-const struct usb_mux usbc0_sbu_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &usbc0_sbu_mux_driver,
+const struct usb_mux_chain usbc0_sbu_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &usbc0_sbu_mux_driver,
+		},
 };
 
 /*****************************************************************************
  * USB-C MUX/Retimer dynamic configuration
  */
+
+/* Place holder for second mux in USBC1 chain */
+struct usb_mux_chain usbc1_mux1;
+
 static void setup_mux(void)
 {
 	if (ec_config_has_usbc1_retimer_tusb544()) {
@@ -163,11 +167,9 @@ static void setup_mux(void)
 		 * Replace usb_muxes[USBC_PORT_C1] with the AMD FP5
 		 * table entry.
 		 */
-		memcpy(&usb_muxes[USBC_PORT_C1],
-		       &usbc1_amd_fp5_usb_mux,
-		       sizeof(struct usb_mux));
+		usb_muxes[USBC_PORT_C1].mux = &usbc1_amd_fp5_usb_mux;
 		/* Set the TUSB544 as the secondary MUX */
-		usb_muxes[USBC_PORT_C1].next_mux = &usbc1_tusb544;
+		usbc1_mux1.mux = &usbc1_tusb544;
 	} else if (ec_config_has_usbc1_retimer_ps8743()) {
 		ccprints("C1 PS8743 detected");
 		/*
@@ -176,92 +178,84 @@ static void setup_mux(void)
 		 * Replace usb_muxes[USBC_PORT_C1] with the PS8743
 		 * table entry.
 		 */
-		memcpy(&usb_muxes[USBC_PORT_C1],
-		       &usbc1_ps8743,
-		       sizeof(struct usb_mux));
+		usb_muxes[USBC_PORT_C1].mux = &usbc1_ps8743;
 		/* Set the AMD FP5 as the secondary MUX */
-		usb_muxes[USBC_PORT_C1].next_mux = &usbc1_amd_fp5_usb_mux;
+		usbc1_mux1.mux = &usbc1_amd_fp5_usb_mux;
 		/* Don't have the AMD FP5 flip */
 		usbc1_amd_fp5_usb_mux.flags = USB_MUX_FLAG_SET_WITHOUT_FLIP;
 	}
 }
 
-struct usb_mux usb_muxes[] = {
+struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.i2c_port = I2C_PORT_USB_AP_MUX,
-		.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
-		.driver = &amd_fp5_usb_mux_driver,
-		.next_mux = &usbc0_sbu_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.i2c_port = I2C_PORT_USB_AP_MUX,
+			.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
+			.driver = &amd_fp5_usb_mux_driver,
+		},
+		.next = &usbc0_sbu_mux,
 	},
 	[USBC_PORT_C1] = {
 		/* Filled in dynamically at startup */
+		.next = &usbc1_mux1,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
 
 static int board_tusb544_mux_set(const struct usb_mux *me,
-				mux_state_t mux_state)
+				 mux_state_t mux_state)
 {
 	int rv = EC_SUCCESS;
 
 	if (mux_state & USB_PD_MUX_USB_ENABLED) {
-
-		rv = tusb544_i2c_field_update8(me,
-					TUSB544_REG_USB3_1_1,
-					TUSB544_EQ_RX_MASK,
-					TUSB544_EQ_RX_DFP_04_UFP_MINUS15);
+		rv = tusb544_i2c_field_update8(
+			me, TUSB544_REG_USB3_1_1, TUSB544_EQ_RX_MASK,
+			TUSB544_EQ_RX_DFP_04_UFP_MINUS15);
 		if (rv)
 			return rv;
 
-		rv = tusb544_i2c_field_update8(me,
-					TUSB544_REG_USB3_1_1,
-					TUSB544_EQ_TX_MASK,
-					TUSB544_EQ_TX_DFP_MINUS14_UFP_MINUS33);
+		rv = tusb544_i2c_field_update8(
+			me, TUSB544_REG_USB3_1_1, TUSB544_EQ_TX_MASK,
+			TUSB544_EQ_TX_DFP_MINUS14_UFP_MINUS33);
 		if (rv)
 			return rv;
 
-		rv = tusb544_i2c_field_update8(me,
-					TUSB544_REG_USB3_1_2,
-					TUSB544_EQ_RX_MASK,
-					TUSB544_EQ_RX_DFP_04_UFP_MINUS15);
+		rv = tusb544_i2c_field_update8(
+			me, TUSB544_REG_USB3_1_2, TUSB544_EQ_RX_MASK,
+			TUSB544_EQ_RX_DFP_04_UFP_MINUS15);
 		if (rv)
 			return rv;
 
-		rv = tusb544_i2c_field_update8(me,
-					TUSB544_REG_USB3_1_2,
-					TUSB544_EQ_TX_MASK,
-					TUSB544_EQ_TX_DFP_MINUS14_UFP_MINUS33);
+		rv = tusb544_i2c_field_update8(
+			me, TUSB544_REG_USB3_1_2, TUSB544_EQ_TX_MASK,
+			TUSB544_EQ_TX_DFP_MINUS14_UFP_MINUS33);
 		if (rv)
 			return rv;
 	}
 
 	if (mux_state & USB_PD_MUX_DP_ENABLED) {
-		rv = tusb544_i2c_field_update8(me,
-					TUSB544_REG_DISPLAYPORT_1,
-					TUSB544_EQ_RX_MASK,
-					TUSB544_EQ_RX_DFP_61_UFP_43);
+		rv = tusb544_i2c_field_update8(me, TUSB544_REG_DISPLAYPORT_1,
+					       TUSB544_EQ_RX_MASK,
+					       TUSB544_EQ_RX_DFP_61_UFP_43);
 		if (rv)
 			return rv;
 
-		rv = tusb544_i2c_field_update8(me,
-					TUSB544_REG_DISPLAYPORT_1,
-					TUSB544_EQ_TX_MASK,
-					TUSB544_EQ_TX_DFP_61_UFP_43);
+		rv = tusb544_i2c_field_update8(me, TUSB544_REG_DISPLAYPORT_1,
+					       TUSB544_EQ_TX_MASK,
+					       TUSB544_EQ_TX_DFP_61_UFP_43);
 		if (rv)
 			return rv;
 
-		rv = tusb544_i2c_field_update8(me,
-					TUSB544_REG_DISPLAYPORT_2,
-					TUSB544_EQ_RX_MASK,
-					TUSB544_EQ_RX_DFP_61_UFP_43);
+		rv = tusb544_i2c_field_update8(me, TUSB544_REG_DISPLAYPORT_2,
+					       TUSB544_EQ_RX_MASK,
+					       TUSB544_EQ_RX_DFP_61_UFP_43);
 		if (rv)
 			return rv;
 
-		rv = tusb544_i2c_field_update8(me,
-					TUSB544_REG_DISPLAYPORT_2,
-					TUSB544_EQ_TX_MASK,
-					TUSB544_EQ_TX_DFP_61_UFP_43);
+		rv = tusb544_i2c_field_update8(me, TUSB544_REG_DISPLAYPORT_2,
+					       TUSB544_EQ_TX_MASK,
+					       TUSB544_EQ_TX_DFP_61_UFP_43);
 		if (rv)
 			return rv;
 
@@ -346,10 +340,9 @@ static void hdmi_hpd_handler(void)
 
 	gpio_set_level(GPIO_EC_DP1_HPD, hpd);
 	ccprints("HDMI HPD %d", hpd);
-	pi3hdx1204_enable(I2C_PORT_TCPC1,
-			  PI3HDX1204_I2C_ADDR_FLAGS,
-			  chipset_in_or_transitioning_to_state(CHIPSET_STATE_ON)
-			  && hpd);
+	pi3hdx1204_enable(
+		I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS,
+		chipset_in_or_transitioning_to_state(CHIPSET_STATE_ON) && hpd);
 }
 DECLARE_DEFERRED(hdmi_hpd_handler);
 
@@ -366,7 +359,7 @@ static void hdmi_hpd_interrupt(enum gpio_signal signal)
 /* Physical fans. These are logically separate from pwm_channels. */
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = -1,
 };
@@ -401,7 +394,7 @@ int board_get_temp(int idx, int *temp_k)
 
 		/* adc power not ready when transition to S5 */
 		if (chipset_in_or_transitioning_to_state(
-			CHIPSET_STATE_SOFT_OFF))
+			    CHIPSET_STATE_SOFT_OFF))
 			return EC_ERROR_NOT_POWERED;
 
 		channel = ADC_TEMP_SENSOR_SOC;
@@ -413,7 +406,7 @@ int board_get_temp(int idx, int *temp_k)
 
 		/* adc power not ready when transition to S5 */
 		if (chipset_in_or_transitioning_to_state(
-			CHIPSET_STATE_SOFT_OFF))
+			    CHIPSET_STATE_SOFT_OFF))
 			return EC_ERROR_NOT_POWERED;
 
 		channel = ADC_TEMP_SENSOR_5V_REGULATOR;
@@ -487,8 +480,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_THERMISTOR_SOC \
-	{ \
+#define THERMAL_THERMISTOR_SOC   \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(62), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(66), \
@@ -506,7 +499,7 @@ __maybe_unused static const struct ec_thermal_config thermal_thermistor_soc =
  * TODO(b/202062363): Remove when clang is fixed.
  */
 #define THERMAL_THERMISTOR_CHARGER \
-	{ \
+	{                          \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(99), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(99), \
@@ -515,16 +508,16 @@ __maybe_unused static const struct ec_thermal_config thermal_thermistor_soc =
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(98), \
 		}, \
 		.temp_fan_off = C_TO_K(98), \
-		.temp_fan_max = C_TO_K(99), \
+		.temp_fan_max = C_TO_K(99),   \
 	}
-__maybe_unused static const struct ec_thermal_config
-	thermal_thermistor_charger = THERMAL_THERMISTOR_CHARGER;
+__maybe_unused static const struct ec_thermal_config thermal_thermistor_charger =
+	THERMAL_THERMISTOR_CHARGER;
 
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_THERMISTOR_5V \
-	{ \
+#define THERMAL_THERMISTOR_5V    \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(60), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(99), \
@@ -541,8 +534,8 @@ __maybe_unused static const struct ec_thermal_config thermal_thermistor_5v =
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CPU \
-	{ \
+#define THERMAL_CPU              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(100), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(105), \
@@ -562,13 +555,13 @@ struct fan_step {
 };
 
 static const struct fan_step fan_table0[] = {
-	{.on =  0, .off =  5, .rpm = 0},
-	{.on = 29, .off =  5, .rpm = 3700},
-	{.on = 38, .off = 19, .rpm = 4000},
-	{.on = 48, .off = 33, .rpm = 4500},
-	{.on = 62, .off = 43, .rpm = 4800},
-	{.on = 76, .off = 52, .rpm = 5200},
-	{.on = 100, .off = 67, .rpm = 6200},
+	{ .on = 0, .off = 5, .rpm = 0 },
+	{ .on = 29, .off = 5, .rpm = 3700 },
+	{ .on = 38, .off = 19, .rpm = 4000 },
+	{ .on = 48, .off = 33, .rpm = 4500 },
+	{ .on = 62, .off = 43, .rpm = 4800 },
+	{ .on = 76, .off = 52, .rpm = 5200 },
+	{ .on = 100, .off = 67, .rpm = 6200 },
 };
 /* All fan tables must have the same number of levels */
 #define NUM_FAN_LEVELS ARRAY_SIZE(fan_table0)
@@ -608,8 +601,7 @@ int fan_percent_to_rpm(int fan, int pct)
 
 	previous_pct = pct;
 
-	if (fan_table[current_level].rpm !=
-		fan_get_rpm_target(FAN_CH(fan)))
+	if (fan_table[current_level].rpm != fan_get_rpm_target(FAN_CH(fan)))
 		cprints(CC_THERMAL, "Setting fan RPM to %d",
 			fan_table[current_level].rpm);
 
@@ -632,15 +624,14 @@ DECLARE_HOOK(HOOK_INIT, setup_fans, HOOK_PRIO_DEFAULT);
  * The connector has 24 pins total, and there is no pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-		{0, 5}, {1, 1}, {1, 0}, {0, 6}, {0, 7},
-		{1, 4}, {1, 3}, {1, 6}, {1, 7}, {3, 1},
-		{2, 0}, {1, 5}, {2, 6}, {2, 7}, {2, 1},
-		{2, 4}, {2, 5}, {1, 2}, {2, 3}, {2, 2},
-		{3, 0}, {-1, -1}, {-1, -1}, {-1, -1},
+	{ 0, 5 }, { 1, 1 }, { 1, 0 }, { 0, 6 },	  { 0, 7 },   { 1, 4 },
+	{ 1, 3 }, { 1, 6 }, { 1, 7 }, { 3, 1 },	  { 2, 0 },   { 1, 5 },
+	{ 2, 6 }, { 2, 7 }, { 2, 1 }, { 2, 4 },	  { 2, 5 },   { 1, 2 },
+	{ 2, 3 }, { 2, 2 }, { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 },
 };
 
 const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 #endif
 
 /*****************************************************************************
@@ -685,9 +676,8 @@ enum gpio_signal board_usbc_port_to_hpd_gpio(int port)
 	 *    from USB-PD messages..
 	 */
 	else if (ec_config_has_mst_hub_rtd2141b())
-		return (board_ver >= 3)
-				? GPIO_USB_C1_HPD_IN_DB_V1
-				: GPIO_NO_HPD;
+		return (board_ver >= 3) ? GPIO_USB_C1_HPD_IN_DB_V1 :
+					  GPIO_NO_HPD;
 
 	/* USB-C1 OPT1 DB uses DP2_HPD. */
 	return GPIO_DP2_HPD;
diff --git a/board/berknip/board.h b/board/berknip/board.h
index 5ef9e33f0c..62261f284b 100644
--- a/board/berknip/board.h
+++ b/board/berknip/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -30,27 +30,27 @@
 #define CONFIG_POWER_SIGNAL_RUNTIME_CONFIG
 
 /* GPIO mapping from board specific name to EC common name. */
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_EC_BATT_PRES_ODL
-#define CONFIG_SCI_GPIO			GPIO_EC_FCH_SCI_ODL
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_AP_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT_L		GPIO_EC_EDP_BL_DISABLE
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_FCH_PWR_BTN_L
-#define GPIO_PCH_RSMRST_L		GPIO_EC_FCH_RSMRST_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S5_L		GPIO_SLP_S5_L
-#define GPIO_PCH_SYS_PWROK		GPIO_EC_FCH_PWROK
-#define GPIO_PCH_WAKE_L			GPIO_EC_FCH_WAKE_L
-#define GPIO_POWER_BUTTON_L		GPIO_EC_PWR_BTN_ODL
-#define GPIO_S5_PGOOD			GPIO_EC_PWROK_OD
-#define GPIO_SYS_RESET_L		GPIO_EC_SYS_RST_L
-#define GPIO_VOLUME_DOWN_L		GPIO_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
+#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL
+#define CONFIG_SCI_GPIO GPIO_EC_FCH_SCI_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_AP_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_EDP_BL_DISABLE
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PCH_PWRBTN_L GPIO_EC_FCH_PWR_BTN_L
+#define GPIO_PCH_RSMRST_L GPIO_EC_FCH_RSMRST_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L
+#define GPIO_PCH_SYS_PWROK GPIO_EC_FCH_PWROK
+#define GPIO_PCH_WAKE_L GPIO_EC_FCH_WAKE_L
+#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL
+#define GPIO_S5_PGOOD GPIO_EC_PWROK_OD
+#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L
+#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
 
 #ifndef __ASSEMBLER__
 
@@ -76,11 +76,7 @@ enum mft_channel {
 	MFT_CH_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_FAN,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_FAN, PWM_CH_COUNT };
 
 enum temp_sensor_id {
 	TEMP_SENSOR_CHARGER = 0,
@@ -90,11 +86,7 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum usba_port {
-	USBA_PORT_A0 = 0,
-	USBA_PORT_A1,
-	USBA_PORT_COUNT
-};
+enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT };
 
 /*****************************************************************************
  * CBI EC FW Configuration
@@ -147,49 +139,39 @@ enum ec_cfg_usb_db_type {
 
 #include "cbi_ec_fw_config.h"
 
-#define HAS_USBC1_RETIMER_PS8743 \
-			(BIT(BERKNIP_DB_T_OPT3_USBAC_HDMI_MSTHUB))
+#define HAS_USBC1_RETIMER_PS8743 (BIT(BERKNIP_DB_T_OPT3_USBAC_HDMI_MSTHUB))
 
 static inline bool ec_config_has_usbc1_retimer_ps8743(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_USBC1_RETIMER_PS8743);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_USBC1_RETIMER_PS8743);
 }
 
-#define HAS_USBC1_RETIMER_TUSB544 \
-			(BIT(BERKNIP_DB_T_OPT1_USBAC_HMDI))
+#define HAS_USBC1_RETIMER_TUSB544 (BIT(BERKNIP_DB_T_OPT1_USBAC_HMDI))
 
 static inline bool ec_config_has_usbc1_retimer_tusb544(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_USBC1_RETIMER_TUSB544);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_USBC1_RETIMER_TUSB544);
 }
 
-#define HAS_HDMI_RETIMER_PI3HDX1204 \
-			(BIT(BERKNIP_DB_T_OPT1_USBAC_HMDI))
+#define HAS_HDMI_RETIMER_PI3HDX1204 (BIT(BERKNIP_DB_T_OPT1_USBAC_HMDI))
 
 static inline bool ec_config_has_hdmi_retimer_pi3hdx1204(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_HDMI_RETIMER_PI3HDX1204);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_HDMI_RETIMER_PI3HDX1204);
 }
 
-#define HAS_MST_HUB_RTD2141B \
-			(BIT(BERKNIP_DB_T_OPT3_USBAC_HDMI_MSTHUB))
+#define HAS_MST_HUB_RTD2141B (BIT(BERKNIP_DB_T_OPT3_USBAC_HDMI_MSTHUB))
 
 static inline bool ec_config_has_mst_hub_rtd2141b(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_MST_HUB_RTD2141B);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_MST_HUB_RTD2141B);
 }
 
-#define HAS_HDMI_CONN_HPD \
-			(BIT(BERKNIP_DB_T_OPT1_USBAC_HMDI))
+#define HAS_HDMI_CONN_HPD (BIT(BERKNIP_DB_T_OPT1_USBAC_HMDI))
 
 static inline bool ec_config_has_hdmi_conn_hpd(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_HDMI_CONN_HPD);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_HDMI_CONN_HPD);
 }
 
 enum gpio_signal board_usbc_port_to_hpd_gpio(int port);
diff --git a/board/berknip/build.mk b/board/berknip/build.mk
index 1c0cbc4f63..45c71f962c 100644
--- a/board/berknip/build.mk
+++ b/board/berknip/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/berknip/ec.tasklist b/board/berknip/ec.tasklist
index 3a08ebc972..779bd4fdd6 100644
--- a/board/berknip/ec.tasklist
+++ b/board/berknip/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/berknip/gpio.inc b/board/berknip/gpio.inc
index 860cbba284..1bba6a3a69 100644
--- a/board/berknip/gpio.inc
+++ b/board/berknip/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/berknip/led.c b/board/berknip/led.c
index 79d691ffac..afa3c3e5d2 100644
--- a/board/berknip/led.c
+++ b/board/berknip/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -35,22 +35,19 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
-enum led_port {
-	RIGHT_PORT = 0,
-	LEFT_PORT
-};
+enum led_port { RIGHT_PORT = 0, LEFT_PORT };
 
 static void led_set_color_battery(int port, enum led_color color)
 {
 	enum gpio_signal amber_led, white_led;
 
 	amber_led = (port == RIGHT_PORT ? GPIO_LED_CHRG_L :
-				 GPIO_C1_CHARGE_LED_AMBER_DB_L);
+					  GPIO_C1_CHARGE_LED_AMBER_DB_L);
 	white_led = (port == RIGHT_PORT ? GPIO_LED_FULL_L :
-				 GPIO_C1_CHARGE_LED_WHITE_DB_L);
+					  GPIO_C1_CHARGE_LED_WHITE_DB_L);
 
 	switch (color) {
 	case LED_WHITE:
@@ -122,17 +119,16 @@ static void set_active_port_color(enum led_color color)
 
 	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
 		led_set_color_battery(RIGHT_PORT,
-				(port == RIGHT_PORT) ? color : LED_OFF);
+				      (port == RIGHT_PORT) ? color : LED_OFF);
 	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
 		led_set_color_battery(LEFT_PORT,
-				(port == LEFT_PORT) ? color : LED_OFF);
+				      (port == LEFT_PORT) ? color : LED_OFF);
 }
 
 static void led_set_battery(void)
 {
 	static int battery_ticks;
 	static int power_ticks;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
@@ -141,18 +137,20 @@ static void led_set_battery(void)
 	 * design, blinking both two side battery white LEDs to indicate
 	 * system suspend with non-charging state.
 	 */
-	if (chipset_in_state(CHIPSET_STATE_SUSPEND |
-				 CHIPSET_STATE_STANDBY) &&
-		charge_get_state() != PWR_STATE_CHARGE) {
-
+	if (chipset_in_state(CHIPSET_STATE_SUSPEND | CHIPSET_STATE_STANDBY) &&
+	    charge_get_state() != PWR_STATE_CHARGE) {
 		power_ticks++;
 
-		led_set_color_battery(RIGHT_PORT, power_ticks
-				% LED_TICKS_PER_CYCLE_S3 < POWER_LED_ON_S3_TICKS
-				? LED_WHITE : LED_OFF);
-		led_set_color_battery(LEFT_PORT, power_ticks
-				% LED_TICKS_PER_CYCLE_S3 < POWER_LED_ON_S3_TICKS
-				? LED_WHITE : LED_OFF);
+		led_set_color_battery(RIGHT_PORT,
+				      power_ticks % LED_TICKS_PER_CYCLE_S3 <
+						      POWER_LED_ON_S3_TICKS ?
+					      LED_WHITE :
+					      LED_OFF);
+		led_set_color_battery(LEFT_PORT,
+				      power_ticks % LED_TICKS_PER_CYCLE_S3 <
+						      POWER_LED_ON_S3_TICKS ?
+					      LED_WHITE :
+					      LED_OFF);
 		return;
 	}
 
@@ -166,9 +164,12 @@ static void led_set_battery(void)
 	case PWR_STATE_DISCHARGE:
 		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
 			if (charge_get_percent() < 10)
-				led_set_color_battery(RIGHT_PORT,
-					(battery_ticks % LED_TICKS_PER_CYCLE
-					 < LED_ON_TICKS) ? LED_WHITE : LED_OFF);
+				led_set_color_battery(
+					RIGHT_PORT,
+					(battery_ticks % LED_TICKS_PER_CYCLE <
+					 LED_ON_TICKS) ?
+						LED_WHITE :
+						LED_OFF);
 			else
 				led_set_color_battery(RIGHT_PORT, LED_OFF);
 		}
@@ -177,19 +178,20 @@ static void led_set_battery(void)
 			led_set_color_battery(LEFT_PORT, LED_OFF);
 		break;
 	case PWR_STATE_ERROR:
-		set_active_port_color((battery_ticks & 0x2) ?
-				LED_WHITE : LED_OFF);
+		set_active_port_color((battery_ticks & 0x2) ? LED_WHITE :
+							      LED_OFF);
 		break;
 	case PWR_STATE_CHARGE_NEAR_FULL:
 		set_active_port_color(LED_WHITE);
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			set_active_port_color((battery_ticks %
-				LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-				LED_AMBER : LED_OFF);
-		else
-			set_active_port_color(LED_WHITE);
+		set_active_port_color(LED_WHITE);
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		set_active_port_color(
+			(battery_ticks % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
+				LED_AMBER :
+				LED_OFF);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
diff --git a/board/blipper/battery.c b/board/blipper/battery.c
index 114cfbc313..61ad95d4b7 100644
--- a/board/blipper/battery.c
+++ b/board/blipper/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/blipper/board.c b/board/blipper/board.c
index c980e3ce0f..766f55579c 100644
--- a/board/blipper/board.c
+++ b/board/blipper/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -47,8 +47,8 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTF(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTF(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
 #define INT_RECHECK_US 5000
 
 __override struct keyboard_scan_config keyscan_config = {
@@ -105,7 +105,6 @@ static void usb_c0_interrupt(enum gpio_signal s)
 
 	/* Check the line again in 5ms */
 	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-
 }
 
 static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
@@ -119,34 +118,26 @@ static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH0
-	},
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH2
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH3
-	},
-	[ADC_TEMP_SENSOR_3] = {
-		.name = "TEMP_SENSOR3",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH15
-	},
+	[ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH0 },
+	[ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH2 },
+	[ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH3 },
+	[ADC_TEMP_SENSOR_3] = { .name = "TEMP_SENSOR3",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH15 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
@@ -182,12 +173,15 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 };
 
 /* USB Muxes */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+			},
 	},
 };
 
@@ -208,16 +202,14 @@ static const struct ec_response_keybd_config blipper_keybd = {
 	.capabilities = KEYBD_CAP_SCRNLOCK_KEY | KEYBD_CAP_NUMERIC_KEYPAD,
 };
 
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
-		return &blipper_keybd;
+	return &blipper_keybd;
 }
 
 /* USB-A charging control */
-const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_EN_USB_A0_VBUS
-};
+const int usb_port_enable[USB_PORT_COUNT] = { GPIO_EN_USB_A0_VBUS };
 
 static uint32_t board_id;
 
@@ -226,11 +218,9 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrices to rotate accelerometers into the standard reference. */
-static const mat33_fp_t lid_lis2dwl_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_lis2dwl_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					    { FLOAT_TO_FP(1), 0, 0 },
+					    { 0, 0, FLOAT_TO_FP(-1) } };
 
 static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
 
@@ -310,11 +300,9 @@ struct motion_sensor_t motion_sensors[] = {
 };
 
 static struct icm_drv_data_t g_icm42607_data;
-const mat33_fp_t based_ref_icm42607 = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t based_ref_icm42607 = { { FLOAT_TO_FP(1), 0, 0 },
+					{ 0, FLOAT_TO_FP(1), 0 },
+					{ 0, 0, FLOAT_TO_FP(1) } };
 struct motion_sensor_t icm42607_base_accel = {
 	 .name = "Base Accel",
 	 .active_mask = SENSOR_ACTIVE_S0_S3,
@@ -342,28 +330,26 @@ struct motion_sensor_t icm42607_base_accel = {
 	 },
 };
 struct motion_sensor_t icm42607_base_gyro = {
-	 .name = "Base Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_ICM42607,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &icm42607_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_icm42607_data,
-	 .port = I2C_PORT_ACCEL,
-	 .i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &based_ref_icm42607,
-	 .min_frequency = ICM42607_GYRO_MIN_FREQ,
-	 .max_frequency = ICM42607_GYRO_MAX_FREQ,
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM42607,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm42607_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm42607_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &based_ref_icm42607,
+	.min_frequency = ICM42607_GYRO_MIN_FREQ,
+	.max_frequency = ICM42607_GYRO_MAX_FREQ,
 };
 
 static struct bmi_drv_data_t g_bmi220_data;
-const mat33_fp_t based_ref_bmi220 = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t based_ref_bmi220 = { { 0, FLOAT_TO_FP(1), 0 },
+				      { FLOAT_TO_FP(-1), 0, 0 },
+				      { 0, 0, FLOAT_TO_FP(1) } };
 struct motion_sensor_t bmi220_base_accel = {
 	 .name = "Base Accel",
 	 .active_mask = SENSOR_ACTIVE_S0_S3,
@@ -391,20 +377,20 @@ struct motion_sensor_t bmi220_base_accel = {
 	 },
 };
 struct motion_sensor_t bmi220_base_gyro = {
-	 .name = "Base Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI220,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi260_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi220_data,
-	 .port = I2C_PORT_ACCEL,
-	 .i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &based_ref_bmi220,
-	 .min_frequency = BMI_GYRO_MIN_FREQ,
-	 .max_frequency = BMI_GYRO_MAX_FREQ,
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_BMI220,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &bmi260_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_bmi220_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &based_ref_bmi220,
+	.min_frequency = BMI_GYRO_MIN_FREQ,
+	.max_frequency = BMI_GYRO_MAX_FREQ,
 };
 
 unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
@@ -448,15 +434,13 @@ void board_init(void)
 		 * line to float.
 		 */
 		gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L,
-				GPIO_INPUT | GPIO_PULL_DOWN);
+			       GPIO_INPUT | GPIO_PULL_DOWN);
 
 		/* Disable Volume keys for blipper */
 		button_disable_gpio(BUTTON_VOLUME_UP);
 		button_disable_gpio(BUTTON_VOLUME_DOWN);
-		gpio_set_flags(GPIO_VOLDN_BTN_ODL,
-				GPIO_INPUT | GPIO_PULL_DOWN);
-		gpio_set_flags(GPIO_VOLUP_BTN_ODL,
-				GPIO_INPUT | GPIO_PULL_DOWN);
+		gpio_set_flags(GPIO_VOLDN_BTN_ODL, GPIO_INPUT | GPIO_PULL_DOWN);
+		gpio_set_flags(GPIO_VOLUP_BTN_ODL, GPIO_INPUT | GPIO_PULL_DOWN);
 	} else {
 		if (get_cbi_ssfc_base_sensor() == SSFC_SENSOR_ICM42607) {
 			motion_sensors[BASE_ACCEL] = icm42607_base_accel;
@@ -579,7 +563,6 @@ int board_is_sourcing_vbus(int port)
 
 	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
 	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
-
 }
 
 int board_set_active_charge_port(int port)
@@ -591,8 +574,7 @@ int board_set_active_charge_port(int port)
 
 	/* Disable all ports. */
 	if (port == CHARGE_PORT_NONE) {
-		tcpc_write(0, TCPC_REG_COMMAND,
-				TCPC_REG_COMMAND_SNK_CTRL_LOW);
+		tcpc_write(0, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
 		raa489000_enable_asgate(0, false);
 		return EC_SUCCESS;
 	}
@@ -605,8 +587,7 @@ int board_set_active_charge_port(int port)
 
 	/* Enable requested charge port. */
 	if (raa489000_enable_asgate(port, true) ||
-	    tcpc_write(0, TCPC_REG_COMMAND,
-		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
+	    tcpc_write(0, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
 		CPRINTUSB("p%d: sink path enable failed.", port);
 		return EC_ERROR_UNKNOWN;
 	}
@@ -638,18 +619,18 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
 /* Thermistors */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Charge",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "5V_Inductor",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_3},
+	[TEMP_SENSOR_1] = { .name = "Charge",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "5V_Inductor",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
diff --git a/board/blipper/board.h b/board/blipper/board.h
index 2e7ad6c6b5..379a92a007 100644
--- a/board/blipper/board.h
+++ b/board/blipper/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,6 +24,7 @@
 /* Charger */
 #define CONFIG_CHARGE_RAMP_HW
 #define CONFIG_CHARGER_RAA489000
+#define PD_MAX_VOLTAGE_MV 20000
 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 #define CONFIG_CHARGER_SENSE_RESISTOR 10
 #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
@@ -36,20 +37,20 @@
 #define CONFIG_LED_ONOFF_STATES
 
 /*SENSOR*/
-#define I2C_PORT_ACCEL	I2C_PORT_SENSOR
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
 #define CONFIG_CMD_ACCELS
 #define CONFIG_CMD_ACCEL_INFO
 #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
 
-#define CONFIG_ACCEL_LIS2DWL		/* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM    /* Base accel */
+#define CONFIG_ACCEL_LIS2DWL /* Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
 #define CONFIG_ACCELGYRO_ICM42607
 #define CONFIG_ACCELGYRO_BMI220
 
 /* Lid operates in forced mode, base in FIFO */
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
 #define CONFIG_ACCEL_FIFO
-#define CONFIG_ACCEL_FIFO_SIZE 256	/* Must be a power of 2 */
+#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */
 #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
 
 #define CONFIG_I2C_XFER_LARGE_TRANSFER
@@ -125,19 +126,14 @@ enum pwm_channel {
 };
 
 /* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
 /* ADC channels */
 enum adc_channel {
-	ADC_VSNS_PP3300_A,     /* ADC0 */
-	ADC_TEMP_SENSOR_1,     /* ADC2 */
-	ADC_TEMP_SENSOR_2,     /* ADC3 */
-	ADC_TEMP_SENSOR_3,     /* ADC15 */
+	ADC_VSNS_PP3300_A, /* ADC0 */
+	ADC_TEMP_SENSOR_1, /* ADC2 */
+	ADC_TEMP_SENSOR_2, /* ADC3 */
+	ADC_TEMP_SENSOR_3, /* ADC15 */
 	ADC_CH_COUNT
 };
 
diff --git a/board/blipper/build.mk b/board/blipper/build.mk
index 8167ca9966..01b890bf29 100644
--- a/board/blipper/build.mk
+++ b/board/blipper/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/blipper/cbi_ssfc.c b/board/blipper/cbi_ssfc.c
index c4b859f133..81f3ee0dad 100644
--- a/board/blipper/cbi_ssfc.c
+++ b/board/blipper/cbi_ssfc.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
 
 enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
 {
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
 }
 
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
 {
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
 }
diff --git a/board/blipper/cbi_ssfc.h b/board/blipper/cbi_ssfc.h
index f4a51b8e91..bc6bc92286 100644
--- a/board/blipper/cbi_ssfc.h
+++ b/board/blipper/cbi_ssfc.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -57,5 +57,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
  */
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
 
-
 #endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/blipper/ec.tasklist b/board/blipper/ec.tasklist
index bdcbcdf074..8ccdfc81b2 100644
--- a/board/blipper/ec.tasklist
+++ b/board/blipper/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/blipper/gpio.inc b/board/blipper/gpio.inc
index 8558aab638..215f31a281 100644
--- a/board/blipper/gpio.inc
+++ b/board/blipper/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/blipper/led.c b/board/blipper/led.c
index c28b39f6af..c6617d081c 100644
--- a/board/blipper/led.c
+++ b/board/blipper/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,42 +11,46 @@
 #include "gpio.h"
 #include "pwm.h"
 
-#define LED_OFF_LVL	0
-#define LED_ON_LVL	1
+#define LED_OFF_LVL 0
+#define LED_ON_LVL 1
 
 __override const int led_charge_lvl_1 = 5;
 
 __override const int led_charge_lvl_2 = 97;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED,   LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,   1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
 
 __override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    1 * LED_ONE_SEC },
+						  { LED_OFF,
+						    3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 __override void led_set_color_battery(enum ec_led_colors color)
diff --git a/board/blipper/usb_pd_policy.c b/board/blipper/usb_pd_policy.c
index b7c0ca21df..a7633b73ac 100644
--- a/board/blipper/usb_pd_policy.c
+++ b/board/blipper/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,8 +13,8 @@
 #include "driver/tcpm/tcpci.h"
 #include "usb_pd.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
diff --git a/board/bloog/battery.c b/board/bloog/battery.c
index f67b21d3b5..af3282576a 100644
--- a/board/bloog/battery.c
+++ b/board/bloog/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/bloog/board.c b/board/bloog/board.c
index 47802bf584..9250dfe299 100644
--- a/board/bloog/board.c
+++ b/board/bloog/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -40,13 +40,13 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
-#define USB_PD_PORT_ANX7447	0
-#define USB_PD_PORT_PS8751	1
+#define USB_PD_PORT_ANX7447 0
+#define USB_PD_PORT_PS8751 1
 
 static uint8_t sku_id;
 
@@ -71,32 +71,32 @@ static void ppc_interrupt(enum gpio_signal signal)
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_AMB] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_AMB] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				  ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_CHARGER] = { "TEMP_CHARGER", NPCX_ADC_CH1,
+				      ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 },
 	/* Vbus C0 sensing (10x voltage divider). PPVAR_USB_C0_VBUS */
-	[ADC_VBUS_C0] = {
-		"VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
+	[ADC_VBUS_C0] = { "VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT * 10,
+			  ADC_READ_MAX + 1, 0 },
 	/* Vbus C1 sensing (10x voltage divider). PPVAR_USB_C1_VBUS */
-	[ADC_VBUS_C1] = {
-		"VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
+	[ADC_VBUS_C1] = { "VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT * 10,
+			  ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp,
-				 .idx = 0},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
+	[TEMP_SENSOR_BATTERY] = { .name = "Battery",
+				  .type = TEMP_SENSOR_TYPE_BATTERY,
+				  .read = charge_get_battery_temp,
+				  .idx = 0 },
+	[TEMP_SENSOR_AMBIENT] = { .name = "Ambient",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_51k1_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_AMB },
+	[TEMP_SENSOR_CHARGER] = { .name = "Charger",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_13k7_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_CHARGER },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -106,23 +106,17 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t lid_a_cover_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0,  FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t lid_a_cover_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				     { 0, FLOAT_TO_FP(1), 0 },
+				     { 0, 0, FLOAT_TO_FP(-1) } };
 
-const mat33_fp_t lid_b_cover_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
+const mat33_fp_t lid_b_cover_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				     { 0, FLOAT_TO_FP(-1), 0 },
+				     { 0, 0, FLOAT_TO_FP(1) } };
 
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				       { 0, FLOAT_TO_FP(-1), 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
 
 /* sensor private data */
 static struct kionix_accel_data kx022_data;
@@ -220,10 +214,10 @@ int board_is_convertible(void)
 	 * Bipship: 53, 54, 55, 56
 	 * Unprovisioned: 255
 	 */
-	return sku_id == 33 || sku_id == 34 || sku_id == 35 || sku_id == 36
-		|| sku_id == 49 || sku_id == 50 || sku_id == 51 || sku_id == 52
-		|| sku_id == 53 || sku_id == 54 || sku_id == 55 || sku_id == 56
-		|| sku_id == 255;
+	return sku_id == 33 || sku_id == 34 || sku_id == 35 || sku_id == 36 ||
+	       sku_id == 49 || sku_id == 50 || sku_id == 51 || sku_id == 52 ||
+	       sku_id == 53 || sku_id == 54 || sku_id == 55 || sku_id == 56 ||
+	       sku_id == 255;
 }
 
 static void board_update_sensor_config_from_sku(void)
@@ -234,8 +228,8 @@ static void board_update_sensor_config_from_sku(void)
 		gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
 
 		/* Override sensor marix for Bipship. */
-		if (sku_id == 53 || sku_id == 54 || sku_id == 55
-			|| sku_id == 56)
+		if (sku_id == 53 || sku_id == 54 || sku_id == 55 ||
+		    sku_id == 56)
 			motion_sensors[LID_ACCEL].rot_standard_ref =
 				&lid_b_cover_ref;
 	} else {
@@ -265,10 +259,10 @@ void board_hibernate_late(void)
 
 	const uint32_t hibernate_pins[][2] = {
 		/* Turn off LEDs before going to hibernate */
-		{GPIO_LED_WHITE_C0_L, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_LED_AMBER_C0_L, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_LED_WHITE_C1_L, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_LED_AMBER_C1_L, GPIO_INPUT | GPIO_PULL_UP},
+		{ GPIO_LED_WHITE_C0_L, GPIO_INPUT | GPIO_PULL_UP },
+		{ GPIO_LED_AMBER_C0_L, GPIO_INPUT | GPIO_PULL_UP },
+		{ GPIO_LED_WHITE_C1_L, GPIO_INPUT | GPIO_PULL_UP },
+		{ GPIO_LED_AMBER_C1_L, GPIO_INPUT | GPIO_PULL_UP },
 	};
 
 	for (i = 0; i < ARRAY_SIZE(hibernate_pins); ++i)
@@ -297,15 +291,15 @@ __override void lid_angle_peripheral_enable(int enable)
  * The connector has 24 pins total, and there is no pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-		{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-		{0, 7}, {1, 4}, {1, 3}, {1, 6}, {1, 7},
-		{3, 1}, {2, 0}, {1, 5}, {2, 6}, {2, 7},
-		{2, 1}, {2, 4}, {2, 5}, {1, 2}, {2, 3},
-		{2, 2}, {3, 0}, {-1, -1}, {-1, -1}, {-1, -1},
+	{ -1, -1 }, { 0, 5 }, { 1, 1 },	  { 1, 0 },   { 0, 6 },
+	{ 0, 7 },   { 1, 4 }, { 1, 3 },	  { 1, 6 },   { 1, 7 },
+	{ 3, 1 },   { 2, 0 }, { 1, 5 },	  { 2, 6 },   { 2, 7 },
+	{ 2, 1 },   { 2, 4 }, { 2, 5 },	  { 1, 2 },   { 2, 3 },
+	{ 2, 2 },   { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 },
 };
 
 const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 #endif
 
 void board_overcurrent_event(int port, int is_overcurrented)
@@ -323,9 +317,8 @@ __override uint32_t board_override_feature_flags0(uint32_t flags0)
 	/*
 	 * Remove keyboard backlight feature for devices that don't support it.
 	 */
-	if (sku_id == 33 || sku_id == 36 || sku_id == 51 ||
-		sku_id == 52 || sku_id == 53 || sku_id == 55 ||
-		sku_id == 66 || sku_id == 68)
+	if (sku_id == 33 || sku_id == 36 || sku_id == 51 || sku_id == 52 ||
+	    sku_id == 53 || sku_id == 55 || sku_id == 66 || sku_id == 68)
 		return (flags0 & ~EC_FEATURE_MASK_0(EC_FEATURE_PWM_KEYB));
 	else
 		return flags0;
diff --git a/board/bloog/board.h b/board/bloog/board.h
index d32fb43578..38e8484df2 100644
--- a/board/bloog/board.h
+++ b/board/bloog/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,8 +27,8 @@
 #define CONFIG_LED_COMMON
 
 /* Sensors */
-#define CONFIG_ACCEL_KX022		/* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM	/* Base accel */
+#define CONFIG_ACCEL_KX022 /* Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
 
 /* Sensors without hardware FIFO are in forced mode */
 #define CONFIG_ACCEL_FORCE_MODE_MASK (1 << LID_ACCEL)
@@ -59,10 +59,10 @@
 #include "registers.h"
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_AMB,		/* ADC0 */
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC1 */
-	ADC_VBUS_C0,			/* ADC9 */
-	ADC_VBUS_C1,			/* ADC4 */
+	ADC_TEMP_SENSOR_AMB, /* ADC0 */
+	ADC_TEMP_SENSOR_CHARGER, /* ADC1 */
+	ADC_VBUS_C0, /* ADC9 */
+	ADC_VBUS_C1, /* ADC4 */
 	ADC_CH_COUNT
 };
 
@@ -73,18 +73,10 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_COUNT };
 
 /* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
 enum battery_type {
 	BATTERY_DYNAPACK_COS,
diff --git a/board/bloog/build.mk b/board/bloog/build.mk
index 137e208b53..fee77e38b5 100644
--- a/board/bloog/build.mk
+++ b/board/bloog/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/bloog/ec.tasklist b/board/bloog/ec.tasklist
index 6eac78a042..6c56976091 100644
--- a/board/bloog/ec.tasklist
+++ b/board/bloog/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/bloog/gpio.inc b/board/bloog/gpio.inc
index 3ee2f88eb1..f07b380974 100644
--- a/board/bloog/gpio.inc
+++ b/board/bloog/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/bloog/led.c b/board/bloog/led.c
index 609b330a56..22f5bc5523 100644
--- a/board/bloog/led.c
+++ b/board/bloog/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -24,11 +24,9 @@
 #define LED_TICKS_PER_CYCLE 10
 #define LED_ON_TICKS 5
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_LEFT_LED,
-	EC_LED_ID_RIGHT_LED,
-	EC_LED_ID_POWER_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_LEFT_LED,
+					     EC_LED_ID_RIGHT_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -36,15 +34,15 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static void led_set_color_battery(int port, enum led_color color)
 {
 	gpio_set_level(port ? GPIO_LED_AMBER_C1_L : GPIO_LED_AMBER_C0_L,
-		(color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
+		       (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
 	gpio_set_level(port ? GPIO_LED_WHITE_C1_L : GPIO_LED_WHITE_C0_L,
-		(color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF);
+		       (color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF);
 }
 
 void led_set_color_power(enum led_color color)
@@ -130,7 +128,6 @@ static void led_set_battery(void)
 {
 	static int battery_ticks;
 	static int power_ticks;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
@@ -141,15 +138,14 @@ static void led_set_battery(void)
 	 */
 	if (!board_is_convertible()) {
 		if (chipset_in_state(CHIPSET_STATE_SUSPEND |
-					 CHIPSET_STATE_STANDBY) &&
-			charge_get_state() != PWR_STATE_CHARGE) {
-
+				     CHIPSET_STATE_STANDBY) &&
+		    charge_get_state() != PWR_STATE_CHARGE) {
 			power_ticks++;
 
-			led_set_color_battery(0, power_ticks & 0x4 ?
-						  LED_WHITE : LED_OFF);
-			led_set_color_battery(1, power_ticks & 0x4 ?
-						  LED_WHITE : LED_OFF);
+			led_set_color_battery(0, power_ticks & 0x4 ? LED_WHITE :
+								     LED_OFF);
+			led_set_color_battery(1, power_ticks & 0x4 ? LED_WHITE :
+								     LED_OFF);
 			return;
 		}
 	}
@@ -164,9 +160,12 @@ static void led_set_battery(void)
 	case PWR_STATE_DISCHARGE:
 		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
 			if (charge_get_percent() < 10)
-				led_set_color_battery(1, (battery_ticks %
-					LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-					LED_WHITE : LED_OFF);
+				led_set_color_battery(
+					1,
+					(battery_ticks % LED_TICKS_PER_CYCLE <
+					 LED_ON_TICKS) ?
+						LED_WHITE :
+						LED_OFF);
 			else
 				led_set_color_battery(1, LED_OFF);
 		}
@@ -175,19 +174,20 @@ static void led_set_battery(void)
 			led_set_color_battery(0, LED_OFF);
 		break;
 	case PWR_STATE_ERROR:
-		set_active_port_color((battery_ticks & 0x2) ?
-				LED_WHITE : LED_OFF);
+		set_active_port_color((battery_ticks & 0x2) ? LED_WHITE :
+							      LED_OFF);
 		break;
 	case PWR_STATE_CHARGE_NEAR_FULL:
 		set_active_port_color(LED_WHITE);
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			set_active_port_color((battery_ticks %
-				LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-				LED_AMBER : LED_OFF);
-		else
-			set_active_port_color(LED_WHITE);
+		set_active_port_color(LED_WHITE);
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		set_active_port_color(
+			(battery_ticks % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
+				LED_AMBER :
+				LED_OFF);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
@@ -205,9 +205,10 @@ static void led_set_power(void)
 		led_set_color_power(LED_WHITE);
 	else if (chipset_in_state(CHIPSET_STATE_SUSPEND |
 				  CHIPSET_STATE_STANDBY))
-		led_set_color_power((power_tick %
-			LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-			LED_WHITE : LED_OFF);
+		led_set_color_power(
+			(power_tick % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
+				LED_WHITE :
+				LED_OFF);
 	else
 		led_set_color_power(LED_OFF);
 }
diff --git a/board/bobba/battery.c b/board/bobba/battery.c
index dbebf250d9..ab77c44062 100644
--- a/board/bobba/battery.c
+++ b/board/bobba/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/bobba/board.c b/board/bobba/board.c
index 1ab1dad660..64e713a55e 100644
--- a/board/bobba/board.c
+++ b/board/bobba/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -48,11 +48,11 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define USB_PD_PORT_ANX7447	0
-#define USB_PD_PORT_PS8751	1
+#define USB_PD_PORT_ANX7447 0
+#define USB_PD_PORT_PS8751 1
 
 static uint8_t sku_id;
 
@@ -62,17 +62,16 @@ static uint8_t sku_id;
  * that we don't have pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-		{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-		{0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3},
-		{-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0},
-		{1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4},
-		{2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0},
-		{-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1},
-		{-1, -1},
+	{ -1, -1 }, { 0, 5 },	{ 1, 1 }, { 1, 0 },   { 0, 6 },	  { 0, 7 },
+	{ -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 },   { -1, -1 }, { 1, 6 },
+	{ 1, 7 },   { 3, 1 },	{ 2, 0 }, { 1, 5 },   { 2, 6 },	  { 2, 7 },
+	{ 2, 1 },   { 2, 4 },	{ 2, 5 }, { 1, 2 },   { 2, 3 },	  { 2, 2 },
+	{ 3, 0 },   { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 },	  { -1, -1 },
+	{ -1, -1 },
 };
 
 const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 
 /* Check PPC ID Pin and Board ver to decide which one ppc is used. */
 static bool support_syv_ppc(void)
@@ -115,31 +114,31 @@ static void ppc_interrupt(enum gpio_signal signal)
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_AMB] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_AMB] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				  ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_CHARGER] = { "TEMP_CHARGER", NPCX_ADC_CH1,
+				      ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 },
 	/* Vbus sensing (1/10 voltage divider). */
-	[ADC_VBUS_C0] = {
-		"VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
-	[ADC_VBUS_C1] = {
-		"VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
+	[ADC_VBUS_C0] = { "VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT * 10,
+			  ADC_READ_MAX + 1, 0 },
+	[ADC_VBUS_C1] = { "VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT * 10,
+			  ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp,
-				 .idx = 0},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
+	[TEMP_SENSOR_BATTERY] = { .name = "Battery",
+				  .type = TEMP_SENSOR_TYPE_BATTERY,
+				  .read = charge_get_battery_temp,
+				  .idx = 0 },
+	[TEMP_SENSOR_AMBIENT] = { .name = "Ambient",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_51k1_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_AMB },
+	[TEMP_SENSOR_CHARGER] = { .name = "Charger",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_13k7_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_CHARGER },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -149,17 +148,13 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0,  0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+				       { FLOAT_TO_FP(1), 0, 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
 
-const mat33_fp_t base_icm_ref = {
-	{ FLOAT_TO_FP(-1), 0,  0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_icm_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				  { 0, FLOAT_TO_FP(-1), 0 },
+				  { 0, 0, FLOAT_TO_FP(1) } };
 
 /*
  * Sparky360 SKU ID 26 has AR Cam, and move base accel/gryo to AR Cam board.
@@ -174,9 +169,9 @@ const mat33_fp_t base_icm_ref = {
  *                                           |0   0.27564   0.96126|
  */
 const mat33_fp_t base_ar_cam_ref = {
-	{ 0, FLOAT_TO_FP(-0.96126), FLOAT_TO_FP(0.27564)},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(0.27564), FLOAT_TO_FP(0.96126)}
+	{ 0, FLOAT_TO_FP(-0.96126), FLOAT_TO_FP(0.27564) },
+	{ FLOAT_TO_FP(1), 0, 0 },
+	{ 0, FLOAT_TO_FP(0.27564), FLOAT_TO_FP(0.96126) }
 };
 
 /* sensor private data */
@@ -301,20 +296,20 @@ struct motion_sensor_t icm426xx_base_accel = {
 };
 
 struct motion_sensor_t icm426xx_base_gyro = {
-	 .name = "Base Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_ICM426XX,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &icm426xx_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_icm426xx_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &base_icm_ref,
-	 .min_frequency = ICM426XX_GYRO_MIN_FREQ,
-	 .max_frequency = ICM426XX_GYRO_MAX_FREQ,
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &base_icm_ref,
+	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
+	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
 };
 
 static int board_is_convertible(void)
@@ -323,9 +318,8 @@ static int board_is_convertible(void)
 	 * SKU ID of Bobba360, Sparky360, & unprovisioned: 9, 10, 11, 12,
 	 * 25, 26, 27, 255
 	 */
-	return sku_id == 9 || sku_id == 10 || sku_id == 11 || sku_id == 12
-		|| sku_id == 25 || sku_id == 26 || sku_id == 27
-		|| sku_id == 255;
+	return sku_id == 9 || sku_id == 10 || sku_id == 11 || sku_id == 12 ||
+	       sku_id == 25 || sku_id == 26 || sku_id == 27 || sku_id == 255;
 }
 
 static int board_with_ar_cam(void)
@@ -407,8 +401,9 @@ static void board_usb_charge_mode_init(void)
 	int i;
 
 	/*
-	 * Only overriding the USB_DISALLOW_SUSPEND_CHARGE in RO is enough because
-	 * USB_SYSJUMP_TAG preserves the settings to RW. And we should honor to it.
+	 * Only overriding the USB_DISALLOW_SUSPEND_CHARGE in RO is enough
+	 * because USB_SYSJUMP_TAG preserves the settings to RW. And we should
+	 * honor to it.
 	 */
 	if (system_jumped_late())
 		return;
@@ -425,7 +420,7 @@ static void board_usb_charge_mode_init(void)
 	 */
 	for (i = 0; i < CONFIG_USB_PORT_POWER_SMART_PORT_COUNT; i++)
 		usb_charge_set_mode(i, CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE,
-				USB_DISALLOW_SUSPEND_CHARGE);
+				    USB_DISALLOW_SUSPEND_CHARGE);
 }
 /*
  * usb_charge_init() is hooked in HOOK_PRIO_DEFAULT and set inhibit_charge to
@@ -462,15 +457,15 @@ __override uint32_t board_override_feature_flags0(uint32_t flags0)
 }
 
 static const struct ppc_config_t ppc_syv682x_port0 = {
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
+	.i2c_port = I2C_PORT_TCPC0,
+	.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+	.drv = &syv682x_drv,
 };
 
 static const struct ppc_config_t ppc_syv682x_port1 = {
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
+	.i2c_port = I2C_PORT_TCPC1,
+	.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+	.drv = &syv682x_drv,
 };
 
 static void board_setup_ppc(void)
@@ -478,11 +473,9 @@ static void board_setup_ppc(void)
 	if (!support_syv_ppc())
 		return;
 
-	memcpy(&ppc_chips[USB_PD_PORT_TCPC_0],
-	       &ppc_syv682x_port0,
+	memcpy(&ppc_chips[USB_PD_PORT_TCPC_0], &ppc_syv682x_port0,
 	       sizeof(struct ppc_config_t));
-	memcpy(&ppc_chips[USB_PD_PORT_TCPC_1],
-	       &ppc_syv682x_port1,
+	memcpy(&ppc_chips[USB_PD_PORT_TCPC_1], &ppc_syv682x_port1,
 	       sizeof(struct ppc_config_t));
 
 	gpio_set_flags(GPIO_USB_PD_C0_INT_ODL, GPIO_INT_BOTH);
@@ -490,14 +483,14 @@ static void board_setup_ppc(void)
 }
 DECLARE_HOOK(HOOK_INIT, board_setup_ppc, HOOK_PRIO_INIT_I2C + 2);
 
-void board_hibernate_late(void) {
-
+void board_hibernate_late(void)
+{
 	int i;
 
 	const uint32_t hibernate_pins[][2] = {
 		/* Turn off LEDs before going to hibernate */
-		{GPIO_BAT_LED_BLUE_L, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_BAT_LED_ORANGE_L, GPIO_INPUT | GPIO_PULL_UP},
+		{ GPIO_BAT_LED_BLUE_L, GPIO_INPUT | GPIO_PULL_UP },
+		{ GPIO_BAT_LED_ORANGE_L, GPIO_INPUT | GPIO_PULL_UP },
 	};
 
 	for (i = 0; i < ARRAY_SIZE(hibernate_pins); ++i)
@@ -528,7 +521,6 @@ void board_overcurrent_event(int port, int is_overcurrented)
 	gpio_set_level(GPIO_USB_C_OC, !is_overcurrented);
 }
 
-
 int ppc_get_alert_status(int port)
 {
 	if (port == 0)
diff --git a/board/bobba/board.h b/board/bobba/board.h
index a1fc900084..2a1be082e8 100644
--- a/board/bobba/board.h
+++ b/board/bobba/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,7 @@
 #define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD
 
 /* I2C bus configuraiton */
-#define I2C_PORT_ACCEL	I2C_PORT_SENSOR
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
 
 /* EC console commands  */
 #define CONFIG_CMD_ACCEL_INFO
@@ -40,10 +40,10 @@
 #define CONFIG_USB_PD_RESET_MIN_BATT_SOC 2
 
 /* Sensors */
-#define CONFIG_ACCEL_KX022	/* Lid accel */
-#define CONFIG_ACCELGYRO_BMI160	/* Base accel main source*/
-#define CONFIG_ACCELGYRO_ICM426XX	/* Base accel second source*/
-#define CONFIG_SYNC		/* Camera VSYNC */
+#define CONFIG_ACCEL_KX022 /* Lid accel */
+#define CONFIG_ACCELGYRO_BMI160 /* Base accel main source*/
+#define CONFIG_ACCELGYRO_ICM426XX /* Base accel second source*/
+#define CONFIG_SYNC /* Camera VSYNC */
 
 #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
 /* Sensors without hardware FIFO are in forced mode */
@@ -55,9 +55,7 @@
 #define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 
-
-#define CONFIG_SYNC_INT_EVENT	\
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
+#define CONFIG_SYNC_INT_EVENT TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
 
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_UPDATE
@@ -88,6 +86,13 @@
 /* SYV682 isn't connected to CC, so TCPC must provide VCONN */
 #define CONFIG_USBC_PPC_SYV682X_NO_CC
 
+/*
+ * SMP battery sleep mode time is 5 second.
+ * Change max sleep time from once/min to once/4sec to prevent
+ * battery entering sleeping mode. See b/226259582.
+ */
+#define CHARGE_MAX_SLEEP_USEC (4 * SECOND)
+
 #ifndef __ASSEMBLER__
 
 /* support factory keyboard test */
@@ -97,10 +102,10 @@
 #include "registers.h"
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_AMB,		/* ADC0 */
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC1 */
-	ADC_VBUS_C0,			/* ADC9 */
-	ADC_VBUS_C1,			/* ADC4 */
+	ADC_TEMP_SENSOR_AMB, /* ADC0 */
+	ADC_TEMP_SENSOR_CHARGER, /* ADC1 */
+	ADC_VBUS_C0, /* ADC9 */
+	ADC_VBUS_C1, /* ADC4 */
 	ADC_CH_COUNT
 };
 
@@ -111,19 +116,10 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_COUNT };
 
 /* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	VSYNC,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, VSYNC, SENSOR_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
diff --git a/board/bobba/build.mk b/board/bobba/build.mk
index 3d04b75731..998a65a3de 100644
--- a/board/bobba/build.mk
+++ b/board/bobba/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/bobba/ec.tasklist b/board/bobba/ec.tasklist
index d98db145e7..977b8b01be 100644
--- a/board/bobba/ec.tasklist
+++ b/board/bobba/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/bobba/gpio.inc b/board/bobba/gpio.inc
index edb76d05f6..f57ea6bf12 100644
--- a/board/bobba/gpio.inc
+++ b/board/bobba/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/bobba/led.c b/board/bobba/led.c
index d247ad0128..54227ed107 100644
--- a/board/bobba/led.c
+++ b/board/bobba/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,8 +10,8 @@
 #include "led_common.h"
 #include "led_onoff_states.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
 __override const int led_charge_lvl_1;
 
@@ -19,18 +19,24 @@ __override const int led_charge_lvl_2 = 100;
 
 /* Bobba: Note there is only LED for charge / power */
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,  2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
 const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
diff --git a/board/boldar/battery.c b/board/boldar/battery.c
index 48f7fcda84..2b2a9f4842 100644
--- a/board/boldar/battery.c
+++ b/board/boldar/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/boldar/board.c b/board/boldar/board.c
index 69546a4ea2..19b8f44020 100644
--- a/board/boldar/board.c
+++ b/board/boldar/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -47,7 +47,7 @@
 
 #include "gpio_list.h" /* Must come after other header files. */
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 /* Keyboard scan setting */
 __override struct keyboard_scan_config keyscan_config = {
@@ -86,7 +86,7 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
@@ -111,8 +111,8 @@ const struct fan_t fans[FAN_CH_COUNT] = {
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CPU \
-	{ \
+#define THERMAL_CPU              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
@@ -133,8 +133,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_INDUCTOR \
-	{ \
+#define THERMAL_INDUCTOR         \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
@@ -281,24 +281,33 @@ static const struct tcpc_config_t tcpc_config_p1_usb3 = {
  * virtual_usb_mux_driver so the AP gets notified of mux changes and updates
  * the TCSS configuration on state changes.
  */
-static const struct usb_mux usbc1_usb3_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	.next_mux = NULL,
+static const struct usb_mux_chain usbc1_usb3_db_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
+	.next = NULL,
 };
 
-static const struct usb_mux mux_config_p1_usb3_active = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-	.next_mux = &usbc1_usb3_db_retimer,
+static const struct usb_mux_chain mux_config_p1_usb3_active = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+	.next = &usbc1_usb3_db_retimer,
 };
 
-static const struct usb_mux mux_config_p1_usb3_passive = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+static const struct usb_mux_chain mux_config_p1_usb3_passive = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
 
 /******************************************************************************/
@@ -313,8 +322,7 @@ static void ps8815_reset(void)
 	int val;
 
 	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 0);
-	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS,
-			   PS8815_PWR_H_RST_H_DELAY_MS));
+	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS));
 	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 1);
 	msleep(PS8815_FW_INIT_DELAY_MS);
 
@@ -325,16 +333,16 @@ static void ps8815_reset(void)
 
 	CPRINTS("%s: patching ps8815 registers", __func__);
 
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
+	if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) ==
+	    EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f was %02x", val);
 
-	if (i2c_write8(I2C_PORT_USB_C1,
-		       PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) == EC_SUCCESS)
+	if (i2c_write8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f,
+		       0x31) == EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f set to 0x31");
 
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
+	if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) ==
+	    EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f now %02x", val);
 }
 
@@ -346,8 +354,9 @@ void board_reset_pd_mcu(void)
 	/* Daughterboard specific reset for port 1 */
 	if (usb_db == DB_USB3_ACTIVE) {
 		ps8815_reset();
-		usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED |
-						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+		usb_mux_hpd_update(USBC_PORT_C1,
+				   USB_PD_MUX_HPD_LVL_DEASSERTED |
+					   USB_PD_MUX_HPD_IRQ_DEASSERTED);
 	}
 }
 
@@ -509,33 +518,43 @@ BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
 
 /******************************************************************************/
 /* USBC mux configuration - Tiger Lake includes internal mux */
-struct usb_mux usbc0_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+struct usb_mux_chain usbc0_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
-struct usb_mux usbc1_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+struct usb_mux_chain usbc1_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
 
-struct usb_mux usb_muxes[] = {
+struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.next_mux = &usbc0_tcss_usb_mux,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_1_MIX,
-		.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_1_MIX,
+			.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc0_tcss_usb_mux,
 	},
 	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.next_mux = &usbc1_tcss_usb_mux,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_1_MIX,
-		.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_1_MIX,
+			.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc1_tcss_usb_mux,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
diff --git a/board/boldar/board.h b/board/boldar/board.h
index 12409a5435..f2a76dab82 100644
--- a/board/boldar/board.h
+++ b/board/boldar/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,7 +25,7 @@
 
 #define CONFIG_POWER_BUTTON
 
-#define CONFIG_HOSTCMD_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST
+#define CONFIG_HOST_INTERFACE_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST
 
 #undef CONFIG_UART_TX_BUF_SIZE
 #define CONFIG_UART_TX_BUF_SIZE 4096
@@ -51,19 +51,18 @@
 
 /* TCS3400 ALS/RGB */
 #define CONFIG_ALS
-#define ALS_COUNT		1
+#define ALS_COUNT 1
 #define CONFIG_ALS_TCS3400
 #define CONFIG_ALS_TCS3400_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS)
 
 /* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
-	(BIT(LID_ACCEL) | BIT(CLEAR_ALS))
+#define CONFIG_ACCEL_FORCE_MODE_MASK (BIT(LID_ACCEL) | BIT(CLEAR_ALS))
 
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE		BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID		LID_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
 
 /* USB Type C and USB PD defines */
 /*
@@ -73,36 +72,36 @@
  */
 #define CONFIG_USB_PID 0x503E
 
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
 
 /* TODO: b/144165680 - measure and check these values on Volteer */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
 
 /*
  * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
  * cables only support up to 60W.
  */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Enabling Thunderbolt-compatible mode */
 #define CONFIG_USB_PD_TBT_COMPAT_MODE
 
 /* Enabling USB4 mode */
 #define CONFIG_USB_PD_USB4
-#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR	0x37
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x40
+#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x37
+#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x40
 
 /* USB Type A Features */
-#define USB_PORT_COUNT			1
+#define USB_PORT_COUNT 1
 #define CONFIG_USB_PORT_POWER_DUMB
 
 /* USBC PPC*/
-#define CONFIG_USBC_PPC_SN5S330		/* USBC port C0 */
-#define CONFIG_USBC_PPC_SYV682X		/* USBC port C1 */
+#define CONFIG_USBC_PPC_SN5S330 /* USBC port C0 */
+#define CONFIG_USBC_PPC_SYV682X /* USBC port C1 */
 
 /* BC 1.2 */
 
@@ -111,8 +110,8 @@
 /* Fan features */
 
 /* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 
 /*
  * Macros for GPIO signals used in common code that don't match the
@@ -120,45 +119,44 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_DSW_PWROK		GPIO_EC_PCH_DSW_PWROK
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_LID_OPEN GPIO_EC_LID_OPEN
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
 
 /* I2C Bus Configuration */
 #define CONFIG_I2C
-#define I2C_PORT_ACCEL		I2C_PORT_SENSOR
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_1_MIX	NPCX_I2C_PORT3_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT3_0
+#define I2C_PORT_POWER NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+
+#define I2C_PORT_BATTERY I2C_PORT_POWER
+#define I2C_PORT_CHARGER I2C_PORT_EEPROM
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 #define CONFIG_I2C_CONTROLLER
 
-
 #ifndef __ASSEMBLER__
 
 #include "gpio_signal.h"
@@ -189,11 +187,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 void board_reset_pd_mcu(void);
 
diff --git a/board/boldar/build.mk b/board/boldar/build.mk
index 838d6a16ce..c994631759 100644
--- a/board/boldar/build.mk
+++ b/board/boldar/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/boldar/ec.tasklist b/board/boldar/ec.tasklist
index 3e20d8ae39..c29125d517 100644
--- a/board/boldar/ec.tasklist
+++ b/board/boldar/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/boldar/gpio.inc b/board/boldar/gpio.inc
index 4f55b5c503..f06541ebbb 100644
--- a/board/boldar/gpio.inc
+++ b/board/boldar/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,7 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
diff --git a/board/boldar/led.c b/board/boldar/led.c
index 6ee71bbe19..d2425d13b6 100644
--- a/board/boldar/led.c
+++ b/board/boldar/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,16 +19,16 @@ const enum ec_led_id supported_led_ids[] = {
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 struct pwm_led_color_map led_color_map[] = {
-				/* Red, Green, Blue */
-	[EC_LED_COLOR_RED] =    {  100,   0,     0 },
-	[EC_LED_COLOR_GREEN] =  {    0, 100,     0 },
-	[EC_LED_COLOR_BLUE] =   {    0,   0,   100 },
+	/* Red, Green, Blue */
+	[EC_LED_COLOR_RED] = { 100, 0, 0 },
+	[EC_LED_COLOR_GREEN] = { 0, 100, 0 },
+	[EC_LED_COLOR_BLUE] = { 0, 0, 100 },
 	/* The green LED seems to be brighter than the others, so turn down
 	 * green from its natural level for these secondary colors.
 	 */
-	[EC_LED_COLOR_YELLOW] = {  100,  70,     0 },
-	[EC_LED_COLOR_WHITE] =  {  100,  70,   100 },
-	[EC_LED_COLOR_AMBER] =  {  100,  20,     0 },
+	[EC_LED_COLOR_YELLOW] = { 100, 70, 0 },
+	[EC_LED_COLOR_WHITE] = { 100, 70, 100 },
+	[EC_LED_COLOR_AMBER] = { 100, 20, 0 },
 };
 
 struct pwm_led pwm_leds[] = {
diff --git a/board/boldar/sensors.c b/board/boldar/sensors.c
index 534065cde3..0670223f13 100644
--- a/board/boldar/sensors.c
+++ b/board/boldar/sensors.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -85,17 +85,13 @@ static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
 };
 
 /* Rotation matrix for the lid accelerometer */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+				       { FLOAT_TO_FP(-1), 0, 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
diff --git a/board/boten/battery.c b/board/boten/battery.c
index 0f4c8ffeb9..c4b4f9261d 100644
--- a/board/boten/battery.c
+++ b/board/boten/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/boten/board.c b/board/boten/board.c
index 76ee055fe4..c47b9e46f0 100644
--- a/board/boten/board.c
+++ b/board/boten/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -40,7 +40,7 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
 #define INT_RECHECK_US 5000
 
 /* C0 interrupt line shared by BC 1.2 and charger */
@@ -84,7 +84,6 @@ static void usb_c0_interrupt(enum gpio_signal s)
 
 	/* Check the line again in 5ms */
 	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-
 }
 
 static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
@@ -114,8 +113,7 @@ DECLARE_DEFERRED(pendetect_deferred);
 void pen_detect_interrupt(enum gpio_signal s)
 {
 	/* Trigger deferred notification of pen detect change */
-	hook_call_deferred(&pendetect_deferred_data,
-			500 * MSEC);
+	hook_call_deferred(&pendetect_deferred_data, 500 * MSEC);
 }
 
 void board_hibernate(void)
@@ -147,27 +145,21 @@ __override void board_pulse_entering_rw(void)
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH0
-	},
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH2
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH3
-	},
+	[ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH0 },
+	[ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH2 },
+	[ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH3 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
@@ -203,12 +195,15 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 };
 
 /* USB Muxes */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+			},
 	},
 };
 
@@ -276,7 +271,6 @@ int board_is_sourcing_vbus(int port)
 
 	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
 	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
-
 }
 
 int board_set_active_charge_port(int port)
@@ -288,8 +282,7 @@ int board_set_active_charge_port(int port)
 
 	/* Disable all ports. */
 	if (port == CHARGE_PORT_NONE) {
-		tcpc_write(0, TCPC_REG_COMMAND,
-				TCPC_REG_COMMAND_SNK_CTRL_LOW);
+		tcpc_write(0, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
 		raa489000_enable_asgate(0, false);
 		return EC_SUCCESS;
 	}
@@ -302,8 +295,7 @@ int board_set_active_charge_port(int port)
 
 	/* Enable requested charge port. */
 	if (raa489000_enable_asgate(port, true) ||
-	    tcpc_write(0, TCPC_REG_COMMAND,
-		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
+	    tcpc_write(0, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
 		CPRINTUSB("p%d: sink path enable failed.", port);
 		return EC_ERROR_UNKNOWN;
 	}
@@ -345,17 +337,13 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrices to rotate accelerometers into the standard reference. */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, FLOAT_TO_FP(1), 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
 
 /* Sensor Data */
 static struct stprivate_data g_lis2dwl_data;
@@ -459,7 +447,7 @@ void board_init(void)
 		gmr_tablet_switch_disable();
 		/* Base accel is not stuffed, don't allow line to float */
 		gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L,
-				GPIO_INPUT | GPIO_PULL_DOWN);
+			       GPIO_INPUT | GPIO_PULL_DOWN);
 
 		/* only clamshell sku todo */
 		gpio_set_flags(GPIO_PEN_DET_ODL, GPIO_INPUT | GPIO_PULL_DOWN);
@@ -488,14 +476,14 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
 /* Thermistors */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
diff --git a/board/boten/board.h b/board/boten/board.h
index a78296e997..ec5d25ff9f 100644
--- a/board/boten/board.h
+++ b/board/boten/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,9 +24,12 @@
 /* Charger */
 #define CONFIG_CHARGE_RAMP_HW
 #define CONFIG_CHARGER_RAA489000
+#define PD_MAX_VOLTAGE_MV 20000
 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 #define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */
+#define CONFIG_OCPC_DEF_RBATT_MOHMS               \
+	22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \
+	    */
 #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
 #define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
 
@@ -40,8 +43,8 @@
 #define CONFIG_PWM
 
 /* Sensors */
-#define CONFIG_ACCEL_LIS2DWL		/* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM	/* Base accel */
+#define CONFIG_ACCEL_LIS2DWL /* Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
 #define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 /* Sensors without hardware FIFO are in forced mode */
@@ -109,26 +112,17 @@ enum pwm_channel {
 };
 
 /* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
 /* ADC channels */
 enum adc_channel {
-	ADC_VSNS_PP3300_A,     /* ADC0 */
-	ADC_TEMP_SENSOR_1,     /* ADC2 */
-	ADC_TEMP_SENSOR_2,     /* ADC3 */
+	ADC_VSNS_PP3300_A, /* ADC0 */
+	ADC_TEMP_SENSOR_1, /* ADC2 */
+	ADC_TEMP_SENSOR_2, /* ADC3 */
 	ADC_CH_COUNT
 };
 
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_COUNT
-};
+enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
diff --git a/board/boten/build.mk b/board/boten/build.mk
index 806168ea0d..9b862c7624 100644
--- a/board/boten/build.mk
+++ b/board/boten/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/boten/cbi_ssfc.c b/board/boten/cbi_ssfc.c
index c4b859f133..81f3ee0dad 100644
--- a/board/boten/cbi_ssfc.c
+++ b/board/boten/cbi_ssfc.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
 
 enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
 {
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
 }
 
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
 {
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
 }
diff --git a/board/boten/cbi_ssfc.h b/board/boten/cbi_ssfc.h
index 935049b6ae..bf8853a43a 100644
--- a/board/boten/cbi_ssfc.h
+++ b/board/boten/cbi_ssfc.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -56,5 +56,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
  */
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
 
-
 #endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/boten/ec.tasklist b/board/boten/ec.tasklist
index be1f92aff2..e610e8ad33 100644
--- a/board/boten/ec.tasklist
+++ b/board/boten/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/boten/gpio.inc b/board/boten/gpio.inc
index 4e8290c277..4c9890441d 100644
--- a/board/boten/gpio.inc
+++ b/board/boten/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/boten/led.c b/board/boten/led.c
index 93675966b3..ca2f7c9399 100644
--- a/board/boten/led.c
+++ b/board/boten/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,41 +11,46 @@
 #include "gpio.h"
 #include "pwm.h"
 
-#define LED_OFF_LVL	0
-#define LED_ON_LVL	1
+#define LED_OFF_LVL 0
+#define LED_ON_LVL 1
 
 __override const int led_charge_lvl_1 = 5;
 
 __override const int led_charge_lvl_2 = 97;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED,   LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,   1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
 
 __override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]            = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]    = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-					 {LED_OFF,         0.5 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-					{LED_OFF,         0.5 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF,            LED_INDEFINITE} },
-};
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 3 * LED_ONE_SEC },
+					       { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    3 * LED_ONE_SEC },
+						  { LED_OFF,
+						    0.5 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
diff --git a/board/boten/usb_pd_policy.c b/board/boten/usb_pd_policy.c
index 65ee678263..74167850ee 100644
--- a/board/boten/usb_pd_policy.c
+++ b/board/boten/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,8 +13,8 @@
 #include "driver/tcpm/tcpci.h"
 #include "usb_pd.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
diff --git a/board/brask/board.c b/board/brask/board.c
index 7b22e37e29..bd9d1d7998 100644
--- a/board/brask/board.c
+++ b/board/brask/board.c
@@ -1,11 +1,11 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 #include <stdbool.h>
 
 #include "adc.h"
-#include "assert.h"
+#include "builtin/assert.h"
 #include "button.h"
 #include "charge_manager.h"
 #include "charge_state_v2.h"
@@ -27,8 +27,8 @@
 #include "fw_config.h"
 
 /* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 static void power_monitor(void);
 DECLARE_DEFERRED(power_monitor);
@@ -140,21 +140,21 @@ static int32_t base_5v_power_z1;
  */
 
 /* PP5000_S5 loads */
-#define PWR_S5_BASE_LOAD  (5*1431)
-#define PWR_S5_FRONT_HIGH (5*1737)
-#define PWR_S5_FRONT_LOW  (5*1055)
-#define PWR_S5_REAR_HIGH  (5*1737)
-#define PWR_S5_REAR_LOW   (5*1055)
-#define PWR_S5_HDMI       (5*580)
-#define PWR_S5_MAX        (5*10000)
-#define FRONT_DELTA       (PWR_S5_FRONT_HIGH - PWR_S5_FRONT_LOW)
-#define REAR_DELTA        (PWR_S5_REAR_HIGH - PWR_S5_REAR_LOW)
+#define PWR_S5_BASE_LOAD (5 * 1431)
+#define PWR_S5_FRONT_HIGH (5 * 1737)
+#define PWR_S5_FRONT_LOW (5 * 1055)
+#define PWR_S5_REAR_HIGH (5 * 1737)
+#define PWR_S5_REAR_LOW (5 * 1055)
+#define PWR_S5_HDMI (5 * 580)
+#define PWR_S5_MAX (5 * 10000)
+#define FRONT_DELTA (PWR_S5_FRONT_HIGH - PWR_S5_FRONT_LOW)
+#define REAR_DELTA (PWR_S5_REAR_HIGH - PWR_S5_REAR_LOW)
 
 /* PP5000_Z1 loads */
-#define PWR_Z1_BASE_LOAD   (5*5)
-#define PWR_Z1_C_HIGH      (5*3600)
-#define PWR_Z1_C_LOW       (5*2000)
-#define PWR_Z1_MAX         (5*9000)
+#define PWR_Z1_BASE_LOAD (5 * 5)
+#define PWR_Z1_C_HIGH (5 * 3600)
+#define PWR_Z1_C_LOW (5 * 2000)
+#define PWR_Z1_MAX (5 * 9000)
 /*
  * Update the 5V power usage, assuming no throttling,
  * and invoke the power monitoring.
@@ -228,7 +228,7 @@ static void port_ocp_interrupt(enum gpio_signal signal)
  * only do that if the system is off since it might still brown out.
  */
 
-#define ADP_DEBOUNCE_MS		1000  /* Debounce time for BJ plug/unplug */
+#define ADP_DEBOUNCE_MS 1000 /* Debounce time for BJ plug/unplug */
 /* Debounced connection state of the barrel jack */
 static int8_t adp_connected = -1;
 static void adp_connect_deferred(void)
@@ -328,26 +328,26 @@ void board_overcurrent_event(int port, int is_overcurrented)
  *
  *  All measurements are in milliwatts.
  */
-#define THROT_TYPE_A_FRONT  BIT(0)
-#define THROT_TYPE_A_REAR   BIT(1)
-#define THROT_TYPE_C0       BIT(2)
-#define THROT_TYPE_C1       BIT(3)
-#define THROT_TYPE_C2       BIT(4)
-#define THROT_PROCHOT       BIT(5)
+#define THROT_TYPE_A_FRONT BIT(0)
+#define THROT_TYPE_A_REAR BIT(1)
+#define THROT_TYPE_C0 BIT(2)
+#define THROT_TYPE_C1 BIT(3)
+#define THROT_TYPE_C2 BIT(4)
+#define THROT_PROCHOT BIT(5)
 
 /*
  * Power gain if front USB A ports are limited.
  */
-#define POWER_GAIN_TYPE_A	3200
+#define POWER_GAIN_TYPE_A 3200
 /*
  * Power gain if Type C port is limited.
  */
-#define POWER_GAIN_TYPE_C	8800
+#define POWER_GAIN_TYPE_C 8800
 /*
  * Power is averaged over 10 ms, with a reading every 2 ms.
  */
-#define POWER_DELAY_MS		2
-#define POWER_READINGS		(10/POWER_DELAY_MS)
+#define POWER_DELAY_MS 2
+#define POWER_READINGS (10 / POWER_DELAY_MS)
 
 static void power_monitor(void)
 {
@@ -363,8 +363,7 @@ static void power_monitor(void)
 	 * If CPU is off or suspended, no need to throttle
 	 * or restrict power.
 	 */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF |
-			     CHIPSET_STATE_SUSPEND)) {
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF | CHIPSET_STATE_SUSPEND)) {
 		/*
 		 * Slow down monitoring, assume no throttling required.
 		 */
@@ -392,7 +391,7 @@ static void power_monitor(void)
 			 */
 			power = (adc_read_channel(ADC_VBUS) *
 				 adc_read_channel(ADC_PPVAR_IMON)) /
-				 1000;
+				1000;
 			/* Init power table */
 			if (history[0] == 0) {
 				for (i = 0; i < POWER_READINGS; i++)
@@ -419,8 +418,7 @@ static void power_monitor(void)
 			 * For barrel-jack supplies, the rating can be
 			 * exceeded briefly, so use the average.
 			 */
-			if (charge_manager_get_supplier() ==
-			    CHARGE_SUPPLIER_PD)
+			if (charge_manager_get_supplier() == CHARGE_SUPPLIER_PD)
 				power = max;
 			else
 				power = total / POWER_READINGS;
@@ -551,24 +549,27 @@ static void power_monitor(void)
 		gpio_set_level(GPIO_EC_PROCHOT_ODL, prochot);
 	}
 	if (diff & THROT_TYPE_C0) {
-		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C0)
-			? TYPEC_RP_1A5 : TYPEC_RP_3A0;
+		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C0) ?
+						TYPEC_RP_1A5 :
+						TYPEC_RP_3A0;
 
 		ppc_set_vbus_source_current_limit(0, rp);
 		tcpm_select_rp_value(0, rp);
 		pd_update_contract(0);
 	}
 	if (diff & THROT_TYPE_C1) {
-		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C1)
-			? TYPEC_RP_1A5 : TYPEC_RP_3A0;
+		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C1) ?
+						TYPEC_RP_1A5 :
+						TYPEC_RP_3A0;
 
 		ppc_set_vbus_source_current_limit(1, rp);
 		tcpm_select_rp_value(1, rp);
 		pd_update_contract(1);
 	}
 	if (diff & THROT_TYPE_C2) {
-		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C2)
-			? TYPEC_RP_1A5 : TYPEC_RP_3A0;
+		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C2) ?
+						TYPEC_RP_1A5 :
+						TYPEC_RP_3A0;
 
 		ppc_set_vbus_source_current_limit(2, rp);
 		tcpm_select_rp_value(2, rp);
diff --git a/board/brask/board.h b/board/brask/board.h
index 1599749a07..dde8b85412 100644
--- a/board/brask/board.h
+++ b/board/brask/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,11 +21,11 @@
 /* HDMI CEC */
 #define CONFIG_CEC
 #define CEC_GPIO_OUT GPIO_HDMI_CEC_OUT
-#define CEC_GPIO_IN  GPIO_HDMI_CEC_IN
+#define CEC_GPIO_IN GPIO_HDMI_CEC_IN
 #define CEC_GPIO_PULL_UP GPIO_HDMI_CEC_PULL_UP
 
 /* USB Type A Features */
-#define USB_PORT_COUNT			4
+#define USB_PORT_COUNT 4
 #define CONFIG_USB_PORT_POWER_DUMB
 
 /* USB Type C and USB PD defines */
@@ -33,7 +33,7 @@
 
 #define CONFIG_IO_EXPANDER
 #define CONFIG_IO_EXPANDER_NCT38XX
-#define CONFIG_IO_EXPANDER_PORT_COUNT		2
+#define CONFIG_IO_EXPANDER_PORT_COUNT 2
 
 #define CONFIG_USB_PD_PPC
 #define CONFIG_USB_PD_TCPM_RT1715
@@ -46,18 +46,18 @@
 #define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_5_50
 
 /* TODO: b/177608416 - measure and check these values on brya */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
 
 /* The design should support up to 100W. */
 /* TODO(b/197702356): Set the max PD to 60W now and change it
  * to 100W after we verify it.
  */
-#define PD_OPERATING_POWER_MW	CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
-#define PD_MAX_POWER_MW		100000
-#define PD_MAX_CURRENT_MA	5000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
+#define PD_MAX_POWER_MW 100000
+#define PD_MAX_CURRENT_MA 5000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /*
  * Macros for GPIO signals used in common code that don't match the
@@ -65,64 +65,65 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_PACKET_MODE_EN		GPIO_EC_GSC_PACKET_MODE
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SYS_SLP_S0IX_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_TEMP_SENSOR_POWER		GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
 
 /*
  * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
  * signal.
  */
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_SEQ_EC_ALL_SYS_PG
-#define GPIO_PG_EC_DSW_PWROK		GPIO_SEQ_EC_DSW_PWROK
-#define GPIO_PG_EC_RSMRST_ODL		GPIO_SEQ_EC_RSMRST_ODL
-#define GPIO_POWER_BUTTON_L		GPIO_GSC_EC_PWR_BTN_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_ODL
-#define GPIO_RECOVERY_L			GPIO_EC_RECOVERY_BTN_OD
-#define GPIO_RECOVERY_L_2		GPIO_GSC_EC_RECOVERY_BTN_OD
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
+#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_OD
+#define GPIO_RECOVERY_L_2 GPIO_GSC_EC_RECOVERY_BTN_OD
 
 /* I2C Bus Configuration */
 
-#define I2C_PORT_DP_REDRIVER		NPCX_I2C_PORT0_0
+#define I2C_PORT_DP_REDRIVER NPCX_I2C_PORT0_0
 
-#define I2C_PORT_USB_C0_C2_TCPC		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1_TCPC		NPCX_I2C_PORT4_1
+#define I2C_PORT_USB_C0_C2_TCPC NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1
 
-#define I2C_PORT_USB_C0_C2_PPC		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_PPC		NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C0_C2_PPC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1
 
-#define I2C_PORT_USB_C0_C2_BC12		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_BC12		NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C0_C2_BC12 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1
 
-#define I2C_PORT_USB_C0_C2_MUX		NPCX_I2C_PORT3_0
-#define I2C_PORT_USB_C1_MUX		NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C0_C2_MUX NPCX_I2C_PORT3_0
+#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1
 
-#define I2C_PORT_QI			NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM			NPCX_I2C_PORT7_0
-#define I2C_PORT_MP2964			NPCX_I2C_PORT7_0
+#define I2C_PORT_QI NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0
 
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 
-#define I2C_ADDR_MP2964_FLAGS	0x20
+#define I2C_ADDR_MP2964_FLAGS 0x20
 
-#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR	0x58
-#define USBC_PORT_C2_BB_RETIMER_I2C_ADDR	0x59
+#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x58
+#define USBC_PORT_C2_BB_RETIMER_I2C_ADDR 0x59
 
 /* Enabling Thunderbolt-compatible mode */
 #define CONFIG_USB_PD_TBT_COMPAT_MODE
 
 /* Enabling USB4 mode */
 #define CONFIG_USB_PD_USB4
+#define CONFIG_USB_PD_DATA_RESET_MSG
 
 /* Retimer */
 #define CONFIG_USBC_RETIMER_FW_UPDATE
@@ -140,7 +141,7 @@
  * TODO(b/197478860): Enable the fan control. We need
  * to check the sensor value and adjust the fan speed.
  */
- #define CONFIG_FANS			FAN_CH_COUNT
+#define CONFIG_FANS FAN_CH_COUNT
 
 /* Include math_util for bitmask_uint64 used in pd_timers */
 #define CONFIG_MATH_UTIL
@@ -153,7 +154,7 @@
 
 #ifndef __ASSEMBLER__
 
-#include "gpio_signal.h"	/* needed by registers.h */
+#include "gpio_signal.h" /* needed by registers.h */
 #include "registers.h"
 #include "usbc_config.h"
 
@@ -171,7 +172,7 @@ enum adc_channel {
 	ADC_TEMP_SENSOR_3_WIFI,
 	ADC_TEMP_SENSOR_4_DIMM,
 	ADC_VBUS,
-	ADC_PPVAR_IMON,              /* ADC3 */
+	ADC_PPVAR_IMON, /* ADC3 */
 	ADC_CH_COUNT
 };
 
@@ -183,28 +184,18 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum ioex_port {
-	IOEX_C0_NCT38XX = 0,
-	IOEX_C2_NCT38XX,
-	IOEX_PORT_COUNT
-};
+enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_C2_NCT38XX, IOEX_PORT_COUNT };
 
 enum pwm_channel {
-	PWM_CH_LED_GREEN,		/* PWM0 */
-	PWM_CH_FAN,                     /* PWM5 */
-	PWM_CH_LED_RED,                 /* PWM2 */
+	PWM_CH_LED_GREEN, /* PWM0 */
+	PWM_CH_FAN, /* PWM5 */
+	PWM_CH_LED_RED, /* PWM2 */
 	PWM_CH_COUNT
 };
 
-enum fan_channel {
-	FAN_CH_0 = 0,
-	FAN_CH_COUNT
-};
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT };
 
-enum mft_channel {
-	MFT_CH_0 = 0,
-	MFT_CH_COUNT
-};
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT };
 
 extern void adp_connect_interrupt(enum gpio_signal signal);
 
diff --git a/board/brask/build.mk b/board/brask/build.mk
index f92c283725..f180fcb8ef 100644
--- a/board/brask/build.mk
+++ b/board/brask/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/brask/ec.tasklist b/board/brask/ec.tasklist
index a366e05682..3572543743 100644
--- a/board/brask/ec.tasklist
+++ b/board/brask/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/brask/fans.c b/board/brask/fans.c
index f2a70636d0..6828438a10 100644
--- a/board/brask/fans.c
+++ b/board/brask/fans.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,7 +25,7 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 static const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
diff --git a/board/brask/fw_config.c b/board/brask/fw_config.c
index a5857ef48f..3ee71e6a0f 100644
--- a/board/brask/fw_config.c
+++ b/board/brask/fw_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,7 +10,7 @@
 #include "cros_board_info.h"
 #include "fw_config.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 static union brask_cbi_fw_config fw_config;
 BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
diff --git a/board/brask/fw_config.h b/board/brask/fw_config.h
index 5ddb3b02a1..95d81f1e05 100644
--- a/board/brask/fw_config.h
+++ b/board/brask/fw_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,15 +13,9 @@
  *
  * Source of truth is the project/brask/brask/config.star configuration file.
  */
-enum ec_cfg_audio_type {
-	DB_AUDIO_UNKNOWN = 0,
-	DB_NAU88L25B_I2S = 1
-};
+enum ec_cfg_audio_type { DB_AUDIO_UNKNOWN = 0, DB_NAU88L25B_I2S = 1 };
 
-enum ec_cfg_bj_power {
-	BJ_135W = 0,
-	BJ_230W = 1
-};
+enum ec_cfg_bj_power { BJ_135W = 0, BJ_230W = 1 };
 
 union brask_cbi_fw_config {
 	struct {
diff --git a/board/brask/gpio.inc b/board/brask/gpio.inc
index 5bd13beaee..5fa07523f6 100644
--- a/board/brask/gpio.inc
+++ b/board/brask/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/brask/i2c.c b/board/brask/i2c.c
index 190f4f019e..3af3e43d75 100644
--- a/board/brask/i2c.c
+++ b/board/brask/i2c.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/brask/led.c b/board/brask/led.c
index 68dffb67a7..0a57994ca0 100644
--- a/board/brask/led.c
+++ b/board/brask/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,16 +19,16 @@
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
 
 /*
  * Due to the CSME-Lite processing, upon startup the CPU transitions through
  * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so
  * delay turning off the LED during suspend/shutdown.
  */
-#define LED_CPU_DELAY_MS	(2000 * MSEC)
+#define LED_CPU_DELAY_MS (2000 * MSEC)
 
-const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 enum led_color {
@@ -84,9 +84,9 @@ static int set_color(enum ec_led_id id, enum led_color color, int duty)
 	}
 }
 
-#define LED_PULSE_US		(2 * SECOND)
+#define LED_PULSE_US (2 * SECOND)
 /* 40 msec for nice and smooth transition. */
-#define LED_PULSE_TICK_US	(40 * MSEC)
+#define LED_PULSE_TICK_US (40 * MSEC)
 
 /*
  * When pulsing is enabled, brightness is incremented by <duty_inc> every
@@ -206,7 +206,7 @@ void show_critical_error(void)
 		set_color(EC_LED_ID_POWER_LED, LED_RED, 100);
 }
 
-static int command_led(int argc, char **argv)
+static int command_led(int argc, const char **argv)
 {
 	enum ec_led_id id = EC_LED_ID_POWER_LED;
 
@@ -231,8 +231,7 @@ static int command_led(int argc, char **argv)
 	}
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(led, command_led,
-			"[debug|red|green|off|alert|crit]",
+DECLARE_CONSOLE_COMMAND(led, command_led, "[debug|red|green|off|alert|crit]",
 			"Turn on/off LED.");
 
 void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
@@ -250,10 +249,10 @@ int led_set_brightness(enum ec_led_id id, const uint8_t *brightness)
 	else
 		return set_color(id, LED_OFF, 0);
 }
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-				int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
-  /* Blink alert if insufficient power per system_can_boot_ap(). */
+	/* Blink alert if insufficient power per system_can_boot_ap(). */
 	int insufficient_power =
 		(charge_ma * charge_mv) <
 		(CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON * 1000);
diff --git a/board/brask/pwm.c b/board/brask/pwm.c
index 5ad905f861..1804cb5586 100644
--- a/board/brask/pwm.c
+++ b/board/brask/pwm.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,21 +11,16 @@
 #include "pwm_chip.h"
 
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED_GREEN] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 2000
-	},
-	[PWM_CH_FAN] = {
-		.channel = 5,
-		.flags = PWM_CONFIG_OPEN_DRAIN | PWM_CONFIG_DSLEEP,
-		.freq = 1000
-	},
-	[PWM_CH_LED_RED] = {
-		.channel = 2,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 2000
-	},
+	[PWM_CH_LED_GREEN] = { .channel = 0,
+			       .flags = PWM_CONFIG_ACTIVE_LOW |
+					PWM_CONFIG_DSLEEP,
+			       .freq = 2000 },
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN | PWM_CONFIG_DSLEEP,
+			 .freq = 1000 },
+	[PWM_CH_LED_RED] = { .channel = 2,
+			     .flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+			     .freq = 2000 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
diff --git a/board/brask/sensors.c b/board/brask/sensors.c
index 2803dd1025..b5caaaf717 100644
--- a/board/brask/sensors.c
+++ b/board/brask/sensors.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -58,30 +58,22 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* Temperature sensor configuration */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1_CPU] = {
-		.name = "CPU",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_1_CPU
-	},
-	[TEMP_SENSOR_2_CPU_VR] = {
-		.name = "CPU VR",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_2_CPU_VR
-	},
-	[TEMP_SENSOR_3_WIFI] = {
-		.name = "WIFI",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_3_WIFI
-	},
-	[TEMP_SENSOR_4_DIMM] = {
-		.name = "DIMM",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_4_DIMM
-	},
+	[TEMP_SENSOR_1_CPU] = { .name = "CPU",
+				.type = TEMP_SENSOR_TYPE_BOARD,
+				.read = get_temp_3v3_30k9_47k_4050b,
+				.idx = ADC_TEMP_SENSOR_1_CPU },
+	[TEMP_SENSOR_2_CPU_VR] = { .name = "CPU VR",
+				   .type = TEMP_SENSOR_TYPE_BOARD,
+				   .read = get_temp_3v3_30k9_47k_4050b,
+				   .idx = ADC_TEMP_SENSOR_2_CPU_VR },
+	[TEMP_SENSOR_3_WIFI] = { .name = "WIFI",
+				 .type = TEMP_SENSOR_TYPE_BOARD,
+				 .read = get_temp_3v3_30k9_47k_4050b,
+				 .idx = ADC_TEMP_SENSOR_3_WIFI },
+	[TEMP_SENSOR_4_DIMM] = { .name = "DIMM",
+				 .type = TEMP_SENSOR_TYPE_BOARD,
+				 .read = get_temp_3v3_30k9_47k_4050b,
+				 .idx = ADC_TEMP_SENSOR_4_DIMM },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -95,8 +87,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CPU \
-	{ \
+#define THERMAL_CPU              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
diff --git a/board/brask/usbc_config.c b/board/brask/usbc_config.c
index caae5437a9..5cec791afc 100644
--- a/board/brask/usbc_config.c
+++ b/board/brask/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -32,8 +32,8 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 /* USBC TCPC configuration */
 const struct tcpc_config_t tcpc_config[] = {
@@ -91,20 +91,29 @@ BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
 /* USBC mux configuration - Alder Lake includes internal mux */
-static const struct usb_mux usbc0_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+static const struct usb_mux_chain usbc0_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
-static const struct usb_mux usbc1_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+static const struct usb_mux_chain usbc1_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
-static const struct usb_mux usbc2_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C2,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+static const struct usb_mux_chain usbc2_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C2,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
 
 struct kb800x_control_t kb800x_control[] = {
@@ -124,29 +133,35 @@ struct kb800x_control_t kb800x_control[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(kb800x_control) == USBC_PORT_COUNT);
 
-const struct usb_mux usb_muxes[] = {
+const struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C0_C2_MUX,
-		.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc0_tcss_usb_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C0_C2_MUX,
+			.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc0_tcss_usb_mux,
 	},
 	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &kb800x_usb_mux_driver,
-		.i2c_port = I2C_PORT_USB_C1_MUX,
-		.i2c_addr_flags = KB800X_I2C_ADDR0_FLAGS,
-		.next_mux = &usbc1_tcss_usb_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &kb800x_usb_mux_driver,
+			.i2c_port = I2C_PORT_USB_C1_MUX,
+			.i2c_addr_flags = KB800X_I2C_ADDR0_FLAGS,
+		},
+		.next = &usbc1_tcss_usb_mux,
 	},
 	[USBC_PORT_C2] = {
-		.usb_port = USBC_PORT_C2,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C0_C2_MUX,
-		.i2c_addr_flags = USBC_PORT_C2_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc2_tcss_usb_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C2,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C0_C2_MUX,
+			.i2c_addr_flags = USBC_PORT_C2_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc2_tcss_usb_mux,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
diff --git a/board/brask/usbc_config.h b/board/brask/usbc_config.h
index 7319bcb5e2..0d4f62651a 100644
--- a/board/brask/usbc_config.h
+++ b/board/brask/usbc_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,7 +8,7 @@
 #ifndef __CROS_EC_USBC_CONFIG_H
 #define __CROS_EC_USBC_CONFIG_H
 
-#define CONFIG_USB_PD_PORT_MAX_COUNT	3
+#define CONFIG_USB_PD_PORT_MAX_COUNT 3
 
 enum usbc_port {
 	USBC_PORT_C0 = 0,
diff --git a/board/brya/battery.c b/board/brya/battery.c
index 91faab57a3..71b46082d8 100644
--- a/board/brya/battery.c
+++ b/board/brya/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -102,10 +102,7 @@ enum battery_present battery_hw_present(void)
 {
 	enum gpio_signal batt_pres;
 
-	if (get_board_id() == 1)
-		batt_pres = GPIO_ID_1_EC_BATT_PRES_ODL;
-	else
-		batt_pres = GPIO_EC_BATT_PRES_ODL;
+	batt_pres = GPIO_EC_BATT_PRES_ODL;
 
 	/* The GPIO is low when the battery is physically present */
 	return gpio_get_level(batt_pres) ? BP_NO : BP_YES;
diff --git a/board/brya/board.c b/board/brya/board.c
index c9246c197b..50b13e8743 100644
--- a/board/brya/board.c
+++ b/board/brya/board.c
@@ -1,22 +1,20 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include "battery.h"
 #include "button.h"
+#include "cbi.h"
 #include "charge_ramp.h"
 #include "charger.h"
 #include "common.h"
-#include "compile_time_macros.h"
 #include "console.h"
-#include "gpio.h"
-#include "gpio_signal.h"
-#include "hooks.h"
-#include "driver/accel_lis2dw12.h"
 #include "driver/accelgyro_lsm6dso.h"
+#include "driver/accel_lis2dw12.h"
 #include "driver/als_tcs3400.h"
 #include "fw_config.h"
+#include "gpio.h"
+#include "gpio_signal.h"
 #include "hooks.h"
 #include "lid_switch.h"
 #include "power_button.h"
@@ -30,8 +28,8 @@
 #include "gpio_list.h" /* Must come after other header files. */
 
 /* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 __override void board_cbi_init(void)
 {
@@ -43,9 +41,7 @@ static void board_chipset_resume(void)
 {
 	/* Allow keyboard backlight to be enabled */
 
-	if (get_board_id() == 1)
-		gpio_set_level(GPIO_ID_1_EC_KB_BL_EN, 1);
-	else
+	if (IS_ENABLED(CONFIG_PWM_KBLIGHT))
 		gpio_set_level(GPIO_EC_KB_BL_EN_L, 0);
 }
 DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
@@ -55,54 +51,7 @@ static void board_chipset_suspend(void)
 {
 	/* Turn off the keyboard backlight if it's on. */
 
-	if (get_board_id() == 1)
-		gpio_set_level(GPIO_ID_1_EC_KB_BL_EN, 0);
-	else
+	if (IS_ENABLED(CONFIG_PWM_KBLIGHT))
 		gpio_set_level(GPIO_EC_KB_BL_EN_L, 1);
 }
 DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-/*
- * Explicitly apply the board ID 1 *gpio.inc settings to pins that
- * were reassigned on current boards.
- */
-
-static void set_board_id_1_gpios(void)
-{
-	if (get_board_id() != 1)
-		return;
-
-	gpio_set_flags(GPIO_ID_1_EC_KB_BL_EN, GPIO_OUT_LOW);
-}
-DECLARE_HOOK(HOOK_INIT, set_board_id_1_gpios, HOOK_PRIO_FIRST);
-
-/*
- * Reclaim GPIO pins on board ID 1 that are used as ADC inputs on
- * current boards. ALT function group MODULE_ADC pins are set in
- * HOOK_PRIO_INIT_ADC and can be reclaimed right after the hook runs.
- */
-
-static void board_id_1_reclaim_adc(void)
-{
-	if (get_board_id() != 1)
-		return;
-
-	/*
-	 * GPIO_ID_1_USB_C0_C2_TCPC_RST_ODL is on GPIO34
-	 *
-	 * The TCPC has already been reset by board_tcpc_init() executed
-	 * from HOOK_PRIO_INIT_CHIPSET. Later, the pin gets set to ADC6
-	 * in HOOK_PRIO_INIT_ADC, so we simply need to set the pin back
-	 * to GPIO34.
-	 */
-	gpio_set_flags(GPIO_ID_1_USB_C0_C2_TCPC_RST_ODL, GPIO_ODR_HIGH);
-	gpio_set_alternate_function(GPIO_PORT_3, BIT(4), GPIO_ALT_FUNC_NONE);
-
-	/*
-	 * The pin gets set to ADC7 in HOOK_PRIO_INIT_ADC, so we simply
-	 * need to set it back to GPIOE1.
-	 */
-	gpio_set_flags(GPIO_ID_1_EC_BATT_PRES_ODL, GPIO_INPUT);
-	gpio_set_alternate_function(GPIO_PORT_E, BIT(1), GPIO_ALT_FUNC_NONE);
-}
-DECLARE_HOOK(HOOK_INIT, board_id_1_reclaim_adc, HOOK_PRIO_INIT_ADC + 1);
diff --git a/board/brya/board.h b/board/brya/board.h
index 8188ee68d9..8b0aceb93b 100644
--- a/board/brya/board.h
+++ b/board/brya/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -39,7 +39,7 @@
 #define CONFIG_LED_PWM_LOW_BATT_COLOR EC_LED_COLOR_AMBER
 
 /* Sensors */
-#define CONFIG_ACCELGYRO_LSM6DSO	/* Base accel */
+#define CONFIG_ACCELGYRO_LSM6DSO /* Base accel */
 #define CONFIG_ACCEL_LSM6DSO_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 
@@ -63,19 +63,18 @@
 /* Lid accel */
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE	BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID	LID_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
 #define CONFIG_ACCEL_LIS2DWL
 #define CONFIG_ACCEL_LIS2DW12_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
 
-
 /* Sensor console commands */
 #define CONFIG_CMD_ACCELS
 #define CONFIG_CMD_ACCEL_INFO
 
 /* USB Type A Features */
-#define USB_PORT_COUNT			1
+#define USB_PORT_COUNT 1
 #define CONFIG_USB_PORT_POWER_DUMB
 
 /* USB Type C and USB PD defines */
@@ -83,7 +82,7 @@
 
 #define CONFIG_IO_EXPANDER
 #define CONFIG_IO_EXPANDER_NCT38XX
-#define CONFIG_IO_EXPANDER_PORT_COUNT		4
+#define CONFIG_IO_EXPANDER_PORT_COUNT 2
 
 #define CONFIG_USB_PD_FRS_PPC
 
@@ -101,17 +100,17 @@
 #define CONFIG_USBC_PPC_NX20P3483
 
 /* TODO: b/177608416 - measure and check these values on brya */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
 
 /*
  * Passive USB-C cables only support up to 60W.
  */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /*
  * Macros for GPIO signals used in common code that don't match the
@@ -119,75 +118,74 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT		GPIO_EC_EN_EDP_BL
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_GSC_PACKET_MODE
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SYS_SLP_S0IX_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_TEMP_SENSOR_POWER		GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
 
 /*
  * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
  * signal.
  */
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_SEQ_EC_ALL_SYS_PG
-#define GPIO_PG_EC_DSW_PWROK		GPIO_SEQ_EC_DSW_PWROK
-#define GPIO_PG_EC_RSMRST_ODL		GPIO_SEQ_EC_RSMRST_ODL
-#define GPIO_POWER_BUTTON_L		GPIO_GSC_EC_PWR_BTN_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_ODL
-
-#define GPIO_ID_1_EC_KB_BL_EN		GPIO_EC_BATT_PRES_ODL
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
 
 /* System has back-lit keyboard */
 #define CONFIG_PWM_KBLIGHT
 
 /* I2C Bus Configuration */
 
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
 
-#define I2C_PORT_USB_C0_C2_TCPC	NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1_TCPC	NPCX_I2C_PORT4_1
+#define I2C_PORT_USB_C0_C2_TCPC NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1
 
-#define I2C_PORT_USB_C0_C2_PPC	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_PPC	NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C0_C2_PPC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1
 
-#define I2C_PORT_USB_C0_C2_BC12	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_BC12	NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C0_C2_BC12 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1
 
-#define I2C_PORT_USB_C0_C2_MUX	NPCX_I2C_PORT3_0
-#define I2C_PORT_USB_C1_MUX	NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C0_C2_MUX NPCX_I2C_PORT3_0
+#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1
 
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT5_0
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT7_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-#define I2C_PORT_MP2964		NPCX_I2C_PORT7_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0
 
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 
-#define I2C_ADDR_MP2964_FLAGS	0x20
+#define I2C_ADDR_MP2964_FLAGS 0x20
 
 /*
  * see b/174768555#comment22
  */
-#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR	0x56
-#define USBC_PORT_C2_BB_RETIMER_I2C_ADDR	0x57
+#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x56
+#define USBC_PORT_C2_BB_RETIMER_I2C_ADDR 0x57
 
 /* Enabling Thunderbolt-compatible mode */
 #define CONFIG_USB_PD_TBT_COMPAT_MODE
 
 /* Enabling USB4 mode */
 #define CONFIG_USB_PD_USB4
+#define CONFIG_USB_PD_DATA_RESET_MSG
 
 /* Retimer */
 #define CONFIG_USBC_RETIMER_FW_UPDATE
@@ -198,15 +196,15 @@
 #define CONFIG_TEMP_SENSOR_POWER
 #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
 
-#define CONFIG_FANS			FAN_CH_COUNT
+#define CONFIG_FANS FAN_CH_COUNT
 
 /* Charger defines */
 #define CONFIG_CHARGER_BQ25720
 #define CONFIG_CHARGER_BQ25720_VSYS_TH2_CUSTOM
-#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV	70
+#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV 70
 #define CONFIG_CHARGE_RAMP_SW
-#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10
 #define CONFIG_CHARGER_BQ25710_PSYS_SENSING
 
 /*
@@ -217,7 +215,7 @@
 
 #ifndef __ASSEMBLER__
 
-#include "gpio_signal.h"	/* needed by registers.h */
+#include "gpio_signal.h" /* needed by registers.h */
 #include "registers.h"
 #include "usbc_config.h"
 
@@ -246,39 +244,23 @@ enum sensor_id {
 	SENSOR_COUNT
 };
 
-enum ioex_port {
-	IOEX_C0_NCT38XX = 0,
-	IOEX_C2_NCT38XX,
-	IOEX_ID_1_C0_NCT38XX,
-	IOEX_ID_1_C2_NCT38XX,
-	IOEX_PORT_COUNT
-};
+enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_C2_NCT38XX, IOEX_PORT_COUNT };
 
-enum battery_type {
-	BATTERY_POWER_TECH,
-	BATTERY_LGC011,
-	BATTERY_TYPE_COUNT
-};
+enum battery_type { BATTERY_POWER_TECH, BATTERY_LGC011, BATTERY_TYPE_COUNT };
 
 enum pwm_channel {
-	PWM_CH_LED2 = 0,		/* PWM0 (white charger) */
-	PWM_CH_LED3,			/* PWM1 (orange on DB) */
-	PWM_CH_LED1,			/* PWM2 (orange charger) */
-	PWM_CH_KBLIGHT,			/* PWM3 */
-	PWM_CH_FAN,			/* PWM5 */
-	PWM_CH_LED4,			/* PWM7 (white on DB) */
+	PWM_CH_LED2 = 0, /* PWM0 (white charger) */
+	PWM_CH_LED3, /* PWM1 (orange on DB) */
+	PWM_CH_LED1, /* PWM2 (orange charger) */
+	PWM_CH_KBLIGHT, /* PWM3 */
+	PWM_CH_FAN, /* PWM5 */
+	PWM_CH_LED4, /* PWM7 (white on DB) */
 	PWM_CH_COUNT
 };
 
-enum fan_channel {
-	FAN_CH_0 = 0,
-	FAN_CH_COUNT
-};
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT };
 
-enum mft_channel {
-	MFT_CH_0 = 0,
-	MFT_CH_COUNT
-};
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT };
 
 #endif /* !__ASSEMBLER__ */
 
diff --git a/board/brya/build.mk b/board/brya/build.mk
index 674c17c1df..bc3e3cd31e 100644
--- a/board/brya/build.mk
+++ b/board/brya/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -22,5 +22,4 @@ board-y+=keyboard.o
 board-y+=led.o
 board-y+=pwm.o
 board-y+=sensors.o
-board-y+=tune_mp2964.o
 board-y+=usbc_config.o
diff --git a/board/brya/charger.c b/board/brya/charger.c
index 476ce97df2..a4fa209246 120000..100644
--- a/board/brya/charger.c
+++ b/board/brya/charger.c
@@ -1 +1,90 @@
-../../baseboard/brya/charger_bq25720.c
\ No newline at end of file
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+
+#include "charge_manager.h"
+#include "charge_state_v2.h"
+#include "charger.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/charger/bq25710.h"
+#include "usbc_ppc.h"
+#include "usb_pd.h"
+#include "util.h"
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+#ifndef CONFIG_ZEPHYR
+/* Charger Chip Configuration */
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = BQ25710_SMBUS_ADDR1_FLAGS,
+		.drv = &bq25710_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CHARGER_NUM);
+#endif
+
+int board_set_active_charge_port(int port)
+{
+	int is_valid_port = board_is_usb_pd_port_present(port);
+	int i;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTSUSB("Disabling all charger ports");
+
+		/* Disable all ports. */
+		for (i = 0; i < ppc_cnt; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (ppc_vbus_sink_enable(i, 0))
+				CPRINTSUSB("Disabling C%d as sink failed.", i);
+		}
+
+		return EC_SUCCESS;
+	} else if (!is_valid_port) {
+		return EC_ERROR_INVAL;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (ppc_is_sourcing_vbus(port)) {
+		CPRINTFUSB("Skip enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTSUSB("New charge port: C%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < ppc_cnt; i++) {
+		if (i == port)
+			continue;
+
+		if (ppc_vbus_sink_enable(i, 0))
+			CPRINTSUSB("C%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTSUSB("C%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+__overridable void board_set_charge_limit(int port, int supplier, int charge_ma,
+					  int max_ma, int charge_mv)
+{
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+}
diff --git a/board/brya/ec.tasklist b/board/brya/ec.tasklist
index 260f6561d9..3b94575196 100644
--- a/board/brya/ec.tasklist
+++ b/board/brya/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/brya/fans.c b/board/brya/fans.c
index 021f0de8e2..eb9bb8a809 100644
--- a/board/brya/fans.c
+++ b/board/brya/fans.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,7 +25,7 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 static const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
diff --git a/board/brya/fw_config.c b/board/brya/fw_config.c
index 414908a1f1..3a4c91acf1 100644
--- a/board/brya/fw_config.c
+++ b/board/brya/fw_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,7 +10,7 @@
 #include "cros_board_info.h"
 #include "fw_config.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 static union brya_cbi_fw_config fw_config;
 BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
@@ -33,21 +33,6 @@ void board_init_fw_config(void)
 		CPRINTS("CBI: Read FW_CONFIG failed, using board defaults");
 		fw_config = fw_config_defaults;
 	}
-
-	if (get_board_id() == 0) {
-		/*
-		 * Early boards have a zero'd out FW_CONFIG, so replace
-		 * it with a sensible default value. If DB_USB_ABSENT2
-		 * was used as an alternate encoding of DB_USB_ABSENT to
-		 * avoid the zero check, then fix it.
-		 */
-		if (fw_config.raw_value == 0) {
-			CPRINTS("CBI: FW_CONFIG is zero, using board defaults");
-			fw_config = fw_config_defaults;
-		} else if (fw_config.usb_db == DB_USB_ABSENT2) {
-			fw_config.usb_db = DB_USB_ABSENT;
-		}
-	}
 }
 
 union brya_cbi_fw_config get_fw_config(void)
diff --git a/board/brya/fw_config.h b/board/brya/fw_config.h
index 6e4eb3ef58..fea6c9a8da 100644
--- a/board/brya/fw_config.h
+++ b/board/brya/fw_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,12 +27,12 @@ enum ec_cfg_keyboard_backlight_type {
 
 union brya_cbi_fw_config {
 	struct {
-		enum ec_cfg_usb_db_type			usb_db : 4;
-		uint32_t				sd_db : 2;
-		uint32_t				lte_db : 1;
-		enum ec_cfg_keyboard_backlight_type	kb_bl : 1;
-		uint32_t				audio : 3;
-		uint32_t				reserved_1 : 21;
+		enum ec_cfg_usb_db_type usb_db : 4;
+		uint32_t sd_db : 2;
+		uint32_t lte_db : 1;
+		enum ec_cfg_keyboard_backlight_type kb_bl : 1;
+		uint32_t audio : 3;
+		uint32_t reserved_1 : 21;
 	};
 	uint32_t raw_value;
 };
diff --git a/board/brya/gpio.inc b/board/brya/gpio.inc
index e88d72eba8..d68dfc4dd0 100644
--- a/board/brya/gpio.inc
+++ b/board/brya/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -28,38 +28,7 @@
  */
 GPIO(EC_KSO_02_INV,               PIN(1, 7), GPIO_OUT_LOW)
 
-/*
- * GPIOE1 is an ALT function ADC INPUT on board ID 2 and a GPIO INPUT on
- * board ID 1. This declaration gives us a signal name to use on board
- * ID 1.
- */
-GPIO(ID_1_EC_BATT_PRES_ODL,       PIN(E, 1), GPIO_INPUT)
-
-/*
- * GPIO34 is an INPUT on board ID 2 and ODR_LOW on board ID 1.
- *
- * Since this pin is pulled up to 3.3V through a 30.9K ohm resistor on
- * board ID 2, we will leak about 0.3mW until the pin is put in ALT mode
- * when MODULE_ADC configuration runs. Initializing the pin to ODR_LOW
- * gives us full control on both boards.
- */
-GPIO(ID_1_USB_C0_C2_TCPC_RST_ODL, PIN(3, 4), GPIO_ODR_LOW)
-
-/* Board ID 1 IO expander configuration */
-
-IOEX(ID_1_USB_C0_RT_RST_ODL, EXPIN(IOEX_ID_1_C0_NCT38XX, 0, 2), GPIO_ODR_LOW)
-/* GPIO03_P1 to PU */
-IOEX(ID_1_USB_C0_FRS_EN,     EXPIN(IOEX_ID_1_C0_NCT38XX, 0, 4), GPIO_LOW)
-IOEX(ID_1_USB_C0_OC_ODL,     EXPIN(IOEX_ID_1_C0_NCT38XX, 0, 6), GPIO_ODR_HIGH)
-/* GPIO07_P1 to PU */
-
-IOEX(ID_1_USB_C2_RT_RST_ODL, EXPIN(IOEX_ID_1_C2_NCT38XX, 0, 2), GPIO_ODR_LOW)
-/* GPIO03_P2 to PU */
-IOEX(ID_1_USB_C2_FRS_EN,     EXPIN(IOEX_ID_1_C2_NCT38XX, 0, 4), GPIO_LOW)
-IOEX(ID_1_USB_C1_OC_ODL,     EXPIN(IOEX_ID_1_C2_NCT38XX, 0, 6), GPIO_ODR_HIGH)
-IOEX(ID_1_USB_C2_OC_ODL,     EXPIN(IOEX_ID_1_C2_NCT38XX, 0, 7), GPIO_ODR_HIGH)
-
-/* Board ID 2 IO expander configuration */
+/* IO expander configuration */
 
 /* GPIO02_P2 to PU */
 /* GPIO03_P2 to PU */
diff --git a/board/brya/i2c.c b/board/brya/i2c.c
index 1e405f4216..feed4023d7 100644
--- a/board/brya/i2c.c
+++ b/board/brya/i2c.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,8 +9,6 @@
 #include "hooks.h"
 #include "i2c.h"
 
-#define BOARD_ID_FAST_PLUS_CAPABLE	2
-
 /* I2C port map configuration */
 const struct i2c_port_t i2c_ports[] = {
 	{
@@ -81,19 +79,3 @@ const struct i2c_port_t i2c_ports[] = {
 	},
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/*
- * I2C controllers are initialized in main.c. This sets the speed much
- * later, but before I2C peripherals are initialized.
- */
-static void set_board_legacy_i2c_speeds(void)
-{
-	if (get_board_id() >= BOARD_ID_FAST_PLUS_CAPABLE)
-		return;
-
-	ccprints("setting USB DB I2C buses to 400 kHz\n");
-
-	i2c_set_freq(I2C_PORT_USB_C1_TCPC, I2C_FREQ_400KHZ);
-	i2c_set_freq(I2C_PORT_USB_C1_PPC, I2C_FREQ_400KHZ);
-}
-DECLARE_HOOK(HOOK_INIT, set_board_legacy_i2c_speeds, HOOK_PRIO_INIT_I2C - 1);
diff --git a/board/brya/keyboard.c b/board/brya/keyboard.c
index a9f033130d..0ebe25dc90 100644
--- a/board/brya/keyboard.c
+++ b/board/brya/keyboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/brya/led.c b/board/brya/led.c
index 78c10e65b8..fec5a13311 100644
--- a/board/brya/led.c
+++ b/board/brya/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -30,13 +30,10 @@ const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
  * both LEDs being off. Cap at 50% to save power.
  */
 struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = {
-				/* Amber, White */
-	[EC_LED_COLOR_RED]    = {   0,   0 },
-	[EC_LED_COLOR_GREEN]  = {   0,   0 },
-	[EC_LED_COLOR_BLUE]   = {   0,   0 },
-	[EC_LED_COLOR_YELLOW] = {   0,   0 },
-	[EC_LED_COLOR_WHITE]  = {   0,  50 },
-	[EC_LED_COLOR_AMBER]  = {  50,   0 },
+	/* Amber, White */
+	[EC_LED_COLOR_RED] = { 0, 0 },	  [EC_LED_COLOR_GREEN] = { 0, 0 },
+	[EC_LED_COLOR_BLUE] = { 0, 0 },	  [EC_LED_COLOR_YELLOW] = { 0, 0 },
+	[EC_LED_COLOR_WHITE] = { 0, 50 }, [EC_LED_COLOR_AMBER] = { 50, 0 },
 };
 
 /* Two logical LEDs with amber and white channels. */
diff --git a/board/brya/pwm.c b/board/brya/pwm.c
index cb452c13ed..bb578968b7 100644
--- a/board/brya/pwm.c
+++ b/board/brya/pwm.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -39,8 +39,8 @@ const struct pwm_t pwm_channels[] = {
 	},
 	[PWM_CH_FAN] = {
 		.channel = 5,
-		.flags = PWM_CONFIG_OPEN_DRAIN | PWM_CONFIG_DSLEEP,
-		.freq = 1000
+		.flags = PWM_CONFIG_OPEN_DRAIN,
+		.freq = 25000,
 	},
 	[PWM_CH_LED4] = {
 		.channel = 7,
diff --git a/board/brya/sensors.c b/board/brya/sensors.c
index 51841b8599..8ab5b58d7e 100644
--- a/board/brya/sensors.c
+++ b/board/brya/sensors.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -55,18 +55,14 @@ static struct stprivate_data g_lis2dw12_data;
 static struct lsm6dso_data lsm6dso_data;
 
 /* TODO(b/184779333): calibrate the orientation matrix on later board stage */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					     { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
 /* TODO(b/184779743): verify orientation matrix */
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, FLOAT_TO_FP(-1), 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
 
 /* TCS3400 private data */
 static struct als_drv_data_t g_tcs3400_data = {
@@ -292,8 +288,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CPU \
-	{ \
+#define THERMAL_CPU              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(85), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(90), \
@@ -322,8 +318,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_AMBIENT \
-	{ \
+#define THERMAL_AMBIENT          \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(85), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(90), \
@@ -351,8 +347,8 @@ __maybe_unused static const struct ec_thermal_config thermal_ambient =
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CHARGER \
-	{ \
+#define THERMAL_CHARGER          \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(105), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(120), \
@@ -372,8 +368,8 @@ __maybe_unused static const struct ec_thermal_config thermal_charger =
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_WWAN \
-	{ \
+#define THERMAL_WWAN             \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(130), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(130), \
@@ -394,20 +390,3 @@ struct ec_thermal_config thermal_params[] = {
 	[TEMP_SENSOR_4_WWAN] = THERMAL_WWAN,
 };
 BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
-
-static void board_thermals_init(void)
-{
-	if (get_board_id() == 1) {
-		/*
-		 * Board ID 1 only has 3 sensors and the AMBIENT sensor
-		 * ADC pins have been reassigned, so we're down to 2
-		 * sensors that can easily be configured. So, alias the
-		 * AMBIENT sensor ADC channel to the unimplemented ADC
-		 * slots.
-		 */
-		adc_channels[ADC_TEMP_SENSOR_3_CHARGER].input_ch = NPCX_ADC_CH1;
-		adc_channels[ADC_TEMP_SENSOR_4_WWAN].input_ch = NPCX_ADC_CH1;
-	}
-}
-
-DECLARE_HOOK(HOOK_INIT, board_thermals_init, HOOK_PRIO_INIT_CHIPSET);
diff --git a/board/brya/tune_mp2964.c b/board/brya/tune_mp2964.c
deleted file mode 100644
index 198f06d8eb..0000000000
--- a/board/brya/tune_mp2964.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Tune the MP2964 IMVP9.1 parameters for brya */
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "hooks.h"
-#include "mp2964.h"
-
-const static struct mp2964_reg_val rail_a[] = {
-	{ MP2964_MFR_ALT_SET,     0xe081 },	/* ALERT_DELAY = 200ns */
-};
-const static struct mp2964_reg_val rail_b[] = {
-	{ MP2964_MFR_ALT_SET,     0xe081 },	/* ALERT_DELAY = 200ns */
-};
-
-static void mp2964_on_startup(void)
-{
-	static int chip_updated;
-	int status;
-
-	if (get_board_id() != 1)
-		return;
-
-	if (chip_updated)
-		return;
-
-	chip_updated = 1;
-
-	ccprintf("%s: attempting to tune PMIC\n", __func__);
-
-	status = mp2964_tune(rail_a, ARRAY_SIZE(rail_a),
-			     rail_b, ARRAY_SIZE(rail_b));
-	if (status != EC_SUCCESS)
-		ccprintf("%s: could not update all settings\n", __func__);
-}
-
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, mp2964_on_startup,
-	     HOOK_PRIO_FIRST);
diff --git a/board/brya/usbc_config.c b/board/brya/usbc_config.c
index eb72412423..0c9afc6943 100644
--- a/board/brya/usbc_config.c
+++ b/board/brya/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -36,17 +36,11 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 #ifdef CONFIG_ZEPHYR
-enum ioex_port {
-	IOEX_C0_NCT38XX = 0,
-	IOEX_C2_NCT38XX,
-	IOEX_ID_1_C0_NCT38XX,
-	IOEX_ID_1_C2_NCT38XX,
-	IOEX_PORT_COUNT
-};
+enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_C2_NCT38XX, IOEX_PORT_COUNT };
 #endif /* CONFIG_ZEPHYR */
 
 #ifndef CONFIG_ZEPHYR
@@ -86,7 +80,7 @@ const struct tcpc_config_t tcpc_config[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
 BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-#endif  /* !CONFIG_ZEPHYR */
+#endif /* !CONFIG_ZEPHYR */
 
 /******************************************************************************/
 /* USB-A charging control */
@@ -100,6 +94,7 @@ BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
 
 /******************************************************************************/
 
+#ifndef CONFIG_ZEPHYR
 /* USBC PPC configuration */
 struct ppc_config_t ppc_chips[] = {
 	[USBC_PORT_C0] = {
@@ -125,17 +120,22 @@ BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
 
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
-#ifndef CONFIG_ZEPHYR
 /* USBC mux configuration - Alder Lake includes internal mux */
-static const struct usb_mux usbc0_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+static const struct usb_mux_chain usbc0_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
-static const struct usb_mux usbc2_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C2,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+static const struct usb_mux_chain usbc2_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C2,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
 
 /*
@@ -143,35 +143,44 @@ static const struct usb_mux usbc2_tcss_usb_mux = {
  * to the virtual_usb_mux_driver so the AP gets notified of mux changes
  * and updates the TCSS configuration on state changes.
  */
-static const struct usb_mux usbc1_usb3_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+static const struct usb_mux_chain usbc1_usb3_db_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 };
 
-const struct usb_mux usb_muxes[] = {
+const struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C0_C2_MUX,
-		.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc0_tcss_usb_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C0_C2_MUX,
+			.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc0_tcss_usb_mux,
 	},
 	[USBC_PORT_C1] = {
-		/* PS8815 DB */
-		.usb_port = USBC_PORT_C1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc1_usb3_db_retimer,
+		.mux = &(const struct usb_mux) {
+			/* PS8815 DB */
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc1_usb3_db_retimer,
 	},
 	[USBC_PORT_C2] = {
-		.usb_port = USBC_PORT_C2,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C0_C2_MUX,
-		.i2c_addr_flags = USBC_PORT_C2_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc2_tcss_usb_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C2,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C0_C2_MUX,
+			.i2c_addr_flags = USBC_PORT_C2_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc2_tcss_usb_mux,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
@@ -215,18 +224,6 @@ struct ioexpander_config_t ioex_config[] = {
 		.drv = &nct38xx_ioexpander_drv,
 		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
 	},
-	[IOEX_ID_1_C0_NCT38XX] = {
-		.i2c_host_port = I2C_PORT_USB_C0_C2_TCPC,
-		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		.drv = &nct38xx_ioexpander_drv,
-		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
-	},
-	[IOEX_ID_1_C2_NCT38XX] = {
-		.i2c_host_port = I2C_PORT_USB_C0_C2_TCPC,
-		.i2c_addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS,
-		.drv = &nct38xx_ioexpander_drv,
-		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
-	},
 };
 BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT);
 #endif /* !CONFIG_ZEPHYR */
@@ -255,8 +252,8 @@ int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
 	}
 
 	if (voltage < BC12_MIN_VOLTAGE) {
-		CPRINTS("%s: port %d: vbus %d lower than %d", __func__,
-			port, voltage, BC12_MIN_VOLTAGE);
+		CPRINTS("%s: port %d: vbus %d lower than %d", __func__, port,
+			voltage, BC12_MIN_VOLTAGE);
 		return 1;
 	}
 
@@ -283,10 +280,7 @@ __override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
 	if (me->usb_port == USBC_PORT_C0) {
 /* TODO: explore how to handle board id in zephyr*/
 #ifndef CONFIG_ZEPHYR
-		if (get_board_id() == 1)
-			rst_signal = IOEX_ID_1_USB_C0_RT_RST_ODL;
-		else
-			rst_signal = IOEX_USB_C0_RT_RST_ODL;
+		rst_signal = IOEX_USB_C0_RT_RST_ODL;
 #else
 		/* On Zephyr use bb_controls generated from DTS */
 		rst_signal = bb_controls[me->usb_port].retimer_rst_gpio;
@@ -294,10 +288,7 @@ __override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
 	} else if (me->usb_port == USBC_PORT_C2) {
 /* TODO: explore how to handle board id in zephyr*/
 #ifndef CONFIG_ZEPHYR
-		if (get_board_id() == 1)
-			rst_signal = IOEX_ID_1_USB_C2_RT_RST_ODL;
-		else
-			rst_signal = IOEX_USB_C2_RT_RST_ODL;
+		rst_signal = IOEX_USB_C2_RT_RST_ODL;
 #else
 		/* On Zephyr use bb_controls generated from DTS */
 		rst_signal = bb_controls[me->usb_port].retimer_rst_gpio;
@@ -324,20 +315,6 @@ __override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
 		 * which powers I2C controller within retimer
 		 */
 		msleep(1);
-		if (get_board_id() == 1) {
-			int val;
-
-			/*
-			 * Check if we were able to deassert
-			 * reset. Board ID 1 uses a GPIO that is
-			 * uncontrollable when a debug accessory is
-			 * connected.
-			 */
-			if (ioex_get_level(rst_signal, &val) != EC_SUCCESS)
-				return EC_ERROR_UNKNOWN;
-			if (val != 1)
-				return EC_ERROR_NOT_POWERED;
-		}
 	} else {
 		ioex_set_level(rst_signal, 0);
 		msleep(1);
@@ -350,10 +327,7 @@ void board_reset_pd_mcu(void)
 	enum gpio_signal tcpc_rst;
 
 #ifndef CONFIG_ZEPHYR
-	if (get_board_id() == 1)
-		tcpc_rst = GPIO_ID_1_USB_C0_C2_TCPC_RST_ODL;
-	else
-		tcpc_rst = GPIO_USB_C0_C2_TCPC_RST_ODL;
+	tcpc_rst = GPIO_USB_C0_C2_TCPC_RST_ODL;
 #else
 	tcpc_rst = GPIO_UNIMPLEMENTED;
 #endif /* !CONFIG_ZEPHYR */
@@ -391,19 +365,14 @@ static void board_tcpc_init(void)
 	if (!system_jumped_late())
 		board_reset_pd_mcu();
 
-	/*
-	 * These IO expander pins are implemented using the
-	 * C0/C2 TCPC, so they must be set up after the TCPC has
-	 * been taken out of reset.
-	 */
+		/*
+		 * These IO expander pins are implemented using the
+		 * C0/C2 TCPC, so they must be set up after the TCPC has
+		 * been taken out of reset.
+		 */
 #ifndef CONFIG_ZEPHYR
-	if (get_board_id() == 1) {
-		ioex_init(IOEX_ID_1_C0_NCT38XX);
-		ioex_init(IOEX_ID_1_C2_NCT38XX);
-	} else {
-		ioex_init(IOEX_C0_NCT38XX);
-		ioex_init(IOEX_C2_NCT38XX);
-	}
+	ioex_init(IOEX_C0_NCT38XX);
+	ioex_init(IOEX_C2_NCT38XX);
 #else
 	gpio_reset_port(DEVICE_DT_GET(DT_NODELABEL(ioex_port1)));
 	gpio_reset_port(DEVICE_DT_GET(DT_NODELABEL(ioex_port2)));
diff --git a/board/brya/usbc_config.h b/board/brya/usbc_config.h
index 9e7652d9a0..bff89438d4 100644
--- a/board/brya/usbc_config.h
+++ b/board/brya/usbc_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,7 +9,7 @@
 #define __CROS_EC_USBC_CONFIG_H
 
 #ifndef CONFIG_ZEPHYR
-#define CONFIG_USB_PD_PORT_MAX_COUNT	3
+#define CONFIG_USB_PD_PORT_MAX_COUNT 3
 #endif
 
 enum usbc_port {
diff --git a/board/bugzzy/battery.c b/board/bugzzy/battery.c
index 23318890f3..2df4848d05 100644
--- a/board/bugzzy/battery.c
+++ b/board/bugzzy/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -85,7 +85,7 @@ const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SDI;
 int charger_profile_override(struct charge_state_data *curr)
 {
 	if ((chipset_in_state(CHIPSET_STATE_ON)) &&
-			(curr->requested_current > CHARGING_CURRENT_45C))
+	    (curr->requested_current > CHARGING_CURRENT_45C))
 		curr->requested_current = CHARGING_CURRENT_45C;
 
 	return 0;
@@ -115,7 +115,7 @@ static void reduce_input_voltage_when_full(void)
 	int port;
 
 	if (charge_get_percent() == 100 &&
-			chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
+	    chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
 		if (max_pd_voltage_mv != PD_VOLTAGE_WHEN_FULL) {
 			saved_input_voltage = max_pd_voltage_mv;
 			max_pd_voltage_mv = PD_VOLTAGE_WHEN_FULL;
@@ -131,5 +131,4 @@ static void reduce_input_voltage_when_full(void)
 			pd_set_external_voltage_limit(port, max_pd_voltage_mv);
 	}
 }
-DECLARE_HOOK(HOOK_SECOND, reduce_input_voltage_when_full,
-		HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_SECOND, reduce_input_voltage_when_full, HOOK_PRIO_DEFAULT);
diff --git a/board/bugzzy/board.c b/board/bugzzy/board.c
index 25fc04a20a..5a28fb2c25 100644
--- a/board/bugzzy/board.c
+++ b/board/bugzzy/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -44,8 +44,8 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 #define INT_RECHECK_US 5000
 
@@ -85,7 +85,6 @@ static void usb_c0_interrupt(enum gpio_signal s)
 
 	/* Check the line again in 5ms */
 	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-
 }
 
 /* C1 interrupt line shared by BC 1.2, TCPC, and charger */
@@ -120,7 +119,6 @@ static void sub_usb_c1_interrupt(enum gpio_signal s)
 
 	/* Check the line again in 5ms */
 	hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
-
 }
 
 static void sub_hdmi_hpd_interrupt(enum gpio_signal s)
@@ -181,22 +179,22 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* Thermistors */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Charger",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "Skin1",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_3},
-	[TEMP_SENSOR_4] = {.name = "Skin2",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_4},
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Charger",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "Skin1",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
+	[TEMP_SENSOR_4] = { .name = "Skin2",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_4 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -212,16 +210,17 @@ void board_init(void)
 
 	if (get_cbi_fw_config_db() == DB_1A_HDMI) {
 		/* Disable i2c on HDMI pins */
-		gpio_config_pin(MODULE_I2C,
-				GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL, 0);
-		gpio_config_pin(MODULE_I2C,
-				GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL, 0);
+		gpio_config_pin(MODULE_I2C, GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL,
+				0);
+		gpio_config_pin(MODULE_I2C, GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL,
+				0);
 
 		/* Set HDMI and sub-rail enables to output */
 		gpio_set_flags(GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL,
 			       chipset_in_state(CHIPSET_STATE_ON) ?
-						GPIO_ODR_LOW : GPIO_ODR_HIGH);
-		gpio_set_flags(GPIO_SUB_C1_INT_EN_RAILS_ODL,   GPIO_ODR_HIGH);
+				       GPIO_ODR_LOW :
+				       GPIO_ODR_HIGH);
+		gpio_set_flags(GPIO_SUB_C1_INT_EN_RAILS_ODL, GPIO_ODR_HIGH);
 
 		/* Select HDMI option */
 		gpio_set_level(GPIO_HDMI_SEL_L, 0);
@@ -230,8 +229,7 @@ void board_init(void)
 		gpio_enable_interrupt(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL);
 	} else {
 		/* Set SDA as an input */
-		gpio_set_flags(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL,
-			       GPIO_INPUT);
+		gpio_set_flags(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL, GPIO_INPUT);
 
 		/* Enable C1 interrupt and check if it needs processing */
 		gpio_enable_interrupt(GPIO_SUB_C1_INT_EN_RAILS_ODL);
@@ -300,10 +298,9 @@ __override void board_power_5v_enable(int enable)
 		gpio_set_level(GPIO_SUB_C1_INT_EN_RAILS_ODL, !enable);
 	} else {
 		if (isl923x_set_comparator_inversion(1, !!enable))
-			CPRINTS("Failed to %sable sub rails!", enable ?
-								"en" : "dis");
+			CPRINTS("Failed to %sable sub rails!",
+				enable ? "en" : "dis");
 	}
-
 }
 
 __override uint8_t board_get_usb_pd_port_count(void)
@@ -328,13 +325,11 @@ int board_is_sourcing_vbus(int port)
 
 	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
 	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
-
 }
 
 int board_set_active_charge_port(int port)
 {
-	int is_real_port = (port >= 0 &&
-			    port < board_get_usb_pd_port_count());
+	int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count());
 	int i;
 	int old_port;
 
@@ -398,8 +393,8 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
 
@@ -426,23 +421,17 @@ static struct mutex g_base_mutex;
 static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
 
 /* Matrices to rotate accelerometers into the standard reference. */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					     { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
 
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+					      { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
 
-static const mat33_fp_t base_standard_ref_lsm = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t base_standard_ref_lsm = { { FLOAT_TO_FP(1), 0, 0 },
+						  { 0, FLOAT_TO_FP(-1), 0 },
+						  { 0, 0, FLOAT_TO_FP(-1) } };
 
 struct motion_sensor_t ldm6dsm_base_accel = {
 	.name = "Base Accel",
@@ -481,8 +470,7 @@ struct motion_sensor_t ldm6dsm_base_gyro = {
 	.location = MOTIONSENSE_LOC_BASE,
 	.drv = &lsm6dsm_drv,
 	.mutex = &g_base_mutex,
-	.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-			MOTIONSENSE_TYPE_GYRO),
+	.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data, MOTIONSENSE_TYPE_GYRO),
 	.port = I2C_PORT_ACCEL,
 	.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
 	.default_range = 1000 | ROUND_UP_FLAG, /* dps */
@@ -601,9 +589,8 @@ void motion_interrupt(enum gpio_signal signal)
 		lsm6dsm_interrupt(signal);
 }
 
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
+__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+				       int *ki_div, int *kd, int *kd_div)
 {
 	*kp = 1;
 	*kp_div = 20;
@@ -671,44 +658,44 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 static int ps8743_tune_mux_c0(const struct usb_mux *me);
 static int ps8743_tune_mux_c1(const struct usb_mux *me);
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PS8743_I2C_ADDR0_FLAG,
-		.driver = &ps8743_usb_mux_driver,
-		.board_init = &ps8743_tune_mux_c0,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = PS8743_I2C_ADDR0_FLAG,
+				.driver = &ps8743_usb_mux_driver,
+				.board_init = &ps8743_tune_mux_c0,
+			},
 	},
 	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PS8743_I2C_ADDR0_FLAG,
-		.driver = &ps8743_usb_mux_driver,
-		.board_init = &ps8743_tune_mux_c1,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_SUB_USB_C1,
+				.i2c_addr_flags = PS8743_I2C_ADDR0_FLAG,
+				.driver = &ps8743_usb_mux_driver,
+				.board_init = &ps8743_tune_mux_c1,
+			},
 	}
 };
 /* USB Mux C0 : board_init of PS8743 */
 static int ps8743_tune_mux_c0(const struct usb_mux *me)
 {
-	ps8743_tune_usb_eq(me,
-			PS8743_USB_EQ_TX_3_6_DB,
-			PS8743_USB_EQ_RX_16_0_DB);
+	ps8743_tune_usb_eq(me, PS8743_USB_EQ_TX_3_6_DB,
+			   PS8743_USB_EQ_RX_16_0_DB);
 
 	return EC_SUCCESS;
 }
 /* USB Mux C1 : board_init of PS8743 */
 static int ps8743_tune_mux_c1(const struct usb_mux *me)
 {
-	ps8743_tune_usb_eq(me,
-			PS8743_USB_EQ_TX_3_6_DB,
-			PS8743_USB_EQ_RX_16_0_DB);
+	ps8743_tune_usb_eq(me, PS8743_USB_EQ_TX_3_6_DB,
+			   PS8743_USB_EQ_RX_16_0_DB);
 
-	ps8743_write(me,
-			PS8743_REG_USB_SWING,
-			PS8743_LFPS_SWG_TD);
-	ps8743_write(me,
-			PS8743_REG_DP_SETTING,
-			PS8743_DP_SWG_ADJ_P15P);
+	ps8743_write(me, PS8743_REG_USB_SWING, PS8743_LFPS_SWG_TD);
+	ps8743_write(me, PS8743_REG_DP_SETTING, PS8743_DP_SWG_ADJ_P15P);
 
 	return EC_SUCCESS;
 }
@@ -735,7 +722,7 @@ uint16_t tcpc_get_alert_status(void)
 	}
 
 	if (board_get_usb_pd_port_count() > 1 &&
-				!gpio_get_level(GPIO_SUB_C1_INT_EN_RAILS_ODL)) {
+	    !gpio_get_level(GPIO_SUB_C1_INT_EN_RAILS_ODL)) {
 		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
 			/* TCPCI spec Rev 1.0 says to ignore bits 14:12. */
 			if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0))
@@ -765,8 +752,8 @@ static const struct ec_response_keybd_config keybd1 = {
 	/* No function keys, no numeric keypad, has screenlock key */
 	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
 };
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	/*
 	 * Future boards should use fw_config if needed.
@@ -830,11 +817,11 @@ static void panel_power_change_deferred(void)
 		gpio_set_level(GPIO_EN_LCD_ENN, signal);
 	} else if (signal != 0) {
 		i2c_write8(I2C_PORT_LCD, I2C_ADDR_ISL98607_FLAGS,
-				ISL98607_REG_VBST_OUT, ISL98607_VBST_OUT_5P65);
+			   ISL98607_REG_VBST_OUT, ISL98607_VBST_OUT_5P65);
 		i2c_write8(I2C_PORT_LCD, I2C_ADDR_ISL98607_FLAGS,
-				ISL98607_REG_VN_OUT, ISL98607_VN_OUT_5P5);
+			   ISL98607_REG_VN_OUT, ISL98607_VN_OUT_5P5);
 		i2c_write8(I2C_PORT_LCD, I2C_ADDR_ISL98607_FLAGS,
-				ISL98607_REG_VP_OUT, ISL98607_VP_OUT_5P5);
+			   ISL98607_REG_VP_OUT, ISL98607_VP_OUT_5P5);
 	}
 	gpio_set_level(GPIO_TSP_TA, signal & extpower_is_present());
 }
@@ -878,9 +865,8 @@ static void lcd_reset_change_deferred(void)
 	if (signal == 0)
 		return;
 
-	i2c_write8(I2C_PORT_LCD, I2C_ADDR_ISL98607_FLAGS,
-			ISL98607_REG_ENABLE, ISL97607_VP_VN_VBST_DIS);
-
+	i2c_write8(I2C_PORT_LCD, I2C_ADDR_ISL98607_FLAGS, ISL98607_REG_ENABLE,
+		   ISL97607_VP_VN_VBST_DIS);
 }
 DECLARE_DEFERRED(lcd_reset_change_deferred);
 void lcd_reset_change_interrupt(enum gpio_signal signal)
@@ -927,8 +913,6 @@ void backlit_gpio_tick(void)
 
 	if (board_id >= 4 && signal == 1)
 		i2c_write16(I2C_PORT_LCD, I2C_ADDR_MP3372_FLAGS,
-				MP3372_REG_ISET_CHEN,
-				MP3372_ISET_15P3_CHEN_ALL);
-
+			    MP3372_REG_ISET_CHEN, MP3372_ISET_15P3_CHEN_ALL);
 }
 DECLARE_HOOK(HOOK_TICK, backlit_gpio_tick, HOOK_PRIO_DEFAULT);
diff --git a/board/bugzzy/board.h b/board/bugzzy/board.h
index 722375b34b..707314d02a 100644
--- a/board/bugzzy/board.h
+++ b/board/bugzzy/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -32,12 +32,15 @@
 
 /* Charger */
 #define CONFIG_CHARGER_RAA489000
+#define PD_MAX_VOLTAGE_MV 20000
 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 #define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */
+#define CONFIG_OCPC_DEF_RBATT_MOHMS               \
+	22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \
+	    */
 #define CONFIG_OCPC
 #define CONFIG_CHARGE_RAMP_HW
-#undef  CONFIG_CHARGER_SINGLE_CHIP
+#undef CONFIG_CHARGER_SINGLE_CHIP
 #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
 #define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
 #define CONFIG_BATTERY_CHECK_CHARGE_TEMP_LIMITS
@@ -60,9 +63,8 @@
 #define GPIO_BAT_LED_GREEN_L GPIO_LED_G_ODL
 #define GPIO_PWR_LED_BLUE_L GPIO_LED_B_ODL
 
-
 /* PWM */
-#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
+#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */
 
 /* Thermistors */
 #define CONFIG_TEMP_SENSOR
@@ -97,23 +99,23 @@
 #undef PD_POWER_SUPPLY_TURN_OFF_DELAY
 #undef CONFIG_USBC_VCONN_SWAP_DELAY_US
 /* 20% margin added for these timings */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	13080	/* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	16080	/* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 13080 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 16080 /* us */
 #undef CONFIG_USBC_VCONN_SWAP_DELAY_US
-#define CONFIG_USBC_VCONN_SWAP_DELAY_US		787	/* us */
+#define CONFIG_USBC_VCONN_SWAP_DELAY_US 787 /* us */
 
 /* I2C configuration */
-#define I2C_PORT_EEPROM     NPCX_I2C_PORT7_0
-#define I2C_PORT_BATTERY    NPCX_I2C_PORT5_0
-#define I2C_PORT_SENSOR     NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0     NPCX_I2C_PORT1_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
 #define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_MUX    I2C_PORT_USB_C0
-#define I2C_PORT_LCD	    NPCX_I2C_PORT3_0
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0
+#define I2C_PORT_LCD NPCX_I2C_PORT3_0
 /* TODO(b:147440290): Need to handle multiple charger ICs */
-#define I2C_PORT_CHARGER    I2C_PORT_USB_C0
+#define I2C_PORT_CHARGER I2C_PORT_USB_C0
 
-#define I2C_PORT_ACCEL      I2C_PORT_SENSOR
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
 
 #define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */
 #define I2C_ADDR_ISL98607_FLAGS 0x29
@@ -121,30 +123,30 @@
 
 /* ISL98607 registers and value */
 /* Enable VP / VN / VBST */
-#define ISL98607_REG_ENABLE	0x05
-#define ISL98607_VP_VN_VBST_EN	0x07
-#define ISL97607_VP_VN_VBST_DIS	0x00
+#define ISL98607_REG_ENABLE 0x05
+#define ISL98607_VP_VN_VBST_EN 0x07
+#define ISL97607_VP_VN_VBST_DIS 0x00
 
 /* VBST Voltage Adjustment */
-#define ISL98607_REG_VBST_OUT	0x06
-#define ISL98607_VBST_OUT_5P65	0x0a
+#define ISL98607_REG_VBST_OUT 0x06
+#define ISL98607_VBST_OUT_5P65 0x0a
 
 /* VN Voltage Adjustment */
-#define ISL98607_REG_VN_OUT	0x08
-#define ISL98607_VN_OUT_5P5	0x0a
+#define ISL98607_REG_VN_OUT 0x08
+#define ISL98607_VN_OUT_5P5 0x0a
 
 /* VP Voltage Adjustment */
-#define ISL98607_REG_VP_OUT	0x09
-#define ISL98607_VP_OUT_5P5	0x0a
+#define ISL98607_REG_VP_OUT 0x09
+#define ISL98607_VP_OUT_5P5 0x0a
 
 /* MP3372 registers and value */
 /* ISET & CHEN */
-#define MP3372_REG_ISET_CHEN		0x00
-#define MP3372_ISET_21P8_CHEN_ALL	0x70ff
-#define MP3372_ISET_19P4_CHEN_ALL	0x63ff
-#define MP3372_ISET_18P0_CHEN_ALL	0x5cff
-#define MP3372_ISET_15P8_CHEN_ALL	0x50ff
-#define MP3372_ISET_15P3_CHEN_ALL	0x4eff
+#define MP3372_REG_ISET_CHEN 0x00
+#define MP3372_ISET_21P8_CHEN_ALL 0x70ff
+#define MP3372_ISET_19P4_CHEN_ALL 0x63ff
+#define MP3372_ISET_18P0_CHEN_ALL 0x5cff
+#define MP3372_ISET_15P8_CHEN_ALL 0x50ff
+#define MP3372_ISET_15P3_CHEN_ALL 0x4eff
 /*
  * I2C pin names for baseboard
  *
@@ -158,18 +160,18 @@
 #define CONFIG_CMD_ACCELS
 #define CONFIG_CMD_ACCEL_INFO
 
-#define CONFIG_ACCELGYRO_BMI160		/* Base accel */
+#define CONFIG_ACCELGYRO_BMI160 /* Base accel */
 
 /* Lid operates in forced mode, base in interrupt mode */
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
 #define CONFIG_ACCEL_FIFO
-#define CONFIG_ACCEL_FIFO_SIZE 256	/* Must be a power of 2 */
+#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */
 #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
 
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 
-#define CONFIG_ACCELGYRO_LSM6DSM        /* Base accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
 #define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 
@@ -204,21 +206,16 @@ enum temp_sensor_id {
 };
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_1,     /* ADC0 */
-	ADC_TEMP_SENSOR_2,     /* ADC1 */
-	ADC_TEMP_SENSOR_3,     /* ADC5 */
-	ADC_TEMP_SENSOR_4,     /* ADC6 */
-	ADC_SUB_ANALOG,	       /* ADC2 */
-	ADC_VSNS_PP3300_A,     /* ADC9 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
+	ADC_TEMP_SENSOR_3, /* ADC5 */
+	ADC_TEMP_SENSOR_4, /* ADC6 */
+	ADC_SUB_ANALOG, /* ADC2 */
+	ADC_VSNS_PP3300_A, /* ADC9 */
 	ADC_CH_COUNT
 };
 
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
diff --git a/board/bugzzy/build.mk b/board/bugzzy/build.mk
index 815a285d83..5b37e085ef 100644
--- a/board/bugzzy/build.mk
+++ b/board/bugzzy/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/bugzzy/cbi_ssfc.c b/board/bugzzy/cbi_ssfc.c
index c4b859f133..81f3ee0dad 100644
--- a/board/bugzzy/cbi_ssfc.c
+++ b/board/bugzzy/cbi_ssfc.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
 
 enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
 {
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
 }
 
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
 {
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
 }
diff --git a/board/bugzzy/cbi_ssfc.h b/board/bugzzy/cbi_ssfc.h
index 935049b6ae..bf8853a43a 100644
--- a/board/bugzzy/cbi_ssfc.h
+++ b/board/bugzzy/cbi_ssfc.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -56,5 +56,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
  */
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
 
-
 #endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/bugzzy/ec.tasklist b/board/bugzzy/ec.tasklist
index d4fb416bce..29666dd959 100644
--- a/board/bugzzy/ec.tasklist
+++ b/board/bugzzy/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/bugzzy/gpio.inc b/board/bugzzy/gpio.inc
index b8bd5bf604..8e0fa56768 100644
--- a/board/bugzzy/gpio.inc
+++ b/board/bugzzy/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/bugzzy/led.c b/board/bugzzy/led.c
index 17da244534..cad2d5ed0b 100644
--- a/board/bugzzy/led.c
+++ b/board/bugzzy/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -12,8 +12,8 @@
 #include "led_common.h"
 #include "led_onoff_states.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
 __override const int led_charge_lvl_1 = 1;
 
@@ -21,33 +21,36 @@ __override const int led_charge_lvl_2 = 100;
 
 /* bugzzy : There are 3 leds for AC, Battery and Power */
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC},
-					{LED_OFF, 1 * LED_ONE_SEC} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED, 0.5 * LED_ONE_SEC},
-					{LED_OFF, 0.5 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC},
-					{LED_OFF, 1 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     1 * LED_ONE_SEC },
+					   { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_GREEN,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED,
+					    0.5 * LED_ONE_SEC },
+					  { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					 { LED_OFF, 1 * LED_ONE_SEC } },
+	};
 
 __override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_BLUE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -57,7 +60,7 @@ __override void led_set_color_power(enum ec_led_colors color)
 
 	/* Don't set led if led_auto_control is disabled. */
 	if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) ||
-		!led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
+	    !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
 		return;
 	}
 
@@ -70,8 +73,7 @@ __override void led_set_color_power(enum ec_led_colors color)
 		return;
 	}
 
-	if (color == EC_LED_COLOR_BLUE)
-	{
+	if (color == EC_LED_COLOR_BLUE) {
 		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
 		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
 		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_ON_LVL);
@@ -87,7 +89,7 @@ __override void led_set_color_battery(enum ec_led_colors color)
 
 	/* Don't set led if led_auto_control is disabled. */
 	if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) ||
-		!led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
+	    !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
 		return;
 	}
 
@@ -140,12 +142,12 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 	if (led_id == EC_LED_ID_BATTERY_LED) {
 		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_OFF_LVL);
 		gpio_set_level(GPIO_BAT_LED_GREEN_L,
-				!brightness[EC_LED_COLOR_GREEN]);
+			       !brightness[EC_LED_COLOR_GREEN]);
 		gpio_set_level(GPIO_BAT_LED_RED_L,
-				!brightness[EC_LED_COLOR_RED]);
+			       !brightness[EC_LED_COLOR_RED]);
 	} else if (led_id == EC_LED_ID_POWER_LED) {
 		gpio_set_level(GPIO_PWR_LED_BLUE_L,
-				!brightness[EC_LED_COLOR_BLUE]);
+			       !brightness[EC_LED_COLOR_BLUE]);
 		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
 		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
 	}
diff --git a/board/bugzzy/usb_pd_policy.c b/board/bugzzy/usb_pd_policy.c
index 15faf41ffc..83c09bb99e 100644
--- a/board/bugzzy/usb_pd_policy.c
+++ b/board/bugzzy/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,8 @@
 #include "driver/tcpm/tcpci.h"
 #include "usb_pd.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
diff --git a/board/burnet/battery.c b/board/burnet/battery.c
index 7d9b659ad1..d76634d6ce 100644
--- a/board/burnet/battery.c
+++ b/board/burnet/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/burnet/board.c b/board/burnet/board.c
index 23abc2dad9..aa378ca289 100644
--- a/board/burnet/board.c
+++ b/board/burnet/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -34,6 +34,7 @@
 #include "it8801.h"
 #include "keyboard_scan.h"
 #include "lid_switch.h"
+#include "panic.h"
 #include "power.h"
 #include "power_button.h"
 #include "registers.h"
@@ -48,8 +49,8 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
@@ -61,40 +62,34 @@ static void tcpc_alert_event(enum gpio_signal signal)
 /******************************************************************************/
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] =  {"BOARD_ID",  3300, 4096, 0, STM32_AIN(10)},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)},
+	[ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(10) },
+	[ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /******************************************************************************/
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "typec",
-		.port = 0,
-		.kbps = 400,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	},
-	{
-		.name = "other",
-		.port = 1,
-		.kbps = 100,
-		.scl  = GPIO_I2C2_SCL,
-		.sda  = GPIO_I2C2_SDA
-	},
+	{ .name = "typec",
+	  .port = 0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "other",
+	  .port = 1,
+	  .kbps = 100,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
 const struct i2c_port_t i2c_bitbang_ports[] = {
-	{
-		.name = "battery",
-		.port = 2,
-		.kbps = 100,
-		.scl  = GPIO_I2C3_SCL,
-		.sda  = GPIO_I2C3_SDA,
-		.drv = &bitbang_drv
-	},
+	{ .name = "battery",
+	  .port = 2,
+	  .kbps = 100,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA,
+	  .drv = &bitbang_drv },
 };
 const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
 
@@ -102,8 +97,8 @@ const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
 
 /* power signal list.  Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
+	{ GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" },
+	{ GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" },
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
@@ -159,8 +154,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-static void board_hpd_status(const struct usb_mux *me,
-			     mux_state_t mux_state,
+static void board_hpd_status(const struct usb_mux *me, mux_state_t mux_state,
 			     bool *ack_required)
 {
 	/* This driver does not use host command ACKs */
@@ -173,13 +167,16 @@ static void board_hpd_status(const struct usb_mux *me,
 	host_set_single_event(EC_HOST_EVENT_USB_MUX);
 }
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+				.hpd_update = &board_hpd_status,
+			},
 	},
 };
 
@@ -225,12 +222,12 @@ int board_set_active_charge_port(int charge_port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-			       CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 int board_discharge_on_ac(int enable)
@@ -300,8 +297,7 @@ static void board_spi_enable(void)
 	/* Pin mux spi peripheral toward the sensor. */
 	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
 }
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP,
-	     board_spi_enable,
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_spi_enable,
 	     MOTION_SENSE_HOOK_PRIO - 1);
 
 static void board_spi_disable(void)
@@ -309,14 +305,15 @@ static void board_spi_disable(void)
 	/* Set pins to a state calming the sensor down. */
 	gpio_set_flags(GPIO_EC_SENSOR_SPI_CK, GPIO_OUT_LOW);
 	gpio_set_level(GPIO_EC_SENSOR_SPI_CK, 0);
+	gpio_set_flags(GPIO_EC_SENSOR_SPI_NSS, GPIO_OUT_LOW);
+	gpio_set_level(GPIO_EC_SENSOR_SPI_NSS, 0);
 	gpio_config_module(MODULE_SPI_CONTROLLER, 0);
 
 	/* Disable spi peripheral and clocks. */
 	spi_enable(&spi_devices[0], 0);
 	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
 }
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN,
-	     board_spi_disable,
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_spi_disable,
 	     MOTION_SENSE_HOOK_PRIO + 1);
 #endif /* !VARIANT_KUKUI_NO_SENSORS */
 
@@ -327,23 +324,17 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Rotation matrixes */
-static const mat33_fp_t lid_standard_ref = {
-	{FLOAT_TO_FP(1), 0, 0},
-	{0, FLOAT_TO_FP(-1), 0},
-	{0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
-static const mat33_fp_t base_bmi160_ref = {
-	{FLOAT_TO_FP(-1), 0, 0},
-	{0, FLOAT_TO_FP(1), 0},
-	{0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t base_bmi160_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					    { 0, FLOAT_TO_FP(1), 0 },
+					    { 0, 0, FLOAT_TO_FP(-1) } };
 
-static const mat33_fp_t base_icm42607_ref = {
-	{0, FLOAT_TO_FP(-1), 0},
-	{FLOAT_TO_FP(-1), 0, 0},
-	{0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t base_icm42607_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+					      { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
 
 /* sensor private data */
 static struct accelgyro_saved_data_t g_bma253_data;
@@ -516,8 +507,7 @@ static void board_update_config(void)
 	enum ec_error_list rv;
 
 	/* Ping for ack */
-	rv = i2c_read8(I2C_PORT_SENSORS,
-		       KX022_ADDR1_FLAGS, KX022_WHOAMI, &val);
+	rv = i2c_read8(I2C_PORT_SENSORS, KX022_ADDR1_FLAGS, KX022_WHOAMI, &val);
 
 	if (rv == EC_SUCCESS)
 		motion_sensors[LID_ACCEL] = lid_accel_kx022;
@@ -553,7 +543,8 @@ static void board_init(void)
 		motion_sensor_count = ARRAY_SIZE(motion_sensors);
 		/* Enable interrupts from BMI160 sensor. */
 		gpio_enable_interrupt(GPIO_ACCEL_INT_ODL);
-		/* For some reason we have to do this again in case of sysjump */
+		/* For some reason we have to do this again in case of sysjump
+		 */
 		board_spi_enable();
 		board_update_config();
 	} else {
@@ -563,8 +554,7 @@ static void board_init(void)
 		/* Turn off GMR interrupt */
 		gmr_tablet_switch_disable();
 		/* Base accel is not stuffed, don't allow line to float */
-		gpio_set_flags(GPIO_ACCEL_INT_ODL,
-			       GPIO_INPUT | GPIO_PULL_DOWN);
+		gpio_set_flags(GPIO_ACCEL_INT_ODL, GPIO_INPUT | GPIO_PULL_DOWN);
 		board_spi_disable();
 	}
 #endif /* !VARIANT_KUKUI_NO_SENSORS */
diff --git a/board/burnet/board.h b/board/burnet/board.h
index 1cc103d6fc..6870ccc2d2 100644
--- a/board/burnet/board.h
+++ b/board/burnet/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -52,9 +52,9 @@
 
 /* Motion Sensors */
 #ifndef VARIANT_KUKUI_NO_SENSORS
-#define CONFIG_ACCEL_BMA255		/* Lid accel */
+#define CONFIG_ACCEL_BMA255 /* Lid accel */
 #define CONFIG_ACCEL_KX022
-#define CONFIG_ACCELGYRO_BMI160		/* Base accel */
+#define CONFIG_ACCELGYRO_BMI160 /* Base accel */
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 /* ICM42607 Base accel/gyro */
@@ -75,20 +75,20 @@
 #endif /* VARIANT_KUKUI_NO_SENSORS */
 
 /* I2C ports */
-#define I2C_PORT_BC12               0
-#define I2C_PORT_TCPC0              0
-#define I2C_PORT_USB_MUX            0
-#define I2C_PORT_BATTERY            2
-#define I2C_PORT_CHARGER            1
-#define I2C_PORT_SENSORS            1
-#define I2C_PORT_KB_DISCRETE        1
-#define I2C_PORT_VIRTUAL_BATTERY    I2C_PORT_BATTERY
+#define I2C_PORT_BC12 0
+#define I2C_PORT_TCPC0 0
+#define I2C_PORT_USB_MUX 0
+#define I2C_PORT_BATTERY 2
+#define I2C_PORT_CHARGER 1
+#define I2C_PORT_SENSORS 1
+#define I2C_PORT_KB_DISCRETE 1
+#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
 
 /* IT8801 I2C address */
-#define KB_DISCRETE_I2C_ADDR_FLAGS  IT8801_I2C_ADDR1
+#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1
 
 /* Enable Accel over SPI */
-#define CONFIG_SPI_ACCEL_PORT    0  /* The first SPI controller port (SPI2) */
+#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */
 
 #define CONFIG_KEYBOARD_PROTOCOL_MKBP
 #define CONFIG_MKBP_EVENT
diff --git a/board/burnet/build.mk b/board/burnet/build.mk
index a6e1c010d7..f583684804 100644
--- a/board/burnet/build.mk
+++ b/board/burnet/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/burnet/ec.tasklist b/board/burnet/ec.tasklist
index c1330b86f8..fb131b8eb4 100644
--- a/board/burnet/ec.tasklist
+++ b/board/burnet/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/burnet/gpio.inc b/board/burnet/gpio.inc
index c43a232870..9bb0aa73db 100644
--- a/board/burnet/gpio.inc
+++ b/board/burnet/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/burnet/led.c b/board/burnet/led.c
index 06ae68609e..4aa91c63e2 100644
--- a/board/burnet/led.c
+++ b/board/burnet/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -17,10 +17,8 @@
 #define POWER_LED_ON 0
 #define POWER_LED_OFF 1
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -28,7 +26,7 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static int led_set_color_battery(enum led_color color)
@@ -111,8 +109,7 @@ static void led_set_power(void)
 	if (chipset_in_state(CHIPSET_STATE_ON))
 		led_set_color_power(LED_WHITE);
 	else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-		led_set_color_power(
-			(power_tick & 0x2) ? LED_WHITE : LED_OFF);
+		led_set_color_power((power_tick & 0x2) ? LED_WHITE : LED_OFF);
 	else
 		led_set_color_power(LED_OFF);
 }
@@ -121,7 +118,6 @@ static void led_set_battery(void)
 {
 	static int battery_ticks;
 	static int power_ticks;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
@@ -132,10 +128,10 @@ static void led_set_battery(void)
 	 */
 	if (!board_is_convertible()) {
 		if (chipset_in_state(CHIPSET_STATE_SUSPEND |
-					 CHIPSET_STATE_STANDBY) &&
-			charge_get_state() != PWR_STATE_CHARGE) {
-			led_set_color_battery(power_ticks++ & 0x2 ?
-						  LED_WHITE : LED_OFF);
+				     CHIPSET_STATE_STANDBY) &&
+		    charge_get_state() != PWR_STATE_CHARGE) {
+			led_set_color_battery(power_ticks++ & 0x2 ? LED_WHITE :
+								    LED_OFF);
 			return;
 		}
 	}
@@ -164,18 +160,18 @@ static void led_set_battery(void)
 			led_set_color_battery(LED_OFF);
 		break;
 	case PWR_STATE_ERROR:
-		led_set_color_battery(
-			(battery_ticks % 0x2) ? LED_WHITE : LED_OFF);
+		led_set_color_battery((battery_ticks % 0x2) ? LED_WHITE :
+							      LED_OFF);
 		break;
 	case PWR_STATE_CHARGE_NEAR_FULL:
 		led_set_color_battery(LED_WHITE);
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			led_set_color_battery(
-				(battery_ticks & 0x2) ? LED_AMBER : LED_OFF);
-		else
-			led_set_color_battery(LED_WHITE);
+		led_set_color_battery(LED_WHITE);
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		led_set_color_battery((battery_ticks & 0x2) ? LED_AMBER :
+							      LED_OFF);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
diff --git a/board/c2d2/board.c b/board/c2d2/board.c
index 24b314118e..fa6373c861 100644
--- a/board/c2d2/board.c
+++ b/board/c2d2/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -30,8 +30,8 @@
 
 #include "gpio_list.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
 /* Forward declarations */
 static void update_vrefs_and_shifters(void);
@@ -41,19 +41,19 @@ static bool is_ec_i2c_enabled(void);
 /* Global state tracking current pin configuration and operations */
 static struct mutex vref_bus_state_mutex;
 static int vref_monitor_disable;
-#define VREF_MON_DIS_H1_RST_HELD	BIT(0)
-#define VREF_MON_DIS_EC_PWR_HELD	BIT(1)
-#define VREF_MON_DIS_SPI_MODE		BIT(2)
+#define VREF_MON_DIS_H1_RST_HELD BIT(0)
+#define VREF_MON_DIS_EC_PWR_HELD BIT(1)
+#define VREF_MON_DIS_SPI_MODE BIT(2)
 
 /*
  * Tracks if bus pins are locked by a function like UART holding, I2C,
  * or SPI.
  */
 enum bus_lock {
-	BUS_UNLOCKED,	/* Normal UART; pins available for other functions */
-	BUS_UART_HELD,	/* UART locked to pins while holding RX low */
-	BUS_SPI,	/* SPI locked to pins */
-	BUS_I2C,	/* I2C bus locked to pins */
+	BUS_UNLOCKED, /* Normal UART; pins available for other functions */
+	BUS_UART_HELD, /* UART locked to pins while holding RX low */
+	BUS_SPI, /* SPI locked to pins */
+	BUS_I2C, /* I2C bus locked to pins */
 };
 /* A0/A1 (H1 UART or SPI) */
 enum bus_lock h1_pins;
@@ -77,7 +77,7 @@ static const char *lock_to_string(const enum bus_lock val)
 	return names[val];
 }
 
-static int command_bus_status(int argc, char **argv)
+static int command_bus_status(int argc, const char **argv)
 {
 	if (argc > 1)
 		return EC_ERROR_PARAM_COUNT;
@@ -88,11 +88,9 @@ static int command_bus_status(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(bus_status, command_bus_status,
-			"",
+DECLARE_CONSOLE_COMMAND(bus_status, command_bus_status, "",
 			"Gets the bus state for swappable pins");
 
-
 /******************************************************************************
  ** Chip-specific board configuration
  */
@@ -114,12 +112,11 @@ void board_config_pre_init(void)
 	 *  i2c : no dma
 	 *  tim16/17: no dma
 	 */
-	STM32_SYSCFG_CFGR1 |= BIT(24);	/* Remap SPI2_RX to channel 6 */
-	STM32_SYSCFG_CFGR1 |= BIT(26);  /* Remap USART3 RX/TX DMA */
-	STM32_SYSCFG_CFGR1 |= BIT(10);  /* Remap USART1 RX/TX DMA */
+	STM32_SYSCFG_CFGR1 |= BIT(24); /* Remap SPI2_RX to channel 6 */
+	STM32_SYSCFG_CFGR1 |= BIT(26); /* Remap USART3 RX/TX DMA */
+	STM32_SYSCFG_CFGR1 |= BIT(10); /* Remap USART1 RX/TX DMA */
 }
 
-
 /******************************************************************************
  ** ADC channels
  */
@@ -147,18 +144,18 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
  * Define the strings used in our USB descriptors.
  */
 const void *const usb_strings[] = {
-	[USB_STR_DESC]			= usb_string_desc,
-	[USB_STR_VENDOR]		= USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]		= USB_STRING_DESC("C2D2"),
-	[USB_STR_SERIALNO]		= 0,
-	[USB_STR_VERSION]		= USB_STRING_DESC(CROS_EC_VERSION32),
-	[USB_STR_USART4_STREAM_NAME]	= USB_STRING_DESC("CR50"),
-	[USB_STR_UPDATE_NAME]		= USB_STRING_DESC("Firmware update"),
-	[USB_STR_CONSOLE_NAME]		= USB_STRING_DESC("C2D2 Shell"),
-	[USB_STR_SPI_NAME]		= USB_STRING_DESC("SPI"),
-	[USB_STR_I2C_NAME]		= USB_STRING_DESC("I2C"),
-	[USB_STR_USART3_STREAM_NAME]	= USB_STRING_DESC("CPU"),
-	[USB_STR_USART1_STREAM_NAME]	= USB_STRING_DESC("EC"),
+	[USB_STR_DESC] = usb_string_desc,
+	[USB_STR_VENDOR] = USB_STRING_DESC("Google LLC"),
+	[USB_STR_PRODUCT] = USB_STRING_DESC("C2D2"),
+	[USB_STR_SERIALNO] = 0,
+	[USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32),
+	[USB_STR_USART4_STREAM_NAME] = USB_STRING_DESC("CR50"),
+	[USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"),
+	[USB_STR_CONSOLE_NAME] = USB_STRING_DESC("C2D2 Shell"),
+	[USB_STR_SPI_NAME] = USB_STRING_DESC("SPI"),
+	[USB_STR_I2C_NAME] = USB_STRING_DESC("I2C"),
+	[USB_STR_USART3_STREAM_NAME] = USB_STRING_DESC("CPU"),
+	[USB_STR_USART1_STREAM_NAME] = USB_STRING_DESC("EC"),
 };
 
 BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
@@ -174,7 +171,7 @@ const struct i2c_port_t i2c_ports[] = {
 		.port = I2C_PORT_EC,
 		.kbps = 100,
 		.scl = GPIO_UART_DBG_TX_EC_RX_SCL,
-		.sda =  GPIO_UART_EC_TX_DBG_RX_SDA,
+		.sda = GPIO_UART_EC_TX_DBG_RX_SDA,
 		.flags = I2C_PORT_FLAG_DYNAMIC_SPEED,
 	},
 	{
@@ -182,7 +179,7 @@ const struct i2c_port_t i2c_ports[] = {
 		.port = I2C_PORT_AUX,
 		.kbps = 100,
 		.scl = GPIO_UART_DBG_TX_AP_RX_INA_SCL,
-		.sda =  GPIO_UART_AP_TX_DBG_RX_INA_SDA,
+		.sda = GPIO_UART_AP_TX_DBG_RX_INA_SDA,
 		.flags = I2C_PORT_FLAG_DYNAMIC_SPEED,
 	},
 };
@@ -203,14 +200,19 @@ const struct ite_dfu_config_t ite_dfu_config = {
  * let the i2c transactions fail instead of using the USB endpoint disable
  * status.
  */
-int usb_i2c_board_is_enabled(void) { return 1; }
+int usb_i2c_board_is_enabled(void)
+{
+	return 1;
+}
 
 /******************************************************************************
  * Forward UARTs as a USB serial interface.
  */
 
-#define USB_STREAM_RX_SIZE	32
-#define USB_STREAM_TX_SIZE	64
+#define USB_STREAM_RX_SIZE 32
+#define USB_STREAM_TX_SIZE 64
+#define USART_TO_USB_SIZE 1024
+#define USB_TO_USART_SIZE 64
 
 /******************************************************************************
  * Forward USART1 (EC) as a simple USB serial interface.
@@ -219,33 +221,22 @@ int usb_i2c_board_is_enabled(void) { return 1; }
 static struct usart_config const usart1;
 struct usb_stream_config const usart1_usb;
 
-static struct queue const usart1_to_usb = QUEUE_DIRECT(128, uint8_t,
-	usart1.producer, usart1_usb.consumer);
-static struct queue const usb_to_usart1 = QUEUE_DIRECT(64, uint8_t,
-	usart1_usb.producer, usart1.consumer);
+static struct queue const usart1_to_usb = QUEUE_DIRECT(
+	USART_TO_USB_SIZE, uint8_t, usart1.producer, usart1_usb.consumer);
+static struct queue const usb_to_usart1 = QUEUE_DIRECT(
+	USB_TO_USART_SIZE, uint8_t, usart1_usb.producer, usart1.consumer);
 
 static struct usart_rx_dma const usart1_rx_dma =
 	USART_RX_DMA(STM32_DMAC_CH5, 32);
 
 static struct usart_config const usart1 =
-	USART_CONFIG(usart1_hw,
-		usart1_rx_dma.usart_rx,
-		usart_tx_interrupt,
-		115200,
-		0,
-		usart1_to_usb,
-		usb_to_usart1);
-
-USB_STREAM_CONFIG_USART_IFACE(usart1_usb,
-	USB_IFACE_USART1_STREAM,
-	USB_STR_USART1_STREAM_NAME,
-	USB_EP_USART1_STREAM,
-	USB_STREAM_RX_SIZE,
-	USB_STREAM_TX_SIZE,
-	usb_to_usart1,
-	usart1_to_usb,
-	usart1)
+	USART_CONFIG(usart1_hw, usart1_rx_dma.usart_rx, usart_tx_interrupt,
+		     115200, 0, usart1_to_usb, usb_to_usart1);
 
+USB_STREAM_CONFIG_USART_IFACE(usart1_usb, USB_IFACE_USART1_STREAM,
+			      USB_STR_USART1_STREAM_NAME, USB_EP_USART1_STREAM,
+			      USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE,
+			      usb_to_usart1, usart1_to_usb, usart1)
 
 /******************************************************************************
  * Forward USART3 (CPU) as a simple USB serial interface.
@@ -254,33 +245,22 @@ USB_STREAM_CONFIG_USART_IFACE(usart1_usb,
 static struct usart_config const usart3;
 struct usb_stream_config const usart3_usb;
 
-static struct queue const usart3_to_usb = QUEUE_DIRECT(1024, uint8_t,
-	usart3.producer, usart3_usb.consumer);
-static struct queue const usb_to_usart3 = QUEUE_DIRECT(64, uint8_t,
-	usart3_usb.producer, usart3.consumer);
+static struct queue const usart3_to_usb = QUEUE_DIRECT(
+	USART_TO_USB_SIZE, uint8_t, usart3.producer, usart3_usb.consumer);
+static struct queue const usb_to_usart3 = QUEUE_DIRECT(
+	USB_TO_USART_SIZE, uint8_t, usart3_usb.producer, usart3.consumer);
 
 static struct usart_rx_dma const usart3_rx_dma =
 	USART_RX_DMA(STM32_DMAC_CH3, 32);
 
 static struct usart_config const usart3 =
-	USART_CONFIG(usart3_hw,
-		usart3_rx_dma.usart_rx,
-		usart_tx_interrupt,
-		115200,
-		0,
-		usart3_to_usb,
-		usb_to_usart3);
-
-USB_STREAM_CONFIG_USART_IFACE(usart3_usb,
-	USB_IFACE_USART3_STREAM,
-	USB_STR_USART3_STREAM_NAME,
-	USB_EP_USART3_STREAM,
-	USB_STREAM_RX_SIZE,
-	USB_STREAM_TX_SIZE,
-	usb_to_usart3,
-	usart3_to_usb,
-	usart3)
+	USART_CONFIG(usart3_hw, usart3_rx_dma.usart_rx, usart_tx_interrupt,
+		     115200, 0, usart3_to_usb, usb_to_usart3);
 
+USB_STREAM_CONFIG_USART_IFACE(usart3_usb, USB_IFACE_USART3_STREAM,
+			      USB_STR_USART3_STREAM_NAME, USB_EP_USART3_STREAM,
+			      USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE,
+			      usb_to_usart3, usart3_to_usb, usart3)
 
 /******************************************************************************
  * Forward USART4 (cr50) as a simple USB serial interface.
@@ -291,29 +271,19 @@ USB_STREAM_CONFIG_USART_IFACE(usart3_usb,
 static struct usart_config const usart4;
 struct usb_stream_config const usart4_usb;
 
-static struct queue const usart4_to_usb = QUEUE_DIRECT(1024, uint8_t,
-	usart4.producer, usart4_usb.consumer);
-static struct queue const usb_to_usart4 = QUEUE_DIRECT(64, uint8_t,
-	usart4_usb.producer, usart4.consumer);
+static struct queue const usart4_to_usb = QUEUE_DIRECT(
+	USART_TO_USB_SIZE, uint8_t, usart4.producer, usart4_usb.consumer);
+static struct queue const usb_to_usart4 = QUEUE_DIRECT(
+	USB_TO_USART_SIZE, uint8_t, usart4_usb.producer, usart4.consumer);
 
 static struct usart_config const usart4 =
-	USART_CONFIG(usart4_hw,
-		usart_rx_interrupt,
-		usart_tx_interrupt,
-		115200,
-		0,
-		usart4_to_usb,
-		usb_to_usart4);
-
-USB_STREAM_CONFIG_USART_IFACE(usart4_usb,
-	USB_IFACE_USART4_STREAM,
-	USB_STR_USART4_STREAM_NAME,
-	USB_EP_USART4_STREAM,
-	USB_STREAM_RX_SIZE,
-	USB_STREAM_TX_SIZE,
-	usb_to_usart4,
-	usart4_to_usb,
-	usart4)
+	USART_CONFIG(usart4_hw, usart_rx_interrupt, usart_tx_interrupt, 115200,
+		     0, usart4_to_usb, usb_to_usart4);
+
+USB_STREAM_CONFIG_USART_IFACE(usart4_usb, USB_IFACE_USART4_STREAM,
+			      USB_STR_USART4_STREAM_NAME, USB_EP_USART4_STREAM,
+			      USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE,
+			      usb_to_usart4, usart4_to_usb, usart4)
 
 /******************************************************************************
  * Set up SPI over USB
@@ -322,7 +292,7 @@ USB_STREAM_CONFIG_USART_IFACE(usart4_usb,
 
 /* SPI devices */
 const struct spi_device_t spi_devices[] = {
-	{ CONFIG_SPI_FLASH_PORT, 1, GPIO_SPI_CSN},
+	{ CONFIG_SPI_FLASH_PORT, 1, GPIO_SPI_CSN },
 };
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
@@ -364,7 +334,7 @@ USB_SPI_CONFIG(usb_spi, USB_IFACE_SPI, USB_EP_SPI,
 /******************************************************************************
  * Check parity setting on usarts.
  */
-static int command_uart_parity(int argc, char **argv)
+static int command_uart_parity(int argc, const char **argv)
 {
 	int parity = 0, newparity;
 	struct usart_config const *usart;
@@ -398,14 +368,13 @@ static int command_uart_parity(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(parity, command_uart_parity,
-			"usart[2|3|4] [0|1|2]",
+DECLARE_CONSOLE_COMMAND(parity, command_uart_parity, "usart[2|3|4] [0|1|2]",
 			"Set parity on uart");
 
 /******************************************************************************
  * Set baud rate setting on usarts.
  */
-static int command_uart_baud(int argc, char **argv)
+static int command_uart_baud(int argc, const char **argv)
 {
 	int baud = 0;
 	struct usart_config const *usart;
@@ -431,14 +400,13 @@ static int command_uart_baud(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(baud, command_uart_baud,
-			"usart[2|3|4] rate",
+DECLARE_CONSOLE_COMMAND(baud, command_uart_baud, "usart[2|3|4] rate",
 			"Set baud rate on uart");
 
 /******************************************************************************
  * Hold the usart pins low while disabling it, or return it to normal.
  */
-static int command_hold_usart_low(int argc, char **argv)
+static int command_hold_usart_low(int argc, const char **argv)
 {
 	enum bus_lock *bus;
 	enum gpio_signal rx;
@@ -501,7 +469,7 @@ static int command_hold_usart_low(int argc, char **argv)
 
 	/* Print status for get and set case. */
 	ccprintf("USART status: %s\n",
-			*bus == BUS_UART_HELD ? "held low" : "normal");
+		 *bus == BUS_UART_HELD ? "held low" : "normal");
 
 	return EC_SUCCESS;
 
@@ -513,7 +481,6 @@ DECLARE_CONSOLE_COMMAND(hold_usart_low, command_hold_usart_low,
 			"usart[1|3|4] [0|1]?",
 			"Get/set the hold-low state for usart port");
 
-
 /******************************************************************************
  * Console commands SPI programming
  */
@@ -523,7 +490,7 @@ enum vref {
 	PP3300 = 3300,
 };
 
-static int command_enable_spi(int argc, char **argv)
+static int command_enable_spi(int argc, const char **argv)
 {
 	static enum vref current_spi_vref_state;
 
@@ -650,8 +617,7 @@ busy_error_unlock:
 	mutex_unlock(&vref_bus_state_mutex);
 	return EC_ERROR_BUSY;
 }
-DECLARE_CONSOLE_COMMAND(enable_spi, command_enable_spi,
-			"[0|1800|3300]?",
+DECLARE_CONSOLE_COMMAND(enable_spi, command_enable_spi, "[0|1800|3300]?",
 			"Get/set the SPI Vref");
 
 /******************************************************************************
@@ -686,7 +652,7 @@ static inline int to_kbps(enum i2c_freq freq)
 	}
 }
 
-static int command_enable_i2c(int argc, char **argv)
+static int command_enable_i2c(int argc, const char **argv)
 {
 	int i2c_index;
 	enum bus_lock *bus;
@@ -770,7 +736,7 @@ DECLARE_CONSOLE_COMMAND(enable_i2c, command_enable_i2c,
  * Console commands for asserting H1 reset and EC Power button
  */
 
-static int command_vref_alternate(int argc, char **argv,
+static int command_vref_alternate(int argc, const char **argv,
 				  const enum gpio_signal vref_signal,
 				  const enum gpio_signal en_signal,
 				  const int state_flag,
@@ -819,7 +785,6 @@ static int command_vref_alternate(int argc, char **argv,
 	ccprintf("%s held: %s\n", print_name,
 		 vref_monitor_disable & state_flag ? "yes" : "no");
 
-
 	return EC_SUCCESS;
 
 busy_error_unlock:
@@ -827,24 +792,23 @@ busy_error_unlock:
 	return EC_ERROR_BUSY;
 }
 
-static int command_pwr_button(int argc, char **argv)
+static int command_pwr_button(int argc, const char **argv)
 {
 	return command_vref_alternate(argc, argv,
 				      GPIO_SPIVREF_HOLDN_ECVREF_H1_PWRBTN_ODL,
 				      GPIO_EN_SPIVREF_HOLDN_ECVREF_H1_PWRBTN,
 				      VREF_MON_DIS_EC_PWR_HELD, "Power button");
 }
-DECLARE_CONSOLE_COMMAND(pwr_button, command_pwr_button,
-			"[0|1]?",
+DECLARE_CONSOLE_COMMAND(pwr_button, command_pwr_button, "[0|1]?",
 			"Get/set the power button state");
 
-static int command_h1_reset(int argc, char **argv)
+static int command_h1_reset(int argc, const char **argv)
 {
 	if ((argc == 2) && !strncasecmp("pulse", argv[1], strlen(argv[1]))) {
 		int rv;
 		int c = 2;
-		char *cmd_on[] = {"", "1", ""};
-		char *cmd_off[] = {"", "0", ""};
+		const char *cmd_on[] = { "", "1", "" };
+		const char *cmd_off[] = { "", "0", "" };
 
 		rv = command_vref_alternate(c, cmd_on,
 					    GPIO_SPIVREF_RSVD_H1VREF_H1_RST_ODL,
@@ -853,11 +817,10 @@ static int command_h1_reset(int argc, char **argv)
 					    "H1 reset");
 		if (rv == EC_SUCCESS) {
 			msleep(100);
-			rv = command_vref_alternate
-				(c, cmd_off,
-				 GPIO_SPIVREF_RSVD_H1VREF_H1_RST_ODL,
-				 GPIO_EN_SPIVREF_RSVD_H1VREF_H1_RST,
-				 VREF_MON_DIS_H1_RST_HELD, "H1 reset");
+			rv = command_vref_alternate(
+				c, cmd_off, GPIO_SPIVREF_RSVD_H1VREF_H1_RST_ODL,
+				GPIO_EN_SPIVREF_RSVD_H1VREF_H1_RST,
+				VREF_MON_DIS_H1_RST_HELD, "H1 reset");
 		}
 		return rv;
 	}
@@ -867,11 +830,9 @@ static int command_h1_reset(int argc, char **argv)
 				      GPIO_EN_SPIVREF_RSVD_H1VREF_H1_RST,
 				      VREF_MON_DIS_H1_RST_HELD, "H1 reset");
 }
-DECLARE_CONSOLE_COMMAND(h1_reset, command_h1_reset,
-			"[0|1|pulse]?",
+DECLARE_CONSOLE_COMMAND(h1_reset, command_h1_reset, "[0|1|pulse]?",
 			"Get/set the h1 reset state");
 
-
 /******************************************************************************
  * Vref detection logic
  */
@@ -880,14 +841,13 @@ DECLARE_CONSOLE_COMMAND(h1_reset, command_h1_reset,
 static enum vref h1_vref;
 static enum vref ec_vref;
 
-static int command_h1_vref_present(int argc, char **argv)
+static int command_h1_vref_present(int argc, const char **argv)
 {
 	ccprintf("H1 Vref: %s\n", h1_vref ? "on" : "off");
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(h1_vref, command_h1_vref_present,
-			"",
+DECLARE_CONSOLE_COMMAND(h1_vref, command_h1_vref_present, "",
 			"Get if the h1 vref is present");
 
 /* Voltage thresholds for rail detection */
@@ -1033,11 +993,9 @@ static void update_vrefs_and_shifters(void)
 void set_up_comparator(void)
 {
 	/* Overwrite any previous values. This is the only comparator usage */
-	STM32_COMP_CSR = STM32_COMP_CMP2HYST_HI |
-			 STM32_COMP_CMP2OUTSEL_NONE |
+	STM32_COMP_CSR = STM32_COMP_CMP2HYST_HI | STM32_COMP_CMP2OUTSEL_NONE |
 			 STM32_COMP_CMP2INSEL_INM5 | /* Watch DAC_OUT2 (PA5) */
-			 STM32_COMP_CMP2MODE_LSPEED |
-			 STM32_COMP_CMP2EN;
+			 STM32_COMP_CMP2MODE_LSPEED | STM32_COMP_CMP2EN;
 
 	/* Set Falling and Rising interrupts for COMP2 */
 	STM32_EXTI_FTSR |= EXTI_COMP2_EVENT;
diff --git a/board/c2d2/board.h b/board/c2d2/board.h
index ada5b01ab6..6b1ac69efd 100644
--- a/board/c2d2/board.h
+++ b/board/c2d2/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,9 +21,9 @@
 
 /* Enable USART */
 #define CONFIG_STREAM_USART
-#define CONFIG_STREAM_USART1	/* EC USART */
-#define CONFIG_STREAM_USART3	/* AP USART - not connected by default */
-#define CONFIG_STREAM_USART4	/* H1 USART */
+#define CONFIG_STREAM_USART1 /* EC USART */
+#define CONFIG_STREAM_USART3 /* AP USART - not connected by default */
+#define CONFIG_STREAM_USART4 /* H1 USART */
 #define CONFIG_STREAM_USB
 #define CONFIG_CMD_USART_INFO
 
@@ -45,35 +45,34 @@
 #define DEFAULT_SERIALNO "Uninitialized"
 #define CONFIG_USB_UPDATE
 
-
 /* USB interface indexes (use define rather than enum to expand them)
  *
  * Note these values are used in servo_interface.py for the 'interface' value
  */
-#define USB_IFACE_USART4_STREAM	0	/* H1 */
-#define USB_IFACE_UPDATE	1
-#define USB_IFACE_SPI		2
-#define USB_IFACE_CONSOLE	3
-#define USB_IFACE_I2C		4
-#define USB_IFACE_USART3_STREAM	5	/* AP (not connected by default) */
-#define USB_IFACE_USART1_STREAM	6	/* EC */
-#define USB_IFACE_COUNT		7
+#define USB_IFACE_USART4_STREAM 0 /* H1 */
+#define USB_IFACE_UPDATE 1
+#define USB_IFACE_SPI 2
+#define USB_IFACE_CONSOLE 3
+#define USB_IFACE_I2C 4
+#define USB_IFACE_USART3_STREAM 5 /* AP (not connected by default) */
+#define USB_IFACE_USART1_STREAM 6 /* EC */
+#define USB_IFACE_COUNT 7
 
 /* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL		0
-#define USB_EP_USART4_STREAM	1
-#define USB_EP_UPDATE		2
-#define USB_EP_SPI		3
-#define USB_EP_CONSOLE		4
-#define USB_EP_I2C		5
-#define USB_EP_USART3_STREAM	6
-#define USB_EP_USART1_STREAM	7
-#define USB_EP_COUNT		8
+#define USB_EP_CONTROL 0
+#define USB_EP_USART4_STREAM 1
+#define USB_EP_UPDATE 2
+#define USB_EP_SPI 3
+#define USB_EP_CONSOLE 4
+#define USB_EP_I2C 5
+#define USB_EP_USART3_STREAM 6
+#define USB_EP_USART1_STREAM 7
+#define USB_EP_COUNT 8
 
 /* Enable control of SPI over USB */
 #define CONFIG_USB_SPI
 #define CONFIG_SPI_CONTROLLER
-#define CONFIG_SPI_FLASH_PORT 0  /* SPI2 is 0th in stm's SPI_REGS var */
+#define CONFIG_SPI_FLASH_PORT 0 /* SPI2 is 0th in stm's SPI_REGS var */
 
 /* Enable control of I2C over USB */
 #define CONFIG_USB_I2C
@@ -87,8 +86,8 @@
 #define CONFIG_I2C_XFER_LARGE_TRANSFER
 #undef CONFIG_USB_I2C_MAX_WRITE_COUNT
 #undef CONFIG_USB_I2C_MAX_READ_COUNT
-#define CONFIG_USB_I2C_MAX_WRITE_COUNT ((1<<9) - 4)
-#define CONFIG_USB_I2C_MAX_READ_COUNT ((1<<9) - 6)
+#define CONFIG_USB_I2C_MAX_WRITE_COUNT ((1 << 9) - 4)
+#define CONFIG_USB_I2C_MAX_READ_COUNT ((1 << 9) - 6)
 
 /*
  * Set all ADC samples to take 239.5 clock cycles. This allows us to measure
@@ -114,7 +113,7 @@
 
 /* Timer selection */
 #define TIM_CLOCK32 2
-#define TIM_ADC     3
+#define TIM_ADC 3
 
 #include "gpio_signal.h"
 
diff --git a/board/c2d2/build.mk b/board/c2d2/build.mk
index 559b6b8e95..d5940c3885 100644
--- a/board/c2d2/build.mk
+++ b/board/c2d2/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/c2d2/ec.tasklist b/board/c2d2/ec.tasklist
index c1fb169118..c45a1e89a7 100644
--- a/board/c2d2/ec.tasklist
+++ b/board/c2d2/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/c2d2/gpio.inc b/board/c2d2/gpio.inc
index 485a603453..b100250f20 100644
--- a/board/c2d2/gpio.inc
+++ b/board/c2d2/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/cappy2/battery.c b/board/cappy2/battery.c
index a0aef7bd4c..19be1825eb 100644
--- a/board/cappy2/battery.c
+++ b/board/cappy2/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,8 +11,8 @@
 #include "common.h"
 #include "util.h"
 
-#define CHARGING_VOLTAGE_MV_SAFE        8400
-#define CHARGING_CURRENT_MA_SAFE        1500
+#define CHARGING_VOLTAGE_MV_SAFE 8400
+#define CHARGING_CURRENT_MA_SAFE 1500
 
 /*
  * Battery info for lalala battery types. Note that the fields
@@ -165,13 +165,13 @@ int charger_profile_override(struct charge_state_data *curr)
 }
 
 enum ec_status charger_profile_override_get_param(uint32_t param,
-				uint32_t *value)
+						  uint32_t *value)
 {
 	return EC_RES_INVALID_PARAM;
 }
 
 enum ec_status charger_profile_override_set_param(uint32_t param,
-				uint32_t value)
+						  uint32_t value)
 {
 	return EC_RES_INVALID_PARAM;
 }
diff --git a/board/cappy2/board.c b/board/cappy2/board.c
index c6f560b503..de651ac874 100644
--- a/board/cappy2/board.c
+++ b/board/cappy2/board.c
@@ -1,11 +1,10 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* cappy2 board-specific configuration */
 
-
 #include "adc_chip.h"
 #include "button.h"
 #include "cbi_fw_config.h"
@@ -39,8 +38,8 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 #define INT_RECHECK_US 5000
 
@@ -80,7 +79,6 @@ static void usb_c0_interrupt(enum gpio_signal s)
 
 	/* Check the line again in 5ms */
 	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-
 }
 
 static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
@@ -159,7 +157,6 @@ __override void board_power_5v_enable(int enable)
 	 */
 	gpio_set_level(GPIO_EN_PP5000, !!enable);
 	gpio_set_level(GPIO_EN_USB_A0_VBUS, !!enable);
-
 }
 
 int board_is_sourcing_vbus(int port)
@@ -168,13 +165,11 @@ int board_is_sourcing_vbus(int port)
 
 	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
 	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
-
 }
 
 int board_set_active_charge_port(int port)
 {
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	int i;
 	int old_port;
 
@@ -234,8 +229,8 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
 
@@ -289,12 +284,15 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PS8743_I2C_ADDR0_FLAG,
-		.driver = &ps8743_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = PS8743_I2C_ADDR0_FLAG,
+				.driver = &ps8743_usb_mux_driver,
+			},
 	},
 };
 
@@ -341,23 +339,22 @@ void board_init(void)
 	/* modify AC DC prochot value */
 	isl923x_set_ac_prochot(CHARGER_SOLO, 4096);
 	isl923x_set_dc_prochot(CHARGER_SOLO, 6000);
-
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
 /* Thermistors */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "Cpu",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_3},
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "Cpu",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
diff --git a/board/cappy2/board.h b/board/cappy2/board.h
index 5a2fa75bba..b21a20d6e5 100644
--- a/board/cappy2/board.h
+++ b/board/cappy2/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,9 +11,9 @@
 #define VARIANT_KEEBY_EC_NPCX797FC
 #include "baseboard.h"
 
-#undef	GPIO_VOLUME_UP_L
-#undef	GPIO_VOLUME_DOWN_L
-#undef	CONFIG_VOLUME_BUTTONS
+#undef GPIO_VOLUME_UP_L
+#undef GPIO_VOLUME_DOWN_L
+#undef CONFIG_VOLUME_BUTTONS
 
 /* System unlocked in early development */
 #define CONFIG_SYSTEM_UNLOCKED
@@ -32,15 +32,16 @@
 
 /* Charger */
 #define CONFIG_CHARGER_RAA489000
+#define PD_MAX_VOLTAGE_MV 20000
 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 #define CONFIG_CHARGER_SENSE_RESISTOR 10
 #define CONFIG_CHARGER_SINGLE_CHIP
 #define CONFIG_CHARGER_PROFILE_OVERRIDE
-#undef	CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
+#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
 #define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
 
 /* Keyboard */
-#undef	CONFIG_PWM_KBLIGHT
+#undef CONFIG_PWM_KBLIGHT
 
 /* LED defines */
 #define CONFIG_LED_COMMON
@@ -50,7 +51,7 @@
 #define GPIO_PWR_LED_BLUE_L GPIO_LED_B_ODL
 
 /* PWM */
-#define NPCX7_PWM1_SEL    0  /* GPIO C2 is used as PWM1. */
+#define NPCX7_PWM1_SEL 0 /* GPIO C2 is used as PWM1. */
 
 /******************************************************************************/
 
@@ -81,11 +82,11 @@
 #define GPIO_TEMP_SENSOR_POWER GPIO_EN_PP3300_A
 
 /* I2C configuration */
-#define I2C_PORT_EEPROM     NPCX_I2C_PORT7_0
-#define I2C_PORT_BATTERY    NPCX_I2C_PORT5_0
-#define I2C_PORT_SENSOR     NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0     NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_MUX    I2C_PORT_USB_C0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0
 
 #define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */
 
@@ -95,11 +96,11 @@
 #include "registers.h"
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_1,     /* ADC0 */
-	ADC_TEMP_SENSOR_2,     /* ADC1 */
-	ADC_SUB_ANALOG,	       /* ADC2 */
-	ADC_TEMP_SENSOR_3,     /* ADC6 */
-	ADC_VSNS_PP3300_A,     /* ADC9 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
+	ADC_SUB_ANALOG, /* ADC2 */
+	ADC_TEMP_SENSOR_3, /* ADC6 */
+	ADC_VSNS_PP3300_A, /* ADC9 */
 	ADC_CH_COUNT
 };
 
diff --git a/board/cappy2/build.mk b/board/cappy2/build.mk
index b012d8d502..eb422dae93 100644
--- a/board/cappy2/build.mk
+++ b/board/cappy2/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/cappy2/cbi_ssfc.c b/board/cappy2/cbi_ssfc.c
index c4b859f133..81f3ee0dad 100644
--- a/board/cappy2/cbi_ssfc.c
+++ b/board/cappy2/cbi_ssfc.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
 
 enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
 {
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
 }
 
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
 {
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
 }
diff --git a/board/cappy2/cbi_ssfc.h b/board/cappy2/cbi_ssfc.h
index 935049b6ae..bf8853a43a 100644
--- a/board/cappy2/cbi_ssfc.h
+++ b/board/cappy2/cbi_ssfc.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -56,5 +56,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
  */
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
 
-
 #endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/cappy2/ec.tasklist b/board/cappy2/ec.tasklist
index 0025c2985b..386e8625b3 100644
--- a/board/cappy2/ec.tasklist
+++ b/board/cappy2/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/cappy2/gpio.inc b/board/cappy2/gpio.inc
index 00799bfdd8..1a32f31e06 100644
--- a/board/cappy2/gpio.inc
+++ b/board/cappy2/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/cappy2/led.c b/board/cappy2/led.c
index fb6faae482..dba215ab51 100644
--- a/board/cappy2/led.c
+++ b/board/cappy2/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -21,33 +21,36 @@ __override const int led_charge_lvl_2 = 100;
 
 /* cappy2 : There are 3 leds for AC, Battery and Power */
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC},
-			{LED_OFF, 1 * LED_ONE_SEC} },
-	[STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR] = {{EC_LED_COLOR_RED, 0.5 * LED_ONE_SEC},
-			{LED_OFF, 0.5 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC},
-			{LED_OFF, 1 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     1 * LED_ONE_SEC },
+					   { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED,
+					    0.5 * LED_ONE_SEC },
+					  { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					 { LED_OFF, 1 * LED_ONE_SEC } },
+	};
 
 __override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_BLUE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -55,7 +58,7 @@ __override void led_set_color_power(enum ec_led_colors color)
 {
 	/* Don't set led if led_auto_control is disabled. */
 	if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) ||
-		!led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
+	    !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
 		return;
 	}
 
@@ -73,7 +76,7 @@ __override void led_set_color_battery(enum ec_led_colors color)
 {
 	/* Don't set led if led_auto_control is disabled. */
 	if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) ||
-		!led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
+	    !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
 		return;
 	}
 
@@ -117,12 +120,12 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 	if (led_id == EC_LED_ID_BATTERY_LED) {
 		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_OFF_LVL);
 		gpio_set_level(GPIO_BAT_LED_GREEN_L,
-			!brightness[EC_LED_COLOR_GREEN]);
+			       !brightness[EC_LED_COLOR_GREEN]);
 		gpio_set_level(GPIO_BAT_LED_RED_L,
-			!brightness[EC_LED_COLOR_RED]);
+			       !brightness[EC_LED_COLOR_RED]);
 	} else if (led_id == EC_LED_ID_POWER_LED) {
 		gpio_set_level(GPIO_PWR_LED_BLUE_L,
-			!brightness[EC_LED_COLOR_BLUE]);
+			       !brightness[EC_LED_COLOR_BLUE]);
 		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
 		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
 	}
diff --git a/board/cappy2/usb_pd_policy.c b/board/cappy2/usb_pd_policy.c
index fd9018a3f0..3410726e87 100644
--- a/board/cappy2/usb_pd_policy.c
+++ b/board/cappy2/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,8 +10,8 @@
 #include "driver/tcpm/tcpci.h"
 #include "usb_pd.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
diff --git a/board/careena/battery.c b/board/careena/battery.c
index 7180109168..ae8b2f905a 100644
--- a/board/careena/battery.c
+++ b/board/careena/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/careena/board.c b/board/careena/board.c
index e8171b1be0..cfe7199a91 100644
--- a/board/careena/board.c
+++ b/board/careena/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,45 +26,35 @@ const enum gpio_signal hibernate_wake_pins[] = {
 	GPIO_POWER_BUTTON_L,
 	GPIO_EC_RST_ODL,
 };
-const int hibernate_wake_pins_used =  ARRAY_SIZE(hibernate_wake_pins);
+const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 
 /* I2C port map. */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl  = GPIO_I2C0_SCL,
-		.sda  = GPIO_I2C0_SDA
-	},
-	{
-		.name = "tcpc0",
-		.port = I2C_PORT_TCPC0,
-		.kbps = 400,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	},
-	{
-		.name = "tcpc1",
-		.port = I2C_PORT_TCPC1,
-		.kbps = 400,
-		.scl  = GPIO_I2C2_SCL,
-		.sda  = GPIO_I2C2_SDA
-	},
-	{
-		.name = "thermal",
-		.port = I2C_PORT_THERMAL_AP,
-		.kbps = 400,
-		.scl  = GPIO_I2C3_SCL,
-		.sda  = GPIO_I2C3_SDA
-	},
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl  = GPIO_I2C7_SCL,
-		.sda  = GPIO_I2C7_SDA
-	},
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_I2C0_SCL,
+	  .sda = GPIO_I2C0_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "tcpc1",
+	  .port = I2C_PORT_TCPC1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "thermal",
+	  .port = I2C_PORT_THERMAL_AP,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_I2C7_SCL,
+	  .sda = GPIO_I2C7_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -114,15 +104,15 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
  * that we don't have pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-		{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-		{0, 7}, {1, 4}, {1, 3}, {1, 6}, {-1, -1},
-		{3, 1}, {2, 0}, {1, 5}, {2, 6}, {-1, -1},
-		{2, 1}, {2, 4}, {2, 5}, {1, 2}, {2, 3},
-		{2, 2}, {3, 0}, {-1, -1}, {-1, -1}, {-1, -1},
+	{ -1, -1 }, { 0, 5 }, { 1, 1 },	  { 1, 0 },   { 0, 6 },
+	{ 0, 7 },   { 1, 4 }, { 1, 3 },	  { 1, 6 },   { -1, -1 },
+	{ 3, 1 },   { 2, 0 }, { 1, 5 },	  { 2, 6 },   { -1, -1 },
+	{ 2, 1 },   { 2, 4 }, { 2, 5 },	  { 1, 2 },   { 2, 3 },
+	{ 2, 2 },   { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 },
 };
 
 const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 
 static int board_is_support_ps8755_tcpc(void)
 {
diff --git a/board/careena/board.h b/board/careena/board.h
index 75545cfcaa..86b88b64f0 100644
--- a/board/careena/board.h
+++ b/board/careena/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,7 +17,7 @@
  * By default, enable all console messages excepted HC, ACPI and event:
  * The sensor stack is generating a lot of activity.
  */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
 #undef CONFIG_HOSTCMD_DEBUG_MODE
 #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
 
@@ -41,10 +41,7 @@
 
 #ifndef __ASSEMBLER__
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_COUNT };
 
 enum battery_type {
 	BATTERY_DYNAPACK_COS,
diff --git a/board/careena/build.mk b/board/careena/build.mk
index c808e65aed..d24127ddae 100644
--- a/board/careena/build.mk
+++ b/board/careena/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/careena/ec.tasklist b/board/careena/ec.tasklist
index b562761311..24300fe7da 100644
--- a/board/careena/ec.tasklist
+++ b/board/careena/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/careena/gpio.inc b/board/careena/gpio.inc
index c84c81a68e..477b17234e 100644
--- a/board/careena/gpio.inc
+++ b/board/careena/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/careena/led.c b/board/careena/led.c
index 4188290b4f..48a065fdb9 100644
--- a/board/careena/led.c
+++ b/board/careena/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -20,7 +20,7 @@
 #define BAT_LED_ON 0
 #define BAT_LED_OFF 1
 
-const enum ec_led_id supported_led_ids[] = {EC_LED_ID_BATTERY_LED};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -28,7 +28,7 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static int led_set_color_battery(enum led_color color)
@@ -88,16 +88,14 @@ static void led_set_battery(void)
 {
 	static int battery_ticks;
 	static int power_ticks;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
 	/* override battery led for system suspend */
-	if (chipset_in_state(CHIPSET_STATE_SUSPEND |
-			     CHIPSET_STATE_STANDBY) &&
+	if (chipset_in_state(CHIPSET_STATE_SUSPEND | CHIPSET_STATE_STANDBY) &&
 	    charge_get_state() != PWR_STATE_CHARGE) {
-		led_set_color_battery(power_ticks++ & 0x4 ?
-				      LED_WHITE : LED_OFF);
+		led_set_color_battery(power_ticks++ & 0x4 ? LED_WHITE :
+							    LED_OFF);
 		return;
 	}
 
@@ -125,18 +123,18 @@ static void led_set_battery(void)
 			led_set_color_battery(LED_OFF);
 		break;
 	case PWR_STATE_ERROR:
-		led_set_color_battery(
-			(battery_ticks & 0x2) ? LED_WHITE : LED_OFF);
+		led_set_color_battery((battery_ticks & 0x2) ? LED_WHITE :
+							      LED_OFF);
 		break;
 	case PWR_STATE_CHARGE_NEAR_FULL:
 		led_set_color_battery(LED_WHITE);
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			led_set_color_battery(
-				(battery_ticks & 0x4) ? LED_AMBER : LED_OFF);
-		else
-			led_set_color_battery(LED_WHITE);
+		led_set_color_battery(LED_WHITE);
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		led_set_color_battery((battery_ticks & 0x4) ? LED_AMBER :
+							      LED_OFF);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
diff --git a/board/casta/battery.c b/board/casta/battery.c
index 0ced18e734..efee023d6a 100644
--- a/board/casta/battery.c
+++ b/board/casta/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -12,8 +12,8 @@
 #include "common.h"
 #include "util.h"
 
-#define CHARGING_VOLTAGE_MV_SAFE        8400
-#define CHARGING_CURRENT_MA_SAFE        1500
+#define CHARGING_VOLTAGE_MV_SAFE 8400
+#define CHARGING_CURRENT_MA_SAFE 1500
 
 /*
  * Battery info for all casta battery types. Note that the fields
@@ -95,12 +95,12 @@ int charger_profile_override(struct charge_state_data *curr)
 		TEMP_OUT_OF_RANGE = TEMP_ZONE_COUNT
 	} temp_zone;
 
-        /*
-         * Precharge must be executed when communication is failed on
+	/*
+	 * Precharge must be executed when communication is failed on
 	 * dead battery.
-         */
-        if(!(curr->batt.flags & BATT_FLAG_RESPONSIVE))
-                return 0;
+	 */
+	if (!(curr->batt.flags & BATT_FLAG_RESPONSIVE))
+		return 0;
 
 	current = curr->requested_current;
 	voltage = curr->requested_voltage;
@@ -146,7 +146,7 @@ int charger_profile_override(struct charge_state_data *curr)
 		break;
 	}
 
-	if(voltage > batt_info->voltage_max)
+	if (voltage > batt_info->voltage_max)
 		voltage = batt_info->voltage_max;
 
 	curr->requested_voltage = MIN(curr->requested_voltage, voltage);
diff --git a/board/casta/board.c b/board/casta/board.c
index 24dafc9fee..512a7c224b 100644
--- a/board/casta/board.c
+++ b/board/casta/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -37,10 +37,10 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 static uint8_t sku_id;
 
@@ -65,27 +65,27 @@ static void ppc_interrupt(enum gpio_signal signal)
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_AMB] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_AMB] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				  ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_CHARGER] = { "TEMP_CHARGER", NPCX_ADC_CH1,
+				      ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* TODO(b/119872005): Casta: confirm thermistor parts */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp,
-				 .idx = 0},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
+	[TEMP_SENSOR_BATTERY] = { .name = "Battery",
+				  .type = TEMP_SENSOR_TYPE_BATTERY,
+				  .read = charge_get_battery_temp,
+				  .idx = 0 },
+	[TEMP_SENSOR_AMBIENT] = { .name = "Ambient",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_51k1_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_AMB },
+	[TEMP_SENSOR_CHARGER] = { .name = "Charger",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_13k7_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_CHARGER },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -103,13 +103,12 @@ const unsigned int chg_cnt = ARRAY_SIZE(chg_chips);
  * I2C callbacks to ensure bus free time for battery I2C transactions is at
  * least 5ms.
  */
-#define BATTERY_FREE_MIN_DELTA_US               (5 * MSEC)
+#define BATTERY_FREE_MIN_DELTA_US (5 * MSEC)
 static timestamp_t battery_last_i2c_time;
 
 static int is_battery_i2c(const int port, const uint16_t addr_flags)
 {
-	return (port == I2C_PORT_BATTERY)
-		&& (addr_flags == BATTERY_ADDR_FLAGS);
+	return (port == I2C_PORT_BATTERY) && (addr_flags == BATTERY_ADDR_FLAGS);
 }
 
 static int is_battery_port(int port)
@@ -157,7 +156,7 @@ DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C);
 
 static void board_init(void)
 {
-	if(get_cbi_ssfc_charger() != SSFC_CHARGER_BQ25710)
+	if (get_cbi_ssfc_charger() != SSFC_CHARGER_BQ25710)
 		return;
 
 	chg_chips[0].drv = &bq25710_drv;
@@ -174,7 +173,6 @@ static void set_input_limit_on_ac_removal(void)
 		return;
 
 	charger_set_input_current_limit(0, CONFIG_CHARGER_INPUT_CURRENT);
-
 }
 DECLARE_HOOK(HOOK_AC_CHANGE, set_input_limit_on_ac_removal, HOOK_PRIO_DEFAULT);
 
diff --git a/board/casta/board.h b/board/casta/board.h
index c8f4f7b1e7..3e7fe066cc 100644
--- a/board/casta/board.h
+++ b/board/casta/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -74,8 +74,8 @@
 #include "registers.h"
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_AMB,		/* ADC0 */
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC1 */
+	ADC_TEMP_SENSOR_AMB, /* ADC0 */
+	ADC_TEMP_SENSOR_CHARGER, /* ADC1 */
 	ADC_CH_COUNT
 };
 
diff --git a/board/casta/build.mk b/board/casta/build.mk
index 3d04b75731..998a65a3de 100644
--- a/board/casta/build.mk
+++ b/board/casta/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/casta/ec.tasklist b/board/casta/ec.tasklist
index ac41d643dc..5a1dc02a25 100644
--- a/board/casta/ec.tasklist
+++ b/board/casta/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/casta/gpio.inc b/board/casta/gpio.inc
index e37926b72e..724efd36ce 100644
--- a/board/casta/gpio.inc
+++ b/board/casta/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/casta/led.c b/board/casta/led.c
index 2c4cc63f80..7dfdc39151 100644
--- a/board/casta/led.c
+++ b/board/casta/led.c
@@ -1,8 +1,8 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
- * Power and battery LED control for Casta 
+ * Power and battery LED control for Casta
  */
 
 #include "chipset.h"
@@ -12,8 +12,8 @@
 #include "led_common.h"
 #include "led_onoff_states.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
 __override const int led_charge_lvl_1 = 1;
 
@@ -21,33 +21,36 @@ __override const int led_charge_lvl_2 = 100;
 
 /* Casta : There are 3 leds for AC, Battery and Power */
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC},
-       					{LED_OFF, 1 * LED_ONE_SEC} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED, 0.5 * LED_ONE_SEC},
-					{LED_OFF, 0.5 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC},
-					{LED_OFF, 1 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     1 * LED_ONE_SEC },
+					   { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_GREEN,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED,
+					    0.5 * LED_ONE_SEC },
+					  { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					 { LED_OFF, 1 * LED_ONE_SEC } },
+	};
 
 __override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_BLUE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -55,14 +58,13 @@ __override void led_set_color_power(enum ec_led_colors color)
 {
 	/* Don't set led if led_auto_control is disabled. */
 	if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) ||
-                !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
+	    !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
 		return;
-        }
+	}
 
-	if (color == EC_LED_COLOR_BLUE)
-	{
-                gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
-                gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
+	if (color == EC_LED_COLOR_BLUE) {
+		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
 		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_ON_LVL);
 	} else {
 		/* LED_OFF and unsupported colors */
@@ -74,17 +76,16 @@ __override void led_set_color_battery(enum ec_led_colors color)
 {
 	/* Don't set led if led_auto_control is disabled. */
 	if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) ||
-                !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
+	    !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
 		return;
-        }
+	}
 
 	/* Battery leds must be turn off when blue led is on
 	 * because casta has 3-in-1 led.
 	 */
-	if(!gpio_get_level(GPIO_PWR_LED_BLUE_L))
-	{
+	if (!gpio_get_level(GPIO_PWR_LED_BLUE_L)) {
 		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); /*red*/
-                gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); /*green*/
+		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); /*green*/
 		return;
 	}
 
@@ -118,10 +119,13 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 {
 	if (led_id == EC_LED_ID_BATTERY_LED) {
 		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, !brightness[EC_LED_COLOR_GREEN]);
-		gpio_set_level(GPIO_BAT_LED_RED_L, !brightness[EC_LED_COLOR_RED]);
+		gpio_set_level(GPIO_BAT_LED_GREEN_L,
+			       !brightness[EC_LED_COLOR_GREEN]);
+		gpio_set_level(GPIO_BAT_LED_RED_L,
+			       !brightness[EC_LED_COLOR_RED]);
 	} else if (led_id == EC_LED_ID_POWER_LED) {
-		gpio_set_level(GPIO_PWR_LED_BLUE_L, !brightness[EC_LED_COLOR_BLUE]);
+		gpio_set_level(GPIO_PWR_LED_BLUE_L,
+			       !brightness[EC_LED_COLOR_BLUE]);
 		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
 		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
 	}
diff --git a/board/cerise/battery.c b/board/cerise/battery.c
index 50d2bf397c..9edab52867 100644
--- a/board/cerise/battery.c
+++ b/board/cerise/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/cerise/board.c b/board/cerise/board.c
index 61722dd530..e3fa60c76a 100644
--- a/board/cerise/board.c
+++ b/board/cerise/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -30,6 +30,7 @@
 #include "it8801.h"
 #include "keyboard_scan.h"
 #include "lid_switch.h"
+#include "panic.h"
 #include "power.h"
 #include "power_button.h"
 #include "pwm.h"
@@ -46,8 +47,8 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
@@ -59,40 +60,34 @@ static void tcpc_alert_event(enum gpio_signal signal)
 /******************************************************************************/
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] =  {"BOARD_ID",  3300, 4096, 0, STM32_AIN(10)},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)},
+	[ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(10) },
+	[ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /******************************************************************************/
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "typec",
-		.port = 0,
-		.kbps = 400,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	},
-	{
-		.name = "other",
-		.port = 1,
-		.kbps = 100,
-		.scl  = GPIO_I2C2_SCL,
-		.sda  = GPIO_I2C2_SDA
-	},
+	{ .name = "typec",
+	  .port = 0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "other",
+	  .port = 1,
+	  .kbps = 100,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
 const struct i2c_port_t i2c_bitbang_ports[] = {
-	{
-		.name = "battery",
-		.port = 2,
-		.kbps = 100,
-		.scl  = GPIO_I2C3_SCL,
-		.sda  = GPIO_I2C3_SDA,
-		.drv  = &bitbang_drv
-	},
+	{ .name = "battery",
+	  .port = 2,
+	  .kbps = 100,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA,
+	  .drv = &bitbang_drv },
 };
 const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
 
@@ -100,8 +95,8 @@ const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
 
 /* power signal list.  Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
+	{ GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" },
+	{ GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" },
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
@@ -157,8 +152,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-static void board_hpd_status(const struct usb_mux *me,
-			     mux_state_t mux_state,
+static void board_hpd_status(const struct usb_mux *me, mux_state_t mux_state,
 			     bool *ack_required)
 {
 	/* This driver does not use host command ACKs */
@@ -171,13 +165,16 @@ static void board_hpd_status(const struct usb_mux *me,
 	host_set_single_event(EC_HOST_EVENT_USB_MUX);
 }
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+				.hpd_update = &board_hpd_status,
+			},
 	},
 };
 
@@ -239,12 +236,12 @@ int board_set_active_charge_port(int charge_port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-			       CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 int board_discharge_on_ac(int enable)
@@ -301,8 +298,7 @@ static void board_spi_enable(void)
 	/* Pin mux spi peripheral toward the sensor. */
 	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
 }
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP,
-	     board_spi_enable,
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_spi_enable,
 	     MOTION_SENSE_HOOK_PRIO - 1);
 
 static void board_spi_disable(void)
@@ -316,8 +312,7 @@ static void board_spi_disable(void)
 	spi_enable(&spi_devices[0], 0);
 	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
 }
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN,
-	     board_spi_disable,
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_spi_disable,
 	     MOTION_SENSE_HOOK_PRIO + 1);
 #endif /* !VARIANT_KUKUI_NO_SENSORS */
 
@@ -359,17 +354,13 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Rotation matrixes */
-static const mat33_fp_t base_standard_ref = {
-	{0, FLOAT_TO_FP(-1), 0},
-	{FLOAT_TO_FP(-1), 0, 0},
-	{0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+					      { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
 
-static const mat33_fp_t lid_standard_ref = {
-	{0, FLOAT_TO_FP(1), 0},
-	{FLOAT_TO_FP(1), 0, 0},
-	{0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					     { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
 /* sensor private data */
 /* Lid accel private data */
diff --git a/board/cerise/board.h b/board/cerise/board.h
index 1cb8cd9266..41d86b956d 100644
--- a/board/cerise/board.h
+++ b/board/cerise/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -56,7 +56,7 @@
 
 /* Motion Sensors */
 #ifndef VARIANT_KUKUI_NO_SENSORS
-#define CONFIG_ACCEL_LIS2DWL    /* Lid accel */
+#define CONFIG_ACCEL_LIS2DWL /* Lid accel */
 #define CONFIG_ACCELGYRO_BMI160 /* Base accel */
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
@@ -72,20 +72,20 @@
 #endif /* VARIANT_KUKUI_NO_SENSORS */
 
 /* I2C ports */
-#define I2C_PORT_BC12               0
-#define I2C_PORT_TCPC0              0
-#define I2C_PORT_USB_MUX            0
-#define I2C_PORT_BATTERY            2
-#define I2C_PORT_CHARGER            board_get_charger_i2c()
-#define I2C_PORT_SENSORS            1
-#define I2C_PORT_KB_DISCRETE        1
-#define I2C_PORT_VIRTUAL_BATTERY    I2C_PORT_BATTERY
+#define I2C_PORT_BC12 0
+#define I2C_PORT_TCPC0 0
+#define I2C_PORT_USB_MUX 0
+#define I2C_PORT_BATTERY 2
+#define I2C_PORT_CHARGER board_get_charger_i2c()
+#define I2C_PORT_SENSORS 1
+#define I2C_PORT_KB_DISCRETE 1
+#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
 
 /* IT8801 I2C address */
-#define KB_DISCRETE_I2C_ADDR_FLAGS  IT8801_I2C_ADDR1
+#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1
 
 /* Enable Accel over SPI */
-#define CONFIG_SPI_ACCEL_PORT    0  /* The first SPI controller port (SPI2) */
+#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */
 
 #define CONFIG_KEYBOARD_PROTOCOL_MKBP
 #define CONFIG_MKBP_EVENT
diff --git a/board/cerise/build.mk b/board/cerise/build.mk
index a6e1c010d7..f583684804 100644
--- a/board/cerise/build.mk
+++ b/board/cerise/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/cerise/ec.tasklist b/board/cerise/ec.tasklist
index 36be2e96a4..e77603a8e2 100644
--- a/board/cerise/ec.tasklist
+++ b/board/cerise/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/cerise/gpio.inc b/board/cerise/gpio.inc
index d7d5b9837d..6edf1f1eab 100644
--- a/board/cerise/gpio.inc
+++ b/board/cerise/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/cerise/led.c b/board/cerise/led.c
index 53bec5bf05..81203ba331 100644
--- a/board/cerise/led.c
+++ b/board/cerise/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,25 +19,32 @@ __override const int led_charge_lvl_1 = 5;
 __override const int led_charge_lvl_2 = 95;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]         = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]         = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF, 3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF, 3 * LED_ONE_SEC} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF, 1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_WHITE,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 __override void led_set_color_battery(enum ec_led_colors color)
diff --git a/board/cherry/battery.c b/board/cherry/battery.c
index 72daf4966d..4f3a12e43d 100644
--- a/board/cherry/battery.c
+++ b/board/cherry/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/cherry/board.c b/board/cherry/board.c
index 69828d19b5..c2ad54acb2 100644
--- a/board/cherry/board.c
+++ b/board/cherry/board.c
@@ -1,9 +1,11 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 /* Cherry board configuration */
 
+#include "charge_manager.h"
+#include "charge_state_v2.h"
 #include "common.h"
 #include "console.h"
 #include "driver/accel_bma422.h"
@@ -21,8 +23,8 @@
 #include "system.h"
 #include "usb_mux.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* Sensor */
 static struct mutex g_base_mutex;
@@ -33,17 +35,13 @@ static struct kionix_accel_data g_kx022_data;
 static struct accelgyro_saved_data_t g_bma422_data;
 
 /* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					      { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
 
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	/*
@@ -199,8 +197,7 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
 /* USB Mux */
 
-static int board_ps8762_mux_set(const struct usb_mux *me,
-				mux_state_t mux_state)
+static int board_ps8762_mux_set(const struct usb_mux *me, mux_state_t mux_state)
 {
 	/* Make sure the PS8802 is awake */
 	RETURN_ERROR(ps8802_i2c_wake(me));
@@ -208,21 +205,18 @@ static int board_ps8762_mux_set(const struct usb_mux *me,
 	/* USB specific config */
 	if (mux_state & USB_PD_MUX_USB_ENABLED) {
 		/* Boost the USB gain */
-		RETURN_ERROR(ps8802_i2c_field_update16(me,
-					PS8802_REG_PAGE2,
-					PS8802_REG2_USB_SSEQ_LEVEL,
-					PS8802_USBEQ_LEVEL_UP_MASK,
-					PS8802_USBEQ_LEVEL_UP_12DB));
+		RETURN_ERROR(ps8802_i2c_field_update16(
+			me, PS8802_REG_PAGE2, PS8802_REG2_USB_SSEQ_LEVEL,
+			PS8802_USBEQ_LEVEL_UP_MASK,
+			PS8802_USBEQ_LEVEL_UP_12DB));
 	}
 
 	/* DP specific config */
 	if (mux_state & USB_PD_MUX_DP_ENABLED) {
 		/* Boost the DP gain */
-		RETURN_ERROR(ps8802_i2c_field_update8(me,
-					PS8802_REG_PAGE2,
-					PS8802_REG2_DPEQ_LEVEL,
-					PS8802_DPEQ_LEVEL_UP_MASK,
-					PS8802_DPEQ_LEVEL_UP_12DB));
+		RETURN_ERROR(ps8802_i2c_field_update8(
+			me, PS8802_REG_PAGE2, PS8802_REG2_DPEQ_LEVEL,
+			PS8802_DPEQ_LEVEL_UP_MASK, PS8802_DPEQ_LEVEL_UP_12DB));
 	}
 
 	return EC_SUCCESS;
@@ -230,11 +224,10 @@ static int board_ps8762_mux_set(const struct usb_mux *me,
 
 static int board_ps8762_mux_init(const struct usb_mux *me)
 {
-	return ps8802_i2c_field_update8(
-			me, PS8802_REG_PAGE1,
-			PS8802_REG_DCIRX,
-			PS8802_AUTO_DCI_MODE_DISABLE | PS8802_FORCE_DCI_MODE,
-			PS8802_AUTO_DCI_MODE_DISABLE);
+	return ps8802_i2c_field_update8(me, PS8802_REG_PAGE1, PS8802_REG_DCIRX,
+					PS8802_AUTO_DCI_MODE_DISABLE |
+						PS8802_FORCE_DCI_MODE,
+					PS8802_AUTO_DCI_MODE_DISABLE);
 }
 
 static int board_anx3443_mux_set(const struct usb_mux *me,
@@ -245,24 +238,37 @@ static int board_anx3443_mux_set(const struct usb_mux *me,
 	return EC_SUCCESS;
 }
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX0,
-		.i2c_addr_flags = PS8802_I2C_ADDR_FLAGS,
-		.driver = &ps8802_usb_mux_driver,
-		.board_init = &board_ps8762_mux_init,
-		.board_set = &board_ps8762_mux_set,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX0,
+				.i2c_addr_flags = PS8802_I2C_ADDR_FLAGS,
+				.driver = &ps8802_usb_mux_driver,
+				.board_init = &board_ps8762_mux_init,
+				.board_set = &board_ps8762_mux_set,
+			},
 	},
 	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_USB_MUX1,
-		.i2c_addr_flags = ANX3443_I2C_ADDR0_FLAGS,
-		.driver = &anx3443_usb_mux_driver,
-		.board_set = &board_anx3443_mux_set,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_USB_MUX1,
+				.i2c_addr_flags = ANX3443_I2C_ADDR0_FLAGS,
+				.driver = &anx3443_usb_mux_driver,
+				.board_set = &board_anx3443_mux_set,
+			},
 	},
 };
 
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
+{
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+}
+
 /* Initialize board. */
 static void board_init(void)
 {
diff --git a/board/cherry/board.h b/board/cherry/board.h
index 73f7d4044d..c94f862ede 100644
--- a/board/cherry/board.h
+++ b/board/cherry/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,14 +26,15 @@
 #define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
 
 /* PD / USB-C / PPC */
-#undef CONFIG_USB_PD_DEBUG_LEVEL /* default to 1, configurable in ec console */
+#undef CONFIG_USB_PD_DEBUG_LEVEL /* default to 1, configurable in ec console \
+				  */
 
 /* Optional console commands */
 #define CONFIG_CMD_FLASH
 #define CONFIG_CMD_SCRATCHPAD
 #define CONFIG_CMD_STACKOVERFLOW
 
-#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV	9000
+#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV 9000
 
 /* Keyboard */
 #define CONFIG_KEYBOARD_REFRESH_ROW3
diff --git a/board/cherry/build.mk b/board/cherry/build.mk
index 0b0569c6d8..998e4d2750 100644
--- a/board/cherry/build.mk
+++ b/board/cherry/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/cherry/ec.tasklist b/board/cherry/ec.tasklist
index f9050fef87..5ce0fab583 100644
--- a/board/cherry/ec.tasklist
+++ b/board/cherry/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/cherry/gpio.inc b/board/cherry/gpio.inc
index 296e3a418e..b953b16b27 100644
--- a/board/cherry/gpio.inc
+++ b/board/cherry/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/cherry/led.c b/board/cherry/led.c
index c177a1b48f..0607301d4c 100644
--- a/board/cherry/led.c
+++ b/board/cherry/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,28 +10,37 @@
 #include "led_onoff_states.h"
 #include "pwm.h"
 
-#define LED_OFF_LVL	0
-#define LED_ON_LVL	1
+#define LED_OFF_LVL 0
+#define LED_ON_LVL 1
 
 __override const int led_charge_lvl_1 = 5;
 __override const int led_charge_lvl_2 = 95;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_S5]     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,           3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_S5] = { { EC_LED_COLOR_BLUE,
+					       LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
 const enum ec_led_id supported_led_ids[] = {
 	EC_LED_ID_BATTERY_LED,
diff --git a/board/cherry_scp/board.h b/board/cherry_scp/board.h
index dcf7f09a6f..0f6d006a44 100644
--- a/board/cherry_scp/board.h
+++ b/board/cherry_scp/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,8 +25,8 @@
 #define CONFIG_ROM_BASE 0x0
 #define CONFIG_RAM_BASE 0x68000
 #define CONFIG_ROM_SIZE (CONFIG_RAM_BASE - CONFIG_ROM_BASE)
-#define CONFIG_RAM_SIZE ((CONFIG_IPC_SHARED_OBJ_ADDR & (~(0x400 - 1))) - \
-			 CONFIG_RAM_BASE)
+#define CONFIG_RAM_SIZE \
+	((CONFIG_IPC_SHARED_OBJ_ADDR & (~(0x400 - 1))) - CONFIG_RAM_BASE)
 
 #define SCP_FW_END 0xc0000
 
diff --git a/board/cherry_scp/build.mk b/board/cherry_scp/build.mk
index 0d6c33755f..498bee2848 100644
--- a/board/cherry_scp/build.mk
+++ b/board/cherry_scp/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/cherry_scp/ec.tasklist b/board/cherry_scp/ec.tasklist
index 1c8cd120a0..353e5ee686 100644
--- a/board/cherry_scp/ec.tasklist
+++ b/board/cherry_scp/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/cherry_scp/gpio.inc b/board/cherry_scp/gpio.inc
index 48b397b9a9..8301fb437f 100644
--- a/board/cherry_scp/gpio.inc
+++ b/board/cherry_scp/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/chocodile_vpdmcu/board.c b/board/chocodile_vpdmcu/board.c
index b3e49fc547..a64da1633e 100644
--- a/board/chocodile_vpdmcu/board.c
+++ b/board/chocodile_vpdmcu/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,7 +20,7 @@
 #include "util.h"
 #include "vpd_api.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
 
 void board_config_pre_init(void)
 {
@@ -40,26 +40,26 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* USB PD CC lines sensing. Converted to mV (3300mV/4096). */
-	[ADC_VCONN_VSENSE] =  {
-	"VCONN_VSENSE",  3000, 4096, 0, STM32_AIN(ADC_VCONN_VSENSE)},
-	[ADC_CC_VPDMCU] =     {
-	"CC_VPDMCU",     3000, 4096, 0, STM32_AIN(ADC_CC_VPDMCU)},
-	[ADC_CC_RP3A0_RD_L] = {
-	"CC_RP3A0_RD_L", 3000, 4096, 0, STM32_AIN(ADC_CC_RP3A0_RD_L)},
-	[ADC_RDCONNECT_REF] = {
-	"RDCONNECT_REF", 3000, 4096, 0, STM32_AIN(ADC_RDCONNECT_REF)},
-	[ADC_CC1_RP3A0_RD_L] = {
-	"CC1_RP1A5_ODH", 3000, 4096, 0, STM32_AIN(ADC_CC1_RP3A0_RD_L)},
-	[ADC_CC2_RP3A0_RD_L] = {
-	"CC2_RP1A5_ODH", 3000, 4096, 0, STM32_AIN(ADC_CC2_RP3A0_RD_L)},
-	[ADC_HOST_VBUS_VSENSE] = {
-	"HOST_VBUS_VSENSE", 3000, 4096, 0, STM32_AIN(ADC_HOST_VBUS_VSENSE)},
-	[ADC_CHARGE_VBUS_VSENSE] = {
-	"CHARGE_VBUS_VSENSE", 3000, 4096, 0, STM32_AIN(ADC_CHARGE_VBUS_VSENSE)},
-	[ADC_CC1_RPUSB_ODH] = {
-	"CC1_RPUSB_ODH", 3000, 4096, 0, STM32_AIN(ADC_CC1_RPUSB_ODH)},
-	[ADC_CC2_RPUSB_ODH] = {
-	"CC2_RPUSB_ODH", 3000, 4096, 0, STM32_AIN(ADC_CC2_RPUSB_ODH)},
+	[ADC_VCONN_VSENSE] = { "VCONN_VSENSE", 3000, 4096, 0,
+			       STM32_AIN(ADC_VCONN_VSENSE) },
+	[ADC_CC_VPDMCU] = { "CC_VPDMCU", 3000, 4096, 0,
+			    STM32_AIN(ADC_CC_VPDMCU) },
+	[ADC_CC_RP3A0_RD_L] = { "CC_RP3A0_RD_L", 3000, 4096, 0,
+				STM32_AIN(ADC_CC_RP3A0_RD_L) },
+	[ADC_RDCONNECT_REF] = { "RDCONNECT_REF", 3000, 4096, 0,
+				STM32_AIN(ADC_RDCONNECT_REF) },
+	[ADC_CC1_RP3A0_RD_L] = { "CC1_RP1A5_ODH", 3000, 4096, 0,
+				 STM32_AIN(ADC_CC1_RP3A0_RD_L) },
+	[ADC_CC2_RP3A0_RD_L] = { "CC2_RP1A5_ODH", 3000, 4096, 0,
+				 STM32_AIN(ADC_CC2_RP3A0_RD_L) },
+	[ADC_HOST_VBUS_VSENSE] = { "HOST_VBUS_VSENSE", 3000, 4096, 0,
+				   STM32_AIN(ADC_HOST_VBUS_VSENSE) },
+	[ADC_CHARGE_VBUS_VSENSE] = { "CHARGE_VBUS_VSENSE", 3000, 4096, 0,
+				     STM32_AIN(ADC_CHARGE_VBUS_VSENSE) },
+	[ADC_CC1_RPUSB_ODH] = { "CC1_RPUSB_ODH", 3000, 4096, 0,
+				STM32_AIN(ADC_CC1_RPUSB_ODH) },
+	[ADC_CC2_RPUSB_ODH] = { "CC2_RPUSB_ODH", 3000, 4096, 0,
+				STM32_AIN(ADC_CC2_RPUSB_ODH) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
diff --git a/board/chocodile_vpdmcu/board.h b/board/chocodile_vpdmcu/board.h
index 552f00aa09..ede07dd9a0 100644
--- a/board/chocodile_vpdmcu/board.h
+++ b/board/chocodile_vpdmcu/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -34,7 +34,7 @@
 #define CPU_CLOCK 48000000
 
 /* the UART console is on USART1 (PA9/PA10) */
-#undef  CONFIG_UART_CONSOLE
+#undef CONFIG_UART_CONSOLE
 #define CONFIG_UART_CONSOLE 1
 
 /* Optional features */
@@ -43,23 +43,23 @@
 #undef CONFIG_CMD_PD
 #undef CONFIG_USBC_VCONN
 #define CONFIG_ADC
-#undef  CONFIG_ADC_WATCHDOG
+#undef CONFIG_ADC_WATCHDOG
 #define CONFIG_ADC_SAMPLE_TIME STM32_ADC_SMPR_41_5_CY
 #define CONFIG_BOARD_PRE_INIT
 #define CONFIG_COMMON_GPIO_SHORTNAMES
-#undef  CONFIG_DEBUG_ASSERT
+#undef CONFIG_DEBUG_ASSERT
 #define CONFIG_FORCE_CONSOLE_RESUME
 #define CONFIG_HIBERNATE
-#undef  CONFIG_HOSTCMD_EVENTS
+#undef CONFIG_HOSTCMD_EVENTS
 #define CONFIG_HW_CRC
-#undef  CONFIG_LID_SWITCH
+#undef CONFIG_LID_SWITCH
 #define CONFIG_LOW_POWER_IDLE
 #define CONFIG_LTO
 #define CONFIG_STM_HWTIMER32
-#undef  CONFIG_TASK_PROFILING
-#undef  CONFIG_UART_TX_BUF_SIZE
-#undef  CONFIG_UART_TX_DMA
-#undef  CONFIG_UART_RX_DMA
+#undef CONFIG_TASK_PROFILING
+#undef CONFIG_UART_TX_BUF_SIZE
+#undef CONFIG_UART_TX_DMA
+#undef CONFIG_UART_RX_DMA
 #define CONFIG_UART_TX_BUF_SIZE 128
 #define CONFIG_USB_PD_PORT_MAX_COUNT 1
 #define CONFIG_USB_PD_TCPC
@@ -74,7 +74,7 @@
 #define CONFIG_USB_PD_INTERNAL_COMP
 #define CONFIG_VBOOT_HASH
 #define CONFIG_WATCHDOG
-#undef  CONFIG_WATCHDOG_HELP
+#undef CONFIG_WATCHDOG_HELP
 
 #define CONFIG_USB_PID 0x5036
 #define VPD_HW_VERSION 0x0001
@@ -92,10 +92,10 @@
 /* GND impedance in milliohms */
 #define VPD_GND_IMPEDANCE 33
 
-#define PD_OPERATING_POWER_MW           15000
-#define PD_MAX_POWER_MW                 45000
-#define PD_MAX_CURRENT_MA               3000
-#define PD_MAX_VOLTAGE_MV               20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 45000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 /*
  * TODO(crosbug.com/p/50519): Remove CONFIG_SYSTEM_UNLOCKED prior to building
  * MP FW.
@@ -103,19 +103,19 @@
 #define CONFIG_SYSTEM_UNLOCKED
 
 #ifdef HAS_TASK_CONSOLE
-#undef  CONFIG_CONSOLE_HISTORY
+#undef CONFIG_CONSOLE_HISTORY
 #define CONFIG_CONSOLE_HISTORY 2
 
 #else
-#undef  CONFIG_CONSOLE_CMDHELP
+#undef CONFIG_CONSOLE_CMDHELP
 #define CONFIG_DEBUG_PRINTF
 #define UARTN CONFIG_UART_CONSOLE
 #define UARTN_BASE STM32_USART_BASE(CONFIG_UART_CONSOLE)
 #endif /* HAS_TASK_CONSOLE */
 
 /* Use PSTATE embedded in the RO image, not in its own erase block */
-#undef  CONFIG_FLASH_PSTATE_BANK
-#undef  CONFIG_FW_PSTATE_SIZE
+#undef CONFIG_FLASH_PSTATE_BANK
+#undef CONFIG_FW_PSTATE_SIZE
 #define CONFIG_FW_PSTATE_SIZE 0
 
 /* Include math_util for bitmask_uint64 used in pd_timers */
@@ -125,7 +125,7 @@
 
 /* Timer selection */
 #define TIM_CLOCK32 2
-#define TIM_ADC     3
+#define TIM_ADC 3
 
 #include "gpio_signal.h"
 
@@ -146,8 +146,8 @@ enum adc_channel {
 };
 
 /* 1.5A Rp */
-#define PD_SRC_VNC            PD_SRC_1_5_VNC_MV
-#define PD_SRC_RD_THRESHOLD   PD_SRC_1_5_RD_THRESH_MV
+#define PD_SRC_VNC PD_SRC_1_5_VNC_MV
+#define PD_SRC_RD_THRESHOLD PD_SRC_1_5_RD_THRESH_MV
 
 #endif /* !__ASSEMBLER__ */
 
diff --git a/board/chocodile_vpdmcu/build.mk b/board/chocodile_vpdmcu/build.mk
index d4e5f58962..21c257bd7e 100644
--- a/board/chocodile_vpdmcu/build.mk
+++ b/board/chocodile_vpdmcu/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/chocodile_vpdmcu/chocodile.html b/board/chocodile_vpdmcu/chocodile.html
index b38edf94ec..6aec670f2a 100644
--- a/board/chocodile_vpdmcu/chocodile.html
+++ b/board/chocodile_vpdmcu/chocodile.html
@@ -866,7 +866,7 @@ th.expander input {
 <text stroke="none" x="4750" y="-25" font-size="40" text-anchor="middle">10</text>
 <text stroke="none" x="250" y="-25" font-size="40" text-anchor="middle">1</text>
 <text stroke="none" x="38" y="-250" font-size="40" text-anchor="middle">A</text>
-<text stroke="none" x="99" y="-97" font-size="24">FOLLOWING NOTICE SHALL APPLY: &nbsp;COPYRIGHT C 2009 GOOGLE, INC. &nbsp;ALL RIGHTS RESERVED.</text>
+<text stroke="none" x="99" y="-97" font-size="24">FOLLOWING NOTICE SHALL APPLY: &nbsp;COPYRIGHT 2009 GOOGLE LLC</text>
 <text stroke="none" x="38" y="-3750" font-size="40" text-anchor="middle">H</text>
 <text stroke="none" x="5750" y="-25" font-size="40" text-anchor="middle">12</text>
 <text stroke="none" x="92" y="-200" font-size="24">THESE MATERIALS (INCLUDING ALL TEXT, SOFTWARE,CODE, DISPLAYS, ARTWORK, AND IMAGES) CONTAIN TRADE SECRETS AND CONFIDENTIAL INFORMATION WHICH ARE PROPRIETARY TO GOOGLE, INC. &nbsp;ANY USE, REPRODUCTION, DISTRIBUTION,</text>
diff --git a/board/chocodile_vpdmcu/ec.tasklist b/board/chocodile_vpdmcu/ec.tasklist
index 6753502b92..ecbd3b052c 100644
--- a/board/chocodile_vpdmcu/ec.tasklist
+++ b/board/chocodile_vpdmcu/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/chocodile_vpdmcu/gpio.inc b/board/chocodile_vpdmcu/gpio.inc
index a34c617ef1..060054f719 100644
--- a/board/chocodile_vpdmcu/gpio.inc
+++ b/board/chocodile_vpdmcu/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/chocodile_vpdmcu/usb_pd_config.h b/board/chocodile_vpdmcu/usb_pd_config.h
index 048bbf3988..7fe608eb2a 100644
--- a/board/chocodile_vpdmcu/usb_pd_config.h
+++ b/board/chocodile_vpdmcu/usb_pd_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -55,7 +55,7 @@ static inline void spi_enable_clock(int port)
 
 #define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
 #define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
-#define TIM_CCR_CS  1
+#define TIM_CCR_CS 1
 
 /* EXTI line 21 is connected to the CMP1 output */
 #define EXTI_COMP1_MASK (1 << 21)
@@ -95,13 +95,15 @@ static inline void pd_tx_spi_reset(int port)
 static inline void pd_tx_enable(int port, int polarity)
 {
 	/* USB_CC_TX_DATA: PB4 is SPI1 MISO */
-	STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B)
-			& ~(3 << (2*4))) /* PB4 disable ADC */
-			|  (2 << (2*4)); /* Set as SPI1_MISO */
+	STM32_GPIO_MODER(GPIO_B) =
+		(STM32_GPIO_MODER(GPIO_B) & ~(3 << (2 * 4))) /* PB4 disable ADC
+							      */
+		| (2 << (2 * 4)); /* Set as SPI1_MISO */
 	/* MCU ADC PA1 pin output low */
-	STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
-			& ~(3 << (2*1))) /* PA1 disable ADC */
-			|  (1 << (2*1)); /* Set as GPO */
+	STM32_GPIO_MODER(GPIO_A) =
+		(STM32_GPIO_MODER(GPIO_A) & ~(3 << (2 * 1))) /* PA1 disable ADC
+							      */
+		| (1 << (2 * 1)); /* Set as GPO */
 	gpio_set_level(GPIO_CC_VPDMCU, 0);
 }
 
@@ -109,11 +111,10 @@ static inline void pd_tx_enable(int port, int polarity)
 static inline void pd_tx_disable(int port, int polarity)
 {
 	/* Set CC_TX_DATA to Hi-Z, PB4 is SPI1 MISO */
-	STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B)
-			& ~(3 << (2*4)));
+	STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B) & ~(3 << (2 * 4)));
 	/* set ADC PA1 pin to ADC function (Hi-Z) */
-	STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
-			|  (3 << (2*1))); /* PA1 as ADC */
+	STM32_GPIO_MODER(GPIO_A) =
+		(STM32_GPIO_MODER(GPIO_A) | (3 << (2 * 1))); /* PA1 as ADC */
 }
 
 /* we know the plug polarity, do the right configuration */
@@ -123,8 +124,8 @@ static inline void pd_select_polarity(int port, int polarity)
 	 * use the right comparator : CC1 -> PA1 (COMP1 INP)
 	 * use VrefInt / 2 as INM (about 600mV)
 	 */
-	STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK)
-		| STM32_COMP_CMP1EN | STM32_COMP_CMP1INSEL_VREF12;
+	STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK) |
+			 STM32_COMP_CMP1EN | STM32_COMP_CMP1INSEL_VREF12;
 }
 
 /* Initialize pins used for TX and put them in Hi-Z */
diff --git a/board/chocodile_vpdmcu/vpd_api.c b/board/chocodile_vpdmcu/vpd_api.c
index cdd2d9776d..fdfdf47efc 100644
--- a/board/chocodile_vpdmcu/vpd_api.c
+++ b/board/chocodile_vpdmcu/vpd_api.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -35,7 +35,7 @@
 #endif
 
 #undef CC_RA
-#define CC_RA(cc, sel)  (cc < pd_src_rd_threshold[sel])
+#define CC_RA(cc, sel) (cc < pd_src_rd_threshold[sel])
 #undef CC_RD
 #define CC_RD(cc, sel) ((cc >= pd_src_rd_threshold[sel]) && (cc < PD_SRC_VNC))
 
@@ -47,16 +47,16 @@
 #define VBUS_DETECT_THRESHOLD 2500 /* mV */
 #define VCONN_DETECT_THRESHOLD 2500 /* mV */
 
-#define SCALE(vmeas, sfactor) (((vmeas) * 1000) / (sfactor))
+#define SCALE(vmeas, sfactor) (((vmeas)*1000) / (sfactor))
 
 /*
  * Type C power source charge current limits are identified by their cc
  * voltage (set by selecting the proper Rd resistor). Any voltage below
  * TYPE_C_SRC_500_THRESHOLD will not be identified as a type C charger.
  */
-#define TYPE_C_SRC_DEFAULT_THRESHOLD    200  /* mV */
-#define TYPE_C_SRC_1500_THRESHOLD       660  /* mV */
-#define TYPE_C_SRC_3000_THRESHOLD       1230 /* mV */
+#define TYPE_C_SRC_DEFAULT_THRESHOLD 200 /* mV */
+#define TYPE_C_SRC_1500_THRESHOLD 660 /* mV */
+#define TYPE_C_SRC_3000_THRESHOLD 1230 /* mV */
 
 /* Charge-Through pull up/down enabled */
 static int ct_cc_pull;
@@ -86,7 +86,7 @@ static int vpd_cc_voltage_to_status(int cc_volt, int cc_pull)
 			return TYPEC_CC_VOLT_RA;
 		else
 			return TYPEC_CC_VOLT_OPEN;
-	/* If we have a pull-down, then we are sink, check for Rp. */
+		/* If we have a pull-down, then we are sink, check for Rp. */
 	} else if (cc_pull == TYPEC_CC_RD || cc_pull == TYPEC_CC_RA_RD) {
 		if (cc_volt >= TYPE_C_SRC_3000_THRESHOLD)
 			return TYPEC_CC_VOLT_RP_3_0;
@@ -218,8 +218,8 @@ void vpd_host_set_pull(int pull, int rp_value)
 
 void vpd_host_get_cc(int *cc)
 {
-	*cc = vpd_cc_voltage_to_status(
-		adc_read_channel(ADC_CC_VPDMCU), host_cc_pull);
+	*cc = vpd_cc_voltage_to_status(adc_read_channel(ADC_CC_VPDMCU),
+				       host_cc_pull);
 }
 
 void vpd_rx_enable(int en)
@@ -237,17 +237,23 @@ void vpd_config_cc_rp3a0_rd_l(enum vpd_pin cfg, int en)
 		gpio_set_level(GPIO_CC_RP3A0_RD_L, en ? 1 : 0);
 
 		/* Disable Analog mode and Enable GPO */
-		STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
-				& ~(3 << (2*2))) /* PA2 disable ADC */
-				|  (1 << (2*2)); /* Set as GPO */
+		STM32_GPIO_MODER(GPIO_A) =
+			(STM32_GPIO_MODER(GPIO_A) & ~(3 << (2 * 2))) /* PA2
+									disable
+									ADC */
+			| (1 << (2 * 2)); /* Set as GPO */
 	} else {
 		/* Set PA2 pin to ANALOG function */
-		STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
-				|  (3 << (2*2))); /* PA2 in ANALOG mode */
+		STM32_GPIO_MODER(GPIO_A) =
+			(STM32_GPIO_MODER(GPIO_A) | (3 << (2 * 2))); /* PA2 in
+									ANALOG
+									mode */
 
 		/* Set PA3 pin to ANALOG function */
-		STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
-				|  (3 << (2*3))); /* PA3 in ANALOG mode */
+		STM32_GPIO_MODER(GPIO_A) =
+			(STM32_GPIO_MODER(GPIO_A) | (3 << (2 * 3))); /* PA3 in
+									ANALOG
+									mode */
 
 		/* Disable Window Mode. Select PA3 */
 		STM32_COMP_CSR &= ~STM32_COMP_WNDWEN;
@@ -276,9 +282,11 @@ void vpd_config_cc1_rp3a0_rd_l(enum vpd_pin cfg, int en)
 		gpio_set_level(GPIO_CC1_RP3A0_RD_L, en ? 1 : 0);
 
 		/* Disable Analog mode and Enable GPO */
-		STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
-				& ~(3 << (2*4))) /* PA4 disable ADC */
-				|  (1 << (2*4)); /* Set as GPO */
+		STM32_GPIO_MODER(GPIO_A) =
+			(STM32_GPIO_MODER(GPIO_A) & ~(3 << (2 * 4))) /* PA4
+									disable
+									ADC */
+			| (1 << (2 * 4)); /* Set as GPO */
 	}
 
 	if (cfg == PIN_ADC || cfg == PIN_CMP) {
@@ -286,13 +294,17 @@ void vpd_config_cc1_rp3a0_rd_l(enum vpd_pin cfg, int en)
 		STM32_COMP_CSR &= ~STM32_COMP_CMP2EN;
 
 		/* Set PA4 pin to Analog mode */
-		STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
-				|  (3 << (2*4))); /* PA4 in ANALOG mode */
+		STM32_GPIO_MODER(GPIO_A) =
+			(STM32_GPIO_MODER(GPIO_A) | (3 << (2 * 4))); /* PA4 in
+									ANALOG
+									mode */
 
 		if (cfg == PIN_CMP) {
 			/* Set PA3 pin to ANALOG function */
-			STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
-				|  (3 << (2*3))); /* PA3 in ANALOG mode */
+			STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) |
+						    (3 << (2 * 3))); /* PA3 in
+									ANALOG
+									mode */
 
 			/* Disable Window Mode. Select PA3*/
 			STM32_COMP_CSR &= ~STM32_COMP_WNDWEN;
@@ -319,9 +331,11 @@ void vpd_config_cc2_rp3a0_rd_l(enum vpd_pin cfg, int en)
 		gpio_set_level(GPIO_CC2_RP3A0_RD_L, en ? 1 : 0);
 
 		/* Disable Analog mode and Enable GPO */
-		STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
-				& ~(3 << (2*5))) /* PA5 disable ADC */
-				|  (1 << (2*5)); /* Set as GPO */
+		STM32_GPIO_MODER(GPIO_A) =
+			(STM32_GPIO_MODER(GPIO_A) & ~(3 << (2 * 5))) /* PA5
+									disable
+									ADC */
+			| (1 << (2 * 5)); /* Set as GPO */
 	}
 
 	if (cfg == PIN_ADC || cfg == PIN_CMP) {
@@ -329,13 +343,17 @@ void vpd_config_cc2_rp3a0_rd_l(enum vpd_pin cfg, int en)
 		STM32_COMP_CSR &= ~STM32_COMP_CMP2EN;
 
 		/* Set PA5 pin to ANALOG function */
-		STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
-				|  (3 << (2*5))); /* PA5 in ANALOG mode */
+		STM32_GPIO_MODER(GPIO_A) =
+			(STM32_GPIO_MODER(GPIO_A) | (3 << (2 * 5))); /* PA5 in
+									ANALOG
+									mode */
 
 		if (cfg == PIN_CMP) {
 			/* Set PA3 pin to ANALOG function */
-			STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
-				|  (3 << (2*3))); /* PA3 in ANALOG mode */
+			STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) |
+						    (3 << (2 * 3))); /* PA3 in
+									ANALOG
+									mode */
 
 			/* Disable Window Mode. */
 			STM32_COMP_CSR &= ~STM32_COMP_WNDWEN;
@@ -362,13 +380,17 @@ void vpd_config_cc1_rpusb_odh(enum vpd_pin cfg, int en)
 		gpio_set_level(GPIO_CC1_RPUSB_ODH, en ? 1 : 0);
 
 		/* Disable Analog mode and Enable GPO */
-		STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B)
-				& ~(3 << (2*0))) /* PB0 disable ADC */
-				|  (1 << (2*0)); /* Set as GPO */
+		STM32_GPIO_MODER(GPIO_B) =
+			(STM32_GPIO_MODER(GPIO_B) & ~(3 << (2 * 0))) /* PB0
+									disable
+									ADC */
+			| (1 << (2 * 0)); /* Set as GPO */
 	} else {
 		/* Enable Analog mode */
-		STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B)
-				|  (3 << (2*0))); /* PB0 in ANALOG mode */
+		STM32_GPIO_MODER(GPIO_B) =
+			(STM32_GPIO_MODER(GPIO_B) | (3 << (2 * 0))); /* PB0 in
+									ANALOG
+									mode */
 	}
 }
 
@@ -382,13 +404,17 @@ void vpd_config_cc2_rpusb_odh(enum vpd_pin cfg, int en)
 		gpio_set_level(GPIO_CC2_RPUSB_ODH, en ? 1 : 0);
 
 		/* Disable Analog mode and Enable GPO */
-		STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B)
-				& ~(3 << (2*1))) /* PB1 disable ADC */
-				|  (1 << (2*1)); /* Set as GPO */
+		STM32_GPIO_MODER(GPIO_B) =
+			(STM32_GPIO_MODER(GPIO_B) & ~(3 << (2 * 1))) /* PB1
+									disable
+									ADC */
+			| (1 << (2 * 1)); /* Set as GPO */
 	} else {
 		/* Enable Analog mode */
-		STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B)
-				|  (3 << (2*1))); /* PB1 in ANALOG mode */
+		STM32_GPIO_MODER(GPIO_B) =
+			(STM32_GPIO_MODER(GPIO_B) | (3 << (2 * 1))); /* PB1 in
+									ANALOG
+									mode */
 	}
 }
 
@@ -405,7 +431,7 @@ inline int vpd_read_host_vbus(void)
 inline int vpd_read_ct_vbus(void)
 {
 	return SCALE(adc_read_channel(ADC_CHARGE_VBUS_VSENSE),
-							VBUS_SCALE_FACTOR);
+		     VBUS_SCALE_FACTOR);
 }
 
 inline int vpd_read_vconn(void)
diff --git a/board/chocodile_vpdmcu/vpd_api.h b/board/chocodile_vpdmcu/vpd_api.h
index df50f92006..5d2fd24afb 100644
--- a/board/chocodile_vpdmcu/vpd_api.h
+++ b/board/chocodile_vpdmcu/vpd_api.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,34 +12,18 @@
 #include "gpio.h"
 #include "usb_pd.h"
 
-enum vpd_pin {
-	PIN_ADC,
-	PIN_CMP,
-	PIN_GPO
-};
+enum vpd_pin { PIN_ADC, PIN_CMP, PIN_GPO };
 
-enum vpd_gpo {
-	GPO_HZ,
-	GPO_HIGH,
-	GPO_LOW
-};
+enum vpd_gpo { GPO_HZ, GPO_HIGH, GPO_LOW };
 
 enum vpd_pwr {
 	PWR_VCONN,
 	PWR_VBUS,
 };
 
-enum vpd_cc {
-	CT_OPEN,
-	CT_CC1,
-	CT_CC2
-};
+enum vpd_cc { CT_OPEN, CT_CC1, CT_CC2 };
 
-enum vpd_billboard {
-	BB_NONE,
-	BB_SRC,
-	BB_SNK
-};
+enum vpd_billboard { BB_NONE, BB_SRC, BB_SNK };
 
 /**
  * Set Charge-Through Rp or Rd on CC lines
diff --git a/board/chronicler/battery.c b/board/chronicler/battery.c
index aee0095765..1d885607b7 100644
--- a/board/chronicler/battery.c
+++ b/board/chronicler/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/chronicler/board.c b/board/chronicler/board.c
index 5f7f717bca..40cefc714d 100644
--- a/board/chronicler/board.c
+++ b/board/chronicler/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -36,22 +36,22 @@
 
 #include "gpio_list.h" /* Must come after other header files. */
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 /******************************************************************************/
 /* Physical fans. These are logically separate from pwm_channels. */
 
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
 
 const struct fan_rpm fan_rpm_0 = {
-	.rpm_min   = 3000,
+	.rpm_min = 3000,
 	.rpm_start = 5000,
-	.rpm_max   = 5100,
+	.rpm_max = 5100,
 };
 
 const struct fan_t fans[FAN_CH_COUNT] = {
@@ -73,23 +73,23 @@ const struct fan_t fans[FAN_CH_COUNT] = {
  * TODO(b/202062363): Remove when clang is fixed.
  */
 #define THERMAL_CONFIG_WITHOUT_FAN \
-	{ \
+	{                          \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(77), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
 		}, \
 		.temp_host_release = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
-		}, \
+		},   \
 	}
-__maybe_unused static const struct ec_thermal_config
-	thermal_config_without_fan = THERMAL_CONFIG_WITHOUT_FAN;
+__maybe_unused static const struct ec_thermal_config thermal_config_without_fan =
+	THERMAL_CONFIG_WITHOUT_FAN;
 
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CONFIG_WITH_FAN \
-	{ \
+#define THERMAL_CONFIG_WITH_FAN  \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(77), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
@@ -120,12 +120,12 @@ struct fan_step {
 
 /* Fan control table */
 static const struct fan_step fan_table0[] = {
-	{.on = 30, .off =  0, .rpm = 3150 },		/* Fan level 0 */
-	{.on = 47, .off = 43, .rpm = 3500 },		/* Fan level 1 */
-	{.on = 50, .off = 47, .rpm = 3750 },		/* Fan level 2 */
-	{.on = 53, .off = 50, .rpm = 4200 },		/* Fan level 3 */
-	{.on = 56, .off = 53, .rpm = 4500 },		/* Fan level 4 */
-	{.on = 59, .off = 56, .rpm = 5000 },		/* Fan level 5 */
+	{ .on = 30, .off = 0, .rpm = 3150 }, /* Fan level 0 */
+	{ .on = 47, .off = 43, .rpm = 3500 }, /* Fan level 1 */
+	{ .on = 50, .off = 47, .rpm = 3750 }, /* Fan level 2 */
+	{ .on = 53, .off = 50, .rpm = 4200 }, /* Fan level 3 */
+	{ .on = 56, .off = 53, .rpm = 4500 }, /* Fan level 4 */
+	{ .on = 59, .off = 56, .rpm = 5000 }, /* Fan level 5 */
 };
 
 /* All fan tables must have the same number of levels */
@@ -148,7 +148,7 @@ int fan_percent_to_rpm(int fan, int pct)
 	if (++cnt != FAN_AVERAGE_TIME_SEC)
 		return fan_table[previous_level].rpm;
 
-	avg_pct = (int) avg_pct / FAN_AVERAGE_TIME_SEC;
+	avg_pct = (int)avg_pct / FAN_AVERAGE_TIME_SEC;
 
 	/*
 	 * Compare the pct and previous pct, we have the three paths :
@@ -287,8 +287,8 @@ static const struct ec_response_keybd_config main_kb = {
 	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
 };
 
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	return &main_kb;
 }
@@ -303,15 +303,15 @@ __override const struct ec_response_keybd_config
  */
 
 const int keyboard_factory_scan_pins[][2] = {
-		{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-		{0, 7}, {1, 4}, {1, 3}, {1, 6}, {1, 7},
-		{3, 1}, {2, 0}, {1, 5}, {2, 6}, {2, 7},
-		{2, 1}, {2, 4}, {2, 5}, {1, 2}, {2, 3},
-		{2, 2}, {3, 0}, {-1, -1}, {-1, -1}, {-1, -1},
+	{ -1, -1 }, { 0, 5 }, { 1, 1 },	  { 1, 0 },   { 0, 6 },
+	{ 0, 7 },   { 1, 4 }, { 1, 3 },	  { 1, 6 },   { 1, 7 },
+	{ 3, 1 },   { 2, 0 }, { 1, 5 },	  { 2, 6 },   { 2, 7 },
+	{ 2, 1 },   { 2, 4 }, { 2, 5 },	  { 1, 2 },   { 2, 3 },
+	{ 2, 2 },   { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 },
 };
 
 const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 #endif
 
 /******************************************************************************/
@@ -322,19 +322,19 @@ static int manual_run_time = -1;
 #endif
 
 struct drop_step {
-	int run_time;	/* battery run time (day) */
-	int drop_volt;	/* drop voltage (mV) */
+	int run_time; /* battery run time (day) */
+	int drop_volt; /* drop voltage (mV) */
 };
 
 /* voltage drop table */
 static const struct drop_step voltage_drop_table[] = {
-	{.run_time =   90, .drop_volt = 13200 },	/* drop level 0 */
-	{.run_time =  198, .drop_volt = 13125 },	/* drop level 1 */
-	{.run_time =  305, .drop_volt = 13050 },	/* drop level 2 */
-	{.run_time =  412, .drop_volt = 12975 },	/* drop level 3 */
-	{.run_time =  519, .drop_volt = 12900 },	/* drop level 4 */
-	{.run_time =  626, .drop_volt = 12825 },	/* drop level 5 */
-	{.run_time =  __INT_MAX__, .drop_volt = 12750 },/* drop level 6 */
+	{ .run_time = 90, .drop_volt = 13200 }, /* drop level 0 */
+	{ .run_time = 198, .drop_volt = 13125 }, /* drop level 1 */
+	{ .run_time = 305, .drop_volt = 13050 }, /* drop level 2 */
+	{ .run_time = 412, .drop_volt = 12975 }, /* drop level 3 */
+	{ .run_time = 519, .drop_volt = 12900 }, /* drop level 4 */
+	{ .run_time = 626, .drop_volt = 12825 }, /* drop level 5 */
+	{ .run_time = __INT_MAX__, .drop_volt = 12750 }, /* drop level 6 */
 };
 
 #define NUM_DROP_LEVELS ARRAY_SIZE(voltage_drop_table)
@@ -346,19 +346,19 @@ static int get_battery_run_time_day(uint32_t *battery_run_time)
 	uint8_t data[6];
 
 	/* get battery run time */
-	rv = sb_read_mfgacc(PARAM_FIRMWARE_RUNTIME,
-			SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data));
+	rv = sb_read_mfgacc(PARAM_FIRMWARE_RUNTIME, SB_ALT_MANUFACTURER_ACCESS,
+			    data, sizeof(data));
 
 	if (rv)
 		return EC_ERROR_UNKNOWN;
 	/*
 	 * The response is 6 bytes; the runtime in seconds is the last 4 bytes.
 	 */
-	run_time = *(int32_t *) (&data[2]);
+	run_time = *(int32_t *)(&data[2]);
 
 #ifdef BATTERY_RUNTIME_TEST
-	cprints(CC_CHARGER, "run_time : 0x%08x (%d day)",
-				run_time, (run_time / 86400));
+	cprints(CC_CHARGER, "run_time : 0x%08x (%d day)", run_time,
+		(run_time / 86400));
 
 	/* manual battery run time fot test */
 	if (manual_run_time != -1)
@@ -388,8 +388,8 @@ int charger_profile_override(struct charge_state_data *curr)
 			break;
 	}
 
-	curr->requested_voltage = MIN(curr->requested_voltage,
-					voltage_drop_table[i].drop_volt);
+	curr->requested_voltage =
+		MIN(curr->requested_voltage, voltage_drop_table[i].drop_volt);
 #ifdef BATTERY_RUNTIME_TEST
 	cprints(CC_CHARGER,
 		"Charger: run time(day): %d, drop level: %d, CV: %d",
@@ -399,13 +399,13 @@ int charger_profile_override(struct charge_state_data *curr)
 }
 
 enum ec_status charger_profile_override_get_param(uint32_t param,
-				uint32_t *value)
+						  uint32_t *value)
 {
 	return EC_RES_INVALID_PARAM;
 }
 
 enum ec_status charger_profile_override_set_param(uint32_t param,
-				uint32_t value)
+						  uint32_t value)
 {
 	return EC_RES_INVALID_PARAM;
 }
@@ -427,7 +427,7 @@ DECLARE_HOOK(HOOK_INIT, battery_runtime_init, HOOK_PRIO_LAST);
 
 #ifdef BATTERY_RUNTIME_TEST
 /* test command */
-static int command_manual_run_time(int argc, char **argv)
+static int command_manual_run_time(int argc, const char **argv)
 {
 	char *e = NULL;
 
@@ -445,10 +445,10 @@ static int command_manual_run_time(int argc, char **argv)
 		return EC_ERROR_PARAM1;
 
 	cprints(CC_CHARGER, "manual run time set to %d sec (%d day)",
-				manual_run_time, (manual_run_time/86400));
+		manual_run_time, (manual_run_time / 86400));
 
 	return EC_SUCCESS;
 }
 DECLARE_CONSOLE_COMMAND(rt, command_manual_run_time, "<battery_run_time_sec>",
-					"Set manual run time for test");
+			"Set manual run time for test");
 #endif
diff --git a/board/chronicler/board.h b/board/chronicler/board.h
index 1f6fb0f287..71ef0bd959 100644
--- a/board/chronicler/board.h
+++ b/board/chronicler/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -37,27 +37,27 @@
 #undef CONFIG_ACCEL_FIFO_SIZE
 
 /* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
 
 /* TODO: b/144165680 - measure and check these values on Volteer */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
 /*
  * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
  * cables only support up to 60W.
  */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* USB Type A Features */
-#define USB_PORT_COUNT			1
+#define USB_PORT_COUNT 1
 #define CONFIG_USB_PORT_POWER_DUMB
 
 /* USBC PPC*/
-#define CONFIG_USBC_PPC_SN5S330		/* USBC port C0 */
-#define CONFIG_USBC_PPC_SYV682X		/* USBC port C1 */
+#define CONFIG_USBC_PPC_SN5S330 /* USBC port C0 */
+#define CONFIG_USBC_PPC_SYV682X /* USBC port C1 */
 #define CONFIG_USB_PD_FRS_PPC
 #undef CONFIG_USB_PD_TCPC_RUNTIME_CONFIG
 #undef CONFIG_USB_PD_TCPM_TUSB422
@@ -72,8 +72,8 @@
 #define CONFIG_FAN_RPM_CUSTOM
 
 /* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 #define CONFIG_CHARGER_PROFILE_OVERRIDE
 
 /* Retimer */
@@ -89,44 +89,44 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_DSW_PWROK		GPIO_EC_PCH_DSW_PWROK
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_LID_OPEN GPIO_EC_LID_OPEN
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL
 
 /* I2C Bus Configuration */
 #define CONFIG_I2C
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_1_MIX	NPCX_I2C_PORT3_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT3_0
+#define I2C_PORT_POWER NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
 
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
+#define I2C_PORT_BATTERY I2C_PORT_POWER
+#define I2C_PORT_CHARGER I2C_PORT_EEPROM
 
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 #define CONFIG_I2C_CONTROLLER
 
 #define CONFIG_DEBUG_ASSERT_BRIEF
 
 /* Disable volume button command in EC console */
-#undef  CONFIG_CMD_BUTTON
+#undef CONFIG_CMD_BUTTON
 
 /* Disable volume button in ectool */
 #undef CONFIG_HOSTCMD_BUTTON
@@ -141,16 +141,9 @@
 
 #include "usbc_config.h"
 
-enum battery_type {
-	BATTERY_NVT_CP813907,
-	BATTERY_TYPE_COUNT
-};
+enum battery_type { BATTERY_NVT_CP813907, BATTERY_TYPE_COUNT };
 
-enum pwm_channel {
-	PWM_CH_FAN,
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_FAN, PWM_CH_KBLIGHT, PWM_CH_COUNT };
 
 void board_reset_pd_mcu(void);
 
diff --git a/board/chronicler/build.mk b/board/chronicler/build.mk
index c0daa31eaa..f317b88795 100644
--- a/board/chronicler/build.mk
+++ b/board/chronicler/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/chronicler/cbi.c b/board/chronicler/cbi.c
index 210207eeac..712461cd2c 100644
--- a/board/chronicler/cbi.c
+++ b/board/chronicler/cbi.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/chronicler/ec.tasklist b/board/chronicler/ec.tasklist
index df7495f2a1..644c36cd37 100644
--- a/board/chronicler/ec.tasklist
+++ b/board/chronicler/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/chronicler/gpio.inc b/board/chronicler/gpio.inc
index b8b8d4f5e7..b0a9ad6981 100644
--- a/board/chronicler/gpio.inc
+++ b/board/chronicler/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,7 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
diff --git a/board/chronicler/keyboard.c b/board/chronicler/keyboard.c
index b9cc378295..9e04d77ca3 100644
--- a/board/chronicler/keyboard.c
+++ b/board/chronicler/keyboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/chronicler/led.c b/board/chronicler/led.c
index dfa7fefa1b..8fd743101a 100644
--- a/board/chronicler/led.c
+++ b/board/chronicler/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -21,10 +21,10 @@
 #define POWER_LED_ON 0
 #define POWER_LED_OFF 1
 
-#define LED_CYCLE_TIME_MS   (2 * 1000)
+#define LED_CYCLE_TIME_MS (2 * 1000)
 #define LED_TICKS_PER_CYCLE (LED_CYCLE_TIME_MS / HOOK_TICK_INTERVAL_MS)
-#define LED_ON_TIME_MS      (1 * 1000)
-#define LED_ON_TICKS        (LED_ON_TIME_MS / HOOK_TICK_INTERVAL_MS)
+#define LED_ON_TIME_MS (1 * 1000)
+#define LED_ON_TICKS (LED_ON_TIME_MS / HOOK_TICK_INTERVAL_MS)
 
 const enum ec_led_id supported_led_ids[] = {
 	EC_LED_ID_LEFT_LED,
@@ -37,22 +37,19 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
-enum led_port {
-	RIGHT_PORT = 0,
-	LEFT_PORT
-};
+enum led_port { RIGHT_PORT = 0, LEFT_PORT };
 
 static void led_set_color_battery(enum led_port port, enum led_color color)
 {
 	enum gpio_signal amber_led, white_led;
 
 	amber_led = (port == RIGHT_PORT ? GPIO_C0_CHARGE_LED_AMBER_L :
-				 GPIO_C1_CHARGE_LED_AMBER_L);
+					  GPIO_C1_CHARGE_LED_AMBER_L);
 	white_led = (port == RIGHT_PORT ? GPIO_C0_CHARGE_LED_WHITE_L :
-				 GPIO_C1_CHARGE_LED_WHITE_L);
+					  GPIO_C1_CHARGE_LED_WHITE_L);
 
 	switch (color) {
 	case LED_WHITE:
@@ -124,17 +121,16 @@ static void set_active_port_color(enum led_color color)
 
 	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
 		led_set_color_battery(RIGHT_PORT,
-				(port == RIGHT_PORT) ? color : LED_OFF);
+				      (port == RIGHT_PORT) ? color : LED_OFF);
 	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
 		led_set_color_battery(LEFT_PORT,
-				(port == LEFT_PORT) ? color : LED_OFF);
+				      (port == LEFT_PORT) ? color : LED_OFF);
 }
 
 static void led_set_battery(void)
 {
 	static int battery_ticks;
 	static int suspend_ticks;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
@@ -144,14 +140,13 @@ static void led_set_battery(void)
 	 * LEDs to indicate system suspend without charging state.
 	 */
 	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
-		charge_get_state() != PWR_STATE_CHARGE) {
-
+	    charge_get_state() != PWR_STATE_CHARGE) {
 		suspend_ticks++;
 
-		led_set_color_battery(RIGHT_PORT, suspend_ticks & 0x4 ?
-					  LED_WHITE : LED_OFF);
-		led_set_color_battery(LEFT_PORT, suspend_ticks & 0x4 ?
-					  LED_WHITE : LED_OFF);
+		led_set_color_battery(
+			RIGHT_PORT, suspend_ticks & 0x4 ? LED_WHITE : LED_OFF);
+		led_set_color_battery(
+			LEFT_PORT, suspend_ticks & 0x4 ? LED_WHITE : LED_OFF);
 		return;
 	}
 
@@ -165,9 +160,12 @@ static void led_set_battery(void)
 	case PWR_STATE_DISCHARGE:
 		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
 			if (charge_get_percent() < 10)
-				led_set_color_battery(RIGHT_PORT,
-					(battery_ticks % LED_TICKS_PER_CYCLE
-					 < LED_ON_TICKS) ? LED_WHITE : LED_OFF);
+				led_set_color_battery(
+					RIGHT_PORT,
+					(battery_ticks % LED_TICKS_PER_CYCLE <
+					 LED_ON_TICKS) ?
+						LED_WHITE :
+						LED_OFF);
 			else
 				led_set_color_battery(RIGHT_PORT, LED_OFF);
 		}
@@ -176,19 +174,20 @@ static void led_set_battery(void)
 			led_set_color_battery(LEFT_PORT, LED_OFF);
 		break;
 	case PWR_STATE_ERROR:
-		set_active_port_color((battery_ticks & 0x2) ?
-				LED_WHITE : LED_OFF);
+		set_active_port_color((battery_ticks & 0x2) ? LED_WHITE :
+							      LED_OFF);
 		break;
 	case PWR_STATE_CHARGE_NEAR_FULL:
 		set_active_port_color(LED_WHITE);
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			set_active_port_color((battery_ticks %
-				LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-				LED_AMBER : LED_OFF);
-		else
-			set_active_port_color(LED_WHITE);
+		set_active_port_color(LED_WHITE);
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		set_active_port_color(
+			(battery_ticks % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
+				LED_AMBER :
+				LED_OFF);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
diff --git a/board/chronicler/usbc_config.c b/board/chronicler/usbc_config.c
index c2783dd755..b05cd4ecfd 100644
--- a/board/chronicler/usbc_config.c
+++ b/board/chronicler/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,18 +23,21 @@
 #include "driver/tcpm/tusb422_public.h"
 #include "driver/tcpm/tcpci.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 /*
  * USB3 DB mux configuration - the top level mux still needs to be set to the
  * virtual_usb_mux_driver so the AP gets notified of mux changes and updates
  * the TCSS configuration on state changes.
  */
-static const struct usb_mux usbc1_usb3_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	.next_mux = NULL,
+static const struct usb_mux_chain usbc1_usb3_db_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
+	.next = NULL,
 };
 
 /******************************************************************************/
@@ -104,17 +107,21 @@ const int usb_port_enable[USB_PORT_COUNT] = {
 
 /******************************************************************************/
 /* USBC mux configuration - Tiger Lake includes internal mux */
-const struct usb_mux usb_muxes[] = {
+const struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 	},
 	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc1_usb3_db_retimer,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc1_usb3_db_retimer,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
@@ -124,8 +131,7 @@ static void ps8815_reset(void)
 	int val;
 
 	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 0);
-	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS,
-			   PS8815_PWR_H_RST_H_DELAY_MS));
+	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS));
 	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 1);
 	msleep(PS8815_FW_INIT_DELAY_MS);
 
@@ -136,16 +142,16 @@ static void ps8815_reset(void)
 
 	CPRINTS("%s: patching ps8815 registers", __func__);
 
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
+	if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) ==
+	    EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f was %02x", val);
 
-	if (i2c_write8(I2C_PORT_USB_C1,
-		       PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) == EC_SUCCESS)
+	if (i2c_write8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f,
+		       0x31) == EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f set to 0x31");
 
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
+	if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) ==
+	    EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f now %02x", val);
 }
 
@@ -207,7 +213,7 @@ void board_reset_pd_mcu(void)
 	/* Daughterboard specific reset for port 1 */
 	ps8815_reset();
 	usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
 
 static void board_tcpc_init(void)
diff --git a/board/chronicler/usbc_config.h b/board/chronicler/usbc_config.h
index 55dfce7621..7428d0c436 100644
--- a/board/chronicler/usbc_config.h
+++ b/board/chronicler/usbc_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,11 +8,7 @@
 #ifndef __CROS_EC_USBC_CONFIG_H
 #define __CROS_EC_USBC_CONFIG_H
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 /* Configure the USB3 daughterboard type */
 void config_usb3_db_type(void);
diff --git a/board/coachz/base_detect.c b/board/coachz/base_detect.c
index 0068b37d8d..f2195f4d8a 100644
--- a/board/coachz/base_detect.c
+++ b/board/coachz/base_detect.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,8 +19,8 @@
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
 /* Base detection and debouncing */
 #define BASE_DETECT_EN_DEBOUNCE_US (350 * MSEC)
@@ -93,8 +93,8 @@ static uint32_t pulse_width;
 
 static void print_base_detect_value(int v, int tmp_pulse_width)
 {
-	CPRINTS("%s = %d (pulse %d)", adc_channels[ADC_BASE_DET].name,
-			v, tmp_pulse_width);
+	CPRINTS("%s = %d (pulse %d)", adc_channels[ADC_BASE_DET].name, v,
+		tmp_pulse_width);
 }
 
 static void base_detect_deferred(void)
@@ -144,12 +144,12 @@ void base_detect_interrupt(enum gpio_signal signal)
 {
 	uint64_t time_now = get_time().val;
 	int debounce_us;
-	
+
 	if (detect_pin_connected(signal))
 		debounce_us = BASE_DETECT_EN_DEBOUNCE_US;
-        else
+	else
 		debounce_us = BASE_DETECT_DIS_DEBOUNCE_US;
-  
+
 	if (base_detect_debounce_time <= time_now) {
 		/*
 		 * Detect and measure detection pin pulse, when base is
@@ -211,7 +211,7 @@ static void base_init(void)
 	if (system_jumped_late() && chipset_in_state(CHIPSET_STATE_ON))
 		base_enable();
 }
-DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT+1);
+DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT + 1);
 
 void base_force_state(enum ec_set_base_state_cmd state)
 {
diff --git a/board/coachz/battery.c b/board/coachz/battery.c
index a5be64df0f..a89b26f49a 100644
--- a/board/coachz/battery.c
+++ b/board/coachz/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/coachz/board.c b/board/coachz/board.c
index 088c958679..c9a22d8211 100644
--- a/board/coachz/board.c
+++ b/board/coachz/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -36,10 +36,10 @@
 #include "task.h"
 #include "usbc_ppc.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define KS_DEBOUNCE_US    (30 * MSEC)  /* Debounce time for kickstand switch */
+#define KS_DEBOUNCE_US (30 * MSEC) /* Debounce time for kickstand switch */
 
 /* Forward declaration */
 static void tcpc_alert_event(enum gpio_signal signal);
@@ -173,8 +173,7 @@ static void ks_change_deferred(void)
 	proximity_detected = !(ks_attached && ks_open);
 	CPRINTS("ks %s %s -> proximity %s",
 		ks_attached ? "attached" : "detached",
-		ks_open ? "open" : "close",
-		proximity_detected ? "on" : "off");
+		ks_open ? "open" : "close", proximity_detected ? "on" : "off");
 
 	debounced_ks_attached = ks_attached;
 	debounced_ks_open = ks_open;
@@ -191,48 +190,36 @@ static void ks_interrupt(enum gpio_signal s)
 
 /* I2C port map */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl  = GPIO_EC_I2C_POWER_SCL,
-		.sda  = GPIO_EC_I2C_POWER_SDA
-	},
-	{
-		.name = "tcpc0",
-		.port = I2C_PORT_TCPC0,
-		.kbps = 1000,
-		.scl  = GPIO_EC_I2C_USB_C0_PD_SCL,
-		.sda  = GPIO_EC_I2C_USB_C0_PD_SDA
-	},
-	{
-		.name = "tcpc1",
-		.port = I2C_PORT_TCPC1,
-		.kbps = 1000,
-		.scl  = GPIO_EC_I2C_USB_C1_PD_SCL,
-		.sda  = GPIO_EC_I2C_USB_C1_PD_SDA
-	},
-	{
-		.name = "wlc",
-		.port = I2C_PORT_WLC,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_WLC_SCL,
-		.sda  = GPIO_EC_I2C_WLC_SDA
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_EEPROM_SCL,
-		.sda  = GPIO_EC_I2C_EEPROM_SDA
-	},
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_SENSOR_SCL,
-		.sda  = GPIO_EC_I2C_SENSOR_SDA
-	},
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_POWER_SCL,
+	  .sda = GPIO_EC_I2C_POWER_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C0_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C0_PD_SDA },
+	{ .name = "tcpc1",
+	  .port = I2C_PORT_TCPC1,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C1_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C1_PD_SDA },
+	{ .name = "wlc",
+	  .port = I2C_PORT_WLC,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_WLC_SCL,
+	  .sda = GPIO_EC_I2C_WLC_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_EEPROM_SCL,
+	  .sda = GPIO_EC_I2C_EEPROM_SDA },
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_SENSOR_SCL,
+	  .sda = GPIO_EC_I2C_SENSOR_SDA },
 };
 
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
@@ -240,45 +227,25 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* Measure VBUS through a 1/10 voltage divider */
-	[ADC_VBUS] = {
-		"VBUS",
-		NPCX_ADC_CH1,
-		ADC_MAX_VOLT * 10,
-		ADC_READ_MAX + 1,
-		0
-	},
+	[ADC_VBUS] = { "VBUS", NPCX_ADC_CH1, ADC_MAX_VOLT * 10,
+		       ADC_READ_MAX + 1, 0 },
 	/*
 	 * Adapter current output or battery charging/discharging current (uV)
 	 * 18x amplification on charger side.
 	 */
-	[ADC_AMON_BMON] = {
-		"AMON_BMON",
-		NPCX_ADC_CH2,
-		ADC_MAX_VOLT * 1000 / 18,
-		ADC_READ_MAX + 1,
-		0
-	},
+	[ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH2, ADC_MAX_VOLT * 1000 / 18,
+			    ADC_READ_MAX + 1, 0 },
 	/*
 	 * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read
 	 * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and
 	 * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we
 	 * only divide by 2 (enough to avoid precision issues).
 	 */
-	[ADC_PSYS] = {
-		"PSYS",
-		NPCX_ADC_CH3,
-		ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1),
-		2,
-		0
-	},
+	[ADC_PSYS] = { "PSYS", NPCX_ADC_CH3,
+		       ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), 2, 0 },
 	/* Base detection */
-	[ADC_BASE_DET] = {
-		"BASE_DET",
-		NPCX_ADC_CH5,
-		ADC_MAX_VOLT,
-		ADC_READ_MAX + 1,
-		0
-	},
+	[ADC_BASE_DET] = { "BASE_DET", NPCX_ADC_CH5, ADC_MAX_VOLT,
+			   ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
@@ -290,16 +257,12 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
 /* Power Path Controller */
 struct ppc_config_t ppc_chips[] = {
-	{
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	{
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
+	{ .i2c_port = I2C_PORT_TCPC0,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
+	{ .i2c_port = I2C_PORT_TCPC1,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
 };
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
@@ -330,16 +293,22 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
  * to AP. But the TCPC chip is also needed to know the HPD status; otherwise,
  * the mux misbehaves.
  */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	},
 	{
-		.usb_port = 1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	}
 };
 
@@ -364,11 +333,9 @@ static struct bmi_drv_data_t g_bmi260_data;
 bool is_bmi260_present;
 
 /* Matrix to rotate accelerometer into standard reference frame */
-const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+				      { FLOAT_TO_FP(1), 0, 0 },
+				      { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	/*
@@ -471,8 +438,8 @@ static void board_detect_motionsensor(void)
 
 	/* Check base accelgyro chip */
 	bmi_read8(motion_sensors[LID_ACCEL].port,
-		motion_sensors[LID_ACCEL].i2c_spi_addr_flags,
-		BMI260_CHIP_ID, &val);
+		  motion_sensors[LID_ACCEL].i2c_spi_addr_flags, BMI260_CHIP_ID,
+		  &val);
 	if (val == BMI260_CHIP_ID_MAJOR) {
 		motion_sensors[LID_ACCEL] = motion_sensors_260[LID_ACCEL];
 		motion_sensors[LID_GYRO] = motion_sensors_260[LID_GYRO];
@@ -553,9 +520,9 @@ void board_tcpc_init(void)
 	 */
 	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
 		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
 
 void board_hibernate(void)
 {
@@ -565,8 +532,7 @@ void board_hibernate(void)
 	 * Sensors are unpowered in hibernate. Apply PD to the
 	 * interrupt lines such that they don't float.
 	 */
-	gpio_set_flags(GPIO_ACCEL_GYRO_INT_L,
-		       GPIO_INPUT | GPIO_PULL_DOWN);
+	gpio_set_flags(GPIO_ACCEL_GYRO_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
 
 	/*
 	 * Board rev 1+ has the hardware fix. Don't need the following
@@ -662,8 +628,7 @@ void board_overcurrent_event(int port, int is_overcurrented)
 
 int board_set_active_charge_port(int port)
 {
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	int i;
 
 	if (!is_real_port && port != CHARGE_PORT_NONE)
@@ -691,7 +656,6 @@ int board_set_active_charge_port(int port)
 		return EC_ERROR_INVAL;
 	}
 
-
 	CPRINTS("New charge port: p%d", port);
 
 	/*
@@ -715,24 +679,22 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	/*
 	 * Ignore lower charge ceiling on PD transition if our battery is
 	 * critical, as we may brownout.
 	 */
-	if (supplier == CHARGE_SUPPLIER_PD &&
-	    charge_ma < 1500 &&
+	if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 &&
 	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
 		CPRINTS("Using max ilim %d", max_ma);
 		charge_ma = max_ma;
 	}
 
 	charge_ma = charge_ma * 95 / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 uint16_t tcpc_get_alert_status(void)
diff --git a/board/coachz/board.h b/board/coachz/board.h
index e1e2d94545..8d21cbc68c 100644
--- a/board/coachz/board.h
+++ b/board/coachz/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,7 +12,7 @@
 
 /* On-body detection */
 #define CONFIG_BODY_DETECTION
-#define CONFIG_BODY_DETECTION_SENSOR           LID_ACCEL
+#define CONFIG_BODY_DETECTION_SENSOR LID_ACCEL
 #define CONFIG_BODY_DETECTION_VAR_NOISE_FACTOR 150 /* % */
 #define CONFIG_GESTURE_DETECTION
 #define CONFIG_GESTURE_DETECTION_MASK BIT(CONFIG_BODY_DETECTION_SENSOR)
@@ -21,7 +21,7 @@
 #define CONFIG_BUTTON_TRIGGERED_RECOVERY
 
 /* Internal SPI flash on NPCX7 */
-#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)  /* 512KB internal spi flash */
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */
 
 /* Save some flash space */
 #define CONFIG_LTO
@@ -34,7 +34,7 @@
 #undef CONFIG_CMD_TASK_RESET
 
 /* Battery */
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY  "LION"
+#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
 #define CONFIG_BATTERY_REVIVE_DISCONNECT
 #define CONFIG_BATTERY_FUEL_GAUGE
 #define CONFIG_BATTERY_VENDOR_PARAM
@@ -101,10 +101,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_DISPLIGHT = 0,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_DISPLIGHT = 0, PWM_CH_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
diff --git a/board/coachz/build.mk b/board/coachz/build.mk
index e8e293064e..01678fc8bb 100644
--- a/board/coachz/build.mk
+++ b/board/coachz/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/coachz/ec.tasklist b/board/coachz/ec.tasklist
index dc5b32b4cf..ecb6672d32 100644
--- a/board/coachz/ec.tasklist
+++ b/board/coachz/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/coachz/gpio.inc b/board/coachz/gpio.inc
index d7ca61ac6b..1bb8e9135b 100644
--- a/board/coachz/gpio.inc
+++ b/board/coachz/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/coachz/led.c b/board/coachz/led.c
index 9dd8729a04..6623089db0 100644
--- a/board/coachz/led.c
+++ b/board/coachz/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -35,15 +35,15 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_BLUE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static void led_set_color(enum led_color color)
 {
 	gpio_set_level(GPIO_EC_CHG_LED_Y_C0,
-		(color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
+		       (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
 	gpio_set_level(GPIO_EC_CHG_LED_W_C0,
-		(color == LED_BLUE) ? BAT_LED_ON : BAT_LED_OFF);
+		       (color == LED_BLUE) ? BAT_LED_ON : BAT_LED_OFF);
 }
 
 void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
@@ -69,7 +69,6 @@ static void board_led_set_battery(void)
 	static int battery_ticks;
 	int color = LED_OFF;
 	int period = 0;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
@@ -84,16 +83,15 @@ static void board_led_set_battery(void)
 			period = (1 + 1) * LED_ONE_SEC;
 			battery_ticks = battery_ticks % period;
 			if (battery_ticks < 1 * LED_ONE_SEC) {
-				if (charge_get_percent() < 10)
-                                {
-                                	/* Blink amber light (1 sec on, 1 sec off) */
+				if (charge_get_percent() < 10) {
+					/* Blink amber light (1 sec on, 1 sec
+					 * off) */
 					color = LED_AMBER;
-                                }
-				else
-                                {
-                                	/* Blink white light (1 sec on, 1 sec off) */
+				} else {
+					/* Blink white light (1 sec on, 1 sec
+					 * off) */
 					color = LED_BLUE;
-                                }
+				}
 			} else {
 				color = LED_OFF;
 			}
@@ -138,16 +136,16 @@ static void board_led_set_battery(void)
 		}
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE) {
-			/* Factory mode: Blue 2 sec, Amber 2 sec */
-			period = (2 + 2) * LED_ONE_SEC;
-			battery_ticks = battery_ticks % period;
-			if (battery_ticks < 2 * LED_ONE_SEC)
-				color = LED_BLUE;
-			else
-				color = LED_AMBER;
-		} else
+		color = LED_BLUE;
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		/* Factory mode: Blue 2 sec, Amber 2 sec */
+		period = (2 + 2) * LED_ONE_SEC;
+		battery_ticks = battery_ticks % period;
+		if (battery_ticks < 2 * LED_ONE_SEC)
 			color = LED_BLUE;
+		else
+			color = LED_AMBER;
 		break;
 	default:
 		/* Other states don't alter LED behavior */
diff --git a/board/coachz/usbc_config.c b/board/coachz/usbc_config.c
index d6930586dd..9409ee04fc 100644
--- a/board/coachz/usbc_config.c
+++ b/board/coachz/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,8 @@
 #include "gpio.h"
 #include "usb_pd.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 const struct charger_config_t chg_chips[] = {
 	{
diff --git a/board/coffeecake/board.c b/board/coffeecake/board.c
index b344a5f745..05cba7e4f7 100644
--- a/board/coffeecake/board.c
+++ b/board/coffeecake/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -31,13 +31,11 @@ void vbus_event(enum gpio_signal signal);
 
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "charger",
-		.port = I2C_PORT_SY21612,
-		.kbps = 400,
-		.scl  = GPIO_I2C0_SCL,
-		.sda  = GPIO_I2C0_SDA
-	},
+	{ .name = "charger",
+	  .port = I2C_PORT_SY21612,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_SCL,
+	  .sda = GPIO_I2C0_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -153,7 +151,7 @@ void board_config_pre_init(void)
 	/* Set 5Vsafe Vdac */
 	board_set_usb_output_voltage(5000);
 	/* Remap USART DMA to match the USART driver */
-	STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10);/* Remap USART1 RX/TX DMA */
+	STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10); /* Remap USART1 RX/TX DMA */
 }
 
 #ifdef CONFIG_SPI_FLASH
@@ -197,10 +195,9 @@ static void factory_validation_deferred(void)
 
 	/* test mcdp via serial to validate function */
 	if (!mcdp_get_info(&info) && (MCDP_FAMILY(info.family) == 0x0010) &&
-	(MCDP_CHIPID(info.chipid) == 0x2850)) {
+	    (MCDP_CHIPID(info.chipid) == 0x2850)) {
 		pd_log_event(PD_EVENT_VIDEO_CODEC,
-			     PD_LOG_PORT_SIZE(0, sizeof(info)),
-			     0, &info);
+			     PD_LOG_PORT_SIZE(0, sizeof(info)), 0, &info);
 	}
 
 	mcdp_disable();
@@ -215,7 +212,8 @@ static void board_post_init(void)
 	 * DUT powered - DRP SINK
 	 */
 	pd_set_dual_role(0, gpio_get_level(GPIO_AC_PRESENT_L) ?
-			 PD_DRP_FORCE_SINK : PD_DRP_FORCE_SOURCE);
+				    PD_DRP_FORCE_SINK :
+				    PD_DRP_FORCE_SOURCE);
 }
 DECLARE_DEFERRED(board_post_init);
 
@@ -233,10 +231,11 @@ static void board_init(void)
 	gpio_enable_interrupt(GPIO_CHARGER_INT);
 	gpio_enable_interrupt(GPIO_USB_C_VBUS_DET_L);
 	/* Set PD_DISCHARGE initial state */
-	gpio_set_level(GPIO_PD_DISCHARGE, gpio_get_level(GPIO_USB_C_VBUS_DET_L));
+	gpio_set_level(GPIO_PD_DISCHARGE,
+		       gpio_get_level(GPIO_USB_C_VBUS_DET_L));
 
 	/* Delay needed to allow HDMI MCU to boot. */
-	hook_call_deferred(&factory_validation_deferred_data, 200*MSEC);
+	hook_call_deferred(&factory_validation_deferred_data, 200 * MSEC);
 	/* Initialize buck-boost converter */
 	hook_call_deferred(&board_post_init_data, 0);
 }
@@ -246,16 +245,16 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* USB PD CC lines sensing. Converted to mV (3300mV/4096). */
-	[ADC_CH_CC1_PD]    = {"USB_C_CC1_PD", 3300, 4096, 0, STM32_AIN(1)},
-	[ADC_VBUS_MON]     = {"VBUS_MON", 13200, 4096, 0, STM32_AIN(2)},
-	[ADC_DAC_REF_TP28] = {"DAC_REF_TP28", 3300, 4096, 0, STM32_AIN(4)},
-	[ADC_DAC_VOLT]     = {"DAC_VOLT", 3300, 4096, 0, STM32_AIN(5)},
+	[ADC_CH_CC1_PD] = { "USB_C_CC1_PD", 3300, 4096, 0, STM32_AIN(1) },
+	[ADC_VBUS_MON] = { "VBUS_MON", 13200, 4096, 0, STM32_AIN(2) },
+	[ADC_DAC_REF_TP28] = { "DAC_REF_TP28", 3300, 4096, 0, STM32_AIN(4) },
+	[ADC_DAC_VOLT] = { "DAC_VOLT", 3300, 4096, 0, STM32_AIN(5) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
-const void * const usb_strings[] = {
+const void *const usb_strings[] = {
 	[USB_STR_DESC] = usb_string_desc,
-	[USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."),
+	[USB_STR_VENDOR] = USB_STRING_DESC("Google LLC"),
 	[USB_STR_PRODUCT] = USB_STRING_DESC("Hoho"),
 	[USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32),
 	[USB_STR_BB_URL] = USB_STRING_DESC(USB_GOOGLE_TYPEC_URL),
diff --git a/board/coffeecake/board.h b/board/coffeecake/board.h
index cabbb0bf4e..966a5b2516 100644
--- a/board/coffeecake/board.h
+++ b/board/coffeecake/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -50,7 +50,7 @@
 #define CONFIG_USB_PD_IDENTITY_HW_VERS 1
 #define CONFIG_USB_PD_IDENTITY_SW_VERS 1
 #define CONFIG_USB_PD_LOGGING
-#undef  CONFIG_EVENT_LOG_SIZE
+#undef CONFIG_EVENT_LOG_SIZE
 #define CONFIG_EVENT_LOG_SIZE 256
 #define CONFIG_USB_PD_CUSTOM_PDO
 #define CONFIG_USB_PD_PORT_MAX_COUNT 1
@@ -80,7 +80,7 @@
 
 /* Timer selection */
 #define TIM_CLOCK32 2
-#define TIM_ADC     3
+#define TIM_ADC 3
 
 #include "gpio_signal.h"
 
@@ -106,21 +106,21 @@ enum usb_strings {
 };
 
 /* 3.0A Rp */
-#define PD_SRC_VNC            PD_SRC_3_0_VNC_MV
-#define PD_SRC_RD_THRESHOLD   PD_SRC_3_0_RD_THRESH_MV
+#define PD_SRC_VNC PD_SRC_3_0_VNC_MV
+#define PD_SRC_RD_THRESHOLD PD_SRC_3_0_RD_THRESH_MV
 
 /* delay necessary for the voltage transition on the power supply */
 /* TODO (code.google.com/p/chrome-os-partner/issues/detail?id=37078)
  * Need to measure these and adjust for honeybuns.
  */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  50000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 50000 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 50000 /* us */
 
 /* Define typical operating power and max power */
 #define PD_OPERATING_POWER_MW 1000
-#define PD_MAX_POWER_MW       22500
-#define PD_MAX_CURRENT_MA     2500
-#define PD_MAX_VOLTAGE_MV     9000
+#define PD_MAX_POWER_MW 22500
+#define PD_MAX_CURRENT_MA 2500
+#define PD_MAX_VOLTAGE_MV 9000
 
 /* Board interfaces */
 void board_set_usb_output_voltage(int mv);
@@ -131,11 +131,11 @@ void board_set_usb_output_voltage(int mv);
 #define USB_DEV_CLASS USB_CLASS_BILLBOARD
 
 /* USB interface indexes (use define rather than enum to expand them) */
-#define USB_IFACE_COUNT     0
+#define USB_IFACE_COUNT 0
 
 /* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL   0
-#define USB_EP_COUNT     1
+#define USB_EP_CONTROL 0
+#define USB_EP_COUNT 1
 
 /* I2C ports */
 #define I2C_PORT_SY21612 0
diff --git a/board/coffeecake/build.mk b/board/coffeecake/build.mk
index 59ca88486b..26ddbbd925 100644
--- a/board/coffeecake/build.mk
+++ b/board/coffeecake/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/coffeecake/ec.tasklist b/board/coffeecake/ec.tasklist
index d6686d72e9..e02c0620f8 100644
--- a/board/coffeecake/ec.tasklist
+++ b/board/coffeecake/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/coffeecake/gpio.inc b/board/coffeecake/gpio.inc
index bab62a6bea..9d0a02ea40 100644
--- a/board/coffeecake/gpio.inc
+++ b/board/coffeecake/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/coffeecake/usb_pd_config.h b/board/coffeecake/usb_pd_config.h
index e2c1dbb2db..728d96bafe 100644
--- a/board/coffeecake/usb_pd_config.h
+++ b/board/coffeecake/usb_pd_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -49,7 +49,7 @@ static inline void spi_enable_clock(int port)
 
 #define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
 #define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
-#define TIM_CCR_CS  1
+#define TIM_CCR_CS 1
 #define EXTI_COMP_MASK(p) BIT(21)
 #define IRQ_COMP STM32_IRQ_COMP
 /* triggers packet detection on comparator falling edge */
@@ -100,8 +100,8 @@ static inline void pd_select_polarity(int port, int polarity)
 	 * use the right comparator : CC1 -> PA1 (COMP1 INP)
 	 * use VrefInt / 2 as INM (about 600mV)
 	 */
-	STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK)
-		| STM32_COMP_CMP1EN | STM32_COMP_CMP1INSEL_VREF12;
+	STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK) |
+			 STM32_COMP_CMP1EN | STM32_COMP_CMP1INSEL_VREF12;
 }
 
 /* Initialize pins used for TX and put them in Hi-Z */
@@ -136,7 +136,7 @@ static inline int pd_adc_read(int port, int cc)
 	 * Check HOST_HIGH Rp setting.
 	 * Return 3300mV on host mode.
 	 */
-	if ((STM32_GPIO_MODER(GPIO_B) & (3 << (2*5))) == (1 << (2*5)))
+	if ((STM32_GPIO_MODER(GPIO_B) & (3 << (2 * 5))) == (1 << (2 * 5)))
 		return 3300;
 	else
 		return 0;
diff --git a/board/coffeecake/usb_pd_pdo.c b/board/coffeecake/usb_pd_pdo.c
index a766d7dbe5..c0d2298706 100644
--- a/board/coffeecake/usb_pd_pdo.c
+++ b/board/coffeecake/usb_pd_pdo.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,15 +7,16 @@
 #include "usb_pd.h"
 #include "usb_pd_pdo.h"
 
-#define PDO_FIXED_FLAGS_EXT (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\
-			     PDO_FIXED_COMM_CAP | PDO_FIXED_UNCONSTRAINED)
+#define PDO_FIXED_FLAGS_EXT                                               \
+	(PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP | PDO_FIXED_COMM_CAP | \
+	 PDO_FIXED_UNCONSTRAINED)
 
-#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\
-			 PDO_FIXED_COMM_CAP)
+#define PDO_FIXED_FLAGS \
+	(PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP | PDO_FIXED_COMM_CAP)
 
 const uint32_t pd_src_pdo[] = {
-	[PDO_IDX_5V]  = PDO_FIXED(5000,  3000, PDO_FIXED_FLAGS_EXT),
-	[PDO_IDX_9V]  = PDO_FIXED(9000,  2500, PDO_FIXED_FLAGS),
+	[PDO_IDX_5V] = PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS_EXT),
+	[PDO_IDX_9V] = PDO_FIXED(9000, 2500, PDO_FIXED_FLAGS),
 };
 const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
 BUILD_ASSERT(ARRAY_SIZE(pd_src_pdo) == PDO_IDX_COUNT);
diff --git a/board/coffeecake/usb_pd_pdo.h b/board/coffeecake/usb_pd_pdo.h
index f695defddb..2ec925955d 100644
--- a/board/coffeecake/usb_pd_pdo.h
+++ b/board/coffeecake/usb_pd_pdo.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/coffeecake/usb_pd_policy.c b/board/coffeecake/usb_pd_policy.c
index c8c74688a8..525d1057e2 100644
--- a/board/coffeecake/usb_pd_policy.c
+++ b/board/coffeecake/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,8 +22,8 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 /* Holds valid object position (opos) for entered mode */
 static int alt_mode[PD_AMODE_COUNT];
@@ -97,31 +97,24 @@ int pd_check_power_swap(int port)
 	return 0;
 }
 
-int pd_check_data_swap(int port,
-		       enum pd_data_role data_role)
+int pd_check_data_swap(int port, enum pd_data_role data_role)
 {
 	/* We can swap to UFP */
 	return data_role == PD_ROLE_DFP;
 }
 
-void pd_execute_data_swap(int port,
-			  enum pd_data_role data_role)
+void pd_execute_data_swap(int port, enum pd_data_role data_role)
 {
 	/* TODO: turn on pp5000, pp3300 */
 }
 
-void pd_check_pr_role(int port,
-		      enum pd_power_role pr_role,
-		      int flags)
+void pd_check_pr_role(int port, enum pd_power_role pr_role, int flags)
 {
 	if (pr_role == PD_ROLE_SINK && !gpio_get_level(GPIO_AC_PRESENT_L))
 		pd_request_power_swap(port);
-
 }
 
-void pd_check_dr_role(int port,
-		      enum pd_data_role dr_role,
-		      int flags)
+void pd_check_dr_role(int port, enum pd_data_role dr_role, int flags)
 {
 	if ((flags & PD_FLAGS_PARTNER_DR_DATA) && dr_role == PD_ROLE_DFP)
 		pd_request_data_swap(port);
@@ -136,8 +129,8 @@ const uint32_t vdo_idh = VDO_IDH(0, /* data caps as USB host */
 const uint32_t vdo_product = VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV);
 
 const uint32_t vdo_ama = VDO_AMA(CONFIG_USB_PD_IDENTITY_HW_VERS,
-				 CONFIG_USB_PD_IDENTITY_SW_VERS,
-				 0, 0, 0, 0, /* SS[TR][12] */
+				 CONFIG_USB_PD_IDENTITY_SW_VERS, 0, 0, 0,
+				 0, /* SS[TR][12] */
 				 0, /* Vconn power */
 				 0, /* Vconn power required */
 				 1, /* Vbus power required */
@@ -163,18 +156,16 @@ static int svdm_response_svids(int port, uint32_t *payload)
 #define OPOS_DP 1
 #define OPOS_GFU 1
 
-const uint32_t vdo_dp_modes[1] =  {
-	VDO_MODE_DP(0,		   /* UFP pin cfg supported : none */
+const uint32_t vdo_dp_modes[1] = {
+	VDO_MODE_DP(0, /* UFP pin cfg supported : none */
 		    MODE_DP_PIN_C, /* DFP pin cfg supported */
-		    1,		   /* no usb2.0	signalling in AMode */
-		    CABLE_PLUG,	   /* its a plug */
-		    MODE_DP_V13,   /* DPv1.3 Support, no Gen2 */
-		    MODE_DP_SNK)   /* Its a sink only */
+		    1, /* no usb2.0	signalling in AMode */
+		    CABLE_PLUG, /* its a plug */
+		    MODE_DP_V13, /* DPv1.3 Support, no Gen2 */
+		    MODE_DP_SNK) /* Its a sink only */
 };
 
-const uint32_t vdo_goog_modes[1] =  {
-	VDO_MODE_GOOGLE(MODE_GOOGLE_FU)
-};
+const uint32_t vdo_goog_modes[1] = { VDO_MODE_GOOGLE(MODE_GOOGLE_FU) };
 
 static int svdm_response_modes(int port, uint32_t *payload)
 {
@@ -196,13 +187,15 @@ static int dp_status(int port, uint32_t *payload)
 	if (opos != OPOS_DP)
 		return 0; /* nak */
 
-	payload[1] = VDO_DP_STATUS(0,                /* IRQ_HPD */
-				   (hpd == 1),       /* HPD_HI|LOW */
-				   0,		     /* request exit DP */
-				   0,		     /* request exit USB */
-				   0,		     /* MF pref */
+	payload[1] = VDO_DP_STATUS(0, /* IRQ_HPD */
+				   (hpd == 1), /* HPD_HI|LOW */
+				   0, /* request exit DP */
+				   0, /* request exit USB */
+				   0, /* MF pref */
 				   gpio_get_level(GPIO_PD_SBU_ENABLE),
-				   0,		     /* power low */
+				   0, /* power
+					 low
+				       */
 				   0x2);
 	return 2;
 }
@@ -281,8 +274,7 @@ const struct svdm_response svdm_rsp = {
 	.exit_mode = &svdm_exit_mode,
 };
 
-int pd_custom_vdm(int port, int cnt, uint32_t *payload,
-		  uint32_t **rpayload)
+int pd_custom_vdm(int port, int cnt, uint32_t *payload, uint32_t **rpayload)
 {
 	int rsize;
 
diff --git a/board/collis/battery.c b/board/collis/battery.c
index 5da46e9caa..21c7b80901 100644
--- a/board/collis/battery.c
+++ b/board/collis/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/collis/board.c b/board/collis/board.c
index fe308778a4..6b2c81bc02 100644
--- a/board/collis/board.c
+++ b/board/collis/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -41,7 +41,7 @@
 
 #include "gpio_list.h" /* Must come after other header files. */
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 /* Keyboard scan setting */
 __override struct keyboard_scan_config keyscan_config = {
@@ -76,8 +76,8 @@ static const struct ec_response_keybd_config copano_kb = {
 	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
 };
 
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	return &copano_kb;
 }
@@ -92,7 +92,6 @@ union volteer_cbi_fw_config fw_config_defaults = {
 
 static void board_init(void)
 {
-
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
@@ -179,8 +178,8 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CPU \
-	{ \
+#define THERMAL_CPU              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
@@ -207,8 +206,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_INDUCTOR \
-	{ \
+#define THERMAL_INDUCTOR         \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
@@ -319,32 +318,42 @@ BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
 
 /******************************************************************************/
 /* USBC mux configuration - Tiger Lake includes internal mux */
-static const struct usb_mux usbc0_usb3_mb_retimer = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	.next_mux = NULL,
+static const struct usb_mux_chain usbc0_usb3_mb_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
+	.next = NULL,
 };
 
-static const struct usb_mux usbc1_usb3_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	.next_mux = NULL,
+static const struct usb_mux_chain usbc1_usb3_db_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
+	.next = NULL,
 };
 
-const struct usb_mux usb_muxes[] = {
+const struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc0_usb3_mb_retimer,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc0_usb3_mb_retimer,
 	},
 	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc1_usb3_db_retimer,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc1_usb3_db_retimer,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
@@ -417,23 +426,22 @@ static void ps8815_reset(int port)
 	}
 
 	gpio_set_level(ps8xxx_rst_odl, 0);
-	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS,
-			   PS8815_PWR_H_RST_H_DELAY_MS));
+	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS));
 	gpio_set_level(ps8xxx_rst_odl, 1);
 	msleep(PS8815_FW_INIT_DELAY_MS);
 
 	CPRINTS("[C%d] %s: patching ps8815 registers", port, __func__);
 
-	if (i2c_read8(i2c_port,
-		      PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
+	if (i2c_read8(i2c_port, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) ==
+	    EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f was %02x", val);
 
-	if (i2c_write8(i2c_port,
-		      PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) == EC_SUCCESS)
+	if (i2c_write8(i2c_port, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) ==
+	    EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f set to 0x31");
 
-	if (i2c_read8(i2c_port,
-		      PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
+	if (i2c_read8(i2c_port, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) ==
+	    EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f now %02x", val);
 }
 
@@ -441,8 +449,8 @@ void board_reset_pd_mcu(void)
 {
 	ps8815_reset(USBC_PORT_C0);
 	usb_mux_hpd_update(USBC_PORT_C0, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 	ps8815_reset(USBC_PORT_C1);
 	usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
diff --git a/board/collis/board.h b/board/collis/board.h
index 22f7af1b6c..d9e903c6b3 100644
--- a/board/collis/board.h
+++ b/board/collis/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -28,11 +28,11 @@
 #define CONFIG_POWER_PP5000_CONTROL
 
 #undef NPCX_PWM1_SEL
-#define NPCX_PWM1_SEL 0		/* GPIO C2 is not used as PWM1 */
+#define NPCX_PWM1_SEL 0 /* GPIO C2 is not used as PWM1 */
 
 /* LED defines */
 #define CONFIG_LED_ONOFF_STATES
-#define CONFIG_LED_ONOFF_STATES_BAT_LOW	10
+#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
 
 /* Keyboard features */
 #define CONFIG_KEYBOARD_VIVALDI
@@ -57,34 +57,34 @@
 
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE		BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID		LID_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
 
 /* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
 
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
 
 /*
  * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
  * cables only support up to 60W, the limitation of 45W is for the Collis
  * board.
  */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		45000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 45000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 #undef CONFIG_USBC_RETIMER_INTEL_BB
 #undef CONFIG_USBC_RETIMER_INTEL_BB_RUNTIME_CONFIG
 
 /* USB Type A Features */
-#define USB_PORT_COUNT			1
+#define USB_PORT_COUNT 1
 #define CONFIG_USB_PORT_POWER_DUMB
 
 /* USBC PPC*/
-#define CONFIG_USBC_PPC_SYV682X		/* USBC port C0/C1 */
+#define CONFIG_USBC_PPC_SYV682X /* USBC port C0/C1 */
 
 #undef CONFIG_USB_MUX_RUNTIME_CONFIG
 #undef CONFIG_USB_PD_TCPC_RUNTIME_CONFIG
@@ -99,8 +99,8 @@
 #undef CONFIG_FANS
 
 /* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 
 /*
  * Macros for GPIO signals used in common code that don't match the
@@ -108,47 +108,46 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_DSW_PWROK		GPIO_EC_PCH_DSW_PWROK
-#define GPIO_PG_EC_DSW_PWROK		GPIO_DSW_PWROK
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_LID_OPEN GPIO_EC_LID_OPEN
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK
+#define GPIO_PG_EC_DSW_PWROK GPIO_DSW_PWROK
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
 
 /* I2C Bus Configuration */
 #define CONFIG_I2C
-#define I2C_PORT_ACCEL		I2C_PORT_SENSOR
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_0_MIX	NPCX_I2C_PORT3_0
-#define I2C_PORT_USB_1_MIX	NPCX_I2C_PORT4_1
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_0_MIX NPCX_I2C_PORT3_0
+#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT4_1
+#define I2C_PORT_POWER NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+
+#define I2C_PORT_BATTERY I2C_PORT_POWER
+#define I2C_PORT_CHARGER I2C_PORT_EEPROM
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 #define CONFIG_I2C_CONTROLLER
 
-
 #ifndef __ASSEMBLER__
 
 #include "gpio_signal.h"
@@ -159,10 +158,7 @@ enum battery_type {
 	BATTERY_TYPE_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_COUNT };
 
 enum sensor_id {
 	LID_ACCEL = 0,
@@ -171,11 +167,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 void board_reset_pd_mcu(void);
 void motion_interrupt(enum gpio_signal signal);
diff --git a/board/collis/build.mk b/board/collis/build.mk
index 546bcba8d2..18397fdec3 100644
--- a/board/collis/build.mk
+++ b/board/collis/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/collis/ec.tasklist b/board/collis/ec.tasklist
index ca6d9fbf14..07a91894ed 100644
--- a/board/collis/ec.tasklist
+++ b/board/collis/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/collis/gpio.inc b/board/collis/gpio.inc
index 95e0ca8ba2..51c5f6b144 100644
--- a/board/collis/gpio.inc
+++ b/board/collis/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,7 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
diff --git a/board/collis/led.c b/board/collis/led.c
index 508a5eb585..9220b7a95c 100644
--- a/board/collis/led.c
+++ b/board/collis/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,28 +9,37 @@
 #include "led_common.h"
 #include "led_onoff_states.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
 __override const int led_charge_lvl_1;
 __override const int led_charge_lvl_2 = 95;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]       = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]       = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]	     = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_WHITE,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
 const enum ec_led_id supported_led_ids[] = {
 	EC_LED_ID_BATTERY_LED,
diff --git a/board/collis/sensors.c b/board/collis/sensors.c
index cdf6db971e..e647fe7d61 100644
--- a/board/collis/sensors.c
+++ b/board/collis/sensors.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -36,22 +36,18 @@ static struct bmi_drv_data_t g_bmi160_data;
 static struct icm_drv_data_t g_icm426xx_data;
 
 /* Rotation matrix for the lid accelerometer */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(1), 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
 
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+				       { 0, FLOAT_TO_FP(-1), 0 },
+				       { 0, 0, FLOAT_TO_FP(-1) } };
 
 const mat33_fp_t base_standard_ref_icm = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)},
+	{ 0, FLOAT_TO_FP(1), 0 },
+	{ FLOAT_TO_FP(1), 0, 0 },
+	{ 0, 0, FLOAT_TO_FP(-1) },
 };
 
 struct motion_sensor_t icm426xx_base_accel = {
diff --git a/board/copano/battery.c b/board/copano/battery.c
index add2094b52..85f3d67448 100644
--- a/board/copano/battery.c
+++ b/board/copano/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/copano/board.c b/board/copano/board.c
index efcde2c177..b4a8c5eb20 100644
--- a/board/copano/board.c
+++ b/board/copano/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -42,7 +42,7 @@
 
 #include "gpio_list.h" /* Must come after other header files. */
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 /* Keyboard scan setting */
 __override struct keyboard_scan_config keyscan_config = {
@@ -77,8 +77,8 @@ static const struct ec_response_keybd_config copano_kb = {
 	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
 };
 
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	return &copano_kb;
 }
@@ -93,7 +93,6 @@ union volteer_cbi_fw_config fw_config_defaults = {
 
 static void board_init(void)
 {
-
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
@@ -180,8 +179,8 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CPU \
-	{ \
+#define THERMAL_CPU              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
@@ -208,8 +207,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_INDUCTOR \
-	{ \
+#define THERMAL_INDUCTOR         \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
@@ -251,12 +250,15 @@ void board_reset_pd_mcu(void)
 }
 
 /* USBC mux configuration - Tiger Lake includes internal mux */
-struct usb_mux usbc0_usb4_mb_retimer = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &bb_usb_retimer,
-	.hpd_update = bb_retimer_hpd_update,
-	.i2c_port = I2C_PORT_USB_0_MIX,
-	.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
+struct usb_mux_chain usbc0_usb4_mb_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_0_MIX,
+			.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
+		},
 };
 /*****************************************************************************
  * USB-C MUX/Retimer dynamic configuration.
@@ -265,7 +267,7 @@ static void setup_mux(void)
 {
 	CPRINTS("C0 supports bb-retimer");
 	/* USB-C port 0 have a retimer */
-	usb_muxes[USBC_PORT_C0].next_mux = &usbc0_usb4_mb_retimer;
+	usb_muxes[USBC_PORT_C0].next = &usbc0_usb4_mb_retimer;
 }
 
 __override void board_cbi_init(void)
@@ -277,7 +279,6 @@ __override void board_cbi_init(void)
 	/* Reassign USB_C0_RT_RST_ODL */
 	bb_controls[USBC_PORT_C0].usb_ls_en_gpio = GPIO_USB_C0_LS_EN;
 	bb_controls[USBC_PORT_C0].retimer_rst_gpio = GPIO_USB_C0_RT_RST_ODL;
-
 }
 
 /******************************************************************************/
@@ -353,24 +354,31 @@ BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
 
 /******************************************************************************/
 /* USBC mux configuration - Tiger Lake includes internal mux */
-struct usb_mux usbc1_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+struct usb_mux_chain usbc1_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
-struct usb_mux usb_muxes[] = {
+struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 	},
 	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.next_mux = &usbc1_tcss_usb_mux,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_1_MIX,
-		.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_1_MIX,
+			.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc1_tcss_usb_mux,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
diff --git a/board/copano/board.h b/board/copano/board.h
index 315d7bc8bb..6efd3e88ee 100644
--- a/board/copano/board.h
+++ b/board/copano/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -28,11 +28,11 @@
 #define CONFIG_POWER_PP5000_CONTROL
 
 #undef NPCX_PWM1_SEL
-#define NPCX_PWM1_SEL 0		/* GPIO C2 is not used as PWM1 */
+#define NPCX_PWM1_SEL 0 /* GPIO C2 is not used as PWM1 */
 
 /* LED defines */
 #define CONFIG_LED_ONOFF_STATES
-#define CONFIG_LED_ONOFF_STATES_BAT_LOW	10
+#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
 
 /* Keyboard features */
 #define CONFIG_KEYBOARD_VIVALDI
@@ -57,23 +57,23 @@
 
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE		BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID		LID_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
 
 /* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
 
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
 
 /*
  * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
  * cables only support up to 60W.
  */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		45000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	15000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 45000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 15000
 
 #define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
 
@@ -82,15 +82,15 @@
 
 /* Enabling USB4 mode */
 #define CONFIG_USB_PD_USB4
-#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR	0x40
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x40
+#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x40
+#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x40
 
 /* USB Type A Features */
-#define USB_PORT_COUNT			1
+#define USB_PORT_COUNT 1
 #define CONFIG_USB_PORT_POWER_DUMB
 
 /* USBC PPC*/
-#define CONFIG_USBC_PPC_SYV682X		/* USBC port C0/C1 */
+#define CONFIG_USBC_PPC_SYV682X /* USBC port C0/C1 */
 #define CONFIG_USB_PD_FRS_PPC
 
 #undef CONFIG_USB_PD_TCPC_RUNTIME_CONFIG
@@ -104,8 +104,8 @@
 #undef CONFIG_FANS
 
 /* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 
 /*
  * Macros for GPIO signals used in common code that don't match the
@@ -113,47 +113,46 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_DSW_PWROK		GPIO_EC_PCH_DSW_PWROK
-#define GPIO_PG_EC_DSW_PWROK		GPIO_DSW_PWROK
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_LID_OPEN GPIO_EC_LID_OPEN
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK
+#define GPIO_PG_EC_DSW_PWROK GPIO_DSW_PWROK
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
 
 /* I2C Bus Configuration */
 #define CONFIG_I2C
-#define I2C_PORT_ACCEL		I2C_PORT_SENSOR
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_0_MIX	NPCX_I2C_PORT3_0
-#define I2C_PORT_USB_1_MIX	NPCX_I2C_PORT4_1
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_0_MIX NPCX_I2C_PORT3_0
+#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT4_1
+#define I2C_PORT_POWER NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+
+#define I2C_PORT_BATTERY I2C_PORT_POWER
+#define I2C_PORT_CHARGER I2C_PORT_EEPROM
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 #define CONFIG_I2C_CONTROLLER
 
-
 #ifndef __ASSEMBLER__
 
 #include "gpio_signal.h"
@@ -164,10 +163,7 @@ enum battery_type {
 	BATTERY_TYPE_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_COUNT };
 
 enum sensor_id {
 	LID_ACCEL = 0,
@@ -176,11 +172,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 void board_reset_pd_mcu(void);
 void motion_interrupt(enum gpio_signal signal);
diff --git a/board/copano/build.mk b/board/copano/build.mk
index 838d6a16ce..c994631759 100644
--- a/board/copano/build.mk
+++ b/board/copano/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/copano/ec.tasklist b/board/copano/ec.tasklist
index 3e20d8ae39..c29125d517 100644
--- a/board/copano/ec.tasklist
+++ b/board/copano/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/copano/gpio.inc b/board/copano/gpio.inc
index 52be1271f1..c6271c20f4 100644
--- a/board/copano/gpio.inc
+++ b/board/copano/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,7 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
diff --git a/board/copano/led.c b/board/copano/led.c
index a5b535000a..15daf7b2b9 100644
--- a/board/copano/led.c
+++ b/board/copano/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,28 +9,37 @@
 #include "led_common.h"
 #include "led_onoff_states.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
 __override const int led_charge_lvl_1;
 __override const int led_charge_lvl_2 = 95;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]       = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]       = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]	     = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_WHITE,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
 const enum ec_led_id supported_led_ids[] = {
 	EC_LED_ID_BATTERY_LED,
diff --git a/board/copano/sensors.c b/board/copano/sensors.c
index 8aa9f5888b..3884c5cc93 100644
--- a/board/copano/sensors.c
+++ b/board/copano/sensors.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -36,22 +36,18 @@ static struct bmi_drv_data_t g_bmi160_data;
 static struct icm_drv_data_t g_icm426xx_data;
 
 /* Rotation matrix for the lid accelerometer */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, FLOAT_TO_FP(1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+				       { 0, FLOAT_TO_FP(-1), 0 },
+				       { 0, 0, FLOAT_TO_FP(-1) } };
 
 const mat33_fp_t base_standard_ref_icm = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)},
+	{ 0, FLOAT_TO_FP(1), 0 },
+	{ FLOAT_TO_FP(1), 0, 0 },
+	{ 0, 0, FLOAT_TO_FP(-1) },
 };
 
 struct motion_sensor_t icm426xx_base_accel = {
diff --git a/board/coral/battery.c b/board/coral/battery.c
index 8dfb05d631..3b105c90ca 100644
--- a/board/coral/battery.c
+++ b/board/coral/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,7 +19,7 @@
 #include "i2c.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 /* Number of writes needed to invoke battery cutoff command */
 #define SHIP_MODE_WRITES 2
@@ -412,7 +412,8 @@ BUILD_ASSERT(ARRAY_SIZE(info) == BATTERY_TYPE_COUNT);
 static inline const struct board_batt_params *board_get_batt_params(void)
 {
 	return &info[board_battery_type == BATTERY_TYPE_COUNT ?
-			DEFAULT_BATTERY_TYPE : board_battery_type];
+			     DEFAULT_BATTERY_TYPE :
+			     board_battery_type];
 }
 
 /* Get type of the battery connected on the board */
@@ -424,14 +425,16 @@ static int board_get_battery_type(void)
 	if (!battery_manufacturer_name(manu_name, sizeof(manu_name))) {
 		for (i = 0; i < BATTERY_TYPE_COUNT; i++) {
 			if (!strcasecmp(manu_name,
-				info[i].fuel_gauge.manuf_name)) {
+					info[i].fuel_gauge.manuf_name)) {
 				if (info[i].fuel_gauge.device_name == NULL) {
 					board_battery_type = i;
 					break;
-				} else if (!battery_device_name(device_name,
-					sizeof(device_name))) {
+				} else if (!battery_device_name(
+						   device_name,
+						   sizeof(device_name))) {
 					if (!strcasecmp(device_name,
-					info[i].fuel_gauge.device_name)) {
+							info[i].fuel_gauge
+								.device_name)) {
 						board_battery_type = i;
 						break;
 					}
@@ -496,7 +499,7 @@ static int charger_should_discharge_on_ac(struct charge_state_data *curr)
 
 	/* Do not discharge on AC if the battery is still waking up */
 	if (!(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
-		!(curr->batt.status & STATUS_FULLY_CHARGED))
+	    !(curr->batt.status & STATUS_FULLY_CHARGED))
 		return 0;
 
 	/*
@@ -513,8 +516,8 @@ static int charger_should_discharge_on_ac(struct charge_state_data *curr)
 	 * and suspend USB charging and DC/DC converter.
 	 */
 	if (!battery_is_cut_off() &&
-		!(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
-		(curr->batt.status & STATUS_FULLY_CHARGED))
+	    !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
+	    (curr->batt.status & STATUS_FULLY_CHARGED))
 		return 1;
 
 	/*
@@ -548,13 +551,13 @@ enum battery_present battery_hw_present(void)
 	return gpio_get_level(GPIO_EC_BATT_PRES_L) ? BP_NO : BP_YES;
 }
 
-
 static int battery_init(void)
 {
 	int batt_status;
 
-	return battery_status(&batt_status) ? 0 :
-		!!(batt_status & STATUS_INITIALIZED);
+	return battery_status(&batt_status) ?
+		       0 :
+		       !!(batt_status & STATUS_INITIALIZED);
 }
 
 /* Allow booting now that the battery has woke up */
@@ -595,12 +598,13 @@ static int battery_check_disconnect(void)
 	/* Read the status of charge/discharge FETs */
 	if (info[board_battery_type].fuel_gauge.fet.mfgacc_support == 1) {
 		rv = sb_read_mfgacc(PARAM_OPERATION_STATUS,
-				SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data));
+				    SB_ALT_MANUFACTURER_ACCESS, data,
+				    sizeof(data));
 		/* Get the lowest 16bits of the OperationStatus() data */
 		reg = data[2] | data[3] << 8;
 	} else
 		rv = sb_read(info[board_battery_type].fuel_gauge.fet.reg_addr,
-					&reg);
+			     &reg);
 
 	if (rv)
 		return BATTERY_DISCONNECT_ERROR;
@@ -650,7 +654,7 @@ enum battery_present battery_is_present(void)
 		 * error due to a failed sb_read.
 		 */
 		battery_report_present_timer_started = 0;
-	}  else if (batt_pres == BP_YES && batt_pres_prev == BP_NO &&
+	} else if (batt_pres == BP_YES && batt_pres_prev == BP_NO &&
 		   !battery_report_present_timer_started) {
 		/*
 		 * Wait 1/2 second before reporting present if it was
@@ -674,11 +678,10 @@ int board_battery_initialized(void)
 	return battery_hw_present() == batt_pres_prev;
 }
 
-
 /* Customs options controllable by host command. */
 #define PARAM_FASTCHARGE (CS_PARAM_CUSTOM_PROFILE_MIN + 0)
-#define PARAM_LEARN_MODE	0x10001
-#define PARAM_DISCONNECT_STATE	0x10002
+#define PARAM_LEARN_MODE 0x10001
+#define PARAM_DISCONNECT_STATE 0x10002
 
 enum ec_status charger_profile_override_get_param(uint32_t param,
 						  uint32_t *value)
diff --git a/board/coral/board.c b/board/coral/board.c
index 21729489bc..c63a2f6ddc 100644
--- a/board/coral/board.c
+++ b/board/coral/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -33,6 +33,7 @@
 #include "math_util.h"
 #include "motion_sense.h"
 #include "motion_lid.h"
+#include "panic.h"
 #include "power.h"
 #include "power_button.h"
 #include "pwm.h"
@@ -53,15 +54,15 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define IN_ALL_SYS_PG	POWER_SIGNAL_MASK(X86_ALL_SYS_PG)
-#define IN_PGOOD_PP3300	POWER_SIGNAL_MASK(X86_PGOOD_PP3300)
-#define IN_PGOOD_PP5000	POWER_SIGNAL_MASK(X86_PGOOD_PP5000)
+#define IN_ALL_SYS_PG POWER_SIGNAL_MASK(X86_ALL_SYS_PG)
+#define IN_PGOOD_PP3300 POWER_SIGNAL_MASK(X86_PGOOD_PP3300)
+#define IN_PGOOD_PP5000 POWER_SIGNAL_MASK(X86_PGOOD_PP5000)
 
-#define USB_PD_PORT_ANX74XX	0
-#define USB_PD_PORT_PS8751	1
+#define USB_PD_PORT_ANX74XX 0
+#define USB_PD_PORT_PS8751 1
 
 static int sku_id;
 
@@ -128,66 +129,51 @@ void tablet_mode_interrupt(enum gpio_signal signal)
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* Vfs = Vref = 2.816V, 10-bit unsigned reading */
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0
-	},
-	[ADC_TEMP_SENSOR_AMB] = {
-		"AMBIENT", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0
-	},
-	[ADC_BOARD_ID] = {
-		"BRD_ID", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0
-	},
-	[ADC_BOARD_SKU_1] = {
-		"BRD_SKU_1", NPCX_ADC_CH3, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0
-	},
-	[ADC_BOARD_SKU_0] = {
-		"BRD_SKU_0", NPCX_ADC_CH4, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0
-	},
+	[ADC_TEMP_SENSOR_CHARGER] = { "CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				      ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_AMB] = { "AMBIENT", NPCX_ADC_CH1, ADC_MAX_VOLT,
+				  ADC_READ_MAX + 1, 0 },
+	[ADC_BOARD_ID] = { "BRD_ID", NPCX_ADC_CH2, ADC_MAX_VOLT,
+			   ADC_READ_MAX + 1, 0 },
+	[ADC_BOARD_SKU_1] = { "BRD_SKU_1", NPCX_ADC_CH3, ADC_MAX_VOLT,
+			      ADC_READ_MAX + 1, 0 },
+	[ADC_BOARD_SKU_0] = { "BRD_SKU_0", NPCX_ADC_CH4, ADC_MAX_VOLT,
+			      ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] =   { 4, PWM_CONFIG_DSLEEP, 100 },
+	[PWM_CH_KBLIGHT] = { 4, PWM_CONFIG_DSLEEP, 100 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
-const struct i2c_port_t i2c_ports[]  = {
-	{
-		.name = "tcpc0",
-		.port = NPCX_I2C_PORT0_0,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_USB_C0_PD_SCL,
-		.sda  = GPIO_EC_I2C_USB_C0_PD_SDA
-	},
-	{
-		.name = "tcpc1",
-		.port = NPCX_I2C_PORT0_1,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_USB_C1_PD_SCL,
-		.sda  = GPIO_EC_I2C_USB_C1_PD_SDA
-	},
-	{
-		.name = "accelgyro",
-		.port = I2C_PORT_GYRO,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_GYRO_SCL,
-		.sda  = GPIO_EC_I2C_GYRO_SDA
-	},
-	{
-		.name = "sensors",
-		.port = NPCX_I2C_PORT2,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_SENSOR_SCL,
-		.sda  = GPIO_EC_I2C_SENSOR_SDA
-	},
-	{
-		.name = "batt",
-		.port = NPCX_I2C_PORT3,
-		.kbps = 100,
-		.scl  = GPIO_EC_I2C_POWER_SCL,
-		.sda  = GPIO_EC_I2C_POWER_SDA
-	},
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "tcpc0",
+	  .port = NPCX_I2C_PORT0_0,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_USB_C0_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C0_PD_SDA },
+	{ .name = "tcpc1",
+	  .port = NPCX_I2C_PORT0_1,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_USB_C1_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C1_PD_SDA },
+	{ .name = "accelgyro",
+	  .port = I2C_PORT_GYRO,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_GYRO_SCL,
+	  .sda = GPIO_EC_I2C_GYRO_SDA },
+	{ .name = "sensors",
+	  .port = NPCX_I2C_PORT2,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_SENSOR_SCL,
+	  .sda = GPIO_EC_I2C_SENSOR_SDA },
+	{ .name = "batt",
+	  .port = NPCX_I2C_PORT3,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_POWER_SCL,
+	  .sda = GPIO_EC_I2C_POWER_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -303,17 +289,21 @@ static int ps8751_tune_mux(const struct usb_mux *me)
 	return EC_SUCCESS;
 }
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_ANX74XX] = {
-		.usb_port = USB_PD_PORT_ANX74XX,
-		.driver = &anx74xx_tcpm_usb_mux_driver,
-		.hpd_update = &anx74xx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_ANX74XX,
+			.driver = &anx74xx_tcpm_usb_mux_driver,
+			.hpd_update = &anx74xx_tcpc_update_hpd_status,
+		},
 	},
 	[USB_PD_PORT_PS8751] = {
-		.usb_port = USB_PD_PORT_PS8751,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-		.board_init = &ps8751_tune_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_PS8751,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			.board_init = &ps8751_tune_mux,
+		},
 	}
 };
 
@@ -419,28 +409,28 @@ static void board_tcpc_init(void)
 	gpio_enable_interrupt(GPIO_USB_C0_CABLE_DET);
 #endif
 	/*
-	* Initialize HPD to low; after sysjump SOC needs to see
-	* HPD pulse to enable video path
-	*/
+	 * Initialize HPD to low; after sysjump SOC needs to see
+	 * HPD pulse to enable video path
+	 */
 	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
 		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
 DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_DEFAULT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp,
-				 .idx = 0},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
+	[TEMP_SENSOR_BATTERY] = { .name = "Battery",
+				  .type = TEMP_SENSOR_TYPE_BATTERY,
+				  .read = charge_get_battery_temp,
+				  .idx = 0 },
+	[TEMP_SENSOR_AMBIENT] = { .name = "Ambient",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_51k1_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_AMB },
+	[TEMP_SENSOR_CHARGER] = { .name = "Charger",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_13k7_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_CHARGER },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -564,8 +554,8 @@ int board_set_active_charge_port(int charge_port)
  * @param charge_ma     Desired charge limit (mA).
  * @param charge_mv     Negotiated charge voltage (mV).
  */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	/* Enable charging trigger by BC1.2 detection */
 	int bc12_enable = (supplier == CHARGE_SUPPLIER_BC12_CDP ||
@@ -577,8 +567,8 @@ void board_set_charge_limit(int port, int supplier, int charge_ma,
 		return;
 
 	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-				   CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 /**
@@ -688,17 +678,17 @@ void board_hibernate_late(void)
 	int i;
 	const uint32_t hibernate_pins[][2] = {
 		/* Turn off LEDs in hibernate */
-		{GPIO_BAT_LED_BLUE, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_BAT_LED_AMBER, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_LID_OPEN, GPIO_INT_RISING | GPIO_PULL_DOWN},
+		{ GPIO_BAT_LED_BLUE, GPIO_INPUT | GPIO_PULL_UP },
+		{ GPIO_BAT_LED_AMBER, GPIO_INPUT | GPIO_PULL_UP },
+		{ GPIO_LID_OPEN, GPIO_INT_RISING | GPIO_PULL_DOWN },
 
 		/*
 		 * BD99956 handles charge input automatically. We'll disable
 		 * charge output in hibernate. Charger will assert ACOK_OD
 		 * when VBUS or VCC are plugged in.
 		 */
-		{GPIO_USB_C0_5V_EN,       GPIO_INPUT  | GPIO_PULL_DOWN},
-		{GPIO_USB_C1_5V_EN,       GPIO_INPUT  | GPIO_PULL_DOWN},
+		{ GPIO_USB_C0_5V_EN, GPIO_INPUT | GPIO_PULL_DOWN },
+		{ GPIO_USB_C1_5V_EN, GPIO_INPUT | GPIO_PULL_DOWN },
 	};
 
 	/* Change GPIOs' state in hibernate for better power consumption */
@@ -725,17 +715,13 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0,  0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+				       { FLOAT_TO_FP(1), 0, 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
 
-const mat33_fp_t mag_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0,  FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t mag_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				      { 0, FLOAT_TO_FP(1), 0 },
+				      { 0, 0, FLOAT_TO_FP(-1) } };
 
 /* sensor private data */
 static struct kionix_accel_data g_kx022_data;
@@ -845,8 +831,8 @@ static void board_set_motion_sensor_count(uint8_t sku_id)
 	 * sensor. If a new SKU id is used that is not in the table, then the
 	 * number of motion sensors will remain as ARRAY_SIZE(motion_sensors).
 	 */
-	motion_sensor_count = SKU_IS_CONVERTIBLE(sku_id) ?
-		ARRAY_SIZE(motion_sensors) : 0;
+	motion_sensor_count =
+		SKU_IS_CONVERTIBLE(sku_id) ? ARRAY_SIZE(motion_sensors) : 0;
 
 	CPRINTS("Motion Sensor Count = %d", motion_sensor_count);
 }
@@ -857,11 +843,11 @@ struct {
 } const coral_board_versions[] = {
 	/* Vin = 3.3V, Ideal voltage, R2 values listed below */
 	/* R1 = 51.1 kOhm */
-	{ BOARD_VERSION_1, 200 },  /* 124 mV, 2.0 Kohm */
-	{ BOARD_VERSION_2, 366 },  /* 278 mV, 4.7 Kohm */
-	{ BOARD_VERSION_3, 550 },  /* 456 mV, 8.2  Kohm */
-	{ BOARD_VERSION_4, 752 },  /* 644 mV, 12.4 Kohm */
-	{ BOARD_VERSION_5, 927},   /* 860 mV, 18.0 Kohm */
+	{ BOARD_VERSION_1, 200 }, /* 124 mV, 2.0 Kohm */
+	{ BOARD_VERSION_2, 366 }, /* 278 mV, 4.7 Kohm */
+	{ BOARD_VERSION_3, 550 }, /* 456 mV, 8.2  Kohm */
+	{ BOARD_VERSION_4, 752 }, /* 644 mV, 12.4 Kohm */
+	{ BOARD_VERSION_5, 927 }, /* 860 mV, 18.0 Kohm */
 	{ BOARD_VERSION_6, 1073 }, /* 993 mV, 22.0 Kohm */
 	{ BOARD_VERSION_7, 1235 }, /* 1152 mV, 27.4 Kohm */
 	{ BOARD_VERSION_8, 1386 }, /* 1318 mV, 34.0 Kohm */
@@ -948,15 +934,15 @@ static void print_form_factor_list(int low, int high)
 	if (high > 255)
 		high = 255;
 	for (id = low; id <= high; id++) {
-		ccprintf("SKU ID %03d: %s\n", id, SKU_IS_CONVERTIBLE(id) ?
-			 "Convertible" : "Clamshell");
+		ccprintf("SKU ID %03d: %s\n", id,
+			 SKU_IS_CONVERTIBLE(id) ? "Convertible" : "Clamshell");
 		/* Don't print too many lines at once */
 		if (!(++count % 5))
 			msleep(20);
 	}
 }
 
-static int command_sku(int argc, char **argv)
+static int command_sku(int argc, const char **argv)
 {
 	enum adc_channel chan;
 
@@ -999,8 +985,7 @@ static int command_sku(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(sku, command_sku,
-			"<board|line0|line1|form [low high]>",
+DECLARE_CONSOLE_COMMAND(sku, command_sku, "<board|line0|line1|form [low high]>",
 			"Get board id, sku, form factor");
 
 __override uint32_t board_get_sku_id(void)
diff --git a/board/coral/board.h b/board/coral/board.h
index 4a1709e7a9..bc6226152c 100644
--- a/board/coral/board.h
+++ b/board/coral/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,7 +12,7 @@
  * By default, enable all console messages except Events:
  * The sensor stack is generating a lot of activity.
  */
-#define CC_DEFAULT     (CC_ALL & ~CC_MASK(CC_EVENTS))
+#define CC_DEFAULT (CC_ALL & ~CC_MASK(CC_EVENTS))
 #undef CONFIG_HOSTCMD_DEBUG_MODE
 #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
 
@@ -23,14 +23,14 @@
 #define CONFIG_CMD_ACCEL_INFO
 #define CONFIG_CMD_BATT_MFG_ACCESS
 #define CONFIG_CMD_CHARGER_ADC_AMON_BMON
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 #define BD9995X_IOUT_GAIN_SELECT \
-		BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V
+	BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V
 
 #define CONFIG_CHARGER_PSYS_READ
 #define BD9995X_PSYS_GAIN_SELECT \
-		BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_02UAW
+	BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_02UAW
 
 #define CONFIG_CMD_I2C_STRESS_TEST
 #define CONFIG_CMD_I2C_STRESS_TEST_ACCEL
@@ -44,7 +44,7 @@
 #define CONFIG_PORT80_HISTORY_LEN 256
 
 /* Battery */
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY  "LION"
+#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
 #define CONFIG_BATTERY_CUT_OFF
 #define CONFIG_BATTERY_HW_PRESENT_CUSTOM
 #define CONFIG_BATTERY_LEVEL_NEAR_FULL 94
@@ -90,7 +90,7 @@
 #define CONFIG_USB_PD_PORT_MAX_COUNT 2
 #define CONFIG_USB_PD_VBUS_DETECT_CHARGER
 #define CONFIG_USB_PD_TCPC_LOW_POWER
-#define CONFIG_USB_PD_TCPM_MUX  /* for both PS8751 and ANX3429 */
+#define CONFIG_USB_PD_TCPM_MUX /* for both PS8751 and ANX3429 */
 #define CONFIG_USB_PD_TCPM_ANX3429
 #define CONFIG_USB_PD_TCPM_PS8751
 #define CONFIG_USB_PD_TCPM_TCPCI
@@ -117,11 +117,11 @@
 /* EC */
 #define CONFIG_ADC
 #define CONFIG_EXTPOWER_GPIO
-#undef   CONFIG_EXTPOWER_DEBOUNCE_MS
-#define  CONFIG_EXTPOWER_DEBOUNCE_MS 1000
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
+#define CONFIG_EXTPOWER_DEBOUNCE_MS 1000
 #define CONFIG_FPU
 /* Region sizes are not a power of 2 so we can't use MPU */
-#undef  CONFIG_MPU
+#undef CONFIG_MPU
 #define CONFIG_HOSTCMD_FLASH_SPI_INFO
 #define CONFIG_I2C
 #define CONFIG_I2C_CONTROLLER
@@ -150,7 +150,7 @@
 #define CONFIG_WIRELESS
 #define CONFIG_WIRELESS_SUSPEND EC_WIRELESS_SWITCH_WLAN_POWER
 #define CONFIG_WLAN_POWER_ACTIVE_LOW
-#define  WIRELESS_GPIO_WLAN_POWER GPIO_WIRELESS_GPIO_WLAN_POWER
+#define WIRELESS_GPIO_WLAN_POWER GPIO_WIRELESS_GPIO_WLAN_POWER
 #define CONFIG_PWR_STATE_DISCHARGE_FULL
 
 /*
@@ -168,7 +168,7 @@
 
 #define CONFIG_FLASH_SIZE_BYTES 524288
 #define CONFIG_SPI_FLASH_REGS
-#define CONFIG_SPI_FLASH_W25Q40	/* FIXME: Should be GD25LQ40? */
+#define CONFIG_SPI_FLASH_W25Q40 /* FIXME: Should be GD25LQ40? */
 
 /*
  * Enable 1 slot of secure temporary storage to support
@@ -178,19 +178,19 @@
 #define CONFIG_VSTORE_SLOT_COUNT 1
 
 /* Optional feature - used by nuvoton */
-#define NPCX_UART_MODULE2    1 /* 0:GPIO10/11 1:GPIO64/65 as UART */
-#define NPCX_JTAG_MODULE2    0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/
+#define NPCX_UART_MODULE2 1 /* 0:GPIO10/11 1:GPIO64/65 as UART */
+#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/
 /* FIXME(dhendrix): these pins are just normal GPIOs on Coral. Do we need
  * to change some other setting to put them in GPIO mode? */
-#define NPCX_TACH_SEL2       0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
+#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
 
 /* I2C ports */
-#define I2C_PORT_GYRO			NPCX_I2C_PORT1
-#define I2C_PORT_LID_ACCEL		NPCX_I2C_PORT2
-#define I2C_PORT_BATTERY		NPCX_I2C_PORT3
-#define I2C_PORT_CHARGER		NPCX_I2C_PORT3
+#define I2C_PORT_GYRO NPCX_I2C_PORT1
+#define I2C_PORT_LID_ACCEL NPCX_I2C_PORT2
+#define I2C_PORT_BATTERY NPCX_I2C_PORT3
+#define I2C_PORT_CHARGER NPCX_I2C_PORT3
 /* Accelerometer and Gyroscope are the same device. */
-#define I2C_PORT_ACCEL			I2C_PORT_GYRO
+#define I2C_PORT_ACCEL I2C_PORT_GYRO
 
 /* Sensors */
 #define CONFIG_MKBP_EVENT
@@ -213,7 +213,6 @@
 /* Depends on how fast the AP boots and typical ODRs */
 #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
 
-
 #ifndef __ASSEMBLER__
 
 #include "gpio_signal.h"
@@ -221,11 +220,11 @@
 
 /* ADC signal */
 enum adc_channel {
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC0 */
-	ADC_TEMP_SENSOR_AMB,		/* ADC1 */
-	ADC_BOARD_ID,			/* ADC2 */
-	ADC_BOARD_SKU_1,		/* ADC3 */
-	ADC_BOARD_SKU_0,		/* ADC4 */
+	ADC_TEMP_SENSOR_CHARGER, /* ADC0 */
+	ADC_TEMP_SENSOR_AMB, /* ADC1 */
+	ADC_BOARD_ID, /* ADC2 */
+	ADC_BOARD_SKU_1, /* ADC3 */
+	ADC_BOARD_SKU_0, /* ADC4 */
 	ADC_CH_COUNT
 };
 
@@ -283,16 +282,16 @@ enum coral_board_version {
  * delay to turn on the power supply max is ~16ms.
  * delay to turn off the power supply max is about ~180ms.
  */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* delay to turn on/off vconn */
 
 /* Define typical operating power and max power */
 #define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       45000
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_VOLTAGE_MV     20000
+#define PD_MAX_POWER_MW 45000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Reset PD MCU */
 void board_reset_pd_mcu(void);
diff --git a/board/coral/build.mk b/board/coral/build.mk
index 728d027803..470e439b13 100644
--- a/board/coral/build.mk
+++ b/board/coral/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/coral/ec.tasklist b/board/coral/ec.tasklist
index eeebc0cc59..bc8668a1db 100644
--- a/board/coral/ec.tasklist
+++ b/board/coral/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/coral/gpio.inc b/board/coral/gpio.inc
index da15615c86..7f09fe0735 100644
--- a/board/coral/gpio.inc
+++ b/board/coral/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/coral/led.c b/board/coral/led.c
index 2a1e39946c..8af0f6f3e2 100644
--- a/board/coral/led.c
+++ b/board/coral/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -28,8 +28,7 @@
 #define LED_POWER_ON_TICKS (LED_POWER_BLINK_ON_MSEC / HOOK_TICK_INTERVAL_MS)
 #define LED_POWER_OFF_TICKS (LED_POWER_BLINK_OFF_MSEC / HOOK_TICK_INTERVAL_MS)
 
-const enum ec_led_id supported_led_ids[] = {
-			EC_LED_ID_BATTERY_LED};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -37,18 +36,14 @@ const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 #define GPIO_LED_COLOR_2 GPIO_BAT_LED_BLUE
 #define GPIO_LED_COLOR_3 GPIO_POW_LED
 
-enum led_phase {
-	LED_PHASE_0,
-	LED_PHASE_1,
-	LED_NUM_PHASES
-};
+enum led_phase { LED_PHASE_0, LED_PHASE_1, LED_NUM_PHASES };
 
 enum led_color {
 	LED_OFF,
 	LED_COLOR_1,
 	LED_COLOR_2,
 	LED_COLOR_BOTH,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 enum led_states {
@@ -85,37 +80,37 @@ struct led_info {
 
 /* COLOR_1 = Amber, COLOR_2 = Blue */
 static const struct led_descriptor led_default_state_table[][LED_NUM_PHASES] = {
-	{ {LED_COLOR_1, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} },
-	{ {LED_COLOR_2, LED_INDEFINITE}, {LED_COLOR_1, LED_INDEFINITE} },
-	{ {LED_COLOR_2, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} },
-	{ {LED_COLOR_2, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} },
-	{ {LED_COLOR_1, 1 * LED_ONE_SEC }, {LED_OFF, 3 * LED_ONE_SEC} },
-	{ {LED_OFF, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} },
-	{ {LED_COLOR_1, 1 * LED_ONE_SEC}, {LED_OFF, 1 * LED_ONE_SEC} },
-	{ {LED_COLOR_1, 2 * LED_ONE_SEC}, {LED_COLOR_2, 2 * LED_ONE_SEC} },
+	{ { LED_COLOR_1, LED_INDEFINITE }, { LED_OFF, LED_INDEFINITE } },
+	{ { LED_COLOR_2, LED_INDEFINITE }, { LED_COLOR_1, LED_INDEFINITE } },
+	{ { LED_COLOR_2, LED_INDEFINITE }, { LED_OFF, LED_INDEFINITE } },
+	{ { LED_COLOR_2, LED_INDEFINITE }, { LED_OFF, LED_INDEFINITE } },
+	{ { LED_COLOR_1, 1 * LED_ONE_SEC }, { LED_OFF, 3 * LED_ONE_SEC } },
+	{ { LED_OFF, LED_INDEFINITE }, { LED_OFF, LED_INDEFINITE } },
+	{ { LED_COLOR_1, 1 * LED_ONE_SEC }, { LED_OFF, 1 * LED_ONE_SEC } },
+	{ { LED_COLOR_1, 2 * LED_ONE_SEC }, { LED_COLOR_2, 2 * LED_ONE_SEC } },
 };
 
 /* COLOR_1 = Green, COLOR_2 = Red */
 static const struct led_descriptor led_robo_state_table[][LED_NUM_PHASES] = {
-	{ {LED_COLOR_2, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} },
-	{ {LED_COLOR_BOTH, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} },
-	{ {LED_COLOR_1, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} },
-	{ {LED_OFF, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} },
-	{ {LED_OFF, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} },
-	{ {LED_OFF, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} },
-	{ {LED_COLOR_2, 1 * LED_ONE_SEC}, {LED_OFF, 1 * LED_ONE_SEC} },
-	{ {LED_COLOR_2, 2 * LED_ONE_SEC}, {LED_COLOR_1, 2 * LED_ONE_SEC} },
+	{ { LED_COLOR_2, LED_INDEFINITE }, { LED_OFF, LED_INDEFINITE } },
+	{ { LED_COLOR_BOTH, LED_INDEFINITE }, { LED_OFF, LED_INDEFINITE } },
+	{ { LED_COLOR_1, LED_INDEFINITE }, { LED_OFF, LED_INDEFINITE } },
+	{ { LED_OFF, LED_INDEFINITE }, { LED_OFF, LED_INDEFINITE } },
+	{ { LED_OFF, LED_INDEFINITE }, { LED_OFF, LED_INDEFINITE } },
+	{ { LED_OFF, LED_INDEFINITE }, { LED_OFF, LED_INDEFINITE } },
+	{ { LED_COLOR_2, 1 * LED_ONE_SEC }, { LED_OFF, 1 * LED_ONE_SEC } },
+	{ { LED_COLOR_2, 2 * LED_ONE_SEC }, { LED_COLOR_1, 2 * LED_ONE_SEC } },
 };
 
 static const struct led_descriptor led_nasher_state_table[][LED_NUM_PHASES] = {
-	{ {LED_COLOR_1, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} },
-	{ {LED_COLOR_2, LED_INDEFINITE}, {LED_COLOR_1, LED_INDEFINITE} },
-	{ {LED_COLOR_2, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} },
-	{ {LED_COLOR_2, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} },
-	{ {LED_COLOR_2, 1 * LED_ONE_SEC}, {LED_OFF, 1 * LED_ONE_SEC} },
-	{ {LED_OFF, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} },
-	{ {LED_COLOR_1, 1 * LED_ONE_SEC}, {LED_OFF, 1 * LED_ONE_SEC} },
-	{ {LED_COLOR_1, 2 * LED_ONE_SEC}, {LED_COLOR_2, 2 * LED_ONE_SEC} },
+	{ { LED_COLOR_1, LED_INDEFINITE }, { LED_OFF, LED_INDEFINITE } },
+	{ { LED_COLOR_2, LED_INDEFINITE }, { LED_COLOR_1, LED_INDEFINITE } },
+	{ { LED_COLOR_2, LED_INDEFINITE }, { LED_OFF, LED_INDEFINITE } },
+	{ { LED_COLOR_2, LED_INDEFINITE }, { LED_OFF, LED_INDEFINITE } },
+	{ { LED_COLOR_2, 1 * LED_ONE_SEC }, { LED_OFF, 1 * LED_ONE_SEC } },
+	{ { LED_OFF, LED_INDEFINITE }, { LED_OFF, LED_INDEFINITE } },
+	{ { LED_COLOR_1, 1 * LED_ONE_SEC }, { LED_OFF, 1 * LED_ONE_SEC } },
+	{ { LED_COLOR_1, 2 * LED_ONE_SEC }, { LED_COLOR_2, 2 * LED_ONE_SEC } },
 };
 
 static struct led_info led;
@@ -176,7 +171,7 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 
 static enum led_states led_get_state(void)
 {
-	int  charge_lvl;
+	int charge_lvl;
 	enum led_states new_state = LED_NUM_STATES;
 
 	switch (charge_get_state()) {
@@ -185,7 +180,8 @@ static enum led_states led_get_state(void)
 		charge_lvl = charge_get_percent();
 		/* Determine which charge state to use */
 		new_state = charge_lvl <= led.charge_lvl_1 ?
-			STATE_CHARGING_LVL_1 : STATE_CHARGING_LVL_2;
+				    STATE_CHARGING_LVL_1 :
+				    STATE_CHARGING_LVL_2;
 		break;
 	case PWR_STATE_DISCHARGE_FULL:
 		if (extpower_is_present()) {
@@ -208,10 +204,10 @@ static enum led_states led_get_state(void)
 		new_state = STATE_CHARGING_LVL_3;
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (charge_get_flags() & CHARGE_FLAG_FORCE_IDLE)
-			new_state = STATE_FACTORY_TEST;
-		else
-			new_state = STATE_DISCHARGE_S0;
+		new_state = STATE_DISCHARGE_S0;
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		new_state = STATE_FACTORY_TEST;
 		break;
 	default:
 		/* Other states don't alter LED behavior */
@@ -248,11 +244,13 @@ static void led_update_battery(void)
 		int period;
 
 		period = led.state_table[led.state][LED_PHASE_0].time +
-			led.state_table[led.state][LED_PHASE_1].time;
+			 led.state_table[led.state][LED_PHASE_1].time;
 		if (period)
-			phase = ticks % period <
-				led.state_table[led.state][LED_PHASE_0].time ?
-				0 : 1;
+			phase = ticks % period < led.state_table[led.state]
+								[LED_PHASE_0]
+									.time ?
+					0 :
+					1;
 	}
 
 	/* Set the color for the given state and phase */
@@ -278,8 +276,8 @@ static void led_robo_update_power(void)
 		 * power LED is off for 600 msec, on for 3 seconds.
 		 */
 		period = LED_POWER_ON_TICKS + LED_POWER_OFF_TICKS;
-		level = ticks % period < LED_POWER_OFF_TICKS ?
-			LED_OFF_LVL : LED_ON_LVL;
+		level = ticks % period < LED_POWER_OFF_TICKS ? LED_OFF_LVL :
+							       LED_ON_LVL;
 		ticks++;
 	} else {
 		level = LED_OFF_LVL;
diff --git a/board/coral/sku.h b/board/coral/sku.h
index 4588932377..c12777a2f7 100644
--- a/board/coral/sku.h
+++ b/board/coral/sku.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,7 +8,7 @@
 #ifndef __CROS_EC_SKU_H
 #define __CROS_EC_SKU_H
 
-#define SKU_CONVERTIBLE(id) (1 << ((id) & 0x7))
+#define SKU_CONVERTIBLE(id) (1 << ((id)&0x7))
 
 /*
  * There are 256 possible SKUs for Coral. This table is used to map a given SKU
@@ -22,7 +22,7 @@ static const uint8_t form_factor[32] = {
 	SKU_CONVERTIBLE(4) | SKU_CONVERTIBLE(5),
 	/* SKU 8 - 15 */
 	SKU_CONVERTIBLE(8) | SKU_CONVERTIBLE(9) | SKU_CONVERTIBLE(10) |
-	SKU_CONVERTIBLE(11),
+		SKU_CONVERTIBLE(11),
 	/* SKU 16 - 23 */
 	0x00,
 	/* SKU 24 - 31 */
@@ -61,7 +61,7 @@ static const uint8_t form_factor[32] = {
 	0x00,
 	/* SKU 160 - 167 */
 	SKU_CONVERTIBLE(163) | SKU_CONVERTIBLE(164) | SKU_CONVERTIBLE(165) |
-	SKU_CONVERTIBLE(166),
+		SKU_CONVERTIBLE(166),
 	/* SKU 168 - 175 */
 	0x00,
 	/* SKU 176 - 183 */
@@ -86,6 +86,6 @@ static const uint8_t form_factor[32] = {
 	0x00,
 };
 
-#define SKU_IS_CONVERTIBLE(id) ((form_factor[(id) >> 3] >> ((id) & 0x7)) & 1)
+#define SKU_IS_CONVERTIBLE(id) ((form_factor[(id) >> 3] >> ((id)&0x7)) & 1)
 
 #endif /* __CROS_EC_SKU_H */
diff --git a/board/coral/usb_pd_policy.c b/board/coral/usb_pd_policy.c
index e071f6ae2a..a2e1f3c412 100644
--- a/board/coral/usb_pd_policy.c
+++ b/board/coral/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,12 +23,12 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT];
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5,
-							TYPEC_RP_1A5};
+static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5,
+							 TYPEC_RP_1A5 };
 
 int board_vbus_source_enabled(int port)
 {
@@ -39,7 +39,8 @@ static void board_vbus_update_source_current(int port)
 {
 	enum gpio_signal gpio = port ? GPIO_USB_C1_5V_EN : GPIO_USB_C0_5V_EN;
 	int flags = (vbus_rp[port] == TYPEC_RP_1A5 && vbus_en[port]) ?
-		(GPIO_INPUT | GPIO_PULL_UP) : (GPIO_OUTPUT | GPIO_PULL_UP);
+			    (GPIO_INPUT | GPIO_PULL_UP) :
+			    (GPIO_OUTPUT | GPIO_PULL_UP);
 
 	/*
 	 * Driving USB_Cx_5V_EN high, actually put a 16.5k resistance
diff --git a/board/corori/battery.c b/board/corori/battery.c
index 405a69751a..f4e126d42e 100644
--- a/board/corori/battery.c
+++ b/board/corori/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/corori/board.c b/board/corori/board.c
index 3453fccef4..4fe1e01fec 100644
--- a/board/corori/board.c
+++ b/board/corori/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -40,14 +40,13 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 #define INT_RECHECK_US 5000
 
-#define ADC_VOL_UP_MASK     BIT(0)
-#define ADC_VOL_DOWN_MASK   BIT(1)
-
+#define ADC_VOL_UP_MASK BIT(0)
+#define ADC_VOL_DOWN_MASK BIT(1)
 
 /******************************************************************************/
 /* USB-A Configuration */
@@ -73,8 +72,8 @@ static const struct ec_response_keybd_config corori_keybd = {
 	/* No function keys, no numeric keypad, no screenlock key */
 };
 
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	return &corori_keybd;
 }
@@ -115,7 +114,6 @@ static void usb_c0_interrupt(enum gpio_signal s)
 
 	/* Check the line again in 5ms */
 	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-
 }
 
 static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
@@ -154,22 +152,22 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* Thermistors */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Charger",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Charger",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_A \
-	{ \
+#define THERMAL_A                \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = 0, \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
@@ -186,8 +184,8 @@ __maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_B \
-	{ \
+#define THERMAL_B                \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = 0, \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(73), \
@@ -249,13 +247,11 @@ int board_is_sourcing_vbus(int port)
 
 	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
 	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
-
 }
 
 int board_set_active_charge_port(int port)
 {
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	int i;
 	int old_port;
 
@@ -315,8 +311,8 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
 
@@ -353,9 +349,8 @@ void board_init(void)
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
+__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+				       int *ki_div, int *kd, int *kd_div)
 {
 	*kp = 1;
 	*kp_div = 20;
@@ -399,12 +394,15 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
-		.driver = &pi3usb3x532_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
+				.driver = &pi3usb3x532_usb_mux_driver,
+			},
 	},
 };
 
@@ -446,46 +444,36 @@ static void board_extpower(void)
 DECLARE_HOOK(HOOK_AC_CHANGE, board_extpower, HOOK_PRIO_DEFAULT);
 
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_EEPROM_SCL,
-		.sda  = GPIO_EC_I2C_EEPROM_SDA
-	},
-
-	{
-		.name = "battery",
-		.port = I2C_PORT_BATTERY,
-		.kbps = 100,
-		.scl  = GPIO_EC_I2C_BATTERY_SCL,
-		.sda  = GPIO_EC_I2C_BATTERY_SDA
-	},
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_EEPROM_SCL,
+	  .sda = GPIO_EC_I2C_EEPROM_SDA },
+
+	{ .name = "battery",
+	  .port = I2C_PORT_BATTERY,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_BATTERY_SCL,
+	  .sda = GPIO_EC_I2C_BATTERY_SDA },
 
 #ifdef HAS_TASK_MOTIONSENSE
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_SENSOR_SCL,
-		.sda  = GPIO_EC_I2C_SENSOR_SDA
-	},
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_SENSOR_SCL,
+	  .sda = GPIO_EC_I2C_SENSOR_SDA },
 #endif
 
-	{
-		.name = "usbc0",
-		.port = I2C_PORT_USB_C0,
-		.kbps = 1000,
-		.scl  = GPIO_EC_I2C_USB_C0_SCL,
-		.sda  = GPIO_EC_I2C_USB_C0_SDA
-	},
+	{ .name = "usbc0",
+	  .port = I2C_PORT_USB_C0,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C0_SCL,
+	  .sda = GPIO_EC_I2C_USB_C0_SDA },
 #if CONFIG_USB_PD_PORT_MAX_COUNT > 1
-	{
-		.name = "sub_usbc1",
-		.port = I2C_PORT_SUB_USB_C1,
-		.kbps = 1000,
-		.scl  = GPIO_EC_I2C_SUB_USB_C1_SCL,
-		.sda  = GPIO_EC_I2C_SUB_USB_C1_SDA
-	},
+	{ .name = "sub_usbc1",
+	  .port = I2C_PORT_SUB_USB_C1,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_SUB_USB_C1_SCL,
+	  .sda = GPIO_EC_I2C_SUB_USB_C1_SDA },
 #endif
 };
diff --git a/board/corori/board.h b/board/corori/board.h
index 42d242abee..75e0e4eec6 100644
--- a/board/corori/board.h
+++ b/board/corori/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,6 +22,7 @@
 
 /* Charger */
 #define CONFIG_CHARGER_RAA489000
+#define PD_MAX_VOLTAGE_MV 20000
 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 #define CONFIG_CHARGER_SENSE_RESISTOR 10
 #undef CONFIG_CMD_CHARGER_DUMP
@@ -34,9 +35,8 @@
 #define GPIO_BAT_LED_AMBER GPIO_LED_Y_ODL
 #define GPIO_PWR_LED_WHITE GPIO_LED_W_ODL
 
-
 /* PWM */
-#define NPCX7_PWM1_SEL    1  /* GPIO C2 is used as PWM1. */
+#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */
 
 /* Temp sensor */
 #define CONFIG_TEMP_SENSOR
@@ -65,16 +65,16 @@
 #define CONFIG_USB_PD_5V_EN_CUSTOM
 
 /* I2C configuration */
-#define I2C_PORT_EEPROM     NPCX_I2C_PORT7_0
-#define I2C_PORT_BATTERY    NPCX_I2C_PORT5_0
-#define I2C_PORT_SENSOR     NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0     NPCX_I2C_PORT1_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
 #define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_MUX    I2C_PORT_USB_C0
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0
 /* TODO(b:147440290): Need to handle multiple charger ICs */
-#define I2C_PORT_CHARGER    I2C_PORT_USB_C0
+#define I2C_PORT_CHARGER I2C_PORT_USB_C0
 
-#define I2C_PORT_ACCEL      I2C_PORT_SENSOR
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
 
 #define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */
 
@@ -89,17 +89,13 @@
 #include "registers.h"
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_1,     /* ADC0 */
-	ADC_TEMP_SENSOR_2,     /* ADC1 */
-	ADC_VSNS_PP3300_A,     /* ADC9 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
+	ADC_VSNS_PP3300_A, /* ADC9 */
 	ADC_CH_COUNT
 };
 
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_COUNT
-};
+enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT };
 
 enum battery_type {
 	BATTERY_C21N2018,
diff --git a/board/corori/build.mk b/board/corori/build.mk
index b012d8d502..eb422dae93 100644
--- a/board/corori/build.mk
+++ b/board/corori/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/corori/cbi_ssfc.c b/board/corori/cbi_ssfc.c
index c4b859f133..81f3ee0dad 100644
--- a/board/corori/cbi_ssfc.c
+++ b/board/corori/cbi_ssfc.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
 
 enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
 {
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
 }
 
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
 {
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
 }
diff --git a/board/corori/cbi_ssfc.h b/board/corori/cbi_ssfc.h
index 935049b6ae..bf8853a43a 100644
--- a/board/corori/cbi_ssfc.h
+++ b/board/corori/cbi_ssfc.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -56,5 +56,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
  */
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
 
-
 #endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/corori/ec.tasklist b/board/corori/ec.tasklist
index 0025c2985b..386e8625b3 100644
--- a/board/corori/ec.tasklist
+++ b/board/corori/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/corori/gpio.inc b/board/corori/gpio.inc
index 5f6f119648..038c70243f 100644
--- a/board/corori/gpio.inc
+++ b/board/corori/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/corori/led.c b/board/corori/led.c
index 96a43caa76..89799c8e74 100644
--- a/board/corori/led.c
+++ b/board/corori/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,20 +19,16 @@
 
 #define LED_ON_LVL 0
 #define LED_OFF_LVL 1
-#define LED_INDEFINITE	UINT8_MAX
-#define LED_ONE_SEC	(1000 / HOOK_TICK_INTERVAL_MS)
-#define LED_OFF         EC_LED_COLOR_COUNT
+#define LED_INDEFINITE UINT8_MAX
+#define LED_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS)
+#define LED_OFF EC_LED_COLOR_COUNT
 
 struct led_descriptor {
 	enum ec_led_colors color;
 	uint8_t time;
 };
 
-enum led_phase {
-	LED_PHASE_0,
-	LED_PHASE_1,
-	LED_NUM_PHASES
-};
+enum led_phase { LED_PHASE_0, LED_PHASE_1, LED_NUM_PHASES };
 
 enum led_states {
 	STATE_CHARGING,
@@ -47,28 +43,32 @@ enum led_states {
 };
 
 static const struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,	     3 * LED_ONE_SEC} },
-	[STATE_BATTERY_S0_ERROR]     = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_BATTERY_S3_BLINK]     = {{EC_LED_COLOR_WHITE,  1 * LED_ONE_SEC},
-					{LED_OFF,	    3 * LED_ONE_SEC} },
-	[STATE_BATTERY_S5_OFF]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_FACTORY_TEST]	     = {{EC_LED_COLOR_WHITE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING] = { { EC_LED_COLOR_AMBER, LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_BATTERY_S0_ERROR] = { { EC_LED_COLOR_AMBER,
+					       1 * LED_ONE_SEC },
+					     { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_BATTERY_S3_BLINK] = { { EC_LED_COLOR_WHITE,
+					       1 * LED_ONE_SEC },
+					     { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_BATTERY_S5_OFF] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-
 static int led_get_charge_percent(void)
 {
 	return DIV_ROUND_NEAREST(charge_get_display_charge(), 10);
@@ -131,7 +131,8 @@ static enum led_states led_get_state(void)
 	case PWR_STATE_DISCHARGE /* and PWR_STATE_DISCHARGE_FULL */:
 		if (chipset_in_state(CHIPSET_STATE_ON))
 			new_state = (led_get_charge_percent() < 10) ?
-				STATE_DISCHARGE_S0_BAT_LOW : STATE_DISCHARGE_S0;
+					    STATE_DISCHARGE_S0_BAT_LOW :
+					    STATE_DISCHARGE_S0;
 		else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
 			new_state = STATE_BATTERY_S3_BLINK;
 		else
@@ -149,10 +150,10 @@ static enum led_states led_get_state(void)
 		new_state = STATE_CHARGING_FULL_CHARGE;
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (charge_get_flags() & CHARGE_FLAG_FORCE_IDLE)
-			new_state = STATE_FACTORY_TEST;
-		else
-			new_state = STATE_DISCHARGE_S0;
+		new_state = STATE_DISCHARGE_S0;
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		new_state = STATE_FACTORY_TEST;
 		break;
 	default:
 		/* Other states don't alter LED behavior */
@@ -182,8 +183,7 @@ static void led_update_battery(void)
 		ticks = 0;
 
 		period = led_bat_state_table[led_state][LED_PHASE_0].time +
-			led_bat_state_table[led_state][LED_PHASE_1].time;
-
+			 led_bat_state_table[led_state][LED_PHASE_1].time;
 	}
 
 	/* If this state is undefined, turn the LED off */
@@ -196,8 +196,8 @@ static void led_update_battery(void)
 	 * Determine which phase of the state table to use. The phase is
 	 * determined if it falls within first phase time duration.
 	 */
-	phase = ticks < led_bat_state_table[led_state][LED_PHASE_0].time ?
-									0 : 1;
+	phase = ticks < led_bat_state_table[led_state][LED_PHASE_0].time ? 0 :
+									   1;
 	ticks = (ticks + 1) % period;
 
 	/* Set the color for the given state and phase */
diff --git a/board/corori/usb_pd_policy.c b/board/corori/usb_pd_policy.c
index fd9018a3f0..3410726e87 100644
--- a/board/corori/usb_pd_policy.c
+++ b/board/corori/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,8 +10,8 @@
 #include "driver/tcpm/tcpci.h"
 #include "usb_pd.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
diff --git a/board/corori2/battery.c b/board/corori2/battery.c
index 1263e4cef0..a59663c751 100644
--- a/board/corori2/battery.c
+++ b/board/corori2/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/corori2/board.c b/board/corori2/board.c
index 0ccd3c3ebc..efebc3af2e 100644
--- a/board/corori2/board.c
+++ b/board/corori2/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -44,8 +44,8 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 #define INT_RECHECK_US 5000
 
@@ -85,7 +85,6 @@ static void usb_c0_interrupt(enum gpio_signal s)
 
 	/* Check the line again in 5ms */
 	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-
 }
 
 /* C1 interrupt line shared by BC 1.2, TCPC, and charger */
@@ -120,7 +119,6 @@ static void sub_usb_c1_interrupt(enum gpio_signal s)
 
 	/* Check the line again in 5ms */
 	hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
-
 }
 
 static void sub_hdmi_hpd_interrupt(enum gpio_signal s)
@@ -167,22 +165,22 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* Thermistors */
 const struct temp_sensor_t temp_sensors[] = {
-	[ADC_TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[ADC_TEMP_SENSOR_2] = {.name = "Charger",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
+	[ADC_TEMP_SENSOR_1] = { .name = "Memory",
+				.type = TEMP_SENSOR_TYPE_BOARD,
+				.read = get_temp_3v3_51k1_47k_4050b,
+				.idx = ADC_TEMP_SENSOR_1 },
+	[ADC_TEMP_SENSOR_2] = { .name = "Charger",
+				.type = TEMP_SENSOR_TYPE_BOARD,
+				.read = get_temp_3v3_51k1_47k_4050b,
+				.idx = ADC_TEMP_SENSOR_2 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_MEMORY \
-	{ \
+#define THERMAL_MEMORY           \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = 0, \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(85), \
@@ -200,8 +198,8 @@ __maybe_unused static const struct ec_thermal_config thermal_memory =
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CHARGER \
-	{ \
+#define THERMAL_CHARGER          \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = 0, \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(80), \
@@ -234,16 +232,17 @@ void board_init(void)
 
 	if (get_cbi_fw_config_db() == DB_1A_HDMI) {
 		/* Disable i2c on HDMI pins */
-		gpio_config_pin(MODULE_I2C,
-				GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL, 0);
-		gpio_config_pin(MODULE_I2C,
-				GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL, 0);
+		gpio_config_pin(MODULE_I2C, GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL,
+				0);
+		gpio_config_pin(MODULE_I2C, GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL,
+				0);
 
 		/* Set HDMI and sub-rail enables to output */
 		gpio_set_flags(GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL,
 			       chipset_in_state(CHIPSET_STATE_ON) ?
-						GPIO_ODR_LOW : GPIO_ODR_HIGH);
-		gpio_set_flags(GPIO_SUB_C1_INT_EN_RAILS_ODL,   GPIO_ODR_HIGH);
+				       GPIO_ODR_LOW :
+				       GPIO_ODR_HIGH);
+		gpio_set_flags(GPIO_SUB_C1_INT_EN_RAILS_ODL, GPIO_ODR_HIGH);
 
 		/* Select HDMI option */
 		gpio_set_level(GPIO_HDMI_SEL_L, 0);
@@ -252,8 +251,7 @@ void board_init(void)
 		gpio_enable_interrupt(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL);
 	} else {
 		/* Set SDA as an input */
-		gpio_set_flags(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL,
-			       GPIO_INPUT);
+		gpio_set_flags(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL, GPIO_INPUT);
 
 		/* Enable C1 interrupt and check if it needs processing */
 		gpio_enable_interrupt(GPIO_SUB_C1_INT_EN_RAILS_ODL);
@@ -320,7 +318,7 @@ static void reconfigure_5v_gpio(void)
 		gpio_set_flags(GPIO_VOLUP_BTN_ODL, GPIO_OUT_LOW);
 	}
 }
-DECLARE_HOOK(HOOK_INIT, reconfigure_5v_gpio, HOOK_PRIO_INIT_I2C+1);
+DECLARE_HOOK(HOOK_INIT, reconfigure_5v_gpio, HOOK_PRIO_INIT_I2C + 1);
 #endif /* BOARD_WADDLEDOO */
 
 static void set_5v_gpio(int level)
@@ -361,10 +359,9 @@ __override void board_power_5v_enable(int enable)
 		gpio_set_level(GPIO_SUB_C1_INT_EN_RAILS_ODL, !enable);
 	} else {
 		if (isl923x_set_comparator_inversion(1, !!enable))
-			CPRINTS("Failed to %sable sub rails!", enable ?
-								"en" : "dis");
+			CPRINTS("Failed to %sable sub rails!",
+				enable ? "en" : "dis");
 	}
-
 }
 
 __override uint8_t board_get_usb_pd_port_count(void)
@@ -389,13 +386,11 @@ int board_is_sourcing_vbus(int port)
 
 	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
 	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
-
 }
 
 int board_set_active_charge_port(int port)
 {
-	int is_real_port = (port >= 0 &&
-			    port < board_get_usb_pd_port_count());
+	int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count());
 	int i;
 	int old_port;
 
@@ -459,8 +454,8 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
 
@@ -485,17 +480,13 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrices to rotate accelerometers into the standard reference. */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					     { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
 
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					      { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
 
 static struct accelgyro_saved_data_t g_bma253_data;
 static struct bmi_drv_data_t g_bmi160_data;
@@ -571,9 +562,8 @@ struct motion_sensor_t motion_sensors[] = {
 
 const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
+__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+				       int *ki_div, int *kd, int *kd_div)
 {
 	*kp = 1;
 	*kp_div = 20;
@@ -660,25 +650,34 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usbc1_retimer = {
-	.usb_port = 1,
-	.i2c_port = I2C_PORT_SUB_USB_C1,
-	.i2c_addr_flags = NB7V904M_I2C_ADDR0,
-	.driver = &nb7v904m_usb_redriver_drv,
+const struct usb_mux_chain usbc1_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = 1,
+			.i2c_port = I2C_PORT_SUB_USB_C1,
+			.i2c_addr_flags = NB7V904M_I2C_ADDR0,
+			.driver = &nb7v904m_usb_redriver_drv,
+		},
 };
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
-		.driver = &pi3usb3x532_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
+				.driver = &pi3usb3x532_usb_mux_driver,
+			},
 	},
 	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
-		.driver = &pi3usb3x532_usb_mux_driver,
-		.next_mux = &usbc1_retimer,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_SUB_USB_C1,
+				.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
+				.driver = &pi3usb3x532_usb_mux_driver,
+			},
+		.next = &usbc1_retimer,
 	}
 };
 
@@ -704,7 +703,7 @@ uint16_t tcpc_get_alert_status(void)
 	}
 
 	if (board_get_usb_pd_port_count() > 1 &&
-				!gpio_get_level(GPIO_SUB_C1_INT_EN_RAILS_ODL)) {
+	    !gpio_get_level(GPIO_SUB_C1_INT_EN_RAILS_ODL)) {
 		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
 			/* TCPCI spec Rev 1.0 says to ignore bits 14:12. */
 			if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0))
diff --git a/board/corori2/board.h b/board/corori2/board.h
index 1e24d5eb71..0fc4423020 100644
--- a/board/corori2/board.h
+++ b/board/corori2/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,7 +19,7 @@
 
 /* Save some flash space */
 #define CONFIG_CHIP_INIT_ROM_REGION
-#undef  CONFIG_CONSOLE_CMDHELP
+#undef CONFIG_CONSOLE_CMDHELP
 #define CONFIG_DEBUG_ASSERT_BRIEF
 #define CONFIG_USB_PD_DEBUG_LEVEL 2
 
@@ -35,11 +35,14 @@
 
 /* Charger */
 #define CONFIG_CHARGER_RAA489000
+#define PD_MAX_VOLTAGE_MV 20000
 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 #define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */
+#define CONFIG_OCPC_DEF_RBATT_MOHMS               \
+	22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \
+	    */
 #define CONFIG_OCPC
-#undef  CONFIG_CHARGER_SINGLE_CHIP
+#undef CONFIG_CHARGER_SINGLE_CHIP
 #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
 #define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
 
@@ -68,7 +71,7 @@
 
 /* PWM */
 #define CONFIG_PWM
-#define NPCX7_PWM1_SEL    1  /* GPIO C2 is used as PWM1. */
+#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */
 
 /* Temp sensor */
 #define CONFIG_TEMP_SENSOR
@@ -98,23 +101,22 @@
 #undef PD_POWER_SUPPLY_TURN_OFF_DELAY
 #undef CONFIG_USBC_VCONN_SWAP_DELAY_US
 /* 20% margin added for these timings */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	13080	/* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	16080	/* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 13080 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 16080 /* us */
 #undef CONFIG_USBC_VCONN_SWAP_DELAY_US
-#define CONFIG_USBC_VCONN_SWAP_DELAY_US		787	/* us */
-
+#define CONFIG_USBC_VCONN_SWAP_DELAY_US 787 /* us */
 
 /* I2C configuration */
-#define I2C_PORT_EEPROM     NPCX_I2C_PORT7_0
-#define I2C_PORT_BATTERY    NPCX_I2C_PORT5_0
-#define I2C_PORT_SENSOR     NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0     NPCX_I2C_PORT1_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
 #define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_MUX    I2C_PORT_USB_C0
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0
 /* TODO(b:147440290): Need to handle multiple charger ICs */
-#define I2C_PORT_CHARGER    I2C_PORT_USB_C0
+#define I2C_PORT_CHARGER I2C_PORT_USB_C0
 
-#define I2C_PORT_ACCEL      I2C_PORT_SENSOR
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
 
 #define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */
 
@@ -128,13 +130,13 @@
 #define GPIO_EC_I2C_SUB_USB_C1_SDA GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL
 
 /* Sensors */
-#define CONFIG_ACCEL_BMA255		/* Lid accel */
-#define CONFIG_ACCELGYRO_BMI160		/* Base accel */
+#define CONFIG_ACCEL_BMA255 /* Lid accel */
+#define CONFIG_ACCELGYRO_BMI160 /* Base accel */
 
 /* Lid operates in forced mode, base in FIFO */
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
 #define CONFIG_ACCEL_FIFO
-#define CONFIG_ACCEL_FIFO_SIZE 256	/* Must be a power of 2 */
+#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */
 #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
 
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
@@ -161,25 +163,16 @@ enum chg_id {
 };
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_1,     /* ADC0 */
-	ADC_TEMP_SENSOR_2,     /* ADC1 */
-	ADC_SUB_ANALOG,	       /* ADC2 */
-	ADC_VSNS_PP3300_A,     /* ADC9 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
+	ADC_SUB_ANALOG, /* ADC2 */
+	ADC_VSNS_PP3300_A, /* ADC9 */
 	ADC_CH_COUNT
 };
 
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_COUNT
-};
+enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT };
 
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
 enum pwm_channel {
 	PWM_CH_KBLIGHT,
diff --git a/board/corori2/build.mk b/board/corori2/build.mk
index af526189dd..1512a49379 100644
--- a/board/corori2/build.mk
+++ b/board/corori2/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/corori2/cbi_ssfc.c b/board/corori2/cbi_ssfc.c
index c4b859f133..81f3ee0dad 100644
--- a/board/corori2/cbi_ssfc.c
+++ b/board/corori2/cbi_ssfc.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
 
 enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
 {
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
 }
 
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
 {
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
 }
diff --git a/board/corori2/cbi_ssfc.h b/board/corori2/cbi_ssfc.h
index 935049b6ae..bf8853a43a 100644
--- a/board/corori2/cbi_ssfc.h
+++ b/board/corori2/cbi_ssfc.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -56,5 +56,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
  */
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
 
-
 #endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/corori2/ec.tasklist b/board/corori2/ec.tasklist
index d4fb416bce..29666dd959 100644
--- a/board/corori2/ec.tasklist
+++ b/board/corori2/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/corori2/gpio.inc b/board/corori2/gpio.inc
index 78d41aab16..63b16a1bc3 100644
--- a/board/corori2/gpio.inc
+++ b/board/corori2/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/corori2/led.c b/board/corori2/led.c
index 3c27bf0f8e..71a8159a07 100644
--- a/board/corori2/led.c
+++ b/board/corori2/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,13 +20,10 @@ const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
  * both LEDs being off.
  */
 struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = {
-				/* Amber, White */
-	[EC_LED_COLOR_RED]    = {   0,   0 },
-	[EC_LED_COLOR_GREEN]  = {   0,   0 },
-	[EC_LED_COLOR_BLUE]   = {   0,   0 },
-	[EC_LED_COLOR_YELLOW] = {   0,   0 },
-	[EC_LED_COLOR_WHITE]  = {   0, 100 },
-	[EC_LED_COLOR_AMBER]  = {  100,  0 },
+	/* Amber, White */
+	[EC_LED_COLOR_RED] = { 0, 0 },	   [EC_LED_COLOR_GREEN] = { 0, 0 },
+	[EC_LED_COLOR_BLUE] = { 0, 0 },	   [EC_LED_COLOR_YELLOW] = { 0, 0 },
+	[EC_LED_COLOR_WHITE] = { 0, 100 }, [EC_LED_COLOR_AMBER] = { 100, 0 },
 };
 
 /* One logical LED with amber and white channels. */
diff --git a/board/corori2/usb_pd_policy.c b/board/corori2/usb_pd_policy.c
index 15faf41ffc..83c09bb99e 100644
--- a/board/corori2/usb_pd_policy.c
+++ b/board/corori2/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,8 @@
 #include "driver/tcpm/tcpci.h"
 #include "usb_pd.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
diff --git a/board/cret/battery.c b/board/cret/battery.c
index ee5def4183..27bfed5355 100644
--- a/board/cret/battery.c
+++ b/board/cret/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -638,8 +638,8 @@ const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_BYD_1VX1H;
 int charger_profile_override(struct charge_state_data *curr)
 {
 	if (chipset_in_state(CHIPSET_STATE_ON)) {
-		curr->requested_current = MIN(curr->requested_current,
-				CHARGING_CURRENT_1100MA);
+		curr->requested_current =
+			MIN(curr->requested_current, CHARGING_CURRENT_1100MA);
 	}
 
 	return 0;
diff --git a/board/cret/board.c b/board/cret/board.c
index 57bddae55e..c9c34d6d32 100644
--- a/board/cret/board.c
+++ b/board/cret/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -44,8 +44,8 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 #define INT_RECHECK_US 5000
 
@@ -86,7 +86,6 @@ static void usb_c0_interrupt(enum gpio_signal s)
 
 	/* Check the line again in 5ms */
 	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-
 }
 
 static void sub_hdmi_hpd_interrupt(enum gpio_signal s)
@@ -202,7 +201,7 @@ static void reconfigure_5v_gpio(void)
 		gpio_set_flags(GPIO_VOLUP_BTN_ODL, GPIO_OUT_LOW);
 	}
 }
-DECLARE_HOOK(HOOK_INIT, reconfigure_5v_gpio, HOOK_PRIO_INIT_I2C+1);
+DECLARE_HOOK(HOOK_INIT, reconfigure_5v_gpio, HOOK_PRIO_INIT_I2C + 1);
 #endif /* BOARD_WADDLEDOO */
 
 static void set_5v_gpio(int level)
@@ -220,7 +219,6 @@ __override void board_power_5v_enable(int enable)
 	 * DB.
 	 */
 	set_5v_gpio(!!enable);
-
 }
 
 __override uint8_t board_get_usb_pd_port_count(void)
@@ -239,13 +237,11 @@ int board_is_sourcing_vbus(int port)
 
 	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
 	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
-
 }
 
 int board_set_active_charge_port(int port)
 {
-	int is_real_port = (port >= 0 &&
-			    port < board_get_usb_pd_port_count());
+	int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count());
 	int i;
 	int old_port;
 
@@ -308,8 +304,8 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
 
@@ -334,17 +330,13 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrices to rotate accelerometers into the standard reference. */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					     { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
 
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					      { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
 
 static struct stprivate_data g_lis2dh_data;
 static struct lsm6dso_data lsm6dso_data;
@@ -424,20 +416,19 @@ unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
 /* Thermistors */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Charger",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Charger",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
+__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+				       int *ki_div, int *kd, int *kd_div)
 {
 	*kp = 1;
 	*kp_div = 20;
@@ -489,12 +480,15 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.drv = &raa489000_tcpm_drv,
 	},
 };
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
-		.driver = &pi3usb3x532_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
+				.driver = &pi3usb3x532_usb_mux_driver,
+			},
 	},
 };
 
@@ -568,8 +562,8 @@ static const struct ec_response_keybd_config cret_keybd = {
 	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
 };
 
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	return &cret_keybd;
 }
diff --git a/board/cret/board.h b/board/cret/board.h
index 69394fe218..2080185c7c 100644
--- a/board/cret/board.h
+++ b/board/cret/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -29,6 +29,7 @@
 
 /* Charger */
 #define CONFIG_CHARGER_RAA489000
+#define PD_MAX_VOLTAGE_MV 20000
 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 #define CONFIG_CHARGER_SENSE_RESISTOR 10
 #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
@@ -47,7 +48,7 @@
 
 /* PWM */
 #define CONFIG_PWM
-#define NPCX7_PWM1_SEL    1  /* GPIO C2 is used as PWM1. */
+#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */
 
 /* USB */
 #define CONFIG_BC12_DETECT_PI3USB9201
@@ -74,23 +75,22 @@
 #undef PD_POWER_SUPPLY_TURN_OFF_DELAY
 #undef CONFIG_USBC_VCONN_SWAP_DELAY_US
 /* 20% margin added for these timings */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	13080	/* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	16080	/* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 13080 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 16080 /* us */
 #undef CONFIG_USBC_VCONN_SWAP_DELAY_US
-#define CONFIG_USBC_VCONN_SWAP_DELAY_US		787	/* us */
-
+#define CONFIG_USBC_VCONN_SWAP_DELAY_US 787 /* us */
 
 /* I2C configuration */
-#define I2C_PORT_EEPROM     NPCX_I2C_PORT7_0
-#define I2C_PORT_BATTERY    NPCX_I2C_PORT5_0
-#define I2C_PORT_SENSOR     NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0     NPCX_I2C_PORT1_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
 #define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_MUX    I2C_PORT_USB_C0
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0
 /* TODO(b:147440290): Need to handle multiple charger ICs */
-#define I2C_PORT_CHARGER    I2C_PORT_USB_C0
+#define I2C_PORT_CHARGER I2C_PORT_USB_C0
 
-#define I2C_PORT_ACCEL      I2C_PORT_SENSOR
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
 
 #define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */
 
@@ -98,18 +98,17 @@
 #define CONFIG_CMD_ACCELS
 #define CONFIG_CMD_ACCEL_INFO
 
-#define CONFIG_ACCEL_LIS2DE		/* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSO	/* Base accel */
+#define CONFIG_ACCEL_LIS2DE /* Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSO /* Base accel */
 #define CONFIG_ACCEL_LSM6DSO_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 
 /* Lid operates in forced mode, base in FIFO */
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
 #define CONFIG_ACCEL_FIFO
-#define CONFIG_ACCEL_FIFO_SIZE 256	/* Must be a power of 2 */
+#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */
 #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
 
-
 #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
 
 #define CONFIG_LID_ANGLE
@@ -132,24 +131,15 @@
 #include "registers.h"
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_1,     /* ADC0 */
-	ADC_TEMP_SENSOR_2,     /* ADC1 */
-	ADC_VSNS_PP3300_A,     /* ADC9 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
+	ADC_VSNS_PP3300_A, /* ADC9 */
 	ADC_CH_COUNT
 };
 
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_COUNT
-};
+enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT };
 
 enum pwm_channel {
 	PWM_CH_KBLIGHT,
diff --git a/board/cret/build.mk b/board/cret/build.mk
index af526189dd..1512a49379 100644
--- a/board/cret/build.mk
+++ b/board/cret/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/cret/cbi_ssfc.c b/board/cret/cbi_ssfc.c
index c4b859f133..81f3ee0dad 100644
--- a/board/cret/cbi_ssfc.c
+++ b/board/cret/cbi_ssfc.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
 
 enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
 {
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
 }
 
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
 {
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
 }
diff --git a/board/cret/cbi_ssfc.h b/board/cret/cbi_ssfc.h
index 058290de8d..bef606bc72 100644
--- a/board/cret/cbi_ssfc.h
+++ b/board/cret/cbi_ssfc.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -61,5 +61,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
  */
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
 
-
 #endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/cret/ec.tasklist b/board/cret/ec.tasklist
index ee5333eb17..a98ca6fd86 100644
--- a/board/cret/ec.tasklist
+++ b/board/cret/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/cret/gpio.inc b/board/cret/gpio.inc
index 352f689620..5f39fedc80 100644
--- a/board/cret/gpio.inc
+++ b/board/cret/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/cret/led.c b/board/cret/led.c
index edfb4ac761..8a7a343fb3 100644
--- a/board/cret/led.c
+++ b/board/cret/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,8 +8,8 @@
 #include "led_common.h"
 #include "led_onoff_states.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
 __override const int led_charge_lvl_1 = 10;
 
@@ -17,23 +17,32 @@ __override const int led_charge_lvl_2 = 100;
 
 /* Cret: Note there is only LED for charge / power */
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_S5]     = {{LED_OFF,	     LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     1 * LED_ONE_SEC },
+					   { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_WHITE,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 BUILD_ASSERT(ARRAY_SIZE(led_bat_state_table) == LED_NUM_STATES);
 
 const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
diff --git a/board/cret/usb_pd_policy.c b/board/cret/usb_pd_policy.c
index 15faf41ffc..83c09bb99e 100644
--- a/board/cret/usb_pd_policy.c
+++ b/board/cret/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,8 @@
 #include "driver/tcpm/tcpci.h"
 #include "usb_pd.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
diff --git a/board/crota/battery.c b/board/crota/battery.c
index 5bdf307b07..4738b5910f 100644
--- a/board/crota/battery.c
+++ b/board/crota/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -63,7 +63,7 @@ const struct board_batt_params board_battery_info[] = {
 		},
 	},
 	/* BYD 13076993-009 Battery Information */
-	[BATTERY_BYD] = {
+	[BATTERY_BYD_GSL4] = {
 		.fuel_gauge = {
 			.manuf_name = "BYD",
 			.device_name = "DELL WV3K8",
@@ -210,7 +210,7 @@ const struct board_batt_params board_battery_info[] = {
 	/* SWD 1002000008482 Battery Information */
 	[BATTERY_SWD_ATL3] = {
 		.fuel_gauge = {
-			.manuf_name = "SWD-ATL3.661",
+			.manuf_name = "SWD-ATL3.660",
 			.device_name = "DELL VKYJX",
 			.ship_mode = {
 				.reg_addr = 0x00,
@@ -323,6 +323,35 @@ const struct board_batt_params board_battery_info[] = {
 			.discharging_max_c	= 70,
 		},
 	},
+	/* BYD 13148981-00 Battery Information */
+	[BATTERY_BYD_CSL4] = {
+		.fuel_gauge = {
+			.manuf_name = "BYD",
+			.device_name = "DELL JGCCT",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 0,
+				.reg_addr = 0x00,
+				.reg_mask = 0x2000,
+				.disconnect_val = 0x2000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 17400,  /* mV */
+			.voltage_normal		= 15000,  /* mV */
+			.voltage_min		= 12000,  /* mV */
+			.precharge_current	= 256,	  /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 60,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= 0,
+			.discharging_max_c	= 70,
+		},
+	},
 	/* Sunwoda 1002000009262 Battery Information */
 	[BATTERY_SWD_ATL4] = {
 		.fuel_gauge = {
@@ -392,6 +421,11 @@ enum battery_present battery_hw_present(void)
 
 	batt_pres = GPIO_EC_BATT_PRES_ODL;
 
-	/* The GPIO is low when the battery is physically present */
-	return gpio_get_level(batt_pres) ? BP_NO : BP_YES;
+	/*
+	 * The GPIO is low when the battery is physically present.
+	 * But if battery cell voltage < 2.5V, it will not able to
+	 * pull down EC_BATT_PRES_ODL. So we need to set pre-charge
+	 * current even EC_BATT_PRES_ODL is high.
+	 */
+	return gpio_get_level(batt_pres) ? BP_NOT_SURE : BP_YES;
 }
diff --git a/board/crota/board.c b/board/crota/board.c
index 855eeabb81..04f64bd2a5 100644
--- a/board/crota/board.c
+++ b/board/crota/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,13 +10,12 @@
 #include "common.h"
 #include "compile_time_macros.h"
 #include "console.h"
-#include "extpower.h"
 #include "gpio.h"
 #include "gpio_signal.h"
 #include "hooks.h"
 #include "driver/accel_lis2dw12.h"
+#include "driver/accelgyro_bmi260.h"
 #include "driver/accelgyro_lsm6dso.h"
-#include "driver/als_tcs3400.h"
 #include "fw_config.h"
 #include "hooks.h"
 #include "lid_switch.h"
@@ -31,8 +30,8 @@
 #include "gpio_list.h" /* Must come after other header files. */
 
 /* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 __override void board_cbi_init(void)
 {
@@ -56,23 +55,3 @@ static void board_chipset_suspend(void)
 	gpio_set_level(GPIO_EC_KB_BL_EN_L, 1);
 }
 DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
-#ifdef CONFIG_USB_PORT_POWER_DUMB_CUSTOM_HOOK
-static void usb_port_startup(void)
-{
-	gpio_set_level(GPIO_EN_PP5000_USBA_R, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, usb_port_startup, HOOK_PRIO_DEFAULT);
-
-static void usba_power(void)
-{
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
-		if (extpower_is_present())
-			gpio_set_level(GPIO_EN_PP5000_USBA_R, 1);
-		else
-			gpio_set_level(GPIO_EN_PP5000_USBA_R, 0);
-	}
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, usba_power, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_AC_CHANGE, usba_power, HOOK_PRIO_DEFAULT);
-#endif  /* CONFIG_USB_PORT_POWER_DUMB_CUSTOM_HOOK */
diff --git a/board/crota/board.h b/board/crota/board.h
index 46f3eb7755..0271a369bc 100644
--- a/board/crota/board.h
+++ b/board/crota/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,7 +22,11 @@
 #define CONFIG_MP2964
 
 /* Sensors */
-#define CONFIG_ACCELGYRO_LSM6DSO	/* Base accel */
+#define CONFIG_ACCELGYRO_BMI260 /* Base accel/gyro */
+#define CONFIG_ACCELGYRO_BMI260_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
+#define CONFIG_ACCELGYRO_LSM6DSO /* Base accel/gyro */
 #define CONFIG_ACCEL_LSM6DSO_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 
@@ -36,14 +40,14 @@
 /* Lid accel */
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE	BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID	LID_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
 #define CONFIG_ACCEL_LIS2DWL
 #define CONFIG_ACCEL_LIS2DW12_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
 
 #define CONFIG_BODY_DETECTION
-#define CONFIG_BODY_DETECTION_SENSOR           BASE_ACCEL
+#define CONFIG_BODY_DETECTION_SENSOR BASE_ACCEL
 #define CONFIG_BODY_DETECTION_VAR_NOISE_FACTOR 150 /* % */
 #define CONFIG_GESTURE_DETECTION
 #define CONFIG_GESTURE_DETECTION_MASK BIT(CONFIG_BODY_DETECTION_SENSOR)
@@ -54,16 +58,15 @@
 #define CONFIG_CMD_ACCEL_INFO
 
 /* USB Type A Features */
-#define USB_PORT_COUNT			1
+#define USB_PORT_COUNT 1
 #define CONFIG_USB_PORT_POWER_DUMB
-#define CONFIG_USB_PORT_POWER_DUMB_CUSTOM_HOOK
 
 /* USB Type C and USB PD defines */
 #define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
 
 #define CONFIG_IO_EXPANDER
 #define CONFIG_IO_EXPANDER_NCT38XX
-#define CONFIG_IO_EXPANDER_PORT_COUNT		2
+#define CONFIG_IO_EXPANDER_PORT_COUNT 2
 
 #define CONFIG_USBC_RETIMER_INTEL_BB
 
@@ -78,17 +81,17 @@
 #define CONFIG_USB_PD_FRS_PPC
 
 /* TODO: b/177608416 - measure and check these values on brya */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
 
 /*
  * Passive USB-C cables only support up to 60W.
  */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /*
  * Macros for GPIO signals used in common code that don't match the
@@ -96,35 +99,35 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT		GPIO_EC_EN_EDP_BL
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_GSC_PACKET_MODE
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SYS_SLP_S0IX_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_TEMP_SENSOR_POWER		GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
 
 /*
  * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
  * signal.
  */
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_SEQ_EC_ALL_SYS_PG
-#define GPIO_PG_EC_DSW_PWROK		GPIO_SEQ_EC_DSW_PWROK
-#define GPIO_PG_EC_RSMRST_ODL		GPIO_SEQ_EC_RSMRST_ODL
-#define GPIO_POWER_BUTTON_L		GPIO_GSC_EC_PWR_BTN_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_ODL
-
-#define GPIO_ID_1_EC_KB_BL_EN		GPIO_EC_BATT_PRES_ODL
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
+
+#define GPIO_ID_1_EC_KB_BL_EN GPIO_EC_BATT_PRES_ODL
 
 /* System has back-lit keyboard */
 #define CONFIG_PWM_KBLIGHT
@@ -134,47 +137,48 @@
 
 /* I2C Bus Configuration */
 
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+
+#define I2C_PORT_USB_C0_C1_TCPC NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1
 
-#define I2C_PORT_USB_C0_C1_TCPC	NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1_TCPC	NPCX_I2C_PORT4_1
+#define I2C_PORT_USB_C0_C1_PPC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1
 
-#define I2C_PORT_USB_C0_C1_PPC	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_PPC	NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C0_C1_BC12 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1
 
-#define I2C_PORT_USB_C0_C1_BC12	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_BC12	NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C0_C1_MUX NPCX_I2C_PORT3_0
+#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1
 
-#define I2C_PORT_USB_C0_C1_MUX	NPCX_I2C_PORT3_0
-#define I2C_PORT_USB_C1_MUX	NPCX_I2C_PORT6_1
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0
 
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT5_0
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT7_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-#define I2C_PORT_MP2964		NPCX_I2C_PORT7_0
+/* define this to avoid error on CONFIG_ACCELGYRO_BMI_COMM_I2C */
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
 
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 
-#define I2C_ADDR_MP2964_FLAGS	0x20
+#define I2C_ADDR_MP2964_FLAGS 0x20
 /*
  * see b/174768555#comment22
  */
-#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR	0x58
-#define USBC_PORT_C1_SOC_BB_RETIMER_I2C_ADDR    0x54
+#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x58
+#define USBC_PORT_C1_SOC_BB_RETIMER_I2C_ADDR 0x54
 /* Type-C connector facing Burnside Bridge retimer */
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x56
+#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x56
 
 /* Enabling Thunderbolt-compatible mode */
 #define CONFIG_USB_PD_TBT_COMPAT_MODE
 
 /* Enabling USB4 mode */
 #define CONFIG_USB_PD_USB4
+#define CONFIG_USB_PD_DATA_RESET_MSG
 
-/*
- * TODO: b/229934138, Disable BBR firmware update temporarily.
- */
 /* Retimer */
-#undef CONFIG_USBC_RETIMER_FW_UPDATE
+#define CONFIG_USBC_RETIMER_FW_UPDATE
 
 /* Thermal features */
 #define CONFIG_THERMISTOR
@@ -182,59 +186,55 @@
 #define CONFIG_TEMP_SENSOR_POWER
 #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
 
-#define CONFIG_FANS			FAN_CH_COUNT
-
 /* LED defines */
 #define CONFIG_LED_ONOFF_STATES
 #define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
 
+/* Fan features */
+#define CONFIG_CUSTOM_FAN_CONTROL
+#define CONFIG_FANS FAN_CH_COUNT
+#define CONFIG_FAN_DYNAMIC
+#define RPM_DEVIATION 1
+
 /* Charger defines */
 #define CONFIG_CHARGER_BQ25720
 #define CONFIG_CHARGER_BQ25720_VSYS_TH2_CUSTOM
-#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV	70
+#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV 70
 #define CONFIG_CHARGE_RAMP_SW
-#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10
 #define CONFIG_CHARGER_BQ25710_PSYS_SENSING
+#define CONFIG_CHARGER_BQ25710_PP_ACOK
 
 #ifndef __ASSEMBLER__
 
-#include "gpio_signal.h"	/* needed by registers.h */
+#include "gpio_signal.h" /* needed by registers.h */
 #include "registers.h"
 #include "usbc_config.h"
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_1_DDR_SOC,
-	ADC_TEMP_SENSOR_2_AMBIENT,
+	ADC_TEMP_SENSOR_1_SOC,
+	ADC_TEMP_SENSOR_2_DDR,
 	ADC_TEMP_SENSOR_3_CHARGER,
-	ADC_TEMP_SENSOR_4_WWAN,
+	ADC_TEMP_SENSOR_4_AMBIENT,
 	ADC_CH_COUNT
 };
 
 enum temp_sensor_id {
-	TEMP_SENSOR_1_DDR_SOC,
-	TEMP_SENSOR_2_AMBIENT,
+	TEMP_SENSOR_1_SOC,
+	TEMP_SENSOR_2_DDR,
 	TEMP_SENSOR_3_CHARGER,
-	TEMP_SENSOR_4_WWAN,
+	TEMP_SENSOR_4_AMBIENT,
 	TEMP_SENSOR_COUNT
 };
 
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL = 0, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
-enum ioex_port {
-	IOEX_C0_NCT38XX = 0,
-	IOEX_C1_NCT38XX,
-	IOEX_PORT_COUNT
-};
+enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_C1_NCT38XX, IOEX_PORT_COUNT };
 
 enum battery_type {
 	BATTERY_ATL,
-	BATTERY_BYD,
+	BATTERY_BYD_GSL4,
 	BATTERY_COM,
 	BATTERY_LGC,
 	BATTERY_SMP_ATL3,
@@ -243,29 +243,35 @@ enum battery_type {
 	BATTERY_SWD_COS3,
 	BATTERY_SMP_ATL4,
 	BATTERY_SMP_COS4,
+	BATTERY_BYD_CSL4,
 	BATTERY_SWD_ATL4,
 	BATTERY_SWD_COS4,
 	BATTERY_TYPE_COUNT
 };
 
 enum pwm_channel {
-	PWM_CH_LED2 = 0,		/* PWM0 (white charger) */
-	PWM_CH_LED1,			/* PWM2 (orange charger) */
-	PWM_CH_KBLIGHT,			/* PWM3 */
-	PWM_CH_FAN,			/* PWM5 */
+	PWM_CH_LED2 = 0, /* PWM0 (white charger) */
+	PWM_CH_LED1, /* PWM2 (orange charger) */
+	PWM_CH_KBLIGHT, /* PWM3 */
+	PWM_CH_FAN, /* PWM5 */
 	PWM_CH_COUNT
 };
 
-enum fan_channel {
-	FAN_CH_0 = 0,
-	FAN_CH_COUNT
-};
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT };
 
-enum mft_channel {
-	MFT_CH_0 = 0,
-	MFT_CH_COUNT
+enum fan_rpm_table {
+	RPM_TABLE_CPU0,
+	RPM_TABLE_CPU1,
+	RPM_TABLE_DDR,
+	RPM_TABLE_CHARGER,
+	RPM_TABLE_AMBIENT,
+	FAN_RPM_TABLE_COUNT
 };
 
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT };
+
+void motion_interrupt(enum gpio_signal signal);
+
 #endif /* !__ASSEMBLER__ */
 
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/crota/build.mk b/board/crota/build.mk
index cd6a38a852..8b85854cf0 100644
--- a/board/crota/build.mk
+++ b/board/crota/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/crota/charger.c b/board/crota/charger.c
index e6a5c446d7..c7dcf7b0c1 100644
--- a/board/crota/charger.c
+++ b/board/crota/charger.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,9 +15,8 @@
 #include "usb_pd.h"
 #include "util.h"
 
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* Charger Chip Configuration */
 const struct charger_config_t chg_chips[] = {
@@ -84,7 +83,6 @@ int board_set_active_charge_port(int port)
 __overridable void board_set_charge_limit(int port, int supplier, int charge_ma,
 					  int max_ma, int charge_mv)
 {
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
diff --git a/board/crota/ec.tasklist b/board/crota/ec.tasklist
index 296654d39d..17eeb4ae7c 100644
--- a/board/crota/ec.tasklist
+++ b/board/crota/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/crota/fans.c b/board/crota/fans.c
index 27f5bca929..17e19dc863 100644
--- a/board/crota/fans.c
+++ b/board/crota/fans.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,6 +12,16 @@
 #include "fan.h"
 #include "hooks.h"
 #include "pwm.h"
+#include "timer.h"
+#include "thermal.h"
+#include "util.h"
+
+#define SENSOR_SOC_FAN_OFF 30
+#define SENSOR_SOC_FAN_MID 47
+#define SENSOR_SOC_FAN_MAX 53
+#define SENSOR_DDR_FAN_TURN_OFF 37
+#define SENSOR_DDR_FAN_TURN_ON 38
+#define RECORD_TIME (2 * MINUTE)
 
 /* MFT channels. These are logically separate from pwm_channels. */
 const struct mft_t mft_channels[] = {
@@ -25,65 +35,152 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 static const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
 
-/*
- * TOOD(b/181271666): thermistor placement and calibration
- *
- * Prototype fan spins at about 4200 RPM at 100% PWM, this
- * is specific to board ID 2 and might also apears in later
- * boards as well.
- */
-static const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 2200,
-	.rpm_start = 2200,
-	.rpm_max = 4200,
+static const struct fan_rpm rpm_table[FAN_RPM_TABLE_COUNT] = {
+	[RPM_TABLE_CPU0] = {
+		.rpm_min = 2200,
+		.rpm_start = 2200,
+		.rpm_max = 3700,
+	},
+
+	[RPM_TABLE_CPU1] = {
+		.rpm_min = 3700,
+		.rpm_start = 3700,
+		.rpm_max = 4000,
+	},
+
+	[RPM_TABLE_DDR] = {
+		.rpm_min = 4000,
+		.rpm_start = 4000,
+		.rpm_max = 4200,
+	},
+
+	[RPM_TABLE_CHARGER] = {
+		.rpm_min = 4000,
+		.rpm_start = 4000,
+		.rpm_max = 4200,
+	},
+
+	[RPM_TABLE_AMBIENT] = {
+		.rpm_min = 4000,
+		.rpm_start = 4000,
+		.rpm_max = 4200,
+	},
 };
 
-const struct fan_t fans[FAN_CH_COUNT] = {
+struct fan_t fans[FAN_CH_COUNT] = {
 	[FAN_CH_0] = {
 		.conf = &fan_conf_0,
-		.rpm = &fan_rpm_0,
+		.rpm = &rpm_table[RPM_TABLE_CPU0],
 	},
 };
 
-#ifndef CONFIG_FANS
-
-/*
- * TODO(b/181271666): use static fan speeds until fan and sensors are
- * tuned. for now, use:
- *
- *   AP off:  33%
- *   AP  on: 100%
- */
-
-static void fan_slow(void)
+static void fan_get_rpm(int fan)
 {
-	const int duty_pct = 33;
-
-	ccprints("%s: speed %d%%", __func__, duty_pct);
+	static timestamp_t deadline;
 
-	pwm_enable(PWM_CH_FAN, 1);
-	pwm_set_duty(PWM_CH_FAN, duty_pct);
+	/* Record actual RPM every 2 minutes. */
+	if (timestamp_expired(deadline, NULL)) {
+		ccprints("fan actual rpm: %d", fan_get_rpm_actual(FAN_CH(fan)));
+		deadline.val += RECORD_TIME;
+	}
 }
 
-static void fan_max(void)
+static void fan_set_percent(int fan, int pct)
 {
-	const int duty_pct = 100;
+	int new_rpm;
 
-	ccprints("%s: speed %d%%", __func__, duty_pct);
-
-	pwm_enable(PWM_CH_FAN, 1);
-	pwm_set_duty(PWM_CH_FAN, duty_pct);
+	new_rpm = fan_percent_to_rpm(fan, pct);
+	fan_set_rpm_target(FAN_CH(fan), new_rpm);
+	fan_get_rpm(fan);
 }
 
-DECLARE_HOOK(HOOK_INIT, fan_slow, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, fan_slow, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, fan_slow, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_RESET, fan_max, HOOK_PRIO_FIRST);
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, fan_max, HOOK_PRIO_DEFAULT);
-
-#endif /* CONFIG_FANS */
+void board_override_fan_control(int fan, int *tmp)
+{
+	/*
+	 * Crota's fan speed is control by four sensors.
+	 *
+	 * Sensor charger control the speed when system's temperature
+	 * is too high.
+	 * Other sensors control normal loading's speed.
+	 *
+	 * When sensor charger is triggered, the fan speed is only
+	 * control by sensor charger, avoid heat damage to system.
+	 * When other sensors is triggered, the fan is control
+	 * by other sensors.
+	 *
+	 * Sensor SOC has two slopes for fan speed.
+	 * Sensor DDR also become a fan on/off switch.
+	 */
+	static int pct;
+	int sensor_soc;
+	int sensor_ddr;
+	int sensor_charger;
+	int sensor_ambient;
+
+	/* Decide sensor SOC temperature using which slope. */
+	if (tmp[TEMP_SENSOR_1_SOC] > SENSOR_SOC_FAN_MID) {
+		thermal_params[TEMP_SENSOR_1_SOC].temp_fan_off =
+			C_TO_K(SENSOR_SOC_FAN_MID);
+		thermal_params[TEMP_SENSOR_1_SOC].temp_fan_max =
+			C_TO_K(SENSOR_SOC_FAN_MAX);
+	} else {
+		thermal_params[TEMP_SENSOR_1_SOC].temp_fan_off =
+			C_TO_K(SENSOR_SOC_FAN_OFF);
+		thermal_params[TEMP_SENSOR_1_SOC].temp_fan_max =
+			C_TO_K(SENSOR_SOC_FAN_MID);
+	}
+
+	sensor_soc = thermal_fan_percent(
+		thermal_params[TEMP_SENSOR_1_SOC].temp_fan_off,
+		thermal_params[TEMP_SENSOR_1_SOC].temp_fan_max,
+		C_TO_K(tmp[TEMP_SENSOR_1_SOC]));
+	sensor_ddr = thermal_fan_percent(
+		thermal_params[TEMP_SENSOR_2_DDR].temp_fan_off,
+		thermal_params[TEMP_SENSOR_2_DDR].temp_fan_max,
+		C_TO_K(tmp[TEMP_SENSOR_2_DDR]));
+	sensor_charger = thermal_fan_percent(
+		thermal_params[TEMP_SENSOR_3_CHARGER].temp_fan_off,
+		thermal_params[TEMP_SENSOR_3_CHARGER].temp_fan_max,
+		C_TO_K(tmp[TEMP_SENSOR_3_CHARGER]));
+	sensor_ambient = thermal_fan_percent(
+		thermal_params[TEMP_SENSOR_4_AMBIENT].temp_fan_off,
+		thermal_params[TEMP_SENSOR_4_AMBIENT].temp_fan_max,
+		C_TO_K(tmp[TEMP_SENSOR_4_AMBIENT]));
+
+	/*
+	 * Sensor DDR turn on when temperature > 38,
+	 * turn off when temperature < 37
+	 */
+	if ((tmp[TEMP_SENSOR_2_DDR]) < SENSOR_DDR_FAN_TURN_OFF) {
+		pct = 0;
+	} else if ((tmp[TEMP_SENSOR_2_DDR]) > SENSOR_DDR_FAN_TURN_ON) {
+		/*
+		 * Decide which sensor was triggered and choose table.
+		 * Priority: charger > soc > ddr > ambient
+		 */
+		if (sensor_charger) {
+			fans[fan].rpm = &rpm_table[RPM_TABLE_CHARGER];
+			pct = sensor_charger;
+		} else if (sensor_soc) {
+			if (tmp[TEMP_SENSOR_1_SOC] > SENSOR_SOC_FAN_MID)
+				fans[fan].rpm = &rpm_table[RPM_TABLE_CPU1];
+			else
+				fans[fan].rpm = &rpm_table[RPM_TABLE_CPU0];
+			pct = sensor_soc;
+		} else if (sensor_ddr) {
+			fans[fan].rpm = &rpm_table[RPM_TABLE_DDR];
+			pct = sensor_ddr;
+		} else {
+			fans[fan].rpm = &rpm_table[RPM_TABLE_AMBIENT];
+			pct = sensor_ambient;
+		}
+	}
+
+	/* Transfer percent to rpm. */
+	fan_set_percent(fan, pct);
+}
diff --git a/board/crota/fw_config.c b/board/crota/fw_config.c
index 35fc466fd1..5feb8a2d3e 100644
--- a/board/crota/fw_config.c
+++ b/board/crota/fw_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,7 +10,7 @@
 #include "cros_board_info.h"
 #include "fw_config.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 static union brya_cbi_fw_config fw_config;
 BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
diff --git a/board/crota/fw_config.h b/board/crota/fw_config.h
index f441650ec6..407af32472 100644
--- a/board/crota/fw_config.h
+++ b/board/crota/fw_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,10 +14,7 @@
  * Source of truth is the project/brya/brya/config.star configuration file.
  */
 
-enum ec_cfg_usb_db_type {
-	DB_USB_ABSENT = 0,
-	DB_USB_ABSENT2 = 15
-};
+enum ec_cfg_usb_db_type { DB_USB_ABSENT = 0, DB_USB_ABSENT2 = 15 };
 
 enum ec_cfg_keyboard_backlight_type {
 	KEYBOARD_BACKLIGHT_DISABLED = 0,
@@ -26,12 +23,12 @@ enum ec_cfg_keyboard_backlight_type {
 
 union brya_cbi_fw_config {
 	struct {
-		enum ec_cfg_usb_db_type			usb_db : 4;
-		uint32_t				sd_db : 2;
-		uint32_t				lte_db : 1;
-		enum ec_cfg_keyboard_backlight_type	kb_bl : 1;
-		uint32_t				audio : 3;
-		uint32_t				reserved_1 : 21;
+		enum ec_cfg_usb_db_type usb_db : 4;
+		uint32_t sd_db : 2;
+		uint32_t lte_db : 1;
+		enum ec_cfg_keyboard_backlight_type kb_bl : 1;
+		uint32_t audio : 3;
+		uint32_t reserved_1 : 21;
 	};
 	uint32_t raw_value;
 };
diff --git a/board/crota/gpio.inc b/board/crota/gpio.inc
index 655fc68060..7668442b7b 100644
--- a/board/crota/gpio.inc
+++ b/board/crota/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2022 The Chromium OS Authors. All rights reserved.
+ * Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,10 +10,10 @@
 /* INTERRUPT GPIOs: */
 GPIO_INT(ACOK_OD,                        PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
 GPIO_INT(EC_ACCEL_INT_R_L,               PIN(8, 1), GPIO_SEL_1P8V | GPIO_INT_FALLING, lis2dw12_interrupt)
-GPIO_INT(EC_IMU_INT_R_L,                 PIN(5, 6), GPIO_SEL_1P8V | GPIO_INT_FALLING, lsm6dso_interrupt)
+GPIO_INT(EC_IMU_INT_R_L,                 PIN(5, 6), GPIO_SEL_1P8V | GPIO_INT_FALLING, motion_interrupt)
 GPIO_INT(EC_PROCHOT_IN_L,                PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
-GPIO_INT(EC_VOLDN_BTN_ODL,               PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(EC_VOLUP_BTN_ODL,               PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(EC_VOLDN_BTN_ODL,               PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(EC_VOLUP_BTN_ODL,               PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
 GPIO_INT(EC_WP_ODL,                      PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
 GPIO_INT(GSC_EC_PWR_BTN_ODL,             PIN(0, 1), GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW, power_button_interrupt)
 GPIO_INT(LID_OPEN,                       PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
@@ -69,6 +69,7 @@ GPIO(PCH_PWROK,                      PIN(7, 2), GPIO_OUT_LOW)
 GPIO(SYS_RST_ODL,                    PIN(C, 5), GPIO_ODR_HIGH)
 GPIO(USB_C0_C1_TCPC_RST_ODL,         PIN(A, 7), GPIO_ODR_LOW)
 GPIO(VCCST_PWRGD_OD,                 PIN(A, 4), GPIO_ODR_LOW)
+GPIO(EC_SENSOR_STRAP,                PIN(5, 7), GPIO_INPUT)
 
 /* UART alternate functions */
 ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)              /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */
@@ -109,7 +110,6 @@ UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
 UNUSED(PIN(3, 2))       /* GPO32/TRIS_L */
 UNUSED(PIN(3, 5))       /* GPO35/CR_SOUT4/TEST_L */
 UNUSED(PIN(6, 6))       /* GPIO66 */
-UNUSED(PIN(5, 7))       /* GPIO57/SER_IRQ/ESPI_ALERT_L */
 UNUSED(PIN(D, 4))       /* GPIOD4/CR_SIN3 */
 UNUSED(PIN(5, 0))       /* GPIO50 */
 UNUSED(PIN(F, 5))       /* GPIOF5/I2C5_SCL1 */
diff --git a/board/crota/i2c.c b/board/crota/i2c.c
index 1fc1126282..681e600bf2 100644
--- a/board/crota/i2c.c
+++ b/board/crota/i2c.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,7 +9,7 @@
 #include "hooks.h"
 #include "i2c.h"
 
-#define BOARD_ID_FAST_PLUS_CAPABLE	2
+#define BOARD_ID_FAST_PLUS_CAPABLE 2
 
 /* I2C port map configuration */
 const struct i2c_port_t i2c_ports[] = {
@@ -63,19 +63,3 @@ const struct i2c_port_t i2c_ports[] = {
 	},
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/*
- * I2C controllers are initialized in main.c. This sets the speed much
- * later, but before I2C peripherals are initialized.
- */
-static void set_board_legacy_i2c_speeds(void)
-{
-	if (get_board_id() >= BOARD_ID_FAST_PLUS_CAPABLE)
-		return;
-
-	ccprints("setting USB DB I2C buses to 400 kHz\n");
-
-	i2c_set_freq(I2C_PORT_USB_C0_C1_TCPC, I2C_FREQ_400KHZ);
-	i2c_set_freq(I2C_PORT_USB_C0_C1_PPC, I2C_FREQ_400KHZ);
-}
-DECLARE_HOOK(HOOK_INIT, set_board_legacy_i2c_speeds, HOOK_PRIO_INIT_I2C - 1);
diff --git a/board/crota/keyboard.c b/board/crota/keyboard.c
index d193ac9034..8911d48b81 100644
--- a/board/crota/keyboard.c
+++ b/board/crota/keyboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -41,8 +41,8 @@ static const struct ec_response_keybd_config crota_kb = {
 	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
 };
 
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	return &crota_kb;
 }
diff --git a/board/crota/led.c b/board/crota/led.c
index 0a9c9503fe..83f3789e36 100644
--- a/board/crota/led.c
+++ b/board/crota/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,6 +8,7 @@
 #include <stdint.h>
 
 #include "charge_manager.h"
+#include "charge_state.h"
 #include "common.h"
 #include "compile_time_macros.h"
 #include "ec_commands.h"
@@ -21,23 +22,27 @@
 #define BAT_LED_OFF_LVL 0
 
 __override const int led_charge_lvl_1 = 5;
-__override const int led_charge_lvl_2 = 100;
+__override const int led_charge_lvl_2 = 96;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_FACTORY_TEST]         = {
-					{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC}
-	},
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_WHITE,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_WHITE,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 1 * LED_ONE_SEC } },
+	};
 
 const enum ec_led_id supported_led_ids[] = {
 	EC_LED_ID_BATTERY_LED,
@@ -87,3 +92,15 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 
 	return EC_SUCCESS;
 }
+
+__override enum led_states board_led_get_state(enum led_states desired_state)
+{
+	/* Make sure when battery is pre-charging, the LED will blinking.
+	 * Otherwise it will wait 30 seconds then blinking.
+	 */
+	if (charge_get_state() == PWR_STATE_IDLE) {
+		if (charge_get_flags() & CHARGE_FLAG_EXTERNAL_POWER)
+			desired_state = STATE_BATTERY_ERROR;
+	}
+	return desired_state;
+}
diff --git a/board/crota/pwm.c b/board/crota/pwm.c
index 51bee909ff..26da4e4f7d 100644
--- a/board/crota/pwm.c
+++ b/board/crota/pwm.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/crota/sensors.c b/board/crota/sensors.c
index baa82f7b56..bbd2686512 100644
--- a/board/crota/sensors.c
+++ b/board/crota/sensors.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,8 +8,8 @@
 #include "accelgyro.h"
 #include "adc.h"
 #include "driver/accel_lis2dw12.h"
+#include "driver/accelgyro_bmi_common.h"
 #include "driver/accelgyro_lsm6dso.h"
-#include "driver/als_tcs3400_public.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "motion_sense.h"
@@ -19,15 +19,15 @@
 
 /* ADC configuration */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1_DDR_SOC] = {
-		.name = "TEMP_DDR_SOC",
+	[ADC_TEMP_SENSOR_1_SOC] = {
+		.name = "TEMP_SOC",
 		.input_ch = NPCX_ADC_CH0,
 		.factor_mul = ADC_MAX_VOLT,
 		.factor_div = ADC_READ_MAX + 1,
 		.shift = 0,
 	},
-	[ADC_TEMP_SENSOR_2_AMBIENT] = {
-		.name = "TEMP_AMBIENT",
+	[ADC_TEMP_SENSOR_2_DDR] = {
+		.name = "TEMP_DDR",
 		.input_ch = NPCX_ADC_CH1,
 		.factor_mul = ADC_MAX_VOLT,
 		.factor_div = ADC_READ_MAX + 1,
@@ -40,8 +40,8 @@ const struct adc_t adc_channels[] = {
 		.factor_div = ADC_READ_MAX + 1,
 		.shift = 0,
 	},
-	[ADC_TEMP_SENSOR_4_WWAN] = {
-		.name = "TEMP_WWAN",
+	[ADC_TEMP_SENSOR_4_AMBIENT] = {
+		.name = "TEMP_AMBIENT",
 		.input_ch = NPCX_ADC_CH7,
 		.factor_mul = ADC_MAX_VOLT,
 		.factor_div = ADC_READ_MAX + 1,
@@ -54,20 +54,19 @@ K_MUTEX_DEFINE(g_lid_accel_mutex);
 K_MUTEX_DEFINE(g_base_accel_mutex);
 static struct stprivate_data g_lis2dw12_data;
 static struct lsm6dso_data lsm6dso_data;
+static struct bmi_drv_data_t g_bmi260_data;
 
-/* TODO(b/184779333): calibrate the orientation matrix on later board stage */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
-/* TODO(b/184779743): verify orientation matrix */
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, FLOAT_TO_FP(1), 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
+
+static const mat33_fp_t base_standard_ref_id_1 = { { 0, FLOAT_TO_FP(1), 0 },
+						   { FLOAT_TO_FP(1), 0, 0 },
+						   { 0, 0, FLOAT_TO_FP(-1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
@@ -145,6 +144,75 @@ struct motion_sensor_t motion_sensors[] = {
 };
 const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
+struct motion_sensor_t bmi260_base_accel = {
+	.name = "Base Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_BMI260,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &bmi260_drv,
+	.mutex = &g_base_accel_mutex,
+	.drv_data = &g_bmi260_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
+	.rot_standard_ref = &base_standard_ref_id_1,
+	.min_frequency = BMI_ACCEL_MIN_FREQ,
+	.max_frequency = BMI_ACCEL_MAX_FREQ,
+	.default_range = 4, /* g */
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+		/* Sensor on in S3 */
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+			.ec_rate = 100 * MSEC,
+		},
+	},
+};
+struct motion_sensor_t bmi260_base_gyro = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_BMI260,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &bmi260_drv,
+	.mutex = &g_base_accel_mutex,
+	.drv_data = &g_bmi260_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &base_standard_ref_id_1,
+	.min_frequency = BMI_GYRO_MIN_FREQ,
+	.max_frequency = BMI_GYRO_MAX_FREQ,
+};
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	if (get_board_id() > 1) {
+		if (gpio_get_level(GPIO_EC_SENSOR_STRAP) == 0)
+			bmi260_interrupt(signal);
+		else
+			lsm6dso_interrupt(signal);
+	} else
+		lsm6dso_interrupt(signal);
+}
+
+static void board_update_motion_sensor_config(void)
+{
+	if (get_board_id() > 1 && gpio_get_level(GPIO_EC_SENSOR_STRAP) == 0) {
+		motion_sensors[BASE_ACCEL] = bmi260_base_accel;
+		motion_sensors[BASE_GYRO] = bmi260_base_gyro;
+		ccprints("BASE IMU is BMI260");
+	} else {
+		ccprints("BASE IMU is LSM6DSO");
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_update_motion_sensor_config,
+	     HOOK_PRIO_INIT_I2C + 1);
+
 static void baseboard_sensors_init(void)
 {
 	/* Enable gpio interrupt for lid accel sensor */
@@ -156,17 +224,17 @@ DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_INIT_I2C + 1);
 
 /* Temperature sensor configuration */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1_DDR_SOC] = {
-		.name = "DDR and SOC",
+	[TEMP_SENSOR_1_SOC] = {
+		.name = "SOC",
 		.type = TEMP_SENSOR_TYPE_BOARD,
 		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_1_DDR_SOC,
+		.idx = ADC_TEMP_SENSOR_1_SOC,
 	},
-	[TEMP_SENSOR_2_AMBIENT] = {
-		.name = "Ambient",
+	[TEMP_SENSOR_2_DDR] = {
+		.name = "DDR",
 		.type = TEMP_SENSOR_TYPE_BOARD,
 		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_2_AMBIENT,
+		.idx = ADC_TEMP_SENSOR_2_DDR,
 	},
 	[TEMP_SENSOR_3_CHARGER] = {
 		.name = "Charger",
@@ -174,124 +242,53 @@ const struct temp_sensor_t temp_sensors[] = {
 		.read = get_temp_3v3_30k9_47k_4050b,
 		.idx = ADC_TEMP_SENSOR_3_CHARGER,
 	},
-	[TEMP_SENSOR_4_WWAN] = {
-		.name = "WWAN",
+	[TEMP_SENSOR_4_AMBIENT] = {
+		.name = "Ambient",
 		.type = TEMP_SENSOR_TYPE_BOARD,
 		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_4_WWAN,
+		.idx = ADC_TEMP_SENSOR_4_AMBIENT,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
-/*
- * TODO(b/180681346): update for Alder Lake/brya
- *
- * Alder Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
- * 130 C.  However, sensor is located next to DDR, so we need to use the lower
- * DDR temperature limit (85 C)
- */
-/*
- * TODO(b/202062363): Remove when clang is fixed.
- */
-#define THERMAL_CPU \
-	{ \
+#define THERMAL_CPU              \
+	{                        \
 		.temp_host = { \
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(85), \
-			[EC_TEMP_THRESH_HALT] = C_TO_K(90), \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(77), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
 		}, \
 		.temp_host_release = { \
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(80), \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(77), \
 		}, \
-		.temp_fan_off = C_TO_K(35), \
-		.temp_fan_max = C_TO_K(60), \
+		.temp_fan_off = C_TO_K(30), \
+		.temp_fan_max = C_TO_K(47), \
 	}
 __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 
-/*
- * TODO(b/180681346): update for Alder Lake/brya
- *
- * Inductor limits - used for both charger and PP3300 regulator
- *
- * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
- *
- * Charger max recommended temperature 100C, max absolute temperature 125C
- * PP3300 regulator: operating range -40 C to 145 C
- *
- * Inductors: limit of 125c
- * PCB: limit is 80c
- */
-/*
- * TODO(b/202062363): Remove when clang is fixed.
- */
-#define THERMAL_AMBIENT \
-	{ \
-		.temp_host = { \
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(85), \
-			[EC_TEMP_THRESH_HALT] = C_TO_K(90), \
-		}, \
-		.temp_host_release = { \
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(80), \
-		}, \
-		.temp_fan_off = C_TO_K(35), \
-		.temp_fan_max = C_TO_K(60), \
+#define THERMAL_DDR                                                     \
+	{                                                               \
+		.temp_fan_off = C_TO_K(56), .temp_fan_max = C_TO_K(59), \
 	}
-__maybe_unused static const struct ec_thermal_config thermal_ambient =
-	THERMAL_AMBIENT;
+__maybe_unused static const struct ec_thermal_config thermal_ddr = THERMAL_DDR;
 
-/*
- * Inductor limits - used for both charger and PP3300 regulator
- *
- * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
- *
- * Charger max recommended temperature 125C, max absolute temperature 150C
- * PP3300 regulator: operating range -40 C to 125 C
- *
- * Inductors: limit of 125c
- * PCB: limit is 80c
- */
-/*
- * TODO(b/202062363): Remove when clang is fixed.
- */
-#define THERMAL_CHARGER \
-	{ \
-		.temp_host = { \
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(105), \
-			[EC_TEMP_THRESH_HALT] = C_TO_K(120), \
-		}, \
-		.temp_host_release = { \
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(90), \
-		}, \
-		.temp_fan_off = C_TO_K(35), \
-		.temp_fan_max = C_TO_K(65), \
+#define THERMAL_CHARGER                                                 \
+	{                                                               \
+		.temp_fan_off = C_TO_K(67), .temp_fan_max = C_TO_K(70), \
 	}
 __maybe_unused static const struct ec_thermal_config thermal_charger =
 	THERMAL_CHARGER;
 
-/*
- * TODO(b/180681346): update for brya WWAN module
- */
-/*
- * TODO(b/202062363): Remove when clang is fixed.
- */
-#define THERMAL_WWAN \
-	{ \
-		.temp_host = { \
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(130), \
-			[EC_TEMP_THRESH_HALT] = C_TO_K(130), \
-		}, \
-		.temp_host_release = { \
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(100), \
-		}, \
-		.temp_fan_off = C_TO_K(35), \
-		.temp_fan_max = C_TO_K(60), \
+#define THERMAL_AMBIENT                                                 \
+	{                                                               \
+		.temp_fan_off = C_TO_K(38), .temp_fan_max = C_TO_K(45), \
 	}
-__maybe_unused static const struct ec_thermal_config thermal_wwan =
-	THERMAL_WWAN;
+__maybe_unused static const struct ec_thermal_config thermal_ambient =
+	THERMAL_AMBIENT;
 
 struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_DDR_SOC] = THERMAL_CPU,
-	[TEMP_SENSOR_2_AMBIENT] = THERMAL_AMBIENT,
+	[TEMP_SENSOR_1_SOC] = THERMAL_CPU,
+	[TEMP_SENSOR_2_DDR] = THERMAL_DDR,
 	[TEMP_SENSOR_3_CHARGER] = THERMAL_CHARGER,
-	[TEMP_SENSOR_4_WWAN] = THERMAL_WWAN,
+	[TEMP_SENSOR_4_AMBIENT] = THERMAL_AMBIENT,
 };
 BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
diff --git a/board/crota/usbc_config.c b/board/crota/usbc_config.c
index a06631489f..84b0934dd8 100644
--- a/board/crota/usbc_config.c
+++ b/board/crota/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -36,15 +36,11 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 #ifdef CONFIG_ZEPHYR
-enum ioex_port {
-	IOEX_C0_NCT38XX = 0,
-	IOEX_C1_NCT38XX,
-	IOEX_PORT_COUNT
-};
+enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_C1_NCT38XX, IOEX_PORT_COUNT };
 #endif /* CONFIG_ZEPHYR */
 
 /* USBC TCPC configuration */
@@ -102,40 +98,53 @@ BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
 /* USBC mux configuration - Alder Lake includes internal mux */
-static const struct usb_mux usbc0_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+static const struct usb_mux_chain usbc0_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
-static const struct usb_mux usbc1_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+static const struct usb_mux_chain usbc1_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
-struct usb_mux soc_side_bb_retimer_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &bb_usb_retimer,
-	.hpd_update = bb_retimer_hpd_update,
-	.i2c_port = I2C_PORT_USB_C0_C1_MUX,
-	.i2c_addr_flags = USBC_PORT_C1_SOC_BB_RETIMER_I2C_ADDR,
-	.next_mux = &usbc1_tcss_usb_mux,
+struct usb_mux_chain soc_side_bb_retimer_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C0_C1_MUX,
+			.i2c_addr_flags = USBC_PORT_C1_SOC_BB_RETIMER_I2C_ADDR,
+		},
+	.next = &usbc1_tcss_usb_mux,
 };
-const struct usb_mux usb_muxes[] = {
+const struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C0_C1_MUX,
-		.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc0_tcss_usb_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C0_C1_MUX,
+			.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc0_tcss_usb_mux,
 	},
 	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C0_C1_MUX,
-		.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
-		.next_mux = &soc_side_bb_retimer_usb_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C0_C1_MUX,
+			.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &soc_side_bb_retimer_usb_mux,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
@@ -204,8 +213,8 @@ int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
 	}
 
 	if (voltage < BC12_MIN_VOLTAGE) {
-		CPRINTS("%s: port %d: vbus %d lower than %d", __func__,
-			port, voltage, BC12_MIN_VOLTAGE);
+		CPRINTS("%s: port %d: vbus %d lower than %d", __func__, port,
+			voltage, BC12_MIN_VOLTAGE);
 		return 1;
 	}
 
diff --git a/board/crota/usbc_config.h b/board/crota/usbc_config.h
index 55134ce79e..63e077ea95 100644
--- a/board/crota/usbc_config.h
+++ b/board/crota/usbc_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,14 +9,10 @@
 #define __CROS_EC_USBC_CONFIG_H
 
 #ifndef CONFIG_ZEPHYR
-#define CONFIG_USB_PD_PORT_MAX_COUNT	2
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
 #endif
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 void config_usb_db_type(void);
 
diff --git a/board/dalboz/battery.c b/board/dalboz/battery.c
index 5a90a767c8..e5adf3c4b3 100644
--- a/board/dalboz/battery.c
+++ b/board/dalboz/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/dalboz/board.c b/board/dalboz/board.c
index e8690d5cc1..471446878f 100644
--- a/board/dalboz/board.c
+++ b/board/dalboz/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,7 +10,7 @@
 #include "driver/accelgyro_lsm6dsm.h"
 #include "driver/bc12/pi3usb9201.h"
 #include "driver/ioexpander/pcal6408.h"
-#include "driver/ppc/aoz1380.h"
+#include "driver/ppc/aoz1380_public.h"
 #include "driver/ppc/nx20p348x.h"
 #include "driver/retimer/pi3hdx1204.h"
 #include "driver/tcpm/nct38xx.h"
@@ -36,8 +36,8 @@
 #include "usb_pd_tcpm.h"
 #include "usbc_ppc.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* This I2C moved. Temporarily detect and support the V0 HW. */
 int I2C_PORT_BATTERY = I2C_PORT_BATTERY_V1;
@@ -84,11 +84,9 @@ static struct stprivate_data g_lis2dwl_data;
 static struct lsm6dsm_data g_lsm6dsm_data = LSM6DSM_DATA;
 
 /* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, FLOAT_TO_FP(-1), 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
 
 /* TODO(gcc >= 5.0) Remove the casts to const pointer at rot_standard_ref */
 struct motion_sensor_t motion_sensors[] = {
@@ -203,9 +201,7 @@ static void board_chipset_resume(void)
 	if (ec_config_has_hdmi_retimer_pi3hdx1204()) {
 		ioex_set_level(IOEX_EN_PWR_HDMI_DB, 1);
 		msleep(PI3HDX1204_POWER_ON_DELAY_MS);
-		pi3hdx1204_enable(I2C_PORT_TCPC1,
-				  PI3HDX1204_I2C_ADDR_FLAGS,
-				  1);
+		pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS, 1);
 	}
 }
 DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
@@ -215,16 +211,13 @@ static void board_chipset_suspend(void)
 	ioex_set_level(IOEX_USB_A1_RETIMER_EN, 0);
 
 	if (ec_config_has_hdmi_retimer_pi3hdx1204()) {
-		pi3hdx1204_enable(I2C_PORT_TCPC1,
-				  PI3HDX1204_I2C_ADDR_FLAGS,
-				  0);
+		pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS, 0);
 		ioex_set_level(IOEX_EN_PWR_HDMI_DB, 0);
 	}
 }
 DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
 
-static int board_ps8743_mux_set(const struct usb_mux *me,
-				mux_state_t mux_state)
+static int board_ps8743_mux_set(const struct usb_mux *me, mux_state_t mux_state)
 {
 	if (mux_state & USB_PD_MUX_DP_ENABLED)
 		/* Enable IN_HPD on the DB */
@@ -236,7 +229,6 @@ static int board_ps8743_mux_set(const struct usb_mux *me,
 	return EC_SUCCESS;
 }
 
-
 /*****************************************************************************
  * USB-C
  */
@@ -274,33 +266,45 @@ const struct usb_mux_driver usbc0_sbu_mux_driver = {
  * Since FSUSB42UMX is not a i2c device, .i2c_port and
  * .i2c_addr_flags are not required here.
  */
-const struct usb_mux usbc0_sbu_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &usbc0_sbu_mux_driver,
+const struct usb_mux_chain usbc0_sbu_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &usbc0_sbu_mux_driver,
+		},
 };
 
-struct usb_mux usbc1_amd_fp5_usb_mux = {
+struct usb_mux usbc1_ps8xxx_mux = {
 	.usb_port = USBC_PORT_C1,
-	.i2c_port = I2C_PORT_USB_AP_MUX,
-	.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
-	.driver = &amd_fp5_usb_mux_driver,
-	.flags = USB_MUX_FLAG_SET_WITHOUT_FLIP,
+	.i2c_port = I2C_PORT_TCPC1,
+	.i2c_addr_flags = PS8743_I2C_ADDR1_FLAG,
+	.driver = &ps8743_usb_mux_driver,
+};
+
+struct usb_mux_chain usbc1_amd_fp5_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.i2c_port = I2C_PORT_USB_AP_MUX,
+			.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
+			.driver = &amd_fp5_usb_mux_driver,
+			.flags = USB_MUX_FLAG_SET_WITHOUT_FLIP,
+		},
 };
 
-struct usb_mux usb_muxes[] = {
+struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.i2c_port = I2C_PORT_USB_AP_MUX,
-		.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
-		.driver = &amd_fp5_usb_mux_driver,
-		.next_mux = &usbc0_sbu_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.i2c_port = I2C_PORT_USB_AP_MUX,
+			.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
+			.driver = &amd_fp5_usb_mux_driver,
+		},
+		.next = &usbc0_sbu_mux,
 	},
 	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = PS8743_I2C_ADDR1_FLAG,
-		.driver = &ps8743_usb_mux_driver,
-		.next_mux = &usbc1_amd_fp5_usb_mux,
+		.mux = &usbc1_ps8xxx_mux,
+		.next = &usbc1_amd_fp5_usb_mux,
 	}
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
@@ -343,8 +347,7 @@ void ppc_interrupt(enum gpio_signal signal)
 
 int board_set_active_charge_port(int port)
 {
-	int is_valid_port = (port >= 0 &&
-			     port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	int i;
 
 	if (port == CHARGE_PORT_NONE) {
@@ -365,7 +368,6 @@ int board_set_active_charge_port(int port)
 		return EC_ERROR_INVAL;
 	}
 
-
 	/* Check if the port is sourcing VBUS. */
 	if (ppc_is_sourcing_vbus(port)) {
 		CPRINTFUSB("Skip enable C%d", port);
@@ -467,7 +469,6 @@ static void reset_nct38xx_port(int port)
 		msleep(NCT3807_RESET_POST_DELAY_MS);
 }
 
-
 void board_reset_pd_mcu(void)
 {
 	/* Reset TCPC0 */
@@ -538,11 +539,9 @@ int board_pd_set_frs_enable(int port, int enable)
 
 	/* Use the TCPC to enable fast switch when FRS included */
 	if (port == USBC_PORT_C0) {
-		rv = ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN,
-				    !!enable);
+		rv = ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN, !!enable);
 	} else {
-		rv = ioex_set_level(IOEX_USB_C1_TCPC_FASTSW_CTL_EN,
-				    !!enable);
+		rv = ioex_set_level(IOEX_USB_C1_TCPC_FASTSW_CTL_EN, !!enable);
 	}
 
 	return rv;
@@ -552,17 +551,17 @@ static void setup_fw_config(void)
 {
 	uint32_t board_version = 0;
 
-	if (cbi_get_board_version(&board_version) == EC_SUCCESS
-	    && board_version >= 2) {
+	if (cbi_get_board_version(&board_version) == EC_SUCCESS &&
+	    board_version >= 2) {
 		ccprints("PS8743 USB MUX");
-		usb_muxes[USBC_PORT_C1].i2c_addr_flags = PS8743_I2C_ADDR1_FLAG;
-		usb_muxes[USBC_PORT_C1].driver = &ps8743_usb_mux_driver;
-		usb_muxes[USBC_PORT_C1].board_set = &board_ps8743_mux_set;
+		usbc1_ps8xxx_mux.i2c_addr_flags = PS8743_I2C_ADDR1_FLAG;
+		usbc1_ps8xxx_mux.driver = &ps8743_usb_mux_driver;
+		usbc1_ps8xxx_mux.board_set = &board_ps8743_mux_set;
 	} else {
 		ccprints("PS8740 USB MUX");
-		usb_muxes[USBC_PORT_C1].i2c_addr_flags = PS8740_I2C_ADDR0_FLAG;
-		usb_muxes[USBC_PORT_C1].driver = &ps8740_usb_mux_driver;
-		usb_muxes[USBC_PORT_C1].board_set = NULL;
+		usbc1_ps8xxx_mux.i2c_addr_flags = PS8740_I2C_ADDR0_FLAG;
+		usbc1_ps8xxx_mux.driver = &ps8740_usb_mux_driver;
+		usbc1_ps8xxx_mux.board_set = NULL;
 	}
 
 	if (ec_config_get_usb_db() == DALBOZ_DB_D_OPT2_USBA_HDMI) {
diff --git a/board/dalboz/board.h b/board/dalboz/board.h
index bcb60bda0b..967d1dce8f 100644
--- a/board/dalboz/board.h
+++ b/board/dalboz/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -40,42 +40,36 @@
 #define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
 #define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
 
-
-
 /* GPIO mapping from board specific name to EC common name. */
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_EC_BATT_PRES_ODL
-#define CONFIG_SCI_GPIO			GPIO_EC_FCH_SCI_ODL
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_AP_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT_L		GPIO_EC_EDP_BL_DISABLE
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_FCH_PWR_BTN_L
-#define GPIO_PCH_RSMRST_L		GPIO_EC_FCH_RSMRST_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S5_L		GPIO_SLP_S5_L
-#define GPIO_PCH_SYS_PWROK		GPIO_EC_FCH_PWROK
-#define GPIO_PCH_WAKE_L			GPIO_EC_FCH_WAKE_L
-#define GPIO_POWER_BUTTON_L		GPIO_EC_PWR_BTN_ODL
-#define GPIO_S0_PGOOD			GPIO_S0_PWROK_OD
-#define GPIO_S5_PGOOD			GPIO_EC_PWROK_OD
-#define GPIO_SYS_RESET_L		GPIO_EC_SYS_RST_L
-#define GPIO_VOLUME_DOWN_L		GPIO_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
+#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL
+#define CONFIG_SCI_GPIO GPIO_EC_FCH_SCI_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_AP_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_EDP_BL_DISABLE
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PCH_PWRBTN_L GPIO_EC_FCH_PWR_BTN_L
+#define GPIO_PCH_RSMRST_L GPIO_EC_FCH_RSMRST_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L
+#define GPIO_PCH_SYS_PWROK GPIO_EC_FCH_PWROK
+#define GPIO_PCH_WAKE_L GPIO_EC_FCH_WAKE_L
+#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL
+#define GPIO_S0_PGOOD GPIO_S0_PWROK_OD
+#define GPIO_S5_PGOOD GPIO_EC_PWROK_OD
+#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L
+#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
 
 #ifndef __ASSEMBLER__
 
 /* This I2C moved. Temporarily detect and support the V0 HW. */
 extern int I2C_PORT_BATTERY;
 
-enum adc_channel {
-	ADC_TEMP_SENSOR_CHARGER,
-	ADC_TEMP_SENSOR_SOC,
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_TEMP_SENSOR_CHARGER, ADC_TEMP_SENSOR_SOC, ADC_CH_COUNT };
 
 enum battery_type {
 	BATTERY_SMP,
@@ -84,10 +78,7 @@ enum battery_type {
 	BATTERY_TYPE_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_COUNT };
 
 enum ioex_port {
 	IOEX_C0_NCT3807 = 0,
@@ -96,9 +87,7 @@ enum ioex_port {
 	IOEX_PORT_COUNT
 };
 
-#define PORT_TO_HPD(port) ((port == 0) \
-	? GPIO_USB3_C0_DP2_HPD \
-	: GPIO_DP1_HPD)
+#define PORT_TO_HPD(port) ((port == 0) ? GPIO_USB3_C0_DP2_HPD : GPIO_DP1_HPD)
 
 enum temp_sensor_id {
 	TEMP_SENSOR_CHARGER = 0,
@@ -107,17 +96,9 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum usba_port {
-	USBA_PORT_A0 = 0,
-	USBA_PORT_A1,
-	USBA_PORT_COUNT
-};
+enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT };
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 /*****************************************************************************
  * CBI EC FW Configuration
@@ -166,31 +147,25 @@ enum ec_cfg_usb_db_type {
 
 #include "cbi_ec_fw_config.h"
 
-#define HAS_USBC1 \
-			(BIT(DALBOZ_DB_D_OPT1_USBAC))
+#define HAS_USBC1 (BIT(DALBOZ_DB_D_OPT1_USBAC))
 
 static inline bool ec_config_has_usbc1(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_USBC1);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_USBC1);
 }
 
-#define HAS_USBC1_RETIMER_PS8740 \
-			(BIT(DALBOZ_DB_D_OPT1_USBAC))
+#define HAS_USBC1_RETIMER_PS8740 (BIT(DALBOZ_DB_D_OPT1_USBAC))
 
 static inline bool ec_config_has_usbc1_retimer_ps8740(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_USBC1_RETIMER_PS8740);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_USBC1_RETIMER_PS8740);
 }
 
-#define HAS_HDMI_RETIMER_PI3HDX1204 \
-			(BIT(DALBOZ_DB_D_OPT2_USBA_HDMI))
+#define HAS_HDMI_RETIMER_PI3HDX1204 (BIT(DALBOZ_DB_D_OPT2_USBA_HDMI))
 
 static inline bool ec_config_has_hdmi_retimer_pi3hdx1204(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_HDMI_RETIMER_PI3HDX1204);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_HDMI_RETIMER_PI3HDX1204);
 }
 
 /* These IO expander GPIOs vary with DB option. */
diff --git a/board/dalboz/build.mk b/board/dalboz/build.mk
index 4ca0cbd96f..cd58c2b91b 100644
--- a/board/dalboz/build.mk
+++ b/board/dalboz/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/dalboz/ec.tasklist b/board/dalboz/ec.tasklist
index 41b83cf4f3..4bb60ed55d 100644
--- a/board/dalboz/ec.tasklist
+++ b/board/dalboz/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/dalboz/gpio.inc b/board/dalboz/gpio.inc
index 74fe019b47..386898f013 100644
--- a/board/dalboz/gpio.inc
+++ b/board/dalboz/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/dalboz/led.c b/board/dalboz/led.c
index 53e94e84d6..d9614539e5 100644
--- a/board/dalboz/led.c
+++ b/board/dalboz/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,44 +8,51 @@
 #include "led_common.h"
 #include "led_onoff_states.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
 __override const int led_charge_lvl_1;
 __override const int led_charge_lvl_2 = 100;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]       = {{EC_LED_COLOR_GREEN,  2 * LED_ONE_SEC},
-					{EC_LED_COLOR_RED, 2 * LED_ONE_SEC} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_GREEN,  2 * LED_ONE_SEC},
-					{EC_LED_COLOR_RED, 2 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_GREEN,
+					     2 * LED_ONE_SEC },
+					   { EC_LED_COLOR_RED,
+					     2 * LED_ONE_SEC } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_GREEN,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_GREEN,
+					    2 * LED_ONE_SEC },
+					  { EC_LED_COLOR_RED,
+					    2 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_GREEN,
+					   LED_INDEFINITE } },
+	};
 
 BUILD_ASSERT(ARRAY_SIZE(led_bat_state_table) == LED_NUM_STATES);
 
 __override const struct led_descriptor
-			led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-				{LED_OFF,          0.5 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 3 * LED_ONE_SEC },
+					       { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
 BUILD_ASSERT(ARRAY_SIZE(led_pwr_state_table) == PWR_LED_NUM_STATES);
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
diff --git a/board/damu/battery.c b/board/damu/battery.c
index c85240a108..2c3b259a23 100644
--- a/board/damu/battery.c
+++ b/board/damu/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/damu/board.c b/board/damu/board.c
index 8a97e53afb..ddc8885e22 100644
--- a/board/damu/board.c
+++ b/board/damu/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -30,6 +30,7 @@
 #include "it8801.h"
 #include "keyboard_scan.h"
 #include "lid_switch.h"
+#include "panic.h"
 #include "power.h"
 #include "power_button.h"
 #include "pwm.h"
@@ -46,8 +47,8 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
@@ -59,40 +60,34 @@ static void tcpc_alert_event(enum gpio_signal signal)
 /******************************************************************************/
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] =  {"BOARD_ID",  3300, 4096, 0, STM32_AIN(10)},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)},
+	[ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(10) },
+	[ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /******************************************************************************/
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "typec",
-		.port = 0,
-		.kbps = 400,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	},
-	{
-		.name = "other",
-		.port = 1,
-		.kbps = 100,
-		.scl  = GPIO_I2C2_SCL,
-		.sda  = GPIO_I2C2_SDA
-	},
+	{ .name = "typec",
+	  .port = 0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "other",
+	  .port = 1,
+	  .kbps = 100,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
 const struct i2c_port_t i2c_bitbang_ports[] = {
-	{
-		.name = "battery",
-		.port = 2,
-		.kbps = 100,
-		.scl  = GPIO_I2C3_SCL,
-		.sda  = GPIO_I2C3_SDA,
-		.drv = &bitbang_drv
-	},
+	{ .name = "battery",
+	  .port = 2,
+	  .kbps = 100,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA,
+	  .drv = &bitbang_drv },
 };
 const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
 
@@ -100,8 +95,8 @@ const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
 
 /* power signal list.  Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
+	{ GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" },
+	{ GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" },
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
@@ -157,8 +152,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-static void board_hpd_status(const struct usb_mux *me,
-			     mux_state_t mux_state,
+static void board_hpd_status(const struct usb_mux *me, mux_state_t mux_state,
 			     bool *ack_required)
 {
 	/* This driver does not use host command ACKs */
@@ -171,13 +165,16 @@ static void board_hpd_status(const struct usb_mux *me,
 	host_set_single_event(EC_HOST_EVENT_USB_MUX);
 }
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+				.hpd_update = &board_hpd_status,
+			},
 	},
 };
 
@@ -239,12 +236,12 @@ int board_set_active_charge_port(int charge_port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-			       CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 int board_discharge_on_ac(int enable)
@@ -301,8 +298,7 @@ static void board_spi_enable(void)
 	/* Pin mux spi peripheral toward the sensor. */
 	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
 }
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP,
-	     board_spi_enable,
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_spi_enable,
 	     MOTION_SENSE_HOOK_PRIO - 1);
 
 static void board_spi_disable(void)
@@ -316,8 +312,7 @@ static void board_spi_disable(void)
 	spi_enable(&spi_devices[0], 0);
 	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
 }
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN,
-	     board_spi_disable,
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_spi_disable,
 	     MOTION_SENSE_HOOK_PRIO + 1);
 #endif /* !VARIANT_KUKUI_NO_SENSORS */
 
@@ -356,17 +351,13 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Rotation matrixes */
-static const mat33_fp_t base_standard_ref = {
-	{FLOAT_TO_FP(1), 0, 0},
-	{0, FLOAT_TO_FP(-1), 0},
-	{0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, FLOAT_TO_FP(-1), 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
 
-static const mat33_fp_t lid_standard_ref = {
-	{FLOAT_TO_FP(1), 0, 0},
-	{0, FLOAT_TO_FP(1), 0},
-	{0, 0, FLOAT_TO_FP(1) }
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(1), 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
 
 /* sensor private data */
 /* Lid accel private data */
diff --git a/board/damu/board.h b/board/damu/board.h
index 1d2993443a..49875e6883 100644
--- a/board/damu/board.h
+++ b/board/damu/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -55,7 +55,7 @@
 
 /* Motion Sensors */
 #ifndef VARIANT_KUKUI_NO_SENSORS
-#define CONFIG_ACCEL_LIS2DWL   	/* Lid accel */
+#define CONFIG_ACCEL_LIS2DWL /* Lid accel */
 #define CONFIG_ACCELGYRO_BMI160 /* Base accel */
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
@@ -71,20 +71,20 @@
 #endif /* VARIANT_KUKUI_NO_SENSORS */
 
 /* I2C ports */
-#define I2C_PORT_BC12               0
-#define I2C_PORT_TCPC0              0
-#define I2C_PORT_USB_MUX            0
-#define I2C_PORT_BATTERY            2
-#define I2C_PORT_CHARGER            board_get_charger_i2c()
-#define I2C_PORT_SENSORS            1
-#define I2C_PORT_KB_DISCRETE        1
-#define I2C_PORT_VIRTUAL_BATTERY    I2C_PORT_BATTERY
+#define I2C_PORT_BC12 0
+#define I2C_PORT_TCPC0 0
+#define I2C_PORT_USB_MUX 0
+#define I2C_PORT_BATTERY 2
+#define I2C_PORT_CHARGER board_get_charger_i2c()
+#define I2C_PORT_SENSORS 1
+#define I2C_PORT_KB_DISCRETE 1
+#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
 
 /* IT8801 I2C address */
-#define KB_DISCRETE_I2C_ADDR_FLAGS  IT8801_I2C_ADDR1
+#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1
 
 /* Enable Accel over SPI */
-#define CONFIG_SPI_ACCEL_PORT    0  /* The first SPI controller port (SPI2) */
+#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */
 
 #define CONFIG_KEYBOARD_PROTOCOL_MKBP
 #define CONFIG_MKBP_EVENT
diff --git a/board/damu/build.mk b/board/damu/build.mk
index 0b3565fd84..6a7e557a0e 100644
--- a/board/damu/build.mk
+++ b/board/damu/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/damu/ec.tasklist b/board/damu/ec.tasklist
index 19d2f34687..30e9967a0a 100644
--- a/board/damu/ec.tasklist
+++ b/board/damu/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/damu/gpio.inc b/board/damu/gpio.inc
index 9ee4035917..9db5b49238 100644
--- a/board/damu/gpio.inc
+++ b/board/damu/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/damu/led.c b/board/damu/led.c
index ee376b4b41..9d2b70795b 100644
--- a/board/damu/led.c
+++ b/board/damu/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -18,33 +18,40 @@ __override const int led_charge_lvl_1 = 5;
 __override const int led_charge_lvl_2 = 95;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
 __override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					 {LED_OFF,         3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    1 * LED_ONE_SEC },
+						  { LED_OFF,
+						    3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-	EC_LED_ID_BATTERY_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED,
+					     EC_LED_ID_BATTERY_LED };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 __override void led_set_color_battery(enum ec_led_colors color)
@@ -79,24 +86,24 @@ __override void led_set_color_power(enum ec_led_colors color)
 
 void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
 {
-	if(led_id == EC_LED_ID_BATTERY_LED) {
+	if (led_id == EC_LED_ID_BATTERY_LED) {
 		brightness_range[EC_LED_COLOR_AMBER] = 1;
 		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	} else if(led_id == EC_LED_ID_POWER_LED) {
+	} else if (led_id == EC_LED_ID_POWER_LED) {
 		brightness_range[EC_LED_COLOR_WHITE] = 1;
 	}
 }
 
 int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 {
-	if(led_id == EC_LED_ID_BATTERY_LED) {
-		if(brightness[EC_LED_COLOR_AMBER] != 0)
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		if (brightness[EC_LED_COLOR_AMBER] != 0)
 			led_set_color_battery(EC_LED_COLOR_AMBER);
-		else if(brightness[EC_LED_COLOR_WHITE] != 0)
+		else if (brightness[EC_LED_COLOR_WHITE] != 0)
 			led_set_color_battery(EC_LED_COLOR_WHITE);
 		else
 			led_set_color_battery(LED_OFF);
-	} else if(led_id == EC_LED_ID_POWER_LED) {
+	} else if (led_id == EC_LED_ID_POWER_LED) {
 		if (brightness[EC_LED_COLOR_WHITE] != 0)
 			led_set_color_power(EC_LED_COLOR_WHITE);
 		else
diff --git a/board/delbin/battery.c b/board/delbin/battery.c
index e907a3574f..6d6ae2afad 100644
--- a/board/delbin/battery.c
+++ b/board/delbin/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/delbin/board.c b/board/delbin/board.c
index 068d453e8d..1cdb42d954 100644
--- a/board/delbin/board.c
+++ b/board/delbin/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,6 +8,7 @@
 #include "common.h"
 #include "accelgyro.h"
 #include "cbi_ec_fw_config.h"
+#include "cbi_ssfc.h"
 #include "driver/accel_bma2x2.h"
 #include "driver/accelgyro_bmi260.h"
 #include "driver/bc12/pi3usb9201.h"
@@ -22,6 +23,7 @@
 #include "gpio.h"
 #include "hooks.h"
 #include "keyboard_scan.h"
+#include "keyboard_customization.h"
 #include "lid_switch.h"
 #include "power.h"
 #include "power_button.h"
@@ -41,7 +43,7 @@
 
 #include "gpio_list.h" /* Must come after other header files. */
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 /* Keyboard scan setting */
 __override struct keyboard_scan_config keyscan_config = {
@@ -60,6 +62,28 @@ __override struct keyboard_scan_config keyscan_config = {
 	},
 };
 
+__override struct key {
+	uint8_t row;
+	uint8_t col;
+} vivaldi_keys[] = {
+	{ .row = 0, .col = 2 }, /* T1 */
+	{ .row = 3, .col = 2 }, /* T2 */
+	{ .row = 2, .col = 2 }, /* T3 */
+	{ .row = 1, .col = 2 }, /* T4 */
+	{ .row = 3, .col = 4 }, /* T5 */
+	{ .row = 2, .col = 4 }, /* T6 */
+	{ .row = 1, .col = 4 }, /* T7 */
+	{ .row = 2, .col = 9 }, /* T8 */
+	{ .row = 1, .col = 9 }, /* T9 */
+	{ .row = 0, .col = 4 }, /* T10 */
+	{ .row = 0, .col = 1 }, /* T11 */
+	{ .row = 1, .col = 5 }, /* T12 */
+	{ .row = 3, .col = 5 }, /* T13 */
+	{ .row = 0, .col = 9 }, /* T14 */
+	{ .row = 0, .col = 11 }, /* T15 */
+};
+BUILD_ASSERT(ARRAY_SIZE(vivaldi_keys) == MAX_TOP_ROW_KEYS);
+
 /******************************************************************************/
 /*
  * FW_CONFIG defaults for Delbin if the CBI data is not initialized.
@@ -70,15 +94,35 @@ union volteer_cbi_fw_config fw_config_defaults = {
 
 static void board_init(void)
 {
+	key_choose();
+
+	if (get_cbi_ssfc_keyboard() == SSFC_KEYBOARD_GAMING) {
+		keyscan_config.actual_key_mask[1] = 0xfa;
+		keyscan_config.actual_key_mask[4] = 0xfe;
+		keyscan_config.actual_key_mask[7] = 0x86;
+		keyscan_config.actual_key_mask[9] = 0xff;
+		keyscan_config.actual_key_mask[11] = 0xff;
+
+		vivaldi_keys[0].row = 4;
+		vivaldi_keys[0].col = 2;
+		vivaldi_keys[4].row = 4;
+		vivaldi_keys[4].col = 4;
+		vivaldi_keys[5].row = 3;
+		vivaldi_keys[5].col = 4;
+		vivaldi_keys[6].row = 2;
+		vivaldi_keys[6].col = 4;
+		vivaldi_keys[9].row = 1;
+		vivaldi_keys[9].col = 4;
+	}
 }
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_PRE_DEFAULT);
 
 /******************************************************************************/
 /* Physical fans. These are logically separate from pwm_channels. */
 
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
@@ -114,8 +158,8 @@ const struct fan_t fans[FAN_CH_COUNT] = {
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CPU \
-	{ \
+#define THERMAL_CPU              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
@@ -142,8 +186,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_INDUCTOR \
-	{ \
+#define THERMAL_INDUCTOR         \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
@@ -270,23 +314,22 @@ static void ps8815_reset(int port)
 	}
 
 	gpio_set_level(ps8xxx_rst_odl, 0);
-	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS,
-			   PS8815_PWR_H_RST_H_DELAY_MS));
+	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS));
 	gpio_set_level(ps8xxx_rst_odl, 1);
 	msleep(PS8815_FW_INIT_DELAY_MS);
 
 	CPRINTS("[C%d] %s: patching ps8815 registers", port, __func__);
 
-	if (i2c_read8(i2c_port,
-		      PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
+	if (i2c_read8(i2c_port, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) ==
+	    EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f was %02x", val);
 
-	if (i2c_write8(i2c_port,
-		      PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) == EC_SUCCESS)
+	if (i2c_write8(i2c_port, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) ==
+	    EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f set to 0x31");
 
-	if (i2c_read8(i2c_port,
-		      PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
+	if (i2c_read8(i2c_port, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) ==
+	    EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f now %02x", val);
 }
 
@@ -294,10 +337,10 @@ void board_reset_pd_mcu(void)
 {
 	ps8815_reset(USBC_PORT_C0);
 	usb_mux_hpd_update(USBC_PORT_C0, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 	ps8815_reset(USBC_PORT_C1);
 	usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
 
 /******************************************************************************/
@@ -349,8 +392,8 @@ static const struct ec_response_keybd_config delbin_kb = {
 	.capabilities = KEYBD_CAP_SCRNLOCK_KEY | KEYBD_CAP_NUMERIC_KEYPAD,
 };
 
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	return &delbin_kb;
 }
@@ -361,19 +404,19 @@ static void ps8811_init(void)
 
 	/* Set Channel A output swing to Level1 */
 	rv = i2c_write8(I2C_PORT_USB_1_MIX,
-		PS8811_I2C_ADDR_FLAGS0 + PS8811_REG_PAGE1, 0x66, 0x10);
+			PS8811_I2C_ADDR_FLAGS0 + PS8811_REG_PAGE1, 0x66, 0x10);
 	/* Set 50 ohm termination adjuct for B channel: -9%*/
 	rv |= i2c_write8(I2C_PORT_USB_1_MIX,
-		PS8811_I2C_ADDR_FLAGS0 + PS8811_REG_PAGE1, 0x73, 0x04);
+			 PS8811_I2C_ADDR_FLAGS0 + PS8811_REG_PAGE1, 0x73, 0x04);
 	/* Set Channel B output swing to Level3 */
 	rv |= i2c_write8(I2C_PORT_USB_1_MIX,
-		PS8811_I2C_ADDR_FLAGS0 + PS8811_REG_PAGE1, 0xA4, 0x03);
+			 PS8811_I2C_ADDR_FLAGS0 + PS8811_REG_PAGE1, 0xA4, 0x03);
 	/* Set PS level for B channel */
 	rv |= i2c_write8(I2C_PORT_USB_1_MIX,
-		PS8811_I2C_ADDR_FLAGS0 + PS8811_REG_PAGE1, 0xA5, 0x84);
+			 PS8811_I2C_ADDR_FLAGS0 + PS8811_REG_PAGE1, 0xA5, 0x84);
 	/* Set DE level for B channel */
 	rv |= i2c_write8(I2C_PORT_USB_1_MIX,
-		PS8811_I2C_ADDR_FLAGS0 + PS8811_REG_PAGE1, 0xA6, 0x16);
+			 PS8811_I2C_ADDR_FLAGS0 + PS8811_REG_PAGE1, 0xA6, 0x16);
 }
 
 /* Called on AP S5 -> S0ix transition */
@@ -440,32 +483,42 @@ BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
 
 /******************************************************************************/
 /* USBC mux configuration - Tiger Lake includes internal mux */
-static const struct usb_mux usbc0_usb3_mb_retimer = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	.next_mux = NULL,
+static const struct usb_mux_chain usbc0_usb3_mb_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
+	.next = NULL,
 };
 
-static const struct usb_mux usbc1_usb3_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	.next_mux = NULL,
+static const struct usb_mux_chain usbc1_usb3_db_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
+	.next = NULL,
 };
 
-const struct usb_mux usb_muxes[] = {
+const struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc0_usb3_mb_retimer,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc0_usb3_mb_retimer,
 	},
 	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc1_usb3_db_retimer,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc1_usb3_db_retimer,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
diff --git a/board/delbin/board.h b/board/delbin/board.h
index c889d65b47..50759b74d2 100644
--- a/board/delbin/board.h
+++ b/board/delbin/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,7 +18,7 @@
 #undef CONFIG_CHIP_INIT_ROM_REGION
 
 #undef NPCX_PWM1_SEL
-#define NPCX_PWM1_SEL 0	/* GPIO C2 is not used as PWM1. */
+#define NPCX_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */
 
 /* Optional features */
 #undef CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
@@ -39,6 +39,8 @@
 /* Keyboard features */
 #define CONFIG_KEYBOARD_VIVALDI
 #define CONFIG_KEYBOARD_REFRESH_ROW3
+#define CONFIG_KEYBOARD_CUSTOMIZATION
+#define CONFIG_KEYBOARD_MULTIPLE
 
 /* Sensors */
 /* BMA253 accelerometer in base */
@@ -58,36 +60,35 @@
 
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE		BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID		LID_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
 
 /* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
 
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
 
 /*
  * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
  * cables only support up to 60W, the limitation of 45W is for the delbin
  * board.
  */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		45000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 45000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 #undef CONFIG_USB_PD_TCPC_RUNTIME_CONFIG
 #undef CONFIG_USB_MUX_RUNTIME_CONFIG
 
 /* USB Type A Features */
-#define USB_PORT_COUNT			1
+#define USB_PORT_COUNT 1
 #define CONFIG_USB_PORT_POWER_DUMB
 
 /* USBC PPC*/
 #define CONFIG_USBC_PPC_SYV682X
 
-
 /* BC 1.2 */
 
 /* Volume Button feature */
@@ -95,8 +96,8 @@
 /* Fan features */
 
 /* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 
 /* Retimer */
 #undef CONFIG_USBC_RETIMER_INTEL_BB
@@ -108,45 +109,44 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_UART2_EC_RX
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PG_EC_DSW_PWROK		GPIO_DSW_PWROK
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_LID_OPEN GPIO_EC_LID_OPEN
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_UART2_EC_RX
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PG_EC_DSW_PWROK GPIO_DSW_PWROK
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
 
 /* I2C Bus Configuration */
 #define CONFIG_I2C
-#define I2C_PORT_ACCEL		I2C_PORT_SENSOR
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_1_MIX	NPCX_I2C_PORT3_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT3_0
+#define I2C_PORT_POWER NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+
+#define I2C_PORT_BATTERY I2C_PORT_POWER
+#define I2C_PORT_CHARGER I2C_PORT_EEPROM
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 #define CONFIG_I2C_CONTROLLER
 
-
 #ifndef __ASSEMBLER__
 
 #include "gpio_signal.h"
@@ -157,11 +157,7 @@ enum battery_type {
 	BATTERY_TYPE_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_FAN = 0,
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_FAN = 0, PWM_CH_KBLIGHT, PWM_CH_COUNT };
 
 enum sensor_id {
 	LID_ACCEL = 0,
@@ -170,11 +166,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 void board_reset_pd_mcu(void);
 void motion_interrupt(enum gpio_signal signal);
diff --git a/board/delbin/build.mk b/board/delbin/build.mk
index 66ad809f59..26007095af 100644
--- a/board/delbin/build.mk
+++ b/board/delbin/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -16,3 +16,4 @@ board-y=board.o
 board-y+=battery.o
 board-y+=led.o
 board-y+=sensors.o
+board-$(CONFIG_KEYBOARD_CUSTOMIZATION)+=keyboard_customization.o
diff --git a/board/delbin/ec.tasklist b/board/delbin/ec.tasklist
index 3e20d8ae39..c29125d517 100644
--- a/board/delbin/ec.tasklist
+++ b/board/delbin/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/delbin/gpio.inc b/board/delbin/gpio.inc
index 61dae06cde..f229e50dcc 100644
--- a/board/delbin/gpio.inc
+++ b/board/delbin/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,7 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
diff --git a/board/delbin/keyboard_customization.c b/board/delbin/keyboard_customization.c
new file mode 100644
index 0000000000..56cf33ad7a
--- /dev/null
+++ b/board/delbin/keyboard_customization.c
@@ -0,0 +1,169 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "cbi_ssfc.h"
+#include "gpio.h"
+#include "keyboard_customization.h"
+#include "keyboard_8042_sharedlib.h"
+#include "keyboard_config.h"
+#include "keyboard_protocol.h"
+#include "keyboard_raw.h"
+#include "keyboard_scan.h"
+
+static uint16_t (*scancode_set2)[KEYBOARD_ROWS];
+
+static uint16_t KB2scancode_set2[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = {
+	{ 0x0000, 0x0000, 0x0014, 0xe01f, 0xe014, 0x0000, 0x0000, 0x0000 },
+	{ 0x0000, 0x0076, 0x0000, 0x000e, 0x001c, 0x003a, 0x000d, 0x0016 },
+	{ 0x006c, 0x000c, 0x0004, 0x0006, 0x0005, 0xe071, 0x0026, 0x002a },
+	{ 0x0032, 0x0034, 0x002c, 0x002e, 0x002b, 0x0029, 0x0025, 0x002d },
+	{ 0xe01f, 0x0009, 0x0083, 0x000b, 0x0003, 0x0041, 0x001e, 0x001d },
+	{ 0x0051, 0x0000, 0x005b, 0x0000, 0x0042, 0x0022, 0x003e, 0x0043 },
+	{ 0x0031, 0x0033, 0x0035, 0x0036, 0x003b, 0x001b, 0x003d, 0x003c },
+	{ 0x0000, 0x0012, 0x0061, 0x0000, 0x0000, 0x0000, 0x0000, 0x0059 },
+	{ 0x0055, 0x0052, 0x0054, 0x004e, 0x004c, 0x0024, 0x0044, 0x004d },
+	{ 0x0045, 0x0001, 0x000a, 0x002f, 0x004b, 0x0049, 0x0046, 0x001a },
+	{ 0xe011, 0x0000, 0x006a, 0x0000, 0x005d, 0x0000, 0x0011, 0x0000 },
+	{ 0xe07a, 0x005d, 0xe075, 0x006b, 0x005a, 0xe072, 0x004a, 0x0066 },
+	{ 0xe06b, 0xe074, 0xe069, 0x0067, 0xe06c, 0x0064, 0x0015, 0xe07d },
+	{ 0x0073, 0x007c, 0x007b, 0x0074, 0x0071, 0xe04a, 0x0070, 0x0021 },
+	{ 0x0023, 0xe05a, 0x0075, 0x0079, 0x007a, 0x0072, 0x007D, 0x0069 },
+};
+
+/* The standard Chrome OS keyboard matrix table in scan code set 2. */
+static uint16_t KB1scancode_set2[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = {
+	{ 0x0000, 0x0000, 0x0014, 0xe01f, 0xe014, 0xe007, 0x0000, 0x0000 },
+	{ 0xe01f, 0x0076, 0x000d, 0x000e, 0x001c, 0x001a, 0x0016, 0x0015 },
+	{ 0x0005, 0x000c, 0x0004, 0x0006, 0x0023, 0x0021, 0x0026, 0x0024 },
+	{ 0x0032, 0x0034, 0x002c, 0x002e, 0x002b, 0x002a, 0x0025, 0x002d },
+	{ 0x0009, 0x0083, 0x000b, 0x0003, 0x001b, 0x0022, 0x001e, 0x001d },
+	{ 0x0051, 0x0000, 0x005b, 0x0000, 0x0042, 0x0041, 0x003e, 0x0043 },
+	{ 0x0031, 0x0033, 0x0035, 0x0036, 0x003b, 0x003a, 0x003d, 0x003c },
+	{ 0x0000, 0x0000, 0x0061, 0x0000, 0x0000, 0x0012, 0x0000, 0x0059 },
+	{ 0x0055, 0x0052, 0x0054, 0x004e, 0x004c, 0x004a, 0x0045, 0x004d },
+	{ 0x0000, 0x0001, 0x000a, 0x002f, 0x004b, 0x0049, 0x0046, 0x0044 },
+	{ 0xe011, 0x0000, 0x006a, 0x0000, 0x005d, 0x0000, 0x0011, 0x0000 },
+#ifndef CONFIG_KEYBOARD_KEYPAD
+	{ 0x0000, 0x0066, 0x0000, 0x005d, 0x005a, 0x0029, 0xe072, 0xe075 },
+	{ 0x0000, 0x0064, 0x0000, 0x0067, 0x0000, 0x0000, 0xe074, 0xe06b },
+#else
+	{ 0x0000, 0x0066, 0xe071, 0x005d, 0x005a, 0x0029, 0xe072, 0xe075 },
+	{ 0xe06c, 0x0064, 0xe07d, 0x0067, 0xe069, 0xe07a, 0xe074, 0xe06b },
+	{ 0xe04a, 0x007c, 0x007b, 0x0074, 0x0071, 0x0073, 0x006b, 0x0070 },
+	{ 0x006c, 0x0075, 0x007d, 0x0079, 0x007a, 0x0072, 0x0069, 0xe05a },
+#endif
+};
+
+uint16_t get_scancode_set2(uint8_t row, uint8_t col)
+{
+	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS) {
+		return *(*(scancode_set2 + col) + row);
+	}
+	return 0;
+}
+
+void set_scancode_set2(uint8_t row, uint8_t col, uint16_t val)
+{
+	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS) {
+		*(*(scancode_set2 + col) + row) = val;
+	}
+}
+
+void board_keyboard_drive_col(int col)
+{
+	/* Drive all lines to high */
+	if (col == KEYBOARD_COLUMN_NONE)
+		gpio_set_level(GPIO_KBD_KSO2, 0);
+
+	/* Set KBSOUT to zero to detect key-press */
+	else if (col == KEYBOARD_COLUMN_ALL)
+		gpio_set_level(GPIO_KBD_KSO2, 1);
+
+	/* Drive one line for detection */
+	else {
+		if (col == 2)
+			gpio_set_level(GPIO_KBD_KSO2, 1);
+		else
+			gpio_set_level(GPIO_KBD_KSO2, 0);
+	}
+}
+
+struct keyboard_type key_typ = {
+	.col_esc = KEYBOARD_COL_ESC,
+	.row_esc = KEYBOARD_ROW_ESC,
+	.col_down = KEYBOARD_COL_DOWN,
+	.row_down = KEYBOARD_ROW_DOWN,
+	.col_left_shift = KEYBOARD_COL_LEFT_SHIFT,
+	.row_left_shift = KEYBOARD_ROW_LEFT_SHIFT,
+	.col_refresh = KEYBOARD_COL_REFRESH,
+	.row_refresh = KEYBOARD_ROW_REFRESH,
+	.col_right_alt = KEYBOARD_COL_RIGHT_ALT,
+	.row_right_alt = KEYBOARD_ROW_RIGHT_ALT,
+	.col_left_alt = KEYBOARD_COL_LEFT_ALT,
+	.row_left_alt = KEYBOARD_ROW_LEFT_ALT,
+	.col_key_r = KEYBOARD_COL_KEY_R,
+	.row_key_r = KEYBOARD_ROW_KEY_R,
+	.col_key_h = KEYBOARD_COL_KEY_H,
+	.row_key_h = KEYBOARD_ROW_KEY_H,
+};
+
+int keyboard_choose(void)
+{
+	if (get_cbi_ssfc_keyboard() == SSFC_KEYBOARD_GAMING)
+		return 1;
+
+	return 0;
+}
+
+void key_choose(void)
+{
+	if (keyboard_choose() == 1) {
+		key_typ.col_esc = KEYBOARD2_COL_ESC;
+		key_typ.row_esc = KEYBOARD2_ROW_ESC;
+		key_typ.col_down = KEYBOARD2_COL_DOWN;
+		key_typ.row_down = KEYBOARD2_ROW_DOWN;
+		key_typ.col_left_shift = KEYBOARD2_COL_LEFT_SHIFT;
+		key_typ.row_left_shift = KEYBOARD2_ROW_LEFT_SHIFT;
+		key_typ.col_refresh = KEYBOARD2_COL_REFRESH;
+		key_typ.row_refresh = KEYBOARD2_ROW_REFRESH;
+		key_typ.col_right_alt = KEYBOARD2_COL_RIGHT_ALT;
+		key_typ.row_right_alt = KEYBOARD2_ROW_RIGHT_ALT;
+		key_typ.col_left_alt = KEYBOARD2_COL_LEFT_ALT;
+		key_typ.row_left_alt = KEYBOARD2_ROW_LEFT_ALT;
+		key_typ.col_key_r = KEYBOARD2_COL_KEY_R;
+		key_typ.row_key_r = KEYBOARD2_ROW_KEY_R;
+		key_typ.col_key_h = KEYBOARD2_COL_KEY_H;
+		key_typ.row_key_h = KEYBOARD2_ROW_KEY_H;
+
+		boot_key_list[0].col = KEYBOARD2_COL_ESC;
+		boot_key_list[0].row = KEYBOARD2_ROW_ESC;
+		boot_key_list[1].col = KEYBOARD2_COL_DOWN;
+		boot_key_list[1].row = KEYBOARD2_ROW_DOWN;
+		boot_key_list[2].col = KEYBOARD2_COL_LEFT_SHIFT;
+		boot_key_list[2].row = KEYBOARD2_ROW_LEFT_SHIFT;
+
+		scancode_set2 = KB2scancode_set2;
+	} else {
+		key_typ.col_esc = KEYBOARD_COL_ESC;
+		key_typ.row_esc = KEYBOARD_ROW_ESC;
+		key_typ.col_down = KEYBOARD_COL_DOWN;
+		key_typ.row_down = KEYBOARD_ROW_DOWN;
+		key_typ.col_left_shift = KEYBOARD_COL_LEFT_SHIFT;
+		key_typ.row_left_shift = KEYBOARD_ROW_LEFT_SHIFT;
+		key_typ.col_refresh = KEYBOARD_COL_REFRESH;
+		key_typ.row_refresh = KEYBOARD_ROW_REFRESH;
+		key_typ.col_right_alt = KEYBOARD_COL_RIGHT_ALT;
+		key_typ.row_right_alt = KEYBOARD_ROW_RIGHT_ALT;
+		key_typ.col_left_alt = KEYBOARD_COL_LEFT_ALT;
+		key_typ.row_left_alt = KEYBOARD_ROW_LEFT_ALT;
+		key_typ.col_key_r = KEYBOARD_COL_KEY_R;
+		key_typ.row_key_r = KEYBOARD_ROW_KEY_R;
+		key_typ.col_key_h = KEYBOARD_COL_KEY_H;
+		key_typ.row_key_h = KEYBOARD_ROW_KEY_H;
+
+		scancode_set2 = KB1scancode_set2;
+	}
+}
diff --git a/board/delbin/keyboard_customization.h b/board/delbin/keyboard_customization.h
new file mode 100644
index 0000000000..bfe5c3b584
--- /dev/null
+++ b/board/delbin/keyboard_customization.h
@@ -0,0 +1,130 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Keyboard configuration */
+
+#ifndef __KEYBOARD_CUSTOMIZATION_H
+#define __KEYBOARD_CUSTOMIZATION_H
+
+/*
+ * KEYBOARD_COLS_MAX has the build time column size. It's used to allocate
+ * exact spaces for arrays. Actual keyboard scanning is done using
+ * keyboard_cols, which holds a runtime column size.
+ */
+#define KEYBOARD_COLS_MAX 16
+#define KEYBOARD_ROWS 8
+
+/*
+ * WARNING: Do not directly modify it. You should call keyboard_raw_set_cols,
+ * instead. It checks whether you're eligible or not.
+ */
+extern uint8_t keyboard_cols;
+
+#define KEYBOARD_ROW_TO_MASK(r) (1 << (r))
+
+#define KEYBOARD_COL_DOWN 11
+#define KEYBOARD_ROW_DOWN 6
+#define KEYBOARD_MASK_DOWN KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_DOWN)
+#define KEYBOARD_COL_ESC 1
+#define KEYBOARD_ROW_ESC 1
+#define KEYBOARD_MASK_ESC KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_ESC)
+#define KEYBOARD_COL_KEY_H 6
+#define KEYBOARD_ROW_KEY_H 1
+#define KEYBOARD_MASK_KEY_H KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_H)
+#define KEYBOARD_COL_KEY_R 3
+#define KEYBOARD_ROW_KEY_R 7
+#define KEYBOARD_MASK_KEY_R KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_R)
+#define KEYBOARD_COL_LEFT_ALT 10
+#define KEYBOARD_ROW_LEFT_ALT 6
+#define KEYBOARD_MASK_LEFT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_ALT)
+#define KEYBOARD_COL_REFRESH 2
+#ifdef CONFIG_KEYBOARD_REFRESH_ROW3
+#define KEYBOARD_ROW_REFRESH 3
+#else
+#define KEYBOARD_ROW_REFRESH 2
+#endif
+#define KEYBOARD_MASK_REFRESH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_REFRESH)
+#define KEYBOARD_COL_RIGHT_ALT 10
+#define KEYBOARD_ROW_RIGHT_ALT 0
+#define KEYBOARD_MASK_RIGHT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_ALT)
+#define KEYBOARD_DEFAULT_COL_VOL_UP 4
+#define KEYBOARD_DEFAULT_ROW_VOL_UP 0
+#define KEYBOARD_COL_LEFT_CTRL 0
+#define KEYBOARD_ROW_LEFT_CTRL 2
+#define KEYBOARD_MASK_LEFT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_CTRL)
+#define KEYBOARD_COL_RIGHT_CTRL 0
+#define KEYBOARD_ROW_RIGHT_CTRL 4
+#define KEYBOARD_MASK_RIGHT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_CTRL)
+#define KEYBOARD_COL_SEARCH 1
+#define KEYBOARD_ROW_SEARCH 0
+#define KEYBOARD_MASK_SEARCH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_SEARCH)
+#define KEYBOARD_COL_KEY_0 8
+#define KEYBOARD_ROW_KEY_0 6
+#define KEYBOARD_MASK_KEY_0 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_0)
+#define KEYBOARD_COL_KEY_1 1
+#define KEYBOARD_ROW_KEY_1 6
+#define KEYBOARD_MASK_KEY_1 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_1)
+#define KEYBOARD_COL_KEY_2 4
+#define KEYBOARD_ROW_KEY_2 6
+#define KEYBOARD_MASK_KEY_2 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_2)
+#define KEYBOARD_COL_LEFT_SHIFT 7
+#define KEYBOARD_ROW_LEFT_SHIFT 5
+#define KEYBOARD_MASK_LEFT_SHIFT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_SHIFT)
+#ifdef CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2
+#define KEYBOARD_MASK_PWRBTN KEYBOARD_ROW_TO_MASK(2)
+#elif defined(CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI3)
+#define KEYBOARD_MASK_PWRBTN KEYBOARD_ROW_TO_MASK(3)
+#endif
+
+/* Columns and masks for keys we particularly care about */
+#define KEYBOARD2_COL_DOWN 11
+#define KEYBOARD2_ROW_DOWN 5
+#define KEYBOARD2_MASK_DOWN KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_DOWN)
+#define KEYBOARD2_COL_ESC 1
+#define KEYBOARD2_ROW_ESC 1
+#define KEYBOARD2_MASK_ESC KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_ESC)
+#define KEYBOARD2_COL_KEY_H 6
+#define KEYBOARD2_ROW_KEY_H 1
+#define KEYBOARD2_MASK_KEY_H KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_KEY_H)
+#define KEYBOARD2_COL_KEY_R 3
+#define KEYBOARD2_ROW_KEY_R 7
+#define KEYBOARD2_MASK_KEY_R KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_KEY_R)
+#define KEYBOARD2_COL_LEFT_ALT 10
+#define KEYBOARD2_ROW_LEFT_ALT 6
+#define KEYBOARD2_MASK_LEFT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_LEFT_ALT)
+#define KEYBOARD2_COL_REFRESH 2
+#define KEYBOARD2_ROW_REFRESH 3
+#define KEYBOARD2_MASK_REFRESH KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_REFRESH)
+#define KEYBOARD2_COL_RIGHT_ALT 10
+#define KEYBOARD2_ROW_RIGHT_ALT 0
+#define KEYBOARD2_MASK_RIGHT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_RIGHT_ALT)
+#define KEYBOARD2_DEFAULT_COL_VOL_UP 4
+#define KEYBOARD2_DEFAULT_ROW_VOL_UP 1
+#define KEYBOARD2_COL_LEFT_CTRL 0
+#define KEYBOARD2_ROW_LEFT_CTRL 2
+#define KEYBOARD2_MASK_LEFT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_LEFT_CTRL)
+#define KEYBOARD2_COL_RIGHT_CTRL 0
+#define KEYBOARD2_ROW_RIGHT_CTRL 4
+#define KEYBOARD2_MASK_RIGHT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_RIGHT_CTRL)
+#define KEYBOARD2_COL_SEARCH 4
+#define KEYBOARD2_ROW_SEARCH 0
+#define KEYBOARD2_MASK_SEARCH KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_SEARCH)
+#define KEYBOARD2_COL_KEY_0 9
+#define KEYBOARD2_ROW_KEY_0 0
+#define KEYBOARD2_MASK_KEY_0 KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_KEY_0)
+#define KEYBOARD2_COL_KEY_1 1
+#define KEYBOARD2_ROW_KEY_1 7
+#define KEYBOARD2_MASK_KEY_1 KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_KEY_1)
+#define KEYBOARD2_COL_KEY_2 4
+#define KEYBOARD2_ROW_KEY_2 6
+#define KEYBOARD2_MASK_KEY_2 KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_KEY_2)
+#define KEYBOARD2_COL_LEFT_SHIFT 7
+#define KEYBOARD2_ROW_LEFT_SHIFT 1
+#define KEYBOARD2_MASK_LEFT_SHIFT KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_LEFT_SHIFT)
+
+int keyboard_choose(void);
+void key_choose(void);
+
+#endif /* __KEYBOARD_CUSTOMIZATION_H */
diff --git a/board/delbin/led.c b/board/delbin/led.c
index d7c1df491f..27eb98a75e 100644
--- a/board/delbin/led.c
+++ b/board/delbin/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,29 +17,37 @@ __override const int led_charge_lvl_1 = 5;
 __override const int led_charge_lvl_2 = 95;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
 __override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	     3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	     3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    1 * LED_ONE_SEC },
+						  { LED_OFF,
+						    3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
 const enum ec_led_id supported_led_ids[] = {
 	EC_LED_ID_BATTERY_LED,
diff --git a/board/delbin/sensors.c b/board/delbin/sensors.c
index a3d5015e2b..77b5757e28 100644
--- a/board/delbin/sensors.c
+++ b/board/delbin/sensors.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -34,22 +34,18 @@ static struct bmi_drv_data_t g_bmi260_data;
 static struct icm_drv_data_t g_icm426xx_data;
 
 /* Rotation matrix for the lid accelerometer */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
 
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+				       { 0, FLOAT_TO_FP(1), 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
 
 const mat33_fp_t base_standard_ref_icm = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)},
+	{ 0, FLOAT_TO_FP(-1), 0 },
+	{ FLOAT_TO_FP(1), 0, 0 },
+	{ 0, 0, FLOAT_TO_FP(1) },
 };
 
 struct motion_sensor_t icm426xx_base_accel = {
diff --git a/board/dewatt/battery.c b/board/dewatt/battery.c
index 40d5f930e3..9b3e15cfcf 100644
--- a/board/dewatt/battery.c
+++ b/board/dewatt/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/dewatt/board.c b/board/dewatt/board.c
index 8d37cd076d..4667979e15 100644
--- a/board/dewatt/board.c
+++ b/board/dewatt/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,6 +9,7 @@
 #include "base_fw_config.h"
 #include "battery.h"
 #include "board_fw_config.h"
+#include "builtin/assert.h"
 #include "button.h"
 #include "charger.h"
 #include "common.h"
@@ -17,7 +18,7 @@
 #include "driver/accelgyro_bmi260.h"
 #include "driver/accel_bma422.h"
 #include "driver/retimer/ps8811.h"
-#include "driver/retimer/ps8818.h"
+#include "driver/retimer/ps8818_public.h"
 #include "driver/temp_sensor/sb_tsi.h"
 #include "driver/temp_sensor/pct2075.h"
 #include "extpower.h"
@@ -47,17 +48,13 @@ static struct bmi_drv_data_t g_bmi_data;
 static struct accelgyro_saved_data_t g_bma422_data;
 
 /* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				       { 0, FLOAT_TO_FP(1), 0 },
+				       { 0, 0, FLOAT_TO_FP(-1) } };
 
-const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
+const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				      { 0, FLOAT_TO_FP(-1), 0 },
+				      { 0, 0, FLOAT_TO_FP(1) } };
 
 /*
  * We have total 30 pins for keyboard connecter {-1, -1} mean
@@ -65,16 +62,15 @@ const mat33_fp_t lid_standard_ref = {
  * that we don't have pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-	{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-	{0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3},
-	{-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0},
-	{1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4},
-	{2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0},
-	{-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1},
-	{-1, -1},
+	{ -1, -1 }, { 0, 5 },	{ 1, 1 }, { 1, 0 },   { 0, 6 },	  { 0, 7 },
+	{ -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 },   { -1, -1 }, { 1, 6 },
+	{ 1, 7 },   { 3, 1 },	{ 2, 0 }, { 1, 5 },   { 2, 6 },	  { 2, 7 },
+	{ 2, 1 },   { 2, 4 },	{ 2, 5 }, { 1, 2 },   { 2, 3 },	  { 2, 2 },
+	{ 3, 0 },   { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 },	  { -1, -1 },
+	{ -1, -1 },
 };
 const int keyboard_factory_scan_pins_used =
-		ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 
 struct motion_sensor_t motion_sensors[] = {
 	[BASE_ACCEL] = {
@@ -178,51 +174,46 @@ board_a1_ps8811_retimer_init(const struct usb_mux *me)
 }
 
 __override int board_c1_ps8818_mux_set(const struct usb_mux *me,
-				    mux_state_t mux_state)
+				       mux_state_t mux_state)
 {
 	int rv = EC_SUCCESS;
 
 	/* USB specific config */
 	if (mux_state & USB_PD_MUX_USB_ENABLED) {
 		/* Boost the USB gain */
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX1EQ_10G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_19DB);
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_APTX1EQ_10G_LEVEL,
+					      PS8818_EQ_LEVEL_UP_MASK,
+					      PS8818_EQ_LEVEL_UP_19DB);
 		if (rv)
 			return rv;
 
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX2EQ_10G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_19DB);
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_APTX2EQ_10G_LEVEL,
+					      PS8818_EQ_LEVEL_UP_MASK,
+					      PS8818_EQ_LEVEL_UP_19DB);
 		if (rv)
 			return rv;
 
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX1EQ_5G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_19DB);
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_APTX1EQ_5G_LEVEL,
+					      PS8818_EQ_LEVEL_UP_MASK,
+					      PS8818_EQ_LEVEL_UP_19DB);
 		if (rv)
 			return rv;
 
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX2EQ_5G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_19DB);
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_APTX2EQ_5G_LEVEL,
+					      PS8818_EQ_LEVEL_UP_MASK,
+					      PS8818_EQ_LEVEL_UP_19DB);
 		if (rv)
 			return rv;
 
 		/* Set the RX input termination */
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_RX_PHY,
-					PS8818_RX_INPUT_TERM_MASK,
-					PS8818_RX_INPUT_TERM_112_OHM);
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_RX_PHY,
+					      PS8818_RX_INPUT_TERM_MASK,
+					      PS8818_RX_INPUT_TERM_112_OHM);
 		if (rv)
 			return rv;
 	}
@@ -230,11 +221,10 @@ __override int board_c1_ps8818_mux_set(const struct usb_mux *me,
 	/* DP specific config */
 	if (mux_state & USB_PD_MUX_DP_ENABLED) {
 		/* Boost the DP gain */
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_DPEQ_LEVEL,
-					PS8818_DPEQ_LEVEL_UP_MASK,
-					PS8818_DPEQ_LEVEL_UP_19DB);
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_DPEQ_LEVEL,
+					      PS8818_DPEQ_LEVEL_UP_MASK,
+					      PS8818_DPEQ_LEVEL_UP_19DB);
 		if (rv)
 			return rv;
 
@@ -302,8 +292,7 @@ static void board_chipset_startup(void)
 	if (get_board_version() > 1)
 		pct2075_init();
 }
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup,
-	     HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
 
 int board_get_soc_temp_k(int idx, int *temp_k)
 {
@@ -437,8 +426,8 @@ static const struct ec_response_keybd_config main_kb = {
 	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
 };
 
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	return &main_kb;
 }
diff --git a/board/dewatt/board.h b/board/dewatt/board.h
index 5d34f8324a..58990c97d3 100644
--- a/board/dewatt/board.h
+++ b/board/dewatt/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,7 +26,7 @@
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 #define CONFIG_ACCEL_BMA4XX
 
-#define I2C_PORT_ACCEL      I2C_PORT_SENSOR
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
 
 /* EC console commands */
 #define CONFIG_CMD_ACCELS
@@ -37,11 +37,11 @@
 #define CONFIG_USB_MUX_ANX7451
 #define CONFIG_USBC_RETIMER_ANX7451
 
-#define PD_OPERATING_POWER_MW   15000
-#define PD_MAX_CURRENT_MA       3250
-#define PD_MAX_VOLTAGE_MV       20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_CURRENT_MA 3250
+#define PD_MAX_VOLTAGE_MV 20000
 /* Max Power = 65 W */
-#define PD_MAX_POWER_MW         ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
+#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
 
 /* USB Type A Features */
 
diff --git a/board/dewatt/board_fw_config.c b/board/dewatt/board_fw_config.c
index e6dbcadb92..7128a153ca 100644
--- a/board/dewatt/board_fw_config.c
+++ b/board/dewatt/board_fw_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,7 +14,8 @@ bool board_is_convertible(void)
 bool board_has_kblight(void)
 {
 	return (get_fw_config_field(FW_CONFIG_KBLIGHT_OFFSET,
-			FW_CONFIG_KBLIGHT_WIDTH) == FW_CONFIG_KBLIGHT_YES);
+				    FW_CONFIG_KBLIGHT_WIDTH) ==
+		FW_CONFIG_KBLIGHT_YES);
 }
 
 enum board_usb_c1_mux board_get_usb_c1_mux(void)
diff --git a/board/dewatt/board_fw_config.h b/board/dewatt/board_fw_config.h
index 1de417d77a..4477aca6fd 100644
--- a/board/dewatt/board_fw_config.h
+++ b/board/dewatt/board_fw_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,26 +13,25 @@
 /*
  * USB Daughter Board (2 bits)
  */
-#define FW_CONFIG_USB_DB_OFFSET			0
-#define FW_CONFIG_USB_DB_WIDTH			2
-#define FW_CONFIG_USB_DB_A1_PS8811_C1_PS8818	0
-#define FW_CONFIG_USB_DB_A1_ANX7491_C1_ANX7451	1
+#define FW_CONFIG_USB_DB_OFFSET 0
+#define FW_CONFIG_USB_DB_WIDTH 2
+#define FW_CONFIG_USB_DB_A1_PS8811_C1_PS8818 0
+#define FW_CONFIG_USB_DB_A1_ANX7491_C1_ANX7451 1
 
 /*
  * Form Factor (1 bits)
  */
-#define FW_CONFIG_FORM_FACTOR_OFFSET		2
-#define FW_CONFIG_FORM_FACTOR_WIDTH		1
-#define FW_CONFIG_FORM_FACTOR_CLAMSHELL		0
-#define FW_CONFIG_FORM_FACTOR_CONVERTIBLE	1
+#define FW_CONFIG_FORM_FACTOR_OFFSET 2
+#define FW_CONFIG_FORM_FACTOR_WIDTH 1
+#define FW_CONFIG_FORM_FACTOR_CLAMSHELL 0
+#define FW_CONFIG_FORM_FACTOR_CONVERTIBLE 1
 
 /*
  * Keyboard Backlight (1 bit)
  */
-#define FW_CONFIG_KBLIGHT_OFFSET		3
-#define FW_CONFIG_KBLIGHT_WIDTH			1
-#define FW_CONFIG_KBLIGHT_NO			0
-#define FW_CONFIG_KBLIGHT_YES			1
-
+#define FW_CONFIG_KBLIGHT_OFFSET 3
+#define FW_CONFIG_KBLIGHT_WIDTH 1
+#define FW_CONFIG_KBLIGHT_NO 0
+#define FW_CONFIG_KBLIGHT_YES 1
 
 #endif /* _GUYBRUSH_CBI_FW_CONFIG__H_ */
diff --git a/board/dewatt/build.mk b/board/dewatt/build.mk
index 8f2b78ddc8..8a1ce35e1e 100644
--- a/board/dewatt/build.mk
+++ b/board/dewatt/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/dewatt/ec.tasklist b/board/dewatt/ec.tasklist
index 94ff657db3..14ecddebc9 100644
--- a/board/dewatt/ec.tasklist
+++ b/board/dewatt/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/dewatt/gpio.inc b/board/dewatt/gpio.inc
index 1bab89ed63..9798239af5 100644
--- a/board/dewatt/gpio.inc
+++ b/board/dewatt/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/dewatt/led.c b/board/dewatt/led.c
index 7cbb9133bf..9453bd8e6e 100644
--- a/board/dewatt/led.c
+++ b/board/dewatt/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -14,10 +14,10 @@
 #include "pwm.h"
 
 /* Note PWM LEDs are active low */
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
-#define CPRINTS(format, args...) cprints(CC_PWM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_PWM, format, ##args)
 
 __override const int led_charge_lvl_1 = 5;
 
@@ -45,20 +45,29 @@ static void led_pwm_ch_init(void)
 DECLARE_HOOK(HOOK_INIT, led_pwm_ch_init, HOOK_PRIO_INIT_PWM - 1);
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_S5]     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,	     3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC},
-					{EC_LED_COLOR_BLUE,  2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_S5] = { { EC_LED_COLOR_BLUE,
+					       LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_BLUE,
+					   2 * LED_ONE_SEC } },
+	};
 
 const enum ec_led_id supported_led_ids[] = {
 	EC_LED_ID_BATTERY_LED,
diff --git a/board/dewatt/thermal.c b/board/dewatt/thermal.c
index 0d0d80095a..bd63fda984 100644
--- a/board/dewatt/thermal.c
+++ b/board/dewatt/thermal.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,7 +12,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_THERMAL, outstr)
-#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
 
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
@@ -93,14 +93,14 @@ struct fan_step {
 };
 
 static const struct fan_step fan_table[] = {
-	{.on =  0, .off =  1, .rpm = 0},
-	{.on =  6, .off =  2, .rpm = 3000},
-	{.on = 28, .off = 15, .rpm = 3300},
-	{.on = 34, .off = 26, .rpm = 3700},
-	{.on = 39, .off = 32, .rpm = 4000},
-	{.on = 45, .off = 38, .rpm = 4300},
-	{.on = 51, .off = 43, .rpm = 4700},
-	{.on = 74, .off = 62, .rpm = 5400},
+	{ .on = 0, .off = 1, .rpm = 0 },
+	{ .on = 6, .off = 2, .rpm = 3000 },
+	{ .on = 28, .off = 15, .rpm = 3300 },
+	{ .on = 34, .off = 26, .rpm = 3700 },
+	{ .on = 39, .off = 32, .rpm = 4000 },
+	{ .on = 45, .off = 38, .rpm = 4300 },
+	{ .on = 51, .off = 43, .rpm = 4700 },
+	{ .on = 74, .off = 62, .rpm = 5400 },
 };
 #define NUM_FAN_LEVELS ARRAY_SIZE(fan_table)
 
@@ -137,10 +137,8 @@ int fan_percent_to_rpm(int fan, int pct)
 
 	previous_pct = pct;
 
-	if (fan_table[current_level].rpm !=
-		fan_get_rpm_target(FAN_CH(fan)))
-		CPRINTS("Setting fan RPM to %d",
-			fan_table[current_level].rpm);
+	if (fan_table[current_level].rpm != fan_get_rpm_target(FAN_CH(fan)))
+		CPRINTS("Setting fan RPM to %d", fan_table[current_level].rpm);
 
 	return fan_table[current_level].rpm;
 }
diff --git a/board/dingdong/board.c b/board/dingdong/board.c
index ddaf6bb928..7f17668313 100644
--- a/board/dingdong/board.c
+++ b/board/dingdong/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -96,7 +96,7 @@ void board_config_pre_init(void)
 	/* enable SYSCFG clock */
 	STM32_RCC_APB2ENR |= BIT(0);
 	/* Remap USART DMA to match the USART driver */
-	STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10);/* Remap USART1 RX/TX DMA */
+	STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10); /* Remap USART1 RX/TX DMA */
 }
 
 /* Initialize board. */
@@ -115,12 +115,12 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* USB PD CC lines sensing. Converted to mV (3300mV/4096). */
-	[ADC_CH_CC1_PD] = {"USB_C_CC1_PD", 3300, 4096, 0, STM32_AIN(1)},
+	[ADC_CH_CC1_PD] = { "USB_C_CC1_PD", 3300, 4096, 0, STM32_AIN(1) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-const void * const usb_strings[] = {
+const void *const usb_strings[] = {
 	[USB_STR_DESC] = usb_string_desc,
-	[USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."),
+	[USB_STR_VENDOR] = USB_STRING_DESC("Google LLC"),
 	[USB_STR_PRODUCT] = USB_STRING_DESC("Dingdong"),
 	[USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32),
 	[USB_STR_BB_URL] = USB_STRING_DESC(USB_GOOGLE_TYPEC_URL),
diff --git a/board/dingdong/board.h b/board/dingdong/board.h
index 64947960ba..c0372c9322 100644
--- a/board/dingdong/board.h
+++ b/board/dingdong/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -39,7 +39,7 @@
 #define CONFIG_USB_PD_IDENTITY_SW_VERS 1
 #define CONFIG_USB_PD_VBUS_DETECT_NONE
 #define CONFIG_USB_PD_LOGGING
-#undef  CONFIG_EVENT_LOG_SIZE
+#undef CONFIG_EVENT_LOG_SIZE
 #define CONFIG_EVENT_LOG_SIZE 256
 #define CONFIG_USB_PD_PORT_MAX_COUNT 1
 #define CONFIG_USB_PD_TCPC
@@ -63,7 +63,7 @@
 
 /* Timer selection */
 #define TIM_CLOCK32 2
-#define TIM_ADC     3
+#define TIM_ADC 3
 
 #include "gpio_signal.h"
 
@@ -86,14 +86,14 @@ enum usb_strings {
 };
 
 /* we are never a source : don't care about power supply */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  0 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 0 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 0 /* us */
 
 /* Define typical operating power and max power */
 #define PD_OPERATING_POWER_MW 1000
-#define PD_MAX_POWER_MW       1500
-#define PD_MAX_CURRENT_MA     300
-#define PD_MAX_VOLTAGE_MV     5000
+#define PD_MAX_POWER_MW 1500
+#define PD_MAX_CURRENT_MA 300
+#define PD_MAX_VOLTAGE_MV 5000
 
 #endif /* !__ASSEMBLER__ */
 
@@ -101,10 +101,10 @@ enum usb_strings {
 #define USB_DEV_CLASS USB_CLASS_BILLBOARD
 
 /* USB interface indexes (use define rather than enum to expand them) */
-#define USB_IFACE_COUNT     0
+#define USB_IFACE_COUNT 0
 
 /* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL   0
-#define USB_EP_COUNT     1
+#define USB_EP_CONTROL 0
+#define USB_EP_COUNT 1
 
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/dingdong/build.mk b/board/dingdong/build.mk
index 71cea3f845..b6fbbe7a9e 100644
--- a/board/dingdong/build.mk
+++ b/board/dingdong/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
+# Copyright 2014 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/dingdong/ec.tasklist b/board/dingdong/ec.tasklist
index 41fc047d6a..5a82344122 100644
--- a/board/dingdong/ec.tasklist
+++ b/board/dingdong/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/dingdong/gpio.inc b/board/dingdong/gpio.inc
index ec1e9a7fa9..d8ea0dfc8f 100644
--- a/board/dingdong/gpio.inc
+++ b/board/dingdong/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
+ * Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/dingdong/usb_pd_config.h b/board/dingdong/usb_pd_config.h
index 2f01c275a8..5a7dfd12a6 100644
--- a/board/dingdong/usb_pd_config.h
+++ b/board/dingdong/usb_pd_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -49,7 +49,7 @@ static inline void spi_enable_clock(int port)
 
 #define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
 #define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
-#define TIM_CCR_CS  1
+#define TIM_CCR_CS 1
 #define EXTI_COMP_MASK(p) BIT(21)
 #define IRQ_COMP STM32_IRQ_COMP
 /* triggers packet detection on comparator falling edge */
@@ -88,9 +88,8 @@ static inline void pd_tx_enable(int port, int polarity)
 static inline void pd_tx_disable(int port, int polarity)
 {
 	/* output low on SPI TX (PB4) to disable the FET */
-	STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B)
-				   & ~(3 << (2*4)))
-				   |  (1 << (2*4));
+	STM32_GPIO_MODER(GPIO_B) =
+		(STM32_GPIO_MODER(GPIO_B) & ~(3 << (2 * 4))) | (1 << (2 * 4));
 	/* put the low level reference in Hi-Z */
 	gpio_set_level(GPIO_PD_CC1_TX_EN, 0);
 }
@@ -101,8 +100,8 @@ static inline void pd_select_polarity(int port, int polarity)
 	 * use the right comparator : CC1 -> PA1 (COMP1 INP)
 	 * use VrefInt / 2 as INM (about 600mV)
 	 */
-	STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK)
-		| STM32_COMP_CMP1EN | STM32_COMP_CMP1INSEL_VREF12;
+	STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK) |
+			 STM32_COMP_CMP1EN | STM32_COMP_CMP1INSEL_VREF12;
 }
 
 /* Initialize pins used for TX and put them in Hi-Z */
@@ -111,7 +110,9 @@ static inline void pd_tx_init(void)
 	gpio_config_module(MODULE_USB_PD, 1);
 }
 
-static inline void pd_set_host_mode(int port, int enable) {}
+static inline void pd_set_host_mode(int port, int enable)
+{
+}
 
 static inline void pd_config_init(int port, uint8_t power_role)
 {
diff --git a/board/dingdong/usb_pd_pdo.c b/board/dingdong/usb_pd_pdo.c
index 990c2de5ab..7b4ed3e2d8 100644
--- a/board/dingdong/usb_pd_pdo.c
+++ b/board/dingdong/usb_pd_pdo.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,6 +15,6 @@ const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
 
 /* Fake PDOs : we just want our pre-defined voltages */
 const uint32_t pd_snk_pdo[] = {
-		PDO_FIXED(5000,   500, PDO_FIXED_FLAGS),
+	PDO_FIXED(5000, 500, PDO_FIXED_FLAGS),
 };
 const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
diff --git a/board/dingdong/usb_pd_pdo.h b/board/dingdong/usb_pd_pdo.h
index 66bb713ee8..e1b628c3a8 100644
--- a/board/dingdong/usb_pd_pdo.h
+++ b/board/dingdong/usb_pd_pdo.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/dingdong/usb_pd_policy.c b/board/dingdong/usb_pd_policy.c
index 9bcc7f806f..493897c6da 100644
--- a/board/dingdong/usb_pd_policy.c
+++ b/board/dingdong/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,8 +20,8 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 /* Holds valid object position (opos) for entered mode */
 static int alt_mode[PD_AMODE_COUNT];
@@ -69,28 +69,22 @@ int pd_check_power_swap(int port)
 	return 0;
 }
 
-int pd_check_data_swap(int port,
-		       enum pd_data_role data_role)
+int pd_check_data_swap(int port, enum pd_data_role data_role)
 {
 	/* Always refuse data swap */
 	return 0;
 }
 
-void pd_execute_data_swap(int port,
-			  enum pd_data_role data_role)
+void pd_execute_data_swap(int port, enum pd_data_role data_role)
 {
 	/* Do nothing */
 }
 
-void pd_check_pr_role(int port,
-		      enum pd_power_role pr_role,
-		      int flags)
+void pd_check_pr_role(int port, enum pd_power_role pr_role, int flags)
 {
 }
 
-void pd_check_dr_role(int port,
-		      enum pd_data_role dr_role,
-		      int flags)
+void pd_check_dr_role(int port, enum pd_data_role dr_role, int flags)
 {
 }
 /* ----------------- Vendor Defined Messages ------------------ */
@@ -103,8 +97,8 @@ const uint32_t vdo_idh = VDO_IDH(0, /* data caps as USB host */
 const uint32_t vdo_product = VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV);
 
 const uint32_t vdo_ama = VDO_AMA(CONFIG_USB_PD_IDENTITY_HW_VERS,
-				 CONFIG_USB_PD_IDENTITY_SW_VERS,
-				 0, 0, 0, 0, /* SS[TR][12] */
+				 CONFIG_USB_PD_IDENTITY_SW_VERS, 0, 0, 0,
+				 0, /* SS[TR][12] */
 				 0, /* Vconn power */
 				 0, /* Vconn power required */
 				 1, /* Vbus power required */
@@ -130,18 +124,16 @@ static int svdm_response_svids(int port, uint32_t *payload)
 #define OPOS_DP 1
 #define OPOS_GFU 1
 
-const uint32_t vdo_dp_modes[1] =  {
-	VDO_MODE_DP(0,             /* UFP pin cfg supported : none */
+const uint32_t vdo_dp_modes[1] = {
+	VDO_MODE_DP(0, /* UFP pin cfg supported : none */
 		    MODE_DP_PIN_E, /* DFP pin cfg supported */
-		    1,		   /* no usb2.0 signalling in AMode */
-		    CABLE_PLUG,    /* its a plug */
-		    MODE_DP_V13,   /* DPv1.3 Support, no Gen2 */
-		    MODE_DP_SNK)   /* Its a sink only */
+		    1, /* no usb2.0 signalling in AMode */
+		    CABLE_PLUG, /* its a plug */
+		    MODE_DP_V13, /* DPv1.3 Support, no Gen2 */
+		    MODE_DP_SNK) /* Its a sink only */
 };
 
-const uint32_t vdo_goog_modes[1] =  {
-	VDO_MODE_GOOGLE(MODE_GOOGLE_FU)
-};
+const uint32_t vdo_goog_modes[1] = { VDO_MODE_GOOGLE(MODE_GOOGLE_FU) };
 
 static int svdm_response_modes(int port, uint32_t *payload)
 {
@@ -163,13 +155,15 @@ static int dp_status(int port, uint32_t *payload)
 	if (opos != OPOS_DP)
 		return 0; /* nak */
 
-	payload[1] = VDO_DP_STATUS(0,                /* IRQ_HPD */
-				   (hpd == 1),       /* HPD_HI|LOW */
-				   0,		     /* request exit DP */
-				   0,		     /* request exit USB */
-				   0,		     /* MF pref */
+	payload[1] = VDO_DP_STATUS(0, /* IRQ_HPD */
+				   (hpd == 1), /* HPD_HI|LOW */
+				   0, /* request exit DP */
+				   0, /* request exit USB */
+				   0, /* MF pref */
 				   gpio_get_level(GPIO_PD_SBU_ENABLE),
-				   0,		     /* power low */
+				   0, /* power
+					 low
+				       */
 				   0x2);
 	return 2;
 }
@@ -249,8 +243,7 @@ const struct svdm_response svdm_rsp = {
 	.exit_mode = &svdm_exit_mode,
 };
 
-int pd_custom_vdm(int port, int cnt, uint32_t *payload,
-		  uint32_t **rpayload)
+int pd_custom_vdm(int port, int cnt, uint32_t *payload, uint32_t **rpayload)
 {
 	int rsize;
 
diff --git a/board/dirinboz/battery.c b/board/dirinboz/battery.c
index c148f9aa52..d02d424ba4 100644
--- a/board/dirinboz/battery.c
+++ b/board/dirinboz/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/dirinboz/board.c b/board/dirinboz/board.c
index d49f82773b..c6e35cf7e8 100644
--- a/board/dirinboz/board.c
+++ b/board/dirinboz/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,7 +8,7 @@
 #include "cros_board_info.h"
 #include "charge_state.h"
 #include "driver/bc12/pi3usb9201.h"
-#include "driver/ppc/aoz1380.h"
+#include "driver/ppc/aoz1380_public.h"
 #include "driver/ppc/nx20p348x.h"
 #include "driver/tcpm/nct38xx.h"
 #include "driver/usb_mux/amd_fp5.h"
@@ -35,8 +35,8 @@
 #include "usb_pd_tcpm.h"
 #include "usbc_ppc.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* This I2C moved. Temporarily detect and support the V0 HW. */
 int I2C_PORT_BATTERY = I2C_PORT_BATTERY_V1;
@@ -98,33 +98,43 @@ const struct usb_mux_driver usbc0_sbu_mux_driver = {
  * Since PI3USB221 is not a i2c device, .i2c_port and
  * .i2c_addr_flags are not required here.
  */
-const struct usb_mux usbc0_sbu_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &usbc0_sbu_mux_driver,
+const struct usb_mux_chain usbc0_sbu_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &usbc0_sbu_mux_driver,
+		},
 };
 
-struct usb_mux usbc1_amd_fp5_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.i2c_port = I2C_PORT_USB_AP_MUX,
-	.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
-	.driver = &amd_fp5_usb_mux_driver,
-	.flags = USB_MUX_FLAG_SET_WITHOUT_FLIP,
+struct usb_mux_chain usbc1_amd_fp5_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.i2c_port = I2C_PORT_USB_AP_MUX,
+			.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
+			.driver = &amd_fp5_usb_mux_driver,
+			.flags = USB_MUX_FLAG_SET_WITHOUT_FLIP,
+		},
 };
 
-struct usb_mux usb_muxes[] = {
+struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.i2c_port = I2C_PORT_USB_AP_MUX,
-		.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
-		.driver = &amd_fp5_usb_mux_driver,
-		.next_mux = &usbc0_sbu_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.i2c_port = I2C_PORT_USB_AP_MUX,
+			.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
+			.driver = &amd_fp5_usb_mux_driver,
+		},
+		.next = &usbc0_sbu_mux,
 	},
 	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = PS8743_I2C_ADDR1_FLAG,
-		.driver = &ps8743_usb_mux_driver,
-		.next_mux = &usbc1_amd_fp5_usb_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.i2c_port = I2C_PORT_TCPC1,
+			.i2c_addr_flags = PS8743_I2C_ADDR1_FLAG,
+			.driver = &ps8743_usb_mux_driver,
+		},
+		.next = &usbc1_amd_fp5_usb_mux,
 	}
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
@@ -167,8 +177,7 @@ void ppc_interrupt(enum gpio_signal signal)
 
 int board_set_active_charge_port(int port)
 {
-	int is_valid_port = (port >= 0 &&
-			     port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	int i;
 
 	if (port == CHARGE_PORT_NONE) {
@@ -189,7 +198,6 @@ int board_set_active_charge_port(int port)
 		return EC_ERROR_INVAL;
 	}
 
-
 	/* Check if the port is sourcing VBUS. */
 	if (ppc_is_sourcing_vbus(port)) {
 		CPRINTFUSB("Skip enable C%d", port);
@@ -291,7 +299,6 @@ static void reset_nct38xx_port(int port)
 		msleep(NCT3807_RESET_POST_DELAY_MS);
 }
 
-
 void board_reset_pd_mcu(void)
 {
 	/* Reset TCPC0 */
@@ -362,11 +369,9 @@ int board_pd_set_frs_enable(int port, int enable)
 
 	/* Use the TCPC to enable fast switch when FRS included */
 	if (port == USBC_PORT_C0) {
-		rv = ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN,
-				    !!enable);
+		rv = ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN, !!enable);
 	} else {
-		rv = ioex_set_level(IOEX_USB_C1_TCPC_FASTSW_CTL_EN,
-				    !!enable);
+		rv = ioex_set_level(IOEX_USB_C1_TCPC_FASTSW_CTL_EN, !!enable);
 	}
 
 	return rv;
@@ -434,14 +439,13 @@ int usb_port_enable[USBA_PORT_COUNT] = {
  * The connector has 24 pins total, and there is no pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-		{0, 5}, {1, 1}, {1, 0}, {0, 6}, {0, 7},
-		{1, 4}, {1, 3}, {1, 6}, {1, 7}, {3, 1},
-		{2, 0}, {1, 5}, {2, 6}, {2, 7}, {2, 1},
-		{2, 4}, {2, 5}, {1, 2}, {2, 3}, {2, 2},
-		{3, 0}, {-1, -1}, {-1, -1}, {-1, -1},
+	{ 0, 5 }, { 1, 1 }, { 1, 0 }, { 0, 6 },	  { 0, 7 },   { 1, 4 },
+	{ 1, 3 }, { 1, 6 }, { 1, 7 }, { 3, 1 },	  { 2, 0 },   { 1, 5 },
+	{ 2, 6 }, { 2, 7 }, { 2, 1 }, { 2, 4 },	  { 2, 5 },   { 1, 2 },
+	{ 2, 3 }, { 2, 2 }, { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 },
 };
 const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 #endif
 
 #define CHARGING_CURRENT_500mA 500
@@ -501,13 +505,13 @@ int charger_profile_override(struct charge_state_data *curr)
 }
 
 enum ec_status charger_profile_override_get_param(uint32_t param,
-							uint32_t *value)
+						  uint32_t *value)
 {
 	return EC_RES_INVALID_PARAM;
 }
 
 enum ec_status charger_profile_override_set_param(uint32_t param,
-							uint32_t value)
+						  uint32_t value)
 {
 	return EC_RES_INVALID_PARAM;
 }
diff --git a/board/dirinboz/board.h b/board/dirinboz/board.h
index 67e083b51f..a27176fcae 100644
--- a/board/dirinboz/board.h
+++ b/board/dirinboz/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,7 +20,7 @@
 #define CONFIG_USB_PD_PORT_MAX_COUNT 2
 #define CONFIG_USB_PORT_ENABLE_DYNAMIC
 
-#undef  CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
+#undef CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
 #define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 40000
 
 #define CONFIG_CHARGER_PROFILE_OVERRIDE
@@ -35,39 +35,35 @@
 #undef CONFIG_LED_ONOFF_STATES
 
 /* GPIO mapping from board specific name to EC common name. */
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_EC_BATT_PRES_ODL
-#define CONFIG_SCI_GPIO			GPIO_EC_FCH_SCI_ODL
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_AP_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT_L		GPIO_EC_EDP_BL_DISABLE
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_FCH_PWR_BTN_L
-#define GPIO_PCH_RSMRST_L		GPIO_EC_FCH_RSMRST_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S5_L		GPIO_SLP_S5_L
-#define GPIO_PCH_SYS_PWROK		GPIO_EC_FCH_PWROK
-#define GPIO_PCH_WAKE_L			GPIO_EC_FCH_WAKE_L
-#define GPIO_POWER_BUTTON_L		GPIO_EC_PWR_BTN_ODL
-#define GPIO_S0_PGOOD			GPIO_S0_PWROK_OD
-#define GPIO_S5_PGOOD			GPIO_EC_PWROK_OD
-#define GPIO_SYS_RESET_L		GPIO_EC_SYS_RST_L
-#define GPIO_VOLUME_DOWN_L		GPIO_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
+#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL
+#define CONFIG_SCI_GPIO GPIO_EC_FCH_SCI_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_AP_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_EDP_BL_DISABLE
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PCH_PWRBTN_L GPIO_EC_FCH_PWR_BTN_L
+#define GPIO_PCH_RSMRST_L GPIO_EC_FCH_RSMRST_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L
+#define GPIO_PCH_SYS_PWROK GPIO_EC_FCH_PWROK
+#define GPIO_PCH_WAKE_L GPIO_EC_FCH_WAKE_L
+#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL
+#define GPIO_S0_PGOOD GPIO_S0_PWROK_OD
+#define GPIO_S5_PGOOD GPIO_EC_PWROK_OD
+#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L
+#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
 
 #ifndef __ASSEMBLER__
 
 /* This I2C moved. Temporarily detect and support the V0 HW. */
 extern int I2C_PORT_BATTERY;
 
-enum adc_channel {
-	ADC_TEMP_SENSOR_CHARGER,
-	ADC_TEMP_SENSOR_SOC,
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_TEMP_SENSOR_CHARGER, ADC_TEMP_SENSOR_SOC, ADC_CH_COUNT };
 
 enum battery_type {
 	BATTERY_SIMPLO_COS,
@@ -79,20 +75,11 @@ enum battery_type {
 	BATTERY_TYPE_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_COUNT };
 
-enum ioex_port {
-	IOEX_C0_NCT3807 = 0,
-	IOEX_C1_NCT3807,
-	IOEX_PORT_COUNT
-};
+enum ioex_port { IOEX_C0_NCT3807 = 0, IOEX_C1_NCT3807, IOEX_PORT_COUNT };
 
-#define PORT_TO_HPD(port) ((port == 0) \
-	? GPIO_USB3_C0_DP2_HPD \
-	: GPIO_DP1_HPD)
+#define PORT_TO_HPD(port) ((port == 0) ? GPIO_USB3_C0_DP2_HPD : GPIO_DP1_HPD)
 
 enum temp_sensor_id {
 	TEMP_SENSOR_CHARGER = 0,
@@ -101,17 +88,9 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum usba_port {
-	USBA_PORT_A0 = 0,
-	USBA_PORT_A1,
-	USBA_PORT_COUNT
-};
+enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT };
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 /*****************************************************************************
  * CBI EC FW Configuration
diff --git a/board/dirinboz/build.mk b/board/dirinboz/build.mk
index 1c0cbc4f63..45c71f962c 100644
--- a/board/dirinboz/build.mk
+++ b/board/dirinboz/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/dirinboz/ec.tasklist b/board/dirinboz/ec.tasklist
index 3a08ebc972..779bd4fdd6 100644
--- a/board/dirinboz/ec.tasklist
+++ b/board/dirinboz/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/dirinboz/gpio.inc b/board/dirinboz/gpio.inc
index f4de7e567a..ab1b83c55f 100644
--- a/board/dirinboz/gpio.inc
+++ b/board/dirinboz/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/dirinboz/led.c b/board/dirinboz/led.c
index b05ade3bcc..1c53b9173e 100644
--- a/board/dirinboz/led.c
+++ b/board/dirinboz/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -28,13 +28,10 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
-enum led_port {
-	LEFT_PORT = 0,
-	RIGHT_PORT
-};
+enum led_port { LEFT_PORT = 0, RIGHT_PORT };
 
 static void led_set_color_battery(int port, enum led_color color)
 {
@@ -44,9 +41,9 @@ static void led_set_color_battery(int port, enum led_color color)
 
 	cbi_get_board_version(&board_ver);
 	amber_led = (port == LEFT_PORT ? GPIO_LED_CHRG_L :
-				 IOEX_C1_CHARGER_LED_AMBER_DB);
+					 IOEX_C1_CHARGER_LED_AMBER_DB);
 	white_led = (port == LEFT_PORT ? GPIO_LED_FULL_L :
-				 IOEX_C1_CHARGER_LED_WHITE_DB);
+					 IOEX_C1_CHARGER_LED_WHITE_DB);
 
 	if ((board_ver >= 3) && (port == RIGHT_PORT)) {
 		led_batt_on_lvl = 1;
@@ -126,17 +123,16 @@ static void set_active_port_color(enum led_color color)
 
 	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
 		led_set_color_battery(RIGHT_PORT,
-				(port == RIGHT_PORT) ? color : LED_OFF);
+				      (port == RIGHT_PORT) ? color : LED_OFF);
 	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
 		led_set_color_battery(LEFT_PORT,
-				(port == LEFT_PORT) ? color : LED_OFF);
+				      (port == LEFT_PORT) ? color : LED_OFF);
 }
 
 static void led_set_battery(void)
 {
 	static int battery_ticks;
 	static int power_ticks;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
@@ -145,16 +141,14 @@ static void led_set_battery(void)
 	 * design, blinking both two side battery white LEDs to indicate
 	 * system suspend with non-charging state.
 	 */
-	if (chipset_in_state(CHIPSET_STATE_SUSPEND |
-				 CHIPSET_STATE_STANDBY) &&
-		charge_get_state() != PWR_STATE_CHARGE) {
-
+	if (chipset_in_state(CHIPSET_STATE_SUSPEND | CHIPSET_STATE_STANDBY) &&
+	    charge_get_state() != PWR_STATE_CHARGE) {
 		power_ticks++;
 
-		led_set_color_battery(RIGHT_PORT, power_ticks & 0x4 ?
-					  LED_WHITE : LED_OFF);
-		led_set_color_battery(LEFT_PORT, power_ticks & 0x4 ?
-					  LED_WHITE : LED_OFF);
+		led_set_color_battery(RIGHT_PORT,
+				      power_ticks & 0x4 ? LED_WHITE : LED_OFF);
+		led_set_color_battery(LEFT_PORT,
+				      power_ticks & 0x4 ? LED_WHITE : LED_OFF);
 		return;
 	}
 
@@ -168,9 +162,12 @@ static void led_set_battery(void)
 	case PWR_STATE_DISCHARGE:
 		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
 			if (charge_get_percent() < 10)
-				led_set_color_battery(RIGHT_PORT,
-					(battery_ticks % LED_TICKS_PER_CYCLE
-					 < LED_ON_TICKS) ? LED_WHITE : LED_OFF);
+				led_set_color_battery(
+					RIGHT_PORT,
+					(battery_ticks % LED_TICKS_PER_CYCLE <
+					 LED_ON_TICKS) ?
+						LED_WHITE :
+						LED_OFF);
 			else
 				led_set_color_battery(RIGHT_PORT, LED_OFF);
 		}
@@ -179,19 +176,20 @@ static void led_set_battery(void)
 			led_set_color_battery(LEFT_PORT, LED_OFF);
 		break;
 	case PWR_STATE_ERROR:
-		set_active_port_color((battery_ticks & 0x2) ?
-				LED_WHITE : LED_OFF);
+		set_active_port_color((battery_ticks & 0x2) ? LED_WHITE :
+							      LED_OFF);
 		break;
 	case PWR_STATE_CHARGE_NEAR_FULL:
 		set_active_port_color(LED_WHITE);
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			set_active_port_color((battery_ticks %
-				LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-				LED_AMBER : LED_OFF);
-		else
-			set_active_port_color(LED_WHITE);
+		set_active_port_color(LED_WHITE);
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		set_active_port_color(
+			(battery_ticks % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
+				LED_AMBER :
+				LED_OFF);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
diff --git a/board/discovery-stm32f072/board.c b/board/discovery-stm32f072/board.c
index 086e5260a2..478bce663c 100644
--- a/board/discovery-stm32f072/board.c
+++ b/board/discovery-stm32f072/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -28,31 +28,22 @@ void button_event(enum gpio_signal signal);
 #include "gpio_list.h"
 
 static enum gpio_signal const usb_gpio_list[] = {
-	GPIO_USER_BUTTON,
-	GPIO_LED_U,
-	GPIO_LED_D,
-	GPIO_LED_L,
-	GPIO_LED_R,
+	GPIO_USER_BUTTON, GPIO_LED_U, GPIO_LED_D, GPIO_LED_L, GPIO_LED_R,
 };
 
 /*
  * This instantiates struct usb_gpio_config const usb_gpio, plus several other
  * variables, all named something beginning with usb_gpio_
  */
-USB_GPIO_CONFIG(usb_gpio,
-		usb_gpio_list,
-		USB_IFACE_GPIO,
-		USB_EP_GPIO);
+USB_GPIO_CONFIG(usb_gpio, usb_gpio_list, USB_IFACE_GPIO, USB_EP_GPIO);
 
 /******************************************************************************
  * Setup USART1 as a loopback device, it just echo's back anything sent to it.
  */
 static struct usart_config const loopback_usart;
 
-static struct queue const loopback_queue =
-	QUEUE_DIRECT(64, uint8_t,
-		     loopback_usart.producer,
-		     loopback_usart.consumer);
+static struct queue const loopback_queue = QUEUE_DIRECT(
+	64, uint8_t, loopback_usart.producer, loopback_usart.consumer);
 
 static struct usart_rx_dma const loopback_rx_dma =
 	USART_RX_DMA(STM32_DMAC_CH3, 8);
@@ -60,14 +51,9 @@ static struct usart_rx_dma const loopback_rx_dma =
 static struct usart_tx_dma const loopback_tx_dma =
 	USART_TX_DMA(STM32_DMAC_CH2, 16);
 
-static struct usart_config const loopback_usart =
-	USART_CONFIG(usart1_hw,
-		     loopback_rx_dma.usart_rx,
-		     loopback_tx_dma.usart_tx,
-		     115200,
-		     0,
-		     loopback_queue,
-		     loopback_queue);
+static struct usart_config const loopback_usart = USART_CONFIG(
+	usart1_hw, loopback_rx_dma.usart_rx, loopback_tx_dma.usart_tx, 115200,
+	0, loopback_queue, loopback_queue);
 
 /******************************************************************************
  * Forward USART4 as a simple USB serial interface.
@@ -75,36 +61,24 @@ static struct usart_config const loopback_usart =
 static struct usart_config const forward_usart;
 struct usb_stream_config const forward_usb;
 
-static struct queue const usart_to_usb = QUEUE_DIRECT(64, uint8_t,
-						      forward_usart.producer,
-						      forward_usb.consumer);
-static struct queue const usb_to_usart = QUEUE_DIRECT(64, uint8_t,
-						      forward_usb.producer,
-						      forward_usart.consumer);
+static struct queue const usart_to_usb =
+	QUEUE_DIRECT(64, uint8_t, forward_usart.producer, forward_usb.consumer);
+static struct queue const usb_to_usart =
+	QUEUE_DIRECT(64, uint8_t, forward_usb.producer, forward_usart.consumer);
 
 static struct usart_tx_dma const forward_tx_dma =
 	USART_TX_DMA(STM32_DMAC_CH7, 16);
 
 static struct usart_config const forward_usart =
-	USART_CONFIG(usart4_hw,
-		     usart_rx_interrupt,
-		     forward_tx_dma.usart_tx,
-		     115200,
-		     0,
-		     usart_to_usb,
-		     usb_to_usart);
-
-#define USB_STREAM_RX_SIZE	16
-#define USB_STREAM_TX_SIZE	16
-
-USB_STREAM_CONFIG(forward_usb,
-		  USB_IFACE_STREAM,
-		  USB_STR_STREAM_NAME,
-		  USB_EP_STREAM,
-		  USB_STREAM_RX_SIZE,
-		  USB_STREAM_TX_SIZE,
-		  usb_to_usart,
-		  usart_to_usb)
+	USART_CONFIG(usart4_hw, usart_rx_interrupt, forward_tx_dma.usart_tx,
+		     115200, 0, usart_to_usb, usb_to_usart);
+
+#define USB_STREAM_RX_SIZE 16
+#define USB_STREAM_TX_SIZE 16
+
+USB_STREAM_CONFIG(forward_usb, USB_IFACE_STREAM, USB_STR_STREAM_NAME,
+		  USB_EP_STREAM, USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE,
+		  usb_to_usart, usart_to_usb)
 
 /******************************************************************************
  * Handle button presses by cycling the LEDs on the board.  Also run a tick
@@ -135,18 +109,17 @@ DECLARE_HOOK(HOOK_TICK, usb_gpio_tick, HOOK_PRIO_DEFAULT);
  * Define the strings used in our USB descriptors.
  */
 const void *const usb_strings[] = {
-	[USB_STR_DESC]         = usb_string_desc,
-	[USB_STR_VENDOR]       = USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]      = USB_STRING_DESC("discovery-stm32f072"),
-	[USB_STR_VERSION]      = USB_STRING_DESC(CROS_EC_VERSION32),
-	[USB_STR_STREAM_NAME]  = USB_STRING_DESC("Forward"),
+	[USB_STR_DESC] = usb_string_desc,
+	[USB_STR_VENDOR] = USB_STRING_DESC("Google LLC"),
+	[USB_STR_PRODUCT] = USB_STRING_DESC("discovery-stm32f072"),
+	[USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32),
+	[USB_STR_STREAM_NAME] = USB_STRING_DESC("Forward"),
 	[USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Shell"),
-	[USB_STR_SPI_NAME]     = USB_STRING_DESC("SPI"),
+	[USB_STR_SPI_NAME] = USB_STRING_DESC("SPI"),
 };
 
 BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
 
-
 /******************************************************************************
  * Support SPI bridging over USB, this requires usb_spi_board_enable and
  * usb_spi_board_disable to be defined to enable and disable the SPI bridge.
@@ -154,7 +127,7 @@ BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
 
 /* SPI devices */
 const struct spi_device_t spi_devices[] = {
-	{ CONFIG_SPI_FLASH_PORT, 0, GPIO_SPI_CS},
+	{ CONFIG_SPI_FLASH_PORT, 0, GPIO_SPI_CS },
 };
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
diff --git a/board/discovery-stm32f072/board.h b/board/discovery-stm32f072/board.h
index b889ebc8fe..d5db803b65 100644
--- a/board/discovery-stm32f072/board.h
+++ b/board/discovery-stm32f072/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -32,27 +32,26 @@
 #define CONFIG_USB_CONSOLE
 
 /* USB interface indexes (use define rather than enum to expand them) */
-#define USB_IFACE_STREAM  0
-#define USB_IFACE_GPIO    1
-#define USB_IFACE_SPI     2
+#define USB_IFACE_STREAM 0
+#define USB_IFACE_GPIO 1
+#define USB_IFACE_SPI 2
 #define USB_IFACE_CONSOLE 3
-#define USB_IFACE_COUNT   4
+#define USB_IFACE_COUNT 4
 
 /* USB endpoint indexes (use define rather than enum to expand them) */
 #define USB_EP_CONTROL 0
-#define USB_EP_STREAM  1
-#define USB_EP_GPIO    2
-#define USB_EP_SPI     3
+#define USB_EP_STREAM 1
+#define USB_EP_GPIO 2
+#define USB_EP_SPI 3
 #define USB_EP_CONSOLE 4
-#define USB_EP_COUNT   5
+#define USB_EP_COUNT 5
 
 /* Enable control of GPIOs over USB */
 #define CONFIG_USB_GPIO
 
 /* Enable control of SPI over USB */
 #define CONFIG_SPI_CONTROLLER
-#define CONFIG_SPI_FLASH_PORT    0  /* First SPI controller port */
-
+#define CONFIG_SPI_FLASH_PORT 0 /* First SPI controller port */
 
 #define CONFIG_USB_SPI
 
diff --git a/board/discovery-stm32f072/build.mk b/board/discovery-stm32f072/build.mk
index c1892335ed..21613f74eb 100644
--- a/board/discovery-stm32f072/build.mk
+++ b/board/discovery-stm32f072/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
+# Copyright 2014 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/discovery-stm32f072/ec.tasklist b/board/discovery-stm32f072/ec.tasklist
index cc4c2ad42d..2bd7e2f5ce 100644
--- a/board/discovery-stm32f072/ec.tasklist
+++ b/board/discovery-stm32f072/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/discovery-stm32f072/gpio.inc b/board/discovery-stm32f072/gpio.inc
index 65bdd0179b..25b5f1b0e0 100644
--- a/board/discovery-stm32f072/gpio.inc
+++ b/board/discovery-stm32f072/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
+ * Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/discovery-stm32f072/openocd-flash.cfg b/board/discovery-stm32f072/openocd-flash.cfg
index ec32416934..05a697acf8 100644
--- a/board/discovery-stm32f072/openocd-flash.cfg
+++ b/board/discovery-stm32f072/openocd-flash.cfg
@@ -1,4 +1,4 @@
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
+# Copyright 2014 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/board/discovery/board.c b/board/discovery/board.c
index 0d4cde2e7c..a9ba174a4f 100644
--- a/board/discovery/board.c
+++ b/board/discovery/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -39,10 +39,8 @@ DECLARE_HOOK(HOOK_TICK, usb_gpio_tick, HOOK_PRIO_DEFAULT);
  */
 static struct usart_config const loopback_usart;
 
-static struct queue const loopback_queue =
-	QUEUE_DIRECT(64, uint8_t,
-		     loopback_usart.producer,
-		     loopback_usart.consumer);
+static struct queue const loopback_queue = QUEUE_DIRECT(
+	64, uint8_t, loopback_usart.producer, loopback_usart.consumer);
 
 static struct usart_rx_dma const loopback_rx_dma =
 	USART_RX_DMA(STM32_DMAC_CH6, 32);
@@ -50,14 +48,9 @@ static struct usart_rx_dma const loopback_rx_dma =
 static struct usart_tx_dma const loopback_tx_dma =
 	USART_TX_DMA(STM32_DMAC_CH7, 16);
 
-static struct usart_config const loopback_usart =
-	USART_CONFIG(usart2_hw,
-		     loopback_rx_dma.usart_rx,
-		     loopback_tx_dma.usart_tx,
-		     115200,
-		     0,
-		     loopback_queue,
-		     loopback_queue);
+static struct usart_config const loopback_usart = USART_CONFIG(
+	usart2_hw, loopback_rx_dma.usart_rx, loopback_tx_dma.usart_tx, 115200,
+	0, loopback_queue, loopback_queue);
 
 /******************************************************************************
  * Initialize board.
diff --git a/board/discovery/board.h b/board/discovery/board.h
index ddd2461a56..e348454af1 100644
--- a/board/discovery/board.h
+++ b/board/discovery/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/discovery/build.mk b/board/discovery/build.mk
index 42f9f9a0fc..e07d8af33d 100644
--- a/board/discovery/build.mk
+++ b/board/discovery/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
+# Copyright 2013 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/discovery/ec.tasklist b/board/discovery/ec.tasklist
index 3822ab3779..e58390c01d 100644
--- a/board/discovery/ec.tasklist
+++ b/board/discovery/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/discovery/gpio.inc b/board/discovery/gpio.inc
index 821f38ca46..da2742ff7a 100644
--- a/board/discovery/gpio.inc
+++ b/board/discovery/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
+ * Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/discovery/openocd-flash.cfg b/board/discovery/openocd-flash.cfg
index 6426ad5473..f87c191576 100644
--- a/board/discovery/openocd-flash.cfg
+++ b/board/discovery/openocd-flash.cfg
@@ -1,4 +1,4 @@
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/board/dojo/battery.c b/board/dojo/battery.c
index 290bf6067c..a766ea3e59 100644
--- a/board/dojo/battery.c
+++ b/board/dojo/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -178,19 +178,18 @@ int charger_profile_override(struct charge_state_data *curr)
 		chg_temp = K_TO_C(chg_temp);
 
 		prev_chg_lvl = chg_lvl;
-		if (chg_temp <= temp_chg_table[chg_lvl].lo_thre &&
-		    chg_lvl > 0)
+		if (chg_temp <= temp_chg_table[chg_lvl].lo_thre && chg_lvl > 0)
 			chg_lvl--;
 		else if (chg_temp >= temp_chg_table[chg_lvl].hi_thre &&
-		         chg_lvl < CHG_LEVEL_COUNT - 1)
+			 chg_lvl < CHG_LEVEL_COUNT - 1)
 			chg_lvl++;
 
 		curr->requested_current = MIN(curr->requested_current,
-		      temp_chg_table[chg_lvl].chg_curr);
+					      temp_chg_table[chg_lvl].chg_curr);
 
-		if(chg_lvl != prev_chg_lvl)
+		if (chg_lvl != prev_chg_lvl)
 			ccprints("Override chg curr to %dmA by chg LEVEL_%d",
-			         curr->requested_current, chg_lvl);
+				 curr->requested_current, chg_lvl);
 	}
 
 	return 0;
diff --git a/board/dojo/board.c b/board/dojo/board.c
index f539d17d2d..65a1635111 100644
--- a/board/dojo/board.c
+++ b/board/dojo/board.c
@@ -1,16 +1,20 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 /* Dojo board configuration */
 
 #include "cbi_fw_config.h"
+#include "cbi_ssfc.h"
+#include "charge_manager.h"
+#include "charge_state_v2.h"
 #include "common.h"
 #include "console.h"
 #include "cros_board_info.h"
 #include "driver/accel_kionix.h"
 #include "driver/accel_kx022.h"
 #include "driver/accelgyro_icm426xx.h"
+#include "driver/accelgyro_icm42607.h"
 #include "driver/accelgyro_icm_common.h"
 #include "driver/accelgyro_bmi_common_public.h"
 #include "driver/accelgyro_bmi260_public.h"
@@ -25,10 +29,11 @@
 #include "system.h"
 #include "usb_mux.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 uint32_t board_version;
+enum ec_ssfc_base_sensor base_sensor;
 
 /* Keyboard scan setting */
 __override struct keyboard_scan_config keyscan_config = {
@@ -45,6 +50,31 @@ __override struct keyboard_scan_config keyscan_config = {
 	},
 };
 
+/* Support keyboard factory test */
+#ifdef CONFIG_KEYBOARD_FACTORY_TEST
+/*
+ * Map keyboard connector pins to EC GPIO pins for factory test.
+ * Pins mapped to {-1, -1} are skipped.
+ * The connector has 30 pins total, and there is no pin 0.
+ */
+const int keyboard_factory_scan_pins[][2] = {
+	{ -1, -1 },	   { GPIO_KSO_H, 4 }, { GPIO_KSO_H, 0 },
+	{ GPIO_KSO_H, 1 }, { GPIO_KSO_H, 3 }, { GPIO_KSO_H, 2 },
+	{ -1, -1 },	   { -1, -1 },	      { GPIO_KSO_L, 5 },
+	{ GPIO_KSO_L, 6 }, { -1, -1 },	      { GPIO_KSO_L, 3 },
+	{ GPIO_KSO_L, 2 }, { GPIO_KSI, 0 },   { GPIO_KSO_L, 1 },
+	{ GPIO_KSO_L, 4 }, { GPIO_KSI, 3 },   { GPIO_KSI, 2 },
+	{ GPIO_KSO_L, 0 }, { GPIO_KSI, 5 },   { GPIO_KSI, 4 },
+	{ GPIO_KSO_L, 7 }, { GPIO_KSI, 6 },   { GPIO_KSI, 7 },
+	{ GPIO_KSI, 1 },   { -1, -1 },	      { GPIO_KSO_H, 5 },
+	{ -1, -1 },	   { GPIO_KSO_H, 6 }, { -1, -1 },
+	{ -1, -1 },
+};
+
+const int keyboard_factory_scan_pins_used =
+	ARRAY_SIZE(keyboard_factory_scan_pins);
+#endif
+
 /* Vol-up key matrix at T13 */
 const struct vol_up_key vol_up_key_matrix_T13 = {
 	.row = 3,
@@ -66,17 +96,20 @@ static void board_update_vol_up_key(void)
 			 * Set vol up key to T13 for KB_BL_TOGGLE_KEY_PRESENT
 			 * and board_version >= 2
 			 */
-			set_vol_up_key(vol_up_key_matrix_T13.row, vol_up_key_matrix_T13.col);
+			set_vol_up_key(vol_up_key_matrix_T13.row,
+				       vol_up_key_matrix_T13.col);
 		} else {
 			/*
 			 * Set vol up key to T12 for KB_BL_TOGGLE_KEY_ABSENT
 			 * and board_version >= 2
 			 */
-			set_vol_up_key(vol_up_key_matrix_T12.row, vol_up_key_matrix_T12.col);
+			set_vol_up_key(vol_up_key_matrix_T12.row,
+				       vol_up_key_matrix_T12.col);
 		}
 	} else {
 		/* Set vol up key to T13 for board_version < 2 */
-		set_vol_up_key(vol_up_key_matrix_T13.row, vol_up_key_matrix_T13.col);
+		set_vol_up_key(vol_up_key_matrix_T13.row,
+			       vol_up_key_matrix_T13.col);
 	}
 }
 
@@ -105,27 +138,26 @@ static struct mutex g_base_mutex;
 static struct mutex g_lid_mutex;
 
 static struct icm_drv_data_t g_icm426xx_data;
+static struct icm_drv_data_t g_icm42607_data;
 static struct bmi_drv_data_t g_bmi260_data;
 static struct kionix_accel_data g_kx022_data;
 
 /* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+					      { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
 
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
-static const mat33_fp_t bmi260_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t icm42607_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+						  { 0, FLOAT_TO_FP(-1), 0 },
+						  { 0, 0, FLOAT_TO_FP(1) } };
+
+static const mat33_fp_t icm426xx_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+						  { 0, FLOAT_TO_FP(-1), 0 },
+						  { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	/*
@@ -136,44 +168,46 @@ struct motion_sensor_t motion_sensors[] = {
 	[BASE_ACCEL] = {
 		.name = "Base Accel",
 		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_ICM426XX,
+		.chip = MOTIONSENSE_CHIP_BMI260,
 		.type = MOTIONSENSE_TYPE_ACCEL,
 		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &icm426xx_drv,
+		.drv = &bmi260_drv,
 		.mutex = &g_base_mutex,
-		.drv_data = &g_icm426xx_data,
+		.drv_data = &g_bmi260_data,
 		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-		.default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs. */
+		.i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
 		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
-		.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
+		.min_frequency = BMI_ACCEL_MIN_FREQ,
+		.max_frequency = BMI_ACCEL_MAX_FREQ,
+		.default_range = 4, /* g */
 		.config = {
 			/* EC use accel for angle detection */
 			[SENSOR_CONFIG_EC_S0] = {
 				.odr = 10000 | ROUND_UP_FLAG,
 				.ec_rate = 100 * MSEC,
 			},
+			/* Sensor on in S3 */
 			[SENSOR_CONFIG_EC_S3] = {
 				.odr = 10000 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
 			},
 		},
 	},
 	[BASE_GYRO] = {
 		.name = "Base Gyro",
 		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_ICM426XX,
+		.chip = MOTIONSENSE_CHIP_BMI260,
 		.type = MOTIONSENSE_TYPE_GYRO,
 		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &icm426xx_drv,
+		.drv = &bmi260_drv,
 		.mutex = &g_base_mutex,
-		.drv_data = &g_icm426xx_data,
+		.drv_data = &g_bmi260_data,
 		.port = I2C_PORT_ACCEL,
-		.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+		.i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
 		.default_range = 1000, /* dps */
 		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = ICM426XX_GYRO_MIN_FREQ,
-		.max_frequency = ICM426XX_GYRO_MAX_FREQ,
+		.min_frequency = BMI_GYRO_MIN_FREQ,
+		.max_frequency = BMI_GYRO_MAX_FREQ,
 	},
 	[LID_ACCEL] = {
 		.name = "Lid Accel",
@@ -205,69 +239,117 @@ struct motion_sensor_t motion_sensors[] = {
 };
 const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
-struct motion_sensor_t bmi260_base_accel = {
+struct motion_sensor_t icm42607_base_accel = {
 	.name = "Base Accel",
 	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_BMI260,
+	.chip = MOTIONSENSE_CHIP_ICM42607,
 	.type = MOTIONSENSE_TYPE_ACCEL,
 	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &bmi260_drv,
+	.drv = &icm42607_drv,
 	.mutex = &g_base_mutex,
-	.drv_data = &g_bmi260_data,
+	.drv_data = &g_icm42607_data,
 	.port = I2C_PORT_ACCEL,
-	.i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
-	.rot_standard_ref = &bmi260_standard_ref,
-	.min_frequency = BMI_ACCEL_MIN_FREQ,
-	.max_frequency = BMI_ACCEL_MAX_FREQ,
-	.default_range = 4, /* g */
+	.i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
+	.default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/
+	.rot_standard_ref = &icm42607_standard_ref,
+	.min_frequency = ICM42607_ACCEL_MIN_FREQ,
+	.max_frequency = ICM42607_ACCEL_MAX_FREQ,
 	.config = {
 		/* EC use accel for angle detection */
 		[SENSOR_CONFIG_EC_S0] = {
 			.odr = 10000 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
 		},
-		/* Sensor on in S3 */
+		/* EC use accel for angle detection */
 		[SENSOR_CONFIG_EC_S3] = {
 			.odr = 10000 | ROUND_UP_FLAG,
+		},
+	},
+};
+
+struct motion_sensor_t icm42607_base_gyro = {
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM42607,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm42607_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm42607_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &icm42607_standard_ref,
+	.min_frequency = ICM42607_GYRO_MIN_FREQ,
+	.max_frequency = ICM42607_GYRO_MAX_FREQ,
+};
+
+struct motion_sensor_t icm426xx_base_accel = {
+	.name = "Base Accel",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_ACCEL,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs. */
+	.rot_standard_ref = &icm426xx_standard_ref,
+	.min_frequency = ICM426XX_ACCEL_MIN_FREQ,
+	.max_frequency = ICM426XX_ACCEL_MAX_FREQ,
+	.config = {
+		/* EC use accel for angle detection */
+		[SENSOR_CONFIG_EC_S0] = {
+			.odr = 10000 | ROUND_UP_FLAG,
 			.ec_rate = 100 * MSEC,
 		},
+		[SENSOR_CONFIG_EC_S3] = {
+			.odr = 10000 | ROUND_UP_FLAG,
+		},
 	},
 };
 
-struct motion_sensor_t bmi260_base_gyro = {
+struct motion_sensor_t icm426xx_base_gyro = {
 	.name = "Base Gyro",
 	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_BMI260,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
 	.type = MOTIONSENSE_TYPE_GYRO,
 	.location = MOTIONSENSE_LOC_BASE,
-	.drv = &bmi260_drv,
+	.drv = &icm426xx_drv,
 	.mutex = &g_base_mutex,
-	.drv_data = &g_bmi260_data,
+	.drv_data = &g_icm426xx_data,
 	.port = I2C_PORT_ACCEL,
-	.i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
 	.default_range = 1000, /* dps */
-	.rot_standard_ref = &bmi260_standard_ref,
-	.min_frequency = BMI_GYRO_MIN_FREQ,
-	.max_frequency = BMI_GYRO_MAX_FREQ,
+	.rot_standard_ref = &icm426xx_standard_ref,
+	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
+	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
 };
 
 static void board_update_motion_sensor_config(void)
 {
-	if (board_version >= 2) {
-		motion_sensors[BASE_ACCEL] = bmi260_base_accel;
-		motion_sensors[BASE_GYRO] = bmi260_base_gyro;
-		ccprints("BASE Accelgyro is BMI260");
-	} else {
+	if (board_version <= 1 || base_sensor == SSFC_SENSOR_ICM426XX) {
+		motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
+		motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
 		ccprints("BASE Accelgyro is ICM426XX");
+	} else if (base_sensor == SSFC_SENSOR_ICM42607) {
+		motion_sensors[BASE_ACCEL] = icm42607_base_accel;
+		motion_sensors[BASE_GYRO] = icm42607_base_gyro;
+		ccprints("BASE Accelgyro is ICM42607");
+	} else {
+		ccprints("BASE Accelgyro is BMI260");
 	}
 }
 
 void motion_interrupt(enum gpio_signal signal)
 {
-	if (board_version >= 2)
-		bmi260_interrupt(signal);
-	else
+	if (board_version <= 1 || base_sensor == SSFC_SENSOR_ICM426XX)
 		icm426xx_interrupt(signal);
+	else if (base_sensor == SSFC_SENSOR_ICM42607)
+		icm42607_interrupt(signal);
+	else
+		bmi260_interrupt(signal);
 }
 
 /* PWM */
@@ -299,7 +381,7 @@ const struct pwm_t pwm_channels[] = {
 	},
 	[PWM_CH_KBLIGHT] = {
 		.channel = 3,
-		.freq_hz = 10000,
+		.freq_hz = 2400,
 		.pcfsr_sel = PWM_PRESCALER_C6,
 	},
 	[PWM_CH_LED_C0_WHITE] = {
@@ -319,8 +401,7 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
 /* USB Mux */
 
-static int board_ps8762_mux_set(const struct usb_mux *me,
-				mux_state_t mux_state)
+static int board_ps8762_mux_set(const struct usb_mux *me, mux_state_t mux_state)
 {
 	/* Make sure the PS8802 is awake */
 	RETURN_ERROR(ps8802_i2c_wake(me));
@@ -328,21 +409,18 @@ static int board_ps8762_mux_set(const struct usb_mux *me,
 	/* USB specific config */
 	if (mux_state & USB_PD_MUX_USB_ENABLED) {
 		/* Boost the USB gain */
-		RETURN_ERROR(ps8802_i2c_field_update16(me,
-					PS8802_REG_PAGE2,
-					PS8802_REG2_USB_SSEQ_LEVEL,
-					PS8802_USBEQ_LEVEL_UP_MASK,
-					PS8802_USBEQ_LEVEL_UP_12DB));
+		RETURN_ERROR(ps8802_i2c_field_update16(
+			me, PS8802_REG_PAGE2, PS8802_REG2_USB_SSEQ_LEVEL,
+			PS8802_USBEQ_LEVEL_UP_MASK,
+			PS8802_USBEQ_LEVEL_UP_12DB));
 	}
 
 	/* DP specific config */
 	if (mux_state & USB_PD_MUX_DP_ENABLED) {
 		/* Boost the DP gain */
-		RETURN_ERROR(ps8802_i2c_field_update8(me,
-					PS8802_REG_PAGE2,
-					PS8802_REG2_DPEQ_LEVEL,
-					PS8802_DPEQ_LEVEL_UP_MASK,
-					PS8802_DPEQ_LEVEL_UP_9DB));
+		RETURN_ERROR(ps8802_i2c_field_update8(
+			me, PS8802_REG_PAGE2, PS8802_REG2_DPEQ_LEVEL,
+			PS8802_DPEQ_LEVEL_UP_MASK, PS8802_DPEQ_LEVEL_UP_9DB));
 	}
 
 	return EC_SUCCESS;
@@ -350,11 +428,10 @@ static int board_ps8762_mux_set(const struct usb_mux *me,
 
 static int board_ps8762_mux_init(const struct usb_mux *me)
 {
-	return ps8802_i2c_field_update8(
-			me, PS8802_REG_PAGE1,
-			PS8802_REG_DCIRX,
-			PS8802_AUTO_DCI_MODE_DISABLE | PS8802_FORCE_DCI_MODE,
-			PS8802_AUTO_DCI_MODE_DISABLE);
+	return ps8802_i2c_field_update8(me, PS8802_REG_PAGE1, PS8802_REG_DCIRX,
+					PS8802_AUTO_DCI_MODE_DISABLE |
+						PS8802_FORCE_DCI_MODE,
+					PS8802_AUTO_DCI_MODE_DISABLE);
 }
 
 static int board_anx3443_mux_set(const struct usb_mux *me,
@@ -365,24 +442,40 @@ static int board_anx3443_mux_set(const struct usb_mux *me,
 	return EC_SUCCESS;
 }
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX0,
-		.i2c_addr_flags = PS8802_I2C_ADDR_FLAGS,
-		.driver = &ps8802_usb_mux_driver,
-		.board_init = &board_ps8762_mux_init,
-		.board_set = &board_ps8762_mux_set,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX0,
+				.i2c_addr_flags = PS8802_I2C_ADDR_FLAGS,
+				.driver = &ps8802_usb_mux_driver,
+				.board_init = &board_ps8762_mux_init,
+				.board_set = &board_ps8762_mux_set,
+			},
 	},
 	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_USB_MUX1,
-		.i2c_addr_flags = ANX3443_I2C_ADDR0_FLAGS,
-		.driver = &anx3443_usb_mux_driver,
-		.board_set = &board_anx3443_mux_set,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_USB_MUX1,
+				.i2c_addr_flags = ANX3443_I2C_ADDR0_FLAGS,
+				.driver = &anx3443_usb_mux_driver,
+				.board_set = &board_anx3443_mux_set,
+			},
 	},
 };
 
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
+{
+	/* Limit input current lower than 2944 mA for safety */
+	charge_ma = MIN(charge_ma, 2944);
+
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+}
+
 /* Initialize board. */
 static void board_init(void)
 {
@@ -393,21 +486,34 @@ static void board_init(void)
 	/* Store board version for use of something */
 	cbi_get_board_version(&board_version);
 
+	/* Store base sensor to recognize which base sensor we are using */
+	base_sensor = get_cbi_ssfc_base_sensor();
+
 	board_update_motion_sensor_config();
 	board_update_vol_up_key();
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
-static void board_do_chipset_resume(void)
+static void enable_nvme(void)
 {
 	gpio_set_level(GPIO_EN_PP3300_SSD, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME_INIT, enable_nvme, HOOK_PRIO_FIRST);
+
+static void disable_nvme(void)
+{
+	gpio_set_level(GPIO_EN_PP3300_SSD, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, disable_nvme, HOOK_PRIO_DEFAULT);
+
+static void board_do_chipset_resume(void)
+{
 	gpio_set_level(GPIO_EN_KB_BL, 1);
 }
 DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_do_chipset_resume, HOOK_PRIO_DEFAULT);
 
 static void board_do_chipset_suspend(void)
 {
-	gpio_set_level(GPIO_EN_PP3300_SSD, 0);
 	gpio_set_level(GPIO_EN_KB_BL, 0);
 }
 DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_do_chipset_suspend, HOOK_PRIO_DEFAULT);
diff --git a/board/dojo/board.h b/board/dojo/board.h
index 734b73bac7..cc2d5eba2f 100644
--- a/board/dojo/board.h
+++ b/board/dojo/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,6 +13,10 @@
 #define CONFIG_LTO
 #define CONFIG_PRESERVE_LOGS
 
+/* Watchdog period in ms */
+#undef CONFIG_WATCHDOG_PERIOD_MS
+#define CONFIG_WATCHDOG_PERIOD_MS 2500
+
 /*
  * TODO: Remove this option once the VBAT no longer keeps high when
  * system's power isn't presented.
@@ -25,6 +29,7 @@
 #define CONFIG_BATTERY_COUNT 1
 #define CONFIG_HOSTCMD_BATTERY_V2
 #define CONFIG_BATTERY_PRESENT_CUSTOM
+#define CONFIG_BATTERY_REVIVE_DISCONNECT
 #define CONFIG_BATTERY_VENDOR_PARAM
 
 /* BC12 */
@@ -32,18 +37,24 @@
 /* Charger */
 #define CONFIG_CHARGER_PROFILE_OVERRIDE
 
+/* Chipset */
+#define CONFIG_CHIPSET_RESUME_INIT_HOOK
+
 /* PD / USB-C / PPC */
-#undef CONFIG_USB_PD_DEBUG_LEVEL /* default to 1, configurable in ec console */
+#undef CONFIG_USB_PD_DEBUG_LEVEL /* default to 1, configurable in ec console \
+				  */
 
 /* Optional console commands */
 #define CONFIG_CMD_FLASH
 #define CONFIG_CMD_SCRATCHPAD
 #define CONFIG_CMD_STACKOVERFLOW
 
-#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV	9000
+#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV 9000
 
 /* Keyboard */
 #define CONFIG_KEYBOARD_REFRESH_ROW3
+#define CONFIG_KEYBOARD_FACTORY_TEST
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
 
 /* Sensor */
 #define CONFIG_GMR_TABLET_MODE
@@ -56,6 +67,11 @@
 #define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 
+/* ICM42607 Base accel/gyro*/
+#define CONFIG_ACCELGYRO_ICM42607
+#define CONFIG_ACCELGYRO_ICM42607_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+
 /* BMI260 accel/gyro in base */
 #define CONFIG_ACCELGYRO_BMI260
 #define CONFIG_ACCELGYRO_BMI260_INT_EVENT \
diff --git a/board/dojo/build.mk b/board/dojo/build.mk
index 25af05d562..740cd30a9d 100644
--- a/board/dojo/build.mk
+++ b/board/dojo/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -11,4 +11,4 @@ CHIP_FAMILY:=it8xxx2
 CHIP_VARIANT:=it81202bx_1024
 BASEBOARD:=cherry
 
-board-y+=led.o battery.o board.o cbi_fw_config.o
+board-y+=led.o battery.o board.o cbi_fw_config.o cbi_ssfc.o
diff --git a/board/dojo/cbi_fw_config.c b/board/dojo/cbi_fw_config.c
index 9972e02249..96e6d9b266 100644
--- a/board/dojo/cbi_fw_config.c
+++ b/board/dojo/cbi_fw_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -30,12 +30,12 @@ DECLARE_HOOK(HOOK_INIT, cbi_fw_config_init, HOOK_PRIO_FIRST);
 
 enum fw_config_kblight_type get_cbi_fw_config_kblight(void)
 {
-	return ((cached_fw_config & FW_CONFIG_KB_BL_MASK)
-			>> FW_CONFIG_KB_BL_OFFSET);
+	return ((cached_fw_config & FW_CONFIG_KB_BL_MASK) >>
+		FW_CONFIG_KB_BL_OFFSET);
 }
 
 enum fw_config_kblayout_type get_cbi_fw_config_kblayout(void)
 {
-	return ((cached_fw_config & FW_CONFIG_KB_LAYOUT_MASK)
-			>> FW_CONFIG_KB_LAYOUT_OFFSET);
+	return ((cached_fw_config & FW_CONFIG_KB_LAYOUT_MASK) >>
+		FW_CONFIG_KB_LAYOUT_OFFSET);
 }
diff --git a/board/dojo/cbi_fw_config.h b/board/dojo/cbi_fw_config.h
index 7f98585b84..6ca0e5b9a8 100644
--- a/board/dojo/cbi_fw_config.h
+++ b/board/dojo/cbi_fw_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,8 +17,8 @@ enum fw_config_kblight_type {
 	KB_BL_ABSENT = 0,
 	KB_BL_PRESENT = 1,
 };
-#define FW_CONFIG_KB_BL_OFFSET			0
-#define FW_CONFIG_KB_BL_MASK			GENMASK(0, 0)
+#define FW_CONFIG_KB_BL_OFFSET 0
+#define FW_CONFIG_KB_BL_MASK GENMASK(0, 0)
 
 /*
  * Keyboard layout (bit 4-5)
@@ -27,8 +27,8 @@ enum fw_config_kblayout_type {
 	KB_BL_TOGGLE_KEY_ABSENT = 0, /* Vol-up key on T12 */
 	KB_BL_TOGGLE_KEY_PRESENT = 1, /* Vol-up key on T13 */
 };
-#define FW_CONFIG_KB_LAYOUT_OFFSET		4
-#define FW_CONFIG_KB_LAYOUT_MASK		GENMASK(5, 4)
+#define FW_CONFIG_KB_LAYOUT_OFFSET 4
+#define FW_CONFIG_KB_LAYOUT_MASK GENMASK(5, 4)
 
 enum fw_config_kblight_type get_cbi_fw_config_kblight(void);
 enum fw_config_kblayout_type get_cbi_fw_config_kblayout(void);
diff --git a/board/shotzo/cbi_ssfc.c b/board/dojo/cbi_ssfc.c
index 9f1383b455..3b7ed483f5 100644
--- a/board/shotzo/cbi_ssfc.c
+++ b/board/dojo/cbi_ssfc.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The ChromiumOS Authors.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,7 +12,7 @@
 #define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 /* Cache SSFC on init since we don't expect it to change in runtime */
-static union dedede_cbi_ssfc cached_ssfc;
+static union dojo_cbi_ssfc cached_ssfc;
 BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t));
 
 static void cbi_ssfc_init(void)
@@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
 
 enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
 {
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
 }
 
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
 {
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
 }
diff --git a/board/shotzo/cbi_ssfc.h b/board/dojo/cbi_ssfc.h
index ddfada8a68..da37dbaca1 100644
--- a/board/shotzo/cbi_ssfc.h
+++ b/board/dojo/cbi_ssfc.h
@@ -1,15 +1,15 @@
-/* Copyright 2022 The ChromiumOS Authors.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#ifndef _DEDEDE_CBI_SSFC__H_
-#define _DEDEDE_CBI_SSFC__H_
+#ifndef _DOJO_CBI_SSFC__H_
+#define _DOJO_CBI_SSFC__H_
 
 #include "stdint.h"
 
 /****************************************************************************
- * Dedede CBI Second Source Factory Cache
+ * Dojo CBI Second Source Factory Cache
  */
 
 /*
@@ -17,10 +17,9 @@
  */
 enum ec_ssfc_base_sensor {
 	SSFC_SENSOR_BASE_DEFAULT = 0,
-	SSFC_SENSOR_BMI160 = 1,
+	SSFC_SENSOR_ICM42607 = 1,
 	SSFC_SENSOR_ICM426XX = 2,
-	SSFC_SENSOR_LSM6DSM = 3,
-	SSFC_SENSOR_ICM42607 = 4
+	SSFC_SENSOR_BMI260 = 3,
 };
 
 /*
@@ -28,11 +27,11 @@ enum ec_ssfc_base_sensor {
  */
 enum ec_ssfc_lid_sensor {
 	SSFC_SENSOR_LID_DEFAULT = 0,
-	SSFC_SENSOR_BMA255 = 1,
-	SSFC_SENSOR_BMA422 = 2,
+	SSFC_SENSOR_BMA422 = 1,
+	SSFC_SENSOR_KX022 = 2,
 };
 
-union dedede_cbi_ssfc {
+union dojo_cbi_ssfc {
 	struct {
 		uint32_t base_sensor : 3;
 		uint32_t lid_sensor : 3;
@@ -55,5 +54,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
  */
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
 
-
-#endif /* _DEDEDE_CBI_SSFC__H_ */
+#endif /* _DOJO_CBI_SSFC__H_ */
diff --git a/board/dojo/ec.tasklist b/board/dojo/ec.tasklist
index f9050fef87..5ce0fab583 100644
--- a/board/dojo/ec.tasklist
+++ b/board/dojo/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/dojo/gpio.inc b/board/dojo/gpio.inc
index c215d3f5d4..0fb85b47b7 100644
--- a/board/dojo/gpio.inc
+++ b/board/dojo/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -118,6 +118,12 @@ ALTERNATE(PIN_MASK(I, 0b11001001), 0, MODULE_ADC, 0) /* ADC 0,3,6,7 */
 /* SPI */
 ALTERNATE(PIN_MASK(M, 0x33), 0, MODULE_SPI, 0) /* SPI */
 
+/* KEYBOARD */
+ALTERNATE(PIN_MASK(KSI,   0xFF), 0, MODULE_KEYBOARD_SCAN, 0)		/* KSI0-7 */
+ALTERNATE(PIN_MASK(KSO_H, 0xFF), 0, MODULE_KEYBOARD_SCAN, 0)		/* KSO8-15 */
+ALTERNATE(PIN_MASK(KSO_L, 0xFB), 0, MODULE_KEYBOARD_SCAN, 0)		/* KSO0-1, 3-7 */
+GPIO(EC_KSO_02_INV, PIN(KSO_L, 2), GPIO_OUT_HIGH) /* KSO2 inverted */
+
 /* Unimplemented Pins  */
 GPIO(PG_PP5000_S5_OD,        PIN(D, 2), GPIO_INPUT)
 /* *_ODL pin has external pullup so don't pull it down. */
diff --git a/board/dojo/led.c b/board/dojo/led.c
index 38d0e4904b..4b2b379a1b 100644
--- a/board/dojo/led.c
+++ b/board/dojo/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -38,7 +38,7 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 enum led_port {
@@ -49,15 +49,15 @@ enum led_port {
 static void battery_led_set_color(enum led_port port, enum led_color color)
 {
 	pwm_enable(port ? PWM_CH_LED_C1_AMBER : PWM_CH_LED_C0_AMBER,
-	           (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
+		   (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
 	pwm_enable(port ? PWM_CH_LED_C1_WHITE : PWM_CH_LED_C0_WHITE,
-	           (color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF);
+		   (color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF);
 }
 
 static void power_led_set_color(enum led_color color)
 {
 	pwm_enable(PWM_CH_LED_PWR,
-	           (color == LED_WHITE) ? PWR_LED_ON : PWR_LED_OFF);
+		   (color == LED_WHITE) ? PWR_LED_ON : PWR_LED_OFF);
 }
 
 void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
@@ -83,17 +83,17 @@ void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
 static int led_set_color(enum ec_led_id led_id, enum led_color color)
 {
 	switch (led_id) {
-		case EC_LED_ID_RIGHT_LED:
-			battery_led_set_color(RIGHT_PORT, color);
-			break;
-		case EC_LED_ID_LEFT_LED:
-			battery_led_set_color(LEFT_PORT, color);
-			break;
-		case EC_LED_ID_POWER_LED:
-			power_led_set_color(color);
-			break;
-		default:
-			return EC_ERROR_UNKNOWN;
+	case EC_LED_ID_RIGHT_LED:
+		battery_led_set_color(RIGHT_PORT, color);
+		break;
+	case EC_LED_ID_LEFT_LED:
+		battery_led_set_color(LEFT_PORT, color);
+		break;
+	case EC_LED_ID_POWER_LED:
+		power_led_set_color(color);
+		break;
+	default:
+		return EC_ERROR_UNKNOWN;
 	}
 
 	return EC_SUCCESS;
@@ -121,17 +121,16 @@ static void set_active_port_color(enum led_color color)
 
 	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
 		battery_led_set_color(RIGHT_PORT,
-		                      (port == RIGHT_PORT) ? color : LED_OFF);
+				      (port == RIGHT_PORT) ? color : LED_OFF);
 	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
 		battery_led_set_color(LEFT_PORT,
-		                      (port == LEFT_PORT) ? color : LED_OFF);
+				      (port == LEFT_PORT) ? color : LED_OFF);
 }
 
 static void board_led_set_battery(void)
 {
 	static int battery_ticks;
 	int battery_led_blink_cycle;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
@@ -142,18 +141,20 @@ static void board_led_set_battery(void)
 		break;
 	case PWR_STATE_DISCHARGE:
 		if (charge_get_percent() <= 10) {
-			battery_led_blink_cycle = battery_ticks %
-			                          (2 * TIMES_TICK_ONE_SEC);
+			battery_led_blink_cycle =
+				battery_ticks % (2 * TIMES_TICK_ONE_SEC);
 			if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
 				battery_led_set_color(RIGHT_PORT,
-				                      (battery_led_blink_cycle <
-				                      TIMES_TICK_ONE_SEC) ?
-				                      LED_AMBER : LED_OFF);
+						      (battery_led_blink_cycle <
+						       TIMES_TICK_ONE_SEC) ?
+							      LED_AMBER :
+							      LED_OFF);
 			if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
 				battery_led_set_color(LEFT_PORT,
-				                      (battery_led_blink_cycle <
-				                      TIMES_TICK_ONE_SEC) ?
-				                      LED_AMBER : LED_OFF);
+						      (battery_led_blink_cycle <
+						       TIMES_TICK_ONE_SEC) ?
+							      LED_AMBER :
+							      LED_OFF);
 		} else {
 			if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
 				battery_led_set_color(RIGHT_PORT, LED_OFF);
@@ -165,27 +166,30 @@ static void board_led_set_battery(void)
 		battery_led_blink_cycle = battery_ticks % TIMES_TICK_ONE_SEC;
 		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
 			battery_led_set_color(RIGHT_PORT,
-			                      (battery_led_blink_cycle <
-			                      TIMES_TICK_HALF_SEC) ?
-			                      LED_AMBER : LED_OFF);
+					      (battery_led_blink_cycle <
+					       TIMES_TICK_HALF_SEC) ?
+						      LED_AMBER :
+						      LED_OFF);
 		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
 			battery_led_set_color(LEFT_PORT,
-			                      (battery_led_blink_cycle <
-			                      TIMES_TICK_HALF_SEC) ?
-			                      LED_AMBER : LED_OFF);
+					      (battery_led_blink_cycle <
+					       TIMES_TICK_HALF_SEC) ?
+						      LED_AMBER :
+						      LED_OFF);
 		break;
 	case PWR_STATE_CHARGE_NEAR_FULL:
 		set_active_port_color(LED_WHITE);
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE) {
-			battery_led_blink_cycle = battery_ticks %
-			                          (2 * TIMES_TICK_ONE_SEC);
-			set_active_port_color((battery_led_blink_cycle <
-			                      TIMES_TICK_ONE_SEC) ?
-			                      LED_AMBER : LED_OFF);
-		} else
-			set_active_port_color(LED_WHITE);
+		set_active_port_color(LED_WHITE);
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		battery_led_blink_cycle =
+			battery_ticks % (2 * TIMES_TICK_ONE_SEC);
+		set_active_port_color(
+			(battery_led_blink_cycle < TIMES_TICK_ONE_SEC) ?
+				LED_AMBER :
+				LED_OFF);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
@@ -205,7 +209,8 @@ static void board_led_set_power(void)
 	} else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
 		power_led_blink_cycle = power_ticks % (2 * TIMES_TICK_ONE_SEC);
 		power_led_set_color(power_led_blink_cycle < TIMES_TICK_ONE_SEC ?
-		                    LED_WHITE : LED_OFF);
+					    LED_WHITE :
+					    LED_OFF);
 	} else {
 		power_led_set_color(LED_OFF);
 	}
@@ -214,7 +219,7 @@ static void board_led_set_power(void)
 /* Called by hook task every TICK */
 static void led_tick(void)
 {
-	if(led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
 		board_led_set_power();
 
 	board_led_set_battery();
diff --git a/board/dood/battery.c b/board/dood/battery.c
index da5f4c47dc..8564eb0926 100644
--- a/board/dood/battery.c
+++ b/board/dood/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/dood/board.c b/board/dood/board.c
index cef4c21268..9d395d3bfe 100644
--- a/board/dood/board.c
+++ b/board/dood/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -45,11 +45,11 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define USB_PD_PORT_ANX7447	0
-#define USB_PD_PORT_PS8751	1
+#define USB_PD_PORT_ANX7447 0
+#define USB_PD_PORT_PS8751 1
 
 static uint8_t sku_id;
 
@@ -59,17 +59,16 @@ static uint8_t sku_id;
  * that we don't have pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-		{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-		{0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3},
-		{-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0},
-		{1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4},
-		{2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0},
-		{-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1},
-		{-1, -1},
+	{ -1, -1 }, { 0, 5 },	{ 1, 1 }, { 1, 0 },   { 0, 6 },	  { 0, 7 },
+	{ -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 },   { -1, -1 }, { 1, 6 },
+	{ 1, 7 },   { 3, 1 },	{ 2, 0 }, { 1, 5 },   { 2, 6 },	  { 2, 7 },
+	{ 2, 1 },   { 2, 4 },	{ 2, 5 }, { 1, 2 },   { 2, 3 },	  { 2, 2 },
+	{ 3, 0 },   { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 },	  { -1, -1 },
+	{ -1, -1 },
 };
 
 const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 
 /* Check PPC ID and board version to decide which one ppc is used. */
 static bool support_syv_ppc(void)
@@ -87,7 +86,6 @@ static bool support_syv_ppc(void)
 
 static void ppc_interrupt(enum gpio_signal signal)
 {
-
 	switch (signal) {
 	case GPIO_USB_PD_C0_INT_ODL:
 		if (support_syv_ppc())
@@ -113,31 +111,31 @@ static void ppc_interrupt(enum gpio_signal signal)
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_AMB] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_AMB] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				  ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_CHARGER] = { "TEMP_CHARGER", NPCX_ADC_CH1,
+				      ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 },
 	/* Vbus sensing (1/10 voltage divider). */
-	[ADC_VBUS_C0] = {
-		"VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
-	[ADC_VBUS_C1] = {
-		"VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
+	[ADC_VBUS_C0] = { "VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT * 10,
+			  ADC_READ_MAX + 1, 0 },
+	[ADC_VBUS_C1] = { "VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT * 10,
+			  ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp,
-				 .idx = 0},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
+	[TEMP_SENSOR_BATTERY] = { .name = "Battery",
+				  .type = TEMP_SENSOR_TYPE_BATTERY,
+				  .read = charge_get_battery_temp,
+				  .idx = 0 },
+	[TEMP_SENSOR_AMBIENT] = { .name = "Ambient",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_51k1_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_AMB },
+	[TEMP_SENSOR_CHARGER] = { .name = "Charger",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_13k7_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_CHARGER },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -147,11 +145,9 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0,  0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+				       { FLOAT_TO_FP(1), 0, 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
 
 /* sensor private data */
 static struct kionix_accel_data g_kx022_data;
@@ -274,8 +270,8 @@ void board_hibernate_late(void)
 
 	const uint32_t hibernate_pins[][2] = {
 		/* Turn off LEDs before going to hibernate */
-		{GPIO_BAT_LED_WHITE_L, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_BAT_LED_AMBER_L, GPIO_INPUT | GPIO_PULL_UP},
+		{ GPIO_BAT_LED_WHITE_L, GPIO_INPUT | GPIO_PULL_UP },
+		{ GPIO_BAT_LED_AMBER_L, GPIO_INPUT | GPIO_PULL_UP },
 	};
 
 	for (i = 0; i < ARRAY_SIZE(hibernate_pins); ++i)
@@ -307,15 +303,15 @@ void board_overcurrent_event(int port, int is_overcurrented)
 }
 
 const struct ppc_config_t ppc_syv682x_port0 = {
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
+	.i2c_port = I2C_PORT_TCPC0,
+	.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+	.drv = &syv682x_drv,
 };
 
 const struct ppc_config_t ppc_syv682x_port1 = {
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
+	.i2c_port = I2C_PORT_TCPC1,
+	.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+	.drv = &syv682x_drv,
 };
 
 static void board_setup_ppc(void)
@@ -323,12 +319,10 @@ static void board_setup_ppc(void)
 	if (!support_syv_ppc())
 		return;
 
-	memcpy(&ppc_chips[USB_PD_PORT_TCPC_0],
-		&ppc_syv682x_port0,
-		sizeof(struct ppc_config_t));
-	memcpy(&ppc_chips[USB_PD_PORT_TCPC_1],
-		&ppc_syv682x_port1,
-		sizeof(struct ppc_config_t));
+	memcpy(&ppc_chips[USB_PD_PORT_TCPC_0], &ppc_syv682x_port0,
+	       sizeof(struct ppc_config_t));
+	memcpy(&ppc_chips[USB_PD_PORT_TCPC_1], &ppc_syv682x_port1,
+	       sizeof(struct ppc_config_t));
 
 	gpio_set_flags(GPIO_USB_PD_C0_INT_ODL, GPIO_INT_BOTH);
 	gpio_set_flags(GPIO_USB_PD_C1_INT_ODL, GPIO_INT_BOTH);
diff --git a/board/dood/board.h b/board/dood/board.h
index 5b9b55af1b..8c9f225a59 100644
--- a/board/dood/board.h
+++ b/board/dood/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,13 +16,13 @@
 #define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD
 
 /* I2C bus configuraiton */
-#define I2C_PORT_ACCEL	I2C_PORT_SENSOR
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
 
 #define CONFIG_LED_COMMON
 
 /* Sensors */
-#define CONFIG_ACCEL_KX022	/* Lid accel */
-#define CONFIG_ACCELGYRO_BMI160	/* Base accel */
+#define CONFIG_ACCEL_KX022 /* Lid accel */
+#define CONFIG_ACCELGYRO_BMI160 /* Base accel */
 
 #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
 /* Sensors without hardware FIFO are in forced mode */
@@ -32,8 +32,7 @@
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 
-#define CONFIG_SYNC_INT_EVENT	\
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
+#define CONFIG_SYNC_INT_EVENT TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
 
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_UPDATE
@@ -60,7 +59,6 @@
 /* prevent pd reset when battery soc under 2% */
 #define CONFIG_USB_PD_RESET_MIN_BATT_SOC 2
 
-
 #ifndef __ASSEMBLER__
 
 /* support factory keyboard test */
@@ -70,10 +68,10 @@
 #include "registers.h"
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_AMB,		/* ADC0 */
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC1 */
-	ADC_VBUS_C0,			/* ADC9 */
-	ADC_VBUS_C1,			/* ADC4 */
+	ADC_TEMP_SENSOR_AMB, /* ADC0 */
+	ADC_TEMP_SENSOR_CHARGER, /* ADC1 */
+	ADC_VBUS_C0, /* ADC9 */
+	ADC_VBUS_C1, /* ADC4 */
 	ADC_CH_COUNT
 };
 
@@ -85,12 +83,7 @@ enum temp_sensor_id {
 };
 
 /* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
diff --git a/board/dood/build.mk b/board/dood/build.mk
index 3d04b75731..998a65a3de 100644
--- a/board/dood/build.mk
+++ b/board/dood/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/dood/ec.tasklist b/board/dood/ec.tasklist
index d98db145e7..977b8b01be 100644
--- a/board/dood/ec.tasklist
+++ b/board/dood/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/dood/gpio.inc b/board/dood/gpio.inc
index 961acf8ee0..b10c377ddf 100644
--- a/board/dood/gpio.inc
+++ b/board/dood/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/dood/led.c b/board/dood/led.c
index 3f6958b1bc..248dae037f 100644
--- a/board/dood/led.c
+++ b/board/dood/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,8 +10,8 @@
 #include "led_common.h"
 #include "led_onoff_states.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
 __override const int led_charge_lvl_1;
 
@@ -19,18 +19,25 @@ __override const int led_charge_lvl_2 = 100;
 
 /* Dood: Note there is only LED for charge / power */
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_WHITE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE,  2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
 const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
diff --git a/board/dooly/board.c b/board/dooly/board.c
index 545ec86ebe..6e1f6ebbeb 100644
--- a/board/dooly/board.c
+++ b/board/dooly/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -50,8 +50,8 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* Sensors */
 static struct mutex g_accel_mutex;
@@ -109,11 +109,9 @@ static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
 	.saturation.atime = TCS_DEFAULT_ATIME,
 };
 
-const mat33_fp_t screen_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0,  0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t screen_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					 { FLOAT_TO_FP(1), 0, 0 },
+					 { 0, 0, FLOAT_TO_FP(-1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[SCREEN_ACCEL] = {
@@ -190,15 +188,15 @@ DECLARE_DEFERRED(power_monitor);
  * that range, so we define and use a 64-bit fixed representation instead.
  */
 typedef int64_t fp64_t;
-#define INT_TO_FP64(x)   ((int64_t)(x) << 32)
-#define FP64_TO_INT(x)   ((x) >> 32)
+#define INT_TO_FP64(x) ((int64_t)(x) << 32)
+#define FP64_TO_INT(x) ((x) >> 32)
 #define FLOAT_TO_FP64(x) ((int64_t)((x) * (float)(1LL << 32)))
 
 __override void tcs3400_translate_to_xyz(struct motion_sensor_t *s,
 					 int32_t *crgb_data, int32_t *xyz_data)
 {
 	struct tcs_saturation_t *sat_p =
-		&(TCS3400_RGB_DRV_DATA(s+1)->saturation);
+		&(TCS3400_RGB_DRV_DATA(s + 1)->saturation);
 
 	int32_t cur_gain = (1 << (2 * sat_p->again));
 	int32_t integration_time_us =
@@ -208,40 +206,37 @@ __override void tcs3400_translate_to_xyz(struct motion_sensor_t *s,
 	fp64_t result;
 
 	/* Use different coefficients based on n_interval = (G+B)/C */
-	fp64_t gb_sum = INT_TO_FP64(crgb_data[2]) +
-			INT_TO_FP64(crgb_data[3]);
+	fp64_t gb_sum = INT_TO_FP64(crgb_data[2]) + INT_TO_FP64(crgb_data[3]);
 	fp64_t n_interval = gb_sum / MAX(crgb_data[0], 1);
 
 	if (n_interval < FLOAT_TO_FP64(0.692)) {
 		const float scale = 799.797;
 
-		c_coeff = FLOAT_TO_FP64(0.009  * scale);
-		r_coeff = FLOAT_TO_FP64(0.056  * scale);
-		g_coeff = FLOAT_TO_FP64(2.735  * scale);
+		c_coeff = FLOAT_TO_FP64(0.009 * scale);
+		r_coeff = FLOAT_TO_FP64(0.056 * scale);
+		g_coeff = FLOAT_TO_FP64(2.735 * scale);
 		b_coeff = FLOAT_TO_FP64(-1.903 * scale);
 	} else if (n_interval < FLOAT_TO_FP64(1.012)) {
 		const float scale = 801.347;
 
-		c_coeff = FLOAT_TO_FP64(0.202  * scale);
-		r_coeff = FLOAT_TO_FP64(-1.1   * scale);
-		g_coeff = FLOAT_TO_FP64(8.692  * scale);
+		c_coeff = FLOAT_TO_FP64(0.202 * scale);
+		r_coeff = FLOAT_TO_FP64(-1.1 * scale);
+		g_coeff = FLOAT_TO_FP64(8.692 * scale);
 		b_coeff = FLOAT_TO_FP64(-7.068 * scale);
 	} else {
 		const float scale = 795.574;
 
 		c_coeff = FLOAT_TO_FP64(-0.661 * scale);
-		r_coeff = FLOAT_TO_FP64(1.334  * scale);
-		g_coeff = FLOAT_TO_FP64(1.095  * scale);
+		r_coeff = FLOAT_TO_FP64(1.334 * scale);
+		g_coeff = FLOAT_TO_FP64(1.095 * scale);
 		b_coeff = FLOAT_TO_FP64(-1.821 * scale);
 	}
 
 	/* Multiply each channel by the coefficient and compute the sum.
 	 * Note: int * fp64_t = fp64_t and fp64_t + fp64_t = fp64_t.
 	 */
-	result = crgb_data[0] * c_coeff +
-		 crgb_data[1] * r_coeff +
-		 crgb_data[2] * g_coeff +
-		 crgb_data[3] * b_coeff;
+	result = crgb_data[0] * c_coeff + crgb_data[1] * r_coeff +
+		 crgb_data[2] * g_coeff + crgb_data[3] * b_coeff;
 
 	/* Adjust for exposure time and sensor gain.
 	 * Note: fp64_t / int = fp64_t.
@@ -328,8 +323,8 @@ uint16_t tcpc_get_alert_status(void)
 }
 
 /* Called when the charge manager has switched to a new port. */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	/* Blink alert if insufficient power per system_can_boot_ap(). */
 	int insufficient_power =
@@ -346,12 +341,12 @@ static int32_t base_5v_power;
  * Power usage for each port as measured or estimated.
  * Units are milliwatts (5v x ma current)
  */
-#define PWR_BASE_LOAD	(5*1335)
-#define PWR_FRONT_HIGH	(5*1603)
-#define PWR_FRONT_LOW	(5*963)
-#define PWR_C_HIGH	(5*3740)
-#define PWR_C_LOW	(5*2090)
-#define PWR_MAX		(5*10000)
+#define PWR_BASE_LOAD (5 * 1335)
+#define PWR_FRONT_HIGH (5 * 1603)
+#define PWR_FRONT_LOW (5 * 963)
+#define PWR_C_HIGH (5 * 3740)
+#define PWR_C_LOW (5 * 2090)
+#define PWR_MAX (5 * 10000)
 
 /*
  * Update the 5V power usage, assuming no throttling,
@@ -416,16 +411,14 @@ static const struct {
 	int current;
 } bj_power[] = {
 	{ /* 0 - 65W (also default) */
-	.voltage = 19500,
-	.current = 3200
-	},
+	  .voltage = 19500,
+	  .current = 3200 },
 	{ /* 1 - 90W */
-	.voltage = 19500,
-	.current = 4600
-	},
+	  .voltage = 19500,
+	  .current = 4600 },
 };
 
-#define ADP_DEBOUNCE_MS		1000  /* Debounce time for BJ plug/unplug */
+#define ADP_DEBOUNCE_MS 1000 /* Debounce time for BJ plug/unplug */
 /* Debounced connection state of the barrel jack */
 static int8_t adp_connected = -1;
 static void adp_connect_deferred(void)
@@ -470,29 +463,26 @@ static void adp_state_init(void)
 }
 DECLARE_HOOK(HOOK_INIT, adp_state_init, HOOK_PRIO_INIT_CHARGE_MANAGER + 1);
 
-
 #include "gpio_list.h" /* Must come after other header files. */
 
 /******************************************************************************/
 /* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
+const struct spi_device_t spi_devices[] = {};
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
 /******************************************************************************/
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN]        = { .channel = 5,
-				.flags = PWM_CONFIG_OPEN_DRAIN,
-				.freq = 25000},
-	[PWM_CH_LED_RED]    = { .channel = 0,
-				.flags = PWM_CONFIG_ACTIVE_LOW |
-					 PWM_CONFIG_DSLEEP,
-				.freq = 2000 },
-	[PWM_CH_LED_WHITE]  = { .channel = 2,
-				.flags = PWM_CONFIG_ACTIVE_LOW |
-					 PWM_CONFIG_DSLEEP,
-				.freq = 2000 },
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
+	[PWM_CH_LED_RED] = { .channel = 0,
+			     .flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+			     .freq = 2000 },
+	[PWM_CH_LED_WHITE] = { .channel = 2,
+			       .flags = PWM_CONFIG_ACTIVE_LOW |
+					PWM_CONFIG_DSLEEP,
+			       .freq = 2000 },
 };
 
 /******************************************************************************/
@@ -517,71 +507,61 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.flags = TCPC_FLAGS_RESET_ACTIVE_HIGH,
 	},
 };
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_TCPC_0] = {
-		.usb_port = USB_PD_PORT_TCPC_0,
-		.driver = &anx7447_usb_mux_driver,
-		.hpd_update = &anx7447_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_0,
+			.driver = &anx7447_usb_mux_driver,
+			.hpd_update = &anx7447_tcpc_update_hpd_status,
+		},
 	},
 	[USB_PD_PORT_TCPC_1] = {
-		.usb_port = USB_PD_PORT_TCPC_1,
-		.driver = &anx7447_usb_mux_driver,
-		.hpd_update = &anx7447_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_1,
+			.driver = &anx7447_usb_mux_driver,
+			.hpd_update = &anx7447_tcpc_update_hpd_status,
+		},
 	},
 };
 
 /******************************************************************************/
 /* I2C port map configuration */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "ina",
-		.port = I2C_PORT_INA,
-		.kbps = 400,
-		.scl  = GPIO_I2C0_SCL,
-		.sda  = GPIO_I2C0_SDA
-	},
-	{
-		.name = "ppc0",
-		.port = I2C_PORT_PPC0,
-		.kbps = 400,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	},
-	{
-		.name = "ppc1",
-		.port = I2C_PORT_PPC1,
-		.kbps = 400,
-		.scl  = GPIO_I2C2_SCL,
-		.sda  = GPIO_I2C2_SDA
-	},
-	{
-		.name = "tcpc0",
-		.port = I2C_PORT_TCPC0,
-		.kbps = 400,
-		.scl  = GPIO_I2C3_SCL,
-		.sda  = GPIO_I2C3_SDA
-	},
-	{
-		.name = "tcpc1",
-		.port = I2C_PORT_TCPC1,
-		.kbps = 400,
-		.scl  = GPIO_I2C4_SCL,
-		.sda  = GPIO_I2C4_SDA
-	},
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 400,
-		.scl  = GPIO_I2C5_SCL,
-		.sda  = GPIO_I2C5_SDA
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl  = GPIO_I2C7_SCL,
-		.sda  = GPIO_I2C7_SDA
-	},
+	{ .name = "ina",
+	  .port = I2C_PORT_INA,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_SCL,
+	  .sda = GPIO_I2C0_SDA },
+	{ .name = "ppc0",
+	  .port = I2C_PORT_PPC0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "ppc1",
+	  .port = I2C_PORT_PPC1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
+	{ .name = "tcpc1",
+	  .port = I2C_PORT_TCPC1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C4_SCL,
+	  .sda = GPIO_I2C4_SDA },
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 400,
+	  .scl = GPIO_I2C5_SCL,
+	  .sda = GPIO_I2C5_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_I2C7_SCL,
+	  .sda = GPIO_I2C7_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -637,15 +617,14 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
 /******************************************************************************/
 /* Wake up pins */
-const enum gpio_signal hibernate_wake_pins[] = {
-};
+const enum gpio_signal hibernate_wake_pins[] = {};
 const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 
 /******************************************************************************/
 /* Physical fans. These are logically separate from pwm_channels. */
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = -1,
 };
@@ -664,7 +643,7 @@ BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
 /******************************************************************************/
 /* MFT channels. These are logically separate from pwm_channels. */
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN },
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
@@ -673,8 +652,8 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_A \
-	{ \
+#define THERMAL_A                \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = 0, \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
@@ -727,7 +706,7 @@ static void cbi_init(void)
 	if (cbi_get_ssfc(&val) == EC_SUCCESS)
 		ssfc = val;
 	CPRINTS("Board Version: %d, SKU ID: 0x%08x, "
-			"F/W config: 0x%08x, SSFC: 0x%08x ",
+		"F/W config: 0x%08x, SSFC: 0x%08x ",
 		board_version, sku_id, fw_config, ssfc);
 }
 DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1);
@@ -793,29 +772,23 @@ static void board_chipset_startup(void)
 	/* set high to enable EDID ROM WP */
 	gpio_set_level(GPIO_EC_EDID_WP_DISABLE_L, 1);
 }
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup,
-	     HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
 
 static void board_chipset_shutdown(void)
 {
 	/* set low to prevent power leakage */
 	gpio_set_level(GPIO_EC_EDID_WP_DISABLE_L, 0);
 }
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown,
-	     HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
 /******************************************************************************/
 /* USB-C PPC Configuration */
 struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.i2c_port = I2C_PORT_PPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	[USB_PD_PORT_TCPC_1] = {
-		.i2c_port = I2C_PORT_PPC1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
+	[USB_PD_PORT_TCPC_0] = { .i2c_port = I2C_PORT_PPC0,
+				 .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+				 .drv = &sn5s330_drv },
+	[USB_PD_PORT_TCPC_1] = { .i2c_port = I2C_PORT_PPC1,
+				 .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+				 .drv = &sn5s330_drv },
 };
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
@@ -842,7 +815,6 @@ static void board_tcpc_init(void)
 	/* Enable other overcurrent interrupts */
 	gpio_enable_interrupt(GPIO_USB_A0_OC_ODL);
 	gpio_enable_interrupt(GPIO_USB_A1_OC_ODL);
-
 }
 /* Make sure this is called after fw_config is initialised */
 DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 2);
@@ -965,8 +937,8 @@ void board_enable_s0_rails(int enable)
 
 unsigned int ec_config_get_bj_power(void)
 {
-	unsigned int bj =
-		(fw_config & EC_CFG_BJ_POWER_MASK) >> EC_CFG_BJ_POWER_L;
+	unsigned int bj = (fw_config & EC_CFG_BJ_POWER_MASK) >>
+			  EC_CFG_BJ_POWER_L;
 	/* Out of range value defaults to 0 */
 	if (bj >= ARRAY_SIZE(bj_power))
 		bj = 0;
@@ -1021,28 +993,28 @@ unsigned int ec_ssfc_get_led_ic(void)
  *
  *  All measurements are in milliwatts.
  */
-#define THROT_TYPE_A		BIT(0)
-#define THROT_TYPE_C		BIT(1)
-#define THROT_PROCHOT		BIT(2)
+#define THROT_TYPE_A BIT(0)
+#define THROT_TYPE_C BIT(1)
+#define THROT_PROCHOT BIT(2)
 
 /*
  * Power gain if front USB A ports are limited.
  */
-#define POWER_GAIN_TYPE_A	3200
+#define POWER_GAIN_TYPE_A 3200
 /*
  * Power gain if Type C port is limited.
  */
-#define POWER_GAIN_TYPE_C	8800
+#define POWER_GAIN_TYPE_C 8800
 /*
  * Power is averaged over 10 ms, with a reading every 2 ms.
  */
-#define POWER_DELAY_MS		2
-#define POWER_READINGS		(10/POWER_DELAY_MS)
+#define POWER_DELAY_MS 2
+#define POWER_READINGS (10 / POWER_DELAY_MS)
 
 /* PROCHOT_DEFER_OFF is to extend CPU prochot long enough
  * to pass safety requirement 30 * 2ms = 60 ms
  */
-#define PROCHOT_DEFER_OFF		30
+#define PROCHOT_DEFER_OFF 30
 
 static void power_monitor(void)
 {
@@ -1058,8 +1030,7 @@ static void power_monitor(void)
 	 * If CPU is off or suspended, no need to throttle
 	 * or restrict power.
 	 */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF |
-			     CHIPSET_STATE_SUSPEND)) {
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF | CHIPSET_STATE_SUSPEND)) {
 		/*
 		 * Slow down monitoring, assume no throttling required.
 		 */
@@ -1087,7 +1058,7 @@ static void power_monitor(void)
 			 */
 			power = (adc_read_channel(ADC_VBUS) *
 				 adc_read_channel(ADC_PPVAR_IMON)) /
-				 1000;
+				1000;
 			/* Init power table */
 			if (history[0] == 0) {
 				for (i = 0; i < POWER_READINGS; i++)
@@ -1114,8 +1085,7 @@ static void power_monitor(void)
 			 * For barrel-jack supplies, the rating can be
 			 * exceeded briefly, so use the average.
 			 */
-			if (charge_manager_get_supplier() ==
-			    CHARGE_SUPPLIER_PD)
+			if (charge_manager_get_supplier() == CHARGE_SUPPLIER_PD)
 				power = max;
 			else
 				power = total / POWER_READINGS;
@@ -1184,8 +1154,8 @@ static void power_monitor(void)
 		 * Check whether type C is not throttled,
 		 * and is not overcurrent.
 		 */
-		if (!((new_state & THROT_TYPE_C) ||
-		       usbc_0_overcurrent || usbc_1_overcurrent)) {
+		if (!((new_state & THROT_TYPE_C) || usbc_0_overcurrent ||
+		      usbc_1_overcurrent)) {
 			/*
 			 * [1] Type C not in overcurrent, throttle it.
 			 */
@@ -1218,8 +1188,9 @@ static void power_monitor(void)
 		gpio_set_level(GPIO_EC_PROCHOT_ODL, prochot);
 	}
 	if (diff & THROT_TYPE_C) {
-		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C)
-			? TYPEC_RP_1A5 : TYPEC_RP_3A0;
+		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C) ?
+						TYPEC_RP_1A5 :
+						TYPEC_RP_3A0;
 
 		ppc_set_vbus_source_current_limit(0, rp);
 		tcpm_select_rp_value(0, rp);
@@ -1302,5 +1273,4 @@ void board_backlight_enable_interrupt(enum gpio_signal signal)
 		oz554_interrupt(signal);
 		break;
 	}
-
 }
diff --git a/board/dooly/board.h b/board/dooly/board.h
index 884117bbbc..cb9d12f4ff 100644
--- a/board/dooly/board.h
+++ b/board/dooly/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,13 +15,13 @@
  * By default, enable all console messages except HC, ACPI and event:
  * The sensor stack is generating a lot of activity.
  */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
 #undef CONFIG_HOSTCMD_DEBUG_MODE
 #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
 
 /* NPCX7 config */
-#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
-#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
+#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */
+#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */
 
 /* Internal SPI flash on NPCX796FC is 512 kB */
 #define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
@@ -49,14 +49,13 @@
 
 /* TCS3400 ALS */
 #define CONFIG_ALS
-#define ALS_COUNT	1
+#define ALS_COUNT 1
 #define CONFIG_ALS_TCS3400
-#define CONFIG_ALS_TCS3400_INT_EVENT\
+#define CONFIG_ALS_TCS3400_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS)
 
 /* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
-	(BIT(SCREEN_ACCEL) | BIT(CLEAR_ALS))
+#define CONFIG_ACCEL_FORCE_MODE_MASK (BIT(SCREEN_ACCEL) | BIT(CLEAR_ALS))
 
 /* EC Defines */
 #define CONFIG_ADC
@@ -74,7 +73,7 @@
 #undef CONFIG_HIBERNATE
 #define CONFIG_HOST_INTERFACE_ESPI
 #define CONFIG_LED_COMMON
-#undef  CONFIG_LID_SWITCH
+#undef CONFIG_LID_SWITCH
 #define CONFIG_LTO
 #define CONFIG_PWM
 #define CONFIG_VBOOT_EFS2
@@ -83,7 +82,6 @@
 #define CONFIG_VSTORE_SLOT_COUNT 1
 #define CONFIG_SHA256
 
-
 /* EC Commands */
 #define CONFIG_CMD_BUTTON
 /* Include CLI command needed to support CCD testing. */
@@ -120,7 +118,7 @@
 #define CONFIG_CPU_PROCHOT_ACTIVE_LOW
 
 /* Dedicated barreljack charger port */
-#undef  CONFIG_DEDICATED_CHARGE_PORT_COUNT
+#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT
 #define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1
 #define DEDICATED_CHARGE_PORT 2
 
@@ -141,15 +139,15 @@
 #define CONFIG_INA3221
 
 /* b/143501304 */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	4000	/* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	2000	/* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 4000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 2000 /* us */
 #undef CONFIG_USBC_VCONN_SWAP_DELAY_US
-#define CONFIG_USBC_VCONN_SWAP_DELAY_US		8000	/* us */
+#define CONFIG_USBC_VCONN_SWAP_DELAY_US 8000 /* us */
 
-#define PD_OPERATING_POWER_MW	CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
-#define PD_MAX_POWER_MW		100000
-#define PD_MAX_CURRENT_MA	5000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
+#define PD_MAX_POWER_MW 100000
+#define PD_MAX_CURRENT_MA 5000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Fan and temp. */
 #define CONFIG_FANS 1
@@ -173,7 +171,7 @@
 #define CONFIG_USB_PD_DECODE_SOP
 #undef CONFIG_USB_CHARGER
 #define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PID		0x5040
+#define CONFIG_USB_PID 0x5040
 #define CONFIG_USB_PD_ALT_MODE
 #define CONFIG_USB_PD_ALT_MODE_DFP
 #define CONFIG_USB_PD_DISCHARGE_PPC
@@ -193,10 +191,10 @@
 #define CONFIG_USBC_VCONN
 #define CONFIG_USBC_VCONN_SWAP
 
-#define USB_PD_PORT_TCPC_0	0
+#define USB_PD_PORT_TCPC_0 0
 #define BOARD_TCPC_C0_RESET_HOLD_DELAY ANX74XX_RESET_HOLD_MS
 #define BOARD_TCPC_C0_RESET_POST_DELAY ANX74XX_RESET_HOLD_MS
-#define USB_PD_PORT_TCPC_1	1
+#define USB_PD_PORT_TCPC_1 1
 #define BOARD_TCPC_C1_RESET_HOLD_DELAY ANX74XX_RESET_HOLD_MS
 #define BOARD_TCPC_C1_RESET_POST_DELAY ANX74XX_RESET_HOLD_MS
 
@@ -208,16 +206,16 @@
 /* I2C Bus Configuration */
 #define CONFIG_I2C
 #define CONFIG_I2C_CONTROLLER
-#define I2C_PORT_INA		NPCX_I2C_PORT0_0
-#define I2C_PORT_SENSORS	NPCX_I2C_PORT0_0
-#define I2C_PORT_PPC0		NPCX_I2C_PORT1_0
-#define I2C_PORT_PPC1		NPCX_I2C_PORT2_0
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT3_0
-#define I2C_PORT_TCPC1		NPCX_I2C_PORT4_1
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-#define I2C_PORT_BACKLIGHT	NPCX_I2C_PORT7_0
+#define I2C_PORT_INA NPCX_I2C_PORT0_0
+#define I2C_PORT_SENSORS NPCX_I2C_PORT0_0
+#define I2C_PORT_PPC0 NPCX_I2C_PORT1_0
+#define I2C_PORT_PPC1 NPCX_I2C_PORT2_0
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT3_0
+#define I2C_PORT_TCPC1 NPCX_I2C_PORT4_1
+#define I2C_PORT_POWER NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+#define I2C_PORT_BACKLIGHT NPCX_I2C_PORT7_0
 
 /*
  * LED backlight controller
@@ -239,11 +237,11 @@ enum charge_port {
 };
 
 enum adc_channel {
-	ADC_SNS_PP3300,     /* ADC2 */
-	ADC_SNS_PP1050,     /* ADC7 */
-	ADC_VBUS,           /* ADC4 */
-	ADC_PPVAR_IMON,     /* ADC9 */
-	ADC_TEMP_SENSOR_1,  /* ADC0 */
+	ADC_SNS_PP3300, /* ADC2 */
+	ADC_SNS_PP1050, /* ADC7 */
+	ADC_VBUS, /* ADC4 */
+	ADC_PPVAR_IMON, /* ADC9 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
 	/* Number of ADC channels */
 	ADC_CH_COUNT
 };
@@ -268,10 +266,7 @@ enum mft_channel {
 	MFT_CH_COUNT,
 };
 
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_COUNT
-};
+enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_COUNT };
 
 enum sensor_id {
 	SCREEN_ACCEL = 0,
@@ -286,7 +281,6 @@ enum ssfc_led_id {
 	SSFC_LED_COUNT,
 };
 
-
 /* Board specific handlers */
 void board_reset_pd_mcu(void);
 void board_set_tcpc_power_mode(int port, int mode);
@@ -299,20 +293,20 @@ void show_critical_error(void);
 /*
  * Barrel-jack power (4 bits).
  */
-#define EC_CFG_BJ_POWER_L		0
-#define EC_CFG_BJ_POWER_H		3
+#define EC_CFG_BJ_POWER_L 0
+#define EC_CFG_BJ_POWER_H 3
 #define EC_CFG_BJ_POWER_MASK GENMASK(EC_CFG_BJ_POWER_H, EC_CFG_BJ_POWER_L)
 /*
  * USB Connector 4 not present (1 bit) (not used).
  */
-#define EC_CFG_NO_USB4_L		4
-#define EC_CFG_NO_USB4_H		4
+#define EC_CFG_NO_USB4_L 4
+#define EC_CFG_NO_USB4_H 4
 #define EC_CFG_NO_USB4_MASK GENMASK(EC_CFG_NO_USB4_H, EC_CFG_NO_USB4_L)
 /*
  * Thermal solution config (3 bits).
  */
-#define EC_CFG_THERMAL_L		5
-#define EC_CFG_THERMAL_H		7
+#define EC_CFG_THERMAL_L 5
+#define EC_CFG_THERMAL_H 7
 #define EC_CFG_THERMAL_MASK GENMASK(EC_CFG_THERMAL_H, EC_CFG_THERMAL_L)
 
 /*
@@ -321,11 +315,10 @@ void show_critical_error(void);
 /*
  * Led driver IC (2 bits).
  */
-#define EC_SSFC_LED_L		0
-#define EC_SSFC_LED_H		1
+#define EC_SSFC_LED_L 0
+#define EC_SSFC_LED_H 1
 #define EC_SSFC_LED_MASK GENMASK(EC_SSFC_LED_H, EC_SSFC_LED_L)
 
-
 unsigned int ec_config_get_bj_power(void);
 unsigned int ec_config_get_thermal_solution(void);
 unsigned int ec_ssfc_get_led_ic(void);
@@ -335,31 +328,31 @@ void board_backlight_enable_interrupt(enum gpio_signal signal);
 #endif /* !__ASSEMBLER__ */
 
 /* Pin renaming */
-#define GPIO_WP_L               GPIO_EC_WP_ODL
-#define GPIO_PP5000_A_PG_OD     GPIO_PG_PP5000_A_OD
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
-#define GPIO_RECOVERY_L         GPIO_EC_RECOVERY_BTN_ODL
-#define GPIO_POWER_BUTTON_L	GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_VOLUME_UP_L	GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L	GPIO_EC_VOLDN_BTN_ODL
-#define GPIO_PCH_WAKE_L		GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L	GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_ENTERING_RW	GPIO_EC_ENTERING_RW
-#define GPIO_SYS_RESET_L	GPIO_SYS_RST_ODL
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_PCH_RTCRST		GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_TEMP_SENSOR_POWER	GPIO_EN_ROA_RAILS
-#define GPIO_AC_PRESENT		GPIO_BJ_ADP_PRESENT_L
+#define GPIO_WP_L GPIO_EC_WP_ODL
+#define GPIO_PP5000_A_PG_OD GPIO_PG_PP5000_A_OD
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
+#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_ODL
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_EN_ROA_RAILS
+#define GPIO_AC_PRESENT GPIO_BJ_ADP_PRESENT_L
 
 /*
  * There is no RSMRST input, so alias it to the output. This short-circuits
  * common_intel_x86_handle_rsmrst.
  */
-#define GPIO_PG_EC_RSMRST_ODL	GPIO_PCH_RSMRST_L
+#define GPIO_PG_EC_RSMRST_ODL GPIO_PCH_RSMRST_L
 
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/dooly/build.mk b/board/dooly/build.mk
index 0f55c45f77..f9096c64ff 100644
--- a/board/dooly/build.mk
+++ b/board/dooly/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/dooly/ec.tasklist b/board/dooly/ec.tasklist
index 72b81be8d8..cf509f86a2 100644
--- a/board/dooly/ec.tasklist
+++ b/board/dooly/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/dooly/gpio.inc b/board/dooly/gpio.inc
index 65488936b7..d92dedd145 100644
--- a/board/dooly/gpio.inc
+++ b/board/dooly/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,12 +25,12 @@ GPIO_INT(PG_VPRIM_CORE_A_OD,   PIN(2, 3), GPIO_INT_BOTH, power_signal_interrupt)
 GPIO_INT(PG_PP1050_A_OD,       PIN(2, 2), GPIO_INT_BOTH, power_signal_interrupt)
 /* EC output, but also interrupt so this can be polled as a power signal */
 GPIO_INT(EC_PCH_RSMRST_L,      PIN(A, 6), GPIO_OUTPUT | GPIO_INT_F_RISING | GPIO_INT_F_FALLING, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(PG_PP2500_DRAM_U_OD,  PIN(2, 0), GPIO_INT_BOTH, power_signal_interrupt)
 GPIO_INT(PG_PP1200_U_OD,       PIN(2, 1), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, slp_s3_interrupt)
 #endif
 GPIO_INT(PG_PP950_VCCIO_OD,    PIN(1, 7), GPIO_INT_BOTH, power_signal_interrupt)
diff --git a/board/dooly/led.c b/board/dooly/led.c
index fefa8908fe..224db77dc0 100644
--- a/board/dooly/led.c
+++ b/board/dooly/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,16 +19,16 @@
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
 
 /*
  * Due to the CSME-Lite processing, upon startup the CPU transitions through
  * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so
  * delay turning off the LED during suspend/shutdown.
  */
-#define LED_CPU_DELAY_MS	(2000 * MSEC)
+#define LED_CPU_DELAY_MS (2000 * MSEC)
 
-const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 enum led_color {
@@ -88,9 +88,9 @@ static int set_color(enum ec_led_id id, enum led_color color, int duty)
 	}
 }
 
-#define LED_PULSE_US		(2 * SECOND)
+#define LED_PULSE_US (2 * SECOND)
 /* 40 msec for nice and smooth transition. */
-#define LED_PULSE_TICK_US	(40 * MSEC)
+#define LED_PULSE_TICK_US (40 * MSEC)
 
 /* When pulsing is enabled, brightness is incremented by <duty_inc> every
  * <interval> usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented
@@ -213,7 +213,7 @@ void show_critical_error(void)
 		set_color(EC_LED_ID_POWER_LED, LED_RED, 100);
 }
 
-static int command_led(int argc, char **argv)
+static int command_led(int argc, const char **argv)
 {
 	enum ec_led_id id = EC_LED_ID_POWER_LED;
 
diff --git a/board/dooly/usb_pd_policy.c b/board/dooly/usb_pd_policy.c
index a8d89130c2..71396e8797 100644
--- a/board/dooly/usb_pd_policy.c
+++ b/board/dooly/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,9 +19,8 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
diff --git a/board/drallion_ish/board.c b/board/drallion_ish/board.c
index fba8a622a9..b23748b62d 100644
--- a/board/drallion_ish/board.c
+++ b/board/drallion_ish/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -43,11 +43,9 @@ static struct stprivate_data g_lis2dh_data;
 static struct lis2mdl_private_data lis2mdl_a_data;
 
 /* Matrix to rotate base sensor into standard reference frame */
-const mat33_fp_t base_rot_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_rot_ref = { { 0, FLOAT_TO_FP(1), 0 },
+				  { FLOAT_TO_FP(-1), 0, 0 },
+				  { 0, 0, FLOAT_TO_FP(1) } };
 
 /* Drivers */
 struct motion_sensor_t motion_sensors[] = {
diff --git a/board/drallion_ish/board.h b/board/drallion_ish/board.h
index a14656e701..d87acc48c3 100644
--- a/board/drallion_ish/board.h
+++ b/board/drallion_ish/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -94,8 +94,8 @@
 #define CONFIG_ISH_PM_D3
 #define CONFIG_ISH_PM_RESET_PREP
 
-#define CONFIG_ISH_D0I2_MIN_USEC        (15*MSEC)
-#define CONFIG_ISH_D0I3_MIN_USEC        (100*MSEC)
+#define CONFIG_ISH_D0I2_MIN_USEC (15 * MSEC)
+#define CONFIG_ISH_D0I3_MIN_USEC (100 * MSEC)
 
 #ifndef __ASSEMBLER__
 
@@ -107,13 +107,7 @@
  * Note: Since we aren't using LPC memory map to transmit sensor data, the
  * order of this enum does not need to be accel, accel, gyro
  */
-enum sensor_id {
-	LID_ACCEL,
-	LID_GYRO,
-	BASE_ACCEL,
-	LID_MAG,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, LID_GYRO, BASE_ACCEL, LID_MAG, SENSOR_COUNT };
 
 #endif /* !__ASSEMBLER__ */
 
diff --git a/board/drallion_ish/build.mk b/board/drallion_ish/build.mk
index 51bd96d339..50d4bf1042 100644
--- a/board/drallion_ish/build.mk
+++ b/board/drallion_ish/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/drallion_ish/ec.tasklist b/board/drallion_ish/ec.tasklist
index a4db486e9a..de7d256324 100644
--- a/board/drallion_ish/ec.tasklist
+++ b/board/drallion_ish/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/drallion_ish/gpio.inc b/board/drallion_ish/gpio.inc
index 93e6752e2b..b1c585b329 100644
--- a/board/drallion_ish/gpio.inc
+++ b/board/drallion_ish/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/dratini/battery.c b/board/dratini/battery.c
index 77c84cd973..5cb57e4ba5 100644
--- a/board/dratini/battery.c
+++ b/board/dratini/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/dratini/board.c b/board/dratini/board.c
index 61634d3a7b..84759b74b6 100644
--- a/board/dratini/board.c
+++ b/board/dratini/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -43,8 +43,8 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void check_reboot_deferred(void);
 DECLARE_DEFERRED(check_reboot_deferred);
@@ -128,16 +128,16 @@ static void bc12_interrupt(enum gpio_signal signal)
 
 /******************************************************************************/
 /* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
+const struct spi_device_t spi_devices[] = {};
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
 /******************************************************************************/
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT]   = { .channel = 3, .flags = 0, .freq = 100 },
-	[PWM_CH_FAN] = {.channel = 5, .flags = PWM_CONFIG_OPEN_DRAIN,
-			.freq = 25000},
+	[PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 100 },
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
@@ -163,16 +163,20 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_TCPC_0] = {
-		.usb_port = USB_PD_PORT_TCPC_0,
-		.driver = &anx7447_usb_mux_driver,
-		.hpd_update = &anx7447_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_0,
+			.driver = &anx7447_usb_mux_driver,
+			.hpd_update = &anx7447_tcpc_update_hpd_status,
+		},
 	},
 	[USB_PD_PORT_TCPC_1] = {
-		.usb_port = USB_PD_PORT_TCPC_1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 	}
 };
 
@@ -201,17 +205,13 @@ static struct bmi_drv_data_t g_bmi160_data;
 static struct accelgyro_saved_data_t g_bma255_data;
 
 /* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, FLOAT_TO_FP(-1), 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
 
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
@@ -291,7 +291,7 @@ unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
@@ -310,44 +310,43 @@ const struct fan_t fans[FAN_CH_COUNT] = {
 /******************************************************************************/
 /* MFT channels. These are logically separate from pwm_channels. */
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN },
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		"TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_2] = {
-		"TEMP_5V_REG", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_3] = {
-		"TEMP_CPU", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_1] = { "TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_2] = { "TEMP_5V_REG", NPCX_ADC_CH1, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_3] = { "TEMP_CPU", NPCX_ADC_CH2, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "5V Reg",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "CPU",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_3},
+	[TEMP_SENSOR_1] = { .name = "Charger",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "5V Reg",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "CPU",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
-
 /* Dratini Temperature sensors */
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_A \
-	{ \
+#define THERMAL_A                \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = 0, \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(73), \
@@ -366,8 +365,8 @@ __maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_B \
-	{ \
+#define THERMAL_B                \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = 0, \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(68), \
@@ -404,8 +403,8 @@ bool board_is_convertible(void)
 	 * Dratini is not.
 	 * Unprovisioned SKU 255.
 	 */
-	return sku_id == 21 || sku_id == 22 || sku_id == 23 ||
-		sku_id == 24 || sku_id == 255;
+	return sku_id == 21 || sku_id == 22 || sku_id == 23 || sku_id == 24 ||
+	       sku_id == 255;
 }
 
 static void board_update_sensor_config_from_sku(void)
@@ -485,7 +484,7 @@ bool board_has_kb_backlight(void)
 	 * Unprovisioned: 255
 	 */
 	return sku_id == 2 || sku_id == 3 || sku_id == 5 || sku_id == 8 ||
-		sku_id == 22 || sku_id == 24 || sku_id == 255;
+	       sku_id == 22 || sku_id == 24 || sku_id == 255;
 }
 
 __override uint32_t board_override_feature_flags0(uint32_t flags0)
@@ -503,15 +502,15 @@ __override uint32_t board_override_feature_flags0(uint32_t flags0)
  * The connector has 24 pins total, and there is no pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-		{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-		{0, 7}, {1, 4}, {1, 3}, {1, 6}, {1, 7},
-		{3, 1}, {2, 0}, {1, 5}, {2, 6}, {2, 7},
-		{2, 1}, {2, 4}, {2, 5}, {1, 2}, {2, 3},
-		{2, 2}, {3, 0}, {-1, -1}, {-1, -1}, {-1, -1},
+	{ -1, -1 }, { 0, 5 }, { 1, 1 },	  { 1, 0 },   { 0, 6 },
+	{ 0, 7 },   { 1, 4 }, { 1, 3 },	  { 1, 6 },   { 1, 7 },
+	{ 3, 1 },   { 2, 0 }, { 1, 5 },	  { 2, 6 },   { 2, 7 },
+	{ 2, 1 },   { 2, 4 }, { 2, 5 },	  { 1, 2 },   { 2, 3 },
+	{ 2, 2 },   { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 },
 };
 
 const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 #endif
 
 /* Disable HDMI power while AP is suspended / off */
@@ -540,7 +539,7 @@ __override void board_chipset_forced_shutdown(void)
 	hook_call_deferred(&check_reboot_deferred_data, -1);
 }
 DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_forced_shutdown,
-	HOOK_PRIO_DEFAULT);
+	     HOOK_PRIO_DEFAULT);
 
 static void check_reboot_deferred(void)
 {
diff --git a/board/dratini/board.h b/board/dratini/board.h
index 82c09494f5..9bb4347158 100644
--- a/board/dratini/board.h
+++ b/board/dratini/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -30,10 +30,10 @@
  * Dratini's battery takes several seconds to come back out of its disconnect
  * state (~4 seconds, but give it 6 for margin).
  */
-#undef  CONFIG_POWER_BUTTON_INIT_TIMEOUT
+#undef CONFIG_POWER_BUTTON_INIT_TIMEOUT
 #define CONFIG_POWER_BUTTON_INIT_TIMEOUT 6
 
-#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV	5000
+#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV 5000
 
 /* Sensors */
 /* BMI160 Base accel/gyro */
@@ -112,16 +112,16 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_AC_PRESENT		GPIO_ACOK_OD
-#define GPIO_PG_EC_RSMRST_ODL	GPIO_PG_EC_RSMRST_L
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_TEMP_SENSOR_POWER	GPIO_EN_A_RAILS
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L
+#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
 
 #ifndef __ASSEMBLER__
 
@@ -129,9 +129,9 @@
 #include "registers.h"
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_1,	/* ADC0 */
-	ADC_TEMP_SENSOR_2,	/* ADC1 */
-	ADC_TEMP_SENSOR_3,	/* ADC2 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
+	ADC_TEMP_SENSOR_3, /* ADC2 */
 	ADC_CH_COUNT
 };
 
@@ -142,11 +142,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_FAN,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_FAN, PWM_CH_COUNT };
 
 enum fan_channel {
 	FAN_CH_0 = 0,
diff --git a/board/dratini/build.mk b/board/dratini/build.mk
index 733912454f..13153c1526 100644
--- a/board/dratini/build.mk
+++ b/board/dratini/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/dratini/ec.tasklist b/board/dratini/ec.tasklist
index 4a1024a091..829be2b7c8 100644
--- a/board/dratini/ec.tasklist
+++ b/board/dratini/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/dratini/gpio.inc b/board/dratini/gpio.inc
index c242919a89..b8649ca3b1 100644
--- a/board/dratini/gpio.inc
+++ b/board/dratini/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,10 +17,10 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(PG_EC_RSMRST_L,       PIN(E, 2), GPIO_INT_BOTH, intel_x86_rsmrst_signal_interrupt)
diff --git a/board/dratini/led.c b/board/dratini/led.c
index a5a8e9e158..029ae11da8 100644
--- a/board/dratini/led.c
+++ b/board/dratini/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -24,11 +24,9 @@
 #define LED_TICKS_PER_CYCLE 10
 #define LED_ON_TICKS 5
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_LEFT_LED,
-	EC_LED_ID_RIGHT_LED,
-	EC_LED_ID_POWER_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_LEFT_LED,
+					     EC_LED_ID_RIGHT_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -36,7 +34,7 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static void led_set_color_battery(int port, enum led_color color)
@@ -147,7 +145,6 @@ static void led_set_battery(void)
 {
 	static int battery_ticks;
 	static int power_ticks;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
@@ -158,15 +155,14 @@ static void led_set_battery(void)
 	 */
 	if (!board_is_convertible()) {
 		if (chipset_in_state(CHIPSET_STATE_SUSPEND |
-					 CHIPSET_STATE_STANDBY) &&
-			charge_get_state() != PWR_STATE_CHARGE) {
-
+				     CHIPSET_STATE_STANDBY) &&
+		    charge_get_state() != PWR_STATE_CHARGE) {
 			power_ticks++;
 
-			led_set_color_battery(0, power_ticks & 0x4 ?
-						  LED_WHITE : LED_OFF);
-			led_set_color_battery(1, power_ticks & 0x4 ?
-						  LED_WHITE : LED_OFF);
+			led_set_color_battery(0, power_ticks & 0x4 ? LED_WHITE :
+								     LED_OFF);
+			led_set_color_battery(1, power_ticks & 0x4 ? LED_WHITE :
+								     LED_OFF);
 			return;
 		}
 	}
@@ -181,9 +177,12 @@ static void led_set_battery(void)
 	case PWR_STATE_DISCHARGE:
 		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
 			if (charge_get_percent() < 10)
-				led_set_color_battery(0, (battery_ticks %
-					LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-					LED_WHITE : LED_OFF);
+				led_set_color_battery(
+					0,
+					(battery_ticks % LED_TICKS_PER_CYCLE <
+					 LED_ON_TICKS) ?
+						LED_WHITE :
+						LED_OFF);
 			else
 				led_set_color_battery(0, LED_OFF);
 		}
@@ -192,19 +191,20 @@ static void led_set_battery(void)
 			led_set_color_battery(1, LED_OFF);
 		break;
 	case PWR_STATE_ERROR:
-		set_active_port_color((battery_ticks & 0x2) ?
-				LED_WHITE : LED_OFF);
+		set_active_port_color((battery_ticks & 0x2) ? LED_WHITE :
+							      LED_OFF);
 		break;
 	case PWR_STATE_CHARGE_NEAR_FULL:
 		set_active_port_color(LED_WHITE);
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			set_active_port_color((battery_ticks %
-				LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-				LED_AMBER : LED_OFF);
-		else
-			set_active_port_color(LED_WHITE);
+		set_active_port_color(LED_WHITE);
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		set_active_port_color(
+			(battery_ticks % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
+				LED_AMBER :
+				LED_OFF);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
@@ -222,9 +222,10 @@ static void led_set_power(void)
 		led_set_color_power(LED_WHITE);
 	else if (chipset_in_state(CHIPSET_STATE_SUSPEND |
 				  CHIPSET_STATE_STANDBY))
-		led_set_color_power((power_tick %
-			LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-			LED_WHITE : LED_OFF);
+		led_set_color_power(
+			(power_tick % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
+				LED_WHITE :
+				LED_OFF);
 	else
 		led_set_color_power(LED_OFF);
 }
diff --git a/board/drawcia/battery.c b/board/drawcia/battery.c
index 62d6e95947..acc50ca048 100644
--- a/board/drawcia/battery.c
+++ b/board/drawcia/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/drawcia/board.c b/board/drawcia/board.c
index ce6247e931..118b3178be 100644
--- a/board/drawcia/board.c
+++ b/board/drawcia/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -43,7 +43,7 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
 
 #define INT_RECHECK_US 5000
 
@@ -182,48 +182,36 @@ static void pen_detect_interrupt(enum gpio_signal s)
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH0
-	},
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH2
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH3
-	},
-	[ADC_SUB_ANALOG] = {
-		.name = "SUB_ANALOG",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH13
-	},
-	[ADC_TEMP_SENSOR_3] = {
-		.name = "TEMP_SENSOR3",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH15
-	},
-	[ADC_TEMP_SENSOR_4] = {
-		.name = "TEMP_SENSOR4",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH16
-	},
+	[ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH0 },
+	[ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH2 },
+	[ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH3 },
+	[ADC_SUB_ANALOG] = { .name = "SUB_ANALOG",
+			     .factor_mul = ADC_MAX_MVOLT,
+			     .factor_div = ADC_READ_MAX + 1,
+			     .shift = 0,
+			     .channel = CHIP_ADC_CH13 },
+	[ADC_TEMP_SENSOR_3] = { .name = "TEMP_SENSOR3",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH15 },
+	[ADC_TEMP_SENSOR_4] = { .name = "TEMP_SENSOR4",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH16 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
@@ -272,19 +260,25 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 };
 
 /* USB Muxes */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+			},
 	},
 	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_SUB_USB_C1,
+				.i2c_addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	},
 };
 
@@ -298,17 +292,13 @@ static struct accelgyro_saved_data_t g_bma422_data;
 static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
 
 /* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, FLOAT_TO_FP(-1), 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
 
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
 /* Drivers */
 struct motion_sensor_t motion_sensors[] = {
@@ -564,8 +554,8 @@ __override void board_power_5v_enable(int enable)
 
 	if (board_get_charger_chip_count() > 1) {
 		if (sm5803_set_gpio0_level(1, !!enable))
-			CPRINTUSB("Failed to %sable sub rails!", enable ?
-								  "en" : "dis");
+			CPRINTUSB("Failed to %sable sub rails!",
+				  enable ? "en" : "dis");
 	}
 }
 
@@ -573,11 +563,11 @@ __override uint8_t board_get_usb_pd_port_count(void)
 {
 	enum fw_config_db db = get_cbi_fw_config_db();
 
-	if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI
-			|| db == DB_1A_HDMI_LTE)
+	if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI ||
+	    db == DB_1A_HDMI_LTE)
 		return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
-	else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A
-			|| db == DB_1C_1A_LTE)
+	else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A ||
+		 db == DB_1C_1A_LTE)
 		return CONFIG_USB_PD_PORT_MAX_COUNT;
 
 	ccprints("Unhandled DB configuration: %d", db);
@@ -588,11 +578,11 @@ __override uint8_t board_get_charger_chip_count(void)
 {
 	enum fw_config_db db = get_cbi_fw_config_db();
 
-	if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI
-			|| db == DB_1A_HDMI_LTE)
+	if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI ||
+	    db == DB_1A_HDMI_LTE)
 		return CHARGER_NUM - 1;
-	else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A
-			|| db == DB_1C_1A_LTE)
+	else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A ||
+		 db == DB_1C_1A_LTE)
 		return CHARGER_NUM;
 
 	ccprints("Unhandled DB configuration: %d", db);
@@ -697,33 +687,31 @@ __override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
 }
 
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq_hz = 10000,
-	}
-};
+const struct pwm_t pwm_channels[] = { [PWM_CH_KBLIGHT] = {
+					      .channel = 0,
+					      .flags = PWM_CONFIG_DSLEEP,
+					      .freq_hz = 10000,
+				      } };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
 /* Thermistors */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "Charger",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_3},
-	[TEMP_SENSOR_4] = {.name = "5V regular",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_4},
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "Charger",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
+	[TEMP_SENSOR_4] = { .name = "5V regular",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_4 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -753,9 +741,8 @@ __override void lid_angle_peripheral_enable(int enable)
 	}
 }
 
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
+__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+				       int *ki_div, int *kd, int *kd_div)
 {
 	*kp = 3;
 	*kp_div = 20;
@@ -774,14 +761,17 @@ __override void ocpc_get_pid_constants(int *kp, int *kp_div,
  * The connector has 24 pins total, and there is no pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-	{-1, -1}, {GPIO_KSO_H, 4}, {GPIO_KSO_H, 0}, {GPIO_KSO_H, 1},
-	{GPIO_KSO_H, 3}, {GPIO_KSO_H, 2}, {GPIO_KSO_L, 5}, {GPIO_KSO_L, 6},
-	{GPIO_KSO_L, 3}, {GPIO_KSO_L, 2}, {GPIO_KSI, 0}, {GPIO_KSO_L, 1},
-	{GPIO_KSO_L, 4}, {GPIO_KSI, 3}, {GPIO_KSI, 2}, {GPIO_KSO_L, 0},
-	{GPIO_KSI, 5}, {GPIO_KSI, 4}, {GPIO_KSO_L, 7}, {GPIO_KSI, 6},
-	{GPIO_KSI, 7}, {GPIO_KSI, 1}, {-1, -1}, {-1, -1}, {-1, -1},
+	{ -1, -1 },	   { GPIO_KSO_H, 4 }, { GPIO_KSO_H, 0 },
+	{ GPIO_KSO_H, 1 }, { GPIO_KSO_H, 3 }, { GPIO_KSO_H, 2 },
+	{ GPIO_KSO_L, 5 }, { GPIO_KSO_L, 6 }, { GPIO_KSO_L, 3 },
+	{ GPIO_KSO_L, 2 }, { GPIO_KSI, 0 },   { GPIO_KSO_L, 1 },
+	{ GPIO_KSO_L, 4 }, { GPIO_KSI, 3 },   { GPIO_KSI, 2 },
+	{ GPIO_KSO_L, 0 }, { GPIO_KSI, 5 },   { GPIO_KSI, 4 },
+	{ GPIO_KSO_L, 7 }, { GPIO_KSI, 6 },   { GPIO_KSI, 7 },
+	{ GPIO_KSI, 1 },   { -1, -1 },	      { -1, -1 },
+	{ -1, -1 },
 };
 
 const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 #endif
diff --git a/board/drawcia/board.h b/board/drawcia/board.h
index 9cff277255..afad544ef8 100644
--- a/board/drawcia/board.h
+++ b/board/drawcia/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,21 +23,24 @@
 
 /* Charger */
 #define CONFIG_CHARGE_RAMP_HW
-#define CONFIG_CHARGER_SM5803		/* C0 and C1: Charger */
+#define CONFIG_CHARGER_SM5803 /* C0 and C1: Charger */
+#define PD_MAX_VOLTAGE_MV 15000
 #define CONFIG_USB_PD_VBUS_DETECT_CHARGER
 #define CONFIG_USB_PD_5V_CHARGER_CTRL
 #define CONFIG_CHARGER_OTG
-#undef  CONFIG_CHARGER_SINGLE_CHIP
+#undef CONFIG_CHARGER_SINGLE_CHIP
 #define CONFIG_OCPC
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr */
+#define CONFIG_OCPC_DEF_RBATT_MOHMS               \
+	21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr \
+	    */
 
 /* PWM */
 #define CONFIG_PWM
 
 /* Sensors */
-#define CONFIG_ACCEL_BMA255		/* Lid accel */
-#define CONFIG_ACCEL_BMA4XX		/* 2nd source Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM	/* Base accel */
+#define CONFIG_ACCEL_BMA255 /* Lid accel */
+#define CONFIG_ACCEL_BMA4XX /* 2nd source Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
 /* Sensors without hardware FIFO are in forced mode */
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
 
@@ -70,8 +73,8 @@
 
 /* TCPC */
 #define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP	/* C0: ITE EC TCPC */
-#define CONFIG_USB_PD_TCPM_PS8705	/* C1: PS8705 TCPC*/
+#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0: ITE EC TCPC */
+#define CONFIG_USB_PD_TCPM_PS8705 /* C1: PS8705 TCPC*/
 #define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1
 #define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
 #define CONFIG_USB_PD_TCPC_LOW_POWER
@@ -82,8 +85,8 @@
 #define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
 
 /* USB Mux and Retimer */
-#define CONFIG_USB_MUX_IT5205			/* C1: ITE Mux */
-#define I2C_PORT_USB_MUX I2C_PORT_USB_C0	/* Required for ITE Mux */
+#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */
 
 /* USB Type A Features */
 #define USB_PORT_COUNT 1
@@ -106,21 +109,16 @@ enum pwm_channel {
 };
 
 /* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
 /* ADC channels */
 enum adc_channel {
-	ADC_VSNS_PP3300_A,     /* ADC0 */
-	ADC_TEMP_SENSOR_1,     /* ADC2 */
-	ADC_TEMP_SENSOR_2,     /* ADC3 */
-	ADC_SUB_ANALOG,        /* ADC13 */
-	ADC_TEMP_SENSOR_3,     /* ADC15 */
-	ADC_TEMP_SENSOR_4,     /* ADC16 */
+	ADC_VSNS_PP3300_A, /* ADC0 */
+	ADC_TEMP_SENSOR_1, /* ADC2 */
+	ADC_TEMP_SENSOR_2, /* ADC3 */
+	ADC_SUB_ANALOG, /* ADC13 */
+	ADC_TEMP_SENSOR_3, /* ADC15 */
+	ADC_TEMP_SENSOR_4, /* ADC16 */
 	ADC_CH_COUNT
 };
 
diff --git a/board/drawcia/build.mk b/board/drawcia/build.mk
index 806168ea0d..9b862c7624 100644
--- a/board/drawcia/build.mk
+++ b/board/drawcia/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/drawcia/cbi_ssfc.c b/board/drawcia/cbi_ssfc.c
index c4b859f133..81f3ee0dad 100644
--- a/board/drawcia/cbi_ssfc.c
+++ b/board/drawcia/cbi_ssfc.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
 
 enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
 {
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
 }
 
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
 {
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
 }
diff --git a/board/drawcia/cbi_ssfc.h b/board/drawcia/cbi_ssfc.h
index 6f3591a496..37e7d9c26f 100644
--- a/board/drawcia/cbi_ssfc.h
+++ b/board/drawcia/cbi_ssfc.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -55,5 +55,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
  */
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
 
-
 #endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/drawcia/ec.tasklist b/board/drawcia/ec.tasklist
index 2edf48ee05..c3c360febb 100644
--- a/board/drawcia/ec.tasklist
+++ b/board/drawcia/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/drawcia/gpio.inc b/board/drawcia/gpio.inc
index 2bfbb9c91b..0c4599911a 100644
--- a/board/drawcia/gpio.inc
+++ b/board/drawcia/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/drawcia/led.c b/board/drawcia/led.c
index ed22fc29ba..8e6263fbbc 100644
--- a/board/drawcia/led.c
+++ b/board/drawcia/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,10 +18,8 @@
 #define POWER_LED_ON 0
 #define POWER_LED_OFF 1
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -29,7 +27,7 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static int led_set_color_battery(enum led_color color)
@@ -116,7 +114,6 @@ static void led_set_battery(void)
 {
 	static int battery_ticks;
 	static int power_ticks;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
@@ -127,9 +124,9 @@ static void led_set_battery(void)
 	 */
 	if (get_cbi_fw_config_tablet_mode() == TABLET_MODE_ABSENT) {
 		if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
-			charge_get_state() != PWR_STATE_CHARGE) {
-			led_set_color_battery(power_ticks++ & 0x2 ?
-						  LED_WHITE : LED_OFF);
+		    charge_get_state() != PWR_STATE_CHARGE) {
+			led_set_color_battery(power_ticks++ & 0x2 ? LED_WHITE :
+								    LED_OFF);
 			return;
 		}
 	}
@@ -158,18 +155,18 @@ static void led_set_battery(void)
 			led_set_color_battery(LED_OFF);
 		break;
 	case PWR_STATE_ERROR:
-		led_set_color_battery(
-			(battery_ticks % 0x2) ? LED_WHITE : LED_OFF);
+		led_set_color_battery((battery_ticks % 0x2) ? LED_WHITE :
+							      LED_OFF);
 		break;
 	case PWR_STATE_CHARGE_NEAR_FULL:
 		led_set_color_battery(LED_WHITE);
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			led_set_color_battery(
-				(battery_ticks & 0x2) ? LED_AMBER : LED_OFF);
-		else
-			led_set_color_battery(LED_WHITE);
+		led_set_color_battery(LED_WHITE);
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		led_set_color_battery((battery_ticks & 0x2) ? LED_AMBER :
+							      LED_OFF);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
@@ -186,8 +183,7 @@ static void led_set_power(void)
 	if (chipset_in_state(CHIPSET_STATE_ON))
 		led_set_color_power(LED_WHITE);
 	else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-		led_set_color_power(
-			(power_tick & 0x2) ? LED_WHITE : LED_OFF);
+		led_set_color_power((power_tick & 0x2) ? LED_WHITE : LED_OFF);
 	else
 		led_set_color_power(LED_OFF);
 }
diff --git a/board/drawcia/usb_pd_policy.c b/board/drawcia/usb_pd_policy.c
index 7046e25d6c..2433b25431 100644
--- a/board/drawcia/usb_pd_policy.c
+++ b/board/drawcia/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,8 +13,8 @@
 #include "driver/tcpm/tcpci.h"
 #include "usb_pd.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
@@ -65,18 +65,7 @@ int pd_set_power_supply_ready(int port)
 
 __override bool pd_check_vbus_level(int port, enum vbus_level level)
 {
-	int vbus_voltage;
-
-	/* If we're unable to speak to the charger, best to guess false */
-	if (charger_get_vbus_voltage(port, &vbus_voltage))
-		return false;
-
-	if (level == VBUS_SAFE0V)
-		return vbus_voltage < PD_V_SAFE0V_MAX;
-	else if (level == VBUS_PRESENT)
-		return vbus_voltage > PD_V_SAFE5V_MIN;
-	else
-		return vbus_voltage < PD_V_SINK_DISCONNECT_MAX;
+	return sm5803_check_vbus_level(port, level);
 }
 
 int pd_snk_is_vbus_provided(int port)
diff --git a/board/drawcia_riscv/battery.c b/board/drawcia_riscv/battery.c
index 4aa0f49043..074bc78d58 100644
--- a/board/drawcia_riscv/battery.c
+++ b/board/drawcia_riscv/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/drawcia_riscv/board.c b/board/drawcia_riscv/board.c
index e770d17818..cbc977d64b 100644
--- a/board/drawcia_riscv/board.c
+++ b/board/drawcia_riscv/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -42,7 +42,7 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
 
 #define INT_RECHECK_US 5000
 
@@ -165,48 +165,36 @@ static void pen_detect_interrupt(enum gpio_signal s)
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH0
-	},
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH2
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH3
-	},
-	[ADC_SUB_ANALOG] = {
-		.name = "SUB_ANALOG",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH13
-	},
-	[ADC_TEMP_SENSOR_3] = {
-		.name = "TEMP_SENSOR3",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH15
-	},
-	[ADC_TEMP_SENSOR_4] = {
-		.name = "TEMP_SENSOR4",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH16
-	},
+	[ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH0 },
+	[ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH2 },
+	[ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH3 },
+	[ADC_SUB_ANALOG] = { .name = "SUB_ANALOG",
+			     .factor_mul = ADC_MAX_MVOLT,
+			     .factor_div = ADC_READ_MAX + 1,
+			     .shift = 0,
+			     .channel = CHIP_ADC_CH13 },
+	[ADC_TEMP_SENSOR_3] = { .name = "TEMP_SENSOR3",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH15 },
+	[ADC_TEMP_SENSOR_4] = { .name = "TEMP_SENSOR4",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH16 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
@@ -255,19 +243,25 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 };
 
 /* USB Muxes */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+			},
 	},
 	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_SUB_USB_C1,
+				.i2c_addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	},
 };
 
@@ -280,17 +274,13 @@ static struct accelgyro_saved_data_t g_bma253_data;
 static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
 
 /* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, FLOAT_TO_FP(-1), 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
 
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
 /* Drivers */
 struct motion_sensor_t motion_sensors[] = {
@@ -496,8 +486,8 @@ __override void board_power_5v_enable(int enable)
 
 	if (board_get_charger_chip_count() > 1) {
 		if (sm5803_set_gpio0_level(1, !!enable))
-			CPRINTUSB("Failed to %sable sub rails!", enable ?
-								  "en" : "dis");
+			CPRINTUSB("Failed to %sable sub rails!",
+				  enable ? "en" : "dis");
 	}
 }
 
@@ -505,11 +495,11 @@ __override uint8_t board_get_usb_pd_port_count(void)
 {
 	enum fw_config_db db = get_cbi_fw_config_db();
 
-	if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI
-			|| db == DB_1A_HDMI_LTE)
+	if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI ||
+	    db == DB_1A_HDMI_LTE)
 		return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
-	else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A
-			|| db == DB_1C_1A_LTE)
+	else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A ||
+		 db == DB_1C_1A_LTE)
 		return CONFIG_USB_PD_PORT_MAX_COUNT;
 
 	ccprints("Unhandled DB configuration: %d", db);
@@ -520,11 +510,11 @@ __override uint8_t board_get_charger_chip_count(void)
 {
 	enum fw_config_db db = get_cbi_fw_config_db();
 
-	if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI
-			|| db == DB_1A_HDMI_LTE)
+	if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI ||
+	    db == DB_1A_HDMI_LTE)
 		return CHARGER_NUM - 1;
-	else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A
-			|| db == DB_1C_1A_LTE)
+	else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A ||
+		 db == DB_1C_1A_LTE)
 		return CHARGER_NUM;
 
 	ccprints("Unhandled DB configuration: %d", db);
@@ -629,33 +619,31 @@ __override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
 }
 
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq_hz = 10000,
-	}
-};
+const struct pwm_t pwm_channels[] = { [PWM_CH_KBLIGHT] = {
+					      .channel = 0,
+					      .flags = PWM_CONFIG_DSLEEP,
+					      .freq_hz = 10000,
+				      } };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
 /* Thermistors */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "Charger",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_3},
-	[TEMP_SENSOR_4] = {.name = "5V regular",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_4},
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "Charger",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
+	[TEMP_SENSOR_4] = { .name = "5V regular",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_4 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -685,9 +673,8 @@ __override void lid_angle_peripheral_enable(int enable)
 	}
 }
 
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
+__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+				       int *ki_div, int *kd, int *kd_div)
 {
 	*kp = 3;
 	*kp_div = 20;
@@ -706,14 +693,17 @@ __override void ocpc_get_pid_constants(int *kp, int *kp_div,
  * The connector has 24 pins total, and there is no pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-	{-1, -1}, {GPIO_KSO_H, 4}, {GPIO_KSO_H, 0}, {GPIO_KSO_H, 1},
-	{GPIO_KSO_H, 3}, {GPIO_KSO_H, 2}, {GPIO_KSO_L, 5}, {GPIO_KSO_L, 6},
-	{GPIO_KSO_L, 3}, {GPIO_KSO_L, 2}, {GPIO_KSI, 0}, {GPIO_KSO_L, 1},
-	{GPIO_KSO_L, 4}, {GPIO_KSI, 3}, {GPIO_KSI, 2}, {GPIO_KSO_L, 0},
-	{GPIO_KSI, 5}, {GPIO_KSI, 4}, {GPIO_KSO_L, 7}, {GPIO_KSI, 6},
-	{GPIO_KSI, 7}, {GPIO_KSI, 1}, {-1, -1}, {-1, -1}, {-1, -1},
+	{ -1, -1 },	   { GPIO_KSO_H, 4 }, { GPIO_KSO_H, 0 },
+	{ GPIO_KSO_H, 1 }, { GPIO_KSO_H, 3 }, { GPIO_KSO_H, 2 },
+	{ GPIO_KSO_L, 5 }, { GPIO_KSO_L, 6 }, { GPIO_KSO_L, 3 },
+	{ GPIO_KSO_L, 2 }, { GPIO_KSI, 0 },   { GPIO_KSO_L, 1 },
+	{ GPIO_KSO_L, 4 }, { GPIO_KSI, 3 },   { GPIO_KSI, 2 },
+	{ GPIO_KSO_L, 0 }, { GPIO_KSI, 5 },   { GPIO_KSI, 4 },
+	{ GPIO_KSO_L, 7 }, { GPIO_KSI, 6 },   { GPIO_KSI, 7 },
+	{ GPIO_KSI, 1 },   { -1, -1 },	      { -1, -1 },
+	{ -1, -1 },
 };
 
 const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 #endif
diff --git a/board/drawcia_riscv/board.h b/board/drawcia_riscv/board.h
index 45f16c9ac3..2867412cf8 100644
--- a/board/drawcia_riscv/board.h
+++ b/board/drawcia_riscv/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -37,20 +37,23 @@
 
 /* Charger */
 #define CONFIG_CHARGE_RAMP_HW
-#define CONFIG_CHARGER_SM5803		/* C0 and C1: Charger */
+#define CONFIG_CHARGER_SM5803 /* C0 and C1: Charger */
+#define PD_MAX_VOLTAGE_MV 15000
 #define CONFIG_USB_PD_VBUS_DETECT_CHARGER
 #define CONFIG_USB_PD_5V_CHARGER_CTRL
 #define CONFIG_CHARGER_OTG
-#undef  CONFIG_CHARGER_SINGLE_CHIP
+#undef CONFIG_CHARGER_SINGLE_CHIP
 #define CONFIG_OCPC
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr */
+#define CONFIG_OCPC_DEF_RBATT_MOHMS               \
+	21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr \
+	    */
 
 /* PWM */
 #define CONFIG_PWM
 
 /* Sensors */
-#define CONFIG_ACCEL_BMA255		/* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM	/* Base accel */
+#define CONFIG_ACCEL_BMA255 /* Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
 /* Sensors without hardware FIFO are in forced mode */
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
 
@@ -83,8 +86,8 @@
 
 /* TCPC */
 #define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP	/* C0: ITE EC TCPC */
-#define CONFIG_USB_PD_TCPM_PS8705	/* C1: PS8705 TCPC*/
+#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0: ITE EC TCPC */
+#define CONFIG_USB_PD_TCPM_PS8705 /* C1: PS8705 TCPC*/
 #define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1
 #define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
 #define CONFIG_USB_PD_TCPC_LOW_POWER
@@ -95,13 +98,16 @@
 #define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
 
 /* USB Mux and Retimer */
-#define CONFIG_USB_MUX_IT5205			/* C1: ITE Mux */
-#define I2C_PORT_USB_MUX I2C_PORT_USB_C0	/* Required for ITE Mux */
+#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */
 
 /* USB Type A Features */
 #define USB_PORT_COUNT 1
 #define CONFIG_USB_PORT_POWER_DUMB
 
+/* Reduce flash image footprint */
+#undef CONFIG_CMD_ACCELS
+
 #ifndef __ASSEMBLER__
 
 #include "gpio_signal.h"
@@ -119,21 +125,16 @@ enum pwm_channel {
 };
 
 /* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
 /* ADC channels */
 enum adc_channel {
-	ADC_VSNS_PP3300_A,     /* ADC0 */
-	ADC_TEMP_SENSOR_1,     /* ADC2 */
-	ADC_TEMP_SENSOR_2,     /* ADC3 */
-	ADC_SUB_ANALOG,        /* ADC13 */
-	ADC_TEMP_SENSOR_3,     /* ADC15 */
-	ADC_TEMP_SENSOR_4,     /* ADC16 */
+	ADC_VSNS_PP3300_A, /* ADC0 */
+	ADC_TEMP_SENSOR_1, /* ADC2 */
+	ADC_TEMP_SENSOR_2, /* ADC3 */
+	ADC_SUB_ANALOG, /* ADC13 */
+	ADC_TEMP_SENSOR_3, /* ADC15 */
+	ADC_TEMP_SENSOR_4, /* ADC16 */
 	ADC_CH_COUNT
 };
 
diff --git a/board/drawcia_riscv/build.mk b/board/drawcia_riscv/build.mk
index cf62dfc823..b63b7a58b9 100644
--- a/board/drawcia_riscv/build.mk
+++ b/board/drawcia_riscv/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/drawcia_riscv/cbi_ssfc.c b/board/drawcia_riscv/cbi_ssfc.c
index c4b859f133..81f3ee0dad 100644
--- a/board/drawcia_riscv/cbi_ssfc.c
+++ b/board/drawcia_riscv/cbi_ssfc.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
 
 enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
 {
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
 }
 
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
 {
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
 }
diff --git a/board/drawcia_riscv/cbi_ssfc.h b/board/drawcia_riscv/cbi_ssfc.h
index 935049b6ae..bf8853a43a 100644
--- a/board/drawcia_riscv/cbi_ssfc.h
+++ b/board/drawcia_riscv/cbi_ssfc.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -56,5 +56,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
  */
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
 
-
 #endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/drawcia_riscv/ec.tasklist b/board/drawcia_riscv/ec.tasklist
index 5c9a2d1a01..c13df44543 100644
--- a/board/drawcia_riscv/ec.tasklist
+++ b/board/drawcia_riscv/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/drawcia_riscv/gpio.inc b/board/drawcia_riscv/gpio.inc
index cf0e3377cd..ad20442673 100644
--- a/board/drawcia_riscv/gpio.inc
+++ b/board/drawcia_riscv/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/drawcia_riscv/led.c b/board/drawcia_riscv/led.c
index d13862cdcd..3cb7cb835e 100644
--- a/board/drawcia_riscv/led.c
+++ b/board/drawcia_riscv/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,10 +18,8 @@
 #define POWER_LED_ON 0
 #define POWER_LED_OFF 1
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -29,7 +27,7 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static int led_set_color_battery(enum led_color color)
@@ -116,7 +114,6 @@ static void led_set_battery(void)
 {
 	static int battery_ticks;
 	static int power_ticks;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
@@ -127,9 +124,9 @@ static void led_set_battery(void)
 	 */
 	if (get_cbi_fw_config_tablet_mode() == TABLET_MODE_ABSENT) {
 		if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
-			charge_get_state() != PWR_STATE_CHARGE) {
-			led_set_color_battery(power_ticks++ & 0x2 ?
-						  LED_WHITE : LED_OFF);
+		    charge_get_state() != PWR_STATE_CHARGE) {
+			led_set_color_battery(power_ticks++ & 0x2 ? LED_WHITE :
+								    LED_OFF);
 			return;
 		}
 	}
@@ -158,18 +155,18 @@ static void led_set_battery(void)
 			led_set_color_battery(LED_OFF);
 		break;
 	case PWR_STATE_ERROR:
-		led_set_color_battery(
-			(battery_ticks % 0x2) ? LED_WHITE : LED_OFF);
+		led_set_color_battery((battery_ticks % 0x2) ? LED_WHITE :
+							      LED_OFF);
 		break;
 	case PWR_STATE_CHARGE_NEAR_FULL:
 		led_set_color_battery(LED_WHITE);
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			led_set_color_battery(
-				(battery_ticks & 0x2) ? LED_AMBER : LED_OFF);
-		else
-			led_set_color_battery(LED_WHITE);
+		led_set_color_battery(LED_WHITE);
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		led_set_color_battery((battery_ticks & 0x2) ? LED_AMBER :
+							      LED_OFF);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
@@ -186,8 +183,7 @@ static void led_set_power(void)
 	if (chipset_in_state(CHIPSET_STATE_ON))
 		led_set_color_power(LED_WHITE);
 	else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-		led_set_color_power(
-			(power_tick & 0x2) ? LED_WHITE : LED_OFF);
+		led_set_color_power((power_tick & 0x2) ? LED_WHITE : LED_OFF);
 	else
 		led_set_color_power(LED_OFF);
 }
diff --git a/board/drawcia_riscv/usb_pd_policy.c b/board/drawcia_riscv/usb_pd_policy.c
index 3ff7152541..8a2c07c575 100644
--- a/board/drawcia_riscv/usb_pd_policy.c
+++ b/board/drawcia_riscv/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,8 +13,8 @@
 #include "driver/tcpm/tcpci.h"
 #include "usb_pd.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
@@ -65,18 +65,7 @@ int pd_set_power_supply_ready(int port)
 
 __override bool pd_check_vbus_level(int port, enum vbus_level level)
 {
-	int vbus_voltage;
-
-	/* If we're unable to speak to the charger, best to guess false */
-	if (charger_get_vbus_voltage(port, &vbus_voltage))
-		return false;
-
-	if (level == VBUS_SAFE0V)
-		return vbus_voltage < PD_V_SAFE0V_MAX;
-	else if (level == VBUS_PRESENT)
-		return vbus_voltage > PD_V_SAFE5V_MIN;
-	else
-		return vbus_voltage < PD_V_SINK_DISCONNECT_MAX;
+	return sm5803_check_vbus_level(port, level);
 }
 
 int pd_snk_is_vbus_provided(int port)
diff --git a/board/driblee/battery.c b/board/driblee/battery.c
index 19f0312305..d73bc104ac 100644
--- a/board/driblee/battery.c
+++ b/board/driblee/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -638,8 +638,8 @@ const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_BYD_1VX1H;
 int charger_profile_override(struct charge_state_data *curr)
 {
 	if (chipset_in_state(CHIPSET_STATE_ON)) {
-		curr->requested_current = MIN(curr->requested_current,
-				CHARGING_CURRENT_1100MA);
+		curr->requested_current =
+			MIN(curr->requested_current, CHARGING_CURRENT_1100MA);
 	}
 
 	return 0;
diff --git a/board/driblee/board.c b/board/driblee/board.c
index 5cf9b686ac..30075e683e 100644
--- a/board/driblee/board.c
+++ b/board/driblee/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -41,13 +41,13 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 #define INT_RECHECK_US 5000
 
-#define ADC_VOL_UP_MASK     BIT(0)
-#define ADC_VOL_DOWN_MASK   BIT(1)
+#define ADC_VOL_UP_MASK BIT(0)
+#define ADC_VOL_DOWN_MASK BIT(1)
 
 static uint8_t new_adc_key_state;
 
@@ -77,8 +77,8 @@ static const struct ec_response_keybd_config driblee_keybd = {
 	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
 };
 
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	return &driblee_keybd;
 }
@@ -119,7 +119,6 @@ static void usb_c0_interrupt(enum gpio_signal s)
 
 	/* Check the line again in 5ms */
 	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-
 }
 
 static void sub_hdmi_hpd_interrupt(enum gpio_signal s)
@@ -165,22 +164,22 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* Thermistors */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Charger",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Charger",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_A \
-	{ \
+#define THERMAL_A                \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = 0, \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
@@ -197,8 +196,8 @@ __maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_B \
-	{ \
+#define THERMAL_B                \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = 0, \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(73), \
@@ -271,13 +270,11 @@ int board_is_sourcing_vbus(int port)
 
 	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
 	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
-
 }
 
 int board_set_active_charge_port(int port)
 {
-	int is_real_port = (port >= 0 &&
-			    port < board_get_usb_pd_port_count());
+	int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count());
 	int i;
 	int old_port;
 
@@ -328,7 +325,7 @@ int board_set_active_charge_port(int port)
 
 	/* Enable requested charge port. */
 	if (raa489000_enable_asgate(port, true) ||
-		tcpc_write(port, TCPC_REG_COMMAND,
+	    tcpc_write(port, TCPC_REG_COMMAND,
 		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
 		CPRINTS("p%d: sink path enable failed.", port);
 		charger_discharge_on_ac(0);
@@ -341,8 +338,8 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
 
@@ -398,9 +395,8 @@ static void hdmi_disable(void)
 }
 DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, hdmi_disable, HOOK_PRIO_DEFAULT);
 
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
+__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+				       int *ki_div, int *kd, int *kd_div)
 {
 	*kp = 1;
 	*kp_div = 20;
@@ -444,12 +440,15 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
-		.driver = &pi3usb3x532_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
+				.driver = &pi3usb3x532_usb_mux_driver,
+			},
 	},
 };
 
diff --git a/board/driblee/board.h b/board/driblee/board.h
index e1bd9d1dca..f6a3ac9130 100644
--- a/board/driblee/board.h
+++ b/board/driblee/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,6 +25,7 @@
 
 /* Charger */
 #define CONFIG_CHARGER_RAA489000
+#define PD_MAX_VOLTAGE_MV 20000
 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 #define CONFIG_CHARGER_SENSE_RESISTOR 10
 #undef CONFIG_CMD_CHARGER_DUMP
@@ -49,7 +50,7 @@
 #define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
 
 /* PWM */
-#define NPCX7_PWM1_SEL    1  /* GPIO C2 is used as PWM1. */
+#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */
 
 /* Temp sensor */
 #define CONFIG_TEMP_SENSOR
@@ -86,16 +87,16 @@
 #define CONFIG_USB_PD_5V_EN_CUSTOM
 
 /* I2C configuration */
-#define I2C_PORT_EEPROM     NPCX_I2C_PORT7_0
-#define I2C_PORT_BATTERY    NPCX_I2C_PORT5_0
-#define I2C_PORT_SENSOR     NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0     NPCX_I2C_PORT1_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
 #define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_MUX    I2C_PORT_USB_C0
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0
 /* TODO(b:147440290): Need to handle multiple charger ICs */
-#define I2C_PORT_CHARGER    I2C_PORT_USB_C0
+#define I2C_PORT_CHARGER I2C_PORT_USB_C0
 
-#define I2C_PORT_ACCEL      I2C_PORT_SENSOR
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
 
 #define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */
 
@@ -111,17 +112,13 @@
 #include "registers.h"
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_1,     /* ADC0 */
-	ADC_TEMP_SENSOR_2,     /* ADC1 */
-	ADC_VSNS_PP3300_A,     /* ADC9 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
+	ADC_VSNS_PP3300_A, /* ADC9 */
 	ADC_CH_COUNT
 };
 
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_COUNT
-};
+enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
diff --git a/board/driblee/build.mk b/board/driblee/build.mk
index b012d8d502..eb422dae93 100644
--- a/board/driblee/build.mk
+++ b/board/driblee/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/driblee/cbi_ssfc.c b/board/driblee/cbi_ssfc.c
index c4b859f133..81f3ee0dad 100644
--- a/board/driblee/cbi_ssfc.c
+++ b/board/driblee/cbi_ssfc.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
 
 enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
 {
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
 }
 
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
 {
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
 }
diff --git a/board/driblee/cbi_ssfc.h b/board/driblee/cbi_ssfc.h
index 935049b6ae..bf8853a43a 100644
--- a/board/driblee/cbi_ssfc.h
+++ b/board/driblee/cbi_ssfc.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -56,5 +56,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
  */
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
 
-
 #endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/driblee/ec.tasklist b/board/driblee/ec.tasklist
index 0025c2985b..386e8625b3 100644
--- a/board/driblee/ec.tasklist
+++ b/board/driblee/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/driblee/gpio.inc b/board/driblee/gpio.inc
index 82ba0d67bc..acd6a33852 100644
--- a/board/driblee/gpio.inc
+++ b/board/driblee/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/driblee/led.c b/board/driblee/led.c
index cd34613a7c..7aa983ea79 100644
--- a/board/driblee/led.c
+++ b/board/driblee/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,23 +19,32 @@ __override const int led_charge_lvl_1 = 10;
 __override const int led_charge_lvl_2 = 100;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_S5]     = {{LED_OFF,	     LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     1 * LED_ONE_SEC },
+					   { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_WHITE,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 BUILD_ASSERT(ARRAY_SIZE(led_bat_state_table) == LED_NUM_STATES);
 
 const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
diff --git a/board/driblee/usb_pd_policy.c b/board/driblee/usb_pd_policy.c
index 19dd01d37b..157f4be2cb 100644
--- a/board/driblee/usb_pd_policy.c
+++ b/board/driblee/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,8 @@
 #include "driver/charger/isl923x_public.h"
 #include "usb_pd.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
diff --git a/board/drobit/battery.c b/board/drobit/battery.c
index f8f3eb296f..0db543a12f 100644
--- a/board/drobit/battery.c
+++ b/board/drobit/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/drobit/board.c b/board/drobit/board.c
index fdfab38b52..19b5162092 100644
--- a/board/drobit/board.c
+++ b/board/drobit/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -41,7 +41,7 @@
 
 #include "gpio_list.h" /* Must come after other header files. */
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 /* Keyboard scan setting */
 __override struct keyboard_scan_config keyscan_config = {
@@ -76,8 +76,8 @@ static const struct ec_response_keybd_config drobit_kb = {
 	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
 };
 
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	return &drobit_kb;
 }
@@ -95,7 +95,7 @@ union volteer_cbi_fw_config fw_config_defaults = {
 
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
@@ -131,8 +131,8 @@ const struct fan_t fans[FAN_CH_COUNT] = {
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CPU \
-	{ \
+#define THERMAL_CPU              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(72), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
@@ -159,8 +159,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_INDUCTOR \
-	{ \
+#define THERMAL_INDUCTOR         \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(72), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
@@ -363,33 +363,43 @@ BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
 
 /******************************************************************************/
 /* USBC mux configuration - Tiger Lake includes internal mux */
-struct usb_mux usbc0_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+struct usb_mux_chain usbc0_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
-struct usb_mux usbc1_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+struct usb_mux_chain usbc1_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
 
-struct usb_mux usb_muxes[] = {
+struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.next_mux = &usbc0_tcss_usb_mux,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_1_MIX,
-		.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_1_MIX,
+			.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc0_tcss_usb_mux,
 	},
 	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.next_mux = &usbc1_tcss_usb_mux,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_1_MIX,
-		.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_1_MIX,
+			.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc1_tcss_usb_mux,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
@@ -467,8 +477,8 @@ DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
 
 /******************************************************************************/
 /* Set the charge limit based upon desired maximum. */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	/*
 	 * Limit the input current to 98% negotiated limit,
@@ -476,6 +486,5 @@ void board_set_charge_limit(int port, int supplier, int charge_ma,
 	 */
 	charge_ma = charge_ma * 98 / 100;
 	charge_set_input_current_limit(
-			MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT),
-			charge_mv);
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
diff --git a/board/drobit/board.h b/board/drobit/board.h
index 12cfe834c6..d6fda98f3d 100644
--- a/board/drobit/board.h
+++ b/board/drobit/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -29,7 +29,7 @@
 
 /* LED defines */
 #define CONFIG_LED_ONOFF_STATES
-#define CONFIG_LED_ONOFF_STATES_BAT_LOW	10
+#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
 
 /* Keyboard features */
 #define CONFIG_KEYBOARD_VIVALDI
@@ -42,20 +42,20 @@
 #undef CONFIG_ACCEL_FIFO_SIZE
 
 /* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
 
 /* TODO: b/144165680 - measure and check these values on Volteer */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
 
 /*
  * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
  * cables only support up to 60W.
  */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 #define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
 #ifdef BOARD_DROBIT_ECMODEENTRY
@@ -68,11 +68,11 @@
 /* Enabling USB4 mode */
 #define CONFIG_USB_PD_USB4
 
-#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR	0x40
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x41
+#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x40
+#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x41
 
 /* USB Type A Features */
-#define USB_PORT_COUNT			1
+#define USB_PORT_COUNT 1
 #define CONFIG_USB_PORT_POWER_DUMB
 
 /* USBC PPC*/
@@ -87,8 +87,8 @@
 /* Fan features */
 
 /* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 
 /*
  * Macros for GPIO signals used in common code that don't match the
@@ -96,42 +96,41 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_DSW_PWROK		GPIO_EC_PCH_DSW_PWROK
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_LID_OPEN GPIO_EC_LID_OPEN
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL
 
 /* I2C Bus Configuration */
 #define CONFIG_I2C
-#define I2C_PORT_USB_C1_MIX	NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_1_MIX	NPCX_I2C_PORT3_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
+#define I2C_PORT_USB_C1_MIX NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT3_0
+#define I2C_PORT_POWER NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
 
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
+#define I2C_PORT_BATTERY I2C_PORT_POWER
+#define I2C_PORT_CHARGER I2C_PORT_EEPROM
 
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 #define CONFIG_I2C_CONTROLLER
 
-
 #ifndef __ASSEMBLER__
 
 #include "gpio_signal.h"
@@ -142,11 +141,7 @@ enum battery_type {
 	BATTERY_TYPE_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_FAN = 0,
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_FAN = 0, PWM_CH_KBLIGHT, PWM_CH_COUNT };
 
 enum sensor_id {
 	LID_ACCEL = 0,
@@ -155,11 +150,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 void board_reset_pd_mcu(void);
 
diff --git a/board/drobit/build.mk b/board/drobit/build.mk
index 43b40c644c..d590255d2a 100644
--- a/board/drobit/build.mk
+++ b/board/drobit/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/drobit/ec.tasklist b/board/drobit/ec.tasklist
index c1b0295d37..a1b5d30d93 100644
--- a/board/drobit/ec.tasklist
+++ b/board/drobit/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/drobit/gpio.inc b/board/drobit/gpio.inc
index 6bacab4474..2057cfd27a 100644
--- a/board/drobit/gpio.inc
+++ b/board/drobit/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,7 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
diff --git a/board/drobit/led.c b/board/drobit/led.c
index 47c3cca5b7..bb712a8fe0 100644
--- a/board/drobit/led.c
+++ b/board/drobit/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,28 +9,37 @@
 #include "led_common.h"
 #include "led_onoff_states.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
 __override const int led_charge_lvl_1;
 __override const int led_charge_lvl_2 = 95;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]       = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]       = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]	     = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_WHITE,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
 const enum ec_led_id supported_led_ids[] = {
 	EC_LED_ID_BATTERY_LED,
diff --git a/board/eldrid/battery.c b/board/eldrid/battery.c
index 3c9f2b0c21..6f9e6df5af 100644
--- a/board/eldrid/battery.c
+++ b/board/eldrid/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -100,7 +100,9 @@ __override bool board_battery_is_initialized(void)
 	bool batt_initialization_state;
 	int batt_status;
 
-	batt_initialization_state = (battery_status(&batt_status) ? false :
-		!!(batt_status & STATUS_INITIALIZED));
+	batt_initialization_state =
+		(battery_status(&batt_status) ?
+			 false :
+			 !!(batt_status & STATUS_INITIALIZED));
 	return batt_initialization_state;
 }
diff --git a/board/eldrid/board.c b/board/eldrid/board.c
index b3d1bb8293..717878bc95 100644
--- a/board/eldrid/board.c
+++ b/board/eldrid/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -48,7 +48,7 @@
 
 #include "gpio_list.h" /* Must come after other header files. */
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 /* Keyboard scan setting */
 __override struct keyboard_scan_config keyscan_config = {
@@ -94,7 +94,7 @@ static void board_charger_config(void)
 		       ISL9241_REG_CONTROL1, &reg) == EC_SUCCESS) {
 		reg |= ISL9241_CONTROL1_PSYS;
 		if (i2c_write16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
-			    ISL9241_REG_CONTROL1, reg))
+				ISL9241_REG_CONTROL1, reg))
 			CPRINTS("Failed to set isl9241");
 	}
 
@@ -105,7 +105,7 @@ static void board_charger_config(void)
 		       ISL9241_REG_CONTROL2, &reg) == EC_SUCCESS) {
 		reg &= ~ISL9241_CONTROL2_PROCHOT_DEBOUNCE_MASK;
 		if (i2c_write16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
-			    ISL9241_REG_CONTROL2, reg))
+				ISL9241_REG_CONTROL2, reg))
 			CPRINTS("Failed to set isl9241");
 	}
 
@@ -116,7 +116,7 @@ static void board_charger_config(void)
 		       ISL9241_REG_CONTROL4, &reg) == EC_SUCCESS) {
 		reg |= ISL9241_CONTROL4_PSYS_RSENSE_RATIO;
 		if (i2c_write16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS,
-			    ISL9241_REG_CONTROL4, reg))
+				ISL9241_REG_CONTROL4, reg))
 			CPRINTS("Failed to set isl9241");
 	}
 }
@@ -166,12 +166,12 @@ __override bool board_is_tbt_usb4_port(int port)
 	 * TODO (b/147732807): All the USB-C ports need to support same
 	 * features. Need to fix once USB-C feature set is known for Volteer.
 	 */
-	return ((port == USBC_PORT_C1)
-		&& ((usb_db == DB_USB4_GEN2) || (usb_db == DB_USB4_GEN3)));
+	return ((port == USBC_PORT_C1) &&
+		((usb_db == DB_USB4_GEN2) || (usb_db == DB_USB4_GEN3)));
 }
 
 __override void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+				       int max_ma, int charge_mv)
 {
 	/*
 	 * b/166728543
@@ -188,9 +188,8 @@ __override void board_set_charge_limit(int port, int supplier, int charge_ma,
 	 */
 	charge_ma = charge_ma * 90 / 100;
 
-	charge_set_input_current_limit(MAX(charge_ma,
-					CONFIG_CHARGER_INPUT_CURRENT),
-					charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 /******************************************************************************/
@@ -198,7 +197,7 @@ __override void board_set_charge_limit(int port, int supplier, int charge_ma,
 
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
@@ -326,24 +325,33 @@ static const struct tcpc_config_t tcpc_config_p1_usb3 = {
  * virtual_usb_mux_driver so the AP gets notified of mux changes and updates
  * the TCSS configuration on state changes.
  */
-static const struct usb_mux usbc1_usb3_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	.next_mux = NULL,
+static const struct usb_mux_chain usbc1_usb3_db_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
+	.next = NULL,
 };
 
-static const struct usb_mux mux_config_p1_usb3_active = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-	.next_mux = &usbc1_usb3_db_retimer,
+static const struct usb_mux_chain mux_config_p1_usb3_active = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+	.next = &usbc1_usb3_db_retimer,
 };
 
-static const struct usb_mux mux_config_p1_usb3_passive = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+static const struct usb_mux_chain mux_config_p1_usb3_passive = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
 
 /******************************************************************************/
@@ -360,8 +368,7 @@ static void ps8815_reset(void)
 	int val;
 
 	gpio_set_level(ps8xxx_rst_odl, 0);
-	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS,
-			   PS8815_PWR_H_RST_H_DELAY_MS));
+	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS));
 	gpio_set_level(ps8xxx_rst_odl, 1);
 	msleep(PS8815_FW_INIT_DELAY_MS);
 
@@ -372,16 +379,16 @@ static void ps8815_reset(void)
 
 	CPRINTS("%s: patching ps8815 registers", __func__);
 
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
+	if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) ==
+	    EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f was %02x", val);
 
-	if (i2c_write8(I2C_PORT_USB_C1,
-		       PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) == EC_SUCCESS)
+	if (i2c_write8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f,
+		       0x31) == EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f set to 0x31");
 
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
+	if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) ==
+	    EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f now %02x", val);
 }
 
@@ -393,8 +400,9 @@ void board_reset_pd_mcu(void)
 	/* Daughterboard specific reset for port 1 */
 	if (usb_db == DB_USB3_ACTIVE) {
 		ps8815_reset();
-		usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED |
-						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+		usb_mux_hpd_update(USBC_PORT_C1,
+				   USB_PD_MUX_HPD_LVL_DEASSERTED |
+					   USB_PD_MUX_HPD_IRQ_DEASSERTED);
 	}
 }
 
@@ -433,8 +441,7 @@ static void config_port_discrete_tcpc(int port)
 	 */
 	if (get_board_id() >= 1) {
 		CPRINTS("C%d: RT1715", port);
-		tcpc_config[port].i2c_info.addr_flags =
-			RT1715_I2C_ADDR_FLAGS;
+		tcpc_config[port].i2c_info.addr_flags = RT1715_I2C_ADDR_FLAGS;
 		tcpc_config[port].drv = &rt1715_tcpm_drv;
 		return;
 	}
@@ -553,16 +560,20 @@ BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
 
 /******************************************************************************/
 /* USBC mux configuration - Tiger Lake includes internal mux */
-struct usb_mux usb_muxes[] = {
+struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 	},
 	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
diff --git a/board/eldrid/board.h b/board/eldrid/board.h
index df785a5573..1bbe183425 100644
--- a/board/eldrid/board.h
+++ b/board/eldrid/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -40,7 +40,7 @@
  * TODO(b/170966461): Re-enable Vivaldi keyboard once
  * 8042 and MKBP drivers can coexist.
  */
-#undef  CONFIG_KEYBOARD_VIVALDI
+#undef CONFIG_KEYBOARD_VIVALDI
 
 /* Sensors */
 /* BMA253 accelerometer in base */
@@ -52,37 +52,36 @@
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 
 /* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
-	(BIT(LID_ACCEL))
+#define CONFIG_ACCEL_FORCE_MODE_MASK (BIT(LID_ACCEL))
 
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE		BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID		LID_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
 
 /* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
 
 /* TODO: b/144165680 - measure and check these values on Volteer */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
 
 /*
  * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
  * cables only support up to 60W.
  */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* USB Type A Features */
-#define USB_PORT_COUNT			1
+#define USB_PORT_COUNT 1
 #define CONFIG_USB_PORT_POWER_DUMB
 
 /* USBC PPC*/
-#define CONFIG_USBC_PPC_SN5S330		/* USBC port C0 */
-#define CONFIG_USBC_PPC_SYV682X		/* USBC port C1 */
+#define CONFIG_USBC_PPC_SN5S330 /* USBC port C0 */
+#define CONFIG_USBC_PPC_SYV682X /* USBC port C1 */
 
 /* BC 1.2 */
 
@@ -92,8 +91,8 @@
 #define CONFIG_CUSTOM_FAN_CONTROL
 
 /* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 
 /* Retimer */
 #undef CONFIG_USBC_RETIMER_INTEL_BB
@@ -105,44 +104,43 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_DSW_PWROK		GPIO_EC_PCH_DSW_PWROK
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_LID_OPEN GPIO_EC_LID_OPEN
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
 
 /* I2C Bus Configuration */
 #define CONFIG_I2C
-#define I2C_PORT_ACCEL		I2C_PORT_SENSOR
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0
+#define I2C_PORT_POWER NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
 
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
+#define I2C_PORT_BATTERY I2C_PORT_POWER
+#define I2C_PORT_CHARGER I2C_PORT_EEPROM
 
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 #define CONFIG_I2C_CONTROLLER
 
-
 #ifndef __ASSEMBLER__
 
 #include "gpio_signal.h"
@@ -168,11 +166,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 void board_reset_pd_mcu(void);
 
diff --git a/board/eldrid/build.mk b/board/eldrid/build.mk
index 868a463932..91041efa43 100644
--- a/board/eldrid/build.mk
+++ b/board/eldrid/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/eldrid/ec.tasklist b/board/eldrid/ec.tasklist
index 3e20d8ae39..c29125d517 100644
--- a/board/eldrid/ec.tasklist
+++ b/board/eldrid/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/eldrid/gpio.inc b/board/eldrid/gpio.inc
index 9d5b374c40..08d754b366 100644
--- a/board/eldrid/gpio.inc
+++ b/board/eldrid/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,7 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
diff --git a/board/eldrid/led.c b/board/eldrid/led.c
index 26526e0b76..797b6d4bda 100644
--- a/board/eldrid/led.c
+++ b/board/eldrid/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,36 +27,39 @@ __override const int led_charge_lvl_1 = 5;
 __override const int led_charge_lvl_2 = 95;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {
-		{EC_LED_COLOR_WHITE, 0.4 * LED_ONE_SEC},
-		{LED_OFF,            0.4 * LED_ONE_SEC}
-	},
-	[STATE_FACTORY_TEST]         = {
-		{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-		{LED_OFF,            1 * LED_ONE_SEC}
-	},
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_WHITE,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_WHITE,
+					    0.4 * LED_ONE_SEC },
+					  { LED_OFF, 0.4 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 1 * LED_ONE_SEC } },
+	};
 
 __override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           =  {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   =  {{EC_LED_COLOR_WHITE,  1 * LED_ONE_SEC},
-		{LED_OFF,	           1 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE,  1 * LED_ONE_SEC},
-		{LED_OFF,	           6 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {
-		{LED_OFF,             LED_INDEFINITE} },
-};
-
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 1 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    1 * LED_ONE_SEC },
+						  { LED_OFF,
+						    6 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
 const enum ec_led_id supported_led_ids[] = {
 	EC_LED_ID_BATTERY_LED,
@@ -80,10 +83,10 @@ __override void led_set_color_battery(enum ec_led_colors color)
 			side_select_duty = 100;
 			break;
 		default:
-		/*
-		 * We need to turn off led here since curr.ac won't update
-		 * immediately but led will update every 200ms.
-		 */
+			/*
+			 * We need to turn off led here since curr.ac won't
+			 * update immediately but led will update every 200ms.
+			 */
 			side_select_duty = 50;
 			color = LED_OFF;
 		}
diff --git a/board/eldrid/sensors.c b/board/eldrid/sensors.c
index a9248938a3..538cacb985 100644
--- a/board/eldrid/sensors.c
+++ b/board/eldrid/sensors.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -30,17 +30,13 @@ static struct accelgyro_saved_data_t g_bma253_data;
 static struct bmi_drv_data_t g_bmi160_data;
 
 /* Rotation matrix for the lid accelerometer */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					     { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+				       { 0, FLOAT_TO_FP(1), 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
diff --git a/board/eldrid/thermal.c b/board/eldrid/thermal.c
index 3f20b16d70..5ce7b362fc 100644
--- a/board/eldrid/thermal.c
+++ b/board/eldrid/thermal.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,8 +15,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_THERMAL, outstr)
-#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args)
-
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
 
 /******************************************************************************/
 /* EC thermal management configuration */
@@ -30,8 +29,8 @@
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CPU \
-	{ \
+#define THERMAL_CPU              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
@@ -56,8 +55,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_INDUCTOR \
-	{ \
+#define THERMAL_INDUCTOR         \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
@@ -102,39 +101,39 @@ struct fan_step {
 static const struct fan_step fan_table[] = {
 	{
 		/* level 0 */
-		.on = {-1, -1, 44, -1},
-		.off = {-1, -1, 0, -1},
-		.rpm = {0},
+		.on = { -1, -1, 44, -1 },
+		.off = { -1, -1, 0, -1 },
+		.rpm = { 0 },
 	},
 	{
 		/* level 1 */
-		.on = {-1, -1, 46, -1},
-		.off = {-1, -1, 44, -1},
-		.rpm = {3200},
+		.on = { -1, -1, 46, -1 },
+		.off = { -1, -1, 44, -1 },
+		.rpm = { 3200 },
 	},
 	{
 		/* level 2 */
-		.on = {-1, -1, 50, -1},
-		.off = {-1, -1, 45, -1},
-		.rpm = {3600},
+		.on = { -1, -1, 50, -1 },
+		.off = { -1, -1, 45, -1 },
+		.rpm = { 3600 },
 	},
 	{
 		/* level 3 */
-		.on = {-1, -1, 54, -1},
-		.off = {-1, -1, 49, -1},
-		.rpm = {4100},
+		.on = { -1, -1, 54, -1 },
+		.off = { -1, -1, 49, -1 },
+		.rpm = { 4100 },
 	},
 	{
 		/* level 4 */
-		.on = {-1, -1, 58, -1},
-		.off = {-1, -1, 53, -1},
-		.rpm = {4900},
+		.on = { -1, -1, 58, -1 },
+		.off = { -1, -1, 53, -1 },
+		.rpm = { 4900 },
 	},
 	{
 		/* level 5 */
-		.on = {-1, -1, 60, -1},
-		.off = {-1, -1, 57, -1},
-		.rpm = {5200},
+		.on = { -1, -1, 60, -1 },
+		.off = { -1, -1, 57, -1 },
+		.rpm = { 5200 },
 	},
 };
 
@@ -162,16 +161,16 @@ int fan_table_to_rpm(int fan, int *temp)
 	if (temp[TEMP_SENSOR_3_DDR_SOC] < prev_temp[TEMP_SENSOR_3_DDR_SOC]) {
 		for (i = current_level; i > 0; i--) {
 			if (temp[TEMP_SENSOR_3_DDR_SOC] <
-				fan_table[i].off[TEMP_SENSOR_3_DDR_SOC])
+			    fan_table[i].off[TEMP_SENSOR_3_DDR_SOC])
 				current_level = i - 1;
 			else
 				break;
 		}
 	} else if (temp[TEMP_SENSOR_3_DDR_SOC] >
-		prev_temp[TEMP_SENSOR_3_DDR_SOC]) {
+		   prev_temp[TEMP_SENSOR_3_DDR_SOC]) {
 		for (i = current_level; i < num_fan_levels; i++) {
 			if (temp[TEMP_SENSOR_3_DDR_SOC] >
-				fan_table[i].on[TEMP_SENSOR_3_DDR_SOC])
+			    fan_table[i].on[TEMP_SENSOR_3_DDR_SOC])
 				current_level = i;
 			else
 				break;
@@ -207,8 +206,7 @@ void board_override_fan_control(int fan, int *temp)
 {
 	if (chipset_in_state(CHIPSET_STATE_ON)) {
 		fan_set_rpm_mode(FAN_CH(fan), 1);
-		fan_set_rpm_target(FAN_CH(fan),
-			fan_table_to_rpm(fan, temp));
+		fan_set_rpm_target(FAN_CH(fan), fan_table_to_rpm(fan, temp));
 	} else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
 		/* Stop fan when enter S0ix */
 		fan_set_rpm_mode(FAN_CH(fan), 1);
diff --git a/board/elemi/battery.c b/board/elemi/battery.c
index 602176b718..f24c4c6847 100644
--- a/board/elemi/battery.c
+++ b/board/elemi/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/elemi/board.c b/board/elemi/board.c
index 1aaf5e1d95..6b166e1206 100644
--- a/board/elemi/board.c
+++ b/board/elemi/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -42,7 +42,7 @@
 
 #include "gpio_list.h" /* Must come after other header files. */
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 /* Keyboard scan setting */
 __override struct keyboard_scan_config keyscan_config = {
@@ -72,7 +72,7 @@ union volteer_cbi_fw_config fw_config_defaults = {
 
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
@@ -101,8 +101,8 @@ const struct fan_t fans[FAN_CH_COUNT] = {
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CPU \
-	{ \
+#define THERMAL_CPU              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(68), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(70), \
@@ -118,8 +118,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CHARGER \
-	{ \
+#define THERMAL_CHARGER          \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(78), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
@@ -136,8 +136,8 @@ __maybe_unused static const struct ec_thermal_config thermal_charger =
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_REGULATOR \
-	{ \
+#define THERMAL_REGULATOR        \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(68), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(70), \
@@ -248,8 +248,8 @@ DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, kb_backlight_disable, HOOK_PRIO_DEFAULT);
 __override void board_ps8xxx_tcpc_init(int port)
 {
 	/* b/189587527: Set Displayport EQ loss up to 10dB */
-	tcpc_addr_write(port, PS8XXX_I2C_ADDR1_P1_FLAGS,
-		PS8815_REG_DP_EQ_SETTING,
+	tcpc_addr_write(
+		port, PS8XXX_I2C_ADDR1_P1_FLAGS, PS8815_REG_DP_EQ_SETTING,
 		PS8815_DPEQ_LOSS_UP_10DB << PS8815_REG_DP_EQ_COMP_SHIFT);
 }
 
@@ -258,11 +258,14 @@ __override void board_ps8xxx_tcpc_init(int port)
  * virtual_usb_mux_driver so the AP gets notified of mux changes and updates
  * the TCSS configuration on state changes.
  */
-static const struct usb_mux usbc1_usb3_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	.next_mux = NULL,
+static const struct usb_mux_chain usbc1_usb3_db_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
+	.next = NULL,
 };
 
 /******************************************************************************/
@@ -277,8 +280,7 @@ static void ps8815_reset(void)
 	int val;
 
 	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 0);
-	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS,
-			   PS8815_PWR_H_RST_H_DELAY_MS));
+	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS));
 	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 1);
 	msleep(PS8815_FW_INIT_DELAY_MS);
 
@@ -289,16 +291,16 @@ static void ps8815_reset(void)
 
 	CPRINTS("%s: patching ps8815 registers", __func__);
 
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
+	if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) ==
+	    EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f was %02x", val);
 
-	if (i2c_write8(I2C_PORT_USB_C1,
-		       PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) == EC_SUCCESS)
+	if (i2c_write8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f,
+		       0x31) == EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f set to 0x31");
 
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
+	if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) ==
+	    EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f now %02x", val);
 }
 
@@ -308,7 +310,7 @@ void board_reset_pd_mcu(void)
 	/* Daughterboard specific reset for port 1 */
 	ps8815_reset();
 	usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
 
 __override void board_cbi_init(void)
@@ -391,17 +393,21 @@ BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
 
 /******************************************************************************/
 /* USBC mux configuration - Tiger Lake includes internal mux */
-const struct usb_mux usb_muxes[] = {
+const struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 	},
 	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc1_usb3_db_retimer,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc1_usb3_db_retimer,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
@@ -458,13 +464,13 @@ int ppc_get_alert_status(int port)
  * The connector has 24 pins total, and there is no pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-		{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-		{0, 7}, {1, 4}, {1, 3}, {1, 6}, {1, 7},
-		{3, 1}, {2, 0}, {1, 5}, {2, 6}, {2, 7},
-		{2, 1}, {2, 4}, {2, 5}, {1, 2}, {2, 3},
-		{2, 2}, {3, 0}, {-1, -1}, {-1, -1}, {-1, -1},
+	{ -1, -1 }, { 0, 5 }, { 1, 1 },	  { 1, 0 },   { 0, 6 },
+	{ 0, 7 },   { 1, 4 }, { 1, 3 },	  { 1, 6 },   { 1, 7 },
+	{ 3, 1 },   { 2, 0 }, { 1, 5 },	  { 2, 6 },   { 2, 7 },
+	{ 2, 1 },   { 2, 4 }, { 2, 5 },	  { 1, 2 },   { 2, 3 },
+	{ 2, 2 },   { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 },
 };
 
 const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 #endif
diff --git a/board/elemi/board.h b/board/elemi/board.h
index 1556a802b6..aa6756d0ce 100644
--- a/board/elemi/board.h
+++ b/board/elemi/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -37,31 +37,31 @@
 #undef CONFIG_ACCEL_FIFO_SIZE
 
 /* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
 
 /* TODO: b/144165680 - measure and check these values on Volteer */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
 /* Experimentally determined. See b/186079130. */
 #undef CONFIG_USBC_VCONN_SWAP_DELAY_US
-#define CONFIG_USBC_VCONN_SWAP_DELAY_US	10000 /* us */
+#define CONFIG_USBC_VCONN_SWAP_DELAY_US 10000 /* us */
 
 /*
  * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
  * cables only support up to 60W.
  */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* USB Type A Features */
-#define USB_PORT_COUNT			1
+#define USB_PORT_COUNT 1
 #define CONFIG_USB_PORT_POWER_DUMB
 
 /* USBC PPC*/
-#define CONFIG_USBC_PPC_SN5S330		/* USBC port C0 */
-#define CONFIG_USBC_PPC_SYV682X		/* USBC port C1 */
+#define CONFIG_USBC_PPC_SN5S330 /* USBC port C0 */
+#define CONFIG_USBC_PPC_SYV682X /* USBC port C1 */
 #undef CONFIG_USB_PD_TCPC_RUNTIME_CONFIG
 #undef CONFIG_USB_PD_TCPM_TUSB422
 #undef CONFIG_USB_MUX_RUNTIME_CONFIG
@@ -74,8 +74,8 @@
 /* Fan features */
 
 /* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 
 /* Retimer */
 #undef CONFIG_USBC_RETIMER_INTEL_BB
@@ -90,41 +90,40 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_DSW_PWROK		GPIO_EC_PCH_DSW_PWROK
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_LID_OPEN GPIO_EC_LID_OPEN
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL
 
 /* I2C Bus Configuration */
 #define CONFIG_I2C
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_1_MIX	NPCX_I2C_PORT3_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT3_0
+#define I2C_PORT_POWER NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
 
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
+#define I2C_PORT_BATTERY I2C_PORT_POWER
+#define I2C_PORT_CHARGER I2C_PORT_EEPROM
 
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 #define CONFIG_I2C_CONTROLLER
 
-
 #ifndef __ASSEMBLER__
 
 #include "gpio_signal.h"
@@ -136,17 +135,9 @@ enum battery_type {
 	BATTERY_TYPE_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_FAN,
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_FAN, PWM_CH_KBLIGHT, PWM_CH_COUNT };
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 void board_reset_pd_mcu(void);
 
diff --git a/board/elemi/build.mk b/board/elemi/build.mk
index 43b40c644c..d590255d2a 100644
--- a/board/elemi/build.mk
+++ b/board/elemi/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/elemi/ec.tasklist b/board/elemi/ec.tasklist
index c1b0295d37..a1b5d30d93 100644
--- a/board/elemi/ec.tasklist
+++ b/board/elemi/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/elemi/gpio.inc b/board/elemi/gpio.inc
index 9886497e24..3dbf9b35c7 100644
--- a/board/elemi/gpio.inc
+++ b/board/elemi/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,7 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
diff --git a/board/elemi/led.c b/board/elemi/led.c
index d8df9c92a0..8deb12474a 100644
--- a/board/elemi/led.c
+++ b/board/elemi/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -21,10 +21,10 @@
 #define POWER_LED_ON 0
 #define POWER_LED_OFF 1
 
-#define LED_CYCLE_TIME_MS   (2 * 1000)
+#define LED_CYCLE_TIME_MS (2 * 1000)
 #define LED_TICKS_PER_CYCLE (LED_CYCLE_TIME_MS / HOOK_TICK_INTERVAL_MS)
-#define LED_ON_TIME_MS      (1 * 1000)
-#define LED_ON_TICKS        (LED_ON_TIME_MS / HOOK_TICK_INTERVAL_MS)
+#define LED_ON_TIME_MS (1 * 1000)
+#define LED_ON_TICKS (LED_ON_TIME_MS / HOOK_TICK_INTERVAL_MS)
 
 const enum ec_led_id supported_led_ids[] = {
 	EC_LED_ID_LEFT_LED,
@@ -37,22 +37,19 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
-enum led_port {
-	RIGHT_PORT = 0,
-	LEFT_PORT
-};
+enum led_port { RIGHT_PORT = 0, LEFT_PORT };
 
 static void led_set_color_battery(int port, enum led_color color)
 {
 	enum gpio_signal amber_led, white_led;
 
 	amber_led = (port == RIGHT_PORT ? GPIO_C0_CHARGE_LED_AMBER_L :
-				 GPIO_C1_CHARGE_LED_AMBER_L);
+					  GPIO_C1_CHARGE_LED_AMBER_L);
 	white_led = (port == RIGHT_PORT ? GPIO_C0_CHARGE_LED_WHITE_L :
-				 GPIO_C1_CHARGE_LED_WHITE_L);
+					  GPIO_C1_CHARGE_LED_WHITE_L);
 
 	switch (color) {
 	case LED_WHITE:
@@ -124,17 +121,16 @@ static void set_active_port_color(enum led_color color)
 
 	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
 		led_set_color_battery(RIGHT_PORT,
-				(port == RIGHT_PORT) ? color : LED_OFF);
+				      (port == RIGHT_PORT) ? color : LED_OFF);
 	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
 		led_set_color_battery(LEFT_PORT,
-				(port == LEFT_PORT) ? color : LED_OFF);
+				      (port == LEFT_PORT) ? color : LED_OFF);
 }
 
 static void led_set_battery(void)
 {
 	static int battery_ticks;
 	static int suspend_ticks;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
@@ -144,14 +140,13 @@ static void led_set_battery(void)
 	 * system suspend without charging state.
 	 */
 	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
-		charge_get_state() != PWR_STATE_CHARGE) {
-
+	    charge_get_state() != PWR_STATE_CHARGE) {
 		suspend_ticks++;
 
-		led_set_color_battery(RIGHT_PORT, suspend_ticks & 0x4 ?
-					  LED_WHITE : LED_OFF);
-		led_set_color_battery(LEFT_PORT, suspend_ticks & 0x4 ?
-					  LED_WHITE : LED_OFF);
+		led_set_color_battery(
+			RIGHT_PORT, suspend_ticks & 0x4 ? LED_WHITE : LED_OFF);
+		led_set_color_battery(
+			LEFT_PORT, suspend_ticks & 0x4 ? LED_WHITE : LED_OFF);
 		return;
 	}
 
@@ -165,9 +160,12 @@ static void led_set_battery(void)
 	case PWR_STATE_DISCHARGE:
 		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
 			if (charge_get_percent() < 10)
-				led_set_color_battery(RIGHT_PORT,
-					(battery_ticks % LED_TICKS_PER_CYCLE
-					 < LED_ON_TICKS) ? LED_WHITE : LED_OFF);
+				led_set_color_battery(
+					RIGHT_PORT,
+					(battery_ticks % LED_TICKS_PER_CYCLE <
+					 LED_ON_TICKS) ?
+						LED_WHITE :
+						LED_OFF);
 			else
 				led_set_color_battery(RIGHT_PORT, LED_OFF);
 		}
@@ -176,19 +174,20 @@ static void led_set_battery(void)
 			led_set_color_battery(LEFT_PORT, LED_OFF);
 		break;
 	case PWR_STATE_ERROR:
-		set_active_port_color((battery_ticks & 0x2) ?
-				LED_WHITE : LED_OFF);
+		set_active_port_color((battery_ticks & 0x2) ? LED_WHITE :
+							      LED_OFF);
 		break;
 	case PWR_STATE_CHARGE_NEAR_FULL:
 		set_active_port_color(LED_WHITE);
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			set_active_port_color((battery_ticks %
-				LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-				LED_AMBER : LED_OFF);
-		else
-			set_active_port_color(LED_WHITE);
+		set_active_port_color(LED_WHITE);
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		set_active_port_color(
+			(battery_ticks % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
+				LED_AMBER :
+				LED_OFF);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
diff --git a/board/elm/battery.c b/board/elm/battery.c
index de9685a89d..9ef59414a2 100644
--- a/board/elm/battery.c
+++ b/board/elm/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,8 +10,8 @@
 #include "util.h"
 
 /* Shutdown mode parameter to write to manufacturer access register */
-#define SB_SHIP_MODE_REG	0x3a
-#define SB_SHUTDOWN_DATA	0xC574
+#define SB_SHIP_MODE_REG 0x3a
+#define SB_SHUTDOWN_DATA 0xC574
 
 static const struct battery_info info = {
 	.voltage_max = 13200,
diff --git a/board/elm/board.c b/board/elm/board.c
index 1c7cc4b320..4007d34379 100644
--- a/board/elm/board.c
+++ b/board/elm/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -49,8 +49,8 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* Dispaly port hardware can connect to port 0, 1 or neither. */
 #define PD_PORT_NONE -1
@@ -73,8 +73,8 @@ void usb_evt(enum gpio_signal signal)
 
 /* power signal list.  Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
-	{GPIO_SOC_POWER_GOOD, POWER_SIGNAL_ACTIVE_HIGH, "POWER_GOOD"},
-	{GPIO_SUSPEND_L, POWER_SIGNAL_ACTIVE_LOW, "SUSPEND#_ASSERTED"},
+	{ GPIO_SOC_POWER_GOOD, POWER_SIGNAL_ACTIVE_HIGH, "POWER_GOOD" },
+	{ GPIO_SUSPEND_L, POWER_SIGNAL_ACTIVE_LOW, "SUSPEND#_ASSERTED" },
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
@@ -84,11 +84,11 @@ const struct adc_t adc_channels[] = {
 	 * PSYS_MONITOR(PA2): ADC_IN2, 1.44 uA/W on 6.05k Ohm
 	 * output in mW
 	 */
-	[ADC_PSYS] = {"PSYS", 379415, 4096, 0, STM32_AIN(2)},
+	[ADC_PSYS] = { "PSYS", 379415, 4096, 0, STM32_AIN(2) },
 	/* AMON_BMON(PC0): ADC_IN10, output in uV */
-	[ADC_AMON_BMON] = {"AMON_BMON", 183333, 4096, 0, STM32_AIN(10)},
+	[ADC_AMON_BMON] = { "AMON_BMON", 183333, 4096, 0, STM32_AIN(10) },
 	/* VDC_BOOSTIN_SENSE(PC1): ADC_IN11, output in mV */
-	[ADC_VBUS] = {"VBUS", 33000, 4096, 0, STM32_AIN(11)},
+	[ADC_VBUS] = { "VBUS", 33000, 4096, 0, STM32_AIN(11) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
@@ -107,23 +107,18 @@ int anx7688_passthru_allowed(const struct i2c_port_t *port,
 }
 
 /* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "battery",
-		.port = I2C_PORT_BATTERY,
-		.kbps = 100,
-		.scl  = GPIO_I2C0_SCL,
-		.sda  = GPIO_I2C0_SDA
-	},
-	{
-		.name = "pd",
-		.port = I2C_PORT_PD_MCU,
-		.kbps = 1000,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA,
-		.passthru_allowed = anx7688_passthru_allowed
-	}
-};
+const struct i2c_port_t i2c_ports[] = { { .name = "battery",
+					  .port = I2C_PORT_BATTERY,
+					  .kbps = 100,
+					  .scl = GPIO_I2C0_SCL,
+					  .sda = GPIO_I2C0_SDA },
+					{ .name = "pd",
+					  .port = I2C_PORT_PD_MCU,
+					  .kbps = 1000,
+					  .scl = GPIO_I2C1_SCL,
+					  .sda = GPIO_I2C1_SDA,
+					  .passthru_allowed =
+						  anx7688_passthru_allowed } };
 
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -162,22 +157,24 @@ BUILD_ASSERT(ARRAY_SIZE(pi3usb9281_chips) ==
  */
 const struct temp_sensor_t temp_sensors[] = {
 #ifdef CONFIG_TEMP_SENSOR_TMP432
-	{"TMP432_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-		TMP432_IDX_LOCAL},
-	{"TMP432_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-		TMP432_IDX_REMOTE1},
-	{"TMP432_Sensor_2", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-		TMP432_IDX_REMOTE2},
+	{ "TMP432_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
+	  TMP432_IDX_LOCAL },
+	{ "TMP432_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
+	  TMP432_IDX_REMOTE1 },
+	{ "TMP432_Sensor_2", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
+	  TMP432_IDX_REMOTE2 },
 #endif
-	{"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp,
-		0},
+	{ "Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.driver    = &anx7688_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &anx7688_usb_mux_driver,
+			},
 	},
 };
 
@@ -207,7 +204,7 @@ void deferred_reset_pd_mcu(void)
 		 * and wait for 1ms.
 		 */
 		gpio_set_level(GPIO_USB_C0_PWR_EN_L, 1);
-		hook_call_deferred(&deferred_reset_pd_mcu_data, 1*MSEC);
+		hook_call_deferred(&deferred_reset_pd_mcu_data, 1 * MSEC);
 		break;
 	case 1:
 		/*
@@ -215,7 +212,7 @@ void deferred_reset_pd_mcu(void)
 		 * pull PD reset pin and wait for another 1ms
 		 */
 		gpio_set_level(GPIO_USB_C0_RST, 1);
-		hook_call_deferred(&deferred_reset_pd_mcu_data, 1*MSEC);
+		hook_call_deferred(&deferred_reset_pd_mcu_data, 1 * MSEC);
 		/* on PD reset, trigger PD task to reset state */
 		task_set_event(TASK_ID_PD_C0, PD_EVENT_TCPC_RESET);
 		break;
@@ -225,7 +222,7 @@ void deferred_reset_pd_mcu(void)
 		 * enable power and wait for 10ms then pull RESET_N
 		 */
 		gpio_set_level(GPIO_USB_C0_PWR_EN_L, 0);
-		hook_call_deferred(&deferred_reset_pd_mcu_data, 10*MSEC);
+		hook_call_deferred(&deferred_reset_pd_mcu_data, 10 * MSEC);
 		break;
 	case 2:
 		/*
@@ -244,7 +241,7 @@ static void board_power_on_pd_mcu(void)
 		return;
 
 	gpio_set_level(GPIO_USB_C0_EXTPWR_EN, 1);
-	hook_call_deferred(&deferred_reset_pd_mcu_data, 1*MSEC);
+	hook_call_deferred(&deferred_reset_pd_mcu_data, 1 * MSEC);
 }
 
 void board_reset_pd_mcu(void)
@@ -253,17 +250,15 @@ void board_reset_pd_mcu(void)
 	anx7688_enable_cable_detection(0);
 
 	/* wait for 10ms, then start port controller's reset sequence */
-	hook_call_deferred(&deferred_reset_pd_mcu_data, 10*MSEC);
+	hook_call_deferred(&deferred_reset_pd_mcu_data, 10 * MSEC);
 }
 
-static int command_pd_reset(int argc, char **argv)
+static int command_pd_reset(int argc, const char **argv)
 {
 	board_reset_pd_mcu();
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(resetpd, command_pd_reset,
-			"",
-			"Reset PD IC");
+DECLARE_CONSOLE_COMMAND(resetpd, command_pd_reset, "", "Reset PD IC");
 
 /**
  * There is a level shift for AC_OK & LID_OPEN signal between AP & EC,
@@ -342,13 +337,13 @@ int board_set_active_charge_port(int charge_port)
  * @param charge_ma     Desired charge limit (mA).
  * @param charge_mv     Negotiated charge voltage (mV).
  */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	/* Limit input current 95% ratio on elm board for safety */
 	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-				   CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 	pd_send_host_event(PD_EVENT_POWER_CHANGE);
 }
 
@@ -464,17 +459,13 @@ DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
 static struct mutex g_kx022_mutex[2];
 
 /* Matrix to rotate accelerometer into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0,  0},
-	{ 0,  FLOAT_TO_FP(1),  0},
-	{ 0,  0, FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				       { 0, FLOAT_TO_FP(1), 0 },
+				       { 0, 0, FLOAT_TO_FP(-1) } };
 
-const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1),  0,  0},
-	{ 0, FLOAT_TO_FP(-1),  0},
-	{ 0,  0, FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+				      { 0, FLOAT_TO_FP(-1), 0 },
+				      { 0, 0, FLOAT_TO_FP(-1) } };
 
 /* KX022 private data */
 struct kionix_accel_data g_kx022_data[2];
diff --git a/board/elm/board.h b/board/elm/board.h
index 8bb8c2bf15..10cb6bb75d 100644
--- a/board/elm/board.h
+++ b/board/elm/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,7 +27,7 @@
 #define CONFIG_LID_ANGLE_UPDATE
 
 #define CONFIG_ADC
-#undef  CONFIG_ADC_WATCHDOG
+#undef CONFIG_ADC_WATCHDOG
 
 /* AC adaptor, charger, battery */
 #define CONFIG_BATTERY_CUT_OFF
@@ -75,10 +75,10 @@
 #define CONFIG_SPI_CONTROLLER
 #define CONFIG_STM_HWTIMER32
 #define CONFIG_VBOOT_HASH
-#undef  CONFIG_WATCHDOG_HELP
+#undef CONFIG_WATCHDOG_HELP
 #define CONFIG_SWITCH
 #define CONFIG_BOARD_VERSION_GPIO
-#undef  CONFIG_UART_CONSOLE
+#undef CONFIG_UART_CONSOLE
 #define CONFIG_UART_CONSOLE 1
 #define CONFIG_TEMP_SENSOR
 #define CONFIG_DPTF
@@ -102,7 +102,7 @@
 #define CONFIG_USB_PD_TCPM_TCPCI
 #define CONFIG_USB_PD_TRY_SRC
 #define CONFIG_USB_PD_VBUS_DETECT_TCPC
-#undef  CONFIG_TCPC_I2C_BASE_ADDR_FLAGS
+#undef CONFIG_TCPC_I2C_BASE_ADDR_FLAGS
 #define CONFIG_TCPC_I2C_BASE_ADDR_FLAGS 0x2C
 #define CONFIG_USB_PD_ANX7688
 
@@ -144,11 +144,11 @@
 #undef CONFIG_EC_WRITABLE_STORAGE_OFF
 #undef CONFIG_EC_WRITABLE_STORAGE_SIZE
 #undef CONFIG_WP_STORAGE_SIZE
-#define CONFIG_RW_MEM_OFF                (128 * 1024)
-#define CONFIG_RW_SIZE                   (128 * 1024)
-#define CONFIG_EC_WRITABLE_STORAGE_OFF   (128 * 1024)
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE  (128 * 1024)
-#define CONFIG_WP_STORAGE_SIZE           (128 * 1024)
+#define CONFIG_RW_MEM_OFF (128 * 1024)
+#define CONFIG_RW_SIZE (128 * 1024)
+#define CONFIG_EC_WRITABLE_STORAGE_OFF (128 * 1024)
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE (128 * 1024)
+#define CONFIG_WP_STORAGE_SIZE (128 * 1024)
 
 /* Drivers */
 #ifndef __ASSEMBLER__
@@ -160,30 +160,30 @@
 #define KB_OUT_PORT_LIST GPIO_A, GPIO_B, GPIO_C, GPIO_D
 
 /* 2 I2C master ports, connect to battery, charger, pd and USB switches */
-#define I2C_PORT_MASTER  0
-#define I2C_PORT_ACCEL   0
+#define I2C_PORT_MASTER 0
+#define I2C_PORT_ACCEL 0
 #define I2C_PORT_BATTERY 0
 #define I2C_PORT_CHARGER 0
 #define I2C_PORT_PERICOM 0
 #define I2C_PORT_THERMAL 0
-#define I2C_PORT_PD_MCU  1
+#define I2C_PORT_PD_MCU 1
 #define I2C_PORT_USB_MUX 1
-#define I2C_PORT_TCPC    1
+#define I2C_PORT_TCPC 1
 
 /* Enable Accel over SPI */
-#define CONFIG_SPI_ACCEL_PORT    0  /* First SPI controller port (SPI2) */
+#define CONFIG_SPI_ACCEL_PORT 0 /* First SPI controller port (SPI2) */
 
 /* Timer selection */
 #define TIM_CLOCK32 2
 #define TIM_WATCHDOG 4
 
 /* Define the host events which are allowed to wakeup AP in S3. */
-#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \
-		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_FASTBOOT))
+#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK                     \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |          \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |      \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |       \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_FASTBOOT))
 
 #include "gpio_signal.h"
 
@@ -201,9 +201,9 @@ enum pwm_channel {
 };
 
 enum adc_channel {
-	ADC_PSYS = 0,  /* PC1: STM32_AIN(2) */
+	ADC_PSYS = 0, /* PC1: STM32_AIN(2) */
 	ADC_AMON_BMON, /* PC0: STM32_AIN(10) */
-	ADC_VBUS,      /* PA2: STM32_AIN(11) */
+	ADC_VBUS, /* PA2: STM32_AIN(11) */
 	ADC_CH_COUNT
 };
 
@@ -231,16 +231,16 @@ enum sensor_id {
  * delay to turn on the power supply max is ~16ms.
  * delay to turn off the power supply max is about ~180ms.
  */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* delay to turn on/off vconn */
 
 /* Define typical operating power and max power */
 #define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       45000
-#define PD_MAX_CURRENT_MA     CONFIG_CHARGER_MAX_INPUT_CURRENT
-#define PD_MAX_VOLTAGE_MV     20000
+#define PD_MAX_POWER_MW 45000
+#define PD_MAX_CURRENT_MA CONFIG_CHARGER_MAX_INPUT_CURRENT
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* The lower the input voltage, the higher the power efficiency. */
 #define PD_PREFER_LOW_VOLTAGE
@@ -250,6 +250,6 @@ void board_reset_pd_mcu(void);
 /* Set AP reset pin according to parameter */
 void board_set_ap_reset(int asserted);
 
-#endif  /* !__ASSEMBLER__ */
+#endif /* !__ASSEMBLER__ */
 
-#endif  /* __CROS_EC_BOARD_H */
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/elm/build.mk b/board/elm/build.mk
index 172a88e843..4d6ba76cae 100644
--- a/board/elm/build.mk
+++ b/board/elm/build.mk
@@ -1,5 +1,5 @@
 #-*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/elm/ec.tasklist b/board/elm/ec.tasklist
index 3ea68bf9f8..be745f7487 100644
--- a/board/elm/ec.tasklist
+++ b/board/elm/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/elm/gpio.inc b/board/elm/gpio.inc
index 0dc89269ba..ef77ad732e 100644
--- a/board/elm/gpio.inc
+++ b/board/elm/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/elm/led.c b/board/elm/led.c
index d73cc05c1b..29140ce237 100644
--- a/board/elm/led.c
+++ b/board/elm/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,10 +19,8 @@
 #define LOW_BATTERY_PERMILLAGE 137
 #define FULL_BATTERY_PERMILLAGE 937
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -31,7 +29,7 @@ enum led_color {
 	BAT_LED_ORANGE,
 	PWR_LED_BLUE,
 	PWR_LED_ORANGE,
-	LED_COLOR_COUNT		/* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static int bat_led_set(enum led_color color, int on)
@@ -111,8 +109,7 @@ static void elm_led_set_power(void)
 		bat_led_set(PWR_LED_ORANGE, 0);
 	} else if (chipset_in_state(CHIPSET_STATE_SUSPEND)) {
 		bat_led_set(PWR_LED_BLUE, 0);
-		bat_led_set(PWR_LED_ORANGE,
-			    (blink_second & 3) ? 0 : 1);
+		bat_led_set(PWR_LED_ORANGE, (blink_second & 3) ? 0 : 1);
 	}
 }
 
@@ -135,8 +132,9 @@ static void elm_led_set_battery(void)
 	/* Make the percentage approximate to UI shown */
 	remaining_capacity = *(int *)host_get_memmap(EC_MEMMAP_BATT_CAP);
 	full_charge_capacity = *(int *)host_get_memmap(EC_MEMMAP_BATT_LFCC);
-	permillage = !full_charge_capacity ? 0 :
-		(1000 * remaining_capacity) / full_charge_capacity;
+	permillage = !full_charge_capacity ?
+			     0 :
+			     (1000 * remaining_capacity) / full_charge_capacity;
 
 	switch (charge_get_state()) {
 	case PWR_STATE_CHARGE:
@@ -156,12 +154,10 @@ static void elm_led_set_battery(void)
 		bat_led_set(BAT_LED_BLUE, 0);
 		if (!chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
 		    permillage <= CRITICAL_LOW_BATTERY_PERMILLAGE)
-			bat_led_set(BAT_LED_ORANGE,
-				    (blink_second & 1) ? 0 : 1);
+			bat_led_set(BAT_LED_ORANGE, (blink_second & 1) ? 0 : 1);
 		else if (!chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
 			 permillage <= LOW_BATTERY_PERMILLAGE)
-			bat_led_set(BAT_LED_ORANGE,
-				    (blink_second & 3) ? 0 : 1);
+			bat_led_set(BAT_LED_ORANGE, (blink_second & 3) ? 0 : 1);
 		else
 			bat_led_set(BAT_LED_ORANGE, 0);
 		break;
diff --git a/board/elm/usb_pd_policy.c b/board/elm/usb_pd_policy.c
index 2eeab736d9..0ba277f71d 100644
--- a/board/elm/usb_pd_policy.c
+++ b/board/elm/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,8 +21,8 @@
 #include "usb_mux.h"
 #include "usb_pd.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_set_power_supply_ready(int port)
 {
diff --git a/board/endeavour/board.c b/board/endeavour/board.c
index 98d805f60a..0d5e633ea0 100644
--- a/board/endeavour/board.c
+++ b/board/endeavour/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -38,8 +38,8 @@
 #include "uart.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static uint8_t board_version;
 static uint32_t oem;
@@ -56,14 +56,15 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* Vbus sensing (1/10 voltage divider). */
-	[ADC_VBUS] = {"VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
+	[ADC_VBUS] = { "VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT * 10,
+		       ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* TODO: Verify fan control and mft */
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_FAN_PWR_EN,
 };
@@ -80,39 +81,31 @@ const struct fan_t fans[] = {
 BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
 
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN },
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
-const struct i2c_port_t i2c_ports[]  = {
-	{
-		.name = "pse",
-		.port = I2C_PORT_PSE,
-		.kbps = 400,
-		.scl  = GPIO_I2C0_0_SCL,
-		.sda  = GPIO_I2C0_0_SDA
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl  = GPIO_I2C0_1_SCL,
-		.sda  = GPIO_I2C0_1_SDA
-	},
-	{
-		.name = "pmic",
-		.port = I2C_PORT_PMIC,
-		.kbps = 400,
-		.scl  = GPIO_I2C2_SCL,
-		.sda  = GPIO_I2C2_SDA
-	},
-	{
-		.name = "thermal",
-		.port = I2C_PORT_THERMAL,
-		.kbps = 400,
-		.scl  = GPIO_I2C3_SCL,
-		.sda  = GPIO_I2C3_SDA
-	},
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "pse",
+	  .port = I2C_PORT_PSE,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_0_SCL,
+	  .sda = GPIO_I2C0_0_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_1_SCL,
+	  .sda = GPIO_I2C0_1_SDA },
+	{ .name = "pmic",
+	  .port = I2C_PORT_PMIC,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "thermal",
+	  .port = I2C_PORT_THERMAL,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -131,10 +124,10 @@ const int usb_port_enable[USB_PORT_COUNT] = {
  *     src/mainboard/google/${board}/acpi/dptf.asl
  */
 const struct temp_sensor_t temp_sensors[] = {
-	{"TMP431_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-			TMP432_IDX_LOCAL},
-	{"TMP431_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-			TMP432_IDX_REMOTE1},
+	{ "TMP431_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
+	  TMP432_IDX_LOCAL },
+	{ "TMP431_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
+	  TMP432_IDX_REMOTE1 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -147,9 +140,11 @@ struct ec_thermal_config thermal_params[] = {
 	 * {Twarn, Thigh, X    }, <off>
 	 * fan_off, fan_max
 	 */
-	{{0, C_TO_K(81), C_TO_K(82)}, {0, C_TO_K(77), 0},
-		C_TO_K(19), C_TO_K(74)},	/* TMP431_Internal */
-	{{0, 0, 0}, {0, 0, 0}, 0, 0},	/* TMP431_Sensor_1 */
+	{ { 0, C_TO_K(81), C_TO_K(82) },
+	  { 0, C_TO_K(77), 0 },
+	  C_TO_K(19),
+	  C_TO_K(74) }, /* TMP431_Internal */
+	{ { 0, 0, 0 }, { 0, 0, 0 }, 0, 0 }, /* TMP431_Sensor_1 */
 };
 BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
 
@@ -318,9 +313,9 @@ int64_t get_time_dsw_pwrok(void)
 }
 
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED_RED]  = { 3, PWM_CONFIG_DSLEEP, 100 },
+	[PWM_CH_LED_RED] = { 3, PWM_CONFIG_DSLEEP, 100 },
 	[PWM_CH_LED_WHITE] = { 5, PWM_CONFIG_DSLEEP, 100 },
-	[PWM_CH_FAN] = {4, PWM_CONFIG_OPEN_DRAIN, 25000},
+	[PWM_CH_FAN] = { 4, PWM_CONFIG_OPEN_DRAIN, 25000 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
@@ -332,21 +327,20 @@ struct fan_step {
 
 /* Note: Do not make the fan on/off point equal to 0 or 100 */
 static const struct fan_step fan_table0[] = {
-	{.on =  0, .off =  2, .rpm = 0},
-	{.on = 11, .off =  2, .rpm = 2500},
-	{.on = 38, .off = 29, .rpm = 3200},
-	{.on = 65, .off = 36, .rpm = 3500},
-	{.on = 76, .off = 64, .rpm = 3900},
-	{.on = 84, .off = 75, .rpm = 4500},
-	{.on = 91, .off = 82, .rpm = 5100},
-	{.on = 98, .off = 89, .rpm = 5400},
+	{ .on = 0, .off = 2, .rpm = 0 },
+	{ .on = 11, .off = 2, .rpm = 2500 },
+	{ .on = 38, .off = 29, .rpm = 3200 },
+	{ .on = 65, .off = 36, .rpm = 3500 },
+	{ .on = 76, .off = 64, .rpm = 3900 },
+	{ .on = 84, .off = 75, .rpm = 4500 },
+	{ .on = 91, .off = 82, .rpm = 5100 },
+	{ .on = 98, .off = 89, .rpm = 5400 },
 };
 /* All fan tables must have the same number of levels */
 #define NUM_FAN_LEVELS ARRAY_SIZE(fan_table0)
 
 static const struct fan_step *fan_table = fan_table0;
 
-
 static void cbi_init(void)
 {
 	uint32_t val;
@@ -403,8 +397,7 @@ int fan_percent_to_rpm(int fan, int pct)
 
 	previous_pct = pct;
 
-	if (fan_table[current_level].rpm !=
-		fan_get_rpm_target(FAN_CH(fan)))
+	if (fan_table[current_level].rpm != fan_get_rpm_target(FAN_CH(fan)))
 		cprints(CC_THERMAL, "Setting fan RPM to %d",
 			fan_table[current_level].rpm);
 
diff --git a/board/endeavour/board.h b/board/endeavour/board.h
index 9b0107b2c4..9c0836b0e3 100644
--- a/board/endeavour/board.h
+++ b/board/endeavour/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,7 +12,7 @@
  * Allow dangerous commands.
  * TODO: Remove this config before production.
  */
-#undef  CONFIG_SYSTEM_UNLOCKED
+#undef CONFIG_SYSTEM_UNLOCKED
 #define CONFIG_USB_PD_COMM_LOCKED
 
 /* EC */
@@ -31,7 +31,7 @@
 #define CONFIG_FPU
 #define CONFIG_I2C
 #define CONFIG_I2C_CONTROLLER
-#undef  CONFIG_LID_SWITCH
+#undef CONFIG_LID_SWITCH
 #define CONFIG_POWER_BUTTON_IGNORE_LID
 #define CONFIG_PWM
 #define CONFIG_LTO
@@ -59,12 +59,12 @@
 #define CONFIG_CHIPSET_HAS_PRE_INIT_CALLBACK
 #define CONFIG_CHIPSET_RESET_HOOK
 #define CONFIG_HOST_INTERFACE_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 #define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD
 
 #define CONFIG_EXTPOWER_GPIO
-#undef  CONFIG_EXTPOWER_DEBOUNCE_MS
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
 #define CONFIG_EXTPOWER_DEBOUNCE_MS 1000
 #define CONFIG_POWER_BUTTON
 #define CONFIG_POWER_BUTTON_X86
@@ -82,18 +82,18 @@
 #define USB_PORT_COUNT 4
 
 /* Optional feature to configure npcx chip */
-#define NPCX_UART_MODULE2	1 /* 1:GPIO64/65 as UART */
-#define NPCX_JTAG_MODULE2	0 /* 0:GPIO21/17/16/20 as JTAG */
-#define NPCX_TACH_SEL2		1 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
+#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART */
+#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 as JTAG */
+#define NPCX_TACH_SEL2 1 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
 
 /* I2C ports */
-#define I2C_PORT_PSE		NPCX_I2C_PORT0_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT0_1
-#define I2C_PORT_PMIC		NPCX_I2C_PORT2
-#define I2C_PORT_THERMAL	NPCX_I2C_PORT3
+#define I2C_PORT_PSE NPCX_I2C_PORT0_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT0_1
+#define I2C_PORT_PMIC NPCX_I2C_PORT2
+#define I2C_PORT_THERMAL NPCX_I2C_PORT3
 
 /* I2C addresses */
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 
 #define CONFIG_VBOOT_HASH
 #define CONFIG_VSTORE
@@ -109,15 +109,12 @@ enum charge_port {
 };
 
 enum temp_sensor_id {
-	TEMP_SENSOR_CHARGER,	/* BD99992GW SYSTHERM1 */
-	TEMP_SENSOR_DRAM,	/* BD99992GW SYSTHERM2 */
+	TEMP_SENSOR_CHARGER, /* BD99992GW SYSTHERM1 */
+	TEMP_SENSOR_DRAM, /* BD99992GW SYSTHERM2 */
 	TEMP_SENSOR_COUNT
 };
 
-enum adc_channel {
-	ADC_VBUS,
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_VBUS, ADC_CH_COUNT };
 
 enum pwm_channel {
 	PWM_CH_LED_RED,
diff --git a/board/endeavour/build.mk b/board/endeavour/build.mk
index 20f3f4d02c..2b19f6b43d 100644
--- a/board/endeavour/build.mk
+++ b/board/endeavour/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/endeavour/ec.tasklist b/board/endeavour/ec.tasklist
index ef58c6267a..9a4435f43e 100644
--- a/board/endeavour/ec.tasklist
+++ b/board/endeavour/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/endeavour/gpio.inc b/board/endeavour/gpio.inc
index 85904aab0c..e67f88347a 100644
--- a/board/endeavour/gpio.inc
+++ b/board/endeavour/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/endeavour/led.c b/board/endeavour/led.c
index b75de503e5..91bd6a3410 100644
--- a/board/endeavour/led.c
+++ b/board/endeavour/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -15,7 +15,7 @@
 #include "timer.h"
 #include "util.h"
 
-const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 enum led_color {
@@ -71,9 +71,9 @@ static int set_color(enum ec_led_id id, enum led_color color, int duty)
 	}
 }
 
-#define LED_PULSE_US		(2 * SECOND)
+#define LED_PULSE_US (2 * SECOND)
 /* 40 msec for nice and smooth transition. */
-#define LED_PULSE_TICK_US	(40 * MSEC)
+#define LED_PULSE_TICK_US (40 * MSEC)
 
 /* When pulsing is enabled, brightness is incremented by <duty_inc> every
  * <interval> usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented
@@ -167,7 +167,7 @@ void show_critical_error(void)
 		set_color(EC_LED_ID_POWER_LED, LED_RED, 100);
 }
 
-static int command_led(int argc, char **argv)
+static int command_led(int argc, const char **argv)
 {
 	enum ec_led_id id = EC_LED_ID_POWER_LED;
 
@@ -190,8 +190,7 @@ static int command_led(int argc, char **argv)
 	}
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(led, command_led,
-			"[debug|red|white|off|crit]",
+DECLARE_CONSOLE_COMMAND(led, command_led, "[debug|red|white|off|crit]",
 			"Turn on/off LED.");
 
 void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
diff --git a/board/endeavour/pse.c b/board/endeavour/pse.c
index 671288ccf5..bda7e1994d 100644
--- a/board/endeavour/pse.c
+++ b/board/endeavour/pse.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,44 +18,44 @@
 #include "timer.h"
 #include "util.h"
 
-#define LTC4291_I2C_ADDR	0x2C
-
-#define LTC4291_REG_SUPEVN_COR	0x0B
-#define LTC4291_REG_STATPWR	0x10
-#define LTC4291_REG_STATPIN	0x11
-#define LTC4291_REG_OPMD	0x12
-#define LTC4291_REG_DISENA	0x13
-#define LTC4291_REG_DETENA	0x14
-#define LTC4291_REG_DETPB	0x18
-#define LTC4291_REG_PWRPB	0x19
-#define LTC4291_REG_RSTPB	0x1A
-#define LTC4291_REG_ID		0x1B
-#define LTC4291_REG_DEVID	0x43
-#define LTC4291_REG_HPMD1	0x46
-#define LTC4291_REG_HPMD2	0x4B
-#define LTC4291_REG_HPMD3	0x50
-#define LTC4291_REG_HPMD4	0x55
-#define LTC4291_REG_LPWRPB	0x6E
-
-#define LTC4291_FLD_STATPIN_AUTO	BIT(0)
-#define LTC4291_FLD_RSTPB_RSTALL	BIT(4)
-
-#define LTC4291_STATPWR_ON_PORT(port)	(0x01 << (port))
-#define LTC4291_DETENA_EN_PORT(port)	(0x11 << (port))
-#define LTC4291_DETPB_EN_PORT(port)	(0x11 << (port))
-#define LTC4291_PWRPB_OFF_PORT(port)	(0x10 << (port))
-
-#define LTC4291_OPMD_AUTO	0xFF
-#define LTC4291_DISENA_ALL	0x0F
-#define LTC4291_DETENA_ALL	0xFF
-#define LTC4291_ID		0x64
-#define LTC4291_DEVID		0x38
-#define LTC4291_HPMD_MIN	0x00
-#define LTC4291_HPMD_MAX	0xA8
-
-#define LTC4291_PORT_MAX	4
-
-#define LTC4291_RESET_DELAY_US	(20 * MSEC)
+#define LTC4291_I2C_ADDR 0x2C
+
+#define LTC4291_REG_SUPEVN_COR 0x0B
+#define LTC4291_REG_STATPWR 0x10
+#define LTC4291_REG_STATPIN 0x11
+#define LTC4291_REG_OPMD 0x12
+#define LTC4291_REG_DISENA 0x13
+#define LTC4291_REG_DETENA 0x14
+#define LTC4291_REG_DETPB 0x18
+#define LTC4291_REG_PWRPB 0x19
+#define LTC4291_REG_RSTPB 0x1A
+#define LTC4291_REG_ID 0x1B
+#define LTC4291_REG_DEVID 0x43
+#define LTC4291_REG_HPMD1 0x46
+#define LTC4291_REG_HPMD2 0x4B
+#define LTC4291_REG_HPMD3 0x50
+#define LTC4291_REG_HPMD4 0x55
+#define LTC4291_REG_LPWRPB 0x6E
+
+#define LTC4291_FLD_STATPIN_AUTO BIT(0)
+#define LTC4291_FLD_RSTPB_RSTALL BIT(4)
+
+#define LTC4291_STATPWR_ON_PORT(port) (0x01 << (port))
+#define LTC4291_DETENA_EN_PORT(port) (0x11 << (port))
+#define LTC4291_DETPB_EN_PORT(port) (0x11 << (port))
+#define LTC4291_PWRPB_OFF_PORT(port) (0x10 << (port))
+
+#define LTC4291_OPMD_AUTO 0xFF
+#define LTC4291_DISENA_ALL 0x0F
+#define LTC4291_DETENA_ALL 0xFF
+#define LTC4291_ID 0x64
+#define LTC4291_DEVID 0x38
+#define LTC4291_HPMD_MIN 0x00
+#define LTC4291_HPMD_MAX 0xA8
+
+#define LTC4291_PORT_MAX 4
+
+#define LTC4291_RESET_DELAY_US (20 * MSEC)
 
 #define I2C_PSE_READ(reg, data) \
 	i2c_read8(I2C_PORT_PSE, LTC4291_I2C_ADDR, LTC4291_REG_##reg, (data))
@@ -63,7 +63,7 @@
 #define I2C_PSE_WRITE(reg, data) \
 	i2c_write8(I2C_PORT_PSE, LTC4291_I2C_ADDR, LTC4291_REG_##reg, (data))
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 static int pse_write_hpmd(int port, int val)
 {
@@ -173,7 +173,7 @@ DECLARE_HOOK(HOOK_CHIPSET_RESUME, pse_init, HOOK_PRIO_DEFAULT);
 /* Also reset the PSE on a reboot to toggle the power. */
 DECLARE_HOOK(HOOK_CHIPSET_RESET, pse_init, HOOK_PRIO_DEFAULT);
 
-static int command_pse(int argc, char **argv)
+static int command_pse(int argc, const char **argv)
 {
 	int port;
 
@@ -205,8 +205,7 @@ static int command_pse(int argc, char **argv)
 	else
 		return EC_ERROR_PARAM2;
 }
-DECLARE_CONSOLE_COMMAND(pse, command_pse,
-			"<port# 0-3> <off | on | min | max>",
+DECLARE_CONSOLE_COMMAND(pse, command_pse, "<port# 0-3> <off | on | min | max>",
 			"Set PSE port power");
 
 static int ec_command_pse_status(int port, uint8_t *status)
diff --git a/board/eve/battery.c b/board/eve/battery.c
index 2a505b80ec..d1ce1fd74a 100644
--- a/board/eve/battery.c
+++ b/board/eve/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -18,10 +18,10 @@
 #include "i2c.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 /* Shutdown mode parameter to write to manufacturer access register */
-#define SB_SHUTDOWN_DATA	0x0010
+#define SB_SHUTDOWN_DATA 0x0010
 
 /* Vendor CTO command parameter */
 #define SB_VENDOR_PARAM_CTO_DISABLE 0
@@ -81,16 +81,16 @@ static int otd_recovery_temp_reg = -1;
  * limits are given by discharging_min/max_c.
  */
 static const struct battery_info batt_info_lg = {
-	.voltage_max		= TARGET_WITH_MARGIN(8800, 5), /* mV */
-	.voltage_normal		= 7700,
-	.voltage_min		= 6100, /* Add 100mV for charger accuracy */
-	.precharge_current	= 256,	/* mA */
-	.start_charging_min_c	= 0,
-	.start_charging_max_c	= 46,
-	.charging_min_c		= 10,
-	.charging_max_c		= 50,
-	.discharging_min_c	= 0,
-	.discharging_max_c	= 60,
+	.voltage_max = TARGET_WITH_MARGIN(8800, 5), /* mV */
+	.voltage_normal = 7700,
+	.voltage_min = 6100, /* Add 100mV for charger accuracy */
+	.precharge_current = 256, /* mA */
+	.start_charging_min_c = 0,
+	.start_charging_max_c = 46,
+	.charging_min_c = 10,
+	.charging_max_c = 50,
+	.discharging_min_c = 0,
+	.discharging_max_c = 60,
 };
 
 /*
@@ -99,16 +99,16 @@ static const struct battery_info batt_info_lg = {
  * limits are given by discharging_min/max_c.
  */
 static const struct battery_info batt_info_lishen = {
-	.voltage_max		= TARGET_WITH_MARGIN(8800, 5), /* mV */
-	.voltage_normal		= 7700,
-	.voltage_min		= 6100, /* Add 100mV for charger accuracy */
-	.precharge_current	= 256,	/* mA */
-	.start_charging_min_c	= 0,
-	.start_charging_max_c	= 46,
-	.charging_min_c		= 10,
-	.charging_max_c		= 50,
-	.discharging_min_c	= 0,
-	.discharging_max_c	= 60,
+	.voltage_max = TARGET_WITH_MARGIN(8800, 5), /* mV */
+	.voltage_normal = 7700,
+	.voltage_min = 6100, /* Add 100mV for charger accuracy */
+	.precharge_current = 256, /* mA */
+	.start_charging_min_c = 0,
+	.start_charging_max_c = 46,
+	.charging_min_c = 10,
+	.charging_max_c = 50,
+	.discharging_min_c = 0,
+	.discharging_max_c = 60,
 };
 
 static const struct board_batt_params info[] = {
@@ -139,7 +139,7 @@ static int board_get_battery_type(void)
 	if (!battery_manufacturer_name(name, sizeof(name))) {
 		for (i = 0; i < BATTERY_TYPE_COUNT; i++) {
 			if (!strncasecmp(name, info[i].manuf_name,
-					 ARRAY_SIZE(name)-1)) {
+					 ARRAY_SIZE(name) - 1)) {
 				board_battery_type = i;
 				break;
 			}
@@ -168,7 +168,9 @@ DECLARE_HOOK(HOOK_INIT, board_init_battery_type, HOOK_PRIO_INIT_I2C + 1);
 const struct battery_info *battery_get_info(void)
 {
 	return info[board_battery_type == BATTERY_TYPE_COUNT ?
-		    DEFAULT_BATTERY_TYPE : board_battery_type].batt_info;
+			    DEFAULT_BATTERY_TYPE :
+			    board_battery_type]
+		.batt_info;
 }
 
 int board_cut_off_battery(void)
@@ -192,7 +194,7 @@ static int charger_should_discharge_on_ac(struct charge_state_data *curr)
 
 	/* Do not discharge on AC if the battery is still waking up */
 	if (!(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
-		!(curr->batt.status & STATUS_FULLY_CHARGED))
+	    !(curr->batt.status & STATUS_FULLY_CHARGED))
 		return 0;
 
 	/*
@@ -209,8 +211,8 @@ static int charger_should_discharge_on_ac(struct charge_state_data *curr)
 	 * and suspend USB charging and DC/DC converter.
 	 */
 	if (!battery_is_cut_off() &&
-		!(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
-		(curr->batt.status & STATUS_FULLY_CHARGED))
+	    !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
+	    (curr->batt.status & STATUS_FULLY_CHARGED))
 		return 1;
 
 	/*
@@ -275,8 +277,9 @@ static int battery_init(void)
 {
 	int batt_status;
 
-	return battery_status(&batt_status) ? 0 :
-		!!(batt_status & STATUS_INITIALIZED);
+	return battery_status(&batt_status) ?
+		       0 :
+		       !!(batt_status & STATUS_INITIALIZED);
 }
 
 /* Allow booting now that the battery has woke up */
@@ -305,8 +308,8 @@ static int battery_check_disconnect(void)
 	uint8_t data[6];
 
 	/* Check if battery discharging is disabled. */
-	rv = sb_read_mfgacc(PARAM_OPERATION_STATUS,
-			    SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data));
+	rv = sb_read_mfgacc(PARAM_OPERATION_STATUS, SB_ALT_MANUFACTURER_ACCESS,
+			    data, sizeof(data));
 	if (rv)
 		return BATTERY_DISCONNECT_ERROR;
 
@@ -384,14 +387,13 @@ static int board_battery_sb_write(uint8_t access, int cmd)
 	buf[1] = cmd & 0xff;
 	buf[2] = (cmd >> 8) & 0xff;
 
-	rv = i2c_xfer(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS,
-		      buf, 1 + sizeof(uint16_t), NULL, 0);
+	rv = i2c_xfer(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS, buf,
+		      1 + sizeof(uint16_t), NULL, 0);
 
 	return rv;
 }
 
-int board_battery_read_mfgacc(int offset, int access,
-				      uint8_t *buf, int len)
+int board_battery_read_mfgacc(int offset, int access, uint8_t *buf, int len)
 {
 	int rv;
 	uint8_t block_len, reg;
@@ -408,7 +410,7 @@ int board_battery_read_mfgacc(int offset, int access,
 
 	reg = access;
 	rv = i2c_xfer_unlocked(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS, &reg, 1,
-	    &block_len, 1, I2C_XFER_START);
+			       &block_len, 1, I2C_XFER_START);
 	if (rv) {
 		i2c_lock(I2C_PORT_BATTERY, 0);
 		return rv;
@@ -419,7 +421,7 @@ int board_battery_read_mfgacc(int offset, int access,
 		block_len = len;
 
 	rv = i2c_xfer_unlocked(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS, NULL, 0,
-	    buf, block_len, I2C_XFER_STOP);
+			       buf, block_len, I2C_XFER_STOP);
 	i2c_lock(I2C_PORT_BATTERY, 0);
 
 	return rv;
@@ -432,7 +434,8 @@ static int board_battery_unseal(uint32_t param)
 
 	/* Get Operation Status */
 	rv = board_battery_read_mfgacc(PARAM_OPERATION_STATUS,
-			    SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data));
+				       SB_ALT_MANUFACTURER_ACCESS, data,
+				       sizeof(data));
 
 	if (rv)
 		return EC_ERROR_UNKNOWN;
@@ -457,7 +460,8 @@ static int board_battery_unseal(uint32_t param)
 
 		/* Verify that battery is unsealed */
 		rv = board_battery_read_mfgacc(PARAM_OPERATION_STATUS,
-			    SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data));
+					       SB_ALT_MANUFACTURER_ACCESS, data,
+					       sizeof(data));
 		if (rv || ((data[3] & 0x3) != 0x2))
 			return EC_ERROR_UNKNOWN;
 	}
@@ -474,7 +478,7 @@ static int board_battery_seal(void)
 	int rv;
 
 	i2c_lock(I2C_PORT_BATTERY, 1);
-	rv = board_battery_sb_write(SB_MANUFACTURER_ACCESS,  0x0030);
+	rv = board_battery_sb_write(SB_MANUFACTURER_ACCESS, 0x0030);
 	i2c_lock(I2C_PORT_BATTERY, 0);
 
 	if (rv != EC_SUCCESS)
@@ -507,8 +511,7 @@ static int board_battery_write_flash(int addr, uint32_t data, int len)
 	len += 4;
 
 	i2c_lock(I2C_PORT_BATTERY, 1);
-	rv = i2c_xfer(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS, buf,
-		      len, NULL, 0);
+	rv = i2c_xfer(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS, buf, len, NULL, 0);
 	i2c_lock(I2C_PORT_BATTERY, 0);
 
 	return rv;
@@ -522,13 +525,13 @@ static int board_battery_read_flash(int block, int len, uint8_t *buf)
 
 	if (len > 4)
 		len = 4;
-	rv = board_battery_read_mfgacc(block,
-			    SB_ALT_MANUFACTURER_ACCESS, data, len + 2);
+	rv = board_battery_read_mfgacc(block, SB_ALT_MANUFACTURER_ACCESS, data,
+				       len + 2);
 	if (rv)
 		return EC_RES_ERROR;
 
 	for (i = 0; i < len; i++)
-		buf[i] = data[i+2];
+		buf[i] = data[i + 2];
 
 	return EC_SUCCESS;
 }
@@ -594,7 +597,7 @@ static int board_battery_fix_otd_recovery_temp(uint32_t value)
 					      (uint8_t *)&otd_recovery_temp))
 			otd_recovery_temp_reg = otd_recovery_temp;
 	} else {
-			otd_recovery_temp_reg = otd_recovery_temp;
+		otd_recovery_temp_reg = otd_recovery_temp;
 	}
 
 	if (board_battery_seal()) {
diff --git a/board/eve/board.c b/board/eve/board.c
index fb0fc4b87a..9b7395b039 100644
--- a/board/eve/board.c
+++ b/board/eve/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -38,6 +38,7 @@
 #include "math_util.h"
 #include "motion_lid.h"
 #include "motion_sense.h"
+#include "panic.h"
 #include "power.h"
 #include "power_button.h"
 #include "pwm.h"
@@ -57,8 +58,8 @@
 #include "util.h"
 #include "espi.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
@@ -171,13 +172,13 @@ __override struct keyboard_scan_config keyscan_config = {
 
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT]     = { 5, 0, 10000 },
-	[PWM_CH_LED_L_RED]   = { 2, PWM_CONFIG_DSLEEP, 100 },
+	[PWM_CH_KBLIGHT] = { 5, 0, 10000 },
+	[PWM_CH_LED_L_RED] = { 2, PWM_CONFIG_DSLEEP, 100 },
 	[PWM_CH_LED_L_GREEN] = { 3, PWM_CONFIG_DSLEEP, 100 },
-	[PWM_CH_LED_L_BLUE]  = { 4, PWM_CONFIG_DSLEEP, 100 },
-	[PWM_CH_LED_R_RED]   = { 1, PWM_CONFIG_DSLEEP, 100 },
+	[PWM_CH_LED_L_BLUE] = { 4, PWM_CONFIG_DSLEEP, 100 },
+	[PWM_CH_LED_R_RED] = { 1, PWM_CONFIG_DSLEEP, 100 },
 	[PWM_CH_LED_R_GREEN] = { 0, PWM_CONFIG_DSLEEP, 100 },
-	[PWM_CH_LED_R_BLUE]  = { 6, PWM_CONFIG_DSLEEP, 100 },
+	[PWM_CH_LED_R_BLUE] = { 6, PWM_CONFIG_DSLEEP, 100 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
@@ -190,42 +191,32 @@ const enum gpio_signal hibernate_wake_pins[] = {
 const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 
 /* I2C port map */
-const struct i2c_port_t i2c_ports[]  = {
-	{
-		.name = "tcpc0",
-		.port = I2C_PORT_TCPC0,
-		.kbps = 400,
-		.scl  = GPIO_I2C0_0_SCL,
-		.sda  = GPIO_I2C0_0_SDA
-	},
-	{
-		.name = "tcpc1",
-		.port = I2C_PORT_TCPC1,
-		.kbps = 400,
-		.scl  = GPIO_I2C0_1_SCL,
-		.sda  = GPIO_I2C0_1_SDA
-	},
-	{
-		.name = "accelgyro",
-		.port = I2C_PORT_GYRO,
-		.kbps = 400,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	},
-	{
-		.name = "sensors",
-		.port = I2C_PORT_LID_ACCEL,
-		.kbps = 400,
-		.scl  = GPIO_I2C2_SCL,
-		.sda  = GPIO_I2C2_SDA
-	},
-	{
-		.name = "batt",
-		.port = I2C_PORT_BATTERY,
-		.kbps = 100,
-		.scl  = GPIO_I2C3_SCL,
-		.sda  = GPIO_I2C3_SDA
-	},
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_0_SCL,
+	  .sda = GPIO_I2C0_0_SDA },
+	{ .name = "tcpc1",
+	  .port = I2C_PORT_TCPC1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_1_SCL,
+	  .sda = GPIO_I2C0_1_SDA },
+	{ .name = "accelgyro",
+	  .port = I2C_PORT_GYRO,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "sensors",
+	  .port = I2C_PORT_LID_ACCEL,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "batt",
+	  .port = I2C_PORT_BATTERY,
+	  .kbps = 100,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -249,16 +240,22 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.driver = &anx74xx_tcpm_usb_mux_driver,
-		.hpd_update = &anx74xx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &anx74xx_tcpm_usb_mux_driver,
+				.hpd_update = &anx74xx_tcpc_update_hpd_status,
+			},
 	},
 	{
-		.usb_port = 1,
-		.driver = &anx74xx_tcpm_usb_mux_driver,
-		.hpd_update = &anx74xx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.driver = &anx74xx_tcpm_usb_mux_driver,
+				.hpd_update = &anx74xx_tcpc_update_hpd_status,
+			},
 	},
 };
 
@@ -360,7 +357,7 @@ void board_tcpc_init(void)
 	 */
 	for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
 		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
 
 uint16_t tcpc_get_alert_status(void)
@@ -381,18 +378,18 @@ uint16_t tcpc_get_alert_status(void)
 }
 
 const struct temp_sensor_t temp_sensors[] = {
-	{"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0},
+	{ "Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0 },
 
 	/* These BD99992GW temp sensors are only readable in S0 */
-	{"Ambient", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM0},
-	{"Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM1},
-	{"DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM2},
-	{"eMMC", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM3},
-	{"Gyro", TEMP_SENSOR_TYPE_BOARD, bmi160_get_sensor_temp, BASE_GYRO},
+	{ "Ambient", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM0 },
+	{ "Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM1 },
+	{ "DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM2 },
+	{ "eMMC", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM3 },
+	{ "Gyro", TEMP_SENSOR_TYPE_BOARD, bmi160_get_sensor_temp, BASE_GYRO },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -408,8 +405,8 @@ static void board_report_pmic_fault(const char *str)
 	uint32_t info;
 
 	/* RESETIRQ1 -- Bit 4: VRFAULT */
-	if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x8, &vrfault)
-	    != EC_SUCCESS)
+	if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x8, &vrfault) !=
+	    EC_SUCCESS)
 		return;
 
 	if (!(vrfault & BIT(4)))
@@ -636,8 +633,8 @@ int board_set_active_charge_port(int charge_port)
  * @param charge_ma     Desired charge limit (mA).
  * @param charge_mv     Negotiated charge voltage (mV).
  */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	/* Enable charging trigger by BC1.2 detection */
 	int bc12_enable = (supplier == CHARGE_SUPPLIER_BC12_CDP ||
@@ -649,8 +646,8 @@ void board_set_charge_limit(int port, int supplier, int charge_ma,
 		return;
 
 	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-				   CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 /**
@@ -719,7 +716,7 @@ __override void lid_angle_peripheral_enable(int enable)
 	 * which might be faulty. Disable keyboard and trackpad wake.
 	 */
 	if (chipset_in_state(CHIPSET_STATE_ANY_OFF) ||
-	   (tablet_get_mode() && chipset_in_state(CHIPSET_STATE_SUSPEND)))
+	    (tablet_get_mode() && chipset_in_state(CHIPSET_STATE_SUSPEND)))
 		enable = 0;
 	keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
 
@@ -851,36 +848,30 @@ static struct mutex g_lid_mutex;
 static struct kionix_accel_data g_kxcj9_data;
 static struct bmi_drv_data_t g_bmi160_data;
 
-static struct si114x_drv_data_t g_si114x_data = {
-	.state = SI114X_NOT_READY,
-	.covered = 0,
-	.type_data = {
-		/* Proximity - unused */
-		{
-		},
-		/* light */
-		{
-			.base_data_reg = SI114X_ALS_VIS_DATA0,
-			.irq_flags = SI114X_IRQ_ENABLE_ALS_IE_INT0 |
-				     SI114X_IRQ_ENABLE_ALS_IE_INT1,
-			.scale = 1,
-			.offset = -256,
-		}
-	}
-};
+static struct si114x_drv_data_t
+	g_si114x_data = { .state = SI114X_NOT_READY,
+			  .covered = 0,
+			  .type_data = {
+				  /* Proximity - unused */
+				  {},
+				  /* light */
+				  {
+					  .base_data_reg = SI114X_ALS_VIS_DATA0,
+					  .irq_flags =
+						  SI114X_IRQ_ENABLE_ALS_IE_INT0 |
+						  SI114X_IRQ_ENABLE_ALS_IE_INT1,
+					  .scale = 1,
+					  .offset = -256,
+				  } } };
 
 /* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t mag_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0,  FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t mag_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				      { 0, FLOAT_TO_FP(1), 0 },
+				      { 0, 0, FLOAT_TO_FP(-1) } };
 
-const mat33_fp_t lid_standard_ref = {
-	{FLOAT_TO_FP(-1),  0,  0},
-	{ 0,  FLOAT_TO_FP(-1), 0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				      { 0, FLOAT_TO_FP(-1), 0 },
+				      { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
diff --git a/board/eve/board.h b/board/eve/board.h
index c1549becfb..defc3e746e 100644
--- a/board/eve/board.h
+++ b/board/eve/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,7 +12,7 @@
  * By default, enable all console messages excepted HC, ACPI and event:
  * The sensor stack is generating a lot of activity.
  */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
 #undef CONFIG_HOSTCMD_DEBUG_MODE
 #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
 
@@ -26,7 +26,7 @@
 #define CONFIG_FLASH_SIZE_BYTES 0x80000
 #define CONFIG_FPU
 /* 7 day delay before hibernate */
-#undef  CONFIG_HIBERNATE_DELAY_SEC
+#undef CONFIG_HIBERNATE_DELAY_SEC
 #define CONFIG_HIBERNATE_DELAY_SEC (3600 * 24 * 7)
 /* 1 day delay before hibernate if battery is less than 10% */
 #define CONFIG_HIBERNATE_BATT_PCT 10
@@ -65,7 +65,7 @@
 #define CONFIG_HOSTCMD_PD_CONTROL
 
 /* EC console history configuration */
-#undef  CONFIG_CONSOLE_HISTORY
+#undef CONFIG_CONSOLE_HISTORY
 #define CONFIG_CONSOLE_HISTORY 1
 
 /* SOC */
@@ -73,12 +73,12 @@
 #define CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET
 #define CONFIG_CHIPSET_RESET_HOOK
 #define CONFIG_HOST_INTERFACE_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 #define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD
 
 #define CONFIG_KEYBOARD_COL2_INVERTED
-#undef  CONFIG_KEYBOARD_VIVALDI
+#undef CONFIG_KEYBOARD_VIVALDI
 #define CONFIG_KEYBOARD_PROTOCOL_8042
 #define CONFIG_KEYBOARD_REFRESH_ROW3
 #define CONFIG_TABLET_MODE
@@ -108,12 +108,12 @@
 #define CONFIG_CHARGER_SENSE_RESISTOR 10
 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 #define BD9995X_IOUT_GAIN_SELECT \
-		BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V
+	BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V
 #define BD9995X_PSYS_GAIN_SELECT \
-		BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_02UAW
+	BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_02UAW
 #define CONFIG_EXTPOWER_GPIO
-#undef   CONFIG_EXTPOWER_DEBOUNCE_MS
-#define  CONFIG_EXTPOWER_DEBOUNCE_MS 1000
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
+#define CONFIG_EXTPOWER_DEBOUNCE_MS 1000
 #define CONFIG_POWER_BUTTON
 #define CONFIG_POWER_BUTTON_X86
 #define CONFIG_POWER_COMMON
@@ -138,7 +138,7 @@
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 #define CONFIG_ACCELGYRO_SEC_ADDR_FLAGS BMM150_ADDR0_FLAGS
-#define CONFIG_ACCELGYRO_BMI160_INT2_OUTPUT  /* Unused */
+#define CONFIG_ACCELGYRO_BMI160_INT2_OUTPUT /* Unused */
 #define CONFIG_MAG_CALIBRATE
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_INVALID_CHECK
@@ -195,26 +195,26 @@
 #define CONFIG_USBC_VCONN_SWAP
 
 /* Optional feature to configure npcx chip */
-#define NPCX_UART_MODULE2	1 /* 1:GPIO64/65 as UART */
-#define NPCX_JTAG_MODULE2	0 /* 0:GPIO21/17/16/20 as JTAG */
-#define NPCX_TACH_SEL2		0 /* 0:GPIO40/73 as TACH */
+#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART */
+#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 as JTAG */
+#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 as TACH */
 
 /* I2C ports */
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT0_0
-#define I2C_PORT_TCPC1		NPCX_I2C_PORT0_1
-#define I2C_PORT_GYRO		NPCX_I2C_PORT1
-#define I2C_PORT_ACCEL		I2C_PORT_GYRO
-#define I2C_PORT_LID_ACCEL	NPCX_I2C_PORT2
-#define I2C_PORT_ALS		NPCX_I2C_PORT2
-#define I2C_PORT_PMIC		NPCX_I2C_PORT3
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT3
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT3
-#define I2C_PORT_THERMAL	I2C_PORT_PMIC
-#define I2C_PORT_MP2949		NPCX_I2C_PORT3
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0
+#define I2C_PORT_TCPC1 NPCX_I2C_PORT0_1
+#define I2C_PORT_GYRO NPCX_I2C_PORT1
+#define I2C_PORT_ACCEL I2C_PORT_GYRO
+#define I2C_PORT_LID_ACCEL NPCX_I2C_PORT2
+#define I2C_PORT_ALS NPCX_I2C_PORT2
+#define I2C_PORT_PMIC NPCX_I2C_PORT3
+#define I2C_PORT_BATTERY NPCX_I2C_PORT3
+#define I2C_PORT_CHARGER NPCX_I2C_PORT3
+#define I2C_PORT_THERMAL I2C_PORT_PMIC
+#define I2C_PORT_MP2949 NPCX_I2C_PORT3
 
 /* I2C addresses */
-#define I2C_ADDR_BD99992_FLAGS	0x30
-#define I2C_ADDR_MP2949_FLAGS	0x20
+#define I2C_ADDR_BD99992_FLAGS 0x30
+#define I2C_ADDR_MP2949_FLAGS 0x20
 
 #ifndef __ASSEMBLER__
 
@@ -234,11 +234,11 @@ enum board_version_list {
 };
 
 enum temp_sensor_id {
-	TEMP_SENSOR_BATTERY,	/* BD99956GW TSENSE */
-	TEMP_SENSOR_AMBIENT,	/* BD99992GW SYSTHERM0 */
-	TEMP_SENSOR_CHARGER,	/* BD99992GW SYSTHERM1 */
-	TEMP_SENSOR_DRAM,	/* BD99992GW SYSTHERM2 */
-	TEMP_SENSOR_EMMC,	/* BD99992GW SYSTHERM3 */
+	TEMP_SENSOR_BATTERY, /* BD99956GW TSENSE */
+	TEMP_SENSOR_AMBIENT, /* BD99992GW SYSTHERM0 */
+	TEMP_SENSOR_CHARGER, /* BD99992GW SYSTHERM1 */
+	TEMP_SENSOR_DRAM, /* BD99992GW SYSTHERM2 */
+	TEMP_SENSOR_EMMC, /* BD99992GW SYSTHERM3 */
 	TEMP_SENSOR_GYRO,
 	TEMP_SENSOR_COUNT
 };
@@ -282,24 +282,22 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum adc_channel {
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_CH_COUNT };
 
 /*
  * delay to turn on the power supply max is ~16ms.
  * delay to turn off the power supply max is about ~180ms.
  */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	250000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* delay to turn on/off vconn */
 
 /* Define typical operating power and max power */
-#define PD_OPERATING_POWER_MW		15000
-#define PD_MAX_POWER_MW			45000
-#define PD_MAX_CURRENT_MA		3000
-#define PD_MAX_VOLTAGE_MV		20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 45000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Board specific handlers */
 int board_get_version(void);
diff --git a/board/eve/build.mk b/board/eve/build.mk
index f47b5d9caf..0913dd9370 100644
--- a/board/eve/build.mk
+++ b/board/eve/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/eve/ec.tasklist b/board/eve/ec.tasklist
index 99de365243..75e5f918c5 100644
--- a/board/eve/ec.tasklist
+++ b/board/eve/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/eve/gpio.inc b/board/eve/gpio.inc
index f9b0c3cfc4..6bf357f0c3 100644
--- a/board/eve/gpio.inc
+++ b/board/eve/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/eve/led.c b/board/eve/led.c
index 91a7b24a2b..9fe3becabd 100644
--- a/board/eve/led.c
+++ b/board/eve/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,8 +19,8 @@
 #include "task.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_PWM, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_PWM, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_PWM, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_PWM, format, ##args)
 
 #define LED_TICK_TIME (500 * MSEC)
 #define LED_TICKS_PER_BEAT 1
@@ -37,7 +37,9 @@
  * (120, .5, .33). For the transitions of interest only S and I are changed and
  * they are changed linearly in HSI space.
  */
-static const uint8_t trans_steps[] = {0, 4, 9, 16, 24, 33, 44, 56, 69, 84, 100};
+static const uint8_t trans_steps[] = {
+	0, 4, 9, 16, 24, 33, 44, 56, 69, 84, 100
+};
 
 /* List of LED colors used */
 enum led_color {
@@ -65,11 +67,7 @@ enum led_pattern {
 	LED_NUM_PATTERNS,
 };
 
-enum led_side {
-	LED_LEFT = 0,
-	LED_RIGHT,
-	LED_BOTH
-};
+enum led_side { LED_LEFT = 0, LED_RIGHT, LED_BOTH };
 
 struct led_info {
 	/* LED pattern manage variables */
@@ -101,8 +99,8 @@ static int double_tap;
 static int led_charge_side;
 static struct led_info led[LED_BOTH];
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_LEFT_LED, EC_LED_ID_RIGHT_LED};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_LEFT_LED,
+					     EC_LED_ID_RIGHT_LED };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 /*
@@ -110,16 +108,18 @@ const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
  * particular pattern never changes from the first phase.
  */
 static const struct led_phase pattern[LED_NUM_PATTERNS] = {
-	{ {LED_OFF, LED_OFF}, {0, 0}, DOUBLE_TAP_TICK_LEN },
-	{ {LED_GREEN, LED_GREEN}, {0, 0}, DOUBLE_TAP_TICK_LEN },
-	{ {LED_WHITE, LED_GREEN}, {2, 4}, DOUBLE_TAP_TICK_LEN },
-	{ {LED_WHITE, LED_WHITE}, {0, 0}, DOUBLE_TAP_TICK_LEN },
-	{ {LED_WHITE, LED_RED}, {2, 4}, DOUBLE_TAP_TICK_LEN },
-	{ {LED_RED, LED_RED}, {0, 0},  DOUBLE_TAP_TICK_LEN},
-	{ {LED_RED, LED_RED_HALF}, {4, 4}, DOUBLE_TAP_TICK_LEN * 2 +
-	  DOUBLE_TAP_TICK_LEN / 2},
-	{ {LED_RED, LED_OFF}, {1, 5}, DOUBLE_TAP_TICK_LEN * 3 +
-	  DOUBLE_TAP_TICK_LEN / 2},
+	{ { LED_OFF, LED_OFF }, { 0, 0 }, DOUBLE_TAP_TICK_LEN },
+	{ { LED_GREEN, LED_GREEN }, { 0, 0 }, DOUBLE_TAP_TICK_LEN },
+	{ { LED_WHITE, LED_GREEN }, { 2, 4 }, DOUBLE_TAP_TICK_LEN },
+	{ { LED_WHITE, LED_WHITE }, { 0, 0 }, DOUBLE_TAP_TICK_LEN },
+	{ { LED_WHITE, LED_RED }, { 2, 4 }, DOUBLE_TAP_TICK_LEN },
+	{ { LED_RED, LED_RED }, { 0, 0 }, DOUBLE_TAP_TICK_LEN },
+	{ { LED_RED, LED_RED_HALF },
+	  { 4, 4 },
+	  DOUBLE_TAP_TICK_LEN * 2 + DOUBLE_TAP_TICK_LEN / 2 },
+	{ { LED_RED, LED_OFF },
+	  { 1, 5 },
+	  DOUBLE_TAP_TICK_LEN * 3 + DOUBLE_TAP_TICK_LEN / 2 },
 };
 
 /*
@@ -129,12 +129,9 @@ static const struct led_phase pattern[LED_NUM_PATTERNS] = {
 #define PWM_CHAN_PER_LED 3
 static const uint8_t color_brightness[LED_COLOR_COUNT][PWM_CHAN_PER_LED] = {
 	/* {Red, Green, Blue}, */
-	[LED_OFF]   = {0, 0, 0},
-	[LED_RED]   = {80,  0, 0},
-	[LED_GREEN] = {0, 80, 0},
-	[LED_BLUE] = {0, 0, 80},
-	[LED_WHITE]  = {100, 100, 100},
-	[LED_RED_HALF]  = {40, 0, 0},
+	[LED_OFF] = { 0, 0, 0 },	 [LED_RED] = { 80, 0, 0 },
+	[LED_GREEN] = { 0, 80, 0 },	 [LED_BLUE] = { 0, 0, 80 },
+	[LED_WHITE] = { 100, 100, 100 }, [LED_RED_HALF] = { 40, 0, 0 },
 };
 
 /*
@@ -153,13 +150,13 @@ struct range_map {
 #error "LED: PULSE_RED battery level <= BLINK_RED level"
 #endif
 static const struct range_map pattern_tbl[] = {
-	{CONFIG_USB_PD_TRY_SRC_MIN_BATT_SOC - 1, BLINK_RED},
-	{5, PULSE_RED},
-	{15, SOLID_RED},
-	{25, WHITE_RED},
-	{75, SOLID_WHITE},
-	{95, WHITE_GREEN},
-	{100, SOLID_GREEN},
+	{ CONFIG_USB_PD_TRY_SRC_MIN_BATT_SOC - 1, BLINK_RED },
+	{ 5, PULSE_RED },
+	{ 15, SOLID_RED },
+	{ 25, WHITE_RED },
+	{ 75, SOLID_WHITE },
+	{ 95, WHITE_GREEN },
+	{ 100, SOLID_GREEN },
 };
 
 enum led_state_change {
@@ -323,18 +320,17 @@ static void led_setup_color_change(int old_idx, int new_idx, enum led_side side)
 		 */
 		total_change = ABS(led[side].rgb_current[rgb_index] -
 				   led[side].rgb_target[rgb_index]);
-		delta_per_step = (total_change << LED_FRAC_BITS)
-			/ (ARRAY_SIZE(trans_steps) - 1);
+		delta_per_step = (total_change << LED_FRAC_BITS) /
+				 (ARRAY_SIZE(trans_steps) - 1);
 		step_value = 0;
 		for (i = 0; i < ARRAY_SIZE(trans_steps); i++) {
-			led[side].trans[i] = start_lvl +
-				((step_value +
-				  (1 << (LED_FRAC_BITS - 1)))
-				 >> LED_FRAC_BITS);
+			led[side].trans[i] =
+				start_lvl +
+				((step_value + (1 << (LED_FRAC_BITS - 1))) >>
+				 LED_FRAC_BITS);
 			step_value += delta_per_step;
 		}
 	}
-
 }
 
 static void led_adjust_color_step(int side)
@@ -397,12 +393,10 @@ static void led_change_color(void)
 	/* Will loop here until the color change is complete. */
 	while (led[LED_LEFT].state != LED_STATE_DONE ||
 	       led[LED_RIGHT].state != LED_STATE_DONE) {
-
 		for (i = 0; i < LED_BOTH; i++) {
 			if (led[i].state != LED_STATE_DONE)
 				/* Move one step in the transition table */
 				led_adjust_color_step(i);
-
 		}
 		msleep(LED_STEP_MSEC);
 	}
@@ -427,14 +421,19 @@ static void led_manage_patterns(enum led_pattern *pattern_desired, int tap)
 			 */
 			if (i == led_charge_side || !led[i].tap_tick_count) {
 				led[i].ticks = 0;
-				led[i].tap_tick_count = tap ?
-					pattern[pattern_desired[i]].tap_len : 0;
+				led[i].tap_tick_count =
+					tap ? pattern[pattern_desired[i]]
+							.tap_len :
+					      0;
 				led[i].pattern_sel = pattern_desired[i];
 			}
 		}
 		/* Determine pattern phase and color for current phase */
 		phase = led[i].ticks < LED_TICKS_PER_BEAT *
-			pattern[led[i].pattern_sel].len[0] ? 0 : 1;
+						pattern[led[i].pattern_sel]
+							.len[0] ?
+				0 :
+				1;
 		color = pattern[led[i].pattern_sel].color[phase];
 		/* If color is changing, then setup the transition. */
 		if (led[i].color != color) {
@@ -458,9 +457,10 @@ static void led_manage_patterns(enum led_pattern *pattern_desired, int tap)
 		 * count.
 		 */
 		if (pattern[led[i].pattern_sel].len[0])
-			if (++led[i].ticks == LED_TICKS_PER_BEAT *
-			    (pattern[led[i].pattern_sel].len[0] +
-			     pattern[led[i].pattern_sel].len[1]))
+			if (++led[i].ticks ==
+			    LED_TICKS_PER_BEAT *
+				    (pattern[led[i].pattern_sel].len[0] +
+				     pattern[led[i].pattern_sel].len[1]))
 				led[i].ticks = 0;
 
 		/* If double tap display is active, decrement its counter */
@@ -535,8 +535,8 @@ static void led_select_pattern(enum led_pattern *pattern_desired, int tap)
 		 * charging side LED.
 		 */
 		if (chg_state == PWR_STATE_CHARGE_NEAR_FULL ||
-		    ((chg_state == PWR_STATE_DISCHARGE_FULL)
-		     && extpower_is_present())) {
+		    ((chg_state == PWR_STATE_DISCHARGE_FULL) &&
+		     extpower_is_present())) {
 			new_pattern = SOLID_GREEN;
 		} else if (chg_state == PWR_STATE_CHARGE) {
 			new_pattern = SOLID_WHITE;
@@ -586,7 +586,6 @@ static void led_init(void)
 		led[i].tap_tick_count = 0;
 		led[i].state = LED_STATE_DONE;
 	}
-
 }
 
 void led_task(void *u)
@@ -633,7 +632,7 @@ void led_task(void *u)
 
 /******************************************************************/
 /* Console commands */
-static int command_led(int argc, char **argv)
+static int command_led(int argc, const char **argv)
 {
 	int side = LED_BOTH;
 	char *e;
diff --git a/board/eve/usb_pd_policy.c b/board/eve/usb_pd_policy.c
index d6dd5ad1be..729cdfa018 100644
--- a/board/eve/usb_pd_policy.c
+++ b/board/eve/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,12 +23,12 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT];
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5,
-							TYPEC_RP_1A5};
+static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5,
+							 TYPEC_RP_1A5 };
 
 int board_vbus_source_enabled(int port)
 {
@@ -38,9 +38,9 @@ int board_vbus_source_enabled(int port)
 static void board_vbus_update_source_current(int port)
 {
 	enum gpio_signal gpio_5v_en = port ? GPIO_USB_C1_5V_EN :
-		GPIO_USB_C0_5V_EN;
+					     GPIO_USB_C0_5V_EN;
 	enum gpio_signal gpio_3a_en = port ? GPIO_EN_USB_C1_3A :
-		GPIO_EN_USB_C0_3A;
+					     GPIO_EN_USB_C0_3A;
 	int flags;
 
 	if (system_get_board_version() >= BOARD_VERSION_P1B) {
@@ -50,8 +50,8 @@ static void board_vbus_update_source_current(int port)
 		 * is controlled by GPIO_USB_C0/1_5V_EN. Both of these signals
 		 * can remain outputs.
 		 */
-		gpio_set_level(gpio_3a_en, vbus_rp[port] == TYPEC_RP_3A0 ?
-			       1 : 0);
+		gpio_set_level(gpio_3a_en,
+			       vbus_rp[port] == TYPEC_RP_3A0 ? 1 : 0);
 		gpio_set_level(gpio_5v_en, vbus_en[port]);
 	} else {
 		/*
@@ -65,8 +65,8 @@ static void board_vbus_update_source_current(int port)
 		 * 1505 mA.
 		 */
 		flags = (vbus_rp[port] == TYPEC_RP_1A5 && vbus_en[port]) ?
-			(GPIO_INPUT | GPIO_PULL_UP) :
-			(GPIO_OUTPUT | GPIO_PULL_UP);
+				(GPIO_INPUT | GPIO_PULL_UP) :
+				(GPIO_OUTPUT | GPIO_PULL_UP);
 		gpio_set_level(gpio_5v_en, vbus_en[port]);
 		gpio_set_flags(gpio_5v_en, flags);
 	}
@@ -120,15 +120,13 @@ int pd_check_vconn_swap(int port)
 	return gpio_get_level(GPIO_PMIC_SLP_SUS_L);
 }
 
-void pd_execute_data_swap(int port,
-			  enum pd_data_role data_role)
+void pd_execute_data_swap(int port, enum pd_data_role data_role)
 {
 	/* Only port 0 supports device mode. */
 	if (port != 0)
 		return;
 
-	gpio_set_level(GPIO_USB2_OTG_ID,
-		      (data_role == PD_ROLE_UFP) ? 1 : 0);
+	gpio_set_level(GPIO_USB2_OTG_ID, (data_role == PD_ROLE_UFP) ? 1 : 0);
 	gpio_set_level(GPIO_USB2_OTG_VBUSSENSE,
-		      (data_role == PD_ROLE_UFP) ? 1 : 0);
+		       (data_role == PD_ROLE_UFP) ? 1 : 0);
 }
diff --git a/board/ezkinil/battery.c b/board/ezkinil/battery.c
index 8c5ec9e1d7..1260b428ae 100644
--- a/board/ezkinil/battery.c
+++ b/board/ezkinil/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/ezkinil/board.c b/board/ezkinil/board.c
index 46757d22f3..c9e1aca267 100644
--- a/board/ezkinil/board.c
+++ b/board/ezkinil/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,7 +14,7 @@
 #include "driver/accelgyro_icm426xx.h"
 #include "driver/accel_kionix.h"
 #include "driver/accel_kx022.h"
-#include "driver/ppc/aoz1380.h"
+#include "driver/ppc/aoz1380_public.h"
 #include "driver/ppc/nx20p348x.h"
 #include "driver/retimer/pi3hdx1204.h"
 #include "driver/retimer/tusb544.h"
@@ -50,17 +50,16 @@ static int board_ver;
  * that we don't have pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-	{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-	{0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3},
-	{-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0},
-	{1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4},
-	{2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0},
-	{-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1},
-	{-1, -1},
+	{ -1, -1 }, { 0, 5 },	{ 1, 1 }, { 1, 0 },   { 0, 6 },	  { 0, 7 },
+	{ -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 },   { -1, -1 }, { 1, 6 },
+	{ 1, 7 },   { 3, 1 },	{ 2, 0 }, { 1, 5 },   { 2, 6 },	  { 2, 7 },
+	{ 2, 1 },   { 2, 4 },	{ 2, 5 }, { 1, 2 },   { 2, 3 },	  { 2, 2 },
+	{ 3, 0 },   { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 },	  { -1, -1 },
+	{ -1, -1 },
 };
 
 const int keyboard_factory_scan_pins_used =
-		ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 
 /* Motion sensors */
 static struct mutex g_lid_mutex;
@@ -72,21 +71,15 @@ static struct bmi_drv_data_t g_bmi160_data;
 static struct icm_drv_data_t g_icm426xx_data;
 
 /* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(-1), 0,  0},
-	{ 0, 0,  FLOAT_TO_FP(-1)}
-};
-const mat33_fp_t base_standard_ref_1 = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0,  FLOAT_TO_FP(-1)}
-};
-const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0,  0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+				       { FLOAT_TO_FP(-1), 0, 0 },
+				       { 0, 0, FLOAT_TO_FP(-1) } };
+const mat33_fp_t base_standard_ref_1 = { { FLOAT_TO_FP(1), 0, 0 },
+					 { 0, FLOAT_TO_FP(-1), 0 },
+					 { 0, 0, FLOAT_TO_FP(-1) } };
+const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				      { 0, FLOAT_TO_FP(-1), 0 },
+				      { 0, 0, FLOAT_TO_FP(1) } };
 
 /* TODO(gcc >= 5.0) Remove the casts to const pointer at rot_standard_ref */
 struct motion_sensor_t motion_sensors[] = {
@@ -211,7 +204,6 @@ struct motion_sensor_t icm426xx_base_gyro = {
 	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
 };
 
-
 struct motion_sensor_t icm42607_base_accel = {
 	.name = "Base Accel",
 	.active_mask = SENSOR_ACTIVE_S0_S3,
@@ -347,9 +339,12 @@ const struct usb_mux_driver usbc0_sbu_mux_driver = {
  * Since FSUSB42UMX is not a i2c device, .i2c_port and
  * .i2c_addr_flags are not required here.
  */
-const struct usb_mux usbc0_sbu_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &usbc0_sbu_mux_driver,
+const struct usb_mux_chain usbc0_sbu_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &usbc0_sbu_mux_driver,
+		},
 };
 
 /*****************************************************************************
@@ -394,6 +389,9 @@ void motion_interrupt(enum gpio_signal signal)
  * USB-C MUX/Retimer dynamic configuration
  */
 
+/* Place holder for second mux in USBC1 chain */
+struct usb_mux_chain usbc1_mux1;
+
 int board_usbc1_retimer_inhpd = IOEX_USB_C1_HPD_IN_DB;
 
 static void setup_mux(void)
@@ -411,11 +409,9 @@ static void setup_mux(void)
 		 * Replace usb_muxes[USBC_PORT_C1] with the AMD FP5
 		 * table entry.
 		 */
-		memcpy(&usb_muxes[USBC_PORT_C1],
-		       &usbc1_amd_fp5_usb_mux,
-		       sizeof(struct usb_mux));
+		usb_muxes[USBC_PORT_C1].mux = &usbc1_amd_fp5_usb_mux;
 		/* Set the PS8818 as the secondary MUX */
-		usb_muxes[USBC_PORT_C1].next_mux = &usbc1_ps8818;
+		usbc1_mux1.mux = &usbc1_ps8818;
 	} else if (mux == SSFC_C1_MUX_TUSB544) {
 		ccprints("C1 TUSB544 detected");
 		/*
@@ -424,11 +420,9 @@ static void setup_mux(void)
 		 * Replace usb_muxes[USBC_PORT_C1] with the AMD FP5
 		 * table entry.
 		 */
-		memcpy(&usb_muxes[USBC_PORT_C1],
-		       &usbc1_amd_fp5_usb_mux,
-		       sizeof(struct usb_mux));
+		usb_muxes[USBC_PORT_C1].mux = &usbc1_amd_fp5_usb_mux;
 		/* Set the TUSB544 as the secondary MUX */
-		usb_muxes[USBC_PORT_C1].next_mux = &usbc1_tusb544;
+		usbc1_mux1.mux = &usbc1_tusb544;
 	} else if (ec_config_has_usbc1_retimer_ps8743()) {
 		ccprints("C1 PS8743 detected");
 		/*
@@ -437,32 +431,33 @@ static void setup_mux(void)
 		 * Replace usb_muxes[USBC_PORT_C1] with the PS8743
 		 * table entry.
 		 */
-		memcpy(&usb_muxes[USBC_PORT_C1],
-		       &usbc1_ps8743,
-		       sizeof(struct usb_mux));
+		usb_muxes[USBC_PORT_C1].mux = &usbc1_ps8743;
 		/* Set the AMD FP5 as the secondary MUX */
-		usb_muxes[USBC_PORT_C1].next_mux = &usbc1_amd_fp5_usb_mux;
+		usbc1_mux1.mux = &usbc1_amd_fp5_usb_mux;
 		/* Don't have the AMD FP5 flip */
 		usbc1_amd_fp5_usb_mux.flags = USB_MUX_FLAG_SET_WITHOUT_FLIP;
 	}
 }
 
-struct usb_mux usb_muxes[] = {
+struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.i2c_port = I2C_PORT_USB_AP_MUX,
-		.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
-		.driver = &amd_fp5_usb_mux_driver,
-		.next_mux = &usbc0_sbu_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.i2c_port = I2C_PORT_USB_AP_MUX,
+			.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
+			.driver = &amd_fp5_usb_mux_driver,
+		},
+		.next = &usbc0_sbu_mux,
 	},
 	[USBC_PORT_C1] = {
 		/* Filled in dynamically at startup */
+		.next = &usbc1_mux1,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
 
 static int board_tusb544_mux_set(const struct usb_mux *me,
-				mux_state_t mux_state)
+				 mux_state_t mux_state)
 {
 	if (mux_state & USB_PD_MUX_DP_ENABLED) {
 		/* Enable IN_HPD on the DB */
@@ -474,8 +469,7 @@ static int board_tusb544_mux_set(const struct usb_mux *me,
 	return EC_SUCCESS;
 }
 
-static int board_ps8743_mux_set(const struct usb_mux *me,
-				mux_state_t mux_state)
+static int board_ps8743_mux_set(const struct usb_mux *me, mux_state_t mux_state)
 {
 	if (mux_state & USB_PD_MUX_DP_ENABLED)
 		/* Enable IN_HPD on the DB */
@@ -543,15 +537,15 @@ __override void ppc_interrupt(enum gpio_signal signal)
 	}
 }
 
-__override int board_aoz1380_set_vbus_source_current_limit(int port,
-						enum tcpc_rp_value rp)
+__override int
+board_aoz1380_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp)
 {
 	int rv;
 
 	/* Use the TCPC to set the current limit */
-	rv = ioex_set_level(port ? IOEX_USB_C1_PPC_ILIM_3A_EN
-				: IOEX_USB_C0_PPC_ILIM_3A_EN,
-				(rp == TYPEC_RP_3A0) ? 1 : 0);
+	rv = ioex_set_level(port ? IOEX_USB_C1_PPC_ILIM_3A_EN :
+				   IOEX_USB_C0_PPC_ILIM_3A_EN,
+			    (rp == TYPEC_RP_3A0) ? 1 : 0);
 
 	return rv;
 }
@@ -621,10 +615,9 @@ static void hdmi_hpd_handler(void)
 
 	gpio_set_level(GPIO_DP1_HPD, hpd);
 	ccprints("HDMI HPD %d", hpd);
-	pi3hdx1204_enable(I2C_PORT_TCPC1,
-			  PI3HDX1204_I2C_ADDR_FLAGS,
-			  chipset_in_or_transitioning_to_state(CHIPSET_STATE_ON)
-			  && hpd);
+	pi3hdx1204_enable(
+		I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS,
+		chipset_in_or_transitioning_to_state(CHIPSET_STATE_ON) && hpd);
 }
 DECLARE_DEFERRED(hdmi_hpd_handler);
 
@@ -652,8 +645,7 @@ static void board_chipset_resume(void)
 	if (ec_config_has_hdmi_retimer_pi3hdx1204()) {
 		ioex_set_level(IOEX_HDMI_POWER_EN_DB, 1);
 		msleep(PI3HDX1204_POWER_ON_DELAY_MS);
-		pi3hdx1204_enable(I2C_PORT_TCPC1,
-				  PI3HDX1204_I2C_ADDR_FLAGS,
+		pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS,
 				  check_hdmi_hpd_status());
 	}
 }
@@ -664,9 +656,7 @@ static void board_chipset_suspend(void)
 	ioex_set_level(IOEX_USB_A1_RETIMER_EN, 0);
 
 	if (ec_config_has_hdmi_retimer_pi3hdx1204()) {
-		pi3hdx1204_enable(I2C_PORT_TCPC1,
-				  PI3HDX1204_I2C_ADDR_FLAGS,
-				  0);
+		pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS, 0);
 		ioex_set_level(IOEX_HDMI_POWER_EN_DB, 0);
 	}
 
@@ -681,7 +671,7 @@ DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
 /* Physical fans. These are logically separate from pwm_channels. */
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = -1,
 };
@@ -772,8 +762,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_THERMISTOR \
-	{ \
+#define THERMAL_THERMISTOR       \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(85), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(95), \
@@ -790,8 +780,8 @@ __maybe_unused static const struct ec_thermal_config thermal_thermistor =
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_SOC \
-	{ \
+#define THERMAL_SOC              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
@@ -814,14 +804,14 @@ struct fan_step {
 
 /* Note: Do not make the fan on/off point equal to 0 or 100 */
 static const struct fan_step fan_table0[] = {
-	{.on =  0, .off =  1, .rpm = 0},
-	{.on =  9, .off =  1, .rpm = 3200},
-	{.on = 21, .off =  7, .rpm = 3500},
-	{.on = 28, .off = 16, .rpm = 3900},
-	{.on = 37, .off = 26, .rpm = 4200},
-	{.on = 47, .off = 35, .rpm = 4600},
-	{.on = 56, .off = 44, .rpm = 5100},
-	{.on = 72, .off = 60, .rpm = 5500},
+	{ .on = 0, .off = 1, .rpm = 0 },
+	{ .on = 9, .off = 1, .rpm = 3200 },
+	{ .on = 21, .off = 7, .rpm = 3500 },
+	{ .on = 28, .off = 16, .rpm = 3900 },
+	{ .on = 37, .off = 26, .rpm = 4200 },
+	{ .on = 47, .off = 35, .rpm = 4600 },
+	{ .on = 56, .off = 44, .rpm = 5100 },
+	{ .on = 72, .off = 60, .rpm = 5500 },
 };
 /* All fan tables must have the same number of levels */
 #define NUM_FAN_LEVELS ARRAY_SIZE(fan_table0)
@@ -867,8 +857,7 @@ int fan_percent_to_rpm(int fan, int pct)
 
 	previous_pct = pct;
 
-	if (fan_table[current_level].rpm !=
-		fan_get_rpm_target(FAN_CH(fan))) {
+	if (fan_table[current_level].rpm != fan_get_rpm_target(FAN_CH(fan))) {
 		cprints(CC_THERMAL, "Setting fan RPM to %d",
 			fan_table[current_level].rpm);
 		board_print_temps();
@@ -878,7 +867,7 @@ int fan_percent_to_rpm(int fan, int pct)
 }
 
 __override void board_set_charge_limit(int port, int supplier, int charge_ma,
-			int max_ma, int charge_mv)
+				       int max_ma, int charge_mv)
 {
 	/*
 	 * Limit the input current to 95% negotiated limit,
@@ -886,7 +875,6 @@ __override void board_set_charge_limit(int port, int supplier, int charge_ma,
 	 */
 	charge_ma = charge_ma * 95 / 100;
 
-	charge_set_input_current_limit(MAX(charge_ma,
-				CONFIG_CHARGER_INPUT_CURRENT),
-				charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
diff --git a/board/ezkinil/board.h b/board/ezkinil/board.h
index 72ccbc78d2..aa1fe065f4 100644
--- a/board/ezkinil/board.h
+++ b/board/ezkinil/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -40,38 +40,34 @@
 #define TUSB544_I2C_ADDR_FLAGS1 0x0F
 
 /* GPIO mapping from board specific name to EC common name. */
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_EC_BATT_PRES_ODL
-#define CONFIG_SCI_GPIO			GPIO_EC_FCH_SCI_ODL
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_AP_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT_L		GPIO_EC_EDP_BL_DISABLE
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_FCH_PWR_BTN_L
-#define GPIO_PCH_RSMRST_L		GPIO_EC_FCH_RSMRST_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S5_L		GPIO_SLP_S5_L
-#define GPIO_PCH_SYS_PWROK		GPIO_EC_FCH_PWROK
-#define GPIO_PCH_WAKE_L			GPIO_EC_FCH_WAKE_L
-#define GPIO_POWER_BUTTON_L		GPIO_EC_PWR_BTN_ODL
-#define GPIO_S0_PGOOD			GPIO_S0_PWROK_OD
-#define GPIO_S5_PGOOD			GPIO_EC_PWROK_OD
-#define GPIO_SYS_RESET_L		GPIO_EC_SYS_RST_L
-#define GPIO_VOLUME_DOWN_L		GPIO_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GPIO_DP1_HPD			GPIO_EC_DP1_HPD
-#define IOEX_HDMI_CONN_HPD_3V3_DB	IOEX_USB_C1_PPC_ILIM_3A_EN
+#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL
+#define CONFIG_SCI_GPIO GPIO_EC_FCH_SCI_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_AP_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_EDP_BL_DISABLE
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PCH_PWRBTN_L GPIO_EC_FCH_PWR_BTN_L
+#define GPIO_PCH_RSMRST_L GPIO_EC_FCH_RSMRST_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L
+#define GPIO_PCH_SYS_PWROK GPIO_EC_FCH_PWROK
+#define GPIO_PCH_WAKE_L GPIO_EC_FCH_WAKE_L
+#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL
+#define GPIO_S0_PGOOD GPIO_S0_PWROK_OD
+#define GPIO_S5_PGOOD GPIO_EC_PWROK_OD
+#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L
+#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
+#define GPIO_DP1_HPD GPIO_EC_DP1_HPD
+#define IOEX_HDMI_CONN_HPD_3V3_DB IOEX_USB_C1_PPC_ILIM_3A_EN
 
 #ifndef __ASSEMBLER__
 
-enum adc_channel {
-	ADC_TEMP_SENSOR_CHARGER,
-	ADC_TEMP_SENSOR_SOC,
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_TEMP_SENSOR_CHARGER, ADC_TEMP_SENSOR_SOC, ADC_CH_COUNT };
 
 enum battery_type {
 	BATTERY_AP19B8M,
@@ -85,11 +81,7 @@ enum mft_channel {
 	MFT_CH_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_FAN,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_FAN, PWM_CH_COUNT };
 
 enum temp_sensor_id {
 	TEMP_SENSOR_CHARGER = 0,
@@ -98,11 +90,7 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum usba_port {
-	USBA_PORT_A0 = 0,
-	USBA_PORT_A1,
-	USBA_PORT_COUNT
-};
+enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT };
 
 /*****************************************************************************
  * CBI EC FW Configuration
@@ -153,57 +141,46 @@ enum ec_cfg_usb_db_type {
 
 #include "cbi_ec_fw_config.h"
 
-#define HAS_USBA1_RETIMER_TUSB522 \
-			(BIT(EZKINIL_DB_T_OPT2_USBAC))
+#define HAS_USBA1_RETIMER_TUSB522 (BIT(EZKINIL_DB_T_OPT2_USBAC))
 
 static inline bool ec_config_has_usba1_retimer_tusb522(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_USBA1_RETIMER_TUSB522);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_USBA1_RETIMER_TUSB522);
 }
 
-#define HAS_USBC1_RETIMER_PS8743 \
-			(BIT(EZKINIL_DB_T_OPT2_USBAC))
+#define HAS_USBC1_RETIMER_PS8743 (BIT(EZKINIL_DB_T_OPT2_USBAC))
 
 static inline bool ec_config_has_usbc1_retimer_ps8743(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_USBC1_RETIMER_PS8743);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_USBC1_RETIMER_PS8743);
 }
 
-#define HAS_USBC1_RETIMER_TUSB544 \
-			(BIT(EZKINIL_DB_T_OPT1_USBC_HDMI))
+#define HAS_USBC1_RETIMER_TUSB544 (BIT(EZKINIL_DB_T_OPT1_USBC_HDMI))
 
 static inline bool ec_config_has_usbc1_retimer_tusb544(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_USBC1_RETIMER_TUSB544);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_USBC1_RETIMER_TUSB544);
 }
 
-#define HAS_HDMI_RETIMER_PI3HDX1204 \
-			(BIT(EZKINIL_DB_T_OPT1_USBC_HDMI))
+#define HAS_HDMI_RETIMER_PI3HDX1204 (BIT(EZKINIL_DB_T_OPT1_USBC_HDMI))
 
 static inline bool ec_config_has_hdmi_retimer_pi3hdx1204(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_HDMI_RETIMER_PI3HDX1204);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_HDMI_RETIMER_PI3HDX1204);
 }
 
-#define HAS_HDMI_CONN_HPD \
-			(BIT(EZKINIL_DB_T_OPT1_USBC_HDMI))
+#define HAS_HDMI_CONN_HPD (BIT(EZKINIL_DB_T_OPT1_USBC_HDMI))
 
 static inline bool ec_config_has_hdmi_conn_hpd(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_HDMI_CONN_HPD);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_HDMI_CONN_HPD);
 }
 
 /* TODO: Fill in with GPIO values */
-#define PORT_TO_HPD(port) ((port == 0) \
-	? GPIO_USB_C0_HPD \
-	: (ec_config_has_usbc1_retimer_ps8743()) \
-		? GPIO_DP1_HPD \
-		: GPIO_DP2_HPD)
+#define PORT_TO_HPD(port)                                           \
+	((port == 0)				? GPIO_USB_C0_HPD : \
+	 (ec_config_has_usbc1_retimer_ps8743()) ? GPIO_DP1_HPD :    \
+						  GPIO_DP2_HPD)
 
 extern const struct usb_mux usbc1_tusb544;
 extern const struct usb_mux usbc1_ps8818;
diff --git a/board/ezkinil/build.mk b/board/ezkinil/build.mk
index 1c0cbc4f63..45c71f962c 100644
--- a/board/ezkinil/build.mk
+++ b/board/ezkinil/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/ezkinil/ec.tasklist b/board/ezkinil/ec.tasklist
index d9c1606eb2..abc796f74f 100644
--- a/board/ezkinil/ec.tasklist
+++ b/board/ezkinil/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/ezkinil/gpio.inc b/board/ezkinil/gpio.inc
index 8e75ec9975..4ea6712424 100644
--- a/board/ezkinil/gpio.inc
+++ b/board/ezkinil/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/ezkinil/led.c b/board/ezkinil/led.c
index 7c425fa138..328b47a9e4 100644
--- a/board/ezkinil/led.c
+++ b/board/ezkinil/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,26 +8,34 @@
 #include "led_common.h"
 #include "led_onoff_states.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
 __override const int led_charge_lvl_1;
 __override const int led_charge_lvl_2 = 100;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]       = {{EC_LED_COLOR_BLUE,  2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{LED_OFF,	     1 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_BLUE,
+					     2 * LED_ONE_SEC },
+					   { EC_LED_COLOR_AMBER,
+					     2 * LED_ONE_SEC } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { LED_OFF, 1 * LED_ONE_SEC },
+					  { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+	};
 BUILD_ASSERT(ARRAY_SIZE(led_bat_state_table) == LED_NUM_STATES);
 
 const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
diff --git a/board/felwinter/battery.c b/board/felwinter/battery.c
index 08c129d118..257d7e8255 100644
--- a/board/felwinter/battery.c
+++ b/board/felwinter/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/felwinter/board.c b/board/felwinter/board.c
index 7f39e58336..556ea2475e 100644
--- a/board/felwinter/board.c
+++ b/board/felwinter/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -29,8 +29,8 @@
 #include "gpio_list.h" /* Must come after other header files. */
 
 /* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 /******************************************************************************/
 /* USB-A charging control */
@@ -94,8 +94,8 @@ int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
 	}
 
 	if (voltage < BC12_MIN_VOLTAGE) {
-		CPRINTS("%s: port %d: vbus %d lower than %d", __func__,
-			port, voltage, BC12_MIN_VOLTAGE);
+		CPRINTS("%s: port %d: vbus %d lower than %d", __func__, port,
+			voltage, BC12_MIN_VOLTAGE);
 		return 1;
 	}
 
@@ -126,7 +126,6 @@ static void board_init(void)
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
-
 /**
  * Deferred function to handle pen detect change
  */
@@ -149,8 +148,7 @@ DECLARE_HOOK(HOOK_INIT, pendetect_deferred, HOOK_PRIO_DEFAULT);
 void pen_detect_interrupt(enum gpio_signal s)
 {
 	/* Trigger deferred notification of pen detect change */
-	hook_call_deferred(&pendetect_deferred_data,
-			500 * MSEC);
+	hook_call_deferred(&pendetect_deferred_data, 500 * MSEC);
 }
 
 void pen_config(void)
diff --git a/board/felwinter/board.h b/board/felwinter/board.h
index 26feb8de3c..17e1cf9246 100644
--- a/board/felwinter/board.h
+++ b/board/felwinter/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,12 +24,12 @@
 /* LED */
 #define CONFIG_LED_ONOFF_STATES
 #define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
-#define GPIO_PWR_LED_WHITE_L	GPIO_LED_1_L
-#define GPIO_BAT_LED_AMBER_L	GPIO_LED_3_L
-#define GPIO_BAT_LED_WHITE_L	GPIO_LED_4_L
+#define GPIO_PWR_LED_WHITE_L GPIO_LED_1_L
+#define GPIO_BAT_LED_AMBER_L GPIO_LED_3_L
+#define GPIO_BAT_LED_WHITE_L GPIO_LED_4_L
 
 /* Sensors */
-#define CONFIG_ACCELGYRO_LSM6DSO	/* Base accel */
+#define CONFIG_ACCELGYRO_LSM6DSO /* Base accel */
 #define CONFIG_ACCEL_LSM6DSO_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 
@@ -43,19 +43,18 @@
 /* Lid accel */
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE	BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID	LID_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
 #define CONFIG_ACCEL_LIS2DWL
 #define CONFIG_ACCEL_LIS2DW12_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
 
-
 /* Sensor console commands */
 #define CONFIG_CMD_ACCELS
 #define CONFIG_CMD_ACCEL_INFO
 
 /* USB Type A Features */
-#define USB_PORT_COUNT			1
+#define USB_PORT_COUNT 1
 #define CONFIG_USB_PORT_POWER_DUMB
 
 /* USB Type C and USB PD defines */
@@ -63,7 +62,7 @@
 
 #define CONFIG_IO_EXPANDER
 #define CONFIG_IO_EXPANDER_NCT38XX
-#define CONFIG_IO_EXPANDER_PORT_COUNT		2
+#define CONFIG_IO_EXPANDER_PORT_COUNT 2
 
 #define CONFIG_USB_PD_TCPM_PS8815
 #define CONFIG_USBC_RETIMER_INTEL_BB
@@ -78,17 +77,17 @@
 #define CONFIG_USBC_PPC_NX20P3483
 
 /* TODO: b/177608416 - measure and check these values on brya */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
 
 /*
  * Passive USB-C cables only support up to 60W.
  */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		65000
-#define PD_MAX_CURRENT_MA	3250
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 65000
+#define PD_MAX_CURRENT_MA 3250
+#define PD_MAX_VOLTAGE_MV 20000
 
 /*
  * Macros for GPIO signals used in common code that don't match the
@@ -96,67 +95,67 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT		GPIO_EC_EN_EDP_BL
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_GSC_PACKET_MODE
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SYS_SLP_S0IX_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_TEMP_SENSOR_POWER	GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
 
 /*
  * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
  * signal.
  */
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_SEQ_EC_ALL_SYS_PG
-#define GPIO_PG_EC_DSW_PWROK		GPIO_SEQ_EC_DSW_PWROK
-#define GPIO_PG_EC_RSMRST_ODL		GPIO_SEQ_EC_RSMRST_ODL
-#define GPIO_POWER_BUTTON_L		GPIO_GSC_EC_PWR_BTN_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_ODL
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
 
 /* System has back-lit keyboard */
 #define CONFIG_PWM_KBLIGHT
 
 /* I2C Bus Configuration */
 
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
 
-#define I2C_PORT_USB_C2_TCPC	NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1_TCPC	NPCX_I2C_PORT4_1
+#define I2C_PORT_USB_C2_TCPC NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1
 
-#define I2C_PORT_USB_C2_PPC	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_PPC	NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C2_PPC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1
 
-#define I2C_PORT_USB_C2_BC12	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_BC12	NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C2_BC12 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1
 
-#define I2C_PORT_USB_C2_MUX	NPCX_I2C_PORT3_0
-#define I2C_PORT_USB_C1_MUX	NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C2_MUX NPCX_I2C_PORT3_0
+#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1
 
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT5_0
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT7_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-#define I2C_PORT_MP2964		NPCX_I2C_PORT7_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0
 
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 
-#define I2C_ADDR_MP2964_FLAGS	0x20
+#define I2C_ADDR_MP2964_FLAGS 0x20
 
 /*
  *
  */
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x56
-#define USBC_PORT_C2_BB_RETIMER_I2C_ADDR	0x58
+#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x56
+#define USBC_PORT_C2_BB_RETIMER_I2C_ADDR 0x58
 
 /* Enabling Thunderbolt-compatible mode */
 #define CONFIG_USB_PD_TBT_COMPAT_MODE
@@ -173,19 +172,19 @@
 #define CONFIG_TEMP_SENSOR_POWER
 #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
 
-#define CONFIG_FANS			FAN_CH_COUNT
+#define CONFIG_FANS FAN_CH_COUNT
 
 /* Charger defines */
 #define CONFIG_CHARGER_ISL9241
 #define CONFIG_CHARGE_RAMP_SW
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 
 #define CONFIG_KEYBOARD_REFRESH_ROW3
 
 #ifndef __ASSEMBLER__
 
-#include "gpio_signal.h"	/* needed by registers.h */
+#include "gpio_signal.h" /* needed by registers.h */
 #include "registers.h"
 #include "usbc_config.h"
 
@@ -203,39 +202,21 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL = 0, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
-enum ioex_port {
-	IOEX_C2_NCT38XX = 0,
-	IOEX_C1_NCT38XX,
-	IOEX_PORT_COUNT
-};
+enum ioex_port { IOEX_C2_NCT38XX = 0, IOEX_C1_NCT38XX, IOEX_PORT_COUNT };
 
-enum battery_type {
-	BATTERY_C536,
-	BATTERY_TYPE_COUNT
-};
+enum battery_type { BATTERY_C536, BATTERY_TYPE_COUNT };
 
 enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,	/* PWM3 */
-	PWM_CH_FAN,			/* PWM5 */
+	PWM_CH_KBLIGHT = 0, /* PWM3 */
+	PWM_CH_FAN, /* PWM5 */
 	PWM_CH_COUNT
 };
 
-enum fan_channel {
-	FAN_CH_0 = 0,
-	FAN_CH_COUNT
-};
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT };
 
-enum mft_channel {
-	MFT_CH_0 = 0,
-	MFT_CH_COUNT
-};
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT };
 
 void pen_detect_interrupt(enum gpio_signal s);
 
diff --git a/board/felwinter/build.mk b/board/felwinter/build.mk
index 5a0a20b5e6..848c76f457 100644
--- a/board/felwinter/build.mk
+++ b/board/felwinter/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/felwinter/charger_isl9241.c b/board/felwinter/charger_isl9241.c
index 8bb38754dd..dd2535ea7c 100644
--- a/board/felwinter/charger_isl9241.c
+++ b/board/felwinter/charger_isl9241.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,9 +15,8 @@
 #include "usb_pd.h"
 #include "util.h"
 
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* Charger Chip Configuration */
 const struct charger_config_t chg_chips[] = {
@@ -85,7 +84,6 @@ __overridable void board_set_charge_limit(int port, int supplier, int charge_ma,
 					  int max_ma, int charge_mv)
 {
 	charge_ma = (charge_ma * 90) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
diff --git a/board/felwinter/ec.tasklist b/board/felwinter/ec.tasklist
index 6d995d6b44..29fd0bf4cb 100644
--- a/board/felwinter/ec.tasklist
+++ b/board/felwinter/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/felwinter/fans.c b/board/felwinter/fans.c
index 636364a6de..5f68df09ff 100644
--- a/board/felwinter/fans.c
+++ b/board/felwinter/fans.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,7 +25,7 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 static const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
diff --git a/board/felwinter/fw_config.c b/board/felwinter/fw_config.c
index 4228394d5b..0a4905bc9d 100644
--- a/board/felwinter/fw_config.c
+++ b/board/felwinter/fw_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,7 +9,7 @@
 #include "cros_board_info.h"
 #include "fw_config.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 static union brya_cbi_fw_config fw_config;
 BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
diff --git a/board/felwinter/fw_config.h b/board/felwinter/fw_config.h
index 5f5f956b61..2a8a175efd 100644
--- a/board/felwinter/fw_config.h
+++ b/board/felwinter/fw_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,37 +14,28 @@
  * Source of truth is the project/brya/felwinter/config.star configuration file.
  */
 
-enum ec_cfg_usb_db_type {
-	DB_USB3_PS8815 = 1,
-	DB_USB4_NCT3807 = 2
-};
+enum ec_cfg_usb_db_type { DB_USB3_PS8815 = 1, DB_USB4_NCT3807 = 2 };
 
 enum ec_cfg_keyboard_backlight_type {
 	KEYBOARD_BACKLIGHT_DISABLED = 0,
 	KEYBOARD_BACKLIGHT_ENABLED = 1
 };
 
-enum ec_cfg_usb_mb_type {
-	MB_USB4_TBT = 0,
-	MB_USB3_NON_TBT = 1
-};
+enum ec_cfg_usb_mb_type { MB_USB4_TBT = 0, MB_USB3_NON_TBT = 1 };
 
-enum ec_cfg_stylus_type {
-	STYLUS_ABSENT = 0,
-	STYLUS_PRSENT = 1
-};
+enum ec_cfg_stylus_type { STYLUS_ABSENT = 0, STYLUS_PRSENT = 1 };
 
 union brya_cbi_fw_config {
 	struct {
-		enum ec_cfg_usb_db_type			usb_db : 3;
-		uint32_t				wifi : 2;
-		enum ec_cfg_stylus_type			stylus : 1;
-		enum ec_cfg_keyboard_backlight_type	kb_bl : 1;
-		uint32_t				audio : 3;
-		uint32_t				thermal : 2;
-		uint32_t				table_mode : 1;
-		enum ec_cfg_usb_mb_type			usb_mb : 3;
-		uint32_t				reserved_1 : 16;
+		enum ec_cfg_usb_db_type usb_db : 3;
+		uint32_t wifi : 2;
+		enum ec_cfg_stylus_type stylus : 1;
+		enum ec_cfg_keyboard_backlight_type kb_bl : 1;
+		uint32_t audio : 3;
+		uint32_t thermal : 2;
+		uint32_t table_mode : 1;
+		enum ec_cfg_usb_mb_type usb_mb : 3;
+		uint32_t reserved_1 : 16;
 	};
 	uint32_t raw_value;
 };
diff --git a/board/felwinter/gpio.inc b/board/felwinter/gpio.inc
index 112047c35f..df992a18eb 100644
--- a/board/felwinter/gpio.inc
+++ b/board/felwinter/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/felwinter/i2c.c b/board/felwinter/i2c.c
index a850c12544..b765ccff98 100644
--- a/board/felwinter/i2c.c
+++ b/board/felwinter/i2c.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/felwinter/keyboard.c b/board/felwinter/keyboard.c
index a8cbf72238..cee23af8c3 100644
--- a/board/felwinter/keyboard.c
+++ b/board/felwinter/keyboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -41,8 +41,8 @@ static const struct ec_response_keybd_config felwinter_kb = {
 	.capabilities = KEYBD_CAP_SCRNLOCK_KEY | KEYBD_CAP_NUMERIC_KEYPAD,
 };
 
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	return &felwinter_kb;
 }
diff --git a/board/felwinter/led.c b/board/felwinter/led.c
index 3b7e649470..2770e7fae8 100644
--- a/board/felwinter/led.c
+++ b/board/felwinter/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,35 +11,43 @@
 #include "led_onoff_states.h"
 #include "system.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
 __override const int led_charge_lvl_1;
-__override const int led_charge_lvl_2 = 94;
+__override const int led_charge_lvl_2 = 95;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF, 3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF, 1 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+	};
 
 __override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    1 * LED_ONE_SEC },
+						  { LED_OFF,
+						    3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
 const enum ec_led_id supported_led_ids[] = {
 	EC_LED_ID_BATTERY_LED,
diff --git a/board/felwinter/pwm.c b/board/felwinter/pwm.c
index fea431c4ce..97b5c17a03 100644
--- a/board/felwinter/pwm.c
+++ b/board/felwinter/pwm.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/felwinter/sensors.c b/board/felwinter/sensors.c
index fd3f721947..6b62f5f4d2 100644
--- a/board/felwinter/sensors.c
+++ b/board/felwinter/sensors.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -46,18 +46,14 @@ K_MUTEX_DEFINE(g_base_accel_mutex);
 static struct stprivate_data g_lis2dw12_data;
 static struct lsm6dso_data lsm6dso_data;
 
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(1), 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
 
 /* TODO(b/184779743): verify orientation matrix */
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, FLOAT_TO_FP(-1), 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
@@ -146,24 +142,18 @@ DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_INIT_I2C + 1);
 
 /* Temperature sensor configuration */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1_DDR_SOC] = {
-		.name = "DDR and SOC",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_1_DDR_SOC
-	},
-	[TEMP_SENSOR_2_FAN] = {
-		.name = "FAN",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_2_FAN
-	},
-	[TEMP_SENSOR_3_CHARGER] = {
-		.name = "Charger",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_3_CHARGER
-	},
+	[TEMP_SENSOR_1_DDR_SOC] = { .name = "DDR and SOC",
+				    .type = TEMP_SENSOR_TYPE_BOARD,
+				    .read = get_temp_3v3_30k9_47k_4050b,
+				    .idx = ADC_TEMP_SENSOR_1_DDR_SOC },
+	[TEMP_SENSOR_2_FAN] = { .name = "FAN",
+				.type = TEMP_SENSOR_TYPE_BOARD,
+				.read = get_temp_3v3_30k9_47k_4050b,
+				.idx = ADC_TEMP_SENSOR_2_FAN },
+	[TEMP_SENSOR_3_CHARGER] = { .name = "Charger",
+				    .type = TEMP_SENSOR_TYPE_BOARD,
+				    .read = get_temp_3v3_30k9_47k_4050b,
+				    .idx = ADC_TEMP_SENSOR_3_CHARGER },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -177,8 +167,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CPU \
-	{ \
+#define THERMAL_CPU              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
@@ -207,8 +197,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_FAN \
-	{ \
+#define THERMAL_FAN              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(60), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(70), \
@@ -221,8 +211,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 	}
 __maybe_unused static const struct ec_thermal_config thermal_fan = THERMAL_FAN;
 
-#define THERMAL_CHARGER \
-	{ \
+#define THERMAL_CHARGER          \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
diff --git a/board/felwinter/usbc_config.c b/board/felwinter/usbc_config.c
index 3d39650ba8..ebe77bf7c7 100644
--- a/board/felwinter/usbc_config.c
+++ b/board/felwinter/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -33,8 +33,8 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 /* USBC TCPC configuration */
 struct tcpc_config_t tcpc_config[] = {
@@ -99,16 +99,22 @@ struct ppc_config_t ppc_chips_c1 = {
 };
 
 /* USBC mux configuration - Alder Lake includes internal mux */
-static const struct usb_mux usbc2_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C2,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+static const struct usb_mux_chain usbc2_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C2,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
 
-static const struct usb_mux usbc1_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+static const struct usb_mux_chain usbc1_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
 
 /*
@@ -116,47 +122,59 @@ static const struct usb_mux usbc1_tcss_usb_mux = {
  * to the virtual_usb_mux_driver so the AP gets notified of mux changes
  * and updates the TCSS configuration on state changes.
  */
-static const struct usb_mux usbc1_usb3_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+static const struct usb_mux_chain usbc1_usb3_db_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 };
 
-struct usb_mux usb_muxes[] = {
+struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C2] = {
-		.usb_port = USBC_PORT_C2,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C2,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 	},
 	[USBC_PORT_C1] = {
-		/* PS8815 DB */
-		.usb_port = USBC_PORT_C1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc1_usb3_db_retimer,
+		.mux = &(const struct usb_mux) {
+			/* PS8815 DB */
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc1_usb3_db_retimer,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
 
-static const struct usb_mux usb_muxes_c1 = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C1_MUX,
-		.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc1_tcss_usb_mux,
+static const struct usb_mux_chain usb_muxes_c1 = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C1_MUX,
+			.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
+		},
+	.next = &usbc1_tcss_usb_mux,
 };
 
-static const struct usb_mux usb_muxes_c2 = {
-		.usb_port = USBC_PORT_C2,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C2_MUX,
-		.i2c_addr_flags = USBC_PORT_C2_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc2_tcss_usb_mux,
+static const struct usb_mux_chain usb_muxes_c2 = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C2,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C2_MUX,
+			.i2c_addr_flags = USBC_PORT_C2_BB_RETIMER_I2C_ADDR,
+		},
+	.next = &usbc2_tcss_usb_mux,
 };
 
-
 /* BC1.2 charger detect configuration */
 const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
 	[USBC_PORT_C2] = {
@@ -254,7 +272,6 @@ void board_reset_pd_mcu(void)
 	if (ec_cfg_usb_db_type() == DB_USB4_NCT3807)
 		gpio_set_level(GPIO_USB_C1_RST_ODL, 0);
 
-
 	/*
 	 * delay for power-on to reset-off and min. assertion time
 	 */
@@ -392,10 +409,9 @@ __override bool board_is_dts_port(int port)
 
 __override bool board_is_tbt_usb4_port(int port)
 {
-	if (((port == USBC_PORT_C2) &&
-		(ec_cfg_usb_mb_type() == MB_USB4_TBT)) ||
-		((port == USBC_PORT_C1) &&
-		(ec_cfg_usb_db_type() == DB_USB4_NCT3807)))
+	if (((port == USBC_PORT_C2) && (ec_cfg_usb_mb_type() == MB_USB4_TBT)) ||
+	    ((port == USBC_PORT_C1) &&
+	     (ec_cfg_usb_db_type() == DB_USB4_NCT3807)))
 		return true;
 
 	return false;
diff --git a/board/felwinter/usbc_config.h b/board/felwinter/usbc_config.h
index 9f0a26210f..cab32351f5 100644
--- a/board/felwinter/usbc_config.h
+++ b/board/felwinter/usbc_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,15 +8,11 @@
 #ifndef __CROS_EC_USBC_CONFIG_H
 #define __CROS_EC_USBC_CONFIG_H
 
-#define CONFIG_USB_PD_PORT_MAX_COUNT	2
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
 #define CONFIG_USB_PD_TCPC_RUNTIME_CONFIG
 #define CONFIG_USB_MUX_RUNTIME_CONFIG
 
-enum usbc_port {
-	USBC_PORT_C2 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C2 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 void config_usb_db_type(void);
 void db_update_usb4_config_from_config(void);
diff --git a/board/fennel/battery.c b/board/fennel/battery.c
index cfd17a136f..882ff0c5a2 100644
--- a/board/fennel/battery.c
+++ b/board/fennel/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/fennel/board.c b/board/fennel/board.c
index b9adcad237..563f680dee 100644
--- a/board/fennel/board.c
+++ b/board/fennel/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -33,6 +33,7 @@
 #include "keyboard_scan.h"
 #include "keyboard_backlight.h"
 #include "lid_switch.h"
+#include "panic.h"
 #include "power.h"
 #include "power_button.h"
 #include "registers.h"
@@ -47,8 +48,8 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
@@ -60,40 +61,34 @@ static void tcpc_alert_event(enum gpio_signal signal)
 /******************************************************************************/
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] =  {"BOARD_ID",  3300, 4096, 0, STM32_AIN(10)},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)},
+	[ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(10) },
+	[ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /******************************************************************************/
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "typec",
-		.port = 0,
-		.kbps = 400,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	},
-	{
-		.name = "other",
-		.port = 1,
-		.kbps = 400,
-		.scl  = GPIO_I2C2_SCL,
-		.sda  = GPIO_I2C2_SDA
-	},
+	{ .name = "typec",
+	  .port = 0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "other",
+	  .port = 1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
 const struct i2c_port_t i2c_bitbang_ports[] = {
-	{
-		.name = "battery",
-		.port = 2,
-		.kbps = 100,
-		.scl  = GPIO_I2C3_SCL,
-		.sda  = GPIO_I2C3_SDA,
-		.drv = &bitbang_drv
-	},
+	{ .name = "battery",
+	  .port = 2,
+	  .kbps = 100,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA,
+	  .drv = &bitbang_drv },
 };
 const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
 
@@ -101,8 +96,8 @@ const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
 
 /* power signal list.  Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
+	{ GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" },
+	{ GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" },
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
@@ -158,8 +153,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-static void board_hpd_status(const struct usb_mux *me,
-			     mux_state_t mux_state,
+static void board_hpd_status(const struct usb_mux *me, mux_state_t mux_state,
 			     bool *ack_required)
 {
 	/* This driver does not use host command ACKs */
@@ -172,13 +166,16 @@ static void board_hpd_status(const struct usb_mux *me,
 	host_set_single_event(EC_HOST_EVENT_USB_MUX);
 }
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+				.hpd_update = &board_hpd_status,
+			},
 	},
 };
 
@@ -240,12 +237,12 @@ int board_set_active_charge_port(int charge_port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-			       CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 int board_discharge_on_ac(int enable)
@@ -302,8 +299,7 @@ static void board_spi_enable(void)
 	/* Pin mux spi peripheral toward the sensor. */
 	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
 }
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP,
-	     board_spi_enable,
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_spi_enable,
 	     MOTION_SENSE_HOOK_PRIO - 1);
 
 static void board_spi_disable(void)
@@ -320,8 +316,7 @@ static void board_spi_disable(void)
 	spi_enable(&spi_devices[0], 0);
 	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
 }
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN,
-	     board_spi_disable,
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_spi_disable,
 	     MOTION_SENSE_HOOK_PRIO + 1);
 #endif /* !VARIANT_KUKUI_NO_SENSORS */
 
@@ -360,17 +355,13 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Rotation matrixes */
-static const mat33_fp_t base_standard_ref = {
-	{0, FLOAT_TO_FP(1), 0},
-	{FLOAT_TO_FP(-1), 0, 0},
-	{0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					      { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
 
-static const mat33_fp_t lid_standard_ref = {
-	{FLOAT_TO_FP(-1), 0, 0},
-	{0, FLOAT_TO_FP(1), 0},
-	{0, 0, FLOAT_TO_FP(-1) }
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, FLOAT_TO_FP(1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
 /* sensor private data */
 /* Lid accel private data */
@@ -417,20 +408,20 @@ struct motion_sensor_t icm42607_base_accel = {
 };
 
 struct motion_sensor_t icm42607_base_gyro = {
-	 .name = "Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_ICM42607,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &icm42607_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_icm42607_data,
-	 .port = CONFIG_SPI_ACCEL_PORT,
-	 .i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = NULL,
-	 .min_frequency = ICM42607_GYRO_MIN_FREQ,
-	 .max_frequency = ICM42607_GYRO_MAX_FREQ,
+	.name = "Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM42607,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm42607_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm42607_data,
+	.port = CONFIG_SPI_ACCEL_PORT,
+	.i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT),
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = NULL,
+	.min_frequency = ICM42607_GYRO_MIN_FREQ,
+	.max_frequency = ICM42607_GYRO_MAX_FREQ,
 };
 
 struct motion_sensor_t motion_sensors[] = {
@@ -522,18 +513,18 @@ static void board_detect_motionsensor(void)
 	if (base_accelgyro_config != BASE_GYRO_NONE)
 		return;
 	/* Check base accelgyro chip */
-	ret = icm_read8(&icm42607_base_accel,
-				ICM42607_REG_WHO_AM_I, &val);
+	ret = icm_read8(&icm42607_base_accel, ICM42607_REG_WHO_AM_I, &val);
 	if (ret)
 		ccprints("Get ICM fail.");
 	if (val == ICM42607_CHIP_ICM42607P) {
 		motion_sensors[BASE_ACCEL] = icm42607_base_accel;
 		motion_sensors[BASE_GYRO] = icm42607_base_gyro;
 	}
-	base_accelgyro_config = (val == ICM42607_CHIP_ICM42607P)
-			? BASE_GYRO_ICM426XX : BASE_GYRO_BMI160;
-	ccprints("BASE Accelgyro: %s", (val == ICM42607_CHIP_ICM42607P)
-			? "ICM42607" : "BMI160");
+	base_accelgyro_config = (val == ICM42607_CHIP_ICM42607P) ?
+					BASE_GYRO_ICM426XX :
+					BASE_GYRO_BMI160;
+	ccprints("BASE Accelgyro: %s",
+		 (val == ICM42607_CHIP_ICM42607P) ? "ICM42607" : "BMI160");
 }
 DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_detect_motionsensor,
 	     HOOK_PRIO_DEFAULT);
@@ -559,7 +550,7 @@ void motion_interrupt(enum gpio_signal signal)
 }
 
 const struct it8801_pwm_t it8801_pwm_channels[] = {
-	[IT8801_PWM_CH_KBLIGHT] = {.index = 4},
+	[IT8801_PWM_CH_KBLIGHT] = { .index = 4 },
 };
 
 void board_kblight_init(void)
@@ -575,11 +566,11 @@ bool board_has_kb_backlight(void)
 #endif /* !VARIANT_KUKUI_NO_SENSORS */
 
 /* Battery functions */
-#define SB_SMARTCHARGE				0x26
+#define SB_SMARTCHARGE 0x26
 /* Quick charge enable bit */
-#define SMART_QUICK_CHARGE			0x02
+#define SMART_QUICK_CHARGE 0x02
 /* Quick charge support bit */
-#define MODE_QUICK_CHARGE_SUPPORT		0x01
+#define MODE_QUICK_CHARGE_SUPPORT 0x01
 
 static void sb_quick_charge_mode(int enable)
 {
@@ -650,8 +641,8 @@ int board_get_battery_i2c(void)
 }
 
 #ifdef SECTION_IS_RW
-static int it8801_get_target_channel(enum pwm_channel *channel,
-				     int type, int index)
+static int it8801_get_target_channel(enum pwm_channel *channel, int type,
+				     int index)
 {
 	switch (type) {
 	case EC_PWM_TYPE_GENERIC:
@@ -674,14 +665,13 @@ host_command_pwm_set_duty(struct host_cmd_handler_args *args)
 	if (it8801_get_target_channel(&channel, p->pwm_type, p->index))
 		return EC_RES_INVALID_PARAM;
 
-	duty = (uint32_t) p->duty * 255 / 65535;
+	duty = (uint32_t)p->duty * 255 / 65535;
 	it8801_pwm_set_raw_duty(channel, duty);
 	it8801_pwm_enable(channel, p->duty > 0);
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_DUTY,
-		     host_command_pwm_set_duty,
+DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_DUTY, host_command_pwm_set_duty,
 		     EC_VER_MASK(0));
 
 static enum ec_status
@@ -695,12 +685,11 @@ host_command_pwm_get_duty(struct host_cmd_handler_args *args)
 	if (it8801_get_target_channel(&channel, p->pwm_type, p->index))
 		return EC_RES_INVALID_PARAM;
 
-	r->duty = (uint32_t) it8801_pwm_get_raw_duty(channel) * 65535 / 255;
+	r->duty = (uint32_t)it8801_pwm_get_raw_duty(channel) * 65535 / 255;
 	args->response_size = sizeof(*r);
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_DUTY,
-		     host_command_pwm_get_duty,
+DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_DUTY, host_command_pwm_get_duty,
 		     EC_VER_MASK(0));
 #endif
diff --git a/board/fennel/board.h b/board/fennel/board.h
index f15e61da11..6bb90ef0f3 100644
--- a/board/fennel/board.h
+++ b/board/fennel/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -52,11 +52,11 @@
 
 /* Motion Sensors */
 #ifndef VARIANT_KUKUI_NO_SENSORS
-#define CONFIG_ACCEL_LIS2DWL    /* Lid accel */
+#define CONFIG_ACCEL_LIS2DWL /* Lid accel */
 #define CONFIG_ACCELGYRO_BMI160 /* Base accel */
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCELGYRO_ICM42607	/* Base accel second source*/
+#define CONFIG_ACCELGYRO_ICM42607 /* Base accel second source*/
 #define CONFIG_ACCELGYRO_ICM42607_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
 #define CONFIG_ALS
@@ -75,20 +75,20 @@
 #endif /* VARIANT_KUKUI_NO_SENSORS */
 
 /* I2C ports */
-#define I2C_PORT_BC12               0
-#define I2C_PORT_TCPC0              0
-#define I2C_PORT_USB_MUX            0
-#define I2C_PORT_CHARGER            board_get_charger_i2c()
-#define I2C_PORT_SENSORS            1
-#define I2C_PORT_KB_DISCRETE        1
-#define I2C_PORT_VIRTUAL_BATTERY    I2C_PORT_BATTERY
-#define I2C_PORT_BATTERY            2
+#define I2C_PORT_BC12 0
+#define I2C_PORT_TCPC0 0
+#define I2C_PORT_USB_MUX 0
+#define I2C_PORT_CHARGER board_get_charger_i2c()
+#define I2C_PORT_SENSORS 1
+#define I2C_PORT_KB_DISCRETE 1
+#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
+#define I2C_PORT_BATTERY 2
 
 /* IT8801 I2C address */
-#define KB_DISCRETE_I2C_ADDR_FLAGS  IT8801_I2C_ADDR1
+#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1
 
 /* Enable Accel over SPI */
-#define CONFIG_SPI_ACCEL_PORT    0  /* The first SPI controller port (SPI2) */
+#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */
 
 #define CONFIG_KEYBOARD_PROTOCOL_MKBP
 #define CONFIG_MKBP_EVENT
diff --git a/board/fennel/build.mk b/board/fennel/build.mk
index a6e1c010d7..f583684804 100644
--- a/board/fennel/build.mk
+++ b/board/fennel/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/fennel/ec.tasklist b/board/fennel/ec.tasklist
index c1330b86f8..fb131b8eb4 100644
--- a/board/fennel/ec.tasklist
+++ b/board/fennel/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/fennel/gpio.inc b/board/fennel/gpio.inc
index 29518fbc4e..5ebecfac53 100644
--- a/board/fennel/gpio.inc
+++ b/board/fennel/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/fennel/led.c b/board/fennel/led.c
index 7d95c4807e..e6badd92bc 100644
--- a/board/fennel/led.c
+++ b/board/fennel/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -18,33 +18,38 @@ __override const int led_charge_lvl_1 = 5;
 __override const int led_charge_lvl_2 = 97;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED,    LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER,  LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
 
 __override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    1 * LED_ONE_SEC },
+						  { LED_OFF,
+						    3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 __override void led_set_color_battery(enum ec_led_colors color)
diff --git a/board/fizz/board.c b/board/fizz/board.c
index a397ca27e4..f58083c6ed 100644
--- a/board/fizz/board.c
+++ b/board/fizz/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -50,8 +50,8 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static uint16_t board_version;
 static uint8_t oem;
@@ -62,7 +62,7 @@ static void tcpc_alert_event(enum gpio_signal signal)
 	schedule_deferred_pd_interrupt(0 /* port */);
 }
 
-#define ADP_DEBOUNCE_MS		1000  /* Debounce time for BJ plug/unplug */
+#define ADP_DEBOUNCE_MS 1000 /* Debounce time for BJ plug/unplug */
 /*
  * ADP_IN pin state. It's initialized to 1 (=unplugged) because the IRQ won't
  * be triggered if BJ is the power source.
@@ -125,7 +125,8 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* Vbus sensing (1/10 voltage divider). */
-	[ADC_VBUS] = {"VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
+	[ADC_VBUS] = { "VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT * 10,
+		       ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
@@ -133,7 +134,7 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 /* Physical fans. These are logically separate from pwm_channels. */
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_FAN_PWR_EN,
 };
@@ -158,47 +159,37 @@ BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
 /******************************************************************************/
 /* MFT channels. These are logically separate from pwm_channels. */
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN },
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 /* I2C port map */
-const struct i2c_port_t i2c_ports[]  = {
-	{
-		.name = "tcpc",
-		.port = NPCX_I2C_PORT0_0,
-		.kbps = 400,
-		.scl  = GPIO_I2C0_0_SCL,
-		.sda  = GPIO_I2C0_0_SDA
-	},
-	{
-		.name = "eeprom",
-		.port = NPCX_I2C_PORT0_1,
-		.kbps = 400,
-		.scl  = GPIO_I2C0_1_SCL,
-		.sda  = GPIO_I2C0_1_SDA
-	},
-	{
-		.name = "charger",
-		.port = NPCX_I2C_PORT1,
-		.kbps = 100,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	},
-	{
-		.name = "pmic",
-		.port = NPCX_I2C_PORT2,
-		.kbps = 400,
-		.scl  = GPIO_I2C2_SCL,
-		.sda  = GPIO_I2C2_SDA
-	},
-	{
-		.name = "thermal",
-		.port = NPCX_I2C_PORT3,
-		.kbps = 400,
-		.scl  = GPIO_I2C3_SCL,
-		.sda  = GPIO_I2C3_SDA
-	},
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "tcpc",
+	  .port = NPCX_I2C_PORT0_0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_0_SCL,
+	  .sda = GPIO_I2C0_0_SDA },
+	{ .name = "eeprom",
+	  .port = NPCX_I2C_PORT0_1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_1_SCL,
+	  .sda = GPIO_I2C0_1_SDA },
+	{ .name = "charger",
+	  .port = NPCX_I2C_PORT1,
+	  .kbps = 100,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "pmic",
+	  .port = NPCX_I2C_PORT2,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "thermal",
+	  .port = NPCX_I2C_PORT3,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -221,21 +212,19 @@ static int ps8751_tune_mux(const struct usb_mux *me)
 	return EC_SUCCESS;
 }
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-		.board_init = &ps8751_tune_mux,
-	}
-};
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = 0,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			.board_init = &ps8751_tune_mux,
+		},
+} };
 
 const int usb_port_enable[USB_PORT_COUNT] = {
-	GPIO_USB1_ENABLE,
-	GPIO_USB2_ENABLE,
-	GPIO_USB3_ENABLE,
-	GPIO_USB4_ENABLE,
-	GPIO_USB5_ENABLE,
+	GPIO_USB1_ENABLE, GPIO_USB2_ENABLE, GPIO_USB3_ENABLE,
+	GPIO_USB4_ENABLE, GPIO_USB5_ENABLE,
 };
 
 void board_reset_pd_mcu(void)
@@ -270,9 +259,9 @@ void board_tcpc_init(void)
 	 */
 	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
 		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
 
 uint16_t tcpc_get_alert_status(void)
 {
@@ -294,10 +283,10 @@ uint16_t tcpc_get_alert_status(void)
  *     src/mainboard/google/${board}/acpi/dptf.asl
  */
 const struct temp_sensor_t temp_sensors[] = {
-	{"TMP431_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-			TMP432_IDX_LOCAL},
-	{"TMP431_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-			TMP432_IDX_REMOTE1},
+	{ "TMP431_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
+	  TMP432_IDX_LOCAL },
+	{ "TMP431_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
+	  TMP432_IDX_REMOTE1 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -310,9 +299,11 @@ struct ec_thermal_config thermal_params[] = {
 	 * {Twarn, Thigh, X    }, <off>
 	 * fan_off, fan_max
 	 */
-	{{0, C_TO_K(80), C_TO_K(81)}, {0, C_TO_K(78), 0},
-		C_TO_K(4), C_TO_K(76)},	/* TMP431_Internal */
-	{{0, 0, 0}, {0, 0, 0}, 0, 0},	/* TMP431_Sensor_1 */
+	{ { 0, C_TO_K(80), C_TO_K(81) },
+	  { 0, C_TO_K(78), 0 },
+	  C_TO_K(4),
+	  C_TO_K(76) }, /* TMP431_Internal */
+	{ { 0, 0, 0 }, { 0, 0, 0 }, 0, 0 }, /* TMP431_Sensor_1 */
 };
 BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
 
@@ -521,8 +512,8 @@ static void set_charge_limit(int charge_ma)
 	}
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	int p87w = 0, p65w = 0, p60w = 0;
 
@@ -533,7 +524,7 @@ void board_set_charge_limit(int port, int supplier, int charge_ma,
 	 * is called.
 	 */
 	led_alert(charge_ma * charge_mv <
-			CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON * 1000);
+		  CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON * 1000);
 
 	/*
 	 * In terms of timing, this should always work because
@@ -580,11 +571,11 @@ void board_set_charge_limit(int port, int supplier, int charge_ma,
 		} else {
 			/*
 			 * TODO:http://crosbug.com/p/65013352.
-	 		 * The current monitoring system doesn't support lower
-	 		 * current. These currents are most likely not enough to
-	 		 * power the system. However, if they're needed, EC can
-	 		 * monitor PMON_PSYS and trigger H_PROCHOT by itself.
-	 		 */
+			 * The current monitoring system doesn't support lower
+			 * current. These currents are most likely not enough to
+			 * power the system. However, if they're needed, EC can
+			 * monitor PMON_PSYS and trigger H_PROCHOT by itself.
+			 */
 			p60w = 1;
 			CPRINTS("Current %dmA not supported", charge_ma);
 		}
@@ -602,9 +593,9 @@ int64_t get_time_dsw_pwrok(void)
 }
 
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED_RED]   = { 3, PWM_CONFIG_DSLEEP, 100 },
+	[PWM_CH_LED_RED] = { 3, PWM_CONFIG_DSLEEP, 100 },
 	[PWM_CH_LED_GREEN] = { 5, PWM_CONFIG_DSLEEP, 100 },
-	[PWM_CH_FAN] = {4, PWM_CONFIG_OPEN_DRAIN, 25000},
+	[PWM_CH_FAN] = { 4, PWM_CONFIG_OPEN_DRAIN, 25000 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
@@ -618,44 +609,44 @@ static const struct fan_step *fan_table;
 
 /* Note: Do not make the fan on/off point equal to 0 or 100 */
 static const struct fan_step fan_table0[] = {
-	{.on =  0, .off =  1, .rpm = 0},
-	{.on = 36, .off =  1, .rpm = 2800},
-	{.on = 58, .off = 58, .rpm = 3200},
-	{.on = 66, .off = 61, .rpm = 3400},
-	{.on = 75, .off = 69, .rpm = 4200},
-	{.on = 81, .off = 76, .rpm = 4800},
-	{.on = 88, .off = 83, .rpm = 5200},
-	{.on = 98, .off = 91, .rpm = 5600},
+	{ .on = 0, .off = 1, .rpm = 0 },
+	{ .on = 36, .off = 1, .rpm = 2800 },
+	{ .on = 58, .off = 58, .rpm = 3200 },
+	{ .on = 66, .off = 61, .rpm = 3400 },
+	{ .on = 75, .off = 69, .rpm = 4200 },
+	{ .on = 81, .off = 76, .rpm = 4800 },
+	{ .on = 88, .off = 83, .rpm = 5200 },
+	{ .on = 98, .off = 91, .rpm = 5600 },
 };
 static const struct fan_step fan_table1[] = {
-	{.on =  0, .off =  1, .rpm = 0},
-	{.on = 36, .off =  1, .rpm = 2800},
-	{.on = 62, .off = 58, .rpm = 3200},
-	{.on = 68, .off = 63, .rpm = 3400},
-	{.on = 75, .off = 69, .rpm = 4200},
-	{.on = 81, .off = 76, .rpm = 4800},
-	{.on = 88, .off = 83, .rpm = 5200},
-	{.on = 98, .off = 91, .rpm = 5600},
+	{ .on = 0, .off = 1, .rpm = 0 },
+	{ .on = 36, .off = 1, .rpm = 2800 },
+	{ .on = 62, .off = 58, .rpm = 3200 },
+	{ .on = 68, .off = 63, .rpm = 3400 },
+	{ .on = 75, .off = 69, .rpm = 4200 },
+	{ .on = 81, .off = 76, .rpm = 4800 },
+	{ .on = 88, .off = 83, .rpm = 5200 },
+	{ .on = 98, .off = 91, .rpm = 5600 },
 };
 static const struct fan_step fan_table2[] = {
-	{.on =  0, .off =  1, .rpm = 0},
-	{.on = 36, .off =  1, .rpm = 2200},
-	{.on = 63, .off = 56, .rpm = 2900},
-	{.on = 69, .off = 65, .rpm = 3000},
-	{.on = 75, .off = 70, .rpm = 3300},
-	{.on = 80, .off = 76, .rpm = 3600},
-	{.on = 87, .off = 81, .rpm = 3900},
-	{.on = 98, .off = 91, .rpm = 5000},
+	{ .on = 0, .off = 1, .rpm = 0 },
+	{ .on = 36, .off = 1, .rpm = 2200 },
+	{ .on = 63, .off = 56, .rpm = 2900 },
+	{ .on = 69, .off = 65, .rpm = 3000 },
+	{ .on = 75, .off = 70, .rpm = 3300 },
+	{ .on = 80, .off = 76, .rpm = 3600 },
+	{ .on = 87, .off = 81, .rpm = 3900 },
+	{ .on = 98, .off = 91, .rpm = 5000 },
 };
 static const struct fan_step fan_table3[] = {
-	{.on =  0, .off =  1, .rpm = 0},
-	{.on = 36, .off = 22, .rpm = 2500},
-	{.on = 54, .off = 49, .rpm = 3200},
-	{.on = 61, .off = 56, .rpm = 3500},
-	{.on = 68, .off = 63, .rpm = 3900},
-	{.on = 75, .off = 69, .rpm = 4500},
-	{.on = 82, .off = 76, .rpm = 5100},
-	{.on = 92, .off = 85, .rpm = 5400},
+	{ .on = 0, .off = 1, .rpm = 0 },
+	{ .on = 36, .off = 22, .rpm = 2500 },
+	{ .on = 54, .off = 49, .rpm = 3200 },
+	{ .on = 61, .off = 56, .rpm = 3500 },
+	{ .on = 68, .off = 63, .rpm = 3900 },
+	{ .on = 75, .off = 69, .rpm = 4500 },
+	{ .on = 82, .off = 76, .rpm = 5100 },
+	{ .on = 92, .off = 85, .rpm = 5400 },
 };
 /* All fan tables must have the same number of levels */
 #define NUM_FAN_LEVELS ARRAY_SIZE(fan_table0)
@@ -748,8 +739,8 @@ static void setup_bj(void)
 
 	switch (oem) {
 	case OEM_KENCH:
-		bj = (BJ_ADAPTER_90W_MASK & BIT(sku)) ?
-			BJ_90W_19P5V : BJ_65W_19P5V;
+		bj = (BJ_ADAPTER_90W_MASK & BIT(sku)) ? BJ_90W_19P5V :
+							BJ_65W_19P5V;
 		break;
 	case OEM_TEEMO:
 	case OEM_BLEEMO:
@@ -758,15 +749,14 @@ static void setup_bj(void)
 	case OEM_WUKONG_A:
 	case OEM_WUKONG_M:
 	case OEM_EXCELSIOR:
-		bj = (BJ_ADAPTER_90W_MASK & BIT(sku)) ?
-			BJ_90W_19V : BJ_65W_19V;
+		bj = (BJ_ADAPTER_90W_MASK & BIT(sku)) ? BJ_90W_19V : BJ_65W_19V;
 		break;
 	case OEM_JAX:
 		bj = BJ_65W_19V;
 		break;
 	default:
-		bj = (BJ_ADAPTER_90W_MASK & BIT(sku)) ?
-			BJ_90W_19P5V : BJ_65W_19P5V;
+		bj = (BJ_ADAPTER_90W_MASK & BIT(sku)) ? BJ_90W_19P5V :
+							BJ_65W_19P5V;
 		break;
 	}
 
@@ -795,8 +785,8 @@ static void board_charge_manager_init(void)
 			charge_manager_update_charge(j, i, NULL);
 	}
 
-	port = gpio_get_level(GPIO_ADP_IN_L) ?
-			CHARGE_PORT_TYPEC0 : CHARGE_PORT_BARRELJACK;
+	port = gpio_get_level(GPIO_ADP_IN_L) ? CHARGE_PORT_TYPEC0 :
+					       CHARGE_PORT_BARRELJACK;
 	CPRINTS("Power source is p%d (%s)", port,
 		port == CHARGE_PORT_TYPEC0 ? "USB-C" : "BJ");
 
@@ -855,8 +845,7 @@ int fan_percent_to_rpm(int fan, int pct)
 
 	previous_pct = pct;
 
-	if (fan_table[current_level].rpm !=
-		fan_get_rpm_target(FAN_CH(fan)))
+	if (fan_table[current_level].rpm != fan_get_rpm_target(FAN_CH(fan)))
 		cprints(CC_THERMAL, "Setting fan RPM to %d",
 			fan_table[current_level].rpm);
 
diff --git a/board/fizz/board.h b/board/fizz/board.h
index ad1ca85cac..a1499f6105 100644
--- a/board/fizz/board.h
+++ b/board/fizz/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,7 +12,7 @@
  * Allow dangerous commands.
  * TODO: Remove this config before production.
  */
-#undef  CONFIG_SYSTEM_UNLOCKED
+#undef CONFIG_SYSTEM_UNLOCKED
 #define CONFIG_USB_PD_COMM_LOCKED
 
 /* EC */
@@ -32,7 +32,7 @@
 #define CONFIG_FPU
 #define CONFIG_I2C
 #define CONFIG_I2C_CONTROLLER
-#undef  CONFIG_LID_SWITCH
+#undef CONFIG_LID_SWITCH
 #define CONFIG_POWER_BUTTON_IGNORE_LID
 #define CONFIG_PWM
 #define CONFIG_LTO
@@ -47,7 +47,7 @@
 #define WIRELESS_GPIO_WLAN_POWER GPIO_PP3300_DX_WLAN
 #define WIRELESS_GPIO_WWAN GPIO_PP3300_DX_LTE
 #define CEC_GPIO_OUT GPIO_CEC_OUT
-#define CEC_GPIO_IN  GPIO_CEC_IN
+#define CEC_GPIO_IN GPIO_CEC_IN
 #define CEC_GPIO_PULL_UP GPIO_CEC_PULL_UP
 #define CONFIG_FANS 1
 #undef CONFIG_FAN_INIT_SPEED
@@ -63,7 +63,7 @@
 #undef CONFIG_CMD_ADC
 
 /* Reduce flash space usage */
-#undef  CONFIG_CONSOLE_CMDHELP
+#undef CONFIG_CONSOLE_CMDHELP
 
 /* SOC */
 #define CONFIG_CHIPSET_SKYLAKE
@@ -71,8 +71,8 @@
 #define CONFIG_CHIPSET_HAS_PRE_INIT_CALLBACK
 #define CONFIG_CHIPSET_RESET_HOOK
 #define CONFIG_HOST_INTERFACE_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 #define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD
 
 /* Charger */
@@ -82,7 +82,7 @@
 
 #define CONFIG_HOSTCMD_PD_CONTROL
 #define CONFIG_EXTPOWER_GPIO
-#undef  CONFIG_EXTPOWER_DEBOUNCE_MS
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
 #define CONFIG_EXTPOWER_DEBOUNCE_MS 1000
 #define CONFIG_POWER_BUTTON
 #define CONFIG_POWER_BUTTON_X86
@@ -96,7 +96,7 @@
 #define CONFIG_TEMP_SENSOR_TMP432
 
 /* USB */
-#undef  CONFIG_USB_CHARGER		/* dnojiri: verify */
+#undef CONFIG_USB_CHARGER /* dnojiri: verify */
 #define CONFIG_USB_PD_ALT_MODE
 #define CONFIG_USB_PD_ALT_MODE_DFP
 #define CONFIG_USB_PD_CUSTOM_PDO
@@ -119,7 +119,7 @@
 #define CONFIG_USBC_VCONN_SWAP
 
 /* Charge ports */
-#undef  CONFIG_DEDICATED_CHARGE_PORT_COUNT
+#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT
 #define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1
 #define DEDICATED_CHARGE_PORT 1
 
@@ -128,21 +128,21 @@
 #define USB_PORT_COUNT 5
 
 /* Optional feature to configure npcx chip */
-#define NPCX_UART_MODULE2	1 /* 1:GPIO64/65 as UART */
-#define NPCX_JTAG_MODULE2	0 /* 0:GPIO21/17/16/20 as JTAG */
-#define NPCX_TACH_SEL2		1 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
+#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART */
+#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 as JTAG */
+#define NPCX_TACH_SEL2 1 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
 
 /* I2C ports */
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT0_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT0_1
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT1
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT1
-#define I2C_PORT_PMIC		NPCX_I2C_PORT2
-#define I2C_PORT_THERMAL	NPCX_I2C_PORT3
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT0_1
+#define I2C_PORT_BATTERY NPCX_I2C_PORT1
+#define I2C_PORT_CHARGER NPCX_I2C_PORT1
+#define I2C_PORT_PMIC NPCX_I2C_PORT2
+#define I2C_PORT_THERMAL NPCX_I2C_PORT3
 
 /* I2C addresses */
-#define I2C_ADDR_TCPC0_FLAGS		0x0b
-#define I2C_ADDR_EEPROM_FLAGS		0x50
+#define I2C_ADDR_TCPC0_FLAGS 0x0b
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 
 /* Verify and jump to RW image on boot */
 #define CONFIG_VBOOT_EFS
@@ -159,18 +159,17 @@
  * end of RW_A and RW_B, respectively.
  */
 #define CONFIG_RW_B
-#define CONFIG_RW_B_MEM_OFF		CONFIG_RO_MEM_OFF
-#undef  CONFIG_RO_SIZE
-#define CONFIG_RO_SIZE			(CONFIG_FLASH_SIZE_BYTES / 4)
-#undef  CONFIG_RW_SIZE
-#define CONFIG_RW_SIZE			CONFIG_RO_SIZE
-#define CONFIG_RW_A_STORAGE_OFF		CONFIG_RW_STORAGE_OFF
-#define CONFIG_RW_B_STORAGE_OFF		(CONFIG_RW_A_STORAGE_OFF + \
-					 CONFIG_RW_SIZE)
-#define CONFIG_RW_A_SIGN_STORAGE_OFF	(CONFIG_RW_A_STORAGE_OFF + \
-					 CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE)
-#define CONFIG_RW_B_SIGN_STORAGE_OFF	(CONFIG_RW_B_STORAGE_OFF + \
-					 CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE)
+#define CONFIG_RW_B_MEM_OFF CONFIG_RO_MEM_OFF
+#undef CONFIG_RO_SIZE
+#define CONFIG_RO_SIZE (CONFIG_FLASH_SIZE_BYTES / 4)
+#undef CONFIG_RW_SIZE
+#define CONFIG_RW_SIZE CONFIG_RO_SIZE
+#define CONFIG_RW_A_STORAGE_OFF CONFIG_RW_STORAGE_OFF
+#define CONFIG_RW_B_STORAGE_OFF (CONFIG_RW_A_STORAGE_OFF + CONFIG_RW_SIZE)
+#define CONFIG_RW_A_SIGN_STORAGE_OFF \
+	(CONFIG_RW_A_STORAGE_OFF + CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE)
+#define CONFIG_RW_B_SIGN_STORAGE_OFF \
+	(CONFIG_RW_B_STORAGE_OFF + CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE)
 
 #define CONFIG_RWSIG
 #define CONFIG_RWSIG_TYPE_RWSIG
@@ -196,15 +195,12 @@ enum charge_port {
 };
 
 enum temp_sensor_id {
-	TEMP_SENSOR_CHARGER,	/* BD99992GW SYSTHERM1 */
-	TEMP_SENSOR_DRAM,	/* BD99992GW SYSTHERM2 */
+	TEMP_SENSOR_CHARGER, /* BD99992GW SYSTHERM1 */
+	TEMP_SENSOR_DRAM, /* BD99992GW SYSTHERM2 */
 	TEMP_SENSOR_COUNT
 };
 
-enum adc_channel {
-	ADC_VBUS,
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_VBUS, ADC_CH_COUNT };
 
 enum pwm_channel {
 	PWM_CH_LED_RED,
@@ -245,17 +241,17 @@ enum OEM_ID {
  * delay to turn on the power supply max is ~16ms.
  * delay to turn off the power supply max is about ~180ms.
  */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	250000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* delay to turn on/off vconn */
 
 /* Define typical operating power. Since Fizz doesn't have a battery to charge,
  * we're not interested in any power lower than the AP power-on threshold. */
-#define PD_OPERATING_POWER_MW	CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
-#define PD_MAX_POWER_MW		100000
-#define PD_MAX_CURRENT_MA	5000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
+#define PD_MAX_POWER_MW 100000
+#define PD_MAX_CURRENT_MA 5000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Board specific handlers */
 void board_reset_pd_mcu(void);
diff --git a/board/fizz/build.mk b/board/fizz/build.mk
index febbb7fac2..b07b1b4cf3 100644
--- a/board/fizz/build.mk
+++ b/board/fizz/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/fizz/ec.tasklist b/board/fizz/ec.tasklist
index 75a09a43df..6212516e6a 100644
--- a/board/fizz/ec.tasklist
+++ b/board/fizz/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/fizz/gpio.inc b/board/fizz/gpio.inc
index 7da0bfce71..2eee02bfd3 100644
--- a/board/fizz/gpio.inc
+++ b/board/fizz/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,10 +13,10 @@ GPIO_INT(AC_PRESENT,		PIN(C, 1), GPIO_INT_BOTH,			extpower_interrupt)
 GPIO_INT(POWER_BUTTON_L,	PIN(0, 4), GPIO_INT_BOTH | GPIO_PULL_UP,	power_button_interrupt)	/* MECH_PWR_BTN_ODL */
 
 GPIO_INT(PCH_SLP_S0_L,		PIN(7, 5), GPIO_INT_BOTH,			power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(PCH_SLP_S3_L,		PIN(7, 3), GPIO_INT_BOTH,			power_signal_interrupt)
 #endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 GPIO_INT(PCH_SLP_S4_L,		PIN(8, 6), GPIO_INT_BOTH,			power_signal_interrupt)
 #endif
 GPIO_INT(PCH_SLP_SUS_L,		PIN(6, 2), GPIO_INT_BOTH,			power_signal_interrupt)
diff --git a/board/fizz/led.c b/board/fizz/led.c
index 9b6942d241..acd0eb5918 100644
--- a/board/fizz/led.c
+++ b/board/fizz/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -15,7 +15,7 @@
 #include "timer.h"
 #include "util.h"
 
-const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 enum led_color {
@@ -76,9 +76,9 @@ static int set_color(enum ec_led_id id, enum led_color color, int duty)
 	}
 }
 
-#define LED_PULSE_US		(2 * SECOND)
+#define LED_PULSE_US (2 * SECOND)
 /* 40 msec for nice and smooth transition. */
-#define LED_PULSE_TICK_US	(40 * MSEC)
+#define LED_PULSE_TICK_US (40 * MSEC)
 
 /* When pulsing is enabled, brightness is incremented by <duty_inc> every
  * <interval> usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented
@@ -181,7 +181,7 @@ void led_critical(void)
 		set_color(EC_LED_ID_POWER_LED, LED_RED, 100);
 }
 
-static int command_led(int argc, char **argv)
+static int command_led(int argc, const char **argv)
 {
 	enum ec_led_id id = EC_LED_ID_POWER_LED;
 
diff --git a/board/fizz/usb_pd_pdo.c b/board/fizz/usb_pd_pdo.c
index bb612affef..edcc43f15a 100644
--- a/board/fizz/usb_pd_pdo.c
+++ b/board/fizz/usb_pd_pdo.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,8 +7,8 @@
 #include "usb_pd.h"
 #include "usb_pd_pdo.h"
 
-#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\
-			 PDO_FIXED_COMM_CAP)
+#define PDO_FIXED_FLAGS \
+	(PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP | PDO_FIXED_COMM_CAP)
 
 const uint32_t pd_src_pdo[] = {
 	PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS),
diff --git a/board/fizz/usb_pd_pdo.h b/board/fizz/usb_pd_pdo.h
index de4f8f9474..97ee437a3f 100644
--- a/board/fizz/usb_pd_pdo.h
+++ b/board/fizz/usb_pd_pdo.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/fizz/usb_pd_policy.c b/board/fizz/usb_pd_policy.c
index 5fc495417f..b3b1ee5971 100644
--- a/board/fizz/usb_pd_policy.c
+++ b/board/fizz/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,8 +23,8 @@
 #include "usb_pd_pdo.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int board_vbus_source_enabled(int port)
 {
diff --git a/board/fleex/battery.c b/board/fleex/battery.c
index 57a5246052..e5efb19920 100644
--- a/board/fleex/battery.c
+++ b/board/fleex/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/fleex/board.c b/board/fleex/board.c
index 4464d45730..063222fbe3 100644
--- a/board/fleex/board.c
+++ b/board/fleex/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -42,11 +42,11 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define USB_PD_PORT_ANX7447	0
-#define USB_PD_PORT_PS8751	1
+#define USB_PD_PORT_ANX7447 0
+#define USB_PD_PORT_PS8751 1
 
 static uint8_t sku_id;
 static int is_support_syv_ppc;
@@ -74,11 +74,9 @@ static void board_update_ppc_config_from_board(void)
 	if (!is_support_syv_ppc)
 		return;
 
-	memcpy(&ppc_chips[USB_PD_PORT_TCPC_0],
-	       &ppc_syv682x_port0,
+	memcpy(&ppc_chips[USB_PD_PORT_TCPC_0], &ppc_syv682x_port0,
 	       sizeof(struct ppc_config_t));
-	memcpy(&ppc_chips[USB_PD_PORT_TCPC_1],
-	       &ppc_syv682x_port1,
+	memcpy(&ppc_chips[USB_PD_PORT_TCPC_1], &ppc_syv682x_port1,
 	       sizeof(struct ppc_config_t));
 
 	gpio_set_flags(GPIO_USB_PD_C0_INT_ODL, GPIO_INT_BOTH);
@@ -112,28 +110,30 @@ static void ppc_interrupt(enum gpio_signal signal)
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_AMB] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_VBUS_C0] = {"VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
-	[ADC_VBUS_C1] = {"VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_AMB] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				  ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_CHARGER] = { "TEMP_CHARGER", NPCX_ADC_CH1,
+				      ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 },
+	[ADC_VBUS_C0] = { "VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT * 10,
+			  ADC_READ_MAX + 1, 0 },
+	[ADC_VBUS_C1] = { "VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT * 10,
+			  ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp,
-				 .idx = 0},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
+	[TEMP_SENSOR_BATTERY] = { .name = "Battery",
+				  .type = TEMP_SENSOR_TYPE_BATTERY,
+				  .read = charge_get_battery_temp,
+				  .idx = 0 },
+	[TEMP_SENSOR_AMBIENT] = { .name = "Ambient",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_51k1_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_AMB },
+	[TEMP_SENSOR_CHARGER] = { .name = "Charger",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_13k7_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_CHARGER },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -143,17 +143,13 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrix to rotate accelerometer into standard reference frame */
-const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1),  0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
+const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+				      { FLOAT_TO_FP(-1), 0, 0 },
+				      { 0, 0, FLOAT_TO_FP(1) } };
 
- const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0,  0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
- };
+const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				       { 0, FLOAT_TO_FP(-1), 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
 
 /* sensor private data */
 static struct stprivate_data g_lis2dh_data;
@@ -242,8 +238,8 @@ unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
 static int board_is_convertible(void)
 {
-	return sku_id == 0x21 || sku_id == 0x22 || sku_id == 0x23
-		|| sku_id == 0xff;
+	return sku_id == 0x21 || sku_id == 0x22 || sku_id == 0x23 ||
+	       sku_id == 0xff;
 }
 
 static void board_update_sensor_config_from_sku(void)
@@ -300,9 +296,10 @@ void board_overcurrent_event(int port, int is_overcurrented)
 static void charger_set_buck_boost_mode(void)
 {
 	int reg;
-	/* Reduce Buck-boost mode switching frequency to improve power efficiency. */
+	/* Reduce Buck-boost mode switching frequency to improve power
+	 * efficiency. */
 	if (i2c_read16(I2C_PORT_CHARGER, I2C_ADDR_CHARGER_FLAGS,
-			ISL9238_REG_CONTROL3, &reg) == EC_SUCCESS) {
+		       ISL9238_REG_CONTROL3, &reg) == EC_SUCCESS) {
 		reg |= ISL9238_C3_BB_SWITCHING_PERIOD;
 		if (i2c_write16(I2C_PORT_CHARGER, I2C_ADDR_CHARGER_FLAGS,
 				ISL9238_REG_CONTROL3, reg))
diff --git a/board/fleex/board.h b/board/fleex/board.h
index b097685449..3095fad271 100644
--- a/board/fleex/board.h
+++ b/board/fleex/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -33,8 +33,8 @@
 #define CONFIG_USB_PD_RESET_MIN_BATT_SOC 2
 
 /* Sensors */
-#define CONFIG_ACCEL_LIS2DE		/* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM	/* Base accel */
+#define CONFIG_ACCEL_LIS2DE /* Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
 /* Sensors without hardware FIFO are in forced mode */
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
 #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
@@ -80,10 +80,10 @@
 #include "registers.h"
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_AMB,		/* ADC0 */
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC1 */
-	ADC_VBUS_C0,			/* ADC9 */
-	ADC_VBUS_C1,			/* ADC4 */
+	ADC_TEMP_SENSOR_AMB, /* ADC0 */
+	ADC_TEMP_SENSOR_CHARGER, /* ADC1 */
+	ADC_VBUS_C0, /* ADC9 */
+	ADC_VBUS_C1, /* ADC4 */
 	ADC_CH_COUNT
 };
 
@@ -94,18 +94,10 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_COUNT };
 
 /* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
diff --git a/board/fleex/build.mk b/board/fleex/build.mk
index 7e806f4667..0eab0adc21 100644
--- a/board/fleex/build.mk
+++ b/board/fleex/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/fleex/ec.tasklist b/board/fleex/ec.tasklist
index d98db145e7..977b8b01be 100644
--- a/board/fleex/ec.tasklist
+++ b/board/fleex/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/fleex/gpio.inc b/board/fleex/gpio.inc
index efedd6989b..0b74f8fa76 100644
--- a/board/fleex/gpio.inc
+++ b/board/fleex/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/fleex/led.c b/board/fleex/led.c
index bf3fd6ccec..4ba3c18457 100644
--- a/board/fleex/led.c
+++ b/board/fleex/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,8 +10,8 @@
 #include "led_common.h"
 #include "led_onoff_states.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
 __override const int led_charge_lvl_1 = 10;
 
@@ -19,23 +19,32 @@ __override const int led_charge_lvl_2 = 100;
 
 /* Fleex: Note there is only LED for charge / power */
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_S5]     = {{LED_OFF,	     LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     1 * LED_ONE_SEC },
+					   { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_WHITE,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 BUILD_ASSERT(ARRAY_SIZE(led_bat_state_table) == LED_NUM_STATES);
 
 const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
diff --git a/board/fleex/usb_pd_policy.c b/board/fleex/usb_pd_policy.c
index 82922f9a4d..bfcf4484e4 100644
--- a/board/fleex/usb_pd_policy.c
+++ b/board/fleex/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/fluffy/board.c b/board/fluffy/board.c
index 874195404b..90de54a761 100644
--- a/board/fluffy/board.c
+++ b/board/fluffy/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,20 +19,20 @@
 
 #include "gpio_list.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
 /******************************************************************************
  * Define the strings used in our USB descriptors.
  */
 
 const void *const usb_strings[] = {
-	[USB_STR_DESC]         = usb_string_desc,
-	[USB_STR_VENDOR]       = USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]      = USB_STRING_DESC("Fluffy"),
+	[USB_STR_DESC] = usb_string_desc,
+	[USB_STR_VENDOR] = USB_STRING_DESC("Google LLC"),
+	[USB_STR_PRODUCT] = USB_STRING_DESC("Fluffy"),
 	/* This gets filled in at runtime. */
-	[USB_STR_SERIALNO]     = USB_STRING_DESC(""),
-	[USB_STR_VERSION]      = USB_STRING_DESC(CROS_EC_VERSION32),
+	[USB_STR_SERIALNO] = USB_STRING_DESC(""),
+	[USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32),
 	[USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Fluffy Shell"),
 };
 
@@ -77,7 +77,7 @@ static void print_port_status(void)
 	CPRINTS("USB MUX: %s", gpio_get_level(GPIO_EN_USB_MUX2) ? "ON" : "OFF");
 }
 
-static int command_cc_flip(int argc, char *argv[])
+static int command_cc_flip(int argc, const char *argv[])
 {
 	int enable;
 
@@ -106,20 +106,19 @@ static int command_cc_flip(int argc, char *argv[])
 	print_port_status();
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(ccflip, command_cc_flip,
-			"<enable/disable>",
+DECLARE_CONSOLE_COMMAND(ccflip, command_cc_flip, "<enable/disable>",
 			"enable or disable flipping CC orientation");
 /*
  * Support tca6416 I2C ioexpander.
  */
-#define GPIOX_I2C_ADDR_FLAGS	0x20
-#define GPIOX_IN_PORT_A		0x0
-#define GPIOX_IN_PORT_B		0x1
-#define GPIOX_OUT_PORT_A	0x2
-#define GPIOX_OUT_PORT_B	0x3
-#define GPIOX_DIR_PORT_A	0x6
-#define GPIOX_DIR_PORT_B	0x7
-#define I2C_PORT_MASTER		1
+#define GPIOX_I2C_ADDR_FLAGS 0x20
+#define GPIOX_IN_PORT_A 0x0
+#define GPIOX_IN_PORT_B 0x1
+#define GPIOX_OUT_PORT_A 0x2
+#define GPIOX_OUT_PORT_B 0x3
+#define GPIOX_DIR_PORT_A 0x6
+#define GPIOX_DIR_PORT_B 0x7
+#define I2C_PORT_MASTER 1
 
 static void i2c_expander_init(void)
 {
@@ -128,12 +127,12 @@ static void i2c_expander_init(void)
 	/*
 	 * Setup P00, P02, P04, P10, and P12 on the I/O expander as an output.
 	 */
-	i2c_write8(I2C_PORT_MASTER, GPIOX_I2C_ADDR_FLAGS,
-		   GPIOX_DIR_PORT_A, 0xea);
-	i2c_write8(I2C_PORT_MASTER, GPIOX_I2C_ADDR_FLAGS,
-		   GPIOX_DIR_PORT_B, 0xfa);
+	i2c_write8(I2C_PORT_MASTER, GPIOX_I2C_ADDR_FLAGS, GPIOX_DIR_PORT_A,
+		   0xea);
+	i2c_write8(I2C_PORT_MASTER, GPIOX_I2C_ADDR_FLAGS, GPIOX_DIR_PORT_B,
+		   0xfa);
 }
-DECLARE_HOOK(HOOK_INIT, i2c_expander_init, HOOK_PRIO_INIT_I2C+1);
+DECLARE_HOOK(HOOK_INIT, i2c_expander_init, HOOK_PRIO_INIT_I2C + 1);
 
 /* Write to a GPIO register on the tca6416 I2C ioexpander. */
 static void write_ioexpander(int bank, int gpio, int reg, int val)
@@ -141,15 +140,13 @@ static void write_ioexpander(int bank, int gpio, int reg, int val)
 	int tmp;
 
 	/* Read output port register */
-	i2c_read8(I2C_PORT_MASTER, GPIOX_I2C_ADDR_FLAGS,
-		  reg + bank, &tmp);
+	i2c_read8(I2C_PORT_MASTER, GPIOX_I2C_ADDR_FLAGS, reg + bank, &tmp);
 	if (val)
 		tmp |= BIT(gpio);
 	else
 		tmp &= ~BIT(gpio);
 	/* Write back modified output port register */
-	i2c_write8(I2C_PORT_MASTER, GPIOX_I2C_ADDR_FLAGS,
-		   reg + bank, tmp);
+	i2c_write8(I2C_PORT_MASTER, GPIOX_I2C_ADDR_FLAGS, reg + bank, tmp);
 }
 
 enum led_ch {
@@ -227,7 +224,6 @@ static void board_init(void)
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
-
 enum usb_mux {
 	USB_MUX0 = 0,
 	USB_MUX1,
@@ -272,7 +268,7 @@ static void set_mux(enum usb_mux mux, uint8_t val)
 }
 
 /* This function assumes only 1 port works at a time. */
-static int command_portctl(int argc, char **argv)
+static int command_portctl(int argc, const char **argv)
 {
 	int port;
 	int enable;
@@ -293,7 +289,7 @@ static int command_portctl(int argc, char **argv)
 
 	gpio_set_level(enabled_port, 0);
 	if (enabled_port != GPIO_EN_C0 + port)
-		CPRINTS("Port %d: disabled", enabled_port-GPIO_EN_C0);
+		CPRINTS("Port %d: disabled", enabled_port - GPIO_EN_C0);
 
 	/* Allow time for an "unplug" to allow VBUS and CC to fall. */
 	usleep(1 * SECOND);
@@ -309,17 +305,17 @@ static int command_portctl(int argc, char **argv)
 		gpio_set_level(enabled_port, 1);
 
 		if (port < 8) {
-			set_mux(USB_MUX0, 7-port);
+			set_mux(USB_MUX0, 7 - port);
 			set_mux(USB_MUX2, 3);
 		} else if (port < 16) {
 			if (port < 14)
-				set_mux(USB_MUX1, 5-(port-8));
+				set_mux(USB_MUX1, 5 - (port - 8));
 			else
-				set_mux(USB_MUX1, 7-(port-14));
+				set_mux(USB_MUX1, 7 - (port - 14));
 
 			set_mux(USB_MUX2, 1);
 		} else {
-			set_mux(USB_MUX2, 7-(port-16));
+			set_mux(USB_MUX2, 7 - (port - 16));
 		}
 
 		gpio_set_level(GPIO_EN_USB_MUX2, 1);
@@ -337,11 +333,11 @@ DECLARE_CONSOLE_COMMAND(portctl, command_portctl,
 			"<port# 0-19> <enable/disable>",
 			"enable or disable a port");
 
-static int command_status(int argc, char **argv)
+static int command_status(int argc, const char **argv)
 {
 	int vbus_mv = adc_read_channel(ADC_PPVAR_VBUS_DUT);
 
-	CPRINTS("PPVAR_VBUS_DUT: %dmV (raw: %d)", vbus_mv*7692/1000,
+	CPRINTS("PPVAR_VBUS_DUT: %dmV (raw: %d)", vbus_mv * 7692 / 1000,
 		vbus_mv);
 	print_port_status();
 
@@ -388,7 +384,8 @@ void show_output_voltage_on_leds(void)
 			set_led(i, i < max_on_exclusive);
 
 		act = (vbus_mv * 76667) / 10000;
-		if ((vbus_mv > prev_vbus_mv+2) || (vbus_mv < prev_vbus_mv-2)) {
+		if ((vbus_mv > prev_vbus_mv + 2) ||
+		    (vbus_mv < prev_vbus_mv - 2)) {
 			CPRINTS("PPVAR_VBUS_DUT: %d mV (raw: %d)", act,
 				vbus_mv);
 			prev_vbus_mv = vbus_mv;
@@ -400,6 +397,5 @@ void show_output_voltage_on_leds(void)
 	 * a hook with a HOOK_TICK period is to allow the LED sweep sequence
 	 * when the board boots up.
 	 */
-	hook_call_deferred(&show_output_voltage_on_leds_data,
-			   500 * MSEC);
+	hook_call_deferred(&show_output_voltage_on_leds_data, 500 * MSEC);
 }
diff --git a/board/fluffy/board.h b/board/fluffy/board.h
index 75e9843b83..1309c41901 100644
--- a/board/fluffy/board.h
+++ b/board/fluffy/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -29,13 +29,13 @@
 #define DEFAULT_SERIALNO "Uninitialized"
 
 /* USB interface indexes (use define rather than enum to expand them) */
-#define USB_IFACE_CONSOLE	0
-#define USB_IFACE_COUNT		1
+#define USB_IFACE_CONSOLE 0
+#define USB_IFACE_COUNT 1
 
 /* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL		0
-#define USB_EP_CONSOLE		1
-#define USB_EP_COUNT		2
+#define USB_EP_CONTROL 0
+#define USB_EP_CONSOLE 1
+#define USB_EP_COUNT 2
 
 /* Optional features */
 #define CONFIG_STM_HWTIMER32
@@ -48,7 +48,7 @@
 
 /* Timer selection */
 #define TIM_CLOCK32 2
-#define TIM_ADC     3
+#define TIM_ADC 3
 
 #include "gpio_signal.h"
 
diff --git a/board/fluffy/build.mk b/board/fluffy/build.mk
index b6761a4692..82aa7522d0 100644
--- a/board/fluffy/build.mk
+++ b/board/fluffy/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -10,9 +10,4 @@ CHIP:=stm32
 CHIP_FAMILY:=stm32f0
 CHIP_VARIANT:=stm32f07x
 
-# Use coreboot-sdk
-$(call set-option,CROSS_COMPILE_arm,\
-	$(CROSS_COMPILE_coreboot_sdk_arm),\
-	/opt/coreboot-sdk/bin/arm-eabi-)
-
 board-y=board.o
diff --git a/board/fluffy/ec.tasklist b/board/fluffy/ec.tasklist
index c732944a23..9c45739414 100644
--- a/board/fluffy/ec.tasklist
+++ b/board/fluffy/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/fluffy/gpio.inc b/board/fluffy/gpio.inc
index 4c802554f9..532422ae5b 100644
--- a/board/fluffy/gpio.inc
+++ b/board/fluffy/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/foob/battery.c b/board/foob/battery.c
index 01a6654920..fe5692eec2 100644
--- a/board/foob/battery.c
+++ b/board/foob/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/foob/board.c b/board/foob/board.c
index 91d66d88d7..c9bf0934ad 100644
--- a/board/foob/board.c
+++ b/board/foob/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -31,11 +31,11 @@
 #include "util.h"
 #include "battery_smart.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define USB_PD_PORT_ANX7447	0
-#define USB_PD_PORT_PS8751	1
+#define USB_PD_PORT_ANX7447 0
+#define USB_PD_PORT_PS8751 1
 
 static uint8_t sku_id;
 
@@ -60,31 +60,31 @@ static void ppc_interrupt(enum gpio_signal signal)
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_AMB] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_AMB] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				  ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_CHARGER] = { "TEMP_CHARGER", NPCX_ADC_CH1,
+				      ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 },
 	/* Vbus sensing (1/10 voltage divider). */
-	[ADC_VBUS_C0] = {
-		"VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
-	[ADC_VBUS_C1] = {
-		"VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
+	[ADC_VBUS_C0] = { "VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT * 10,
+			  ADC_READ_MAX + 1, 0 },
+	[ADC_VBUS_C1] = { "VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT * 10,
+			  ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp,
-				 .idx = 0},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
+	[TEMP_SENSOR_BATTERY] = { .name = "Battery",
+				  .type = TEMP_SENSOR_TYPE_BATTERY,
+				  .read = charge_get_battery_temp,
+				  .idx = 0 },
+	[TEMP_SENSOR_AMBIENT] = { .name = "Ambient",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_51k1_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_AMB },
+	[TEMP_SENSOR_CHARGER] = { .name = "Charger",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_13k7_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_CHARGER },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -94,11 +94,9 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrix to rotate lid and base sensor into standard reference frame */
-const mat33_fp_t standard_rot_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
+const mat33_fp_t standard_rot_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				      { 0, FLOAT_TO_FP(-1), 0 },
+				      { 0, 0, FLOAT_TO_FP(1) } };
 
 /* sensor private data */
 static struct stprivate_data g_lis2dh_data;
@@ -238,11 +236,11 @@ int board_is_lid_angle_tablet_mode(void)
 }
 
 /* Battery functions */
-#define SB_OPTIONALMFG_FUNCTION2		0x3e
+#define SB_OPTIONALMFG_FUNCTION2 0x3e
 /* Optional mfg function2 */
-#define SMART_QUICK_CHARGE			(1<<12)
+#define SMART_QUICK_CHARGE (1 << 12)
 /* Quick charge support */
-#define MODE_QUICK_CHARGE_SUPPORT		(1<<4)
+#define MODE_QUICK_CHARGE_SUPPORT (1 << 4)
 
 static void sb_quick_charge_mode(int enable)
 {
diff --git a/board/foob/board.h b/board/foob/board.h
index 07637c3373..f6d0f20607 100644
--- a/board/foob/board.h
+++ b/board/foob/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -30,8 +30,8 @@
 #define CONFIG_CMD_ACCEL_INFO
 
 /* Sensors */
-#define CONFIG_ACCEL_LIS2DE             /* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM        /* Base accel */
+#define CONFIG_ACCEL_LIS2DE /* Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
 /* Sensors without hardware FIFO are in forced mode */
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
 
@@ -50,10 +50,10 @@
 #include "registers.h"
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_AMB,		/* ADC0 */
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC1 */
-	ADC_VBUS_C0,			/* ADC9 */
-	ADC_VBUS_C1,			/* ADC4 */
+	ADC_TEMP_SENSOR_AMB, /* ADC0 */
+	ADC_TEMP_SENSOR_CHARGER, /* ADC1 */
+	ADC_VBUS_C0, /* ADC9 */
+	ADC_VBUS_C1, /* ADC4 */
 	ADC_CH_COUNT,
 };
 
@@ -64,18 +64,10 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_COUNT };
 
 /* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
diff --git a/board/foob/build.mk b/board/foob/build.mk
index 137e208b53..fee77e38b5 100644
--- a/board/foob/build.mk
+++ b/board/foob/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/foob/ec.tasklist b/board/foob/ec.tasklist
index 6eac78a042..6c56976091 100644
--- a/board/foob/ec.tasklist
+++ b/board/foob/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/foob/gpio.inc b/board/foob/gpio.inc
index ad6773a211..3a553f6e91 100644
--- a/board/foob/gpio.inc
+++ b/board/foob/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/foob/led.c b/board/foob/led.c
index bb7764dadd..b8cdc4c252 100644
--- a/board/foob/led.c
+++ b/board/foob/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,32 +19,35 @@ __override const int led_charge_lvl_1 = 5;
 __override const int led_charge_lvl_2 = 97;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
 
 __override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-					{LED_OFF,	   0.5 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 3 * LED_ONE_SEC },
+					       { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-	EC_LED_ID_BATTERY_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED,
+					     EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
diff --git a/board/fusb307bgevb/board.c b/board/fusb307bgevb/board.c
index f3f4da1a74..1388aef49a 100644
--- a/board/fusb307bgevb/board.c
+++ b/board/fusb307bgevb/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,8 +24,8 @@
 #include "usb_common.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
@@ -72,10 +72,13 @@ static void button_refresh_event_deferred(void)
 	/* Display supply voltage on first page. */
 	lcd_clear();
 	for (i = 0; i < MIN(pd_get_src_cap_cnt(0), 4); i++) {
+		int rv;
 		pd_extract_pdo_power(pd_get_src_caps(0)[i], &ma, &mv, &unused);
-		snprintf(c, ARRAY_SIZE(c), "[%d] %dmV %dmA", i, mv, ma);
-		lcd_set_cursor(0, i);
-		lcd_print_string(c);
+		rv = snprintf(c, ARRAY_SIZE(c), "[%d] %dmV %dmA", i, mv, ma);
+		if (rv > 0) {
+			lcd_set_cursor(0, i);
+			lcd_print_string(c);
+		}
 	}
 
 	/* Display selector */
@@ -107,21 +110,29 @@ static void button_down_event_deferred(void)
 	if (count == 0) {
 		lcd_clear();
 		for (i = 0; i < MIN(pd_get_src_cap_cnt(0), 4); i++) {
+			int rv;
 			pd_extract_pdo_power(pd_get_src_caps(0)[i], &ma, &mv,
 					     &unused);
-			snprintf(c, ARRAY_SIZE(c), "[%d] %dmV %dmA", i, mv, ma);
-			lcd_set_cursor(0, i);
-			lcd_print_string(c);
+			rv = snprintf(c, ARRAY_SIZE(c), "[%d] %dmV %dmA", i, mv,
+				      ma);
+			if (rv > 0) {
+				lcd_set_cursor(0, i);
+				lcd_print_string(c);
+			}
 		}
 	}
 	if (count == 4) {
 		lcd_clear();
 		for (i = 4; i < pd_get_src_cap_cnt(0); i++) {
+			int rv;
 			pd_extract_pdo_power(pd_get_src_caps(0)[i], &ma, &mv,
 					     &unused);
-			snprintf(c, ARRAY_SIZE(c), "[%d] %dmV %dmA", i, mv, ma);
-			lcd_set_cursor(0, i - 4);
-			lcd_print_string(c);
+			rv = snprintf(c, ARRAY_SIZE(c), "[%d] %dmV %dmA", i, mv,
+				      ma);
+			if (rv > 0) {
+				lcd_set_cursor(0, i - 4);
+				lcd_print_string(c);
+			}
 		}
 	}
 
@@ -156,20 +167,15 @@ static enum gpio_signal const usb_gpio_list[] = {
  * This instantiates struct usb_gpio_config const usb_gpio, plus several other
  * variables, all named something beginning with usb_gpio_
  */
-USB_GPIO_CONFIG(usb_gpio,
-		usb_gpio_list,
-		USB_IFACE_GPIO,
-		USB_EP_GPIO);
+USB_GPIO_CONFIG(usb_gpio, usb_gpio_list, USB_IFACE_GPIO, USB_EP_GPIO);
 
 /******************************************************************************
  * Setup USART1 as a loopback device, it just echo's back anything sent to it.
  */
 static struct usart_config const loopback_usart;
 
-static struct queue const loopback_queue =
-	QUEUE_DIRECT(64, uint8_t,
-		     loopback_usart.producer,
-		     loopback_usart.consumer);
+static struct queue const loopback_queue = QUEUE_DIRECT(
+	64, uint8_t, loopback_usart.producer, loopback_usart.consumer);
 
 static struct usart_rx_dma const loopback_rx_dma =
 	USART_RX_DMA(STM32_DMAC_CH3, 8);
@@ -177,14 +183,9 @@ static struct usart_rx_dma const loopback_rx_dma =
 static struct usart_tx_dma const loopback_tx_dma =
 	USART_TX_DMA(STM32_DMAC_CH2, 16);
 
-static struct usart_config const loopback_usart =
-	USART_CONFIG(usart1_hw,
-		     loopback_rx_dma.usart_rx,
-		     loopback_tx_dma.usart_tx,
-		     115200,
-		     0,
-		     loopback_queue,
-		     loopback_queue);
+static struct usart_config const loopback_usart = USART_CONFIG(
+	usart1_hw, loopback_rx_dma.usart_rx, loopback_tx_dma.usart_tx, 115200,
+	0, loopback_queue, loopback_queue);
 
 /******************************************************************************
  * Forward USART4 as a simple USB serial interface.
@@ -192,46 +193,34 @@ static struct usart_config const loopback_usart =
 static struct usart_config const forward_usart;
 struct usb_stream_config const forward_usb;
 
-static struct queue const usart_to_usb = QUEUE_DIRECT(64, uint8_t,
-						      forward_usart.producer,
-						      forward_usb.consumer);
-static struct queue const usb_to_usart = QUEUE_DIRECT(64, uint8_t,
-						      forward_usb.producer,
-						      forward_usart.consumer);
+static struct queue const usart_to_usb =
+	QUEUE_DIRECT(64, uint8_t, forward_usart.producer, forward_usb.consumer);
+static struct queue const usb_to_usart =
+	QUEUE_DIRECT(64, uint8_t, forward_usb.producer, forward_usart.consumer);
 
 static struct usart_tx_dma const forward_tx_dma =
 	USART_TX_DMA(STM32_DMAC_CH7, 16);
 
 static struct usart_config const forward_usart =
-	USART_CONFIG(usart4_hw,
-		     usart_rx_interrupt,
-		     forward_tx_dma.usart_tx,
-		     115200,
-		     0,
-		     usart_to_usb,
-		     usb_to_usart);
-
-#define USB_STREAM_RX_SIZE	16
-#define USB_STREAM_TX_SIZE	16
-
-USB_STREAM_CONFIG(forward_usb,
-		  USB_IFACE_STREAM,
-		  USB_STR_STREAM_NAME,
-		  USB_EP_STREAM,
-		  USB_STREAM_RX_SIZE,
-		  USB_STREAM_TX_SIZE,
-		  usb_to_usart,
-		  usart_to_usb)
+	USART_CONFIG(usart4_hw, usart_rx_interrupt, forward_tx_dma.usart_tx,
+		     115200, 0, usart_to_usb, usb_to_usart);
+
+#define USB_STREAM_RX_SIZE 16
+#define USB_STREAM_TX_SIZE 16
+
+USB_STREAM_CONFIG(forward_usb, USB_IFACE_STREAM, USB_STR_STREAM_NAME,
+		  USB_EP_STREAM, USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE,
+		  usb_to_usart, usart_to_usb)
 
 /******************************************************************************
  * Define the strings used in our USB descriptors.
  */
 const void *const usb_strings[] = {
-	[USB_STR_DESC]         = usb_string_desc,
-	[USB_STR_VENDOR]       = USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]      = USB_STRING_DESC("fusb307bgevb"),
-	[USB_STR_VERSION]      = USB_STRING_DESC(CROS_EC_VERSION32),
-	[USB_STR_STREAM_NAME]  = USB_STRING_DESC("Forward"),
+	[USB_STR_DESC] = usb_string_desc,
+	[USB_STR_VENDOR] = USB_STRING_DESC("Google LLC"),
+	[USB_STR_PRODUCT] = USB_STRING_DESC("fusb307bgevb"),
+	[USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32),
+	[USB_STR_STREAM_NAME] = USB_STRING_DESC("Forward"),
 	[USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Shell"),
 };
 
@@ -240,15 +229,11 @@ BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
 /******************************************************************************
  * I2C interface.
  */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "tcpc",
-		.port = I2C_PORT_TCPC,
-		.kbps = 400 /* kHz */,
-		.scl  = GPIO_I2C2_SCL,
-		.sda  = GPIO_I2C2_SDA
-	}
-};
+const struct i2c_port_t i2c_ports[] = { { .name = "tcpc",
+					  .port = I2C_PORT_TCPC,
+					  .kbps = 400 /* kHz */,
+					  .scl = GPIO_I2C2_SCL,
+					  .sda = GPIO_I2C2_SDA } };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
 /******************************************************************************
@@ -265,7 +250,6 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-
 uint16_t tcpc_get_alert_status(void)
 {
 	uint16_t status = 0;
@@ -329,6 +313,5 @@ static void board_init(void)
 	queue_init(&usb_to_usart);
 	usart_init(&loopback_usart);
 	usart_init(&forward_usart);
-
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/fusb307bgevb/board.h b/board/fusb307bgevb/board.h
index 3495f7125f..5e45b346b7 100644
--- a/board/fusb307bgevb/board.h
+++ b/board/fusb307bgevb/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,6 +8,7 @@
 #ifndef __CROS_EC_BOARD_H
 #define __CROS_EC_BOARD_H
 
+#define CONFIG_LTO
 
 /* 48 MHz SYSCLK clock frequency */
 #define CPU_CLOCK 48000000
@@ -56,11 +57,11 @@
 #define PD_OPERATING_POWER_MW 15000
 #define PD_MAX_VOLTAGE_MV 20000
 #define PD_MAX_CURRENT_MA 3000
-#define PD_MAX_POWER_MW       ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
+#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
 
 /* Degine board specific type-C power constants */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY 160000  /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 160000 /* us */
 
 /* I2C master port connected to the TCPC */
 #define I2C_PORT_TCPC 1
@@ -69,23 +70,24 @@
 #define LCD_SLAVE_ADDR 0x27
 
 /* USB interface indexes (use define rather than enum to expand them) */
-#define USB_IFACE_STREAM  0
-#define USB_IFACE_GPIO    1
-#define USB_IFACE_SPI     2
+#define USB_IFACE_STREAM 0
+#define USB_IFACE_GPIO 1
+#define USB_IFACE_SPI 2
 #define USB_IFACE_CONSOLE 3
-#define USB_IFACE_COUNT   4
+#define USB_IFACE_COUNT 4
 
 /* USB endpoint indexes (use define rather than enum to expand them) */
 #define USB_EP_CONTROL 0
-#define USB_EP_STREAM  1
-#define USB_EP_GPIO    2
-#define USB_EP_SPI     3
+#define USB_EP_STREAM 1
+#define USB_EP_GPIO 2
+#define USB_EP_SPI 3
 #define USB_EP_CONSOLE 4
-#define USB_EP_COUNT   5
+#define USB_EP_COUNT 5
 
 /* Enable control of GPIOs over USB */
 #define CONFIG_USB_GPIO
 
+#undef CONFIG_CMD_GETTIME
 #undef CONFIG_WATCHDOG_HELP
 #undef CONFIG_LID_SWITCH
 
diff --git a/board/fusb307bgevb/build.mk b/board/fusb307bgevb/build.mk
index 1372562107..923b144165 100644
--- a/board/fusb307bgevb/build.mk
+++ b/board/fusb307bgevb/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/fusb307bgevb/ec.tasklist b/board/fusb307bgevb/ec.tasklist
index e25b8f7a68..bca2d075be 100644
--- a/board/fusb307bgevb/ec.tasklist
+++ b/board/fusb307bgevb/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/fusb307bgevb/gpio.inc b/board/fusb307bgevb/gpio.inc
index 16a845576d..ba3b84fb08 100644
--- a/board/fusb307bgevb/gpio.inc
+++ b/board/fusb307bgevb/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/fusb307bgevb/lcd.c b/board/fusb307bgevb/lcd.c
index 892888329e..f907de7462 100644
--- a/board/fusb307bgevb/lcd.c
+++ b/board/fusb307bgevb/lcd.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -26,17 +26,17 @@ static struct lcd_state_info state = {
 /* write either command or data */
 static void expander_write(uint8_t data)
 {
-	i2c_write8(I2C_PORT_TCPC, LCD_SLAVE_ADDR, 0x00, data |
-		state.backlightval);
+	i2c_write8(I2C_PORT_TCPC, LCD_SLAVE_ADDR, 0x00,
+		   data | state.backlightval);
 }
 
 static void pulse_enable(uint8_t data)
 {
-	expander_write(data | LCD_EN);/* En high */
-	usleep(1);	/* enable pulse must be >450ns */
+	expander_write(data | LCD_EN); /* En high */
+	usleep(1); /* enable pulse must be >450ns */
 
-	expander_write(data & ~LCD_EN);/* En low */
-	usleep(50);	/* commands need > 37us to settle */
+	expander_write(data & ~LCD_EN); /* En low */
+	usleep(50); /* commands need > 37us to settle */
 }
 
 static void write_4bits(uint8_t value)
@@ -63,8 +63,8 @@ static void command(uint8_t value)
 /********** high level commands, for the user! */
 void lcd_clear(void)
 {
-	command(LCD_CLEAR_DISPLAY);/* clear display, set cursor to zero */
-	usleep(2000);	/* this command takes a long time! */
+	command(LCD_CLEAR_DISPLAY); /* clear display, set cursor to zero */
+	usleep(2000); /* this command takes a long time! */
 }
 
 void lcd_set_cursor(uint8_t col, uint8_t row)
diff --git a/board/fusb307bgevb/lcd.h b/board/fusb307bgevb/lcd.h
index 21b0ee9ce9..9ed773d92f 100644
--- a/board/fusb307bgevb/lcd.h
+++ b/board/fusb307bgevb/lcd.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,50 +11,50 @@
 #include "common.h"
 
 /* commands */
-#define LCD_CLEAR_DISPLAY	BIT(0)
-#define LCD_RETURN_HOME		BIT(1)
-#define LCD_ENTRYMODE_SET	BIT(2)
-#define LCD_DISPLAY_CONTROL	BIT(3)
-#define LCD_CURSOR_SHIFT	BIT(4)
-#define LCD_FUNCTION_SET	BIT(5)
-#define LCD_SET_CGRAMADDR	BIT(6)
-#define LCD_SET_DDRAMADDR	BIT(7)
+#define LCD_CLEAR_DISPLAY BIT(0)
+#define LCD_RETURN_HOME BIT(1)
+#define LCD_ENTRYMODE_SET BIT(2)
+#define LCD_DISPLAY_CONTROL BIT(3)
+#define LCD_CURSOR_SHIFT BIT(4)
+#define LCD_FUNCTION_SET BIT(5)
+#define LCD_SET_CGRAMADDR BIT(6)
+#define LCD_SET_DDRAMADDR BIT(7)
 
 /* flags for display entry mode */
-#define LCD_ENTRY_RIGHT			0x00
-#define LCD_ENTRY_LEFT			BIT(1)
-#define LCD_ENTRY_SHIFT_INCREMENT	BIT(0)
-#define LCD_ENTRY_SHIFT_DECREMENT	0x00
+#define LCD_ENTRY_RIGHT 0x00
+#define LCD_ENTRY_LEFT BIT(1)
+#define LCD_ENTRY_SHIFT_INCREMENT BIT(0)
+#define LCD_ENTRY_SHIFT_DECREMENT 0x00
 
 /* flags for display on/off control */
-#define LCD_DISPLAY_ON	BIT(2)
-#define LCD_DISPLAY_OFF	0x00
-#define LCD_CURSOR_ON	BIT(1)
-#define LCD_CURSOR_OFF	0x00
-#define LCD_BLINK_ON	BIT(0)
-#define LCD_BLINK_OFF	0x00
+#define LCD_DISPLAY_ON BIT(2)
+#define LCD_DISPLAY_OFF 0x00
+#define LCD_CURSOR_ON BIT(1)
+#define LCD_CURSOR_OFF 0x00
+#define LCD_BLINK_ON BIT(0)
+#define LCD_BLINK_OFF 0x00
 
 /* flags for display/cursor shift */
-#define LCD_DISPLAY_MOVE	BIT(3)
-#define LCD_CURSOR_MOVE		0x00
-#define LCD_MOVE_RIGHT		BIT(2)
-#define LCD_MOVE_LEFT		0x00
+#define LCD_DISPLAY_MOVE BIT(3)
+#define LCD_CURSOR_MOVE 0x00
+#define LCD_MOVE_RIGHT BIT(2)
+#define LCD_MOVE_LEFT 0x00
 
 /* flags for function set */
-#define LCD_8BITMODE	BIT(4)
-#define LCD_4BITMODE	0x00
-#define LCD_2LINE	BIT(3)
-#define LCD_1LINE	0x00
-#define LCD_5X10DOTS	BIT(2)
-#define LCD_5X8DOTS	0x00
+#define LCD_8BITMODE BIT(4)
+#define LCD_4BITMODE 0x00
+#define LCD_2LINE BIT(3)
+#define LCD_1LINE 0x00
+#define LCD_5X10DOTS BIT(2)
+#define LCD_5X8DOTS 0x00
 
 /* flags for backlight control */
-#define LCD_BACKLIGHT		BIT(3)
-#define LCD_NO_BACKLIGHT	0x00
+#define LCD_BACKLIGHT BIT(3)
+#define LCD_NO_BACKLIGHT 0x00
 
-#define LCD_EN	BIT(2) /* Enable bit */
-#define LCD_RW	BIT(1) /* Read/Write bit */
-#define LCD_RS	BIT(0) /* Register select bit */
+#define LCD_EN BIT(2) /* Enable bit */
+#define LCD_RW BIT(1) /* Read/Write bit */
+#define LCD_RS BIT(0) /* Register select bit */
 
 void lcd_init(uint8_t cols, uint8_t rows, uint8_t dotsize);
 void lcd_set_cursor(uint8_t col, uint8_t row);
diff --git a/board/gaelin/board.c b/board/gaelin/board.c
new file mode 100644
index 0000000000..3409aa750f
--- /dev/null
+++ b/board/gaelin/board.c
@@ -0,0 +1,591 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include <stdbool.h>
+
+#include "adc.h"
+#include "assert.h"
+#include "button.h"
+#include "charge_manager.h"
+#include "charge_state_v2.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "power_button.h"
+#include "hooks.h"
+#include "peripheral_charger.h"
+#include "power.h"
+#include "switch.h"
+#include "throttle_ap.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+#include "driver/tcpm/tcpci.h"
+#include "fw_config.h"
+
+/* Console output macros */
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+
+static void power_monitor(void);
+DECLARE_DEFERRED(power_monitor);
+
+/******************************************************************************/
+/* USB-A charging control */
+
+const int usb_port_enable[USB_PORT_COUNT] = {
+	GPIO_EN_PP5000_USBA,
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
+
+extern struct pchg_drv cps8100_drv;
+struct pchg pchgs[] = {
+	[0] = {
+		.cfg = &(const struct pchg_config) {
+			.drv = &cps8100_drv,
+			.i2c_port = I2C_PORT_QI,
+			.irq_pin = GPIO_QI_INT_ODL,
+			.full_percent = 96,
+			.block_size = 128,
+		},
+		.events = QUEUE_NULL(PCHG_EVENT_QUEUE_SIZE, enum pchg_event),
+	},
+};
+const int pchg_count = ARRAY_SIZE(pchgs);
+
+__override void board_pchg_power_on(int port, bool on)
+{
+	if (port == 0)
+		gpio_set_level(GPIO_EC_QI_PWR, on);
+	else
+		CPRINTS("%s: Invalid port=%d", __func__, port);
+}
+
+/******************************************************************************/
+
+int board_set_active_charge_port(int port)
+{
+	CPRINTS("Requested charge port change to %d", port);
+
+	/*
+	 * The charge manager may ask us to switch to no charger if we're
+	 * running off USB-C only but upstream doesn't support PD. It requires
+	 * that we accept this switch otherwise it triggers an assert and EC
+	 * reset; it's not possible to boot the AP anyway, but we want to avoid
+	 * resetting the EC so we can continue to do the "low power" LED blink.
+	 */
+	if (port == CHARGE_PORT_NONE)
+		return EC_SUCCESS;
+
+	if (port < 0 || CHARGE_PORT_COUNT <= port)
+		return EC_ERROR_INVAL;
+
+	if (port == charge_manager_get_active_charge_port())
+		return EC_SUCCESS;
+
+	/* Don't charge from a source port */
+	if (board_vbus_source_enabled(port))
+		return EC_ERROR_INVAL;
+
+	if (!chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
+		int bj_active, bj_requested;
+
+		if (charge_manager_get_active_charge_port() != CHARGE_PORT_NONE)
+			/* Change is only permitted while the system is off */
+			return EC_ERROR_INVAL;
+
+		/*
+		 * Current setting is no charge port but the AP is on, so the
+		 * charge manager is out of sync (probably because we're
+		 * reinitializing after sysjump). Reject requests that aren't
+		 * in sync with our outputs.
+		 */
+		bj_active = !gpio_get_level(GPIO_EN_PPVAR_BJ_ADP_L);
+		bj_requested = port == CHARGE_PORT_BARRELJACK;
+		if (bj_active != bj_requested)
+			return EC_ERROR_INVAL;
+	}
+
+	CPRINTS("New charger p%d", port);
+
+	switch (port) {
+	case CHARGE_PORT_TYPEC0:
+	case CHARGE_PORT_TYPEC1:
+	case CHARGE_PORT_TYPEC2:
+		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 1);
+		break;
+	case CHARGE_PORT_BARRELJACK:
+		/* Make sure BJ adapter is sourcing power */
+		if (gpio_get_level(GPIO_BJ_ADP_PRESENT_ODL))
+			return EC_ERROR_INVAL;
+		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 0);
+		break;
+	default:
+		return EC_ERROR_INVAL;
+	}
+
+	return EC_SUCCESS;
+}
+
+static uint8_t usbc_overcurrent;
+static int32_t base_5v_power_s5;
+static int32_t base_5v_power_z1;
+
+/*
+ * Power usage for each port as measured or estimated.
+ * Units are milliwatts (5v x ma current)
+ */
+
+/* PP5000_S5 loads */
+#define PWR_S5_BASE_LOAD (5 * 1431)
+#define PWR_S5_FRONT_HIGH (5 * 1737)
+#define PWR_S5_FRONT_LOW (5 * 1055)
+#define PWR_S5_REAR_HIGH (5 * 1737)
+#define PWR_S5_REAR_LOW (5 * 1055)
+#define PWR_S5_HDMI (5 * 580)
+#define PWR_S5_MAX (5 * 10000)
+#define FRONT_DELTA (PWR_S5_FRONT_HIGH - PWR_S5_FRONT_LOW)
+#define REAR_DELTA (PWR_S5_REAR_HIGH - PWR_S5_REAR_LOW)
+
+/* PP5000_Z1 loads */
+#define PWR_Z1_BASE_LOAD (5 * 5)
+#define PWR_Z1_C_HIGH (5 * 3600)
+#define PWR_Z1_C_LOW (5 * 2000)
+#define PWR_Z1_MAX (5 * 9000)
+/*
+ * Update the 5V power usage, assuming no throttling,
+ * and invoke the power monitoring.
+ */
+static void update_5v_usage(void)
+{
+	int front_ports = 0;
+	int rear_ports = 0;
+
+	/*
+	 * Recalculate the 5V load, assuming no throttling.
+	 */
+	base_5v_power_s5 = PWR_S5_BASE_LOAD;
+	if (!gpio_get_level(GPIO_USB_A0_OC_ODL)) {
+		front_ports++;
+		base_5v_power_s5 += PWR_S5_FRONT_LOW;
+	}
+	if (!gpio_get_level(GPIO_USB_A1_OC_ODL)) {
+		front_ports++;
+		base_5v_power_s5 += PWR_S5_FRONT_LOW;
+	}
+	/*
+	 * Only 1 front port can run higher power at a time.
+	 */
+	if (front_ports > 0)
+		base_5v_power_s5 += PWR_S5_FRONT_HIGH - PWR_S5_FRONT_LOW;
+
+	if (!gpio_get_level(GPIO_USB_A2_OC_ODL)) {
+		rear_ports++;
+		base_5v_power_s5 += PWR_S5_REAR_LOW;
+	}
+	if (!gpio_get_level(GPIO_USB_A3_OC_ODL)) {
+		rear_ports++;
+		base_5v_power_s5 += PWR_S5_REAR_LOW;
+	}
+	/*
+	 * Only 1 rear port can run higher power at a time.
+	 */
+	if (rear_ports > 0)
+		base_5v_power_s5 += PWR_S5_REAR_HIGH - PWR_S5_REAR_LOW;
+	if (!gpio_get_level(GPIO_HDMI_CONN_OC_ODL))
+		base_5v_power_s5 += PWR_S5_HDMI;
+	base_5v_power_z1 = PWR_Z1_BASE_LOAD;
+	if (usbc_overcurrent)
+		base_5v_power_z1 += PWR_Z1_C_HIGH;
+	/*
+	 * Invoke the power handler immediately.
+	 */
+	hook_call_deferred(&power_monitor_data, 0);
+}
+DECLARE_DEFERRED(update_5v_usage);
+/*
+ * Start power monitoring after ADCs have been initialised.
+ */
+DECLARE_HOOK(HOOK_INIT, update_5v_usage, HOOK_PRIO_INIT_ADC + 1);
+
+static void port_ocp_interrupt(enum gpio_signal signal)
+{
+	hook_call_deferred(&update_5v_usage_data, 0);
+}
+#include "gpio_list.h" /* Must come after other header files. */
+
+/******************************************************************************/
+/*
+ * Barrel jack power supply handling
+ *
+ * EN_PPVAR_BJ_ADP_L must default active to ensure we can power on when the
+ * barrel jack is connected, and the USB-C port can bring the EC up fine in
+ * dead-battery mode. Both the USB-C and barrel jack switches do reverse
+ * protection, so we're safe to turn one on then the other off- but we should
+ * only do that if the system is off since it might still brown out.
+ */
+
+#define ADP_DEBOUNCE_MS 1000 /* Debounce time for BJ plug/unplug */
+/* Debounced connection state of the barrel jack */
+static int8_t adp_connected = -1;
+static void adp_connect_deferred(void)
+{
+	struct charge_port_info pi = { 0 };
+	int connected = !gpio_get_level(GPIO_BJ_ADP_PRESENT_ODL);
+
+	/* Debounce */
+	if (connected == adp_connected)
+		return;
+	if (connected)
+		ec_bj_power(&pi.voltage, &pi.current);
+	charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED,
+				     DEDICATED_CHARGE_PORT, &pi);
+	adp_connected = connected;
+}
+DECLARE_DEFERRED(adp_connect_deferred);
+
+/* IRQ for BJ plug/unplug. It shouldn't be called if BJ is the power source. */
+void adp_connect_interrupt(enum gpio_signal signal)
+{
+	hook_call_deferred(&adp_connect_deferred_data, ADP_DEBOUNCE_MS * MSEC);
+}
+
+static void adp_state_init(void)
+{
+	ASSERT(CHARGE_PORT_ENUM_COUNT == CHARGE_PORT_COUNT);
+	/*
+	 * Initialize all charge suppliers to 0. The charge manager waits until
+	 * all ports have reported in before doing anything.
+	 */
+	for (int i = 0; i < CHARGE_PORT_COUNT; i++) {
+		for (int j = 0; j < CHARGE_SUPPLIER_COUNT; j++)
+			charge_manager_update_charge(j, i, NULL);
+	}
+
+	/* Report charge state from the barrel jack. */
+	adp_connect_deferred();
+}
+DECLARE_HOOK(HOOK_INIT, adp_state_init, HOOK_PRIO_INIT_CHARGE_MANAGER + 1);
+
+static void board_init(void)
+{
+	gpio_enable_interrupt(GPIO_BJ_ADP_PRESENT_ODL);
+	gpio_enable_interrupt(GPIO_HDMI_CONN_OC_ODL);
+	gpio_enable_interrupt(GPIO_USB_A0_OC_ODL);
+	gpio_enable_interrupt(GPIO_USB_A1_OC_ODL);
+	gpio_enable_interrupt(GPIO_USB_A2_OC_ODL);
+	gpio_enable_interrupt(GPIO_USB_A3_OC_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+void board_overcurrent_event(int port, int is_overcurrented)
+{
+	/* Check that port number is valid. */
+	if ((port < 0) || (port >= CONFIG_USB_PD_PORT_MAX_COUNT))
+		return;
+	usbc_overcurrent = is_overcurrented;
+	update_5v_usage();
+}
+/*
+ * Power monitoring and management.
+ *
+ * the power budgets are met without letting the system fall into
+ * power deficit (perhaps causing a brownout).
+ *
+ * There are 2 power budgets that need to be managed:
+ * The overall goal is to gracefully manage the power demand so that
+ *  - overall system power as measured on the main power supply rail.
+ *  - 5V power delivered to the USB and HDMI ports.
+ *
+ * The actual system power demand is calculated from the VBUS voltage and
+ * the input current (read from a shunt), averaged over 5 readings.
+ * The power budget limit is from the charge manager.
+ *
+ * The 5V power cannot be read directly. Instead, we rely on overcurrent
+ * inputs from the USB and HDMI ports to indicate that the port is in use
+ * (and drawing maximum power).
+ *
+ * There are 3 throttles that can be applied (in priority order):
+ *
+ *  - Type A BC1.2 front port restriction (3W)
+ *  - Type A BC1.2 rear port restriction (3W)
+ *  - Type C PD (throttle to 1.5A if sourcing)
+ *  - Turn on PROCHOT, which immediately throttles the CPU.
+ *
+ *  The first 3 throttles affect both the system power and the 5V rails.
+ *  The third is a last resort to force an immediate CPU throttle to
+ *  reduce the overall power use.
+ *
+ *  The strategy is to determine what the state of the throttles should be,
+ *  and to then turn throttles off or on as needed to match this.
+ *
+ *  This function runs on demand, or every 2 ms when the CPU is up,
+ *  and continually monitors the power usage, applying the
+ *  throttles when necessary.
+ *
+ *  All measurements are in milliwatts.
+ */
+#define THROT_TYPE_A_FRONT BIT(0)
+#define THROT_TYPE_A_REAR BIT(1)
+#define THROT_TYPE_C0 BIT(2)
+#define THROT_TYPE_C1 BIT(3)
+#define THROT_TYPE_C2 BIT(4)
+#define THROT_PROCHOT BIT(5)
+
+/*
+ * Power gain if front USB A ports are limited.
+ */
+#define POWER_GAIN_TYPE_A 3200
+/*
+ * Power gain if Type C port is limited.
+ */
+#define POWER_GAIN_TYPE_C 8800
+/*
+ * Power is averaged over 10 ms, with a reading every 2 ms.
+ */
+#define POWER_DELAY_MS 2
+#define POWER_READINGS (10 / POWER_DELAY_MS)
+
+static void power_monitor(void)
+{
+	static uint32_t current_state;
+	static uint32_t history[POWER_READINGS];
+	static uint8_t index;
+	int32_t delay;
+	uint32_t new_state = 0, diff;
+	int32_t headroom_5v_s5 = PWR_S5_MAX - base_5v_power_s5;
+	int32_t headroom_5v_z1 = PWR_Z1_MAX - base_5v_power_z1;
+
+	/*
+	 * If CPU is off or suspended, no need to throttle
+	 * or restrict power.
+	 */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF | CHIPSET_STATE_SUSPEND)) {
+		/*
+		 * Slow down monitoring, assume no throttling required.
+		 */
+		delay = 20 * MSEC;
+		/*
+		 * Clear the first entry of the power table so that
+		 * it is re-initilalised when the CPU starts.
+		 */
+		history[0] = 0;
+	} else {
+		int32_t charger_mw;
+
+		delay = POWER_DELAY_MS * MSEC;
+		/*
+		 * Get current charger limit (in mw).
+		 * If not configured yet, skip.
+		 */
+		charger_mw = charge_manager_get_power_limit_uw() / 1000;
+		if (charger_mw != 0) {
+			int32_t gap, total, max, power;
+			int i;
+
+			/*
+			 * Read power usage.
+			 */
+			power = (adc_read_channel(ADC_VBUS) *
+				 adc_read_channel(ADC_PPVAR_IMON)) /
+				1000;
+			/* Init power table */
+			if (history[0] == 0) {
+				for (i = 0; i < POWER_READINGS; i++)
+					history[i] = power;
+			}
+			/*
+			 * Update the power readings and
+			 * calculate the average and max.
+			 */
+			history[index] = power;
+			index = (index + 1) % POWER_READINGS;
+			total = 0;
+			max = history[0];
+			for (i = 0; i < POWER_READINGS; i++) {
+				total += history[i];
+				if (history[i] > max)
+					max = history[i];
+			}
+			/*
+			 * For Type-C power supplies, there is
+			 * less tolerance for exceeding the rating,
+			 * so use the max power that has been measured
+			 * over the measuring period.
+			 * For barrel-jack supplies, the rating can be
+			 * exceeded briefly, so use the average.
+			 */
+			if (charge_manager_get_supplier() == CHARGE_SUPPLIER_PD)
+				power = max;
+			else
+				power = total / POWER_READINGS;
+			/*
+			 * Calculate gap, and if negative, power
+			 * demand is exceeding configured power budget, so
+			 * throttling is required to reduce the demand.
+			 */
+			gap = charger_mw - power;
+			/*
+			 * Limiting type-A power rear ports.
+			 */
+			if (gap <= 0) {
+				new_state |= THROT_TYPE_A_REAR;
+				headroom_5v_s5 += REAR_DELTA;
+				if (!(current_state & THROT_TYPE_A_REAR))
+					gap += POWER_GAIN_TYPE_A;
+			}
+			/*
+			 * Limiting type-A power front ports.
+			 */
+			if (gap <= 0) {
+				new_state |= THROT_TYPE_A_FRONT;
+				headroom_5v_s5 += FRONT_DELTA;
+				if (!(current_state & THROT_TYPE_A_REAR))
+					gap += POWER_GAIN_TYPE_A;
+			}
+			/*
+			 * If the type-C port is sourcing power,
+			 * check whether it should be throttled.
+			 */
+			if (ppc_is_sourcing_vbus(0) && gap <= 0) {
+				new_state |= THROT_TYPE_C0;
+				headroom_5v_z1 += PWR_Z1_C_HIGH - PWR_Z1_C_LOW;
+				if (!(current_state & THROT_TYPE_C0))
+					gap += POWER_GAIN_TYPE_C;
+			}
+			/*
+			 * If the type-C port is sourcing power,
+			 * check whether it should be throttled.
+			 */
+			if (ppc_is_sourcing_vbus(1) && gap <= 0) {
+				new_state |= THROT_TYPE_C1;
+				headroom_5v_z1 += PWR_Z1_C_HIGH - PWR_Z1_C_LOW;
+				if (!(current_state & THROT_TYPE_C1))
+					gap += POWER_GAIN_TYPE_C;
+			}
+			/*
+			 * If the type-C port is sourcing power,
+			 * check whether it should be throttled.
+			 */
+			if (ppc_is_sourcing_vbus(2) && gap <= 0) {
+				new_state |= THROT_TYPE_C2;
+				headroom_5v_z1 += PWR_Z1_C_HIGH - PWR_Z1_C_LOW;
+				if (!(current_state & THROT_TYPE_C2))
+					gap += POWER_GAIN_TYPE_C;
+			}
+			/*
+			 * As a last resort, turn on PROCHOT to
+			 * throttle the CPU.
+			 */
+			if (gap <= 0)
+				new_state |= THROT_PROCHOT;
+		}
+	}
+	/*
+	 * Check the 5v power usage and if necessary,
+	 * adjust the throttles in priority order.
+	 *
+	 * Either throttle may have already been activated by
+	 * the overall power control.
+	 *
+	 * We rely on the overcurrent detection to inform us
+	 * if the port is in use.
+	 *
+	 *  - If type C not already throttled:
+	 *	* If not overcurrent, prefer to limit type C [1].
+	 *	* If in overcurrentuse:
+	 *		- limit type A first [2]
+	 *		- If necessary, limit type C [3].
+	 *  - If type A not throttled, if necessary limit it [2].
+	 */
+	if (headroom_5v_z1 < 0) {
+		/*
+		 * Check whether type C is not throttled,
+		 * and is not overcurrent.
+		 */
+		if (!((new_state & THROT_TYPE_C0) || usbc_overcurrent)) {
+			/*
+			 * [1] Type C not in overcurrent, throttle it.
+			 */
+			headroom_5v_z1 += PWR_Z1_C_HIGH - PWR_Z1_C_LOW;
+			new_state |= THROT_TYPE_C0;
+		}
+		/*
+		 * [2] If still under-budget, limit type C.
+		 * No need to check if it is already throttled or not.
+		 */
+		if (headroom_5v_z1 < 0)
+			new_state |= THROT_TYPE_C0;
+	}
+	if (headroom_5v_s5 < 0) {
+		/*
+		 * [1] If type A rear not already throttled, and power still
+		 * needed, limit type A rear.
+		 */
+		if (!(new_state & THROT_TYPE_A_REAR) && headroom_5v_s5 < 0) {
+			headroom_5v_s5 += PWR_S5_REAR_HIGH - PWR_S5_REAR_LOW;
+			new_state |= THROT_TYPE_A_REAR;
+		}
+		/*
+		 * [2] If type A front not already throttled, and power still
+		 * needed, limit type A front.
+		 */
+		if (!(new_state & THROT_TYPE_A_FRONT) && headroom_5v_s5 < 0) {
+			headroom_5v_s5 += PWR_S5_FRONT_HIGH - PWR_S5_FRONT_LOW;
+			new_state |= THROT_TYPE_A_FRONT;
+		}
+	}
+	/*
+	 * Turn the throttles on or off if they have changed.
+	 */
+	diff = new_state ^ current_state;
+	current_state = new_state;
+	if (diff & THROT_PROCHOT) {
+		int prochot = (new_state & THROT_PROCHOT) ? 0 : 1;
+
+		gpio_set_level(GPIO_EC_PROCHOT_ODL, prochot);
+	}
+	if (diff & THROT_TYPE_C0) {
+		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C0) ?
+						TYPEC_RP_1A5 :
+						TYPEC_RP_3A0;
+
+		ppc_set_vbus_source_current_limit(0, rp);
+		tcpm_select_rp_value(0, rp);
+		pd_update_contract(0);
+	}
+	if (diff & THROT_TYPE_C1) {
+		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C1) ?
+						TYPEC_RP_1A5 :
+						TYPEC_RP_3A0;
+
+		ppc_set_vbus_source_current_limit(1, rp);
+		tcpm_select_rp_value(1, rp);
+		pd_update_contract(1);
+	}
+	if (diff & THROT_TYPE_C2) {
+		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C2) ?
+						TYPEC_RP_1A5 :
+						TYPEC_RP_3A0;
+
+		ppc_set_vbus_source_current_limit(2, rp);
+		tcpm_select_rp_value(2, rp);
+		pd_update_contract(2);
+	}
+	if (diff & THROT_TYPE_A_REAR) {
+		int typea_bc = (new_state & THROT_TYPE_A_REAR) ? 1 : 0;
+
+		gpio_set_level(GPIO_USB_A_LOW_PWR0_OD, typea_bc);
+		gpio_set_level(GPIO_USB_A_LOW_PWR1_OD, typea_bc);
+	}
+	if (diff & THROT_TYPE_A_FRONT) {
+		int typea_bc = (new_state & THROT_TYPE_A_FRONT) ? 1 : 0;
+
+		gpio_set_level(GPIO_USB_A_LOW_PWR2_OD, typea_bc);
+		gpio_set_level(GPIO_USB_A_LOW_PWR3_OD, typea_bc);
+	}
+	hook_call_deferred(&power_monitor_data, delay);
+}
diff --git a/board/gaelin/board.h b/board/gaelin/board.h
new file mode 100644
index 0000000000..f113c6cffd
--- /dev/null
+++ b/board/gaelin/board.h
@@ -0,0 +1,203 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Brask board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "compile_time_macros.h"
+
+/* Baseboard features */
+#include "baseboard.h"
+
+#define CONFIG_MP2964
+
+/* Barrel Jack */
+#define DEDICATED_CHARGE_PORT 3
+
+/* HDMI CEC */
+#define CONFIG_CEC
+#define CEC_GPIO_OUT GPIO_HDMI_CEC_OUT
+#define CEC_GPIO_IN GPIO_HDMI_CEC_IN
+#define CEC_GPIO_PULL_UP GPIO_HDMI_CEC_PULL_UP
+
+/* USB Type A Features */
+#define USB_PORT_COUNT 4
+#define CONFIG_USB_PORT_POWER_DUMB
+
+/* USB Type C and USB PD defines */
+#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
+
+#define CONFIG_IO_EXPANDER
+#define CONFIG_IO_EXPANDER_NCT38XX
+#define CONFIG_IO_EXPANDER_PORT_COUNT 2
+
+#define CONFIG_USB_PD_PPC
+#define CONFIG_USB_PD_TCPM_RT1715
+#define CONFIG_USBC_RETIMER_INTEL_BB
+
+#define CONFIG_USBC_RETIMER_KB800X
+#define CONFIG_KB800X_CUSTOM_XBAR
+#define CONFIG_USBC_PPC_SYV682X
+#undef CONFIG_SYV682X_HV_ILIM
+#define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_5_50
+
+/* TODO: b/177608416 - measure and check these values on brya */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
+
+/* The design should support up to 100W. */
+/* TODO(b/197702356): Set the max PD to 60W now and change it
+ * to 100W after we verify it.
+ */
+#define PD_OPERATING_POWER_MW CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
+#define PD_MAX_POWER_MW 100000
+#define PD_MAX_CURRENT_MA 5000
+#define PD_MAX_VOLTAGE_MV 20000
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
+
+/*
+ * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
+ * signal.
+ */
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
+#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_OD
+#define GPIO_RECOVERY_L_2 GPIO_GSC_EC_RECOVERY_BTN_OD
+
+/* I2C Bus Configuration */
+
+#define I2C_PORT_DP_REDRIVER NPCX_I2C_PORT0_0
+
+#define I2C_PORT_USB_C0_C2_TCPC NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1
+
+#define I2C_PORT_USB_C0_C2_PPC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1
+
+#define I2C_PORT_USB_C0_C2_BC12 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1
+
+#define I2C_PORT_USB_C0_C2_MUX NPCX_I2C_PORT3_0
+#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1
+
+#define I2C_PORT_QI NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+
+#define I2C_ADDR_MP2964_FLAGS 0x20
+
+#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x58
+#define USBC_PORT_C2_BB_RETIMER_I2C_ADDR 0x59
+
+/* Enabling Thunderbolt-compatible mode */
+#define CONFIG_USB_PD_TBT_COMPAT_MODE
+
+/* Enabling USB4 mode */
+#define CONFIG_USB_PD_USB4
+
+/* Retimer */
+#define CONFIG_USBC_RETIMER_FW_UPDATE
+
+/* Thermal features */
+#define CONFIG_THERMISTOR
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_TEMP_SENSOR_POWER
+#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
+
+/* ADC */
+#define CONFIG_ADC
+
+/*
+ * TODO(b/197478860): Enable the fan control. We need
+ * to check the sensor value and adjust the fan speed.
+ */
+#define CONFIG_FANS FAN_CH_COUNT
+
+/* Include math_util for bitmask_uint64 used in pd_timers */
+#define CONFIG_MATH_UTIL
+
+/* WPC/Qi charger */
+#ifdef SECTION_IS_RW
+#define CONFIG_PERIPHERAL_CHARGER
+#define CONFIG_CPS8100
+#endif
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h" /* needed by registers.h */
+#include "registers.h"
+#include "usbc_config.h"
+
+enum charge_port {
+	CHARGE_PORT_TYPEC0,
+	CHARGE_PORT_TYPEC1,
+	CHARGE_PORT_TYPEC2,
+	CHARGE_PORT_BARRELJACK,
+	CHARGE_PORT_ENUM_COUNT
+};
+
+enum adc_channel {
+	ADC_TEMP_SENSOR_1_CPU,
+	ADC_TEMP_SENSOR_2_CPU_VR,
+	ADC_TEMP_SENSOR_3_WIFI,
+	ADC_TEMP_SENSOR_4_DIMM,
+	ADC_VBUS,
+	ADC_PPVAR_IMON, /* ADC3 */
+	ADC_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_1_CPU,
+	TEMP_SENSOR_2_CPU_VR,
+	TEMP_SENSOR_3_WIFI,
+	TEMP_SENSOR_4_DIMM,
+	TEMP_SENSOR_COUNT
+};
+
+enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_C2_NCT38XX, IOEX_PORT_COUNT };
+
+enum pwm_channel {
+	PWM_CH_LED_GREEN, /* PWM0 */
+	PWM_CH_FAN, /* PWM5 */
+	PWM_CH_LED_RED, /* PWM2 */
+	PWM_CH_COUNT
+};
+
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT };
+
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT };
+
+extern void adp_connect_interrupt(enum gpio_signal signal);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/ghost/build.mk b/board/gaelin/build.mk
index 4efdd19249..3de758d1bd 100644
--- a/board/ghost/build.mk
+++ b/board/gaelin/build.mk
@@ -1,24 +1,21 @@
 # -*- makefile -*-
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
-# Ghost board specific files build
+# Brask board specific files build
 #
 
 CHIP:=npcx
 CHIP_FAMILY:=npcx9
 CHIP_VARIANT:=npcx9m3f
-BASEBOARD:=brya
+BASEBOARD:=brask
 
 board-y=
-board-y+=battery.o
 board-y+=board.o
-board-y+=charger.o
 board-y+=fans.o
 board-y+=fw_config.o
 board-y+=i2c.o
-board-y+=keyboard.o
 board-y+=led.o
 board-y+=pwm.o
 board-y+=sensors.o
diff --git a/board/gaelin/ec.tasklist b/board/gaelin/ec.tasklist
new file mode 100644
index 0000000000..d16fc35f52
--- /dev/null
+++ b/board/gaelin/ec.tasklist
@@ -0,0 +1,29 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ *
+ * USB_CHG_Px tasks must be contiguous (see USB_CHG_PORT_TO_TASK_ID(x)).
+ * PD_Cx tasks must be contiguous (see PD_PORT_TO_TASK_ID(x))
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS_RW(PCHG, pchg_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P2, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C2, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_shared_alert_task, (BIT(2) | BIT(0)), LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CEC, cec_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/gaelin/fans.c b/board/gaelin/fans.c
new file mode 100644
index 0000000000..6828438a10
--- /dev/null
+++ b/board/gaelin/fans.c
@@ -0,0 +1,50 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Physical fans. These are logically separate from pwm_channels. */
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "fan_chip.h"
+#include "fan.h"
+#include "hooks.h"
+#include "pwm.h"
+
+/* MFT channels. These are logically separate from pwm_channels. */
+const struct mft_t mft_channels[] = {
+	[MFT_CH_0] = {
+		.module = NPCX_MFT_MODULE_2,
+		.clk_src = TCKC_LFCLK,
+		.pwm_id = PWM_CH_FAN,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
+
+static const struct fan_conf fan_conf_0 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
+	.pgood_gpio = -1,
+	.enable_gpio = GPIO_EN_PP5000_FAN,
+};
+
+/*
+ * TOOD(b/197478860): need to update for real fan
+ *
+ * Prototype fan spins at about 7200 RPM at 100% PWM.
+ * Set minimum at around 30% PWM.
+ */
+static const struct fan_rpm fan_rpm_0 = {
+	.rpm_min = 2200,
+	.rpm_start = 2200,
+	.rpm_max = 7200,
+};
+
+const struct fan_t fans[FAN_CH_COUNT] = {
+	[FAN_CH_0] = {
+		.conf = &fan_conf_0,
+		.rpm = &fan_rpm_0,
+	},
+};
diff --git a/board/gaelin/fw_config.c b/board/gaelin/fw_config.c
new file mode 100644
index 0000000000..3ee71e6a0f
--- /dev/null
+++ b/board/gaelin/fw_config.c
@@ -0,0 +1,65 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "cbi.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "fw_config.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+static union brask_cbi_fw_config fw_config;
+BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
+
+/*
+ * FW_CONFIG defaults for brask if the CBI.FW_CONFIG data is not
+ * initialized.
+ */
+static const union brask_cbi_fw_config fw_config_defaults = {
+	.audio = DB_NAU88L25B_I2S,
+	.bj_power = BJ_135W,
+};
+
+/*
+ * Barrel-jack power adapter ratings.
+ */
+static const struct {
+	int voltage;
+	int current;
+} bj_power[] = {
+	[BJ_135W] = { /* 0 - 135W (also default) */
+			.voltage = 19500,
+			.current = 6920
+	},
+	[BJ_230W] = { /* 1 - 230W */
+			.voltage = 19500,
+			.current = 11800
+	}
+};
+
+/****************************************************************************
+ * Brask FW_CONFIG access
+ */
+void board_init_fw_config(void)
+{
+	if (cbi_get_fw_config(&fw_config.raw_value)) {
+		CPRINTS("CBI: Read FW_CONFIG failed, using board defaults");
+		fw_config = fw_config_defaults;
+	}
+}
+
+void ec_bj_power(uint32_t *voltage, uint32_t *current)
+{
+	unsigned int bj;
+
+	bj = fw_config.bj_power;
+	/* Out of range value defaults to 0 */
+	if (bj >= ARRAY_SIZE(bj_power))
+		bj = 0;
+	*voltage = bj_power[bj].voltage;
+	*current = bj_power[bj].current;
+}
diff --git a/board/gaelin/fw_config.h b/board/gaelin/fw_config.h
new file mode 100644
index 0000000000..95d81f1e05
--- /dev/null
+++ b/board/gaelin/fw_config.h
@@ -0,0 +1,41 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __BOARD_BRASK_FW_CONFIG_H_
+#define __BOARD_BRASK_FW_CONFIG_H_
+
+#include <stdint.h>
+
+/****************************************************************************
+ * CBI FW_CONFIG layout for Brask board.
+ *
+ * Source of truth is the project/brask/brask/config.star configuration file.
+ */
+enum ec_cfg_audio_type { DB_AUDIO_UNKNOWN = 0, DB_NAU88L25B_I2S = 1 };
+
+enum ec_cfg_bj_power { BJ_135W = 0, BJ_230W = 1 };
+
+union brask_cbi_fw_config {
+	struct {
+		uint32_t audio : 3;
+		uint32_t bj_power : 2;
+		uint32_t reserved_1 : 27;
+	};
+	uint32_t raw_value;
+};
+
+/**
+ * Read the cached FW_CONFIG.  Guaranteed to have valid values.
+ *
+ * @return the FW_CONFIG for the board.
+ */
+union brask_cbi_fw_config get_fw_config(void);
+
+/**
+ * Get the barrel-jack power from FW_CONFIG.
+ */
+void ec_bj_power(uint32_t *voltage, uint32_t *current);
+
+#endif /* __BOARD_BRASK_FW_CONFIG_H_ */
diff --git a/board/gaelin/gpio.inc b/board/gaelin/gpio.inc
new file mode 100644
index 0000000000..51cf0010c6
--- /dev/null
+++ b/board/gaelin/gpio.inc
@@ -0,0 +1,187 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* INTERRUPT GPIOs: */
+
+GPIO_INT(ACOK_OD,                    PIN(0, 0), GPIO_INT_BOTH, extpower_interrupt)
+GPIO_INT(EC_PROCHOT_IN_L,            PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
+GPIO_INT(EC_WP_ODL,                  PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
+GPIO_INT(GSC_EC_PWR_BTN_ODL,         PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)
+GPIO_INT(SEQ_EC_ALL_SYS_PG,          PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_DSW_PWROK,           PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SEQ_EC_RSMRST_ODL,          PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_S3_L,                   PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,                  PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SYS_SLP_S0IX_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(USB_C0_BC12_INT_ODL,        PIN(C, 6), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C0_C2_TCPC_INT_ODL,     PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C0_PPC_INT_ODL,         PIN(6, 2), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C0_RT_INT_ODL,          PIN(B, 1), GPIO_INT_FALLING, retimer_interrupt)
+GPIO_INT(USB_C1_BC12_INT_ODL,        PIN(5, 0), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C1_PPC_INT_ODL,         PIN(F, 5), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C1_TCPC_INT_ODL,        PIN(A, 2), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(USB_C2_BC12_INT_ODL,        PIN(8, 3), GPIO_INT_FALLING, bc12_interrupt)
+GPIO_INT(USB_C2_PPC_INT_ODL,         PIN(7, 0), GPIO_INT_FALLING, ppc_interrupt)
+GPIO_INT(USB_C2_RT_INT_ODL,          PIN(4, 1), GPIO_INT_FALLING, retimer_interrupt)
+GPIO_INT(BJ_ADP_PRESENT_ODL,         PIN(8, 2), GPIO_INT_BOTH | GPIO_PULL_UP, adp_connect_interrupt)
+GPIO_INT(EC_RECOVERY_BTN_OD,         PIN(2, 3), GPIO_INT_BOTH, button_interrupt)
+GPIO_INT(HDMI_CONN_OC_ODL,           PIN(2, 4), GPIO_INPUT | GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(USB_A0_OC_ODL,              PIN(3, 1), GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(USB_A1_OC_ODL,              PIN(3, 0), GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(USB_A2_OC_ODL,              PIN(2, 7), GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH, port_ocp_interrupt)
+GPIO_INT(USB_A3_OC_ODL,              PIN(2, 6), GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH, port_ocp_interrupt)
+#ifdef SECTION_IS_RW
+GPIO_INT(QI_INT_ODL,                 PIN(9, 6), GPIO_INT_FALLING, pchg_irq)
+#else
+UNIMPLEMENTED(QI_INT_ODL)
+#endif
+
+/* CCD */
+GPIO(CCD_MODE_ODL,                   PIN(E, 5), GPIO_INPUT)
+
+/* Security */
+GPIO(EC_ENTERING_RW,                 PIN(0, 3), GPIO_OUT_LOW)
+GPIO(EC_GSC_PACKET_MODE,             PIN(7, 5), GPIO_OUT_LOW)
+
+/* Fan */
+GPIO(EN_PP5000_FAN,                  PIN(6, 1), GPIO_OUT_HIGH)
+
+/* ADC, need to check the usage */
+GPIO(ANALOG_PPVAR_PWR_IN_IMON_EC,    PIN(4, 2), GPIO_INPUT)
+
+/* Display */
+GPIO(DP_CONN_OC_ODL,                 PIN(2, 5), GPIO_INPUT)
+
+
+/* BarrelJack */
+GPIO(EN_PPVAR_BJ_ADP_L,              PIN(0, 7), GPIO_OUT_LOW)
+
+/* Chipset PCH */
+GPIO(EC_PCHHOT_ODL,                  PIN(7, 4), GPIO_INPUT)
+GPIO(EC_PCH_INT_ODL,                 PIN(B, 0), GPIO_ODR_HIGH)
+GPIO(EC_PCH_RSMRST_L,                PIN(A, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_RTCRST,                  PIN(7, 6), GPIO_OUT_LOW)
+GPIO(EC_PCH_SYS_PWROK,               PIN(3, 7), GPIO_OUT_LOW)
+GPIO(EC_PCH_WAKE_ODL,                PIN(C, 0), GPIO_ODR_HIGH)
+GPIO(EC_PROCHOT_ODL,                 PIN(6, 3), GPIO_ODR_HIGH)
+GPIO(EN_S5_RAILS,                    PIN(B, 6), GPIO_OUT_LOW)
+GPIO(PCH_PWROK,                      PIN(7, 2), GPIO_OUT_LOW)
+GPIO(SYS_RST_ODL,                    PIN(C, 5), GPIO_ODR_HIGH)
+GPIO(VCCST_PWRGD_OD,                 PIN(A, 4), GPIO_ODR_LOW)
+GPIO(IMVP9_VRRDY_OD,                 PIN(6, 0), GPIO_INPUT)
+GPIO(CPU_C10_GATE_L,                 PIN(6, 7), GPIO_INPUT)
+
+/* Button */
+GPIO(EC_PCH_PWR_BTN_ODL,             PIN(C, 1), GPIO_ODR_HIGH)
+GPIO(GSC_EC_RECOVERY_BTN_OD,         PIN(2, 2), GPIO_INPUT)
+
+/* NFC */
+/* TODO(b/194068530): Enable NFC */
+GPIO(NFC_COIL_ACT_L,                 PIN(D, 4), GPIO_INPUT)
+GPIO(NFC_LOW_POWER_MODE,             PIN(9, 5), GPIO_OUT_HIGH)
+GPIO(NFC_CARD_DET_L,                 PIN(A, 3), GPIO_INPUT)
+GPIO(EN_NFC_BUZZER,                  PIN(0, 5), GPIO_OUT_LOW)
+
+/* Wireless Charger */
+GPIO(EC_QI_PWR,                      PIN(D, 2), GPIO_OUT_LOW)
+GPIO(QI_RESET_L,                     PIN(9, 3), GPIO_OUT_HIGH)
+
+/* HDMI CEC */
+/* TODO(b/197474873): Enable HDMI CEC */
+GPIO(HDMI_CEC_IN,                    PIN(4, 0), GPIO_INPUT)
+GPIO(HDMI_CEC_OUT,                   PIN(D, 3), GPIO_OUT_HIGH | GPIO_OPEN_DRAIN)
+GPIO(HDMI_CEC_PULL_UP,               PIN(C, 2), GPIO_OUT_HIGH)
+
+/* I2C SCL/SDA */
+GPIO(EC_I2C_QI_SCL,                  PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_QI_SDA,                  PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SCL_R,              PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_MISC_SDA_R,              PIN(B, 2), GPIO_INPUT)
+GPIO(EC_I2C_DP_SCL,                  PIN(B, 5), GPIO_INPUT)
+GPIO(EC_I2C_DP_SDA,                  PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_PPC_SCL,       PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_PPC_SDA,       PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_RT_SCL,        PIN(D, 1), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_RT_SDA,        PIN(D, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_TCPC_SCL,      PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_C0_C2_TCPC_SDA,      PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_MIX_SCL,          PIN(E, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_MIX_SDA,          PIN(E, 3), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_TCPC_SCL,         PIN(F, 3), GPIO_INPUT)
+GPIO(EC_I2C_USB_C1_TCPC_SDA,         PIN(F, 2), GPIO_INPUT)
+
+/* USBA */
+GPIO(EN_PP5000_USBA,                 PIN(D, 7), GPIO_OUT_LOW)
+GPIO(USB_A0_STATUS_L,                PIN(2, 1), GPIO_INPUT)
+GPIO(USB_A1_STATUS_L,                PIN(2, 0), GPIO_INPUT)
+GPIO(USB_A2_STATUS_L,                PIN(1, 7), GPIO_INPUT)
+GPIO(USB_A3_STATUS_L,                PIN(1, 6), GPIO_INPUT)
+GPIO(USB_A_LOW_PWR0_OD,              PIN(1, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(USB_A_LOW_PWR1_OD,              PIN(1, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(USB_A_LOW_PWR2_OD,              PIN(1, 1), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(USB_A_LOW_PWR3_OD,              PIN(1, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(USB_A_OC_SOC_L,                 PIN(8, 0), GPIO_OUT_HIGH)
+
+/* LED */
+/* TODO(b/197471359): LED implementation */
+GPIO(LED_GREEN_L,                    PIN(C, 3), GPIO_OUT_LOW)
+GPIO(LED_RED_L,                      PIN(C, 4), GPIO_OUT_LOW)
+
+/* USBC */
+GPIO(USB_C0_C2_TCPC_RST_ODL,         PIN(A, 7), GPIO_ODR_LOW)
+GPIO(USB_C1_FRS_EN,                  PIN(9, 4), GPIO_OUT_LOW)
+GPIO(USB_C1_RT_INT_ODL,              PIN(A, 0), GPIO_INPUT)
+GPIO(USB_C1_RT_RST_R_L,              PIN(0, 2), GPIO_OUT_LOW)
+
+/* GPIO02_P2 to PU */
+/* GPIO03_P2 to PU */
+IOEX(USB_C0_OC_ODL,          EXPIN(IOEX_C0_NCT38XX, 0, 4), GPIO_ODR_HIGH)
+IOEX(USB_C0_FRS_EN,          EXPIN(IOEX_C0_NCT38XX, 0, 6), GPIO_LOW)
+IOEX(USB_C0_RT_RST_ODL,      EXPIN(IOEX_C0_NCT38XX, 0, 7), GPIO_ODR_LOW)
+
+IOEX(USB_C2_RT_RST_ODL,      EXPIN(IOEX_C2_NCT38XX, 0, 2), GPIO_ODR_LOW)
+IOEX(USB_C1_OC_ODL,          EXPIN(IOEX_C2_NCT38XX, 0, 3), GPIO_ODR_HIGH)
+IOEX(USB_C2_OC_ODL,          EXPIN(IOEX_C2_NCT38XX, 0, 4), GPIO_ODR_HIGH)
+IOEX(USB_C2_FRS_EN,          EXPIN(IOEX_C2_NCT38XX, 0, 6), GPIO_LOW)
+/* GPIO07_P2 to PU */
+
+/* UART alternate functions */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)              /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */
+
+/* I2C alternate functions */
+ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)               /* GPIO33/I2C5_SCL0/CTS_L, GPIO36/RTS_L/I2C5_SDA0 */
+ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)               /* GPIO87/I2C1_SDA0 */
+ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)               /* GPIO92/I2C2_SCL0, GPIO91/I2C2_SDA0, GPIO90/I2C1_SCL0 */
+ALTERNATE(PIN_MASK(B, 0x0c), 0, MODULE_I2C, 0)               /* GPIOB3/I2C7_SCL0/DCD_L, GPIOB2/I2C7_SDA0/DSR_L */
+ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, 0)               /* GPIOB5/I2C0_SCL0, GPIOB4/I2C0_SDA0 */
+ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)               /* GPIOD1/I2C3_SCL0, GPIOD0/I2C3_SDA0 */
+ALTERNATE(PIN_MASK(E, 0x18), 0, MODULE_I2C, 0)               /* GPIOE4/I2C6_SCL1/I3C_SCL, GPIOE3/I2C6_SDA1/I3C_SDA */
+ALTERNATE(PIN_MASK(F, 0x0c), 0, MODULE_I2C, 0)               /* GPIOF3/I2C4_SCL1, GPIOF2/I2C4_SDA1 */
+
+/* PWM alternate functions */
+ALTERNATE(PIN_MASK(7, 0x08), 0, MODULE_PWM, 0)               /* GPIO73/TA2 */
+ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)               /* GPIOB7/PWM5 */
+ALTERNATE(PIN_MASK(C, 0x18), 0, MODULE_PWM, 0)               /* GPIOC4/PWM2, GPIOC3/PWM0 */
+
+/* ADC alternate functions */
+ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0)               /* GPIO34/PS2_DAT2/ADC6 */
+ALTERNATE(PIN_MASK(4, 0x38), 0, MODULE_ADC, 0)               /* GPIO45/ADC0, GPIO44/ADC1, GPIO43/ADC2 */
+ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0)               /* GPIOE1/ADC7 */
+
+/* Unused Pins */
+UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
+UNUSED(PIN(3, 2))       /* GPO32/TRIS_L */
+UNUSED(PIN(3, 5))       /* GPO35/CR_SOUT4/TEST_L */
+UNUSED(PIN(6, 6))       /* GPIO66 */
+UNUSED(PIN(8, 1))       /* GPIO81/PECI_DATA */
+UNUSED(PIN(5, 6))       /* GPIO56/CLKRUN# */
+UNUSED(PIN(9, 7))       /* GPIO97 */
+UNUSED(PIN(8, 6))       /* GPIO86/TXD/CR_SOUT2 */
+UNUSED(PIN(1, 3))       /* KSO06/GPO13/GP_SEL# */
+UNUSED(PIN(1, 2))       /* KSO07/GPO12/JEN# */
+UNUSED(PIN(0, 6))       /* KSO11/GPIO06/P80_CLK */
+UNUSED(PIN(0, 4))       /* KSO13/GPIO04 */
diff --git a/board/gaelin/i2c.c b/board/gaelin/i2c.c
new file mode 100644
index 0000000000..0a0b6b69a6
--- /dev/null
+++ b/board/gaelin/i2c.c
@@ -0,0 +1,78 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "compile_time_macros.h"
+
+#include "i2c.h"
+
+/* I2C port map configuration */
+const struct i2c_port_t i2c_ports[] = {
+	{
+		/* I2C0 */
+		.name = "dp_redriver",
+		.port = I2C_PORT_DP_REDRIVER,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_DP_SCL,
+		.sda = GPIO_EC_I2C_DP_SDA,
+	},
+	{
+		/* I2C1 */
+		.name = "tcpc0,2",
+		.port = I2C_PORT_USB_C0_C2_TCPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C2_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C2_TCPC_SDA,
+	},
+	{
+		/* I2C2 */
+		.name = "ppc0,2",
+		.port = I2C_PORT_USB_C0_C2_PPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C2_PPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C2_PPC_SDA,
+	},
+	{
+		/* I2C3 */
+		.name = "retimer0,2",
+		.port = I2C_PORT_USB_C0_C2_MUX,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C0_C2_RT_SCL,
+		.sda = GPIO_EC_I2C_USB_C0_C2_RT_SDA,
+	},
+	{
+		/* I2C4 C1 TCPC */
+		.name = "tcpc1",
+		.port = I2C_PORT_USB_C1_TCPC,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_USB_C1_TCPC_SCL,
+		.sda = GPIO_EC_I2C_USB_C1_TCPC_SDA,
+	},
+	{
+		/* I2C5 */
+		.name = "wireless_charger",
+		.port = I2C_PORT_QI,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_QI_SCL,
+		.sda = GPIO_EC_I2C_QI_SDA,
+	},
+	{
+		/* I2C6 */
+		.name = "ppc1",
+		.port = I2C_PORT_USB_C1_PPC,
+		.kbps = 1000,
+		.scl = GPIO_EC_I2C_USB_C1_MIX_SCL,
+		.sda = GPIO_EC_I2C_USB_C1_MIX_SDA,
+	},
+	{
+		/* I2C7 */
+		.name = "eeprom",
+		.port = I2C_PORT_EEPROM,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_MISC_SCL_R,
+		.sda = GPIO_EC_I2C_MISC_SDA_R,
+	},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/board/gaelin/led.c b/board/gaelin/led.c
new file mode 100644
index 0000000000..842cee0530
--- /dev/null
+++ b/board/gaelin/led.c
@@ -0,0 +1,260 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power LED control for Brask.
+ * Solid green - active power
+ * Green flashing - suspended
+ * Red flashing - alert
+ * Solid red - critical
+ */
+
+#include "chipset.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "led_common.h"
+#include "pwm.h"
+#include "timer.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
+
+/*
+ * Due to the CSME-Lite processing, upon startup the CPU transitions through
+ * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so
+ * delay turning off the LED during suspend/shutdown.
+ */
+#define LED_CPU_DELAY_MS (2000 * MSEC)
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED };
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+enum led_color {
+	LED_OFF = 0,
+	LED_RED,
+	LED_GREEN,
+
+	/* Number of colors, not a color itself */
+	LED_COLOR_COUNT
+};
+
+static int set_color_power(enum led_color color, int duty)
+{
+	int green = 0;
+	int red = 0;
+
+	if (duty < 0 || 100 < duty)
+		return EC_ERROR_UNKNOWN;
+
+	switch (color) {
+	case LED_OFF:
+		break;
+	case LED_GREEN:
+		green = 1;
+		break;
+	case LED_RED:
+		red = 1;
+		break;
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+
+	if (red)
+		pwm_set_duty(PWM_CH_LED_RED, duty);
+	else
+		pwm_set_duty(PWM_CH_LED_RED, 0);
+
+	if (green)
+		pwm_set_duty(PWM_CH_LED_GREEN, duty);
+	else
+		pwm_set_duty(PWM_CH_LED_GREEN, 0);
+
+	return EC_SUCCESS;
+}
+
+static int set_color(enum ec_led_id id, enum led_color color, int duty)
+{
+	switch (id) {
+	case EC_LED_ID_POWER_LED:
+		return set_color_power(color, duty);
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+}
+
+#define LED_PULSE_US (2 * SECOND)
+/* 40 msec for nice and smooth transition. */
+#define LED_PULSE_TICK_US (40 * MSEC)
+
+/*
+ * When pulsing is enabled, brightness is incremented by <duty_inc> every
+ * <interval> usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented
+ * likewise in LED_PULSE_US usec.
+ */
+static struct {
+	uint32_t interval;
+	int duty_inc;
+	enum led_color color;
+	int duty;
+} led_pulse;
+
+#define CONFIG_TICK(interval, color) \
+	config_tick((interval), 100 / (LED_PULSE_US / (interval)), (color))
+
+static void config_tick(uint32_t interval, int duty_inc, enum led_color color)
+{
+	led_pulse.interval = interval;
+	led_pulse.duty_inc = duty_inc;
+	led_pulse.color = color;
+	led_pulse.duty = 0;
+}
+
+static void pulse_power_led(enum led_color color)
+{
+	set_color(EC_LED_ID_POWER_LED, color, led_pulse.duty);
+	if (led_pulse.duty + led_pulse.duty_inc > 100)
+		led_pulse.duty_inc = led_pulse.duty_inc * -1;
+	else if (led_pulse.duty + led_pulse.duty_inc < 0)
+		led_pulse.duty_inc = led_pulse.duty_inc * -1;
+	led_pulse.duty += led_pulse.duty_inc;
+}
+
+static void led_tick(void);
+DECLARE_DEFERRED(led_tick);
+static void led_tick(void)
+{
+	uint32_t elapsed;
+	uint32_t next = 0;
+	uint32_t start = get_time().le.lo;
+
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		pulse_power_led(led_pulse.color);
+	elapsed = get_time().le.lo - start;
+	next = led_pulse.interval > elapsed ? led_pulse.interval - elapsed : 0;
+	hook_call_deferred(&led_tick_data, next);
+}
+
+static void led_suspend(void)
+{
+	CONFIG_TICK(LED_PULSE_TICK_US, LED_GREEN);
+	led_tick();
+}
+DECLARE_DEFERRED(led_suspend);
+
+static void led_shutdown(void)
+{
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_OFF, 0);
+}
+DECLARE_DEFERRED(led_shutdown);
+
+static void led_shutdown_hook(void)
+{
+	hook_call_deferred(&led_tick_data, -1);
+	hook_call_deferred(&led_suspend_data, -1);
+	hook_call_deferred(&led_shutdown_data, LED_CPU_DELAY_MS);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, led_shutdown_hook, HOOK_PRIO_DEFAULT);
+
+static void led_suspend_hook(void)
+{
+	hook_call_deferred(&led_shutdown_data, -1);
+	hook_call_deferred(&led_suspend_data, LED_CPU_DELAY_MS);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, led_suspend_hook, HOOK_PRIO_DEFAULT);
+
+static void led_resume(void)
+{
+	/*
+	 * Assume there is no race condition with led_tick, which also
+	 * runs in hook_task.
+	 */
+	hook_call_deferred(&led_tick_data, -1);
+	/*
+	 * Avoid invoking the suspend/shutdown delayed hooks.
+	 */
+	hook_call_deferred(&led_suspend_data, -1);
+	hook_call_deferred(&led_shutdown_data, -1);
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_GREEN, 100);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, led_resume, HOOK_PRIO_DEFAULT);
+
+void led_alert(int enable)
+{
+	if (enable) {
+		/* Overwrite the current signal */
+		config_tick(1 * SECOND, 100, LED_RED);
+		led_tick();
+	} else {
+		/* Restore the previous signal */
+		if (chipset_in_state(CHIPSET_STATE_ON))
+			led_resume();
+		else if (chipset_in_state(CHIPSET_STATE_SUSPEND))
+			led_suspend_hook();
+		else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+			led_shutdown_hook();
+	}
+}
+
+void show_critical_error(void)
+{
+	hook_call_deferred(&led_tick_data, -1);
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		set_color(EC_LED_ID_POWER_LED, LED_RED, 100);
+}
+
+static int command_led(int argc, const char **argv)
+{
+	enum ec_led_id id = EC_LED_ID_POWER_LED;
+
+	if (argc < 2)
+		return EC_ERROR_PARAM_COUNT;
+
+	if (!strcasecmp(argv[1], "debug")) {
+		led_auto_control(id, !led_auto_control_is_enabled(id));
+		ccprintf("o%s\n", led_auto_control_is_enabled(id) ? "ff" : "n");
+	} else if (!strcasecmp(argv[1], "off")) {
+		set_color(id, LED_OFF, 0);
+	} else if (!strcasecmp(argv[1], "red")) {
+		set_color(id, LED_RED, 100);
+	} else if (!strcasecmp(argv[1], "green")) {
+		set_color(id, LED_GREEN, 100);
+	} else if (!strcasecmp(argv[1], "alert")) {
+		led_alert(1);
+	} else if (!strcasecmp(argv[1], "crit")) {
+		show_critical_error();
+	} else {
+		return EC_ERROR_PARAM1;
+	}
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(led, command_led, "[debug|red|green|off|alert|crit]",
+			"Turn on/off LED.");
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	brightness_range[EC_LED_COLOR_RED] = 100;
+	brightness_range[EC_LED_COLOR_GREEN] = 100;
+}
+
+int led_set_brightness(enum ec_led_id id, const uint8_t *brightness)
+{
+	if (brightness[EC_LED_COLOR_RED])
+		return set_color(id, LED_RED, brightness[EC_LED_COLOR_RED]);
+	else if (brightness[EC_LED_COLOR_GREEN])
+		return set_color(id, LED_GREEN, brightness[EC_LED_COLOR_GREEN]);
+	else
+		return set_color(id, LED_OFF, 0);
+}
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
+{
+	/* Blink alert if insufficient power per system_can_boot_ap(). */
+	int insufficient_power =
+		(charge_ma * charge_mv) <
+		(CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON * 1000);
+	led_alert(insufficient_power);
+}
diff --git a/board/gaelin/pwm.c b/board/gaelin/pwm.c
new file mode 100644
index 0000000000..3d4335f453
--- /dev/null
+++ b/board/gaelin/pwm.c
@@ -0,0 +1,40 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+
+#include "compile_time_macros.h"
+#include "hooks.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_LED_GREEN] = { .channel = 0,
+			       .flags = PWM_CONFIG_ACTIVE_LOW |
+					PWM_CONFIG_DSLEEP,
+			       .freq = 2000 },
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN | PWM_CONFIG_DSLEEP,
+			 .freq = 1000 },
+	[PWM_CH_LED_RED] = { .channel = 2,
+			     .flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+			     .freq = 2000 },
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+static void board_pwm_init(void)
+{
+	/*
+	 * TODO(b/197478860): Turn on the fan at 100% by default
+	 * We need to find tune the fan speed according to the
+	 * thermal sensor value.
+	 */
+	pwm_enable(PWM_CH_FAN, 1);
+	pwm_set_duty(PWM_CH_FAN, 100);
+
+	pwm_enable(PWM_CH_LED_RED, 1);
+	pwm_enable(PWM_CH_LED_GREEN, 1);
+}
+DECLARE_HOOK(HOOK_INIT, board_pwm_init, HOOK_PRIO_DEFAULT);
diff --git a/board/gaelin/sensors.c b/board/gaelin/sensors.c
new file mode 100644
index 0000000000..162140d37d
--- /dev/null
+++ b/board/gaelin/sensors.c
@@ -0,0 +1,114 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "adc_chip.h"
+#include "hooks.h"
+#include "temp_sensor.h"
+#include "thermal.h"
+#include "temp_sensor/thermistor.h"
+
+/* ADC configuration */
+const struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_1_CPU] = {
+		.name = "TEMP_CPU",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_2_CPU_VR] = {
+		.name = "TEMP_CPU_VR",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_3_WIFI] = {
+		.name = "TEMP_WIFI",
+		.input_ch = NPCX_ADC_CH6,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_4_DIMM] = {
+		.name = "TEMP_DIMM",
+		.input_ch = NPCX_ADC_CH7,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_VBUS] = {  /* 5/39 voltage divider */
+		.name = "VBUS",
+		.input_ch = NPCX_ADC_CH2,
+		.factor_mul = ADC_MAX_VOLT * 39,
+		.factor_div = (ADC_READ_MAX + 1) * 5,
+	},
+	[ADC_PPVAR_IMON] = {  /* 872.3 mV/A */
+		.name = "PPVAR_IMON",
+		.input_ch = NPCX_ADC_CH3,
+		.factor_mul = ADC_MAX_VOLT * 1433,
+		.factor_div = (ADC_READ_MAX + 1) * 1250,
+	},
+
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* Temperature sensor configuration */
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_1_CPU] = { .name = "CPU",
+				.type = TEMP_SENSOR_TYPE_BOARD,
+				.read = get_temp_3v3_30k9_47k_4050b,
+				.idx = ADC_TEMP_SENSOR_1_CPU },
+	[TEMP_SENSOR_2_CPU_VR] = { .name = "CPU VR",
+				   .type = TEMP_SENSOR_TYPE_BOARD,
+				   .read = get_temp_3v3_30k9_47k_4050b,
+				   .idx = ADC_TEMP_SENSOR_2_CPU_VR },
+	[TEMP_SENSOR_3_WIFI] = { .name = "WIFI",
+				 .type = TEMP_SENSOR_TYPE_BOARD,
+				 .read = get_temp_3v3_30k9_47k_4050b,
+				 .idx = ADC_TEMP_SENSOR_3_WIFI },
+	[TEMP_SENSOR_4_DIMM] = { .name = "DIMM",
+				 .type = TEMP_SENSOR_TYPE_BOARD,
+				 .read = get_temp_3v3_30k9_47k_4050b,
+				 .idx = ADC_TEMP_SENSOR_4_DIMM },
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+/*
+ * TODO(b/180681346): update for Alder Lake/brya
+ *
+ * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
+ * 130 C.  However, sensor is located next to DDR, so we need to use the lower
+ * DDR temperature limit (85 C)
+ */
+/*
+ * TODO(b/202062363): Remove when clang is fixed.
+ */
+#define THERMAL_CPU              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+		}, \
+		.temp_fan_off = C_TO_K(35), \
+		.temp_fan_max = C_TO_K(50), \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
+
+/*
+ * TODO(b/197478860): add the thermal sensor setting
+ */
+/* this should really be "const" */
+struct ec_thermal_config thermal_params[] = {
+	[TEMP_SENSOR_1_CPU] = THERMAL_CPU,
+	[TEMP_SENSOR_2_CPU_VR] = THERMAL_CPU,
+	[TEMP_SENSOR_3_WIFI] = THERMAL_CPU,
+	[TEMP_SENSOR_4_DIMM] = THERMAL_CPU,
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
diff --git a/board/gaelin/usbc_config.c b/board/gaelin/usbc_config.c
new file mode 100644
index 0000000000..806ff2c4ee
--- /dev/null
+++ b/board/gaelin/usbc_config.c
@@ -0,0 +1,416 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/bc12/pi3usb9201_public.h"
+#include "driver/ppc/syv682x_public.h"
+#include "driver/retimer/bb_retimer_public.h"
+#include "driver/retimer/kb800x.h"
+#include "driver/tcpm/nct38xx.h"
+#include "driver/tcpm/rt1715.h"
+#include "driver/tcpm/tcpci.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "ioexpander.h"
+#include "system.h"
+#include "task.h"
+#include "task_id.h"
+#include "timer.h"
+#include "usbc_config.h"
+#include "usbc_ppc.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+/* USBC TCPC configuration */
+const struct tcpc_config_t tcpc_config[] = {
+	[USBC_PORT_C0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0_C2_TCPC,
+			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_NO_DEBUG_ACC_CONTROL,
+	},
+	[USBC_PORT_C1] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C1_TCPC,
+			.addr_flags = RT1715_I2C_ADDR_FLAGS,
+		},
+		.drv = &rt1715_tcpm_drv,
+	},
+	[USBC_PORT_C2] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0_C2_TCPC,
+			.addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
+BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
+
+/* USBC PPC configuration */
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_C2_PPC,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.drv = &syv682x_drv,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C1_PPC,
+		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.drv = &syv682x_drv,
+	},
+	[USBC_PORT_C2] = {
+		.i2c_port = I2C_PORT_USB_C0_C2_PPC,
+		.i2c_addr_flags = SYV682X_ADDR2_FLAGS,
+		.drv = &syv682x_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
+
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/* USBC mux configuration - Alder Lake includes internal mux */
+static const struct usb_mux_chain usbc0_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+static const struct usb_mux_chain usbc1_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+static const struct usb_mux_chain usbc2_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C2,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+};
+
+struct kb800x_control_t kb800x_control[] = {
+	[USBC_PORT_C0] = {
+	},
+	[USBC_PORT_C1] = {
+		.retimer_rst_gpio = GPIO_USB_C1_RT_RST_R_L,
+		.ss_lanes = {
+			[KB800X_A0] = KB800X_TX0, [KB800X_A1] = KB800X_RX0,
+			[KB800X_B0] = KB800X_RX1, [KB800X_B1] = KB800X_TX1,
+			[KB800X_C0] = KB800X_RX0, [KB800X_C1] = KB800X_TX0,
+			[KB800X_D0] = KB800X_TX1, [KB800X_D1] = KB800X_RX1,
+			}
+	},
+	[USBC_PORT_C2] = {
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(kb800x_control) == USBC_PORT_COUNT);
+
+const struct usb_mux_chain usb_muxes[] = {
+	[USBC_PORT_C0] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C0_C2_MUX,
+			.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc0_tcss_usb_mux,
+	},
+	[USBC_PORT_C1] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &kb800x_usb_mux_driver,
+			.i2c_port = I2C_PORT_USB_C1_MUX,
+			.i2c_addr_flags = KB800X_I2C_ADDR0_FLAGS,
+		},
+		.next = &usbc1_tcss_usb_mux,
+	},
+	[USBC_PORT_C2] = {
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C2,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C0_C2_MUX,
+			.i2c_addr_flags = USBC_PORT_C2_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc2_tcss_usb_mux,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
+
+/* BC1.2 charger detect configuration */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0_C2_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_USB_C1_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+	[USBC_PORT_C2] = {
+		.i2c_port = I2C_PORT_USB_C0_C2_BC12,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_1_FLAGS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
+
+/*
+ * USB C0 and C2 uses burnside bridge chips and have their reset
+ * controlled by their respective TCPC chips acting as GPIO expanders.
+ *
+ * ioex_init() is normally called before we take the TCPCs out of
+ * reset, so we need to start in disabled mode, then explicitly
+ * call ioex_init().
+ */
+
+struct ioexpander_config_t ioex_config[] = {
+	[IOEX_C0_NCT38XX] = {
+		.i2c_host_port = I2C_PORT_USB_C0_C2_TCPC,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
+	},
+	[IOEX_C2_NCT38XX] = {
+		.i2c_host_port = I2C_PORT_USB_C0_C2_TCPC,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT);
+
+__override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
+{
+	enum ioex_signal rst_signal;
+
+	if (me->usb_port == USBC_PORT_C0) {
+		rst_signal = IOEX_USB_C0_RT_RST_ODL;
+	} else if (me->usb_port == USBC_PORT_C2) {
+		rst_signal = IOEX_USB_C2_RT_RST_ODL;
+	} else {
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * We do not have a load switch for the burnside bridge chips,
+	 * so we only need to sequence reset.
+	 */
+
+	if (enable) {
+		/*
+		 * Tpw, minimum time from VCC to RESET_N de-assertion is 100us.
+		 * For boards that don't provide a load switch control, the
+		 * retimer_init() function ensures power is up before calling
+		 * this function.
+		 */
+		ioex_set_level(rst_signal, 1);
+		/*
+		 * Allow 1ms time for the retimer to power up lc_domain
+		 * which powers I2C controller within retimer
+		 */
+		msleep(1);
+	} else {
+		ioex_set_level(rst_signal, 0);
+		msleep(1);
+	}
+	return EC_SUCCESS;
+}
+
+__override int bb_retimer_reset(const struct usb_mux *me)
+{
+	/*
+	 * TODO(b/193402306, b/195375738): Remove this once transition to
+	 * QS Silicon is complete
+	 */
+	bb_retimer_power_enable(me, false);
+	msleep(5);
+	bb_retimer_power_enable(me, true);
+	msleep(25);
+
+	return EC_SUCCESS;
+}
+
+void board_reset_pd_mcu(void)
+{
+	enum gpio_signal tcpc_rst;
+
+	tcpc_rst = GPIO_USB_C0_C2_TCPC_RST_ODL;
+
+	/*
+	 * TODO(b/179648104): figure out correct timing
+	 */
+
+	gpio_set_level(tcpc_rst, 0);
+	gpio_set_level(GPIO_USB_C1_RT_RST_R_L, 0);
+
+	/*
+	 * delay for power-on to reset-off and min. assertion time
+	 */
+
+	msleep(20);
+
+	gpio_set_level(tcpc_rst, 1);
+	gpio_set_level(GPIO_USB_C1_RT_RST_R_L, 1);
+
+	/* wait for chips to come up */
+
+	msleep(50);
+}
+
+static void enable_ioex(int ioex)
+{
+	ioex_init(ioex);
+}
+
+static void board_tcpc_init(void)
+{
+	/* Don't reset TCPCs after initial reset */
+	if (!system_jumped_late()) {
+		board_reset_pd_mcu();
+
+		/*
+		 * These IO expander pins are implemented using the
+		 * C0/C2 TCPC, so they must be set up after the TCPC has
+		 * been taken out of reset.
+		 */
+		enable_ioex(IOEX_C0_NCT38XX);
+		enable_ioex(IOEX_C2_NCT38XX);
+	}
+
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C2_PPC_INT_ODL);
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_C2_TCPC_INT_ODL);
+
+	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (gpio_get_level(GPIO_USB_C0_C2_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_0 | PD_STATUS_TCPC_ALERT_2;
+
+	if (gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL) == 0)
+		status |= PD_STATUS_TCPC_ALERT_1;
+
+	return status;
+}
+
+int ppc_get_alert_status(int port)
+{
+	if (port == USBC_PORT_C0)
+		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
+	else if (port == USBC_PORT_C1)
+		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
+	else if (port == USBC_PORT_C2)
+		return gpio_get_level(GPIO_USB_C2_PPC_INT_ODL) == 0;
+	return 0;
+}
+
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_C2_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_TCPC_INT_ODL:
+		schedule_deferred_pd_interrupt(USBC_PORT_C1);
+		break;
+	default:
+		break;
+	}
+}
+
+void bc12_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_BC12_INT_ODL:
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+		break;
+	case GPIO_USB_C1_BC12_INT_ODL:
+		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+		break;
+	case GPIO_USB_C2_BC12_INT_ODL:
+		usb_charger_task_set_event(2, USB_CHG_EVENT_BC12);
+		break;
+	default:
+		break;
+	}
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C0);
+		break;
+	case GPIO_USB_C1_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C1);
+		break;
+	case GPIO_USB_C2_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C2);
+		break;
+	default:
+		break;
+	}
+}
+
+void retimer_interrupt(enum gpio_signal signal)
+{
+	/*
+	 * TODO(b/179513527): add USB-C support
+	 */
+}
+
+__override bool board_is_dts_port(int port)
+{
+	return port == USBC_PORT_C0;
+}
+
+__override bool board_is_tbt_usb4_port(int port)
+{
+	return true;
+}
+
+__override enum tbt_compat_cable_speed board_get_max_tbt_speed(int port)
+{
+	if (!board_is_tbt_usb4_port(port))
+		return TBT_SS_RES_0;
+
+	return TBT_SS_TBT_GEN3;
+}
diff --git a/board/ghost/usbc_config.h b/board/gaelin/usbc_config.h
index 047d094c6d..5e7beae21a 100644
--- a/board/ghost/usbc_config.h
+++ b/board/gaelin/usbc_config.h
@@ -1,22 +1,19 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-/* Ghost board-specific USB-C configuration */
+/* Brya board-specific USB-C configuration */
 
 #ifndef __CROS_EC_USBC_CONFIG_H
 #define __CROS_EC_USBC_CONFIG_H
 
-#include "baseboard_usbc_config.h"
-
-#ifndef CONFIG_ZEPHYR
-#define CONFIG_USB_PD_PORT_MAX_COUNT	2
-#endif
+#define CONFIG_USB_PD_PORT_MAX_COUNT 3
 
 enum usbc_port {
 	USBC_PORT_C0 = 0,
 	USBC_PORT_C1,
+	USBC_PORT_C2,
 	USBC_PORT_COUNT
 };
 
diff --git a/board/ghost/vif_override.xml b/board/gaelin/vif_override.xml
index 32736caf64..32736caf64 100644
--- a/board/ghost/vif_override.xml
+++ b/board/gaelin/vif_override.xml
diff --git a/board/galtic/battery.c b/board/galtic/battery.c
index df23027815..10fc273303 100644
--- a/board/galtic/battery.c
+++ b/board/galtic/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/galtic/board.c b/board/galtic/board.c
index 727e31508e..af0638be20 100644
--- a/board/galtic/board.c
+++ b/board/galtic/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -47,8 +47,8 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
 
 #define INT_RECHECK_US 5000
 
@@ -131,34 +131,26 @@ static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH0
-	},
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH2
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH3
-	},
-	[ADC_TEMP_SENSOR_3] = {
-		.name = "TEMP_SENSOR3",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH15
-	},
+	[ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH0 },
+	[ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH2 },
+	[ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH3 },
+	[ADC_TEMP_SENSOR_3] = { .name = "TEMP_SENSOR3",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH15 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
@@ -218,40 +210,31 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 };
 
 /* USB Retimer */
-enum tusb544_conf {
-	USB_DP = 0,
-	USB_DP_INV,
-	USB,
-	USB_INV,
-	DP,
-	DP_INV
-};
+enum tusb544_conf { USB_DP = 0, USB_DP_INV, USB, USB_INV, DP, DP_INV };
 
-static int board_tusb544_set(const struct usb_mux *me,
-		mux_state_t mux_state)
+static int board_tusb544_set(const struct usb_mux *me, mux_state_t mux_state)
 {
-	int  rv = EC_SUCCESS;
+	int rv = EC_SUCCESS;
 	enum tusb544_conf usb_mode = 0;
 	/* USB */
 	if (mux_state & USB_PD_MUX_USB_ENABLED) {
 		/* USB with DP */
 		if (mux_state & USB_PD_MUX_DP_ENABLED) {
-			usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-					? USB_DP_INV
-					: USB_DP;
+			usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ?
+					   USB_DP_INV :
+					   USB_DP;
 		}
 		/* USB without DP */
 		else {
-			usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-					? USB_INV
-					: USB;
+			usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ?
+					   USB_INV :
+					   USB;
 		}
 	}
 	/* DP without USB */
 	else if (mux_state & USB_PD_MUX_DP_ENABLED) {
-		usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-				? DP_INV
-				: DP;
+		usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ? DP_INV :
+									DP;
 	}
 	/* Nothing enabled */
 	else
@@ -320,11 +303,9 @@ static int board_tusb544_set(const struct usb_mux *me,
 	return rv;
 }
 
-static int board_ps8743_mux_set(const struct usb_mux *me,
-				mux_state_t mux_state)
+static int board_ps8743_mux_set(const struct usb_mux *me, mux_state_t mux_state)
 {
-	return ps8743_write(me, PS8743_REG_USB_EQ_RX,
-				PS8743_USB_EQ_RX_16_7_DB);
+	return ps8743_write(me, PS8743_REG_USB_EQ_RX, PS8743_USB_EQ_RX_16_7_DB);
 }
 
 const struct usb_mux usbc1_retimer = {
@@ -341,20 +322,31 @@ const struct usb_mux usbc1_virtual_mux_ps8743 = {
 	.hpd_update = &virtual_hpd_update,
 };
 
+struct usb_mux usbc1_mux0_data = {
+	.usb_port = 1,
+	.i2c_port = I2C_PORT_SUB_USB_C1,
+	.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+	.driver = &it5205_usb_mux_driver,
+};
+
+struct usb_mux_chain usbc1_mux1 = {
+	.mux = &usbc1_retimer,
+};
+
 /* USB Muxes */
-struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+			},
 	},
 	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.next_mux = &usbc1_retimer,
+		.mux = &usbc1_mux0_data,
+		.next = &usbc1_mux1,
 	},
 };
 
@@ -392,8 +384,8 @@ static const struct ec_response_keybd_config galtic_kb = {
 	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
 };
 
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	if (get_cbi_fw_config_numeric_pad() == NUMERIC_PAD_PRESENT)
 		return &galith_kb;
@@ -442,10 +434,10 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 void setup_mux_config(void)
 {
 	if (get_cbi_ssfc_mux_redriver() == SSFC_MUX_PS8743) {
-		usb_muxes[1].i2c_addr_flags = PS8743_I2C_ADDR1_FLAG;
-		usb_muxes[1].driver = &ps8743_usb_mux_driver;
-		usb_muxes[1].next_mux = &usbc1_virtual_mux_ps8743;
-		usb_muxes[1].board_set = &board_ps8743_mux_set;
+		usbc1_mux0_data.i2c_addr_flags = PS8743_I2C_ADDR1_FLAG;
+		usbc1_mux0_data.driver = &ps8743_usb_mux_driver;
+		usbc1_mux1.mux = &usbc1_virtual_mux_ps8743;
+		usbc1_mux0_data.board_set = &board_ps8743_mux_set;
 	}
 }
 DECLARE_HOOK(HOOK_INIT, setup_mux_config, HOOK_PRIO_INIT_I2C + 2);
@@ -532,8 +524,7 @@ int board_is_sourcing_vbus(int port)
 
 int board_set_active_charge_port(int port)
 {
-		int is_real_port = (port >= 0 &&
-			    port < board_get_usb_pd_port_count());
+	int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count());
 	int i;
 	int old_port;
 
@@ -595,12 +586,10 @@ int board_set_active_charge_port(int port)
 	charger_discharge_on_ac(0);
 
 	return EC_SUCCESS;
-
 }
 
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
+__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+				       int *ki_div, int *kd, int *kd_div)
 {
 	*kp = 1;
 	*kp_div = 20;
@@ -634,27 +623,21 @@ static struct mutex g_base_mutex;
 
 /* Sensor Data */
 static struct accelgyro_saved_data_t g_bma253_data;
-static struct kionix_accel_data  g_kx022_data;
+static struct kionix_accel_data g_kx022_data;
 static struct bmi_drv_data_t g_bmi160_data;
 static struct icm_drv_data_t g_icm426xx_data;
 
-const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+				      { 0, FLOAT_TO_FP(-1), 0 },
+				      { 0, 0, FLOAT_TO_FP(-1) } };
 
-const mat33_fp_t base_standard_ref_icm = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t base_standard_ref_icm = { { FLOAT_TO_FP(1), 0, 0 },
+					   { 0, FLOAT_TO_FP(-1), 0 },
+					   { 0, 0, FLOAT_TO_FP(-1) } };
 
-const mat33_fp_t base_standard_ref_bmi = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t base_standard_ref_bmi = { { 0, FLOAT_TO_FP(-1), 0 },
+					   { FLOAT_TO_FP(-1), 0, 0 },
+					   { 0, 0, FLOAT_TO_FP(-1) } };
 
 struct motion_sensor_t bma253_lid_accel = {
 	.name = "Lid Accel",
@@ -826,26 +809,26 @@ DECLARE_HOOK(HOOK_INIT, board_sensors_init, HOOK_PRIO_DEFAULT);
 
 /* Thermistors */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Charger",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Vcore",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_3},
+	[TEMP_SENSOR_1] = { .name = "Charger",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Vcore",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CHARGER \
-	{ \
+#define THERMAL_CHARGER          \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(85), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(98), \
@@ -859,8 +842,8 @@ __maybe_unused static const struct ec_thermal_config thermal_charger =
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_VCORE \
-	{ \
+#define THERMAL_VCORE            \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
@@ -874,8 +857,8 @@ __maybe_unused static const struct ec_thermal_config thermal_vcore =
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_AMBIENT \
-	{ \
+#define THERMAL_AMBIENT          \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
@@ -941,8 +924,8 @@ static void get_battery_cell(void)
 {
 	int val;
 
-	if (i2c_read16(I2C_PORT_USB_C0, ISL923X_ADDR_FLAGS,
-		       ISL9238_REG_INFO2, &val) == EC_SUCCESS) {
+	if (i2c_read16(I2C_PORT_USB_C0, ISL923X_ADDR_FLAGS, ISL9238_REG_INFO2,
+		       &val) == EC_SUCCESS) {
 		/* PROG resistor read out. Number of battery cells [4:0] */
 		val = val & 0x001f;
 	}
@@ -958,7 +941,7 @@ static void get_battery_cell(void)
 
 	CPRINTS("Get battery cells: %d", battery_cell);
 }
-DECLARE_HOOK(HOOK_INIT, get_battery_cell, HOOK_PRIO_INIT_I2C+1);
+DECLARE_HOOK(HOOK_INIT, get_battery_cell, HOOK_PRIO_INIT_I2C + 1);
 
 enum battery_cell_type board_get_battery_cell_type(void)
 {
diff --git a/board/galtic/board.h b/board/galtic/board.h
index 50f9fdca9c..cfed23b359 100644
--- a/board/galtic/board.h
+++ b/board/galtic/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,12 +22,15 @@
 #define CONFIG_BC12_DETECT_PI3USB9201
 
 /* Charger */
-#define CONFIG_CHARGER_RAA489000	/* C0 and C1: Charger */
+#define CONFIG_CHARGER_RAA489000 /* C0 and C1: Charger */
+#define PD_MAX_VOLTAGE_MV 20000
 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 #define CONFIG_CHARGER_SENSE_RESISTOR 10
-#undef  CONFIG_CHARGER_SINGLE_CHIP
+#undef CONFIG_CHARGER_SINGLE_CHIP
 #define CONFIG_OCPC
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */
+#define CONFIG_OCPC_DEF_RBATT_MOHMS               \
+	22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \
+	    */
 #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
 #define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
 
@@ -35,19 +38,19 @@
 
 /* LED */
 #define CONFIG_LED_ONOFF_STATES
-#define CONFIG_LED_ONOFF_STATES_BAT_LOW	10
+#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
 
 /* PWM */
 #define CONFIG_PWM
 
 /* Sensors */
-#define CONFIG_ACCEL_BMA255		/* Lid accel */
-#define CONFIG_ACCEL_KX022		/* Lid accel */
-#define CONFIG_ACCELGYRO_BMI160		/* Base accel */
+#define CONFIG_ACCEL_BMA255 /* Lid accel */
+#define CONFIG_ACCEL_KX022 /* Lid accel */
+#define CONFIG_ACCELGYRO_BMI160 /* Base accel */
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 #define CONFIG_ACCELGYRO_BMI_COMM_I2C
-#define CONFIG_ACCELGYRO_ICM426XX	/* Base accel */
+#define CONFIG_ACCELGYRO_ICM426XX /* Base accel */
 #define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 #define CONFIG_ACCELGYRO_ICM_COMM_I2C
@@ -86,11 +89,11 @@
 #define CONFIG_THROTTLE_AP
 
 /* USB Mux and Retimer */
-#define CONFIG_USB_MUX_IT5205			/* C1: ITE Mux */
-#define CONFIG_USB_MUX_PS8743			/* C1: PS8743 Mux */
-#define I2C_PORT_USB_MUX I2C_PORT_USB_C0	/* Required for ITE Mux */
+#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */
+#define CONFIG_USB_MUX_PS8743 /* C1: PS8743 Mux */
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */
 
-#define CONFIG_USBC_RETIMER_TUSB544		/* C1 Redriver: TUSB544 */
+#define CONFIG_USBC_RETIMER_TUSB544 /* C1 Redriver: TUSB544 */
 #define CONFIG_USB_MUX_RUNTIME_CONFIG
 #define CONFIG_USB_MUX_VIRTUAL
 
@@ -116,19 +119,14 @@ enum pwm_channel {
 };
 
 /* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
 /* ADC channels */
 enum adc_channel {
-	ADC_VSNS_PP3300_A,     /* ADC0 */
-	ADC_TEMP_SENSOR_1,     /* ADC2 */
-	ADC_TEMP_SENSOR_2,     /* ADC3 */
-	ADC_TEMP_SENSOR_3,     /* ADC15 */
+	ADC_VSNS_PP3300_A, /* ADC0 */
+	ADC_TEMP_SENSOR_1, /* ADC2 */
+	ADC_TEMP_SENSOR_2, /* ADC3 */
+	ADC_TEMP_SENSOR_3, /* ADC15 */
 	ADC_CH_COUNT
 };
 
diff --git a/board/galtic/build.mk b/board/galtic/build.mk
index 806168ea0d..9b862c7624 100644
--- a/board/galtic/build.mk
+++ b/board/galtic/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/galtic/cbi_ssfc.c b/board/galtic/cbi_ssfc.c
index c760f37573..7a7ed9f7cf 100644
--- a/board/galtic/cbi_ssfc.c
+++ b/board/galtic/cbi_ssfc.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,15 +27,15 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
 
 enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
 {
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
 }
 
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
 {
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
 }
 
 enum ec_ssfc_mux_redriver get_cbi_ssfc_mux_redriver(void)
 {
-	return (enum ec_ssfc_mux_redriver) cached_ssfc.mux_redriver;
+	return (enum ec_ssfc_mux_redriver)cached_ssfc.mux_redriver;
 }
diff --git a/board/galtic/cbi_ssfc.h b/board/galtic/cbi_ssfc.h
index 686dcb4d47..84f321977e 100644
--- a/board/galtic/cbi_ssfc.h
+++ b/board/galtic/cbi_ssfc.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -37,7 +37,7 @@ enum ec_ssfc_lid_sensor {
  * Mux Redriver (Bit 6)
  */
 enum ec_ssfc_mux_redriver {
-	SSFC_MUX_DEFAULT = 0,		/* IT5205 + TUSB544 */
+	SSFC_MUX_DEFAULT = 0, /* IT5205 + TUSB544 */
 	SSFC_MUX_PS8743 = 1,
 };
 
diff --git a/board/galtic/ec.tasklist b/board/galtic/ec.tasklist
index 762325a825..bc2fea6148 100644
--- a/board/galtic/ec.tasklist
+++ b/board/galtic/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/galtic/gpio.inc b/board/galtic/gpio.inc
index bd8787acb3..721a193f36 100644
--- a/board/galtic/gpio.inc
+++ b/board/galtic/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/galtic/led.c b/board/galtic/led.c
index ecd40dc973..1438ccd91a 100644
--- a/board/galtic/led.c
+++ b/board/galtic/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,28 +9,37 @@
 #include "led_common.h"
 #include "led_onoff_states.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
 __override const int led_charge_lvl_1;
 __override const int led_charge_lvl_2 = 95;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]       = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]       = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC},
-					{LED_OFF,            2 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]	     = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { LED_OFF, 2 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
 const enum ec_led_id supported_led_ids[] = {
 	EC_LED_ID_BATTERY_LED,
diff --git a/board/galtic/usb_pd_policy.c b/board/galtic/usb_pd_policy.c
index 3190595596..23166f7fca 100644
--- a/board/galtic/usb_pd_policy.c
+++ b/board/galtic/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,8 @@
 #include "driver/tcpm/tcpci.h"
 #include "usb_pd.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
diff --git a/board/garg/battery.c b/board/garg/battery.c
index ac65572d09..5706344191 100644
--- a/board/garg/battery.c
+++ b/board/garg/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/garg/board.c b/board/garg/board.c
index de55f33c6a..60365a6312 100644
--- a/board/garg/board.c
+++ b/board/garg/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -44,11 +44,11 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define USB_PD_PORT_ANX7447	0
-#define USB_PD_PORT_PS8751	1
+#define USB_PD_PORT_ANX7447 0
+#define USB_PD_PORT_PS8751 1
 
 static uint8_t sku_id;
 
@@ -58,17 +58,16 @@ static uint8_t sku_id;
  * that we don't have pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-		{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-		{0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3},
-		{-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0},
-		{1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4},
-		{2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0},
-		{-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1},
-		{-1, -1},
+	{ -1, -1 }, { 0, 5 },	{ 1, 1 }, { 1, 0 },   { 0, 6 },	  { 0, 7 },
+	{ -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 },   { -1, -1 }, { 1, 6 },
+	{ 1, 7 },   { 3, 1 },	{ 2, 0 }, { 1, 5 },   { 2, 6 },	  { 2, 7 },
+	{ 2, 1 },   { 2, 4 },	{ 2, 5 }, { 1, 2 },   { 2, 3 },	  { 2, 2 },
+	{ 3, 0 },   { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 },	  { -1, -1 },
+	{ -1, -1 },
 };
 
 const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 
 static void ppc_interrupt(enum gpio_signal signal)
 {
@@ -91,31 +90,31 @@ static void ppc_interrupt(enum gpio_signal signal)
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_AMB] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_AMB] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				  ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_CHARGER] = { "TEMP_CHARGER", NPCX_ADC_CH1,
+				      ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 },
 	/* Vbus sensing (1/10 voltage divider). */
-	[ADC_VBUS_C0] = {
-		"VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
-	[ADC_VBUS_C1] = {
-		"VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
+	[ADC_VBUS_C0] = { "VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT * 10,
+			  ADC_READ_MAX + 1, 0 },
+	[ADC_VBUS_C1] = { "VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT * 10,
+			  ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp,
-				 .idx = 0},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
+	[TEMP_SENSOR_BATTERY] = { .name = "Battery",
+				  .type = TEMP_SENSOR_TYPE_BATTERY,
+				  .read = charge_get_battery_temp,
+				  .idx = 0 },
+	[TEMP_SENSOR_AMBIENT] = { .name = "Ambient",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_51k1_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_AMB },
+	[TEMP_SENSOR_CHARGER] = { .name = "Charger",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_13k7_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_CHARGER },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -125,24 +124,17 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0,  0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
-
-const mat33_fp_t base_icm_ref = {
-	{ FLOAT_TO_FP(-1), 0,  0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+				       { FLOAT_TO_FP(1), 0, 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
 
-static const mat33_fp_t base_bmi260_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_icm_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				  { 0, FLOAT_TO_FP(-1), 0 },
+				  { 0, 0, FLOAT_TO_FP(1) } };
 
+static const mat33_fp_t base_bmi260_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+					    { FLOAT_TO_FP(1), 0, 0 },
+					    { 0, 0, FLOAT_TO_FP(1) } };
 
 /* sensor private data */
 static struct kionix_accel_data g_kx022_data;
@@ -256,20 +248,20 @@ struct motion_sensor_t icm426xx_base_accel = {
 };
 
 struct motion_sensor_t icm426xx_base_gyro = {
-	 .name = "Base Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_ICM426XX,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &icm426xx_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_icm426xx_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &base_icm_ref,
-	 .min_frequency = ICM426XX_GYRO_MIN_FREQ,
-	 .max_frequency = ICM426XX_GYRO_MAX_FREQ,
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &base_icm_ref,
+	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
+	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
 };
 
 struct motion_sensor_t bmi260_base_accel = {
@@ -318,7 +310,6 @@ struct motion_sensor_t bmi260_base_gyro = {
 	.max_frequency = BMI_GYRO_MAX_FREQ,
 };
 
-
 static int board_is_convertible(void)
 {
 	/*
@@ -389,8 +380,8 @@ void board_hibernate_late(void)
 
 	const uint32_t hibernate_pins[][2] = {
 		/* Turn off LEDs before going to hibernate */
-		{GPIO_BAT_LED_BLUE_L, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_BAT_LED_ORANGE_L, GPIO_INPUT | GPIO_PULL_UP},
+		{ GPIO_BAT_LED_BLUE_L, GPIO_INPUT | GPIO_PULL_UP },
+		{ GPIO_BAT_LED_ORANGE_L, GPIO_INPUT | GPIO_PULL_UP },
 	};
 
 	for (i = 0; i < ARRAY_SIZE(hibernate_pins); ++i)
diff --git a/board/garg/board.h b/board/garg/board.h
index 638c8c93a0..23f44b469e 100644
--- a/board/garg/board.h
+++ b/board/garg/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,6 +10,7 @@
 
 /* Free up flash space */
 #define CONFIG_LTO
+#undef CONFIG_CMD_BATTFAKE
 
 /* Select Baseboard features */
 #define VARIANT_OCTOPUS_EC_NPCX796FB
@@ -19,16 +20,16 @@
 #define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD
 
 /* I2C bus configuraiton */
-#define I2C_PORT_ACCEL	I2C_PORT_SENSOR
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
 
 #define CONFIG_LED_COMMON
 
 /* Sensors */
-#define CONFIG_ACCEL_KX022	/* Lid accel */
-#define CONFIG_ACCELGYRO_BMI160	/* Base accel */
-#define CONFIG_ACCELGYRO_BMI260	/* 3rd Base accel */
-#define CONFIG_ACCELGYRO_ICM426XX	/* 2nd Base accel */
-#define CONFIG_SYNC		/* Camera VSYNC */
+#define CONFIG_ACCEL_KX022 /* Lid accel */
+#define CONFIG_ACCELGYRO_BMI160 /* Base accel */
+#define CONFIG_ACCELGYRO_BMI260 /* 3rd Base accel */
+#define CONFIG_ACCELGYRO_ICM426XX /* 2nd Base accel */
+#define CONFIG_SYNC /* Camera VSYNC */
 
 #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
 /* Sensors without hardware FIFO are in forced mode */
@@ -42,8 +43,7 @@
 #define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 
-#define CONFIG_SYNC_INT_EVENT	\
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
+#define CONFIG_SYNC_INT_EVENT TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
 
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_UPDATE
@@ -68,10 +68,10 @@
 #include "registers.h"
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_AMB,		/* ADC0 */
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC1 */
-	ADC_VBUS_C0,			/* ADC9 */
-	ADC_VBUS_C1,			/* ADC4 */
+	ADC_TEMP_SENSOR_AMB, /* ADC0 */
+	ADC_TEMP_SENSOR_CHARGER, /* ADC1 */
+	ADC_VBUS_C0, /* ADC9 */
+	ADC_VBUS_C1, /* ADC4 */
 	ADC_CH_COUNT
 };
 
@@ -83,13 +83,7 @@ enum temp_sensor_id {
 };
 
 /* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	VSYNC,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, VSYNC, SENSOR_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
diff --git a/board/garg/build.mk b/board/garg/build.mk
index 137e208b53..fee77e38b5 100644
--- a/board/garg/build.mk
+++ b/board/garg/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/garg/ec.tasklist b/board/garg/ec.tasklist
index 6eac78a042..6c56976091 100644
--- a/board/garg/ec.tasklist
+++ b/board/garg/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/garg/gpio.inc b/board/garg/gpio.inc
index 995986d600..57feead408 100644
--- a/board/garg/gpio.inc
+++ b/board/garg/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/garg/led.c b/board/garg/led.c
index bc77efe9b9..eff8c1307b 100644
--- a/board/garg/led.c
+++ b/board/garg/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,8 +10,8 @@
 #include "led_common.h"
 #include "led_onoff_states.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
 __override const int led_charge_lvl_1;
 
@@ -19,18 +19,24 @@ __override const int led_charge_lvl_2 = 100;
 
 /* Garg: Note there is only LED for charge / power */
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,  2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
 const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
diff --git a/board/gelarshie/base_detect.c b/board/gelarshie/base_detect.c
index a5bbca427b..e045e9ea4f 100644
--- a/board/gelarshie/base_detect.c
+++ b/board/gelarshie/base_detect.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,8 +19,8 @@
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
 /* Base detection and debouncing */
 #define BASE_DETECT_EN_DEBOUNCE_US (350 * MSEC)
@@ -93,8 +93,8 @@ static uint32_t pulse_width;
 
 static void print_base_detect_value(int v, int tmp_pulse_width)
 {
-	CPRINTS("%s = %d (pulse %d)", adc_channels[ADC_BASE_DET].name,
-			v, tmp_pulse_width);
+	CPRINTS("%s = %d (pulse %d)", adc_channels[ADC_BASE_DET].name, v,
+		tmp_pulse_width);
 }
 
 static void base_detect_deferred(void)
@@ -144,12 +144,12 @@ void base_detect_interrupt(enum gpio_signal signal)
 {
 	uint64_t time_now = get_time().val;
 	int debounce_us;
-	
+
 	if (detect_pin_connected(signal))
 		debounce_us = BASE_DETECT_EN_DEBOUNCE_US;
-        else
+	else
 		debounce_us = BASE_DETECT_DIS_DEBOUNCE_US;
-  
+
 	if (base_detect_debounce_time <= time_now) {
 		/*
 		 * Detect and measure detection pin pulse, when base is
@@ -211,7 +211,7 @@ static void base_init(void)
 	if (system_jumped_late() && chipset_in_state(CHIPSET_STATE_ON))
 		base_enable();
 }
-DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT+1);
+DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT + 1);
 
 void base_force_state(enum ec_set_base_state_cmd state)
 {
diff --git a/board/gelarshie/battery.c b/board/gelarshie/battery.c
index 45934366b7..da96b773f8 100644
--- a/board/gelarshie/battery.c
+++ b/board/gelarshie/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/gelarshie/board.c b/board/gelarshie/board.c
index b16e2f823f..11346a3c7d 100644
--- a/board/gelarshie/board.c
+++ b/board/gelarshie/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -37,10 +37,10 @@
 #include "task.h"
 #include "usbc_ppc.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define KS_DEBOUNCE_US    (30 * MSEC)  /* Debounce time for kickstand switch */
+#define KS_DEBOUNCE_US (30 * MSEC) /* Debounce time for kickstand switch */
 
 /* Forward declaration */
 static void tcpc_alert_event(enum gpio_signal signal);
@@ -149,8 +149,7 @@ static void ks_change_deferred(void)
 	proximity_detected = !(ks_attached && ks_open);
 	CPRINTS("ks %s %s -> proximity %s",
 		ks_attached ? "attached" : "detached",
-		ks_open ? "open" : "close",
-		proximity_detected ? "on" : "off");
+		ks_open ? "open" : "close", proximity_detected ? "on" : "off");
 
 	debounced_ks_attached = ks_attached;
 	debounced_ks_open = ks_open;
@@ -172,41 +171,31 @@ static void switchcap_interrupt(enum gpio_signal signal)
 
 /* I2C port map */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl  = GPIO_EC_I2C_POWER_SCL,
-		.sda  = GPIO_EC_I2C_POWER_SDA
-	},
-	{
-		.name = "tcpc0",
-		.port = I2C_PORT_TCPC0,
-		.kbps = 1000,
-		.scl  = GPIO_EC_I2C_USB_C0_PD_SCL,
-		.sda  = GPIO_EC_I2C_USB_C0_PD_SDA
-	},
-	{
-		.name = "tcpc1",
-		.port = I2C_PORT_TCPC1,
-		.kbps = 1000,
-		.scl  = GPIO_EC_I2C_USB_C1_PD_SCL,
-		.sda  = GPIO_EC_I2C_USB_C1_PD_SDA
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_EEPROM_SCL,
-		.sda  = GPIO_EC_I2C_EEPROM_SDA
-	},
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_SENSOR_SCL,
-		.sda  = GPIO_EC_I2C_SENSOR_SDA
-	},
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_POWER_SCL,
+	  .sda = GPIO_EC_I2C_POWER_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C0_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C0_PD_SDA },
+	{ .name = "tcpc1",
+	  .port = I2C_PORT_TCPC1,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C1_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C1_PD_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_EEPROM_SCL,
+	  .sda = GPIO_EC_I2C_EEPROM_SDA },
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_SENSOR_SCL,
+	  .sda = GPIO_EC_I2C_SENSOR_SDA },
 };
 
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
@@ -214,45 +203,25 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* Measure VBUS through a 1/10 voltage divider */
-	[ADC_VBUS] = {
-		"VBUS",
-		NPCX_ADC_CH1,
-		ADC_MAX_VOLT * 10,
-		ADC_READ_MAX + 1,
-		0
-	},
+	[ADC_VBUS] = { "VBUS", NPCX_ADC_CH1, ADC_MAX_VOLT * 10,
+		       ADC_READ_MAX + 1, 0 },
 	/*
 	 * Adapter current output or battery charging/discharging current (uV)
 	 * 18x amplification on charger side.
 	 */
-	[ADC_AMON_BMON] = {
-		"AMON_BMON",
-		NPCX_ADC_CH2,
-		ADC_MAX_VOLT * 1000 / 18,
-		ADC_READ_MAX + 1,
-		0
-	},
+	[ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH2, ADC_MAX_VOLT * 1000 / 18,
+			    ADC_READ_MAX + 1, 0 },
 	/*
 	 * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read
 	 * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and
 	 * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we
 	 * only divide by 2 (enough to avoid precision issues).
 	 */
-	[ADC_PSYS] = {
-		"PSYS",
-		NPCX_ADC_CH3,
-		ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1),
-		2,
-		0
-	},
+	[ADC_PSYS] = { "PSYS", NPCX_ADC_CH3,
+		       ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), 2, 0 },
 	/* Base detection */
-	[ADC_BASE_DET] = {
-		"BASE_DET",
-		NPCX_ADC_CH5,
-		ADC_MAX_VOLT,
-		ADC_READ_MAX + 1,
-		0
-	},
+	[ADC_BASE_DET] = { "BASE_DET", NPCX_ADC_CH5, ADC_MAX_VOLT,
+			   ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
@@ -270,16 +239,12 @@ const struct ln9310_config_t ln9310_config = {
 
 /* Power Path Controller */
 struct ppc_config_t ppc_chips[] = {
-	{
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	{
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
+	{ .i2c_port = I2C_PORT_TCPC0,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
+	{ .i2c_port = I2C_PORT_TCPC1,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
 };
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
@@ -310,16 +275,22 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
  * to AP. But the TCPC chip is also needed to know the HPD status; otherwise,
  * the mux misbehaves.
  */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	},
 	{
-		.usb_port = 1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	}
 };
 
@@ -344,11 +315,9 @@ static struct bmi_drv_data_t g_bmi260_data;
 bool is_bmi260_present;
 
 /* Matrix to rotate accelerometer into standard reference frame */
-const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+				      { FLOAT_TO_FP(1), 0, 0 },
+				      { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	/*
@@ -451,8 +420,8 @@ static void board_detect_motionsensor(void)
 
 	/* Check base accelgyro chip */
 	bmi_read8(motion_sensors[LID_ACCEL].port,
-		motion_sensors[LID_ACCEL].i2c_spi_addr_flags,
-		BMI260_CHIP_ID, &val);
+		  motion_sensors[LID_ACCEL].i2c_spi_addr_flags, BMI260_CHIP_ID,
+		  &val);
 	if (val == BMI260_CHIP_ID_MAJOR) {
 		motion_sensors[LID_ACCEL] = motion_sensors_260[LID_ACCEL];
 		motion_sensors[LID_GYRO] = motion_sensors_260[LID_GYRO];
@@ -553,9 +522,9 @@ void board_tcpc_init(void)
 	 */
 	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
 		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
 
 void board_hibernate(void)
 {
@@ -565,8 +534,7 @@ void board_hibernate(void)
 	 * Sensors are unpowered in hibernate. Apply PD to the
 	 * interrupt lines such that they don't float.
 	 */
-	gpio_set_flags(GPIO_ACCEL_GYRO_INT_L,
-		       GPIO_INPUT | GPIO_PULL_DOWN);
+	gpio_set_flags(GPIO_ACCEL_GYRO_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
 
 	/*
 	 * Board rev 1+ has the hardware fix. Don't need the following
@@ -663,8 +631,7 @@ void board_overcurrent_event(int port, int is_overcurrented)
 
 int board_set_active_charge_port(int port)
 {
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	int i;
 
 	if (!is_real_port && port != CHARGE_PORT_NONE)
@@ -692,7 +659,6 @@ int board_set_active_charge_port(int port)
 		return EC_ERROR_INVAL;
 	}
 
-
 	CPRINTS("New charge port: p%d", port);
 
 	/*
@@ -716,24 +682,22 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	/*
 	 * Ignore lower charge ceiling on PD transition if our battery is
 	 * critical, as we may brownout.
 	 */
-	if (supplier == CHARGE_SUPPLIER_PD &&
-	    charge_ma < 1500 &&
+	if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 &&
 	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
 		CPRINTS("Using max ilim %d", max_ma);
 		charge_ma = max_ma;
 	}
 
 	charge_ma = charge_ma * 95 / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 uint16_t tcpc_get_alert_status(void)
diff --git a/board/gelarshie/board.h b/board/gelarshie/board.h
index 45b8c42dcc..7e27c7a62f 100644
--- a/board/gelarshie/board.h
+++ b/board/gelarshie/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,7 +12,7 @@
 
 /* On-body detection */
 #define CONFIG_BODY_DETECTION
-#define CONFIG_BODY_DETECTION_SENSOR           LID_ACCEL
+#define CONFIG_BODY_DETECTION_SENSOR LID_ACCEL
 #define CONFIG_BODY_DETECTION_VAR_NOISE_FACTOR 150 /* % */
 #define CONFIG_GESTURE_DETECTION
 #define CONFIG_GESTURE_DETECTION_MASK BIT(CONFIG_BODY_DETECTION_SENSOR)
@@ -21,7 +21,7 @@
 #define CONFIG_BUTTON_TRIGGERED_RECOVERY
 
 /* Internal SPI flash on NPCX7 */
-#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)  /* 512KB internal spi flash */
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */
 
 /* Switchcap */
 #define CONFIG_LN9310
@@ -37,7 +37,7 @@
 #undef CONFIG_CMD_TASK_RESET
 
 /* Battery */
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY  "LION"
+#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
 #define CONFIG_BATTERY_REVIVE_DISCONNECT
 #define CONFIG_BATTERY_FUEL_GAUGE
 #define CONFIG_BATTERY_VENDOR_PARAM
@@ -103,10 +103,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_DISPLIGHT = 0,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_DISPLIGHT = 0, PWM_CH_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
diff --git a/board/gelarshie/build.mk b/board/gelarshie/build.mk
index 84616b4e1c..5b0f734fda 100644
--- a/board/gelarshie/build.mk
+++ b/board/gelarshie/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/gelarshie/ec.tasklist b/board/gelarshie/ec.tasklist
index 0d861dda25..7d193fecf3 100644
--- a/board/gelarshie/ec.tasklist
+++ b/board/gelarshie/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/gelarshie/gpio.inc b/board/gelarshie/gpio.inc
index cb0f842102..189a9657a6 100644
--- a/board/gelarshie/gpio.inc
+++ b/board/gelarshie/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2022 The Chromium OS Authors. All rights reserved.
+ * Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/gelarshie/led.c b/board/gelarshie/led.c
index 0a6c85be6d..e401787f7f 100644
--- a/board/gelarshie/led.c
+++ b/board/gelarshie/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -35,15 +35,15 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_BLUE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static void led_set_color(enum led_color color)
 {
 	gpio_set_level(GPIO_EC_CHG_LED_Y_C0,
-		(color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
+		       (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
 	gpio_set_level(GPIO_EC_CHG_LED_W_C0,
-		(color == LED_BLUE) ? BAT_LED_ON : BAT_LED_OFF);
+		       (color == LED_BLUE) ? BAT_LED_ON : BAT_LED_OFF);
 }
 
 void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
@@ -69,7 +69,6 @@ static void board_led_set_battery(void)
 	static int battery_ticks;
 	int color = LED_OFF;
 	int period = 0;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
@@ -84,16 +83,15 @@ static void board_led_set_battery(void)
 			period = (1 + 1) * LED_ONE_SEC;
 			battery_ticks = battery_ticks % period;
 			if (battery_ticks < 1 * LED_ONE_SEC) {
-				if (charge_get_percent() < 10)
-                                {
-                                	/* Blink amber light (1 sec on, 1 sec off) */
+				if (charge_get_percent() < 10) {
+					/* Blink amber light (1 sec on, 1 sec
+					 * off) */
 					color = LED_AMBER;
-                                }
-				else
-                                {
-                                	/* Blink white light (1 sec on, 1 sec off) */
+				} else {
+					/* Blink white light (1 sec on, 1 sec
+					 * off) */
 					color = LED_BLUE;
-                                }
+				}
 			} else {
 				color = LED_OFF;
 			}
@@ -138,16 +136,16 @@ static void board_led_set_battery(void)
 		}
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE) {
-			/* Factory mode: Blue 2 sec, Amber 2 sec */
-			period = (2 + 2) * LED_ONE_SEC;
-			battery_ticks = battery_ticks % period;
-			if (battery_ticks < 2 * LED_ONE_SEC)
-				color = LED_BLUE;
-			else
-				color = LED_AMBER;
-		} else
+		color = LED_BLUE;
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		/* Factory mode: Blue 2 sec, Amber 2 sec */
+		period = (2 + 2) * LED_ONE_SEC;
+		battery_ticks = battery_ticks % period;
+		if (battery_ticks < 2 * LED_ONE_SEC)
 			color = LED_BLUE;
+		else
+			color = LED_AMBER;
 		break;
 	default:
 		/* Other states don't alter LED behavior */
diff --git a/board/gelarshie/usbc_config.c b/board/gelarshie/usbc_config.c
index 86a2f4663f..7389f8cb52 100644
--- a/board/gelarshie/usbc_config.c
+++ b/board/gelarshie/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,8 @@
 #include "gpio.h"
 #include "usb_pd.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 const struct charger_config_t chg_chips[] = {
 	{
diff --git a/board/genesis/board.c b/board/genesis/board.c
index 5305c8d630..5c3f1c5c00 100644
--- a/board/genesis/board.c
+++ b/board/genesis/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -36,8 +36,8 @@
 #include "usb_common.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
 static void power_monitor(void);
 DECLARE_DEFERRED(power_monitor);
@@ -49,14 +49,14 @@ static int32_t base_5v_power;
  * Power usage for each port as measured or estimated.
  * Units are milliwatts (5v x ma current)
  */
-#define PWR_BASE_LOAD	(5*1335)
-#define PWR_FRONT_HIGH	(5*1500)
-#define PWR_FRONT_LOW	(5*900)
-#define PWR_REAR	(5*1500)
-#define PWR_HDMI	(5*562)
-#define PWR_C_HIGH	(5*3740)
-#define PWR_C_LOW	(5*2090)
-#define PWR_MAX		(5*10000)
+#define PWR_BASE_LOAD (5 * 1335)
+#define PWR_FRONT_HIGH (5 * 1500)
+#define PWR_FRONT_LOW (5 * 900)
+#define PWR_REAR (5 * 1500)
+#define PWR_HDMI (5 * 562)
+#define PWR_C_HIGH (5 * 3740)
+#define PWR_C_LOW (5 * 2090)
+#define PWR_MAX (5 * 10000)
 
 /*
  * Update the 5V power usage, assuming no throttling,
@@ -112,69 +112,56 @@ static void port_ocp_interrupt(enum gpio_signal signal)
 
 /******************************************************************************/
 /* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
+const struct spi_device_t spi_devices[] = {};
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
 /******************************************************************************/
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN]        = { .channel = 5,
-				.flags = PWM_CONFIG_OPEN_DRAIN,
-				.freq = 25000},
-	[PWM_CH_LED_RED]    = { .channel = 0,
-				.flags = PWM_CONFIG_DSLEEP,
-				.freq = 2000 },
-	[PWM_CH_LED_WHITE]  = { .channel = 2,
-				.flags = PWM_CONFIG_DSLEEP,
-				.freq = 2000 },
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
+	[PWM_CH_LED_RED] = { .channel = 0,
+			     .flags = PWM_CONFIG_DSLEEP,
+			     .freq = 2000 },
+	[PWM_CH_LED_WHITE] = { .channel = 2,
+			       .flags = PWM_CONFIG_DSLEEP,
+			       .freq = 2000 },
 };
 
 /******************************************************************************/
 /* I2C port map configuration */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "ina",
-		.port = I2C_PORT_INA,
-		.kbps = 400,
-		.scl  = GPIO_I2C0_SCL,
-		.sda  = GPIO_I2C0_SDA
-	},
-	{
-		.name = "ppc0",
-		.port = I2C_PORT_PPC0,
-		.kbps = 400,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	},
-	{
-		.name = "tcpc0",
-		.port = I2C_PORT_TCPC0,
-		.kbps = 400,
-		.scl  = GPIO_I2C3_SCL,
-		.sda  = GPIO_I2C3_SDA
-	},
-	{
-		.name = "pse",
-		.port = I2C_PORT_PSE,
-		.kbps = 400,
-		.scl  = GPIO_I2C4_SCL,
-		.sda  = GPIO_I2C4_SDA
-	},
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 400,
-		.scl  = GPIO_I2C5_SCL,
-		.sda  = GPIO_I2C5_SDA
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl  = GPIO_I2C7_SCL,
-		.sda  = GPIO_I2C7_SDA
-	},
+	{ .name = "ina",
+	  .port = I2C_PORT_INA,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_SCL,
+	  .sda = GPIO_I2C0_SDA },
+	{ .name = "ppc0",
+	  .port = I2C_PORT_PPC0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
+	{ .name = "pse",
+	  .port = I2C_PORT_PSE,
+	  .kbps = 400,
+	  .scl = GPIO_I2C4_SCL,
+	  .sda = GPIO_I2C4_SDA },
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 400,
+	  .scl = GPIO_I2C5_SCL,
+	  .sda = GPIO_I2C5_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_I2C7_SCL,
+	  .sda = GPIO_I2C7_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -230,15 +217,14 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
 /******************************************************************************/
 /* Wake up pins */
-const enum gpio_signal hibernate_wake_pins[] = {
-};
+const enum gpio_signal hibernate_wake_pins[] = {};
 const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 
 /******************************************************************************/
 /* Physical fans. These are logically separate from pwm_channels. */
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = -1,
 };
@@ -257,7 +243,7 @@ BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
 /******************************************************************************/
 /* MFT channels. These are logically separate from pwm_channels. */
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN },
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
@@ -266,8 +252,8 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_A \
-	{ \
+#define THERMAL_A                \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = 0, \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(78), \
@@ -420,23 +406,23 @@ void board_enable_s0_rails(int enable)
  *
  *  All measurements are in milliwatts.
  */
-#define THROT_TYPE_A		BIT(0)
-#define THROT_TYPE_C		BIT(1)
-#define THROT_PROCHOT		BIT(2)
+#define THROT_TYPE_A BIT(0)
+#define THROT_TYPE_C BIT(1)
+#define THROT_PROCHOT BIT(2)
 
 /*
  * Power gain if front USB A ports are limited.
  */
-#define POWER_GAIN_TYPE_A	3200
+#define POWER_GAIN_TYPE_A 3200
 /*
  * Power gain if Type C port is limited.
  */
-#define POWER_GAIN_TYPE_C	8800
+#define POWER_GAIN_TYPE_C 8800
 /*
  * Power is averaged over 10 ms, with a reading every 2 ms.
  */
-#define POWER_DELAY_MS		2
-#define POWER_READINGS		(10/POWER_DELAY_MS)
+#define POWER_DELAY_MS 2
+#define POWER_READINGS (10 / POWER_DELAY_MS)
 
 static void power_monitor(void)
 {
@@ -449,8 +435,7 @@ static void power_monitor(void)
 	 * If CPU is off or suspended, no need to throttle
 	 * or restrict power.
 	 */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF |
-			     CHIPSET_STATE_SUSPEND)) {
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF | CHIPSET_STATE_SUSPEND)) {
 		/*
 		 * Slow down monitoring, assume no throttling required.
 		 */
diff --git a/board/genesis/board.h b/board/genesis/board.h
index 9c9233590e..41de23b6a8 100644
--- a/board/genesis/board.h
+++ b/board/genesis/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,8 +12,8 @@
 #define CONFIG_UART_TX_BUF_SIZE 4096
 
 /* NPCX7 config */
-#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
-#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
+#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */
+#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */
 
 /* Internal SPI flash on NPCX796FC is 512 kB */
 #define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
@@ -40,7 +40,7 @@
 #undef CONFIG_HIBERNATE
 #define CONFIG_HOST_INTERFACE_ESPI
 #define CONFIG_LED_COMMON
-#undef  CONFIG_LID_SWITCH
+#undef CONFIG_LID_SWITCH
 #define CONFIG_LTO
 #define CONFIG_PWM
 #define CONFIG_VBOOT_EFS2
@@ -118,13 +118,13 @@
 /* I2C Bus Configuration */
 #define CONFIG_I2C
 #define CONFIG_I2C_CONTROLLER
-#define I2C_PORT_INA		NPCX_I2C_PORT0_0
-#define I2C_PORT_PPC0		NPCX_I2C_PORT1_0
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT3_0
-#define I2C_PORT_PSE		NPCX_I2C_PORT4_1
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_PORT_INA NPCX_I2C_PORT0_0
+#define I2C_PORT_PPC0 NPCX_I2C_PORT1_0
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT3_0
+#define I2C_PORT_PSE NPCX_I2C_PORT4_1
+#define I2C_PORT_POWER NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 
 #define PP5000_PGOOD_POWER_SIGNAL_MASK POWER_SIGNAL_MASK(PP5000_A_PGOOD)
 
@@ -134,11 +134,11 @@
 #include "registers.h"
 
 enum adc_channel {
-	ADC_SNS_PP3300,     /* ADC2 */
-	ADC_SNS_PP1050,     /* ADC7 */
-	ADC_VBUS,           /* ADC4 */
-	ADC_PPVAR_IMON,     /* ADC9 */
-	ADC_TEMP_SENSOR_1,  /* ADC0 */
+	ADC_SNS_PP3300, /* ADC2 */
+	ADC_SNS_PP1050, /* ADC7 */
+	ADC_VBUS, /* ADC4 */
+	ADC_PPVAR_IMON, /* ADC9 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
 	/* Number of ADC channels */
 	ADC_CH_COUNT
 };
@@ -163,11 +163,7 @@ enum mft_channel {
 	MFT_CH_COUNT,
 };
 
-enum temp_sensor_id {
-	TEMP_SENSOR_CORE,
-	TEMP_SENSOR_COUNT
-};
-
+enum temp_sensor_id { TEMP_SENSOR_CORE, TEMP_SENSOR_COUNT };
 
 /* Board specific handlers */
 void led_alert(int enable);
@@ -179,20 +175,20 @@ void show_critical_error(void);
 /*
  * Barrel-jack power (4 bits).
  */
-#define EC_CFG_BJ_POWER_L		0
-#define EC_CFG_BJ_POWER_H		3
+#define EC_CFG_BJ_POWER_L 0
+#define EC_CFG_BJ_POWER_H 3
 #define EC_CFG_BJ_POWER_MASK GENMASK(EC_CFG_BJ_POWER_H, EC_CFG_BJ_POWER_L)
 /*
  * USB Connector 4 not present (1 bit).
  */
-#define EC_CFG_NO_USB4_L		4
-#define EC_CFG_NO_USB4_H		4
+#define EC_CFG_NO_USB4_L 4
+#define EC_CFG_NO_USB4_H 4
 #define EC_CFG_NO_USB4_MASK GENMASK(EC_CFG_NO_USB4_H, EC_CFG_NO_USB4_L)
 /*
  * Thermal solution config (3 bits).
  */
-#define EC_CFG_THERMAL_L		5
-#define EC_CFG_THERMAL_H		7
+#define EC_CFG_THERMAL_L 5
+#define EC_CFG_THERMAL_H 7
 #define EC_CFG_THERMAL_MASK GENMASK(EC_CFG_THERMAL_H, EC_CFG_THERMAL_L)
 
 unsigned int ec_config_get_thermal_solution(void);
@@ -200,30 +196,30 @@ unsigned int ec_config_get_thermal_solution(void);
 #endif /* !__ASSEMBLER__ */
 
 /* Pin renaming */
-#define GPIO_WP_L               GPIO_EC_WP_ODL
-#define GPIO_PP5000_A_PG_OD     GPIO_PG_PP5000_A_OD
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
-#define GPIO_RECOVERY_L         GPIO_EC_RECOVERY_BTN_ODL
-#define GPIO_RECOVERY_L_2       GPIO_H1_EC_RECOVERY_BTN_ODL
-#define GPIO_POWER_BUTTON_L	GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_PCH_WAKE_L		GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L	GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_ENTERING_RW	GPIO_EC_ENTERING_RW
-#define GPIO_SYS_RESET_L	GPIO_SYS_RST_ODL
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_PCH_RTCRST		GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_TEMP_SENSOR_POWER	GPIO_EN_ROA_RAILS
-#define GPIO_AC_PRESENT		GPIO_BJ_ADP_PRESENT_L
+#define GPIO_WP_L GPIO_EC_WP_ODL
+#define GPIO_PP5000_A_PG_OD GPIO_PG_PP5000_A_OD
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
+#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_ODL
+#define GPIO_RECOVERY_L_2 GPIO_H1_EC_RECOVERY_BTN_ODL
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_EN_ROA_RAILS
+#define GPIO_AC_PRESENT GPIO_BJ_ADP_PRESENT_L
 
 /*
  * There is no RSMRST input, so alias it to the output. This short-circuits
  * common_intel_x86_handle_rsmrst.
  */
-#define GPIO_PG_EC_RSMRST_ODL	GPIO_PCH_RSMRST_L
+#define GPIO_PG_EC_RSMRST_ODL GPIO_PCH_RSMRST_L
 
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/genesis/build.mk b/board/genesis/build.mk
index 2785133e11..50d3763d2b 100644
--- a/board/genesis/build.mk
+++ b/board/genesis/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/genesis/ec.tasklist b/board/genesis/ec.tasklist
index 3828142c55..c43d643410 100644
--- a/board/genesis/ec.tasklist
+++ b/board/genesis/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/genesis/gpio.inc b/board/genesis/gpio.inc
index d8f2989b8e..7d2c33c5a9 100644
--- a/board/genesis/gpio.inc
+++ b/board/genesis/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,12 +25,12 @@ GPIO_INT(PG_VPRIM_CORE_A_OD,   PIN(2, 3), GPIO_INT_BOTH, power_signal_interrupt)
 GPIO_INT(PG_PP1050_A_OD,       PIN(2, 2), GPIO_INT_BOTH, power_signal_interrupt)
 /* EC output, but also interrupt so this can be polled as a power signal */
 GPIO_INT(EC_PCH_RSMRST_L,      PIN(A, 6), GPIO_OUTPUT | GPIO_INT_F_RISING | GPIO_INT_F_FALLING, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(PG_PP2500_DRAM_U_OD,  PIN(2, 0), GPIO_INT_BOTH, power_signal_interrupt)
 GPIO_INT(PG_PP1200_U_OD,       PIN(2, 1), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, slp_s3_interrupt)
 #endif
 GPIO_INT(PG_PP950_VCCIO_OD,    PIN(1, 7), GPIO_INT_BOTH, power_signal_interrupt)
diff --git a/board/genesis/led.c b/board/genesis/led.c
index c562dff27e..9258b6eb6d 100644
--- a/board/genesis/led.c
+++ b/board/genesis/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,16 +19,16 @@
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
 
 /*
  * Due to the CSME-Lite processing, upon startup the CPU transitions through
  * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so
  * delay turning off the LED during suspend/shutdown.
  */
-#define LED_CPU_DELAY_MS	(2000 * MSEC)
+#define LED_CPU_DELAY_MS (2000 * MSEC)
 
-const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 enum led_color {
@@ -89,9 +89,9 @@ static int set_color(enum ec_led_id id, enum led_color color, int duty)
 	}
 }
 
-#define LED_PULSE_US		(2 * SECOND)
+#define LED_PULSE_US (2 * SECOND)
 /* 40 msec for nice and smooth transition. */
-#define LED_PULSE_TICK_US	(40 * MSEC)
+#define LED_PULSE_TICK_US (40 * MSEC)
 
 /* When pulsing is enabled, brightness is incremented by <duty_inc> every
  * <interval> usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented
@@ -223,7 +223,7 @@ void show_critical_error(void)
 		set_color(EC_LED_ID_POWER_LED, LED_RED, 100);
 }
 
-static int command_led(int argc, char **argv)
+static int command_led(int argc, const char **argv)
 {
 	enum ec_led_id id = EC_LED_ID_POWER_LED;
 
diff --git a/board/genesis/pse.c b/board/genesis/pse.c
index 671288ccf5..bda7e1994d 100644
--- a/board/genesis/pse.c
+++ b/board/genesis/pse.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,44 +18,44 @@
 #include "timer.h"
 #include "util.h"
 
-#define LTC4291_I2C_ADDR	0x2C
-
-#define LTC4291_REG_SUPEVN_COR	0x0B
-#define LTC4291_REG_STATPWR	0x10
-#define LTC4291_REG_STATPIN	0x11
-#define LTC4291_REG_OPMD	0x12
-#define LTC4291_REG_DISENA	0x13
-#define LTC4291_REG_DETENA	0x14
-#define LTC4291_REG_DETPB	0x18
-#define LTC4291_REG_PWRPB	0x19
-#define LTC4291_REG_RSTPB	0x1A
-#define LTC4291_REG_ID		0x1B
-#define LTC4291_REG_DEVID	0x43
-#define LTC4291_REG_HPMD1	0x46
-#define LTC4291_REG_HPMD2	0x4B
-#define LTC4291_REG_HPMD3	0x50
-#define LTC4291_REG_HPMD4	0x55
-#define LTC4291_REG_LPWRPB	0x6E
-
-#define LTC4291_FLD_STATPIN_AUTO	BIT(0)
-#define LTC4291_FLD_RSTPB_RSTALL	BIT(4)
-
-#define LTC4291_STATPWR_ON_PORT(port)	(0x01 << (port))
-#define LTC4291_DETENA_EN_PORT(port)	(0x11 << (port))
-#define LTC4291_DETPB_EN_PORT(port)	(0x11 << (port))
-#define LTC4291_PWRPB_OFF_PORT(port)	(0x10 << (port))
-
-#define LTC4291_OPMD_AUTO	0xFF
-#define LTC4291_DISENA_ALL	0x0F
-#define LTC4291_DETENA_ALL	0xFF
-#define LTC4291_ID		0x64
-#define LTC4291_DEVID		0x38
-#define LTC4291_HPMD_MIN	0x00
-#define LTC4291_HPMD_MAX	0xA8
-
-#define LTC4291_PORT_MAX	4
-
-#define LTC4291_RESET_DELAY_US	(20 * MSEC)
+#define LTC4291_I2C_ADDR 0x2C
+
+#define LTC4291_REG_SUPEVN_COR 0x0B
+#define LTC4291_REG_STATPWR 0x10
+#define LTC4291_REG_STATPIN 0x11
+#define LTC4291_REG_OPMD 0x12
+#define LTC4291_REG_DISENA 0x13
+#define LTC4291_REG_DETENA 0x14
+#define LTC4291_REG_DETPB 0x18
+#define LTC4291_REG_PWRPB 0x19
+#define LTC4291_REG_RSTPB 0x1A
+#define LTC4291_REG_ID 0x1B
+#define LTC4291_REG_DEVID 0x43
+#define LTC4291_REG_HPMD1 0x46
+#define LTC4291_REG_HPMD2 0x4B
+#define LTC4291_REG_HPMD3 0x50
+#define LTC4291_REG_HPMD4 0x55
+#define LTC4291_REG_LPWRPB 0x6E
+
+#define LTC4291_FLD_STATPIN_AUTO BIT(0)
+#define LTC4291_FLD_RSTPB_RSTALL BIT(4)
+
+#define LTC4291_STATPWR_ON_PORT(port) (0x01 << (port))
+#define LTC4291_DETENA_EN_PORT(port) (0x11 << (port))
+#define LTC4291_DETPB_EN_PORT(port) (0x11 << (port))
+#define LTC4291_PWRPB_OFF_PORT(port) (0x10 << (port))
+
+#define LTC4291_OPMD_AUTO 0xFF
+#define LTC4291_DISENA_ALL 0x0F
+#define LTC4291_DETENA_ALL 0xFF
+#define LTC4291_ID 0x64
+#define LTC4291_DEVID 0x38
+#define LTC4291_HPMD_MIN 0x00
+#define LTC4291_HPMD_MAX 0xA8
+
+#define LTC4291_PORT_MAX 4
+
+#define LTC4291_RESET_DELAY_US (20 * MSEC)
 
 #define I2C_PSE_READ(reg, data) \
 	i2c_read8(I2C_PORT_PSE, LTC4291_I2C_ADDR, LTC4291_REG_##reg, (data))
@@ -63,7 +63,7 @@
 #define I2C_PSE_WRITE(reg, data) \
 	i2c_write8(I2C_PORT_PSE, LTC4291_I2C_ADDR, LTC4291_REG_##reg, (data))
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 static int pse_write_hpmd(int port, int val)
 {
@@ -173,7 +173,7 @@ DECLARE_HOOK(HOOK_CHIPSET_RESUME, pse_init, HOOK_PRIO_DEFAULT);
 /* Also reset the PSE on a reboot to toggle the power. */
 DECLARE_HOOK(HOOK_CHIPSET_RESET, pse_init, HOOK_PRIO_DEFAULT);
 
-static int command_pse(int argc, char **argv)
+static int command_pse(int argc, const char **argv)
 {
 	int port;
 
@@ -205,8 +205,7 @@ static int command_pse(int argc, char **argv)
 	else
 		return EC_ERROR_PARAM2;
 }
-DECLARE_CONSOLE_COMMAND(pse, command_pse,
-			"<port# 0-3> <off | on | min | max>",
+DECLARE_CONSOLE_COMMAND(pse, command_pse, "<port# 0-3> <off | on | min | max>",
 			"Set PSE port power");
 
 static int ec_command_pse_status(int port, uint8_t *status)
diff --git a/board/ghost/battery.c b/board/ghost/battery.c
deleted file mode 100644
index 50086b6c86..0000000000
--- a/board/ghost/battery.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery.h"
-#include "battery_fuel_gauge.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "gpio.h"
-#include "gpio_signal.h"
-
-/*
- * Battery info for all Ghost battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* POW-TECH GQA05 Battery Information */
-	[BATTERY_POWER_TECH] = {
-		/* BQ40Z50 Fuel Gauge */
-		.fuel_gauge = {
-			.manuf_name = "POW-TECH",
-			.device_name = "BATGQA05L22",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x00,
-				.reg_mask = 0x2000,		/* XDSG */
-				.disconnect_val = 0x2000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= TARGET_WITH_MARGIN(13050, 5),
-			.voltage_normal		= 11400, /* mV */
-			.voltage_min		= 9000, /* mV */
-			.precharge_current	= 280,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 45,
-			.discharging_min_c	= -10,
-			.discharging_max_c	= 60,
-		},
-	},
-	/*
-	 * TODO(b/233120385): verify these
-	 */
-	[BATTERY_SWD_ATL] = {
-		/* BQ40Z50-R3 Fuel Gauge */
-		.fuel_gauge = {
-			.manuf_name = "SWD",
-			.device_name = "1163985013",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x00,
-				.reg_mask = 0x2000,		/* XDSG */
-				.disconnect_val = 0x2000,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= TARGET_WITH_MARGIN(8960, 5),
-			.voltage_normal		= 7780, /* mV */
-			.voltage_min		= 6000, /* mV */
-			.precharge_current	= 570,	/* mA */
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 60,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= -20,
-			.discharging_max_c	= 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_POWER_TECH;
-
-enum battery_present battery_hw_present(void)
-{
-	enum gpio_signal batt_pres;
-
-	batt_pres = GPIO_EC_BATT_PRES_ODL;
-
-	/* The GPIO is low when the battery is physically present */
-	return gpio_get_level(batt_pres) ? BP_NO : BP_YES;
-}
diff --git a/board/ghost/board.c b/board/ghost/board.c
deleted file mode 100644
index d156a78975..0000000000
--- a/board/ghost/board.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "gpio.h"
-#include "hooks.h"
-#include "lid_switch.h"
-#include "power_button.h"
-#include "power.h"
-#include "switch.h"
-#include "throttle_ap.h"
-
-#include "gpio_list.h" /* Must come after other header files. */
-
-/* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-
-/* Called on AP S3 -> S0 transition */
-static void board_chipset_resume(void)
-{
-	/* Allow keyboard backlight to be enabled */
-
-	gpio_set_level(GPIO_EC_KB_BL_EN, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0 -> S3 transition */
-static void board_chipset_suspend(void)
-{
-	/* Turn off the keyboard backlight if it's on. */
-
-	gpio_set_level(GPIO_EC_KB_BL_EN, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
diff --git a/board/ghost/board.h b/board/ghost/board.h
deleted file mode 100644
index 79be17ac2f..0000000000
--- a/board/ghost/board.h
+++ /dev/null
@@ -1,192 +0,0 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Ghost board configuration */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#include "compile_time_macros.h"
-
-/*
- * Early ghost boards are not set up for vivaldi
- */
-#undef CONFIG_KEYBOARD_VIVALDI
-
-/* Baseboard features */
-#include "baseboard.h"
-
-/*
- * TODO(b/230813416): remove after bringup
- */
-#define CONFIG_BRINGUP
-
-/* Buttons are not supported */
-#undef CONFIG_VOLUME_BUTTONS
-#undef CONFIG_MKBP_INPUT_DEVICES
-
-/* Tablet mode is not supported */
-#undef CONFIG_TABLET_MODE
-#undef CONFIG_TABLET_MODE_SWITCH
-#undef CONFIG_LID_ANGLE
-
-/* BC1.2 is not supported */
-#undef CONFIG_USB_CHARGER
-#undef CONFIG_BC12_SINGLE_DRIVER
-#undef CONFIG_BC12_DETECT_PI3USB9201
-
-#define CONFIG_MP2964
-
-/* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
-
-#define CONFIG_IO_EXPANDER
-#define CONFIG_IO_EXPANDER_NCT38XX
-#define CONFIG_IO_EXPANDER_PORT_COUNT		2
-
-#define CONFIG_USB_PD_FRS_PPC
-
-#define CONFIG_USBC_RETIMER_INTEL_BB
-
-#define CONFIG_USBC_PPC_SYV682X
-
-/* TODO: b/177608416 - measure and check these values on brya */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
-
-/*
- * Passive USB-C cables only support up to 60W.
- */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
-
-/*
- * Macros for GPIO signals used in common code that don't match the
- * schematic names. Signal names in gpio.inc match the schematic and are
- * then redefined here to so it's more clear which signal is being used for
- * which purpose.
- */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT		GPIO_EC_EN_EDP_BL
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_GSC_PACKET_MODE
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SYS_SLP_S0IX_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_TEMP_SENSOR_POWER		GPIO_SEQ_EC_DSW_PWROK
-
-/*
- * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
- * signal.
- */
-#define GPIO_IMVP9_VRRDY_OD		GPIO_IMVP91_VRRDY_OD
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_SEQ_EC_ALL_SYS_PG
-#define GPIO_PG_EC_DSW_PWROK		GPIO_SEQ_EC_DSW_PWROK
-#define GPIO_PG_EC_RSMRST_ODL		GPIO_SEQ_EC_RSMRST_ODL
-#define GPIO_POWER_BUTTON_L		GPIO_GSC_EC_PWR_BTN_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_ODL
-
-/* System has back-lit keyboard */
-#define CONFIG_PWM_KBLIGHT
-
-/* I2C Bus Configuration */
-
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-
-#define I2C_PORT_USB_C0_C1_TCPC	NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C0_C1_PPC	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C0_RT	NPCX_I2C_PORT3_0
-#define I2C_PORT_USB_C1_RT	NPCX_I2C_PORT6_1
-
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT5_0
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT5_0
-#define I2C_PORT_MISC		NPCX_I2C_PORT7_0
-
-#define I2C_PORT_EEPROM		I2C_PORT_MISC
-#define I2C_PORT_MP2964		I2C_PORT_MISC
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-
-#define I2C_ADDR_MP2964_FLAGS	0x20
-
-#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR	0x57
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x57
-
-/* Enabling Thunderbolt-compatible mode */
-#define CONFIG_USB_PD_TBT_COMPAT_MODE
-
-/* Enabling USB4 mode */
-#define CONFIG_USB_PD_USB4
-
-/* Retimer */
-#define CONFIG_USBC_RETIMER_FW_UPDATE
-
-/* Thermal features */
-#define CONFIG_THERMISTOR
-#define CONFIG_TEMP_SENSOR
-#define CONFIG_TEMP_SENSOR_POWER
-#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
-
-/* Charger defines */
-#define CONFIG_CHARGER_ISL9241
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	20
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"	/* needed by registers.h */
-#include "registers.h"
-#include "usbc_config.h"
-
-enum adc_channel {
-	ADC_TEMP_SENSOR_1_DDR_SOC,
-	ADC_TEMP_SENSOR_2_AMBIENT,
-	ADC_TEMP_SENSOR_3_CHARGER,
-	ADC_TEMP_SENSOR_4_WWAN,
-	ADC_CH_COUNT
-};
-
-enum temp_sensor_id {
-	TEMP_SENSOR_1_DDR_SOC,
-	TEMP_SENSOR_2_AMBIENT,
-	TEMP_SENSOR_3_CHARGER,
-	TEMP_SENSOR_4_WWAN,
-	TEMP_SENSOR_COUNT
-};
-
-enum ioex_port {
-	IOEX_C0_NCT38XX = 0,
-	IOEX_C1_NCT38XX,
-	IOEX_PORT_COUNT
-};
-
-enum battery_type {
-	BATTERY_POWER_TECH,
-	BATTERY_SWD_ATL,
-	BATTERY_TYPE_COUNT
-};
-
-enum pwm_channel {
-	PWM_CH_LED1 = 0,		/* PWM0 */
-	PWM_CH_LED2,			/* PWM1 */
-	PWM_CH_FAN2,			/* PWM2 */
-	PWM_CH_KBLIGHT,			/* PWM3 */
-	PWM_CH_FAN1,			/* PWM5 */
-	PWM_CH_COUNT
-};
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/ghost/charger.c b/board/ghost/charger.c
deleted file mode 100644
index 6e14119a77..0000000000
--- a/board/ghost/charger.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "charger.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "driver/charger/isl9241.h"
-#include "usbc_ppc.h"
-#include "usb_pd.h"
-#include "util.h"
-
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-#ifndef CONFIG_ZEPHYR
-/* Charger Chip Configuration */
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = ISL9241_ADDR_FLAGS,
-		.drv = &isl9241_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CHARGER_NUM);
-#endif
-
-int board_set_active_charge_port(int port)
-{
-	int is_valid_port = board_is_usb_pd_port_present(port);
-	int i;
-
-	if (port == CHARGE_PORT_NONE) {
-		CPRINTSUSB("Disabling all charger ports");
-
-		/* Disable all ports. */
-		for (i = 0; i < ppc_cnt; i++) {
-			/*
-			 * Do not return early if one fails otherwise we can
-			 * get into a boot loop assertion failure.
-			 */
-			if (ppc_vbus_sink_enable(i, 0))
-				CPRINTSUSB("Disabling C%d as sink failed.", i);
-		}
-
-		return EC_SUCCESS;
-	} else if (!is_valid_port) {
-		return EC_ERROR_INVAL;
-	}
-
-	/* Check if the port is sourcing VBUS. */
-	if (ppc_is_sourcing_vbus(port)) {
-		CPRINTFUSB("Skip enable C%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	CPRINTSUSB("New charge port: C%d", port);
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < ppc_cnt; i++) {
-		if (i == port)
-			continue;
-
-		if (ppc_vbus_sink_enable(i, 0))
-			CPRINTSUSB("C%d: sink path disable failed.", i);
-	}
-
-	/* Enable requested charge port. */
-	if (ppc_vbus_sink_enable(port, 1)) {
-		CPRINTSUSB("C%d: sink path enable failed.", port);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-__overridable void board_set_charge_limit(int port, int supplier, int charge_ma,
-					  int max_ma, int charge_mv)
-{
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
-}
diff --git a/board/ghost/ec.tasklist b/board/ghost/ec.tasklist
deleted file mode 100644
index 0c79416198..0000000000
--- a/board/ghost/ec.tasklist
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * See CONFIG_TASK_LIST in config.h for details.
- *
- * USB_CHG_Px tasks must be contiguous (see USB_CHG_PORT_TO_TASK_ID(x)).
- * PD_Cx tasks must be contiguous (see PD_PORT_TO_TASK_ID(x))
- */
-
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, HOOKS_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, BASEBOARD_CHARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(CHIPSET, chipset_task, NULL, BASEBOARD_CHIPSET_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_MUX, usb_mux_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, CONSOLE_TASK_STACK_SIZE) \
-	TASK_ALWAYS(POWERBTN, power_button_task, NULL, BASEBOARD_POWERBTN_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C0, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, BASEBOARD_PD_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_shared_alert_task, (BIT(1) | BIT(0)), BASEBOARD_PD_INT_TASK_STACK_SIZE)
diff --git a/board/ghost/fans.c b/board/ghost/fans.c
deleted file mode 100644
index 375ea9a669..0000000000
--- a/board/ghost/fans.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Physical fans. These are logically separate from pwm_channels. */
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "fan_chip.h"
-#include "fan.h"
-#include "hooks.h"
-#include "pwm.h"
-
-#ifndef CONFIG_FANS
-
-/*
- * TODO(b/233126129): use static fan speeds until fan and sensors are
- * tuned. for now, use:
- *
- *   AP off:  33%
- *   AP  on:  50%
- */
-
-static void fan_slow(void)
-{
-	const int duty_pct = 33;
-
-	ccprints("%s: speed %d%%", __func__, duty_pct);
-
-	pwm_enable(PWM_CH_FAN1, 1);
-	pwm_set_duty(PWM_CH_FAN1, duty_pct);
-	pwm_enable(PWM_CH_FAN2, 1);
-	pwm_set_duty(PWM_CH_FAN2, duty_pct);
-}
-
-static void fan_max(void)
-{
-	const int duty_pct = 50;
-
-	ccprints("%s: speed %d%%", __func__, duty_pct);
-
-	pwm_enable(PWM_CH_FAN1, 1);
-	pwm_set_duty(PWM_CH_FAN1, duty_pct);
-	pwm_enable(PWM_CH_FAN2, 1);
-	pwm_set_duty(PWM_CH_FAN2, duty_pct);
-}
-
-DECLARE_HOOK(HOOK_INIT, fan_slow, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, fan_slow, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, fan_slow, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_RESET, fan_max, HOOK_PRIO_FIRST);
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, fan_max, HOOK_PRIO_DEFAULT);
-
-#endif /* CONFIG_FANS */
diff --git a/board/ghost/fw_config.c b/board/ghost/fw_config.c
deleted file mode 100644
index 4a968caccd..0000000000
--- a/board/ghost/fw_config.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "cbi.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "cros_board_info.h"
-#include "fw_config.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-static union ghost_cbi_fw_config fw_config;
-BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
-
-/*
- * FW_CONFIG defaults for ghost if the CBI.FW_CONFIG data is not
- * initialized.
- */
-static const union ghost_cbi_fw_config fw_config_defaults = {
-	.kb_bl = KEYBOARD_BACKLIGHT_ENABLED,
-};
-
-/****************************************************************************
- * Ghost FW_CONFIG access
- */
-void board_init_fw_config(void)
-{
-	if (cbi_get_fw_config(&fw_config.raw_value)) {
-		CPRINTS("CBI: Read FW_CONFIG failed, using board defaults");
-		fw_config = fw_config_defaults;
-	}
-}
-
-union ghost_cbi_fw_config get_fw_config(void)
-{
-	return fw_config;
-}
diff --git a/board/ghost/fw_config.h b/board/ghost/fw_config.h
deleted file mode 100644
index df2ceae238..0000000000
--- a/board/ghost/fw_config.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __BOARD_GHOST_FW_CONFIG_H_
-#define __BOARD_GHOST_FW_CONFIG_H_
-
-#include <stdint.h>
-
-/*
- * TODO(b/233319598): what needs to go into FW_CONFIG
- *
- * CBI FW_CONFIG layout for Ghost board.
- *
- * Source of truth is the project/brya/brya/config.star configuration file.
- */
-
-enum ec_cfg_keyboard_backlight_type {
-	KEYBOARD_BACKLIGHT_DISABLED = 0,
-	KEYBOARD_BACKLIGHT_ENABLED = 1
-};
-
-union ghost_cbi_fw_config {
-	struct {
-		uint32_t				reserved_1 : 4;
-		uint32_t				sd_db : 2;
-		uint32_t				lte_db : 1;
-		enum ec_cfg_keyboard_backlight_type	kb_bl : 1;
-		uint32_t				audio : 3;
-		uint32_t				reserved_2 : 21;
-	};
-	uint32_t raw_value;
-};
-
-/**
- * Read the cached FW_CONFIG.  Guaranteed to have valid values.
- *
- * @return the FW_CONFIG for the board.
- */
-union ghost_cbi_fw_config get_fw_config(void);
-
-/**
- * Get the USB daughter board type from FW_CONFIG.
- *
- * @return the USB daughter board type.
- */
-enum ec_cfg_usb_db_type ec_cfg_usb_db_type(void);
-
-#endif /* __BOARD_GHOST_FW_CONFIG_H_ */
diff --git a/board/ghost/generated-gpio.inc b/board/ghost/generated-gpio.inc
deleted file mode 100644
index 593eb21dec..0000000000
--- a/board/ghost/generated-gpio.inc
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * This file was auto-generated.
- */
-
-/* INTERRUPT GPIOs: */
-GPIO_INT(ACOK_OD,                        PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt)
-GPIO_INT(EC_PROCHOT_IN_L,                PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt)
-GPIO_INT(EC_WP_ODL,                      PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(GSC_EC_PWR_BTN_ODL,             PIN(0, 1), GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW, power_button_interrupt)
-GPIO_INT(LID_OPEN,                       PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)
-GPIO_INT(SEQ_EC_ALL_SYS_PG,              PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SEQ_EC_DSW_PWROK,               PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SEQ_EC_RSMRST_ODL,              PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_S3_L,                       PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SLP_SUS_L,                      PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(SYS_SLP_S0IX_L,                 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(USB_C0_C1_TCPC_INT_ODL,         PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C0_PPC_INT_ODL,             PIN(6, 2), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C0_RT_INT_ODL,              PIN(B, 1), GPIO_INT_FALLING, retimer_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,             PIN(7, 0), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C1_RT_INT_ODL,              PIN(4, 1), GPIO_INT_FALLING, retimer_interrupt)
-
-/* USED GPIOs: */
-GPIO(CCD_MODE_ODL,                   PIN(E, 5), GPIO_INPUT)
-GPIO(CHARGER_INT_ODL,                PIN(7, 3), GPIO_INPUT)
-GPIO(CPU_C10_GATE_L,                 PIN(6, 7), GPIO_INPUT)
-GPIO(EC_ALS_RGB_INT_R_L,             PIN(D, 4), GPIO_INPUT)
-GPIO(EC_BATT_PRES_ODL,               PIN(A, 3), GPIO_INPUT)
-GPIO(EC_ENTERING_RW,                 PIN(0, 3), GPIO_OUT_LOW)
-GPIO(EC_EN_EDP_BL,                   PIN(8, 3), GPIO_OUT_HIGH)
-GPIO(EC_GSC_PACKET_MODE,             PIN(7, 5), GPIO_OUT_LOW)
-GPIO(EC_I2C_BAT_SCL,                 PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_BAT_SDA,                 PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C_MISC_SCL_R,              PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_MISC_SDA_R,              PIN(B, 2), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,              PIN(B, 5), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SENSOR_SDA,              PIN(B, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_USB_C0_C1_PPC_BC_SCL,    PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_C1_PPC_BC_SDA,    PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_C1_TCPC_SCL,      PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_C1_TCPC_SDA,      PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_RT_SCL,           PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C_USB_C0_RT_SDA,           PIN(D, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_RT_SCL,           PIN(E, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_RT_SDA,           PIN(E, 3), GPIO_INPUT)
-GPIO(EC_KB_BL_EN,                    PIN(F, 5), GPIO_OUT_HIGH)
-GPIO(EC_PCHHOT_ODL,                  PIN(7, 4), GPIO_INPUT)
-GPIO(EC_PCH_INT_ODL,                 PIN(B, 0), GPIO_ODR_HIGH)
-GPIO(EC_PCH_PWR_BTN_ODL,             PIN(C, 1), GPIO_ODR_HIGH)
-GPIO(EC_PCH_RSMRST_L,                PIN(A, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_RTCRST,                  PIN(7, 6), GPIO_OUT_LOW)
-GPIO(EC_PCH_SYS_PWROK,               PIN(3, 7), GPIO_OUT_LOW)
-GPIO(EC_PCH_WAKE_R_ODL,              PIN(C, 0), GPIO_ODR_HIGH)
-GPIO(EC_PROCHOT_ODL,                 PIN(6, 3), GPIO_ODR_HIGH)
-GPIO(EN_PP5000_FAN,                  PIN(6, 1), GPIO_OUT_HIGH)
-GPIO(EN_S5_RAILS,                    PIN(B, 6), GPIO_OUT_LOW)
-GPIO(FAN_TACH2,                      PIN(D, 3), GPIO_INPUT)
-GPIO(GLOGO_EN,                       PIN(D, 7), GPIO_OUT_LOW)
-GPIO(IMVP91_VRRDY_OD,                PIN(4, 3), GPIO_INPUT)
-GPIO(PCH_PWROK,                      PIN(7, 2), GPIO_OUT_LOW)
-GPIO(SYS_RST_ODL,                    PIN(C, 5), GPIO_ODR_HIGH)
-GPIO(USB_C0_C1_TCPC_RST_ODL,         PIN(A, 7), GPIO_ODR_LOW)
-GPIO(VCCST_PWRGD_OD,                 PIN(A, 4), GPIO_ODR_LOW)
-
-/* UART alternate functions */
-ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)              /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */
-
-/* I2C alternate functions */
-ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0)               /* GPIO33/I2C5_SCL0/CTS_L, GPIO36/RTS_L/I2C5_SDA0 */
-ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0)               /* GPIO87/I2C1_SDA0 */
-ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0)               /* GPIO92/I2C2_SCL0, GPIO91/I2C2_SDA0, GPIO90/I2C1_SCL0 */
-ALTERNATE(PIN_MASK(B, 0x0c), 0, MODULE_I2C, 0)               /* GPIOB3/I2C7_SCL0/DCD_L, GPIOB2/I2C7_SDA0/DSR_L */
-ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, GPIO_SEL_1P8V)   /* GPIOB5/I2C0_SCL0, GPIOB4/I2C0_SDA0 */
-ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0)               /* GPIOD1/I2C3_SCL0, GPIOD0/I2C3_SDA0 */
-ALTERNATE(PIN_MASK(E, 0x18), 0, MODULE_I2C, 0)               /* GPIOE4/I2C6_SCL1/I3C_SCL, GPIOE3/I2C6_SDA1/I3C_SDA */
-
-/* PWM alternate functions */
-ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0)               /* GPIO40/TA1 */
-ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)               /* GPIO80/PWM3 */
-ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)               /* GPIOB7/PWM5 */
-ALTERNATE(PIN_MASK(C, 0x1c), 0, MODULE_PWM, 0)               /* GPIOC2/PWM1/I2C6_SCL0, GPIOC3/PWM0, GPIOC4/PWM2 */
-
-/* ADC alternate functions */
-ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0)               /* GPIO34/PS2_DAT2/ADC6 */
-ALTERNATE(PIN_MASK(4, 0x34), 0, MODULE_ADC, 0)               /* GPIO42/ADC3/RI_L, GPIO45/ADC0, GPIO44/ADC1 */
-ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0)               /* GPIOE1/ADC7 */
-
-/* KB alternate functions */
-ALTERNATE(PIN_MASK(0, 0xe0), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO10&P80_CLK/GPIO07, KSO11&P80_DAT/GPIO06, KSO12/GPIO05 */
-ALTERNATE(PIN_MASK(1, 0x7f), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO06/GPO13/GP_SEL_L, KSO07/GPO12/JEN_L, KSO03/GPIO16/JTAG_TDO0_SWO, KSO04/GPIO15/XNOR, KSO05/GPIO14, KSO08/GPIO11/CR_SOUT1, KSO09/GPIO10/CR_SIN1 */
-
-ALTERNATE(PIN_MASK(2, 0xfc), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI3/GPIO26/TRACEDATA0, KSI2/GPIO27/TRACEDATA1, KSI4/GPIO25/TRACECLK/GP_SCLK, KSI5/GPIO24/GP_MISO, KSI6/GPIO23/S_SBUB, KSI7/GPIO22/S_SBUA */
-ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KB, GPIO_ODR_HIGH)    /* KSO00/GPIO21/JTAG_TCK_SWCLK, KSO01/GPIO20/JTAG_TMS_SWIO */
-ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI0/GPIO31/TRACEDATA3/GP_MOSI, KSI1/GPIO30/TRACEDATA2/GP_CS_L */
-
-/* PMU alternate functions */
-ALTERNATE(PIN_MASK(0, 0x01), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN2_L&GPI00/GPIO00 */
-ALTERNATE(PIN_MASK(0, 0x02), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW) /* GPIO01/PSL_IN3_L&GPI01 */
-ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN1_L&GPID2/GPIOD2 */
-
-/* GPIO alternate functions */
-ALTERNATE(PIN_MASK(D, 0x08), 0, MODULE_GPIO, GPIO_INPUT)     /* GPIOD3/TB1 */
-
-/* Unused Pins */
-UNUSED(PIN(5, 7))       /* SER_IRQ/ESPI_ALERT_L/GPIO57 */
-UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
-UNUSED(PIN(3, 2))       /* GPO32/TRIS_L */
-UNUSED(PIN(3, 5))       /* GPO35/CR_SOUT4/TEST_L */
-UNUSED(PIN(6, 6))       /* GPIO66 */
-
-/* Pre-configured PSL balls:  J8  K6 */
-
-/* Unreferenced balls */
-/* ['D10', 'D11', 'D6', 'E11', 'F12', 'F5', 'F6', 'F7', 'G10', 'G11', 'G12', 'G6', 'J9', 'L10', 'M11', 'M12', 'M2', 'M7'] */
diff --git a/board/ghost/gpio.inc b/board/ghost/gpio.inc
deleted file mode 100644
index 40d9aa1418..0000000000
--- a/board/ghost/gpio.inc
+++ /dev/null
@@ -1,37 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2022 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#define MODULE_KB		MODULE_KEYBOARD_SCAN
-
-/*
- * Generated-gpio.inc is produced using a Brya specific tool that
- * parses the GPIO definitions derived from the board schematics and
- * EC pinout descriptions derived form the chip datasheets to generate
- * the Chrome EC GPIO pinout definitions. Due to the confidential
- * nature of schematics and datasheets, they are not provided here.
- *
- * Variants that do not auto-generate their GPIO definitions should
- * combine the Brya gpio.inc and generated-gpio.inc into their
- * gpio.inc and customize as appropriate.
- */
-
-#include "generated-gpio.inc"
-
-/*
- * The NPCX keyboard driver does not use named GPIOs to access
- * keyboard scan pins, so we do not list them in *gpio.inc. However, when
- * KEYBOARD_COL2_INVERTED is defined, this name is required.
- */
-GPIO(EC_KSO_02_INV,               PIN(1, 7), GPIO_OUT_LOW)
-
-IOEX(USB_C0_RT_RST_ODL,      EXPIN(IOEX_C0_NCT38XX, 0, 2), GPIO_ODR_LOW)
-IOEX(USB_C0_OC_ODL,          EXPIN(IOEX_C0_NCT38XX, 0, 4), GPIO_ODR_HIGH)
-IOEX(USB_C0_FRS_EN,          EXPIN(IOEX_C0_NCT38XX, 0, 6), GPIO_OUT_LOW)
-
-IOEX(USB_C1_OC_ODL,          EXPIN(IOEX_C1_NCT38XX, 0, 4), GPIO_ODR_HIGH)
-IOEX(USB_C1_FRS_EN,          EXPIN(IOEX_C1_NCT38XX, 0, 6), GPIO_OUT_LOW)
-IOEX(USB_C1_RT_RST_ODL,      EXPIN(IOEX_C1_NCT38XX, 0, 7), GPIO_ODR_LOW)
diff --git a/board/ghost/i2c.c b/board/ghost/i2c.c
deleted file mode 100644
index f65a074344..0000000000
--- a/board/ghost/i2c.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "i2c.h"
-
-/* I2C port map configuration */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		/* I2C0 */
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_SENSOR_SCL,
-		.sda = GPIO_EC_I2C_SENSOR_SDA,
-	},
-	{
-		/* I2C1 */
-		.name = "tcpc0,1",
-		.port = I2C_PORT_USB_C0_C1_TCPC,
-		/* TODO(b/233013680): set to 1000 when validated */
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_USB_C0_C1_TCPC_SCL,
-		.sda = GPIO_EC_I2C_USB_C0_C1_TCPC_SDA,
-	},
-	{
-		/* I2C2 */
-		.name = "ppc0,1",
-		.port = I2C_PORT_USB_C0_C1_PPC,
-		/* TODO(b/233013680): set to 1000 when validated */
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_USB_C0_C1_PPC_BC_SCL,
-		.sda = GPIO_EC_I2C_USB_C0_C1_PPC_BC_SDA,
-	},
-	{
-		/* I2C3 */
-		.name = "retimer0",
-		.port = I2C_PORT_USB_C0_RT,
-		/* TODO(b/233013680): set to 1000 when validated */
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_USB_C0_RT_SCL,
-		.sda = GPIO_EC_I2C_USB_C0_RT_SDA,
-	},
-	{
-		/* I2C5 */
-		.name = "battery",
-		.port = I2C_PORT_BATTERY,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C_BAT_SCL,
-		.sda = GPIO_EC_I2C_BAT_SDA,
-	},
-	{
-		/* I2C6 */
-		.name = "retimer1",
-		.port = I2C_PORT_USB_C1_RT,
-		/* TODO(b/233013680): set to 1000 when validated */
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_USB_C1_RT_SCL,
-		.sda = GPIO_EC_I2C_USB_C1_RT_SDA,
-	},
-	{
-		/* I2C7 */
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_MISC_SCL_R,
-		.sda = GPIO_EC_I2C_MISC_SDA_R,
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/board/ghost/keyboard.c b/board/ghost/keyboard.c
deleted file mode 100644
index 133d574dfa..0000000000
--- a/board/ghost/keyboard.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-
-#include "keyboard_scan.h"
-#include "timer.h"
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/* Increase from 50 us, because KSO_02 passes through the H1. */
-	.output_settle_us = 80,
-	/* Other values should be the same as the default configuration. */
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
diff --git a/board/ghost/led.c b/board/ghost/led.c
deleted file mode 100644
index 685d96dbb2..0000000000
--- a/board/ghost/led.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Ghost specific PWM LED settings.
- *
- * Early boards have 2 PWM LEDs which we simply treat as power
- * indicators.
- */
-
-#include <stdint.h>
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "ec_commands.h"
-#include "pwm.h"
-#include "util.h"
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	memset(brightness_range, '\0',
-	       sizeof(*brightness_range) * EC_LED_COLOR_COUNT);
-	brightness_range[EC_LED_COLOR_WHITE] = 100;
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	uint8_t duty_percent;
-
-	if (led_id != EC_LED_ID_POWER_LED)
-		return EC_ERROR_UNKNOWN;
-
-	duty_percent = brightness[EC_LED_COLOR_WHITE];
-	if (duty_percent > 100)
-		duty_percent = 100;
-	pwm_set_duty(PWM_CH_LED1, duty_percent);
-	pwm_set_duty(PWM_CH_LED2, duty_percent);
-
-	return EC_SUCCESS;
-}
diff --git a/board/ghost/pwm.c b/board/ghost/pwm.c
deleted file mode 100644
index e5fe44dea5..0000000000
--- a/board/ghost/pwm.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-
-#include "compile_time_macros.h"
-#include "hooks.h"
-#include "pwm.h"
-#include "pwm_chip.h"
-
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED1] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 4800,
-	},
-	[PWM_CH_LED2] = {
-		.channel = 1,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 4800,
-	},
-	[PWM_CH_FAN2] = {
-		.channel = 2,
-		.flags = PWM_CONFIG_OPEN_DRAIN | PWM_CONFIG_DSLEEP,
-		.freq = 1000,
-	},
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = 0,
-		/*
-		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
-		 * flicker. Higher frequencies consume similar average power to
-		 * lower PWM frequencies, but higher frequencies record a much
-		 * lower maximum power.
-		 */
-		.freq = 2400,
-	},
-	[PWM_CH_FAN1] = {
-		.channel = 5,
-		.flags = PWM_CONFIG_OPEN_DRAIN | PWM_CONFIG_DSLEEP,
-		.freq = 1000,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-static void board_pwm_init(void)
-{
-	/*
-	 * Turn on all the LEDs at 50%.
-	 */
-	pwm_enable(PWM_CH_LED1, 1);
-	pwm_set_duty(PWM_CH_LED1, 50);
-	pwm_enable(PWM_CH_LED2, 1);
-	pwm_set_duty(PWM_CH_LED2, 50);
-
-	pwm_enable(PWM_CH_KBLIGHT, 1);
-	pwm_set_duty(PWM_CH_KBLIGHT, 50);
-}
-DECLARE_HOOK(HOOK_INIT, board_pwm_init, HOOK_PRIO_DEFAULT);
diff --git a/board/ghost/sensors.c b/board/ghost/sensors.c
deleted file mode 100644
index 202f9c6ef8..0000000000
--- a/board/ghost/sensors.c
+++ /dev/null
@@ -1,187 +0,0 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "adc_chip.h"
-#include "ec_commands.h"
-#include "temp_sensor.h"
-#include "temp_sensor/thermistor.h"
-
-/* ADC configuration */
-struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1_DDR_SOC] = {
-		.name = "TEMP_DDR_SOC",
-		.input_ch = NPCX_ADC_CH0,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_2_AMBIENT] = {
-		.name = "TEMP_AMBIENT",
-		.input_ch = NPCX_ADC_CH1,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_3_CHARGER] = {
-		.name = "TEMP_CHARGER",
-		.input_ch = NPCX_ADC_CH6,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-	[ADC_TEMP_SENSOR_4_WWAN] = {
-		.name = "TEMP_WWAN",
-		.input_ch = NPCX_ADC_CH7,
-		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
-
-/* Temperature sensor configuration */
-const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1_DDR_SOC] = {
-		.name = "DDR and SOC",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_1_DDR_SOC,
-	},
-	[TEMP_SENSOR_2_AMBIENT] = {
-		.name = "Ambient",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_2_AMBIENT,
-	},
-	[TEMP_SENSOR_3_CHARGER] = {
-		.name = "Charger",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_3_CHARGER,
-	},
-	[TEMP_SENSOR_4_WWAN] = {
-		.name = "WWAN",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_4_WWAN,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/*
- * TODO(b/233311897): update temps for ghost
- *
- * Alder Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
- * 130 C.  However, sensor is located next to DDR, so we need to use the lower
- * DDR temperature limit (85 C)
- */
-/*
- * TODO(b/202062363): Remove when clang is fixed.
- */
-#define THERMAL_CPU \
-	{ \
-		.temp_host = { \
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(85), \
-			[EC_TEMP_THRESH_HALT] = C_TO_K(90), \
-		}, \
-		.temp_host_release = { \
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(80), \
-		}, \
-		.temp_fan_off = C_TO_K(35), \
-		.temp_fan_max = C_TO_K(60), \
-	}
-__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
-
-/*
- * TODO(b/233311897): update temps for ghost
- *
- * Inductor limits - used for both charger and PP3300 regulator
- *
- * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
- *
- * Charger max recommended temperature 100C, max absolute temperature 125C
- * PP3300 regulator: operating range -40 C to 145 C
- *
- * Inductors: limit of 125c
- * PCB: limit is 80c
- */
-/*
- * TODO(b/202062363): Remove when clang is fixed.
- */
-#define THERMAL_AMBIENT \
-	{ \
-		.temp_host = { \
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(85), \
-			[EC_TEMP_THRESH_HALT] = C_TO_K(90), \
-		}, \
-		.temp_host_release = { \
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(80), \
-		}, \
-		.temp_fan_off = C_TO_K(35), \
-		.temp_fan_max = C_TO_K(60), \
-	}
-__maybe_unused static const struct ec_thermal_config thermal_ambient =
-	THERMAL_AMBIENT;
-
-/*
- * TODO(b/233311897): update temps for ghost
- *
- * Inductor limits - used for both charger and PP3300 regulator
- *
- * Need to use the lower of the charger IC, PP3300 regulator, and the inductors
- *
- * Charger max recommended temperature 125C, max absolute temperature 150C
- * PP3300 regulator: operating range -40 C to 125 C
- *
- * Inductors: limit of 125c
- * PCB: limit is 80c
- */
-/*
- * TODO(b/202062363): Remove when clang is fixed.
- */
-#define THERMAL_CHARGER \
-	{ \
-		.temp_host = { \
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(105), \
-			[EC_TEMP_THRESH_HALT] = C_TO_K(120), \
-		}, \
-		.temp_host_release = { \
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(90), \
-		}, \
-		.temp_fan_off = C_TO_K(35), \
-		.temp_fan_max = C_TO_K(65), \
-	}
-__maybe_unused static const struct ec_thermal_config thermal_charger =
-	THERMAL_CHARGER;
-
-/*
- * TODO(b/233311897): update temps for ghost
- */
-/*
- * TODO(b/202062363): Remove when clang is fixed.
- */
-#define THERMAL_WWAN \
-	{ \
-		.temp_host = { \
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(130), \
-			[EC_TEMP_THRESH_HALT] = C_TO_K(130), \
-		}, \
-		.temp_host_release = { \
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(100), \
-		}, \
-		.temp_fan_off = C_TO_K(35), \
-		.temp_fan_max = C_TO_K(60), \
-	}
-__maybe_unused static const struct ec_thermal_config thermal_wwan =
-	THERMAL_WWAN;
-
-struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_DDR_SOC] = THERMAL_CPU,
-	[TEMP_SENSOR_2_AMBIENT] = THERMAL_AMBIENT,
-	[TEMP_SENSOR_3_CHARGER] = THERMAL_CHARGER,
-	[TEMP_SENSOR_4_WWAN] = THERMAL_WWAN,
-};
-BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
diff --git a/board/ghost/usbc_config.c b/board/ghost/usbc_config.c
deleted file mode 100644
index f8b1df5ade..0000000000
--- a/board/ghost/usbc_config.c
+++ /dev/null
@@ -1,299 +0,0 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <stdint.h>
-#include <stdbool.h>
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "driver/ppc/syv682x_public.h"
-#include "driver/retimer/bb_retimer_public.h"
-#include "driver/tcpm/nct38xx.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "gpio_signal.h"
-#include "hooks.h"
-#include "ioexpander.h"
-#include "system.h"
-#include "timer.h"
-#include "usbc_config.h"
-#include "usbc_ppc.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usb_pd_tbt.h"
-#include "usb_pd_tcpm.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-#ifdef CONFIG_ZEPHYR
-enum ioex_port {
-	IOEX_C0_NCT38XX = 0,
-	IOEX_C1_NCT38XX,
-	IOEX_PORT_COUNT
-};
-#endif /* CONFIG_ZEPHYR */
-
-/* USBC TCPC configuration */
-const struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0_C1_TCPC,
-			.addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS,
-		},
-		.drv = &nct38xx_tcpm_drv,
-		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
-			TCPC_FLAGS_NO_DEBUG_ACC_CONTROL,
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0_C1_TCPC,
-			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		},
-		.drv = &nct38xx_tcpm_drv,
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-/******************************************************************************/
-
-/* USBC PPC configuration */
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0_C1_PPC,
-		.i2c_addr_flags = SYV682X_ADDR2_FLAGS,
-		.frs_en = IOEX_USB_C0_FRS_EN,
-		.drv = &syv682x_drv,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C0_C1_PPC,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.frs_en = IOEX_USB_C1_FRS_EN,
-		.drv = &syv682x_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/* USBC mux configuration - Alder Lake includes internal mux */
-static const struct usb_mux usbc0_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-static const struct usb_mux usbc1_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-
-const struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C0_RT,
-		.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc0_tcss_usb_mux,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C1_RT,
-		.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc1_tcss_usb_mux,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-#ifndef CONFIG_ZEPHYR
-/*
- * USB C0 and C1 uses burnside bridge chips and have their reset
- * controlled by their respective TCPC chips acting as GPIO expanders.
- *
- * ioex_init() is normally called before we take the TCPCs out of
- * reset, so we need to start in disabled mode, then explicitly
- * call ioex_init().
- */
-
-struct ioexpander_config_t ioex_config[] = {
-	[IOEX_C0_NCT38XX] = {
-		.i2c_host_port = I2C_PORT_USB_C0_C1_TCPC,
-		.i2c_addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS,
-		.drv = &nct38xx_ioexpander_drv,
-		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
-	},
-	[IOEX_C1_NCT38XX] = {
-		.i2c_host_port = I2C_PORT_USB_C0_C1_TCPC,
-		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		.drv = &nct38xx_ioexpander_drv,
-		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT);
-#endif /* !CONFIG_ZEPHYR */
-
-__override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
-{
-	enum ioex_signal rst_signal;
-
-	if (me->usb_port == USBC_PORT_C0)
-		rst_signal = IOEX_USB_C0_RT_RST_ODL;
-	else if (me->usb_port == USBC_PORT_C1)
-		rst_signal = IOEX_USB_C1_RT_RST_ODL;
-	else
-		return EC_ERROR_INVAL;
-
-	/*
-	 * We do not have a load switch for the burnside bridge chips,
-	 * so we only need to sequence reset.
-	 */
-
-	if (enable) {
-		/*
-		 * Tpw, minimum time from VCC to RESET_N de-assertion is 100us.
-		 * For boards that don't provide a load switch control, the
-		 * retimer_init() function ensures power is up before calling
-		 * this function.
-		 */
-		ioex_set_level(rst_signal, 1);
-		/*
-		 * Allow 1ms time for the retimer to power up lc_domain
-		 * which powers I2C controller within retimer
-		 */
-		msleep(1);
-	} else {
-		ioex_set_level(rst_signal, 0);
-		msleep(1);
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_reset_pd_mcu(void)
-{
-	enum gpio_signal tcpc_rst;
-
-	tcpc_rst = GPIO_USB_C0_C1_TCPC_RST_ODL;
-
-	gpio_set_level(tcpc_rst, 0);
-
-	/*
-	 * delay for power-on to reset-off and min. assertion time.
-	 * the nct380x needs a 100 ns reset pulse.
-	 */
-
-	msleep(1);
-
-	gpio_set_level(tcpc_rst, 1);
-
-	/*
-	 * wait for chips to come up.
-	 * the nct3808 needs 3 ms.
-	 */
-
-	msleep(5);
-}
-
-static void board_tcpc_init(void)
-{
-	/* Don't reset TCPCs after initial reset */
-	if (!system_jumped_late())
-		board_reset_pd_mcu();
-
-	/*
-	 * These IO expander pins are implemented using the
-	 * C0/C1 TCPC, so they must be set up after the TCPC has
-	 * been taken out of reset.
-	 */
-	ioex_init(IOEX_C0_NCT38XX);
-	ioex_init(IOEX_C1_NCT38XX);
-
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_C1_TCPC_INT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	if (gpio_get_level(GPIO_USB_C0_C1_TCPC_INT_ODL) == 0)
-		status |= PD_STATUS_TCPC_ALERT_0 | PD_STATUS_TCPC_ALERT_1;
-
-	return status;
-}
-
-int ppc_get_alert_status(int port)
-{
-	if (port == USBC_PORT_C0)
-		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
-	else if (port == USBC_PORT_C1)
-		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
-	return 0;
-}
-
-void tcpc_alert_event(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_C1_TCPC_INT_ODL:
-		schedule_deferred_pd_interrupt(USBC_PORT_C0);
-		break;
-	default:
-		break;
-	}
-}
-
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C0);
-		break;
-	case GPIO_USB_C1_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C1);
-		break;
-	default:
-		break;
-	}
-}
-
-void retimer_interrupt(enum gpio_signal signal)
-{
-	/*
-	 * TODO(b/233317538): do we need this interrupt
-	 */
-}
-
-__override bool board_is_dts_port(int port)
-{
-	return port == USBC_PORT_C0;
-}
-
-__override bool board_is_tbt_usb4_port(int port)
-{
-	if (port == USBC_PORT_C0 || port == USBC_PORT_C1)
-		return true;
-
-	return false;
-}
-
-__override enum tbt_compat_cable_speed board_get_max_tbt_speed(int port)
-{
-	if (!board_is_tbt_usb4_port(port))
-		return TBT_SS_RES_0;
-
-	return TBT_SS_TBT_GEN3;
-}
diff --git a/board/gimble/battery.c b/board/gimble/battery.c
index 235503a6f1..89b0ddf1e2 100644
--- a/board/gimble/battery.c
+++ b/board/gimble/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/gimble/board.c b/board/gimble/board.c
index 2d0ebdeb80..0ca135b9fd 100644
--- a/board/gimble/board.c
+++ b/board/gimble/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -35,8 +35,8 @@
 #include "gpio_list.h" /* Must come after other header files. */
 
 /* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 /******************************************************************************/
 /* USB-A charging control */
@@ -106,8 +106,8 @@ int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
 	}
 
 	if (voltage < BC12_MIN_VOLTAGE) {
-		CPRINTS("%s: port %d: vbus %d lower than %d", __func__,
-			port, voltage, BC12_MIN_VOLTAGE);
+		CPRINTS("%s: port %d: vbus %d lower than %d", __func__, port,
+			voltage, BC12_MIN_VOLTAGE);
 		return 1;
 	}
 
@@ -141,53 +141,53 @@ __overridable void board_ps8xxx_tcpc_init(int port)
 {
 	int val;
 
-	if (i2c_read8(I2C_PORT_USB_C1_TCPC,
-		PS8XXX_I2C_ADDR1_P1_FLAGS, PS8815_REG_APTX_EQ_AT_10G, &val))
+	if (i2c_read8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_P1_FLAGS,
+		      PS8815_REG_APTX_EQ_AT_10G, &val))
 		CPRINTS("ps8815: fail to read reg 0x%02x",
 			PS8815_REG_APTX_EQ_AT_10G);
 
 	/* APTX2 EQ 23dB, APTX1 EQ 23dB */
-	if (i2c_write8(I2C_PORT_USB_C1_TCPC,
-		PS8XXX_I2C_ADDR1_P1_FLAGS, PS8815_REG_APTX_EQ_AT_10G, 0x99))
+	if (i2c_write8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_P1_FLAGS,
+		       PS8815_REG_APTX_EQ_AT_10G, 0x99))
 		CPRINTS("ps8815: fail to write reg 0x%02x",
 			PS8815_REG_APTX_EQ_AT_10G);
 
-	if (i2c_read8(I2C_PORT_USB_C1_TCPC,
-		PS8XXX_I2C_ADDR1_P1_FLAGS, PS8815_REG_RX_EQ_AT_10G, &val))
+	if (i2c_read8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_P1_FLAGS,
+		      PS8815_REG_RX_EQ_AT_10G, &val))
 		CPRINTS("ps8815: fail to read reg 0x%02x",
 			PS8815_REG_RX_EQ_AT_10G);
 
 	/* RX2 EQ 18dB, RX1 EQ 16dB */
-	if (i2c_write8(I2C_PORT_USB_C1_TCPC,
-		PS8XXX_I2C_ADDR1_P1_FLAGS, PS8815_REG_RX_EQ_AT_10G, 0x64))
+	if (i2c_write8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_P1_FLAGS,
+		       PS8815_REG_RX_EQ_AT_10G, 0x64))
 		CPRINTS("ps8815: fail to write reg 0x%02x",
 			PS8815_REG_RX_EQ_AT_10G);
 
-	if (i2c_read8(I2C_PORT_USB_C1_TCPC,
-		PS8XXX_I2C_ADDR1_P1_FLAGS, PS8815_REG_APTX_EQ_AT_5G, &val))
+	if (i2c_read8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_P1_FLAGS,
+		      PS8815_REG_APTX_EQ_AT_5G, &val))
 		CPRINTS("ps8815: fail to read reg 0x%02x",
 			PS8815_REG_APTX_EQ_AT_5G);
 
 	/* APTX2 EQ 16dB, APTX1 EQ 16dB */
-	if (i2c_write8(I2C_PORT_USB_C1_TCPC,
-		PS8XXX_I2C_ADDR1_P1_FLAGS, PS8815_REG_APTX_EQ_AT_5G, 0x44))
+	if (i2c_write8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_P1_FLAGS,
+		       PS8815_REG_APTX_EQ_AT_5G, 0x44))
 		CPRINTS("ps8815: fail to write reg 0x%02x",
 			PS8815_REG_APTX_EQ_AT_5G);
 
-	if (i2c_read8(I2C_PORT_USB_C1_TCPC,
-		PS8XXX_I2C_ADDR1_P1_FLAGS, PS8815_REG_RX_EQ_AT_5G, &val))
+	if (i2c_read8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_P1_FLAGS,
+		      PS8815_REG_RX_EQ_AT_5G, &val))
 		CPRINTS("ps8815: fail to read reg 0x%02x",
 			PS8815_REG_RX_EQ_AT_5G);
 
 	/* RX2 EQ 16dB, RX1 EQ 16dB */
-	if (i2c_write8(I2C_PORT_USB_C1_TCPC,
-		PS8XXX_I2C_ADDR1_P1_FLAGS, PS8815_REG_RX_EQ_AT_5G, 0x44))
+	if (i2c_write8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_P1_FLAGS,
+		       PS8815_REG_RX_EQ_AT_5G, 0x44))
 		CPRINTS("ps8815: fail to write reg 0x%02x",
 			PS8815_REG_RX_EQ_AT_5G);
 }
 
 __override void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+				       int max_ma, int charge_mv)
 {
 	/*
 	 * Follow OEM request to limit the input current to
@@ -195,7 +195,6 @@ __override void board_set_charge_limit(int port, int supplier, int charge_ma,
 	 */
 	charge_ma = charge_ma * 90 / 100;
 
-	charge_set_input_current_limit(MAX(charge_ma,
-					CONFIG_CHARGER_INPUT_CURRENT),
-					charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
diff --git a/board/gimble/board.h b/board/gimble/board.h
index 32b2945abe..015f3f78e6 100644
--- a/board/gimble/board.h
+++ b/board/gimble/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,7 +25,7 @@
 /* BMA253 accelerometer in lid */
 #define CONFIG_ACCEL_BMA255
 
-#define CONFIG_ACCELGYRO_BMI160	/* Base accel/gyro */
+#define CONFIG_ACCELGYRO_BMI160 /* Base accel/gyro */
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 
@@ -42,8 +42,8 @@
 /* Lid accel */
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE	BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID	LID_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
 
 /* Enable sensor fifo, must also define the _SIZE and _THRES */
 #define CONFIG_ACCEL_FIFO
@@ -57,13 +57,13 @@
 #define CONFIG_CMD_ACCEL_INFO
 
 /* USB Type A Features */
-#define USB_PORT_COUNT			1
+#define USB_PORT_COUNT 1
 #define CONFIG_USB_PORT_POWER_DUMB
 
 /* USB Type C and USB PD defines */
 #define CONFIG_IO_EXPANDER
 #define CONFIG_IO_EXPANDER_NCT38XX
-#define CONFIG_IO_EXPANDER_PORT_COUNT		1
+#define CONFIG_IO_EXPANDER_PORT_COUNT 1
 
 #define CONFIG_USB_PD_TCPM_PS8815
 #define CONFIG_USB_PD_TCPM_PS8815_FORCE_DID
@@ -78,9 +78,9 @@
 #define CONFIG_USB_PD_FRS_PPC
 
 /* measure and check these values on gimble */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
 
 /* I2C speed console command */
 #define CONFIG_CMD_I2C_SPEED
@@ -91,10 +91,10 @@
 /*
  * Passive USB-C cables only support up to 60W.
  */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /*
  * Macros for GPIO signals used in common code that don't match the
@@ -102,33 +102,33 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT		GPIO_EC_EN_EDP_BL
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_GSC_PACKET_MODE
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SYS_SLP_S0IX_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_TEMP_SENSOR_POWER		GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
 
 /*
  * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
  * signal.
  */
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_SEQ_EC_ALL_SYS_PG
-#define GPIO_PG_EC_DSW_PWROK		GPIO_SEQ_EC_DSW_PWROK
-#define GPIO_PG_EC_RSMRST_ODL		GPIO_SEQ_EC_RSMRST_ODL
-#define GPIO_POWER_BUTTON_L		GPIO_GSC_EC_PWR_BTN_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_ODL
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
 
 /* System has back-lit keyboard */
 #define CONFIG_PWM_KBLIGHT
@@ -139,28 +139,28 @@
 
 /* I2C Bus Configuration */
 
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
 
-#define I2C_PORT_USB_C0_TCPC	NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1_TCPC	NPCX_I2C_PORT4_1
+#define I2C_PORT_USB_C0_TCPC NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1
 
-#define I2C_PORT_USB_C0_PPC	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_PPC	NPCX_I2C_PORT4_1
+#define I2C_PORT_USB_C0_PPC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT4_1
 
-#define I2C_PORT_USB_C0_BC12	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_BC12	NPCX_I2C_PORT4_1
+#define I2C_PORT_USB_C0_BC12 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT4_1
 
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT5_0
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT7_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-#define I2C_PORT_MP2964		NPCX_I2C_PORT7_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0
 
 /* define this to aviod error on CONFIG_ACCELGYRO_BMI_COMM_I2C */
-#define I2C_PORT_ACCEL		I2C_PORT_SENSOR
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
 
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 
-#define I2C_ADDR_MP2964_FLAGS	0x20
+#define I2C_ADDR_MP2964_FLAGS 0x20
 
 /* Disabling Thunderbolt-compatible mode */
 #undef CONFIG_USB_PD_TBT_COMPAT_MODE
@@ -191,14 +191,14 @@
 /* Charger defines */
 #define CONFIG_CHARGER_BQ25720
 #define CONFIG_CHARGER_BQ25720_VSYS_TH2_CUSTOM
-#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV	70
+#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV 70
 #define CONFIG_CHARGE_RAMP_SW
-#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10
 #define CONFIG_CHARGER_BQ25710_PSYS_SENSING
 
 /* PROCHOT defines */
-#define BATT_MAX_CONTINUE_DISCHARGE_WATT    45
+#define BATT_MAX_CONTINUE_DISCHARGE_WATT 45
 
 /* Prochot assertion/deassertion ratios*/
 #define PROCHOT_ADAPTER_WATT_RATIO 97
@@ -213,7 +213,7 @@
 
 #ifndef __ASSEMBLER__
 
-#include "gpio_signal.h"	/* needed by registers.h */
+#include "gpio_signal.h" /* needed by registers.h */
 #include "registers.h"
 #include "usbc_config.h"
 
@@ -232,17 +232,9 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL = 0, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
-enum ioex_port {
-	IOEX_C0_NCT38XX = 0,
-	IOEX_PORT_COUNT
-};
+enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_PORT_COUNT };
 
 enum battery_type {
 	BATTERY_SIMPLO_HIGHPOWER,
@@ -251,24 +243,18 @@ enum battery_type {
 };
 
 enum pwm_channel {
-	PWM_CH_LED2 = 0,		/* PWM0 (white charger) */
-	PWM_CH_LED3,			/* PWM1 (orange on DB) */
-	PWM_CH_LED1,			/* PWM2 (orange charger) */
-	PWM_CH_KBLIGHT,			/* PWM3 */
-	PWM_CH_FAN,			/* PWM5 */
-	PWM_CH_LED4,			/* PWM7 (white on DB) */
+	PWM_CH_LED2 = 0, /* PWM0 (white charger) */
+	PWM_CH_LED3, /* PWM1 (orange on DB) */
+	PWM_CH_LED1, /* PWM2 (orange charger) */
+	PWM_CH_KBLIGHT, /* PWM3 */
+	PWM_CH_FAN, /* PWM5 */
+	PWM_CH_LED4, /* PWM7 (white on DB) */
 	PWM_CH_COUNT
 };
 
-enum fan_channel {
-	FAN_CH_0 = 0,
-	FAN_CH_COUNT
-};
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT };
 
-enum mft_channel {
-	MFT_CH_0 = 0,
-	MFT_CH_COUNT
-};
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT };
 
 void motion_interrupt(enum gpio_signal signal);
 
diff --git a/board/gimble/build.mk b/board/gimble/build.mk
index c43f37b4dd..cad0da2a4e 100644
--- a/board/gimble/build.mk
+++ b/board/gimble/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/gimble/charger.c b/board/gimble/charger.c
index 476ce97df2..a4fa209246 120000..100644
--- a/board/gimble/charger.c
+++ b/board/gimble/charger.c
@@ -1 +1,90 @@
-../../baseboard/brya/charger_bq25720.c
\ No newline at end of file
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+
+#include "charge_manager.h"
+#include "charge_state_v2.h"
+#include "charger.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/charger/bq25710.h"
+#include "usbc_ppc.h"
+#include "usb_pd.h"
+#include "util.h"
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+#ifndef CONFIG_ZEPHYR
+/* Charger Chip Configuration */
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = BQ25710_SMBUS_ADDR1_FLAGS,
+		.drv = &bq25710_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CHARGER_NUM);
+#endif
+
+int board_set_active_charge_port(int port)
+{
+	int is_valid_port = board_is_usb_pd_port_present(port);
+	int i;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTSUSB("Disabling all charger ports");
+
+		/* Disable all ports. */
+		for (i = 0; i < ppc_cnt; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (ppc_vbus_sink_enable(i, 0))
+				CPRINTSUSB("Disabling C%d as sink failed.", i);
+		}
+
+		return EC_SUCCESS;
+	} else if (!is_valid_port) {
+		return EC_ERROR_INVAL;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (ppc_is_sourcing_vbus(port)) {
+		CPRINTFUSB("Skip enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTSUSB("New charge port: C%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < ppc_cnt; i++) {
+		if (i == port)
+			continue;
+
+		if (ppc_vbus_sink_enable(i, 0))
+			CPRINTSUSB("C%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTSUSB("C%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+__overridable void board_set_charge_limit(int port, int supplier, int charge_ma,
+					  int max_ma, int charge_mv)
+{
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+}
diff --git a/board/gimble/ec.tasklist b/board/gimble/ec.tasklist
index 9207f8729d..27ab9a6e63 100644
--- a/board/gimble/ec.tasklist
+++ b/board/gimble/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/gimble/fans.c b/board/gimble/fans.c
index d966056331..90e251511f 100644
--- a/board/gimble/fans.c
+++ b/board/gimble/fans.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,7 +25,7 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 static const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
diff --git a/board/gimble/fw_config.c b/board/gimble/fw_config.c
index 1589811ad0..8698145efd 100644
--- a/board/gimble/fw_config.c
+++ b/board/gimble/fw_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,7 +9,7 @@
 #include "cros_board_info.h"
 #include "fw_config.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 static union brya_cbi_fw_config fw_config;
 BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
diff --git a/board/gimble/fw_config.h b/board/gimble/fw_config.h
index 32631f7b77..fcf24b4094 100644
--- a/board/gimble/fw_config.h
+++ b/board/gimble/fw_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,22 +25,19 @@ enum ec_cfg_keyboard_backlight_type {
 	KEYBOARD_BACKLIGHT_ENABLED = 1
 };
 
-enum ec_cfg_keyboard_layout {
-	KB_LAYOUT_DEFAULT = 0,
-	KB_LAYOUT_1 = 1
-};
+enum ec_cfg_keyboard_layout { KB_LAYOUT_DEFAULT = 0, KB_LAYOUT_1 = 1 };
 
 union brya_cbi_fw_config {
 	struct {
-		enum ec_cfg_usb_db_type			usb_db : 4;
-		uint32_t				sd_db : 2;
-		uint32_t				reserved_0 : 1;
-		enum ec_cfg_keyboard_backlight_type	kb_bl : 1;
-		uint32_t				audio : 3;
-		uint32_t				cellular_db : 2;
-		uint32_t				wifi_sar_id : 1;
-		enum ec_cfg_keyboard_layout		kb_layout : 2;
-		uint32_t				reserved_1 : 16;
+		enum ec_cfg_usb_db_type usb_db : 4;
+		uint32_t sd_db : 2;
+		uint32_t reserved_0 : 1;
+		enum ec_cfg_keyboard_backlight_type kb_bl : 1;
+		uint32_t audio : 3;
+		uint32_t cellular_db : 2;
+		uint32_t wifi_sar_id : 1;
+		enum ec_cfg_keyboard_layout kb_layout : 2;
+		uint32_t reserved_1 : 16;
 	};
 	uint32_t raw_value;
 };
diff --git a/board/gimble/gpio.inc b/board/gimble/gpio.inc
index 412673c227..1961f1bcb4 100644
--- a/board/gimble/gpio.inc
+++ b/board/gimble/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/gimble/i2c.c b/board/gimble/i2c.c
index 7bedcc05db..621e7bf3f0 100644
--- a/board/gimble/i2c.c
+++ b/board/gimble/i2c.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/gimble/keyboard.c b/board/gimble/keyboard.c
index cec70e3d97..e1b0ca8a21 100644
--- a/board/gimble/keyboard.c
+++ b/board/gimble/keyboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -44,8 +44,8 @@ static const struct ec_response_keybd_config gimble_kb = {
 	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
 };
 
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	return &gimble_kb;
 }
diff --git a/board/gimble/led.c b/board/gimble/led.c
index 3176e1a35d..7b6fd5c24e 100644
--- a/board/gimble/led.c
+++ b/board/gimble/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -28,34 +28,34 @@ __override const int led_charge_lvl_1 = 5;
 __override const int led_charge_lvl_2 = 95;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {
-					{EC_LED_COLOR_AMBER, 0.5 * LED_ONE_SEC},
-					{LED_OFF,            0.5 * LED_ONE_SEC}
-	},
-	[STATE_FACTORY_TEST]         = {
-					{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC}
-	},
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    0.5 * LED_ONE_SEC },
+					  { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 1 * LED_ONE_SEC } },
+	};
 
 __override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           =  {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   =  {{LED_OFF,  LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] =  {{LED_OFF,  LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {
-		{LED_OFF,             LED_INDEFINITE} },
-};
-
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
 const enum ec_led_id supported_led_ids[] = {
 	EC_LED_ID_BATTERY_LED,
@@ -108,7 +108,7 @@ __override void led_set_color_battery(enum ec_led_colors color)
 		default: /* Unknown charging port */
 			break;
 		}
-	} else {  
+	} else {
 		switch (color) {
 		case EC_LED_COLOR_AMBER:
 			led1_duty = BAT_LED_ON_LVL;
diff --git a/board/gimble/pwm.c b/board/gimble/pwm.c
index 54ffd9411d..9f9a8ed94f 100644
--- a/board/gimble/pwm.c
+++ b/board/gimble/pwm.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/gimble/sensors.c b/board/gimble/sensors.c
index 0e030846db..d39d43d887 100644
--- a/board/gimble/sensors.c
+++ b/board/gimble/sensors.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,6 +11,8 @@
 #include "driver/accel_bma422.h"
 #include "driver/accelgyro_bmi_common.h"
 #include "driver/accelgyro_lsm6dsm.h"
+#include "driver/tcpm/ps8xxx_public.h"
+#include "driver/tcpm/tcpci.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "keyboard_scan.h"
@@ -67,30 +69,22 @@ static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
 static struct accelgyro_saved_data_t g_bma422_data;
 
 /* TODO(b/192477578): calibrate the orientation matrix on later board stage */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					     { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
-static const mat33_fp_t lid_standard_ref_id_1 = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref_id_1 = { { 0, FLOAT_TO_FP(1), 0 },
+						  { FLOAT_TO_FP(1), 0, 0 },
+						  { 0, 0, FLOAT_TO_FP(-1) } };
 
 /* TODO(b/192477578): calibrate the orientation matrix on later board stage */
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, FLOAT_TO_FP(-1), 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
 
-static const mat33_fp_t base_standard_ref_id_1 = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t base_standard_ref_id_1 = { { 0, FLOAT_TO_FP(1), 0 },
+						   { FLOAT_TO_FP(-1), 0, 0 },
+						   { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
@@ -285,24 +279,18 @@ DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_INIT_I2C + 1);
 
 /* Temperature sensor configuration */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1_DDR_SOC] = {
-		.name = "DDR and SOC",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_1_DDR_SOC
-	},
-	[TEMP_SENSOR_2_FAN] = {
-		.name = "Fan",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_2_FAN
-	},
-	[TEMP_SENSOR_3_CHARGER] = {
-		.name = "Charger",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_3_CHARGER
-	},
+	[TEMP_SENSOR_1_DDR_SOC] = { .name = "DDR and SOC",
+				    .type = TEMP_SENSOR_TYPE_BOARD,
+				    .read = get_temp_3v3_30k9_47k_4050b,
+				    .idx = ADC_TEMP_SENSOR_1_DDR_SOC },
+	[TEMP_SENSOR_2_FAN] = { .name = "Fan",
+				.type = TEMP_SENSOR_TYPE_BOARD,
+				.read = get_temp_3v3_30k9_47k_4050b,
+				.idx = ADC_TEMP_SENSOR_2_FAN },
+	[TEMP_SENSOR_3_CHARGER] = { .name = "Charger",
+				    .type = TEMP_SENSOR_TYPE_BOARD,
+				    .read = get_temp_3v3_30k9_47k_4050b,
+				    .idx = ADC_TEMP_SENSOR_3_CHARGER },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -316,8 +304,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CPU \
-	{ \
+#define THERMAL_CPU              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
@@ -344,8 +332,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_INDUCTOR \
-	{ \
+#define THERMAL_INDUCTOR         \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
@@ -357,6 +345,19 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 __maybe_unused static const struct ec_thermal_config thermal_inductor =
 	THERMAL_INDUCTOR;
 
+#define THERMAL_FAN_MISSING      \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(100), \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+		}, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_fan_missing =
+	THERMAL_FAN_MISSING;
+
 /* this should really be "const" */
 struct ec_thermal_config thermal_params[] = {
 	[TEMP_SENSOR_1_DDR_SOC] = THERMAL_CPU,
@@ -364,4 +365,23 @@ struct ec_thermal_config thermal_params[] = {
 	[TEMP_SENSOR_2_FAN] = THERMAL_INDUCTOR,
 	[TEMP_SENSOR_3_CHARGER] = THERMAL_INDUCTOR,
 };
+
+struct ec_thermal_config temp_sensor_2_fan_set[] = {
+	[TEMP_SENSOR_2_FAN] = THERMAL_FAN_MISSING,
+};
+
+static void config_thermal_params(void)
+{
+	int rv, val;
+
+	rv = tcpc_addr_read16_no_lpm_exit(USBC_PORT_C1, PS8XXX_I2C_ADDR1_FLAGS,
+					  TCPC_REG_VENDOR_ID, &val);
+
+	if (rv != 0) {
+		thermal_params[TEMP_SENSOR_2_FAN] =
+			temp_sensor_2_fan_set[TEMP_SENSOR_2_FAN];
+	}
+}
+DECLARE_HOOK(HOOK_INIT, config_thermal_params, HOOK_PRIO_INIT_I2C + 1);
+
 BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
diff --git a/board/gimble/thermal.c b/board/gimble/thermal.c
index 25e7bf2c00..37184f92f2 100644
--- a/board/gimble/thermal.c
+++ b/board/gimble/thermal.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,9 +15,7 @@
 #include "util.h"
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_THERMAL, outstr)
-#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args)
-
-
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
 
 struct fan_step {
 	/*
@@ -42,45 +40,45 @@ struct fan_step {
 static const struct fan_step fan_table[] = {
 	{
 		/* level 0 */
-		.on = {43, -1, -1},
-		.off = {0, -1, -1},
-		.rpm = {0},
-		.rpm_tablet = {0},
+		.on = { 43, -1, -1 },
+		.off = { 0, -1, -1 },
+		.rpm = { 0 },
+		.rpm_tablet = { 0 },
 	},
 	{
 		/* level 1 */
-		.on = {45, -1, -1},
-		.off = {43, -1, -1},
-		.rpm = {3400},
-		.rpm_tablet = {3400},
+		.on = { 45, -1, -1 },
+		.off = { 43, -1, -1 },
+		.rpm = { 3400 },
+		.rpm_tablet = { 3400 },
 	},
 	{
 		/* level 2 */
-		.on = {46, -1, -1},
-		.off = {44, -1, -1},
-		.rpm = {3800},
-		.rpm_tablet = {3700},
+		.on = { 46, -1, -1 },
+		.off = { 44, -1, -1 },
+		.rpm = { 3800 },
+		.rpm_tablet = { 3700 },
 	},
 	{
 		/* level 3 */
-		.on = {48, -1, -1},
-		.off = {45, -1, -1},
-		.rpm = {4200},
-		.rpm_tablet = {4100},
+		.on = { 48, -1, -1 },
+		.off = { 45, -1, -1 },
+		.rpm = { 4200 },
+		.rpm_tablet = { 4100 },
 	},
 	{
 		/* level 4 */
-		.on = {50, -1, -1},
-		.off = {47, -1, -1},
-		.rpm = {4800},
-		.rpm_tablet = {4800},
+		.on = { 50, -1, -1 },
+		.off = { 47, -1, -1 },
+		.rpm = { 4800 },
+		.rpm_tablet = { 4800 },
 	},
 	{
 		/* level 5 */
-		.on = {52, -1, -1},
-		.off = {49, -1, -1},
-		.rpm = {5400},
-		.rpm_tablet = {5200},
+		.on = { 52, -1, -1 },
+		.off = { 49, -1, -1 },
+		.rpm = { 5400 },
+		.rpm_tablet = { 5200 },
 	},
 };
 const int num_fan_levels = ARRAY_SIZE(fan_table);
@@ -106,18 +104,15 @@ int fan_table_to_rpm(int fan, int *temp, enum temp_sensor_id temp_sensor)
 	 */
 	if (temp[temp_sensor] < prev_temp[temp_sensor]) {
 		for (i = current_level; i > 0; i--) {
-			if (temp[temp_sensor] <
-				fan_table[i].off[temp_sensor])
+			if (temp[temp_sensor] < fan_table[i].off[temp_sensor])
 				current_level = i - 1;
 			else
 				break;
 		}
-	} else if (temp[temp_sensor] >
-		prev_temp[temp_sensor]) {
+	} else if (temp[temp_sensor] > prev_temp[temp_sensor]) {
 		for (i = current_level; i < num_fan_levels; i++) {
-			if (temp[temp_sensor] >
-				fan_table[i].on[temp_sensor])
-				current_level = i + 1;
+			if (temp[temp_sensor] >= fan_table[i].on[temp_sensor])
+				current_level = i;
 			else
 				break;
 		}
@@ -151,7 +146,8 @@ void board_override_fan_control(int fan, int *temp)
 	if (chipset_in_state(CHIPSET_STATE_ON)) {
 		fan_set_rpm_mode(FAN_CH(fan), 1);
 		fan_set_rpm_target(FAN_CH(fan),
-			fan_table_to_rpm(FAN_CH(fan), temp, TEMP_SENSOR_1_DDR_SOC));
+				   fan_table_to_rpm(FAN_CH(fan), temp,
+						    TEMP_SENSOR_1_DDR_SOC));
 	} else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
 		/* Stop fan when enter S0ix */
 		fan_set_rpm_mode(FAN_CH(fan), 1);
diff --git a/board/gimble/usbc_config.c b/board/gimble/usbc_config.c
index e747ab0df9..feb123a525 100644
--- a/board/gimble/usbc_config.c
+++ b/board/gimble/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -34,8 +34,8 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 /* USBC TCPC configuration */
 const struct tcpc_config_t tcpc_config[] = {
@@ -88,26 +88,33 @@ unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
  * to the virtual_usb_mux_driver so the AP gets notified of mux changes
  * and updates the TCSS configuration on state changes.
  */
-static const struct usb_mux usbc1_usb3_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	.next_mux = NULL,
+static const struct usb_mux_chain usbc1_usb3_db_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
+	.next = NULL,
 };
 
 /* USBC mux configuration - Alder Lake includes internal mux */
-const struct usb_mux usb_muxes[] = {
+const struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 	},
 	[USBC_PORT_C1] = {
-		/* PS8815 DB */
-		.usb_port = USBC_PORT_C1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc1_usb3_db_retimer,
+		.mux = &(const struct usb_mux) {
+			/* PS8815 DB */
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc1_usb3_db_retimer,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
@@ -160,12 +167,11 @@ void board_reset_pd_mcu(void)
 	if (battery_hw_present())
 		gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 0);
 
-	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS,
-			   PS8815_PWR_H_RST_H_DELAY_MS));
+	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS));
 
 	gpio_set_level(GPIO_USB_C0_TCPC_RST_ODL, 1);
 	gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 1);
-	
+
 	/* wait for chips to come up */
 	msleep(PS8815_FW_INIT_DELAY_MS);
 }
diff --git a/board/gimble/usbc_config.h b/board/gimble/usbc_config.h
index 87e601ee3e..ab2dabc1e9 100644
--- a/board/gimble/usbc_config.h
+++ b/board/gimble/usbc_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,13 +8,9 @@
 #ifndef __CROS_EC_USBC_CONFIG_H
 #define __CROS_EC_USBC_CONFIG_H
 
-#define CONFIG_USB_PD_PORT_MAX_COUNT	2
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 void config_usb_db_type(void);
 
diff --git a/board/gingerbread/board.c b/board/gingerbread/board.c
index 3d80985c0a..8d14bda30c 100644
--- a/board/gingerbread/board.c
+++ b/board/gingerbread/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -31,8 +31,8 @@
 #include "usb_tc_sm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
 #define QUICHE_PD_DEBUG_LVL 1
 
@@ -102,27 +102,27 @@ static void board_pwr_btn_interrupt(enum gpio_signal signal)
  * signals is driven by USB/MST hub power sequencing requirements.
  */
 const struct power_seq board_power_seq[] = {
-	{GPIO_EN_AC_JACK,               1, 20},
-	{GPIO_EN_PP5000_A,              1, 31},
-	{GPIO_EN_PP3300_A,              1, 135},
-	{GPIO_EN_BB,                    1, 30},
-	{GPIO_EN_PP1100_A,              1, 30},
-	{GPIO_EN_PP1000_A,              1, 20},
-	{GPIO_EN_PP1050_A,              1, 30},
-	{GPIO_EN_PP1200_A,              1, 20},
-	{GPIO_EN_PP5000_HSPORT,         1, 31},
-	{GPIO_EN_DP_SINK,               1, 80},
-	{GPIO_MST_LP_CTL_L,             1, 80},
-	{GPIO_MST_RST_L,                1, 41},
-	{GPIO_EC_HUB1_RESET_L,          1, 41},
-	{GPIO_EC_HUB2_RESET_L,          1, 33},
-	{GPIO_USBC_DP_PD_RST_L,         1, 100},
-	{GPIO_USBC_UF_RESET_L,          1, 33},
-	{GPIO_DEMUX_DUAL_DP_PD_N,       1, 100},
-	{GPIO_DEMUX_DUAL_DP_RESET_N,    1, 100},
-	{GPIO_DEMUX_DP_HDMI_PD_N,       1, 10},
-	{GPIO_DEMUX_DUAL_DP_MODE,       1, 10},
-	{GPIO_DEMUX_DP_HDMI_MODE,       1, 1},
+	{ GPIO_EN_AC_JACK, 1, 20 },
+	{ GPIO_EN_PP5000_A, 1, 31 },
+	{ GPIO_EN_PP3300_A, 1, 135 },
+	{ GPIO_EN_BB, 1, 30 },
+	{ GPIO_EN_PP1100_A, 1, 30 },
+	{ GPIO_EN_PP1000_A, 1, 20 },
+	{ GPIO_EN_PP1050_A, 1, 30 },
+	{ GPIO_EN_PP1200_A, 1, 20 },
+	{ GPIO_EN_PP5000_HSPORT, 1, 31 },
+	{ GPIO_EN_DP_SINK, 1, 80 },
+	{ GPIO_MST_LP_CTL_L, 1, 80 },
+	{ GPIO_MST_RST_L, 1, 41 },
+	{ GPIO_EC_HUB1_RESET_L, 1, 41 },
+	{ GPIO_EC_HUB2_RESET_L, 1, 33 },
+	{ GPIO_USBC_DP_PD_RST_L, 1, 100 },
+	{ GPIO_USBC_UF_RESET_L, 1, 33 },
+	{ GPIO_DEMUX_DUAL_DP_PD_N, 1, 100 },
+	{ GPIO_DEMUX_DUAL_DP_RESET_N, 1, 100 },
+	{ GPIO_DEMUX_DP_HDMI_PD_N, 1, 10 },
+	{ GPIO_DEMUX_DUAL_DP_MODE, 1, 10 },
+	{ GPIO_DEMUX_DP_HDMI_MODE, 1, 1 },
 };
 
 const size_t board_power_seq_count = ARRAY_SIZE(board_power_seq);
@@ -131,13 +131,13 @@ const size_t board_power_seq_count = ARRAY_SIZE(board_power_seq);
  * Define the strings used in our USB descriptors.
  */
 const void *const usb_strings[] = {
-	[USB_STR_DESC]         = usb_string_desc,
-	[USB_STR_VENDOR]       = USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]      = USB_STRING_DESC("Gingerbread"),
-	[USB_STR_SERIALNO]     = 0,
-	[USB_STR_VERSION]      =
-			USB_STRING_DESC(CROS_EC_SECTION ":" CROS_EC_VERSION32),
-	[USB_STR_UPDATE_NAME]  = USB_STRING_DESC("Firmware update"),
+	[USB_STR_DESC] = usb_string_desc,
+	[USB_STR_VENDOR] = USB_STRING_DESC("Google LLC"),
+	[USB_STR_PRODUCT] = USB_STRING_DESC("Gingerbread"),
+	[USB_STR_SERIALNO] = 0,
+	[USB_STR_VERSION] =
+		USB_STRING_DESC(CROS_EC_SECTION ":" CROS_EC_VERSION32),
+	[USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"),
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
 
@@ -186,33 +186,33 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_HOST] = {
-		.usb_port = USB_PD_PORT_HOST,
-		.i2c_port = I2C_PORT_I2C1,
-		.i2c_addr_flags = TUSB1064_I2C_ADDR0_FLAGS,
-		.driver = &tusb1064_usb_mux_driver,
-		.board_set = &board_tusb1064_dp_rx_eq_set,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_HOST,
+			.i2c_port = I2C_PORT_I2C1,
+			.i2c_addr_flags = TUSB1064_I2C_ADDR0_FLAGS,
+			.driver = &tusb1064_usb_mux_driver,
+			.board_set = &board_tusb1064_dp_rx_eq_set,
+		},
 	},
 	[USB_PD_PORT_DP] = {
-		.usb_port = USB_PD_PORT_DP,
-		.i2c_port = I2C_PORT_I2C3,
-		.i2c_addr_flags = PS8XXX_I2C_ADDR2_FLAGS,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_DP,
+			.i2c_port = I2C_PORT_I2C3,
+			.i2c_addr_flags = PS8XXX_I2C_ADDR2_FLAGS,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 	},
 };
 
 /* USB-C PPC Configuration */
 struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_HOST] = {
-		.i2c_port = I2C_PORT_I2C3,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	[USB_PD_PORT_DP] = {
-		.drv = &board_ppc_null_drv
-	},
+	[USB_PD_PORT_HOST] = { .i2c_port = I2C_PORT_I2C3,
+			       .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+			       .drv = &sn5s330_drv },
+	[USB_PD_PORT_DP] = { .drv = &board_ppc_null_drv },
 };
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
@@ -239,7 +239,6 @@ void board_reset_pd_mcu(void)
 	msleep(PS8805_FW_INIT_DELAY_MS);
 }
 
-
 /* Power Delivery and charging functions */
 void board_enable_usbc_interrupts(void)
 {
@@ -253,7 +252,6 @@ void board_enable_usbc_interrupts(void)
 
 	/* Enable HPD interrupt */
 	gpio_enable_interrupt(GPIO_DDI_MST_IN_HPD);
-
 }
 
 /* Power Delivery and charging functions */
@@ -267,7 +265,6 @@ void board_disable_usbc_interrupts(void)
 
 	/* Disable HPD interrupt */
 	gpio_disable_interrupt(GPIO_DDI_MST_IN_HPD);
-
 }
 
 void board_tcpc_init(void)
@@ -351,7 +348,7 @@ static void board_usb_tc_disconnect(void)
 		gpio_set_level(GPIO_EC_HUB2_RESET_L, 0);
 	}
 }
-DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, board_usb_tc_disconnect, \
+DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, board_usb_tc_disconnect,
 	     HOOK_PRIO_DEFAULT);
 
 #endif /* SECTION_IS_RW */
diff --git a/board/gingerbread/board.h b/board/gingerbread/board.h
index cfc5bbf0a0..09e9e0b7fe 100644
--- a/board/gingerbread/board.h
+++ b/board/gingerbread/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,7 +20,6 @@
 #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
 #undef CONFIG_FLASH_PSTATE_LOCKED
 
-
 #define CONFIG_WP_ACTIVE_HIGH
 
 /* Console */
@@ -29,8 +28,8 @@
 #define CONFIG_UART_TX_DMA_PH DMAMUX_REQ_USART3_TX
 
 /* USB Type C and USB PD defines */
-#define USB_PD_PORT_HOST   0
-#define USB_PD_PORT_DP   1
+#define USB_PD_PORT_HOST 0
+#define USB_PD_PORT_DP 1
 
 #define CONFIG_USB_PD_PORT_MAX_COUNT 2
 #define CONFIG_USB_MUX_TUSB1064
@@ -44,13 +43,13 @@
 #define CONFIG_USB_PD_IDENTITY_SW_VERS 1
 
 /* I2C port names */
-#define I2C_PORT_I2C1	0
-#define I2C_PORT_I2C2	1
-#define I2C_PORT_I2C3	2
+#define I2C_PORT_I2C1 0
+#define I2C_PORT_I2C2 1
+#define I2C_PORT_I2C3 2
 /* Required symbolic I2C port names */
 #define I2C_PORT_MP4245 I2C_PORT_I2C3
 #define I2C_PORT_EEPROM I2C_PORT_I2C1
-#define MP4245_I2C_ADDR_FLAGS  MP4245_I2C_ADDR_0_FLAGS
+#define MP4245_I2C_ADDR_FLAGS MP4245_I2C_ADDR_0_FLAGS
 
 /*
  * Macros for GPIO signals used in common code that don't match the
@@ -58,9 +57,9 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_ENTERING_RW	GPIO_EC_ENTERING_RW
-#define GPIO_WP_L		GPIO_EC_WP_L
-#define GPIO_WP		GPIO_EC_WP_L
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_WP GPIO_EC_WP_L
 
 /* Include math_util for bitmask_uint64 used in pd_timers */
 #define CONFIG_MATH_UTIL
@@ -80,7 +79,7 @@
 #define GPIO_TRIGGER_1 GPIO_USB3_A1_CDP_EN
 #define GPIO_TRIGGER_2 GPIO_USB3_A2_CDP_EN
 
-enum  debug_gpio {
+enum debug_gpio {
 	TRIGGER_1 = 0,
 	TRIGGER_2,
 };
diff --git a/board/gingerbread/build.mk b/board/gingerbread/build.mk
index f994cc1434..d7ca7b35b5 100644
--- a/board/gingerbread/build.mk
+++ b/board/gingerbread/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/gingerbread/ec.tasklist b/board/gingerbread/ec.tasklist
index cc36bf5a74..ffd4a604c9 100644
--- a/board/gingerbread/ec.tasklist
+++ b/board/gingerbread/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/gingerbread/gpio.inc b/board/gingerbread/gpio.inc
index 6226ff747e..4da3c973c1 100644
--- a/board/gingerbread/gpio.inc
+++ b/board/gingerbread/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/gooey/battery.c b/board/gooey/battery.c
index c40e0d7ec7..e8cec5af5f 100644
--- a/board/gooey/battery.c
+++ b/board/gooey/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/gooey/board.c b/board/gooey/board.c
index fe7e2c3792..250f6afd61 100644
--- a/board/gooey/board.c
+++ b/board/gooey/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -40,7 +40,7 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
 #define INT_RECHECK_US 5000
 
 /* C0 interrupt line shared by BC 1.2 and charger */
@@ -84,7 +84,6 @@ static void usb_c0_interrupt(enum gpio_signal s)
 
 	/* Check the line again in 5ms */
 	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-
 }
 
 static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
@@ -114,8 +113,7 @@ DECLARE_DEFERRED(pendetect_deferred);
 void pen_detect_interrupt(enum gpio_signal s)
 {
 	/* Trigger deferred notification of pen detect change */
-	hook_call_deferred(&pendetect_deferred_data,
-			500 * MSEC);
+	hook_call_deferred(&pendetect_deferred_data, 500 * MSEC);
 }
 
 void board_hibernate(void)
@@ -132,27 +130,21 @@ void board_hibernate(void)
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH0
-	},
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH2
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH3
-	},
+	[ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH0 },
+	[ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH2 },
+	[ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH3 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
@@ -188,12 +180,15 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 };
 
 /* USB Muxes */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+			},
 	},
 };
 
@@ -291,7 +286,6 @@ int board_is_sourcing_vbus(int port)
 
 	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
 	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
-
 }
 
 int board_set_active_charge_port(int port)
@@ -303,8 +297,7 @@ int board_set_active_charge_port(int port)
 
 	/* Disable all ports. */
 	if (port == CHARGE_PORT_NONE) {
-		tcpc_write(0, TCPC_REG_COMMAND,
-				TCPC_REG_COMMAND_SNK_CTRL_LOW);
+		tcpc_write(0, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
 		raa489000_enable_asgate(0, false);
 		return EC_SUCCESS;
 	}
@@ -317,8 +310,7 @@ int board_set_active_charge_port(int port)
 
 	/* Enable requested charge port. */
 	if (raa489000_enable_asgate(port, true) ||
-	    tcpc_write(0, TCPC_REG_COMMAND,
-		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
+	    tcpc_write(0, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
 		CPRINTUSB("p%d: sink path enable failed.", port);
 		return EC_ERROR_UNKNOWN;
 	}
@@ -360,17 +352,13 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrices to rotate accelerometers into the standard reference. */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, FLOAT_TO_FP(1), 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
 
 /* Sensor Data */
 static struct stprivate_data g_lis2dwl_data;
@@ -452,14 +440,14 @@ const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
 /* Thermistors */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -508,8 +496,8 @@ static const struct ec_response_keybd_config gooey_keybd = {
 	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
 };
 
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	return &gooey_keybd;
 }
diff --git a/board/gooey/board.h b/board/gooey/board.h
index 4681fb5dcf..b586c0f334 100644
--- a/board/gooey/board.h
+++ b/board/gooey/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,9 +24,12 @@
 /* Charger */
 #define CONFIG_CHARGE_RAMP_HW
 #define CONFIG_CHARGER_RAA489000
+#define PD_MAX_VOLTAGE_MV 20000
 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 #define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */
+#define CONFIG_OCPC_DEF_RBATT_MOHMS               \
+	22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \
+	    */
 #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
 #define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
 
@@ -40,8 +43,8 @@
 #define CONFIG_PWM
 
 /* Sensors */
-#define CONFIG_ACCEL_LIS2DWL		/* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM	/* Base accel */
+#define CONFIG_ACCEL_LIS2DWL /* Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
 #define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 /* Sensors without hardware FIFO are in forced mode */
@@ -109,26 +112,17 @@ enum pwm_channel {
 };
 
 /* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
 /* ADC channels */
 enum adc_channel {
-	ADC_VSNS_PP3300_A,     /* ADC0 */
-	ADC_TEMP_SENSOR_1,     /* ADC2 */
-	ADC_TEMP_SENSOR_2,     /* ADC3 */
+	ADC_VSNS_PP3300_A, /* ADC0 */
+	ADC_TEMP_SENSOR_1, /* ADC2 */
+	ADC_TEMP_SENSOR_2, /* ADC3 */
 	ADC_CH_COUNT
 };
 
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_COUNT
-};
+enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
diff --git a/board/gooey/build.mk b/board/gooey/build.mk
index ff15b3e8e4..f65b5e8f0c 100644
--- a/board/gooey/build.mk
+++ b/board/gooey/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/gooey/ec.tasklist b/board/gooey/ec.tasklist
index bdcbcdf074..8ccdfc81b2 100644
--- a/board/gooey/ec.tasklist
+++ b/board/gooey/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/gooey/gpio.inc b/board/gooey/gpio.inc
index 1eaae9e354..8eb1f5ef22 100644
--- a/board/gooey/gpio.inc
+++ b/board/gooey/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/gooey/led.c b/board/gooey/led.c
index 6d55ce2932..5c7eb08407 100644
--- a/board/gooey/led.c
+++ b/board/gooey/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,41 +11,46 @@
 #include "gpio.h"
 #include "pwm.h"
 
-#define LED_OFF_LVL	0
-#define LED_ON_LVL	1
+#define LED_OFF_LVL 0
+#define LED_ON_LVL 1
 
 __override const int led_charge_lvl_1 = 5;
 
 __override const int led_charge_lvl_2 = 97;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED,   LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,   1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
 
 __override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]            = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]    = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-					 {LED_OFF,         0.5 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-					{LED_OFF,         0.5 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF,            LED_INDEFINITE} },
-};
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 3 * LED_ONE_SEC },
+					       { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    3 * LED_ONE_SEC },
+						  { LED_OFF,
+						    0.5 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
diff --git a/board/gooey/usb_pd_policy.c b/board/gooey/usb_pd_policy.c
index b7c0ca21df..a7633b73ac 100644
--- a/board/gooey/usb_pd_policy.c
+++ b/board/gooey/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,8 +13,8 @@
 #include "driver/tcpm/tcpci.h"
 #include "usb_pd.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
diff --git a/board/goroh/battery.c b/board/goroh/battery.c
index f76af4d99b..4da7b255e0 100644
--- a/board/goroh/battery.c
+++ b/board/goroh/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/goroh/board.c b/board/goroh/board.c
index c99b0deff6..a9eaa35b92 100644
--- a/board/goroh/board.c
+++ b/board/goroh/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -41,9 +41,9 @@
 #include "usb_pd_tcpm.h"
 #include "usbc_ppc.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* Initialize board. */
 static void board_init(void)
@@ -55,41 +55,35 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
-	{ "BOARD_ID",     ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH1 },
-	{ "TEMP_CPU",     ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH2 },
-	{ "TEMP_GPU",     ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH3 },
+	{ "BOARD_ID", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH1 },
+	{ "TEMP_CPU", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH2 },
+	{ "TEMP_GPU", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH3 },
 	{ "TEMP_CHARGER", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH5 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* PWM channels.  */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED_GREEN] = {
-		.channel = PWM_HW_CH_DCR0,
-		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_OPEN_DRAIN |
-			 PWM_CONFIG_ACTIVE_LOW,
-		.freq_hz = 324, /* maximum supported frequency */
-		.pcfsr_sel = PWM_PRESCALER_C4
-	},
-	[PWM_CH_LED_RED] = {
-		.channel = PWM_HW_CH_DCR1,
-		.flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_OPEN_DRAIN |
-			 PWM_CONFIG_ACTIVE_LOW,
-		.freq_hz = 324, /* maximum supported frequency */
-		.pcfsr_sel = PWM_PRESCALER_C4
-	},
-	[PWM_CH_FAN] = {
-		.channel = PWM_HW_CH_DCR2,
-		.flags = PWM_CONFIG_OPEN_DRAIN,
-		.freq_hz = 25000, /* maximum supported frequency */
-		.pcfsr_sel = PWM_PRESCALER_C4
-	},
-	[PWM_CH_KBLIGHT] = {
-		.channel = PWM_HW_CH_DCR3,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq_hz = 25000,
-		.pcfsr_sel = PWM_PRESCALER_C4
-	},
+	[PWM_CH_LED_GREEN] = { .channel = PWM_HW_CH_DCR0,
+			       .flags = PWM_CONFIG_DSLEEP |
+					PWM_CONFIG_OPEN_DRAIN |
+					PWM_CONFIG_ACTIVE_LOW,
+			       .freq_hz = 324, /* maximum supported frequency */
+			       .pcfsr_sel = PWM_PRESCALER_C4 },
+	[PWM_CH_LED_RED] = { .channel = PWM_HW_CH_DCR1,
+			     .flags = PWM_CONFIG_DSLEEP |
+				      PWM_CONFIG_OPEN_DRAIN |
+				      PWM_CONFIG_ACTIVE_LOW,
+			     .freq_hz = 324, /* maximum supported frequency */
+			     .pcfsr_sel = PWM_PRESCALER_C4 },
+	[PWM_CH_FAN] = { .channel = PWM_HW_CH_DCR2,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq_hz = 25000, /* maximum supported frequency */
+			 .pcfsr_sel = PWM_PRESCALER_C4 },
+	[PWM_CH_KBLIGHT] = { .channel = PWM_HW_CH_DCR3,
+			     .flags = PWM_CONFIG_DSLEEP,
+			     .freq_hz = 25000,
+			     .pcfsr_sel = PWM_PRESCALER_C4 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
diff --git a/board/goroh/board.h b/board/goroh/board.h
index c5b1758aa4..b15c7de076 100644
--- a/board/goroh/board.h
+++ b/board/goroh/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -46,7 +46,7 @@
 #define CONFIG_CMD_SCRATCHPAD
 #define CONFIG_CMD_STACKOVERFLOW
 
-#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV	9000
+#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV 9000
 
 /* Sensor */
 #define CONFIG_GMR_TABLET_MODE
@@ -99,20 +99,16 @@ enum sensor_id {
 };
 
 enum adc_channel {
-	ADC_BOARD_ID,            /* ADC 1 */
-	ADC_TEMP_SENSOR_CPU,     /* ADC 2 */
-	ADC_TEMP_SENSOR_GPU,     /* ADC 3 */
+	ADC_BOARD_ID, /* ADC 1 */
+	ADC_TEMP_SENSOR_CPU, /* ADC 2 */
+	ADC_TEMP_SENSOR_GPU, /* ADC 3 */
 	ADC_TEMP_SENSOR_CHARGER, /* ADC 5 */
 
 	/* Number of ADC channels */
 	ADC_CH_COUNT,
 };
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 enum pwm_channel {
 	PWM_CH_LED_GREEN,
@@ -122,10 +118,7 @@ enum pwm_channel {
 	PWM_CH_COUNT,
 };
 
-enum fan_channel {
-	FAN_CH_0,
-	FAN_CH_COUNT
-};
+enum fan_channel { FAN_CH_0, FAN_CH_COUNT };
 
 enum temp_sensor_id {
 	TEMP_SENSOR_CPU,
diff --git a/board/goroh/build.mk b/board/goroh/build.mk
index 4bc0561678..5f2dea191a 100644
--- a/board/goroh/build.mk
+++ b/board/goroh/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/goroh/ec.tasklist b/board/goroh/ec.tasklist
index 6bc80781d8..148b7679ae 100644
--- a/board/goroh/ec.tasklist
+++ b/board/goroh/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/goroh/fans.c b/board/goroh/fans.c
index 415eb9681d..1ac9a79acb 100644
--- a/board/goroh/fans.c
+++ b/board/goroh/fans.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/goroh/gpio.inc b/board/goroh/gpio.inc
index 9d10ea37bd..5d534044fe 100644
--- a/board/goroh/gpio.inc
+++ b/board/goroh/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/goroh/led.c b/board/goroh/led.c
index 63f00ef82e..7ed155acc0 100644
--- a/board/goroh/led.c
+++ b/board/goroh/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,13 +9,10 @@
 #include "pwm.h"
 
 struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = {
-				/* Green, Red */
-	[EC_LED_COLOR_RED]    = {   0, 100 },
-	[EC_LED_COLOR_GREEN]  = { 100,   0 },
-	[EC_LED_COLOR_BLUE]   = {   0,   0 },
-	[EC_LED_COLOR_YELLOW] = {   0,   0 },
-	[EC_LED_COLOR_WHITE]  = {   0,   0 },
-	[EC_LED_COLOR_AMBER]  = {   0,   0 },
+	/* Green, Red */
+	[EC_LED_COLOR_RED] = { 0, 100 }, [EC_LED_COLOR_GREEN] = { 100, 0 },
+	[EC_LED_COLOR_BLUE] = { 0, 0 },	 [EC_LED_COLOR_YELLOW] = { 0, 0 },
+	[EC_LED_COLOR_WHITE] = { 0, 0 }, [EC_LED_COLOR_AMBER] = { 0, 0 },
 };
 
 struct pwm_led pwm_leds[CONFIG_LED_PWM_COUNT] = {
diff --git a/board/goroh/sensors.c b/board/goroh/sensors.c
index fe0a50b762..4499ebf64c 100644
--- a/board/goroh/sensors.c
+++ b/board/goroh/sensors.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/goroh/usbc_confg.c b/board/goroh/usbc_confg.c
index 57a52da986..2f1b4a021f 100644
--- a/board/goroh/usbc_confg.c
+++ b/board/goroh/usbc_confg.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/grunt/battery.c b/board/grunt/battery.c
index 359ec9785b..7c7ec44c56 100644
--- a/board/grunt/battery.c
+++ b/board/grunt/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/grunt/board.c b/board/grunt/board.c
index 0efa8b9696..9c4666fec5 100644
--- a/board/grunt/board.c
+++ b/board/grunt/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,52 +25,40 @@ const enum gpio_signal hibernate_wake_pins[] = {
 	GPIO_AC_PRESENT,
 	GPIO_POWER_BUTTON_L,
 };
-const int hibernate_wake_pins_used =  ARRAY_SIZE(hibernate_wake_pins);
+const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 
 /* I2C port map. */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl  = GPIO_I2C0_SCL,
-		.sda  = GPIO_I2C0_SDA
-	},
-	{
-		.name = "tcpc0",
-		.port = I2C_PORT_TCPC0,
-		.kbps = 400,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	},
-	{
-		.name = "tcpc1",
-		.port = I2C_PORT_TCPC1,
-		.kbps = 400,
-		.scl  = GPIO_I2C2_SCL,
-		.sda  = GPIO_I2C2_SDA
-	},
-	{
-		.name = "thermal",
-		.port = I2C_PORT_THERMAL_AP,
-		.kbps = 400,
-		.scl  = GPIO_I2C3_SCL,
-		.sda  = GPIO_I2C3_SDA
-	},
-	{
-		.name = "kblight",
-		.port = I2C_PORT_KBLIGHT,
-		.kbps = 100,
-		.scl  = GPIO_I2C5_SCL,
-		.sda  = GPIO_I2C5_SDA
-	},
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl  = GPIO_I2C7_SCL,
-		.sda  = GPIO_I2C7_SDA
-	},
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_I2C0_SCL,
+	  .sda = GPIO_I2C0_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "tcpc1",
+	  .port = I2C_PORT_TCPC1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "thermal",
+	  .port = I2C_PORT_THERMAL_AP,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
+	{ .name = "kblight",
+	  .port = I2C_PORT_KBLIGHT,
+	  .kbps = 100,
+	  .scl = GPIO_I2C5_SCL,
+	  .sda = GPIO_I2C5_SDA },
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_I2C7_SCL,
+	  .sda = GPIO_I2C7_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
diff --git a/board/grunt/board.h b/board/grunt/board.h
index fe0d9e3d0f..b8cb063dee 100644
--- a/board/grunt/board.h
+++ b/board/grunt/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,7 @@
  * By default, enable all console messages excepted HC, ACPI and event:
  * The sensor stack is generating a lot of activity.
  */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
 #undef CONFIG_HOSTCMD_DEBUG_MODE
 #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
 
@@ -62,7 +62,7 @@
 /*
  * Slew rate on the PP1800_SENSOR load switch requires a short delay on startup.
  */
-#undef  CONFIG_MOTION_SENSE_RESUME_DELAY_US
+#undef CONFIG_MOTION_SENSE_RESUME_DELAY_US
 #define CONFIG_MOTION_SENSE_RESUME_DELAY_US (10 * MSEC)
 
 #ifndef __ASSEMBLER__
diff --git a/board/grunt/build.mk b/board/grunt/build.mk
index c808e65aed..d24127ddae 100644
--- a/board/grunt/build.mk
+++ b/board/grunt/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/grunt/ec.tasklist b/board/grunt/ec.tasklist
index dc898c4502..9572d61c8f 100644
--- a/board/grunt/ec.tasklist
+++ b/board/grunt/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/grunt/gpio.inc b/board/grunt/gpio.inc
index 97f5afabfd..8c75686f47 100644
--- a/board/grunt/gpio.inc
+++ b/board/grunt/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/grunt/led.c b/board/grunt/led.c
index 824ec55f6c..0a7a794bfd 100644
--- a/board/grunt/led.c
+++ b/board/grunt/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,13 +19,10 @@ const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
  * both LEDs being off.
  */
 struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = {
-				/* Amber, Blue */
-	[EC_LED_COLOR_RED]    = {   0,   0 },
-	[EC_LED_COLOR_GREEN]  = {   0,   0 },
-	[EC_LED_COLOR_BLUE]   = {   0, 100 },
-	[EC_LED_COLOR_YELLOW] = {   0,   0 },
-	[EC_LED_COLOR_WHITE]  = {   0,   0 },
-	[EC_LED_COLOR_AMBER]  = {  100,  0 },
+	/* Amber, Blue */
+	[EC_LED_COLOR_RED] = { 0, 0 },	  [EC_LED_COLOR_GREEN] = { 0, 0 },
+	[EC_LED_COLOR_BLUE] = { 0, 100 }, [EC_LED_COLOR_YELLOW] = { 0, 0 },
+	[EC_LED_COLOR_WHITE] = { 0, 0 },  [EC_LED_COLOR_AMBER] = { 100, 0 },
 };
 
 /* One logical LED with amber and blue channels. */
diff --git a/board/gumboz/battery.c b/board/gumboz/battery.c
index 7d1831fdbc..8b9b3ddf96 100644
--- a/board/gumboz/battery.c
+++ b/board/gumboz/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/gumboz/board.c b/board/gumboz/board.c
index f90902f765..82522ada4d 100644
--- a/board/gumboz/board.c
+++ b/board/gumboz/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,7 +10,7 @@
 #include "driver/accel_kionix.h"
 #include "driver/accelgyro_lsm6dsm.h"
 #include "driver/bc12/pi3usb9201.h"
-#include "driver/ppc/aoz1380.h"
+#include "driver/ppc/aoz1380_public.h"
 #include "driver/ppc/nx20p348x.h"
 #include "driver/tcpm/nct38xx.h"
 #include "driver/usb_mux/amd_fp5.h"
@@ -36,8 +36,8 @@
 #include "usb_pd_tcpm.h"
 #include "usbc_ppc.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* This I2C moved. Temporarily detect and support the V0 HW. */
 int I2C_PORT_BATTERY = I2C_PORT_BATTERY_V1;
@@ -49,21 +49,17 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* sensor private data */
-static struct kionix_accel_data  g_kx022_data;
+static struct kionix_accel_data g_kx022_data;
 static struct lsm6dsm_data g_lsm6dsm_data = LSM6DSM_DATA;
 
 /* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
 
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, FLOAT_TO_FP(-1), 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
 
 /* TODO(gcc >= 5.0) Remove the casts to const pointer at rot_standard_ref */
 struct motion_sensor_t motion_sensors[] = {
@@ -199,33 +195,43 @@ const struct usb_mux_driver usbc0_sbu_mux_driver = {
  * Since PI3USB221 is not a i2c device, .i2c_port and
  * .i2c_addr_flags are not required here.
  */
-const struct usb_mux usbc0_sbu_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &usbc0_sbu_mux_driver,
+const struct usb_mux_chain usbc0_sbu_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &usbc0_sbu_mux_driver,
+		},
 };
 
-struct usb_mux usbc1_amd_fp5_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.i2c_port = I2C_PORT_USB_AP_MUX,
-	.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
-	.driver = &amd_fp5_usb_mux_driver,
-	.flags = USB_MUX_FLAG_SET_WITHOUT_FLIP,
+struct usb_mux_chain usbc1_amd_fp5_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.i2c_port = I2C_PORT_USB_AP_MUX,
+			.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
+			.driver = &amd_fp5_usb_mux_driver,
+			.flags = USB_MUX_FLAG_SET_WITHOUT_FLIP,
+		},
 };
 
-struct usb_mux usb_muxes[] = {
+struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.i2c_port = I2C_PORT_USB_AP_MUX,
-		.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
-		.driver = &amd_fp5_usb_mux_driver,
-		.next_mux = &usbc0_sbu_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.i2c_port = I2C_PORT_USB_AP_MUX,
+			.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
+			.driver = &amd_fp5_usb_mux_driver,
+		},
+		.next = &usbc0_sbu_mux,
 	},
 	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = PS8743_I2C_ADDR1_FLAG,
-		.driver = &ps8743_usb_mux_driver,
-		.next_mux = &usbc1_amd_fp5_usb_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.i2c_port = I2C_PORT_TCPC1,
+			.i2c_addr_flags = PS8743_I2C_ADDR1_FLAG,
+			.driver = &ps8743_usb_mux_driver,
+		},
+		.next = &usbc1_amd_fp5_usb_mux,
 	}
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
@@ -268,8 +274,7 @@ void ppc_interrupt(enum gpio_signal signal)
 
 int board_set_active_charge_port(int port)
 {
-	int is_valid_port = (port >= 0 &&
-			     port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	int i;
 
 	if (port == CHARGE_PORT_NONE) {
@@ -290,7 +295,6 @@ int board_set_active_charge_port(int port)
 		return EC_ERROR_INVAL;
 	}
 
-
 	/* Check if the port is sourcing VBUS. */
 	if (ppc_is_sourcing_vbus(port)) {
 		CPRINTFUSB("Skip enable C%d", port);
@@ -392,7 +396,6 @@ static void reset_nct38xx_port(int port)
 		msleep(NCT3807_RESET_POST_DELAY_MS);
 }
 
-
 void board_reset_pd_mcu(void)
 {
 	/* Reset TCPC0 */
@@ -463,11 +466,9 @@ int board_pd_set_frs_enable(int port, int enable)
 
 	/* Use the TCPC to enable fast switch when FRS included */
 	if (port == USBC_PORT_C0) {
-		rv = ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN,
-				    !!enable);
+		rv = ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN, !!enable);
 	} else {
-		rv = ioex_set_level(IOEX_USB_C1_TCPC_FASTSW_CTL_EN,
-				    !!enable);
+		rv = ioex_set_level(IOEX_USB_C1_TCPC_FASTSW_CTL_EN, !!enable);
 	}
 
 	return rv;
@@ -539,14 +540,13 @@ int usb_port_enable[USBA_PORT_COUNT] = {
  * The connector has 24 pins total, and there is no pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-		{0, 5}, {1, 1}, {1, 0}, {0, 6}, {0, 7},
-		{1, 4}, {1, 3}, {1, 6}, {1, 7}, {3, 1},
-		{2, 0}, {1, 5}, {2, 6}, {2, 7}, {2, 1},
-		{2, 4}, {2, 5}, {1, 2}, {2, 3}, {2, 2},
-		{3, 0}, {-1, -1}, {-1, -1}, {-1, -1},
+	{ 0, 5 }, { 1, 1 }, { 1, 0 }, { 0, 6 },	  { 0, 7 },   { 1, 4 },
+	{ 1, 3 }, { 1, 6 }, { 1, 7 }, { 3, 1 },	  { 2, 0 },   { 1, 5 },
+	{ 2, 6 }, { 2, 7 }, { 2, 1 }, { 2, 4 },	  { 2, 5 },   { 1, 2 },
+	{ 2, 3 }, { 2, 2 }, { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 },
 };
 const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 #endif
 
 #define CHARGING_CURRENT_500MA 500
@@ -586,12 +586,11 @@ int charger_profile_override(struct charge_state_data *curr)
 	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
 		return 0;
 
-	curr->requested_current = (limit_charge) ? CHARGING_CURRENT_500MA
-						 : curr->batt.desired_current;
+	curr->requested_current = (limit_charge) ? CHARGING_CURRENT_500MA :
+						   curr->batt.desired_current;
 
 	if (limit_usbc_power != limit_usbc_power_backup) {
-		rp = (limit_usbc_power) ? TYPEC_RP_1A5
-					: TYPEC_RP_3A0;
+		rp = (limit_usbc_power) ? TYPEC_RP_1A5 : TYPEC_RP_3A0;
 
 		ppc_set_vbus_source_current_limit(0, rp);
 		tcpm_select_rp_value(0, rp);
@@ -605,13 +604,13 @@ int charger_profile_override(struct charge_state_data *curr)
 }
 
 enum ec_status charger_profile_override_get_param(uint32_t param,
-							uint32_t *value)
+						  uint32_t *value)
 {
 	return EC_RES_INVALID_PARAM;
 }
 
 enum ec_status charger_profile_override_set_param(uint32_t param,
-							uint32_t value)
+						  uint32_t value)
 {
 	return EC_RES_INVALID_PARAM;
 }
diff --git a/board/gumboz/board.h b/board/gumboz/board.h
index 42e2b23c32..b2f7682ed8 100644
--- a/board/gumboz/board.h
+++ b/board/gumboz/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,7 +20,7 @@
 #define CONFIG_USB_PD_PORT_MAX_COUNT 2
 #define CONFIG_USB_PORT_ENABLE_DYNAMIC
 
-#undef  CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
+#undef CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
 #define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 40000
 
 #define CONFIG_CHARGER_PROFILE_OVERRIDE
@@ -38,7 +38,7 @@
 #define CONFIG_ACCELGYRO_LSM6DSM
 #define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-#define CONFIG_ACCEL_KX022		/* Lid accel */
+#define CONFIG_ACCEL_KX022 /* Lid accel */
 #define CONFIG_CMD_ACCELS
 #define CONFIG_CMD_ACCEL_INFO
 #define CONFIG_TABLET_MODE
@@ -48,42 +48,36 @@
 #define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
 #define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
 
-
-
 /* GPIO mapping from board specific name to EC common name. */
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_EC_BATT_PRES_ODL
-#define CONFIG_SCI_GPIO			GPIO_EC_FCH_SCI_ODL
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_AP_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT_L		GPIO_EC_EDP_BL_DISABLE
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_FCH_PWR_BTN_L
-#define GPIO_PCH_RSMRST_L		GPIO_EC_FCH_RSMRST_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S5_L		GPIO_SLP_S5_L
-#define GPIO_PCH_SYS_PWROK		GPIO_EC_FCH_PWROK
-#define GPIO_PCH_WAKE_L			GPIO_EC_FCH_WAKE_L
-#define GPIO_POWER_BUTTON_L		GPIO_EC_PWR_BTN_ODL
-#define GPIO_S0_PGOOD			GPIO_S0_PWROK_OD
-#define GPIO_S5_PGOOD			GPIO_EC_PWROK_OD
-#define GPIO_SYS_RESET_L		GPIO_EC_SYS_RST_L
-#define GPIO_VOLUME_DOWN_L		GPIO_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
+#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL
+#define CONFIG_SCI_GPIO GPIO_EC_FCH_SCI_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_AP_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_EDP_BL_DISABLE
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PCH_PWRBTN_L GPIO_EC_FCH_PWR_BTN_L
+#define GPIO_PCH_RSMRST_L GPIO_EC_FCH_RSMRST_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L
+#define GPIO_PCH_SYS_PWROK GPIO_EC_FCH_PWROK
+#define GPIO_PCH_WAKE_L GPIO_EC_FCH_WAKE_L
+#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL
+#define GPIO_S0_PGOOD GPIO_S0_PWROK_OD
+#define GPIO_S5_PGOOD GPIO_EC_PWROK_OD
+#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L
+#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
 
 #ifndef __ASSEMBLER__
 
 /* This I2C moved. Temporarily detect and support the V0 HW. */
 extern int I2C_PORT_BATTERY;
 
-enum adc_channel {
-	ADC_TEMP_SENSOR_CHARGER,
-	ADC_TEMP_SENSOR_SOC,
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_TEMP_SENSOR_CHARGER, ADC_TEMP_SENSOR_SOC, ADC_CH_COUNT };
 
 enum battery_type {
 	BATTERY_SIMPLO_COS,
@@ -95,20 +89,11 @@ enum battery_type {
 	BATTERY_TYPE_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_COUNT };
 
-enum ioex_port {
-	IOEX_C0_NCT3807 = 0,
-	IOEX_C1_NCT3807,
-	IOEX_PORT_COUNT
-};
+enum ioex_port { IOEX_C0_NCT3807 = 0, IOEX_C1_NCT3807, IOEX_PORT_COUNT };
 
-#define PORT_TO_HPD(port) ((port == 0) \
-	? GPIO_USB3_C0_DP2_HPD \
-	: GPIO_DP1_HPD)
+#define PORT_TO_HPD(port) ((port == 0) ? GPIO_USB3_C0_DP2_HPD : GPIO_DP1_HPD)
 
 enum temp_sensor_id {
 	TEMP_SENSOR_CHARGER = 0,
@@ -117,17 +102,9 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum usba_port {
-	USBA_PORT_A0 = 0,
-	USBA_PORT_A1,
-	USBA_PORT_COUNT
-};
+enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT };
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 /*****************************************************************************
  * CBI EC FW Configuration
diff --git a/board/gumboz/build.mk b/board/gumboz/build.mk
index 1c0cbc4f63..45c71f962c 100644
--- a/board/gumboz/build.mk
+++ b/board/gumboz/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/gumboz/ec.tasklist b/board/gumboz/ec.tasklist
index d9c1606eb2..abc796f74f 100644
--- a/board/gumboz/ec.tasklist
+++ b/board/gumboz/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/gumboz/gpio.inc b/board/gumboz/gpio.inc
index 9beaecc17a..2e7e4b78a9 100644
--- a/board/gumboz/gpio.inc
+++ b/board/gumboz/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/gumboz/led.c b/board/gumboz/led.c
index ac27fe3a2c..95f61494f9 100644
--- a/board/gumboz/led.c
+++ b/board/gumboz/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,11 +23,9 @@
 #define LED_TICKS_PER_CYCLE 10
 #define LED_ON_TICKS 5
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_LEFT_LED,
-	EC_LED_ID_RIGHT_LED,
-	EC_LED_ID_POWER_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_LEFT_LED,
+					     EC_LED_ID_RIGHT_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -35,13 +33,10 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
-enum led_port {
-	LEFT_PORT = 0,
-	RIGHT_PORT
-};
+enum led_port { LEFT_PORT = 0, RIGHT_PORT };
 
 static void led_set_color_battery(int port, enum led_color color)
 {
@@ -51,9 +46,9 @@ static void led_set_color_battery(int port, enum led_color color)
 
 	cbi_get_board_version(&board_ver);
 	amber_led = (port == LEFT_PORT ? GPIO_LED_CHRG_L :
-				 IOEX_C1_CHARGER_LED_AMBER_DB);
+					 IOEX_C1_CHARGER_LED_AMBER_DB);
 	white_led = (port == LEFT_PORT ? GPIO_LED_FULL_L :
-				 IOEX_C1_CHARGER_LED_WHITE_DB);
+					 IOEX_C1_CHARGER_LED_WHITE_DB);
 
 	if ((board_ver >= 2) && (port == RIGHT_PORT)) {
 		led_batt_on_lvl = 1;
@@ -156,16 +151,15 @@ static void set_active_port_color(enum led_color color)
 
 	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
 		led_set_color_battery(RIGHT_PORT,
-				(port == RIGHT_PORT) ? color : LED_OFF);
+				      (port == RIGHT_PORT) ? color : LED_OFF);
 	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
 		led_set_color_battery(LEFT_PORT,
-				(port == LEFT_PORT) ? color : LED_OFF);
+				      (port == LEFT_PORT) ? color : LED_OFF);
 }
 
 static void led_set_battery(void)
 {
 	static int battery_ticks;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
@@ -177,9 +171,12 @@ static void led_set_battery(void)
 	case PWR_STATE_DISCHARGE:
 		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
 			if (charge_get_percent() < 10)
-				led_set_color_battery(RIGHT_PORT,
-					(battery_ticks % LED_TICKS_PER_CYCLE
-					 < LED_ON_TICKS) ? LED_WHITE : LED_OFF);
+				led_set_color_battery(
+					RIGHT_PORT,
+					(battery_ticks % LED_TICKS_PER_CYCLE <
+					 LED_ON_TICKS) ?
+						LED_WHITE :
+						LED_OFF);
 			else
 				led_set_color_battery(RIGHT_PORT, LED_OFF);
 		}
@@ -188,19 +185,20 @@ static void led_set_battery(void)
 			led_set_color_battery(LEFT_PORT, LED_OFF);
 		break;
 	case PWR_STATE_ERROR:
-		set_active_port_color((battery_ticks & 0x2) ?
-				LED_WHITE : LED_OFF);
+		set_active_port_color((battery_ticks & 0x2) ? LED_WHITE :
+							      LED_OFF);
 		break;
 	case PWR_STATE_CHARGE_NEAR_FULL:
 		set_active_port_color(LED_WHITE);
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			set_active_port_color((battery_ticks %
-				LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-				LED_AMBER : LED_OFF);
-		else
-			set_active_port_color(LED_WHITE);
+		set_active_port_color(LED_WHITE);
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		set_active_port_color(
+			(battery_ticks % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
+				LED_AMBER :
+				LED_OFF);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
@@ -217,9 +215,10 @@ static void led_set_power(void)
 	if (chipset_in_state(CHIPSET_STATE_ON))
 		led_set_color_power(LED_WHITE);
 	else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-		led_set_color_power((power_tick %
-			LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-			LED_WHITE : LED_OFF);
+		led_set_color_power(
+			(power_tick % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
+				LED_WHITE :
+				LED_OFF);
 	else
 		led_set_color_power(LED_OFF);
 }
diff --git a/board/guybrush/battery.c b/board/guybrush/battery.c
index ddf3adff50..e7163c8a11 100644
--- a/board/guybrush/battery.c
+++ b/board/guybrush/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/guybrush/board.c b/board/guybrush/board.c
index 6ba8de04c9..663094233e 100644
--- a/board/guybrush/board.c
+++ b/board/guybrush/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,6 +8,7 @@
 #include "adc.h"
 #include "base_fw_config.h"
 #include "board_fw_config.h"
+#include "builtin/assert.h"
 #include "button.h"
 #include "common.h"
 #include "cros_board_info.h"
@@ -16,7 +17,7 @@
 #include "driver/accelgyro_bmi323.h"
 #include "driver/accel_bma422.h"
 #include "driver/retimer/ps8811.h"
-#include "driver/retimer/ps8818.h"
+#include "driver/retimer/ps8818_public.h"
 #include "driver/temp_sensor/sb_tsi.h"
 #include "driver/temp_sensor/tmp112.h"
 #include "extpower.h"
@@ -45,17 +46,13 @@ static struct bmi_drv_data_t g_bmi_data;
 static struct accelgyro_saved_data_t g_bma422_data;
 
 /* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(1),  0},
-	{ 0, 0,  FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				       { 0, FLOAT_TO_FP(1), 0 },
+				       { 0, 0, FLOAT_TO_FP(-1) } };
 
-const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0,  FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+				      { FLOAT_TO_FP(-1), 0, 0 },
+				      { 0, 0, FLOAT_TO_FP(-1) } };
 
 /*
  * We have total 30 pins for keyboard connecter {-1, -1} mean
@@ -63,16 +60,15 @@ const mat33_fp_t lid_standard_ref = {
  * that we don't have pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-	{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-	{0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3},
-	{-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0},
-	{1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4},
-	{2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0},
-	{-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1},
-	{-1, -1},
+	{ -1, -1 }, { 0, 5 },	{ 1, 1 }, { 1, 0 },   { 0, 6 },	  { 0, 7 },
+	{ -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 },   { -1, -1 }, { 1, 6 },
+	{ 1, 7 },   { 3, 1 },	{ 2, 0 }, { 1, 5 },   { 2, 6 },	  { 2, 7 },
+	{ 2, 1 },   { 2, 4 },	{ 2, 5 }, { 1, 2 },   { 2, 3 },	  { 2, 2 },
+	{ 3, 0 },   { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 },	  { -1, -1 },
+	{ -1, -1 },
 };
 const int keyboard_factory_scan_pins_used =
-		ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
@@ -222,51 +218,46 @@ board_a1_ps8811_retimer_init(const struct usb_mux *me)
 }
 
 __override int board_c1_ps8818_mux_set(const struct usb_mux *me,
-				    mux_state_t mux_state)
+				       mux_state_t mux_state)
 {
 	int rv = EC_SUCCESS;
 
 	/* USB specific config */
 	if (mux_state & USB_PD_MUX_USB_ENABLED) {
 		/* Boost the USB gain */
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX1EQ_10G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_19DB);
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_APTX1EQ_10G_LEVEL,
+					      PS8818_EQ_LEVEL_UP_MASK,
+					      PS8818_EQ_LEVEL_UP_19DB);
 		if (rv)
 			return rv;
 
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX2EQ_10G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_19DB);
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_APTX2EQ_10G_LEVEL,
+					      PS8818_EQ_LEVEL_UP_MASK,
+					      PS8818_EQ_LEVEL_UP_19DB);
 		if (rv)
 			return rv;
 
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX1EQ_5G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_19DB);
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_APTX1EQ_5G_LEVEL,
+					      PS8818_EQ_LEVEL_UP_MASK,
+					      PS8818_EQ_LEVEL_UP_19DB);
 		if (rv)
 			return rv;
 
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX2EQ_5G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_19DB);
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_APTX2EQ_5G_LEVEL,
+					      PS8818_EQ_LEVEL_UP_MASK,
+					      PS8818_EQ_LEVEL_UP_19DB);
 		if (rv)
 			return rv;
 
 		/* Set the RX input termination */
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_RX_PHY,
-					PS8818_RX_INPUT_TERM_MASK,
-					PS8818_RX_INPUT_TERM_112_OHM);
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_RX_PHY,
+					      PS8818_RX_INPUT_TERM_MASK,
+					      PS8818_RX_INPUT_TERM_112_OHM);
 		if (rv)
 			return rv;
 	}
@@ -274,11 +265,10 @@ __override int board_c1_ps8818_mux_set(const struct usb_mux *me,
 	/* DP specific config */
 	if (mux_state & USB_PD_MUX_DP_ENABLED) {
 		/* Boost the DP gain */
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_DPEQ_LEVEL,
-					PS8818_DPEQ_LEVEL_UP_MASK,
-					PS8818_DPEQ_LEVEL_UP_19DB);
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_DPEQ_LEVEL,
+					      PS8818_DPEQ_LEVEL_UP_MASK,
+					      PS8818_DPEQ_LEVEL_UP_19DB);
 		if (rv)
 			return rv;
 
@@ -356,8 +346,7 @@ static void board_chipset_startup(void)
 	if (get_board_version() > 1)
 		tmp112_init();
 }
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup,
-	     HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
 
 int board_get_soc_temp_k(int idx, int *temp_k)
 {
@@ -490,8 +479,7 @@ struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT] = {
 		.temp_host_release = {
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
 		},
-		/* TODO: Setting fan off to 0 so it's allways on */
-		.temp_fan_off = C_TO_K(0),
+		.temp_fan_off = C_TO_K(25),
 		.temp_fan_max = C_TO_K(70),
 	},
 	[TEMP_SENSOR_CHARGER] = {
diff --git a/board/guybrush/board.h b/board/guybrush/board.h
index a749802cfa..094b98f23e 100644
--- a/board/guybrush/board.h
+++ b/board/guybrush/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,7 +25,7 @@
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 #define CONFIG_ACCEL_BMA4XX
 
-#define I2C_PORT_ACCEL      I2C_PORT_SENSOR
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
 
 /* EC console commands */
 #define CONFIG_CMD_ACCELS
@@ -36,11 +36,11 @@
 #define CONFIG_USB_MUX_ANX7451
 #define CONFIG_USBC_RETIMER_ANX7451
 
-#define PD_OPERATING_POWER_MW   15000
-#define PD_MAX_CURRENT_MA       5000
-#define PD_MAX_VOLTAGE_MV       20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_CURRENT_MA 5000
+#define PD_MAX_VOLTAGE_MV 20000
 /* Max Power = 100 W */
-#define PD_MAX_POWER_MW         ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
+#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
 
 /* USB Type A Features */
 
diff --git a/board/guybrush/board_fw_config.c b/board/guybrush/board_fw_config.c
index c919d82851..0484b82461 100644
--- a/board/guybrush/board_fw_config.c
+++ b/board/guybrush/board_fw_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,14 +9,15 @@
 bool board_is_convertible(void)
 {
 	return (get_fw_config_field(FW_CONFIG_FORM_FACTOR_OFFSET,
-			FW_CONFIG_FORM_FACTOR_WIDTH)
-			== FW_CONFIG_FORM_FACTOR_CONVERTIBLE);
+				    FW_CONFIG_FORM_FACTOR_WIDTH) ==
+		FW_CONFIG_FORM_FACTOR_CONVERTIBLE);
 }
 
 bool board_has_kblight(void)
 {
 	return (get_fw_config_field(FW_CONFIG_KBLIGHT_OFFSET,
-			FW_CONFIG_KBLIGHT_WIDTH) == FW_CONFIG_KBLIGHT_YES);
+				    FW_CONFIG_KBLIGHT_WIDTH) ==
+		FW_CONFIG_KBLIGHT_YES);
 }
 
 enum board_usb_c1_mux board_get_usb_c1_mux(void)
diff --git a/board/guybrush/board_fw_config.h b/board/guybrush/board_fw_config.h
index 1de417d77a..4477aca6fd 100644
--- a/board/guybrush/board_fw_config.h
+++ b/board/guybrush/board_fw_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,26 +13,25 @@
 /*
  * USB Daughter Board (2 bits)
  */
-#define FW_CONFIG_USB_DB_OFFSET			0
-#define FW_CONFIG_USB_DB_WIDTH			2
-#define FW_CONFIG_USB_DB_A1_PS8811_C1_PS8818	0
-#define FW_CONFIG_USB_DB_A1_ANX7491_C1_ANX7451	1
+#define FW_CONFIG_USB_DB_OFFSET 0
+#define FW_CONFIG_USB_DB_WIDTH 2
+#define FW_CONFIG_USB_DB_A1_PS8811_C1_PS8818 0
+#define FW_CONFIG_USB_DB_A1_ANX7491_C1_ANX7451 1
 
 /*
  * Form Factor (1 bits)
  */
-#define FW_CONFIG_FORM_FACTOR_OFFSET		2
-#define FW_CONFIG_FORM_FACTOR_WIDTH		1
-#define FW_CONFIG_FORM_FACTOR_CLAMSHELL		0
-#define FW_CONFIG_FORM_FACTOR_CONVERTIBLE	1
+#define FW_CONFIG_FORM_FACTOR_OFFSET 2
+#define FW_CONFIG_FORM_FACTOR_WIDTH 1
+#define FW_CONFIG_FORM_FACTOR_CLAMSHELL 0
+#define FW_CONFIG_FORM_FACTOR_CONVERTIBLE 1
 
 /*
  * Keyboard Backlight (1 bit)
  */
-#define FW_CONFIG_KBLIGHT_OFFSET		3
-#define FW_CONFIG_KBLIGHT_WIDTH			1
-#define FW_CONFIG_KBLIGHT_NO			0
-#define FW_CONFIG_KBLIGHT_YES			1
-
+#define FW_CONFIG_KBLIGHT_OFFSET 3
+#define FW_CONFIG_KBLIGHT_WIDTH 1
+#define FW_CONFIG_KBLIGHT_NO 0
+#define FW_CONFIG_KBLIGHT_YES 1
 
 #endif /* _GUYBRUSH_CBI_FW_CONFIG__H_ */
diff --git a/board/guybrush/build.mk b/board/guybrush/build.mk
index a7865db889..806e8988a2 100644
--- a/board/guybrush/build.mk
+++ b/board/guybrush/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/guybrush/ec.tasklist b/board/guybrush/ec.tasklist
index f7cf0f7205..7a64850dfb 100644
--- a/board/guybrush/ec.tasklist
+++ b/board/guybrush/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/guybrush/gpio.inc b/board/guybrush/gpio.inc
index b7381f588d..ffc567b261 100644
--- a/board/guybrush/gpio.inc
+++ b/board/guybrush/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/guybrush/led.c b/board/guybrush/led.c
index b17c8be488..26b1fc826a 100644
--- a/board/guybrush/led.c
+++ b/board/guybrush/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -12,29 +12,37 @@
 #include "pwm.h"
 
 /* Note PWM LEDs are active low */
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
-#define CPRINTS(format, args...) cprints(CC_PWM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_PWM, format, ##args)
 
 __override const int led_charge_lvl_1 = 5;
 
 __override const int led_charge_lvl_2 = 97;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC},
-					{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_WHITE,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC } },
+	};
 
 const enum ec_led_id supported_led_ids[] = {
 	EC_LED_ID_BATTERY_LED,
diff --git a/board/guybrush/thermal.c b/board/guybrush/thermal.c
index 606d21cfdf..5bb1295f84 100644
--- a/board/guybrush/thermal.c
+++ b/board/guybrush/thermal.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,7 +12,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_THERMAL, outstr)
-#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
 
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
diff --git a/board/haboki/battery.c b/board/haboki/battery.c
index 551ff1cbc0..72ad9ad6cb 100644
--- a/board/haboki/battery.c
+++ b/board/haboki/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/haboki/board.c b/board/haboki/board.c
index 3a33787603..d7509115b5 100644
--- a/board/haboki/board.c
+++ b/board/haboki/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -41,7 +41,7 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
 
 #define INT_RECHECK_US 5000
 
@@ -164,48 +164,36 @@ static void pen_detect_interrupt(enum gpio_signal s)
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH0
-	},
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH2
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH3
-	},
-	[ADC_SUB_ANALOG] = {
-		.name = "SUB_ANALOG",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH13
-	},
-	[ADC_TEMP_SENSOR_3] = {
-		.name = "TEMP_SENSOR3",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH15
-	},
-	[ADC_TEMP_SENSOR_4] = {
-		.name = "TEMP_SENSOR4",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH16
-	},
+	[ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH0 },
+	[ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH2 },
+	[ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH3 },
+	[ADC_SUB_ANALOG] = { .name = "SUB_ANALOG",
+			     .factor_mul = ADC_MAX_MVOLT,
+			     .factor_div = ADC_READ_MAX + 1,
+			     .shift = 0,
+			     .channel = CHIP_ADC_CH13 },
+	[ADC_TEMP_SENSOR_3] = { .name = "TEMP_SENSOR3",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH15 },
+	[ADC_TEMP_SENSOR_4] = { .name = "TEMP_SENSOR4",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH16 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
@@ -254,19 +242,25 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 };
 
 /* USB Muxes */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+			},
 	},
 	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_SUB_USB_C1,
+				.i2c_addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	},
 };
 
@@ -279,17 +273,13 @@ static struct accelgyro_saved_data_t g_bma253_data;
 static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
 
 /* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, FLOAT_TO_FP(-1), 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
 
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
 /* Drivers */
 struct motion_sensor_t motion_sensors[] = {
@@ -480,8 +470,8 @@ __override void board_power_5v_enable(int enable)
 
 	if (board_get_charger_chip_count() > 1) {
 		if (sm5803_set_gpio0_level(1, !!enable))
-			CPRINTUSB("Failed to %sable sub rails!", enable ?
-								  "en" : "dis");
+			CPRINTUSB("Failed to %sable sub rails!",
+				  enable ? "en" : "dis");
 	}
 }
 
@@ -489,11 +479,11 @@ __override uint8_t board_get_usb_pd_port_count(void)
 {
 	enum fw_config_db db = get_cbi_fw_config_db();
 
-	if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI
-			|| db == DB_1A_HDMI_LTE)
+	if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI ||
+	    db == DB_1A_HDMI_LTE)
 		return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
-	else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A
-			|| db == DB_1C_1A_LTE)
+	else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A ||
+		 db == DB_1C_1A_LTE)
 		return CONFIG_USB_PD_PORT_MAX_COUNT;
 
 	ccprints("Unhandled DB configuration: %d", db);
@@ -504,11 +494,11 @@ __override uint8_t board_get_charger_chip_count(void)
 {
 	enum fw_config_db db = get_cbi_fw_config_db();
 
-	if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI
-			|| db == DB_1A_HDMI_LTE)
+	if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI ||
+	    db == DB_1A_HDMI_LTE)
 		return CHARGER_NUM - 1;
-	else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A
-			|| db == DB_1C_1A_LTE)
+	else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A ||
+		 db == DB_1C_1A_LTE)
 		return CHARGER_NUM;
 
 	ccprints("Unhandled DB configuration: %d", db);
@@ -613,33 +603,31 @@ __override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
 }
 
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq_hz = 10000,
-	}
-};
+const struct pwm_t pwm_channels[] = { [PWM_CH_KBLIGHT] = {
+					      .channel = 0,
+					      .flags = PWM_CONFIG_DSLEEP,
+					      .freq_hz = 10000,
+				      } };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
 /* Thermistors */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "Charger",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_3},
-	[TEMP_SENSOR_4] = {.name = "5V regular",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_4},
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "Charger",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
+	[TEMP_SENSOR_4] = { .name = "5V regular",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_4 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -669,9 +657,8 @@ __override void lid_angle_peripheral_enable(int enable)
 	}
 }
 
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
+__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+				       int *ki_div, int *kd, int *kd_div)
 {
 	*kp = 3;
 	*kp_div = 20;
@@ -690,14 +677,17 @@ __override void ocpc_get_pid_constants(int *kp, int *kp_div,
  * The connector has 24 pins total, and there is no pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-	{-1, -1}, {GPIO_KSO_H, 4}, {GPIO_KSO_H, 0}, {GPIO_KSO_H, 1},
-	{GPIO_KSO_H, 3}, {GPIO_KSO_H, 2}, {GPIO_KSO_L, 5}, {GPIO_KSO_L, 6},
-	{GPIO_KSO_L, 3}, {GPIO_KSO_L, 2}, {GPIO_KSI, 0}, {GPIO_KSO_L, 1},
-	{GPIO_KSO_L, 4}, {GPIO_KSI, 3}, {GPIO_KSI, 2}, {GPIO_KSO_L, 0},
-	{GPIO_KSI, 5}, {GPIO_KSI, 4}, {GPIO_KSO_L, 7}, {GPIO_KSI, 6},
-	{GPIO_KSI, 7}, {GPIO_KSI, 1}, {-1, -1}, {-1, -1}, {-1, -1},
+	{ -1, -1 },	   { GPIO_KSO_H, 4 }, { GPIO_KSO_H, 0 },
+	{ GPIO_KSO_H, 1 }, { GPIO_KSO_H, 3 }, { GPIO_KSO_H, 2 },
+	{ GPIO_KSO_L, 5 }, { GPIO_KSO_L, 6 }, { GPIO_KSO_L, 3 },
+	{ GPIO_KSO_L, 2 }, { GPIO_KSI, 0 },   { GPIO_KSO_L, 1 },
+	{ GPIO_KSO_L, 4 }, { GPIO_KSI, 3 },   { GPIO_KSI, 2 },
+	{ GPIO_KSO_L, 0 }, { GPIO_KSI, 5 },   { GPIO_KSI, 4 },
+	{ GPIO_KSO_L, 7 }, { GPIO_KSI, 6 },   { GPIO_KSI, 7 },
+	{ GPIO_KSI, 1 },   { -1, -1 },	      { -1, -1 },
+	{ -1, -1 },
 };
 
 const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 #endif
diff --git a/board/haboki/board.h b/board/haboki/board.h
index 58dafb945f..0365d094ea 100644
--- a/board/haboki/board.h
+++ b/board/haboki/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,20 +23,23 @@
 
 /* Charger */
 #define CONFIG_CHARGE_RAMP_HW
-#define CONFIG_CHARGER_SM5803		/* C0 and C1: Charger */
+#define CONFIG_CHARGER_SM5803 /* C0 and C1: Charger */
+#define PD_MAX_VOLTAGE_MV 15000
 #define CONFIG_USB_PD_VBUS_DETECT_CHARGER
 #define CONFIG_USB_PD_5V_CHARGER_CTRL
 #define CONFIG_CHARGER_OTG
-#undef  CONFIG_CHARGER_SINGLE_CHIP
+#undef CONFIG_CHARGER_SINGLE_CHIP
 #define CONFIG_OCPC
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr */
+#define CONFIG_OCPC_DEF_RBATT_MOHMS               \
+	21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr \
+	    */
 
 /* PWM */
 #define CONFIG_PWM
 
 /* Sensors */
-#define CONFIG_ACCEL_BMA255		/* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM	/* Base accel */
+#define CONFIG_ACCEL_BMA255 /* Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
 /* Sensors without hardware FIFO are in forced mode */
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
 
@@ -69,8 +72,8 @@
 
 /* TCPC */
 #define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP	/* C0: ITE EC TCPC */
-#define CONFIG_USB_PD_TCPM_PS8705	/* C1: PS8705 TCPC*/
+#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0: ITE EC TCPC */
+#define CONFIG_USB_PD_TCPM_PS8705 /* C1: PS8705 TCPC*/
 #define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1
 #define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
 #define CONFIG_USB_PD_TCPC_LOW_POWER
@@ -81,8 +84,8 @@
 #define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
 
 /* USB Mux and Retimer */
-#define CONFIG_USB_MUX_IT5205			/* C1: ITE Mux */
-#define I2C_PORT_USB_MUX I2C_PORT_USB_C0	/* Required for ITE Mux */
+#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */
 
 /* USB Type A Features */
 #define USB_PORT_COUNT 1
@@ -105,21 +108,16 @@ enum pwm_channel {
 };
 
 /* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
 /* ADC channels */
 enum adc_channel {
-	ADC_VSNS_PP3300_A,     /* ADC0 */
-	ADC_TEMP_SENSOR_1,     /* ADC2 */
-	ADC_TEMP_SENSOR_2,     /* ADC3 */
-	ADC_SUB_ANALOG,        /* ADC13 */
-	ADC_TEMP_SENSOR_3,     /* ADC15 */
-	ADC_TEMP_SENSOR_4,     /* ADC16 */
+	ADC_VSNS_PP3300_A, /* ADC0 */
+	ADC_TEMP_SENSOR_1, /* ADC2 */
+	ADC_TEMP_SENSOR_2, /* ADC3 */
+	ADC_SUB_ANALOG, /* ADC13 */
+	ADC_TEMP_SENSOR_3, /* ADC15 */
+	ADC_TEMP_SENSOR_4, /* ADC16 */
 	ADC_CH_COUNT
 };
 
diff --git a/board/haboki/build.mk b/board/haboki/build.mk
index aa0e3b766e..4362df50a4 100644
--- a/board/haboki/build.mk
+++ b/board/haboki/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/haboki/cbi_ssfc.c b/board/haboki/cbi_ssfc.c
index c4b859f133..81f3ee0dad 100644
--- a/board/haboki/cbi_ssfc.c
+++ b/board/haboki/cbi_ssfc.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
 
 enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
 {
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
 }
 
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
 {
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
 }
diff --git a/board/haboki/cbi_ssfc.h b/board/haboki/cbi_ssfc.h
index 935049b6ae..bf8853a43a 100644
--- a/board/haboki/cbi_ssfc.h
+++ b/board/haboki/cbi_ssfc.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -56,5 +56,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
  */
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
 
-
 #endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/haboki/ec.tasklist b/board/haboki/ec.tasklist
index 5c9a2d1a01..c13df44543 100644
--- a/board/haboki/ec.tasklist
+++ b/board/haboki/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/haboki/gpio.inc b/board/haboki/gpio.inc
index c1a03bfd56..8ecc458a19 100644
--- a/board/haboki/gpio.inc
+++ b/board/haboki/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/haboki/led.c b/board/haboki/led.c
index 3e3a61edc2..b31d4fab75 100644
--- a/board/haboki/led.c
+++ b/board/haboki/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,10 +18,8 @@
 #define POWER_LED_ON 0
 #define POWER_LED_OFF 1
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -29,7 +27,7 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static int led_set_color_battery(enum led_color color)
@@ -116,7 +114,6 @@ static void led_set_battery(void)
 {
 	static int battery_ticks;
 	static int power_ticks;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
@@ -127,9 +124,9 @@ static void led_set_battery(void)
 	 */
 	if (get_cbi_fw_config_tablet_mode() == TABLET_MODE_ABSENT) {
 		if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
-			charge_get_state() != PWR_STATE_CHARGE) {
-			led_set_color_battery(power_ticks++ & 0x2 ?
-						  LED_WHITE : LED_OFF);
+		    charge_get_state() != PWR_STATE_CHARGE) {
+			led_set_color_battery(power_ticks++ & 0x2 ? LED_WHITE :
+								    LED_OFF);
 			return;
 		}
 	}
@@ -158,18 +155,18 @@ static void led_set_battery(void)
 			led_set_color_battery(LED_OFF);
 		break;
 	case PWR_STATE_ERROR:
-		led_set_color_battery(
-			(battery_ticks % 0x2) ? LED_WHITE : LED_OFF);
+		led_set_color_battery((battery_ticks % 0x2) ? LED_WHITE :
+							      LED_OFF);
 		break;
 	case PWR_STATE_CHARGE_NEAR_FULL:
 		led_set_color_battery(LED_WHITE);
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			led_set_color_battery(
-				(battery_ticks & 0x2) ? LED_AMBER : LED_OFF);
-		else
-			led_set_color_battery(LED_WHITE);
+		led_set_color_battery(LED_WHITE);
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		led_set_color_battery((battery_ticks & 0x2) ? LED_AMBER :
+							      LED_OFF);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
@@ -186,8 +183,7 @@ static void led_set_power(void)
 	if (chipset_in_state(CHIPSET_STATE_ON))
 		led_set_color_power(LED_WHITE);
 	else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-		led_set_color_power(
-			(power_tick & 0x2) ? LED_WHITE : LED_OFF);
+		led_set_color_power((power_tick & 0x2) ? LED_WHITE : LED_OFF);
 	else
 		led_set_color_power(LED_OFF);
 }
diff --git a/board/haboki/usb_pd_policy.c b/board/haboki/usb_pd_policy.c
index 3ff7152541..8a2c07c575 100644
--- a/board/haboki/usb_pd_policy.c
+++ b/board/haboki/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,8 +13,8 @@
 #include "driver/tcpm/tcpci.h"
 #include "usb_pd.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
@@ -65,18 +65,7 @@ int pd_set_power_supply_ready(int port)
 
 __override bool pd_check_vbus_level(int port, enum vbus_level level)
 {
-	int vbus_voltage;
-
-	/* If we're unable to speak to the charger, best to guess false */
-	if (charger_get_vbus_voltage(port, &vbus_voltage))
-		return false;
-
-	if (level == VBUS_SAFE0V)
-		return vbus_voltage < PD_V_SAFE0V_MAX;
-	else if (level == VBUS_PRESENT)
-		return vbus_voltage > PD_V_SAFE5V_MIN;
-	else
-		return vbus_voltage < PD_V_SINK_DISCONNECT_MAX;
+	return sm5803_check_vbus_level(port, level);
 }
 
 int pd_snk_is_vbus_provided(int port)
diff --git a/board/hammer/battery.c b/board/hammer/battery.c
index 4025a08b14..df6a716cd7 100644
--- a/board/hammer/battery.c
+++ b/board/hammer/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,8 +13,8 @@
 #include "util.h"
 
 /* Shutdown mode parameter to write to manufacturer access register */
-#define SB_SHIP_MODE_REG	SB_MANUFACTURER_ACCESS
-#define SB_SHUTDOWN_DATA        0x0010
+#define SB_SHIP_MODE_REG SB_MANUFACTURER_ACCESS
+#define SB_SHUTDOWN_DATA 0x0010
 
 static const struct battery_info info = {
 	.voltage_max = 8800,
diff --git a/board/hammer/board.c b/board/hammer/board.c
index 3e3491d3e1..4700130b4b 100644
--- a/board/hammer/board.c
+++ b/board/hammer/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -48,21 +48,21 @@
 #define CROS_EC_SECTION "RO"
 #endif
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 /******************************************************************************
  * Define the strings used in our USB descriptors.
  */
 const void *const usb_strings[] = {
-	[USB_STR_DESC]         = usb_string_desc,
-	[USB_STR_VENDOR]       = USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]      = USB_STRING_DESC("Hammer"),
-	[USB_STR_SERIALNO]     = 0,
-	[USB_STR_VERSION]      =
-			USB_STRING_DESC(CROS_EC_SECTION ":" CROS_EC_VERSION32),
-	[USB_STR_SPI_NAME]     = USB_STRING_DESC("SPI"),
-	[USB_STR_I2C_NAME]     = USB_STRING_DESC("I2C"),
-	[USB_STR_UPDATE_NAME]  = USB_STRING_DESC("Firmware update"),
+	[USB_STR_DESC] = usb_string_desc,
+	[USB_STR_VENDOR] = USB_STRING_DESC("Google LLC"),
+	[USB_STR_PRODUCT] = USB_STRING_DESC("Hammer"),
+	[USB_STR_SERIALNO] = 0,
+	[USB_STR_VERSION] =
+		USB_STRING_DESC(CROS_EC_SECTION ":" CROS_EC_VERSION32),
+	[USB_STR_SPI_NAME] = USB_STRING_DESC("SPI"),
+	[USB_STR_I2C_NAME] = USB_STRING_DESC("I2C"),
+	[USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"),
 #ifdef CONFIG_USB_ISOCHRONOUS
 	[USB_STR_HEATMAP_NAME] = USB_STRING_DESC("Heatmap"),
 #endif
@@ -84,28 +84,28 @@ const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
 USB_SPI_CONFIG(usb_spi, USB_IFACE_I2C_SPI, USB_EP_I2C_SPI, 0);
 /* SPI interface is always enabled, no need to do anything. */
-void usb_spi_board_enable(struct usb_spi_config const *config) {}
-void usb_spi_board_disable(struct usb_spi_config const *config) {}
-#endif  /* !HAS_SPI_TOUCHPAD */
+void usb_spi_board_enable(struct usb_spi_config const *config)
+{
+}
+void usb_spi_board_disable(struct usb_spi_config const *config)
+{
+}
+#endif /* !HAS_SPI_TOUCHPAD */
 
 #ifdef CONFIG_I2C
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "master",
-		.port = I2C_PORT_MASTER,
-		.kbps = 400,
-		.scl  = GPIO_MASTER_I2C_SCL,
-		.sda  = GPIO_MASTER_I2C_SDA
-	},
+	{ .name = "master",
+	  .port = I2C_PORT_MASTER,
+	  .kbps = 400,
+	  .scl = GPIO_MASTER_I2C_SCL,
+	  .sda = GPIO_MASTER_I2C_SDA },
 #ifdef BOARD_WAND
-	{
-		.name = "charger",
-		.port = I2C_PORT_CHARGER,
-		.kbps = 100,
-		.scl  = GPIO_CHARGER_I2C_SCL,
-		.sda  = GPIO_CHARGER_I2C_SDA
-	},
+	{ .name = "charger",
+	  .port = I2C_PORT_CHARGER,
+	  .kbps = 100,
+	  .scl = GPIO_CHARGER_I2C_SCL,
+	  .sda = GPIO_CHARGER_I2C_SDA },
 #endif
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
@@ -125,7 +125,7 @@ const struct charger_config_t chg_chips[] = {
 #ifdef HAS_BACKLIGHT
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	{STM32_TIM(TIM_KBLIGHT), STM32_TIM_CH(1), 0, KBLIGHT_PWM_FREQ},
+	{ STM32_TIM(TIM_KBLIGHT), STM32_TIM_CH(1), 0, KBLIGHT_PWM_FREQ },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 #endif /* HAS_BACKLIGHT */
@@ -154,26 +154,22 @@ __override struct keyboard_scan_config keyscan_config = {
 struct consumer const ec_ec_usart_consumer;
 static struct usart_config const ec_ec_usart;
 
-struct queue const ec_ec_comm_server_input = QUEUE_DIRECT(64, uint8_t,
-				ec_ec_usart.producer, ec_ec_usart_consumer);
-struct queue const ec_ec_comm_server_output = QUEUE_DIRECT(64, uint8_t,
-				null_producer, ec_ec_usart.consumer);
+struct queue const ec_ec_comm_server_input =
+	QUEUE_DIRECT(64, uint8_t, ec_ec_usart.producer, ec_ec_usart_consumer);
+struct queue const ec_ec_comm_server_output =
+	QUEUE_DIRECT(64, uint8_t, null_producer, ec_ec_usart.consumer);
 
 struct consumer const ec_ec_usart_consumer = {
 	.queue = &ec_ec_comm_server_input,
-	.ops   = &((struct consumer_ops const) {
+	.ops = &((struct consumer_ops const){
 		.written = ec_ec_comm_server_written,
 	}),
 };
 
 static struct usart_config const ec_ec_usart =
-	USART_CONFIG(EC_EC_UART,
-		usart_rx_interrupt,
-		usart_tx_interrupt,
-		115200,
-		USART_CONFIG_FLAG_HDSEL,
-		ec_ec_comm_server_input,
-		ec_ec_comm_server_output);
+	USART_CONFIG(EC_EC_UART, usart_rx_interrupt, usart_tx_interrupt, 115200,
+		     USART_CONFIG_FLAG_HDSEL, ec_ec_comm_server_input,
+		     ec_ec_comm_server_output);
 #endif /* BOARD_WAND && SECTION_IS_RW */
 
 /******************************************************************************
@@ -280,9 +276,9 @@ static void board_tablet_mode_change(void)
 		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
 }
 DECLARE_HOOK(HOOK_TABLET_MODE_CHANGE, board_tablet_mode_change,
-		HOOK_PRIO_DEFAULT);
+	     HOOK_PRIO_DEFAULT);
 /* Run after tablet_mode_init. */
-DECLARE_HOOK(HOOK_INIT, board_tablet_mode_change, HOOK_PRIO_DEFAULT+1);
+DECLARE_HOOK(HOOK_INIT, board_tablet_mode_change, HOOK_PRIO_DEFAULT + 1);
 #endif
 
 /*
@@ -295,7 +291,7 @@ int board_get_entropy(void *buffer, int len)
 	uint8_t *data = buffer;
 	uint32_t start;
 	/* We expect one SOF per ms, so wait at most 2ms. */
-	const uint32_t timeout = 2*MSEC;
+	const uint32_t timeout = 2 * MSEC;
 
 	for (i = 0; i < len; i++) {
 		STM32_CRS_ICR |= STM32_CRS_ICR_SYNCOKC;
@@ -326,8 +322,9 @@ __override const char *board_read_serial(void)
 		int i;
 
 		for (i = 0; i < idlen && pos < sizeof(str); i++, pos += 2) {
-			snprintf(&str[pos], sizeof(str)-pos,
-				"%02x", id[i]);
+			if (snprintf(&str[pos], sizeof(str) - pos, "%02x",
+				     id[i]) < 0)
+				return NULL;
 		}
 	}
 
@@ -390,8 +387,8 @@ static const struct ec_response_keybd_config duck_kb = {
 	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
 };
 
-__override
-const struct ec_response_keybd_config *board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	if (IS_ENABLED(BOARD_ZED) || IS_ENABLED(BOARD_STAR) ||
 	    IS_ENABLED(BOARD_GELATIN))
diff --git a/board/hammer/board.h b/board/hammer/board.h
index 768d15bc5b..bce7dc39f4 100644
--- a/board/hammer/board.h
+++ b/board/hammer/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -46,27 +46,27 @@
 /* Do not use a dedicated PSTATE bank */
 #undef CONFIG_FLASH_PSTATE_BANK
 
-#define CONFIG_SHAREDLIB_SIZE	0
+#define CONFIG_SHAREDLIB_SIZE 0
 
-#define CONFIG_RO_MEM_OFF	0
-#define CONFIG_RO_STORAGE_OFF	0
-#define CONFIG_RO_SIZE		(44*1024)
+#define CONFIG_RO_MEM_OFF 0
+#define CONFIG_RO_STORAGE_OFF 0
+#define CONFIG_RO_SIZE (44 * 1024)
 
 /* EC rollback protection block */
 #define CONFIG_ROLLBACK_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
 #define CONFIG_ROLLBACK_SIZE CONFIG_FLASH_BANK_SIZE
 
-#define CONFIG_RW_MEM_OFF	(CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE)
-#define CONFIG_RW_STORAGE_OFF	0
-#define CONFIG_RW_SIZE		(CONFIG_FLASH_SIZE_BYTES - CONFIG_RW_MEM_OFF)
+#define CONFIG_RW_MEM_OFF (CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE)
+#define CONFIG_RW_STORAGE_OFF 0
+#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE_BYTES - CONFIG_RW_MEM_OFF)
 
-#define CONFIG_EC_PROTECTED_STORAGE_OFF		CONFIG_RO_MEM_OFF
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE	CONFIG_RO_SIZE
-#define CONFIG_EC_WRITABLE_STORAGE_OFF		CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE		CONFIG_RW_SIZE
+#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF
+#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE
+#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE
 
-#define CONFIG_WP_STORAGE_OFF		CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE		CONFIG_EC_PROTECTED_STORAGE_SIZE
+#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
+#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
 
 /* The UART console is on USART1 (PA9/PA10) */
 #undef CONFIG_UART_CONSOLE
@@ -110,48 +110,48 @@
 
 /* USB interface indexes (use define rather than enum to expand them) */
 #ifdef SECTION_IS_RW
-#define USB_IFACE_HID_KEYBOARD	0
-#define USB_IFACE_UPDATE	1
+#define USB_IFACE_HID_KEYBOARD 0
+#define USB_IFACE_UPDATE 1
 #ifdef HAS_NO_TOUCHPAD
-#define USB_IFACE_COUNT		2
+#define USB_IFACE_COUNT 2
 #else /* !HAS_NO_TOUCHPAD */
-#define USB_IFACE_HID_TOUCHPAD	2
+#define USB_IFACE_HID_TOUCHPAD 2
 /* Can be either I2C or SPI passthrough, depending on the board. */
-#define USB_IFACE_I2C_SPI	3
+#define USB_IFACE_I2C_SPI 3
 #if defined(CONFIG_USB_ISOCHRONOUS)
-#define USB_IFACE_ST_TOUCHPAD	4
-#define USB_IFACE_COUNT		5
-#else  /* !CONFIG_USB_ISOCHRONOUS */
-#define USB_IFACE_COUNT		4
-#endif  /* CONFIG_USB_ISOCHRONOUS */
+#define USB_IFACE_ST_TOUCHPAD 4
+#define USB_IFACE_COUNT 5
+#else /* !CONFIG_USB_ISOCHRONOUS */
+#define USB_IFACE_COUNT 4
+#endif /* CONFIG_USB_ISOCHRONOUS */
 #endif /* !HAS_NO_TOUCHPAD */
-#else  /* !SECTION_IS_RW */
-#define USB_IFACE_UPDATE	0
-#define USB_IFACE_COUNT		1
-#endif  /* SECTION_IS_RW */
+#else /* !SECTION_IS_RW */
+#define USB_IFACE_UPDATE 0
+#define USB_IFACE_COUNT 1
+#endif /* SECTION_IS_RW */
 
 /* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL		0
-#define USB_EP_UPDATE		1
+#define USB_EP_CONTROL 0
+#define USB_EP_UPDATE 1
 #ifdef SECTION_IS_RW
-#define USB_EP_HID_KEYBOARD	2
+#define USB_EP_HID_KEYBOARD 2
 #ifdef HAS_NO_TOUCHPAD
-#define USB_EP_COUNT		3
+#define USB_EP_COUNT 3
 #else /* !HAS_NO_TOUCHPAD */
-#define USB_EP_HID_TOUCHPAD	3
+#define USB_EP_HID_TOUCHPAD 3
 /* Can be either I2C or SPI passthrough, depending on the board. */
-#define USB_EP_I2C_SPI		4
+#define USB_EP_I2C_SPI 4
 #if defined(CONFIG_USB_ISOCHRONOUS)
-#define USB_EP_ST_TOUCHPAD	5
-#define USB_EP_ST_TOUCHPAD_INT	6
-#define USB_EP_COUNT		7
+#define USB_EP_ST_TOUCHPAD 5
+#define USB_EP_ST_TOUCHPAD_INT 6
+#define USB_EP_COUNT 7
 #else /* !CONFIG_USB_ISOCHRONOUS */
-#define USB_EP_COUNT		5
+#define USB_EP_COUNT 5
 #endif /* CONFIG_USB_ISOCHRONOUS */
 #endif /* !HAS_NO_TOUCHPAD */
-#else  /* !SECTION_IS_RW */
-#define USB_EP_COUNT		2
-#endif  /* SECTION_IS_RW */
+#else /* !SECTION_IS_RW */
+#define USB_EP_COUNT 2
+#endif /* SECTION_IS_RW */
 
 /* Optional features */
 #define CONFIG_BOARD_PRE_INIT
@@ -177,13 +177,19 @@
 #undef CONFIG_USB_I2C_MAX_WRITE_COUNT
 #ifdef VARIANT_HAMMER_TP_LARGE_PAGE
 /* Zed requires 516 byte per packet for touchpad update */
-#define CONFIG_USB_I2C_MAX_WRITE_COUNT (1024 - 4) /* 4 is maximum header size */
+#define CONFIG_USB_I2C_MAX_WRITE_COUNT         \
+	(1024 - 4) /* 4 is maximum header size \
+		    */
 #else
-#define CONFIG_USB_I2C_MAX_WRITE_COUNT (128 - 4) /* 4 is maximum header size */
+#define CONFIG_USB_I2C_MAX_WRITE_COUNT        \
+	(128 - 4) /* 4 is maximum header size \
+		   */
 #endif
 
 #undef CONFIG_USB_I2C_MAX_READ_COUNT
-#define CONFIG_USB_I2C_MAX_READ_COUNT (1024 - 6) /* 6 is maximum header size */
+#define CONFIG_USB_I2C_MAX_READ_COUNT          \
+	(1024 - 6) /* 6 is maximum header size \
+		    */
 
 #define CONFIG_I2C_XFER_LARGE_TRANSFER
 
@@ -201,7 +207,7 @@
 #define CONFIG_USB_HID_TOUCHPAD
 
 /* Virtual address for touchpad FW in USB updater. */
-#define CONFIG_TOUCHPAD_VIRTUAL_OFF	0x80000000
+#define CONFIG_TOUCHPAD_VIRTUAL_OFF 0x80000000
 
 /* Include touchpad FW hashes in image */
 #define CONFIG_TOUCHPAD_HASH_FW
@@ -315,10 +321,10 @@
 #endif
 
 /* Maximum current to draw. */
-#define MAX_CURRENT_MA			2000
+#define MAX_CURRENT_MA 2000
 /* Maximum current/voltage to provide over OTG. */
-#define MAX_OTG_CURRENT_MA		2000
-#define MAX_OTG_VOLTAGE_MV		20000
+#define MAX_OTG_CURRENT_MA 2000
+#define MAX_OTG_VOLTAGE_MV 20000
 
 #ifndef __ASSEMBLER__
 
diff --git a/board/hammer/build.mk b/board/hammer/build.mk
index b32a6b768a..d41aed0d84 100644
--- a/board/hammer/build.mk
+++ b/board/hammer/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/hammer/ec.tasklist b/board/hammer/ec.tasklist
index b568619065..e528d20cd8 100644
--- a/board/hammer/ec.tasklist
+++ b/board/hammer/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/hammer/gpio.inc b/board/hammer/gpio.inc
index 8372d4fc4b..d79895564d 100644
--- a/board/hammer/gpio.inc
+++ b/board/hammer/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/hammer/variants.h b/board/hammer/variants.h
index 71e70f5758..06dbe3d0f7 100644
--- a/board/hammer/variants.h
+++ b/board/hammer/variants.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -55,7 +55,7 @@
 #define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 511
 #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 1018 /* tenth of mm */
 #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 566 /* tenth of mm */
-#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (48*1024)
+#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (48 * 1024)
 #elif defined(BOARD_BLAND)
 #define CONFIG_USB_HID_KEYBOARD_VIVALDI
 #define CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS 10
@@ -65,7 +65,7 @@
 #define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 511
 #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 839 /* tenth of mm */
 #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 457 /* tenth of mm */
-#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (64*1024)
+#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (64 * 1024)
 #elif defined(BOARD_DON)
 #define HAS_I2C_TOUCHPAD
 #define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X 2925
@@ -73,7 +73,7 @@
 #define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 511
 #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 929 /* tenth of mm */
 #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 457 /* tenth of mm */
-#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (56*1024)
+#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (56 * 1024)
 #elif defined(BOARD_DUCK)
 #define CONFIG_USB_HID_KEYBOARD_VIVALDI
 #define CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS 10
@@ -83,7 +83,7 @@
 #define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 511
 #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 839 /* tenth of mm */
 #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 457 /* tenth of mm */
-#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (64*1024)
+#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (64 * 1024)
 #elif defined(BOARD_EEL)
 #define CONFIG_USB_HID_KEYBOARD_VIVALDI
 #define CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS 10
@@ -93,7 +93,7 @@
 #define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 511
 #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 839 /* tenth of mm */
 #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 457 /* tenth of mm */
-#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (64*1024)
+#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (64 * 1024)
 #elif defined(BOARD_GELATIN)
 #define CONFIG_USB_HID_KEYBOARD_VIVALDI
 #define CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS 10
@@ -104,7 +104,7 @@
 #define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 511
 #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 1060 /* tenth of mm */
 #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 575 /* tenth of mm */
-#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (64*1024)
+#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (64 * 1024)
 #elif defined(BOARD_MAGNEMITE)
 #define HAS_NO_TOUCHPAD
 #elif defined(BOARD_MASTERBALL)
@@ -114,7 +114,7 @@
 #define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 511
 #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 839 /* tenth of mm */
 #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 457 /* tenth of mm */
-#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (64*1024)
+#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (64 * 1024)
 #elif defined(BOARD_MOONBALL)
 #define HAS_I2C_TOUCHPAD
 #define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X 2925
@@ -122,7 +122,7 @@
 #define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 511
 #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 929 /* tenth of mm */
 #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 457 /* tenth of mm */
-#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (56*1024)
+#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (56 * 1024)
 #elif defined(BOARD_STAFF)
 #define HAS_I2C_TOUCHPAD
 #define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X 3206
@@ -130,7 +130,7 @@
 #define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 511
 #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 1018 /* tenth of mm */
 #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 582 /* tenth of mm */
-#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (56*1024)
+#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (56 * 1024)
 #elif defined(BOARD_STAR)
 #define CONFIG_USB_HID_KEYBOARD_VIVALDI
 #define CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS 10
@@ -140,7 +140,7 @@
 #define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 511
 #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 1042 /* tenth of mm */
 #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 569 /* tenth of mm */
-#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (64*1024)
+#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (64 * 1024)
 #elif defined(BOARD_WHISKERS)
 #define HAS_SPI_TOUCHPAD
 #define HAS_EN_PP3300_TP_ACTIVE_HIGH
@@ -149,7 +149,7 @@
 #define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 255
 #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 1031 /* tenth of mm */
 #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 751 /* tenth of mm */
-#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (CONFIG_UPDATE_PDU_SIZE + 128*1024)
+#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (CONFIG_UPDATE_PDU_SIZE + 128 * 1024)
 /* Enable to send heatmap to AP */
 #define CONFIG_USB_ISOCHRONOUS
 #elif defined(BOARD_ZED)
@@ -163,7 +163,7 @@
 #define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 511
 #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 1060 /* tenth of mm */
 #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 575 /* tenth of mm */
-#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (64*1024)
+#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (64 * 1024)
 #else
 #error "No touchpad information for board."
 #endif
@@ -175,8 +175,8 @@
 #endif
 
 /* Backlight */
-#if defined(BOARD_HAMMER) || defined(BOARD_STAFF) || \
-    defined(BOARD_WAND) || defined(BOARD_WHISKERS)
+#if defined(BOARD_HAMMER) || defined(BOARD_STAFF) || defined(BOARD_WAND) || \
+	defined(BOARD_WHISKERS)
 /*
  * Even with this option, we detect the backlight presence using a PU/PD on the
  * PWM pin. Not defining this totally disables support.
@@ -196,9 +196,9 @@
 #endif /* BOARD_HAMMER/WAND/WHISKERS */
 
 /* GMR sensor for tablet mode detection */
-#if defined(BOARD_DON) || defined(BOARD_MASTERBALL) || \
-    defined(BOARD_MOONBALL) || defined(BOARD_WHISKERS) || \
-    defined(BOARD_EEL)
+#if defined(BOARD_DON) || defined(BOARD_MASTERBALL) ||        \
+	defined(BOARD_MOONBALL) || defined(BOARD_WHISKERS) || \
+	defined(BOARD_EEL)
 #define CONFIG_GMR_TABLET_MODE
 #endif
 
diff --git a/board/hatch/battery.c b/board/hatch/battery.c
index b81fa795b9..444262b353 100644
--- a/board/hatch/battery.c
+++ b/board/hatch/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/hatch/board.c b/board/hatch/board.c
index 1cb3282299..a15e276113 100644
--- a/board/hatch/board.c
+++ b/board/hatch/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -42,8 +42,8 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* GPIO to enable/disable the USB Type-A port. */
 const int usb_port_enable[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT] = {
@@ -109,16 +109,16 @@ static void bc12_interrupt(enum gpio_signal signal)
 
 /******************************************************************************/
 /* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
+const struct spi_device_t spi_devices[] = {};
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
 /******************************************************************************/
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT]   = { .channel = 3, .flags = 0, .freq = 10000 },
-	[PWM_CH_FAN] = {.channel = 5, .flags = PWM_CONFIG_OPEN_DRAIN,
-			.freq = 25000},
+	[PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 },
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
@@ -144,16 +144,20 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_TCPC_0] = {
-		.usb_port = USB_PD_PORT_TCPC_0,
-		.driver = &anx7447_usb_mux_driver,
-		.hpd_update = &anx7447_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_0,
+			.driver = &anx7447_usb_mux_driver,
+			.hpd_update = &anx7447_tcpc_update_hpd_status,
+		},
 	},
 	[USB_PD_PORT_TCPC_1] = {
-		.usb_port = USB_PD_PORT_TCPC_1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 	}
 };
 
@@ -220,22 +224,18 @@ static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
 };
 
 /* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					      { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
 
 /*
  * TODO(b/124337208): P0 boards don't have this sensor mounted so the rotation
  * matrix can't be tested properly. This needs to be revisited after EVT to make
  * sure the rotaiton matrix for the lid sensor is correct.
  */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+					     { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
@@ -359,7 +359,7 @@ BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
 
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
@@ -378,32 +378,31 @@ const struct fan_t fans[FAN_CH_COUNT] = {
 /******************************************************************************/
 /* MFT channels. These are logically separate from pwm_channels. */
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN },
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_2] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_1] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_2] = { "TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Temp1",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Temp2",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_2},
+	[TEMP_SENSOR_1] = { .name = "Temp1",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Temp2",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
-
 /* Hatch Temperature sensors */
 /*
  * TODO(b/124316213): These setting need to be reviewed and set appropriately
@@ -413,8 +412,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_A \
-	{ \
+#define THERMAL_A                \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = 0, \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
@@ -469,7 +468,6 @@ static void board_gpio_set_pp5000(void)
 	} else if (board_id >= 1) {
 		reset_gpio_flags(GPIO_EN_PP5000_A_V1, GPIO_OUT_LOW);
 	}
-
 }
 
 static void board_init(void)
diff --git a/board/hatch/board.h b/board/hatch/board.h
index 78c97372ec..0de9a4828f 100644
--- a/board/hatch/board.h
+++ b/board/hatch/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -43,7 +43,7 @@
 #define CONFIG_ALS_TCS3400
 #define CONFIG_ALS_TCS3400_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS)
-#define I2C_PORT_ALS      I2C_PORT_SENSOR
+#define I2C_PORT_ALS I2C_PORT_SENSOR
 
 /* USB Type C and USB PD defines */
 #define CONFIG_USB_PD_COMM_LOCKED
@@ -107,16 +107,16 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_AC_PRESENT		GPIO_ACOK_OD
-#define GPIO_PG_EC_RSMRST_ODL	GPIO_PG_EC_RSMRST_L
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_TEMP_SENSOR_POWER	GPIO_EN_A_RAILS
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L
+#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
 
 #ifndef __ASSEMBLER__
 
@@ -128,8 +128,8 @@
 extern enum gpio_signal gpio_en_pp5000_a;
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_1,	/* ADC0 */
-	ADC_TEMP_SENSOR_2,	/* ADC1 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
 	ADC_CH_COUNT
 };
 
@@ -142,11 +142,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_FAN,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_FAN, PWM_CH_COUNT };
 
 enum fan_channel {
 	FAN_CH_0 = 0,
@@ -160,11 +156,7 @@ enum mft_channel {
 	MFT_CH_COUNT,
 };
 
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_COUNT
-};
+enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
diff --git a/board/hatch/build.mk b/board/hatch/build.mk
index 733912454f..13153c1526 100644
--- a/board/hatch/build.mk
+++ b/board/hatch/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/hatch/ec.tasklist b/board/hatch/ec.tasklist
index 4a1024a091..829be2b7c8 100644
--- a/board/hatch/ec.tasklist
+++ b/board/hatch/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/hatch/gpio.inc b/board/hatch/gpio.inc
index cd241f15f5..22cda73feb 100644
--- a/board/hatch/gpio.inc
+++ b/board/hatch/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,10 +16,10 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(PG_EC_RSMRST_L,       PIN(E, 2), GPIO_INT_BOTH, intel_x86_rsmrst_signal_interrupt)
diff --git a/board/hatch/led.c b/board/hatch/led.c
index d03aed0585..5bb76e1812 100644
--- a/board/hatch/led.c
+++ b/board/hatch/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,22 +19,26 @@ __override const int led_charge_lvl_1 = 5;
 __override const int led_charge_lvl_2 = 95;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
diff --git a/board/hatch_fp/board.c b/board/hatch_fp/board.c
index b48dce2b7e..00e7949083 100644
--- a/board/hatch_fp/board.c
+++ b/board/hatch_fp/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/hatch_fp/board.h b/board/hatch_fp/board.h
index 290e0f80e6..d36a9228c1 100644
--- a/board/hatch_fp/board.h
+++ b/board/hatch_fp/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -59,28 +59,28 @@
 
 #define CONFIG_FLASH_WRITE_SIZE STM32_FLASH_WRITE_SIZE_3300
 
-#define CONFIG_SHAREDLIB_SIZE   0
+#define CONFIG_SHAREDLIB_SIZE 0
 
-#define CONFIG_RO_MEM_OFF       0
-#define CONFIG_RO_STORAGE_OFF   0
-#define CONFIG_RO_SIZE          (128 * 1024)
+#define CONFIG_RO_MEM_OFF 0
+#define CONFIG_RO_STORAGE_OFF 0
+#define CONFIG_RO_SIZE (128 * 1024)
 
 /* EC rollback protection block */
 #define CONFIG_ROLLBACK_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
 #define CONFIG_ROLLBACK_SIZE (128 * 1024 * 2) /* 2 blocks of 128KB each */
 
-#define CONFIG_RW_MEM_OFF	(CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE)
-#define CONFIG_RW_STORAGE_OFF	0
-#define CONFIG_RW_SIZE		(CONFIG_FLASH_SIZE_BYTES -		\
-				(CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF))
+#define CONFIG_RW_MEM_OFF (CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE)
+#define CONFIG_RW_STORAGE_OFF 0
+#define CONFIG_RW_SIZE \
+	(CONFIG_FLASH_SIZE_BYTES - (CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF))
 
-#define CONFIG_EC_PROTECTED_STORAGE_OFF         CONFIG_RO_MEM_OFF
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE        CONFIG_RO_SIZE
-#define CONFIG_EC_WRITABLE_STORAGE_OFF          CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE         CONFIG_RW_SIZE
+#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF
+#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE
+#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE
 
-#define CONFIG_WP_STORAGE_OFF           CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE          CONFIG_EC_PROTECTED_STORAGE_SIZE
+#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
+#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
 
 /*
  * We want to prevent flash readout, and use it as indicator of protection
@@ -189,7 +189,7 @@
 
 /* SPI configuration for the fingerprint sensor */
 #define CONFIG_SPI_CONTROLLER
-#define CONFIG_SPI_FP_PORT  0 /* SPI2: first master config */
+#define CONFIG_SPI_FP_PORT 0 /* SPI2: first master config */
 #define CONFIG_FINGERPRINT_MCU
 #ifdef SECTION_IS_RW
 #define CONFIG_FP_SENSOR_FPC1025
@@ -230,7 +230,7 @@
 #define CONFIG_HOST_COMMAND_STATUS
 #define CONFIG_MKBP_EVENT
 #define CONFIG_MKBP_USE_GPIO
-#define CONFIG_PRINTF_LEGACY_LI_FORMAT
+#define CONFIG_PRINTF_LONG_IS_32BITS
 #define CONFIG_RNG
 #define CONFIG_SHA256
 #define CONFIG_SHA256_UNROLLED
diff --git a/board/hatch_fp/board_rw.c b/board/hatch_fp/board_rw.c
index 00a6b89b19..93a62b09bc 100644
--- a/board/hatch_fp/board_rw.c
+++ b/board/hatch_fp/board_rw.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/hatch_fp/board_rw.h b/board/hatch_fp/board_rw.h
index 1bee6c947d..fc38dcc259 100644
--- a/board/hatch_fp/board_rw.h
+++ b/board/hatch_fp/board_rw.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/hatch_fp/build.mk b/board/hatch_fp/build.mk
index cffb093fc8..d42dc15918 100644
--- a/board/hatch_fp/build.mk
+++ b/board/hatch_fp/build.mk
@@ -1,4 +1,4 @@
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -31,6 +31,7 @@ test-list-y=\
        compile_time_macros \
        cortexm_fpu \
        crc \
+       debug \
        flash_physical \
        flash_write_protect \
        fpsensor \
@@ -49,6 +50,7 @@ test-list-y=\
        sha256 \
        sha256_unrolled \
        static_if \
+       stdlib \
        stm32f_rtc \
        system_is_locked \
        timer_dos \
diff --git a/board/hatch_fp/ec.tasklist b/board/hatch_fp/ec.tasklist
index ed1e6ed294..2a4771fa98 100644
--- a/board/hatch_fp/ec.tasklist
+++ b/board/hatch_fp/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/hatch_fp/fpsensor_detect.c b/board/hatch_fp/fpsensor_detect.c
index 638b5fbfe0..7e3b99cac7 100644
--- a/board/hatch_fp/fpsensor_detect.c
+++ b/board/hatch_fp/fpsensor_detect.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/hatch_fp/fpsensor_detect_rw.c b/board/hatch_fp/fpsensor_detect_rw.c
index 274cfee054..2a313cda18 100644
--- a/board/hatch_fp/fpsensor_detect_rw.c
+++ b/board/hatch_fp/fpsensor_detect_rw.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/hatch_fp/gpio.inc b/board/hatch_fp/gpio.inc
index c5319c2bee..dc185751bc 100644
--- a/board/hatch_fp/gpio.inc
+++ b/board/hatch_fp/gpio.inc
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/hatch_fp/gpio_rw.inc b/board/hatch_fp/gpio_rw.inc
index 3dfe890c12..dc82cd984a 100644
--- a/board/hatch_fp/gpio_rw.inc
+++ b/board/hatch_fp/gpio_rw.inc
@@ -1,5 +1,5 @@
 /*
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/helios/battery.c b/board/helios/battery.c
index c7168caf8a..dcc9503244 100644
--- a/board/helios/battery.c
+++ b/board/helios/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/helios/board.c b/board/helios/board.c
index b4d2fb1ef8..256459314c 100644
--- a/board/helios/board.c
+++ b/board/helios/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -44,8 +44,8 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void ppc_interrupt(enum gpio_signal signal)
 {
@@ -134,16 +134,16 @@ static void board_gmr_tablet_switch_isr(enum gpio_signal signal)
 
 /******************************************************************************/
 /* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
+const struct spi_device_t spi_devices[] = {};
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
 /******************************************************************************/
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT]   = { .channel = 3, .flags = 0, .freq = 10000 },
-	[PWM_CH_FAN] = {.channel = 5, .flags = PWM_CONFIG_OPEN_DRAIN,
-			.freq = 25000},
+	[PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 },
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
@@ -168,16 +168,20 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_TCPC_0] = {
-		.usb_port = USB_PD_PORT_TCPC_0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_0,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 	},
 	[USB_PD_PORT_TCPC_1] = {
-		.usb_port = USB_PD_PORT_TCPC_1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 	}
 };
 
@@ -215,22 +219,18 @@ enum base_accelgyro_type {
 static enum base_accelgyro_type base_accelgyro_config;
 
 /* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					      { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
 
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					     { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
 static const mat33_fp_t base_standard_ref_icm = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)},
+	{ FLOAT_TO_FP(-1), 0, 0 },
+	{ 0, FLOAT_TO_FP(1), 0 },
+	{ 0, 0, FLOAT_TO_FP(-1) },
 };
 
 struct motion_sensor_t icm426xx_base_accel = {
@@ -379,8 +379,7 @@ static void board_detect_motionsense(void)
 		ccprints("Base Accelgyro: BMI160");
 	}
 }
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_detect_motionsense,
-	     HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_detect_motionsense, HOOK_PRIO_DEFAULT);
 DECLARE_HOOK(HOOK_INIT, board_detect_motionsense, HOOK_PRIO_INIT_I2C + 1);
 
 /******************************************************************************/
@@ -388,7 +387,7 @@ DECLARE_HOOK(HOOK_INIT, board_detect_motionsense, HOOK_PRIO_INIT_I2C + 1);
 
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
@@ -407,40 +406,40 @@ const struct fan_t fans[FAN_CH_COUNT] = {
 /******************************************************************************/
 /* MFT channels. These are logically separate from pwm_channels. */
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN },
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		"TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_2] = {
-		"TEMP_5V_REG", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_3] = {
-		"TEMP_AMB", NPCX_ADC_CH3, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_4] = {
-		"TEMP_CPU", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_1] = { "TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_2] = { "TEMP_5V_REG", NPCX_ADC_CH1, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_3] = { "TEMP_AMB", NPCX_ADC_CH3, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_4] = { "TEMP_CPU", NPCX_ADC_CH2, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Temp1",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Temp2",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "Temp3",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_3},
-	[TEMP_SENSOR_4] = {.name = "Temp4",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_4},
+	[TEMP_SENSOR_1] = { .name = "Temp1",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Temp2",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "Temp3",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
+	[TEMP_SENSOR_4] = { .name = "Temp4",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_4 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -448,8 +447,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_A \
-	{ \
+#define THERMAL_A                \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = 0, \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
@@ -500,8 +499,8 @@ int board_tcpc_post_init(int port)
 		/* Set MUX_DP_EQ to 3.6dB (0x98) */
 		rv = tcpc_write(port, PS8XXX_REG_MUX_DP_EQ_CONFIGURATION, 0x98);
 	else if (port == USB_PD_PORT_TCPC_1)
-		rv = tcpc_write(port,
-				PS8XXX_REG_MUX_USB_C2SS_HS_THRESHOLD, 0x80);
+		rv = tcpc_write(port, PS8XXX_REG_MUX_USB_C2SS_HS_THRESHOLD,
+				0x80);
 
 	return rv;
 }
diff --git a/board/helios/board.h b/board/helios/board.h
index 174c5157b6..83ffd2b4b7 100644
--- a/board/helios/board.h
+++ b/board/helios/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -56,7 +56,7 @@
  * Helios' battery takes several seconds to come back out of its disconnect
  * state (~4.2 seconds on the unit I have, so give it a little more for margin).
  */
-#undef  CONFIG_POWER_BUTTON_INIT_TIMEOUT
+#undef CONFIG_POWER_BUTTON_INIT_TIMEOUT
 #define CONFIG_POWER_BUTTON_INIT_TIMEOUT 6
 
 /* BC 1.2 */
@@ -85,16 +85,16 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_AC_PRESENT		GPIO_ACOK_OD
-#define GPIO_PG_EC_RSMRST_ODL	GPIO_PG_EC_RSMRST_L
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_TEMP_SENSOR_POWER	GPIO_EN_A_RAILS
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L
+#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
 
 #ifndef __ASSEMBLER__
 
@@ -102,10 +102,10 @@
 #include "registers.h"
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_1,	/* ADC0 */
-	ADC_TEMP_SENSOR_2,	/* ADC1 */
-	ADC_TEMP_SENSOR_3,	/* ADC3 */
-	ADC_TEMP_SENSOR_4,	/* ADC2 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
+	ADC_TEMP_SENSOR_3, /* ADC3 */
+	ADC_TEMP_SENSOR_4, /* ADC2 */
 	ADC_CH_COUNT
 };
 
@@ -117,11 +117,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_FAN,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_FAN, PWM_CH_COUNT };
 
 enum fan_channel {
 	FAN_CH_0 = 0,
diff --git a/board/helios/build.mk b/board/helios/build.mk
index 733912454f..13153c1526 100644
--- a/board/helios/build.mk
+++ b/board/helios/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/helios/ec.tasklist b/board/helios/ec.tasklist
index 63d366a33b..7fb3e38b63 100644
--- a/board/helios/ec.tasklist
+++ b/board/helios/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/helios/gpio.inc b/board/helios/gpio.inc
index d16e1643be..65fc10f761 100644
--- a/board/helios/gpio.inc
+++ b/board/helios/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,10 +17,10 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(PG_EC_RSMRST_L,       PIN(E, 2), GPIO_INT_BOTH, intel_x86_rsmrst_signal_interrupt)
diff --git a/board/helios/led.c b/board/helios/led.c
index 7a63c4401c..92fb7d80ce 100644
--- a/board/helios/led.c
+++ b/board/helios/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,29 +19,37 @@ __override const int led_charge_lvl_1 = 5;
 __override const int led_charge_lvl_2 = 95;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
 __override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	     3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	     3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    1 * LED_ONE_SEC },
+						  { LED_OFF,
+						    3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
 const enum ec_led_id supported_led_ids[] = {
 	EC_LED_ID_BATTERY_LED,
diff --git a/board/herobrine/battery.c b/board/herobrine/battery.c
index 38e22aafb3..84c43cc263 100644
--- a/board/herobrine/battery.c
+++ b/board/herobrine/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/herobrine/board.c b/board/herobrine/board.c
index fea8bf3a88..1ef1801c44 100644
--- a/board/herobrine/board.c
+++ b/board/herobrine/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,8 +26,8 @@
 #include "usbc_config.h"
 #include "usbc_ppc.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 #include "gpio_list.h"
 
@@ -50,10 +50,8 @@ __override struct keyboard_scan_config keyscan_config = {
 	 * Unmask 0x08 in [0] (KSO_00/KSI_03, the new location of Search key);
 	 * as it still uses the legacy location (KSO_01/KSI_00).
 	 */
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca
-	},
+	.actual_key_mask = { 0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, 0xa4,
+			     0xff, 0xfe, 0x55, 0xfa, 0xca },
 	/* Other values should be the same as the default configuration. */
 	.debounce_down_us = 9 * MSEC,
 	.debounce_up_us = 30 * MSEC,
@@ -64,48 +62,36 @@ __override struct keyboard_scan_config keyscan_config = {
 
 /* I2C port map */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl  = GPIO_EC_I2C_POWER_SCL,
-		.sda  = GPIO_EC_I2C_POWER_SDA
-	},
-	{
-		.name = "tcpc0",
-		.port = I2C_PORT_TCPC0,
-		.kbps = 1000,
-		.scl  = GPIO_EC_I2C_USB_C0_PD_SCL,
-		.sda  = GPIO_EC_I2C_USB_C0_PD_SDA
-	},
-	{
-		.name = "tcpc1",
-		.port = I2C_PORT_TCPC1,
-		.kbps = 1000,
-		.scl  = GPIO_EC_I2C_USB_C1_PD_SCL,
-		.sda  = GPIO_EC_I2C_USB_C1_PD_SDA
-	},
-	{
-		.name = "rtc",
-		.port = I2C_PORT_RTC,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_RTC_SCL,
-		.sda  = GPIO_EC_I2C_RTC_SDA
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_EEPROM_SCL,
-		.sda  = GPIO_EC_I2C_EEPROM_SDA
-	},
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_SENSOR_SCL,
-		.sda  = GPIO_EC_I2C_SENSOR_SDA
-	},
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_POWER_SCL,
+	  .sda = GPIO_EC_I2C_POWER_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C0_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C0_PD_SDA },
+	{ .name = "tcpc1",
+	  .port = I2C_PORT_TCPC1,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C1_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C1_PD_SDA },
+	{ .name = "rtc",
+	  .port = I2C_PORT_RTC,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_RTC_SCL,
+	  .sda = GPIO_EC_I2C_RTC_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_EEPROM_SCL,
+	  .sda = GPIO_EC_I2C_EEPROM_SDA },
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_SENSOR_SCL,
+	  .sda = GPIO_EC_I2C_SENSOR_SDA },
 };
 
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
@@ -113,37 +99,22 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* Measure VBUS through a 1/10 voltage divider */
-	[ADC_VBUS] = {
-		"VBUS",
-		NPCX_ADC_CH1,
-		ADC_MAX_VOLT * 10,
-		ADC_READ_MAX + 1,
-		0
-	},
+	[ADC_VBUS] = { "VBUS", NPCX_ADC_CH1, ADC_MAX_VOLT * 10,
+		       ADC_READ_MAX + 1, 0 },
 	/*
 	 * Adapter current output or battery charging/discharging current (uV)
 	 * 18x amplification on charger side.
 	 */
-	[ADC_AMON_BMON] = {
-		"AMON_BMON",
-		NPCX_ADC_CH2,
-		ADC_MAX_VOLT * 1000 / 18,
-		ADC_READ_MAX + 1,
-		0
-	},
+	[ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH2, ADC_MAX_VOLT * 1000 / 18,
+			    ADC_READ_MAX + 1, 0 },
 	/*
 	 * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read
 	 * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and
 	 * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we
 	 * only divide by 2 (enough to avoid precision issues).
 	 */
-	[ADC_PSYS] = {
-		"PSYS",
-		NPCX_ADC_CH3,
-		ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1),
-		2,
-		0
-	},
+	[ADC_PSYS] = { "PSYS", NPCX_ADC_CH3,
+		       ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), 2, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
@@ -214,17 +185,13 @@ static struct bmi_drv_data_t g_bmi260_data;
 static struct accelgyro_saved_data_t g_bma255_data;
 
 /* Matrix to rotate accelerometer into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0,  0},
-	{ 0,  FLOAT_TO_FP(-1),  0},
-	{ 0,  0, FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+				       { 0, FLOAT_TO_FP(-1), 0 },
+				       { 0, 0, FLOAT_TO_FP(-1) } };
 
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					     { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
diff --git a/board/herobrine/board.h b/board/herobrine/board.h
index 15cbcf305a..59580826f5 100644
--- a/board/herobrine/board.h
+++ b/board/herobrine/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,7 +25,7 @@
 #define CONFIG_PWM_KBLIGHT
 
 /* Battery */
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY  "LION"
+#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
 #define CONFIG_BATTERY_REVIVE_DISCONNECT
 #define CONFIG_BATTERY_FUEL_GAUGE
 
@@ -62,26 +62,21 @@
 #define CONFIG_GMR_TABLET_MODE
 
 /* GPIO alias */
-#define GPIO_AC_PRESENT		GPIO_ACOK_OD
-#define GPIO_WP_L		GPIO_EC_WP_ODL
-#define GPIO_SWITCHCAP_PG	GPIO_SRC_VPH_PWR_PG
-#define GPIO_ACOK_OD		GPIO_CHG_ACOK_OD
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_S5
-#define GPIO_POWER_GOOD		GPIO_MB_POWER_GOOD
-#define GPIO_EC_INT_L		GPIO_AP_EC_INT_L
-#define GPIO_DP_HOT_PLUG_DET	GPIO_DP_HOT_PLUG_DET_R
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_WP_L GPIO_EC_WP_ODL
+#define GPIO_SWITCHCAP_PG GPIO_SRC_VPH_PWR_PG
+#define GPIO_ACOK_OD GPIO_CHG_ACOK_OD
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_S5
+#define GPIO_POWER_GOOD GPIO_MB_POWER_GOOD
+#define GPIO_EC_INT_L GPIO_AP_EC_INT_L
+#define GPIO_DP_HOT_PLUG_DET GPIO_DP_HOT_PLUG_DET_R
 
 #ifndef __ASSEMBLER__
 
 #include "gpio_signal.h"
 #include "registers.h"
 
-enum adc_channel {
-	ADC_VBUS,
-	ADC_AMON_BMON,
-	ADC_PSYS,
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_VBUS, ADC_AMON_BMON, ADC_PSYS, ADC_CH_COUNT };
 
 /* Motion sensors */
 enum sensor_id {
@@ -91,11 +86,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_DISPLIGHT,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_DISPLIGHT, PWM_CH_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
diff --git a/board/herobrine/build.mk b/board/herobrine/build.mk
index 601c45a042..6827780a6c 100644
--- a/board/herobrine/build.mk
+++ b/board/herobrine/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/herobrine/ec.tasklist b/board/herobrine/ec.tasklist
index 5beeb38feb..228828af3c 100644
--- a/board/herobrine/ec.tasklist
+++ b/board/herobrine/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/herobrine/gpio.inc b/board/herobrine/gpio.inc
index 239bedd95d..9628684737 100644
--- a/board/herobrine/gpio.inc
+++ b/board/herobrine/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/herobrine/led.c b/board/herobrine/led.c
index 295c8effeb..fb68e85deb 100644
--- a/board/herobrine/led.c
+++ b/board/herobrine/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -31,15 +31,15 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static void side_led_set_color(int port, enum led_color color)
 {
 	gpio_set_level(port ? GPIO_EC_CHG_LED_Y_C1 : GPIO_EC_CHG_LED_Y_C0,
-		(color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
+		       (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
 	gpio_set_level(port ? GPIO_EC_CHG_LED_W_C1 : GPIO_EC_CHG_LED_W_C0,
-		(color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF);
+		       (color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF);
 }
 
 void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
@@ -90,7 +90,6 @@ static void set_active_port_color(enum led_color color)
 static void board_led_set_battery(void)
 {
 	static int battery_ticks;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
@@ -102,8 +101,9 @@ static void board_led_set_battery(void)
 	case PWR_STATE_DISCHARGE:
 		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
 			if (charge_get_percent() <= 10)
-				side_led_set_color(0,
-				   (battery_ticks & 0x4) ? LED_WHITE : LED_OFF);
+				side_led_set_color(0, (battery_ticks & 0x4) ?
+							      LED_WHITE :
+							      LED_OFF);
 			else
 				side_led_set_color(0, LED_OFF);
 		}
@@ -112,18 +112,18 @@ static void board_led_set_battery(void)
 			side_led_set_color(1, LED_OFF);
 		break;
 	case PWR_STATE_ERROR:
-		set_active_port_color((battery_ticks & 0x2) ?
-				LED_WHITE : LED_OFF);
+		set_active_port_color((battery_ticks & 0x2) ? LED_WHITE :
+							      LED_OFF);
 		break;
 	case PWR_STATE_CHARGE_NEAR_FULL:
 		set_active_port_color(LED_WHITE);
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			set_active_port_color((battery_ticks & 0x4) ?
-					LED_AMBER : LED_OFF);
-		else
-			set_active_port_color(LED_WHITE);
+		set_active_port_color(LED_WHITE);
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		set_active_port_color((battery_ticks & 0x4) ? LED_AMBER :
+							      LED_OFF);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
diff --git a/board/herobrine/switchcap.c b/board/herobrine/switchcap.c
index 16b0db6ef6..5173e27f75 100644
--- a/board/herobrine/switchcap.c
+++ b/board/herobrine/switchcap.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/herobrine/usbc_config.c b/board/herobrine/usbc_config.c
index 93ec401171..98d1b70bac 100644
--- a/board/herobrine/usbc_config.c
+++ b/board/herobrine/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,8 +23,8 @@
 #include "usbc_ocp.h"
 #include "usbc_ppc.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* GPIO Interrupt Handlers */
 void tcpc_alert_event(enum gpio_signal signal)
@@ -84,16 +84,12 @@ void ppc_interrupt(enum gpio_signal signal)
 
 /* Power Path Controller */
 struct ppc_config_t ppc_chips[] = {
-	{
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	{
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
+	{ .i2c_port = I2C_PORT_TCPC0,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
+	{ .i2c_port = I2C_PORT_TCPC1,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
 };
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
@@ -124,16 +120,22 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
  * to AP. But the TCPC chip is also needed to know the HPD status; otherwise,
  * the mux misbehaves.
  */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	},
 	{
-		.usb_port = 1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	}
 };
 
@@ -186,7 +188,7 @@ void board_tcpc_init(void)
 	 */
 	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
 		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
 DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
 
@@ -232,8 +234,7 @@ void board_overcurrent_event(int port, int is_overcurrented)
 
 int board_set_active_charge_port(int port)
 {
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	int i;
 
 	if (!is_real_port && port != CHARGE_PORT_NONE)
@@ -261,7 +262,6 @@ int board_set_active_charge_port(int port)
 		return EC_ERROR_INVAL;
 	}
 
-
 	CPRINTS("New charge port: p%d", port);
 
 	/*
@@ -285,23 +285,21 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	/*
 	 * Ignore lower charge ceiling on PD transition if our battery is
 	 * critical, as we may brownout.
 	 */
-	if (supplier == CHARGE_SUPPLIER_PD &&
-	    charge_ma < 1500 &&
+	if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 &&
 	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
 		CPRINTS("Using max ilim %d", max_ma);
 		charge_ma = max_ma;
 	}
 
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 uint16_t tcpc_get_alert_status(void)
diff --git a/board/herobrine/usbc_config.h b/board/herobrine/usbc_config.h
index 69f546ef85..da19a67d2d 100644
--- a/board/herobrine/usbc_config.h
+++ b/board/herobrine/usbc_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/hoho/board.c b/board/hoho/board.c
index 07b772c826..e981c9ce87 100644
--- a/board/hoho/board.c
+++ b/board/hoho/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -98,7 +98,7 @@ void board_config_pre_init(void)
 	/* enable SYSCFG clock */
 	STM32_RCC_APB2ENR |= BIT(0);
 	/* Remap USART DMA to match the USART driver */
-	STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10);/* Remap USART1 RX/TX DMA */
+	STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10); /* Remap USART1 RX/TX DMA */
 }
 
 #ifdef CONFIG_SPI_FLASH
@@ -142,11 +142,10 @@ static void factory_validation_deferred(void)
 
 	/* test mcdp via serial to validate function */
 	if (!mcdp_get_info(&info) && (MCDP_FAMILY(info.family) == 0x0010) &&
-	(MCDP_CHIPID(info.chipid) == 0x2850)) {
+	    (MCDP_CHIPID(info.chipid) == 0x2850)) {
 		gpio_set_level(GPIO_MCDP_READY, 1);
 		pd_log_event(PD_EVENT_VIDEO_CODEC,
-			     PD_LOG_PORT_SIZE(0, sizeof(info)),
-			     0, &info);
+			     PD_LOG_PORT_SIZE(0, sizeof(info)), 0, &info);
 	}
 
 	mcdp_disable();
@@ -167,7 +166,7 @@ static void board_init(void)
 
 	gpio_set_level(GPIO_STM_READY, 1); /* factory test only */
 	/* Delay needed to allow HDMI MCU to boot. */
-	hook_call_deferred(&factory_validation_deferred_data, 200*MSEC);
+	hook_call_deferred(&factory_validation_deferred_data, 200 * MSEC);
 }
 
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
@@ -175,13 +174,13 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* USB PD CC lines sensing. Converted to mV (3300mV/4096). */
-	[ADC_CH_CC1_PD] = {"USB_C_CC1_PD", 3300, 4096, 0, STM32_AIN(1)},
+	[ADC_CH_CC1_PD] = { "USB_C_CC1_PD", 3300, 4096, 0, STM32_AIN(1) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
-const void * const usb_strings[] = {
+const void *const usb_strings[] = {
 	[USB_STR_DESC] = usb_string_desc,
-	[USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."),
+	[USB_STR_VENDOR] = USB_STRING_DESC("Google LLC"),
 	[USB_STR_PRODUCT] = USB_STRING_DESC("Hoho"),
 	[USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32),
 	[USB_STR_BB_URL] = USB_STRING_DESC(USB_GOOGLE_TYPEC_URL),
diff --git a/board/hoho/board.h b/board/hoho/board.h
index 635abfbeda..7768ab7293 100644
--- a/board/hoho/board.h
+++ b/board/hoho/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -43,7 +43,7 @@
 #define CONFIG_USB_PD_IDENTITY_HW_VERS 1
 #define CONFIG_USB_PD_IDENTITY_SW_VERS 1
 #define CONFIG_USB_PD_LOGGING
-#undef  CONFIG_EVENT_LOG_SIZE
+#undef CONFIG_EVENT_LOG_SIZE
 #define CONFIG_EVENT_LOG_SIZE 256
 #define CONFIG_USB_PD_PORT_MAX_COUNT 1
 #define CONFIG_USB_PD_TCPC
@@ -72,7 +72,7 @@
 
 /* Timer selection */
 #define TIM_CLOCK32 2
-#define TIM_ADC     3
+#define TIM_ADC 3
 
 #include "gpio_signal.h"
 
@@ -95,14 +95,14 @@ enum usb_strings {
 };
 
 /* we are never a source : don't care about power supply */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  0 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 0 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 0 /* us */
 
 /* Define typical operating power and max power */
 #define PD_OPERATING_POWER_MW 1000
-#define PD_MAX_POWER_MW       1500
-#define PD_MAX_CURRENT_MA     300
-#define PD_MAX_VOLTAGE_MV     5000
+#define PD_MAX_POWER_MW 1500
+#define PD_MAX_CURRENT_MA 300
+#define PD_MAX_VOLTAGE_MV 5000
 
 #endif /* !__ASSEMBLER__ */
 
@@ -110,10 +110,10 @@ enum usb_strings {
 #define USB_DEV_CLASS USB_CLASS_BILLBOARD
 
 /* USB interface indexes (use define rather than enum to expand them) */
-#define USB_IFACE_COUNT     0
+#define USB_IFACE_COUNT 0
 
 /* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL   0
-#define USB_EP_COUNT     1
+#define USB_EP_CONTROL 0
+#define USB_EP_COUNT 1
 
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/hoho/build.mk b/board/hoho/build.mk
index 71cea3f845..b6fbbe7a9e 100644
--- a/board/hoho/build.mk
+++ b/board/hoho/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
+# Copyright 2014 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/hoho/ec.tasklist b/board/hoho/ec.tasklist
index 41fc047d6a..5a82344122 100644
--- a/board/hoho/ec.tasklist
+++ b/board/hoho/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/hoho/gpio.inc b/board/hoho/gpio.inc
index 6d0701ded1..56a4f8808e 100644
--- a/board/hoho/gpio.inc
+++ b/board/hoho/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
+ * Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/hoho/usb_pd_config.h b/board/hoho/usb_pd_config.h
index 2f01c275a8..5a7dfd12a6 100644
--- a/board/hoho/usb_pd_config.h
+++ b/board/hoho/usb_pd_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -49,7 +49,7 @@ static inline void spi_enable_clock(int port)
 
 #define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
 #define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
-#define TIM_CCR_CS  1
+#define TIM_CCR_CS 1
 #define EXTI_COMP_MASK(p) BIT(21)
 #define IRQ_COMP STM32_IRQ_COMP
 /* triggers packet detection on comparator falling edge */
@@ -88,9 +88,8 @@ static inline void pd_tx_enable(int port, int polarity)
 static inline void pd_tx_disable(int port, int polarity)
 {
 	/* output low on SPI TX (PB4) to disable the FET */
-	STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B)
-				   & ~(3 << (2*4)))
-				   |  (1 << (2*4));
+	STM32_GPIO_MODER(GPIO_B) =
+		(STM32_GPIO_MODER(GPIO_B) & ~(3 << (2 * 4))) | (1 << (2 * 4));
 	/* put the low level reference in Hi-Z */
 	gpio_set_level(GPIO_PD_CC1_TX_EN, 0);
 }
@@ -101,8 +100,8 @@ static inline void pd_select_polarity(int port, int polarity)
 	 * use the right comparator : CC1 -> PA1 (COMP1 INP)
 	 * use VrefInt / 2 as INM (about 600mV)
 	 */
-	STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK)
-		| STM32_COMP_CMP1EN | STM32_COMP_CMP1INSEL_VREF12;
+	STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK) |
+			 STM32_COMP_CMP1EN | STM32_COMP_CMP1INSEL_VREF12;
 }
 
 /* Initialize pins used for TX and put them in Hi-Z */
@@ -111,7 +110,9 @@ static inline void pd_tx_init(void)
 	gpio_config_module(MODULE_USB_PD, 1);
 }
 
-static inline void pd_set_host_mode(int port, int enable) {}
+static inline void pd_set_host_mode(int port, int enable)
+{
+}
 
 static inline void pd_config_init(int port, uint8_t power_role)
 {
diff --git a/board/hoho/usb_pd_pdo.c b/board/hoho/usb_pd_pdo.c
index 19b5d127a5..c52179acfc 100644
--- a/board/hoho/usb_pd_pdo.c
+++ b/board/hoho/usb_pd_pdo.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,6 +13,6 @@ const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
 
 /* Fake PDOs : we just want our pre-defined voltages */
 const uint32_t pd_snk_pdo[] = {
-		PDO_FIXED(5000, 500, PDO_FIXED_COMM_CAP),
+	PDO_FIXED(5000, 500, PDO_FIXED_COMM_CAP),
 };
 const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
diff --git a/board/hoho/usb_pd_pdo.h b/board/hoho/usb_pd_pdo.h
index 8a43db795e..e04c3aa677 100644
--- a/board/hoho/usb_pd_pdo.h
+++ b/board/hoho/usb_pd_pdo.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/hoho/usb_pd_policy.c b/board/hoho/usb_pd_policy.c
index 73f3fca16e..baf05d0e71 100644
--- a/board/hoho/usb_pd_policy.c
+++ b/board/hoho/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,8 +21,8 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 /* Holds valid object position (opos) for entered mode */
 static int alt_mode[PD_AMODE_COUNT];
@@ -54,22 +54,18 @@ __override int pd_check_power_swap(int port)
 	return 0;
 }
 
-__override int pd_check_data_swap(int port,
-				  enum pd_data_role data_role)
+__override int pd_check_data_swap(int port, enum pd_data_role data_role)
 {
 	/* Always refuse data swap */
 	return 0;
 }
 
-__override void pd_check_pr_role(int port,
-				 enum pd_power_role pr_role,
+__override void pd_check_pr_role(int port, enum pd_power_role pr_role,
 				 int flags)
 {
 }
 
-__override void pd_check_dr_role(int port,
-				 enum pd_data_role dr_role,
-				 int flags)
+__override void pd_check_dr_role(int port, enum pd_data_role dr_role, int flags)
 {
 }
 /* ----------------- Vendor Defined Messages ------------------ */
@@ -82,8 +78,8 @@ const uint32_t vdo_idh = VDO_IDH(0, /* data caps as USB host */
 const uint32_t vdo_product = VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV);
 
 const uint32_t vdo_ama = VDO_AMA(CONFIG_USB_PD_IDENTITY_HW_VERS,
-				 CONFIG_USB_PD_IDENTITY_SW_VERS,
-				 0, 0, 0, 0, /* SS[TR][12] */
+				 CONFIG_USB_PD_IDENTITY_SW_VERS, 0, 0, 0,
+				 0, /* SS[TR][12] */
 				 0, /* Vconn power */
 				 0, /* Vconn power required */
 				 1, /* Vbus power required */
@@ -109,18 +105,16 @@ static int svdm_response_svids(int port, uint32_t *payload)
 #define OPOS_DP 1
 #define OPOS_GFU 1
 
-const uint32_t vdo_dp_modes[1] =  {
-	VDO_MODE_DP(0,		   /* UFP pin cfg supported : none */
+const uint32_t vdo_dp_modes[1] = {
+	VDO_MODE_DP(0, /* UFP pin cfg supported : none */
 		    MODE_DP_PIN_C, /* DFP pin cfg supported */
-		    1,		   /* no usb2.0	signalling in AMode */
-		    CABLE_PLUG,	   /* its a plug */
-		    MODE_DP_V13,   /* DPv1.3 Support, no Gen2 */
-		    MODE_DP_SNK)   /* Its a sink only */
+		    1, /* no usb2.0	signalling in AMode */
+		    CABLE_PLUG, /* its a plug */
+		    MODE_DP_V13, /* DPv1.3 Support, no Gen2 */
+		    MODE_DP_SNK) /* Its a sink only */
 };
 
-const uint32_t vdo_goog_modes[1] =  {
-	VDO_MODE_GOOGLE(MODE_GOOGLE_FU)
-};
+const uint32_t vdo_goog_modes[1] = { VDO_MODE_GOOGLE(MODE_GOOGLE_FU) };
 
 static int svdm_response_modes(int port, uint32_t *payload)
 {
@@ -142,13 +136,15 @@ static int dp_status(int port, uint32_t *payload)
 	if (opos != OPOS_DP)
 		return 0; /* nak */
 
-	payload[1] = VDO_DP_STATUS(0,                /* IRQ_HPD */
-				   (hpd == 1),       /* HPD_HI|LOW */
-				   0,		     /* request exit DP */
-				   0,		     /* request exit USB */
-				   0,		     /* MF pref */
+	payload[1] = VDO_DP_STATUS(0, /* IRQ_HPD */
+				   (hpd == 1), /* HPD_HI|LOW */
+				   0, /* request exit DP */
+				   0, /* request exit USB */
+				   0, /* MF pref */
 				   gpio_get_level(GPIO_PD_SBU_ENABLE),
-				   0,		     /* power low */
+				   0, /* power
+					 low
+				       */
 				   0x2);
 	return 2;
 }
@@ -227,8 +223,7 @@ const struct svdm_response svdm_rsp = {
 	.exit_mode = &svdm_exit_mode,
 };
 
-int pd_custom_vdm(int port, int cnt, uint32_t *payload,
-		  uint32_t **rpayload)
+int pd_custom_vdm(int port, int cnt, uint32_t *payload, uint32_t **rpayload)
 {
 	int rsize;
 
diff --git a/board/homestar/base_detect.c b/board/homestar/base_detect.c
index b08784357b..7625db02d7 100644
--- a/board/homestar/base_detect.c
+++ b/board/homestar/base_detect.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,8 +19,8 @@
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
 /* Make sure POGO VBUS starts later then PP3300_HUB when power on  */
 #define BASE_DETECT_EN_LATER_US (600 * MSEC)
@@ -96,8 +96,8 @@ static uint32_t pulse_width;
 
 static void print_base_detect_value(int v, int tmp_pulse_width)
 {
-	CPRINTS("%s = %d (pulse %d)", adc_channels[ADC_BASE_DET].name,
-			v, tmp_pulse_width);
+	CPRINTS("%s = %d (pulse %d)", adc_channels[ADC_BASE_DET].name, v,
+		tmp_pulse_width);
 }
 
 static void base_detect_deferred(void)
@@ -188,8 +188,7 @@ static void base_enable(void)
 {
 	/* Enable base detection interrupt. */
 	base_detect_debounce_time = get_time().val;
-	hook_call_deferred(&base_detect_deferred_data,
-			BASE_DETECT_EN_LATER_US);
+	hook_call_deferred(&base_detect_deferred_data, BASE_DETECT_EN_LATER_US);
 	gpio_enable_interrupt(GPIO_BASE_DET_L);
 }
 DECLARE_HOOK(HOOK_CHIPSET_STARTUP, base_enable, HOOK_PRIO_DEFAULT);
@@ -215,7 +214,7 @@ static void base_init(void)
 	if (system_jumped_late() && chipset_in_state(CHIPSET_STATE_ON))
 		base_enable();
 }
-DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT+1);
+DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT + 1);
 
 void base_force_state(enum ec_set_base_state_cmd state)
 {
diff --git a/board/homestar/battery.c b/board/homestar/battery.c
index 7cfd201b0f..01fdb29f6a 100644
--- a/board/homestar/battery.c
+++ b/board/homestar/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/homestar/board.c b/board/homestar/board.c
index 05c9759355..ab4b95b625 100644
--- a/board/homestar/board.c
+++ b/board/homestar/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -39,10 +39,10 @@
 #include "task.h"
 #include "usbc_ppc.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define KS_DEBOUNCE_US    (30 * MSEC)  /* Debounce time for kickstand switch */
+#define KS_DEBOUNCE_US (30 * MSEC) /* Debounce time for kickstand switch */
 
 /* Forward declaration */
 static void tcpc_alert_event(enum gpio_signal signal);
@@ -119,41 +119,31 @@ static void switchcap_interrupt(enum gpio_signal signal)
 
 /* I2C port map */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl  = GPIO_EC_I2C_POWER_SCL,
-		.sda  = GPIO_EC_I2C_POWER_SDA
-	},
-	{
-		.name = "tcpc0",
-		.port = I2C_PORT_TCPC0,
-		.kbps = 1000,
-		.scl  = GPIO_EC_I2C_USB_C0_PD_SCL,
-		.sda  = GPIO_EC_I2C_USB_C0_PD_SDA
-	},
-	{
-		.name = "tcpc1",
-		.port = I2C_PORT_TCPC1,
-		.kbps = 1000,
-		.scl  = GPIO_EC_I2C_USB_C1_PD_SCL,
-		.sda  = GPIO_EC_I2C_USB_C1_PD_SDA
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_EEPROM_SCL,
-		.sda  = GPIO_EC_I2C_EEPROM_SDA
-	},
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_SENSOR_SCL,
-		.sda  = GPIO_EC_I2C_SENSOR_SDA
-	},
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_POWER_SCL,
+	  .sda = GPIO_EC_I2C_POWER_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C0_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C0_PD_SDA },
+	{ .name = "tcpc1",
+	  .port = I2C_PORT_TCPC1,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C1_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C1_PD_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_EEPROM_SCL,
+	  .sda = GPIO_EC_I2C_EEPROM_SDA },
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_SENSOR_SCL,
+	  .sda = GPIO_EC_I2C_SENSOR_SDA },
 };
 
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
@@ -161,45 +151,25 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* Measure VBUS through a 1/10 voltage divider */
-	[ADC_VBUS] = {
-		"VBUS",
-		NPCX_ADC_CH1,
-		ADC_MAX_VOLT * 10,
-		ADC_READ_MAX + 1,
-		0
-	},
+	[ADC_VBUS] = { "VBUS", NPCX_ADC_CH1, ADC_MAX_VOLT * 10,
+		       ADC_READ_MAX + 1, 0 },
 	/*
 	 * Adapter current output or battery charging/discharging current (uV)
 	 * 18x amplification on charger side.
 	 */
-	[ADC_AMON_BMON] = {
-		"AMON_BMON",
-		NPCX_ADC_CH2,
-		ADC_MAX_VOLT * 1000 / 18,
-		ADC_READ_MAX + 1,
-		0
-	},
+	[ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH2, ADC_MAX_VOLT * 1000 / 18,
+			    ADC_READ_MAX + 1, 0 },
 	/*
 	 * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read
 	 * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and
 	 * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we
 	 * only divide by 2 (enough to avoid precision issues).
 	 */
-	[ADC_PSYS] = {
-		"PSYS",
-		NPCX_ADC_CH3,
-		ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1),
-		2,
-		0
-	},
+	[ADC_PSYS] = { "PSYS", NPCX_ADC_CH3,
+		       ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), 2, 0 },
 	/* Base detection */
-	[ADC_BASE_DET] = {
-		"BASE_DET",
-		NPCX_ADC_CH5,
-		ADC_MAX_VOLT,
-		ADC_READ_MAX + 1,
-		0
-	},
+	[ADC_BASE_DET] = { "BASE_DET", NPCX_ADC_CH5, ADC_MAX_VOLT,
+			   ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
@@ -217,16 +187,12 @@ const struct ln9310_config_t ln9310_config = {
 
 /* Power Path Controller */
 struct ppc_config_t ppc_chips[] = {
-	{
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	{
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
+	{ .i2c_port = I2C_PORT_TCPC0,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
+	{ .i2c_port = I2C_PORT_TCPC1,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
 };
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
@@ -257,16 +223,22 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
  * to AP. But the TCPC chip is also needed to know the HPD status; otherwise,
  * the mux misbehaves.
  */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	},
 	{
-		.usb_port = 1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	}
 };
 
@@ -297,17 +269,13 @@ enum lid_accelgyro_type {
 static enum lid_accelgyro_type lid_accelgyro_config;
 
 /* Matrix to rotate accelerometer into standard reference frame */
-const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				      { 0, FLOAT_TO_FP(-1), 0 },
+				      { 0, 0, FLOAT_TO_FP(1) } };
 
-const mat33_fp_t lid_standard_ref_icm42607 = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t lid_standard_ref_icm42607 = { { 0, FLOAT_TO_FP(1), 0 },
+					       { FLOAT_TO_FP(-1), 0, 0 },
+					       { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t icm42607_lid_accel = {
 	.name = "Lid Accel",
@@ -502,9 +470,9 @@ void board_tcpc_init(void)
 	 */
 	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
 		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
 
 void board_hibernate(void)
 {
@@ -514,8 +482,7 @@ void board_hibernate(void)
 	 * Sensors are unpowered in hibernate. Apply PD to the
 	 * interrupt lines such that they don't float.
 	 */
-	gpio_set_flags(GPIO_ACCEL_GYRO_INT_L,
-		       GPIO_INPUT | GPIO_PULL_DOWN);
+	gpio_set_flags(GPIO_ACCEL_GYRO_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
 
 	/*
 	 * Board rev 1+ has the hardware fix. Don't need the following
@@ -612,8 +579,7 @@ void board_overcurrent_event(int port, int is_overcurrented)
 
 int board_set_active_charge_port(int port)
 {
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	int i;
 
 	if (!is_real_port && port != CHARGE_PORT_NONE)
@@ -641,7 +607,6 @@ int board_set_active_charge_port(int port)
 		return EC_ERROR_INVAL;
 	}
 
-
 	CPRINTS("New charge port: p%d", port);
 
 	/*
@@ -665,24 +630,22 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	/*
 	 * Ignore lower charge ceiling on PD transition if our battery is
 	 * critical, as we may brownout.
 	 */
-	if (supplier == CHARGE_SUPPLIER_PD &&
-	    charge_ma < 1500 &&
+	if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 &&
 	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
 		CPRINTS("Using max ilim %d", max_ma);
 		charge_ma = max_ma;
 	}
 
 	charge_ma = charge_ma * 95 / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 uint16_t tcpc_get_alert_status(void)
diff --git a/board/homestar/board.h b/board/homestar/board.h
index 74de48df1d..230aa6e7d3 100644
--- a/board/homestar/board.h
+++ b/board/homestar/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,16 +10,19 @@
 
 #include "baseboard.h"
 
+/* Free up flash space */
+#undef CONFIG_CONSOLE_CMDHELP
+
 #define CONFIG_BUTTON_TRIGGERED_RECOVERY
 
 /* Internal SPI flash on NPCX7 */
-#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)  /* 512KB internal spi flash */
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */
 
 /* Switchcap */
 #define CONFIG_LN9310
 
 /* Battery */
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY  "LION"
+#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
 #define CONFIG_BATTERY_REVIVE_DISCONNECT
 #define CONFIG_BATTERY_FUEL_GAUGE
 #define CONFIG_BATTERY_VENDOR_PARAM
@@ -90,10 +93,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_DISPLIGHT = 0,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_DISPLIGHT = 0, PWM_CH_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
diff --git a/board/homestar/build.mk b/board/homestar/build.mk
index 452abeb591..363ef59a16 100644
--- a/board/homestar/build.mk
+++ b/board/homestar/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/homestar/ec.tasklist b/board/homestar/ec.tasklist
index ea2aaa97f5..8fc8115afc 100644
--- a/board/homestar/ec.tasklist
+++ b/board/homestar/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/homestar/gpio.inc b/board/homestar/gpio.inc
index 77a69a5faa..37e71977ac 100644
--- a/board/homestar/gpio.inc
+++ b/board/homestar/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/homestar/led.c b/board/homestar/led.c
index 3950ce1ec0..c314d584c3 100644
--- a/board/homestar/led.c
+++ b/board/homestar/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -36,15 +36,15 @@ enum led_color {
 	LED_RED,
 	LED_GREEN,
 	LED_AMBER,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static void led_set_color(enum led_color color)
 {
 	gpio_set_level(GPIO_EC_CHG_LED_R_C0,
-		(color == LED_RED) ? BAT_LED_ON : BAT_LED_OFF);
+		       (color == LED_RED) ? BAT_LED_ON : BAT_LED_OFF);
 	gpio_set_level(GPIO_EC_CHG_LED_G_C0,
-		(color == LED_GREEN) ? BAT_LED_ON : BAT_LED_OFF);
+		       (color == LED_GREEN) ? BAT_LED_ON : BAT_LED_OFF);
 	if (color == LED_AMBER) {
 		gpio_set_level(GPIO_EC_CHG_LED_R_C0, BAT_LED_ON);
 		gpio_set_level(GPIO_EC_CHG_LED_G_C0, BAT_LED_ON);
@@ -78,7 +78,6 @@ static void board_led_set_battery(void)
 	int color = LED_OFF;
 	int period = 0;
 	int percent = DIV_ROUND_NEAREST(charge_get_display_charge(), 10);
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
@@ -86,13 +85,13 @@ static void board_led_set_battery(void)
 	case PWR_STATE_CHARGE:
 	case PWR_STATE_CHARGE_NEAR_FULL:
 		if (chipset_in_state(CHIPSET_STATE_ON |
-					CHIPSET_STATE_ANY_SUSPEND |
-					CHIPSET_STATE_ANY_OFF)) {
+				     CHIPSET_STATE_ANY_SUSPEND |
+				     CHIPSET_STATE_ANY_OFF)) {
 			if (percent <= BATTERY_LEVEL_CRITICAL) {
 				/* battery capa <= 5%, Red */
 				color = LED_RED;
 			} else if (percent > BATTERY_LEVEL_CRITICAL &&
-					percent < BATTERY_LEVEL_NEAR_FULL) {
+				   percent < BATTERY_LEVEL_NEAR_FULL) {
 				/* 5% < battery capa < 97%, Orange */
 				color = LED_AMBER;
 			} else {
@@ -115,16 +114,16 @@ static void board_led_set_battery(void)
 			color = LED_OFF;
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE) {
-			/* Factory mode, Red 2 sec, green 2 sec */
-			period = (2 + 2) * LED_ONE_SEC;
-			battery_ticks = battery_ticks % period;
-			if (battery_ticks < 2 * LED_ONE_SEC)
-				color = LED_RED;
-			else
-				color = LED_GREEN;
-		} else
+		color = LED_RED;
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		/* Factory mode, Red 2 sec, green 2 sec */
+		period = (2 + 2) * LED_ONE_SEC;
+		battery_ticks = battery_ticks % period;
+		if (battery_ticks < 2 * LED_ONE_SEC)
 			color = LED_RED;
+		else
+			color = LED_GREEN;
 		break;
 	default:
 		/* Other states don't alter LED behavior */
@@ -147,7 +146,7 @@ void led_control(enum ec_led_id led_id, enum ec_led_state state)
 	enum led_color color;
 
 	if ((led_id != EC_LED_ID_RECOVERY_HW_REINIT_LED) &&
-		(led_id != EC_LED_ID_SYSRQ_DEBUG_LED))
+	    (led_id != EC_LED_ID_SYSRQ_DEBUG_LED))
 		return;
 
 	if (state == LED_STATE_RESET) {
diff --git a/board/homestar/usbc_config.c b/board/homestar/usbc_config.c
index aac136415d..5d30adb6e2 100644
--- a/board/homestar/usbc_config.c
+++ b/board/homestar/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,8 @@
 #include "console.h"
 #include "usb_pd.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 const struct charger_config_t chg_chips[] = {
 	{
diff --git a/board/host/battery.c b/board/host/battery.c
index 58390133e4..f3ce1766f5 100644
--- a/board/host/battery.c
+++ b/board/host/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -14,8 +14,7 @@
 
 static uint16_t mock_smart_battery[SB_MANUFACTURER_DATA + 1];
 
-int sb_i2c_xfer(int port, uint16_t addr_flags,
-		const uint8_t *out, int out_size,
+int sb_i2c_xfer(int port, uint16_t addr_flags, const uint8_t *out, int out_size,
 		uint8_t *in, int in_size, int flags)
 {
 	if (out_size == 0)
@@ -23,7 +22,7 @@ int sb_i2c_xfer(int port, uint16_t addr_flags,
 
 	if (port != I2C_PORT_BATTERY || addr_flags != BATTERY_ADDR_FLAGS)
 		return EC_ERROR_INVAL;
-	if (out[0]  >= ARRAY_SIZE(mock_smart_battery))
+	if (out[0] >= ARRAY_SIZE(mock_smart_battery))
 		return EC_ERROR_UNIMPLEMENTED;
 	if (out_size == 1) {
 		/* Read */
@@ -56,12 +55,12 @@ static const struct battery_info bat_info = {
 	 *   normal = 7.4V
 	 *   min    = 6.0V
 	 */
-	.voltage_max    = 8400,
+	.voltage_max = 8400,
 	.voltage_normal = 7400,
-	.voltage_min    = 6000,
+	.voltage_min = 6000,
 
 	/* Pre-charge current: I <= 0.01C */
-	.precharge_current  = 64, /* mA */
+	.precharge_current = 64, /* mA */
 
 	/*
 	 * Operational temperature range
@@ -70,10 +69,10 @@ static const struct battery_info bat_info = {
 	 */
 	.start_charging_min_c = 0,
 	.start_charging_max_c = 50,
-	.charging_min_c       = 0,
-	.charging_max_c       = 50,
-	.discharging_min_c    = -20,
-	.discharging_max_c    = 60,
+	.charging_min_c = 0,
+	.charging_max_c = 50,
+	.discharging_min_c = -20,
+	.discharging_max_c = 60,
 };
 
 const struct battery_info *battery_get_info(void)
diff --git a/board/host/board.c b/board/host/board.c
index e639b6bc99..baaed22b43 100644
--- a/board/host/board.c
+++ b/board/host/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -28,7 +28,7 @@
  * GPIO ports.  This maps back to 0, which is then ignored by the host GPIO mock
  * code.
  */
-#define GPIO_0  0
+#define GPIO_0 0
 
 #include "gpio_list.h"
 
@@ -48,10 +48,10 @@ test_mockable_static int mock_temp_get_val(int idx, int *temp_ptr)
 }
 
 const struct temp_sensor_t temp_sensors[] = {
-	{"CPU", TEMP_SENSOR_TYPE_CPU, mock_temp_get_val, 0},
-	{"Board", TEMP_SENSOR_TYPE_BOARD, mock_temp_get_val, 1},
-	{"Case", TEMP_SENSOR_TYPE_CASE, mock_temp_get_val, 2},
-	{"Battery", TEMP_SENSOR_TYPE_BOARD, mock_temp_get_val, 3},
+	{ "CPU", TEMP_SENSOR_TYPE_CPU, mock_temp_get_val, 0 },
+	{ "Board", TEMP_SENSOR_TYPE_BOARD, mock_temp_get_val, 1 },
+	{ "Case", TEMP_SENSOR_TYPE_CASE, mock_temp_get_val, 2 },
+	{ "Battery", TEMP_SENSOR_TYPE_BOARD, mock_temp_get_val, 3 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -67,45 +67,31 @@ test_mockable void fps_event(enum gpio_signal signal)
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
 #ifdef I2C_PORT_BATTERY
-	{
-		.name = "battery",
-		.port = I2C_PORT_BATTERY,
-		.kbps = 100,
-		.scl  = 0,
-		.sda  = 0
-	},
+	{ .name = "battery",
+	  .port = I2C_PORT_BATTERY,
+	  .kbps = 100,
+	  .scl = 0,
+	  .sda = 0 },
 #elif defined I2C_PORT_LIGHTBAR
-	{
-		.name = "lightbar",
-		.port = I2C_PORT_LIGHTBAR,
-		.kbps = 100,
-		.scl  = 0,
-		.sda  = 0
-	},
+	{ .name = "lightbar",
+	  .port = I2C_PORT_LIGHTBAR,
+	  .kbps = 100,
+	  .scl = 0,
+	  .sda = 0 },
 #elif defined I2C_PORT_HOST_TCPC
-	{
-		.name = "tcpc",
-		.port = I2C_PORT_HOST_TCPC,
-		.kbps = 100,
-		.scl  = 0,
-		.sda  = 0
-	},
+	{ .name = "tcpc",
+	  .port = I2C_PORT_HOST_TCPC,
+	  .kbps = 100,
+	  .scl = 0,
+	  .sda = 0 },
 #elif defined I2C_PORT_EEPROM
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 100,
-		.scl  = 0,
-		.sda  = 0
-	},
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 100,
+	  .scl = 0,
+	  .sda = 0 },
 #elif defined I2C_PORT_WLC
-	{
-		.name = "wlc",
-		.port = I2C_PORT_WLC,
-		.kbps = 100,
-		.scl  = 0,
-		.sda  = 0
-	},
+	{ .name = "wlc", .port = I2C_PORT_WLC, .kbps = 100, .scl = 0, .sda = 0 },
 #endif
 };
 
@@ -141,9 +127,8 @@ int board_get_entropy(void *buffer, int len)
 
 static uint8_t eeprom[CBI_IMAGE_SIZE];
 
-int eeprom_i2c_xfer(int port, uint16_t addr_flags,
-		    const uint8_t *out, int out_size,
-		    uint8_t *in, int in_size, int flags)
+int eeprom_i2c_xfer(int port, uint16_t addr_flags, const uint8_t *out,
+		    int out_size, uint8_t *in, int in_size, int flags)
 {
 	static int offset;
 
diff --git a/board/host/board.h b/board/host/board.h
index 979763af4e..165331ce4c 100644
--- a/board/host/board.h
+++ b/board/host/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -30,6 +30,8 @@
 #define CONFIG_USB_PD_CUSTOM_PDO
 #define CONFIG_USB_PD_DUAL_ROLE
 
+#define CONFIG_CMD_AP_RESET_LOG
+
 #include "gpio_signal.h"
 
 enum temp_sensor_id {
@@ -65,25 +67,25 @@ enum {
 };
 
 /* Standard-current Rp */
-#define PD_SRC_VNC           PD_SRC_DEF_VNC_MV
-#define PD_SRC_RD_THRESHOLD  PD_SRC_DEF_RD_THRESH_MV
+#define PD_SRC_VNC PD_SRC_DEF_VNC_MV
+#define PD_SRC_RD_THRESHOLD PD_SRC_DEF_RD_THRESH_MV
 
 /* delay necessary for the voltage transition on the power supply */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  20000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 20000 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 20000 /* us */
 
 /* Define typical operating power and max power */
 #define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       60000
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_VOLTAGE_MV     20000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
-#define PD_MIN_CURRENT_MA     500
-#define PD_MIN_POWER_MW       7500
+#define PD_MIN_CURRENT_MA 500
+#define PD_MIN_POWER_MW 7500
 
 /* Configuration for fake Fingerprint Sensor */
 #define CONFIG_SPI_CONTROLLER
-#define CONFIG_SPI_FP_PORT    1 /* SPI1: third master config */
+#define CONFIG_SPI_FP_PORT 1 /* SPI1: third master config */
 
 #define CONFIG_RNG
 void fps_event(enum gpio_signal signal);
@@ -92,7 +94,7 @@ void fps_event(enum gpio_signal signal);
 
 #define CONFIG_I2C
 #define CONFIG_I2C_CONTROLLER
-#define I2C_PORT_EEPROM		0
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_PORT_EEPROM 0
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/host/build.mk b/board/host/build.mk
index 17927528c2..a1fad4723a 100644
--- a/board/host/build.mk
+++ b/board/host/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
+# Copyright 2013 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/host/charger.c b/board/host/charger.c
index 4db1f44351..fddadf245d 100644
--- a/board/host/charger.c
+++ b/board/host/charger.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -12,15 +12,15 @@
 #include "util.h"
 
 static const struct charger_info mock_charger_info = {
-	.name         = "MockCharger",
-	.voltage_max  = 19200,
-	.voltage_min  = 1024,
+	.name = "MockCharger",
+	.voltage_max = 19200,
+	.voltage_min = 1024,
 	.voltage_step = 16,
-	.current_max  = 8192,
-	.current_min  = 128,
+	.current_max = 8192,
+	.current_min = 128,
 	.current_step = 128,
-	.input_current_max  = 8064,
-	.input_current_min  = 128,
+	.input_current_max = 8064,
+	.input_current_min = 128,
 	.input_current_step = 128,
 };
 
@@ -37,7 +37,6 @@ static const struct charger_info *mock_get_info(int chgnum)
 	return &mock_charger_info;
 }
 
-
 static enum ec_error_list mock_get_status(int chgnum, int *status)
 {
 	*status = CHARGER_LEVEL_2;
@@ -47,7 +46,6 @@ static enum ec_error_list mock_get_status(int chgnum, int *status)
 	return EC_SUCCESS;
 }
 
-
 static enum ec_error_list mock_set_mode(int chgnum, int mode)
 {
 	if (mode & CHARGE_FLAG_INHIBIT_CHARGE)
@@ -57,14 +55,12 @@ static enum ec_error_list mock_set_mode(int chgnum, int mode)
 	return EC_SUCCESS;
 }
 
-
 static enum ec_error_list mock_get_current(int chgnum, int *current)
 {
 	*current = mock_current;
 	return EC_SUCCESS;
 }
 
-
 static enum ec_error_list mock_set_current(int chgnum, int current)
 {
 	const struct charger_info *info = mock_get_info(chgnum);
@@ -86,7 +82,6 @@ static enum ec_error_list mock_get_voltage(int chgnum, int *voltage)
 	return EC_SUCCESS;
 }
 
-
 static enum ec_error_list mock_set_voltage(int chgnum, int voltage)
 {
 	mock_voltage = voltage;
@@ -94,27 +89,23 @@ static enum ec_error_list mock_set_voltage(int chgnum, int voltage)
 	return EC_SUCCESS;
 }
 
-
 static enum ec_error_list mock_get_option(int chgnum, int *option)
 {
 	*option = mock_option;
 	return EC_SUCCESS;
 }
 
-
 static enum ec_error_list mock_set_option(int chgnum, int option)
 {
 	mock_option = option;
 	return EC_SUCCESS;
 }
 
-
 static enum ec_error_list mock_manufacturer_id(int chgnum, int *id)
 {
 	return EC_SUCCESS;
 }
 
-
 static enum ec_error_list mock_device_id(int chgnum, int *id)
 {
 	return EC_SUCCESS;
@@ -127,7 +118,6 @@ static enum ec_error_list mock_get_input_current_limit(int chgnum,
 	return EC_SUCCESS;
 }
 
-
 static enum ec_error_list mock_set_input_current_limit(int chgnum, int current)
 {
 	const struct charger_info *info = mock_get_info(chgnum);
@@ -144,7 +134,6 @@ static enum ec_error_list mock_set_input_current_limit(int chgnum, int current)
 	return EC_SUCCESS;
 }
 
-
 static enum ec_error_list mock_post_init(int chgnum)
 {
 	mock_current = mock_input_current = CONFIG_CHARGER_INPUT_CURRENT;
diff --git a/board/host/chipset.c b/board/host/chipset.c
index 0a7385fc84..47ad097c53 100644
--- a/board/host/chipset.c
+++ b/board/host/chipset.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/host/ec.tasklist b/board/host/ec.tasklist
index c056c51e8a..0195800932 100644
--- a/board/host/ec.tasklist
+++ b/board/host/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/host/fan.c b/board/host/fan.c
index 1e1001f1cd..de335afa06 100644
--- a/board/host/fan.c
+++ b/board/host/fan.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,7 +22,10 @@ const struct fan_rpm fan_rpm_0 = {
 };
 
 const struct fan_t fans[CONFIG_FANS] = {
-	{ .conf = &fan_conf_0, .rpm = &fan_rpm_0, },
+	{
+		.conf = &fan_conf_0,
+		.rpm = &fan_rpm_0,
+	},
 };
 
 static int mock_enabled;
diff --git a/board/host/gpio.inc b/board/host/gpio.inc
index ce69385259..ab30915881 100644
--- a/board/host/gpio.inc
+++ b/board/host/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
+ * Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/host/usb_pd_config.c b/board/host/usb_pd_config.c
index 878e747342..10ed9536fa 100644
--- a/board/host/usb_pd_config.c
+++ b/board/host/usb_pd_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/host/usb_pd_config.h b/board/host/usb_pd_config.h
index fb12b2ce7d..0fff2af019 100644
--- a/board/host/usb_pd_config.h
+++ b/board/host/usb_pd_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/host/usb_pd_pdo.c b/board/host/usb_pd_pdo.c
index a84b03f75f..a352148ecb 100644
--- a/board/host/usb_pd_pdo.c
+++ b/board/host/usb_pd_pdo.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,14 +10,14 @@
 #define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP)
 
 const uint32_t pd_src_pdo[] = {
-		PDO_FIXED(5000,   900, PDO_FIXED_FLAGS),
-		PDO_FIXED(12000,  3000, PDO_FIXED_FLAGS),
+	PDO_FIXED(5000, 900, PDO_FIXED_FLAGS),
+	PDO_FIXED(12000, 3000, PDO_FIXED_FLAGS),
 };
 const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
 
 const uint32_t pd_snk_pdo[] = {
-		PDO_FIXED(5000, 500, PDO_FIXED_FLAGS),
-		PDO_BATT(4750, 21000, 15000),
-		PDO_VAR(4750, 21000, 3000),
+	PDO_FIXED(5000, 500, PDO_FIXED_FLAGS),
+	PDO_BATT(4750, 21000, 15000),
+	PDO_VAR(4750, 21000, 3000),
 };
 const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
diff --git a/board/host/usb_pd_pdo.h b/board/host/usb_pd_pdo.h
index 64d73c7a15..4f1a64dced 100644
--- a/board/host/usb_pd_pdo.h
+++ b/board/host/usb_pd_pdo.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/host/usb_pd_policy.c b/board/host/usb_pd_policy.c
index b90db882ce..dc965ca192 100644
--- a/board/host/usb_pd_policy.c
+++ b/board/host/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,8 +9,8 @@
 #include "usb_pd_pdo.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 test_mockable int pd_set_power_supply_ready(int port)
 {
@@ -41,22 +41,18 @@ __override int pd_check_power_swap(int port)
 	return 1;
 }
 
-__override int pd_check_data_swap(int port,
-				  enum pd_data_role data_role)
+__override int pd_check_data_swap(int port, enum pd_data_role data_role)
 {
 	/* Always allow data swap */
 	return 1;
 }
 
-__override void pd_check_pr_role(int port,
-				 enum pd_power_role pr_role,
+__override void pd_check_pr_role(int port, enum pd_power_role pr_role,
 				 int flags)
 {
 }
 
-__override void pd_check_dr_role(int port,
-				 enum pd_data_role dr_role,
-				 int flags)
+__override void pd_check_dr_role(int port, enum pd_data_role dr_role, int flags)
 {
 }
 
diff --git a/board/hyperdebug/board.c b/board/hyperdebug/board.c
new file mode 100644
index 0000000000..37e41f66a9
--- /dev/null
+++ b/board/hyperdebug/board.c
@@ -0,0 +1,329 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* HyperDebug board configuration */
+
+#include "common.h"
+#include "console.h"
+#include "ec_version.h"
+#include "gpio.h"
+#include "i2c.h"
+#include "queue_policies.h"
+#include "registers.h"
+#include "spi.h"
+#include "task.h"
+#include "timer.h"
+#include "usart-stm32l5.h"
+#include "usb_hw.h"
+#include "usb_spi.h"
+#include "usb-stream.h"
+#include "gpio_list.h"
+
+void board_config_pre_init(void)
+{
+	/* enable SYSCFG clock */
+	STM32_RCC_APB2ENR |= STM32_RCC_SYSCFGEN;
+}
+
+/******************************************************************************
+ * Forward UARTs as a USB serial interface.
+ */
+
+#define USB_STREAM_RX_SIZE 16
+#define USB_STREAM_TX_SIZE 16
+
+/******************************************************************************
+ * Forward USART2 as a simple USB serial interface.
+ */
+
+static struct usart_config const usart2;
+struct usb_stream_config const usart2_usb;
+
+static struct queue const usart2_to_usb =
+	QUEUE_DIRECT(64, uint8_t, usart2.producer, usart2_usb.consumer);
+static struct queue const usb_to_usart2 =
+	QUEUE_DIRECT(64, uint8_t, usart2_usb.producer, usart2.consumer);
+
+static struct usart_config const usart2 =
+	USART_CONFIG(usart2_hw, usart_rx_interrupt, usart_tx_interrupt, 115200,
+		     0, usart2_to_usb, usb_to_usart2);
+
+USB_STREAM_CONFIG(usart2_usb, USB_IFACE_USART2_STREAM,
+		  USB_STR_USART2_STREAM_NAME, USB_EP_USART2_STREAM,
+		  USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE, usb_to_usart2,
+		  usart2_to_usb)
+
+/******************************************************************************
+ * Forward USART3 as a simple USB serial interface.
+ */
+
+static struct usart_config const usart3;
+struct usb_stream_config const usart3_usb;
+
+static struct queue const usart3_to_usb =
+	QUEUE_DIRECT(64, uint8_t, usart3.producer, usart3_usb.consumer);
+static struct queue const usb_to_usart3 =
+	QUEUE_DIRECT(64, uint8_t, usart3_usb.producer, usart3.consumer);
+
+static struct usart_config const usart3 =
+	USART_CONFIG(usart3_hw, usart_rx_interrupt, usart_tx_interrupt, 115200,
+		     0, usart3_to_usb, usb_to_usart3);
+
+USB_STREAM_CONFIG(usart3_usb, USB_IFACE_USART3_STREAM,
+		  USB_STR_USART3_STREAM_NAME, USB_EP_USART3_STREAM,
+		  USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE, usb_to_usart3,
+		  usart3_to_usb)
+
+/******************************************************************************
+ * Forward USART4 as a simple USB serial interface.
+ */
+
+static struct usart_config const usart4;
+struct usb_stream_config const usart4_usb;
+
+static struct queue const usart4_to_usb =
+	QUEUE_DIRECT(64, uint8_t, usart4.producer, usart4_usb.consumer);
+static struct queue const usb_to_usart4 =
+	QUEUE_DIRECT(64, uint8_t, usart4_usb.producer, usart4.consumer);
+
+static struct usart_config const usart4 =
+	USART_CONFIG(usart4_hw, usart_rx_interrupt, usart_tx_interrupt, 115200,
+		     0, usart4_to_usb, usb_to_usart4);
+
+USB_STREAM_CONFIG(usart4_usb, USB_IFACE_USART4_STREAM,
+		  USB_STR_USART4_STREAM_NAME, USB_EP_USART4_STREAM,
+		  USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE, usb_to_usart4,
+		  usart4_to_usb)
+
+/******************************************************************************
+ * Forward USART5 as a simple USB serial interface.
+ */
+
+static struct usart_config const usart5;
+struct usb_stream_config const usart5_usb;
+
+static struct queue const usart5_to_usb =
+	QUEUE_DIRECT(64, uint8_t, usart5.producer, usart5_usb.consumer);
+static struct queue const usb_to_usart5 =
+	QUEUE_DIRECT(64, uint8_t, usart5_usb.producer, usart5.consumer);
+
+static struct usart_config const usart5 =
+	USART_CONFIG(usart5_hw, usart_rx_interrupt, usart_tx_interrupt, 115200,
+		     0, usart5_to_usb, usb_to_usart5);
+
+USB_STREAM_CONFIG(usart5_usb, USB_IFACE_USART5_STREAM,
+		  USB_STR_USART5_STREAM_NAME, USB_EP_USART5_STREAM,
+		  USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE, usb_to_usart5,
+		  usart5_to_usb)
+
+/******************************************************************************
+ * Support SPI bridging over USB, this requires usb_spi_board_enable and
+ * usb_spi_board_disable to be defined to enable and disable the SPI bridge.
+ */
+
+/* SPI devices */
+const struct spi_device_t spi_devices[] = {
+	{ 1 /* SPI2 */, 7, GPIO_SPI2_CS },
+};
+const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
+
+void usb_spi_board_enable(struct usb_spi_config const *config)
+{
+	/* Configure SPI GPIOs */
+	gpio_config_module(MODULE_SPI, 1);
+	gpio_config_module(MODULE_SPI_FLASH, 1);
+
+	/* Set all SPI pins to high speed */
+	STM32_GPIO_OSPEEDR(GPIO_F) |= 0xFFF00000;
+	STM32_GPIO_OSPEEDR(GPIO_D) |= 0x000000C3;
+	STM32_GPIO_OSPEEDR(GPIO_C) |= 0x000000F0;
+
+	/* Enable clocks to SPI2 module */
+	STM32_RCC_APB1ENR1 |= STM32_RCC_APB1ENR1_SPI2EN;
+
+	/* Reset SPI2 */
+	STM32_RCC_APB1RSTR1 |= STM32_RCC_APB1RSTR1_SPI2RST;
+	STM32_RCC_APB1RSTR1 &= ~STM32_RCC_APB1RSTR1_SPI2RST;
+
+	spi_enable(&spi_devices[0], 1);
+}
+
+void usb_spi_board_disable(struct usb_spi_config const *config)
+{
+	spi_enable(&spi_devices[0], 0);
+
+	/* Disable clocks to SPI2 module */
+	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
+
+	/* Release SPI GPIOs */
+	gpio_config_module(MODULE_SPI_FLASH, 0);
+}
+
+USB_SPI_CONFIG(usb_spi, USB_IFACE_SPI, USB_EP_SPI, 0);
+
+/******************************************************************************
+ * Support I2C bridging over USB.
+ */
+
+/* I2C ports */
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "controller",
+	  .port = I2C_PORT_CONTROLLER,
+	  .kbps = 100,
+	  .scl = GPIO_TPM_I2C1_HOST_SCL,
+	  .sda = GPIO_TPM_I2C1_HOST_SDA },
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+int usb_i2c_board_is_enabled(void)
+{
+	return 1;
+}
+
+/******************************************************************************
+ * Define the strings used in our USB descriptors.
+ */
+
+const void *const usb_strings[] = {
+	[USB_STR_DESC] = usb_string_desc,
+	[USB_STR_VENDOR] = USB_STRING_DESC("Google LLC"),
+	[USB_STR_PRODUCT] = USB_STRING_DESC("HyperDebug"),
+	[USB_STR_SERIALNO] = 0,
+	[USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32),
+	[USB_STR_CONSOLE_NAME] = USB_STRING_DESC("HyperDebug Shell"),
+	[USB_STR_SPI_NAME] = USB_STRING_DESC("SPI"),
+	[USB_STR_I2C_NAME] = USB_STRING_DESC("I2C"),
+	[USB_STR_USART2_STREAM_NAME] = USB_STRING_DESC("UART2"),
+	[USB_STR_USART3_STREAM_NAME] = USB_STRING_DESC("UART3"),
+	[USB_STR_USART4_STREAM_NAME] = USB_STRING_DESC("UART4"),
+	[USB_STR_USART5_STREAM_NAME] = USB_STRING_DESC("UART5"),
+};
+
+BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
+
+/******************************************************************************
+ * Initialize board.
+ */
+
+static void board_init(void)
+{
+	STM32_GPIO_BSRR(STM32_GPIOE_BASE) |= 0x0000FF00;
+
+	/* We know VDDIO2 is present, enable the GPIO circuit. */
+	STM32_PWR_CR2 |= STM32_PWR_CR2_IOSV;
+
+	/* USB to serial queues */
+	queue_init(&usart2_to_usb);
+	queue_init(&usb_to_usart2);
+	queue_init(&usart3_to_usb);
+	queue_init(&usb_to_usart3);
+	queue_init(&usart4_to_usb);
+	queue_init(&usb_to_usart4);
+	queue_init(&usart5_to_usb);
+	queue_init(&usb_to_usart5);
+
+	STM32_GPIO_BSRR(STM32_GPIOE_BASE) |= 0x0F000000;
+	/* UART init */
+	usart_init(&usart2);
+	usart_init(&usart3);
+	usart_init(&usart4);
+	usart_init(&usart5);
+
+	/* Structured endpoints */
+	usb_spi_enable(&usb_spi, 1);
+	STM32_GPIO_BSRR(STM32_GPIOE_BASE) |= 0xF0000000;
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+/**
+ * Find a GPIO signal by name.
+ *
+ * This is copied from gpio.c unfortunately, as it is static over there.
+ *
+ * @param name		Signal name to find
+ *
+ * @return the signal index, or GPIO_COUNT if no match.
+ */
+static enum gpio_signal find_signal_by_name(const char *name)
+{
+	int i;
+
+	if (!name || !*name)
+		return GPIO_COUNT;
+
+	for (i = 0; i < GPIO_COUNT; i++)
+		if (gpio_is_implemented(i) &&
+		    !strcasecmp(name, gpio_get_name(i)))
+			return i;
+
+	return GPIO_COUNT;
+}
+
+/*
+ * Set the mode of a GPIO pin: input/opendrain/pushpull.
+ */
+static int command_gpio_mode(int argc, const char **argv)
+{
+	int gpio;
+	int flags;
+
+	if (argc < 3)
+		return EC_ERROR_PARAM_COUNT;
+
+	gpio = find_signal_by_name(argv[1]);
+	if (gpio == GPIO_COUNT)
+		return EC_ERROR_PARAM1;
+	flags = gpio_get_flags(gpio);
+
+	flags = flags & ~(GPIO_INPUT | GPIO_OUTPUT | GPIO_OPEN_DRAIN);
+	if (strcasecmp(argv[2], "input") == 0)
+		flags |= GPIO_INPUT;
+	else if (strcasecmp(argv[2], "opendrain") == 0)
+		flags |= GPIO_OUTPUT | GPIO_OPEN_DRAIN;
+	else if (strcasecmp(argv[2], "pushpull") == 0)
+		flags |= GPIO_OUTPUT;
+	else
+		return EC_ERROR_PARAM2;
+
+	/* Update GPIO flags. */
+	gpio_set_flags(gpio, flags);
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND_FLAGS(gpiomode, command_gpio_mode,
+			      "name <input | opendrain | pushpull>",
+			      "Set a GPIO mode", CMD_FLAG_RESTRICTED);
+
+/*
+ * Set the weak pulling of a GPIO pin: up/down/none.
+ */
+static int command_gpio_pull_mode(int argc, const char **argv)
+{
+	int gpio;
+	int flags;
+
+	if (argc < 3)
+		return EC_ERROR_PARAM_COUNT;
+
+	gpio = find_signal_by_name(argv[1]);
+	if (gpio == GPIO_COUNT)
+		return EC_ERROR_PARAM1;
+	flags = gpio_get_flags(gpio);
+
+	flags = flags & ~(GPIO_PULL_UP | GPIO_PULL_DOWN);
+	if (strcasecmp(argv[2], "none") == 0)
+		;
+	else if (strcasecmp(argv[2], "up") == 0)
+		flags |= GPIO_PULL_UP;
+	else if (strcasecmp(argv[2], "down") == 0)
+		flags |= GPIO_PULL_DOWN;
+	else
+		return EC_ERROR_PARAM2;
+
+	/* Update GPIO flags. */
+	gpio_set_flags(gpio, flags);
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND_FLAGS(gpiopullmode, command_gpio_pull_mode,
+			      "name <none | up | down>",
+			      "Set a GPIO weak pull mode", CMD_FLAG_RESTRICTED);
diff --git a/board/hyperdebug/board.h b/board/hyperdebug/board.h
new file mode 100644
index 0000000000..9d15311784
--- /dev/null
+++ b/board/hyperdebug/board.h
@@ -0,0 +1,153 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* HyperDebug configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#define CONFIG_LTO
+
+/* 48 MHz SYSCLK clock frequency */
+#define CPU_CLOCK 48000000
+
+#define CONFIG_BOARD_PRE_INIT
+
+#define CONFIG_ROM_BASE 0x0
+#define CONFIG_ROM_SIZE (CONFIG_RAM_BASE - CONFIG_ROM_BASE)
+
+/* Enable USB forwarding on UART 2, 3, 4, and 5. */
+#define CONFIG_STREAM_USART
+#undef CONFIG_STREAM_USART1
+#define CONFIG_STREAM_USART2
+#define CONFIG_STREAM_USART3
+#define CONFIG_STREAM_USART4
+#define CONFIG_STREAM_USART5
+#undef CONFIG_STREAM_USART9
+#define CONFIG_STREAM_USB
+#define CONFIG_CMD_USART_INFO
+
+/* The UART console is on LPUART (UART9), connected to st-link debugger. */
+#undef CONFIG_UART_CONSOLE
+#define CONFIG_UART_CONSOLE 9
+#undef CONFIG_UART_TX_DMA
+#undef CONFIG_UART_RX_DMA
+
+/* Optional features */
+#define CONFIG_STM_HWTIMER32
+#define CONFIG_HW_CRC
+#undef CONFIG_PVD
+/*
+ * See 'Programmable voltage detector characteristics' in the
+ * STM32F072x8 Datasheet.  PVD Threshold 1 corresponds to a falling
+ * voltage threshold of min:2.09V, max:2.27V.
+ */
+#define PVD_THRESHOLD (1)
+
+/* USB Configuration */
+
+#define CONFIG_USB
+#define CONFIG_USB_PID 0x520e
+#define CONFIG_USB_CONSOLE
+
+/*
+ * Enabling USB updating would exceed the number of USB endpoints
+ * supported by the hardware.  We will have to rely on the built-in
+ * DFU support of STM32 chips.
+ */
+#undef CONFIG_USB_UPDATE
+
+#undef CONFIG_USB_MAXPOWER_MA
+#define CONFIG_USB_MAXPOWER_MA 100
+
+#define CONFIG_USB_SERIALNO
+#define DEFAULT_SERIALNO "Uninitialized"
+
+/* USB interface indexes (use define rather than enum to expand them) */
+#define USB_IFACE_CONSOLE 0
+#define USB_IFACE_SPI 1
+#define USB_IFACE_I2C 2
+#define USB_IFACE_USART2_STREAM 3
+#define USB_IFACE_USART3_STREAM 4
+#define USB_IFACE_USART4_STREAM 5
+#define USB_IFACE_USART5_STREAM 6
+#define USB_IFACE_COUNT 7
+
+/* USB endpoint indexes (use define rather than enum to expand them) */
+#define USB_EP_CONTROL 0
+#define USB_EP_CONSOLE 1
+#define USB_EP_SPI 2
+#define USB_EP_I2C 3
+#define USB_EP_USART2_STREAM 4
+#define USB_EP_USART3_STREAM 5
+#define USB_EP_USART4_STREAM 6
+#define USB_EP_USART5_STREAM 7
+#define USB_EP_COUNT 8
+
+/*
+ * Do not enable the common EC command gpioset for recasting of GPIO
+ * type. Instead, board specific commands are used for implementing
+ * the OpenTitan tool requirements.
+ */
+#undef CONFIG_CMD_GPIO_EXTENDED
+#define CONFIG_GPIO_GET_EXTENDED
+
+/* Enable control of SPI over USB */
+#define CONFIG_USB_SPI
+#define CONFIG_USB_SPI_BUFFER_SIZE 2048
+#define CONFIG_SPI_CONTROLLER
+
+/* Enable control of I2C over USB */
+#define CONFIG_USB_I2C
+#define CONFIG_I2C
+#define CONFIG_I2C_CONTROLLER
+#define I2C_PORT_CONTROLLER 0
+#define CONFIG_STM32_SPI1_CONTROLLER
+
+/* See i2c_ite_flash_support.c for more information about these values */
+/*#define CONFIG_ITE_FLASH_SUPPORT */
+/*#define CONFIG_I2C_XFER_LARGE_TRANSFER */
+#undef CONFIG_USB_I2C_MAX_WRITE_COUNT
+#undef CONFIG_USB_I2C_MAX_READ_COUNT
+#define CONFIG_USB_I2C_MAX_WRITE_COUNT ((1 << 9) - 4)
+#define CONFIG_USB_I2C_MAX_READ_COUNT ((1 << 9) - 6)
+
+/* This is not actually an EC so disable some features. */
+#undef CONFIG_WATCHDOG_HELP
+#undef CONFIG_LID_SWITCH
+
+/*
+ * Allow dangerous commands all the time, since we don't have a write protect
+ * switch.
+ */
+#define CONFIG_SYSTEM_UNLOCKED
+
+#ifndef __ASSEMBLER__
+
+/* Timer selection */
+#define TIM_CLOCK32 2
+
+#include "gpio_signal.h"
+
+/* USB string indexes */
+enum usb_strings {
+	USB_STR_DESC = 0,
+	USB_STR_VENDOR,
+	USB_STR_PRODUCT,
+	USB_STR_SERIALNO,
+	USB_STR_VERSION,
+	USB_STR_CONSOLE_NAME,
+	USB_STR_SPI_NAME,
+	USB_STR_I2C_NAME,
+	USB_STR_USART2_STREAM_NAME,
+	USB_STR_USART3_STREAM_NAME,
+	USB_STR_USART4_STREAM_NAME,
+	USB_STR_USART5_STREAM_NAME,
+
+	USB_STR_COUNT
+};
+
+#endif /* !__ASSEMBLER__ */
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/hyperdebug/build.mk b/board/hyperdebug/build.mk
new file mode 100644
index 0000000000..d65418f259
--- /dev/null
+++ b/board/hyperdebug/build.mk
@@ -0,0 +1,13 @@
+# -*- makefile -*-
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+
+# the IC is STmicro STM32F302R8
+CHIP:=stm32
+CHIP_FAMILY:=stm32l5
+CHIP_VARIANT:=stm32l552xe
+
+board-y=board.o
diff --git a/board/hyperdebug/ec.tasklist b/board/hyperdebug/ec.tasklist
new file mode 100644
index 0000000000..ed894a7f87
--- /dev/null
+++ b/board/hyperdebug/ec.tasklist
@@ -0,0 +1,11 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS,   hook_task,    NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE)
diff --git a/board/hyperdebug/gpio.inc b/board/hyperdebug/gpio.inc
new file mode 100644
index 0000000000..5dc0cebc1b
--- /dev/null
+++ b/board/hyperdebug/gpio.inc
@@ -0,0 +1,186 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * List of all GPIO pins available for Host computer to manipulate.
+ * The are named based on their location on the two 70-pin DIL
+ * connectors on either side of the HyperDebug board.  Pins with
+ * special functions are commented out, and declared with relevant
+ * symbolic name further below.
+ */
+
+GPIO(CN7_1,			PIN(C, 6),  GPIO_INPUT)
+/*GPIO(CN7_2,			PIN(B, 8),  GPIO_INPUT) I2C1 */
+GPIO(CN7_3,			PIN(D, 11), GPIO_INPUT)
+/*GPIO(CN7_4,			PIN(B, 9),  GPIO_INPUT) I2C1 */
+GPIO(CN7_5,			PIN(B, 13), GPIO_INPUT)
+/* CN7_6 is VREFP */
+GPIO(CN7_7,			PIN(D, 12), GPIO_INPUT)
+/* CN7_8 is GND */
+/*GPIO(CN7_9,			PIN(A, 4),  GPIO_INPUT) CC1 */
+/*GPIO(CN7_10,			PIN(A, 5),  GPIO_INPUT) CC2 */
+GPIO(CN7_11,			PIN(B, 4),  GPIO_INPUT)
+GPIO(CN7_12,			PIN(A, 6),  GPIO_INPUT)
+/*GPIO(CN7_13,			PIN(B, 5),  GPIO_INPUT) Nucleo USB-C */
+GPIO(CN7_14,			PIN(A, 7),  GPIO_INPUT)
+GPIO(CN7_15,			PIN(B, 3),  GPIO_INPUT)
+GPIO(CN7_16,			PIN(D, 14), GPIO_INPUT)
+/*GPIO(CN7_17,			PIN(A, 4),  GPIO_INPUT)*/
+GPIO(CN7_18,			PIN(D, 15), GPIO_INPUT)
+/*GPIO(CN7_19,			PIN(B, 4),  GPIO_INPUT)*/
+GPIO(CN7_20,			PIN(F, 12), GPIO_INPUT)
+
+/* CN8_1 is NC */
+GPIO(CN8_2,			PIN(C, 8),  GPIO_INPUT)
+/* CN8_3 is IOREF */
+GPIO(CN8_4,			PIN(C, 9),  GPIO_INPUT)
+/* CN8_5 is NRST */
+/*GPIO(CN8_6,			PIN(C, 10), GPIO_INPUT) UART4 */
+/* CN8_7 is 3V3 */
+/*GPIO(CN8_8,			PIN(C, 11), GPIO_INPUT) UART4 */
+/* CN8_9 is 5V */
+/*GPIO(CN8_10,			PIN(C, 12), GPIO_INPUT) UART5 */
+/* CN8_11 is GND */
+/*GPIO(CN8_12,			PIN(D, 2),  GPIO_INPUT) UART5 */
+/* CN8_13 is GND */
+GPIO(CN8_14,			PIN(F, 3),  GPIO_INPUT)
+/* CN8_15 is VIN */
+GPIO(CN8_16,			PIN(F, 5),  GPIO_INPUT)
+
+GPIO(CN9_1,			PIN(A, 3),  GPIO_INPUT)
+GPIO(CN9_2,			PIN(D, 7),  GPIO_INPUT)
+GPIO(CN9_3,			PIN(A, 2),  GPIO_INPUT)
+/*GPIO(CN9_4,			PIN(D, 6),  GPIO_INPUT) UART2 */
+GPIO(CN9_5,			PIN(C, 3),  GPIO_INPUT)
+/*GPIO(CN9_6,			PIN(D, 5),  GPIO_INPUT) UART2 */
+GPIO(CN9_7,			PIN(B, 0),  GPIO_INPUT)
+/*GPIO(CN9_8,			PIN(D, 4),  GPIO_INPUT) SPI2 */
+/*GPIO(CN9_9,			PIN(C, 1),  GPIO_INPUT) I2C3 */
+/*GPIO(CN9_10,			PIN(D, 3),  GPIO_INPUT) SPI2 */
+/*GPIO(CN9_11,			PIN(C, 0),  GPIO_INPUT) I2C3 */
+/* CN9_12 is GND */
+GPIO(CN9_13,			PIN(B, 2),  GPIO_INPUT)
+GPIO(CN9_14,			PIN(E, 2),  GPIO_INPUT)
+GPIO(CN9_15,			PIN(B, 6),  GPIO_INPUT)
+GPIO(CN9_16,			PIN(E, 4),  GPIO_INPUT)
+GPIO(CN9_17,			PIN(F, 2),  GPIO_INPUT)
+GPIO(CN9_18,			PIN(E, 5),  GPIO_INPUT)
+/*GPIO(CN9_19,			PIN(F, 1),  GPIO_INPUT) I2C2 */
+GPIO(CN9_20,			PIN(E, 6),  GPIO_INPUT)
+/*GPIO(CN9_21,			PIN(F, 0),  GPIO_INPUT) I2C2 */
+GPIO(CN9_22,			PIN(E, 3),  GPIO_INPUT)
+/* CN9_23 is GND */
+GPIO(CN9_24,			PIN(F, 8),  GPIO_INPUT)
+/*GPIO(CN9_25,			PIN(D, 0),  GPIO_INPUT) SPI2 */
+GPIO(CN9_26,			PIN(F, 7),  GPIO_INPUT)
+/*GPIO(CN9_27,			PIN(D, 1),  GPIO_INPUT) SPI2 */
+GPIO(CN9_28,			PIN(F, 9),  GPIO_INPUT)
+GPIO(CN9_29,			PIN(G, 0),  GPIO_INPUT)
+GPIO(CN9_30,			PIN(G, 1),  GPIO_INPUT)
+
+/* CN10_1 is AVDD */
+GPIO(CN10_2,			PIN(F, 13), GPIO_INPUT)
+/* CN10_3 is AGND */
+GPIO(CN10_4,			PIN(E, 9),  GPIO_INPUT)
+/* CN10_5 is GND */
+/*GPIO(CN10_6,			PIN(E, 11), GPIO_INPUT) QSPI */
+GPIO(CN10_7,			PIN(B, 1),  GPIO_INPUT)
+GPIO(CN10_8,			PIN(F, 14), GPIO_INPUT)
+/*GPIO(CN10_9,			PIN(C, 2),  GPIO_INPUT) Nucleo USB VBUS sense */
+/*GPIO(CN10_10,			PIN(E, 13), GPIO_INPUT) QSPI */
+GPIO(CN10_11,			PIN(A, 1),  GPIO_INPUT)
+GPIO(CN10_12,			PIN(F, 15), GPIO_INPUT)
+/*GPIO(CN10_13,			PIN(A, 2),  GPIO_INPUT)*/
+/*GPIO(CN10_14,			PIN(D, 8),  GPIO_INPUT) UART3 */
+GPIO(CN10_15,			PIN(B, 10), GPIO_INPUT)
+/*GPIO(CN10_16,			PIN(D, 9),  GPIO_INPUT) UART3 */
+/* CN10_17 is GND */
+GPIO(CN10_18,			PIN(E, 8),  GPIO_INPUT)
+/*GPIO(CN10_19,			PIN(E, 15), GPIO_INPUT) QSPI */
+GPIO(CN10_20,			PIN(E, 7),  GPIO_INPUT)
+/*GPIO(CN10_21,			PIN(B, 0),  GPIO_INPUT)*/
+/* CN10_22 is GND */
+/*GPIO(CN10_23,			PIN(E, 12), GPIO_INPUT) QSPI */
+/*GPIO(CN10_24,			PIN(E, 10), GPIO_INPUT) QSPI */
+/*GPIO(CN10_25,			PIN(E, 14), GPIO_INPUT) QSPI */
+/*GPIO(CN10_26,			PIN(E, 12), GPIO_INPUT) QSPI */
+/* CN10_27 is GND */
+/*GPIO(CN10_28,			PIN(E, 14), GPIO_INPUT) QSPI */
+GPIO(CN10_29,			PIN(A, 0),  GPIO_INPUT)
+/*GPIO(CN10_30,			PIN(E, 15), GPIO_INPUT) QSPI */
+GPIO(CN10_31,			PIN(A, 8),  GPIO_INPUT)
+/*GPIO(CN10_32,			PIN(B, 10), GPIO_INPUT)*/
+GPIO(CN10_33,			PIN(E, 0),  GPIO_INPUT)
+GPIO(CN10_34,			PIN(B, 11), GPIO_INPUT)
+
+
+/* QSPI controller */
+GPIO(QSPI_DEV_CLK,		PIN(E, 10), GPIO_INPUT)
+GPIO(QSPI_DEV_CS_L,		PIN(E, 11), GPIO_INPUT)
+GPIO(QSPI_DEV_D0,		PIN(E, 12), GPIO_INPUT)
+GPIO(QSPI_DEV_D1,		PIN(E, 13), GPIO_INPUT)
+GPIO(QSPI_DEV_D2,		PIN(E, 14), GPIO_INPUT)
+GPIO(QSPI_DEV_D3,		PIN(E, 15), GPIO_INPUT)
+
+/* I2C pins should be configured as inputs until I2C module is    */
+/* initialized. This will avoid driving the lines unintentionally.*/
+GPIO(TPM_I2C1_HOST_SCL,		PIN(B, 8),  GPIO_OUTPUT | GPIO_OPEN_DRAIN)
+GPIO(TPM_I2C1_HOST_SDA,		PIN(B, 9),  GPIO_OUTPUT | GPIO_OPEN_DRAIN)
+GPIO(INA_I2C2_DEV_SCL,		PIN(F, 1),  GPIO_OUTPUT | GPIO_OPEN_DRAIN)
+GPIO(INA_I2C2_DEV_SDA,		PIN(F, 0),  GPIO_OUTPUT | GPIO_OPEN_DRAIN)
+GPIO(AUX_I2C3_DEV_SCL,		PIN(C, 0),  GPIO_OUTPUT | GPIO_OPEN_DRAIN)
+GPIO(AUX_I2C3_DEV_SDA,		PIN(C, 1),  GPIO_OUTPUT | GPIO_OPEN_DRAIN)
+
+/* These pins are used for USART and are set to alternate mode below */
+GPIO(USART2_OT_TX,		PIN(D, 5),  GPIO_INPUT)
+GPIO(USART2_OT_RX,		PIN(D, 6),  GPIO_INPUT)
+GPIO(USART4_AP_TX,		PIN(C, 10), GPIO_INPUT)
+GPIO(USART4_AP_RX,		PIN(C, 11), GPIO_INPUT)
+GPIO(USART5_FPMCU_TX,		PIN(C, 12), GPIO_INPUT)
+GPIO(USART5_FPMCU_RX,		PIN(D, 2),  GPIO_INPUT)
+GPIO(USART3_EC_TX,		PIN(D, 8),  GPIO_INPUT)
+GPIO(USART3_EC_RX,		PIN(D, 9),  GPIO_INPUT)
+GPIO(LPUART1_HYPER_RX,		PIN(G, 7),  GPIO_INPUT)
+GPIO(LPUART1_HYPER_TX,		PIN(G, 8),  GPIO_INPUT)
+
+/* Additional SPI controller, only available on CN11/CN12 */
+GPIO(SPI2_CS,			PIN(D, 0),  GPIO_OUT_HIGH)
+GPIO(SPI2_SCK,			PIN(D, 1),  GPIO_ALTERNATE)
+GPIO(SPI2_CIDO,			PIN(D, 3),  GPIO_ALTERNATE)
+GPIO(SPI2_CODI,			PIN(D, 4),  GPIO_ALTERNATE)
+
+/* USB pins */
+GPIO(USB_FS_DM,			PIN(A, 11), GPIO_ALTERNATE)
+GPIO(USB_FS_DP,			PIN(A, 12), GPIO_ALTERNATE)
+GPIO(CC1,			PIN(A, 4),  GPIO_ANALOG)
+GPIO(CC2,			PIN(A, 5),  GPIO_ANALOG)
+
+/* Signals for hardware on the Nucleo board itself */
+GPIO(NUCLEO_LED1,		PIN(C, 7),  GPIO_OUT_HIGH) /* Green */
+GPIO(NUCLEO_LED2,		PIN(B, 7),  GPIO_OUT_LOW) /* Blue */
+GPIO(NUCLEO_LED3,		PIN(A, 9),  GPIO_OUT_LOW) /* Red */
+
+/* Unimplemented signals since we are not an EC */
+UNIMPLEMENTED(ENTERING_RW)
+UNIMPLEMENTED(WP_L)
+
+
+ALTERNATE(PIN_MASK(A, 0x1800), 10, MODULE_USB, 0) /* USB: PA11/12 */
+
+ALTERNATE(PIN_MASK(D, 0x0060), 7, MODULE_UART, 0) /* USART2: PD5/PD6 - OT UART */
+ALTERNATE(PIN_MASK(C, 0x0C00), 8, MODULE_UART, 0) /* USART4: PC10/PC11 - AP UART */
+ALTERNATE(PIN_MASK(D, 0x0300), 7, MODULE_UART, 0) /* USART3: PD8/PD9 - EC UART */
+ALTERNATE(PIN_MASK(C, 0x1000), 8, MODULE_UART, 0) /* USART5: PC12 - FP MCU UART */
+ALTERNATE(PIN_MASK(D, 0x0004), 8, MODULE_UART, 0) /* USART5: PD2 - FP MCU UART */
+ALTERNATE(PIN_MASK(G, 0x0180), 8, MODULE_UART, 0) /* LPUART1: PG7/PG8 - HyperDebug console */
+
+ALTERNATE(PIN_MASK(F, 0x0003), 4, MODULE_I2C, GPIO_OPEN_DRAIN) /* I2C2: PF0/PF1 */
+ALTERNATE(PIN_MASK(B, 0x0300), 4, MODULE_I2C, GPIO_OPEN_DRAIN) /* I2C1: PB8/PB9 */
+ALTERNATE(PIN_MASK(C, 0x0003), 4, MODULE_I2C, GPIO_OPEN_DRAIN) /* I2C3: PC0/PC1 */
+/*ALTERNATE(PIN_MASK(E, 0xFC00), 10, MODULE_SPI_FLASH, 0) / * QSPI: PE10-15 */
+/*ALTERNATE(PIN_MASK(D, 0x0001), 5, MODULE_SPI, 0) / * SPI2: PD0 CS */
+ALTERNATE(PIN_MASK(D, 0x001A), 5, MODULE_SPI, 0) /* SPI2: PD1/PD3/PD4 SCK/CIDO/DOCI */
diff --git a/board/icarus/battery.c b/board/icarus/battery.c
index 6f6b49899a..5e1671f5f3 100644
--- a/board/icarus/battery.c
+++ b/board/icarus/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/icarus/board.c b/board/icarus/board.c
index 4dcb55d472..be464e3a77 100644
--- a/board/icarus/board.c
+++ b/board/icarus/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,6 +26,7 @@
 #include "i2c.h"
 #include "keyboard_scan.h"
 #include "lid_switch.h"
+#include "panic.h"
 #include "power.h"
 #include "power_button.h"
 #include "registers.h"
@@ -40,8 +41,8 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 #include "gpio_list.h"
 
@@ -51,18 +52,21 @@
  * The connector has 24 pins total, and there is no pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-	{-1, -1}, {GPIO_KSO_H, 4}, {GPIO_KSO_H, 0}, {GPIO_KSO_H, 1},
-	{GPIO_KSO_H, 3}, {GPIO_KSO_H, 2}, {-1, -1}, {-1, -1},
-	{GPIO_KSO_L, 5}, {GPIO_KSO_L, 6}, {-1, -1}, {GPIO_KSO_L, 3},
-	{GPIO_KSO_L, 2}, {GPIO_KSI, 0}, {GPIO_KSO_L, 1}, {GPIO_KSO_L, 4},
-	{GPIO_KSI, 3}, {GPIO_KSI, 2}, {GPIO_KSO_L, 0}, {GPIO_KSI, 5},
-	{GPIO_KSI, 4}, {GPIO_KSO_L, 7}, {GPIO_KSI, 6}, {GPIO_KSI, 7},
-	{GPIO_KSI, 1}, {-1, -1}, {GPIO_KSO_H, 5}, {-1, -1},
-	{GPIO_KSO_H, 6}, {-1, -1}, {-1, -1},
+	{ -1, -1 },	   { GPIO_KSO_H, 4 }, { GPIO_KSO_H, 0 },
+	{ GPIO_KSO_H, 1 }, { GPIO_KSO_H, 3 }, { GPIO_KSO_H, 2 },
+	{ -1, -1 },	   { -1, -1 },	      { GPIO_KSO_L, 5 },
+	{ GPIO_KSO_L, 6 }, { -1, -1 },	      { GPIO_KSO_L, 3 },
+	{ GPIO_KSO_L, 2 }, { GPIO_KSI, 0 },   { GPIO_KSO_L, 1 },
+	{ GPIO_KSO_L, 4 }, { GPIO_KSI, 3 },   { GPIO_KSI, 2 },
+	{ GPIO_KSO_L, 0 }, { GPIO_KSI, 5 },   { GPIO_KSI, 4 },
+	{ GPIO_KSO_L, 7 }, { GPIO_KSI, 6 },   { GPIO_KSI, 7 },
+	{ GPIO_KSI, 1 },   { -1, -1 },	      { GPIO_KSO_H, 5 },
+	{ -1, -1 },	   { GPIO_KSO_H, 6 }, { -1, -1 },
+	{ -1, -1 },
 };
 
 const int keyboard_factory_scan_pins_used =
-		ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 
 /* Wake-up pins for hibernate */
 const enum gpio_signal hibernate_wake_pins[] = {
@@ -75,39 +79,33 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 /******************************************************************************/
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] = {"BOARD_ID", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0,
-				CHIP_ADC_CH1},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0,
-				CHIP_ADC_CH2},
-	[ADC_VBUS] = {"VBUS", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0,
-				CHIP_ADC_CH0},
+	[ADC_BOARD_ID] = { "BOARD_ID", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0,
+			   CHIP_ADC_CH1 },
+	[ADC_EC_SKU_ID] = { "EC_SKU_ID", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0,
+			    CHIP_ADC_CH2 },
+	[ADC_VBUS] = { "VBUS", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0,
+		       CHIP_ADC_CH0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /******************************************************************************/
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "typec",
-		.port = IT83XX_I2C_CH_C,
-		.kbps = 400,
-		.scl  = GPIO_I2C_C_SCL,
-		.sda  = GPIO_I2C_C_SDA
-	},
-	{
-		.name = "other",
-		.port = IT83XX_I2C_CH_B,
-		.kbps = 100,
-		.scl  = GPIO_I2C_B_SCL,
-		.sda  = GPIO_I2C_B_SDA
-	},
-	{
-		.name = "battery",
-		.port = IT83XX_I2C_CH_A,
-		.kbps = 100,
-		.scl  = GPIO_I2C_A_SCL,
-		.sda  = GPIO_I2C_A_SDA
-	},
+	{ .name = "typec",
+	  .port = IT83XX_I2C_CH_C,
+	  .kbps = 400,
+	  .scl = GPIO_I2C_C_SCL,
+	  .sda = GPIO_I2C_C_SDA },
+	{ .name = "other",
+	  .port = IT83XX_I2C_CH_B,
+	  .kbps = 100,
+	  .scl = GPIO_I2C_B_SCL,
+	  .sda = GPIO_I2C_B_SDA },
+	{ .name = "battery",
+	  .port = IT83XX_I2C_CH_A,
+	  .kbps = 100,
+	  .scl = GPIO_I2C_A_SCL,
+	  .sda = GPIO_I2C_A_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -115,8 +113,8 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
 /* power signal list.  Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
+	{ GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" },
+	{ GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" },
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
@@ -139,8 +137,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-static void board_hpd_status(const struct usb_mux *me,
-			     mux_state_t mux_state,
+static void board_hpd_status(const struct usb_mux *me, mux_state_t mux_state,
 			     bool *ack_required)
 {
 	/* This driver does not use host command ACKs */
@@ -153,13 +150,16 @@ static void board_hpd_status(const struct usb_mux *me,
 	host_set_single_event(EC_HOST_EVENT_USB_MUX);
 }
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+				.hpd_update = &board_hpd_status,
+			},
 	},
 };
 
@@ -204,12 +204,12 @@ int board_set_active_charge_port(int charge_port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-			       CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 int board_discharge_on_ac(int enable)
diff --git a/board/icarus/board.h b/board/icarus/board.h
index 0fe63af10c..98b6da3fd5 100644
--- a/board/icarus/board.h
+++ b/board/icarus/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -48,14 +48,14 @@
 #undef CONFIG_ACCEL_FIFO_THRES
 
 /* I2C ports */
-#define I2C_PORT_BC12               IT83XX_I2C_CH_C
-#define I2C_PORT_TCPC0              IT83XX_I2C_CH_C
-#define I2C_PORT_USB_MUX            IT83XX_I2C_CH_C
-#define I2C_PORT_CHARGER            IT83XX_I2C_CH_A
-#define I2C_PORT_SENSORS            IT83XX_I2C_CH_B
-#define I2C_PORT_ACCEL              I2C_PORT_SENSORS
-#define I2C_PORT_BATTERY            IT83XX_I2C_CH_A
-#define I2C_PORT_VIRTUAL_BATTERY    I2C_PORT_BATTERY
+#define I2C_PORT_BC12 IT83XX_I2C_CH_C
+#define I2C_PORT_TCPC0 IT83XX_I2C_CH_C
+#define I2C_PORT_USB_MUX IT83XX_I2C_CH_C
+#define I2C_PORT_CHARGER IT83XX_I2C_CH_A
+#define I2C_PORT_SENSORS IT83XX_I2C_CH_B
+#define I2C_PORT_ACCEL I2C_PORT_SENSORS
+#define I2C_PORT_BATTERY IT83XX_I2C_CH_A
+#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
 
 #define CONFIG_KEYBOARD_PROTOCOL_MKBP
 #define CONFIG_MKBP_EVENT
@@ -114,7 +114,7 @@ enum battery_type {
 
 /* support factory keyboard test */
 #define CONFIG_KEYBOARD_FACTORY_TEST
-#define GPIO_KBD_KSO2		GPIO_EC_KSO_02_INV
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
 
 #ifdef SECTION_IS_RO
 /* Interrupt handler for AP jump to BL */
diff --git a/board/icarus/build.mk b/board/icarus/build.mk
index 9ca7933e2a..a1ca27116e 100644
--- a/board/icarus/build.mk
+++ b/board/icarus/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/icarus/ec.tasklist b/board/icarus/ec.tasklist
index e8ad538bc2..9b6e29ea07 100644
--- a/board/icarus/ec.tasklist
+++ b/board/icarus/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/icarus/gpio.inc b/board/icarus/gpio.inc
index a3a097c17b..1ec4c9cc41 100644
--- a/board/icarus/gpio.inc
+++ b/board/icarus/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/icarus/led.c b/board/icarus/led.c
index 076199b2ed..bbbad7ceb8 100644
--- a/board/icarus/led.c
+++ b/board/icarus/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -14,22 +14,27 @@
 __override const int led_charge_lvl_1 = 5;
 __override const int led_charge_lvl_2 = 95;
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 __override void led_set_color_battery(enum ec_led_colors color)
 {
diff --git a/board/it83xx_evb/board.c b/board/it83xx_evb/board.c
index a18b8b3b70..37ee2f48ed 100644
--- a/board/it83xx_evb/board.c
+++ b/board/it83xx_evb/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/it83xx_evb/board.h b/board/it83xx_evb/board.h
index 754474174c..d3eec7f09e 100644
--- a/board/it83xx_evb/board.h
+++ b/board/it83xx_evb/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/it83xx_evb/build.mk b/board/it83xx_evb/build.mk
index e4c8c01b89..9a78775633 100644
--- a/board/it83xx_evb/build.mk
+++ b/board/it83xx_evb/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
+# Copyright 2013 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/it83xx_evb/ec.tasklist b/board/it83xx_evb/ec.tasklist
index 3ca78d55db..e5d2d246df 100644
--- a/board/it83xx_evb/ec.tasklist
+++ b/board/it83xx_evb/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/it83xx_evb/gpio.inc b/board/it83xx_evb/gpio.inc
index 505f91ad64..e3014814d7 100644
--- a/board/it83xx_evb/gpio.inc
+++ b/board/it83xx_evb/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
+ * Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/it8xxx2_evb/board.c b/board/it8xxx2_evb/board.c
index 0daa3d48cd..404a575e42 100644
--- a/board/it8xxx2_evb/board.c
+++ b/board/it8xxx2_evb/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/it8xxx2_evb/board.h b/board/it8xxx2_evb/board.h
index 1369e43496..766f0fab4f 100644
--- a/board/it8xxx2_evb/board.h
+++ b/board/it8xxx2_evb/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/it8xxx2_evb/build.mk b/board/it8xxx2_evb/build.mk
index b54a2fcbb6..6fefa1fc6c 100644
--- a/board/it8xxx2_evb/build.mk
+++ b/board/it8xxx2_evb/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/it8xxx2_evb/ec.tasklist b/board/it8xxx2_evb/ec.tasklist
index ff184489e3..a25dab19eb 100644
--- a/board/it8xxx2_evb/ec.tasklist
+++ b/board/it8xxx2_evb/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/it8xxx2_evb/gpio.inc b/board/it8xxx2_evb/gpio.inc
index e5e7d5e942..32d9de4a05 100644
--- a/board/it8xxx2_evb/gpio.inc
+++ b/board/it8xxx2_evb/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/it8xxx2_pdevb/board.c b/board/it8xxx2_pdevb/board.c
index 9161b2ce2e..2bcc58a58c 100644
--- a/board/it8xxx2_pdevb/board.c
+++ b/board/it8xxx2_pdevb/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,12 +14,12 @@
 #include "timer.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
-#define USB_PD_PORT_ITE_0   0
-#define USB_PD_PORT_ITE_1   1
-#define USB_PD_PORT_ITE_2   2
-#define RESISTIVE_DIVIDER   11
+#define USB_PD_PORT_ITE_0 0
+#define USB_PD_PORT_ITE_1 1
+#define USB_PD_PORT_ITE_2 2
+#define RESISTIVE_DIVIDER 11
 
 int board_get_battery_soc(void)
 {
@@ -83,7 +83,7 @@ void board_pd_vbus_ctrl(int port, int enabled)
 		gpio_set_level(GPIO_USBPD_PORTA_VBUS_OUTPUT, enabled);
 		if (!enabled) {
 			gpio_set_level(GPIO_USBPD_PORTA_VBUS_DROP, 1);
-			udelay(10*MSEC); /* 10ms is a try and error value */
+			udelay(10 * MSEC); /* 10ms is a try and error value */
 		}
 		gpio_set_level(GPIO_USBPD_PORTA_VBUS_DROP, 0);
 	} else if (port == USBPD_PORT_B) {
@@ -91,7 +91,7 @@ void board_pd_vbus_ctrl(int port, int enabled)
 		gpio_set_level(GPIO_USBPD_PORTB_VBUS_OUTPUT, enabled);
 		if (!enabled) {
 			gpio_set_level(GPIO_USBPD_PORTB_VBUS_DROP, 1);
-			udelay(10*MSEC); /* 10ms is a try and error value */
+			udelay(10 * MSEC); /* 10ms is a try and error value */
 		}
 		gpio_set_level(GPIO_USBPD_PORTB_VBUS_DROP, 0);
 	} else if (port == USBPD_PORT_C) {
@@ -99,13 +99,13 @@ void board_pd_vbus_ctrl(int port, int enabled)
 		gpio_set_level(GPIO_USBPD_PORTC_VBUS_OUTPUT, enabled);
 		if (!enabled) {
 			gpio_set_level(GPIO_USBPD_PORTC_VBUS_DROP, 1);
-			udelay(10*MSEC); /* 10ms is a try and error value */
+			udelay(10 * MSEC); /* 10ms is a try and error value */
 		}
 		gpio_set_level(GPIO_USBPD_PORTC_VBUS_DROP, 0);
 	}
 
 	if (enabled)
-		udelay(10*MSEC); /* 10ms is a try and error value */
+		udelay(10 * MSEC); /* 10ms is a try and error value */
 }
 
 void pd_set_input_current_limit(int port, uint32_t max_ma,
@@ -120,8 +120,7 @@ void pd_set_input_current_limit(int port, uint32_t max_ma,
  * so use the same frequency and prescaler register setting is required if
  * number of pwm channel greater than three.
  */
-const struct pwm_t pwm_channels[] = {
-};
+const struct pwm_t pwm_channels[] = {};
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
diff --git a/board/it8xxx2_pdevb/board.h b/board/it8xxx2_pdevb/board.h
index d23898f3aa..e617a015bd 100644
--- a/board/it8xxx2_pdevb/board.h
+++ b/board/it8xxx2_pdevb/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -42,12 +42,12 @@
 #define CONFIG_USB_PD_CUSTOM_PDO
 #define CONFIG_USB_PD_3A_PORTS 0
 #define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_PORT_MAX_COUNT    2
-#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT   2
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 2
 #define CONFIG_USB_PD_TCPMV2
 #define CONFIG_USB_DRP_ACC_TRYSRC
 #define CONFIG_USB_PD_REV30
-#define CONFIG_USB_PID 0x1234            /* Invalid PID for development board */
+#define CONFIG_USB_PID 0x1234 /* Invalid PID for development board */
 #define CONFIG_USB_PD_DEBUG_LEVEL 2
 #define CONFIG_USB_PD_TCPM_ITE_ON_CHIP
 #define CONFIG_USB_PD_TRY_SRC
@@ -82,16 +82,16 @@ enum adc_channel {
 
 /* Define typical operating power and max power */
 #define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       60000
-#define PD_MAX_CURRENT_MA     3000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
 /* Try to negotiate to 20V since i2c noise problems should be fixed. */
-#define PD_MAX_VOLTAGE_MV     20000
+#define PD_MAX_VOLTAGE_MV 20000
 /* TODO: determine the following board specific type-C power constants */
 /*
  * delay to turn on the power supply max is ~16ms.
  * delay to turn off the power supply max is about ~180ms.
  */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* delay to turn on/off vconn */
diff --git a/board/it8xxx2_pdevb/build.mk b/board/it8xxx2_pdevb/build.mk
index b54a2fcbb6..6fefa1fc6c 100644
--- a/board/it8xxx2_pdevb/build.mk
+++ b/board/it8xxx2_pdevb/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/it8xxx2_pdevb/ec.tasklist b/board/it8xxx2_pdevb/ec.tasklist
index 41fc733526..ef1195fe7e 100644
--- a/board/it8xxx2_pdevb/ec.tasklist
+++ b/board/it8xxx2_pdevb/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/it8xxx2_pdevb/gpio.inc b/board/it8xxx2_pdevb/gpio.inc
index afc83a82c3..a03509507b 100644
--- a/board/it8xxx2_pdevb/gpio.inc
+++ b/board/it8xxx2_pdevb/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/jacuzzi/battery.c b/board/jacuzzi/battery.c
index 443bf1e98a..1caeb7e3c5 100644
--- a/board/jacuzzi/battery.c
+++ b/board/jacuzzi/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -120,7 +120,8 @@ const struct board_batt_params board_battery_info[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
 
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_PANASONIC_AC16L5J_KT00205009;
+const enum battery_type DEFAULT_BATTERY_TYPE =
+	BATTERY_PANASONIC_AC16L5J_KT00205009;
 
 enum battery_present battery_hw_present(void)
 {
diff --git a/board/jacuzzi/board.c b/board/jacuzzi/board.c
index 861c139fdf..129b75f8e2 100644
--- a/board/jacuzzi/board.c
+++ b/board/jacuzzi/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -32,6 +32,7 @@
 #include "it8801.h"
 #include "keyboard_scan.h"
 #include "lid_switch.h"
+#include "panic.h"
 #include "power.h"
 #include "power_button.h"
 #include "registers.h"
@@ -46,8 +47,8 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
@@ -59,50 +60,42 @@ static void tcpc_alert_event(enum gpio_signal signal)
 /******************************************************************************/
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] =  {"BOARD_ID",  3300, 4096, 0, STM32_AIN(10)},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)},
+	[ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(10) },
+	[ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /******************************************************************************/
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "typec",
-		.port = 0,
-		.kbps = 400,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	},
+	{ .name = "typec",
+	  .port = 0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
 #ifdef BOARD_JACUZZI
-	{
-		.name = "other",
-		.port = 1,
-		.kbps = 100,
-		.scl  = GPIO_I2C2_SCL,
-		.sda  = GPIO_I2C2_SDA
-	},
+	{ .name = "other",
+	  .port = 1,
+	  .kbps = 100,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
 #else /* Juniper */
-	{
-		.name = "other",
-		.port = 1,
-		.kbps = 400,
-		.scl  = GPIO_I2C2_SCL,
-		.sda  = GPIO_I2C2_SDA
-	},
+	{ .name = "other",
+	  .port = 1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
 #endif
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
 const struct i2c_port_t i2c_bitbang_ports[] = {
-	{
-		.name = "battery",
-		.port = 2,
-		.kbps = 100,
-		.scl  = GPIO_I2C3_SCL,
-		.sda  = GPIO_I2C3_SDA,
-		.drv = &bitbang_drv
-	},
+	{ .name = "battery",
+	  .port = 2,
+	  .kbps = 100,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA,
+	  .drv = &bitbang_drv },
 };
 const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
 
@@ -110,8 +103,8 @@ const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
 
 /* power signal list.  Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
+	{ GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" },
+	{ GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" },
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
@@ -167,8 +160,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-static void board_hpd_status(const struct usb_mux *me,
-			     mux_state_t mux_state,
+static void board_hpd_status(const struct usb_mux *me, mux_state_t mux_state,
 			     bool *ack_required)
 {
 	/* This driver does not use host command ACKs */
@@ -181,13 +173,16 @@ static void board_hpd_status(const struct usb_mux *me,
 	host_set_single_event(EC_HOST_EVENT_USB_MUX);
 }
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+				.hpd_update = &board_hpd_status,
+			},
 	},
 };
 
@@ -249,12 +244,12 @@ int board_set_active_charge_port(int charge_port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-			       CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 int board_discharge_on_ac(int enable)
@@ -311,8 +306,7 @@ static void board_spi_enable(void)
 	/* Pin mux spi peripheral toward the sensor. */
 	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
 }
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP,
-	     board_spi_enable,
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_spi_enable,
 	     MOTION_SENSE_HOOK_PRIO - 1);
 
 static void board_spi_disable(void)
@@ -329,8 +323,7 @@ static void board_spi_disable(void)
 	spi_enable(&spi_devices[0], 0);
 	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
 }
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN,
-	     board_spi_disable,
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_spi_disable,
 	     MOTION_SENSE_HOOK_PRIO + 1);
 #endif /* !VARIANT_KUKUI_NO_SENSORS */
 
@@ -368,14 +361,12 @@ static void board_init(void)
 #ifndef VARIANT_KUKUI_NO_SENSORS
 		motion_sensor_count = 0;
 		gpio_disable_interrupt(GPIO_ACCEL_INT_ODL);
-		gpio_set_flags(GPIO_ACCEL_INT_ODL,
-			       GPIO_INPUT | GPIO_PULL_DOWN);
+		gpio_set_flags(GPIO_ACCEL_INT_ODL, GPIO_INPUT | GPIO_PULL_DOWN);
 #endif /* !VARIANT_KUKUI_NO_SENSORS */
 		/* Disable tablet mode. */
 		tablet_set_mode(0, TABLET_TRIGGER_LID);
 		gmr_tablet_switch_disable();
-		gpio_set_flags(GPIO_TABLET_MODE_L,
-			       GPIO_INPUT | GPIO_PULL_UP);
+		gpio_set_flags(GPIO_TABLET_MODE_L, GPIO_INPUT | GPIO_PULL_UP);
 	}
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
@@ -387,17 +378,13 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Rotation matrixes */
-static const mat33_fp_t base_bmi160_ref = {
-	{FLOAT_TO_FP(1), 0, 0},
-	{0, FLOAT_TO_FP(1), 0},
-	{0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t base_bmi160_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					    { 0, FLOAT_TO_FP(1), 0 },
+					    { 0, 0, FLOAT_TO_FP(1) } };
 
-static const mat33_fp_t base_icm426xx_ref = {
-	{0, FLOAT_TO_FP(-1), 0},
-	{FLOAT_TO_FP(1), 0, 0},
-	{0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t base_icm426xx_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+					      { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
 
 /* sensor private data */
 static struct kionix_accel_data g_kx022_data;
@@ -558,10 +545,11 @@ static void board_detect_motionsensor(void)
 		motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
 		motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
 	}
-	base_accelgyro_config = (val == ICM426XX_CHIP_ICM40608)
-		 ? BASE_GYRO_ICM426XX : BASE_GYRO_BMI160;
-	CPRINTS("Base Accelgyro: %s", (val == ICM426XX_CHIP_ICM40608)
-		 ? "ICM40608" : "BMI160");
+	base_accelgyro_config = (val == ICM426XX_CHIP_ICM40608) ?
+					BASE_GYRO_ICM426XX :
+					BASE_GYRO_BMI160;
+	CPRINTS("Base Accelgyro: %s",
+		(val == ICM426XX_CHIP_ICM40608) ? "ICM40608" : "BMI160");
 }
 DECLARE_HOOK(HOOK_INIT, board_detect_motionsensor, HOOK_PRIO_DEFAULT);
 
diff --git a/board/jacuzzi/board.h b/board/jacuzzi/board.h
index da66312411..0fd5f6496d 100644
--- a/board/jacuzzi/board.h
+++ b/board/jacuzzi/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -58,7 +58,7 @@
 /* Motion Sensors */
 #ifndef VARIANT_KUKUI_NO_SENSORS
 #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-#define CONFIG_ACCEL_KX022	/* Lid accel */
+#define CONFIG_ACCEL_KX022 /* Lid accel */
 #define CONFIG_ACCELGYRO_BMI160 /* Base accel */
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
@@ -71,7 +71,6 @@
 #define CONFIG_ALS
 #define CONFIG_CMD_ACCEL_INFO
 
-
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_UPDATE
 #define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
@@ -84,24 +83,24 @@
 #endif /* VARIANT_KUKUI_NO_SENSORS */
 
 /* I2C ports */
-#define I2C_PORT_BC12               0
-#define I2C_PORT_TCPC0              0
-#define I2C_PORT_USB_MUX            0
-#define I2C_PORT_CHARGER            board_get_charger_i2c()
-#define I2C_PORT_SENSORS            1
-#define I2C_PORT_KB_DISCRETE        1
-#define I2C_PORT_VIRTUAL_BATTERY    I2C_PORT_BATTERY
+#define I2C_PORT_BC12 0
+#define I2C_PORT_TCPC0 0
+#define I2C_PORT_USB_MUX 0
+#define I2C_PORT_CHARGER board_get_charger_i2c()
+#define I2C_PORT_SENSORS 1
+#define I2C_PORT_KB_DISCRETE 1
+#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
 #ifdef BOARD_JACUZZI
-#define I2C_PORT_BATTERY            1
+#define I2C_PORT_BATTERY 1
 #else /* Juniper */
-#define I2C_PORT_BATTERY            2
+#define I2C_PORT_BATTERY 2
 #endif
 
 /* IT8801 I2C address */
-#define KB_DISCRETE_I2C_ADDR_FLAGS  IT8801_I2C_ADDR1
+#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1
 
 /* Enable Accel over SPI */
-#define CONFIG_SPI_ACCEL_PORT    0  /* The first SPI controller port (SPI2) */
+#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */
 
 #define CONFIG_KEYBOARD_PROTOCOL_MKBP
 #define CONFIG_MKBP_EVENT
diff --git a/board/jacuzzi/build.mk b/board/jacuzzi/build.mk
index e449fce9fc..80c34a4e46 100644
--- a/board/jacuzzi/build.mk
+++ b/board/jacuzzi/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/jacuzzi/ec.tasklist b/board/jacuzzi/ec.tasklist
index b695d05a71..dd3b853c27 100644
--- a/board/jacuzzi/ec.tasklist
+++ b/board/jacuzzi/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/jacuzzi/gpio.inc b/board/jacuzzi/gpio.inc
index 60288e7195..b534ad2ea1 100644
--- a/board/jacuzzi/gpio.inc
+++ b/board/jacuzzi/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/jacuzzi/led.c b/board/jacuzzi/led.c
index e76b73bc9a..f648e879d0 100644
--- a/board/jacuzzi/led.c
+++ b/board/jacuzzi/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -15,22 +15,27 @@
 __override const int led_charge_lvl_1 = 5;
 __override const int led_charge_lvl_2 = 95;
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 __override void led_set_color_battery(enum ec_led_colors color)
 {
diff --git a/board/jinlon/battery.c b/board/jinlon/battery.c
index 12c2e38d84..9cf4c15458 100644
--- a/board/jinlon/battery.c
+++ b/board/jinlon/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/jinlon/board.c b/board/jinlon/board.c
index 58e7e1b427..717c8db09c 100644
--- a/board/jinlon/board.c
+++ b/board/jinlon/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -44,8 +44,8 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void check_reboot_deferred(void);
 DECLARE_DEFERRED(check_reboot_deferred);
@@ -114,18 +114,19 @@ static void bc12_interrupt(enum gpio_signal signal)
 
 /******************************************************************************/
 /* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
+const struct spi_device_t spi_devices[] = {};
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
 /******************************************************************************/
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT]   = { .channel = 3, .flags = 0, .freq = 100 },
-	[PWM_CH_FAN] = {.channel = 5, .flags = PWM_CONFIG_OPEN_DRAIN,
-			.freq = 25000},
-	[PWM_CH_FAN2] = {.channel = 6, .flags = PWM_CONFIG_OPEN_DRAIN,
-			.freq = 25000},
+	[PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 100 },
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
+	[PWM_CH_FAN2] = { .channel = 6,
+			  .flags = PWM_CONFIG_OPEN_DRAIN,
+			  .freq = 25000 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
@@ -150,16 +151,20 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_TCPC_0] = {
-		.usb_port = USB_PD_PORT_TCPC_0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_0,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 	},
 	[USB_PD_PORT_TCPC_1] = {
-		.usb_port = USB_PD_PORT_TCPC_1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 	}
 };
 
@@ -188,17 +193,13 @@ static struct bmi_drv_data_t g_bmi160_data;
 static struct accelgyro_saved_data_t g_bma255_data;
 
 /* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+					      { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
 
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
@@ -278,14 +279,14 @@ unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
 
 const struct fan_conf fan_conf_1 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_1,	/* Use MFT id to control fan */
+	.ch = MFT_CH_1, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN2,
 };
@@ -311,49 +312,48 @@ const struct fan_t fans[FAN_CH_COUNT] = {
 /******************************************************************************/
 /* MFT channels. These are logically separate from pwm_channels. */
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN},
-	[MFT_CH_1] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN2},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN },
+	[MFT_CH_1] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN2 },
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		"TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_2] = {
-		"TEMP_5V_REG", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_3] = {
-		"TEMP_CPU", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_1] = { "TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_2] = { "TEMP_5V_REG", NPCX_ADC_CH1, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_3] = { "TEMP_CPU", NPCX_ADC_CH2, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "5v Reg",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "CPU",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_3},
-	[TEMP_SENSOR_4] = {.name = "IR Sensor",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = oti502_get_val,
-				 .idx = OTI502_IDX_OBJECT},
+	[TEMP_SENSOR_1] = { .name = "Charger",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "5v Reg",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "CPU",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
+	[TEMP_SENSOR_4] = { .name = "IR Sensor",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = oti502_get_val,
+			    .idx = OTI502_IDX_OBJECT },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
-
 /* Dratini Temperature sensors */
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_A \
-	{ \
+#define THERMAL_A                \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = 0, \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
@@ -368,8 +368,8 @@ __maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_B \
-	{ \
+#define THERMAL_B                \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = 0, \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
@@ -438,8 +438,8 @@ static const struct ec_response_keybd_config keybd2 = {
 	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
 };
 
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	/*
 	 * Future boards should use fw_config instead of SKU ID
@@ -487,15 +487,15 @@ void board_overcurrent_event(int port, int is_overcurrented)
  * The connector has 24 pins total, and there is no pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-		{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-		{0, 7}, {1, 4}, {1, 3}, {1, 6}, {1, 7},
-		{3, 1}, {2, 0}, {1, 5}, {2, 6}, {2, 7},
-		{2, 1}, {2, 4}, {2, 5}, {1, 2}, {2, 3},
-		{2, 2}, {3, 0}, {-1, -1}, {-1, -1}, {-1, -1},
+	{ -1, -1 }, { 0, 5 }, { 1, 1 },	  { 1, 0 },   { 0, 6 },
+	{ 0, 7 },   { 1, 4 }, { 1, 3 },	  { 1, 6 },   { 1, 7 },
+	{ 3, 1 },   { 2, 0 }, { 1, 5 },	  { 2, 6 },   { 2, 7 },
+	{ 2, 1 },   { 2, 4 }, { 2, 5 },	  { 1, 2 },   { 2, 3 },
+	{ 2, 2 },   { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 },
 };
 
 const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 #endif
 
 bool board_is_convertible(void)
@@ -503,10 +503,9 @@ bool board_is_convertible(void)
 	const uint8_t sku = get_board_sku();
 
 	return (sku == 255) || (sku == 1) || (sku == 2) || (sku == 21) ||
-		(sku == 22);
+	       (sku == 22);
 }
 
-
 void all_sys_pgood_check_reboot(void)
 {
 	hook_call_deferred(&check_reboot_deferred_data, 3000 * MSEC);
@@ -517,7 +516,7 @@ __override void board_chipset_forced_shutdown(void)
 	hook_call_deferred(&check_reboot_deferred_data, -1);
 }
 DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_forced_shutdown,
-	HOOK_PRIO_DEFAULT);
+	     HOOK_PRIO_DEFAULT);
 
 static void check_reboot_deferred(void)
 {
diff --git a/board/jinlon/board.h b/board/jinlon/board.h
index d4ecf9bbd6..350376dd63 100644
--- a/board/jinlon/board.h
+++ b/board/jinlon/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -32,10 +32,10 @@
  * Jinlon's battery takes several seconds to come back out of its disconnect
  * state (~4 seconds, but give it 6 for margin).
  */
-#undef  CONFIG_POWER_BUTTON_INIT_TIMEOUT
+#undef CONFIG_POWER_BUTTON_INIT_TIMEOUT
 #define CONFIG_POWER_BUTTON_INIT_TIMEOUT 6
 
-#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV	5000
+#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV 5000
 
 /* Sensors */
 /* BMI160 Base accel/gyro */
@@ -117,16 +117,16 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_AC_PRESENT		GPIO_ACOK_OD
-#define GPIO_PG_EC_RSMRST_ODL	GPIO_PG_EC_RSMRST_L
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_TEMP_SENSOR_POWER	GPIO_EN_A_RAILS
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L
+#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
 
 #ifndef __ASSEMBLER__
 
@@ -134,9 +134,9 @@
 #include "registers.h"
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_1,	/* ADC0 */
-	ADC_TEMP_SENSOR_2,	/* ADC1 */
-	ADC_TEMP_SENSOR_3,	/* ADC2 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
+	ADC_TEMP_SENSOR_3, /* ADC2 */
 	ADC_CH_COUNT
 };
 
@@ -147,12 +147,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_FAN,
-	PWM_CH_FAN2,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_FAN, PWM_CH_FAN2, PWM_CH_COUNT };
 
 enum fan_channel {
 	FAN_CH_0 = 0,
diff --git a/board/jinlon/build.mk b/board/jinlon/build.mk
index 2d6118ea70..4e42a0616e 100644
--- a/board/jinlon/build.mk
+++ b/board/jinlon/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/jinlon/ec.tasklist b/board/jinlon/ec.tasklist
index 4a1024a091..829be2b7c8 100644
--- a/board/jinlon/ec.tasklist
+++ b/board/jinlon/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/jinlon/gpio.inc b/board/jinlon/gpio.inc
index f57a331436..91002dacc1 100644
--- a/board/jinlon/gpio.inc
+++ b/board/jinlon/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,10 +17,10 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(PG_EC_RSMRST_L,       PIN(E, 2), GPIO_INT_BOTH, intel_x86_rsmrst_signal_interrupt)
diff --git a/board/jinlon/led.c b/board/jinlon/led.c
index 4cef6dc3ae..8ab3d7631f 100644
--- a/board/jinlon/led.c
+++ b/board/jinlon/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -25,11 +25,9 @@
 #define LED_ON_TICKS 5
 #define POWER_LED_ON_TICKS 2
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_LEFT_LED,
-	EC_LED_ID_RIGHT_LED,
-	EC_LED_ID_POWER_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_LEFT_LED,
+					     EC_LED_ID_RIGHT_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -37,7 +35,7 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static void led_set_color_battery(int port, enum led_color color)
@@ -147,7 +145,6 @@ static void set_active_port_color(enum led_color color)
 static void led_set_battery(void)
 {
 	static int battery_ticks;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
@@ -159,9 +156,12 @@ static void led_set_battery(void)
 	case PWR_STATE_DISCHARGE:
 		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
 			if (charge_get_percent() < 10)
-				led_set_color_battery(0, (battery_ticks %
-					LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-					LED_WHITE : LED_OFF);
+				led_set_color_battery(
+					0,
+					(battery_ticks % LED_TICKS_PER_CYCLE <
+					 LED_ON_TICKS) ?
+						LED_WHITE :
+						LED_OFF);
 			else
 				led_set_color_battery(0, LED_OFF);
 		}
@@ -170,19 +170,20 @@ static void led_set_battery(void)
 			led_set_color_battery(1, LED_OFF);
 		break;
 	case PWR_STATE_ERROR:
-		set_active_port_color((battery_ticks & 0x2) ?
-				LED_WHITE : LED_OFF);
+		set_active_port_color((battery_ticks & 0x2) ? LED_WHITE :
+							      LED_OFF);
 		break;
 	case PWR_STATE_CHARGE_NEAR_FULL:
 		set_active_port_color(LED_WHITE);
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			set_active_port_color((battery_ticks %
-				LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-				LED_AMBER : LED_OFF);
-		else
-			set_active_port_color(LED_WHITE);
+		set_active_port_color(LED_WHITE);
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		set_active_port_color(
+			(battery_ticks % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
+				LED_AMBER :
+				LED_OFF);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
@@ -200,9 +201,10 @@ static void led_set_power(void)
 		led_set_color_power(LED_WHITE);
 	else if (chipset_in_state(CHIPSET_STATE_SUSPEND |
 				  CHIPSET_STATE_STANDBY))
-		led_set_color_power((power_tick %
-			LED_TICKS_PER_CYCLE < POWER_LED_ON_TICKS) ?
-			LED_WHITE : LED_OFF);
+		led_set_color_power((power_tick % LED_TICKS_PER_CYCLE <
+				     POWER_LED_ON_TICKS) ?
+					    LED_WHITE :
+					    LED_OFF);
 	else
 		led_set_color_power(LED_OFF);
 }
diff --git a/board/jinlon/thermal.c b/board/jinlon/thermal.c
index 03437fa3cd..70e6016109 100644
--- a/board/jinlon/thermal.c
+++ b/board/jinlon/thermal.c
@@ -1,8 +1,9 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "builtin/assert.h"
 #include "chipset.h"
 #include "common.h"
 #include "console.h"
@@ -16,7 +17,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_THERMAL, outstr)
-#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
 
 struct fan_step {
 	/*
@@ -40,109 +41,108 @@ static const struct fan_step *fan_step_table;
 static const struct fan_step fan_table_clamshell[] = {
 	{
 		/* level 0 */
-		.on = {0, -1, 54, 37},
-		.off = {99, -1, 99, 99},
-		.rpm = {0, 0},
+		.on = { 0, -1, 54, 37 },
+		.off = { 99, -1, 99, 99 },
+		.rpm = { 0, 0 },
 	},
 	{
 		/* level 1 */
-		.on = {0, -1, 57, 39},
-		.off = {99, -1, 54, 37},
-		.rpm = {3950, 3850},
+		.on = { 0, -1, 57, 39 },
+		.off = { 99, -1, 54, 37 },
+		.rpm = { 3950, 3850 },
 	},
 	{
 		/* level 2 */
-		.on = {0, -1, 58, 40},
-		.off = {99, -1, 57, 39},
-		.rpm = {4200, 4100},
+		.on = { 0, -1, 58, 40 },
+		.off = { 99, -1, 57, 39 },
+		.rpm = { 4200, 4100 },
 	},
 	{
 		/* level 3 */
-		.on = {0, -1, 59, 41},
-		.off = {99, -1, 58, 40},
-		.rpm = {4550, 4450},
+		.on = { 0, -1, 59, 41 },
+		.off = { 99, -1, 58, 40 },
+		.rpm = { 4550, 4450 },
 	},
 	{
 		/* level 4 */
-		.on = {62, -1, 60, 42},
-		.off = {58, -1, 59, 41},
-		.rpm = {4900, 4800},
+		.on = { 62, -1, 60, 42 },
+		.off = { 58, -1, 59, 41 },
+		.rpm = { 4900, 4800 },
 	},
 	{
 		/* level 5 */
-		.on = {64, -1, 61, 43},
-		.off = {62, -1, 60, 42},
-		.rpm = {5250, 5150},
+		.on = { 64, -1, 61, 43 },
+		.off = { 62, -1, 60, 42 },
+		.rpm = { 5250, 5150 },
 	},
 	{
 		/* level 6 */
-		.on = {65, -1, 64, 45},
-		.off = {63, -1, 61, 43},
-		.rpm = {5400, 5300},
+		.on = { 65, -1, 64, 45 },
+		.off = { 63, -1, 61, 43 },
+		.rpm = { 5400, 5300 },
 	},
 	{
 		/* level 7 */
-		.on = {100, -1, 100, 100},
-		.off = {65, -1, 62, 44},
-		.rpm = {6000, 5900},
+		.on = { 100, -1, 100, 100 },
+		.off = { 65, -1, 62, 44 },
+		.rpm = { 6000, 5900 },
 	},
 };
 
 static const struct fan_step fan_table_tablet[] = {
 	{
 		/* level 0 */
-		.on = {0, -1, 55, 41},
-		.off = {99, -1, 99, 99},
-		.rpm = {0, 0},
+		.on = { 0, -1, 55, 41 },
+		.off = { 99, -1, 99, 99 },
+		.rpm = { 0, 0 },
 	},
 	{
 		/* level 1 */
-		.on = {0, -1, 56, 42},
-		.off = {99, -1, 55, 41},
-		.rpm = {0, 0},
+		.on = { 0, -1, 56, 42 },
+		.off = { 99, -1, 55, 41 },
+		.rpm = { 0, 0 },
 	},
 	{
 		/* level 2 */
-		.on = {0, -1, 57, 43},
-		.off = {99, -1, 56, 42},
-		.rpm = {4000, 3350},
+		.on = { 0, -1, 57, 43 },
+		.off = { 99, -1, 56, 42 },
+		.rpm = { 4000, 3350 },
 	},
 	{
 		/* level 3 */
-		.on = {0, -1, 58, 44},
-		.off = {99, -1, 57, 43},
-		.rpm = {4200, 3400},
+		.on = { 0, -1, 58, 44 },
+		.off = { 99, -1, 57, 43 },
+		.rpm = { 4200, 3400 },
 	},
 	{
 		/* level 4 */
-		.on = {60, -1, 59, 45},
-		.off = {58, -1, 58, 44},
-		.rpm = {4400, 3500},
+		.on = { 60, -1, 59, 45 },
+		.off = { 58, -1, 58, 44 },
+		.rpm = { 4400, 3500 },
 	},
 	{
 		/* level 5 */
-		.on = {62, -1, 60, 46},
-		.off = {60, -1, 59, 45},
-		.rpm = {4800, 4350},
+		.on = { 62, -1, 60, 46 },
+		.off = { 60, -1, 59, 45 },
+		.rpm = { 4800, 4350 },
 	},
 	{
 		/* level 6 */
-		.on = {65, -1, 61, 47},
-		.off = {62, -1, 60, 46},
-		.rpm = {5000, 4500},
+		.on = { 65, -1, 61, 47 },
+		.off = { 62, -1, 60, 46 },
+		.rpm = { 5000, 4500 },
 	},
 	{
 		/* level 7 */
-		.on = {100, -1, 100, 100},
-		.off = {65, -1, 61, 47},
-		.rpm = {5200, 5100},
+		.on = { 100, -1, 100, 100 },
+		.off = { 65, -1, 61, 47 },
+		.rpm = { 5200, 5100 },
 	},
 };
 
 #define NUM_FAN_LEVELS ARRAY_SIZE(fan_table_clamshell)
 
-BUILD_ASSERT(ARRAY_SIZE(fan_table_clamshell) ==
-	ARRAY_SIZE(fan_table_tablet));
+BUILD_ASSERT(ARRAY_SIZE(fan_table_clamshell) == ARRAY_SIZE(fan_table_tablet));
 
 int fan_table_to_rpm(int fan, int *temp)
 {
@@ -165,12 +165,15 @@ int fan_table_to_rpm(int fan, int *temp)
 	 */
 
 	if (temp[TEMP_SENSOR_1] < prev_tmp[TEMP_SENSOR_1] ||
-		temp[TEMP_SENSOR_3] < prev_tmp[TEMP_SENSOR_3] ||
-		temp[TEMP_SENSOR_4] < prev_tmp[TEMP_SENSOR_4]) {
+	    temp[TEMP_SENSOR_3] < prev_tmp[TEMP_SENSOR_3] ||
+	    temp[TEMP_SENSOR_4] < prev_tmp[TEMP_SENSOR_4]) {
 		for (i = current_level; i > 0; i--) {
-			if (temp[TEMP_SENSOR_1] < fan_step_table[i].off[TEMP_SENSOR_1] &&
-				 temp[TEMP_SENSOR_4] < fan_step_table[i].off[TEMP_SENSOR_4] &&
-				 temp[TEMP_SENSOR_3] < fan_step_table[i].off[TEMP_SENSOR_3])
+			if (temp[TEMP_SENSOR_1] <
+				    fan_step_table[i].off[TEMP_SENSOR_1] &&
+			    temp[TEMP_SENSOR_4] <
+				    fan_step_table[i].off[TEMP_SENSOR_4] &&
+			    temp[TEMP_SENSOR_3] <
+				    fan_step_table[i].off[TEMP_SENSOR_3])
 				current_level = i - 1;
 			else
 				break;
@@ -179,9 +182,12 @@ int fan_table_to_rpm(int fan, int *temp)
 		   temp[TEMP_SENSOR_3] > prev_tmp[TEMP_SENSOR_3] ||
 		   temp[TEMP_SENSOR_4] > prev_tmp[TEMP_SENSOR_4]) {
 		for (i = current_level; i < NUM_FAN_LEVELS; i++) {
-			if ((temp[TEMP_SENSOR_1] > fan_step_table[i].on[TEMP_SENSOR_1] &&
-				 temp[TEMP_SENSOR_4] > fan_step_table[i].on[TEMP_SENSOR_4]) ||
-				 temp[TEMP_SENSOR_3] > fan_step_table[i].on[TEMP_SENSOR_3])
+			if ((temp[TEMP_SENSOR_1] >
+				     fan_step_table[i].on[TEMP_SENSOR_1] &&
+			     temp[TEMP_SENSOR_4] >
+				     fan_step_table[i].on[TEMP_SENSOR_4]) ||
+			    temp[TEMP_SENSOR_3] >
+				    fan_step_table[i].on[TEMP_SENSOR_3])
 				current_level = i + 1;
 			else
 				break;
@@ -212,10 +218,8 @@ int fan_table_to_rpm(int fan, int *temp)
 
 void board_override_fan_control(int fan, int *tmp)
 {
-	if (chipset_in_state(CHIPSET_STATE_ON |
-		CHIPSET_STATE_ANY_SUSPEND)) {
+	if (chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND)) {
 		fan_set_rpm_mode(FAN_CH(fan), 1);
-		fan_set_rpm_target(FAN_CH(fan),
-			fan_table_to_rpm(fan, tmp));
+		fan_set_rpm_target(FAN_CH(fan), fan_table_to_rpm(fan, tmp));
 	}
 }
diff --git a/board/kakadu/board.c b/board/kakadu/board.c
index 89905aa4a3..4be1e3f795 100644
--- a/board/kakadu/board.c
+++ b/board/kakadu/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,6 +27,7 @@
 #include "host_command.h"
 #include "i2c.h"
 #include "lid_switch.h"
+#include "panic.h"
 #include "power.h"
 #include "power_button.h"
 #include "pwm.h"
@@ -43,8 +44,8 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
@@ -61,45 +62,40 @@ static void gauge_interrupt(enum gpio_signal signal)
 /******************************************************************************/
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] = {"BOARD_ID", 3300, 4096, 0, STM32_AIN(10)},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)},
-	[ADC_BATT_ID] = {"BATT_ID", 3300, 4096, 0, STM32_AIN(7)},
-	[ADC_POGO_ADC_INT_L] = {"POGO_ADC_INT_L", 3300, 4096, 0, STM32_AIN(6)},
+	[ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(10) },
+	[ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8) },
+	[ADC_BATT_ID] = { "BATT_ID", 3300, 4096, 0, STM32_AIN(7) },
+	[ADC_POGO_ADC_INT_L] = { "POGO_ADC_INT_L", 3300, 4096, 0,
+				 STM32_AIN(6) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /******************************************************************************/
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "typec",
-		.port = 0,
-		.kbps = 400,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	},
-	{
-		.name = "other",
-		.port = 1,
-		.kbps = 400,
-		.scl  = GPIO_I2C2_SCL,
-		.sda  = GPIO_I2C2_SDA
-	},
+	{ .name = "typec",
+	  .port = 0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "other",
+	  .port = 1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
-
 /* power signal list.  Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
+	{ GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" },
+	{ GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" },
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
 /******************************************************************************/
 /* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
+const struct spi_device_t spi_devices[] = {};
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
 /******************************************************************************/
@@ -119,8 +115,7 @@ struct mt6370_thermal_bound thermal_bound = {
 	.err = 4,
 };
 
-static void board_hpd_update(const struct usb_mux *me,
-			     mux_state_t mux_state,
+static void board_hpd_update(const struct usb_mux *me, mux_state_t mux_state,
 			     bool *ack_required)
 {
 	/* This driver does not use host command ACKs */
@@ -147,13 +142,16 @@ __override const struct rt946x_init_setting *board_rt946x_init_setting(void)
 	return &battery_init_setting;
 }
 
-struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_update,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+				.hpd_update = &board_hpd_update,
+			},
 	},
 };
 
@@ -244,9 +242,8 @@ int extpower_is_present(void)
 	if (board_vbus_source_enabled(CHARGE_PORT_USB_C))
 		usb_c_extpower_present = 0;
 	else
-		usb_c_extpower_present = tcpm_check_vbus_level(
-							CHARGE_PORT_USB_C,
-							VBUS_PRESENT);
+		usb_c_extpower_present =
+			tcpm_check_vbus_level(CHARGE_PORT_USB_C, VBUS_PRESENT);
 
 	return usb_c_extpower_present;
 }
@@ -334,17 +331,13 @@ enum lid_accelgyro_type {
 static enum lid_accelgyro_type lid_accelgyro_config;
 
 /* Matrix to rotate accelerometer into standard reference frame */
-static const mat33_fp_t lid_standard_ref = {
-	{FLOAT_TO_FP(-1), 0, 0},
-	{0, FLOAT_TO_FP(-1), 0},
-	{0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
 
-const mat33_fp_t lid_standard_ref_icm42607 = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t lid_standard_ref_icm42607 = { { 0, FLOAT_TO_FP(1), 0 },
+					       { FLOAT_TO_FP(-1), 0, 0 },
+					       { 0, 0, FLOAT_TO_FP(1) } };
 struct motion_sensor_t icm42607_lid_accel = {
 	 .name = "Accel",
 	 .active_mask = SENSOR_ACTIVE_S0_S3,
@@ -370,20 +363,20 @@ struct motion_sensor_t icm42607_lid_accel = {
 };
 
 struct motion_sensor_t icm42607_lid_gyro = {
-	 .name = "Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_ICM42607,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &icm42607_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_icm42607_data,
-	 .port = I2C_PORT_ACCEL,
-	 .i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &lid_standard_ref_icm42607,
-	 .min_frequency = ICM42607_GYRO_MIN_FREQ,
-	 .max_frequency = ICM42607_GYRO_MAX_FREQ,
+	.name = "Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM42607,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_LID,
+	.drv = &icm42607_drv,
+	.mutex = &g_lid_mutex,
+	.drv_data = &g_icm42607_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &lid_standard_ref_icm42607,
+	.min_frequency = ICM42607_GYRO_MIN_FREQ,
+	.max_frequency = ICM42607_GYRO_MAX_FREQ,
 };
 
 struct motion_sensor_t motion_sensors[] = {
@@ -460,18 +453,18 @@ static void board_detect_motionsensor(void)
 	if (lid_accelgyro_config != LID_GYRO_NONE)
 		return;
 	/* Check base accelgyro chip */
-	ret = icm_read8(&icm42607_lid_accel,
-				ICM42607_REG_WHO_AM_I, &val);
+	ret = icm_read8(&icm42607_lid_accel, ICM42607_REG_WHO_AM_I, &val);
 	if (ret)
 		ccprints("Get ICM fail.");
 	if (val == ICM42607_CHIP_ICM42607P) {
 		motion_sensors[LID_ACCEL] = icm42607_lid_accel;
 		motion_sensors[LID_GYRO] = icm42607_lid_gyro;
 	}
-	lid_accelgyro_config = (val == ICM42607_CHIP_ICM42607P)
-			? LID_GYRO_ICM426XX : LID_GYRO_BMI160;
-	ccprints("LID Accelgyro: %s", (val == ICM42607_CHIP_ICM42607P)
-			? "ICM42607" : "BMI160");
+	lid_accelgyro_config = (val == ICM42607_CHIP_ICM42607P) ?
+				       LID_GYRO_ICM426XX :
+				       LID_GYRO_BMI160;
+	ccprints("LID Accelgyro: %s",
+		 (val == ICM42607_CHIP_ICM42607P) ? "ICM42607" : "BMI160");
 }
 DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_detect_motionsensor,
 	     HOOK_PRIO_DEFAULT);
@@ -525,9 +518,8 @@ __override int board_charge_port_is_connected(int port)
 	return gpio_get_level(GPIO_POGO_VBUS_PRESENT);
 }
 
-__override
-void board_fill_source_power_info(int port,
-				  struct ec_response_usb_pd_power_info *r)
+__override void
+board_fill_source_power_info(int port, struct ec_response_usb_pd_power_info *r)
 {
 	r->meas.voltage_now = 3300;
 	r->meas.voltage_max = 3300;
@@ -540,13 +532,10 @@ void board_fill_source_power_info(int port,
 static void mt6370_reg_fix(void)
 {
 	i2c_update8(chg_chips[CHARGER_SOLO].i2c_port,
-		    chg_chips[CHARGER_SOLO].i2c_addr_flags,
-		    RT946X_REG_CHGCTRL1,
+		    chg_chips[CHARGER_SOLO].i2c_addr_flags, RT946X_REG_CHGCTRL1,
 		    BIT(3) | BIT(5), MASK_CLR);
 	i2c_update8(chg_chips[CHARGER_SOLO].i2c_port,
-		    chg_chips[CHARGER_SOLO].i2c_addr_flags,
-		    RT946X_REG_CHGCTRL2,
-		    BIT(5) | BIT(RT946X_SHIFT_BATDET_DIS_DLY),
-		    MASK_CLR);
+		    chg_chips[CHARGER_SOLO].i2c_addr_flags, RT946X_REG_CHGCTRL2,
+		    BIT(5) | BIT(RT946X_SHIFT_BATDET_DIS_DLY), MASK_CLR);
 }
 DECLARE_HOOK(HOOK_INIT, mt6370_reg_fix, HOOK_PRIO_DEFAULT);
diff --git a/board/kakadu/board.h b/board/kakadu/board.h
index 09ff6d10be..5d64af2f6b 100644
--- a/board/kakadu/board.h
+++ b/board/kakadu/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,7 +8,7 @@
 #ifndef __CROS_EC_BOARD_H
 #define __CROS_EC_BOARD_H
 
-#define BQ27541_ADDR	0x55
+#define BQ27541_ADDR 0x55
 #define VARIANT_KUKUI_BATTERY_BQ27541
 #define VARIANT_KUKUI_POGO_KEYBOARD
 
@@ -27,35 +27,33 @@
 #define CONFIG_USB_MUX_RUNTIME_CONFIG
 
 /* Battery */
-#define BATTERY_DESIRED_CHARGING_CURRENT    3500  /* mA */
+#define BATTERY_DESIRED_CHARGING_CURRENT 3500 /* mA */
 
 #define CONFIG_CHARGER_MT6370_BACKLIGHT
 
-
 /* Motion Sensors */
 #ifdef SECTION_IS_RW
 #define CONFIG_ACCELGYRO_BMI160
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
-#define CONFIG_ACCELGYRO_ICM42607	/* Base accel second source*/
+#define CONFIG_ACCELGYRO_ICM42607 /* Base accel second source*/
 #define CONFIG_ACCELGYRO_ICM42607_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
 
 /* Camera VSYNC */
 #define CONFIG_SYNC
 #define CONFIG_SYNC_COMMAND
-#define CONFIG_SYNC_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
+#define CONFIG_SYNC_INT_EVENT TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
 #endif /* SECTION_IS_RW */
 
 /* I2C ports */
-#define I2C_PORT_CHARGER  0
-#define I2C_PORT_TCPC0    0
-#define I2C_PORT_USB_MUX  0
-#define I2C_PORT_BATTERY  1
+#define I2C_PORT_CHARGER 0
+#define I2C_PORT_TCPC0 0
+#define I2C_PORT_USB_MUX 0
+#define I2C_PORT_BATTERY 1
 #define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
-#define I2C_PORT_ACCEL    1
-#define I2C_PORT_BC12     1
+#define I2C_PORT_ACCEL 1
+#define I2C_PORT_BC12 1
 
 /* Route sbs host requests to virtual battery driver */
 #define VIRTUAL_BATTERY_ADDR_FLAGS 0x0B
diff --git a/board/kakadu/build.mk b/board/kakadu/build.mk
index 7a3953b8bb..52ee1b3354 100644
--- a/board/kakadu/build.mk
+++ b/board/kakadu/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/kakadu/ec.tasklist b/board/kakadu/ec.tasklist
index fc26f445b2..8be28c373d 100644
--- a/board/kakadu/ec.tasklist
+++ b/board/kakadu/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/kakadu/gpio.inc b/board/kakadu/gpio.inc
index f52f2b7f2f..6f494a9388 100644
--- a/board/kakadu/gpio.inc
+++ b/board/kakadu/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/kakadu/led.c b/board/kakadu/led.c
index 504bdf0d2f..26e1ea22bb 100644
--- a/board/kakadu/led.c
+++ b/board/kakadu/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -16,13 +16,13 @@ const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-#define LED_OFF		MT6370_LED_ID_OFF
-#define LED_AMBER	MT6370_LED_ID1
-#define LED_WHITE	MT6370_LED_ID2
+#define LED_OFF MT6370_LED_ID_OFF
+#define LED_AMBER MT6370_LED_ID1
+#define LED_WHITE MT6370_LED_ID2
 
-#define LED_MASK_OFF	0
-#define LED_MASK_AMBER	MT6370_MASK_RGB_ISNK1DIM_EN
-#define LED_MASK_WHITE	MT6370_MASK_RGB_ISNK2DIM_EN
+#define LED_MASK_OFF 0
+#define LED_MASK_AMBER MT6370_MASK_RGB_ISNK1DIM_EN
+#define LED_MASK_WHITE MT6370_MASK_RGB_ISNK2DIM_EN
 
 static void kakadu_led_set_battery(void)
 {
diff --git a/board/kano/battery.c b/board/kano/battery.c
index 395b45371d..0b1d956173 100644
--- a/board/kano/battery.c
+++ b/board/kano/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/kano/board.c b/board/kano/board.c
index 7ed766698c..06f4a543d8 100644
--- a/board/kano/board.c
+++ b/board/kano/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,8 +27,8 @@
 #include "gpio_list.h" /* Must come after other header files. */
 
 /* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 /******************************************************************************/
 /* USB-A charging control */
@@ -80,8 +80,8 @@ int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
 	}
 
 	if (voltage < BC12_MIN_VOLTAGE) {
-		CPRINTS("%s: port %d: vbus %d lower than %d", __func__,
-			port, voltage, BC12_MIN_VOLTAGE);
+		CPRINTS("%s: port %d: vbus %d lower than %d", __func__, port,
+			voltage, BC12_MIN_VOLTAGE);
 		return 1;
 	}
 
@@ -108,15 +108,14 @@ enum battery_present battery_hw_present(void)
  * that we don't have pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-	{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-	{0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3},
-	{-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0},
-	{1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4},
-	{2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0},
-	{-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1},
-	{-1, -1},
+	{ -1, -1 }, { 0, 5 },	{ 1, 1 }, { 1, 0 },   { 0, 6 },	  { 0, 7 },
+	{ -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 },   { -1, -1 }, { 1, 6 },
+	{ 1, 7 },   { 3, 1 },	{ 2, 0 }, { 1, 5 },   { 2, 6 },	  { 2, 7 },
+	{ 2, 1 },   { 2, 4 },	{ 2, 5 }, { 1, 2 },   { 2, 3 },	  { 2, 2 },
+	{ 3, 0 },   { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 },	  { -1, -1 },
+	{ -1, -1 },
 };
 
 const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 #endif
diff --git a/board/kano/board.h b/board/kano/board.h
index e3988aad3f..156df67af0 100644
--- a/board/kano/board.h
+++ b/board/kano/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,7 +25,7 @@
 #define CONFIG_LED_ONOFF_STATES
 
 /* Sensors */
-#define CONFIG_ACCELGYRO_ICM426XX	/* Base accel */
+#define CONFIG_ACCELGYRO_ICM426XX /* Base accel */
 #define CONFIG_ACCELGYRO_ICM_COMM_I2C
 #define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
@@ -46,12 +46,11 @@
 /* Lid accel */
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE	BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID	LID_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
 #define CONFIG_ACCEL_KX022
 #define CONFIG_ACCEL_BMA4XX
 
-
 /* Sensor console commands */
 #define CONFIG_CMD_ACCELS
 #define CONFIG_CMD_ACCEL_INFO
@@ -61,9 +60,8 @@
 #define CONFIG_KEYBOARD_REFRESH_ROW3
 #define CONFIG_KEYBOARD_FACTORY_TEST
 
-
 /* USB Type A Features */
-#define USB_PORT_COUNT			1
+#define USB_PORT_COUNT 1
 #define CONFIG_USB_PORT_POWER_DUMB
 
 /* USB Type C and USB PD defines */
@@ -77,17 +75,17 @@
 #define CONFIG_USB_PD_TCPM_RT1715
 
 /* TODO: b/177608416 - measure and check these values on brya */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
 
 /*
  * Passive USB-C cables only support up to 60W.
  */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /*
  * Macros for GPIO signals used in common code that don't match the
@@ -95,70 +93,70 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT		GPIO_EC_EN_EDP_BL
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_GSC_PACKET_MODE
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SYS_SLP_S0IX_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_TEMP_SENSOR_POWER		GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
 
 /*
  * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
  * signal.
  */
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_SEQ_EC_ALL_SYS_PG
-#define GPIO_PG_EC_DSW_PWROK		GPIO_SEQ_EC_DSW_PWROK
-#define GPIO_PG_EC_RSMRST_ODL		GPIO_SEQ_EC_RSMRST_ODL
-#define GPIO_POWER_BUTTON_L		GPIO_GSC_EC_PWR_BTN_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_ODL
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
 
 /* System has back-lit keyboard */
 #define CONFIG_PWM_KBLIGHT
 
 /* I2C Bus Configuration */
 
-#define I2C_PORT_ACCEL		NPCX_I2C_PORT0_0
+#define I2C_PORT_ACCEL NPCX_I2C_PORT0_0
 
-#define I2C_PORT_USB_C0_C2_TCPC	NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1_TCPC	NPCX_I2C_PORT4_1
+#define I2C_PORT_USB_C0_C2_TCPC NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1
 
-#define I2C_PORT_USB_C0_C2_PPC	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_PPC	NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C0_C2_PPC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1
 
-#define I2C_PORT_USB_C0_C2_BC12	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_BC12	NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C0_C2_BC12 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1
 
-#define I2C_PORT_USB_C0_C2_MUX	NPCX_I2C_PORT3_0
-#define I2C_PORT_USB_C1_MUX	NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C0_C2_MUX NPCX_I2C_PORT3_0
+#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1
 
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT5_0
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT7_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-#define I2C_PORT_MP2964		NPCX_I2C_PORT7_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0
 
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 
-#define I2C_ADDR_MP2964_FLAGS	0x20
+#define I2C_ADDR_MP2964_FLAGS 0x20
 
 /*
  * see b/174768555#comment22
  */
-#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR	0x54
+#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x54
 /* SOC facing Burnside Bridge retimer */
-#define USBC_PORT_C1_SOC_BB_RETIMER_I2C_ADDR    0x55
+#define USBC_PORT_C1_SOC_BB_RETIMER_I2C_ADDR 0x55
 /* Type-C connector facing Burnside Bridge retimer */
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x56
+#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x56
 
 /* Enabling Thunderbolt-compatible mode */
 #define CONFIG_USB_PD_TBT_COMPAT_MODE
@@ -180,12 +178,12 @@
 /* Charger defines */
 #define CONFIG_CHARGER_ISL9241
 #define CONFIG_CHARGE_RAMP_SW
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 
 #ifndef __ASSEMBLER__
 
-#include "gpio_signal.h"	/* needed by registers.h */
+#include "gpio_signal.h" /* needed by registers.h */
 #include "registers.h"
 #include "usbc_config.h"
 
@@ -203,33 +201,19 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL = 0, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
-enum battery_type {
-	BATTERY_AP19B8M,
-	BATTERY_TYPE_COUNT
-};
+enum battery_type { BATTERY_AP19B8M, BATTERY_TYPE_COUNT };
 
 enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,		/* PWM3 */
-	PWM_CH_FAN,			/* PWM5 */
+	PWM_CH_KBLIGHT = 0, /* PWM3 */
+	PWM_CH_FAN, /* PWM5 */
 	PWM_CH_COUNT
 };
 
-enum fan_channel {
-	FAN_CH_0 = 0,
-	FAN_CH_COUNT
-};
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT };
 
-enum mft_channel {
-	MFT_CH_0 = 0,
-	MFT_CH_COUNT
-};
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT };
 
 void motion_interrupt(enum gpio_signal signal);
 
diff --git a/board/kano/build.mk b/board/kano/build.mk
index df453187bf..0393829e6e 100644
--- a/board/kano/build.mk
+++ b/board/kano/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/kano/charger.c b/board/kano/charger.c
index 9f7c760858..ab48a7338c 100644
--- a/board/kano/charger.c
+++ b/board/kano/charger.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,9 +15,8 @@
 #include "usb_pd.h"
 #include "util.h"
 
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* Charger Chip Configuration */
 const struct charger_config_t chg_chips[] = {
@@ -84,7 +83,6 @@ int board_set_active_charge_port(int port)
 __overridable void board_set_charge_limit(int port, int supplier, int charge_ma,
 					  int max_ma, int charge_mv)
 {
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
diff --git a/board/kano/ec.tasklist b/board/kano/ec.tasklist
index f52567d9fa..64edf7bf2e 100644
--- a/board/kano/ec.tasklist
+++ b/board/kano/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/kano/fans.c b/board/kano/fans.c
index b652ec90da..54ec134fd2 100644
--- a/board/kano/fans.c
+++ b/board/kano/fans.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,7 +25,7 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 static const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
diff --git a/board/kano/fw_config.c b/board/kano/fw_config.c
index e6e5ba28bb..f04fd0063b 100644
--- a/board/kano/fw_config.c
+++ b/board/kano/fw_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,7 +9,7 @@
 #include "cros_board_info.h"
 #include "fw_config.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 static union kano_cbi_fw_config fw_config;
 BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
diff --git a/board/kano/fw_config.h b/board/kano/fw_config.h
index 88573bdd33..9f0c1c3373 100644
--- a/board/kano/fw_config.h
+++ b/board/kano/fw_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,12 +26,12 @@ enum ec_cfg_thermal_solution_type {
 
 union kano_cbi_fw_config {
 	struct {
-		enum ec_cfg_keyboard_backlight_type	kb_bl : 1;
-		uint32_t				audio : 3;
-		uint32_t				ufc : 2;
-		uint32_t				stylus : 1;
-		enum ec_cfg_thermal_solution_type	thermal_solution : 1;
-		uint32_t				reserved_1 : 24;
+		enum ec_cfg_keyboard_backlight_type kb_bl : 1;
+		uint32_t audio : 3;
+		uint32_t ufc : 2;
+		uint32_t stylus : 1;
+		enum ec_cfg_thermal_solution_type thermal_solution : 1;
+		uint32_t reserved_1 : 24;
 	};
 	uint32_t raw_value;
 };
diff --git a/board/kano/gpio.inc b/board/kano/gpio.inc
index cfcc6bbd3f..2ace5cbbca 100644
--- a/board/kano/gpio.inc
+++ b/board/kano/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/kano/i2c.c b/board/kano/i2c.c
index e779e119e3..6f5983c928 100644
--- a/board/kano/i2c.c
+++ b/board/kano/i2c.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/kano/keyboard.c b/board/kano/keyboard.c
index 38e96620e2..a96971c781 100644
--- a/board/kano/keyboard.c
+++ b/board/kano/keyboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -41,8 +41,8 @@ static const struct ec_response_keybd_config kano_kb = {
 	},
 	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
 };
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	return &kano_kb;
 }
diff --git a/board/kano/led.c b/board/kano/led.c
index 23c9fca50c..1bbfc283de 100644
--- a/board/kano/led.c
+++ b/board/kano/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  * Power and battery LED control for kano
@@ -18,23 +18,28 @@ __override const int led_charge_lvl_1 = 5;
 __override const int led_charge_lvl_2 = 95;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
diff --git a/board/kano/pwm.c b/board/kano/pwm.c
index f2c0d0db7d..6aae786cf3 100644
--- a/board/kano/pwm.c
+++ b/board/kano/pwm.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/kano/sensors.c b/board/kano/sensors.c
index e3e2f9d920..5eb1f6f933 100644
--- a/board/kano/sensors.c
+++ b/board/kano/sensors.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -65,27 +65,19 @@ static enum base_accelgyro_type base_accelgyro_config;
  * TODO:(b/197200940): Verify lid and base orientation
  * matrix on proto board.
  */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, FLOAT_TO_FP(1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, FLOAT_TO_FP(1), 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
 
-static const mat33_fp_t lid_bma422_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-static const mat33_fp_t base_bmi260_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lid_bma422_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+						    { FLOAT_TO_FP(-1), 0, 0 },
+						    { 0, 0, FLOAT_TO_FP(-1) } };
+static const mat33_fp_t base_bmi260_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+						     { FLOAT_TO_FP(-1), 0, 0 },
+						     { 0, 0, FLOAT_TO_FP(1) } };
 
 static struct motion_sensor_t bmi260_base_accel = {
 	.name = "Base Accel",
@@ -244,15 +236,15 @@ static void baseboard_sensors_detect(void)
 		return;
 
 	ret = i2c_read8(I2C_PORT_ACCEL, BMA4_I2C_ADDR_SECONDARY,
-		BMA4_CHIP_ID_ADDR, &val);
+			BMA4_CHIP_ID_ADDR, &val);
 	if (ret == 0 && val == BMA422_CHIP_ID) {
 		motion_sensors[LID_ACCEL] = bma422_lid_accel;
 		ccprints("LID_ACCEL is BMA422");
 	} else
 		ccprints("LID_ACCEL is KX022");
 
-	ret = bmi_read8(I2C_PORT_ACCEL, BMI260_ADDR0_FLAGS,
-		BMI260_CHIP_ID, &val);
+	ret = bmi_read8(I2C_PORT_ACCEL, BMI260_ADDR0_FLAGS, BMI260_CHIP_ID,
+			&val);
 	if (ret == 0 && val == BMI260_CHIP_ID_MAJOR) {
 		motion_sensors[BASE_ACCEL] = bmi260_base_accel;
 		motion_sensors[BASE_GYRO] = bmi260_base_gyro;
@@ -263,8 +255,7 @@ static void baseboard_sensors_detect(void)
 		ccprints("BASE ACCEL IS ICM426XX");
 	}
 }
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, baseboard_sensors_detect,
-	     HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, baseboard_sensors_detect, HOOK_PRIO_DEFAULT);
 
 static void baseboard_sensors_init(void)
 {
@@ -285,24 +276,18 @@ void motion_interrupt(enum gpio_signal signal)
 
 /* Temperature sensor configuration */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1_DDR_SOC] = {
-		.name = "DDR and SOC",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_1_DDR_SOC
-	},
-	[TEMP_SENSOR_2_FAN] = {
-		.name = "FAN",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_2_FAN
-	},
-	[TEMP_SENSOR_3_CHARGER] = {
-		.name = "CHARGER",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_3_CHARGER
-	},
+	[TEMP_SENSOR_1_DDR_SOC] = { .name = "DDR and SOC",
+				    .type = TEMP_SENSOR_TYPE_BOARD,
+				    .read = get_temp_3v3_30k9_47k_4050b,
+				    .idx = ADC_TEMP_SENSOR_1_DDR_SOC },
+	[TEMP_SENSOR_2_FAN] = { .name = "FAN",
+				.type = TEMP_SENSOR_TYPE_BOARD,
+				.read = get_temp_3v3_30k9_47k_4050b,
+				.idx = ADC_TEMP_SENSOR_2_FAN },
+	[TEMP_SENSOR_3_CHARGER] = { .name = "CHARGER",
+				    .type = TEMP_SENSOR_TYPE_BOARD,
+				    .read = get_temp_3v3_30k9_47k_4050b,
+				    .idx = ADC_TEMP_SENSOR_3_CHARGER },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -316,8 +301,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CPU \
-	{ \
+#define THERMAL_CPU              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = 0, \
 			[EC_TEMP_THRESH_HALT] = 0, \
@@ -346,8 +331,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_FAN \
-	{ \
+#define THERMAL_FAN              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(85), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(90), \
@@ -363,8 +348,8 @@ __maybe_unused static const struct ec_thermal_config thermal_fan = THERMAL_FAN;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_FAN_28W \
-	{ \
+#define THERMAL_FAN_28W          \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(85), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(90), \
@@ -376,7 +361,7 @@ __maybe_unused static const struct ec_thermal_config thermal_fan = THERMAL_FAN;
 		.temp_fan_max = C_TO_K(62), \
 	}
 __maybe_unused static const struct ec_thermal_config thermal_fan_28w =
-							THERMAL_FAN_28W;
+	THERMAL_FAN_28W;
 
 /*
  * Set value to zero to disable charger thermal control.
@@ -384,8 +369,8 @@ __maybe_unused static const struct ec_thermal_config thermal_fan_28w =
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CHARGER \
-	{ \
+#define THERMAL_CHARGER          \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = 0, \
 			[EC_TEMP_THRESH_HALT] = 0, \
@@ -397,13 +382,13 @@ __maybe_unused static const struct ec_thermal_config thermal_fan_28w =
 		.temp_fan_max = 0, \
 	}
 __maybe_unused static const struct ec_thermal_config thermal_charger =
-							THERMAL_CHARGER;
+	THERMAL_CHARGER;
 
 /* this should really be "const" */
 struct ec_thermal_config thermal_params[] = {
 	[TEMP_SENSOR_1_DDR_SOC] = THERMAL_CPU,
 	[TEMP_SENSOR_2_FAN] = THERMAL_FAN,
-	[TEMP_SENSOR_3_CHARGER]	= THERMAL_CHARGER,
+	[TEMP_SENSOR_3_CHARGER] = THERMAL_CHARGER,
 };
 BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
 
diff --git a/board/kano/usbc_config.c b/board/kano/usbc_config.c
index 0167646790..ed18b2d021 100644
--- a/board/kano/usbc_config.c
+++ b/board/kano/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -31,8 +31,8 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 /* USBC TCPC configuration */
 const struct tcpc_config_t tcpc_config[] = {
@@ -79,43 +79,56 @@ BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
 /* USBC mux configuration - Alder Lake includes internal mux */
-static const struct usb_mux usbc0_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+static const struct usb_mux_chain usbc0_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
 
-static const struct usb_mux usbc1_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+static const struct usb_mux_chain usbc1_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
 
-struct usb_mux soc_side_bb_retimer_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &bb_usb_retimer,
-	.hpd_update = bb_retimer_hpd_update,
-	.i2c_port = I2C_PORT_USB_C1_MUX,
-	.i2c_addr_flags = USBC_PORT_C1_SOC_BB_RETIMER_I2C_ADDR,
-	.next_mux = &usbc1_tcss_usb_mux,
+struct usb_mux_chain soc_side_bb_retimer_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C1_MUX,
+			.i2c_addr_flags = USBC_PORT_C1_SOC_BB_RETIMER_I2C_ADDR,
+		},
+	.next = &usbc1_tcss_usb_mux,
 };
 
-const struct usb_mux usb_muxes[] = {
+const struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C0_C2_MUX,
-		.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc0_tcss_usb_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C0_C2_MUX,
+			.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc0_tcss_usb_mux,
 	},
 	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C1_MUX,
-		.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
-		.next_mux = &soc_side_bb_retimer_usb_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C1_MUX,
+			.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &soc_side_bb_retimer_usb_mux,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
diff --git a/board/kano/usbc_config.h b/board/kano/usbc_config.h
index 38fce7d2cf..72e26c31c1 100644
--- a/board/kano/usbc_config.h
+++ b/board/kano/usbc_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,13 +8,9 @@
 #ifndef __CROS_EC_USBC_CONFIG_H
 #define __CROS_EC_USBC_CONFIG_H
 
-#define CONFIG_USB_PD_PORT_MAX_COUNT	2
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 void config_usb_db_type(void);
 
diff --git a/board/kappa/battery.c b/board/kappa/battery.c
index a098e2b8ce..bd8f05b418 100644
--- a/board/kappa/battery.c
+++ b/board/kappa/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/kappa/board.c b/board/kappa/board.c
index a0d5fda409..c04b24d3ed 100644
--- a/board/kappa/board.c
+++ b/board/kappa/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -30,6 +30,7 @@
 #include "it8801.h"
 #include "keyboard_scan.h"
 #include "lid_switch.h"
+#include "panic.h"
 #include "power.h"
 #include "power_button.h"
 #include "registers.h"
@@ -44,8 +45,8 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
@@ -57,40 +58,34 @@ static void tcpc_alert_event(enum gpio_signal signal)
 /******************************************************************************/
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] =  {"BOARD_ID",  3300, 4096, 0, STM32_AIN(10)},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)},
+	[ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(10) },
+	[ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /******************************************************************************/
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "typec",
-		.port = 0,
-		.kbps = 400,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	},
-	{
-		.name = "other",
-		.port = 1,
-		.kbps = 100,
-		.scl  = GPIO_I2C2_SCL,
-		.sda  = GPIO_I2C2_SDA
-	},
+	{ .name = "typec",
+	  .port = 0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "other",
+	  .port = 1,
+	  .kbps = 100,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
 const struct i2c_port_t i2c_bitbang_ports[] = {
-	{
-		.name = "battery",
-		.port = 2,
-		.kbps = 100,
-		.scl  = GPIO_I2C3_SCL,
-		.sda  = GPIO_I2C3_SDA,
-		.drv = &bitbang_drv
-	},
+	{ .name = "battery",
+	  .port = 2,
+	  .kbps = 100,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA,
+	  .drv = &bitbang_drv },
 };
 const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
 
@@ -98,8 +93,8 @@ const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
 
 /* power signal list.  Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
+	{ GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" },
+	{ GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" },
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
@@ -132,8 +127,7 @@ struct ioexpander_config_t ioex_config[CONFIG_IO_EXPANDER_PORT_COUNT] = {
 /******************************************************************************/
 /* SPI devices */
 /* TODO: to be added once sensors land via CL:1714436 */
-const struct spi_device_t spi_devices[] = {
-};
+const struct spi_device_t spi_devices[] = {};
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
 const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
@@ -155,8 +149,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-static void board_hpd_status(const struct usb_mux *me,
-			     mux_state_t mux_state,
+static void board_hpd_status(const struct usb_mux *me, mux_state_t mux_state,
 			     bool *ack_required)
 {
 	/* This driver does not use host command ACKs */
@@ -169,13 +162,16 @@ static void board_hpd_status(const struct usb_mux *me,
 	host_set_single_event(EC_HOST_EVENT_USB_MUX);
 }
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+				.hpd_update = &board_hpd_status,
+			},
 	},
 };
 
@@ -221,12 +217,12 @@ int board_set_active_charge_port(int charge_port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-			       CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 int board_discharge_on_ac(int enable)
diff --git a/board/kappa/board.h b/board/kappa/board.h
index 7cc7f68406..6b6461ae83 100644
--- a/board/kappa/board.h
+++ b/board/kappa/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -50,16 +50,16 @@
 #undef CONFIG_TABLET_MODE_SWITCH
 
 /* I2C ports */
-#define I2C_PORT_BC12               0
-#define I2C_PORT_TCPC0              0
-#define I2C_PORT_USB_MUX            0
-#define I2C_PORT_BATTERY            2
-#define I2C_PORT_CHARGER            1
-#define I2C_PORT_KB_DISCRETE        1
-#define I2C_PORT_VIRTUAL_BATTERY    I2C_PORT_BATTERY
+#define I2C_PORT_BC12 0
+#define I2C_PORT_TCPC0 0
+#define I2C_PORT_USB_MUX 0
+#define I2C_PORT_BATTERY 2
+#define I2C_PORT_CHARGER 1
+#define I2C_PORT_KB_DISCRETE 1
+#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
 
 /* IT8801 I2C address */
-#define KB_DISCRETE_I2C_ADDR_FLAGS  IT8801_I2C_ADDR1
+#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1
 
 #define CONFIG_KEYBOARD_PROTOCOL_MKBP
 #define CONFIG_MKBP_EVENT
diff --git a/board/kappa/build.mk b/board/kappa/build.mk
index e449fce9fc..80c34a4e46 100644
--- a/board/kappa/build.mk
+++ b/board/kappa/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/kappa/ec.tasklist b/board/kappa/ec.tasklist
index c41e203780..3705823bac 100644
--- a/board/kappa/ec.tasklist
+++ b/board/kappa/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/kappa/gpio.inc b/board/kappa/gpio.inc
index 0e01d54f10..d7d6c5267b 100644
--- a/board/kappa/gpio.inc
+++ b/board/kappa/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/kappa/led.c b/board/kappa/led.c
index 5b65d7b948..1c7979eac0 100644
--- a/board/kappa/led.c
+++ b/board/kappa/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -14,7 +14,7 @@
 #define BAT_LED_ON 0
 #define BAT_LED_OFF 1
 
-const enum ec_led_id supported_led_ids[] = {EC_LED_ID_BATTERY_LED};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -22,7 +22,7 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static int led_set_color_battery(enum led_color color)
@@ -82,16 +82,14 @@ static void led_set_battery(void)
 {
 	static int battery_ticks;
 	static int power_ticks;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
 	/* override battery led for system suspend */
-	if (chipset_in_state(CHIPSET_STATE_SUSPEND |
-			     CHIPSET_STATE_STANDBY) &&
+	if (chipset_in_state(CHIPSET_STATE_SUSPEND | CHIPSET_STATE_STANDBY) &&
 	    charge_get_state() != PWR_STATE_CHARGE) {
-		led_set_color_battery(power_ticks++ & 0x2 ?
-				      LED_WHITE : LED_OFF);
+		led_set_color_battery(power_ticks++ & 0x2 ? LED_WHITE :
+							    LED_OFF);
 		return;
 	}
 
@@ -119,19 +117,18 @@ static void led_set_battery(void)
 			led_set_color_battery(LED_OFF);
 		break;
 	case PWR_STATE_ERROR:
-		led_set_color_battery(
-			(battery_ticks % 0x2) ? LED_WHITE : LED_OFF);
+		led_set_color_battery((battery_ticks % 0x2) ? LED_WHITE :
+							      LED_OFF);
 		break;
 	case PWR_STATE_CHARGE_NEAR_FULL:
 		led_set_color_battery(LED_WHITE);
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			led_set_color_battery(
-				(battery_ticks & 0x2) ? LED_AMBER : LED_OFF);
-		else
-			led_set_color_battery(LED_WHITE);
+		led_set_color_battery(LED_WHITE);
 		break;
+	case PWR_STATE_FORCED_IDLE:
+		led_set_color_battery((battery_ticks & 0x2) ? LED_AMBER :
+							      LED_OFF);
 	default:
 		/* Other states don't alter LED behavior */
 		break;
diff --git a/board/karma/board.c b/board/karma/board.c
index 4e9f9166ff..df053ad782 100644
--- a/board/karma/board.c
+++ b/board/karma/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,8 +8,8 @@
 #include "hooks.h"
 #include "oz554.h"
 
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args)
 
 void oz554_board_init(void)
 {
diff --git a/board/karma/board.h b/board/karma/board.h
index 372b18509b..c3b6cd074a 100644
--- a/board/karma/board.h
+++ b/board/karma/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/karma/build.mk b/board/karma/build.mk
index 2554425920..bee5d9f886 100644
--- a/board/karma/build.mk
+++ b/board/karma/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/karma/ec.tasklist b/board/karma/ec.tasklist
index ca4e3b5ee6..829c9f19bc 100644
--- a/board/karma/ec.tasklist
+++ b/board/karma/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/karma/gpio.inc b/board/karma/gpio.inc
index bdf0ab93be..2f0fef053e 100644
--- a/board/karma/gpio.inc
+++ b/board/karma/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/katsu/board.c b/board/katsu/board.c
index a91f2c4afa..3527214f62 100644
--- a/board/katsu/board.c
+++ b/board/katsu/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,6 +26,7 @@
 #include "host_command.h"
 #include "i2c.h"
 #include "lid_switch.h"
+#include "panic.h"
 #include "power.h"
 #include "power_button.h"
 #include "pwm.h"
@@ -42,8 +43,8 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
@@ -60,45 +61,40 @@ static void gauge_interrupt(enum gpio_signal signal)
 /******************************************************************************/
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] = {"BOARD_ID", 3300, 4096, 0, STM32_AIN(10)},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)},
-	[ADC_BATT_ID] = {"BATT_ID", 3300, 4096, 0, STM32_AIN(7)},
-	[ADC_POGO_ADC_INT_L] = {"POGO_ADC_INT_L", 3300, 4096, 0, STM32_AIN(6)},
+	[ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(10) },
+	[ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8) },
+	[ADC_BATT_ID] = { "BATT_ID", 3300, 4096, 0, STM32_AIN(7) },
+	[ADC_POGO_ADC_INT_L] = { "POGO_ADC_INT_L", 3300, 4096, 0,
+				 STM32_AIN(6) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /******************************************************************************/
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "typec",
-		.port = 0,
-		.kbps = 400,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	},
-	{
-		.name = "other",
-		.port = 1,
-		.kbps = 400,
-		.scl  = GPIO_I2C2_SCL,
-		.sda  = GPIO_I2C2_SDA
-	},
+	{ .name = "typec",
+	  .port = 0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "other",
+	  .port = 1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
-
 /* power signal list.  Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
+	{ GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" },
+	{ GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" },
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
 /******************************************************************************/
 /* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
+const struct spi_device_t spi_devices[] = {};
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
 /******************************************************************************/
@@ -118,8 +114,7 @@ struct mt6370_thermal_bound thermal_bound = {
 	.err = 4,
 };
 
-static void board_hpd_update(const struct usb_mux *me,
-			     mux_state_t mux_state,
+static void board_hpd_update(const struct usb_mux *me, mux_state_t mux_state,
 			     bool *ack_required)
 {
 	/* This driver does not use host command ACKs */
@@ -146,13 +141,16 @@ __override const struct rt946x_init_setting *board_rt946x_init_setting(void)
 	return &battery_init_setting;
 }
 
-struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_update,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+				.hpd_update = &board_hpd_update,
+			},
 	},
 };
 
@@ -244,9 +242,8 @@ int extpower_is_present(void)
 	if (board_vbus_source_enabled(CHARGE_PORT_USB_C))
 		usb_c_extpower_present = 0;
 	else
-		usb_c_extpower_present = tcpm_check_vbus_level(
-							CHARGE_PORT_USB_C,
-							VBUS_PRESENT);
+		usb_c_extpower_present =
+			tcpm_check_vbus_level(CHARGE_PORT_USB_C, VBUS_PRESENT);
 
 	if (prev_usb_c_extpower_present != usb_c_extpower_present) {
 		if (usb_c_extpower_present)
@@ -332,11 +329,9 @@ static struct mutex g_lid_mutex;
 static struct icm_drv_data_t g_icm426xx_data;
 
 /* Matrix to rotate accelerometer into standard reference frame */
-static const mat33_fp_t lid_standard_ref = {
-	{0, FLOAT_TO_FP(1), 0},
-	{FLOAT_TO_FP(-1), 0, 0},
-	{0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					     { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	/*
@@ -436,9 +431,8 @@ __override int board_charge_port_is_connected(int port)
 	return gpio_get_level(GPIO_POGO_VBUS_PRESENT);
 }
 
-__override
-void board_fill_source_power_info(int port,
-				  struct ec_response_usb_pd_power_info *r)
+__override void
+board_fill_source_power_info(int port, struct ec_response_usb_pd_power_info *r)
 {
 	r->meas.voltage_now = 3300;
 	r->meas.voltage_max = 3300;
@@ -451,13 +445,10 @@ void board_fill_source_power_info(int port,
 static void mt6370_reg_fix(void)
 {
 	i2c_update8(chg_chips[CHARGER_SOLO].i2c_port,
-		    chg_chips[CHARGER_SOLO].i2c_addr_flags,
-		    RT946X_REG_CHGCTRL1,
+		    chg_chips[CHARGER_SOLO].i2c_addr_flags, RT946X_REG_CHGCTRL1,
 		    BIT(3) | BIT(5), MASK_CLR);
 	i2c_update8(chg_chips[CHARGER_SOLO].i2c_port,
-		    chg_chips[CHARGER_SOLO].i2c_addr_flags,
-		    RT946X_REG_CHGCTRL2,
-		    BIT(5) | BIT(RT946X_SHIFT_BATDET_DIS_DLY),
-		    MASK_CLR);
+		    chg_chips[CHARGER_SOLO].i2c_addr_flags, RT946X_REG_CHGCTRL2,
+		    BIT(5) | BIT(RT946X_SHIFT_BATDET_DIS_DLY), MASK_CLR);
 }
 DECLARE_HOOK(HOOK_INIT, mt6370_reg_fix, HOOK_PRIO_DEFAULT);
diff --git a/board/katsu/board.h b/board/katsu/board.h
index afb5cf28e0..6f53801ffc 100644
--- a/board/katsu/board.h
+++ b/board/katsu/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,7 +8,7 @@
 #ifndef __CROS_EC_BOARD_H
 #define __CROS_EC_BOARD_H
 
-#define BQ27541_ADDR	0x55
+#define BQ27541_ADDR 0x55
 #define VARIANT_KUKUI_BATTERY_BQ27541
 #define VARIANT_KUKUI_POGO_KEYBOARD
 
@@ -27,11 +27,10 @@
 #define CONFIG_USB_MUX_RUNTIME_CONFIG
 
 /* Battery */
-#define BATTERY_DESIRED_CHARGING_CURRENT    3500  /* mA */
+#define BATTERY_DESIRED_CHARGING_CURRENT 3500 /* mA */
 
 #define CONFIG_CHARGER_MT6370_BACKLIGHT
 
-
 /* Motion Sensors */
 #ifdef SECTION_IS_RW
 #define CONFIG_ACCELGYRO_ICM426XX
@@ -41,18 +40,17 @@
 /* Camera VSYNC */
 #define CONFIG_SYNC
 #define CONFIG_SYNC_COMMAND
-#define CONFIG_SYNC_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
+#define CONFIG_SYNC_INT_EVENT TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
 #endif /* SECTION_IS_RW */
 
 /* I2C ports */
-#define I2C_PORT_CHARGER  0
-#define I2C_PORT_TCPC0    0
-#define I2C_PORT_USB_MUX  0
-#define I2C_PORT_BATTERY  1
+#define I2C_PORT_CHARGER 0
+#define I2C_PORT_TCPC0 0
+#define I2C_PORT_USB_MUX 0
+#define I2C_PORT_BATTERY 1
 #define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
-#define I2C_PORT_ACCEL    1
-#define I2C_PORT_BC12     1
+#define I2C_PORT_ACCEL 1
+#define I2C_PORT_BC12 1
 
 /* Route sbs host requests to virtual battery driver */
 #define VIRTUAL_BATTERY_ADDR_FLAGS 0x0B
@@ -63,12 +61,12 @@
 #define CONFIG_MKBP_EVENT_WAKEUP_MASK \
 	(BIT(EC_MKBP_EVENT_SENSOR_FIFO) | BIT(EC_MKBP_EVENT_HOST_EVENT))
 #undef CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK
-#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \
-		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
+#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK                   \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |        \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |    \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |    \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
 
 #define PD_OPERATING_POWER_MW 15000
 
diff --git a/board/katsu/build.mk b/board/katsu/build.mk
index 7a3953b8bb..52ee1b3354 100644
--- a/board/katsu/build.mk
+++ b/board/katsu/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/katsu/ec.tasklist b/board/katsu/ec.tasklist
index fc26f445b2..8be28c373d 100644
--- a/board/katsu/ec.tasklist
+++ b/board/katsu/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/katsu/gpio.inc b/board/katsu/gpio.inc
index f938153045..82f7ddb3af 100644
--- a/board/katsu/gpio.inc
+++ b/board/katsu/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/katsu/led.c b/board/katsu/led.c
index c72f5e4cdb..3ce9466613 100644
--- a/board/katsu/led.c
+++ b/board/katsu/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -16,13 +16,13 @@ const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
-#define LED_OFF		MT6370_LED_ID_OFF
-#define LED_AMBER	MT6370_LED_ID1
-#define LED_WHITE	MT6370_LED_ID2
+#define LED_OFF MT6370_LED_ID_OFF
+#define LED_AMBER MT6370_LED_ID1
+#define LED_WHITE MT6370_LED_ID2
 
-#define LED_MASK_OFF	0
-#define LED_MASK_AMBER	MT6370_MASK_RGB_ISNK1DIM_EN
-#define LED_MASK_WHITE	MT6370_MASK_RGB_ISNK2DIM_EN
+#define LED_MASK_OFF 0
+#define LED_MASK_AMBER MT6370_MASK_RGB_ISNK1DIM_EN
+#define LED_MASK_WHITE MT6370_MASK_RGB_ISNK2DIM_EN
 
 static void katsu_led_set_battery(void)
 {
diff --git a/board/kindred/battery.c b/board/kindred/battery.c
index 9db25ac059..a087d0a85f 100644
--- a/board/kindred/battery.c
+++ b/board/kindred/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/kindred/board.c b/board/kindred/board.c
index 78ec2abf0c..d6c9372d47 100644
--- a/board/kindred/board.c
+++ b/board/kindred/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -46,8 +46,8 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static int lid_device_id;
 static int base_device_id;
@@ -66,17 +66,16 @@ const int usb_port_enable[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT] = {
  * that we don't have pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-		{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-		{0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3},
-		{-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0},
-		{1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4},
-		{2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0},
-		{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1},
-		{-1, -1},
+	{ -1, -1 }, { 0, 5 },	{ 1, 1 },   { 1, 0 },	{ 0, 6 },   { 0, 7 },
+	{ -1, -1 }, { -1, -1 }, { 1, 4 },   { 1, 3 },	{ -1, -1 }, { 1, 6 },
+	{ 1, 7 },   { 3, 1 },	{ 2, 0 },   { 1, 5 },	{ 2, 6 },   { 2, 7 },
+	{ 2, 1 },   { 2, 4 },	{ 2, 5 },   { 1, 2 },	{ 2, 3 },   { 2, 2 },
+	{ 3, 0 },   { -1, -1 }, { -1, -1 }, { -1, -1 }, { -1, -1 }, { -1, -1 },
+	{ -1, -1 },
 };
 
 const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 
 static void ppc_interrupt(enum gpio_signal signal)
 {
@@ -137,16 +136,16 @@ static void bc12_interrupt(enum gpio_signal signal)
 
 /******************************************************************************/
 /* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
+const struct spi_device_t spi_devices[] = {};
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
 /******************************************************************************/
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT]   = { .channel = 3, .flags = 0, .freq = 10000 },
-	[PWM_CH_FAN] = {.channel = 5, .flags = PWM_CONFIG_OPEN_DRAIN,
-			.freq = 25000},
+	[PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 },
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
@@ -173,16 +172,20 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_TCPC_0] = {
-		.usb_port = USB_PD_PORT_TCPC_0,
-		.driver = &anx7447_usb_mux_driver,
-		.hpd_update = &anx7447_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_0,
+			.driver = &anx7447_usb_mux_driver,
+			.hpd_update = &anx7447_tcpc_update_hpd_status,
+		},
 	},
 	[USB_PD_PORT_TCPC_1] = {
-		.usb_port = USB_PD_PORT_TCPC_1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 	}
 };
 
@@ -213,23 +216,17 @@ static struct accelgyro_saved_data_t g_bma255_data;
 static struct kionix_accel_data g_kx022_data;
 
 /* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, FLOAT_TO_FP(-1), 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
 
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
 
-static const mat33_fp_t base_icm_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t base_icm_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					 { FLOAT_TO_FP(-1), 0, 0 },
+					 { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t kx022_lid_accel = {
 	.name = "Lid Accel",
@@ -302,7 +299,6 @@ struct motion_sensor_t icm426xx_base_gyro = {
 	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
 };
 
-
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
 		.name = "Lid Accel",
@@ -382,7 +378,7 @@ unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
@@ -401,38 +397,37 @@ const struct fan_t fans[FAN_CH_COUNT] = {
 /******************************************************************************/
 /* MFT channels. These are logically separate from pwm_channels. */
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN },
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_2] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_3] = {
-		"TEMP_WIFI", NPCX_ADC_CH3, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_1] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_2] = { "TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_3] = { "TEMP_WIFI", NPCX_ADC_CH3, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Temp1",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Temp2",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "Temp3",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_3},
+	[TEMP_SENSOR_1] = { .name = "Temp1",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Temp2",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "Temp3",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
-
 /* Hatch Temperature sensors */
 /*
  * TODO(b/124316213): These setting need to be reviewed and set appropriately
@@ -442,8 +437,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_A \
-	{ \
+#define THERMAL_A                \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = 0, \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
@@ -498,7 +493,6 @@ static void board_gpio_set_pp5000(void)
 	} else if (board_id >= 1) {
 		reset_gpio_flags(GPIO_EN_PP5000_A_V1, GPIO_OUT_LOW);
 	}
-
 }
 
 bool board_is_convertible(void)
@@ -582,15 +576,14 @@ static void determine_accel_devices(void)
 
 	if (read_time == 0 && board_is_convertible()) {
 		/* Read g sensor chip id*/
-		i2c_read8(I2C_PORT_ACCEL,
-			  KX022_ADDR0_FLAGS, KX022_WHOAMI, &lid_device_id);
+		i2c_read8(I2C_PORT_ACCEL, KX022_ADDR0_FLAGS, KX022_WHOAMI,
+			  &lid_device_id);
 		/* Read gyro sensor id*/
-		i2c_read8(I2C_PORT_ACCEL,
-			  ICM426XX_ADDR0_FLAGS,
-			    ICM426XX_REG_WHO_AM_I, &base_device_id);
+		i2c_read8(I2C_PORT_ACCEL, ICM426XX_ADDR0_FLAGS,
+			  ICM426XX_REG_WHO_AM_I, &base_device_id);
 
-		CPRINTS("Motion Sensor Base id = %d Lid id =%d",
-			  base_device_id, lid_device_id);
+		CPRINTS("Motion Sensor Base id = %d Lid id =%d", base_device_id,
+			lid_device_id);
 
 		if (lid_device_id == KX022_WHO_AM_I_VAL) {
 			motion_sensors[LID_ACCEL] = kx022_lid_accel;
@@ -657,7 +650,8 @@ __override void board_chipset_forced_shutdown(void)
 {
 	hook_call_deferred(&check_reboot_deferred_data, -1);
 }
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_forced_shutdown, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_forced_shutdown,
+	     HOOK_PRIO_DEFAULT);
 
 static void check_reboot_deferred(void)
 {
diff --git a/board/kindred/board.h b/board/kindred/board.h
index f85742d27e..1372887446 100644
--- a/board/kindred/board.h
+++ b/board/kindred/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,7 +12,7 @@
 #include "baseboard.h"
 
 #define CONFIG_POWER_BUTTON
-#undef  CONFIG_POWER_BUTTON_INIT_TIMEOUT
+#undef CONFIG_POWER_BUTTON_INIT_TIMEOUT
 #define CONFIG_POWER_BUTTON_INIT_TIMEOUT 2
 #define CONFIG_KEYBOARD_PROTOCOL_8042
 #define CONFIG_LED_COMMON
@@ -111,16 +111,16 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_AC_PRESENT		GPIO_ACOK_OD
-#define GPIO_PG_EC_RSMRST_ODL	GPIO_PG_EC_RSMRST_L
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_TEMP_SENSOR_POWER	GPIO_EN_A_RAILS
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L
+#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
 
 #ifndef __ASSEMBLER__
 #include "gpio_signal.h"
@@ -131,9 +131,9 @@
 extern enum gpio_signal gpio_en_pp5000_a;
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_1,	/* ADC0 */
-	ADC_TEMP_SENSOR_2,	/* ADC1 */
-	ADC_TEMP_SENSOR_3,	/* ADC3 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
+	ADC_TEMP_SENSOR_3, /* ADC3 */
 	ADC_CH_COUNT
 };
 
@@ -144,11 +144,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_FAN,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_FAN, PWM_CH_COUNT };
 
 enum fan_channel {
 	FAN_CH_0 = 0,
diff --git a/board/kindred/build.mk b/board/kindred/build.mk
index 733912454f..13153c1526 100644
--- a/board/kindred/build.mk
+++ b/board/kindred/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/kindred/ec.tasklist b/board/kindred/ec.tasklist
index 4a1024a091..829be2b7c8 100644
--- a/board/kindred/ec.tasklist
+++ b/board/kindred/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/kindred/gpio.inc b/board/kindred/gpio.inc
index 2adb08f564..ec336c5542 100644
--- a/board/kindred/gpio.inc
+++ b/board/kindred/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,10 +16,10 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(PG_EC_RSMRST_L,       PIN(E, 2), GPIO_INT_BOTH, intel_x86_rsmrst_signal_interrupt)
diff --git a/board/kindred/led.c b/board/kindred/led.c
index ff91d15424..05cc15b617 100644
--- a/board/kindred/led.c
+++ b/board/kindred/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,23 +19,28 @@ __override const int led_charge_lvl_1 = 5;
 __override const int led_charge_lvl_2 = 95;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
diff --git a/board/kingoftown/battery.c b/board/kingoftown/battery.c
index 3fd82bc282..3a74f99907 100644
--- a/board/kingoftown/battery.c
+++ b/board/kingoftown/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/kingoftown/board.c b/board/kingoftown/board.c
index e3d91575e1..9ee1402380 100644
--- a/board/kingoftown/board.c
+++ b/board/kingoftown/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,8 +26,8 @@
 #include "usbc_config.h"
 #include "usbc_ppc.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 #include "gpio_list.h"
 
@@ -39,10 +39,8 @@ __override struct keyboard_scan_config keyscan_config = {
 	 * Unmask 0x08 in [0] (KSO_00/KSI_03, the new location of Search key);
 	 * as it still uses the legacy location (KSO_01/KSI_00).
 	 */
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca
-	},
+	.actual_key_mask = { 0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, 0xa4,
+			     0xff, 0xfe, 0x55, 0xfa, 0xca },
 	/* Other values should be the same as the default configuration. */
 	.debounce_down_us = 9 * MSEC,
 	.debounce_up_us = 30 * MSEC,
@@ -57,52 +55,42 @@ __override struct keyboard_scan_config keyscan_config = {
  * The connector has 24 pins total, and there is no pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-	{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-	{0, 7}, {1, 4}, {1, 3}, {1, 6}, {1, 7},
-	{3, 1}, {2, 0}, {1, 5}, {2, 6}, {2, 7},
-	{2, 1}, {2, 4}, {2, 5}, {1, 2}, {2, 3},
-	{2, 2}, {3, 0}, {-1, -1}, {-1, -1}, {-1, -1},
+	{ -1, -1 }, { 0, 5 }, { 1, 1 },	  { 1, 0 },   { 0, 6 },
+	{ 0, 7 },   { 1, 4 }, { 1, 3 },	  { 1, 6 },   { 1, 7 },
+	{ 3, 1 },   { 2, 0 }, { 1, 5 },	  { 2, 6 },   { 2, 7 },
+	{ 2, 1 },   { 2, 4 }, { 2, 5 },	  { 1, 2 },   { 2, 3 },
+	{ 2, 2 },   { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 },
 };
 const int keyboard_factory_scan_pins_used =
-		ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 
 /* I2C port map */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl  = GPIO_EC_I2C_POWER_SCL,
-		.sda  = GPIO_EC_I2C_POWER_SDA
-	},
-	{
-		.name = "tcpc0",
-		.port = I2C_PORT_TCPC0,
-		.kbps = 1000,
-		.scl  = GPIO_EC_I2C_USB_C0_PD_SCL,
-		.sda  = GPIO_EC_I2C_USB_C0_PD_SDA
-	},
-	{
-		.name = "tcpc1",
-		.port = I2C_PORT_TCPC1,
-		.kbps = 1000,
-		.scl  = GPIO_EC_I2C_USB_C1_PD_SCL,
-		.sda  = GPIO_EC_I2C_USB_C1_PD_SDA
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_EEPROM_SCL,
-		.sda  = GPIO_EC_I2C_EEPROM_SDA
-	},
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_SENSOR_SCL,
-		.sda  = GPIO_EC_I2C_SENSOR_SDA
-	},
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_POWER_SCL,
+	  .sda = GPIO_EC_I2C_POWER_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C0_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C0_PD_SDA },
+	{ .name = "tcpc1",
+	  .port = I2C_PORT_TCPC1,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C1_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C1_PD_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_EEPROM_SCL,
+	  .sda = GPIO_EC_I2C_EEPROM_SDA },
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_SENSOR_SCL,
+	  .sda = GPIO_EC_I2C_SENSOR_SDA },
 };
 
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
@@ -110,37 +98,22 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* Measure VBUS through a 1/10 voltage divider */
-	[ADC_VBUS] = {
-		"VBUS",
-		NPCX_ADC_CH1,
-		ADC_MAX_VOLT * 10,
-		ADC_READ_MAX + 1,
-		0
-	},
+	[ADC_VBUS] = { "VBUS", NPCX_ADC_CH1, ADC_MAX_VOLT * 10,
+		       ADC_READ_MAX + 1, 0 },
 	/*
 	 * Adapter current output or battery charging/discharging current (uV)
 	 * 18x amplification on charger side.
 	 */
-	[ADC_AMON_BMON] = {
-		"AMON_BMON",
-		NPCX_ADC_CH2,
-		ADC_MAX_VOLT * 1000 / 18,
-		ADC_READ_MAX + 1,
-		0
-	},
+	[ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH2, ADC_MAX_VOLT * 1000 / 18,
+			    ADC_READ_MAX + 1, 0 },
 	/*
 	 * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read
 	 * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and
 	 * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we
 	 * only divide by 2 (enough to avoid precision issues).
 	 */
-	[ADC_PSYS] = {
-		"PSYS",
-		NPCX_ADC_CH3,
-		ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1),
-		2,
-		0
-	},
+	[ADC_PSYS] = { "PSYS", NPCX_ADC_CH3,
+		       ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), 2, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
@@ -192,17 +165,13 @@ static struct bmi_drv_data_t g_bmi160_data;
 static struct accelgyro_saved_data_t g_bma255_data;
 
 /* Matrix to rotate accelerometer into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0,  0},
-	{ 0,  FLOAT_TO_FP(-1),  0},
-	{ 0,  0, FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+				       { 0, FLOAT_TO_FP(-1), 0 },
+				       { 0, 0, FLOAT_TO_FP(-1) } };
 
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					     { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
diff --git a/board/kingoftown/board.h b/board/kingoftown/board.h
index e71fdd6741..6b553f65fa 100644
--- a/board/kingoftown/board.h
+++ b/board/kingoftown/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,7 +11,7 @@
 #include "baseboard.h"
 
 /* Internal SPI flash on NPCX7 */
-#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)  /* 512KB internal spi flash */
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */
 
 /* Keyboard */
 #define CONFIG_KEYBOARD_PROTOCOL_MKBP
@@ -20,7 +20,7 @@
 #define CONFIG_PWM_KBLIGHT
 
 /* Battery */
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY  "LION"
+#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
 #define CONFIG_BATTERY_REVIVE_DISCONNECT
 #define CONFIG_BATTERY_FUEL_GAUGE
 #define CONFIG_BATTERY_VENDOR_PARAM
@@ -68,12 +68,7 @@
 #include "gpio_signal.h"
 #include "registers.h"
 
-enum adc_channel {
-	ADC_VBUS,
-	ADC_AMON_BMON,
-	ADC_PSYS,
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_VBUS, ADC_AMON_BMON, ADC_PSYS, ADC_CH_COUNT };
 
 /* Motion sensors */
 enum sensor_id {
@@ -83,11 +78,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_DISPLIGHT,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_DISPLIGHT, PWM_CH_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
diff --git a/board/kingoftown/build.mk b/board/kingoftown/build.mk
index 5415d90b29..2c5eb4ae2e 100644
--- a/board/kingoftown/build.mk
+++ b/board/kingoftown/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/kingoftown/ec.tasklist b/board/kingoftown/ec.tasklist
index 5beeb38feb..228828af3c 100644
--- a/board/kingoftown/ec.tasklist
+++ b/board/kingoftown/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/kingoftown/gpio.inc b/board/kingoftown/gpio.inc
index 612de59128..7147869ea3 100644
--- a/board/kingoftown/gpio.inc
+++ b/board/kingoftown/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/kingoftown/hibernate.c b/board/kingoftown/hibernate.c
index 504a295463..9b64e85053 100644
--- a/board/kingoftown/hibernate.c
+++ b/board/kingoftown/hibernate.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,6 @@ void board_hibernate(void)
 	 * Sensors are unpowered in hibernate. Apply PD to the
 	 * interrupt lines such that they don't float.
 	 */
-	gpio_set_flags(GPIO_ACCEL_GYRO_INT_L,
-		       GPIO_INPUT | GPIO_PULL_DOWN);
-	gpio_set_flags(GPIO_LID_ACCEL_INT_L,
-		       GPIO_INPUT | GPIO_PULL_DOWN);
+	gpio_set_flags(GPIO_ACCEL_GYRO_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
+	gpio_set_flags(GPIO_LID_ACCEL_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
 }
diff --git a/board/kingoftown/led.c b/board/kingoftown/led.c
index a543bb5403..2bbb0de0af 100644
--- a/board/kingoftown/led.c
+++ b/board/kingoftown/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -36,15 +36,15 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static void side_led_set_color(int port, enum led_color color)
 {
 	gpio_set_level(port ? GPIO_EC_CHG_LED_Y_C1 : GPIO_EC_CHG_LED_Y_C0,
-		(color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
+		       (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
 	gpio_set_level(port ? GPIO_EC_CHG_LED_W_C1 : GPIO_EC_CHG_LED_W_C0,
-		(color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF);
+		       (color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF);
 }
 
 void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
@@ -97,7 +97,6 @@ static void board_led_set_battery(void)
 	static int battery_ticks;
 	static int power_ticks;
 	int led_blink_cycle;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
@@ -107,15 +106,16 @@ static void board_led_set_battery(void)
 	 * charging.
 	 */
 	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
-            charge_get_state() != PWR_STATE_CHARGE) {
-
+	    charge_get_state() != PWR_STATE_CHARGE) {
 		power_ticks++;
 		led_blink_cycle = power_ticks % (2 * TIMES_TICK_ONE_SEC);
 
 		side_led_set_color(0, (led_blink_cycle < TIMES_TICK_ONE_SEC) ?
-								LED_WHITE : LED_OFF);
+					      LED_WHITE :
+					      LED_OFF);
 		side_led_set_color(1, (led_blink_cycle < TIMES_TICK_ONE_SEC) ?
-								LED_WHITE : LED_OFF);
+					      LED_WHITE :
+					      LED_OFF);
 		return;
 	}
 
@@ -128,15 +128,18 @@ static void board_led_set_battery(void)
 		break;
 	case PWR_STATE_DISCHARGE:
 		if (charge_get_percent() <= 10) {
-			led_blink_cycle = battery_ticks % (2 * TIMES_TICK_ONE_SEC);
+			led_blink_cycle =
+				battery_ticks % (2 * TIMES_TICK_ONE_SEC);
 			if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
-				side_led_set_color(1,
-					(led_blink_cycle < TIMES_TICK_ONE_SEC) ?
-							LED_AMBER : LED_OFF);
+				side_led_set_color(1, (led_blink_cycle <
+						       TIMES_TICK_ONE_SEC) ?
+							      LED_AMBER :
+							      LED_OFF);
 			if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
-				side_led_set_color(0,
-					(led_blink_cycle < TIMES_TICK_ONE_SEC) ?
-							LED_AMBER : LED_OFF);
+				side_led_set_color(0, (led_blink_cycle <
+						       TIMES_TICK_ONE_SEC) ?
+							      LED_AMBER :
+							      LED_OFF);
 		} else {
 			if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
 				side_led_set_color(1, LED_OFF);
@@ -147,23 +150,27 @@ static void board_led_set_battery(void)
 	case PWR_STATE_ERROR:
 		led_blink_cycle = battery_ticks % TIMES_TICK_ONE_SEC;
 		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
-			side_led_set_color(1, (led_blink_cycle < TIMES_TICK_HALF_SEC) ?
-								LED_AMBER : LED_OFF);
+			side_led_set_color(1, (led_blink_cycle <
+					       TIMES_TICK_HALF_SEC) ?
+						      LED_AMBER :
+						      LED_OFF);
 		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
-			side_led_set_color(0, (led_blink_cycle < TIMES_TICK_HALF_SEC) ?
-								LED_AMBER : LED_OFF);
+			side_led_set_color(0, (led_blink_cycle <
+					       TIMES_TICK_HALF_SEC) ?
+						      LED_AMBER :
+						      LED_OFF);
 		break;
 	case PWR_STATE_CHARGE_NEAR_FULL:
 		set_active_port_color(LED_WHITE);
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE) {
-			led_blink_cycle = battery_ticks % (2 * TIMES_TICK_ONE_SEC);
-			set_active_port_color(
-				(led_blink_cycle < TIMES_TICK_ONE_SEC) ?
-					LED_AMBER : LED_OFF);
-		} else
-			set_active_port_color(LED_WHITE);
+		set_active_port_color(LED_WHITE);
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		led_blink_cycle = battery_ticks % (2 * TIMES_TICK_ONE_SEC);
+		set_active_port_color((led_blink_cycle < TIMES_TICK_ONE_SEC) ?
+					      LED_AMBER :
+					      LED_OFF);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
diff --git a/board/kingoftown/switchcap.c b/board/kingoftown/switchcap.c
index 16b0db6ef6..5173e27f75 100644
--- a/board/kingoftown/switchcap.c
+++ b/board/kingoftown/switchcap.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/kingoftown/usbc_config.c b/board/kingoftown/usbc_config.c
index 9343fa2256..f0f17e93a9 100644
--- a/board/kingoftown/usbc_config.c
+++ b/board/kingoftown/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,8 +25,8 @@
 #include "usbc_ocp.h"
 #include "usbc_ppc.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 const struct charger_config_t chg_chips[] = {
 	{
@@ -132,16 +132,12 @@ void ppc_interrupt(enum gpio_signal signal)
 
 /* Power Path Controller */
 struct ppc_config_t ppc_chips[] = {
-	{
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	{
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
+	{ .i2c_port = I2C_PORT_TCPC0,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
+	{ .i2c_port = I2C_PORT_TCPC1,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
 };
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
@@ -172,16 +168,22 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
  * to AP. But the TCPC chip is also needed to know the HPD status; otherwise,
  * the mux misbehaves.
  */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	},
 	{
-		.usb_port = 1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	}
 };
 
@@ -234,7 +236,7 @@ void board_tcpc_init(void)
 	 */
 	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
 		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
 DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
 
@@ -280,8 +282,7 @@ void board_overcurrent_event(int port, int is_overcurrented)
 
 int board_set_active_charge_port(int port)
 {
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	int i;
 
 	if (!is_real_port && port != CHARGE_PORT_NONE)
@@ -309,7 +310,6 @@ int board_set_active_charge_port(int port)
 		return EC_ERROR_INVAL;
 	}
 
-
 	CPRINTS("New charge port: p%d", port);
 
 	/*
@@ -333,23 +333,21 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	/*
 	 * Ignore lower charge ceiling on PD transition if our battery is
 	 * critical, as we may brownout.
 	 */
-	if (supplier == CHARGE_SUPPLIER_PD &&
-	    charge_ma < 1500 &&
+	if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 &&
 	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
 		CPRINTS("Using max ilim %d", max_ma);
 		charge_ma = max_ma;
 	}
 
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 uint16_t tcpc_get_alert_status(void)
diff --git a/board/kingoftown/usbc_config.h b/board/kingoftown/usbc_config.h
index 654da35f74..7718aea74c 100644
--- a/board/kingoftown/usbc_config.h
+++ b/board/kingoftown/usbc_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/kinox/board.c b/board/kinox/board.c
index a814c7a20d..7c55fba876 100644
--- a/board/kinox/board.c
+++ b/board/kinox/board.c
@@ -1,9 +1,9 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include "assert.h"
+#include "builtin/assert.h"
 #include "button.h"
 #include "charge_manager.h"
 #include "charge_state_v2.h"
@@ -11,7 +11,6 @@
 #include "compile_time_macros.h"
 #include "console.h"
 #include "cros_board_info.h"
-#include "fw_config.h"
 #include "gpio.h"
 #include "gpio_signal.h"
 #include "power_button.h"
@@ -21,12 +20,13 @@
 #include "throttle_ap.h"
 #include "usbc_config.h"
 #include "usbc_ppc.h"
+#include "fw_config.h"
 
 #include "gpio_list.h" /* Must come after other header files. */
 
 /* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 /******************************************************************************/
 /* USB-A charging control */
@@ -40,8 +40,6 @@ BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT);
 
 int board_set_active_charge_port(int port)
 {
-	int rv;
-
 	CPRINTS("Requested charge port change to %d", port);
 
 	/*
@@ -64,15 +62,23 @@ int board_set_active_charge_port(int port)
 	if (board_vbus_source_enabled(port))
 		return EC_ERROR_INVAL;
 
-	/* Don't change the charge port */
-	if (charge_manager_get_active_charge_port() != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	/* Make sure BJ adapter is sourcing power */
-	if (port == CHARGE_PORT_BARRELJACK &&
-				gpio_get_level(GPIO_BJ_ADP_PRESENT_ODL)) {
-		CPRINTS("BJ port selected, but not present!");
-		return EC_ERROR_INVAL;
+	if (!chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
+		int bj_active, bj_requested;
+
+		if (charge_manager_get_active_charge_port() != CHARGE_PORT_NONE)
+			/* Change is only permitted while the system is off */
+			return EC_ERROR_INVAL;
+
+		/*
+		 * Current setting is no charge port but the AP is on, so the
+		 * charge manager is out of sync (probably because we're
+		 * reinitializing after sysjump). Reject requests that aren't
+		 * in sync with our outputs.
+		 */
+		bj_active = !gpio_get_level(GPIO_EN_PPVAR_BJ_ADP_L);
+		bj_requested = port == CHARGE_PORT_BARRELJACK;
+		if (bj_active != bj_requested)
+			return EC_ERROR_INVAL;
 	}
 
 	CPRINTS("New charger p%d", port);
@@ -80,19 +86,12 @@ int board_set_active_charge_port(int port)
 	switch (port) {
 	case CHARGE_PORT_TYPEC0:
 		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 1);
-		rv = ppc_vbus_sink_enable(CHARGE_PORT_TYPEC0, 1);
-		if (rv) {
-			CPRINTS("Failed to enable C0 sink path");
-			return rv;
-		}
 		break;
 	case CHARGE_PORT_BARRELJACK:
-		rv = ppc_vbus_sink_enable(CHARGE_PORT_TYPEC0, 0);
-		if (rv) {
-			CPRINTS("Failed to disable C0 sink path");
-			return rv;
-		}
-		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 0);
+		/* Make sure BJ adapter is sourcing power */
+		if (gpio_get_level(GPIO_BJ_ADP_PRESENT_ODL))
+			return EC_ERROR_INVAL;
+		ppc_vbus_sink_enable(0, 0);
 		break;
 	default:
 		return EC_ERROR_INVAL;
@@ -101,8 +100,8 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-				int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 }
 
@@ -122,5 +121,6 @@ DECLARE_HOOK(HOOK_INIT, adp_state_init, HOOK_PRIO_INIT_CHARGE_MANAGER + 1);
 
 static void board_init(void)
 {
+	gpio_enable_interrupt(GPIO_BJ_ADP_PRESENT_ODL);
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/kinox/board.h b/board/kinox/board.h
index 6637fbfec1..5e22e22269 100644
--- a/board/kinox/board.h
+++ b/board/kinox/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,37 +19,36 @@
 /* HDMI CEC */
 #define CONFIG_CEC
 #define CEC_GPIO_OUT GPIO_HDMI_CEC_OUT
-#define CEC_GPIO_IN  GPIO_HDMI_CEC_IN
+#define CEC_GPIO_IN GPIO_HDMI_CEC_IN
 #define CEC_GPIO_PULL_UP GPIO_HDMI_CEC_PULL_UP
 
 /* USB Type A Features */
-#define USB_PORT_COUNT			4
+#define USB_PORT_COUNT 4
 #define CONFIG_USB_PORT_POWER_DUMB
 
 /* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
-
 #define CONFIG_USB_PD_PPC
 #define CONFIG_USB_PD_TCPM_PS8815
 #define CONFIG_USB_PD_TCPM_PS8815_FORCE_DID
+#undef CONFIG_USB_PD_TCPM_NCT38XX
 
 #define CONFIG_USBC_PPC_SYV682X
 #undef CONFIG_SYV682X_HV_ILIM
 #define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_5_50
 
 /* TODO: b/177608416 - measure and check these values on brya */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
 
 /* The design should support up to 100W. */
 /* TODO(b/197702356): Set the max PD to 60W now and change it
  * to 100W after we verify it.
  */
-#define PD_OPERATING_POWER_MW	CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
-#define PD_MAX_POWER_MW		100000
-#define PD_MAX_CURRENT_MA	5000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
+#define PD_MAX_POWER_MW 100000
+#define PD_MAX_CURRENT_MA 5000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /*
  * Macros for GPIO signals used in common code that don't match the
@@ -57,52 +56,44 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_PACKET_MODE_EN		GPIO_EC_GSC_PACKET_MODE
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SYS_SLP_S0IX_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_TEMP_SENSOR_POWER		GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
 
 /*
  * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
  * signal.
  */
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_SEQ_EC_ALL_SYS_PG
-#define GPIO_PG_EC_DSW_PWROK		GPIO_SEQ_EC_DSW_PWROK
-#define GPIO_PG_EC_RSMRST_ODL		GPIO_SEQ_EC_RSMRST_ODL
-#define GPIO_POWER_BUTTON_L		GPIO_GSC_EC_PWR_BTN_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_ODL
-#define GPIO_RECOVERY_L			GPIO_EC_RECOVERY_BTN_OD
-#define GPIO_RECOVERY_L_2		GPIO_GSC_EC_RECOVERY_BTN_OD
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
+#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_OD
+#define GPIO_RECOVERY_L_2 GPIO_GSC_EC_RECOVERY_BTN_OD
 
 /* I2C Bus Configuration */
-#define I2C_PORT_USB_C0_PPC			NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C0_TCPC		NPCX_I2C_PORT4_1
-#define I2C_PORT_USB_C0_BC12		NPCX_I2C_PORT6_1
-
-#define I2C_PORT_EEPROM				NPCX_I2C_PORT7_0
+#define I2C_PORT_USB_C0_PPC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C0_TCPC NPCX_I2C_PORT4_1
+#define I2C_PORT_USB_C0_BC12 NPCX_I2C_PORT6_1
 
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
 
-#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR	0x58
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 
 /* I2C control host command */
 #define CONFIG_HOSTCMD_I2C_CONTROL
 
-/* Enabling Thunderbolt-compatible mode */
-#define CONFIG_USB_PD_TBT_COMPAT_MODE
-
-/* Enabling USB4 mode */
-#define CONFIG_USB_PD_USB4
-
 /* Thermal features */
 #define CONFIG_THERMISTOR
 #define CONFIG_TEMP_SENSOR
@@ -116,24 +107,18 @@
  * TODO(b/197478860): Enable the fan control. We need
  * to check the sensor value and adjust the fan speed.
  */
- #define CONFIG_FANS			FAN_CH_COUNT
+#define CONFIG_FANS FAN_CH_COUNT
 
 /* Include math_util for bitmask_uint64 used in pd_timers */
 #define CONFIG_MATH_UTIL
 
 #ifndef __ASSEMBLER__
 
-#include "gpio_signal.h"	/* needed by registers.h */
+#include "gpio_signal.h" /* needed by registers.h */
 #include "registers.h"
 #include "usbc_config.h"
 
-enum adp_id {
-	UNKNOWN,
-	TINY,
-	TIO1,
-	TIO2,
-	TYPEC
-};
+enum adp_id { UNKNOWN, TINY, TIO1, TIO2, TYPEC };
 
 struct adpater_id_params {
 	int min_voltage;
@@ -170,27 +155,20 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum ioex_port {
-	IOEX_C0_NCT38XX = 0,
-	IOEX_PORT_COUNT
-};
+enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_PORT_COUNT };
 
 enum pwm_channel {
-	PWM_CH_LED_GREEN,		/* PWM0 */
-	PWM_CH_FAN,                     /* PWM5 */
-	PWM_CH_LED_RED,                 /* PWM2 */
+	PWM_CH_LED_GREEN, /* PWM0 */
+	PWM_CH_FAN, /* PWM5 */
+	PWM_CH_LED_RED, /* PWM2 */
 	PWM_CH_COUNT
 };
 
-enum fan_channel {
-	FAN_CH_0 = 0,
-	FAN_CH_COUNT
-};
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT };
 
-enum mft_channel {
-	MFT_CH_0 = 0,
-	MFT_CH_COUNT
-};
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT };
+
+extern void adp_connect_interrupt(enum gpio_signal signal);
 
 #endif /* !__ASSEMBLER__ */
 
diff --git a/board/kinox/build.mk b/board/kinox/build.mk
index 440d137968..3eb2d2b2d5 100644
--- a/board/kinox/build.mk
+++ b/board/kinox/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/kinox/ec.tasklist b/board/kinox/ec.tasklist
index 025d8f86b4..6524d9c2b0 100644
--- a/board/kinox/ec.tasklist
+++ b/board/kinox/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/kinox/fans.c b/board/kinox/fans.c
index a82a61648d..cb65e95f62 100644
--- a/board/kinox/fans.c
+++ b/board/kinox/fans.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,7 +25,7 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 static const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP12000_FAN,
 };
@@ -37,9 +37,9 @@ static const struct fan_conf fan_conf_0 = {
  * Set minimum at around 30% PWM.
  */
 static const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 750,
-	.rpm_start = 750,
-	.rpm_max = 5200,
+	.rpm_min = 1000,
+	.rpm_start = 1000,
+	.rpm_max = 4200,
 };
 
 const struct fan_t fans[FAN_CH_COUNT] = {
diff --git a/board/kinox/fw_config.c b/board/kinox/fw_config.c
index 02f39e70f4..9736de1110 100644
--- a/board/kinox/fw_config.c
+++ b/board/kinox/fw_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,7 +10,7 @@
 #include "cros_board_info.h"
 #include "fw_config.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 static union kinox_cbi_fw_config fw_config;
 BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
diff --git a/board/kinox/fw_config.h b/board/kinox/fw_config.h
index 0d79d55376..a3efa7bfe9 100644
--- a/board/kinox/fw_config.h
+++ b/board/kinox/fw_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,11 +14,7 @@
  * Source of truth is the project/brask/kinox/config.star configuration file.
  */
 
-enum ec_cfg_dp_display {
-	ABSENT = 0,
-	DB_HDMI = 1,
-	DB_DP = 2
-};
+enum ec_cfg_dp_display { ABSENT = 0, DB_HDMI = 1, DB_DP = 2 };
 
 union kinox_cbi_fw_config {
 	struct {
diff --git a/board/kinox/gpio.inc b/board/kinox/gpio.inc
index d21782ba37..f3d94ebf07 100644
--- a/board/kinox/gpio.inc
+++ b/board/kinox/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2022 The Chromium OS Authors. All rights reserved.
+ * Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,6 +19,7 @@ GPIO_INT(SYS_SLP_S0IX_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_inte
 GPIO_INT(USB_C0_BC12_INT_ODL,        PIN(C, 6), GPIO_INT_FALLING, bc12_interrupt)
 GPIO_INT(USB_C0_PPC_INT_ODL,         PIN(F, 5), GPIO_INT_FALLING, ppc_interrupt)
 GPIO_INT(USB_C0_TCPC_INT_ODL,        PIN(A, 2), GPIO_INT_FALLING, tcpc_alert_event)
+GPIO_INT(BJ_ADP_PRESENT_ODL,         PIN(8, 2), GPIO_INT_BOTH | GPIO_PULL_UP, adp_connect_interrupt)
 GPIO_INT(EC_RECOVERY_BTN_OD,         PIN(2, 3), GPIO_INT_BOTH, button_interrupt)
 
 /* CCD */
@@ -29,7 +30,7 @@ GPIO(EC_ENTERING_RW,                 PIN(0, 3), GPIO_OUT_LOW)
 GPIO(EC_GSC_PACKET_MODE,             PIN(7, 5), GPIO_OUT_LOW)
 
 /* Fan */
-GPIO(EN_PP12000_FAN,                 PIN(6, 1), GPIO_OUT_HIGH)
+GPIO(EN_PP12000_FAN,                 PIN(6, 1), GPIO_OUT_LOW)
 
 /* Display */
 GPIO(DP_CONN_OC_ODL,                 PIN(2, 5), GPIO_INPUT)
@@ -37,7 +38,6 @@ GPIO(HDMI_CONN_OC_ODL,               PIN(2, 4), GPIO_INPUT)
 
 /* BarrelJack */
 GPIO(EN_PPVAR_BJ_ADP_L,              PIN(0, 7), GPIO_OUT_LOW)
-GPIO(BJ_ADP_PRESENT_ODL,             PIN(8, 2), GPIO_INPUT)
 
 /* Chipset PCH */
 GPIO(EC_PCHHOT_ODL,                  PIN(7, 4), GPIO_INPUT)
@@ -58,7 +58,7 @@ GPIO(CPU_C10_GATE_L,                 PIN(6, 7), GPIO_INPUT)
 GPIO(EC_PCH_PWR_BTN_ODL,             PIN(C, 1), GPIO_ODR_HIGH)
 GPIO(GSC_EC_RECOVERY_BTN_OD,         PIN(2, 2), GPIO_INPUT)
 
-GPIO(SIO_LEGO_EN,                    PIN(9, 6), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(SIO_LEGO_EN_L,                  PIN(9, 6), GPIO_OUT_LOW)
 
 /* HDMI CEC */
 /* TODO(b/197474873): Enable HDMI CEC */
diff --git a/board/kinox/i2c.c b/board/kinox/i2c.c
index d58deaa89a..0213134fcb 100644
--- a/board/kinox/i2c.c
+++ b/board/kinox/i2c.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/kinox/led.c b/board/kinox/led.c
index 00381fa7f4..d2a9a599cf 100644
--- a/board/kinox/led.c
+++ b/board/kinox/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,16 +19,16 @@
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
 
 /*
  * Due to the CSME-Lite processing, upon startup the CPU transitions through
  * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so
  * delay turning off the LED during suspend/shutdown.
  */
-#define LED_CPU_DELAY_MS	(2000 * MSEC)
+#define LED_CPU_DELAY_MS (2000 * MSEC)
 
-const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 enum led_color {
@@ -84,9 +84,9 @@ static int set_color(enum ec_led_id id, enum led_color color, int duty)
 	}
 }
 
-#define LED_PULSE_US		(2 * SECOND)
+#define LED_PULSE_US (2 * SECOND)
 /* 40 msec for nice and smooth transition. */
-#define LED_PULSE_TICK_US	(40 * MSEC)
+#define LED_PULSE_TICK_US (40 * MSEC)
 
 /*
  * When pulsing is enabled, brightness is incremented by <duty_inc> every
@@ -217,7 +217,7 @@ void show_critical_error(void)
 		set_color(EC_LED_ID_POWER_LED, LED_RED, 100);
 }
 
-static int command_led(int argc, char **argv)
+static int command_led(int argc, const char **argv)
 {
 	enum ec_led_id id = EC_LED_ID_POWER_LED;
 
@@ -242,8 +242,7 @@ static int command_led(int argc, char **argv)
 	}
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(led, command_led,
-			"[debug|red|green|off|alert|crit]",
+DECLARE_CONSOLE_COMMAND(led, command_led, "[debug|red|green|off|alert|crit]",
 			"Turn on/off LED.");
 
 void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
diff --git a/board/kinox/power_detection.c b/board/kinox/power_detection.c
index 54ca591252..c5b4a1a1ab 100644
--- a/board/kinox/power_detection.c
+++ b/board/kinox/power_detection.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,215 +17,211 @@
 #include "util.h"
 
 /* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 /******************************************************************************/
 
-static const char * const adp_id_names[] = {
-	"unknown",
-	"tiny",
-	"tio1",
-	"tio2",
-	"typec",
+static const char *const adp_id_names[] = {
+	"unknown", "tiny", "tio1", "tio2", "typec",
 };
 
 /* ADP_ID control */
 struct adpater_id_params tio1_power[] = {
 	{
-	.min_voltage = 3300,
-	.max_voltage = 3300,
-	.charge_voltage = 20000,
-	.charge_current = 6000,
-	.watt = 120,
-	.obp95 = 1990,
-	.obp85 = 1780,
+		.min_voltage = 2816,
+		.max_voltage = 2816,
+		.charge_voltage = 20000,
+		.charge_current = 6000,
+		.watt = 120,
+		.obp95 = 1990,
+		.obp85 = 1780,
 	},
 };
 
 struct adpater_id_params tio2_power[] = {
 	{
-	.min_voltage = 0,
-	.max_voltage = 68,
-	.charge_voltage = 20000,
-	.charge_current = 8500,
-	.watt = 170,
-	.obp95 = 2820,
-	.obp85 = 916,
+		.min_voltage = 0,
+		.max_voltage = 68,
+		.charge_voltage = 20000,
+		.charge_current = 8500,
+		.watt = 170,
+		.obp95 = 2820,
+		.obp85 = 916,
 	},
 	{
-	.min_voltage = 68,
-	.max_voltage = 142,
-	.charge_voltage = 20000,
-	.charge_current = 2250,
-	.watt = 45,
-	.obp95 = 750,
-	.obp85 = 670,
+		.min_voltage = 68,
+		.max_voltage = 142,
+		.charge_voltage = 20000,
+		.charge_current = 2250,
+		.watt = 45,
+		.obp95 = 750,
+		.obp85 = 670,
 	},
 	{
-	.min_voltage = 200,
-	.max_voltage = 288,
-	.charge_voltage = 20000,
-	.charge_current = 3250,
-	.watt = 65,
-	.obp95 = 1080,
-	.obp85 = 960,
+		.min_voltage = 200,
+		.max_voltage = 288,
+		.charge_voltage = 20000,
+		.charge_current = 3250,
+		.watt = 65,
+		.obp95 = 1080,
+		.obp85 = 960,
 	},
 	{
-	.min_voltage = 531,
-	.max_voltage = 607,
-	.charge_voltage = 20000,
-	.charge_current = 6000,
-	.watt = 120,
-	.obp95 = 1990,
-	.obp85 = 1780,
+		.min_voltage = 384,
+		.max_voltage = 480,
+		.charge_voltage = 20000,
+		.charge_current = 7500,
+		.watt = 150,
+		.obp95 = 2490,
+		.obp85 = 2220,
 	},
 	{
-	.min_voltage = 384,
-	.max_voltage = 480,
-	.charge_voltage = 20000,
-	.charge_current = 7500,
-	.watt = 150,
-	.obp95 = 2490,
-	.obp85 = 2220,
+		.min_voltage = 531,
+		.max_voltage = 607,
+		.charge_voltage = 20000,
+		.charge_current = 6000,
+		.watt = 120,
+		.obp95 = 1990,
+		.obp85 = 1780,
 	},
 	{
-	.min_voltage = 1062,
-	.max_voltage = 1126,
-	.charge_voltage = 20000,
-	.charge_current = 8500,
-	.watt = 170,
-	.obp95 = 2820,
-	.obp85 = 916,
+		.min_voltage = 1062,
+		.max_voltage = 1126,
+		.charge_voltage = 20000,
+		.charge_current = 8500,
+		.watt = 170,
+		.obp95 = 2820,
+		.obp85 = 916,
 	},
 	{
-	.min_voltage = 2816,
-	.max_voltage = 3300,
-	.charge_voltage = 20000,
-	.charge_current = 6000,
-	.watt = 120,
-	.obp95 = 1990,
-	.obp85 = 1780,
+		.min_voltage = 2816,
+		.max_voltage = 2816,
+		.charge_voltage = 20000,
+		.charge_current = 6000,
+		.watt = 120,
+		.obp95 = 1990,
+		.obp85 = 1780,
 	},
 };
 
 struct adpater_id_params tiny_power[] = {
 	{
-	.min_voltage = 68,
-	.max_voltage = 142,
-	.charge_voltage = 20000,
-	.charge_current = 2250,
-	.watt = 45,
-	.obp95 = 750,
-	.obp85 = 670,
+		.min_voltage = 68,
+		.max_voltage = 142,
+		.charge_voltage = 20000,
+		.charge_current = 2250,
+		.watt = 45,
+		.obp95 = 750,
+		.obp85 = 670,
 	},
 	{
-	.min_voltage = 200,
-	.max_voltage = 288,
-	.charge_voltage = 20000,
-	.charge_current = 3250,
-	.watt = 65,
-	.obp95 = 1080,
-	.obp85 = 960,
+		.min_voltage = 200,
+		.max_voltage = 288,
+		.charge_voltage = 20000,
+		.charge_current = 3250,
+		.watt = 65,
+		.obp95 = 1080,
+		.obp85 = 960,
 	},
 	{
-	.min_voltage = 384,
-	.max_voltage = 480,
-	.charge_voltage = 20000,
-	.charge_current = 4500,
-	.watt = 90,
-	.obp95 = 1490,
-	.obp85 = 1330,
+		.min_voltage = 384,
+		.max_voltage = 480,
+		.charge_voltage = 20000,
+		.charge_current = 4500,
+		.watt = 90,
+		.obp95 = 1490,
+		.obp85 = 1330,
 	},
 	{
-	.min_voltage = 531,
-	.max_voltage = 607,
-	.charge_voltage = 20000,
-	.charge_current = 6000,
-	.watt = 120,
-	.obp95 = 0x2D3,
-	.obp85 = 0x286,
+		.min_voltage = 531,
+		.max_voltage = 607,
+		.charge_voltage = 20000,
+		.charge_current = 6000,
+		.watt = 120,
+		.obp95 = 0x2D3,
+		.obp85 = 0x286,
 	},
 	{
-	.min_voltage = 653,
-	.max_voltage = 783,
-	.charge_voltage = 20000,
-	.charge_current = 6750,
-	.watt = 135,
-	.obp95 = 2240,
-	.obp85 = 2000,
+		.min_voltage = 653,
+		.max_voltage = 783,
+		.charge_voltage = 20000,
+		.charge_current = 6750,
+		.watt = 135,
+		.obp95 = 2240,
+		.obp85 = 2000,
 	},
 	{
-	.min_voltage = 851,
-	.max_voltage = 997,
-	.charge_voltage = 20000,
-	.charge_current = 7500,
-	.watt = 150,
-	.obp95 = 2490,
-	.obp85 = 2220,
+		.min_voltage = 851,
+		.max_voltage = 997,
+		.charge_voltage = 20000,
+		.charge_current = 7500,
+		.watt = 150,
+		.obp95 = 2490,
+		.obp85 = 2220,
 	},
 	{
-	.min_voltage = 1063,
-	.max_voltage = 1226,
-	.charge_voltage = 20000,
-	.charge_current = 8500,
-	.watt = 170,
-	.obp95 = 2820,
-	.obp85 = 916,
+		.min_voltage = 1063,
+		.max_voltage = 1226,
+		.charge_voltage = 20000,
+		.charge_current = 8500,
+		.watt = 170,
+		.obp95 = 2820,
+		.obp85 = 916,
 	},
 	{
-	.min_voltage = 1749,
-	.max_voltage = 1968,
-	.charge_voltage = 20000,
-	.charge_current = 11500,
-	.watt = 230,
-	.obp95 = 3810,
-	.obp85 = 3410,
+		.min_voltage = 1749,
+		.max_voltage = 1968,
+		.charge_voltage = 20000,
+		.charge_current = 11500,
+		.watt = 230,
+		.obp95 = 3810,
+		.obp85 = 3410,
 	},
 };
 
 struct adpater_id_params typec_power[] = {
 	{
-	.charge_voltage = 20000,
-	.charge_current = 1500,
-	.watt = 30,
-	.obp95 = 500,
-	.obp85 = 440,
+		.charge_voltage = 20000,
+		.charge_current = 1500,
+		.watt = 30,
+		.obp95 = 500,
+		.obp85 = 440,
 	},
 	{
-	.charge_voltage = 15000,
-	.charge_current = 2000,
-	.watt = 30,
-	.obp95 = 660,
-	.obp85 = 590,
+		.charge_voltage = 15000,
+		.charge_current = 2000,
+		.watt = 30,
+		.obp95 = 660,
+		.obp85 = 590,
 	},
 	{
-	.charge_voltage = 20000,
-	.charge_current = 2250,
-	.watt = 45,
-	.obp95 = 750,
-	.obp85 = 670,
+		.charge_voltage = 20000,
+		.charge_current = 2250,
+		.watt = 45,
+		.obp95 = 750,
+		.obp85 = 670,
 	},
 	{
-	.charge_voltage = 15000,
-	.charge_current = 3000,
-	.watt = 45,
-	.obp95 = 990,
-	.obp85 = 890,
+		.charge_voltage = 15000,
+		.charge_current = 3000,
+		.watt = 45,
+		.obp95 = 990,
+		.obp85 = 890,
 	},
 	{
-	.charge_voltage = 20000,
-	.charge_current = 3250,
-	.watt = 65,
-	.obp95 = 1080,
-	.obp85 = 960,
+		.charge_voltage = 20000,
+		.charge_current = 3250,
+		.watt = 65,
+		.obp95 = 1080,
+		.obp85 = 960,
 	},
 	{
-	.charge_voltage = 20000,
-	.charge_current = 5000,
-	.watt = 100,
-	.obp95 = 1660,
-	.obp85 = 1480,
+		.charge_voltage = 20000,
+		.charge_current = 5000,
+		.watt = 100,
+		.obp95 = 1660,
+		.obp85 = 1480,
 	},
 };
 
@@ -241,7 +237,7 @@ void obp_point_95(void)
 
 	/* Trigger the PROCHOT */
 	gpio_set_level(GPIO_EC_PROCHOT_ODL, 0);
-	CPRINTF("Adapter voltage over then 95%% trigger prochot.");
+	CPRINTS("Adapter voltage over 95%% trigger prochot.");
 }
 
 void obp_point_85(void)
@@ -253,20 +249,20 @@ void obp_point_85(void)
 
 	/* Release the PROCHOT */
 	gpio_set_level(GPIO_EC_PROCHOT_ODL, 1);
-	CPRINTF("Adapter voltage less then 85%% release prochot.");
+	CPRINTS("Adapter voltage lower than 85%% release prochot.");
 }
 
 struct npcx_adc_thresh_t adc_obp_point_95 = {
 	.adc_ch = ADC_PWR_IN_IMON,
 	.adc_thresh_cb = obp_point_95,
-	.thresh_assert = 3300,	/* Default */
+	.thresh_assert = 3300, /* Default */
 };
 
 struct npcx_adc_thresh_t adc_obp_point_85 = {
 	.adc_ch = ADC_PWR_IN_IMON,
 	.adc_thresh_cb = obp_point_85,
 	.lower_or_higher = 1,
-	.thresh_assert = 0,	/* Default */
+	.thresh_assert = 0, /* Default */
 };
 
 static void set_up_adc_irqs(void)
@@ -295,14 +291,16 @@ void set_the_obp(int power_type_index, int adp_type)
 		switch (adp_type) {
 		case TIO1:
 		case TIO2:
+			gpio_set_level(GPIO_SIO_LEGO_EN_L, 0);
 			charge_manager_update_charge(
-						CHARGE_SUPPLIER_PROPRIETARY,
-						DEDICATED_CHARGE_PORT, &pi);
+				CHARGE_SUPPLIER_PROPRIETARY,
+				DEDICATED_CHARGE_PORT, &pi);
 			break;
 		case TINY:
-			charge_manager_update_charge(
-						CHARGE_SUPPLIER_DEDICATED,
-						DEDICATED_CHARGE_PORT, &pi);
+			gpio_set_level(GPIO_SIO_LEGO_EN_L, 1);
+			charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED,
+						     DEDICATED_CHARGE_PORT,
+						     &pi);
 			break;
 		}
 	}
@@ -323,10 +321,10 @@ void set_the_obp(int power_type_index, int adp_type)
  *  |            |                |
  *  |---220 ms---|-----400 ms-----|
  *
- * Tiny: Twice adapter ADC values are less than 0x3FF.
- * TIO1: Twice adapter ADC values are 0x3FF.
- * TIO2: First adapter ADC value less than 0x3FF.
- *       Second adpater ADC value is 0x3FF.
+ * Tiny: Twice adapter ADC values are less than 2.816v.
+ * TIO1: Twice adapter ADC values are 2.816v.
+ * TIO2: First adapter ADC value less than 2.816v.
+ *       Second adpater ADC value is 2.816v.
  */
 static void adp_id_deferred(void);
 DECLARE_DEFERRED(adp_id_deferred);
@@ -344,36 +342,39 @@ void adp_id_deferred(void)
 		adp_id_value_debounce = adp_id_value;
 		/* for delay the 400ms to get the next APD_ID value */
 		hook_call_deferred(&adp_id_deferred_data, 400 * MSEC);
-	} else if (adp_id_value_debounce == 0x3FF && adp_id_value == 0x3FF) {
+	} else if (adp_id_value_debounce == ADC_MAX_VOLT &&
+		   adp_id_value == ADC_MAX_VOLT) {
 		adp_finial_adc_value = adp_id_value;
 		adp_type = TIO1;
-	} else if (adp_id_value_debounce < 0x3FF && adp_id_value == 0x3FF) {
+	} else if (adp_id_value_debounce < ADC_MAX_VOLT &&
+		   adp_id_value == ADC_MAX_VOLT) {
 		adp_finial_adc_value = adp_id_value_debounce;
 		adp_type = TIO2;
-	} else if (adp_id_value_debounce < 0x3FF && adp_id_value < 0x3FF) {
+	} else if (adp_id_value_debounce < ADC_MAX_VOLT &&
+		   adp_id_value < ADC_MAX_VOLT) {
 		adp_finial_adc_value = adp_id_value;
 		adp_type = TINY;
 	} else {
 		CPRINTS("ADP_ID mismatch anything!");
-		/* Set the default 65w adaptor max ADC value */
-		adp_finial_adc_value = 0x69;
+		/* Set the default TINY 45w adapter */
+		adp_finial_adc_value = 142;
 		adp_type = TINY;
 	}
 
 	switch (adp_type) {
 	case TIO1:
-		power_type_len = sizeof(tio1_power) /
-					sizeof(struct adpater_id_params);
+		power_type_len =
+			sizeof(tio1_power) / sizeof(struct adpater_id_params);
 		memcpy(&power_type, &tio1_power, sizeof(tio1_power));
 		break;
 	case TIO2:
-		power_type_len = sizeof(tio2_power) /
-					sizeof(struct adpater_id_params);
+		power_type_len =
+			sizeof(tio2_power) / sizeof(struct adpater_id_params);
 		memcpy(&power_type, &tio2_power, sizeof(tio2_power));
 		break;
 	case TINY:
-		power_type_len = sizeof(tiny_power) /
-					sizeof(struct adpater_id_params);
+		power_type_len =
+			sizeof(tiny_power) / sizeof(struct adpater_id_params);
 		memcpy(&power_type, &tiny_power, sizeof(tiny_power));
 		break;
 	}
@@ -388,10 +389,19 @@ void adp_id_deferred(void)
 
 static void barrel_jack_setting(void)
 {
+	struct charge_port_info pi = { 0 };
 	/* Check ADP_ID when barrel jack is present */
-	if (!gpio_get_level(GPIO_BJ_ADP_PRESENT_ODL))
+	if (!gpio_get_level(GPIO_BJ_ADP_PRESENT_ODL)) {
+		/* Set the default TINY 45w adapter */
+		pi.voltage = 20000;
+		pi.current = 2250;
+
+		charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED,
+					     DEDICATED_CHARGE_PORT, &pi);
+
 		/* Delay 220ms to get the first ADP_ID value */
 		hook_call_deferred(&adp_id_deferred_data, 220 * MSEC);
+	}
 }
 DECLARE_HOOK(HOOK_INIT, barrel_jack_setting, HOOK_PRIO_DEFAULT);
 
@@ -405,13 +415,13 @@ static void typec_adapter_setting(void)
 	/* Check the barrel jack is not present */
 	if (gpio_get_level(GPIO_BJ_ADP_PRESENT_ODL)) {
 		adapter_current_ma = charge_manager_get_charger_current();
-		power_type_len = sizeof(typec_power) /
-					sizeof(struct adpater_id_params);
+		power_type_len =
+			sizeof(typec_power) / sizeof(struct adpater_id_params);
 
 		memcpy(&power_type, &typec_power, sizeof(typec_power));
 		for (i = (power_type_len - 1); i >= 0; i--) {
 			if (adapter_current_ma >=
-				power_type[i].charge_current) {
+			    power_type[i].charge_current) {
 				set_the_obp(i, adp_type);
 				break;
 			}
@@ -419,3 +429,10 @@ static void typec_adapter_setting(void)
 	}
 }
 DECLARE_HOOK(HOOK_CHIPSET_RESUME, typec_adapter_setting, HOOK_PRIO_DEFAULT);
+
+/* IRQ for BJ plug/unplug. It shouldn't be called if BJ is the power source. */
+void adp_connect_interrupt(enum gpio_signal signal)
+{
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		hook_call_deferred(&adp_id_deferred_data, 0);
+}
diff --git a/board/kinox/pwm.c b/board/kinox/pwm.c
index 112ee62c8c..ce1f83e187 100644
--- a/board/kinox/pwm.c
+++ b/board/kinox/pwm.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,34 +11,23 @@
 #include "pwm_chip.h"
 
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED_GREEN] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 2000
-	},
-	[PWM_CH_FAN] = {
-		.channel = 5,
-		.flags = PWM_CONFIG_OPEN_DRAIN,
-		.freq = 25000
-	},
-	[PWM_CH_LED_RED] = {
-		.channel = 2,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 2000
-	},
+	[PWM_CH_LED_GREEN] = { .channel = 0,
+			       .flags = PWM_CONFIG_ACTIVE_LOW |
+					PWM_CONFIG_DSLEEP |
+					PWM_CONFIG_OPEN_DRAIN,
+			       .freq = 2000 },
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
+	[PWM_CH_LED_RED] = { .channel = 2,
+			     .flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+			     .freq = 2000 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
 static void board_pwm_init(void)
 {
-	/*
-	 * TODO(b/197478860): Turn on the fan at 100% by default
-	 * We need to find tune the fan speed according to the
-	 * thermal sensor value.
-	 */
 	pwm_enable(PWM_CH_FAN, 1);
-	pwm_set_duty(PWM_CH_FAN, 100);
-
 	pwm_enable(PWM_CH_LED_RED, 1);
 	pwm_enable(PWM_CH_LED_GREEN, 1);
 }
diff --git a/board/kinox/sensors.c b/board/kinox/sensors.c
index e444664e8f..86c60b1427 100644
--- a/board/kinox/sensors.c
+++ b/board/kinox/sensors.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -56,37 +56,29 @@ const struct adc_t adc_channels[] = {
 		.name = "ADP_ID",
 		.input_ch = NPCX_ADC_CH4,
 		.factor_mul = ADC_MAX_VOLT,
-		.factor_div = ADC_READ_MAX + 1,
+		.factor_div = ADC_READ_MAX,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* Temperature sensor configuration */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1_CPU] = {
-		.name = "CPU",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_1_CPU
-	},
-	[TEMP_SENSOR_2_CPU_VR] = {
-		.name = "CPU VR",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_2_CPU_VR
-	},
-	[TEMP_SENSOR_3_WIFI] = {
-		.name = "WIFI",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_3_WIFI
-	},
-	[TEMP_SENSOR_4_DIMM] = {
-		.name = "DIMM",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_4_DIMM
-	},
+	[TEMP_SENSOR_1_CPU] = { .name = "CPU",
+				.type = TEMP_SENSOR_TYPE_BOARD,
+				.read = get_temp_3v3_30k9_47k_4050b,
+				.idx = ADC_TEMP_SENSOR_1_CPU },
+	[TEMP_SENSOR_2_CPU_VR] = { .name = "CPU VR",
+				   .type = TEMP_SENSOR_TYPE_BOARD,
+				   .read = get_temp_3v3_30k9_47k_4050b,
+				   .idx = ADC_TEMP_SENSOR_2_CPU_VR },
+	[TEMP_SENSOR_3_WIFI] = { .name = "WIFI",
+				 .type = TEMP_SENSOR_TYPE_BOARD,
+				 .read = get_temp_3v3_30k9_47k_4050b,
+				 .idx = ADC_TEMP_SENSOR_3_WIFI },
+	[TEMP_SENSOR_4_DIMM] = { .name = "DIMM",
+				 .type = TEMP_SENSOR_TYPE_BOARD,
+				 .read = get_temp_3v3_30k9_47k_4050b,
+				 .idx = ADC_TEMP_SENSOR_4_DIMM },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -100,8 +92,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CPU \
-	{ \
+#define THERMAL_CPU              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = 0, \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(95), \
@@ -112,8 +104,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(90), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(90), \
 		}, \
-		.temp_fan_off = C_TO_K(35), \
-		.temp_fan_max = C_TO_K(65), \
+		.temp_fan_off = C_TO_K(25), \
+		.temp_fan_max = C_TO_K(75), \
 	}
 __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 
diff --git a/board/kinox/usbc_config.c b/board/kinox/usbc_config.c
index a5c171bede..feeb3be6d1 100644
--- a/board/kinox/usbc_config.c
+++ b/board/kinox/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -28,8 +28,8 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 /* USBC TCPC configuration */
 const struct tcpc_config_t tcpc_config[] = {
@@ -61,19 +61,24 @@ BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
 /* USBC mux configuration - Alder Lake includes internal mux */
-static const struct usb_mux usbc0_usb3_retimer = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+static const struct usb_mux_chain usbc0_usb3_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 };
 
-const struct usb_mux usb_muxes[] = {
+const struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		/* PS8815 */
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc0_usb3_retimer,
+		.mux = &(const struct usb_mux) {
+			/* PS8815 */
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc0_usb3_retimer,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
diff --git a/board/kinox/usbc_config.h b/board/kinox/usbc_config.h
index b294eb69c8..7a212f8fb6 100644
--- a/board/kinox/usbc_config.h
+++ b/board/kinox/usbc_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,11 +8,8 @@
 #ifndef __CROS_EC_USBC_CONFIG_H
 #define __CROS_EC_USBC_CONFIG_H
 
-#define CONFIG_USB_PD_PORT_MAX_COUNT	1
+#define CONFIG_USB_PD_PORT_MAX_COUNT 1
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_COUNT };
 
 #endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/kodama/battery.c b/board/kodama/battery.c
index 1dbff92a00..1c6737bd3a 100644
--- a/board/kodama/battery.c
+++ b/board/kodama/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,7 +14,7 @@
 #include "usb_pd.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 const struct board_batt_params board_battery_info[] = {
 	[BATTERY_SIMPLO] = {
@@ -95,9 +95,9 @@ int charger_profile_override(struct charge_state_data *curr)
 	 * When smart battery temperature is more than 45 deg C, the max
 	 * charging voltage is 4100mV.
 	 */
-	if (curr->state == ST_CHARGE && bat_temp_c >= 450
-		&& !(curr->batt.flags & BATT_FLAG_BAD_TEMPERATURE))
-		curr->requested_voltage	= 4100;
+	if (curr->state == ST_CHARGE && bat_temp_c >= 450 &&
+	    !(curr->batt.flags & BATT_FLAG_BAD_TEMPERATURE))
+		curr->requested_voltage = 4100;
 	else
 		curr->requested_voltage = batt_info->voltage_max;
 
diff --git a/board/kodama/board.c b/board/kodama/board.c
index 2fa3ae8a3e..5ebcf00d40 100644
--- a/board/kodama/board.c
+++ b/board/kodama/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,6 +25,7 @@
 #include "i2c.h"
 #include "i2c_bitbang.h"
 #include "lid_switch.h"
+#include "panic.h"
 #include "power.h"
 #include "power_button.h"
 #include "pwm.h"
@@ -40,8 +41,8 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
@@ -53,56 +54,50 @@ static void tcpc_alert_event(enum gpio_signal signal)
 /******************************************************************************/
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] = {"BOARD_ID", 3300, 4096, 0, STM32_AIN(10)},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)},
-	[ADC_POGO_ADC_INT_L] = {"POGO_ADC_INT_L", 3300, 4096, 0, STM32_AIN(6)},
+	[ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(10) },
+	[ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8) },
+	[ADC_POGO_ADC_INT_L] = { "POGO_ADC_INT_L", 3300, 4096, 0,
+				 STM32_AIN(6) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /******************************************************************************/
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "typec",
-		.port = 0,
-		.kbps = 400,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	},
-	{
-		.name = "other",
-		.port = 1,
-		.kbps = 400,
-		.scl  = GPIO_I2C2_SCL,
-		.sda  = GPIO_I2C2_SDA,
-		.flags = I2C_PORT_FLAG_DYNAMIC_SPEED
-	},
+	{ .name = "typec",
+	  .port = 0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "other",
+	  .port = 1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA,
+	  .flags = I2C_PORT_FLAG_DYNAMIC_SPEED },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
 const struct i2c_port_t i2c_bitbang_ports[] = {
-	{
-		.name = "battery",
-		.port = 2,
-		.kbps = 100,
-		.scl  = GPIO_I2C3_SCL,
-		.sda  = GPIO_I2C3_SDA,
-		.drv = &bitbang_drv
-	},
+	{ .name = "battery",
+	  .port = 2,
+	  .kbps = 100,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA,
+	  .drv = &bitbang_drv },
 };
 const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
 
 /* power signal list.  Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
+	{ GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" },
+	{ GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" },
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
 /******************************************************************************/
 /* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
+const struct spi_device_t spi_devices[] = {};
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
 /******************************************************************************/
@@ -122,8 +117,7 @@ struct mt6370_thermal_bound thermal_bound = {
 	.err = 4,
 };
 
-static void board_hpd_status(const struct usb_mux *me,
-			     mux_state_t mux_state,
+static void board_hpd_status(const struct usb_mux *me, mux_state_t mux_state,
 			     bool *ack_required)
 {
 	/* This driver does not use host command ACKs */
@@ -136,7 +130,6 @@ static void board_hpd_status(const struct usb_mux *me,
 	host_set_single_event(EC_HOST_EVENT_USB_MUX);
 }
 
-
 __override const struct rt946x_init_setting *board_rt946x_init_setting(void)
 {
 	static const struct rt946x_init_setting battery_init_setting = {
@@ -151,13 +144,16 @@ __override const struct rt946x_init_setting *board_rt946x_init_setting(void)
 	return &battery_init_setting;
 }
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+				.hpd_update = &board_hpd_status,
+			},
 	},
 };
 
@@ -238,9 +234,8 @@ int extpower_is_present(void)
 	if (board_vbus_source_enabled(CHARGE_PORT_USB_C))
 		usb_c_extpower_present = 0;
 	else
-		usb_c_extpower_present = tcpm_check_vbus_level(
-							CHARGE_PORT_USB_C,
-							VBUS_PRESENT);
+		usb_c_extpower_present =
+			tcpm_check_vbus_level(CHARGE_PORT_USB_C, VBUS_PRESENT);
 
 	return usb_c_extpower_present;
 }
@@ -260,11 +255,11 @@ static void board_init(void)
 #ifdef SECTION_IS_RW
 	int val;
 
-	i2c_read8(I2C_PORT_CHARGER, CHARGER_I2C_ADDR_FLAGS,
-			RT946X_REG_CHGCTRL1, &val);
+	i2c_read8(I2C_PORT_CHARGER, CHARGER_I2C_ADDR_FLAGS, RT946X_REG_CHGCTRL1,
+		  &val);
 	val &= RT946X_MASK_OPA_MODE;
 	i2c_write8(I2C_PORT_CHARGER, CHARGER_I2C_ADDR_FLAGS,
-		RT946X_REG_CHGCTRL1, (val | RT946X_MASK_STAT_EN));
+		   RT946X_REG_CHGCTRL1, (val | RT946X_MASK_STAT_EN));
 #endif
 
 	/* If the reset cause is external, pulse PMIC force reset. */
@@ -317,7 +312,7 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 static void board_i2c_init(void)
 {
 	if (board_get_version() < 2)
-		i2c_set_freq(1,  I2C_FREQ_100KHZ);
+		i2c_set_freq(1, I2C_FREQ_100KHZ);
 }
 DECLARE_HOOK(HOOK_INIT, board_i2c_init, HOOK_PRIO_INIT_I2C);
 
@@ -329,11 +324,9 @@ static struct mutex g_lid_mutex;
 static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
 
 /* Matrix to rotate accelerometer into standard reference frame */
-static const mat33_fp_t lid_standard_ref = {
-	{0, FLOAT_TO_FP(1), 0},
-	{FLOAT_TO_FP(-1), 0, 0},
-	{0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					     { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
diff --git a/board/kodama/board.h b/board/kodama/board.h
index de953cba0b..b16e9f84a7 100644
--- a/board/kodama/board.h
+++ b/board/kodama/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,7 +15,6 @@
 #define VARIANT_KUKUI_TABLET_PWRBTN
 #undef CONFIG_CMD_MFALLOW
 
-
 #ifndef SECTION_IS_RW
 #define VARIANT_KUKUI_NO_SENSORS
 #endif /* SECTION_IS_RW */
@@ -39,7 +38,7 @@
 #define CONFIG_SMBUS_PEC
 
 /* Battery */
-#define BATTERY_DESIRED_CHARGING_CURRENT    2000  /* mA */
+#define BATTERY_DESIRED_CHARGING_CURRENT 2000 /* mA */
 
 #define CONFIG_CHARGER_MT6370_BACKLIGHT
 #define CONFIG_CHARGER_MAINTAIN_VBAT
@@ -53,19 +52,18 @@
 /* Camera VSYNC */
 #define CONFIG_SYNC
 #define CONFIG_SYNC_COMMAND
-#define CONFIG_SYNC_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
+#define CONFIG_SYNC_INT_EVENT TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
 #endif /* SECTION_IS_RW */
 
 /* Disable verbose output in EC pd */
 #define CONFIG_CMD_PD_SRCCAPS_REDUCED_SIZE
 
 /* I2C ports */
-#define I2C_PORT_CHARGER  0
-#define I2C_PORT_TCPC0    0
-#define I2C_PORT_USB_MUX  0
-#define I2C_PORT_ACCEL    1
-#define I2C_PORT_BATTERY  board_get_battery_i2c()
+#define I2C_PORT_CHARGER 0
+#define I2C_PORT_TCPC0 0
+#define I2C_PORT_USB_MUX 0
+#define I2C_PORT_ACCEL 1
+#define I2C_PORT_BATTERY board_get_battery_i2c()
 #define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
 
 /* Define the host events which are allowed to wakeup AP in S3. */
diff --git a/board/kodama/build.mk b/board/kodama/build.mk
index 0b3565fd84..6a7e557a0e 100644
--- a/board/kodama/build.mk
+++ b/board/kodama/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/kodama/ec.tasklist b/board/kodama/ec.tasklist
index f71a208dd6..e66c52616b 100644
--- a/board/kodama/ec.tasklist
+++ b/board/kodama/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/kodama/gpio.inc b/board/kodama/gpio.inc
index 75a3db7d20..d72532ff70 100644
--- a/board/kodama/gpio.inc
+++ b/board/kodama/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/kodama/led.c b/board/kodama/led.c
index d96b340d73..d6c4297a44 100644
--- a/board/kodama/led.c
+++ b/board/kodama/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,45 +11,48 @@
 #include "led_onoff_states.h"
 #include "ec_commands.h"
 
-#define LED_RED		MT6370_LED_ID1
-#define LED_GREEN	MT6370_LED_ID2
-#define LED_WHITE	MT6370_LED_ID3
+#define LED_RED MT6370_LED_ID1
+#define LED_GREEN MT6370_LED_ID2
+#define LED_WHITE MT6370_LED_ID3
 
-#define LED_MASK_OFF	0
-#define LED_MASK_RED	MT6370_MASK_RGB_ISNK1DIM_EN
-#define LED_MASK_GREEN	MT6370_MASK_RGB_ISNK2DIM_EN
-#define LED_MASK_WHITE	MT6370_MASK_RGB_ISNK3DIM_EN
+#define LED_MASK_OFF 0
+#define LED_MASK_RED MT6370_MASK_RGB_ISNK1DIM_EN
+#define LED_MASK_GREEN MT6370_MASK_RGB_ISNK2DIM_EN
+#define LED_MASK_WHITE MT6370_MASK_RGB_ISNK3DIM_EN
 
 __override const int led_charge_lvl_1 = 5;
 __override const int led_charge_lvl_2 = 97;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
 
 __override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-					{LED_OFF,	   LED_ONE_SEC / 2} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-	EC_LED_ID_BATTERY_LED
-};
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 3 * LED_ONE_SEC },
+					       { LED_OFF, LED_ONE_SEC / 2 } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED,
+					     EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
diff --git a/board/kohaku/battery.c b/board/kohaku/battery.c
index 8d35008f6e..693c5b5221 100644
--- a/board/kohaku/battery.c
+++ b/board/kohaku/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/kohaku/board.c b/board/kohaku/board.c
index bf22dd6d41..42a5304353 100644
--- a/board/kohaku/board.c
+++ b/board/kohaku/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -41,8 +41,8 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void ppc_interrupt(enum gpio_signal signal)
 {
@@ -98,14 +98,13 @@ static void bc12_interrupt(enum gpio_signal signal)
 
 /******************************************************************************/
 /* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
+const struct spi_device_t spi_devices[] = {};
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
 /******************************************************************************/
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT]   = { .channel = 3, .flags = 0, .freq = 10000 },
+	[PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
@@ -130,16 +129,20 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_TCPC_0] = {
-		.usb_port = USB_PD_PORT_TCPC_0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_0,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 	},
 	[USB_PD_PORT_TCPC_1] = {
-		.usb_port = USB_PD_PORT_TCPC_1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 	}
 };
 
@@ -223,11 +226,9 @@ static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
 };
 
 /* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					      { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
@@ -383,34 +384,34 @@ BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
 /**********************************************************************/
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		"TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_2] = {
-		"TEMP_AMB", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_3] = {
-		"TEMP_GT", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_4] = {
-		"TEMP_IA", NPCX_ADC_CH3, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_1] = { "TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_2] = { "TEMP_AMB", NPCX_ADC_CH1, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_3] = { "TEMP_GT", NPCX_ADC_CH2, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_4] = { "TEMP_IA", NPCX_ADC_CH3, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "GT",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_3},
-	[TEMP_SENSOR_4] = {.name = "IA",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_4},
+	[TEMP_SENSOR_1] = { .name = "Charger",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "GT",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
+	[TEMP_SENSOR_4] = { .name = "IA",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_4 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -423,8 +424,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_A \
-	{ \
+#define THERMAL_A                \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = 0, \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
diff --git a/board/kohaku/board.h b/board/kohaku/board.h
index de87000f34..d120e308aa 100644
--- a/board/kohaku/board.h
+++ b/board/kohaku/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -35,8 +35,7 @@
 #define CONFIG_ACCELGYRO_BMI160_INT2_OUTPUT
 /* Camera VSYNC */
 #define CONFIG_SYNC
-#define CONFIG_SYNC_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
+#define CONFIG_SYNC_INT_EVENT TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
 /* BMA253 Lid accel */
 #define CONFIG_ACCEL_BMA255
 #define CONFIG_LID_ANGLE
@@ -46,7 +45,7 @@
 /* BH1730 and TCS3400 ALS */
 #define CONFIG_ALS
 #define ALS_COUNT 2
-#define I2C_PORT_ALS      I2C_PORT_SENSOR
+#define I2C_PORT_ALS I2C_PORT_SENSOR
 #define CONFIG_ALS_BH1730
 #define CONFIG_ALS_TCS3400
 #define CONFIG_ALS_TCS3400_INT_EVENT \
@@ -70,18 +69,18 @@
  * Kohaku will not use both BH1730_LUXTH3_1K condition
  * and BH1730_LUXTH4_1K condition.
  */
-#define BH1730_LUXTH1_1K                270
-#define BH1730_LUXTH1_D0_1K             19200
-#define BH1730_LUXTH1_D1_1K             30528
-#define BH1730_LUXTH2_1K                655360000
-#define BH1730_LUXTH2_D0_1K             11008
-#define BH1730_LUXTH2_D1_1K             10752
-#define BH1730_LUXTH3_1K                1030
-#define BH1730_LUXTH3_D0_1K             11008
-#define BH1730_LUXTH3_D1_1K             10752
-#define BH1730_LUXTH4_1K                3670
-#define BH1730_LUXTH4_D0_1K             11008
-#define BH1730_LUXTH4_D1_1K             10752
+#define BH1730_LUXTH1_1K 270
+#define BH1730_LUXTH1_D0_1K 19200
+#define BH1730_LUXTH1_D1_1K 30528
+#define BH1730_LUXTH2_1K 655360000
+#define BH1730_LUXTH2_D0_1K 11008
+#define BH1730_LUXTH2_D1_1K 10752
+#define BH1730_LUXTH3_1K 1030
+#define BH1730_LUXTH3_D0_1K 11008
+#define BH1730_LUXTH3_D1_1K 10752
+#define BH1730_LUXTH4_1K 3670
+#define BH1730_LUXTH4_D0_1K 11008
+#define BH1730_LUXTH4_D1_1K 10752
 
 /* USB Type C and USB PD defines */
 #define CONFIG_USB_PD_COMM_LOCKED
@@ -130,16 +129,16 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_AC_PRESENT		GPIO_ACOK_OD
-#define GPIO_PG_EC_RSMRST_ODL	GPIO_PG_EC_RSMRST_L
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_TEMP_SENSOR_POWER	GPIO_EN_A_RAILS
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L
+#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
 
 #ifndef __ASSEMBLER__
 
@@ -150,10 +149,10 @@
 extern enum gpio_signal gpio_en_pp5000_a;
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_1,	/* ADC0 */
-	ADC_TEMP_SENSOR_2,	/* ADC1 */
-	ADC_TEMP_SENSOR_3,	/* ADC2 */
-	ADC_TEMP_SENSOR_4,	/* ADC3 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
+	ADC_TEMP_SENSOR_3, /* ADC2 */
+	ADC_TEMP_SENSOR_4, /* ADC3 */
 	ADC_CH_COUNT
 };
 
@@ -168,10 +167,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_COUNT };
 
 enum temp_sensor_id {
 	TEMP_SENSOR_1,
diff --git a/board/kohaku/build.mk b/board/kohaku/build.mk
index 733912454f..13153c1526 100644
--- a/board/kohaku/build.mk
+++ b/board/kohaku/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/kohaku/ec.tasklist b/board/kohaku/ec.tasklist
index 63d366a33b..7fb3e38b63 100644
--- a/board/kohaku/ec.tasklist
+++ b/board/kohaku/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/kohaku/gpio.inc b/board/kohaku/gpio.inc
index 742a570cf8..eaddb14e2b 100644
--- a/board/kohaku/gpio.inc
+++ b/board/kohaku/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,10 +16,10 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(PG_EC_RSMRST_L,       PIN(E, 2), GPIO_INT_BOTH, intel_x86_rsmrst_signal_interrupt)
diff --git a/board/kohaku/led.c b/board/kohaku/led.c
index 029cf5c315..2fbf2da3a5 100644
--- a/board/kohaku/led.c
+++ b/board/kohaku/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -12,8 +12,8 @@
 #include "led_common.h"
 #include "led_onoff_states.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
 __override const int led_charge_lvl_1;
 
@@ -21,32 +21,35 @@ __override const int led_charge_lvl_2 = 100;
 
 /* Kohaku : There are 3 leds for AC, Battery and Power */
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED, 0.5 * LED_ONE_SEC},
-					{LED_OFF, 0.5 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC},
-					{LED_OFF, 1 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_GREEN,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED,
+					    0.5 * LED_ONE_SEC },
+					  { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					 { LED_OFF, 1 * LED_ONE_SEC } },
+	};
 
 __override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_BLUE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -54,12 +57,11 @@ __override void led_set_color_power(enum ec_led_colors color)
 {
 	/* Don't set led if led_auto_control is disabled. */
 	if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) ||
-		!led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
+	    !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
 		return;
 	}
 
-	if (color == EC_LED_COLOR_BLUE)
-	{
+	if (color == EC_LED_COLOR_BLUE) {
 		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
 		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
 		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_ON_LVL);
@@ -73,15 +75,14 @@ __override void led_set_color_battery(enum ec_led_colors color)
 {
 	/* Don't set led if led_auto_control is disabled. */
 	if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) ||
-		!led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
+	    !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
 		return;
 	}
 
 	/* Battery leds must be turn off when blue led is on
 	 * because kohaku has 3-in-1 led.
 	 */
-	if(!gpio_get_level(GPIO_PWR_LED_BLUE_L))
-	{
+	if (!gpio_get_level(GPIO_PWR_LED_BLUE_L)) {
 		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
 		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
 		return;
@@ -117,10 +118,13 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 {
 	if (led_id == EC_LED_ID_BATTERY_LED) {
 		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, !brightness[EC_LED_COLOR_GREEN]);
-		gpio_set_level(GPIO_BAT_LED_RED_L, !brightness[EC_LED_COLOR_RED]);
+		gpio_set_level(GPIO_BAT_LED_GREEN_L,
+			       !brightness[EC_LED_COLOR_GREEN]);
+		gpio_set_level(GPIO_BAT_LED_RED_L,
+			       !brightness[EC_LED_COLOR_RED]);
 	} else if (led_id == EC_LED_ID_POWER_LED) {
-		gpio_set_level(GPIO_PWR_LED_BLUE_L, !brightness[EC_LED_COLOR_BLUE]);
+		gpio_set_level(GPIO_PWR_LED_BLUE_L,
+			       !brightness[EC_LED_COLOR_BLUE]);
 		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
 		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
 	}
diff --git a/board/kracko/battery.c b/board/kracko/battery.c
index 13faf9f12b..4b8bbb7351 100644
--- a/board/kracko/battery.c
+++ b/board/kracko/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/kracko/board.c b/board/kracko/board.c
index 3458f91a98..136b05ea1e 100644
--- a/board/kracko/board.c
+++ b/board/kracko/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -43,7 +43,7 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
 
 #define INT_RECHECK_US 5000
 
@@ -166,48 +166,36 @@ static void pen_detect_interrupt(enum gpio_signal s)
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH0
-	},
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH2
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH3
-	},
-	[ADC_SUB_ANALOG] = {
-		.name = "SUB_ANALOG",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH13
-	},
-	[ADC_TEMP_SENSOR_3] = {
-		.name = "TEMP_SENSOR3",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH15
-	},
-	[ADC_TEMP_SENSOR_4] = {
-		.name = "TEMP_SENSOR4",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH16
-	},
+	[ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH0 },
+	[ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH2 },
+	[ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH3 },
+	[ADC_SUB_ANALOG] = { .name = "SUB_ANALOG",
+			     .factor_mul = ADC_MAX_MVOLT,
+			     .factor_div = ADC_READ_MAX + 1,
+			     .shift = 0,
+			     .channel = CHIP_ADC_CH13 },
+	[ADC_TEMP_SENSOR_3] = { .name = "TEMP_SENSOR3",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH15 },
+	[ADC_TEMP_SENSOR_4] = { .name = "TEMP_SENSOR4",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH16 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
@@ -256,19 +244,25 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 };
 
 /* USB Muxes */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+			},
 	},
 	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_SUB_USB_C1,
+				.i2c_addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	},
 };
 
@@ -282,23 +276,17 @@ static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
 static struct kionix_accel_data g_kx022_data;
 
 /* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, FLOAT_TO_FP(-1), 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
 
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
-static const mat33_fp_t lid_kx022_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_kx022_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					  { 0, FLOAT_TO_FP(1), 0 },
+					  { 0, 0, FLOAT_TO_FP(-1) } };
 
 /* Drivers */
 struct motion_sensor_t kx022_lid_accel = {
@@ -538,8 +526,8 @@ __override void board_power_5v_enable(int enable)
 
 	if (board_get_charger_chip_count() > 1) {
 		if (sm5803_set_gpio0_level(1, !!enable))
-			CPRINTUSB("Failed to %sable sub rails!", enable ?
-								  "en" : "dis");
+			CPRINTUSB("Failed to %sable sub rails!",
+				  enable ? "en" : "dis");
 	}
 }
 
@@ -547,11 +535,11 @@ __override uint8_t board_get_usb_pd_port_count(void)
 {
 	enum fw_config_db db = get_cbi_fw_config_db();
 
-	if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI
-			|| db == DB_1A_HDMI_LTE)
+	if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI ||
+	    db == DB_1A_HDMI_LTE)
 		return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
-	else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A
-			|| db == DB_1C_1A_LTE)
+	else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A ||
+		 db == DB_1C_1A_LTE)
 		return CONFIG_USB_PD_PORT_MAX_COUNT;
 
 	ccprints("Unhandled DB configuration: %d", db);
@@ -562,11 +550,11 @@ __override uint8_t board_get_charger_chip_count(void)
 {
 	enum fw_config_db db = get_cbi_fw_config_db();
 
-	if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI
-			|| db == DB_1A_HDMI_LTE)
+	if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI ||
+	    db == DB_1A_HDMI_LTE)
 		return CHARGER_NUM - 1;
-	else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A
-			|| db == DB_1C_1A_LTE)
+	else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A ||
+		 db == DB_1C_1A_LTE)
 		return CHARGER_NUM;
 
 	ccprints("Unhandled DB configuration: %d", db);
@@ -671,33 +659,31 @@ __override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
 }
 
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq_hz = 10000,
-	}
-};
+const struct pwm_t pwm_channels[] = { [PWM_CH_KBLIGHT] = {
+					      .channel = 0,
+					      .flags = PWM_CONFIG_DSLEEP,
+					      .freq_hz = 10000,
+				      } };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
 /* Thermistors */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "Charger",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_3},
-	[TEMP_SENSOR_4] = {.name = "5V regular",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_4},
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "Charger",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
+	[TEMP_SENSOR_4] = { .name = "5V regular",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_4 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -727,9 +713,8 @@ __override void lid_angle_peripheral_enable(int enable)
 	}
 }
 
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
+__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+				       int *ki_div, int *kd, int *kd_div)
 {
 	*kp = 3;
 	*kp_div = 20;
@@ -748,14 +733,17 @@ __override void ocpc_get_pid_constants(int *kp, int *kp_div,
  * The connector has 24 pins total, and there is no pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-	{-1, -1}, {GPIO_KSO_H, 4}, {GPIO_KSO_H, 0}, {GPIO_KSO_H, 1},
-	{GPIO_KSO_H, 3}, {GPIO_KSO_H, 2}, {GPIO_KSO_L, 5}, {GPIO_KSO_L, 6},
-	{GPIO_KSO_L, 3}, {GPIO_KSO_L, 2}, {GPIO_KSI, 0}, {GPIO_KSO_L, 1},
-	{GPIO_KSO_L, 4}, {GPIO_KSI, 3}, {GPIO_KSI, 2}, {GPIO_KSO_L, 0},
-	{GPIO_KSI, 5}, {GPIO_KSI, 4}, {GPIO_KSO_L, 7}, {GPIO_KSI, 6},
-	{GPIO_KSI, 7}, {GPIO_KSI, 1}, {-1, -1}, {-1, -1}, {-1, -1},
+	{ -1, -1 },	   { GPIO_KSO_H, 4 }, { GPIO_KSO_H, 0 },
+	{ GPIO_KSO_H, 1 }, { GPIO_KSO_H, 3 }, { GPIO_KSO_H, 2 },
+	{ GPIO_KSO_L, 5 }, { GPIO_KSO_L, 6 }, { GPIO_KSO_L, 3 },
+	{ GPIO_KSO_L, 2 }, { GPIO_KSI, 0 },   { GPIO_KSO_L, 1 },
+	{ GPIO_KSO_L, 4 }, { GPIO_KSI, 3 },   { GPIO_KSI, 2 },
+	{ GPIO_KSO_L, 0 }, { GPIO_KSI, 5 },   { GPIO_KSI, 4 },
+	{ GPIO_KSO_L, 7 }, { GPIO_KSI, 6 },   { GPIO_KSI, 7 },
+	{ GPIO_KSI, 1 },   { -1, -1 },	      { -1, -1 },
+	{ -1, -1 },
 };
 
 const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 #endif
diff --git a/board/kracko/board.h b/board/kracko/board.h
index 57f7927b86..78b1be8662 100644
--- a/board/kracko/board.h
+++ b/board/kracko/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,13 +23,16 @@
 
 /* Charger */
 #define CONFIG_CHARGE_RAMP_HW
-#define CONFIG_CHARGER_SM5803		/* C0 and C1: Charger */
+#define CONFIG_CHARGER_SM5803 /* C0 and C1: Charger */
+#define PD_MAX_VOLTAGE_MV 15000
 #define CONFIG_USB_PD_VBUS_DETECT_CHARGER
 #define CONFIG_USB_PD_5V_CHARGER_CTRL
 #define CONFIG_CHARGER_OTG
-#undef  CONFIG_CHARGER_SINGLE_CHIP
+#undef CONFIG_CHARGER_SINGLE_CHIP
 #define CONFIG_OCPC
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr */
+#define CONFIG_OCPC_DEF_RBATT_MOHMS               \
+	21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr \
+	    */
 
 /* PWM */
 #define CONFIG_PWM
@@ -38,9 +41,9 @@
 #define CONFIG_LED_ONOFF_STATES
 
 /* Sensors */
-#define CONFIG_ACCEL_BMA255		/* Lid accel */
-#define CONFIG_ACCEL_KX022		/* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM	/* Base accel */
+#define CONFIG_ACCEL_BMA255 /* Lid accel */
+#define CONFIG_ACCEL_KX022 /* Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
 /* Sensors without hardware FIFO are in forced mode */
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
 
@@ -73,8 +76,8 @@
 
 /* TCPC */
 #define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP	/* C0: ITE EC TCPC */
-#define CONFIG_USB_PD_TCPM_PS8705	/* C1: PS8705 TCPC*/
+#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0: ITE EC TCPC */
+#define CONFIG_USB_PD_TCPM_PS8705 /* C1: PS8705 TCPC*/
 #define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1
 #define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
 #define CONFIG_USB_PD_TCPC_LOW_POWER
@@ -85,8 +88,8 @@
 #define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
 
 /* USB Mux and Retimer */
-#define CONFIG_USB_MUX_IT5205			/* C1: ITE Mux */
-#define I2C_PORT_USB_MUX I2C_PORT_USB_C0	/* Required for ITE Mux */
+#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */
 
 /* USB Type A Features */
 #define USB_PORT_COUNT 1
@@ -109,21 +112,16 @@ enum pwm_channel {
 };
 
 /* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
 /* ADC channels */
 enum adc_channel {
-	ADC_VSNS_PP3300_A,     /* ADC0 */
-	ADC_TEMP_SENSOR_1,     /* ADC2 */
-	ADC_TEMP_SENSOR_2,     /* ADC3 */
-	ADC_SUB_ANALOG,        /* ADC13 */
-	ADC_TEMP_SENSOR_3,     /* ADC15 */
-	ADC_TEMP_SENSOR_4,     /* ADC16 */
+	ADC_VSNS_PP3300_A, /* ADC0 */
+	ADC_TEMP_SENSOR_1, /* ADC2 */
+	ADC_TEMP_SENSOR_2, /* ADC3 */
+	ADC_SUB_ANALOG, /* ADC13 */
+	ADC_TEMP_SENSOR_3, /* ADC15 */
+	ADC_TEMP_SENSOR_4, /* ADC16 */
 	ADC_CH_COUNT
 };
 
diff --git a/board/kracko/build.mk b/board/kracko/build.mk
index 8167ca9966..01b890bf29 100644
--- a/board/kracko/build.mk
+++ b/board/kracko/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/kracko/cbi_ssfc.c b/board/kracko/cbi_ssfc.c
index c4b859f133..81f3ee0dad 100644
--- a/board/kracko/cbi_ssfc.c
+++ b/board/kracko/cbi_ssfc.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
 
 enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
 {
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
 }
 
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
 {
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
 }
diff --git a/board/kracko/cbi_ssfc.h b/board/kracko/cbi_ssfc.h
index 935049b6ae..bf8853a43a 100644
--- a/board/kracko/cbi_ssfc.h
+++ b/board/kracko/cbi_ssfc.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -56,5 +56,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
  */
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
 
-
 #endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/kracko/ec.tasklist b/board/kracko/ec.tasklist
index 5c9a2d1a01..c13df44543 100644
--- a/board/kracko/ec.tasklist
+++ b/board/kracko/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/kracko/gpio.inc b/board/kracko/gpio.inc
index cdcf8834c7..a138a925f3 100644
--- a/board/kracko/gpio.inc
+++ b/board/kracko/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/kracko/led.c b/board/kracko/led.c
index af78cfa883..22a906807b 100644
--- a/board/kracko/led.c
+++ b/board/kracko/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,8 +10,8 @@
 #include "led_common.h"
 #include "led_onoff_states.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
 __override const int led_charge_lvl_1;
 
@@ -19,18 +19,24 @@ __override const int led_charge_lvl_2 = 100;
 
 /* Kracko: Note there is only LED for charge / power */
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,  2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
 const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
diff --git a/board/kracko/usb_pd_policy.c b/board/kracko/usb_pd_policy.c
index 3ff7152541..8a2c07c575 100644
--- a/board/kracko/usb_pd_policy.c
+++ b/board/kracko/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,8 +13,8 @@
 #include "driver/tcpm/tcpci.h"
 #include "usb_pd.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
@@ -65,18 +65,7 @@ int pd_set_power_supply_ready(int port)
 
 __override bool pd_check_vbus_level(int port, enum vbus_level level)
 {
-	int vbus_voltage;
-
-	/* If we're unable to speak to the charger, best to guess false */
-	if (charger_get_vbus_voltage(port, &vbus_voltage))
-		return false;
-
-	if (level == VBUS_SAFE0V)
-		return vbus_voltage < PD_V_SAFE0V_MAX;
-	else if (level == VBUS_PRESENT)
-		return vbus_voltage > PD_V_SAFE5V_MIN;
-	else
-		return vbus_voltage < PD_V_SINK_DISCONNECT_MAX;
+	return sm5803_check_vbus_level(port, level);
 }
 
 int pd_snk_is_vbus_provided(int port)
diff --git a/board/kukui/board.c b/board/kukui/board.c
index a3468b62ca..6fafc949e1 100644
--- a/board/kukui/board.c
+++ b/board/kukui/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,6 +27,7 @@
 #include "host_command.h"
 #include "i2c.h"
 #include "lid_switch.h"
+#include "panic.h"
 #include "power.h"
 #include "power_button.h"
 #include "pwm.h"
@@ -43,8 +44,8 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
@@ -65,30 +66,27 @@ static void motion_interrupt(enum gpio_signal signal);
 /******************************************************************************/
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] = {"BOARD_ID", 3300, 4096, 0, STM32_AIN(10)},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)},
-	[ADC_BATT_ID] = {"BATT_ID", 3300, 4096, 0, STM32_AIN(7)},
-	[ADC_POGO_ADC_INT_L] = {"POGO_ADC_INT_L", 3300, 4096, 0, STM32_AIN(6)},
+	[ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(10) },
+	[ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8) },
+	[ADC_BATT_ID] = { "BATT_ID", 3300, 4096, 0, STM32_AIN(7) },
+	[ADC_POGO_ADC_INT_L] = { "POGO_ADC_INT_L", 3300, 4096, 0,
+				 STM32_AIN(6) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /******************************************************************************/
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "typec",
-		.port = 0,
-		.kbps = 400,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	},
-	{
-		.name = "other",
-		.port = 1,
-		.kbps = 400,
-		.scl  = GPIO_I2C2_SCL,
-		.sda  = GPIO_I2C2_SDA
-	},
+	{ .name = "typec",
+	  .port = 0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "other",
+	  .port = 1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -96,15 +94,14 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
 /* power signal list.  Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
+	{ GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" },
+	{ GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" },
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
 /******************************************************************************/
 /* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
+const struct spi_device_t spi_devices[] = {};
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
 /******************************************************************************/
@@ -134,8 +131,7 @@ void board_set_dp_mux_control(int output_enable, int polarity)
 		gpio_set_level(GPIO_USB_C0_DP_POLARITY, polarity);
 }
 
-static void board_hpd_update(const struct usb_mux *me,
-			     mux_state_t mux_state,
+static void board_hpd_update(const struct usb_mux *me, mux_state_t mux_state,
 			     bool *ack_required)
 {
 	/* This driver does not use host command ACKs */
@@ -162,13 +158,17 @@ __override const struct rt946x_init_setting *board_rt946x_init_setting(void)
 	return &battery_init_setting;
 }
 
-struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+struct usb_mux usbc0_mux0 = {
+	.usb_port = 0,
+	.i2c_port = I2C_PORT_USB_MUX,
+	.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+	.driver = &it5205_usb_mux_driver,
+	.hpd_update = &board_hpd_update,
+};
+
+struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_update,
+		.mux = &usbc0_mux0,
 	},
 };
 
@@ -266,9 +266,8 @@ int extpower_is_present(void)
 	if (board_vbus_source_enabled(CHARGE_PORT_USB_C))
 		usb_c_extpower_present = 0;
 	else
-		usb_c_extpower_present = tcpm_check_vbus_level(
-							CHARGE_PORT_USB_C,
-							VBUS_PRESENT);
+		usb_c_extpower_present =
+			tcpm_check_vbus_level(CHARGE_PORT_USB_C, VBUS_PRESENT);
 
 	return usb_c_extpower_present || kukui_pogo_extpower_present();
 }
@@ -357,15 +356,15 @@ static void board_rev_init(void)
 		/* configure PI3USB9201 to USB Path ON Mode */
 		i2c_write8(I2C_PORT_BC12, BC12_I2C_ADDR_FLAGS,
 			   PI3USB9201_REG_CTRL_1,
-			   (PI3USB9201_USB_PATH_ON <<
-			    PI3USB9201_REG_CTRL_1_MODE_SHIFT));
+			   (PI3USB9201_USB_PATH_ON
+			    << PI3USB9201_REG_CTRL_1_MODE_SHIFT));
 	}
 
 	if (board_get_version() < 5) {
 		gpio_set_flags(GPIO_USB_C0_DP_OE_L, GPIO_OUT_HIGH);
 		gpio_set_flags(GPIO_USB_C0_DP_POLARITY, GPIO_OUT_LOW);
-		usb_muxes[0].driver = &virtual_usb_mux_driver;
-		usb_muxes[0].hpd_update = &virtual_hpd_update;
+		usbc0_mux0.driver = &virtual_usb_mux_driver;
+		usbc0_mux0.hpd_update = &virtual_hpd_update;
 	}
 }
 DECLARE_HOOK(HOOK_INIT, board_rev_init, HOOK_PRIO_INIT_ADC + 1);
@@ -438,26 +437,20 @@ static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
 
 /* Matrix to rotate accelerometer into standard reference frame */
 #ifdef BOARD_KUKUI
-static const mat33_fp_t lid_standard_ref = {
-	{FLOAT_TO_FP(1), 0, 0},
-	{0, FLOAT_TO_FP(1), 0},
-	{0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(1), 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
 #else
-static const mat33_fp_t lid_standard_ref = {
-	{FLOAT_TO_FP(-1), 0, 0},
-	{0, FLOAT_TO_FP(-1), 0},
-	{0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
 #endif /* BOARD_KUKUI */
 
 #ifdef CONFIG_MAG_BMI_BMM150
 /* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t mag_standard_ref = {
-	{0, FLOAT_TO_FP(-1), 0},
-	{FLOAT_TO_FP(-1), 0, 0},
-	{0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t mag_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+					     { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 #endif /* CONFIG_MAG_BMI_BMM150 */
 
 struct motion_sensor_t motion_sensors[] = {
@@ -632,7 +625,6 @@ static void motion_interrupt(enum gpio_signal signal)
 #elif !defined(VARIANT_KUKUI_NO_SENSORS)
 	bmi160_interrupt(signal);
 #endif /* BOARD_KRANE, !VARIANT_KUKUI_NO_SENSORS */
-
 }
 #endif /* SECTION_IS_RW */
 
@@ -669,9 +661,8 @@ __override int board_charge_port_is_connected(int port)
 	return gpio_get_level(GPIO_POGO_VBUS_PRESENT);
 }
 
-__override
-void board_fill_source_power_info(int port,
-				  struct ec_response_usb_pd_power_info *r)
+__override void
+board_fill_source_power_info(int port, struct ec_response_usb_pd_power_info *r)
 {
 	r->meas.voltage_now = 3300;
 	r->meas.voltage_max = 3300;
diff --git a/board/kukui/board.h b/board/kukui/board.h
index 8cedd195e1..94c05a1209 100644
--- a/board/kukui/board.h
+++ b/board/kukui/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -37,9 +37,9 @@
 
 /* Battery */
 #ifdef BOARD_KRANE
-#define BATTERY_DESIRED_CHARGING_CURRENT    3500  /* mA */
+#define BATTERY_DESIRED_CHARGING_CURRENT 3500 /* mA */
 #else
-#define BATTERY_DESIRED_CHARGING_CURRENT    2000  /* mA */
+#define BATTERY_DESIRED_CHARGING_CURRENT 2000 /* mA */
 #endif /* BOARD_KRANE */
 
 #ifdef BOARD_KRANE
@@ -79,19 +79,18 @@
 /* Camera VSYNC */
 #define CONFIG_SYNC
 #define CONFIG_SYNC_COMMAND
-#define CONFIG_SYNC_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
+#define CONFIG_SYNC_INT_EVENT TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
 #endif /* SECTION_IS_RW */
 
 /* I2C ports */
-#define I2C_PORT_CHARGER  0
-#define I2C_PORT_TCPC0    0
-#define I2C_PORT_USB_MUX  0
-#define I2C_PORT_BATTERY  1
+#define I2C_PORT_CHARGER 0
+#define I2C_PORT_TCPC0 0
+#define I2C_PORT_USB_MUX 0
+#define I2C_PORT_BATTERY 1
 #define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
-#define I2C_PORT_ACCEL    1
-#define I2C_PORT_BC12     1
-#define I2C_PORT_ALS      1
+#define I2C_PORT_ACCEL 1
+#define I2C_PORT_BC12 1
+#define I2C_PORT_ALS 1
 
 /* Route sbs host requests to virtual battery driver */
 #define VIRTUAL_BATTERY_ADDR_FLAGS 0x0B
diff --git a/board/kukui/build.mk b/board/kukui/build.mk
index 694879cee6..b60b9cf091 100644
--- a/board/kukui/build.mk
+++ b/board/kukui/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/kukui/ec.tasklist b/board/kukui/ec.tasklist
index 9ba564ce52..2551038b66 100644
--- a/board/kukui/ec.tasklist
+++ b/board/kukui/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/kukui/gpio.inc b/board/kukui/gpio.inc
index eed1fea828..efac70d681 100644
--- a/board/kukui/gpio.inc
+++ b/board/kukui/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/kukui/led.c b/board/kukui/led.c
index 59f7681754..9cfdf855be 100644
--- a/board/kukui/led.c
+++ b/board/kukui/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -17,15 +17,15 @@ const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 static enum charge_state prv_chstate = PWR_STATE_INIT;
 
-#define LED_OFF		MT6370_LED_ID_OFF
-#define LED_RED		MT6370_LED_ID1
-#define LED_GREEN	MT6370_LED_ID2
-#define LED_BLUE	MT6370_LED_ID3
+#define LED_OFF MT6370_LED_ID_OFF
+#define LED_RED MT6370_LED_ID1
+#define LED_GREEN MT6370_LED_ID2
+#define LED_BLUE MT6370_LED_ID3
 
-#define LED_MASK_OFF	0
-#define LED_MASK_RED	MT6370_MASK_RGB_ISNK1DIM_EN
-#define LED_MASK_GREEN	MT6370_MASK_RGB_ISNK2DIM_EN
-#define LED_MASK_BLUE	MT6370_MASK_RGB_ISNK3DIM_EN
+#define LED_MASK_OFF 0
+#define LED_MASK_RED MT6370_MASK_RGB_ISNK1DIM_EN
+#define LED_MASK_GREEN MT6370_MASK_RGB_ISNK2DIM_EN
+#define LED_MASK_BLUE MT6370_MASK_RGB_ISNK3DIM_EN
 
 static void kukui_led_set_battery(void)
 {
@@ -35,8 +35,7 @@ static void kukui_led_set_battery(void)
 
 	chstate = charge_get_state();
 
-	if (prv_chstate == chstate &&
-		chstate != PWR_STATE_DISCHARGE)
+	if (prv_chstate == chstate && chstate != PWR_STATE_DISCHARGE)
 		return;
 
 	prv_chstate = chstate;
@@ -62,8 +61,7 @@ static void kukui_led_set_battery(void)
 		return;
 	}
 
-	if (prv_r == br[EC_LED_COLOR_RED] &&
-	    prv_g == br[EC_LED_COLOR_GREEN] &&
+	if (prv_r == br[EC_LED_COLOR_RED] && prv_g == br[EC_LED_COLOR_GREEN] &&
 	    prv_b == br[EC_LED_COLOR_BLUE])
 		return;
 
diff --git a/board/kukui_scp/board.c b/board/kukui_scp/board.c
index d86e7e5fc6..7eab3c59a6 100644
--- a/board/kukui_scp/board.c
+++ b/board/kukui_scp/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/kukui_scp/board.h b/board/kukui_scp/board.h
index 0c42c0cf2a..64104060ab 100644
--- a/board/kukui_scp/board.h
+++ b/board/kukui_scp/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,8 +16,8 @@
 #define CONFIG_FLASH_SIZE_BYTES 0x58000 /* Image file size: 256KB */
 #endif
 
-#undef  CONFIG_LID_SWITCH
-#undef  CONFIG_FW_INCLUDE_RO
+#undef CONFIG_LID_SWITCH
+#undef CONFIG_FW_INCLUDE_RO
 #define CONFIG_MKBP_EVENT
 /* Sent MKBP event via IPI. */
 #define CONFIG_MKBP_USE_CUSTOM
@@ -27,10 +27,12 @@
 #define CONFIG_HOSTCMD_ALIGNED
 
 /*
+ * mt8183:
+ *
  * RW only, no flash
  * +-------------------- 0x0
  * | ROM vectortable, .text, .rodata, .data LMA
- * +-------------------- 0x10000
+ * +-------------------- 0x58000
  * | RAM .bss, .data
  * +-------------------- 0x7BDB0
  * | IPI shared buffer with AP (288 + 8) * 2
@@ -40,11 +42,23 @@
  * | 8KB D-CACHE
  * +-------------------- 0x80000
  */
-#ifdef CHIP_VARIANT_MT8186
-#define ICACHE_BASE 0x3E000
-#else
-#define ICACHE_BASE 0x7C000
-#endif
+
+/*
+ * mt8186:
+ *
+ * RW only, no flash
+ * +-------------------- 0x0
+ * | ROM vectortable, .text, .rodata, .data LMA
+ * +-------------------- 0x2C000
+ * | RAM .bss, .data
+ * +-------------------- 0x3BDB0
+ * | IPI shared buffer with AP (288 + 8) * 2 => 0x250
+ * +-------------------- 0x3C000
+ * | 8KB I-CACHE
+ * +-------------------- 0x3E000
+ * | 8KB D-CACHE
+ * +-------------------- 0x40000
+ */
 
 #define CONFIG_ROM_BASE 0x0
 
@@ -54,6 +68,12 @@
 #define CONFIG_RAM_BASE 0x58000
 #endif
 
+#ifdef CHIP_VARIANT_MT8186
+#define ICACHE_BASE 0x3C000
+#else
+#define ICACHE_BASE 0x7C000
+#endif
+
 #define CONFIG_ROM_SIZE (CONFIG_RAM_BASE - CONFIG_ROM_BASE)
 #define CONFIG_RAM_SIZE (CONFIG_IPC_SHARED_OBJ_ADDR - CONFIG_RAM_BASE)
 #define CONFIG_CODE_RAM_SIZE CONFIG_RAM_BASE
@@ -64,12 +84,19 @@
 #define CONFIG_DRAM_BASE 0x10000000
 /* Shared memory address in AP physical address space. */
 #define CONFIG_DRAM_BASE_LOAD 0x50000000
+
+#ifdef CHIP_VARIANT_MT8186
+#define CONFIG_DRAM_SIZE 0x010a0000 /* 16 MB */
+#define CACHE_TRANS_AP_SIZE 0x010a0000
+#else
 #define CONFIG_DRAM_SIZE 0x01400000 /* 20 MB */
+#define CACHE_TRANS_AP_SIZE 0x00400000
+#endif
 
 /* IPI configs */
 #define CONFIG_IPC_SHARED_OBJ_BUF_SIZE 288
-#define CONFIG_IPC_SHARED_OBJ_ADDR                                             \
-	(ICACHE_BASE -                                                         \
+#define CONFIG_IPC_SHARED_OBJ_ADDR \
+	(ICACHE_BASE -             \
 	 (CONFIG_IPC_SHARED_OBJ_BUF_SIZE + 2 * 4 /* int32_t */) * 2)
 #define CONFIG_IPI
 #define CONFIG_RPMSG_NAME_SERVICE
@@ -95,11 +122,10 @@
 
 #define IPI_NS_SERVICE 0xFF
 
-
 #undef CONFIG_UART_TX_BUF_SIZE
 #define CONFIG_UART_TX_BUF_SIZE 8192
 
-#undef  CONFIG_UART_CONSOLE
+#undef CONFIG_UART_CONSOLE
 /*
  * CONFIG_UART_CONSOLE
  *   0 - SCP UART0
@@ -112,8 +138,8 @@
 #define CONFIG_UART_CONSOLE 0
 #endif
 /* We let AP setup the correct pinmux. */
-#undef    UART0_PINMUX_11_12
-#undef    UART0_PINMUX_110_112
+#undef UART0_PINMUX_11_12
+#undef UART0_PINMUX_110_112
 
 /* Track AP power state */
 #define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
diff --git a/board/kukui_scp/build.mk b/board/kukui_scp/build.mk
index 0fdaa1c820..f04d506057 100644
--- a/board/kukui_scp/build.mk
+++ b/board/kukui_scp/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/kukui_scp/ec.tasklist b/board/kukui_scp/ec.tasklist
index 935d409b00..82bb6db382 100644
--- a/board/kukui_scp/ec.tasklist
+++ b/board/kukui_scp/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/kukui_scp/fd.c b/board/kukui_scp/fd.c
index 237f15ca94..be0bdeab57 100644
--- a/board/kukui_scp/fd.c
+++ b/board/kukui_scp/fd.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,12 +20,11 @@
 static struct consumer const event_fd_consumer;
 static void event_fd_written(struct consumer const *consumer, size_t count);
 
-static struct queue const fd_queue = QUEUE_DIRECT(4, struct fd_msg,
-						  null_producer,
-						  event_fd_consumer);
+static struct queue const fd_queue =
+	QUEUE_DIRECT(4, struct fd_msg, null_producer, event_fd_consumer);
 static struct consumer const event_fd_consumer = {
 	.queue = &fd_queue,
-	.ops = &((struct consumer_ops const) {
+	.ops = &((struct consumer_ops const){
 		.written = event_fd_written,
 	}),
 };
@@ -33,7 +32,9 @@ static struct consumer const event_fd_consumer = {
 /* Stub functions only provided by private overlays. */
 // Jerry TODO implement private part and remove this
 #ifndef HAVE_PRIVATE_MT8183
-void fd_ipi_msg_handler(void *data) {}
+void fd_ipi_msg_handler(void *data)
+{
+}
 #endif
 
 static void event_fd_written(struct consumer const *consumer, size_t count)
diff --git a/board/kukui_scp/fd.h b/board/kukui_scp/fd.h
index 3f70387400..cea5817942 100644
--- a/board/kukui_scp/fd.h
+++ b/board/kukui_scp/fd.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/kukui_scp/gpio.inc b/board/kukui_scp/gpio.inc
index b186904aad..6cc2e0495e 100644
--- a/board/kukui_scp/gpio.inc
+++ b/board/kukui_scp/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/kukui_scp/isp_p1_srv.c b/board/kukui_scp/isp_p1_srv.c
index 5c2ae7c2e9..40dd37ff90 100644
--- a/board/kukui_scp/isp_p1_srv.c
+++ b/board/kukui_scp/isp_p1_srv.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,19 +20,21 @@
 static struct consumer const event_isp_consumer;
 static void event_isp_written(struct consumer const *consumer, size_t count);
 
-static struct queue const event_isp_queue = QUEUE_DIRECT(8,
-	struct isp_msg, null_producer, event_isp_consumer);
+static struct queue const event_isp_queue =
+	QUEUE_DIRECT(8, struct isp_msg, null_producer, event_isp_consumer);
 
 static struct consumer const event_isp_consumer = {
 	.queue = &event_isp_queue,
-	.ops = &((struct consumer_ops const) {
+	.ops = &((struct consumer_ops const){
 		.written = event_isp_written,
 	}),
 };
 
 /* Stub functions only provided by private overlays. */
 #ifndef HAVE_PRIVATE_MT8183
-void isp_msg_handler(void *data) {}
+void isp_msg_handler(void *data)
+{
+}
 #endif
 
 static void event_isp_written(struct consumer const *consumer, size_t count)
diff --git a/board/kukui_scp/isp_p1_srv.h b/board/kukui_scp/isp_p1_srv.h
index ba6fa7d110..e0abe9e4c8 100644
--- a/board/kukui_scp/isp_p1_srv.h
+++ b/board/kukui_scp/isp_p1_srv.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,7 +13,8 @@ struct isp_msg {
 	unsigned char msg[140];
 };
 
-BUILD_ASSERT(member_size(struct isp_msg, msg) <= CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
+BUILD_ASSERT(member_size(struct isp_msg, msg) <=
+	     CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
 
 /* Functions provided by private overlay. */
 void isp_msg_handler(void *data);
diff --git a/board/kukui_scp/isp_p2_srv.c b/board/kukui_scp/isp_p2_srv.c
index dba330c6a8..f38d4401ff 100644
--- a/board/kukui_scp/isp_p2_srv.c
+++ b/board/kukui_scp/isp_p2_srv.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,19 +19,21 @@
 static struct consumer const event_dip_consumer;
 static void event_dip_written(struct consumer const *consumer, size_t count);
 
-static struct queue const event_dip_queue = QUEUE_DIRECT(4,
-	struct dip_msg_service, null_producer, event_dip_consumer);
+static struct queue const event_dip_queue = QUEUE_DIRECT(
+	4, struct dip_msg_service, null_producer, event_dip_consumer);
 
 static struct consumer const event_dip_consumer = {
 	.queue = &event_dip_queue,
-	.ops = &((struct consumer_ops const) {
+	.ops = &((struct consumer_ops const){
 		.written = event_dip_written,
 	}),
 };
 
 /* Stub functions only provided by private overlays. */
 #ifndef HAVE_PRIVATE_MT8183
-void dip_msg_handler(void *data) {}
+void dip_msg_handler(void *data)
+{
+}
 #endif
 
 static void event_dip_written(struct consumer const *consumer, size_t count)
diff --git a/board/kukui_scp/isp_p2_srv.h b/board/kukui_scp/isp_p2_srv.h
index 70fb0673de..3c1ba50f1c 100644
--- a/board/kukui_scp/isp_p2_srv.h
+++ b/board/kukui_scp/isp_p2_srv.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,7 +13,8 @@ struct dip_msg_service {
 	unsigned char msg[288];
 };
 
-BUILD_ASSERT(member_size(struct dip_msg_service, msg) <= CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
+BUILD_ASSERT(member_size(struct dip_msg_service, msg) <=
+	     CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
 
 /* Functions provided by private overlay. */
 void dip_msg_handler(void *data);
diff --git a/board/kukui_scp/mdp_ipi_message.c b/board/kukui_scp/mdp_ipi_message.c
index eca40b741b..f0bf7f2f92 100644
--- a/board/kukui_scp/mdp_ipi_message.c
+++ b/board/kukui_scp/mdp_ipi_message.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,19 +18,23 @@
 static struct consumer const event_mdp_consumer;
 static void event_mdp_written(struct consumer const *consumer, size_t count);
 
-static struct queue const event_mdp_queue = QUEUE_DIRECT(4,
-	struct mdp_msg_service, null_producer, event_mdp_consumer);
+static struct queue const event_mdp_queue = QUEUE_DIRECT(
+	4, struct mdp_msg_service, null_producer, event_mdp_consumer);
 static struct consumer const event_mdp_consumer = {
 	.queue = &event_mdp_queue,
-	.ops = &((struct consumer_ops const) {
+	.ops = &((struct consumer_ops const){
 		.written = event_mdp_written,
 	}),
 };
 
 /* Stub functions only provided by private overlays. */
 #ifndef HAVE_PRIVATE_MT8183
-void mdp_common_init(void) {}
-void mdp_ipi_task_handler(void *pvParameters) {}
+void mdp_common_init(void)
+{
+}
+void mdp_ipi_task_handler(void *pvParameters)
+{
+}
 #endif
 
 static void event_mdp_written(struct consumer const *consumer, size_t count)
diff --git a/board/kukui_scp/mdp_ipi_message.h b/board/kukui_scp/mdp_ipi_message.h
index bcedb58504..0e46b947b2 100644
--- a/board/kukui_scp/mdp_ipi_message.h
+++ b/board/kukui_scp/mdp_ipi_message.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,9 +11,10 @@ struct mdp_msg_service {
 	unsigned char msg[20];
 };
 
-BUILD_ASSERT(member_size(struct mdp_msg_service, msg) <= CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
+BUILD_ASSERT(member_size(struct mdp_msg_service, msg) <=
+	     CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
 
 void mdp_common_init(void);
 void mdp_ipi_task_handler(void *pvParameters);
 
-#endif  // _MDP_IPI_MESSAGE_H
+#endif // _MDP_IPI_MESSAGE_H
diff --git a/board/kukui_scp/update_scp b/board/kukui_scp/update_scp
index 448a8f74db..67aaacdcdc 100755
--- a/board/kukui_scp/update_scp
+++ b/board/kukui_scp/update_scp
@@ -1,5 +1,5 @@
 #!/bin/bash
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/board/kukui_scp/vdec.c b/board/kukui_scp/vdec.c
index eb4f1f8fa1..317d83d0d5 100644
--- a/board/kukui_scp/vdec.c
+++ b/board/kukui_scp/vdec.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,19 +20,23 @@
 static struct consumer const event_vdec_consumer;
 static void event_vdec_written(struct consumer const *consumer, size_t count);
 
-static struct queue const event_vdec_queue = QUEUE_DIRECT(8,
-	struct vdec_msg, null_producer, event_vdec_consumer);
+static struct queue const event_vdec_queue =
+	QUEUE_DIRECT(8, struct vdec_msg, null_producer, event_vdec_consumer);
 static struct consumer const event_vdec_consumer = {
 	.queue = &event_vdec_queue,
-	.ops = &((struct consumer_ops const) {
+	.ops = &((struct consumer_ops const){
 		.written = event_vdec_written,
 	}),
 };
 
 /* Stub functions only provided by private overlays. */
 #ifndef HAVE_PRIVATE_MT8183
-void vdec_h264_service_init(void) {}
-void vdec_h264_msg_handler(void *data) {}
+void vdec_h264_service_init(void)
+{
+}
+void vdec_h264_msg_handler(void *data)
+{
+}
 #endif
 
 static vdec_msg_handler mtk_vdec_msg_handle[VDEC_MAX];
diff --git a/board/kukui_scp/vdec.h b/board/kukui_scp/vdec.h
index 9cfb877e12..9284c28a40 100644
--- a/board/kukui_scp/vdec.h
+++ b/board/kukui_scp/vdec.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,7 +24,8 @@ struct vdec_msg {
 	unsigned char msg[48];
 };
 
-BUILD_ASSERT(member_size(struct vdec_msg, msg) <= CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
+BUILD_ASSERT(member_size(struct vdec_msg, msg) <=
+	     CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
 
 /* Functions provided by private overlay. */
 void vdec_h264_service_init(void);
diff --git a/board/kukui_scp/venc.c b/board/kukui_scp/venc.c
index c7e19d120c..1f07a6eea0 100644
--- a/board/kukui_scp/venc.c
+++ b/board/kukui_scp/venc.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,11 +20,11 @@
 static struct consumer const event_venc_consumer;
 static void event_venc_written(struct consumer const *consumer, size_t count);
 
-static struct queue const event_venc_queue = QUEUE_DIRECT(8,
-	struct venc_msg, null_producer, event_venc_consumer);
+static struct queue const event_venc_queue =
+	QUEUE_DIRECT(8, struct venc_msg, null_producer, event_venc_consumer);
 static struct consumer const event_venc_consumer = {
 	.queue = &event_venc_queue,
-	.ops = &((struct consumer_ops const) {
+	.ops = &((struct consumer_ops const){
 		.written = event_venc_written,
 	}),
 };
@@ -33,7 +33,9 @@ static venc_msg_handler mtk_venc_msg_handle[VENC_MAX];
 
 /* Stub functions only provided by private overlays. */
 #ifndef HAVE_PRIVATE_MT8183
-void venc_h264_msg_handler(void *data) {}
+void venc_h264_msg_handler(void *data)
+{
+}
 #endif
 
 static void event_venc_written(struct consumer const *consumer, size_t count)
diff --git a/board/kukui_scp/venc.h b/board/kukui_scp/venc.h
index 7046633046..1fc8421795 100644
--- a/board/kukui_scp/venc.h
+++ b/board/kukui_scp/venc.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,7 +22,8 @@ struct venc_msg {
 	unsigned char msg[288];
 };
 
-BUILD_ASSERT(member_size(struct venc_msg, msg) <= CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
+BUILD_ASSERT(member_size(struct venc_msg, msg) <=
+	     CONFIG_IPC_SHARED_OBJ_BUF_SIZE);
 
 /* Functions provided by private overlay. */
 void venc_h264_msg_handler(void *data);
diff --git a/board/kuldax/board.c b/board/kuldax/board.c
index 631aca2bdd..44b7dfdc3f 100644
--- a/board/kuldax/board.c
+++ b/board/kuldax/board.c
@@ -1,11 +1,11 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 #include <stdbool.h>
 
 #include "adc.h"
-#include "assert.h"
+#include "builtin/assert.h"
 #include "button.h"
 #include "charge_manager.h"
 #include "charge_state_v2.h"
@@ -27,8 +27,8 @@
 #include "fw_config.h"
 
 /* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 static void power_monitor(void);
 DECLARE_DEFERRED(power_monitor);
@@ -113,8 +113,6 @@ int board_set_active_charge_port(int port)
 
 	switch (port) {
 	case CHARGE_PORT_TYPEC0:
-	case CHARGE_PORT_TYPEC1:
-	case CHARGE_PORT_TYPEC2:
 		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 1);
 		break;
 	case CHARGE_PORT_BARRELJACK:
@@ -140,21 +138,21 @@ static int32_t base_5v_power_z1;
  */
 
 /* PP5000_S5 loads */
-#define PWR_S5_BASE_LOAD  (5*1431)
-#define PWR_S5_FRONT_HIGH (5*1737)
-#define PWR_S5_FRONT_LOW  (5*1055)
-#define PWR_S5_REAR_HIGH  (5*1737)
-#define PWR_S5_REAR_LOW   (5*1055)
-#define PWR_S5_HDMI       (5*580)
-#define PWR_S5_MAX        (5*10000)
-#define FRONT_DELTA       (PWR_S5_FRONT_HIGH - PWR_S5_FRONT_LOW)
-#define REAR_DELTA        (PWR_S5_REAR_HIGH - PWR_S5_REAR_LOW)
+#define PWR_S5_BASE_LOAD (5 * 1431)
+#define PWR_S5_FRONT_HIGH (5 * 1737)
+#define PWR_S5_FRONT_LOW (5 * 1055)
+#define PWR_S5_REAR_HIGH (5 * 1737)
+#define PWR_S5_REAR_LOW (5 * 1055)
+#define PWR_S5_HDMI (5 * 580)
+#define PWR_S5_MAX (5 * 10000)
+#define FRONT_DELTA (PWR_S5_FRONT_HIGH - PWR_S5_FRONT_LOW)
+#define REAR_DELTA (PWR_S5_REAR_HIGH - PWR_S5_REAR_LOW)
 
 /* PP5000_Z1 loads */
-#define PWR_Z1_BASE_LOAD   (5*5)
-#define PWR_Z1_C_HIGH      (5*3600)
-#define PWR_Z1_C_LOW       (5*2000)
-#define PWR_Z1_MAX         (5*9000)
+#define PWR_Z1_BASE_LOAD (5 * 5)
+#define PWR_Z1_C_HIGH (5 * 3600)
+#define PWR_Z1_C_LOW (5 * 2000)
+#define PWR_Z1_MAX (5 * 9000)
 /*
  * Update the 5V power usage, assuming no throttling,
  * and invoke the power monitoring.
@@ -228,7 +226,7 @@ static void port_ocp_interrupt(enum gpio_signal signal)
  * only do that if the system is off since it might still brown out.
  */
 
-#define ADP_DEBOUNCE_MS		1000  /* Debounce time for BJ plug/unplug */
+#define ADP_DEBOUNCE_MS 1000 /* Debounce time for BJ plug/unplug */
 /* Debounced connection state of the barrel jack */
 static int8_t adp_connected = -1;
 static void adp_connect_deferred(void)
@@ -328,26 +326,26 @@ void board_overcurrent_event(int port, int is_overcurrented)
  *
  *  All measurements are in milliwatts.
  */
-#define THROT_TYPE_A_FRONT  BIT(0)
-#define THROT_TYPE_A_REAR   BIT(1)
-#define THROT_TYPE_C0       BIT(2)
-#define THROT_TYPE_C1       BIT(3)
-#define THROT_TYPE_C2       BIT(4)
-#define THROT_PROCHOT       BIT(5)
+#define THROT_TYPE_A_FRONT BIT(0)
+#define THROT_TYPE_A_REAR BIT(1)
+#define THROT_TYPE_C0 BIT(2)
+#define THROT_TYPE_C1 BIT(3)
+#define THROT_TYPE_C2 BIT(4)
+#define THROT_PROCHOT BIT(5)
 
 /*
  * Power gain if front USB A ports are limited.
  */
-#define POWER_GAIN_TYPE_A	3200
+#define POWER_GAIN_TYPE_A 3200
 /*
  * Power gain if Type C port is limited.
  */
-#define POWER_GAIN_TYPE_C	8800
+#define POWER_GAIN_TYPE_C 8800
 /*
  * Power is averaged over 10 ms, with a reading every 2 ms.
  */
-#define POWER_DELAY_MS		2
-#define POWER_READINGS		(10/POWER_DELAY_MS)
+#define POWER_DELAY_MS 2
+#define POWER_READINGS (10 / POWER_DELAY_MS)
 
 static void power_monitor(void)
 {
@@ -363,8 +361,7 @@ static void power_monitor(void)
 	 * If CPU is off or suspended, no need to throttle
 	 * or restrict power.
 	 */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF |
-			     CHIPSET_STATE_SUSPEND)) {
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF | CHIPSET_STATE_SUSPEND)) {
 		/*
 		 * Slow down monitoring, assume no throttling required.
 		 */
@@ -392,7 +389,7 @@ static void power_monitor(void)
 			 */
 			power = (adc_read_channel(ADC_VBUS) *
 				 adc_read_channel(ADC_PPVAR_IMON)) /
-				 1000;
+				1000;
 			/* Init power table */
 			if (history[0] == 0) {
 				for (i = 0; i < POWER_READINGS; i++)
@@ -419,8 +416,7 @@ static void power_monitor(void)
 			 * For barrel-jack supplies, the rating can be
 			 * exceeded briefly, so use the average.
 			 */
-			if (charge_manager_get_supplier() ==
-			    CHARGE_SUPPLIER_PD)
+			if (charge_manager_get_supplier() == CHARGE_SUPPLIER_PD)
 				power = max;
 			else
 				power = total / POWER_READINGS;
@@ -459,26 +455,6 @@ static void power_monitor(void)
 					gap += POWER_GAIN_TYPE_C;
 			}
 			/*
-			 * If the type-C port is sourcing power,
-			 * check whether it should be throttled.
-			 */
-			if (ppc_is_sourcing_vbus(1) && gap <= 0) {
-				new_state |= THROT_TYPE_C1;
-				headroom_5v_z1 += PWR_Z1_C_HIGH - PWR_Z1_C_LOW;
-				if (!(current_state & THROT_TYPE_C1))
-					gap += POWER_GAIN_TYPE_C;
-			}
-			/*
-			 * If the type-C port is sourcing power,
-			 * check whether it should be throttled.
-			 */
-			if (ppc_is_sourcing_vbus(2) && gap <= 0) {
-				new_state |= THROT_TYPE_C2;
-				headroom_5v_z1 += PWR_Z1_C_HIGH - PWR_Z1_C_LOW;
-				if (!(current_state & THROT_TYPE_C2))
-					gap += POWER_GAIN_TYPE_C;
-			}
-			/*
 			 * As a last resort, turn on PROCHOT to
 			 * throttle the CPU.
 			 */
@@ -551,24 +527,27 @@ static void power_monitor(void)
 		gpio_set_level(GPIO_EC_PROCHOT_ODL, prochot);
 	}
 	if (diff & THROT_TYPE_C0) {
-		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C0)
-			? TYPEC_RP_1A5 : TYPEC_RP_3A0;
+		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C0) ?
+						TYPEC_RP_1A5 :
+						TYPEC_RP_3A0;
 
 		ppc_set_vbus_source_current_limit(0, rp);
 		tcpm_select_rp_value(0, rp);
 		pd_update_contract(0);
 	}
 	if (diff & THROT_TYPE_C1) {
-		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C1)
-			? TYPEC_RP_1A5 : TYPEC_RP_3A0;
+		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C1) ?
+						TYPEC_RP_1A5 :
+						TYPEC_RP_3A0;
 
 		ppc_set_vbus_source_current_limit(1, rp);
 		tcpm_select_rp_value(1, rp);
 		pd_update_contract(1);
 	}
 	if (diff & THROT_TYPE_C2) {
-		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C2)
-			? TYPEC_RP_1A5 : TYPEC_RP_3A0;
+		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C2) ?
+						TYPEC_RP_1A5 :
+						TYPEC_RP_3A0;
 
 		ppc_set_vbus_source_current_limit(2, rp);
 		tcpm_select_rp_value(2, rp);
@@ -584,7 +563,6 @@ static void power_monitor(void)
 		int typea_bc = (new_state & THROT_TYPE_A_FRONT) ? 1 : 0;
 
 		gpio_set_level(GPIO_USB_A_LOW_PWR2_OD, typea_bc);
-		gpio_set_level(GPIO_USB_A_LOW_PWR3_OD, typea_bc);
 	}
 	hook_call_deferred(&power_monitor_data, delay);
 }
diff --git a/board/kuldax/board.h b/board/kuldax/board.h
index e73d1d8d4b..64804bf16a 100644
--- a/board/kuldax/board.h
+++ b/board/kuldax/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,48 +16,42 @@
 #define CONFIG_MP2964
 
 /* Barrel Jack */
-#define DEDICATED_CHARGE_PORT 3
+#define DEDICATED_CHARGE_PORT 1
 
 /* HDMI CEC */
 #define CONFIG_CEC
 #define CEC_GPIO_OUT GPIO_HDMI_CEC_OUT
-#define CEC_GPIO_IN  GPIO_HDMI_CEC_IN
+#define CEC_GPIO_IN GPIO_HDMI_CEC_IN
 #define CEC_GPIO_PULL_UP GPIO_HDMI_CEC_PULL_UP
 
 /* USB Type A Features */
-#define USB_PORT_COUNT			4
+#define USB_PORT_COUNT 4
 #define CONFIG_USB_PORT_POWER_DUMB
 
 /* USB Type C and USB PD defines */
 #define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
 
-#define CONFIG_IO_EXPANDER
-#define CONFIG_IO_EXPANDER_NCT38XX
-#define CONFIG_IO_EXPANDER_PORT_COUNT		2
-
 #define CONFIG_USB_PD_PPC
 #define CONFIG_USB_PD_TCPM_RT1715
 #define CONFIG_USBC_RETIMER_INTEL_BB
 
-#define CONFIG_USBC_RETIMER_KB800X
-#define CONFIG_KB800X_CUSTOM_XBAR
 #define CONFIG_USBC_PPC_SYV682X
 #undef CONFIG_SYV682X_HV_ILIM
 #define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_5_50
 
 /* TODO: b/177608416 - measure and check these values on brya */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
 
 /* The design should support up to 100W. */
 /* TODO(b/197702356): Set the max PD to 60W now and change it
  * to 100W after we verify it.
  */
-#define PD_OPERATING_POWER_MW	CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
-#define PD_MAX_POWER_MW		100000
-#define PD_MAX_CURRENT_MA	5000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
+#define PD_MAX_POWER_MW 100000
+#define PD_MAX_CURRENT_MA 5000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /*
  * Macros for GPIO signals used in common code that don't match the
@@ -65,64 +59,63 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_PACKET_MODE_EN		GPIO_EC_GSC_PACKET_MODE
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SYS_SLP_S0IX_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_TEMP_SENSOR_POWER		GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
 
 /*
  * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
  * signal.
  */
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_SEQ_EC_ALL_SYS_PG
-#define GPIO_PG_EC_DSW_PWROK		GPIO_SEQ_EC_DSW_PWROK
-#define GPIO_PG_EC_RSMRST_ODL		GPIO_SEQ_EC_RSMRST_ODL
-#define GPIO_POWER_BUTTON_L		GPIO_GSC_EC_PWR_BTN_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_ODL
-#define GPIO_RECOVERY_L			GPIO_EC_RECOVERY_BTN_OD
-#define GPIO_RECOVERY_L_2		GPIO_GSC_EC_RECOVERY_BTN_OD
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
+#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_OD
+#define GPIO_RECOVERY_L_2 GPIO_GSC_EC_RECOVERY_BTN_OD
 
 /* I2C Bus Configuration */
 
-#define I2C_PORT_DP_REDRIVER		NPCX_I2C_PORT0_0
-
-#define I2C_PORT_USB_C0_C2_TCPC		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1_TCPC		NPCX_I2C_PORT4_1
+#define I2C_PORT_DP_REDRIVER NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0_C2_TCPC NPCX_I2C_PORT1_0
 
-#define I2C_PORT_USB_C0_C2_PPC		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_PPC		NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C0_C2_PPC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1
 
-#define I2C_PORT_USB_C0_C2_BC12		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_BC12		NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C0_C2_BC12 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1
 
-#define I2C_PORT_USB_C0_C2_MUX		NPCX_I2C_PORT3_0
-#define I2C_PORT_USB_C1_MUX		NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C0_C2_MUX NPCX_I2C_PORT3_0
+#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1
 
-#define I2C_PORT_QI			NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM			NPCX_I2C_PORT7_0
-#define I2C_PORT_MP2964			NPCX_I2C_PORT7_0
+#define I2C_PORT_QI NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0
 
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 
-#define I2C_ADDR_MP2964_FLAGS	0x20
+#define I2C_ADDR_MP2964_FLAGS 0x20
 
-#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR	0x58
-#define USBC_PORT_C2_BB_RETIMER_I2C_ADDR	0x59
+#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x58
+#define USBC_PORT_C2_BB_RETIMER_I2C_ADDR 0x59
 
 /* Enabling Thunderbolt-compatible mode */
 #define CONFIG_USB_PD_TBT_COMPAT_MODE
 
 /* Enabling USB4 mode */
 #define CONFIG_USB_PD_USB4
+#define CONFIG_USB_PD_DATA_RESET_MSG
 
 /* Retimer */
 #define CONFIG_USBC_RETIMER_FW_UPDATE
@@ -140,7 +133,7 @@
  * TODO(b/197478860): Enable the fan control. We need
  * to check the sensor value and adjust the fan speed.
  */
- #define CONFIG_FANS			FAN_CH_COUNT
+#define CONFIG_FANS FAN_CH_COUNT
 
 /* Include math_util for bitmask_uint64 used in pd_timers */
 #define CONFIG_MATH_UTIL
@@ -153,14 +146,12 @@
 
 #ifndef __ASSEMBLER__
 
-#include "gpio_signal.h"	/* needed by registers.h */
+#include "gpio_signal.h" /* needed by registers.h */
 #include "registers.h"
 #include "usbc_config.h"
 
 enum charge_port {
 	CHARGE_PORT_TYPEC0,
-	CHARGE_PORT_TYPEC1,
-	CHARGE_PORT_TYPEC2,
 	CHARGE_PORT_BARRELJACK,
 	CHARGE_PORT_ENUM_COUNT
 };
@@ -171,7 +162,7 @@ enum adc_channel {
 	ADC_TEMP_SENSOR_3_WIFI,
 	ADC_TEMP_SENSOR_4_DIMM,
 	ADC_VBUS,
-	ADC_PPVAR_IMON,              /* ADC3 */
+	ADC_PPVAR_IMON, /* ADC3 */
 	ADC_CH_COUNT
 };
 
@@ -183,28 +174,16 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum ioex_port {
-	IOEX_C0_NCT38XX = 0,
-	IOEX_C2_NCT38XX,
-	IOEX_PORT_COUNT
-};
-
 enum pwm_channel {
-	PWM_CH_LED_GREEN,		/* PWM0 */
-	PWM_CH_FAN,                     /* PWM5 */
-	PWM_CH_LED_RED,                 /* PWM2 */
+	PWM_CH_LED_GREEN, /* PWM0 */
+	PWM_CH_FAN, /* PWM5 */
+	PWM_CH_LED_RED, /* PWM2 */
 	PWM_CH_COUNT
 };
 
-enum fan_channel {
-	FAN_CH_0 = 0,
-	FAN_CH_COUNT
-};
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT };
 
-enum mft_channel {
-	MFT_CH_0 = 0,
-	MFT_CH_COUNT
-};
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT };
 
 extern void adp_connect_interrupt(enum gpio_signal signal);
 
diff --git a/board/kuldax/build.mk b/board/kuldax/build.mk
index 9c668e0e2a..3de758d1bd 100644
--- a/board/kuldax/build.mk
+++ b/board/kuldax/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/kuldax/ec.tasklist b/board/kuldax/ec.tasklist
index 0688607266..23218133a8 100644
--- a/board/kuldax/ec.tasklist
+++ b/board/kuldax/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,8 +22,5 @@
 	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
 	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
 	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C2, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C0, pd_shared_alert_task, (BIT(2) | BIT(0)), LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, LARGER_TASK_STACK_SIZE) \
 	TASK_ALWAYS(CEC, cec_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/kuldax/fans.c b/board/kuldax/fans.c
index f2a70636d0..a2acd805f8 100644
--- a/board/kuldax/fans.c
+++ b/board/kuldax/fans.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,7 +25,7 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 static const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
@@ -37,9 +37,9 @@ static const struct fan_conf fan_conf_0 = {
  * Set minimum at around 30% PWM.
  */
 static const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 2200,
-	.rpm_start = 2200,
-	.rpm_max = 7200,
+	.rpm_min = 2400,
+	.rpm_start = 2400,
+	.rpm_max = 4500,
 };
 
 const struct fan_t fans[FAN_CH_COUNT] = {
diff --git a/board/kuldax/fw_config.c b/board/kuldax/fw_config.c
index a5857ef48f..4229f3bed1 100644
--- a/board/kuldax/fw_config.c
+++ b/board/kuldax/fw_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,7 +10,7 @@
 #include "cros_board_info.h"
 #include "fw_config.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 static union brask_cbi_fw_config fw_config;
 BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
@@ -31,13 +31,21 @@ static const struct {
 	int voltage;
 	int current;
 } bj_power[] = {
-	[BJ_135W] = { /* 0 - 135W (also default) */
-			.voltage = 19500,
-			.current = 6920
+	[BJ_150W] = { /* 0 - 150W (also default)*/
+			.voltage = 20000,
+			.current = 7500
 	},
 	[BJ_230W] = { /* 1 - 230W */
 			.voltage = 19500,
 			.current = 11800
+	},
+	[BJ_65W] = { /* 2 - 65W */
+			.voltage = 19000,
+			.current = 3420
+	},
+	[BJ_135W] = { /* 4 - 135W */
+			.voltage = 19500,
+			.current = 6920
 	}
 };
 
diff --git a/board/kuldax/fw_config.h b/board/kuldax/fw_config.h
index 5ddb3b02a1..d7fa0a11a9 100644
--- a/board/kuldax/fw_config.h
+++ b/board/kuldax/fw_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,15 +13,9 @@
  *
  * Source of truth is the project/brask/brask/config.star configuration file.
  */
-enum ec_cfg_audio_type {
-	DB_AUDIO_UNKNOWN = 0,
-	DB_NAU88L25B_I2S = 1
-};
+enum ec_cfg_audio_type { DB_AUDIO_UNKNOWN = 0, DB_NAU88L25B_I2S = 1 };
 
-enum ec_cfg_bj_power {
-	BJ_135W = 0,
-	BJ_230W = 1
-};
+enum ec_cfg_bj_power { BJ_150W = 0, BJ_230W = 1, BJ_65W = 2, BJ_135W = 3 };
 
 union brask_cbi_fw_config {
 	struct {
diff --git a/board/kuldax/gpio.inc b/board/kuldax/gpio.inc
index 617463b7f6..253d9b7fc3 100644
--- a/board/kuldax/gpio.inc
+++ b/board/kuldax/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2022 The Chromium OS Authors. All rights reserved.
+ * Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,12 +21,6 @@ GPIO_INT(USB_C0_BC12_INT_ODL,        PIN(C, 6), GPIO_INT_FALLING, bc12_interrupt
 GPIO_INT(USB_C0_C2_TCPC_INT_ODL,     PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)
 GPIO_INT(USB_C0_PPC_INT_ODL,         PIN(6, 2), GPIO_INT_FALLING, ppc_interrupt)
 GPIO_INT(USB_C0_RT_INT_ODL,          PIN(B, 1), GPIO_INT_FALLING, retimer_interrupt)
-GPIO_INT(USB_C1_BC12_INT_ODL,        PIN(5, 0), GPIO_INT_FALLING, bc12_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,         PIN(F, 5), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C1_TCPC_INT_ODL,        PIN(A, 2), GPIO_INT_FALLING, tcpc_alert_event)
-GPIO_INT(USB_C2_BC12_INT_ODL,        PIN(8, 3), GPIO_INT_FALLING, bc12_interrupt)
-GPIO_INT(USB_C2_PPC_INT_ODL,         PIN(7, 0), GPIO_INT_FALLING, ppc_interrupt)
-GPIO_INT(USB_C2_RT_INT_ODL,          PIN(4, 1), GPIO_INT_FALLING, retimer_interrupt)
 GPIO_INT(BJ_ADP_PRESENT_ODL,         PIN(8, 2), GPIO_INT_BOTH | GPIO_PULL_UP, adp_connect_interrupt)
 GPIO_INT(EC_RECOVERY_BTN_OD,         PIN(2, 3), GPIO_INT_BOTH, button_interrupt)
 GPIO_INT(HDMI_CONN_OC_ODL,           PIN(2, 4), GPIO_INPUT | GPIO_INT_BOTH, port_ocp_interrupt)
@@ -79,13 +73,6 @@ GPIO(CPU_C10_GATE_L,                 PIN(6, 7), GPIO_INPUT)
 GPIO(EC_PCH_PWR_BTN_ODL,             PIN(C, 1), GPIO_ODR_HIGH)
 GPIO(GSC_EC_RECOVERY_BTN_OD,         PIN(2, 2), GPIO_INPUT)
 
-/* NFC */
-/* TODO(b/194068530): Enable NFC */
-GPIO(NFC_COIL_ACT_L,                 PIN(D, 4), GPIO_INPUT)
-GPIO(NFC_LOW_POWER_MODE,             PIN(9, 5), GPIO_OUT_HIGH)
-GPIO(NFC_CARD_DET_L,                 PIN(A, 3), GPIO_INPUT)
-GPIO(EN_NFC_BUZZER,                  PIN(0, 5), GPIO_OUT_LOW)
-
 /* Wireless Charger */
 GPIO(EC_QI_PWR,                      PIN(D, 2), GPIO_OUT_LOW)
 GPIO(QI_RESET_L,                     PIN(9, 3), GPIO_OUT_HIGH)
@@ -111,19 +98,14 @@ GPIO(EC_I2C_USB_C0_C2_TCPC_SCL,      PIN(9, 0), GPIO_INPUT)
 GPIO(EC_I2C_USB_C0_C2_TCPC_SDA,      PIN(8, 7), GPIO_INPUT)
 GPIO(EC_I2C_USB_C1_MIX_SCL,          PIN(E, 4), GPIO_INPUT)
 GPIO(EC_I2C_USB_C1_MIX_SDA,          PIN(E, 3), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_TCPC_SCL,         PIN(F, 3), GPIO_INPUT)
-GPIO(EC_I2C_USB_C1_TCPC_SDA,         PIN(F, 2), GPIO_INPUT)
 
 /* USBA */
 GPIO(EN_PP5000_USBA,                 PIN(D, 7), GPIO_OUT_LOW)
 GPIO(USB_A0_STATUS_L,                PIN(2, 1), GPIO_INPUT)
 GPIO(USB_A1_STATUS_L,                PIN(2, 0), GPIO_INPUT)
-GPIO(USB_A2_STATUS_L,                PIN(1, 7), GPIO_INPUT)
-GPIO(USB_A3_STATUS_L,                PIN(1, 6), GPIO_INPUT)
 GPIO(USB_A_LOW_PWR0_OD,              PIN(1, 5), GPIO_INPUT | GPIO_PULL_DOWN)
 GPIO(USB_A_LOW_PWR1_OD,              PIN(1, 4), GPIO_INPUT | GPIO_PULL_DOWN)
 GPIO(USB_A_LOW_PWR2_OD,              PIN(1, 1), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(USB_A_LOW_PWR3_OD,              PIN(1, 0), GPIO_INPUT | GPIO_PULL_DOWN)
 GPIO(USB_A_OC_SOC_L,                 PIN(8, 0), GPIO_OUT_HIGH)
 
 /* LED */
@@ -132,22 +114,9 @@ GPIO(LED_GREEN_L,                    PIN(C, 3), GPIO_OUT_LOW)
 GPIO(LED_RED_L,                      PIN(C, 4), GPIO_OUT_LOW)
 
 /* USBC */
-GPIO(USB_C0_C2_TCPC_RST_ODL,         PIN(A, 7), GPIO_ODR_LOW)
-GPIO(USB_C1_FRS_EN,                  PIN(9, 4), GPIO_OUT_LOW)
+GPIO(USB_C0_FRS_EN,                  PIN(A, 3), GPIO_OUT_LOW)
 GPIO(USB_C1_RT_INT_ODL,              PIN(A, 0), GPIO_INPUT)
-GPIO(USB_C1_RT_RST_R_L,              PIN(0, 2), GPIO_OUT_LOW)
-
-/* GPIO02_P2 to PU */
-/* GPIO03_P2 to PU */
-IOEX(USB_C0_OC_ODL,          EXPIN(IOEX_C0_NCT38XX, 0, 4), GPIO_ODR_HIGH)
-IOEX(USB_C0_FRS_EN,          EXPIN(IOEX_C0_NCT38XX, 0, 6), GPIO_LOW)
-IOEX(USB_C0_RT_RST_ODL,      EXPIN(IOEX_C0_NCT38XX, 0, 7), GPIO_ODR_LOW)
-
-IOEX(USB_C2_RT_RST_ODL,      EXPIN(IOEX_C2_NCT38XX, 0, 2), GPIO_ODR_LOW)
-IOEX(USB_C1_OC_ODL,          EXPIN(IOEX_C2_NCT38XX, 0, 3), GPIO_ODR_HIGH)
-IOEX(USB_C2_OC_ODL,          EXPIN(IOEX_C2_NCT38XX, 0, 4), GPIO_ODR_HIGH)
-IOEX(USB_C2_FRS_EN,          EXPIN(IOEX_C2_NCT38XX, 0, 6), GPIO_LOW)
-/* GPIO07_P2 to PU */
+GPIO(USB_C0_RT_RST_ODL,              PIN(9, 5), GPIO_ODR_LOW)
 
 /* UART alternate functions */
 ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)              /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */
@@ -173,15 +142,31 @@ ALTERNATE(PIN_MASK(4, 0x38), 0, MODULE_ADC, 0)               /* GPIO45/ADC0, GPI
 ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0)               /* GPIOE1/ADC7 */
 
 /* Unused Pins */
-UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
+UNUSED(PIN(0, 2))       /* GPIO02/PSL_IN4 */
+UNUSED(PIN(0, 4))       /* KSO13/GPIO04 */
+UNUSED(PIN(0, 5))       /* KSO13/GPIO05 */
+UNUSED(PIN(0, 6))       /* KSO11/GPIO06/P80_CLK */
+UNUSED(PIN(1, 0))       /* KSO9/GPIO10/CR_SIN1 */
+UNUSED(PIN(1, 2))       /* KSO07/GPO12/JEN# */
+UNUSED(PIN(1, 3))       /* KSO06/GPO13/GP_SEL# */
+UNUSED(PIN(1, 6))       /* KSO3/GPIO16 */
+UNUSED(PIN(1, 7))       /* KSO2/GPIO17/JTAG_TDI */
 UNUSED(PIN(3, 2))       /* GPO32/TRIS_L */
 UNUSED(PIN(3, 5))       /* GPO35/CR_SOUT4/TEST_L */
+UNUSED(PIN(4, 1))       /* GPIO41/ADC4 */
+UNUSED(PIN(5, 0))       /* GPIO50 */
+UNUSED(PIN(5, 6))       /* GPIO56/CLKRUN# */
 UNUSED(PIN(6, 6))       /* GPIO66 */
+UNUSED(PIN(7, 0))       /* GPIO70/PS2_DAT0*/
 UNUSED(PIN(8, 1))       /* GPIO81/PECI_DATA */
-UNUSED(PIN(5, 6))       /* GPIO56/CLKRUN# */
-UNUSED(PIN(9, 7))       /* GPIO97 */
+UNUSED(PIN(8, 3))       /* KSO15/GPIO83 */
 UNUSED(PIN(8, 6))       /* GPIO86/TXD/CR_SOUT2 */
-UNUSED(PIN(1, 3))       /* KSO06/GPO13/GP_SEL# */
-UNUSED(PIN(1, 2))       /* KSO07/GPO12/JEN# */
-UNUSED(PIN(0, 6))       /* KSO11/GPIO06/P80_CLK */
-UNUSED(PIN(0, 4))       /* KSO13/GPIO04 */
+UNUSED(PIN(9, 7))       /* GPIO97 */
+UNUSED(PIN(9, 4))       /* GPIO94*/
+UNUSED(PIN(A, 2))       /* F_SCLK/GPIOA2 */
+UNUSED(PIN(A, 7))       /* GPIOA7 */
+UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
+UNUSED(PIN(D, 4))       /* GPIOD4/CR_SIN3 */
+UNUSED(PIN(F, 2))       /* GPIOF2/I2C4_SDA1*/
+UNUSED(PIN(F, 3))       /* GPIOF3/I2C4_SCL1*/
+UNUSED(PIN(F, 5))       /* GPIOF5/I2C5_SCL1*/
diff --git a/board/kuldax/i2c.c b/board/kuldax/i2c.c
index 9c92852461..b38080f6a5 100644
--- a/board/kuldax/i2c.c
+++ b/board/kuldax/i2c.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -43,14 +43,6 @@ const struct i2c_port_t i2c_ports[] = {
 		.sda = GPIO_EC_I2C_USB_C0_C2_RT_SDA,
 	},
 	{
-		/* I2C4 C1 TCPC */
-		.name = "tcpc1",
-		.port = I2C_PORT_USB_C1_TCPC,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_USB_C1_TCPC_SCL,
-		.sda = GPIO_EC_I2C_USB_C1_TCPC_SDA,
-	},
-	{
 		/* I2C5 */
 		.name = "wireless_charger",
 		.port = I2C_PORT_QI,
diff --git a/board/kuldax/led.c b/board/kuldax/led.c
index c5e74d29c2..842cee0530 100644
--- a/board/kuldax/led.c
+++ b/board/kuldax/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,16 +19,16 @@
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
 
 /*
  * Due to the CSME-Lite processing, upon startup the CPU transitions through
  * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so
  * delay turning off the LED during suspend/shutdown.
  */
-#define LED_CPU_DELAY_MS	(2000 * MSEC)
+#define LED_CPU_DELAY_MS (2000 * MSEC)
 
-const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 enum led_color {
@@ -84,9 +84,9 @@ static int set_color(enum ec_led_id id, enum led_color color, int duty)
 	}
 }
 
-#define LED_PULSE_US		(2 * SECOND)
+#define LED_PULSE_US (2 * SECOND)
 /* 40 msec for nice and smooth transition. */
-#define LED_PULSE_TICK_US	(40 * MSEC)
+#define LED_PULSE_TICK_US (40 * MSEC)
 
 /*
  * When pulsing is enabled, brightness is incremented by <duty_inc> every
@@ -206,7 +206,7 @@ void show_critical_error(void)
 		set_color(EC_LED_ID_POWER_LED, LED_RED, 100);
 }
 
-static int command_led(int argc, char **argv)
+static int command_led(int argc, const char **argv)
 {
 	enum ec_led_id id = EC_LED_ID_POWER_LED;
 
@@ -231,8 +231,7 @@ static int command_led(int argc, char **argv)
 	}
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(led, command_led,
-			"[debug|red|green|off|alert|crit]",
+DECLARE_CONSOLE_COMMAND(led, command_led, "[debug|red|green|off|alert|crit]",
 			"Turn on/off LED.");
 
 void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
@@ -250,10 +249,10 @@ int led_set_brightness(enum ec_led_id id, const uint8_t *brightness)
 	else
 		return set_color(id, LED_OFF, 0);
 }
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-				int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
-  /* Blink alert if insufficient power per system_can_boot_ap(). */
+	/* Blink alert if insufficient power per system_can_boot_ap(). */
 	int insufficient_power =
 		(charge_ma * charge_mv) <
 		(CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON * 1000);
diff --git a/board/kuldax/pwm.c b/board/kuldax/pwm.c
index 125d507a82..fe7e82894a 100644
--- a/board/kuldax/pwm.c
+++ b/board/kuldax/pwm.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,21 +11,16 @@
 #include "pwm_chip.h"
 
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED_GREEN] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 2000
-	},
-	[PWM_CH_FAN] = {
-		.channel = 5,
-		.flags = PWM_CONFIG_OPEN_DRAIN | PWM_CONFIG_DSLEEP,
-		.freq = 1000
-	},
-	[PWM_CH_LED_RED] = {
-		.channel = 2,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 2000
-	},
+	[PWM_CH_LED_GREEN] = { .channel = 0,
+			       .flags = PWM_CONFIG_ACTIVE_LOW |
+					PWM_CONFIG_DSLEEP,
+			       .freq = 2000 },
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
+	[PWM_CH_LED_RED] = { .channel = 2,
+			     .flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+			     .freq = 2000 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
diff --git a/board/kuldax/sensors.c b/board/kuldax/sensors.c
index 8455a8fbc2..96f49de8a3 100644
--- a/board/kuldax/sensors.c
+++ b/board/kuldax/sensors.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -58,65 +58,60 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* Temperature sensor configuration */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1_CPU] = {
-		.name = "CPU",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_1_CPU
-	},
-	[TEMP_SENSOR_2_CPU_VR] = {
-		.name = "CPU VR",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_2_CPU_VR
-	},
-	[TEMP_SENSOR_3_WIFI] = {
-		.name = "WIFI",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_3_WIFI
-	},
-	[TEMP_SENSOR_4_DIMM] = {
-		.name = "DIMM",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_4_DIMM
-	},
+	[TEMP_SENSOR_1_CPU] = { .name = "CPU",
+				.type = TEMP_SENSOR_TYPE_BOARD,
+				.read = get_temp_3v3_30k9_47k_4050b,
+				.idx = ADC_TEMP_SENSOR_1_CPU },
+	[TEMP_SENSOR_2_CPU_VR] = { .name = "CPU VR",
+				   .type = TEMP_SENSOR_TYPE_BOARD,
+				   .read = get_temp_3v3_30k9_47k_4050b,
+				   .idx = ADC_TEMP_SENSOR_2_CPU_VR },
+	[TEMP_SENSOR_3_WIFI] = { .name = "WIFI",
+				 .type = TEMP_SENSOR_TYPE_BOARD,
+				 .read = get_temp_3v3_30k9_47k_4050b,
+				 .idx = ADC_TEMP_SENSOR_3_WIFI },
+	[TEMP_SENSOR_4_DIMM] = { .name = "DIMM",
+				 .type = TEMP_SENSOR_TYPE_BOARD,
+				 .read = get_temp_3v3_30k9_47k_4050b,
+				 .idx = ADC_TEMP_SENSOR_4_DIMM },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
 /*
- * TODO(b/180681346): update for Alder Lake/brya
- *
- * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
- * 130 C.  However, sensor is located next to DDR, so we need to use the lower
- * DDR temperature limit (85 C)
+ * TODO(b/238260272): add the thermal sensor setting
  */
-/*
- * TODO(b/202062363): Remove when clang is fixed.
- */
-#define THERMAL_CPU \
-	{ \
+#define THERMAL_CPU              \
+	{                        \
 		.temp_host = { \
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
-			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(90), \
 		}, \
 		.temp_host_release = { \
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(70), \
 		}, \
 		.temp_fan_off = C_TO_K(35), \
-		.temp_fan_max = C_TO_K(50), \
+		.temp_fan_max = C_TO_K(89), \
 	}
 __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 
-/*
- * TODO(b/197478860): add the thermal sensor setting
- */
-/* this should really be "const" */
+#define THERMAL_FAN              \
+	{                        \
+		.temp_host = { \
+			[EC_TEMP_THRESH_HIGH] = 0, \
+			[EC_TEMP_THRESH_HALT] = 0, \
+		}, \
+		.temp_host_release = { \
+			[EC_TEMP_THRESH_HIGH] = 0, \
+		}, \
+		.temp_fan_off = 0, \
+		.temp_fan_max = 0, \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_fan = THERMAL_FAN;
+
 struct ec_thermal_config thermal_params[] = {
 	[TEMP_SENSOR_1_CPU] = THERMAL_CPU,
-	[TEMP_SENSOR_2_CPU_VR] = THERMAL_CPU,
-	[TEMP_SENSOR_3_WIFI] = THERMAL_CPU,
-	[TEMP_SENSOR_4_DIMM] = THERMAL_CPU,
+	[TEMP_SENSOR_2_CPU_VR] = THERMAL_FAN,
+	[TEMP_SENSOR_3_WIFI] = THERMAL_FAN,
+	[TEMP_SENSOR_4_DIMM] = THERMAL_FAN,
 };
 BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
diff --git a/board/kuldax/usbc_config.c b/board/kuldax/usbc_config.c
index fddc9a449c..c0d34fc581 100644
--- a/board/kuldax/usbc_config.c
+++ b/board/kuldax/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,14 +13,12 @@
 #include "driver/ppc/syv682x_public.h"
 #include "driver/retimer/bb_retimer_public.h"
 #include "driver/retimer/kb800x.h"
-#include "driver/tcpm/nct38xx.h"
 #include "driver/tcpm/rt1715.h"
 #include "driver/tcpm/tcpci.h"
 #include "ec_commands.h"
 #include "gpio.h"
 #include "gpio_signal.h"
 #include "hooks.h"
-#include "ioexpander.h"
 #include "system.h"
 #include "task.h"
 #include "task_id.h"
@@ -32,175 +30,70 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 /* USBC TCPC configuration */
-const struct tcpc_config_t tcpc_config[] = {
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USBC_PORT_C0] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
 			.port = I2C_PORT_USB_C0_C2_TCPC,
-			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		},
-		.drv = &nct38xx_tcpm_drv,
-		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
-			TCPC_FLAGS_NO_DEBUG_ACC_CONTROL,
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C1_TCPC,
 			.addr_flags = RT1715_I2C_ADDR_FLAGS,
 		},
 		.drv = &rt1715_tcpm_drv,
 	},
-	[USBC_PORT_C2] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0_C2_TCPC,
-			.addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS,
-		},
-		.drv = &nct38xx_tcpm_drv,
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-	},
 };
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
 
 /* USBC PPC configuration */
-struct ppc_config_t ppc_chips[] = {
+struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USBC_PORT_C0] = {
 		.i2c_port = I2C_PORT_USB_C0_C2_PPC,
 		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
 		.drv = &syv682x_drv,
 	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1_PPC,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
-	},
-	[USBC_PORT_C2] = {
-		.i2c_port = I2C_PORT_USB_C0_C2_PPC,
-		.i2c_addr_flags = SYV682X_ADDR2_FLAGS,
-		.drv = &syv682x_drv,
-	},
 };
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
 
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
 /* USBC mux configuration - Alder Lake includes internal mux */
-static const struct usb_mux usbc0_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-static const struct usb_mux usbc1_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-static const struct usb_mux usbc2_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C2,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-
-struct kb800x_control_t kb800x_control[] = {
-	[USBC_PORT_C0] = {
-	},
-	[USBC_PORT_C1] = {
-		.retimer_rst_gpio = GPIO_USB_C1_RT_RST_R_L,
-		.ss_lanes = {
-			[KB800X_A0] = KB800X_TX0, [KB800X_A1] = KB800X_RX0,
-			[KB800X_B0] = KB800X_RX1, [KB800X_B1] = KB800X_TX1,
-			[KB800X_C0] = KB800X_RX0, [KB800X_C1] = KB800X_TX0,
-			[KB800X_D0] = KB800X_TX1, [KB800X_D1] = KB800X_RX1,
-			}
-	},
-	[USBC_PORT_C2] = {
-	},
+static const struct usb_mux_chain usbc0_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
-BUILD_ASSERT(ARRAY_SIZE(kb800x_control) == USBC_PORT_COUNT);
 
-const struct usb_mux usb_muxes[] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C0_C2_MUX,
-		.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc0_tcss_usb_mux,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &kb800x_usb_mux_driver,
-		.i2c_port = I2C_PORT_USB_C1_MUX,
-		.i2c_addr_flags = KB800X_I2C_ADDR0_FLAGS,
-		.next_mux = &usbc1_tcss_usb_mux,
-	},
-	[USBC_PORT_C2] = {
-		.usb_port = USBC_PORT_C2,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C0_C2_MUX,
-		.i2c_addr_flags = USBC_PORT_C2_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc2_tcss_usb_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C0_C2_MUX,
+			.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc0_tcss_usb_mux,
 	},
 };
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
 
 /* BC1.2 charger detect configuration */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+const struct pi3usb9201_config_t
+	pi3usb9201_bc12_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USBC_PORT_C0] = {
 		.i2c_port = I2C_PORT_USB_C0_C2_BC12,
 		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
 	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1_BC12,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	[USBC_PORT_C2] = {
-		.i2c_port = I2C_PORT_USB_C0_C2_BC12,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_1_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-/*
- * USB C0 and C2 uses burnside bridge chips and have their reset
- * controlled by their respective TCPC chips acting as GPIO expanders.
- *
- * ioex_init() is normally called before we take the TCPCs out of
- * reset, so we need to start in disabled mode, then explicitly
- * call ioex_init().
- */
-
-struct ioexpander_config_t ioex_config[] = {
-	[IOEX_C0_NCT38XX] = {
-		.i2c_host_port = I2C_PORT_USB_C0_C2_TCPC,
-		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		.drv = &nct38xx_ioexpander_drv,
-		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
-	},
-	[IOEX_C2_NCT38XX] = {
-		.i2c_host_port = I2C_PORT_USB_C0_C2_TCPC,
-		.i2c_addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS,
-		.drv = &nct38xx_ioexpander_drv,
-		.flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED,
-	},
 };
-BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT);
 
 __override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
 {
-	enum ioex_signal rst_signal;
+	enum gpio_signal rst_signal;
 
 	if (me->usb_port == USBC_PORT_C0) {
-		rst_signal = IOEX_USB_C0_RT_RST_ODL;
-	} else if (me->usb_port == USBC_PORT_C2) {
-		rst_signal = IOEX_USB_C2_RT_RST_ODL;
+		rst_signal = GPIO_USB_C0_RT_RST_ODL;
 	} else {
 		return EC_ERROR_INVAL;
 	}
@@ -217,14 +110,14 @@ __override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
 		 * retimer_init() function ensures power is up before calling
 		 * this function.
 		 */
-		ioex_set_level(rst_signal, 1);
+		gpio_set_level(rst_signal, 1);
 		/*
 		 * Allow 1ms time for the retimer to power up lc_domain
 		 * which powers I2C controller within retimer
 		 */
 		msleep(1);
 	} else {
-		ioex_set_level(rst_signal, 0);
+		gpio_set_level(rst_signal, 0);
 		msleep(1);
 	}
 	return EC_SUCCESS;
@@ -246,34 +139,9 @@ __override int bb_retimer_reset(const struct usb_mux *me)
 
 void board_reset_pd_mcu(void)
 {
-	enum gpio_signal tcpc_rst;
-
-	tcpc_rst = GPIO_USB_C0_C2_TCPC_RST_ODL;
-
 	/*
 	 * TODO(b/179648104): figure out correct timing
 	 */
-
-	gpio_set_level(tcpc_rst, 0);
-	gpio_set_level(GPIO_USB_C1_RT_RST_R_L, 0);
-
-	/*
-	 * delay for power-on to reset-off and min. assertion time
-	 */
-
-	msleep(20);
-
-	gpio_set_level(tcpc_rst, 1);
-	gpio_set_level(GPIO_USB_C1_RT_RST_R_L, 1);
-
-	/* wait for chips to come up */
-
-	msleep(50);
-}
-
-static void enable_ioex(int ioex)
-{
-	ioex_init(ioex);
 }
 
 static void board_tcpc_init(void)
@@ -281,25 +149,13 @@ static void board_tcpc_init(void)
 	/* Don't reset TCPCs after initial reset */
 	if (!system_jumped_late()) {
 		board_reset_pd_mcu();
-
-		/*
-		 * These IO expander pins are implemented using the
-		 * C0/C2 TCPC, so they must be set up after the TCPC has
-		 * been taken out of reset.
-		 */
-		enable_ioex(IOEX_C0_NCT38XX);
-		enable_ioex(IOEX_C2_NCT38XX);
 	}
 
 	/* Enable PPC interrupts. */
 	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C2_PPC_INT_ODL);
 
 	/* Enable TCPC interrupts. */
 	gpio_enable_interrupt(GPIO_USB_C0_C2_TCPC_INT_ODL);
-
-	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
 }
 DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
 
@@ -310,9 +166,6 @@ uint16_t tcpc_get_alert_status(void)
 	if (gpio_get_level(GPIO_USB_C0_C2_TCPC_INT_ODL) == 0)
 		status |= PD_STATUS_TCPC_ALERT_0 | PD_STATUS_TCPC_ALERT_2;
 
-	if (gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL) == 0)
-		status |= PD_STATUS_TCPC_ALERT_1;
-
 	return status;
 }
 
@@ -320,10 +173,6 @@ int ppc_get_alert_status(int port)
 {
 	if (port == USBC_PORT_C0)
 		return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0;
-	else if (port == USBC_PORT_C1)
-		return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0;
-	else if (port == USBC_PORT_C2)
-		return gpio_get_level(GPIO_USB_C2_PPC_INT_ODL) == 0;
 	return 0;
 }
 
@@ -333,9 +182,6 @@ void tcpc_alert_event(enum gpio_signal signal)
 	case GPIO_USB_C0_C2_TCPC_INT_ODL:
 		schedule_deferred_pd_interrupt(USBC_PORT_C0);
 		break;
-	case GPIO_USB_C1_TCPC_INT_ODL:
-		schedule_deferred_pd_interrupt(USBC_PORT_C1);
-		break;
 	default:
 		break;
 	}
@@ -347,12 +193,6 @@ void bc12_interrupt(enum gpio_signal signal)
 	case GPIO_USB_C0_BC12_INT_ODL:
 		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
 		break;
-	case GPIO_USB_C1_BC12_INT_ODL:
-		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
-		break;
-	case GPIO_USB_C2_BC12_INT_ODL:
-		usb_charger_task_set_event(2, USB_CHG_EVENT_BC12);
-		break;
 	default:
 		break;
 	}
@@ -364,12 +204,6 @@ void ppc_interrupt(enum gpio_signal signal)
 	case GPIO_USB_C0_PPC_INT_ODL:
 		syv682x_interrupt(USBC_PORT_C0);
 		break;
-	case GPIO_USB_C1_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C1);
-		break;
-	case GPIO_USB_C2_PPC_INT_ODL:
-		syv682x_interrupt(USBC_PORT_C2);
-		break;
 	default:
 		break;
 	}
diff --git a/board/kuldax/usbc_config.h b/board/kuldax/usbc_config.h
index 1ccb5f0a71..7a212f8fb6 100644
--- a/board/kuldax/usbc_config.h
+++ b/board/kuldax/usbc_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,13 +8,8 @@
 #ifndef __CROS_EC_USBC_CONFIG_H
 #define __CROS_EC_USBC_CONFIG_H
 
-#define CONFIG_USB_PD_PORT_MAX_COUNT	3
+#define CONFIG_USB_PD_PORT_MAX_COUNT 1
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_C2,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_COUNT };
 
 #endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/lalala/battery.c b/board/lalala/battery.c
index 326ac93a6b..4edf5fa864 100644
--- a/board/lalala/battery.c
+++ b/board/lalala/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/lalala/board.c b/board/lalala/board.c
index 59eb9fd4a8..78404d6821 100644
--- a/board/lalala/board.c
+++ b/board/lalala/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -51,13 +51,13 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 #define INT_RECHECK_US 5000
 
-#define ADC_VOL_UP_MASK     BIT(0)
-#define ADC_VOL_DOWN_MASK   BIT(1)
+#define ADC_VOL_UP_MASK BIT(0)
+#define ADC_VOL_DOWN_MASK BIT(1)
 
 static uint8_t new_adc_key_state;
 
@@ -110,8 +110,8 @@ static const struct ec_response_keybd_config lalala_keybd = {
 	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
 };
 
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	return &lalala_keybd;
 }
@@ -152,7 +152,6 @@ static void usb_c0_interrupt(enum gpio_signal s)
 
 	/* Check the line again in 5ms */
 	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-
 }
 
 /* C1 interrupt line shared by BC 1.2, TCPC, and charger */
@@ -226,22 +225,22 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* Thermistors */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_A \
-	{ \
+#define THERMAL_A                \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = 0, \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
@@ -258,8 +257,8 @@ __maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_B \
-	{ \
+#define THERMAL_B                \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = 0, \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(73), \
@@ -334,13 +333,11 @@ int board_is_sourcing_vbus(int port)
 
 	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
 	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
-
 }
 
 int board_set_active_charge_port(int port)
 {
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	int i;
 	int old_port;
 
@@ -400,8 +397,8 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
 
@@ -426,18 +423,13 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrices to rotate accelerometers into the standard reference. */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					      { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
 
 /* BMA253 private data */
 static struct accelgyro_saved_data_t g_bma253_data;
@@ -445,11 +437,9 @@ static struct accelgyro_saved_data_t g_bma253_data;
 /* BMI160 private data */
 static struct bmi_drv_data_t g_bmi160_data;
 
-static const mat33_fp_t base_icm_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t base_icm_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					 { 0, FLOAT_TO_FP(1), 0 },
+					 { 0, 0, FLOAT_TO_FP(-1) } };
 
 /* ICM426 private data */
 static struct icm_drv_data_t g_icm426xx_data;
@@ -633,7 +623,7 @@ void board_init(void)
 		gmr_tablet_switch_disable();
 		/* Base accel is not stuffed, don't allow line to float */
 		gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L,
-		GPIO_INPUT | GPIO_PULL_DOWN);
+			       GPIO_INPUT | GPIO_PULL_DOWN);
 	}
 
 	/* Turn on 5V if the system is on, otherwise turn it off. */
@@ -648,20 +638,19 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
 void motion_interrupt(enum gpio_signal signal)
 {
-		switch (get_cbi_ssfc_base_sensor()) {
-		case SSFC_SENSOR_ICM426XX:
-			icm426xx_interrupt(signal);
-			break;
-		case SSFC_SENSOR_BMI160:
-		default:
-			bmi160_interrupt(signal);
-			break;
-		}
+	switch (get_cbi_ssfc_base_sensor()) {
+	case SSFC_SENSOR_ICM426XX:
+		icm426xx_interrupt(signal);
+		break;
+	case SSFC_SENSOR_BMI160:
+	default:
+		bmi160_interrupt(signal);
+		break;
+	}
 }
 
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
+__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+				       int *ki_div, int *kd, int *kd_div)
 {
 	*kp = 1;
 	*kp_div = 20;
@@ -737,18 +726,24 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
-		.driver = &pi3usb3x532_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
+				.driver = &pi3usb3x532_usb_mux_driver,
+			},
 	},
 	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PS8802_I2C_ADDR_FLAGS_CUSTOM,
-		.driver = &ps8802_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_SUB_USB_C1,
+				.i2c_addr_flags = PS8802_I2C_ADDR_FLAGS_CUSTOM,
+				.driver = &ps8802_usb_mux_driver,
+			},
 	}
 };
 
diff --git a/board/lalala/board.h b/board/lalala/board.h
index c8f40d518d..4967e49752 100644
--- a/board/lalala/board.h
+++ b/board/lalala/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,11 +22,14 @@
 
 /* Charger */
 #define CONFIG_CHARGER_RAA489000
+#define PD_MAX_VOLTAGE_MV 20000
 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 #define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */
+#define CONFIG_OCPC_DEF_RBATT_MOHMS               \
+	22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \
+	    */
 #define CONFIG_OCPC
-#undef  CONFIG_CHARGER_SINGLE_CHIP
+#undef CONFIG_CHARGER_SINGLE_CHIP
 #undef CONFIG_CMD_CHARGER_DUMP
 #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
 #define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
@@ -44,7 +47,7 @@
 
 /* PWM */
 #define CONFIG_PWM
-#define NPCX7_PWM1_SEL    1  /* GPIO C2 is used as PWM1. */
+#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */
 
 /* Temp sensor */
 #define CONFIG_TEMP_SENSOR
@@ -81,16 +84,16 @@
 #define CONFIG_USB_PD_5V_EN_CUSTOM
 
 /* I2C configuration */
-#define I2C_PORT_EEPROM     NPCX_I2C_PORT7_0
-#define I2C_PORT_BATTERY    NPCX_I2C_PORT5_0
-#define I2C_PORT_SENSOR     NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0     NPCX_I2C_PORT1_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
 #define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_MUX    I2C_PORT_USB_C0
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0
 /* TODO(b:147440290): Need to handle multiple charger ICs */
-#define I2C_PORT_CHARGER    I2C_PORT_USB_C0
+#define I2C_PORT_CHARGER I2C_PORT_USB_C0
 
-#define I2C_PORT_ACCEL      I2C_PORT_SENSOR
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
 
 #define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */
 
@@ -99,15 +102,15 @@
 #define CONFIG_CMD_ACCEL_INFO
 #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
 
-#define CONFIG_ACCEL_BMA255		/* Lid accel */
-#define CONFIG_ACCELGYRO_BMI160		/* Base accel */
-#define CONFIG_ACCEL_KX022		/* Lid accel */
-#define CONFIG_ACCELGYRO_ICM426XX	/* Base accel second source*/
+#define CONFIG_ACCEL_BMA255 /* Lid accel */
+#define CONFIG_ACCELGYRO_BMI160 /* Base accel */
+#define CONFIG_ACCEL_KX022 /* Lid accel */
+#define CONFIG_ACCELGYRO_ICM426XX /* Base accel second source*/
 
 /* Lid operates in forced mode, base in FIFO */
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
 #define CONFIG_ACCEL_FIFO
-#define CONFIG_ACCEL_FIFO_SIZE 256	/* Must be a power of 2 */
+#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */
 #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
 
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
@@ -143,25 +146,16 @@ enum chg_id {
 };
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_1,     /* ADC0 */
-	ADC_TEMP_SENSOR_2,     /* ADC1 */
-	ADC_SUB_ANALOG,	       /* ADC2 */
-	ADC_VSNS_PP3300_A,     /* ADC9 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
+	ADC_SUB_ANALOG, /* ADC2 */
+	ADC_VSNS_PP3300_A, /* ADC9 */
 	ADC_CH_COUNT
 };
 
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_COUNT
-};
+enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT };
 
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
 enum pwm_channel {
 	PWM_CH_KBLIGHT,
diff --git a/board/lalala/build.mk b/board/lalala/build.mk
index b012d8d502..eb422dae93 100644
--- a/board/lalala/build.mk
+++ b/board/lalala/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/lalala/cbi_ssfc.c b/board/lalala/cbi_ssfc.c
index c4b859f133..81f3ee0dad 100644
--- a/board/lalala/cbi_ssfc.c
+++ b/board/lalala/cbi_ssfc.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
 
 enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
 {
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
 }
 
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
 {
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
 }
diff --git a/board/lalala/cbi_ssfc.h b/board/lalala/cbi_ssfc.h
index 935049b6ae..bf8853a43a 100644
--- a/board/lalala/cbi_ssfc.h
+++ b/board/lalala/cbi_ssfc.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -56,5 +56,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
  */
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
 
-
 #endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/lalala/ec.tasklist b/board/lalala/ec.tasklist
index d4fb416bce..29666dd959 100644
--- a/board/lalala/ec.tasklist
+++ b/board/lalala/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/lalala/gpio.inc b/board/lalala/gpio.inc
index 3d81cd089d..8d37079ca4 100644
--- a/board/lalala/gpio.inc
+++ b/board/lalala/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/lalala/led.c b/board/lalala/led.c
index cfe6f9eb6a..db36e2cb0b 100644
--- a/board/lalala/led.c
+++ b/board/lalala/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,23 +19,28 @@ __override const int led_charge_lvl_1 = 5;
 __override const int led_charge_lvl_2 = 95;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
diff --git a/board/lalala/usb_pd_policy.c b/board/lalala/usb_pd_policy.c
index fd9018a3f0..3410726e87 100644
--- a/board/lalala/usb_pd_policy.c
+++ b/board/lalala/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,8 +10,8 @@
 #include "driver/tcpm/tcpci.h"
 #include "usb_pd.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
diff --git a/board/lantis/battery.c b/board/lantis/battery.c
index 9f9deddb2b..6dfb91ef50 100644
--- a/board/lantis/battery.c
+++ b/board/lantis/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/lantis/board.c b/board/lantis/board.c
index f8c8b2e477..08fc84e222 100644
--- a/board/lantis/board.c
+++ b/board/lantis/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -46,7 +46,7 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
 
 #define INT_RECHECK_US 5000
 
@@ -183,48 +183,36 @@ static void pen_detect_interrupt(enum gpio_signal s)
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH0
-	},
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH2
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH3
-	},
-	[ADC_SUB_ANALOG] = {
-		.name = "SUB_ANALOG",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH13
-	},
-	[ADC_TEMP_SENSOR_3] = {
-		.name = "TEMP_SENSOR3",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH15
-	},
-	[ADC_TEMP_SENSOR_4] = {
-		.name = "TEMP_SENSOR4",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH16
-	},
+	[ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH0 },
+	[ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH2 },
+	[ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH3 },
+	[ADC_SUB_ANALOG] = { .name = "SUB_ANALOG",
+			     .factor_mul = ADC_MAX_MVOLT,
+			     .factor_div = ADC_READ_MAX + 1,
+			     .shift = 0,
+			     .channel = CHIP_ADC_CH13 },
+	[ADC_TEMP_SENSOR_3] = { .name = "TEMP_SENSOR3",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH15 },
+	[ADC_TEMP_SENSOR_4] = { .name = "TEMP_SENSOR4",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH16 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
@@ -273,19 +261,25 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 };
 
 /* USB Muxes */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+			},
 	},
 	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_SUB_USB_C1,
+				.i2c_addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	},
 };
 
@@ -299,17 +293,13 @@ static struct accelgyro_saved_data_t g_bma422_data;
 static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
 
 /* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+					      { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
 
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
 
 /* Drivers */
 struct motion_sensor_t motion_sensors[] = {
@@ -497,8 +487,8 @@ static const struct ec_response_keybd_config landrid_keybd = {
 	/* No function keys and no screenlock key */
 };
 
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	if (get_cbi_fw_config_numeric_pad()) {
 		if (get_cbi_fw_config_kblight())
@@ -513,8 +503,7 @@ __override const struct ec_response_keybd_config
 	}
 }
 
-__override
-uint8_t board_keyboard_row_refresh(void)
+__override uint8_t board_keyboard_row_refresh(void)
 {
 	if (gpio_get_level(GPIO_EC_VIVALDIKEYBOARD_ID))
 		return 3;
@@ -674,8 +663,8 @@ __override void board_power_5v_enable(int enable)
 
 	if (board_get_charger_chip_count() > 1) {
 		if (sm5803_set_gpio0_level(1, !!enable))
-			CPRINTUSB("Failed to %sable sub rails!", enable ?
-								  "en" : "dis");
+			CPRINTUSB("Failed to %sable sub rails!",
+				  enable ? "en" : "dis");
 	}
 }
 
@@ -683,11 +672,11 @@ __override uint8_t board_get_usb_pd_port_count(void)
 {
 	enum fw_config_db db = get_cbi_fw_config_db();
 
-	if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI
-			|| db == DB_1A_HDMI_LTE)
+	if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI ||
+	    db == DB_1A_HDMI_LTE)
 		return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
-	else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A
-			|| db == DB_1C_1A_LTE)
+	else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A ||
+		 db == DB_1C_1A_LTE)
 		return CONFIG_USB_PD_PORT_MAX_COUNT;
 
 	ccprints("Unhandled DB configuration: %d", db);
@@ -698,11 +687,11 @@ __override uint8_t board_get_charger_chip_count(void)
 {
 	enum fw_config_db db = get_cbi_fw_config_db();
 
-	if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI
-			|| db == DB_1A_HDMI_LTE)
+	if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI ||
+	    db == DB_1A_HDMI_LTE)
 		return CHARGER_NUM - 1;
-	else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A
-			|| db == DB_1C_1A_LTE)
+	else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A ||
+		 db == DB_1C_1A_LTE)
 		return CHARGER_NUM;
 
 	ccprints("Unhandled DB configuration: %d", db);
@@ -804,33 +793,31 @@ __override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
 }
 
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq_hz = 10000,
-	}
-};
+const struct pwm_t pwm_channels[] = { [PWM_CH_KBLIGHT] = {
+					      .channel = 0,
+					      .flags = PWM_CONFIG_DSLEEP,
+					      .freq_hz = 100,
+				      } };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
 /* Thermistors */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "Charger",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_3},
-	[TEMP_SENSOR_4] = {.name = "5V regular",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_4},
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "Charger",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
+	[TEMP_SENSOR_4] = { .name = "5V regular",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_4 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -860,9 +847,8 @@ __override void lid_angle_peripheral_enable(int enable)
 	}
 }
 
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
+__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+				       int *ki_div, int *kd, int *kd_div)
 {
 	*kp = 3;
 	*kp_div = 20;
@@ -881,14 +867,17 @@ __override void ocpc_get_pid_constants(int *kp, int *kp_div,
  * The connector has 24 pins total, and there is no pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-	{-1, -1}, {GPIO_KSO_H, 4}, {GPIO_KSO_H, 0}, {GPIO_KSO_H, 1},
-	{GPIO_KSO_H, 3}, {GPIO_KSO_H, 2}, {GPIO_KSO_L, 5}, {GPIO_KSO_L, 6},
-	{GPIO_KSO_L, 3}, {GPIO_KSO_L, 2}, {GPIO_KSI, 0}, {GPIO_KSO_L, 1},
-	{GPIO_KSO_L, 4}, {GPIO_KSI, 3}, {GPIO_KSI, 2}, {GPIO_KSO_L, 0},
-	{GPIO_KSI, 5}, {GPIO_KSI, 4}, {GPIO_KSO_L, 7}, {GPIO_KSI, 6},
-	{GPIO_KSI, 7}, {GPIO_KSI, 1}, {-1, -1}, {-1, -1}, {-1, -1},
+	{ -1, -1 },	   { GPIO_KSO_H, 4 }, { GPIO_KSO_H, 0 },
+	{ GPIO_KSO_H, 1 }, { GPIO_KSO_H, 3 }, { GPIO_KSO_H, 2 },
+	{ GPIO_KSO_L, 5 }, { GPIO_KSO_L, 6 }, { GPIO_KSO_L, 3 },
+	{ GPIO_KSO_L, 2 }, { GPIO_KSI, 0 },   { GPIO_KSO_L, 1 },
+	{ GPIO_KSO_L, 4 }, { GPIO_KSI, 3 },   { GPIO_KSI, 2 },
+	{ GPIO_KSO_L, 0 }, { GPIO_KSI, 5 },   { GPIO_KSI, 4 },
+	{ GPIO_KSO_L, 7 }, { GPIO_KSI, 6 },   { GPIO_KSI, 7 },
+	{ GPIO_KSI, 1 },   { -1, -1 },	      { -1, -1 },
+	{ -1, -1 },
 };
 
 const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 #endif
diff --git a/board/lantis/board.h b/board/lantis/board.h
index 067ff7eb94..bda4b01280 100644
--- a/board/lantis/board.h
+++ b/board/lantis/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,21 +23,24 @@
 
 /* Charger */
 #define CONFIG_CHARGE_RAMP_HW
-#define CONFIG_CHARGER_SM5803		/* C0 and C1: Charger */
+#define CONFIG_CHARGER_SM5803 /* C0 and C1: Charger */
+#define PD_MAX_VOLTAGE_MV 15000
 #define CONFIG_USB_PD_VBUS_DETECT_CHARGER
 #define CONFIG_USB_PD_5V_CHARGER_CTRL
 #define CONFIG_CHARGER_OTG
-#undef  CONFIG_CHARGER_SINGLE_CHIP
+#undef CONFIG_CHARGER_SINGLE_CHIP
 #define CONFIG_OCPC
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr */
+#define CONFIG_OCPC_DEF_RBATT_MOHMS               \
+	21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr \
+	    */
 
 /* PWM */
 #define CONFIG_PWM
 
 /* Sensors */
-#define CONFIG_ACCEL_BMA255		/* Lid accel */
-#define CONFIG_ACCEL_BMA4XX		/* 2nd source Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM	/* Base accel */
+#define CONFIG_ACCEL_BMA255 /* Lid accel */
+#define CONFIG_ACCEL_BMA4XX /* 2nd source Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
 /* Sensors without hardware FIFO are in forced mode */
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
 
@@ -68,8 +71,8 @@
 
 /* TCPC */
 #define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP	/* C0: ITE EC TCPC */
-#define CONFIG_USB_PD_TCPM_PS8705	/* C1: PS8705 TCPC*/
+#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0: ITE EC TCPC */
+#define CONFIG_USB_PD_TCPM_PS8705 /* C1: PS8705 TCPC*/
 #define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1
 #define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
 #define CONFIG_USB_PD_TCPC_LOW_POWER
@@ -80,8 +83,8 @@
 #define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
 
 /* USB Mux and Retimer */
-#define CONFIG_USB_MUX_IT5205			/* C1: ITE Mux */
-#define I2C_PORT_USB_MUX I2C_PORT_USB_C0	/* Required for ITE Mux */
+#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */
 
 /* USB Type A Features */
 #define USB_PORT_COUNT 1
@@ -104,21 +107,16 @@ enum pwm_channel {
 };
 
 /* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
 /* ADC channels */
 enum adc_channel {
-	ADC_VSNS_PP3300_A,     /* ADC0 */
-	ADC_TEMP_SENSOR_1,     /* ADC2 */
-	ADC_TEMP_SENSOR_2,     /* ADC3 */
-	ADC_SUB_ANALOG,        /* ADC13 */
-	ADC_TEMP_SENSOR_3,     /* ADC15 */
-	ADC_TEMP_SENSOR_4,     /* ADC16 */
+	ADC_VSNS_PP3300_A, /* ADC0 */
+	ADC_TEMP_SENSOR_1, /* ADC2 */
+	ADC_TEMP_SENSOR_2, /* ADC3 */
+	ADC_SUB_ANALOG, /* ADC13 */
+	ADC_TEMP_SENSOR_3, /* ADC15 */
+	ADC_TEMP_SENSOR_4, /* ADC16 */
 	ADC_CH_COUNT
 };
 
@@ -143,10 +141,7 @@ enum battery_type {
 	BATTERY_TYPE_COUNT,
 };
 
-enum ec_cfg_keyboard_layout {
-	KB_LAYOUT_DEFAULT = 0,
-	KB_LAYOUT_1 = 1
-};
+enum ec_cfg_keyboard_layout { KB_LAYOUT_DEFAULT = 0, KB_LAYOUT_1 = 1 };
 
 #endif /* !__ASSEMBLER__ */
 
diff --git a/board/lantis/build.mk b/board/lantis/build.mk
index 806168ea0d..9b862c7624 100644
--- a/board/lantis/build.mk
+++ b/board/lantis/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/lantis/cbi_ssfc.c b/board/lantis/cbi_ssfc.c
index c4b859f133..81f3ee0dad 100644
--- a/board/lantis/cbi_ssfc.c
+++ b/board/lantis/cbi_ssfc.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
 
 enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
 {
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
 }
 
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
 {
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
 }
diff --git a/board/lantis/cbi_ssfc.h b/board/lantis/cbi_ssfc.h
index 448fa5a163..e6606e8b1b 100644
--- a/board/lantis/cbi_ssfc.h
+++ b/board/lantis/cbi_ssfc.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -36,18 +36,18 @@ enum ec_ssfc_lid_sensor {
  * Audio Codec Source(Bit 8-10)
  */
 enum ec_ssfc_audio_codec_source {
-        SSFC_AUDIO_CODEC_DEFAULT = 0,
-        SSFC_AUDIO_CODEC_VD = 1,
-        SSFC_ADUIO_CODEC_VS = 2,
+	SSFC_AUDIO_CODEC_DEFAULT = 0,
+	SSFC_AUDIO_CODEC_VD = 1,
+	SSFC_ADUIO_CODEC_VS = 2,
 };
 
 /*
  * Touchscreen Driver Source(Bit 11-13)
  */
 enum ec_ssfc_ts_driver_source {
-        SSFC_TS_DRIVER_DEFAULT = 0,
-        SSFC_TS_DRIVER_GENERIC = 1,
-        SSFC_TS_DRIVER_HID = 2,
+	SSFC_TS_DRIVER_DEFAULT = 0,
+	SSFC_TS_DRIVER_GENERIC = 1,
+	SSFC_TS_DRIVER_HID = 2,
 };
 
 union dedede_cbi_ssfc {
@@ -56,7 +56,7 @@ union dedede_cbi_ssfc {
 		uint32_t lid_sensor : 3;
 		uint32_t reserved : 2;
 		uint32_t audio_codec_source : 3;
-		uint32_t ts_driver_source: 3;
+		uint32_t ts_driver_source : 3;
 		uint32_t reserved_2 : 18;
 	};
 	uint32_t raw_value;
@@ -76,5 +76,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
  */
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
 
-
 #endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/lantis/ec.tasklist b/board/lantis/ec.tasklist
index 2edf48ee05..c3c360febb 100644
--- a/board/lantis/ec.tasklist
+++ b/board/lantis/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/lantis/gpio.inc b/board/lantis/gpio.inc
index 2be82d2358..6afb9ccc4b 100644
--- a/board/lantis/gpio.inc
+++ b/board/lantis/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/lantis/led.c b/board/lantis/led.c
index 632f91e118..d6dbc929a8 100644
--- a/board/lantis/led.c
+++ b/board/lantis/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,11 +19,9 @@
 #define POWER_LED_ON 0
 #define POWER_LED_OFF 1
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_LEFT_LED,
-	EC_LED_ID_RIGHT_LED,
-	EC_LED_ID_POWER_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_LEFT_LED,
+					     EC_LED_ID_RIGHT_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -31,22 +29,19 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
-enum led_port {
-	LEFT_PORT = 0,
-	RIGHT_PORT
-};
+enum led_port { LEFT_PORT = 0, RIGHT_PORT };
 
 static int led_set_color_battery(int port, enum led_color color)
 {
 	enum gpio_signal amber_led, white_led;
 
 	amber_led = (port == RIGHT_PORT ? GPIO_BAT_LED_AMBER_C1 :
-				 GPIO_BAT_LED_AMBER_C0);
+					  GPIO_BAT_LED_AMBER_C0);
 	white_led = (port == RIGHT_PORT ? GPIO_BAT_LED_WHITE_C1 :
-				 GPIO_BAT_LED_WHITE_C0);
+					  GPIO_BAT_LED_WHITE_C0);
 
 	switch (color) {
 	case LED_OFF:
@@ -144,7 +139,7 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 static bool is_led_old_policy(void)
 {
 	if (get_cbi_fw_config_numeric_pad() == NUMERIC_PAD_ABSENT &&
-		get_cbi_fw_config_tablet_mode() == TABLET_MODE_ABSENT)
+	    get_cbi_fw_config_tablet_mode() == TABLET_MODE_ABSENT)
 		return 1;
 	else
 		return 0;
@@ -160,17 +155,16 @@ static void set_active_port_color(enum led_color color)
 
 	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
 		led_set_color_battery(RIGHT_PORT,
-				(port == RIGHT_PORT) ? color : LED_OFF);
+				      (port == RIGHT_PORT) ? color : LED_OFF);
 	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
 		led_set_color_battery(LEFT_PORT,
-				(port == LEFT_PORT) ? color : LED_OFF);
+				      (port == LEFT_PORT) ? color : LED_OFF);
 }
 
 static void led_set_battery(void)
 {
 	static int battery_ticks;
 	static int power_ticks;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
@@ -181,14 +175,15 @@ static void led_set_battery(void)
 	 */
 	if (get_cbi_fw_config_tablet_mode() == TABLET_MODE_ABSENT) {
 		if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
-			charge_get_state() != PWR_STATE_CHARGE) {
-
+		    charge_get_state() != PWR_STATE_CHARGE) {
 			power_ticks++;
 
 			led_set_color_battery(RIGHT_PORT, power_ticks & 0x2 ?
-						  LED_WHITE : LED_OFF);
+								  LED_WHITE :
+								  LED_OFF);
 			led_set_color_battery(LEFT_PORT, power_ticks & 0x2 ?
-						  LED_WHITE : LED_OFF);
+								 LED_WHITE :
+								 LED_OFF);
 			return;
 		}
 	}
@@ -212,22 +207,25 @@ static void led_set_battery(void)
 		 */
 		if (charge_get_percent() < 10) {
 			if (is_led_old_policy()) {
-				led_set_color_battery(
-					RIGHT_PORT, (battery_ticks & 0x2) ?
-					LED_WHITE : LED_OFF);
+				led_set_color_battery(RIGHT_PORT,
+						      (battery_ticks & 0x2) ?
+							      LED_WHITE :
+							      LED_OFF);
 			} else {
 				if (led_auto_control_is_enabled(
-					EC_LED_ID_RIGHT_LED))
+					    EC_LED_ID_RIGHT_LED))
 					led_set_color_battery(
 						RIGHT_PORT,
 						(battery_ticks & 0x2) ?
-						LED_AMBER : LED_OFF);
+							LED_AMBER :
+							LED_OFF);
 				if (led_auto_control_is_enabled(
-					EC_LED_ID_LEFT_LED))
+					    EC_LED_ID_LEFT_LED))
 					led_set_color_battery(
 						LEFT_PORT,
 						(battery_ticks & 0x2) ?
-						LED_AMBER : LED_OFF);
+							LED_AMBER :
+							LED_OFF);
 			}
 		} else {
 			set_active_port_color(LED_OFF);
@@ -245,11 +243,11 @@ static void led_set_battery(void)
 		set_active_port_color(LED_WHITE);
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			set_active_port_color(
-				(battery_ticks & 0x2) ? LED_AMBER : LED_OFF);
-		else
-			set_active_port_color(LED_WHITE);
+		set_active_port_color(LED_WHITE);
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		set_active_port_color((battery_ticks & 0x2) ? LED_AMBER :
+							      LED_OFF);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
@@ -266,8 +264,7 @@ static void led_set_power(void)
 	if (chipset_in_state(CHIPSET_STATE_ON))
 		led_set_color_power(LED_WHITE);
 	else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-		led_set_color_power(
-			(power_tick & 0x2) ? LED_WHITE : LED_OFF);
+		led_set_color_power((power_tick & 0x2) ? LED_WHITE : LED_OFF);
 	else
 		led_set_color_power(LED_OFF);
 }
diff --git a/board/lantis/usb_pd_policy.c b/board/lantis/usb_pd_policy.c
index 7046e25d6c..2433b25431 100644
--- a/board/lantis/usb_pd_policy.c
+++ b/board/lantis/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,8 +13,8 @@
 #include "driver/tcpm/tcpci.h"
 #include "usb_pd.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
@@ -65,18 +65,7 @@ int pd_set_power_supply_ready(int port)
 
 __override bool pd_check_vbus_level(int port, enum vbus_level level)
 {
-	int vbus_voltage;
-
-	/* If we're unable to speak to the charger, best to guess false */
-	if (charger_get_vbus_voltage(port, &vbus_voltage))
-		return false;
-
-	if (level == VBUS_SAFE0V)
-		return vbus_voltage < PD_V_SAFE0V_MAX;
-	else if (level == VBUS_PRESENT)
-		return vbus_voltage > PD_V_SAFE5V_MIN;
-	else
-		return vbus_voltage < PD_V_SINK_DISCONNECT_MAX;
+	return sm5803_check_vbus_level(port, level);
 }
 
 int pd_snk_is_vbus_provided(int port)
diff --git a/board/lazor/battery.c b/board/lazor/battery.c
index 6cad716e2c..61de35da12 100644
--- a/board/lazor/battery.c
+++ b/board/lazor/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/lazor/board.c b/board/lazor/board.c
index e25b83d7db..974f09e55f 100644
--- a/board/lazor/board.c
+++ b/board/lazor/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -33,8 +33,9 @@
 #include "usbc_config.h"
 #include "usbc_ppc.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+/* Disable debug messages to free flash space */
+#define CPRINTS(format, args...)
+#define CPRINTF(format, args...)
 
 #include "gpio_list.h"
 
@@ -46,10 +47,8 @@ __override struct keyboard_scan_config keyscan_config = {
 	 * Unmask 0x08 in [0] (KSO_00/KSI_03, the new location of Search key);
 	 * as it still uses the legacy location (KSO_01/KSI_00).
 	 */
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca
-	},
+	.actual_key_mask = { 0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, 0xa4,
+			     0xff, 0xfe, 0x55, 0xfa, 0xca },
 	/* Other values should be the same as the default configuration. */
 	.debounce_down_us = 9 * MSEC,
 	.debounce_up_us = 30 * MSEC,
@@ -64,55 +63,44 @@ __override struct keyboard_scan_config keyscan_config = {
  * that we don't have pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-	{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-	{0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3},
-	{-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0},
-	{1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4},
-	{2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0},
-	{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1},
-	{-1, -1},
+	{ -1, -1 }, { 0, 5 },	{ 1, 1 },   { 1, 0 },	{ 0, 6 },   { 0, 7 },
+	{ -1, -1 }, { -1, -1 }, { 1, 4 },   { 1, 3 },	{ -1, -1 }, { 1, 6 },
+	{ 1, 7 },   { 3, 1 },	{ 2, 0 },   { 1, 5 },	{ 2, 6 },   { 2, 7 },
+	{ 2, 1 },   { 2, 4 },	{ 2, 5 },   { 1, 2 },	{ 2, 3 },   { 2, 2 },
+	{ 3, 0 },   { -1, -1 }, { -1, -1 }, { -1, -1 }, { -1, -1 }, { -1, -1 },
+	{ -1, -1 },
 };
 
 const int keyboard_factory_scan_pins_used =
-		ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 
 /* I2C port map */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl  = GPIO_EC_I2C_POWER_SCL,
-		.sda  = GPIO_EC_I2C_POWER_SDA
-	},
-	{
-		.name = "tcpc0",
-		.port = I2C_PORT_TCPC0,
-		.kbps = 1000,
-		.scl  = GPIO_EC_I2C_USB_C0_PD_SCL,
-		.sda  = GPIO_EC_I2C_USB_C0_PD_SDA
-	},
-	{
-		.name = "tcpc1",
-		.port = I2C_PORT_TCPC1,
-		.kbps = 1000,
-		.scl  = GPIO_EC_I2C_USB_C1_PD_SCL,
-		.sda  = GPIO_EC_I2C_USB_C1_PD_SDA
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_EEPROM_SCL,
-		.sda  = GPIO_EC_I2C_EEPROM_SDA
-	},
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_SENSOR_SCL,
-		.sda  = GPIO_EC_I2C_SENSOR_SDA
-	},
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_POWER_SCL,
+	  .sda = GPIO_EC_I2C_POWER_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C0_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C0_PD_SDA },
+	{ .name = "tcpc1",
+	  .port = I2C_PORT_TCPC1,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C1_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C1_PD_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_EEPROM_SCL,
+	  .sda = GPIO_EC_I2C_EEPROM_SDA },
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_SENSOR_SCL,
+	  .sda = GPIO_EC_I2C_SENSOR_SDA },
 };
 
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
@@ -120,37 +108,22 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* Measure VBUS through a 1/10 voltage divider */
-	[ADC_VBUS] = {
-		"VBUS",
-		NPCX_ADC_CH1,
-		ADC_MAX_VOLT * 10,
-		ADC_READ_MAX + 1,
-		0
-	},
+	[ADC_VBUS] = { "VBUS", NPCX_ADC_CH1, ADC_MAX_VOLT * 10,
+		       ADC_READ_MAX + 1, 0 },
 	/*
 	 * Adapter current output or battery charging/discharging current (uV)
 	 * 18x amplification on charger side.
 	 */
-	[ADC_AMON_BMON] = {
-		"AMON_BMON",
-		NPCX_ADC_CH2,
-		ADC_MAX_VOLT * 1000 / 18,
-		ADC_READ_MAX + 1,
-		0
-	},
+	[ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH2, ADC_MAX_VOLT * 1000 / 18,
+			    ADC_READ_MAX + 1, 0 },
 	/*
 	 * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read
 	 * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and
 	 * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we
 	 * only divide by 2 (enough to avoid precision issues).
 	 */
-	[ADC_PSYS] = {
-		"PSYS",
-		NPCX_ADC_CH3,
-		ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1),
-		2,
-		0
-	},
+	[ADC_PSYS] = { "PSYS", NPCX_ADC_CH3,
+		       ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), 2, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
@@ -177,29 +150,21 @@ enum base_accelgyro_type {
 };
 
 /* Matrix to rotate accelerometer into standard reference frame */
-const mat33_fp_t base_standard_ref_bmi160 = {
-	{ FLOAT_TO_FP(1), 0,  0},
-	{ 0,  FLOAT_TO_FP(-1),  0},
-	{ 0,  0, FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t base_standard_ref_bmi160 = { { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, FLOAT_TO_FP(-1), 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
 
-const mat33_fp_t base_standard_ref_icm426xx = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0,  0, FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t base_standard_ref_icm426xx = { { 0, FLOAT_TO_FP(1), 0 },
+						{ FLOAT_TO_FP(1), 0, 0 },
+						{ 0, 0, FLOAT_TO_FP(-1) } };
 
-static const mat33_fp_t lid_standard_ref_bma255 = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lid_standard_ref_bma255 = { { FLOAT_TO_FP(-1), 0, 0 },
+						    { 0, FLOAT_TO_FP(-1), 0 },
+						    { 0, 0, FLOAT_TO_FP(1) } };
 
-static const mat33_fp_t lid_standard_ref_kx022 = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lid_standard_ref_kx022 = { { FLOAT_TO_FP(-1), 0, 0 },
+						   { 0, FLOAT_TO_FP(-1), 0 },
+						   { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
@@ -371,7 +336,7 @@ static void board_detect_motionsensor(void)
 
 	/* Check lid accel chip */
 	ret = i2c_read8(I2C_PORT_SENSOR, BMA2x2_I2C_ADDR1_FLAGS,
-		BMA2x2_CHIP_ID_ADDR, &val);
+			BMA2x2_CHIP_ID_ADDR, &val);
 	if (ret)
 		motion_sensors[LID_ACCEL] = kx022_lid_accel;
 
@@ -384,10 +349,11 @@ static void board_detect_motionsensor(void)
 		motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
 	}
 
-	base_accelgyro_config = (val == ICM426XX_CHIP_ICM40608)
-		 ? BASE_GYRO_ICM426XX : BASE_GYRO_BMI160;
-	CPRINTS("Base Accelgyro: %s", (val == ICM426XX_CHIP_ICM40608)
-		 ? "ICM40608" : "BMI160");
+	base_accelgyro_config = (val == ICM426XX_CHIP_ICM40608) ?
+					BASE_GYRO_ICM426XX :
+					BASE_GYRO_BMI160;
+	CPRINTS("Base Accelgyro: %s",
+		(val == ICM426XX_CHIP_ICM40608) ? "ICM40608" : "BMI160");
 }
 
 static void board_update_sensor_config_from_sku(void)
diff --git a/board/lazor/board.h b/board/lazor/board.h
index f4f722c6a2..427db5e82e 100644
--- a/board/lazor/board.h
+++ b/board/lazor/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,9 +11,10 @@
 #include "baseboard.h"
 
 /* Internal SPI flash on NPCX7 */
-#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)  /* 512KB internal spi flash */
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */
 
 /* Reduce flash usage */
+#define CONFIG_LTO
 #define CONFIG_USB_PD_DEBUG_LEVEL 2
 
 /* Switchcap */
@@ -25,7 +26,7 @@
 #define CONFIG_PWM_KBLIGHT
 
 /* Battery */
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY  "LION"
+#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
 #define CONFIG_BATTERY_REVIVE_DISCONNECT
 #define CONFIG_BATTERY_FUEL_GAUGE
 
@@ -91,12 +92,7 @@
 #include "registers.h"
 #include "sku.h"
 
-enum adc_channel {
-	ADC_VBUS,
-	ADC_AMON_BMON,
-	ADC_PSYS,
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_VBUS, ADC_AMON_BMON, ADC_PSYS, ADC_CH_COUNT };
 
 /* Motion sensors */
 enum sensor_id {
@@ -106,11 +102,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_DISPLIGHT,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_DISPLIGHT, PWM_CH_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
diff --git a/board/lazor/build.mk b/board/lazor/build.mk
index 8cf8679e35..c17ab5e40c 100644
--- a/board/lazor/build.mk
+++ b/board/lazor/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/lazor/ec.tasklist b/board/lazor/ec.tasklist
index 2b55c26c20..92d5a1dde1 100644
--- a/board/lazor/ec.tasklist
+++ b/board/lazor/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/lazor/gpio.inc b/board/lazor/gpio.inc
index b5c15b3729..c7af05eb3b 100644
--- a/board/lazor/gpio.inc
+++ b/board/lazor/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/lazor/hibernate.c b/board/lazor/hibernate.c
index d262a33121..67d9b30791 100644
--- a/board/lazor/hibernate.c
+++ b/board/lazor/hibernate.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/lazor/led.c b/board/lazor/led.c
index f9c91c1c6a..cf1f68d77e 100644
--- a/board/lazor/led.c
+++ b/board/lazor/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -32,15 +32,15 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_BLUE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static void led_set_color(enum led_color color)
 {
 	gpio_set_level(GPIO_EC_CHG_LED_Y_C1,
-		(color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
+		       (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
 	gpio_set_level(GPIO_EC_CHG_LED_B_C1,
-		(color == LED_BLUE) ? BAT_LED_ON : BAT_LED_OFF);
+		       (color == LED_BLUE) ? BAT_LED_ON : BAT_LED_OFF);
 }
 
 void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
@@ -66,7 +66,6 @@ static void board_led_set_battery(void)
 	static int battery_ticks;
 	int color = LED_OFF;
 	int period = 0;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
@@ -106,16 +105,16 @@ static void board_led_set_battery(void)
 		color = LED_BLUE;
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE) {
-			/* Factory mode: Blue 2 sec, Amber 2 sec */
-			period = (2 + 2) * LED_ONE_SEC;
-			battery_ticks = battery_ticks % period;
-			if (battery_ticks < 2 * LED_ONE_SEC)
-				color = LED_BLUE;
-			else
-				color = LED_AMBER;
-		} else
+		color = LED_BLUE;
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		/* Factory mode: Blue 2 sec, Amber 2 sec */
+		period = (2 + 2) * LED_ONE_SEC;
+		battery_ticks = battery_ticks % period;
+		if (battery_ticks < 2 * LED_ONE_SEC)
 			color = LED_BLUE;
+		else
+			color = LED_AMBER;
 		break;
 	default:
 		/* Other states don't alter LED behavior */
diff --git a/board/lazor/sku.c b/board/lazor/sku.c
index 1f63d05bf6..625231f5a9 100644
--- a/board/lazor/sku.c
+++ b/board/lazor/sku.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,8 +14,8 @@
 #include "system.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static uint8_t sku_id;
 
diff --git a/board/lazor/sku.h b/board/lazor/sku.h
index 85f549858a..3ba687939d 100644
--- a/board/lazor/sku.h
+++ b/board/lazor/sku.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/lazor/switchcap.c b/board/lazor/switchcap.c
index 16f4a54c79..f18378cab7 100644
--- a/board/lazor/switchcap.c
+++ b/board/lazor/switchcap.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,8 +14,8 @@
 #include "system.h"
 #include "sku.h"
 
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args)
 
 /* LN9310 switchcap */
 const struct ln9310_config_t ln9310_config = {
diff --git a/board/lazor/usbc_config.c b/board/lazor/usbc_config.c
index 59951223ec..11cc649573 100644
--- a/board/lazor/usbc_config.c
+++ b/board/lazor/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,8 +27,9 @@
 #include "usbc_ocp.h"
 #include "usbc_ppc.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+/* Disable debug messages to free flash space */
+#define CPRINTS(format, args...)
+#define CPRINTF(format, args...)
 
 const struct charger_config_t chg_chips[] = {
 	{
@@ -149,16 +150,12 @@ void tcpc_alert_event(enum gpio_signal signal)
 
 /* Power Path Controller */
 struct ppc_config_t ppc_chips[] = {
-	{
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	{
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
+	{ .i2c_port = I2C_PORT_TCPC0,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
+	{ .i2c_port = I2C_PORT_TCPC1,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
 };
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
@@ -189,16 +186,22 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
  * to AP. But the TCPC chip is also needed to know the HPD status; otherwise,
  * the mux misbehaves.
  */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	},
 	{
-		.usb_port = 1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	}
 };
 
@@ -271,7 +274,7 @@ void board_tcpc_init(void)
 	 */
 	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
 		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
 DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
 
@@ -316,8 +319,7 @@ void board_overcurrent_event(int port, int is_overcurrented)
 
 int board_set_active_charge_port(int port)
 {
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	int i;
 
 	if (!is_real_port && port != CHARGE_PORT_NONE)
@@ -345,7 +347,6 @@ int board_set_active_charge_port(int port)
 		return EC_ERROR_INVAL;
 	}
 
-
 	CPRINTS("New charge port: p%d", port);
 
 	/*
@@ -369,23 +370,21 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	/*
 	 * Ignore lower charge ceiling on PD transition if our battery is
 	 * critical, as we may brownout.
 	 */
-	if (supplier == CHARGE_SUPPLIER_PD &&
-	    charge_ma < 1500 &&
+	if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 &&
 	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
 		CPRINTS("Using max ilim %d", max_ma);
 		charge_ma = max_ma;
 	}
 
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 uint16_t tcpc_get_alert_status(void)
diff --git a/board/lazor/usbc_config.h b/board/lazor/usbc_config.h
index 9c1d8d1e74..53d6df3983 100644
--- a/board/lazor/usbc_config.h
+++ b/board/lazor/usbc_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/liara/battery.c b/board/liara/battery.c
index bf244125b0..291925cd06 100644
--- a/board/liara/battery.c
+++ b/board/liara/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/liara/board.c b/board/liara/board.c
index c8fdeff2cd..f51fa1e2dd 100644
--- a/board/liara/board.c
+++ b/board/liara/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,52 +25,40 @@ const enum gpio_signal hibernate_wake_pins[] = {
 	GPIO_POWER_BUTTON_L,
 	GPIO_EC_RST_ODL,
 };
-const int hibernate_wake_pins_used =  ARRAY_SIZE(hibernate_wake_pins);
+const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 
 /* I2C port map. */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl  = GPIO_I2C0_SCL,
-		.sda  = GPIO_I2C0_SDA
-	},
-	{
-		.name = "tcpc0",
-		.port = I2C_PORT_TCPC0,
-		.kbps = 400,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	},
-	{
-		.name = "tcpc1",
-		.port = I2C_PORT_TCPC1,
-		.kbps = 400,
-		.scl  = GPIO_I2C2_SCL,
-		.sda  = GPIO_I2C2_SDA
-	},
-	{
-		.name = "thermal",
-		.port = I2C_PORT_THERMAL_AP,
-		.kbps = 400,
-		.scl  = GPIO_I2C3_SCL,
-		.sda  = GPIO_I2C3_SDA
-	},
-	{
-		.name = "kblight",
-		.port = I2C_PORT_KBLIGHT,
-		.kbps = 100,
-		.scl  = GPIO_I2C5_SCL,
-		.sda  = GPIO_I2C5_SDA
-	},
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl  = GPIO_I2C7_SCL,
-		.sda  = GPIO_I2C7_SDA
-	},
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_I2C0_SCL,
+	  .sda = GPIO_I2C0_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "tcpc1",
+	  .port = I2C_PORT_TCPC1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "thermal",
+	  .port = I2C_PORT_THERMAL_AP,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
+	{ .name = "kblight",
+	  .port = I2C_PORT_KBLIGHT,
+	  .kbps = 100,
+	  .scl = GPIO_I2C5_SCL,
+	  .sda = GPIO_I2C5_SDA },
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_I2C7_SCL,
+	  .sda = GPIO_I2C7_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
diff --git a/board/liara/board.h b/board/liara/board.h
index ae4494115b..4ef9a11793 100644
--- a/board/liara/board.h
+++ b/board/liara/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,13 +17,13 @@
  * By default, enable all console messages excepted HC, ACPI and event:
  * The sensor stack is generating a lot of activity.
  */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
 #undef CONFIG_HOSTCMD_DEBUG_MODE
 #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
 
 #define CONFIG_MKBP_USE_HOST_EVENT
 
-#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV	5000
+#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV 5000
 
 /* Power and battery LEDs */
 #define CONFIG_LED_COMMON
diff --git a/board/liara/build.mk b/board/liara/build.mk
index c808e65aed..d24127ddae 100644
--- a/board/liara/build.mk
+++ b/board/liara/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/liara/ec.tasklist b/board/liara/ec.tasklist
index b562761311..24300fe7da 100644
--- a/board/liara/ec.tasklist
+++ b/board/liara/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/liara/gpio.inc b/board/liara/gpio.inc
index 343c50f503..a1c3e1a25f 100644
--- a/board/liara/gpio.inc
+++ b/board/liara/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/liara/led.c b/board/liara/led.c
index 371c08ce40..45cc43edc8 100644
--- a/board/liara/led.c
+++ b/board/liara/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,13 +19,10 @@ const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
  * both LEDs being off.
  */
 struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = {
-				/* White, Amber */
-	[EC_LED_COLOR_RED]    = {   0,   0 },
-	[EC_LED_COLOR_GREEN]  = {   0,   0 },
-	[EC_LED_COLOR_BLUE]   = {   0,   0 },
-	[EC_LED_COLOR_YELLOW] = {   0,   0 },
-	[EC_LED_COLOR_WHITE]  = { 100,   0 },
-	[EC_LED_COLOR_AMBER]  = {   0, 100 },
+	/* White, Amber */
+	[EC_LED_COLOR_RED] = { 0, 0 },	   [EC_LED_COLOR_GREEN] = { 0, 0 },
+	[EC_LED_COLOR_BLUE] = { 0, 0 },	   [EC_LED_COLOR_YELLOW] = { 0, 0 },
+	[EC_LED_COLOR_WHITE] = { 100, 0 }, [EC_LED_COLOR_AMBER] = { 0, 100 },
 };
 
 /* One logical LED with amber and blue channels. */
diff --git a/board/lick/battery.c b/board/lick/battery.c
index fa746a8c9f..01ab23dd3b 100644
--- a/board/lick/battery.c
+++ b/board/lick/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/lick/board.c b/board/lick/board.c
index 678634f785..d20aad2968 100644
--- a/board/lick/board.c
+++ b/board/lick/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -31,11 +31,11 @@
 #include "util.h"
 #include "battery_smart.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define USB_PD_PORT_ANX7447	0
-#define USB_PD_PORT_PS8751	1
+#define USB_PD_PORT_ANX7447 0
+#define USB_PD_PORT_PS8751 1
 
 static uint8_t sku_id;
 
@@ -60,31 +60,31 @@ static void ppc_interrupt(enum gpio_signal signal)
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_AMB] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_AMB] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				  ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_CHARGER] = { "TEMP_CHARGER", NPCX_ADC_CH1,
+				      ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 },
 	/* Vbus sensing (1/10 voltage divider). */
-	[ADC_VBUS_C0] = {
-		"VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
-	[ADC_VBUS_C1] = {
-		"VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
+	[ADC_VBUS_C0] = { "VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT * 10,
+			  ADC_READ_MAX + 1, 0 },
+	[ADC_VBUS_C1] = { "VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT * 10,
+			  ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp,
-				 .idx = 0},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
+	[TEMP_SENSOR_BATTERY] = { .name = "Battery",
+				  .type = TEMP_SENSOR_TYPE_BATTERY,
+				  .read = charge_get_battery_temp,
+				  .idx = 0 },
+	[TEMP_SENSOR_AMBIENT] = { .name = "Ambient",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_51k1_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_AMB },
+	[TEMP_SENSOR_CHARGER] = { .name = "Charger",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_13k7_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_CHARGER },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -94,11 +94,9 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrix to rotate lid and base sensor into standard reference frame */
-const mat33_fp_t standard_rot_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
+const mat33_fp_t standard_rot_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				      { 0, FLOAT_TO_FP(-1), 0 },
+				      { 0, 0, FLOAT_TO_FP(1) } };
 
 /* sensor private data */
 static struct stprivate_data g_lis2dh_data;
@@ -192,11 +190,10 @@ static int board_is_convertible(void)
 
 static void board_update_sensor_config_from_sku(void)
 {
-		motion_sensor_count = 0;
-		gmr_tablet_switch_disable();
-		/* Base accel is not stuffed, don't allow line to float */
-		gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L,
-			       GPIO_INPUT | GPIO_PULL_DOWN);
+	motion_sensor_count = 0;
+	gmr_tablet_switch_disable();
+	/* Base accel is not stuffed, don't allow line to float */
+	gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
 }
 
 static void cbi_init(void)
@@ -232,11 +229,11 @@ int board_is_lid_angle_tablet_mode(void)
 }
 
 /* Battery functions */
-#define SB_OPTIONALMFG_FUNCTION2		0x3e
+#define SB_OPTIONALMFG_FUNCTION2 0x3e
 /* Optional mfg function2 */
-#define SMART_QUICK_CHARGE			(1<<12)
+#define SMART_QUICK_CHARGE (1 << 12)
 /* Quick charge support */
-#define MODE_QUICK_CHARGE_SUPPORT		(1<<4)
+#define MODE_QUICK_CHARGE_SUPPORT (1 << 4)
 
 static void sb_quick_charge_mode(int enable)
 {
diff --git a/board/lick/board.h b/board/lick/board.h
index 5c75a38c84..05f24f141d 100644
--- a/board/lick/board.h
+++ b/board/lick/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -30,8 +30,8 @@
 #define CONFIG_CMD_ACCEL_INFO
 
 /* Sensors */
-#define CONFIG_ACCEL_LIS2DE             /* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM        /* Base accel */
+#define CONFIG_ACCEL_LIS2DE /* Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
 /* Sensors without hardware FIFO are in forced mode */
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
 
@@ -50,10 +50,10 @@
 #include "registers.h"
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_AMB,		/* ADC0 */
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC1 */
-	ADC_VBUS_C0,			/* ADC9 */
-	ADC_VBUS_C1,			/* ADC4 */
+	ADC_TEMP_SENSOR_AMB, /* ADC0 */
+	ADC_TEMP_SENSOR_CHARGER, /* ADC1 */
+	ADC_VBUS_C0, /* ADC9 */
+	ADC_VBUS_C1, /* ADC4 */
 	ADC_CH_COUNT,
 };
 
@@ -64,18 +64,10 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_COUNT };
 
 /* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
diff --git a/board/lick/build.mk b/board/lick/build.mk
index 137e208b53..fee77e38b5 100644
--- a/board/lick/build.mk
+++ b/board/lick/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/lick/ec.tasklist b/board/lick/ec.tasklist
index 6eac78a042..6c56976091 100644
--- a/board/lick/ec.tasklist
+++ b/board/lick/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/lick/gpio.inc b/board/lick/gpio.inc
index ad6773a211..3a553f6e91 100644
--- a/board/lick/gpio.inc
+++ b/board/lick/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/lick/led.c b/board/lick/led.c
index a7832c5e78..80972c468b 100644
--- a/board/lick/led.c
+++ b/board/lick/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,32 +19,35 @@ __override const int led_charge_lvl_1 = 5;
 __override const int led_charge_lvl_2 = 97;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
 
 __override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-					{LED_OFF,	   0.5 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 3 * LED_ONE_SEC },
+					       { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-	EC_LED_ID_BATTERY_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED,
+					     EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
diff --git a/board/lindar/battery.c b/board/lindar/battery.c
index 533db6ae0d..e206a5c6aa 100644
--- a/board/lindar/battery.c
+++ b/board/lindar/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -129,7 +129,9 @@ __override bool board_battery_is_initialized(void)
 	bool batt_initialization_state;
 	int batt_status;
 
-	batt_initialization_state = (battery_status(&batt_status) ? false :
-		!!(batt_status & STATUS_INITIALIZED));
+	batt_initialization_state =
+		(battery_status(&batt_status) ?
+			 false :
+			 !!(batt_status & STATUS_INITIALIZED));
 	return batt_initialization_state;
 }
diff --git a/board/lindar/board.c b/board/lindar/board.c
index 79ef3a4cbb..5bb155550e 100644
--- a/board/lindar/board.c
+++ b/board/lindar/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -41,8 +41,8 @@
 
 #include "gpio_list.h" /* Must come after other header files. */
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ##args)
 
 /* Keyboard scan setting */
 __override struct keyboard_scan_config keyscan_config = {
@@ -113,7 +113,7 @@ __override void lid_angle_peripheral_enable(int enable)
 {
 	if (ec_cfg_has_tabletmode()) {
 		if (chipset_in_state(CHIPSET_STATE_ANY_OFF) ||
-			tablet_get_mode())
+		    tablet_get_mode())
 			enable = 0;
 		keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE);
 	}
@@ -130,17 +130,13 @@ static struct stprivate_data g_lis2dh_data;
 static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
 
 /* Matrix to rotate lid and base sensor into standard reference frame */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					     { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, FLOAT_TO_FP(-1), 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
@@ -225,7 +221,7 @@ unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
@@ -261,8 +257,8 @@ const struct fan_t fans[FAN_CH_COUNT] = {
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CPU \
-	{ \
+#define THERMAL_CPU              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(90), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(100), \
@@ -289,8 +285,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_INDUCTOR \
-	{ \
+#define THERMAL_INDUCTOR         \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(90), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(100), \
@@ -425,8 +421,7 @@ static void ps8815_reset(void)
 	int val;
 
 	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 0);
-	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS,
-			   PS8815_PWR_H_RST_H_DELAY_MS));
+	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS));
 	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 1);
 	msleep(PS8815_FW_INIT_DELAY_MS);
 
@@ -437,16 +432,16 @@ static void ps8815_reset(void)
 
 	CPRINTS("%s: patching ps8815 registers", __func__);
 
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
+	if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) ==
+	    EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f was %02x", val);
 
-	if (i2c_write8(I2C_PORT_USB_C1,
-		       PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) == EC_SUCCESS)
+	if (i2c_write8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f,
+		       0x31) == EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f set to 0x31");
 
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
+	if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) ==
+	    EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f now %02x", val);
 }
 
@@ -454,7 +449,7 @@ void board_reset_pd_mcu(void)
 {
 	ps8815_reset();
 	usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
 
 /******************************************************************************/
@@ -530,25 +525,32 @@ BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
 
 /******************************************************************************/
 /* USBC mux configuration - Tiger Lake includes internal mux */
-static const struct usb_mux usbc1_usb3_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	.next_mux = NULL,
+static const struct usb_mux_chain usbc1_usb3_db_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
+	.next = NULL,
 };
 
-const struct usb_mux usb_muxes[] = {
+const struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = NULL,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = NULL,
 	},
 	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc1_usb3_db_retimer,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc1_usb3_db_retimer,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
diff --git a/board/lindar/board.h b/board/lindar/board.h
index bc49b8514d..7c407d05a7 100644
--- a/board/lindar/board.h
+++ b/board/lindar/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,12 +27,11 @@
 
 /* Sensors */
 #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-#define CONFIG_ACCEL_LIS2DE             /* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM        /* Base accel */
+#define CONFIG_ACCEL_LIS2DE /* Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
 
 /* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
-	BIT(LID_ACCEL)
+#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
 
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_UPDATE
@@ -43,31 +42,29 @@
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 
 /* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
-
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
 
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
 
 /*
  * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
  * cables only support up to 60W.
  */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		45000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
-
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 45000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 #undef CONFIG_USB_MUX_RUNTIME_CONFIG
 
 /* USB Type A Features */
-#define USB_PORT_COUNT			1
+#define USB_PORT_COUNT 1
 #define CONFIG_USB_PORT_POWER_DUMB
 
 /* USBC PPC*/
-#define CONFIG_USBC_PPC_SN5S330		/* USBC port C0 */
-#define CONFIG_USBC_PPC_SYV682X		/* USBC port C1 */
+#define CONFIG_USBC_PPC_SN5S330 /* USBC port C0 */
+#define CONFIG_USBC_PPC_SYV682X /* USBC port C1 */
 
 /* BC 1.2 */
 
@@ -76,8 +73,8 @@
 /* Fan features */
 
 /* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 
 /* Retimer */
 #undef CONFIG_USBC_RETIMER_INTEL_BB
@@ -92,42 +89,42 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SYS_PWROK		GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_MUTE_BTN_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_LID_OPEN GPIO_EC_LID_OPEN
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_MUTE_BTN_ODL
 
 /* I2C Bus Configuration */
 #define CONFIG_I2C
 #define CONFIG_I2C_BUS_MAY_BE_UNPOWERED
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_LIGHTBAR	NPCX_I2C_PORT3_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0
+#define I2C_PORT_LIGHTBAR NPCX_I2C_PORT3_0
+#define I2C_PORT_POWER NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
 
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
+#define I2C_PORT_BATTERY I2C_PORT_POWER
+#define I2C_PORT_CHARGER I2C_PORT_EEPROM
 
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 #define CONFIG_I2C_CONTROLLER
 
 #ifndef __ASSEMBLER__
@@ -156,11 +153,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 void board_reset_pd_mcu(void);
 
diff --git a/board/lindar/build.mk b/board/lindar/build.mk
index 43b40c644c..d590255d2a 100644
--- a/board/lindar/build.mk
+++ b/board/lindar/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/lindar/ec.tasklist b/board/lindar/ec.tasklist
index 3e20d8ae39..c29125d517 100644
--- a/board/lindar/ec.tasklist
+++ b/board/lindar/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/lindar/gpio.inc b/board/lindar/gpio.inc
index 30dd2a3920..f8c036b96c 100644
--- a/board/lindar/gpio.inc
+++ b/board/lindar/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,7 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
diff --git a/board/lindar/ktd20xx.h b/board/lindar/ktd20xx.h
index ad93ee3de8..63e3bfb363 100644
--- a/board/lindar/ktd20xx.h
+++ b/board/lindar/ktd20xx.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -120,21 +120,21 @@
  */
 
 enum ktd20xx_register {
-	KTD20XX_ID_DATA     = 0x00,
-	KTD20XX_STATUS_REG  = 0x01,
-	KTD20XX_CTRL_CFG    = 0x02,
-	KTD20XX_IRED_SET0   = 0x03,
-	KTD20XX_IGRN_SET0   = 0x04,
-	KTD20XX_IBLU_SET0   = 0x05,
-	KTD20XX_IRED_SET1   = 0x06,
-	KTD20XX_IGRN_SET1   = 0x07,
-	KTD20XX_IBLU_SET1   = 0x08,
-	KTD20XX_ISEL_A12    = 0x09,
-	KTD20XX_ISEL_A34    = 0x0A,
-	KTD20XX_ISEL_B12    = 0x0B,
-	KTD20XX_ISEL_B34    = 0x0C,
-	KTD20XX_ISEL_C12    = 0x0D,
-	KTD20XX_ISEL_C34    = 0x0E,
+	KTD20XX_ID_DATA = 0x00,
+	KTD20XX_STATUS_REG = 0x01,
+	KTD20XX_CTRL_CFG = 0x02,
+	KTD20XX_IRED_SET0 = 0x03,
+	KTD20XX_IGRN_SET0 = 0x04,
+	KTD20XX_IBLU_SET0 = 0x05,
+	KTD20XX_IRED_SET1 = 0x06,
+	KTD20XX_IGRN_SET1 = 0x07,
+	KTD20XX_IBLU_SET1 = 0x08,
+	KTD20XX_ISEL_A12 = 0x09,
+	KTD20XX_ISEL_A34 = 0x0A,
+	KTD20XX_ISEL_B12 = 0x0B,
+	KTD20XX_ISEL_B34 = 0x0C,
+	KTD20XX_ISEL_C12 = 0x0D,
+	KTD20XX_ISEL_C34 = 0x0E,
 	KTD20XX_TOTOAL_REG
 };
 
diff --git a/board/lindar/led.c b/board/lindar/led.c
index 6d602d5c4e..9ad7b48fb2 100644
--- a/board/lindar/led.c
+++ b/board/lindar/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -23,44 +23,49 @@
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
 __override const int led_charge_lvl_1 = 5;
 
 __override const int led_charge_lvl_2 = 97;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,   1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
 
 __override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]            = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]    = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					 {LED_OFF,         3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					 {LED_OFF,         3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF,            LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    1 * LED_ONE_SEC },
+						  { LED_OFF,
+						    3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -135,9 +140,8 @@ static void controller_write(uint8_t reg, uint8_t val)
 	buf[0] = reg;
 	buf[1] = val;
 
-	i2c_xfer_unlocked(I2C_PORT_LIGHTBAR, ktd2061_i2c_addr,
-			buf, 2, 0, 0,
-			I2C_XFER_SINGLE);
+	i2c_xfer_unlocked(I2C_PORT_LIGHTBAR, ktd2061_i2c_addr, buf, 2, 0, 0,
+			  I2C_XFER_SINGLE);
 }
 
 enum lightbar_states {
@@ -187,51 +191,46 @@ struct lightbar_descriptor {
 	uint8_t ticks;
 };
 
-#define BAR_INFINITE      UINT8_MAX
-#define LIGHTBAR_ONE_SEC  (1000 / HOOK_TICK_INTERVAL_MS)
+#define BAR_INFINITE UINT8_MAX
+#define LIGHTBAR_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS)
 #define LIGHTBAR_COUNT_FOR_RESUME_FROM_SLEEP (3 * LIGHTBAR_ONE_SEC)
 int lightbar_resume_tick;
 
-const struct lightbar_descriptor
-	lb_table[LB_NUM_STATES][LIGHTBAR_NUM_PHASES] = {
-	[LB_STATE_OFF]              = {{BAR_OFF, BAR_INFINITE} },
-	[LB_STATE_LID_CLOSE]        = {{BAR_OFF, BAR_INFINITE} },
-	[LB_STATE_SLEEP_AC_ONLY]    = {{BAR_OFF, BAR_INFINITE} },
-	[LB_STATE_SLEEP_AC_BAT_LOW] = {{BAR_COLOR_ORG_20_PERCENT,
-				BAR_INFINITE} },
-	[LB_STATE_SLEEP_AC_BAT_LV1] = {{BAR_COLOR_GRN_40_PERCENT,
-				BAR_INFINITE} },
-	[LB_STATE_SLEEP_AC_BAT_LV2] = {{BAR_COLOR_GRN_60_PERCENT,
-				BAR_INFINITE} },
-	[LB_STATE_SLEEP_AC_BAT_LV3] = {{BAR_COLOR_GRN_80_PERCENT,
-				BAR_INFINITE} },
-	[LB_STATE_SLEEP_AC_BAT_LV4] = {{BAR_COLOR_GRN_FULL, BAR_INFINITE} },
-	[LB_STATE_SLEEP_BAT_LOW]    = {{BAR_OFF, 5 * LIGHTBAR_ONE_SEC},
-				{BAR_COLOR_ORG_FULL, LIGHTBAR_ONE_SEC} },
-	[LB_STATE_SLEEP_BAT_ONLY]   = {{BAR_OFF, BAR_INFINITE} },
-	[LB_STATE_S0_AC_ONLY]       = {{BAR_OFF, BAR_INFINITE} },
-	[LB_STATE_S0_BAT_LOW]       = {{BAR_COLOR_ORG_20_PERCENT,
-				BAR_INFINITE} },
-	[LB_STATE_S0_BAT_LV1]       = {{BAR_COLOR_GRN_40_PERCENT,
-				BAR_INFINITE} },
-	[LB_STATE_S0_BAT_LV2]       = {{BAR_COLOR_GRN_60_PERCENT,
-				BAR_INFINITE} },
-	[LB_STATE_S0_BAT_LV3]       = {{BAR_COLOR_GRN_80_PERCENT,
-				BAR_INFINITE} },
-	[LB_STATE_S0_BAT_LV4]       = {{BAR_COLOR_GRN_FULL, BAR_INFINITE} },
+const struct lightbar_descriptor lb_table[LB_NUM_STATES][LIGHTBAR_NUM_PHASES] = {
+	[LB_STATE_OFF] = { { BAR_OFF, BAR_INFINITE } },
+	[LB_STATE_LID_CLOSE] = { { BAR_OFF, BAR_INFINITE } },
+	[LB_STATE_SLEEP_AC_ONLY] = { { BAR_OFF, BAR_INFINITE } },
+	[LB_STATE_SLEEP_AC_BAT_LOW] = { { BAR_COLOR_ORG_20_PERCENT,
+					  BAR_INFINITE } },
+	[LB_STATE_SLEEP_AC_BAT_LV1] = { { BAR_COLOR_GRN_40_PERCENT,
+					  BAR_INFINITE } },
+	[LB_STATE_SLEEP_AC_BAT_LV2] = { { BAR_COLOR_GRN_60_PERCENT,
+					  BAR_INFINITE } },
+	[LB_STATE_SLEEP_AC_BAT_LV3] = { { BAR_COLOR_GRN_80_PERCENT,
+					  BAR_INFINITE } },
+	[LB_STATE_SLEEP_AC_BAT_LV4] = { { BAR_COLOR_GRN_FULL, BAR_INFINITE } },
+	[LB_STATE_SLEEP_BAT_LOW] = { { BAR_OFF, 5 * LIGHTBAR_ONE_SEC },
+				     { BAR_COLOR_ORG_FULL, LIGHTBAR_ONE_SEC } },
+	[LB_STATE_SLEEP_BAT_ONLY] = { { BAR_OFF, BAR_INFINITE } },
+	[LB_STATE_S0_AC_ONLY] = { { BAR_OFF, BAR_INFINITE } },
+	[LB_STATE_S0_BAT_LOW] = { { BAR_COLOR_ORG_20_PERCENT, BAR_INFINITE } },
+	[LB_STATE_S0_BAT_LV1] = { { BAR_COLOR_GRN_40_PERCENT, BAR_INFINITE } },
+	[LB_STATE_S0_BAT_LV2] = { { BAR_COLOR_GRN_60_PERCENT, BAR_INFINITE } },
+	[LB_STATE_S0_BAT_LV3] = { { BAR_COLOR_GRN_80_PERCENT, BAR_INFINITE } },
+	[LB_STATE_S0_BAT_LV4] = { { BAR_COLOR_GRN_FULL, BAR_INFINITE } },
 };
 
-#define DISABLE_LIGHTBAR         0x00
-#define ENABLE_LIGHTBAR          0x80
-#define I_OFF                    0x00
-#define GRN_I_ON                 0x1E
-#define ORG_I_ON                 0x28
-#define SEL_OFF                  0x00
-#define SEL_1ST_LED              BIT(7)
-#define SEL_2ND_LED              BIT(3)
-#define SEL_BOTH                 (SEL_1ST_LED | SEL_2ND_LED)
-#define SKU_ID_NONE              0x00
-#define SKU_ID_INVALID           0x01
+#define DISABLE_LIGHTBAR 0x00
+#define ENABLE_LIGHTBAR 0x80
+#define I_OFF 0x00
+#define GRN_I_ON 0x1E
+#define ORG_I_ON 0x28
+#define SEL_OFF 0x00
+#define SEL_1ST_LED BIT(7)
+#define SEL_2ND_LED BIT(3)
+#define SEL_BOTH (SEL_1ST_LED | SEL_2ND_LED)
+#define SKU_ID_NONE 0x00
+#define SKU_ID_INVALID 0x01
 #define LB_SUPPORTED_SKUID_LOWER 458700
 #define LB_SUPPORTED_SKUID_UPPER 458800
 
@@ -259,7 +258,7 @@ static bool lightbar_is_supported(void)
 	 * if system support lightbar or not.
 	 */
 	if (skuid >= LB_SUPPORTED_SKUID_LOWER &&
-		skuid <= LB_SUPPORTED_SKUID_UPPER)
+	    skuid <= LB_SUPPORTED_SKUID_UPPER)
 		result = true;
 	else
 		result = false;
@@ -310,8 +309,7 @@ static void lightbar_set_demo_state(enum lightbar_states tmp_state)
 				LIGHTBAR_COUNT_FOR_RESUME_FROM_SLEEP;
 	}
 	ccprintf("lightbar_demo_state = %d; lightbar_resume_tick %d.\n",
-			lightbar_demo_state,
-			lightbar_resume_tick);
+		 lightbar_demo_state, lightbar_resume_tick);
 }
 
 static enum lightbar_states lightbar_get_demo_state(void)
@@ -321,8 +319,8 @@ static enum lightbar_states lightbar_get_demo_state(void)
 	 * simulate lightbar off.
 	 */
 	if ((lightbar_demo_state != LB_NUM_STATES) &&
-		(lightbar_demo_state >= LB_STATE_S0_AC_ONLY) &&
-		(lightbar_resume_tick == 0))
+	    (lightbar_demo_state >= LB_STATE_S0_AC_ONLY) &&
+	    (lightbar_resume_tick == 0))
 		return LB_STATE_OFF;
 
 	return lightbar_demo_state;
@@ -356,89 +354,65 @@ static bool lightbar_is_enabled(void)
  * ISEL_A12, ISEL_A34, ISEL_B12, ISEL_B34, ISEL_C12, ISEL_C34
  */
 const uint8_t lightbar_10_led_cfg[LIGHTBAR_COLOR_TOTAL][KTD20XX_TOTOAL_REG] = {
-	[BAR_RESET] = {
-		0x00, 0x00, DISABLE_LIGHTBAR,
-		I_OFF, I_OFF, I_OFF, I_OFF, I_OFF, I_OFF,
-		SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF
-	},
-	[BAR_OFF] = {
-		0x00, 0x00, DISABLE_LIGHTBAR,
-		I_OFF, I_OFF, I_OFF, I_OFF, I_OFF, I_OFF,
-		SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF
-	},
-	[BAR_COLOR_ORG_20_PERCENT] = {
-		0x00, 0x00, ENABLE_LIGHTBAR,
-		I_OFF, ORG_I_ON, I_OFF, I_OFF, I_OFF, I_OFF,
-		SEL_OFF, SEL_BOTH, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF
-	},
-	[BAR_COLOR_GRN_40_PERCENT] = {
-		0x00, 0x00, ENABLE_LIGHTBAR,
-		GRN_I_ON, I_OFF, I_OFF, I_OFF, I_OFF, I_OFF,
-		SEL_BOTH, SEL_BOTH, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF
-	},
-	[BAR_COLOR_GRN_60_PERCENT] = {
-		0x00, 0x00, ENABLE_LIGHTBAR,
-		GRN_I_ON, I_OFF, I_OFF, I_OFF, I_OFF, I_OFF,
-		SEL_BOTH, SEL_BOTH, SEL_OFF, SEL_BOTH, SEL_OFF, SEL_OFF
-	},
-	[BAR_COLOR_GRN_80_PERCENT] = {
-		0x00, 0x00, ENABLE_LIGHTBAR,
-		GRN_I_ON, I_OFF, I_OFF, I_OFF, I_OFF, I_OFF,
-		SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_OFF, SEL_OFF
-	},
-	[BAR_COLOR_GRN_FULL] = {
-		0x00, 0x00, ENABLE_LIGHTBAR,
-		GRN_I_ON, I_OFF, I_OFF, I_OFF, I_OFF, I_OFF,
-		SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_OFF
-	},
-	[BAR_COLOR_ORG_FULL] = {
-		0x00, 0x00, ENABLE_LIGHTBAR,
-		I_OFF, ORG_I_ON, I_OFF, I_OFF, I_OFF, I_OFF,
-		SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_OFF
-	}
+	[BAR_RESET] = { 0x00, 0x00, DISABLE_LIGHTBAR, I_OFF, I_OFF, I_OFF,
+			I_OFF, I_OFF, I_OFF, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF,
+			SEL_OFF, SEL_OFF },
+	[BAR_OFF] = { 0x00, 0x00, DISABLE_LIGHTBAR, I_OFF, I_OFF, I_OFF, I_OFF,
+		      I_OFF, I_OFF, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF,
+		      SEL_OFF },
+	[BAR_COLOR_ORG_20_PERCENT] = { 0x00, 0x00, ENABLE_LIGHTBAR, I_OFF,
+				       ORG_I_ON, I_OFF, I_OFF, I_OFF, I_OFF,
+				       SEL_OFF, SEL_BOTH, SEL_OFF, SEL_OFF,
+				       SEL_OFF, SEL_OFF },
+	[BAR_COLOR_GRN_40_PERCENT] = { 0x00, 0x00, ENABLE_LIGHTBAR, GRN_I_ON,
+				       I_OFF, I_OFF, I_OFF, I_OFF, I_OFF,
+				       SEL_BOTH, SEL_BOTH, SEL_OFF, SEL_OFF,
+				       SEL_OFF, SEL_OFF },
+	[BAR_COLOR_GRN_60_PERCENT] = { 0x00, 0x00, ENABLE_LIGHTBAR, GRN_I_ON,
+				       I_OFF, I_OFF, I_OFF, I_OFF, I_OFF,
+				       SEL_BOTH, SEL_BOTH, SEL_OFF, SEL_BOTH,
+				       SEL_OFF, SEL_OFF },
+	[BAR_COLOR_GRN_80_PERCENT] = { 0x00, 0x00, ENABLE_LIGHTBAR, GRN_I_ON,
+				       I_OFF, I_OFF, I_OFF, I_OFF, I_OFF,
+				       SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH,
+				       SEL_OFF, SEL_OFF },
+	[BAR_COLOR_GRN_FULL] = { 0x00, 0x00, ENABLE_LIGHTBAR, GRN_I_ON, I_OFF,
+				 I_OFF, I_OFF, I_OFF, I_OFF, SEL_BOTH, SEL_BOTH,
+				 SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_OFF },
+	[BAR_COLOR_ORG_FULL] = { 0x00, 0x00, ENABLE_LIGHTBAR, I_OFF, ORG_I_ON,
+				 I_OFF, I_OFF, I_OFF, I_OFF, SEL_BOTH, SEL_BOTH,
+				 SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_OFF }
 };
 
 const uint8_t lightbar_12_led_cfg[LIGHTBAR_COLOR_TOTAL][KTD20XX_TOTOAL_REG] = {
-	[BAR_RESET] = {
-		0x00, 0x00, DISABLE_LIGHTBAR,
-		I_OFF, I_OFF, I_OFF, I_OFF, I_OFF, I_OFF,
-		SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF
-	},
-	[BAR_OFF] = {
-		0x00, 0x00, DISABLE_LIGHTBAR,
-		I_OFF, I_OFF, I_OFF, I_OFF, I_OFF, I_OFF,
-		SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF
-	},
-	[BAR_COLOR_ORG_20_PERCENT] = {
-		0x00, 0x00, ENABLE_LIGHTBAR,
-		I_OFF, ORG_I_ON, I_OFF, I_OFF, I_OFF, I_OFF,
-		SEL_2ND_LED, SEL_BOTH, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF
-	},
-	[BAR_COLOR_GRN_40_PERCENT] = {
-		0x00, 0x00, ENABLE_LIGHTBAR,
-		GRN_I_ON, I_OFF, I_OFF, I_OFF, I_OFF, I_OFF,
-		SEL_BOTH, SEL_BOTH, SEL_OFF, SEL_2ND_LED, SEL_OFF, SEL_OFF
-	},
-	[BAR_COLOR_GRN_60_PERCENT] = {
-		0x00, 0x00, ENABLE_LIGHTBAR,
-		GRN_I_ON, I_OFF, I_OFF, I_OFF, I_OFF, I_OFF,
-		SEL_BOTH, SEL_BOTH, SEL_2ND_LED, SEL_BOTH, SEL_OFF, SEL_OFF
-	},
-	[BAR_COLOR_GRN_80_PERCENT] = {
-		0x00, 0x00, ENABLE_LIGHTBAR,
-		GRN_I_ON, I_OFF, I_OFF, I_OFF, I_OFF, I_OFF,
-		SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_OFF, SEL_2ND_LED
-	},
-	[BAR_COLOR_GRN_FULL] = {
-		0x00, 0x00, ENABLE_LIGHTBAR,
-		GRN_I_ON, I_OFF, I_OFF, I_OFF, I_OFF, I_OFF,
-		SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH
-	},
-	[BAR_COLOR_ORG_FULL] = {
-		0x00, 0x00, ENABLE_LIGHTBAR,
-		I_OFF, ORG_I_ON, I_OFF, I_OFF, I_OFF, I_OFF,
-		SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH
-	}
+	[BAR_RESET] = { 0x00, 0x00, DISABLE_LIGHTBAR, I_OFF, I_OFF, I_OFF,
+			I_OFF, I_OFF, I_OFF, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF,
+			SEL_OFF, SEL_OFF },
+	[BAR_OFF] = { 0x00, 0x00, DISABLE_LIGHTBAR, I_OFF, I_OFF, I_OFF, I_OFF,
+		      I_OFF, I_OFF, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF,
+		      SEL_OFF },
+	[BAR_COLOR_ORG_20_PERCENT] = { 0x00, 0x00, ENABLE_LIGHTBAR, I_OFF,
+				       ORG_I_ON, I_OFF, I_OFF, I_OFF, I_OFF,
+				       SEL_2ND_LED, SEL_BOTH, SEL_OFF, SEL_OFF,
+				       SEL_OFF, SEL_OFF },
+	[BAR_COLOR_GRN_40_PERCENT] = { 0x00, 0x00, ENABLE_LIGHTBAR, GRN_I_ON,
+				       I_OFF, I_OFF, I_OFF, I_OFF, I_OFF,
+				       SEL_BOTH, SEL_BOTH, SEL_OFF, SEL_2ND_LED,
+				       SEL_OFF, SEL_OFF },
+	[BAR_COLOR_GRN_60_PERCENT] = { 0x00, 0x00, ENABLE_LIGHTBAR, GRN_I_ON,
+				       I_OFF, I_OFF, I_OFF, I_OFF, I_OFF,
+				       SEL_BOTH, SEL_BOTH, SEL_2ND_LED,
+				       SEL_BOTH, SEL_OFF, SEL_OFF },
+	[BAR_COLOR_GRN_80_PERCENT] = { 0x00, 0x00, ENABLE_LIGHTBAR, GRN_I_ON,
+				       I_OFF, I_OFF, I_OFF, I_OFF, I_OFF,
+				       SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH,
+				       SEL_OFF, SEL_2ND_LED },
+	[BAR_COLOR_GRN_FULL] = { 0x00, 0x00, ENABLE_LIGHTBAR, GRN_I_ON, I_OFF,
+				 I_OFF, I_OFF, I_OFF, I_OFF, SEL_BOTH, SEL_BOTH,
+				 SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH },
+	[BAR_COLOR_ORG_FULL] = { 0x00, 0x00, ENABLE_LIGHTBAR, I_OFF, ORG_I_ON,
+				 I_OFF, I_OFF, I_OFF, I_OFF, SEL_BOTH, SEL_BOTH,
+				 SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH }
 };
 
 /*
@@ -462,7 +436,7 @@ static void lightbar_set_color(enum ec_lightbar_colors color)
 		controller_write(i, lightbar_ctrl[color][i]);
 
 	controller_write(KTD20XX_CTRL_CFG,
-					lightbar_ctrl[color][KTD20XX_CTRL_CFG]);
+			 lightbar_ctrl[color][KTD20XX_CTRL_CFG]);
 
 	i2c_lock(I2C_PORT_LIGHTBAR, 0);
 }
@@ -519,10 +493,10 @@ static void lightbar_sleep_exit(void)
 
 DECLARE_HOOK(HOOK_CHIPSET_RESUME, lightbar_sleep_exit, HOOK_PRIO_DEFAULT);
 
-#define LB_BAT_THRESHOLD_1	16
-#define LB_BAT_THRESHOLD_2	40
-#define LB_BAT_THRESHOLD_3	60
-#define LB_BAT_THRESHOLD_4	80
+#define LB_BAT_THRESHOLD_1 16
+#define LB_BAT_THRESHOLD_2 40
+#define LB_BAT_THRESHOLD_3 60
+#define LB_BAT_THRESHOLD_4 80
 
 static enum lightbar_states lightbar_get_state(void)
 {
@@ -536,7 +510,7 @@ static enum lightbar_states lightbar_get_state(void)
 
 	if (lightbar_resume_tick) {
 		if ((battery_is_present() == BP_YES) &&
-			charge_get_display_charge()) {
+		    charge_get_display_charge()) {
 			if (cur_bat_percent < LB_BAT_THRESHOLD_1)
 				new_state = LB_STATE_S0_BAT_LOW;
 			else if (cur_bat_percent < LB_BAT_THRESHOLD_2)
@@ -557,7 +531,7 @@ static enum lightbar_states lightbar_get_state(void)
 
 	if (extpower_is_present()) {
 		if ((battery_is_present() == BP_YES) &&
-			charge_get_display_charge()) {
+		    charge_get_display_charge()) {
 			if (cur_bat_percent < LB_BAT_THRESHOLD_1)
 				new_state = LB_STATE_SLEEP_AC_BAT_LOW;
 			else if (cur_bat_percent < LB_BAT_THRESHOLD_2)
@@ -607,15 +581,14 @@ static void lightbar_update(void)
 	if (lightbar_resume_tick)
 		lightbar_resume_tick--;
 
-	if (desired_state != lb_cur_state &&
-		desired_state < LB_NUM_STATES) {
+	if (desired_state != lb_cur_state && desired_state < LB_NUM_STATES) {
 		/* State is changing */
 		lb_cur_state = desired_state;
 		/* Reset ticks and period when state changes */
 		ticks = 0;
 
 		period = lb_table[lb_cur_state][LIGHTBAR_PHASE_0].ticks +
-			lb_table[lb_cur_state][LIGHTBAR_PHASE_1].ticks;
+			 lb_table[lb_cur_state][LIGHTBAR_PHASE_1].ticks;
 
 		/*
 		 * System will be waken up when AC status change in S0ix. Due to
@@ -630,7 +603,8 @@ static void lightbar_update(void)
 	/* If this state is undefined, turn lightbar off */
 	if (period == 0) {
 		CPRINTS("Undefined lightbar behavior for lightbar state %d,"
-			"turning off lightbar", lb_cur_state);
+			"turning off lightbar",
+			lb_cur_state);
 		lightbar_set_color(BAR_OFF);
 		return;
 	}
@@ -649,7 +623,6 @@ static void lightbar_update(void)
 
 	/* Set the color for the given state and phase */
 	lightbar_set_color(lb_table[lb_cur_state][phase].color);
-
 }
 
 DECLARE_HOOK(HOOK_TICK, lightbar_update, HOOK_PRIO_DEFAULT);
@@ -663,17 +636,15 @@ static void lightbar_dump_status(void)
 	int cbi_ssfc_lightbar;
 
 	ccprintf("lightbar is %ssupported, %sabled, auto_control: %sabled\n",
-			lightbar_is_supported()?"":"un-",
-			lightbar_is_enabled()?"en":"dis",
-			lightbar_is_auto_control()?"en":"dis");
+		 lightbar_is_supported() ? "" : "un-",
+		 lightbar_is_enabled() ? "en" : "dis",
+		 lightbar_is_auto_control() ? "en" : "dis");
 
 	cbi_bid = get_board_id();
 	cbi_get_sku_id(&cbi_skuid);
 	cbi_ssfc_lightbar = get_cbi_ssfc_lightbar();
-	ccprintf("board id = %d, skuid = %d, ssfc_lightbar = %d\n",
-			cbi_bid,
-			cbi_skuid,
-			cbi_ssfc_lightbar);
+	ccprintf("board id = %d, skuid = %d, ssfc_lightbar = %d\n", cbi_bid,
+		 cbi_skuid, cbi_ssfc_lightbar);
 }
 
 #ifdef CONFIG_CONSOLE_CMDHELP
@@ -682,16 +653,16 @@ static int help(const char *cmd)
 	ccprintf("Usage:\n");
 	ccprintf("  %s                       - dump lightbar status\n", cmd);
 	ccprintf("  %s on                    - set on lightbar auto control\n",
-				cmd);
+		 cmd);
 	ccprintf("  %s off                   - set off lightbar auto control\n",
-				cmd);
-	ccprintf("  %s demo [%x - %x]          - demo lightbar state\n",
-				cmd, LB_STATE_OFF, (LB_NUM_STATES - 1));
+		 cmd);
+	ccprintf("  %s demo [%x - %x]          - demo lightbar state\n", cmd,
+		 LB_STATE_OFF, (LB_NUM_STATES - 1));
 	return EC_SUCCESS;
 }
 #endif
 
-static int command_lightbar(int argc, char **argv)
+static int command_lightbar(int argc, const char **argv)
 {
 	/* no args = dump lightbar status */
 	if (argc == 1) {
@@ -700,9 +671,9 @@ static int command_lightbar(int argc, char **argv)
 	}
 
 	if (!strcasecmp(argv[1], "help")) {
-	#ifdef CONFIG_CONSOLE_CMDHELP
+#ifdef CONFIG_CONSOLE_CMDHELP
 		help(argv[0]);
-	#endif
+#endif
 		return EC_SUCCESS;
 	}
 
@@ -744,8 +715,7 @@ static int command_lightbar(int argc, char **argv)
 	return EC_ERROR_INVAL;
 }
 
-DECLARE_CONSOLE_COMMAND(lightbar, command_lightbar,
-			"[help | on | off | demo]",
+DECLARE_CONSOLE_COMMAND(lightbar, command_lightbar, "[help | on | off | demo]",
 			"get/set lightbar status");
 
 /****************************************************************************/
@@ -788,6 +758,4 @@ static enum ec_status lpc_cmd_lightbar(struct host_cmd_handler_args *args)
 	return EC_RES_SUCCESS;
 }
 
-DECLARE_HOST_COMMAND(EC_CMD_LIGHTBAR_CMD,
-		     lpc_cmd_lightbar,
-		     EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_LIGHTBAR_CMD, lpc_cmd_lightbar, EC_VER_MASK(0));
diff --git a/board/madoo/battery.c b/board/madoo/battery.c
index 92afe149f3..b37cb463dd 100644
--- a/board/madoo/battery.c
+++ b/board/madoo/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -12,7 +12,7 @@
 #include "extpower.h"
 
 /* Shutdown mode parameter to write to manufacturer access register */
-#define SB_SHUTDOWN_DATA	0x0010
+#define SB_SHUTDOWN_DATA 0x0010
 
 const struct board_batt_params board_battery_info[] = {
 	[BATTERY_SIMPLO_HIGHPOWER] = {
diff --git a/board/madoo/board.c b/board/madoo/board.c
index 2f465a81f0..eedf8e6fdd 100644
--- a/board/madoo/board.c
+++ b/board/madoo/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -46,8 +46,8 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 #define INT_RECHECK_US 5000
 
@@ -87,7 +87,6 @@ static void usb_c0_interrupt(enum gpio_signal s)
 
 	/* Check the line again in 5ms */
 	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-
 }
 
 /* C1 interrupt line shared by BC 1.2, TCPC, and charger */
@@ -122,7 +121,6 @@ static void sub_usb_c1_interrupt(enum gpio_signal s)
 
 	/* Check the line again in 5ms */
 	hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
-
 }
 
 static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
@@ -237,8 +235,7 @@ __override void board_power_5v_enable(int enable)
 	set_5v_gpio(!!enable);
 
 	if (isl923x_set_comparator_inversion(1, !!enable))
-		CPRINTS("Failed to %sable sub rails!", enable ?
-								"en" : "dis");
+		CPRINTS("Failed to %sable sub rails!", enable ? "en" : "dis");
 }
 
 int board_is_sourcing_vbus(int port)
@@ -247,13 +244,11 @@ int board_is_sourcing_vbus(int port)
 
 	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
 	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
-
 }
 
 int board_set_active_charge_port(int port)
 {
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	int i;
 	int old_port;
 
@@ -317,8 +312,8 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
 
@@ -344,17 +339,13 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrices to rotate accelerometers into the standard reference. */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					     { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					      { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
 
 static struct accelgyro_saved_data_t g_bma253_data;
 static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
@@ -434,20 +425,19 @@ const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
 /* Thermistors */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Charger",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Charger",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
+__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+				       int *ki_div, int *kd, int *kd_div)
 {
 	*kp = 1;
 	*kp_div = 20;
@@ -522,31 +512,43 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usbc0_retimer = {
-	.usb_port = 0,
-	.i2c_port = I2C_PORT_USB_C0,
-	.i2c_addr_flags = NB7V904M_I2C_ADDR0,
-	.driver = &nb7v904m_usb_redriver_drv,
+const struct usb_mux_chain usbc0_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = 0,
+			.i2c_port = I2C_PORT_USB_C0,
+			.i2c_addr_flags = NB7V904M_I2C_ADDR0,
+			.driver = &nb7v904m_usb_redriver_drv,
+		},
 };
-const struct usb_mux usbc1_retimer = {
-	.usb_port = 1,
-	.i2c_port = I2C_PORT_SUB_USB_C1,
-	.i2c_addr_flags = NB7V904M_I2C_ADDR0,
-	.driver = &nb7v904m_usb_redriver_drv,
+const struct usb_mux_chain usbc1_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = 1,
+			.i2c_port = I2C_PORT_SUB_USB_C1,
+			.i2c_addr_flags = NB7V904M_I2C_ADDR0,
+			.driver = &nb7v904m_usb_redriver_drv,
+		},
 };
-struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
-		.driver = &pi3usb3x532_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
+				.driver = &pi3usb3x532_usb_mux_driver,
+			},
 	},
 	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
-		.driver = &pi3usb3x532_usb_mux_driver,
-		.next_mux = &usbc1_retimer,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_SUB_USB_C1,
+				.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
+				.driver = &pi3usb3x532_usb_mux_driver,
+			},
+		.next = &usbc1_retimer,
 	}
 };
 
@@ -554,10 +556,10 @@ static void reconfigure_usbmux(void)
 {
 	if (system_get_board_version() < 2) {
 		CPRINTS("add redriver at usbc0");
-		usb_muxes[0].next_mux = &usbc0_retimer;
+		usb_muxes[0].next = &usbc0_retimer;
 	}
 }
-DECLARE_HOOK(HOOK_INIT, reconfigure_usbmux, HOOK_PRIO_INIT_I2C+1);
+DECLARE_HOOK(HOOK_INIT, reconfigure_usbmux, HOOK_PRIO_INIT_I2C + 1);
 
 uint16_t tcpc_get_alert_status(void)
 {
diff --git a/board/madoo/board.h b/board/madoo/board.h
index 1a0e37ac90..82cfa30b0e 100644
--- a/board/madoo/board.h
+++ b/board/madoo/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,11 +13,14 @@
 
 /* Charger */
 #define CONFIG_CHARGER_RAA489000
+#define PD_MAX_VOLTAGE_MV 20000
 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 #define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */
+#define CONFIG_OCPC_DEF_RBATT_MOHMS               \
+	22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \
+	    */
 #define CONFIG_OCPC
-#undef  CONFIG_CHARGER_SINGLE_CHIP
+#undef CONFIG_CHARGER_SINGLE_CHIP
 
 /* EC console commands */
 #define CONFIG_CMD_TCPC_DUMP
@@ -31,7 +34,7 @@
 
 /* PWM */
 #define CONFIG_PWM
-#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
+#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */
 
 /* USB */
 #define CONFIG_BC12_DETECT_PI3USB9201
@@ -58,16 +61,16 @@
 #define CONFIG_USB_PD_5V_EN_CUSTOM
 
 /* I2C configuration */
-#define I2C_PORT_EEPROM     NPCX_I2C_PORT7_0
-#define I2C_PORT_BATTERY    NPCX_I2C_PORT5_0
-#define I2C_PORT_SENSOR     NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0     NPCX_I2C_PORT1_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
 #define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_MUX    I2C_PORT_USB_C0
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0
 /* TODO(b:147440290): Need to handle multiple charger ICs */
-#define I2C_PORT_CHARGER    I2C_PORT_USB_C0
+#define I2C_PORT_CHARGER I2C_PORT_USB_C0
 
-#define I2C_PORT_ACCEL      I2C_PORT_SENSOR
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
 
 #define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */
 
@@ -75,16 +78,15 @@
 #define CONFIG_CMD_ACCELS
 #define CONFIG_CMD_ACCEL_INFO
 
-#define CONFIG_ACCEL_BMA255		/* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM	/* Base accel */
+#define CONFIG_ACCEL_BMA255 /* Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
 
 /* Lid operates in forced mode, base in FIFO */
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
 #define CONFIG_ACCEL_FIFO
-#define CONFIG_ACCEL_FIFO_SIZE 256	/* Must be a power of 2 */
+#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */
 #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
 
-
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_UPDATE
 #define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
@@ -119,25 +121,16 @@ enum chg_id {
 };
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_1,     /* ADC0 */
-	ADC_TEMP_SENSOR_2,     /* ADC1 */
-	ADC_SUB_ANALOG,	       /* ADC2 */
-	ADC_VSNS_PP3300_A,     /* ADC9 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
+	ADC_SUB_ANALOG, /* ADC2 */
+	ADC_VSNS_PP3300_A, /* ADC9 */
 	ADC_CH_COUNT
 };
 
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_COUNT
-};
+enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT };
 
 enum pwm_channel {
 	PWM_CH_KBLIGHT,
diff --git a/board/madoo/build.mk b/board/madoo/build.mk
index cd002a20e7..1531d1f3ae 100644
--- a/board/madoo/build.mk
+++ b/board/madoo/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/madoo/cbi_ssfc.c b/board/madoo/cbi_ssfc.c
index c4b859f133..81f3ee0dad 100644
--- a/board/madoo/cbi_ssfc.c
+++ b/board/madoo/cbi_ssfc.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
 
 enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
 {
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
 }
 
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
 {
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
 }
diff --git a/board/madoo/cbi_ssfc.h b/board/madoo/cbi_ssfc.h
index 873b90f993..13800bcc85 100644
--- a/board/madoo/cbi_ssfc.h
+++ b/board/madoo/cbi_ssfc.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -57,5 +57,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
  */
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
 
-
 #endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/madoo/ec.tasklist b/board/madoo/ec.tasklist
index 0aba1fabeb..ba5855412d 100644
--- a/board/madoo/ec.tasklist
+++ b/board/madoo/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/madoo/gpio.inc b/board/madoo/gpio.inc
index b26c7814ce..d3eb97ed11 100644
--- a/board/madoo/gpio.inc
+++ b/board/madoo/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/madoo/led.c b/board/madoo/led.c
index aef7b0e425..90cd0ab210 100644
--- a/board/madoo/led.c
+++ b/board/madoo/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -14,8 +14,8 @@
 #include "hooks.h"
 #include "system.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
 __override const int led_charge_lvl_1;
 
@@ -23,34 +23,40 @@ __override const int led_charge_lvl_2 = 100;
 
 /* madoo: Note there is only LED for charge / power */
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF, 1 * LED_ONE_SEC} },
-	/* STATE_DISCHARGE_S3 will changed if sku is clamshells */
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER, 0.5 * LED_ONE_SEC},
-					{LED_OFF, 0.5 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 1 * LED_ONE_SEC } },
+		/* STATE_DISCHARGE_S3 will changed if sku is clamshells */
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    0.5 * LED_ONE_SEC },
+					  { LED_OFF, 0.5 * LED_ONE_SEC } },
+	};
 
 __override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   1 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   1 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 1 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    1 * LED_ONE_SEC },
+						  { LED_OFF,
+						    1 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -77,8 +83,8 @@ int battery_safety_check(void)
 		return false;
 
 	/* turn off LED due to a safety fault */
-	rv = sb_read_mfgacc(PARAM_SAFETY_STATUS,
-			    SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data));
+	rv = sb_read_mfgacc(PARAM_SAFETY_STATUS, SB_ALT_MANUFACTURER_ACCESS,
+			    data, sizeof(data));
 	if (rv)
 		return false;
 	/*
@@ -111,7 +117,7 @@ __override void led_set_color_battery(enum ec_led_colors color)
 			gpio_set_level(GPIO_BAT_LED_WHITE_L, LED_OFF_LVL);
 			gpio_set_level(GPIO_EC_CHG_LED_R_W, LED_OFF_LVL);
 		} else if (charge_manager_get_active_charge_port() == 1 ||
-			system_get_board_version() < 3) {
+			   system_get_board_version() < 3) {
 			gpio_set_level(GPIO_BAT_LED_WHITE_L, LED_ON_LVL);
 			gpio_set_level(GPIO_BAT_LED_AMBER_L, LED_OFF_LVL);
 		} else if (charge_manager_get_active_charge_port() == 0) {
@@ -125,11 +131,11 @@ __override void led_set_color_battery(enum ec_led_colors color)
 			gpio_set_level(GPIO_BAT_LED_AMBER_L, LED_OFF_LVL);
 			gpio_set_level(GPIO_EC_CHG_LED_R_Y, LED_OFF_LVL);
 		} else if (charge_get_state() == PWR_STATE_ERROR &&
-				system_get_board_version() >= 3) {
+			   system_get_board_version() >= 3) {
 			gpio_set_level(GPIO_EC_CHG_LED_R_W, LED_OFF_LVL);
 			gpio_set_level(GPIO_EC_CHG_LED_R_Y, LED_ON_LVL);
 		} else if (charge_manager_get_active_charge_port() == 1 ||
-				system_get_board_version() < 3) {
+			   system_get_board_version() < 3) {
 			gpio_set_level(GPIO_BAT_LED_WHITE_L, LED_OFF_LVL);
 			gpio_set_level(GPIO_BAT_LED_AMBER_L, LED_ON_LVL);
 			gpio_set_level(GPIO_EC_CHG_LED_R_Y, LED_OFF_LVL);
@@ -137,7 +143,7 @@ __override void led_set_color_battery(enum ec_led_colors color)
 			gpio_set_level(GPIO_EC_CHG_LED_R_W, LED_OFF_LVL);
 			gpio_set_level(GPIO_EC_CHG_LED_R_Y, LED_ON_LVL);
 		} else if (charge_get_percent() <
-				CONFIG_LED_ONOFF_STATES_BAT_LOW) {
+			   CONFIG_LED_ONOFF_STATES_BAT_LOW) {
 			gpio_set_level(GPIO_EC_CHG_LED_R_W, LED_OFF_LVL);
 			gpio_set_level(GPIO_EC_CHG_LED_R_Y, LED_ON_LVL);
 		}
diff --git a/board/madoo/usb_pd_policy.c b/board/madoo/usb_pd_policy.c
index 02bb449f60..2bad4d6931 100644
--- a/board/madoo/usb_pd_policy.c
+++ b/board/madoo/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,8 @@
 #include "driver/tcpm/tcpci.h"
 #include "usb_pd.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
diff --git a/board/magolor/battery.c b/board/magolor/battery.c
index 84f75732ec..e9bacbbf58 100644
--- a/board/magolor/battery.c
+++ b/board/magolor/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/magolor/board.c b/board/magolor/board.c
index 710a94f54a..bfa77375e5 100644
--- a/board/magolor/board.c
+++ b/board/magolor/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -52,13 +52,13 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 #define INT_RECHECK_US 5000
 
-#define ADC_VOL_UP_MASK     BIT(0)
-#define ADC_VOL_DOWN_MASK   BIT(1)
+#define ADC_VOL_UP_MASK BIT(0)
+#define ADC_VOL_DOWN_MASK BIT(1)
 
 static uint8_t new_adc_key_state;
 
@@ -165,8 +165,7 @@ static const struct ec_response_keybd_config magma_keybd = {
 	.capabilities = KEYBD_CAP_SCRNLOCK_KEY | KEYBD_CAP_NUMERIC_KEYPAD,
 };
 
-__override
-uint8_t board_keyboard_row_refresh(void)
+__override uint8_t board_keyboard_row_refresh(void)
 {
 	if (gpio_get_level(GPIO_EC_VIVALDIKEYBOARD_ID))
 		return 3;
@@ -174,16 +173,15 @@ uint8_t board_keyboard_row_refresh(void)
 		return 2;
 }
 
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	if (get_cbi_fw_config_numeric_pad()) {
 		if (gpio_get_level(GPIO_EC_VIVALDIKEYBOARD_ID))
 			return &magma_keybd;
 		else
 			return &magpie_keybd;
-	}
-	else {
+	} else {
 		if (gpio_get_level(GPIO_EC_VIVALDIKEYBOARD_ID))
 			return &magister_keybd;
 		else
@@ -198,16 +196,15 @@ __override const struct ec_response_keybd_config
  * that we don't have pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-	{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-	{0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3},
-	{-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0},
-	{1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4},
-	{2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0},
-	{-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1},
-	{-1, -1},
+	{ -1, -1 }, { 0, 5 },	{ 1, 1 }, { 1, 0 },   { 0, 6 },	  { 0, 7 },
+	{ -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 },   { -1, -1 }, { 1, 6 },
+	{ 1, 7 },   { 3, 1 },	{ 2, 0 }, { 1, 5 },   { 2, 6 },	  { 2, 7 },
+	{ 2, 1 },   { 2, 4 },	{ 2, 5 }, { 1, 2 },   { 2, 3 },	  { 2, 2 },
+	{ 3, 0 },   { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 },	  { -1, -1 },
+	{ -1, -1 },
 };
 const int keyboard_factory_scan_pins_used =
-		ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 
 /* C0 interrupt line shared by BC 1.2 and charger */
 static void check_c0_line(void);
@@ -245,7 +242,6 @@ static void usb_c0_interrupt(enum gpio_signal s)
 
 	/* Check the line again in 5ms */
 	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-
 }
 
 /* C1 interrupt line shared by BC 1.2, TCPC, and charger */
@@ -326,22 +322,22 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* Thermistors */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_A \
-	{ \
+#define THERMAL_A                \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = 0, \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
@@ -358,8 +354,8 @@ __maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_B \
-	{ \
+#define THERMAL_B                \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = 0, \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(73), \
@@ -443,7 +439,7 @@ static void reconfigure_5v_gpio(void)
 		gpio_set_flags(GPIO_VOLUP_BTN_ODL, GPIO_OUT_LOW);
 	}
 }
-DECLARE_HOOK(HOOK_INIT, reconfigure_5v_gpio, HOOK_PRIO_INIT_I2C+1);
+DECLARE_HOOK(HOOK_INIT, reconfigure_5v_gpio, HOOK_PRIO_INIT_I2C + 1);
 #endif /* BOARD_WADDLEDOO */
 
 static void set_5v_gpio(int level)
@@ -492,8 +488,8 @@ __override void board_power_5v_enable(int enable)
 		gpio_set_level(GPIO_SUB_C1_INT_EN_RAILS_ODL, !enable);
 	} else {
 		if (isl923x_set_comparator_inversion(1, !!enable))
-			CPRINTS("Failed to %sable sub rails!", enable ?
-								  "en" : "dis");
+			CPRINTS("Failed to %sable sub rails!",
+				enable ? "en" : "dis");
 
 		if (!enable)
 			return;
@@ -503,7 +499,7 @@ __override void board_power_5v_enable(int enable)
 		 */
 		if (get_cbi_ssfc_usb_mux() == SSFC_USBMUX_PS8762)
 			hook_call_deferred(&ps8762_chaddr_deferred_data,
-						   15 * MSEC);
+					   15 * MSEC);
 	}
 }
 
@@ -529,13 +525,11 @@ int board_is_sourcing_vbus(int port)
 
 	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
 	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
-
 }
 
 int board_set_active_charge_port(int port)
 {
-	int is_real_port = (port >= 0 &&
-			    port < board_get_usb_pd_port_count());
+	int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count());
 	int i;
 	int old_port;
 
@@ -599,8 +593,8 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
 
@@ -625,25 +619,18 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrices to rotate accelerometers into the standard reference. */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
 /* Matrices to rotate accelerometers into the magister reference. */
-static const mat33_fp_t lid_magister_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
-
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_magister_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
 
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					      { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
 
 /* BMA253 private data */
 static struct accelgyro_saved_data_t g_bma253_data;
@@ -652,11 +639,9 @@ static struct accelgyro_saved_data_t g_bma253_data;
 static struct bmi_drv_data_t g_bmi160_data;
 
 #ifdef BOARD_MAGOLOR
-static const mat33_fp_t base_icm_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t base_icm_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					 { 0, FLOAT_TO_FP(1), 0 },
+					 { 0, 0, FLOAT_TO_FP(-1) } };
 
 /* ICM426 private data */
 static struct icm_drv_data_t g_icm426xx_data;
@@ -814,7 +799,7 @@ unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 static void pendetect_deferred(void)
 {
 	int pen_charge_enable = !gpio_get_level(GPIO_PEN_DET_ODL) &&
-	    !chipset_in_state(CHIPSET_STATE_ANY_OFF);
+				!chipset_in_state(CHIPSET_STATE_ANY_OFF);
 
 	if (pen_charge_enable)
 		gpio_set_level(GPIO_EN_PP5000_PEN, 1);
@@ -839,15 +824,21 @@ static void pen_charge_check(void)
 DECLARE_HOOK(HOOK_CHIPSET_STARTUP, pen_charge_check, HOOK_PRIO_LAST);
 DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, pen_charge_check, HOOK_PRIO_LAST);
 
-
 /*****************************************************************************
  * USB-C MUX/Retimer dynamic configuration
  */
+struct usb_mux usbc1_mux0 = {
+	.usb_port = 1,
+	.i2c_port = I2C_PORT_SUB_USB_C1,
+	.i2c_addr_flags = PS8802_I2C_ADDR_FLAGS_CUSTOM,
+	.driver = &ps8802_usb_mux_driver,
+};
+
 static void setup_mux(void)
 {
 	if (get_cbi_ssfc_usb_mux() == SSFC_USBMUX_PS8743) {
-		usb_muxes[USBC_PORT_C1].i2c_addr_flags = PS8743_I2C_ADDR0_FLAG;
-		usb_muxes[USBC_PORT_C1].driver = &ps8743_usb_mux_driver;
+		usbc1_mux0.i2c_addr_flags = PS8743_I2C_ADDR0_FLAG;
+		usbc1_mux0.driver = &ps8743_usb_mux_driver;
 		ccprints("PS8743 USB MUX");
 	} else
 		ccprints("PS8762 USB MUX");
@@ -862,16 +853,17 @@ void board_init(void)
 
 	if (get_cbi_fw_config_db() == DB_1A_HDMI) {
 		/* Disable i2c on HDMI pins */
-		gpio_config_pin(MODULE_I2C,
-				GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL, 0);
-		gpio_config_pin(MODULE_I2C,
-				GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL, 0);
+		gpio_config_pin(MODULE_I2C, GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL,
+				0);
+		gpio_config_pin(MODULE_I2C, GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL,
+				0);
 
 		/* Set HDMI and sub-rail enables to output */
 		gpio_set_flags(GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL,
 			       chipset_in_state(CHIPSET_STATE_ON) ?
-						GPIO_ODR_LOW : GPIO_ODR_HIGH);
-		gpio_set_flags(GPIO_SUB_C1_INT_EN_RAILS_ODL,   GPIO_ODR_HIGH);
+				       GPIO_ODR_LOW :
+				       GPIO_ODR_HIGH);
+		gpio_set_flags(GPIO_SUB_C1_INT_EN_RAILS_ODL, GPIO_ODR_HIGH);
 
 		/* Select HDMI option */
 		gpio_set_level(GPIO_HDMI_SEL_L, 0);
@@ -881,8 +873,7 @@ void board_init(void)
 
 	} else {
 		/* Set SDA as an input */
-		gpio_set_flags(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL,
-			       GPIO_INPUT);
+		gpio_set_flags(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL, GPIO_INPUT);
 
 		/* Enable C1 interrupt and check if it needs processing */
 		gpio_enable_interrupt(GPIO_SUB_C1_INT_EN_RAILS_ODL);
@@ -907,8 +898,8 @@ void board_init(void)
 			ccprints("LID_ACCEL is KX022");
 		} else {
 			if (system_get_board_version() >= 5) {
-				motion_sensors[LID_ACCEL]
-				.rot_standard_ref = &lid_magister_ref;
+				motion_sensors[LID_ACCEL].rot_standard_ref =
+					&lid_magister_ref;
 			}
 			ccprints("LID_ACCEL is BMA253");
 		}
@@ -921,7 +912,7 @@ void board_init(void)
 		gmr_tablet_switch_disable();
 		/* Base accel is not stuffed, don't allow line to float */
 		gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L,
-		GPIO_INPUT | GPIO_PULL_DOWN);
+			       GPIO_INPUT | GPIO_PULL_DOWN);
 	}
 
 	if (get_cbi_fw_config_stylus() == STYLUS_PRESENT) {
@@ -930,8 +921,7 @@ void board_init(void)
 		pen_charge_check();
 	} else {
 		gpio_disable_interrupt(GPIO_PEN_DET_ODL);
-		gpio_set_flags(GPIO_PEN_DET_ODL,
-		GPIO_INPUT | GPIO_PULL_DOWN);
+		gpio_set_flags(GPIO_PEN_DET_ODL, GPIO_INPUT | GPIO_PULL_DOWN);
 	}
 
 	/* Turn on 5V if the system is on, otherwise turn it off. */
@@ -944,32 +934,30 @@ void board_init(void)
 
 #ifdef BOARD_MAGOLOR
 	/* Support Keyboard Pad */
-		board_update_no_keypad_by_fwconfig();
+	board_update_no_keypad_by_fwconfig();
 #endif
-
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
 void motion_interrupt(enum gpio_signal signal)
 {
 #ifdef BOARD_MAGOLOR
-		switch (get_cbi_ssfc_base_sensor()) {
-		case SSFC_SENSOR_ICM426XX:
-			icm426xx_interrupt(signal);
-			break;
-		case SSFC_SENSOR_BMI160:
-		default:
-			bmi160_interrupt(signal);
-			break;
-		}
-	#else
+	switch (get_cbi_ssfc_base_sensor()) {
+	case SSFC_SENSOR_ICM426XX:
+		icm426xx_interrupt(signal);
+		break;
+	case SSFC_SENSOR_BMI160:
+	default:
 		bmi160_interrupt(signal);
+		break;
+	}
+#else
+	bmi160_interrupt(signal);
 #endif
 }
 
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
+__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+				       int *ki_div, int *kd, int *kd_div)
 {
 	*kp = 1;
 	*kp_div = 20;
@@ -1045,18 +1033,17 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USBC_PORT_C0] = {
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
-		.driver = &pi3usb3x532_usb_mux_driver,
+		.mux = &(const struct usb_mux) {
+			.usb_port = 0,
+			.i2c_port = I2C_PORT_USB_C0,
+			.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
+			.driver = &pi3usb3x532_usb_mux_driver,
+		},
 	},
 	[USBC_PORT_C1] = {
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PS8802_I2C_ADDR_FLAGS_CUSTOM,
-		.driver = &ps8802_usb_mux_driver,
+		.mux = &usbc1_mux0,
 	}
 };
 
@@ -1082,7 +1069,7 @@ uint16_t tcpc_get_alert_status(void)
 	}
 
 	if (board_get_usb_pd_port_count() > 1 &&
-				!gpio_get_level(GPIO_SUB_C1_INT_EN_RAILS_ODL)) {
+	    !gpio_get_level(GPIO_SUB_C1_INT_EN_RAILS_ODL)) {
 		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
 			/* TCPCI spec Rev 1.0 says to ignore bits 14:12. */
 			if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0))
diff --git a/board/magolor/board.h b/board/magolor/board.h
index 40391d16c6..481856323f 100644
--- a/board/magolor/board.h
+++ b/board/magolor/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -34,11 +34,14 @@
 
 /* Charger */
 #define CONFIG_CHARGER_RAA489000
+#define PD_MAX_VOLTAGE_MV 20000
 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 #define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */
+#define CONFIG_OCPC_DEF_RBATT_MOHMS               \
+	22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \
+	    */
 #define CONFIG_OCPC
-#undef  CONFIG_CHARGER_SINGLE_CHIP
+#undef CONFIG_CHARGER_SINGLE_CHIP
 #undef CONFIG_CMD_CHARGER_DUMP
 #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
 #define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
@@ -59,7 +62,7 @@
 
 /* PWM */
 #define CONFIG_PWM
-#define NPCX7_PWM1_SEL    1  /* GPIO C2 is used as PWM1. */
+#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */
 
 /* Temp sensor */
 #define CONFIG_TEMP_SENSOR
@@ -98,16 +101,16 @@
 #define CONFIG_USB_PD_5V_EN_CUSTOM
 
 /* I2C configuration */
-#define I2C_PORT_EEPROM     NPCX_I2C_PORT7_0
-#define I2C_PORT_BATTERY    NPCX_I2C_PORT5_0
-#define I2C_PORT_SENSOR     NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0     NPCX_I2C_PORT1_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
 #define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_MUX    I2C_PORT_USB_C0
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0
 /* TODO(b:147440290): Need to handle multiple charger ICs */
-#define I2C_PORT_CHARGER    I2C_PORT_USB_C0
+#define I2C_PORT_CHARGER I2C_PORT_USB_C0
 
-#define I2C_PORT_ACCEL      I2C_PORT_SENSOR
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
 
 #define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */
 
@@ -125,18 +128,18 @@
 #define CONFIG_CMD_ACCEL_INFO
 #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
 
-#define CONFIG_ACCEL_BMA255		/* Lid accel */
-#define CONFIG_ACCELGYRO_BMI160		/* Base accel */
+#define CONFIG_ACCEL_BMA255 /* Lid accel */
+#define CONFIG_ACCELGYRO_BMI160 /* Base accel */
 
 #ifdef BOARD_MAGOLOR
-#define CONFIG_ACCEL_KX022		/* Lid accel */
-#define CONFIG_ACCELGYRO_ICM426XX	/* Base accel second source*/
+#define CONFIG_ACCEL_KX022 /* Lid accel */
+#define CONFIG_ACCELGYRO_ICM426XX /* Base accel second source*/
 #endif
 
 /* Lid operates in forced mode, base in FIFO */
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
 #define CONFIG_ACCEL_FIFO
-#define CONFIG_ACCEL_FIFO_SIZE 256	/* Must be a power of 2 */
+#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */
 #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
 
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
@@ -174,25 +177,16 @@ enum chg_id {
 };
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_1,     /* ADC0 */
-	ADC_TEMP_SENSOR_2,     /* ADC1 */
-	ADC_SUB_ANALOG,	       /* ADC2 */
-	ADC_VSNS_PP3300_A,     /* ADC9 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
+	ADC_SUB_ANALOG, /* ADC2 */
+	ADC_VSNS_PP3300_A, /* ADC9 */
 	ADC_CH_COUNT
 };
 
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_COUNT
-};
+enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT };
 
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
 enum pwm_channel {
 	PWM_CH_KBLIGHT,
@@ -208,11 +202,7 @@ enum battery_type {
 	BATTERY_TYPE_COUNT,
 };
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 void motion_interrupt(enum gpio_signal signal);
 void pen_detect_interrupt(enum gpio_signal s);
diff --git a/board/magolor/build.mk b/board/magolor/build.mk
index fcf5dec3ed..c69e903608 100644
--- a/board/magolor/build.mk
+++ b/board/magolor/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/magolor/cbi_ssfc.c b/board/magolor/cbi_ssfc.c
index 7708bb9905..155ecae6bf 100644
--- a/board/magolor/cbi_ssfc.c
+++ b/board/magolor/cbi_ssfc.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,15 +27,15 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
 
 enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
 {
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
 }
 
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
 {
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
 }
 
 enum ec_ssfc_usb_mux get_cbi_ssfc_usb_mux(void)
 {
-	return (enum ec_ssfc_usb_mux) cached_ssfc.usb_mux;
+	return (enum ec_ssfc_usb_mux)cached_ssfc.usb_mux;
 }
diff --git a/board/magolor/cbi_ssfc.h b/board/magolor/cbi_ssfc.h
index f59d165071..78e32f5810 100644
--- a/board/magolor/cbi_ssfc.h
+++ b/board/magolor/cbi_ssfc.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -45,12 +45,12 @@ union dedede_cbi_ssfc {
 	struct {
 		uint32_t base_sensor : 3;
 		uint32_t lid_sensor : 3;
-		uint32_t cam_wfc: 3;
-		uint32_t cam_ufc: 2;
-		uint32_t cam_vcm: 2;
-		uint32_t TS_Source: 4;
-		uint32_t AUDIO_CODEC_SOURCE: 3;
-		uint32_t usb_mux: 2;
+		uint32_t cam_wfc : 3;
+		uint32_t cam_ufc : 2;
+		uint32_t cam_vcm : 2;
+		uint32_t TS_Source : 4;
+		uint32_t AUDIO_CODEC_SOURCE : 3;
+		uint32_t usb_mux : 2;
 		uint32_t reserved_2 : 10;
 	};
 	uint32_t raw_value;
diff --git a/board/magolor/ec.tasklist b/board/magolor/ec.tasklist
index 0aba1fabeb..ba5855412d 100644
--- a/board/magolor/ec.tasklist
+++ b/board/magolor/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/magolor/gpio.inc b/board/magolor/gpio.inc
index 00a6b4effc..77cf523de1 100644
--- a/board/magolor/gpio.inc
+++ b/board/magolor/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/magolor/led.c b/board/magolor/led.c
index 5206244073..891bc4cecb 100644
--- a/board/magolor/led.c
+++ b/board/magolor/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,23 +19,28 @@ __override const int led_charge_lvl_1 = 5;
 __override const int led_charge_lvl_2 = 95;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
diff --git a/board/magolor/usb_pd_policy.c b/board/magolor/usb_pd_policy.c
index 02bb449f60..2bad4d6931 100644
--- a/board/magolor/usb_pd_policy.c
+++ b/board/magolor/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,8 @@
 #include "driver/tcpm/tcpci.h"
 #include "usb_pd.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
diff --git a/board/makomo/battery.c b/board/makomo/battery.c
index 1b162e93c7..1f5be3dbe3 100644
--- a/board/makomo/battery.c
+++ b/board/makomo/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/makomo/board.c b/board/makomo/board.c
index e50f84f3fb..24b34d9a75 100644
--- a/board/makomo/board.c
+++ b/board/makomo/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -31,6 +31,7 @@
 #include "keyboard_scan.h"
 #include "keyboard_backlight.h"
 #include "lid_switch.h"
+#include "panic.h"
 #include "power.h"
 #include "power_button.h"
 #include "registers.h"
@@ -45,8 +46,8 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
@@ -58,40 +59,34 @@ static void tcpc_alert_event(enum gpio_signal signal)
 /******************************************************************************/
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] =  {"BOARD_ID",  3300, 4096, 0, STM32_AIN(10)},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)},
+	[ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(10) },
+	[ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /******************************************************************************/
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "typec",
-		.port = 0,
-		.kbps = 400,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	},
-	{
-		.name = "other",
-		.port = 1,
-		.kbps = 400,
-		.scl  = GPIO_I2C2_SCL,
-		.sda  = GPIO_I2C2_SDA
-	},
+	{ .name = "typec",
+	  .port = 0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "other",
+	  .port = 1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
 const struct i2c_port_t i2c_bitbang_ports[] = {
-	{
-		.name = "battery",
-		.port = 2,
-		.kbps = 100,
-		.scl  = GPIO_I2C3_SCL,
-		.sda  = GPIO_I2C3_SDA,
-		.drv = &bitbang_drv
-	},
+	{ .name = "battery",
+	  .port = 2,
+	  .kbps = 100,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA,
+	  .drv = &bitbang_drv },
 };
 const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
 
@@ -99,8 +94,8 @@ const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
 
 /* power signal list.  Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
+	{ GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" },
+	{ GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" },
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
@@ -156,8 +151,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-static void board_hpd_status(const struct usb_mux *me,
-			     mux_state_t mux_state,
+static void board_hpd_status(const struct usb_mux *me, mux_state_t mux_state,
 			     bool *ack_required)
 {
 	/* This driver does not use host command ACKs */
@@ -170,13 +164,16 @@ static void board_hpd_status(const struct usb_mux *me,
 	host_set_single_event(EC_HOST_EVENT_USB_MUX);
 }
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+				.hpd_update = &board_hpd_status,
+			},
 	},
 };
 
@@ -238,12 +235,12 @@ int board_set_active_charge_port(int charge_port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-			       CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 int board_discharge_on_ac(int enable)
@@ -300,8 +297,7 @@ static void board_spi_enable(void)
 	/* Pin mux spi peripheral toward the sensor. */
 	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
 }
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP,
-	     board_spi_enable,
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_spi_enable,
 	     MOTION_SENSE_HOOK_PRIO - 1);
 
 static void board_spi_disable(void)
@@ -315,8 +311,7 @@ static void board_spi_disable(void)
 	spi_enable(&spi_devices[0], 0);
 	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
 }
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN,
-	     board_spi_disable,
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_spi_disable,
 	     MOTION_SENSE_HOOK_PRIO + 1);
 #endif /* !VARIANT_KUKUI_NO_SENSORS */
 
@@ -355,17 +350,13 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Rotation matrixes */
-static const mat33_fp_t base_standard_ref = {
-	{0, FLOAT_TO_FP(1), 0},
-	{FLOAT_TO_FP(-1), 0, 0},
-	{0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					      { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
 
-static const mat33_fp_t lid_standard_ref = {
-	{FLOAT_TO_FP(-1), 0, 0},
-	{0, FLOAT_TO_FP(1), 0},
-	{0, 0, FLOAT_TO_FP(-1) }
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, FLOAT_TO_FP(1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
 /* sensor private data */
 /* Lid accel private data */
@@ -453,7 +444,7 @@ struct motion_sensor_t motion_sensors[] = {
 const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
 const struct it8801_pwm_t it8801_pwm_channels[] = {
-	[IT8801_PWM_CH_KBLIGHT] = {.index = 4},
+	[IT8801_PWM_CH_KBLIGHT] = { .index = 4 },
 };
 
 void board_kblight_init(void)
@@ -469,11 +460,11 @@ bool board_has_kb_backlight(void)
 #endif /* !VARIANT_KUKUI_NO_SENSORS */
 
 /* Battery functions */
-#define SB_SMARTCHARGE				0x26
+#define SB_SMARTCHARGE 0x26
 /* Quick charge enable bit */
-#define SMART_QUICK_CHARGE			0x02
+#define SMART_QUICK_CHARGE 0x02
 /* Quick charge support bit */
-#define MODE_QUICK_CHARGE_SUPPORT		0x01
+#define MODE_QUICK_CHARGE_SUPPORT 0x01
 
 static void sb_quick_charge_mode(int enable)
 {
@@ -544,8 +535,8 @@ int board_get_battery_i2c(void)
 }
 
 #ifdef SECTION_IS_RW
-static int it8801_get_target_channel(enum pwm_channel *channel,
-				     int type, int index)
+static int it8801_get_target_channel(enum pwm_channel *channel, int type,
+				     int index)
 {
 	switch (type) {
 	case EC_PWM_TYPE_GENERIC:
@@ -568,14 +559,13 @@ host_command_pwm_set_duty(struct host_cmd_handler_args *args)
 	if (it8801_get_target_channel(&channel, p->pwm_type, p->index))
 		return EC_RES_INVALID_PARAM;
 
-	duty = (uint32_t) p->duty * 255 / 65535;
+	duty = (uint32_t)p->duty * 255 / 65535;
 	it8801_pwm_set_raw_duty(channel, duty);
 	it8801_pwm_enable(channel, p->duty > 0);
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_DUTY,
-		     host_command_pwm_set_duty,
+DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_DUTY, host_command_pwm_set_duty,
 		     EC_VER_MASK(0));
 
 static enum ec_status
@@ -589,12 +579,11 @@ host_command_pwm_get_duty(struct host_cmd_handler_args *args)
 	if (it8801_get_target_channel(&channel, p->pwm_type, p->index))
 		return EC_RES_INVALID_PARAM;
 
-	r->duty = (uint32_t) it8801_pwm_get_raw_duty(channel) * 65535 / 255;
+	r->duty = (uint32_t)it8801_pwm_get_raw_duty(channel) * 65535 / 255;
 	args->response_size = sizeof(*r);
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_DUTY,
-		     host_command_pwm_get_duty,
+DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_DUTY, host_command_pwm_get_duty,
 		     EC_VER_MASK(0));
 #endif
diff --git a/board/makomo/board.h b/board/makomo/board.h
index 9919557553..bf705e9560 100644
--- a/board/makomo/board.h
+++ b/board/makomo/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -53,14 +53,13 @@
 
 /* Motion Sensors */
 #ifndef VARIANT_KUKUI_NO_SENSORS
-#define CONFIG_ACCEL_LIS2DWL    /* Lid accel */
+#define CONFIG_ACCEL_LIS2DWL /* Lid accel */
 #define CONFIG_ACCELGYRO_BMI160 /* Base accel */
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 #define CONFIG_ALS
 #define CONFIG_CMD_ACCEL_INFO
 
-
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_UPDATE
 #define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
@@ -76,20 +75,20 @@
 #endif /* VARIANT_KUKUI_NO_SENSORS */
 
 /* I2C ports */
-#define I2C_PORT_BC12               0
-#define I2C_PORT_TCPC0              0
-#define I2C_PORT_USB_MUX            0
-#define I2C_PORT_CHARGER            board_get_charger_i2c()
-#define I2C_PORT_SENSORS            1
-#define I2C_PORT_KB_DISCRETE        1
-#define I2C_PORT_VIRTUAL_BATTERY    I2C_PORT_BATTERY
-#define I2C_PORT_BATTERY            2
+#define I2C_PORT_BC12 0
+#define I2C_PORT_TCPC0 0
+#define I2C_PORT_USB_MUX 0
+#define I2C_PORT_CHARGER board_get_charger_i2c()
+#define I2C_PORT_SENSORS 1
+#define I2C_PORT_KB_DISCRETE 1
+#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
+#define I2C_PORT_BATTERY 2
 
 /* IT8801 I2C address */
-#define KB_DISCRETE_I2C_ADDR_FLAGS  IT8801_I2C_ADDR1
+#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1
 
 /* Enable Accel over SPI */
-#define CONFIG_SPI_ACCEL_PORT    0  /* The first SPI controller port (SPI2) */
+#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */
 
 #define CONFIG_KEYBOARD_PROTOCOL_MKBP
 #define CONFIG_MKBP_EVENT
diff --git a/board/makomo/build.mk b/board/makomo/build.mk
index 04b88d3d79..5b31bc2d67 100644
--- a/board/makomo/build.mk
+++ b/board/makomo/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/makomo/ec.tasklist b/board/makomo/ec.tasklist
index e943459024..23b568cb28 100644
--- a/board/makomo/ec.tasklist
+++ b/board/makomo/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/makomo/gpio.inc b/board/makomo/gpio.inc
index 287ebbda1f..8cbdef529e 100644
--- a/board/makomo/gpio.inc
+++ b/board/makomo/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/makomo/led.c b/board/makomo/led.c
index 140c31babe..0870806eff 100644
--- a/board/makomo/led.c
+++ b/board/makomo/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -18,33 +18,38 @@ __override const int led_charge_lvl_1 = 5;
 __override const int led_charge_lvl_2 = 97;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED,    LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER,  LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
 
 __override const struct led_descriptor
-led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    1 * LED_ONE_SEC },
+						  { LED_OFF,
+						    3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 __override void led_set_color_battery(enum ec_led_colors color)
diff --git a/board/marzipan/battery.c b/board/marzipan/battery.c
index 3a9a1cbaf1..fa3a4ec189 100644
--- a/board/marzipan/battery.c
+++ b/board/marzipan/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/marzipan/board.c b/board/marzipan/board.c
index e5e12a1afc..125c39a826 100644
--- a/board/marzipan/board.c
+++ b/board/marzipan/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -39,8 +39,8 @@
 #include "usbc_ocp.h"
 #include "usbc_ppc.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 #include "gpio_list.h"
 
@@ -91,10 +91,8 @@ __override struct keyboard_scan_config keyscan_config = {
 	 * Unmask 0x08 in [0] (KSO_00/KSI_03, the new location of Search key);
 	 * as it still uses the legacy location (KSO_01/KSI_00).
 	 */
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca
-	},
+	.actual_key_mask = { 0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, 0xa4,
+			     0xff, 0xfe, 0x55, 0xfa, 0xca },
 	/* Other values should be the same as the default configuration. */
 	.debounce_down_us = 9 * MSEC,
 	.debounce_up_us = 30 * MSEC,
@@ -105,41 +103,31 @@ __override struct keyboard_scan_config keyscan_config = {
 
 /* I2C port map */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl  = GPIO_EC_I2C_POWER_SCL,
-		.sda  = GPIO_EC_I2C_POWER_SDA
-	},
-	{
-		.name = "tcpc0",
-		.port = I2C_PORT_TCPC0,
-		.kbps = 1000,
-		.scl  = GPIO_EC_I2C_USB_C0_PD_SCL,
-		.sda  = GPIO_EC_I2C_USB_C0_PD_SDA
-	},
-	{
-		.name = "tcpc1",
-		.port = I2C_PORT_TCPC1,
-		.kbps = 1000,
-		.scl  = GPIO_EC_I2C_USB_C1_PD_SCL,
-		.sda  = GPIO_EC_I2C_USB_C1_PD_SDA
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_EEPROM_SCL,
-		.sda  = GPIO_EC_I2C_EEPROM_SDA
-	},
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_SENSOR_SCL,
-		.sda  = GPIO_EC_I2C_SENSOR_SDA
-	},
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_POWER_SCL,
+	  .sda = GPIO_EC_I2C_POWER_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C0_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C0_PD_SDA },
+	{ .name = "tcpc1",
+	  .port = I2C_PORT_TCPC1,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C1_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C1_PD_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_EEPROM_SCL,
+	  .sda = GPIO_EC_I2C_EEPROM_SDA },
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_SENSOR_SCL,
+	  .sda = GPIO_EC_I2C_SENSOR_SDA },
 };
 
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
@@ -147,37 +135,22 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* Measure VBUS through a 1/10 voltage divider */
-	[ADC_VBUS] = {
-		"VBUS",
-		NPCX_ADC_CH1,
-		ADC_MAX_VOLT * 10,
-		ADC_READ_MAX + 1,
-		0
-	},
+	[ADC_VBUS] = { "VBUS", NPCX_ADC_CH1, ADC_MAX_VOLT * 10,
+		       ADC_READ_MAX + 1, 0 },
 	/*
 	 * Adapter current output or battery charging/discharging current (uV)
 	 * 18x amplification on charger side.
 	 */
-	[ADC_AMON_BMON] = {
-		"AMON_BMON",
-		NPCX_ADC_CH2,
-		ADC_MAX_VOLT * 1000 / 18,
-		ADC_READ_MAX + 1,
-		0
-	},
+	[ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH2, ADC_MAX_VOLT * 1000 / 18,
+			    ADC_READ_MAX + 1, 0 },
 	/*
 	 * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read
 	 * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and
 	 * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we
 	 * only divide by 2 (enough to avoid precision issues).
 	 */
-	[ADC_PSYS] = {
-		"PSYS",
-		NPCX_ADC_CH3,
-		ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1),
-		2,
-		0
-	},
+	[ADC_PSYS] = { "PSYS", NPCX_ADC_CH3,
+		       ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), 2, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
@@ -190,16 +163,12 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
 /* Power Path Controller */
 struct ppc_config_t ppc_chips[] = {
-	{
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	{
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
+	{ .i2c_port = I2C_PORT_TCPC0,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
+	{ .i2c_port = I2C_PORT_TCPC1,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
 };
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
@@ -230,16 +199,22 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
  * to AP. But the TCPC chip is also needed to know the HPD status; otherwise,
  * the mux misbehaves.
  */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	},
 	{
-		.usb_port = 1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	}
 };
 
@@ -271,29 +246,21 @@ enum base_accelgyro_type {
 };
 
 /* Matrix to rotate accelerometer into standard reference frame */
-const mat33_fp_t base_standard_ref_bmi160 = {
-	{ FLOAT_TO_FP(1), 0,  0},
-	{ 0,  FLOAT_TO_FP(-1),  0},
-	{ 0,  0, FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t base_standard_ref_bmi160 = { { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, FLOAT_TO_FP(-1), 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
 
-const mat33_fp_t base_standard_ref_icm426xx = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0,  0, FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t base_standard_ref_icm426xx = { { 0, FLOAT_TO_FP(1), 0 },
+						{ FLOAT_TO_FP(1), 0, 0 },
+						{ 0, 0, FLOAT_TO_FP(-1) } };
 
-static const mat33_fp_t lid_standard_ref_bma255 = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lid_standard_ref_bma255 = { { FLOAT_TO_FP(-1), 0, 0 },
+						    { 0, FLOAT_TO_FP(-1), 0 },
+						    { 0, 0, FLOAT_TO_FP(1) } };
 
-static const mat33_fp_t lid_standard_ref_kx022 = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lid_standard_ref_kx022 = { { FLOAT_TO_FP(-1), 0, 0 },
+						   { 0, FLOAT_TO_FP(-1), 0 },
+						   { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
@@ -465,7 +432,7 @@ static void board_detect_motionsensor(void)
 
 	/* Check lid accel chip */
 	ret = i2c_read8(I2C_PORT_SENSOR, BMA2x2_I2C_ADDR1_FLAGS,
-		BMA2x2_CHIP_ID_ADDR, &val);
+			BMA2x2_CHIP_ID_ADDR, &val);
 	if (ret)
 		motion_sensors[LID_ACCEL] = kx022_lid_accel;
 
@@ -478,10 +445,11 @@ static void board_detect_motionsensor(void)
 		motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
 	}
 
-	base_accelgyro_config = (val == ICM426XX_CHIP_ICM40608)
-		 ? BASE_GYRO_ICM426XX : BASE_GYRO_BMI160;
-	CPRINTS("Base Accelgyro: %s", (val == ICM426XX_CHIP_ICM40608)
-		 ? "ICM40608" : "BMI160");
+	base_accelgyro_config = (val == ICM426XX_CHIP_ICM40608) ?
+					BASE_GYRO_ICM426XX :
+					BASE_GYRO_BMI160;
+	CPRINTS("Base Accelgyro: %s",
+		(val == ICM426XX_CHIP_ICM40608) ? "ICM40608" : "BMI160");
 }
 
 /* Initialize board. */
@@ -539,9 +507,9 @@ void board_tcpc_init(void)
 	 */
 	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
 		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
 
 /* Called on AP S0 -> S3 transition */
 static void board_chipset_suspend(void)
@@ -606,8 +574,7 @@ void board_overcurrent_event(int port, int is_overcurrented)
 
 int board_set_active_charge_port(int port)
 {
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	int i;
 
 	if (!is_real_port && port != CHARGE_PORT_NONE)
@@ -635,7 +602,6 @@ int board_set_active_charge_port(int port)
 		return EC_ERROR_INVAL;
 	}
 
-
 	CPRINTS("New charge port: p%d", port);
 
 	/*
@@ -659,23 +625,21 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	/*
 	 * Ignore lower charge ceiling on PD transition if our battery is
 	 * critical, as we may brownout.
 	 */
-	if (supplier == CHARGE_SUPPLIER_PD &&
-	    charge_ma < 1500 &&
+	if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 &&
 	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
 		CPRINTS("Using max ilim %d", max_ma);
 		charge_ma = max_ma;
 	}
 
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 uint16_t tcpc_get_alert_status(void)
diff --git a/board/marzipan/board.h b/board/marzipan/board.h
index 28dc5d273a..c651e55965 100644
--- a/board/marzipan/board.h
+++ b/board/marzipan/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,7 +11,7 @@
 #include "baseboard.h"
 
 /* Internal SPI flash on NPCX7 */
-#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)  /* 512KB internal spi flash */
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */
 
 /* Keyboard */
 #define CONFIG_KEYBOARD_PROTOCOL_MKBP
@@ -19,7 +19,7 @@
 #define CONFIG_PWM_KBLIGHT
 
 /* Battery */
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY  "LION"
+#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
 #define CONFIG_BATTERY_REVIVE_DISCONNECT
 #define CONFIG_BATTERY_FUEL_GAUGE
 
@@ -71,12 +71,7 @@
 #include "gpio_signal.h"
 #include "registers.h"
 
-enum adc_channel {
-	ADC_VBUS,
-	ADC_AMON_BMON,
-	ADC_PSYS,
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_VBUS, ADC_AMON_BMON, ADC_PSYS, ADC_CH_COUNT };
 
 /* Motion sensors */
 enum sensor_id {
@@ -86,11 +81,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_DISPLIGHT,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_DISPLIGHT, PWM_CH_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
diff --git a/board/marzipan/build.mk b/board/marzipan/build.mk
index 09853a26d7..048f0787f7 100644
--- a/board/marzipan/build.mk
+++ b/board/marzipan/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/marzipan/ec.tasklist b/board/marzipan/ec.tasklist
index 5beeb38feb..228828af3c 100644
--- a/board/marzipan/ec.tasklist
+++ b/board/marzipan/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/marzipan/gpio.inc b/board/marzipan/gpio.inc
index 11fa6b5a53..633f689c66 100644
--- a/board/marzipan/gpio.inc
+++ b/board/marzipan/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/marzipan/led.c b/board/marzipan/led.c
index e4b34576c8..0a6d8df959 100644
--- a/board/marzipan/led.c
+++ b/board/marzipan/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -32,15 +32,15 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_BLUE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static void led_set_color(enum led_color color)
 {
 	gpio_set_level(GPIO_EC_CHG_LED_Y_C1,
-		(color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
+		       (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
 	gpio_set_level(GPIO_EC_CHG_LED_B_C1,
-		(color == LED_BLUE) ? BAT_LED_ON : BAT_LED_OFF);
+		       (color == LED_BLUE) ? BAT_LED_ON : BAT_LED_OFF);
 }
 
 void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
@@ -66,7 +66,6 @@ static void board_led_set_battery(void)
 	static int battery_ticks;
 	int color = LED_OFF;
 	int period = 0;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
@@ -106,16 +105,16 @@ static void board_led_set_battery(void)
 		color = LED_BLUE;
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE) {
-			/* Factory mode: Blue 2 sec, Amber 2 sec */
-			period = (2 + 2) * LED_ONE_SEC;
-			battery_ticks = battery_ticks % period;
-			if (battery_ticks < 2 * LED_ONE_SEC)
-				color = LED_BLUE;
-			else
-				color = LED_AMBER;
-		} else
+		color = LED_BLUE;
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		/* Factory mode: Blue 2 sec, Amber 2 sec */
+		period = (2 + 2) * LED_ONE_SEC;
+		battery_ticks = battery_ticks % period;
+		if (battery_ticks < 2 * LED_ONE_SEC)
 			color = LED_BLUE;
+		else
+			color = LED_AMBER;
 		break;
 	default:
 		/* Other states don't alter LED behavior */
diff --git a/board/marzipan/switchcap.c b/board/marzipan/switchcap.c
index 26009d55d8..853f677f27 100644
--- a/board/marzipan/switchcap.c
+++ b/board/marzipan/switchcap.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,8 +12,8 @@
 #include "power/qcom.h"
 #include "system.h"
 
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args)
 
 void board_set_switchcap_power(int enable)
 {
diff --git a/board/marzipan/usbc_config.c b/board/marzipan/usbc_config.c
index e8fc9e76a3..5b41e22d33 100644
--- a/board/marzipan/usbc_config.c
+++ b/board/marzipan/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,8 @@
 #include "usb_pd.h"
 #include "usbc_config.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 const struct charger_config_t chg_chips[] = {
 	{
diff --git a/board/marzipan/usbc_config.h b/board/marzipan/usbc_config.h
index 7f72b01700..56cdb155ea 100644
--- a/board/marzipan/usbc_config.h
+++ b/board/marzipan/usbc_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/max32660-eval/board.c b/board/max32660-eval/board.c
index 15a856ab4e..91e78287f3 100644
--- a/board/max32660-eval/board.c
+++ b/board/max32660-eval/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/max32660-eval/board.h b/board/max32660-eval/board.h
index bcca57f18a..9061b0b958 100644
--- a/board/max32660-eval/board.h
+++ b/board/max32660-eval/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/max32660-eval/build.mk b/board/max32660-eval/build.mk
index a613922cd2..3e50dd9a00 100644
--- a/board/max32660-eval/build.mk
+++ b/board/max32660-eval/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/max32660-eval/ec.tasklist b/board/max32660-eval/ec.tasklist
index 5e58b9dea8..c92b25295b 100644
--- a/board/max32660-eval/ec.tasklist
+++ b/board/max32660-eval/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/max32660-eval/gpio.inc b/board/max32660-eval/gpio.inc
index 3ced37a77f..e7397e11a4 100644
--- a/board/max32660-eval/gpio.inc
+++ b/board/max32660-eval/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/mchpevb1/battery.c b/board/mchpevb1/battery.c
index fcc09994bf..d8f7496fa0 100644
--- a/board/mchpevb1/battery.c
+++ b/board/mchpevb1/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -14,15 +14,15 @@
 #include "util.h"
 
 /* Shutdown mode parameter to write to manufacturer access register */
-#define PARAM_CUT_OFF_LOW  0x10
+#define PARAM_CUT_OFF_LOW 0x10
 #define PARAM_CUT_OFF_HIGH 0x00
 
 /* Battery info for BQ40Z55 */
 static const struct battery_info info = {
-	.voltage_max = 8700,        /* mV */
+	.voltage_max = 8700, /* mV */
 	.voltage_normal = 7600,
 	.voltage_min = 6000,
-	.precharge_current = 256,   /* mA */
+	.precharge_current = 256, /* mA */
 	.start_charging_min_c = 0,
 	.start_charging_max_c = 46,
 	.charging_min_c = 0,
@@ -47,10 +47,10 @@ int board_cut_off_battery(void)
 	buf[2] = PARAM_CUT_OFF_HIGH;
 
 	i2c_lock(I2C_PORT_BATTERY, 1);
-	rv = i2c_xfer_unlocked(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS,
-			       buf, 3, NULL, 0, I2C_XFER_SINGLE);
-	rv |= i2c_xfer_unlocked(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS,
-				buf, 3, NULL, 0, I2C_XFER_SINGLE);
+	rv = i2c_xfer_unlocked(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS, buf, 3,
+			       NULL, 0, I2C_XFER_SINGLE);
+	rv |= i2c_xfer_unlocked(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS, buf, 3,
+				NULL, 0, I2C_XFER_SINGLE);
 	i2c_lock(I2C_PORT_BATTERY, 0);
 
 	return rv;
@@ -214,7 +214,7 @@ enum ec_status charger_profile_override_set_param(uint32_t param,
 	return EC_RES_INVALID_PARAM;
 }
 
-static int command_fastcharge(int argc, char **argv)
+static int command_fastcharge(int argc, const char **argv)
 {
 	if (argc > 1 && !parse_bool(argv[1], &fast_charging_allowed))
 		return EC_ERROR_PARAM1;
@@ -223,8 +223,7 @@ static int command_fastcharge(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(fastcharge, command_fastcharge,
-			"[on|off]",
+DECLARE_CONSOLE_COMMAND(fastcharge, command_fastcharge, "[on|off]",
 			"Get or set fast charging profile");
 
-#endif	/* CONFIG_CHARGER_PROFILE_OVERRIDE */
+#endif /* CONFIG_CHARGER_PROFILE_OVERRIDE */
diff --git a/board/mchpevb1/board.c b/board/mchpevb1/board.c
index 2991b59299..23135108f6 100644
--- a/board/mchpevb1/board.c
+++ b/board/mchpevb1/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -58,26 +58,25 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* NOTE: MEC17xx EVB + SKL RVP3 does not use BD99992 PMIC.
  * RVP3 PMIC controlled by RVP3 logic.
  */
-#define I2C_ADDR_BD99992_FLAGS	0x30
+#define I2C_ADDR_BD99992_FLAGS 0x30
 
 /*
  * Maxim DS1624 I2C temperature sensor used for testing I2C.
  * DS1624 contains one internal temperature sensor
  * and EEPROM. It has no external temperature inputs.
  */
-#define DS1624_I2C_ADDR_FLAGS	(0x48 | I2C_FLAG_BIG_ENDIAN)
-#define DS1624_IDX_LOCAL	0
-#define DS1624_READ_TEMP16	0xAA	/* read 16-bit temperature */
-#define DS1624_ACCESS_CFG	0xAC	/* read/write 8-bit config */
-#define DS1624_CMD_START	0xEE
-#define DS1624_CMD_STOP		0x22
+#define DS1624_I2C_ADDR_FLAGS (0x48 | I2C_FLAG_BIG_ENDIAN)
+#define DS1624_IDX_LOCAL 0
+#define DS1624_READ_TEMP16 0xAA /* read 16-bit temperature */
+#define DS1624_ACCESS_CFG 0xAC /* read/write 8-bit config */
+#define DS1624_CMD_START 0xEE
+#define DS1624_CMD_STOP 0x22
 
 /*
  * static global and routine to return smart battery
@@ -116,7 +115,6 @@ void board_config_pre_init(void)
 }
 #endif /* #ifdef CONFIG_BOARD_PRE_INIT */
 
-
 /*
  * Use EC to handle ALL_SYS_PWRGD signal.
  * MEC17xx connected to SKL/KBL RVP3 reference board
@@ -135,8 +133,8 @@ static void board_all_sys_pwrgd(void)
 
 	CPRINTS("ALL_SYS_PWRGD=%d SYS_RESET_L=%d", allsys_in, allsys_out);
 
-	trace2(0, BRD, 0, "ALL_SYS_PWRGD=%d SYS_RESET_L=%d",
-			allsys_in, allsys_out);
+	trace2(0, BRD, 0, "ALL_SYS_PWRGD=%d SYS_RESET_L=%d", allsys_in,
+	       allsys_out);
 
 	/*
 	 * Wait at least 10 ms between power signals going high
@@ -161,14 +159,12 @@ void all_sys_pwrgd_interrupt(enum gpio_signal signal)
 }
 #endif /* #ifdef CONFIG_BOARD_HAS_ALL_SYS_PWRGD */
 
-
 #ifdef HAS_TASK_PDCMD
 /* Exchange status with PD MCU. */
 static void pd_mcu_interrupt(enum gpio_signal signal)
 {
 	/* Exchange status with PD MCU to determine interrupt cause */
 	host_command_pd_send_status(0);
-
 }
 #endif
 
@@ -217,33 +213,29 @@ void tablet_mode_interrupt(enum gpio_signal signal)
  */
 const struct adc_t adc_channels[] = {
 	/* Vbus sensing. Converted to mV, full ADC is equivalent to 30V. */
-	[ADC_VBUS] = {"VBUS", 30000, 1024, 0, 1},
+	[ADC_VBUS] = { "VBUS", 30000, 1024, 0, 1 },
 	/* Adapter current output or battery discharging current */
-	[ADC_AMON_BMON] = {"AMON_BMON", 25000, 3072, 0, 3},
+	[ADC_AMON_BMON] = { "AMON_BMON", 25000, 3072, 0, 3 },
 	/* System current consumption */
-	[ADC_PSYS] = {"PSYS", 1, 1, 0, 4},
-	[ADC_CASE] = {"CASE", 1, 1, 0, 7},
+	[ADC_PSYS] = { "PSYS", 1, 1, 0, 4 },
+	[ADC_CASE] = { "CASE", 1, 1, 0, 7 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /*
  * MCHP EVB connected to KBL RVP3
  */
-const struct i2c_port_t i2c_ports[]  = {
-	{
-		.name = "sensors",
-		.port = MCHP_I2C_PORT4,
-		.kbps = 100,
-		.scl  = GPIO_SMB04_SCL,
-		.sda  = GPIO_SMB04_SDA
-	},
-	{
-		.name = "batt",
-		.port = MCHP_I2C_PORT5,
-		.kbps = 100,
-		.scl  = GPIO_SMB05_SCL,
-		.sda  = GPIO_SMB05_SDA
-	},
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "sensors",
+	  .port = MCHP_I2C_PORT4,
+	  .kbps = 100,
+	  .scl = GPIO_SMB04_SCL,
+	  .sda = GPIO_SMB04_SDA },
+	{ .name = "batt",
+	  .port = MCHP_I2C_PORT5,
+	  .kbps = 100,
+	  .scl = GPIO_SMB05_SCL,
+	  .sda = GPIO_SMB05_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -273,19 +265,15 @@ int board_i2c_p2c(int port)
 
 #ifdef CONFIG_USB_POWER_DELIVERY
 const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{I2C_PORT_TCPC,
-	 CONFIG_TCPC_I2C_BASE_ADDR_FLAGS,
-	 &tcpci_tcpm_drv},
+	{ I2C_PORT_TCPC, CONFIG_TCPC_I2C_BASE_ADDR_FLAGS, &tcpci_tcpm_drv },
 
-	{I2C_PORT_TCPC,
-	 CONFIG_TCPC_I2C_BASE_ADDR_FLAGS + 1,
-	 &tcpci_tcpm_drv},
+	{ I2C_PORT_TCPC, CONFIG_TCPC_I2C_BASE_ADDR_FLAGS + 1, &tcpci_tcpm_drv },
 };
 #endif
 
 /* SPI devices */
 const struct spi_device_t spi_devices[] = {
-	{ QMSPI0_PORT, 4, GPIO_QMSPI_CS0},
+	{ QMSPI0_PORT, 4, GPIO_QMSPI_CS0 },
 #if defined(CONFIG_SPI_ACCEL_PORT)
 	{ GPSPI0_PORT, 2, GPIO_SPI0_CS0 },
 #endif
@@ -299,7 +287,6 @@ const enum gpio_signal hibernate_wake_pins[] = {
 };
 const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 
-
 /*
  * Deep sleep support, called by chip level.
  */
@@ -362,18 +349,24 @@ struct pi3usb9281_config pi3usb9281_chips[] = {
 BUILD_ASSERT(ARRAY_SIZE(pi3usb9281_chips) ==
 	     CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT);
 
-struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
-		.driver = &pi3usb3x532_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX,
+				.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
+				.driver = &pi3usb3x532_usb_mux_driver,
+			},
 	},
 	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = 0x10,
-		.driver = &ps8740_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_USB_MUX,
+				.i2c_addr_flags = 0x10,
+				.driver = &ps8740_usb_mux_driver,
+			},
 	}
 };
 #endif
@@ -429,9 +422,9 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
  * a static global in this module.
  */
 const struct temp_sensor_t temp_sensors[] = {
-	{"Battery", TEMP_SENSOR_TYPE_BATTERY, sb_temp, 0},
-	{"Ambient", TEMP_SENSOR_TYPE_BOARD, ds1624_get_val, 0},
-	{"Case", TEMP_SENSOR_TYPE_CASE, therm_get_val, (int)ADC_CASE},
+	{ "Battery", TEMP_SENSOR_TYPE_BATTERY, sb_temp, 0 },
+	{ "Ambient", TEMP_SENSOR_TYPE_BOARD, ds1624_get_val, 0 },
+	{ "Case", TEMP_SENSOR_TYPE_CASE, therm_get_val, (int)ADC_CASE },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 #endif
@@ -440,16 +433,16 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 #ifdef CONFIG_ALS
 /* ALS instances. Must be in same order as enum als_id. */
 struct als_t als[] = {
-	{"TI", opt3001_init, opt3001_read_lux, 5},
+	{ "TI", opt3001_init, opt3001_read_lux, 5 },
 };
 BUILD_ASSERT(ARRAY_SIZE(als) == ALS_COUNT);
 #endif
 
 const struct button_config buttons[CONFIG_BUTTON_COUNT] = {
-	{"Volume Down", KEYBOARD_BUTTON_VOLUME_DOWN, GPIO_VOLUME_DOWN_L,
-	 30 * MSEC, 0},
-	{"Volume Up", KEYBOARD_BUTTON_VOLUME_UP, GPIO_VOLUME_UP_L,
-	 30 * MSEC, 0},
+	{ "Volume Down", KEYBOARD_BUTTON_VOLUME_DOWN, GPIO_VOLUME_DOWN_L,
+	  30 * MSEC, 0 },
+	{ "Volume Up", KEYBOARD_BUTTON_VOLUME_UP, GPIO_VOLUME_UP_L, 30 * MSEC,
+	  0 },
 };
 
 /* MCHP mec1701_evb connected to Intel SKL RVP3 with Kabylake
@@ -490,8 +483,7 @@ static void board_pmic_init(void)
 	cfg = 0x66;
 	rv = i2c_read8(I2C_PORT_THERMAL, DS1624_I2C_ADDR_FLAGS,
 		       DS1624_ACCESS_CFG, &cfg);
-	trace2(0, BRD, 0, "Read DS1624 Config rv = %d  cfg = 0x%02X",
-	       rv, cfg);
+	trace2(0, BRD, 0, "Read DS1624 Config rv = %d  cfg = 0x%02X", rv, cfg);
 
 	if ((rv == EC_SUCCESS) && (cfg & (1u << 0))) {
 		/* one-shot mode switch to continuous */
@@ -536,16 +528,13 @@ static void board_init(void)
 	/* Provide AC status to the PCH */
 	gpio_set_level(GPIO_PCH_ACOK, extpower_is_present());
 
-	if (system_jumped_late() &&
-	    chipset_in_state(CHIPSET_STATE_ON)) {
+	if (system_jumped_late() && chipset_in_state(CHIPSET_STATE_ON)) {
 		trace0(0, BRD, 0, "board_init: S0 call board_spi_enable");
 		board_spi_enable();
 	}
-
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
-
 /**
  * Buffer the AC present GPIO to the PCH.
  */
@@ -577,8 +566,7 @@ int board_set_active_charge_port(int charge_port)
 
 	if (is_real_port && source) {
 		CPRINTS("MEC1701 Skip enable p%d", charge_port);
-		trace1(0, BOARD, 0, "Skip enable charge port %d",
-			charge_port);
+		trace1(0, BOARD, 0, "Skip enable charge port %d", charge_port);
 		return EC_ERROR_INVAL;
 	}
 
@@ -592,10 +580,12 @@ int board_set_active_charge_port(int charge_port)
 	} else {
 		/* Make sure non-charging port is disabled */
 		gpio_set_level(charge_port ? GPIO_USB_C0_CHARGE_EN_L :
-					     GPIO_USB_C1_CHARGE_EN_L, 1);
+					     GPIO_USB_C1_CHARGE_EN_L,
+			       1);
 		/* Enable charging port */
 		gpio_set_level(charge_port ? GPIO_USB_C1_CHARGE_EN_L :
-					     GPIO_USB_C0_CHARGE_EN_L, 0);
+					     GPIO_USB_C0_CHARGE_EN_L,
+			       0);
 	}
 
 	return EC_SUCCESS;
@@ -609,23 +599,12 @@ int board_set_active_charge_port(int charge_port)
  * @param charge_ma     Desired charge limit (mA).
  * @param charge_mv     Negotiated charge voltage (mV).
  */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_set_input_current_limit(MAX(charge_ma,
-				   CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
-}
-#else
-/*
- * TODO HACK providing functions from common/charge_state_v2.c
- * which is not compiled in when no charger
- */
-int charge_prevent_power_on(int power_button_pressed)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
-	return 0;
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
-
-
 #endif
 
 /*
@@ -657,23 +636,18 @@ static void board_chipset_startup(void)
 	gpio_set_level(GPIO_USB2_ENABLE, 1);
 	hook_call_deferred(&enable_input_devices_data, 0);
 }
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP,
-		board_chipset_startup,
-		HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
 
 /* Called on AP S3 -> S5 transition */
 static void board_chipset_shutdown(void)
 {
 	CPRINTS("MEC1701 HOOK_CHIPSET_SHUTDOWN board_chipset_shutdown");
-	trace0(0, HOOK, 0,
-	       "HOOK_CHIPSET_SHUTDOWN board_chipset_shutdown");
+	trace0(0, HOOK, 0, "HOOK_CHIPSET_SHUTDOWN board_chipset_shutdown");
 	gpio_set_level(GPIO_USB1_ENABLE, 0);
 	gpio_set_level(GPIO_USB2_ENABLE, 0);
 	hook_call_deferred(&enable_input_devices_data, 0);
 }
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN,
-		board_chipset_shutdown,
-		HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
 
 /* Called on AP S3 -> S0 transition */
 static void board_chipset_resume(void)
@@ -685,10 +659,9 @@ static void board_chipset_resume(void)
 	gpio_set_level(GPIO_PP1800_DX_AUDIO_EN, 1);
 	gpio_set_level(GPIO_PP1800_DX_SENSOR_EN, 1);
 #endif
-
 }
 DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume,
-	     MOTION_SENSE_HOOK_PRIO-1);
+	     MOTION_SENSE_HOOK_PRIO - 1);
 
 /* Called on AP S0 -> S3 transition */
 static void board_chipset_suspend(void)
@@ -701,9 +674,7 @@ static void board_chipset_suspend(void)
 	gpio_set_level(GPIO_PP1800_DX_SENSOR_EN, 0);
 #endif
 }
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND,
-		board_chipset_suspend,
-		HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
 
 void board_hibernate_late(void)
 {
@@ -780,7 +751,6 @@ static void board_handle_reboot(void)
 }
 DECLARE_HOOK(HOOK_INIT, board_handle_reboot, HOOK_PRIO_FIRST);
 
-
 static int sb_temp(int idx, int *temp_ptr)
 {
 	if (idx != 0)
@@ -817,8 +787,8 @@ static void sb_update(void)
 	rv = sb_read(SB_TEMPERATURE, &smart_batt_temp);
 	smart_batt_temp = smart_batt_temp / 10;
 
-	trace12(0, BRD, 0, "sb_read temperature rv=%d  temp=%d K",
-		rv, smart_batt_temp);
+	trace12(0, BRD, 0, "sb_read temperature rv=%d  temp=%d K", rv,
+		smart_batt_temp);
 }
 
 /*
diff --git a/board/mchpevb1/board.h b/board/mchpevb1/board.h
index e16d0bb10f..10208ca736 100644
--- a/board/mchpevb1/board.h
+++ b/board/mchpevb1/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -88,7 +88,6 @@
  * #define EVB_NO_ESPI_TEST_MODE
  */
 
-
 /*
  * DEBUG
  * Disable ARM Cortex-M4 write buffer so
@@ -104,7 +103,7 @@
  * Values in MHz are 20, 25, 33, 50, and 66
  */
 /* KBL + EVB fly-wire hook up only supports 20MHz */
-#define CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ	MCHP_ESPI_CAP1_MAX_FREQ_20M
+#define CONFIG_HOST_INTERFACE_ESPI_EC_MAX_FREQ MCHP_ESPI_CAP1_MAX_FREQ_20M
 
 /*
  * EC eSPI advertises IO lanes
@@ -114,7 +113,7 @@
  * 3 = Single, Dual, and Quad
  */
 /* KBL + EVB fly-wire hook up only support Single mode */
-#define CONFIG_HOSTCMD_ESPI_EC_MODE	MCHP_ESPI_CAP1_SINGLE_MODE
+#define CONFIG_HOST_INTERFACE_ESPI_EC_MODE MCHP_ESPI_CAP1_SINGLE_MODE
 
 /*
  * Bit map of eSPI channels EC advertises
@@ -123,7 +122,7 @@
  * bit[2] = 1 OOB channel
  * bit[3] = 1 Flash channel
  */
-#define CONFIG_HOSTCMD_ESPI_EC_CHAN_BITMAP	MCHP_ESPI_CAP0_ALL_CHAN_SUPP
+#define CONFIG_HOST_INTERFACE_ESPI_EC_CHAN_BITMAP MCHP_ESPI_CAP0_ALL_CHAN_SUPP
 
 #define CONFIG_MCHP_ESPI_VW_SAVE_ON_SLEEP
 
@@ -146,7 +145,6 @@
 /* #define CONFIG_CHARGE_MANAGER */
 /* #define CONFIG_CHARGE_RAMP_SW */
 
-
 /* #define CONFIG_CHARGER */
 
 /* #define CONFIG_CHARGER_DISCHARGE_ON_AC */
@@ -164,8 +162,8 @@
 #define CONFIG_CHIPSET_RESET_HOOK
 
 #define CONFIG_HOST_INTERFACE_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 #define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD
 
 #define CONFIG_CLOCK_CRYSTAL
@@ -190,7 +188,6 @@
  * #define CONFIG_LOW_POWER_IDLE
  */
 
-
 /* #define CONFIG_GPIO_POWER_DOWN */
 
 /*
@@ -270,8 +267,8 @@
  * Configure for smaller flash is OK for testing except
  * for SPI flash lock bit.
  */
- #define CONFIG_FLASH_SIZE_BYTES 524288
- #define CONFIG_SPI_FLASH_W25X40
+#define CONFIG_FLASH_SIZE_BYTES 524288
+#define CONFIG_SPI_FLASH_W25X40
 /*
  * #define CONFIG_FLASH_SIZE_BYTES 0x1000000
  * #define CONFIG_SPI_FLASH_W25Q128
@@ -321,7 +318,7 @@
  * Make sure to not include GPSPI in little-firmware(LFW)
  */
 #ifndef LFW
-#define CONFIG_MCHP_GPSPI	0x01
+#define CONFIG_MCHP_GPSPI 0x01
 #endif
 
 /* SPI Accelerometer
@@ -360,9 +357,8 @@
 #define GPIO_BAT_LED_GREEN GPIO_CHARGE_LED_2
 
 /* I2C ports */
-#define I2C_CONTROLLER_COUNT	2
-#define I2C_PORT_COUNT		2
-
+#define I2C_CONTROLLER_COUNT 2
+#define I2C_PORT_COUNT 2
 
 /*
  * Map I2C Ports to Controllers for this board.
@@ -377,26 +373,26 @@
  * All other ports set to 0xff (not used)
  */
 
-#define I2C_PORT_PMIC           MCHP_I2C_PORT10
-#define I2C_PORT_USB_CHARGER_1	MCHP_I2C_PORT2
-#define I2C_PORT_USB_MUX        MCHP_I2C_PORT2
-#define I2C_PORT_USB_CHARGER_2	MCHP_I2C_PORT2
-#define I2C_PORT_PD_MCU         MCHP_I2C_PORT3
-#define I2C_PORT_TCPC           MCHP_I2C_PORT3
-#define I2C_PORT_ALS            MCHP_I2C_PORT4
-#define I2C_PORT_ACCEL          MCHP_I2C_PORT4
-#define I2C_PORT_BATTERY        MCHP_I2C_PORT5
-#define I2C_PORT_CHARGER        MCHP_I2C_PORT5
+#define I2C_PORT_PMIC MCHP_I2C_PORT10
+#define I2C_PORT_USB_CHARGER_1 MCHP_I2C_PORT2
+#define I2C_PORT_USB_MUX MCHP_I2C_PORT2
+#define I2C_PORT_USB_CHARGER_2 MCHP_I2C_PORT2
+#define I2C_PORT_PD_MCU MCHP_I2C_PORT3
+#define I2C_PORT_TCPC MCHP_I2C_PORT3
+#define I2C_PORT_ALS MCHP_I2C_PORT4
+#define I2C_PORT_ACCEL MCHP_I2C_PORT4
+#define I2C_PORT_BATTERY MCHP_I2C_PORT5
+#define I2C_PORT_CHARGER MCHP_I2C_PORT5
 
 /* Thermal sensors read through PMIC ADC interface */
 #if 0
-#define I2C_PORT_THERMAL	I2C_PORT_PMIC
+#define I2C_PORT_THERMAL I2C_PORT_PMIC
 #else
-#define I2C_PORT_THERMAL	MCHP_I2C_PORT4
+#define I2C_PORT_THERMAL MCHP_I2C_PORT4
 #endif
 
 /* Ambient Light Sensor address */
-#define OPT3001_I2C_ADDR_FLAGS	OPT3001_I2C_ADDR1_FLAGS
+#define OPT3001_I2C_ADDR_FLAGS OPT3001_I2C_ADDR1_FLAGS
 
 /* Modules we want to exclude */
 #undef CONFIG_CMD_HASH
@@ -425,9 +421,9 @@ enum temp_sensor_id {
 	/* These temp sensors are only readable in S0 */
 	TEMP_SENSOR_AMBIENT,
 	TEMP_SENSOR_CASE,
-/*	TEMP_SENSOR_CHARGER, */
-/*	TEMP_SENSOR_DRAM, */
-/*	TEMP_SENSOR_WIFI, */
+	/*	TEMP_SENSOR_CHARGER, */
+	/*	TEMP_SENSOR_DRAM, */
+	/*	TEMP_SENSOR_WIFI, */
 
 	TEMP_SENSOR_COUNT
 };
@@ -453,25 +449,24 @@ enum als_id {
  * delay to turn on the power supply max is ~16ms.
  * delay to turn off the power supply max is about ~180ms.
  */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* delay to turn on/off vconn */
 
 /* Define typical operating power and max power */
 #define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       45000
-#define PD_MAX_CURRENT_MA     3000
+#define PD_MAX_POWER_MW 45000
+#define PD_MAX_CURRENT_MA 3000
 
 /* Try to negotiate to 20V since i2c noise problems should be fixed. */
-#define PD_MAX_VOLTAGE_MV     20000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /*
  * include TFDP macros from mchp chip level
  */
 #include "tfdp_chip.h"
 
-
 /* Map I2C port to controller */
 int board_i2c_p2c(int port);
 
diff --git a/board/mchpevb1/build.mk b/board/mchpevb1/build.mk
index 412b04d46b..c92a045646 100644
--- a/board/mchpevb1/build.mk
+++ b/board/mchpevb1/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/mchpevb1/ec.tasklist b/board/mchpevb1/ec.tasklist
index 6fcd5faa98..f187bb914a 100644
--- a/board/mchpevb1/ec.tasklist
+++ b/board/mchpevb1/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/mchpevb1/gpio.inc b/board/mchpevb1/gpio.inc
index 3949e31843..b3aa29941e 100644
--- a/board/mchpevb1/gpio.inc
+++ b/board/mchpevb1/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/mchpevb1/led.c b/board/mchpevb1/led.c
index 7b9f7646cb..8a5d85e97d 100644
--- a/board/mchpevb1/led.c
+++ b/board/mchpevb1/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -30,8 +30,7 @@
  * NOTE: GPIO_BAT_LED_xxx defined in board.h
  */
 
-const enum ec_led_id supported_led_ids[] = {
-			EC_LED_ID_BATTERY_LED};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -40,7 +39,7 @@ enum led_color {
 	LED_RED,
 	LED_AMBER,
 	LED_GREEN,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static int bat_led_set_color(enum led_color color)
@@ -68,8 +67,7 @@ static int bat_led_set_color(enum led_color color)
 	return EC_SUCCESS;
 }
 
-void led_get_brightness_range(enum ec_led_id led_id,
-		uint8_t *brightness_range)
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
 {
 	brightness_range[EC_LED_COLOR_RED] = 1;
 	brightness_range[EC_LED_COLOR_GREEN] = 1;
@@ -114,7 +112,6 @@ static void board_led_set_battery(void)
 {
 #ifdef CONFIG_CHARGER
 	static int battery_ticks;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
@@ -129,34 +126,42 @@ static void board_led_set_battery(void)
 	case PWR_STATE_DISCHARGE:
 		/* Less than 3%, blink one second every two second */
 		if (!chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
-			charge_get_percent() < CRITICAL_LOW_BATTERY_PERCENTAGE)
+		    charge_get_percent() < CRITICAL_LOW_BATTERY_PERCENTAGE)
 			board_led_set_color_battery(
 				(battery_ticks % LED_TOTAL_2SECS_TICKS <
-				 LED_ON_1SEC_TICKS) ? LED_AMBER : LED_OFF);
+				 LED_ON_1SEC_TICKS) ?
+					LED_AMBER :
+					LED_OFF);
 		/* Less than 10%, blink one second every four seconds */
 		else if (!chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
-			charge_get_percent() < LOW_BATTERY_PERCENTAGE)
+			 charge_get_percent() < LOW_BATTERY_PERCENTAGE)
 			board_led_set_color_battery(
 				(battery_ticks % LED_TOTAL_4SECS_TICKS <
-				 LED_ON_1SEC_TICKS) ? LED_AMBER : LED_OFF);
+				 LED_ON_1SEC_TICKS) ?
+					LED_AMBER :
+					LED_OFF);
 		else
 			board_led_set_color_battery(LED_OFF);
 		break;
 	case PWR_STATE_ERROR:
 		board_led_set_color_battery(
 			(battery_ticks % LED_TOTAL_2SECS_TICKS <
-			 LED_ON_1SEC_TICKS) ? LED_RED : LED_OFF);
+			 LED_ON_1SEC_TICKS) ?
+				LED_RED :
+				LED_OFF);
 		break;
 	case PWR_STATE_CHARGE_NEAR_FULL:
 		board_led_set_color_battery(LED_GREEN);
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			board_led_set_color_battery(
-				(battery_ticks % LED_TOTAL_4SECS_TICKS <
-				 LED_ON_2SECS_TICKS) ? LED_GREEN : LED_AMBER);
-		else
-			board_led_set_color_battery(LED_GREEN);
+		board_led_set_color_battery(LED_GREEN);
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		board_led_set_color_battery(
+			(battery_ticks % LED_TOTAL_4SECS_TICKS <
+			 LED_ON_2SECS_TICKS) ?
+				LED_GREEN :
+				LED_AMBER);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
@@ -165,7 +170,6 @@ static void board_led_set_battery(void)
 #endif
 }
 
-
 static void led_second(void)
 {
 	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
diff --git a/board/mchpevb1/usb_pd_policy.c b/board/mchpevb1/usb_pd_policy.c
index 690f8b8a3c..f84d5d1171 100644
--- a/board/mchpevb1/usb_pd_policy.c
+++ b/board/mchpevb1/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,19 +18,16 @@
 #include "usb_mux.h"
 #include "usb_pd.h"
 
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_set_power_supply_ready(int port)
 {
 	/* Disable charging */
-	gpio_set_level(port ? GPIO_USB_C1_CHARGE_EN_L :
-			      GPIO_USB_C0_CHARGE_EN_L, 1);
+	gpio_set_level(port ? GPIO_USB_C1_CHARGE_EN_L : GPIO_USB_C0_CHARGE_EN_L,
+		       1);
 	/* Provide VBUS */
-	gpio_set_level(port ? GPIO_USB_C1_5V_EN :
-			      GPIO_USB_C0_5V_EN, 1);
+	gpio_set_level(port ? GPIO_USB_C1_5V_EN : GPIO_USB_C0_5V_EN, 1);
 
 	/* notify host of power info change */
 	pd_send_host_event(PD_EVENT_POWER_CHANGE);
@@ -41,8 +38,7 @@ int pd_set_power_supply_ready(int port)
 void pd_power_supply_reset(int port)
 {
 	/* Disable VBUS */
-	gpio_set_level(port ? GPIO_USB_C1_5V_EN :
-			      GPIO_USB_C0_5V_EN, 0);
+	gpio_set_level(port ? GPIO_USB_C1_5V_EN : GPIO_USB_C0_5V_EN, 0);
 
 	/* notify host of power info change */
 	pd_send_host_event(PD_EVENT_POWER_CHANGE);
diff --git a/board/meep/battery.c b/board/meep/battery.c
index ca9fc531b3..56434d98da 100644
--- a/board/meep/battery.c
+++ b/board/meep/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/meep/board.c b/board/meep/board.c
index 3771c72072..62e4881b1b 100644
--- a/board/meep/board.c
+++ b/board/meep/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -42,13 +42,13 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
-#define USB_PD_PORT_ANX7447	0
-#define USB_PD_PORT_PS8751	1
+#define USB_PD_PORT_ANX7447 0
+#define USB_PD_PORT_PS8751 1
 
 #ifdef CONFIG_KEYBOARD_KEYPAD
 #error "KSO_14 was repurposed to PPC_ID pin so CONFIG_KEYBOARD_KEYPAD \
@@ -86,32 +86,32 @@ static void ppc_interrupt(enum gpio_signal signal)
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_AMB] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_AMB] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				  ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_CHARGER] = { "TEMP_CHARGER", NPCX_ADC_CH1,
+				      ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 },
 	/* Vbus C0 sensing (10x voltage divider). PPVAR_USB_C0_VBUS */
-	[ADC_VBUS_C0] = {
-		"VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
+	[ADC_VBUS_C0] = { "VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT * 10,
+			  ADC_READ_MAX + 1, 0 },
 	/* Vbus C1 sensing (10x voltage divider). PPVAR_USB_C1_VBUS */
-	[ADC_VBUS_C1] = {
-		"VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
+	[ADC_VBUS_C1] = { "VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT * 10,
+			  ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp,
-				 .idx = 0},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
+	[TEMP_SENSOR_BATTERY] = { .name = "Battery",
+				  .type = TEMP_SENSOR_TYPE_BATTERY,
+				  .read = charge_get_battery_temp,
+				  .idx = 0 },
+	[TEMP_SENSOR_AMBIENT] = { .name = "Ambient",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_51k1_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_AMB },
+	[TEMP_SENSOR_CHARGER] = { .name = "Charger",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_13k7_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_CHARGER },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -121,17 +121,13 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t lid_standrd_ref = {
-	{ FLOAT_TO_FP(1),  0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t lid_standrd_ref = { { FLOAT_TO_FP(1), 0, 0 },
+				     { 0, FLOAT_TO_FP(-1), 0 },
+				     { 0, 0, FLOAT_TO_FP(-1) } };
 
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1),  0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+				       { 0, FLOAT_TO_FP(-1), 0 },
+				       { 0, 0, FLOAT_TO_FP(-1) } };
 
 /* sensor private data */
 static struct kionix_accel_data kx022_data;
@@ -228,9 +224,9 @@ int board_is_convertible(void)
 	 * Vortininja: 49, 50, 51, 52
 	 * Unprovisioned: 255
 	 */
-	return sku_id == 1 || sku_id == 2 || sku_id == 3 ||
-	       sku_id == 4 || sku_id == 49 || sku_id == 50 ||
-	       sku_id == 51 || sku_id == 52 || sku_id == 255;
+	return sku_id == 1 || sku_id == 2 || sku_id == 3 || sku_id == 4 ||
+	       sku_id == 49 || sku_id == 50 || sku_id == 51 || sku_id == 52 ||
+	       sku_id == 255;
 }
 
 static void board_update_sensor_config_from_sku(void)
@@ -306,8 +302,8 @@ void board_hibernate_late(void)
 
 	const uint32_t hibernate_pins[][2] = {
 		/* Turn off LEDs before going to hibernate */
-		{GPIO_BAT_LED_WHITE_L, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_BAT_LED_AMBER_L, GPIO_INPUT | GPIO_PULL_UP},
+		{ GPIO_BAT_LED_WHITE_L, GPIO_INPUT | GPIO_PULL_UP },
+		{ GPIO_BAT_LED_AMBER_L, GPIO_INPUT | GPIO_PULL_UP },
 	};
 
 	for (i = 0; i < ARRAY_SIZE(hibernate_pins); ++i)
@@ -336,15 +332,15 @@ __override void lid_angle_peripheral_enable(int enable)
  * The connector has 24 pins total, and there is no pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-		{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-		{0, 7}, {1, 4}, {1, 3}, {1, 6}, {1, 7},
-		{3, 1}, {2, 0}, {1, 5}, {2, 6}, {2, 7},
-		{2, 1}, {2, 4}, {2, 5}, {1, 2}, {2, 3},
-		{2, 2}, {3, 0}, {-1, -1}, {-1, -1}, {-1, -1},
+	{ -1, -1 }, { 0, 5 }, { 1, 1 },	  { 1, 0 },   { 0, 6 },
+	{ 0, 7 },   { 1, 4 }, { 1, 3 },	  { 1, 6 },   { 1, 7 },
+	{ 3, 1 },   { 2, 0 }, { 1, 5 },	  { 2, 6 },   { 2, 7 },
+	{ 2, 1 },   { 2, 4 }, { 2, 5 },	  { 1, 2 },   { 2, 3 },
+	{ 2, 2 },   { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 },
 };
 
 const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 #endif
 
 void board_overcurrent_event(int port, int is_overcurrented)
@@ -389,31 +385,29 @@ __override uint16_t board_get_ps8xxx_product_id(int port)
 }
 
 static const struct ppc_config_t ppc_syv682x_port0 = {
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
+	.i2c_port = I2C_PORT_TCPC0,
+	.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+	.drv = &syv682x_drv,
 };
 
 static const struct ppc_config_t ppc_syv682x_port1 = {
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
+	.i2c_port = I2C_PORT_TCPC1,
+	.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+	.drv = &syv682x_drv,
 };
 
 static void board_setup_ppc(void)
 {
 	if (c0_port_ppc == PPC_SYV682X) {
-		memcpy(&ppc_chips[USB_PD_PORT_TCPC_0],
-			   &ppc_syv682x_port0,
-			   sizeof(struct ppc_config_t));
+		memcpy(&ppc_chips[USB_PD_PORT_TCPC_0], &ppc_syv682x_port0,
+		       sizeof(struct ppc_config_t));
 
 		gpio_set_flags(GPIO_USB_PD_C0_INT_ODL, GPIO_INT_BOTH);
 	}
 
 	if (c1_port_ppc == PPC_SYV682X) {
-		memcpy(&ppc_chips[USB_PD_PORT_TCPC_1],
-			   &ppc_syv682x_port1,
-			   sizeof(struct ppc_config_t));
+		memcpy(&ppc_chips[USB_PD_PORT_TCPC_1], &ppc_syv682x_port1,
+		       sizeof(struct ppc_config_t));
 
 		gpio_set_flags(GPIO_USB_PD_C1_INT_ODL, GPIO_INT_BOTH);
 	}
diff --git a/board/meep/board.h b/board/meep/board.h
index 008592c7f1..6f437fb852 100644
--- a/board/meep/board.h
+++ b/board/meep/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,8 +22,8 @@
 #define CONFIG_LED_COMMON
 
 /* Sensors */
-#define CONFIG_ACCEL_KX022		/* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM	/* Base accel */
+#define CONFIG_ACCEL_KX022 /* Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
 
 /* Sensors without hardware FIFO are in forced mode */
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
@@ -66,10 +66,10 @@
 #include "registers.h"
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_AMB,		/* ADC0 */
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC1 */
-	ADC_VBUS_C0,			/* ADC9 */
-	ADC_VBUS_C1,			/* ADC4 */
+	ADC_TEMP_SENSOR_AMB, /* ADC0 */
+	ADC_TEMP_SENSOR_CHARGER, /* ADC1 */
+	ADC_VBUS_C0, /* ADC9 */
+	ADC_VBUS_C1, /* ADC4 */
 	ADC_CH_COUNT
 };
 
@@ -80,18 +80,10 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_COUNT };
 
 /* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
 enum battery_type {
 	BATTERY_DYNAPACK_COS,
diff --git a/board/meep/build.mk b/board/meep/build.mk
index 3d04b75731..998a65a3de 100644
--- a/board/meep/build.mk
+++ b/board/meep/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/meep/ec.tasklist b/board/meep/ec.tasklist
index d98db145e7..977b8b01be 100644
--- a/board/meep/ec.tasklist
+++ b/board/meep/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/meep/gpio.inc b/board/meep/gpio.inc
index ebb69bdf53..aeb659624a 100644
--- a/board/meep/gpio.inc
+++ b/board/meep/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/meep/led.c b/board/meep/led.c
index e20a88d268..87d94904c4 100644
--- a/board/meep/led.c
+++ b/board/meep/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,8 +11,8 @@
 #include "led_onoff_states.h"
 #include "hooks.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
 __override const int led_charge_lvl_1;
 
@@ -20,36 +20,43 @@ __override const int led_charge_lvl_2 = 100;
 
 /* Meep: Note there is only LED for charge / power */
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF, 1 * LED_ONE_SEC} },
-	/* STATE_DISCHARGE_S3 will changed if sku is clamshells */
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_WHITE, 0.5 * LED_ONE_SEC},
-					{LED_OFF, 0.5 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF, 1 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_WHITE,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 1 * LED_ONE_SEC } },
+		/* STATE_DISCHARGE_S3 will changed if sku is clamshells */
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_WHITE,
+					    0.5 * LED_ONE_SEC },
+					  { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 1 * LED_ONE_SEC } },
+	};
 
 __override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   1 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   1 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 1 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    1 * LED_ONE_SEC },
+						  { LED_OFF,
+						    1 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 
 static void s3_led_init(void)
 {
diff --git a/board/metaknight/battery.c b/board/metaknight/battery.c
index 943771ffa4..cff274ae4f 100644
--- a/board/metaknight/battery.c
+++ b/board/metaknight/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/metaknight/board.c b/board/metaknight/board.c
index bfff864b89..5aa3a21cc0 100644
--- a/board/metaknight/board.c
+++ b/board/metaknight/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -49,13 +49,13 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 #define INT_RECHECK_US 5000
 
-#define ADC_VOL_UP_MASK     BIT(0)
-#define ADC_VOL_DOWN_MASK   BIT(1)
+#define ADC_VOL_UP_MASK BIT(0)
+#define ADC_VOL_DOWN_MASK BIT(1)
 
 static uint8_t new_adc_key_state;
 
@@ -101,7 +101,6 @@ static void usb_c0_interrupt(enum gpio_signal s)
 
 	/* Check the line again in 5ms */
 	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-
 }
 
 static void sub_hdmi_hpd_interrupt(enum gpio_signal s)
@@ -119,7 +118,7 @@ static void sub_hdmi_hpd_interrupt(enum gpio_signal s)
 static void pen_input_deferred(void)
 {
 	int pen_charge_enable = !gpio_get_level(GPIO_PEN_DET_ODL) &&
-			!chipset_in_state(CHIPSET_STATE_ANY_OFF);
+				!chipset_in_state(CHIPSET_STATE_ANY_OFF);
 
 	if (pen_charge_enable)
 		gpio_set_level(GPIO_EN_PP3300_PEN, 1);
@@ -181,26 +180,22 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 /* Thermistors */
 const struct temp_sensor_t temp_sensors[] = {
 
-	[TEMP_SENSOR_MEMORY] = {
-		.name = "Memory",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_51k1_47k_4050b,
-		.idx  = ADC_TEMP_SENSOR_1
-	},
-	[TEMP_SENSOR_CPU] = {
-		.name = "CPU",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_51k1_47k_4050b,
-		.idx  = ADC_TEMP_SENSOR_2
-	},
+	[TEMP_SENSOR_MEMORY] = { .name = "Memory",
+				 .type = TEMP_SENSOR_TYPE_BOARD,
+				 .read = get_temp_3v3_51k1_47k_4050b,
+				 .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_CPU] = { .name = "CPU",
+			      .type = TEMP_SENSOR_TYPE_BOARD,
+			      .read = get_temp_3v3_51k1_47k_4050b,
+			      .idx = ADC_TEMP_SENSOR_2 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_MEMORY \
-	{ \
+#define THERMAL_MEMORY           \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = 0, \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
@@ -218,8 +213,8 @@ __maybe_unused static const struct ec_thermal_config thermal_memory =
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CPU \
-	{ \
+#define THERMAL_CPU              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = 0, \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
@@ -238,7 +233,7 @@ struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
 static void setup_thermal(void)
 {
 	thermal_params[TEMP_SENSOR_MEMORY] = thermal_memory;
-	thermal_params[TEMP_SENSOR_CPU]    = thermal_cpu;
+	thermal_params[TEMP_SENSOR_CPU] = thermal_cpu;
 }
 
 void board_hibernate(void)
@@ -274,7 +269,7 @@ static void reconfigure_5v_gpio(void)
 		gpio_set_flags(GPIO_VOLUP_BTN_ODL, GPIO_OUT_LOW);
 	}
 }
-DECLARE_HOOK(HOOK_INIT, reconfigure_5v_gpio, HOOK_PRIO_INIT_I2C+1);
+DECLARE_HOOK(HOOK_INIT, reconfigure_5v_gpio, HOOK_PRIO_INIT_I2C + 1);
 #endif /* BOARD_WADDLEDOO */
 
 static void set_5v_gpio(int level)
@@ -312,7 +307,7 @@ __override void board_power_5v_enable(int enable)
 	set_5v_gpio(!!enable);
 
 	if (get_cbi_fw_config_db() == DB_1A_HDMI ||
-		get_cbi_fw_config_db() == DB_LTE_HDMI) {
+	    get_cbi_fw_config_db() == DB_LTE_HDMI) {
 		gpio_set_level(GPIO_SUB_C1_INT_EN_RAILS_ODL, !enable);
 	}
 }
@@ -333,13 +328,11 @@ int board_is_sourcing_vbus(int port)
 
 	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
 	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
-
 }
 
 int board_set_active_charge_port(int port)
 {
-	int is_real_port = (port >= 0 &&
-			    port < board_get_usb_pd_port_count());
+	int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count());
 	int i;
 	int old_port;
 
@@ -403,8 +396,8 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
 
@@ -429,29 +422,21 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrices to rotate accelerometers into the standard reference. */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
 
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					      { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
 
-static const mat33_fp_t base_lsm6dsm_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t base_lsm6dsm_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, FLOAT_TO_FP(1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
-static const mat33_fp_t base_icm_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t base_icm_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					 { 0, FLOAT_TO_FP(1), 0 },
+					 { 0, 0, FLOAT_TO_FP(-1) } };
 
 static struct accelgyro_saved_data_t g_bma253_data;
 static struct bmi_drv_data_t g_bmi160_data;
@@ -593,8 +578,7 @@ struct motion_sensor_t lsm6dsm_base_gyro = {
 	.location = MOTIONSENSE_LOC_BASE,
 	.drv = &lsm6dsm_drv,
 	.mutex = &g_base_mutex,
-	.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-			MOTIONSENSE_TYPE_GYRO),
+	.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data, MOTIONSENSE_TYPE_GYRO),
 	.port = I2C_PORT_SENSOR,
 	.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
 	.default_range = 1000 | ROUND_UP_FLAG, /* dps */
@@ -603,7 +587,6 @@ struct motion_sensor_t lsm6dsm_base_gyro = {
 	.max_frequency = LSM6DSM_ODR_MAX_VAL,
 };
 
-
 struct motion_sensor_t icm426xx_base_accel = {
 	.name = "Base Accel",
 	.active_mask = SENSOR_ACTIVE_S0_S3,
@@ -660,12 +643,12 @@ void board_init(void)
 	check_c0_line();
 
 	if (get_cbi_fw_config_db() == DB_1A_HDMI ||
-		get_cbi_fw_config_db() == DB_LTE_HDMI) {
+	    get_cbi_fw_config_db() == DB_LTE_HDMI) {
 		/* Disable i2c on HDMI pins */
 		gpio_config_pin(MODULE_I2C, GPIO_HDMI_HPD_SUB_ODL, 0);
 		gpio_config_pin(MODULE_I2C, GPIO_GPIO92_NC, 0);
 
-		gpio_set_flags(GPIO_SUB_C1_INT_EN_RAILS_ODL,   GPIO_ODR_HIGH);
+		gpio_set_flags(GPIO_SUB_C1_INT_EN_RAILS_ODL, GPIO_ODR_HIGH);
 
 		/* Select HDMI option */
 		gpio_set_level(GPIO_HDMI_SEL_L, 0);
@@ -674,8 +657,7 @@ void board_init(void)
 		gpio_enable_interrupt(GPIO_HDMI_HPD_SUB_ODL);
 	} else {
 		/* Set SDA as an input */
-		gpio_set_flags(GPIO_HDMI_HPD_SUB_ODL,
-			       GPIO_INPUT);
+		gpio_set_flags(GPIO_HDMI_HPD_SUB_ODL, GPIO_INPUT);
 	}
 	/* Enable gpio interrupt for base accelgyro sensor */
 	gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
@@ -693,11 +675,11 @@ void board_init(void)
 
 	if (base_gyro_config == SSFC_SENSOR_LSM6DSM) {
 		motion_sensors[BASE_ACCEL] = lsm6dsm_base_accel;
-		motion_sensors[BASE_GYRO]  = lsm6dsm_base_gyro;
+		motion_sensors[BASE_GYRO] = lsm6dsm_base_gyro;
 		cprints(CC_SYSTEM, "SSFC: BASE GYRO is LSM6DSM");
 	} else if (get_cbi_ssfc_base_sensor() == SSFC_SENSOR_ICM426XX) {
 		motion_sensors[BASE_ACCEL] = icm426xx_base_accel;
-		motion_sensors[BASE_GYRO]  = icm426xx_base_gyro;
+		motion_sensors[BASE_GYRO] = icm426xx_base_gyro;
 		cprints(CC_SYSTEM, "SSFC: BASE GYRO is ICM426XX");
 	} else
 		cprints(CC_SYSTEM, "SSFC: BASE GYRO is BMI160");
@@ -710,7 +692,6 @@ void board_init(void)
 
 	/* Initial thermal */
 	setup_thermal();
-
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
@@ -748,12 +729,15 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
-		.driver = &pi3usb3x532_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
+				.driver = &pi3usb3x532_usb_mux_driver,
+			},
 	},
 };
 
@@ -873,45 +857,35 @@ void motion_interrupt(enum gpio_signal signal)
 }
 
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_EEPROM_SCL,
-		.sda  = GPIO_EC_I2C_EEPROM_SDA
-	},
-
-	{
-		.name = "battery",
-		.port = I2C_PORT_BATTERY,
-		.kbps = 100,
-		.scl  = GPIO_EC_I2C_BATTERY_SCL,
-		.sda  = GPIO_EC_I2C_BATTERY_SDA
-	},
-
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_SENSOR_SCL,
-		.sda  = GPIO_EC_I2C_SENSOR_SDA
-	},
-
-	{
-		.name = "usbc0",
-		.port = I2C_PORT_USB_C0,
-		.kbps = 1000,
-		.scl  = GPIO_EC_I2C_USB_C0_SCL,
-		.sda  = GPIO_EC_I2C_USB_C0_SDA
-	},
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_EEPROM_SCL,
+	  .sda = GPIO_EC_I2C_EEPROM_SDA },
+
+	{ .name = "battery",
+	  .port = I2C_PORT_BATTERY,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_BATTERY_SCL,
+	  .sda = GPIO_EC_I2C_BATTERY_SDA },
+
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_SENSOR_SCL,
+	  .sda = GPIO_EC_I2C_SENSOR_SDA },
+
+	{ .name = "usbc0",
+	  .port = I2C_PORT_USB_C0,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C0_SCL,
+	  .sda = GPIO_EC_I2C_USB_C0_SDA },
 #if CONFIG_USB_PD_PORT_MAX_COUNT > 1
-	{
-		.name = "sub_usbc1",
-		.port = I2C_PORT_SUB_USB_C1,
-		.kbps = 1000,
-		.scl  = GPIO_EC_I2C_SUB_USB_C1_SCL,
-		.sda  = GPIO_EC_I2C_SUB_USB_C1_SDA
-	},
+	{ .name = "sub_usbc1",
+	  .port = I2C_PORT_SUB_USB_C1,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_SUB_USB_C1_SCL,
+	  .sda = GPIO_EC_I2C_SUB_USB_C1_SDA },
 #endif
 };
 
diff --git a/board/metaknight/board.h b/board/metaknight/board.h
index c331c76457..5bd3c56a83 100644
--- a/board/metaknight/board.h
+++ b/board/metaknight/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,15 +11,15 @@
 #define VARIANT_DEDEDE_EC_NPCX796FC
 #include "baseboard.h"
 
-
 /* Battery */
 #define CONFIG_BATTERY_FUEL_GAUGE
 
 /* Charger */
 #define CONFIG_CHARGER_RAA489000
+#define PD_MAX_VOLTAGE_MV 20000
 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 #define CONFIG_CHARGER_SENSE_RESISTOR 10
-#undef  CONFIG_CHARGER_SINGLE_CHIP
+#undef CONFIG_CHARGER_SINGLE_CHIP
 #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
 #define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
 
@@ -31,12 +31,11 @@
  */
 #define GPIO_USB_C1_INT_ODL GPIO_SUB_C1_INT_EN_RAILS_ODL
 
-
 /* LED defines */
 #define CONFIG_LED_ONOFF_STATES
 
 /* PWM */
-#define NPCX7_PWM1_SEL    1  /* GPIO C2 is used as PWM1. */
+#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */
 
 /* Temp sensor */
 #define CONFIG_TEMP_SENSOR
@@ -71,16 +70,16 @@
 #define CONFIG_USB_PD_5V_EN_CUSTOM
 
 /* I2C configuration */
-#define I2C_PORT_EEPROM     NPCX_I2C_PORT7_0
-#define I2C_PORT_BATTERY    NPCX_I2C_PORT5_0
-#define I2C_PORT_SENSOR     NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0     NPCX_I2C_PORT1_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
 #define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_MUX    I2C_PORT_USB_C0
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0
 /* TODO(b:147440290): Need to handle multiple charger ICs */
-#define I2C_PORT_CHARGER    I2C_PORT_USB_C0
+#define I2C_PORT_CHARGER I2C_PORT_USB_C0
 
-#define I2C_PORT_ACCEL      I2C_PORT_SENSOR
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
 
 #define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */
 
@@ -97,16 +96,16 @@
 #define CONFIG_CMD_ACCELS
 #define CONFIG_CMD_ACCEL_INFO
 
-#define CONFIG_ACCEL_BMA255         /* Lid accel */
-#define CONFIG_ACCEL_KX022          /* Lid accel second source */
-#define CONFIG_ACCELGYRO_BMI160     /* Base accel */
-#define CONFIG_ACCELGYRO_LSM6DSM    /* Base accel second source */
-#define CONFIG_ACCELGYRO_ICM426XX   /* Base accel second source */
+#define CONFIG_ACCEL_BMA255 /* Lid accel */
+#define CONFIG_ACCEL_KX022 /* Lid accel second source */
+#define CONFIG_ACCELGYRO_BMI160 /* Base accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel second source */
+#define CONFIG_ACCELGYRO_ICM426XX /* Base accel second source */
 
 /* Lid operates in forced mode, base in FIFO */
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
 #define CONFIG_ACCEL_FIFO
-#define CONFIG_ACCEL_FIFO_SIZE 256	/* Must be a power of 2 */
+#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */
 #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
 
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
@@ -154,25 +153,16 @@ enum chg_id {
 };
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_1,     /* ADC0 */
-	ADC_TEMP_SENSOR_2,     /* ADC1 */
-	ADC_SUB_ANALOG,	       /* ADC2 */
-	ADC_VSNS_PP3300_A,     /* ADC9 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
+	ADC_SUB_ANALOG, /* ADC2 */
+	ADC_VSNS_PP3300_A, /* ADC9 */
 	ADC_CH_COUNT
 };
 
-enum temp_sensor_id {
-	TEMP_SENSOR_MEMORY,
-	TEMP_SENSOR_CPU,
-	TEMP_SENSOR_COUNT
-};
+enum temp_sensor_id { TEMP_SENSOR_MEMORY, TEMP_SENSOR_CPU, TEMP_SENSOR_COUNT };
 
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
 enum pwm_channel {
 	PWM_CH_COUNT,
diff --git a/board/metaknight/build.mk b/board/metaknight/build.mk
index cd002a20e7..1531d1f3ae 100644
--- a/board/metaknight/build.mk
+++ b/board/metaknight/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/metaknight/cbi_ssfc.c b/board/metaknight/cbi_ssfc.c
index c4b859f133..81f3ee0dad 100644
--- a/board/metaknight/cbi_ssfc.c
+++ b/board/metaknight/cbi_ssfc.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
 
 enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
 {
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
 }
 
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
 {
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
 }
diff --git a/board/metaknight/cbi_ssfc.h b/board/metaknight/cbi_ssfc.h
index 935049b6ae..bf8853a43a 100644
--- a/board/metaknight/cbi_ssfc.h
+++ b/board/metaknight/cbi_ssfc.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -56,5 +56,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
  */
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
 
-
 #endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/metaknight/ec.tasklist b/board/metaknight/ec.tasklist
index dc4065cf98..6316569c9a 100644
--- a/board/metaknight/ec.tasklist
+++ b/board/metaknight/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/metaknight/gpio.inc b/board/metaknight/gpio.inc
index dee2e2dadf..4d68595d65 100644
--- a/board/metaknight/gpio.inc
+++ b/board/metaknight/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/metaknight/led.c b/board/metaknight/led.c
index 466037695c..a48b4bcf2a 100644
--- a/board/metaknight/led.c
+++ b/board/metaknight/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,20 +19,27 @@ __override const int led_charge_lvl_1;
 __override const int led_charge_lvl_2 = 100;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
 const enum ec_led_id supported_led_ids[] = {
 	EC_LED_ID_BATTERY_LED,
diff --git a/board/metaknight/usb_pd_policy.c b/board/metaknight/usb_pd_policy.c
index 3190595596..23166f7fca 100644
--- a/board/metaknight/usb_pd_policy.c
+++ b/board/metaknight/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,8 @@
 #include "driver/tcpm/tcpci.h"
 #include "usb_pd.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
diff --git a/board/mithrax/battery.c b/board/mithrax/battery.c
index 8c03169b1c..16840d5b3d 100644
--- a/board/mithrax/battery.c
+++ b/board/mithrax/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -87,6 +87,35 @@ const struct board_batt_params board_battery_info[] = {
 			.discharging_max_c	= 60,
 		},
 	},
+	[BATTERY_C340] = {
+		.fuel_gauge = {
+			.manuf_name = "AS3FXXD3KB",
+			.device_name = "C340152",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr = 0x99,
+				.reg_mask       = 0x000C,
+				.disconnect_val = 0x000C,
+				.cfet_mask = 0x0004,
+				.cfet_off_val = 0x0004,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13350,
+			.voltage_normal		= 11985, /* mV */
+			.voltage_min		= 9000, /* mV */
+			.precharge_current	= 256,	/* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 45,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 60,
+		},
+	},
 };
 BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
 
diff --git a/board/mithrax/board.c b/board/mithrax/board.c
index 3db87618f8..69ba7d5b32 100644
--- a/board/mithrax/board.c
+++ b/board/mithrax/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,12 +25,15 @@
 #include "tablet_mode.h"
 #include "throttle_ap.h"
 #include "usbc_config.h"
+#include "keyboard_backlight.h"
+#include "rgb_keyboard.h"
+#include "ec_commands.h"
 
 #include "gpio_list.h" /* Must come after other header files. */
 
 /* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 static void rgb_backlight_config(void);
 
@@ -57,14 +60,6 @@ static void board_chipset_resume(void)
 }
 DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
 
-/* Called on AP S0 -> S3 transition */
-static void board_chipset_suspend(void)
-{
-	/* Turn off the keyboard backlight if it's on. */
-	gpio_set_level(GPIO_EC_KB_BL_EN_L, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
-
 /* Called on AP S5 -> S3 transition */
 static void board_chipset_startup(void)
 {
@@ -97,8 +92,8 @@ int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
 	}
 
 	if (voltage < BC12_MIN_VOLTAGE) {
-		CPRINTS("%s: port %d: vbus %d lower than %d", __func__,
-			port, voltage, BC12_MIN_VOLTAGE);
+		CPRINTS("%s: port %d: vbus %d lower than %d", __func__, port,
+			voltage, BC12_MIN_VOLTAGE);
 		return 1;
 	}
 
@@ -119,18 +114,11 @@ enum battery_present battery_hw_present(void)
 
 static void board_init(void)
 {
-	if (ec_cfg_usb_db_type() == DB_USB4_NCT3807)
-		db_update_usb4_config_from_config();
-
-	if (ec_cfg_usb_mb_type() == MB_USB4_TBT)
-		mb_update_usb4_tbt_config_from_config();
-
 	if (ec_cfg_stylus() == STYLUS_PRSENT)
 		gpio_enable_interrupt(GPIO_PEN_DET_ODL);
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
-
 /**
  * Deferred function to handle pen detect change
  */
@@ -153,8 +141,7 @@ DECLARE_HOOK(HOOK_INIT, pendetect_deferred, HOOK_PRIO_DEFAULT);
 void pen_detect_interrupt(enum gpio_signal s)
 {
 	/* Trigger deferred notification of pen detect change */
-	hook_call_deferred(&pendetect_deferred_data,
-			500 * MSEC);
+	hook_call_deferred(&pendetect_deferred_data, 500 * MSEC);
 }
 
 void pen_config(void)
@@ -182,3 +169,16 @@ static void rgb_backlight_config(void)
 	else
 		gpio_set_level(GPIO_EN_PP5000_LED, 0);
 }
+
+void board_kblight_init(void)
+{
+	if ((IS_ENABLED(CONFIG_PWM_KBLIGHT)) &&
+	    (ec_cfg_kb_backlight() == SOLID_COLOR)) {
+		kblight_register(&kblight_pwm);
+		rgbkbd_type = EC_RGBKBD_TYPE_UNKNOWN;
+	} else if ((IS_ENABLED(CONFIG_RGB_KEYBOARD)) &&
+		   (ec_cfg_kb_backlight() == RGB)) {
+		kblight_register(&kblight_rgbkbd);
+		rgbkbd_type = EC_RGBKBD_TYPE_FOUR_ZONES_4_LEDS;
+	}
+}
diff --git a/board/mithrax/board.h b/board/mithrax/board.h
index c9d2112b2c..d12375d678 100644
--- a/board/mithrax/board.h
+++ b/board/mithrax/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -29,11 +29,11 @@
 /* LED */
 #define CONFIG_LED_ONOFF_STATES
 #define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
-#define GPIO_BAT_LED_AMBER_L	GPIO_LED_3_L
-#define GPIO_BAT_LED_WHITE_L	GPIO_LED_4_L
+#define GPIO_BAT_LED_AMBER_L GPIO_LED_3_L
+#define GPIO_BAT_LED_WHITE_L GPIO_LED_4_L
 
 /* Sensors */
-#define CONFIG_ACCELGYRO_LSM6DSO	/* Base accel */
+#define CONFIG_ACCELGYRO_LSM6DSO /* Base accel */
 #define CONFIG_ACCEL_LSM6DSO_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 
@@ -49,8 +49,8 @@
 /* Lid accel */
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE	BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID	LID_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
 #define CONFIG_ACCEL_LIS2DWL
 #define CONFIG_ACCEL_LIS2DW_AS_BASE
 #define CONFIG_ACCEL_LIS2DW12_INT_EVENT \
@@ -61,16 +61,15 @@
 #define CONFIG_CMD_ACCEL_INFO
 
 /* USB Type A Features */
-#define USB_PORT_COUNT			1
+#define USB_PORT_COUNT 1
 #define CONFIG_USB_PORT_POWER_DUMB
 
 /* USB Type C and USB PD defines */
 #define CONFIG_IO_EXPANDER
 #define CONFIG_IO_EXPANDER_NCT38XX
-#define CONFIG_IO_EXPANDER_PORT_COUNT		2
+#define CONFIG_IO_EXPANDER_PORT_COUNT 2
 
 #define CONFIG_USB_PD_TCPM_PS8815
-#define CONFIG_USBC_RETIMER_INTEL_BB
 
 /* I2C control host command */
 #define CONFIG_HOSTCMD_I2C_CONTROL
@@ -82,17 +81,17 @@
 #define CONFIG_USBC_PPC_NX20P3483
 
 /* TODO: b/177608416 - measure and check these values on mithrax */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
 
 /*
  * Passive USB-C cables only support up to 60W.
  */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		65000
-#define PD_MAX_CURRENT_MA	3250
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 65000
+#define PD_MAX_CURRENT_MA 3250
+#define PD_MAX_VOLTAGE_MV 20000
 
 /*
  * Macros for GPIO signals used in common code that don't match the
@@ -100,74 +99,66 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT		GPIO_EC_EN_EDP_BL
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_GSC_PACKET_MODE
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SYS_SLP_S0IX_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_TEMP_SENSOR_POWER	GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
 
 /*
  * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
  * signal.
  */
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_SEQ_EC_ALL_SYS_PG
-#define GPIO_PG_EC_DSW_PWROK		GPIO_SEQ_EC_DSW_PWROK
-#define GPIO_PG_EC_RSMRST_ODL		GPIO_SEQ_EC_RSMRST_ODL
-#define GPIO_POWER_BUTTON_L		GPIO_GSC_EC_PWR_BTN_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_ODL
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
 
 /* System has back-lit keyboard */
 #define CONFIG_KEYBOARD_BACKLIGHT
 
 /* I2C Bus Configuration */
 
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
 
-#define I2C_PORT_USB_C2_TCPC	NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1_TCPC	NPCX_I2C_PORT4_1
+#define I2C_PORT_USB_C2_TCPC NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1
 
-#define I2C_PORT_USB_C2_PPC	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_PPC	NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C2_PPC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1
 
-#define I2C_PORT_USB_C2_BC12	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_BC12	NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C2_BC12 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1
 
-#define I2C_PORT_USB_C2_MUX	NPCX_I2C_PORT3_0
-#define I2C_PORT_USB_C1_MUX	NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C2_MUX NPCX_I2C_PORT3_0
+#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1
 
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT5_0
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT7_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-#define I2C_PORT_MP2964		NPCX_I2C_PORT7_0
-#define I2C_PORT_KBMCU		NPCX_I2C_PORT3_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0
+#define I2C_PORT_KBMCU NPCX_I2C_PORT3_0
 
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 
-#define I2C_ADDR_MP2964_FLAGS	0x20
+#define I2C_ADDR_MP2964_FLAGS 0x20
 
 /*
  *
  */
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x56
-#define USBC_PORT_C2_BB_RETIMER_I2C_ADDR	0x58
-
-/* Enabling Thunderbolt-compatible mode */
-#define CONFIG_USB_PD_TBT_COMPAT_MODE
-
-/* Enabling USB4 mode */
-#define CONFIG_USB_PD_USB4
 
 /* Retimer */
 #define CONFIG_USBC_RETIMER_FW_UPDATE
@@ -178,26 +169,28 @@
 #define CONFIG_TEMP_SENSOR_POWER
 #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
 
-#define CONFIG_FANS			FAN_CH_COUNT
+#define CONFIG_FANS FAN_CH_COUNT
 
 /* Charger defines */
 #define CONFIG_CHARGER_ISL9241
 #define CONFIG_CHARGE_RAMP_SW
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 
 /* RGB Keyboard */
 #ifdef SECTION_IS_RW
 #define CONFIG_RGB_KEYBOARD
-#define CONFIG_LED_DRIVER_TLC59116F     /* TLC59116F on I2C */
-#define TLC59116F_I2C_ADDR_FLAG		TLC59116F_ADDR3_FLAG
+#define CONFIG_LED_DRIVER_TLC59116F /* TLC59116F on I2C */
+#define TLC59116F_I2C_ADDR_FLAG TLC59116F_ADDR3_FLAG
 #endif /* SECTION_IS_RW */
-#define RGB_GRID0_COL		4
-#define RGB_GRID0_ROW		1
+#define RGB_GRID0_COL 4
+#define RGB_GRID0_ROW 1
+
+#define CONFIG_PWM_KBLIGHT
 
 #ifndef __ASSEMBLER__
 
-#include "gpio_signal.h"	/* needed by registers.h */
+#include "gpio_signal.h" /* needed by registers.h */
 #include "registers.h"
 #include "usbc_config.h"
 
@@ -215,40 +208,26 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL = 0, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
-enum ioex_port {
-	IOEX_C2_NCT38XX = 0,
-	IOEX_C1_NCT38XX,
-	IOEX_PORT_COUNT
-};
+enum ioex_port { IOEX_C2_NCT38XX = 0, IOEX_C1_NCT38XX, IOEX_PORT_COUNT };
 
 enum battery_type {
 	BATTERY_C536,
 	BATTERY_C490,
+	BATTERY_C340,
 	BATTERY_TYPE_COUNT
 };
 
 enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,	/* PWM3 */
-	PWM_CH_FAN,			/* PWM5 */
+	PWM_CH_KBLIGHT = 0, /* PWM3 */
+	PWM_CH_FAN, /* PWM5 */
 	PWM_CH_COUNT
 };
 
-enum fan_channel {
-	FAN_CH_0 = 0,
-	FAN_CH_COUNT
-};
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT };
 
-enum mft_channel {
-	MFT_CH_0 = 0,
-	MFT_CH_COUNT
-};
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT };
 
 void pen_detect_interrupt(enum gpio_signal s);
 
diff --git a/board/mithrax/build.mk b/board/mithrax/build.mk
index a7ec1987de..ca2d2e6c70 100644
--- a/board/mithrax/build.mk
+++ b/board/mithrax/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/mithrax/charger_isl9241.c b/board/mithrax/charger_isl9241.c
index 10bc45b333..a9eafe353e 100644
--- a/board/mithrax/charger_isl9241.c
+++ b/board/mithrax/charger_isl9241.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,9 +15,8 @@
 #include "usb_pd.h"
 #include "util.h"
 
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* Charger Chip Configuration */
 const struct charger_config_t chg_chips[] = {
@@ -85,7 +84,6 @@ __overridable void board_set_charge_limit(int port, int supplier, int charge_ma,
 					  int max_ma, int charge_mv)
 {
 	charge_ma = (charge_ma * 90) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
diff --git a/board/mithrax/ec.tasklist b/board/mithrax/ec.tasklist
index b6a6557d1e..8949bb98e7 100644
--- a/board/mithrax/ec.tasklist
+++ b/board/mithrax/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/mithrax/fans.c b/board/mithrax/fans.c
index 1f75eb6ca3..fd7b380f77 100644
--- a/board/mithrax/fans.c
+++ b/board/mithrax/fans.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,7 +25,7 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 static const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
diff --git a/board/mithrax/fw_config.c b/board/mithrax/fw_config.c
index 6985059d50..17b623371f 100644
--- a/board/mithrax/fw_config.c
+++ b/board/mithrax/fw_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,7 +9,7 @@
 #include "cros_board_info.h"
 #include "fw_config.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 static union mithrax_cbi_fw_config fw_config;
 BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
diff --git a/board/mithrax/fw_config.h b/board/mithrax/fw_config.h
index 4e9ba7f3c6..c7053c0da4 100644
--- a/board/mithrax/fw_config.h
+++ b/board/mithrax/fw_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,43 +14,31 @@
  * Source of truth is the project/brya/mithrax/config.star configuration file.
  */
 
-enum ec_cfg_usb_db_type {
-	DB_USB3_PS8815 = 1,
-	DB_USB4_NCT3807 = 2
-};
+enum ec_cfg_usb_db_type { DB_USB_ABSENT = 0, DB_USB3_PS8815 = 1 };
 
 enum ec_cfg_keyboard_backlight_type {
 	KEYBOARD_BACKLIGHT_DISABLED = 0,
 	KEYBOARD_BACKLIGHT_ENABLED = 1
 };
 
-enum ec_cfg_usb_mb_type {
-	MB_USB4_TBT = 0,
-	MB_USB3_NON_TBT = 1
-};
+enum ec_cfg_usb_mb_type { NA = 0, MB_USB3_NON_TBT = 1 };
 
-enum ec_cfg_stylus_type {
-	STYLUS_ABSENT = 0,
-	STYLUS_PRSENT = 1
-};
+enum ec_cfg_stylus_type { STYLUS_ABSENT = 0, STYLUS_PRSENT = 1 };
 
-enum ec_cfg_kb_backlight_type {
-	SOLID_COLOR = 0,
-	RGB = 1
-};
+enum ec_cfg_kb_backlight_type { SOLID_COLOR = 0, RGB = 1 };
 
 union mithrax_cbi_fw_config {
 	struct {
-		enum ec_cfg_usb_db_type			usb_db : 3;
-		uint32_t				wifi : 1;
-		enum ec_cfg_kb_backlight_type		rgb : 1;
-		enum ec_cfg_stylus_type			stylus : 1;
-		enum ec_cfg_keyboard_backlight_type	kb_bl : 1;
-		uint32_t				audio : 3;
-		uint32_t				thermal : 2;
-		uint32_t				table_mode : 1;
-		enum ec_cfg_usb_mb_type			usb_mb : 3;
-		uint32_t				reserved_1 : 16;
+		enum ec_cfg_usb_db_type usb_db : 3;
+		uint32_t wifi : 1;
+		enum ec_cfg_kb_backlight_type rgb : 1;
+		enum ec_cfg_stylus_type stylus : 1;
+		enum ec_cfg_keyboard_backlight_type kb_bl : 1;
+		uint32_t audio : 3;
+		uint32_t thermal : 2;
+		uint32_t table_mode : 1;
+		enum ec_cfg_usb_mb_type usb_mb : 3;
+		uint32_t reserved_1 : 16;
 	};
 	uint32_t raw_value;
 };
diff --git a/board/mithrax/gpio.inc b/board/mithrax/gpio.inc
index 133efd0390..1ee2ae40f0 100644
--- a/board/mithrax/gpio.inc
+++ b/board/mithrax/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2022 The Chromium OS Authors. All rights reserved.
+ * Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/mithrax/i2c.c b/board/mithrax/i2c.c
index 7833d1c154..76a9dfdc1c 100644
--- a/board/mithrax/i2c.c
+++ b/board/mithrax/i2c.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/mithrax/keyboard.c b/board/mithrax/keyboard.c
index 6534c7bc63..36830958f5 100644
--- a/board/mithrax/keyboard.c
+++ b/board/mithrax/keyboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -61,145 +61,20 @@ const uint8_t rgbkbd_count = ARRAY_SIZE(rgbkbds);
 const uint8_t rgbkbd_hsize = RGB_GRID0_COL;
 const uint8_t rgbkbd_vsize = RGB_GRID0_ROW;
 
-#define LED(x, y)	RGBKBD_COORD((x), (y))
-#define DELM		RGBKBD_DELM
+enum ec_rgbkbd_type rgbkbd_type;
+#define LED(x, y) RGBKBD_COORD((x), (y))
+#define DELM RGBKBD_DELM
+
 const uint8_t rgbkbd_map[] = {
-	DELM,				/* 0: (null) */
-	LED(0, 0), DELM,		/* 1: ~ ` */
-	LED(0, 0), DELM,		/* 2: ! 1 */
-	LED(0, 0), DELM,		/* 3: @ 2 */
-	LED(0, 0), DELM,		/* 4: # 3 */
-	LED(1, 0), DELM,		/* 5: $ 4 */
-	LED(1, 0), DELM,		/* 6: % 5 */
-	LED(1, 0), DELM,		/* 7: ^ 6 */
-	LED(2, 0), DELM,		/* 8: & 7 */
-	LED(2, 0), DELM,		/* 9: * 8 */
-	LED(2, 0), DELM,		/* 10: ( 9 */
-	LED(2, 0), DELM,		/* 11: ) 0 */
-	LED(2, 0), DELM,		/* 12: _ - */
-	LED(3, 0), DELM,		/* 13: + = */
-	DELM,				/* 14: (null) */
-	LED(3, 0), DELM,		/* 15: backspace */
-	LED(0, 0), DELM,		/* 16: tab */
-	LED(0, 0), DELM,		/* 17: q */
-	LED(0, 0), DELM,		/* 18: w */
-	LED(0, 0), DELM,		/* 19: e */
-	LED(1, 0), DELM,		/* 20: r */
-	LED(1, 0), DELM,		/* 21: t */
-	LED(1, 0), DELM,		/* 22: y */
-	LED(2, 0), DELM,		/* 23: u */
-	LED(2, 0), DELM,		/* 24: i */
-	LED(2, 0), DELM,		/* 25: o */
-	LED(2, 0), DELM,		/* 26: p */
-	LED(2, 0), DELM,		/* 27: [ { */
-	LED(3, 0), DELM,		/* 28: ] } */
-	LED(3, 0), DELM,		/* 29: \ | */
-	LED(0, 0), DELM,		/* 30: caps lock */
-	LED(0, 0), DELM,		/* 31: a */
-	LED(0, 0), DELM,		/* 32: s */
-	LED(0, 0), DELM,		/* 33: d */
-	LED(1, 0), DELM,		/* 34: f */
-	LED(1, 0), DELM,		/* 35: g */
-	LED(1, 0), DELM,		/* 36: h */
-	LED(2, 0), DELM,		/* 37: j */
-	LED(2, 0), DELM,		/* 38: k */
-	LED(2, 0), DELM,		/* 39: l */
-	LED(3, 0), DELM,		/* 40: ; : */
-	LED(3, 0), DELM,		/* 41: " ' */
-	DELM,				/* 42: (null) */
-	LED(3, 0), DELM,		/* 43: enter */
-	LED(0, 0), DELM,		/* 44: L-shift */
-	DELM,				/* 45: (null) */
-	LED(0, 0), DELM,		/* 46: z */
-	LED(0, 0), DELM,		/* 47: x */
-	LED(0, 0), DELM,		/* 48: c */
-	LED(1, 0), DELM,		/* 49: v */
-	LED(1, 0), DELM,		/* 50: b */
-	LED(1, 0), DELM,		/* 51: n */
-	LED(2, 0), DELM,		/* 52: m */
-	LED(2, 0), DELM,		/* 53: , < */
-	LED(2, 0), DELM,		/* 54: . > */
-	LED(3, 0), DELM,		/* 55: / ? */
-	DELM,				/* 56: (null) */
-	LED(3, 0), DELM,		/* 57: R-shift */
-	LED(0, 0), DELM,		/* 58: L-ctrl */
-	LED(3, 0), DELM,		/* 59: power */
-	LED(0, 0), DELM,		/* 60: L-alt */
-	LED(0, 0), LED(1, 0),
-	LED(2, 0), DELM,		/* 61: space */
-	LED(2, 0), DELM,		/* 62: R-alt */
-	DELM,				/* 63: (null) */
-	LED(2, 0), DELM,		/* 64: R-ctrl */
-	DELM,				/* 65: (null) */
-	DELM,				/* 66: (null) */
-	DELM,				/* 67: (null) */
-	DELM,				/* 68: (null) */
-	DELM,				/* 69: (null) */
-	DELM,				/* 70: (null) */
-	DELM,				/* 71: (null) */
-	DELM,				/* 72: (null) */
-	DELM,				/* 73: (null) */
-	DELM,				/* 74: (null) */
-	DELM,				/* 75: (null) */
-	DELM,				/* 76: delete */
-	DELM,				/* 77: (null) */
-	DELM,				/* 78: (null) */
-	LED(3, 0), DELM,		/* 79: left */
-	DELM,				/* 80: home */
-	DELM,				/* 81: end */
-	DELM,				/* 82: (null) */
-	LED(3, 0), DELM,		/* 83: up */
-	LED(3, 0), DELM,		/* 84: down */
-	DELM,				/* 85: page up */
-	DELM,				/* 86: page down */
-	DELM,				/* 87: (null) */
-	DELM,				/* 88: (null) */
-	LED(3, 0), DELM,		/* 89: right */
-	DELM,				/* 90: (null) */
-	DELM,				/* 91: numpad 7 */
-	DELM,				/* 92: numpad 4 */
-	DELM,				/* 93: numpad 1 */
-	DELM,				/* 94: (null) */
-	DELM,				/* 95: numpad / */
-	DELM,				/* 96: numpad 8 */
-	DELM,				/* 97: numpad 5 */
-	DELM,				/* 98: numpad 2 */
-	DELM,				/* 99: numpad 0 */
-	DELM,				/* 100: numpad * */
-	DELM,				/* 101: numpad 9 */
-	DELM,				/* 102: numpad 6 */
-	DELM,				/* 103: numpad 3 */
-	DELM,				/* 104: numpad . */
-	DELM,				/* 105: numpad - */
-	DELM,				/* 106: numpad + */
-	DELM,				/* 107: (null) */
-	DELM,				/* 108: numpad enter */
-	DELM,				/* 109: (null) */
-	LED(0, 0), DELM,		/* 110: esc */
-	LED(0, 0), DELM,		/* T1: back */
-	LED(0, 0), DELM,		/* T2: refresh */
-	LED(1, 0), DELM,		/* T3: full screen */
-	LED(1, 0), DELM,		/* T4: overview */
-	LED(1, 0), DELM,		/* T5: snapshot */
-	LED(2, 0), DELM,		/* T6: brightness down */
-	LED(2, 0), DELM,		/* T7: brightness up */
-	LED(2, 0), DELM,		/* T8: mute */
-	LED(2, 0), DELM,		/* T9: volume down */
-	LED(3, 0), DELM,		/* T10: volume up */
-	DELM,				/* T11: (null) */
-	DELM,				/* T12: (null) */
-	DELM,				/* T13: (null) */
-	DELM,				/* T14: (null) */
-	DELM,				/* T15: (null) */
-	DELM,				/* 126: (null) */
-	DELM,				/* 127: (null) */
+	DELM,	   LED(0, 0), DELM,	 LED(1, 0), DELM,
+	LED(2, 0), DELM,      LED(3, 0), DELM,	    DELM,
 };
 #undef LED
 #undef DELM
 const size_t rgbkbd_map_size = ARRAY_SIZE(rgbkbd_map);
 
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	return &mithrax_kb;
 }
@@ -213,20 +88,20 @@ __override const struct key {
 	uint8_t row;
 	uint8_t col;
 } vivaldi_keys[] = {
-	{.row = 4, .col = 2},	/* T1 */
-	{.row = 3, .col = 2},	/* T2 */
-	{.row = 2, .col = 2},	/* T3 */
-	{.row = 1, .col = 2},	/* T4 */
-	{.row = 4, .col = 4},	/* T5 */
-	{.row = 3, .col = 4},	/* T6 */
-	{.row = 2, .col = 4},	/* T7 */
-	{.row = 2, .col = 9},	/* T8 */
-	{.row = 1, .col = 9},	/* T9 */
-	{.row = 1, .col = 4},	/* T10 */
-	{.row = 0, .col = 4},	/* T11 */
-	{.row = 1, .col = 5},	/* T12 */
-	{.row = 3, .col = 5},	/* T13 */
-	{.row = 2, .col = 1},	/* T14 */
-	{.row = 0, .col = 1},	/* T15 */
+	{ .row = 4, .col = 2 }, /* T1 */
+	{ .row = 3, .col = 2 }, /* T2 */
+	{ .row = 2, .col = 2 }, /* T3 */
+	{ .row = 1, .col = 2 }, /* T4 */
+	{ .row = 4, .col = 4 }, /* T5 */
+	{ .row = 3, .col = 4 }, /* T6 */
+	{ .row = 2, .col = 4 }, /* T7 */
+	{ .row = 2, .col = 9 }, /* T8 */
+	{ .row = 1, .col = 9 }, /* T9 */
+	{ .row = 1, .col = 4 }, /* T10 */
+	{ .row = 0, .col = 4 }, /* T11 */
+	{ .row = 1, .col = 5 }, /* T12 */
+	{ .row = 3, .col = 5 }, /* T13 */
+	{ .row = 2, .col = 1 }, /* T14 */
+	{ .row = 0, .col = 1 }, /* T15 */
 };
 BUILD_ASSERT(ARRAY_SIZE(vivaldi_keys) == MAX_TOP_ROW_KEYS);
diff --git a/board/mithrax/keyboard_customization.c b/board/mithrax/keyboard_customization.c
index 4e45de34be..cc3623390f 100644
--- a/board/mithrax/keyboard_customization.c
+++ b/board/mithrax/keyboard_customization.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The ChromiumOS Authors.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,24 +12,23 @@
 #include "keyboard_raw.h"
 
 static uint16_t scancode_set2[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = {
-	{0x0000, 0x0000, 0x0014, 0xe01f, 0xe014, 0x0000, 0x0000, 0x0000},
-	{0x001f, 0x0076, 0x0017, 0x000e, 0x001c, 0x003a, 0x000d, 0x0016},
-	{0x006c, 0xe024, 0xe01d, 0xe020, 0xe038, 0xe071, 0x0026, 0x002a},
-	{0x0032, 0x0034, 0x002c, 0x002e, 0x002b, 0x0029, 0x0025, 0x002d},
-	{0x0078, 0xe032, 0xe035, 0xe02c, 0xe02d, 0x0041, 0x001e, 0x001d},
-	{0x0051, 0x0007, 0x005b, 0x000f, 0x0042, 0x0022, 0x003e, 0x0043},
-	{0x0031, 0x0033, 0x0035, 0x0036, 0x003b, 0x001b, 0x003d, 0x003c},
-	{0x0000, 0x0012, 0x0061, 0x0000, 0x0000, 0x0000, 0x0000, 0x0059},
-	{0x0055, 0x0052, 0x0054, 0x004e, 0x004c, 0x0024, 0x0044, 0x004d},
-	{0x0045, 0xe021, 0xe023, 0x002f, 0x004b, 0x0049, 0x0046, 0x001a},
-	{0xe011, 0x0000, 0x006a, 0x0000, 0x005d, 0x0000, 0x0011, 0x0000},
-	{0xe07a, 0x005d, 0xe075, 0x006b, 0x005a, 0xe072, 0x004a, 0x0066},
-	{0xe06b, 0xe074, 0xe069, 0x0067, 0xe06c, 0x0064, 0x0015, 0xe07d},
-	{0x0073, 0x007c, 0x007b, 0x0074, 0x0071, 0xe04a, 0x0070, 0x0021},
-	{0x0023, 0xe05a, 0x0075, 0x0079, 0x007a, 0x0072, 0x007d, 0x0069},
+	{ 0x0000, 0x0000, 0x0014, 0xe01f, 0xe014, 0x0000, 0x0000, 0x0000 },
+	{ 0x001f, 0x0076, 0x0017, 0x000e, 0x001c, 0x003a, 0x000d, 0x0016 },
+	{ 0x006c, 0xe024, 0xe01d, 0xe020, 0xe038, 0xe071, 0x0026, 0x002a },
+	{ 0x0032, 0x0034, 0x002c, 0x002e, 0x002b, 0x0029, 0x0025, 0x002d },
+	{ 0x0078, 0xe032, 0xe035, 0xe02c, 0xe02d, 0x0041, 0x001e, 0x001d },
+	{ 0x0051, 0x0007, 0x005b, 0x000f, 0x0042, 0x0022, 0x003e, 0x0043 },
+	{ 0x0031, 0x0033, 0x0035, 0x0036, 0x003b, 0x001b, 0x003d, 0x003c },
+	{ 0x0000, 0x0012, 0x0061, 0x0000, 0x0000, 0x0000, 0x0000, 0x0059 },
+	{ 0x0055, 0x0052, 0x0054, 0x004e, 0x004c, 0x0024, 0x0044, 0x004d },
+	{ 0x0045, 0xe021, 0xe023, 0x002f, 0x004b, 0x0049, 0x0046, 0x001a },
+	{ 0xe011, 0x0000, 0x006a, 0x0000, 0x005d, 0x0000, 0x0011, 0x0000 },
+	{ 0xe07a, 0x005d, 0xe075, 0x006b, 0x005a, 0xe072, 0x004a, 0x0066 },
+	{ 0xe06b, 0xe074, 0xe069, 0x0067, 0xe06c, 0x0064, 0x0015, 0xe07d },
+	{ 0x0073, 0x007c, 0x007b, 0x0074, 0x0071, 0xe04a, 0x0070, 0x0021 },
+	{ 0x0023, 0xe05a, 0x0075, 0x0079, 0x007a, 0x0072, 0x007d, 0x0069 },
 };
 
-
 uint16_t get_scancode_set2(uint8_t row, uint8_t col)
 {
 	if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS)
@@ -64,38 +63,30 @@ void board_keyboard_drive_col(int col)
 
 #ifdef CONFIG_KEYBOARD_DEBUG
 static char keycap_label[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = {
-	{'c',        KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
-		KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO},
-	{KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
-		KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO},
-	{'q',        KLLI_UNKNO, KLLI_UNKNO, KLLI_TAB,   '`',
-		'1',        KLLI_UNKNO, 'a'},
-	{KLLI_R_ALT, KLLI_L_ALT, KLLI_UNKNO, KLLI_UNKNO,
-		KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO},
-	{KLLI_UNKNO, KLLI_SPACE, 'e',        KLLI_F4,
-		KLLI_SEARC, '3',        KLLI_F3,    KLLI_UNKNO},
-	{'x',        'z',        KLLI_F2,    KLLI_F1,
-		's',        '2',        'w',        KLLI_ESC},
-	{'v',        'b',        'g',        't',
-		'5',        '4',        'r',        'f'},
-	{'m',        'n',        'h',        'y',
-		'6',        '7',        'u',        'j'},
-	{'.',        KLLI_DOWN,  '\\',       'o',
-		KLLI_F10,   '9',        KLLI_UNKNO, 'l'},
-	{KLLI_R_SHT, KLLI_L_SHT, KLLI_UNKNO, KLLI_UNKNO,
-		KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO},
-	{',',        KLLI_UNKNO, KLLI_F7,    KLLI_F6,
-		KLLI_F5,    '8',        'i',        'k'},
-	{KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_F9,
-		KLLI_UNKNO, KLLI_UNKNO, KLLI_LEFT,  KLLI_UNKNO},
-	{KLLI_R_CTR, KLLI_L_CTR, KLLI_UNKNO, KLLI_UNKNO,
-		KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO},
-	{'/',        KLLI_UP,    '-',        KLLI_UNKNO,
-		'0',        'p',        '[',        ';'},
-	{'\'',       KLLI_ENTER, KLLI_UNKNO, KLLI_UNKNO,
-		'=',        KLLI_B_SPC, ']',        'd'},
-	{KLLI_UNKNO, KLLI_F8,    KLLI_RIGHT, KLLI_UNKNO,
-		KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO},
+	{ 'c', KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO },
+	{ KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO },
+	{ 'q', KLLI_UNKNO, KLLI_UNKNO, KLLI_TAB, '`', '1', KLLI_UNKNO, 'a' },
+	{ KLLI_R_ALT, KLLI_L_ALT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO },
+	{ KLLI_UNKNO, KLLI_SPACE, 'e', KLLI_F4, KLLI_SEARC, '3', KLLI_F3,
+	  KLLI_UNKNO },
+	{ 'x', 'z', KLLI_F2, KLLI_F1, 's', '2', 'w', KLLI_ESC },
+	{ 'v', 'b', 'g', 't', '5', '4', 'r', 'f' },
+	{ 'm', 'n', 'h', 'y', '6', '7', 'u', 'j' },
+	{ '.', KLLI_DOWN, '\\', 'o', KLLI_F10, '9', KLLI_UNKNO, 'l' },
+	{ KLLI_R_SHT, KLLI_L_SHT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO },
+	{ ',', KLLI_UNKNO, KLLI_F7, KLLI_F6, KLLI_F5, '8', 'i', 'k' },
+	{ KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_F9, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_LEFT, KLLI_UNKNO },
+	{ KLLI_R_CTR, KLLI_L_CTR, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO },
+	{ '/', KLLI_UP, '-', KLLI_UNKNO, '0', 'p', '[', ';' },
+	{ '\'', KLLI_ENTER, KLLI_UNKNO, KLLI_UNKNO, '=', KLLI_B_SPC, ']', 'd' },
+	{ KLLI_UNKNO, KLLI_F8, KLLI_RIGHT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO },
 };
 
 char get_keycap_label(uint8_t row, uint8_t col)
diff --git a/board/mithrax/keyboard_customization.h b/board/mithrax/keyboard_customization.h
index b177a11eb4..1d0e6ec483 100644
--- a/board/mithrax/keyboard_customization.h
+++ b/board/mithrax/keyboard_customization.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The ChromiumOS Authors.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,47 +25,47 @@ extern uint8_t keyboard_cols;
 #define KEYBOARD_ROW_TO_MASK(r) (1 << (r))
 
 /* Columns and masks for keys we particularly care about */
-#define KEYBOARD_COL_DOWN	11
-#define KEYBOARD_ROW_DOWN	5
-#define KEYBOARD_MASK_DOWN	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_DOWN)
-#define KEYBOARD_COL_ESC	1
-#define KEYBOARD_ROW_ESC	1
-#define KEYBOARD_MASK_ESC	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_ESC)
-#define KEYBOARD_COL_KEY_H	6
-#define KEYBOARD_ROW_KEY_H	1
-#define KEYBOARD_MASK_KEY_H	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_H)
-#define KEYBOARD_COL_KEY_R	3
-#define KEYBOARD_ROW_KEY_R	7
-#define KEYBOARD_MASK_KEY_R	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_R)
-#define KEYBOARD_COL_LEFT_ALT	10
-#define KEYBOARD_ROW_LEFT_ALT	6
-#define KEYBOARD_MASK_LEFT_ALT	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_ALT)
-#define KEYBOARD_COL_REFRESH	2
-#define KEYBOARD_ROW_REFRESH	3
-#define KEYBOARD_MASK_REFRESH	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_REFRESH)
-#define KEYBOARD_COL_RIGHT_ALT	10
-#define KEYBOARD_ROW_RIGHT_ALT	0
-#define KEYBOARD_MASK_RIGHT_ALT	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_ALT)
-#define KEYBOARD_DEFAULT_COL_VOL_UP	4
-#define KEYBOARD_DEFAULT_ROW_VOL_UP	1
-#define KEYBOARD_COL_LEFT_CTRL  0
-#define KEYBOARD_ROW_LEFT_CTRL  2
+#define KEYBOARD_COL_DOWN 11
+#define KEYBOARD_ROW_DOWN 5
+#define KEYBOARD_MASK_DOWN KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_DOWN)
+#define KEYBOARD_COL_ESC 1
+#define KEYBOARD_ROW_ESC 1
+#define KEYBOARD_MASK_ESC KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_ESC)
+#define KEYBOARD_COL_KEY_H 6
+#define KEYBOARD_ROW_KEY_H 1
+#define KEYBOARD_MASK_KEY_H KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_H)
+#define KEYBOARD_COL_KEY_R 3
+#define KEYBOARD_ROW_KEY_R 7
+#define KEYBOARD_MASK_KEY_R KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_R)
+#define KEYBOARD_COL_LEFT_ALT 10
+#define KEYBOARD_ROW_LEFT_ALT 6
+#define KEYBOARD_MASK_LEFT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_ALT)
+#define KEYBOARD_COL_REFRESH 2
+#define KEYBOARD_ROW_REFRESH 3
+#define KEYBOARD_MASK_REFRESH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_REFRESH)
+#define KEYBOARD_COL_RIGHT_ALT 10
+#define KEYBOARD_ROW_RIGHT_ALT 0
+#define KEYBOARD_MASK_RIGHT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_ALT)
+#define KEYBOARD_DEFAULT_COL_VOL_UP 4
+#define KEYBOARD_DEFAULT_ROW_VOL_UP 1
+#define KEYBOARD_COL_LEFT_CTRL 0
+#define KEYBOARD_ROW_LEFT_CTRL 2
 #define KEYBOARD_MASK_LEFT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_CTRL)
 #define KEYBOARD_COL_RIGHT_CTRL 0
 #define KEYBOARD_ROW_RIGHT_CTRL 4
 #define KEYBOARD_MASK_RIGHT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_CTRL)
-#define KEYBOARD_COL_SEARCH     0
-#define KEYBOARD_ROW_SEARCH     3
-#define KEYBOARD_MASK_SEARCH    KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_SEARCH)
-#define KEYBOARD_COL_KEY_0      9
-#define KEYBOARD_ROW_KEY_0      0
-#define KEYBOARD_MASK_KEY_0     KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_0)
-#define KEYBOARD_COL_KEY_1      1
-#define KEYBOARD_ROW_KEY_1      7
-#define KEYBOARD_MASK_KEY_1     KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_1)
-#define KEYBOARD_COL_KEY_2      4
-#define KEYBOARD_ROW_KEY_2      6
-#define KEYBOARD_MASK_KEY_2     KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_2)
+#define KEYBOARD_COL_SEARCH 0
+#define KEYBOARD_ROW_SEARCH 3
+#define KEYBOARD_MASK_SEARCH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_SEARCH)
+#define KEYBOARD_COL_KEY_0 9
+#define KEYBOARD_ROW_KEY_0 0
+#define KEYBOARD_MASK_KEY_0 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_0)
+#define KEYBOARD_COL_KEY_1 1
+#define KEYBOARD_ROW_KEY_1 7
+#define KEYBOARD_MASK_KEY_1 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_1)
+#define KEYBOARD_COL_KEY_2 4
+#define KEYBOARD_ROW_KEY_2 6
+#define KEYBOARD_MASK_KEY_2 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_2)
 #define KEYBOARD_COL_LEFT_SHIFT 7
 #define KEYBOARD_ROW_LEFT_SHIFT 1
 #define KEYBOARD_MASK_LEFT_SHIFT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_SHIFT)
diff --git a/board/mithrax/led.c b/board/mithrax/led.c
index 5abaed2a25..660fc8ce2d 100644
--- a/board/mithrax/led.c
+++ b/board/mithrax/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,26 +11,33 @@
 #include "led_onoff_states.h"
 #include "system.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
 __override const int led_charge_lvl_1;
-__override const int led_charge_lvl_2 = 94;
+__override const int led_charge_lvl_2 = 95;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF, 3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF, 3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF, 1 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_WHITE,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+	};
 
 const enum ec_led_id supported_led_ids[] = {
 	EC_LED_ID_BATTERY_LED,
diff --git a/board/mithrax/pwm.c b/board/mithrax/pwm.c
index ffc90e910a..8f3759316e 100644
--- a/board/mithrax/pwm.c
+++ b/board/mithrax/pwm.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/mithrax/sensors.c b/board/mithrax/sensors.c
index fff002dda6..b72022a0e0 100644
--- a/board/mithrax/sensors.c
+++ b/board/mithrax/sensors.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -46,18 +46,14 @@ K_MUTEX_DEFINE(g_base_accel_mutex);
 static struct stprivate_data g_lis2dw12_data;
 static struct lsm6dso_data lsm6dso_data;
 
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(1), 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
 
 /* TODO(b/184779743): verify orientation matrix */
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, FLOAT_TO_FP(-1), 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
@@ -146,24 +142,18 @@ DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_INIT_I2C + 1);
 
 /* Temperature sensor configuration */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1_DDR_SOC] = {
-		.name = "DDR and SOC",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_1_DDR_SOC
-	},
-	[TEMP_SENSOR_2_FAN] = {
-		.name = "FAN",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_2_FAN
-	},
-	[TEMP_SENSOR_3_CHARGER] = {
-		.name = "Charger",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_3_CHARGER
-	},
+	[TEMP_SENSOR_1_DDR_SOC] = { .name = "DDR and SOC",
+				    .type = TEMP_SENSOR_TYPE_BOARD,
+				    .read = get_temp_3v3_30k9_47k_4050b,
+				    .idx = ADC_TEMP_SENSOR_1_DDR_SOC },
+	[TEMP_SENSOR_2_FAN] = { .name = "FAN",
+				.type = TEMP_SENSOR_TYPE_BOARD,
+				.read = get_temp_3v3_30k9_47k_4050b,
+				.idx = ADC_TEMP_SENSOR_2_FAN },
+	[TEMP_SENSOR_3_CHARGER] = { .name = "Charger",
+				    .type = TEMP_SENSOR_TYPE_BOARD,
+				    .read = get_temp_3v3_30k9_47k_4050b,
+				    .idx = ADC_TEMP_SENSOR_3_CHARGER },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -177,8 +167,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CPU \
-	{ \
+#define THERMAL_CPU              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
@@ -207,8 +197,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_FAN \
-	{ \
+#define THERMAL_FAN              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(60), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(70), \
@@ -221,8 +211,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 	}
 __maybe_unused static const struct ec_thermal_config thermal_fan = THERMAL_FAN;
 
-#define THERMAL_CHARGER \
-	{ \
+#define THERMAL_CHARGER          \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
diff --git a/board/mithrax/usbc_config.c b/board/mithrax/usbc_config.c
index b1b28ab7c2..10189bbf50 100644
--- a/board/mithrax/usbc_config.c
+++ b/board/mithrax/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -33,8 +33,8 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 /* USBC TCPC configuration */
 struct tcpc_config_t tcpc_config[] = {
@@ -63,17 +63,6 @@ struct tcpc_config_t tcpc_config[] = {
 BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
 BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
 
-struct tcpc_config_t tcpc_config_c1 = {
-	.bus_type = EC_BUS_TYPE_I2C,
-	.i2c_info = {
-		.port = I2C_PORT_USB_C1_TCPC,
-		.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-	},
-	.drv = &nct38xx_tcpm_drv,
-	.flags = TCPC_FLAGS_TCPCI_REV2_0 |
-		TCPC_FLAGS_NO_DEBUG_ACC_CONTROL,
-};
-
 /* USBC PPC configuration */
 struct ppc_config_t ppc_chips[] = {
 	[USBC_PORT_C2] = {
@@ -92,71 +81,40 @@ BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
 
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
-struct ppc_config_t ppc_chips_c1 = {
-	.i2c_port = I2C_PORT_USB_C1_PPC,
-	.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-	.drv = &syv682x_drv,
-};
-
-/* USBC mux configuration - Alder Lake includes internal mux */
-static const struct usb_mux usbc2_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C2,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-
-static const struct usb_mux usbc1_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-
 /*
  * USB3 DB mux configuration - the top level mux still needs to be set
  * to the virtual_usb_mux_driver so the AP gets notified of mux changes
  * and updates the TCSS configuration on state changes.
  */
-static const struct usb_mux usbc1_usb3_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+static const struct usb_mux_chain usbc1_usb3_db_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 };
 
-struct usb_mux usb_muxes[] = {
+struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C2] = {
-		.usb_port = USBC_PORT_C2,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C2,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 	},
 	[USBC_PORT_C1] = {
-		/* PS8815 DB */
-		.usb_port = USBC_PORT_C1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc1_usb3_db_retimer,
+		.mux = &(const struct usb_mux) {
+			/* PS8815 DB */
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc1_usb3_db_retimer,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
 
-static const struct usb_mux usb_muxes_c1 = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C1_MUX,
-		.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc1_tcss_usb_mux,
-};
-
-static const struct usb_mux usb_muxes_c2 = {
-		.usb_port = USBC_PORT_C2,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C2_MUX,
-		.i2c_addr_flags = USBC_PORT_C2_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc2_tcss_usb_mux,
-};
-
-
 /* BC1.2 charger detect configuration */
 const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
 	[USBC_PORT_C2] = {
@@ -251,10 +209,6 @@ void board_reset_pd_mcu(void)
 	gpio_set_level(GPIO_USB_C0_C2_TCPC_RST_ODL, 0);
 	gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 0);
 
-	if (ec_cfg_usb_db_type() == DB_USB4_NCT3807)
-		gpio_set_level(GPIO_USB_C1_RST_ODL, 0);
-
-
 	/*
 	 * delay for power-on to reset-off and min. assertion time
 	 */
@@ -264,9 +218,6 @@ void board_reset_pd_mcu(void)
 	gpio_set_level(GPIO_USB_C0_C2_TCPC_RST_ODL, 1);
 	gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 1);
 
-	if (ec_cfg_usb_db_type() == DB_USB4_NCT3807)
-		gpio_set_level(GPIO_USB_C1_RST_ODL, 1);
-
 	/* wait for chips to come up */
 
 	msleep(50);
@@ -288,8 +239,6 @@ static void board_tcpc_init(void)
 		 * C0/C2 TCPC, so they must be set up after the TCPC has
 		 * been taken out of reset.
 		 */
-		if (ec_cfg_usb_db_type() == DB_USB4_NCT3807)
-			enable_ioex(IOEX_C1_NCT38XX);
 		enable_ioex(IOEX_C2_NCT38XX);
 	}
 
@@ -361,14 +310,7 @@ void ppc_interrupt(enum gpio_signal signal)
 {
 	switch (signal) {
 	case GPIO_USB_C1_PPC_INT_ODL:
-		switch (ec_cfg_usb_db_type()) {
-		case DB_USB3_PS8815:
-			nx20p348x_interrupt(USBC_PORT_C1);
-			break;
-		case DB_USB4_NCT3807:
-			syv682x_interrupt(USBC_PORT_C1);
-			break;
-		}
+		nx20p348x_interrupt(USBC_PORT_C1);
 		break;
 	case GPIO_USB_C2_PPC_INT_ODL:
 		syv682x_interrupt(USBC_PORT_C2);
@@ -392,12 +334,6 @@ __override bool board_is_dts_port(int port)
 
 __override bool board_is_tbt_usb4_port(int port)
 {
-	if (((port == USBC_PORT_C2) &&
-		(ec_cfg_usb_mb_type() == MB_USB4_TBT)) ||
-		((port == USBC_PORT_C1) &&
-		(ec_cfg_usb_db_type() == DB_USB4_NCT3807)))
-		return true;
-
 	return false;
 }
 
@@ -408,15 +344,3 @@ __override enum tbt_compat_cable_speed board_get_max_tbt_speed(int port)
 
 	return TBT_SS_TBT_GEN3;
 }
-
-void db_update_usb4_config_from_config(void)
-{
-	tcpc_config[USBC_PORT_C1] = tcpc_config_c1;
-	ppc_chips[USBC_PORT_C1] = ppc_chips_c1;
-	usb_muxes[USBC_PORT_C1] = usb_muxes_c1;
-}
-
-void mb_update_usb4_tbt_config_from_config(void)
-{
-	usb_muxes[USBC_PORT_C2] = usb_muxes_c2;
-}
diff --git a/board/mithrax/usbc_config.h b/board/mithrax/usbc_config.h
index aaf1d02b10..22242d7c5b 100644
--- a/board/mithrax/usbc_config.h
+++ b/board/mithrax/usbc_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,18 +8,12 @@
 #ifndef __CROS_EC_USBC_CONFIG_H
 #define __CROS_EC_USBC_CONFIG_H
 
-#define CONFIG_USB_PD_PORT_MAX_COUNT	2
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
 #define CONFIG_USB_PD_TCPC_RUNTIME_CONFIG
 #define CONFIG_USB_MUX_RUNTIME_CONFIG
 
-enum usbc_port {
-	USBC_PORT_C2 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C2 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 void config_usb_db_type(void);
-void db_update_usb4_config_from_config(void);
-void mb_update_usb4_tbt_config_from_config(void);
 
 #endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/moli/board.c b/board/moli/board.c
index 4a6445a8d6..acc12f9831 100644
--- a/board/moli/board.c
+++ b/board/moli/board.c
@@ -1,10 +1,10 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "adc.h"
-#include "assert.h"
+#include "builtin/assert.h"
 #include "button.h"
 #include "charge_manager.h"
 #include "charge_state_v2.h"
@@ -24,8 +24,8 @@
 #include "usbc_ppc.h"
 
 /* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 static void power_monitor(void);
 DECLARE_DEFERRED(power_monitor);
@@ -124,13 +124,11 @@ static const struct {
 	int current;
 } bj_power[] = {
 	{ /* 0 - 90W (also default) */
-	.voltage = 19000,
-	.current = 4740
-	},
+	  .voltage = 19000,
+	  .current = 4740 },
 	{ /* 1 - 135W */
-	.voltage = 19000,
-	.current = 6920
-	},
+	  .voltage = 19500,
+	  .current = 6920 },
 };
 
 static unsigned int ec_config_get_bj_power(void)
@@ -146,7 +144,7 @@ static unsigned int ec_config_get_bj_power(void)
 	return bj;
 }
 
-#define ADP_DEBOUNCE_MS		1000  /* Debounce time for BJ plug/unplug */
+#define ADP_DEBOUNCE_MS 1000 /* Debounce time for BJ plug/unplug */
 /* Debounced connection state of the barrel jack */
 static int8_t adp_connected = -1;
 static void adp_connect_deferred(void)
@@ -249,25 +247,25 @@ void board_overcurrent_event(int port, int is_overcurrented)
  *
  *  All measurements are in milliwatts.
  */
-#define THROT_TYPE_A_FRONT  BIT(0)
-#define THROT_TYPE_A_REAR   BIT(1)
-#define THROT_TYPE_C0       BIT(2)
-#define THROT_TYPE_C1       BIT(3)
-#define THROT_PROCHOT       BIT(5)
+#define THROT_TYPE_A_FRONT BIT(0)
+#define THROT_TYPE_A_REAR BIT(1)
+#define THROT_TYPE_C0 BIT(2)
+#define THROT_TYPE_C1 BIT(3)
+#define THROT_PROCHOT BIT(5)
 
 /*
  * Power gain if front USB A ports are limited.
  */
-#define POWER_GAIN_TYPE_A	3200
+#define POWER_GAIN_TYPE_A 3200
 /*
  * Power gain if Type C port is limited.
  */
-#define POWER_GAIN_TYPE_C	8800
+#define POWER_GAIN_TYPE_C 8800
 /*
  * Power is averaged over 10 ms, with a reading every 2 ms.
  */
-#define POWER_DELAY_MS		2
-#define POWER_READINGS		(10/POWER_DELAY_MS)
+#define POWER_DELAY_MS 2
+#define POWER_READINGS (10 / POWER_DELAY_MS)
 
 #include "gpio_list.h" /* Must come after other header files. */
 
@@ -283,8 +281,7 @@ static void power_monitor(void)
 	 * If CPU is off or suspended, no need to throttle
 	 * or restrict power.
 	 */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF |
-			     CHIPSET_STATE_SUSPEND)) {
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF | CHIPSET_STATE_SUSPEND)) {
 		/*
 		 * Slow down monitoring, assume no throttling required.
 		 */
@@ -312,7 +309,7 @@ static void power_monitor(void)
 			 */
 			power = (adc_read_channel(ADC_VBUS) *
 				 adc_read_channel(ADC_PPVAR_IMON)) /
-				 1000;
+				1000;
 			/* Init power table */
 			if (history[0] == 0) {
 				for (i = 0; i < POWER_READINGS; i++)
@@ -339,8 +336,7 @@ static void power_monitor(void)
 			 * For barrel-jack supplies, the rating can be
 			 * exceeded briefly, so use the average.
 			 */
-			if (charge_manager_get_supplier() ==
-			    CHARGE_SUPPLIER_PD)
+			if (charge_manager_get_supplier() == CHARGE_SUPPLIER_PD)
 				power = max;
 			else
 				power = total / POWER_READINGS;
@@ -403,16 +399,18 @@ static void power_monitor(void)
 		gpio_set_level(GPIO_EC_PROCHOT_ODL, prochot);
 	}
 	if (diff & THROT_TYPE_C0) {
-		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C0)
-			? TYPEC_RP_1A5 : TYPEC_RP_3A0;
+		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C0) ?
+						TYPEC_RP_1A5 :
+						TYPEC_RP_3A0;
 
 		ppc_set_vbus_source_current_limit(0, rp);
 		tcpm_select_rp_value(0, rp);
 		pd_update_contract(0);
 	}
 	if (diff & THROT_TYPE_C1) {
-		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C1)
-			? TYPEC_RP_1A5 : TYPEC_RP_3A0;
+		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C1) ?
+						TYPEC_RP_1A5 :
+						TYPEC_RP_3A0;
 
 		ppc_set_vbus_source_current_limit(1, rp);
 		tcpm_select_rp_value(1, rp);
diff --git a/board/moli/board.h b/board/moli/board.h
index 50744db067..ddd86c4e35 100644
--- a/board/moli/board.h
+++ b/board/moli/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,11 +21,11 @@
 /* HDMI CEC */
 #define CONFIG_CEC
 #define CEC_GPIO_OUT GPIO_HDMI_CEC_OUT
-#define CEC_GPIO_IN  GPIO_HDMI_CEC_IN
+#define CEC_GPIO_IN GPIO_HDMI_CEC_IN
 #define CEC_GPIO_PULL_UP GPIO_HDMI_CEC_PULL_UP
 
 /* USB Type A Features */
-#define USB_PORT_COUNT			4
+#define USB_PORT_COUNT 4
 #define CONFIG_USB_PORT_POWER_DUMB
 
 /* USB Type C and USB PD defines */
@@ -33,7 +33,7 @@
 
 #define CONFIG_IO_EXPANDER
 #define CONFIG_IO_EXPANDER_NCT38XX
-#define CONFIG_IO_EXPANDER_PORT_COUNT		2
+#define CONFIG_IO_EXPANDER_PORT_COUNT 2
 
 #define CONFIG_USB_PD_PPC
 #define CONFIG_USBC_RETIMER_INTEL_BB
@@ -43,18 +43,18 @@
 #define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_5_50
 
 /* TODO: b/177608416 - measure and check these values on brya */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
 
 /* The design should support up to 100W. */
 /* TODO(b/197702356): Set the max PD to 60W now and change it
  * to 100W after we verify it.
  */
-#define PD_OPERATING_POWER_MW	CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
-#define PD_MAX_POWER_MW		100000
-#define PD_MAX_CURRENT_MA	5000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
+#define PD_MAX_POWER_MW 100000
+#define PD_MAX_CURRENT_MA 5000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /*
  * Macros for GPIO signals used in common code that don't match the
@@ -62,59 +62,60 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_PACKET_MODE_EN		GPIO_EC_GSC_PACKET_MODE
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SYS_SLP_S0IX_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_TEMP_SENSOR_POWER		GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
 
 /*
  * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
  * signal.
  */
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_SEQ_EC_ALL_SYS_PG
-#define GPIO_PG_EC_DSW_PWROK		GPIO_SEQ_EC_DSW_PWROK
-#define GPIO_PG_EC_RSMRST_ODL		GPIO_SEQ_EC_RSMRST_ODL
-#define GPIO_POWER_BUTTON_L		GPIO_GSC_EC_PWR_BTN_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_ODL
-#define GPIO_RECOVERY_L			GPIO_EC_RECOVERY_BTN_ODL
-#define GPIO_RECOVERY_L_2		GPIO_GSC_EC_RECOVERY_BTN_ODL
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
+#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_ODL
+#define GPIO_RECOVERY_L_2 GPIO_GSC_EC_RECOVERY_BTN_ODL
 
 /* I2C Bus Configuration */
 
-#define I2C_PORT_USB_C0_C1_TCPC		NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C0_C1_TCPC NPCX_I2C_PORT1_0
 
-#define I2C_PORT_USB_C0_C1_PPC		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_A0_A1_MIX		NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C0_C1_PPC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_A0_A1_MIX NPCX_I2C_PORT6_1
 
-#define I2C_PORT_USB_C0_C1_BC12		NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C0_C1_BC12 NPCX_I2C_PORT2_0
 
-#define I2C_PORT_USB_C0_C1_MUX		NPCX_I2C_PORT3_0
+#define I2C_PORT_USB_C0_C1_MUX NPCX_I2C_PORT3_0
 
-#define I2C_PORT_QI			NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM			NPCX_I2C_PORT7_0
-#define I2C_PORT_MP2964			NPCX_I2C_PORT7_0
+#define I2C_PORT_QI NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0
 
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 
-#define I2C_ADDR_MP2964_FLAGS	0x20
+#define I2C_ADDR_MP2964_FLAGS 0x20
 
-#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR	0x56
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x57
+#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x56
+#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x57
 
 /* Enabling Thunderbolt-compatible mode */
 #define CONFIG_USB_PD_TBT_COMPAT_MODE
 
 /* Enabling USB4 mode */
 #define CONFIG_USB_PD_USB4
+#define CONFIG_USB_PD_DATA_RESET_MSG
 
 /* Retimer */
 #define CONFIG_USBC_RETIMER_FW_UPDATE
@@ -129,15 +130,16 @@
 #define CONFIG_ADC
 
 /* Fan */
-#define CONFIG_FANS			FAN_CH_COUNT
-#define RPM_DEVIATION		1
+#define CONFIG_FANS FAN_CH_COUNT
+#define RPM_DEVIATION 1
+#define CONFIG_CUSTOM_FAN_CONTROL
 
 /* Include math_util for bitmask_uint64 used in pd_timers */
 #define CONFIG_MATH_UTIL
 
 #ifndef __ASSEMBLER__
 
-#include "gpio_signal.h"	/* needed by registers.h */
+#include "gpio_signal.h" /* needed by registers.h */
 #include "registers.h"
 #include "usbc_config.h"
 
@@ -153,7 +155,7 @@ enum adc_channel {
 	ADC_TEMP_SENSOR_2_CPU_VR,
 	ADC_TEMP_SENSOR_4_DIMM,
 	ADC_VBUS,
-	ADC_PPVAR_IMON,              /* ADC3 */
+	ADC_PPVAR_IMON, /* ADC3 */
 	ADC_CH_COUNT
 };
 
@@ -164,28 +166,18 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum ioex_port {
-	IOEX_C0_NCT38XX = 0,
-	IOEX_C1_NCT38XX,
-	IOEX_PORT_COUNT
-};
+enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_C1_NCT38XX, IOEX_PORT_COUNT };
 
 enum pwm_channel {
-	PWM_CH_LED_AMBER,		/* PWM0 */
-	PWM_CH_FAN,                     /* PWM5 */
-	PWM_CH_LED_BLUE,                /* PWM2 */
+	PWM_CH_LED_AMBER, /* PWM0 */
+	PWM_CH_FAN, /* PWM5 */
+	PWM_CH_LED_BLUE, /* PWM2 */
 	PWM_CH_COUNT
 };
 
-enum fan_channel {
-	FAN_CH_0 = 0,
-	FAN_CH_COUNT
-};
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT };
 
-enum mft_channel {
-	MFT_CH_0 = 0,
-	MFT_CH_COUNT
-};
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT };
 
 /*
  * firmware config fields
@@ -193,8 +185,8 @@ enum mft_channel {
 /*
  * Barrel-jack power (2 bits).
  */
-#define EC_CFG_BJ_POWER_L		0
-#define EC_CFG_BJ_POWER_H		1
+#define EC_CFG_BJ_POWER_L 0
+#define EC_CFG_BJ_POWER_H 1
 #define EC_CFG_BJ_POWER_MASK GENMASK(EC_CFG_BJ_POWER_H, EC_CFG_BJ_POWER_L)
 
 extern void adp_connect_interrupt(enum gpio_signal signal);
diff --git a/board/moli/build.mk b/board/moli/build.mk
index 00fc2723cd..4897d446b2 100644
--- a/board/moli/build.mk
+++ b/board/moli/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -18,4 +18,5 @@ board-y+=i2c.o
 board-y+=led.o
 board-y+=pwm.o
 board-y+=sensors.o
+board-y+=thermal.o
 board-y+=usbc_config.o
diff --git a/board/moli/ec.tasklist b/board/moli/ec.tasklist
index f51cbddd1b..2fda1cfb5e 100644
--- a/board/moli/ec.tasklist
+++ b/board/moli/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/moli/fans.c b/board/moli/fans.c
index f2a70636d0..7ad99d4af1 100644
--- a/board/moli/fans.c
+++ b/board/moli/fans.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,21 +25,15 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 static const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
 
-/*
- * TOOD(b/197478860): need to update for real fan
- *
- * Prototype fan spins at about 7200 RPM at 100% PWM.
- * Set minimum at around 30% PWM.
- */
 static const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 2200,
-	.rpm_start = 2200,
-	.rpm_max = 7200,
+	.rpm_min = 1500,
+	.rpm_start = 1500,
+	.rpm_max = 5200,
 };
 
 const struct fan_t fans[FAN_CH_COUNT] = {
diff --git a/board/moli/gpio.inc b/board/moli/gpio.inc
index 21336f6245..fb3b508573 100644
--- a/board/moli/gpio.inc
+++ b/board/moli/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2022 The Chromium OS Authors. All rights reserved.
+ * Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -115,6 +115,10 @@ GPIO(USB_C0_C1_TCPC_RST_ODL,         PIN(F, 5), GPIO_ODR_LOW)
 /* LAN */
 GPIO(LAN_PWR_GOOD,                   PIN(0, 2), GPIO_INPUT)
 
+/* LED */
+GPIO(LED_ORANGE_CONTROL,             PIN(3, 1), GPIO_ODR_LOW)
+GPIO(LED_BLUE_CONTROL,               PIN(2, 5), GPIO_ODR_LOW)
+
 /* Option Board */
 GPIO(HDMI1_MONITOR_ON,               PIN(B, 4), GPIO_INPUT)
 GPIO(HDMI1_MONON_SIO,                PIN(1, 6), GPIO_ODR_LOW)
@@ -153,7 +157,6 @@ ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0)               /* GPIOE1/ADC7 */
 
 /* Unused Pins */
 UNUSED(PIN(D, 6))       /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
-UNUSED(PIN(3, 1))       /* KSI0/GPIO31/TRACEDATA3/GP_MOSI */
 UNUSED(PIN(3, 2))       /* GPO32/TRIS_L */
 UNUSED(PIN(3, 5))       /* GPO35/CR_SOUT4/TEST_L */
 UNUSED(PIN(6, 6))       /* GPIO66 */
@@ -169,7 +172,6 @@ UNUSED(PIN(5, 0))       /* GPIO50 */
 UNUSED(PIN(9, 4))       /* GPIO94 */
 UNUSED(PIN(A, 0))       /* F_CS0_L/GPIOA0 */
 UNUSED(PIN(3, 4))       /* GPIO34/PS2_DAT2/ADC6 */
-UNUSED(PIN(2, 5))       /* KSI4/GPIO25/TRACECLK/GP_SCLK */
 UNUSED(PIN(F, 3))       /* GPIOF3/I2C4_SCL1 */
 UNUSED(PIN(F, 2))       /* GPIOF2/I2C4_SDA1 */
 UNUSED(PIN(A, 7))       /* GPIOA7/PS2_DAT3/TB2/F_DIO3 */
diff --git a/board/moli/i2c.c b/board/moli/i2c.c
index 534cc89a57..97625c9b29 100644
--- a/board/moli/i2c.c
+++ b/board/moli/i2c.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/moli/led.c b/board/moli/led.c
index 4f04ecdf43..f2ab214418 100644
--- a/board/moli/led.c
+++ b/board/moli/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,16 +19,16 @@
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
 
 /*
  * Due to the CSME-Lite processing, upon startup the CPU transitions through
  * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so
  * delay turning off the LED during suspend/shutdown.
  */
-#define LED_CPU_DELAY_MS	(2000 * MSEC)
+#define LED_CPU_DELAY_MS (2000 * MSEC)
 
-const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 enum led_color {
@@ -61,15 +61,21 @@ static int set_color_power(enum led_color color, int duty)
 		return EC_ERROR_UNKNOWN;
 	}
 
-	if (blue)
+	if (blue && duty) {
+		gpio_set_level(GPIO_LED_BLUE_CONTROL, 1);
 		pwm_set_duty(PWM_CH_LED_BLUE, duty);
-	else
+	} else {
+		gpio_set_level(GPIO_LED_BLUE_CONTROL, 0);
 		pwm_set_duty(PWM_CH_LED_BLUE, 0);
+	}
 
-	if (amber)
+	if (amber && duty) {
+		gpio_set_level(GPIO_LED_ORANGE_CONTROL, 1);
 		pwm_set_duty(PWM_CH_LED_AMBER, duty);
-	else
+	} else {
+		gpio_set_level(GPIO_LED_ORANGE_CONTROL, 0);
 		pwm_set_duty(PWM_CH_LED_AMBER, 0);
+	}
 
 	return EC_SUCCESS;
 }
@@ -84,9 +90,11 @@ static int set_color(enum ec_led_id id, enum led_color color, int duty)
 	}
 }
 
-#define LED_PULSE_US		(2 * SECOND)
-/* 40 msec for nice and smooth transition. */
-#define LED_PULSE_TICK_US	(40 * MSEC)
+#define LED_PERIOD (4 * SECOND)
+#define LED_DUTY_CYCLE (25)
+#define LED_PULSE_US (LED_PERIOD * LED_DUTY_CYCLE / 100 / 2)
+/* 10 msec for nice and smooth transition. */
+#define LED_PULSE_TICK_US (10 * MSEC)
 
 /*
  * When pulsing is enabled, brightness is incremented by <duty_inc> every
@@ -98,17 +106,26 @@ static struct {
 	int duty_inc;
 	enum led_color color;
 	int duty;
+	uint32_t time_off;
 } led_pulse;
 
-#define CONFIG_TICK(interval, color) \
-	config_tick((interval), 100 / (LED_PULSE_US / (interval)), (color))
+/*
+ * LED_PERIOD = time_on + time_off;
+ * time_on = LED_PULSE_US * 2;
+ * time_off = LED_PERIOD - LED_PULSE_US * 2;
+ */
+#define CONFIG_TICK(interval, period, color)                       \
+	config_tick((interval), 100 / (LED_PULSE_US / (interval)), \
+		    LED_PERIOD - LED_PULSE_US * 2, (color))
 
-static void config_tick(uint32_t interval, int duty_inc, enum led_color color)
+static void config_tick(uint32_t interval, int duty_inc, int time_off,
+			enum led_color color)
 {
 	led_pulse.interval = interval;
 	led_pulse.duty_inc = duty_inc;
 	led_pulse.color = color;
 	led_pulse.duty = 0;
+	led_pulse.time_off = time_off;
 }
 
 static void pulse_power_led(enum led_color color)
@@ -133,12 +150,15 @@ static void led_tick(void)
 		pulse_power_led(led_pulse.color);
 	elapsed = get_time().le.lo - start;
 	next = led_pulse.interval > elapsed ? led_pulse.interval - elapsed : 0;
+	next = (led_pulse.duty - led_pulse.duty_inc) ?
+		       next :
+		       next + led_pulse.time_off;
 	hook_call_deferred(&led_tick_data, next);
 }
 
 static void led_suspend(void)
 {
-	CONFIG_TICK(LED_PULSE_TICK_US, LED_AMBER);
+	CONFIG_TICK(LED_PULSE_TICK_US, LED_PERIOD, LED_BLUE);
 	led_tick();
 }
 DECLARE_DEFERRED(led_suspend);
@@ -178,7 +198,7 @@ static void led_resume(void)
 	hook_call_deferred(&led_suspend_data, -1);
 	hook_call_deferred(&led_shutdown_data, -1);
 	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		set_color(EC_LED_ID_POWER_LED, LED_AMBER, 100);
+		set_color(EC_LED_ID_POWER_LED, LED_BLUE, 100);
 }
 DECLARE_HOOK(HOOK_CHIPSET_RESUME, led_resume, HOOK_PRIO_DEFAULT);
 
@@ -186,7 +206,7 @@ void led_alert(int enable)
 {
 	if (enable) {
 		/* Overwrite the current signal */
-		config_tick(1 * SECOND, 100, LED_BLUE);
+		config_tick(1 * SECOND, 100, 0, LED_AMBER);
 		led_tick();
 	} else {
 		/* Restore the previous signal */
@@ -203,10 +223,10 @@ void show_critical_error(void)
 {
 	hook_call_deferred(&led_tick_data, -1);
 	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		set_color(EC_LED_ID_POWER_LED, LED_BLUE, 100);
+		set_color(EC_LED_ID_POWER_LED, LED_AMBER, 100);
 }
 
-static int command_led(int argc, char **argv)
+static int command_led(int argc, const char **argv)
 {
 	enum ec_led_id id = EC_LED_ID_POWER_LED;
 
@@ -231,8 +251,7 @@ static int command_led(int argc, char **argv)
 	}
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(led, command_led,
-			"[debug|blue|amber|off|alert|crit]",
+DECLARE_CONSOLE_COMMAND(led, command_led, "[debug|blue|amber|off|alert|crit]",
 			"Turn on/off LED.");
 
 void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
@@ -251,8 +270,8 @@ int led_set_brightness(enum ec_led_id id, const uint8_t *brightness)
 		return set_color(id, LED_OFF, 0);
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-				int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	/* Blink alert if insufficient power per system_can_boot_ap(). */
 	int insufficient_power =
diff --git a/board/moli/pwm.c b/board/moli/pwm.c
index ad3d45f34c..480c90a78f 100644
--- a/board/moli/pwm.c
+++ b/board/moli/pwm.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,34 +11,23 @@
 #include "pwm_chip.h"
 
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED_AMBER] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 2000
-	},
-	[PWM_CH_FAN] = {
-		.channel = 5,
-		.flags = PWM_CONFIG_OPEN_DRAIN,
-		.freq = 25000
-	},
-	[PWM_CH_LED_BLUE] = {
-		.channel = 2,
-		.flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-		.freq = 2000
-	},
+	[PWM_CH_LED_AMBER] = { .channel = 0,
+			       .flags = PWM_CONFIG_ACTIVE_LOW |
+					PWM_CONFIG_DSLEEP,
+			       .freq = 2000 },
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
+	[PWM_CH_LED_BLUE] = { .channel = 2,
+			      .flags = PWM_CONFIG_ACTIVE_LOW |
+				       PWM_CONFIG_DSLEEP,
+			      .freq = 2000 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
 static void board_pwm_init(void)
 {
-	/*
-	 * TODO(b/197478860): Turn on the fan at 100% by default
-	 * We need to find tune the fan speed according to the
-	 * thermal sensor value.
-	 */
 	pwm_enable(PWM_CH_FAN, 1);
-	pwm_set_duty(PWM_CH_FAN, 100);
-
 	pwm_enable(PWM_CH_LED_BLUE, 1);
 	pwm_enable(PWM_CH_LED_AMBER, 1);
 }
diff --git a/board/moli/sensors.c b/board/moli/sensors.c
index 8992b24ac4..5394f16f5d 100644
--- a/board/moli/sensors.c
+++ b/board/moli/sensors.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -51,58 +51,52 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* Temperature sensor configuration */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1_SSD] = {
-		.name = "SSD",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_1_SSD
-	},
-	[TEMP_SENSOR_2_CPU_VR] = {
-		.name = "CPU VR",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_2_CPU_VR
-	},
-	[TEMP_SENSOR_4_DIMM] = {
-		.name = "DIMM",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_4_DIMM
-	},
+	[TEMP_SENSOR_1_SSD] = { .name = "SSD",
+				.type = TEMP_SENSOR_TYPE_BOARD,
+				.read = get_temp_3v3_30k9_47k_4050b,
+				.idx = ADC_TEMP_SENSOR_1_SSD },
+	[TEMP_SENSOR_2_CPU_VR] = { .name = "CPU VR",
+				   .type = TEMP_SENSOR_TYPE_BOARD,
+				   .read = get_temp_3v3_30k9_47k_4050b,
+				   .idx = ADC_TEMP_SENSOR_2_CPU_VR },
+	[TEMP_SENSOR_4_DIMM] = { .name = "DIMM",
+				 .type = TEMP_SENSOR_TYPE_BOARD,
+				 .read = get_temp_3v3_30k9_47k_4050b,
+				 .idx = ADC_TEMP_SENSOR_4_DIMM },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
-/*
- * TODO(b/180681346): update for Alder Lake/brya
- *
- * Tiger Lake specifies 100 C as maximum TDP temperature.  THRMTRIP# occurs at
- * 130 C.  However, sensor is located next to DDR, so we need to use the lower
- * DDR temperature limit (85 C)
- */
-/*
- * TODO(b/202062363): Remove when clang is fixed.
- */
-#define THERMAL_CPU \
-	{ \
-		.temp_host = { \
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
-			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
-		}, \
-		.temp_host_release = { \
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
-		}, \
-		.temp_fan_off = C_TO_K(35), \
-		.temp_fan_max = C_TO_K(50), \
+#define THERMAL_SSD                                         \
+	{                                                   \
+		.temp_host = {                              \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(64), \
+		},                                          \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_ssd = THERMAL_SSD;
+
+#define THERMAL_CPU                                          \
+	{                                                    \
+		.temp_host = {                               \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(100), \
+		},                                           \
 	}
 __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 
+#define THERMAL_DIMM                                        \
+	{                                                   \
+		.temp_host = {                              \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(67), \
+		},                                          \
+	}
+__maybe_unused static const struct ec_thermal_config thermal_dimm =
+	THERMAL_DIMM;
 /*
  * TODO(b/197478860): add the thermal sensor setting
  */
 /* this should really be "const" */
 struct ec_thermal_config thermal_params[] = {
-	[TEMP_SENSOR_1_SSD] = THERMAL_CPU,
+	[TEMP_SENSOR_1_SSD] = THERMAL_SSD,
 	[TEMP_SENSOR_2_CPU_VR] = THERMAL_CPU,
-	[TEMP_SENSOR_4_DIMM] = THERMAL_CPU,
+	[TEMP_SENSOR_4_DIMM] = THERMAL_DIMM,
 };
 BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
diff --git a/board/moli/thermal.c b/board/moli/thermal.c
new file mode 100644
index 0000000000..110d8ae2db
--- /dev/null
+++ b/board/moli/thermal.c
@@ -0,0 +1,143 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "chipset.h"
+#include "common.h"
+#include "console.h"
+#include "fan.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "temp_sensor.h"
+#include "thermal.h"
+#include "util.h"
+/* Console output macros */
+#define CPUTS(outstr) cputs(CC_THERMAL, outstr)
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
+
+struct fan_step {
+	/*
+	 * Sensor 1~4 trigger point, set -1 if we're not using this
+	 * sensor to determine fan speed.
+	 */
+	int8_t on[TEMP_SENSOR_COUNT];
+	/*
+	 * Sensor 1~4 trigger point, set -1 if we're not using this
+	 * sensor to determine fan speed.
+	 */
+	int8_t off[TEMP_SENSOR_COUNT];
+	/* Fan rpm */
+	uint16_t rpm[FAN_CH_COUNT];
+};
+
+static const struct fan_step fan_table[] = {
+	{
+		/* level 0 */
+		.on = { -1, 47, -1 },
+		.off = { -1, 0, -1 },
+		.rpm = { 1900 },
+	},
+	{
+		/* level 1 */
+		.on = { -1, 50, -1 },
+		.off = { -1, 47, -1 },
+		.rpm = { 2400 },
+	},
+	{
+		/* level 2 */
+		.on = { -1, 60, -1 },
+		.off = { -1, 57, -1 },
+		.rpm = { 3000 },
+	},
+	{
+		/* level 3 */
+		.on = { -1, 70, -1 },
+		.off = { -1, 67, -1 },
+		.rpm = { 3500 },
+	},
+	{
+		/* level 4 */
+		.on = { -1, 80, -1 },
+		.off = { -1, 77, -1 },
+		.rpm = { 4000 },
+	},
+	{
+		/* level 5 */
+		.on = { -1, 90, -1 },
+		.off = { -1, 87, -1 },
+		.rpm = { 4500 },
+	},
+};
+const int num_fan_levels = ARRAY_SIZE(fan_table);
+
+int fan_table_to_rpm(int fan, int *temp, enum temp_sensor_id temp_sensor)
+{
+	/* current fan level */
+	static int current_level;
+	/* previous fan level */
+	static int prev_current_level;
+	/* previous sensor temperature */
+	static int prev_temp[TEMP_SENSOR_COUNT];
+	int i;
+	int new_rpm = 0;
+
+	/*
+	 * Compare the current and previous temperature, we have
+	 * the three paths :
+	 *  1. decreasing path. (check the release point)
+	 *  2. increasing path. (check the trigger point)
+	 *  3. invariant path. (return the current RPM)
+	 */
+	if (temp[temp_sensor] < prev_temp[temp_sensor]) {
+		for (i = current_level; i > 0; i--) {
+			if (temp[temp_sensor] < fan_table[i].off[temp_sensor])
+				current_level = i - 1;
+			else
+				break;
+		}
+	} else if (temp[temp_sensor] > prev_temp[temp_sensor]) {
+		for (i = current_level; i < num_fan_levels; i++) {
+			if (temp[temp_sensor] >= fan_table[i].on[temp_sensor])
+				current_level = i;
+			else
+				break;
+		}
+	}
+	if (current_level < 0)
+		current_level = 0;
+	if (current_level >= num_fan_levels)
+		current_level = num_fan_levels - 1;
+
+	if (current_level != prev_current_level) {
+		CPRINTS("temp: %d, prev_temp: %d", temp[temp_sensor],
+			prev_temp[temp_sensor]);
+		CPRINTS("current_level: %d", current_level);
+	}
+
+	prev_temp[temp_sensor] = temp[temp_sensor];
+	prev_current_level = current_level;
+
+	switch (fan) {
+	case FAN_CH_0:
+		new_rpm = fan_table[current_level].rpm[FAN_CH_0];
+		break;
+	default:
+		break;
+	}
+	return new_rpm;
+}
+
+void board_override_fan_control(int fan, int *temp)
+{
+	if (chipset_in_state(CHIPSET_STATE_ON)) {
+		fan_set_rpm_mode(FAN_CH(fan), 1);
+		fan_set_rpm_target(FAN_CH(fan),
+				   fan_table_to_rpm(FAN_CH(fan), temp,
+						    TEMP_SENSOR_2_CPU_VR));
+	} else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
+		/* Stop fan when enter S0ix */
+		fan_set_rpm_mode(FAN_CH(fan), 1);
+		fan_set_rpm_target(FAN_CH(fan), 0);
+	}
+}
diff --git a/board/moli/usbc_config.c b/board/moli/usbc_config.c
index a54564c34c..fce8b46aa2 100644
--- a/board/moli/usbc_config.c
+++ b/board/moli/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -30,8 +30,8 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 /* USBC TCPC configuration */
 const struct tcpc_config_t tcpc_config[] = {
@@ -76,34 +76,44 @@ BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
 /* USBC mux configuration - Alder Lake includes internal mux */
-static const struct usb_mux usbc0_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+static const struct usb_mux_chain usbc0_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
 
-static const struct usb_mux usbc1_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+static const struct usb_mux_chain usbc1_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
 
-const struct usb_mux usb_muxes[] = {
+const struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C0_C1_MUX,
-		.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc0_tcss_usb_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C0_C1_MUX,
+			.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc0_tcss_usb_mux,
 	},
 	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C0_C1_MUX,
-		.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc1_tcss_usb_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C0_C1_MUX,
+			.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc1_tcss_usb_mux,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
diff --git a/board/moli/usbc_config.h b/board/moli/usbc_config.h
index 002f4803b7..219ad9a745 100644
--- a/board/moli/usbc_config.h
+++ b/board/moli/usbc_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,12 +8,8 @@
 #ifndef __CROS_EC_USBC_CONFIG_H
 #define __CROS_EC_USBC_CONFIG_H
 
-#define CONFIG_USB_PD_PORT_MAX_COUNT	2
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 #endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/moonbuggy/board.c b/board/moonbuggy/board.c
index cfe0121374..9d8162c2d0 100644
--- a/board/moonbuggy/board.c
+++ b/board/moonbuggy/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -36,8 +36,8 @@
 #include "usb_common.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
 static void power_monitor(void);
 DECLARE_DEFERRED(power_monitor);
@@ -49,14 +49,14 @@ static int32_t base_5v_power;
  * Power usage for each port as measured or estimated.
  * Units are milliwatts (5v x ma current)
  */
-#define PWR_BASE_LOAD	(5*1335)
-#define PWR_FRONT_HIGH	(5*1500)
-#define PWR_FRONT_LOW	(5*900)
-#define PWR_REAR	(5*1500)
-#define PWR_HDMI	(5*562)
-#define PWR_C_HIGH	(5*3740)
-#define PWR_C_LOW	(5*2090)
-#define PWR_MAX		(5*10000)
+#define PWR_BASE_LOAD (5 * 1335)
+#define PWR_FRONT_HIGH (5 * 1500)
+#define PWR_FRONT_LOW (5 * 900)
+#define PWR_REAR (5 * 1500)
+#define PWR_HDMI (5 * 562)
+#define PWR_C_HIGH (5 * 3740)
+#define PWR_C_LOW (5 * 2090)
+#define PWR_MAX (5 * 10000)
 
 /*
  * Update the 5V power usage, assuming no throttling,
@@ -147,64 +147,52 @@ void ads_12v_interrupt(enum gpio_signal signal)
 
 /******************************************************************************/
 /* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
+const struct spi_device_t spi_devices[] = {};
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
 /******************************************************************************/
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN]        = { .channel = 5,
-				.flags = PWM_CONFIG_OPEN_DRAIN,
-				.freq = 25000},
-	[PWM_CH_LED_RED]    = { .channel = 0,
-				.flags = PWM_CONFIG_ACTIVE_LOW |
-					 PWM_CONFIG_DSLEEP,
-				.freq = 2000 },
-	[PWM_CH_LED_WHITE]  = { .channel = 2,
-				.flags = PWM_CONFIG_ACTIVE_LOW |
-					 PWM_CONFIG_DSLEEP,
-				.freq = 2000 },
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
+	[PWM_CH_LED_RED] = { .channel = 0,
+			     .flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+			     .freq = 2000 },
+	[PWM_CH_LED_WHITE] = { .channel = 2,
+			       .flags = PWM_CONFIG_ACTIVE_LOW |
+					PWM_CONFIG_DSLEEP,
+			       .freq = 2000 },
 };
 
 /******************************************************************************/
 /* I2C port map configuration */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "ina",
-		.port = I2C_PORT_INA,
-		.kbps = 400,
-		.scl  = GPIO_I2C0_SCL,
-		.sda  = GPIO_I2C0_SDA
-	},
-	{
-		.name = "tcpc0",
-		.port = I2C_PORT_TCPC0,
-		.kbps = 400,
-		.scl  = GPIO_I2C3_SCL,
-		.sda  = GPIO_I2C3_SDA
-	},
-	{
-		.name = "pse",
-		.port = I2C_PORT_PSE,
-		.kbps = 400,
-		.scl  = GPIO_I2C4_SCL,
-		.sda  = GPIO_I2C4_SDA
-	},
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 400,
-		.scl  = GPIO_I2C5_SCL,
-		.sda  = GPIO_I2C5_SDA
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl  = GPIO_I2C7_SCL,
-		.sda  = GPIO_I2C7_SDA
-	},
+	{ .name = "ina",
+	  .port = I2C_PORT_INA,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_SCL,
+	  .sda = GPIO_I2C0_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
+	{ .name = "pse",
+	  .port = I2C_PORT_PSE,
+	  .kbps = 400,
+	  .scl = GPIO_I2C4_SCL,
+	  .sda = GPIO_I2C4_SDA },
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 400,
+	  .scl = GPIO_I2C5_SCL,
+	  .sda = GPIO_I2C5_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_I2C7_SCL,
+	  .sda = GPIO_I2C7_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -260,15 +248,14 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
 /******************************************************************************/
 /* Wake up pins */
-const enum gpio_signal hibernate_wake_pins[] = {
-};
+const enum gpio_signal hibernate_wake_pins[] = {};
 const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 
 /******************************************************************************/
 /* Physical fans. These are logically separate from pwm_channels. */
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = -1,
 };
@@ -287,7 +274,7 @@ BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
 /******************************************************************************/
 /* MFT channels. These are logically separate from pwm_channels. */
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN },
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
@@ -296,8 +283,8 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_A \
-	{ \
+#define THERMAL_A                \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = 0, \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(85), \
@@ -382,13 +369,16 @@ static void board_init(void)
 	 */
 	if (board_version < 2)
 		button_disable_gpio(BUTTON_RECOVERY);
+
+	/* ADS GPIO interrupt enable*/
+	gpio_enable_interrupt(GPIO_ADS_5VS_V2_ADP_PRESENT_L);
+	gpio_enable_interrupt(GPIO_BJ_ADP_PRESENT_L);
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
 /******************************************************************************/
 /* USB-A port control */
-const int usb_port_enable[USB_PORT_COUNT] = {
-};
+const int usb_port_enable[USB_PORT_COUNT] = {};
 
 int64_t get_time_dsw_pwrok(void)
 {
@@ -449,23 +439,23 @@ void board_enable_s0_rails(int enable)
  *
  *  All measurements are in milliwatts.
  */
-#define THROT_TYPE_A		BIT(0)
-#define THROT_TYPE_C		BIT(1)
-#define THROT_PROCHOT		BIT(2)
+#define THROT_TYPE_A BIT(0)
+#define THROT_TYPE_C BIT(1)
+#define THROT_PROCHOT BIT(2)
 
 /*
  * Power gain if front USB A ports are limited.
  */
-#define POWER_GAIN_TYPE_A	3200
+#define POWER_GAIN_TYPE_A 3200
 /*
  * Power gain if Type C port is limited.
  */
-#define POWER_GAIN_TYPE_C	8800
+#define POWER_GAIN_TYPE_C 8800
 /*
  * Power is averaged over 10 ms, with a reading every 2 ms.
  */
-#define POWER_DELAY_MS		2
-#define POWER_READINGS		(10/POWER_DELAY_MS)
+#define POWER_DELAY_MS 2
+#define POWER_READINGS (10 / POWER_DELAY_MS)
 
 static void power_monitor(void)
 {
@@ -478,8 +468,7 @@ static void power_monitor(void)
 	 * If CPU is off or suspended, no need to throttle
 	 * or restrict power.
 	 */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF |
-			     CHIPSET_STATE_SUSPEND)) {
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF | CHIPSET_STATE_SUSPEND)) {
 		/*
 		 * Slow down monitoring, assume no throttling required.
 		 */
diff --git a/board/moonbuggy/board.h b/board/moonbuggy/board.h
index b5e8424230..26e230b2a7 100644
--- a/board/moonbuggy/board.h
+++ b/board/moonbuggy/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,8 +12,8 @@
 #define CONFIG_UART_TX_BUF_SIZE 4096
 
 /* NPCX7 config */
-#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
-#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
+#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */
+#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */
 
 /* Internal SPI flash on NPCX796FC is 512 kB */
 #define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
@@ -40,7 +40,7 @@
 #undef CONFIG_HIBERNATE
 #define CONFIG_HOST_INTERFACE_ESPI
 #define CONFIG_LED_COMMON
-#undef  CONFIG_LID_SWITCH
+#undef CONFIG_LID_SWITCH
 #define CONFIG_LTO
 #define CONFIG_PWM
 #define CONFIG_VBOOT_EFS2
@@ -119,12 +119,12 @@
 /* I2C Bus Configuration */
 #define CONFIG_I2C
 #define CONFIG_I2C_CONTROLLER
-#define I2C_PORT_INA		NPCX_I2C_PORT0_0
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT3_0
-#define I2C_PORT_PSE		NPCX_I2C_PORT4_1
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_PORT_INA NPCX_I2C_PORT0_0
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT3_0
+#define I2C_PORT_PSE NPCX_I2C_PORT4_1
+#define I2C_PORT_POWER NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 
 #define PP5000_PGOOD_POWER_SIGNAL_MASK POWER_SIGNAL_MASK(PP5000_A_PGOOD)
 
@@ -134,11 +134,11 @@
 #include "registers.h"
 
 enum adc_channel {
-	ADC_SNS_PP3300,     /* ADC2 */
-	ADC_SNS_PP1050,     /* ADC7 */
-	ADC_VBUS,           /* ADC4 */
-	ADC_PPVAR_IMON,     /* ADC9 */
-	ADC_TEMP_SENSOR_1,  /* ADC0 */
+	ADC_SNS_PP3300, /* ADC2 */
+	ADC_SNS_PP1050, /* ADC7 */
+	ADC_VBUS, /* ADC4 */
+	ADC_PPVAR_IMON, /* ADC9 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
 	/* Number of ADC channels */
 	ADC_CH_COUNT
 };
@@ -163,10 +163,7 @@ enum mft_channel {
 	MFT_CH_COUNT,
 };
 
-enum temp_sensor_id {
-	TEMP_SENSOR_CORE,
-	TEMP_SENSOR_COUNT
-};
+enum temp_sensor_id { TEMP_SENSOR_CORE, TEMP_SENSOR_COUNT };
 
 /* Board specific handlers */
 void led_alert(int enable);
@@ -182,20 +179,20 @@ void ads_12v_interrupt(enum gpio_signal signal);
 /*
  * Barrel-jack power (4 bits).
  */
-#define EC_CFG_BJ_POWER_L		0
-#define EC_CFG_BJ_POWER_H		3
+#define EC_CFG_BJ_POWER_L 0
+#define EC_CFG_BJ_POWER_H 3
 #define EC_CFG_BJ_POWER_MASK GENMASK(EC_CFG_BJ_POWER_H, EC_CFG_BJ_POWER_L)
 /*
  * USB Connector 4 not present (1 bit).
  */
-#define EC_CFG_NO_USB4_L		4
-#define EC_CFG_NO_USB4_H		4
+#define EC_CFG_NO_USB4_L 4
+#define EC_CFG_NO_USB4_H 4
 #define EC_CFG_NO_USB4_MASK GENMASK(EC_CFG_NO_USB4_H, EC_CFG_NO_USB4_L)
 /*
  * Thermal solution config (3 bits).
  */
-#define EC_CFG_THERMAL_L		5
-#define EC_CFG_THERMAL_H		7
+#define EC_CFG_THERMAL_L 5
+#define EC_CFG_THERMAL_H 7
 #define EC_CFG_THERMAL_MASK GENMASK(EC_CFG_THERMAL_H, EC_CFG_THERMAL_L)
 
 unsigned int ec_config_get_thermal_solution(void);
@@ -203,30 +200,30 @@ unsigned int ec_config_get_thermal_solution(void);
 #endif /* !__ASSEMBLER__ */
 
 /* Pin renaming */
-#define GPIO_WP_L               GPIO_EC_WP_ODL
-#define GPIO_PP5000_A_PG_OD     GPIO_PG_PP5000_A_OD
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
-#define GPIO_RECOVERY_L         GPIO_EC_RECOVERY_BTN_ODL
-#define GPIO_RECOVERY_L_2       GPIO_H1_EC_RECOVERY_BTN_ODL
-#define GPIO_POWER_BUTTON_L	GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_PCH_WAKE_L		GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L	GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_ENTERING_RW	GPIO_EC_ENTERING_RW
-#define GPIO_SYS_RESET_L	GPIO_SYS_RST_ODL
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_PCH_RTCRST		GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_TEMP_SENSOR_POWER	GPIO_EN_ROA_RAILS
-#define GPIO_AC_PRESENT		GPIO_BJ_ADP_PRESENT_L
+#define GPIO_WP_L GPIO_EC_WP_ODL
+#define GPIO_PP5000_A_PG_OD GPIO_PG_PP5000_A_OD
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
+#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_ODL
+#define GPIO_RECOVERY_L_2 GPIO_H1_EC_RECOVERY_BTN_ODL
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_EN_ROA_RAILS
+#define GPIO_AC_PRESENT GPIO_BJ_ADP_PRESENT_L
 
 /*
  * There is no RSMRST input, so alias it to the output. This short-circuits
  * common_intel_x86_handle_rsmrst.
  */
-#define GPIO_PG_EC_RSMRST_ODL	GPIO_PCH_RSMRST_L
+#define GPIO_PG_EC_RSMRST_ODL GPIO_PCH_RSMRST_L
 
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/moonbuggy/build.mk b/board/moonbuggy/build.mk
index 0acd315b39..aca2a91e5c 100644
--- a/board/moonbuggy/build.mk
+++ b/board/moonbuggy/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/moonbuggy/ec.tasklist b/board/moonbuggy/ec.tasklist
index 3828142c55..c43d643410 100644
--- a/board/moonbuggy/ec.tasklist
+++ b/board/moonbuggy/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/moonbuggy/gpio.inc b/board/moonbuggy/gpio.inc
index b2d25440a6..bb914d2254 100644
--- a/board/moonbuggy/gpio.inc
+++ b/board/moonbuggy/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,12 +25,12 @@ GPIO_INT(PG_VPRIM_CORE_A_OD,   PIN(2, 3), GPIO_INT_BOTH, power_signal_interrupt)
 GPIO_INT(PG_PP1050_A_OD,       PIN(2, 2), GPIO_INT_BOTH, power_signal_interrupt)
 /* EC output, but also interrupt so this can be polled as a power signal */
 GPIO_INT(EC_PCH_RSMRST_L,      PIN(A, 6), GPIO_OUTPUT | GPIO_INT_F_RISING | GPIO_INT_F_FALLING, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(PG_PP2500_DRAM_U_OD,  PIN(2, 0), GPIO_INT_BOTH, power_signal_interrupt)
 GPIO_INT(PG_PP1200_U_OD,       PIN(2, 1), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, slp_s3_interrupt)
 #endif
 GPIO_INT(PG_PP950_VCCIO_OD,    PIN(1, 7), GPIO_INT_BOTH, power_signal_interrupt)
diff --git a/board/moonbuggy/led.c b/board/moonbuggy/led.c
index f05733a387..cc76c36dce 100644
--- a/board/moonbuggy/led.c
+++ b/board/moonbuggy/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,16 +19,16 @@
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
 
 /*
  * Due to the CSME-Lite processing, upon startup the CPU transitions through
  * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so
  * delay turning off the LED during suspend/shutdown.
  */
-#define LED_CPU_DELAY_MS	(2000 * MSEC)
+#define LED_CPU_DELAY_MS (2000 * MSEC)
 
-const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 enum led_color {
@@ -84,9 +84,9 @@ static int set_color(enum ec_led_id id, enum led_color color, int duty)
 	}
 }
 
-#define LED_PULSE_US		(2 * SECOND)
+#define LED_PULSE_US (2 * SECOND)
 /* 40 msec for nice and smooth transition. */
-#define LED_PULSE_TICK_US	(40 * MSEC)
+#define LED_PULSE_TICK_US (40 * MSEC)
 
 /* When pulsing is enabled, brightness is incremented by <duty_inc> every
  * <interval> usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented
@@ -218,7 +218,7 @@ void show_critical_error(void)
 		set_color(EC_LED_ID_POWER_LED, LED_RED, 100);
 }
 
-static int command_led(int argc, char **argv)
+static int command_led(int argc, const char **argv)
 {
 	enum ec_led_id id = EC_LED_ID_POWER_LED;
 
@@ -243,8 +243,7 @@ static int command_led(int argc, char **argv)
 	}
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(led, command_led,
-			"[debug|red|white|off|alert|crit]",
+DECLARE_CONSOLE_COMMAND(led, command_led, "[debug|red|white|off|alert|crit]",
 			"Turn on/off LED.");
 
 void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
diff --git a/board/moonbuggy/pse.c b/board/moonbuggy/pse.c
index 84d5048a86..c309db887a 100644
--- a/board/moonbuggy/pse.c
+++ b/board/moonbuggy/pse.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,44 +18,44 @@
 #include "timer.h"
 #include "util.h"
 
-#define LTC4291_I2C_ADDR	0x2C
-
-#define LTC4291_REG_SUPEVN_COR	0x0B
-#define LTC4291_REG_STATPWR	0x10
-#define LTC4291_REG_STATPIN	0x11
-#define LTC4291_REG_OPMD	0x12
-#define LTC4291_REG_DISENA	0x13
-#define LTC4291_REG_DETENA	0x14
-#define LTC4291_REG_DETPB	0x18
-#define LTC4291_REG_PWRPB	0x19
-#define LTC4291_REG_RSTPB	0x1A
-#define LTC4291_REG_ID		0x1B
-#define LTC4291_REG_DEVID	0x43
-#define LTC4291_REG_HPMD1	0x46
-#define LTC4291_REG_HPMD2	0x4B
-#define LTC4291_REG_HPMD3	0x50
-#define LTC4291_REG_HPMD4	0x55
-#define LTC4291_REG_LPWRPB	0x6E
-
-#define LTC4291_FLD_STATPIN_AUTO	BIT(0)
-#define LTC4291_FLD_RSTPB_RSTALL	BIT(4)
-
-#define LTC4291_STATPWR_ON_PORT(port)	(0x01 << (port))
-#define LTC4291_DETENA_EN_PORT(port)	(0x11 << (port))
-#define LTC4291_DETPB_EN_PORT(port)	(0x11 << (port))
-#define LTC4291_PWRPB_OFF_PORT(port)	(0x10 << (port))
-
-#define LTC4291_OPMD_AUTO	0xFF
-#define LTC4291_DISENA_ALL	0x0F
-#define LTC4291_DETENA_ALL	0xFF
-#define LTC4291_ID		0x64
-#define LTC4291_DEVID		0x38
-#define LTC4291_HPMD_MIN	0x00
-#define LTC4291_HPMD_MAX	0xA8
-
-#define LTC4291_PORT_MAX	4
-
-#define LTC4291_RESET_DELAY_US	(20 * MSEC)
+#define LTC4291_I2C_ADDR 0x2C
+
+#define LTC4291_REG_SUPEVN_COR 0x0B
+#define LTC4291_REG_STATPWR 0x10
+#define LTC4291_REG_STATPIN 0x11
+#define LTC4291_REG_OPMD 0x12
+#define LTC4291_REG_DISENA 0x13
+#define LTC4291_REG_DETENA 0x14
+#define LTC4291_REG_DETPB 0x18
+#define LTC4291_REG_PWRPB 0x19
+#define LTC4291_REG_RSTPB 0x1A
+#define LTC4291_REG_ID 0x1B
+#define LTC4291_REG_DEVID 0x43
+#define LTC4291_REG_HPMD1 0x46
+#define LTC4291_REG_HPMD2 0x4B
+#define LTC4291_REG_HPMD3 0x50
+#define LTC4291_REG_HPMD4 0x55
+#define LTC4291_REG_LPWRPB 0x6E
+
+#define LTC4291_FLD_STATPIN_AUTO BIT(0)
+#define LTC4291_FLD_RSTPB_RSTALL BIT(4)
+
+#define LTC4291_STATPWR_ON_PORT(port) (0x01 << (port))
+#define LTC4291_DETENA_EN_PORT(port) (0x11 << (port))
+#define LTC4291_DETPB_EN_PORT(port) (0x11 << (port))
+#define LTC4291_PWRPB_OFF_PORT(port) (0x10 << (port))
+
+#define LTC4291_OPMD_AUTO 0xFF
+#define LTC4291_DISENA_ALL 0x0F
+#define LTC4291_DETENA_ALL 0xFF
+#define LTC4291_ID 0x64
+#define LTC4291_DEVID 0x38
+#define LTC4291_HPMD_MIN 0x00
+#define LTC4291_HPMD_MAX 0xA8
+
+#define LTC4291_PORT_MAX 4
+
+#define LTC4291_RESET_DELAY_US (20 * MSEC)
 
 #define I2C_PSE_READ(reg, data) \
 	i2c_read8(I2C_PORT_PSE, LTC4291_I2C_ADDR, LTC4291_REG_##reg, (data))
@@ -63,7 +63,7 @@
 #define I2C_PSE_WRITE(reg, data) \
 	i2c_write8(I2C_PORT_PSE, LTC4291_I2C_ADDR, LTC4291_REG_##reg, (data))
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 static int pse_write_hpmd(int port, int val)
 {
@@ -172,7 +172,7 @@ DECLARE_HOOK(HOOK_CHIPSET_RESUME, pse_init, HOOK_PRIO_DEFAULT);
 /* Also reset the PSE on a reboot to toggle the power. */
 DECLARE_HOOK(HOOK_CHIPSET_RESET, pse_init, HOOK_PRIO_DEFAULT);
 
-static int command_pse(int argc, char **argv)
+static int command_pse(int argc, const char **argv)
 {
 	int port;
 
@@ -204,8 +204,7 @@ static int command_pse(int argc, char **argv)
 	else
 		return EC_ERROR_PARAM2;
 }
-DECLARE_CONSOLE_COMMAND(pse, command_pse,
-			"<port# 0-3> <off | on | min | max>",
+DECLARE_CONSOLE_COMMAND(pse, command_pse, "<port# 0-3> <off | on | min | max>",
 			"Set PSE port power");
 
 static int ec_command_pse_status(int port, uint8_t *status)
diff --git a/board/morphius/battery.c b/board/morphius/battery.c
index 6d8a8190b2..6867bcd8bd 100644
--- a/board/morphius/battery.c
+++ b/board/morphius/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/morphius/board.c b/board/morphius/board.c
index beca0d89f0..e801fd8569 100644
--- a/board/morphius/board.c
+++ b/board/morphius/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,7 @@
 #include "driver/accelgyro_icm426xx.h"
 #include "driver/accel_kionix.h"
 #include "driver/accel_kx022.h"
-#include "driver/ppc/aoz1380.h"
+#include "driver/ppc/aoz1380_public.h"
 #include "driver/ppc/nx20p348x.h"
 #include "driver/retimer/pi3dpx1207.h"
 #include "driver/retimer/pi3hdx1204.h"
@@ -59,21 +59,15 @@ static bool ignore_c1_dp;
 static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
-mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-const mat33_fp_t base_standard_ref_1 = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0,  FLOAT_TO_FP(-1)}
-};
-mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0,  0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+				 { FLOAT_TO_FP(1), 0, 0 },
+				 { 0, 0, FLOAT_TO_FP(-1) } };
+const mat33_fp_t base_standard_ref_1 = { { FLOAT_TO_FP(-1), 0, 0 },
+					 { 0, FLOAT_TO_FP(1), 0 },
+					 { 0, 0, FLOAT_TO_FP(-1) } };
+mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+				{ FLOAT_TO_FP(-1), 0, 0 },
+				{ 0, 0, FLOAT_TO_FP(1) } };
 
 /* sensor private data */
 static struct kionix_accel_data g_kx022_data;
@@ -293,6 +287,10 @@ void motion_interrupt(enum gpio_signal signal)
 /*****************************************************************************
  * USB-C MUX/Retimer dynamic configuration
  */
+
+/* Place holder for second mux in USBC1 chain */
+struct usb_mux_chain usbc1_mux1;
+
 static void setup_mux(void)
 {
 	if (ec_config_has_usbc1_retimer_ps8802()) {
@@ -304,12 +302,10 @@ static void setup_mux(void)
 		 * Replace usb_muxes[USBC_PORT_C1] with the PS8802
 		 * table entry.
 		 */
-		memcpy(&usb_muxes[USBC_PORT_C1],
-		       &usbc1_ps8802,
-		       sizeof(struct usb_mux));
+		usb_muxes[USBC_PORT_C1].mux = &usbc1_ps8802;
 
 		/* Set the AMD FP5 as the secondary MUX */
-		usb_muxes[USBC_PORT_C1].next_mux = &usbc1_amd_fp5_usb_mux;
+		usbc1_mux1.mux = &usbc1_amd_fp5_usb_mux;
 
 		/* Don't have the AMD FP5 flip */
 		usbc1_amd_fp5_usb_mux.flags = USB_MUX_FLAG_SET_WITHOUT_FLIP;
@@ -323,12 +319,10 @@ static void setup_mux(void)
 		 * Replace usb_muxes[USBC_PORT_C1] with the AMD FP5
 		 * table entry.
 		 */
-		memcpy(&usb_muxes[USBC_PORT_C1],
-		       &usbc1_amd_fp5_usb_mux,
-		       sizeof(struct usb_mux));
+		usb_muxes[USBC_PORT_C1].mux = &usbc1_amd_fp5_usb_mux;
 
 		/* Set the PS8818 as the secondary MUX */
-		usb_muxes[USBC_PORT_C1].next_mux = &usbc1_ps8818;
+		usbc1_mux1.mux = &usbc1_ps8818;
 	}
 }
 
@@ -342,23 +336,29 @@ const struct pi3dpx1207_usb_control pi3dpx1207_controls[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(pi3dpx1207_controls) == USBC_PORT_COUNT);
 
-const struct usb_mux usbc0_pi3dpx1207_usb_retimer = {
-	.usb_port = USBC_PORT_C0,
-	.i2c_port = I2C_PORT_TCPC0,
-	.i2c_addr_flags = PI3DPX1207_I2C_ADDR_FLAGS,
-	.driver = &pi3dpx1207_usb_retimer,
+const struct usb_mux_chain usbc0_pi3dpx1207_usb_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.i2c_port = I2C_PORT_TCPC0,
+			.i2c_addr_flags = PI3DPX1207_I2C_ADDR_FLAGS,
+			.driver = &pi3dpx1207_usb_retimer,
+		},
 };
 
-struct usb_mux usb_muxes[] = {
+struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.i2c_port = I2C_PORT_USB_AP_MUX,
-		.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
-		.driver = &amd_fp5_usb_mux_driver,
-		.next_mux = &usbc0_pi3dpx1207_usb_retimer,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.i2c_port = I2C_PORT_USB_AP_MUX,
+			.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
+			.driver = &amd_fp5_usb_mux_driver,
+		},
+		.next = &usbc0_pi3dpx1207_usb_retimer,
 	},
 	[USBC_PORT_C1] = {
 		/* Filled in dynamically at startup */
+		.next = &usbc1_mux1,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
@@ -400,11 +400,9 @@ int board_usbc_port_to_hpd_gpio_or_ioex(int port)
 	 * this will be removed when version_2 hardware is retired.
 	 */
 	else if (ec_config_has_mst_hub_rtd2141b())
-		return (board_ver >= 4)
-				? GPIO_USB_C1_HPD_IN_DB_V1
-				: (board_ver == 3)
-					? IOEX_USB_C1_HPD_IN_DB
-					: GPIO_EC_DP1_HPD;
+		return (board_ver >= 4) ? GPIO_USB_C1_HPD_IN_DB_V1 :
+		       (board_ver == 3) ? IOEX_USB_C1_HPD_IN_DB :
+					  GPIO_EC_DP1_HPD;
 
 	/* USB-C1 OPT1 DB uses DP2_HPD. */
 	return GPIO_DP2_HPD;
@@ -486,7 +484,7 @@ DECLARE_HOOK(HOOK_INIT, setup_fw_config, HOOK_PRIO_INIT_I2C + 2);
 /* Physical fans. These are logically separate from pwm_channels. */
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = -1,
 };
@@ -584,8 +582,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CPU \
-	{ \
+#define THERMAL_CPU              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(90), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(105), \
@@ -605,11 +603,11 @@ static void setup_fans(void)
 DECLARE_HOOK(HOOK_INIT, setup_fans, HOOK_PRIO_DEFAULT);
 
 /* Battery functions */
-#define SB_OPTIONALMFG_FUNCTION2        0x26
-#define SMART_CHARGE_SUPPORT            0x01
-#define SMART_CHARGE_ENABLE             0x02
-#define SB_SMART_CHARGE_ENABLE          1
-#define SB_SMART_CHARGE_DISABLE         0
+#define SB_OPTIONALMFG_FUNCTION2 0x26
+#define SMART_CHARGE_SUPPORT 0x01
+#define SMART_CHARGE_ENABLE 0x02
+#define SB_SMART_CHARGE_ENABLE 1
+#define SB_SMART_CHARGE_DISABLE 0
 
 static void sb_smart_charge_mode(int enable)
 {
@@ -651,18 +649,18 @@ __override void ppc_interrupt(enum gpio_signal signal)
  * the attached NCT3807 to control a GPIO to indicate 1A5 or 3A0
  * current limits.
  */
-__override int board_aoz1380_set_vbus_source_current_limit(int port,
-						enum tcpc_rp_value rp)
+__override int
+board_aoz1380_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp)
 {
 	int rv;
 
 	/* Use the TCPC to set the current limit */
 	if (port == 0) {
 		rv = ioex_set_level(IOEX_USB_C0_PPC_ILIM_3A_EN,
-			    (rp == TYPEC_RP_3A0) ? 1 : 0);
+				    (rp == TYPEC_RP_3A0) ? 1 : 0);
 	} else if (board_ver >= 3) {
 		rv = ioex_set_level(IOEX_USB_C1_PPC_ILIM_3A_EN,
-			    (rp == TYPEC_RP_3A0) ? 1 : 0);
+				    (rp == TYPEC_RP_3A0) ? 1 : 0);
 	} else {
 		rv = 1;
 	}
@@ -716,8 +714,7 @@ static void board_chipset_resume(void)
 			ioex_set_level(IOEX_HDMI_POWER_EN_DB, 1);
 			msleep(PI3HDX1204_POWER_ON_DELAY_MS);
 		}
-		pi3hdx1204_enable(I2C_PORT_TCPC1,
-				  PI3HDX1204_I2C_ADDR_FLAGS,
+		pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS,
 				  check_hdmi_hpd_status());
 	}
 }
@@ -735,16 +732,14 @@ static void board_chipset_suspend(void)
 	sb_smart_charge_mode(SB_SMART_CHARGE_ENABLE);
 
 	if (ec_config_has_hdmi_retimer_pi3hdx1204()) {
-		pi3hdx1204_enable(I2C_PORT_TCPC1,
-				  PI3HDX1204_I2C_ADDR_FLAGS,
-				  0);
+		pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS, 0);
 		if (board_ver >= 3)
 			ioex_set_level(IOEX_HDMI_POWER_EN_DB, 0);
 	}
 
 	/* Wait 500ms before allowing DP event to cause resume. */
-	if (ec_config_has_mst_hub_rtd2141b()
-	    && (dp_flags[USBC_PORT_C1] & DP_FLAGS_DP_ON)) {
+	if (ec_config_has_mst_hub_rtd2141b() &&
+	    (dp_flags[USBC_PORT_C1] & DP_FLAGS_DP_ON)) {
 		ignore_c1_dp = true;
 		hook_call_deferred(&board_chipset_suspend_delay_data,
 				   500 * MSEC);
@@ -789,15 +784,14 @@ BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
  * The connector has 24 pins total, and there is no pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-		{3, 0}, {2, 2}, {2, 3}, {1, 2}, {2, 5},
-		{2, 4}, {2, 1}, {2, 7}, {2, 6}, {1, 5},
-		{2, 0}, {3, 1}, {1, 7}, {1, 6}, {-1, -1},
-		{1, 3}, {1, 4}, {-1, -1}, {-1, -1}, {0, 7},
-		{0, 6}, {1, 0}, {1, 1}, {0, 5},
+	{ 3, 0 },   { 2, 2 }, { 2, 3 },	  { 1, 2 }, { 2, 5 }, { 2, 4 },
+	{ 2, 1 },   { 2, 7 }, { 2, 6 },	  { 1, 5 }, { 2, 0 }, { 3, 1 },
+	{ 1, 7 },   { 1, 6 }, { -1, -1 }, { 1, 3 }, { 1, 4 }, { -1, -1 },
+	{ -1, -1 }, { 0, 7 }, { 0, 6 },	  { 1, 0 }, { 1, 1 }, { 0, 5 },
 };
 
 const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 #endif
 
 /*****************************************************************************
@@ -840,10 +834,9 @@ static void hdmi_hpd_handler(void)
 
 	gpio_set_level(GPIO_EC_DP1_HPD, hpd);
 	ccprints("HDMI HPD %d", hpd);
-	pi3hdx1204_enable(I2C_PORT_TCPC1,
-			  PI3HDX1204_I2C_ADDR_FLAGS,
-			  chipset_in_or_transitioning_to_state(CHIPSET_STATE_ON)
-			  && hpd);
+	pi3hdx1204_enable(
+		I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS,
+		chipset_in_or_transitioning_to_state(CHIPSET_STATE_ON) && hpd);
 }
 DECLARE_DEFERRED(hdmi_hpd_handler);
 
diff --git a/board/morphius/board.h b/board/morphius/board.h
index 180b1df9d0..39bce41a46 100644
--- a/board/morphius/board.h
+++ b/board/morphius/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -52,36 +52,35 @@
 #define RPM_DEVIATION 1
 
 /* GPIO mapping from board specific name to EC common name. */
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_EC_BATT_PRES_ODL
-#define CONFIG_SCI_GPIO			GPIO_EC_FCH_SCI_ODL
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_AP_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT_L		GPIO_EC_EDP_BL_DISABLE
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_FCH_PWR_BTN_L
-#define GPIO_PCH_RSMRST_L		GPIO_EC_FCH_RSMRST_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S5_L		GPIO_SLP_S5_L
-#define GPIO_PCH_SYS_PWROK		GPIO_EC_FCH_PWROK
-#define GPIO_PCH_WAKE_L			GPIO_EC_FCH_WAKE_L
-#define GPIO_POWER_BUTTON_L		GPIO_EC_PWR_BTN_ODL
-#define GPIO_S0_PGOOD			GPIO_S0_PWROK_OD
-#define GPIO_S5_PGOOD			GPIO_EC_PWROK_OD
-#define GPIO_SYS_RESET_L		GPIO_EC_SYS_RST_L
-#define GPIO_TEMP_SENSOR_POWER		GPIO_EN_PWR_A
-#define GPIO_VOLUME_DOWN_L		GPIO_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
+#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL
+#define CONFIG_SCI_GPIO GPIO_EC_FCH_SCI_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_AP_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_EDP_BL_DISABLE
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PCH_PWRBTN_L GPIO_EC_FCH_PWR_BTN_L
+#define GPIO_PCH_RSMRST_L GPIO_EC_FCH_RSMRST_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L
+#define GPIO_PCH_SYS_PWROK GPIO_EC_FCH_PWROK
+#define GPIO_PCH_WAKE_L GPIO_EC_FCH_WAKE_L
+#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL
+#define GPIO_S0_PGOOD GPIO_S0_PWROK_OD
+#define GPIO_S5_PGOOD GPIO_EC_PWROK_OD
+#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_EN_PWR_A
+#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
 
 /* I2C mapping from board specific function*/
-#define I2C_PORT_THERMAL	I2C_PORT_AP_HDMI
+#define I2C_PORT_THERMAL I2C_PORT_AP_HDMI
 
 #ifndef __ASSEMBLER__
 
-
 void ps2_pwr_en_interrupt(enum gpio_signal signal);
 
 enum adc_channel {
@@ -118,11 +117,7 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum usba_port {
-	USBA_PORT_A0 = 0,
-	USBA_PORT_A1,
-	USBA_PORT_COUNT
-};
+enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT };
 
 /*****************************************************************************
  * CBI EC FW Configuration
@@ -172,40 +167,32 @@ enum ec_cfg_usb_db_type {
 
 #include "cbi_ec_fw_config.h"
 
-#define HAS_USBC1_RETIMER_PS8802 \
-			(BIT(MORPHIUS_DB_T_OPT3_USBC_HDMI_MSTHUB))
+#define HAS_USBC1_RETIMER_PS8802 (BIT(MORPHIUS_DB_T_OPT3_USBC_HDMI_MSTHUB))
 
 static inline bool ec_config_has_usbc1_retimer_ps8802(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_USBC1_RETIMER_PS8802);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_USBC1_RETIMER_PS8802);
 }
 
-#define HAS_USBC1_RETIMER_PS8818 \
-			(BIT(MORPHIUS_DB_T_OPT1_USBC_HDMI))
+#define HAS_USBC1_RETIMER_PS8818 (BIT(MORPHIUS_DB_T_OPT1_USBC_HDMI))
 
 static inline bool ec_config_has_usbc1_retimer_ps8818(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_USBC1_RETIMER_PS8818);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_USBC1_RETIMER_PS8818);
 }
 
-#define HAS_HDMI_RETIMER_PI3HDX1204 \
-			(BIT(MORPHIUS_DB_T_OPT1_USBC_HDMI))
+#define HAS_HDMI_RETIMER_PI3HDX1204 (BIT(MORPHIUS_DB_T_OPT1_USBC_HDMI))
 
 static inline bool ec_config_has_hdmi_retimer_pi3hdx1204(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_HDMI_RETIMER_PI3HDX1204);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_HDMI_RETIMER_PI3HDX1204);
 }
 
-#define HAS_MST_HUB_RTD2141B \
-			(BIT(MORPHIUS_DB_T_OPT3_USBC_HDMI_MSTHUB))
+#define HAS_MST_HUB_RTD2141B (BIT(MORPHIUS_DB_T_OPT3_USBC_HDMI_MSTHUB))
 
 static inline bool ec_config_has_mst_hub_rtd2141b(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_MST_HUB_RTD2141B);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_MST_HUB_RTD2141B);
 }
 
 void motion_interrupt(enum gpio_signal signal);
@@ -219,12 +206,11 @@ void motion_interrupt(enum gpio_signal signal);
 int board_usbc_port_to_hpd_gpio_or_ioex(int port);
 #define PORT_TO_HPD(port) board_usbc_port_to_hpd_gpio_or_ioex(port)
 
-extern const struct usb_mux usbc0_pi3dpx1207_usb_retimer;
-extern const struct usb_mux usbc1_ps8802;
+extern const struct usb_mux_chain usbc0_pi3dpx1207_usb_retimer;
 extern const struct usb_mux usbc1_ps8818;
+extern struct usb_mux usbc1_ps8802;
 extern struct usb_mux usbc1_amd_fp5_usb_mux;
 
 #endif /* !__ASSEMBLER__ */
 
-
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/morphius/build.mk b/board/morphius/build.mk
index 4c2a6c5546..d6a15192ec 100644
--- a/board/morphius/build.mk
+++ b/board/morphius/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/morphius/ec.tasklist b/board/morphius/ec.tasklist
index 41b83cf4f3..4bb60ed55d 100644
--- a/board/morphius/ec.tasklist
+++ b/board/morphius/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/morphius/gpio.inc b/board/morphius/gpio.inc
index f14c56c66f..0597419c63 100644
--- a/board/morphius/gpio.inc
+++ b/board/morphius/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/morphius/led.c b/board/morphius/led.c
index 5e72653fe3..23f715da02 100644
--- a/board/morphius/led.c
+++ b/board/morphius/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,8 +17,8 @@
 #include "timer.h"
 #include "util.h"
 
-#define LED_BAT_OFF_LVL	0
-#define LED_BAT_ON_LVL	1
+#define LED_BAT_OFF_LVL 0
+#define LED_BAT_ON_LVL 1
 #define LED_BAT_S3_OFF_TIME_MS 3000
 #define LED_BAT_S3_PWM_RESCALE 5
 #define LED_BAT_S3_TICK_MS 50
@@ -34,10 +34,8 @@
 
 static int ticks;
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -45,13 +43,13 @@ enum led_color {
 	LED_OFF = 0,
 	LED_WHITE,
 	LED_AMBER,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 /* PWM brightness vs. color, in the order of off, white */
 static const uint8_t color_brightness[2] = {
-	[LED_OFF]   = 0,
-	[LED_WHITE]   = 100,
+	[LED_OFF] = 0,
+	[LED_WHITE] = 100,
 };
 
 void led_set_color_power(enum led_color color)
@@ -111,10 +109,10 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 	} else if (led_id == EC_LED_ID_POWER_LED) {
 		if (brightness[EC_LED_COLOR_WHITE] != 0)
 			pwm_set_duty(PWM_CH_POWER_LED,
-						color_brightness[LED_WHITE]);
+				     color_brightness[LED_WHITE]);
 		else
 			pwm_set_duty(PWM_CH_POWER_LED,
-						color_brightness[LED_OFF]);
+				     color_brightness[LED_OFF]);
 	}
 
 	return EC_SUCCESS;
@@ -133,8 +131,8 @@ static void suspend_led_update_deferred(void)
 	if (ticks <= TICKS_STEP2_DIMMER) {
 		pwm_set_duty(PWM_CH_POWER_LED, ticks * LED_BAT_S3_PWM_RESCALE);
 	} else if (ticks <= TICKS_STEP3_OFF) {
-		pwm_set_duty(PWM_CH_POWER_LED,
-					(TICKS_STEP3_OFF - ticks) * LED_BAT_S3_PWM_RESCALE);
+		pwm_set_duty(PWM_CH_POWER_LED, (TICKS_STEP3_OFF - ticks) *
+						       LED_BAT_S3_PWM_RESCALE);
 	} else {
 		ticks = TICKS_STEP1_BRIGHTER;
 		delay = LED_BAT_S3_OFF_TIME_MS * MSEC;
@@ -161,7 +159,6 @@ DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, suspend_led_deinit, HOOK_PRIO_DEFAULT);
 static void led_set_battery(void)
 {
 	static int battery_ticks;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
@@ -177,11 +174,11 @@ static void led_set_battery(void)
 		led_set_color_battery(LED_WHITE);
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			led_set_color_battery(
-				(battery_ticks & 0x4) ? LED_AMBER : LED_OFF);
-		else
-			led_set_color_battery(LED_WHITE);
+		led_set_color_battery(LED_WHITE);
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		led_set_color_battery((battery_ticks & 0x4) ? LED_AMBER :
+							      LED_OFF);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
@@ -204,9 +201,10 @@ static void led_set_power(void)
 			power_ticks = 0;
 
 		while (blink_ticks < LED_PWR_TICKS_PER_CYCLE) {
-			led_set_color_power(
-				(power_ticks % LED_TOTAL_TICKS) < LED_ON_TICKS ?
-				LED_WHITE : LED_OFF);
+			led_set_color_power((power_ticks % LED_TOTAL_TICKS) <
+							    LED_ON_TICKS ?
+						    LED_WHITE :
+						    LED_OFF);
 
 			previous_state_suspend = 1;
 			return;
diff --git a/board/morphius/thermal.c b/board/morphius/thermal.c
index a51dee7c8b..2ffc2d105b 100644
--- a/board/morphius/thermal.c
+++ b/board/morphius/thermal.c
@@ -1,8 +1,9 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "builtin/assert.h"
 #include "chipset.h"
 #include "common.h"
 #include "console.h"
@@ -20,7 +21,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_THERMAL, outstr)
-#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
 
 struct fan_step {
 	/*
@@ -44,316 +45,315 @@ static const struct fan_step *fan_step_table;
 static const struct fan_step fan1_table_clamshell[] = {
 	{
 		/* level 0 */
-		.on = {-1, -1, -1, -1},
-		.off = {-1, -1, -1, -1},
-		.rpm = {0},
+		.on = { -1, -1, -1, -1 },
+		.off = { -1, -1, -1, -1 },
+		.rpm = { 0 },
 	},
 	{
 		/* level 1 */
-		.on = {-1, -1, 40, -1},
-		.off = {-1, -1, 31, -1},
-		.rpm = {1900},
+		.on = { -1, -1, 40, -1 },
+		.off = { -1, -1, 31, -1 },
+		.rpm = { 1900 },
 	},
 	{
 		/* level 2 */
-		.on = {-1, -1, 45, -1},
-		.off = {-1, -1, 43, -1},
-		.rpm = {2900},
+		.on = { -1, -1, 45, -1 },
+		.off = { -1, -1, 43, -1 },
+		.rpm = { 2900 },
 	},
 	{
 		/* level 3 */
-		.on = {-1, -1, 48, -1},
-		.off = {-1, -1, 46, -1},
-		.rpm = {3200},
+		.on = { -1, -1, 48, -1 },
+		.off = { -1, -1, 46, -1 },
+		.rpm = { 3200 },
 	},
 	{
 		/* level 4 */
-		.on = {-1, -1, 51, -1},
-		.off = {-1, -1, 49, -1},
-		.rpm = {3550},
+		.on = { -1, -1, 51, -1 },
+		.off = { -1, -1, 49, -1 },
+		.rpm = { 3550 },
 	},
 	{
 		/* level 5 */
-		.on = {-1, -1, 54, -1},
-		.off = {-1, -1, 52, -1},
-		.rpm = {3950},
+		.on = { -1, -1, 54, -1 },
+		.off = { -1, -1, 52, -1 },
+		.rpm = { 3950 },
 	},
 	{
 		/* level 6 */
-		.on = {-1, -1, 57, -1},
-		.off = {-1, -1, 55, -1},
-		.rpm = {4250},
+		.on = { -1, -1, 57, -1 },
+		.off = { -1, -1, 55, -1 },
+		.rpm = { 4250 },
 	},
 	{
 		/* level 7 */
-		.on = {-1, -1, 60, -1},
-		.off = {-1, -1, 58, -1},
-		.rpm = {4650},
+		.on = { -1, -1, 60, -1 },
+		.off = { -1, -1, 58, -1 },
+		.rpm = { 4650 },
 	},
 };
 
 static const struct fan_step fan1_table_tablet[] = {
 	{
 		/* level 0 */
-		.on = {-1, -1, -1, -1},
-		.off = {-1, -1, -1, -1},
-		.rpm = {0},
+		.on = { -1, -1, -1, -1 },
+		.off = { -1, -1, -1, -1 },
+		.rpm = { 0 },
 	},
 	{
 		/* level 1 */
-		.on = {-1, -1, 41, -1},
-		.off = {-1, -1, 31, -1},
-		.rpm = {2100},
+		.on = { -1, -1, 41, -1 },
+		.off = { -1, -1, 31, -1 },
+		.rpm = { 2100 },
 	},
 	{
 		/* level 2 */
-		.on = {-1, -1, 50, -1},
-		.off = {-1, -1, 48, -1},
-		.rpm = {2600},
+		.on = { -1, -1, 50, -1 },
+		.off = { -1, -1, 48, -1 },
+		.rpm = { 2600 },
 	},
 	{
 		/* level 3 */
-		.on = {-1, -1, 54, -1},
-		.off = {-1, -1, 52, -1},
-		.rpm = {2800},
+		.on = { -1, -1, 54, -1 },
+		.off = { -1, -1, 52, -1 },
+		.rpm = { 2800 },
 	},
 	{
 		/* level 4 */
-		.on = {-1, -1, 57, -1},
-		.off = {-1, -1, 55, -1},
-		.rpm = {3300},
+		.on = { -1, -1, 57, -1 },
+		.off = { -1, -1, 55, -1 },
+		.rpm = { 3300 },
 	},
 	{
 		/* level 5 */
-		.on = {-1, -1, 60, -1},
-		.off = {-1, -1, 58, -1},
-		.rpm = {3800},
+		.on = { -1, -1, 60, -1 },
+		.off = { -1, -1, 58, -1 },
+		.rpm = { 3800 },
 	},
 	{
 		/* level 6 */
-		.on = {-1, -1, 72, -1},
-		.off = {-1, -1, 69, -1},
-		.rpm = {4000},
+		.on = { -1, -1, 72, -1 },
+		.off = { -1, -1, 69, -1 },
+		.rpm = { 4000 },
 	},
 	{
 		/* level 7 */
-		.on = {-1, -1, 74, -1},
-		.off = {-1, -1, 73, -1},
-		.rpm = {4300},
+		.on = { -1, -1, 74, -1 },
+		.off = { -1, -1, 73, -1 },
+		.rpm = { 4300 },
 	},
 };
 
 static const struct fan_step fan1_table_stand[] = {
 	{
 		/* level 0 */
-		.on = {-1, -1, -1, -1},
-		.off = {-1, -1, -1, -1},
-		.rpm = {0},
+		.on = { -1, -1, -1, -1 },
+		.off = { -1, -1, -1, -1 },
+		.rpm = { 0 },
 	},
 	{
 		/* level 1 */
-		.on = {-1, -1, 34, -1},
-		.off = {-1, -1, 31, -1},
-		.rpm = {1850},
+		.on = { -1, -1, 34, -1 },
+		.off = { -1, -1, 31, -1 },
+		.rpm = { 1850 },
 	},
 	{
 		/* level 2 */
-		.on = {-1, -1, 42, -1},
-		.off = {-1, -1, 39, -1},
-		.rpm = {2550},
+		.on = { -1, -1, 42, -1 },
+		.off = { -1, -1, 39, -1 },
+		.rpm = { 2550 },
 	},
 	{
 		/* level 3 */
-		.on = {-1, -1, 49, -1},
-		.off = {-1, -1, 48, -1},
-		.rpm = {2900},
+		.on = { -1, -1, 49, -1 },
+		.off = { -1, -1, 48, -1 },
+		.rpm = { 2900 },
 	},
 	{
 		/* level 4 */
-		.on = {-1, -1, 51, -1},
-		.off = {-1, -1, 50, -1},
-		.rpm = {3350},
+		.on = { -1, -1, 51, -1 },
+		.off = { -1, -1, 50, -1 },
+		.rpm = { 3350 },
 	},
 	{
 		/* level 5 */
-		.on = {-1, -1, 53, -1},
-		.off = {-1, -1, 52, -1},
-		.rpm = {3700},
+		.on = { -1, -1, 53, -1 },
+		.off = { -1, -1, 52, -1 },
+		.rpm = { 3700 },
 	},
 	{
 		/* level 6 */
-		.on = {-1, -1, 55, -1},
-		.off = {-1, -1, 54, -1},
-		.rpm = {3900},
+		.on = { -1, -1, 55, -1 },
+		.off = { -1, -1, 54, -1 },
+		.rpm = { 3900 },
 	},
 	{
 		/* level 7 */
-		.on = {-1, -1, 57, -1},
-		.off = {-1, -1, 56, -1},
-		.rpm = {4250},
+		.on = { -1, -1, 57, -1 },
+		.off = { -1, -1, 56, -1 },
+		.rpm = { 4250 },
 	},
 };
 
 static const struct fan_step fan0_table_clamshell[] = {
 	{
 		/* level 0 */
-		.on = {-1, -1, -1, -1},
-		.off = {-1, -1, -1, -1},
-		.rpm = {0},
+		.on = { -1, -1, -1, -1 },
+		.off = { -1, -1, -1, -1 },
+		.rpm = { 0 },
 	},
 	{
 		/* level 1 */
-		.on = {-1, -1, 41, -1},
-		.off = {-1, -1, 31, -1},
-		.rpm = {2350},
+		.on = { -1, -1, 41, -1 },
+		.off = { -1, -1, 31, -1 },
+		.rpm = { 2350 },
 	},
 	{
 		/* level 2 */
-		.on = {-1, -1, 44, -1},
-		.off = {-1, -1, 42, -1},
-		.rpm = {3300},
+		.on = { -1, -1, 44, -1 },
+		.off = { -1, -1, 42, -1 },
+		.rpm = { 3300 },
 	},
 	{
 		/* level 3 */
-		.on = {-1, -1, 47, -1},
-		.off = {-1, -1, 45, -1},
-		.rpm = {3600},
+		.on = { -1, -1, 47, -1 },
+		.off = { -1, -1, 45, -1 },
+		.rpm = { 3600 },
 	},
 	{
 		/* level 4 */
-		.on = {-1, -1, 50, -1},
-		.off = {-1, -1, 48, -1},
-		.rpm = {4050},
+		.on = { -1, -1, 50, -1 },
+		.off = { -1, -1, 48, -1 },
+		.rpm = { 4050 },
 	},
 	{
 		/* level 5 */
-		.on = {-1, -1, 53, -1},
-		.off = {-1, -1, 51, -1},
-		.rpm = {4450},
+		.on = { -1, -1, 53, -1 },
+		.off = { -1, -1, 51, -1 },
+		.rpm = { 4450 },
 	},
 	{
 		/* level 6 */
-		.on = {-1, -1, 56, -1},
-		.off = {-1, -1, 54, -1},
-		.rpm = {4750},
+		.on = { -1, -1, 56, -1 },
+		.off = { -1, -1, 54, -1 },
+		.rpm = { 4750 },
 	},
 	{
 		/* level 7 */
-		.on = {-1, -1, 59, -1},
-		.off = {-1, -1, 57, -1},
-		.rpm = {5150},
+		.on = { -1, -1, 59, -1 },
+		.off = { -1, -1, 57, -1 },
+		.rpm = { 5150 },
 	},
 };
 
 static const struct fan_step fan0_table_tablet[] = {
 	{
 		/* level 0 */
-		.on = {-1, -1, -1, -1},
-		.off = {-1, -1, -1, -1},
-		.rpm = {0},
+		.on = { -1, -1, -1, -1 },
+		.off = { -1, -1, -1, -1 },
+		.rpm = { 0 },
 	},
 	{
 		/* level 1 */
-		.on = {-1, -1, 41, -1},
-		.off = {-1, -1, 31, -1},
-		.rpm = {2250},
+		.on = { -1, -1, 41, -1 },
+		.off = { -1, -1, 31, -1 },
+		.rpm = { 2250 },
 	},
 	{
 		/* level 2 */
-		.on = {-1, -1, 50, -1},
-		.off = {-1, -1, 48, -1},
-		.rpm = {2850},
+		.on = { -1, -1, 50, -1 },
+		.off = { -1, -1, 48, -1 },
+		.rpm = { 2850 },
 	},
 	{
 		/* level 3 */
-		.on = {-1, -1, 54, -1},
-		.off = {-1, -1, 51, -1},
-		.rpm = {3100},
+		.on = { -1, -1, 54, -1 },
+		.off = { -1, -1, 51, -1 },
+		.rpm = { 3100 },
 	},
 	{
 		/* level 4 */
-		.on = {-1, -1, 57, -1},
-		.off = {-1, -1, 55, -1},
-		.rpm = {3500},
+		.on = { -1, -1, 57, -1 },
+		.off = { -1, -1, 55, -1 },
+		.rpm = { 3500 },
 	},
 	{
 		/* level 5 */
-		.on = {-1, -1, 60, -1},
-		.off = {-1, -1, 58, -1},
-		.rpm = {3900},
+		.on = { -1, -1, 60, -1 },
+		.off = { -1, -1, 58, -1 },
+		.rpm = { 3900 },
 	},
 	{
 		/* level 6 */
-		.on = {-1, -1, 72, -1},
-		.off = {-1, -1, 69, -1},
-		.rpm = {4150},
+		.on = { -1, -1, 72, -1 },
+		.off = { -1, -1, 69, -1 },
+		.rpm = { 4150 },
 	},
 	{
 		/* level 7 */
-		.on = {-1, -1, 74, -1},
-		.off = {-1, -1, 73, -1},
-		.rpm = {4400},
+		.on = { -1, -1, 74, -1 },
+		.off = { -1, -1, 73, -1 },
+		.rpm = { 4400 },
 	},
 };
 
 static const struct fan_step fan0_table_stand[] = {
 	{
 		/* level 0 */
-		.on = {-1, -1, -1, -1},
-		.off = {-1, -1, -1, -1},
-		.rpm = {0},
+		.on = { -1, -1, -1, -1 },
+		.off = { -1, -1, -1, -1 },
+		.rpm = { 0 },
 	},
 	{
 		/* level 1 */
-		.on = {-1, -1, 34, -1},
-		.off = {-1, -1, 31, -1},
-		.rpm = {2250},
+		.on = { -1, -1, 34, -1 },
+		.off = { -1, -1, 31, -1 },
+		.rpm = { 2250 },
 	},
 	{
 		/* level 2 */
-		.on = {-1, -1, 42, -1},
-		.off = {-1, -1, 39, -1},
-		.rpm = {2800},
+		.on = { -1, -1, 42, -1 },
+		.off = { -1, -1, 39, -1 },
+		.rpm = { 2800 },
 	},
 	{
 		/* level 3 */
-		.on = {-1, -1, 49, -1},
-		.off = {-1, -1, 48, -1},
-		.rpm = {3150},
+		.on = { -1, -1, 49, -1 },
+		.off = { -1, -1, 48, -1 },
+		.rpm = { 3150 },
 	},
 	{
 		/* level 4 */
-		.on = {-1, -1, 51, -1},
-		.off = {-1, -1, 50, -1},
-		.rpm = {3550},
+		.on = { -1, -1, 51, -1 },
+		.off = { -1, -1, 50, -1 },
+		.rpm = { 3550 },
 	},
 	{
 		/* level 5 */
-		.on = {-1, -1, 53, -1},
-		.off = {-1, -1, 52, -1},
-		.rpm = {3900},
+		.on = { -1, -1, 53, -1 },
+		.off = { -1, -1, 52, -1 },
+		.rpm = { 3900 },
 	},
 	{
 		/* level 6 */
-		.on = {-1, -1, 55, -1},
-		.off = {-1, -1, 54, -1},
-		.rpm = {4150},
+		.on = { -1, -1, 55, -1 },
+		.off = { -1, -1, 54, -1 },
+		.rpm = { 4150 },
 	},
 	{
 		/* level 7 */
-		.on = {-1, -1, 57, -1},
-		.off = {-1, -1, 56, -1},
-		.rpm = {4400},
+		.on = { -1, -1, 57, -1 },
+		.off = { -1, -1, 56, -1 },
+		.rpm = { 4400 },
 	},
 };
 
 #define NUM_FAN_LEVELS ARRAY_SIZE(fan1_table_clamshell)
 
-#define lid_angle_tablet	340
+#define lid_angle_tablet 340
 static int throttle_on;
 
-BUILD_ASSERT(ARRAY_SIZE(fan1_table_clamshell) ==
-	ARRAY_SIZE(fan1_table_tablet));
+BUILD_ASSERT(ARRAY_SIZE(fan1_table_clamshell) == ARRAY_SIZE(fan1_table_tablet));
 
 #define average_time 60
 int fan_table_to_rpm(int fan, int *temp)
@@ -404,7 +404,7 @@ int fan_table_to_rpm(int fan, int *temp)
 	for (j = 0; j < average_time; j++)
 		avg_sum = avg_sum + avg_calc_tmp[TEMP_SENSOR_CPU][j];
 
-	avg_tmp[TEMP_SENSOR_CPU] = avg_sum/average_time;
+	avg_tmp[TEMP_SENSOR_CPU] = avg_sum / average_time;
 
 	/*
 	 * Compare the current and previous temperature, we have
@@ -416,10 +416,10 @@ int fan_table_to_rpm(int fan, int *temp)
 	if (avg_tmp[TEMP_SENSOR_CPU] < prev_tmp[TEMP_SENSOR_CPU]) {
 		for (i = current_level; i >= 0; i--) {
 			if (avg_tmp[TEMP_SENSOR_CPU] <
-				fan_step_table[i].off[TEMP_SENSOR_CPU]) {
-			/*
-			 * fan step down debounce
-			 */
+			    fan_step_table[i].off[TEMP_SENSOR_CPU]) {
+				/*
+				 * fan step down debounce
+				 */
 				if (fan_down_count < 10) {
 					fan_down_count++;
 					fan_up_count = 0;
@@ -434,12 +434,12 @@ int fan_table_to_rpm(int fan, int *temp)
 				break;
 		}
 	} else if (avg_tmp[TEMP_SENSOR_CPU] > prev_tmp[TEMP_SENSOR_CPU]) {
-		for (i = current_level+1; i < NUM_FAN_LEVELS; i++) {
+		for (i = current_level + 1; i < NUM_FAN_LEVELS; i++) {
 			if ((avg_tmp[TEMP_SENSOR_CPU] >
-				 fan_step_table[i].on[TEMP_SENSOR_CPU])) {
-			/*
-			 * fan step up debounce
-			 */
+			     fan_step_table[i].on[TEMP_SENSOR_CPU])) {
+				/*
+				 * fan step up debounce
+				 */
 				if (fan_up_count < 10) {
 					fan_up_count++;
 					fan_down_count = 0;
@@ -499,10 +499,8 @@ void thermal_protect(void)
 	int rv1, rv2;
 	int thermal_sensor1, thermal_sensor2;
 
-	rv1 = temp_sensor_read(TEMP_SENSOR_5V_REGULATOR,
-				   &thermal_sensor1);
-	rv2 = temp_sensor_read(TEMP_SENSOR_CPU,
-				   &thermal_sensor2);
+	rv1 = temp_sensor_read(TEMP_SENSOR_5V_REGULATOR, &thermal_sensor1);
+	rv2 = temp_sensor_read(TEMP_SENSOR_CPU, &thermal_sensor2);
 
 	if (rv2 == EC_SUCCESS) {
 		if ((!lid_is_open()) && (!extpower_is_present())) {
@@ -523,8 +521,8 @@ void thermal_protect(void)
 	}
 
 	if (rv1 == EC_SUCCESS) {
-		if ((!lid_is_open()) && (!extpower_is_present())
-			&& thermal_sensor1 > C_TO_K(51))
+		if ((!lid_is_open()) && (!extpower_is_present()) &&
+		    thermal_sensor1 > C_TO_K(51))
 			chipset_force_shutdown(CHIPSET_SHUTDOWN_THERMAL);
 	}
 }
diff --git a/board/mrbland/base_detect.c b/board/mrbland/base_detect.c
index 70217868ea..82326ab456 100644
--- a/board/mrbland/base_detect.c
+++ b/board/mrbland/base_detect.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,8 +20,8 @@
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
 /* Make sure POGO VBUS starts later then PP3300_HUB when power on  */
 #define BASE_DETECT_EN_LATER_US (600 * MSEC)
@@ -85,7 +85,7 @@ static void base_detect_change(enum base_status status)
 {
 	int connected = (status == BASE_CONNECTED);
 	bool base_enable_allow =
-	    !chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF);
+		!chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF);
 
 	if ((current_base_status == status) &&
 	    (current_base_enable_allow == base_enable_allow))
@@ -109,8 +109,8 @@ static uint32_t pulse_width;
 
 static void print_base_detect_value(int v, int tmp_pulse_width)
 {
-	CPRINTS("%s = %d (pulse %d)", adc_channels[ADC_BASE_DET].name,
-			v, tmp_pulse_width);
+	CPRINTS("%s = %d (pulse %d)", adc_channels[ADC_BASE_DET].name, v,
+		tmp_pulse_width);
 }
 
 static void base_detect_deferred(void)
@@ -202,8 +202,7 @@ static void base_enable(void)
 {
 	/* Enable base detection interrupt. */
 	base_detect_debounce_time = get_time().val;
-	hook_call_deferred(&base_detect_deferred_data,
-			BASE_DETECT_EN_LATER_US);
+	hook_call_deferred(&base_detect_deferred_data, BASE_DETECT_EN_LATER_US);
 	gpio_enable_interrupt(GPIO_BASE_DET_L);
 }
 DECLARE_HOOK(HOOK_CHIPSET_STARTUP, base_enable, HOOK_PRIO_DEFAULT);
@@ -228,7 +227,7 @@ static void base_init(void)
 	if (system_jumped_late() && chipset_in_state(CHIPSET_STATE_ON))
 		base_enable();
 }
-DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT+1);
+DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT + 1);
 
 void base_force_state(enum ec_set_base_state_cmd state)
 {
diff --git a/board/mrbland/battery.c b/board/mrbland/battery.c
index ee58ff70bb..d6dda523be 100644
--- a/board/mrbland/battery.c
+++ b/board/mrbland/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/mrbland/board.c b/board/mrbland/board.c
index dd56bcd0cc..50ba008512 100644
--- a/board/mrbland/board.c
+++ b/board/mrbland/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -39,10 +39,10 @@
 #include "task.h"
 #include "usbc_ppc.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define KS_DEBOUNCE_US    (30 * MSEC)  /* Debounce time for kickstand switch */
+#define KS_DEBOUNCE_US (30 * MSEC) /* Debounce time for kickstand switch */
 
 /* Forward declaration */
 static void tcpc_alert_event(enum gpio_signal signal);
@@ -107,34 +107,26 @@ static void switchcap_interrupt(enum gpio_signal signal)
 
 /* I2C port map */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl  = GPIO_EC_I2C_POWER_SCL,
-		.sda  = GPIO_EC_I2C_POWER_SDA
-	},
-	{
-		.name = "tcpc0",
-		.port = I2C_PORT_TCPC0,
-		.kbps = 1000,
-		.scl  = GPIO_EC_I2C_USB_C0_PD_SCL,
-		.sda  = GPIO_EC_I2C_USB_C0_PD_SDA
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_EEPROM_SCL,
-		.sda  = GPIO_EC_I2C_EEPROM_SDA
-	},
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_SENSOR_SCL,
-		.sda  = GPIO_EC_I2C_SENSOR_SDA
-	},
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_POWER_SCL,
+	  .sda = GPIO_EC_I2C_POWER_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C0_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C0_PD_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_EEPROM_SCL,
+	  .sda = GPIO_EC_I2C_EEPROM_SDA },
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_SENSOR_SCL,
+	  .sda = GPIO_EC_I2C_SENSOR_SDA },
 };
 
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
@@ -142,45 +134,25 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* Measure VBUS through a 1/10 voltage divider */
-	[ADC_VBUS] = {
-		"VBUS",
-		NPCX_ADC_CH1,
-		ADC_MAX_VOLT * 10,
-		ADC_READ_MAX + 1,
-		0
-	},
+	[ADC_VBUS] = { "VBUS", NPCX_ADC_CH1, ADC_MAX_VOLT * 10,
+		       ADC_READ_MAX + 1, 0 },
 	/*
 	 * Adapter current output or battery charging/discharging current (uV)
 	 * 18x amplification on charger side.
 	 */
-	[ADC_AMON_BMON] = {
-		"AMON_BMON",
-		NPCX_ADC_CH2,
-		ADC_MAX_VOLT * 1000 / 18,
-		ADC_READ_MAX + 1,
-		0
-	},
+	[ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH2, ADC_MAX_VOLT * 1000 / 18,
+			    ADC_READ_MAX + 1, 0 },
 	/*
 	 * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read
 	 * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and
 	 * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we
 	 * only divide by 2 (enough to avoid precision issues).
 	 */
-	[ADC_PSYS] = {
-		"PSYS",
-		NPCX_ADC_CH3,
-		ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1),
-		2,
-		0
-	},
+	[ADC_PSYS] = { "PSYS", NPCX_ADC_CH3,
+		       ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), 2, 0 },
 	/* Base detection */
-	[ADC_BASE_DET] = {
-		"BASE_DET",
-		NPCX_ADC_CH5,
-		ADC_MAX_VOLT,
-		ADC_READ_MAX + 1,
-		0
-	},
+	[ADC_BASE_DET] = { "BASE_DET", NPCX_ADC_CH5, ADC_MAX_VOLT,
+			   ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
@@ -198,11 +170,9 @@ const struct ln9310_config_t ln9310_config = {
 
 /* Power Path Controller */
 struct ppc_config_t ppc_chips[] = {
-	{
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
+	{ .i2c_port = I2C_PORT_TCPC0,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
 };
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
@@ -225,11 +195,14 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
  * to AP. But the TCPC chip is also needed to know the HPD status; otherwise,
  * the mux misbehaves.
  */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	},
 };
 
@@ -256,17 +229,13 @@ enum lid_accelgyro_type {
 static enum lid_accelgyro_type lid_accelgyro_config;
 
 /* Matrix to rotate accelerometer into standard reference frame */
-const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+				      { 0, FLOAT_TO_FP(1), 0 },
+				      { 0, 0, FLOAT_TO_FP(1) } };
 
-const mat33_fp_t lid_standard_ref_icm42607 = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t lid_standard_ref_icm42607 = { { 0, FLOAT_TO_FP(-1), 0 },
+					       { FLOAT_TO_FP(1), 0, 0 },
+					       { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t icm42607_lid_accel = {
 	.name = "Lid Accel",
@@ -458,9 +427,9 @@ void board_tcpc_init(void)
 	 */
 	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
 		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
 
 void board_hibernate(void)
 {
@@ -470,8 +439,7 @@ void board_hibernate(void)
 	 * Sensors are unpowered in hibernate. Apply PD to the
 	 * interrupt lines such that they don't float.
 	 */
-	gpio_set_flags(GPIO_ACCEL_GYRO_INT_L,
-		       GPIO_INPUT | GPIO_PULL_DOWN);
+	gpio_set_flags(GPIO_ACCEL_GYRO_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
 
 	/*
 	 * Board rev 1+ has the hardware fix. Don't need the following
@@ -566,8 +534,7 @@ void board_overcurrent_event(int port, int is_overcurrented)
 
 int board_set_active_charge_port(int port)
 {
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	int i;
 
 	if (!is_real_port && port != CHARGE_PORT_NONE)
@@ -595,7 +562,6 @@ int board_set_active_charge_port(int port)
 		return EC_ERROR_INVAL;
 	}
 
-
 	CPRINTS("New charge port: p%d", port);
 
 	/*
@@ -619,24 +585,22 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	/*
 	 * Ignore lower charge ceiling on PD transition if our battery is
 	 * critical, as we may brownout.
 	 */
-	if (supplier == CHARGE_SUPPLIER_PD &&
-	    charge_ma < 1500 &&
+	if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 &&
 	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
 		CPRINTS("Using max ilim %d", max_ma);
 		charge_ma = max_ma;
 	}
 
 	charge_ma = charge_ma * 95 / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 uint16_t tcpc_get_alert_status(void)
diff --git a/board/mrbland/board.h b/board/mrbland/board.h
index bac5bf0ee1..0f78db50d9 100644
--- a/board/mrbland/board.h
+++ b/board/mrbland/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,13 +13,13 @@
 #define CONFIG_BUTTON_TRIGGERED_RECOVERY
 
 /* Internal SPI flash on NPCX7 */
-#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)  /* 512KB internal spi flash */
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */
 
 /* Switchcap */
 #define CONFIG_LN9310
 
 /* Battery */
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY  "LION"
+#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
 #define CONFIG_BATTERY_REVIVE_DISCONNECT
 #define CONFIG_BATTERY_FUEL_GAUGE
 #define CONFIG_BATTERY_VENDOR_PARAM
@@ -40,7 +40,7 @@
 
 /* I2C */
 #undef I2C_PORT_TCPC0
-#define I2C_PORT_TCPC0   NPCX_I2C_PORT2_0
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT2_0
 
 /* Lid accel/gyro */
 #define CONFIG_ACCELGYRO_BMI160
@@ -86,10 +86,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_DISPLIGHT = 0,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_DISPLIGHT = 0, PWM_CH_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
diff --git a/board/mrbland/build.mk b/board/mrbland/build.mk
index 452abeb591..363ef59a16 100644
--- a/board/mrbland/build.mk
+++ b/board/mrbland/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/mrbland/ec.tasklist b/board/mrbland/ec.tasklist
index 493c39dc6c..fc40a8b684 100644
--- a/board/mrbland/ec.tasklist
+++ b/board/mrbland/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/mrbland/gpio.inc b/board/mrbland/gpio.inc
index 6d09e87688..b5ff32f0b8 100644
--- a/board/mrbland/gpio.inc
+++ b/board/mrbland/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/mrbland/led.c b/board/mrbland/led.c
index a8d2fcda30..07994b8f51 100644
--- a/board/mrbland/led.c
+++ b/board/mrbland/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -38,15 +38,15 @@ enum led_color {
 	LED_GREEN,
 	LED_AMBER,
 	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static void led_set_color_battery(enum led_color color)
 {
 	gpio_set_level(GPIO_EC_CHG_LED_R_C0,
-		(color == LED_RED) ? BAT_LED_ON : BAT_LED_OFF);
+		       (color == LED_RED) ? BAT_LED_ON : BAT_LED_OFF);
 	gpio_set_level(GPIO_EC_CHG_LED_G_C0,
-		(color == LED_GREEN) ? BAT_LED_ON : BAT_LED_OFF);
+		       (color == LED_GREEN) ? BAT_LED_ON : BAT_LED_OFF);
 	if (color == LED_AMBER) {
 		gpio_set_level(GPIO_EC_CHG_LED_R_C0, BAT_LED_ON);
 		gpio_set_level(GPIO_EC_CHG_LED_G_C0, BAT_LED_ON);
@@ -56,7 +56,7 @@ static void led_set_color_battery(enum led_color color)
 static void led_set_color_power(enum led_color color)
 {
 	gpio_set_level(GPIO_EC_PWRBTN_LED,
-		(color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF);
+		       (color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF);
 }
 
 void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
@@ -97,7 +97,6 @@ static void board_led_set_battery(void)
 	int color = LED_OFF;
 	int period = 0;
 	int percent = DIV_ROUND_NEAREST(charge_get_display_charge(), 10);
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
@@ -105,13 +104,13 @@ static void board_led_set_battery(void)
 	case PWR_STATE_CHARGE:
 	case PWR_STATE_CHARGE_NEAR_FULL:
 		if (chipset_in_state(CHIPSET_STATE_ON |
-					CHIPSET_STATE_ANY_SUSPEND |
-					CHIPSET_STATE_ANY_OFF)) {
+				     CHIPSET_STATE_ANY_SUSPEND |
+				     CHIPSET_STATE_ANY_OFF)) {
 			if (percent <= BATTERY_LEVEL_CRITICAL) {
 				/* battery capa <= 5%, Red */
 				color = LED_RED;
 			} else if (percent > BATTERY_LEVEL_CRITICAL &&
-					percent < BATTERY_LEVEL_NEAR_FULL) {
+				   percent < BATTERY_LEVEL_NEAR_FULL) {
 				/* 5% < battery capa < 97%, Orange */
 				color = LED_AMBER;
 			} else {
@@ -133,16 +132,16 @@ static void board_led_set_battery(void)
 			color = LED_OFF;
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE) {
-			/* Factory mode, Red 2 sec, green 2 sec */
-			period = (2 + 2) * LED_ONE_SEC;
-			battery_ticks = battery_ticks % period;
-			if (battery_ticks < 2 * LED_ONE_SEC)
-				color = LED_RED;
-			else
-				color = LED_GREEN;
-		} else
+		color = LED_RED;
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		/* Factory mode, Red 2 sec, green 2 sec */
+		period = (2 + 2) * LED_ONE_SEC;
+		battery_ticks = battery_ticks % period;
+		if (battery_ticks < 2 * LED_ONE_SEC)
 			color = LED_RED;
+		else
+			color = LED_GREEN;
 		break;
 	default:
 		/* Other states don't alter LED behavior */
@@ -203,7 +202,7 @@ void led_control(enum ec_led_id led_id, enum ec_led_state state)
 	enum led_color color;
 
 	if ((led_id != EC_LED_ID_RECOVERY_HW_REINIT_LED) &&
-		(led_id != EC_LED_ID_SYSRQ_DEBUG_LED))
+	    (led_id != EC_LED_ID_SYSRQ_DEBUG_LED))
 		return;
 
 	if (state == LED_STATE_RESET) {
diff --git a/board/mrbland/usbc_config.c b/board/mrbland/usbc_config.c
index aac136415d..5d30adb6e2 100644
--- a/board/mrbland/usbc_config.c
+++ b/board/mrbland/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,8 @@
 #include "console.h"
 #include "usb_pd.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 const struct charger_config_t chg_chips[] = {
 	{
diff --git a/board/munna/battery.c b/board/munna/battery.c
index 1b162e93c7..1f5be3dbe3 100644
--- a/board/munna/battery.c
+++ b/board/munna/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/munna/board.c b/board/munna/board.c
index 8eca3f61f1..f6996b8460 100644
--- a/board/munna/board.c
+++ b/board/munna/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -31,6 +31,7 @@
 #include "keyboard_scan.h"
 #include "keyboard_backlight.h"
 #include "lid_switch.h"
+#include "panic.h"
 #include "power.h"
 #include "power_button.h"
 #include "registers.h"
@@ -44,8 +45,8 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
@@ -57,42 +58,36 @@ static void tcpc_alert_event(enum gpio_signal signal)
 /******************************************************************************/
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] = {"BOARD_ID", 3300, 4096, 0, STM32_AIN(5),
-			   STM32_RANK(1)},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(15),
-			    STM32_RANK(2)},
+	[ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(5),
+			   STM32_RANK(1) },
+	[ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(15),
+			    STM32_RANK(2) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /******************************************************************************/
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "typec",
-		.port = 0,
-		.kbps = 400,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	},
-	{
-		.name = "other",
-		.port = 2,
-		.kbps = 400,
-		.scl  = GPIO_I2C3_SCL,
-		.sda  = GPIO_I2C3_SDA
-	},
+	{ .name = "typec",
+	  .port = 0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "other",
+	  .port = 2,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
 const struct i2c_port_t i2c_bitbang_ports[] = {
-	{
-		.name = "battery",
-		.port = 3,
-		.kbps = 100,
-		.scl = GPIO_I2C4_SCL,
-		.sda = GPIO_I2C4_SDA,
-		.drv = &bitbang_drv
-	},
+	{ .name = "battery",
+	  .port = 3,
+	  .kbps = 100,
+	  .scl = GPIO_I2C4_SCL,
+	  .sda = GPIO_I2C4_SDA,
+	  .drv = &bitbang_drv },
 };
 const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
 
@@ -100,8 +95,8 @@ const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
 
 /* power signal list.  Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
+	{ GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" },
+	{ GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" },
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
@@ -157,8 +152,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-static void board_hpd_status(const struct usb_mux *me,
-			     mux_state_t mux_state,
+static void board_hpd_status(const struct usb_mux *me, mux_state_t mux_state,
 			     bool *ack_required)
 {
 	/* This driver does not use host command ACKs */
@@ -171,13 +165,16 @@ static void board_hpd_status(const struct usb_mux *me,
 	host_set_single_event(EC_HOST_EVENT_USB_MUX);
 }
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+				.hpd_update = &board_hpd_status,
+			},
 	},
 };
 
@@ -239,12 +236,12 @@ int board_set_active_charge_port(int charge_port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-			       CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 int board_discharge_on_ac(int enable)
@@ -314,8 +311,7 @@ static void board_spi_enable(void)
 	/* Pin mux spi peripheral toward the sensor. */
 	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
 }
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP,
-	     board_spi_enable,
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_spi_enable,
 	     MOTION_SENSE_HOOK_PRIO - 1);
 
 static void board_spi_disable(void)
@@ -333,8 +329,7 @@ static void board_spi_disable(void)
 	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
 #endif
 }
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN,
-	     board_spi_disable,
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_spi_disable,
 	     MOTION_SENSE_HOOK_PRIO + 1);
 #endif /* !VARIANT_KUKUI_NO_SENSORS */
 
@@ -373,17 +368,13 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Rotation matrixes */
-static const mat33_fp_t base_standard_ref = {
-	{0, FLOAT_TO_FP(1), 0},
-	{FLOAT_TO_FP(-1), 0, 0},
-	{0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					      { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
 
-static const mat33_fp_t lid_standard_ref = {
-	{FLOAT_TO_FP(-1), 0, 0},
-	{0, FLOAT_TO_FP(1), 0},
-	{0, 0, FLOAT_TO_FP(-1) }
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, FLOAT_TO_FP(1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
 /* sensor private data */
 /* Lid accel private data */
@@ -471,7 +462,7 @@ struct motion_sensor_t motion_sensors[] = {
 const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
 const struct it8801_pwm_t it8801_pwm_channels[] = {
-	[IT8801_PWM_CH_KBLIGHT] = {.index = 4},
+	[IT8801_PWM_CH_KBLIGHT] = { .index = 4 },
 };
 
 void board_kblight_init(void)
@@ -487,11 +478,11 @@ bool board_has_kb_backlight(void)
 #endif /* !VARIANT_KUKUI_NO_SENSORS */
 
 /* Battery functions */
-#define SB_SMARTCHARGE				0x26
+#define SB_SMARTCHARGE 0x26
 /* Quick charge enable bit */
-#define SMART_QUICK_CHARGE			0x02
+#define SMART_QUICK_CHARGE 0x02
 /* Quick charge support bit */
-#define MODE_QUICK_CHARGE_SUPPORT		0x01
+#define MODE_QUICK_CHARGE_SUPPORT 0x01
 
 static void sb_quick_charge_mode(int enable)
 {
@@ -562,8 +553,8 @@ int board_get_battery_i2c(void)
 }
 
 #ifdef SECTION_IS_RW
-static int it8801_get_target_channel(enum pwm_channel *channel,
-				     int type, int index)
+static int it8801_get_target_channel(enum pwm_channel *channel, int type,
+				     int index)
 {
 	switch (type) {
 	case EC_PWM_TYPE_GENERIC:
@@ -586,14 +577,13 @@ host_command_pwm_set_duty(struct host_cmd_handler_args *args)
 	if (it8801_get_target_channel(&channel, p->pwm_type, p->index))
 		return EC_RES_INVALID_PARAM;
 
-	duty = (uint32_t) p->duty * 255 / 65535;
+	duty = (uint32_t)p->duty * 255 / 65535;
 	it8801_pwm_set_raw_duty(channel, duty);
 	it8801_pwm_enable(channel, p->duty > 0);
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_DUTY,
-		     host_command_pwm_set_duty,
+DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_DUTY, host_command_pwm_set_duty,
 		     EC_VER_MASK(0));
 
 static enum ec_status
@@ -607,12 +597,11 @@ host_command_pwm_get_duty(struct host_cmd_handler_args *args)
 	if (it8801_get_target_channel(&channel, p->pwm_type, p->index))
 		return EC_RES_INVALID_PARAM;
 
-	r->duty = (uint32_t) it8801_pwm_get_raw_duty(channel) * 65535 / 255;
+	r->duty = (uint32_t)it8801_pwm_get_raw_duty(channel) * 65535 / 255;
 	args->response_size = sizeof(*r);
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_DUTY,
-		     host_command_pwm_get_duty,
+DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_DUTY, host_command_pwm_get_duty,
 		     EC_VER_MASK(0));
 #endif
diff --git a/board/munna/board.h b/board/munna/board.h
index 322f145e33..5dc35c68df 100644
--- a/board/munna/board.h
+++ b/board/munna/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,13 +27,13 @@
 #undef STM32_PLLM
 #undef STM32_PLLN
 #undef STM32_PLLR
-#define STM32_PLLM	1
+#define STM32_PLLM 1
 #ifdef STM32_HSE_CLOCK
-#define STM32_PLLN	12
+#define STM32_PLLN 12
 #else
-#define STM32_PLLN	10
+#define STM32_PLLN 10
 #endif
-#define STM32_PLLR	2
+#define STM32_PLLR 2
 
 #define STM32_USE_PLL
 
@@ -65,13 +65,12 @@
 #define CONFIG_LED_ONOFF_STATES
 #define CONFIG_LED_POWER_LED
 
-#undef	CONFIG_WATCHDOG_PERIOD_MS
+#undef CONFIG_WATCHDOG_PERIOD_MS
 #define CONFIG_WATCHDOG_PERIOD_MS 4000
 
-
 /* Motion Sensors */
 #ifndef VARIANT_KUKUI_NO_SENSORS
-#define CONFIG_ACCEL_LIS2DWL    /* Lid accel */
+#define CONFIG_ACCEL_LIS2DWL /* Lid accel */
 #define CONFIG_ACCELGYRO_BMI160 /* Base accel */
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
@@ -93,34 +92,34 @@
 #endif /* VARIANT_KUKUI_NO_SENSORS */
 
 /* I2C ports */
-#define I2C_PORT_BC12               0
-#define I2C_PORT_TCPC0              0
-#define I2C_PORT_USB_MUX            0
-#define I2C_PORT_CHARGER            2
-#define I2C_PORT_SENSORS            2
-#define I2C_PORT_KB_DISCRETE        2
-#define I2C_PORT_VIRTUAL_BATTERY    I2C_PORT_BATTERY
-#define I2C_PORT_BATTERY            3
-#define I2C_PORT_TCPC0              0
+#define I2C_PORT_BC12 0
+#define I2C_PORT_TCPC0 0
+#define I2C_PORT_USB_MUX 0
+#define I2C_PORT_CHARGER 2
+#define I2C_PORT_SENSORS 2
+#define I2C_PORT_KB_DISCRETE 2
+#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
+#define I2C_PORT_BATTERY 3
+#define I2C_PORT_TCPC0 0
 
 #undef I2C_CONTROLLER_COUNT
 #undef I2C_PORT_COUNT
-#define I2C_CONTROLLER_COUNT        3
-#define I2C_PORT_COUNT              3
+#define I2C_CONTROLLER_COUNT 3
+#define I2C_PORT_COUNT 3
 
 /* IT8801 I2C address */
-#define KB_DISCRETE_I2C_ADDR_FLAGS  IT8801_I2C_ADDR1
+#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1
 
 /* Enable Accel over SPI */
-#define CONFIG_SPI_ACCEL_PORT    0  /* The first SPI controller port (SPI2) */
+#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */
 
 #define CONFIG_KEYBOARD_PROTOCOL_MKBP
 #define CONFIG_MKBP_EVENT
 #define CONFIG_MKBP_USE_GPIO
 /* Define the MKBP events which are allowed to wakeup AP in S3. */
-#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \
-		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK            \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
 
 #undef CONFIG_GMR_TABLET_MODE
 #undef GPIO_TABLET_MODE_L
diff --git a/board/munna/build.mk b/board/munna/build.mk
index 594bac4de9..aab7974af2 100644
--- a/board/munna/build.mk
+++ b/board/munna/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/munna/ec.tasklist b/board/munna/ec.tasklist
index 6b29595620..1e7e61108b 100644
--- a/board/munna/ec.tasklist
+++ b/board/munna/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/munna/gpio.inc b/board/munna/gpio.inc
index 50e5ee3a47..72de7677dc 100644
--- a/board/munna/gpio.inc
+++ b/board/munna/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/munna/led.c b/board/munna/led.c
index fa4f46b6ab..bd286b25a3 100644
--- a/board/munna/led.c
+++ b/board/munna/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -18,33 +18,38 @@ __override const int led_charge_lvl_1 = 5;
 __override const int led_charge_lvl_2 = 97;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED,    LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER,  LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
 
 __override const struct led_descriptor
-led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    1 * LED_ONE_SEC },
+						  { LED_OFF,
+						    3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 __override void led_set_color_battery(enum ec_led_colors color)
diff --git a/board/mushu/battery.c b/board/mushu/battery.c
index 7e48dfdc19..d523d918f7 100644
--- a/board/mushu/battery.c
+++ b/board/mushu/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/mushu/board.c b/board/mushu/board.c
index 8e46caa2ed..7197f7e136 100644
--- a/board/mushu/board.c
+++ b/board/mushu/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -44,8 +44,8 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* GPIO to enable/disable the USB Type-A port. */
 const int usb_port_enable[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT] = {
@@ -111,18 +111,19 @@ static void bc12_interrupt(enum gpio_signal signal)
 
 /******************************************************************************/
 /* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
+const struct spi_device_t spi_devices[] = {};
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
 /******************************************************************************/
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT]   = { .channel = 3, .flags = 0, .freq = 10000 },
-	[PWM_CH_FAN] = {.channel = 5, .flags = PWM_CONFIG_OPEN_DRAIN,
-			.freq = 25000},
-	[PWM_CH_FAN2] = {.channel = 6, .flags = PWM_CONFIG_OPEN_DRAIN,
-			.freq = 25000},
+	[PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 },
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
+	[PWM_CH_FAN2] = { .channel = 6,
+			  .flags = PWM_CONFIG_OPEN_DRAIN,
+			  .freq = 25000 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
@@ -148,16 +149,20 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_TCPC_0] = {
-		.usb_port = USB_PD_PORT_TCPC_0,
-		.driver = &anx7447_usb_mux_driver,
-		.hpd_update = &anx7447_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_0,
+			.driver = &anx7447_usb_mux_driver,
+			.hpd_update = &anx7447_tcpc_update_hpd_status,
+		},
 	},
 	[USB_PD_PORT_TCPC_1] = {
-		.usb_port = USB_PD_PORT_TCPC_1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 	}
 };
 
@@ -224,22 +229,18 @@ static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
 };
 
 /* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					      { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
 
 /*
  * TODO(b/124337208): P0 boards don't have this sensor mounted so the rotation
  * matrix can't be tested properly. This needs to be revisited after EVT to make
  * sure the rotation matrix for the lid sensor is correct.
  */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+					     { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
@@ -363,14 +364,14 @@ BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
 
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
 
 const struct fan_conf fan_conf_1 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_1,	/* Use MFT id to control fan */
+	.ch = MFT_CH_1, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
@@ -394,61 +395,48 @@ const struct fan_t fans[FAN_CH_COUNT] = {
 /******************************************************************************/
 /* MFT channels. These are logically separate from pwm_channels. */
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN},
-	[MFT_CH_1] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN2},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN },
+	[MFT_CH_1] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN2 },
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		"TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_2] = {
-		"TEMP_5V", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_1] = { "TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_2] = { "TEMP_5V", NPCX_ADC_CH1, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_CHARGER] = {
-		.name = "CHARGER",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_1
-	},
-	[TEMP_5V] = {
-		.name = "5V",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_2
-	},
-	[TEMP_GPU] = {
-		.name = "GPU",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_R19ME4070,
-		.idx = R19ME4070_LOCAL
-	},
-	[TEMP_F75303_LOCAL] = {
-		.name = "F75303_Local",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = f75303_get_val,
-		.idx = F75303_IDX_LOCAL
-	},
-	[TEMP_F75303_GPU] = {
-		.name = "F75303_GPU",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = f75303_get_val,
-		.idx = F75303_IDX_REMOTE1
-	},
-	[TEMP_F75303_GPU_POWER] = {
-		.name = "F75303_GPU_Power",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = f75303_get_val,
-		.idx = F75303_IDX_REMOTE2
-	},
+	[TEMP_CHARGER] = { .name = "CHARGER",
+			   .type = TEMP_SENSOR_TYPE_BOARD,
+			   .read = get_temp_3v3_30k9_47k_4050b,
+			   .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_5V] = { .name = "5V",
+		      .type = TEMP_SENSOR_TYPE_BOARD,
+		      .read = get_temp_3v3_30k9_47k_4050b,
+		      .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_GPU] = { .name = "GPU",
+		       .type = TEMP_SENSOR_TYPE_BOARD,
+		       .read = get_temp_R19ME4070,
+		       .idx = R19ME4070_LOCAL },
+	[TEMP_F75303_LOCAL] = { .name = "F75303_Local",
+				.type = TEMP_SENSOR_TYPE_BOARD,
+				.read = f75303_get_val,
+				.idx = F75303_IDX_LOCAL },
+	[TEMP_F75303_GPU] = { .name = "F75303_GPU",
+			      .type = TEMP_SENSOR_TYPE_BOARD,
+			      .read = f75303_get_val,
+			      .idx = F75303_IDX_REMOTE1 },
+	[TEMP_F75303_GPU_POWER] = { .name = "F75303_GPU_Power",
+				    .type = TEMP_SENSOR_TYPE_BOARD,
+				    .read = f75303_get_val,
+				    .idx = F75303_IDX_REMOTE2 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
-
 /* Hatch Temperature sensors */
 /*
  * TODO(b/124316213): These setting need to be reviewed and set appropriately
@@ -458,8 +446,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_A \
-	{ \
+#define THERMAL_A                \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = 0, \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
@@ -478,8 +466,8 @@ __maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_B \
-	{ \
+#define THERMAL_B                \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = 0, \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
@@ -495,7 +483,6 @@ __maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A;
 	}
 __maybe_unused static const struct ec_thermal_config thermal_b = THERMAL_B;
 
-
 struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
 
 static void setup_fans(void)
@@ -536,7 +523,6 @@ static void board_gpio_set_pp5000(void)
 	} else if (board_id >= 1) {
 		reset_gpio_flags(GPIO_EN_PP5000_A_V1, GPIO_OUT_LOW);
 	}
-
 }
 
 static void board_init(void)
diff --git a/board/mushu/board.h b/board/mushu/board.h
index 5f80b4a2e6..02443bbfa3 100644
--- a/board/mushu/board.h
+++ b/board/mushu/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,10 +13,10 @@
 
 /* Reduce flash usage */
 #define CONFIG_USB_PD_DEBUG_LEVEL 2
-#undef  CONFIG_CMD_ACCELSPOOF
-#undef  CONFIG_CMD_CHARGER_DUMP
-#undef  CONFIG_CMD_PPC_DUMP
-#undef  CONFIG_CONSOLE_CMDHELP
+#undef CONFIG_CMD_ACCELSPOOF
+#undef CONFIG_CMD_CHARGER_DUMP
+#undef CONFIG_CMD_PPC_DUMP
+#undef CONFIG_CONSOLE_CMDHELP
 
 #define CONFIG_POWER_BUTTON
 #define CONFIG_KEYBOARD_PROTOCOL_8042
@@ -26,14 +26,12 @@
 #define CONFIG_HOST_INTERFACE_ESPI
 #undef CONFIG_CMD_MFALLOW
 
-
 #undef CONFIG_UART_TX_BUF_SIZE
 #define CONFIG_UART_TX_BUF_SIZE 4096
 
 /* Keyboard features */
 #define CONFIG_PWM_KBLIGHT
 
-
 /* Sensors */
 /* BMI160 Base accel/gyro */
 #define CONFIG_ACCELGYRO_BMI160
@@ -53,7 +51,7 @@
 #define CONFIG_ALS_TCS3400
 #define CONFIG_ALS_TCS3400_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS)
-#define I2C_PORT_ALS      I2C_PORT_SENSOR
+#define I2C_PORT_ALS I2C_PORT_SENSOR
 #define CONFIG_TEMP_SENSOR
 /* AMD SMBUS Temp sensors */
 #define CONFIG_TEMP_SENSOR_AMD_R19ME4070
@@ -64,7 +62,7 @@
 #define I2C_PORT_THERMAL I2C_PORT_SENSOR
 
 /* GPU features */
-#define I2C_PORT_GPU                    NPCX_I2C_PORT4_1
+#define I2C_PORT_GPU NPCX_I2C_PORT4_1
 
 /* USB Type C and USB PD defines */
 #undef CONFIG_USB_PD_TCPMV1
@@ -139,16 +137,16 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_AC_PRESENT		GPIO_ACOK_OD
-#define GPIO_PG_EC_RSMRST_ODL	GPIO_PG_EC_RSMRST_L
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_TEMP_SENSOR_POWER	GPIO_EN_A_RAILS
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L
+#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
 
 #ifndef __ASSEMBLER__
 
@@ -160,8 +158,8 @@
 extern enum gpio_signal gpio_en_pp5000_a;
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_1,	/* ADC0 */
-	ADC_TEMP_SENSOR_2,	/* ADC1 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
 	ADC_CH_COUNT
 };
 
@@ -174,12 +172,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_FAN,
-	PWM_CH_FAN2,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_FAN, PWM_CH_FAN2, PWM_CH_COUNT };
 
 enum fan_channel {
 	FAN_CH_0 = 0,
@@ -212,15 +205,14 @@ enum battery_type {
 	BATTERY_TYPE_COUNT,
 };
 
-
 #undef PD_OPERATING_POWER_MW
-#define PD_OPERATING_POWER_MW	15000
+#define PD_OPERATING_POWER_MW 15000
 #undef PD_MAX_POWER_MW
-#define PD_MAX_POWER_MW		100000
+#define PD_MAX_POWER_MW 100000
 #undef PD_MAX_CURRENT_MA
-#define PD_MAX_CURRENT_MA	5000
+#define PD_MAX_CURRENT_MA 5000
 #undef PD_MAX_VOLTAGE_MV
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_MAX_VOLTAGE_MV 20000
 
 #endif /* !__ASSEMBLER__ */
 
diff --git a/board/mushu/build.mk b/board/mushu/build.mk
index 2d6118ea70..4e42a0616e 100644
--- a/board/mushu/build.mk
+++ b/board/mushu/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/mushu/ec.tasklist b/board/mushu/ec.tasklist
index 4a1024a091..829be2b7c8 100644
--- a/board/mushu/ec.tasklist
+++ b/board/mushu/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/mushu/gpio.inc b/board/mushu/gpio.inc
index cc8c7a0154..e1711a87e1 100644
--- a/board/mushu/gpio.inc
+++ b/board/mushu/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,10 +16,10 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(PG_EC_RSMRST_L,       PIN(E, 2), GPIO_INT_BOTH, intel_x86_rsmrst_signal_interrupt)
diff --git a/board/mushu/led.c b/board/mushu/led.c
index a5d81fabd4..6d20ecdedf 100644
--- a/board/mushu/led.c
+++ b/board/mushu/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,22 +19,26 @@ __override const int led_charge_lvl_1 = 5;
 __override const int led_charge_lvl_2 = 95;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
diff --git a/board/mushu/thermal.c b/board/mushu/thermal.c
index b61f36ab8a..da8f29de08 100644
--- a/board/mushu/thermal.c
+++ b/board/mushu/thermal.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,8 +23,7 @@ void fan_set_percent(int fan, int pct)
 	new_rpm = fan_percent_to_rpm(fan, pct);
 	actual_rpm = fan_get_rpm_actual(FAN_CH(fan));
 
-	if (new_rpm &&
-	    actual_rpm < min_rpm &&
+	if (new_rpm && actual_rpm < min_rpm &&
 	    new_rpm < fans[fan].rpm->rpm_start)
 		new_rpm = fans[fan].rpm->rpm_start;
 
diff --git a/board/nami/battery.c b/board/nami/battery.c
index 149272c8c1..18f03fc9de 100644
--- a/board/nami/battery.c
+++ b/board/nami/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -16,8 +16,8 @@
 #include "hooks.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 /* Default, Nami, Vayne */
 static const struct battery_info info_0 = {
@@ -243,8 +243,9 @@ static int battery_init(void)
 	if (batt_status & STATUS_INITIALIZED)
 		return 1;
 
-	return battery_status(&batt_status) ? 0 :
-		!!(batt_status & STATUS_INITIALIZED);
+	return battery_status(&batt_status) ?
+		       0 :
+		       !!(batt_status & STATUS_INITIALIZED);
 }
 
 enum battery_disconnect_grace_period {
@@ -278,13 +279,13 @@ static int battery_check_disconnect_ti_bq40z50(void)
 	uint8_t data[6];
 
 	/* Check if battery charging + discharging is disabled. */
-	rv = sb_read_mfgacc(PARAM_OPERATION_STATUS,
-			    SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data));
+	rv = sb_read_mfgacc(PARAM_OPERATION_STATUS, SB_ALT_MANUFACTURER_ACCESS,
+			    data, sizeof(data));
 	if (rv)
 		return BATTERY_DISCONNECT_ERROR;
 
-	if ((data[3] & (BATTERY_DISCHARGING_DISABLED |
-			BATTERY_CHARGING_DISABLED)) ==
+	if ((data[3] &
+	     (BATTERY_DISCHARGING_DISABLED | BATTERY_CHARGING_DISABLED)) ==
 	    (BATTERY_DISCHARGING_DISABLED | BATTERY_CHARGING_DISABLED)) {
 		if (oem != PROJECT_SONA)
 			return BATTERY_DISCONNECTED;
@@ -298,10 +299,10 @@ static int battery_check_disconnect_ti_bq40z50(void)
 		 * stop charging and avoid damaging the battery.
 		 */
 		if (disconnect_grace_period ==
-				BATTERY_DISCONNECT_GRACE_PERIOD_OVER)
+		    BATTERY_DISCONNECT_GRACE_PERIOD_OVER)
 			return BATTERY_DISCONNECTED;
 		if (disconnect_grace_period ==
-				BATTERY_DISCONNECT_GRACE_PERIOD_OFF)
+		    BATTERY_DISCONNECT_GRACE_PERIOD_OFF)
 			hook_call_deferred(&battery_disconnect_timer_data,
 					   5 * SECOND);
 		ccprintf("Battery disconnect grace period\n");
diff --git a/board/nami/board.c b/board/nami/board.c
index 20882cff13..02fb27a283 100644
--- a/board/nami/board.c
+++ b/board/nami/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -65,11 +65,11 @@
 #include "fan.h"
 #include "fan_chip.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define USB_PD_PORT_PS8751	0
-#define USB_PD_PORT_ANX7447	1
+#define USB_PD_PORT_PS8751 0
+#define USB_PD_PORT_ANX7447 1
 
 uint16_t board_version;
 uint8_t oem = PROJECT_NAMI;
@@ -82,17 +82,16 @@ uint8_t model;
  * that we don't have pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-	{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-	{0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3},
-	{-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0},
-	{1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4},
-	{2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0},
-	{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1},
-	{-1, -1},
+	{ -1, -1 }, { 0, 5 },	{ 1, 1 },   { 1, 0 },	{ 0, 6 },   { 0, 7 },
+	{ -1, -1 }, { -1, -1 }, { 1, 4 },   { 1, 3 },	{ -1, -1 }, { 1, 6 },
+	{ 1, 7 },   { 3, 1 },	{ 2, 0 },   { 1, 5 },	{ 2, 6 },   { 2, 7 },
+	{ 2, 1 },   { 2, 4 },	{ 2, 5 },   { 1, 2 },	{ 2, 3 },   { 2, 2 },
+	{ 3, 0 },   { -1, -1 }, { -1, -1 }, { -1, -1 }, { -1, -1 }, { -1, -1 },
+	{ -1, -1 },
 };
 
 const int keyboard_factory_scan_pins_used =
-		ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
@@ -151,13 +150,14 @@ void usb1_evt(enum gpio_signal signal)
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* Vbus sensing (10x voltage divider). PPVAR_BOOSTIN_SENSE */
-	[ADC_VBUS] = {"VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
+	[ADC_VBUS] = { "VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT * 10,
+		       ADC_READ_MAX + 1, 0 },
 	/*
 	 * Adapter current output or battery charging/discharging current (uV)
 	 * 18x amplification on charger side.
 	 */
-	[ADC_AMON_BMON] = {"AMON_BMON", NPCX_ADC_CH1, ADC_MAX_VOLT*1000/18,
-			   ADC_READ_MAX+1, 0},
+	[ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH1, ADC_MAX_VOLT * 1000 / 18,
+			    ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
@@ -166,7 +166,7 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = -1,
 };
@@ -212,54 +212,42 @@ struct fan_t fans[FAN_CH_COUNT] = {
 /******************************************************************************/
 /* MFT channels. These are logically separate from pwm_channels. */
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN },
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 /* I2C port map */
-const struct i2c_port_t i2c_ports[]  = {
-	{
-		.name = "tcpc0",
-		.port = NPCX_I2C_PORT0_0,
-		.kbps = 400,
-		.scl  = GPIO_I2C0_0_SCL,
-		.sda  = GPIO_I2C0_0_SDA
-	},
-	{
-		.name = "tcpc1",
-		.port = NPCX_I2C_PORT0_1,
-		.kbps = 400,
-		.scl  = GPIO_I2C0_1_SCL,
-		.sda  = GPIO_I2C0_1_SDA
-	},
-	{
-		.name = "battery",
-		.port = NPCX_I2C_PORT1,
-		.kbps = 100,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	},
-	{
-		.name = "charger",
-		.port = NPCX_I2C_PORT2,
-		.kbps = 100,
-		.scl  = GPIO_I2C2_SCL,
-		.sda  = GPIO_I2C2_SDA
-	},
-	{
-		.name = "pmic",
-		.port = NPCX_I2C_PORT2,
-		.kbps = 400,
-		.scl  = GPIO_I2C2_SCL,
-		.sda  = GPIO_I2C2_SDA
-	},
-	{
-		.name = "accelgyro",
-		.port = NPCX_I2C_PORT3,
-		.kbps = 400,
-		.scl  = GPIO_I2C3_SCL,
-		.sda  = GPIO_I2C3_SDA
-	},
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "tcpc0",
+	  .port = NPCX_I2C_PORT0_0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_0_SCL,
+	  .sda = GPIO_I2C0_0_SDA },
+	{ .name = "tcpc1",
+	  .port = NPCX_I2C_PORT0_1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_1_SCL,
+	  .sda = GPIO_I2C0_1_SDA },
+	{ .name = "battery",
+	  .port = NPCX_I2C_PORT1,
+	  .kbps = 100,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "charger",
+	  .port = NPCX_I2C_PORT2,
+	  .kbps = 100,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "pmic",
+	  .port = NPCX_I2C_PORT2,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "accelgyro",
+	  .port = NPCX_I2C_PORT3,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -294,16 +282,22 @@ static int ps8751_tune_mux(const struct usb_mux *me)
 	return EC_SUCCESS;
 }
 
-struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+struct usb_mux usb_mux_ps8751 = {
+	.usb_port = USB_PD_PORT_PS8751,
+	.driver = &tcpci_tcpm_usb_mux_driver,
+	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+};
+
+struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_PS8751] = {
-		.usb_port = USB_PD_PORT_PS8751,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux = &usb_mux_ps8751,
 	},
 	[USB_PD_PORT_ANX7447] = {
-		.usb_port = USB_PD_PORT_ANX7447,
-		.driver = &anx7447_usb_mux_driver,
-		.hpd_update = &anx7447_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_ANX7447,
+			.driver = &anx7447_usb_mux_driver,
+			.hpd_update = &anx7447_tcpc_update_hpd_status,
+		},
 	}
 };
 
@@ -333,7 +327,6 @@ void board_reset_pd_mcu(void)
 	if (oem == PROJECT_AKALI && board_version < 0x0200) {
 		if (anx7447_flash_erase(USB_PD_PORT_ANX7447))
 			CPRINTS("Failed to erase OCM flash");
-
 	}
 
 	/* Assert reset */
@@ -358,7 +351,7 @@ void board_tcpc_init(void)
 	gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL);
 
 	if (oem == PROJECT_SONA && model != MODEL_SYNDRA)
-		usb_muxes[USB_PD_PORT_PS8751].board_init = ps8751_tune_mux;
+		usb_mux_ps8751.board_init = ps8751_tune_mux;
 
 	/*
 	 * Initialize HPD to low; after sysjump SOC needs to see
@@ -366,7 +359,7 @@ void board_tcpc_init(void)
 	 */
 	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
 		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
 DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 2);
 
@@ -391,12 +384,12 @@ uint16_t tcpc_get_alert_status(void)
  * F75303_Remote1 is near CPU, and F75303_Remote2 is near 5V power IC.
  */
 const struct temp_sensor_t temp_sensors[TEMP_SENSOR_COUNT] = {
-	{"F75303_Local", TEMP_SENSOR_TYPE_BOARD, f75303_get_val,
-		F75303_IDX_LOCAL},
-	{"F75303_Remote1", TEMP_SENSOR_TYPE_CPU, f75303_get_val,
-		F75303_IDX_REMOTE1},
-	{"F75303_Remote2", TEMP_SENSOR_TYPE_BOARD, f75303_get_val,
-		F75303_IDX_REMOTE2},
+	{ "F75303_Local", TEMP_SENSOR_TYPE_BOARD, f75303_get_val,
+	  F75303_IDX_LOCAL },
+	{ "F75303_Remote1", TEMP_SENSOR_TYPE_CPU, f75303_get_val,
+	  F75303_IDX_REMOTE1 },
+	{ "F75303_Remote2", TEMP_SENSOR_TYPE_BOARD, f75303_get_val,
+	  F75303_IDX_REMOTE2 },
 };
 
 struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
@@ -405,8 +398,8 @@ struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT];
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_A \
-	{ \
+#define THERMAL_A                \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = 0, \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
@@ -426,8 +419,8 @@ __maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_B1 \
-	{ \
+#define THERMAL_B1               \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = 0, \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(82), \
@@ -447,8 +440,8 @@ __maybe_unused static const struct ec_thermal_config thermal_b1 = THERMAL_B1;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_B2 \
-	{ \
+#define THERMAL_B2               \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = 0, \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(84), \
@@ -468,8 +461,8 @@ __maybe_unused static const struct ec_thermal_config thermal_b2 = THERMAL_B2;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_C1 \
-	{ \
+#define THERMAL_C1               \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = 0, \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(66), \
@@ -489,8 +482,8 @@ __maybe_unused static const struct ec_thermal_config thermal_c1 = THERMAL_C1;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_C2 \
-	{ \
+#define THERMAL_C2               \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = 0, \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(74), \
@@ -510,8 +503,8 @@ __maybe_unused static const struct ec_thermal_config thermal_c2 = THERMAL_C2;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_D0 \
-	{ \
+#define THERMAL_D0               \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = C_TO_K(79), \
 			[EC_TEMP_THRESH_HIGH] = 0, \
@@ -531,8 +524,8 @@ __maybe_unused static const struct ec_thermal_config thermal_d0 = THERMAL_D0;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_D1 \
-	{ \
+#define THERMAL_D1               \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = C_TO_K(59), \
 			[EC_TEMP_THRESH_HIGH] = 0, \
@@ -552,8 +545,8 @@ __maybe_unused static const struct ec_thermal_config thermal_d1 = THERMAL_D1;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_D2 \
-	{ \
+#define THERMAL_D2               \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = C_TO_K(59), \
 			[EC_TEMP_THRESH_HIGH] = 0, \
@@ -570,11 +563,9 @@ __maybe_unused static const struct ec_thermal_config thermal_d1 = THERMAL_D1;
 __maybe_unused static const struct ec_thermal_config thermal_d2 = THERMAL_D2;
 
 #define I2C_PMIC_READ(reg, data) \
-		i2c_read8(I2C_PORT_PMIC, TPS650X30_I2C_ADDR1_FLAGS,\
-			  (reg), (data))
+	i2c_read8(I2C_PORT_PMIC, TPS650X30_I2C_ADDR1_FLAGS, (reg), (data))
 #define I2C_PMIC_WRITE(reg, data) \
-		i2c_write8(I2C_PORT_PMIC, TPS650X30_I2C_ADDR1_FLAGS,\
-			   (reg), (data))
+	i2c_write8(I2C_PORT_PMIC, TPS650X30_I2C_ADDR1_FLAGS, (reg), (data))
 
 static void board_pmic_init(void)
 {
@@ -726,8 +717,8 @@ int board_set_active_charge_port(int charge_port)
 			    charge_port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	/* check if we are sourcing VBUS on the port */
 	/* dnojiri: revisit */
-	int is_source = gpio_get_level(charge_port == 0 ?
-			GPIO_USB_C0_5V_EN : GPIO_USB_C1_5V_EN);
+	int is_source = gpio_get_level(charge_port == 0 ? GPIO_USB_C0_5V_EN :
+							  GPIO_USB_C1_5V_EN);
 
 	if (is_real_port && is_source) {
 		CPRINTF("No charging on source port p%d is ", charge_port);
@@ -745,17 +736,19 @@ int board_set_active_charge_port(int charge_port)
 		/* dnojiri: revisit. there is always this assumption that
 		 * battery is present. If not, this may cause brownout. */
 		gpio_set_level(charge_port ? GPIO_USB_C0_CHARGE_L :
-					     GPIO_USB_C1_CHARGE_L, 1);
+					     GPIO_USB_C1_CHARGE_L,
+			       1);
 		/* Enable charging port */
 		gpio_set_level(charge_port ? GPIO_USB_C1_CHARGE_L :
-					     GPIO_USB_C0_CHARGE_L, 0);
+					     GPIO_USB_C0_CHARGE_L,
+			       0);
 	}
 
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	/*
 	 * Limit the input current to 96% negotiated limit,
@@ -764,12 +757,11 @@ void board_set_charge_limit(int port, int supplier, int charge_ma,
 	int factor = 96;
 
 	if (oem == PROJECT_AKALI &&
-		(model == MODEL_EKKO || model == MODEL_BARD))
+	    (model == MODEL_EKKO || model == MODEL_BARD))
 		factor = 95;
 	charge_ma = charge_ma * factor / 100;
 	charge_set_input_current_limit(
-			MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT),
-			charge_mv);
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 void board_hibernate(void)
@@ -782,9 +774,9 @@ void board_hibernate(void)
 }
 
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_LED1]   = { 3, PWM_CONFIG_DSLEEP, 1200 },
+	[PWM_CH_LED1] = { 3, PWM_CONFIG_DSLEEP, 1200 },
 	[PWM_CH_LED2] = { 5, PWM_CONFIG_DSLEEP, 1200 },
-	[PWM_CH_FAN] = {4, PWM_CONFIG_OPEN_DRAIN, 25000},
+	[PWM_CH_FAN] = { 4, PWM_CONFIG_OPEN_DRAIN, 25000 },
 	/*
 	 * 1.2kHz is a multiple of both 50 and 60. So a video recorder
 	 * (generally designed to ignore either 50 or 60 Hz flicker) will not
@@ -806,23 +798,17 @@ static struct kionix_accel_data g_kx022_data;
 static struct accelgyro_saved_data_t g_bma255_data;
 
 /* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+				       { FLOAT_TO_FP(1), 0, 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
 
-const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+				      { 0, FLOAT_TO_FP(-1), 0 },
+				      { 0, 0, FLOAT_TO_FP(-1) } };
 
-const mat33_fp_t rotation_x180_z90 = {
-	{ 0, FLOAT_TO_FP(-1), 0 },
-	{ FLOAT_TO_FP(-1), 0, 0 },
-	{ 0, 0, FLOAT_TO_FP(-1) }
-};
+const mat33_fp_t rotation_x180_z90 = { { 0, FLOAT_TO_FP(-1), 0 },
+				       { FLOAT_TO_FP(-1), 0, 0 },
+				       { 0, 0, FLOAT_TO_FP(-1) } };
 
 const struct motion_sensor_t lid_accel_1 = {
 	.name = "Lid Accel",
@@ -1096,7 +1082,7 @@ static void board_init(void)
 		       ISL9238_REG_CONTROL3, &reg) == EC_SUCCESS) {
 		reg |= ISL9238_C3_BB_SWITCHING_PERIOD;
 		if (i2c_write16(I2C_PORT_CHARGER, I2C_ADDR_CHARGER_FLAGS,
-			    ISL9238_REG_CONTROL3, reg))
+				ISL9238_REG_CONTROL3, reg))
 			CPRINTF("Failed to set isl9238\n");
 	}
 
@@ -1188,14 +1174,13 @@ void board_kblight_init(void)
 	}
 }
 
-enum critical_shutdown board_critical_shutdown_check(
-		struct charge_state_data *curr)
+enum critical_shutdown
+board_critical_shutdown_check(struct charge_state_data *curr)
 {
 	if (oem == PROJECT_VAYNE)
 		return CRITICAL_SHUTDOWN_CUTOFF;
 	else
 		return CRITICAL_SHUTDOWN_HIBERNATE;
-
 }
 
 uint8_t board_set_battery_level_shutdown(void)
diff --git a/board/nami/board.h b/board/nami/board.h
index dde32b65f8..879fb443be 100644
--- a/board/nami/board.h
+++ b/board/nami/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,7 +12,7 @@
  * By default, enable all console messages except ACPI and host event because
  * the sensor stack is generating a lot of activity.
  */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
 
 /* EC */
 #define CONFIG_ADC
@@ -74,8 +74,8 @@
 #define CONFIG_CHIPSET_HAS_PRE_INIT_CALLBACK
 #define CONFIG_CHIPSET_RESET_HOOK
 #define CONFIG_HOST_INTERFACE_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 #define CONFIG_HOSTCMD_FLASH_SPI_INFO
 #define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD
 
@@ -87,8 +87,8 @@
 #define CONFIG_BATTERY_SMART
 #define CONFIG_PWR_STATE_DISCHARGE_FULL
 #define CONFIG_BATTERY_REQUESTS_NIL_WHEN_DEAD
-#undef  CONFIG_BATT_HOST_FULL_FACTOR
-#define CONFIG_BATT_HOST_FULL_FACTOR	100
+#undef CONFIG_BATT_HOST_FULL_FACTOR
+#define CONFIG_BATT_HOST_FULL_FACTOR 100
 
 /* Charger */
 #define CONFIG_CHARGE_MANAGER
@@ -98,8 +98,8 @@
 #define CONFIG_CHARGER_ISL9238
 #define CONFIG_CHARGER_DISCHARGE_ON_AC
 #define CONFIG_CHARGER_INPUT_CURRENT 512
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON		27000
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT	15000
+#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 27000
+#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT 15000
 /* AP's thresholds. */
 #define CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT 3
 #define CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW 27000
@@ -110,11 +110,11 @@
 #define CONFIG_CMD_CHARGER_ADC_AMON_BMON
 #define CONFIG_HOSTCMD_PD_CONTROL
 #define CONFIG_EXTPOWER_GPIO
-#undef  CONFIG_EXTPOWER_DEBOUNCE_MS
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
 #define CONFIG_EXTPOWER_DEBOUNCE_MS 1000
 #define CONFIG_POWER_BUTTON
 #define CONFIG_POWER_BUTTON_X86
-#undef  CONFIG_POWER_BUTTON_INIT_TIMEOUT
+#undef CONFIG_POWER_BUTTON_INIT_TIMEOUT
 #define CONFIG_POWER_BUTTON_INIT_TIMEOUT 6
 #define CONFIG_POWER_COMMON
 #define CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD 30
@@ -180,34 +180,33 @@
 #define CONFIG_USBC_VCONN_SWAP
 #define CONFIG_USB_MUX_RUNTIME_CONFIG
 
-
 /* BC 1.2 charger */
 #define CONFIG_BC12_DETECT_PI3USB9281
 #define CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT 2
 
 /* Optional feature to configure npcx chip */
-#define NPCX_UART_MODULE2	1 /* 1:GPIO64/65 as UART */
-#define NPCX_JTAG_MODULE2	0 /* 0:GPIO21/17/16/20 as JTAG */
-#define NPCX_TACH_SEL2		1 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
+#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART */
+#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 as JTAG */
+#define NPCX_TACH_SEL2 1 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
 
 /* I2C ports */
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT0_0
-#define I2C_PORT_TCPC1		NPCX_I2C_PORT0_1
-#define I2C_PORT_USB_CHARGER_0	NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_CHARGER_1	NPCX_I2C_PORT0_1
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT0_0
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT1
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT1
-#define I2C_PORT_PMIC		NPCX_I2C_PORT2
-#define I2C_PORT_KBLIGHT	NPCX_I2C_PORT2
-#define I2C_PORT_GYRO		NPCX_I2C_PORT3
-#define I2C_PORT_ACCEL		NPCX_I2C_PORT3
-#define I2C_PORT_THERMAL	NPCX_I2C_PORT3
-#define I2C_PORT_ALS		NPCX_I2C_PORT3
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0
+#define I2C_PORT_TCPC1 NPCX_I2C_PORT0_1
+#define I2C_PORT_USB_CHARGER_0 NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_CHARGER_1 NPCX_I2C_PORT0_1
+#define I2C_PORT_EEPROM NPCX_I2C_PORT0_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT1
+#define I2C_PORT_CHARGER NPCX_I2C_PORT1
+#define I2C_PORT_PMIC NPCX_I2C_PORT2
+#define I2C_PORT_KBLIGHT NPCX_I2C_PORT2
+#define I2C_PORT_GYRO NPCX_I2C_PORT3
+#define I2C_PORT_ACCEL NPCX_I2C_PORT3
+#define I2C_PORT_THERMAL NPCX_I2C_PORT3
+#define I2C_PORT_ALS NPCX_I2C_PORT3
 
 /* I2C addresses */
-#define I2C_ADDR_MP2949_FLAGS	0x20
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_ADDR_MP2949_FLAGS 0x20
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 
 #ifndef __ASSEMBLER__
 
@@ -284,26 +283,26 @@ enum model_id {
 	MODEL_BARD = 2,
 };
 
-#define SKU_ID_MASK_KBLIGHT	BIT(0)
-#define SKU_ID_MASK_CONVERTIBLE	BIT(9)
-#define SKU_ID_MASK_KEYPAD	BIT(15)
-#define SKU_ID_MASK_UK2		BIT(18)
+#define SKU_ID_MASK_KBLIGHT BIT(0)
+#define SKU_ID_MASK_CONVERTIBLE BIT(9)
+#define SKU_ID_MASK_KEYPAD BIT(15)
+#define SKU_ID_MASK_UK2 BIT(18)
 
 /* TODO(crosbug.com/p/61098): Verify the numbers below. */
 /*
  * delay to turn on the power supply max is ~16ms.
  * delay to turn off the power supply max is about ~180ms.
  */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	250000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* delay to turn on/off vconn */
 
 /* Define typical operating power and max power */
-#define PD_OPERATING_POWER_MW		15000
-#define PD_MAX_POWER_MW			70000
-#define PD_MAX_CURRENT_MA		3500
-#define PD_MAX_VOLTAGE_MV		20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 70000
+#define PD_MAX_CURRENT_MA 3500
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Board specific handlers */
 void board_reset_pd_mcu(void);
@@ -319,7 +318,7 @@ extern uint32_t sku;
 extern uint8_t model;
 
 /* SKU_ID[24:31] are dedicated to OEM customization */
-#define CBI_SKU_CUSTOM_FIELD(val)	((val) >> 24)
+#define CBI_SKU_CUSTOM_FIELD(val) ((val) >> 24)
 
 void ccd_mode_isr(enum gpio_signal signal);
 
diff --git a/board/nami/build.mk b/board/nami/build.mk
index f4bf21113d..8f3a138f56 100644
--- a/board/nami/build.mk
+++ b/board/nami/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/nami/ec.tasklist b/board/nami/ec.tasklist
index 93fcda9f91..99d0f15b70 100644
--- a/board/nami/ec.tasklist
+++ b/board/nami/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nami/gpio.inc b/board/nami/gpio.inc
index f4119c96a6..124af79f49 100644
--- a/board/nami/gpio.inc
+++ b/board/nami/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nami/led.c b/board/nami/led.c
index 17af4d5f82..ce9cefed7f 100644
--- a/board/nami/led.c
+++ b/board/nami/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -38,8 +38,8 @@
 #include "timer.h"
 #include "util.h"
 
-const enum ec_led_id supported_led_ids[] = {
-		EC_LED_ID_BATTERY_LED, EC_LED_ID_POWER_LED};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 enum led_color {
@@ -79,19 +79,19 @@ struct led_pattern {
 	uint8_t pulse;
 };
 
-#define PULSE_NO		0
-#define PULSE(interval)		(BIT(7) | (interval))
-#define BLINK(interval) 	(interval)
-#define ALTERNATE(interval)	(BIT(6) | (interval))
-#define IS_PULSING(pulse)	((pulse) & 0x80)
-#define IS_ALTERNATE(pulse)	((pulse) & 0x40)
-#define PULSE_INTERVAL(pulse)	(((pulse) & 0x3f) * 100 * MSEC)
+#define PULSE_NO 0
+#define PULSE(interval) (BIT(7) | (interval))
+#define BLINK(interval) (interval)
+#define ALTERNATE(interval) (BIT(6) | (interval))
+#define IS_PULSING(pulse) ((pulse)&0x80)
+#define IS_ALTERNATE(pulse) ((pulse)&0x40)
+#define PULSE_INTERVAL(pulse) (((pulse)&0x3f) * 100 * MSEC)
 
 /* 40 msec for nice and smooth transition. */
-#define LED_PULSE_TICK_US	(40 * MSEC)
+#define LED_PULSE_TICK_US (40 * MSEC)
 
 typedef struct led_pattern led_patterns[LED_CHARGE_STATE_COUNT]
-					[LED_POWER_STATE_COUNT];
+				       [LED_POWER_STATE_COUNT];
 
 /*
  * Nami/Vayne - One dual color LED:
@@ -105,11 +105,17 @@ typedef struct led_pattern led_patterns[LED_CHARGE_STATE_COUNT]
  */
 const static led_patterns battery_pattern_0 = {
 	/* discharging: s0, s3, s5 */
-	{{LED_WHITE, PULSE_NO}, {LED_WHITE, PULSE(10)}, {LED_OFF,  PULSE_NO}},
+	{ { LED_WHITE, PULSE_NO },
+	  { LED_WHITE, PULSE(10) },
+	  { LED_OFF, PULSE_NO } },
 	/* charging: s0, s3, s5 */
-	{{LED_AMBER, PULSE_NO}, {LED_AMBER, PULSE_NO}, {LED_AMBER, PULSE_NO}},
+	{ { LED_AMBER, PULSE_NO },
+	  { LED_AMBER, PULSE_NO },
+	  { LED_AMBER, PULSE_NO } },
 	/* full: s0, s3, s5 */
-	{{LED_WHITE, PULSE_NO}, {LED_WHITE, PULSE_NO}, {LED_WHITE, PULSE_NO}},
+	{ { LED_WHITE, PULSE_NO },
+	  { LED_WHITE, PULSE_NO },
+	  { LED_WHITE, PULSE_NO } },
 };
 
 /*
@@ -117,11 +123,15 @@ const static led_patterns battery_pattern_0 = {
  */
 const static led_patterns battery_pattern_1 = {
 	/* discharging: s0, s3, s5 */
-	{{LED_OFF,   PULSE_NO}, {LED_OFF,   PULSE_NO}, {LED_OFF,   PULSE_NO}},
+	{ { LED_OFF, PULSE_NO }, { LED_OFF, PULSE_NO }, { LED_OFF, PULSE_NO } },
 	/* charging: s0, s3, s5 */
-	{{LED_AMBER, PULSE_NO}, {LED_AMBER, PULSE_NO}, {LED_AMBER, PULSE_NO}},
+	{ { LED_AMBER, PULSE_NO },
+	  { LED_AMBER, PULSE_NO },
+	  { LED_AMBER, PULSE_NO } },
 	/* full: s0, s3, s5 */
-	{{LED_WHITE, PULSE_NO}, {LED_WHITE, PULSE_NO}, {LED_WHITE, PULSE_NO}},
+	{ { LED_WHITE, PULSE_NO },
+	  { LED_WHITE, PULSE_NO },
+	  { LED_WHITE, PULSE_NO } },
 };
 
 /*
@@ -132,11 +142,15 @@ const static led_patterns battery_pattern_1 = {
  */
 const static led_patterns battery_pattern_2 = {
 	/* discharging: s0, s3, s5 */
-	{{LED_OFF,   PULSE_NO}, {LED_OFF,   PULSE_NO}, {LED_OFF,   PULSE_NO}},
+	{ { LED_OFF, PULSE_NO }, { LED_OFF, PULSE_NO }, { LED_OFF, PULSE_NO } },
 	/* charging: s0, s3, s5 */
-	{{LED_AMBER, PULSE_NO}, {LED_AMBER, PULSE_NO}, {LED_AMBER, PULSE_NO}},
+	{ { LED_AMBER, PULSE_NO },
+	  { LED_AMBER, PULSE_NO },
+	  { LED_AMBER, PULSE_NO } },
 	/* full: s0, s3, s5 */
-	{{LED_WHITE, PULSE_NO}, {LED_WHITE, PULSE_NO}, {LED_WHITE, PULSE_NO}},
+	{ { LED_WHITE, PULSE_NO },
+	  { LED_WHITE, PULSE_NO },
+	  { LED_WHITE, PULSE_NO } },
 };
 
 /*
@@ -144,11 +158,17 @@ const static led_patterns battery_pattern_2 = {
  */
 const static led_patterns power_pattern_1 = {
 	/* discharging: s0, s3, s5 */
-	{{LED_WHITE, PULSE_NO}, {LED_WHITE, BLINK(10)}, {LED_OFF, PULSE_NO}},
+	{ { LED_WHITE, PULSE_NO },
+	  { LED_WHITE, BLINK(10) },
+	  { LED_OFF, PULSE_NO } },
 	/* charging: s0, s3, s5 */
-	{{LED_WHITE, PULSE_NO}, {LED_WHITE, BLINK(10)}, {LED_OFF, PULSE_NO}},
+	{ { LED_WHITE, PULSE_NO },
+	  { LED_WHITE, BLINK(10) },
+	  { LED_OFF, PULSE_NO } },
 	/* full: s0, s3, s5 */
-	{{LED_WHITE, PULSE_NO}, {LED_WHITE, BLINK(10)}, {LED_OFF, PULSE_NO}},
+	{ { LED_WHITE, PULSE_NO },
+	  { LED_WHITE, BLINK(10) },
+	  { LED_OFF, PULSE_NO } },
 };
 
 /*
@@ -159,11 +179,17 @@ const static led_patterns power_pattern_1 = {
  */
 const static led_patterns power_pattern_2 = {
 	/* discharging: s0, s3, s5 */
-	{{LED_WHITE, 0}, {LED_WHITE, ALTERNATE(BLINK(10))}, {LED_OFF, 0}},
+	{ { LED_WHITE, 0 },
+	  { LED_WHITE, ALTERNATE(BLINK(10)) },
+	  { LED_OFF, 0 } },
 	/* charging: s0, s3, s5 */
-	{{LED_WHITE, 0}, {LED_WHITE, ALTERNATE(BLINK(10))}, {LED_OFF, 0}},
+	{ { LED_WHITE, 0 },
+	  { LED_WHITE, ALTERNATE(BLINK(10)) },
+	  { LED_OFF, 0 } },
 	/* full: s0, s3, s5 */
-	{{LED_WHITE, 0}, {LED_WHITE, ALTERNATE(BLINK(10))}, {LED_OFF, 0}},
+	{ { LED_WHITE, 0 },
+	  { LED_WHITE, ALTERNATE(BLINK(10)) },
+	  { LED_OFF, 0 } },
 };
 
 /*
@@ -178,30 +204,42 @@ const static led_patterns power_pattern_2 = {
  */
 const static led_patterns battery_pattern_3 = {
 	/* discharging: s0, s3, s5 */
-	{{LED_WHITE, 0}, {LED_AMBER, ALTERNATE(BLINK(10))}, {LED_OFF, 0}},
+	{ { LED_WHITE, 0 },
+	  { LED_AMBER, ALTERNATE(BLINK(10)) },
+	  { LED_OFF, 0 } },
 	/* charging: s0, s3, s5 */
-	{{LED_AMBER, PULSE_NO}, {LED_AMBER, PULSE_NO}, {LED_AMBER,  PULSE_NO}},
+	{ { LED_AMBER, PULSE_NO },
+	  { LED_AMBER, PULSE_NO },
+	  { LED_AMBER, PULSE_NO } },
 	/* full: s0, s3, s5 */
-	{{LED_WHITE, PULSE_NO}, {LED_WHITE, PULSE_NO}, {LED_WHITE,  PULSE_NO}},
+	{ { LED_WHITE, PULSE_NO },
+	  { LED_WHITE, PULSE_NO },
+	  { LED_WHITE, PULSE_NO } },
 };
 
 const static led_patterns battery_pattern_4 = {
 	/* discharging: s0, s3, s5 */
-	{{LED_WHITE, PULSE_NO}, {LED_WHITE, BLINK(10)}, {LED_OFF, PULSE_NO}},
+	{ { LED_WHITE, PULSE_NO },
+	  { LED_WHITE, BLINK(10) },
+	  { LED_OFF, PULSE_NO } },
 	/* charging: s0, s3, s5 */
-	{{LED_AMBER, PULSE_NO}, {LED_AMBER, PULSE_NO},  {LED_AMBER, PULSE_NO}},
+	{ { LED_AMBER, PULSE_NO },
+	  { LED_AMBER, PULSE_NO },
+	  { LED_AMBER, PULSE_NO } },
 	/* full: s0, s3, s5 */
-	{{LED_WHITE, PULSE_NO}, {LED_WHITE, PULSE_NO},  {LED_WHITE, PULSE_NO}},
+	{ { LED_WHITE, PULSE_NO },
+	  { LED_WHITE, PULSE_NO },
+	  { LED_WHITE, PULSE_NO } },
 };
 
 /* Patterns for battery LED and power LED. Initialized at run-time. */
 static led_patterns const *patterns[2];
 /* Pattern for battery error. Only blinking battery LED is supported. */
-static struct led_pattern battery_error = {LED_AMBER, BLINK(10)};
+static struct led_pattern battery_error = { LED_AMBER, BLINK(10) };
 /* Pattern for low state of charge. Only battery LED is supported. */
-static struct led_pattern low_battery = {LED_WHITE, BLINK(10)};
+static struct led_pattern low_battery = { LED_WHITE, BLINK(10) };
 /* Pattern for factory mode. Blinking 2-color battery LED. */
-static struct led_pattern battery_factory = {LED_FACTORY, BLINK(20)};
+static struct led_pattern battery_factory = { LED_FACTORY, BLINK(20) };
 static int low_battery_soc;
 static void led_charge_hook(void);
 static enum led_power_state power_state;
@@ -222,7 +260,7 @@ static void led_init(void)
 			patterns[1] = &power_pattern_1;
 		}
 		battery_error.pulse = BLINK(5);
-		low_battery_soc = 100;  /* 10.0% */
+		low_battery_soc = 100; /* 10.0% */
 		break;
 	case PROJECT_PANTHEON:
 		patterns[0] = &battery_pattern_2;
@@ -452,7 +490,7 @@ void config_led(enum ec_led_id id, enum led_charge_state charge)
 
 	pattern = patterns[id];
 	if (!pattern)
-		return;	/* This LED isn't present */
+		return; /* This LED isn't present */
 
 	start_tick(id, &(*pattern)[charge][power_state]);
 }
@@ -499,14 +537,15 @@ static void call_handler(void)
 		led_alert(1);
 		break;
 	case PWR_STATE_IDLE:
-		/* External power connected in IDLE. This is also used to show
-		 * factory mode when 'ectool chargecontrol idle' is run during
-		 * factory process. */
-		if (charge_get_flags() & CHARGE_FLAG_FORCE_IDLE)
-			led_factory(1);
+		/* External power connected in IDLE. */
 		break;
-	default:
-		;
+	case PWR_STATE_FORCED_IDLE:
+		/* This is used to show factory mode when
+		 * 'ectool chargecontrol idle' is run during factory process.
+		 */
+		led_factory(1);
+		break;
+	default:;
 	}
 }
 
@@ -548,7 +587,7 @@ static void print_config(enum ec_led_id id)
 	ccprintf("  Interval:%d\n", tick[id].interval);
 }
 
-static int command_led(int argc, char **argv)
+static int command_led(int argc, const char **argv)
 {
 	enum ec_led_id id = EC_LED_ID_BATTERY_LED;
 	static int alert = 0;
@@ -587,9 +626,10 @@ static int command_led(int argc, char **argv)
 	}
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(led, command_led,
-			"[debug|red|green|amber|off|alert|s0|s3|s5|conf|factory]",
-			"Turn on/off LED.");
+DECLARE_CONSOLE_COMMAND(
+	led, command_led,
+	"[debug|red|green|amber|off|alert|s0|s3|s5|conf|factory]",
+	"Turn on/off LED.");
 
 void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
 {
diff --git a/board/nami/usb_pd_policy.c b/board/nami/usb_pd_policy.c
index c1d5591d7c..e022adc5d9 100644
--- a/board/nami/usb_pd_policy.c
+++ b/board/nami/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,12 +22,12 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT];
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5,
-							TYPEC_RP_1A5};
+static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5,
+							 TYPEC_RP_1A5 };
 int board_vbus_source_enabled(int port)
 {
 	return vbus_en[port];
@@ -52,8 +52,7 @@ __override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
 int pd_set_power_supply_ready(int port)
 {
 	/* Disable charging */
-	gpio_set_level(port ? GPIO_USB_C1_CHARGE_L :
-			      GPIO_USB_C0_CHARGE_L, 1);
+	gpio_set_level(port ? GPIO_USB_C1_CHARGE_L : GPIO_USB_C0_CHARGE_L, 1);
 
 	/* Ensure we advertise the proper available current quota */
 	charge_manager_source_port(port, 1);
@@ -103,8 +102,7 @@ int pd_check_vconn_swap(int port)
 	return gpio_get_level(GPIO_PMIC_SLP_SUS_L);
 }
 
-__override void pd_execute_data_swap(int port,
-				     enum pd_data_role data_role)
+__override void pd_execute_data_swap(int port, enum pd_data_role data_role)
 {
 	/* Only port 0 supports device mode. */
 	if (port != 0)
diff --git a/board/nautilus/battery.c b/board/nautilus/battery.c
index aaa4a43c06..dd9b72e222 100644
--- a/board/nautilus/battery.c
+++ b/board/nautilus/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -17,19 +17,19 @@
 static enum battery_present batt_pres_prev = BP_NOT_SURE;
 
 /* Shutdown mode parameters to write to manufacturer access register */
-#define SB_SHIP_MODE_REG	SB_MANUFACTURER_ACCESS
-#define SB_SHUTDOWN_DATA	0x0010
+#define SB_SHIP_MODE_REG SB_MANUFACTURER_ACCESS
+#define SB_SHUTDOWN_DATA 0x0010
 
 /*
  * Unlike other smart batteries, Nautilus battery uses different bit fields
  * in manufacturer access register for the conditions of the CHG/DSG FETs.
  */
-#define BATFETS_SHIFT		(14)
-#define BATFETS_MASK		(0x3)
-#define BATFETS_DISABLED	(0x2)
+#define BATFETS_SHIFT (14)
+#define BATFETS_MASK (0x3)
+#define BATFETS_DISABLED (0x2)
 
-#define CHARGING_VOLTAGE_MV_SAFE	8400
-#define CHARGING_CURRENT_MA_SAFE	1500
+#define CHARGING_VOLTAGE_MV_SAFE 8400
+#define CHARGING_CURRENT_MA_SAFE 1500
 
 static const struct battery_info info = {
 	.voltage_max = 8700,
@@ -160,8 +160,9 @@ static int battery_init(void)
 {
 	int batt_status;
 
-	return battery_status(&batt_status) ? 0 :
-		!!(batt_status & STATUS_INITIALIZED);
+	return battery_status(&batt_status) ?
+		       0 :
+		       !!(batt_status & STATUS_INITIALIZED);
 }
 
 /*
@@ -185,8 +186,7 @@ static int battery_check_disconnect(void)
 	if (rv)
 		return BATTERY_DISCONNECT_ERROR;
 
-	if (((batt_mfgacc >> BATFETS_SHIFT) & BATFETS_MASK) ==
-	    BATFETS_DISABLED)
+	if (((batt_mfgacc >> BATFETS_SHIFT) & BATFETS_MASK) == BATFETS_DISABLED)
 		return BATTERY_DISCONNECTED;
 
 	return BATTERY_NOT_DISCONNECTED;
diff --git a/board/nautilus/board.c b/board/nautilus/board.c
index 73a40b8433..3cdd7abaf1 100644
--- a/board/nautilus/board.c
+++ b/board/nautilus/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -35,6 +35,7 @@
 #include "motion_lid.h"
 #include "motion_sense.h"
 #include "pi3usb9281.h"
+#include "panic.h"
 #include "power.h"
 #include "power_button.h"
 #include "spi.h"
@@ -52,8 +53,8 @@
 #include "util.h"
 #include "espi.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
@@ -75,9 +76,9 @@ static void vbus_discharge_handler(void)
 {
 	if (system_get_board_version() >= 2) {
 		pd_set_vbus_discharge(0,
-				gpio_get_level(GPIO_USB_C0_VBUS_WAKE_L));
+				      gpio_get_level(GPIO_USB_C0_VBUS_WAKE_L));
 		pd_set_vbus_discharge(1,
-				gpio_get_level(GPIO_USB_C1_VBUS_WAKE_L));
+				      gpio_get_level(GPIO_USB_C1_VBUS_WAKE_L));
 	}
 }
 DECLARE_DEFERRED(vbus_discharge_handler);
@@ -122,56 +123,47 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* Base detection */
-	[ADC_BASE_DET] = {"BASE_DET", NPCX_ADC_CH0,
-			  ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_BASE_DET] = { "BASE_DET", NPCX_ADC_CH0, ADC_MAX_VOLT,
+			   ADC_READ_MAX + 1, 0 },
 	/* Vbus sensing (10x voltage divider). */
-	[ADC_VBUS] = {"VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
+	[ADC_VBUS] = { "VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT * 10,
+		       ADC_READ_MAX + 1, 0 },
 	/*
 	 * Adapter current output or battery charging/discharging current (uV)
 	 * 18x amplification on charger side.
 	 */
-	[ADC_AMON_BMON] = {"AMON_BMON", NPCX_ADC_CH1, ADC_MAX_VOLT*1000/18,
-			   ADC_READ_MAX+1, 0},
+	[ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH1, ADC_MAX_VOLT * 1000 / 18,
+			    ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* I2C port map */
-const struct i2c_port_t i2c_ports[]  = {
-	{
-		.name = "tcpc0",
-		.port = NPCX_I2C_PORT0_0,
-		.kbps = 400,
-		.scl  = GPIO_I2C0_0_SCL,
-		.sda  = GPIO_I2C0_0_SDA
-	},
-	{
-		.name = "tcpc1",
-		.port = NPCX_I2C_PORT0_1,
-		.kbps = 400,
-		.scl  = GPIO_I2C0_1_SCL,
-		.sda  = GPIO_I2C0_1_SDA
-	},
-	{
-		.name = "charger",
-		.port = NPCX_I2C_PORT1,
-		.kbps = 100,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	},
-	{
-		.name = "pmic",
-		.port = NPCX_I2C_PORT2,
-		.kbps = 400,
-		.scl  = GPIO_I2C2_SCL,
-		.sda  = GPIO_I2C2_SDA
-	},
-	{
-		.name = "accelgyro",
-		.port = NPCX_I2C_PORT3,
-		.kbps = 400,
-		.scl  = GPIO_I2C3_SCL,
-		.sda  = GPIO_I2C3_SDA
-	},
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "tcpc0",
+	  .port = NPCX_I2C_PORT0_0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_0_SCL,
+	  .sda = GPIO_I2C0_0_SDA },
+	{ .name = "tcpc1",
+	  .port = NPCX_I2C_PORT0_1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_1_SCL,
+	  .sda = GPIO_I2C0_1_SDA },
+	{ .name = "charger",
+	  .port = NPCX_I2C_PORT1,
+	  .kbps = 100,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "pmic",
+	  .port = NPCX_I2C_PORT2,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "accelgyro",
+	  .port = NPCX_I2C_PORT3,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -195,16 +187,22 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	},
 	{
-		.usb_port = 1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	}
 };
 
@@ -222,7 +220,7 @@ BUILD_ASSERT(ARRAY_SIZE(pi3usb9281_chips) ==
 	     CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT);
 
 const int usb_port_enable[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT] = {
-        GPIO_USB1_ENABLE,
+	GPIO_USB1_ENABLE,
 };
 
 const struct charger_config_t chg_chips[] = {
@@ -260,9 +258,9 @@ void board_tcpc_init(void)
 	 */
 	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
 		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
 
 uint16_t tcpc_get_alert_status(void)
 {
@@ -282,13 +280,13 @@ uint16_t tcpc_get_alert_status(void)
 }
 
 const struct temp_sensor_t temp_sensors[] = {
-	{"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0},
+	{ "Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0 },
 
 	/* These BD99992GW temp sensors are only readable in S0 */
-	{"Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM1},
-	{"DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM2},
+	{ "Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM1 },
+	{ "DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM2 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -304,8 +302,8 @@ static void board_report_pmic_fault(const char *str)
 	uint32_t info;
 
 	/* RESETIRQ1 -- Bit 4: VRFAULT */
-	if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x8, &vrfault)
-	    != EC_SUCCESS)
+	if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x8, &vrfault) !=
+	    EC_SUCCESS)
 		return;
 
 	if (!(vrfault & BIT(4)))
@@ -414,8 +412,7 @@ static void board_pmic_enable_slp_s0_vr_decay(void)
 	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x38, 0x7a);
 }
 
-__override void power_board_handle_host_sleep_event(
-		enum host_sleep_event state)
+__override void power_board_handle_host_sleep_event(enum host_sleep_event state)
 {
 	if (state == HOST_SLEEP_EVENT_S0IX_SUSPEND)
 		board_pmic_enable_slp_s0_vr_decay();
@@ -463,13 +460,13 @@ static void board_init(void)
 	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L);
 
 	/* Level of sensor's I2C and interrupt are 3.3V on proto board */
-	if(system_get_board_version() < 2) {
+	if (system_get_board_version() < 2) {
 		/* ACCELGYRO3_INT_L */
 		gpio_set_flags(GPIO_ACCELGYRO3_INT_L, GPIO_INT_FALLING);
 		/* I2C3_SCL / I2C3_SDA */
 		gpio_set_flags(GPIO_I2C3_SCL, GPIO_INPUT);
 		gpio_set_flags(GPIO_I2C3_SDA, GPIO_INPUT);
-        }
+	}
 
 	/* Enable Gyro interrupts */
 	gpio_enable_interrupt(GPIO_ACCELGYRO3_INT_L);
@@ -519,10 +516,12 @@ int board_set_active_charge_port(int charge_port)
 	} else {
 		/* Make sure non-charging port is disabled */
 		gpio_set_level(charge_port ? GPIO_USB_C0_CHARGE_L :
-					     GPIO_USB_C1_CHARGE_L, 1);
+					     GPIO_USB_C1_CHARGE_L,
+			       1);
 		/* Enable charging port */
 		gpio_set_level(charge_port ? GPIO_USB_C1_CHARGE_L :
-					     GPIO_USB_C0_CHARGE_L, 0);
+					     GPIO_USB_C0_CHARGE_L,
+			       0);
 	}
 
 	return EC_SUCCESS;
@@ -536,16 +535,16 @@ int board_set_active_charge_port(int charge_port)
  * @param charge_ma     Desired charge limit (mA).
  * @param charge_mv     Negotiated charge voltage (mV).
  */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
-        /*
-         * Limit the input current to 96% negotiated limit,
-         * to account for the charger chip margin.
-         */
+	/*
+	 * Limit the input current to 96% negotiated limit,
+	 * to account for the charger chip margin.
+	 */
 	charge_ma = charge_ma * 96 / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-				   CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 /**
@@ -571,7 +570,7 @@ void board_hibernate(void)
 	CPRINTS("Triggering PMIC shutdown.");
 	uart_flush_output();
 
-    /* Trigger PMIC shutdown. */
+	/* Trigger PMIC shutdown. */
 	if (i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x49, 0x01)) {
 		/*
 		 * If we can't tell the PMIC to shutdown, instead reset
@@ -625,17 +624,13 @@ static struct bmi_drv_data_t g_bmi160_data;
 static struct accelgyro_saved_data_t g_bma255_data;
 
 /* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0 },
-	{ 0,  FLOAT_TO_FP(1), 0 },
-	{ 0, 0, FLOAT_TO_FP(-1) }
-};
+const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				       { 0, FLOAT_TO_FP(1), 0 },
+				       { 0, 0, FLOAT_TO_FP(-1) } };
 
-const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0 },
-	{ 0,  FLOAT_TO_FP(1), 0 },
-	{ 0, 0, FLOAT_TO_FP(-1) }
-};
+const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				      { 0, FLOAT_TO_FP(1), 0 },
+				      { 0, 0, FLOAT_TO_FP(-1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
@@ -779,13 +774,12 @@ int board_has_working_reset_flags(void)
  * I2C callbacks to ensure bus free time for battery I2C transactions is at
  * least 5ms.
  */
-#define BATTERY_FREE_MIN_DELTA_US		(5 * MSEC)
+#define BATTERY_FREE_MIN_DELTA_US (5 * MSEC)
 static timestamp_t battery_last_i2c_time;
 
 static int is_battery_i2c(const int port, const uint16_t addr_flags)
 {
-	return (port == I2C_PORT_BATTERY)
-		&& (addr_flags == BATTERY_ADDR_FLAGS);
+	return (port == I2C_PORT_BATTERY) && (addr_flags == BATTERY_ADDR_FLAGS);
 }
 
 void i2c_start_xfer_notify(const int port, const uint16_t addr_flags)
diff --git a/board/nautilus/board.h b/board/nautilus/board.h
index 3af9ee9b03..10d31f8555 100644
--- a/board/nautilus/board.h
+++ b/board/nautilus/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -63,8 +63,8 @@
 #define CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET
 #define CONFIG_CHIPSET_RESET_HOOK
 #define CONFIG_HOST_INTERFACE_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 #define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD
 
 /* Battery */
@@ -88,8 +88,8 @@
 #define CONFIG_CMD_CHARGER_ADC_AMON_BMON
 #define CONFIG_HOSTCMD_PD_CONTROL
 #define CONFIG_EXTPOWER_GPIO
-#undef   CONFIG_EXTPOWER_DEBOUNCE_MS
-#define  CONFIG_EXTPOWER_DEBOUNCE_MS 1000
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
+#define CONFIG_EXTPOWER_DEBOUNCE_MS 1000
 #define CONFIG_POWER_BUTTON
 #define CONFIG_POWER_BUTTON_X86
 #define CONFIG_POWER_COMMON
@@ -128,7 +128,7 @@
 /* Depends on how fast the AP boots and typical ODRs */
 #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
 
-#undef  CONFIG_UART_TX_BUF_SIZE
+#undef CONFIG_UART_TX_BUF_SIZE
 #define CONFIG_UART_TX_BUF_SIZE 2048
 
 #define CONFIG_TABLET_MODE
@@ -162,27 +162,27 @@
 #define CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT 2
 
 /* Optional feature to configure npcx chip */
-#define NPCX_UART_MODULE2	1 /* 1:GPIO64/65 as UART */
-#define NPCX_JTAG_MODULE2	0 /* 0:GPIO21/17/16/20 as JTAG */
-#define NPCX_TACH_SEL2		0 /* 0:GPIO40/73 as TACH */
+#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART */
+#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 as JTAG */
+#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 as TACH */
 
 /* I2C ports */
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT0_0
-#define I2C_PORT_TCPC1		NPCX_I2C_PORT0_1
-#define I2C_PORT_USB_CHARGER_1	NPCX_I2C_PORT0_1
-#define I2C_PORT_USB_CHARGER_0	NPCX_I2C_PORT1
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT1
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT1
-#define I2C_PORT_PMIC		NPCX_I2C_PORT2
-#define I2C_PORT_MP2949		NPCX_I2C_PORT2
-#define I2C_PORT_GYRO		NPCX_I2C_PORT3
-#define I2C_PORT_BARO		NPCX_I2C_PORT3
-#define I2C_PORT_ACCEL		I2C_PORT_GYRO
-#define I2C_PORT_THERMAL	I2C_PORT_PMIC
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0
+#define I2C_PORT_TCPC1 NPCX_I2C_PORT0_1
+#define I2C_PORT_USB_CHARGER_1 NPCX_I2C_PORT0_1
+#define I2C_PORT_USB_CHARGER_0 NPCX_I2C_PORT1
+#define I2C_PORT_CHARGER NPCX_I2C_PORT1
+#define I2C_PORT_BATTERY NPCX_I2C_PORT1
+#define I2C_PORT_PMIC NPCX_I2C_PORT2
+#define I2C_PORT_MP2949 NPCX_I2C_PORT2
+#define I2C_PORT_GYRO NPCX_I2C_PORT3
+#define I2C_PORT_BARO NPCX_I2C_PORT3
+#define I2C_PORT_ACCEL I2C_PORT_GYRO
+#define I2C_PORT_THERMAL I2C_PORT_PMIC
 
 /* I2C addresses */
-#define I2C_ADDR_BD99992_FLAGS	0x30
-#define I2C_ADDR_MP2949_FLAGS	0x20
+#define I2C_ADDR_BD99992_FLAGS 0x30
+#define I2C_ADDR_MP2949_FLAGS 0x20
 
 #ifndef __ASSEMBLER__
 
@@ -191,9 +191,9 @@
 
 /* Nautilus doesn't have systherm0 and systherm3 */
 enum temp_sensor_id {
-	TEMP_SENSOR_BATTERY,	/* BD99956GW TSENSE */
-	TEMP_SENSOR_CHARGER,	/* BD99992GW SYSTHERM1 */
-	TEMP_SENSOR_DRAM,	/* BD99992GW SYSTHERM2 */
+	TEMP_SENSOR_BATTERY, /* BD99956GW TSENSE */
+	TEMP_SENSOR_CHARGER, /* BD99992GW SYSTHERM1 */
+	TEMP_SENSOR_DRAM, /* BD99992GW SYSTHERM2 */
 	TEMP_SENSOR_COUNT
 };
 
@@ -211,28 +211,23 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum adc_channel {
-	ADC_BASE_DET,
-	ADC_VBUS,
-	ADC_AMON_BMON,
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_BASE_DET, ADC_VBUS, ADC_AMON_BMON, ADC_CH_COUNT };
 
 /* TODO(crosbug.com/p/61098): Verify the numbers below. */
 /*
  * delay to turn on the power supply max is ~16ms.
  * delay to turn off the power supply max is about ~180ms.
  */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	250000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* delay to turn on/off vconn */
 
 /* Define typical operating power and max power */
-#define PD_OPERATING_POWER_MW		15000
-#define PD_MAX_POWER_MW			45000
-#define PD_MAX_CURRENT_MA		3000
-#define PD_MAX_VOLTAGE_MV		20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 45000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Board specific handlers */
 int board_get_version(void);
diff --git a/board/nautilus/build.mk b/board/nautilus/build.mk
index f4bf21113d..8f3a138f56 100644
--- a/board/nautilus/build.mk
+++ b/board/nautilus/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/nautilus/ec.tasklist b/board/nautilus/ec.tasklist
index 8257734572..bcc5fc37e5 100644
--- a/board/nautilus/ec.tasklist
+++ b/board/nautilus/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nautilus/gpio.inc b/board/nautilus/gpio.inc
index 9cfc1e0bfd..13305d50fb 100644
--- a/board/nautilus/gpio.inc
+++ b/board/nautilus/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,10 +14,10 @@ GPIO_INT(USB_C1_PD_INT_ODL,	PIN(C, 5), GPIO_INT_FALLING,			tcpc_alert_event)
 GPIO_INT(PCH_SLP_S0_L,		PIN(7, 5), GPIO_INT_BOTH,			power_signal_interrupt)
 #endif
 /* Use VW signals instead of GPIOs */
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(PCH_SLP_S3_L,		PIN(7, 3), GPIO_INT_BOTH,			power_signal_interrupt)
 #endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 GPIO_INT(PCH_SLP_S4_L,		PIN(8, 6), GPIO_INT_BOTH,			power_signal_interrupt)
 #endif
 GPIO_INT(PCH_SLP_SUS_L,		PIN(6, 2), GPIO_INT_BOTH,			power_signal_interrupt)
diff --git a/board/nautilus/led.c b/board/nautilus/led.c
index 86567701f0..3fab136610 100644
--- a/board/nautilus/led.c
+++ b/board/nautilus/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -23,9 +23,8 @@
 #define LED_TOTAL_TICKS 16
 #define LED_ON_TICKS 8
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-	EC_LED_ID_BATTERY_LED};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED,
+					     EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -67,7 +66,6 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 	return EC_SUCCESS;
 }
 
-
 static void nautilus_led_set_power_battery(void)
 {
 	static unsigned int power_ticks;
@@ -82,9 +80,10 @@ static void nautilus_led_set_power_battery(void)
 
 	/* Flash red on critical battery, which usually inhibits AP power-on. */
 	if (battery_is_present() != BP_YES ||
-		charge_percent < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
-			set_color(((power_ticks++ % LED_TOTAL_TICKS) < LED_ON_TICKS) ?
-						  LED_RED : LED_OFF);
+	    charge_percent < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
+		set_color(((power_ticks++ % LED_TOTAL_TICKS) < LED_ON_TICKS) ?
+				  LED_RED :
+				  LED_OFF);
 		return;
 	}
 
@@ -92,7 +91,7 @@ static void nautilus_led_set_power_battery(void)
 	switch (chg_state) {
 	case PWR_STATE_DISCHARGE:
 		if ((charge_get_flags() & CHARGE_FLAG_EXTERNAL_POWER) &&
-			charge_percent >= BATTERY_LEVEL_NEAR_FULL)
+		    charge_percent >= BATTERY_LEVEL_NEAR_FULL)
 			cur_led_color = LED_GREEN;
 		else
 			cur_led_color = LED_OFF;
@@ -101,15 +100,17 @@ static void nautilus_led_set_power_battery(void)
 		cur_led_color = LED_RED;
 		break;
 	case PWR_STATE_ERROR:
-		cur_led_color = ((power_ticks++ % LED_TOTAL_TICKS)
-					  < LED_ON_TICKS) ? LED_RED : LED_GREEN;
+		cur_led_color =
+			((power_ticks++ % LED_TOTAL_TICKS) < LED_ON_TICKS) ?
+				LED_RED :
+				LED_GREEN;
 		break;
 	case PWR_STATE_CHARGE_NEAR_FULL:
 	case PWR_STATE_IDLE:
-		if(charge_get_flags() & CHARGE_FLAG_EXTERNAL_POWER)
-			cur_led_color = LED_GREEN;
-		else
-			cur_led_color = LED_OFF;
+		cur_led_color = LED_OFF;
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		cur_led_color = LED_GREEN;
 		break;
 	default:
 		cur_led_color = LED_RED;
@@ -128,8 +129,8 @@ static void nautilus_led_set_power_battery(void)
 static void led_tick(void)
 {
 	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED) &&
-		led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
-			nautilus_led_set_power_battery();
+	    led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
+		nautilus_led_set_power_battery();
 	}
 }
 
diff --git a/board/nautilus/usb_pd_policy.c b/board/nautilus/usb_pd_policy.c
index be4716b860..e01fd75f73 100644
--- a/board/nautilus/usb_pd_policy.c
+++ b/board/nautilus/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,12 +21,12 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT];
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5,
-							TYPEC_RP_1A5};
+static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5,
+							 TYPEC_RP_1A5 };
 
 int board_vbus_source_enabled(int port)
 {
@@ -47,8 +47,8 @@ static void board_vbus_update_source_current(int port)
 		 * is controlled by GPIO_USB_C0/1_5V_EN. Both of these signals
 		 * can remain outputs.
 		 */
-		gpio_set_level(gpio_3a_en, vbus_rp[port] == TYPEC_RP_3A0 ?
-				1 : 0);
+		gpio_set_level(gpio_3a_en,
+			       vbus_rp[port] == TYPEC_RP_3A0 ? 1 : 0);
 		gpio_set_level(gpio_5v_en, vbus_en[port]);
 	} else {
 		/*
@@ -60,8 +60,8 @@ static void board_vbus_update_source_current(int port)
 		 * 1505 mA.
 		 */
 		int flags = (vbus_rp[port] == TYPEC_RP_1A5 && vbus_en[port]) ?
-			(GPIO_INPUT | GPIO_PULL_UP) :
-			(GPIO_OUTPUT | GPIO_PULL_UP);
+				    (GPIO_INPUT | GPIO_PULL_UP) :
+				    (GPIO_OUTPUT | GPIO_PULL_UP);
 		gpio_set_level(gpio_5v_en, vbus_en[port]);
 		gpio_set_flags(gpio_5v_en, flags);
 	}
@@ -78,8 +78,7 @@ __override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
 int pd_set_power_supply_ready(int port)
 {
 	/* Disable charging */
-	gpio_set_level(port ? GPIO_USB_C1_CHARGE_L :
-			      GPIO_USB_C0_CHARGE_L, 1);
+	gpio_set_level(port ? GPIO_USB_C1_CHARGE_L : GPIO_USB_C0_CHARGE_L, 1);
 
 	/* Ensure we advertise the proper available current quota */
 	charge_manager_source_port(port, 1);
@@ -124,22 +123,19 @@ int pd_snk_is_vbus_provided(int port)
 				      GPIO_USB_C0_VBUS_WAKE_L);
 }
 
-
 int pd_check_vconn_swap(int port)
 {
 	/* in G3, do not allow vconn swap since pp5000_A rail is off */
 	return gpio_get_level(GPIO_PMIC_SLP_SUS_L);
 }
 
-__override void pd_execute_data_swap(int port,
-				     enum pd_data_role data_role)
+__override void pd_execute_data_swap(int port, enum pd_data_role data_role)
 {
 	/* Only port 0 supports device mode. */
 	if (port != 0)
 		return;
 
-	gpio_set_level(GPIO_USB2_OTG_ID,
-		      (data_role == PD_ROLE_UFP) ? 1 : 0);
+	gpio_set_level(GPIO_USB2_OTG_ID, (data_role == PD_ROLE_UFP) ? 1 : 0);
 	gpio_set_level(GPIO_USB2_OTG_VBUSSENSE,
-		      (data_role == PD_ROLE_UFP) ? 1 : 0);
+		       (data_role == PD_ROLE_UFP) ? 1 : 0);
 }
diff --git a/board/nightfury/battery.c b/board/nightfury/battery.c
index a3b251229b..9e9b9baa74 100644
--- a/board/nightfury/battery.c
+++ b/board/nightfury/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -111,10 +111,10 @@ enum battery_present variant_battery_present(void)
 
 int charger_profile_override(struct charge_state_data *curr)
 {
-	if(chipset_in_state(CHIPSET_STATE_ANY_OFF))
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
 		return 0;
 
-	if(curr->requested_current > CHARGING_CURRENT_45C)
+	if (curr->requested_current > CHARGING_CURRENT_45C)
 		curr->requested_current = CHARGING_CURRENT_45C;
 
 	return 0;
@@ -124,13 +124,13 @@ int charger_profile_override(struct charge_state_data *curr)
 #define PARAM_FASTCHARGE (CS_PARAM_CUSTOM_PROFILE_MIN + 0)
 
 enum ec_status charger_profile_override_get_param(uint32_t param,
-                                                  uint32_t *value)
+						  uint32_t *value)
 {
-        return EC_RES_INVALID_PARAM;
+	return EC_RES_INVALID_PARAM;
 }
 
 enum ec_status charger_profile_override_set_param(uint32_t param,
-                                                  uint32_t value)
+						  uint32_t value)
 {
-        return EC_RES_INVALID_PARAM;
+	return EC_RES_INVALID_PARAM;
 }
diff --git a/board/nightfury/board.c b/board/nightfury/board.c
index faaea01042..bfcdd14628 100644
--- a/board/nightfury/board.c
+++ b/board/nightfury/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -44,8 +44,8 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void ppc_interrupt(enum gpio_signal signal)
 {
@@ -101,23 +101,16 @@ static void bc12_interrupt(enum gpio_signal signal)
 
 /******************************************************************************/
 /* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
+const struct spi_device_t spi_devices[] = {};
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
 /******************************************************************************/
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = 0,
-		.freq = 10000
-	},
-	[PWM_CH_FAN] = {
-		.channel = 5,
-		.flags = PWM_CONFIG_OPEN_DRAIN,
-		.freq = 25000
-	},
+	[PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 },
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
@@ -142,14 +135,18 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_TCPC_0] = {
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 	},
 	[USB_PD_PORT_TCPC_1] = {
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 	}
 };
 
@@ -186,22 +183,18 @@ static struct opt3001_drv_data_t g_opt3001_data = {
 static struct stprivate_data g_lis2ds_data;
 
 /* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					      { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
 
 /*
  * TODO(b/124337208): P0 boards don't have this sensor mounted so the rotation
  * matrix can't be tested properly. This needs to be revisited after EVT to make
  * sure the rotation matrix for the lid sensor is correct.
  */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+					     { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
@@ -341,49 +334,49 @@ const struct fan_t fans[FAN_CH_COUNT] = {
 /******************************************************************************/
 /* MFT channels. These are logically separate from pwm_channels. */
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN },
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 /**********************************************************************/
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		"TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_2] = {
-		"TEMP_IA", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_3] = {
-		"TEMP_GT", NPCX_ADC_CH3, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_1] = { "TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_2] = { "TEMP_IA", NPCX_ADC_CH1, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_3] = { "TEMP_GT", NPCX_ADC_CH3, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "IA",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "GT",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_3},
+	[TEMP_SENSOR_1] = { .name = "Charger",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "IA",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "GT",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
 /* Nightfury Temperature sensors */
 /*
  * TODO(b/138578073): These setting need to be reviewed and set appropriately
- * for Nightfury. They matter when the EC is controlling the fan as opposed to DPTF
- * control.
+ * for Nightfury. They matter when the EC is controlling the fan as opposed to
+ * DPTF control.
  */
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_A \
-	{ \
+#define THERMAL_A                \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = 0, \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
diff --git a/board/nightfury/board.h b/board/nightfury/board.h
index 67e55f974e..9831741d5a 100644
--- a/board/nightfury/board.h
+++ b/board/nightfury/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -45,7 +45,7 @@
 /* BH1730 and TCS3400 ALS */
 #define CONFIG_ALS
 #define ALS_COUNT 1
-#define I2C_PORT_ALS      I2C_PORT_SENSOR
+#define I2C_PORT_ALS I2C_PORT_SENSOR
 #define CONFIG_ALS_OPT3001
 #define OPT3001_I2C_ADDR_FLAGS OPT3001_I2C_ADDR1_FLAGS
 
@@ -66,18 +66,18 @@
  * Nightfury will not use both BH1730_LUXTH3_1K condition
  * and BH1730_LUXTH4_1K condition.
  */
-#define BH1730_LUXTH1_1K                270
-#define BH1730_LUXTH1_D0_1K             19200
-#define BH1730_LUXTH1_D1_1K             30528
-#define BH1730_LUXTH2_1K                655360000
-#define BH1730_LUXTH2_D0_1K             11008
-#define BH1730_LUXTH2_D1_1K             10752
-#define BH1730_LUXTH3_1K                1030
-#define BH1730_LUXTH3_D0_1K             11008
-#define BH1730_LUXTH3_D1_1K             10752
-#define BH1730_LUXTH4_1K                3670
-#define BH1730_LUXTH4_D0_1K             11008
-#define BH1730_LUXTH4_D1_1K             10752
+#define BH1730_LUXTH1_1K 270
+#define BH1730_LUXTH1_D0_1K 19200
+#define BH1730_LUXTH1_D1_1K 30528
+#define BH1730_LUXTH2_1K 655360000
+#define BH1730_LUXTH2_D0_1K 11008
+#define BH1730_LUXTH2_D1_1K 10752
+#define BH1730_LUXTH3_1K 1030
+#define BH1730_LUXTH3_D0_1K 11008
+#define BH1730_LUXTH3_D1_1K 10752
+#define BH1730_LUXTH4_1K 3670
+#define BH1730_LUXTH4_D0_1K 11008
+#define BH1730_LUXTH4_D1_1K 10752
 
 /* USB Type C and USB PD defines */
 #define CONFIG_USB_MUX_RUNTIME_CONFIG
@@ -132,16 +132,16 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_AC_PRESENT		GPIO_ACOK_OD
-#define GPIO_PG_EC_RSMRST_ODL	GPIO_PG_EC_RSMRST_L
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_TEMP_SENSOR_POWER	GPIO_EN_A_RAILS
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L
+#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
 
 #ifndef __ASSEMBLER__
 
@@ -152,9 +152,9 @@
 extern enum gpio_signal gpio_en_pp5000_a;
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_1,	/* ADC0 */
-	ADC_TEMP_SENSOR_2,	/* ADC1 */
-	ADC_TEMP_SENSOR_3,	/* ADC3 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
+	ADC_TEMP_SENSOR_3, /* ADC3 */
 	ADC_CH_COUNT
 };
 
@@ -166,11 +166,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_FAN,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_FAN, PWM_CH_COUNT };
 
 enum fan_channel {
 	FAN_CH_0 = 0,
diff --git a/board/nightfury/build.mk b/board/nightfury/build.mk
index e91262fd43..169668e64c 100644
--- a/board/nightfury/build.mk
+++ b/board/nightfury/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/nightfury/ec.tasklist b/board/nightfury/ec.tasklist
index 101713dc6e..507845b304 100644
--- a/board/nightfury/ec.tasklist
+++ b/board/nightfury/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nightfury/gpio.inc b/board/nightfury/gpio.inc
index 68d847fe92..710bf07c17 100644
--- a/board/nightfury/gpio.inc
+++ b/board/nightfury/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,10 +16,10 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(PG_EC_RSMRST_L,       PIN(E, 2), GPIO_INT_BOTH, intel_x86_rsmrst_signal_interrupt)
diff --git a/board/nightfury/led.c b/board/nightfury/led.c
index dce39acfd6..9d2c367ab5 100644
--- a/board/nightfury/led.c
+++ b/board/nightfury/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -12,8 +12,8 @@
 #include "led_common.h"
 #include "led_onoff_states.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
 __override const int led_charge_lvl_1 = 1;
 
@@ -21,33 +21,36 @@ __override const int led_charge_lvl_2 = 100;
 
 /* Nightfury : There are 3 leds for AC, Battery and Power */
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED, 0.5 * LED_ONE_SEC},
-                                        {LED_OFF, 0.5 * LED_ONE_SEC} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED, 0.5 * LED_ONE_SEC},
-					{LED_OFF, 0.5 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC},
-					{LED_OFF, 1 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     0.5 * LED_ONE_SEC },
+					   { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_GREEN,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED,
+					    0.5 * LED_ONE_SEC },
+					  { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					 { LED_OFF, 1 * LED_ONE_SEC } },
+	};
 
 __override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_BLUE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -55,12 +58,11 @@ __override void led_set_color_power(enum ec_led_colors color)
 {
 	/* Don't set led if led_auto_control is disabled. */
 	if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) ||
-		!led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
+	    !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
 		return;
 	}
 
-	if (color == EC_LED_COLOR_BLUE)
-	{
+	if (color == EC_LED_COLOR_BLUE) {
 		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
 		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
 		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_ON_LVL);
@@ -74,15 +76,14 @@ __override void led_set_color_battery(enum ec_led_colors color)
 {
 	/* Don't set led if led_auto_control is disabled. */
 	if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) ||
-		!led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
+	    !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
 		return;
 	}
 
 	/* Battery leds must be turn off when blue led is on
 	 * because Nightfury has 3-in-1 led.
 	 */
-	if(!gpio_get_level(GPIO_PWR_LED_BLUE_L))
-	{
+	if (!gpio_get_level(GPIO_PWR_LED_BLUE_L)) {
 		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
 		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
 		return;
@@ -118,10 +119,13 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 {
 	if (led_id == EC_LED_ID_BATTERY_LED) {
 		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, !brightness[EC_LED_COLOR_GREEN]);
-		gpio_set_level(GPIO_BAT_LED_RED_L, !brightness[EC_LED_COLOR_RED]);
+		gpio_set_level(GPIO_BAT_LED_GREEN_L,
+			       !brightness[EC_LED_COLOR_GREEN]);
+		gpio_set_level(GPIO_BAT_LED_RED_L,
+			       !brightness[EC_LED_COLOR_RED]);
 	} else if (led_id == EC_LED_ID_POWER_LED) {
-		gpio_set_level(GPIO_PWR_LED_BLUE_L, !brightness[EC_LED_COLOR_BLUE]);
+		gpio_set_level(GPIO_PWR_LED_BLUE_L,
+			       !brightness[EC_LED_COLOR_BLUE]);
 		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
 		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
 	}
diff --git a/board/nipperkin/battery.c b/board/nipperkin/battery.c
index 5a3656c734..b8bedb535e 100644
--- a/board/nipperkin/battery.c
+++ b/board/nipperkin/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/nipperkin/board.c b/board/nipperkin/board.c
index 93db38b7ec..e4f3c0db57 100644
--- a/board/nipperkin/board.c
+++ b/board/nipperkin/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,7 +17,7 @@
 #include "driver/charger/isl9241.h"
 #include "driver/retimer/pi3hdx1204.h"
 #include "driver/retimer/ps8811.h"
-#include "driver/retimer/ps8818.h"
+#include "driver/retimer/ps8818_public.h"
 #include "driver/temp_sensor/sb_tsi.h"
 #include "driver/temp_sensor/pct2075.h"
 #include "extpower.h"
@@ -45,16 +45,15 @@ static void hdmi_hpd_interrupt(enum gpio_signal signal);
  * that we don't have pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-	{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-	{0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3},
-	{-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0},
-	{1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4},
-	{2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0},
-	{-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1},
-	{-1, -1},
+	{ -1, -1 }, { 0, 5 },	{ 1, 1 }, { 1, 0 },   { 0, 6 },	  { 0, 7 },
+	{ -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 },   { -1, -1 }, { 1, 6 },
+	{ 1, 7 },   { 3, 1 },	{ 2, 0 }, { 1, 5 },   { 2, 6 },	  { 2, 7 },
+	{ 2, 1 },   { 2, 4 },	{ 2, 5 }, { 1, 2 },   { 2, 3 },	  { 2, 2 },
+	{ 3, 0 },   { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 },	  { -1, -1 },
+	{ -1, -1 },
 };
 const int keyboard_factory_scan_pins_used =
-		ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 
 __override enum ec_error_list
 board_a1_ps8811_retimer_init(const struct usb_mux *me)
@@ -63,51 +62,46 @@ board_a1_ps8811_retimer_init(const struct usb_mux *me)
 }
 
 __override int board_c1_ps8818_mux_set(const struct usb_mux *me,
-				    mux_state_t mux_state)
+				       mux_state_t mux_state)
 {
 	int rv = EC_SUCCESS;
 
 	/* USB specific config */
 	if (mux_state & USB_PD_MUX_USB_ENABLED) {
 		/* Boost the USB gain */
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX1EQ_10G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_19DB);
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_APTX1EQ_10G_LEVEL,
+					      PS8818_EQ_LEVEL_UP_MASK,
+					      PS8818_EQ_LEVEL_UP_19DB);
 		if (rv)
 			return rv;
 
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX2EQ_10G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_19DB);
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_APTX2EQ_10G_LEVEL,
+					      PS8818_EQ_LEVEL_UP_MASK,
+					      PS8818_EQ_LEVEL_UP_19DB);
 		if (rv)
 			return rv;
 
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX1EQ_5G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_19DB);
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_APTX1EQ_5G_LEVEL,
+					      PS8818_EQ_LEVEL_UP_MASK,
+					      PS8818_EQ_LEVEL_UP_19DB);
 		if (rv)
 			return rv;
 
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX2EQ_5G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_19DB);
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_APTX2EQ_5G_LEVEL,
+					      PS8818_EQ_LEVEL_UP_MASK,
+					      PS8818_EQ_LEVEL_UP_19DB);
 		if (rv)
 			return rv;
 
 		/* Set the RX input termination */
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_RX_PHY,
-					PS8818_RX_INPUT_TERM_MASK,
-					PS8818_RX_INPUT_TERM_112_OHM);
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_RX_PHY,
+					      PS8818_RX_INPUT_TERM_MASK,
+					      PS8818_RX_INPUT_TERM_112_OHM);
 		if (rv)
 			return rv;
 	}
@@ -115,11 +109,10 @@ __override int board_c1_ps8818_mux_set(const struct usb_mux *me,
 	/* DP specific config */
 	if (mux_state & USB_PD_MUX_DP_ENABLED) {
 		/* Boost the DP gain */
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_DPEQ_LEVEL,
-					PS8818_DPEQ_LEVEL_UP_MASK,
-					PS8818_DPEQ_LEVEL_UP_19DB);
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_DPEQ_LEVEL,
+					      PS8818_DPEQ_LEVEL_UP_MASK,
+					      PS8818_DPEQ_LEVEL_UP_19DB);
 		if (rv)
 			return rv;
 
@@ -145,8 +138,7 @@ static void board_chipset_startup(void)
 	if (get_board_version() > 1)
 		pct2075_init();
 }
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup,
-	     HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
 
 int board_get_soc_temp_k(int idx, int *temp_k)
 {
@@ -336,17 +328,15 @@ static void board_chipset_resume(void)
 	ioex_set_level(IOEX_EN_PWR_HDMI, 1);
 	ioex_set_level(IOEX_HDMI_DATA_EN, 1);
 	msleep(PI3HDX1204_POWER_ON_DELAY_MS);
-	pi3hdx1204_enable(I2C_PORT_TCPC1,
-		PI3HDX1204_I2C_ADDR_FLAGS,
-		check_hdmi_hpd_status());
+	pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS,
+			  check_hdmi_hpd_status());
 }
 DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
 
 /* Called on AP suspend */
 static void board_chipset_suspend(void)
 {
-	pi3hdx1204_enable(I2C_PORT_TCPC1,
-		PI3HDX1204_I2C_ADDR_FLAGS, 0);
+	pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS, 0);
 	ioex_set_level(IOEX_HDMI_DATA_EN, 0);
 	ioex_set_level(IOEX_EN_PWR_HDMI, 0);
 	ioex_set_level(IOEX_USB_A1_PD_R_L, 0);
@@ -499,10 +489,9 @@ static void hdmi_hpd_handler(void)
 	int hpd = check_hdmi_hpd_status();
 
 	ccprints("HDMI HPD %d", hpd);
-	pi3hdx1204_enable(I2C_PORT_TCPC1,
-			  PI3HDX1204_I2C_ADDR_FLAGS,
-			  chipset_in_or_transitioning_to_state(CHIPSET_STATE_ON)
-			  && hpd);
+	pi3hdx1204_enable(
+		I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS,
+		chipset_in_or_transitioning_to_state(CHIPSET_STATE_ON) && hpd);
 }
 DECLARE_DEFERRED(hdmi_hpd_handler);
 
diff --git a/board/nipperkin/board.h b/board/nipperkin/board.h
index ce458113b2..af684e1f49 100644
--- a/board/nipperkin/board.h
+++ b/board/nipperkin/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,11 +21,11 @@
 #define CONFIG_CMD_BUTTON
 
 /* USB Type C and USB PD defines */
-#define PD_OPERATING_POWER_MW   15000
-#define PD_MAX_CURRENT_MA       5000
-#define PD_MAX_VOLTAGE_MV       20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_CURRENT_MA 5000
+#define PD_MAX_VOLTAGE_MV 20000
 /* Max Power = 100 W */
-#define PD_MAX_POWER_MW         ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
+#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
 
 #define CONFIG_CHARGER_PROFILE_OVERRIDE
 
diff --git a/board/nipperkin/board_fw_config.c b/board/nipperkin/board_fw_config.c
index c9fa01bc7a..e21e42689f 100644
--- a/board/nipperkin/board_fw_config.c
+++ b/board/nipperkin/board_fw_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,7 +9,8 @@
 bool board_has_kblight(void)
 {
 	return (get_fw_config_field(FW_CONFIG_KBLIGHT_OFFSET,
-			FW_CONFIG_KBLIGHT_WIDTH) == FW_CONFIG_KBLIGHT_YES);
+				    FW_CONFIG_KBLIGHT_WIDTH) ==
+		FW_CONFIG_KBLIGHT_YES);
 }
 
 enum board_usb_c1_mux board_get_usb_c1_mux(void)
@@ -25,6 +26,6 @@ enum board_usb_a1_retimer board_get_usb_a1_retimer(void)
 bool board_has_privacy_panel(void)
 {
 	return (get_fw_config_field(FW_CONFIG_KEYBOARD_OFFSET,
-			FW_CONFIG_KEYBOARD_WIDTH) ==
-			FW_CONFIG_KEYBOARD_PRIVACY_YES);
+				    FW_CONFIG_KEYBOARD_WIDTH) ==
+		FW_CONFIG_KEYBOARD_PRIVACY_YES);
 }
diff --git a/board/nipperkin/board_fw_config.h b/board/nipperkin/board_fw_config.h
index 77306ccb6f..f4673f732e 100644
--- a/board/nipperkin/board_fw_config.h
+++ b/board/nipperkin/board_fw_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,10 +13,10 @@
 /*
  * Keyboard Backlight (1 bit)
  */
-#define FW_CONFIG_KBLIGHT_OFFSET		0
-#define FW_CONFIG_KBLIGHT_WIDTH			1
-#define FW_CONFIG_KBLIGHT_NO			0
-#define FW_CONFIG_KBLIGHT_YES			1
+#define FW_CONFIG_KBLIGHT_OFFSET 0
+#define FW_CONFIG_KBLIGHT_WIDTH 1
+#define FW_CONFIG_KBLIGHT_NO 0
+#define FW_CONFIG_KBLIGHT_YES 1
 
 /*
  * Bit 1 ~ 6 not related to EC function
@@ -25,10 +25,10 @@
 /*
  * Keyboard (1 bit)
  */
-#define FW_CONFIG_KEYBOARD_OFFSET		7
-#define FW_CONFIG_KEYBOARD_WIDTH		1
-#define FW_CONFIG_KEYBOARD_PRIVACY_YES		0
-#define FW_CONFIG_KEYBOARD_PRIVACY_NO		1
+#define FW_CONFIG_KEYBOARD_OFFSET 7
+#define FW_CONFIG_KEYBOARD_WIDTH 1
+#define FW_CONFIG_KEYBOARD_PRIVACY_YES 0
+#define FW_CONFIG_KEYBOARD_PRIVACY_NO 1
 
 bool board_has_privacy_panel(void);
 
diff --git a/board/nipperkin/build.mk b/board/nipperkin/build.mk
index 5f5ffb9ce4..aad8b2ae09 100644
--- a/board/nipperkin/build.mk
+++ b/board/nipperkin/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/nipperkin/ec.tasklist b/board/nipperkin/ec.tasklist
index ccdff9847c..a127b13eba 100644
--- a/board/nipperkin/ec.tasklist
+++ b/board/nipperkin/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nipperkin/gpio.inc b/board/nipperkin/gpio.inc
index bd00c932af..0a8c6d9a65 100644
--- a/board/nipperkin/gpio.inc
+++ b/board/nipperkin/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nipperkin/led.c b/board/nipperkin/led.c
index 93131400d2..c7d6e0e0bc 100644
--- a/board/nipperkin/led.c
+++ b/board/nipperkin/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -35,22 +35,19 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
-enum led_port {
-	LED_LEFT_PORT = 0,
-	LED_RIGHT_PORT
-};
+enum led_port { LED_LEFT_PORT = 0, LED_RIGHT_PORT };
 
 static void led_set_color_battery(enum led_port port, enum led_color color)
 {
 	enum gpio_signal amber_led, white_led;
 
 	amber_led = (port == LED_LEFT_PORT ? GPIO_C0_CHARGE_LED_AMBER_L :
-				 GPIO_C1_CHARGE_LED_AMBER_L);
+					     GPIO_C1_CHARGE_LED_AMBER_L);
 	white_led = (port == LED_LEFT_PORT ? GPIO_C0_CHARGE_LED_WHITE_L :
-				 GPIO_C1_CHARGE_LED_WHITE_L);
+					     GPIO_C1_CHARGE_LED_WHITE_L);
 
 	switch (color) {
 	case LED_WHITE:
@@ -121,18 +118,19 @@ static void set_active_port_color(enum led_color color)
 	int port = charge_manager_get_active_charge_port();
 
 	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
-		led_set_color_battery(LED_RIGHT_PORT,
-				(port == LED_RIGHT_PORT) ? color : LED_OFF);
+		led_set_color_battery(LED_RIGHT_PORT, (port == LED_RIGHT_PORT) ?
+							      color :
+							      LED_OFF);
 	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
-		led_set_color_battery(LED_LEFT_PORT,
-				(port == LED_LEFT_PORT) ? color : LED_OFF);
+		led_set_color_battery(LED_LEFT_PORT, (port == LED_LEFT_PORT) ?
+							     color :
+							     LED_OFF);
 }
 
 static void led_set_battery(void)
 {
 	static int battery_ticks;
 	static int power_ticks;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
@@ -142,16 +140,19 @@ static void led_set_battery(void)
 	 * system suspend with non-charging state.
 	 */
 	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
-		charge_get_state() != PWR_STATE_CHARGE) {
-
+	    charge_get_state() != PWR_STATE_CHARGE) {
 		power_ticks++;
 
-		led_set_color_battery(LED_RIGHT_PORT, power_ticks
-				% LED_TICKS_PER_CYCLE_S3 < POWER_LED_ON_S3_TICKS
-				? LED_WHITE : LED_OFF);
-		led_set_color_battery(LED_LEFT_PORT, power_ticks
-				% LED_TICKS_PER_CYCLE_S3 < POWER_LED_ON_S3_TICKS
-				? LED_WHITE : LED_OFF);
+		led_set_color_battery(LED_RIGHT_PORT,
+				      power_ticks % LED_TICKS_PER_CYCLE_S3 <
+						      POWER_LED_ON_S3_TICKS ?
+					      LED_WHITE :
+					      LED_OFF);
+		led_set_color_battery(LED_LEFT_PORT,
+				      power_ticks % LED_TICKS_PER_CYCLE_S3 <
+						      POWER_LED_ON_S3_TICKS ?
+					      LED_WHITE :
+					      LED_OFF);
 		return;
 	}
 
@@ -165,30 +166,38 @@ static void led_set_battery(void)
 	case PWR_STATE_DISCHARGE:
 		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
 			if (charge_get_percent() < 10)
-				led_set_color_battery(LED_RIGHT_PORT,
-					(battery_ticks % LED_TICKS_PER_CYCLE
-					 < LED_ON_TICKS) ? LED_AMBER : LED_OFF);
+				led_set_color_battery(
+					LED_RIGHT_PORT,
+					(battery_ticks % LED_TICKS_PER_CYCLE <
+					 LED_ON_TICKS) ?
+						LED_AMBER :
+						LED_OFF);
 			else
 				led_set_color_battery(LED_RIGHT_PORT, LED_OFF);
 		}
 
 		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) {
 			if (charge_get_percent() < 10)
-				led_set_color_battery(LED_LEFT_PORT,
-					(battery_ticks % LED_TICKS_PER_CYCLE
-					 < LED_ON_TICKS) ? LED_AMBER : LED_OFF);
+				led_set_color_battery(
+					LED_LEFT_PORT,
+					(battery_ticks % LED_TICKS_PER_CYCLE <
+					 LED_ON_TICKS) ?
+						LED_AMBER :
+						LED_OFF);
 			else
 				led_set_color_battery(LED_LEFT_PORT, LED_OFF);
 		}
 		break;
 	case PWR_STATE_ERROR:
 		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
-			led_set_color_battery(LED_RIGHT_PORT,
+			led_set_color_battery(
+				LED_RIGHT_PORT,
 				(battery_ticks & 0x1) ? LED_AMBER : LED_OFF);
 		}
 
 		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) {
-			led_set_color_battery(LED_LEFT_PORT,
+			led_set_color_battery(
+				LED_LEFT_PORT,
 				(battery_ticks & 0x1) ? LED_AMBER : LED_OFF);
 		}
 		break;
@@ -197,12 +206,13 @@ static void led_set_battery(void)
 		set_active_port_color(LED_WHITE);
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			set_active_port_color((battery_ticks %
-				LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-				LED_AMBER : LED_OFF);
-		else
-			set_active_port_color(LED_WHITE);
+		set_active_port_color(LED_WHITE);
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		set_active_port_color(
+			(battery_ticks % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
+				LED_AMBER :
+				LED_OFF);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
diff --git a/board/nipperkin/thermal.c b/board/nipperkin/thermal.c
index eecf23a9e3..117a6d08fa 100644
--- a/board/nipperkin/thermal.c
+++ b/board/nipperkin/thermal.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,7 +18,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_THERMAL, outstr)
-#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
 
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
@@ -59,52 +59,51 @@ struct fan_step {
 static const struct fan_step fan_step_table[] = {
 	{
 		/* level 0 */
-		.on = {51, 0, 44, -1, -1, -1},
-		.off = {99, 99, 99, -1, -1, -1},
-		.rpm = {0},
+		.on = { 51, 0, 44, -1, -1, -1 },
+		.off = { 99, 99, 99, -1, -1, -1 },
+		.rpm = { 0 },
 	},
 	{
 		/* level 1 */
-		.on = {52, 0, 47, -1, -1, -1},
-		.off = {50, 99, 43, -1, -1, -1},
-		.rpm = {3000},
+		.on = { 52, 0, 47, -1, -1, -1 },
+		.off = { 50, 99, 43, -1, -1, -1 },
+		.rpm = { 3000 },
 	},
 	{
 		/* level 2 */
-		.on = {53, 0, 49, -1, -1, -1},
-		.off = {51, 99, 45, -1, -1, -1},
-		.rpm = {3400},
+		.on = { 53, 0, 49, -1, -1, -1 },
+		.off = { 51, 99, 45, -1, -1, -1 },
+		.rpm = { 3400 },
 	},
 	{
 		/* level 3 */
-		.on = {54, 0, 51, -1, -1, -1},
-		.off = {52, 99, 47, -1, -1, -1},
-		.rpm = {3800},
+		.on = { 54, 0, 51, -1, -1, -1 },
+		.off = { 52, 99, 47, -1, -1, -1 },
+		.rpm = { 3800 },
 	},
 	{
 		/* level 4 */
-		.on = {56, 50, 53, -1, -1, -1},
-		.off = {53, 47, 49, -1, -1, -1},
-		.rpm = {4100},
+		.on = { 56, 50, 53, -1, -1, -1 },
+		.off = { 53, 47, 49, -1, -1, -1 },
+		.rpm = { 4100 },
 	},
 	{
 		/* level 5 */
-		.on = {57, 52, 55, -1, -1, -1},
-		.off = {55, 49, 51, -1, -1, -1},
-		.rpm = {4400},
+		.on = { 57, 52, 55, -1, -1, -1 },
+		.off = { 55, 49, 51, -1, -1, -1 },
+		.rpm = { 4400 },
 	},
 	{
 		/* level 6 */
-		.on = {100, 100, 100, -1, -1, -1},
-		.off = {56, 51, 53, -1, -1, -1},
-		.rpm = {4900},
+		.on = { 100, 100, 100, -1, -1, -1 },
+		.off = { 56, 51, 53, -1, -1, -1 },
+		.rpm = { 4900 },
 	},
 };
 
 #define NUM_FAN_LEVELS ARRAY_SIZE(fan_step_table)
 
-BUILD_ASSERT(ARRAY_SIZE(fan_step_table) ==
-	ARRAY_SIZE(fan_step_table));
+BUILD_ASSERT(ARRAY_SIZE(fan_step_table) == ARRAY_SIZE(fan_step_table));
 
 int fan_table_to_rpm(int fan, int *temp)
 {
@@ -121,30 +120,29 @@ int fan_table_to_rpm(int fan, int *temp)
 	 *  3. invariant path. (return the current RPM)
 	 */
 	if (temp[TEMP_SENSOR_CHARGER] < prev_tmp[TEMP_SENSOR_CHARGER] ||
-		temp[TEMP_SENSOR_MEMORY] < prev_tmp[TEMP_SENSOR_MEMORY] ||
-		temp[TEMP_SENSOR_SOC] < prev_tmp[TEMP_SENSOR_SOC]) {
+	    temp[TEMP_SENSOR_MEMORY] < prev_tmp[TEMP_SENSOR_MEMORY] ||
+	    temp[TEMP_SENSOR_SOC] < prev_tmp[TEMP_SENSOR_SOC]) {
 		for (i = current_level; i > 0; i--) {
 			if (temp[TEMP_SENSOR_CHARGER] <
-				fan_step_table[i].off[TEMP_SENSOR_CHARGER] &&
-				temp[TEMP_SENSOR_MEMORY] <
-				fan_step_table[i].off[TEMP_SENSOR_MEMORY] &&
-				temp[TEMP_SENSOR_SOC] <
-				fan_step_table[i].off[TEMP_SENSOR_SOC]) {
+				    fan_step_table[i].off[TEMP_SENSOR_CHARGER] &&
+			    temp[TEMP_SENSOR_MEMORY] <
+				    fan_step_table[i].off[TEMP_SENSOR_MEMORY] &&
+			    temp[TEMP_SENSOR_SOC] <
+				    fan_step_table[i].off[TEMP_SENSOR_SOC]) {
 				current_level = i - 1;
 			} else
 				break;
 		}
 	} else if (temp[TEMP_SENSOR_CHARGER] > prev_tmp[TEMP_SENSOR_CHARGER] ||
-			temp[TEMP_SENSOR_MEMORY]
-				> prev_tmp[TEMP_SENSOR_MEMORY] ||
-			temp[TEMP_SENSOR_SOC] > prev_tmp[TEMP_SENSOR_SOC]) {
+		   temp[TEMP_SENSOR_MEMORY] > prev_tmp[TEMP_SENSOR_MEMORY] ||
+		   temp[TEMP_SENSOR_SOC] > prev_tmp[TEMP_SENSOR_SOC]) {
 		for (i = current_level; i < NUM_FAN_LEVELS; i++) {
 			if ((temp[TEMP_SENSOR_CHARGER] >
-				fan_step_table[i].on[TEMP_SENSOR_CHARGER] &&
-				temp[TEMP_SENSOR_MEMORY] >
-				fan_step_table[i].on[TEMP_SENSOR_MEMORY]) ||
-				temp[TEMP_SENSOR_SOC] >
-				fan_step_table[i].on[TEMP_SENSOR_SOC]) {
+				     fan_step_table[i].on[TEMP_SENSOR_CHARGER] &&
+			     temp[TEMP_SENSOR_MEMORY] >
+				     fan_step_table[i].on[TEMP_SENSOR_MEMORY]) ||
+			    temp[TEMP_SENSOR_SOC] >
+				    fan_step_table[i].on[TEMP_SENSOR_SOC]) {
 				current_level = i + 1;
 			} else
 				break;
@@ -167,15 +165,12 @@ int fan_table_to_rpm(int fan, int *temp)
 
 void board_override_fan_control(int fan, int *tmp)
 {
-	if (chipset_in_state(CHIPSET_STATE_ON |
-		CHIPSET_STATE_ANY_SUSPEND)) {
+	if (chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND)) {
 		fan_set_rpm_mode(FAN_CH(fan), 1);
-		fan_set_rpm_target(FAN_CH(fan),
-			fan_table_to_rpm(fan, tmp));
+		fan_set_rpm_target(FAN_CH(fan), fan_table_to_rpm(fan, tmp));
 	}
 }
 
-
 struct chg_curr_step {
 	int on;
 	int off;
@@ -183,12 +178,11 @@ struct chg_curr_step {
 };
 
 static const struct chg_curr_step chg_curr_table[] = {
-	{.on =  0, .off =  0, .curr_ma = 3566},
-	{.on = 66, .off = 65, .curr_ma = 2500},
-	{.on = 70, .off = 69, .curr_ma = 1500},
+	{ .on = 0, .off = 0, .curr_ma = 3566 },
+	{ .on = 66, .off = 65, .curr_ma = 2500 },
+	{ .on = 70, .off = 69, .curr_ma = 1500 },
 };
 
-
 #define NUM_CHG_CURRENT_LEVELS ARRAY_SIZE(chg_curr_table)
 
 int charger_profile_override(struct charge_state_data *curr)
@@ -200,7 +194,6 @@ int charger_profile_override(struct charge_state_data *curr)
 	static int current_level;
 	static int prev_tmp;
 
-
 	if (!(curr->batt.flags & BATT_FLAG_RESPONSIVE))
 		return 0;
 
@@ -214,12 +207,13 @@ int charger_profile_override(struct charge_state_data *curr)
 
 	if (chipset_in_state(CHIPSET_STATE_ON)) {
 		if (chg_temp_c < prev_tmp) {
-			if ((chg_temp_c <= chg_curr_table[current_level].off)
-				&& (current_level > 0))
+			if ((chg_temp_c <= chg_curr_table[current_level].off) &&
+			    (current_level > 0))
 				current_level -= 1;
 		} else if (chg_temp_c > prev_tmp) {
-			if ((chg_temp_c >= chg_curr_table[current_level + 1].on)
-				&& (current_level < NUM_CHG_CURRENT_LEVELS - 1))
+			if ((chg_temp_c >=
+			     chg_curr_table[current_level + 1].on) &&
+			    (current_level < NUM_CHG_CURRENT_LEVELS - 1))
 				current_level += 1;
 		}
 
diff --git a/board/nocturne/base_detect.c b/board/nocturne/base_detect.c
index 48c7b1f9dd..807aa3e14a 100644
--- a/board/nocturne/base_detect.c
+++ b/board/nocturne/base_detect.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,8 +26,8 @@
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USB, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args)
 
 #define DEFAULT_POLL_TIMEOUT_US (250 * MSEC)
 #define DEBOUNCE_TIMEOUT_US (20 * MSEC)
@@ -62,7 +62,6 @@
  */
 #define WINDOW_SIZE 5
 
-
 enum base_detect_state {
 	BASE_DETACHED = 0,
 	BASE_ATTACHED_DEBOUNCE,
@@ -82,7 +81,7 @@ static timestamp_t detached_decision_deadline;
 static void enable_base_interrupts(int enable)
 {
 	int (*fn)(enum gpio_signal) = enable ? gpio_enable_interrupt :
-		gpio_disable_interrupt;
+					       gpio_disable_interrupt;
 
 	/* This pin is present on boards newer than rev 0. */
 	if (board_get_version() > 0)
@@ -141,28 +140,26 @@ static void base_detect_changed(void)
 static int base_seems_attached(int attach_pin_mv, int detach_pin_mv)
 {
 	/* We can't tell if we don't have good readings. */
-	if (attach_pin_mv == ADC_READ_ERROR ||
-	    detach_pin_mv == ADC_READ_ERROR)
+	if (attach_pin_mv == ADC_READ_ERROR || detach_pin_mv == ADC_READ_ERROR)
 		return 0;
 
 	if (gpio_get_level(GPIO_BASE_PWR_EN))
 		return (attach_pin_mv >= PWREN_ATTACH_MIN_MV) &&
-			(detach_pin_mv >= DETACH_MIN_MV);
+		       (detach_pin_mv >= DETACH_MIN_MV);
 	else
 		return (attach_pin_mv <= ATTACH_MAX_MV) &&
-			(attach_pin_mv >= ATTACH_MIN_MV) &&
-			(detach_pin_mv <= DETACH_MIN_MV);
+		       (attach_pin_mv >= ATTACH_MIN_MV) &&
+		       (detach_pin_mv <= DETACH_MIN_MV);
 }
 
 static int base_seems_detached(int attach_pin_mv, int detach_pin_mv)
 {
 	/* We can't tell if we don't have good readings. */
-	if (attach_pin_mv == ADC_READ_ERROR ||
-	    detach_pin_mv == ADC_READ_ERROR)
+	if (attach_pin_mv == ADC_READ_ERROR || detach_pin_mv == ADC_READ_ERROR)
 		return 0;
 
 	return (attach_pin_mv >= PWREN_ATTACH_MIN_MV) &&
-		(detach_pin_mv <= DETACH_MIN_MV);
+	       (detach_pin_mv <= DETACH_MIN_MV);
 }
 
 static void set_state(enum base_detect_state new_state)
@@ -194,9 +191,9 @@ static void base_detect_deferred(void)
 
 	if (forced_state != BASE_NO_FORCED_STATE) {
 		if (state != forced_state) {
-			CPRINTS("BD forced  %s",
-				forced_state == BASE_ATTACHED ?
-				"attached" : "detached");
+			CPRINTS("BD forced  %s", forced_state == BASE_ATTACHED ?
+							 "attached" :
+							 "detached");
 			set_state(forced_state);
 			base_detect_changed();
 		}
@@ -212,8 +209,7 @@ static void base_detect_deferred(void)
 	if (debug) {
 		int i;
 
-		CPRINTS("BD st%d: att: %dmV det: %dmV", state,
-			attach_reading,
+		CPRINTS("BD st%d: att: %dmV det: %dmV", state, attach_reading,
 			detach_reading);
 		CPRINTF("det readings = [");
 		for (i = 0; i < WINDOW_SIZE; i++)
@@ -341,7 +337,6 @@ static void check_and_reapply_base_power_deferred(void)
 		hook_call_deferred(&clear_base_power_on_attempts_deferred_data,
 				   SECOND);
 	}
-
 }
 DECLARE_DEFERRED(check_and_reapply_base_power_deferred);
 
@@ -366,20 +361,19 @@ void base_pwr_fault_interrupt(enum gpio_signal s)
 	}
 }
 
-static int command_basedetectdebug(int argc, char **argv)
+static int command_basedetectdebug(int argc, const char **argv)
 {
 	if ((argc > 1) && !parse_bool(argv[1], &debug))
 		return EC_ERROR_PARAM1;
 
-	CPRINTS("BD: %sst%d", forced_state != BASE_NO_FORCED_STATE ?
-						  "forced " : "", state);
+	CPRINTS("BD: %sst%d",
+		forced_state != BASE_NO_FORCED_STATE ? "forced " : "", state);
 	return EC_SUCCESS;
 }
 
 DECLARE_CONSOLE_COMMAND(basedebug, command_basedetectdebug, "[ena|dis]",
 			"En/Disable base detection debug");
 
-
 void base_force_state(enum ec_set_base_state_cmd state)
 {
 	if (state == EC_SET_BASE_STATE_ATTACH)
diff --git a/board/nocturne/battery.c b/board/nocturne/battery.c
index 0e568ca6f9..c81640e983 100644
--- a/board/nocturne/battery.c
+++ b/board/nocturne/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -21,26 +21,26 @@
 #include "usb_pd.h"
 
 /* Shutdown mode parameter to write to manufacturer access register */
-#define SB_SHUTDOWN_DATA	0x0010
+#define SB_SHUTDOWN_DATA 0x0010
 
 /*
  * We need to stop charging the battery when the DRAM temperature sensor gets
  * over 47 C (320 K), and resume charging once it cools back down.
  */
-#define DRAM_STOPCHARGE_TEMP_K	320
+#define DRAM_STOPCHARGE_TEMP_K 320
 
 /* Battery info */
 static const struct battery_info info = {
-	.voltage_max		= 8880,
-	.voltage_normal		= 7700,
-	.voltage_min		= 6000,
-	.precharge_current	= 160,
-	.start_charging_min_c	= 10,
-	.start_charging_max_c	= 50,
-	.charging_min_c		= 10,
-	.charging_max_c		= 50,
-	.discharging_min_c	= -20,
-	.discharging_max_c	= 60,
+	.voltage_max = 8880,
+	.voltage_normal = 7700,
+	.voltage_min = 6000,
+	.precharge_current = 160,
+	.start_charging_min_c = 10,
+	.start_charging_max_c = 50,
+	.charging_min_c = 10,
+	.charging_max_c = 50,
+	.discharging_min_c = -20,
+	.discharging_max_c = 60,
 };
 
 int board_cut_off_battery(void)
@@ -78,8 +78,8 @@ enum battery_disconnect_state battery_get_disconnect_state(void)
 		return BATTERY_NOT_DISCONNECTED;
 
 	/* Check if battery discharge FET is disabled. */
-	rv = sb_read_mfgacc(PARAM_OPERATION_STATUS,
-			    SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data));
+	rv = sb_read_mfgacc(PARAM_OPERATION_STATUS, SB_ALT_MANUFACTURER_ACCESS,
+			    data, sizeof(data));
 	if (rv)
 		return BATTERY_DISCONNECT_ERROR;
 	if (~data[3] & (BATTERY_DISCHARGING_DISABLED)) {
@@ -91,8 +91,8 @@ enum battery_disconnect_state battery_get_disconnect_state(void)
 	 * Battery discharge FET is disabled.  Verify that we didn't enter this
 	 * state due to a safety fault.
 	 */
-	rv = sb_read_mfgacc(PARAM_SAFETY_STATUS,
-			    SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data));
+	rv = sb_read_mfgacc(PARAM_SAFETY_STATUS, SB_ALT_MANUFACTURER_ACCESS,
+			    data, sizeof(data));
 	if (rv || data[2] || data[3] || data[4] || data[5])
 		return BATTERY_DISCONNECT_ERROR;
 
diff --git a/board/nocturne/board.c b/board/nocturne/board.c
index ac29dfb942..d32f036844 100644
--- a/board/nocturne/board.c
+++ b/board/nocturne/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -30,6 +30,7 @@
 #include "lpc.h"
 #include "mkbp_event.h"
 #include "motion_sense.h"
+#include "panic.h"
 #include "power.h"
 #include "power_button.h"
 #include "pwm.h"
@@ -46,8 +47,8 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void tcpc_alert_event(enum gpio_signal s)
 {
@@ -101,80 +102,67 @@ const enum gpio_signal hibernate_wake_pins[] = {
 	GPIO_AC_PRESENT,
 	GPIO_POWER_BUTTON_L,
 };
-const int hibernate_wake_pins_used =  ARRAY_SIZE(hibernate_wake_pins);
+const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 
 const struct adc_t adc_channels[] = {
-	[ADC_BASE_ATTACH] = {
-		"BASE ATTACH", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0
-	},
+	[ADC_BASE_ATTACH] = { "BASE ATTACH", NPCX_ADC_CH0, ADC_MAX_VOLT,
+			      ADC_READ_MAX + 1, 0 },
 
-	[ADC_BASE_DETACH] = {
-		"BASE DETACH", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0
-	},
+	[ADC_BASE_DETACH] = { "BASE DETACH", NPCX_ADC_CH1, ADC_MAX_VOLT,
+			      ADC_READ_MAX + 1, 0 },
 };
 
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_DB0_LED_RED] =   { 3, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-				   986 },
+	[PWM_CH_DB0_LED_RED] = { 3, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+				 986 },
 	[PWM_CH_DB0_LED_GREEN] = { 0, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
 				   986 },
-	[PWM_CH_DB0_LED_BLUE] =  { 2, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-				   986 },
-	[PWM_CH_DB1_LED_RED] =   { 7, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-				   986 },
+	[PWM_CH_DB0_LED_BLUE] = { 2, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+				  986 },
+	[PWM_CH_DB1_LED_RED] = { 7, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+				 986 },
 	[PWM_CH_DB1_LED_GREEN] = { 5, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
 				   986 },
-	[PWM_CH_DB1_LED_BLUE] =  { 6, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
-				   986 },
+	[PWM_CH_DB1_LED_BLUE] = { 6, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+				  986 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
 /* I2C port map */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "battery",
-		.port = I2C_PORT_BATTERY,
-		.kbps = 100,
-		.scl  = GPIO_EC_I2C4_BATTERY_SCL,
-		.sda  = GPIO_EC_I2C4_BATTERY_SDA
-	},
-
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl  = GPIO_EC_I2C0_POWER_SCL,
-		.sda  = GPIO_EC_I2C0_POWER_SDA
-	},
-
-	{
-		.name = "als_gyro",
-		.port = I2C_PORT_ALS_GYRO,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C5_ALS_GYRO_SCL,
-		.sda  = GPIO_EC_I2C5_ALS_GYRO_SDA
-	},
-
-	{
-		.name = "usbc0",
-		.port = I2C_PORT_USB_C0,
-		.kbps = 100,
-		.scl  = GPIO_USB_C0_SCL,
-		.sda  = GPIO_USB_C0_SDA
-	},
-
-	{
-		.name = "usbc1",
-		.port = I2C_PORT_USB_C1,
-		.kbps = 100,
-		.scl  = GPIO_USB_C1_SCL,
-		.sda  = GPIO_USB_C1_SDA
-	},
+	{ .name = "battery",
+	  .port = I2C_PORT_BATTERY,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C4_BATTERY_SCL,
+	  .sda = GPIO_EC_I2C4_BATTERY_SDA },
+
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C0_POWER_SCL,
+	  .sda = GPIO_EC_I2C0_POWER_SDA },
+
+	{ .name = "als_gyro",
+	  .port = I2C_PORT_ALS_GYRO,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C5_ALS_GYRO_SCL,
+	  .sda = GPIO_EC_I2C5_ALS_GYRO_SDA },
+
+	{ .name = "usbc0",
+	  .port = I2C_PORT_USB_C0,
+	  .kbps = 100,
+	  .scl = GPIO_USB_C0_SCL,
+	  .sda = GPIO_USB_C0_SDA },
+
+	{ .name = "usbc1",
+	  .port = I2C_PORT_USB_C1,
+	  .kbps = 100,
+	  .scl = GPIO_USB_C1_SCL,
+	  .sda = GPIO_USB_C1_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
-
 /*
  * Motion Sense
  */
@@ -191,11 +179,9 @@ static struct opt3001_drv_data_t g_opt3001_data = {
 };
 
 /* Matrix to rotate accel/gyro into standard reference frame. */
-const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1),  0},
-	{ FLOAT_TO_FP(-1), 0,  0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+				      { FLOAT_TO_FP(-1), 0, 0 },
+				      { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
@@ -303,11 +289,9 @@ static void enable_sensor_irqs(void)
 DECLARE_HOOK(HOOK_CHIPSET_RESUME, enable_sensor_irqs, HOOK_PRIO_DEFAULT);
 
 struct ppc_config_t ppc_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
+	{ .i2c_port = I2C_PORT_USB_C0,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
 	{
 		.i2c_port = I2C_PORT_USB_C1,
 		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
@@ -335,17 +319,23 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	},
 
 	{
-		.usb_port = 1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	},
 };
 
@@ -366,8 +356,7 @@ DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
 static void imvp8_tune_deferred(void)
 {
 	/* For the IMVP8, reduce the steps during decay from 3 to 1. */
-	if (i2c_write16(I2C_PORT_POWER, I2C_ADDR_MP2949_FLAGS,
-			0xFA, 0x0AC5))
+	if (i2c_write16(I2C_PORT_POWER, I2C_ADDR_MP2949_FLAGS, 0xFA, 0x0AC5))
 		CPRINTS("Failed to change step decay!");
 }
 DECLARE_DEFERRED(imvp8_tune_deferred);
@@ -522,8 +511,7 @@ static void board_pmic_enable_slp_s0_vr_decay(void)
 	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x38, 0x6a);
 }
 
-__override void power_board_handle_host_sleep_event(
-		enum host_sleep_event state)
+__override void power_board_handle_host_sleep_event(enum host_sleep_event state)
 {
 	if (state == HOST_SLEEP_EVENT_S0IX_SUSPEND)
 		board_pmic_enable_slp_s0_vr_decay();
@@ -536,8 +524,7 @@ static void board_pmic_init(void)
 	int pgmask1;
 
 	/* Mask V5A_DS3_PG from PMIC PGMASK1. */
-	if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS,
-		      0x18, &pgmask1))
+	if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x18, &pgmask1))
 		return;
 	pgmask1 |= BIT(2);
 	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x18, pgmask1);
@@ -611,19 +598,19 @@ static int read_gyro_sensor_temp(int idx, int *temp_ptr)
 }
 
 const struct temp_sensor_t temp_sensors[] = {
-	{"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0},
+	{ "Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0 },
 
 	/* These BD99992GW temp sensors are only readable in S0 */
-	{"Ambient", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM0},
-	{"Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM1},
-	{"DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM2},
-	{"eMMC", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM3},
+	{ "Ambient", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM0 },
+	{ "Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM1 },
+	{ "DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM2 },
+	{ "eMMC", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM3 },
 	/* The Gyro temperature sensor is only readable in S0. */
-	{"Gyro", TEMP_SENSOR_TYPE_BOARD, read_gyro_sensor_temp, LID_GYRO}
+	{ "Gyro", TEMP_SENSOR_TYPE_BOARD, read_gyro_sensor_temp, LID_GYRO }
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -633,16 +620,15 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
  */
 struct ec_thermal_config thermal_params[] = {
 	/* {Twarn, Thigh, Thalt}, fan_off, fan_max */
-	{{0,          0, 0}, {0, 0, 0}, 0, 0}, /* Battery */
-	{{0,          0, 0}, {0, 0, 0}, 0, 0}, /* Ambient */
-	{{0,          0, 0}, {0, 0, 0}, 0, 0}, /* Charger */
-	{{0, C_TO_K(52), 0}, {0, 0, 0}, 0, 0}, /* DRAM */
-	{{0,          0, 0}, {0, 0, 0}, 0, 0}, /* eMMC */
-	{{0,          0, 0}, {0, 0, 0}, 0, 0}  /* Gyro */
+	{ { 0, 0, 0 }, { 0, 0, 0 }, 0, 0 }, /* Battery */
+	{ { 0, 0, 0 }, { 0, 0, 0 }, 0, 0 }, /* Ambient */
+	{ { 0, 0, 0 }, { 0, 0, 0 }, 0, 0 }, /* Charger */
+	{ { 0, C_TO_K(52), 0 }, { 0, 0, 0 }, 0, 0 }, /* DRAM */
+	{ { 0, 0, 0 }, { 0, 0, 0 }, 0, 0 }, /* eMMC */
+	{ { 0, 0, 0 }, { 0, 0, 0 }, 0, 0 } /* Gyro */
 };
 BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
 
-
 /*
  * Check if PMIC fault registers indicate VR fault. If yes, print out fault
  * register info to console. Additionally, set panic reason so that the OS can
@@ -655,8 +641,8 @@ static void board_report_pmic_fault(const char *str)
 	uint32_t info;
 
 	/* RESETIRQ1 -- Bit 4: VRFAULT */
-	if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x8, &vrfault)
-	    != EC_SUCCESS)
+	if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x8, &vrfault) !=
+	    EC_SUCCESS)
 		return;
 
 	if (!(vrfault & BIT(4)))
@@ -709,8 +695,7 @@ void board_set_tcpc_power_mode(int port, int mode)
 
 int board_set_active_charge_port(int port)
 {
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	int i;
 	int rv;
 	int old_port;
@@ -775,8 +760,8 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
 
diff --git a/board/nocturne/board.h b/board/nocturne/board.h
index 2a21392313..279016ec98 100644
--- a/board/nocturne/board.h
+++ b/board/nocturne/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,14 +12,14 @@
  * By default, enable all console messages excepted HC, ACPI and event:
  * The sensor stack is generating a lot of activity.
  */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
 #undef CONFIG_HOSTCMD_DEBUG_MODE
 #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
 
 /* NPCX7 config */
-#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
-#define NPCX_TACH_SEL2    0  /* No tach. */
-#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
+#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */
+#define NPCX_TACH_SEL2 0 /* No tach. */
+#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */
 #define CONFIG_HIBERNATE_PSL
 
 /* Internal SPI flash on NPCX7 */
@@ -56,7 +56,7 @@
 #define CONFIG_BATTERY_SMART
 #define CONFIG_BATTERY_REVIVE_DISCONNECT
 #define CONFIG_BATTERY_PRESENT_GPIO GPIO_BAT_PRESENT_L
-#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV	9000
+#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV 9000
 
 /* Buttons / Switches */
 #define CONFIG_BASE_ATTACHED_SWITCH
@@ -85,7 +85,7 @@
 
 /* MKBP */
 #define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_EVENT_WAKEUP_MASK (1<<EC_MKBP_EVENT_SWITCH)
+#define CONFIG_MKBP_EVENT_WAKEUP_MASK (1 << EC_MKBP_EVENT_SWITCH)
 #define CONFIG_MKBP_INPUT_DEVICES
 #define CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT
 
@@ -104,8 +104,7 @@
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL)
 #define CONFIG_SYNC
-#define CONFIG_SYNC_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
+#define CONFIG_SYNC_INT_EVENT TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
 #define CONFIG_TEMP_SENSOR
 #define CONFIG_TEMP_SENSOR_BD99992GW
 #define CONFIG_THERMISTOR_NCP15WB
@@ -160,9 +159,9 @@
 #define CONFIG_USBC_VCONN_SWAP
 
 /* Define typical operating power and max power. */
-#define PD_MAX_VOLTAGE_MV     20000
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_POWER_MW       45000
+#define PD_MAX_VOLTAGE_MV 20000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_POWER_MW 45000
 #define PD_OPERATING_POWER_MW 15000
 
 /* TODO(aaboagye): Verify these timings. */
@@ -170,52 +169,52 @@
  * delay to turn on the power supply max is ~16ms.
  * delay to turn off the power supply max is about ~180ms.
  */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY   30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY  250000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* I2C config */
-#define I2C_PORT_CHARGER  I2C_PORT_POWER
-#define I2C_PORT_PMIC     I2C_PORT_POWER
-#define I2C_PORT_POWER    NPCX_I2C_PORT0_0
-#define I2C_PORT_BATTERY  NPCX_I2C_PORT4_1
+#define I2C_PORT_CHARGER I2C_PORT_POWER
+#define I2C_PORT_PMIC I2C_PORT_POWER
+#define I2C_PORT_POWER NPCX_I2C_PORT0_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT4_1
 #define I2C_PORT_ALS_GYRO NPCX_I2C_PORT5_0
-#define I2C_PORT_ACCEL    I2C_PORT_ALS_GYRO
-#define I2C_PORT_USB_C0   NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1   NPCX_I2C_PORT2_0
-#define I2C_PORT_THERMAL  I2C_PORT_PMIC
+#define I2C_PORT_ACCEL I2C_PORT_ALS_GYRO
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0
+#define I2C_PORT_THERMAL I2C_PORT_PMIC
 
 #define GPIO_USB_C0_SCL GPIO_EC_I2C1_USB_C0_SCL
 #define GPIO_USB_C0_SDA GPIO_EC_I2C1_USB_C0_SDA
 #define GPIO_USB_C1_SCL GPIO_EC_I2C2_USB_C1_SCL
 #define GPIO_USB_C1_SDA GPIO_EC_I2C2_USB_C1_SDA
 
-#define I2C_ADDR_MP2949_FLAGS  0x20
+#define I2C_ADDR_MP2949_FLAGS 0x20
 #define I2C_ADDR_BD99992_FLAGS 0x30
 
 /*
  * Remapping of schematic GPIO names to common GPIO names expected (hardcoded)
  * in the EC code base.
  */
-#define GPIO_AC_PRESENT       GPIO_ACOK_OD
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
 #define GPIO_ENABLE_BACKLIGHT GPIO_EC_BL_DISABLE_ODL
-#define GPIO_BAT_PRESENT_L    GPIO_EC_BATT_PRES_L
-#define GPIO_ENTERING_RW      GPIO_EC_ENTERING_RW
-#define GPIO_PCH_PWRBTN_L     GPIO_EC_PCH_PWR_BTN_L
-#define GPIO_PCH_RSMRST_L     GPIO_RSMRST_L
-#define GPIO_PCH_RTCRST       GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L     GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L     GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L     GPIO_SLP_S4_L
-#define GPIO_PCH_SLP_SUS_L    GPIO_SLP_SUS_L_PCH
-#define GPIO_PCH_WAKE_L       GPIO_EC_PCH_WAKE_L
-#define GPIO_PMIC_DPWROK      GPIO_ROP_DSW_PWROK_EC
-#define GPIO_PMIC_SLP_SUS_L   GPIO_SLP_SUS_L_PMIC
-#define GPIO_POWER_BUTTON_L   GPIO_EC_PWR_BTN_IN_ODL
-#define GPIO_CPU_PROCHOT      GPIO_EC_PROCHOT_ODL
+#define GPIO_BAT_PRESENT_L GPIO_EC_BATT_PRES_L
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_L
+#define GPIO_PCH_RSMRST_L GPIO_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L
+#define GPIO_PCH_SLP_SUS_L GPIO_SLP_SUS_L_PCH
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_L
+#define GPIO_PMIC_DPWROK GPIO_ROP_DSW_PWROK_EC
+#define GPIO_PMIC_SLP_SUS_L GPIO_SLP_SUS_L_PMIC
+#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_IN_ODL
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
 #define GPIO_PG_EC_RSMRST_ODL GPIO_ROP_EC_RSMRST_L
-#define GPIO_VOLUME_UP_L      GPIO_H1_EC_VOL_UP_ODL
-#define GPIO_VOLUME_DOWN_L    GPIO_H1_EC_VOL_DOWN_ODL
-#define GPIO_WP_L             GPIO_EC_WP_L
+#define GPIO_VOLUME_UP_L GPIO_H1_EC_VOL_UP_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_H1_EC_VOL_DOWN_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
 
 #define PORT_TO_HPD(port) ((port) ? GPIO_USB_C1_DP_HPD : GPIO_USB_C0_DP_HPD)
 
@@ -225,19 +224,15 @@
 #include "registers.h"
 
 /* ADC signal */
-enum adc_channel {
-	ADC_BASE_ATTACH,
-	ADC_BASE_DETACH,
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_BASE_ATTACH, ADC_BASE_DETACH, ADC_CH_COUNT };
 
 enum temp_sensor_id {
-	TEMP_SENSOR_BATTERY,	/* BD99956GW TSENSE */
-	TEMP_SENSOR_AMBIENT,	/* BD99992GW SYSTHERM0 */
-	TEMP_SENSOR_CHARGER,	/* BD99992GW SYSTHERM1 */
-	TEMP_SENSOR_DRAM,	/* BD99992GW SYSTHERM2 */
-	TEMP_SENSOR_EMMC,	/* BD99992GW SYSTHERM3 */
-	TEMP_SENSOR_GYRO,	/* BMI160 */
+	TEMP_SENSOR_BATTERY, /* BD99956GW TSENSE */
+	TEMP_SENSOR_AMBIENT, /* BD99992GW SYSTHERM0 */
+	TEMP_SENSOR_CHARGER, /* BD99992GW SYSTHERM1 */
+	TEMP_SENSOR_DRAM, /* BD99992GW SYSTHERM2 */
+	TEMP_SENSOR_EMMC, /* BD99992GW SYSTHERM3 */
+	TEMP_SENSOR_GYRO, /* BMI160 */
 	TEMP_SENSOR_COUNT
 };
 
diff --git a/board/nocturne/build.mk b/board/nocturne/build.mk
index 1c2e1e04f2..3a43716534 100644
--- a/board/nocturne/build.mk
+++ b/board/nocturne/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/nocturne/ec.tasklist b/board/nocturne/ec.tasklist
index 4fb7a035a9..5c7988f1d6 100644
--- a/board/nocturne/ec.tasklist
+++ b/board/nocturne/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nocturne/gpio.inc b/board/nocturne/gpio.inc
index 75d2275424..e820bca8f0 100644
--- a/board/nocturne/gpio.inc
+++ b/board/nocturne/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nocturne/led.c b/board/nocturne/led.c
index b214a8df84..ba3320cd22 100644
--- a/board/nocturne/led.c
+++ b/board/nocturne/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,35 +19,35 @@ const enum ec_led_id supported_led_ids[] = {
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 struct pwm_led_color_map led_color_map_v3[EC_LED_COLOR_COUNT] = {
-				/* Red, Green, Blue */
-	[EC_LED_COLOR_RED]    = {  36,   0,   0 },
-	[EC_LED_COLOR_GREEN]  = {   0,  15,   0 },
-	[EC_LED_COLOR_BLUE]   = {   0,   0, 100 },
-	[EC_LED_COLOR_YELLOW] = {  36,  15,   0 },
-	[EC_LED_COLOR_WHITE]  = {  30,   9,  15 },
-	[EC_LED_COLOR_AMBER]  = {  30,   1,   0 },
+	/* Red, Green, Blue */
+	[EC_LED_COLOR_RED] = { 36, 0, 0 },
+	[EC_LED_COLOR_GREEN] = { 0, 15, 0 },
+	[EC_LED_COLOR_BLUE] = { 0, 0, 100 },
+	[EC_LED_COLOR_YELLOW] = { 36, 15, 0 },
+	[EC_LED_COLOR_WHITE] = { 30, 9, 15 },
+	[EC_LED_COLOR_AMBER] = { 30, 1, 0 },
 };
 
 /* Map for board rev 2 */
 struct pwm_led_color_map led_color_map_v2[EC_LED_COLOR_COUNT] = {
-				/* Red, Green, Blue */
-	[EC_LED_COLOR_RED]    = {  62,   0,   0 },
-	[EC_LED_COLOR_GREEN]  = {   0,  31,   0 },
-	[EC_LED_COLOR_BLUE]   = {   0,   0, 100 },
-	[EC_LED_COLOR_YELLOW] = { 100,  54,   0 },
-	[EC_LED_COLOR_WHITE]  = {  70,  54, 100 },
-	[EC_LED_COLOR_AMBER]  = { 100,  15,   0 },
+	/* Red, Green, Blue */
+	[EC_LED_COLOR_RED] = { 62, 0, 0 },
+	[EC_LED_COLOR_GREEN] = { 0, 31, 0 },
+	[EC_LED_COLOR_BLUE] = { 0, 0, 100 },
+	[EC_LED_COLOR_YELLOW] = { 100, 54, 0 },
+	[EC_LED_COLOR_WHITE] = { 70, 54, 100 },
+	[EC_LED_COLOR_AMBER] = { 100, 15, 0 },
 };
 
 /* Map for board rev 0 and 1 */
 struct pwm_led_color_map led_color_map_v0_1[EC_LED_COLOR_COUNT] = {
-				/* Red, Green, Blue */
-	[EC_LED_COLOR_RED]    = {   1,   0,   0 },
-	[EC_LED_COLOR_GREEN]  = {   0,   1,   0 },
-	[EC_LED_COLOR_BLUE]   = {   0,   0,   1 },
-	[EC_LED_COLOR_YELLOW] = {   1,   1,   0 },
-	[EC_LED_COLOR_WHITE]  = {   9,  15,  15 },
-	[EC_LED_COLOR_AMBER]  = {  15,   1,   0 },
+	/* Red, Green, Blue */
+	[EC_LED_COLOR_RED] = { 1, 0, 0 },
+	[EC_LED_COLOR_GREEN] = { 0, 1, 0 },
+	[EC_LED_COLOR_BLUE] = { 0, 0, 1 },
+	[EC_LED_COLOR_YELLOW] = { 1, 1, 0 },
+	[EC_LED_COLOR_WHITE] = { 9, 15, 15 },
+	[EC_LED_COLOR_AMBER] = { 15, 1, 0 },
 };
 
 struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = { { 0 } };
@@ -135,4 +135,4 @@ static void select_color_map(void)
 		break;
 	}
 }
-DECLARE_HOOK(HOOK_INIT, select_color_map, HOOK_PRIO_INIT_PWM-1);
+DECLARE_HOOK(HOOK_INIT, select_color_map, HOOK_PRIO_INIT_PWM - 1);
diff --git a/board/nocturne/usb_pd_policy.c b/board/nocturne/usb_pd_policy.c
index 14329b61b3..5f1e5af365 100644
--- a/board/nocturne/usb_pd_policy.c
+++ b/board/nocturne/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,8 +16,8 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
@@ -25,8 +25,7 @@ int pd_check_vconn_swap(int port)
 	return gpio_get_level(GPIO_EN_5V);
 }
 
-__override void pd_execute_data_swap(int port,
-				     enum pd_data_role data_role)
+__override void pd_execute_data_swap(int port, enum pd_data_role data_role)
 {
 	int level;
 
@@ -96,9 +95,8 @@ int pd_set_power_supply_ready(int port)
 __override void svdm_safe_dp_mode(int port)
 {
 	/* make DP interface safe until configure */
-	usb_mux_set(port, USB_PD_MUX_NONE,
-		USB_SWITCH_CONNECT,
-		polarity_rm_dts(pd_get_polarity(port)));
+	usb_mux_set(port, USB_PD_MUX_NONE, USB_SWITCH_CONNECT,
+		    polarity_rm_dts(pd_get_polarity(port)));
 
 	/*
 	 * Isolate the SBU lines.
diff --git a/board/nocturne_fp/board.h b/board/nocturne_fp/board.h
index 704c5a0565..e7d34445b0 100644
--- a/board/nocturne_fp/board.h
+++ b/board/nocturne_fp/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -51,28 +51,28 @@
 #undef CONFIG_WP_STORAGE_OFF
 #undef CONFIG_WP_STORAGE_SIZE
 
-#define CONFIG_SHAREDLIB_SIZE   0
+#define CONFIG_SHAREDLIB_SIZE 0
 
-#define CONFIG_RO_MEM_OFF       0
-#define CONFIG_RO_STORAGE_OFF   0
-#define CONFIG_RO_SIZE          (768*1024)
+#define CONFIG_RO_MEM_OFF 0
+#define CONFIG_RO_STORAGE_OFF 0
+#define CONFIG_RO_SIZE (768 * 1024)
 
 /* EC rollback protection block */
 #define CONFIG_ROLLBACK_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
 #define CONFIG_ROLLBACK_SIZE (CONFIG_FLASH_BANK_SIZE * 2)
 
-#define CONFIG_RW_MEM_OFF	(CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE)
-#define CONFIG_RW_STORAGE_OFF	0
-#define CONFIG_RW_SIZE		(CONFIG_FLASH_SIZE_BYTES -		\
-				(CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF))
+#define CONFIG_RW_MEM_OFF (CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE)
+#define CONFIG_RW_STORAGE_OFF 0
+#define CONFIG_RW_SIZE \
+	(CONFIG_FLASH_SIZE_BYTES - (CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF))
 
-#define CONFIG_EC_PROTECTED_STORAGE_OFF         CONFIG_RO_MEM_OFF
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE        CONFIG_RO_SIZE
-#define CONFIG_EC_WRITABLE_STORAGE_OFF          CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE         CONFIG_RW_SIZE
+#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF
+#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE
+#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE
 
-#define CONFIG_WP_STORAGE_OFF           CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE          CONFIG_EC_PROTECTED_STORAGE_SIZE
+#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
+#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
 
 /*
  * We want to prevent flash readout, and use it as indicator of protection
@@ -106,7 +106,7 @@
 #undef CONFIG_LID_SWITCH
 #define CONFIG_MKBP_EVENT
 #define CONFIG_MKBP_USE_GPIO
-#define CONFIG_PRINTF_LEGACY_LI_FORMAT
+#define CONFIG_PRINTF_LONG_IS_32BITS
 #define CONFIG_SHA256
 #define CONFIG_SHA256_UNROLLED
 #define CONFIG_SPI
@@ -155,7 +155,7 @@
 
 /* SPI configuration for the fingerprint sensor */
 #define CONFIG_SPI_CONTROLLER
-#define CONFIG_SPI_FP_PORT  2 /* SPI4: third master config */
+#define CONFIG_SPI_FP_PORT 2 /* SPI4: third master config */
 
 #define CONFIG_FINGERPRINT_MCU
 #ifdef SECTION_IS_RW
@@ -168,7 +168,7 @@
  */
 #define CONFIG_MALLOC
 /* Special memory regions to store large arrays */
-#define FP_FRAME_SECTION    __SECTION(ahb4)
+#define FP_FRAME_SECTION __SECTION(ahb4)
 #define FP_TEMPLATE_SECTION __SECTION(ahb)
 
 #else /* SECTION_IS_RO */
diff --git a/board/nocturne_fp/board_ro.c b/board/nocturne_fp/board_ro.c
index 7f20002435..f215cd91cf 100644
--- a/board/nocturne_fp/board_ro.c
+++ b/board/nocturne_fp/board_ro.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,7 +15,6 @@
 #error "This file should only be built for RO."
 #endif
 
-
 /**
  * Disable restricted commands when the system is locked.
  *
diff --git a/board/nocturne_fp/board_rw.c b/board/nocturne_fp/board_rw.c
index abc6bf88d8..fd5899c799 100644
--- a/board/nocturne_fp/board_rw.c
+++ b/board/nocturne_fp/board_rw.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nocturne_fp/board_rw.h b/board/nocturne_fp/board_rw.h
index 6ef7cc29b4..1687da3737 100644
--- a/board/nocturne_fp/board_rw.h
+++ b/board/nocturne_fp/board_rw.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nocturne_fp/build.mk b/board/nocturne_fp/build.mk
index cc985141d1..55f6f95b4b 100644
--- a/board/nocturne_fp/build.mk
+++ b/board/nocturne_fp/build.mk
@@ -1,4 +1,4 @@
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -31,6 +31,7 @@ test-list-y=\
        compile_time_macros \
        cortexm_fpu \
        crc \
+       debug \
        flash_physical \
        flash_write_protect \
        fpsensor \
@@ -49,6 +50,7 @@ test-list-y=\
        sha256 \
        sha256_unrolled \
        static_if \
+       stdlib \
        system_is_locked \
        timer_dos \
        utils \
diff --git a/board/nocturne_fp/ec.tasklist b/board/nocturne_fp/ec.tasklist
index ed1e6ed294..2a4771fa98 100644
--- a/board/nocturne_fp/ec.tasklist
+++ b/board/nocturne_fp/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nocturne_fp/fpsensor_detect.c b/board/nocturne_fp/fpsensor_detect.c
index 5a4b95e64c..2541aa3c68 100644
--- a/board/nocturne_fp/fpsensor_detect.c
+++ b/board/nocturne_fp/fpsensor_detect.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nocturne_fp/fpsensor_detect_rw.c b/board/nocturne_fp/fpsensor_detect_rw.c
index e4a670e211..d26927c187 100644
--- a/board/nocturne_fp/fpsensor_detect_rw.c
+++ b/board/nocturne_fp/fpsensor_detect_rw.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nocturne_fp/gpio.inc b/board/nocturne_fp/gpio.inc
index dc15ab0ef0..b0e1c3a80b 100644
--- a/board/nocturne_fp/gpio.inc
+++ b/board/nocturne_fp/gpio.inc
@@ -1,5 +1,5 @@
 /*
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nocturne_fp/gpio_rw.inc b/board/nocturne_fp/gpio_rw.inc
index 2de4c3e92a..9ee3af139f 100644
--- a/board/nocturne_fp/gpio_rw.inc
+++ b/board/nocturne_fp/gpio_rw.inc
@@ -1,5 +1,5 @@
 /*
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nocturne_fp/ro_workarounds.c b/board/nocturne_fp/ro_workarounds.c
index e6417ddc08..11f025fd5b 100644
--- a/board/nocturne_fp/ro_workarounds.c
+++ b/board/nocturne_fp/ro_workarounds.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,7 +19,7 @@
 #include "watchdog.h"
 
 /* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 /*
  * We only patch RW to ensure that future ROs have correct behavior.
@@ -30,7 +30,7 @@
  * Add in ap-off flag to be able to detect on next boot.
  * No other code in this build uses this ap-off reset flag.
  */
-#define FORGE_PORFLAG_FLAGS (EC_RESET_FLAG_POWER_ON|EC_RESET_FLAG_AP_OFF)
+#define FORGE_PORFLAG_FLAGS (EC_RESET_FLAG_POWER_ON | EC_RESET_FLAG_AP_OFF)
 
 static void wp_change_deferred(void)
 {
@@ -75,8 +75,7 @@ void wp_event(enum gpio_signal signal)
  * This function is also called from system_reset to set the final save
  * reset flags, before an actual planned reset.
  */
-__override
-void bkpdata_write_reset_flags(uint32_t save_flags)
+__override void bkpdata_write_reset_flags(uint32_t save_flags)
 {
 	/* Preserve flags in case a reset pulse occurs */
 	if (!gpio_get_level(GPIO_WP))
diff --git a/board/npcx7_evb/board.c b/board/npcx7_evb/board.c
index 7909668d2c..c78a30f3de 100644
--- a/board/npcx7_evb/board.c
+++ b/board/npcx7_evb/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -36,18 +36,23 @@
 /******************************************************************************/
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
-	[ADC_CH_0] = {"ADC0", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_1] = {"ADC1", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_2] = {"ADC2", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_3] = {"ADC3", NPCX_ADC_CH3, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_4] = {"ADC4", NPCX_ADC_CH4, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_CH_0] = { "ADC0", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+		       0 },
+	[ADC_CH_1] = { "ADC1", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+		       0 },
+	[ADC_CH_2] = { "ADC2", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+		       0 },
+	[ADC_CH_3] = { "ADC3", NPCX_ADC_CH3, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+		       0 },
+	[ADC_CH_4] = { "ADC4", NPCX_ADC_CH4, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+		       0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /******************************************************************************/
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN] = { 0, PWM_CONFIG_OPEN_DRAIN, 25000},
+	[PWM_CH_FAN] = { 0, PWM_CONFIG_OPEN_DRAIN, 25000 },
 	[PWM_CH_KBLIGHT] = { 2, 0, 10000 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
@@ -56,7 +61,7 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 /* Physical fans. These are logically separate from pwm_channels. */
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = 0,	/* Use MFT id to control fan */
+	.ch = 0, /* Use MFT id to control fan */
 	.pgood_gpio = GPIO_PGOOD_FAN,
 	.enable_gpio = -1,
 };
@@ -75,55 +80,45 @@ BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
 /******************************************************************************/
 /* MFT channels. These are logically separate from pwm_channels. */
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN },
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 /******************************************************************************/
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "master0-0",
-		.port = NPCX_I2C_PORT0_0,
-		.kbps = 100,
-		.scl  = GPIO_I2C0_SCL0,
-		.sda  = GPIO_I2C0_SDA0
-	},
-	{
-		.name = "master1-0",
-		.port = NPCX_I2C_PORT1_0,
-		.kbps = 100,
-		.scl  = GPIO_I2C1_SCL0,
-		.sda  = GPIO_I2C1_SDA0
-	},
-	{
-		.name = "master2-0",
-		.port = NPCX_I2C_PORT2_0,
-		.kbps = 100,
-		.scl  = GPIO_I2C2_SCL0,
-		.sda  = GPIO_I2C2_SDA0
-	},
-	{
-		.name = "master3-0",
-		.port = NPCX_I2C_PORT3_0,
-		.kbps = 100,
-		.scl  = GPIO_I2C3_SCL0,
-		.sda  = GPIO_I2C3_SDA0
-	},
-	{
-		.name = "master7-0",
-		.port = NPCX_I2C_PORT7_0,
-		.kbps = 100,
-		.scl  = GPIO_I2C7_SCL0,
-		.sda  = GPIO_I2C7_SDA0
-	},
+	{ .name = "master0-0",
+	  .port = NPCX_I2C_PORT0_0,
+	  .kbps = 100,
+	  .scl = GPIO_I2C0_SCL0,
+	  .sda = GPIO_I2C0_SDA0 },
+	{ .name = "master1-0",
+	  .port = NPCX_I2C_PORT1_0,
+	  .kbps = 100,
+	  .scl = GPIO_I2C1_SCL0,
+	  .sda = GPIO_I2C1_SDA0 },
+	{ .name = "master2-0",
+	  .port = NPCX_I2C_PORT2_0,
+	  .kbps = 100,
+	  .scl = GPIO_I2C2_SCL0,
+	  .sda = GPIO_I2C2_SDA0 },
+	{ .name = "master3-0",
+	  .port = NPCX_I2C_PORT3_0,
+	  .kbps = 100,
+	  .scl = GPIO_I2C3_SCL0,
+	  .sda = GPIO_I2C3_SDA0 },
+	{ .name = "master7-0",
+	  .port = NPCX_I2C_PORT7_0,
+	  .kbps = 100,
+	  .scl = GPIO_I2C7_SCL0,
+	  .sda = GPIO_I2C7_SDA0 },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
 /******************************************************************************/
 /* SPI devices */
 const struct spi_device_t spi_devices[] = {
-	{ CONFIG_SPI_FLASH_PORT, 0, GPIO_SPI_CS_L},
+	{ CONFIG_SPI_FLASH_PORT, 0, GPIO_SPI_CS_L },
 };
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
diff --git a/board/npcx7_evb/board.h b/board/npcx7_evb/board.h
index ab8b850d94..8a7b0246e9 100644
--- a/board/npcx7_evb/board.h
+++ b/board/npcx7_evb/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,11 +15,11 @@
  *     npcx7m6f/npcx7m6fb/npcx7m6fc/npcx7m7fc/npcx7m7wb/npcx7m7wc
  */
 #if defined(CHIP_VARIANT_NPCX7M6G)
-#define BOARD_VERSION  1
-#elif defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \
+#define BOARD_VERSION 1
+#elif defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) ||    \
 	defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M7FC) || \
 	defined(CHIP_VARIANT_NPCX7M7WB) || defined(CHIP_VARIANT_NPCX7M7WC)
-#define BOARD_VERSION  2
+#define BOARD_VERSION 2
 #endif
 
 /* EC modules */
@@ -29,8 +29,8 @@
 #define CONFIG_I2C
 /* Features of eSPI */
 #define CONFIG_HOST_INTERFACE_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 
 /* Optional features */
 #define CONFIG_ENABLE_JTAG_SELECTION
@@ -39,9 +39,9 @@
 #define CONFIG_I2C_CONTROLLER
 
 #define CONFIG_KEYBOARD_PROTOCOL_8042
-#undef  CONFIG_LOW_POWER_IDLE /* Deep Sleep Support */
+#undef CONFIG_LOW_POWER_IDLE /* Deep Sleep Support */
 #define CONFIG_POWER_BUTTON
-#undef  CONFIG_PSTORE
+#undef CONFIG_PSTORE
 #define CONFIG_PWM_KBLIGHT
 #define CONFIG_VBOOT_HASH
 #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands */
@@ -57,7 +57,7 @@
 
 /* I2C port for CONFIG_CMD_I2CWEDGE */
 #define I2C_PORT_MASTER NPCX_I2C_PORT0_0
-#define I2C_PORT_HOST   0
+#define I2C_PORT_HOST 0
 
 /* Fans for testing */
 #define CONFIG_FANS 1
@@ -95,20 +95,20 @@
 
 /* Select which UART Controller is the Console UART */
 #undef CONFIG_CONSOLE_UART
-#define CONFIG_CONSOLE_UART    0 /* 0:UART1 1:UART2 */
+#define CONFIG_CONSOLE_UART 0 /* 0:UART1 1:UART2 */
 /*
  * This definition below actually doesn't define which UART controller to be
  * used. Instead, it defines which pinouts (GPIO10/11 or GPIO64/65) are
  * connected to "UART1" controller.
  */
 #if (BOARD_VERSION == 2)
-#define NPCX_UART_MODULE2  1 /* 1:GPIO64/65 as UART1 */
+#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART1 */
 #else
-#define NPCX_UART_MODULE2  0 /* 0:GPIO10/11 as UART1 */
+#define NPCX_UART_MODULE2 0 /* 0:GPIO10/11 as UART1 */
 #endif
-#define NPCX_JTAG_MODULE2  0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG */
-#define NPCX_TACH_SEL2     0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
-#define NPCX7_PWM1_SEL     0 /* 0:GPIOC2 as I2CSCL0 1:as PWM1 (only in npcx7) */
+#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG */
+#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
+#define NPCX7_PWM1_SEL 0 /* 0:GPIOC2 as I2CSCL0 1:as PWM1 (only in npcx7) */
 
 #ifndef __ASSEMBLER__
 
diff --git a/board/npcx7_evb/build.mk b/board/npcx7_evb/build.mk
index 4bd829202c..e51c3bdc5c 100644
--- a/board/npcx7_evb/build.mk
+++ b/board/npcx7_evb/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/npcx7_evb/ec.tasklist b/board/npcx7_evb/ec.tasklist
index 88b5ffaa62..24e3b42d7c 100644
--- a/board/npcx7_evb/ec.tasklist
+++ b/board/npcx7_evb/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/npcx7_evb/gpio.inc b/board/npcx7_evb/gpio.inc
index 145a48de85..b8cfa1d8d5 100644
--- a/board/npcx7_evb/gpio.inc
+++ b/board/npcx7_evb/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/npcx9_evb/board.c b/board/npcx9_evb/board.c
index b412fe8b30..d0c90ee9b1 100644
--- a/board/npcx9_evb/board.c
+++ b/board/npcx9_evb/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -36,25 +36,37 @@
 /******************************************************************************/
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
-	[ADC_CH_0] = {"ADC0", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_1] = {"ADC1", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_2] = {"ADC2", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_3] = {"ADC3", NPCX_ADC_CH3, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_4] = {"ADC4", NPCX_ADC_CH4, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_5] = {"ADC5", NPCX_ADC_CH5, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_6] = {"ADC6", NPCX_ADC_CH6, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_7] = {"ADC7", NPCX_ADC_CH7, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_8] = {"ADC8", NPCX_ADC_CH8, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_9] = {"ADC9", NPCX_ADC_CH9, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_10] = {"ADC10", NPCX_ADC_CH10, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_11] = {"ADC11", NPCX_ADC_CH11, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_CH_0] = { "ADC0", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+		       0 },
+	[ADC_CH_1] = { "ADC1", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+		       0 },
+	[ADC_CH_2] = { "ADC2", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+		       0 },
+	[ADC_CH_3] = { "ADC3", NPCX_ADC_CH3, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+		       0 },
+	[ADC_CH_4] = { "ADC4", NPCX_ADC_CH4, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+		       0 },
+	[ADC_CH_5] = { "ADC5", NPCX_ADC_CH5, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+		       0 },
+	[ADC_CH_6] = { "ADC6", NPCX_ADC_CH6, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+		       0 },
+	[ADC_CH_7] = { "ADC7", NPCX_ADC_CH7, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+		       0 },
+	[ADC_CH_8] = { "ADC8", NPCX_ADC_CH8, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+		       0 },
+	[ADC_CH_9] = { "ADC9", NPCX_ADC_CH9, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+		       0 },
+	[ADC_CH_10] = { "ADC10", NPCX_ADC_CH10, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+			0 },
+	[ADC_CH_11] = { "ADC11", NPCX_ADC_CH11, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+			0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /******************************************************************************/
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN] = { 0, PWM_CONFIG_OPEN_DRAIN, 25000},
+	[PWM_CH_FAN] = { 0, PWM_CONFIG_OPEN_DRAIN, 25000 },
 	[PWM_CH_KBLIGHT] = { 2, 0, 10000 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
@@ -63,7 +75,7 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 /* Physical fans. These are logically separate from pwm_channels. */
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = 0,	/* Use MFT id to control fan */
+	.ch = 0, /* Use MFT id to control fan */
 	.pgood_gpio = GPIO_PGOOD_FAN,
 	.enable_gpio = -1,
 };
@@ -96,48 +108,38 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 /******************************************************************************/
 /* MFT channels. These are logically separate from pwm_channels. */
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN },
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 /******************************************************************************/
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "master0-0",
-		.port = NPCX_I2C_PORT0_0,
-		.kbps = 100,
-		.scl  = GPIO_I2C0_SCL0,
-		.sda  = GPIO_I2C0_SDA0
-	},
-	{
-		.name = "master1-0",
-		.port = NPCX_I2C_PORT1_0,
-		.kbps = 100,
-		.scl  = GPIO_I2C1_SCL0,
-		.sda  = GPIO_I2C1_SDA0
-	},
-	{
-		.name = "master2-0",
-		.port = NPCX_I2C_PORT2_0,
-		.kbps = 100,
-		.scl  = GPIO_I2C2_SCL0,
-		.sda  = GPIO_I2C2_SDA0
-	},
-	{
-		.name = "master3-0",
-		.port = NPCX_I2C_PORT3_0,
-		.kbps = 100,
-		.scl  = GPIO_I2C3_SCL0,
-		.sda  = GPIO_I2C3_SDA0
-	},
-	{
-		.name = "master7-0",
-		.port = NPCX_I2C_PORT7_0,
-		.kbps = 100,
-		.scl  = GPIO_I2C7_SCL0,
-		.sda  = GPIO_I2C7_SDA0
-	},
+	{ .name = "master0-0",
+	  .port = NPCX_I2C_PORT0_0,
+	  .kbps = 100,
+	  .scl = GPIO_I2C0_SCL0,
+	  .sda = GPIO_I2C0_SDA0 },
+	{ .name = "master1-0",
+	  .port = NPCX_I2C_PORT1_0,
+	  .kbps = 100,
+	  .scl = GPIO_I2C1_SCL0,
+	  .sda = GPIO_I2C1_SDA0 },
+	{ .name = "master2-0",
+	  .port = NPCX_I2C_PORT2_0,
+	  .kbps = 100,
+	  .scl = GPIO_I2C2_SCL0,
+	  .sda = GPIO_I2C2_SDA0 },
+	{ .name = "master3-0",
+	  .port = NPCX_I2C_PORT3_0,
+	  .kbps = 100,
+	  .scl = GPIO_I2C3_SCL0,
+	  .sda = GPIO_I2C3_SDA0 },
+	{ .name = "master7-0",
+	  .port = NPCX_I2C_PORT7_0,
+	  .kbps = 100,
+	  .scl = GPIO_I2C7_SCL0,
+	  .sda = GPIO_I2C7_SDA0 },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
diff --git a/board/npcx9_evb/board.h b/board/npcx9_evb/board.h
index a0d209c938..681e36157a 100644
--- a/board/npcx9_evb/board.h
+++ b/board/npcx9_evb/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,8 +14,8 @@
 #define CONFIG_I2C
 /* Features of eSPI */
 #define CONFIG_HOST_INTERFACE_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 
 /* Optional features */
 #define CONFIG_ENABLE_JTAG_SELECTION
@@ -25,9 +25,9 @@
 #define CONFIG_I2C_CONTROLLER
 
 #define CONFIG_KEYBOARD_PROTOCOL_8042
-#undef  CONFIG_LOW_POWER_IDLE /* Deep Sleep Support */
+#undef CONFIG_LOW_POWER_IDLE /* Deep Sleep Support */
 #define CONFIG_POWER_BUTTON
-#undef  CONFIG_PSTORE
+#undef CONFIG_PSTORE
 #define CONFIG_PWM_KBLIGHT
 #define CONFIG_VBOOT_HASH
 #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands */
@@ -43,14 +43,14 @@
 
 /* I2C port for CONFIG_CMD_I2CWEDGE */
 #define I2C_PORT_MASTER NPCX_I2C_PORT0_0
-#define I2C_PORT_HOST   0
+#define I2C_PORT_HOST 0
 
 /* Fans for testing */
 #define CONFIG_FANS 1
 
 #define CONFIG_TEMP_SENSOR
 #define CONFIG_TEMP_SENSOR_TMP112
-#define I2C_PORT_THERMAL	NPCX_I2C_PORT2_0
+#define I2C_PORT_THERMAL NPCX_I2C_PORT2_0
 
 #define CONFIG_KEYBOARD_KSO_HIGH_DRIVE /* Quasi-bidirectional buf for KSOs */
 #define CONFIG_HIBERNATE_PSL /* Use PSL (Power Switch Logic) for hibernate */
@@ -60,15 +60,15 @@
 
 /* Select which UART Controller is the Console UART */
 #undef CONFIG_CONSOLE_UART
-#define CONFIG_CONSOLE_UART    0 /* 0:UART1 1:UART2 */
+#define CONFIG_CONSOLE_UART 0 /* 0:UART1 1:UART2 */
 /*
  * This definition below actually doesn't define which UART controller to be
  * used. Instead, it defines which pinouts (GPIO10/11 or GPIO64/65) are
  * connected to "UART1" controller.
  */
-#define NPCX_UART_MODULE2  1 /* 1:GPIO64/65 as UART1 */
-#define NPCX_TACH_SEL2     0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
-#define NPCX9_PWM1_SEL     0 /* 0:GPIOC2 as I2CSCL0 1:as PWM1 */
+#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART1 */
+#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
+#define NPCX9_PWM1_SEL 0 /* 0:GPIOC2 as I2CSCL0 1:as PWM1 */
 
 #ifndef __ASSEMBLER__
 
@@ -94,7 +94,7 @@ enum tmp112_sensor {
 };
 
 enum temp_sensor_id {
-	TEMP_SENSOR_SYSTHERM0,	/* TMP100 */
+	TEMP_SENSOR_SYSTHERM0, /* TMP100 */
 	TEMP_SENSOR_COUNT
 };
 
diff --git a/board/npcx9_evb/build.mk b/board/npcx9_evb/build.mk
index 92bcc84144..d2526afb1b 100644
--- a/board/npcx9_evb/build.mk
+++ b/board/npcx9_evb/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/npcx9_evb/ec.tasklist b/board/npcx9_evb/ec.tasklist
index 9560b43561..d41f0ade2f 100644
--- a/board/npcx9_evb/ec.tasklist
+++ b/board/npcx9_evb/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/npcx9_evb/gpio.inc b/board/npcx9_evb/gpio.inc
index ec57c1afc5..28dbbba93a 100644
--- a/board/npcx9_evb/gpio.inc
+++ b/board/npcx9_evb/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/npcx_evb/board.c b/board/npcx_evb/board.c
index ee448bbbd2..06ab55f94a 100644
--- a/board/npcx_evb/board.c
+++ b/board/npcx_evb/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -35,16 +35,19 @@
 /******************************************************************************/
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
-	[ADC_CH_0] = {"ADC0", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_1] = {"ADC1", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_2] = {"ADC2", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_CH_0] = { "ADC0", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+		       0 },
+	[ADC_CH_1] = { "ADC1", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+		       0 },
+	[ADC_CH_2] = { "ADC2", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+		       0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /******************************************************************************/
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN] = { 0, PWM_CONFIG_OPEN_DRAIN, 25000},
+	[PWM_CH_FAN] = { 0, PWM_CONFIG_OPEN_DRAIN, 25000 },
 #if (CONFIG_FANS == 2)
 	[PWM_CH_FAN2] = { 2, 0, 25000 },
 #endif
@@ -56,14 +59,14 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 /* Physical fans. These are logically separate from pwm_channels. */
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = 0,	/* Use MFT id to control fan */
+	.ch = 0, /* Use MFT id to control fan */
 	.pgood_gpio = GPIO_PGOOD_FAN,
 	.enable_gpio = -1,
 };
 
 const struct fan_conf fan_conf_1 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = 1,	/* Use MFT id to control fan */
+	.ch = 1, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = -1,
 };
@@ -91,9 +94,9 @@ BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
 /******************************************************************************/
 /* MFT channels. These are logically separate from pwm_channels. */
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN },
 #if (CONFIG_FANS == 2)
-	[MFT_CH_1] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN2},
+	[MFT_CH_1] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN2 },
 #endif
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
@@ -101,48 +104,38 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 /******************************************************************************/
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "master0-0",
-		.port = NPCX_I2C_PORT0_0,
-		.kbps = 100,
-		.scl  = GPIO_I2C0_SCL0,
-		.sda  = GPIO_I2C0_SDA0
-	},
-	{
-		.name = "master0-1",
-		.port = NPCX_I2C_PORT0_1,
-		.kbps = 100,
-		.scl  = GPIO_I2C0_SCL1,
-		.sda  = GPIO_I2C0_SDA1
-	},
-	{
-		.name = "master1",
-		.port = NPCX_I2C_PORT1,
-		.kbps = 100,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	},
-	{
-		.name = "master2",
-		.port = NPCX_I2C_PORT2,
-		.kbps = 100,
-		.scl  = GPIO_I2C2_SCL,
-		.sda  = GPIO_I2C2_SDA
-	},
-	{
-		.name = "master3",
-		.port = NPCX_I2C_PORT3,
-		.kbps = 100,
-		.scl  = GPIO_I2C3_SCL,
-		.sda  = GPIO_I2C3_SDA
-	},
+	{ .name = "master0-0",
+	  .port = NPCX_I2C_PORT0_0,
+	  .kbps = 100,
+	  .scl = GPIO_I2C0_SCL0,
+	  .sda = GPIO_I2C0_SDA0 },
+	{ .name = "master0-1",
+	  .port = NPCX_I2C_PORT0_1,
+	  .kbps = 100,
+	  .scl = GPIO_I2C0_SCL1,
+	  .sda = GPIO_I2C0_SDA1 },
+	{ .name = "master1",
+	  .port = NPCX_I2C_PORT1,
+	  .kbps = 100,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "master2",
+	  .port = NPCX_I2C_PORT2,
+	  .kbps = 100,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "master3",
+	  .port = NPCX_I2C_PORT3,
+	  .kbps = 100,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
 /******************************************************************************/
 /* SPI devices */
 const struct spi_device_t spi_devices[] = {
-	{ CONFIG_SPI_FLASH_PORT, 0, GPIO_SPI_CS_L},
+	{ CONFIG_SPI_FLASH_PORT, 0, GPIO_SPI_CS_L },
 };
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
diff --git a/board/npcx_evb/board.h b/board/npcx_evb/board.h
index 5a22435396..82675ee9d8 100644
--- a/board/npcx_evb/board.h
+++ b/board/npcx_evb/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,7 +19,7 @@
 #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands for testing */
 #define CONFIG_SPI_FLASH_PORT 0
 #define CONFIG_SPI_FLASH
-#define CONFIG_FLASH_SIZE_BYTES          0x00800000 /* 8MB spi flash */
+#define CONFIG_FLASH_SIZE_BYTES 0x00800000 /* 8MB spi flash */
 #define CONFIG_SPI_FLASH_REGS
 #define CONFIG_SPI_FLASH_W25Q64
 #define CONFIG_I2C
@@ -41,29 +41,24 @@
 #define CONFIG_CMD_SCRATCHPAD
 #define CONFIG_CMD_I2CWEDGE
 
-#define CONFIG_FANS                     1
+#define CONFIG_FANS 1
 
 /* Optional feature - used by nuvoton */
-#define NPCX_UART_MODULE2    0 /* 0:GPIO10/11 1:GPIO64/65 as UART */
-#define NPCX_JTAG_MODULE2    0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/
-#define NPCX_TACH_SEL2       0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
+#define NPCX_UART_MODULE2 0 /* 0:GPIO10/11 1:GPIO64/65 as UART */
+#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/
+#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
 
 /* Optional for testing */
-#undef  CONFIG_PSTORE
-#undef  CONFIG_LOW_POWER_IDLE           /* Deep Sleep Support */
+#undef CONFIG_PSTORE
+#undef CONFIG_LOW_POWER_IDLE /* Deep Sleep Support */
 
 /* Single I2C port, where the EC is the master. */
-#define I2C_PORT_MASTER         NPCX_I2C_PORT0_0
-#define I2C_PORT_HOST           0
+#define I2C_PORT_MASTER NPCX_I2C_PORT0_0
+#define I2C_PORT_HOST 0
 
 #ifndef __ASSEMBLER__
 
-enum adc_channel {
-	ADC_CH_0 = 0,
-	ADC_CH_1,
-	ADC_CH_2,
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_CH_0 = 0, ADC_CH_1, ADC_CH_2, ADC_CH_COUNT };
 
 enum pwm_channel {
 	PWM_CH_FAN,
diff --git a/board/npcx_evb/build.mk b/board/npcx_evb/build.mk
index 7dfc4544f2..c86457489f 100644
--- a/board/npcx_evb/build.mk
+++ b/board/npcx_evb/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
+# Copyright 2014 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/npcx_evb/ec.tasklist b/board/npcx_evb/ec.tasklist
index b0d584174e..82d4d031a2 100644
--- a/board/npcx_evb/ec.tasklist
+++ b/board/npcx_evb/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/npcx_evb/gpio.inc b/board/npcx_evb/gpio.inc
index c4e673fd25..584cbfd9b2 100644
--- a/board/npcx_evb/gpio.inc
+++ b/board/npcx_evb/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
+ * Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/npcx_evb_arm/board.c b/board/npcx_evb_arm/board.c
index abb6e2279b..209bf047e2 100644
--- a/board/npcx_evb_arm/board.c
+++ b/board/npcx_evb_arm/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -35,16 +35,19 @@
 /******************************************************************************/
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
-	[ADC_CH_0] = {"ADC0", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_1] = {"ADC1", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_CH_2] = {"ADC2", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_CH_0] = { "ADC0", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+		       0 },
+	[ADC_CH_1] = { "ADC1", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+		       0 },
+	[ADC_CH_2] = { "ADC2", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX + 1,
+		       0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /******************************************************************************/
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN] = { 0, PWM_CONFIG_OPEN_DRAIN, 25000},
+	[PWM_CH_FAN] = { 0, PWM_CONFIG_OPEN_DRAIN, 25000 },
 	[PWM_CH_KBLIGHT] = { 1, 0, 10000 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
@@ -53,7 +56,7 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 /* Physical fans. These are logically separate from pwm_channels. */
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = 0,	/* Use MFT id to control fan */
+	.ch = 0, /* Use MFT id to control fan */
 	.pgood_gpio = GPIO_PGOOD_FAN,
 	.enable_gpio = -1,
 };
@@ -72,48 +75,38 @@ BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
 /******************************************************************************/
 /* MFT channels. These are logically separate from pwm_channels. */
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN },
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 /******************************************************************************/
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "master0-0",
-		.port = NPCX_I2C_PORT0_0,
-		.kbps = 100,
-		.scl  = GPIO_I2C0_SCL0,
-		.sda  = GPIO_I2C0_SDA0
-	},
-	{
-		.name = "master0-1",
-		.port = NPCX_I2C_PORT0_1,
-		.kbps = 100,
-		.scl  = GPIO_I2C0_SCL1,
-		.sda  = GPIO_I2C0_SDA1
-	},
-	{
-		.name = "master1",
-		.port = NPCX_I2C_PORT1,
-		.kbps = 100,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	},
-	{
-		.name = "master2",
-		.port = NPCX_I2C_PORT2,
-		.kbps = 100,
-		.scl  = GPIO_I2C2_SCL,
-		.sda  = GPIO_I2C2_SDA
-	},
-	{
-		.name = "master3",
-		.port = NPCX_I2C_PORT3,
-		.kbps = 100,
-		.scl  = GPIO_I2C3_SCL,
-		.sda  = GPIO_I2C3_SDA
-	},
+	{ .name = "master0-0",
+	  .port = NPCX_I2C_PORT0_0,
+	  .kbps = 100,
+	  .scl = GPIO_I2C0_SCL0,
+	  .sda = GPIO_I2C0_SDA0 },
+	{ .name = "master0-1",
+	  .port = NPCX_I2C_PORT0_1,
+	  .kbps = 100,
+	  .scl = GPIO_I2C0_SCL1,
+	  .sda = GPIO_I2C0_SDA1 },
+	{ .name = "master1",
+	  .port = NPCX_I2C_PORT1,
+	  .kbps = 100,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "master2",
+	  .port = NPCX_I2C_PORT2,
+	  .kbps = 100,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "master3",
+	  .port = NPCX_I2C_PORT3,
+	  .kbps = 100,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
diff --git a/board/npcx_evb_arm/board.h b/board/npcx_evb_arm/board.h
index a56cec9783..f342d5c37f 100644
--- a/board/npcx_evb_arm/board.h
+++ b/board/npcx_evb_arm/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,13 +15,14 @@
 
 /* Optional features */
 #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands for testing */
-#define CONFIG_FLASH_SIZE_BYTES          0x00800000 /* 8MB spi flash */
+#define CONFIG_FLASH_SIZE_BYTES 0x00800000 /* 8MB spi flash */
 #define CONFIG_SPI_FLASH_REGS
 #define CONFIG_SPI_FLASH_W25Q64
 #define CONFIG_I2C
 #define CONFIG_I2C_CONTROLLER
 
-#define CONFIG_KEYBOARD_PROTOCOL_MKBP /* Instead of 8042 protocol of keyboard */
+#define CONFIG_KEYBOARD_PROTOCOL_MKBP /* Instead of 8042 protocol of keyboard \
+				       */
 #define CONFIG_MKBP_USE_GPIO
 #define CONFIG_POWER_BUTTON
 #define CONFIG_VBOOT_HASH
@@ -38,34 +39,29 @@
 #define CONFIG_CMD_SCRATCHPAD
 #define CONFIG_CMD_I2CWEDGE
 
-#define CONFIG_UART_HOST                0
-#define CONFIG_FANS                     1
+#define CONFIG_UART_HOST 0
+#define CONFIG_FANS 1
 
 /* Optional feature - used by nuvoton */
-#define NPCX_UART_MODULE2    0 /* 0:GPIO10/11 1:GPIO64/65 as UART */
-#define NPCX_JTAG_MODULE2    0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/
-#define NPCX_TACH_SEL2       0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
+#define NPCX_UART_MODULE2 0 /* 0:GPIO10/11 1:GPIO64/65 as UART */
+#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/
+#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
 /* Enable SHI PU on transition to S0. Disable the PU otherwise for leakage. */
 #define NPCX_SHI_CS_PU
 /* Enable bypass since shi outputs invalid data when across 256B boundary */
 #define NPCX_SHI_BYPASS_OVER_256B
 
 /* Optional for testing */
-#undef  CONFIG_PSTORE
-#undef  CONFIG_LOW_POWER_IDLE           /* Deep Sleep Support */
+#undef CONFIG_PSTORE
+#undef CONFIG_LOW_POWER_IDLE /* Deep Sleep Support */
 
 /* Single I2C port, where the EC is the master. */
-#define I2C_PORT_MASTER         NPCX_I2C_PORT0_0
-#define I2C_PORT_HOST           0
+#define I2C_PORT_MASTER NPCX_I2C_PORT0_0
+#define I2C_PORT_HOST 0
 
 #ifndef __ASSEMBLER__
 
-enum adc_channel {
-	ADC_CH_0 = 0,
-	ADC_CH_1,
-	ADC_CH_2,
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_CH_0 = 0, ADC_CH_1, ADC_CH_2, ADC_CH_COUNT };
 
 enum pwm_channel {
 	PWM_CH_FAN,
diff --git a/board/npcx_evb_arm/build.mk b/board/npcx_evb_arm/build.mk
index 48116c5454..e1a3762504 100644
--- a/board/npcx_evb_arm/build.mk
+++ b/board/npcx_evb_arm/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/npcx_evb_arm/ec.tasklist b/board/npcx_evb_arm/ec.tasklist
index a014b86350..078059e9d8 100644
--- a/board/npcx_evb_arm/ec.tasklist
+++ b/board/npcx_evb_arm/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/npcx_evb_arm/gpio.inc b/board/npcx_evb_arm/gpio.inc
index 1cdda98300..dc94a8ac7b 100644
--- a/board/npcx_evb_arm/gpio.inc
+++ b/board/npcx_evb_arm/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nucleo-dartmonkey/board.c b/board/nucleo-dartmonkey/board.c
index ea0d11eaf5..1cd6ef5dee 100644
--- a/board/nucleo-dartmonkey/board.c
+++ b/board/nucleo-dartmonkey/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -38,8 +38,8 @@ static void ap_deferred(void)
 	 * in S0:   SLP_ALT_L is 1 and SLP_L is 1.
 	 * in S5/G3, the FP MCU should not be running.
 	 */
-	int running = gpio_get_level(GPIO_SLP_ALT_L)
-			&& gpio_get_level(GPIO_SLP_L);
+	int running = gpio_get_level(GPIO_SLP_ALT_L) &&
+		      gpio_get_level(GPIO_SLP_L);
 
 	if (running) { /* S0 */
 		disable_sleep(SLEEP_MASK_AP_RUN);
@@ -92,7 +92,7 @@ static void board_init(void)
 	spi_configure();
 
 	ccprints("TRANSPORT_SEL: %s",
-		fp_transport_type_to_str(get_fp_transport_type()));
+		 fp_transport_type_to_str(get_fp_transport_type()));
 
 	/* Enable interrupt on PCH power signals */
 	gpio_enable_interrupt(GPIO_SLP_ALT_L);
diff --git a/board/nucleo-dartmonkey/board.h b/board/nucleo-dartmonkey/board.h
index 9e220db7dc..76e278b4ca 100644
--- a/board/nucleo-dartmonkey/board.h
+++ b/board/nucleo-dartmonkey/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -33,27 +33,27 @@
 
 /* SPI configuration for the fingerprint sensor */
 #define CONFIG_SPI_CONTROLLER
-#define CONFIG_SPI_FP_PORT  2 /* SPI4: third master config */
+#define CONFIG_SPI_FP_PORT 2 /* SPI4: third master config */
 
 #define CONFIG_FINGERPRINT_MCU
 
 #ifdef SECTION_IS_RW
-	/* Select fingerprint sensor */
-#	define CONFIG_FP_SENSOR_FPC1145
-#	define CONFIG_CMD_FPSENSOR_DEBUG
-	/* Special memory regions to store large arrays */
-#	define FP_FRAME_SECTION    __SECTION(ahb4)
-#	define FP_TEMPLATE_SECTION __SECTION(ahb)
-	/*
-	 * Use the malloc code only in the RW section (for the private library),
-	 * we cannot enable it in RO since it is not compatible with the RW
-	 * verification (shared_mem_init done too late).
-	 */
-#	define CONFIG_MALLOC
+/* Select fingerprint sensor */
+#define CONFIG_FP_SENSOR_FPC1145
+#define CONFIG_CMD_FPSENSOR_DEBUG
+/* Special memory regions to store large arrays */
+#define FP_FRAME_SECTION __SECTION(ahb4)
+#define FP_TEMPLATE_SECTION __SECTION(ahb)
+/*
+ * Use the malloc code only in the RW section (for the private library),
+ * we cannot enable it in RO since it is not compatible with the RW
+ * verification (shared_mem_init done too late).
+ */
+#define CONFIG_MALLOC
 #endif /* SECTION_IS_RW */
 
 #ifndef __ASSEMBLER__
-	void fps_event(enum gpio_signal signal);
+void fps_event(enum gpio_signal signal);
 #endif /* !__ASSEMBLER__ */
 
 #endif /* __BOARD_H */
diff --git a/board/nucleo-dartmonkey/build.mk b/board/nucleo-dartmonkey/build.mk
index 4bc677e7e0..8aa93b8fe5 100644
--- a/board/nucleo-dartmonkey/build.mk
+++ b/board/nucleo-dartmonkey/build.mk
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -15,6 +15,7 @@ test-list-y=\
        cec \
        compile_time_macros \
        crc \
+       debug \
        flash_physical \
        flash_write_protect \
        fpsensor \
@@ -32,6 +33,7 @@ test-list-y=\
        sha256 \
        sha256_unrolled \
        static_if \
+       stdlib \
        timer_dos \
        utils \
        utils_str \
diff --git a/board/nucleo-dartmonkey/ec.tasklist b/board/nucleo-dartmonkey/ec.tasklist
index 80e226637b..7f35361949 100644
--- a/board/nucleo-dartmonkey/ec.tasklist
+++ b/board/nucleo-dartmonkey/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nucleo-dartmonkey/fpsensor_detect.c b/board/nucleo-dartmonkey/fpsensor_detect.c
index 72b9b89e11..7a9c128211 100644
--- a/board/nucleo-dartmonkey/fpsensor_detect.c
+++ b/board/nucleo-dartmonkey/fpsensor_detect.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nucleo-dartmonkey/gpio.inc b/board/nucleo-dartmonkey/gpio.inc
index 11709fe738..a9e5101855 100644
--- a/board/nucleo-dartmonkey/gpio.inc
+++ b/board/nucleo-dartmonkey/gpio.inc
@@ -1,5 +1,5 @@
 /*
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nucleo-f072rb/board.c b/board/nucleo-f072rb/board.c
index 078af171cb..729589a702 100644
--- a/board/nucleo-f072rb/board.c
+++ b/board/nucleo-f072rb/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,8 +21,12 @@ void button_event(enum gpio_signal signal)
  * Mock interrupt handler. It's supposed to be overwritten by each suite
  * if needed.
  */
-__attribute__((weak)) void cts_irq1(enum gpio_signal signal) {}
-__attribute__((weak)) void cts_irq2(enum gpio_signal signal) {}
+__attribute__((weak)) void cts_irq1(enum gpio_signal signal)
+{
+}
+__attribute__((weak)) void cts_irq2(enum gpio_signal signal)
+{
+}
 #endif
 
 #include "gpio_list.h"
@@ -38,14 +42,12 @@ void tick_event(void)
 DECLARE_HOOK(HOOK_TICK, tick_event, HOOK_PRIO_DEFAULT);
 
 #ifdef CTS_MODULE_I2C
-const struct i2c_port_t i2c_ports[]  = {
-	{
-		.name = "test",
-		.port = STM32_I2C1_PORT,
-		.kbps = 100,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	},
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "test",
+	  .port = STM32_I2C1_PORT,
+	  .kbps = 100,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
 };
 
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
@@ -57,6 +59,5 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 static void board_init(void)
 {
 	gpio_enable_interrupt(GPIO_USER_BUTTON);
-
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/nucleo-f072rb/board.h b/board/nucleo-f072rb/board.h
index 0ec675ab61..d807209564 100644
--- a/board/nucleo-f072rb/board.h
+++ b/board/nucleo-f072rb/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,7 +20,7 @@
 
 #ifdef CTS_MODULE
 #undef STM32_IRQ_EXT2_3_PRIORITY
-#define STM32_IRQ_EXT2_3_PRIORITY	2
+#define STM32_IRQ_EXT2_3_PRIORITY 2
 #ifdef CTS_MODULE_I2C
 #define CONFIG_I2C
 #define CONFIG_I2C_CONTROLLER
diff --git a/board/nucleo-f072rb/build.mk b/board/nucleo-f072rb/build.mk
index 0e069a31ad..7ac70706fc 100644
--- a/board/nucleo-f072rb/build.mk
+++ b/board/nucleo-f072rb/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/nucleo-f072rb/ec.tasklist b/board/nucleo-f072rb/ec.tasklist
index a6385530b5..3ddec80f41 100644
--- a/board/nucleo-f072rb/ec.tasklist
+++ b/board/nucleo-f072rb/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nucleo-f072rb/gpio.inc b/board/nucleo-f072rb/gpio.inc
index 6f3b592845..a14c7a5470 100644
--- a/board/nucleo-f072rb/gpio.inc
+++ b/board/nucleo-f072rb/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nucleo-f072rb/openocd-flash.cfg b/board/nucleo-f072rb/openocd-flash.cfg
index 91e3805c74..f06b3c22a2 100644
--- a/board/nucleo-f072rb/openocd-flash.cfg
+++ b/board/nucleo-f072rb/openocd-flash.cfg
@@ -1,4 +1,4 @@
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/board/nucleo-f411re/board.c b/board/nucleo-f411re/board.c
index 96e7fefb69..0c77a64e71 100644
--- a/board/nucleo-f411re/board.c
+++ b/board/nucleo-f411re/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -43,22 +43,20 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* Arduino connectors analog pins */
-	[ADC1_0] = {"ADC1_0",  3000, 4096, 0, STM32_AIN(0)},
-	[ADC1_1] = {"ADC1_1",  3000, 4096, 0, STM32_AIN(1)},
-	[ADC1_4] = {"ADC1_4",  3000, 4096, 0, STM32_AIN(4)},
-	[ADC1_8] = {"ADC1_8",  3000, 4096, 0, STM32_AIN(8)},
+	[ADC1_0] = { "ADC1_0", 3000, 4096, 0, STM32_AIN(0) },
+	[ADC1_1] = { "ADC1_1", 3000, 4096, 0, STM32_AIN(1) },
+	[ADC1_4] = { "ADC1_4", 3000, 4096, 0, STM32_AIN(4) },
+	[ADC1_8] = { "ADC1_8", 3000, 4096, 0, STM32_AIN(8) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "master",
-		.port = I2C_PORT_MASTER,
-		.kbps = 100,
-		.scl  = GPIO_MASTER_I2C_SCL,
-		.sda  = GPIO_MASTER_I2C_SDA
-	},
+	{ .name = "master",
+	  .port = I2C_PORT_MASTER,
+	  .kbps = 100,
+	  .scl = GPIO_MASTER_I2C_SCL,
+	  .sda = GPIO_MASTER_I2C_SDA },
 };
 
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
@@ -117,13 +115,12 @@ const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
 #ifdef CONFIG_DMA_HELP
 #include "dma.h"
-static int command_dma_help(int argc, char **argv)
+static int command_dma_help(int argc, const char **argv)
 {
 	dma_dump(STM32_DMA2_STREAM0);
 	dma_test(STM32_DMA2_STREAM0);
 	dma_dump(STM32_DMA2_STREAM0);
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(dmahelp, command_dma_help,
-			NULL, "Run DMA test");
+DECLARE_CONSOLE_COMMAND(dmahelp, command_dma_help, NULL, "Run DMA test");
 #endif
diff --git a/board/nucleo-f411re/board.h b/board/nucleo-f411re/board.h
index 56d2ad41d0..d4e299dcff 100644
--- a/board/nucleo-f411re/board.h
+++ b/board/nucleo-f411re/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,7 +12,6 @@
 #define CPU_CLOCK 84000000
 #define CONFIG_FLASH_WRITE_SIZE STM32_FLASH_WRITE_SIZE_3300
 
-
 /* the UART console is on USART2 (PA2/PA3) */
 #undef CONFIG_UART_CONSOLE
 #define CONFIG_UART_CONSOLE 2
@@ -43,7 +42,7 @@
 #define CONFIG_I2C_CONTROLLER
 #define CONFIG_I2C_DEBUG
 #define I2C_PORT_MASTER 1
-#define I2C_PORT_SLAVE 0        /* needed for DMAC macros (ugh) */
+#define I2C_PORT_SLAVE 0 /* needed for DMAC macros (ugh) */
 #define I2C_PORT_ACCEL I2C_PORT_MASTER
 
 #ifndef __ASSEMBLER__
diff --git a/board/nucleo-f411re/build.mk b/board/nucleo-f411re/build.mk
index 3a5fc28558..93a0a02ecc 100644
--- a/board/nucleo-f411re/build.mk
+++ b/board/nucleo-f411re/build.mk
@@ -1,4 +1,4 @@
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/nucleo-f411re/ec.tasklist b/board/nucleo-f411re/ec.tasklist
index b5e3cb82b2..a9566a92aa 100644
--- a/board/nucleo-f411re/ec.tasklist
+++ b/board/nucleo-f411re/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nucleo-f411re/gpio.inc b/board/nucleo-f411re/gpio.inc
index 83a9e51a08..2fd98f2a4a 100644
--- a/board/nucleo-f411re/gpio.inc
+++ b/board/nucleo-f411re/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nucleo-f411re/openocd-flash.cfg b/board/nucleo-f411re/openocd-flash.cfg
index 7a6ea6316c..23da86c6ba 100644
--- a/board/nucleo-f411re/openocd-flash.cfg
+++ b/board/nucleo-f411re/openocd-flash.cfg
@@ -1,4 +1,4 @@
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/board/nucleo-f412zg/board.c b/board/nucleo-f412zg/board.c
index da3b4a3d4d..9ab9bfa190 100644
--- a/board/nucleo-f412zg/board.c
+++ b/board/nucleo-f412zg/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -31,8 +31,8 @@ static void ap_deferred(void)
 	 * in S0:   SLP_S3_L is 1 and SLP_S0_L is 1.
 	 * in S5/G3, the FP MCU should not be running.
 	 */
-	int running = gpio_get_level(GPIO_PCH_SLP_S3_L)
-			&& gpio_get_level(GPIO_PCH_SLP_S0_L);
+	int running = gpio_get_level(GPIO_PCH_SLP_S3_L) &&
+		      gpio_get_level(GPIO_PCH_SLP_S0_L);
 
 	if (running) { /* S0 */
 		disable_sleep(SLEEP_MASK_AP_RUN);
diff --git a/board/nucleo-f412zg/board.h b/board/nucleo-f412zg/board.h
index f6e1368847..7e3c8d976d 100644
--- a/board/nucleo-f412zg/board.h
+++ b/board/nucleo-f412zg/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,6 +26,6 @@
  * Enable the blink example that exercises the LEDs.
  */
 #define CONFIG_BLINK
-#define CONFIG_BLINK_LEDS    GPIO_LED1, GPIO_LED2, GPIO_LED3
+#define CONFIG_BLINK_LEDS GPIO_LED1, GPIO_LED2, GPIO_LED3
 
 #endif /* __BOARD_H */
diff --git a/board/nucleo-f412zg/build.mk b/board/nucleo-f412zg/build.mk
index 6d46b6c289..be4f65063b 100644
--- a/board/nucleo-f412zg/build.mk
+++ b/board/nucleo-f412zg/build.mk
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -14,6 +14,7 @@ test-list-y=\
        cec \
        compile_time_macros \
        crc \
+       debug \
        flash_physical \
        flash_write_protect \
        mpu \
@@ -29,6 +30,7 @@ test-list-y=\
        sha256 \
        sha256_unrolled \
        static_if \
+       stdlib \
        stm32f_rtc \
        timer_dos \
        utils \
diff --git a/board/nucleo-f412zg/ec.tasklist b/board/nucleo-f412zg/ec.tasklist
index 896eb2fdb3..04e21000f9 100644
--- a/board/nucleo-f412zg/ec.tasklist
+++ b/board/nucleo-f412zg/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nucleo-f412zg/gpio.inc b/board/nucleo-f412zg/gpio.inc
index 57f78203ba..6cc09a20df 100644
--- a/board/nucleo-f412zg/gpio.inc
+++ b/board/nucleo-f412zg/gpio.inc
@@ -1,5 +1,5 @@
 /*
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nucleo-g431rb/board.c b/board/nucleo-g431rb/board.c
index 2daf157e22..ef73c00924 100644
--- a/board/nucleo-g431rb/board.c
+++ b/board/nucleo-g431rb/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,7 +11,6 @@
 
 #include "gpio_list.h" /* Must come after other header files. */
 
-
 static void board_init(void)
 {
 	/*
diff --git a/board/nucleo-g431rb/board.h b/board/nucleo-g431rb/board.h
index a65daa4364..905b4ea110 100644
--- a/board/nucleo-g431rb/board.h
+++ b/board/nucleo-g431rb/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,14 +14,13 @@
 #define CPU_CLOCK 48000000
 #define CONFIG_STM_HWTIMER32
 #define TIM_CLOCK32 2
-#define TIM_CLOCK_MSB  3
+#define TIM_CLOCK_MSB 3
 #define TIM_CLOCK_LSB 15
 #define TIM_WATCHDOG 7
 
 /* Nucelo platform does not have a lid switch */
 #undef CONFIG_LID_SWITCH
 
-
 /* Setup UART console */
 /*
  * The STM32G431 Nucleo-64 has two UARTs which can be connected to the virtual
@@ -49,24 +48,20 @@
 #define CONFIG_UART_TX_DMA_PH DMAMUX_REQ_USART1_TX
 #endif
 
-
 /*
  * Macros for GPIO signals used in common code that don't match the
  * schematic names. Signal names in gpio.inc match the schematic and are
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_ENTERING_RW	GPIO_EC_ENTERING_RW
-#define GPIO_WP_L		GPIO_EC_WP_L
-
-
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_WP_L GPIO_EC_WP_L
 
 #ifndef __ASSEMBLER__
 
 #include "gpio_signal.h"
 #include "registers.h"
 
-
 #endif /* !__ASSEMBLER__ */
 
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/nucleo-g431rb/build.mk b/board/nucleo-g431rb/build.mk
index 8140048cdd..a5a00675ee 100644
--- a/board/nucleo-g431rb/build.mk
+++ b/board/nucleo-g431rb/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/nucleo-g431rb/ec.tasklist b/board/nucleo-g431rb/ec.tasklist
index c272906fc7..682e6d8290 100644
--- a/board/nucleo-g431rb/ec.tasklist
+++ b/board/nucleo-g431rb/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nucleo-g431rb/gpio.inc b/board/nucleo-g431rb/gpio.inc
index 4dd4a6d966..4c7507eff9 100644
--- a/board/nucleo-g431rb/gpio.inc
+++ b/board/nucleo-g431rb/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nucleo-h743zi/board.c b/board/nucleo-h743zi/board.c
index c69a456425..f63c362d5f 100644
--- a/board/nucleo-h743zi/board.c
+++ b/board/nucleo-h743zi/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -31,8 +31,8 @@ static void ap_deferred(void)
 	 * in S0:   SLP_S3_L is 1 and SLP_S0_L is 1.
 	 * in S5/G3, the FP MCU should not be running.
 	 */
-	int running = gpio_get_level(GPIO_PCH_SLP_S3_L)
-			&& gpio_get_level(GPIO_PCH_SLP_S0_L);
+	int running = gpio_get_level(GPIO_PCH_SLP_S3_L) &&
+		      gpio_get_level(GPIO_PCH_SLP_S0_L);
 
 	if (running) { /* S0 */
 		disable_sleep(SLEEP_MASK_AP_RUN);
diff --git a/board/nucleo-h743zi/board.h b/board/nucleo-h743zi/board.h
index 966f2a8c94..81cdd60fc9 100644
--- a/board/nucleo-h743zi/board.h
+++ b/board/nucleo-h743zi/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -28,6 +28,6 @@
  * Enable the blink example that exercises the LEDs.
  */
 #define CONFIG_BLINK
-#define CONFIG_BLINK_LEDS    GPIO_LED1, GPIO_LED2, GPIO_LED3
+#define CONFIG_BLINK_LEDS GPIO_LED1, GPIO_LED2, GPIO_LED3
 
 #endif /* __BOARD_H */
diff --git a/board/nucleo-h743zi/build.mk b/board/nucleo-h743zi/build.mk
index 1230d9b334..0fb7975f32 100644
--- a/board/nucleo-h743zi/build.mk
+++ b/board/nucleo-h743zi/build.mk
@@ -1,4 +1,4 @@
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -14,6 +14,7 @@ test-list-y=\
        cec \
        compile_time_macros \
        crc \
+       debug \
        flash_physical \
        flash_write_protect \
        mpu \
@@ -29,6 +30,7 @@ test-list-y=\
        sha256 \
        sha256_unrolled \
        static_if \
+       stdlib \
        timer_dos \
        utils \
        utils_str \
diff --git a/board/nucleo-h743zi/ec.tasklist b/board/nucleo-h743zi/ec.tasklist
index 9c37e0b58b..ed124cd672 100644
--- a/board/nucleo-h743zi/ec.tasklist
+++ b/board/nucleo-h743zi/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nucleo-h743zi/gpio.inc b/board/nucleo-h743zi/gpio.inc
index 0f2bb32d75..a93133abd7 100644
--- a/board/nucleo-h743zi/gpio.inc
+++ b/board/nucleo-h743zi/gpio.inc
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nuwani/battery.c b/board/nuwani/battery.c
index 5cbbeb5123..e24b442049 100644
--- a/board/nuwani/battery.c
+++ b/board/nuwani/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/nuwani/board.c b/board/nuwani/board.c
index 567a26c8ef..eb36ad9df8 100644
--- a/board/nuwani/board.c
+++ b/board/nuwani/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -29,45 +29,35 @@ const enum gpio_signal hibernate_wake_pins[] = {
 	GPIO_POWER_BUTTON_L,
 	GPIO_EC_RST_ODL,
 };
-const int hibernate_wake_pins_used =  ARRAY_SIZE(hibernate_wake_pins);
+const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 
 /* I2C port map. */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl  = GPIO_I2C0_SCL,
-		.sda  = GPIO_I2C0_SDA
-	},
-	{
-		.name = "tcpc0",
-		.port = I2C_PORT_TCPC0,
-		.kbps = 400,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	},
-	{
-		.name = "tcpc1",
-		.port = I2C_PORT_TCPC1,
-		.kbps = 400,
-		.scl  = GPIO_I2C2_SCL,
-		.sda  = GPIO_I2C2_SDA
-	},
-	{
-		.name = "thermal",
-		.port = I2C_PORT_THERMAL_AP,
-		.kbps = 400,
-		.scl  = GPIO_I2C3_SCL,
-		.sda  = GPIO_I2C3_SDA
-	},
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl  = GPIO_I2C7_SCL,
-		.sda  = GPIO_I2C7_SDA
-	},
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_I2C0_SCL,
+	  .sda = GPIO_I2C0_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "tcpc1",
+	  .port = I2C_PORT_TCPC1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "thermal",
+	  .port = I2C_PORT_THERMAL_AP,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_I2C7_SCL,
+	  .sda = GPIO_I2C7_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -80,19 +70,15 @@ static struct stprivate_data g_lis2dwl_data;
 /* Base accel private data */
 static struct lsm6dsm_data g_lsm6dsm_data = LSM6DSM_DATA;
 
-
 /* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t lsm6dsm_base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lsm6dsm_base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+						      { 0, FLOAT_TO_FP(-1), 0 },
+						      { 0, 0,
+							FLOAT_TO_FP(1) } };
 
-static const mat33_fp_t treeya_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t treeya_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+						{ FLOAT_TO_FP(1), 0, 0 },
+						{ 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t lid_accel_1 = {
 	.name = "Lid Accel",
@@ -159,8 +145,7 @@ struct motion_sensor_t base_gyro_1 = {
 	.location = MOTIONSENSE_LOC_BASE,
 	.drv = &lsm6dsm_drv,
 	.mutex = &g_base_mutex_1,
-	.drv_data = LSM6DSM_ST_DATA(g_lsm6dsm_data,
-			MOTIONSENSE_TYPE_GYRO),
+	.drv_data = LSM6DSM_ST_DATA(g_lsm6dsm_data, MOTIONSENSE_TYPE_GYRO),
 	.port = I2C_PORT_ACCEL,
 	.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
 	.default_range = 1000 | ROUND_UP_FLAG, /* dps */
@@ -188,10 +173,12 @@ void board_update_sensor_config_from_sku(void)
 			motion_sensors[LID_ACCEL] = lid_accel_1;
 			motion_sensors[BASE_ACCEL] = base_accel_1;
 			motion_sensors[BASE_GYRO] = base_gyro_1;
-		} else{
+		} else {
 			/*Need to change matrix for treeya*/
-			motion_sensors[BASE_ACCEL].rot_standard_ref = &treeya_standard_ref;
-			motion_sensors[BASE_GYRO].rot_standard_ref = &treeya_standard_ref;
+			motion_sensors[BASE_ACCEL].rot_standard_ref =
+				&treeya_standard_ref;
+			motion_sensors[BASE_GYRO].rot_standard_ref =
+				&treeya_standard_ref;
 		}
 
 		/* Enable Gyro interrupts */
@@ -201,8 +188,7 @@ void board_update_sensor_config_from_sku(void)
 		/* Device is clamshell only */
 		tablet_set_mode(0, TABLET_TRIGGER_LID);
 		/* Gyro is not present, don't allow line to float */
-		gpio_set_flags(GPIO_6AXIS_INT_L,
-			       GPIO_INPUT | GPIO_PULL_DOWN);
+		gpio_set_flags(GPIO_6AXIS_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
 	}
 }
 
diff --git a/board/nuwani/board.h b/board/nuwani/board.h
index 6bdffa73ac..b58102efe7 100644
--- a/board/nuwani/board.h
+++ b/board/nuwani/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,7 @@
  * By default, enable all console messages excepted HC, ACPI and event:
  * The sensor stack is generating a lot of activity.
  */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
 #undef CONFIG_HOSTCMD_DEBUG_MODE
 #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
 
@@ -47,7 +47,7 @@
 /*
  * Slew rate on the PP1800_SENSOR load switch requires a short delay on startup.
  */
-#undef  CONFIG_MOTION_SENSE_RESUME_DELAY_US
+#undef CONFIG_MOTION_SENSE_RESUME_DELAY_US
 #define CONFIG_MOTION_SENSE_RESUME_DELAY_US (10 * MSEC)
 
 /* Second set of sensor drivers */
@@ -58,7 +58,6 @@
 
 #ifndef __ASSEMBLER__
 
-
 enum battery_type {
 	BATTERY_SMP,
 	BATTERY_LGC,
diff --git a/board/nuwani/build.mk b/board/nuwani/build.mk
index 85b141b15d..c754c96237 100644
--- a/board/nuwani/build.mk
+++ b/board/nuwani/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/nuwani/ec.tasklist b/board/nuwani/ec.tasklist
index 2874dff927..c5db864fe5 100644
--- a/board/nuwani/ec.tasklist
+++ b/board/nuwani/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nuwani/gpio.inc b/board/nuwani/gpio.inc
index 18c72c8125..e01af85e34 100644
--- a/board/nuwani/gpio.inc
+++ b/board/nuwani/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/nuwani/led.c b/board/nuwani/led.c
index 76156d66d4..4013f22bd5 100644
--- a/board/nuwani/led.c
+++ b/board/nuwani/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,40 +8,43 @@
 #include "led_common.h"
 #include "gpio.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
 __override const int led_charge_lvl_1 = 5;
 
 __override const int led_charge_lvl_2 = 97;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,  2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
 
 __override const struct led_descriptor
-			led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-				{LED_OFF,          0.5 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 3 * LED_ONE_SEC },
+					       { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
diff --git a/board/oak/battery.c b/board/oak/battery.c
index fffd2f7763..b9b410932d 100644
--- a/board/oak/battery.c
+++ b/board/oak/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,7 +11,7 @@
 #include "util.h"
 
 /* Shutdown mode parameter to write to manufacturer access register */
-#define PARAM_CUT_OFF_LOW  0x10
+#define PARAM_CUT_OFF_LOW 0x10
 #define PARAM_CUT_OFF_HIGH 0x00
 
 static const struct battery_info info = {
@@ -21,7 +21,7 @@ static const struct battery_info info = {
 	/*
 	 * TODO(crosbug.com/p/44428):
 	 * In order to compatible with 2S battery, set min voltage as 6V rather
-         * than 9V. Should set voltage_min to 9V, when 2S battery
+	 * than 9V. Should set voltage_min to 9V, when 2S battery
 	 * phased out.
 	 */
 	.voltage_min = 6000,
@@ -57,10 +57,10 @@ static int cutoff(void)
 	buf[2] = PARAM_CUT_OFF_HIGH;
 
 	i2c_lock(I2C_PORT_BATTERY, 1);
-	rv = i2c_xfer_unlocked(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS,
-			       buf, 3, NULL, 0, I2C_XFER_SINGLE);
-	rv |= i2c_xfer_unlocked(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS,
-				buf, 3, NULL, 0, I2C_XFER_SINGLE);
+	rv = i2c_xfer_unlocked(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS, buf, 3,
+			       NULL, 0, I2C_XFER_SINGLE);
+	rv |= i2c_xfer_unlocked(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS, buf, 3,
+				NULL, 0, I2C_XFER_SINGLE);
 	i2c_lock(I2C_PORT_BATTERY, 0);
 
 	return rv;
diff --git a/board/oak/board.c b/board/oak/board.c
index 1c2e65b12a..468b6e6677 100644
--- a/board/oak/board.c
+++ b/board/oak/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -52,8 +52,8 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* Dispaly port hardware can connect to port 0, 1 or neither. */
 #define PD_PORT_NONE -1
@@ -76,8 +76,8 @@ void usb_evt(enum gpio_signal signal)
 
 /* power signal list.  Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
-	{GPIO_SOC_POWER_GOOD, POWER_SIGNAL_ACTIVE_HIGH, "POWER_GOOD"},
-	{GPIO_SUSPEND_L, POWER_SIGNAL_ACTIVE_LOW, "SUSPEND#_ASSERTED"},
+	{ GPIO_SOC_POWER_GOOD, POWER_SIGNAL_ACTIVE_HIGH, "POWER_GOOD" },
+	{ GPIO_SUSPEND_L, POWER_SIGNAL_ACTIVE_LOW, "SUSPEND#_ASSERTED" },
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
@@ -87,39 +87,32 @@ const struct adc_t adc_channels[] = {
 	 * PSYS_MONITOR(PA2): ADC_IN2, 1.44 uA/W on 6.05k Ohm
 	 * output in mW
 	 */
-	[ADC_PSYS] = {"PSYS", 379415, 4096, 0, STM32_AIN(2)},
+	[ADC_PSYS] = { "PSYS", 379415, 4096, 0, STM32_AIN(2) },
 	/* AMON_BMON(PC0): ADC_IN10, output in uV */
-	[ADC_AMON_BMON] = {"AMON_BMON", 183333, 4096, 0, STM32_AIN(10)},
+	[ADC_AMON_BMON] = { "AMON_BMON", 183333, 4096, 0, STM32_AIN(10) },
 	/* VDC_BOOSTIN_SENSE(PC1): ADC_IN11, output in mV */
-	[ADC_VBUS] = {"VBUS", 33000, 4096, 0, STM32_AIN(11)},
+	[ADC_VBUS] = { "VBUS", 33000, 4096, 0, STM32_AIN(11) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "battery",
-		.port = I2C_PORT_BATTERY,
-		.kbps = 100,
-		.scl  = GPIO_I2C0_SCL,
-		.sda  = GPIO_I2C0_SDA
-	},
-	{
-		.name = "pd",
-		.port = I2C_PORT_PD_MCU,
-		.kbps = 1000,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	}
-};
+const struct i2c_port_t i2c_ports[] = { { .name = "battery",
+					  .port = I2C_PORT_BATTERY,
+					  .kbps = 100,
+					  .scl = GPIO_I2C0_SCL,
+					  .sda = GPIO_I2C0_SDA },
+					{ .name = "pd",
+					  .port = I2C_PORT_PD_MCU,
+					  .kbps = 1000,
+					  .scl = GPIO_I2C1_SCL,
+					  .sda = GPIO_I2C1_SDA } };
 
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
 #ifdef CONFIG_ACCELGYRO_BMI160
 /* SPI devices */
-const struct spi_device_t spi_devices[] = {
-	{ CONFIG_SPI_ACCEL_PORT, 1, GPIO_SPI2_NSS }
-};
+const struct spi_device_t spi_devices[] = { { CONFIG_SPI_ACCEL_PORT, 1,
+					      GPIO_SPI2_NSS } };
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 #endif
 
@@ -184,42 +177,47 @@ const struct charger_config_t chg_chips[] = {
  *     src/mainboard/google/${board}/acpi/dptf.asl
  */
 const struct temp_sensor_t temp_sensors[] = {
-	{"TMP432_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-		TMP432_IDX_LOCAL},
-	{"TMP432_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-		TMP432_IDX_REMOTE1},
-	{"TMP432_Sensor_2", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-		TMP432_IDX_REMOTE2},
-	{"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp,
-		0},
+	{ "TMP432_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
+	  TMP432_IDX_LOCAL },
+	{ "TMP432_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
+	  TMP432_IDX_REMOTE1 },
+	{ "TMP432_Sensor_2", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
+	  TMP432_IDX_REMOTE2 },
+	{ "Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
 #ifdef HAS_TASK_ALS
 /* ALS instances. Must be in same order as enum als_id. */
 struct als_t als[] = {
-	{"TI", opt3001_init, opt3001_read_lux, 5},
+	{ "TI", opt3001_init, opt3001_read_lux, 5 },
 };
 BUILD_ASSERT(ARRAY_SIZE(als) == ALS_COUNT);
 #endif
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
-		.driver    = &pi3usb3x532_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX,
+				.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
+				.driver = &pi3usb3x532_usb_mux_driver,
+			},
 	},
 	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_USB_MUX,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_USB_MUX,
 #if (BOARD_REV <= OAK_REV4)
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR1,
-		.driver    = &pi3usb3x532_usb_mux_driver,
+				.i2c_addr_flags = PI3USB3X532_I2C_ADDR1,
+				.driver = &pi3usb3x532_usb_mux_driver,
 #else
-		.i2c_addr_flags = 0x10,
-		.driver = &ps8740_usb_mux_driver,
+				.i2c_addr_flags = 0x10,
+				.driver = &ps8740_usb_mux_driver,
 #endif
+			},
 	},
 };
 
@@ -340,10 +338,12 @@ int board_set_active_charge_port(int charge_port)
 	} else {
 		/* Make sure non-charging port is disabled */
 		gpio_set_level(charge_port ? GPIO_USB_C0_CHARGE_L :
-					     GPIO_USB_C1_CHARGE_L, 1);
+					     GPIO_USB_C1_CHARGE_L,
+			       1);
 		/* Enable charging port */
 		gpio_set_level(charge_port ? GPIO_USB_C1_CHARGE_L :
-					     GPIO_USB_C0_CHARGE_L, 0);
+					     GPIO_USB_C0_CHARGE_L,
+			       0);
 	}
 
 	return EC_SUCCESS;
@@ -357,11 +357,11 @@ int board_set_active_charge_port(int charge_port)
  * @param charge_ma     Desired charge limit (mA).
  * @param charge_mv     Negotiated charge voltage (mV).
  */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
-	charge_set_input_current_limit(MAX(charge_ma,
-				   CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 	pd_send_host_event(PD_EVENT_POWER_CHANGE);
 }
 
@@ -552,8 +552,8 @@ void vbus_task(void *u)
 			}
 
 			if (wake)
-				usb_charger_task_set_event(
-						port, USB_CHG_EVENT_BC12);
+				usb_charger_task_set_event(port,
+							   USB_CHG_EVENT_BC12);
 		}
 		task_wait_event(-1);
 	}
@@ -569,15 +569,15 @@ void vbus_task(void *u)
 #ifdef CONFIG_TEMP_SENSOR_TMP432
 static void tmp432_set_power_deferred(void)
 {
-       /* Shut tmp432 down if not in S0 && no external power */
-       if (!extpower_is_present() && !chipset_in_state(CHIPSET_STATE_ON)) {
-               if (EC_SUCCESS != tmp432_set_power(TMP432_POWER_OFF))
+	/* Shut tmp432 down if not in S0 && no external power */
+	if (!extpower_is_present() && !chipset_in_state(CHIPSET_STATE_ON)) {
+		if (EC_SUCCESS != tmp432_set_power(TMP432_POWER_OFF))
 			CPRINTS("ERROR: Can't shutdown TMP432.");
-               return;
-       }
+		return;
+	}
 
-       /*  else, turn it on. */
-       if (EC_SUCCESS != tmp432_set_power(TMP432_POWER_ON))
+	/*  else, turn it on. */
+	if (EC_SUCCESS != tmp432_set_power(TMP432_POWER_ON))
 		CPRINTS("ERROR: Can't turn on TMP432.");
 }
 DECLARE_DEFERRED(tmp432_set_power_deferred);
@@ -602,7 +602,7 @@ static void board_chipset_pre_init(void)
 	board_extpower_buffer_to_soc();
 #if BOARD_REV >= OAK_REV5
 	/* Enable DP muxer */
-	gpio_set_level(GPIO_DP_MUX_EN_L , 0);
+	gpio_set_level(GPIO_DP_MUX_EN_L, 0);
 	gpio_set_level(GPIO_PARADE_MUX_EN, 1);
 #endif
 }
@@ -615,13 +615,12 @@ static void board_chipset_shutdown(void)
 	gpio_set_level(GPIO_LEVEL_SHIFT_EN_L, 1);
 #if BOARD_REV >= OAK_REV5
 	/* Disable DP muxer */
-	gpio_set_level(GPIO_DP_MUX_EN_L , 1);
+	gpio_set_level(GPIO_DP_MUX_EN_L, 1);
 	gpio_set_level(GPIO_PARADE_MUX_EN, 0);
 #endif
 }
 DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
 
-
 /* Called on AP S3 -> S0 transition */
 static void board_chipset_resume(void)
 {
@@ -650,11 +649,9 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0,  0},
-	{ 0, FLOAT_TO_FP(-1),  0},
-	{ 0,  0,  FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				       { 0, FLOAT_TO_FP(-1), 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
 #endif
 
 static struct kionix_accel_data g_kx022_data;
diff --git a/board/oak/board.h b/board/oak/board.h
index b40215a7bf..6f5ed3fc87 100644
--- a/board/oak/board.h
+++ b/board/oak/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,7 +23,7 @@
 #endif
 
 #define CONFIG_ADC
-#undef  CONFIG_ADC_WATCHDOG
+#undef CONFIG_ADC_WATCHDOG
 
 #if BOARD_REV >= OAK_REV5
 /* Add for Ambient Light Sensor */
@@ -107,10 +107,10 @@
 #define CONFIG_SPI_CONTROLLER
 #define CONFIG_STM_HWTIMER32
 #define CONFIG_VBOOT_HASH
-#undef  CONFIG_WATCHDOG_HELP
+#undef CONFIG_WATCHDOG_HELP
 #define CONFIG_SWITCH
 #define CONFIG_BOARD_VERSION_GPIO
-#undef  CONFIG_UART_CONSOLE
+#undef CONFIG_UART_CONSOLE
 #define CONFIG_UART_CONSOLE 1
 #define CONFIG_TEMP_SENSOR
 #define CONFIG_TEMP_SENSOR_TMP432
@@ -149,19 +149,19 @@
 #define KB_OUT_PORT_LIST GPIO_A, GPIO_B, GPIO_C, GPIO_D
 
 /* 2 I2C master ports, connect to battery, charger, pd and USB switches */
-#define I2C_PORT_MASTER  0
-#define I2C_PORT_ACCEL   0
-#define I2C_PORT_ALS     0
+#define I2C_PORT_MASTER 0
+#define I2C_PORT_ACCEL 0
+#define I2C_PORT_ALS 0
 #define I2C_PORT_BATTERY 0
 #define I2C_PORT_CHARGER 0
 #define I2C_PORT_PERICOM 0
 #define I2C_PORT_THERMAL 0
-#define I2C_PORT_PD_MCU  1
+#define I2C_PORT_PD_MCU 1
 #define I2C_PORT_USB_MUX 1
-#define I2C_PORT_TCPC    1
+#define I2C_PORT_TCPC 1
 
 /* Enable Accel over SPI */
-#define CONFIG_SPI_ACCEL_PORT    0  /* First SPI controller port (SPI2) */
+#define CONFIG_SPI_ACCEL_PORT 0 /* First SPI controller port (SPI2) */
 
 /* Ambient Light Sensor address */
 #define OPT3001_I2C_ADDR_FLAGS OPT3001_I2C_ADDR1_FLAGS
@@ -171,12 +171,12 @@
 #define TIM_WATCHDOG 4
 
 /* Define the host events which are allowed to wakeup AP in S3. */
-#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \
-		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_FASTBOOT))
+#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK                     \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |          \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |      \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |       \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_FASTBOOT))
 
 #include "gpio_signal.h"
 
@@ -194,9 +194,9 @@ enum pwm_channel {
 };
 
 enum adc_channel {
-	ADC_PSYS = 0,  /* PC1: STM32_AIN(2) */
+	ADC_PSYS = 0, /* PC1: STM32_AIN(2) */
 	ADC_AMON_BMON, /* PC0: STM32_AIN(10) */
-	ADC_VBUS,      /* PA2: STM32_AIN(11) */
+	ADC_VBUS, /* PA2: STM32_AIN(11) */
 	ADC_CH_COUNT
 };
 
@@ -235,16 +235,16 @@ enum als_id {
  * delay to turn on the power supply max is ~16ms.
  * delay to turn off the power supply max is about ~180ms.
  */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* delay to turn on/off vconn */
 
 /* Define typical operating power and max power */
 #define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       60000
-#define PD_MAX_CURRENT_MA     CONFIG_CHARGER_MAX_INPUT_CURRENT
-#define PD_MAX_VOLTAGE_MV     20000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA CONFIG_CHARGER_MAX_INPUT_CURRENT
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Reset PD MCU */
 void board_reset_pd_mcu(void);
@@ -256,6 +256,6 @@ void board_typec_dp_on(int port);
 void board_typec_dp_off(int port, int *dp_flags);
 void board_typec_dp_set(int port, int level);
 
-#endif  /* !__ASSEMBLER__ */
+#endif /* !__ASSEMBLER__ */
 
-#endif  /* __CROS_EC_BOARD_H */
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/oak/board_revs.h b/board/oak/board_revs.h
index 34fc4bfc88..6220a05fb0 100644
--- a/board/oak/board_revs.h
+++ b/board/oak/board_revs.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,7 +12,7 @@
 #define OAK_REV3 3
 #define OAK_REV4 4
 #define OAK_REV5 5
-#define OAK_REV_LAST    OAK_REV5
+#define OAK_REV_LAST OAK_REV5
 #define OAK_REV_DEFAULT OAK_REV5
 
 #if !defined(BOARD_REV)
diff --git a/board/oak/build.mk b/board/oak/build.mk
index dc21970df0..1cbbb2ac63 100644
--- a/board/oak/build.mk
+++ b/board/oak/build.mk
@@ -1,5 +1,5 @@
 #-*- makefile -*-
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/oak/ec.tasklist b/board/oak/ec.tasklist
index 2af7da77eb..80c39f2617 100644
--- a/board/oak/ec.tasklist
+++ b/board/oak/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/oak/gpio.inc b/board/oak/gpio.inc
index 3789f3ec35..b2ce008363 100644
--- a/board/oak/gpio.inc
+++ b/board/oak/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/oak/led.c b/board/oak/led.c
index 877f115a12..64f5123b3c 100644
--- a/board/oak/led.c
+++ b/board/oak/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -14,9 +14,7 @@
 #include "util.h"
 #include "system.h"
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -27,7 +25,7 @@ enum led_color {
 	BAT_LED_AMBER,
 	PWR_LED_GREEN,
 	PWR_LED_ORANGE,
-	LED_COLOR_COUNT		/* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static int bat_led_set(enum led_color color, int on)
@@ -113,7 +111,7 @@ static void oak_led_set_power(int board_version)
 
 	power_second++;
 
-	switch(board_version) {
+	switch (board_version) {
 	case OAK_REV3:
 	case OAK_REV4:
 		/*
@@ -131,8 +129,7 @@ static void oak_led_set_power(int board_version)
 			bat_led_set(PWR_LED_ORANGE, 0);
 		} else if (chipset_in_state(CHIPSET_STATE_SUSPEND)) {
 			bat_led_set(PWR_LED_GREEN, 0);
-			bat_led_set(PWR_LED_ORANGE,
-				    (power_second & 3) ? 0 : 1);
+			bat_led_set(PWR_LED_ORANGE, (power_second & 3) ? 0 : 1);
 		}
 		break;
 	default:
@@ -146,7 +143,7 @@ static void oak_led_set_battery(int board_version)
 
 	battery_second++;
 
-	switch(board_version) {
+	switch (board_version) {
 	case OAK_REV3:
 	case OAK_REV4:
 		/*
@@ -169,10 +166,10 @@ static void oak_led_set_battery(int board_version)
 			bat_led_set(BAT_LED_GREEN, 0);
 			if (charge_get_percent() < 3)
 				bat_led_set(BAT_LED_RED,
-					  (battery_second & 1) ? 0 : 1);
+					    (battery_second & 1) ? 0 : 1);
 			else if (charge_get_percent() < 10)
 				bat_led_set(BAT_LED_RED,
-					  (battery_second & 3) ? 0 : 1);
+					    (battery_second & 3) ? 0 : 1);
 			else
 				bat_led_set(BAT_LED_RED, 0);
 			break;
@@ -191,7 +188,8 @@ static void oak_led_set_battery(int board_version)
 	default:
 		/*
 		 * Put power control here since we are using the "battery" LED.
-		 * This allows LED autocontrol to be turned off by cmd during factory test.
+		 * This allows LED autocontrol to be turned off by cmd during
+		 * factory test.
 		 *
 		 * PWR LED behavior:
 		 * Power on: Green
@@ -205,8 +203,8 @@ static void oak_led_set_battery(int board_version)
 		else if (chipset_in_state(CHIPSET_STATE_SUSPEND)) {
 			int cycle_time = 4;
 			/* Oak rev5 with GlaDOS ID has a extremely power
-			 * comsuming LED. Increase LED blink cycle time to reduce
-			 * S3 power comsuption. */
+			 * comsuming LED. Increase LED blink cycle time to
+			 * reduce S3 power comsuption. */
 			if (board_version >= OAK_REV5)
 				cycle_time = 10;
 			bat_led_set(BAT_LED_GREEN,
@@ -231,10 +229,10 @@ static void oak_led_set_battery(int board_version)
 		case PWR_STATE_DISCHARGE:
 			if (charge_get_percent() < 3)
 				bat_led_set(BAT_LED_ORANGE,
-					  (battery_second & 1) ? 0 : 1);
+					    (battery_second & 1) ? 0 : 1);
 			else if (charge_get_percent() < 10)
 				bat_led_set(BAT_LED_ORANGE,
-					  (battery_second & 3) ? 0 : 1);
+					    (battery_second & 3) ? 0 : 1);
 			else
 				bat_led_set(BAT_LED_ORANGE, 0);
 			break;
diff --git a/board/oak/usb_pd_policy.c b/board/oak/usb_pd_policy.c
index a4e62ebe88..c337aa4b59 100644
--- a/board/oak/usb_pd_policy.c
+++ b/board/oak/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,17 +18,15 @@
 #include "usb_mux.h"
 #include "usb_pd.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_set_power_supply_ready(int port)
 {
 	/* Disable charging */
-	gpio_set_level(port ? GPIO_USB_C1_CHARGE_L :
-			      GPIO_USB_C0_CHARGE_L, 1);
+	gpio_set_level(port ? GPIO_USB_C1_CHARGE_L : GPIO_USB_C0_CHARGE_L, 1);
 	/* Provide VBUS */
-	gpio_set_level(port ? GPIO_USB_C1_5V_EN :
-			      GPIO_USB_C0_5V_EN, 1);
+	gpio_set_level(port ? GPIO_USB_C1_5V_EN : GPIO_USB_C0_5V_EN, 1);
 
 	/* notify host of power info change */
 	pd_send_host_event(PD_EVENT_POWER_CHANGE);
@@ -39,8 +37,7 @@ int pd_set_power_supply_ready(int port)
 void pd_power_supply_reset(int port)
 {
 	/* Disable VBUS */
-	gpio_set_level(port ? GPIO_USB_C1_5V_EN :
-			      GPIO_USB_C0_5V_EN, 0);
+	gpio_set_level(port ? GPIO_USB_C1_5V_EN : GPIO_USB_C0_5V_EN, 0);
 
 	/* notify host of power info change */
 	pd_send_host_event(PD_EVENT_POWER_CHANGE);
diff --git a/board/osiris/battery.c b/board/osiris/battery.c
index 61c0f7f886..669b592b1b 100644
--- a/board/osiris/battery.c
+++ b/board/osiris/battery.c
@@ -1,12 +1,16 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Battery pack vendor provided charging profile
  */
 
+#include "battery.h"
 #include "battery_fuel_gauge.h"
 #include "cbi.h"
+#include "charge_ramp.h"
+#include "charge_state.h"
+#include "charger_profile_override.h"
 #include "common.h"
 #include "compile_time_macros.h"
 #include "gpio.h"
@@ -33,39 +37,6 @@
  * address, mask, and disconnect value need to be provided.
  */
 const struct board_batt_params board_battery_info[] = {
-	/*
-	 * TODO(b:229947325): Copy kano battery AP19B8M for early support,
-	 * It should remove before FSI.
-	 */
-	/* LGC AP19B8M Battery Information */
-	[BATTERY_AP19B8M] = {
-		.fuel_gauge = {
-			.manuf_name = "LGC KT0030G024",
-			.ship_mode = {
-				.reg_addr = 0x3A,
-				.reg_data = { 0xC574, 0xC574 },
-			},
-			.fet = {
-				.reg_addr = 0x43,
-				.reg_mask = 0x0001,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0002,
-				.cfet_off_val = 0x0000,
-			}
-		},
-		.batt_info = {
-			.voltage_max          = 13350,
-			.voltage_normal       = 11610,
-			.voltage_min          = 9000,
-			.precharge_current    = 256,
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 50,
-			.charging_min_c       = 0,
-			.charging_max_c       = 60,
-			.discharging_min_c    = -20,
-			.discharging_max_c    = 75,
-		},
-	},
 	/* COSMX AP22ABN Battery Information */
 	[BATTERY_COSMX_AP22ABN] = {
 		.fuel_gauge = {
@@ -107,3 +78,73 @@ enum battery_present battery_hw_present(void)
 	/* The GPIO is low when the battery is physically present */
 	return gpio_get_level(GPIO_EC_BATT_PRES_ODL) ? BP_NO : BP_YES;
 }
+
+static int charger_should_discharge_on_ac(struct charge_state_data *curr)
+{
+	/* can not discharge on AC without battery */
+	if (curr->batt.is_present != BP_YES)
+		return 0;
+
+	/* Do not discharge when battery disconnect */
+	if (battery_get_disconnect_state() != BATTERY_NOT_DISCONNECTED)
+		return 0;
+
+	/* Do not discharge on AC if the battery is still waking up */
+	if ((curr->batt.flags & BATT_FLAG_BAD_STATUS) ||
+	    (!(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
+	     !(curr->batt.status & STATUS_FULLY_CHARGED)))
+		return 0;
+
+	/*
+	 * In heavy load (>3A being withdrawn from VSYS) the DCDC of the
+	 * charger operates on hybrid mode. This causes a slight voltage
+	 * ripple on VSYS that falls in the audible noise frequency (single
+	 * digit kHz range). This small ripple generates audible noise in
+	 * the output ceramic capacitors (caps on VSYS and any input of
+	 * DCDC under VSYS).
+	 *
+	 * To overcome this issue, force battery discharging when battery
+	 * full, So the battery MOS of NVDC charger will turn on always,
+	 * it make the Vsys same as Vbat and the noise has been improved.
+	 */
+	if (!battery_is_cut_off() &&
+	    !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
+	    (curr->batt.status & STATUS_FULLY_CHARGED))
+		return 1;
+
+	return 0;
+}
+
+/*
+ * This can override the smart battery's charging profile. To make a change,
+ * modify one or more of requested_voltage, requested_current, or state.
+ * Leave everything else unchanged.
+ *
+ * Return the next poll period in usec, or zero to use the default (which is
+ * state dependent).
+ */
+int charger_profile_override(struct charge_state_data *curr)
+{
+	int disch_on_ac = charger_should_discharge_on_ac(curr);
+
+	charger_discharge_on_ac(disch_on_ac);
+
+	if (disch_on_ac) {
+		curr->state = ST_DISCHARGE;
+		return 0;
+	}
+
+	return 0;
+}
+
+enum ec_status charger_profile_override_get_param(uint32_t param,
+						  uint32_t *value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+enum ec_status charger_profile_override_set_param(uint32_t param,
+						  uint32_t value)
+{
+	return EC_RES_INVALID_PARAM;
+}
diff --git a/board/osiris/board.c b/board/osiris/board.c
index 8d20de1550..6cfd7d8c26 100644
--- a/board/osiris/board.c
+++ b/board/osiris/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,15 +20,14 @@
 #include "power.h"
 #include "registers.h"
 #include "switch.h"
-#include "tablet_mode.h"
 #include "throttle_ap.h"
 #include "usbc_config.h"
 
 #include "gpio_list.h" /* Must come after other header files. */
 
 /* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 /* Called on AP S3 -> S0 transition */
 static void board_chipset_resume(void)
@@ -66,15 +65,14 @@ __override void board_kblight_init(void)
  * that we don't have pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-	{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-	{0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3},
-	{-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0},
-	{1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4},
-	{2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0},
-	{-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1},
-	{-1, -1},
+	{ -1, -1 }, { 0, 5 },	{ 1, 1 }, { 1, 0 },   { 0, 6 },	  { 0, 7 },
+	{ -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 },   { -1, -1 }, { 1, 6 },
+	{ 1, 7 },   { 3, 1 },	{ 2, 0 }, { 1, 5 },   { 2, 6 },	  { 2, 7 },
+	{ 2, 1 },   { 2, 4 },	{ 2, 5 }, { 1, 2 },   { 2, 3 },	  { 2, 2 },
+	{ 3, 0 },   { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 },	  { -1, -1 },
+	{ -1, -1 },
 };
 
 const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 #endif
diff --git a/board/osiris/board.h b/board/osiris/board.h
index 292a540087..c35cdce314 100644
--- a/board/osiris/board.h
+++ b/board/osiris/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,11 +21,16 @@
 
 #define CONFIG_MP2964
 
+/* Tablet mode is not supported */
+#undef CONFIG_TABLET_MODE
+#undef CONFIG_TABLET_MODE_SWITCH
+#undef CONFIG_LID_ANGLE
+
 /* LED */
 #define CONFIG_LED_ONOFF_STATES
 
 /* USB Type A Features */
-#define USB_PORT_COUNT			1
+#define USB_PORT_COUNT 1
 #define CONFIG_USB_PORT_POWER_DUMB
 
 #undef CONFIG_USB_PD_TCPM_NCT38XX
@@ -48,17 +53,20 @@
 #define CONFIG_USBC_PPC_SYV682X
 
 /* TODO: b/177608416 - measure and check these values on osiris */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
 
 /*
  * Passive USB-C cables only support up to 60W.
  */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
+
+#define CONFIG_CHARGER_PROFILE_OVERRIDE
+#define CONFIG_PWR_STATE_DISCHARGE_FULL
 
 /*
  * Macros for GPIO signals used in common code that don't match the
@@ -66,56 +74,55 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT		GPIO_EC_EN_EDP_BL
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_GSC_PACKET_MODE
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SYS_SLP_S0IX_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_TEMP_SENSOR_POWER		GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
 
 /*
  * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
  * signal.
  */
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_SEQ_EC_ALL_SYS_PG
-#define GPIO_PG_EC_DSW_PWROK		GPIO_SEQ_EC_DSW_PWROK
-#define GPIO_PG_EC_RSMRST_ODL		GPIO_SEQ_EC_RSMRST_ODL
-#define GPIO_POWER_BUTTON_L		GPIO_GSC_EC_PWR_BTN_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_ODL
-
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
 
 /* I2C Bus Configuration */
 
-#define I2C_PORT_RGBKB		NPCX_I2C_PORT0_0
+#define I2C_PORT_RGBKB NPCX_I2C_PORT0_0
 
-#define I2C_PORT_USB_C0_C2_TCPC	NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1_TCPC	NPCX_I2C_PORT4_1
+#define I2C_PORT_USB_C0_C2_TCPC NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1
 
-#define I2C_PORT_USB_C0_C2_PPC	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_PPC	NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C0_C2_PPC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1
 
-#define I2C_PORT_USB_C0_C2_BC12	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_BC12	NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C0_C2_BC12 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1
 
-#define I2C_PORT_USB_C1_MUX	NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1
 
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT5_0
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT7_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-#define I2C_PORT_MP2964		NPCX_I2C_PORT7_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0
 
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 
-#define I2C_ADDR_MP2964_FLAGS	0x20
+#define I2C_ADDR_MP2964_FLAGS 0x20
 
 /* Thermal features */
 #define CONFIG_THERMISTOR
@@ -123,32 +130,37 @@
 #define CONFIG_TEMP_SENSOR_POWER
 #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
 
-#define CONFIG_FANS			FAN_CH_COUNT
+#define CONFIG_FANS FAN_CH_COUNT
+#define CONFIG_FAN_RPM_CUSTOM
 
 /* Charger defines */
 #define CONFIG_CHARGER_ISL9241
 #define CONFIG_CHARGE_RAMP_SW
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
+
+/* shutdown if soc <= 3%, default is 4% */
+#undef CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE
+#define CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE 3
 
 #undef CONFIG_VOLUME_BUTTONS
 
 /* RGB Keyboard */
 #define CONFIG_KEYBOARD_BACKLIGHT
-#define GPIO_RGBKBD_SDB_L	GPIO_EC_KB_BL_EN_L
+#define GPIO_RGBKBD_SDB_L GPIO_EC_KB_BL_EN_L
 #ifdef SECTION_IS_RW
 #define CONFIG_RGB_KEYBOARD
-#define CONFIG_LED_DRIVER_IS31FL3733B     /* is31fl3733b on I2C */
+#define CONFIG_LED_DRIVER_IS31FL3733B /* is31fl3733b on I2C */
 #endif
-#define RGB_GRID0_COL		12
-#define RGB_GRID0_ROW		1
-#define I2C_PORT_KBMCU		I2C_PORT_RGBKB
+#define RGB_GRID0_COL 12
+#define RGB_GRID0_ROW 1
+#define I2C_PORT_KBMCU I2C_PORT_RGBKB
 
 #define CONFIG_KEYBOARD_FACTORY_TEST
 
 #ifndef __ASSEMBLER__
 
-#include "gpio_signal.h"	/* needed by registers.h */
+#include "gpio_signal.h" /* needed by registers.h */
 #include "registers.h"
 #include "usbc_config.h"
 
@@ -166,27 +178,17 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum battery_type {
-	BATTERY_AP19B8M,
-	BATTERY_COSMX_AP22ABN,
-	BATTERY_TYPE_COUNT
-};
+enum battery_type { BATTERY_COSMX_AP22ABN, BATTERY_TYPE_COUNT };
 
 enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,		/* PWM3 */
-	PWM_CH_FAN,			/* PWM5 */
+	PWM_CH_FAN = 0, /* PWM5 */
+	PWM_CH_FAN2, /* PWM3 */
 	PWM_CH_COUNT
 };
 
-enum fan_channel {
-	FAN_CH_0 = 0,
-	FAN_CH_COUNT
-};
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_1, FAN_CH_COUNT };
 
-enum mft_channel {
-	MFT_CH_0 = 0,
-	MFT_CH_COUNT
-};
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_1, MFT_CH_COUNT };
 
 #ifdef CONFIG_KEYBOARD_FACTORY_TEST
 extern const int keyboard_factory_scan_pins[][2];
diff --git a/board/osiris/build.mk b/board/osiris/build.mk
index b4a75892a5..fc29a4bb0e 100644
--- a/board/osiris/build.mk
+++ b/board/osiris/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/osiris/charger.c b/board/osiris/charger.c
index 85e0de90fe..88f5b85a41 100644
--- a/board/osiris/charger.c
+++ b/board/osiris/charger.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,9 +15,8 @@
 #include "usb_pd.h"
 #include "util.h"
 
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* Charger Chip Configuration */
 const struct charger_config_t chg_chips[] = {
@@ -84,7 +83,6 @@ int board_set_active_charge_port(int port)
 __overridable void board_set_charge_limit(int port, int supplier, int charge_ma,
 					  int max_ma, int charge_mv)
 {
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
diff --git a/board/osiris/ec.tasklist b/board/osiris/ec.tasklist
index cc968777a2..1b6c9cb361 100644
--- a/board/osiris/ec.tasklist
+++ b/board/osiris/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/osiris/fans.c b/board/osiris/fans.c
index fa5a8dc09a..5878d4c4c5 100644
--- a/board/osiris/fans.c
+++ b/board/osiris/fans.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,6 +12,7 @@
 #include "fan.h"
 #include "hooks.h"
 #include "pwm.h"
+#include "util.h"
 
 /* MFT channels. These are logically separate from pwm_channels. */
 const struct mft_t mft_channels[] = {
@@ -20,16 +21,28 @@ const struct mft_t mft_channels[] = {
 		.clk_src = TCKC_LFCLK,
 		.pwm_id = PWM_CH_FAN,
 	},
+	[MFT_CH_1] = {
+		.module = NPCX_MFT_MODULE_2,
+		.clk_src = TCKC_LFCLK,
+		.pwm_id = PWM_CH_FAN2,
+	},
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 static const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
 
+static const struct fan_conf fan_conf_1 = {
+	.flags = FAN_USE_RPM_MODE,
+	.ch = MFT_CH_1, /* Use MFT id to control fan */
+	.pgood_gpio = -1,
+	.enable_gpio = GPIO_EN_PP5000_FAN2,
+};
+
 /*
  * TODO(b/234545460): thermistor placement and calibration
  *
@@ -38,8 +51,14 @@ static const struct fan_conf fan_conf_0 = {
  * boards as well.
  */
 static const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 3000,
-	.rpm_start = 3000,
+	.rpm_min = 2500,
+	.rpm_start = 2500,
+	.rpm_max = 6000,
+};
+
+static const struct fan_rpm fan_rpm_1 = {
+	.rpm_min = 2500,
+	.rpm_start = 2500,
 	.rpm_max = 6000,
 };
 
@@ -48,4 +67,154 @@ const struct fan_t fans[FAN_CH_COUNT] = {
 		.conf = &fan_conf_0,
 		.rpm = &fan_rpm_0,
 	},
+	[FAN_CH_1] = {
+		.conf = &fan_conf_1,
+		.rpm = &fan_rpm_1,
+	},
+};
+
+/* fan control */
+
+struct fan_step {
+	int on;
+	int off;
+	int rpm;
+};
+
+struct fan_table_config {
+	/* number of control_table */
+	uint8_t step;
+	/* fan control table */
+	const struct fan_step *control_table;
+};
+
+const struct fan_step fan_table0[] = {
+	{ .on = 25, .off = 0, .rpm = 0 },
+	{ .on = 37, .off = 34, .rpm = 2500 },
+	{ .on = 42, .off = 39, .rpm = 2800 },
+	{ .on = 46, .off = 43, .rpm = 3000 },
+	{ .on = 51, .off = 48, .rpm = 3200 },
+	{ .on = 55, .off = 52, .rpm = 3600 },
+	{ .on = 59, .off = 56, .rpm = 4000 },
+	{ .on = 66, .off = 63, .rpm = 4600 },
+	{ .on = 72, .off = 69, .rpm = 5000 },
+	{ .on = 74, .off = 71, .rpm = 5500 },
+};
+const int fan_table0_count = ARRAY_SIZE(fan_table0);
+
+const struct fan_step fan_table1[] = {
+	{ .on = 25, .off = 0, .rpm = 0 },
+	{ .on = 51, .off = 48, .rpm = 3200 },
+	{ .on = 55, .off = 52, .rpm = 3600 },
+	{ .on = 59, .off = 56, .rpm = 4000 },
+	{ .on = 66, .off = 63, .rpm = 4600 },
+	{ .on = 72, .off = 69, .rpm = 5000 },
+	{ .on = 74, .off = 71, .rpm = 5500 },
+};
+const int fan_table1_count = ARRAY_SIZE(fan_table1);
+
+/* Fan control configuration */
+static struct fan_table_config fan_tables[] = {
+	[FAN_CH_0] = {
+		.step = fan_table0_count,
+		.control_table = (const struct fan_step *) &fan_table0,
+	},
+	[FAN_CH_1] = {
+		.step = fan_table1_count,
+		.control_table = (const struct fan_step *) &fan_table1,
+	},
 };
+BUILD_ASSERT(ARRAY_SIZE(fan_tables) == FAN_CH_COUNT);
+
+static int current_level[] = { 0, 0 };
+BUILD_ASSERT(ARRAY_SIZE(current_level) == FAN_CH_COUNT);
+
+static int previous_level[] = { 0, 0 };
+BUILD_ASSERT(ARRAY_SIZE(previous_level) == FAN_CH_COUNT);
+
+#undef BOARD_FAN_TEST
+
+#ifdef BOARD_FAN_TEST
+static int manual_temp = -1;
+#endif
+
+int fan_percent_to_rpm(int fan, int pct)
+{
+	static struct fan_table_config *fan_table;
+	static int previous_pct;
+	int i;
+
+	fan_table = &fan_tables[fan];
+
+#ifdef BOARD_FAN_TEST
+	if (manual_temp != -1)
+		pct = manual_temp;
+#endif
+
+	/*
+	 * Compare the pct and previous pct, we have the three paths :
+	 *  1. decreasing path. (check the off point)
+	 *  2. increasing path. (check the on point)
+	 *  3. invariant path. (return the current RPM)
+	 */
+	if (pct < previous_pct) {
+		for (i = current_level[fan]; i >= 0; i--) {
+			if (pct <= fan_table->control_table[i].off)
+				current_level[fan] = i - 1;
+			else
+				break;
+		}
+	} else if (pct > previous_pct) {
+		for (i = current_level[fan] + 1; i < fan_table->step; i++) {
+			if (pct >= fan_table->control_table[i].on)
+				current_level[fan] = i;
+			else
+				break;
+		}
+	}
+
+	if (current_level[fan] < 0)
+		current_level[fan] = 0;
+
+	if (current_level[fan] != previous_level[fan])
+		cprints(CC_THERMAL, "Fan %d: Set fan RPM to %d", fan,
+			fan_table->control_table[current_level[fan]].rpm);
+
+	if (fan == (FAN_CH_COUNT - 1))
+		previous_pct = pct;
+
+#ifdef BOARD_FAN_TEST
+	if (manual_temp != -1)
+		ccprints("Fan%d: temps:%d curr:%d prev:%d rpm:%d", fan, pct,
+			 current_level[fan], previous_level[fan],
+			 fan_table->control_table[current_level[fan]].rpm);
+#endif
+
+	previous_level[fan] = current_level[fan];
+
+	return fan_table->control_table[current_level[fan]].rpm;
+}
+
+#ifdef BOARD_FAN_TEST
+static int command_fan_test(int argc, const char **argv)
+{
+	char *e;
+	int t;
+
+	if (argc > 1) {
+		t = strtoi(argv[1], &e, 0);
+		if (*e) {
+			ccprints("Invalid test temp");
+			return EC_ERROR_INVAL;
+		}
+		manual_temp = t;
+		ccprints("manual temp is %d", manual_temp);
+		return EC_SUCCESS;
+	}
+	manual_temp = -1;
+	ccprints("manual temp reset");
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(fan_test, command_fan_test, "[temperature]",
+			"set manual temperature for fan test");
+#endif
diff --git a/board/osiris/fw_config.c b/board/osiris/fw_config.c
index 6a4469163b..1fb085fe6e 100644
--- a/board/osiris/fw_config.c
+++ b/board/osiris/fw_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,7 +10,7 @@
 #include "cros_board_info.h"
 #include "fw_config.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 static union osiris_cbi_fw_config fw_config;
 BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
diff --git a/board/osiris/fw_config.h b/board/osiris/fw_config.h
index c10e6a99ca..fb776dc5a4 100644
--- a/board/osiris/fw_config.h
+++ b/board/osiris/fw_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,10 +21,10 @@ enum ec_cfg_keyboard_backlight_type {
 
 union osiris_cbi_fw_config {
 	struct {
-		enum ec_cfg_keyboard_backlight_type	kb_bl : 1;
-		uint32_t				reserved_1 : 1;
-		uint32_t				audio : 2;
-		uint32_t				reserved_2 : 28;
+		enum ec_cfg_keyboard_backlight_type kb_bl : 1;
+		uint32_t reserved_1 : 1;
+		uint32_t audio : 2;
+		uint32_t reserved_2 : 28;
 	};
 	uint32_t raw_value;
 };
diff --git a/board/osiris/gpio.inc b/board/osiris/gpio.inc
index ca22ddba08..ea196571f8 100644
--- a/board/osiris/gpio.inc
+++ b/board/osiris/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2022 The Chromium OS Authors. All rights reserved.
+ * Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,7 +19,6 @@ GPIO_INT(SEQ_EC_RSMRST_ODL,              PIN(E, 2), GPIO_INT_BOTH, power_signal_
 GPIO_INT(SLP_S3_L,                       PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 GPIO_INT(SLP_SUS_L,                      PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
 GPIO_INT(SYS_SLP_S0IX_L,                 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(TABLET_MODE_L,                  PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
 GPIO_INT(USB_C0_BC12_INT_ODL,            PIN(C, 6), GPIO_INT_FALLING, bc12_interrupt)
 GPIO_INT(USB_C0_C2_TCPC_INT_ODL,         PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)
 GPIO_INT(USB_C0_PPC_INT_ODL,             PIN(6, 2), GPIO_INT_FALLING, ppc_interrupt)
@@ -59,7 +58,8 @@ GPIO(EC_PCH_RTCRST,                  PIN(7, 6), GPIO_OUT_LOW)
 GPIO(EC_PCH_SYS_PWROK,               PIN(3, 7), GPIO_OUT_LOW)
 GPIO(EC_PCH_WAKE_R_ODL,              PIN(C, 0), GPIO_ODR_HIGH)
 GPIO(EC_PROCHOT_ODL,                 PIN(6, 3), GPIO_ODR_HIGH)
-GPIO(EN_PP5000_FAN,                  PIN(6, 1), GPIO_OUT_HIGH)
+GPIO(EN_PP5000_FAN,                  PIN(6, 1), GPIO_OUT_LOW)
+GPIO(EN_PP5000_FAN2,                 PIN(9, 7), GPIO_OUT_LOW)
 GPIO(EN_PP5000_USBA_R,               PIN(D, 7), GPIO_OUT_LOW)
 GPIO(EN_S5_RAILS,                    PIN(B, 6), GPIO_OUT_LOW)
 GPIO(IMVP9_VRRDY_OD,                 PIN(4, 3), GPIO_INPUT)
@@ -74,7 +74,6 @@ GPIO(LED_1_L,                        PIN(C, 4), GPIO_OUT_HIGH)
 GPIO(LED_2_L,                        PIN(C, 3), GPIO_OUT_HIGH)
 GPIO(KYBL_EN,                        PIN(A, 7), GPIO_OUT_LOW)
 GPIO(AMP_PWR_EN,                     PIN(5, 7), GPIO_OUT_LOW)
-GPIO(EC_FAN_TACH_2,                  PIN(7, 3), GPIO_INPUT)
 GPIO(RGB_KB_INT,                     PIN(5, 6), GPIO_INPUT)
 
 /* UART alternate functions */
@@ -92,6 +91,7 @@ ALTERNATE(PIN_MASK(F, 0x0c), 0, MODULE_I2C, 0)               /* GPIOF3/I2C4_SCL1
 
 /* PWM alternate functions */
 ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0)               /* GPIO40/TA1 */
+ALTERNATE(PIN_MASK(7, 0x08), 0, MODULE_PWM, 0)               /* GPIO73/TA2 */
 ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0)               /* GPIO80/PWM3 */
 ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0)               /* GPIOB7/PWM5 */
 
@@ -122,9 +122,9 @@ UNUSED(PIN(8, 3))       /* GPIO83 */
 UNUSED(PIN(7, 0))       /* GPIO70 */
 UNUSED(PIN(8, 1))       /* GPIO81 */
 UNUSED(PIN(9, 3))       /* GPIO93 */
-UNUSED(PIN(9, 7))       /* GPIO97 */
 UNUSED(PIN(D, 0))       /* GPIOD0/I2C3_SDA0 */
 UNUSED(PIN(D, 1))       /* GPIOD1/I2C3_SCL0 */
+UNUSED(PIN(9, 5))       /* GPIO95 */
 
 /* Pre-configured PSL balls:  J8  K6 */
 
diff --git a/board/osiris/i2c.c b/board/osiris/i2c.c
index 7c88d306a7..2d0656c484 100644
--- a/board/osiris/i2c.c
+++ b/board/osiris/i2c.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,7 +9,7 @@
 #include "hooks.h"
 #include "i2c.h"
 
-#define BOARD_ID_FAST_PLUS_CAPABLE	2
+#define BOARD_ID_FAST_PLUS_CAPABLE 2
 
 /* I2C port map configuration */
 const struct i2c_port_t i2c_ports[] = {
diff --git a/board/osiris/keyboard.c b/board/osiris/keyboard.c
index cf74661173..cd557760eb 100644
--- a/board/osiris/keyboard.c
+++ b/board/osiris/keyboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,29 +12,28 @@
 #include "rgb_keyboard.h"
 #include "timer.h"
 
-
-#define CPRINTF(format, args...) cprintf(CC_KEYBOARD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_KEYBOARD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ##args)
 
 const struct key {
 	uint8_t row;
 	uint8_t col;
 } vivaldi_keys[] = {
-	{.row = 4, .col = 2},	/* T1 */
-	{.row = 3, .col = 2},	/* T2 */
-	{.row = 2, .col = 2},	/* T3 */
-	{.row = 1, .col = 2},	/* T4 */
-	{.row = 4, .col = 4},	/* T5 */
-	{.row = 3, .col = 4},	/* T6 */
-	{.row = 2, .col = 4},	/* T7 */
-	{.row = 2, .col = 9},	/* T8 */
-	{.row = 1, .col = 9},	/* T9 */
-	{.row = 1, .col = 4},	/* T10 */
-	{.row = 0, .col = 4},	/* T11 */
-	{.row = 1, .col = 5},	/* T12 */
-	{.row = 3, .col = 5},	/* T13 */
-	{.row = 2, .col = 1},	/* T14 */
-	{.row = 0, .col = 1},	/* T15 */
+	{ .row = 4, .col = 2 }, /* T1 */
+	{ .row = 3, .col = 2 }, /* T2 */
+	{ .row = 2, .col = 2 }, /* T3 */
+	{ .row = 1, .col = 2 }, /* T4 */
+	{ .row = 4, .col = 4 }, /* T5 */
+	{ .row = 3, .col = 4 }, /* T6 */
+	{ .row = 2, .col = 4 }, /* T7 */
+	{ .row = 2, .col = 9 }, /* T8 */
+	{ .row = 1, .col = 9 }, /* T9 */
+	{ .row = 1, .col = 4 }, /* T10 */
+	{ .row = 0, .col = 4 }, /* T11 */
+	{ .row = 1, .col = 5 }, /* T12 */
+	{ .row = 3, .col = 5 }, /* T13 */
+	{ .row = 2, .col = 1 }, /* T14 */
+	{ .row = 0, .col = 1 }, /* T15 */
 };
 BUILD_ASSERT(ARRAY_SIZE(vivaldi_keys) == MAX_TOP_ROW_KEYS);
 
@@ -55,8 +54,8 @@ static const struct ec_response_keybd_config osiris_vivaldi_kb = {
 	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
 };
 
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	return &osiris_vivaldi_kb;
 }
@@ -81,139 +80,16 @@ const uint8_t rgbkbd_count = ARRAY_SIZE(rgbkbds);
 const uint8_t rgbkbd_hsize = RGB_GRID0_COL;
 const uint8_t rgbkbd_vsize = RGB_GRID0_ROW;
 
-/* TODO(b/233323599): need to check and update */
-#define LED(x, y)	RGBKBD_COORD((x), (y))
-#define DELM		RGBKBD_DELM
+enum ec_rgbkbd_type rgbkbd_type = EC_RGBKBD_TYPE_FOUR_ZONES_12_LEDS;
+
+#define LED(x, y) RGBKBD_COORD((x), (y))
+#define DELM RGBKBD_DELM
+
 const uint8_t rgbkbd_map[] = {
-	DELM,				/* 0: (null) */
-	LED(0, 0), DELM,		/* 1: ~ ` */
-	LED(0, 0), DELM,		/* 2: ! 1 */
-	LED(1, 0), DELM,		/* 3: @ 2 */
-	LED(1, 0), DELM,		/* 4: # 3 */
-	LED(2, 0), DELM,		/* 5: $ 4 */
-	LED(3, 0), DELM,		/* 6: % 5 */
-	LED(5, 0), DELM,		/* 7: ^ 6 */
-	LED(6, 0), DELM,		/* 8: & 7 */
-	LED(6, 0), DELM,		/* 9: * 8 */
-	LED(7, 0), DELM,		/* 10: ( 9 */
-	LED(8, 0), DELM,		/* 11: ) 0 */
-	LED(9, 0), DELM,		/* 12: _ - */
-	LED(10, 0), DELM,		/* 13: + = */
-	DELM,				/* 14: (null) */
-	LED(11, 0), DELM,		/* 15: backspace */
-	LED(0, 0), DELM,		/* 16: tab */
-	LED(0, 0), DELM,		/* 17: q */
-	LED(1, 0), DELM,		/* 18: w */
-	LED(2, 0), DELM,		/* 19: e */
-	LED(3, 0), DELM,		/* 20: r */
-	LED(4, 0), DELM,		/* 21: t */
-	LED(5, 0), DELM,		/* 22: y */
-	LED(6, 0), DELM,		/* 23: u */
-	LED(7, 0), DELM,		/* 24: i */
-	LED(8, 0), DELM,		/* 25: o */
-	LED(9, 0), DELM,		/* 26: p */
-	LED(10, 0), DELM,		/* 27: [ { */
-	LED(11, 0), DELM,		/* 28: ] } */
-	LED(11, 0), DELM,		/* 29: \ | */
-	LED(0, 0), DELM,		/* 30: caps lock */
-	LED(1, 0), DELM,		/* 31: a */
-	LED(1, 0), DELM,		/* 32: s */
-	LED(2, 0), DELM,		/* 33: d */
-	LED(3, 0), DELM,		/* 34: f */
-	LED(4, 0), DELM,		/* 35: g */
-	LED(5, 0), DELM,		/* 36: h */
-	LED(6, 0), DELM,		/* 37: j */
-	LED(7, 0), DELM,		/* 38: k */
-	LED(8, 0), DELM,		/* 39: l */
-	LED(9, 0), DELM,		/* 40: ; : */
-	LED(10, 0), DELM,		/* 41: " ' */
-	DELM,				/* 42: (null) */
-	LED(11, 0), DELM,		/* 43: enter */
-	LED(0, 0), DELM,		/* 44: L-shift */
-	DELM,				/* 45: (null) */
-	LED(1, 0), DELM,		/* 46: z */
-	LED(2, 0), DELM,		/* 47: x */
-	LED(3, 0), DELM,		/* 48: c */
-	LED(3, 0), DELM,		/* 49: v */
-	LED(5, 0), DELM,		/* 50: b */
-	LED(6, 0), DELM,		/* 51: n */
-	LED(7, 0), DELM,		/* 52: m */
-	LED(8, 0), DELM,		/* 53: , < */
-	LED(9, 0), DELM,		/* 54: . > */
-	LED(10, 0), DELM,		/* 55: / ? */
-	DELM,				/* 56: (null) */
-	LED(11, 0), DELM,		/* 57: R-shift */
-	LED(0, 0), DELM,		/* 58: L-ctrl */
-	LED(11, 0), DELM,		/* 59: power */
-	LED(1, 0), LED(2, 0), DELM,	/* 60: L-alt */
-	LED(3, 0), LED(4, 0),
-	LED(5, 0), LED(6, 0), DELM,	/* 61: space */
-	LED(8, 0), DELM,		/* 62: R-alt */
-	DELM,				/* 63: (null) */
-	LED(9, 0), DELM,		/* 64: R-ctrl */
-	DELM,				/* 65: (null) */
-	DELM,				/* 66: (null) */
-	DELM,				/* 67: (null) */
-	DELM,				/* 68: (null) */
-	DELM,				/* 69: (null) */
-	DELM,				/* 70: (null) */
-	DELM,				/* 71: (null) */
-	DELM,				/* 72: (null) */
-	DELM,				/* 73: (null) */
-	DELM,				/* 74: (null) */
-	DELM,				/* 75: (null) */
-	DELM,				/* 76: delete */
-	DELM,				/* 77: (null) */
-	DELM,				/* 78: (null) */
-	LED(10, 0), DELM,		/* 79: left */
-	DELM,				/* 80: home */
-	DELM,				/* 81: end */
-	DELM,				/* 82: (null) */
-	LED(11, 0), DELM,		/* 83: up */
-	LED(11, 0), DELM,		/* 84: down */
-	DELM,				/* 85: page up */
-	DELM,				/* 86: page down */
-	DELM,				/* 87: (null) */
-	DELM,				/* 88: (null) */
-	LED(11, 0), DELM,		/* 89: right */
-	DELM,				/* 90: (null) */
-	DELM,				/* 91: numpad 7 */
-	DELM,				/* 92: numpad 4 */
-	DELM,				/* 93: numpad 1 */
-	DELM,				/* 94: (null) */
-	DELM,				/* 95: numpad / */
-	DELM,				/* 96: numpad 8 */
-	DELM,				/* 97: numpad 5 */
-	DELM,				/* 98: numpad 2 */
-	DELM,				/* 99: numpad 0 */
-	DELM,				/* 100: numpad * */
-	DELM,				/* 101: numpad 9 */
-	DELM,				/* 102: numpad 6 */
-	DELM,				/* 103: numpad 3 */
-	DELM,				/* 104: numpad . */
-	DELM,				/* 105: numpad - */
-	DELM,				/* 106: numpad + */
-	DELM,				/* 107: (null) */
-	DELM,				/* 108: numpad enter */
-	DELM,				/* 109: (null) */
-	LED(0, 0), DELM,		/* 110: esc */
-	LED(0, 0), DELM,		/* T1: back */
-	LED(1, 0), DELM,		/* T2: refresh */
-	LED(2, 0), DELM,		/* T3: full screen */
-	LED(3, 0), DELM,		/* T4: overview */
-	LED(5, 0), DELM,		/* T5: snapshot */
-	LED(6, 0), DELM,		/* T6: brightness down */
-	LED(7, 0), DELM,		/* T7: brightness up */
-	LED(8, 0), DELM,		/* T8: mute */
-	LED(9, 0), DELM,		/* T9: volume down */
-	LED(10, 0), DELM,		/* T10: volume up */
-	DELM,				/* T11: (null) */
-	DELM,				/* T12: (null) */
-	DELM,				/* T13: (null) */
-	DELM,				/* T14: (null) */
-	DELM,				/* T15: (null) */
-	DELM,				/* 126: (null) */
-	DELM,				/* 127: (null) */
+	DELM, LED(0, 0), DELM, LED(1, 0), DELM, LED(2, 0),  DELM, LED(3, 0),
+	DELM, LED(4, 0), DELM, LED(5, 0), DELM, LED(6, 0),  DELM, LED(7, 0),
+	DELM, LED(8, 0), DELM, LED(9, 0), DELM, LED(10, 0), DELM, LED(11, 0),
+	DELM, DELM,
 };
 #undef LED
 #undef DELM
@@ -237,28 +113,28 @@ __override struct keyboard_scan_config keyscan_config = {
 };
 
 static uint16_t scancode_set2_rgb[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = {
-	{0x0000, 0x0000, 0x0014, 0xe01f, 0xe014, 0xe007, 0x0000, 0x0000},
-	{0x001f, 0x0076, 0x0017, 0x000e, 0x001c, 0x003a, 0x000d, 0x0016},
-	{0x006c, 0x000c, 0x0004, 0x0006, 0x0005, 0xe071, 0x0026, 0x002a},
-	{0x0032, 0x0034, 0x002c, 0x002e, 0x002b, 0x0029, 0x0025, 0x002d},
-	{0x0078, 0x0009, 0x0083, 0x000b, 0x0003, 0x0041, 0x001e, 0x001d},
-	{0x0051, 0x0007, 0x005b, 0x0000, 0x0042, 0x0022, 0x003e, 0x0043},
-	{0x0031, 0x0033, 0x0035, 0x0036, 0x003b, 0x001b, 0x003d, 0x003c},
-	{0x0000, 0x0012, 0x0061, 0x0000, 0x0000, 0x0000, 0x0000, 0x0059},
-	{0x0055, 0x0052, 0x0054, 0x004e, 0x004c, 0x0024, 0x0044, 0x004d},
-	{0x0045, 0x0001, 0x000a, 0x002f, 0x004b, 0x0049, 0x0046, 0x001A},
-	{0xe011, 0x0000, 0x006a, 0x0000, 0x005d, 0x0000, 0x0011, 0x0000},
-	{0xe07a, 0x005d, 0xe075, 0x006b, 0x005a, 0xe072, 0x004a, 0x0066},
-	{0xe06b, 0xe074, 0xe069, 0x0067, 0xe0c6, 0x0064, 0x0015, 0xe07d},
-	{0x0073, 0x0066, 0xe071, 0x005d, 0x005a, 0xe04a, 0x0070, 0x0021},
-	{0x0023, 0xe05a, 0x0075, 0x0067, 0xe069, 0xe07a, 0x007d, 0x0069},
+	{ 0x0000, 0x0000, 0x0014, 0xe01f, 0xe014, 0xe007, 0x0000, 0x0000 },
+	{ 0x001f, 0x0076, 0x0017, 0x000e, 0x001c, 0x003a, 0x000d, 0x0016 },
+	{ 0x006c, 0x000c, 0x0004, 0x0006, 0x0005, 0xe071, 0x0026, 0x002a },
+	{ 0x0032, 0x0034, 0x002c, 0x002e, 0x002b, 0x0029, 0x0025, 0x002d },
+	{ 0x0078, 0x0009, 0x0083, 0x000b, 0x0003, 0x0041, 0x001e, 0x001d },
+	{ 0x0051, 0x0007, 0x005b, 0x0000, 0x0042, 0x0022, 0x003e, 0x0043 },
+	{ 0x0031, 0x0033, 0x0035, 0x0036, 0x003b, 0x001b, 0x003d, 0x003c },
+	{ 0x0000, 0x0012, 0x0061, 0x0000, 0x0000, 0x0000, 0x0000, 0x0059 },
+	{ 0x0055, 0x0052, 0x0054, 0x004e, 0x004c, 0x0024, 0x0044, 0x004d },
+	{ 0x0045, 0x0001, 0x000a, 0x002f, 0x004b, 0x0049, 0x0046, 0x001A },
+	{ 0xe011, 0x0000, 0x006a, 0x0000, 0x005d, 0x0000, 0x0011, 0x0000 },
+	{ 0xe07a, 0x005d, 0xe075, 0x006b, 0x005a, 0xe072, 0x004a, 0x0066 },
+	{ 0xe06b, 0xe074, 0xe069, 0x0067, 0xe0c6, 0x0064, 0x0015, 0xe07d },
+	{ 0x0073, 0x0066, 0xe071, 0x005d, 0x005a, 0xe04a, 0x0070, 0x0021 },
+	{ 0x0023, 0xe05a, 0x0075, 0x0067, 0xe069, 0xe07a, 0x007d, 0x0069 },
 };
 
 static void keyboard_matrix_init(void)
 {
 	CPRINTS("%s", __func__);
 
-	register_scancode_set2((uint16_t *) &scancode_set2_rgb,
-					sizeof(scancode_set2_rgb));
+	register_scancode_set2((uint16_t *)&scancode_set2_rgb,
+			       sizeof(scancode_set2_rgb));
 }
 DECLARE_HOOK(HOOK_INIT, keyboard_matrix_init, HOOK_PRIO_PRE_DEFAULT);
diff --git a/board/osiris/led.c b/board/osiris/led.c
index 7c4efdf93f..993c2969d4 100644
--- a/board/osiris/led.c
+++ b/board/osiris/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  * Power and battery LED control for osiris
@@ -21,23 +21,28 @@ __override const int led_charge_lvl_1 = 5;
 __override const int led_charge_lvl_2 = 95;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
diff --git a/board/osiris/pwm.c b/board/osiris/pwm.c
index 530a777a8f..eb178750e9 100644
--- a/board/osiris/pwm.c
+++ b/board/osiris/pwm.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,31 +11,11 @@
 #include "pwm_chip.h"
 
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 3,
-		.flags = 0,
-		/*
-		 * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent
-		 * flicker. Higher frequencies consume similar average power to
-		 * lower PWM frequencies, but higher frequencies record a much
-		 * lower maximum power.
-		 */
-		.freq = 25000,
-	},
-	[PWM_CH_FAN] = {
-		.channel = 5,
-		.flags = PWM_CONFIG_OPEN_DRAIN,
-		.freq = 25000
-	},
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
+	[PWM_CH_FAN2] = { .channel = 3,
+			  .flags = PWM_CONFIG_OPEN_DRAIN,
+			  .freq = 25000 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-static void board_pwm_init(void)
-{
-	/*
-	 * Turn on the fan at 50%.
-	 */
-	pwm_enable(PWM_CH_KBLIGHT, 1);
-	pwm_set_duty(PWM_CH_KBLIGHT, 50);
-}
-DECLARE_HOOK(HOOK_INIT, board_pwm_init, HOOK_PRIO_DEFAULT);
diff --git a/board/osiris/sensors.c b/board/osiris/sensors.c
index e02bee6a20..9ad528c069 100644
--- a/board/osiris/sensors.c
+++ b/board/osiris/sensors.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -63,30 +63,29 @@ const struct temp_sensor_t temp_sensors[] = {
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
 /*
- * TODO(b/234545460): update for Alder Lake/brya
- *
- * temperature limit, See thermal table in b/234545460#comment2
+ * Temperature limit, See thermal table in b/234545460#comment16
+ * For real temperature in fan control table, set temp_fan_off
+ * and temp_fan_max to 0 and 99.
  */
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CPU \
-	{ \
+#define THERMAL_CPU              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(78), \
-			[EC_TEMP_THRESH_HALT] = C_TO_K(90), \
+			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
 		}, \
 		.temp_host_release = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
 		}, \
-		.temp_fan_off = C_TO_K(25), \
-		.temp_fan_max = C_TO_K(89), \
+		.temp_fan_off = C_TO_K(0), \
+		.temp_fan_max = C_TO_K(99), \
 	}
 __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 
-
-#define THERMAL_UNUSED \
-	{ \
+#define THERMAL_UNUSED           \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = 0, \
 			[EC_TEMP_THRESH_HALT] = 0, \
diff --git a/board/osiris/usbc_config.c b/board/osiris/usbc_config.c
index 9a165ecdcc..d116e080ad 100644
--- a/board/osiris/usbc_config.c
+++ b/board/osiris/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -32,8 +32,8 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 /* USBC TCPC configuration */
 const struct tcpc_config_t tcpc_config[] = {
@@ -94,39 +94,48 @@ BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
 
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
-
 /*
  * USB3 MB/DB mux configuration - the top level mux still needs to be set
  * to the virtual_usb_mux_driver so the AP gets notified of mux changes
  * and updates the TCSS configuration on state changes.
  */
 
-static const struct usb_mux usbc0_usb3_mb_retimer = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+static const struct usb_mux_chain usbc0_usb3_mb_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 };
 
-static const struct usb_mux usbc1_usb3_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+static const struct usb_mux_chain usbc1_usb3_db_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 };
 
-const struct usb_mux usb_muxes[] = {
+const struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		/* PS8815 MB */
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc0_usb3_mb_retimer,
+		.mux = &(const struct usb_mux) {
+			/* PS8815 MB */
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc0_usb3_mb_retimer,
 	},
 	[USBC_PORT_C1] = {
-		/* PS8815 DB */
-		.usb_port = USBC_PORT_C1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc1_usb3_db_retimer,
+		.mux = &(const struct usb_mux) {
+			/* PS8815 DB */
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc1_usb3_db_retimer,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
@@ -144,7 +153,6 @@ const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
 
-
 #ifdef CONFIG_CHARGE_RAMP_SW
 
 /*
@@ -169,8 +177,8 @@ int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
 	}
 
 	if (voltage < BC12_MIN_VOLTAGE) {
-		CPRINTS("%s: port %d: vbus %d lower than %d", __func__,
-			port, voltage, BC12_MIN_VOLTAGE);
+		CPRINTS("%s: port %d: vbus %d lower than %d", __func__, port,
+			voltage, BC12_MIN_VOLTAGE);
 		return 1;
 	}
 
@@ -220,7 +228,6 @@ static void board_tcpc_init(void)
 	/* Enable BC1.2 interrupts. */
 	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
 	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
-
 }
 DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
 
diff --git a/board/osiris/usbc_config.h b/board/osiris/usbc_config.h
index 3ea16a6d56..dac4177f0c 100644
--- a/board/osiris/usbc_config.h
+++ b/board/osiris/usbc_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,14 +9,10 @@
 #define __CROS_EC_USBC_CONFIG_H
 
 #ifndef CONFIG_ZEPHYR
-#define CONFIG_USB_PD_PORT_MAX_COUNT	2
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
 #endif
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 void config_usb_db_type(void);
 
diff --git a/board/palkia/battery.c b/board/palkia/battery.c
index 76e58aa618..ed7efdb423 100644
--- a/board/palkia/battery.c
+++ b/board/palkia/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/palkia/board.c b/board/palkia/board.c
index cbf0e3178e..e0aab014a0 100644
--- a/board/palkia/board.c
+++ b/board/palkia/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -39,13 +39,12 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static const uint8_t actual_key_mask[KEYBOARD_COLS_MAX] = {
-	0x01, 0x68, 0xbd, 0x03, 0x7e, 0xff, 0xff,
-	0xff, 0xff, 0x03, 0xfd, 0x48, 0x03, 0xff,
-	0xf7, 0x16  /* full set */
+	0x01, 0x68, 0xbd, 0x03, 0x7e, 0xff, 0xff, 0xff,
+	0xff, 0x03, 0xfd, 0x48, 0x03, 0xff, 0xf7, 0x16 /* full set */
 };
 
 /* GPIO to enable/disable the USB Type-A port. */
@@ -119,16 +118,16 @@ static void board_lid_interrupt(enum gpio_signal signal)
 
 /******************************************************************************/
 /* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
+const struct spi_device_t spi_devices[] = {};
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
 /******************************************************************************/
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
 	[PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 },
-	[PWM_CH_FAN] = {.channel = 5, .flags = PWM_CONFIG_OPEN_DRAIN,
-			.freq = 25000},
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
@@ -145,11 +144,13 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	}
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_TCPC_0] = {
-		.usb_port = USB_PD_PORT_TCPC_0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_0,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 	},
 };
 
@@ -165,7 +166,7 @@ const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
 
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
@@ -184,40 +185,40 @@ const struct fan_t fans[FAN_CH_COUNT] = {
 /******************************************************************************/
 /* MFT channels. These are logically separate from pwm_channels. */
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN },
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		"TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_2] = {
-		"TEMP_5V_REG", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_3] = {
-		"TEMP_AMB", NPCX_ADC_CH3, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_4] = {
-		"TEMP_CPU", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_1] = { "TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_2] = { "TEMP_5V_REG", NPCX_ADC_CH1, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_3] = { "TEMP_AMB", NPCX_ADC_CH3, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_4] = { "TEMP_CPU", NPCX_ADC_CH2, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Temp1",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Temp2",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "Temp3",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_3},
-	[TEMP_SENSOR_4] = {.name = "Temp4",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_4},
+	[TEMP_SENSOR_1] = { .name = "Temp1",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Temp2",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "Temp3",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
+	[TEMP_SENSOR_4] = { .name = "Temp4",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_4 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -225,8 +226,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_A \
-	{ \
+#define THERMAL_A                \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = 0, \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
diff --git a/board/palkia/board.h b/board/palkia/board.h
index 783f01c444..d4de1aca39 100644
--- a/board/palkia/board.h
+++ b/board/palkia/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -46,7 +46,7 @@
  * Palkia' battery takes several seconds to come back out of its disconnect
  * state (~4.2 seconds on the unit I have, so give it a little more for margin).
  */
-#undef  CONFIG_POWER_BUTTON_INIT_TIMEOUT
+#undef CONFIG_POWER_BUTTON_INIT_TIMEOUT
 #define CONFIG_POWER_BUTTON_INIT_TIMEOUT 6
 
 /* BC 1.2 */
@@ -70,16 +70,16 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_AC_PRESENT		GPIO_ACOK_OD
-#define GPIO_PG_EC_RSMRST_ODL	GPIO_PG_EC_RSMRST_L
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_TEMP_SENSOR_POWER	GPIO_EN_A_RAILS
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L
+#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
 
 #ifndef __ASSEMBLER__
 
@@ -87,18 +87,14 @@
 #include "registers.h"
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_1,	/* ADC0 */
-	ADC_TEMP_SENSOR_2,	/* ADC1 */
-	ADC_TEMP_SENSOR_3,	/* ADC3 */
-	ADC_TEMP_SENSOR_4,	/* ADC2 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
+	ADC_TEMP_SENSOR_3, /* ADC3 */
+	ADC_TEMP_SENSOR_4, /* ADC2 */
 	ADC_CH_COUNT
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_FAN,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_FAN, PWM_CH_COUNT };
 
 enum fan_channel {
 	FAN_CH_0 = 0,
diff --git a/board/palkia/build.mk b/board/palkia/build.mk
index cf0939b776..3ad9efe889 100644
--- a/board/palkia/build.mk
+++ b/board/palkia/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/palkia/ec.tasklist b/board/palkia/ec.tasklist
index be39ae64a2..2a0d89d14e 100644
--- a/board/palkia/ec.tasklist
+++ b/board/palkia/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/palkia/gpio.inc b/board/palkia/gpio.inc
index ec7ce25538..dfe92f8a81 100644
--- a/board/palkia/gpio.inc
+++ b/board/palkia/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,10 +16,10 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(PG_EC_RSMRST_L,       PIN(E, 2), GPIO_INT_BOTH, intel_x86_rsmrst_signal_interrupt)
diff --git a/board/palkia/keyboard_customization.c b/board/palkia/keyboard_customization.c
index b39bf09f08..da69078c35 100644
--- a/board/palkia/keyboard_customization.c
+++ b/board/palkia/keyboard_customization.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,22 +12,22 @@
 #include "keyboard_raw.h"
 
 static uint16_t scancode_set2[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = {
-	{0x0021, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
-	{0x0000, 0x0000, 0x0000, 0x0011, 0x0000, 0x0000, 0x0000, 0x0000},
-	{0x0015, 0x0000, 0x0014, 0x000d, 0x000e, 0x0016, 0x0000, 0x001c},
-	{0xe011, 0x0011, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
-	{0x0000, 0x0029, 0x0024, 0x000c, 0xe01f, 0x0026, 0x0004, 0x0000},
-	{0x0022, 0x001a, 0x0006, 0x0005, 0x001b, 0x001e, 0x001d, 0x0076},
-	{0x002a, 0x0032, 0x0034, 0x002c, 0x002e, 0x0025, 0x002d, 0x002b},
-	{0x003a, 0x0031, 0x0033, 0x0035, 0x0036, 0x003d, 0x003c, 0x003b},
-	{0x0049, 0xe072, 0x005d, 0x0044, 0x0009, 0x0046, 0x0000, 0x004b},
-	{0x0059, 0x0012, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
-	{0x0041, 0x0000, 0x0083, 0x000b, 0x0003, 0x003e, 0x0043, 0x0042},
-	{0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x0000, 0xe06b, 0x0000},
-	{0xe014, 0x0014, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
-	{0x004a, 0xe075, 0x004e, 0x0000, 0x0045, 0x004d, 0x0054, 0x004c},
-	{0x0052, 0x005a, 0x0000, 0x0000, 0x0055, 0x0066, 0x005b, 0x0023},
-	{0x0000, 0x000a, 0xe074, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
+	{ 0x0021, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 },
+	{ 0x0000, 0x0000, 0x0000, 0x0011, 0x0000, 0x0000, 0x0000, 0x0000 },
+	{ 0x0015, 0x0000, 0x0014, 0x000d, 0x000e, 0x0016, 0x0000, 0x001c },
+	{ 0xe011, 0x0011, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 },
+	{ 0x0000, 0x0029, 0x0024, 0x000c, 0xe01f, 0x0026, 0x0004, 0x0000 },
+	{ 0x0022, 0x001a, 0x0006, 0x0005, 0x001b, 0x001e, 0x001d, 0x0076 },
+	{ 0x002a, 0x0032, 0x0034, 0x002c, 0x002e, 0x0025, 0x002d, 0x002b },
+	{ 0x003a, 0x0031, 0x0033, 0x0035, 0x0036, 0x003d, 0x003c, 0x003b },
+	{ 0x0049, 0xe072, 0x005d, 0x0044, 0x0009, 0x0046, 0x0000, 0x004b },
+	{ 0x0059, 0x0012, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 },
+	{ 0x0041, 0x0000, 0x0083, 0x000b, 0x0003, 0x003e, 0x0043, 0x0042 },
+	{ 0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x0000, 0xe06b, 0x0000 },
+	{ 0xe014, 0x0014, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 },
+	{ 0x004a, 0xe075, 0x004e, 0x0000, 0x0045, 0x004d, 0x0054, 0x004c },
+	{ 0x0052, 0x005a, 0x0000, 0x0000, 0x0055, 0x0066, 0x005b, 0x0023 },
+	{ 0x0000, 0x000a, 0xe074, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 },
 };
 
 uint16_t get_scancode_set2(uint8_t row, uint8_t col)
@@ -64,38 +64,30 @@ void board_keyboard_drive_col(int col)
 
 #ifdef CONFIG_KEYBOARD_DEBUG
 static char keycap_label[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = {
-	{'c',        KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
-		KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO},
-	{KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
-		KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO},
-	{'q',        KLLI_UNKNO, KLLI_UNKNO, KLLI_TAB,   '`',
-		'1',        KLLI_UNKNO, 'a'},
-	{KLLI_R_ALT, KLLI_L_ALT, KLLI_UNKNO, KLLI_UNKNO,
-		KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO},
-	{KLLI_UNKNO, KLLI_SPACE, 'e',        KLLI_F4,
-		KLLI_SEARC, '3',        KLLI_F3,    KLLI_UNKNO},
-	{'x',        'z',        KLLI_F2,    KLLI_F1,
-		's',        '2',        'w',        KLLI_ESC},
-	{'v',        'b',        'g',        't',
-		'5',        '4',        'r',        'f'},
-	{'m',        'n',        'h',        'y',
-		'6',        '7',        'u',        'j'},
-	{'.',        KLLI_DOWN,  '\\',       'o',
-		KLLI_F10,   '9',        KLLI_UNKNO, 'l'},
-	{KLLI_R_SHT, KLLI_L_SHT, KLLI_UNKNO, KLLI_UNKNO,
-		KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO},
-	{',',        KLLI_UNKNO, KLLI_F7,    KLLI_F6,
-		KLLI_F5,    '8',        'i',        'k'},
-	{KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_F9,
-		KLLI_UNKNO, KLLI_UNKNO, KLLI_LEFT,  KLLI_UNKNO},
-	{KLLI_R_CTR, KLLI_L_CTR, KLLI_UNKNO, KLLI_UNKNO,
-		KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO},
-	{'/',        KLLI_UP,    '-',        KLLI_UNKNO,
-		'0',        'p',        '[',        ';'},
-	{'\'',       KLLI_ENTER, KLLI_UNKNO, KLLI_UNKNO,
-		'=',        KLLI_B_SPC, ']',        'd'},
-	{KLLI_UNKNO, KLLI_F8,    KLLI_RIGHT, KLLI_UNKNO,
-		KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO},
+	{ 'c', KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO },
+	{ KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO },
+	{ 'q', KLLI_UNKNO, KLLI_UNKNO, KLLI_TAB, '`', '1', KLLI_UNKNO, 'a' },
+	{ KLLI_R_ALT, KLLI_L_ALT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO },
+	{ KLLI_UNKNO, KLLI_SPACE, 'e', KLLI_F4, KLLI_SEARC, '3', KLLI_F3,
+	  KLLI_UNKNO },
+	{ 'x', 'z', KLLI_F2, KLLI_F1, 's', '2', 'w', KLLI_ESC },
+	{ 'v', 'b', 'g', 't', '5', '4', 'r', 'f' },
+	{ 'm', 'n', 'h', 'y', '6', '7', 'u', 'j' },
+	{ '.', KLLI_DOWN, '\\', 'o', KLLI_F10, '9', KLLI_UNKNO, 'l' },
+	{ KLLI_R_SHT, KLLI_L_SHT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO },
+	{ ',', KLLI_UNKNO, KLLI_F7, KLLI_F6, KLLI_F5, '8', 'i', 'k' },
+	{ KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_F9, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_LEFT, KLLI_UNKNO },
+	{ KLLI_R_CTR, KLLI_L_CTR, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO },
+	{ '/', KLLI_UP, '-', KLLI_UNKNO, '0', 'p', '[', ';' },
+	{ '\'', KLLI_ENTER, KLLI_UNKNO, KLLI_UNKNO, '=', KLLI_B_SPC, ']', 'd' },
+	{ KLLI_UNKNO, KLLI_F8, KLLI_RIGHT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO },
 };
 
 char get_keycap_label(uint8_t row, uint8_t col)
diff --git a/board/palkia/keyboard_customization.h b/board/palkia/keyboard_customization.h
index 37ce1cf61f..fc97ffd728 100644
--- a/board/palkia/keyboard_customization.h
+++ b/board/palkia/keyboard_customization.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,47 +25,47 @@ extern uint8_t keyboard_cols;
 #define KEYBOARD_ROW_TO_MASK(r) (1 << (r))
 
 /* Columns and masks for keys we particularly care about */
-#define KEYBOARD_COL_DOWN	8
-#define KEYBOARD_ROW_DOWN	1
-#define KEYBOARD_MASK_DOWN	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_DOWN)
-#define KEYBOARD_COL_ESC	5
-#define KEYBOARD_ROW_ESC	7
-#define KEYBOARD_MASK_ESC	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_ESC)
-#define KEYBOARD_COL_KEY_H	7
-#define KEYBOARD_ROW_KEY_H	2
-#define KEYBOARD_MASK_KEY_H	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_H)
-#define KEYBOARD_COL_KEY_R	6
-#define KEYBOARD_ROW_KEY_R	6
-#define KEYBOARD_MASK_KEY_R	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_R)
-#define KEYBOARD_COL_LEFT_ALT	3
-#define KEYBOARD_ROW_LEFT_ALT	1
-#define KEYBOARD_MASK_LEFT_ALT	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_ALT)
-#define KEYBOARD_COL_REFRESH	4
-#define KEYBOARD_ROW_REFRESH	6
-#define KEYBOARD_MASK_REFRESH	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_REFRESH)
-#define KEYBOARD_COL_RIGHT_ALT	3
-#define KEYBOARD_ROW_RIGHT_ALT	0
-#define KEYBOARD_MASK_RIGHT_ALT	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_ALT)
-#define KEYBOARD_DEFAULT_COL_VOL_UP	8
-#define KEYBOARD_DEFAULT_ROW_VOL_UP	4
-#define KEYBOARD_COL_LEFT_CTRL  12
-#define KEYBOARD_ROW_LEFT_CTRL  1
+#define KEYBOARD_COL_DOWN 8
+#define KEYBOARD_ROW_DOWN 1
+#define KEYBOARD_MASK_DOWN KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_DOWN)
+#define KEYBOARD_COL_ESC 5
+#define KEYBOARD_ROW_ESC 7
+#define KEYBOARD_MASK_ESC KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_ESC)
+#define KEYBOARD_COL_KEY_H 7
+#define KEYBOARD_ROW_KEY_H 2
+#define KEYBOARD_MASK_KEY_H KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_H)
+#define KEYBOARD_COL_KEY_R 6
+#define KEYBOARD_ROW_KEY_R 6
+#define KEYBOARD_MASK_KEY_R KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_R)
+#define KEYBOARD_COL_LEFT_ALT 3
+#define KEYBOARD_ROW_LEFT_ALT 1
+#define KEYBOARD_MASK_LEFT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_ALT)
+#define KEYBOARD_COL_REFRESH 4
+#define KEYBOARD_ROW_REFRESH 6
+#define KEYBOARD_MASK_REFRESH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_REFRESH)
+#define KEYBOARD_COL_RIGHT_ALT 3
+#define KEYBOARD_ROW_RIGHT_ALT 0
+#define KEYBOARD_MASK_RIGHT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_ALT)
+#define KEYBOARD_DEFAULT_COL_VOL_UP 8
+#define KEYBOARD_DEFAULT_ROW_VOL_UP 4
+#define KEYBOARD_COL_LEFT_CTRL 12
+#define KEYBOARD_ROW_LEFT_CTRL 1
 #define KEYBOARD_MASK_LEFT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_CTRL)
 #define KEYBOARD_COL_RIGHT_CTRL 12
 #define KEYBOARD_ROW_RIGHT_CTRL 0
 #define KEYBOARD_MASK_RIGHT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_CTRL)
-#define KEYBOARD_COL_SEARCH     2
-#define KEYBOARD_ROW_SEARCH     3
-#define KEYBOARD_MASK_SEARCH    KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_SEARCH)
-#define KEYBOARD_COL_KEY_0      13
-#define KEYBOARD_ROW_KEY_0      4
-#define KEYBOARD_MASK_KEY_0     KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_0)
-#define KEYBOARD_COL_KEY_1      2
-#define KEYBOARD_ROW_KEY_1      5
-#define KEYBOARD_MASK_KEY_1     KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_1)
-#define KEYBOARD_COL_KEY_2      5
-#define KEYBOARD_ROW_KEY_2      5
-#define KEYBOARD_MASK_KEY_2     KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_2)
+#define KEYBOARD_COL_SEARCH 2
+#define KEYBOARD_ROW_SEARCH 3
+#define KEYBOARD_MASK_SEARCH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_SEARCH)
+#define KEYBOARD_COL_KEY_0 13
+#define KEYBOARD_ROW_KEY_0 4
+#define KEYBOARD_MASK_KEY_0 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_0)
+#define KEYBOARD_COL_KEY_1 2
+#define KEYBOARD_ROW_KEY_1 5
+#define KEYBOARD_MASK_KEY_1 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_1)
+#define KEYBOARD_COL_KEY_2 5
+#define KEYBOARD_ROW_KEY_2 5
+#define KEYBOARD_MASK_KEY_2 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_2)
 #define KEYBOARD_COL_LEFT_SHIFT 9
 #define KEYBOARD_ROW_LEFT_SHIFT 1
 #define KEYBOARD_MASK_LEFT_SHIFT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_SHIFT)
diff --git a/board/palkia/led.c b/board/palkia/led.c
index df74a38d52..f5242a04c0 100644
--- a/board/palkia/led.c
+++ b/board/palkia/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,29 +19,37 @@ __override const int led_charge_lvl_1 = 5;
 __override const int led_charge_lvl_2 = 95;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
 __override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	     3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	     3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    1 * LED_ONE_SEC },
+						  { LED_OFF,
+						    3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
 const enum ec_led_id supported_led_ids[] = {
 	EC_LED_ID_BATTERY_LED,
diff --git a/board/panqueque/board.c b/board/panqueque/board.c
index cea834c75e..786fe5f5aa 100644
--- a/board/panqueque/board.c
+++ b/board/panqueque/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -28,8 +28,8 @@
 #include "usb_tc_sm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
 #define QUICHE_PD_DEBUG_LVL 1
 
@@ -84,25 +84,25 @@ static void board_usbc_usb3_interrupt(enum gpio_signal signal)
  * signals is driven by USB/MST hub power sequencing requirements.
  */
 const struct power_seq board_power_seq[] = {
-	{GPIO_EN_AC_JACK,               1, 20},
-	{GPIO_EC_DFU_MUX_CTRL,          0, 0},
-	{GPIO_EN_PP5000_A,              1, 31},
-	{GPIO_MST_LP_CTL_L,             1, 0},
-	{GPIO_EN_PP3300_B,              1, 1},
-	{GPIO_EN_PP1100_A,              1, 100+30},
-	{GPIO_EN_BB,                    1, 30},
-	{GPIO_EN_PP1050_A,              1, 30},
-	{GPIO_EN_PP1200_A,              1, 20},
-	{GPIO_EN_PP5000_C,              1, 20},
-	{GPIO_EN_PP5000_HSPORT,         1, 31},
-	{GPIO_EN_DP_SINK,               1, 80},
-	{GPIO_MST_RST_L,                1, 61},
-	{GPIO_EC_HUB2_RESET_L,          1, 41},
-	{GPIO_EC_HUB3_RESET_L,          1, 33},
-	{GPIO_DP_SINK_RESET,            1, 100},
-	{GPIO_USBC_UF_RESET_L,          1, 33},
-	{GPIO_DEMUX_DP_HDMI_PD_N,       1, 10},
-	{GPIO_DEMUX_DP_HDMI_MODE,       1, 5},
+	{ GPIO_EN_AC_JACK, 1, 20 },
+	{ GPIO_EC_DFU_MUX_CTRL, 0, 0 },
+	{ GPIO_EN_PP5000_A, 1, 31 },
+	{ GPIO_MST_LP_CTL_L, 1, 0 },
+	{ GPIO_EN_PP3300_B, 1, 1 },
+	{ GPIO_EN_PP1100_A, 1, 100 + 30 },
+	{ GPIO_EN_BB, 1, 30 },
+	{ GPIO_EN_PP1050_A, 1, 30 },
+	{ GPIO_EN_PP1200_A, 1, 20 },
+	{ GPIO_EN_PP5000_C, 1, 20 },
+	{ GPIO_EN_PP5000_HSPORT, 1, 31 },
+	{ GPIO_EN_DP_SINK, 1, 80 },
+	{ GPIO_MST_RST_L, 1, 61 },
+	{ GPIO_EC_HUB2_RESET_L, 1, 41 },
+	{ GPIO_EC_HUB3_RESET_L, 1, 33 },
+	{ GPIO_DP_SINK_RESET, 1, 100 },
+	{ GPIO_USBC_UF_RESET_L, 1, 33 },
+	{ GPIO_DEMUX_DP_HDMI_PD_N, 1, 10 },
+	{ GPIO_DEMUX_DP_HDMI_MODE, 1, 5 },
 };
 const size_t board_power_seq_count = ARRAY_SIZE(board_power_seq);
 
@@ -110,13 +110,13 @@ const size_t board_power_seq_count = ARRAY_SIZE(board_power_seq);
  * Define the strings used in our USB descriptors.
  */
 const void *const usb_strings[] = {
-	[USB_STR_DESC]         = usb_string_desc,
-	[USB_STR_VENDOR]       = USB_STRING_DESC("Plugable"),
-	[USB_STR_PRODUCT]      = USB_STRING_DESC("UC-MSTHDC"),
-	[USB_STR_SERIALNO]     = 0,
-	[USB_STR_VERSION]      =
-			USB_STRING_DESC(CROS_EC_SECTION ":" CROS_EC_VERSION32),
-	[USB_STR_UPDATE_NAME]  = USB_STRING_DESC("Firmware update"),
+	[USB_STR_DESC] = usb_string_desc,
+	[USB_STR_VENDOR] = USB_STRING_DESC("Plugable"),
+	[USB_STR_PRODUCT] = USB_STRING_DESC("UC-MSTHDC"),
+	[USB_STR_SERIALNO] = 0,
+	[USB_STR_VERSION] =
+		USB_STRING_DESC(CROS_EC_SECTION ":" CROS_EC_VERSION32),
+	[USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"),
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
 
@@ -135,8 +135,7 @@ struct ppc_config_t ppc_chips[] = {
  * PS8802 set mux board tuning.
  * Adds in board specific gain and DP lane count configuration
  */
-static int board_ps8822_mux_set(const struct usb_mux *me,
-				mux_state_t mux_state)
+static int board_ps8822_mux_set(const struct usb_mux *me, mux_state_t mux_state)
 {
 	int rv = EC_SUCCESS;
 
@@ -155,28 +154,26 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_HOST] = {
-		.usb_port = USB_PD_PORT_HOST,
-		.i2c_port = I2C_PORT_I2C1,
-		.i2c_addr_flags = PS8822_I2C_ADDR3_FLAG,
-		.driver = &ps8822_usb_mux_driver,
-		.board_set = &board_ps8822_mux_set,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_HOST,
+			.i2c_port = I2C_PORT_I2C1,
+			.i2c_addr_flags = PS8822_I2C_ADDR3_FLAG,
+			.driver = &ps8822_usb_mux_driver,
+			.board_set = &board_ps8822_mux_set,
+		},
 	},
 };
 
 /* USB-C PPC Configuration */
 struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_HOST] = {
-		.i2c_port = I2C_PORT_I2C1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	[USB_PD_PORT_USB3] = {
-		.i2c_port = I2C_PORT_I2C3,
-		.i2c_addr_flags = SN5S330_ADDR1_FLAGS,
-		.drv = &sn5s330_drv
-	},
+	[USB_PD_PORT_HOST] = { .i2c_port = I2C_PORT_I2C1,
+			       .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+			       .drv = &sn5s330_drv },
+	[USB_PD_PORT_USB3] = { .i2c_port = I2C_PORT_I2C3,
+			       .i2c_addr_flags = SN5S330_ADDR1_FLAGS,
+			       .drv = &sn5s330_drv },
 };
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
@@ -284,14 +281,13 @@ static void board_usb_tc_disconnect(void)
 	if (port == USB_PD_PORT_HOST)
 		gpio_set_level(GPIO_UFP_PLUG_DET, 1);
 }
-DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, board_usb_tc_disconnect,\
+DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, board_usb_tc_disconnect,
 	     HOOK_PRIO_DEFAULT);
 
 #endif /* SECTION_IS_RW */
 
 static void board_init(void)
 {
-
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
@@ -328,7 +324,7 @@ void board_debug_gpio(enum debug_gpio trigger, int level, int pulse_usec)
 	}
 }
 
-static int command_dplane(int argc, char **argv)
+static int command_dplane(int argc, const char **argv)
 {
 	char *e;
 	int lane;
@@ -356,6 +352,4 @@ static int command_dplane(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(dplane, command_dplane,
-			"<2 | 4>",
-			"MST lane control.");
+DECLARE_CONSOLE_COMMAND(dplane, command_dplane, "<2 | 4>", "MST lane control.");
diff --git a/board/panqueque/board.h b/board/panqueque/board.h
index 39aed68f8e..24eeebabe5 100644
--- a/board/panqueque/board.h
+++ b/board/panqueque/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,8 +21,8 @@
 #undef CONFIG_FLASH_PSTATE_LOCKED
 
 /* USB Type C and USB PD defines */
-#define USB_PD_PORT_HOST   0
-#define USB_PD_PORT_USB3   1
+#define USB_PD_PORT_HOST 0
+#define USB_PD_PORT_USB3 1
 
 /*
  * Only the host and display usbc ports are usb-pd capable. There is a 2nd usbc
@@ -40,9 +40,9 @@
 #define CONFIG_USB_PD_IDENTITY_SW_VERS 1
 
 /* I2C port names */
-#define I2C_PORT_I2C1	0
-#define I2C_PORT_I2C2	1
-#define I2C_PORT_I2C3	2
+#define I2C_PORT_I2C1 0
+#define I2C_PORT_I2C2 1
+#define I2C_PORT_I2C3 2
 
 /* Required symbolic I2C port names */
 #define I2C_PORT_MP4245 I2C_PORT_I2C3
@@ -68,7 +68,7 @@
 #define GPIO_TRIGGER_1 GPIO_USB3_A5_CDP_EN
 #define GPIO_TRIGGER_2 GPIO_USB3_A6_CDP_EN
 
-enum  debug_gpio {
+enum debug_gpio {
 	TRIGGER_1 = 0,
 	TRIGGER_2,
 };
diff --git a/board/panqueque/build.mk b/board/panqueque/build.mk
index 49775523af..8f9795eca9 100644
--- a/board/panqueque/build.mk
+++ b/board/panqueque/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/panqueque/ec.tasklist b/board/panqueque/ec.tasklist
index 7a67fce776..7bd8acaa5f 100644
--- a/board/panqueque/ec.tasklist
+++ b/board/panqueque/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/panqueque/gpio.inc b/board/panqueque/gpio.inc
index fa1b900c82..4fd80ec754 100644
--- a/board/panqueque/gpio.inc
+++ b/board/panqueque/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2022 The Chromium OS Authors. All rights reserved.
+ * Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/pazquel/battery.c b/board/pazquel/battery.c
index e1415f5682..bd600aed5b 100644
--- a/board/pazquel/battery.c
+++ b/board/pazquel/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/pazquel/board.c b/board/pazquel/board.c
index d3568a4bcb..90dcc6cd0d 100644
--- a/board/pazquel/board.c
+++ b/board/pazquel/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,8 +10,10 @@
 #include "charge_manager.h"
 #include "charge_state.h"
 #include "extpower.h"
+#include "driver/accel_kionix.h"
 #include "driver/accel_bma2x2.h"
 #include "driver/accelgyro_bmi_common.h"
+#include "driver/accelgyro_bmi323.h"
 #include "driver/ppc/sn5s330.h"
 #include "driver/tcpm/ps8xxx.h"
 #include "driver/tcpm/tcpci.h"
@@ -33,8 +35,8 @@
 #include "usbc_ocp.h"
 #include "usbc_ppc.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* Forward declaration */
 static void tcpc_alert_event(enum gpio_signal signal);
@@ -127,10 +129,8 @@ __override struct keyboard_scan_config keyscan_config = {
 	 * 2. T11 key not in keyboard (KSI_0,KSO_1):
 	 *    change actual_key_mask[1] from 0xff to 0xfe
 	 */
-	 .actual_key_mask = {
-         0x1c, 0xfe, 0xff, 0xff, 0xff, 0xf5, 0xff,
-	 0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca
-	 },
+	.actual_key_mask = { 0x1c, 0xfe, 0xff, 0xff, 0xff, 0xf5, 0xff, 0xa4,
+			     0xff, 0xfe, 0x55, 0xfa, 0xca },
 	/* Other values should be the same as the default configuration. */
 	.debounce_down_us = 9 * MSEC,
 	.debounce_up_us = 30 * MSEC,
@@ -141,41 +141,31 @@ __override struct keyboard_scan_config keyscan_config = {
 
 /* I2C port map */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl  = GPIO_EC_I2C_POWER_SCL,
-		.sda  = GPIO_EC_I2C_POWER_SDA
-	},
-	{
-		.name = "tcpc0",
-		.port = I2C_PORT_TCPC0,
-		.kbps = 1000,
-		.scl  = GPIO_EC_I2C_USB_C0_PD_SCL,
-		.sda  = GPIO_EC_I2C_USB_C0_PD_SDA
-	},
-	{
-		.name = "tcpc1",
-		.port = I2C_PORT_TCPC1,
-		.kbps = 1000,
-		.scl  = GPIO_EC_I2C_USB_C1_PD_SCL,
-		.sda  = GPIO_EC_I2C_USB_C1_PD_SDA
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_EEPROM_SCL,
-		.sda  = GPIO_EC_I2C_EEPROM_SDA
-	},
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_SENSOR_SCL,
-		.sda  = GPIO_EC_I2C_SENSOR_SDA
-	},
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_POWER_SCL,
+	  .sda = GPIO_EC_I2C_POWER_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C0_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C0_PD_SDA },
+	{ .name = "tcpc1",
+	  .port = I2C_PORT_TCPC1,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C1_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C1_PD_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_EEPROM_SCL,
+	  .sda = GPIO_EC_I2C_EEPROM_SDA },
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_SENSOR_SCL,
+	  .sda = GPIO_EC_I2C_SENSOR_SDA },
 };
 
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
@@ -183,58 +173,39 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* Measure VBUS through a 1/10 voltage divider */
-	[ADC_VBUS] = {
-		"VBUS",
-		NPCX_ADC_CH1,
-		ADC_MAX_VOLT * 10,
-		ADC_READ_MAX + 1,
-		0
-	},
+	[ADC_VBUS] = { "VBUS", NPCX_ADC_CH1, ADC_MAX_VOLT * 10,
+		       ADC_READ_MAX + 1, 0 },
 	/*
 	 * Adapter current output or battery charging/discharging current (uV)
 	 * 18x amplification on charger side.
 	 */
-	[ADC_AMON_BMON] = {
-		"AMON_BMON",
-		NPCX_ADC_CH2,
-		ADC_MAX_VOLT * 1000 / 18,
-		ADC_READ_MAX + 1,
-		0
-	},
+	[ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH2, ADC_MAX_VOLT * 1000 / 18,
+			    ADC_READ_MAX + 1, 0 },
 	/*
 	 * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read
 	 * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and
 	 * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we
 	 * only divide by 2 (enough to avoid precision issues).
 	 */
-	[ADC_PSYS] = {
-		"PSYS",
-		NPCX_ADC_CH3,
-		ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1),
-		2,
-		0
-	},
+	[ADC_PSYS] = { "PSYS", NPCX_ADC_CH3,
+		       ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), 2, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 },	
+	[PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 },
 	[PWM_CH_DISPLIGHT] = { .channel = 5, .flags = 0, .freq = 20000 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
 /* Power Path Controller */
 struct ppc_config_t ppc_chips[] = {
-	{
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	{
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
+	{ .i2c_port = I2C_PORT_TCPC0,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
+	{ .i2c_port = I2C_PORT_TCPC1,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
 };
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
@@ -265,16 +236,22 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
  * to AP. But the TCPC chip is also needed to know the HPD status; otherwise,
  * the mux misbehaves.
  */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	},
 	{
-		.usb_port = 1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	}
 };
 
@@ -293,19 +270,6 @@ const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
 		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
 	},
 };
-
-static void board_update_sensor_config_clamshell(void)
-{
-	motion_sensor_count = 0;
-	gmr_tablet_switch_disable();
-	/* The sensors are not stuffed; don't allow lines to float */
-	gpio_set_flags(GPIO_ACCEL_GYRO_INT_L,
-		       GPIO_INPUT | GPIO_PULL_DOWN);
-	gpio_set_flags(GPIO_LID_ACCEL_INT_L,
-		       GPIO_INPUT | GPIO_PULL_DOWN);
-}
-DECLARE_HOOK(HOOK_INIT, board_update_sensor_config_clamshell,
-	     HOOK_PRIO_INIT_I2C + 2);
 /* Initialize board. */
 static void board_init(void)
 {
@@ -352,9 +316,19 @@ void board_tcpc_init(void)
 	 */
 	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
 		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+	/*
+	 * Pazquel/pazquel360 share the same firmware ,only pazquel360 has
+	 * volume keys. So disable volume keys for pazquel board
+	 */
+	if (!board_has_side_volume_buttons()) {
+		button_disable_gpio(BUTTON_VOLUME_UP);
+		button_disable_gpio(BUTTON_VOLUME_DOWN);
+		gpio_set_flags(GPIO_VOLUME_DOWN_L, GPIO_INPUT | GPIO_PULL_DOWN);
+		gpio_set_flags(GPIO_VOLUME_UP_L, GPIO_INPUT | GPIO_PULL_DOWN);
+	}
 }
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
 
 static void da9313_pvc_mode_ctrl(int enable)
 {
@@ -364,12 +338,12 @@ static void da9313_pvc_mode_ctrl(int enable)
 	 */
 	if (enable)
 		i2c_update8(I2C_PORT_POWER, DA9313_I2C_ADDR_FLAGS,
-			    DA9313_REG_PVC_CTRL,
-			    DA9313_PVC_CTRL_PVC_MODE, MASK_SET);
+			    DA9313_REG_PVC_CTRL, DA9313_PVC_CTRL_PVC_MODE,
+			    MASK_SET);
 	else
 		i2c_update8(I2C_PORT_POWER, DA9313_I2C_ADDR_FLAGS,
-			    DA9313_REG_PVC_CTRL,
-			    DA9313_PVC_CTRL_PVC_MODE, MASK_CLR);
+			    DA9313_REG_PVC_CTRL, DA9313_PVC_CTRL_PVC_MODE,
+			    MASK_CLR);
 }
 
 void da9313_init(void)
@@ -377,7 +351,7 @@ void da9313_init(void)
 	/* PVC operates in fixed frequency mode in S0. */
 	da9313_pvc_mode_ctrl(0);
 }
-DECLARE_HOOK(HOOK_INIT, da9313_init, HOOK_PRIO_DEFAULT+1);
+DECLARE_HOOK(HOOK_INIT, da9313_init, HOOK_PRIO_DEFAULT + 1);
 
 void board_hibernate(void)
 {
@@ -387,10 +361,8 @@ void board_hibernate(void)
 	 * Sensors are unpowered in hibernate. Apply PD to the
 	 * interrupt lines such that they don't float.
 	 */
-	gpio_set_flags(GPIO_ACCEL_GYRO_INT_L,
-		       GPIO_INPUT | GPIO_PULL_DOWN);
-	gpio_set_flags(GPIO_LID_ACCEL_INT_L,
-		       GPIO_INPUT | GPIO_PULL_DOWN);
+	gpio_set_flags(GPIO_ACCEL_GYRO_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
+	gpio_set_flags(GPIO_LID_ACCEL_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
 
 	/*
 	 * Enable the PPC power sink path before EC enters hibernate;
@@ -435,8 +407,23 @@ static void board_shutdown_complete(void)
 	}
 }
 DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN_COMPLETE, board_shutdown_complete,
-		HOOK_PRIO_DEFAULT);
+	     HOOK_PRIO_DEFAULT);
 
+__override uint32_t board_get_sku_id(void)
+{
+	static int sku_id = -1;
+
+	if (sku_id == -1) {
+		int bits[3];
+
+		bits[0] = gpio_get_ternary(GPIO_SKU_ID0);
+		bits[1] = gpio_get_ternary(GPIO_SKU_ID1);
+		bits[2] = gpio_get_ternary(GPIO_SKU_ID2);
+		sku_id = binary_first_base3_from_bits(bits, ARRAY_SIZE(bits));
+	}
+
+	return (uint32_t)sku_id;
+}
 
 void board_set_switchcap_power(int enable)
 {
@@ -495,8 +482,7 @@ void board_overcurrent_event(int port, int is_overcurrented)
 
 int board_set_active_charge_port(int port)
 {
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	int i;
 
 	if (!is_real_port && port != CHARGE_PORT_NONE)
@@ -524,7 +510,6 @@ int board_set_active_charge_port(int port)
 		return EC_ERROR_INVAL;
 	}
 
-
 	CPRINTS("New charge port: p%d", port);
 
 	/*
@@ -548,23 +533,21 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	/*
 	 * Ignore lower charge ceiling on PD transition if our battery is
 	 * critical, as we may brownout.
 	 */
-	if (supplier == CHARGE_SUPPLIER_PD &&
-	    charge_ma < 1500 &&
+	if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 &&
 	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
 		CPRINTS("Using max ilim %d", max_ma);
 		charge_ma = max_ma;
 	}
 
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 uint16_t tcpc_get_alert_status(void)
@@ -585,94 +568,157 @@ uint16_t tcpc_get_alert_status(void)
 static struct mutex g_base_mutex;
 static struct mutex g_lid_mutex;
 
-static struct bmi_drv_data_t g_bmi160_data;
-static struct accelgyro_saved_data_t g_bma255_data;
-
 /* Matrix to rotate accelerometer into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0,  0},
-	{ 0,  FLOAT_TO_FP(-1),  0},
-	{ 0,  0, FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+				       { 0, FLOAT_TO_FP(-1), 0 },
+				       { 0, 0, FLOAT_TO_FP(-1) } };
 
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static struct kionix_accel_data g_kx022_data;
 
+static const mat33_fp_t lid_standard_ref_kx022 = { { FLOAT_TO_FP(1), 0, 0 },
+						   { 0, FLOAT_TO_FP(1), 0 },
+						   { 0, 0, FLOAT_TO_FP(-1) } };
+
+static struct bmi_drv_data_t g_bmi_data;
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
-	 .name = "Lid Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMA255,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_LID,
-	 .drv = &bma2x2_accel_drv,
-	 .mutex = &g_lid_mutex,
-	 .drv_data = &g_bma255_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-	 .rot_standard_ref = &lid_standard_ref,
-	 .default_range = 2, /* g, to support lid angle calculation. */
-	 .min_frequency = BMA255_ACCEL_MIN_FREQ,
-	 .max_frequency = BMA255_ACCEL_MAX_FREQ,
-	 .config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 10000 | ROUND_UP_FLAG,
-		},
-		/* Sensor on for lid angle detection */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 10000 | ROUND_UP_FLAG,
+		.name = "Lid Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_KX022,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_LID,
+		.drv = &kionix_accel_drv,
+		.mutex = &g_lid_mutex,
+		.drv_data = &g_kx022_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = KX022_ADDR1_FLAGS,
+		.rot_standard_ref = &lid_standard_ref_kx022,
+		.default_range = 2, /* g */
+		/* We only use 2g because its resolution is only 8-bits */
+		.min_frequency = KX022_ACCEL_MIN_FREQ,
+		.max_frequency = KX022_ACCEL_MAX_FREQ,
+		.config = {
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 10000 | ROUND_UP_FLAG,
+			},
 		},
-	 },
 	},
 	/*
-	 * Note: bmi160: supports accelerometer and gyro sensor
+	 * Note: bmi232: supports accelerometer and gyro sensor
 	 * Requirement: accelerometer sensor must init before gyro sensor
 	 * DO NOT change the order of the following table.
 	 */
 	[BASE_ACCEL] = {
-	 .name = "Base Accel",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_ACCEL,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .rot_standard_ref = &base_standard_ref,
-	 .default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
-	 .min_frequency = BMI_ACCEL_MIN_FREQ,
-	 .max_frequency = BMI_ACCEL_MAX_FREQ,
-	 .config = {
-		 [SENSOR_CONFIG_EC_S0] = {
-			 .odr = 10000 | ROUND_UP_FLAG,
-		 },
-		 /* Sensor on for lid angle detection */
-		 [SENSOR_CONFIG_EC_S3] = {
-			 .odr = 10000 | ROUND_UP_FLAG,
-		 },
-	 },
+		.name = "Base Accel",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMI323,
+		.type = MOTIONSENSE_TYPE_ACCEL,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &bmi3xx_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = &g_bmi_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMI3_ADDR_I2C_PRIM,
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = BMI_ACCEL_MIN_FREQ,
+		.max_frequency = BMI_ACCEL_MAX_FREQ,
+		.default_range = 4,  /* g, to meet CDD 7.3.1/C-1-4 reqs */
+		.config = {
+			/* EC use accel for angle detection */
+			[SENSOR_CONFIG_EC_S0] = {
+				.odr = 12500 | ROUND_UP_FLAG,
+				.ec_rate = 100 * MSEC,
+			},
+			/* Sensor on in S3 */
+			[SENSOR_CONFIG_EC_S3] = {
+				.odr = 12500 | ROUND_UP_FLAG,
+				.ec_rate = 0,
+			},
+		},
 	},
 	[BASE_GYRO] = {
-	 .name = "Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI160,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi160_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi160_data,
-	 .port = I2C_PORT_SENSOR,
-	 .i2c_spi_addr_flags = BMI160_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &base_standard_ref,
-	 .min_frequency = BMI_GYRO_MIN_FREQ,
-	 .max_frequency = BMI_GYRO_MAX_FREQ,
+		.name = "Base Gyro",
+		.active_mask = SENSOR_ACTIVE_S0_S3,
+		.chip = MOTIONSENSE_CHIP_BMI323,
+		.type = MOTIONSENSE_TYPE_GYRO,
+		.location = MOTIONSENSE_LOC_BASE,
+		.drv = &bmi3xx_drv,
+		.mutex = &g_base_mutex,
+		.drv_data = &g_bmi_data,
+		.port = I2C_PORT_SENSOR,
+		.i2c_spi_addr_flags = BMI3_ADDR_I2C_PRIM,
+		.default_range = 1000, /* dps */
+		.rot_standard_ref = &base_standard_ref,
+		.min_frequency = BMI_GYRO_MIN_FREQ,
+		.max_frequency = BMI_GYRO_MAX_FREQ,
 	},
 };
 unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
+
+static void board_update_sensor_config_from_sku(void)
+{
+	if (board_is_clamshell()) {
+		motion_sensor_count = 0;
+		gmr_tablet_switch_disable();
+		/* The sensors are not stuffed; don't allow lines to float */
+		gpio_set_flags(GPIO_ACCEL_GYRO_INT_L,
+			       GPIO_INPUT | GPIO_PULL_DOWN);
+		gpio_set_flags(GPIO_LID_ACCEL_INT_L,
+			       GPIO_INPUT | GPIO_PULL_DOWN);
+	} else {
+		motion_sensor_count = ARRAY_SIZE(motion_sensors);
+		/* Enable interrupt for the base accel sensor */
+		gpio_enable_interrupt(GPIO_ACCEL_GYRO_INT_L);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, board_update_sensor_config_from_sku,
+	     HOOK_PRIO_INIT_I2C + 2);
+
+static uint8_t sku_id;
+
+enum board_model {
+	PAZQUEL,
+	PAZQUEL360,
+	UNKNOWN,
+};
+
+static const char *const model_name[] = {
+	"PAZQUEL",
+	"PAZQUEL360",
+	"UNKNOWN",
+};
+
+static enum board_model get_model(void)
+{
+	if (sku_id == 0 || sku_id == 1 || sku_id == 2 || sku_id == 3 ||
+	    sku_id == 4 || sku_id == 5 || sku_id == 6)
+		return PAZQUEL;
+	if (sku_id >= 8)
+		return PAZQUEL360;
+	return UNKNOWN;
+}
+
+int board_is_clamshell(void)
+{
+	return get_model() == PAZQUEL;
+}
+
+/* Read SKU ID from GPIO and initialize variables for board variants */
+static void sku_init(void)
+{
+	sku_id = system_get_sku_id();
+	CPRINTS("SKU: %u (%s)", sku_id, model_name[get_model()]);
+}
+DECLARE_HOOK(HOOK_INIT, sku_init, HOOK_PRIO_INIT_I2C + 1);
+
+int board_has_side_volume_buttons(void)
+{
+	return get_model() == PAZQUEL360;
+}
+__override int mkbp_support_volume_buttons(void)
+{
+	return board_has_side_volume_buttons();
+}
diff --git a/board/pazquel/board.h b/board/pazquel/board.h
index dc80fc9829..414c8ab7dd 100644
--- a/board/pazquel/board.h
+++ b/board/pazquel/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,7 +11,7 @@
 #include "baseboard.h"
 
 /* Internal SPI flash on NPCX7 */
-#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)  /* 512KB internal spi flash */
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */
 
 /* Keyboard */
 #define CONFIG_KEYBOARD_PROTOCOL_MKBP
@@ -37,19 +37,16 @@
 #define USB_PORT_COUNT 1
 #define CONFIG_USB_PORT_POWER_DUMB
 
-/* No side volume button */
-#undef CONFIG_VOLUME_BUTTONS
-
 /* Sensors */
 #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-/* BMI160 Base accel/gyro */
-#define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
+/* BMI323 Base accel/gyro */
+#define CONFIG_ACCELGYRO_BMI3XX
+#define CONFIG_ACCELGYRO_BMI3XX_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 #define OPT3001_I2C_ADDR_FLAGS OPT3001_I2C_ADDR1_FLAGS
 
-/* BMA253 lid accel */
-#define CONFIG_ACCEL_BMA255
+/* KX022 lid accel */
+#define CONFIG_ACCEL_KX022
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
 
 #define CONFIG_LID_ANGLE
@@ -72,17 +69,14 @@
 #define DA9313_PVC_CTRL_PVC_MODE BIT(1)
 #define DA9313_PVC_CTRL_PVC_EN BIT(0)
 
+/* Button Config*/
+#define CONFIG_BUTTONS_RUNTIME_CONFIG
 #ifndef __ASSEMBLER__
 
 #include "gpio_signal.h"
 #include "registers.h"
 
-enum adc_channel {
-	ADC_VBUS,
-	ADC_AMON_BMON,
-	ADC_PSYS,
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_VBUS, ADC_AMON_BMON, ADC_PSYS, ADC_CH_COUNT };
 
 /* Motion sensors */
 enum sensor_id {
@@ -92,11 +86,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_DISPLIGHT,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_DISPLIGHT, PWM_CH_COUNT };
 
 enum battery_type {
 	BATTERY_GANFENG,
@@ -106,6 +96,8 @@ enum battery_type {
 /* Reset all TCPCs. */
 void board_reset_pd_mcu(void);
 void board_set_tcpc_power_mode(int port, int mode);
+int board_is_clamshell(void);
+int board_has_side_volume_buttons(void);
 
 #endif /* !defined(__ASSEMBLER__) */
 
diff --git a/board/pazquel/build.mk b/board/pazquel/build.mk
index f130540bd4..3bc07db568 100644
--- a/board/pazquel/build.mk
+++ b/board/pazquel/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/pazquel/ec.tasklist b/board/pazquel/ec.tasklist
index 5beeb38feb..228828af3c 100644
--- a/board/pazquel/ec.tasklist
+++ b/board/pazquel/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/pazquel/gpio.inc b/board/pazquel/gpio.inc
index 4ebd09b4ee..8d9a2827bc 100644
--- a/board/pazquel/gpio.inc
+++ b/board/pazquel/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,6 +21,8 @@ GPIO_INT(USB_A0_OC_ODL,        PIN(D, 1), GPIO_INT_BOTH | GPIO_PULL_UP, usba_oc_
 GPIO_INT(CHG_ACOK_OD,       PIN(0, 0), GPIO_INT_BOTH, extpower_interrupt)  /* ACOK */
 GPIO_INT(CCD_MODE_ODL,      PIN(E, 3), GPIO_INT_FALLING, board_connect_c0_sbu)  /* Case Closed Debug Mode */
 GPIO_INT(EC_PWR_BTN_ODL,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)  /* Power button */
+GPIO_INT(EC_VOLDN_BTN_ODL,  PIN(7, 0), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Down button */
+GPIO_INT(EC_VOLUP_BTN_ODL,  PIN(F, 2), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* Volume Up button */
 GPIO_INT(EC_WP_ODL,         PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)  /* Write protection */
 GPIO_INT(LID_OPEN_EC,       PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)  /* Lid open */
 GPIO_INT(AP_RST_L,          PIN(C, 1), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_ap_rst_interrupt)  /* PMIC to signal AP reset */
@@ -39,7 +41,7 @@ GPIO_INT(AP_EC_SPI_CS_L,    PIN(5, 3), GPIO_INT_FALLING | GPIO_PULL_DOWN, shi_cs
 
 /* Sensor interrupts */
 GPIO_INT(TABLET_MODE_L,     PIN(C, 6), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-GPIO_INT(ACCEL_GYRO_INT_L,  PIN(A, 0), GPIO_INT_FALLING, bmi160_interrupt)  /* Accelerometer/gyro interrupt */
+GPIO_INT(ACCEL_GYRO_INT_L,  PIN(A, 0), GPIO_INT_FALLING, bmi3xx_interrupt)  /* Accelerometer/gyro interrupt */
 
 /*
  * EC_RST_ODL used to be a wake source from PSL mode. However, we disabled
@@ -157,8 +159,6 @@ UNUSED(PIN(8, 3))
 UNUSED(PIN(B, 1))
 UNUSED(PIN(5, 0))
 UNUSED(PIN(D, 3))
-UNUSED(PIN(7, 0))
-UNUSED(PIN(F, 2))
 
 /* Alternate functions GPIO definitions */
 ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)            /* UART (GPIO64/65) */
diff --git a/board/pazquel/led.c b/board/pazquel/led.c
index aabf33f3f0..180e9829f5 100644
--- a/board/pazquel/led.c
+++ b/board/pazquel/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -31,15 +31,15 @@ enum led_color {
 	LED_OFF = 0,
 	LED_RED,
 	LED_BLUE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static void led_set_color(enum led_color color)
 {
 	gpio_set_level(GPIO_EC_CHG_LED_Y_C1,
-		(color == LED_RED) ? BAT_LED_ON : BAT_LED_OFF);
+		       (color == LED_RED) ? BAT_LED_ON : BAT_LED_OFF);
 	gpio_set_level(GPIO_EC_CHG_LED_W_C1,
-		(color == LED_BLUE) ? BAT_LED_ON : BAT_LED_OFF);
+		       (color == LED_BLUE) ? BAT_LED_ON : BAT_LED_OFF);
 }
 
 void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
@@ -65,7 +65,6 @@ static void board_led_set_battery(void)
 	static int battery_ticks;
 	enum led_color color = LED_OFF;
 	int period = 0;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
@@ -105,16 +104,16 @@ static void board_led_set_battery(void)
 		color = LED_BLUE;
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE) {
-			/* Factory mode: Blue 2 sec, Red 2 sec */
-			period = (2 + 2) * LED_ONE_SEC;
-			battery_ticks = battery_ticks % period;
-			if (battery_ticks < 2 * LED_ONE_SEC)
-				color = LED_BLUE;
-			else
-				color = LED_RED;
-		} else
+		color = LED_BLUE;
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		/* Factory mode: Blue 2 sec, Red 2 sec */
+		period = (2 + 2) * LED_ONE_SEC;
+		battery_ticks = battery_ticks % period;
+		if (battery_ticks < 2 * LED_ONE_SEC)
 			color = LED_BLUE;
+		else
+			color = LED_RED;
 		break;
 	default:
 		/* Other states don't alter LED behavior */
diff --git a/board/pazquel/usbc_config.c b/board/pazquel/usbc_config.c
index aac136415d..5d30adb6e2 100644
--- a/board/pazquel/usbc_config.c
+++ b/board/pazquel/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,8 @@
 #include "console.h"
 #include "usb_pd.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 const struct charger_config_t chg_chips[] = {
 	{
diff --git a/board/pdeval-stm32f072/PD_evaluation.md b/board/pdeval-stm32f072/PD_evaluation.md
index 4f1c8636c6..fd4763a849 100644
--- a/board/pdeval-stm32f072/PD_evaluation.md
+++ b/board/pdeval-stm32f072/PD_evaluation.md
@@ -43,12 +43,12 @@ also need to create/delete the corresponding `PD_Cx` tasks in
 [board/pdeval-stm32f072/ec.tasklist](ec.tasklist).
 
 By default, the firmware is using I2C1 with SCL/SDA on pins PB6 and PB7, running
-with a 100kHz clock, and tries to talk to TCPCs at i2c slave addresses 0x9c and
+with a 100kHz clock, and tries to talk to TCPCs at i2c target addresses 0x9c and
 0x9e. To change the pins or speed, you need to edit `i2c_ports` in
 [board/pdeval-stm32f072/board.c](board.c), update `I2C_PORT_TCPC` in
 [board/pdeval-stm32f072/board.h](board.h) with the right controller number, and
 change the pin mux in [board/pdeval-stm32f072/gpio.inc](gpio.inc). To change
-TCPC i2c slave addresses, update `TCPC1_I2C_ADDR` and `TCPC2_I2C_ADDR` in
+TCPC i2c target addresses, update `TCPC1_I2C_ADDR` and `TCPC2_I2C_ADDR` in
 [board/pdeval-stm32f072/board.h](board.h).
 
 The I2C bus needs pull-up resistors on SCL/SDA. If your setup doesn't have
diff --git a/board/pdeval-stm32f072/board.c b/board/pdeval-stm32f072/board.c
index 525f14a4af..e1e75bcea7 100644
--- a/board/pdeval-stm32f072/board.c
+++ b/board/pdeval-stm32f072/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -30,10 +30,10 @@ void alert_event(enum gpio_signal signal)
 #include "gpio_list.h"
 
 const void *const usb_strings[] = {
-	[USB_STR_DESC]         = usb_string_desc,
-	[USB_STR_VENDOR]       = USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]      = USB_STRING_DESC("PDeval-stm32f072"),
-	[USB_STR_VERSION]      = USB_STRING_DESC(CROS_EC_VERSION32),
+	[USB_STR_DESC] = usb_string_desc,
+	[USB_STR_VENDOR] = USB_STRING_DESC("Google LLC"),
+	[USB_STR_PRODUCT] = USB_STRING_DESC("PDeval-stm32f072"),
+	[USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32),
 	[USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Shell"),
 };
 
@@ -52,15 +52,11 @@ void board_reset_pd_mcu(void)
 }
 
 /* I2C ports */
-const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "tcpc",
-		.port = I2C_PORT_TCPC,
-		.kbps = 400 /* kHz */,
-		.scl  = GPIO_I2C0_SCL,
-		.sda  = GPIO_I2C0_SDA
-	}
-};
+const struct i2c_port_t i2c_ports[] = { { .name = "tcpc",
+					  .port = I2C_PORT_TCPC,
+					  .kbps = 400 /* kHz */,
+					  .scl = GPIO_I2C0_SCL,
+					  .sda = GPIO_I2C0_SDA } };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
 const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
diff --git a/board/pdeval-stm32f072/board.h b/board/pdeval-stm32f072/board.h
index c075772e9f..4cb55573f4 100644
--- a/board/pdeval-stm32f072/board.h
+++ b/board/pdeval-stm32f072/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,6 +15,8 @@
 #undef CONFIG_UART_CONSOLE
 #define CONFIG_UART_CONSOLE 2
 
+#define CONFIG_LTO
+
 /* Optional features */
 #define CONFIG_HW_CRC
 #define CONFIG_I2C
@@ -32,6 +34,7 @@
 #define CONFIG_USB_PD_VBUS_DETECT_TCPC
 #define CONFIG_USB_PD_TCPM_ANX7447
 #define CONFIG_USB_PD_TCPM_MUX
+#define CONFIG_USBC_SS_MUX
 
 #undef CONFIG_USB_PD_INITIAL_DRP_STATE
 #define CONFIG_USB_PD_INITIAL_DRP_STATE PD_DRP_TOGGLE_ON
@@ -40,14 +43,14 @@
 #define CONFIG_USB_PD_PULLUP TYPEC_RP_USB
 
 /* fake board specific type-C power constants */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 650000 /* us */
 
 /* Define typical operating power and max power */
 #define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       60000
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_VOLTAGE_MV     20000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* I2C master port connected to the TCPC */
 #define I2C_PORT_TCPC 0
@@ -66,12 +69,12 @@
 
 /* USB interface indexes (use define rather than enum to expand them) */
 #define USB_IFACE_CONSOLE 0
-#define USB_IFACE_COUNT   1
+#define USB_IFACE_COUNT 1
 
 /* USB endpoint indexes (use define rather than enum to expand them) */
 #define USB_EP_CONTROL 0
 #define USB_EP_CONSOLE 1
-#define USB_EP_COUNT   2
+#define USB_EP_COUNT 2
 
 /* Remove console commands / features for flash / RAM savings */
 #undef CONFIG_WATCHDOG_HELP
diff --git a/board/pdeval-stm32f072/build.mk b/board/pdeval-stm32f072/build.mk
index 30d5bf8ac8..2238f8f59a 100644
--- a/board/pdeval-stm32f072/build.mk
+++ b/board/pdeval-stm32f072/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/pdeval-stm32f072/ec.tasklist b/board/pdeval-stm32f072/ec.tasklist
index 5003fc7ba1..e897969a55 100644
--- a/board/pdeval-stm32f072/ec.tasklist
+++ b/board/pdeval-stm32f072/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/pdeval-stm32f072/gpio.inc b/board/pdeval-stm32f072/gpio.inc
index 5409077c34..fb8537ffbe 100644
--- a/board/pdeval-stm32f072/gpio.inc
+++ b/board/pdeval-stm32f072/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/pdeval-stm32f072/openocd-flash.cfg b/board/pdeval-stm32f072/openocd-flash.cfg
index ec32416934..05a697acf8 100644
--- a/board/pdeval-stm32f072/openocd-flash.cfg
+++ b/board/pdeval-stm32f072/openocd-flash.cfg
@@ -1,4 +1,4 @@
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
+# Copyright 2014 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/board/pdeval-stm32f072/usb_pd_pdo.c b/board/pdeval-stm32f072/usb_pd_pdo.c
index 442e708923..31d84f9785 100644
--- a/board/pdeval-stm32f072/usb_pd_pdo.c
+++ b/board/pdeval-stm32f072/usb_pd_pdo.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/pdeval-stm32f072/usb_pd_pdo.h b/board/pdeval-stm32f072/usb_pd_pdo.h
index 58fd1f153c..13640a7471 100644
--- a/board/pdeval-stm32f072/usb_pd_pdo.h
+++ b/board/pdeval-stm32f072/usb_pd_pdo.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/pdeval-stm32f072/usb_pd_policy.c b/board/pdeval-stm32f072/usb_pd_policy.c
index b7425ce66c..9ea36a1b0d 100644
--- a/board/pdeval-stm32f072/usb_pd_policy.c
+++ b/board/pdeval-stm32f072/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,18 +17,21 @@
 #include "usb_pd.h"
 #include "usb_pd_pdo.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 /* Used to fake VBUS presence since no GPIO is available to read VBUS */
 static int vbus_present;
 
-
 #if defined(CONFIG_USB_PD_TCPM_MUX) && defined(CONFIG_USB_PD_TCPM_ANX7447)
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.driver    = &anx7447_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &anx7447_usb_mux_driver,
+				.hpd_update = &anx7447_tcpc_update_hpd_status,
+			},
 	},
 };
 #endif
@@ -81,8 +84,8 @@ void pd_power_supply_reset(int port)
 void pd_set_input_current_limit(int port, uint32_t max_ma,
 				uint32_t supply_voltage)
 {
-	CPRINTS("USBPD current limit port %d max %d mA %d mV",
-		port, max_ma, supply_voltage);
+	CPRINTS("USBPD current limit port %d max %d mA %d mV", port, max_ma,
+		supply_voltage);
 	/* do some LED coding of the power we can sink */
 	if (max_ma) {
 		if (supply_voltage > 6500)
@@ -98,8 +101,8 @@ void pd_set_input_current_limit(int port, uint32_t max_ma,
 __override void typec_set_input_current_limit(int port, uint32_t max_ma,
 					      uint32_t supply_voltage)
 {
-	CPRINTS("TYPEC current limit port %d max %d mA %d mV",
-		port, max_ma, supply_voltage);
+	CPRINTS("TYPEC current limit port %d max %d mA %d mV", port, max_ma,
+		supply_voltage);
 	gpio_set_level(GPIO_LED_R, !!max_ma);
 }
 
@@ -109,24 +112,21 @@ void button_event(enum gpio_signal signal)
 	CPRINTS("VBUS %d", vbus_present);
 }
 
-static int command_vbus_toggle(int argc, char **argv)
+static int command_vbus_toggle(int argc, const char **argv)
 {
 	vbus_present = !vbus_present;
 	CPRINTS("VBUS %d", vbus_present);
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(vbus, command_vbus_toggle,
-			"",
-			"Toggle VBUS detected");
+DECLARE_CONSOLE_COMMAND(vbus, command_vbus_toggle, "", "Toggle VBUS detected");
 
 int pd_snk_is_vbus_provided(int port)
 {
 	return vbus_present;
 }
 
-__override int pd_check_data_swap(int port,
-				  enum pd_data_role data_role)
+__override int pd_check_data_swap(int port, enum pd_data_role data_role)
 {
 	/* Always allow data swap */
 	return 1;
@@ -144,22 +144,18 @@ int pd_check_vconn_swap(int port)
 }
 #endif
 
-__override void pd_check_pr_role(int port,
-				 enum pd_power_role pr_role,
+__override void pd_check_pr_role(int port, enum pd_power_role pr_role,
 				 int flags)
 {
 }
 
-__override void pd_check_dr_role(int port,
-				 enum pd_data_role dr_role,
-				 int flags)
+__override void pd_check_dr_role(int port, enum pd_data_role dr_role, int flags)
 {
 }
 /* ----------------- Vendor Defined Messages ------------------ */
 const uint32_t vdo_idh = VDO_IDH(1, /* data caps as USB host */
 				 0, /* data caps as USB device */
-				 IDH_PTYPE_PERIPH,
-				 0, /* supports alt modes */
+				 IDH_PTYPE_PERIPH, 0, /* supports alt modes */
 				 0x0000);
 
 const uint32_t vdo_product = VDO_PRODUCT(0x0000, 0x0000);
@@ -193,87 +189,62 @@ __override int svdm_dp_config(int port, uint32_t *payload)
 {
 	int opos = pd_alt_mode(port, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT);
 	int pin_mode = pd_dfp_dp_get_pin_mode(port, dp_status[port]);
-	bool unused;
-#if defined(CONFIG_USB_PD_TCPM_MUX) && defined(CONFIG_USB_PD_TCPM_ANX7447)
-	const struct usb_mux *mux = &usb_muxes[port];
-#endif
-
-#ifdef CONFIG_USB_PD_TCPM_ANX7447
 	mux_state_t mux_state = USB_PD_MUX_NONE;
-	if (polarity_rm_dts(pd_get_polarity(port)))
-		mux_state |= USB_PD_MUX_POLARITY_INVERTED;
-#endif
 
 	CPRINTS("pin_mode = %d", pin_mode);
 	if (!pin_mode)
 		return 0;
 
-#if defined(CONFIG_USB_PD_TCPM_MUX) && defined(CONFIG_USB_PD_TCPM_ANX7447)
 	switch (pin_mode) {
 	case MODE_DP_PIN_A:
 	case MODE_DP_PIN_C:
 	case MODE_DP_PIN_E:
 		mux_state |= USB_PD_MUX_DP_ENABLED;
-		/*
-		 * Note: Direct mux driver calls are deprecated.  Calls
-		 * should go through the usb_mux APIs instead.
-		 */
-		mux->driver->set(mux, mux_state, &unused);
 		break;
 	case MODE_DP_PIN_B:
 	case MODE_DP_PIN_D:
 	case MODE_DP_PIN_F:
 		mux_state |= USB_PD_MUX_DOCK;
-		mux->driver->set(mux, mux_state, &unused);
 		break;
 	}
-#endif
+	usb_mux_set(port, mux_state, USB_SWITCH_CONNECT,
+		    polarity_rm_dts(pd_get_polarity(port)));
 
 	/*
 	 * board_set_usb_mux(port, USB_PD_MUX_DP_ENABLED,
 	 * polarity_rm_dts(pd_get_polarity(port)));
 	 */
-	payload[0] = VDO(USB_SID_DISPLAYPORT, 1,
-			 CMD_DP_CONFIG | VDO_OPOS(opos));
+	payload[0] =
+		VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_CONFIG | VDO_OPOS(opos));
 	payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */
-				1,             /* DPv1.3 signaling */
-				2);            /* UFP connected */
+				1, /* DPv1.3 signaling */
+				2); /* UFP connected */
 	return 2;
 }
 
 __override void svdm_dp_post_config(int port)
 {
-	bool unused;
-	const struct usb_mux *mux = &usb_muxes[port];
-
 	dp_flags[port] |= DP_FLAGS_DP_ON;
 	if (!(dp_flags[port] & DP_FLAGS_HPD_HI_PENDING))
 		return;
 
-	/* Note: Usage is deprecated, use usb_mux_hpd_update instead */
-	if (IS_ENABLED(CONFIG_USB_PD_TCPM_ANX7447))
-		anx7447_tcpc_update_hpd_status(mux, USB_PD_MUX_HPD_LVL |
-					       USB_PD_MUX_HPD_IRQ_DEASSERTED,
-					       &unused);
+	usb_mux_hpd_update(port,
+			   USB_PD_MUX_HPD_LVL | USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
 
 __override int svdm_dp_attention(int port, uint32_t *payload)
 {
-#ifdef CONFIG_USB_PD_TCPM_ANX7447
 	int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]);
 	int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]);
-	const struct usb_mux *mux = &usb_muxes[port];
-	bool unused;
 
-	mux_state_t mux_state = (lvl ? USB_PD_MUX_HPD_LVL :
-				 USB_PD_MUX_HPD_LVL_DEASSERTED) |
-				(irq ? USB_PD_MUX_HPD_IRQ :
-				 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+	mux_state_t mux_state =
+		(lvl ? USB_PD_MUX_HPD_LVL : USB_PD_MUX_HPD_LVL_DEASSERTED) |
+		(irq ? USB_PD_MUX_HPD_IRQ : USB_PD_MUX_HPD_IRQ_DEASSERTED);
 
 	/* Note: Usage is deprecated, use usb_mux_hpd_update instead */
 	CPRINTS("Attention: 0x%x", payload[1]);
-	anx7447_tcpc_update_hpd_status(mux, mux_state, &unused);
-#endif
+	usb_mux_hpd_update(port, mux_state);
+
 	dp_status[port] = payload[1];
 
 	/* ack */
@@ -282,8 +253,7 @@ __override int svdm_dp_attention(int port, uint32_t *payload)
 
 __override void svdm_exit_dp_mode(int port)
 {
-#ifdef CONFIG_USB_PD_TCPM_ANX7447
-	anx7447_tcpc_clear_hpd_status(port);
-#endif
+	usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
+					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
 #endif /* CONFIG_USB_PD_ALT_MODE_DFP */
diff --git a/board/phaser/battery.c b/board/phaser/battery.c
index 2e1f77d552..25a0fbce92 100644
--- a/board/phaser/battery.c
+++ b/board/phaser/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/phaser/board.c b/board/phaser/board.c
index 6259ad3cd7..6ebaab0b4a 100644
--- a/board/phaser/board.c
+++ b/board/phaser/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,6 +6,7 @@
 /* Phaser board-specific configuration */
 
 #include "adc.h"
+#include "builtin/stdnoreturn.h"
 #include "button.h"
 #include "charge_state.h"
 #include "common.h"
@@ -34,11 +35,11 @@
 #include "util.h"
 #include "battery_smart.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define USB_PD_PORT_ANX7447	0
-#define USB_PD_PORT_PS8751	1
+#define USB_PD_PORT_ANX7447 0
+#define USB_PD_PORT_PS8751 1
 
 static uint8_t sku_id;
 static bool support_syv_ppc;
@@ -85,31 +86,31 @@ static void ppc_interrupt(enum gpio_signal signal)
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_AMB] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_AMB] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				  ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_CHARGER] = { "TEMP_CHARGER", NPCX_ADC_CH1,
+				      ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 },
 	/* Vbus sensing (1/10 voltage divider). */
-	[ADC_VBUS_C0] = {
-		"VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
-	[ADC_VBUS_C1] = {
-		"VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
+	[ADC_VBUS_C0] = { "VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT * 10,
+			  ADC_READ_MAX + 1, 0 },
+	[ADC_VBUS_C1] = { "VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT * 10,
+			  ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp,
-				 .idx = 0},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
+	[TEMP_SENSOR_BATTERY] = { .name = "Battery",
+				  .type = TEMP_SENSOR_TYPE_BATTERY,
+				  .read = charge_get_battery_temp,
+				  .idx = 0 },
+	[TEMP_SENSOR_AMBIENT] = { .name = "Ambient",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_51k1_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_AMB },
+	[TEMP_SENSOR_CHARGER] = { .name = "Charger",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_13k7_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_CHARGER },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -119,11 +120,9 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrix to rotate lid and base sensor into standard reference frame */
-const mat33_fp_t standard_rot_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
+const mat33_fp_t standard_rot_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				      { 0, FLOAT_TO_FP(-1), 0 },
+				      { 0, 0, FLOAT_TO_FP(1) } };
 
 /* sensor private data */
 static struct stprivate_data g_lis2dh_data;
@@ -212,8 +211,8 @@ unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
 static int board_is_convertible(void)
 {
-	return sku_id == 2 || sku_id == 3 || sku_id == 4 || sku_id == 5 || \
-		sku_id == 255;
+	return sku_id == 2 || sku_id == 3 || sku_id == 4 || sku_id == 5 ||
+	       sku_id == 255;
 }
 
 static void board_update_sensor_config_from_sku(void)
@@ -331,7 +330,7 @@ void board_hibernate_late(void)
 	}
 
 	/* Clear all pending IRQ otherwise wfi will have no affect */
-	for (i = NPCX_IRQ_0 ; i < NPCX_IRQ_COUNT ; i++)
+	for (i = NPCX_IRQ_0; i < NPCX_IRQ_COUNT; i++)
 		task_clear_pending_irq(i);
 
 	__enter_hibernate_in_psl();
@@ -358,11 +357,11 @@ int board_is_lid_angle_tablet_mode(void)
 }
 
 /* Battery functions */
-#define SB_OPTIONALMFG_FUNCTION2		0x3e
+#define SB_OPTIONALMFG_FUNCTION2 0x3e
 /* Optional mfg function2 */
-#define SMART_QUICK_CHARGE			(1<<12)
+#define SMART_QUICK_CHARGE (1 << 12)
 /* Quick charge support */
-#define MODE_QUICK_CHARGE_SUPPORT		(1<<4)
+#define MODE_QUICK_CHARGE_SUPPORT (1 << 4)
 
 static void sb_quick_charge_mode(int enable)
 {
@@ -411,15 +410,15 @@ void board_overcurrent_event(int port, int is_overcurrented)
 }
 
 static const struct ppc_config_t ppc_syv682x_port0 = {
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
+	.i2c_port = I2C_PORT_TCPC0,
+	.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+	.drv = &syv682x_drv,
 };
 
 static const struct ppc_config_t ppc_syv682x_port1 = {
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv,
+	.i2c_port = I2C_PORT_TCPC1,
+	.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+	.drv = &syv682x_drv,
 };
 
 static void board_setup_ppc(void)
@@ -427,12 +426,10 @@ static void board_setup_ppc(void)
 	if (!support_syv_ppc)
 		return;
 
-	memcpy(&ppc_chips[USB_PD_PORT_TCPC_0],
-		&ppc_syv682x_port0,
-		sizeof(struct ppc_config_t));
-	memcpy(&ppc_chips[USB_PD_PORT_TCPC_1],
-		&ppc_syv682x_port1,
-		sizeof(struct ppc_config_t));
+	memcpy(&ppc_chips[USB_PD_PORT_TCPC_0], &ppc_syv682x_port0,
+	       sizeof(struct ppc_config_t));
+	memcpy(&ppc_chips[USB_PD_PORT_TCPC_1], &ppc_syv682x_port1,
+	       sizeof(struct ppc_config_t));
 
 	gpio_set_flags(GPIO_USB_PD_C0_INT_ODL, GPIO_INT_BOTH);
 	gpio_set_flags(GPIO_USB_PD_C1_INT_ODL, GPIO_INT_BOTH);
diff --git a/board/phaser/board.h b/board/phaser/board.h
index a03782b245..54f3cf3b32 100644
--- a/board/phaser/board.h
+++ b/board/phaser/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -44,8 +44,8 @@
 #define CONFIG_CMD_ACCEL_INFO
 
 /* Sensors */
-#define CONFIG_ACCEL_LIS2DE             /* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM        /* Base accel */
+#define CONFIG_ACCEL_LIS2DE /* Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
 /* Sensors without hardware FIFO are in forced mode */
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
 
@@ -60,8 +60,8 @@
 
 /* Additional PPC second source */
 #define CONFIG_USBC_PPC_SYV682X
-#define	CONFIG_USBC_PPC_DEDICATED_INT
-#undef	CONFIG_SYV682X_HV_ILIM
+#define CONFIG_USBC_PPC_DEDICATED_INT
+#undef CONFIG_SYV682X_HV_ILIM
 #define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_5_50
 /* SYV682 isn't connected to CC, so TCPC must provide VCONN */
 #define CONFIG_USBC_PPC_SYV682X_NO_CC
@@ -72,10 +72,10 @@
 #include "registers.h"
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_AMB,		/* ADC0 */
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC1 */
-	ADC_VBUS_C0,			/* ADC9 */
-	ADC_VBUS_C1,			/* ADC4 */
+	ADC_TEMP_SENSOR_AMB, /* ADC0 */
+	ADC_TEMP_SENSOR_CHARGER, /* ADC1 */
+	ADC_VBUS_C0, /* ADC9 */
+	ADC_VBUS_C1, /* ADC4 */
 	ADC_CH_COUNT,
 };
 
@@ -86,18 +86,10 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_COUNT };
 
 /* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
diff --git a/board/phaser/build.mk b/board/phaser/build.mk
index 3d04b75731..998a65a3de 100644
--- a/board/phaser/build.mk
+++ b/board/phaser/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/phaser/ec.tasklist b/board/phaser/ec.tasklist
index d98db145e7..977b8b01be 100644
--- a/board/phaser/ec.tasklist
+++ b/board/phaser/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/phaser/gpio.inc b/board/phaser/gpio.inc
index 639ed914b6..c6d2be7fc6 100644
--- a/board/phaser/gpio.inc
+++ b/board/phaser/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/phaser/led.c b/board/phaser/led.c
index cce1c3289e..998b948804 100644
--- a/board/phaser/led.c
+++ b/board/phaser/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,32 +19,35 @@ __override const int led_charge_lvl_1 = 5;
 __override const int led_charge_lvl_2 = 97;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
 
 __override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-					{LED_OFF,	   0.5 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 3 * LED_ONE_SEC },
+					       { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-	EC_LED_ID_BATTERY_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED,
+					     EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
diff --git a/board/pico/battery.c b/board/pico/battery.c
index 6f6b49899a..5e1671f5f3 100644
--- a/board/pico/battery.c
+++ b/board/pico/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/pico/board.c b/board/pico/board.c
index 093a34d54d..f884545b6d 100644
--- a/board/pico/board.c
+++ b/board/pico/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -28,6 +28,7 @@
 #include "i2c.h"
 #include "keyboard_scan.h"
 #include "lid_switch.h"
+#include "panic.h"
 #include "power.h"
 #include "power_button.h"
 #include "registers.h"
@@ -43,8 +44,8 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 #include "gpio_list.h"
 
@@ -55,17 +56,13 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Rotation matrixes */
-static const mat33_fp_t lid_standard_ref = {
-	{FLOAT_TO_FP(1), 0, 0},
-	{0, FLOAT_TO_FP(-1), 0},
-	{0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
-static const mat33_fp_t base_standard_ref = {
-	{FLOAT_TO_FP(1), 0, 0},
-	{0, FLOAT_TO_FP(1), 0},
-	{0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, FLOAT_TO_FP(1), 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
 
 /* sensor private data */
 static struct kionix_accel_data g_kx022_data;
@@ -171,18 +168,21 @@ int board_sensor_at_360(void)
  * The connector has 24 pins total, and there is no pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-	{-1, -1}, {GPIO_KSO_H, 4}, {GPIO_KSO_H, 0}, {GPIO_KSO_H, 1},
-	{GPIO_KSO_H, 3}, {GPIO_KSO_H, 2}, {-1, -1}, {-1, -1},
-	{GPIO_KSO_L, 5}, {GPIO_KSO_L, 6}, {-1, -1}, {GPIO_KSO_L, 3},
-	{GPIO_KSO_L, 2}, {GPIO_KSI, 0}, {GPIO_KSO_L, 1}, {GPIO_KSO_L, 4},
-	{GPIO_KSI, 3}, {GPIO_KSI, 2}, {GPIO_KSO_L, 0}, {GPIO_KSI, 5},
-	{GPIO_KSI, 4}, {GPIO_KSO_L, 7}, {GPIO_KSI, 6}, {GPIO_KSI, 7},
-	{GPIO_KSI, 1}, {-1, -1}, {GPIO_KSO_H, 5}, {-1, -1},
-	{GPIO_KSO_H, 6}, {-1, -1}, {-1, -1},
+	{ -1, -1 },	   { GPIO_KSO_H, 4 }, { GPIO_KSO_H, 0 },
+	{ GPIO_KSO_H, 1 }, { GPIO_KSO_H, 3 }, { GPIO_KSO_H, 2 },
+	{ -1, -1 },	   { -1, -1 },	      { GPIO_KSO_L, 5 },
+	{ GPIO_KSO_L, 6 }, { -1, -1 },	      { GPIO_KSO_L, 3 },
+	{ GPIO_KSO_L, 2 }, { GPIO_KSI, 0 },   { GPIO_KSO_L, 1 },
+	{ GPIO_KSO_L, 4 }, { GPIO_KSI, 3 },   { GPIO_KSI, 2 },
+	{ GPIO_KSO_L, 0 }, { GPIO_KSI, 5 },   { GPIO_KSI, 4 },
+	{ GPIO_KSO_L, 7 }, { GPIO_KSI, 6 },   { GPIO_KSI, 7 },
+	{ GPIO_KSI, 1 },   { -1, -1 },	      { GPIO_KSO_H, 5 },
+	{ -1, -1 },	   { GPIO_KSO_H, 6 }, { -1, -1 },
+	{ -1, -1 },
 };
 
 const int keyboard_factory_scan_pins_used =
-		ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 
 /* Wake-up pins for hibernate */
 const enum gpio_signal hibernate_wake_pins[] = {
@@ -195,39 +195,33 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 /******************************************************************************/
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] = {"BOARD_ID", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0,
-				CHIP_ADC_CH1},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0,
-				CHIP_ADC_CH2},
-	[ADC_VBUS] = {"VBUS", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0,
-				CHIP_ADC_CH0},
+	[ADC_BOARD_ID] = { "BOARD_ID", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0,
+			   CHIP_ADC_CH1 },
+	[ADC_EC_SKU_ID] = { "EC_SKU_ID", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0,
+			    CHIP_ADC_CH2 },
+	[ADC_VBUS] = { "VBUS", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0,
+		       CHIP_ADC_CH0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /******************************************************************************/
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "typec",
-		.port = IT83XX_I2C_CH_C,
-		.kbps = 400,
-		.scl  = GPIO_I2C_C_SCL,
-		.sda  = GPIO_I2C_C_SDA
-	},
-	{
-		.name = "sensor",
-		.port = IT83XX_I2C_CH_B,
-		.kbps = 400,
-		.scl  = GPIO_I2C_B_SCL,
-		.sda  = GPIO_I2C_B_SDA
-	},
-	{
-		.name = "battery",
-		.port = IT83XX_I2C_CH_A,
-		.kbps = 100,
-		.scl  = GPIO_I2C_A_SCL,
-		.sda  = GPIO_I2C_A_SDA
-	},
+	{ .name = "typec",
+	  .port = IT83XX_I2C_CH_C,
+	  .kbps = 400,
+	  .scl = GPIO_I2C_C_SCL,
+	  .sda = GPIO_I2C_C_SDA },
+	{ .name = "sensor",
+	  .port = IT83XX_I2C_CH_B,
+	  .kbps = 400,
+	  .scl = GPIO_I2C_B_SCL,
+	  .sda = GPIO_I2C_B_SDA },
+	{ .name = "battery",
+	  .port = IT83XX_I2C_CH_A,
+	  .kbps = 100,
+	  .scl = GPIO_I2C_A_SCL,
+	  .sda = GPIO_I2C_A_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -235,8 +229,8 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
 /* power signal list.  Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
+	{ GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" },
+	{ GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" },
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
@@ -259,8 +253,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-static void board_hpd_status(const struct usb_mux *me,
-			     mux_state_t mux_state,
+static void board_hpd_status(const struct usb_mux *me, mux_state_t mux_state,
 			     bool *ack_required)
 {
 	/* This driver does not use host command ACKs */
@@ -273,13 +266,16 @@ static void board_hpd_status(const struct usb_mux *me,
 	host_set_single_event(EC_HOST_EVENT_USB_MUX);
 }
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+				.hpd_update = &board_hpd_status,
+			},
 	},
 };
 
@@ -324,12 +320,12 @@ int board_set_active_charge_port(int charge_port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-			       CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 int board_discharge_on_ac(int enable)
@@ -401,8 +397,7 @@ static void board_motion_init(void)
 		/* Disable tablet mode. */
 		tablet_set_mode(0, TABLET_TRIGGER_LID);
 		gmr_tablet_switch_disable();
-		gpio_set_flags(GPIO_TABLET_MODE_L,
-				GPIO_INPUT | GPIO_PULL_UP);
+		gpio_set_flags(GPIO_TABLET_MODE_L, GPIO_INPUT | GPIO_PULL_UP);
 	}
 }
 DECLARE_HOOK(HOOK_INIT, board_motion_init, HOOK_PRIO_DEFAULT + 1);
diff --git a/board/pico/board.h b/board/pico/board.h
index 6e1fe1d964..665cf59691 100644
--- a/board/pico/board.h
+++ b/board/pico/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -50,7 +50,7 @@
 /* Motion Sensors */
 #ifndef VARIANT_KUKUI_NO_SENSORS
 #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-#define CONFIG_ACCEL_KX022      /* Lid accel */
+#define CONFIG_ACCEL_KX022 /* Lid accel */
 #define CONFIG_ACCELGYRO_BMI160 /* Base accel */
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
@@ -68,14 +68,14 @@
 #endif /* !VARIANT_KUKUI_NO_SENSORS */
 
 /* I2C ports */
-#define I2C_PORT_BC12               IT83XX_I2C_CH_C
-#define I2C_PORT_TCPC0              IT83XX_I2C_CH_C
-#define I2C_PORT_USB_MUX            IT83XX_I2C_CH_C
-#define I2C_PORT_CHARGER            IT83XX_I2C_CH_A
-#define I2C_PORT_SENSORS            IT83XX_I2C_CH_B
-#define I2C_PORT_ACCEL              I2C_PORT_SENSORS
-#define I2C_PORT_BATTERY            IT83XX_I2C_CH_A
-#define I2C_PORT_VIRTUAL_BATTERY    I2C_PORT_BATTERY
+#define I2C_PORT_BC12 IT83XX_I2C_CH_C
+#define I2C_PORT_TCPC0 IT83XX_I2C_CH_C
+#define I2C_PORT_USB_MUX IT83XX_I2C_CH_C
+#define I2C_PORT_CHARGER IT83XX_I2C_CH_A
+#define I2C_PORT_SENSORS IT83XX_I2C_CH_B
+#define I2C_PORT_ACCEL I2C_PORT_SENSORS
+#define I2C_PORT_BATTERY IT83XX_I2C_CH_A
+#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
 
 #define CONFIG_KEYBOARD_PROTOCOL_MKBP
 #define CONFIG_MKBP_EVENT
@@ -129,7 +129,7 @@ enum battery_type {
 
 /* support factory keyboard test */
 #define CONFIG_KEYBOARD_FACTORY_TEST
-#define GPIO_KBD_KSO2		GPIO_EC_KSO_02_INV
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
 extern const int keyboard_factory_scan_pins[][2];
 extern const int keyboard_factory_scan_pins_used;
 
diff --git a/board/pico/build.mk b/board/pico/build.mk
index 9ca7933e2a..a1ca27116e 100644
--- a/board/pico/build.mk
+++ b/board/pico/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/pico/ec.tasklist b/board/pico/ec.tasklist
index 5c272d04f4..883033408a 100644
--- a/board/pico/ec.tasklist
+++ b/board/pico/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/pico/gpio.inc b/board/pico/gpio.inc
index 34ac5cf7af..359e25451e 100644
--- a/board/pico/gpio.inc
+++ b/board/pico/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/pico/led.c b/board/pico/led.c
index 076199b2ed..bbbad7ceb8 100644
--- a/board/pico/led.c
+++ b/board/pico/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -14,22 +14,27 @@
 __override const int led_charge_lvl_1 = 5;
 __override const int led_charge_lvl_2 = 95;
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 __override void led_set_color_battery(enum ec_led_colors color)
 {
diff --git a/board/pirika/battery.c b/board/pirika/battery.c
index 2da3296106..f753eba554 100644
--- a/board/pirika/battery.c
+++ b/board/pirika/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/pirika/board.c b/board/pirika/board.c
index 7a21d632d2..8913ec0f07 100644
--- a/board/pirika/board.c
+++ b/board/pirika/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -41,8 +41,8 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
 
 #define INT_RECHECK_US 5000
 
@@ -104,8 +104,8 @@ static const struct ec_response_keybd_config pasara_kb = {
 	},
 	.capabilities = KEYBD_CAP_SCRNLOCK_KEY | KEYBD_CAP_NUMERIC_KEYPAD,
 };
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	if (get_cbi_fw_config_numeric_pad() == NUMERIC_PAD_ABSENT)
 		return &pirika_kb;
@@ -188,34 +188,26 @@ static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH0
-	},
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH2
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH3
-	},
-	[ADC_TEMP_SENSOR_3] = {
-		.name = "TEMP_SENSOR3",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH15
-	},
+	[ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH0 },
+	[ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH2 },
+	[ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH3 },
+	[ADC_TEMP_SENSOR_3] = { .name = "TEMP_SENSOR3",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH15 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
@@ -275,40 +267,31 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 };
 
 /* USB Retimer */
-enum tusb544_conf {
-	USB_DP = 0,
-	USB_DP_INV,
-	USB,
-	USB_INV,
-	DP,
-	DP_INV
-};
+enum tusb544_conf { USB_DP = 0, USB_DP_INV, USB, USB_INV, DP, DP_INV };
 
-static int board_tusb544_set(const struct usb_mux *me,
-		mux_state_t mux_state)
+static int board_tusb544_set(const struct usb_mux *me, mux_state_t mux_state)
 {
-	int  rv = EC_SUCCESS;
+	int rv = EC_SUCCESS;
 	enum tusb544_conf usb_mode = 0;
 	/* USB */
 	if (mux_state & USB_PD_MUX_USB_ENABLED) {
 		/* USB with DP */
 		if (mux_state & USB_PD_MUX_DP_ENABLED) {
-			usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-					? USB_DP_INV
-					: USB_DP;
+			usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ?
+					   USB_DP_INV :
+					   USB_DP;
 		}
 		/* USB without DP */
 		else {
-			usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-					? USB_INV
-					: USB;
+			usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ?
+					   USB_INV :
+					   USB;
 		}
 	}
 	/* DP without USB */
 	else if (mux_state & USB_PD_MUX_DP_ENABLED) {
-		usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-				? DP_INV
-				: DP;
+		usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ? DP_INV :
+									DP;
 	}
 	/* Nothing enabled */
 	else
@@ -377,28 +360,37 @@ static int board_tusb544_set(const struct usb_mux *me,
 	return rv;
 }
 
-const struct usb_mux usbc1_retimer = {
-	.usb_port = 1,
-	.i2c_port = I2C_PORT_SUB_USB_C1,
-	.i2c_addr_flags = TUSB544_I2C_ADDR_FLAGS0,
-	.driver = &tusb544_drv,
-	.board_set = &board_tusb544_set,
+const struct usb_mux_chain usbc1_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = 1,
+			.i2c_port = I2C_PORT_SUB_USB_C1,
+			.i2c_addr_flags = TUSB544_I2C_ADDR_FLAGS0,
+			.driver = &tusb544_drv,
+			.board_set = &board_tusb544_set,
+		},
 };
 
 /* USB Muxes */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+			},
 	},
 	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.next_mux = &usbc1_retimer,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_SUB_USB_C1,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+			},
+		.next = &usbc1_retimer,
 	},
 };
 
@@ -521,8 +513,7 @@ int board_is_sourcing_vbus(int port)
 
 int board_set_active_charge_port(int port)
 {
-		int is_real_port = (port >= 0 &&
-			    port < board_get_usb_pd_port_count());
+	int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count());
 	int i;
 	int old_port;
 
@@ -584,12 +575,10 @@ int board_set_active_charge_port(int port)
 	charger_discharge_on_ac(0);
 
 	return EC_SUCCESS;
-
 }
 
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
+__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+				       int *ki_div, int *kd, int *kd_div)
 {
 	*kp = 1;
 	*kp_div = 20;
@@ -622,7 +611,7 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Sensor Data */
-static struct kionix_accel_data  g_kx022_data;
+static struct kionix_accel_data g_kx022_data;
 static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
 
 /* Drivers */
@@ -702,26 +691,26 @@ const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
 /* Thermistors */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Charger",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Vcore",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_3},
+	[TEMP_SENSOR_1] = { .name = "Charger",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Vcore",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CHARGER \
-	{ \
+#define THERMAL_CHARGER          \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(68), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(90), \
@@ -735,8 +724,8 @@ __maybe_unused static const struct ec_thermal_config thermal_charger =
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_VCORE \
-	{ \
+#define THERMAL_VCORE            \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
@@ -750,8 +739,8 @@ __maybe_unused static const struct ec_thermal_config thermal_vcore =
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_AMBIENT \
-	{ \
+#define THERMAL_AMBIENT          \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
diff --git a/board/pirika/board.h b/board/pirika/board.h
index 932653e1ae..c8e2f3eb35 100644
--- a/board/pirika/board.h
+++ b/board/pirika/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,12 +25,15 @@
 #define CONFIG_BC12_DETECT_PI3USB9201
 
 /* Charger */
-#define CONFIG_CHARGER_RAA489000	/* C0 and C1: Charger */
+#define CONFIG_CHARGER_RAA489000 /* C0 and C1: Charger */
+#define PD_MAX_VOLTAGE_MV 20000
 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 #define CONFIG_CHARGER_SENSE_RESISTOR 10
-#undef  CONFIG_CHARGER_SINGLE_CHIP
+#undef CONFIG_CHARGER_SINGLE_CHIP
 #define CONFIG_OCPC
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */
+#define CONFIG_OCPC_DEF_RBATT_MOHMS               \
+	22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \
+	    */
 #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
 #define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
 
@@ -38,14 +41,14 @@
 
 /* LED */
 #define CONFIG_LED_ONOFF_STATES
-#define CONFIG_LED_ONOFF_STATES_BAT_LOW	10
+#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
 
 /* PWM */
 #define CONFIG_PWM
 
 /* Sensors */
-#define CONFIG_ACCEL_KX022		/* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM	/* Base accel */
+#define CONFIG_ACCEL_KX022 /* Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
 #define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 /* Sensors without hardware FIFO are in forced mode */
@@ -83,10 +86,10 @@
 #define CONFIG_CHIPSET_CAN_THROTTLE
 
 /* USB Mux and Retimer */
-#define CONFIG_USB_MUX_IT5205			/* C1: ITE Mux */
-#define I2C_PORT_USB_MUX I2C_PORT_USB_C0	/* Required for ITE Mux */
+#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */
 
-#define CONFIG_USBC_RETIMER_TUSB544		/* C1 Redriver: TUSB544 */
+#define CONFIG_USBC_RETIMER_TUSB544 /* C1 Redriver: TUSB544 */
 
 /* Keyboard */
 #define CONFIG_KEYBOARD_VIVALDI
@@ -110,19 +113,14 @@ enum pwm_channel {
 };
 
 /* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
 /* ADC channels */
 enum adc_channel {
-	ADC_VSNS_PP3300_A,     /* ADC0 */
-	ADC_TEMP_SENSOR_1,     /* ADC2 */
-	ADC_TEMP_SENSOR_2,     /* ADC3 */
-	ADC_TEMP_SENSOR_3,     /* ADC15 */
+	ADC_VSNS_PP3300_A, /* ADC0 */
+	ADC_TEMP_SENSOR_1, /* ADC2 */
+	ADC_TEMP_SENSOR_2, /* ADC3 */
+	ADC_TEMP_SENSOR_3, /* ADC15 */
 	ADC_CH_COUNT
 };
 
diff --git a/board/pirika/build.mk b/board/pirika/build.mk
index 8167ca9966..01b890bf29 100644
--- a/board/pirika/build.mk
+++ b/board/pirika/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/pirika/cbi_ssfc.c b/board/pirika/cbi_ssfc.c
index c4b859f133..81f3ee0dad 100644
--- a/board/pirika/cbi_ssfc.c
+++ b/board/pirika/cbi_ssfc.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
 
 enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
 {
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
 }
 
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
 {
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
 }
diff --git a/board/pirika/cbi_ssfc.h b/board/pirika/cbi_ssfc.h
index 935049b6ae..bf8853a43a 100644
--- a/board/pirika/cbi_ssfc.h
+++ b/board/pirika/cbi_ssfc.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -56,5 +56,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
  */
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
 
-
 #endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/pirika/ec.tasklist b/board/pirika/ec.tasklist
index d6fa610141..f7c32f66bf 100644
--- a/board/pirika/ec.tasklist
+++ b/board/pirika/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/pirika/gpio.inc b/board/pirika/gpio.inc
index 90e6de2607..5ec1003a70 100644
--- a/board/pirika/gpio.inc
+++ b/board/pirika/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/pirika/led.c b/board/pirika/led.c
index 2fe70f5fe8..916f691dd6 100644
--- a/board/pirika/led.c
+++ b/board/pirika/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,28 +9,37 @@
 #include "led_common.h"
 #include "led_onoff_states.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
 __override const int led_charge_lvl_1;
 __override const int led_charge_lvl_2 = 95;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]       = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]       = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC},
-					{LED_OFF,            2 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]	     = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { LED_OFF, 2 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
 const enum ec_led_id supported_led_ids[] = {
 	EC_LED_ID_BATTERY_LED,
diff --git a/board/pirika/usb_pd_policy.c b/board/pirika/usb_pd_policy.c
index 15faf41ffc..83c09bb99e 100644
--- a/board/pirika/usb_pd_policy.c
+++ b/board/pirika/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,8 @@
 #include "driver/tcpm/tcpci.h"
 #include "usb_pd.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
diff --git a/board/plankton/board.c b/board/plankton/board.c
index 5a62f63c86..2bf57084ce 100644
--- a/board/plankton/board.c
+++ b/board/plankton/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -78,14 +78,12 @@ void hpd_lvl_deferred(void)
 		/* Configure redriver's back side */
 		if (level)
 			sn75dp130_dpcd_init();
-
 	}
 
 	/* Send queued IRQ if the cable is attached */
 	if (hpd_possible_irq && level && dp_mode)
 		pd_send_hpd(0, hpd_irq);
 	hpd_possible_irq = 0;
-
 }
 DECLARE_DEFERRED(hpd_lvl_deferred);
 
@@ -103,8 +101,7 @@ void hpd_event(enum gpio_signal signal)
 	hpd_prev_ts = now.val;
 
 	/* All previous hpd level events need to be re-triggered */
-	hook_call_deferred(&hpd_lvl_deferred_data,
-			   HPD_USTREAM_DEBOUNCE_LVL);
+	hook_call_deferred(&hpd_lvl_deferred_data, HPD_USTREAM_DEBOUNCE_LVL);
 }
 
 /* Debounce time for voltage buttons */
@@ -134,8 +131,7 @@ enum usbc_action {
 	USBC_ACT_COUNT
 };
 
-enum board_src_cap src_cap_mapping[USBC_ACT_COUNT] =
-{
+enum board_src_cap src_cap_mapping[USBC_ACT_COUNT] = {
 	[USBC_ACT_5V_TO_DUT] = SRC_CAP_5V,
 	[USBC_ACT_12V_TO_DUT] = SRC_CAP_12V,
 	[USBC_ACT_20V_TO_DUT] = SRC_CAP_20V,
@@ -155,21 +151,21 @@ static void set_active_cc(int cc)
 	 * disabled then only set the active CC line.
 	 */
 	/* Pull-up on CC2 */
-	gpio_set_flags(GPIO_USBC_CC2_HOST,
-		       ((cc || drp_enable) && host_mode) ?
-		       GPIO_OUT_HIGH : GPIO_INPUT);
+	gpio_set_flags(GPIO_USBC_CC2_HOST, ((cc || drp_enable) && host_mode) ?
+						   GPIO_OUT_HIGH :
+						   GPIO_INPUT);
 	/* Pull-down on CC2 */
 	gpio_set_flags(GPIO_USBC_CC2_DEVICE_ODL,
-		       ((cc || drp_enable) && !host_mode) ?
-		       GPIO_OUT_LOW : GPIO_INPUT);
+		       ((cc || drp_enable) && !host_mode) ? GPIO_OUT_LOW :
+							    GPIO_INPUT);
 	/* Pull-up on CC1 */
-	gpio_set_flags(GPIO_USBC_CC1_HOST,
-		       ((!cc || drp_enable) && host_mode) ?
-		       GPIO_OUT_HIGH : GPIO_INPUT);
+	gpio_set_flags(GPIO_USBC_CC1_HOST, ((!cc || drp_enable) && host_mode) ?
+						   GPIO_OUT_HIGH :
+						   GPIO_INPUT);
 	/* Pull-down on CC1 */
 	gpio_set_flags(GPIO_USBC_CC1_DEVICE_ODL,
-		       ((!cc || drp_enable) && !host_mode) ?
-		       GPIO_OUT_LOW : GPIO_INPUT);
+		       ((!cc || drp_enable) && !host_mode) ? GPIO_OUT_LOW :
+							     GPIO_INPUT);
 }
 
 /**
@@ -221,7 +217,7 @@ static void fake_disconnect_end(void)
 	board_pd_set_host_mode(fake_pd_host_mode);
 
 	/* Restart CC cable detection */
-	hook_call_deferred(&detect_cc_cable_data, 500*MSEC);
+	hook_call_deferred(&detect_cc_cable_data, 500 * MSEC);
 }
 DECLARE_DEFERRED(fake_disconnect_end);
 
@@ -361,10 +357,10 @@ static void set_usbc_action(enum usbc_action act)
 		gpio_set_level(GPIO_CASE_CLOSE_EN, 1);
 		gpio_set_level(GPIO_CASE_CLOSE_DFU_L, 1);
 		break;
-	case  USBC_ACT_DRP_TOGGLE:
+	case USBC_ACT_DRP_TOGGLE:
 		/* Toggle dualrole mode setting. */
-		update_usbc_dual_role(drp_enable ?
-				      PD_DRP_TOGGLE_OFF : PD_DRP_TOGGLE_ON);
+		update_usbc_dual_role(drp_enable ? PD_DRP_TOGGLE_OFF :
+						   PD_DRP_TOGGLE_ON);
 		break;
 	default:
 		break;
@@ -424,8 +420,8 @@ static void button_deferred(void)
 		break;
 	}
 
-	ccprintf("Button %d = %d\n",
-		 button_pressed, gpio_get_level(button_pressed));
+	ccprintf("Button %d = %d\n", button_pressed,
+		 gpio_get_level(button_pressed));
 }
 DECLARE_DEFERRED(button_deferred);
 
@@ -453,20 +449,18 @@ void vbus_event(enum gpio_signal signal)
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* USB PD CC lines sensing. Converted to mV (3300mV/4096). */
-	[ADC_CH_CC1_PD] = {"CC1_PD", 3300, 4096, 0, STM32_AIN(0)},
-	[ADC_CH_CC2_PD] = {"CC2_PD", 3300, 4096, 0, STM32_AIN(4)},
+	[ADC_CH_CC1_PD] = { "CC1_PD", 3300, 4096, 0, STM32_AIN(0) },
+	[ADC_CH_CC2_PD] = { "CC2_PD", 3300, 4096, 0, STM32_AIN(4) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "master",
-		.port = I2C_PORT_MASTER,
-		.kbps = 100,
-		.scl  = GPIO_MASTER_I2C_SCL,
-		.sda  = GPIO_MASTER_I2C_SDA
-	},
+	{ .name = "master",
+	  .port = I2C_PORT_MASTER,
+	  .kbps = 100,
+	  .scl = GPIO_MASTER_I2C_SCL,
+	  .sda = GPIO_MASTER_I2C_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -476,12 +470,12 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
  * Pin number for active-high reset from PCA9534 to CMOS pull-down to
  * SN75DP130's RSTN (active-low)
  */
-#define REDRIVER_RST_PIN  0x1
+#define REDRIVER_RST_PIN 0x1
 
 static int sn75dp130_i2c_write(uint8_t index, uint8_t value)
 {
-	return i2c_write8(I2C_PORT_MASTER, SN75DP130_I2C_ADDR_FLAGS,
-			  index, value);
+	return i2c_write8(I2C_PORT_MASTER, SN75DP130_I2C_ADDR_FLAGS, index,
+			  value);
 }
 
 /**
@@ -494,17 +488,15 @@ static int sn75dp130_reset(void)
 {
 	int rv;
 
-	rv = pca9534_config_pin(I2C_PORT_MASTER, 0x20,
-				REDRIVER_RST_PIN, PCA9534_OUTPUT);
+	rv = pca9534_config_pin(I2C_PORT_MASTER, 0x20, REDRIVER_RST_PIN,
+				PCA9534_OUTPUT);
 	/* Assert (its active high) */
-	rv |= pca9534_set_level(I2C_PORT_MASTER, 0x20,
-				REDRIVER_RST_PIN, 1);
+	rv |= pca9534_set_level(I2C_PORT_MASTER, 0x20, REDRIVER_RST_PIN, 1);
 	/* datasheet recommends > 100usec */
 	usleep(200);
 
 	/* De-assert */
-	rv |= pca9534_set_level(I2C_PORT_MASTER, 0x20,
-				REDRIVER_RST_PIN, 0);
+	rv |= pca9534_set_level(I2C_PORT_MASTER, 0x20, REDRIVER_RST_PIN, 0);
 	/* datasheet recommends > 400msec */
 	usleep(450 * MSEC);
 	return rv;
@@ -555,7 +547,7 @@ static int sn75dp130_redriver_init(void)
 	return rv;
 }
 
-static int cmd_usbc_action(int argc, char *argv[])
+static int cmd_usbc_action(int argc, const char *argv[])
 {
 	enum usbc_action act;
 
@@ -600,12 +592,10 @@ int board_in_hub_mode(void)
 	int ret;
 	int level;
 
-	ret = pca9534_config_pin(I2C_PORT_MASTER, 0x20,
-				 6, PCA9534_INPUT);
+	ret = pca9534_config_pin(I2C_PORT_MASTER, 0x20, 6, PCA9534_INPUT);
 	if (ret)
 		return -1;
-	ret = pca9534_get_level(I2C_PORT_MASTER, 0x20,
-				6, &level);
+	ret = pca9534_get_level(I2C_PORT_MASTER, 0x20, 6, &level);
 	if (ret)
 		return -1;
 	return level;
@@ -615,17 +605,14 @@ static int board_usb_hub_reset(void)
 {
 	int ret;
 
-	ret = pca9534_config_pin(I2C_PORT_MASTER, 0x20,
-				 7, PCA9534_OUTPUT);
+	ret = pca9534_config_pin(I2C_PORT_MASTER, 0x20, 7, PCA9534_OUTPUT);
 	if (ret)
 		return ret;
-	ret = pca9534_set_level(I2C_PORT_MASTER, 0x20,
-				7, 0);
+	ret = pca9534_set_level(I2C_PORT_MASTER, 0x20, 7, 0);
 	if (ret)
 		return ret;
 	usleep(100 * MSEC);
-	return pca9534_set_level(I2C_PORT_MASTER, 0x20,
-				 7, 1);
+	return pca9534_set_level(I2C_PORT_MASTER, 0x20, 7, 1);
 }
 
 void board_maybe_reset_usb_hub(void)
@@ -634,12 +621,11 @@ void board_maybe_reset_usb_hub(void)
 		board_usb_hub_reset();
 }
 
-static int cmd_usb_hub_reset(int argc, char *argv[])
+static int cmd_usb_hub_reset(int argc, const char *argv[])
 {
 	return board_usb_hub_reset();
 }
-DECLARE_CONSOLE_COMMAND(hub_reset, cmd_usb_hub_reset,
-			NULL, "Reset USB hub");
+DECLARE_CONSOLE_COMMAND(hub_reset, cmd_usb_hub_reset, NULL, "Reset USB hub");
 
 static void board_usb_hub_reset_no_return(void)
 {
@@ -668,7 +654,7 @@ int board_fake_pd_adc_read(int cc)
 			 * on other CC line. */
 			if (active_cc == cc)
 				return adc_read_channel(cc ? ADC_CH_CC2_PD :
-							ADC_CH_CC1_PD);
+							     ADC_CH_CC1_PD);
 			else
 				return host_mode ? 3000 : 0;
 		}
@@ -754,7 +740,7 @@ static void board_init(void)
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
-static int cmd_fake_disconnect(int argc, char *argv[])
+static int cmd_fake_disconnect(int argc, const char *argv[])
 {
 	int delay_ms, duration_ms;
 	char *e;
@@ -776,8 +762,8 @@ static int cmd_fake_disconnect(int argc, char *argv[])
 	fake_pd_disconnect_duration_us = duration_ms * MSEC;
 	hook_call_deferred(&fake_disconnect_start_data, delay_ms * MSEC);
 
-	ccprintf("Fake disconnect for %d ms starting in %d ms.\n",
-		 duration_ms, delay_ms);
+	ccprintf("Fake disconnect for %d ms starting in %d ms.\n", duration_ms,
+		 delay_ms);
 
 	return EC_SUCCESS;
 }
@@ -791,7 +777,7 @@ static void trigger_dfu_release(void)
 }
 DECLARE_DEFERRED(trigger_dfu_release);
 
-static int cmd_trigger_dfu(int argc, char *argv[])
+static int cmd_trigger_dfu(int argc, const char *argv[])
 {
 	gpio_set_level(GPIO_CASE_CLOSE_DFU_L, 0);
 	ccprintf("Asserting CASE_CLOSE_DFU_L.\n");
diff --git a/board/plankton/board.h b/board/plankton/board.h
index 39ab706cd2..224364269b 100644
--- a/board/plankton/board.h
+++ b/board/plankton/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -58,7 +58,7 @@
 
 /* Timer selection */
 #define TIM_CLOCK32 2
-#define TIM_ADC     3
+#define TIM_ADC 3
 
 #include "gpio_signal.h"
 
@@ -77,18 +77,18 @@ enum board_src_cap {
 };
 
 /* 3.0A Rp */
-#define PD_SRC_VNC            PD_SRC_3_0_VNC_MV
-#define PD_SNK_RD_THRESHOLD   PD_SRC_3_0_RD_THRESH_MV
+#define PD_SRC_VNC PD_SRC_3_0_VNC_MV
+#define PD_SNK_RD_THRESHOLD PD_SRC_3_0_RD_THRESH_MV
 
 /* delay necessary for the voltage transition on the power supply */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  50000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 50000 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 50000 /* us */
 
 /* Define typical operating power and max power */
 #define PD_OPERATING_POWER_MW 5000
-#define PD_MAX_POWER_MW       60000
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_VOLTAGE_MV     20000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Set USB PD source capability */
 void board_set_source_cap(enum board_src_cap cap);
diff --git a/board/plankton/build.mk b/board/plankton/build.mk
index 662be139c7..0e597a478f 100644
--- a/board/plankton/build.mk
+++ b/board/plankton/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
+# Copyright 2014 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/plankton/ec.tasklist b/board/plankton/ec.tasklist
index 41fc047d6a..5a82344122 100644
--- a/board/plankton/ec.tasklist
+++ b/board/plankton/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/plankton/gpio.inc b/board/plankton/gpio.inc
index 9c618dbaa6..edccec814c 100644
--- a/board/plankton/gpio.inc
+++ b/board/plankton/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
+ * Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/plankton/usb_pd_config.h b/board/plankton/usb_pd_config.h
index fca6484069..47614c3fce 100644
--- a/board/plankton/usb_pd_config.h
+++ b/board/plankton/usb_pd_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -50,7 +50,7 @@ static inline void spi_enable_clock(int port)
 
 #define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
 #define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
-#define TIM_CCR_CS  1
+#define TIM_CCR_CS 1
 #define EXTI_COMP_MASK(p) BIT(21)
 #define IRQ_COMP STM32_IRQ_COMP
 /* triggers packet detection on comparator falling edge */
@@ -92,9 +92,8 @@ static inline void pd_tx_disable(int port, int polarity)
 {
 	/* output low on SPI TX to disable the FET */
 	/* PA6 is SPI1_MISO */
-	STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
-				   & ~(3 << (2*6)))
-				   |  (1 << (2*6));
+	STM32_GPIO_MODER(GPIO_A) =
+		(STM32_GPIO_MODER(GPIO_A) & ~(3 << (2 * 6))) | (1 << (2 * 6));
 	/* put the low level reference in Hi-Z */
 	gpio_set_level(GPIO_USBC_CC1_TX_EN, 0);
 	gpio_set_level(GPIO_USBC_CC2_TX_EN, 0);
@@ -104,11 +103,10 @@ static inline void pd_tx_disable(int port, int polarity)
 static inline void pd_select_polarity(int port, int polarity)
 {
 	/* use the right comparator non inverted input for COMP1 */
-	STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK)
-			| STM32_COMP_CMP1EN
-			| (polarity ?
-			   STM32_COMP_CMP1INSEL_INM4 :
-			   STM32_COMP_CMP1INSEL_INM6);
+	STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK) |
+			 STM32_COMP_CMP1EN |
+			 (polarity ? STM32_COMP_CMP1INSEL_INM4 :
+				     STM32_COMP_CMP1INSEL_INM6);
 	gpio_set_level(GPIO_USBC_POLARITY, polarity);
 }
 
diff --git a/board/plankton/usb_pd_pdo.c b/board/plankton/usb_pd_pdo.c
index f51a40abdc..52dcc11352 100644
--- a/board/plankton/usb_pd_pdo.c
+++ b/board/plankton/usb_pd_pdo.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,28 +7,28 @@
 #include "usb_pd.h"
 #include "usb_pd_pdo.h"
 
-#define PDO_FIXED_FLAGS (PDO_FIXED_DATA_SWAP | PDO_FIXED_UNCONSTRAINED |\
-			 PDO_FIXED_COMM_CAP)
+#define PDO_FIXED_FLAGS \
+	(PDO_FIXED_DATA_SWAP | PDO_FIXED_UNCONSTRAINED | PDO_FIXED_COMM_CAP)
 
 /* Source PDOs */
 const uint32_t pd_src_pdo[] = {
-		PDO_FIXED(5000,  3000, PDO_FIXED_FLAGS),
-		PDO_FIXED(12000, 3000, PDO_FIXED_FLAGS),
-		PDO_FIXED(20000, 3000, PDO_FIXED_FLAGS),
+	PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS),
+	PDO_FIXED(12000, 3000, PDO_FIXED_FLAGS),
+	PDO_FIXED(20000, 3000, PDO_FIXED_FLAGS),
 };
 
 /* Fake PDOs : we just want our pre-defined voltages */
 const uint32_t pd_snk_pdo[] = {
-		PDO_FIXED(5000,   500, PDO_FIXED_FLAGS),
-		PDO_FIXED(12000,  500, PDO_FIXED_FLAGS),
-		PDO_FIXED(20000,  500, PDO_FIXED_FLAGS),
+	PDO_FIXED(5000, 500, PDO_FIXED_FLAGS),
+	PDO_FIXED(12000, 500, PDO_FIXED_FLAGS),
+	PDO_FIXED(20000, 500, PDO_FIXED_FLAGS),
 };
 const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
 
 static const int pd_src_pdo_cnts[] = {
-		[SRC_CAP_5V] = 1,
-		[SRC_CAP_12V] = 2,
-		[SRC_CAP_20V] = 3,
+	[SRC_CAP_5V] = 1,
+	[SRC_CAP_12V] = 2,
+	[SRC_CAP_20V] = 3,
 };
 
 static int pd_src_pdo_idx;
diff --git a/board/plankton/usb_pd_pdo.h b/board/plankton/usb_pd_pdo.h
index 20e8976348..030dab9287 100644
--- a/board/plankton/usb_pd_pdo.h
+++ b/board/plankton/usb_pd_pdo.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/plankton/usb_pd_policy.c b/board/plankton/usb_pd_policy.c
index 238f2297f5..355919e06a 100644
--- a/board/plankton/usb_pd_policy.c
+++ b/board/plankton/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,8 +18,8 @@
 #include "usb_pd_pdo.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 /* Acceptable margin between requested VBUS and measured value */
 #define MARGIN_MV 400 /* mV */
@@ -27,7 +27,6 @@
 /* Whether alternate mode has been entered or not */
 static int alt_mode;
 
-
 void pd_set_input_current_limit(int port, uint32_t max_ma,
 				uint32_t supply_voltage)
 {
@@ -77,22 +76,18 @@ __override int pd_check_power_swap(int port)
 	return 1;
 }
 
-__override int pd_check_data_swap(int port,
-				  enum pd_data_role data_role)
+__override int pd_check_data_swap(int port, enum pd_data_role data_role)
 {
 	/* Always allow data swap */
 	return 1;
 }
 
-__override void pd_check_pr_role(int port,
-				 enum pd_power_role pr_role,
+__override void pd_check_pr_role(int port, enum pd_power_role pr_role,
 				 int flags)
 {
 }
 
-__override void pd_check_dr_role(int port,
-				 enum pd_data_role dr_role,
-				 int flags)
+__override void pd_check_dr_role(int port, enum pd_data_role dr_role, int flags)
 {
 	/* If Plankton is in USB hub mode, always act as UFP */
 	if (board_in_hub_mode() && dr_role == PD_ROLE_DFP &&
@@ -110,8 +105,8 @@ const uint32_t vdo_idh = VDO_IDH(0, /* data caps as USB host */
 const uint32_t vdo_product = VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV);
 
 const uint32_t vdo_ama = VDO_AMA(CONFIG_USB_PD_IDENTITY_HW_VERS,
-				 CONFIG_USB_PD_IDENTITY_SW_VERS,
-				 0, 0, 0, 0, /* SS[TR][12] */
+				 CONFIG_USB_PD_IDENTITY_SW_VERS, 0, 0, 0,
+				 0, /* SS[TR][12] */
 				 0, /* Vconn power */
 				 0, /* Vconn power required */
 				 1, /* Vbus power required */
@@ -139,13 +134,13 @@ static int svdm_response_svids(int port, uint32_t *payload)
 #define MODE_CNT 1
 #define OPOS 1
 
-const uint32_t vdo_dp_mode[MODE_CNT] =  {
-	VDO_MODE_DP(0,		   /* UFP pin cfg supported : none */
+const uint32_t vdo_dp_mode[MODE_CNT] = {
+	VDO_MODE_DP(0, /* UFP pin cfg supported : none */
 		    MODE_DP_PIN_E, /* DFP pin cfg supported */
-		    1,		   /* no usb2.0	signalling in AMode */
-		    CABLE_PLUG,	   /* its a plug */
-		    MODE_DP_V13,   /* DPv1.3 Support, no Gen2 */
-		    MODE_DP_SNK)   /* Its a sink only */
+		    1, /* no usb2.0	signalling in AMode */
+		    CABLE_PLUG, /* its a plug */
+		    MODE_DP_V13, /* DPv1.3 Support, no Gen2 */
+		    MODE_DP_SNK) /* Its a sink only */
 };
 
 static int svdm_response_modes(int port, uint32_t *payload)
@@ -167,13 +162,13 @@ static int dp_status(int port, uint32_t *payload)
 	if (opos != OPOS)
 		return 0; /* nak */
 
-	payload[1] = VDO_DP_STATUS(0,                /* IRQ_HPD */
-				   (hpd == 1),       /* HPD_HI|LOW */
-				   0,		     /* request exit DP */
-				   0,		     /* request exit USB */
-				   0,		     /* MF pref */
+	payload[1] = VDO_DP_STATUS(0, /* IRQ_HPD */
+				   (hpd == 1), /* HPD_HI|LOW */
+				   0, /* request exit DP */
+				   0, /* request exit USB */
+				   0, /* MF pref */
 				   !gpio_get_level(GPIO_USBC_SS_USB_MODE),
-				   0,		     /* power low */
+				   0, /* power low */
 				   0x2);
 	return 2;
 }
diff --git a/board/polyberry/board.c b/board/polyberry/board.c
index 5bb811f82c..f9fdd44ff8 100644
--- a/board/polyberry/board.c
+++ b/board/polyberry/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,13 +24,13 @@
  * Define the strings used in our USB descriptors.
  */
 const void *const usb_strings[] = {
-	[USB_STR_DESC]		= usb_string_desc,
-	[USB_STR_VENDOR]	= USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]	= USB_STRING_DESC("Polyberry"),
-	[USB_STR_SERIALNO]	= USB_STRING_DESC("1234-a"),
-	[USB_STR_VERSION]	= USB_STRING_DESC(CROS_EC_VERSION32),
-	[USB_STR_CONSOLE_NAME]	= USB_STRING_DESC("Polyberry EC Shell"),
-	[USB_STR_UPDATE_NAME]	= USB_STRING_DESC("Firmware update"),
+	[USB_STR_DESC] = usb_string_desc,
+	[USB_STR_VENDOR] = USB_STRING_DESC("Google LLC"),
+	[USB_STR_PRODUCT] = USB_STRING_DESC("Polyberry"),
+	[USB_STR_SERIALNO] = USB_STRING_DESC("1234-a"),
+	[USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32),
+	[USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Polyberry EC Shell"),
+	[USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"),
 };
 
 BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
@@ -47,15 +47,15 @@ struct dwc_usb usb_ctl = {
 	.irq = STM32_IRQ_OTG_HS,
 };
 
-#define GPIO_SET_HS(bank, number)	\
-	(STM32_GPIO_OSPEEDR(GPIO_##bank) |= (0x3 << ((number) * 2)))
+#define GPIO_SET_HS(bank, number) \
+	(STM32_GPIO_OSPEEDR(GPIO_##bank) |= (0x3 << ((number)*2)))
 
 void board_config_post_gpio_init(void)
 {
 	/* We use MCO2 clock passthrough to provide a clock to USB HS */
 	gpio_config_module(MODULE_MCO, 1);
 	/* GPIO PC9 to high speed */
-	GPIO_SET_HS(C,  9);
+	GPIO_SET_HS(C, 9);
 
 	if (usb_ctl.phy_type == USB_PHY_ULPI)
 		gpio_set_level(GPIO_USB_MUX_SEL, 0);
@@ -66,19 +66,19 @@ void board_config_post_gpio_init(void)
 	GPIO_SET_HS(A, 11);
 	GPIO_SET_HS(A, 12);
 
-	GPIO_SET_HS(C,  3);
-	GPIO_SET_HS(C,  2);
-	GPIO_SET_HS(C,  0);
-	GPIO_SET_HS(A,  5);
+	GPIO_SET_HS(C, 3);
+	GPIO_SET_HS(C, 2);
+	GPIO_SET_HS(C, 0);
+	GPIO_SET_HS(A, 5);
 
-	GPIO_SET_HS(B,  5);
+	GPIO_SET_HS(B, 5);
 	GPIO_SET_HS(B, 13);
 	GPIO_SET_HS(B, 12);
-	GPIO_SET_HS(B,  2);
+	GPIO_SET_HS(B, 2);
 	GPIO_SET_HS(B, 10);
-	GPIO_SET_HS(B,  1);
-	GPIO_SET_HS(B,  0);
-	GPIO_SET_HS(A,  3);
+	GPIO_SET_HS(B, 1);
+	GPIO_SET_HS(B, 0);
+	GPIO_SET_HS(A, 3);
 }
 
 static void board_init(void)
diff --git a/board/polyberry/board.h b/board/polyberry/board.h
index 8e55967bf5..41069f2722 100644
--- a/board/polyberry/board.h
+++ b/board/polyberry/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -44,15 +44,15 @@
 #define DEFAULT_SERIALNO "Uninitialized"
 
 /* USB interface indexes (use define rather than enum to expand them) */
-#define USB_IFACE_CONSOLE	0
-#define USB_IFACE_UPDATE	1
-#define USB_IFACE_COUNT		2
+#define USB_IFACE_CONSOLE 0
+#define USB_IFACE_UPDATE 1
+#define USB_IFACE_COUNT 2
 
 /* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL		0
-#define USB_EP_CONSOLE		1
-#define USB_EP_UPDATE		2
-#define USB_EP_COUNT		3
+#define USB_EP_CONTROL 0
+#define USB_EP_CONSOLE 1
+#define USB_EP_UPDATE 2
+#define USB_EP_COUNT 3
 
 /* This is not actually a Chromium EC so disable some features. */
 #undef CONFIG_WATCHDOG_HELP
diff --git a/board/polyberry/build.mk b/board/polyberry/build.mk
index 6b06f2bb8f..61e4b79d47 100644
--- a/board/polyberry/build.mk
+++ b/board/polyberry/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/polyberry/ec.tasklist b/board/polyberry/ec.tasklist
index c1fb169118..c45a1e89a7 100644
--- a/board/polyberry/ec.tasklist
+++ b/board/polyberry/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/polyberry/gpio.inc b/board/polyberry/gpio.inc
index 536dccc5ff..d862155c4d 100644
--- a/board/polyberry/gpio.inc
+++ b/board/polyberry/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/pompom/battery.c b/board/pompom/battery.c
index 7ce8eec202..2566813651 100644
--- a/board/pompom/battery.c
+++ b/board/pompom/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/pompom/board.c b/board/pompom/board.c
index 56241083d3..394f06be8e 100644
--- a/board/pompom/board.c
+++ b/board/pompom/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -34,8 +34,8 @@
 #include "usbc_ocp.h"
 #include "usbc_ppc.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* Forward declaration */
 static void tcpc_alert_event(enum gpio_signal signal);
@@ -115,10 +115,8 @@ __override struct keyboard_scan_config keyscan_config = {
 	 * as it uses the new location (KSO_00/KSI_03). And T11 key, which maps
 	 * to KSO_01/KSI_00, is not there.
 	 */
-	.actual_key_mask = {
-		0x1c, 0xfe, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca
-	},
+	.actual_key_mask = { 0x1c, 0xfe, 0xff, 0xff, 0xff, 0xf5, 0xff, 0xa4,
+			     0xff, 0xfe, 0x55, 0xfa, 0xca },
 	/* Other values should be the same as the default configuration. */
 	.debounce_down_us = 9 * MSEC,
 	.debounce_up_us = 30 * MSEC,
@@ -129,34 +127,26 @@ __override struct keyboard_scan_config keyscan_config = {
 
 /* I2C port map */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl  = GPIO_EC_I2C_POWER_SCL,
-		.sda  = GPIO_EC_I2C_POWER_SDA
-	},
-	{
-		.name = "tcpc0",
-		.port = I2C_PORT_TCPC0,
-		.kbps = 1000,
-		.scl  = GPIO_EC_I2C_USB_C0_PD_SCL,
-		.sda  = GPIO_EC_I2C_USB_C0_PD_SDA
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_EEPROM_SCL,
-		.sda  = GPIO_EC_I2C_EEPROM_SDA
-	},
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_SENSOR_SCL,
-		.sda  = GPIO_EC_I2C_SENSOR_SDA
-	},
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_POWER_SCL,
+	  .sda = GPIO_EC_I2C_POWER_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C0_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C0_PD_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_EEPROM_SCL,
+	  .sda = GPIO_EC_I2C_EEPROM_SDA },
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_SENSOR_SCL,
+	  .sda = GPIO_EC_I2C_SENSOR_SDA },
 };
 
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
@@ -164,37 +154,22 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* Measure VBUS through a 1/10 voltage divider */
-	[ADC_VBUS] = {
-		"VBUS",
-		NPCX_ADC_CH1,
-		ADC_MAX_VOLT * 10,
-		ADC_READ_MAX + 1,
-		0
-	},
+	[ADC_VBUS] = { "VBUS", NPCX_ADC_CH1, ADC_MAX_VOLT * 10,
+		       ADC_READ_MAX + 1, 0 },
 	/*
 	 * Adapter current output or battery charging/discharging current (uV)
 	 * 18x amplification on charger side.
 	 */
-	[ADC_AMON_BMON] = {
-		"AMON_BMON",
-		NPCX_ADC_CH2,
-		ADC_MAX_VOLT * 1000 / 18,
-		ADC_READ_MAX + 1,
-		0
-	},
+	[ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH2, ADC_MAX_VOLT * 1000 / 18,
+			    ADC_READ_MAX + 1, 0 },
 	/*
 	 * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read
 	 * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and
 	 * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we
 	 * only divide by 2 (enough to avoid precision issues).
 	 */
-	[ADC_PSYS] = {
-		"PSYS",
-		NPCX_ADC_CH3,
-		ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1),
-		2,
-		0
-	},
+	[ADC_PSYS] = { "PSYS", NPCX_ADC_CH3,
+		       ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), 2, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
@@ -207,11 +182,9 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
 /* Power Path Controller */
 struct ppc_config_t ppc_chips[] = {
-	{
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
+	{ .i2c_port = I2C_PORT_TCPC0,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
 };
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
@@ -234,11 +207,14 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
  * to AP. But the TCPC chip is also needed to know the HPD status; otherwise,
  * the mux misbehaves.
  */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	},
 };
 
@@ -299,10 +275,8 @@ void board_hibernate(void)
 	 * Sensors are unpowered in hibernate. Apply PD to the
 	 * interrupt lines such that they don't float.
 	 */
-	gpio_set_flags(GPIO_ACCEL_GYRO_INT_L,
-		       GPIO_INPUT | GPIO_PULL_DOWN);
-	gpio_set_flags(GPIO_LID_ACCEL_INT_L,
-		       GPIO_INPUT | GPIO_PULL_DOWN);
+	gpio_set_flags(GPIO_ACCEL_GYRO_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
+	gpio_set_flags(GPIO_LID_ACCEL_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
 
 	/*
 	 * Board rev 2+ has the hardware fix. Don't need the following
@@ -351,9 +325,9 @@ void board_tcpc_init(void)
 	 */
 	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
 		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
 
 /* Called on AP S0 -> S3 transition */
 static void board_chipset_suspend(void)
@@ -431,8 +405,7 @@ void board_overcurrent_event(int port, int is_overcurrented)
 
 int board_set_active_charge_port(int port)
 {
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	int i;
 
 	if (!is_real_port && port != CHARGE_PORT_NONE)
@@ -460,7 +433,6 @@ int board_set_active_charge_port(int port)
 		return EC_ERROR_INVAL;
 	}
 
-
 	CPRINTS("New charge port: p%d", port);
 
 	/*
@@ -484,24 +456,22 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	/*
 	 * Ignore lower charge ceiling on PD transition if our battery is
 	 * critical, as we may brownout.
 	 */
-	if (supplier == CHARGE_SUPPLIER_PD &&
-	    charge_ma < 1500 &&
+	if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 &&
 	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
 		CPRINTS("Using max ilim %d", max_ma);
 		charge_ma = max_ma;
 	}
 
 	charge_ma = charge_ma * 95 / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 uint16_t tcpc_get_alert_status(void)
@@ -524,17 +494,13 @@ static struct accelgyro_saved_data_t g_bma255_data;
 static struct stprivate_data g_lis2dwl_data;
 
 /* Matrix to rotate accelerometer into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0,  0},
-	{ 0,  FLOAT_TO_FP(1),  0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+				       { 0, FLOAT_TO_FP(1), 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
 
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					     { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
@@ -644,11 +610,11 @@ static void board_detect_motionsensor(void)
 	int val = 0;
 
 	/*
-	 * BMA253 and LIS2DWL have same slave address, so we check the
+	 * BMA253 and LIS2DWL have same target address, so we check the
 	 * LIS2DWL WHO AM I register to check the lid accel type
 	 */
-	i2c_read8(I2C_PORT_SENSOR, LIS2DWL_ADDR0_FLAGS,
-		LIS2DW12_WHO_AM_I_REG, &val);
+	i2c_read8(I2C_PORT_SENSOR, LIS2DWL_ADDR0_FLAGS, LIS2DW12_WHO_AM_I_REG,
+		  &val);
 
 	if (val == LIS2DW12_WHO_AM_I) {
 		motion_sensors[LID_ACCEL] = lis2dwl_lid_accel;
diff --git a/board/pompom/board.h b/board/pompom/board.h
index 110774cb97..40e7185c16 100644
--- a/board/pompom/board.h
+++ b/board/pompom/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,7 +12,7 @@
 #include "board_revs.h"
 
 /* Internal SPI flash on NPCX7 */
-#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)  /* 512KB internal spi flash */
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */
 
 /* Keyboard */
 #define CONFIG_KEYBOARD_PROTOCOL_MKBP
@@ -72,12 +72,7 @@
 #include "gpio_signal.h"
 #include "registers.h"
 
-enum adc_channel {
-	ADC_VBUS,
-	ADC_AMON_BMON,
-	ADC_PSYS,
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_VBUS, ADC_AMON_BMON, ADC_PSYS, ADC_CH_COUNT };
 
 /* Motion sensors */
 enum sensor_id {
@@ -87,11 +82,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_DISPLIGHT,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_DISPLIGHT, PWM_CH_COUNT };
 
 enum battery_type {
 	BATTERY_BYD,
diff --git a/board/pompom/board_revs.h b/board/pompom/board_revs.h
index 1ac5ee1337..8edc249df0 100644
--- a/board/pompom/board_revs.h
+++ b/board/pompom/board_revs.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,7 +8,7 @@
 
 #define POMPOM_REV0 0
 #define POMPOM_REV1 1
-#define POMPOM_REV_LAST    POMPOM_REV1
+#define POMPOM_REV_LAST POMPOM_REV1
 #define POMPOM_REV_DEFAULT POMPOM_REV1
 
 #if !defined(BOARD_REV)
@@ -19,5 +19,4 @@
 #error "Board revision out of range"
 #endif
 
-
 #endif /* __CROS_EC_BOARD_REVS_H */
diff --git a/board/pompom/build.mk b/board/pompom/build.mk
index 04c90da3fe..8d302988f4 100644
--- a/board/pompom/build.mk
+++ b/board/pompom/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/pompom/ec.tasklist b/board/pompom/ec.tasklist
index 7ec8b46059..9145e6dd84 100644
--- a/board/pompom/ec.tasklist
+++ b/board/pompom/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/pompom/gpio.inc b/board/pompom/gpio.inc
index 531452eae3..3016f8b9d5 100644
--- a/board/pompom/gpio.inc
+++ b/board/pompom/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/pompom/led.c b/board/pompom/led.c
index db571a067c..31fccbf4e2 100644
--- a/board/pompom/led.c
+++ b/board/pompom/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -31,21 +31,21 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static void led_set_color_battery(enum led_color color)
 {
 	gpio_set_level(GPIO_EC_CHG_LED_Y_C0,
-		(color == LED_AMBER) ? LED_ON_LVL : LED_OFF_LVL);
+		       (color == LED_AMBER) ? LED_ON_LVL : LED_OFF_LVL);
 	gpio_set_level(GPIO_EC_CHG_LED_W_C0,
-		(color == LED_WHITE) ? LED_ON_LVL : LED_OFF_LVL);
+		       (color == LED_WHITE) ? LED_ON_LVL : LED_OFF_LVL);
 }
 
 void led_set_color_power(enum led_color color)
 {
 	gpio_set_level(GPIO_EC_PWR_LED_W,
-		(color == LED_WHITE) ? LED_ON_LVL : LED_OFF_LVL);
+		       (color == LED_WHITE) ? LED_ON_LVL : LED_OFF_LVL);
 }
 
 void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
@@ -82,7 +82,6 @@ static void board_led_set_battery(void)
 	static int battery_ticks;
 	int color = LED_OFF;
 	int period = 0;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
@@ -109,16 +108,16 @@ static void board_led_set_battery(void)
 		color = LED_WHITE;
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE) {
-			/* Factory mode: White 2 sec, Amber 2 sec */
-			period = (2 + 2);
-			battery_ticks = battery_ticks % period;
-			if (battery_ticks < 2)
-				color = LED_WHITE;
-			else
-				color = LED_AMBER;
-		} else
+		color = LED_WHITE;
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		/* Factory mode: White 2 sec, Amber 2 sec */
+		period = (2 + 2);
+		battery_ticks = battery_ticks % period;
+		if (battery_ticks < 2)
 			color = LED_WHITE;
+		else
+			color = LED_AMBER;
 		break;
 	default:
 		/* Other states don't alter LED behavior */
diff --git a/board/pompom/usbc_config.c b/board/pompom/usbc_config.c
index aac136415d..5d30adb6e2 100644
--- a/board/pompom/usbc_config.c
+++ b/board/pompom/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,8 @@
 #include "console.h"
 #include "usb_pd.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 const struct charger_config_t chg_chips[] = {
 	{
diff --git a/board/poppy/base_detect_lux.c b/board/poppy/base_detect_lux.c
index c348eb681d..8b799a3dbd 100644
--- a/board/poppy/base_detect_lux.c
+++ b/board/poppy/base_detect_lux.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,8 +20,8 @@
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USB, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args)
 
 /* Base detection and debouncing */
 #define BASE_DETECT_DEBOUNCE_US (20 * MSEC)
@@ -44,7 +44,7 @@
 #define BASE_DISCONNECTED_CONNECT_MAX_MV 600
 
 #define BASE_DISCONNECTED_MIN_MV 2800
-#define BASE_DISCONNECTED_MAX_MV (ADC_MAX_VOLT+1)
+#define BASE_DISCONNECTED_MAX_MV (ADC_MAX_VOLT + 1)
 
 /*
  * When base is connected, then gets disconnected:
@@ -93,7 +93,7 @@ int board_is_base_connected(void)
 void board_enable_base_power(int enable)
 {
 	gpio_set_level(GPIO_PPVAR_VAR_BASE,
-		enable && current_base_status == BASE_CONNECTED);
+		       enable && current_base_status == BASE_CONNECTED);
 }
 
 /*
@@ -181,8 +181,7 @@ static void base_detect_deferred(void)
 retry:
 	print_base_detect_value("status unclear", v);
 	/* Unclear base status, schedule again in a while. */
-	hook_call_deferred(&base_detect_deferred_data,
-				   BASE_DETECT_RETRY_US);
+	hook_call_deferred(&base_detect_deferred_data, BASE_DETECT_RETRY_US);
 }
 
 void base_detect_interrupt(enum gpio_signal signal)
@@ -216,7 +215,7 @@ static void base_init(void)
 	hook_call_deferred(&base_detect_deferred_data, BASE_DETECT_DEBOUNCE_US);
 	gpio_enable_interrupt(GPIO_BASE_DET_A);
 }
-DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT+1);
+DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT + 1);
 
 void base_force_state(enum ec_set_base_state_cmd state)
 {
@@ -230,7 +229,7 @@ void base_force_state(enum ec_set_base_state_cmd state)
 		CPRINTS("BD forced disconnected");
 	} else {
 		hook_call_deferred(&base_detect_deferred_data,
-			BASE_DETECT_DEBOUNCE_US);
+				   BASE_DETECT_DEBOUNCE_US);
 		gpio_enable_interrupt(GPIO_BASE_DET_A);
 		CPRINTS("BD forced reset");
 	}
diff --git a/board/poppy/base_detect_poppy.c b/board/poppy/base_detect_poppy.c
index 0fde6fb8e6..e6ac6e8da7 100644
--- a/board/poppy/base_detect_poppy.c
+++ b/board/poppy/base_detect_poppy.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,8 +19,8 @@
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USB, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args)
 
 /* Base detection and debouncing */
 #define BASE_DETECT_DEBOUNCE_US (20 * MSEC)
@@ -101,7 +101,6 @@ static void base_detect_change(enum base_status status)
 		acpi_dptf_set_profile_num(DPTF_PROFILE_BASE_ATTACHED);
 	else
 		acpi_dptf_set_profile_num(DPTF_PROFILE_BASE_DETACHED);
-
 }
 
 /* Measure detection pin pulse duration (used to wake AP from deep S3). */
@@ -110,8 +109,8 @@ static uint32_t pulse_width;
 
 static void print_base_detect_value(int v, int tmp_pulse_width)
 {
-	CPRINTS("%s = %d (pulse %d)", adc_channels[ADC_BASE_DET].name,
-			v, tmp_pulse_width);
+	CPRINTS("%s = %d (pulse %d)", adc_channels[ADC_BASE_DET].name, v,
+		tmp_pulse_width);
 }
 
 static void base_detect_deferred(void)
@@ -243,7 +242,7 @@ static void base_init(void)
 	if (system_jumped_late() && chipset_in_state(CHIPSET_STATE_ON))
 		base_enable();
 }
-DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT+1);
+DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT + 1);
 
 void base_force_state(enum ec_set_base_state_cmd state)
 {
diff --git a/board/poppy/battery.c b/board/poppy/battery.c
index 4085651cc2..5006edf123 100644
--- a/board/poppy/battery.c
+++ b/board/poppy/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -14,14 +14,14 @@
 #include "gpio.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 static enum battery_present batt_pres_prev = BP_NOT_SURE;
 
 /* Shutdown mode parameter to write to manufacturer access register */
-#define SB_SHIP_MODE_REG	SB_MANUFACTURER_ACCESS
-#define SB_SHUTDOWN_DATA	0x0010
-#define SB_REVIVE_DATA		0x23a7
+#define SB_SHIP_MODE_REG SB_MANUFACTURER_ACCESS
+#define SB_SHUTDOWN_DATA 0x0010
+#define SB_REVIVE_DATA 0x23a7
 
 #if defined(BOARD_SORAKA) || defined(BOARD_LUX)
 static const struct battery_info info = {
@@ -86,8 +86,9 @@ static int battery_init(void)
 {
 	int batt_status;
 
-	return battery_status(&batt_status) ? 0 :
-		!!(batt_status & STATUS_INITIALIZED);
+	return battery_status(&batt_status) ?
+		       0 :
+		       !!(batt_status & STATUS_INITIALIZED);
 }
 
 /*
@@ -108,13 +109,13 @@ static int battery_check_disconnect(void)
 	uint8_t data[6];
 
 	/* Check if battery charging + discharging is disabled. */
-	rv = sb_read_mfgacc(PARAM_OPERATION_STATUS,
-			    SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data));
+	rv = sb_read_mfgacc(PARAM_OPERATION_STATUS, SB_ALT_MANUFACTURER_ACCESS,
+			    data, sizeof(data));
 	if (rv)
 		return BATTERY_DISCONNECT_ERROR;
 
-	if ((data[3] & (BATTERY_DISCHARGING_DISABLED |
-			BATTERY_CHARGING_DISABLED)) ==
+	if ((data[3] &
+	     (BATTERY_DISCHARGING_DISABLED | BATTERY_CHARGING_DISABLED)) ==
 	    (BATTERY_DISCHARGING_DISABLED | BATTERY_CHARGING_DISABLED))
 		return BATTERY_DISCONNECTED;
 
diff --git a/board/poppy/board.c b/board/poppy/board.c
index 3aa99c1161..a69fdd3f16 100644
--- a/board/poppy/board.c
+++ b/board/poppy/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -34,6 +34,7 @@
 #include "math_util.h"
 #include "motion_lid.h"
 #include "motion_sense.h"
+#include "panic.h"
 #include "pi3usb9281.h"
 #include "power.h"
 #include "power_button.h"
@@ -52,10 +53,10 @@
 #include "util.h"
 #include "espi.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define USB_PD_PORT_ANX74XX	0
+#define USB_PD_PORT_ANX74XX 0
 
 /* Minimum input current limit. */
 #define ILIM_MIN_MA 472
@@ -80,9 +81,9 @@ static void vbus_discharge_handler(void)
 {
 	if (system_get_board_version() >= 2) {
 		pd_set_vbus_discharge(0,
-				gpio_get_level(GPIO_USB_C0_VBUS_WAKE_L));
+				      gpio_get_level(GPIO_USB_C0_VBUS_WAKE_L));
 		pd_set_vbus_discharge(1,
-				gpio_get_level(GPIO_USB_C1_VBUS_WAKE_L));
+				      gpio_get_level(GPIO_USB_C1_VBUS_WAKE_L));
 	}
 }
 DECLARE_DEFERRED(vbus_discharge_handler);
@@ -154,16 +155,17 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* Base detection */
-	[ADC_BASE_DET] = {"BASE_DET", NPCX_ADC_CH0,
-			  ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_BASE_DET] = { "BASE_DET", NPCX_ADC_CH0, ADC_MAX_VOLT,
+			   ADC_READ_MAX + 1, 0 },
 	/* Vbus sensing (10x voltage divider). */
-	[ADC_VBUS] = {"VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
+	[ADC_VBUS] = { "VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT * 10,
+		       ADC_READ_MAX + 1, 0 },
 	/*
 	 * Adapter current output or battery charging/discharging current (uV)
 	 * 18x amplification on charger side.
 	 */
-	[ADC_AMON_BMON] = {"AMON_BMON", NPCX_ADC_CH1, ADC_MAX_VOLT*1000/18,
-			   ADC_READ_MAX+1, 0},
+	[ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH1, ADC_MAX_VOLT * 1000 / 18,
+			    ADC_READ_MAX + 1, 0 },
 #ifdef BOARD_LUX
 	/*
 	 * ISL9238 PSYS output is 1.44 uA/W over 12.4K resistor, to read
@@ -171,49 +173,39 @@ const struct adc_t adc_channels[] = {
 	 * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we
 	 * only divide by 2 (enough to avoid precision issues).
 	 */
-	[ADC_PSYS] = {"PSYS", NPCX_ADC_CH3,
-		      ADC_MAX_VOLT*56250*2/(ADC_READ_MAX+1), 2, 0},
+	[ADC_PSYS] = { "PSYS", NPCX_ADC_CH3,
+		       ADC_MAX_VOLT * 56250 * 2 / (ADC_READ_MAX + 1), 2, 0 },
 #endif
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* I2C port map */
-const struct i2c_port_t i2c_ports[]  = {
-	{
-		.name = "tcpc",
-		.port = NPCX_I2C_PORT0_0,
-		.kbps = 400,
-		.scl  = GPIO_I2C0_0_SCL,
-		.sda  = GPIO_I2C0_0_SDA
-	},
-	{
-		.name = "als",
-		.port = NPCX_I2C_PORT0_1,
-		.kbps = 400,
-		.scl  = GPIO_I2C0_1_SCL,
-		.sda  = GPIO_I2C0_1_SDA
-	},
-	{
-		.name = "charger",
-		.port = NPCX_I2C_PORT1,
-		.kbps = 100,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	},
-	{
-		.name = "pmic",
-		.port = NPCX_I2C_PORT2,
-		.kbps = 400,
-		.scl  = GPIO_I2C2_SCL,
-		.sda  = GPIO_I2C2_SDA
-	},
-	{
-		.name = "accelgyro",
-		.port = NPCX_I2C_PORT3,
-		.kbps = 400,
-		.scl  = GPIO_I2C3_SCL,
-		.sda  = GPIO_I2C3_SDA
-	},
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "tcpc",
+	  .port = NPCX_I2C_PORT0_0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_0_SCL,
+	  .sda = GPIO_I2C0_0_SDA },
+	{ .name = "als",
+	  .port = NPCX_I2C_PORT0_1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_1_SCL,
+	  .sda = GPIO_I2C0_1_SDA },
+	{ .name = "charger",
+	  .port = NPCX_I2C_PORT1,
+	  .kbps = 100,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "pmic",
+	  .port = NPCX_I2C_PORT2,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "accelgyro",
+	  .port = NPCX_I2C_PORT3,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -237,16 +229,22 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.driver = &anx74xx_tcpm_usb_mux_driver,
-		.hpd_update = &anx74xx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &anx74xx_tcpm_usb_mux_driver,
+				.hpd_update = &anx74xx_tcpc_update_hpd_status,
+			},
 	},
 	{
-		.usb_port = 1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	}
 };
 
@@ -271,7 +269,6 @@ const struct charger_config_t chg_chips[] = {
 	},
 };
 
-
 /**
  * Power on (or off) a single TCPC.
  * minimum on/off delays are included.
@@ -349,9 +346,9 @@ void board_tcpc_init(void)
 	 */
 	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
 		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
 
 uint16_t tcpc_get_alert_status(void)
 {
@@ -371,17 +368,17 @@ uint16_t tcpc_get_alert_status(void)
 }
 
 const struct temp_sensor_t temp_sensors[] = {
-	{"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0},
+	{ "Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0 },
 
 	/* These BD99992GW temp sensors are only readable in S0 */
-	{"Ambient", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM0},
-	{"Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM1},
-	{"DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM2},
-	{"eMMC", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM3},
+	{ "Ambient", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM0 },
+	{ "Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM1 },
+	{ "DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM2 },
+	{ "eMMC", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM3 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -397,8 +394,8 @@ static void board_report_pmic_fault(const char *str)
 	uint32_t info;
 
 	/* RESETIRQ1 -- Bit 4: VRFAULT */
-	if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x8, &vrfault)
-	    != EC_SUCCESS)
+	if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x8, &vrfault) !=
+	    EC_SUCCESS)
 		return;
 
 	if (!(vrfault & BIT(4)))
@@ -507,8 +504,7 @@ static void board_pmic_enable_slp_s0_vr_decay(void)
 	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x38, 0x7a);
 }
 
-__override void power_board_handle_host_sleep_event(
-		enum host_sleep_event state)
+__override void power_board_handle_host_sleep_event(enum host_sleep_event state)
 {
 	if (state == HOST_SLEEP_EVENT_S0IX_SUSPEND)
 		board_pmic_enable_slp_s0_vr_decay();
@@ -561,9 +557,9 @@ static void board_init(void)
 		 * force detection on both ports.
 		 */
 		gpio_set_flags(GPIO_USB_C0_VBUS_WAKE_L,
-			GPIO_INPUT | GPIO_PULL_DOWN);
+			       GPIO_INPUT | GPIO_PULL_DOWN);
 		gpio_set_flags(GPIO_USB_C1_VBUS_WAKE_L,
-			GPIO_INPUT | GPIO_PULL_DOWN);
+			       GPIO_INPUT | GPIO_PULL_DOWN);
 
 		vbus0_evt(GPIO_USB_C0_VBUS_WAKE_L);
 		vbus1_evt(GPIO_USB_C1_VBUS_WAKE_L);
@@ -582,10 +578,9 @@ static void board_init(void)
 	 */
 	if (system_get_board_version() >= 5)
 		gpio_set_flags(GPIO_LED_YELLOW_C0_OLD,
-			GPIO_INPUT | GPIO_PULL_UP);
+			       GPIO_INPUT | GPIO_PULL_UP);
 	else
-		gpio_set_flags(GPIO_LED_YELLOW_C0,
-			GPIO_INPUT | GPIO_PULL_UP);
+		gpio_set_flags(GPIO_LED_YELLOW_C0, GPIO_INPUT | GPIO_PULL_UP);
 
 #ifdef BOARD_SORAKA
 	/*
@@ -594,18 +589,12 @@ static void board_init(void)
 	 * for better S0ix/S3 power
 	 */
 	if (system_get_board_version() >= 4) {
-		gpio_set_flags(GPIO_WLAN_PE_RST,
-			GPIO_INPUT | GPIO_PULL_UP);
-		gpio_set_flags(GPIO_PP3300_DX_LTE,
-			GPIO_INPUT | GPIO_PULL_UP);
-		gpio_set_flags(GPIO_LTE_GPS_OFF_L,
-			GPIO_INPUT | GPIO_PULL_UP);
-		gpio_set_flags(GPIO_LTE_BODY_SAR_L,
-			GPIO_INPUT | GPIO_PULL_UP);
-		gpio_set_flags(GPIO_LTE_WAKE_L,
-			GPIO_INPUT | GPIO_PULL_UP);
-		gpio_set_flags(GPIO_LTE_OFF_ODL,
-			GPIO_INPUT | GPIO_PULL_UP);
+		gpio_set_flags(GPIO_WLAN_PE_RST, GPIO_INPUT | GPIO_PULL_UP);
+		gpio_set_flags(GPIO_PP3300_DX_LTE, GPIO_INPUT | GPIO_PULL_UP);
+		gpio_set_flags(GPIO_LTE_GPS_OFF_L, GPIO_INPUT | GPIO_PULL_UP);
+		gpio_set_flags(GPIO_LTE_BODY_SAR_L, GPIO_INPUT | GPIO_PULL_UP);
+		gpio_set_flags(GPIO_LTE_WAKE_L, GPIO_INPUT | GPIO_PULL_UP);
+		gpio_set_flags(GPIO_LTE_OFF_ODL, GPIO_INPUT | GPIO_PULL_UP);
 	}
 #endif
 
@@ -671,10 +660,12 @@ int board_set_active_charge_port(int charge_port)
 #endif
 		/* Make sure non-charging port is disabled */
 		gpio_set_level(charge_port ? GPIO_USB_C0_CHARGE_L :
-					     GPIO_USB_C1_CHARGE_L, 1);
+					     GPIO_USB_C1_CHARGE_L,
+			       1);
 		/* Enable charging port */
 		gpio_set_level(charge_port ? GPIO_USB_C1_CHARGE_L :
-					     GPIO_USB_C0_CHARGE_L, 0);
+					     GPIO_USB_C0_CHARGE_L,
+			       0);
 	}
 
 	return EC_SUCCESS;
@@ -688,8 +679,8 @@ int board_set_active_charge_port(int charge_port)
  * @param charge_ma     Desired charge limit (mA).
  * @param charge_mv     Negotiated charge voltage (mV).
  */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	/* Adjust ILIM according to measurements to eliminate overshoot. */
 	charge_ma = (charge_ma - 500) * 31 / 32 + 472;
@@ -706,8 +697,7 @@ void board_hibernate(void)
 	uart_flush_output();
 
 	/* Trigger PMIC shutdown. */
-	if (i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS,
-		       0x49, 0x01)) {
+	if (i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x49, 0x01)) {
 		/*
 		 * If we can't tell the PMIC to shutdown, instead reset
 		 * and don't start the AP. Hopefully we'll be able to
@@ -763,31 +753,23 @@ static struct opt3001_drv_data_t g_opt3001_data = {
 };
 
 /* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t mag_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0,  FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t mag_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				      { 0, FLOAT_TO_FP(1), 0 },
+				      { 0, 0, FLOAT_TO_FP(-1) } };
 
 #ifdef BOARD_SORAKA
-const mat33_fp_t lid_standard_ref = {
-	{ 0,  FLOAT_TO_FP(-1),  0},
-	{FLOAT_TO_FP(1),  0,  0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+				      { FLOAT_TO_FP(1), 0, 0 },
+				      { 0, 0, FLOAT_TO_FP(1) } };
 
 /* For rev3 and older */
-const mat33_fp_t lid_standard_ref_old = {
-	{FLOAT_TO_FP(-1),  0,  0},
-	{ 0,  FLOAT_TO_FP(-1),  0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t lid_standard_ref_old = { { FLOAT_TO_FP(-1), 0, 0 },
+					  { 0, FLOAT_TO_FP(-1), 0 },
+					  { 0, 0, FLOAT_TO_FP(1) } };
 #else
-const mat33_fp_t lid_standard_ref = {
-	{FLOAT_TO_FP(-1),  0,  0},
-	{ 0,  FLOAT_TO_FP(-1),  0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				      { 0, FLOAT_TO_FP(-1), 0 },
+				      { 0, 0, FLOAT_TO_FP(1) } };
 #endif
 
 struct motion_sensor_t motion_sensors[] = {
diff --git a/board/poppy/board.h b/board/poppy/board.h
index 46a6fa19d3..6f95a9abeb 100644
--- a/board/poppy/board.h
+++ b/board/poppy/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -64,8 +64,8 @@
 #define CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET
 #define CONFIG_CHIPSET_RESET_HOOK
 #define CONFIG_HOST_INTERFACE_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 #define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD
 
 /* Battery */
@@ -101,8 +101,8 @@
 #define CONFIG_CMD_CHARGER_ADC_AMON_BMON
 #define CONFIG_HOSTCMD_PD_CONTROL
 #define CONFIG_EXTPOWER_GPIO
-#undef   CONFIG_EXTPOWER_DEBOUNCE_MS
-#define  CONFIG_EXTPOWER_DEBOUNCE_MS 1000
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
+#define CONFIG_EXTPOWER_DEBOUNCE_MS 1000
 #define CONFIG_POWER_BUTTON
 #define CONFIG_POWER_BUTTON_X86
 #define CONFIG_POWER_COMMON
@@ -141,7 +141,7 @@
 #define CONFIG_TABLET_MODE
 #define CONFIG_TABLET_MODE_SWITCH
 
-#undef  CONFIG_UART_TX_BUF_SIZE
+#undef CONFIG_UART_TX_BUF_SIZE
 #define CONFIG_UART_TX_BUF_SIZE 2048
 
 /* USB */
@@ -172,28 +172,28 @@
 #define CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT 2
 
 /* Optional feature to configure npcx chip */
-#define NPCX_UART_MODULE2	1 /* 1:GPIO64/65 as UART */
-#define NPCX_JTAG_MODULE2	0 /* 0:GPIO21/17/16/20 as JTAG */
-#define NPCX_TACH_SEL2		0 /* 0:GPIO40/73 as TACH */
+#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART */
+#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 as JTAG */
+#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 as TACH */
 
 /* I2C ports */
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT0_0
-#define I2C_PORT_TCPC1		NPCX_I2C_PORT0_0
-#define I2C_PORT_ALS		NPCX_I2C_PORT0_1
-#define I2C_PORT_USB_CHARGER_1	NPCX_I2C_PORT0_1
-#define I2C_PORT_USB_CHARGER_0	NPCX_I2C_PORT1
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT1
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT1
-#define I2C_PORT_PMIC		NPCX_I2C_PORT2
-#define I2C_PORT_MP2949		NPCX_I2C_PORT2
-#define I2C_PORT_GYRO		NPCX_I2C_PORT3
-#define I2C_PORT_BARO		NPCX_I2C_PORT3
-#define I2C_PORT_ACCEL		I2C_PORT_GYRO
-#define I2C_PORT_THERMAL	I2C_PORT_PMIC
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0
+#define I2C_PORT_TCPC1 NPCX_I2C_PORT0_0
+#define I2C_PORT_ALS NPCX_I2C_PORT0_1
+#define I2C_PORT_USB_CHARGER_1 NPCX_I2C_PORT0_1
+#define I2C_PORT_USB_CHARGER_0 NPCX_I2C_PORT1
+#define I2C_PORT_CHARGER NPCX_I2C_PORT1
+#define I2C_PORT_BATTERY NPCX_I2C_PORT1
+#define I2C_PORT_PMIC NPCX_I2C_PORT2
+#define I2C_PORT_MP2949 NPCX_I2C_PORT2
+#define I2C_PORT_GYRO NPCX_I2C_PORT3
+#define I2C_PORT_BARO NPCX_I2C_PORT3
+#define I2C_PORT_ACCEL I2C_PORT_GYRO
+#define I2C_PORT_THERMAL I2C_PORT_PMIC
 
 /* I2C addresses */
-#define I2C_ADDR_BD99992_FLAGS	0x30
-#define I2C_ADDR_MP2949_FLAGS	0x20
+#define I2C_ADDR_BD99992_FLAGS 0x30
+#define I2C_ADDR_MP2949_FLAGS 0x20
 
 #ifndef __ASSEMBLER__
 
@@ -201,11 +201,11 @@
 #include "registers.h"
 
 enum temp_sensor_id {
-	TEMP_SENSOR_BATTERY,	/* BD99956GW TSENSE */
-	TEMP_SENSOR_AMBIENT,	/* BD99992GW SYSTHERM0 */
-	TEMP_SENSOR_CHARGER,	/* BD99992GW SYSTHERM1 */
-	TEMP_SENSOR_DRAM,	/* BD99992GW SYSTHERM2 */
-	TEMP_SENSOR_EMMC,	/* BD99992GW SYSTHERM3 */
+	TEMP_SENSOR_BATTERY, /* BD99956GW TSENSE */
+	TEMP_SENSOR_AMBIENT, /* BD99992GW SYSTHERM0 */
+	TEMP_SENSOR_CHARGER, /* BD99992GW SYSTHERM1 */
+	TEMP_SENSOR_DRAM, /* BD99992GW SYSTHERM2 */
+	TEMP_SENSOR_EMMC, /* BD99992GW SYSTHERM3 */
 	TEMP_SENSOR_COUNT
 };
 
@@ -238,16 +238,16 @@ enum adc_channel {
  * delay to turn on the power supply max is ~16ms.
  * delay to turn off the power supply max is about ~180ms.
  */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	250000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* delay to turn on/off vconn */
 
 /* Define typical operating power and max power */
-#define PD_OPERATING_POWER_MW		15000
-#define PD_MAX_POWER_MW			45000
-#define PD_MAX_CURRENT_MA		3000
-#define PD_MAX_VOLTAGE_MV		20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 45000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Board specific handlers */
 int board_get_version(void);
diff --git a/board/poppy/build.mk b/board/poppy/build.mk
index df32a7ca8f..36c55d3048 100644
--- a/board/poppy/build.mk
+++ b/board/poppy/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/poppy/ec.tasklist b/board/poppy/ec.tasklist
index 7591137bc9..4ee0b53a32 100644
--- a/board/poppy/ec.tasklist
+++ b/board/poppy/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/poppy/gpio.inc b/board/poppy/gpio.inc
index 286085d39c..63a8d3ce99 100644
--- a/board/poppy/gpio.inc
+++ b/board/poppy/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,14 +13,14 @@ GPIO_INT(USB_C1_PD_INT_ODL,	PIN(C, 5), GPIO_INT_FALLING,			tcpc_alert_event)
 #ifdef CONFIG_POWER_S0IX
 GPIO_INT(PCH_SLP_S0_L,		PIN(7, 5), GPIO_INT_BOTH,			power_signal_interrupt)
 #endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 #ifdef BOARD_LUX
 GPIO_INT(PCH_SLP_S3_L,		PIN(2, 2), GPIO_INT_BOTH,			power_signal_interrupt)
 #else
 GPIO_INT(PCH_SLP_S3_L,		PIN(7, 3), GPIO_INT_BOTH,			power_signal_interrupt)
 #endif
-#endif /* CONFIG_HOSTCMD_ESPI_VW_SLP_S3 */
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#endif /* CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3 */
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 GPIO_INT(PCH_SLP_S4_L,		PIN(8, 6), GPIO_INT_BOTH,			power_signal_interrupt)
 #endif
 GPIO_INT(PCH_SLP_SUS_L,		PIN(6, 2), GPIO_INT_BOTH,			power_signal_interrupt)
diff --git a/board/poppy/led.c b/board/poppy/led.c
index 0c2d7f1832..f388dd0326 100644
--- a/board/poppy/led.c
+++ b/board/poppy/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -31,17 +31,18 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static void side_led_set_color(int port, enum led_color color)
 {
 	int yellow_c0 = (system_get_board_version() >= 5) ?
-			GPIO_LED_YELLOW_C0 : GPIO_LED_YELLOW_C0_OLD;
+				GPIO_LED_YELLOW_C0 :
+				GPIO_LED_YELLOW_C0_OLD;
 	gpio_set_level(port ? GPIO_LED_YELLOW_C1 : yellow_c0,
-		(color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
+		       (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
 	gpio_set_level(port ? GPIO_LED_WHITE_C1 : GPIO_LED_WHITE_C0,
-		(color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF);
+		       (color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF);
 }
 
 void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
@@ -92,7 +93,6 @@ static void set_active_port_color(enum led_color color)
 static void board_led_set_battery(void)
 {
 	static int battery_ticks;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
@@ -104,8 +104,9 @@ static void board_led_set_battery(void)
 	case PWR_STATE_DISCHARGE:
 		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) {
 			if (charge_get_percent() <= 10)
-				side_led_set_color(0,
-				   (battery_ticks & 0x4) ? LED_WHITE : LED_OFF);
+				side_led_set_color(0, (battery_ticks & 0x4) ?
+							      LED_WHITE :
+							      LED_OFF);
 			else
 				side_led_set_color(0, LED_OFF);
 		}
@@ -114,18 +115,18 @@ static void board_led_set_battery(void)
 			side_led_set_color(1, LED_OFF);
 		break;
 	case PWR_STATE_ERROR:
-		set_active_port_color((battery_ticks & 0x2) ?
-				LED_WHITE : LED_OFF);
+		set_active_port_color((battery_ticks & 0x2) ? LED_WHITE :
+							      LED_OFF);
 		break;
 	case PWR_STATE_CHARGE_NEAR_FULL:
 		set_active_port_color(LED_WHITE);
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			set_active_port_color((battery_ticks & 0x4) ?
-					LED_AMBER : LED_OFF);
-		else
-			set_active_port_color(LED_WHITE);
+		set_active_port_color(LED_WHITE);
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		set_active_port_color((battery_ticks & 0x4) ? LED_AMBER :
+							      LED_OFF);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
diff --git a/board/poppy/usb_pd_policy.c b/board/poppy/usb_pd_policy.c
index a32b77bbe7..ec2ea00076 100644
--- a/board/poppy/usb_pd_policy.c
+++ b/board/poppy/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,12 +22,12 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT];
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5,
-							TYPEC_RP_1A5};
+static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5,
+							 TYPEC_RP_1A5 };
 
 int board_vbus_source_enabled(int port)
 {
@@ -48,8 +48,8 @@ static void board_vbus_update_source_current(int port)
 		 * is controlled by GPIO_USB_C0/1_5V_EN. Both of these signals
 		 * can remain outputs.
 		 */
-		gpio_set_level(gpio_3a_en, vbus_rp[port] == TYPEC_RP_3A0 ?
-				1 : 0);
+		gpio_set_level(gpio_3a_en,
+			       vbus_rp[port] == TYPEC_RP_3A0 ? 1 : 0);
 		gpio_set_level(gpio_5v_en, vbus_en[port]);
 	} else {
 		/*
@@ -61,8 +61,8 @@ static void board_vbus_update_source_current(int port)
 		 * 1505 mA.
 		 */
 		int flags = (vbus_rp[port] == TYPEC_RP_1A5 && vbus_en[port]) ?
-			(GPIO_INPUT | GPIO_PULL_UP) :
-			(GPIO_OUTPUT | GPIO_PULL_UP);
+				    (GPIO_INPUT | GPIO_PULL_UP) :
+				    (GPIO_OUTPUT | GPIO_PULL_UP);
 		gpio_set_level(gpio_5v_en, vbus_en[port]);
 		gpio_set_flags(gpio_5v_en, flags);
 	}
@@ -79,8 +79,7 @@ void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
 int pd_set_power_supply_ready(int port)
 {
 	/* Disable charging */
-	gpio_set_level(port ? GPIO_USB_C1_CHARGE_L :
-			      GPIO_USB_C0_CHARGE_L, 1);
+	gpio_set_level(port ? GPIO_USB_C1_CHARGE_L : GPIO_USB_C0_CHARGE_L, 1);
 
 	/* Ensure we advertise the proper available current quota */
 	charge_manager_source_port(port, 1);
@@ -131,15 +130,13 @@ int pd_check_vconn_swap(int port)
 	return gpio_get_level(GPIO_PMIC_SLP_SUS_L);
 }
 
-__override void pd_execute_data_swap(int port,
-				     enum pd_data_role data_role)
+__override void pd_execute_data_swap(int port, enum pd_data_role data_role)
 {
 	/* Only port 0 supports device mode. */
 	if (port != 0)
 		return;
 
-	gpio_set_level(GPIO_USB2_OTG_ID,
-		      (data_role == PD_ROLE_UFP) ? 1 : 0);
+	gpio_set_level(GPIO_USB2_OTG_ID, (data_role == PD_ROLE_UFP) ? 1 : 0);
 	gpio_set_level(GPIO_USB2_OTG_VBUSSENSE,
-		      (data_role == PD_ROLE_UFP) ? 1 : 0);
+		       (data_role == PD_ROLE_UFP) ? 1 : 0);
 }
diff --git a/board/primus/battery.c b/board/primus/battery.c
index e9e822f2e8..1b0d74bed3 100644
--- a/board/primus/battery.c
+++ b/board/primus/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -32,7 +32,7 @@
  * address, mask, and disconnect value need to be provided.
  */
 const struct board_batt_params board_battery_info[] = {
-	[BATTERY_SUNWODA] = {
+	[BATTERY_SUNWODA_5B11F21946] = {
 		.fuel_gauge = {
 			.manuf_name = "Sunwoda",
 			.device_name = "LNV-5B11F21946",
@@ -61,7 +61,36 @@ const struct board_batt_params board_battery_info[] = {
 		},
 	},
 
-	[BATTERY_SMP] = {
+	[BATTERY_SUNWODA_5B11H56342] = {
+		.fuel_gauge = {
+			.manuf_name = "Sunwoda",
+			.device_name = "LNV-5B11H56342",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0000,
+				.reg_mask = 0x6000,
+				.disconnect_val = 0x6000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13200, /* mV */
+			.voltage_normal		= 11520, /* mV */
+			.voltage_min		= 9000,  /* mV */
+			.precharge_current	= 251,	 /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 60,
+		},
+	},
+
+	[BATTERY_SMP_5B11F21953] = {
 		.fuel_gauge = {
 			.manuf_name = "SMP",
 			.device_name = "LNV-5B11F21953",
@@ -90,7 +119,36 @@ const struct board_batt_params board_battery_info[] = {
 		},
 	},
 
-	[BATTERY_CELXPERT] = {
+	[BATTERY_SMP_5B11H56344] = {
+		.fuel_gauge = {
+			.manuf_name = "SMP",
+			.device_name = "LNV-5B11H56344",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0000,
+				.reg_mask = 0x6000,
+				.disconnect_val = 0x6000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13200, /* mV */
+			.voltage_normal		= 11520, /* mV */
+			.voltage_min		= 9000,  /* mV */
+			.precharge_current	= 250,	 /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 60,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 60,
+		},
+	},
+
+	[BATTERY_CELXPERT_5B11F21941] = {
 		.fuel_gauge = {
 			.manuf_name = "Celxpert",
 			.device_name = "LNV-5B11F21941",
@@ -118,7 +176,36 @@ const struct board_batt_params board_battery_info[] = {
 			.discharging_max_c	= 70,
 		},
 	},
+
+	[BATTERY_CELXPERT_5B11H56343] = {
+		.fuel_gauge = {
+			.manuf_name = "Celxpert",
+			.device_name = "LNV-5B11H56343",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0000,
+				.reg_mask = 0x6000,
+				.disconnect_val = 0x6000,
+			}
+		},
+		.batt_info = {
+			.voltage_max		= 13200, /* mV */
+			.voltage_normal		= 11520, /* mV */
+			.voltage_min		= 9000,  /* mV */
+			.precharge_current	= 487,	 /* mA */
+			.start_charging_min_c	= 0,
+			.start_charging_max_c	= 50,
+			.charging_min_c		= 0,
+			.charging_max_c		= 60,
+			.discharging_min_c	= -20,
+			.discharging_max_c	= 70,
+		},
+	},
 };
 BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
 
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SUNWODA;
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SUNWODA_5B11F21946;
diff --git a/board/primus/board.c b/board/primus/board.c
index d0fa9f6cae..8b5f1a86fc 100644
--- a/board/primus/board.c
+++ b/board/primus/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -30,8 +30,8 @@
 #include "gpio_list.h" /* Must come after other header files. */
 
 /* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 #define KBLIGHT_LED_ON_LVL 100
 #define KBLIGHT_LED_OFF_LVL 0
@@ -93,8 +93,8 @@ int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
 	}
 
 	if (voltage < BC12_MIN_VOLTAGE) {
-		CPRINTS("%s: port %d: vbus %d lower than %d", __func__,
-			port, voltage, BC12_MIN_VOLTAGE);
+		CPRINTS("%s: port %d: vbus %d lower than %d", __func__, port,
+			voltage, BC12_MIN_VOLTAGE);
 		return 1;
 	}
 
@@ -123,7 +123,7 @@ static void keyboard_init(void)
 DECLARE_HOOK(HOOK_INIT, keyboard_init, HOOK_PRIO_DEFAULT);
 
 __override void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+				       int max_ma, int charge_mv)
 {
 	/*
 	 * Need to set different input current limit depend on system state.
@@ -131,15 +131,14 @@ __override void board_set_charge_limit(int port, int supplier, int charge_ma,
 	 */
 
 	if (((max_ma == PD_MAX_CURRENT_MA) &&
-		chipset_in_state(CHIPSET_STATE_ANY_OFF)) ||
-		(max_ma != PD_MAX_CURRENT_MA))
+	     chipset_in_state(CHIPSET_STATE_ANY_OFF)) ||
+	    (max_ma != PD_MAX_CURRENT_MA))
 		charge_ma = charge_ma * 97 / 100;
 	else
 		charge_ma = charge_ma * 93 / 100;
 
-	charge_set_input_current_limit(MAX(charge_ma,
-					CONFIG_CHARGER_INPUT_CURRENT),
-					charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 static void configure_input_current_limit(void)
@@ -155,16 +154,16 @@ static void configure_input_current_limit(void)
 	adapter_current_ma = charge_manager_get_charger_current();
 
 	if ((adapter_current_ma == PD_MAX_CURRENT_MA) &&
-		chipset_in_or_transitioning_to_state(CHIPSET_STATE_SUSPEND))
+	    chipset_in_or_transitioning_to_state(CHIPSET_STATE_SUSPEND))
 		adapter_current_ma = PD_MAX_SUSPEND_CURRENT_MA;
 	else
 		adapter_current_ma = adapter_current_ma * 97 / 100;
 
 	charge_set_input_current_limit(MAX(adapter_current_ma,
-					CONFIG_CHARGER_INPUT_CURRENT),
-					adapter_current_mv);
+					   CONFIG_CHARGER_INPUT_CURRENT),
+				       adapter_current_mv);
 }
 DECLARE_HOOK(HOOK_CHIPSET_STARTUP, configure_input_current_limit,
-		HOOK_PRIO_DEFAULT);
+	     HOOK_PRIO_DEFAULT);
 DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN_COMPLETE, configure_input_current_limit,
-		HOOK_PRIO_DEFAULT);
+	     HOOK_PRIO_DEFAULT);
diff --git a/board/primus/board.h b/board/primus/board.h
index 0b118efb6d..7346acc2ab 100644
--- a/board/primus/board.h
+++ b/board/primus/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -31,29 +31,29 @@
 #undef CONFIG_VOLUME_BUTTONS
 
 /* USB Type A Features */
-#define USB_PORT_COUNT			1
+#define USB_PORT_COUNT 1
 #define CONFIG_USB_PORT_POWER_DUMB
 
 /* USB Type C and USB PD defines */
 #define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
 
-#undef  CONFIG_USB_PD_TCPM_NCT38XX
+#undef CONFIG_USB_PD_TCPM_NCT38XX
 #define CONFIG_USB_PD_TCPM_RT1715
 #define CONFIG_USBC_RETIMER_INTEL_BB
 
 #define CONFIG_USBC_PPC_SYV682X
 
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
 
 /*
  * Passive USB-C cables only support up to 60W.
  */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		65000
-#define PD_MAX_CURRENT_MA	3250
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 65000
+#define PD_MAX_CURRENT_MA 3250
+#define PD_MAX_VOLTAGE_MV 20000
 
 /*
  * Macros for GPIO signals used in common code that don't match the
@@ -61,33 +61,33 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT		GPIO_EC_EN_EDP_BL
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_GSC_PACKET_MODE
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SYS_SLP_S0IX_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_TEMP_SENSOR_POWER		GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
 
 /*
  * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
  * signal.
  */
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_SEQ_EC_ALL_SYS_PG
-#define GPIO_PG_EC_DSW_PWROK		GPIO_SEQ_EC_DSW_PWROK
-#define GPIO_PG_EC_RSMRST_ODL		GPIO_SEQ_EC_RSMRST_ODL
-#define GPIO_POWER_BUTTON_L		GPIO_GSC_EC_PWR_BTN_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_ODL
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
 
-#define GPIO_ID_1_EC_KB_BL_EN		GPIO_EC_BATT_PRES_ODL
+#define GPIO_ID_1_EC_KB_BL_EN GPIO_EC_BATT_PRES_ODL
 
 /* System has back-lit keyboard */
 #define CONFIG_PWM_KBLIGHT
@@ -97,23 +97,23 @@
 
 /* I2C Bus Configuration */
 
-#define I2C_PORT_USB_C0_TCPC		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1_TCPC		NPCX_I2C_PORT4_1
-#define I2C_PORT_USB_C0_C1_PPC_BC	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C0_C1_BC12		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C0_C1_RT		NPCX_I2C_PORT3_0
-#define I2C_PORT_BATTERY		NPCX_I2C_PORT5_0
-#define I2C_PORT_USB_A0_A1_MIX		NPCX_I2C_PORT6_1
-#define I2C_PORT_CHARGER		NPCX_I2C_PORT7_0
-#define I2C_PORT_EEPROM			NPCX_I2C_PORT7_0
-#define I2C_PORT_MP2964			NPCX_I2C_PORT7_0
+#define I2C_PORT_USB_C0_TCPC NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1
+#define I2C_PORT_USB_C0_C1_PPC_BC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C0_C1_BC12 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C0_C1_RT NPCX_I2C_PORT3_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_USB_A0_A1_MIX NPCX_I2C_PORT6_1
+#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0
 
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 
-#define I2C_ADDR_MP2964_FLAGS	0x20
+#define I2C_ADDR_MP2964_FLAGS 0x20
 
-#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR	0x56
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x57
+#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x56
+#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x57
 
 /* Enabling Thunderbolt-compatible mode */
 #define CONFIG_USB_PD_TBT_COMPAT_MODE
@@ -135,19 +135,19 @@
 
 /* Fan features */
 #define CONFIG_CUSTOM_FAN_CONTROL
-#define CONFIG_FANS			FAN_CH_COUNT
-#define RPM_DEVIATION	1
+#define CONFIG_FANS FAN_CH_COUNT
+#define RPM_DEVIATION 1
 
 /* Charger defines */
 #define CONFIG_CHARGER_BQ25720
 #define CONFIG_CHARGER_BQ25720_VSYS_TH2_CUSTOM
-#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV	70
+#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV 70
 #define CONFIG_CHARGE_RAMP_SW
-#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10
 
 /* PROCHOT defines */
-#define BATT_MAX_CONTINUE_DISCHARGE_WATT    66
+#define BATT_MAX_CONTINUE_DISCHARGE_WATT 66
 
 /* Prochot assertion/deassertion ratios*/
 #define PROCHOT_ADAPTER_WATT_RATIO 97
@@ -164,11 +164,11 @@
 #define CONFIG_8042_AUX
 #define CONFIG_PS2
 #define CONFIG_CMD_PS2
-#define PRIMUS_PS2_CH		NPCX_PS2_CH1
+#define PRIMUS_PS2_CH NPCX_PS2_CH1
 
 #ifndef __ASSEMBLER__
 
-#include "gpio_signal.h"	/* needed by registers.h */
+#include "gpio_signal.h" /* needed by registers.h */
 #include "registers.h"
 #include "usbc_config.h"
 
@@ -201,31 +201,28 @@ enum sensor_id {
 };
 
 enum battery_type {
-	BATTERY_SUNWODA,
-	BATTERY_SMP,
-	BATTERY_CELXPERT,
+	BATTERY_SUNWODA_5B11F21946,
+	BATTERY_SUNWODA_5B11H56342,
+	BATTERY_SMP_5B11F21953,
+	BATTERY_SMP_5B11H56344,
+	BATTERY_CELXPERT_5B11F21941,
+	BATTERY_CELXPERT_5B11H56343,
 	BATTERY_TYPE_COUNT
 };
 
 enum pwm_channel {
-	PWM_CH_LED2_WHITE = 0,	/* PWM0 (white charger) */
-	PWM_CH_TKP_A_LED_N,		/* PWM1 (LOGO led on A cover) */
-	PWM_CH_LED1_AMBER,		/* PWM2 (orange charger) */
-	PWM_CH_KBLIGHT,			/* PWM3 */
-	PWM_CH_FAN,			/* PWM5 */
-	PWM_CH_LED4,			/* PWM7 (power) */
+	PWM_CH_LED2_WHITE = 0, /* PWM0 (white charger) */
+	PWM_CH_TKP_A_LED_N, /* PWM1 (LOGO led on A cover) */
+	PWM_CH_LED1_AMBER, /* PWM2 (orange charger) */
+	PWM_CH_KBLIGHT, /* PWM3 */
+	PWM_CH_FAN, /* PWM5 */
+	PWM_CH_LED4, /* PWM7 (power) */
 	PWM_CH_COUNT
 };
 
-enum fan_channel {
-	FAN_CH_0 = 0,
-	FAN_CH_COUNT
-};
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT };
 
-enum mft_channel {
-	MFT_CH_0 = 0,
-	MFT_CH_COUNT
-};
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT };
 
 #endif /* !__ASSEMBLER__ */
 
diff --git a/board/primus/build.mk b/board/primus/build.mk
index ddf50b46e2..409a9dd45e 100644
--- a/board/primus/build.mk
+++ b/board/primus/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/primus/cbi_ssfc.c b/board/primus/cbi_ssfc.c
index dd59bb2c9f..45afa622ab 100644
--- a/board/primus/cbi_ssfc.c
+++ b/board/primus/cbi_ssfc.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/primus/cbi_ssfc.h b/board/primus/cbi_ssfc.h
index d1ad8c991f..fe4c2fb4e5 100644
--- a/board/primus/cbi_ssfc.h
+++ b/board/primus/cbi_ssfc.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/primus/charger.c b/board/primus/charger.c
index 476ce97df2..a4fa209246 120000..100644
--- a/board/primus/charger.c
+++ b/board/primus/charger.c
@@ -1 +1,90 @@
-../../baseboard/brya/charger_bq25720.c
\ No newline at end of file
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+
+#include "charge_manager.h"
+#include "charge_state_v2.h"
+#include "charger.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/charger/bq25710.h"
+#include "usbc_ppc.h"
+#include "usb_pd.h"
+#include "util.h"
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+#ifndef CONFIG_ZEPHYR
+/* Charger Chip Configuration */
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = BQ25710_SMBUS_ADDR1_FLAGS,
+		.drv = &bq25710_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CHARGER_NUM);
+#endif
+
+int board_set_active_charge_port(int port)
+{
+	int is_valid_port = board_is_usb_pd_port_present(port);
+	int i;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTSUSB("Disabling all charger ports");
+
+		/* Disable all ports. */
+		for (i = 0; i < ppc_cnt; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (ppc_vbus_sink_enable(i, 0))
+				CPRINTSUSB("Disabling C%d as sink failed.", i);
+		}
+
+		return EC_SUCCESS;
+	} else if (!is_valid_port) {
+		return EC_ERROR_INVAL;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (ppc_is_sourcing_vbus(port)) {
+		CPRINTFUSB("Skip enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTSUSB("New charge port: C%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < ppc_cnt; i++) {
+		if (i == port)
+			continue;
+
+		if (ppc_vbus_sink_enable(i, 0))
+			CPRINTSUSB("C%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTSUSB("C%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+__overridable void board_set_charge_limit(int port, int supplier, int charge_ma,
+					  int max_ma, int charge_mv)
+{
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+}
diff --git a/board/primus/ec.tasklist b/board/primus/ec.tasklist
index bf2ec04c62..3afcca805e 100644
--- a/board/primus/ec.tasklist
+++ b/board/primus/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/primus/fans.c b/board/primus/fans.c
index 001c6fde5c..b3c72c074b 100644
--- a/board/primus/fans.c
+++ b/board/primus/fans.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,7 +25,7 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 static const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
diff --git a/board/primus/fw_config.c b/board/primus/fw_config.c
index 0384d05b9d..82ba396901 100644
--- a/board/primus/fw_config.c
+++ b/board/primus/fw_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,7 +9,7 @@
 #include "cros_board_info.h"
 #include "fw_config.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 static union primus_cbi_fw_config fw_config;
 BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
diff --git a/board/primus/fw_config.h b/board/primus/fw_config.h
index f8792f1443..81fa5481f8 100644
--- a/board/primus/fw_config.h
+++ b/board/primus/fw_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,21 +25,18 @@ enum ec_cfg_keyboard_backlight_type {
 	KEYBOARD_BACKLIGHT_ENABLED = 1
 };
 
-enum ec_cfg_mlb_usb {
-	MLB_USB_TBT = 0,
-	MLB_USB_USB4 = 1
-};
+enum ec_cfg_mlb_usb { MLB_USB_TBT = 0, MLB_USB_USB4 = 1 };
 
 union primus_cbi_fw_config {
 	struct {
-		enum ec_cfg_usb_db_type			usb_db : 4;
-		uint32_t				sd_db : 2;
-		uint32_t				reserved_0 : 1;
-		enum ec_cfg_keyboard_backlight_type	kb_bl : 1;
-		uint32_t				audio : 3;
-		uint32_t				cellular_db : 2;
-		enum ec_cfg_mlb_usb			mlb_usb : 1;
-		uint32_t				reserved_1 : 18;
+		enum ec_cfg_usb_db_type usb_db : 4;
+		uint32_t sd_db : 2;
+		uint32_t reserved_0 : 1;
+		enum ec_cfg_keyboard_backlight_type kb_bl : 1;
+		uint32_t audio : 3;
+		uint32_t cellular_db : 2;
+		enum ec_cfg_mlb_usb mlb_usb : 1;
+		uint32_t reserved_1 : 18;
 	};
 	uint32_t raw_value;
 };
diff --git a/board/primus/gpio.inc b/board/primus/gpio.inc
index ce66027514..9928eb0cc5 100644
--- a/board/primus/gpio.inc
+++ b/board/primus/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/primus/i2c.c b/board/primus/i2c.c
index 019862f441..21939347b1 100644
--- a/board/primus/i2c.c
+++ b/board/primus/i2c.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/primus/keyboard.c b/board/primus/keyboard.c
index 5b45b60b19..9c9a37e9fc 100644
--- a/board/primus/keyboard.c
+++ b/board/primus/keyboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/primus/led.c b/board/primus/led.c
index 3a8da5ac32..70c1c89188 100644
--- a/board/primus/led.c
+++ b/board/primus/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,32 +24,30 @@
 #include "task.h"
 #include "timer.h"
 #include "util.h"
-#define CPRINTS(format, args...) cprints(CC_LOGOLED, format, ## args)
-
-#define LED_ON_LVL		100
-#define LED_OFF_LVL		0
-#define LED_BAT_S3_OFF_TIME_MS	3000
-#define LED_BAT_S3_TICK_MS	50
-#define LED_BAT_S3_PWM_RESCALE	5
-#define LED_TOTAL_TICKS		6
-#define TICKS_STEP1_BRIGHTER	0
-#define TICKS_STEP2_DIMMER	(1000 / LED_BAT_S3_TICK_MS)
-#define TICKS_STEP3_OFF		(2 * TICKS_STEP2_DIMMER)
-#define LED_ONE_SEC		(1000 / HOOK_TICK_INTERVAL_MS)
-#define LED_LOGO_TICK_SEC	(LED_ONE_SEC / 4)
+#define CPRINTS(format, args...) cprints(CC_LOGOLED, format, ##args)
+
+#define LED_ON_LVL 100
+#define LED_OFF_LVL 0
+#define LED_BAT_S3_OFF_TIME_MS 3000
+#define LED_BAT_S3_TICK_MS 50
+#define LED_BAT_S3_PWM_RESCALE 5
+#define LED_TOTAL_TICKS 6
+#define TICKS_STEP1_BRIGHTER 0
+#define TICKS_STEP2_DIMMER (1000 / LED_BAT_S3_TICK_MS)
+#define TICKS_STEP3_OFF (2 * TICKS_STEP2_DIMMER)
+#define LED_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS)
+#define LED_LOGO_TICK_SEC (LED_ONE_SEC / 4)
 /* Total on/off duration in a period */
-#define PERIOD			(LED_LOGO_TICK_SEC * 2)
-#define LED_ON			1
-#define LED_OFF			EC_LED_COLOR_COUNT
-#define LED_EVENT_SUSPEND	TASK_EVENT_CUSTOM_BIT(0)
-#define LED_EVENT_200MS_TICK	TASK_EVENT_CUSTOM_BIT(1)
+#define PERIOD (LED_LOGO_TICK_SEC * 2)
+#define LED_ON 1
+#define LED_OFF EC_LED_COLOR_COUNT
+#define LED_EVENT_SUSPEND TASK_EVENT_CUSTOM_BIT(0)
+#define LED_EVENT_200MS_TICK TASK_EVENT_CUSTOM_BIT(1)
 
 static int tick;
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 static void led_set_color_battery(enum ec_led_colors color)
@@ -94,11 +92,11 @@ void led_set_color_power(int onoff_status)
 	/* primus logo led and power led have same behavior. */
 	if (onoff_status == LED_ON) {
 		pwm_set_duty(PWM_CH_TKP_A_LED_N, LED_ON_LVL);
-		pwm_set_duty(PWM_CH_LED4,        LED_ON_LVL);
+		pwm_set_duty(PWM_CH_LED4, LED_ON_LVL);
 	} else {
 		/* LED_OFF and unsupported colors */
 		pwm_set_duty(PWM_CH_TKP_A_LED_N, LED_OFF_LVL);
-		pwm_set_duty(PWM_CH_LED4,        LED_OFF_LVL);
+		pwm_set_duty(PWM_CH_LED4, LED_OFF_LVL);
 	}
 }
 
@@ -176,7 +174,7 @@ static void suspend_led_update(void)
 		 * if we are not transitioning to suspend, we should break here.
 		 */
 		if (!chipset_in_or_transitioning_to_state(
-			CHIPSET_STATE_ANY_SUSPEND))
+			    CHIPSET_STATE_ANY_SUSPEND))
 			break;
 
 		/* 1s gradual on, 1s gradual off, 3s off */
@@ -187,9 +185,9 @@ static void suspend_led_update(void)
 			 * behavior.
 			 */
 			pwm_set_duty(PWM_CH_TKP_A_LED_N,
-				tick * LED_BAT_S3_PWM_RESCALE);
+				     tick * LED_BAT_S3_PWM_RESCALE);
 			pwm_set_duty(PWM_CH_LED4,
-				tick * LED_BAT_S3_PWM_RESCALE);
+				     tick * LED_BAT_S3_PWM_RESCALE);
 			msleep(LED_BAT_S3_TICK_MS);
 		} else if (tick <= TICKS_STEP3_OFF) {
 			/* decrease 5 duty every 50ms until PWM=0
@@ -197,10 +195,12 @@ static void suspend_led_update(void)
 			 * A-cover and power button led are shared same
 			 * behavior.
 			 */
-			pwm_set_duty(PWM_CH_TKP_A_LED_N, (TICKS_STEP3_OFF
-				- tick) * LED_BAT_S3_PWM_RESCALE);
-			pwm_set_duty(PWM_CH_LED4, (TICKS_STEP3_OFF
-				- tick) * LED_BAT_S3_PWM_RESCALE);
+			pwm_set_duty(PWM_CH_TKP_A_LED_N,
+				     (TICKS_STEP3_OFF - tick) *
+					     LED_BAT_S3_PWM_RESCALE);
+			pwm_set_duty(PWM_CH_LED4,
+				     (TICKS_STEP3_OFF - tick) *
+					     LED_BAT_S3_PWM_RESCALE);
 			msleep(LED_BAT_S3_TICK_MS);
 		} else {
 			tick = TICKS_STEP1_BRIGHTER;
diff --git a/board/primus/ps2.c b/board/primus/ps2.c
index ba341f6be0..2a0a764d5e 100644
--- a/board/primus/ps2.c
+++ b/board/primus/ps2.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,7 +15,7 @@
 #include "registers.h"
 #include "time.h"
 
-#define	PS2_TRANSMIT_DELAY_MS	10
+#define PS2_TRANSMIT_DELAY_MS 10
 
 static uint8_t queue_data[3];
 static int data_count;
@@ -39,8 +39,8 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
  */
 static void enable_ps2(void)
 {
-	gpio_set_alternate_function(GPIO_PORT_6,
-		BIT(2) | BIT(3), GPIO_ALT_FUNC_DEFAULT);
+	gpio_set_alternate_function(GPIO_PORT_6, BIT(2) | BIT(3),
+				    GPIO_ALT_FUNC_DEFAULT);
 }
 DECLARE_DEFERRED(enable_ps2);
 
@@ -48,8 +48,8 @@ static void disable_ps2(void)
 {
 	gpio_set_flags(GPIO_EC_PS2_SCL_TPAD, GPIO_ODR_LOW);
 	gpio_set_flags(GPIO_EC_PS2_SDA_TPAD, GPIO_ODR_LOW);
-	gpio_set_alternate_function(GPIO_PORT_6,
-		BIT(2) | BIT(3), GPIO_ALT_FUNC_NONE);
+	gpio_set_alternate_function(GPIO_PORT_6, BIT(2) | BIT(3),
+				    GPIO_ALT_FUNC_NONE);
 	/* make sure PLTRST# goes high and re-enable PS2.*/
 	hook_call_deferred(&enable_ps2_data, 2 * SECOND);
 }
@@ -96,7 +96,7 @@ uint8_t get_trackpoint_id(void)
 	 * Also make sure only return the trackpoint device ID.
 	 */
 	if (queue_data[1] == TP_VARIANT_ELAN ||
-		queue_data[1] == TP_VARIANT_SYNAPTICS)
+	    queue_data[1] == TP_VARIANT_SYNAPTICS)
 		return queue_data[1];
 	else
 		return 0;
@@ -129,10 +129,10 @@ static void ps2_suspend(void)
 	 */
 	if (trackpoint_id == TP_VARIANT_ELAN)
 		send_command_to_trackpoint(TP_TOGGLE_BURST,
-			TP_TOGGLE_ELAN_SLEEP);
+					   TP_TOGGLE_ELAN_SLEEP);
 	else if (trackpoint_id == TP_VARIANT_SYNAPTICS)
 		send_command_to_trackpoint(TP_TOGGLE_SOURCE_TAG,
-			TP_TOGGLE_SNAPTICS_SLEEP);
+					   TP_TOGGLE_SNAPTICS_SLEEP);
 
 	/* Clear the data in queue and the counter */
 	memset(queue_data, 0, ARRAY_SIZE(queue_data));
@@ -154,7 +154,7 @@ static void ps2_resume(void)
 	 */
 	if (trackpoint_id == TP_VARIANT_SYNAPTICS)
 		send_command_to_trackpoint(TP_TOGGLE_SOURCE_TAG,
-			TP_TOGGLE_SNAPTICS_SLEEP);
+					   TP_TOGGLE_SNAPTICS_SLEEP);
 
 	/* Clear the data in queue and the counter */
 	memset(queue_data, 0, ARRAY_SIZE(queue_data));
diff --git a/board/primus/ps2.h b/board/primus/ps2.h
index 0943d5ba4b..a82d6d566a 100644
--- a/board/primus/ps2.h
+++ b/board/primus/ps2.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,20 +12,20 @@
  * 0x01 was the original IBM trackpoint, others implement very limited
  * subset of trackpoint features.
  */
-#define TP_READ_ID			0xE1	/* Sent for device identification */
+#define TP_READ_ID 0xE1 /* Sent for device identification */
 
-#define TP_COMMAND			0xE2	/* Commands start with this */
+#define TP_COMMAND 0xE2 /* Commands start with this */
 
 /*
  * Toggling Flag bits
  */
-#define TP_TOGGLE			0x47	/* Toggle command */
+#define TP_TOGGLE 0x47 /* Toggle command */
 
-#define TP_VARIANT_ELAN			0x03
-#define TP_VARIANT_SYNAPTICS		0x06
-#define TP_TOGGLE_SOURCE_TAG		0x20
-#define TP_TOGGLE_BURST			0x28
-#define TP_TOGGLE_SNAPTICS_SLEEP	0x10
-#define TP_TOGGLE_ELAN_SLEEP		0x8
+#define TP_VARIANT_ELAN 0x03
+#define TP_VARIANT_SYNAPTICS 0x06
+#define TP_TOGGLE_SOURCE_TAG 0x20
+#define TP_TOGGLE_BURST 0x28
+#define TP_TOGGLE_SNAPTICS_SLEEP 0x10
+#define TP_TOGGLE_ELAN_SLEEP 0x8
 
 #endif /* __CROS_EC_PRIMUS_PS2_H */
diff --git a/board/primus/pwm.c b/board/primus/pwm.c
index 26ca6e5b92..f2889c2b8e 100644
--- a/board/primus/pwm.c
+++ b/board/primus/pwm.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/primus/sensors.c b/board/primus/sensors.c
index 60cfa1428f..9c0a9d69e8 100644
--- a/board/primus/sensors.c
+++ b/board/primus/sensors.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -59,36 +59,26 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* Temperature sensor configuration */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1_DDR_SOC] = {
-		.name = "DDR and SOC",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_1_DDR_SOC
-	},
-	[TEMP_SENSOR_2_SSD] = {
-		.name = "SSD",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_2_SSD
-	},
-	[TEMP_SENSOR_3_CHARGER] = {
-		.name = "Charger",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_3_CHARGER
-	},
-	[TEMP_SENSOR_4_MEMORY] = {
-		.name = "MEMORY",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_4_MEMORY
-	},
-	[TEMP_SENSOR_5_USBC] = {
-		.name = "USBC",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_5_USBC
-	},
+	[TEMP_SENSOR_1_DDR_SOC] = { .name = "DDR and SOC",
+				    .type = TEMP_SENSOR_TYPE_BOARD,
+				    .read = get_temp_3v3_30k9_47k_4050b,
+				    .idx = ADC_TEMP_SENSOR_1_DDR_SOC },
+	[TEMP_SENSOR_2_SSD] = { .name = "SSD",
+				.type = TEMP_SENSOR_TYPE_BOARD,
+				.read = get_temp_3v3_30k9_47k_4050b,
+				.idx = ADC_TEMP_SENSOR_2_SSD },
+	[TEMP_SENSOR_3_CHARGER] = { .name = "Charger",
+				    .type = TEMP_SENSOR_TYPE_BOARD,
+				    .read = get_temp_3v3_30k9_47k_4050b,
+				    .idx = ADC_TEMP_SENSOR_3_CHARGER },
+	[TEMP_SENSOR_4_MEMORY] = { .name = "MEMORY",
+				   .type = TEMP_SENSOR_TYPE_BOARD,
+				   .read = get_temp_3v3_30k9_47k_4050b,
+				   .idx = ADC_TEMP_SENSOR_4_MEMORY },
+	[TEMP_SENSOR_5_USBC] = { .name = "USBC",
+				 .type = TEMP_SENSOR_TYPE_BOARD,
+				 .read = get_temp_3v3_30k9_47k_4050b,
+				 .idx = ADC_TEMP_SENSOR_5_USBC },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -102,8 +92,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CPU \
-	{ \
+#define THERMAL_CPU              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(90), \
@@ -119,8 +109,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_SSD \
-	{ \
+#define THERMAL_SSD              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(92), \
@@ -149,8 +139,8 @@ __maybe_unused static const struct ec_thermal_config thermal_ssd = THERMAL_SSD;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_INDUCTOR \
-	{ \
+#define THERMAL_INDUCTOR         \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(90), \
diff --git a/board/primus/thermal.c b/board/primus/thermal.c
index f5e200b14c..00e2dddf98 100644
--- a/board/primus/thermal.c
+++ b/board/primus/thermal.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,9 +14,7 @@
 #include "util.h"
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_THERMAL, outstr)
-#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args)
-
-
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
 
 struct fan_step {
 	/*
@@ -36,51 +34,51 @@ struct fan_step {
 static const struct fan_step fan_table[] = {
 	{
 		/* level 0 */
-		.on = {40, -1, -1, -1, -1},
-		.off = {0, -1, -1, -1, -1},
-		.rpm = {0},
+		.on = { 40, -1, -1, -1, -1 },
+		.off = { 0, -1, -1, -1, -1 },
+		.rpm = { 0 },
 	},
 	{
 		/* level 1 */
-		.on = {42, -1, -1, -1, -1},
-		.off = {40, -1, -1, -1, -1},
-		.rpm = {1800},
+		.on = { 42, -1, -1, -1, -1 },
+		.off = { 40, -1, -1, -1, -1 },
+		.rpm = { 1800 },
 	},
 	{
 		/* level 2 */
-		.on = {43, -1, -1, -1, -1},
-		.off = {42, -1, -1, -1, -1},
-		.rpm = {2000},
+		.on = { 43, -1, -1, -1, -1 },
+		.off = { 42, -1, -1, -1, -1 },
+		.rpm = { 2000 },
 	},
 	{
 		/* level 3 */
-		.on = {44, -1, -1, -1, -1},
-		.off = {43, -1, -1, -1, -1},
-		.rpm = {2200},
+		.on = { 44, -1, -1, -1, -1 },
+		.off = { 43, -1, -1, -1, -1 },
+		.rpm = { 2200 },
 	},
 	{
 		/* level 4 */
-		.on = {45, -1, -1, -1, -1},
-		.off = {44, -1, -1, -1, -1},
-		.rpm = {2500},
+		.on = { 45, -1, -1, -1, -1 },
+		.off = { 44, -1, -1, -1, -1 },
+		.rpm = { 2500 },
 	},
 	{
 		/* level 5 */
-		.on = {46, -1, -1, -1, -1},
-		.off = {45, -1, -1, -1, -1},
-		.rpm = {2800},
+		.on = { 46, -1, -1, -1, -1 },
+		.off = { 45, -1, -1, -1, -1 },
+		.rpm = { 2800 },
 	},
 	{
 		/* level 6 */
-		.on = {47, -1, -1, -1, -1},
-		.off = {46, -1, -1, -1, -1},
-		.rpm = {3000},
+		.on = { 47, -1, -1, -1, -1 },
+		.off = { 46, -1, -1, -1, -1 },
+		.rpm = { 3000 },
 	},
 	{
 		/* level 7 */
-		.on = {75, -1, -1, -1, -1},
-		.off = {72, -1, -1, -1, -1},
-		.rpm = {3200},
+		.on = { 75, -1, -1, -1, -1 },
+		.off = { 72, -1, -1, -1, -1 },
+		.rpm = { 3200 },
 	},
 };
 const int num_fan_levels = ARRAY_SIZE(fan_table);
@@ -106,17 +104,14 @@ int fan_table_to_rpm(int fan, int *temp, enum temp_sensor_id temp_sensor)
 	 */
 	if (temp[temp_sensor] < prev_temp[temp_sensor]) {
 		for (i = current_level; i > 0; i--) {
-			if (temp[temp_sensor] <
-				fan_table[i].off[temp_sensor])
+			if (temp[temp_sensor] < fan_table[i].off[temp_sensor])
 				current_level = i - 1;
 			else
 				break;
 		}
-	} else if (temp[temp_sensor] >
-		prev_temp[temp_sensor]) {
+	} else if (temp[temp_sensor] > prev_temp[temp_sensor]) {
 		for (i = current_level; i < num_fan_levels; i++) {
-			if (temp[temp_sensor] >
-				fan_table[i].on[temp_sensor])
+			if (temp[temp_sensor] > fan_table[i].on[temp_sensor])
 				current_level = i + 1;
 			else
 				break;
@@ -148,7 +143,8 @@ void board_override_fan_control(int fan, int *temp)
 	if (chipset_in_state(CHIPSET_STATE_ON)) {
 		fan_set_rpm_mode(FAN_CH(fan), 1);
 		fan_set_rpm_target(FAN_CH(fan),
-			fan_table_to_rpm(FAN_CH(fan), temp, TEMP_SENSOR_1_DDR_SOC));
+				   fan_table_to_rpm(FAN_CH(fan), temp,
+						    TEMP_SENSOR_1_DDR_SOC));
 	} else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
 		/* Stop fan when enter S0ix */
 		fan_set_rpm_mode(FAN_CH(fan), 1);
diff --git a/board/primus/usbc_config.c b/board/primus/usbc_config.c
index ecaac56b2d..a11a8d588f 100644
--- a/board/primus/usbc_config.c
+++ b/board/primus/usbc_config.c
@@ -1,9 +1,8 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-
 #include <stdint.h>
 #include <stdbool.h>
 
@@ -32,8 +31,8 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 /* USBC TCPC configuration */
 const struct tcpc_config_t tcpc_config[] = {
@@ -75,33 +74,43 @@ BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
 /* USBC mux configuration - Alder Lake includes internal mux */
-static const struct usb_mux usbc0_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+static const struct usb_mux_chain usbc0_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
-static const struct usb_mux usbc1_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+static const struct usb_mux_chain usbc1_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
 
-const struct usb_mux usb_muxes[] = {
+const struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C0_C1_RT,
-		.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc0_tcss_usb_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C0_C1_RT,
+			.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc0_tcss_usb_mux,
 	},
 	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C0_C1_RT,
-		.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc1_tcss_usb_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C0_C1_RT,
+			.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc1_tcss_usb_mux,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
@@ -178,7 +187,6 @@ void board_reset_pd_mcu(void)
 
 static void board_tcpc_init(void)
 {
-
 	/* Don't reset TCPCs after initial reset */
 	if (!system_jumped_late()) {
 		board_reset_pd_mcu();
@@ -195,7 +203,6 @@ static void board_tcpc_init(void)
 	/* Enable BC1.2 interrupts. */
 	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
 	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
-
 }
 DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
 
diff --git a/board/primus/usbc_config.h b/board/primus/usbc_config.h
index 8bc1918c02..1e087f083c 100644
--- a/board/primus/usbc_config.h
+++ b/board/primus/usbc_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,13 +8,9 @@
 #ifndef __CROS_EC_USBC_CONFIG_H
 #define __CROS_EC_USBC_CONFIG_H
 
-#define CONFIG_USB_PD_PORT_MAX_COUNT	2
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 void config_usb_db_type(void);
 
diff --git a/board/prism/board.c b/board/prism/board.c
index dc5c042db1..1c7778f72f 100644
--- a/board/prism/board.c
+++ b/board/prism/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -37,20 +37,20 @@
 #define CROS_EC_SECTION "RO"
 #endif
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 /******************************************************************************
  * Define the strings used in our USB descriptors.
  */
 const void *const usb_strings[] = {
-	[USB_STR_DESC]         = usb_string_desc,
-	[USB_STR_VENDOR]       = USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]      = USB_STRING_DESC("Prism"),
-	[USB_STR_SERIALNO]     = 0,
-	[USB_STR_VERSION]      =
-			USB_STRING_DESC(CROS_EC_SECTION ":" CROS_EC_VERSION32),
-	[USB_STR_UPDATE_NAME]  = USB_STRING_DESC("Firmware update"),
-	[USB_STR_HOSTCMD_NAME]  = USB_STRING_DESC("Host command"),
+	[USB_STR_DESC] = usb_string_desc,
+	[USB_STR_VENDOR] = USB_STRING_DESC("Google LLC"),
+	[USB_STR_PRODUCT] = USB_STRING_DESC("Prism"),
+	[USB_STR_SERIALNO] = 0,
+	[USB_STR_VERSION] =
+		USB_STRING_DESC(CROS_EC_SECTION ":" CROS_EC_VERSION32),
+	[USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"),
+	[USB_STR_HOSTCMD_NAME] = USB_STRING_DESC("Host command"),
 };
 
 BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
@@ -61,10 +61,9 @@ BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
 
 #ifdef SECTION_IS_RW
 const struct spi_device_t spi_devices[] = {
-	[SPI_RGB0_DEVICE_ID] = {
-			CONFIG_SPI_RGB_PORT,
-			2, /* 2: Fpclk/8 = 48Mhz/8 = 6Mhz */
-			GPIO_SPI1_CS1_L },
+	[SPI_RGB0_DEVICE_ID] = { CONFIG_SPI_RGB_PORT, 2, /* 2: Fpclk/8 = 48Mhz/8
+							    = 6Mhz */
+				 GPIO_SPI1_CS1_L },
 	[SPI_RGB1_DEVICE_ID] = { CONFIG_SPI_RGB_PORT, 2, GPIO_SPI1_CS2_L },
 };
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
@@ -103,143 +102,141 @@ const uint8_t rgbkbd_count = ARRAY_SIZE(rgbkbds);
 const uint8_t rgbkbd_hsize = RGB_GRID0_COL + RGB_GRID1_COL;
 const uint8_t rgbkbd_vsize = RGB_GRID0_ROW;
 
-#define LED(x, y)	RGBKBD_COORD((x), (y))
-#define DELM		RGBKBD_DELM
+enum ec_rgbkbd_type rgbkbd_type = EC_RGBKBD_TYPE_PER_KEY;
+
+#define LED(x, y) RGBKBD_COORD((x), (y))
+#define DELM RGBKBD_DELM
+
 const uint8_t rgbkbd_map[] = {
-	DELM,				/* 0: (null) */
-	LED( 0, 1), DELM,		/* 1: ~ ` */
-	LED( 1, 1), LED( 1, 2), DELM,	/* 2: ! 1 */
-	LED( 2, 1), LED( 2, 2), DELM,	/* 3: @ 2 */
-	LED( 3, 1), LED( 3, 2), DELM,	/* 4: # 3 */
-	LED( 4, 1), LED( 4, 2), DELM,	/* 5: $ 4 */
-	LED( 5, 1), LED( 5, 2), DELM,	/* 6: % 5 */
-	LED( 6, 1), LED( 6, 2), DELM,	/* 7: ^ 6 */
-	LED( 7, 1), LED( 7, 2), DELM,	/* 8: & 7 */
-	LED( 8, 1), LED( 8, 2), DELM,	/* 9: * 8 */
-	LED( 9, 1), LED( 9, 2), DELM,	/* 10: ( 9 */
-	LED(10, 1), LED(10, 2), DELM,	/* 11: ) 0 */
-	LED(11, 1), LED(11, 2), DELM,	/* 12: _ - */
-	LED(12, 1), LED(12, 2), DELM,	/* 13: + = */
-	DELM,				/* 14: (null) */
-	LED(13, 1), LED(13, 2), DELM,	/* 15: backspace */
-	LED( 0, 3), DELM,		/* 16: tab */
-	LED( 1, 3), DELM,		/* 17: q */
-	LED( 2, 3), DELM,		/* 18: w */
-	LED( 3, 3), DELM,		/* 19: e */
-	LED( 4, 3), DELM,		/* 20: r */
-	LED( 5, 3), DELM,		/* 21: t */
-	LED( 6, 3), DELM,		/* 22: y */
-	LED( 7, 3), DELM,		/* 23: u */
-	LED( 8, 3), DELM,		/* 24: i */
-	LED( 9, 3), DELM,		/* 25: o */
-	LED(10, 3), DELM,		/* 26: p */
-	LED(11, 3), LED(12, 3), DELM,	/* 27: [ { */
-	LED(13, 3), LED(14, 3), DELM,	/* 28: ] } */
-	LED(15, 3), LED(16, 3), DELM,	/* 29: \ | */
-	LED( 0, 4), LED( 1, 4), DELM,	/* 30: caps lock */
-	LED( 2, 4), DELM,		/* 31: a */
-	LED( 3, 4), DELM,		/* 32: s */
-	LED( 4, 4), DELM,		/* 33: d */
-	LED( 5, 4), DELM,		/* 34: f */
-	LED( 6, 4), DELM,		/* 35: g */
-	LED( 7, 4), DELM,		/* 36: h */
-	LED( 8, 4), DELM,		/* 37: j */
-	LED( 9, 4), DELM,		/* 38: k */
-	LED(10, 4), DELM,		/* 39: l */
-	LED(11, 4), LED(12, 4), DELM,	/* 40: ; : */
-	LED(13, 4), LED(14, 4), DELM,	/* 41: " ' */
-	DELM,				/* 42: (null) */
-	LED(15, 4), LED(16, 4), DELM,	/* 43: enter */
-	LED( 0, 5), LED( 1, 5),
-	LED( 2, 5), DELM,		/* 44: L-shift */
-	DELM,				/* 45: (null) */
-	LED( 3, 5), DELM,		/* 46: z */
-	LED( 4, 5), DELM,		/* 47: x */
-	LED( 5, 5), DELM,		/* 48: c */
-	LED( 6, 5), DELM,		/* 49: v */
-	LED( 7, 5), DELM,		/* 50: b */
-	LED( 8, 5), DELM,		/* 51: n */
-	LED( 9, 5), DELM,		/* 52: m */
-	LED(10, 5), LED(11, 5), DELM,	/* 53: , < */
-	LED(12, 5), LED(13, 5), DELM,	/* 54: . > */
-	LED(14, 5), LED(15, 5), DELM,	/* 55: / ? */
-	DELM,				/* 56: (null) */
-	LED(16, 5), LED(17, 5),
-	LED(18, 5), DELM,		/* 57: R-shift */
-	LED(17, 4), LED(18, 4),
-	LED(19, 4), DELM,		/* 58: L-ctrl */
-	LED(15, 0), DELM,		/* 59: power */
-	LED(17, 2), LED(18, 2),
-	LED(19, 2), DELM,		/* 60: L-alt */
-	LED(17, 3), LED(18, 3),
-	LED(19, 3), LED(20, 3),
-	LED(21, 3), DELM,		/* 61: space */
-	LED(20, 2), DELM,		/* 62: R-alt */
-	DELM,				/* 63: (null) */
-	LED(21, 2), DELM,		/* 64: R-ctrl */
-	DELM,				/* 65: (null) */
-	DELM,				/* 66: (null) */
-	DELM,				/* 67: (null) */
-	DELM,				/* 68: (null) */
-	DELM,				/* 69: (null) */
-	DELM,				/* 70: (null) */
-	DELM,				/* 71: (null) */
-	DELM,				/* 72: (null) */
-	DELM,				/* 73: (null) */
-	DELM,				/* 74: (null) */
-	DELM,				/* 75: (null) */
-	DELM,				/* 76: (null) */
-	DELM,				/* 77: (null) */
-	DELM,				/* 78: (null) */
-	LED(19, 5), DELM,		/* 79: left */
-	DELM,				/* 80: (null) */
-	DELM,				/* 81: (null) */
-	DELM,				/* 82: (null) */
-	LED(20, 4), DELM,		/* 83: up */
-	LED(20, 5), DELM,		/* 84: down */
-	DELM,				/* 85: (null) */
-	DELM,				/* 86: (null) */
-	DELM,				/* 87: (null) */
-	DELM,				/* 88: (null) */
-	LED(21, 5), DELM,		/* 89: right */
-	DELM,				/* 90: (null) */
-	DELM,				/* 91: (null) */
-	DELM,				/* 92: (null) */
-	DELM,				/* 93: (null) */
-	DELM,				/* 94: (null) */
-	DELM,				/* 95: (null) */
-	DELM,				/* 96: (null) */
-	DELM,				/* 97: (null) */
-	DELM,				/* 98: (null) */
-	DELM,				/* 99: (null) */
-	DELM,				/* 100: (null) */
-	DELM,				/* 101: (null) */
-	DELM,				/* 102: (null) */
-	DELM,				/* 103: (null) */
-	DELM,				/* 104: (null) */
-	DELM,				/* 105: (null) */
-	DELM,				/* 106: (null) */
-	DELM,				/* 107: (null) */
-	DELM,				/* 108: (null) */
-	DELM,				/* 109: (null) */
-	LED( 0, 0), DELM,		/* 110: esc */
-	LED( 1, 0), DELM,		/* T1: previous page */
-	LED( 2, 0), DELM,		/* T2: refresh */
-	LED( 3, 0), DELM,		/* T3: full screen */
-	LED( 4, 0), DELM,		/* T4: windows */
-	LED( 5, 0), DELM,		/* T5: screenshot */
-	LED( 6, 0), DELM,		/* T6: brightness down */
-	LED( 7, 0), DELM,		/* T7: brightness up */
-	LED( 8, 0), DELM,		/* T8: KB backlight off */
-	LED( 9, 0), DELM,		/* T9: play/pause */
-	LED(10, 0), DELM,		/* T10: mute microphone */
-	LED(11, 0), DELM,		/* T11: mute speakers */
-	LED(12, 0), DELM,		/* T12: volume down */
-	LED(13, 0), DELM,		/* T13: volume up */
-	DELM,				/* T14: (null) */
-	DELM,				/* T15: (null) */
-	DELM,				/* 126: (null) */
-	DELM,				/* 127: (null) */
+	DELM, /* 0: (null) */
+	LED(0, 1),  LED(0, 2),	DELM, /* 1: ~ ` */
+	LED(1, 1),  LED(1, 2),	DELM, /* 2: ! 1 */
+	LED(2, 1),  LED(2, 2),	DELM, /* 3: @ 2 */
+	LED(3, 1),  LED(3, 2),	DELM, /* 4: # 3 */
+	LED(4, 1),  LED(4, 2),	DELM, /* 5: $ 4 */
+	LED(5, 1),  LED(5, 2),	DELM, /* 6: % 5 */
+	LED(6, 1),  LED(6, 2),	DELM, /* 7: ^ 6 */
+	LED(7, 1),  LED(7, 2),	DELM, /* 8: & 7 */
+	LED(8, 1),  LED(8, 2),	DELM, /* 9: * 8 */
+	LED(9, 1),  LED(9, 2),	DELM, /* 10: ( 9 */
+	LED(10, 1), LED(10, 2), DELM, /* 11: ) 0 */
+	LED(11, 1), LED(11, 2), DELM, /* 12: _ - */
+	LED(12, 1), LED(12, 2), DELM, /* 13: + = */
+	DELM, /* 14: (null) */
+	LED(13, 1), LED(13, 2), DELM, /* 15: backspace */
+	LED(0, 3),  LED(15, 2), DELM, /* 16: tab */
+	LED(1, 3),  DELM, /* 17: q */
+	LED(2, 3),  DELM, /* 18: w */
+	LED(3, 3),  DELM, /* 19: e */
+	LED(4, 3),  DELM, /* 20: r */
+	LED(5, 3),  DELM, /* 21: t */
+	LED(6, 3),  DELM, /* 22: y */
+	LED(7, 3),  DELM, /* 23: u */
+	LED(8, 3),  DELM, /* 24: i */
+	LED(9, 3),  DELM, /* 25: o */
+	LED(10, 3), DELM, /* 26: p */
+	LED(11, 3), LED(12, 3), DELM, /* 27: [ { */
+	LED(13, 3), LED(14, 3), DELM, /* 28: ] } */
+	LED(15, 3), LED(16, 3), DELM, /* 29: \ | */
+	LED(0, 4),  LED(1, 4),	DELM, /* 30: caps lock */
+	LED(2, 4),  DELM, /* 31: a */
+	LED(3, 4),  DELM, /* 32: s */
+	LED(4, 4),  DELM, /* 33: d */
+	LED(5, 4),  DELM, /* 34: f */
+	LED(6, 4),  DELM, /* 35: g */
+	LED(7, 4),  DELM, /* 36: h */
+	LED(8, 4),  DELM, /* 37: j */
+	LED(9, 4),  DELM, /* 38: k */
+	LED(10, 4), DELM, /* 39: l */
+	LED(11, 4), LED(12, 4), DELM, /* 40: ; : */
+	LED(13, 4), LED(14, 4), DELM, /* 41: " ' */
+	DELM, /* 42: (null) */
+	LED(15, 4), LED(16, 4), DELM, /* 43: enter */
+	LED(0, 5),  LED(1, 5),	LED(2, 5),  DELM, /* 44: L-shift */
+	DELM, /* 45: (null) */
+	LED(3, 5),  DELM, /* 46: z */
+	LED(4, 5),  DELM, /* 47: x */
+	LED(5, 5),  DELM, /* 48: c */
+	LED(6, 5),  DELM, /* 49: v */
+	LED(7, 5),  DELM, /* 50: b */
+	LED(8, 5),  DELM, /* 51: n */
+	LED(9, 5),  DELM, /* 52: m */
+	LED(10, 5), LED(11, 5), DELM, /* 53: , < */
+	LED(12, 5), LED(13, 5), DELM, /* 54: . > */
+	LED(14, 5), LED(15, 5), DELM, /* 55: / ? */
+	DELM, /* 56: (null) */
+	LED(16, 5), LED(17, 5), LED(18, 5), DELM, /* 57: R-shift */
+	LED(17, 4), LED(18, 4), LED(19, 4), DELM, /* 58: L-ctrl */
+	LED(15, 0), DELM, /* 59: power */
+	LED(17, 2), LED(18, 2), LED(19, 2), DELM, /* 60: L-alt */
+	LED(17, 3), LED(18, 3), LED(19, 3), LED(20, 3),
+	LED(21, 3), LED(16, 2), DELM, /* 61: space */
+	LED(20, 2), DELM, /* 62: R-alt */
+	DELM, /* 63: (null) */
+	LED(21, 2), DELM, /* 64: R-ctrl */
+	DELM, /* 65: (null) */
+	DELM, /* 66: (null) */
+	DELM, /* 67: (null) */
+	DELM, /* 68: (null) */
+	DELM, /* 69: (null) */
+	DELM, /* 70: (null) */
+	DELM, /* 71: (null) */
+	DELM, /* 72: (null) */
+	DELM, /* 73: (null) */
+	DELM, /* 74: (null) */
+	DELM, /* 75: (null) */
+	DELM, /* 76: (null) */
+	DELM, /* 77: (null) */
+	DELM, /* 78: (null) */
+	LED(19, 5), DELM, /* 79: left */
+	DELM, /* 80: (null) */
+	DELM, /* 81: (null) */
+	DELM, /* 82: (null) */
+	LED(20, 4), DELM, /* 83: up */
+	LED(20, 5), DELM, /* 84: down */
+	DELM, /* 85: (null) */
+	DELM, /* 86: (null) */
+	DELM, /* 87: (null) */
+	DELM, /* 88: (null) */
+	LED(21, 5), DELM, /* 89: right */
+	DELM, /* 90: (null) */
+	DELM, /* 91: (null) */
+	DELM, /* 92: (null) */
+	DELM, /* 93: (null) */
+	DELM, /* 94: (null) */
+	DELM, /* 95: (null) */
+	DELM, /* 96: (null) */
+	DELM, /* 97: (null) */
+	DELM, /* 98: (null) */
+	DELM, /* 99: (null) */
+	DELM, /* 100: (null) */
+	DELM, /* 101: (null) */
+	DELM, /* 102: (null) */
+	DELM, /* 103: (null) */
+	DELM, /* 104: (null) */
+	DELM, /* 105: (null) */
+	DELM, /* 106: (null) */
+	DELM, /* 107: (null) */
+	DELM, /* 108: (null) */
+	DELM, /* 109: (null) */
+	LED(0, 0),  DELM, /* 110: esc */
+	LED(1, 0),  DELM, /* T1: previous page */
+	LED(2, 0),  DELM, /* T2: refresh */
+	LED(3, 0),  DELM, /* T3: full screen */
+	LED(4, 0),  DELM, /* T4: windows */
+	LED(5, 0),  DELM, /* T5: screenshot */
+	LED(6, 0),  DELM, /* T6: brightness down */
+	LED(7, 0),  DELM, /* T7: brightness up */
+	LED(8, 0),  DELM, /* T8: KB backlight off */
+	LED(9, 0),  DELM, /* T9: play/pause */
+	LED(10, 0), DELM, /* T10: mute microphone */
+	LED(11, 0), DELM, /* T11: mute speakers */
+	LED(12, 0), DELM, /* T12: volume down */
+	LED(13, 0), DELM, /* T13: volume up */
+	DELM, /* T14: (null) */
+	DELM, /* T15: (null) */
+	DELM, /* 126: (null) */
+	DELM, /* 127: (null) */
 };
 #undef LED
 #undef DELM
@@ -322,7 +319,7 @@ int board_get_entropy(void *buffer, int len)
 	uint8_t *data = buffer;
 	uint32_t start;
 	/* We expect one SOF per ms, so wait at most 2ms. */
-	const uint32_t timeout = 2*MSEC;
+	const uint32_t timeout = 2 * MSEC;
 
 	for (i = 0; i < len; i++) {
 		STM32_CRS_ICR |= STM32_CRS_ICR_SYNCOKC;
@@ -353,8 +350,9 @@ __override const char *board_read_serial(void)
 		int i;
 
 		for (i = 0; i < idlen && pos < sizeof(str); i++, pos += 2) {
-			snprintf(&str[pos], sizeof(str)-pos,
-				"%02x", id[i]);
+			if (snprintf(&str[pos], sizeof(str) - pos, "%02x",
+				     id[i]) < 0)
+				return NULL;
 		}
 	}
 
diff --git a/board/prism/board.h b/board/prism/board.h
index 1734624752..9cca111ba2 100644
--- a/board/prism/board.h
+++ b/board/prism/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,13 +8,15 @@
 #ifndef __CROS_EC_BOARD_H
 #define __CROS_EC_BOARD_H
 
-/* TODO: May remove CONFIG_SYSTEM_UNLOCKED prior to building MP FW. */
-#define CONFIG_SYSTEM_UNLOCKED
+/* Prism doesn't use WP GPIO, set WP enabled */
+#ifdef SECTION_IS_RO
+#define CONFIG_WP_ALWAYS
+#endif
 
 /* TODO: May define FLASH_PSTATE_LOCKED prior to building MP FW. */
 #undef CONFIG_FLASH_PSTATE_LOCKED
 
-/* USB ID. TODO: May need to find one for Prism. */
+/* USB ID for Prism */
 #define CONFIG_USB_PID 0x5022
 
 /* 48 MHz SYSCLK clock frequency */
@@ -24,15 +26,15 @@
 #ifdef SECTION_IS_RW
 #define CONFIG_KEYBOARD_BACKLIGHT
 #define CONFIG_RGB_KEYBOARD
-#define GPIO_RGBKBD_SDB_L	GPIO_SDB_L
-#define GPIO_RGBKBD_POWER	GPIO_L_POWER
+#define GPIO_RGBKBD_SDB_L GPIO_SDB_L
+#define GPIO_RGBKBD_POWER GPIO_L_POWER
 #define CONFIG_LED_DRIVER_IS31FL3743B
-#define SPI_RGB0_DEVICE_ID	0
-#define SPI_RGB1_DEVICE_ID	1
-#define RGB_GRID0_COL		11
-#define RGB_GRID0_ROW		6
-#define RGB_GRID1_COL		11
-#define RGB_GRID1_ROW		6
+#define SPI_RGB0_DEVICE_ID 0
+#define SPI_RGB1_DEVICE_ID 1
+#define RGB_GRID0_COL 11
+#define RGB_GRID0_ROW 6
+#define RGB_GRID1_COL 11
+#define RGB_GRID1_ROW 6
 
 /* Enable control of SPI over USB */
 #define CONFIG_SPI_CONTROLLER
@@ -74,27 +76,27 @@
 /* Do not use a dedicated PSTATE bank */
 #undef CONFIG_FLASH_PSTATE_BANK
 
-#define CONFIG_SHAREDLIB_SIZE	0
+#define CONFIG_SHAREDLIB_SIZE 0
 
-#define CONFIG_RO_MEM_OFF	0
-#define CONFIG_RO_STORAGE_OFF	0
-#define CONFIG_RO_SIZE		(44*1024)
+#define CONFIG_RO_MEM_OFF 0
+#define CONFIG_RO_STORAGE_OFF 0
+#define CONFIG_RO_SIZE (44 * 1024)
 
 /* EC rollback protection block */
 #define CONFIG_ROLLBACK_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
 #define CONFIG_ROLLBACK_SIZE CONFIG_FLASH_BANK_SIZE
 
-#define CONFIG_RW_MEM_OFF	(CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE)
-#define CONFIG_RW_STORAGE_OFF	0
-#define CONFIG_RW_SIZE		(CONFIG_FLASH_SIZE_BYTES - CONFIG_RW_MEM_OFF)
+#define CONFIG_RW_MEM_OFF (CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE)
+#define CONFIG_RW_STORAGE_OFF 0
+#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE_BYTES - CONFIG_RW_MEM_OFF)
 
-#define CONFIG_EC_PROTECTED_STORAGE_OFF		CONFIG_RO_MEM_OFF
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE	CONFIG_RO_SIZE
-#define CONFIG_EC_WRITABLE_STORAGE_OFF		CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE		CONFIG_RW_SIZE
+#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF
+#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE
+#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE
 
-#define CONFIG_WP_STORAGE_OFF		CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE		CONFIG_EC_PROTECTED_STORAGE_SIZE
+#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
+#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
 
 /* The UART console is on USART1 (PA9/PA10) */
 #undef CONFIG_UART_CONSOLE
@@ -120,24 +122,24 @@
 
 #define CONFIG_USB_SERIALNO
 /* Replaced at runtime (board_read_serial) by chip unique-id-based number. */
-#define DEFAULT_SERIALNO ""
+#define DEFAULT_SERIALNO "Uninitialized"
 
 /* USB interface indexes (use define rather than enum to expand them) */
-#undef  CONFIG_HOSTCMD_EVENTS
-#define USB_IFACE_UPDATE	0
+#undef CONFIG_HOSTCMD_EVENTS
+#define USB_IFACE_UPDATE 0
 #ifdef SECTION_IS_RW
 #define CONFIG_HOST_INTERFACE_USB
-#define USB_IFACE_HOSTCMD	1
-#define USB_IFACE_COUNT		2
+#define USB_IFACE_HOSTCMD 1
+#define USB_IFACE_COUNT 2
 #else
-#define USB_IFACE_COUNT		1
+#define USB_IFACE_COUNT 1
 #endif
 
 /* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL		0
-#define USB_EP_UPDATE		1
-#define USB_EP_HOSTCMD		2
-#define USB_EP_COUNT		3
+#define USB_EP_CONTROL 0
+#define USB_EP_UPDATE 1
+#define USB_EP_HOSTCMD 2
+#define USB_EP_COUNT 3
 
 /* Optional features */
 #define CONFIG_BOARD_PRE_INIT
@@ -192,10 +194,10 @@
 #endif
 
 /* Maximum current to draw. */
-#define MAX_CURRENT_MA			2000
+#define MAX_CURRENT_MA 2000
 /* Maximum current/voltage to provide over OTG. */
-#define MAX_OTG_CURRENT_MA		2000
-#define MAX_OTG_VOLTAGE_MV		20000
+#define MAX_OTG_CURRENT_MA 2000
+#define MAX_OTG_VOLTAGE_MV 20000
 
 #ifndef __ASSEMBLER__
 
diff --git a/board/prism/build.mk b/board/prism/build.mk
index 824b05cab8..aed193a2e9 100644
--- a/board/prism/build.mk
+++ b/board/prism/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/prism/ec.tasklist b/board/prism/ec.tasklist
index 10fdb1b75f..aaf9b15a5e 100644
--- a/board/prism/ec.tasklist
+++ b/board/prism/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/prism/gpio.inc b/board/prism/gpio.inc
index 469ac690c6..2b8f2ee9b8 100644
--- a/board/prism/gpio.inc
+++ b/board/prism/gpio.inc
@@ -1,12 +1,10 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-GPIO(WP_L,			PIN(A, 13), GPIO_INPUT | GPIO_PULL_UP)
-
 #ifdef SECTION_IS_RW
 
 GPIO(SDB_L,		PIN(A, 0), GPIO_OUT_LOW)
@@ -24,3 +22,4 @@ ALTERNATE(PIN_MASK(A, 0x00e0), 0, MODULE_SPI_CONTROLLER, GPIO_PULL_UP)
 ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART, GPIO_PULL_UP)
 
 UNIMPLEMENTED(ENTERING_RW)
+UNIMPLEMENTED(WP_L)
diff --git a/board/puff/board.c b/board/puff/board.c
index a893de33c3..d863b5fc0b 100644
--- a/board/puff/board.c
+++ b/board/puff/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -45,8 +45,8 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void power_monitor(void);
 DECLARE_DEFERRED(power_monitor);
@@ -88,8 +88,8 @@ uint16_t tcpc_get_alert_status(void)
 }
 
 /* Called when the charge manager has switched to a new port. */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	/* Blink alert if insufficient power per system_can_boot_ap(). */
 	int insufficient_power =
@@ -105,14 +105,14 @@ static int32_t base_5v_power;
  * Power usage for each port as measured or estimated.
  * Units are milliwatts (5v x ma current)
  */
-#define PWR_BASE_LOAD	(5*1335)
-#define PWR_FRONT_HIGH	(5*1603)
-#define PWR_FRONT_LOW	(5*963)
-#define PWR_REAR	(5*1075)
-#define PWR_HDMI	(5*562)
-#define PWR_C_HIGH	(5*3740)
-#define PWR_C_LOW	(5*2090)
-#define PWR_MAX		(5*10000)
+#define PWR_BASE_LOAD (5 * 1335)
+#define PWR_FRONT_HIGH (5 * 1603)
+#define PWR_FRONT_LOW (5 * 963)
+#define PWR_REAR (5 * 1075)
+#define PWR_HDMI (5 * 562)
+#define PWR_C_HIGH (5 * 3740)
+#define PWR_C_LOW (5 * 2090)
+#define PWR_MAX (5 * 10000)
 
 /*
  * Update the 5V power usage, assuming no throttling,
@@ -185,16 +185,14 @@ static const struct {
 	int current;
 } bj_power[] = {
 	{ /* 0 - 65W (also default) */
-	.voltage = 19000,
-	.current = 3420
-	},
+	  .voltage = 19000,
+	  .current = 3420 },
 	{ /* 1 - 90W */
-	.voltage = 19000,
-	.current = 4740
-	},
+	  .voltage = 19000,
+	  .current = 4740 },
 };
 
-#define ADP_DEBOUNCE_MS		1000  /* Debounce time for BJ plug/unplug */
+#define ADP_DEBOUNCE_MS 1000 /* Debounce time for BJ plug/unplug */
 /* Debounced connection state of the barrel jack */
 static int8_t adp_connected = -1;
 static void adp_connect_deferred(void)
@@ -239,29 +237,26 @@ static void adp_state_init(void)
 }
 DECLARE_HOOK(HOOK_INIT, adp_state_init, HOOK_PRIO_INIT_CHARGE_MANAGER + 1);
 
-
 #include "gpio_list.h" /* Must come after other header files. */
 
 /******************************************************************************/
 /* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
+const struct spi_device_t spi_devices[] = {};
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
 /******************************************************************************/
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN]        = { .channel = 5,
-				.flags = PWM_CONFIG_OPEN_DRAIN,
-				.freq = 25000},
-	[PWM_CH_LED_RED]    = { .channel = 0,
-				.flags = PWM_CONFIG_ACTIVE_LOW |
-					 PWM_CONFIG_DSLEEP,
-				.freq = 2000 },
-	[PWM_CH_LED_GREEN]  = { .channel = 2,
-				.flags = PWM_CONFIG_ACTIVE_LOW |
-					 PWM_CONFIG_DSLEEP,
-				.freq = 2000 },
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
+	[PWM_CH_LED_RED] = { .channel = 0,
+			     .flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP,
+			     .freq = 2000 },
+	[PWM_CH_LED_GREEN] = { .channel = 2,
+			       .flags = PWM_CONFIG_ACTIVE_LOW |
+					PWM_CONFIG_DSLEEP,
+			       .freq = 2000 },
 };
 
 /******************************************************************************/
@@ -277,52 +272,44 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 		.flags = TCPC_FLAGS_RESET_ACTIVE_HIGH,
 	},
 };
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_TCPC_0] = {
-		.usb_port = USB_PD_PORT_TCPC_0,
-		.driver = &anx7447_usb_mux_driver,
-		.hpd_update = &anx7447_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_0,
+			.driver = &anx7447_usb_mux_driver,
+			.hpd_update = &anx7447_tcpc_update_hpd_status,
+		},
 	},
 };
 
 /******************************************************************************/
 /* I2C port map configuration */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "ina",
-		.port = I2C_PORT_INA,
-		.kbps = 400,
-		.scl  = GPIO_I2C0_SCL,
-		.sda  = GPIO_I2C0_SDA
-	},
-	{
-		.name = "ppc0",
-		.port = I2C_PORT_PPC0,
-		.kbps = 400,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	},
-	{
-		.name = "tcpc0",
-		.port = I2C_PORT_TCPC0,
-		.kbps = 400,
-		.scl  = GPIO_I2C3_SCL,
-		.sda  = GPIO_I2C3_SDA
-	},
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 400,
-		.scl  = GPIO_I2C5_SCL,
-		.sda  = GPIO_I2C5_SDA
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl  = GPIO_I2C7_SCL,
-		.sda  = GPIO_I2C7_SDA
-	},
+	{ .name = "ina",
+	  .port = I2C_PORT_INA,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_SCL,
+	  .sda = GPIO_I2C0_SDA },
+	{ .name = "ppc0",
+	  .port = I2C_PORT_PPC0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 400,
+	  .scl = GPIO_I2C5_SCL,
+	  .sda = GPIO_I2C5_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_I2C7_SCL,
+	  .sda = GPIO_I2C7_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -378,15 +365,14 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
 /******************************************************************************/
 /* Wake up pins */
-const enum gpio_signal hibernate_wake_pins[] = {
-};
+const enum gpio_signal hibernate_wake_pins[] = {};
 const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 
 /******************************************************************************/
 /* Physical fans. These are logically separate from pwm_channels. */
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = -1,
 };
@@ -405,7 +391,7 @@ BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
 /******************************************************************************/
 /* MFT channels. These are logically separate from pwm_channels. */
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN },
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
@@ -414,8 +400,8 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_A \
-	{ \
+#define THERMAL_A                \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = 0, \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(68), \
@@ -434,8 +420,8 @@ __maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_B \
-	{ \
+#define THERMAL_B                \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = 0, \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(78), \
@@ -537,16 +523,13 @@ static void board_chipset_startup(void)
 	if (ppc_is_sourcing_vbus(0))
 		ppc_vbus_source_enable(0, 1);
 }
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup,
-	     HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
 /******************************************************************************/
 /* USB-C PPC Configuration */
 struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_TCPC_0] = {
-		.i2c_port = I2C_PORT_PPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
+	[USB_PD_PORT_TCPC_0] = { .i2c_port = I2C_PORT_PPC0,
+				 .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+				 .drv = &sn5s330_drv },
 };
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
@@ -579,14 +562,12 @@ static void board_tcpc_init(void)
 		/*
 		 * By default configured as output low.
 		 */
-		gpio_set_flags(GPIO_USB_A4_OC_ODL,
-			       GPIO_INPUT | GPIO_INT_BOTH);
+		gpio_set_flags(GPIO_USB_A4_OC_ODL, GPIO_INPUT | GPIO_INT_BOTH);
 		gpio_enable_interrupt(GPIO_USB_A4_OC_ODL);
 	} else {
 		/* Ensure no interrupts from pin */
 		gpio_disable_interrupt(GPIO_USB_A4_OC_ODL);
 	}
-
 }
 /* Make sure this is called after fw_config is initialised */
 DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 2);
@@ -705,8 +686,8 @@ void board_enable_s0_rails(int enable)
 
 unsigned int ec_config_get_bj_power(void)
 {
-	unsigned int bj =
-		(fw_config & EC_CFG_BJ_POWER_MASK) >> EC_CFG_BJ_POWER_L;
+	unsigned int bj = (fw_config & EC_CFG_BJ_POWER_MASK) >>
+			  EC_CFG_BJ_POWER_L;
 	/* Out of range value defaults to 0 */
 	if (bj >= ARRAY_SIZE(bj_power))
 		bj = 0;
@@ -781,23 +762,23 @@ DECLARE_HOOK(HOOK_INIT, setup_thermal, HOOK_PRIO_DEFAULT - 1);
  *
  *  All measurements are in milliwatts.
  */
-#define THROT_TYPE_A		BIT(0)
-#define THROT_TYPE_C		BIT(1)
-#define THROT_PROCHOT		BIT(2)
+#define THROT_TYPE_A BIT(0)
+#define THROT_TYPE_C BIT(1)
+#define THROT_PROCHOT BIT(2)
 
 /*
  * Power gain if front USB A ports are limited.
  */
-#define POWER_GAIN_TYPE_A	3200
+#define POWER_GAIN_TYPE_A 3200
 /*
  * Power gain if Type C port is limited.
  */
-#define POWER_GAIN_TYPE_C	8800
+#define POWER_GAIN_TYPE_C 8800
 /*
  * Power is averaged over 10 ms, with a reading every 2 ms.
  */
-#define POWER_DELAY_MS		2
-#define POWER_READINGS		(10/POWER_DELAY_MS)
+#define POWER_DELAY_MS 2
+#define POWER_READINGS (10 / POWER_DELAY_MS)
 
 static void power_monitor(void)
 {
@@ -812,8 +793,7 @@ static void power_monitor(void)
 	 * If CPU is off or suspended, no need to throttle
 	 * or restrict power.
 	 */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF |
-			     CHIPSET_STATE_SUSPEND)) {
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF | CHIPSET_STATE_SUSPEND)) {
 		/*
 		 * Slow down monitoring, assume no throttling required.
 		 */
@@ -841,7 +821,7 @@ static void power_monitor(void)
 			 */
 			power = (adc_read_channel(ADC_VBUS) *
 				 adc_read_channel(ADC_PPVAR_IMON)) /
-				 1000;
+				1000;
 			/* Init power table */
 			if (history[0] == 0) {
 				for (i = 0; i < POWER_READINGS; i++)
@@ -868,8 +848,7 @@ static void power_monitor(void)
 			 * For barrel-jack supplies, the rating can be
 			 * exceeded briefly, so use the average.
 			 */
-			if (charge_manager_get_supplier() ==
-			    CHARGE_SUPPLIER_PD)
+			if (charge_manager_get_supplier() == CHARGE_SUPPLIER_PD)
 				power = max;
 			else
 				power = total / POWER_READINGS;
@@ -961,8 +940,9 @@ static void power_monitor(void)
 		gpio_set_level(GPIO_EC_PROCHOT_ODL, prochot);
 	}
 	if (diff & THROT_TYPE_C) {
-		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C)
-			? TYPEC_RP_1A5 : TYPEC_RP_3A0;
+		enum tcpc_rp_value rp = (new_state & THROT_TYPE_C) ?
+						TYPEC_RP_1A5 :
+						TYPEC_RP_3A0;
 
 		ppc_set_vbus_source_current_limit(0, rp);
 		tcpm_select_rp_value(0, rp);
diff --git a/board/puff/board.h b/board/puff/board.h
index 185c3d0076..59c177c604 100644
--- a/board/puff/board.h
+++ b/board/puff/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,8 +12,8 @@
 #define CONFIG_UART_TX_BUF_SIZE 4096
 
 /* NPCX7 config */
-#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
-#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
+#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */
+#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */
 
 /* Internal SPI flash on NPCX796FC is 512 kB */
 #define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
@@ -40,7 +40,7 @@
 #undef CONFIG_HIBERNATE
 #define CONFIG_HOST_INTERFACE_ESPI
 #define CONFIG_LED_COMMON
-#undef  CONFIG_LID_SWITCH
+#undef CONFIG_LID_SWITCH
 #define CONFIG_LTO
 #define CONFIG_PWM
 #define CONFIG_VBOOT_EFS2
@@ -85,7 +85,7 @@
 #define CONFIG_CPU_PROCHOT_ACTIVE_LOW
 
 /* Dedicated barreljack charger port */
-#undef  CONFIG_DEDICATED_CHARGE_PORT_COUNT
+#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT
 #define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1
 #define DEDICATED_CHARGE_PORT 1
 
@@ -104,15 +104,15 @@
 #define CONFIG_INA3221
 
 /* b/143501304 */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	4000	/* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	2000	/* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 4000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 2000 /* us */
 #undef CONFIG_USBC_VCONN_SWAP_DELAY_US
-#define CONFIG_USBC_VCONN_SWAP_DELAY_US		8000	/* us */
+#define CONFIG_USBC_VCONN_SWAP_DELAY_US 8000 /* us */
 
-#define PD_OPERATING_POWER_MW	CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
-#define PD_MAX_POWER_MW		100000
-#define PD_MAX_CURRENT_MA	5000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
+#define PD_MAX_POWER_MW 100000
+#define PD_MAX_CURRENT_MA 5000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Fan and temp. */
 #define CONFIG_FANS 1
@@ -136,7 +136,7 @@
 #define CONFIG_USB_PD_DECODE_SOP
 #undef CONFIG_USB_CHARGER
 #define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PID		0x5040
+#define CONFIG_USB_PID 0x5040
 #define CONFIG_USB_PD_ALT_MODE
 #define CONFIG_USB_PD_ALT_MODE_DFP
 #define CONFIG_USB_PD_DISCHARGE_PPC
@@ -156,7 +156,7 @@
 #define CONFIG_USBC_VCONN
 #define CONFIG_USBC_VCONN_SWAP
 
-#define USB_PD_PORT_TCPC_0	0
+#define USB_PD_PORT_TCPC_0 0
 #define BOARD_TCPC_C0_RESET_HOLD_DELAY ANX74XX_RESET_HOLD_MS
 #define BOARD_TCPC_C0_RESET_POST_DELAY ANX74XX_RESET_HOLD_MS
 
@@ -168,12 +168,12 @@
 /* I2C Bus Configuration */
 #define CONFIG_I2C
 #define CONFIG_I2C_CONTROLLER
-#define I2C_PORT_INA		NPCX_I2C_PORT0_0
-#define I2C_PORT_PPC0		NPCX_I2C_PORT1_0
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT3_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_PORT_INA NPCX_I2C_PORT0_0
+#define I2C_PORT_PPC0 NPCX_I2C_PORT1_0
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT3_0
+#define I2C_PORT_POWER NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 
 #define PP5000_PGOOD_POWER_SIGNAL_MASK POWER_SIGNAL_MASK(PP5000_A_PGOOD)
 
@@ -191,11 +191,11 @@ enum charge_port {
 };
 
 enum adc_channel {
-	ADC_SNS_PP3300,     /* ADC2 */
-	ADC_SNS_PP1050,     /* ADC7 */
-	ADC_VBUS,           /* ADC4 */
-	ADC_PPVAR_IMON,     /* ADC9 */
-	ADC_TEMP_SENSOR_1,  /* ADC0 */
+	ADC_SNS_PP3300, /* ADC2 */
+	ADC_SNS_PP1050, /* ADC7 */
+	ADC_VBUS, /* ADC4 */
+	ADC_PPVAR_IMON, /* ADC9 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
 	/* Number of ADC channels */
 	ADC_CH_COUNT
 };
@@ -220,11 +220,7 @@ enum mft_channel {
 	MFT_CH_COUNT,
 };
 
-enum temp_sensor_id {
-	TEMP_SENSOR_CORE,
-	TEMP_SENSOR_COUNT
-};
-
+enum temp_sensor_id { TEMP_SENSOR_CORE, TEMP_SENSOR_COUNT };
 
 /* Board specific handlers */
 void board_reset_pd_mcu(void);
@@ -238,20 +234,20 @@ void show_critical_error(void);
 /*
  * Barrel-jack power (4 bits).
  */
-#define EC_CFG_BJ_POWER_L		0
-#define EC_CFG_BJ_POWER_H		3
+#define EC_CFG_BJ_POWER_L 0
+#define EC_CFG_BJ_POWER_H 3
 #define EC_CFG_BJ_POWER_MASK GENMASK(EC_CFG_BJ_POWER_H, EC_CFG_BJ_POWER_L)
 /*
  * USB Connector 4 not present (1 bit).
  */
-#define EC_CFG_NO_USB4_L		4
-#define EC_CFG_NO_USB4_H		4
+#define EC_CFG_NO_USB4_L 4
+#define EC_CFG_NO_USB4_H 4
 #define EC_CFG_NO_USB4_MASK GENMASK(EC_CFG_NO_USB4_H, EC_CFG_NO_USB4_L)
 /*
  * Thermal solution config (3 bits).
  */
-#define EC_CFG_THERMAL_L		5
-#define EC_CFG_THERMAL_H		7
+#define EC_CFG_THERMAL_L 5
+#define EC_CFG_THERMAL_H 7
 #define EC_CFG_THERMAL_MASK GENMASK(EC_CFG_THERMAL_H, EC_CFG_THERMAL_L)
 
 unsigned int ec_config_get_bj_power(void);
@@ -261,30 +257,30 @@ unsigned int ec_config_get_thermal_solution(void);
 #endif /* !__ASSEMBLER__ */
 
 /* Pin renaming */
-#define GPIO_WP_L               GPIO_EC_WP_ODL
-#define GPIO_PP5000_A_PG_OD     GPIO_PG_PP5000_A_OD
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
-#define GPIO_RECOVERY_L         GPIO_EC_RECOVERY_BTN_ODL
-#define GPIO_RECOVERY_L_2       GPIO_H1_EC_RECOVERY_BTN_ODL
-#define GPIO_POWER_BUTTON_L	GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_PCH_WAKE_L		GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L	GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_ENTERING_RW	GPIO_EC_ENTERING_RW
-#define GPIO_SYS_RESET_L	GPIO_SYS_RST_ODL
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_PCH_RTCRST		GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_TEMP_SENSOR_POWER	GPIO_EN_ROA_RAILS
-#define GPIO_AC_PRESENT		GPIO_BJ_ADP_PRESENT_L
+#define GPIO_WP_L GPIO_EC_WP_ODL
+#define GPIO_PP5000_A_PG_OD GPIO_PG_PP5000_A_OD
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
+#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_ODL
+#define GPIO_RECOVERY_L_2 GPIO_H1_EC_RECOVERY_BTN_ODL
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_EN_ROA_RAILS
+#define GPIO_AC_PRESENT GPIO_BJ_ADP_PRESENT_L
 
 /*
  * There is no RSMRST input, so alias it to the output. This short-circuits
  * common_intel_x86_handle_rsmrst.
  */
-#define GPIO_PG_EC_RSMRST_ODL	GPIO_PCH_RSMRST_L
+#define GPIO_PG_EC_RSMRST_ODL GPIO_PCH_RSMRST_L
 
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/puff/build.mk b/board/puff/build.mk
index e9968d5710..3edfc84c2f 100644
--- a/board/puff/build.mk
+++ b/board/puff/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/puff/ec.tasklist b/board/puff/ec.tasklist
index ae10417dff..d579f65fd9 100644
--- a/board/puff/ec.tasklist
+++ b/board/puff/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/puff/gpio.inc b/board/puff/gpio.inc
index b51f595e81..5f7650a682 100644
--- a/board/puff/gpio.inc
+++ b/board/puff/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,12 +25,12 @@ GPIO_INT(PG_VPRIM_CORE_A_OD,   PIN(2, 3), GPIO_INT_BOTH, power_signal_interrupt)
 GPIO_INT(PG_PP1050_A_OD,       PIN(2, 2), GPIO_INT_BOTH, power_signal_interrupt)
 /* EC output, but also interrupt so this can be polled as a power signal */
 GPIO_INT(EC_PCH_RSMRST_L,      PIN(A, 6), GPIO_OUTPUT | GPIO_INT_F_RISING | GPIO_INT_F_FALLING, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(PG_PP2500_DRAM_U_OD,  PIN(2, 0), GPIO_INT_BOTH, power_signal_interrupt)
 GPIO_INT(PG_PP1200_U_OD,       PIN(2, 1), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, slp_s3_interrupt)
 #endif
 GPIO_INT(PG_PP950_VCCIO_OD,    PIN(1, 7), GPIO_INT_BOTH, power_signal_interrupt)
diff --git a/board/puff/led.c b/board/puff/led.c
index ba87f05460..9cca110467 100644
--- a/board/puff/led.c
+++ b/board/puff/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,16 +19,16 @@
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
 
 /*
  * Due to the CSME-Lite processing, upon startup the CPU transitions through
  * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so
  * delay turning off the LED during suspend/shutdown.
  */
-#define LED_CPU_DELAY_MS	(2000 * MSEC)
+#define LED_CPU_DELAY_MS (2000 * MSEC)
 
-const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 enum led_color {
@@ -89,9 +89,9 @@ static int set_color(enum ec_led_id id, enum led_color color, int duty)
 	}
 }
 
-#define LED_PULSE_US		(2 * SECOND)
+#define LED_PULSE_US (2 * SECOND)
 /* 40 msec for nice and smooth transition. */
-#define LED_PULSE_TICK_US	(40 * MSEC)
+#define LED_PULSE_TICK_US (40 * MSEC)
 
 /* When pulsing is enabled, brightness is incremented by <duty_inc> every
  * <interval> usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented
@@ -214,7 +214,7 @@ void show_critical_error(void)
 		set_color(EC_LED_ID_POWER_LED, LED_RED, 100);
 }
 
-static int command_led(int argc, char **argv)
+static int command_led(int argc, const char **argv)
 {
 	enum ec_led_id id = EC_LED_ID_POWER_LED;
 
diff --git a/board/puff/usb_pd_policy.c b/board/puff/usb_pd_policy.c
index 9b0a372400..e3fc86c8ca 100644
--- a/board/puff/usb_pd_policy.c
+++ b/board/puff/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,9 +19,8 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
diff --git a/board/quackingstick/base_detect.c b/board/quackingstick/base_detect.c
index d008226125..620381f09b 100644
--- a/board/quackingstick/base_detect.c
+++ b/board/quackingstick/base_detect.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,8 +19,8 @@
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
 /* Base detection and debouncing */
 #define BASE_DETECT_EN_DEBOUNCE_US (350 * MSEC)
@@ -93,8 +93,8 @@ static uint32_t pulse_width;
 
 static void print_base_detect_value(int v, int tmp_pulse_width)
 {
-	CPRINTS("%s = %d (pulse %d)", adc_channels[ADC_BASE_DET].name,
-			v, tmp_pulse_width);
+	CPRINTS("%s = %d (pulse %d)", adc_channels[ADC_BASE_DET].name, v,
+		tmp_pulse_width);
 }
 
 static void base_detect_deferred(void)
@@ -211,7 +211,7 @@ static void base_init(void)
 	if (system_jumped_late() && chipset_in_state(CHIPSET_STATE_ON))
 		base_enable();
 }
-DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT+1);
+DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT + 1);
 
 void base_force_state(enum ec_set_base_state_cmd state)
 {
diff --git a/board/quackingstick/battery.c b/board/quackingstick/battery.c
index 43cd8b9d8b..5376e74dc5 100644
--- a/board/quackingstick/battery.c
+++ b/board/quackingstick/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/quackingstick/board.c b/board/quackingstick/board.c
index 9756eb0651..6cdf814c74 100644
--- a/board/quackingstick/board.c
+++ b/board/quackingstick/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -40,10 +40,10 @@
 #include "thermal.h"
 #include "usbc_ppc.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define KS_DEBOUNCE_US    (30 * MSEC)  /* Debounce time for kickstand switch */
+#define KS_DEBOUNCE_US (30 * MSEC) /* Debounce time for kickstand switch */
 
 /* Forward declaration */
 static void tcpc_alert_event(enum gpio_signal signal);
@@ -102,34 +102,26 @@ static void board_connect_c0_sbu(enum gpio_signal s)
 
 /* I2C port map */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl  = GPIO_EC_I2C_POWER_SCL,
-		.sda  = GPIO_EC_I2C_POWER_SDA
-	},
-	{
-		.name = "tcpc0",
-		.port = I2C_PORT_TCPC0,
-		.kbps = 1000,
-		.scl  = GPIO_EC_I2C_USB_C0_PD_SCL,
-		.sda  = GPIO_EC_I2C_USB_C0_PD_SDA
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_EEPROM_SCL,
-		.sda  = GPIO_EC_I2C_EEPROM_SDA
-	},
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_SENSOR_SCL,
-		.sda  = GPIO_EC_I2C_SENSOR_SDA
-	},
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_POWER_SCL,
+	  .sda = GPIO_EC_I2C_POWER_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C0_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C0_PD_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_EEPROM_SCL,
+	  .sda = GPIO_EC_I2C_EEPROM_SDA },
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_SENSOR_SCL,
+	  .sda = GPIO_EC_I2C_SENSOR_SDA },
 };
 
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
@@ -204,11 +196,9 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
 /* Power Path Controller */
 struct ppc_config_t ppc_chips[] = {
-	{
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
+	{ .i2c_port = I2C_PORT_TCPC0,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
 };
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
@@ -231,11 +221,14 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
  * to AP. But the TCPC chip is also needed to know the HPD status; otherwise,
  * the mux misbehaves.
  */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	},
 };
 
@@ -262,11 +255,9 @@ enum lid_accelgyro_type {
 static enum lid_accelgyro_type lid_accelgyro_config;
 
 /* Matrix to rotate accelerometer into standard reference frame */
-const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+				      { FLOAT_TO_FP(-1), 0, 0 },
+				      { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	/*
@@ -365,8 +356,7 @@ static void board_detect_motionsensor(void)
 		return;
 
 	/* Check base accelgyro chip */
-	icm_read8(&motion_sensors_icm[LID_ACCEL], ICM42607_REG_WHO_AM_I,
-		  &val);
+	icm_read8(&motion_sensors_icm[LID_ACCEL], ICM42607_REG_WHO_AM_I, &val);
 	if (val == ICM42607_CHIP_ICM42607P) {
 		motion_sensors[LID_ACCEL] = motion_sensors_icm[LID_ACCEL];
 		motion_sensors[LID_GYRO] = motion_sensors_icm[LID_GYRO];
@@ -443,9 +433,31 @@ void board_tcpc_init(void)
 	 */
 	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
 		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
+
+enum battery_present battery_is_present(void)
+{
+	static int first_check_done;
+
+	/*
+	 * b/231911921: It's found that the D-FET status is incorrect
+	 * when the battery resume from cut off. The battery needs
+	 * about 2s to ready to discharge so delay 2s before charge
+	 * manager init.
+	 */
+	if (!first_check_done) {
+		if (battery_get_disconnect_state() ==
+		    BATTERY_NOT_DISCONNECTED) {
+			CPRINTS("Delay 2s on the first power on.");
+			sleep(2);
+		}
+		first_check_done = 1;
+	}
+
+	return gpio_get_level(GPIO_BATT_PRES_ODL) ? BP_NO : BP_YES;
 }
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
 
 void board_hibernate(void)
 {
@@ -455,8 +467,7 @@ void board_hibernate(void)
 	 * Sensors are unpowered in hibernate. Apply PD to the
 	 * interrupt lines such that they don't float.
 	 */
-	gpio_set_flags(GPIO_ACCEL_GYRO_INT_L,
-		       GPIO_INPUT | GPIO_PULL_DOWN);
+	gpio_set_flags(GPIO_ACCEL_GYRO_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
 
 	/*
 	 * Board rev 1+ has the hardware fix. Don't need the following
@@ -550,8 +561,7 @@ void board_overcurrent_event(int port, int is_overcurrented)
 
 int board_set_active_charge_port(int port)
 {
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	int i;
 
 	if (!is_real_port && port != CHARGE_PORT_NONE)
@@ -579,7 +589,6 @@ int board_set_active_charge_port(int port)
 		return EC_ERROR_INVAL;
 	}
 
-
 	CPRINTS("New charge port: p%d", port);
 
 	/*
@@ -603,24 +612,22 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	/*
 	 * Ignore lower charge ceiling on PD transition if our battery is
 	 * critical, as we may brownout.
 	 */
-	if (supplier == CHARGE_SUPPLIER_PD &&
-	    charge_ma < 1500 &&
+	if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 &&
 	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
 		CPRINTS("Using max ilim %d", max_ma);
 		charge_ma = max_ma;
 	}
 
 	charge_ma = charge_ma * 95 / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 /**
@@ -629,7 +636,7 @@ void board_set_charge_limit(int port, int supplier, int charge_ma,
 static void pen_input_deferred(void)
 {
 	bool pen_charge_enable = !gpio_get_level(GPIO_EC_PEN_PDCT_L) &&
-			!chipset_in_state(CHIPSET_STATE_ANY_OFF);
+				 !chipset_in_state(CHIPSET_STATE_ANY_OFF);
 
 	gpio_set_level(GPIO_PEN_PWR_EN, pen_charge_enable);
 
diff --git a/board/quackingstick/board.h b/board/quackingstick/board.h
index f537d6b472..9b50237b4d 100644
--- a/board/quackingstick/board.h
+++ b/board/quackingstick/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,7 +13,7 @@
 #define CONFIG_BUTTON_TRIGGERED_RECOVERY
 
 /* Internal SPI flash on NPCX7 */
-#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)  /* 512KB internal spi flash */
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */
 
 /* Save some flash space */
 #define CONFIG_LTO
@@ -26,8 +26,9 @@
 #undef CONFIG_CMD_TASK_RESET
 
 /* Battery */
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY  "LION"
-#define CONFIG_BATTERY_REVIVE_DISCONNECT
+#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
+#undef CONFIG_BATTERY_PRESENT_GPIO
+#define CONFIG_BATTERY_PRESENT_CUSTOM
 #define CONFIG_BATTERY_FUEL_GAUGE
 #define CONFIG_BATTERY_VENDOR_PARAM
 
@@ -82,10 +83,7 @@ enum adc_channel {
 	ADC_CH_COUNT
 };
 
-enum temp_sensor_id {
-	TEMP_SENSOR_SYS2,
-	TEMP_SENSOR_COUNT
-};
+enum temp_sensor_id { TEMP_SENSOR_SYS2, TEMP_SENSOR_COUNT };
 
 /* Motion sensors */
 enum sensor_id {
@@ -94,10 +92,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_DISPLIGHT = 0,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_DISPLIGHT = 0, PWM_CH_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
diff --git a/board/quackingstick/build.mk b/board/quackingstick/build.mk
index 452abeb591..363ef59a16 100644
--- a/board/quackingstick/build.mk
+++ b/board/quackingstick/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/quackingstick/ec.tasklist b/board/quackingstick/ec.tasklist
index 0b6b66ab71..6cc550374d 100644
--- a/board/quackingstick/ec.tasklist
+++ b/board/quackingstick/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/quackingstick/gpio.inc b/board/quackingstick/gpio.inc
index c126b59977..ee3cedf704 100644
--- a/board/quackingstick/gpio.inc
+++ b/board/quackingstick/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/quackingstick/led.c b/board/quackingstick/led.c
index e282459476..a18124f2be 100644
--- a/board/quackingstick/led.c
+++ b/board/quackingstick/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -35,15 +35,15 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_BLUE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static void led_set_color(enum led_color color)
 {
 	gpio_set_level(GPIO_LED_ORANGE,
-		(color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
+		       (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
 	gpio_set_level(GPIO_LED_BLUE,
-		(color == LED_BLUE) ? BAT_LED_ON : BAT_LED_OFF);
+		       (color == LED_BLUE) ? BAT_LED_ON : BAT_LED_OFF);
 }
 
 void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
@@ -69,7 +69,6 @@ static void board_led_set_battery(void)
 	static int battery_ticks;
 	int color = LED_OFF;
 	int period = 0;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
@@ -80,7 +79,7 @@ static void board_led_set_battery(void)
 		break;
 	case PWR_STATE_DISCHARGE:
 		if (chipset_in_or_transitioning_to_state(
-		    CHIPSET_STATE_ANY_SUSPEND)) {
+			    CHIPSET_STATE_ANY_SUSPEND)) {
 			/* Discharging in S3: Amber 1 sec, off 3 sec */
 			period = (1 + 3) * LED_ONE_SEC;
 			battery_ticks = battery_ticks % period;
@@ -89,7 +88,7 @@ static void board_led_set_battery(void)
 			else
 				color = LED_OFF;
 		} else if (chipset_in_or_transitioning_to_state(
-			   CHIPSET_STATE_ANY_OFF)) {
+				   CHIPSET_STATE_ANY_OFF)) {
 			/* Discharging in S5: off */
 			color = LED_OFF;
 		} else {
@@ -111,16 +110,16 @@ static void board_led_set_battery(void)
 		color = LED_BLUE;
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE) {
-			/* Factory mode: Blue 2 sec, Amber 2 sec */
-			period = (2 + 2) * LED_ONE_SEC;
-			battery_ticks = battery_ticks % period;
-			if (battery_ticks < 2 * LED_ONE_SEC)
-				color = LED_BLUE;
-			else
-				color = LED_AMBER;
-		} else
+		color = LED_BLUE;
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		/* Factory mode: Blue 2 sec, Amber 2 sec */
+		period = (2 + 2) * LED_ONE_SEC;
+		battery_ticks = battery_ticks % period;
+		if (battery_ticks < 2 * LED_ONE_SEC)
 			color = LED_BLUE;
+		else
+			color = LED_AMBER;
 		break;
 	default:
 		/* Other states don't alter LED behavior */
diff --git a/board/quackingstick/usbc_config.c b/board/quackingstick/usbc_config.c
index 1873e916ad..8107e2c286 100644
--- a/board/quackingstick/usbc_config.c
+++ b/board/quackingstick/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,8 +13,8 @@
 #include "usb_pd.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 const struct charger_config_t chg_chips[] = {
 	{
@@ -25,16 +25,16 @@ const struct charger_config_t chg_chips[] = {
 };
 
 struct temp_chg_step {
-	int low;	/* temp thershold ('C) to lower level*/
-	int high;	/* temp thershold ('C) to higher level */
-	int current;	/* charging limitation (mA) */
+	int low; /* temp thershold ('C) to lower level*/
+	int high; /* temp thershold ('C) to higher level */
+	int current; /* charging limitation (mA) */
 };
 
 static const struct temp_chg_step temp_chg_table[] = {
-	{.low =  0, .high = 50, .current = 3000},	/* Lv0: normal charge */
-	{.low = 48, .high = 53, .current = 1500},
-	{.low = 51, .high = 56, .current = 1000},
-	{.low = 54, .high = 100, .current = 800},
+	{ .low = 0, .high = 50, .current = 3000 }, /* Lv0: normal charge */
+	{ .low = 48, .high = 53, .current = 1500 },
+	{ .low = 51, .high = 56, .current = 1000 },
+	{ .low = 54, .high = 100, .current = 800 },
 };
 #define NUM_TEMP_CHG_LEVELS ARRAY_SIZE(temp_chg_table)
 
@@ -64,8 +64,9 @@ int charger_profile_override(struct charge_state_data *curr)
 		if (current_level >= NUM_TEMP_CHG_LEVELS)
 			current_level = NUM_TEMP_CHG_LEVELS - 1;
 
-		curr->requested_current = MIN(curr->requested_current,
-			temp_chg_table[current_level].current);
+		curr->requested_current =
+			MIN(curr->requested_current,
+			    temp_chg_table[current_level].current);
 	}
 
 	/* Lower the max requested voltage to 5V when battery is full. */
diff --git a/board/quiche/board.c b/board/quiche/board.c
index 67d4c00297..454cd2ce6a 100644
--- a/board/quiche/board.c
+++ b/board/quiche/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -29,8 +29,8 @@
 #include "usb_tc_sm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
 #define QUICHE_PD_DEBUG_LVL 1
 
@@ -104,29 +104,29 @@ static void board_usbc_usb3_interrupt(enum gpio_signal signal)
  * signals is driven by USB/MST hub power sequencing requirements.
  */
 const struct power_seq board_power_seq[] = {
-	{GPIO_EN_AC_JACK,               1, 20},
-	{GPIO_EC_DFU_MUX_CTRL,          0, 0},
-	{GPIO_EN_PP5000_A,              1, 31},
-	{GPIO_MST_LP_CTL_L,             1, 0},
-	{GPIO_EN_PP3300_B,              1, 1},
-	{GPIO_EN_PP1100_A,              1, 100+30},
-	{GPIO_EN_BB,                    1, 30},
-	{GPIO_EN_PP1050_A,              1, 30},
-	{GPIO_EN_PP1200_A,              1, 20},
-	{GPIO_EN_PP5000_C,              1, 20},
-	{GPIO_EN_PP5000_HSPORT,         1, 31},
-	{GPIO_EN_DP_SINK,               1, 80},
-	{GPIO_MST_RST_L,                1, 61},
-	{GPIO_EC_HUB2_RESET_L,          1, 41},
-	{GPIO_EC_HUB3_RESET_L,          1, 33},
-	{GPIO_DP_SINK_RESET,            1, 100},
-	{GPIO_USBC_DP_PD_RST_L,         1, 100},
-	{GPIO_USBC_UF_RESET_L,          1, 33},
-	{GPIO_DEMUX_DUAL_DP_PD_N,       1, 100},
-	{GPIO_DEMUX_DUAL_DP_RESET_N,    1, 100},
-	{GPIO_DEMUX_DP_HDMI_PD_N,       1, 10},
-	{GPIO_DEMUX_DUAL_DP_MODE,       1, 10},
-	{GPIO_DEMUX_DP_HDMI_MODE,       1, 5},
+	{ GPIO_EN_AC_JACK, 1, 20 },
+	{ GPIO_EC_DFU_MUX_CTRL, 0, 0 },
+	{ GPIO_EN_PP5000_A, 1, 31 },
+	{ GPIO_MST_LP_CTL_L, 1, 0 },
+	{ GPIO_EN_PP3300_B, 1, 1 },
+	{ GPIO_EN_PP1100_A, 1, 100 + 30 },
+	{ GPIO_EN_BB, 1, 30 },
+	{ GPIO_EN_PP1050_A, 1, 30 },
+	{ GPIO_EN_PP1200_A, 1, 20 },
+	{ GPIO_EN_PP5000_C, 1, 20 },
+	{ GPIO_EN_PP5000_HSPORT, 1, 31 },
+	{ GPIO_EN_DP_SINK, 1, 80 },
+	{ GPIO_MST_RST_L, 1, 61 },
+	{ GPIO_EC_HUB2_RESET_L, 1, 41 },
+	{ GPIO_EC_HUB3_RESET_L, 1, 33 },
+	{ GPIO_DP_SINK_RESET, 1, 100 },
+	{ GPIO_USBC_DP_PD_RST_L, 1, 100 },
+	{ GPIO_USBC_UF_RESET_L, 1, 33 },
+	{ GPIO_DEMUX_DUAL_DP_PD_N, 1, 100 },
+	{ GPIO_DEMUX_DUAL_DP_RESET_N, 1, 100 },
+	{ GPIO_DEMUX_DP_HDMI_PD_N, 1, 10 },
+	{ GPIO_DEMUX_DUAL_DP_MODE, 1, 10 },
+	{ GPIO_DEMUX_DP_HDMI_MODE, 1, 5 },
 };
 const size_t board_power_seq_count = ARRAY_SIZE(board_power_seq);
 
@@ -134,13 +134,13 @@ const size_t board_power_seq_count = ARRAY_SIZE(board_power_seq);
  * Define the strings used in our USB descriptors.
  */
 const void *const usb_strings[] = {
-	[USB_STR_DESC]         = usb_string_desc,
-	[USB_STR_VENDOR]       = USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]      = USB_STRING_DESC("Quiche"),
-	[USB_STR_SERIALNO]     = 0,
-	[USB_STR_VERSION]      =
-			USB_STRING_DESC(CROS_EC_SECTION ":" CROS_EC_VERSION32),
-	[USB_STR_UPDATE_NAME]  = USB_STRING_DESC("Firmware update"),
+	[USB_STR_DESC] = usb_string_desc,
+	[USB_STR_VENDOR] = USB_STRING_DESC("Google LLC"),
+	[USB_STR_PRODUCT] = USB_STRING_DESC("Quiche"),
+	[USB_STR_SERIALNO] = 0,
+	[USB_STR_VERSION] =
+		USB_STRING_DESC(CROS_EC_SECTION ":" CROS_EC_VERSION32),
+	[USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"),
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
 
@@ -159,8 +159,7 @@ struct ppc_config_t ppc_chips[] = {
  * PS8802 set mux board tuning.
  * Adds in board specific gain and DP lane count configuration
  */
-static int board_ps8822_mux_set(const struct usb_mux *me,
-				mux_state_t mux_state)
+static int board_ps8822_mux_set(const struct usb_mux *me, mux_state_t mux_state)
 {
 	int rv = EC_SUCCESS;
 
@@ -187,40 +186,38 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_HOST] = {
-		.usb_port = USB_PD_PORT_HOST,
-		.i2c_port = I2C_PORT_I2C1,
-		.i2c_addr_flags = PS8822_I2C_ADDR3_FLAG,
-		.driver = &ps8822_usb_mux_driver,
-		.board_set = &board_ps8822_mux_set,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_HOST,
+			.i2c_port = I2C_PORT_I2C1,
+			.i2c_addr_flags = PS8822_I2C_ADDR3_FLAG,
+			.driver = &ps8822_usb_mux_driver,
+			.board_set = &board_ps8822_mux_set,
+		},
 	},
 	[USB_PD_PORT_DP] = {
-		.usb_port = USB_PD_PORT_DP,
-		.i2c_port = I2C_PORT_I2C1,
-		.i2c_addr_flags = PS8XXX_I2C_ADDR2_FLAGS,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_DP,
+			.i2c_port = I2C_PORT_I2C1,
+			.i2c_addr_flags = PS8XXX_I2C_ADDR2_FLAGS,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 	},
 };
 
 /* USB-C PPC Configuration */
 struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_HOST] = {
-		.i2c_port = I2C_PORT_I2C1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	[USB_PD_PORT_DP] = {
-		.i2c_port = I2C_PORT_I2C1,
-		.i2c_addr_flags = SN5S330_ADDR2_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	[USB_PD_PORT_USB3] = {
-		.i2c_port = I2C_PORT_I2C3,
-		.i2c_addr_flags = SN5S330_ADDR1_FLAGS,
-		.drv = &sn5s330_drv
-	},
+	[USB_PD_PORT_HOST] = { .i2c_port = I2C_PORT_I2C1,
+			       .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+			       .drv = &sn5s330_drv },
+	[USB_PD_PORT_DP] = { .i2c_port = I2C_PORT_I2C1,
+			     .i2c_addr_flags = SN5S330_ADDR2_FLAGS,
+			     .drv = &sn5s330_drv },
+	[USB_PD_PORT_USB3] = { .i2c_port = I2C_PORT_I2C3,
+			       .i2c_addr_flags = SN5S330_ADDR1_FLAGS,
+			       .drv = &sn5s330_drv },
 };
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
@@ -366,14 +363,13 @@ static void board_usb_tc_disconnect(void)
 	if (port == USB_PD_PORT_HOST)
 		gpio_set_level(GPIO_UFP_PLUG_DET, 1);
 }
-DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, board_usb_tc_disconnect, \
+DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, board_usb_tc_disconnect,
 	     HOOK_PRIO_DEFAULT);
 
 #endif /* SECTION_IS_RW */
 
 static void board_init(void)
 {
-
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
@@ -410,7 +406,7 @@ void board_debug_gpio(enum debug_gpio trigger, int level, int pulse_usec)
 	}
 }
 
-static int command_dplane(int argc, char **argv)
+static int command_dplane(int argc, const char **argv)
 {
 	char *e;
 	int lane;
@@ -438,6 +434,4 @@ static int command_dplane(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(dplane, command_dplane,
-			"<2 | 4>",
-			"MST lane control.");
+DECLARE_CONSOLE_COMMAND(dplane, command_dplane, "<2 | 4>", "MST lane control.");
diff --git a/board/quiche/board.h b/board/quiche/board.h
index 98feab31f6..b1ba0c5eba 100644
--- a/board/quiche/board.h
+++ b/board/quiche/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,11 +20,10 @@
 #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
 #undef CONFIG_FLASH_PSTATE_LOCKED
 
-
 /* USB Type C and USB PD defines */
-#define USB_PD_PORT_HOST   0
-#define USB_PD_PORT_DP     1
-#define USB_PD_PORT_USB3   2
+#define USB_PD_PORT_HOST 0
+#define USB_PD_PORT_DP 1
+#define USB_PD_PORT_USB3 2
 
 /*
  * The host (C0) and display (C1) usbc ports are usb-pd capable. There is
@@ -41,9 +40,9 @@
 #define CONFIG_USB_PD_IDENTITY_SW_VERS 1
 
 /* I2C port names */
-#define I2C_PORT_I2C1	0
-#define I2C_PORT_I2C2	1
-#define I2C_PORT_I2C3	2
+#define I2C_PORT_I2C1 0
+#define I2C_PORT_I2C2 1
+#define I2C_PORT_I2C3 2
 
 /* Required symbolic I2C port names */
 #define I2C_PORT_MP4245 I2C_PORT_I2C3
@@ -71,7 +70,7 @@
 #define GPIO_TRIGGER_1 GPIO_EC_STATUS_LED1
 #define GPIO_TRIGGER_2 GPIO_EC_STATUS_LED2
 
-enum  debug_gpio {
+enum debug_gpio {
 	TRIGGER_1 = 0,
 	TRIGGER_2,
 };
diff --git a/board/quiche/build.mk b/board/quiche/build.mk
index 1a8ec0d625..76a59e502a 100644
--- a/board/quiche/build.mk
+++ b/board/quiche/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/quiche/ec.tasklist b/board/quiche/ec.tasklist
index cc36bf5a74..ffd4a604c9 100644
--- a/board/quiche/ec.tasklist
+++ b/board/quiche/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/quiche/gpio.inc b/board/quiche/gpio.inc
index 9514858ca7..afd18e5bb6 100644
--- a/board/quiche/gpio.inc
+++ b/board/quiche/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/rainier/board.c b/board/rainier/board.c
index c992584d76..07a006b671 100644
--- a/board/rainier/board.c
+++ b/board/rainier/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -40,8 +40,8 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
@@ -65,41 +65,39 @@ static void warm_reset_request_interrupt(enum gpio_signal signal)
 /******************************************************************************/
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] = {"BOARD_ID", 16, 4096, 0, STM32_AIN(10)},
+	[ADC_BOARD_ID] = { "BOARD_ID", 16, 4096, 0, STM32_AIN(10) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /******************************************************************************/
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "tcpc0",
-		.port = I2C_PORT_TCPC0,
-		.kbps = 1000,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	},
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 1000,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
 /* power signal list.  Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
-	{GPIO_PP1250_S3_PG,    POWER_SIGNAL_ACTIVE_HIGH, "PP1250_S3_PWR_GOOD"},
-	{GPIO_PP900_S0_PG,     POWER_SIGNAL_ACTIVE_HIGH, "PP900_S0_PWR_GOOD"},
-	{GPIO_AP_CORE_PG,      POWER_SIGNAL_ACTIVE_HIGH, "AP_PWR_GOOD"},
-	{GPIO_AP_EC_S3_S0_L,   POWER_SIGNAL_ACTIVE_LOW, "SUSPEND_DEASSERTED"},
+	{ GPIO_PP1250_S3_PG, POWER_SIGNAL_ACTIVE_HIGH, "PP1250_S3_PWR_GOOD" },
+	{ GPIO_PP900_S0_PG, POWER_SIGNAL_ACTIVE_HIGH, "PP900_S0_PWR_GOOD" },
+	{ GPIO_AP_CORE_PG, POWER_SIGNAL_ACTIVE_HIGH, "AP_PWR_GOOD" },
+	{ GPIO_AP_EC_S3_S0_L, POWER_SIGNAL_ACTIVE_LOW, "SUSPEND_DEASSERTED" },
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
 #ifdef CONFIG_TEMP_SENSOR_TMP432
 /* Temperature sensors data; must be in same order as enum temp_sensor_id. */
 const struct temp_sensor_t temp_sensors[] = {
-	{"TMP432_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-		TMP432_IDX_LOCAL, 4},
-	{"TMP432_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-		TMP432_IDX_REMOTE1, 4},
-	{"TMP432_Sensor_2", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-		TMP432_IDX_REMOTE2, 4},
+	{ "TMP432_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
+	  TMP432_IDX_LOCAL, 4 },
+	{ "TMP432_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
+	  TMP432_IDX_REMOTE1, 4 },
+	{ "TMP432_Sensor_2", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
+	  TMP432_IDX_REMOTE2, 4 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -108,9 +106,9 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
  * same order as enum temp_sensor_id. To always ignore any temp, use 0.
  */
 struct ec_thermal_config thermal_params[] = {
-	{{0, 0, 0}, 0, 0}, /* TMP432_Internal */
-	{{0, 0, 0}, 0, 0}, /* TMP432_Sensor_1 */
-	{{0, 0, 0}, 0, 0}, /* TMP432_Sensor_2 */
+	{ { 0, 0, 0 }, 0, 0 }, /* TMP432_Internal */
+	{ { 0, 0, 0 }, 0, 0 }, /* TMP432_Sensor_1 */
+	{ { 0, 0, 0 }, 0, 0 }, /* TMP432_Sensor_2 */
 };
 BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
 #endif
@@ -125,9 +123,8 @@ const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
 /******************************************************************************/
 /* Wake-up pins for hibernate */
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_POWER_BUTTON_L, GPIO_CHARGER_INT_L
-};
+const enum gpio_signal hibernate_wake_pins[] = { GPIO_POWER_BUTTON_L,
+						 GPIO_CHARGER_INT_L };
 const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 
 /******************************************************************************/
@@ -142,11 +139,14 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &virtual_usb_mux_driver,
+				.hpd_update = &virtual_hpd_update,
+			},
 	},
 };
 
@@ -173,8 +173,8 @@ int board_set_active_charge_port(int charge_port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			     int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	/*
 	 * NOP because there is no internal power therefore no charging.
@@ -190,7 +190,7 @@ int extpower_is_present(void)
 
 int pd_snk_is_vbus_provided(int port)
 {
-  /* Must be, if we're at a stage where this function is called. */
+	/* Must be, if we're at a stage where this function is called. */
 	return 1;
 }
 
@@ -207,8 +207,7 @@ static void board_spi_enable(void)
 
 	spi_enable(&spi_devices[0], 1);
 }
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP,
-	     board_spi_enable,
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_spi_enable,
 	     MOTION_SENSE_HOOK_PRIO - 1);
 
 static void board_spi_disable(void)
@@ -220,9 +219,8 @@ static void board_spi_disable(void)
 
 	gpio_config_module(MODULE_SPI_CONTROLLER, 0);
 }
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN,
-		 board_spi_disable,
-		 MOTION_SENSE_HOOK_PRIO + 1);
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_spi_disable,
+	     MOTION_SENSE_HOOK_PRIO + 1);
 
 static void board_init(void)
 {
@@ -255,8 +253,8 @@ void board_config_pre_init(void)
 	 * Ch4: USART1_TX / Ch5: USART1_RX (1000)
 	 * Ch6: SPI2_RX / Ch7: SPI2_TX (0011)
 	 */
-	STM32_DMA_CSELR(STM32_DMAC_CH4) = (8 << 12) | (8 << 16) |
-					  (3 << 20) | (3 << 24);
+	STM32_DMA_CSELR(STM32_DMAC_CH4) = (8 << 12) | (8 << 16) | (3 << 20) |
+					  (3 << 24);
 }
 
 void board_hibernate(void)
@@ -301,16 +299,16 @@ struct {
 	enum rainier_board_version version;
 	int expect_mv;
 } const rainier_boards[] = {
-	{ BOARD_VERSION_REV0, 109 },   /* 51.1K , 2.2K(gru 3.3K) ohm */
-	{ BOARD_VERSION_REV1, 211 },   /* 51.1k , 6.8K ohm */
-	{ BOARD_VERSION_REV2, 319 },   /* 51.1K , 11K ohm */
-	{ BOARD_VERSION_REV3, 427 },   /* 56K   , 17.4K ohm */
-	{ BOARD_VERSION_REV4, 542 },   /* 51.1K , 22K ohm */
-	{ BOARD_VERSION_REV5, 666 },   /* 51.1K , 30K ohm */
-	{ BOARD_VERSION_REV6, 781 },   /* 51.1K , 39.2K ohm */
-	{ BOARD_VERSION_REV7, 900 },   /* 56K   , 56K ohm */
-	{ BOARD_VERSION_REV8, 1023 },  /* 47K   , 61.9K ohm */
-	{ BOARD_VERSION_REV9, 1137 },  /* 47K   , 80.6K ohm */
+	{ BOARD_VERSION_REV0, 109 }, /* 51.1K , 2.2K(gru 3.3K) ohm */
+	{ BOARD_VERSION_REV1, 211 }, /* 51.1k , 6.8K ohm */
+	{ BOARD_VERSION_REV2, 319 }, /* 51.1K , 11K ohm */
+	{ BOARD_VERSION_REV3, 427 }, /* 56K   , 17.4K ohm */
+	{ BOARD_VERSION_REV4, 542 }, /* 51.1K , 22K ohm */
+	{ BOARD_VERSION_REV5, 666 }, /* 51.1K , 30K ohm */
+	{ BOARD_VERSION_REV6, 781 }, /* 51.1K , 39.2K ohm */
+	{ BOARD_VERSION_REV7, 900 }, /* 56K   , 56K ohm */
+	{ BOARD_VERSION_REV8, 1023 }, /* 47K   , 61.9K ohm */
+	{ BOARD_VERSION_REV9, 1137 }, /* 47K   , 80.6K ohm */
 	{ BOARD_VERSION_REV10, 1240 }, /* 56K   , 124K ohm */
 	{ BOARD_VERSION_REV11, 1343 }, /* 51.1K , 150K ohm */
 	{ BOARD_VERSION_REV12, 1457 }, /* 47K   , 200K ohm */
@@ -358,11 +356,9 @@ static struct mutex g_base_mutex;
 static struct bmi_drv_data_t g_bmi160_data;
 
 /* Matrix to rotate accelerometer into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1),  0},
-	{ FLOAT_TO_FP(-1), 0,  0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+				       { FLOAT_TO_FP(-1), 0, 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
 
 static struct bmp280_drv_data_t bmp280_drv_data;
 
@@ -436,9 +432,3 @@ int board_allow_i2c_passthru(const struct i2c_cmd_desc_t *cmd_desc)
 	 */
 	return 0;
 }
-
-int charge_prevent_power_on(int power_button_pressed)
-{
-	/* Assume there is always sufficient power from charger to power on. */
-	return 0;
-}
diff --git a/board/rainier/board.h b/board/rainier/board.h
index e3d333e2f1..3cf5405f9a 100644
--- a/board/rainier/board.h
+++ b/board/rainier/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,7 +10,7 @@
 
 /* Optional modules */
 #define CONFIG_ADC
-#undef  CONFIG_ADC_WATCHDOG
+#undef CONFIG_ADC_WATCHDOG
 #define CONFIG_CHIPSET_RK3399
 #define CONFIG_CMD_ACCELS
 #define CONFIG_CMD_RTC
@@ -30,11 +30,11 @@
 
 #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands for testing */
 
-#undef  CONFIG_UART_CONSOLE
+#undef CONFIG_UART_CONSOLE
 #define CONFIG_UART_CONSOLE 1
 
 /* Region sizes are no longer a power of 2 so we can't enable MPU */
-#undef  CONFIG_MPU
+#undef CONFIG_MPU
 
 /* Enable a different power-on sequence than the one on gru */
 #undef CONFIG_CHIPSET_POWER_SEQ_VERSION
@@ -104,38 +104,38 @@
 #define CONFIG_USB_PD_COMM_LOCKED
 
 #define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_VOLTAGE_MV     12850
+#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 12850
 
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY 50000  /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 50000 /* us */
 
 /* Timer selection */
-#define TIM_CLOCK32  2
+#define TIM_CLOCK32 2
 #define TIM_WATCHDOG 7
 
 /* 48 MHz SYSCLK clock frequency */
 #define CPU_CLOCK 48000000
 
 /* Optional for testing */
-#undef  CONFIG_PECI
-#undef  CONFIG_PSTORE
+#undef CONFIG_PECI
+#undef CONFIG_PSTORE
 
 #define CONFIG_TASK_PROFILING
 
 #define I2C_PORT_TCPC0 1
 
 /* Enable Accel over SPI */
-#define CONFIG_SPI_ACCEL_PORT    0  /* The first SPI controller port (SPI2) */
+#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */
 
 #define CONFIG_MKBP_INPUT_DEVICES
 #define CONFIG_MKBP_EVENT
 #define CONFIG_MKBP_USE_GPIO
 /* Define the host events which are allowed to wakeup AP in S3. */
-#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \
-		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC))
+#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK                \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC))
 
 #ifndef __ASSEMBLER__
 
diff --git a/board/rainier/build.mk b/board/rainier/build.mk
index b77a900d56..b95d9dc46e 100644
--- a/board/rainier/build.mk
+++ b/board/rainier/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/rainier/ec.tasklist b/board/rainier/ec.tasklist
index ed574a1d6a..5008495942 100644
--- a/board/rainier/ec.tasklist
+++ b/board/rainier/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/rainier/gpio.inc b/board/rainier/gpio.inc
index f5a4f360b3..1cf1080e05 100644
--- a/board/rainier/gpio.inc
+++ b/board/rainier/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/rainier/usb_pd_policy.c b/board/rainier/usb_pd_policy.c
index 6de1dc9271..45a51015a6 100644
--- a/board/rainier/usb_pd_policy.c
+++ b/board/rainier/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,8 +18,8 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 static uint8_t vbus_en;
 
diff --git a/board/rammus/battery.c b/board/rammus/battery.c
index 1ae15e9dcc..9a538cc5e6 100644
--- a/board/rammus/battery.c
+++ b/board/rammus/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -17,8 +17,8 @@
 static enum battery_present batt_pres_prev = BP_NOT_SURE;
 
 /* Shutdown mode parameters to write to manufacturer access register */
-#define SB_SHIP_MODE_REG	SB_MANUFACTURER_ACCESS
-#define SB_SHUTDOWN_DATA	0x0010
+#define SB_SHIP_MODE_REG SB_MANUFACTURER_ACCESS
+#define SB_SHUTDOWN_DATA 0x0010
 
 static const struct battery_info info = {
 	.voltage_max = 13200,
@@ -63,8 +63,9 @@ static int battery_init(void)
 {
 	int batt_status;
 
-	return battery_status(&batt_status) ? 0 :
-		!!(batt_status & STATUS_INITIALIZED);
+	return battery_status(&batt_status) ?
+		       0 :
+		       !!(batt_status & STATUS_INITIALIZED);
 }
 
 /*
@@ -85,13 +86,13 @@ static int battery_check_disconnect(void)
 	uint8_t data[6];
 
 	/* Check if battery charging + discharging is disabled. */
-	rv = sb_read_mfgacc(PARAM_OPERATION_STATUS,
-			    SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data));
+	rv = sb_read_mfgacc(PARAM_OPERATION_STATUS, SB_ALT_MANUFACTURER_ACCESS,
+			    data, sizeof(data));
 	if (rv)
 		return BATTERY_DISCONNECT_ERROR;
 
-	if ((data[3] & (BATTERY_DISCHARGING_DISABLED |
-			BATTERY_CHARGING_DISABLED)) ==
+	if ((data[3] &
+	     (BATTERY_DISCHARGING_DISABLED | BATTERY_CHARGING_DISABLED)) ==
 	    (BATTERY_DISCHARGING_DISABLED | BATTERY_CHARGING_DISABLED))
 		return BATTERY_DISCONNECTED;
 
diff --git a/board/rammus/board.c b/board/rammus/board.c
index a27828694d..8cbc6c6856 100644
--- a/board/rammus/board.c
+++ b/board/rammus/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -39,6 +39,7 @@
 #include "math_util.h"
 #include "motion_lid.h"
 #include "motion_sense.h"
+#include "panic.h"
 #include "pi3usb9281.h"
 #include "power.h"
 #include "power_button.h"
@@ -59,11 +60,11 @@
 #include "util.h"
 #include "espi.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
-#define USB_PD_PORT_PS8751	1
-#define USB_PD_PORT_ANX7447	0
+#define USB_PD_PORT_PS8751 1
+#define USB_PD_PORT_ANX7447 0
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
@@ -130,53 +131,44 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* Vbus sensing (10x voltage divider). */
-	[ADC_VBUS] = {"VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0},
+	[ADC_VBUS] = { "VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT * 10,
+		       ADC_READ_MAX + 1, 0 },
 	/*
 	 * Adapter current output or battery charging/discharging current (uV)
 	 * 18x amplification on charger side.
 	 */
-	[ADC_AMON_BMON] = {"AMON_BMON", NPCX_ADC_CH1, ADC_MAX_VOLT*1000/18,
-			   ADC_READ_MAX+1, 0},
+	[ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH1, ADC_MAX_VOLT * 1000 / 18,
+			    ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* I2C port map */
-const struct i2c_port_t i2c_ports[]  = {
-	{
-		.name = "i2c_0_0",
-		.port = NPCX_I2C_PORT0_0,
-		.kbps = 400,
-		.scl  = GPIO_I2C0_0_SCL,
-		.sda  = GPIO_I2C0_0_SDA
-	},
-	{
-		.name = "i2c_0_1",
-		.port = NPCX_I2C_PORT0_1,
-		.kbps = 400,
-		.scl  = GPIO_I2C0_1_SCL,
-		.sda  = GPIO_I2C0_1_SDA
-	},
-	{
-		.name = "i2c_1",
-		.port = NPCX_I2C_PORT1,
-		.kbps = 100,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	},
-	{
-		.name = "i2c_2",
-		.port = NPCX_I2C_PORT2,
-		.kbps = 400,
-		.scl  = GPIO_I2C2_SCL,
-		.sda  = GPIO_I2C2_SDA
-	},
-	{
-		.name = "i2c_3",
-		.port = NPCX_I2C_PORT3,
-		.kbps = 400,
-		.scl  = GPIO_I2C3_SCL,
-		.sda  = GPIO_I2C3_SDA
-	},
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "i2c_0_0",
+	  .port = NPCX_I2C_PORT0_0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_0_SCL,
+	  .sda = GPIO_I2C0_0_SDA },
+	{ .name = "i2c_0_1",
+	  .port = NPCX_I2C_PORT0_1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_1_SCL,
+	  .sda = GPIO_I2C0_1_SDA },
+	{ .name = "i2c_1",
+	  .port = NPCX_I2C_PORT1,
+	  .kbps = 100,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "i2c_2",
+	  .port = NPCX_I2C_PORT2,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "i2c_3",
+	  .port = NPCX_I2C_PORT3,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -210,16 +202,20 @@ struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_PS8751] = {
-		.usb_port = USB_PD_PORT_PS8751,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_PS8751,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 	},
 	[USB_PD_PORT_ANX7447] = {
-		.usb_port = USB_PD_PORT_ANX7447,
-		.driver = &anx7447_usb_mux_driver,
-		.hpd_update = &anx7447_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_ANX7447,
+			.driver = &anx7447_usb_mux_driver,
+			.hpd_update = &anx7447_tcpc_update_hpd_status,
+		},
 	}
 };
 
@@ -262,7 +258,7 @@ static void ps8751_i2c_remap(void)
 	uint32_t board_version;
 
 	if (cbi_get_board_version(&board_version) != EC_SUCCESS ||
-		board_version > 1)
+	    board_version > 1)
 		return;
 	/*
 	 * Due to b/118063849, we separate the ps8751 and anx3447 to
@@ -293,9 +289,9 @@ void board_tcpc_init(void)
 	 */
 	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
 		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
 
 uint16_t tcpc_get_alert_status(void)
 {
@@ -315,17 +311,17 @@ uint16_t tcpc_get_alert_status(void)
 }
 
 const struct temp_sensor_t temp_sensors[] = {
-	{"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0},
+	{ "Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0 },
 
 	/* These BD99992GW temp sensors are only readable in S0 */
-	{"Ambient", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM0},
-	{"Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM1},
-	{"DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM2},
-	{"eMMC", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
-	 BD99992GW_ADC_CHANNEL_SYSTHERM3},
+	{ "Ambient", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM0 },
+	{ "Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM1 },
+	{ "DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM2 },
+	{ "eMMC", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+	  BD99992GW_ADC_CHANNEL_SYSTHERM3 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -341,8 +337,8 @@ static void board_report_pmic_fault(const char *str)
 	uint32_t info;
 
 	/* RESETIRQ1 -- Bit 4: VRFAULT */
-	if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x8, &vrfault)
-	    != EC_SUCCESS)
+	if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x8, &vrfault) !=
+	    EC_SUCCESS)
 		return;
 
 	if (!(vrfault & BIT(4)))
@@ -433,8 +429,7 @@ static void board_pmic_enable_slp_s0_vr_decay(void)
 	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x38, 0x7a);
 }
 
-__override void power_board_handle_host_sleep_event(
-		enum host_sleep_event state)
+__override void power_board_handle_host_sleep_event(enum host_sleep_event state)
 {
 	if (state == HOST_SLEEP_EVENT_S0IX_SUSPEND)
 		board_pmic_enable_slp_s0_vr_decay();
@@ -508,7 +503,7 @@ static void usb_charge_mode_init(void)
 	 * inhibit_charging_in_suspend.
 	 */
 	usb_charge_set_mode(0, CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE,
-			USB_DISALLOW_SUSPEND_CHARGE);
+			    USB_DISALLOW_SUSPEND_CHARGE);
 }
 DECLARE_HOOK(HOOK_INIT, usb_charge_mode_init, HOOK_PRIO_DEFAULT + 1);
 
@@ -552,10 +547,12 @@ int board_set_active_charge_port(int charge_port)
 	} else {
 		/* Make sure non-charging port is disabled */
 		gpio_set_level(charge_port ? GPIO_EN_USB_C0_CHARGE_EC_L :
-					     GPIO_EN_USB_C1_CHARGE_EC_L, 1);
+					     GPIO_EN_USB_C1_CHARGE_EC_L,
+			       1);
 		/* Enable charging port */
 		gpio_set_level(charge_port ? GPIO_EN_USB_C1_CHARGE_EC_L :
-					     GPIO_EN_USB_C0_CHARGE_EC_L, 0);
+					     GPIO_EN_USB_C0_CHARGE_EC_L,
+			       0);
 	}
 
 	return EC_SUCCESS;
@@ -569,8 +566,8 @@ int board_set_active_charge_port(int charge_port)
  * @param charge_ma     Desired charge limit (mA).
  * @param charge_mv     Negotiated charge voltage (mV).
  */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	/*
 	 * Limit the input current to 96% negotiated limit,
@@ -578,8 +575,7 @@ void board_set_charge_limit(int port, int supplier, int charge_ma,
 	 */
 	charge_ma = charge_ma * 96 / 100;
 	charge_set_input_current_limit(
-			MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT),
-			charge_mv);
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 void board_hibernate(void)
@@ -625,23 +621,17 @@ static struct accelgyro_saved_data_t g_bma255_data;
 static struct kionix_accel_data g_kx022_data;
 
 /* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0 },
-	{ 0,  FLOAT_TO_FP(-1), 0 },
-	{ 0, 0, FLOAT_TO_FP(-1) }
-};
+const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+				       { 0, FLOAT_TO_FP(-1), 0 },
+				       { 0, 0, FLOAT_TO_FP(-1) } };
 
-const mat33_fp_t base_standard_ref_icm = {
-	{ 0, FLOAT_TO_FP(1), 0 },
-	{ FLOAT_TO_FP(1), 0, 0 },
-	{ 0, 0, FLOAT_TO_FP(-1) }
-};
+const mat33_fp_t base_standard_ref_icm = { { 0, FLOAT_TO_FP(1), 0 },
+					   { FLOAT_TO_FP(1), 0, 0 },
+					   { 0, 0, FLOAT_TO_FP(-1) } };
 
-const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0 },
-	{ 0,  FLOAT_TO_FP(1), 0 },
-	{ 0, 0, FLOAT_TO_FP(-1) }
-};
+const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				      { 0, FLOAT_TO_FP(1), 0 },
+				      { 0, 0, FLOAT_TO_FP(-1) } };
 
 struct motion_sensor_t base_accel_icm = {
 	.name = "Base Accel",
diff --git a/board/rammus/board.h b/board/rammus/board.h
index e044148401..77515a40ba 100644
--- a/board/rammus/board.h
+++ b/board/rammus/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,7 +12,7 @@
  * By default, enable all console messages excepted HC, ACPI and event:
  * The sensor stack is generating a lot of activity.
  */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
 #undef CONFIG_HOSTCMD_DEBUG_MODE
 #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
 
@@ -29,7 +29,7 @@
 #define CONFIG_I2C
 #define CONFIG_I2C_CONTROLLER
 #define CONFIG_KEYBOARD_COL2_INVERTED
-#undef  CONFIG_KEYBOARD_VIVALDI
+#undef CONFIG_KEYBOARD_VIVALDI
 #define CONFIG_KEYBOARD_PROTOCOL_8042
 #define CONFIG_LED_COMMON
 #define CONFIG_LID_SWITCH
@@ -67,8 +67,8 @@
 #define CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET
 #define CONFIG_CHIPSET_RESET_HOOK
 #define CONFIG_HOST_INTERFACE_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 #define CONFIG_HOSTCMD_FLASH_SPI_INFO
 
 /* Battery */
@@ -92,8 +92,8 @@
 #define CONFIG_CMD_CHARGER_ADC_AMON_BMON
 #define CONFIG_HOSTCMD_PD_CONTROL
 #define CONFIG_EXTPOWER_GPIO
-#undef   CONFIG_EXTPOWER_DEBOUNCE_MS
-#define  CONFIG_EXTPOWER_DEBOUNCE_MS 1000
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
+#define CONFIG_EXTPOWER_DEBOUNCE_MS 1000
 #define CONFIG_POWER_BUTTON
 #define CONFIG_POWER_BUTTON_X86
 #define CONFIG_POWER_COMMON
@@ -140,7 +140,7 @@
 /* Depends on how fast the AP boots and typical ODRs */
 #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
 
-#undef  CONFIG_UART_TX_BUF_SIZE
+#undef CONFIG_UART_TX_BUF_SIZE
 #define CONFIG_UART_TX_BUF_SIZE 1024
 
 #define CONFIG_TABLET_MODE
@@ -181,45 +181,45 @@
 #define CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT 2
 
 /* Optional feature to configure npcx chip */
-#define NPCX_UART_MODULE2	1 /* 1:GPIO64/65 as UART */
-#define NPCX_JTAG_MODULE2	0 /* 0:GPIO21/17/16/20 as JTAG */
-#define NPCX_TACH_SEL2		0 /* 0:GPIO40/73 as TACH */
+#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART */
+#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 as JTAG */
+#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 as TACH */
 
 /* I2C ports */
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT0_0
-#define I2C_PORT_TCPC1		NPCX_I2C_PORT0_1
-#define I2C_PORT_USB_CHARGER_1	NPCX_I2C_PORT0_1
-#define I2C_PORT_USB_CHARGER_0	NPCX_I2C_PORT1
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT1
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT0_0
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT1
-#define I2C_PORT_PMIC		NPCX_I2C_PORT2
-#define I2C_PORT_MP2949		NPCX_I2C_PORT2
-#define I2C_PORT_GYRO		NPCX_I2C_PORT3
-#define I2C_PORT_ACCEL		I2C_PORT_GYRO
-#define I2C_PORT_THERMAL	I2C_PORT_PMIC
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0
+#define I2C_PORT_TCPC1 NPCX_I2C_PORT0_1
+#define I2C_PORT_USB_CHARGER_1 NPCX_I2C_PORT0_1
+#define I2C_PORT_USB_CHARGER_0 NPCX_I2C_PORT1
+#define I2C_PORT_CHARGER NPCX_I2C_PORT1
+#define I2C_PORT_EEPROM NPCX_I2C_PORT0_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT1
+#define I2C_PORT_PMIC NPCX_I2C_PORT2
+#define I2C_PORT_MP2949 NPCX_I2C_PORT2
+#define I2C_PORT_GYRO NPCX_I2C_PORT3
+#define I2C_PORT_ACCEL I2C_PORT_GYRO
+#define I2C_PORT_THERMAL I2C_PORT_PMIC
 
 /* I2C addresses */
-#define I2C_ADDR_BD99992_FLAGS	0x30
-#define I2C_ADDR_MP2949_FLAGS	0x20
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_ADDR_BD99992_FLAGS 0x30
+#define I2C_ADDR_MP2949_FLAGS 0x20
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 
 /* Rename GPIOs */
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_SUS_L	GPIO_SLP_SUS_L_PCH
-#define GPIO_PG_EC_RSMRST_ODL	GPIO_ROP_EC_RSMRST_L
-#define GPIO_PMIC_DPWROK	GPIO_ROP_DSW_PWROK
-#define GPIO_POWER_BUTTON_L	GPIO_PWR_BTN_ODL
-#define GPIO_VOLUME_DOWN_L	GPIO_VOLDN_BTN
-#define GPIO_VOLUME_UP_L	GPIO_VOLUP_BTN
-#define GPIO_AC_PRESENT		GPIO_ROP_EC_ACOK
-#define GPIO_ENABLE_BACKLIGHT	GPIO_BL_DISABLE_L
-#define GPIO_CPU_PROCHOT	GPIO_PCH_PROCHOT
-#define GPIO_PCH_PWRBTN_L	GPIO_PCH_PWR_BTN_L
-#define GPIO_EC_PLATFORM_RST	GPIO_PLATFORM_RST
-#define GPIO_PMIC_SLP_SUS_L	GPIO_SLP_SUS_L_PMIC
-#define GPIO_USB_C0_5V_EN	GPIO_EN_USB_C0_5V_OUT
-#define GPIO_USB_C1_5V_EN	GPIO_EN_USB_C1_5V_OUT
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_SUS_L GPIO_SLP_SUS_L_PCH
+#define GPIO_PG_EC_RSMRST_ODL GPIO_ROP_EC_RSMRST_L
+#define GPIO_PMIC_DPWROK GPIO_ROP_DSW_PWROK
+#define GPIO_POWER_BUTTON_L GPIO_PWR_BTN_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN
+#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN
+#define GPIO_AC_PRESENT GPIO_ROP_EC_ACOK
+#define GPIO_ENABLE_BACKLIGHT GPIO_BL_DISABLE_L
+#define GPIO_CPU_PROCHOT GPIO_PCH_PROCHOT
+#define GPIO_PCH_PWRBTN_L GPIO_PCH_PWR_BTN_L
+#define GPIO_EC_PLATFORM_RST GPIO_PLATFORM_RST
+#define GPIO_PMIC_SLP_SUS_L GPIO_SLP_SUS_L_PMIC
+#define GPIO_USB_C0_5V_EN GPIO_EN_USB_C0_5V_OUT
+#define GPIO_USB_C1_5V_EN GPIO_EN_USB_C1_5V_OUT
 
 #ifndef __ASSEMBLER__
 
@@ -227,11 +227,11 @@
 #include "registers.h"
 
 enum temp_sensor_id {
-	TEMP_SENSOR_BATTERY,	/* Smart Battery Temperature */
-	TEMP_SENSOR_AMBIENT,	/* BD99992GW SYSTHERM0 */
-	TEMP_SENSOR_CHARGER,	/* BD99992GW SYSTHERM1 */
-	TEMP_SENSOR_DRAM,	/* BD99992GW SYSTHERM2 */
-	TEMP_SENSOR_EMMC,	/* BD99992GW SYSTHERM3 */
+	TEMP_SENSOR_BATTERY, /* Smart Battery Temperature */
+	TEMP_SENSOR_AMBIENT, /* BD99992GW SYSTHERM0 */
+	TEMP_SENSOR_CHARGER, /* BD99992GW SYSTHERM1 */
+	TEMP_SENSOR_DRAM, /* BD99992GW SYSTHERM2 */
+	TEMP_SENSOR_EMMC, /* BD99992GW SYSTHERM3 */
 	TEMP_SENSOR_COUNT
 };
 
@@ -248,11 +248,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum adc_channel {
-	ADC_VBUS,
-	ADC_AMON_BMON,
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_VBUS, ADC_AMON_BMON, ADC_CH_COUNT };
 
 enum pwm_channel {
 	PWM_CH_KBLIGHT,
@@ -265,16 +261,16 @@ enum pwm_channel {
  * delay to turn on the power supply max is ~16ms.
  * delay to turn off the power supply max is about ~180ms.
  */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	250000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* delay to turn on/off vconn */
 
 /* Define typical operating power and max power */
-#define PD_OPERATING_POWER_MW		15000
-#define PD_MAX_POWER_MW			45000
-#define PD_MAX_CURRENT_MA		3000
-#define PD_MAX_VOLTAGE_MV		20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 45000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Board specific handlers */
 void board_reset_pd_mcu(void);
diff --git a/board/rammus/build.mk b/board/rammus/build.mk
index 5a9cabdcae..9bc5e8a822 100644
--- a/board/rammus/build.mk
+++ b/board/rammus/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/rammus/cbi_ssfc.c b/board/rammus/cbi_ssfc.c
index e1f6fa4bd2..99c303eac5 100644
--- a/board/rammus/cbi_ssfc.c
+++ b/board/rammus/cbi_ssfc.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,7 +23,7 @@ static void cbi_ssfc_init(void)
 
 	CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value);
 }
-DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_INIT_I2C+1);
+DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_INIT_I2C + 1);
 
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
 {
diff --git a/board/rammus/cbi_ssfc.h b/board/rammus/cbi_ssfc.h
index 2ca20f2376..e6351db03f 100644
--- a/board/rammus/cbi_ssfc.h
+++ b/board/rammus/cbi_ssfc.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/rammus/ec.tasklist b/board/rammus/ec.tasklist
index f708a41386..c2738d28b5 100644
--- a/board/rammus/ec.tasklist
+++ b/board/rammus/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/rammus/gpio.inc b/board/rammus/gpio.inc
index 1e05cbe9a7..df12930ccd 100644
--- a/board/rammus/gpio.inc
+++ b/board/rammus/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/rammus/led.c b/board/rammus/led.c
index e6187ce4b5..5ae415a61a 100644
--- a/board/rammus/led.c
+++ b/board/rammus/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -23,9 +23,8 @@
 #define LED_CHARGE_PULSE 10
 #define LED_POWER_PULSE 15
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-	EC_LED_ID_BATTERY_LED};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED,
+					     EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -47,24 +46,20 @@ enum led_power_state {
 };
 
 static const struct {
-	uint8_t led1:1;
-	uint8_t led2:1;
-} led_chg_state_table[] = {
-	[LED_STATE_DISCHARGE] = {LED_OFF, LED_OFF},
-	[LED_STATE_CHARGE] = {LED_OFF, LED_ON},
-	[LED_STATE_FULL] = {LED_ON, LED_OFF},
-	[LED_STATE_ERROR_PHASE0] = {LED_OFF, LED_OFF},
-	[LED_STATE_ERROR_PHASE1] = {LED_OFF, LED_ON}
-};
+	uint8_t led1 : 1;
+	uint8_t led2 : 1;
+} led_chg_state_table[] = { [LED_STATE_DISCHARGE] = { LED_OFF, LED_OFF },
+			    [LED_STATE_CHARGE] = { LED_OFF, LED_ON },
+			    [LED_STATE_FULL] = { LED_ON, LED_OFF },
+			    [LED_STATE_ERROR_PHASE0] = { LED_OFF, LED_OFF },
+			    [LED_STATE_ERROR_PHASE1] = { LED_OFF, LED_ON } };
 
 static const struct {
-	uint8_t led:1;
-} led_pwr_state_table[] = {
-	[LED_STATE_S0] = {LED_ON},
-	[LED_STATE_S3_PHASE0] = {LED_OFF},
-	[LED_STATE_S3_PHASE1] = {LED_ON},
-	[LED_STATE_S5] = {LED_OFF}
-};
+	uint8_t led : 1;
+} led_pwr_state_table[] = { [LED_STATE_S0] = { LED_ON },
+			    [LED_STATE_S3_PHASE0] = { LED_OFF },
+			    [LED_STATE_S3_PHASE1] = { LED_ON },
+			    [LED_STATE_S5] = { LED_OFF } };
 
 void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
 {
@@ -100,7 +95,7 @@ static void rammus_led_set_power(void)
 
 	chipset_state = chipset_in_state(CHIPSET_STATE_HARD_OFF) |
 			(chipset_in_state(CHIPSET_STATE_SOFT_OFF) << 1) |
-			(chipset_in_state(CHIPSET_STATE_SUSPEND)  << 2) |
+			(chipset_in_state(CHIPSET_STATE_SUSPEND) << 2) |
 			(chipset_in_state(CHIPSET_STATE_ON) << 3) |
 			(chipset_in_state(CHIPSET_STATE_STANDBY) << 4);
 
@@ -136,7 +131,7 @@ static void rammus_led_set_battery(void)
 	switch (chg_state) {
 	case PWR_STATE_DISCHARGE:
 		if ((charge_get_flags() & CHARGE_FLAG_EXTERNAL_POWER) &&
-			charge_percent >= BATTERY_LEVEL_NEAR_FULL)
+		    charge_percent >= BATTERY_LEVEL_NEAR_FULL)
 			config_battery_led(LED_STATE_FULL);
 		else
 			config_battery_led(LED_STATE_DISCHARGE);
@@ -154,10 +149,11 @@ static void rammus_led_set_battery(void)
 		break;
 	case PWR_STATE_CHARGE_NEAR_FULL:
 	case PWR_STATE_IDLE:
-		if(charge_get_flags() & CHARGE_FLAG_EXTERNAL_POWER)
-			config_battery_led(LED_STATE_FULL);
-		else
-			config_battery_led(LED_STATE_DISCHARGE);
+		config_battery_led(LED_STATE_DISCHARGE);
+		charge_ticks = 0;
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		config_battery_led(LED_STATE_FULL);
 		charge_ticks = 0;
 		break;
 	default:
diff --git a/board/rammus/usb_pd_policy.c b/board/rammus/usb_pd_policy.c
index 652c9bb259..6242625d26 100644
--- a/board/rammus/usb_pd_policy.c
+++ b/board/rammus/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,12 +21,12 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT];
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5,
-							TYPEC_RP_1A5};
+static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5,
+							 TYPEC_RP_1A5 };
 
 int board_vbus_source_enabled(int port)
 {
@@ -53,7 +53,8 @@ int pd_set_power_supply_ready(int port)
 {
 	/* Disable charging */
 	gpio_set_level(port ? GPIO_EN_USB_C1_CHARGE_EC_L :
-			      GPIO_EN_USB_C0_CHARGE_EC_L, 1);
+			      GPIO_EN_USB_C0_CHARGE_EC_L,
+		       1);
 
 	/* Ensure we advertise the proper available current quota */
 	charge_manager_source_port(port, 1);
@@ -103,13 +104,11 @@ int pd_check_vconn_swap(int port)
 	return gpio_get_level(GPIO_SLP_SUS_L_PMIC);
 }
 
-__override void pd_execute_data_swap(int port,
-				     enum pd_data_role data_role)
+__override void pd_execute_data_swap(int port, enum pd_data_role data_role)
 {
 	/* Only port 0 supports device mode. */
 	if (port != 0)
 		return;
 
-	gpio_set_level(GPIO_USB2_ID2,
-		      (data_role == PD_ROLE_UFP) ? 1 : 0);
+	gpio_set_level(GPIO_USB2_ID2, (data_role == PD_ROLE_UFP) ? 1 : 0);
 }
diff --git a/board/redrix/battery.c b/board/redrix/battery.c
index 4e74b92acb..c5c144113b 100644
--- a/board/redrix/battery.c
+++ b/board/redrix/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/redrix/board.c b/board/redrix/board.c
index 5cf76b5447..e66a1ce518 100644
--- a/board/redrix/board.c
+++ b/board/redrix/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -31,8 +31,8 @@
 #include "gpio_list.h" /* Must come after other header files. */
 
 /* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 /* Battery discharging over-current limit is 8A */
 #define BATT_OC_LIMIT -8000
diff --git a/board/redrix/board.h b/board/redrix/board.h
index 96b48bd6be..211af39816 100644
--- a/board/redrix/board.h
+++ b/board/redrix/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,15 +23,15 @@
 #define CONFIG_CHIPSET_RESUME_INIT_HOOK
 
 /* Sensors */
-#define CONFIG_ACCEL_BMA255		/* Lid accel */
-#define CONFIG_ACCEL_BMA4XX		/* 2nd source Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM	/* Base accel */
+#define CONFIG_ACCEL_BMA255 /* Lid accel */
+#define CONFIG_ACCEL_BMA4XX /* 2nd source Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
 #define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE	BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID	LID_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
 
 /* TCS3400 ALS */
 #define CONFIG_ALS
@@ -48,9 +48,7 @@
 #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
 
 /* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
-	(BIT(LID_ACCEL) | BIT(CLEAR_ALS))
-
+#define CONFIG_ACCEL_FORCE_MODE_MASK (BIT(LID_ACCEL) | BIT(CLEAR_ALS))
 
 /* Sensor console commands */
 #define CONFIG_CMD_ACCELS
@@ -65,7 +63,7 @@
 #endif
 
 /* USB Type A Features */
-#define USB_PORT_COUNT			1
+#define USB_PORT_COUNT 1
 #define CONFIG_USB_PORT_POWER_DUMB
 
 /* USB Type C and USB PD defines */
@@ -73,7 +71,7 @@
 
 #define CONFIG_IO_EXPANDER
 #define CONFIG_IO_EXPANDER_NCT38XX
-#define CONFIG_IO_EXPANDER_PORT_COUNT		2
+#define CONFIG_IO_EXPANDER_PORT_COUNT 2
 
 #define CONFIG_USB_PD_FRS_PPC
 
@@ -83,17 +81,17 @@
 #define CONFIG_USBC_PPC_NX20P3483
 
 /* TODO: b/193452481 - measure and check these values on redrix */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
 
 /*
  * Passive USB-C cables only support up to 60W.
  */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /*
  * Macros for GPIO signals used in common code that don't match the
@@ -101,73 +99,74 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT		GPIO_EC_EN_EDP_BL
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_GSC_PACKET_MODE
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SYS_SLP_S0IX_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_TEMP_SENSOR_POWER		GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
 
 /*
  * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
  * signal.
  */
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_SEQ_EC_ALL_SYS_PG
-#define GPIO_PG_EC_DSW_PWROK		GPIO_SEQ_EC_DSW_PWROK
-#define GPIO_PG_EC_RSMRST_ODL		GPIO_SEQ_EC_RSMRST_ODL
-#define GPIO_POWER_BUTTON_L		GPIO_GSC_EC_PWR_BTN_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_ODL
-
-#define GPIO_WLC_NRST_CONN		GPIO_PEN_RST_L
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
+
+#define GPIO_WLC_NRST_CONN GPIO_PEN_RST_L
 
 /* System has back-lit keyboard */
 #define CONFIG_PWM_KBLIGHT
 
 /* I2C Bus Configuration */
 
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
 
-#define I2C_PORT_USB_C0_TCPC	NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1_TCPC	NPCX_I2C_PORT4_1
+#define I2C_PORT_USB_C0_TCPC NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1
 
-#define I2C_PORT_USB_C0_PPC	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_PPC	NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C0_PPC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1
 
-#define I2C_PORT_USB_C0_BC12	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_BC12	NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C0_BC12 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1
 
-#define I2C_PORT_USB_C0_MUX	NPCX_I2C_PORT3_0
-#define I2C_PORT_USB_C1_MUX	NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C0_MUX NPCX_I2C_PORT3_0
+#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1
 
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT5_0
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT7_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-#define I2C_PORT_WLC		NPCX_I2C_PORT7_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_WLC NPCX_I2C_PORT7_0
 
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 
 /*
  * see b/174768555#comment22
  */
-#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR	0x56
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x58
+#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x56
+#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x58
 
 /* Enabling Thunderbolt-compatible mode */
 #define CONFIG_USB_PD_TBT_COMPAT_MODE
 
 /* Enabling USB4 mode */
 #define CONFIG_USB_PD_USB4
+#define CONFIG_USB_PD_DATA_RESET_MSG
 
 /* Retimer */
 #define CONFIG_USBC_RETIMER_FW_UPDATE
@@ -179,9 +178,9 @@
 #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
 
 /* Fan features */
-#define CONFIG_FANS		FAN_CH_COUNT
+#define CONFIG_FANS FAN_CH_COUNT
 #define CONFIG_CUSTOM_FAN_CONTROL
-#define RPM_DEVIATION	1
+#define RPM_DEVIATION 1
 
 /* Charger defines */
 #define CONFIG_CHARGER_BQ25720
@@ -192,12 +191,12 @@
  * discharge current limit and what was tested to prevent the AP
  * rebooting with low charge level batteries.
  */
-#define CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA	8192
+#define CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA 8192
 #define CONFIG_CHARGER_BQ25720_VSYS_TH2_CUSTOM
-#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV	70
+#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV 70
 #define CONFIG_CHARGE_RAMP_HW
-#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10
 #define CONFIG_CHARGER_PROFILE_OVERRIDE
 
 /* Keyboard features */
@@ -207,7 +206,7 @@
 
 #ifndef __ASSEMBLER__
 
-#include "gpio_signal.h"	/* needed by registers.h */
+#include "gpio_signal.h" /* needed by registers.h */
 #include "registers.h"
 #include "usbc_config.h"
 
@@ -236,35 +235,20 @@ enum sensor_id {
 	SENSOR_COUNT
 };
 
-enum ioex_port {
-	IOEX_C0_NCT38XX = 0,
-	IOEX_C1_NCT38XX,
-	IOEX_PORT_COUNT
-};
+enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_C1_NCT38XX, IOEX_PORT_COUNT };
 
-enum battery_type {
-	BATTERY_DYNAPACK_COS,
-	BATTERY_TYPE_COUNT
-};
+enum battery_type { BATTERY_DYNAPACK_COS, BATTERY_TYPE_COUNT };
 
 enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,		/* PWM3 */
-	PWM_CH_FAN,			/* PWM5 */
-	PWM_CH_FAN2,			/* PWM7 */
+	PWM_CH_KBLIGHT = 0, /* PWM3 */
+	PWM_CH_FAN, /* PWM5 */
+	PWM_CH_FAN2, /* PWM7 */
 	PWM_CH_COUNT
 };
 
-enum fan_channel {
-	FAN_CH_0 = 0,
-	FAN_CH_1,
-	FAN_CH_COUNT
-};
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_1, FAN_CH_COUNT };
 
-enum mft_channel {
-	MFT_CH_0 = 0,
-	MFT_CH_1,
-	MFT_CH_COUNT
-};
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_1, MFT_CH_COUNT };
 
 #ifdef CONFIG_KEYBOARD_FACTORY_TEST
 extern const int keyboard_factory_scan_pins[][2];
diff --git a/board/redrix/build.mk b/board/redrix/build.mk
index 7177a844ad..e021ebc4f4 100644
--- a/board/redrix/build.mk
+++ b/board/redrix/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/redrix/cbi_ssfc.c b/board/redrix/cbi_ssfc.c
index 364b3d96fe..e0e954a7a6 100644
--- a/board/redrix/cbi_ssfc.c
+++ b/board/redrix/cbi_ssfc.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/redrix/cbi_ssfc.h b/board/redrix/cbi_ssfc.h
index ddcfbb9281..724daa3782 100644
--- a/board/redrix/cbi_ssfc.h
+++ b/board/redrix/cbi_ssfc.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/redrix/charger.c b/board/redrix/charger.c
index 476ce97df2..a4fa209246 120000..100644
--- a/board/redrix/charger.c
+++ b/board/redrix/charger.c
@@ -1 +1,90 @@
-../../baseboard/brya/charger_bq25720.c
\ No newline at end of file
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+
+#include "charge_manager.h"
+#include "charge_state_v2.h"
+#include "charger.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/charger/bq25710.h"
+#include "usbc_ppc.h"
+#include "usb_pd.h"
+#include "util.h"
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+#ifndef CONFIG_ZEPHYR
+/* Charger Chip Configuration */
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = BQ25710_SMBUS_ADDR1_FLAGS,
+		.drv = &bq25710_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CHARGER_NUM);
+#endif
+
+int board_set_active_charge_port(int port)
+{
+	int is_valid_port = board_is_usb_pd_port_present(port);
+	int i;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTSUSB("Disabling all charger ports");
+
+		/* Disable all ports. */
+		for (i = 0; i < ppc_cnt; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (ppc_vbus_sink_enable(i, 0))
+				CPRINTSUSB("Disabling C%d as sink failed.", i);
+		}
+
+		return EC_SUCCESS;
+	} else if (!is_valid_port) {
+		return EC_ERROR_INVAL;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (ppc_is_sourcing_vbus(port)) {
+		CPRINTFUSB("Skip enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTSUSB("New charge port: C%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < ppc_cnt; i++) {
+		if (i == port)
+			continue;
+
+		if (ppc_vbus_sink_enable(i, 0))
+			CPRINTSUSB("C%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTSUSB("C%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+__overridable void board_set_charge_limit(int port, int supplier, int charge_ma,
+					  int max_ma, int charge_mv)
+{
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+}
diff --git a/board/redrix/ec.tasklist b/board/redrix/ec.tasklist
index cfc1fea6ea..f755b40858 100644
--- a/board/redrix/ec.tasklist
+++ b/board/redrix/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/redrix/fans.c b/board/redrix/fans.c
index d464eeab67..9adf3cabce 100644
--- a/board/redrix/fans.c
+++ b/board/redrix/fans.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -30,14 +30,14 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 static const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
 
 static const struct fan_conf fan_conf_1 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_1,	/* Use MFT id to control fan */
+	.ch = MFT_CH_1, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN2,
 };
diff --git a/board/redrix/fw_config.c b/board/redrix/fw_config.c
index e59688b17d..cfbf46291c 100644
--- a/board/redrix/fw_config.c
+++ b/board/redrix/fw_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,7 +9,7 @@
 #include "cros_board_info.h"
 #include "fw_config.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 static union redrix_cbi_fw_config fw_config;
 BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
diff --git a/board/redrix/fw_config.h b/board/redrix/fw_config.h
index 9a73890f7d..02157bf23e 100644
--- a/board/redrix/fw_config.h
+++ b/board/redrix/fw_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,20 +19,17 @@ enum ec_cfg_keyboard_backlight_type {
 	KEYBOARD_BACKLIGHT_ENABLED = 1
 };
 
-enum ec_cfg_eps_type {
-	EPS_DISABLED = 0,
-	EPS_ENABLED = 1
-};
+enum ec_cfg_eps_type { EPS_DISABLED = 0, EPS_ENABLED = 1 };
 
 union redrix_cbi_fw_config {
 	struct {
-		uint32_t				sd_db : 2;
-		enum ec_cfg_keyboard_backlight_type	kb_bl : 1;
-		uint32_t				audio : 3;
-		uint32_t				lte_db : 2;
-		uint32_t				ufc : 2;
-		enum ec_cfg_eps_type			eps : 1;
-		uint32_t				reserved_1 : 21;
+		uint32_t sd_db : 2;
+		enum ec_cfg_keyboard_backlight_type kb_bl : 1;
+		uint32_t audio : 3;
+		uint32_t lte_db : 2;
+		uint32_t ufc : 2;
+		enum ec_cfg_eps_type eps : 1;
+		uint32_t reserved_1 : 21;
 	};
 	uint32_t raw_value;
 };
diff --git a/board/redrix/gpio.inc b/board/redrix/gpio.inc
index 99f5237003..0f39efe33b 100644
--- a/board/redrix/gpio.inc
+++ b/board/redrix/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/redrix/i2c.c b/board/redrix/i2c.c
index 5b71c4eb71..0d6f92ad90 100644
--- a/board/redrix/i2c.c
+++ b/board/redrix/i2c.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/redrix/keyboard.c b/board/redrix/keyboard.c
index e1a5381a6c..11cfaaa02d 100644
--- a/board/redrix/keyboard.c
+++ b/board/redrix/keyboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -74,7 +74,6 @@ board_vivaldi_keybd_config(void)
 		return &keybd2;
 }
 
-
 #ifdef CONFIG_KEYBOARD_FACTORY_TEST
 /*
  * Map keyboard connector pins to EC GPIO pins for factory test.
@@ -82,13 +81,13 @@ board_vivaldi_keybd_config(void)
  * The connector has 24 pins total, and there is no pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-		{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-		{0, 7}, {1, 4}, {1, 3}, {1, 6}, {1, 7},
-		{3, 1}, {2, 0}, {1, 5}, {2, 6}, {2, 7},
-		{2, 1}, {2, 4}, {2, 5}, {1, 2}, {2, 3},
-		{2, 2}, {3, 0}, {-1, -1}, {-1, -1}, {-1, -1},
+	{ -1, -1 }, { 0, 5 }, { 1, 1 },	  { 1, 0 },   { 0, 6 },
+	{ 0, 7 },   { 1, 4 }, { 1, 3 },	  { 1, 6 },   { 1, 7 },
+	{ 3, 1 },   { 2, 0 }, { 1, 5 },	  { 2, 6 },   { 2, 7 },
+	{ 2, 1 },   { 2, 4 }, { 2, 5 },	  { 1, 2 },   { 2, 3 },
+	{ 2, 2 },   { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 },
 };
 
 const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 #endif
diff --git a/board/redrix/led.c b/board/redrix/led.c
index 86e60b725a..c8654b3589 100644
--- a/board/redrix/led.c
+++ b/board/redrix/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -24,16 +24,14 @@
 #define POWER_LED_OFF 1
 
 #define LED_TICK_INTERVAL_MS (500 * MSEC)
-#define LED_CYCLE_TIME_MS    (2000 * MSEC)
-#define LED_TICKS_PER_CYCLE  (LED_CYCLE_TIME_MS / LED_TICK_INTERVAL_MS)
-#define LED_ON_TIME_MS       (1000 * MSEC)
-#define LED_ON_TICKS         (LED_ON_TIME_MS / LED_TICK_INTERVAL_MS)
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_LEFT_LED,
-	EC_LED_ID_RIGHT_LED,
-	EC_LED_ID_POWER_LED
-};
+#define LED_CYCLE_TIME_MS (2000 * MSEC)
+#define LED_TICKS_PER_CYCLE (LED_CYCLE_TIME_MS / LED_TICK_INTERVAL_MS)
+#define LED_ON_TIME_MS (1000 * MSEC)
+#define LED_ON_TICKS (LED_ON_TIME_MS / LED_TICK_INTERVAL_MS)
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_LEFT_LED,
+					     EC_LED_ID_RIGHT_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -41,22 +39,19 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
-enum led_port {
-	LEFT_PORT = 0,
-	RIGHT_PORT
-};
+enum led_port { LEFT_PORT = 0, RIGHT_PORT };
 
 static void led_set_color_battery(int port, enum led_color color)
 {
 	enum gpio_signal amber_led, white_led;
 
 	amber_led = (port == RIGHT_PORT ? GPIO_C1_CHARGE_LED_AMBER_L :
-				 GPIO_C0_CHARGE_LED_AMBER_L);
+					  GPIO_C0_CHARGE_LED_AMBER_L);
 	white_led = (port == RIGHT_PORT ? GPIO_C1_CHARGE_LED_WHITE_L :
-				 GPIO_C0_CHARGE_LED_WHITE_L);
+					  GPIO_C0_CHARGE_LED_WHITE_L);
 
 	switch (color) {
 	case LED_WHITE:
@@ -151,16 +146,15 @@ static void set_active_port_color(enum led_color color)
 
 	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
 		led_set_color_battery(RIGHT_PORT,
-				(port == RIGHT_PORT) ? color : LED_OFF);
+				      (port == RIGHT_PORT) ? color : LED_OFF);
 	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
 		led_set_color_battery(LEFT_PORT,
-				(port == LEFT_PORT) ? color : LED_OFF);
+				      (port == LEFT_PORT) ? color : LED_OFF);
 }
 
 static void led_set_battery(void)
 {
 	static unsigned int battery_ticks;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
@@ -172,43 +166,52 @@ static void led_set_battery(void)
 	case PWR_STATE_DISCHARGE:
 		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
 			if (charge_get_percent() < 10)
-				led_set_color_battery(RIGHT_PORT,
-					(battery_ticks % LED_TICKS_PER_CYCLE
-					 < LED_ON_TICKS) ? LED_AMBER : LED_OFF);
+				led_set_color_battery(
+					RIGHT_PORT,
+					(battery_ticks % LED_TICKS_PER_CYCLE <
+					 LED_ON_TICKS) ?
+						LED_AMBER :
+						LED_OFF);
 			else
 				led_set_color_battery(RIGHT_PORT, LED_OFF);
 		}
 
 		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) {
 			if (charge_get_percent() < 10)
-				led_set_color_battery(LEFT_PORT,
-					(battery_ticks % LED_TICKS_PER_CYCLE
-					 < LED_ON_TICKS) ? LED_AMBER : LED_OFF);
+				led_set_color_battery(
+					LEFT_PORT,
+					(battery_ticks % LED_TICKS_PER_CYCLE <
+					 LED_ON_TICKS) ?
+						LED_AMBER :
+						LED_OFF);
 			else
 				led_set_color_battery(LEFT_PORT, LED_OFF);
 		}
 		break;
 	case PWR_STATE_ERROR:
 		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
-			led_set_color_battery(RIGHT_PORT, (battery_ticks & 0x1)
-				? LED_AMBER : LED_OFF);
+			led_set_color_battery(
+				RIGHT_PORT,
+				(battery_ticks & 0x1) ? LED_AMBER : LED_OFF);
 		}
 
 		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) {
-			led_set_color_battery(LEFT_PORT, (battery_ticks & 0x1)
-				? LED_AMBER : LED_OFF);
+			led_set_color_battery(LEFT_PORT, (battery_ticks & 0x1) ?
+								 LED_AMBER :
+								 LED_OFF);
 		}
 		break;
 	case PWR_STATE_CHARGE_NEAR_FULL:
 		set_active_port_color(LED_WHITE);
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			set_active_port_color((battery_ticks %
-				LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-				LED_AMBER : LED_OFF);
-		else
-			set_active_port_color(LED_WHITE);
+		set_active_port_color(LED_WHITE);
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		set_active_port_color(
+			(battery_ticks % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
+				LED_AMBER :
+				LED_OFF);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
diff --git a/board/redrix/pwm.c b/board/redrix/pwm.c
index 8e3d9c4022..dac3991526 100644
--- a/board/redrix/pwm.c
+++ b/board/redrix/pwm.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/redrix/sensors.c b/board/redrix/sensors.c
index df0e94f518..db645e5942 100644
--- a/board/redrix/sensors.c
+++ b/board/redrix/sensors.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -57,17 +57,13 @@ static struct accelgyro_saved_data_t g_bma253_data;
 static struct accelgyro_saved_data_t g_bma422_data;
 static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
 
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, FLOAT_TO_FP(1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, FLOAT_TO_FP(1), 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
 
 /* TCS3400 private data */
 static struct als_drv_data_t g_tcs3400_data = {
@@ -118,7 +114,7 @@ static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
 			.cover_scale = ALS_CHANNEL_SCALE(1.6)
 		}
 	},
-	.calibration.irt = INT_TO_FP(0.41),
+	.calibration.irt = FLOAT_TO_FP(0.41),
 	.saturation.again = TCS_DEFAULT_AGAIN,
 	.saturation.atime = TCS_DEFAULT_ATIME,
 };
@@ -291,38 +287,30 @@ DECLARE_HOOK(HOOK_INIT, board_sensors_init, HOOK_PRIO_INIT_I2C + 1);
 
 /* Temperature sensor configuration */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1_DDR] = {
-		.name = "DDR",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_1_DDR
-	},
-	[TEMP_SENSOR_2_SOC] = {
-		.name = "SOC",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_2_SOC
-	},
-	[TEMP_SENSOR_3_CHARGER] = {
-		.name = "Charger",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_3_CHARGER
-	},
-	[TEMP_SENSOR_4_REGULATOR] = {
-		.name = "Regulator",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_4_REGULATOR
-	},
+	[TEMP_SENSOR_1_DDR] = { .name = "DDR",
+				.type = TEMP_SENSOR_TYPE_BOARD,
+				.read = get_temp_3v3_30k9_47k_4050b,
+				.idx = ADC_TEMP_SENSOR_1_DDR },
+	[TEMP_SENSOR_2_SOC] = { .name = "SOC",
+				.type = TEMP_SENSOR_TYPE_BOARD,
+				.read = get_temp_3v3_30k9_47k_4050b,
+				.idx = ADC_TEMP_SENSOR_2_SOC },
+	[TEMP_SENSOR_3_CHARGER] = { .name = "Charger",
+				    .type = TEMP_SENSOR_TYPE_BOARD,
+				    .read = get_temp_3v3_30k9_47k_4050b,
+				    .idx = ADC_TEMP_SENSOR_3_CHARGER },
+	[TEMP_SENSOR_4_REGULATOR] = { .name = "Regulator",
+				      .type = TEMP_SENSOR_TYPE_BOARD,
+				      .read = get_temp_3v3_30k9_47k_4050b,
+				      .idx = ADC_TEMP_SENSOR_4_REGULATOR },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_DDR \
-	{ \
+#define THERMAL_DDR              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
@@ -341,8 +329,8 @@ __maybe_unused static const struct ec_thermal_config thermal_ddr = THERMAL_DDR;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CPU \
-	{ \
+#define THERMAL_CPU              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
@@ -356,8 +344,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CHARGER \
-	{ \
+#define THERMAL_CHARGER          \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(80), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(85), \
@@ -372,8 +360,8 @@ __maybe_unused static const struct ec_thermal_config thermal_charger =
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_REGULATOR \
-	{ \
+#define THERMAL_REGULATOR        \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(80), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(85), \
diff --git a/board/redrix/thermal.c b/board/redrix/thermal.c
index 71902a5430..e192157943 100644
--- a/board/redrix/thermal.c
+++ b/board/redrix/thermal.c
@@ -1,8 +1,9 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "builtin/assert.h"
 #include "chipset.h"
 #include "common.h"
 #include "console.h"
@@ -16,7 +17,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_THERMAL, outstr)
-#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
 
 struct fan_step {
 	/*
@@ -40,97 +41,96 @@ static const struct fan_step *fan_step_table;
 static const struct fan_step fan_table_clamshell[] = {
 	{
 		/* level 0 */
-		.on = {53, 53, 0, -1},
-		.off = {99, 99, 99, -1},
-		.rpm = {0, 0},
+		.on = { 53, 53, 0, -1 },
+		.off = { 99, 99, 99, -1 },
+		.rpm = { 0, 0 },
 	},
 	{
 		/* level 1 */
-		.on = {54, 54, 0, -1},
-		.off = {53, 53, 99, -1},
-		.rpm = {3900, 4300},
+		.on = { 54, 54, 0, -1 },
+		.off = { 53, 53, 99, -1 },
+		.rpm = { 3900, 4300 },
 	},
 	{
 		/* level 2 */
-		.on = {55, 55, 0, -1},
-		.off = {54, 54, 99, -1},
-		.rpm = {4800, 5200},
+		.on = { 55, 55, 0, -1 },
+		.off = { 54, 54, 99, -1 },
+		.rpm = { 4800, 5200 },
 	},
 	{
 		/* level 3 */
-		.on = {56, 56, 0, -1},
-		.off = {54, 55, 99, -1},
-		.rpm = {5000, 5500},
+		.on = { 56, 56, 0, -1 },
+		.off = { 54, 55, 99, -1 },
+		.rpm = { 5000, 5500 },
 	},
 	{
 		/* level 4 */
-		.on = {57, 57, 61, -1},
-		.off = {56, 56, 59, -1},
-		.rpm = {5200, 5700},
+		.on = { 57, 57, 61, -1 },
+		.off = { 56, 56, 59, -1 },
+		.rpm = { 5200, 5700 },
 	},
 	{
 		/* level 5 */
-		.on = {58, 58, 63, -1},
-		.off = {57, 57, 61, -1},
-		.rpm = {5700, 6200},
+		.on = { 58, 58, 63, -1 },
+		.off = { 57, 57, 61, -1 },
+		.rpm = { 5700, 6200 },
 	},
 	{
 		/* level 6 */
-		.on = {100, 100, 100, -1},
-		.off = {58, 58, 63, -1},
-		.rpm = {6200, 6400},
+		.on = { 100, 100, 100, -1 },
+		.off = { 58, 58, 63, -1 },
+		.rpm = { 6200, 6400 },
 	},
 };
 
 static const struct fan_step fan_table_tablet[] = {
 	{
 		/* level 0 */
-		.on = {52, 55, 0, -1},
-		.off = {99, 99, 99, -1},
-		.rpm = {0, 0},
+		.on = { 52, 55, 0, -1 },
+		.off = { 99, 99, 99, -1 },
+		.rpm = { 0, 0 },
 	},
 	{
 		/* level 1 */
-		.on = {53, 56, 0, -1},
-		.off = {52, 55, 99, -1},
-		.rpm = {4100, 4200},
+		.on = { 53, 56, 0, -1 },
+		.off = { 52, 55, 99, -1 },
+		.rpm = { 4100, 4200 },
 	},
 	{
 		/* level 2 */
-		.on = {54, 57, 0, -1},
-		.off = {53, 56, 99, -1},
-		.rpm = {4500, 4800},
+		.on = { 54, 57, 0, -1 },
+		.off = { 53, 56, 99, -1 },
+		.rpm = { 4500, 4800 },
 	},
 	{
 		/* level 3 */
-		.on = {55, 58, 0, -1},
-		.off = {54, 57, 99, -1},
-		.rpm = {4800, 5200},
+		.on = { 55, 58, 0, -1 },
+		.off = { 54, 57, 99, -1 },
+		.rpm = { 4800, 5200 },
 	},
 	{
 		/* level 4 */
-		.on = {56, 59, 61, -1},
-		.off = {55, 58, 59, -1},
-		.rpm = {5100, 5400},
+		.on = { 56, 59, 61, -1 },
+		.off = { 55, 58, 59, -1 },
+		.rpm = { 5100, 5400 },
 	},
 	{
 		/* level 5 */
-		.on = {57, 60, 63, -1},
-		.off = {56, 59, 61, -1},
-		.rpm = {5500, 5800},
+		.on = { 57, 60, 63, -1 },
+		.off = { 56, 59, 61, -1 },
+		.rpm = { 5500, 5800 },
 	},
 	{
 		/* level 6 */
-		.on = {100, 100, 100, -1},
-		.off = {57, 60, 63, -1},
-		.rpm = {6000, 6200},
+		.on = { 100, 100, 100, -1 },
+		.off = { 57, 60, 63, -1 },
+		.rpm = { 6000, 6200 },
 	},
 };
 
 #define NUM_FAN_LEVELS ARRAY_SIZE(fan_table_clamshell)
 
-BUILD_ASSERT(ARRAY_SIZE(fan_table_clamshell) ==
-	ARRAY_SIZE(fan_table_tablet));
+BUILD_ASSERT(ARRAY_SIZE(fan_table_clamshell) == ARRAY_SIZE(fan_table_tablet));
 
 int fan_table_to_rpm(int fan, int *temp)
 {
@@ -156,11 +156,12 @@ int fan_table_to_rpm(int fan, int *temp)
 	    temp[TEMP_SENSOR_3_CHARGER] < prev_tmp[TEMP_SENSOR_3_CHARGER]) {
 		for (i = current_level; i > 0; i--) {
 			if (temp[TEMP_SENSOR_1_DDR] <
-				fan_step_table[i].off[TEMP_SENSOR_1_DDR] &&
+				    fan_step_table[i].off[TEMP_SENSOR_1_DDR] &&
 			    temp[TEMP_SENSOR_3_CHARGER] <
-				fan_step_table[i].off[TEMP_SENSOR_3_CHARGER] &&
+				    fan_step_table[i]
+					    .off[TEMP_SENSOR_3_CHARGER] &&
 			    temp[TEMP_SENSOR_2_SOC] <
-				fan_step_table[i].off[TEMP_SENSOR_2_SOC])
+				    fan_step_table[i].off[TEMP_SENSOR_2_SOC])
 				current_level = i - 1;
 			else
 				break;
@@ -168,14 +169,15 @@ int fan_table_to_rpm(int fan, int *temp)
 	} else if (temp[TEMP_SENSOR_1_DDR] > prev_tmp[TEMP_SENSOR_1_DDR] ||
 		   temp[TEMP_SENSOR_2_SOC] > prev_tmp[TEMP_SENSOR_2_SOC] ||
 		   temp[TEMP_SENSOR_3_CHARGER] >
-			prev_tmp[TEMP_SENSOR_3_CHARGER]) {
+			   prev_tmp[TEMP_SENSOR_3_CHARGER]) {
 		for (i = current_level; i < NUM_FAN_LEVELS; i++) {
 			if ((temp[TEMP_SENSOR_1_DDR] >
-				fan_step_table[i].on[TEMP_SENSOR_1_DDR] &&
-			    temp[TEMP_SENSOR_3_CHARGER] >
-				fan_step_table[i].on[TEMP_SENSOR_3_CHARGER]) ||
+				     fan_step_table[i].on[TEMP_SENSOR_1_DDR] &&
+			     temp[TEMP_SENSOR_3_CHARGER] >
+				     fan_step_table[i]
+					     .on[TEMP_SENSOR_3_CHARGER]) ||
 			    temp[TEMP_SENSOR_2_SOC] >
-				fan_step_table[i].on[TEMP_SENSOR_2_SOC])
+				    fan_step_table[i].on[TEMP_SENSOR_2_SOC])
 				current_level = i + 1;
 			else
 				break;
@@ -206,10 +208,8 @@ int fan_table_to_rpm(int fan, int *temp)
 
 void board_override_fan_control(int fan, int *tmp)
 {
-	if (chipset_in_state(CHIPSET_STATE_ON |
-		CHIPSET_STATE_ANY_SUSPEND)) {
+	if (chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND)) {
 		fan_set_rpm_mode(FAN_CH(fan), 1);
-		fan_set_rpm_target(FAN_CH(fan),
-			fan_table_to_rpm(fan, tmp));
+		fan_set_rpm_target(FAN_CH(fan), fan_table_to_rpm(fan, tmp));
 	}
 }
diff --git a/board/redrix/usbc_config.c b/board/redrix/usbc_config.c
index e463c15da1..a53e2c8909 100644
--- a/board/redrix/usbc_config.c
+++ b/board/redrix/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -31,8 +31,8 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 /* USBC TCPC configuration */
 const struct tcpc_config_t tcpc_config[] = {
@@ -78,33 +78,43 @@ BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
 /* USBC mux configuration - Alder Lake includes internal mux */
-static const struct usb_mux usbc0_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+static const struct usb_mux_chain usbc0_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
-static const struct usb_mux usbc1_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+static const struct usb_mux_chain usbc1_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
 
-const struct usb_mux usb_muxes[] = {
+const struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C0_MUX,
-		.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc0_tcss_usb_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C0_MUX,
+			.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc0_tcss_usb_mux,
 	},
 	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C1_MUX,
-		.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc1_tcss_usb_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C1_MUX,
+			.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc1_tcss_usb_mux,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
diff --git a/board/redrix/usbc_config.h b/board/redrix/usbc_config.h
index dcaa52d7a9..248e697572 100644
--- a/board/redrix/usbc_config.h
+++ b/board/redrix/usbc_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,12 +8,8 @@
 #ifndef __CROS_EC_USBC_CONFIG_H
 #define __CROS_EC_USBC_CONFIG_H
 
-#define CONFIG_USB_PD_PORT_MAX_COUNT	2
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 #endif /* __CROS_EC_USBC_CONFIG_H */
diff --git a/board/reef/battery.c b/board/reef/battery.c
index 83a3679b26..52ec2a0471 100644
--- a/board/reef/battery.c
+++ b/board/reef/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -20,7 +20,7 @@
 #include "i2c.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 enum battery_type {
 	BATTERY_SONY_CORP,
@@ -135,7 +135,7 @@ const struct battery_info batt_info_smp_cos4870 = {
 	 * unwanted low VSYS_Prochot# assertion can be avoided.
 	 */
 	.voltage_min = 6100,
-	.precharge_current = 256,	/* mA */
+	.precharge_current = 256, /* mA */
 	.start_charging_min_c = 0,
 	.start_charging_max_c = 46,
 	.charging_min_c = 0,
@@ -183,7 +183,7 @@ const struct battery_info batt_info_sonycorp = {
 	 * unwanted low VSYS_Prochot# assertion can be avoided.
 	 */
 	.voltage_min = 6100,
-	.precharge_current = 256,	/* mA */
+	.precharge_current = 256, /* mA */
 	.start_charging_min_c = 0,
 	.start_charging_max_c = 50,
 	.charging_min_c = 0,
@@ -240,7 +240,7 @@ const struct battery_info batt_info_panasoic = {
 	 * unwanted low VSYS_Prochot# assertion can be avoided.
 	 */
 	.voltage_min = 6100,
-	.precharge_current = 256,	/* mA */
+	.precharge_current = 256, /* mA */
 	.start_charging_min_c = 0,
 	.start_charging_max_c = 50,
 	.charging_min_c = 0,
@@ -384,7 +384,7 @@ const struct battery_info batt_info_c22n1626 = {
 	 * unwanted low VSYS_Prochot# assertion can be avoided.
 	 */
 	.voltage_min = 6100,
-	.precharge_current = 256,	/* mA */
+	.precharge_current = 256, /* mA */
 	.start_charging_min_c = 0,
 	.start_charging_max_c = 45,
 	.charging_min_c = 0,
@@ -398,7 +398,7 @@ static int batt_smp_cos4870_init(void)
 	int batt_status;
 
 	return battery_status(&batt_status) ? 0 :
-		batt_status & STATUS_INITIALIZED;
+					      batt_status & STATUS_INITIALIZED;
 }
 
 static int batt_sony_corp_init(void)
@@ -411,8 +411,9 @@ static int batt_sony_corp_init(void)
 	 *      : 0b - Allowed to Discharge
 	 *      : 1b - Not Allowed to Discharge
 	 */
-	return sb_read(SB_MANUFACTURER_ACCESS, &batt_status) ? 0 :
-		!(batt_status & SONY_DISCHARGE_DISABLE_FET_BIT);
+	return sb_read(SB_MANUFACTURER_ACCESS, &batt_status) ?
+		       0 :
+		       !(batt_status & SONY_DISCHARGE_DISABLE_FET_BIT);
 }
 
 static int batt_panasonic_init(void)
@@ -425,8 +426,9 @@ static int batt_panasonic_init(void)
 	 *      : 0b - Not Allowed to Discharge
 	 *      : 1b - Allowed to Discharge
 	 */
-	return sb_read(SB_MANUFACTURER_ACCESS, &batt_status) ? 0 :
-		!!(batt_status & PANASONIC_DISCHARGE_ENABLE_FET_BIT);
+	return sb_read(SB_MANUFACTURER_ACCESS, &batt_status) ?
+		       0 :
+		       !!(batt_status & PANASONIC_DISCHARGE_ENABLE_FET_BIT);
 }
 
 static int batt_c22n1626_init(void)
@@ -439,8 +441,9 @@ static int batt_c22n1626_init(void)
 	 *      : 0b - Not Allowed to Discharge
 	 *      : 1b - Allowed to Discharge
 	 */
-	return sb_read(SB_PACK_STATUS, &batt_status) ? 0 :
-		!!(batt_status & C22N1626_DISCHARGE_ENABLE_FET_BIT);
+	return sb_read(SB_PACK_STATUS, &batt_status) ?
+		       0 :
+		       !!(batt_status & C22N1626_DISCHARGE_ENABLE_FET_BIT);
 }
 
 static const struct ship_mode_info ship_mode_info_smp_cos4870 = {
@@ -461,7 +464,7 @@ static const struct ship_mode_info ship_mode_info_panasonic = {
 	.batt_init = batt_panasonic_init,
 };
 
-static const struct ship_mode_info ship_mode_info_c22n1626= {
+static const struct ship_mode_info ship_mode_info_c22n1626 = {
 	.ship_mode_reg = 0x00,
 	.ship_mode_data = 0x0010,
 	.batt_init = batt_c22n1626_init,
@@ -513,7 +516,8 @@ BUILD_ASSERT(ARRAY_SIZE(info) == BATTERY_TYPE_COUNT);
 static inline const struct board_batt_params *board_get_batt_params(void)
 {
 	return &info[board_battery_type == BATTERY_TYPE_COUNT ?
-			DEFAULT_BATTERY_TYPE : board_battery_type];
+			     DEFAULT_BATTERY_TYPE :
+			     board_battery_type];
 }
 
 enum battery_present battery_hw_present(void)
@@ -540,8 +544,9 @@ static int board_get_battery_type(void)
 
 	/* Initialize fast charging parameters */
 	chg_params = board_get_batt_params()->fast_chg_params;
-	prev_chg_profile_info = &chg_params->chg_profile_info[
-					chg_params->default_temp_range_profile];
+	prev_chg_profile_info =
+		&chg_params->chg_profile_info
+			 [chg_params->default_temp_range_profile];
 
 	return board_battery_type;
 }
@@ -571,11 +576,11 @@ int board_cut_off_battery(void)
 {
 	int rv;
 	const struct ship_mode_info *ship_mode_inf =
-				board_get_batt_params()->ship_mode_inf;
+		board_get_batt_params()->ship_mode_inf;
 
 	/* Ship mode command must be sent twice to take effect */
 	rv = sb_write(ship_mode_inf->ship_mode_reg,
-			ship_mode_inf->ship_mode_data);
+		      ship_mode_inf->ship_mode_data);
 	if (rv != EC_SUCCESS)
 		return rv;
 
@@ -591,7 +596,7 @@ static int charger_should_discharge_on_ac(struct charge_state_data *curr)
 
 	/* Do not discharge on AC if the battery is still waking up */
 	if (!(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
-		!(curr->batt.status & STATUS_FULLY_CHARGED))
+	    !(curr->batt.status & STATUS_FULLY_CHARGED))
 		return 0;
 
 	/*
@@ -608,8 +613,8 @@ static int charger_should_discharge_on_ac(struct charge_state_data *curr)
 	 * and suspend USB charging and DC/DC converter.
 	 */
 	if (!battery_is_cut_off() &&
-		!(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
-		(curr->batt.status & STATUS_FULLY_CHARGED))
+	    !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
+	    (curr->batt.status & STATUS_FULLY_CHARGED))
 		return 1;
 
 	/*
@@ -642,10 +647,10 @@ int charger_profile_override(struct charge_state_data *curr)
 		return 0;
 	}
 
-	return charger_profile_override_common(curr,
-			board_get_batt_params()->fast_chg_params,
-			&prev_chg_profile_info,
-			board_get_batt_params()->batt_info->voltage_max);
+	return charger_profile_override_common(
+		curr, board_get_batt_params()->fast_chg_params,
+		&prev_chg_profile_info,
+		board_get_batt_params()->batt_info->voltage_max);
 }
 
 /*
@@ -671,7 +676,7 @@ enum battery_present battery_is_present(void)
 	 * Battery status will be inactive until it is initialized.
 	 */
 	if (batt_pres == BP_YES && batt_pres_prev != batt_pres &&
-		!battery_is_cut_off()) {
+	    !battery_is_cut_off()) {
 		/* Re-init board battery if battery presence status changes */
 		if (board_get_battery_type() == BATTERY_TYPE_COUNT) {
 			if (bd9995x_get_battery_voltage() >=
diff --git a/board/reef/board.c b/board/reef/board.c
index e224169f3b..5e608ee4ee 100644
--- a/board/reef/board.c
+++ b/board/reef/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -34,6 +34,7 @@
 #include "math_util.h"
 #include "motion_sense.h"
 #include "motion_lid.h"
+#include "panic.h"
 #include "power.h"
 #include "power_button.h"
 #include "pwm.h"
@@ -53,15 +54,15 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define IN_ALL_SYS_PG	POWER_SIGNAL_MASK(X86_ALL_SYS_PG)
-#define IN_PGOOD_PP3300	POWER_SIGNAL_MASK(X86_PGOOD_PP3300)
-#define IN_PGOOD_PP5000	POWER_SIGNAL_MASK(X86_PGOOD_PP5000)
+#define IN_ALL_SYS_PG POWER_SIGNAL_MASK(X86_ALL_SYS_PG)
+#define IN_PGOOD_PP3300 POWER_SIGNAL_MASK(X86_PGOOD_PP3300)
+#define IN_PGOOD_PP5000 POWER_SIGNAL_MASK(X86_PGOOD_PP5000)
 
-#define USB_PD_PORT_ANX74XX	0
-#define USB_PD_PORT_PS8751	1
+#define USB_PD_PORT_ANX74XX 0
+#define USB_PD_PORT_PS8751 1
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
@@ -126,61 +127,48 @@ void tablet_mode_interrupt(enum gpio_signal signal)
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* Vfs = Vref = 2.816V, 10-bit unsigned reading */
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0
-	},
-	[ADC_TEMP_SENSOR_AMB] = {
-		"AMBIENT", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0
-	},
-	[ADC_BOARD_ID] = {
-		"BRD_ID", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0
-	},
+	[ADC_TEMP_SENSOR_CHARGER] = { "CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				      ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_AMB] = { "AMBIENT", NPCX_ADC_CH1, ADC_MAX_VOLT,
+				  ADC_READ_MAX + 1, 0 },
+	[ADC_BOARD_ID] = { "BRD_ID", NPCX_ADC_CH2, ADC_MAX_VOLT,
+			   ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
 	[PWM_CH_LED_GREEN] = { 2, PWM_CONFIG_DSLEEP, 100 },
-	[PWM_CH_LED_RED] =   { 3, PWM_CONFIG_DSLEEP, 100 },
+	[PWM_CH_LED_RED] = { 3, PWM_CONFIG_DSLEEP, 100 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
-const struct i2c_port_t i2c_ports[]  = {
-	{
-		.name = "tcpc0",
-		.port = NPCX_I2C_PORT0_0,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_USB_C0_PD_SCL,
-		.sda  = GPIO_EC_I2C_USB_C0_PD_SDA
-	},
-	{
-		.name = "tcpc1",
-		.port = NPCX_I2C_PORT0_1,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_USB_C1_PD_SCL,
-		.sda  = GPIO_EC_I2C_USB_C1_PD_SDA
-	},
-	{
-		.name = "accelgyro",
-		.port = I2C_PORT_GYRO,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_GYRO_SCL,
-		.sda  = GPIO_EC_I2C_GYRO_SDA
-	},
-	{
-		.name = "sensors",
-		.port = NPCX_I2C_PORT2,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_SENSOR_SCL,
-		.sda  = GPIO_EC_I2C_SENSOR_SDA
-	},
-	{
-		.name = "batt",
-		.port = NPCX_I2C_PORT3,
-		.kbps = 100,
-		.scl  = GPIO_EC_I2C_POWER_SCL,
-		.sda  = GPIO_EC_I2C_POWER_SDA
-	},
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "tcpc0",
+	  .port = NPCX_I2C_PORT0_0,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_USB_C0_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C0_PD_SDA },
+	{ .name = "tcpc1",
+	  .port = NPCX_I2C_PORT0_1,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_USB_C1_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C1_PD_SDA },
+	{ .name = "accelgyro",
+	  .port = I2C_PORT_GYRO,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_GYRO_SCL,
+	  .sda = GPIO_EC_I2C_GYRO_SDA },
+	{ .name = "sensors",
+	  .port = NPCX_I2C_PORT2,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_SENSOR_SCL,
+	  .sda = GPIO_EC_I2C_SENSOR_SDA },
+	{ .name = "batt",
+	  .port = NPCX_I2C_PORT3,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_POWER_SCL,
+	  .sda = GPIO_EC_I2C_POWER_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -308,17 +296,21 @@ static int ps8751_tune_mux(const struct usb_mux *me)
 	return EC_SUCCESS;
 }
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_ANX74XX] = {
-		.usb_port = USB_PD_PORT_ANX74XX,
-		.driver = &anx74xx_tcpm_usb_mux_driver,
-		.hpd_update = &anx74xx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_ANX74XX,
+			.driver = &anx74xx_tcpm_usb_mux_driver,
+			.hpd_update = &anx74xx_tcpc_update_hpd_status,
+		},
 	},
 	[USB_PD_PORT_PS8751] = {
-		.usb_port = USB_PD_PORT_PS8751,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-		.board_init = &ps8751_tune_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_PS8751,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			.board_init = &ps8751_tune_mux,
+		},
 	}
 };
 
@@ -413,28 +405,28 @@ void board_tcpc_init(void)
 	gpio_enable_interrupt(GPIO_USB_C0_CABLE_DET);
 #endif
 	/*
-	* Initialize HPD to low; after sysjump SOC needs to see
-	* HPD pulse to enable video path
-	*/
+	 * Initialize HPD to low; after sysjump SOC needs to see
+	 * HPD pulse to enable video path
+	 */
 	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
 		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp,
-				 .idx = 0},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
+	[TEMP_SENSOR_BATTERY] = { .name = "Battery",
+				  .type = TEMP_SENSOR_TYPE_BATTERY,
+				  .read = charge_get_battery_temp,
+				  .idx = 0 },
+	[TEMP_SENSOR_AMBIENT] = { .name = "Ambient",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_51k1_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_AMB },
+	[TEMP_SENSOR_CHARGER] = { .name = "Charger",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_13k7_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_CHARGER },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -551,8 +543,8 @@ int board_set_active_charge_port(int charge_port)
  * @param charge_ma     Desired charge limit (mA).
  * @param charge_mv     Negotiated charge voltage (mV).
  */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	/* Enable charging trigger by BC1.2 detection */
 	int bc12_enable = (supplier == CHARGE_SUPPLIER_BC12_CDP ||
@@ -564,8 +556,8 @@ void board_set_charge_limit(int port, int supplier, int charge_ma,
 		return;
 
 	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-				   CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 /**
@@ -675,17 +667,17 @@ void board_hibernate_late(void)
 	int i;
 	const uint32_t hibernate_pins[][2] = {
 		/* Turn off LEDs in hibernate */
-		{GPIO_BAT_LED_BLUE, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_BAT_LED_AMBER, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_LID_OPEN, GPIO_INT_RISING | GPIO_PULL_DOWN},
+		{ GPIO_BAT_LED_BLUE, GPIO_INPUT | GPIO_PULL_UP },
+		{ GPIO_BAT_LED_AMBER, GPIO_INPUT | GPIO_PULL_UP },
+		{ GPIO_LID_OPEN, GPIO_INT_RISING | GPIO_PULL_DOWN },
 
 		/*
 		 * BD99956 handles charge input automatically. We'll disable
 		 * charge output in hibernate. Charger will assert ACOK_OD
 		 * when VBUS or VCC are plugged in.
 		 */
-		{GPIO_USB_C0_5V_EN,       GPIO_INPUT  | GPIO_PULL_DOWN},
-		{GPIO_USB_C1_5V_EN,       GPIO_INPUT  | GPIO_PULL_DOWN},
+		{ GPIO_USB_C0_5V_EN, GPIO_INPUT | GPIO_PULL_DOWN },
+		{ GPIO_USB_C1_5V_EN, GPIO_INPUT | GPIO_PULL_DOWN },
 	};
 
 	/* Change GPIOs' state in hibernate for better power consumption */
@@ -712,17 +704,13 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0,  0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+				       { FLOAT_TO_FP(1), 0, 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
 
-const mat33_fp_t mag_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0,  FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t mag_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				      { 0, FLOAT_TO_FP(1), 0 },
+				      { 0, 0, FLOAT_TO_FP(-1) } };
 
 /* sensor private data */
 static struct kionix_accel_data g_kx022_data;
@@ -890,8 +878,8 @@ struct {
 	int thresh_mv;
 } const reef_board_versions[] = {
 	/* Vin = 3.3V, R1 = 46.4K, R2 values listed below */
-	{ BOARD_VERSION_1, 328 * 1.03 },  /* 5.11 Kohm */
-	{ BOARD_VERSION_2, 670 * 1.03 },  /* 11.8 Kohm */
+	{ BOARD_VERSION_1, 328 * 1.03 }, /* 5.11 Kohm */
+	{ BOARD_VERSION_2, 670 * 1.03 }, /* 11.8 Kohm */
 	{ BOARD_VERSION_3, 1012 * 1.03 }, /* 20.5 Kohm */
 	{ BOARD_VERSION_4, 1357 * 1.03 }, /* 32.4 Kohm */
 	{ BOARD_VERSION_5, 1690 * 1.03 }, /* 48.7 Kohm */
diff --git a/board/reef/board.h b/board/reef/board.h
index d4cc2ccad2..fc25024dff 100644
--- a/board/reef/board.h
+++ b/board/reef/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,24 +12,23 @@
  * By default, enable all console messages excepted HC, ACPI and event:
  * The sensor stack is generating a lot of activity.
  */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
 #undef CONFIG_HOSTCMD_DEBUG_MODE
 #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
 
-
 /* EC console commands  */
 #define CONFIG_CMD_ACCELS
 #define CONFIG_CMD_ACCEL_INFO
 #define CONFIG_CMD_BATT_MFG_ACCESS
 #define CONFIG_CMD_CHARGER_ADC_AMON_BMON
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 #define BD9995X_IOUT_GAIN_SELECT \
-		BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V
+	BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V
 
 #define CONFIG_CHARGER_PSYS_READ
 #define BD9995X_PSYS_GAIN_SELECT \
-		BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_02UAW
+	BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_02UAW
 
 #define CONFIG_CMD_I2C_STRESS_TEST
 #define CONFIG_CMD_I2C_STRESS_TEST_ACCEL
@@ -39,7 +38,7 @@
 #define CONFIG_CMD_I2C_STRESS_TEST_TCPC
 
 /* Battery */
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY  "LION"
+#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
 #define CONFIG_BATTERY_CUT_OFF
 #define CONFIG_BATTERY_PRESENT_CUSTOM
 #define CONFIG_BATTERY_SMART
@@ -60,7 +59,7 @@
 #define CONFIG_USB_CHARGER
 #define CONFIG_CHARGER_PROFILE_OVERRIDE
 #define CONFIG_CHARGER_PROFILE_OVERRIDE_COMMON
-#undef  CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES
+#undef CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES
 #define CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES 3
 #define CONFIG_CHARGE_MANAGER_EXTERNAL_POWER_LIMIT
 
@@ -87,7 +86,7 @@
 #define CONFIG_USB_PD_PORT_MAX_COUNT 2
 #define CONFIG_USB_PD_VBUS_DETECT_CHARGER
 #define CONFIG_USB_PD_TCPC_LOW_POWER
-#define CONFIG_USB_PD_TCPM_MUX  /* for both PS8751 and ANX3429 */
+#define CONFIG_USB_PD_TCPM_MUX /* for both PS8751 and ANX3429 */
 #define CONFIG_USB_PD_TCPM_ANX3429
 #define CONFIG_USB_PD_TCPM_PS8751
 #define CONFIG_USB_PD_TCPM_TCPCI
@@ -115,8 +114,8 @@
 /* EC */
 #define CONFIG_ADC
 #define CONFIG_EXTPOWER_GPIO
-#undef   CONFIG_EXTPOWER_DEBOUNCE_MS
-#define  CONFIG_EXTPOWER_DEBOUNCE_MS 1000
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
+#define CONFIG_EXTPOWER_DEBOUNCE_MS 1000
 #define CONFIG_FPU
 #define CONFIG_HOSTCMD_FLASH_SPI_INFO
 #define CONFIG_I2C
@@ -145,7 +144,7 @@
 #define CONFIG_WIRELESS
 #define CONFIG_WIRELESS_SUSPEND EC_WIRELESS_SWITCH_WLAN_POWER
 #define CONFIG_WLAN_POWER_ACTIVE_LOW
-#define  WIRELESS_GPIO_WLAN_POWER GPIO_WIRELESS_GPIO_WLAN_POWER
+#define WIRELESS_GPIO_WLAN_POWER GPIO_WIRELESS_GPIO_WLAN_POWER
 #define CONFIG_PWR_STATE_DISCHARGE_FULL
 #undef CONFIG_UART_TX_BUF_SIZE
 #define CONFIG_UART_TX_BUF_SIZE 512
@@ -165,7 +164,7 @@
 
 #define CONFIG_FLASH_SIZE_BYTES 524288
 #define CONFIG_SPI_FLASH_REGS
-#define CONFIG_SPI_FLASH_W25Q40	/* FIXME: Should be GD25LQ40? */
+#define CONFIG_SPI_FLASH_W25Q40 /* FIXME: Should be GD25LQ40? */
 
 /*
  * Enable 1 slot of secure temporary storage to support
@@ -175,21 +174,21 @@
 #define CONFIG_VSTORE_SLOT_COUNT 1
 
 /* Optional feature - used by nuvoton */
-#define NPCX_UART_MODULE2    1 /* 0:GPIO10/11 1:GPIO64/65 as UART */
-#define NPCX_JTAG_MODULE2    0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/
+#define NPCX_UART_MODULE2 1 /* 0:GPIO10/11 1:GPIO64/65 as UART */
+#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/
 /* FIXME(dhendrix): these pins are just normal GPIOs on Reef. Do we need
  * to change some other setting to put them in GPIO mode? */
-#define NPCX_TACH_SEL2       0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
+#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */
 
 /* I2C ports */
-#define I2C_PORT_GYRO			NPCX_I2C_PORT1
-#define I2C_PORT_LID_ACCEL		NPCX_I2C_PORT2
-#define I2C_PORT_ALS			NPCX_I2C_PORT2
-#define I2C_PORT_BARO			NPCX_I2C_PORT2
-#define I2C_PORT_BATTERY		NPCX_I2C_PORT3
-#define I2C_PORT_CHARGER		NPCX_I2C_PORT3
+#define I2C_PORT_GYRO NPCX_I2C_PORT1
+#define I2C_PORT_LID_ACCEL NPCX_I2C_PORT2
+#define I2C_PORT_ALS NPCX_I2C_PORT2
+#define I2C_PORT_BARO NPCX_I2C_PORT2
+#define I2C_PORT_BATTERY NPCX_I2C_PORT3
+#define I2C_PORT_CHARGER NPCX_I2C_PORT3
 /* Accelerometer and Gyroscope are the same device. */
-#define I2C_PORT_ACCEL			I2C_PORT_GYRO
+#define I2C_PORT_ACCEL I2C_PORT_GYRO
 
 /* Sensors */
 #define CONFIG_MKBP_EVENT
@@ -215,7 +214,6 @@
 /* Depends on how fast the AP boots and typical ODRs */
 #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
 
-
 #ifndef __ASSEMBLER__
 
 #include "gpio_signal.h"
@@ -223,9 +221,9 @@
 
 /* ADC signal */
 enum adc_channel {
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC0 */
-	ADC_TEMP_SENSOR_AMB,		/* ADC1 */
-	ADC_BOARD_ID,			/* ADC2 */
+	ADC_TEMP_SENSOR_CHARGER, /* ADC0 */
+	ADC_TEMP_SENSOR_AMB, /* ADC1 */
+	ADC_BOARD_ID, /* ADC2 */
 	ADC_CH_COUNT
 };
 
@@ -286,16 +284,16 @@ enum reef_board_version {
  * delay to turn on the power supply max is ~16ms.
  * delay to turn off the power supply max is about ~180ms.
  */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* delay to turn on/off vconn */
 
 /* Define typical operating power and max power */
 #define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       45000
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_VOLTAGE_MV     20000
+#define PD_MAX_POWER_MW 45000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Reset PD MCU */
 void board_reset_pd_mcu(void);
diff --git a/board/reef/build.mk b/board/reef/build.mk
index 728d027803..470e439b13 100644
--- a/board/reef/build.mk
+++ b/board/reef/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/reef/ec.tasklist b/board/reef/ec.tasklist
index eeebc0cc59..bc8668a1db 100644
--- a/board/reef/ec.tasklist
+++ b/board/reef/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/reef/gpio.inc b/board/reef/gpio.inc
index f508d7a84e..5693274284 100644
--- a/board/reef/gpio.inc
+++ b/board/reef/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/reef/led.c b/board/reef/led.c
index 807b1c109c..95db062d10 100644
--- a/board/reef/led.c
+++ b/board/reef/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -27,8 +27,7 @@
 #define LED_ON_1SEC_TICKS 1
 #define LED_ON_2SECS_TICKS 2
 
-const enum ec_led_id supported_led_ids[] = {
-			EC_LED_ID_BATTERY_LED};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -36,7 +35,7 @@ enum led_color {
 	LED_OFF = 0,
 	LED_BLUE,
 	LED_AMBER,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static int led_set_color_battery(enum led_color color)
@@ -112,27 +111,31 @@ static void led_set_battery(void)
 		} else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
 			/* Blink once every four seconds. */
 			led_set_color_battery(
-				(suspend_ticks % LED_TOTAL_4SECS_TICKS)
-				< LED_ON_1SEC_TICKS ? LED_AMBER : LED_OFF);
+				(suspend_ticks % LED_TOTAL_4SECS_TICKS) <
+						LED_ON_1SEC_TICKS ?
+					LED_AMBER :
+					LED_OFF);
 		} else {
 			led_set_color_battery(LED_OFF);
 		}
 		break;
 	case PWR_STATE_ERROR:
-		led_set_color_battery(
-			(battery_ticks % LED_TOTAL_2SECS_TICKS <
-			 LED_ON_1SEC_TICKS) ? LED_AMBER : LED_OFF);
+		led_set_color_battery((battery_ticks % LED_TOTAL_2SECS_TICKS <
+				       LED_ON_1SEC_TICKS) ?
+					      LED_AMBER :
+					      LED_OFF);
 		break;
 	case PWR_STATE_CHARGE_NEAR_FULL:
 		led_set_color_battery(LED_BLUE);
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (charge_get_flags() & CHARGE_FLAG_FORCE_IDLE)
-			led_set_color_battery(
-				(battery_ticks % LED_TOTAL_4SECS_TICKS <
-				 LED_ON_2SECS_TICKS) ? LED_AMBER : LED_BLUE);
-		else
-			led_set_color_battery(LED_BLUE);
+		led_set_color_battery(LED_BLUE);
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		led_set_color_battery((battery_ticks % LED_TOTAL_4SECS_TICKS <
+				       LED_ON_2SECS_TICKS) ?
+					      LED_AMBER :
+					      LED_BLUE);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
diff --git a/board/reef/usb_pd_policy.c b/board/reef/usb_pd_policy.c
index 2d2ef416b2..e21d4984c1 100644
--- a/board/reef/usb_pd_policy.c
+++ b/board/reef/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,12 +23,12 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT];
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5,
-							TYPEC_RP_1A5};
+static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5,
+							 TYPEC_RP_1A5 };
 
 int board_vbus_source_enabled(int port)
 {
@@ -39,7 +39,8 @@ static void board_vbus_update_source_current(int port)
 {
 	enum gpio_signal gpio = port ? GPIO_USB_C1_5V_EN : GPIO_USB_C0_5V_EN;
 	int flags = (vbus_rp[port] == TYPEC_RP_1A5 && vbus_en[port]) ?
-		(GPIO_INPUT | GPIO_PULL_UP) : (GPIO_OUTPUT | GPIO_PULL_UP);
+			    (GPIO_INPUT | GPIO_PULL_UP) :
+			    (GPIO_OUTPUT | GPIO_PULL_UP);
 
 	/*
 	 * Driving USB_Cx_5V_EN high, actually put a 16.5k resistance
diff --git a/board/reef_it8320/battery.c b/board/reef_it8320/battery.c
index 1b16a672b2..f03000f3c7 100644
--- a/board/reef_it8320/battery.c
+++ b/board/reef_it8320/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -20,7 +20,7 @@
 #include "i2c.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 enum battery_type {
 	BATTERY_SONY_CORP,
@@ -135,7 +135,7 @@ const struct battery_info batt_info_smp_cos4870 = {
 	 * unwanted low VSYS_Prochot# assertion can be avoided.
 	 */
 	.voltage_min = 6100,
-	.precharge_current = 256,	/* mA */
+	.precharge_current = 256, /* mA */
 	.start_charging_min_c = 0,
 	.start_charging_max_c = 46,
 	.charging_min_c = 0,
@@ -183,7 +183,7 @@ const struct battery_info batt_info_sonycorp = {
 	 * unwanted low VSYS_Prochot# assertion can be avoided.
 	 */
 	.voltage_min = 6100,
-	.precharge_current = 256,	/* mA */
+	.precharge_current = 256, /* mA */
 	.start_charging_min_c = 0,
 	.start_charging_max_c = 50,
 	.charging_min_c = 0,
@@ -240,7 +240,7 @@ const struct battery_info batt_info_panasoic = {
 	 * unwanted low VSYS_Prochot# assertion can be avoided.
 	 */
 	.voltage_min = 6100,
-	.precharge_current = 256,	/* mA */
+	.precharge_current = 256, /* mA */
 	.start_charging_min_c = 0,
 	.start_charging_max_c = 50,
 	.charging_min_c = 0,
@@ -384,7 +384,7 @@ const struct battery_info batt_info_c22n1626 = {
 	 * unwanted low VSYS_Prochot# assertion can be avoided.
 	 */
 	.voltage_min = 6100,
-	.precharge_current = 256,	/* mA */
+	.precharge_current = 256, /* mA */
 	.start_charging_min_c = 0,
 	.start_charging_max_c = 45,
 	.charging_min_c = 0,
@@ -398,7 +398,7 @@ static int batt_smp_cos4870_init(void)
 	int batt_status;
 
 	return battery_status(&batt_status) ? 0 :
-		batt_status & STATUS_INITIALIZED;
+					      batt_status & STATUS_INITIALIZED;
 }
 
 static int batt_sony_corp_init(void)
@@ -411,8 +411,9 @@ static int batt_sony_corp_init(void)
 	 *      : 0b - Allowed to Discharge
 	 *      : 1b - Not Allowed to Discharge
 	 */
-	return sb_read(SB_MANUFACTURER_ACCESS, &batt_status) ? 0 :
-		!(batt_status & SONY_DISCHARGE_DISABLE_FET_BIT);
+	return sb_read(SB_MANUFACTURER_ACCESS, &batt_status) ?
+		       0 :
+		       !(batt_status & SONY_DISCHARGE_DISABLE_FET_BIT);
 }
 
 static int batt_panasonic_init(void)
@@ -425,8 +426,9 @@ static int batt_panasonic_init(void)
 	 *      : 0b - Not Allowed to Discharge
 	 *      : 1b - Allowed to Discharge
 	 */
-	return sb_read(SB_MANUFACTURER_ACCESS, &batt_status) ? 0 :
-		!!(batt_status & PANASONIC_DISCHARGE_ENABLE_FET_BIT);
+	return sb_read(SB_MANUFACTURER_ACCESS, &batt_status) ?
+		       0 :
+		       !!(batt_status & PANASONIC_DISCHARGE_ENABLE_FET_BIT);
 }
 
 static int batt_c22n1626_init(void)
@@ -439,8 +441,9 @@ static int batt_c22n1626_init(void)
 	 *      : 0b - Not Allowed to Discharge
 	 *      : 1b - Allowed to Discharge
 	 */
-	return sb_read(SB_PACK_STATUS, &batt_status) ? 0 :
-		!!(batt_status & C22N1626_DISCHARGE_ENABLE_FET_BIT);
+	return sb_read(SB_PACK_STATUS, &batt_status) ?
+		       0 :
+		       !!(batt_status & C22N1626_DISCHARGE_ENABLE_FET_BIT);
 }
 
 static const struct ship_mode_info ship_mode_info_smp_cos4870 = {
@@ -513,7 +516,8 @@ BUILD_ASSERT(ARRAY_SIZE(info) == BATTERY_TYPE_COUNT);
 static inline const struct board_batt_params *board_get_batt_params(void)
 {
 	return &info[board_battery_type == BATTERY_TYPE_COUNT ?
-			DEFAULT_BATTERY_TYPE : board_battery_type];
+			     DEFAULT_BATTERY_TYPE :
+			     board_battery_type];
 }
 
 enum battery_present battery_hw_present(void)
@@ -540,8 +544,9 @@ static int board_get_battery_type(void)
 
 	/* Initialize fast charging parameters */
 	chg_params = board_get_batt_params()->fast_chg_params;
-	prev_chg_profile_info = &chg_params->chg_profile_info[
-					chg_params->default_temp_range_profile];
+	prev_chg_profile_info =
+		&chg_params->chg_profile_info
+			 [chg_params->default_temp_range_profile];
 
 	return board_battery_type;
 }
@@ -571,11 +576,11 @@ int board_cut_off_battery(void)
 {
 	int rv;
 	const struct ship_mode_info *ship_mode_inf =
-				board_get_batt_params()->ship_mode_inf;
+		board_get_batt_params()->ship_mode_inf;
 
 	/* Ship mode command must be sent twice to take effect */
 	rv = sb_write(ship_mode_inf->ship_mode_reg,
-			ship_mode_inf->ship_mode_data);
+		      ship_mode_inf->ship_mode_data);
 	if (rv != EC_SUCCESS)
 		return rv;
 
@@ -591,7 +596,7 @@ static int charger_should_discharge_on_ac(struct charge_state_data *curr)
 
 	/* Do not discharge on AC if the battery is still waking up */
 	if (!(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
-		!(curr->batt.status & STATUS_FULLY_CHARGED))
+	    !(curr->batt.status & STATUS_FULLY_CHARGED))
 		return 0;
 
 	/*
@@ -608,8 +613,8 @@ static int charger_should_discharge_on_ac(struct charge_state_data *curr)
 	 * and suspend USB charging and DC/DC converter.
 	 */
 	if (!battery_is_cut_off() &&
-		!(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
-		(curr->batt.status & STATUS_FULLY_CHARGED))
+	    !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
+	    (curr->batt.status & STATUS_FULLY_CHARGED))
 		return 1;
 
 	/*
@@ -642,10 +647,10 @@ int charger_profile_override(struct charge_state_data *curr)
 		return 0;
 	}
 
-	return charger_profile_override_common(curr,
-			board_get_batt_params()->fast_chg_params,
-			&prev_chg_profile_info,
-			board_get_batt_params()->batt_info->voltage_max);
+	return charger_profile_override_common(
+		curr, board_get_batt_params()->fast_chg_params,
+		&prev_chg_profile_info,
+		board_get_batt_params()->batt_info->voltage_max);
 }
 
 /*
@@ -671,7 +676,7 @@ enum battery_present battery_is_present(void)
 	 * Battery status will be inactive until it is initialized.
 	 */
 	if (batt_pres == BP_YES && batt_pres_prev != batt_pres &&
-		!battery_is_cut_off()) {
+	    !battery_is_cut_off()) {
 		/* Re-init board battery if battery presence status changes */
 		if (board_get_battery_type() == BATTERY_TYPE_COUNT) {
 			if (bd9995x_get_battery_voltage() >=
diff --git a/board/reef_it8320/board.c b/board/reef_it8320/board.c
index 1b6bc3d137..b00e451842 100644
--- a/board/reef_it8320/board.c
+++ b/board/reef_it8320/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -29,6 +29,7 @@
 #include "math_util.h"
 #include "motion_sense.h"
 #include "motion_lid.h"
+#include "panic.h"
 #include "power.h"
 #include "power_button.h"
 #include "pwm.h"
@@ -48,50 +49,40 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define IN_ALL_SYS_PG	POWER_SIGNAL_MASK(X86_ALL_SYS_PG)
-#define IN_PGOOD_PP3300	POWER_SIGNAL_MASK(X86_PGOOD_PP3300)
-#define IN_PGOOD_PP5000	POWER_SIGNAL_MASK(X86_PGOOD_PP5000)
+#define IN_ALL_SYS_PG POWER_SIGNAL_MASK(X86_ALL_SYS_PG)
+#define IN_PGOOD_PP3300 POWER_SIGNAL_MASK(X86_PGOOD_PP3300)
+#define IN_PGOOD_PP5000 POWER_SIGNAL_MASK(X86_PGOOD_PP5000)
 
 #include "gpio_list.h"
 
 const struct adc_t adc_channels[] = {
 	/* Convert to mV (3000mV/1024). */
-	{"CHARGER",     3000, 1024, 0, CHIP_ADC_CH1}, /* GPI1 */
-	{"AMBIENT",     3000, 1024, 0, CHIP_ADC_CH2}, /* GPI2 */
-	{"BRD_ID",      3000, 1024, 0, CHIP_ADC_CH3}, /* GPI3 */
+	{ "CHARGER", 3000, 1024, 0, CHIP_ADC_CH1 }, /* GPI1 */
+	{ "AMBIENT", 3000, 1024, 0, CHIP_ADC_CH2 }, /* GPI2 */
+	{ "BRD_ID", 3000, 1024, 0, CHIP_ADC_CH3 }, /* GPI3 */
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
-const struct i2c_port_t i2c_ports[]  = {
-	{
-		.name = "mux",
-		.port = IT83XX_I2C_CH_C,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_C_SCL,
-		.sda  = GPIO_EC_I2C_C_SDA
-	},
-	{
-		.name = "batt",
-		.port = IT83XX_I2C_CH_E,
-		.kbps = 100,
-		.scl  = GPIO_EC_I2C_E_SCL,
-		.sda  = GPIO_EC_I2C_E_SDA
-	},
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "mux",
+	  .port = IT83XX_I2C_CH_C,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_C_SCL,
+	  .sda = GPIO_EC_I2C_C_SDA },
+	{ .name = "batt",
+	  .port = IT83XX_I2C_CH_E,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_E_SCL,
+	  .sda = GPIO_EC_I2C_E_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
 const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_EMBEDDED,
-		.drv = &it83xx_tcpm_drv
-	},
-	{
-		.bus_type = EC_BUS_TYPE_EMBEDDED,
-		.drv = &it83xx_tcpm_drv
-	},
+	{ .bus_type = EC_BUS_TYPE_EMBEDDED, .drv = &it83xx_tcpm_drv },
+	{ .bus_type = EC_BUS_TYPE_EMBEDDED, .drv = &it83xx_tcpm_drv },
 };
 
 void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
@@ -126,9 +117,8 @@ static void it83xx_tcpc_update_hpd_status(const struct usb_mux *me,
 {
 	int hpd_lvl = (mux_state & USB_PD_MUX_HPD_LVL) ? 1 : 0;
 	int hpd_irq = (mux_state & USB_PD_MUX_HPD_IRQ) ? 1 : 0;
-	enum gpio_signal gpio =
-		me->usb_port ? GPIO_USB_C1_HPD_1P8_ODL
-			     : GPIO_USB_C0_HPD_1P8_ODL;
+	enum gpio_signal gpio = me->usb_port ? GPIO_USB_C1_HPD_1P8_ODL :
+					       GPIO_USB_C0_HPD_1P8_ODL;
 
 	/* This driver does not use host command ACKs */
 	*ack_required = false;
@@ -143,20 +133,26 @@ static void it83xx_tcpc_update_hpd_status(const struct usb_mux *me,
 	}
 }
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
-		.driver = &pi3usb3x532_usb_mux_driver,
-		.hpd_update = &it83xx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX,
+				.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
+				.driver = &pi3usb3x532_usb_mux_driver,
+				.hpd_update = &it83xx_tcpc_update_hpd_status,
+			},
 	},
 	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = 0x10,
-		.driver = &ps8740_usb_mux_driver,
-		.hpd_update = &it83xx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_USB_MUX,
+				.i2c_addr_flags = 0x10,
+				.driver = &ps8740_usb_mux_driver,
+				.hpd_update = &it83xx_tcpc_update_hpd_status,
+			},
 	},
 };
 
@@ -165,18 +161,18 @@ const int usb_port_enable[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT] = {
 };
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp,
-				 .idx = 0},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
+	[TEMP_SENSOR_BATTERY] = { .name = "Battery",
+				  .type = TEMP_SENSOR_TYPE_BATTERY,
+				  .read = charge_get_battery_temp,
+				  .idx = 0 },
+	[TEMP_SENSOR_AMBIENT] = { .name = "Ambient",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_51k1_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_AMB },
+	[TEMP_SENSOR_CHARGER] = { .name = "Charger",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_13k7_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_CHARGER },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -234,12 +230,12 @@ static void board_init(void)
 	gpio_enable_interrupt(GPIO_CHARGER_INT_L);
 
 	/*
-	* Initialize HPD to low; after sysjump SOC needs to see
-	* HPD pulse to enable video path
-	*/
+	 * Initialize HPD to low; after sysjump SOC needs to see
+	 * HPD pulse to enable video path
+	 */
 	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
 		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_INIT_I2C + 1);
 
@@ -303,8 +299,8 @@ int board_set_active_charge_port(int charge_port)
  * @param charge_ma     Desired charge limit (mA).
  * @param charge_mv     Negotiated charge voltage (mV).
  */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	/* Enable charging trigger by BC1.2 detection */
 	int bc12_enable = (supplier == CHARGE_SUPPLIER_BC12_CDP ||
@@ -316,8 +312,8 @@ void board_set_charge_limit(int port, int supplier, int charge_ma,
 		return;
 
 	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-				   CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 /**
@@ -406,17 +402,17 @@ void board_hibernate_late(void)
 	int i;
 	const uint32_t hibernate_pins[][2] = {
 		/* Turn off LEDs in hibernate */
-		{GPIO_BAT_LED_BLUE, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_BAT_LED_AMBER, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_LID_OPEN, GPIO_INT_RISING | GPIO_PULL_DOWN},
+		{ GPIO_BAT_LED_BLUE, GPIO_INPUT | GPIO_PULL_UP },
+		{ GPIO_BAT_LED_AMBER, GPIO_INPUT | GPIO_PULL_UP },
+		{ GPIO_LID_OPEN, GPIO_INT_RISING | GPIO_PULL_DOWN },
 
 		/*
 		 * BD99956 handles charge input automatically. We'll disable
 		 * charge output in hibernate. Charger will assert ACOK_OD
 		 * when VBUS or VCC are plugged in.
 		 */
-		{GPIO_USB_C0_5V_EN,       GPIO_INPUT  | GPIO_PULL_DOWN},
-		{GPIO_USB_C1_5V_EN,       GPIO_INPUT  | GPIO_PULL_DOWN},
+		{ GPIO_USB_C0_5V_EN, GPIO_INPUT | GPIO_PULL_DOWN },
+		{ GPIO_USB_C1_5V_EN, GPIO_INPUT | GPIO_PULL_DOWN },
 	};
 
 	/* Change GPIOs' state in hibernate for better power consumption */
@@ -447,8 +443,8 @@ struct {
 	int thresh_mv;
 } const reef_it8320_board_versions[] = {
 	/* Vin = 3.3V, R1 = 46.4K, R2 values listed below */
-	{ BOARD_VERSION_1, 328 * 1.03 },  /* 5.11 Kohm */
-	{ BOARD_VERSION_2, 670 * 1.03 },  /* 11.8 Kohm */
+	{ BOARD_VERSION_1, 328 * 1.03 }, /* 5.11 Kohm */
+	{ BOARD_VERSION_2, 670 * 1.03 }, /* 11.8 Kohm */
 	{ BOARD_VERSION_3, 1012 * 1.03 }, /* 20.5 Kohm */
 	{ BOARD_VERSION_4, 1357 * 1.03 }, /* 32.4 Kohm */
 	{ BOARD_VERSION_5, 1690 * 1.03 }, /* 48.7 Kohm */
diff --git a/board/reef_it8320/board.h b/board/reef_it8320/board.h
index cf29faa8f8..45abf34151 100644
--- a/board/reef_it8320/board.h
+++ b/board/reef_it8320/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,24 +19,24 @@
  * By default, enable all console messages excepted HC, ACPI and event:
  * The sensor stack is generating a lot of activity.
  */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
 #undef CONFIG_HOSTCMD_DEBUG_MODE
 #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
 
 /* EC console commands  */
 #define CONFIG_CMD_BATT_MFG_ACCESS
 #define CONFIG_CMD_CHARGER_ADC_AMON_BMON
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 #define BD9995X_IOUT_GAIN_SELECT \
-		BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V
+	BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V
 
 #define CONFIG_CHARGER_PSYS_READ
 #define BD9995X_PSYS_GAIN_SELECT \
-		BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_02UAW
+	BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_02UAW
 
 /* Battery */
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY  "LION"
+#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
 #define CONFIG_BATTERY_CUT_OFF
 #define CONFIG_BATTERY_PRESENT_CUSTOM
 #define CONFIG_BATTERY_SMART
@@ -57,7 +57,7 @@
 #define CONFIG_USB_CHARGER
 #define CONFIG_CHARGER_PROFILE_OVERRIDE
 #define CONFIG_CHARGER_PROFILE_OVERRIDE_COMMON
-#undef  CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES
+#undef CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES
 #define CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES 3
 #define CONFIG_CHARGE_MANAGER_EXTERNAL_POWER_LIMIT
 
@@ -89,7 +89,7 @@
 #define CONFIG_USB_PD_TCPMV2
 #define CONFIG_USB_DRP_ACC_TRYSRC
 #define CONFIG_USB_PD_REV30
-#define CONFIG_USB_PID 0x1234            /* Invalid PID for development board */
+#define CONFIG_USB_PID 0x1234 /* Invalid PID for development board */
 #define CONFIG_USB_PD_DECODE_SOP
 #define CONFIG_USB_PD_DEBUG_LEVEL 2
 #define CONFIG_USB_PD_COMM_LOCKED
@@ -112,7 +112,7 @@
 /* EC */
 #define CONFIG_ADC
 #define CONFIG_EXTPOWER_GPIO
-#undef  CONFIG_EXTPOWER_DEBOUNCE_MS
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
 #define CONFIG_EXTPOWER_DEBOUNCE_MS 1000
 #define CONFIG_I2C
 #define CONFIG_I2C_CONTROLLER
@@ -162,15 +162,15 @@
 #include "registers.h"
 
 /* I2C ports */
-#define I2C_PORT_USB_MUX		IT83XX_I2C_CH_C
-#define I2C_PORT_BATTERY		IT83XX_I2C_CH_E
-#define I2C_PORT_CHARGER		IT83XX_I2C_CH_E
+#define I2C_PORT_USB_MUX IT83XX_I2C_CH_C
+#define I2C_PORT_BATTERY IT83XX_I2C_CH_E
+#define I2C_PORT_CHARGER IT83XX_I2C_CH_E
 
 /* ADC signal */
 enum adc_channel {
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC CH1 */
-	ADC_TEMP_SENSOR_AMB,		/* ADC CH2 */
-	ADC_BOARD_ID,			/* ADC CH3 */
+	ADC_TEMP_SENSOR_CHARGER, /* ADC CH1 */
+	ADC_TEMP_SENSOR_AMB, /* ADC CH2 */
+	ADC_BOARD_ID, /* ADC CH3 */
 	ADC_CH_COUNT
 };
 
@@ -200,16 +200,16 @@ enum reef_it8320_board_version {
  * delay to turn on the power supply max is ~16ms.
  * delay to turn off the power supply max is about ~180ms.
  */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* delay to turn on/off vconn */
 
 /* Define typical operating power and max power */
 #define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       45000
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_VOLTAGE_MV     20000
+#define PD_MAX_POWER_MW 45000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Reset PD MCU */
 void board_reset_pd_mcu(void);
diff --git a/board/reef_it8320/build.mk b/board/reef_it8320/build.mk
index e5c12f9090..0c2fcec14f 100644
--- a/board/reef_it8320/build.mk
+++ b/board/reef_it8320/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/reef_it8320/ec.tasklist b/board/reef_it8320/ec.tasklist
index fdaf792a17..7faf124d53 100644
--- a/board/reef_it8320/ec.tasklist
+++ b/board/reef_it8320/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/reef_it8320/gpio.inc b/board/reef_it8320/gpio.inc
index ac2fbf486e..54528d3818 100644
--- a/board/reef_it8320/gpio.inc
+++ b/board/reef_it8320/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/reef_it8320/led.c b/board/reef_it8320/led.c
index a1ea5964a8..1b521b9409 100644
--- a/board/reef_it8320/led.c
+++ b/board/reef_it8320/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -27,8 +27,7 @@
 #define LED_ON_1SEC_TICKS 1
 #define LED_ON_2SECS_TICKS 2
 
-const enum ec_led_id supported_led_ids[] = {
-			EC_LED_ID_BATTERY_LED};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -36,7 +35,7 @@ enum led_color {
 	LED_OFF = 0,
 	LED_BLUE,
 	LED_AMBER,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static int led_set_color_battery(enum led_color color)
@@ -113,27 +112,31 @@ static void led_set_battery(void)
 		} else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
 			/* Blink once every four seconds. */
 			led_set_color_battery(
-				(suspend_ticks % LED_TOTAL_4SECS_TICKS)
-				< LED_ON_1SEC_TICKS ? LED_AMBER : LED_OFF);
+				(suspend_ticks % LED_TOTAL_4SECS_TICKS) <
+						LED_ON_1SEC_TICKS ?
+					LED_AMBER :
+					LED_OFF);
 		} else {
 			led_set_color_battery(LED_OFF);
 		}
 		break;
 	case PWR_STATE_ERROR:
-		led_set_color_battery(
-			(battery_ticks % LED_TOTAL_2SECS_TICKS <
-			 LED_ON_1SEC_TICKS) ? LED_AMBER : LED_OFF);
+		led_set_color_battery((battery_ticks % LED_TOTAL_2SECS_TICKS <
+				       LED_ON_1SEC_TICKS) ?
+					      LED_AMBER :
+					      LED_OFF);
 		break;
 	case PWR_STATE_CHARGE_NEAR_FULL:
 		led_set_color_battery(LED_BLUE);
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (charge_get_flags() & CHARGE_FLAG_FORCE_IDLE)
-			led_set_color_battery(
-				(battery_ticks % LED_TOTAL_4SECS_TICKS <
-				 LED_ON_2SECS_TICKS) ? LED_AMBER : LED_BLUE);
-		else
-			led_set_color_battery(LED_BLUE);
+		led_set_color_battery(LED_BLUE);
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		led_set_color_battery((battery_ticks % LED_TOTAL_4SECS_TICKS <
+				       LED_ON_2SECS_TICKS) ?
+					      LED_AMBER :
+					      LED_BLUE);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
diff --git a/board/reef_it8320/usb_pd_policy.c b/board/reef_it8320/usb_pd_policy.c
index 7fec6bc975..ce909520a2 100644
--- a/board/reef_it8320/usb_pd_policy.c
+++ b/board/reef_it8320/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,12 +23,12 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT];
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5,
-							TYPEC_RP_1A5};
+static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5,
+							 TYPEC_RP_1A5 };
 
 int board_vbus_source_enabled(int port)
 {
@@ -39,7 +39,7 @@ static void board_vbus_update_source_current(int port)
 {
 	enum gpio_signal gpio = port ? GPIO_USB_C1_5V_EN : GPIO_USB_C0_5V_EN;
 	enum gpio_signal gpio_3a_en = port ? GPIO_EN_USB_C1_3A :
-		GPIO_EN_USB_C0_3A;
+					     GPIO_EN_USB_C0_3A;
 
 	gpio_set_level(gpio_3a_en, vbus_rp[port] == TYPEC_RP_3A0 ? 1 : 0);
 	gpio_set_level(gpio, vbus_en[port]);
diff --git a/board/reef_mchp/battery.c b/board/reef_mchp/battery.c
index c557533c9d..d18caec5d0 100644
--- a/board/reef_mchp/battery.c
+++ b/board/reef_mchp/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -22,7 +22,7 @@
 #include "tfdp_chip.h"
 
 #define CPUTS(outstr) cputs(CC_CHARGER, outstr)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 enum battery_type {
 	BATTERY_SONY_CORP,
@@ -137,7 +137,7 @@ const struct battery_info batt_info_smp_cos4870 = {
 	 * unwanted low VSYS_Prochot# assertion can be avoided.
 	 */
 	.voltage_min = 6100,
-	.precharge_current = 256,	/* mA */
+	.precharge_current = 256, /* mA */
 	.start_charging_min_c = 0,
 	.start_charging_max_c = 46,
 	.charging_min_c = 0,
@@ -185,7 +185,7 @@ const struct battery_info batt_info_sonycorp = {
 	 * unwanted low VSYS_Prochot# assertion can be avoided.
 	 */
 	.voltage_min = 6100,
-	.precharge_current = 256,	/* mA */
+	.precharge_current = 256, /* mA */
 	.start_charging_min_c = 0,
 	.start_charging_max_c = 50,
 	.charging_min_c = 0,
@@ -242,7 +242,7 @@ const struct battery_info batt_info_panasoic = {
 	 * unwanted low VSYS_Prochot# assertion can be avoided.
 	 */
 	.voltage_min = 6100,
-	.precharge_current = 256,	/* mA */
+	.precharge_current = 256, /* mA */
 	.start_charging_min_c = 0,
 	.start_charging_max_c = 50,
 	.charging_min_c = 0,
@@ -386,7 +386,7 @@ const struct battery_info batt_info_c22n1626 = {
 	 * unwanted low VSYS_Prochot# assertion can be avoided.
 	 */
 	.voltage_min = 6100,
-	.precharge_current = 256,	/* mA */
+	.precharge_current = 256, /* mA */
 	.start_charging_min_c = 0,
 	.start_charging_max_c = 45,
 	.charging_min_c = 0,
@@ -400,7 +400,7 @@ static int batt_smp_cos4870_init(void)
 	int batt_status;
 
 	return battery_status(&batt_status) ? 0 :
-		batt_status & STATUS_INITIALIZED;
+					      batt_status & STATUS_INITIALIZED;
 }
 
 static int batt_sony_corp_init(void)
@@ -413,8 +413,9 @@ static int batt_sony_corp_init(void)
 	 *      : 0b - Allowed to Discharge
 	 *      : 1b - Not Allowed to Discharge
 	 */
-	return sb_read(SB_MANUFACTURER_ACCESS, &batt_status) ? 0 :
-		!(batt_status & SONY_DISCHARGE_DISABLE_FET_BIT);
+	return sb_read(SB_MANUFACTURER_ACCESS, &batt_status) ?
+		       0 :
+		       !(batt_status & SONY_DISCHARGE_DISABLE_FET_BIT);
 }
 
 static int batt_panasonic_init(void)
@@ -427,8 +428,9 @@ static int batt_panasonic_init(void)
 	 *      : 0b - Not Allowed to Discharge
 	 *      : 1b - Allowed to Discharge
 	 */
-	return sb_read(SB_MANUFACTURER_ACCESS, &batt_status) ? 0 :
-		!!(batt_status & PANASONIC_DISCHARGE_ENABLE_FET_BIT);
+	return sb_read(SB_MANUFACTURER_ACCESS, &batt_status) ?
+		       0 :
+		       !!(batt_status & PANASONIC_DISCHARGE_ENABLE_FET_BIT);
 }
 
 static int batt_c22n1626_init(void)
@@ -441,8 +443,9 @@ static int batt_c22n1626_init(void)
 	 *      : 0b - Not Allowed to Discharge
 	 *      : 1b - Allowed to Discharge
 	 */
-	return sb_read(SB_PACK_STATUS, &batt_status) ? 0 :
-		!!(batt_status & C22N1626_DISCHARGE_ENABLE_FET_BIT);
+	return sb_read(SB_PACK_STATUS, &batt_status) ?
+		       0 :
+		       !!(batt_status & C22N1626_DISCHARGE_ENABLE_FET_BIT);
 }
 
 static const struct ship_mode_info ship_mode_info_smp_cos4870 = {
@@ -515,7 +518,8 @@ BUILD_ASSERT(ARRAY_SIZE(info) == BATTERY_TYPE_COUNT);
 static inline const struct board_batt_params *board_get_batt_params(void)
 {
 	return &info[board_battery_type == BATTERY_TYPE_COUNT ?
-			DEFAULT_BATTERY_TYPE : board_battery_type];
+			     DEFAULT_BATTERY_TYPE :
+			     board_battery_type];
 }
 
 enum battery_present battery_hw_present(void)
@@ -545,8 +549,9 @@ static int board_get_battery_type(void)
 
 	/* Initialize fast charging parameters */
 	chg_params = board_get_batt_params()->fast_chg_params;
-	prev_chg_profile_info = &chg_params->chg_profile_info[
-			chg_params->default_temp_range_profile];
+	prev_chg_profile_info =
+		&chg_params->chg_profile_info
+			 [chg_params->default_temp_range_profile];
 
 	return board_battery_type;
 }
@@ -561,8 +566,7 @@ static int board_get_battery_type(void)
 static void board_init_battery_type(void)
 {
 	if (board_get_battery_type() != BATTERY_TYPE_COUNT)
-		CPRINTS("found batt:%s",
-			info[board_battery_type].manuf_name);
+		CPRINTS("found batt:%s", info[board_battery_type].manuf_name);
 	else
 		CPUTS("battery not found");
 }
@@ -577,16 +581,16 @@ int board_cut_off_battery(void)
 {
 	int rv;
 	const struct ship_mode_info *ship_mode_inf =
-				board_get_batt_params()->ship_mode_inf;
+		board_get_batt_params()->ship_mode_inf;
 
 	/* Ship mode command must be sent twice to take effect */
 	rv = sb_write(ship_mode_inf->ship_mode_reg,
-			ship_mode_inf->ship_mode_data);
+		      ship_mode_inf->ship_mode_data);
 	if (rv != EC_SUCCESS)
 		return rv;
 
 	rv = sb_write(ship_mode_inf->ship_mode_reg,
-			ship_mode_inf->ship_mode_data);
+		      ship_mode_inf->ship_mode_data);
 
 	return rv;
 }
@@ -599,7 +603,7 @@ static int charger_should_discharge_on_ac(struct charge_state_data *curr)
 
 	/* Do not discharge on AC if the battery is still waking up */
 	if (!(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
-			!(curr->batt.status & STATUS_FULLY_CHARGED))
+	    !(curr->batt.status & STATUS_FULLY_CHARGED))
 		return 0;
 
 	/*
@@ -616,8 +620,8 @@ static int charger_should_discharge_on_ac(struct charge_state_data *curr)
 	 * and suspend USB charging and DC/DC converter.
 	 */
 	if (!battery_is_cut_off() &&
-		!(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
-			(curr->batt.status & STATUS_FULLY_CHARGED))
+	    !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
+	    (curr->batt.status & STATUS_FULLY_CHARGED))
 		return 1;
 
 	/*
@@ -650,10 +654,10 @@ int charger_profile_override(struct charge_state_data *curr)
 		return 0;
 	}
 
-	return charger_profile_override_common(curr,
-			board_get_batt_params()->fast_chg_params,
-			&prev_chg_profile_info,
-			board_get_batt_params()->batt_info->voltage_max);
+	return charger_profile_override_common(
+		curr, board_get_batt_params()->fast_chg_params,
+		&prev_chg_profile_info,
+		board_get_batt_params()->batt_info->voltage_max);
 }
 
 /*
@@ -679,7 +683,7 @@ enum battery_present battery_is_present(void)
 	 * Battery status will be inactive until it is initialized.
 	 */
 	if (batt_pres == BP_YES && batt_pres_prev != batt_pres &&
-		!battery_is_cut_off()) {
+	    !battery_is_cut_off()) {
 		/* Re-init board battery if battery presence status changes */
 		if (board_get_battery_type() == BATTERY_TYPE_COUNT) {
 			if (bd9995x_get_battery_voltage() >=
diff --git a/board/reef_mchp/board.c b/board/reef_mchp/board.c
index c9293ad080..39196cb308 100644
--- a/board/reef_mchp/board.c
+++ b/board/reef_mchp/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -35,6 +35,7 @@
 #include "math_util.h"
 #include "motion_sense.h"
 #include "motion_lid.h"
+#include "panic.h"
 #include "power.h"
 #include "power_button.h"
 #include "pwm.h"
@@ -57,17 +58,16 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-
 #define CPUTS(outstr) cputs(CC_USBCHARGE, outstr)
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define IN_ALL_SYS_PG	POWER_SIGNAL_MASK(X86_ALL_SYS_PG)
-#define IN_PGOOD_PP3300	POWER_SIGNAL_MASK(X86_PGOOD_PP3300)
-#define IN_PGOOD_PP5000	POWER_SIGNAL_MASK(X86_PGOOD_PP5000)
+#define IN_ALL_SYS_PG POWER_SIGNAL_MASK(X86_ALL_SYS_PG)
+#define IN_PGOOD_PP3300 POWER_SIGNAL_MASK(X86_PGOOD_PP3300)
+#define IN_PGOOD_PP5000 POWER_SIGNAL_MASK(X86_PGOOD_PP5000)
 
-#define USB_PD_PORT_ANX74XX	0
-#define USB_PD_PORT_PS8751	1
+#define USB_PD_PORT_ANX74XX 0
+#define USB_PD_PORT_PS8751 1
 
 #ifdef CONFIG_BOARD_PRE_INIT
 /*
@@ -161,7 +161,7 @@ void tablet_mode_interrupt(enum gpio_signal signal)
 
 /* SPI devices */
 const struct spi_device_t spi_devices[] = {
-	{ QMSPI0_PORT, 4, GPIO_QMSPI_CS0},
+	{ QMSPI0_PORT, 4, GPIO_QMSPI_CS0 },
 #if defined(CONFIG_SPI_ACCEL_PORT)
 	{ GPSPI0_PORT, 2, GPIO_SPI0_CS0 },
 #endif
@@ -175,15 +175,9 @@ const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
  */
 const struct adc_t adc_channels[] = {
 	/* Vref = 3.000V, 10-bit unsigned reading */
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"CHARGER", 3000, 1024, 0, 0
-	},
-	[ADC_TEMP_SENSOR_AMB] = {
-		"AMBIENT", 3000, 1024, 0, 1
-	},
-	[ADC_BOARD_ID] = {
-		"BRD_ID", 3000, 1024, 0, 2
-	},
+	[ADC_TEMP_SENSOR_CHARGER] = { "CHARGER", 3000, 1024, 0, 0 },
+	[ADC_TEMP_SENSOR_AMB] = { "AMBIENT", 3000, 1024, 0, 1 },
+	[ADC_BOARD_ID] = { "BRD_ID", 3000, 1024, 0, 2 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
@@ -192,7 +186,7 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 const struct pwm_t pwm_channels[] = {
 	/* channel, flags */
 	[PWM_CH_LED_GREEN] = { 4, PWM_CONFIG_DSLEEP },
-	[PWM_CH_LED_RED] =   { 5, PWM_CONFIG_DSLEEP },
+	[PWM_CH_LED_RED] = { 5, PWM_CONFIG_DSLEEP },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 #endif /* #ifdef CONFIG_PWM */
@@ -203,42 +197,32 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
  * Due to added RC of interposer board temporarily reduce
  * 400 to 100 kHz.
  */
-const struct i2c_port_t i2c_ports[]  = {
-	{
-		.name = "tcpc0",
-		.port = MCHP_I2C_PORT0,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_USB_C0_PD_SCL,
-		.sda  = GPIO_EC_I2C_USB_C0_PD_SDA
-	},
-	{
-		.name = "tcpc1",
-		.port = MCHP_I2C_PORT2,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_USB_C1_PD_SCL,
-		.sda  = GPIO_EC_I2C_USB_C1_PD_SDA
-	},
-	{
-		.name = "accelgyro",
-		.port = I2C_PORT_GYRO,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_GYRO_SCL,
-		.sda  = GPIO_EC_I2C_GYRO_SDA
-	},
-	{
-		.name = "sensors",
-		.port = MCHP_I2C_PORT7,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_SENSOR_SCL,
-		.sda  = GPIO_EC_I2C_SENSOR_SDA
-	},
-	{
-		.name = "batt",
-		.port = MCHP_I2C_PORT3,
-		.kbps = 100,
-		.scl  = GPIO_EC_I2C_POWER_SCL,
-		.sda  = GPIO_EC_I2C_POWER_SDA
-	},
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "tcpc0",
+	  .port = MCHP_I2C_PORT0,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_USB_C0_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C0_PD_SDA },
+	{ .name = "tcpc1",
+	  .port = MCHP_I2C_PORT2,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_USB_C1_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C1_PD_SDA },
+	{ .name = "accelgyro",
+	  .port = I2C_PORT_GYRO,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_GYRO_SCL,
+	  .sda = GPIO_EC_I2C_GYRO_SDA },
+	{ .name = "sensors",
+	  .port = MCHP_I2C_PORT7,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_SENSOR_SCL,
+	  .sda = GPIO_EC_I2C_SENSOR_SDA },
+	{ .name = "batt",
+	  .port = MCHP_I2C_PORT3,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_POWER_SCL,
+	  .sda = GPIO_EC_I2C_POWER_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -415,17 +399,21 @@ static int ps8751_tune_mux(const struct usb_mux *me)
  * tcpc_config array. The tcpc_config array contains the actual EC I2C
  * port, device address, and a function pointer into the driver code.
  */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_ANX74XX] = {
-		.usb_port = USB_PD_PORT_ANX74XX,
-		.driver = &anx74xx_tcpm_usb_mux_driver,
-		.hpd_update = &anx74xx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_ANX74XX,
+			.driver = &anx74xx_tcpm_usb_mux_driver,
+			.hpd_update = &anx74xx_tcpc_update_hpd_status,
+		},
 	},
 	[USB_PD_PORT_PS8751] = {
-		.usb_port = USB_PD_PORT_PS8751,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-		.board_init = &ps8751_tune_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_PS8751,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			.board_init = &ps8751_tune_mux,
+		},
 	}
 };
 
@@ -534,9 +522,9 @@ void board_tcpc_init(void)
 	 */
 	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
 		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
-DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1);
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
 
 /*
  * Data derived from Seinhart-Hart equation in a resistor divider circuit with
@@ -573,8 +561,7 @@ int board_get_charger_temp(int idx, int *temp_ptr)
 	if (mv < 0)
 		return -1;
 
-	*temp_ptr = thermistor_linear_interpolate(mv,
-		&charger_thermistor_info);
+	*temp_ptr = thermistor_linear_interpolate(mv, &charger_thermistor_info);
 	*temp_ptr = C_TO_K(*temp_ptr);
 	return 0;
 }
@@ -614,8 +601,7 @@ int board_get_ambient_temp(int idx, int *temp_ptr)
 	if (mv < 0)
 		return -1;
 
-	*temp_ptr = thermistor_linear_interpolate(mv,
-		&amb_thermistor_info);
+	*temp_ptr = thermistor_linear_interpolate(mv, &amb_thermistor_info);
 	*temp_ptr = C_TO_K(*temp_ptr);
 	return 0;
 }
@@ -626,9 +612,9 @@ int board_get_ambient_temp(int idx, int *temp_ptr)
  * delay from read to taking action
  */
 const struct temp_sensor_t temp_sensors[] = {
-	{"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0},
-	{"Ambient", TEMP_SENSOR_TYPE_BOARD, board_get_ambient_temp, 0},
-	{"Charger", TEMP_SENSOR_TYPE_BOARD, board_get_charger_temp, 1},
+	{ "Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0 },
+	{ "Ambient", TEMP_SENSOR_TYPE_BOARD, board_get_ambient_temp, 0 },
+	{ "Charger", TEMP_SENSOR_TYPE_BOARD, board_get_charger_temp, 1 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -750,8 +736,8 @@ int board_set_active_charge_port(int charge_port)
  * @param charge_ma     Desired charge limit (mA).
  * @param charge_mv     Negotiated charge voltage (mV).
  */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	/* Enable charging trigger by BC1.2 detection */
 	int bc12_enable = (supplier == CHARGE_SUPPLIER_BC12_CDP ||
@@ -763,8 +749,8 @@ void board_set_charge_limit(int port, int supplier, int charge_ma,
 		return;
 
 	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-			CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 /**
@@ -890,17 +876,17 @@ void board_hibernate_late(void)
 	int i;
 	const uint32_t hibernate_pins[][2] = {
 		/* Turn off LEDs in hibernate */
-		{GPIO_BAT_LED_BLUE, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_BAT_LED_AMBER, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_LID_OPEN, GPIO_INT_RISING | GPIO_PULL_DOWN},
+		{ GPIO_BAT_LED_BLUE, GPIO_INPUT | GPIO_PULL_UP },
+		{ GPIO_BAT_LED_AMBER, GPIO_INPUT | GPIO_PULL_UP },
+		{ GPIO_LID_OPEN, GPIO_INT_RISING | GPIO_PULL_DOWN },
 
 		/*
 		 * BD99956 handles charge input automatically. We'll disable
 		 * charge output in hibernate. Charger will assert ACOK_OD
 		 * when VBUS or VCC are plugged in.
 		 */
-		{GPIO_USB_C0_5V_EN,       GPIO_INPUT  | GPIO_PULL_DOWN},
-		{GPIO_USB_C1_5V_EN,       GPIO_INPUT  | GPIO_PULL_DOWN},
+		{ GPIO_USB_C0_5V_EN, GPIO_INPUT | GPIO_PULL_DOWN },
+		{ GPIO_USB_C1_5V_EN, GPIO_INPUT | GPIO_PULL_DOWN },
 	};
 
 	/* Change GPIOs' state in hibernate for better power consumption */
@@ -927,17 +913,13 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0,  0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+				       { FLOAT_TO_FP(1), 0, 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
 
-const mat33_fp_t mag_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0,  FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t mag_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				      { 0, FLOAT_TO_FP(1), 0 },
+				      { 0, 0, FLOAT_TO_FP(-1) } };
 
 /* sensor private data */
 static struct kionix_accel_data g_kx022_data;
@@ -1113,8 +1095,8 @@ struct {
 	int thresh_mv;
 } const reef_board_versions[] = {
 	/* Vin = 3.3V, R1 = 46.4K, R2 values listed below */
-	{ BOARD_VERSION_1, 328 * 1.03 },  /* 5.11 Kohm */
-	{ BOARD_VERSION_2, 670 * 1.03 },  /* 11.8 Kohm */
+	{ BOARD_VERSION_1, 328 * 1.03 }, /* 5.11 Kohm */
+	{ BOARD_VERSION_2, 670 * 1.03 }, /* 11.8 Kohm */
 	{ BOARD_VERSION_3, 1012 * 1.03 }, /* 20.5 Kohm */
 	{ BOARD_VERSION_4, 1357 * 1.03 }, /* 32.4 Kohm */
 	{ BOARD_VERSION_5, 1690 * 1.03 }, /* 48.7 Kohm */
diff --git a/board/reef_mchp/board.h b/board/reef_mchp/board.h
index ad98fac829..bde2d831d3 100644
--- a/board/reef_mchp/board.h
+++ b/board/reef_mchp/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,7 +12,7 @@
  * By default, enable all console messages excepted HC, ACPI and event:
  * The sensor stack is generating a lot of activity.
  */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
 #undef CONFIG_HOSTCMD_DEBUG_MODE
 #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
 
@@ -24,14 +24,14 @@
 #define CONFIG_CMD_ACCEL_INFO
 #define CONFIG_CMD_BATT_MFG_ACCESS
 #define CONFIG_CMD_CHARGER_ADC_AMON_BMON
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 #define BD9995X_IOUT_GAIN_SELECT \
-		BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V
+	BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V
 
 #define CONFIG_CHARGER_PSYS_READ
 #define BD9995X_PSYS_GAIN_SELECT \
-		BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_02UAW
+	BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_02UAW
 
 #define CONFIG_CMD_I2C_STRESS_TEST
 #define CONFIG_CMD_I2C_STRESS_TEST_ACCEL
@@ -41,7 +41,7 @@
 #define CONFIG_CMD_I2C_STRESS_TEST_TCPC
 
 /* Battery */
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY  "LION"
+#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
 #define CONFIG_BATTERY_CUT_OFF
 #define CONFIG_BATTERY_PRESENT_CUSTOM
 #define CONFIG_BATTERY_SMART
@@ -62,7 +62,7 @@
 #define CONFIG_USB_CHARGER
 #define CONFIG_CHARGER_PROFILE_OVERRIDE
 #define CONFIG_CHARGER_PROFILE_OVERRIDE_COMMON
-#undef  CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES
+#undef CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES
 #define CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES 3
 #define CONFIG_CHARGE_MANAGER_EXTERNAL_POWER_LIMIT
 
@@ -89,7 +89,7 @@
 #define CONFIG_USB_PD_PORT_MAX_COUNT 2
 #define CONFIG_USB_PD_VBUS_DETECT_CHARGER
 #define CONFIG_USB_PD_TCPC_LOW_POWER
-#define CONFIG_USB_PD_TCPM_MUX  /* for both PS8751 and ANX3429 */
+#define CONFIG_USB_PD_TCPM_MUX /* for both PS8751 and ANX3429 */
 #define CONFIG_USB_PD_TCPM_ANX3429 /* Silicon on Reef is ANX3429 */
 #define CONFIG_USB_PD_TCPM_PS8751
 #define CONFIG_USB_PD_TCPM_TCPCI
@@ -117,8 +117,8 @@
 /* EC */
 #define CONFIG_ADC
 #define CONFIG_EXTPOWER_GPIO
-#undef   CONFIG_EXTPOWER_DEBOUNCE_MS
-#define  CONFIG_EXTPOWER_DEBOUNCE_MS 1000
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
+#define CONFIG_EXTPOWER_DEBOUNCE_MS 1000
 #define CONFIG_FPU
 #define CONFIG_HOSTCMD_FLASH_SPI_INFO
 #define CONFIG_I2C
@@ -145,7 +145,7 @@
 #define CONFIG_WIRELESS
 #define CONFIG_WIRELESS_SUSPEND EC_WIRELESS_SWITCH_WLAN_POWER
 #define CONFIG_WLAN_POWER_ACTIVE_LOW
-#define  WIRELESS_GPIO_WLAN_POWER GPIO_WIRELESS_GPIO_WLAN_POWER
+#define WIRELESS_GPIO_WLAN_POWER GPIO_WIRELESS_GPIO_WLAN_POWER
 #define CONFIG_PWR_STATE_DISCHARGE_FULL
 
 /*
@@ -171,7 +171,7 @@
 
 #define CONFIG_FLASH_SIZE_BYTES 524288
 #define CONFIG_SPI_FLASH_REGS
-#define CONFIG_SPI_FLASH_W25Q40	/* FIXME: Should be GD25LQ40? */
+#define CONFIG_SPI_FLASH_W25Q40 /* FIXME: Should be GD25LQ40? */
 
 /*
  * Enable 1 slot of secure temporary storage to support
@@ -186,17 +186,17 @@
 #define CONFIG_BOARD_PRE_INIT
 
 /* I2C ports */
-#define I2C_CONTROLLER_COUNT	4
-#define I2C_PORT_COUNT		5
-
-#define I2C_PORT_GYRO			MCHP_I2C_PORT6
-#define I2C_PORT_LID_ACCEL		MCHP_I2C_PORT7
-#define I2C_PORT_ALS			MCHP_I2C_PORT7
-#define I2C_PORT_BARO			MCHP_I2C_PORT7
-#define I2C_PORT_BATTERY		MCHP_I2C_PORT3
-#define I2C_PORT_CHARGER		MCHP_I2C_PORT3
+#define I2C_CONTROLLER_COUNT 4
+#define I2C_PORT_COUNT 5
+
+#define I2C_PORT_GYRO MCHP_I2C_PORT6
+#define I2C_PORT_LID_ACCEL MCHP_I2C_PORT7
+#define I2C_PORT_ALS MCHP_I2C_PORT7
+#define I2C_PORT_BARO MCHP_I2C_PORT7
+#define I2C_PORT_BATTERY MCHP_I2C_PORT3
+#define I2C_PORT_CHARGER MCHP_I2C_PORT3
 /* Accelerometer and Gyroscope are the same device. */
-#define I2C_PORT_ACCEL			I2C_PORT_GYRO
+#define I2C_PORT_ACCEL I2C_PORT_GYRO
 
 /* Sensors */
 #define CONFIG_MKBP_EVENT
@@ -222,7 +222,6 @@
 /* Depends on how fast the AP boots and typical ODRs */
 #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
 
-
 #ifndef __ASSEMBLER__
 
 #include "gpio_signal.h"
@@ -230,9 +229,9 @@
 
 /* ADC signal */
 enum adc_channel {
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC0 */
-	ADC_TEMP_SENSOR_AMB,		/* ADC1 */
-	ADC_BOARD_ID,			/* ADC2 */
+	ADC_TEMP_SENSOR_CHARGER, /* ADC0 */
+	ADC_TEMP_SENSOR_AMB, /* ADC1 */
+	ADC_BOARD_ID, /* ADC2 */
 	ADC_CH_COUNT
 };
 
@@ -271,7 +270,7 @@ enum sensor_id {
 	BASE_GYRO,
 	BASE_MAG,
 	BASE_BARO,
-	LID_ALS,	/* firmware-reef-9042.B doesn't have this */
+	LID_ALS, /* firmware-reef-9042.B doesn't have this */
 	SENSOR_COUNT,
 };
 
@@ -294,16 +293,16 @@ enum reef_board_version {
  * delay to turn on the power supply max is ~16ms.
  * delay to turn off the power supply max is about ~180ms.
  */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 
 /* delay to turn on/off vconn */
 
 /* Define typical operating power and max power */
 #define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       45000
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_VOLTAGE_MV     20000
+#define PD_MAX_POWER_MW 45000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Reset PD MCU */
 void board_reset_pd_mcu(void);
diff --git a/board/reef_mchp/build.mk b/board/reef_mchp/build.mk
index 19fffbaf0d..afc530837e 100644
--- a/board/reef_mchp/build.mk
+++ b/board/reef_mchp/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/reef_mchp/ec.tasklist b/board/reef_mchp/ec.tasklist
index adf63fae62..8611d09301 100644
--- a/board/reef_mchp/ec.tasklist
+++ b/board/reef_mchp/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/reef_mchp/gpio.inc b/board/reef_mchp/gpio.inc
index 3274af3bff..9783649e25 100644
--- a/board/reef_mchp/gpio.inc
+++ b/board/reef_mchp/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/reef_mchp/led.c b/board/reef_mchp/led.c
index ca49fe4ed5..469758dc26 100644
--- a/board/reef_mchp/led.c
+++ b/board/reef_mchp/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -27,8 +27,7 @@
 #define LED_ON_1SEC_TICKS 1
 #define LED_ON_2SECS_TICKS 2
 
-const enum ec_led_id supported_led_ids[] = {
-			EC_LED_ID_BATTERY_LED};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -36,7 +35,7 @@ enum led_color {
 	LED_OFF = 0,
 	LED_BLUE,
 	LED_AMBER,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static int led_set_color_battery(enum led_color color)
@@ -113,16 +112,19 @@ static void led_set_battery(void)
 		} else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
 			/* Blink once every four seconds. */
 			led_set_color_battery(
-				(suspend_ticks % LED_TOTAL_4SECS_TICKS)
-				< LED_ON_1SEC_TICKS ? LED_AMBER : LED_OFF);
+				(suspend_ticks % LED_TOTAL_4SECS_TICKS) <
+						LED_ON_1SEC_TICKS ?
+					LED_AMBER :
+					LED_OFF);
 		} else {
 			led_set_color_battery(LED_OFF);
 		}
 		break;
 	case PWR_STATE_ERROR:
-		led_set_color_battery(
-			(battery_ticks % LED_TOTAL_2SECS_TICKS <
-			 LED_ON_1SEC_TICKS) ? LED_AMBER : LED_OFF);
+		led_set_color_battery((battery_ticks % LED_TOTAL_2SECS_TICKS <
+				       LED_ON_1SEC_TICKS) ?
+					      LED_AMBER :
+					      LED_OFF);
 		break;
 	case PWR_STATE_CHARGE_NEAR_FULL:
 		led_set_color_battery(LED_BLUE);
@@ -131,7 +133,9 @@ static void led_set_battery(void)
 		if (charge_get_flags() & CHARGE_FLAG_FORCE_IDLE)
 			led_set_color_battery(
 				(battery_ticks % LED_TOTAL_4SECS_TICKS <
-				 LED_ON_2SECS_TICKS) ? LED_AMBER : LED_BLUE);
+				 LED_ON_2SECS_TICKS) ?
+					LED_AMBER :
+					LED_BLUE);
 		else
 			led_set_color_battery(LED_BLUE);
 		break;
diff --git a/board/reef_mchp/usb_pd_policy.c b/board/reef_mchp/usb_pd_policy.c
index 90f44f8580..478f760989 100644
--- a/board/reef_mchp/usb_pd_policy.c
+++ b/board/reef_mchp/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,12 +25,12 @@
 
 #include "tfdp_chip.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT];
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5,
-							TYPEC_RP_1A5};
+static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5,
+							 TYPEC_RP_1A5 };
 
 int board_vbus_source_enabled(int port)
 {
@@ -41,7 +41,8 @@ static void board_vbus_update_source_current(int port)
 {
 	enum gpio_signal gpio = port ? GPIO_USB_C1_5V_EN : GPIO_USB_C0_5V_EN;
 	int flags = (vbus_rp[port] == TYPEC_RP_1A5 && vbus_en[port]) ?
-		(GPIO_INPUT | GPIO_PULL_UP) : (GPIO_OUTPUT | GPIO_PULL_UP);
+			    (GPIO_INPUT | GPIO_PULL_UP) :
+			    (GPIO_OUTPUT | GPIO_PULL_UP);
 
 	/*
 	 * Driving USB_Cx_5V_EN high, actually put a 16.5k resistance
diff --git a/board/sasuke/battery.c b/board/sasuke/battery.c
index ad7ea9c2fe..c06f88ddfd 100644
--- a/board/sasuke/battery.c
+++ b/board/sasuke/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -12,7 +12,7 @@
 #include "usb_pd.h"
 #include "util.h"
 
-#define CHARGING_CURRENT_REDUCE	4000
+#define CHARGING_CURRENT_REDUCE 4000
 /*
  * Battery info for all sasuke battery types. Note that the fields
  * start_charging_min/max and charging_min/max are not used for the charger.
@@ -152,7 +152,7 @@ static void reduce_input_voltage_when_full(void)
 	int port;
 
 	if (charge_get_percent() == 100 &&
-			chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
+	    chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
 		if (max_pd_voltage_mv != PD_VOLTAGE_WHEN_FULL) {
 			saved_input_voltage = max_pd_voltage_mv;
 			max_pd_voltage_mv = PD_VOLTAGE_WHEN_FULL;
@@ -168,5 +168,4 @@ static void reduce_input_voltage_when_full(void)
 			pd_set_external_voltage_limit(port, max_pd_voltage_mv);
 	}
 }
-DECLARE_HOOK(HOOK_SECOND, reduce_input_voltage_when_full,
-             HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_SECOND, reduce_input_voltage_when_full, HOOK_PRIO_DEFAULT);
diff --git a/board/sasuke/board.c b/board/sasuke/board.c
index 830c92eb47..ddd5279d62 100644
--- a/board/sasuke/board.c
+++ b/board/sasuke/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -42,8 +42,8 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 #define INT_RECHECK_US 5000
 
@@ -83,7 +83,6 @@ static void usb_c0_interrupt(enum gpio_signal s)
 
 	/* Check the line again in 5ms */
 	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-
 }
 
 /* C1 interrupt line shared by BC 1.2, TCPC, and charger */
@@ -118,7 +117,6 @@ static void sub_usb_c1_interrupt(enum gpio_signal s)
 
 	/* Check the line again in 5ms */
 	hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
-
 }
 static void sub_hdmi_hpd_interrupt(enum gpio_signal s)
 {
@@ -164,22 +162,21 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* Thermistors */
 const struct temp_sensor_t temp_sensors[] = {
-        [TEMP_SENSOR_1] = {.name = "Memory",
-                           .type = TEMP_SENSOR_TYPE_BOARD,
-                           .read = get_temp_3v3_51k1_47k_4050b,
-                           .idx = ADC_TEMP_SENSOR_1},
-        [TEMP_SENSOR_2] = {.name = "Charger",
-                           .type = TEMP_SENSOR_TYPE_BOARD,
-                           .read = get_temp_3v3_51k1_47k_4050b,
-                           .idx = ADC_TEMP_SENSOR_2},
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Charger",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
-
 static int board_id = -1;
 static int mux_c1 = SSFC_USB_SS_MUX_DEFAULT;
 
-extern const struct usb_mux usbc0_retimer;
+extern const struct usb_mux_chain usbc0_retimer;
 extern const struct usb_mux usbmux_ps8743;
 
 void board_init(void)
@@ -191,16 +188,17 @@ void board_init(void)
 
 	if (get_cbi_fw_config_db() == DB_1A_HDMI) {
 		/* Disable i2c on HDMI pins */
-		gpio_config_pin(MODULE_I2C,
-				GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL, 0);
-		gpio_config_pin(MODULE_I2C,
-				GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL, 0);
+		gpio_config_pin(MODULE_I2C, GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL,
+				0);
+		gpio_config_pin(MODULE_I2C, GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL,
+				0);
 
 		/* Set HDMI and sub-rail enables to output */
 		gpio_set_flags(GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL,
 			       chipset_in_state(CHIPSET_STATE_ON) ?
-						GPIO_ODR_LOW : GPIO_ODR_HIGH);
-		gpio_set_flags(GPIO_SUB_C1_INT_EN_RAILS_ODL,   GPIO_ODR_HIGH);
+				       GPIO_ODR_LOW :
+				       GPIO_ODR_HIGH);
+		gpio_set_flags(GPIO_SUB_C1_INT_EN_RAILS_ODL, GPIO_ODR_HIGH);
 
 		/* Select HDMI option */
 		gpio_set_level(GPIO_HDMI_SEL_L, 0);
@@ -209,8 +207,7 @@ void board_init(void)
 		gpio_enable_interrupt(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL);
 	} else {
 		/* Set SDA as an input */
-		gpio_set_flags(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL,
-			       GPIO_INPUT);
+		gpio_set_flags(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL, GPIO_INPUT);
 
 		/* Enable C1 interrupts */
 		gpio_enable_interrupt(GPIO_SUB_C1_INT_EN_RAILS_ODL);
@@ -229,18 +226,19 @@ void board_init(void)
 			board_id = val;
 			if (board_id == 2) {
 				nb7v904m_lpm_disable = 1;
-				nb7v904m_set_aux_ch_switch(&usbc0_retimer,
-						NB7V904M_AUX_CH_FLIPPED);
+				nb7v904m_set_aux_ch_switch(
+					usbc0_retimer.mux,
+					NB7V904M_AUX_CH_FLIPPED);
 			}
 		}
 	}
 
 	mux_c1 = get_cbi_ssfc_usb_ss_mux();
 
-	if (mux_c1 == SSFC_USB_SS_MUX_PS8743)
-		memcpy(&usb_muxes[1],
-				&usbmux_ps8743,
-				sizeof(struct usb_mux));
+	if (mux_c1 == SSFC_USB_SS_MUX_PS8743) {
+		usb_muxes[1].mux = &usbmux_ps8743;
+		usb_muxes[1].next = NULL;
+	}
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
@@ -302,10 +300,9 @@ __override void board_power_5v_enable(int enable)
 		gpio_set_level(GPIO_SUB_C1_INT_EN_RAILS_ODL, !enable);
 	} else {
 		if (isl923x_set_comparator_inversion(1, !!enable))
-			CPRINTS("Failed to %sable sub rails!", enable ?
-								"en" : "dis");
+			CPRINTS("Failed to %sable sub rails!",
+				enable ? "en" : "dis");
 	}
-
 }
 
 __override uint8_t board_get_usb_pd_port_count(void)
@@ -330,13 +327,11 @@ int board_is_sourcing_vbus(int port)
 
 	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
 	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
-
 }
 
 int board_set_active_charge_port(int port)
 {
-	int is_real_port = (port >= 0 &&
-			    port < board_get_usb_pd_port_count());
+	int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count());
 	int i;
 	int old_port;
 
@@ -400,8 +395,8 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
 
@@ -421,9 +416,8 @@ __override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
 	raa489000_set_output_current(port, rp);
 }
 
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
+__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+				       int *ki_div, int *kd, int *kd_div)
 {
 	*kp = 1;
 	*kp_div = 20;
@@ -489,24 +483,30 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 };
 
 static int board_nb7v904m_mux_set_c0(const struct usb_mux *me,
-						mux_state_t mux_state);
+				     mux_state_t mux_state);
 static int board_nb7v904m_mux_set(const struct usb_mux *me,
-						mux_state_t mux_state);
+				  mux_state_t mux_state);
 static int ps8743_tune_mux(const struct usb_mux *me);
 
-const struct usb_mux usbc0_retimer = {
-	.usb_port = 0,
-	.i2c_port = I2C_PORT_USB_C0,
-	.i2c_addr_flags = NB7V904M_I2C_ADDR0,
-	.driver = &nb7v904m_usb_redriver_drv,
-	.board_set = &board_nb7v904m_mux_set_c0,
+const struct usb_mux_chain usbc0_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = 0,
+			.i2c_port = I2C_PORT_USB_C0,
+			.i2c_addr_flags = NB7V904M_I2C_ADDR0,
+			.driver = &nb7v904m_usb_redriver_drv,
+			.board_set = &board_nb7v904m_mux_set_c0,
+		},
 };
-const struct usb_mux usbc1_retimer = {
-	.usb_port = 1,
-	.i2c_port = I2C_PORT_SUB_USB_C1,
-	.i2c_addr_flags = NB7V904M_I2C_ADDR0,
-	.driver = &nb7v904m_usb_redriver_drv,
-	.board_set = &board_nb7v904m_mux_set,
+const struct usb_mux_chain usbc1_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = 1,
+			.i2c_port = I2C_PORT_SUB_USB_C1,
+			.i2c_addr_flags = NB7V904M_I2C_ADDR0,
+			.driver = &nb7v904m_usb_redriver_drv,
+			.board_set = &board_nb7v904m_mux_set,
+		},
 };
 
 const struct usb_mux usbmux_ps8743 = {
@@ -517,35 +517,40 @@ const struct usb_mux usbmux_ps8743 = {
 	.board_init = &ps8743_tune_mux,
 };
 
-struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
-		.driver = &pi3usb3x532_usb_mux_driver,
-		.next_mux = &usbc0_retimer,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
+				.driver = &pi3usb3x532_usb_mux_driver,
+			},
+		.next = &usbc0_retimer,
 	},
 	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
-		.driver = &pi3usb3x532_usb_mux_driver,
-		.next_mux = &usbc1_retimer,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_SUB_USB_C1,
+				.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
+				.driver = &pi3usb3x532_usb_mux_driver,
+			},
+		.next = &usbc1_retimer,
 	}
 };
 /* USB Mux C1 : board_init of PS8743 */
 static int ps8743_tune_mux(const struct usb_mux *me)
 {
-	ps8743_tune_usb_eq(me,
-			PS8743_USB_EQ_TX_3_6_DB,
-			PS8743_USB_EQ_RX_16_0_DB);
+	ps8743_tune_usb_eq(me, PS8743_USB_EQ_TX_3_6_DB,
+			   PS8743_USB_EQ_RX_16_0_DB);
 
 	return EC_SUCCESS;
 }
 
 /* USB Mux C0 */
 static int board_nb7v904m_mux_set_c0(const struct usb_mux *me,
-						mux_state_t mux_state)
+				     mux_state_t mux_state)
 {
 	int rv = EC_SUCCESS;
 	int flipped = !!(mux_state & USB_PD_MUX_POLARITY_INVERTED);
@@ -563,79 +568,74 @@ static int board_nb7v904m_mux_set_c0(const struct usb_mux *me,
 		if (mux_state & USB_PD_MUX_DP_ENABLED) {
 			/* USB with DP */
 			if (flipped) {
-				rv |= nb7v904m_tune_usb_set_eq(me,
-							NB7V904M_CH_A_EQ_10_DB,
-							NB7V904M_CH_B_EQ_0_DB,
-							NB7V904M_CH_C_EQ_2_DB,
-							NB7V904M_CH_D_EQ_2_DB);
-				rv |= nb7v904m_tune_usb_flat_gain(me,
-							NB7V904M_CH_A_GAIN_0_DB,
-							NB7V904M_CH_B_GAIN_1P5_DB,
-							NB7V904M_CH_C_GAIN_0_DB,
-							NB7V904M_CH_D_GAIN_0_DB);
-				rv |= nb7v904m_set_loss_profile_match(me,
-							NB7V904M_LOSS_PROFILE_A,
-							NB7V904M_LOSS_PROFILE_A,
-							NB7V904M_LOSS_PROFILE_C,
-							NB7V904M_LOSS_PROFILE_C);
-			}
-			else {
-				rv |= nb7v904m_tune_usb_set_eq(me,
-							NB7V904M_CH_A_EQ_2_DB,
-							NB7V904M_CH_B_EQ_2_DB,
-							NB7V904M_CH_C_EQ_0_DB,
-							NB7V904M_CH_D_EQ_10_DB);
-				rv |= nb7v904m_tune_usb_flat_gain(me,
-							NB7V904M_CH_A_GAIN_0_DB,
-							NB7V904M_CH_B_GAIN_0_DB,
-							NB7V904M_CH_C_GAIN_1P5_DB,
-							NB7V904M_CH_D_GAIN_0_DB);
-				rv |= nb7v904m_set_loss_profile_match(me,
-							NB7V904M_LOSS_PROFILE_C,
-							NB7V904M_LOSS_PROFILE_C,
-							NB7V904M_LOSS_PROFILE_A,
-							NB7V904M_LOSS_PROFILE_A);
+				rv |= nb7v904m_tune_usb_set_eq(
+					me, NB7V904M_CH_A_EQ_10_DB,
+					NB7V904M_CH_B_EQ_0_DB,
+					NB7V904M_CH_C_EQ_2_DB,
+					NB7V904M_CH_D_EQ_2_DB);
+				rv |= nb7v904m_tune_usb_flat_gain(
+					me, NB7V904M_CH_A_GAIN_0_DB,
+					NB7V904M_CH_B_GAIN_1P5_DB,
+					NB7V904M_CH_C_GAIN_0_DB,
+					NB7V904M_CH_D_GAIN_0_DB);
+				rv |= nb7v904m_set_loss_profile_match(
+					me, NB7V904M_LOSS_PROFILE_A,
+					NB7V904M_LOSS_PROFILE_A,
+					NB7V904M_LOSS_PROFILE_C,
+					NB7V904M_LOSS_PROFILE_C);
+			} else {
+				rv |= nb7v904m_tune_usb_set_eq(
+					me, NB7V904M_CH_A_EQ_2_DB,
+					NB7V904M_CH_B_EQ_2_DB,
+					NB7V904M_CH_C_EQ_0_DB,
+					NB7V904M_CH_D_EQ_10_DB);
+				rv |= nb7v904m_tune_usb_flat_gain(
+					me, NB7V904M_CH_A_GAIN_0_DB,
+					NB7V904M_CH_B_GAIN_0_DB,
+					NB7V904M_CH_C_GAIN_1P5_DB,
+					NB7V904M_CH_D_GAIN_0_DB);
+				rv |= nb7v904m_set_loss_profile_match(
+					me, NB7V904M_LOSS_PROFILE_C,
+					NB7V904M_LOSS_PROFILE_C,
+					NB7V904M_LOSS_PROFILE_A,
+					NB7V904M_LOSS_PROFILE_A);
 			}
 		} else {
 			/* USB only */
 			if (board_id == 2)
-				rv |= nb7v904m_set_aux_ch_switch(me,
-						NB7V904M_AUX_CH_FLIPPED);
+				rv |= nb7v904m_set_aux_ch_switch(
+					me, NB7V904M_AUX_CH_FLIPPED);
 
 			rv |= nb7v904m_tune_usb_set_eq(me,
-						NB7V904M_CH_A_EQ_10_DB,
-						NB7V904M_CH_B_EQ_0_DB,
-						NB7V904M_CH_C_EQ_0_DB,
-						NB7V904M_CH_D_EQ_10_DB);
-			rv |= nb7v904m_tune_usb_flat_gain(me,
-						NB7V904M_CH_A_GAIN_0_DB,
-						NB7V904M_CH_B_GAIN_1P5_DB,
-						NB7V904M_CH_C_GAIN_1P5_DB,
-						NB7V904M_CH_D_GAIN_0_DB);
-			rv |= nb7v904m_set_loss_profile_match(me,
-						NB7V904M_LOSS_PROFILE_A,
-						NB7V904M_LOSS_PROFILE_A,
-						NB7V904M_LOSS_PROFILE_A,
-						NB7V904M_LOSS_PROFILE_A);
+						       NB7V904M_CH_A_EQ_10_DB,
+						       NB7V904M_CH_B_EQ_0_DB,
+						       NB7V904M_CH_C_EQ_0_DB,
+						       NB7V904M_CH_D_EQ_10_DB);
+			rv |= nb7v904m_tune_usb_flat_gain(
+				me, NB7V904M_CH_A_GAIN_0_DB,
+				NB7V904M_CH_B_GAIN_1P5_DB,
+				NB7V904M_CH_C_GAIN_1P5_DB,
+				NB7V904M_CH_D_GAIN_0_DB);
+			rv |= nb7v904m_set_loss_profile_match(
+				me, NB7V904M_LOSS_PROFILE_A,
+				NB7V904M_LOSS_PROFILE_A,
+				NB7V904M_LOSS_PROFILE_A,
+				NB7V904M_LOSS_PROFILE_A);
 		}
 
 	} else if (mux_state & USB_PD_MUX_DP_ENABLED) {
 		/* 4 lanes DP */
-		rv |= nb7v904m_tune_usb_set_eq(me,
-					NB7V904M_CH_A_EQ_2_DB,
-					NB7V904M_CH_B_EQ_2_DB,
-					NB7V904M_CH_C_EQ_2_DB,
-					NB7V904M_CH_D_EQ_2_DB);
-		rv |= nb7v904m_tune_usb_flat_gain(me,
-					NB7V904M_CH_A_GAIN_0_DB,
-					NB7V904M_CH_B_GAIN_0_DB,
-					NB7V904M_CH_C_GAIN_0_DB,
-					NB7V904M_CH_D_GAIN_0_DB);
-		rv |= nb7v904m_set_loss_profile_match(me,
-					NB7V904M_LOSS_PROFILE_C,
-					NB7V904M_LOSS_PROFILE_C,
-					NB7V904M_LOSS_PROFILE_C,
-					NB7V904M_LOSS_PROFILE_C);
+		rv |= nb7v904m_tune_usb_set_eq(me, NB7V904M_CH_A_EQ_2_DB,
+					       NB7V904M_CH_B_EQ_2_DB,
+					       NB7V904M_CH_C_EQ_2_DB,
+					       NB7V904M_CH_D_EQ_2_DB);
+		rv |= nb7v904m_tune_usb_flat_gain(me, NB7V904M_CH_A_GAIN_0_DB,
+						  NB7V904M_CH_B_GAIN_0_DB,
+						  NB7V904M_CH_C_GAIN_0_DB,
+						  NB7V904M_CH_D_GAIN_0_DB);
+		rv |= nb7v904m_set_loss_profile_match(
+			me, NB7V904M_LOSS_PROFILE_C, NB7V904M_LOSS_PROFILE_C,
+			NB7V904M_LOSS_PROFILE_C, NB7V904M_LOSS_PROFILE_C);
 	}
 
 	return rv;
@@ -643,7 +643,7 @@ static int board_nb7v904m_mux_set_c0(const struct usb_mux *me,
 
 /* USB Mux */
 static int board_nb7v904m_mux_set(const struct usb_mux *me,
-						mux_state_t mux_state)
+				  mux_state_t mux_state)
 {
 	int rv = EC_SUCCESS;
 	int flipped = !!(mux_state & USB_PD_MUX_POLARITY_INVERTED);
@@ -652,75 +652,70 @@ static int board_nb7v904m_mux_set(const struct usb_mux *me,
 		/* USB with DP */
 		if (mux_state & USB_PD_MUX_DP_ENABLED) {
 			if (flipped) {
-				rv |= nb7v904m_tune_usb_set_eq(me,
-							NB7V904M_CH_A_EQ_10_DB,
-							NB7V904M_CH_ALL_SKIP_EQ,
-							NB7V904M_CH_ALL_SKIP_EQ,
-							NB7V904M_CH_D_EQ_4_DB);
-				rv |= nb7v904m_tune_usb_flat_gain(me,
-							NB7V904M_CH_ALL_SKIP_GAIN,
-							NB7V904M_CH_B_GAIN_3P5_DB,
-							NB7V904M_CH_C_GAIN_0_DB,
-							NB7V904M_CH_ALL_SKIP_GAIN);
-				rv |= nb7v904m_set_loss_profile_match(me,
-							NB7V904M_LOSS_PROFILE_A,
-							NB7V904M_LOSS_PROFILE_A,
-							NB7V904M_LOSS_PROFILE_D,
-							NB7V904M_LOSS_PROFILE_D);
-			}
-			else {
-				rv |= nb7v904m_tune_usb_set_eq(me,
-							NB7V904M_CH_A_EQ_4_DB,
-							NB7V904M_CH_ALL_SKIP_EQ,
-							NB7V904M_CH_ALL_SKIP_EQ,
-							NB7V904M_CH_D_EQ_10_DB);
-				rv |= nb7v904m_tune_usb_flat_gain(me,
-							NB7V904M_CH_ALL_SKIP_GAIN,
-							NB7V904M_CH_B_GAIN_0_DB,
-							NB7V904M_CH_C_GAIN_3P5_DB,
-							NB7V904M_CH_ALL_SKIP_GAIN);
-				rv |= nb7v904m_set_loss_profile_match(me,
-							NB7V904M_LOSS_PROFILE_D,
-							NB7V904M_LOSS_PROFILE_D,
-							NB7V904M_LOSS_PROFILE_A,
-							NB7V904M_LOSS_PROFILE_A);
+				rv |= nb7v904m_tune_usb_set_eq(
+					me, NB7V904M_CH_A_EQ_10_DB,
+					NB7V904M_CH_ALL_SKIP_EQ,
+					NB7V904M_CH_ALL_SKIP_EQ,
+					NB7V904M_CH_D_EQ_4_DB);
+				rv |= nb7v904m_tune_usb_flat_gain(
+					me, NB7V904M_CH_ALL_SKIP_GAIN,
+					NB7V904M_CH_B_GAIN_3P5_DB,
+					NB7V904M_CH_C_GAIN_0_DB,
+					NB7V904M_CH_ALL_SKIP_GAIN);
+				rv |= nb7v904m_set_loss_profile_match(
+					me, NB7V904M_LOSS_PROFILE_A,
+					NB7V904M_LOSS_PROFILE_A,
+					NB7V904M_LOSS_PROFILE_D,
+					NB7V904M_LOSS_PROFILE_D);
+			} else {
+				rv |= nb7v904m_tune_usb_set_eq(
+					me, NB7V904M_CH_A_EQ_4_DB,
+					NB7V904M_CH_ALL_SKIP_EQ,
+					NB7V904M_CH_ALL_SKIP_EQ,
+					NB7V904M_CH_D_EQ_10_DB);
+				rv |= nb7v904m_tune_usb_flat_gain(
+					me, NB7V904M_CH_ALL_SKIP_GAIN,
+					NB7V904M_CH_B_GAIN_0_DB,
+					NB7V904M_CH_C_GAIN_3P5_DB,
+					NB7V904M_CH_ALL_SKIP_GAIN);
+				rv |= nb7v904m_set_loss_profile_match(
+					me, NB7V904M_LOSS_PROFILE_D,
+					NB7V904M_LOSS_PROFILE_D,
+					NB7V904M_LOSS_PROFILE_A,
+					NB7V904M_LOSS_PROFILE_A);
 			}
 		} else {
 			/* USB only */
 			rv |= nb7v904m_tune_usb_set_eq(me,
-						NB7V904M_CH_A_EQ_10_DB,
-						NB7V904M_CH_ALL_SKIP_EQ,
-						NB7V904M_CH_ALL_SKIP_EQ,
-						NB7V904M_CH_D_EQ_10_DB);
-			rv |= nb7v904m_tune_usb_flat_gain(me,
-						NB7V904M_CH_ALL_SKIP_GAIN,
-						NB7V904M_CH_B_GAIN_3P5_DB,
-						NB7V904M_CH_C_GAIN_3P5_DB,
-						NB7V904M_CH_ALL_SKIP_GAIN);
-			rv |= nb7v904m_set_loss_profile_match(me,
-						NB7V904M_LOSS_PROFILE_A,
-						NB7V904M_LOSS_PROFILE_A,
-						NB7V904M_LOSS_PROFILE_A,
-						NB7V904M_LOSS_PROFILE_A);
+						       NB7V904M_CH_A_EQ_10_DB,
+						       NB7V904M_CH_ALL_SKIP_EQ,
+						       NB7V904M_CH_ALL_SKIP_EQ,
+						       NB7V904M_CH_D_EQ_10_DB);
+			rv |= nb7v904m_tune_usb_flat_gain(
+				me, NB7V904M_CH_ALL_SKIP_GAIN,
+				NB7V904M_CH_B_GAIN_3P5_DB,
+				NB7V904M_CH_C_GAIN_3P5_DB,
+				NB7V904M_CH_ALL_SKIP_GAIN);
+			rv |= nb7v904m_set_loss_profile_match(
+				me, NB7V904M_LOSS_PROFILE_A,
+				NB7V904M_LOSS_PROFILE_A,
+				NB7V904M_LOSS_PROFILE_A,
+				NB7V904M_LOSS_PROFILE_A);
 		}
 
 	} else if (mux_state & USB_PD_MUX_DP_ENABLED) {
 		/* 4 lanes DP */
-		rv |= nb7v904m_tune_usb_set_eq(me,
-					NB7V904M_CH_A_EQ_4_DB,
-					NB7V904M_CH_ALL_SKIP_EQ,
-					NB7V904M_CH_ALL_SKIP_EQ,
-					NB7V904M_CH_D_EQ_4_DB);
-		rv |= nb7v904m_tune_usb_flat_gain(me,
-					NB7V904M_CH_ALL_SKIP_GAIN,
-					NB7V904M_CH_B_GAIN_0_DB,
-					NB7V904M_CH_C_GAIN_0_DB,
-					NB7V904M_CH_ALL_SKIP_GAIN);
-		rv |= nb7v904m_set_loss_profile_match(me,
-					NB7V904M_LOSS_PROFILE_D,
-					NB7V904M_LOSS_PROFILE_D,
-					NB7V904M_LOSS_PROFILE_D,
-					NB7V904M_LOSS_PROFILE_D);
+		rv |= nb7v904m_tune_usb_set_eq(me, NB7V904M_CH_A_EQ_4_DB,
+					       NB7V904M_CH_ALL_SKIP_EQ,
+					       NB7V904M_CH_ALL_SKIP_EQ,
+					       NB7V904M_CH_D_EQ_4_DB);
+		rv |= nb7v904m_tune_usb_flat_gain(me, NB7V904M_CH_ALL_SKIP_GAIN,
+						  NB7V904M_CH_B_GAIN_0_DB,
+						  NB7V904M_CH_C_GAIN_0_DB,
+						  NB7V904M_CH_ALL_SKIP_GAIN);
+		rv |= nb7v904m_set_loss_profile_match(
+			me, NB7V904M_LOSS_PROFILE_D, NB7V904M_LOSS_PROFILE_D,
+			NB7V904M_LOSS_PROFILE_D, NB7V904M_LOSS_PROFILE_D);
 	}
 
 	return rv;
@@ -748,7 +743,7 @@ uint16_t tcpc_get_alert_status(void)
 	}
 
 	if (board_get_usb_pd_port_count() > 1 &&
-				!gpio_get_level(GPIO_SUB_C1_INT_EN_RAILS_ODL)) {
+	    !gpio_get_level(GPIO_SUB_C1_INT_EN_RAILS_ODL)) {
 		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
 			/* TCPCI spec Rev 1.0 says to ignore bits 14:12. */
 			if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0))
@@ -778,8 +773,8 @@ static const struct ec_response_keybd_config keybd1 = {
 	},
 	/* No function keys, no numeric keypad and no screenlock key */
 };
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	/*
 	 * Future boards should use fw_config if needed.
diff --git a/board/sasuke/board.h b/board/sasuke/board.h
index 4d70cda5ab..64c830df0f 100644
--- a/board/sasuke/board.h
+++ b/board/sasuke/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,13 +23,16 @@
 
 /* Charger */
 #define CONFIG_CHARGER_RAA489000
+#define PD_MAX_VOLTAGE_MV 20000
 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 #define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */
+#define CONFIG_OCPC_DEF_RBATT_MOHMS               \
+	22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \
+	    */
 #define CONFIG_OCPC
 #define CONFIG_CHARGER_PROFILE_OVERRIDE
 #define CONFIG_CHARGE_RAMP_HW
-#undef  CONFIG_CHARGER_SINGLE_CHIP
+#undef CONFIG_CHARGER_SINGLE_CHIP
 
 #define CONFIG_BATTERY_CHECK_CHARGE_TEMP_LIMITS
 
@@ -50,9 +53,8 @@
 #define GPIO_BAT_LED_GREEN_L GPIO_LED_G_ODL
 #define GPIO_PWR_LED_BLUE_L GPIO_LED_B_ODL
 
-
 /* PWM */
-#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
+#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */
 
 /* Thermistors */
 #define CONFIG_TEMP_SENSOR
@@ -85,10 +87,10 @@
 #undef PD_POWER_SUPPLY_TURN_OFF_DELAY
 #undef CONFIG_USBC_VCONN_SWAP_DELAY_US
 /* 20% margin added for these timings */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	13080	/* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	16080	/* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 13080 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 16080 /* us */
 #undef CONFIG_USBC_VCONN_SWAP_DELAY_US
-#define CONFIG_USBC_VCONN_SWAP_DELAY_US		787	/* us */
+#define CONFIG_USBC_VCONN_SWAP_DELAY_US 787 /* us */
 
 /* USB Type A Features */
 #define USB_PORT_COUNT 1
@@ -101,16 +103,16 @@
 #define GPIO_USB1_ILIM_SEL GPIO_EN_USB_A0_5V_SUB
 
 /* I2C configuration */
-#define I2C_PORT_EEPROM     NPCX_I2C_PORT7_0
-#define I2C_PORT_BATTERY    NPCX_I2C_PORT5_0
-#define I2C_PORT_SENSOR     NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0     NPCX_I2C_PORT1_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
 #define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_MUX    I2C_PORT_USB_C0
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0
 /* TODO(b:147440290): Need to handle multiple charger ICs */
-#define I2C_PORT_CHARGER    I2C_PORT_USB_C0
+#define I2C_PORT_CHARGER I2C_PORT_USB_C0
 
-#define I2C_PORT_ACCEL      I2C_PORT_SENSOR
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
 
 #define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */
 
@@ -142,17 +144,13 @@ enum chg_id {
 	CHARGER_NUM,
 };
 
-enum temp_sensor_id {
-        TEMP_SENSOR_1,
-        TEMP_SENSOR_2,
-        TEMP_SENSOR_COUNT
-};
+enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT };
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_1,     /* ADC0 */
-	ADC_TEMP_SENSOR_2,     /* ADC1 */
-	ADC_SUB_ANALOG,	       /* ADC2 */
-	ADC_VSNS_PP3300_A,     /* ADC9 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
+	ADC_SUB_ANALOG, /* ADC2 */
+	ADC_VSNS_PP3300_A, /* ADC9 */
 	ADC_CH_COUNT
 };
 
diff --git a/board/sasuke/build.mk b/board/sasuke/build.mk
index cd002a20e7..1531d1f3ae 100644
--- a/board/sasuke/build.mk
+++ b/board/sasuke/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/sasuke/cbi_ssfc.c b/board/sasuke/cbi_ssfc.c
index 61db1ef4f6..4f726ce6a3 100644
--- a/board/sasuke/cbi_ssfc.c
+++ b/board/sasuke/cbi_ssfc.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,15 +27,15 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
 
 enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
 {
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
 }
 
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
 {
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
 }
 
 enum ec_ssfc_usb_ss_mux get_cbi_ssfc_usb_ss_mux(void)
 {
-	return (enum ec_ssfc_usb_ss_mux) cached_ssfc.usb_ss_mux;
+	return (enum ec_ssfc_usb_ss_mux)cached_ssfc.usb_ss_mux;
 }
diff --git a/board/sasuke/cbi_ssfc.h b/board/sasuke/cbi_ssfc.h
index af47a1c2cd..7cf6e954a1 100644
--- a/board/sasuke/cbi_ssfc.h
+++ b/board/sasuke/cbi_ssfc.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -73,5 +73,4 @@ enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
  */
 enum ec_ssfc_usb_ss_mux get_cbi_ssfc_usb_ss_mux(void);
 
-
 #endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/sasuke/ec.tasklist b/board/sasuke/ec.tasklist
index a867bdbbae..17d4f989b3 100644
--- a/board/sasuke/ec.tasklist
+++ b/board/sasuke/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/sasuke/gpio.inc b/board/sasuke/gpio.inc
index 4b970f9798..46069c35eb 100644
--- a/board/sasuke/gpio.inc
+++ b/board/sasuke/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/sasuke/led.c b/board/sasuke/led.c
index 37cbad75e5..8ccce58d4c 100644
--- a/board/sasuke/led.c
+++ b/board/sasuke/led.c
@@ -1,8 +1,8 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
- * Power and battery LED control for sasuke 
+ * Power and battery LED control for sasuke
  */
 
 #include "chipset.h"
@@ -12,8 +12,8 @@
 #include "led_common.h"
 #include "led_onoff_states.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
 __override const int led_charge_lvl_1 = 1;
 
@@ -21,33 +21,36 @@ __override const int led_charge_lvl_2 = 100;
 
 /* sasuke : There are 3 leds for AC, Battery and Power */
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC},
-       					{LED_OFF, 1 * LED_ONE_SEC} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED, 0.5 * LED_ONE_SEC},
-					{LED_OFF, 0.5 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC},
-					{LED_OFF, 1 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     1 * LED_ONE_SEC },
+					   { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_GREEN,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED,
+					    0.5 * LED_ONE_SEC },
+					  { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					 { LED_OFF, 1 * LED_ONE_SEC } },
+	};
 
 __override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_BLUE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -55,14 +58,13 @@ __override void led_set_color_power(enum ec_led_colors color)
 {
 	/* Don't set led if led_auto_control is disabled. */
 	if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) ||
-                !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
+	    !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
 		return;
-        }
+	}
 
-	if (color == EC_LED_COLOR_BLUE)
-	{
-                gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
-                gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
+	if (color == EC_LED_COLOR_BLUE) {
+		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
 		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_ON_LVL);
 	} else {
 		/* LED_OFF and unsupported colors */
@@ -74,17 +76,16 @@ __override void led_set_color_battery(enum ec_led_colors color)
 {
 	/* Don't set led if led_auto_control is disabled. */
 	if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) ||
-                !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
+	    !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
 		return;
-        }
+	}
 
 	/* Battery leds must be turn off when blue led is on
 	 * because casta has 3-in-1 led.
 	 */
-	if(!gpio_get_level(GPIO_PWR_LED_BLUE_L))
-	{
+	if (!gpio_get_level(GPIO_PWR_LED_BLUE_L)) {
 		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); /*red*/
-                gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); /*green*/
+		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); /*green*/
 		return;
 	}
 
@@ -118,10 +119,13 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 {
 	if (led_id == EC_LED_ID_BATTERY_LED) {
 		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_OFF_LVL);
-		gpio_set_level(GPIO_BAT_LED_GREEN_L, !brightness[EC_LED_COLOR_GREEN]);
-		gpio_set_level(GPIO_BAT_LED_RED_L, !brightness[EC_LED_COLOR_RED]);
+		gpio_set_level(GPIO_BAT_LED_GREEN_L,
+			       !brightness[EC_LED_COLOR_GREEN]);
+		gpio_set_level(GPIO_BAT_LED_RED_L,
+			       !brightness[EC_LED_COLOR_RED]);
 	} else if (led_id == EC_LED_ID_POWER_LED) {
-		gpio_set_level(GPIO_PWR_LED_BLUE_L, !brightness[EC_LED_COLOR_BLUE]);
+		gpio_set_level(GPIO_PWR_LED_BLUE_L,
+			       !brightness[EC_LED_COLOR_BLUE]);
 		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
 		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
 	}
diff --git a/board/sasuke/usb_pd_policy.c b/board/sasuke/usb_pd_policy.c
index 3190595596..23166f7fca 100644
--- a/board/sasuke/usb_pd_policy.c
+++ b/board/sasuke/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,8 @@
 #include "driver/tcpm/tcpci.h"
 #include "usb_pd.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
diff --git a/board/sasukette/battery.c b/board/sasukette/battery.c
index 652c04a651..7a4670816e 100644
--- a/board/sasukette/battery.c
+++ b/board/sasukette/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -12,8 +12,8 @@
 #include "common.h"
 #include "util.h"
 
-#define CHARGING_VOLTAGE_MV_SAFE        8400
-#define CHARGING_CURRENT_MA_SAFE        1500
+#define CHARGING_VOLTAGE_MV_SAFE 8400
+#define CHARGING_CURRENT_MA_SAFE 1500
 
 /*
  * Battery info for all sasukette battery types. Note that the fields
@@ -165,13 +165,13 @@ int charger_profile_override(struct charge_state_data *curr)
 }
 
 enum ec_status charger_profile_override_get_param(uint32_t param,
-				uint32_t *value)
+						  uint32_t *value)
 {
 	return EC_RES_INVALID_PARAM;
 }
 
 enum ec_status charger_profile_override_set_param(uint32_t param,
-				uint32_t value)
+						  uint32_t value)
 {
 	return EC_RES_INVALID_PARAM;
 }
diff --git a/board/sasukette/board.c b/board/sasukette/board.c
index cbc786b892..e45213a63a 100644
--- a/board/sasukette/board.c
+++ b/board/sasukette/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -41,7 +41,7 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
 
 #define INT_RECHECK_US 5000
 
@@ -90,45 +90,35 @@ static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH0
-	},
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH2
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH3
-	},
-	[ADC_TEMP_SENSOR_3] = {
-		.name = "TEMP_SENSOR3",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH15
-	},
+	[ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH0 },
+	[ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH2 },
+	[ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH3 },
+	[ADC_TEMP_SENSOR_3] = { .name = "TEMP_SENSOR3",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH15 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* BC 1.2 chips */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-		.flags = PI3USB9201_ALWAYS_POWERED,
-	}
-};
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = { {
+	.i2c_port = I2C_PORT_USB_C0,
+	.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	.flags = PI3USB9201_ALWAYS_POWERED,
+} };
 
 int pd_snk_is_vbus_provided(int port)
 {
@@ -136,13 +126,11 @@ int pd_snk_is_vbus_provided(int port)
 }
 
 /* Charger chips */
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,
-		.drv = &isl923x_drv,
-	}
-};
+const struct charger_config_t chg_chips[] = { {
+	.i2c_port = I2C_PORT_USB_C0,
+	.i2c_addr_flags = ISL923X_ADDR_FLAGS,
+	.drv = &isl923x_drv,
+} };
 
 /* TCPCs */
 const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
@@ -158,14 +146,15 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 };
 
 /* USB Muxes */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-	}
-};
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = 0,
+			.i2c_port = I2C_PORT_USB_C0,
+			.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+			.driver = &it5205_usb_mux_driver,
+		},
+} };
 
 static uint32_t board_id;
 
@@ -285,8 +274,7 @@ int board_is_sourcing_vbus(int port)
 
 int board_set_active_charge_port(int port)
 {
-	int is_real_port = (port >= 0 &&
-			    port < board_get_usb_pd_port_count());
+	int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count());
 	int i;
 	int old_port;
 
@@ -359,17 +347,17 @@ __override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
 
 /* Thermistors */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "Cpu",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_3},
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "Cpu",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
diff --git a/board/sasukette/board.h b/board/sasukette/board.h
index a1d987aaf3..44cb65239a 100644
--- a/board/sasukette/board.h
+++ b/board/sasukette/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -29,6 +29,7 @@
 
 /* Charger */
 #define CONFIG_CHARGER_RAA489000
+#define PD_MAX_VOLTAGE_MV 20000
 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 #define CONFIG_CHARGER_SENSE_RESISTOR 10
 #define CONFIG_CHARGER_SINGLE_CHIP
@@ -60,8 +61,8 @@
 #define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
 
 /* USB Mux and Retimer */
-#define CONFIG_USB_MUX_IT5205			/* C1: ITE Mux */
-#define I2C_PORT_USB_MUX I2C_PORT_USB_C0	/* Required for ITE Mux */
+#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */
 
 #ifndef __ASSEMBLER__
 
@@ -70,10 +71,10 @@
 
 /* ADC channels */
 enum adc_channel {
-	ADC_VSNS_PP3300_A,     /* ADC0 */
-	ADC_TEMP_SENSOR_1,     /* ADC2 */
-	ADC_TEMP_SENSOR_2,     /* ADC3 */
-	ADC_TEMP_SENSOR_3,     /* ADC15*/
+	ADC_VSNS_PP3300_A, /* ADC0 */
+	ADC_TEMP_SENSOR_1, /* ADC2 */
+	ADC_TEMP_SENSOR_2, /* ADC3 */
+	ADC_TEMP_SENSOR_3, /* ADC15*/
 	ADC_CH_COUNT
 };
 
diff --git a/board/sasukette/build.mk b/board/sasukette/build.mk
index 8167ca9966..01b890bf29 100644
--- a/board/sasukette/build.mk
+++ b/board/sasukette/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/sasukette/cbi_ssfc.c b/board/sasukette/cbi_ssfc.c
index c4b859f133..81f3ee0dad 100644
--- a/board/sasukette/cbi_ssfc.c
+++ b/board/sasukette/cbi_ssfc.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
 
 enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
 {
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
 }
 
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
 {
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
 }
diff --git a/board/sasukette/cbi_ssfc.h b/board/sasukette/cbi_ssfc.h
index 935049b6ae..bf8853a43a 100644
--- a/board/sasukette/cbi_ssfc.h
+++ b/board/sasukette/cbi_ssfc.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -56,5 +56,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
  */
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
 
-
 #endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/sasukette/ec.tasklist b/board/sasukette/ec.tasklist
index bb4d9c6a61..d4a6c2cab3 100644
--- a/board/sasukette/ec.tasklist
+++ b/board/sasukette/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/sasukette/gpio.inc b/board/sasukette/gpio.inc
index 396a5595fa..de63737e75 100644
--- a/board/sasukette/gpio.inc
+++ b/board/sasukette/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/sasukette/led.c b/board/sasukette/led.c
index 28643a7b87..af6d3635ac 100644
--- a/board/sasukette/led.c
+++ b/board/sasukette/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -13,8 +13,8 @@
 #include "led_common.h"
 #include "led_onoff_states.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
 __override const int led_charge_lvl_1 = 1;
 
@@ -22,33 +22,36 @@ __override const int led_charge_lvl_2 = 100;
 
 /* Sasukette : There are 3 leds for AC, Battery and Power */
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC},
-			{LED_OFF, 1 * LED_ONE_SEC} },
-	[STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR] = {{EC_LED_COLOR_RED, 0.5 * LED_ONE_SEC},
-			{LED_OFF, 0.5 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC},
-			{LED_OFF, 1 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     1 * LED_ONE_SEC },
+					   { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED,
+					    0.5 * LED_ONE_SEC },
+					  { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					 { LED_OFF, 1 * LED_ONE_SEC } },
+	};
 
 __override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_BLUE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -56,7 +59,7 @@ __override void led_set_color_power(enum ec_led_colors color)
 {
 	/* Don't set led if led_auto_control is disabled. */
 	if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) ||
-		!led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
+	    !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
 		return;
 	}
 
@@ -74,7 +77,7 @@ __override void led_set_color_battery(enum ec_led_colors color)
 {
 	/* Don't set led if led_auto_control is disabled. */
 	if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) ||
-		!led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
+	    !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
 		return;
 	}
 
@@ -118,12 +121,12 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 	if (led_id == EC_LED_ID_BATTERY_LED) {
 		gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_OFF_LVL);
 		gpio_set_level(GPIO_BAT_LED_GREEN_L,
-			!brightness[EC_LED_COLOR_GREEN]);
+			       !brightness[EC_LED_COLOR_GREEN]);
 		gpio_set_level(GPIO_BAT_LED_RED_L,
-			!brightness[EC_LED_COLOR_RED]);
+			       !brightness[EC_LED_COLOR_RED]);
 	} else if (led_id == EC_LED_ID_POWER_LED) {
 		gpio_set_level(GPIO_PWR_LED_BLUE_L,
-			!brightness[EC_LED_COLOR_BLUE]);
+			       !brightness[EC_LED_COLOR_BLUE]);
 		gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL);
 		gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL);
 	}
diff --git a/board/sasukette/usb_pd_policy.c b/board/sasukette/usb_pd_policy.c
index 15faf41ffc..83c09bb99e 100644
--- a/board/sasukette/usb_pd_policy.c
+++ b/board/sasukette/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,8 @@
 #include "driver/tcpm/tcpci.h"
 #include "usb_pd.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
diff --git a/board/scarlet/battery.c b/board/scarlet/battery.c
index 0be4cc93e2..5d4412f66c 100644
--- a/board/scarlet/battery.c
+++ b/board/scarlet/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -32,11 +32,7 @@
 static uint8_t batt_id = 0xff;
 
 /* Do not change the enum values. We directly use strap gpio level to index. */
-enum battery_type {
-	BATTERY_SIMPLO = 0,
-	BATTERY_AETECH,
-	BATTERY_COUNT
-};
+enum battery_type { BATTERY_SIMPLO = 0, BATTERY_AETECH, BATTERY_COUNT };
 
 static const struct battery_info info[] = {
 	[BATTERY_SIMPLO] = {
@@ -192,7 +188,7 @@ int charger_profile_override(struct charge_state_data *curr)
 	else {
 		for (temp_zone = 0; temp_zone < TEMP_ZONE_COUNT; temp_zone++) {
 			if (bat_temp_c <
-				temp_zones[batt_id][temp_zone].temp_max)
+			    temp_zones[batt_id][temp_zone].temp_max)
 				break;
 		}
 	}
@@ -233,9 +229,10 @@ int charger_profile_override(struct charge_state_data *curr)
 		curr->requested_voltage =
 			temp_zones[batt_id][temp_zone].desired_voltage;
 
-		curr->requested_current = (charge_phase) ?
-			CHARGE_PHASE_CHANGED_CURRENT_MA :
-			temp_zones[batt_id][temp_zone].desired_current;
+		curr->requested_current =
+			(charge_phase) ?
+				CHARGE_PHASE_CHANGED_CURRENT_MA :
+				temp_zones[batt_id][temp_zone].desired_current;
 		break;
 	case TEMP_OUT_OF_RANGE:
 		curr->requested_current = curr->requested_voltage = 0;
@@ -281,8 +278,7 @@ static void board_charge_termination(void)
 			te = 1;
 	}
 }
-DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE,
-	     board_charge_termination,
+DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, board_charge_termination,
 	     HOOK_PRIO_DEFAULT);
 
 /* Customs options controllable by host command. */
diff --git a/board/scarlet/board.c b/board/scarlet/board.c
index 3d9049c983..34e5cc456c 100644
--- a/board/scarlet/board.c
+++ b/board/scarlet/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,6 +24,7 @@
 #include "hooks.h"
 #include "host_command.h"
 #include "i2c.h"
+#include "panic.h"
 #include "power.h"
 #include "power_button.h"
 #include "pwm.h"
@@ -43,8 +44,8 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
@@ -68,27 +69,23 @@ static void warm_reset_request_interrupt(enum gpio_signal signal)
 /******************************************************************************/
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] = {"BOARD_ID", 3300, 4096, 0, STM32_AIN(10)},
+	[ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(10) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /******************************************************************************/
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "charger",
-		.port = I2C_PORT_CHARGER,
-		.kbps = 400,
-		.scl  = GPIO_I2C0_SCL,
-		.sda  = GPIO_I2C0_SDA
-	},
-	{
-		.name = "tcpc0",
-		.port = I2C_PORT_TCPC0,
-		.kbps = 1000,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	},
+	{ .name = "charger",
+	  .port = I2C_PORT_CHARGER,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_SCL,
+	  .sda = GPIO_I2C0_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 1000,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -104,22 +101,22 @@ const struct charger_config_t chg_chips[] = {
 
 /* power signal list.  Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
-	{GPIO_PP1250_S3_PG,    POWER_SIGNAL_ACTIVE_HIGH, "PP1250_S3_PWR_GOOD"},
-	{GPIO_PP900_S0_PG,     POWER_SIGNAL_ACTIVE_HIGH, "PP900_S0_PWR_GOOD"},
-	{GPIO_AP_CORE_PG,      POWER_SIGNAL_ACTIVE_HIGH, "AP_PWR_GOOD"},
-	{GPIO_AP_EC_S3_S0_L,   POWER_SIGNAL_ACTIVE_LOW, "SUSPEND_DEASSERTED"},
+	{ GPIO_PP1250_S3_PG, POWER_SIGNAL_ACTIVE_HIGH, "PP1250_S3_PWR_GOOD" },
+	{ GPIO_PP900_S0_PG, POWER_SIGNAL_ACTIVE_HIGH, "PP900_S0_PWR_GOOD" },
+	{ GPIO_AP_CORE_PG, POWER_SIGNAL_ACTIVE_HIGH, "AP_PWR_GOOD" },
+	{ GPIO_AP_EC_S3_S0_L, POWER_SIGNAL_ACTIVE_LOW, "SUSPEND_DEASSERTED" },
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
 #ifdef CONFIG_TEMP_SENSOR_TMP432
 /* Temperature sensors data; must be in same order as enum temp_sensor_id. */
 const struct temp_sensor_t temp_sensors[] = {
-	{"TMP432_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-		TMP432_IDX_LOCAL, 4},
-	{"TMP432_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-		TMP432_IDX_REMOTE1, 4},
-	{"TMP432_Sensor_2", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
-		TMP432_IDX_REMOTE2, 4},
+	{ "TMP432_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
+	  TMP432_IDX_LOCAL, 4 },
+	{ "TMP432_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
+	  TMP432_IDX_REMOTE1, 4 },
+	{ "TMP432_Sensor_2", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
+	  TMP432_IDX_REMOTE2, 4 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -128,9 +125,9 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
  * same order as enum temp_sensor_id. To always ignore any temp, use 0.
  */
 struct ec_thermal_config thermal_params[] = {
-	{{0, 0, 0}, 0, 0}, /* TMP432_Internal */
-	{{0, 0, 0}, 0, 0}, /* TMP432_Sensor_1 */
-	{{0, 0, 0}, 0, 0}, /* TMP432_Sensor_2 */
+	{ { 0, 0, 0 }, 0, 0 }, /* TMP432_Internal */
+	{ { 0, 0, 0 }, 0, 0 }, /* TMP432_Sensor_1 */
+	{ { 0, 0, 0 }, 0, 0 }, /* TMP432_Sensor_2 */
 };
 BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
 #endif
@@ -154,11 +151,14 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &virtual_usb_mux_driver,
+				.hpd_update = &virtual_hpd_update,
+			},
 	},
 };
 
@@ -166,11 +166,11 @@ void board_reset_pd_mcu(void)
 {
 }
 
-enum critical_shutdown board_critical_shutdown_check(
-		struct charge_state_data *curr)
+enum critical_shutdown
+board_critical_shutdown_check(struct charge_state_data *curr)
 {
 	if ((curr->batt.flags & BATT_FLAG_BAD_VOLTAGE) ||
-		(curr->batt.voltage <= BAT_LOW_VOLTAGE_THRESH))
+	    (curr->batt.voltage <= BAT_LOW_VOLTAGE_THRESH))
 		return CRITICAL_SHUTDOWN_CUTOFF;
 	else
 		return CRITICAL_SHUTDOWN_IGNORE;
@@ -212,11 +212,11 @@ int board_set_active_charge_port(int charge_port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
-	charge_set_input_current_limit(MAX(charge_ma,
-			       CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 int extpower_is_present(void)
@@ -252,8 +252,7 @@ static void board_spi_enable(void)
 
 	spi_enable(&spi_devices[0], 1);
 }
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP,
-	     board_spi_enable,
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_spi_enable,
 	     MOTION_SENSE_HOOK_PRIO - 1);
 
 static void board_spi_disable(void)
@@ -265,8 +264,7 @@ static void board_spi_disable(void)
 
 	gpio_config_module(MODULE_SPI_CONTROLLER, 0);
 }
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN,
-	     board_spi_disable,
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_spi_disable,
 	     MOTION_SENSE_HOOK_PRIO + 1);
 
 static void board_init(void)
@@ -306,8 +304,8 @@ void board_config_pre_init(void)
 	 * Ch4: USART1_TX / Ch5: USART1_RX (1000)
 	 * Ch6: SPI2_RX / Ch7: SPI2_TX (0011)
 	 */
-	STM32_DMA_CSELR(STM32_DMAC_CH4) = (8 << 12) | (8 << 16) |
-					  (3 << 20) | (3 << 24);
+	STM32_DMA_CSELR(STM32_DMAC_CH4) = (8 << 12) | (8 << 16) | (3 << 20) |
+					  (3 << 24);
 }
 
 enum scarlet_board_version {
@@ -335,16 +333,16 @@ struct {
 	enum scarlet_board_version version;
 	int expect_mv;
 } const scarlet_boards[] = {
-	{ BOARD_VERSION_REV0, 109 },   /* 51.1K , 2.2K(gru 3.3K) ohm */
-	{ BOARD_VERSION_REV1, 211 },   /* 51.1k , 6.8K ohm */
-	{ BOARD_VERSION_REV2, 319 },   /* 51.1K , 11K ohm */
-	{ BOARD_VERSION_REV3, 427 },   /* 56K   , 17.4K ohm */
-	{ BOARD_VERSION_REV4, 542 },   /* 51.1K , 22K ohm */
-	{ BOARD_VERSION_REV5, 666 },   /* 51.1K , 30K ohm */
-	{ BOARD_VERSION_REV6, 781 },   /* 51.1K , 39.2K ohm */
-	{ BOARD_VERSION_REV7, 900 },   /* 56K   , 56K ohm */
-	{ BOARD_VERSION_REV8, 1023 },  /* 47K   , 61.9K ohm */
-	{ BOARD_VERSION_REV9, 1137 },  /* 47K   , 80.6K ohm */
+	{ BOARD_VERSION_REV0, 109 }, /* 51.1K , 2.2K(gru 3.3K) ohm */
+	{ BOARD_VERSION_REV1, 211 }, /* 51.1k , 6.8K ohm */
+	{ BOARD_VERSION_REV2, 319 }, /* 51.1K , 11K ohm */
+	{ BOARD_VERSION_REV3, 427 }, /* 56K   , 17.4K ohm */
+	{ BOARD_VERSION_REV4, 542 }, /* 51.1K , 22K ohm */
+	{ BOARD_VERSION_REV5, 666 }, /* 51.1K , 30K ohm */
+	{ BOARD_VERSION_REV6, 781 }, /* 51.1K , 39.2K ohm */
+	{ BOARD_VERSION_REV7, 900 }, /* 56K   , 56K ohm */
+	{ BOARD_VERSION_REV8, 1023 }, /* 47K   , 61.9K ohm */
+	{ BOARD_VERSION_REV9, 1137 }, /* 47K   , 80.6K ohm */
 	{ BOARD_VERSION_REV10, 1240 }, /* 56K   , 124K ohm */
 	{ BOARD_VERSION_REV11, 1343 }, /* 51.1K , 150K ohm */
 	{ BOARD_VERSION_REV12, 1457 }, /* 47K   , 200K ohm */
@@ -400,11 +398,9 @@ static struct mutex g_base_mutex;
 static struct bmi_drv_data_t g_bmi160_data;
 
 /* Matrix to rotate accelerometer into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0,  0},
-	{ 0,  FLOAT_TO_FP(-1),  0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+				       { 0, FLOAT_TO_FP(-1), 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	/*
diff --git a/board/scarlet/board.h b/board/scarlet/board.h
index 19fda5382f..1d1a7ced79 100644
--- a/board/scarlet/board.h
+++ b/board/scarlet/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,12 +15,12 @@
 
 /* Optional modules */
 #define CONFIG_ADC
-#undef  CONFIG_ADC_WATCHDOG
+#undef CONFIG_ADC_WATCHDOG
 #define CONFIG_CHIPSET_RK3399
 #define CONFIG_CMD_ACCELS
 #define CONFIG_CMD_RTC
 #define CONFIG_EMULATED_SYSRQ
-#undef  CONFIG_HIBERNATE
+#undef CONFIG_HIBERNATE
 #define CONFIG_HOSTCMD_RTC
 #define CONFIG_I2C
 #define CONFIG_I2C_CONTROLLER
@@ -40,7 +40,7 @@
 
 #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands for testing */
 
-#undef  CONFIG_UART_CONSOLE
+#undef CONFIG_UART_CONSOLE
 #define CONFIG_UART_CONSOLE 1
 #define CONFIG_UART_RX_DMA
 
@@ -92,8 +92,7 @@
 /* Camera VSYNC */
 #define CONFIG_SYNC
 #define CONFIG_SYNC_COMMAND
-#define CONFIG_SYNC_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
+#define CONFIG_SYNC_INT_EVENT TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
 
 /* To be able to indicate the device is in tablet mode. */
 #define CONFIG_TABLET_MODE
@@ -137,33 +136,33 @@
 #endif
 
 /* Battery parameters for max17055 ModelGauge m5 algorithm. */
-#define BATTERY_MAX17055_RSENSE             5     /* m-ohm */
-#define BATTERY_DESIRED_CHARGING_CURRENT    4000  /* mA */
+#define BATTERY_MAX17055_RSENSE 5 /* m-ohm */
+#define BATTERY_DESIRED_CHARGING_CURRENT 4000 /* mA */
 
 #define CONFIG_THROTTLE_AP_ON_BAT_DISCHG_CURRENT
-#define BAT_MAX_DISCHG_CURRENT	5000 /* mA */
+#define BAT_MAX_DISCHG_CURRENT 5000 /* mA */
 
 #define CONFIG_THROTTLE_AP_ON_BAT_VOLTAGE
 #define BAT_LOW_VOLTAGE_THRESH 3200 /* mV */
 
 #define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_VOLTAGE_MV     12850
+#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 12850
 
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY 50000  /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 50000 /* us */
 
 /* Timer selection */
-#define TIM_CLOCK32  2
+#define TIM_CLOCK32 2
 #define TIM_WATCHDOG 7
 
 /* 48 MHz SYSCLK clock frequency */
 #define CPU_CLOCK 48000000
 
 /* Optional for testing */
-#undef  CONFIG_PECI
-#undef  CONFIG_PSTORE
+#undef CONFIG_PECI
+#undef CONFIG_PSTORE
 
 /* Modules we want to exclude */
 #undef CONFIG_CMD_BATTFAKE
@@ -176,24 +175,24 @@
 
 #define CONFIG_TASK_PROFILING
 
-#define I2C_PORT_CHARGER  0
-#define I2C_PORT_BATTERY  0
+#define I2C_PORT_CHARGER 0
+#define I2C_PORT_BATTERY 0
 #define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
-#define I2C_PORT_TCPC0    1
+#define I2C_PORT_TCPC0 1
 
 /* Route sbs host requests to virtual battery driver */
 #define VIRTUAL_BATTERY_ADDR_FLAGS 0x0B
 
 /* Enable Accel over SPI */
-#define CONFIG_SPI_ACCEL_PORT    0  /* The first SPI controller port (SPI2) */
+#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */
 
 #define CONFIG_MKBP_INPUT_DEVICES
 #define CONFIG_MKBP_EVENT
 #define CONFIG_MKBP_USE_GPIO
 /* Define the host events which are allowed to wakeup AP in S3. */
-#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \
-		(EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |\
-		 EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC))
+#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK                \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC))
 
 #ifndef __ASSEMBLER__
 
diff --git a/board/scarlet/build.mk b/board/scarlet/build.mk
index f2966fea6a..adecf6b4ea 100644
--- a/board/scarlet/build.mk
+++ b/board/scarlet/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/scarlet/ec.tasklist b/board/scarlet/ec.tasklist
index 1548272184..08baec1e86 100644
--- a/board/scarlet/ec.tasklist
+++ b/board/scarlet/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/scarlet/gpio.inc b/board/scarlet/gpio.inc
index 9c45295a7f..15ce1cb681 100644
--- a/board/scarlet/gpio.inc
+++ b/board/scarlet/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/scarlet/led.c b/board/scarlet/led.c
index d327ee46d6..6f42f462cf 100644
--- a/board/scarlet/led.c
+++ b/board/scarlet/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -28,7 +28,7 @@ enum led_color {
 	LED_RED,
 	LED_AMBER,
 	LED_GREEN,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static int bat_led_set_color(enum led_color color)
@@ -69,13 +69,13 @@ static void scarlet_led_set_battery(void)
 		break;
 	case PWR_STATE_DISCHARGE:
 		if (charge_get_percent() < 3)
-			bat_led_set_color((battery_second & 1)
-					? LED_OFF : LED_AMBER);
+			bat_led_set_color((battery_second & 1) ? LED_OFF :
+								 LED_AMBER);
 		else if (charge_get_percent() < 10)
-			bat_led_set_color((battery_second & 3)
-					? LED_OFF : LED_AMBER);
+			bat_led_set_color((battery_second & 3) ? LED_OFF :
+								 LED_AMBER);
 		else if (charge_get_percent() >= BATTERY_LEVEL_NEAR_FULL &&
-		    (chflags & CHARGE_FLAG_EXTERNAL_POWER))
+			 (chflags & CHARGE_FLAG_EXTERNAL_POWER))
 			bat_led_set_color(LED_GREEN);
 		else
 			bat_led_set_color(LED_OFF);
@@ -87,11 +87,11 @@ static void scarlet_led_set_battery(void)
 		bat_led_set_color(LED_GREEN);
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE. */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			bat_led_set_color(
-				(battery_second & 0x2) ? LED_GREEN : LED_AMBER);
-		else
-			bat_led_set_color(LED_GREEN);
+		bat_led_set_color(LED_GREEN);
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		bat_led_set_color((battery_second & 0x2) ? LED_GREEN :
+							   LED_AMBER);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
@@ -112,10 +112,12 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 	if (led_id == EC_LED_ID_BATTERY_LED) {
 		gpio_set_level(GPIO_BAT_LED_RED,
 			       (brightness[EC_LED_COLOR_RED] != 0) ?
-				BAT_LED_ON : BAT_LED_OFF);
+				       BAT_LED_ON :
+				       BAT_LED_OFF);
 		gpio_set_level(GPIO_BAT_LED_GREEN,
 			       (brightness[EC_LED_COLOR_GREEN] != 0) ?
-				BAT_LED_ON : BAT_LED_OFF);
+				       BAT_LED_ON :
+				       BAT_LED_OFF);
 		return EC_SUCCESS;
 	}
 	return EC_ERROR_UNKNOWN;
diff --git a/board/scarlet/usb_pd_policy.c b/board/scarlet/usb_pd_policy.c
index cba4540ecd..919e7a8864 100644
--- a/board/scarlet/usb_pd_policy.c
+++ b/board/scarlet/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,8 +21,8 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 static uint8_t vbus_en;
 
@@ -33,7 +33,6 @@ int board_vbus_source_enabled(int port)
 
 int pd_set_power_supply_ready(int port)
 {
-
 	pd_set_vbus_discharge(port, 0);
 	/* Provide VBUS */
 	vbus_en = 1;
diff --git a/board/scout/board.c b/board/scout/board.c
index ce0ee8ceae..2c391ecd32 100644
--- a/board/scout/board.c
+++ b/board/scout/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -37,8 +37,8 @@
 #include "usb_common.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
 /* Sensors */
 
@@ -147,14 +147,14 @@ static int32_t base_5v_power;
  * Power usage for each port as measured or estimated.
  * Units are milliwatts (5v x ma current)
  */
-#define PWR_BASE_LOAD	(5*1335)
-#define PWR_FRONT_HIGH	(5*1603)
-#define PWR_FRONT_LOW	(5*963)
-#define PWR_REAR	(5*1075)
-#define PWR_HDMI	(5*562)
-#define PWR_C_HIGH	(5*3740)
-#define PWR_C_LOW	(5*2090)
-#define PWR_MAX		(5*10000)
+#define PWR_BASE_LOAD (5 * 1335)
+#define PWR_FRONT_HIGH (5 * 1603)
+#define PWR_FRONT_LOW (5 * 963)
+#define PWR_REAR (5 * 1075)
+#define PWR_HDMI (5 * 562)
+#define PWR_C_HIGH (5 * 3740)
+#define PWR_C_LOW (5 * 2090)
+#define PWR_MAX (5 * 10000)
 
 /*
  * Update the 5V power usage, assuming no throttling,
@@ -212,69 +212,56 @@ static void port_ocp_interrupt(enum gpio_signal signal)
 
 /******************************************************************************/
 /* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
+const struct spi_device_t spi_devices[] = {};
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
 /******************************************************************************/
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN]        = { .channel = 5,
-				.flags = PWM_CONFIG_OPEN_DRAIN,
-				.freq = 25000},
-	[PWM_CH_LED_RED]    = { .channel = 0,
-				.flags = PWM_CONFIG_DSLEEP,
-				.freq = 2000 },
-	[PWM_CH_LED_WHITE]  = { .channel = 2,
-				.flags = PWM_CONFIG_DSLEEP,
-				.freq = 2000 },
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
+	[PWM_CH_LED_RED] = { .channel = 0,
+			     .flags = PWM_CONFIG_DSLEEP,
+			     .freq = 2000 },
+	[PWM_CH_LED_WHITE] = { .channel = 2,
+			       .flags = PWM_CONFIG_DSLEEP,
+			       .freq = 2000 },
 };
 
 /******************************************************************************/
 /* I2C port map configuration */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "ina",
-		.port = I2C_PORT_INA,
-		.kbps = 400,
-		.scl  = GPIO_I2C0_SCL,
-		.sda  = GPIO_I2C0_SDA
-	},
-	{
-		.name = "ppc0",
-		.port = I2C_PORT_PPC0,
-		.kbps = 400,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	},
-	{
-		.name = "scaler",
-		.port = I2C_PORT_SCALER,
-		.kbps = 400,
-		.scl  = GPIO_I2C2_SCL,
-		.sda  = GPIO_I2C2_SDA
-	},
-	{
-		.name = "tcpc0",
-		.port = I2C_PORT_TCPC0,
-		.kbps = 400,
-		.scl  = GPIO_I2C3_SCL,
-		.sda  = GPIO_I2C3_SDA
-	},
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 400,
-		.scl  = GPIO_I2C5_SCL,
-		.sda  = GPIO_I2C5_SDA
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl  = GPIO_I2C7_SCL,
-		.sda  = GPIO_I2C7_SDA
-	},
+	{ .name = "ina",
+	  .port = I2C_PORT_INA,
+	  .kbps = 400,
+	  .scl = GPIO_I2C0_SCL,
+	  .sda = GPIO_I2C0_SDA },
+	{ .name = "ppc0",
+	  .port = I2C_PORT_PPC0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "scaler",
+	  .port = I2C_PORT_SCALER,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 400,
+	  .scl = GPIO_I2C5_SCL,
+	  .sda = GPIO_I2C5_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_I2C7_SCL,
+	  .sda = GPIO_I2C7_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -342,15 +329,14 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
 /******************************************************************************/
 /* Wake up pins */
-const enum gpio_signal hibernate_wake_pins[] = {
-};
+const enum gpio_signal hibernate_wake_pins[] = {};
 const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 
 /******************************************************************************/
 /* Physical fans. These are logically separate from pwm_channels. */
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = -1,
 };
@@ -369,7 +355,7 @@ BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
 /******************************************************************************/
 /* MFT channels. These are logically separate from pwm_channels. */
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN },
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
@@ -378,8 +364,8 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_A \
-	{ \
+#define THERMAL_A                \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = 0, \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(85), \
@@ -398,8 +384,8 @@ __maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_B \
-	{ \
+#define THERMAL_B                \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = 0, \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(78), \
@@ -650,23 +636,23 @@ DECLARE_HOOK(HOOK_INIT, setup_thermal, HOOK_PRIO_DEFAULT - 1);
  *
  *  All measurements are in milliwatts.
  */
-#define THROT_TYPE_A		BIT(0)
-#define THROT_TYPE_C		BIT(1)
-#define THROT_PROCHOT		BIT(2)
+#define THROT_TYPE_A BIT(0)
+#define THROT_TYPE_C BIT(1)
+#define THROT_PROCHOT BIT(2)
 
 /*
  * Power gain if front USB A ports are limited.
  */
-#define POWER_GAIN_TYPE_A	3200
+#define POWER_GAIN_TYPE_A 3200
 /*
  * Power gain if Type C port is limited.
  */
-#define POWER_GAIN_TYPE_C	8800
+#define POWER_GAIN_TYPE_C 8800
 /*
  * Power is averaged over 10 ms, with a reading every 2 ms.
  */
-#define POWER_DELAY_MS		2
-#define POWER_READINGS		(10/POWER_DELAY_MS)
+#define POWER_DELAY_MS 2
+#define POWER_READINGS (10 / POWER_DELAY_MS)
 
 static void power_monitor(void)
 {
@@ -679,8 +665,7 @@ static void power_monitor(void)
 	 * If CPU is off or suspended, no need to throttle
 	 * or restrict power.
 	 */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF |
-			     CHIPSET_STATE_SUSPEND)) {
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF | CHIPSET_STATE_SUSPEND)) {
 		/*
 		 * Slow down monitoring, assume no throttling required.
 		 */
diff --git a/board/scout/board.h b/board/scout/board.h
index 53958b1686..41a93845d7 100644
--- a/board/scout/board.h
+++ b/board/scout/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,8 +12,8 @@
 #define CONFIG_UART_TX_BUF_SIZE 4096
 
 /* NPCX7 config */
-#define NPCX7_PWM1_SEL    0  /* GPIO C2 is not used as PWM1. */
-#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
+#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */
+#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */
 
 /* Internal SPI flash on NPCX796FC is 512 kB */
 #define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
@@ -40,7 +40,7 @@
 #undef CONFIG_HIBERNATE
 #define CONFIG_HOST_INTERFACE_ESPI
 #define CONFIG_LED_COMMON
-#undef  CONFIG_LID_SWITCH
+#undef CONFIG_LID_SWITCH
 #define CONFIG_LTO
 #define CONFIG_PWM
 #define CONFIG_VBOOT_EFS2
@@ -50,7 +50,7 @@
 #define CONFIG_SHA256
 
 /* Sensor */
-#undef  CONFIG_MOTION_SENSE_RESUME_DELAY_US
+#undef CONFIG_MOTION_SENSE_RESUME_DELAY_US
 #define CONFIG_MOTION_SENSE_RESUME_DELAY_US (1000 * MSEC)
 #define CONFIG_CMD_ACCEL_INFO
 /* Enable sensor fifo, must also define the _SIZE and _THRES */
@@ -139,14 +139,14 @@
 /* I2C Bus Configuration */
 #define CONFIG_I2C
 #define CONFIG_I2C_CONTROLLER
-#define I2C_PORT_INA		NPCX_I2C_PORT0_0
-#define I2C_PORT_PPC0		NPCX_I2C_PORT1_0
-#define I2C_PORT_SCALER		NPCX_I2C_PORT2_0
-#define I2C_PORT_SENSORS	NPCX_I2C_PORT3_0
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT3_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_PORT_INA NPCX_I2C_PORT0_0
+#define I2C_PORT_PPC0 NPCX_I2C_PORT1_0
+#define I2C_PORT_SCALER NPCX_I2C_PORT2_0
+#define I2C_PORT_SENSORS NPCX_I2C_PORT3_0
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT3_0
+#define I2C_PORT_POWER NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 
 #define PP5000_PGOOD_POWER_SIGNAL_MASK POWER_SIGNAL_MASK(PP5000_A_PGOOD)
 
@@ -164,12 +164,12 @@ enum board_version {
 };
 
 enum adc_channel {
-	ADC_SNS_PP3300,     /* ADC2 */
-	ADC_SNS_PP1050,     /* ADC7 */
-	ADC_VBUS,           /* ADC4 */
-	ADC_PPVAR_IMON,     /* ADC9 */
-	ADC_TEMP_SENSOR_1,  /* ADC0 */
-	ADC_TEMP_SENSOR_2,  /* ADC1 */
+	ADC_SNS_PP3300, /* ADC2 */
+	ADC_SNS_PP1050, /* ADC7 */
+	ADC_VBUS, /* ADC4 */
+	ADC_PPVAR_IMON, /* ADC9 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
 	/* Number of ADC channels */
 	ADC_CH_COUNT
 };
@@ -194,11 +194,7 @@ enum mft_channel {
 	MFT_CH_COUNT,
 };
 
-enum temp_sensor_id {
-	TEMP_SENSOR_CORE,
-	TEMP_SENSOR_WIFI,
-	TEMP_SENSOR_COUNT
-};
+enum temp_sensor_id { TEMP_SENSOR_CORE, TEMP_SENSOR_WIFI, TEMP_SENSOR_COUNT };
 
 enum sensor_id {
 	CLEAR_ALS,
@@ -218,20 +214,20 @@ void show_critical_error(void);
 /*
  * Barrel-jack power (4 bits).
  */
-#define EC_CFG_BJ_POWER_L		0
-#define EC_CFG_BJ_POWER_H		3
+#define EC_CFG_BJ_POWER_L 0
+#define EC_CFG_BJ_POWER_H 3
 #define EC_CFG_BJ_POWER_MASK GENMASK(EC_CFG_BJ_POWER_H, EC_CFG_BJ_POWER_L)
 /*
  * USB Connector 4 not present (1 bit).
  */
-#define EC_CFG_NO_USB4_L		4
-#define EC_CFG_NO_USB4_H		4
+#define EC_CFG_NO_USB4_L 4
+#define EC_CFG_NO_USB4_H 4
 #define EC_CFG_NO_USB4_MASK GENMASK(EC_CFG_NO_USB4_H, EC_CFG_NO_USB4_L)
 /*
  * Thermal solution config (3 bits).
  */
-#define EC_CFG_THERMAL_L		5
-#define EC_CFG_THERMAL_H		7
+#define EC_CFG_THERMAL_L 5
+#define EC_CFG_THERMAL_H 7
 #define EC_CFG_THERMAL_MASK GENMASK(EC_CFG_THERMAL_H, EC_CFG_THERMAL_L)
 
 int ec_config_get_usb4_present(void);
@@ -240,30 +236,30 @@ unsigned int ec_config_get_thermal_solution(void);
 #endif /* !__ASSEMBLER__ */
 
 /* Pin renaming */
-#define GPIO_WP_L               GPIO_EC_WP_ODL
-#define GPIO_PP5000_A_PG_OD     GPIO_PG_PP5000_A_OD
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
-#define GPIO_RECOVERY_L         GPIO_EC_RECOVERY_BTN_ODL
-#define GPIO_RECOVERY_L_2       GPIO_H1_EC_RECOVERY_BTN_ODL
-#define GPIO_POWER_BUTTON_L	GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_PCH_WAKE_L		GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L	GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_ENTERING_RW	GPIO_EC_ENTERING_RW
-#define GPIO_SYS_RESET_L	GPIO_SYS_RST_ODL
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_PCH_RTCRST		GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_TEMP_SENSOR_POWER	GPIO_EN_ROA_RAILS
-#define GPIO_AC_PRESENT		GPIO_BJ_ADP_PRESENT_L
+#define GPIO_WP_L GPIO_EC_WP_ODL
+#define GPIO_PP5000_A_PG_OD GPIO_PG_PP5000_A_OD
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
+#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_ODL
+#define GPIO_RECOVERY_L_2 GPIO_H1_EC_RECOVERY_BTN_ODL
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_EN_ROA_RAILS
+#define GPIO_AC_PRESENT GPIO_BJ_ADP_PRESENT_L
 
 /*
  * There is no RSMRST input, so alias it to the output. This short-circuits
  * common_intel_x86_handle_rsmrst.
  */
-#define GPIO_PG_EC_RSMRST_ODL	GPIO_PCH_RSMRST_L
+#define GPIO_PG_EC_RSMRST_ODL GPIO_PCH_RSMRST_L
 
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/scout/build.mk b/board/scout/build.mk
index cf964a2d15..7b9d891a0c 100644
--- a/board/scout/build.mk
+++ b/board/scout/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/scout/ec.tasklist b/board/scout/ec.tasklist
index 0e4ec4d284..0c3296d173 100644
--- a/board/scout/ec.tasklist
+++ b/board/scout/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/scout/gpio.inc b/board/scout/gpio.inc
index 914dbe8639..8a6b5bb074 100644
--- a/board/scout/gpio.inc
+++ b/board/scout/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,12 +25,12 @@ GPIO_INT(PG_VPRIM_CORE_A_OD,   PIN(2, 3), GPIO_INT_BOTH, power_signal_interrupt)
 GPIO_INT(PG_PP1050_A_OD,       PIN(2, 2), GPIO_INT_BOTH, power_signal_interrupt)
 /* EC output, but also interrupt so this can be polled as a power signal */
 GPIO_INT(EC_PCH_RSMRST_L,      PIN(A, 6), GPIO_OUTPUT | GPIO_INT_F_RISING | GPIO_INT_F_FALLING, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(PG_PP2500_DRAM_U_OD,  PIN(2, 0), GPIO_INT_BOTH, power_signal_interrupt)
 GPIO_INT(PG_PP1200_U_OD,       PIN(2, 1), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, slp_s3_interrupt)
 #endif
 GPIO_INT(PG_PP950_VCCIO_OD,    PIN(1, 7), GPIO_INT_BOTH, power_signal_interrupt)
diff --git a/board/scout/led.c b/board/scout/led.c
index 3066c182d1..ad244ab99e 100644
--- a/board/scout/led.c
+++ b/board/scout/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,16 +19,16 @@
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
 
 /*
  * Due to the CSME-Lite processing, upon startup the CPU transitions through
  * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so
  * delay turning off the LED during suspend/shutdown.
  */
-#define LED_CPU_DELAY_MS	(2000 * MSEC)
+#define LED_CPU_DELAY_MS (2000 * MSEC)
 
-const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 enum led_color {
@@ -89,9 +89,9 @@ static int set_color(enum ec_led_id id, enum led_color color, int duty)
 	}
 }
 
-#define LED_PULSE_US		(2 * SECOND)
+#define LED_PULSE_US (2 * SECOND)
 /* 40 msec for nice and smooth transition. */
-#define LED_PULSE_TICK_US	(40 * MSEC)
+#define LED_PULSE_TICK_US (40 * MSEC)
 
 /* When pulsing is enabled, brightness is incremented by <duty_inc> every
  * <interval> usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented
@@ -233,7 +233,7 @@ void show_critical_error(void)
 		set_color(EC_LED_ID_POWER_LED, LED_RED, 100);
 }
 
-static int command_led(int argc, char **argv)
+static int command_led(int argc, const char **argv)
 {
 	enum ec_led_id id = EC_LED_ID_POWER_LED;
 
diff --git a/board/servo_micro/board.c b/board/servo_micro/board.c
index f82376a15a..b51c522277 100644
--- a/board/servo_micro/board.c
+++ b/board/servo_micro/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -45,21 +45,20 @@ void board_config_pre_init(void)
 	 *  i2c : no dma
 	 *  tim16/17: no dma
 	 */
-	STM32_SYSCFG_CFGR1 |= BIT(26);  /* Remap USART3 RX/TX DMA */
+	STM32_SYSCFG_CFGR1 |= BIT(26); /* Remap USART3 RX/TX DMA */
 
 	/* Remap SPI2 to DMA channels 6 and 7 */
 	/* STM32F072 SPI2 defaults to using DMA channels 4 and 5 */
 	/* but cros_ec hardcodes a 6/7 assumption in registers.h */
 	STM32_SYSCFG_CFGR1 |= BIT(24);
-
 }
 
 /******************************************************************************
  * Forward UARTs as a USB serial interface.
  */
 
-#define USB_STREAM_RX_SIZE	32
-#define USB_STREAM_TX_SIZE	64
+#define USB_STREAM_RX_SIZE 32
+#define USB_STREAM_TX_SIZE 64
 
 /******************************************************************************
  * Forward USART2 (EC) as a simple USB serial interface.
@@ -68,33 +67,22 @@ void board_config_pre_init(void)
 static struct usart_config const usart2;
 struct usb_stream_config const usart2_usb;
 
-static struct queue const usart2_to_usb = QUEUE_DIRECT(1024, uint8_t,
-	usart2.producer, usart2_usb.consumer);
-static struct queue const usb_to_usart2 = QUEUE_DIRECT(64, uint8_t,
-	usart2_usb.producer, usart2.consumer);
+static struct queue const usart2_to_usb =
+	QUEUE_DIRECT(1024, uint8_t, usart2.producer, usart2_usb.consumer);
+static struct queue const usb_to_usart2 =
+	QUEUE_DIRECT(64, uint8_t, usart2_usb.producer, usart2.consumer);
 
 static struct usart_rx_dma const usart2_rx_dma =
 	USART_RX_DMA(STM32_DMAC_CH5, 32);
 
 static struct usart_config const usart2 =
-	USART_CONFIG(usart2_hw,
-		usart2_rx_dma.usart_rx,
-		usart_tx_interrupt,
-		115200,
-		0,
-		usart2_to_usb,
-		usb_to_usart2);
-
-USB_STREAM_CONFIG_USART_IFACE(usart2_usb,
-	USB_IFACE_USART2_STREAM,
-	USB_STR_USART2_STREAM_NAME,
-	USB_EP_USART2_STREAM,
-	USB_STREAM_RX_SIZE,
-	USB_STREAM_TX_SIZE,
-	usb_to_usart2,
-	usart2_to_usb,
-	usart2)
+	USART_CONFIG(usart2_hw, usart2_rx_dma.usart_rx, usart_tx_interrupt,
+		     115200, 0, usart2_to_usb, usb_to_usart2);
 
+USB_STREAM_CONFIG_USART_IFACE(usart2_usb, USB_IFACE_USART2_STREAM,
+			      USB_STR_USART2_STREAM_NAME, USB_EP_USART2_STREAM,
+			      USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE,
+			      usb_to_usart2, usart2_to_usb, usart2)
 
 /******************************************************************************
  * Forward USART3 (CPU) as a simple USB serial interface.
@@ -103,33 +91,22 @@ USB_STREAM_CONFIG_USART_IFACE(usart2_usb,
 static struct usart_config const usart3;
 struct usb_stream_config const usart3_usb;
 
-static struct queue const usart3_to_usb = QUEUE_DIRECT(1024, uint8_t,
-	usart3.producer, usart3_usb.consumer);
-static struct queue const usb_to_usart3 = QUEUE_DIRECT(64, uint8_t,
-	usart3_usb.producer, usart3.consumer);
+static struct queue const usart3_to_usb =
+	QUEUE_DIRECT(1024, uint8_t, usart3.producer, usart3_usb.consumer);
+static struct queue const usb_to_usart3 =
+	QUEUE_DIRECT(64, uint8_t, usart3_usb.producer, usart3.consumer);
 
 static struct usart_rx_dma const usart3_rx_dma =
 	USART_RX_DMA(STM32_DMAC_CH3, 32);
 
 static struct usart_config const usart3 =
-	USART_CONFIG(usart3_hw,
-		usart3_rx_dma.usart_rx,
-		usart_tx_interrupt,
-		115200,
-		0,
-		usart3_to_usb,
-		usb_to_usart3);
-
-USB_STREAM_CONFIG_USART_IFACE(usart3_usb,
-	USB_IFACE_USART3_STREAM,
-	USB_STR_USART3_STREAM_NAME,
-	USB_EP_USART3_STREAM,
-	USB_STREAM_RX_SIZE,
-	USB_STREAM_TX_SIZE,
-	usb_to_usart3,
-	usart3_to_usb,
-	usart3)
+	USART_CONFIG(usart3_hw, usart3_rx_dma.usart_rx, usart_tx_interrupt,
+		     115200, 0, usart3_to_usb, usb_to_usart3);
 
+USB_STREAM_CONFIG_USART_IFACE(usart3_usb, USB_IFACE_USART3_STREAM,
+			      USB_STR_USART3_STREAM_NAME, USB_EP_USART3_STREAM,
+			      USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE,
+			      usb_to_usart3, usart3_to_usb, usart3)
 
 /******************************************************************************
  * Forward USART4 (cr50) as a simple USB serial interface.
@@ -139,34 +116,24 @@ USB_STREAM_CONFIG_USART_IFACE(usart3_usb,
 static struct usart_config const usart4;
 struct usb_stream_config const usart4_usb;
 
-static struct queue const usart4_to_usb = QUEUE_DIRECT(64, uint8_t,
-	usart4.producer, usart4_usb.consumer);
-static struct queue const usb_to_usart4 = QUEUE_DIRECT(64, uint8_t,
-	usart4_usb.producer, usart4.consumer);
+static struct queue const usart4_to_usb =
+	QUEUE_DIRECT(1024, uint8_t, usart4.producer, usart4_usb.consumer);
+static struct queue const usb_to_usart4 =
+	QUEUE_DIRECT(64, uint8_t, usart4_usb.producer, usart4.consumer);
 
 static struct usart_config const usart4 =
-	USART_CONFIG(usart4_hw,
-		usart_rx_interrupt,
-		usart_tx_interrupt,
-		115200,
-		0,
-		usart4_to_usb,
-		usb_to_usart4);
-
-USB_STREAM_CONFIG_USART_IFACE(usart4_usb,
-	USB_IFACE_USART4_STREAM,
-	USB_STR_USART4_STREAM_NAME,
-	USB_EP_USART4_STREAM,
-	USB_STREAM_RX_SIZE,
-	USB_STREAM_TX_SIZE,
-	usb_to_usart4,
-	usart4_to_usb,
-	usart4)
+	USART_CONFIG(usart4_hw, usart_rx_interrupt, usart_tx_interrupt, 115200,
+		     0, usart4_to_usb, usb_to_usart4);
+
+USB_STREAM_CONFIG_USART_IFACE(usart4_usb, USB_IFACE_USART4_STREAM,
+			      USB_STR_USART4_STREAM_NAME, USB_EP_USART4_STREAM,
+			      USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE,
+			      usb_to_usart4, usart4_to_usb, usart4)
 
 /******************************************************************************
  * Check parity setting on usarts.
  */
-static int command_uart_parity(int argc, char **argv)
+static int command_uart_parity(int argc, const char **argv)
 {
 	int parity = 0, newparity;
 	struct usart_config const *usart;
@@ -200,14 +167,13 @@ static int command_uart_parity(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(parity, command_uart_parity,
-			"usart[2|3|4] [0|1|2]",
+DECLARE_CONSOLE_COMMAND(parity, command_uart_parity, "usart[2|3|4] [0|1|2]",
 			"Set parity on uart");
 
 /******************************************************************************
  * Set baud rate setting on usarts.
  */
-static int command_uart_baud(int argc, char **argv)
+static int command_uart_baud(int argc, const char **argv)
 {
 	int baud = 0;
 	struct usart_config const *usart;
@@ -233,14 +199,13 @@ static int command_uart_baud(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(baud, command_uart_baud,
-			"usart[2|3|4] rate",
+DECLARE_CONSOLE_COMMAND(baud, command_uart_baud, "usart[2|3|4] rate",
 			"Set baud rate on uart");
 
 /******************************************************************************
  * Hold the usart pins low while disabling it, or return it to normal.
  */
-static int command_hold_usart_low(int argc, char **argv)
+static int command_hold_usart_low(int argc, const char **argv)
 {
 	/* Each bit represents if that port rx is being held low */
 	static int usart_status;
@@ -297,7 +262,7 @@ static int command_hold_usart_low(int argc, char **argv)
 
 	/* Print status for get and set case. */
 	ccprintf("USART status: %s\n",
-			usart_status & usart_mask ? "held low" : "normal");
+		 usart_status & usart_mask ? "held low" : "normal");
 
 	return EC_SUCCESS;
 }
@@ -309,18 +274,18 @@ DECLARE_CONSOLE_COMMAND(hold_usart_low, command_hold_usart_low,
  * Define the strings used in our USB descriptors.
  */
 const void *const usb_strings[] = {
-	[USB_STR_DESC]         = usb_string_desc,
-	[USB_STR_VENDOR]       = USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]      = USB_STRING_DESC("Servo Micro"),
-	[USB_STR_SERIALNO]     = 0,
-	[USB_STR_VERSION]      = USB_STRING_DESC(CROS_EC_VERSION32),
-	[USB_STR_SPI_NAME]     = USB_STRING_DESC("SPI"),
-	[USB_STR_I2C_NAME]     = USB_STRING_DESC("I2C"),
-	[USB_STR_USART4_STREAM_NAME]  = USB_STRING_DESC("UART3"),
+	[USB_STR_DESC] = usb_string_desc,
+	[USB_STR_VENDOR] = USB_STRING_DESC("Google LLC"),
+	[USB_STR_PRODUCT] = USB_STRING_DESC("Servo Micro"),
+	[USB_STR_SERIALNO] = 0,
+	[USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32),
+	[USB_STR_SPI_NAME] = USB_STRING_DESC("SPI"),
+	[USB_STR_I2C_NAME] = USB_STRING_DESC("I2C"),
+	[USB_STR_USART4_STREAM_NAME] = USB_STRING_DESC("UART3"),
 	[USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Servo Shell"),
-	[USB_STR_USART3_STREAM_NAME]  = USB_STRING_DESC("CPU"),
-	[USB_STR_USART2_STREAM_NAME]  = USB_STRING_DESC("EC"),
-	[USB_STR_UPDATE_NAME]  = USB_STRING_DESC("Firmware update"),
+	[USB_STR_USART3_STREAM_NAME] = USB_STRING_DESC("CPU"),
+	[USB_STR_USART2_STREAM_NAME] = USB_STRING_DESC("EC"),
+	[USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"),
 };
 
 BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
@@ -332,7 +297,7 @@ BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
 
 /* SPI devices */
 const struct spi_device_t spi_devices[] = {
-	{ CONFIG_SPI_FLASH_PORT, 1, GPIO_SPI_CS},
+	{ CONFIG_SPI_FLASH_PORT, 1, GPIO_SPI_CS },
 };
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
@@ -373,17 +338,18 @@ USB_SPI_CONFIG(usb_spi, USB_IFACE_SPI, USB_EP_SPI, 0);
 
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "master",
-		.port = I2C_PORT_MASTER,
-		.kbps = 100,
-		.scl  = GPIO_MASTER_I2C_SCL,
-		.sda  = GPIO_MASTER_I2C_SDA
-	},
+	{ .name = "master",
+	  .port = I2C_PORT_MASTER,
+	  .kbps = 100,
+	  .scl = GPIO_MASTER_I2C_SCL,
+	  .sda = GPIO_MASTER_I2C_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
-int usb_i2c_board_is_enabled(void) { return 1; }
+int usb_i2c_board_is_enabled(void)
+{
+	return 1;
+}
 
 /* Configure ITE flash support module */
 const struct ite_dfu_config_t ite_dfu_config = {
diff --git a/board/servo_micro/board.h b/board/servo_micro/board.h
index 1983ee13e3..801b67e07e 100644
--- a/board/servo_micro/board.h
+++ b/board/servo_micro/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -33,9 +33,10 @@
 #define CONFIG_STM_HWTIMER32
 #define CONFIG_HW_CRC
 #define CONFIG_PVD
-/* See 'Programmable voltage detector characteristics' in the STM32F072x8 Datasheet.
-   PVD Threshold 1 corresponds to a falling voltage threshold of min:2.09V, max:2.27V. */
-#define PVD_THRESHOLD     (1)
+/* See 'Programmable voltage detector characteristics' in the STM32F072x8
+   Datasheet. PVD Threshold 1 corresponds to a falling voltage threshold of
+   min:2.09V, max:2.27V. */
+#define PVD_THRESHOLD (1)
 
 /* USB Configuration */
 #define CONFIG_USB
@@ -50,25 +51,25 @@
 #define DEFAULT_SERIALNO "Uninitialized"
 
 /* USB interface indexes (use define rather than enum to expand them) */
-#define USB_IFACE_USART4_STREAM	0
-#define USB_IFACE_UPDATE	1
-#define USB_IFACE_SPI		2
-#define USB_IFACE_CONSOLE	3
-#define USB_IFACE_I2C		4
-#define USB_IFACE_USART3_STREAM	5
-#define USB_IFACE_USART2_STREAM	6
-#define USB_IFACE_COUNT		7
+#define USB_IFACE_USART4_STREAM 0
+#define USB_IFACE_UPDATE 1
+#define USB_IFACE_SPI 2
+#define USB_IFACE_CONSOLE 3
+#define USB_IFACE_I2C 4
+#define USB_IFACE_USART3_STREAM 5
+#define USB_IFACE_USART2_STREAM 6
+#define USB_IFACE_COUNT 7
 
 /* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL		0
-#define USB_EP_USART4_STREAM	1
-#define USB_EP_UPDATE		2
-#define USB_EP_SPI		3
-#define USB_EP_CONSOLE		4
-#define USB_EP_I2C		5
-#define USB_EP_USART3_STREAM	6
-#define USB_EP_USART2_STREAM	7
-#define USB_EP_COUNT		8
+#define USB_EP_CONTROL 0
+#define USB_EP_USART4_STREAM 1
+#define USB_EP_UPDATE 2
+#define USB_EP_SPI 3
+#define USB_EP_CONSOLE 4
+#define USB_EP_I2C 5
+#define USB_EP_USART3_STREAM 6
+#define USB_EP_USART2_STREAM 7
+#define USB_EP_COUNT 8
 
 /* Enable console recasting of GPIO type. */
 #define CONFIG_CMD_GPIO_EXTENDED
@@ -76,7 +77,7 @@
 /* Enable control of SPI over USB */
 #define CONFIG_USB_SPI
 #define CONFIG_SPI_CONTROLLER
-#define CONFIG_SPI_FLASH_PORT    0  /* First SPI controller port */
+#define CONFIG_SPI_FLASH_PORT 0 /* First SPI controller port */
 
 /* This is not actually an EC so disable some features. */
 #undef CONFIG_WATCHDOG_HELP
@@ -93,8 +94,8 @@
 #define CONFIG_I2C_XFER_LARGE_TRANSFER
 #undef CONFIG_USB_I2C_MAX_WRITE_COUNT
 #undef CONFIG_USB_I2C_MAX_READ_COUNT
-#define CONFIG_USB_I2C_MAX_WRITE_COUNT ((1<<9) - 4)
-#define CONFIG_USB_I2C_MAX_READ_COUNT ((1<<9) - 6)
+#define CONFIG_USB_I2C_MAX_WRITE_COUNT ((1 << 9) - 4)
+#define CONFIG_USB_I2C_MAX_READ_COUNT ((1 << 9) - 6)
 
 /*
  * Allow dangerous commands all the time, since we don't have a write protect
diff --git a/board/servo_micro/build.mk b/board/servo_micro/build.mk
index 0e069a31ad..7ac70706fc 100644
--- a/board/servo_micro/build.mk
+++ b/board/servo_micro/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/servo_micro/ccd.md b/board/servo_micro/ccd.md
index 267da66776..2398e1dd46 100644
--- a/board/servo_micro/ccd.md
+++ b/board/servo_micro/ccd.md
@@ -1,5 +1,5 @@
 <!--
- Copyright 2018 The Chromium OS Authors. All rights reserved.
+ Copyright 2018 The ChromiumOS Authors
  Use of this source code is governed by a BSD-style license that can be
  found in the LICENSE file.
 -->
diff --git a/board/servo_micro/ec.tasklist b/board/servo_micro/ec.tasklist
index c1fb169118..c45a1e89a7 100644
--- a/board/servo_micro/ec.tasklist
+++ b/board/servo_micro/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/servo_micro/gpio.inc b/board/servo_micro/gpio.inc
index 10e411c5f2..ad1739f1e6 100644
--- a/board/servo_micro/gpio.inc
+++ b/board/servo_micro/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/servo_v4/board.c b/board/servo_v4/board.c
index b304408f74..5320d7fd1c 100644
--- a/board/servo_v4/board.c
+++ b/board/servo_v4/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -33,8 +33,8 @@
 #include "usb-stream.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
 /******************************************************************************
  * GPIO interrupt handlers.
@@ -175,23 +175,22 @@ void board_config_pre_init(void)
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* USB PD CC lines sensing. Converted to mV (3300mV/4096). */
-	[ADC_CHG_CC1_PD] = {"CHG_CC1_PD", 3300, 4096, 0, STM32_AIN(2)},
-	[ADC_CHG_CC2_PD] = {"CHG_CC2_PD", 3300, 4096, 0, STM32_AIN(4)},
-	[ADC_DUT_CC1_PD] = {"DUT_CC1_PD", 3300, 4096, 0, STM32_AIN(0)},
-	[ADC_DUT_CC2_PD] = {"DUT_CC2_PD", 3300, 4096, 0, STM32_AIN(5)},
-	[ADC_SBU1_DET] = {"SBU1_DET", 3300, 4096, 0, STM32_AIN(3)},
-	[ADC_SBU2_DET] = {"SBU2_DET", 3300, 4096, 0, STM32_AIN(7)},
-	[ADC_SUB_C_REF] = {"SUB_C_REF", 3300, 4096, 0, STM32_AIN(1)},
+	[ADC_CHG_CC1_PD] = { "CHG_CC1_PD", 3300, 4096, 0, STM32_AIN(2) },
+	[ADC_CHG_CC2_PD] = { "CHG_CC2_PD", 3300, 4096, 0, STM32_AIN(4) },
+	[ADC_DUT_CC1_PD] = { "DUT_CC1_PD", 3300, 4096, 0, STM32_AIN(0) },
+	[ADC_DUT_CC2_PD] = { "DUT_CC2_PD", 3300, 4096, 0, STM32_AIN(5) },
+	[ADC_SBU1_DET] = { "SBU1_DET", 3300, 4096, 0, STM32_AIN(3) },
+	[ADC_SBU2_DET] = { "SBU2_DET", 3300, 4096, 0, STM32_AIN(7) },
+	[ADC_SUB_C_REF] = { "SUB_C_REF", 3300, 4096, 0, STM32_AIN(1) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
-
 /******************************************************************************
  * Forward UARTs as a USB serial interface.
  */
 
-#define USB_STREAM_RX_SIZE	16
-#define USB_STREAM_TX_SIZE	16
+#define USB_STREAM_RX_SIZE 16
+#define USB_STREAM_TX_SIZE 16
 
 /******************************************************************************
  * Forward USART3 as a simple USB serial interface.
@@ -200,29 +199,19 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 static struct usart_config const usart3;
 struct usb_stream_config const usart3_usb;
 
-static struct queue const usart3_to_usb = QUEUE_DIRECT(64, uint8_t,
-	usart3.producer, usart3_usb.consumer);
-static struct queue const usb_to_usart3 = QUEUE_DIRECT(64, uint8_t,
-	usart3_usb.producer, usart3.consumer);
+static struct queue const usart3_to_usb =
+	QUEUE_DIRECT(64, uint8_t, usart3.producer, usart3_usb.consumer);
+static struct queue const usb_to_usart3 =
+	QUEUE_DIRECT(64, uint8_t, usart3_usb.producer, usart3.consumer);
 
 static struct usart_config const usart3 =
-	USART_CONFIG(usart3_hw,
-		usart_rx_interrupt,
-		usart_tx_interrupt,
-		115200,
-		0,
-		usart3_to_usb,
-		usb_to_usart3);
-
-USB_STREAM_CONFIG(usart3_usb,
-	USB_IFACE_USART3_STREAM,
-	USB_STR_USART3_STREAM_NAME,
-	USB_EP_USART3_STREAM,
-	USB_STREAM_RX_SIZE,
-	USB_STREAM_TX_SIZE,
-	usb_to_usart3,
-	usart3_to_usb)
+	USART_CONFIG(usart3_hw, usart_rx_interrupt, usart_tx_interrupt, 115200,
+		     0, usart3_to_usb, usb_to_usart3);
 
+USB_STREAM_CONFIG(usart3_usb, USB_IFACE_USART3_STREAM,
+		  USB_STR_USART3_STREAM_NAME, USB_EP_USART3_STREAM,
+		  USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE, usb_to_usart3,
+		  usart3_to_usb)
 
 /******************************************************************************
  * Forward USART4 as a simple USB serial interface.
@@ -231,44 +220,34 @@ USB_STREAM_CONFIG(usart3_usb,
 static struct usart_config const usart4;
 struct usb_stream_config const usart4_usb;
 
-static struct queue const usart4_to_usb = QUEUE_DIRECT(64, uint8_t,
-	usart4.producer, usart4_usb.consumer);
-static struct queue const usb_to_usart4 = QUEUE_DIRECT(64, uint8_t,
-	usart4_usb.producer, usart4.consumer);
+static struct queue const usart4_to_usb =
+	QUEUE_DIRECT(64, uint8_t, usart4.producer, usart4_usb.consumer);
+static struct queue const usb_to_usart4 =
+	QUEUE_DIRECT(64, uint8_t, usart4_usb.producer, usart4.consumer);
 
 static struct usart_config const usart4 =
-	USART_CONFIG(usart4_hw,
-		usart_rx_interrupt,
-		usart_tx_interrupt,
-		9600,
-		0,
-		usart4_to_usb,
-		usb_to_usart4);
-
-USB_STREAM_CONFIG(usart4_usb,
-	USB_IFACE_USART4_STREAM,
-	USB_STR_USART4_STREAM_NAME,
-	USB_EP_USART4_STREAM,
-	USB_STREAM_RX_SIZE,
-	USB_STREAM_TX_SIZE,
-	usb_to_usart4,
-	usart4_to_usb)
+	USART_CONFIG(usart4_hw, usart_rx_interrupt, usart_tx_interrupt, 9600, 0,
+		     usart4_to_usb, usb_to_usart4);
+
+USB_STREAM_CONFIG(usart4_usb, USB_IFACE_USART4_STREAM,
+		  USB_STR_USART4_STREAM_NAME, USB_EP_USART4_STREAM,
+		  USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE, usb_to_usart4,
+		  usart4_to_usb)
 
 /*
  * Define usb interface descriptor for the `EMPTY` usb interface, to satisfy
  * UEFI and kernel requirements (see b/183857501).
  */
-const struct usb_interface_descriptor
-USB_IFACE_DESC(USB_IFACE_EMPTY) = {
-	.bLength            = USB_DT_INTERFACE_SIZE,
-	.bDescriptorType    = USB_DT_INTERFACE,
-	.bInterfaceNumber   = USB_IFACE_EMPTY,
-	.bAlternateSetting  = 0,
-	.bNumEndpoints      = 0,
-	.bInterfaceClass    = USB_CLASS_VENDOR_SPEC,
+const struct usb_interface_descriptor USB_IFACE_DESC(USB_IFACE_EMPTY) = {
+	.bLength = USB_DT_INTERFACE_SIZE,
+	.bDescriptorType = USB_DT_INTERFACE,
+	.bInterfaceNumber = USB_IFACE_EMPTY,
+	.bAlternateSetting = 0,
+	.bNumEndpoints = 0,
+	.bInterfaceClass = USB_CLASS_VENDOR_SPEC,
 	.bInterfaceSubClass = 0,
 	.bInterfaceProtocol = 0,
-	.iInterface         = 0,
+	.iInterface = 0,
 };
 
 /******************************************************************************
@@ -276,39 +255,38 @@ USB_IFACE_DESC(USB_IFACE_EMPTY) = {
  */
 
 const void *const usb_strings[] = {
-	[USB_STR_DESC]         = usb_string_desc,
-	[USB_STR_VENDOR]       = USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]      = USB_STRING_DESC("Servo V4"),
-	[USB_STR_SERIALNO]     = USB_STRING_DESC("1234-a"),
-	[USB_STR_VERSION]      = USB_STRING_DESC(CROS_EC_VERSION32),
-	[USB_STR_I2C_NAME]     = USB_STRING_DESC("I2C"),
+	[USB_STR_DESC] = usb_string_desc,
+	[USB_STR_VENDOR] = USB_STRING_DESC("Google LLC"),
+	[USB_STR_PRODUCT] = USB_STRING_DESC("Servo V4"),
+	[USB_STR_SERIALNO] = USB_STRING_DESC("1234-a"),
+	[USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32),
+	[USB_STR_I2C_NAME] = USB_STRING_DESC("I2C"),
 	[USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Servo EC Shell"),
-	[USB_STR_USART3_STREAM_NAME]  = USB_STRING_DESC("DUT UART"),
-	[USB_STR_USART4_STREAM_NAME]  = USB_STRING_DESC("Atmega UART"),
-	[USB_STR_UPDATE_NAME]  = USB_STRING_DESC("Firmware update"),
+	[USB_STR_USART3_STREAM_NAME] = USB_STRING_DESC("DUT UART"),
+	[USB_STR_USART4_STREAM_NAME] = USB_STRING_DESC("Atmega UART"),
+	[USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"),
 };
 
 BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
 
-
-
 /******************************************************************************
  * Support I2C bridging over USB.
  */
 
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "master",
-		.port = I2C_PORT_MASTER,
-		.kbps = 100,
-		.scl  = GPIO_MASTER_I2C_SCL,
-		.sda  = GPIO_MASTER_I2C_SDA
-	},
+	{ .name = "master",
+	  .port = I2C_PORT_MASTER,
+	  .kbps = 100,
+	  .scl = GPIO_MASTER_I2C_SCL,
+	  .sda = GPIO_MASTER_I2C_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
-int usb_i2c_board_is_enabled(void) { return 1; }
+int usb_i2c_board_is_enabled(void)
+{
+	return 1;
+}
 
 /******************************************************************************
  * Initialize board.
@@ -317,14 +295,13 @@ int usb_i2c_board_is_enabled(void) { return 1; }
 /*
  * Support tca6416 I2C ioexpander.
  */
-#define GPIOX_I2C_ADDR_FLAGS	0x20
-#define GPIOX_IN_PORT_A		0x0
-#define GPIOX_IN_PORT_B		0x1
-#define GPIOX_OUT_PORT_A	0x2
-#define GPIOX_OUT_PORT_B	0x3
-#define GPIOX_DIR_PORT_A	0x6
-#define GPIOX_DIR_PORT_B	0x7
-
+#define GPIOX_I2C_ADDR_FLAGS 0x20
+#define GPIOX_IN_PORT_A 0x0
+#define GPIOX_IN_PORT_B 0x1
+#define GPIOX_OUT_PORT_A 0x2
+#define GPIOX_OUT_PORT_B 0x3
+#define GPIOX_DIR_PORT_A 0x6
+#define GPIOX_DIR_PORT_B 0x7
 
 /* Write a GPIO output on the tca6416 I2C ioexpander. */
 static void write_ioexpander(int bank, int gpio, int val)
@@ -394,15 +371,15 @@ static void init_ioexpander(void)
  * Max observed USB low across sampled systems: 666mV
  * Min observed USB high across sampled systems: 3026mV
  */
-#define GND_MAX_MV	700
-#define USB_HIGH_MV	2500
-#define SBU_DIRECT	0
-#define SBU_FLIP	1
+#define GND_MAX_MV 700
+#define USB_HIGH_MV 2500
+#define SBU_DIRECT 0
+#define SBU_FLIP 1
 
-#define MODE_SBU_DISCONNECT	0
-#define MODE_SBU_CONNECT	1
-#define MODE_SBU_FLIP		2
-#define MODE_SBU_OTHER		3
+#define MODE_SBU_DISCONNECT 0
+#define MODE_SBU_CONNECT 1
+#define MODE_SBU_FLIP 2
+#define MODE_SBU_OTHER 3
 
 static void ccd_measure_sbu(void);
 DECLARE_DEFERRED(ccd_measure_sbu);
@@ -445,12 +422,12 @@ static void ccd_measure_sbu(void)
 		} else {
 			count++;
 		}
-	/*
-	 * If SuzyQ is enabled, we'll poll for a persistent no-signal for
-	 * 500ms. Since USB is differential, we should never see GND/GND
-	 * while the device is connected.
-	 * If disconnected, electrically remove SuzyQ.
-	 */
+		/*
+		 * If SuzyQ is enabled, we'll poll for a persistent no-signal
+		 * for 500ms. Since USB is differential, we should never see
+		 * GND/GND while the device is connected. If disconnected,
+		 * electrically remove SuzyQ.
+		 */
 	} else if ((mux_en) && (sbu1 < GND_MAX_MV) && (sbu2 < GND_MAX_MV)) {
 		/* Check for SBU disconnect if connected. */
 		if (last != MODE_SBU_DISCONNECT) {
diff --git a/board/servo_v4/board.h b/board/servo_v4/board.h
index 910d6caacc..289c117989 100644
--- a/board/servo_v4/board.h
+++ b/board/servo_v4/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -38,9 +38,10 @@
 #define CONFIG_STM_HWTIMER32
 #define CONFIG_HW_CRC
 #define CONFIG_PVD
-/* See 'Programmable voltage detector characteristics' in the STM32F072x8 Datasheet.
-   PVD Threshold 1 corresponds to a falling voltage threshold of min:2.09V, max:2.27V. */
-#define PVD_THRESHOLD     (1)
+/* See 'Programmable voltage detector characteristics' in the STM32F072x8
+   Datasheet. PVD Threshold 1 corresponds to a falling voltage threshold of
+   min:2.09V, max:2.27V. */
+#define PVD_THRESHOLD (1)
 
 /* USB Configuration */
 #define CONFIG_USB
@@ -60,23 +61,23 @@
 #define DEFAULT_MAC_ADDR "Uninitialized"
 
 /* USB interface indexes (use define rather than enum to expand them) */
-#define USB_IFACE_CONSOLE	0
-#define USB_IFACE_EMPTY		1
-#define USB_IFACE_I2C		2
-#define USB_IFACE_USART3_STREAM	3
-#define USB_IFACE_USART4_STREAM	4
-#define USB_IFACE_UPDATE	5
-#define USB_IFACE_COUNT		6
+#define USB_IFACE_CONSOLE 0
+#define USB_IFACE_EMPTY 1
+#define USB_IFACE_I2C 2
+#define USB_IFACE_USART3_STREAM 3
+#define USB_IFACE_USART4_STREAM 4
+#define USB_IFACE_UPDATE 5
+#define USB_IFACE_COUNT 6
 
 /* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL		0
-#define USB_EP_CONSOLE		1
-#define USB_EP_EMPTY		2
-#define USB_EP_I2C		3
-#define USB_EP_USART3_STREAM	4
-#define USB_EP_USART4_STREAM	5
-#define USB_EP_UPDATE		6
-#define USB_EP_COUNT		7
+#define USB_EP_CONTROL 0
+#define USB_EP_CONSOLE 1
+#define USB_EP_EMPTY 2
+#define USB_EP_I2C 3
+#define USB_EP_USART3_STREAM 4
+#define USB_EP_USART4_STREAM 5
+#define USB_EP_UPDATE 6
+#define USB_EP_COUNT 7
 
 /* Enable console recasting of GPIO type. */
 #define CONFIG_CMD_GPIO_EXTENDED
@@ -113,7 +114,7 @@
 
 /* PD features */
 #define CONFIG_ADC
-#undef  CONFIG_ADC_WATCHDOG
+#undef CONFIG_ADC_WATCHDOG
 #define CONFIG_BOARD_PRE_INIT
 /*
  * If task profiling is enabled then the rx falling edge detection interrupts
@@ -122,7 +123,7 @@
 #undef CONFIG_TASK_PROFILING
 
 #define CONFIG_CHARGE_MANAGER
-#undef  CONFIG_CHARGE_MANAGER_SAFE_MODE
+#undef CONFIG_CHARGE_MANAGER_SAFE_MODE
 #define CONFIG_USB_POWER_DELIVERY
 #define CONFIG_USB_PD_TCPMV1
 #define CONFIG_CMD_PD
@@ -144,22 +145,22 @@
 #define CONFIG_USB_PD_INITIAL_DRP_STATE PD_DRP_FORCE_SINK
 
 /* Variable-current Rp no connect and Ra attach macros */
-#define CC_NC(port, cc, sel)  (pd_tcpc_cc_nc(port, cc, sel))
-#define CC_RA(port, cc, sel)  (pd_tcpc_cc_ra(port, cc, sel))
+#define CC_NC(port, cc, sel) (pd_tcpc_cc_nc(port, cc, sel))
+#define CC_RA(port, cc, sel) (pd_tcpc_cc_ra(port, cc, sel))
 
 /*
  * TODO(crosbug.com/p/60792): The delay values are currently just place holders
  * and the delay will need to be relative to the circuitry that allows VBUS to
  * be supplied to the DUT port from the CHG port.
  */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  50000  /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 50000 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 50000 /* us */
 
 /* Define typical operating power and max power */
 #define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       60000
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_VOLTAGE_MV     20000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 /*
  * Define PDO selection logic for SourceCap.
  * On a 45W PD charger, it might provide PDOs with 15V/3A and 20V/2.25A.
@@ -180,8 +181,7 @@
 
 /* Timer selection */
 #define TIM_CLOCK32 2
-#define TIM_ADC     3
-
+#define TIM_ADC 3
 
 #include "gpio_signal.h"
 
@@ -200,7 +200,6 @@ enum usb_strings {
 	USB_STR_COUNT
 };
 
-
 /* ADC signal */
 enum adc_channel {
 	ADC_CHG_CC1_PD,
diff --git a/board/servo_v4/build.mk b/board/servo_v4/build.mk
index 6c39be0475..05a0684696 100644
--- a/board/servo_v4/build.mk
+++ b/board/servo_v4/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/servo_v4/ec.tasklist b/board/servo_v4/ec.tasklist
index 2111c6b761..f51780dce4 100644
--- a/board/servo_v4/ec.tasklist
+++ b/board/servo_v4/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/servo_v4/gpio.inc b/board/servo_v4/gpio.inc
index 76b9a06d0f..afc5789636 100644
--- a/board/servo_v4/gpio.inc
+++ b/board/servo_v4/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/servo_v4/usb_pd_config.h b/board/servo_v4/usb_pd_config.h
index af9d84922c..8437af3118 100644
--- a/board/servo_v4/usb_pd_config.h
+++ b/board/servo_v4/usb_pd_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -56,22 +56,22 @@
 #define CONFIG_HW_CRC
 
 /* Servo v4 CC configuration */
-#define CC_DETACH	BIT(0)   /* Emulate detach: both CC open */
-#define CC_DISABLE_DTS	BIT(1)   /* Apply resistors to single or both CC? */
-#define CC_ALLOW_SRC	BIT(2)   /* Allow charge through by policy? */
-#define CC_ENABLE_DRP	BIT(3)   /* Enable dual-role port */
-#define CC_SNK_WITH_PD	BIT(4)   /* Force enabling PD comm for sink role */
-#define CC_POLARITY	BIT(5)   /* CC polarity */
+#define CC_DETACH BIT(0) /* Emulate detach: both CC open */
+#define CC_DISABLE_DTS BIT(1) /* Apply resistors to single or both CC? */
+#define CC_ALLOW_SRC BIT(2) /* Allow charge through by policy? */
+#define CC_ENABLE_DRP BIT(3) /* Enable dual-role port */
+#define CC_SNK_WITH_PD BIT(4) /* Force enabling PD comm for sink role */
+#define CC_POLARITY BIT(5) /* CC polarity */
 
 /* Servo v4 DP alt-mode configuration */
-#define ALT_DP_ENABLE		BIT(0)   /* Enable DP alt-mode or not */
-#define ALT_DP_PIN_C		BIT(1)   /* Pin assignment C supported */
-#define ALT_DP_PIN_D		BIT(2)   /* Pin assignment D supported */
-#define ALT_DP_PIN_E		BIT(3)   /* Pin assignment E supported */
-#define ALT_DP_MF_PREF		BIT(4)   /* Multi-Function preferred */
-#define ALT_DP_PLUG		BIT(5)   /* Plug or receptacle */
-#define ALT_DP_OVERRIDE_HPD	BIT(6)   /* Override the HPD signal */
-#define ALT_DP_HPD_LVL		BIT(7)   /* HPD level if overridden */
+#define ALT_DP_ENABLE BIT(0) /* Enable DP alt-mode or not */
+#define ALT_DP_PIN_C BIT(1) /* Pin assignment C supported */
+#define ALT_DP_PIN_D BIT(2) /* Pin assignment D supported */
+#define ALT_DP_PIN_E BIT(3) /* Pin assignment E supported */
+#define ALT_DP_MF_PREF BIT(4) /* Multi-Function preferred */
+#define ALT_DP_PLUG BIT(5) /* Plug or receptacle */
+#define ALT_DP_OVERRIDE_HPD BIT(6) /* Override the HPD signal */
+#define ALT_DP_HPD_LVL BIT(7) /* HPD level if overridden */
 
 /* TX uses SPI1 on PB3-4 for CHG port, SPI2 on PB 13-14 for DUT port */
 #define SPI_REGS(p) ((p) ? STM32_SPI2_REGS : STM32_SPI1_REGS)
@@ -94,14 +94,14 @@ static inline void spi_enable_clock(int port)
 
 #define TIM_TX_CCR_IDX(p) ((p) ? TIM_TX_CCR_DUT : TIM_TX_CCR_CHG)
 #define TIM_RX_CCR_IDX(p) ((p) ? TIM_RX_CCR_DUT : TIM_RX_CCR_CHG)
-#define TIM_CCR_CS  1
+#define TIM_CCR_CS 1
 
 /*
  * EXTI line 21 is connected to the CMP1 output,
  * EXTI line 22 is connected to the CMP2 output,
  * CHG uses CMP2, and DUT uses CMP1.
  */
-#define EXTI_COMP_MASK(p) ((p) ? (1<<21) : BIT(22))
+#define EXTI_COMP_MASK(p) ((p) ? (1 << 21) : BIT(22))
 
 #define IRQ_COMP STM32_IRQ_COMP
 /* triggers packet detection on comparator falling edge */
@@ -193,13 +193,25 @@ static inline void pd_select_polarity(int port, int polarity)
 	if (port == 0) {
 		/* CHG use the right comparator inverted input for COMP2 */
 		STM32_COMP_CSR = (val & ~STM32_COMP_CMP2INSEL_MASK) |
-			(polarity ? STM32_COMP_CMP2INSEL_INM4  /* PA4: C0_CC2 */
-				  : STM32_COMP_CMP2INSEL_INM6);/* PA2: C0_CC1 */
+				 (polarity ?
+					  STM32_COMP_CMP2INSEL_INM4 /* PA4:
+								       C0_CC2
+								     */
+					  :
+					  STM32_COMP_CMP2INSEL_INM6); /* PA2:
+									 C0_CC1
+								       */
 	} else {
 		/* DUT use the right comparator inverted input for COMP1 */
 		STM32_COMP_CSR = (val & ~STM32_COMP_CMP1INSEL_MASK) |
-			(polarity ? STM32_COMP_CMP1INSEL_INM5  /* PA5: C1_CC2 */
-			 : STM32_COMP_CMP1INSEL_INM6);/* PA0: C1_CC1 */
+				 (polarity ?
+					  STM32_COMP_CMP1INSEL_INM5 /* PA5:
+								       C1_CC2
+								     */
+					  :
+					  STM32_COMP_CMP1INSEL_INM6); /* PA0:
+									 C1_CC1
+								       */
 	}
 }
 
@@ -279,7 +291,6 @@ static inline void pd_config_init(int port, uint8_t power_role)
 
 	/* Initialize TX pins and put them in Hi-Z */
 	pd_tx_init();
-
 }
 
 int pd_adc_read(int port, int cc);
diff --git a/board/servo_v4/usb_pd_pdo.c b/board/servo_v4/usb_pd_pdo.c
index 8df0eac2c2..b2eeee8e52 100644
--- a/board/servo_v4/usb_pd_pdo.c
+++ b/board/servo_v4/usb_pd_pdo.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,9 +12,9 @@
 #define CHG_PDO_FIXED_FLAGS (PDO_FIXED_DATA_SWAP)
 
 const uint32_t pd_snk_pdo[] = {
-		PDO_FIXED(5000, 500, CHG_PDO_FIXED_FLAGS),
-		PDO_BATT(4750, 21000, 15000),
-		PDO_VAR(4750, 21000, 3000),
+	PDO_FIXED(5000, 500, CHG_PDO_FIXED_FLAGS),
+	PDO_BATT(4750, 21000, 15000),
+	PDO_VAR(4750, 21000, 3000),
 };
 const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
 
@@ -48,7 +48,7 @@ int charge_manager_get_source_pdo(const uint32_t **src_pdo, const int port)
 	 * port, otherwise we provide no power.
 	 */
 	if (charge_port_is_active()) {
-		*src_pdo =  pd_src_chg_pdo;
+		*src_pdo = pd_src_chg_pdo;
 		pdo_cnt = chg_pdo_cnt;
 	}
 
diff --git a/board/servo_v4/usb_pd_pdo.h b/board/servo_v4/usb_pd_pdo.h
index bb9d8adca6..acab299690 100644
--- a/board/servo_v4/usb_pd_pdo.h
+++ b/board/servo_v4/usb_pd_pdo.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/servo_v4/usb_pd_policy.c b/board/servo_v4/usb_pd_policy.c
index 61931cda8b..1dbe586585 100644
--- a/board/servo_v4/usb_pd_policy.c
+++ b/board/servo_v4/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -28,55 +28,57 @@
 #include "usb_pd_pdo.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
-#define DUT_PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\
-			     PDO_FIXED_COMM_CAP)
+#define DUT_PDO_FIXED_FLAGS \
+	(PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP | PDO_FIXED_COMM_CAP)
 
-#define VBUS_UNCHANGED(curr, pend, new) (curr == new && pend == new)
+#define VBUS_UNCHANGED(curr, pend, new) (curr == new &&pend == new)
 
 /* Macros to config the PD role */
 #define CONF_SET_CLEAR(c, set, clear) ((c | (set)) & ~(clear))
-#define CONF_SRC(c) CONF_SET_CLEAR(c, \
-				CC_DISABLE_DTS | CC_ALLOW_SRC, \
-				CC_ENABLE_DRP | CC_SNK_WITH_PD)
-#define CONF_SNK(c) CONF_SET_CLEAR(c, \
-				CC_DISABLE_DTS, \
-				CC_ALLOW_SRC | CC_ENABLE_DRP | CC_SNK_WITH_PD)
-#define CONF_PDSNK(c) CONF_SET_CLEAR(c, \
-				CC_DISABLE_DTS | CC_SNK_WITH_PD, \
-				CC_ALLOW_SRC | CC_ENABLE_DRP)
-#define CONF_DRP(c) CONF_SET_CLEAR(c, \
-				CC_DISABLE_DTS | CC_ALLOW_SRC | CC_ENABLE_DRP, \
-				CC_SNK_WITH_PD)
-#define CONF_SRCDTS(c) CONF_SET_CLEAR(c, \
-				CC_ALLOW_SRC, \
-				CC_ENABLE_DRP | CC_DISABLE_DTS | CC_SNK_WITH_PD)
-#define CONF_SNKDTS(c) CONF_SET_CLEAR(c, \
-				0, \
-				CC_ALLOW_SRC | CC_ENABLE_DRP | \
-				CC_DISABLE_DTS | CC_SNK_WITH_PD)
-#define CONF_PDSNKDTS(c) CONF_SET_CLEAR(c, \
-				CC_SNK_WITH_PD, \
-				CC_ALLOW_SRC | CC_ENABLE_DRP | CC_DISABLE_DTS)
-#define CONF_DRPDTS(c) CONF_SET_CLEAR(c, \
-				CC_ALLOW_SRC | CC_ENABLE_DRP, \
-				CC_DISABLE_DTS | CC_SNK_WITH_PD)
+#define CONF_SRC(c)                                      \
+	CONF_SET_CLEAR(c, CC_DISABLE_DTS | CC_ALLOW_SRC, \
+		       CC_ENABLE_DRP | CC_SNK_WITH_PD)
+#define CONF_SNK(c)                       \
+	CONF_SET_CLEAR(c, CC_DISABLE_DTS, \
+		       CC_ALLOW_SRC | CC_ENABLE_DRP | CC_SNK_WITH_PD)
+#define CONF_PDSNK(c)                                      \
+	CONF_SET_CLEAR(c, CC_DISABLE_DTS | CC_SNK_WITH_PD, \
+		       CC_ALLOW_SRC | CC_ENABLE_DRP)
+#define CONF_DRP(c)                                                      \
+	CONF_SET_CLEAR(c, CC_DISABLE_DTS | CC_ALLOW_SRC | CC_ENABLE_DRP, \
+		       CC_SNK_WITH_PD)
+#define CONF_SRCDTS(c)                  \
+	CONF_SET_CLEAR(c, CC_ALLOW_SRC, \
+		       CC_ENABLE_DRP | CC_DISABLE_DTS | CC_SNK_WITH_PD)
+#define CONF_SNKDTS(c)                                                 \
+	CONF_SET_CLEAR(c, 0,                                           \
+		       CC_ALLOW_SRC | CC_ENABLE_DRP | CC_DISABLE_DTS | \
+			       CC_SNK_WITH_PD)
+#define CONF_PDSNKDTS(c)                  \
+	CONF_SET_CLEAR(c, CC_SNK_WITH_PD, \
+		       CC_ALLOW_SRC | CC_ENABLE_DRP | CC_DISABLE_DTS)
+#define CONF_DRPDTS(c)                                  \
+	CONF_SET_CLEAR(c, CC_ALLOW_SRC | CC_ENABLE_DRP, \
+		       CC_DISABLE_DTS | CC_SNK_WITH_PD)
+#define CONF_DTSOFF(c) CONF_SET_CLEAR(c, CC_DISABLE_DTS, 0)
+#define CONF_DTSON(c) CONF_SET_CLEAR(c, 0, CC_DISABLE_DTS)
 
 /* Macros to apply Rd/Rp to CC lines */
-#define DUT_ACTIVE_CC_SET(r, flags) \
-	gpio_set_flags(cc_config & CC_POLARITY ? \
-				CONCAT2(GPIO_USB_DUT_CC2_, r) : \
-				CONCAT2(GPIO_USB_DUT_CC1_, r), \
+#define DUT_ACTIVE_CC_SET(r, flags)                            \
+	gpio_set_flags(cc_config &CC_POLARITY ?                \
+			       CONCAT2(GPIO_USB_DUT_CC2_, r) : \
+			       CONCAT2(GPIO_USB_DUT_CC1_, r),  \
 		       flags)
-#define DUT_INACTIVE_CC_SET(r, flags) \
-	gpio_set_flags(cc_config & CC_POLARITY ? \
-				CONCAT2(GPIO_USB_DUT_CC1_, r) : \
-				CONCAT2(GPIO_USB_DUT_CC2_, r), \
+#define DUT_INACTIVE_CC_SET(r, flags)                          \
+	gpio_set_flags(cc_config &CC_POLARITY ?                \
+			       CONCAT2(GPIO_USB_DUT_CC1_, r) : \
+			       CONCAT2(GPIO_USB_DUT_CC2_, r),  \
 		       flags)
-#define DUT_BOTH_CC_SET(r, flags) \
-	do { \
+#define DUT_BOTH_CC_SET(r, flags)                                     \
+	do {                                                          \
 		gpio_set_flags(CONCAT2(GPIO_USB_DUT_CC1_, r), flags); \
 		gpio_set_flags(CONCAT2(GPIO_USB_DUT_CC2_, r), flags); \
 	} while (0)
@@ -94,15 +96,15 @@ static int cc_config = CC_ALLOW_SRC;
 
 /* Voltage thresholds for no connect in DTS mode */
 static int pd_src_vnc_dts[TYPEC_RP_RESERVED][2] = {
-	{PD_SRC_3_0_VNC_MV, PD_SRC_1_5_VNC_MV},
-	{PD_SRC_1_5_VNC_MV, PD_SRC_DEF_VNC_MV},
-	{PD_SRC_3_0_VNC_MV, PD_SRC_DEF_VNC_MV},
+	{ PD_SRC_3_0_VNC_MV, PD_SRC_1_5_VNC_MV },
+	{ PD_SRC_1_5_VNC_MV, PD_SRC_DEF_VNC_MV },
+	{ PD_SRC_3_0_VNC_MV, PD_SRC_DEF_VNC_MV },
 };
 /* Voltage thresholds for Ra attach in DTS mode */
 static int pd_src_rd_threshold_dts[TYPEC_RP_RESERVED][2] = {
-	{PD_SRC_3_0_RD_THRESH_MV, PD_SRC_1_5_RD_THRESH_MV},
-	{PD_SRC_1_5_RD_THRESH_MV, PD_SRC_DEF_RD_THRESH_MV},
-	{PD_SRC_3_0_RD_THRESH_MV, PD_SRC_DEF_RD_THRESH_MV},
+	{ PD_SRC_3_0_RD_THRESH_MV, PD_SRC_1_5_RD_THRESH_MV },
+	{ PD_SRC_1_5_RD_THRESH_MV, PD_SRC_DEF_RD_THRESH_MV },
+	{ PD_SRC_3_0_RD_THRESH_MV, PD_SRC_DEF_RD_THRESH_MV },
 };
 /* Voltage thresholds for no connect in normal SRC mode */
 static int pd_src_vnc[TYPEC_RP_RESERVED] = {
@@ -139,7 +141,8 @@ static uint8_t allow_dr_swap = 1;
 static uint32_t max_supported_voltage(void)
 {
 	int board_max_mv = board_get_version() >= BOARD_VERSION_BLACK ?
-		PD_MAX_VOLTAGE_MV : MAX_MV_RED_BLUE;
+				   PD_MAX_VOLTAGE_MV :
+				   MAX_MV_RED_BLUE;
 
 	return board_max_mv < user_limited_max_mv ? board_max_mv :
 						    user_limited_max_mv;
@@ -263,8 +266,8 @@ static void update_ports(void)
 					break;
 
 				/* Find the 'best' PDO <= voltage */
-				pdo_index =
-				pd_find_pdo_index(pd_get_src_cap_cnt(CHG),
+				pdo_index = pd_find_pdo_index(
+					pd_get_src_cap_cnt(CHG),
 					pd_get_src_caps(CHG),
 					pd_src_voltages_mv[i], &pdo);
 				/* Don't duplicate PDOs */
@@ -287,9 +290,9 @@ static void update_ports(void)
 		} else {
 			/* 5V PDO */
 			pd_src_chg_pdo[0] = PDO_FIXED_VOLT(PD_MIN_MV) |
-				PDO_FIXED_CURR(vbus[CHG].ma) |
-				DUT_PDO_FIXED_FLAGS |
-				PDO_FIXED_UNCONSTRAINED;
+					    PDO_FIXED_CURR(vbus[CHG].ma) |
+					    DUT_PDO_FIXED_FLAGS |
+					    PDO_FIXED_UNCONSTRAINED;
 
 			chg_pdo_cnt = 1;
 		}
@@ -314,8 +317,8 @@ int board_set_active_charge_port(int charge_port)
 	return 0;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	if (port != CHG)
 		return;
@@ -361,8 +364,9 @@ int pd_tcpc_cc_nc(int port, int cc_volt, int cc_sel)
 	if (cc_config & CC_DISABLE_DTS)
 		nc = cc_volt >= pd_src_vnc[rp_index];
 	else
-		nc = cc_volt >= pd_src_vnc_dts[rp_index][
-				cc_config & CC_POLARITY ? !cc_sel : cc_sel];
+		nc = cc_volt >=
+		     pd_src_vnc_dts[rp_index]
+				   [cc_config & CC_POLARITY ? !cc_sel : cc_sel];
 
 	return nc;
 }
@@ -388,8 +392,10 @@ int pd_tcpc_cc_ra(int port, int cc_volt, int cc_sel)
 	if (cc_config & CC_DISABLE_DTS)
 		ra = cc_volt < pd_src_rd_threshold[rp_index];
 	else
-		ra = cc_volt < pd_src_rd_threshold_dts[rp_index][
-				cc_config & CC_POLARITY ? !cc_sel : cc_sel];
+		ra = cc_volt <
+		     pd_src_rd_threshold_dts[rp_index]
+					    [cc_config & CC_POLARITY ? !cc_sel :
+								       cc_sel];
 
 	return ra;
 }
@@ -548,7 +554,6 @@ int pd_set_rp_rd(int port, int cc_pull, int rp_value)
 			DUT_ACTIVE_CC_PD(RD);
 		else
 			DUT_BOTH_CC_PD(RD);
-
 	}
 
 	rp_value_stored = rp_value;
@@ -591,8 +596,7 @@ __override void pd_transition_voltage(int idx)
 		/* Wait for CHG transition */
 		deadline.val = get_time().val + PD_T_PS_TRANSITION;
 		CPRINTS("Waiting for CHG port transition");
-		while (charge_port_is_active() &&
-		       vbus[CHG].mv != mv &&
+		while (charge_port_is_active() && vbus[CHG].mv != mv &&
 		       get_time().val < deadline.val)
 			msleep(10);
 
@@ -652,9 +656,7 @@ void pd_power_supply_reset(int port)
 
 int pd_snk_is_vbus_provided(int port)
 {
-
-	return gpio_get_level(port ? GPIO_USB_DET_PP_DUT :
-				     GPIO_USB_DET_PP_CHG);
+	return gpio_get_level(port ? GPIO_USB_DET_PP_DUT : GPIO_USB_DET_PP_CHG);
 }
 
 __override int pd_check_power_swap(int port)
@@ -671,7 +673,8 @@ __override int pd_check_power_swap(int port)
 	if (port == CHG)
 		return 0;
 
-	if (pd_get_power_role(port) == PD_ROLE_SINK && !(cc_config & CC_ALLOW_SRC))
+	if (pd_get_power_role(port) == PD_ROLE_SINK &&
+	    !(cc_config & CC_ALLOW_SRC))
 		return 0;
 
 	if (pd_snk_is_vbus_provided(CHG))
@@ -680,8 +683,7 @@ __override int pd_check_power_swap(int port)
 	return 0;
 }
 
-__override int pd_check_data_swap(int port,
-				  enum pd_data_role data_role)
+__override int pd_check_data_swap(int port, enum pd_data_role data_role)
 {
 	/*
 	 * Servo should allow data role swaps to let DUT see the USB hub, but
@@ -693,8 +695,7 @@ __override int pd_check_data_swap(int port,
 	return allow_dr_swap;
 }
 
-__override void pd_execute_data_swap(int port,
-				     enum pd_data_role data_role)
+__override void pd_execute_data_swap(int port, enum pd_data_role data_role)
 {
 	/*
 	 * TODO(b/137887386): Turn on the fastboot/DFU path when data swap to
@@ -702,8 +703,7 @@ __override void pd_execute_data_swap(int port,
 	 */
 }
 
-__override void pd_check_pr_role(int port,
-				 enum pd_power_role pr_role,
+__override void pd_check_pr_role(int port, enum pd_power_role pr_role,
 				 int flags)
 {
 	/*
@@ -714,9 +714,7 @@ __override void pd_check_pr_role(int port,
 	 */
 }
 
-__override void pd_check_dr_role(int port,
-				 enum pd_data_role dr_role,
-				 int flags)
+__override void pd_check_dr_role(int port, enum pd_data_role dr_role, int flags)
 {
 	if (port == CHG)
 		return;
@@ -726,15 +724,14 @@ __override void pd_check_dr_role(int port,
 		pd_request_data_swap(port);
 }
 
-
 /* ----------------- Vendor Defined Messages ------------------ */
 /*
  * DP alt-mode config, user configurable.
  * Default is the mode disabled, supporting the C and D pin assignment,
  * multi-function preferred, and a plug.
  */
-static int alt_dp_config = (ALT_DP_PIN_C | ALT_DP_PIN_D | ALT_DP_MF_PREF |
-			    ALT_DP_PLUG);
+static int alt_dp_config =
+	(ALT_DP_PIN_C | ALT_DP_PIN_D | ALT_DP_MF_PREF | ALT_DP_PLUG);
 
 /**
  * Get the pins based on the user config.
@@ -769,8 +766,8 @@ const uint32_t vdo_idh = VDO_IDH(0, /* data caps as USB host */
 const uint32_t vdo_product = VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV);
 
 const uint32_t vdo_ama = VDO_AMA(CONFIG_USB_PD_IDENTITY_HW_VERS,
-				 CONFIG_USB_PD_IDENTITY_SW_VERS,
-				 0, 0, 0, 0, /* SS[TR][12] */
+				 CONFIG_USB_PD_IDENTITY_SW_VERS, 0, 0, 0,
+				 0, /* SS[TR][12] */
 				 0, /* Vconn power */
 				 0, /* Vconn power required */
 				 0, /* Vbus power required */
@@ -808,13 +805,13 @@ uint32_t vdo_dp_mode[MODE_CNT];
 
 static int svdm_response_modes(int port, uint32_t *payload)
 {
-	vdo_dp_mode[0] =
-		VDO_MODE_DP(0,             /* UFP pin cfg supported: none */
-			    alt_dp_config_pins(),  /* DFP pin */
-			    1,             /* no usb2.0 signalling in AMode */
-			    alt_dp_config_cable(), /* plug or receptacle */
-			    MODE_DP_V13,   /* DPv1.3 Support, no Gen2 */
-			    MODE_DP_SNK);  /* Its a sink only */
+	vdo_dp_mode[0] = VDO_MODE_DP(0, /* UFP pin cfg supported: none */
+				     alt_dp_config_pins(), /* DFP pin */
+				     1, /* no usb2.0 signalling in AMode */
+				     alt_dp_config_cable(), /* plug or
+							       receptacle */
+				     MODE_DP_V13, /* DPv1.3 Support, no Gen2 */
+				     MODE_DP_SNK); /* Its a sink only */
 
 	/* CCD uses the SBU lines; don't enable DP when dts-mode enabled */
 	if (!(cc_config & CC_DISABLE_DTS))
@@ -881,17 +878,18 @@ static int dp_status(int port, uint32_t *payload)
 	int hpd = get_hpd_level();
 
 	if (opos != OPOS)
-		return 0;  /* NAK */
-
-	payload[1] = VDO_DP_STATUS(
-		0,                /* IRQ_HPD */
-		hpd,              /* HPD_HI|LOW */
-		0,                /* request exit DP */
-		0,                /* request exit USB */
-		(alt_dp_config & ALT_DP_MF_PREF) != 0,  /* MF pref */
-		is_typec_dp_muxed(),
-		0,                /* power low */
-		hpd ? 0x2 : 0);
+		return 0; /* NAK */
+
+	payload[1] =
+		VDO_DP_STATUS(0, /* IRQ_HPD */
+			      hpd, /* HPD_HI|LOW */
+			      0, /* request exit DP */
+			      0, /* request exit USB */
+			      (alt_dp_config & ALT_DP_MF_PREF) != 0, /* MF
+									pref
+								      */
+			      is_typec_dp_muxed(), 0, /* power low */
+			      hpd ? 0x2 : 0);
 	return 2;
 }
 
@@ -911,7 +909,7 @@ static int svdm_enter_mode(int port, uint32_t *payload)
 	/* SID & mode request is valid */
 	if ((PD_VDO_VID(payload[0]) != USB_SID_DISPLAYPORT) ||
 	    (PD_VDO_OPOS(payload[0]) != OPOS))
-		return 0;  /* NAK */
+		return 0; /* NAK */
 
 	alt_mode = OPOS;
 	return 1;
@@ -950,7 +948,7 @@ const struct svdm_response svdm_rsp = {
 };
 
 __override int pd_custom_vdm(int port, int cnt, uint32_t *payload,
-		  uint32_t **rpayload)
+			     uint32_t **rpayload)
 {
 	int cmd = PD_VDO_CMD(payload[0]);
 
@@ -962,7 +960,7 @@ __override int pd_custom_vdm(int port, int cnt, uint32_t *payload,
 	case VDO_CMD_VERSION:
 		/* guarantee last byte of payload is null character */
 		*(payload + cnt - 1) = 0;
-		CPRINTF("ver: %s\n", (char *)(payload+1));
+		CPRINTF("ver: %s\n", (char *)(payload + 1));
 		break;
 	case VDO_CMD_CURRENT:
 		CPRINTF("Current: %dmA\n", payload[1]);
@@ -984,12 +982,10 @@ static void print_cc_mode(void)
 		 gpio_get_level(GPIO_DUT_CHG_EN) ? "on" : "off");
 	ccprintf("chg allowed: %s\n", cc_config & CC_ALLOW_SRC ? "on" : "off");
 	ccprintf("drp enabled: %s\n", cc_config & CC_ENABLE_DRP ? "on" : "off");
-	ccprintf("cc polarity: %s\n", cc_config & CC_POLARITY ? "cc2" :
-								"cc1");
+	ccprintf("cc polarity: %s\n", cc_config & CC_POLARITY ? "cc2" : "cc1");
 	ccprintf("pd enabled: %s\n", pd_comm_is_enabled(DUT) ? "on" : "off");
 }
 
-
 static void do_cc(int cc_config_new)
 {
 	int chargeable;
@@ -1059,7 +1055,7 @@ static void do_cc(int cc_config_new)
 	}
 }
 
-static int command_cc(int argc, char **argv)
+static int command_cc(int argc, const char **argv)
 {
 	int cc_config_new = cc_config;
 
@@ -1090,6 +1086,10 @@ static int command_cc(int argc, char **argv)
 			cc_config_new = CONF_PDSNKDTS(cc_config_new);
 		else if (!strcasecmp(argv[1], "drpdts"))
 			cc_config_new = CONF_DRPDTS(cc_config_new);
+		else if (!strcasecmp(argv[1], "dtsoff"))
+			cc_config_new = CONF_DTSOFF(cc_config_new);
+		else if (!strcasecmp(argv[1], "dtson"))
+			cc_config_new = CONF_DTSON(cc_config_new);
 		else
 			return EC_ERROR_PARAM2;
 	}
@@ -1108,7 +1108,7 @@ static int command_cc(int argc, char **argv)
 }
 DECLARE_CONSOLE_COMMAND(cc, command_cc,
 			"[off|on|src|snk|pdsnk|drp|srcdts|snkdts|pdsnkdts|"
-			"drpdts] [cc1|cc2]",
+			"drpdts|dtsoff|dtson] [cc1|cc2]",
 			"Servo_v4 DTS and CHG mode");
 
 static void fake_disconnect_end(void)
@@ -1128,7 +1128,7 @@ static void fake_disconnect_start(void)
 }
 DECLARE_DEFERRED(fake_disconnect_start);
 
-static int cmd_fake_disconnect(int argc, char *argv[])
+static int cmd_fake_disconnect(int argc, const char *argv[])
 {
 	int delay_ms, duration_ms;
 	char *e;
@@ -1150,18 +1150,18 @@ static int cmd_fake_disconnect(int argc, char *argv[])
 	fake_pd_disconnect_duration_us = duration_ms * MSEC;
 	hook_call_deferred(&fake_disconnect_start_data, delay_ms * MSEC);
 
-	ccprintf("Fake disconnect for %d ms starting in %d ms.\n",
-		duration_ms, delay_ms);
+	ccprintf("Fake disconnect for %d ms starting in %d ms.\n", duration_ms,
+		 delay_ms);
 
 	return EC_SUCCESS;
 }
 DECLARE_CONSOLE_COMMAND(fakedisconnect, cmd_fake_disconnect,
 			"<delay_ms> <duration_ms>", NULL);
 
-static int cmd_ada_srccaps(int argc, char *argv[])
+static int cmd_ada_srccaps(int argc, const char *argv[])
 {
 	int i;
-	const uint32_t * const ada_srccaps = pd_get_src_caps(CHG);
+	const uint32_t *const ada_srccaps = pd_get_src_caps(CHG);
 
 	for (i = 0; i < pd_get_src_cap_cnt(CHG); ++i) {
 		uint32_t max_ma, max_mv, unused;
@@ -1176,11 +1176,10 @@ static int cmd_ada_srccaps(int argc, char *argv[])
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(ada_srccaps, cmd_ada_srccaps,
-			"",
+DECLARE_CONSOLE_COMMAND(ada_srccaps, cmd_ada_srccaps, "",
 			"Print adapter SrcCap");
 
-static int cmd_dp_action(int argc, char *argv[])
+static int cmd_dp_action(int argc, const char *argv[])
 {
 	int i;
 	char *e;
@@ -1199,8 +1198,8 @@ static int cmd_dp_action(int argc, char *argv[])
 		alt_dp_config &= ~ALT_DP_ENABLE;
 	} else if (!strcasecmp(argv[1], "pins")) {
 		if (argc >= 3) {
-			alt_dp_config &= ~(ALT_DP_PIN_C | ALT_DP_PIN_D |
-					   ALT_DP_PIN_E);
+			alt_dp_config &=
+				~(ALT_DP_PIN_C | ALT_DP_PIN_D | ALT_DP_PIN_E);
 			for (i = 0; i < 3; i++) {
 				if (!argv[2][i])
 					break;
@@ -1273,10 +1272,10 @@ static int cmd_dp_action(int argc, char *argv[])
 			}
 		}
 		CPRINTS("HPD source: %s",
-			(alt_dp_config & ALT_DP_OVERRIDE_HPD) ? "overridden"
-							      : "external");
+			(alt_dp_config & ALT_DP_OVERRIDE_HPD) ? "overridden" :
+								"external");
 		CPRINTS("HPD level: %d", get_hpd_level());
-	}  else if (!strcasecmp(argv[1], "help")) {
+	} else if (!strcasecmp(argv[1], "help")) {
 		CPRINTS("Usage: usbc_action dp [enable|disable|hpd|mf|pins|"
 			"plug]");
 	}
@@ -1284,7 +1283,7 @@ static int cmd_dp_action(int argc, char *argv[])
 	return EC_SUCCESS;
 }
 
-static int cmd_usbc_action(int argc, char *argv[])
+static int cmd_usbc_action(int argc, const char *argv[])
 {
 	if (argc >= 2 && !strcasecmp(argv[1], "dp"))
 		return cmd_dp_action(argc - 1, &argv[1]);
diff --git a/board/servo_v4p1/board.c b/board/servo_v4p1/board.c
index 3284b4ef58..c3caa1eff1 100644
--- a/board/servo_v4p1/board.c
+++ b/board/servo_v4p1/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -85,14 +85,20 @@ static int board_tusb1064_dp_rx_eq_set(const struct usb_mux *me,
 	return rv;
 }
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[CHG] = { /* CHG port connected directly to USB 3.0 hub, no mux */ },
-	[DUT] = { /* DUT port with UFP mux */
-		.usb_port = DUT,
-		.i2c_port = I2C_PORT_MASTER,
-		.i2c_addr_flags = TUSB1064_I2C_ADDR10_FLAGS,
-		.driver = &tusb1064_usb_mux_driver,
-		.board_set = &board_tusb1064_dp_rx_eq_set,
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	[CHG] = {
+		/* CHG port connected directly to USB 3.0 hub, no mux */
+	},
+	[DUT] = {
+		/* DUT port with UFP mux */
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = DUT,
+				.i2c_port = I2C_PORT_MASTER,
+				.i2c_addr_flags = TUSB1064_I2C_ADDR10_FLAGS,
+				.driver = &tusb1064_usb_mux_driver,
+				.board_set = &board_tusb1064_dp_rx_eq_set,
+			},
 	}
 };
 
@@ -182,9 +188,9 @@ static void tcpc_evt(enum gpio_signal signal)
 	update_status_fusb302b();
 }
 
-#define HOST_HUB		0
+#define HOST_HUB 0
 struct uhub_i2c_iface_t uhub_config[] = {
-	{I2C_PORT_MASTER, GL3590_I2C_ADDR0},
+	{ I2C_PORT_MASTER, GL3590_I2C_ADDR0 },
 };
 
 static void host_hub_evt(void)
@@ -231,8 +237,8 @@ void ext_hpd_detection_enable(int enable)
 
 #include "gpio_list.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
 /******************************************************************************
  * Board pre-init function.
@@ -276,23 +282,22 @@ void board_config_pre_init(void)
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* USB PD CC lines sensing. Converted to mV (3300mV/4096). */
-	[ADC_CHG_CC1_PD] = {"CHG_CC1_PD", 3300, 4096, 0, STM32_AIN(2)},
-	[ADC_CHG_CC2_PD] = {"CHG_CC2_PD", 3300, 4096, 0, STM32_AIN(4)},
-	[ADC_DUT_CC1_PD] = {"DUT_CC1_PD", 3300, 4096, 0, STM32_AIN(0)},
-	[ADC_DUT_CC2_PD] = {"DUT_CC2_PD", 3300, 4096, 0, STM32_AIN(5)},
-	[ADC_SBU1_DET] = {"SBU1_DET", 3300, 4096, 0, STM32_AIN(3)},
-	[ADC_SBU2_DET] = {"SBU2_DET", 3300, 4096, 0, STM32_AIN(7)},
-	[ADC_SUB_C_REF] = {"SUB_C_REF", 3300, 4096, 0, STM32_AIN(1)},
+	[ADC_CHG_CC1_PD] = { "CHG_CC1_PD", 3300, 4096, 0, STM32_AIN(2) },
+	[ADC_CHG_CC2_PD] = { "CHG_CC2_PD", 3300, 4096, 0, STM32_AIN(4) },
+	[ADC_DUT_CC1_PD] = { "DUT_CC1_PD", 3300, 4096, 0, STM32_AIN(0) },
+	[ADC_DUT_CC2_PD] = { "DUT_CC2_PD", 3300, 4096, 0, STM32_AIN(5) },
+	[ADC_SBU1_DET] = { "SBU1_DET", 3300, 4096, 0, STM32_AIN(3) },
+	[ADC_SBU2_DET] = { "SBU2_DET", 3300, 4096, 0, STM32_AIN(7) },
+	[ADC_SUB_C_REF] = { "SUB_C_REF", 3300, 4096, 0, STM32_AIN(1) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
-
 /******************************************************************************
  * Forward UARTs as a USB serial interface.
  */
 
-#define USB_STREAM_RX_SIZE	16
-#define USB_STREAM_TX_SIZE	16
+#define USB_STREAM_RX_SIZE 16
+#define USB_STREAM_TX_SIZE 16
 
 /******************************************************************************
  * Forward USART3 as a simple USB serial interface.
@@ -301,29 +306,19 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 static struct usart_config const usart3;
 struct usb_stream_config const usart3_usb;
 
-static struct queue const usart3_to_usb = QUEUE_DIRECT(64, uint8_t,
-	usart3.producer, usart3_usb.consumer);
-static struct queue const usb_to_usart3 = QUEUE_DIRECT(64, uint8_t,
-	usart3_usb.producer, usart3.consumer);
+static struct queue const usart3_to_usb =
+	QUEUE_DIRECT(64, uint8_t, usart3.producer, usart3_usb.consumer);
+static struct queue const usb_to_usart3 =
+	QUEUE_DIRECT(64, uint8_t, usart3_usb.producer, usart3.consumer);
 
 static struct usart_config const usart3 =
-	USART_CONFIG(usart3_hw,
-		usart_rx_interrupt,
-		usart_tx_interrupt,
-		115200,
-		0,
-		usart3_to_usb,
-		usb_to_usart3);
-
-USB_STREAM_CONFIG(usart3_usb,
-	USB_IFACE_USART3_STREAM,
-	USB_STR_USART3_STREAM_NAME,
-	USB_EP_USART3_STREAM,
-	USB_STREAM_RX_SIZE,
-	USB_STREAM_TX_SIZE,
-	usb_to_usart3,
-	usart3_to_usb)
+	USART_CONFIG(usart3_hw, usart_rx_interrupt, usart_tx_interrupt, 115200,
+		     0, usart3_to_usb, usb_to_usart3);
 
+USB_STREAM_CONFIG(usart3_usb, USB_IFACE_USART3_STREAM,
+		  USB_STR_USART3_STREAM_NAME, USB_EP_USART3_STREAM,
+		  USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE, usb_to_usart3,
+		  usart3_to_usb)
 
 /******************************************************************************
  * Forward USART4 as a simple USB serial interface.
@@ -332,46 +327,34 @@ USB_STREAM_CONFIG(usart3_usb,
 static struct usart_config const usart4;
 struct usb_stream_config const usart4_usb;
 
-static struct queue const usart4_to_usb = QUEUE_DIRECT(64, uint8_t,
-	usart4.producer, usart4_usb.consumer);
-static struct queue const usb_to_usart4 = QUEUE_DIRECT(64, uint8_t,
-	usart4_usb.producer, usart4.consumer);
+static struct queue const usart4_to_usb =
+	QUEUE_DIRECT(64, uint8_t, usart4.producer, usart4_usb.consumer);
+static struct queue const usb_to_usart4 =
+	QUEUE_DIRECT(64, uint8_t, usart4_usb.producer, usart4.consumer);
 
 static struct usart_config const usart4 =
-	USART_CONFIG(usart4_hw,
-		usart_rx_interrupt,
-		usart_tx_interrupt,
-		9600,
-		0,
-		usart4_to_usb,
-		usb_to_usart4);
-
-USB_STREAM_CONFIG_USART_IFACE(usart4_usb,
-	USB_IFACE_USART4_STREAM,
-	USB_STR_USART4_STREAM_NAME,
-	USB_EP_USART4_STREAM,
-	USB_STREAM_RX_SIZE,
-	USB_STREAM_TX_SIZE,
-	usb_to_usart4,
-	usart4_to_usb,
-	usart4)
+	USART_CONFIG(usart4_hw, usart_rx_interrupt, usart_tx_interrupt, 9600, 0,
+		     usart4_to_usb, usb_to_usart4);
 
+USB_STREAM_CONFIG_USART_IFACE(usart4_usb, USB_IFACE_USART4_STREAM,
+			      USB_STR_USART4_STREAM_NAME, USB_EP_USART4_STREAM,
+			      USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE,
+			      usb_to_usart4, usart4_to_usb, usart4)
 
 /*
  * Define usb interface descriptor for the `EMPTY` usb interface, to satisfy
  * UEFI and kernel requirements (see b/183857501).
  */
-const struct usb_interface_descriptor
-USB_IFACE_DESC(USB_IFACE_EMPTY) = {
-	.bLength            = USB_DT_INTERFACE_SIZE,
-	.bDescriptorType    = USB_DT_INTERFACE,
-	.bInterfaceNumber   = USB_IFACE_EMPTY,
-	.bAlternateSetting  = 0,
-	.bNumEndpoints      = 0,
-	.bInterfaceClass    = USB_CLASS_VENDOR_SPEC,
+const struct usb_interface_descriptor USB_IFACE_DESC(USB_IFACE_EMPTY) = {
+	.bLength = USB_DT_INTERFACE_SIZE,
+	.bDescriptorType = USB_DT_INTERFACE,
+	.bInterfaceNumber = USB_IFACE_EMPTY,
+	.bAlternateSetting = 0,
+	.bNumEndpoints = 0,
+	.bInterfaceClass = USB_CLASS_VENDOR_SPEC,
 	.bInterfaceSubClass = 0,
 	.bInterfaceProtocol = 0,
-	.iInterface         = 0,
+	.iInterface = 0,
 };
 
 /******************************************************************************
@@ -379,40 +362,38 @@ USB_IFACE_DESC(USB_IFACE_EMPTY) = {
  */
 
 const void *const usb_strings[] = {
-	[USB_STR_DESC]         = usb_string_desc,
-	[USB_STR_VENDOR]       = USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]      = USB_STRING_DESC("Servo V4p1"),
-	[USB_STR_SERIALNO]     = USB_STRING_DESC("1234-a"),
-	[USB_STR_VERSION]      = USB_STRING_DESC(CROS_EC_VERSION32),
-	[USB_STR_I2C_NAME]     = USB_STRING_DESC("I2C"),
+	[USB_STR_DESC] = usb_string_desc,
+	[USB_STR_VENDOR] = USB_STRING_DESC("Google LLC"),
+	[USB_STR_PRODUCT] = USB_STRING_DESC("Servo V4p1"),
+	[USB_STR_SERIALNO] = USB_STRING_DESC("1234-a"),
+	[USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32),
+	[USB_STR_I2C_NAME] = USB_STRING_DESC("I2C"),
 	[USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Servo EC Shell"),
-	[USB_STR_USART3_STREAM_NAME]  = USB_STRING_DESC("DUT UART"),
-	[USB_STR_USART4_STREAM_NAME]  = USB_STRING_DESC("Atmega UART"),
-	[USB_STR_UPDATE_NAME]  = USB_STRING_DESC("Firmware update"),
+	[USB_STR_USART3_STREAM_NAME] = USB_STRING_DESC("DUT UART"),
+	[USB_STR_USART4_STREAM_NAME] = USB_STRING_DESC("Atmega UART"),
+	[USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"),
 };
 
 BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
 
-
-
 /******************************************************************************
  * Support I2C bridging over USB.
  */
 
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "master",
-		.port = I2C_PORT_MASTER,
-		.kbps = 100,
-		.scl  = GPIO_MASTER_I2C_SCL,
-		.sda  = GPIO_MASTER_I2C_SDA
-	},
+	{ .name = "master",
+	  .port = I2C_PORT_MASTER,
+	  .kbps = 100,
+	  .scl = GPIO_MASTER_I2C_SCL,
+	  .sda = GPIO_MASTER_I2C_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
-int usb_i2c_board_is_enabled(void) { return 1; }
-
+int usb_i2c_board_is_enabled(void)
+{
+	return 1;
+}
 
 /******************************************************************************
  * Initialize board.
@@ -547,18 +528,14 @@ void tick_event(void)
 DECLARE_HOOK(HOOK_TICK, tick_event, HOOK_PRIO_DEFAULT);
 
 struct ioexpander_config_t ioex_config[] = {
-	[0] = {
-		.drv = &tca64xxa_ioexpander_drv,
+	[0] = { .drv = &tca64xxa_ioexpander_drv,
 		.i2c_host_port = TCA6416A_PORT,
 		.i2c_addr_flags = TCA6416A_ADDR,
-		.flags = IOEX_FLAGS_TCA64XXA_FLAG_VER_TCA6416A
-	},
-	[1] = {
-		.drv = &tca64xxa_ioexpander_drv,
+		.flags = IOEX_FLAGS_TCA64XXA_FLAG_VER_TCA6416A },
+	[1] = { .drv = &tca64xxa_ioexpander_drv,
 		.i2c_host_port = TCA6424A_PORT,
 		.i2c_addr_flags = TCA6424A_ADDR,
-		.flags = IOEX_FLAGS_TCA64XXA_FLAG_VER_TCA6424A
-	}
+		.flags = IOEX_FLAGS_TCA64XXA_FLAG_VER_TCA6424A }
 };
 
 #endif /* SECTION_IS_RO */
diff --git a/board/servo_v4p1/board.h b/board/servo_v4p1/board.h
index 86367a5d0b..b6c7915c6c 100644
--- a/board/servo_v4p1/board.h
+++ b/board/servo_v4p1/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -58,31 +58,30 @@
 
 #define CONFIG_RAM_BANK_SIZE CONFIG_RAM_SIZE
 
-
 #define CONFIG_FLASH_PSTATE
 #define CONFIG_FLASH_PSTATE_BANK
 
-#define CONFIG_SHAREDLIB_SIZE   0
+#define CONFIG_SHAREDLIB_SIZE 0
 
-#define CONFIG_RO_MEM_OFF       0
-#define CONFIG_RO_STORAGE_OFF   0
-#define CONFIG_RO_SIZE          (92*1024)
+#define CONFIG_RO_MEM_OFF 0
+#define CONFIG_RO_STORAGE_OFF 0
+#define CONFIG_RO_SIZE (92 * 1024)
 
-#define CONFIG_FW_PSTATE_OFF    (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
-#define CONFIG_FW_PSTATE_SIZE   CONFIG_FLASH_BANK_SIZE
+#define CONFIG_FW_PSTATE_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
+#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE
 
-#define CONFIG_RW_MEM_OFF       (CONFIG_FW_PSTATE_OFF + CONFIG_FW_PSTATE_SIZE)
-#define CONFIG_RW_STORAGE_OFF   0
-#define CONFIG_RW_SIZE          (CONFIG_FLASH_SIZE_BYTES - \
-				(CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF))
+#define CONFIG_RW_MEM_OFF (CONFIG_FW_PSTATE_OFF + CONFIG_FW_PSTATE_SIZE)
+#define CONFIG_RW_STORAGE_OFF 0
+#define CONFIG_RW_SIZE \
+	(CONFIG_FLASH_SIZE_BYTES - (CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF))
 
-#define CONFIG_EC_PROTECTED_STORAGE_OFF         CONFIG_RO_MEM_OFF
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE        CONFIG_RO_SIZE
-#define CONFIG_EC_WRITABLE_STORAGE_OFF          CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE         CONFIG_RW_SIZE
+#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF
+#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE
+#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE
 
-#define CONFIG_WP_STORAGE_OFF           CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE          CONFIG_EC_PROTECTED_STORAGE_SIZE
+#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
+#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
 
 /* Enable USART1,3,4 and USB streams */
 #define CONFIG_STREAM_USART
@@ -106,7 +105,7 @@
  * STM32F072x8 Datasheet. PVD Threshold 1 corresponds to a
  * falling voltage threshold of min:2.09V, max:2.27V.
  */
-#define PVD_THRESHOLD     (1)
+#define PVD_THRESHOLD (1)
 
 /* USB Configuration */
 #define CONFIG_USB
@@ -125,23 +124,23 @@
 #define DEFAULT_MAC_ADDR "Uninitialized"
 
 /* USB interface indexes (use define rather than enum to expand them) */
-#define USB_IFACE_CONSOLE	0
-#define USB_IFACE_EMPTY		1
-#define USB_IFACE_I2C		2
-#define USB_IFACE_USART3_STREAM	3
-#define USB_IFACE_USART4_STREAM	4
-#define USB_IFACE_UPDATE	5
-#define USB_IFACE_COUNT		6
+#define USB_IFACE_CONSOLE 0
+#define USB_IFACE_EMPTY 1
+#define USB_IFACE_I2C 2
+#define USB_IFACE_USART3_STREAM 3
+#define USB_IFACE_USART4_STREAM 4
+#define USB_IFACE_UPDATE 5
+#define USB_IFACE_COUNT 6
 
 /* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL		0
-#define USB_EP_CONSOLE		1
-#define USB_EP_EMPTY		2
-#define USB_EP_I2C		3
-#define USB_EP_USART3_STREAM	4
-#define USB_EP_USART4_STREAM	5
-#define USB_EP_UPDATE		6
-#define USB_EP_COUNT		7
+#define USB_EP_CONTROL 0
+#define USB_EP_CONSOLE 1
+#define USB_EP_EMPTY 2
+#define USB_EP_I2C 3
+#define USB_EP_USART3_STREAM 4
+#define USB_EP_USART4_STREAM 5
+#define USB_EP_UPDATE 6
+#define USB_EP_COUNT 7
 
 /* Enable console recasting of GPIO type. */
 #define CONFIG_CMD_GPIO_EXTENDED
@@ -182,7 +181,7 @@
 
 /* PD features */
 #define CONFIG_ADC
-#undef  CONFIG_ADC_WATCHDOG
+#undef CONFIG_ADC_WATCHDOG
 #define CONFIG_BOARD_PRE_INIT
 /*
  * If task profiling is enabled then the rx falling edge detection interrupts
@@ -196,7 +195,7 @@
 #define CONFIG_USB_HUB_GL3590
 #define CONFIG_INA231
 #define CONFIG_CHARGE_MANAGER
-#undef  CONFIG_CHARGE_MANAGER_SAFE_MODE
+#undef CONFIG_CHARGE_MANAGER_SAFE_MODE
 #define CONFIG_USB_MUX_TUSB1064
 #define CONFIG_USB_POWER_DELIVERY
 #define CONFIG_USB_PD_TCPMV1
@@ -221,8 +220,8 @@
 #define CONFIG_USB_PD_INITIAL_DRP_STATE PD_DRP_FORCE_SINK
 
 /* Variable-current Rp no connect and Ra attach macros */
-#define CC_NC(port, cc, sel)  (pd_tcpc_cc_nc(port, cc, sel))
-#define CC_RA(port, cc, sel)  (pd_tcpc_cc_ra(port, cc, sel))
+#define CC_NC(port, cc, sel) (pd_tcpc_cc_nc(port, cc, sel))
+#define CC_RA(port, cc, sel) (pd_tcpc_cc_ra(port, cc, sel))
 
 /*
  * These power-supply timing values are now set towards maximum spec limit,
@@ -231,14 +230,14 @@
  * Currently tuned with the Apple 96W adapter.
  * TODO: Change to EVENT-based PS_RDY notification (b/214216304)
  */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  (121*MSEC)
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY (461*MSEC)
+#define PD_POWER_SUPPLY_TURN_ON_DELAY (121 * MSEC)
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY (461 * MSEC)
 
 /* Define typical operating power and max power */
 #define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       100000
-#define PD_MAX_CURRENT_MA     5000
-#define PD_MAX_VOLTAGE_MV     20000
+#define PD_MAX_POWER_MW 100000
+#define PD_MAX_CURRENT_MA 5000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Add the raw option to the i2c_xfer command */
 #define CONFIG_CMD_I2C_XFER_RAW
@@ -266,8 +265,7 @@
 
 /* Timer selection */
 #define TIM_CLOCK32 2
-#define TIM_ADC     3
-
+#define TIM_ADC 3
 
 #include "gpio_signal.h"
 
@@ -286,7 +284,6 @@ enum usb_strings {
 	USB_STR_COUNT
 };
 
-
 /* ADC signal */
 enum adc_channel {
 	ADC_CHG_CC1_PD,
diff --git a/board/servo_v4p1/build.mk b/board/servo_v4p1/build.mk
index 872b4d4281..c1e8db9cd8 100644
--- a/board/servo_v4p1/build.mk
+++ b/board/servo_v4p1/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/servo_v4p1/ccd_measure_sbu.c b/board/servo_v4p1/ccd_measure_sbu.c
index b9c9680cc9..41d53ab597 100644
--- a/board/servo_v4p1/ccd_measure_sbu.c
+++ b/board/servo_v4p1/ccd_measure_sbu.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,8 @@
 #include "ioexpanders.h"
 #include "timer.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
 /*
  * Define voltage thresholds for SBU USB detection.
@@ -20,15 +20,15 @@
  * Max observed USB low across sampled systems: 666mV
  * Min observed USB high across sampled systems: 3026mV
  */
-#define GND_MAX_MV      700
-#define USB_HIGH_MV     2500
-#define SBU_DIRECT      0
-#define SBU_FLIP        1
+#define GND_MAX_MV 700
+#define USB_HIGH_MV 2500
+#define SBU_DIRECT 0
+#define SBU_FLIP 1
 
-#define MODE_SBU_DISCONNECT     0
-#define MODE_SBU_CONNECT        1
-#define MODE_SBU_FLIP           2
-#define MODE_SBU_OTHER          3
+#define MODE_SBU_DISCONNECT 0
+#define MODE_SBU_CONNECT 1
+#define MODE_SBU_FLIP 2
+#define MODE_SBU_OTHER 3
 
 static void ccd_measure_sbu(void);
 DECLARE_DEFERRED(ccd_measure_sbu);
diff --git a/board/servo_v4p1/ccd_measure_sbu.h b/board/servo_v4p1/ccd_measure_sbu.h
index 0dd1ce0de7..8635f892a4 100644
--- a/board/servo_v4p1/ccd_measure_sbu.h
+++ b/board/servo_v4p1/ccd_measure_sbu.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/servo_v4p1/chg_control.c b/board/servo_v4p1/chg_control.c
index 19be03a755..76f3dc9649 100644
--- a/board/servo_v4p1/chg_control.c
+++ b/board/servo_v4p1/chg_control.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,7 +10,7 @@
 #include "timer.h"
 #include "usb_pd.h"
 
-#define CHG_P5V_POWER  0
+#define CHG_P5V_POWER 0
 #define CHG_VBUS_POWER 1
 
 void chg_reset(void)
@@ -55,9 +55,11 @@ void chg_attach_cc_rds(bool en)
 		 * Configure USB_CHG_CC1_MCU and USB_CHG_CC2_MCU as
 		 * ANALOG input
 		 */
-		STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
-			| (3 << (2*2)) | /* PA2 in ANALOG mode */
-			  (3 << (2*4))); /* PA4 in ANALOG mode */
+		STM32_GPIO_MODER(GPIO_A) =
+			(STM32_GPIO_MODER(GPIO_A) | (3 << (2 * 2)) | /* PA2 in
+									ANALOG
+									mode */
+			 (3 << (2 * 4))); /* PA4 in ANALOG mode */
 	} else {
 		/*
 		 * Configure USB_CHG_CC1_MCU and USB_CHG_CC2_MCU as GPIO and
@@ -71,10 +73,12 @@ void chg_attach_cc_rds(bool en)
 		gpio_set_level(GPIO_USB_CHG_CC2_MCU, 1);
 
 		/* Disable Analog mode and Enable GPO */
-		STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
-			& ~(3 << (2*2) | /* PA2 disable ADC */
-			    3 << (2*4))) /* PA4 disable ADC */
-			|  (1 << (2*2) | /* Set as GPO */
-			    1 << (2*4)); /* Set as GPO */
+		STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) &
+					    ~(3 << (2 * 2) | /* PA2 disable ADC
+							      */
+					      3 << (2 * 4))) /* PA4 disable ADC
+							      */
+					   | (1 << (2 * 2) | /* Set as GPO */
+					      1 << (2 * 4)); /* Set as GPO */
 	}
 }
diff --git a/board/servo_v4p1/chg_control.h b/board/servo_v4p1/chg_control.h
index 8b81708ccc..91e3601ac8 100644
--- a/board/servo_v4p1/chg_control.h
+++ b/board/servo_v4p1/chg_control.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,11 +8,7 @@
 
 #include <stdbool.h>
 
-enum chg_cc_t {
-	CHG_OPEN,
-	CHG_CC1,
-	CHG_CC2
-};
+enum chg_cc_t { CHG_OPEN, CHG_CC1, CHG_CC2 };
 
 enum chg_power_select_t {
 	CHG_POWER_OFF,
diff --git a/board/servo_v4p1/dacs.c b/board/servo_v4p1/dacs.c
index 838cdbbc8b..355e27684b 100644
--- a/board/servo_v4p1/dacs.c
+++ b/board/servo_v4p1/dacs.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,17 +14,17 @@
 #define CC1_DAC_ADDR 0x48
 #define CC2_DAC_ADDR 0x49
 
-#define REG_NOOP    0
-#define REG_DEVID   1
-#define REG_SYNC    2
-#define REG_CONFIG  3
-#define REG_GAIN    4
+#define REG_NOOP 0
+#define REG_DEVID 1
+#define REG_SYNC 2
+#define REG_CONFIG 3
+#define REG_GAIN 4
 #define REG_TRIGGER 5
-#define REG_STATUS  7
-#define REG_DAC     8
+#define REG_STATUS 7
+#define REG_DAC 8
 
-#define DAC1	BIT(0)
-#define DAC2	BIT(1)
+#define DAC1 BIT(0)
+#define DAC2 BIT(1)
 
 static uint8_t dac_enabled;
 
@@ -103,7 +103,7 @@ int write_dac(enum dac_t dac, uint16_t value)
 }
 
 #ifdef SECTION_IS_RO
-static int cmd_cc_dac(int argc, char *argv[])
+static int cmd_cc_dac(int argc, const char *argv[])
 {
 	uint8_t dac;
 	uint64_t mv;
@@ -135,7 +135,6 @@ static int cmd_cc_dac(int argc, char *argv[])
 	}
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(cc_dac, cmd_cc_dac,
-			"dac <\"on\"|\"off\"|mv>",
+DECLARE_CONSOLE_COMMAND(cc_dac, cmd_cc_dac, "dac <\"on\"|\"off\"|mv>",
 			"Set Servo v4.1 CC dacs");
 #endif
diff --git a/board/servo_v4p1/dacs.h b/board/servo_v4p1/dacs.h
index bd0ecd67da..4b2028c648 100644
--- a/board/servo_v4p1/dacs.h
+++ b/board/servo_v4p1/dacs.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/servo_v4p1/ec.tasklist b/board/servo_v4p1/ec.tasklist
index 07250f018e..6c9abf1c07 100644
--- a/board/servo_v4p1/ec.tasklist
+++ b/board/servo_v4p1/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/servo_v4p1/fusb302b.c b/board/servo_v4p1/fusb302b.c
index 4e144dec05..e8fdbde68b 100644
--- a/board/servo_v4p1/fusb302b.c
+++ b/board/servo_v4p1/fusb302b.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -72,7 +72,6 @@ int init_fusb302b(int p)
 	if (ret)
 		return ret;
 
-
 	ret = tcpc_read(TCPC_REG_INTERRUPTA, &interrupta);
 	if (ret)
 		return ret;
@@ -159,7 +158,6 @@ int get_cc(int *cc1, int *cc2)
 	else
 		orig_meas_cc2 = 0;
 
-
 	/* Disable CC2 measurement switch, enable CC1 measurement switch */
 	reg &= ~TCPC_REG_SWITCHES0_MEAS_CC2;
 	reg |= TCPC_REG_SWITCHES0_MEAS_CC1;
diff --git a/board/servo_v4p1/fusb302b.h b/board/servo_v4p1/fusb302b.h
index ec89c0c207..cebf5409f5 100644
--- a/board/servo_v4p1/fusb302b.h
+++ b/board/servo_v4p1/fusb302b.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,173 +22,173 @@
 /* FUSB302B11MPX */
 #define FUSB302_I2C_ADDR_B11_FLAGS 0x25
 
-#define TCPC_REG_DEVICE_ID	0x01
-
-#define TCPC_REG_SWITCHES0	0x02
-#define TCPC_REG_SWITCHES0_CC2_PU_EN	(1<<7)
-#define TCPC_REG_SWITCHES0_CC1_PU_EN	(1<<6)
-#define TCPC_REG_SWITCHES0_VCONN_CC2	(1<<5)
-#define TCPC_REG_SWITCHES0_VCONN_CC1	(1<<4)
-#define TCPC_REG_SWITCHES0_MEAS_CC2	(1<<3)
-#define TCPC_REG_SWITCHES0_MEAS_CC1	(1<<2)
-#define TCPC_REG_SWITCHES0_CC2_PD_EN	(1<<1)
-#define TCPC_REG_SWITCHES0_CC1_PD_EN	(1<<0)
-
-#define TCPC_REG_SWITCHES1	0x03
-#define TCPC_REG_SWITCHES1_POWERROLE	(1<<7)
-#define TCPC_REG_SWITCHES1_SPECREV1	(1<<6)
-#define TCPC_REG_SWITCHES1_SPECREV0	(1<<5)
-#define TCPC_REG_SWITCHES1_DATAROLE	(1<<4)
-#define TCPC_REG_SWITCHES1_AUTO_GCRC	(1<<2)
-#define TCPC_REG_SWITCHES1_TXCC2_EN	(1<<1)
-#define TCPC_REG_SWITCHES1_TXCC1_EN	(1<<0)
-
-#define TCPC_REG_MEASURE	0x04
-#define TCPC_REG_MEASURE_MDAC_MASK	0x3F
-#define TCPC_REG_MEASURE_VBUS		(1<<6)
+#define TCPC_REG_DEVICE_ID 0x01
+
+#define TCPC_REG_SWITCHES0 0x02
+#define TCPC_REG_SWITCHES0_CC2_PU_EN (1 << 7)
+#define TCPC_REG_SWITCHES0_CC1_PU_EN (1 << 6)
+#define TCPC_REG_SWITCHES0_VCONN_CC2 (1 << 5)
+#define TCPC_REG_SWITCHES0_VCONN_CC1 (1 << 4)
+#define TCPC_REG_SWITCHES0_MEAS_CC2 (1 << 3)
+#define TCPC_REG_SWITCHES0_MEAS_CC1 (1 << 2)
+#define TCPC_REG_SWITCHES0_CC2_PD_EN (1 << 1)
+#define TCPC_REG_SWITCHES0_CC1_PD_EN (1 << 0)
+
+#define TCPC_REG_SWITCHES1 0x03
+#define TCPC_REG_SWITCHES1_POWERROLE (1 << 7)
+#define TCPC_REG_SWITCHES1_SPECREV1 (1 << 6)
+#define TCPC_REG_SWITCHES1_SPECREV0 (1 << 5)
+#define TCPC_REG_SWITCHES1_DATAROLE (1 << 4)
+#define TCPC_REG_SWITCHES1_AUTO_GCRC (1 << 2)
+#define TCPC_REG_SWITCHES1_TXCC2_EN (1 << 1)
+#define TCPC_REG_SWITCHES1_TXCC1_EN (1 << 0)
+
+#define TCPC_REG_MEASURE 0x04
+#define TCPC_REG_MEASURE_MDAC_MASK 0x3F
+#define TCPC_REG_MEASURE_VBUS (1 << 6)
 /*
  * MDAC reference voltage step size is 42 mV. Round our thresholds to reduce
  * maximum error, which also matches suggested thresholds in datasheet
  * (Table 3. Host Interrupt Summary).
  */
-#define TCPC_REG_MEASURE_MDAC_MV(mv)	(DIV_ROUND_NEAREST((mv), 42) & 0x3f)
-
-#define TCPC_REG_CONTROL0	0x06
-#define TCPC_REG_CONTROL0_TX_FLUSH	(1<<6)
-#define TCPC_REG_CONTROL0_INT_MASK	(1<<5)
-#define TCPC_REG_CONTROL0_HOST_CUR_MASK (3<<2)
-#define TCPC_REG_CONTROL0_HOST_CUR_3A0  (3<<2)
-#define TCPC_REG_CONTROL0_HOST_CUR_1A5  (2<<2)
-#define TCPC_REG_CONTROL0_HOST_CUR_USB  (1<<2)
-#define TCPC_REG_CONTROL0_TX_START	(1<<0)
-
-#define TCPC_REG_CONTROL1	0x07
-#define TCPC_REG_CONTROL1_ENSOP2DB	(1<<6)
-#define TCPC_REG_CONTROL1_ENSOP1DB	(1<<5)
-#define TCPC_REG_CONTROL1_BIST_MODE2	(1<<4)
-#define TCPC_REG_CONTROL1_RX_FLUSH	(1<<2)
-#define TCPC_REG_CONTROL1_ENSOP2	(1<<1)
-#define TCPC_REG_CONTROL1_ENSOP1	(1<<0)
-
-#define TCPC_REG_CONTROL2	0x08
+#define TCPC_REG_MEASURE_MDAC_MV(mv) (DIV_ROUND_NEAREST((mv), 42) & 0x3f)
+
+#define TCPC_REG_CONTROL0 0x06
+#define TCPC_REG_CONTROL0_TX_FLUSH (1 << 6)
+#define TCPC_REG_CONTROL0_INT_MASK (1 << 5)
+#define TCPC_REG_CONTROL0_HOST_CUR_MASK (3 << 2)
+#define TCPC_REG_CONTROL0_HOST_CUR_3A0 (3 << 2)
+#define TCPC_REG_CONTROL0_HOST_CUR_1A5 (2 << 2)
+#define TCPC_REG_CONTROL0_HOST_CUR_USB (1 << 2)
+#define TCPC_REG_CONTROL0_TX_START (1 << 0)
+
+#define TCPC_REG_CONTROL1 0x07
+#define TCPC_REG_CONTROL1_ENSOP2DB (1 << 6)
+#define TCPC_REG_CONTROL1_ENSOP1DB (1 << 5)
+#define TCPC_REG_CONTROL1_BIST_MODE2 (1 << 4)
+#define TCPC_REG_CONTROL1_RX_FLUSH (1 << 2)
+#define TCPC_REG_CONTROL1_ENSOP2 (1 << 1)
+#define TCPC_REG_CONTROL1_ENSOP1 (1 << 0)
+
+#define TCPC_REG_CONTROL2 0x08
 /* two-bit field, valid values below */
-#define TCPC_REG_CONTROL2_MODE_MASK	(0x3<<TCPC_REG_CONTROL2_MODE_POS)
-#define TCPC_REG_CONTROL2_MODE_DFP	(0x3)
-#define TCPC_REG_CONTROL2_MODE_UFP	(0x2)
-#define TCPC_REG_CONTROL2_MODE_DRP	(0x1)
-#define TCPC_REG_CONTROL2_MODE_POS	(1)
-#define TCPC_REG_CONTROL2_TOGGLE	(1<<0)
-
-#define TCPC_REG_CONTROL3	0x09
-#define TCPC_REG_CONTROL3_SEND_HARDRESET	(1<<6)
-#define TCPC_REG_CONTROL3_BIST_TMODE		(1<<5) /* 302B Only */
-#define TCPC_REG_CONTROL3_AUTO_HARDRESET	(1<<4)
-#define TCPC_REG_CONTROL3_AUTO_SOFTRESET	(1<<3)
+#define TCPC_REG_CONTROL2_MODE_MASK (0x3 << TCPC_REG_CONTROL2_MODE_POS)
+#define TCPC_REG_CONTROL2_MODE_DFP (0x3)
+#define TCPC_REG_CONTROL2_MODE_UFP (0x2)
+#define TCPC_REG_CONTROL2_MODE_DRP (0x1)
+#define TCPC_REG_CONTROL2_MODE_POS (1)
+#define TCPC_REG_CONTROL2_TOGGLE (1 << 0)
+
+#define TCPC_REG_CONTROL3 0x09
+#define TCPC_REG_CONTROL3_SEND_HARDRESET (1 << 6)
+#define TCPC_REG_CONTROL3_BIST_TMODE (1 << 5) /* 302B Only */
+#define TCPC_REG_CONTROL3_AUTO_HARDRESET (1 << 4)
+#define TCPC_REG_CONTROL3_AUTO_SOFTRESET (1 << 3)
 /* two-bit field */
-#define TCPC_REG_CONTROL3_N_RETRIES		(1<<1)
-#define TCPC_REG_CONTROL3_N_RETRIES_POS		(1)
-#define TCPC_REG_CONTROL3_N_RETRIES_SIZE	(2)
-#define TCPC_REG_CONTROL3_AUTO_RETRY		(1<<0)
-
-#define TCPC_REG_MASK		0x0A
-#define TCPC_REG_MASK_VBUSOK		(1<<7)
-#define TCPC_REG_MASK_ACTIVITY		(1<<6)
-#define TCPC_REG_MASK_COMP_CHNG		(1<<5)
-#define TCPC_REG_MASK_CRC_CHK		(1<<4)
-#define TCPC_REG_MASK_ALERT		(1<<3)
-#define TCPC_REG_MASK_WAKE		(1<<2)
-#define TCPC_REG_MASK_COLLISION		(1<<1)
-#define TCPC_REG_MASK_BC_LVL		(1<<0)
-
-#define TCPC_REG_POWER		0x0B
-#define TCPC_REG_POWER_PWR		(1<<0)	/* four-bit field */
-#define TCPC_REG_POWER_PWR_LOW		0x1 /* Bandgap + Wake circuitry */
-#define TCPC_REG_POWER_PWR_MEDIUM	0x3 /* LOW + Receiver + Current refs */
-#define TCPC_REG_POWER_PWR_HIGH		0x7 /* MEDIUM + Measure block */
-#define TCPC_REG_POWER_PWR_ALL		0xF /* HIGH + Internal Oscillator */
-
-#define TCPC_REG_RESET		0x0C
-#define TCPC_REG_RESET_PD_RESET		(1<<1)
-#define TCPC_REG_RESET_SW_RESET		(1<<0)
-
-#define TCPC_REG_MASKA		0x0E
-#define TCPC_REG_MASKA_OCP_TEMP		(1<<7)
-#define TCPC_REG_MASKA_TOGDONE		(1<<6)
-#define TCPC_REG_MASKA_SOFTFAIL		(1<<5)
-#define TCPC_REG_MASKA_RETRYFAIL	(1<<4)
-#define TCPC_REG_MASKA_HARDSENT		(1<<3)
-#define TCPC_REG_MASKA_TX_SUCCESS	(1<<2)
-#define TCPC_REG_MASKA_SOFTRESET	(1<<1)
-#define TCPC_REG_MASKA_HARDRESET	(1<<0)
-
-#define TCPC_REG_MASKB		0x0F
-#define TCPC_REG_MASKB_GCRCSENT		(1<<0)
-
-#define TCPC_REG_STATUS0A	0x3C
-#define TCPC_REG_STATUS0A_SOFTFAIL	(1<<5)
-#define TCPC_REG_STATUS0A_RETRYFAIL	(1<<4)
-#define TCPC_REG_STATUS0A_POWER		(1<<2) /* two-bit field */
-#define TCPC_REG_STATUS0A_RX_SOFT_RESET	(1<<1)
-#define TCPC_REG_STATUS0A_RX_HARD_RESEt	(1<<0)
-
-#define TCPC_REG_STATUS1A	0x3D
+#define TCPC_REG_CONTROL3_N_RETRIES (1 << 1)
+#define TCPC_REG_CONTROL3_N_RETRIES_POS (1)
+#define TCPC_REG_CONTROL3_N_RETRIES_SIZE (2)
+#define TCPC_REG_CONTROL3_AUTO_RETRY (1 << 0)
+
+#define TCPC_REG_MASK 0x0A
+#define TCPC_REG_MASK_VBUSOK (1 << 7)
+#define TCPC_REG_MASK_ACTIVITY (1 << 6)
+#define TCPC_REG_MASK_COMP_CHNG (1 << 5)
+#define TCPC_REG_MASK_CRC_CHK (1 << 4)
+#define TCPC_REG_MASK_ALERT (1 << 3)
+#define TCPC_REG_MASK_WAKE (1 << 2)
+#define TCPC_REG_MASK_COLLISION (1 << 1)
+#define TCPC_REG_MASK_BC_LVL (1 << 0)
+
+#define TCPC_REG_POWER 0x0B
+#define TCPC_REG_POWER_PWR (1 << 0) /* four-bit field */
+#define TCPC_REG_POWER_PWR_LOW 0x1 /* Bandgap + Wake circuitry */
+#define TCPC_REG_POWER_PWR_MEDIUM 0x3 /* LOW + Receiver + Current refs */
+#define TCPC_REG_POWER_PWR_HIGH 0x7 /* MEDIUM + Measure block */
+#define TCPC_REG_POWER_PWR_ALL 0xF /* HIGH + Internal Oscillator */
+
+#define TCPC_REG_RESET 0x0C
+#define TCPC_REG_RESET_PD_RESET (1 << 1)
+#define TCPC_REG_RESET_SW_RESET (1 << 0)
+
+#define TCPC_REG_MASKA 0x0E
+#define TCPC_REG_MASKA_OCP_TEMP (1 << 7)
+#define TCPC_REG_MASKA_TOGDONE (1 << 6)
+#define TCPC_REG_MASKA_SOFTFAIL (1 << 5)
+#define TCPC_REG_MASKA_RETRYFAIL (1 << 4)
+#define TCPC_REG_MASKA_HARDSENT (1 << 3)
+#define TCPC_REG_MASKA_TX_SUCCESS (1 << 2)
+#define TCPC_REG_MASKA_SOFTRESET (1 << 1)
+#define TCPC_REG_MASKA_HARDRESET (1 << 0)
+
+#define TCPC_REG_MASKB 0x0F
+#define TCPC_REG_MASKB_GCRCSENT (1 << 0)
+
+#define TCPC_REG_STATUS0A 0x3C
+#define TCPC_REG_STATUS0A_SOFTFAIL (1 << 5)
+#define TCPC_REG_STATUS0A_RETRYFAIL (1 << 4)
+#define TCPC_REG_STATUS0A_POWER (1 << 2) /* two-bit field */
+#define TCPC_REG_STATUS0A_RX_SOFT_RESET (1 << 1)
+#define TCPC_REG_STATUS0A_RX_HARD_RESEt (1 << 0)
+
+#define TCPC_REG_STATUS1A 0x3D
 /* three-bit field, valid values below */
-#define TCPC_REG_STATUS1A_TOGSS		(1<<3)
-#define TCPC_REG_STATUS1A_TOGSS_RUNNING		0x0
-#define TCPC_REG_STATUS1A_TOGSS_SRC1		0x1
-#define TCPC_REG_STATUS1A_TOGSS_SRC2		0x2
-#define TCPC_REG_STATUS1A_TOGSS_SNK1		0x5
-#define TCPC_REG_STATUS1A_TOGSS_SNK2		0x6
-#define TCPC_REG_STATUS1A_TOGSS_AA		0x7
-#define TCPC_REG_STATUS1A_TOGSS_POS		(3)
-#define TCPC_REG_STATUS1A_TOGSS_MASK		(0x7)
-
-#define TCPC_REG_STATUS1A_RXSOP2DB	(1<<2)
-#define TCPC_REG_STATUS1A_RXSOP1DB	(1<<1)
-#define TCPC_REG_STATUS1A_RXSOP		(1<<0)
-
-#define TCPC_REG_INTERRUPTA	0x3E
-#define TCPC_REG_INTERRUPTA_OCP_TEMP	(1<<7)
-#define TCPC_REG_INTERRUPTA_TOGDONE	(1<<6)
-#define TCPC_REG_INTERRUPTA_SOFTFAIL	(1<<5)
-#define TCPC_REG_INTERRUPTA_RETRYFAIL	(1<<4)
-#define TCPC_REG_INTERRUPTA_HARDSENT	(1<<3)
-#define TCPC_REG_INTERRUPTA_TX_SUCCESS	(1<<2)
-#define TCPC_REG_INTERRUPTA_SOFTRESET	(1<<1)
-#define TCPC_REG_INTERRUPTA_HARDRESET	(1<<0)
-
-#define TCPC_REG_INTERRUPTB	0x3F
-#define TCPC_REG_INTERRUPTB_GCRCSENT		(1<<0)
-
-#define TCPC_REG_STATUS0	0x40
-#define TCPC_REG_STATUS0_VBUSOK		(1<<7)
-#define TCPC_REG_STATUS0_ACTIVITY	(1<<6)
-#define TCPC_REG_STATUS0_COMP		(1<<5)
-#define TCPC_REG_STATUS0_CRC_CHK	(1<<4)
-#define TCPC_REG_STATUS0_ALERT		(1<<3)
-#define TCPC_REG_STATUS0_WAKE		(1<<2)
-#define TCPC_REG_STATUS0_BC_LVL1	(1<<1) /* two-bit field */
-#define TCPC_REG_STATUS0_BC_LVL0	(1<<0) /* two-bit field */
-
-#define TCPC_REG_STATUS1	0x41
-#define TCPC_REG_STATUS1_RXSOP2		(1<<7)
-#define TCPC_REG_STATUS1_RXSOP1		(1<<6)
-#define TCPC_REG_STATUS1_RX_EMPTY	(1<<5)
-#define TCPC_REG_STATUS1_RX_FULL	(1<<4)
-#define TCPC_REG_STATUS1_TX_EMPTY	(1<<3)
-#define TCPC_REG_STATUS1_TX_FULL	(1<<2)
-
-#define TCPC_REG_INTERRUPT	0x42
-#define TCPC_REG_INTERRUPT_VBUSOK	(1<<7)
-#define TCPC_REG_INTERRUPT_ACTIVITY	(1<<6)
-#define TCPC_REG_INTERRUPT_COMP_CHNG	(1<<5)
-#define TCPC_REG_INTERRUPT_CRC_CHK	(1<<4)
-#define TCPC_REG_INTERRUPT_ALERT	(1<<3)
-#define TCPC_REG_INTERRUPT_WAKE		(1<<2)
-#define TCPC_REG_INTERRUPT_COLLISION	(1<<1)
-#define TCPC_REG_INTERRUPT_BC_LVL	(1<<0)
-
-#define TCPC_REG_FIFOS		0x43
+#define TCPC_REG_STATUS1A_TOGSS (1 << 3)
+#define TCPC_REG_STATUS1A_TOGSS_RUNNING 0x0
+#define TCPC_REG_STATUS1A_TOGSS_SRC1 0x1
+#define TCPC_REG_STATUS1A_TOGSS_SRC2 0x2
+#define TCPC_REG_STATUS1A_TOGSS_SNK1 0x5
+#define TCPC_REG_STATUS1A_TOGSS_SNK2 0x6
+#define TCPC_REG_STATUS1A_TOGSS_AA 0x7
+#define TCPC_REG_STATUS1A_TOGSS_POS (3)
+#define TCPC_REG_STATUS1A_TOGSS_MASK (0x7)
+
+#define TCPC_REG_STATUS1A_RXSOP2DB (1 << 2)
+#define TCPC_REG_STATUS1A_RXSOP1DB (1 << 1)
+#define TCPC_REG_STATUS1A_RXSOP (1 << 0)
+
+#define TCPC_REG_INTERRUPTA 0x3E
+#define TCPC_REG_INTERRUPTA_OCP_TEMP (1 << 7)
+#define TCPC_REG_INTERRUPTA_TOGDONE (1 << 6)
+#define TCPC_REG_INTERRUPTA_SOFTFAIL (1 << 5)
+#define TCPC_REG_INTERRUPTA_RETRYFAIL (1 << 4)
+#define TCPC_REG_INTERRUPTA_HARDSENT (1 << 3)
+#define TCPC_REG_INTERRUPTA_TX_SUCCESS (1 << 2)
+#define TCPC_REG_INTERRUPTA_SOFTRESET (1 << 1)
+#define TCPC_REG_INTERRUPTA_HARDRESET (1 << 0)
+
+#define TCPC_REG_INTERRUPTB 0x3F
+#define TCPC_REG_INTERRUPTB_GCRCSENT (1 << 0)
+
+#define TCPC_REG_STATUS0 0x40
+#define TCPC_REG_STATUS0_VBUSOK (1 << 7)
+#define TCPC_REG_STATUS0_ACTIVITY (1 << 6)
+#define TCPC_REG_STATUS0_COMP (1 << 5)
+#define TCPC_REG_STATUS0_CRC_CHK (1 << 4)
+#define TCPC_REG_STATUS0_ALERT (1 << 3)
+#define TCPC_REG_STATUS0_WAKE (1 << 2)
+#define TCPC_REG_STATUS0_BC_LVL1 (1 << 1) /* two-bit field */
+#define TCPC_REG_STATUS0_BC_LVL0 (1 << 0) /* two-bit field */
+
+#define TCPC_REG_STATUS1 0x41
+#define TCPC_REG_STATUS1_RXSOP2 (1 << 7)
+#define TCPC_REG_STATUS1_RXSOP1 (1 << 6)
+#define TCPC_REG_STATUS1_RX_EMPTY (1 << 5)
+#define TCPC_REG_STATUS1_RX_FULL (1 << 4)
+#define TCPC_REG_STATUS1_TX_EMPTY (1 << 3)
+#define TCPC_REG_STATUS1_TX_FULL (1 << 2)
+
+#define TCPC_REG_INTERRUPT 0x42
+#define TCPC_REG_INTERRUPT_VBUSOK (1 << 7)
+#define TCPC_REG_INTERRUPT_ACTIVITY (1 << 6)
+#define TCPC_REG_INTERRUPT_COMP_CHNG (1 << 5)
+#define TCPC_REG_INTERRUPT_CRC_CHK (1 << 4)
+#define TCPC_REG_INTERRUPT_ALERT (1 << 3)
+#define TCPC_REG_INTERRUPT_WAKE (1 << 2)
+#define TCPC_REG_INTERRUPT_COLLISION (1 << 1)
+#define TCPC_REG_INTERRUPT_BC_LVL (1 << 0)
+
+#define TCPC_REG_FIFOS 0x43
 
 /* Tokens defined for the FUSB302 TX FIFO */
 enum fusb302_txfifo_tokens {
diff --git a/board/servo_v4p1/gpio.inc b/board/servo_v4p1/gpio.inc
index 070aa90098..fe631aca80 100644
--- a/board/servo_v4p1/gpio.inc
+++ b/board/servo_v4p1/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/servo_v4p1/ina231s.c b/board/servo_v4p1/ina231s.c
index 3382686f3f..637a878ef7 100644
--- a/board/servo_v4p1/ina231s.c
+++ b/board/servo_v4p1/ina231s.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,9 +7,9 @@
 #include "ina2xx.h"
 #include "util.h"
 
-#define PP_DUT_IDX	0
-#define PP_CHG_IDX	1
-#define SR_CHG_IDX	2
+#define PP_DUT_IDX 0
+#define PP_CHG_IDX 1
+#define SR_CHG_IDX 2
 
 void init_ina231s(void)
 {
diff --git a/board/servo_v4p1/ina231s.h b/board/servo_v4p1/ina231s.h
index 9c3804e769..6f0828127b 100644
--- a/board/servo_v4p1/ina231s.h
+++ b/board/servo_v4p1/ina231s.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/servo_v4p1/ioexpanders.c b/board/servo_v4p1/ioexpanders.c
index 46dcbcc167..275804de89 100644
--- a/board/servo_v4p1/ioexpanders.c
+++ b/board/servo_v4p1/ioexpanders.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,22 +9,22 @@
 #include "ioexpander.h"
 #include "ioexpanders.h"
 
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 /******************************************************************************
  * Initialize IOExpanders.
  */
 
-#define PCAL6524HE_PORT			TCA6424A_PORT
-#define PCAL6524HE_ADDR			TCA6424A_ADDR
-#define PCAL6524HE_DEVICE_ID_ADDR	0x7c
-#define PCAL6524HE_DEVICE_ID_REG	0x46
-#define PCAL6524HE_DEVICE_ID0		0
-#define PCAL6524HE_DEVICE_ID1           0x08
-#define PCAL6524HE_DEVICE_ID2           0x30
-#define PCAL6524HE_INT_MASK_REG_PORT1	0x55
-#define PCAL6524HE_INT_MASK_REG_PORT2   0x56
+#define PCAL6524HE_PORT TCA6424A_PORT
+#define PCAL6524HE_ADDR TCA6424A_ADDR
+#define PCAL6524HE_DEVICE_ID_ADDR 0x7c
+#define PCAL6524HE_DEVICE_ID_REG 0x46
+#define PCAL6524HE_DEVICE_ID0 0
+#define PCAL6524HE_DEVICE_ID1 0x08
+#define PCAL6524HE_DEVICE_ID2 0x30
+#define PCAL6524HE_INT_MASK_REG_PORT1 0x55
+#define PCAL6524HE_INT_MASK_REG_PORT2 0x56
 
 static enum servo_board_id board_id_val = BOARD_ID_UNSET;
 
@@ -51,16 +51,16 @@ int init_ioexpanders(void)
 
 	/* Attempt to read the device id register of the PCAL6524HE device */
 	i2c_read_block(PCAL6524HE_PORT, PCAL6524HE_DEVICE_ID_ADDR,
-					PCAL6524HE_DEVICE_ID_REG, dat, 3);
+		       PCAL6524HE_DEVICE_ID_REG, dat, 3);
 
 	if (dat[2] == PCAL6524HE_DEVICE_ID2 &&
-			dat[1] == PCAL6524HE_DEVICE_ID1 &&
-			dat[0] == PCAL6524HE_DEVICE_ID0) {
+	    dat[1] == PCAL6524HE_DEVICE_ID1 &&
+	    dat[0] == PCAL6524HE_DEVICE_ID0) {
 		ccprintf("Detected PCAL6524HE\n");
 		i2c_write8(PCAL6524HE_PORT, PCAL6524HE_ADDR,
-				PCAL6524HE_INT_MASK_REG_PORT1, 0);
+			   PCAL6524HE_INT_MASK_REG_PORT1, 0);
 		i2c_write8(PCAL6524HE_PORT, PCAL6524HE_ADDR,
-				PCAL6524HE_INT_MASK_REG_PORT2, 0xbe);
+			   PCAL6524HE_INT_MASK_REG_PORT2, 0xbe);
 	} else {
 		ccprintf("Detected TCA6424A\n");
 	}
@@ -74,7 +74,7 @@ int init_ioexpanders(void)
 	}
 
 	if ((!!(irqs & HOST_CHRG_DET) != bc12_charger) &&
-		(board_id_det() <= BOARD_ID_REV1)) {
+	    (board_id_det() <= BOARD_ID_REV1)) {
 		CPRINTF("BC1.2 charger %s\n",
 			(irqs & HOST_CHRG_DET) ? "plugged" : "unplugged");
 		bc12_charger = !!(irqs & HOST_CHRG_DET);
@@ -220,8 +220,7 @@ inline int board_id_det(void)
 
 		/* Cache board ID at init */
 		if (ioex_get_port(IOEX_GET_INFO(IOEX_BOARD_ID_DET0)->ioex,
-		    IOEX_GET_INFO(IOEX_BOARD_ID_DET0)->port,
-		    &id))
+				  IOEX_GET_INFO(IOEX_BOARD_ID_DET0)->port, &id))
 			return id;
 
 		/* Board ID consists of bits 5, 4, and 3 */
@@ -296,8 +295,7 @@ inline int read_faults(void)
 	int val;
 
 	ioex_get_port(IOEX_GET_INFO(IOEX_USERVO_FAULT_L)->ioex,
-		      IOEX_GET_INFO(IOEX_USERVO_FAULT_L)->port,
-		      &val);
+		      IOEX_GET_INFO(IOEX_USERVO_FAULT_L)->port, &val);
 
 	return val;
 }
@@ -307,8 +305,7 @@ inline int read_irqs(void)
 	int val;
 
 	ioex_get_port(IOEX_GET_INFO(IOEX_SYS_PWR_IRQ_ODL)->ioex,
-		      IOEX_GET_INFO(IOEX_SYS_PWR_IRQ_ODL)->port,
-		      &val);
+		      IOEX_GET_INFO(IOEX_SYS_PWR_IRQ_ODL)->port, &val);
 
 	return val;
 }
@@ -343,9 +340,7 @@ inline int board_id_det(void)
 		int res;
 
 		/* Cache board ID at init */
-		res = i2c_read8(TCA6416A_PORT,
-				TCA6416A_ADDR,
-				BOARD_ID_DET_PORT,
+		res = i2c_read8(TCA6416A_PORT, TCA6416A_ADDR, BOARD_ID_DET_PORT,
 				&id);
 		if (res != EC_SUCCESS)
 			return res;
diff --git a/board/servo_v4p1/ioexpanders.h b/board/servo_v4p1/ioexpanders.h
index 6565992857..313fea46a4 100644
--- a/board/servo_v4p1/ioexpanders.h
+++ b/board/servo_v4p1/ioexpanders.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,10 +10,7 @@
 #define BOARD_ID_DET_OFFSET 3
 #define BOARD_ID_DET_PORT 1
 
-enum uservo_fastboot_mux_sel_t {
-	MUX_SEL_USERVO = 0,
-	MUX_SEL_FASTBOOT = 1
-};
+enum uservo_fastboot_mux_sel_t { MUX_SEL_USERVO = 0, MUX_SEL_FASTBOOT = 1 };
 
 /*
  * Initialize Ioexpanders
@@ -236,14 +233,14 @@ int get_dut_chg_en(void);
  */
 int host_or_chg_ctl(int en);
 
-#define USERVO_FAULT_L		BIT(0)
-#define USB3_A0_FAULT_L		BIT(1)
-#define USB3_A1_FAULT_L		BIT(2)
-#define USB_DUTCHG_FLT_ODL	BIT(3)
-#define PP3300_DP_FAULT_L	BIT(4)
-#define DAC_BUF1_LATCH_FAULT_L	BIT(5)
-#define DAC_BUF2_LATCH_FAULT_L	BIT(6)
-#define PP5000_SRC_SEL		BIT(7)
+#define USERVO_FAULT_L BIT(0)
+#define USB3_A0_FAULT_L BIT(1)
+#define USB3_A1_FAULT_L BIT(2)
+#define USB_DUTCHG_FLT_ODL BIT(3)
+#define PP3300_DP_FAULT_L BIT(4)
+#define DAC_BUF1_LATCH_FAULT_L BIT(5)
+#define DAC_BUF2_LATCH_FAULT_L BIT(6)
+#define PP5000_SRC_SEL BIT(7)
 
 /**
  * Read any faults that may have occurred. A fault has occurred if the
@@ -271,8 +268,8 @@ int host_or_chg_ctl(int en);
  */
 int read_faults(void);
 
-#define HOST_CHRG_DET	BIT(0)
-#define SYS_PWR_IRQ_ODL	BIT(6)
+#define HOST_CHRG_DET BIT(0)
+#define SYS_PWR_IRQ_ODL BIT(6)
 
 /**
  * Read irqs which indicate some system event.
diff --git a/board/servo_v4p1/pathsel.c b/board/servo_v4p1/pathsel.c
index 7b71fba169..eba1733e05 100644
--- a/board/servo_v4p1/pathsel.c
+++ b/board/servo_v4p1/pathsel.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/servo_v4p1/pathsel.h b/board/servo_v4p1/pathsel.h
index 7365d3adf3..5f228aceb9 100644
--- a/board/servo_v4p1/pathsel.h
+++ b/board/servo_v4p1/pathsel.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/servo_v4p1/pi3usb9201.c b/board/servo_v4p1/pi3usb9201.c
index 102eaf790d..976c213c49 100644
--- a/board/servo_v4p1/pi3usb9201.c
+++ b/board/servo_v4p1/pi3usb9201.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,7 @@
 #include "i2c.h"
 #include "pi3usb9201.h"
 
-#define PI3USB9201_ADDR	0x5f
+#define PI3USB9201_ADDR 0x5f
 
 inline void init_pi3usb9201(void)
 {
@@ -19,7 +19,7 @@ inline void init_pi3usb9201(void)
 }
 
 inline void write_pi3usb9201(enum pi3usb9201_reg_t reg,
-					enum pi3usb9201_dat_t dat)
+			     enum pi3usb9201_dat_t dat)
 {
 	i2c_write8(1, PI3USB9201_ADDR, reg, dat);
 }
diff --git a/board/servo_v4p1/pi3usb9201.h b/board/servo_v4p1/pi3usb9201.h
index 826db8b871..863fc4129a 100644
--- a/board/servo_v4p1/pi3usb9201.h
+++ b/board/servo_v4p1/pi3usb9201.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,35 +6,29 @@
 #ifndef __CROS_EC_PI3USB9201_H
 #define __CROS_EC_PI3USB9201_H
 
-enum pi3usb9201_reg_t {
-	CTRL_REG1,
-	CTRL_REG2,
-	CLIENT_STATUS,
-	HOST_STATUS
-};
+enum pi3usb9201_reg_t { CTRL_REG1, CTRL_REG2, CLIENT_STATUS, HOST_STATUS };
 
 enum pi3usb9201_dat_t {
-	POWER_DOWN	= 0x0,
-	SDP_HOST_MODE	= 0x2,
-	DCP_HOST_MODE	= 0x4,
-	CDP_HOST_MODE	= 0x6,
-	CLIENT_MODE	= 0x8,
-	USB_PATH_ON	= 0xe
+	POWER_DOWN = 0x0,
+	SDP_HOST_MODE = 0x2,
+	DCP_HOST_MODE = 0x4,
+	CDP_HOST_MODE = 0x6,
+	CLIENT_MODE = 0x8,
+	USB_PATH_ON = 0xe
 };
 
-
 /* Client Status bits */
-#define CS_DCP			BIT(7)
-#define CS_SDP			BIT(6)
-#define CS_CDP			BIT(5)
-#define CS_1A_CHARGER		BIT(3)
-#define CS_2A_CHARGER		BIT(2)
-#define CS_2_4A_CHARGER		BIT(1)
+#define CS_DCP BIT(7)
+#define CS_SDP BIT(6)
+#define CS_CDP BIT(5)
+#define CS_1A_CHARGER BIT(3)
+#define CS_2A_CHARGER BIT(2)
+#define CS_2_4A_CHARGER BIT(1)
 
 /* Host Status bits */
-#define HS_USB_UNPLUGGED	BIT(2)
-#define HS_USB_PLUGGED		BIT(1)
-#define HS_BC1_2		BIT(0)
+#define HS_USB_UNPLUGGED BIT(2)
+#define HS_USB_PLUGGED BIT(1)
+#define HS_BC1_2 BIT(0)
 
 /**
  * Selects Client Mode and client mode detection
diff --git a/board/servo_v4p1/usb_pd_config.h b/board/servo_v4p1/usb_pd_config.h
index 7e97d68a11..e65ed3cd62 100644
--- a/board/servo_v4p1/usb_pd_config.h
+++ b/board/servo_v4p1/usb_pd_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -47,26 +47,27 @@
 #define CONFIG_HW_CRC
 
 /* Servo v4 CC configuration */
-#define CC_DETACH	BIT(0)   /* Emulate detach: both CC open */
-#define CC_DISABLE_DTS	BIT(1)   /* Apply resistors to single or both CC? */
-#define CC_ALLOW_SRC	BIT(2)   /* Allow charge through by policy? */
-#define CC_ENABLE_DRP	BIT(3)   /* Enable dual-role port */
-#define CC_SNK_WITH_PD	BIT(4)   /* Force enabling PD comm for sink role */
-#define CC_POLARITY	BIT(5)   /* CC polarity */
-#define CC_EMCA_SERVO	BIT(6)   /*
-				  * Emulate Electronically Marked Cable Assembly
-				  * (EMCA) servo (or non-EMCA)
-				  */
-#define CC_FASTBOOT_DFP	BIT(7)   /* Allow mux uServo->Fastboot on DFP */
+#define CC_DETACH BIT(0) /* Emulate detach: both CC open */
+#define CC_DISABLE_DTS BIT(1) /* Apply resistors to single or both CC? */
+#define CC_ALLOW_SRC BIT(2) /* Allow charge through by policy? */
+#define CC_ENABLE_DRP BIT(3) /* Enable dual-role port */
+#define CC_SNK_WITH_PD BIT(4) /* Force enabling PD comm for sink role */
+#define CC_POLARITY BIT(5) /* CC polarity */
+#define CC_EMCA_SERVO                                          \
+	BIT(6) /*                                              \
+		* Emulate Electronically Marked Cable Assembly \
+		* (EMCA) servo (or non-EMCA)                   \
+		*/
+#define CC_FASTBOOT_DFP BIT(7) /* Allow mux uServo->Fastboot on DFP */
 
 /* Servo v4 DP alt-mode configuration */
-#define ALT_DP_ENABLE		BIT(0)   /* Enable DP alt-mode or not */
-#define ALT_DP_PIN_C		BIT(1)   /* Pin assignment C supported */
-#define ALT_DP_PIN_D		BIT(2)   /* Pin assignment D supported */
-#define ALT_DP_MF_PREF		BIT(3)   /* Multi-Function preferred */
-#define ALT_DP_PLUG		BIT(4)   /* Plug or receptacle */
-#define ALT_DP_OVERRIDE_HPD	BIT(5)   /* Override the HPD signal */
-#define ALT_DP_HPD_LVL		BIT(6)   /* HPD level if overridden */
+#define ALT_DP_ENABLE BIT(0) /* Enable DP alt-mode or not */
+#define ALT_DP_PIN_C BIT(1) /* Pin assignment C supported */
+#define ALT_DP_PIN_D BIT(2) /* Pin assignment D supported */
+#define ALT_DP_MF_PREF BIT(3) /* Multi-Function preferred */
+#define ALT_DP_PLUG BIT(4) /* Plug or receptacle */
+#define ALT_DP_OVERRIDE_HPD BIT(5) /* Override the HPD signal */
+#define ALT_DP_HPD_LVL BIT(6) /* HPD level if overridden */
 
 /* TX uses SPI1 on PB3-4 for CHG port, SPI2 on PB 13-14 for DUT port */
 #define SPI_REGS(p) ((p) ? STM32_SPI2_REGS : STM32_SPI1_REGS)
@@ -89,14 +90,14 @@ static inline void spi_enable_clock(int port)
 
 #define TIM_TX_CCR_IDX(p) ((p) ? TIM_TX_CCR_DUT : TIM_TX_CCR_CHG)
 #define TIM_RX_CCR_IDX(p) ((p) ? TIM_RX_CCR_DUT : TIM_RX_CCR_CHG)
-#define TIM_CCR_CS  1
+#define TIM_CCR_CS 1
 
 /*
  * EXTI line 21 is connected to the CMP1 output,
  * EXTI line 22 is connected to the CMP2 output,
  * CHG uses CMP2, and DUT uses CMP1.
  */
-#define EXTI_COMP_MASK(p) ((p) ? (1<<21) : BIT(22))
+#define EXTI_COMP_MASK(p) ((p) ? (1 << 21) : BIT(22))
 
 #define IRQ_COMP STM32_IRQ_COMP
 /* triggers packet detection on comparator falling edge */
@@ -188,13 +189,25 @@ static inline void pd_select_polarity(int port, int polarity)
 	if (port == CHG) {
 		/* CHG use the right comparator inverted input for COMP2 */
 		STM32_COMP_CSR = (val & ~STM32_COMP_CMP2INSEL_MASK) |
-			(polarity ? STM32_COMP_CMP2INSEL_INM4  /* PA4: C0_CC2 */
-				  : STM32_COMP_CMP2INSEL_INM6);/* PA2: C0_CC1 */
+				 (polarity ?
+					  STM32_COMP_CMP2INSEL_INM4 /* PA4:
+								       C0_CC2
+								     */
+					  :
+					  STM32_COMP_CMP2INSEL_INM6); /* PA2:
+									 C0_CC1
+								       */
 	} else {
 		/* DUT use the right comparator inverted input for COMP1 */
 		STM32_COMP_CSR = (val & ~STM32_COMP_CMP1INSEL_MASK) |
-			(polarity ? STM32_COMP_CMP1INSEL_INM5  /* PA5: C1_CC2 */
-			 : STM32_COMP_CMP1INSEL_INM6);/* PA0: C1_CC1 */
+				 (polarity ?
+					  STM32_COMP_CMP1INSEL_INM5 /* PA5:
+								       C1_CC2
+								     */
+					  :
+					  STM32_COMP_CMP1INSEL_INM6); /* PA0:
+									 C1_CC1
+								       */
 	}
 }
 
@@ -274,7 +287,6 @@ static inline void pd_config_init(int port, uint8_t power_role)
 
 	/* Initialize TX pins and put them in Hi-Z */
 	pd_tx_init();
-
 }
 
 int pd_adc_read(int port, int cc);
diff --git a/board/servo_v4p1/usb_pd_policy.c b/board/servo_v4p1/usb_pd_policy.c
index 26dc64c7d5..98d6255c29 100644
--- a/board/servo_v4p1/usb_pd_policy.c
+++ b/board/servo_v4p1/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,57 +26,59 @@
 #include "usb_pd_config.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
-#define DUT_PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\
-			     PDO_FIXED_COMM_CAP)
+#define DUT_PDO_FIXED_FLAGS \
+	(PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP | PDO_FIXED_COMM_CAP)
 
 #define CHG_PDO_FIXED_FLAGS (PDO_FIXED_DATA_SWAP)
 
-#define VBUS_UNCHANGED(curr, pend, new) (curr == new && pend == new)
+#define VBUS_UNCHANGED(curr, pend, new) (curr == new &&pend == new)
 
 /* Macros to config the PD role */
 #define CONF_SET_CLEAR(c, set, clear) ((c | (set)) & ~(clear))
-#define CONF_SRC(c) CONF_SET_CLEAR(c, \
-				CC_DISABLE_DTS | CC_ALLOW_SRC, \
-				CC_ENABLE_DRP | CC_SNK_WITH_PD)
-#define CONF_SNK(c) CONF_SET_CLEAR(c, \
-				CC_DISABLE_DTS, \
-				CC_ALLOW_SRC | CC_ENABLE_DRP | CC_SNK_WITH_PD)
-#define CONF_PDSNK(c) CONF_SET_CLEAR(c, \
-				CC_DISABLE_DTS | CC_SNK_WITH_PD, \
-				CC_ALLOW_SRC | CC_ENABLE_DRP)
-#define CONF_DRP(c) CONF_SET_CLEAR(c, \
-				CC_DISABLE_DTS | CC_ALLOW_SRC | CC_ENABLE_DRP, \
-				CC_SNK_WITH_PD)
-#define CONF_SRCDTS(c) CONF_SET_CLEAR(c, \
-				CC_ALLOW_SRC, \
-				CC_ENABLE_DRP | CC_DISABLE_DTS | CC_SNK_WITH_PD)
-#define CONF_SNKDTS(c) CONF_SET_CLEAR(c, \
-				0, \
-				CC_ALLOW_SRC | CC_ENABLE_DRP | \
-				CC_DISABLE_DTS | CC_SNK_WITH_PD)
-#define CONF_PDSNKDTS(c) CONF_SET_CLEAR(c, \
-				CC_SNK_WITH_PD, \
-				CC_ALLOW_SRC | CC_ENABLE_DRP | CC_DISABLE_DTS)
-#define CONF_DRPDTS(c) CONF_SET_CLEAR(c, \
-				CC_ALLOW_SRC | CC_ENABLE_DRP, \
-				CC_DISABLE_DTS | CC_SNK_WITH_PD)
+#define CONF_SRC(c)                                      \
+	CONF_SET_CLEAR(c, CC_DISABLE_DTS | CC_ALLOW_SRC, \
+		       CC_ENABLE_DRP | CC_SNK_WITH_PD)
+#define CONF_SNK(c)                       \
+	CONF_SET_CLEAR(c, CC_DISABLE_DTS, \
+		       CC_ALLOW_SRC | CC_ENABLE_DRP | CC_SNK_WITH_PD)
+#define CONF_PDSNK(c)                                      \
+	CONF_SET_CLEAR(c, CC_DISABLE_DTS | CC_SNK_WITH_PD, \
+		       CC_ALLOW_SRC | CC_ENABLE_DRP)
+#define CONF_DRP(c)                                                      \
+	CONF_SET_CLEAR(c, CC_DISABLE_DTS | CC_ALLOW_SRC | CC_ENABLE_DRP, \
+		       CC_SNK_WITH_PD)
+#define CONF_SRCDTS(c)                  \
+	CONF_SET_CLEAR(c, CC_ALLOW_SRC, \
+		       CC_ENABLE_DRP | CC_DISABLE_DTS | CC_SNK_WITH_PD)
+#define CONF_SNKDTS(c)                                                 \
+	CONF_SET_CLEAR(c, 0,                                           \
+		       CC_ALLOW_SRC | CC_ENABLE_DRP | CC_DISABLE_DTS | \
+			       CC_SNK_WITH_PD)
+#define CONF_PDSNKDTS(c)                  \
+	CONF_SET_CLEAR(c, CC_SNK_WITH_PD, \
+		       CC_ALLOW_SRC | CC_ENABLE_DRP | CC_DISABLE_DTS)
+#define CONF_DRPDTS(c)                                  \
+	CONF_SET_CLEAR(c, CC_ALLOW_SRC | CC_ENABLE_DRP, \
+		       CC_DISABLE_DTS | CC_SNK_WITH_PD)
+#define CONF_DTSOFF(c) CONF_SET_CLEAR(c, CC_DISABLE_DTS, 0)
+#define CONF_DTSON(c) CONF_SET_CLEAR(c, 0, CC_DISABLE_DTS)
 
 /* Macros to apply Rd/Rp to CC lines */
-#define DUT_ACTIVE_CC_SET(r, flags) \
-	gpio_set_flags(cc_config & CC_POLARITY ? \
-				CONCAT2(GPIO_USB_DUT_CC2_, r) : \
-				CONCAT2(GPIO_USB_DUT_CC1_, r), \
+#define DUT_ACTIVE_CC_SET(r, flags)                            \
+	gpio_set_flags(cc_config &CC_POLARITY ?                \
+			       CONCAT2(GPIO_USB_DUT_CC2_, r) : \
+			       CONCAT2(GPIO_USB_DUT_CC1_, r),  \
 		       flags)
-#define DUT_INACTIVE_CC_SET(r, flags) \
-	gpio_set_flags(cc_config & CC_POLARITY ? \
-				CONCAT2(GPIO_USB_DUT_CC1_, r) : \
-				CONCAT2(GPIO_USB_DUT_CC2_, r), \
+#define DUT_INACTIVE_CC_SET(r, flags)                          \
+	gpio_set_flags(cc_config &CC_POLARITY ?                \
+			       CONCAT2(GPIO_USB_DUT_CC1_, r) : \
+			       CONCAT2(GPIO_USB_DUT_CC2_, r),  \
 		       flags)
-#define DUT_BOTH_CC_SET(r, flags) \
-	do { \
+#define DUT_BOTH_CC_SET(r, flags)                                     \
+	do {                                                          \
 		gpio_set_flags(CONCAT2(GPIO_USB_DUT_CC1_, r), flags); \
 		gpio_set_flags(CONCAT2(GPIO_USB_DUT_CC2_, r), flags); \
 	} while (0)
@@ -98,15 +100,15 @@
  * than 5V.
  */
 static const uint16_t pd_src_voltages_mv[] = {
-		5000, 9000, 10000, 12000, 15000, 20000,
+	5000, 9000, 10000, 12000, 15000, 20000,
 };
 static uint32_t pd_src_chg_pdo[ARRAY_SIZE(pd_src_voltages_mv)];
 static uint8_t chg_pdo_cnt;
 
 const uint32_t pd_snk_pdo[] = {
-		PDO_FIXED(5000, 500, CHG_PDO_FIXED_FLAGS),
-		PDO_BATT(4750, 21000, 15000),
-		PDO_VAR(4750, 21000, 3000),
+	PDO_FIXED(5000, 500, CHG_PDO_FIXED_FLAGS),
+	PDO_BATT(4750, 21000, 15000),
+	PDO_VAR(4750, 21000, 3000),
 };
 const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
 
@@ -123,15 +125,15 @@ static int cc_config = CC_ALLOW_SRC | CC_EMCA_SERVO;
 
 /* Voltage thresholds for no connect in DTS mode */
 static int pd_src_vnc_dts[TYPEC_RP_RESERVED][2] = {
-	{PD_SRC_3_0_VNC_MV, PD_SRC_1_5_VNC_MV},
-	{PD_SRC_1_5_VNC_MV, PD_SRC_DEF_VNC_MV},
-	{PD_SRC_3_0_VNC_MV, PD_SRC_DEF_VNC_MV},
+	{ PD_SRC_3_0_VNC_MV, PD_SRC_1_5_VNC_MV },
+	{ PD_SRC_1_5_VNC_MV, PD_SRC_DEF_VNC_MV },
+	{ PD_SRC_3_0_VNC_MV, PD_SRC_DEF_VNC_MV },
 };
 /* Voltage thresholds for Ra attach in DTS mode */
 static int pd_src_rd_threshold_dts[TYPEC_RP_RESERVED][2] = {
-	{PD_SRC_3_0_RD_THRESH_MV, PD_SRC_1_5_RD_THRESH_MV},
-	{PD_SRC_1_5_RD_THRESH_MV, PD_SRC_DEF_RD_THRESH_MV},
-	{PD_SRC_3_0_RD_THRESH_MV, PD_SRC_DEF_RD_THRESH_MV},
+	{ PD_SRC_3_0_RD_THRESH_MV, PD_SRC_1_5_RD_THRESH_MV },
+	{ PD_SRC_1_5_RD_THRESH_MV, PD_SRC_DEF_RD_THRESH_MV },
+	{ PD_SRC_3_0_RD_THRESH_MV, PD_SRC_DEF_RD_THRESH_MV },
 };
 /* Voltage thresholds for no connect in normal SRC mode */
 static int pd_src_vnc[TYPEC_RP_RESERVED] = {
@@ -291,8 +293,8 @@ static void update_ports(void)
 					break;
 
 				/* Find the 'best' PDO <= voltage */
-				pdo_index =
-				pd_find_pdo_index(pd_get_src_cap_cnt(CHG),
+				pdo_index = pd_find_pdo_index(
+					pd_get_src_cap_cnt(CHG),
 					pd_get_src_caps(CHG),
 					pd_src_voltages_mv[i], &pdo);
 				/* Don't duplicate PDOs */
@@ -315,9 +317,9 @@ static void update_ports(void)
 		} else {
 			/* 5V PDO */
 			pd_src_chg_pdo[0] = PDO_FIXED_VOLT(PD_MIN_MV) |
-				PDO_FIXED_CURR(vbus[CHG].ma) |
-				DUT_PDO_FIXED_FLAGS |
-				PDO_FIXED_UNCONSTRAINED;
+					    PDO_FIXED_CURR(vbus[CHG].ma) |
+					    DUT_PDO_FIXED_FLAGS |
+					    PDO_FIXED_UNCONSTRAINED;
 
 			chg_pdo_cnt = 1;
 		}
@@ -342,8 +344,8 @@ int board_set_active_charge_port(int charge_port)
 	return 0;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	if (port != CHG)
 		return;
@@ -389,8 +391,9 @@ int pd_tcpc_cc_nc(int port, int cc_volt, int cc_sel)
 	if (cc_config & CC_DISABLE_DTS)
 		nc = cc_volt >= pd_src_vnc[rp_index];
 	else
-		nc = cc_volt >= pd_src_vnc_dts[rp_index][
-				cc_config & CC_POLARITY ? !cc_sel : cc_sel];
+		nc = cc_volt >=
+		     pd_src_vnc_dts[rp_index]
+				   [cc_config & CC_POLARITY ? !cc_sel : cc_sel];
 
 	return nc;
 }
@@ -416,8 +419,10 @@ int pd_tcpc_cc_ra(int port, int cc_volt, int cc_sel)
 	if (cc_config & CC_DISABLE_DTS)
 		ra = cc_volt < pd_src_rd_threshold[rp_index];
 	else
-		ra = cc_volt < pd_src_rd_threshold_dts[rp_index][
-				cc_config & CC_POLARITY ? !cc_sel : cc_sel];
+		ra = cc_volt <
+		     pd_src_rd_threshold_dts[rp_index]
+					    [cc_config & CC_POLARITY ? !cc_sel :
+								       cc_sel];
 
 	return ra;
 }
@@ -459,13 +464,11 @@ int pd_adc_read(int port, int cc)
 		 *
 		 * This is basically a hack faking "vOpen" from TCPCI spec.
 		 */
-		if ((cc_config & CC_DISABLE_DTS) &&
-		    port == DUT &&
+		if ((cc_config & CC_DISABLE_DTS) && port == DUT &&
 		    cc == ((cc_config & CC_POLARITY) ? 0 : 1)) {
-
-			if ((cc_pull_stored == TYPEC_CC_RD)  ||
-				(cc_pull_stored == TYPEC_CC_RA) ||
-				(cc_pull_stored == TYPEC_CC_RA_RD))
+			if ((cc_pull_stored == TYPEC_CC_RD) ||
+			    (cc_pull_stored == TYPEC_CC_RA) ||
+			    (cc_pull_stored == TYPEC_CC_RA_RD))
 				mv = -1;
 			else if (cc_pull_stored == TYPEC_CC_RP)
 				mv = 3301;
@@ -594,7 +597,7 @@ int pd_set_rp_rd(int port, int cc_pull, int rp_value)
 	if (cc_pull == TYPEC_CC_RP) {
 		rv = board_set_rp(rp_value);
 	} else if ((cc_pull == TYPEC_CC_RD) || (cc_pull == TYPEC_CC_RA_RD) ||
-				(cc_pull == TYPEC_CC_RA)) {
+		   (cc_pull == TYPEC_CC_RA)) {
 		/*
 		 * The DUT port uses a captive cable. It can present Rd on both
 		 * CC1 and CC2. If DTS mode is enabled, then present Rd on both
@@ -673,7 +676,7 @@ int charge_manager_get_source_pdo(const uint32_t **src_pdo, const int port)
 	 * port, otherwise we provide no power.
 	 */
 	if (charge_port_is_active()) {
-		*src_pdo =  pd_src_chg_pdo;
+		*src_pdo = pd_src_chg_pdo;
 		pdo_cnt = chg_pdo_cnt;
 	}
 
@@ -697,8 +700,7 @@ __override void pd_transition_voltage(int idx)
 		/* Wait for CHG transition */
 		deadline.val = get_time().val + PD_T_PS_TRANSITION;
 		CPRINTS("Waiting for CHG port transition");
-		while (charge_port_is_active() &&
-		       vbus[CHG].mv != mv &&
+		while (charge_port_is_active() && vbus[CHG].mv != mv &&
 		       get_time().val < deadline.val)
 			msleep(10);
 
@@ -760,8 +762,7 @@ void pd_power_supply_reset(int port)
 
 int pd_snk_is_vbus_provided(int port)
 {
-	return gpio_get_level(port ? GPIO_USB_DET_PP_DUT :
-				     GPIO_USB_DET_PP_CHG);
+	return gpio_get_level(port ? GPIO_USB_DET_PP_DUT : GPIO_USB_DET_PP_CHG);
 }
 
 __override int pd_check_power_swap(int port)
@@ -778,7 +779,8 @@ __override int pd_check_power_swap(int port)
 	if (port == CHG)
 		return 0;
 
-	if (pd_get_power_role(port) == PD_ROLE_SINK && !(cc_config & CC_ALLOW_SRC))
+	if (pd_get_power_role(port) == PD_ROLE_SINK &&
+	    !(cc_config & CC_ALLOW_SRC))
 		return 0;
 
 	if (pd_snk_is_vbus_provided(CHG))
@@ -787,8 +789,7 @@ __override int pd_check_power_swap(int port)
 	return 0;
 }
 
-__override int pd_check_data_swap(int port,
-				  enum pd_data_role data_role)
+__override int pd_check_data_swap(int port, enum pd_data_role data_role)
 {
 	/*
 	 * Servo should allow data role swaps to let DUT see the USB hub, but
@@ -800,8 +801,7 @@ __override int pd_check_data_swap(int port,
 	return allow_dr_swap;
 }
 
-__override void pd_execute_data_swap(int port,
-				     enum pd_data_role data_role)
+__override void pd_execute_data_swap(int port, enum pd_data_role data_role)
 {
 	if (port == CHG)
 		return;
@@ -838,12 +838,12 @@ __override void pd_execute_data_swap(int port,
 			uservo_to_host();
 		break;
 	default:
-		CPRINTS("C%d: %s: Invalid data_role:%d", port, __func__,  data_role);
+		CPRINTS("C%d: %s: Invalid data_role:%d", port, __func__,
+			data_role);
 	}
 }
 
-__override void pd_check_pr_role(int port,
-				 enum pd_power_role pr_role,
+__override void pd_check_pr_role(int port, enum pd_power_role pr_role,
 				 int flags)
 {
 	/*
@@ -854,9 +854,7 @@ __override void pd_check_pr_role(int port,
 	 */
 }
 
-__override void pd_check_dr_role(int port,
-				 enum pd_data_role dr_role,
-				 int flags)
+__override void pd_check_dr_role(int port, enum pd_data_role dr_role, int flags)
 {
 	if (port == CHG)
 		return;
@@ -866,15 +864,14 @@ __override void pd_check_dr_role(int port,
 		pd_request_data_swap(port);
 }
 
-
 /* ----------------- Vendor Defined Messages ------------------ */
 /*
  * DP alt-mode config, user configurable.
  * Default is the mode disabled, supporting the C and D pin assignment,
  * multi-function preferred, and a plug.
  */
-static int alt_dp_config = (ALT_DP_PIN_C | ALT_DP_PIN_D | ALT_DP_MF_PREF |
-			    ALT_DP_PLUG);
+static int alt_dp_config =
+	(ALT_DP_PIN_C | ALT_DP_PIN_D | ALT_DP_MF_PREF | ALT_DP_PLUG);
 
 /**
  * Get the pins based on the user config.
@@ -907,8 +904,8 @@ const uint32_t vdo_idh = VDO_IDH(0, /* data caps as USB host */
 const uint32_t vdo_product = VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV);
 
 const uint32_t vdo_ama = VDO_AMA(CONFIG_USB_PD_IDENTITY_HW_VERS,
-				 CONFIG_USB_PD_IDENTITY_SW_VERS,
-				 0, 0, 0, 0, /* SS[TR][12] */
+				 CONFIG_USB_PD_IDENTITY_SW_VERS, 0, 0, 0,
+				 0, /* SS[TR][12] */
 				 0, /* Vconn power */
 				 0, /* Vconn power required */
 				 0, /* Vbus power required */
@@ -946,13 +943,13 @@ uint32_t vdo_dp_mode[MODE_CNT];
 
 static int svdm_response_modes(int port, uint32_t *payload)
 {
-	vdo_dp_mode[0] =
-		VDO_MODE_DP(0,             /* UFP pin cfg supported: none */
-			    alt_dp_config_pins(),  /* DFP pin */
-			    1,             /* no usb2.0 signalling in AMode */
-			    alt_dp_config_cable(), /* plug or receptacle */
-			    MODE_DP_V13,   /* DPv1.3 Support, no Gen2 */
-			    MODE_DP_SNK);  /* Its a sink only */
+	vdo_dp_mode[0] = VDO_MODE_DP(0, /* UFP pin cfg supported: none */
+				     alt_dp_config_pins(), /* DFP pin */
+				     1, /* no usb2.0 signalling in AMode */
+				     alt_dp_config_cable(), /* plug or
+							       receptacle */
+				     MODE_DP_V13, /* DPv1.3 Support, no Gen2 */
+				     MODE_DP_SNK); /* Its a sink only */
 
 	/* CCD uses the SBU lines; don't enable DP when dts-mode enabled */
 	if (!(cc_config & CC_DISABLE_DTS))
@@ -1007,17 +1004,18 @@ static int dp_status(int port, uint32_t *payload)
 	int dp_enabled = !!(state & USB_PD_MUX_DP_ENABLED);
 
 	if (opos != OPOS)
-		return 0;  /* NAK */
-
-	payload[1] = VDO_DP_STATUS(
-		0,                /* IRQ_HPD */
-		hpd,              /* HPD_HI|LOW */
-		0,                /* request exit DP */
-		0,                /* request exit USB */
-		(alt_dp_config & ALT_DP_MF_PREF) != 0,  /* MF pref */
-		dp_enabled,
-		0,                /* power low */
-		hpd ? 0x2 : 0);
+		return 0; /* NAK */
+
+	payload[1] =
+		VDO_DP_STATUS(0, /* IRQ_HPD */
+			      hpd, /* HPD_HI|LOW */
+			      0, /* request exit DP */
+			      0, /* request exit USB */
+			      (alt_dp_config & ALT_DP_MF_PREF) != 0, /* MF
+									pref
+								      */
+			      dp_enabled, 0, /* power low */
+			      hpd ? 0x2 : 0);
 
 	return 2;
 }
@@ -1038,7 +1036,7 @@ static int svdm_enter_mode(int port, uint32_t *payload)
 	/* SID & mode request is valid */
 	if ((PD_VDO_VID(payload[0]) != USB_SID_DISPLAYPORT) ||
 	    (PD_VDO_OPOS(payload[0]) != OPOS))
-		return 0;  /* NAK */
+		return 0; /* NAK */
 
 	alt_mode = OPOS;
 	return 1;
@@ -1080,7 +1078,7 @@ const struct svdm_response svdm_rsp = {
 };
 
 __override int pd_custom_vdm(int port, int cnt, uint32_t *payload,
-		  uint32_t **rpayload)
+			     uint32_t **rpayload)
 {
 	int cmd = PD_VDO_CMD(payload[0]);
 
@@ -1092,7 +1090,7 @@ __override int pd_custom_vdm(int port, int cnt, uint32_t *payload,
 	case VDO_CMD_VERSION:
 		/* guarantee last byte of payload is null character */
 		*(payload + cnt - 1) = 0;
-		CPRINTF("ver: %s\n", (char *)(payload+1));
+		CPRINTF("ver: %s\n", (char *)(payload + 1));
 		break;
 	case VDO_CMD_CURRENT:
 		CPRINTF("Current: %dmA\n", payload[1]);
@@ -1110,18 +1108,15 @@ static void print_cc_mode(void)
 	/* Get current CCD status */
 	ccprintf("cc: %s\n", cc_config & CC_DETACH ? "off" : "on");
 	ccprintf("dts mode: %s\n", cc_config & CC_DISABLE_DTS ? "off" : "on");
-	ccprintf("chg mode: %s\n",
-		 get_dut_chg_en() ? "on" : "off");
+	ccprintf("chg mode: %s\n", get_dut_chg_en() ? "on" : "off");
 	ccprintf("chg allowed: %s\n", cc_config & CC_ALLOW_SRC ? "on" : "off");
 	ccprintf("drp enabled: %s\n", cc_config & CC_ENABLE_DRP ? "on" : "off");
-	ccprintf("cc polarity: %s\n", cc_config & CC_POLARITY ? "cc2" :
-								"cc1");
+	ccprintf("cc polarity: %s\n", cc_config & CC_POLARITY ? "cc2" : "cc1");
 	ccprintf("pd enabled: %s\n", pd_comm_is_enabled(DUT) ? "on" : "off");
-	ccprintf("emca: %s\n", cc_config & CC_EMCA_SERVO ?
-					"emarked" : "non-emarked");
+	ccprintf("emca: %s\n",
+		 cc_config & CC_EMCA_SERVO ? "emarked" : "non-emarked");
 }
 
-
 static void do_cc(int cc_config_new)
 {
 	int chargeable;
@@ -1192,7 +1187,7 @@ static void do_cc(int cc_config_new)
 	}
 }
 
-static int command_cc(int argc, char **argv)
+static int command_cc(int argc, const char **argv)
 {
 	int cc_config_new = cc_config;
 
@@ -1223,6 +1218,10 @@ static int command_cc(int argc, char **argv)
 			cc_config_new = CONF_PDSNKDTS(cc_config_new);
 		else if (!strcasecmp(argv[1], "drpdts"))
 			cc_config_new = CONF_DRPDTS(cc_config_new);
+		else if (!strcasecmp(argv[1], "dtsoff"))
+			cc_config_new = CONF_DTSOFF(cc_config_new);
+		else if (!strcasecmp(argv[1], "dtson"))
+			cc_config_new = CONF_DTSON(cc_config_new);
 		else if (!strcasecmp(argv[1], "emca"))
 			cc_config_new |= CC_EMCA_SERVO;
 		else if (!strcasecmp(argv[1], "nonemca"))
@@ -1245,7 +1244,7 @@ static int command_cc(int argc, char **argv)
 }
 DECLARE_CONSOLE_COMMAND(cc, command_cc,
 			"[off|on|src|snk|pdsnk|drp|srcdts|snkdts|pdsnkdts|"
-			"drpdts|emca|nonemca] [cc1|cc2]",
+			"drpdts|dtsoff|dtson|emca|nonemca] [cc1|cc2]",
 			"Servo_v4 DTS and CHG mode");
 
 static void fake_disconnect_end(void)
@@ -1265,7 +1264,7 @@ static void fake_disconnect_start(void)
 }
 DECLARE_DEFERRED(fake_disconnect_start);
 
-static int cmd_fake_disconnect(int argc, char *argv[])
+static int cmd_fake_disconnect(int argc, const char *argv[])
 {
 	int delay_ms, duration_ms;
 	char *e;
@@ -1287,18 +1286,18 @@ static int cmd_fake_disconnect(int argc, char *argv[])
 	fake_pd_disconnect_duration_us = duration_ms * MSEC;
 	hook_call_deferred(&fake_disconnect_start_data, delay_ms * MSEC);
 
-	ccprintf("Fake disconnect for %d ms starting in %d ms.\n",
-		duration_ms, delay_ms);
+	ccprintf("Fake disconnect for %d ms starting in %d ms.\n", duration_ms,
+		 delay_ms);
 
 	return EC_SUCCESS;
 }
 DECLARE_CONSOLE_COMMAND(fakedisconnect, cmd_fake_disconnect,
 			"<delay_ms> <duration_ms>", NULL);
 
-static int cmd_ada_srccaps(int argc, char *argv[])
+static int cmd_ada_srccaps(int argc, const char *argv[])
 {
 	int i;
-	const uint32_t * const ada_srccaps = pd_get_src_caps(CHG);
+	const uint32_t *const ada_srccaps = pd_get_src_caps(CHG);
 
 	for (i = 0; i < pd_get_src_cap_cnt(CHG); ++i) {
 		uint32_t max_ma, max_mv, unused;
@@ -1314,11 +1313,10 @@ static int cmd_ada_srccaps(int argc, char *argv[])
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(ada_srccaps, cmd_ada_srccaps,
-			"",
+DECLARE_CONSOLE_COMMAND(ada_srccaps, cmd_ada_srccaps, "",
 			"Print adapter SrcCap");
 
-static int cmd_dp_action(int argc, char *argv[])
+static int cmd_dp_action(int argc, const char *argv[])
 {
 	int i;
 	char *e;
@@ -1354,8 +1352,7 @@ static int cmd_dp_action(int argc, char *argv[])
 				}
 			}
 		}
-		CPRINTS("Pins: %s%s",
-			(alt_dp_config & ALT_DP_PIN_C) ? "C" : "",
+		CPRINTS("Pins: %s%s", (alt_dp_config & ALT_DP_PIN_C) ? "C" : "",
 			(alt_dp_config & ALT_DP_PIN_D) ? "D" : "");
 	} else if (!strcasecmp(argv[1], "mf")) {
 		if (argc >= 3) {
@@ -1405,10 +1402,10 @@ static int cmd_dp_action(int argc, char *argv[])
 			}
 		}
 		CPRINTS("HPD source: %s",
-			(alt_dp_config & ALT_DP_OVERRIDE_HPD) ? "overridden"
-							      : "external");
+			(alt_dp_config & ALT_DP_OVERRIDE_HPD) ? "overridden" :
+								"external");
 		CPRINTS("HPD level: %d", get_hpd_level());
-	}  else if (!strcasecmp(argv[1], "help")) {
+	} else if (!strcasecmp(argv[1], "help")) {
 		CPRINTS("Usage: usbc_action dp [enable|disable|hpd|mf|pins|"
 			"plug]");
 	}
@@ -1416,7 +1413,7 @@ static int cmd_dp_action(int argc, char *argv[])
 	return EC_SUCCESS;
 }
 
-static int cmd_usbc_action(int argc, char *argv[])
+static int cmd_usbc_action(int argc, const char *argv[])
 {
 	if (argc >= 2 && !strcasecmp(argv[1], "dp"))
 		return cmd_dp_action(argc - 1, &argv[1]);
diff --git a/board/servo_v4p1/usb_sm.c b/board/servo_v4p1/usb_sm.c
index 94b5e0c08d..4c448b7c9d 100644
--- a/board/servo_v4p1/usb_sm.c
+++ b/board/servo_v4p1/usb_sm.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,8 @@
 #include "util.h"
 
 #ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USB, format, ##args)
 #else /* CONFIG_COMMON_RUNTIME */
 #define CPRINTF(format, args...)
 #define CPRINTS(format, args...)
@@ -22,8 +22,8 @@
 struct internal_ctx {
 	usb_state_ptr last_entered;
 	uint32_t running : 1;
-	uint32_t enter	 : 1;
-	uint32_t exit	 : 1;
+	uint32_t enter : 1;
+	uint32_t exit : 1;
 };
 BUILD_ASSERT(sizeof(struct internal_ctx) ==
 	     member_size(struct sm_ctx, internal));
@@ -64,9 +64,9 @@ static usb_state_ptr shared_parent_state(usb_state_ptr a, usb_state_ptr b)
  * functions.
  */
 static void call_entry_functions(const int port,
-			       struct internal_ctx *const internal,
-			       const usb_state_ptr stop,
-			       const usb_state_ptr current)
+				 struct internal_ctx *const internal,
+				 const usb_state_ptr stop,
+				 const usb_state_ptr current)
 {
 	if (current == stop)
 		return;
@@ -91,7 +91,7 @@ static void call_entry_functions(const int port,
  * during an exit function.
  */
 static void call_exit_functions(const int port, const usb_state_ptr stop,
-			      const usb_state_ptr current)
+				const usb_state_ptr current)
 {
 	if (current == stop)
 		return;
@@ -105,7 +105,7 @@ static void call_exit_functions(const int port, const usb_state_ptr stop,
 void set_state(const int port, struct sm_ctx *const ctx,
 	       const usb_state_ptr new_state)
 {
-	struct internal_ctx * const internal = (void *) ctx->internal;
+	struct internal_ctx *const internal = (void *)ctx->internal;
 	usb_state_ptr last_state;
 	usb_state_ptr shared_parent;
 
@@ -115,8 +115,8 @@ void set_state(const int port, struct sm_ctx *const ctx,
 	 * intended state to transition into.
 	 */
 	if (internal->exit) {
-		CPRINTF("C%d: Ignoring set state to 0x%pP within 0x%pP",
-			port, new_state, ctx->current);
+		CPRINTF("C%d: Ignoring set state to 0x%p within 0x%p", port,
+			new_state, ctx->current);
 		return;
 	}
 
@@ -167,8 +167,8 @@ void set_state(const int port, struct sm_ctx *const ctx,
  * functions.
  */
 static void call_run_functions(const int port,
-			     const struct internal_ctx *const internal,
-			     const usb_state_ptr current)
+			       const struct internal_ctx *const internal,
+			       const usb_state_ptr current)
 {
 	if (!current)
 		return;
@@ -185,7 +185,7 @@ static void call_run_functions(const int port,
 
 void run_state(const int port, struct sm_ctx *const ctx)
 {
-	struct internal_ctx * const internal = (void *) ctx->internal;
+	struct internal_ctx *const internal = (void *)ctx->internal;
 
 	internal->running = true;
 	call_run_functions(port, internal, ctx->current);
diff --git a/board/servo_v4p1/usb_tc_snk_sm.c b/board/servo_v4p1/usb_tc_snk_sm.c
index 95586943bf..d76c2fe24f 100644
--- a/board/servo_v4p1/usb_tc_snk_sm.c
+++ b/board/servo_v4p1/usb_tc_snk_sm.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,15 +14,15 @@
 #include "usb_sm.h"
 #include "usb_tc_sm.h"
 
-#define EVT_TIMEOUT_NEVER  (-1)
-#define EVT_TIMEOUT_5MS    (5 * MSEC)
+#define EVT_TIMEOUT_NEVER (-1)
+#define EVT_TIMEOUT_5MS (5 * MSEC)
 
 /*
  * USB Type-C Sink
  *   See Figure 4-13 in Release 1.4 of USB Type-C Spec.
  */
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 /* Type-C Layer Flags */
 
@@ -36,9 +36,9 @@ enum usb_tc_state {
 static const struct usb_state tc_states[];
 
 /* TypeC Power strings */
-static const char * const pwr2_5_str = "5V/0.5A";
-static const char * const pwr7_5_str = "5V/1.5A";
-static const char * const pwr15_str  = "5V/3A";
+static const char *const pwr2_5_str = "5V/0.5A";
+static const char *const pwr7_5_str = "5V/1.5A";
+static const char *const pwr15_str = "5V/3A";
 
 static struct type_c {
 	/* state machine context */
@@ -101,8 +101,8 @@ static void print_alt_power(void)
 	char const *pwr;
 
 	cc = tc.polarity ? tc.cc2 : tc.cc1;
-	if (cc == TYPEC_CC_VOLT_OPEN ||
-		cc == TYPEC_CC_VOLT_RA || cc == TYPEC_CC_VOLT_RD) {
+	if (cc == TYPEC_CC_VOLT_OPEN || cc == TYPEC_CC_VOLT_RA ||
+	    cc == TYPEC_CC_VOLT_RD) {
 		/* Supply removed or not detected */
 		return;
 	}
diff --git a/board/shotzo/battery.c b/board/shotzo/battery.c
deleted file mode 100644
index f71533accf..0000000000
--- a/board/shotzo/battery.c
+++ /dev/null
@@ -1,349 +0,0 @@
-/* Copyright 2022 The ChromiumOS Authors.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery_fuel_gauge.h"
-#include "charge_state.h"
-#include "common.h"
-
-/*
- * Battery info for all shotzo battery types. Note that the fields
- * start_charging_min/max and charging_min/max are not used for the charger.
- * The effective temperature limits are given by discharging_min/max_c.
- *
- * Fuel Gauge (FG) parameters which are used for determining if the battery
- * is connected, the appropriate ship mode (battery cutoff) command, and the
- * charge/discharge FETs status.
- *
- * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
- * register. For some batteries, the charge/discharge FET bits are set when
- * charging/discharging is active, in other types, these bits set mean that
- * charging/discharging is disabled. Therefore, in addition to the mask for
- * these bits, a disconnect value must be specified. Note that for TI fuel
- * gauge, the charge/discharge FET status is found in Operation Status (0x54),
- * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
- * Operation status which contains the FET status bits.
- *
- * The assumption for battery types supported is that the charge/discharge FET
- * status can be read with a sb_read() command and therefore, only the register
- * address, mask, and disconnect value need to be provided.
- */
-const struct board_batt_params board_battery_info[] = {
-	/* DynaPack CosMX Battery Information */
-	[BATTERY_DYNAPACK_COS] = {
-		.fuel_gauge = {
-			.manuf_name = "333-2C-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0004,
-				.cfet_off_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* DynaPack ATL Battery Information */
-	[BATTERY_DYNAPACK_ATL] = {
-		.fuel_gauge = {
-			.manuf_name = "333-27-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0004,
-				.cfet_off_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* DynaPack HIGHPOWER Battery Information */
-	[BATTERY_DYNAPACK_HIGHPOWER] = {
-		.fuel_gauge = {
-			.manuf_name = "333-2D-0D-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0004,
-				.cfet_off_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* DynaPack BYD Battery Information */
-	[BATTERY_DYNAPACK_BYD] = {
-		.fuel_gauge = {
-			.manuf_name = "333-2E-0D-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0004,
-				.cfet_off_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* Samsung SDI Battery Information */
-	[BATTERY_SAMSUNG_SDI] = {
-		.fuel_gauge = {
-			.manuf_name = "333-54-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0004,
-				.cfet_off_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* Simplo CosMX Battery Information */
-	[BATTERY_SIMPLO_COS] = {
-		.fuel_gauge = {
-			.manuf_name = "333-1C-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0004,
-				.cfet_off_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* Simplo HIGHPOWER Battery Information */
-	[BATTERY_SIMPLO_HIGHPOWER] = {
-		.fuel_gauge = {
-			.manuf_name = "333-1D-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0004,
-				.cfet_off_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* CosMX Battery Information */
-	[BATTERY_COS] = {
-		.fuel_gauge = {
-			.manuf_name = "333-AC-0D-A",
-			.ship_mode = {
-				.reg_addr = 0x00,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0004,
-				.cfet_off_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,	/* mV */
-			.voltage_normal = 7700,
-			.voltage_min = 6000,
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* CosMX B00C4473A9D0002 Battery Information */
-	[BATTERY_COS_2] = {
-		.fuel_gauge = {
-			.manuf_name = "333-AC-DA-A",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 1,
-				.reg_addr = 0x0,
-				.reg_mask = 0x0006,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0004,
-				.cfet_off_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,		/* mV */
-			.voltage_normal = 7700,		/* mV */
-			.voltage_min = 6000,		/* mV */
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-
-	/* ATL GB-S20-4473A9-01H&020H Battery Information
-	 * Gauge IC : RAJ240045
-	 */
-	[BATTERY_ATL] = {
-		.fuel_gauge = {
-			.manuf_name = "313-B7-0D-A",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x0010, 0x0010 },
-			},
-			.fet = {
-				.mfgacc_support = 0,
-				.reg_addr = 0x43,
-				.reg_mask = 0x0003,
-				.disconnect_val = 0x0,
-				.cfet_mask = 0x0002,
-				.cfet_off_val = 0x0,
-			},
-		},
-		.batt_info = {
-			.voltage_max = 8800,		/* mV */
-			.voltage_normal = 7700,		/* mV */
-			.voltage_min = 6000,		/* mV */
-			.precharge_current = 256,	/* mA */
-			.start_charging_min_c = 0,
-			.start_charging_max_c = 45,
-			.charging_min_c = 0,
-			.charging_max_c = 45,
-			.discharging_min_c = -10,
-			.discharging_max_c = 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_DYNAPACK_COS;
diff --git a/board/shotzo/board.c b/board/shotzo/board.c
index a7cd45c7c6..dea75ee7d2 100644
--- a/board/shotzo/board.c
+++ b/board/shotzo/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The ChromiumOS Authors.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,16 +8,12 @@
 #include "adc_chip.h"
 #include "button.h"
 #include "cbi_fw_config.h"
-#include "cbi_ssfc.h"
 #include "charge_manager.h"
 #include "charge_state_v2.h"
 #include "charger.h"
 #include "cros_board_info.h"
-#include "driver/accel_bma2x2.h"
-#include "driver/accel_bma422.h"
-#include "driver/accelgyro_lsm6dsm.h"
-#include "driver/bc12/pi3usb9201.h"
 #include "driver/charger/sm5803.h"
+#include "driver/led/oz554.h"
 #include "driver/temp_sensor/thermistor.h"
 #include "driver/tcpm/it83xx_pd.h"
 #include "driver/tcpm/ps8xxx.h"
@@ -25,25 +21,19 @@
 #include "gpio.h"
 #include "hooks.h"
 #include "intc.h"
-#include "keyboard_scan.h"
-#include "lid_switch.h"
 #include "power.h"
 #include "power_button.h"
-#include "pwm.h"
-#include "pwm_chip.h"
 #include "switch.h"
 #include "system.h"
-#include "tablet_mode.h"
 #include "task.h"
 #include "tcpm/tcpci.h"
 #include "temp_sensor.h"
 #include "uart.h"
-#include "usb_charge.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
 
 #define INT_RECHECK_US 5000
 
@@ -54,28 +44,12 @@ const int usb_port_enable[USB_PORT_COUNT] = {
 	GPIO_EN_USB_A_5V,
 };
 
-__override void board_process_pd_alert(int port)
-{
-	/*
-	 * PD_INT task will process this alert, and that task is only needed on
-	 * C1.
-	 */
-	if (port != 1)
-		return;
-
-	if (gpio_get_level(GPIO_USB_C1_INT_ODL))
-		return;
-
-	sm5803_handle_interrupt(port);
-}
-
-/* C0 interrupt line shared by BC 1.2 and charger */
+/* C0 interrupt line triggered by charger */
 static void check_c0_line(void);
 DECLARE_DEFERRED(check_c0_line);
 
 static void notify_c0_chips(void)
 {
-	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
 	sm5803_interrupt(0);
 }
 
@@ -103,337 +77,196 @@ static void usb_c0_interrupt(enum gpio_signal s)
 	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
 }
 
-/* C1 interrupt line shared by BC 1.2, TCPC, and charger */
-static void check_c1_line(void);
-DECLARE_DEFERRED(check_c1_line);
-
-static void notify_c1_chips(void)
+static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
 {
-	schedule_deferred_pd_interrupt(1);
-	usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+	cprints(CC_USBPD, "C0: CC OVP, SBU OVP, or thermal event");
+	pd_handle_cc_overvoltage(0);
 }
 
-static void check_c1_line(void)
-{
-	/*
-	 * If line is still being held low, see if there's more to process from
-	 * one of the chips.
-	 */
-	if (!gpio_get_level(GPIO_USB_C1_INT_ODL)) {
-		notify_c1_chips();
-		hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
-	}
-}
+/******************************************************************************/
+/*
+ * Barrel jack power supply handling
+ *
+ * EN_PPVAR_BJ_ADP_L must default active to ensure we can power on when the
+ * barrel jack is connected, and the USB-C port can bring the EC up fine in
+ * dead-battery mode. Both the USB-C and barrel jack switches do reverse
+ * protection, so we're safe to turn one on then the other off- but we should
+ * only do that if the system is off since it might still brown out.
+ */
 
-static void usb_c1_interrupt(enum gpio_signal s)
+static int barrel_jack_adapter_is_present(void)
 {
-	/* Cancel any previous calls to check the interrupt line */
-	hook_call_deferred(&check_c1_line_data, -1);
+	/* Shotzo barrel jack adapter present pin is active low. */
+	return !gpio_get_level(GPIO_BJ_ADP_PRESENT_L);
+}
 
-	/* Notify all chips using this line that an interrupt came in */
-	notify_c1_chips();
+/*
+ * Barrel-jack power adapter ratings.
+ */
 
-	/* Check the line again in 5ms */
-	hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
-}
+#define BJ_ADP_RATING_DEFAULT 0 /* BJ power ratings default */
+static const struct {
+	int voltage;
+	int current;
+} bj_power[] = {
+	{ /* 0 - 90W (also default) */
+	  .voltage = 19500,
+	  .current = 4500 },
+};
 
-static void board_enable_hdmi_hpd(int enable)
+/* Debounced connection state of the barrel jack */
+static int8_t adp_connected = -1;
+static void adp_connect_deferred(void)
 {
-	enum fw_config_db db = get_cbi_fw_config_db();
-	int hdmi_hpd = gpio_get_level(GPIO_VOLUP_BTN_ODL_HDMI_HPD);
-
-	if (db == DB_1A_HDMI || db == DB_LTE_HDMI || db == DB_1A_HDMI_LTE) {
-		/* Check if we can report HDMI_HPD signal to CPU  */
-		if (enable)
-			gpio_set_level(GPIO_EC_AP_USB_C1_HDMI_HPD, hdmi_hpd);
-		else
-			gpio_set_level(GPIO_EC_AP_USB_C1_HDMI_HPD, 0);
+	struct charge_port_info pi = { 0 };
+	int connected = barrel_jack_adapter_is_present();
+
+	/* Debounce */
+	if (connected == adp_connected)
+		return;
+	if (connected) {
+		unsigned int bj = BJ_ADP_RATING_DEFAULT;
+
+		pi.voltage = bj_power[bj].voltage;
+		pi.current = bj_power[bj].current;
 	}
+	charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED,
+				     DEDICATED_CHARGE_PORT, &pi);
+	adp_connected = connected;
 }
+DECLARE_DEFERRED(adp_connect_deferred);
 
-static void button_sub_hdmi_hpd_interrupt(enum gpio_signal s)
+#define ADP_DEBOUNCE_MS 1000 /* Debounce time for BJ plug/unplug */
+/* IRQ for BJ plug/unplug. It shouldn't be called if BJ is the power source. */
+static void adp_connect_interrupt(enum gpio_signal signal)
 {
-	enum fw_config_db db = get_cbi_fw_config_db();
-	int hdmi_hpd = gpio_get_level(GPIO_VOLUP_BTN_ODL_HDMI_HPD);
-
-	if (db == DB_1A_HDMI || db == DB_LTE_HDMI || db == DB_1A_HDMI_LTE) {
-		/* Do not report HDMI_HPD signal to CPU when system off. */
-		if (!chipset_in_state(CHIPSET_STATE_ANY_OFF))
-			gpio_set_level(GPIO_EC_AP_USB_C1_HDMI_HPD, hdmi_hpd);
-	} else
-		button_interrupt(s);
+	hook_call_deferred(&adp_connect_deferred_data, ADP_DEBOUNCE_MS * MSEC);
 }
-
-static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
+static void adp_state_init(void)
 {
-	cprints(CC_USBPD, "C0: CC OVP, SBU OVP, or thermal event");
-	pd_handle_cc_overvoltage(0);
-}
-
-static void pen_detect_interrupt(enum gpio_signal s)
-{
-	int pen_detect = !gpio_get_level(GPIO_PEN_DET_ODL);
+	/*
+	 * Initialize all charge suppliers to 0. The charge manager waits until
+	 * all ports have reported in before doing anything.
+	 */
+	for (int i = 0; i < CHARGE_PORT_COUNT; i++) {
+		for (int j = 0; j < CHARGE_SUPPLIER_COUNT; j++)
+			charge_manager_update_charge(j, i, NULL);
+	}
 
-	gpio_set_level(GPIO_EN_PP5000_PEN, pen_detect);
+	/* Report charge state from the barrel jack. */
+	adp_connect_deferred();
 }
+DECLARE_HOOK(HOOK_INIT, adp_state_init, HOOK_PRIO_INIT_CHARGE_MANAGER + 1);
 
 /* Must come after other header files and interrupt handler declarations */
 #include "gpio_list.h"
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH0
-	},
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH2
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH3
-	},
-	[ADC_SUB_ANALOG] = {
-		.name = "SUB_ANALOG",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH13
-	},
-	[ADC_TEMP_SENSOR_3] = {
-		.name = "TEMP_SENSOR3",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH15
-	},
-	[ADC_TEMP_SENSOR_4] = {
-		.name = "TEMP_SENSOR4",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH16
-	},
+	[ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH0 },
+	[ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH2 },
+	[ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH3 },
+	[ADC_SUB_ANALOG] = { .name = "SUB_ANALOG",
+			     .factor_mul = ADC_MAX_MVOLT,
+			     .factor_div = ADC_READ_MAX + 1,
+			     .shift = 0,
+			     .channel = CHIP_ADC_CH13 },
+	[ADC_TEMP_SENSOR_3] = { .name = "TEMP_SENSOR3",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH15 },
+	[ADC_TEMP_SENSOR_4] = { .name = "TEMP_SENSOR4",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH16 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
-/* BC 1.2 chips */
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	{
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-		.flags = PI3USB9201_ALWAYS_POWERED,
-	},
-	{
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-		.flags = PI3USB9201_ALWAYS_POWERED,
-	},
-};
-
 /* Charger chips */
-const struct charger_config_t chg_chips[] = {
-	[CHARGER_PRIMARY] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = SM5803_ADDR_CHARGER_FLAGS,
-		.drv = &sm5803_drv,
-	},
-	[CHARGER_SECONDARY] = {
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = SM5803_ADDR_CHARGER_FLAGS,
-		.drv = &sm5803_drv,
-	},
-};
+const struct charger_config_t
+	chg_chips[] = { [CHARGER_SOLO] = {
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = SM5803_ADDR_CHARGER_FLAGS,
+				.drv = &sm5803_drv,
+			} };
 
 /* TCPCs */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.bus_type = EC_BUS_TYPE_EMBEDDED,
-		.drv = &it83xx_tcpm_drv,
-	},
-	{
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_SUB_USB_C1,
-			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { {
+	.bus_type = EC_BUS_TYPE_EMBEDDED,
+	.drv = &it83xx_tcpm_drv,
+} };
 
 /* USB Muxes */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-	},
-	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	},
-};
-
-/* Sensor Mutexes */
-static struct mutex g_lid_mutex;
-static struct mutex g_base_mutex;
-
-/* Sensor Data */
-static struct accelgyro_saved_data_t g_bma253_data;
-static struct accelgyro_saved_data_t g_bma422_data;
-static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
-
-/* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-/* Drivers */
-struct motion_sensor_t motion_sensors[] = {
-	[LID_ACCEL] = {
-		.name = "Lid Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_BMA255,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_LID,
-		.drv = &bma2x2_accel_drv,
-		.mutex = &g_lid_mutex,
-		.drv_data = &g_bma253_data,
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = BMA2x2_I2C_ADDR1_FLAGS,
-		.rot_standard_ref = &lid_standard_ref,
-		.default_range = 2,
-		.min_frequency = BMA255_ACCEL_MIN_FREQ,
-		.max_frequency = BMA255_ACCEL_MAX_FREQ,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-			},
-		},
-	},
-	[BASE_ACCEL] = {
-		.name = "Base Accel",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_ACCEL,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_ACCEL),
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.rot_standard_ref = &base_standard_ref,
-		.default_range = 4,  /* g */
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-		.config = {
-			[SENSOR_CONFIG_EC_S0] = {
-				.odr = 13000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
-			[SENSOR_CONFIG_EC_S3] = {
-				.odr = 10000 | ROUND_UP_FLAG,
-				.ec_rate = 100 * MSEC,
-			},
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = 0,
+			.i2c_port = I2C_PORT_USB_C0,
+			.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+			.driver = &it5205_usb_mux_driver,
 		},
-	},
-	[BASE_GYRO] = {
-		.name = "Base Gyro",
-		.active_mask = SENSOR_ACTIVE_S0_S3,
-		.chip = MOTIONSENSE_CHIP_LSM6DSM,
-		.type = MOTIONSENSE_TYPE_GYRO,
-		.location = MOTIONSENSE_LOC_BASE,
-		.drv = &lsm6dsm_drv,
-		.mutex = &g_base_mutex,
-		.drv_data = LSM6DSM_ST_DATA(lsm6dsm_data,
-				MOTIONSENSE_TYPE_GYRO),
-		.port = I2C_PORT_SENSOR,
-		.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
-		.default_range = 1000 | ROUND_UP_FLAG, /* dps */
-		.rot_standard_ref = &base_standard_ref,
-		.min_frequency = LSM6DSM_ODR_MIN_VAL,
-		.max_frequency = LSM6DSM_ODR_MAX_VAL,
-	},
-};
+} };
 
-unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
-
-struct motion_sensor_t bma422_lid_accel = {
-	.name = "Lid Accel",
-	.active_mask = SENSOR_ACTIVE_S0_S3,
-	.chip = MOTIONSENSE_CHIP_BMA422,
-	.type = MOTIONSENSE_TYPE_ACCEL,
-	.location = MOTIONSENSE_LOC_LID,
-	.drv = &bma4_accel_drv,
-	.mutex = &g_lid_mutex,
-	.drv_data = &g_bma422_data,
-	.port = I2C_PORT_SENSOR,
-	.i2c_spi_addr_flags = BMA4_I2C_ADDR_PRIMARY,
-	.rot_standard_ref = &lid_standard_ref,
-	.default_range = 2,
-	.min_frequency = BMA4_ACCEL_MIN_FREQ,
-	.max_frequency = BMA4_ACCEL_MAX_FREQ,
-	.config = {
-		/* EC use accel for angle detection */
-		[SENSOR_CONFIG_EC_S0] = {
-			.odr = 12500 | ROUND_UP_FLAG,
-			.ec_rate = 100 * MSEC,
-		},
-		/* Sensor on in S3 */
-		[SENSOR_CONFIG_EC_S3] = {
-			.odr = 12500 | ROUND_UP_FLAG,
-			.ec_rate = 0,
-		},
-	},
-};
-
-static void board_update_motion_sensor_config(void)
+void oz554_board_init(void)
 {
-	if (get_cbi_ssfc_lid_sensor() == SSFC_SENSOR_BMA422)
-		motion_sensors[LID_ACCEL] = bma422_lid_accel;
+	int panel_id = 0;
+	int oz554_id;
+
+	oz554_id = gpio_get_level(GPIO_BL_OZ554_ID);
+	panel_id |= gpio_get_level(GPIO_PANEL_ID0) << 0;
+	panel_id |= gpio_get_level(GPIO_PANEL_ID1) << 1;
+	panel_id |= gpio_get_level(GPIO_PANEL_ID2) << 2;
+	panel_id |= gpio_get_level(GPIO_PANEL_ID3) << 3;
+
+	if (oz554_id == 0)
+		CPRINTUSB("OZ554ELN");
+	else if (oz554_id == 1)
+		CPRINTUSB("OZ554ALN");
+	else
+		CPRINTUSB("OZ554A UNKNOWN");
+
+	switch (panel_id) {
+	case 0x00:
+		CPRINTUSB("PANEL M238HAN");
+		oz554_set_config(0, 0xF1);
+		oz554_set_config(1, 0x43);
+		oz554_set_config(2, 0x44);
+		oz554_set_config(5, 0xBF);
+		break;
+	case 0x08:
+		CPRINTUSB("PANEL MV238FHM");
+		oz554_set_config(0, 0xF1);
+		oz554_set_config(1, 0x43);
+		oz554_set_config(2, 0x3C);
+		oz554_set_config(5, 0xD7);
+		break;
+	default:
+		CPRINTUSB("PANEL UNKNOWN");
+		break;
+	}
 }
 
 void board_init(void)
 {
 	int on;
-	enum fw_config_db db = get_cbi_fw_config_db();
-
-	if (db == DB_1A_HDMI || db == DB_LTE_HDMI || db == DB_1A_HDMI_LTE) {
-		/* Select HDMI option */
-		gpio_set_level(GPIO_HDMI_SEL_L, 0);
-	} else {
-		/* Select AUX option */
-		gpio_set_level(GPIO_HDMI_SEL_L, 1);
-	}
+
+	gpio_enable_interrupt(GPIO_BJ_ADP_PRESENT_L);
 
 	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_INT_ODL);
 
 	/* Store board version for use in determining charge limits */
 	cbi_get_board_version(&board_version);
@@ -444,42 +277,15 @@ void board_init(void)
 	 */
 	if (!gpio_get_level(GPIO_USB_C0_INT_ODL))
 		hook_call_deferred(&check_c0_line_data, 0);
-	if (!gpio_get_level(GPIO_USB_C1_INT_ODL))
-		hook_call_deferred(&check_c1_line_data, 0);
 
 	gpio_enable_interrupt(GPIO_USB_C0_CCSBU_OVP_ODL);
 
-	if (get_cbi_fw_config_tablet_mode() == TABLET_MODE_PRESENT) {
-		motion_sensor_count = ARRAY_SIZE(motion_sensors);
-		/* Enable Base Accel interrupt */
-		gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L);
-
-		board_update_motion_sensor_config();
-	} else {
-		motion_sensor_count = 0;
-		gmr_tablet_switch_disable();
-		/* Base accel is not stuffed, don't allow line to float */
-		gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L,
-			       GPIO_INPUT | GPIO_PULL_DOWN);
-	}
-
-	gpio_enable_interrupt(GPIO_PEN_DET_ODL);
-
-	/* Make sure pen detection is triggered or not at sysjump */
-	if (!gpio_get_level(GPIO_PEN_DET_ODL))
-		gpio_set_level(GPIO_EN_PP5000_PEN, 1);
-
-	/* Make sure HDMI_HPD signal can be reported to CPU at sysjump */
-	board_enable_hdmi_hpd(1);
+	oz554_board_init();
+	gpio_enable_interrupt(GPIO_PANEL_BACKLIGHT_EN);
 
 	/* Charger on the MB will be outputting PROCHOT_ODL and OD CHG_DET */
-	sm5803_configure_gpio0(CHARGER_PRIMARY, GPIO0_MODE_PROCHOT, 1);
-	sm5803_configure_chg_det_od(CHARGER_PRIMARY, 1);
-
-	if (board_get_charger_chip_count() > 1) {
-		/* Charger on the sub-board will be a push-pull GPIO */
-		sm5803_configure_gpio0(CHARGER_SECONDARY, GPIO0_MODE_OUTPUT, 0);
-	}
+	sm5803_configure_gpio0(CHARGER_SOLO, GPIO0_MODE_PROCHOT, 1);
+	sm5803_configure_chg_det_od(CHARGER_SOLO, 1);
 
 	/* Turn on 5V if the system is on, otherwise turn it off */
 	on = chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND |
@@ -490,47 +296,21 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
 static void board_resume(void)
 {
-	sm5803_disable_low_power_mode(CHARGER_PRIMARY);
-	if (board_get_charger_chip_count() > 1)
-		sm5803_disable_low_power_mode(CHARGER_SECONDARY);
-
-	/* Enable reporting HDMI_HPD to CPU when system resume */
-	board_enable_hdmi_hpd(1);
+	sm5803_disable_low_power_mode(CHARGER_SOLO);
 }
 DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_resume, HOOK_PRIO_DEFAULT);
 
 static void board_suspend(void)
 {
-	sm5803_enable_low_power_mode(CHARGER_PRIMARY);
-	if (board_get_charger_chip_count() > 1)
-		sm5803_enable_low_power_mode(CHARGER_SECONDARY);
+	sm5803_enable_low_power_mode(CHARGER_SOLO);
 }
 DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_suspend, HOOK_PRIO_DEFAULT);
 
 static void board_shutdown(void)
 {
-	/* Disable reporting HDMI_HPD to CPU at shutdown */
-	board_enable_hdmi_hpd(0);
 }
 DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_shutdown, HOOK_PRIO_DEFAULT);
 
-void board_hibernate(void)
-{
-	/*
-	 * Put all charger ICs present into low power mode before entering
-	 * z-state.
-	 */
-	sm5803_hibernate(CHARGER_PRIMARY);
-	if (board_get_charger_chip_count() > 1)
-		sm5803_hibernate(CHARGER_SECONDARY);
-}
-
-__override void board_ocpc_init(struct ocpc_data *ocpc)
-{
-	/* There's no provision to measure Isys */
-	ocpc->chg_flags[CHARGER_SECONDARY] |= OCPC_NO_ISYS_MEAS_CAP;
-}
-
 __override void board_pulse_entering_rw(void)
 {
 	/*
@@ -549,8 +329,7 @@ __override void board_pulse_entering_rw(void)
 void board_reset_pd_mcu(void)
 {
 	/*
-	 * Nothing to do.  TCPC C0 is internal, TCPC C1 reset pin is not
-	 * connected to the EC.
+	 * Nothing to do.  TCPC C0 is internal.
 	 */
 }
 
@@ -561,111 +340,104 @@ __override void board_power_5v_enable(int enable)
 	 * sets it through the charger GPIO.
 	 */
 	gpio_set_level(GPIO_EN_PP5000, !!enable);
-
-	if (board_get_charger_chip_count() > 1) {
-		if (sm5803_set_gpio0_level(1, !!enable))
-			CPRINTUSB("Failed to %sable sub rails!", enable ?
-								  "en" : "dis");
-	}
 }
 
-__override uint8_t board_get_usb_pd_port_count(void)
+uint16_t tcpc_get_alert_status(void)
 {
-	enum fw_config_db db = get_cbi_fw_config_db();
-
-	if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI
-			|| db == DB_1A_HDMI_LTE)
-		return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
-	else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A
-			|| db == DB_1C_1A_LTE)
-		return CONFIG_USB_PD_PORT_MAX_COUNT;
-
-	ccprints("Unhandled DB configuration: %d", db);
+	/*
+	 * TCPC 0 is embedded in the EC and processes interrupts in the chip
+	 * code (it83xx/intc.c)
+	 */
 	return 0;
 }
 
-__override uint8_t board_get_charger_chip_count(void)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
-	enum fw_config_db db = get_cbi_fw_config_db();
-
-	if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI
-			|| db == DB_1A_HDMI_LTE)
-		return CHARGER_NUM - 1;
-	else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A
-			|| db == DB_1C_1A_LTE)
-		return CHARGER_NUM;
-
-	ccprints("Unhandled DB configuration: %d", db);
-	return 0;
+	if (port == CHARGER_SOLO) {
+		charger_set_input_current_limit(CHARGER_SOLO, max_ma);
+	}
 }
 
-uint16_t tcpc_get_alert_status(void)
+__override int extpower_is_present(void)
 {
-	/*
-	 * TCPC 0 is embedded in the EC and processes interrupts in the chip
-	 * code (it83xx/intc.c)
-	 */
+	int port;
+	int rv;
+	bool acok;
+
+	for (port = 0; port < board_get_usb_pd_port_count(); port++) {
+		rv = sm5803_is_acok(port, &acok);
+		if ((rv == EC_SUCCESS) && acok)
+			return 1;
+	}
 
-	uint16_t status = 0;
-	int regval;
+	if (!gpio_get_level(GPIO_EN_PPVAR_BJ_ADP_L))
+		return 1;
 
-	/* Check whether TCPC 1 pulled the shared interrupt line */
-	if (!gpio_get_level(GPIO_USB_C1_INT_ODL)) {
-		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
-			if (regval)
-				status = PD_STATUS_TCPC_ALERT_1;
-		}
-	}
+	CPRINTUSB("No external power present.");
 
-	return status;
+	return 0;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
-			    int charge_mv)
+int board_set_active_charge_port(int port)
 {
-	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
+	CPRINTUSB("Requested charge port change to %d", port);
 
-	/* Limit C1 on board version 0 to 2.0 A */
-	if ((board_version == 0) && (port == 1))
-		icl = MIN(icl, 2000);
 	/*
-	 * TODO(b/151955431): Characterize the input current limit in case a
-	 * scaling needs to be applied here
+	 * The charge manager may ask us to switch to no charger if we're
+	 * running off USB-C only but upstream doesn't support PD. It requires
+	 * that we accept this switch otherwise it triggers an assert and EC
+	 * reset; it's not possible to boot the AP anyway, but we want to avoid
+	 * resetting the EC so we can continue to do the "low power" LED blink.
 	 */
-	charge_set_input_current_limit(icl, charge_mv);
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_valid_port = (port >= 0 && port < board_get_usb_pd_port_count());
+	if (port == CHARGE_PORT_NONE)
+		return EC_SUCCESS;
 
-	if (!is_valid_port && port != CHARGE_PORT_NONE)
+	if (port < 0 || CHARGE_PORT_COUNT <= port)
 		return EC_ERROR_INVAL;
 
-	if (port == CHARGE_PORT_NONE) {
-		CPRINTUSB("Disabling all charge ports");
+	if (port == charge_manager_get_active_charge_port())
+		return EC_SUCCESS;
 
-		sm5803_vbus_sink_enable(CHARGER_PRIMARY, 0);
+	/* Don't charge from a source port */
+	if (board_vbus_source_enabled(port))
+		return EC_ERROR_INVAL;
 
-		if (board_get_charger_chip_count() > 1)
-			sm5803_vbus_sink_enable(CHARGER_SECONDARY, 0);
+	if (!chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
+		int bj_active, bj_requested;
 
-		return EC_SUCCESS;
-	}
+		if (charge_manager_get_active_charge_port() != CHARGE_PORT_NONE)
+			/* Change is only permitted while the system is off */
+			return EC_ERROR_INVAL;
 
-	CPRINTUSB("New chg p%d", port);
+		/*
+		 * Current setting is no charge port but the AP is on, so the
+		 * charge manager is out of sync (probably because we're
+		 * reinitializing after sysjump). Reject requests that aren't
+		 * in sync with our outputs.
+		 */
+		bj_active = !gpio_get_level(GPIO_EN_PPVAR_BJ_ADP_L);
+		bj_requested = port == CHARGE_PORT_BARRELJACK;
+		if (bj_active != bj_requested)
+			return EC_ERROR_INVAL;
+	}
 
-	/*
-	 * Ensure other port is turned off, then enable new charge port
-	 */
-	if (port == 0) {
-		if (board_get_charger_chip_count() > 1)
-			sm5803_vbus_sink_enable(CHARGER_SECONDARY, 0);
-		sm5803_vbus_sink_enable(CHARGER_PRIMARY, 1);
-
-	} else {
-		sm5803_vbus_sink_enable(CHARGER_PRIMARY, 0);
-		sm5803_vbus_sink_enable(CHARGER_SECONDARY, 1);
+	CPRINTUSB("New charger p%d", port);
+
+	switch (port) {
+	case CHARGE_PORT_TYPEC0:
+		sm5803_vbus_sink_enable(CHARGER_SOLO, 1);
+		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 1);
+		break;
+	case CHARGE_PORT_BARRELJACK:
+		/* Make sure BJ adapter is sourcing power */
+		if (!barrel_jack_adapter_is_present())
+			return EC_ERROR_INVAL;
+		gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 0);
+		sm5803_vbus_sink_enable(CHARGER_SOLO, 0);
+		break;
+	default:
+		return EC_ERROR_INVAL;
 	}
 
 	return EC_SUCCESS;
@@ -696,92 +468,23 @@ __override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
 	charger_set_otg_current_voltage(port, current, 5000);
 }
 
-/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq_hz = 10000,
-	}
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
 /* Thermistors */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "Charger",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_3},
-	[TEMP_SENSOR_4] = {.name = "5V regular",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_4},
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "Charger",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
+	[TEMP_SENSOR_4] = { .name = "5V regular",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_4 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
-
-/* This callback disables keyboard when convertibles are fully open */
-__override void lid_angle_peripheral_enable(int enable)
-{
-	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
-
-	/*
-	 * If the lid is in tablet position via other sensors,
-	 * ignore the lid angle, which might be faulty then
-	 * disable keyboard.
-	 */
-	if (tablet_get_mode())
-		enable = 0;
-
-	if (enable) {
-		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
-	} else {
-		/*
-		 * Ensure that the chipset is off before disabling the keyboard.
-		 * When the chipset is on, the EC keeps the keyboard enabled and
-		 * the AP decides whether to ignore input devices or not.
-		 */
-		if (!chipset_in_s0)
-			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
-	}
-}
-
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
-{
-	*kp = 3;
-	*kp_div = 20;
-
-	*ki = 3;
-	*ki_div = 125;
-
-	*kd = 4;
-	*kd_div = 40;
-}
-
-#ifdef CONFIG_KEYBOARD_FACTORY_TEST
-/*
- * Map keyboard connector pins to EC GPIO pins for factory test.
- * Pins mapped to {-1, -1} are skipped.
- * The connector has 24 pins total, and there is no pin 0.
- */
-const int keyboard_factory_scan_pins[][2] = {
-	{-1, -1}, {GPIO_KSO_H, 4}, {GPIO_KSO_H, 0}, {GPIO_KSO_H, 1},
-	{GPIO_KSO_H, 3}, {GPIO_KSO_H, 2}, {GPIO_KSO_L, 5}, {GPIO_KSO_L, 6},
-	{GPIO_KSO_L, 3}, {GPIO_KSO_L, 2}, {GPIO_KSI, 0}, {GPIO_KSO_L, 1},
-	{GPIO_KSO_L, 4}, {GPIO_KSI, 3}, {GPIO_KSI, 2}, {GPIO_KSO_L, 0},
-	{GPIO_KSI, 5}, {GPIO_KSI, 4}, {GPIO_KSO_L, 7}, {GPIO_KSI, 6},
-	{GPIO_KSI, 7}, {GPIO_KSI, 1}, {-1, -1}, {-1, -1}, {-1, -1},
-};
-
-const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
-#endif
diff --git a/board/shotzo/board.h b/board/shotzo/board.h
index 7235499624..c6fcceb045 100644
--- a/board/shotzo/board.h
+++ b/board/shotzo/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The ChromiumOS Authors.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,66 +12,17 @@
 #define VARIANT_DEDEDE_EC_IT8320
 #include "baseboard.h"
 
-#undef GPIO_VOLUME_UP_L
-#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL_HDMI_HPD
-
-/* Battery */
-#define CONFIG_BATTERY_FUEL_GAUGE
-
-/* BC 1.2 */
-#define CONFIG_BC12_DETECT_PI3USB9201
-
 /* Charger */
-#define CONFIG_CHARGE_RAMP_HW
-#define CONFIG_CHARGER_SM5803		/* C0 and C1: Charger */
+#define CONFIG_CHARGER
+#define CONFIG_CHARGER_SM5803 /* C0 and C1: Charger */
+#define PD_MAX_VOLTAGE_MV 15000
 #define CONFIG_USB_PD_VBUS_DETECT_CHARGER
 #define CONFIG_USB_PD_5V_CHARGER_CTRL
 #define CONFIG_CHARGER_OTG
-#undef  CONFIG_CHARGER_SINGLE_CHIP
-#define CONFIG_OCPC
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr */
-
-/* PWM */
-#define CONFIG_PWM
-
-/* Sensors */
-#define CONFIG_ACCEL_BMA255		/* Lid accel */
-#define CONFIG_ACCEL_BMA4XX		/* 2nd source Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM	/* Base accel */
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
-
-#define CONFIG_CMD_ACCELS
-#define CONFIG_CMD_ACCEL_INFO
-
-/* Enable sensor fifo, must also define the _SIZE and _THRES */
-#define CONFIG_ACCEL_FIFO
-/* Power of 2 - Too large of a fifo causes too much timestamp jitter */
-#define CONFIG_ACCEL_FIFO_SIZE 256
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
-
-#define CONFIG_TABLET_MODE
-#define CONFIG_TABLET_MODE_SWITCH
-#define CONFIG_GMR_TABLET_MODE
-
-/* Keyboard */
-#define CONFIG_KEYBOARD_FACTORY_TEST
-#define CONFIG_PWM_KBLIGHT
 
 /* TCPC */
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP	/* C0: ITE EC TCPC */
-#define CONFIG_USB_PD_TCPM_PS8705	/* C1: PS8705 TCPC*/
+#define CONFIG_USB_PD_PORT_MAX_COUNT 1
+#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0: ITE EC TCPC */
 #define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1
 #define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
 #define CONFIG_USB_PD_TCPC_LOW_POWER
@@ -82,45 +33,59 @@
 #define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
 
 /* USB Mux and Retimer */
-#define CONFIG_USB_MUX_IT5205			/* C1: ITE Mux */
-#define I2C_PORT_USB_MUX I2C_PORT_USB_C0	/* Required for ITE Mux */
+#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */
 
 /* USB Type A Features */
 #define USB_PORT_COUNT 1
 #define CONFIG_USB_PORT_POWER_DUMB
 
+/* Buttons */
+#define CONFIG_DEDICATED_RECOVERY_BUTTON
+#define CONFIG_DEDICATED_RECOVERY_BUTTON_2
+#define CONFIG_EMULATED_SYSRQ
+#define CONFIG_POWER_BUTTON_IGNORE_LID
+
+/* Dedicated barreljack charger port */
+#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT
+#define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1
+#define DEDICATED_CHARGE_PORT 1
+
+/* LED backlight controller */
+#define CONFIG_LED_DRIVER_OZ554
+
+/* Unused Features */
+#undef CONFIG_BACKLIGHT_LID
+#undef CONFIG_BATTERY_CUT_OFF
+#undef CONFIG_BATTERY_PRESENT_GPIO
+#undef CONFIG_BATTERY_SMART
+#undef CONFIG_BATTERY_REQUESTS_NIL_WHEN_DEAD
+#undef CONFIG_BATTERY_REVIVE_DISCONNECT
+#undef CONFIG_CMD_KEYBOARD
+#undef CONFIG_HIBERNATE
+#undef CONFIG_KEYBOARD_BOOT_KEYS
+#undef CONFIG_KEYBOARD_RUNTIME_KEYS
+#undef CONFIG_LID_SWITCH
+#undef CONFIG_USB_CHARGER
+#undef CONFIG_VOLUME_BUTTONS
+#undef GPIO_USB_C1_DP_HPD
+
+/* I2C Bus Configuration */
+#define I2C_PORT_BACKLIGHT I2C_PORT_SENSOR
+
 #ifndef __ASSEMBLER__
 
 #include "gpio_signal.h"
 #include "registers.h"
 
-enum chg_id {
-	CHARGER_PRIMARY,
-	CHARGER_SECONDARY,
-	CHARGER_NUM,
-};
-
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT,
-};
-
-/* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
-
 /* ADC channels */
 enum adc_channel {
-	ADC_VSNS_PP3300_A,     /* ADC0 */
-	ADC_TEMP_SENSOR_1,     /* ADC2 */
-	ADC_TEMP_SENSOR_2,     /* ADC3 */
-	ADC_SUB_ANALOG,        /* ADC13 */
-	ADC_TEMP_SENSOR_3,     /* ADC15 */
-	ADC_TEMP_SENSOR_4,     /* ADC16 */
+	ADC_VSNS_PP3300_A, /* ADC0 */
+	ADC_TEMP_SENSOR_1, /* ADC2 */
+	ADC_TEMP_SENSOR_2, /* ADC3 */
+	ADC_SUB_ANALOG, /* ADC13 */
+	ADC_TEMP_SENSOR_3, /* ADC15 */
+	ADC_TEMP_SENSOR_4, /* ADC16 */
 	ADC_CH_COUNT
 };
 
@@ -132,21 +97,20 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-/* List of possible batteries */
-enum battery_type {
-	BATTERY_DYNAPACK_COS,
-	BATTERY_DYNAPACK_ATL,
-	BATTERY_DYNAPACK_HIGHPOWER,
-	BATTERY_DYNAPACK_BYD,
-	BATTERY_SAMSUNG_SDI,
-	BATTERY_SIMPLO_COS,
-	BATTERY_SIMPLO_HIGHPOWER,
-	BATTERY_COS,
-	BATTERY_COS_2,
-	BATTERY_ATL,
-	BATTERY_TYPE_COUNT,
+enum charge_port {
+	CHARGE_PORT_TYPEC0,
+	CHARGE_PORT_BARRELJACK,
 };
 
+/* Board specific handlers */
+void led_alert(int enable);
+#define PORT_TO_HPD(port) (GPIO_USB_C0_DP_HPD)
+
+/* Pin renaming */
+#define GPIO_AC_PRESENT GPIO_BJ_ADP_PRESENT_L
+#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_ODL
+#define GPIO_RECOVERY_L_2 GPIO_H1_EC_RECOVERY_BTN_ODL
+
 #endif /* !__ASSEMBLER__ */
 
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/shotzo/build.mk b/board/shotzo/build.mk
index 4d677400a9..07ea50c392 100644
--- a/board/shotzo/build.mk
+++ b/board/shotzo/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2022 The ChromiumOS Authors.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -11,5 +11,4 @@ CHIP_FAMILY:=it8320
 CHIP_VARIANT:=it8320dx
 BASEBOARD:=dedede
 
-board-y=board.o cbi_ssfc.o led.o usb_pd_policy.o
-board-$(CONFIG_BATTERY_SMART)+=battery.o
+board-y=board.o led.o usb_pd_policy.o
diff --git a/board/shotzo/ec.tasklist b/board/shotzo/ec.tasklist
index 99f42b5579..1447f9db15 100644
--- a/board/shotzo/ec.tasklist
+++ b/board/shotzo/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2022 The ChromiumOS Authors.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,16 +9,8 @@
 
 #define CONFIG_TASK_LIST \
 	TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(CHARGER, charger_task, NULL, TRENTA_TASK_STACK_SIZE) \
 	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, LARGER_TASK_STACK_SIZE) \
 	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, VENTI_TASK_STACK_SIZE) \
 	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
 	TASK_ALWAYS(POWERBTN, power_button_task, NULL, ULTRA_TASK_STACK_SIZE) \
-	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, ULTRA_TASK_STACK_SIZE) \
-        TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-        TASK_ALWAYS(PD_C1, pd_task, NULL, ULTRA_TASK_STACK_SIZE) \
-        TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, ULTRA_TASK_STACK_SIZE)
+        TASK_ALWAYS(PD_C0, pd_task, NULL, ULTRA_TASK_STACK_SIZE)
diff --git a/board/shotzo/gpio.inc b/board/shotzo/gpio.inc
index 5d00a0b0e7..4a26d2631a 100644
--- a/board/shotzo/gpio.inc
+++ b/board/shotzo/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2022 The ChromiumOS Authors.
+ * Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -29,18 +29,15 @@ GPIO_INT(UART1_RX,	 PIN(B, 0), GPIO_INT_BOTH, uart_deepsleep_interrupt)	/* UART_
 #endif
 
 /* USB-C interrupts */
-GPIO_INT(USB_C0_INT_ODL,	PIN(K, 0), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt) /* BC12 and charger */
-GPIO_INT(USB_C1_INT_ODL,	PIN(E, 6), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c1_interrupt) /* TCPC, charger, BC12 */
+GPIO_INT(USB_C0_INT_ODL,	PIN(K, 0), GPIO_INT_FALLING | GPIO_PULL_UP, usb_c0_interrupt) /* charger */
 GPIO_INT(USB_C0_CCSBU_OVP_ODL,	PIN(K, 6), GPIO_INT_FALLING | GPIO_PULL_UP, c0_ccsbu_ovp_interrupt) /* Fault protection */
 
 /* Other interrupts */
-GPIO_INT(LID_OPEN,		PIN(F, 3), GPIO_INT_BOTH, lid_interrupt)
-GPIO_INT(LID_360_L,		PIN(A, 7), GPIO_INT_BOTH, gmr_tablet_switch_isr)
-GPIO_INT(VOLDN_BTN_ODL,		PIN(I, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
-GPIO_INT(VOLUP_BTN_ODL_HDMI_HPD,	PIN(I, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_sub_hdmi_hpd_interrupt)
-GPIO_INT(BASE_SIXAXIS_INT_L,	PIN(J, 0), GPIO_INT_FALLING | GPIO_SEL_1P8V, lsm6dsm_interrupt)
 GPIO_INT(EC_WP_OD,		PIN(A, 6), GPIO_INT_BOTH, switch_interrupt)
-GPIO_INT(PEN_DET_ODL,		PIN(J, 1), GPIO_INT_BOTH | GPIO_PULL_UP, pen_detect_interrupt)
+GPIO_INT(BJ_ADP_PRESENT_L,	PIN(J, 1), GPIO_INT_BOTH | GPIO_PULL_UP, adp_connect_interrupt)
+GPIO_INT(PANEL_BACKLIGHT_EN,	PIN(J, 3), GPIO_INT_RISING, oz554_interrupt)
+GPIO_INT(EC_RECOVERY_BTN_ODL,	PIN(F, 1), GPIO_INT_BOTH, button_interrupt)
+GPIO_INT(H1_EC_RECOVERY_BTN_ODL,	PIN(KSI, 5), GPIO_INT_BOTH, button_interrupt)
 
 /* Power sequence GPIOs */
 GPIO(EC_AP_RTCRST,		PIN(K, 2), GPIO_OUT_LOW)
@@ -84,50 +81,71 @@ GPIO(EN_USB_A_5V,			PIN(L, 6), GPIO_OUT_LOW)
 GPIO(EN_USB_C0_CC1_VCONN,	PIN(H, 4), GPIO_OUT_LOW)
 GPIO(EN_USB_C0_CC2_VCONN,	PIN(H, 6), GPIO_OUT_LOW)
 GPIO(EC_AP_USB_C0_HPD,		PIN(L, 4), GPIO_OUT_LOW)
-GPIO(EC_AP_USB_C1_HDMI_HPD,	PIN(K, 7), GPIO_OUT_LOW)
 GPIO(USB_C0_FRS,		PIN(C, 4), GPIO_OUT_LOW)
 GPIO(HDMI_SEL_L,		PIN(C, 6), GPIO_OUT_HIGH)
 
 /* MKBP event synchronization */
 GPIO(EC_AP_MKBP_INT_L,	PIN(L, 5), GPIO_ODR_HIGH)
 
-/* Misc pins which will run to the I/O board */
-GPIO(EC_SUB_IO_1_2, PIN(F, 0), GPIO_INPUT)
-GPIO(EC_SUB_IO_2_1, PIN(F, 1), GPIO_INPUT)
-
 /* Misc */
-GPIO(EN_BL_OD,			PIN(K, 4), GPIO_ODR_LOW)
 GPIO(EC_ENTERING_RW,		PIN(G, 0), GPIO_OUT_LOW)
 GPIO(EC_ENTERING_RW2,		PIN(C, 7), GPIO_OUT_LOW)
 GPIO(CCD_MODE_ODL,		PIN(H, 5), GPIO_ODR_HIGH)
-GPIO(EC_BATTERY_PRES_ODL,	PIN(I, 4), GPIO_INPUT)
-GPIO(EN_KB_BL,			PIN(J, 3), GPIO_OUT_LOW) /* Currently unused */
 GPIO(ECH1_PACKET_MODE,		PIN(H, 1), GPIO_OUT_LOW)
-GPIO(EN_PP5000_PEN,		PIN(B, 5), GPIO_OUT_LOW)
+GPIO(EN_PPVAR_BJ_ADP_L,		PIN(J, 0), GPIO_OUT_LOW)
+GPIO(EN_VBUS_PWR,		PIN(F, 3), GPIO_OUT_HIGH)
+GPIO(PANEL_ID0,			PIN(K, 4), GPIO_INPUT)
+GPIO(PANEL_ID1,			PIN(J, 4), GPIO_INPUT)
+GPIO(PANEL_ID2,			PIN(J, 5), GPIO_INPUT)
+GPIO(PANEL_ID3,			PIN(J, 6), GPIO_INPUT)
+GPIO(BL_OZ554_ID,		PIN(A, 7), GPIO_INPUT)
+GPIO(EC_CRTL,			PIN(F, 0), GPIO_OUT_LOW)
+GPIO(EC_EDID_WRITE_EN_L,	PIN(B, 5), GPIO_ODR_HIGH)
 
 /* NC pins, enable internal pull-down to avoid floating state. */
+GPIO(GPIOA0_NC, PIN(A, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOA2_NC, PIN(A, 2), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOA3_NC, PIN(A, 3), GPIO_INPUT | GPIO_PULL_DOWN)
 GPIO(GPIOC0_NC, PIN(C, 0), GPIO_INPUT | GPIO_PULL_DOWN)
 GPIO(GPIOC3_NC, PIN(C, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOE6_NC, PIN(E, 6), GPIO_INPUT | GPIO_PULL_DOWN)
 GPIO(GPIOG3_NC, PIN(G, 3), GPIO_INPUT | GPIO_PULL_DOWN)
 GPIO(GPIOG4_NC, PIN(G, 4), GPIO_INPUT | GPIO_PULL_DOWN)
 GPIO(GPIOG5_NC, PIN(G, 5), GPIO_INPUT | GPIO_PULL_DOWN)
 GPIO(GPIOG6_NC, PIN(G, 6), GPIO_INPUT | GPIO_PULL_DOWN)
 GPIO(GPIOG7_NC, PIN(G, 7), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ4_NC, PIN(J, 4), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ5_NC, PIN(J, 5), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(GPIOJ6_NC, PIN(J, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOI4_NC, PIN(I, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOI6_NC, PIN(I, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOI7_NC, PIN(I, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(GPIOK7_NC, PIN(K, 7), GPIO_INPUT | GPIO_PULL_DOWN)
 GPIO(GPIOM6_NC, PIN(M, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSI0_NC, 	PIN(KSI, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSI1_NC, 	PIN(KSI, 1), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSI2_NC, 	PIN(KSI, 2), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSI3_NC, 	PIN(KSI, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSI4_NC, 	PIN(KSI, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSI6_NC, 	PIN(KSI, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSI7_NC, 	PIN(KSI, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSO0_NC, 	PIN(KSO_L, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSO1_NC, 	PIN(KSO_L, 1), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSO3_NC, 	PIN(KSO_L, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSO4_NC, 	PIN(KSO_L, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSO5_NC, 	PIN(KSO_L, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSO6_NC, 	PIN(KSO_L, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSO7_NC, 	PIN(KSO_L, 7), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSO8_NC, 	PIN(KSO_H, 0), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSO9_NC, 	PIN(KSO_H, 1), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSO10_NC, 	PIN(KSO_H, 2), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSO11_NC, 	PIN(KSO_H, 3), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSO12_NC, 	PIN(KSO_H, 4), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSO13_NC, 	PIN(KSO_H, 5), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSO14_NC, 	PIN(KSO_H, 6), GPIO_INPUT | GPIO_PULL_DOWN)
+GPIO(KSO15_NC, 	PIN(KSO_H, 7), GPIO_INPUT | GPIO_PULL_DOWN)
 
 /* LED */
-GPIO(BAT_LED_AMBER_L,	 PIN(A, 1), GPIO_OUT_HIGH)
-GPIO(BAT_LED_WHITE_L,	 PIN(A, 2), GPIO_OUT_HIGH)
-GPIO(PWR_LED_WHITE_L,	 PIN(A, 3), GPIO_OUT_HIGH)
+GPIO(PWR_LED_WHITE_L,	 PIN(A, 1), GPIO_OUT_HIGH)
 
 /* Alternate functions GPIO definitions */
-/* Keyboard */
-ALTERNATE(PIN_MASK(KSI,   0xFF), 0, MODULE_KEYBOARD_SCAN, 0)		/* KSI0-7 */
-ALTERNATE(PIN_MASK(KSO_H, 0xFF), 0, MODULE_KEYBOARD_SCAN, 0)		/* KSO8-15 */
-ALTERNATE(PIN_MASK(KSO_L, 0xFB), 0, MODULE_KEYBOARD_SCAN, 0)		/* KSO0-1, 3-7 */
 GPIO(EC_KSO_02_INV, PIN(KSO_L, 2), GPIO_OUT_HIGH)			/* KSO2 inverted */
 
 /* UART */
@@ -143,6 +161,3 @@ ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), 0, MODULE_I2C, 0)		/* I2C5 */
 /* ADC */
 ALTERNATE(PIN_MASK(L, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0)	/* ADC13: EC_SUB_ANALOG, ADC15: TEMP_SENSOR_3, ADC16: TEMP_SENSOR_4 */
 ALTERNATE(PIN_MASK(I, BIT(0) | BIT(2) | BIT(3)), 0, MODULE_ADC, 0)	/* ADC0: EC_VSNS_PP3300_A, ADC2: TEMP_SENSOR_1, ADC3: TEMP_SENSOR_2 */
-
-/* PWM */
-ALTERNATE(PIN_MASK(A, BIT(0)), 0, MODULE_PWM, 0) 			/* KB_BL_PWM */
diff --git a/board/shotzo/led.c b/board/shotzo/led.c
index 761b4b4047..9ca9e7a498 100644
--- a/board/shotzo/led.c
+++ b/board/shotzo/led.c
@@ -1,58 +1,45 @@
-/* Copyright 2022 The ChromiumOS Authors.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-/* Shotzo specific LED settings. */
+/* Power LED control for Shotzo.
+ * Solid white - active power
+ * 25% duty cycle white, 1s on and 3s off- suspend
+ * Blinking quicky white, 0.5s on and 0.5s off - alert
+ * 2 long 2 short white, long for 1s, short for 0.5s and interval
+ * is 0.5s - critical
+ * Off - shut down
+ */
 
-#include "cbi_fw_config.h"
-#include "charge_state.h"
-#include "extpower.h"
+#include "chipset.h"
+#include "console.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "led_common.h"
+#include "timer.h"
+#include "util.h"
 
-#define BAT_LED_ON 0
-#define BAT_LED_OFF 1
+/*
+ * Due to the CSME-Lite processing, upon startup the CPU transitions through
+ * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so
+ * delay turning off the LED during suspend/shutdown.
+ */
+#define LED_CPU_DELAY_MS (2000 * MSEC)
 
 #define POWER_LED_ON 0
 #define POWER_LED_OFF 1
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 enum led_color {
 	LED_OFF = 0,
-	LED_AMBER,
 	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
-static int led_set_color_battery(enum led_color color)
-{
-	switch (color) {
-	case LED_OFF:
-		gpio_set_level(GPIO_BAT_LED_WHITE_L, BAT_LED_OFF);
-		gpio_set_level(GPIO_BAT_LED_AMBER_L, BAT_LED_OFF);
-		break;
-	case LED_WHITE:
-		gpio_set_level(GPIO_BAT_LED_WHITE_L, BAT_LED_ON);
-		gpio_set_level(GPIO_BAT_LED_AMBER_L, BAT_LED_OFF);
-		break;
-	case LED_AMBER:
-		gpio_set_level(GPIO_BAT_LED_WHITE_L, BAT_LED_OFF);
-		gpio_set_level(GPIO_BAT_LED_AMBER_L, BAT_LED_ON);
-		break;
-	default:
-		return EC_ERROR_UNKNOWN;
-	}
-	return EC_SUCCESS;
-}
-
 static int led_set_color_power(enum led_color color)
 {
 	switch (color) {
@@ -68,29 +55,11 @@ static int led_set_color_power(enum led_color color)
 	return EC_SUCCESS;
 }
 
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	switch (led_id) {
-	case EC_LED_ID_BATTERY_LED:
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		break;
-	case EC_LED_ID_POWER_LED:
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-		break;
-	default:
-		break;
-	}
-}
-
 static int led_set_color(enum ec_led_id led_id, enum led_color color)
 {
 	int rv;
 
 	switch (led_id) {
-	case EC_LED_ID_BATTERY_LED:
-		rv = led_set_color_battery(color);
-		break;
 	case EC_LED_ID_POWER_LED:
 		rv = led_set_color_power(color);
 		break;
@@ -100,105 +69,174 @@ static int led_set_color(enum ec_led_id led_id, enum led_color color)
 	return rv;
 }
 
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+/* When blinking is enabled, led will blinking according to led_blinking_array.
+ * 1 means led on, 0 means led off, restart from head after reaching the tail.
+ * The interval is LED_BLINKING_MS.
+ */
+#define LED_BLINKING_MS (500 * MSEC)
+static int *led_blinking_array;
+static int led_blinking_count;
+static int led_blinking_index;
+static void led_blinking(void);
+DECLARE_DEFERRED(led_blinking);
+static void led_blinking(void)
 {
-	if (brightness[EC_LED_COLOR_WHITE] != 0)
-		led_set_color(led_id, LED_WHITE);
-	else if (brightness[EC_LED_COLOR_AMBER] != 0)
-		led_set_color(led_id, LED_AMBER);
-	else
-		led_set_color(led_id, LED_OFF);
+	uint32_t elapsed;
+	uint32_t next = 0;
+	uint32_t start = get_time().le.lo;
+	int signal;
 
-	return EC_SUCCESS;
+	if (led_blinking_array == NULL)
+		return;
+
+	if (led_blinking_index > (led_blinking_count - 1))
+		led_blinking_index = 0;
+
+	signal = *(led_blinking_array + led_blinking_index);
+
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED)) {
+		switch (signal) {
+		case 0:
+			led_set_color(EC_LED_ID_POWER_LED, LED_OFF);
+			led_blinking_index += 1;
+			break;
+		case 1:
+			led_set_color(EC_LED_ID_POWER_LED, LED_WHITE);
+			led_blinking_index += 1;
+			break;
+		default:
+			led_blinking_index = 0;
+		}
+	}
+
+	elapsed = get_time().le.lo - start;
+	next = elapsed < LED_BLINKING_MS ? LED_BLINKING_MS - elapsed : 0;
+	hook_call_deferred(&led_blinking_data, next);
 }
 
-static void led_set_battery(void)
+static int led_suspend_array[] = { 1, 1, 0, 0, 0, 0, 0, 0 };
+const int led_suspend_count = ARRAY_SIZE(led_suspend_array);
+static void led_suspend(void)
 {
-	static int battery_ticks;
-	static int power_ticks;
-	uint32_t chflags = charge_get_flags();
-
-	battery_ticks++;
-
-	/*
-	 * Override battery LED for Drawlet/Drawman, Drawlet/Drawman
-	 * don't have power LED, blinking battery white LED to indicate
-	 * system suspend without charging.
-	 */
-	if (get_cbi_fw_config_tablet_mode() == TABLET_MODE_ABSENT) {
-		if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
-			charge_get_state() != PWR_STATE_CHARGE) {
-			led_set_color_battery(power_ticks++ & 0x2 ?
-						  LED_WHITE : LED_OFF);
-			return;
-		}
+	led_blinking_array = led_suspend_array;
+	led_blinking_count = led_suspend_count;
+	led_blinking_index = 0;
+	led_blinking();
+}
+DECLARE_DEFERRED(led_suspend);
+
+static void led_shutdown(void)
+{
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		led_set_color(EC_LED_ID_POWER_LED, LED_OFF);
+}
+DECLARE_DEFERRED(led_shutdown);
+
+static void led_suspend_hook(void)
+{
+	hook_call_deferred(&led_blinking_data, -1);
+	hook_call_deferred(&led_shutdown_data, -1);
+	hook_call_deferred(&led_suspend_data, LED_CPU_DELAY_MS);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, led_suspend_hook, HOOK_PRIO_DEFAULT);
+
+static void led_shutdown_hook(void)
+{
+	hook_call_deferred(&led_blinking_data, -1);
+	hook_call_deferred(&led_suspend_data, -1);
+	hook_call_deferred(&led_shutdown_data, LED_CPU_DELAY_MS);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, led_shutdown_hook, HOOK_PRIO_DEFAULT);
+
+static void led_resume_hook(void)
+{
+	hook_call_deferred(&led_blinking_data, -1);
+	hook_call_deferred(&led_suspend_data, -1);
+	hook_call_deferred(&led_shutdown_data, -1);
+
+	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
+		led_set_color(EC_LED_ID_POWER_LED, LED_WHITE);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, led_resume_hook, HOOK_PRIO_DEFAULT);
+
+static int led_alert_array[] = { 1, 0 };
+const int led_alert_count = ARRAY_SIZE(led_alert_array);
+void led_alert(int enable)
+{
+	if (enable) {
+		/* Overwrite the current signal */
+		hook_call_deferred(&led_blinking_data, -1);
+		led_blinking_array = led_alert_array;
+		led_blinking_count = led_alert_count;
+		led_blinking_index = 0;
+		led_blinking();
+	} else {
+		/* Restore the previous signal */
+		if (chipset_in_state(CHIPSET_STATE_ON))
+			led_resume_hook();
+		else if (chipset_in_state(CHIPSET_STATE_SUSPEND))
+			led_suspend_hook();
+		else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+			led_shutdown_hook();
 	}
+}
 
-	power_ticks = 0;
+static int led_critical_array[] = { 1, 1, 0, 1, 1, 0, 1, 0, 1, 0 };
+const int led_critical_count = ARRAY_SIZE(led_critical_array);
+void show_critical_error(void)
+{
+	hook_call_deferred(&led_blinking_data, -1);
+	led_blinking_array = led_critical_array;
+	led_blinking_count = led_critical_count;
+	led_blinking_index = 0;
+	led_blinking();
+}
 
-	switch (charge_get_state()) {
-	case PWR_STATE_CHARGE:
-		led_set_color_battery(LED_AMBER);
-		break;
-	case PWR_STATE_DISCHARGE_FULL:
-		if (extpower_is_present()) {
-			led_set_color_battery(LED_WHITE);
-			break;
-		}
-		/* Intentional fall-through */
-	case PWR_STATE_DISCHARGE:
-		/*
-		 * Blink white light (1 sec on, 1 sec off)
-		 * when battery capacity is less than 10%
-		 */
-		if (charge_get_percent() < 10)
-			led_set_color_battery(
-				(battery_ticks & 0x2) ? LED_WHITE : LED_OFF);
-		else
-			led_set_color_battery(LED_OFF);
-		break;
-	case PWR_STATE_ERROR:
-		led_set_color_battery(
-			(battery_ticks % 0x2) ? LED_WHITE : LED_OFF);
-		break;
-	case PWR_STATE_CHARGE_NEAR_FULL:
-		led_set_color_battery(LED_WHITE);
-		break;
-	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			led_set_color_battery(
-				(battery_ticks & 0x2) ? LED_AMBER : LED_OFF);
-		else
-			led_set_color_battery(LED_WHITE);
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	switch (led_id) {
+	case EC_LED_ID_POWER_LED:
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
 		break;
 	default:
-		/* Other states don't alter LED behavior */
 		break;
 	}
 }
 
-static void led_set_power(void)
+int led_set_brightness(enum ec_led_id id, const uint8_t *brightness)
 {
-	static int power_tick;
-
-	power_tick++;
-
-	if (chipset_in_state(CHIPSET_STATE_ON))
-		led_set_color_power(LED_WHITE);
-	else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-		led_set_color_power(
-			(power_tick & 0x2) ? LED_WHITE : LED_OFF);
+	if (brightness[EC_LED_COLOR_WHITE] != 0)
+		led_set_color(id, LED_WHITE);
 	else
-		led_set_color_power(LED_OFF);
+		led_set_color(id, LED_OFF);
+
+	return EC_SUCCESS;
 }
 
-/* Called by hook task every TICK */
-static void led_tick(void)
+static int command_led(int argc, const char **argv)
 {
-	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		led_set_power();
-
-	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
-		led_set_battery();
+	enum ec_led_id id = EC_LED_ID_POWER_LED;
+
+	if (argc < 2)
+		return EC_ERROR_PARAM_COUNT;
+
+	if (!strcasecmp(argv[1], "debug")) {
+		led_auto_control(id, !led_auto_control_is_enabled(id));
+		ccprintf("o%s\n", led_auto_control_is_enabled(id) ? "ff" : "n");
+	} else if (!strcasecmp(argv[1], "off")) {
+		led_set_color(id, LED_OFF);
+	} else if (!strcasecmp(argv[1], "white")) {
+		led_set_color(id, LED_WHITE);
+	} else if (!strcasecmp(argv[1], "alert")) {
+		led_alert(1);
+	} else if (!strcasecmp(argv[1], "crit")) {
+		show_critical_error();
+	} else if (!strcasecmp(argv[1], "resume")) {
+		led_resume_hook();
+	} else {
+		return EC_ERROR_PARAM1;
+	}
+	return EC_SUCCESS;
 }
-DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
+DECLARE_CONSOLE_COMMAND(led, command_led, "[debug|white|off|alert|crit|resume]",
+			"Turn on/off LED.");
diff --git a/board/shotzo/usb_pd_policy.c b/board/shotzo/usb_pd_policy.c
index 1bba648eba..8c2b840121 100644
--- a/board/shotzo/usb_pd_policy.c
+++ b/board/shotzo/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The ChromiumOS Authors.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,8 +13,8 @@
 #include "driver/tcpm/tcpci.h"
 #include "usb_pd.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
@@ -65,21 +65,18 @@ int pd_set_power_supply_ready(int port)
 
 __override bool pd_check_vbus_level(int port, enum vbus_level level)
 {
-	int vbus_voltage;
-
-	/* If we're unable to speak to the charger, best to guess false */
-	if (charger_get_vbus_voltage(port, &vbus_voltage))
-		return false;
-
-	if (level == VBUS_SAFE0V)
-		return vbus_voltage < PD_V_SAFE0V_MAX;
-	else if (level == VBUS_PRESENT)
-		return vbus_voltage > PD_V_SAFE5V_MIN;
-	else
-		return vbus_voltage < PD_V_SINK_DISCONNECT_MAX;
+	return sm5803_check_vbus_level(port, level);
 }
 
 int pd_snk_is_vbus_provided(int port)
 {
 	return sm5803_is_vbus_present(port);
 }
+
+int board_vbus_source_enabled(int port)
+{
+	/* Ignore non-PD ports (the barrel jack). */
+	if (port >= CONFIG_USB_PD_PORT_MAX_COUNT)
+		return 0;
+	return charger_is_sourcing_otg_power(port);
+}
diff --git a/board/shuboz/battery.c b/board/shuboz/battery.c
index 155cadab41..f24c50d931 100644
--- a/board/shuboz/battery.c
+++ b/board/shuboz/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -133,7 +133,7 @@ int charger_profile_override(struct charge_state_data *curr)
 		return 0;
 
 	if (current_level != 0) {
-		if (curr->requested_current > current_table[current_level-1])
+		if (curr->requested_current > current_table[current_level - 1])
 			curr->requested_current =
 				current_table[current_level - 1];
 	}
diff --git a/board/shuboz/board.c b/board/shuboz/board.c
index 027a6ee634..41d985df7c 100644
--- a/board/shuboz/board.c
+++ b/board/shuboz/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,7 +13,7 @@
 #include "driver/accel_kionix.h"
 #include "driver/accel_kx022.h"
 #include "driver/bc12/pi3usb9201.h"
-#include "driver/ppc/aoz1380.h"
+#include "driver/ppc/aoz1380_public.h"
 #include "driver/ppc/nx20p348x.h"
 #include "driver/tcpm/nct38xx.h"
 #include "driver/usb_mux/amd_fp5.h"
@@ -39,8 +39,8 @@
 #include "usb_pd_tcpm.h"
 #include "usbc_ppc.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* This I2C moved. Temporarily detect and support the V0 HW. */
 int I2C_PORT_BATTERY = I2C_PORT_BATTERY_V1;
@@ -62,15 +62,13 @@ static const mat33_fp_t lid_standard_ref = {
 	{ 0, FLOAT_TO_FP(-1), 0 },
 	{ 0, 0, FLOAT_TO_FP(-1) },
 };
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+					      { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
 static const mat33_fp_t base_standard_ref_icm = {
-	{FLOAT_TO_FP(1), 0, 0},
-	{0, FLOAT_TO_FP(-1), 0},
-	{0, 0, FLOAT_TO_FP(-1)},
+	{ FLOAT_TO_FP(1), 0, 0 },
+	{ 0, FLOAT_TO_FP(-1), 0 },
+	{ 0, 0, FLOAT_TO_FP(-1) },
 };
 
 /* TODO(gcc >= 5.0) Remove the casts to const pointer at rot_standard_ref */
@@ -226,8 +224,7 @@ static void board_chipset_suspend(void)
 }
 DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
 
-static int board_ps8743_mux_set(const struct usb_mux *me,
-				mux_state_t mux_state)
+static int board_ps8743_mux_set(const struct usb_mux *me, mux_state_t mux_state)
 {
 	int res;
 
@@ -242,7 +239,6 @@ static int board_ps8743_mux_set(const struct usb_mux *me,
 	return res;
 }
 
-
 /*****************************************************************************
  * USB-C
  */
@@ -280,34 +276,44 @@ const struct usb_mux_driver usbc0_sbu_mux_driver = {
  * Since FSUSB42UMX is not a i2c device, .i2c_port and
  * .i2c_addr_flags are not required here.
  */
-const struct usb_mux usbc0_sbu_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &usbc0_sbu_mux_driver,
+const struct usb_mux_chain usbc0_sbu_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &usbc0_sbu_mux_driver,
+		},
 };
 
-struct usb_mux usbc1_amd_fp5_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.i2c_port = I2C_PORT_USB_AP_MUX,
-	.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
-	.driver = &amd_fp5_usb_mux_driver,
-	.flags = USB_MUX_FLAG_SET_WITHOUT_FLIP,
+struct usb_mux_chain usbc1_amd_fp5_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.i2c_port = I2C_PORT_USB_AP_MUX,
+			.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
+			.driver = &amd_fp5_usb_mux_driver,
+			.flags = USB_MUX_FLAG_SET_WITHOUT_FLIP,
+		},
 };
 
-struct usb_mux usb_muxes[] = {
+struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.i2c_port = I2C_PORT_USB_AP_MUX,
-		.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
-		.driver = &amd_fp5_usb_mux_driver,
-		.next_mux = &usbc0_sbu_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.i2c_port = I2C_PORT_USB_AP_MUX,
+			.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
+			.driver = &amd_fp5_usb_mux_driver,
+		},
+		.next = &usbc0_sbu_mux,
 	},
 	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = PS8743_I2C_ADDR1_FLAG,
-		.driver = &ps8743_usb_mux_driver,
-		.board_set = &board_ps8743_mux_set,
-		.next_mux = &usbc1_amd_fp5_usb_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.i2c_port = I2C_PORT_TCPC1,
+			.i2c_addr_flags = PS8743_I2C_ADDR1_FLAG,
+			.driver = &ps8743_usb_mux_driver,
+			.board_set = &board_ps8743_mux_set,
+		},
+		.next = &usbc1_amd_fp5_usb_mux,
 	}
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
@@ -350,8 +356,7 @@ void ppc_interrupt(enum gpio_signal signal)
 
 int board_set_active_charge_port(int port)
 {
-	int is_valid_port = (port >= 0 &&
-			     port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	int i;
 
 	if (port == CHARGE_PORT_NONE) {
@@ -372,7 +377,6 @@ int board_set_active_charge_port(int port)
 		return EC_ERROR_INVAL;
 	}
 
-
 	/* Check if the port is sourcing VBUS. */
 	if (ppc_is_sourcing_vbus(port)) {
 		CPRINTFUSB("Skip enable C%d", port);
@@ -474,7 +478,6 @@ static void reset_nct38xx_port(int port)
 		msleep(NCT3807_RESET_POST_DELAY_MS);
 }
 
-
 void board_reset_pd_mcu(void)
 {
 	/* Reset TCPC0 */
@@ -545,11 +548,9 @@ int board_pd_set_frs_enable(int port, int enable)
 
 	/* Use the TCPC to enable fast switch when FRS included */
 	if (port == USBC_PORT_C0) {
-		rv = ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN,
-				    !!enable);
+		rv = ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN, !!enable);
 	} else {
-		rv = ioex_set_level(IOEX_USB_C1_TCPC_FASTSW_CTL_EN,
-				    !!enable);
+		rv = ioex_set_level(IOEX_USB_C1_TCPC_FASTSW_CTL_EN, !!enable);
 	}
 
 	return rv;
diff --git a/board/shuboz/board.h b/board/shuboz/board.h
index 6573273b93..ada5b1499d 100644
--- a/board/shuboz/board.h
+++ b/board/shuboz/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,11 +21,11 @@
 #define CONFIG_USB_PD_PORT_MAX_COUNT 2
 #define CONFIG_USB_PORT_ENABLE_DYNAMIC
 
-#undef  PD_MAX_POWER_MW
-#define PD_MAX_POWER_MW		45000
-#undef  PD_MAX_CURRENT_MA
-#define PD_MAX_CURRENT_MA	3000
-#undef  CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
+#undef PD_MAX_POWER_MW
+#define PD_MAX_POWER_MW 45000
+#undef PD_MAX_CURRENT_MA
+#define PD_MAX_CURRENT_MA 3000
+#undef CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
 #define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 40000
 
 #define CONFIG_CHARGER_PROFILE_OVERRIDE
@@ -61,59 +61,46 @@
 #define CONFIG_POWER_BUTTON_INIT_TIMEOUT 5
 
 /* GPIO mapping from board specific name to EC common name. */
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_EC_BATT_PRES_ODL
-#define CONFIG_SCI_GPIO			GPIO_EC_FCH_SCI_ODL
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_AP_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT_L		GPIO_EC_EDP_BL_DISABLE
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_FCH_PWR_BTN_L
-#define GPIO_PCH_RSMRST_L		GPIO_EC_FCH_RSMRST_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S5_L		GPIO_SLP_S5_L
-#define GPIO_PCH_SYS_PWROK		GPIO_EC_FCH_PWROK
-#define GPIO_PCH_WAKE_L			GPIO_EC_FCH_WAKE_L
-#define GPIO_POWER_BUTTON_L		GPIO_EC_PWR_BTN_ODL
-#define GPIO_S0_PGOOD			GPIO_S0_PWROK_OD
-#define GPIO_S5_PGOOD			GPIO_EC_PWROK_OD
-#define GPIO_SYS_RESET_L		GPIO_EC_SYS_RST_L
-#define GPIO_VOLUME_DOWN_L		GPIO_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
+#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL
+#define CONFIG_SCI_GPIO GPIO_EC_FCH_SCI_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_AP_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_EDP_BL_DISABLE
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PCH_PWRBTN_L GPIO_EC_FCH_PWR_BTN_L
+#define GPIO_PCH_RSMRST_L GPIO_EC_FCH_RSMRST_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L
+#define GPIO_PCH_SYS_PWROK GPIO_EC_FCH_PWROK
+#define GPIO_PCH_WAKE_L GPIO_EC_FCH_WAKE_L
+#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL
+#define GPIO_S0_PGOOD GPIO_S0_PWROK_OD
+#define GPIO_S5_PGOOD GPIO_EC_PWROK_OD
+#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L
+#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
 
 #ifndef __ASSEMBLER__
 
 /* This I2C moved. Temporarily detect and support the V0 HW. */
 extern int I2C_PORT_BATTERY;
 
-enum adc_channel {
-	ADC_TEMP_SENSOR_CHARGER,
-	ADC_TEMP_SENSOR_SOC,
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_TEMP_SENSOR_CHARGER, ADC_TEMP_SENSOR_SOC, ADC_CH_COUNT };
 
 enum battery_type {
 	BATTERY_CM1500,
 	BATTERY_TYPE_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_COUNT };
 
-enum ioex_port {
-	IOEX_C0_NCT3807 = 0,
-	IOEX_C1_NCT3807,
-	IOEX_PORT_COUNT
-};
+enum ioex_port { IOEX_C0_NCT3807 = 0, IOEX_C1_NCT3807, IOEX_PORT_COUNT };
 
-#define PORT_TO_HPD(port) ((port == 0) \
-	? GPIO_USB3_C0_DP2_HPD \
-	: GPIO_DP1_HPD)
+#define PORT_TO_HPD(port) ((port == 0) ? GPIO_USB3_C0_DP2_HPD : GPIO_DP1_HPD)
 
 enum temp_sensor_id {
 	TEMP_SENSOR_CHARGER = 0,
@@ -122,17 +109,9 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum usba_port {
-	USBA_PORT_A0 = 0,
-	USBA_PORT_A1,
-	USBA_PORT_COUNT
-};
+enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT };
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 /*****************************************************************************
  * CBI EC FW Configuration
diff --git a/board/shuboz/build.mk b/board/shuboz/build.mk
index 1c0cbc4f63..45c71f962c 100644
--- a/board/shuboz/build.mk
+++ b/board/shuboz/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/shuboz/ec.tasklist b/board/shuboz/ec.tasklist
index d9c1606eb2..abc796f74f 100644
--- a/board/shuboz/ec.tasklist
+++ b/board/shuboz/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/shuboz/gpio.inc b/board/shuboz/gpio.inc
index b093a7e6d6..c824a80cd4 100644
--- a/board/shuboz/gpio.inc
+++ b/board/shuboz/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/shuboz/led.c b/board/shuboz/led.c
index af91f32ec6..dc3361ba5a 100644
--- a/board/shuboz/led.c
+++ b/board/shuboz/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,28 +9,37 @@
 #include "led_common.h"
 #include "led_onoff_states.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
 __override const int led_charge_lvl_1;
 __override const int led_charge_lvl_2 = 95;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]       = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]       = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC},
-					{LED_OFF,            2 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]	     = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { LED_OFF, 2 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
 BUILD_ASSERT(ARRAY_SIZE(led_bat_state_table) == LED_NUM_STATES);
 
diff --git a/board/spherion/battery.c b/board/spherion/battery.c
index 3613a4750c..83361bd9fc 100644
--- a/board/spherion/battery.c
+++ b/board/spherion/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -88,11 +88,12 @@ int charger_profile_override(struct charge_state_data *curr)
 		temp_sensor_read(TEMP_SENSOR_CHARGER, &charger_temp);
 		charger_temp_c = K_TO_C(charger_temp);
 		if (charger_temp_c > 52)
-			curr->requested_current = MIN(curr->requested_current,
-			    2200);
+			curr->requested_current =
+				MIN(curr->requested_current, 2200);
 		else if (charger_temp_c > 48)
-			curr->requested_current = MIN(curr->requested_current,
-			    CONFIG_CHARGER_MAX_INPUT_CURRENT);
+			curr->requested_current =
+				MIN(curr->requested_current,
+				    CONFIG_CHARGER_MAX_INPUT_CURRENT);
 	}
 
 	return 0;
diff --git a/board/spherion/board.c b/board/spherion/board.c
index 95fa0a06de..0170a8998e 100644
--- a/board/spherion/board.c
+++ b/board/spherion/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -46,30 +46,30 @@
 #include "usb_pd_tcpm.h"
 #include "usbc_ppc.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
 	/* Convert to mV (3000mV/1024). */
-	{"VBUS_C0", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0, CHIP_ADC_CH0},
-	{"BOARD_ID_0", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH1},
-	{"BOARD_ID_1", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH2},
+	{ "VBUS_C0", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0, CHIP_ADC_CH0 },
+	{ "BOARD_ID_0", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH1 },
+	{ "BOARD_ID_1", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH2 },
 	/* AMON/BMON gain = 17.97 */
-	{"CHARGER_AMON_R", ADC_MAX_MVOLT * 1000 / 17.97, ADC_READ_MAX + 1, 0,
-	 CHIP_ADC_CH3},
-	{"VBUS_C1", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0, CHIP_ADC_CH5},
-	{"CHARGER_PMON", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH6},
-	{"TEMP_SENSOR_CHARGER", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0,
-	 CHIP_ADC_CH7},
+	{ "CHARGER_AMON_R", ADC_MAX_MVOLT * 1000 / 17.97, ADC_READ_MAX + 1, 0,
+	  CHIP_ADC_CH3 },
+	{ "VBUS_C1", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0, CHIP_ADC_CH5 },
+	{ "CHARGER_PMON", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH6 },
+	{ "TEMP_SENSOR_CHARGER", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0,
+	  CHIP_ADC_CH7 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
+	[TEMP_SENSOR_CHARGER] = { .name = "Charger",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_30k9_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_CHARGER },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -82,12 +82,10 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
  * number of pwm channel greater than three.
  */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT] = {
-		.channel = PWM_HW_CH_DCR2,
-		.flags = 0,
-		.freq_hz = 10000,
-		.pcfsr_sel = PWM_PRESCALER_C4
-	},
+	[PWM_CH_KBLIGHT] = { .channel = PWM_HW_CH_DCR2,
+			     .flags = 0,
+			     .freq_hz = 10000,
+			     .pcfsr_sel = PWM_PRESCALER_C4 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
@@ -106,13 +104,11 @@ DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, kb_backlight_disable, HOOK_PRIO_DEFAULT);
 void board_usb_mux_init(void)
 {
 	if (board_get_sub_board() == SUB_BOARD_TYPEC) {
-		ps8743_tune_usb_eq(&usb_muxes[1],
-				   PS8743_USB_EQ_TX_12_8_DB,
+		ps8743_tune_usb_eq(usb_muxes[1].mux, PS8743_USB_EQ_TX_12_8_DB,
 				   PS8743_USB_EQ_RX_12_8_DB);
-		ps8743_field_update(&usb_muxes[1],
-				   PS8743_REG_DCI_CONFIG_2,
-				   PS8743_AUTO_DCI_MODE_MASK,
-				   PS8743_AUTO_DCI_MODE_FORCE_USB);
+		ps8743_field_update(usb_muxes[1].mux, PS8743_REG_DCI_CONFIG_2,
+				    PS8743_AUTO_DCI_MODE_MASK,
+				    PS8743_AUTO_DCI_MODE_FORCE_USB);
 	}
 }
 DECLARE_HOOK(HOOK_INIT, board_usb_mux_init, HOOK_PRIO_INIT_I2C + 1);
diff --git a/board/spherion/board.h b/board/spherion/board.h
index a27258bc94..07f36a4efc 100644
--- a/board/spherion/board.h
+++ b/board/spherion/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -45,7 +45,7 @@
 #define PD_MAX_CURRENT_MA CONFIG_CHARGER_MAX_INPUT_CURRENT
 #define PD_MAX_VOLTAGE_MV 20000
 #define PD_OPERATING_POWER_MW 15000
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
 #undef CONFIG_SYV682X_HV_ILIM
 #define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_5_50
@@ -75,18 +75,15 @@ enum battery_type {
 	BATTERY_TYPE_COUNT,
 };
 
-enum temp_sensor_id {
-	TEMP_SENSOR_CHARGER,
-	TEMP_SENSOR_COUNT
-};
+enum temp_sensor_id { TEMP_SENSOR_CHARGER, TEMP_SENSOR_COUNT };
 
 enum adc_channel {
-	ADC_VBUS_C0,             /* ADC 0 */
-	ADC_BOARD_ID_0,          /* ADC 1 */
-	ADC_BOARD_ID_1,          /* ADC 2 */
-	ADC_CHARGER_AMON_R,      /* ADC 3 */
-	ADC_VBUS_C1,             /* ADC 5 */
-	ADC_CHARGER_PMON,        /* ADC 6 */
+	ADC_VBUS_C0, /* ADC 0 */
+	ADC_BOARD_ID_0, /* ADC 1 */
+	ADC_BOARD_ID_1, /* ADC 2 */
+	ADC_CHARGER_AMON_R, /* ADC 3 */
+	ADC_VBUS_C1, /* ADC 5 */
+	ADC_CHARGER_PMON, /* ADC 6 */
 	ADC_TEMP_SENSOR_CHARGER, /* ADC 7 */
 	/* Number of ADC channels */
 	ADC_CH_COUNT,
diff --git a/board/spherion/build.mk b/board/spherion/build.mk
index 4dc5a3e62e..9126acf43f 100644
--- a/board/spherion/build.mk
+++ b/board/spherion/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/spherion/ec.tasklist b/board/spherion/ec.tasklist
index c92920ade6..ea717385a0 100644
--- a/board/spherion/ec.tasklist
+++ b/board/spherion/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/spherion/gpio.inc b/board/spherion/gpio.inc
index b618911e02..177ccd07ca 100644
--- a/board/spherion/gpio.inc
+++ b/board/spherion/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/spherion/led.c b/board/spherion/led.c
index aad85d02c1..54f073b8cb 100644
--- a/board/spherion/led.c
+++ b/board/spherion/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -16,19 +16,26 @@ __override const int led_charge_lvl_1 = 5;
 __override const int led_charge_lvl_2 = 95;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
 const enum ec_led_id supported_led_ids[] = {
 	EC_LED_ID_BATTERY_LED,
@@ -61,9 +68,8 @@ void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
 {
 	if (led_id == EC_LED_ID_BATTERY_LED) {
 		brightness_range[EC_LED_COLOR_AMBER] =
-				MT6360_LED_BRIGHTNESS_MAX;
-		brightness_range[EC_LED_COLOR_BLUE] =
-				MT6360_LED_BRIGHTNESS_MAX;
+			MT6360_LED_BRIGHTNESS_MAX;
+		brightness_range[EC_LED_COLOR_BLUE] = MT6360_LED_BRIGHTNESS_MAX;
 	}
 }
 
diff --git a/board/stern/battery.c b/board/stern/battery.c
index 50d2bf397c..9edab52867 100644
--- a/board/stern/battery.c
+++ b/board/stern/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/stern/board.c b/board/stern/board.c
index fd3a95a987..26576ede86 100644
--- a/board/stern/board.c
+++ b/board/stern/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -30,6 +30,7 @@
 #include "it8801.h"
 #include "keyboard_scan.h"
 #include "lid_switch.h"
+#include "panic.h"
 #include "power.h"
 #include "power_button.h"
 #include "pwm.h"
@@ -46,8 +47,8 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
@@ -59,40 +60,34 @@ static void tcpc_alert_event(enum gpio_signal signal)
 /******************************************************************************/
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] =  {"BOARD_ID",  3300, 4096, 0, STM32_AIN(10)},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)},
+	[ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(10) },
+	[ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /******************************************************************************/
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "typec",
-		.port = 0,
-		.kbps = 400,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	},
-	{
-		.name = "other",
-		.port = 1,
-		.kbps = 100,
-		.scl  = GPIO_I2C2_SCL,
-		.sda  = GPIO_I2C2_SDA
-	},
+	{ .name = "typec",
+	  .port = 0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "other",
+	  .port = 1,
+	  .kbps = 100,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
 const struct i2c_port_t i2c_bitbang_ports[] = {
-	{
-		.name = "battery",
-		.port = 2,
-		.kbps = 100,
-		.scl  = GPIO_I2C3_SCL,
-		.sda  = GPIO_I2C3_SDA,
-		.drv = &bitbang_drv
-	},
+	{ .name = "battery",
+	  .port = 2,
+	  .kbps = 100,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA,
+	  .drv = &bitbang_drv },
 };
 const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
 
@@ -100,8 +95,8 @@ const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
 
 /* power signal list.  Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
+	{ GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" },
+	{ GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" },
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
@@ -157,8 +152,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-static void board_hpd_status(const struct usb_mux *me,
-			     mux_state_t mux_state,
+static void board_hpd_status(const struct usb_mux *me, mux_state_t mux_state,
 			     bool *ack_required)
 {
 	/* This driver does not use host command ACKs */
@@ -171,13 +165,16 @@ static void board_hpd_status(const struct usb_mux *me,
 	host_set_single_event(EC_HOST_EVENT_USB_MUX);
 }
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+				.hpd_update = &board_hpd_status,
+			},
 	},
 };
 
@@ -239,12 +236,12 @@ int board_set_active_charge_port(int charge_port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-			       CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 int board_discharge_on_ac(int enable)
@@ -301,8 +298,7 @@ static void board_spi_enable(void)
 	/* Pin mux spi peripheral toward the sensor. */
 	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
 }
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP,
-	     board_spi_enable,
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_spi_enable,
 	     MOTION_SENSE_HOOK_PRIO - 1);
 
 static void board_spi_disable(void)
@@ -316,8 +312,7 @@ static void board_spi_disable(void)
 	spi_enable(&spi_devices[0], 0);
 	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
 }
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN,
-	     board_spi_disable,
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_spi_disable,
 	     MOTION_SENSE_HOOK_PRIO + 1);
 #endif /* !VARIANT_KUKUI_NO_SENSORS */
 
@@ -356,17 +351,13 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Rotation matrixes */
-static const mat33_fp_t base_standard_ref = {
-	{FLOAT_TO_FP(1), 0, 0},
-	{0, FLOAT_TO_FP(-1), 0},
-	{0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, FLOAT_TO_FP(-1), 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
 
-static const mat33_fp_t lid_standard_ref = {
-	{FLOAT_TO_FP(1), 0, 0},
-	{0, FLOAT_TO_FP(1), 0},
-	{0, 0, FLOAT_TO_FP(1) }
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(1), 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
 
 /* sensor private data */
 /* Lid accel private data */
diff --git a/board/stern/board.h b/board/stern/board.h
index f113969d3d..eedbc2a44c 100644
--- a/board/stern/board.h
+++ b/board/stern/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -55,7 +55,7 @@
 
 /* Motion Sensors */
 #ifndef VARIANT_KUKUI_NO_SENSORS
-#define CONFIG_ACCEL_LIS2DWL    /* Lid accel */
+#define CONFIG_ACCEL_LIS2DWL /* Lid accel */
 #define CONFIG_ACCELGYRO_BMI160 /* Base accel */
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
@@ -71,20 +71,20 @@
 #endif /* VARIANT_KUKUI_NO_SENSORS */
 
 /* I2C ports */
-#define I2C_PORT_BC12               0
-#define I2C_PORT_TCPC0              0
-#define I2C_PORT_USB_MUX            0
-#define I2C_PORT_BATTERY            2
-#define I2C_PORT_CHARGER            board_get_charger_i2c()
-#define I2C_PORT_SENSORS            1
-#define I2C_PORT_KB_DISCRETE        1
-#define I2C_PORT_VIRTUAL_BATTERY    I2C_PORT_BATTERY
+#define I2C_PORT_BC12 0
+#define I2C_PORT_TCPC0 0
+#define I2C_PORT_USB_MUX 0
+#define I2C_PORT_BATTERY 2
+#define I2C_PORT_CHARGER board_get_charger_i2c()
+#define I2C_PORT_SENSORS 1
+#define I2C_PORT_KB_DISCRETE 1
+#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
 
 /* IT8801 I2C address */
-#define KB_DISCRETE_I2C_ADDR_FLAGS  IT8801_I2C_ADDR1
+#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1
 
 /* Enable Accel over SPI */
-#define CONFIG_SPI_ACCEL_PORT    0  /* The first SPI controller port (SPI2) */
+#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */
 
 #define CONFIG_KEYBOARD_PROTOCOL_MKBP
 #define CONFIG_MKBP_EVENT
diff --git a/board/stern/build.mk b/board/stern/build.mk
index a6e1c010d7..f583684804 100644
--- a/board/stern/build.mk
+++ b/board/stern/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/stern/ec.tasklist b/board/stern/ec.tasklist
index 36be2e96a4..e77603a8e2 100644
--- a/board/stern/ec.tasklist
+++ b/board/stern/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/stern/gpio.inc b/board/stern/gpio.inc
index 3a162d6124..85d080b2e9 100644
--- a/board/stern/gpio.inc
+++ b/board/stern/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/stern/led.c b/board/stern/led.c
index ac4813c8c0..8a5f9d26d8 100644
--- a/board/stern/led.c
+++ b/board/stern/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -18,32 +18,37 @@ __override const int led_charge_lvl_1 = 5;
 __override const int led_charge_lvl_2 = 95;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
 __override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	   3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_POWER_LED,
-	EC_LED_ID_BATTERY_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED,
+					     EC_LED_ID_BATTERY_LED };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 __override void led_set_color_battery(enum ec_led_colors color)
diff --git a/board/stm32f446e-eval/board.c b/board/stm32f446e-eval/board.c
index fd6ff8bbe2..7039064cbf 100644
--- a/board/stm32f446e-eval/board.c
+++ b/board/stm32f446e-eval/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,12 +20,12 @@
  * Define the strings used in our USB descriptors.
  */
 const void *const usb_strings[] = {
-	[USB_STR_DESC]		= usb_string_desc,
-	[USB_STR_VENDOR]	= USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]	= USB_STRING_DESC("stm32f446-eval"),
-	[USB_STR_SERIALNO]	= USB_STRING_DESC("1234-a"),
-	[USB_STR_VERSION]	= USB_STRING_DESC(CROS_EC_VERSION32),
-	[USB_STR_CONSOLE_NAME]	= USB_STRING_DESC("EC Shell"),
+	[USB_STR_DESC] = usb_string_desc,
+	[USB_STR_VENDOR] = USB_STRING_DESC("Google LLC"),
+	[USB_STR_PRODUCT] = USB_STRING_DESC("stm32f446-eval"),
+	[USB_STR_SERIALNO] = USB_STRING_DESC("1234-a"),
+	[USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32),
+	[USB_STR_CONSOLE_NAME] = USB_STRING_DESC("EC Shell"),
 };
 
 BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
@@ -43,25 +43,21 @@ struct dwc_usb usb_ctl = {
 
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "i2c1",
-		.port = I2C_PORT_0,
-		.kbps = 100,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	},
-	{
-		.name = "fmpi2c4",
-		.port = FMPI2C_PORT_3,
-		.kbps = 100,
-		.scl  = GPIO_FMPI2C_SCL,
-		.sda  = GPIO_FMPI2C_SDA
-	},
+	{ .name = "i2c1",
+	  .port = I2C_PORT_0,
+	  .kbps = 100,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "fmpi2c4",
+	  .port = FMPI2C_PORT_3,
+	  .kbps = 100,
+	  .scl = GPIO_FMPI2C_SCL,
+	  .sda = GPIO_FMPI2C_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
-#define GPIO_SET_HS(bank, number)	\
-	(STM32_GPIO_OSPEEDR(GPIO_##bank) |= (0x3 << ((number) * 2)))
+#define GPIO_SET_HS(bank, number) \
+	(STM32_GPIO_OSPEEDR(GPIO_##bank) |= (0x3 << ((number)*2)))
 
 void board_config_post_gpio_init(void)
 {
@@ -74,27 +70,27 @@ void board_config_post_gpio_init(void)
 	GPIO_SET_HS(A, 11);
 	GPIO_SET_HS(A, 12);
 
-	GPIO_SET_HS(C,  3);
-	GPIO_SET_HS(C,  2);
-	GPIO_SET_HS(C,  0);
-	GPIO_SET_HS(A,  5);
+	GPIO_SET_HS(C, 3);
+	GPIO_SET_HS(C, 2);
+	GPIO_SET_HS(C, 0);
+	GPIO_SET_HS(A, 5);
 
-	GPIO_SET_HS(B,  5);
+	GPIO_SET_HS(B, 5);
 	GPIO_SET_HS(B, 13);
 	GPIO_SET_HS(B, 12);
-	GPIO_SET_HS(B,  2);
+	GPIO_SET_HS(B, 2);
 	GPIO_SET_HS(B, 10);
-	GPIO_SET_HS(B,  1);
-	GPIO_SET_HS(B,  0);
-	GPIO_SET_HS(A,  3);
+	GPIO_SET_HS(B, 1);
+	GPIO_SET_HS(B, 0);
+	GPIO_SET_HS(A, 3);
 
 	/* Set I2C GPIO to HS */
-	GPIO_SET_HS(B,  6);
-	GPIO_SET_HS(B,  7);
-	GPIO_SET_HS(F,  1);
-	GPIO_SET_HS(F,  0);
-	GPIO_SET_HS(A,  8);
-	GPIO_SET_HS(B,  4);
-	GPIO_SET_HS(C,  6);
-	GPIO_SET_HS(C,  7);
+	GPIO_SET_HS(B, 6);
+	GPIO_SET_HS(B, 7);
+	GPIO_SET_HS(F, 1);
+	GPIO_SET_HS(F, 0);
+	GPIO_SET_HS(A, 8);
+	GPIO_SET_HS(B, 4);
+	GPIO_SET_HS(C, 6);
+	GPIO_SET_HS(C, 7);
 }
diff --git a/board/stm32f446e-eval/board.h b/board/stm32f446e-eval/board.h
index aa498d6caa..4ae9117829 100644
--- a/board/stm32f446e-eval/board.h
+++ b/board/stm32f446e-eval/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -43,12 +43,12 @@
 
 /* USB interface indexes (use define rather than enum to expand them) */
 #define USB_IFACE_CONSOLE 0
-#define USB_IFACE_COUNT   1
+#define USB_IFACE_COUNT 1
 
 /* USB endpoint indexes (use define rather than enum to expand them) */
 #define USB_EP_CONTROL 0
 #define USB_EP_CONSOLE 1
-#define USB_EP_COUNT   2
+#define USB_EP_COUNT 2
 
 /* This is not actually an EC so disable some features. */
 #undef CONFIG_WATCHDOG_HELP
diff --git a/board/stm32f446e-eval/build.mk b/board/stm32f446e-eval/build.mk
index 6b06f2bb8f..61e4b79d47 100644
--- a/board/stm32f446e-eval/build.mk
+++ b/board/stm32f446e-eval/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/stm32f446e-eval/ec.tasklist b/board/stm32f446e-eval/ec.tasklist
index 2a1ffbf652..6a12f02976 100644
--- a/board/stm32f446e-eval/ec.tasklist
+++ b/board/stm32f446e-eval/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/stm32f446e-eval/gpio.inc b/board/stm32f446e-eval/gpio.inc
index afc8d1e486..8eb7c6090d 100644
--- a/board/stm32f446e-eval/gpio.inc
+++ b/board/stm32f446e-eval/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/stm32l476g-eval/board.c b/board/stm32l476g-eval/board.c
index 70375abe95..e3f467ac50 100644
--- a/board/stm32l476g-eval/board.c
+++ b/board/stm32l476g-eval/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -32,14 +32,12 @@ void tick_event(void)
 DECLARE_HOOK(HOOK_TICK, tick_event, HOOK_PRIO_DEFAULT);
 
 #ifdef CTS_MODULE_I2C
-const struct i2c_port_t i2c_ports[]  = {
-	{
-		.name = "test",
-		.port = STM32_I2C2_PORT,
-		.kbps = 100,
-		.scl  = GPIO_I2C2_SCL,
-		.sda  = GPIO_I2C2_SDA
-	},
+const struct i2c_port_t i2c_ports[] = {
+	{ .name = "test",
+	  .port = STM32_I2C2_PORT,
+	  .kbps = 100,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 #endif
diff --git a/board/stm32l476g-eval/board.h b/board/stm32l476g-eval/board.h
index e8ce99845f..26ea530e4e 100644
--- a/board/stm32l476g-eval/board.h
+++ b/board/stm32l476g-eval/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,8 +10,8 @@
 
 #ifdef CTS_MODULE
 /* CTS tests are small. We can use smaller size to expedite flash time. */
-#undef  CONFIG_FLASH_SIZE_BYTES
-#define CONFIG_FLASH_SIZE_BYTES 0x00040000	/* 256k */
+#undef CONFIG_FLASH_SIZE_BYTES
+#define CONFIG_FLASH_SIZE_BYTES 0x00040000 /* 256k */
 #endif
 
 /* Optional features */
@@ -54,18 +54,18 @@
 #undef CONFIG_FLASH_PHYSICAL
 
 /* Timer selection */
-#define TIM_CLOCK32	5
+#define TIM_CLOCK32 5
 
 /* External clock speeds (8 MHz) */
 #define STM32_HSE_CLOCK 8000000
 
 /* PLL configuration. Freq = STM32_HSE_CLOCK * n/m/r */
 #undef STM32_PLLM
-#define STM32_PLLM	1
+#define STM32_PLLM 1
 #undef STM32_PLLN
-#define STM32_PLLN	10
+#define STM32_PLLN 10
 #undef STM32_PLLR
-#define STM32_PLLR	2
+#define STM32_PLLR 2
 
 #include "gpio_signal.h"
 
diff --git a/board/stm32l476g-eval/build.mk b/board/stm32l476g-eval/build.mk
index 23c7cd9d38..d453ea9979 100644
--- a/board/stm32l476g-eval/build.mk
+++ b/board/stm32l476g-eval/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/stm32l476g-eval/ec.tasklist b/board/stm32l476g-eval/ec.tasklist
index adfd7c7e92..f580a9d9e5 100644
--- a/board/stm32l476g-eval/ec.tasklist
+++ b/board/stm32l476g-eval/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/stm32l476g-eval/gpio.inc b/board/stm32l476g-eval/gpio.inc
index 9cf5bc0aa4..e84543f8f6 100644
--- a/board/stm32l476g-eval/gpio.inc
+++ b/board/stm32l476g-eval/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/stm32l476g-eval/openocd-flash.cfg b/board/stm32l476g-eval/openocd-flash.cfg
index a347f88b79..2f6a266d93 100644
--- a/board/stm32l476g-eval/openocd-flash.cfg
+++ b/board/stm32l476g-eval/openocd-flash.cfg
@@ -1,4 +1,4 @@
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/board/storo/battery.c b/board/storo/battery.c
index b28e5bbf37..5a927ffc26 100644
--- a/board/storo/battery.c
+++ b/board/storo/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/storo/board.c b/board/storo/board.c
index d7e0305d1f..f6f3ed5750 100644
--- a/board/storo/board.c
+++ b/board/storo/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -48,8 +48,8 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 #define INT_RECHECK_US 5000
 
@@ -139,34 +139,26 @@ static void pen_detect_interrupt(enum gpio_signal s)
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH0
-	},
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH2
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH3
-	},
-	[ADC_TEMP_SENSOR_3] = {
-		.name = "TEMP_SENSOR3",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH15
-	},
+	[ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH0 },
+	[ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH2 },
+	[ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH3 },
+	[ADC_TEMP_SENSOR_3] = { .name = "TEMP_SENSOR3",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH15 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
@@ -226,14 +218,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 };
 
 /* USB Retimer */
-enum tusb544_conf {
-	USB_DP = 0,
-	USB_DP_INV,
-	USB,
-	USB_INV,
-	DP,
-	DP_INV
-};
+enum tusb544_conf { USB_DP = 0, USB_DP_INV, USB, USB_INV, DP, DP_INV };
 
 /*
  * Registers we care about of are all the same between NCS8510 and TUSB544,
@@ -246,33 +231,32 @@ enum tusb544_conf {
  */
 static int board_tusb544_set(const struct usb_mux *me, mux_state_t mux_state)
 {
-	int  rv = EC_SUCCESS;
+	int rv = EC_SUCCESS;
 	int reg;
 	enum tusb544_conf usb_mode = 0;
 
 	if (mux_state & USB_PD_MUX_USB_ENABLED) {
 		if (mux_state & USB_PD_MUX_DP_ENABLED) {
 			/* USB with DP */
-			usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-					? USB_DP_INV
-					: USB_DP;
+			usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ?
+					   USB_DP_INV :
+					   USB_DP;
 		} else {
 			/* USB without DP */
-			usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-					? USB_INV
-					: USB;
+			usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ?
+					   USB_INV :
+					   USB;
 		}
 	} else if (mux_state & USB_PD_MUX_DP_ENABLED) {
 		/* DP without USB */
-		usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-				? DP_INV
-				: DP;
+		usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ? DP_INV :
+									DP;
 	} else {
 		return EC_SUCCESS;
 	}
 
-	rv = i2c_read8(me->i2c_port, me->i2c_addr_flags,
-			TUSB544_REG_GENERAL6, &reg);
+	rv = i2c_read8(me->i2c_port, me->i2c_addr_flags, TUSB544_REG_GENERAL6,
+		       &reg);
 	if (rv)
 		return rv;
 
@@ -280,52 +264,52 @@ static int board_tusb544_set(const struct usb_mux *me, mux_state_t mux_state)
 	reg &= ~TUSB544_VOD_DCGAIN_SEL;
 	reg |= (TUSB544_VOD_DCGAIN_SETTING_5 << 2);
 
-	rv = i2c_write8(me->i2c_port, me->i2c_addr_flags,
-			TUSB544_REG_GENERAL6, reg);
+	rv = i2c_write8(me->i2c_port, me->i2c_addr_flags, TUSB544_REG_GENERAL6,
+			reg);
 	if (rv)
 		return rv;
 
 	/* Write the retimer config byte */
 	if (usb_mode == USB_INV) {
 		rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_GENERAL4, 0x15);
+				 TUSB544_REG_GENERAL4, 0x15);
 		rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_USB3_1_1, 0xff);
+				 TUSB544_REG_USB3_1_1, 0xff);
 		rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_USB3_1_2, 0xff);
+				 TUSB544_REG_USB3_1_2, 0xff);
 	} else if (usb_mode == USB) {
 		rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_GENERAL4, 0x11);
+				 TUSB544_REG_GENERAL4, 0x11);
 		rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_USB3_1_1, 0xff);
+				 TUSB544_REG_USB3_1_1, 0xff);
 		rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_USB3_1_2, 0xff);
+				 TUSB544_REG_USB3_1_2, 0xff);
 	} else if (usb_mode == USB_DP_INV) {
 		rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_GENERAL4, 0x1F);
+				 TUSB544_REG_GENERAL4, 0x1F);
 		rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_USB3_1_1, 0xff);
+				 TUSB544_REG_USB3_1_1, 0xff);
 		rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_USB3_1_2, 0xff);
+				 TUSB544_REG_USB3_1_2, 0xff);
 	} else if (usb_mode == USB_DP) {
 		rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_GENERAL4, 0x1B);
+				 TUSB544_REG_GENERAL4, 0x1B);
 		rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_USB3_1_1, 0xff);
+				 TUSB544_REG_USB3_1_1, 0xff);
 		rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_USB3_1_2, 0xff);
+				 TUSB544_REG_USB3_1_2, 0xff);
 	} else if (usb_mode == DP_INV) {
 		rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_GENERAL4, 0x1E);
+				 TUSB544_REG_GENERAL4, 0x1E);
 	} else if (usb_mode == DP) {
 		rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_GENERAL4, 0x1A);
+				 TUSB544_REG_GENERAL4, 0x1A);
 	}
 
 	rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_DISPLAYPORT_1, 0x66);
+			 TUSB544_REG_DISPLAYPORT_1, 0x66);
 	rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags,
-				TUSB544_REG_DISPLAYPORT_2, 0x66);
+			 TUSB544_REG_DISPLAYPORT_2, 0x66);
 	if (rv)
 		return EC_ERROR_UNKNOWN;
 	else
@@ -333,28 +317,37 @@ static int board_tusb544_set(const struct usb_mux *me, mux_state_t mux_state)
 }
 
 /* USB Retimer */
-const struct usb_mux usbc1_retimer = {
-	.usb_port = 1,
-	.i2c_port = I2C_PORT_SUB_USB_C1,
-	.i2c_addr_flags = TUSB544_I2C_ADDR_FLAGS0,
-	.driver = &tusb544_drv,
-	.board_set = &board_tusb544_set,
+const struct usb_mux_chain usbc1_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = 1,
+			.i2c_port = I2C_PORT_SUB_USB_C1,
+			.i2c_addr_flags = TUSB544_I2C_ADDR_FLAGS0,
+			.driver = &tusb544_drv,
+			.board_set = &board_tusb544_set,
+		},
 };
 
 /* USB Muxes */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+			},
 	},
 	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.next_mux = &usbc1_retimer,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_SUB_USB_C1,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+			},
+		.next = &usbc1_retimer,
 	},
 };
 
@@ -461,8 +454,7 @@ int board_is_sourcing_vbus(int port)
 
 int board_set_active_charge_port(int port)
 {
-	int is_real_port = (port >= 0 &&
-			    port < board_get_usb_pd_port_count());
+	int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count());
 	int i;
 	int old_port;
 
@@ -526,9 +518,8 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
+__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+				       int *ki_div, int *kd, int *kd_div)
 {
 	*kp = 3;
 	*kp_div = 14;
@@ -553,17 +544,13 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrices to rotate accelerometers into the standard reference. */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					     { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					      { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
 
 static struct accelgyro_saved_data_t g_bma253_data;
 static struct bmi_drv_data_t g_bmi160_data;
@@ -639,11 +626,9 @@ struct motion_sensor_t motion_sensors[] = {
 
 unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
-static const mat33_fp_t lid_lis2dwl_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_lis2dwl_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					    { FLOAT_TO_FP(1), 0, 0 },
+					    { 0, 0, FLOAT_TO_FP(-1) } };
 
 /* Lid accel private data */
 static struct stprivate_data g_lis2dwl_data;
@@ -675,11 +660,9 @@ struct motion_sensor_t lis2dwl_lid_accel = {
 		},
 };
 
-static const mat33_fp_t lid_KX022_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_KX022_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					  { FLOAT_TO_FP(1), 0, 0 },
+					  { 0, 0, FLOAT_TO_FP(-1) } };
 
 static struct kionix_accel_data g_kx022_data;
 struct motion_sensor_t kx022_lid_accel = {
@@ -710,11 +693,9 @@ struct motion_sensor_t kx022_lid_accel = {
 };
 
 static struct icm_drv_data_t g_icm42607_data;
-const mat33_fp_t based_ref_icm42607 = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t based_ref_icm42607 = { { FLOAT_TO_FP(1), 0, 0 },
+					{ 0, FLOAT_TO_FP(1), 0 },
+					{ 0, 0, FLOAT_TO_FP(1) } };
 struct motion_sensor_t icm42607_base_accel = {
 	 .name = "Base Accel",
 	 .active_mask = SENSOR_ACTIVE_S0_S3,
@@ -743,29 +724,26 @@ struct motion_sensor_t icm42607_base_accel = {
 };
 
 struct motion_sensor_t icm42607_base_gyro = {
-	 .name = "Base Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_ICM42607,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &icm42607_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_icm42607_data,
-	 .port = I2C_PORT_ACCEL,
-	 .i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &based_ref_icm42607,
-	 .min_frequency = ICM42607_GYRO_MIN_FREQ,
-	 .max_frequency = ICM42607_GYRO_MAX_FREQ,
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM42607,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm42607_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm42607_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &based_ref_icm42607,
+	.min_frequency = ICM42607_GYRO_MIN_FREQ,
+	.max_frequency = ICM42607_GYRO_MAX_FREQ,
 };
 
-
 static struct bmi_drv_data_t g_bmi220_data;
-const mat33_fp_t based_ref_bmi220 = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t based_ref_bmi220 = { { 0, FLOAT_TO_FP(1), 0 },
+				      { FLOAT_TO_FP(-1), 0, 0 },
+				      { 0, 0, FLOAT_TO_FP(1) } };
 struct motion_sensor_t bmi220_base_accel = {
 	 .name = "Base Accel",
 	 .active_mask = SENSOR_ACTIVE_S0_S3,
@@ -794,20 +772,20 @@ struct motion_sensor_t bmi220_base_accel = {
 };
 
 struct motion_sensor_t bmi220_base_gyro = {
-	 .name = "Base Gyro",
-	 .active_mask = SENSOR_ACTIVE_S0_S3,
-	 .chip = MOTIONSENSE_CHIP_BMI220,
-	 .type = MOTIONSENSE_TYPE_GYRO,
-	 .location = MOTIONSENSE_LOC_BASE,
-	 .drv = &bmi260_drv,
-	 .mutex = &g_base_mutex,
-	 .drv_data = &g_bmi220_data,
-	 .port = I2C_PORT_ACCEL,
-	 .i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
-	 .default_range = 1000, /* dps */
-	 .rot_standard_ref = &based_ref_bmi220,
-	 .min_frequency = BMI_GYRO_MIN_FREQ,
-	 .max_frequency = BMI_GYRO_MAX_FREQ,
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_BMI220,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &bmi260_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_bmi220_data,
+	.port = I2C_PORT_ACCEL,
+	.i2c_spi_addr_flags = BMI260_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &based_ref_bmi220,
+	.min_frequency = BMI_GYRO_MIN_FREQ,
+	.max_frequency = BMI_GYRO_MAX_FREQ,
 };
 
 void board_init(void)
@@ -846,13 +824,13 @@ void board_init(void)
 	if (board_id > 2) {
 		if (get_cbi_fw_config_tablet_mode()) {
 			if (get_cbi_ssfc_base_sensor() ==
-						SSFC_SENSOR_ICM42607) {
+			    SSFC_SENSOR_ICM42607) {
 				motion_sensors[BASE_ACCEL] =
-						icm42607_base_accel;
+					icm42607_base_accel;
 				motion_sensors[BASE_GYRO] = icm42607_base_gyro;
 				CPRINTF("BASE GYRO is ICM42607");
 			} else if (get_cbi_ssfc_base_sensor() ==
-						SSFC_SENSOR_BMI220) {
+				   SSFC_SENSOR_BMI220) {
 				motion_sensors[BASE_ACCEL] = bmi220_base_accel;
 				motion_sensors[BASE_GYRO] = bmi220_base_gyro;
 				CPRINTF("BASE GYRO is BMI220");
@@ -864,7 +842,7 @@ void board_init(void)
 				motion_sensors[LID_ACCEL] = lis2dwl_lid_accel;
 				CPRINTF("LID_ACCEL is LIS2DWL");
 			} else if (get_cbi_ssfc_lid_sensor() ==
-						SSFC_SENSOR_KX022) {
+				   SSFC_SENSOR_KX022) {
 				motion_sensors[LID_ACCEL] = kx022_lid_accel;
 				CPRINTF("LID_ACCEL is KX022");
 			} else {
@@ -878,7 +856,7 @@ void board_init(void)
 			 * line to float.
 			 */
 			gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L,
-					GPIO_INPUT | GPIO_PULL_DOWN);
+				       GPIO_INPUT | GPIO_PULL_DOWN);
 		}
 	} else {
 		if (get_cbi_ssfc_base_sensor() == SSFC_SENSOR_ICM42607) {
@@ -908,34 +886,34 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
 void motion_interrupt(enum gpio_signal signal)
 {
-		switch (get_cbi_ssfc_base_sensor()) {
-		case SSFC_SENSOR_ICM42607:
-			icm42607_interrupt(signal);
-			break;
-		case SSFC_SENSOR_BMI220:
-			bmi260_interrupt(signal);
-			break;
-		case SSFC_SENSOR_BMI160:
-		default:
-			bmi160_interrupt(signal);
-			break;
-		}
+	switch (get_cbi_ssfc_base_sensor()) {
+	case SSFC_SENSOR_ICM42607:
+		icm42607_interrupt(signal);
+		break;
+	case SSFC_SENSOR_BMI220:
+		bmi260_interrupt(signal);
+		break;
+	case SSFC_SENSOR_BMI160:
+	default:
+		bmi160_interrupt(signal);
+		break;
+	}
 }
 
 /* Thermistors */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
-	[TEMP_SENSOR_3] = {.name = "Cpu",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_3},
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
+	[TEMP_SENSOR_3] = { .name = "Cpu",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_3 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
diff --git a/board/storo/board.h b/board/storo/board.h
index 4532d11b4e..93dd573ba1 100644
--- a/board/storo/board.h
+++ b/board/storo/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,11 +25,14 @@
 
 /* Charger */
 #define CONFIG_CHARGER_RAA489000
+#define PD_MAX_VOLTAGE_MV 20000
 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 #define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */
+#define CONFIG_OCPC_DEF_RBATT_MOHMS               \
+	22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \
+	    */
 #define CONFIG_OCPC
-#undef  CONFIG_CHARGER_SINGLE_CHIP
+#undef CONFIG_CHARGER_SINGLE_CHIP
 #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
 #define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
 
@@ -37,19 +40,19 @@
 
 /* LED */
 #define CONFIG_LED_ONOFF_STATES
-#define CONFIG_LED_ONOFF_STATES_BAT_LOW	10
+#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10
 
-#define I2C_PORT_ACCEL	I2C_PORT_SENSOR
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
 
 /* Sensors */
 #define CONFIG_CMD_ACCELS
 #define CONFIG_CMD_ACCEL_INFO
 #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
 
-#define CONFIG_ACCEL_BMA255		/* Lid accel */
+#define CONFIG_ACCEL_BMA255 /* Lid accel */
 #define CONFIG_ACCEL_LIS2DWL
 #define CONFIG_ACCEL_KX022
-#define CONFIG_ACCELGYRO_BMI160	/* Base accel */
+#define CONFIG_ACCELGYRO_BMI160 /* Base accel */
 #define CONFIG_ACCELGYRO_ICM42607
 #define CONFIG_ACCELGYRO_BMI220
 #define CONFIG_I2C_XFER_LARGE_TRANSFER
@@ -57,7 +60,7 @@
 /* Lid operates in forced mode, base in FIFO */
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
 #define CONFIG_ACCEL_FIFO
-#define CONFIG_ACCEL_FIFO_SIZE 256	/* Must be a power of 2 */
+#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */
 #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
 
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
@@ -95,12 +98,10 @@
 #define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
 
 /* USB Mux and Retimer */
-#define CONFIG_USB_MUX_IT5205			/* C1: ITE Mux */
-#define I2C_PORT_USB_MUX I2C_PORT_USB_C0	/* Required for ITE Mux */
-
-#define CONFIG_USBC_RETIMER_TUSB544		/* C1 Redriver: TUSB544 */
-
+#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */
 
+#define CONFIG_USBC_RETIMER_TUSB544 /* C1 Redriver: TUSB544 */
 
 #ifndef __ASSEMBLER__
 
@@ -113,22 +114,15 @@ enum chg_id {
 	CHARGER_NUM,
 };
 
-
-
 /* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
 /* ADC channels */
 enum adc_channel {
-	ADC_VSNS_PP3300_A,     /* ADC0 */
-	ADC_TEMP_SENSOR_1,     /* ADC2 */
-	ADC_TEMP_SENSOR_2,     /* ADC3 */
-	ADC_TEMP_SENSOR_3,     /* ADC15*/
+	ADC_VSNS_PP3300_A, /* ADC0 */
+	ADC_TEMP_SENSOR_1, /* ADC2 */
+	ADC_TEMP_SENSOR_2, /* ADC3 */
+	ADC_TEMP_SENSOR_3, /* ADC15*/
 	ADC_CH_COUNT
 };
 
diff --git a/board/storo/build.mk b/board/storo/build.mk
index 8167ca9966..01b890bf29 100644
--- a/board/storo/build.mk
+++ b/board/storo/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/storo/cbi_ssfc.c b/board/storo/cbi_ssfc.c
index c4b859f133..81f3ee0dad 100644
--- a/board/storo/cbi_ssfc.c
+++ b/board/storo/cbi_ssfc.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
 
 enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
 {
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
 }
 
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
 {
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
 }
diff --git a/board/storo/cbi_ssfc.h b/board/storo/cbi_ssfc.h
index f4a51b8e91..bc6bc92286 100644
--- a/board/storo/cbi_ssfc.h
+++ b/board/storo/cbi_ssfc.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -57,5 +57,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
  */
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
 
-
 #endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/storo/ec.tasklist b/board/storo/ec.tasklist
index d54ff847e6..8abd36b4be 100644
--- a/board/storo/ec.tasklist
+++ b/board/storo/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/storo/gpio.inc b/board/storo/gpio.inc
index b7541c5259..cb07474f52 100644
--- a/board/storo/gpio.inc
+++ b/board/storo/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/storo/led.c b/board/storo/led.c
index d5094f1f30..76bfc05861 100644
--- a/board/storo/led.c
+++ b/board/storo/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,28 +10,37 @@
 #include "led_common.h"
 #include "led_onoff_states.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
 __override const int led_charge_lvl_1 = 5;
 __override const int led_charge_lvl_2 = 95;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]       = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]       = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]	     = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_WHITE,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
 const enum ec_led_id supported_led_ids[] = {
 	EC_LED_ID_BATTERY_LED,
diff --git a/board/storo/usb_pd_policy.c b/board/storo/usb_pd_policy.c
index 15faf41ffc..83c09bb99e 100644
--- a/board/storo/usb_pd_policy.c
+++ b/board/storo/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,8 @@
 #include "driver/tcpm/tcpci.h"
 #include "usb_pd.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
diff --git a/board/stryke/battery.c b/board/stryke/battery.c
index 0144c049b5..7690cd420f 100644
--- a/board/stryke/battery.c
+++ b/board/stryke/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/stryke/board.c b/board/stryke/board.c
index 783f73a666..1d1bbbe949 100644
--- a/board/stryke/board.c
+++ b/board/stryke/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -41,8 +41,8 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* GPIO to enable/disable the USB Type-A port. */
 const int usb_port_enable[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT] = {
@@ -108,16 +108,16 @@ static void bc12_interrupt(enum gpio_signal signal)
 
 /******************************************************************************/
 /* SPI devices */
-const struct spi_device_t spi_devices[] = {
-};
+const struct spi_device_t spi_devices[] = {};
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
 /******************************************************************************/
 /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_KBLIGHT]   = { .channel = 3, .flags = 0, .freq = 10000 },
-	[PWM_CH_FAN] = {.channel = 5, .flags = PWM_CONFIG_OPEN_DRAIN,
-			.freq = 25000},
+	[PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 },
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
@@ -143,16 +143,20 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	[USB_PD_PORT_TCPC_0] = {
-		.usb_port = USB_PD_PORT_TCPC_0,
-		.driver = &anx7447_usb_mux_driver,
-		.hpd_update = &anx7447_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_0,
+			.driver = &anx7447_usb_mux_driver,
+			.hpd_update = &anx7447_tcpc_update_hpd_status,
+		},
 	},
 	[USB_PD_PORT_TCPC_1] = {
-		.usb_port = USB_PD_PORT_TCPC_1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USB_PD_PORT_TCPC_1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 	}
 };
 
@@ -181,22 +185,18 @@ static struct bmi_drv_data_t g_bmi160_data;
 static struct accelgyro_saved_data_t g_bma255_data;
 
 /* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					      { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
 
 /*
  * TODO(b/124337208): P0 boards don't have this sensor mounted so the rotation
  * matrix can't be tested properly. This needs to be revisited after EVT to make
  * sure the rotaiton matrix for the lid sensor is correct.
  */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+					     { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
@@ -277,7 +277,7 @@ unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
@@ -296,32 +296,31 @@ const struct fan_t fans[FAN_CH_COUNT] = {
 /******************************************************************************/
 /* MFT channels. These are logically separate from pwm_channels. */
 const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN},
+	[MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN },
 };
 BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_1] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_2] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_1] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_2] = { "TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT,
+				ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Temp1",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Temp2",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_30k9_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_2},
+	[TEMP_SENSOR_1] = { .name = "Temp1",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Temp2",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_30k9_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
-
 /* Stryke Temperature sensors */
 /*
  * TODO(b/124316213): These setting need to be reviewed and set appropriately
@@ -331,8 +330,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_A \
-	{ \
+#define THERMAL_A                \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = 0, \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
@@ -387,7 +386,6 @@ static void board_gpio_set_pp5000(void)
 	} else if (board_id >= 1) {
 		reset_gpio_flags(GPIO_EN_PP5000_A_V1, GPIO_OUT_LOW);
 	}
-
 }
 
 static void board_init(void)
diff --git a/board/stryke/board.h b/board/stryke/board.h
index 205c3bbd4a..165cdd53a8 100644
--- a/board/stryke/board.h
+++ b/board/stryke/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -100,16 +100,16 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_PCH_RSMRST_L	GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
-#define GPIO_CPU_PROCHOT	GPIO_EC_PROCHOT_ODL
-#define GPIO_AC_PRESENT		GPIO_ACOK_OD
-#define GPIO_PG_EC_RSMRST_ODL	GPIO_PG_EC_RSMRST_L
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_PCH_SYS_PWROK
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_TEMP_SENSOR_POWER	GPIO_EN_A_RAILS
-#define GPIO_EN_PP5000		GPIO_EN_PP5000_A
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L
+#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
 
 #ifndef __ASSEMBLER__
 
@@ -121,8 +121,8 @@
 extern enum gpio_signal gpio_en_pp5000_a;
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_1,	/* ADC0 */
-	ADC_TEMP_SENSOR_2,	/* ADC1 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
 	ADC_CH_COUNT
 };
 
@@ -133,11 +133,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_FAN,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_FAN, PWM_CH_COUNT };
 
 enum fan_channel {
 	FAN_CH_0 = 0,
@@ -151,11 +147,7 @@ enum mft_channel {
 	MFT_CH_COUNT,
 };
 
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_COUNT
-};
+enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
diff --git a/board/stryke/build.mk b/board/stryke/build.mk
index 733912454f..13153c1526 100644
--- a/board/stryke/build.mk
+++ b/board/stryke/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/stryke/ec.tasklist b/board/stryke/ec.tasklist
index 4a1024a091..829be2b7c8 100644
--- a/board/stryke/ec.tasklist
+++ b/board/stryke/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/stryke/gpio.inc b/board/stryke/gpio.inc
index 8b241b2850..f839d16f84 100644
--- a/board/stryke/gpio.inc
+++ b/board/stryke/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,10 +16,10 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 GPIO_INT(SLP_S4_L,             PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(PG_EC_RSMRST_L,       PIN(E, 2), GPIO_INT_BOTH, intel_x86_rsmrst_signal_interrupt)
diff --git a/board/stryke/led.c b/board/stryke/led.c
index 4e210f34e2..d49e29782c 100644
--- a/board/stryke/led.c
+++ b/board/stryke/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,22 +19,26 @@ __override const int led_charge_lvl_1 = 5;
 __override const int led_charge_lvl_2 = 95;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
diff --git a/board/sweetberry/board.c b/board/sweetberry/board.c
index bee8f91a22..0fdfcda7be 100644
--- a/board/sweetberry/board.c
+++ b/board/sweetberry/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -28,14 +28,14 @@
  * Define the strings used in our USB descriptors.
  */
 const void *const usb_strings[] = {
-	[USB_STR_DESC]		= usb_string_desc,
-	[USB_STR_VENDOR]	= USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]	= USB_STRING_DESC("Sweetberry"),
-	[USB_STR_SERIALNO]	= USB_STRING_DESC("1234-a"),
-	[USB_STR_VERSION]	= USB_STRING_DESC(CROS_EC_VERSION32),
-	[USB_STR_I2C_NAME]	= USB_STRING_DESC("I2C"),
-	[USB_STR_CONSOLE_NAME]	= USB_STRING_DESC("Sweetberry EC Shell"),
-	[USB_STR_UPDATE_NAME]	= USB_STRING_DESC("Firmware update"),
+	[USB_STR_DESC] = usb_string_desc,
+	[USB_STR_VENDOR] = USB_STRING_DESC("Google LLC"),
+	[USB_STR_PRODUCT] = USB_STRING_DESC("Sweetberry"),
+	[USB_STR_SERIALNO] = USB_STRING_DESC("1234-a"),
+	[USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32),
+	[USB_STR_I2C_NAME] = USB_STRING_DESC("I2C"),
+	[USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Sweetberry EC Shell"),
+	[USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"),
 };
 
 BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
@@ -59,48 +59,43 @@ struct dwc_usb usb_ctl = {
 
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "i2c1",
-		.port = I2C_PORT_0,
-		.kbps = 400,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	},
-	{
-		.name = "i2c2",
-		.port = I2C_PORT_1,
-		.kbps = 400,
-		.scl  = GPIO_I2C2_SCL,
-		.sda  = GPIO_I2C2_SDA
-	},
-	{
-		.name = "i2c3",
-		.port = I2C_PORT_2,
-		.kbps = 400,
-		.scl  = GPIO_I2C3_SCL,
-		.sda  = GPIO_I2C3_SDA
-	},
-	{
-		.name = "fmpi2c4",
-		.port = FMPI2C_PORT_3,
-		.kbps = 900,
-		.scl  = GPIO_FMPI2C_SCL,
-		.sda  = GPIO_FMPI2C_SDA
-	},
+	{ .name = "i2c1",
+	  .port = I2C_PORT_0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "i2c2",
+	  .port = I2C_PORT_1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "i2c3",
+	  .port = I2C_PORT_2,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
+	{ .name = "fmpi2c4",
+	  .port = FMPI2C_PORT_3,
+	  .kbps = 900,
+	  .scl = GPIO_FMPI2C_SCL,
+	  .sda = GPIO_FMPI2C_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
-int usb_i2c_board_is_enabled(void) { return 1; }
+int usb_i2c_board_is_enabled(void)
+{
+	return 1;
+}
 
-#define GPIO_SET_HS(bank, number)	\
-	(STM32_GPIO_OSPEEDR(GPIO_##bank) |= (0x3 << ((number) * 2)))
+#define GPIO_SET_HS(bank, number) \
+	(STM32_GPIO_OSPEEDR(GPIO_##bank) |= (0x3 << ((number)*2)))
 
 void board_config_post_gpio_init(void)
 {
 	/* We use MCO2 clock passthrough to provide a clock to USB HS */
 	gpio_config_module(MODULE_MCO, 1);
 	/* GPIO PC9 to high speed */
-	GPIO_SET_HS(C,  9);
+	GPIO_SET_HS(C, 9);
 
 	if (usb_ctl.phy_type == USB_PHY_ULPI)
 		gpio_set_level(GPIO_USB_MUX_SEL, 0);
@@ -111,29 +106,29 @@ void board_config_post_gpio_init(void)
 	GPIO_SET_HS(A, 11);
 	GPIO_SET_HS(A, 12);
 
-	GPIO_SET_HS(C,  3);
-	GPIO_SET_HS(C,  2);
-	GPIO_SET_HS(C,  0);
-	GPIO_SET_HS(A,  5);
+	GPIO_SET_HS(C, 3);
+	GPIO_SET_HS(C, 2);
+	GPIO_SET_HS(C, 0);
+	GPIO_SET_HS(A, 5);
 
-	GPIO_SET_HS(B,  5);
+	GPIO_SET_HS(B, 5);
 	GPIO_SET_HS(B, 13);
 	GPIO_SET_HS(B, 12);
-	GPIO_SET_HS(B,  2);
+	GPIO_SET_HS(B, 2);
 	GPIO_SET_HS(B, 10);
-	GPIO_SET_HS(B,  1);
-	GPIO_SET_HS(B,  0);
-	GPIO_SET_HS(A,  3);
+	GPIO_SET_HS(B, 1);
+	GPIO_SET_HS(B, 0);
+	GPIO_SET_HS(A, 3);
 
 	/* Set I2C GPIO to HS */
-	GPIO_SET_HS(B,  6);
-	GPIO_SET_HS(B,  7);
-	GPIO_SET_HS(F,  1);
-	GPIO_SET_HS(F,  0);
-	GPIO_SET_HS(A,  8);
-	GPIO_SET_HS(B,  4);
-	GPIO_SET_HS(C,  6);
-	GPIO_SET_HS(C,  7);
+	GPIO_SET_HS(B, 6);
+	GPIO_SET_HS(B, 7);
+	GPIO_SET_HS(F, 1);
+	GPIO_SET_HS(F, 0);
+	GPIO_SET_HS(A, 8);
+	GPIO_SET_HS(B, 4);
+	GPIO_SET_HS(C, 6);
+	GPIO_SET_HS(C, 7);
 }
 
 static void board_init(void)
diff --git a/board/sweetberry/board.h b/board/sweetberry/board.h
index 55aab7d1ee..4387cd4094 100644
--- a/board/sweetberry/board.h
+++ b/board/sweetberry/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -48,28 +48,28 @@
 #define DEFAULT_SERIALNO "Uninitialized"
 
 /* USB interface indexes (use define rather than enum to expand them) */
-#define USB_IFACE_CONSOLE	0
-#define USB_IFACE_UPDATE	1
-#define USB_IFACE_POWER		2
-#define USB_IFACE_I2C		3
-#define USB_IFACE_COUNT		4
+#define USB_IFACE_CONSOLE 0
+#define USB_IFACE_UPDATE 1
+#define USB_IFACE_POWER 2
+#define USB_IFACE_I2C 3
+#define USB_IFACE_COUNT 4
 
 /* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL		0
-#define USB_EP_CONSOLE		1
-#define USB_EP_UPDATE		2
-#define USB_EP_POWER		3
-#define USB_EP_I2C		4
-#define USB_EP_COUNT		5
+#define USB_EP_CONTROL 0
+#define USB_EP_CONSOLE 1
+#define USB_EP_UPDATE 2
+#define USB_EP_POWER 3
+#define USB_EP_I2C 4
+#define USB_EP_COUNT 5
 
 #define CONFIG_USB_I2C
 #define CONFIG_I2C
 #define CONFIG_I2C_CONTROLLER
-#define I2C_PORT_0	0
-#define I2C_PORT_1	1
-#define I2C_PORT_2	2
-#define FMPI2C_PORT_3	3
-#define I2C_PORT_COUNT	4
+#define I2C_PORT_0 0
+#define I2C_PORT_1 1
+#define I2C_PORT_2 2
+#define FMPI2C_PORT_3 3
+#define I2C_PORT_COUNT 4
 
 /* This is not actually a Chromium EC so disable some features. */
 #undef CONFIG_WATCHDOG_HELP
diff --git a/board/sweetberry/build.mk b/board/sweetberry/build.mk
index 6b06f2bb8f..61e4b79d47 100644
--- a/board/sweetberry/build.mk
+++ b/board/sweetberry/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/sweetberry/ec.tasklist b/board/sweetberry/ec.tasklist
index c1fb169118..c45a1e89a7 100644
--- a/board/sweetberry/ec.tasklist
+++ b/board/sweetberry/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/sweetberry/gpio.inc b/board/sweetberry/gpio.inc
index cfab7fc1f3..28b91d0dec 100644
--- a/board/sweetberry/gpio.inc
+++ b/board/sweetberry/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/taeko/battery.c b/board/taeko/battery.c
index 0fd9c9fab2..24ce4c1bdf 100644
--- a/board/taeko/battery.c
+++ b/board/taeko/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -151,7 +151,9 @@ __override bool board_battery_is_initialized(void)
 	bool batt_initialization_state;
 	int batt_status;
 
-	batt_initialization_state = (battery_status(&batt_status) ? false :
-		!!(batt_status & STATUS_INITIALIZED));
+	batt_initialization_state =
+		(battery_status(&batt_status) ?
+			 false :
+			 !!(batt_status & STATUS_INITIALIZED));
 	return batt_initialization_state;
 }
diff --git a/board/taeko/board.c b/board/taeko/board.c
index f4f29e1199..79ef4029d6 100644
--- a/board/taeko/board.c
+++ b/board/taeko/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -35,8 +35,8 @@
 #include "gpio_list.h" /* Must come after other header files. */
 
 /* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 /******************************************************************************/
 /* USB-A charging control */
@@ -121,8 +121,8 @@ int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
 	}
 
 	if (voltage < BC12_MIN_VOLTAGE) {
-		CPRINTS("%s: port %d: vbus %d lower than %d", __func__,
-			port, voltage, BC12_MIN_VOLTAGE);
+		CPRINTS("%s: port %d: vbus %d lower than %d", __func__, port,
+			voltage, BC12_MIN_VOLTAGE);
 		return 1;
 	}
 
@@ -138,7 +138,7 @@ enum battery_present battery_hw_present(void)
 }
 
 __override void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+				       int max_ma, int charge_mv)
 {
 	/*
 	 * Follow OEM request to limit the input current to
@@ -146,7 +146,6 @@ __override void board_set_charge_limit(int port, int supplier, int charge_ma,
 	 */
 	charge_ma = charge_ma * 95 / 100;
 
-	charge_set_input_current_limit(MAX(charge_ma,
-					CONFIG_CHARGER_INPUT_CURRENT),
-					charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
diff --git a/board/taeko/board.h b/board/taeko/board.h
index a6395ffc61..c3193c8847 100644
--- a/board/taeko/board.h
+++ b/board/taeko/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -30,18 +30,17 @@
 #define CONFIG_LED_ONOFF_STATES
 
 /* Sensors */
-#define	CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
+#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
 
 /* Button */
 #define CONFIG_BUTTONS_RUNTIME_CONFIG
 
-
 /* Change Request (b/199529373)
  * GYRO sensor change from ST LSM6DSOETR3TR to ST LSM6DS3TR-C
  *	LSM6DSOETR3TR base accel/gyro if board id = 0
  *	LSM6DS3TR-C Base accel/gyro if board id > 0
  */
-#define CONFIG_ACCELGYRO_LSM6DSO	/* Base accel */
+#define CONFIG_ACCELGYRO_LSM6DSO /* Base accel */
 #define CONFIG_ACCEL_LSM6DSO_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 #define CONFIG_ACCELGYRO_LSM6DSM
@@ -56,14 +55,13 @@
 #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
 
 /* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
-	(BIT(LID_ACCEL))
+#define CONFIG_ACCEL_FORCE_MODE_MASK (BIT(LID_ACCEL))
 
 /* Lid accel */
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE	BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID	LID_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
 #define CONFIG_ACCEL_BMA4XX
 #define CONFIG_ACCEL_LIS2DWL
 
@@ -72,7 +70,7 @@
 #define CONFIG_CMD_ACCEL_INFO
 
 /* USB Type A Features */
-#define USB_PORT_COUNT			1
+#define USB_PORT_COUNT 1
 #define CONFIG_USB_PORT_POWER_DUMB
 
 /* USB Type C and USB PD defines */
@@ -80,7 +78,7 @@
 
 #define CONFIG_IO_EXPANDER
 #define CONFIG_IO_EXPANDER_NCT38XX
-#define CONFIG_IO_EXPANDER_PORT_COUNT		1
+#define CONFIG_IO_EXPANDER_PORT_COUNT 1
 
 #define CONFIG_USB_PD_FRS_PPC
 #define CONFIG_USB_PD_FRS
@@ -88,6 +86,7 @@
 #define CONFIG_USB_PD_TCPM_PS8815_FORCE_DID
 #define CONFIG_USBC_PPC_SYV682X
 #define CONFIG_USBC_PPC_NX20P3483
+#define CONFIG_USBC_NX20P348X_RCP_5VSRC_MASK_ENABLE
 
 /* I2C speed console command */
 #define CONFIG_CMD_I2C_SPEED
@@ -96,76 +95,77 @@
 #define CONFIG_HOSTCMD_I2C_CONTROL
 
 /* TODO: b/177608416 - measure and check these values on brya */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
 
 /*
  * Passive USB-C cables only support up to 60W.
  */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		45000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 45000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* The lower the input voltage, the higher the power efficiency. */
 #define PD_PREFER_LOW_VOLTAGE
 
+#undef CONFIG_CMD_POWERINDEBUG
+
 /*
  * Macros for GPIO signals used in common code that don't match the
  * schematic names. Signal names in gpio.inc match the schematic and are
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT		GPIO_EC_EN_EDP_BL
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_GSC_PACKET_MODE
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SYS_SLP_S0IX_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_TEMP_SENSOR_POWER	GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
 
 /*
  * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
  * signal.
  */
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_SEQ_EC_ALL_SYS_PG
-#define GPIO_PG_EC_DSW_PWROK		GPIO_SEQ_EC_DSW_PWROK
-#define GPIO_PG_EC_RSMRST_ODL		GPIO_SEQ_EC_RSMRST_ODL
-#define GPIO_POWER_BUTTON_L		GPIO_GSC_EC_PWR_BTN_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_ODL
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
 
 /* System has back-lit keyboard */
 #define CONFIG_PWM_KBLIGHT
 
-
 /* I2C Bus Configuration */
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0_TCPC	NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1_TCPC	NPCX_I2C_PORT4_1
-#define I2C_PORT_USB_C0_PPC	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_PPC	NPCX_I2C_PORT6_1
-#define I2C_PORT_USB_C0_BC12	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_BC12	NPCX_I2C_PORT6_1
-#define I2C_PORT_USB_C1_MUX	NPCX_I2C_PORT6_1
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT5_0
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT7_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-#define I2C_PORT_MP2964		NPCX_I2C_PORT7_0
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-
-#define I2C_ADDR_MP2964_FLAGS	0x20
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0_TCPC NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1
+#define I2C_PORT_USB_C0_PPC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C0_BC12 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+
+#define I2C_ADDR_MP2964_FLAGS 0x20
 
 /* Thermal features */
 #define CONFIG_THERMISTOR
@@ -174,16 +174,16 @@
 #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
 
 /* Fan */
-#define CONFIG_FANS			FAN_CH_COUNT
+#define CONFIG_FANS FAN_CH_COUNT
 
 /* Charger defines */
 #define CONFIG_CHARGER_BQ25720
 #define CONFIG_CHARGER_BQ25720_VSYS_TH2_CUSTOM
 /* 37h BIT7:2 VSYS_TH2 6.0V */
-#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV	60
+#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV 60
 #define CONFIG_CHARGE_RAMP_SW
-#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10
 /* 30h BIT13:12 Enable PSYS 00b */
 #define CONFIG_CHARGER_BQ25710_PSYS_SENSING
 /* 31h BIT3 = 1 Enable ACOC */
@@ -200,15 +200,14 @@
 #define CONFIG_CHARGER_BQ25710_PP_COMP
 /* 36h UVP 5600mV */
 #define CONFIG_CHARGER_BQ25720_VSYS_UVP_CUSTOM
-#define CONFIG_CHARGER_BQ25720_VSYS_UVP \
-	BQ25720_CHARGE_OPTION_4_VSYS_UVP__5P6
+#define CONFIG_CHARGER_BQ25720_VSYS_UVP BQ25720_CHARGE_OPTION_4_VSYS_UVP__5P6
 /* 3Eh BIT15:8 VSYS_MIN 6.1V */
 #define CONFIG_CHARGER_BQ25710_VSYS_MIN_VOLTAGE_CUSTOM
 #define CONFIG_CHARGER_BQ25710_VSYS_MIN_VOLTAGE_MV 6100
 
 #ifndef __ASSEMBLER__
 
-#include "gpio_signal.h"	/* needed by registers.h */
+#include "gpio_signal.h" /* needed by registers.h */
 #include "registers.h"
 #include "usbc_config.h"
 
@@ -228,17 +227,9 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL = 0, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
-enum ioex_port {
-	IOEX_C0_NCT38XX = 0,
-	IOEX_PORT_COUNT
-};
+enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_PORT_COUNT };
 
 enum battery_type {
 	BATTERY_SMP_51W,
@@ -249,20 +240,14 @@ enum battery_type {
 };
 
 enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,		/* PWM3 */
-	PWM_CH_FAN,			/* PWM5 */
+	PWM_CH_KBLIGHT = 0, /* PWM3 */
+	PWM_CH_FAN, /* PWM5 */
 	PWM_CH_COUNT
 };
 
-enum fan_channel {
-	FAN_CH_0 = 0,
-	FAN_CH_COUNT
-};
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT };
 
-enum mft_channel {
-	MFT_CH_0 = 0,
-	MFT_CH_COUNT
-};
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT };
 
 void motion_interrupt(enum gpio_signal signal);
 
diff --git a/board/taeko/build.mk b/board/taeko/build.mk
index 442d30718f..9d193faf4e 100644
--- a/board/taeko/build.mk
+++ b/board/taeko/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/taeko/charger.c b/board/taeko/charger.c
index 476ce97df2..a4fa209246 120000..100644
--- a/board/taeko/charger.c
+++ b/board/taeko/charger.c
@@ -1 +1,90 @@
-../../baseboard/brya/charger_bq25720.c
\ No newline at end of file
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+
+#include "charge_manager.h"
+#include "charge_state_v2.h"
+#include "charger.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/charger/bq25710.h"
+#include "usbc_ppc.h"
+#include "usb_pd.h"
+#include "util.h"
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+#ifndef CONFIG_ZEPHYR
+/* Charger Chip Configuration */
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = BQ25710_SMBUS_ADDR1_FLAGS,
+		.drv = &bq25710_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CHARGER_NUM);
+#endif
+
+int board_set_active_charge_port(int port)
+{
+	int is_valid_port = board_is_usb_pd_port_present(port);
+	int i;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTSUSB("Disabling all charger ports");
+
+		/* Disable all ports. */
+		for (i = 0; i < ppc_cnt; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (ppc_vbus_sink_enable(i, 0))
+				CPRINTSUSB("Disabling C%d as sink failed.", i);
+		}
+
+		return EC_SUCCESS;
+	} else if (!is_valid_port) {
+		return EC_ERROR_INVAL;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (ppc_is_sourcing_vbus(port)) {
+		CPRINTFUSB("Skip enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTSUSB("New charge port: C%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < ppc_cnt; i++) {
+		if (i == port)
+			continue;
+
+		if (ppc_vbus_sink_enable(i, 0))
+			CPRINTSUSB("C%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTSUSB("C%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+__overridable void board_set_charge_limit(int port, int supplier, int charge_ma,
+					  int max_ma, int charge_mv)
+{
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+}
diff --git a/board/taeko/ec.tasklist b/board/taeko/ec.tasklist
index 6d995d6b44..29fd0bf4cb 100644
--- a/board/taeko/ec.tasklist
+++ b/board/taeko/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/taeko/fans.c b/board/taeko/fans.c
index e6273ec210..de3a49d45d 100644
--- a/board/taeko/fans.c
+++ b/board/taeko/fans.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,7 +25,7 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 static const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
diff --git a/board/taeko/fw_config.c b/board/taeko/fw_config.c
index 02480a6205..e04386051d 100644
--- a/board/taeko/fw_config.c
+++ b/board/taeko/fw_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,7 +10,7 @@
 #include "fw_config.h"
 #include "gpio.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 static union taeko_cbi_fw_config fw_config;
 BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
diff --git a/board/taeko/fw_config.h b/board/taeko/fw_config.h
index 4062946868..5217a72d0a 100644
--- a/board/taeko/fw_config.h
+++ b/board/taeko/fw_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,20 +14,14 @@
  * Source of truth is the project/taeko/taeko/config.star configuration file.
  */
 
-enum ec_cfg_usb_db_type {
-	DB_USB_ABSENT = 0,
-	DB_USB3_PS8815 = 1
-};
+enum ec_cfg_usb_db_type { DB_USB_ABSENT = 0, DB_USB3_PS8815 = 1 };
 
 enum ec_cfg_keyboard_backlight_type {
 	KEYBOARD_BACKLIGHT_DISABLED = 0,
 	KEYBOARD_BACKLIGHT_ENABLED = 1
 };
 
-enum ec_cfg_tabletmode_type {
-	TABLETMODE_DISABLED = 0,
-	TABLETMODE_ENABLED = 1
-};
+enum ec_cfg_tabletmode_type { TABLETMODE_DISABLED = 0, TABLETMODE_ENABLED = 1 };
 
 enum ec_cfg_kbnumpad {
 	KEYBOARD_NUMBER_PAD_ABSENT = 0,
@@ -46,11 +40,11 @@ enum ec_cfg_emmc_status {
 
 union taeko_cbi_fw_config {
 	struct {
-		enum ec_cfg_usb_db_type			usb_db : 2;
-		uint32_t				sd_db : 2;
-		enum ec_cfg_keyboard_backlight_type	kb_bl : 1;
-		uint32_t				audio : 3;
-		uint32_t				reserved_1 : 4;
+		enum ec_cfg_usb_db_type usb_db : 2;
+		uint32_t sd_db : 2;
+		enum ec_cfg_keyboard_backlight_type kb_bl : 1;
+		uint32_t audio : 3;
+		uint32_t reserved_1 : 4;
 		/* b/194515356 - Fw config structure
 		 * b/203630618 - Move tablet mode to bit14
 		 * bit8-9: kb_layout
@@ -58,11 +52,11 @@ union taeko_cbi_fw_config {
 		 * bit12: nvme
 		 * bit13: emmc
 		 */
-		enum ec_cfg_nvme_status			nvme_status : 1;
-		enum ec_cfg_emmc_status			emmc_status : 1;
-		enum ec_cfg_tabletmode_type		tabletmode : 1;
-		enum ec_cfg_kbnumpad                    kbnumpad : 1;
-		uint32_t				reserved_2 : 16;
+		enum ec_cfg_nvme_status nvme_status : 1;
+		enum ec_cfg_emmc_status emmc_status : 1;
+		enum ec_cfg_tabletmode_type tabletmode : 1;
+		enum ec_cfg_kbnumpad kbnumpad : 1;
+		uint32_t reserved_2 : 16;
 	};
 	uint32_t raw_value;
 };
diff --git a/board/taeko/gpio.inc b/board/taeko/gpio.inc
index 216ecfe99d..44cb489257 100644
--- a/board/taeko/gpio.inc
+++ b/board/taeko/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/taeko/i2c.c b/board/taeko/i2c.c
index 2c990254fa..79eddd663d 100644
--- a/board/taeko/i2c.c
+++ b/board/taeko/i2c.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/taeko/keyboard.c b/board/taeko/keyboard.c
index 5ad9a6cdf3..943f9f2635 100644
--- a/board/taeko/keyboard.c
+++ b/board/taeko/keyboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -43,7 +43,7 @@ static const struct ec_response_keybd_config taeko_kb = {
 };
 
 static const struct ec_response_keybd_config tarlo_kb = {
-	.num_top_row_keys = 14,
+	.num_top_row_keys = 11,
 	.action_keys = {
 		TK_BACK,		/* T1 */
 		TK_REFRESH,		/* T2 */
@@ -52,22 +52,58 @@ static const struct ec_response_keybd_config tarlo_kb = {
 		TK_SNAPSHOT,		/* T5 */
 		TK_BRIGHTNESS_DOWN,	/* T6 */
 		TK_BRIGHTNESS_UP,	/* T7 */
-		TK_ABSENT,              /* T8 */
-		TK_ABSENT,              /* T9 */
-		TK_ABSENT,              /* T10 */
-		TK_MICMUTE,             /* T11 */
-		TK_VOL_MUTE,		/* T12 */
-		TK_VOL_DOWN,		/* T13 */
-		TK_VOL_UP,		/* T14 */
+		TK_MICMUTE,             /* T8 */
+		TK_VOL_MUTE,		/* T9 */
+		TK_VOL_DOWN,		/* T10 */
+		TK_VOL_UP,		/* T11 */
 	},
 	.capabilities = KEYBD_CAP_SCRNLOCK_KEY | KEYBD_CAP_NUMERIC_KEYPAD,
 };
 
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
+/*
+ * Row Column info for Top row keys T1 - T15.
+ * Since tarlo keyboard top row keys have some issue when press with search
+ * key together.
+ * Needs to add row and col setting for top row.
+ * Change T8 row, col to (0,1)
+ * Change T9 row, col to (1,5)
+ * Change T10 row, col to (3,5)
+ * Change T11 row, col to (0,9)
+ */
+__override struct key {
+	uint8_t row;
+	uint8_t col;
+} vivaldi_keys[] = {
+	{ .row = 0, .col = 2 }, /* T1 */
+	{ .row = 3, .col = 2 }, /* T2 */
+	{ .row = 2, .col = 2 }, /* T3 */
+	{ .row = 1, .col = 2 }, /* T4 */
+	{ .row = 3, .col = 4 }, /* T5 */
+	{ .row = 2, .col = 4 }, /* T6 */
+	{ .row = 1, .col = 4 }, /* T7 */
+	{ .row = 0, .col = 1 }, /* T8 */
+	{ .row = 1, .col = 5 }, /* T9 */
+	{ .row = 3, .col = 5 }, /* T10 */
+	{ .row = 0, .col = 9 }, /* T11 */
+	{ .row = 2, .col = 9 }, /* T12 */
+	{ .row = 1, .col = 9 }, /* T13 */
+	{ .row = 0, .col = 4 }, /* T14 */
+	{ .row = 0, .col = 11 }, /* T15 */
+};
+BUILD_ASSERT(ARRAY_SIZE(vivaldi_keys) == MAX_TOP_ROW_KEYS);
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	if (ec_cfg_has_keyboard_number_pad())
 		return &tarlo_kb;
-	else
+	else {
+		vivaldi_keys[7].row = 2; /* T8 */
+		vivaldi_keys[7].col = 9;
+		vivaldi_keys[8].row = 1; /* T9 */
+		vivaldi_keys[8].col = 9;
+		vivaldi_keys[9].row = 0; /* T10 */
+		vivaldi_keys[9].col = 4;
 		return &taeko_kb;
+	}
 }
diff --git a/board/taeko/led.c b/board/taeko/led.c
index 35d4fe4146..7a58e486b0 100644
--- a/board/taeko/led.c
+++ b/board/taeko/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,44 +14,49 @@
 #include "led_common.h"
 #include "gpio.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
 __override const int led_charge_lvl_1 = 5;
 
 __override const int led_charge_lvl_2 = 97;
 
 __override struct led_descriptor
-		led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,   1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
 
 __override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]            = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]    = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					 {LED_OFF,         3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					 {LED_OFF,         3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF,            LED_INDEFINITE} },
-};
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    1 * LED_ONE_SEC },
+						  { LED_OFF,
+						    3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
diff --git a/board/taeko/pwm.c b/board/taeko/pwm.c
index b5fef384f9..899cf1db15 100644
--- a/board/taeko/pwm.c
+++ b/board/taeko/pwm.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -32,7 +32,6 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 
 static void board_pwm_init(void)
 {
-
 	pwm_enable(PWM_CH_KBLIGHT, 1);
 	pwm_set_duty(PWM_CH_KBLIGHT, 50);
 }
diff --git a/board/taeko/sensors.c b/board/taeko/sensors.c
index 22a349d95f..f695862fa8 100644
--- a/board/taeko/sensors.c
+++ b/board/taeko/sensors.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,8 +22,8 @@
 #include "tablet_mode.h"
 
 #if 0
-#define CPRINTS(format, args...) ccprints(format, ## args)
-#define CPRINTF(format, args...) ccprintf(format, ## args)
+#define CPRINTS(format, args...) ccprints(format, ##args)
+#define CPRINTF(format, args...) ccprintf(format, ##args)
 #else
 #define CPRINTS(format, args...)
 #define CPRINTF(format, args...)
@@ -70,23 +70,17 @@ static struct lsm6dso_data lsm6dso_data;
 static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
 
 /* The matrix for new DB */
-static const mat33_fp_t lid_ref_for_new_DB = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_ref_for_new_DB = { { FLOAT_TO_FP(-1), 0, 0 },
+					       { 0, FLOAT_TO_FP(1), 0 },
+					       { 0, 0, FLOAT_TO_FP(-1) } };
 /* Matrix to rotate lid and base sensor into standard reference frame */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					     { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
 
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, FLOAT_TO_FP(1), 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
 
 struct motion_sensor_t bma422_lid_accel = {
 	.name = "Lid Accel - BMA",
@@ -243,7 +237,6 @@ unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 #endif
 
-
 static void board_detect_motionsensor(void)
 {
 	int ret;
@@ -260,8 +253,8 @@ static void board_detect_motionsensor(void)
 		return;
 
 	/* Check lid accel chip */
-	ret = i2c_read8(I2C_PORT_SENSOR, LIS2DW12_ADDR1,
-			LIS2DW12_WHO_AM_I_REG, &val);
+	ret = i2c_read8(I2C_PORT_SENSOR, LIS2DW12_ADDR1, LIS2DW12_WHO_AM_I_REG,
+			&val);
 	if (ret == 0 && val == LIS2DW12_WHO_AM_I) {
 		CPRINTS("LID_ACCEL is LIS2DW12");
 		return;
@@ -281,8 +274,7 @@ static void board_detect_motionsensor(void)
 		 */
 		if (get_board_id() >= 2) {
 			/* Need to change matrix when board ID >= 2 */
-			bma422_lid_accel.rot_standard_ref =
-					&lid_ref_for_new_DB;
+			bma422_lid_accel.rot_standard_ref = &lid_ref_for_new_DB;
 		}
 		return;
 	}
@@ -293,7 +285,7 @@ static void board_detect_motionsensor(void)
 	CPRINTS("No LID_ACCEL are detected");
 }
 DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_detect_motionsensor,
-		HOOK_PRIO_DEFAULT);
+	     HOOK_PRIO_DEFAULT);
 
 static void baseboard_sensors_init(void)
 {
@@ -316,7 +308,7 @@ static void baseboard_sensors_init(void)
 		if (get_board_id() >= 2) {
 			/* Need to change matrix when board ID >= 2 */
 			motion_sensors[LID_ACCEL].rot_standard_ref =
-							&lid_ref_for_new_DB;
+				&lid_ref_for_new_DB;
 		}
 
 		/* Enable gpio interrupt for base accelgyro sensor */
@@ -327,41 +319,32 @@ static void baseboard_sensors_init(void)
 		gmr_tablet_switch_disable();
 		gpio_set_flags(GPIO_TABLET_MODE_L, GPIO_INPUT | GPIO_PULL_DOWN);
 		/* Gyro is not present, don't allow line to float */
-		gpio_set_flags(GPIO_EC_IMU_INT_R_L, GPIO_INPUT |
-				GPIO_PULL_DOWN);
+		gpio_set_flags(GPIO_EC_IMU_INT_R_L,
+			       GPIO_INPUT | GPIO_PULL_DOWN);
 	}
 }
 DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_INIT_I2C + 1);
 
 /* Temperature sensor configuration */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1_DDR_SOC] = {
-		.name = "DDR and SOC",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_1_DDR_SOC
-	},
-	[TEMP_SENSOR_2_FAN] = {
-		.name = "FAN",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_2_FAN
-	},
-	[TEMP_SENSOR_3_CHARGER] = {
-		.name = "CHARGER",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_3_CHARGER
-	},
-	[TEMP_SENSOR_4_CPUCHOKE] = {
-		.name = "CPU CHOKE",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_4_CPUCHOKE
-	},
+	[TEMP_SENSOR_1_DDR_SOC] = { .name = "DDR and SOC",
+				    .type = TEMP_SENSOR_TYPE_BOARD,
+				    .read = get_temp_3v3_30k9_47k_4050b,
+				    .idx = ADC_TEMP_SENSOR_1_DDR_SOC },
+	[TEMP_SENSOR_2_FAN] = { .name = "FAN",
+				.type = TEMP_SENSOR_TYPE_BOARD,
+				.read = get_temp_3v3_30k9_47k_4050b,
+				.idx = ADC_TEMP_SENSOR_2_FAN },
+	[TEMP_SENSOR_3_CHARGER] = { .name = "CHARGER",
+				    .type = TEMP_SENSOR_TYPE_BOARD,
+				    .read = get_temp_3v3_30k9_47k_4050b,
+				    .idx = ADC_TEMP_SENSOR_3_CHARGER },
+	[TEMP_SENSOR_4_CPUCHOKE] = { .name = "CPU CHOKE",
+				     .type = TEMP_SENSOR_TYPE_BOARD,
+				     .read = get_temp_3v3_30k9_47k_4050b,
+				     .idx = ADC_TEMP_SENSOR_4_CPUCHOKE },
 };
 
-
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
 /*
@@ -374,8 +357,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CPU \
-	{ \
+#define THERMAL_CPU              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(90), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(100), \
@@ -384,7 +367,7 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(85), \
 		}, \
 		.temp_fan_off = C_TO_K(35), \
-		.temp_fan_max = C_TO_K(60), \
+		.temp_fan_max = C_TO_K(70), \
 	}
 __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 
@@ -404,8 +387,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_FAN \
-	{ \
+#define THERMAL_FAN              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(90), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(100), \
@@ -414,7 +397,7 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(85), \
 		}, \
 		.temp_fan_off = C_TO_K(35), \
-		.temp_fan_max = C_TO_K(60), \
+		.temp_fan_max = C_TO_K(70), \
 	}
 __maybe_unused static const struct ec_thermal_config thermal_fan = THERMAL_FAN;
 
diff --git a/board/taeko/usbc_config.c b/board/taeko/usbc_config.c
index 0a1b7ff194..71a495c402 100644
--- a/board/taeko/usbc_config.c
+++ b/board/taeko/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -34,13 +34,13 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 #if 0
 /* Debug only! */
-#define CPRINTSUSB(format, args...) cprints(CC_USBPD, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBPD, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBPD, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBPD, format, ##args)
 #else
 #define CPRINTSUSB(format, args...)
 #define CPRINTFUSB(format, args...)
@@ -99,24 +99,31 @@ unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
  * to the virtual_usb_mux_driver so the AP gets notified of mux changes
  * and updates the TCSS configuration on state changes.
  */
-static const struct usb_mux usbc1_usb3_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+static const struct usb_mux_chain usbc1_usb3_db_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 };
 
-const struct usb_mux usb_muxes[] = {
+const struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 	},
 	[USBC_PORT_C1] = {
-		/* PS8815 DB */
-		.usb_port = USBC_PORT_C1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc1_usb3_db_retimer,
+		.mux = &(const struct usb_mux) {
+			/* PS8815 DB */
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc1_usb3_db_retimer,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
@@ -169,21 +176,20 @@ static void ps8815_reset(void)
 
 	CPRINTS("%s: patching ps8815 registers", __func__);
 
-	if (i2c_read8(I2C_PORT_USB_C1_TCPC,
-		      PS8XXX_I2C_ADDR1_FLAGS, 0x0f, &val) == EC_SUCCESS)
+	if (i2c_read8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_FLAGS, 0x0f,
+		      &val) == EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f was %02x", val);
 	else {
 		CPRINTS("delay 10ms to make sure PS8815 is waken from idle");
 		msleep(10);
 	}
 
-
-	if (i2c_write8(I2C_PORT_USB_C1_TCPC,
-		       PS8XXX_I2C_ADDR1_FLAGS, 0x0f, 0x31) == EC_SUCCESS)
+	if (i2c_write8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_FLAGS, 0x0f,
+		       0x31) == EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f set to 0x31");
 
-	if (i2c_read8(I2C_PORT_USB_C1_TCPC,
-		      PS8XXX_I2C_ADDR1_FLAGS, 0x0f, &val) == EC_SUCCESS)
+	if (i2c_read8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_FLAGS, 0x0f,
+		      &val) == EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f now %02x", val);
 }
 
@@ -209,10 +215,11 @@ static void board_init_ps8815_detection(void)
 
 	CPRINTSUSB("%s", __func__);
 
-	rv = i2c_read8(I2C_PORT_USB_C1_TCPC,
-			PS8XXX_I2C_ADDR1_FLAGS, 0x00, &val);
+	rv = i2c_read8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_FLAGS, 0x00,
+		       &val);
 
-	db_usb_hw_pres = (rv == EC_SUCCESS)?DB_USB_PRESENT:DB_USB_NOT_PRESENT;
+	db_usb_hw_pres = (rv == EC_SUCCESS) ? DB_USB_PRESENT :
+					      DB_USB_NOT_PRESENT;
 
 	if (db_usb_hw_pres == DB_USB_NOT_PRESENT)
 		CPRINTS("DB isn't plugged or something went wrong!");
@@ -230,7 +237,7 @@ static bool board_detect_ps8815_db(void)
 		return true;
 
 	if (ec_cfg_usb_db_type() == DB_USB3_PS8815 &&
-		db_usb_hw_pres == DB_USB_PRESENT)
+	    db_usb_hw_pres == DB_USB_PRESENT)
 		return true;
 
 	CPRINTSUSB("No PS8815 DB");
@@ -257,8 +264,7 @@ void board_reset_pd_mcu(void)
 	/*
 	 * delay for power-on to reset-off and min. assertion time
 	 */
-	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS,
-			   PS8815_PWR_H_RST_H_DELAY_MS));
+	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS));
 
 	gpio_set_level(GPIO_USB_C0_TCPC_RST_ODL, 1);
 	gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 1);
@@ -274,7 +280,7 @@ void board_reset_pd_mcu(void)
 	 */
 	board_init_ps8815_detection();
 	usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED |
-				USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
 
 static void board_tcpc_init(void)
@@ -385,7 +391,7 @@ __override bool board_is_dts_port(int port)
 
 __override uint8_t board_get_usb_pd_port_count(void)
 {
-	CPRINTSUSB("%s is called by task_id:%d",  __func__, task_get_current());
+	CPRINTSUSB("%s is called by task_id:%d", __func__, task_get_current());
 
 	if (board_detect_ps8815_db())
 		return CONFIG_USB_PD_PORT_MAX_COUNT;
diff --git a/board/taeko/usbc_config.h b/board/taeko/usbc_config.h
index 9030333dbc..9a35b4880f 100644
--- a/board/taeko/usbc_config.h
+++ b/board/taeko/usbc_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,13 +8,9 @@
 #ifndef __CROS_EC_USBC_CONFIG_H
 #define __CROS_EC_USBC_CONFIG_H
 
-#define CONFIG_USB_PD_PORT_MAX_COUNT	2
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 void config_usb_db_type(void);
 
diff --git a/board/taniks/battery.c b/board/taniks/battery.c
index f62aae62a1..013c27602c 100644
--- a/board/taniks/battery.c
+++ b/board/taniks/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -124,7 +124,9 @@ __override bool board_battery_is_initialized(void)
 	bool batt_initialization_state;
 	int batt_status;
 
-	batt_initialization_state = (battery_status(&batt_status) ? false :
-		!!(batt_status & STATUS_INITIALIZED));
+	batt_initialization_state =
+		(battery_status(&batt_status) ?
+			 false :
+			 !!(batt_status & STATUS_INITIALIZED));
 	return batt_initialization_state;
 }
diff --git a/board/taniks/board.c b/board/taniks/board.c
index 894e055b9a..5da998524b 100644
--- a/board/taniks/board.c
+++ b/board/taniks/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -34,8 +34,8 @@
 #include "gpio_list.h" /* Must come after other header files. */
 
 /* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 /******************************************************************************/
 /* USB-A charging control */
@@ -60,9 +60,7 @@ __override void board_cbi_init(void)
 
 void board_init(void)
 {
-#ifdef SECTION_IS_RW
 	rgbkbd_register_init_setting(&rgbkbd_init_taniks);
-#endif
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
@@ -102,8 +100,8 @@ int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
 	}
 
 	if (voltage < BC12_MIN_VOLTAGE) {
-		CPRINTS("%s: port %d: vbus %d lower than %d", __func__,
-			port, voltage, BC12_MIN_VOLTAGE);
+		CPRINTS("%s: port %d: vbus %d lower than %d", __func__, port,
+			voltage, BC12_MIN_VOLTAGE);
 		return 1;
 	}
 
@@ -119,7 +117,7 @@ enum battery_present battery_hw_present(void)
 }
 
 __override void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+				       int max_ma, int charge_mv)
 {
 	/*
 	 * Follow OEM request to limit the input current to
@@ -127,7 +125,6 @@ __override void board_set_charge_limit(int port, int supplier, int charge_ma,
 	 */
 	charge_ma = charge_ma * 95 / 100;
 
-	charge_set_input_current_limit(MAX(charge_ma,
-					CONFIG_CHARGER_INPUT_CURRENT),
-					charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
diff --git a/board/taniks/board.h b/board/taniks/board.h
index 0756395afa..6cd42ad7bb 100644
--- a/board/taniks/board.h
+++ b/board/taniks/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -40,15 +40,14 @@
 #define CONFIG_LED_ONOFF_STATES
 
 /* Sensors */
-#define	CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-
+#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
 
 /* Change Request (b/211078551)
  * GYRO sensor change from ST LSM6DSOETR3TR to ST LSM6DS3TR-C
  *	LSM6DSOETR3TR base accel/gyro if board id = 0
  *	LSM6DS3TR-C Base accel/gyro if board id > 0
  */
-#define CONFIG_ACCELGYRO_LSM6DSO	/* Base accel */
+#define CONFIG_ACCELGYRO_LSM6DSO /* Base accel */
 #define CONFIG_ACCEL_LSM6DSO_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 #define CONFIG_ACCELGYRO_LSM6DSM
@@ -63,35 +62,34 @@
 #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
 
 /* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
-	(BIT(LID_ACCEL))
+#define CONFIG_ACCEL_FORCE_MODE_MASK (BIT(LID_ACCEL))
 
 /* Lid accel */
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE	BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID	LID_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
 #define CONFIG_ACCEL_BMA4XX
 #define CONFIG_ACCEL_LIS2DWL
 
-
 /* Sensor console commands */
 #define CONFIG_CMD_ACCELS
 #define CONFIG_CMD_ACCEL_INFO
 
 /* USB Type A Features */
-#define USB_PORT_COUNT			1
+#define USB_PORT_COUNT 1
 #define CONFIG_USB_PORT_POWER_DUMB
 
 #define CONFIG_IO_EXPANDER
 #define CONFIG_IO_EXPANDER_NCT38XX
-#define CONFIG_IO_EXPANDER_PORT_COUNT		1
+#define CONFIG_IO_EXPANDER_PORT_COUNT 1
 
 /* USB Type C and USB PD defines */
 #define CONFIG_USB_PD_TCPM_PS8815
 #define CONFIG_USB_PD_TCPM_PS8815_FORCE_DID
 #define CONFIG_USBC_PPC_SYV682X
 #define CONFIG_USBC_PPC_NX20P3483
+#define CONFIG_USBC_NX20P348X_RCP_5VSRC_MASK_ENABLE
 
 #define CONFIG_USB_PD_FRS_PPC
 #define CONFIG_USB_PD_FRS
@@ -103,17 +101,17 @@
 #define CONFIG_HOSTCMD_I2C_CONTROL
 
 /* TODO: b/177608416 - measure and check these values on brya */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
 
 /*
  * Passive USB-C cables only support up to 60W.
  */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		45000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 45000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* The lower the input voltage, the higher the power efficiency. */
 #define PD_PREFER_LOW_VOLTAGE
@@ -124,94 +122,94 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT		GPIO_EC_EN_EDP_BL
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KSI_00			GPIO_EC_KSI_00
-#define GPIO_KSI_01			GPIO_EC_KSI_01
-#define GPIO_KSI_02			GPIO_EC_KSI_02
-#define GPIO_KSI_03			GPIO_EC_KSI_03
-#define GPIO_KSI_04			GPIO_EC_KSI_04
-#define GPIO_KSI_05			GPIO_EC_KSI_05
-#define GPIO_KSI_06			GPIO_EC_KSI_06
-#define GPIO_KSI_07			GPIO_EC_KSI_07
-#define GPIO_KSO_00			GPIO_EC_KSO_00
-#define GPIO_KSO_01			GPIO_EC_KSO_01
-#define GPIO_KSO_02			GPIO_EC_KSO_02_R
-#define GPIO_KSO_03			GPIO_EC_KSO_03
-#define GPIO_KSO_04			GPIO_EC_KSO_04
-#define GPIO_KSO_05			GPIO_EC_KSO_05
-#define GPIO_KSO_06			GPIO_EC_KSO_06_R
-#define GPIO_KSO_07			GPIO_EC_KSO_07_R
-#define GPIO_KSO_08			GPIO_EC_KSO_08
-#define GPIO_KSO_09			GPIO_EC_KSO_09
-#define GPIO_KSO_10			GPIO_EC_KSO_10
-#define GPIO_KSO_11			GPIO_EC_KSO_11
-#define GPIO_KSO_12			GPIO_EC_KSO_12
-#define GPIO_KSO_13			GPIO_EC_KSO_13
-#define GPIO_KSO_14			GPIO_EC_KSO_14
-#define GPIO_RFR_KEY_L			GPIO_EC_RFR_KEY_ODL_R
-#define GPIO_PACKET_MODE_EN		GPIO_EC_GSC_PACKET_MODE
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SYS_SLP_S0IX_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KSI_00 GPIO_EC_KSI_00
+#define GPIO_KSI_01 GPIO_EC_KSI_01
+#define GPIO_KSI_02 GPIO_EC_KSI_02
+#define GPIO_KSI_03 GPIO_EC_KSI_03
+#define GPIO_KSI_04 GPIO_EC_KSI_04
+#define GPIO_KSI_05 GPIO_EC_KSI_05
+#define GPIO_KSI_06 GPIO_EC_KSI_06
+#define GPIO_KSI_07 GPIO_EC_KSI_07
+#define GPIO_KSO_00 GPIO_EC_KSO_00
+#define GPIO_KSO_01 GPIO_EC_KSO_01
+#define GPIO_KSO_02 GPIO_EC_KSO_02_R
+#define GPIO_KSO_03 GPIO_EC_KSO_03
+#define GPIO_KSO_04 GPIO_EC_KSO_04
+#define GPIO_KSO_05 GPIO_EC_KSO_05
+#define GPIO_KSO_06 GPIO_EC_KSO_06_R
+#define GPIO_KSO_07 GPIO_EC_KSO_07_R
+#define GPIO_KSO_08 GPIO_EC_KSO_08
+#define GPIO_KSO_09 GPIO_EC_KSO_09
+#define GPIO_KSO_10 GPIO_EC_KSO_10
+#define GPIO_KSO_11 GPIO_EC_KSO_11
+#define GPIO_KSO_12 GPIO_EC_KSO_12
+#define GPIO_KSO_13 GPIO_EC_KSO_13
+#define GPIO_KSO_14 GPIO_EC_KSO_14
+#define GPIO_RFR_KEY_L GPIO_EC_RFR_KEY_ODL_R
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
 
 /*
  * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
  * signal.
  */
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_SEQ_EC_ALL_SYS_PG
-#define GPIO_PG_EC_DSW_PWROK		GPIO_SEQ_EC_DSW_PWROK
-#define GPIO_PG_EC_RSMRST_ODL		GPIO_SEQ_EC_RSMRST_ODL
-#define GPIO_POWER_BUTTON_L		GPIO_GSC_EC_PWR_BTN_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_ODL
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
 
 /* System has back-lit keyboard */
 #define CONFIG_PWM
 #define CONFIG_KEYBOARD_BACKLIGHT
 
 /* I2C Bus Configuration */
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0_TCPC	NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1_TCPC	NPCX_I2C_PORT4_1
-#define I2C_PORT_USB_C0_PPC	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_PPC	NPCX_I2C_PORT6_1
-#define I2C_PORT_USB_C0_BC12	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_BC12	NPCX_I2C_PORT6_1
-#define I2C_PORT_USB_C1_MUX	NPCX_I2C_PORT6_1
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT5_0
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT7_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-#define I2C_PORT_MP2964		NPCX_I2C_PORT7_0
-#define I2C_PORT_KBMCU		NPCX_I2C_PORT3_0
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-
-#define I2C_ADDR_MP2964_FLAGS	0x20
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0_TCPC NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1
+#define I2C_PORT_USB_C0_PPC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C0_BC12 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0
+#define I2C_PORT_KBMCU NPCX_I2C_PORT3_0
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
+
+#define I2C_ADDR_MP2964_FLAGS 0x20
 
 /* Thermal features */
 #define CONFIG_THERMISTOR
 #define CONFIG_TEMP_SENSOR
-#define CONFIG_TEMP_SENSOR_POWER_GPIO	GPIO_SEQ_EC_DSW_PWROK
+#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_SEQ_EC_DSW_PWROK
 #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
 
 /* Fan */
-#define CONFIG_FANS			FAN_CH_COUNT
+#define CONFIG_FANS FAN_CH_COUNT
 
 /* Charger defines */
 #define CONFIG_CHARGER_BQ25720
 #define CONFIG_CHARGER_BQ25720_VSYS_TH2_CUSTOM
 /* 37h BIT7:2 VSYS_TH2 6.0V */
-#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV	60
+#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV 60
 #define CONFIG_CHARGE_RAMP_SW
-#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10
 /* 30h BIT13:12 Enable PSYS 00b */
 #define CONFIG_CHARGER_BQ25710_PSYS_SENSING
 /* 30h BIT7 1.2V enable*/
@@ -232,24 +230,23 @@
 #define CONFIG_CHARGER_BQ25710_PP_COMP
 /* 36h UVP 5600mV */
 #define CONFIG_CHARGER_BQ25720_VSYS_UVP_CUSTOM
-#define CONFIG_CHARGER_BQ25720_VSYS_UVP \
-	BQ25720_CHARGE_OPTION_4_VSYS_UVP__5P6
+#define CONFIG_CHARGER_BQ25720_VSYS_UVP BQ25720_CHARGE_OPTION_4_VSYS_UVP__5P6
 /* 3Eh BIT15:8 VSYS_MIN 6.1V */
 #define CONFIG_CHARGER_BQ25710_VSYS_MIN_VOLTAGE_CUSTOM
 #define CONFIG_CHARGER_BQ25710_VSYS_MIN_VOLTAGE_MV 6100
 
 /* RGB Keyboard */
-#define GPIO_RGBKBD_SDB_L	GPIO_KBMCU_INT_ODL
-#ifdef SECTION_IS_RW
+#define GPIO_RGBKBD_SDB_L GPIO_KBMCU_INT_ODL
+
 #define CONFIG_RGB_KEYBOARD
-#define CONFIG_LED_DRIVER_AW20198     /* Awinic AW20198 on I2C */
-#endif
-#define RGB_GRID0_COL		8
-#define RGB_GRID0_ROW		6
+#define CONFIG_LED_DRIVER_AW20198 /* Awinic AW20198 on I2C */
+
+#define RGB_GRID0_COL 8
+#define RGB_GRID0_ROW 6
 
 #ifndef __ASSEMBLER__
 
-#include "gpio_signal.h"	/* needed by registers.h */
+#include "gpio_signal.h" /* needed by registers.h */
 #include "registers.h"
 #include "usbc_config.h"
 
@@ -275,17 +272,9 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum sensor_id {
-	LID_ACCEL = 0,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL = 0, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
-enum ioex_port {
-	IOEX_C0_NCT38XX = 0,
-	IOEX_PORT_COUNT
-};
+enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_PORT_COUNT };
 
 enum battery_type {
 	BATTERY_SMP_51W,
@@ -295,19 +284,13 @@ enum battery_type {
 };
 
 enum pwm_channel {
-	PWM_CH_FAN,			/* PWM5 */
+	PWM_CH_FAN, /* PWM5 */
 	PWM_CH_COUNT
 };
 
-enum fan_channel {
-	FAN_CH_0 = 0,
-	FAN_CH_COUNT
-};
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT };
 
-enum mft_channel {
-	MFT_CH_0 = 0,
-	MFT_CH_COUNT
-};
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT };
 
 void motion_interrupt(enum gpio_signal signal);
 
diff --git a/board/taniks/build.mk b/board/taniks/build.mk
index 2afcd5a0f8..7d01cfff96 100644
--- a/board/taniks/build.mk
+++ b/board/taniks/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/taniks/charger.c b/board/taniks/charger.c
index 476ce97df2..a4fa209246 120000..100644
--- a/board/taniks/charger.c
+++ b/board/taniks/charger.c
@@ -1 +1,90 @@
-../../baseboard/brya/charger_bq25720.c
\ No newline at end of file
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+
+#include "charge_manager.h"
+#include "charge_state_v2.h"
+#include "charger.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/charger/bq25710.h"
+#include "usbc_ppc.h"
+#include "usb_pd.h"
+#include "util.h"
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+#ifndef CONFIG_ZEPHYR
+/* Charger Chip Configuration */
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = BQ25710_SMBUS_ADDR1_FLAGS,
+		.drv = &bq25710_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CHARGER_NUM);
+#endif
+
+int board_set_active_charge_port(int port)
+{
+	int is_valid_port = board_is_usb_pd_port_present(port);
+	int i;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTSUSB("Disabling all charger ports");
+
+		/* Disable all ports. */
+		for (i = 0; i < ppc_cnt; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (ppc_vbus_sink_enable(i, 0))
+				CPRINTSUSB("Disabling C%d as sink failed.", i);
+		}
+
+		return EC_SUCCESS;
+	} else if (!is_valid_port) {
+		return EC_ERROR_INVAL;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (ppc_is_sourcing_vbus(port)) {
+		CPRINTFUSB("Skip enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTSUSB("New charge port: C%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < ppc_cnt; i++) {
+		if (i == port)
+			continue;
+
+		if (ppc_vbus_sink_enable(i, 0))
+			CPRINTSUSB("C%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTSUSB("C%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+__overridable void board_set_charge_limit(int port, int supplier, int charge_ma,
+					  int max_ma, int charge_mv)
+{
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+}
diff --git a/board/taniks/ec.tasklist b/board/taniks/ec.tasklist
index 13a5229984..c879d3f77c 100644
--- a/board/taniks/ec.tasklist
+++ b/board/taniks/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,7 +12,7 @@
 
 #define CONFIG_TASK_LIST \
 	TASK_ALWAYS(HOOKS, hook_task, NULL, HOOKS_TASK_STACK_SIZE) \
-	TASK_ALWAYS_RW(RGBKBD, rgbkbd_task, NULL, BASEBOARD_RGBKBD_TASK_STACK_SIZE) \
+	TASK_ALWAYS(RGBKBD, rgbkbd_task, NULL, BASEBOARD_RGBKBD_TASK_STACK_SIZE) \
 	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, BASEBOARD_CHG_RAMP_TASK_STACK_SIZE) \
 	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
 	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \
diff --git a/board/taniks/fans.c b/board/taniks/fans.c
index d50d3e5506..aeb2ff2caa 100644
--- a/board/taniks/fans.c
+++ b/board/taniks/fans.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,7 +25,7 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 static const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
diff --git a/board/taniks/fw_config.c b/board/taniks/fw_config.c
index cf1e27ad83..7d6323c868 100644
--- a/board/taniks/fw_config.c
+++ b/board/taniks/fw_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,7 +10,7 @@
 #include "fw_config.h"
 #include "gpio.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 static union taniks_cbi_fw_config fw_config;
 BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
@@ -65,7 +65,7 @@ void board_init_fw_config(void)
 		CPRINTS("CBI: Using board defaults for early board");
 		if (ec_cfg_has_tabletmode()) {
 			fw_config = fw_config_defaults;
-		} 
+		}
 	}
 
 	determine_storage();
diff --git a/board/taniks/fw_config.h b/board/taniks/fw_config.h
index 9e1b0ebdf1..05ca552538 100644
--- a/board/taniks/fw_config.h
+++ b/board/taniks/fw_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,20 +14,14 @@
  * Source of truth is the project/taniks/taniks/config.star configuration file.
  */
 
-enum ec_cfg_usb_db_type {
-	DB_USB_ABSENT = 0,
-	DB_USB3_PS8815 = 1
-};
+enum ec_cfg_usb_db_type { DB_USB_ABSENT = 0, DB_USB3_PS8815 = 1 };
 
 enum ec_cfg_keyboard_backlight_type {
 	KEYBOARD_BACKLIGHT_DISABLED = 0,
 	KEYBOARD_BACKLIGHT_ENABLED = 1
 };
 
-enum ec_cfg_tabletmode_type {
-	TABLETMODE_DISABLED = 0,
-	TABLETMODE_ENABLED = 1
-};
+enum ec_cfg_tabletmode_type { TABLETMODE_DISABLED = 0, TABLETMODE_ENABLED = 1 };
 
 enum ec_cfg_nvme_status {
 	NVME_DISABLED = 0,
@@ -40,11 +34,11 @@ enum ec_cfg_emmc_status {
 
 union taniks_cbi_fw_config {
 	struct {
-		enum ec_cfg_usb_db_type			usb_db : 2;
-		uint32_t				sd_db : 2;
-		enum ec_cfg_keyboard_backlight_type	kb_bl : 1;
-		uint32_t				audio : 3;
-		uint32_t				reserved_1 : 4;
+		enum ec_cfg_usb_db_type usb_db : 2;
+		uint32_t sd_db : 2;
+		enum ec_cfg_keyboard_backlight_type kb_bl : 1;
+		uint32_t audio : 3;
+		uint32_t reserved_1 : 4;
 		/* b/211079131 - Fw config structure
 		 * b/211076082 - Move tablet mode to bit14
 		 * bit8-9: kb_layout
@@ -52,10 +46,10 @@ union taniks_cbi_fw_config {
 		 * bit12: nvme
 		 * bit13: emmc
 		 */
-		enum ec_cfg_nvme_status			nvme_status : 1;
-		enum ec_cfg_emmc_status			emmc_status : 1;
-		enum ec_cfg_tabletmode_type		tabletmode : 1;
-		uint32_t				reserved_2 : 17;
+		enum ec_cfg_nvme_status nvme_status : 1;
+		enum ec_cfg_emmc_status emmc_status : 1;
+		enum ec_cfg_tabletmode_type tabletmode : 1;
+		uint32_t reserved_2 : 17;
 	};
 	uint32_t raw_value;
 };
diff --git a/board/taniks/gpio.inc b/board/taniks/gpio.inc
index 0dff3216de..d2c2bdffb9 100644
--- a/board/taniks/gpio.inc
+++ b/board/taniks/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/taniks/i2c.c b/board/taniks/i2c.c
index 769385c46f..5be2ad4b85 100644
--- a/board/taniks/i2c.c
+++ b/board/taniks/i2c.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -44,7 +44,8 @@ const struct i2c_port_t i2c_ports[] = {
 	},
 	{
 		/* I2C4 C1 TCPC */
-		/* TODO(b/211080526): Change TCPC1's (PS8815) I2C frequency from 400Khz to 1000Khz */
+		/* TODO(b/211080526): Change TCPC1's (PS8815) I2C frequency from
+		   400Khz to 1000Khz */
 		.name = "tcpc1",
 		.port = I2C_PORT_USB_C1_TCPC,
 		.kbps = 1000,
diff --git a/board/taniks/keyboard.c b/board/taniks/keyboard.c
index 99099b4661..069627a168 100644
--- a/board/taniks/keyboard.c
+++ b/board/taniks/keyboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -28,7 +28,7 @@ __override struct keyboard_scan_config keyscan_config = {
 };
 
 static const struct ec_response_keybd_config taniks_kb = {
-	.num_top_row_keys = 14,
+	.num_top_row_keys = 11,
 	.action_keys = {
 		TK_BACK,		/* T1 */
 		TK_REFRESH,		/* T2 */
@@ -37,17 +37,47 @@ static const struct ec_response_keybd_config taniks_kb = {
 		TK_SNAPSHOT,		/* T5 */
 		TK_BRIGHTNESS_DOWN,	/* T6 */
 		TK_BRIGHTNESS_UP,	/* T7 */
-		TK_ABSENT,		/* T8 */
-		TK_ABSENT,		/* T9 */
-		TK_ABSENT,		/* T10 */
-		TK_MICMUTE,		/* T11 */
-		TK_VOL_MUTE,		/* T12 */
-		TK_VOL_DOWN,		/* T13 */
-		TK_VOL_UP,		/* T14 */
+		TK_MICMUTE,		/* T8 */
+		TK_VOL_MUTE,		/* T9 */
+		TK_VOL_DOWN,		/* T10 */
+		TK_VOL_UP,		/* T11 */
 	},
 	.capabilities = KEYBD_CAP_SCRNLOCK_KEY | KEYBD_CAP_NUMERIC_KEYPAD,
 };
 
+/*
+ * Row Column info for Top row keys T1 - T15.
+ * For taniks keyboard layout(T11 - T14) and
+ * printing(F8 - F11) are different issue.
+ * Move T11 - T14 row and col setting to T8 - T11.
+ * Need define row col to mapping matrix layout.
+ * Change T8 row, col to (0,1)
+ * Change T9 row, col to (1,5)
+ * Change T10 row, col to (3,5)
+ * Change T11 row, col to (0,9)
+ */
+__override const struct key {
+	uint8_t row;
+	uint8_t col;
+} vivaldi_keys[] = {
+	{ .row = 0, .col = 2 }, /* T1 */
+	{ .row = 3, .col = 2 }, /* T2 */
+	{ .row = 2, .col = 2 }, /* T3 */
+	{ .row = 1, .col = 2 }, /* T4 */
+	{ .row = 3, .col = 4 }, /* T5 */
+	{ .row = 2, .col = 4 }, /* T6 */
+	{ .row = 1, .col = 4 }, /* T7 */
+	{ .row = 0, .col = 1 }, /* T8 */
+	{ .row = 1, .col = 5 }, /* T9 */
+	{ .row = 3, .col = 5 }, /* T10 */
+	{ .row = 0, .col = 9 }, /* T11 */
+	{ .row = 2, .col = 9 }, /* T12 */
+	{ .row = 1, .col = 9 }, /* T13 */
+	{ .row = 0, .col = 4 }, /* T14 */
+	{ .row = 0, .col = 11 }, /* T15 */
+};
+BUILD_ASSERT(ARRAY_SIZE(vivaldi_keys) == MAX_TOP_ROW_KEYS);
+
 static struct rgb_s grid0[RGB_GRID0_COL * RGB_GRID0_ROW];
 
 struct rgbkbd rgbkbds[] = {
@@ -66,146 +96,30 @@ const uint8_t rgbkbd_count = ARRAY_SIZE(rgbkbds);
 const uint8_t rgbkbd_hsize = RGB_GRID0_COL;
 const uint8_t rgbkbd_vsize = RGB_GRID0_ROW;
 
-#define LED(x, y)	RGBKBD_COORD((x), (y))
-#define DELM		RGBKBD_DELM
+enum ec_rgbkbd_type rgbkbd_type = EC_RGBKBD_TYPE_FOUR_ZONES_40_LEDS;
+
+#define LED(x, y) RGBKBD_COORD((x), (y))
+#define DELM RGBKBD_DELM
+
 const uint8_t rgbkbd_map[] = {
-	DELM,				/* 0: (null) */
-	LED( 0, 0), DELM,		/* 1: ~ ` */
-	LED( 2, 0), LED( 4, 0), DELM,	/* 2: ! 1 */
-	LED( 6, 0), DELM,		/* 3: @ 2 */
-	LED( 0, 1), DELM,		/* 4: # 3 */
-	LED( 2, 1), DELM,		/* 5: $ 4 */
-	LED( 4, 1), LED( 6, 1), DELM,	/* 6: % 5 */
-	LED( 0, 2), DELM,		/* 7: ^ 6 */
-	LED( 2, 2), DELM,		/* 8: & 7 */
-	LED( 4, 2), DELM,		/* 9: * 8 */
-	LED( 6, 2), DELM,		/* 10: ( 9 */
-	LED( 0, 3), DELM,		/* 11: ) 0 */
-	LED( 1, 3), DELM,		/* 12: _ - */
-	LED( 3, 3), DELM,		/* 13: + = */
-	DELM,				/* 14: (null) */
-	LED( 5, 3), LED( 6, 3), DELM,	/* 15: backspace */
-	LED( 0, 0), DELM,		/* 16: tab */
-	LED( 2, 0), LED( 4, 0), DELM,	/* 17: q */
-	LED( 6, 0), DELM,		/* 18: w */
-	LED( 0, 1), DELM,		/* 19: e */
-	LED( 2, 1), DELM,		/* 20: r */
-	LED( 4, 1), LED( 6, 1), DELM,	/* 21: t */
-	LED( 0, 2), DELM,		/* 22: y */
-	LED( 2, 2), DELM,		/* 23: u */
-	LED( 4, 2), DELM,		/* 24: i */
-	LED( 6, 2), DELM,		/* 25: o */
-	LED( 0, 3), LED( 1, 3), DELM,	/* 26: p */
-	LED( 3, 3), DELM,		/* 27: [ { */
-	LED( 5, 3), DELM,		/* 28: ] } */
-	LED( 6, 3), DELM,		/* 29: \ | */
-	LED( 0, 0), DELM,		/* 30: caps lock */
-	LED( 2, 0), LED( 4, 0), DELM,	/* 31: a */
-	LED( 6, 0), DELM,		/* 32: s */
-	LED( 0, 1), DELM,		/* 33: d */
-	LED( 2, 1), DELM,		/* 34: f */
-	LED( 4, 1), LED( 6, 1), DELM,	/* 35: g */
-	LED( 0, 2), DELM,		/* 36: h */
-	LED( 2, 2), DELM,		/* 37: j */
-	LED( 4, 2), DELM,		/* 38: k */
-	LED( 6, 4), DELM,		/* 39: l */
-	LED( 0, 3), LED( 1, 3), DELM,	/* 40: ; : */
-	LED( 3, 3), DELM,		/* 41: " ' */
-	DELM,				/* 42: (null) */
-	LED( 5, 3), LED( 6, 3), DELM,	/* 43: enter */
-	LED( 1, 0), LED( 3, 0), DELM,	/* 44: L-shift */
-	DELM,				/* 45: (null) */
-	LED( 5, 0), DELM,		/* 46: z */
-	LED( 7, 0), DELM,		/* 47: x */
-	LED( 1, 1), DELM,		/* 48: c */
-	LED( 3, 1), DELM,		/* 49: v */
-	LED( 5, 1), LED( 7, 1), DELM,	/* 50: b */
-	LED( 1, 2), DELM,		/* 51: n */
-	LED( 3, 2), DELM,		/* 52: m */
-	LED( 5, 2), DELM,		/* 53: , < */
-	LED( 7, 2), DELM,		/* 54: . > */
-	LED( 2, 3), DELM,		/* 55: / ? */
-	DELM,				/* 56: (null) */
-	LED( 4, 3), LED( 7, 3), DELM,	/* 57: R-shift */
-	LED( 1, 0), LED( 3, 0), DELM,	/* 58: L-ctrl */
-	LED( 5, 3), LED( 6, 3), DELM,	/* 59: power */
-	LED( 5, 0), LED( 7, 0), DELM,	/* 60: L-alt */
-	LED( 1, 1), LED( 3, 1),
-	LED( 5, 1), LED( 7, 1),
-	LED( 1, 2), LED( 3, 2), DELM,	/* 61: space */
-	LED( 5, 2), DELM,		/* 62: R-alt */
-	DELM,				/* 63: (null) */
-	LED( 7, 2), DELM,		/* 64: R-ctrl */
-	DELM,				/* 65: (null) */
-	DELM,				/* 66: (null) */
-	DELM,				/* 67: (null) */
-	DELM,				/* 68: (null) */
-	DELM,				/* 69: (null) */
-	DELM,				/* 70: (null) */
-	DELM,				/* 71: (null) */
-	DELM,				/* 72: (null) */
-	DELM,				/* 73: (null) */
-	DELM,				/* 74: (null) */
-	DELM,				/* 75: (null) */
-	LED( 0, 4), DELM,		/* 76: delete */
-	DELM,				/* 77: (null) */
-	DELM,				/* 78: (null) */
-	LED( 2, 3), DELM,		/* 79: left */
-	LED( 4, 4), DELM,		/* 80: home */
-	LED( 6, 4), DELM,		/* 81: end */
-	DELM,				/* 82: (null) */
-	LED( 4, 3), DELM,		/* 83: up */
-	LED( 4, 3), DELM,		/* 84: down */
-	LED( 0, 4), DELM,		/* 85: page up */
-	LED( 2, 4), DELM,		/* 86: page down */
-	DELM,				/* 87: (null) */
-	DELM,				/* 88: (null) */
-	LED( 7, 3), DELM,		/* 89: right */
-	DELM,				/* 90: (null) */
-	LED( 0, 4), DELM,		/* 91: numpad 7 */
-	LED( 0, 4), DELM,		/* 92: numpad 4 */
-	LED( 1, 4), DELM,		/* 93: numpad 1 */
-	DELM,				/* 94: (null) */
-	LED( 2, 4), DELM,		/* 95: numpad / */
-	LED( 2, 4), DELM,		/* 96: numpad 8 */
-	LED( 2, 4), DELM,		/* 97: numpad 5 */
-	LED( 3, 4), DELM,		/* 98: numpad 2 */
-	LED( 3, 4), DELM,		/* 99: numpad 0 */
-	LED( 4, 4), DELM,		/* 100: numpad * */
-	LED( 4, 4), DELM,		/* 101: numpad 9 */
-	LED( 4, 4), DELM,		/* 102: numpad 6 */
-	LED( 5, 4), DELM,		/* 103: numpad 3 */
-	LED( 5, 4), DELM,		/* 104: numpad . */
-	LED( 6, 4), DELM,		/* 105: numpad - */
-	LED( 6, 4), DELM,		/* 106: numpad + */
-	DELM,				/* 107: (null) */
-	LED( 7, 4), DELM,		/* 108: numpad enter */
-	DELM,				/* 109: (null) */
-	LED( 0, 0), DELM,		/* 110: esc */
-	LED( 2, 0), LED( 4, 0), DELM,	/* T1: back */
-	LED( 6, 0), DELM,		/* T2: refresh */
-	LED( 0, 1), DELM,		/* T3: full screen */
-	LED( 2, 1), DELM,		/* T4: overview */
-	LED( 4, 1), LED( 6, 1), DELM,	/* T5: snapshot */
-	LED( 0, 2), DELM,		/* T6: brightness down */
-	LED( 2, 2), DELM,		/* T7: brightness up */
-	DELM,				/* T8: (null) */
-	DELM,				/* T9: (null) */
-	DELM,				/* T10: (null) */
-	LED( 4, 2), DELM,		/* T11: mic mute */
-	LED( 6, 2), DELM,		/* T12: volume mute */
-	LED( 0, 3), LED( 1, 3), DELM,	/* T13: volume down */
-	LED( 3, 3), DELM,		/* T14: volume up */
-	DELM,				/* T15: (null) */
-	DELM,				/* 126: (null) */
-	DELM,				/* 127: (null) */
+	DELM, LED(0, 0), DELM, LED(1, 0), DELM, LED(2, 0), DELM, LED(3, 0),
+	DELM, LED(4, 0), DELM, LED(5, 0), DELM, LED(6, 0), DELM, LED(7, 0),
+	DELM, LED(0, 1), DELM, LED(1, 1), DELM, LED(2, 1), DELM, LED(3, 1),
+	DELM, LED(4, 1), DELM, LED(5, 1), DELM, LED(6, 1), DELM, LED(7, 1),
+	DELM, LED(0, 2), DELM, LED(1, 2), DELM, LED(2, 2), DELM, LED(3, 2),
+	DELM, LED(4, 2), DELM, LED(5, 2), DELM, LED(6, 2), DELM, LED(7, 2),
+	DELM, LED(0, 3), DELM, LED(1, 3), DELM, LED(2, 3), DELM, LED(3, 3),
+	DELM, LED(4, 3), DELM, LED(5, 3), DELM, LED(6, 3), DELM, LED(7, 3),
+	DELM, LED(0, 4), DELM, LED(1, 4), DELM, LED(2, 4), DELM, LED(3, 4),
+	DELM, LED(4, 4), DELM, LED(5, 4), DELM, LED(6, 4), DELM, LED(7, 4),
+	DELM, DELM,
 };
 #undef LED
 #undef DELM
 const size_t rgbkbd_map_size = ARRAY_SIZE(rgbkbd_map);
 
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	return &taniks_kb;
 }
diff --git a/board/taniks/led.c b/board/taniks/led.c
index 1631bce51f..6b7e0bb6cd 100644
--- a/board/taniks/led.c
+++ b/board/taniks/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,44 +14,49 @@
 #include "led_common.h"
 #include "gpio.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
 __override const int led_charge_lvl_1 = 5;
 
 __override const int led_charge_lvl_2 = 97;
 
 __override struct led_descriptor
-		led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,   1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
 
 __override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]            = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]    = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					 {LED_OFF,         3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					 {LED_OFF,         3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF,            LED_INDEFINITE} },
-};
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    1 * LED_ONE_SEC },
+						  { LED_OFF,
+						    3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
diff --git a/board/taniks/pwm.c b/board/taniks/pwm.c
index 7e834385bf..d23358db5f 100644
--- a/board/taniks/pwm.c
+++ b/board/taniks/pwm.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,10 +11,8 @@
 #include "pwm_chip.h"
 
 const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN] = {
-		.channel = 5,
-		.flags = PWM_CONFIG_OPEN_DRAIN,
-		.freq = 25000
-	},
+	[PWM_CH_FAN] = { .channel = 5,
+			 .flags = PWM_CONFIG_OPEN_DRAIN,
+			 .freq = 25000 },
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
diff --git a/board/taniks/sensors.c b/board/taniks/sensors.c
index d480849036..5371f94081 100644
--- a/board/taniks/sensors.c
+++ b/board/taniks/sensors.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,8 +22,8 @@
 #include "tablet_mode.h"
 
 #if 1
-#define CPRINTS(format, args...) ccprints(format, ## args)
-#define CPRINTF(format, args...) ccprintf(format, ## args)
+#define CPRINTS(format, args...) ccprints(format, ##args)
+#define CPRINTF(format, args...) ccprintf(format, ##args)
 #else
 #define CPRINTS(format, args...)
 #define CPRINTF(format, args...)
@@ -119,17 +119,13 @@ static struct lsm6dso_data lsm6dso_data;
 static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
 
 /* Matrix to rotate lid and base sensor into standard reference frame */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					     { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
 
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, FLOAT_TO_FP(1), 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
 
 struct motion_sensor_t bma422_lid_accel = {
 	.name = "Lid Accel - BMA",
@@ -287,7 +283,6 @@ unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 #endif
 
-
 static void board_detect_motionsensor(void)
 {
 	int ret;
@@ -304,8 +299,8 @@ static void board_detect_motionsensor(void)
 		return;
 
 	/* Check lid accel chip */
-	ret = i2c_read8(I2C_PORT_SENSOR, LIS2DW12_ADDR1,
-			LIS2DW12_WHO_AM_I_REG, &val);
+	ret = i2c_read8(I2C_PORT_SENSOR, LIS2DW12_ADDR1, LIS2DW12_WHO_AM_I_REG,
+			&val);
 	if (ret == 0 && val == LIS2DW12_WHO_AM_I) {
 		CPRINTS("LID_ACCEL is LIS2DW12");
 		return;
@@ -332,7 +327,7 @@ static void board_detect_motionsensor(void)
 	CPRINTS("No LID_ACCEL are detected");
 }
 DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_detect_motionsensor,
-		HOOK_PRIO_DEFAULT);
+	     HOOK_PRIO_DEFAULT);
 
 static void baseboard_sensors_init(void)
 {
@@ -344,27 +339,20 @@ DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_INIT_I2C + 1);
 
 /* Temperature sensor configuration */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1_DDR_SOC] = {
-		.name = "DDR and SOC",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_1_DDR_SOC
-	},
-	[TEMP_SENSOR_3_CHARGER] = {
-		.name = "CHARGER",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_3_CHARGER
-	},
-	[TEMP_SENSOR_4_CPUCHOKE] = {
-		.name = "CPU CHOKE",
-		.type = TEMP_SENSOR_TYPE_BOARD,
-		.read = get_temp_3v3_30k9_47k_4050b,
-		.idx = ADC_TEMP_SENSOR_4_CPUCHOKE
-	},
+	[TEMP_SENSOR_1_DDR_SOC] = { .name = "DDR and SOC",
+				    .type = TEMP_SENSOR_TYPE_BOARD,
+				    .read = get_temp_3v3_30k9_47k_4050b,
+				    .idx = ADC_TEMP_SENSOR_1_DDR_SOC },
+	[TEMP_SENSOR_3_CHARGER] = { .name = "CHARGER",
+				    .type = TEMP_SENSOR_TYPE_BOARD,
+				    .read = get_temp_3v3_30k9_47k_4050b,
+				    .idx = ADC_TEMP_SENSOR_3_CHARGER },
+	[TEMP_SENSOR_4_CPUCHOKE] = { .name = "CPU CHOKE",
+				     .type = TEMP_SENSOR_TYPE_BOARD,
+				     .read = get_temp_3v3_30k9_47k_4050b,
+				     .idx = ADC_TEMP_SENSOR_4_CPUCHOKE },
 };
 
-
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
 /*
@@ -377,8 +365,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CPU \
-	{ \
+#define THERMAL_CPU              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(90), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(100), \
@@ -387,7 +375,7 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(85), \
 		}, \
 		.temp_fan_off = C_TO_K(35), \
-		.temp_fan_max = C_TO_K(60), \
+		.temp_fan_max = C_TO_K(70), \
 	}
 __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 
@@ -407,8 +395,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_FAN \
-	{ \
+#define THERMAL_FAN              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(90), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(100), \
@@ -417,7 +405,7 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(85), \
 		}, \
 		.temp_fan_off = C_TO_K(35), \
-		.temp_fan_max = C_TO_K(60), \
+		.temp_fan_max = C_TO_K(70), \
 	}
 __maybe_unused static const struct ec_thermal_config thermal_fan = THERMAL_FAN;
 
diff --git a/board/taniks/usbc_config.c b/board/taniks/usbc_config.c
index 0a1b7ff194..71a495c402 100644
--- a/board/taniks/usbc_config.c
+++ b/board/taniks/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -34,13 +34,13 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 #if 0
 /* Debug only! */
-#define CPRINTSUSB(format, args...) cprints(CC_USBPD, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBPD, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBPD, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBPD, format, ##args)
 #else
 #define CPRINTSUSB(format, args...)
 #define CPRINTFUSB(format, args...)
@@ -99,24 +99,31 @@ unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
  * to the virtual_usb_mux_driver so the AP gets notified of mux changes
  * and updates the TCSS configuration on state changes.
  */
-static const struct usb_mux usbc1_usb3_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+static const struct usb_mux_chain usbc1_usb3_db_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 };
 
-const struct usb_mux usb_muxes[] = {
+const struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 	},
 	[USBC_PORT_C1] = {
-		/* PS8815 DB */
-		.usb_port = USBC_PORT_C1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc1_usb3_db_retimer,
+		.mux = &(const struct usb_mux) {
+			/* PS8815 DB */
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc1_usb3_db_retimer,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
@@ -169,21 +176,20 @@ static void ps8815_reset(void)
 
 	CPRINTS("%s: patching ps8815 registers", __func__);
 
-	if (i2c_read8(I2C_PORT_USB_C1_TCPC,
-		      PS8XXX_I2C_ADDR1_FLAGS, 0x0f, &val) == EC_SUCCESS)
+	if (i2c_read8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_FLAGS, 0x0f,
+		      &val) == EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f was %02x", val);
 	else {
 		CPRINTS("delay 10ms to make sure PS8815 is waken from idle");
 		msleep(10);
 	}
 
-
-	if (i2c_write8(I2C_PORT_USB_C1_TCPC,
-		       PS8XXX_I2C_ADDR1_FLAGS, 0x0f, 0x31) == EC_SUCCESS)
+	if (i2c_write8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_FLAGS, 0x0f,
+		       0x31) == EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f set to 0x31");
 
-	if (i2c_read8(I2C_PORT_USB_C1_TCPC,
-		      PS8XXX_I2C_ADDR1_FLAGS, 0x0f, &val) == EC_SUCCESS)
+	if (i2c_read8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_FLAGS, 0x0f,
+		      &val) == EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f now %02x", val);
 }
 
@@ -209,10 +215,11 @@ static void board_init_ps8815_detection(void)
 
 	CPRINTSUSB("%s", __func__);
 
-	rv = i2c_read8(I2C_PORT_USB_C1_TCPC,
-			PS8XXX_I2C_ADDR1_FLAGS, 0x00, &val);
+	rv = i2c_read8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_FLAGS, 0x00,
+		       &val);
 
-	db_usb_hw_pres = (rv == EC_SUCCESS)?DB_USB_PRESENT:DB_USB_NOT_PRESENT;
+	db_usb_hw_pres = (rv == EC_SUCCESS) ? DB_USB_PRESENT :
+					      DB_USB_NOT_PRESENT;
 
 	if (db_usb_hw_pres == DB_USB_NOT_PRESENT)
 		CPRINTS("DB isn't plugged or something went wrong!");
@@ -230,7 +237,7 @@ static bool board_detect_ps8815_db(void)
 		return true;
 
 	if (ec_cfg_usb_db_type() == DB_USB3_PS8815 &&
-		db_usb_hw_pres == DB_USB_PRESENT)
+	    db_usb_hw_pres == DB_USB_PRESENT)
 		return true;
 
 	CPRINTSUSB("No PS8815 DB");
@@ -257,8 +264,7 @@ void board_reset_pd_mcu(void)
 	/*
 	 * delay for power-on to reset-off and min. assertion time
 	 */
-	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS,
-			   PS8815_PWR_H_RST_H_DELAY_MS));
+	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS));
 
 	gpio_set_level(GPIO_USB_C0_TCPC_RST_ODL, 1);
 	gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 1);
@@ -274,7 +280,7 @@ void board_reset_pd_mcu(void)
 	 */
 	board_init_ps8815_detection();
 	usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED |
-				USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
 
 static void board_tcpc_init(void)
@@ -385,7 +391,7 @@ __override bool board_is_dts_port(int port)
 
 __override uint8_t board_get_usb_pd_port_count(void)
 {
-	CPRINTSUSB("%s is called by task_id:%d",  __func__, task_get_current());
+	CPRINTSUSB("%s is called by task_id:%d", __func__, task_get_current());
 
 	if (board_detect_ps8815_db())
 		return CONFIG_USB_PD_PORT_MAX_COUNT;
diff --git a/board/taniks/usbc_config.h b/board/taniks/usbc_config.h
index 8bcf365e8d..c9b8a8d71c 100644
--- a/board/taniks/usbc_config.h
+++ b/board/taniks/usbc_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,13 +8,9 @@
 #ifndef __CROS_EC_USBC_CONFIG_H
 #define __CROS_EC_USBC_CONFIG_H
 
-#define CONFIG_USB_PD_PORT_MAX_COUNT	2
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 void config_usb_db_type(void);
 
diff --git a/board/terrador/battery.c b/board/terrador/battery.c
index d129ede528..caaf3d6d55 100644
--- a/board/terrador/battery.c
+++ b/board/terrador/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/terrador/board.c b/board/terrador/board.c
index d6378d6aaa..8426216e79 100644
--- a/board/terrador/board.c
+++ b/board/terrador/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -43,7 +43,7 @@
 
 #include "gpio_list.h" /* Must come after other header files. */
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 /* Keyboard scan setting */
 __override struct keyboard_scan_config keyscan_config = {
@@ -71,7 +71,6 @@ union volteer_cbi_fw_config fw_config_defaults = {
 
 static void board_init(void)
 {
-
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
@@ -173,8 +172,8 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CPU \
-	{ \
+#define THERMAL_CPU              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
@@ -201,8 +200,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_INDUCTOR \
-	{ \
+#define THERMAL_INDUCTOR         \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
@@ -244,12 +243,15 @@ void board_reset_pd_mcu(void)
 }
 
 /* USBC mux configuration - Tiger Lake includes internal mux */
-struct usb_mux usbc0_usb4_mb_retimer = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &bb_usb_retimer,
-	.hpd_update = bb_retimer_hpd_update,
-	.i2c_port = I2C_PORT_USB_0_MIX,
-	.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
+struct usb_mux_chain usbc0_usb4_mb_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_0_MIX,
+			.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
+		},
 };
 /*****************************************************************************
  * USB-C MUX/Retimer dynamic configuration.
@@ -258,7 +260,7 @@ static void setup_mux(void)
 {
 	CPRINTS("C0 supports bb-retimer");
 	/* USB-C port 0 have a retimer */
-	usb_muxes[USBC_PORT_C0].next_mux = &usbc0_usb4_mb_retimer;
+	usb_muxes[USBC_PORT_C0].next = &usbc0_usb4_mb_retimer;
 }
 
 __override void board_cbi_init(void)
@@ -270,7 +272,6 @@ __override void board_cbi_init(void)
 	/* Reassign USB_C0_RT_RST_ODL */
 	bb_controls[USBC_PORT_C0].usb_ls_en_gpio = GPIO_USB_C0_LS_EN;
 	bb_controls[USBC_PORT_C0].retimer_rst_gpio = GPIO_USB_C0_RT_RST_ODL;
-
 }
 
 /******************************************************************************/
@@ -344,24 +345,31 @@ BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
 
 /******************************************************************************/
 /* USBC mux configuration - Tiger Lake includes internal mux */
-struct usb_mux usbc1_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+struct usb_mux_chain usbc1_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
-struct usb_mux usb_muxes[] = {
+struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 	},
 	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.next_mux = &usbc1_tcss_usb_mux,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_1_MIX,
-		.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_1_MIX,
+			.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc1_tcss_usb_mux,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
diff --git a/board/terrador/board.h b/board/terrador/board.h
index 4572a544c8..e0a075df9c 100644
--- a/board/terrador/board.h
+++ b/board/terrador/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,6 +14,8 @@
 /* Free flash space */
 #define CONFIG_USB_PD_DEBUG_LEVEL 2
 #undef CONFIG_CONSOLE_CMDHELP
+#undef CONFIG_CMD_BATTFAKE
+#define CONFIG_DEBUG_ASSERT_BRIEF
 
 /* Optional features */
 #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
@@ -46,49 +48,48 @@
 
 /* TCS3400 ALS */
 #define CONFIG_ALS
-#define ALS_COUNT		1
+#define ALS_COUNT 1
 #define CONFIG_ALS_TCS3400
 #define CONFIG_ALS_TCS3400_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS)
 
 /* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
-	(BIT(LID_ACCEL) | BIT(CLEAR_ALS))
+#define CONFIG_ACCEL_FORCE_MODE_MASK (BIT(LID_ACCEL) | BIT(CLEAR_ALS))
 
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE		BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID		LID_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
 
 /* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
 
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
 
 /*
  * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
  * cables only support up to 60W.
  */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Enabling Thunderbolt-compatible mode */
 #define CONFIG_USB_PD_TBT_COMPAT_MODE
 
 /* Enabling USB4 mode */
 #define CONFIG_USB_PD_USB4
-#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR	0x40
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x40
+#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x40
+#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x40
 
 /* USB Type A Features */
-#define USB_PORT_COUNT			1
+#define USB_PORT_COUNT 1
 #define CONFIG_USB_PORT_POWER_DUMB
 
 /* USBC PPC*/
-#define CONFIG_USBC_PPC_SYV682X		/* USBC port C0/C1 */
+#define CONFIG_USBC_PPC_SYV682X /* USBC port C0/C1 */
 
 /* BC 1.2 */
 
@@ -98,8 +99,8 @@
 #undef CONFIG_FANS
 
 /* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 
 /*
  * Macros for GPIO signals used in common code that don't match the
@@ -107,47 +108,46 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_DSW_PWROK		GPIO_EC_PCH_DSW_PWROK
-#define GPIO_PG_EC_DSW_PWROK		GPIO_DSW_PWROK
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_LID_OPEN GPIO_EC_LID_OPEN
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK
+#define GPIO_PG_EC_DSW_PWROK GPIO_DSW_PWROK
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
 
 /* I2C Bus Configuration */
 #define CONFIG_I2C
-#define I2C_PORT_ACCEL		I2C_PORT_SENSOR
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_0_MIX	NPCX_I2C_PORT3_0
-#define I2C_PORT_USB_1_MIX	NPCX_I2C_PORT4_1
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_0_MIX NPCX_I2C_PORT3_0
+#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT4_1
+#define I2C_PORT_POWER NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+
+#define I2C_PORT_BATTERY I2C_PORT_POWER
+#define I2C_PORT_CHARGER I2C_PORT_EEPROM
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 #define CONFIG_I2C_CONTROLLER
 
-
 #ifndef __ASSEMBLER__
 
 #include "gpio_signal.h"
@@ -176,11 +176,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 void board_reset_pd_mcu(void);
 
diff --git a/board/terrador/build.mk b/board/terrador/build.mk
index b78172d3cf..824bac888e 100644
--- a/board/terrador/build.mk
+++ b/board/terrador/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/terrador/ec.tasklist b/board/terrador/ec.tasklist
index 3e20d8ae39..c29125d517 100644
--- a/board/terrador/ec.tasklist
+++ b/board/terrador/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/terrador/gpio.inc b/board/terrador/gpio.inc
index f32b8328e3..6d3c4cb720 100644
--- a/board/terrador/gpio.inc
+++ b/board/terrador/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,7 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
diff --git a/board/terrador/led.c b/board/terrador/led.c
index 640312bd64..ce2d497ea7 100644
--- a/board/terrador/led.c
+++ b/board/terrador/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,16 +19,16 @@ const enum ec_led_id supported_led_ids[] = {
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 struct pwm_led_color_map led_color_map[] = {
-				/* Green, Red, Blue */
-	[EC_LED_COLOR_GREEN] =  {    100,   0,    0 },
-	[EC_LED_COLOR_RED] =    {      0, 100,    0 },
-	[EC_LED_COLOR_BLUE] =   {      0,   0,  100 },
+	/* Green, Red, Blue */
+	[EC_LED_COLOR_GREEN] = { 100, 0, 0 },
+	[EC_LED_COLOR_RED] = { 0, 100, 0 },
+	[EC_LED_COLOR_BLUE] = { 0, 0, 100 },
 	/* The green LED seems to be brighter than the others, so turn down
 	 * green from its natural level for these secondary colors.
 	 */
-	[EC_LED_COLOR_YELLOW] = {     70, 100,    0 },
-	[EC_LED_COLOR_WHITE] =  {     70, 100,  100 },
-	[EC_LED_COLOR_AMBER] =  {     20, 100,    0 },
+	[EC_LED_COLOR_YELLOW] = { 70, 100, 0 },
+	[EC_LED_COLOR_WHITE] = { 70, 100, 100 },
+	[EC_LED_COLOR_AMBER] = { 20, 100, 0 },
 };
 
 struct pwm_led pwm_leds[] = {
diff --git a/board/terrador/sensors.c b/board/terrador/sensors.c
index 77b26515c0..8f187f904c 100644
--- a/board/terrador/sensors.c
+++ b/board/terrador/sensors.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -85,17 +85,13 @@ static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
 };
 
 /* Rotation matrix for the lid accelerometer */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+				       { FLOAT_TO_FP(-1), 0, 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
diff --git a/board/tglrvp_ish/board.c b/board/tglrvp_ish/board.c
index a0584410b3..f05d7d337c 100644
--- a/board/tglrvp_ish/board.c
+++ b/board/tglrvp_ish/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,11 +19,7 @@
 
 /* I2C port map */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 1000
-	},
+	{ .name = "sensor", .port = I2C_PORT_SENSOR, .kbps = 1000 },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
diff --git a/board/tglrvp_ish/board.h b/board/tglrvp_ish/board.h
index 12f4b5992a..702494cdcc 100644
--- a/board/tglrvp_ish/board.h
+++ b/board/tglrvp_ish/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,7 +22,7 @@
 #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
 
 /* ISH specific */
-#undef  CONFIG_DEBUG_ASSERT
+#undef CONFIG_DEBUG_ASSERT
 #define CONFIG_CLOCK_CRYSTAL
 #define CONFIG_ISH_UART_0
 /* EC */
@@ -31,7 +31,7 @@
 #define CONFIG_I2C
 #define CONFIG_I2C_CONTROLLER
 
-#define CONFIG_ACCELGYRO_LSM6DSM	/* For LSM6DS3 */
+#define CONFIG_ACCELGYRO_LSM6DSM /* For LSM6DS3 */
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(BASE_ACCEL)
 
 /* Host command over HECI */
@@ -81,8 +81,8 @@
 
 #define CONFIG_ISH_IPAPG
 
-#define CONFIG_ISH_D0I2_MIN_USEC	(15*MSEC)
-#define CONFIG_ISH_D0I3_MIN_USEC	(50*MSEC)
+#define CONFIG_ISH_D0I2_MIN_USEC (15 * MSEC)
+#define CONFIG_ISH_D0I3_MIN_USEC (50 * MSEC)
 
 #define CONFIG_ISH_NEW_PM
 
@@ -92,10 +92,7 @@
 #include "registers.h"
 
 /* Motion sensors */
-enum sensor_id {
-	BASE_ACCEL,
-	SENSOR_COUNT
-};
+enum sensor_id { BASE_ACCEL, SENSOR_COUNT };
 
 #endif /* !__ASSEMBLER__ */
 
diff --git a/board/tglrvp_ish/build.mk b/board/tglrvp_ish/build.mk
index 74ec3c865f..4a84a1f475 100644
--- a/board/tglrvp_ish/build.mk
+++ b/board/tglrvp_ish/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/tglrvp_ish/ec.tasklist b/board/tglrvp_ish/ec.tasklist
index a4db486e9a..de7d256324 100644
--- a/board/tglrvp_ish/ec.tasklist
+++ b/board/tglrvp_ish/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/tglrvp_ish/gpio.inc b/board/tglrvp_ish/gpio.inc
index 286309e388..8b25af63cb 100644
--- a/board/tglrvp_ish/gpio.inc
+++ b/board/tglrvp_ish/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/tigertail/board.c b/board/tigertail/board.c
index e7679a125d..abdd3df10b 100644
--- a/board/tigertail/board.c
+++ b/board/tigertail/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,16 +27,14 @@
 
 #include "gpio_list.h"
 
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 /******************************************************************************
  * Forward UARTs as a USB serial interface.
  */
 
-#define USB_STREAM_RX_SIZE	16
-#define USB_STREAM_TX_SIZE	16
+#define USB_STREAM_RX_SIZE 16
+#define USB_STREAM_TX_SIZE 16
 
 /******************************************************************************
  * Forward USART1 as a simple USB serial interface.
@@ -44,43 +42,33 @@
 static struct usart_config const usart1;
 struct usb_stream_config const usart1_usb;
 
-static struct queue const usart1_to_usb = QUEUE_DIRECT(64, uint8_t,
-	usart1.producer, usart1_usb.consumer);
-static struct queue const usb_to_usart1 = QUEUE_DIRECT(64, uint8_t,
-	usart1_usb.producer, usart1.consumer);
+static struct queue const usart1_to_usb =
+	QUEUE_DIRECT(64, uint8_t, usart1.producer, usart1_usb.consumer);
+static struct queue const usb_to_usart1 =
+	QUEUE_DIRECT(64, uint8_t, usart1_usb.producer, usart1.consumer);
 
 static struct usart_config const usart1 =
-	USART_CONFIG(usart1_hw,
-		usart_rx_interrupt,
-		usart_tx_interrupt,
-		115200,
-		0,
-		usart1_to_usb,
-		usb_to_usart1);
-
-USB_STREAM_CONFIG(usart1_usb,
-	USB_IFACE_USART1_STREAM,
-	USB_STR_USART1_STREAM_NAME,
-	USB_EP_USART1_STREAM,
-	USB_STREAM_RX_SIZE,
-	USB_STREAM_TX_SIZE,
-	usb_to_usart1,
-	usart1_to_usb)
+	USART_CONFIG(usart1_hw, usart_rx_interrupt, usart_tx_interrupt, 115200,
+		     0, usart1_to_usb, usb_to_usart1);
 
+USB_STREAM_CONFIG(usart1_usb, USB_IFACE_USART1_STREAM,
+		  USB_STR_USART1_STREAM_NAME, USB_EP_USART1_STREAM,
+		  USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE, usb_to_usart1,
+		  usart1_to_usb)
 
 /******************************************************************************
  * Define the strings used in our USB descriptors.
  */
 const void *const usb_strings[] = {
-	[USB_STR_DESC]         = usb_string_desc,
-	[USB_STR_VENDOR]       = USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT]      = USB_STRING_DESC("Tigertail"),
-	[USB_STR_SERIALNO]     = 0,
-	[USB_STR_VERSION]      = USB_STRING_DESC(CROS_EC_VERSION32),
-	[USB_STR_I2C_NAME]     = USB_STRING_DESC("I2C"),
-	[USB_STR_USART1_STREAM_NAME]  = USB_STRING_DESC("DUT UART"),
+	[USB_STR_DESC] = usb_string_desc,
+	[USB_STR_VENDOR] = USB_STRING_DESC("Google LLC"),
+	[USB_STR_PRODUCT] = USB_STRING_DESC("Tigertail"),
+	[USB_STR_SERIALNO] = 0,
+	[USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32),
+	[USB_STR_I2C_NAME] = USB_STRING_DESC("I2C"),
+	[USB_STR_USART1_STREAM_NAME] = USB_STRING_DESC("DUT UART"),
 	[USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Tigertail Console"),
-	[USB_STR_UPDATE_NAME]  = USB_STRING_DESC("Firmware update"),
+	[USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"),
 };
 
 BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
@@ -90,30 +78,29 @@ BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
  */
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_SBU1] = {"SBU1", 3300, 4096, 0, STM32_AIN(6)},
-	[ADC_SBU2] = {"SBU2", 3300, 4096, 0, STM32_AIN(7)},
+	[ADC_SBU1] = { "SBU1", 3300, 4096, 0, STM32_AIN(6) },
+	[ADC_SBU2] = { "SBU2", 3300, 4096, 0, STM32_AIN(7) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
-
-
 /******************************************************************************
  * Support I2C bridging over USB.
  */
 
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "master",
-		.port = I2C_PORT_MASTER,
-		.kbps = 100,
-		.scl  = GPIO_MASTER_I2C_SCL,
-		.sda  = GPIO_MASTER_I2C_SDA
-	},
+	{ .name = "master",
+	  .port = I2C_PORT_MASTER,
+	  .kbps = 100,
+	  .scl = GPIO_MASTER_I2C_SCL,
+	  .sda = GPIO_MASTER_I2C_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
-int usb_i2c_board_is_enabled(void) { return 1; }
+int usb_i2c_board_is_enabled(void)
+{
+	return 1;
+}
 
 /******************************************************************************
  * Console commands.
@@ -138,7 +125,7 @@ static void set_uart_gpios(int state)
 {
 	int uart = GPIO_INPUT;
 	int dir = 0;
-	int voltage = 1;  /* 1: 1.8v, 0: 3.3v */
+	int voltage = 1; /* 1: 1.8v, 0: 3.3v */
 	int enabled = 0;
 
 	gpio_set_level(GPIO_ST_UART_LVL_DIS, 1);
@@ -287,7 +274,7 @@ void set_uart_state(int state)
  */
 void uart_sbu_tick(void)
 {
-	static int debounce;  /* = 0 */
+	static int debounce; /* = 0 */
 
 	if (uart_detect != UART_DETECT_AUTO)
 		return;
@@ -324,7 +311,7 @@ void uart_sbu_tick(void)
 }
 DECLARE_HOOK(HOOK_TICK, uart_sbu_tick, HOOK_PRIO_DEFAULT);
 
-static int command_uart(int argc, char **argv)
+static int command_uart(int argc, const char **argv)
 {
 	const char *uart_state_str = "off";
 	const char *uart_detect_str = "manual";
@@ -349,15 +336,15 @@ static int command_uart(int argc, char **argv)
 	uart_state_str = uart_state_names[uart_state];
 	if (uart_detect == UART_DETECT_AUTO)
 		uart_detect_str = "auto";
-	ccprintf("UART mux is: %s, setting: %s\n",
-		uart_state_str, uart_detect_str);
+	ccprintf("UART mux is: %s, setting: %s\n", uart_state_str,
+		 uart_detect_str);
 
 	return EC_SUCCESS;
 }
 DECLARE_CONSOLE_COMMAND(uart, command_uart,
-	"[off|on18|on33|flip18|flip33|auto]",
-	"Set the sbu uart state\n"
-	"WARNING: 3.3v may damage 1.8v devices.\n");
+			"[off|on18|on33|flip18|flip33|auto]",
+			"Set the sbu uart state\n"
+			"WARNING: 3.3v may damage 1.8v devices.\n");
 
 static void set_led_a(int r, int g, int b)
 {
@@ -422,7 +409,6 @@ void set_mux_state(int state)
 		set_led_b(1, 0, 0);
 }
 
-
 /* On button press, toggle between mux A, B, off. */
 static int button_ready = 1;
 void button_interrupt_deferred(void)
@@ -461,7 +447,7 @@ void button_interrupt(enum gpio_signal signal)
 	hook_call_deferred(&button_interrupt_deferred_data, 0);
 }
 
-static int command_mux(int argc, char **argv)
+static int command_mux(int argc, const char **argv)
 {
 	char *mux_state_str = "off";
 
@@ -484,9 +470,8 @@ static int command_mux(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(mux, command_mux,
-	"[off|A|B]",
-	"Get/set the mux and enable state of the TYPE-C mux");
+DECLARE_CONSOLE_COMMAND(mux, command_mux, "[off|A|B]",
+			"Get/set the mux and enable state of the TYPE-C mux");
 
 /******************************************************************************
  * Initialize board.
diff --git a/board/tigertail/board.h b/board/tigertail/board.h
index 3b15c4c774..ea4d11db06 100644
--- a/board/tigertail/board.h
+++ b/board/tigertail/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -40,19 +40,19 @@
 #define DEFAULT_SERIALNO "Uninitialized"
 
 /* USB interface indexes (use define rather than enum to expand them) */
-#define USB_IFACE_CONSOLE	0
-#define USB_IFACE_UPDATE	1
-#define USB_IFACE_USART1_STREAM	2
-#define USB_IFACE_I2C		3
-#define USB_IFACE_COUNT		4
+#define USB_IFACE_CONSOLE 0
+#define USB_IFACE_UPDATE 1
+#define USB_IFACE_USART1_STREAM 2
+#define USB_IFACE_I2C 3
+#define USB_IFACE_COUNT 4
 
 /* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL		0
-#define USB_EP_CONSOLE		1
-#define USB_EP_UPDATE		2
-#define USB_EP_USART1_STREAM	3
-#define USB_EP_I2C		4
-#define USB_EP_COUNT		5
+#define USB_EP_CONTROL 0
+#define USB_EP_CONSOLE 1
+#define USB_EP_UPDATE 2
+#define USB_EP_USART1_STREAM 3
+#define USB_EP_I2C 4
+#define USB_EP_COUNT 5
 
 /* Enable console recasting of GPIO type. */
 #define CONFIG_CMD_GPIO_EXTENDED
@@ -77,14 +77,11 @@
  */
 #define CONFIG_SYSTEM_UNLOCKED
 
-
 #ifndef __ASSEMBLER__
 
 /* Timer selection */
 #define TIM_CLOCK32 2
-#define TIM_ADC     3
-
-
+#define TIM_ADC 3
 
 #include "gpio_signal.h"
 
diff --git a/board/tigertail/build.mk b/board/tigertail/build.mk
index 9e7fae1c07..7766dd5e6b 100644
--- a/board/tigertail/build.mk
+++ b/board/tigertail/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/tigertail/ec.tasklist b/board/tigertail/ec.tasklist
index afdb5dedc7..c254025ebc 100644
--- a/board/tigertail/ec.tasklist
+++ b/board/tigertail/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/tigertail/gpio.inc b/board/tigertail/gpio.inc
index 107d3b2a2e..41c96cba46 100644
--- a/board/tigertail/gpio.inc
+++ b/board/tigertail/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/treeya/battery.c b/board/treeya/battery.c
index a98a38d3e9..8dce09612b 100644
--- a/board/treeya/battery.c
+++ b/board/treeya/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/treeya/board.c b/board/treeya/board.c
index 642948dbd0..9a887a9f2d 100644
--- a/board/treeya/board.c
+++ b/board/treeya/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -32,45 +32,35 @@ const enum gpio_signal hibernate_wake_pins[] = {
 	GPIO_POWER_BUTTON_L,
 	GPIO_EC_RST_ODL,
 };
-const int hibernate_wake_pins_used =  ARRAY_SIZE(hibernate_wake_pins);
+const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
 
 /* I2C port map. */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl  = GPIO_I2C0_SCL,
-		.sda  = GPIO_I2C0_SDA
-	},
-	{
-		.name = "tcpc0",
-		.port = I2C_PORT_TCPC0,
-		.kbps = 400,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	},
-	{
-		.name = "tcpc1",
-		.port = I2C_PORT_TCPC1,
-		.kbps = 400,
-		.scl  = GPIO_I2C2_SCL,
-		.sda  = GPIO_I2C2_SDA
-	},
-	{
-		.name = "thermal",
-		.port = I2C_PORT_THERMAL_AP,
-		.kbps = 400,
-		.scl  = GPIO_I2C3_SCL,
-		.sda  = GPIO_I2C3_SDA
-	},
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl  = GPIO_I2C7_SCL,
-		.sda  = GPIO_I2C7_SDA
-	},
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_I2C0_SCL,
+	  .sda = GPIO_I2C0_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "tcpc1",
+	  .port = I2C_PORT_TCPC1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
+	{ .name = "thermal",
+	  .port = I2C_PORT_THERMAL_AP,
+	  .kbps = 400,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA },
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_I2C7_SCL,
+	  .sda = GPIO_I2C7_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -83,19 +73,15 @@ static struct stprivate_data g_lis2dwl_data;
 /* Base accel private data */
 static struct lsm6dsm_data g_lsm6dsm_data = LSM6DSM_DATA;
 
-
 /* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t lsm6dsm_base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lsm6dsm_base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+						      { 0, FLOAT_TO_FP(-1), 0 },
+						      { 0, 0,
+							FLOAT_TO_FP(1) } };
 
-static const mat33_fp_t treeya_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t treeya_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+						{ FLOAT_TO_FP(1), 0, 0 },
+						{ 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t lid_accel_1 = {
 	.name = "Lid Accel",
@@ -162,8 +148,7 @@ struct motion_sensor_t base_gyro_1 = {
 	.location = MOTIONSENSE_LOC_BASE,
 	.drv = &lsm6dsm_drv,
 	.mutex = &g_base_mutex_1,
-	.drv_data = LSM6DSM_ST_DATA(g_lsm6dsm_data,
-			MOTIONSENSE_TYPE_GYRO),
+	.drv_data = LSM6DSM_ST_DATA(g_lsm6dsm_data, MOTIONSENSE_TYPE_GYRO),
 	.port = I2C_PORT_ACCEL,
 	.i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS,
 	.default_range = 1000 | ROUND_UP_FLAG, /* dps */
@@ -177,8 +162,8 @@ static int board_use_st_sensor(void)
 	/* sku_id 0xa8-0xa9, 0xbe, 0xbf use ST sensors */
 	uint32_t sku_id = system_get_sku_id();
 
-	if (sku_id == 0xa8 || sku_id == 0xa9 ||
-		sku_id == 0xbe || sku_id == 0xbf)
+	if (sku_id == 0xa8 || sku_id == 0xa9 || sku_id == 0xbe ||
+	    sku_id == 0xbf)
 		return 1;
 	else
 		return 0;
@@ -197,10 +182,12 @@ void board_update_sensor_config_from_sku(void)
 			motion_sensors[LID_ACCEL] = lid_accel_1;
 			motion_sensors[BASE_ACCEL] = base_accel_1;
 			motion_sensors[BASE_GYRO] = base_gyro_1;
-		} else{
+		} else {
 			/*Need to change matrix for treeya*/
-			motion_sensors[BASE_ACCEL].rot_standard_ref = &treeya_standard_ref;
-			motion_sensors[BASE_GYRO].rot_standard_ref = &treeya_standard_ref;
+			motion_sensors[BASE_ACCEL].rot_standard_ref =
+				&treeya_standard_ref;
+			motion_sensors[BASE_GYRO].rot_standard_ref =
+				&treeya_standard_ref;
 		}
 
 		/* Enable Gyro interrupts */
@@ -210,12 +197,11 @@ void board_update_sensor_config_from_sku(void)
 		/* Device is clamshell only */
 		tablet_set_mode(0, TABLET_TRIGGER_LID);
 		/* Gyro is not present, don't allow line to float */
-		gpio_set_flags(GPIO_6AXIS_INT_L,
-			       GPIO_INPUT | GPIO_PULL_DOWN);
+		gpio_set_flags(GPIO_6AXIS_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
 	}
 
-	if (sku_id == 160 || sku_id == 168 || sku_id == 169 ||
-			sku_id == 190 || sku_id == 191) {
+	if (sku_id == 160 || sku_id == 168 || sku_id == 169 || sku_id == 190 ||
+	    sku_id == 191) {
 		is_psl_hibernate = 0;
 	} else {
 		is_psl_hibernate = 1;
@@ -312,7 +298,7 @@ void board_hibernate_late(void)
 	}
 
 	/* Clear all pending IRQ otherwise wfi will have no affect */
-	for (i = NPCX_IRQ_0 ; i < NPCX_IRQ_COUNT ; i++)
+	for (i = NPCX_IRQ_0; i < NPCX_IRQ_COUNT; i++)
 		task_clear_pending_irq(i);
 
 	__enter_hibernate_in_psl();
diff --git a/board/treeya/board.h b/board/treeya/board.h
index e1bae50532..75c093cd71 100644
--- a/board/treeya/board.h
+++ b/board/treeya/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -30,7 +30,7 @@
  * By default, enable all console messages excepted HC, ACPI and event:
  * The sensor stack is generating a lot of activity.
  */
-#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
+#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
 #undef CONFIG_HOSTCMD_DEBUG_MODE
 #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
 
@@ -61,7 +61,7 @@
 /*
  * Slew rate on the PP1800_SENSOR load switch requires a short delay on startup.
  */
-#undef  CONFIG_MOTION_SENSE_RESUME_DELAY_US
+#undef CONFIG_MOTION_SENSE_RESUME_DELAY_US
 #define CONFIG_MOTION_SENSE_RESUME_DELAY_US (10 * MSEC)
 
 /* Second set of sensor drivers */
@@ -72,7 +72,6 @@
 
 #ifndef __ASSEMBLER__
 
-
 enum battery_type {
 	BATTERY_SMP,
 	BATTERY_LGC,
diff --git a/board/treeya/build.mk b/board/treeya/build.mk
index 250abe6712..618554c11f 100644
--- a/board/treeya/build.mk
+++ b/board/treeya/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/treeya/ec.tasklist b/board/treeya/ec.tasklist
index fb6e2f75a1..7c9bfc2aff 100644
--- a/board/treeya/ec.tasklist
+++ b/board/treeya/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/treeya/gpio.inc b/board/treeya/gpio.inc
index 70e2e1b29c..f0de3fc62c 100644
--- a/board/treeya/gpio.inc
+++ b/board/treeya/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/treeya/led.c b/board/treeya/led.c
index 9647b45e74..74d3bdef7e 100644
--- a/board/treeya/led.c
+++ b/board/treeya/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,40 +8,43 @@
 #include "led_common.h"
 #include "gpio.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
 __override const int led_charge_lvl_1 = 5;
 
 __override const int led_charge_lvl_2 = 97;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC},
-					{LED_OFF,            1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,  2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
 
 __override const struct led_descriptor
-			led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-				{LED_OFF,          0.5 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 3 * LED_ONE_SEC },
+					       { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
diff --git a/board/trembyle/battery.c b/board/trembyle/battery.c
index 33e4e9ce5d..22724f11b4 100644
--- a/board/trembyle/battery.c
+++ b/board/trembyle/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/trembyle/board.c b/board/trembyle/board.c
index ae81323902..d9d71a0895 100644
--- a/board/trembyle/board.c
+++ b/board/trembyle/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -37,8 +37,8 @@
 
 #include "gpio_list.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* Motion sensors */
 static struct mutex g_lid_mutex;
@@ -205,8 +205,8 @@ static void board_chipset_resume(void)
 		int val;
 
 		rv = i2c_read8(I2C_PORT_USBA0,
-				PS8811_I2C_ADDR_FLAGS3 + PS8811_REG_PAGE1,
-				PS8811_REG1_USB_BEQ_LEVEL, &val);
+			       PS8811_I2C_ADDR_FLAGS3 + PS8811_REG_PAGE1,
+			       PS8811_REG1_USB_BEQ_LEVEL, &val);
 		if (!rv)
 			break;
 	}
@@ -220,10 +220,10 @@ static void board_chipset_resume(void)
 		rv = i2c_write8(I2C_PORT_USBA1,
 				PS8811_I2C_ADDR_FLAGS3 + PS8811_REG_PAGE1,
 				PS8811_REG1_USB_BEQ_LEVEL,
-				(PS8811_BEQ_I2C_LEVEL_UP_13DB <<
-				PS8811_BEQ_I2C_LEVEL_UP_SHIFT) |
-				(PS8811_BEQ_PIN_LEVEL_UP_18DB <<
-				PS8811_BEQ_PIN_LEVEL_UP_SHIFT));
+				(PS8811_BEQ_I2C_LEVEL_UP_13DB
+				 << PS8811_BEQ_I2C_LEVEL_UP_SHIFT) |
+					(PS8811_BEQ_PIN_LEVEL_UP_18DB
+					 << PS8811_BEQ_PIN_LEVEL_UP_SHIFT));
 		if (!rv)
 			break;
 	}
@@ -233,9 +233,7 @@ static void board_chipset_resume(void)
 	}
 
 	if (ec_config_has_hdmi_retimer_pi3hdx1204()) {
-		pi3hdx1204_enable(I2C_PORT_TCPC1,
-				  PI3HDX1204_I2C_ADDR_FLAGS,
-				  1);
+		pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS, 1);
 	}
 }
 DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
@@ -246,9 +244,7 @@ static void board_chipset_suspend(void)
 	ioex_set_level(IOEX_USB_A1_RETIMER_EN, 0);
 
 	if (ec_config_has_hdmi_retimer_pi3hdx1204()) {
-		pi3hdx1204_enable(I2C_PORT_TCPC1,
-				  PI3HDX1204_I2C_ADDR_FLAGS,
-				  0);
+		pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS, 0);
 	}
 }
 DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
@@ -256,6 +252,10 @@ DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
 /*****************************************************************************
  * USB-C MUX/Retimer dynamic configuration
  */
+
+/* Place holder for second mux in USBC1 chain */
+struct usb_mux_chain usbc1_mux1;
+
 static void setup_mux(void)
 {
 	if (ec_config_has_usbc1_retimer_ps8802()) {
@@ -265,12 +265,10 @@ static void setup_mux(void)
 		 * Replace usb_muxes[USBC_PORT_C1] with the PS8802
 		 * table entry.
 		 */
-		memcpy(&usb_muxes[USBC_PORT_C1],
-		       &usbc1_ps8802,
-		       sizeof(struct usb_mux));
+		usb_muxes[USBC_PORT_C1].mux = &usbc1_ps8802;
 
 		/* Set the AMD FP5 as the secondary MUX */
-		usb_muxes[USBC_PORT_C1].next_mux = &usbc1_amd_fp5_usb_mux;
+		usbc1_mux1.mux = &usbc1_amd_fp5_usb_mux;
 
 		/* Don't have the AMD FP5 flip */
 		usbc1_amd_fp5_usb_mux.flags = USB_MUX_FLAG_SET_WITHOUT_FLIP;
@@ -282,12 +280,10 @@ static void setup_mux(void)
 		 * Replace usb_muxes[USBC_PORT_C1] with the AMD FP5
 		 * table entry.
 		 */
-		memcpy(&usb_muxes[USBC_PORT_C1],
-		       &usbc1_amd_fp5_usb_mux,
-		       sizeof(struct usb_mux));
+		usb_muxes[USBC_PORT_C1].mux = &usbc1_amd_fp5_usb_mux;
 
 		/* Set the PS8818 as the secondary MUX */
-		usb_muxes[USBC_PORT_C1].next_mux = &usbc1_ps8818;
+		usbc1_mux1.mux = &usbc1_ps8818;
 	}
 }
 
@@ -301,23 +297,29 @@ const struct pi3dpx1207_usb_control pi3dpx1207_controls[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(pi3dpx1207_controls) == USBC_PORT_COUNT);
 
-const struct usb_mux usbc0_pi3dpx1207_usb_retimer = {
-	.usb_port = USBC_PORT_C0,
-	.i2c_port = I2C_PORT_TCPC0,
-	.i2c_addr_flags = PI3DPX1207_I2C_ADDR_FLAGS,
-	.driver = &pi3dpx1207_usb_retimer,
+const struct usb_mux_chain usbc0_pi3dpx1207_usb_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.i2c_port = I2C_PORT_TCPC0,
+			.i2c_addr_flags = PI3DPX1207_I2C_ADDR_FLAGS,
+			.driver = &pi3dpx1207_usb_retimer,
+		},
 };
 
-struct usb_mux usb_muxes[] = {
+struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.i2c_port = I2C_PORT_USB_AP_MUX,
-		.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
-		.driver = &amd_fp5_usb_mux_driver,
-		.next_mux = &usbc0_pi3dpx1207_usb_retimer,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.i2c_port = I2C_PORT_USB_AP_MUX,
+			.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
+			.driver = &amd_fp5_usb_mux_driver,
+		},
+		.next = &usbc0_pi3dpx1207_usb_retimer,
 	},
 	[USBC_PORT_C1] = {
 		/* Filled in dynamically at startup */
+		.next = &usbc1_mux1,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
@@ -361,7 +363,7 @@ DECLARE_HOOK(HOOK_INIT, setup_fw_config, HOOK_PRIO_INIT_I2C + 2);
 /* Physical fans. These are logically separate from pwm_channels. */
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = -1,
 };
@@ -452,8 +454,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_THERMISTOR \
-	{ \
+#define THERMAL_THERMISTOR       \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(90), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(92), \
@@ -470,8 +472,8 @@ __maybe_unused static const struct ec_thermal_config thermal_thermistor =
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CPU \
-	{ \
+#define THERMAL_CPU              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(90), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(92), \
diff --git a/board/trembyle/board.h b/board/trembyle/board.h
index 6d3382af08..2e3d40ac8f 100644
--- a/board/trembyle/board.h
+++ b/board/trembyle/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -29,36 +29,32 @@
 #define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
 
 /* GPIO mapping from board specific name to EC common name. */
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_EC_BATT_PRES_ODL
-#define CONFIG_SCI_GPIO			GPIO_EC_FCH_SCI_ODL
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_AP_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT_L		GPIO_EC_EDP_BL_DISABLE
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_FCH_PWR_BTN_L
-#define GPIO_PCH_RSMRST_L		GPIO_EC_FCH_RSMRST_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S5_L		GPIO_SLP_S5_L
-#define GPIO_PCH_SYS_PWROK		GPIO_EC_FCH_PWROK
-#define GPIO_PCH_WAKE_L			GPIO_EC_FCH_WAKE_L
-#define GPIO_POWER_BUTTON_L		GPIO_EC_PWR_BTN_ODL
-#define GPIO_S0_PGOOD			GPIO_S0_PWROK_OD
-#define GPIO_S5_PGOOD			GPIO_EC_PWROK_OD
-#define GPIO_SYS_RESET_L		GPIO_EC_SYS_RST_L
-#define GPIO_VOLUME_DOWN_L		GPIO_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
+#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL
+#define CONFIG_SCI_GPIO GPIO_EC_FCH_SCI_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_AP_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_EDP_BL_DISABLE
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PCH_PWRBTN_L GPIO_EC_FCH_PWR_BTN_L
+#define GPIO_PCH_RSMRST_L GPIO_EC_FCH_RSMRST_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L
+#define GPIO_PCH_SYS_PWROK GPIO_EC_FCH_PWROK
+#define GPIO_PCH_WAKE_L GPIO_EC_FCH_WAKE_L
+#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL
+#define GPIO_S0_PGOOD GPIO_S0_PWROK_OD
+#define GPIO_S5_PGOOD GPIO_EC_PWROK_OD
+#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L
+#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
 
 #ifndef __ASSEMBLER__
 
-enum adc_channel {
-	ADC_TEMP_SENSOR_CHARGER,
-	ADC_TEMP_SENSOR_SOC,
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_TEMP_SENSOR_CHARGER, ADC_TEMP_SENSOR_SOC, ADC_CH_COUNT };
 
 enum battery_type {
 	BATTERY_AP18F4M,
@@ -71,11 +67,7 @@ enum mft_channel {
 	MFT_CH_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_FAN,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_FAN, PWM_CH_COUNT };
 
 enum temp_sensor_id {
 	TEMP_SENSOR_CHARGER = 0,
@@ -84,11 +76,7 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum usba_port {
-	USBA_PORT_A0 = 0,
-	USBA_PORT_A1,
-	USBA_PORT_COUNT
-};
+enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT };
 
 /*****************************************************************************
  * CBI EC FW Configuration
@@ -153,61 +141,51 @@ enum ec_cfg_usb_db_type {
 
 #include "cbi_ec_fw_config.h"
 
-#define HAS_USBC1_RETIMER_PS8802 \
-			(BIT(TREMBYLE_DB_T_OPT2_USBAC) | \
-			 BIT(TREMBYLE_DB_T_OPT3_USBAC_HDMI_MSTHUB))
+#define HAS_USBC1_RETIMER_PS8802         \
+	(BIT(TREMBYLE_DB_T_OPT2_USBAC) | \
+	 BIT(TREMBYLE_DB_T_OPT3_USBAC_HDMI_MSTHUB))
 
 static inline bool ec_config_has_usbc1_retimer_ps8802(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_USBC1_RETIMER_PS8802);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_USBC1_RETIMER_PS8802);
 }
 
-#define HAS_USBC1_RETIMER_PS8818 \
-			(BIT(TREMBYLE_DB_T_OPT1_USBAC_HMDI))
+#define HAS_USBC1_RETIMER_PS8818 (BIT(TREMBYLE_DB_T_OPT1_USBAC_HMDI))
 
 static inline bool ec_config_has_usbc1_retimer_ps8818(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_USBC1_RETIMER_PS8818);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_USBC1_RETIMER_PS8818);
 }
 
-#define HAS_HDMI_RETIMER_PI3HDX1204 \
-			(BIT(TREMBYLE_DB_T_OPT1_USBAC_HMDI))
+#define HAS_HDMI_RETIMER_PI3HDX1204 (BIT(TREMBYLE_DB_T_OPT1_USBAC_HMDI))
 
 static inline bool ec_config_has_hdmi_retimer_pi3hdx1204(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_HDMI_RETIMER_PI3HDX1204);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_HDMI_RETIMER_PI3HDX1204);
 }
 
-#define HAS_MST_HUB_RTD2141B \
-			(BIT(TREMBYLE_DB_T_OPT3_USBAC_HDMI_MSTHUB))
+#define HAS_MST_HUB_RTD2141B (BIT(TREMBYLE_DB_T_OPT3_USBAC_HDMI_MSTHUB))
 
 static inline bool ec_config_has_mst_hub_rtd2141b(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_MST_HUB_RTD2141B);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_MST_HUB_RTD2141B);
 }
 
-#define HAS_HDMI_CONN_HPD \
-			(BIT(TREMBYLE_DB_T_OPT1_USBAC_HMDI))
+#define HAS_HDMI_CONN_HPD (BIT(TREMBYLE_DB_T_OPT1_USBAC_HMDI))
 
 static inline bool ec_config_has_hdmi_conn_hpd(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_HDMI_CONN_HPD);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_HDMI_CONN_HPD);
 }
 
-#define PORT_TO_HPD(port) ((port == 0) \
-	? GPIO_USB_C0_HPD \
-	: (ec_config_has_usbc1_retimer_ps8802()) \
-		? GPIO_DP1_HPD \
-		: GPIO_DP2_HPD)
+#define PORT_TO_HPD(port)                                           \
+	((port == 0)				? GPIO_USB_C0_HPD : \
+	 (ec_config_has_usbc1_retimer_ps8802()) ? GPIO_DP1_HPD :    \
+						  GPIO_DP2_HPD)
 
-extern const struct usb_mux usbc0_pi3dpx1207_usb_retimer;
-extern const struct usb_mux usbc1_ps8802;
+extern const struct usb_mux_chain usbc0_pi3dpx1207_usb_retimer;
 extern const struct usb_mux usbc1_ps8818;
+extern struct usb_mux usbc1_ps8802;
 extern struct usb_mux usbc1_amd_fp5_usb_mux;
 
 void hdmi_hpd_interrupt(enum ioex_signal signal);
diff --git a/board/trembyle/build.mk b/board/trembyle/build.mk
index 4ca0cbd96f..cd58c2b91b 100644
--- a/board/trembyle/build.mk
+++ b/board/trembyle/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/trembyle/ec.tasklist b/board/trembyle/ec.tasklist
index 41b83cf4f3..4bb60ed55d 100644
--- a/board/trembyle/ec.tasklist
+++ b/board/trembyle/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/trembyle/gpio.inc b/board/trembyle/gpio.inc
index 6cc3e6fe09..7c49eef74e 100644
--- a/board/trembyle/gpio.inc
+++ b/board/trembyle/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/trembyle/led.c b/board/trembyle/led.c
index 3e2d195a06..ec4e93dca5 100644
--- a/board/trembyle/led.c
+++ b/board/trembyle/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,26 +8,34 @@
 #include "led_common.h"
 #include "led_onoff_states.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
 __override const int led_charge_lvl_1;
 __override const int led_charge_lvl_2 = 100;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]       = {{EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC},
-					{EC_LED_COLOR_RED,  2 * LED_ONE_SEC} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_RED,  LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_RED,  1 * LED_ONE_SEC},
-					{LED_OFF,           3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,           LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC},
-					{EC_LED_COLOR_RED,  2 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_BLUE,
+					     2 * LED_ONE_SEC },
+					   { EC_LED_COLOR_RED,
+					     2 * LED_ONE_SEC } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_BLUE,
+					    2 * LED_ONE_SEC },
+					  { EC_LED_COLOR_RED,
+					    2 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+	};
 BUILD_ASSERT(ARRAY_SIZE(led_bat_state_table) == LED_NUM_STATES);
 
 const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
diff --git a/board/trogdor/battery.c b/board/trogdor/battery.c
index e95735eda7..cffda632bc 100644
--- a/board/trogdor/battery.c
+++ b/board/trogdor/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/trogdor/board.c b/board/trogdor/board.c
index 7036e57c4a..863f2884b8 100644
--- a/board/trogdor/board.c
+++ b/board/trogdor/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,8 +26,8 @@
 #include "usbc_config.h"
 #include "usbc_ppc.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 #include "gpio_list.h"
 
@@ -39,10 +39,8 @@ __override struct keyboard_scan_config keyscan_config = {
 	 * Unmask 0x08 in [0] (KSO_00/KSI_03, the new location of Search key);
 	 * as it still uses the legacy location (KSO_01/KSI_00).
 	 */
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca
-	},
+	.actual_key_mask = { 0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, 0xa4,
+			     0xff, 0xfe, 0x55, 0xfa, 0xca },
 	/* Other values should be the same as the default configuration. */
 	.debounce_down_us = 9 * MSEC,
 	.debounce_up_us = 30 * MSEC,
@@ -53,41 +51,31 @@ __override struct keyboard_scan_config keyscan_config = {
 
 /* I2C port map */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl  = GPIO_EC_I2C_POWER_SCL,
-		.sda  = GPIO_EC_I2C_POWER_SDA
-	},
-	{
-		.name = "tcpc0",
-		.port = I2C_PORT_TCPC0,
-		.kbps = 1000,
-		.scl  = GPIO_EC_I2C_USB_C0_PD_SCL,
-		.sda  = GPIO_EC_I2C_USB_C0_PD_SDA
-	},
-	{
-		.name = "tcpc1",
-		.port = I2C_PORT_TCPC1,
-		.kbps = 1000,
-		.scl  = GPIO_EC_I2C_USB_C1_PD_SCL,
-		.sda  = GPIO_EC_I2C_USB_C1_PD_SDA
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_EEPROM_SCL,
-		.sda  = GPIO_EC_I2C_EEPROM_SDA
-	},
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_SENSOR_SCL,
-		.sda  = GPIO_EC_I2C_SENSOR_SDA
-	},
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_POWER_SCL,
+	  .sda = GPIO_EC_I2C_POWER_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C0_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C0_PD_SDA },
+	{ .name = "tcpc1",
+	  .port = I2C_PORT_TCPC1,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C1_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C1_PD_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_EEPROM_SCL,
+	  .sda = GPIO_EC_I2C_EEPROM_SDA },
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_SENSOR_SCL,
+	  .sda = GPIO_EC_I2C_SENSOR_SDA },
 };
 
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
@@ -95,37 +83,22 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* Measure VBUS through a 1/10 voltage divider */
-	[ADC_VBUS] = {
-		"VBUS",
-		NPCX_ADC_CH1,
-		ADC_MAX_VOLT * 10,
-		ADC_READ_MAX + 1,
-		0
-	},
+	[ADC_VBUS] = { "VBUS", NPCX_ADC_CH1, ADC_MAX_VOLT * 10,
+		       ADC_READ_MAX + 1, 0 },
 	/*
 	 * Adapter current output or battery charging/discharging current (uV)
 	 * 18x amplification on charger side.
 	 */
-	[ADC_AMON_BMON] = {
-		"AMON_BMON",
-		NPCX_ADC_CH2,
-		ADC_MAX_VOLT * 1000 / 18,
-		ADC_READ_MAX + 1,
-		0
-	},
+	[ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH2, ADC_MAX_VOLT * 1000 / 18,
+			    ADC_READ_MAX + 1, 0 },
 	/*
 	 * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read
 	 * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and
 	 * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we
 	 * only divide by 2 (enough to avoid precision issues).
 	 */
-	[ADC_PSYS] = {
-		"PSYS",
-		NPCX_ADC_CH3,
-		ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1),
-		2,
-		0
-	},
+	[ADC_PSYS] = { "PSYS", NPCX_ADC_CH3,
+		       ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), 2, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
@@ -177,17 +150,13 @@ static struct bmi_drv_data_t g_bmi160_data;
 static struct accelgyro_saved_data_t g_bma255_data;
 
 /* Matrix to rotate accelerometer into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(1), 0,  0},
-	{ 0,  FLOAT_TO_FP(-1),  0},
-	{ 0,  0, FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+				       { 0, FLOAT_TO_FP(-1), 0 },
+				       { 0, 0, FLOAT_TO_FP(-1) } };
 
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					     { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
diff --git a/board/trogdor/board.h b/board/trogdor/board.h
index 0faa3a8bf0..2c8e67d26b 100644
--- a/board/trogdor/board.h
+++ b/board/trogdor/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,7 +19,7 @@
 #define CONFIG_I2C_DEBUG
 
 /* Internal SPI flash on NPCX7 */
-#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)  /* 512KB internal spi flash */
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */
 
 /* Keyboard */
 #define CONFIG_KEYBOARD_PROTOCOL_MKBP
@@ -27,7 +27,7 @@
 #define CONFIG_PWM_KBLIGHT
 
 /* Battery */
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY  "LION"
+#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
 #define CONFIG_BATTERY_REVIVE_DISCONNECT
 #define CONFIG_BATTERY_FUEL_GAUGE
 
@@ -74,12 +74,7 @@
 #include "gpio_signal.h"
 #include "registers.h"
 
-enum adc_channel {
-	ADC_VBUS,
-	ADC_AMON_BMON,
-	ADC_PSYS,
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_VBUS, ADC_AMON_BMON, ADC_PSYS, ADC_CH_COUNT };
 
 /* Motion sensors */
 enum sensor_id {
@@ -89,11 +84,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_DISPLIGHT,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_DISPLIGHT, PWM_CH_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
diff --git a/board/trogdor/build.mk b/board/trogdor/build.mk
index 7fe4452669..becaf09262 100644
--- a/board/trogdor/build.mk
+++ b/board/trogdor/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/trogdor/ec.tasklist b/board/trogdor/ec.tasklist
index eb14fab204..97b5046f7f 100644
--- a/board/trogdor/ec.tasklist
+++ b/board/trogdor/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/trogdor/gpio.inc b/board/trogdor/gpio.inc
index aaac15839e..63d6e84963 100644
--- a/board/trogdor/gpio.inc
+++ b/board/trogdor/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/trogdor/hibernate.c b/board/trogdor/hibernate.c
index 504a295463..9b64e85053 100644
--- a/board/trogdor/hibernate.c
+++ b/board/trogdor/hibernate.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,6 @@ void board_hibernate(void)
 	 * Sensors are unpowered in hibernate. Apply PD to the
 	 * interrupt lines such that they don't float.
 	 */
-	gpio_set_flags(GPIO_ACCEL_GYRO_INT_L,
-		       GPIO_INPUT | GPIO_PULL_DOWN);
-	gpio_set_flags(GPIO_LID_ACCEL_INT_L,
-		       GPIO_INPUT | GPIO_PULL_DOWN);
+	gpio_set_flags(GPIO_ACCEL_GYRO_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
+	gpio_set_flags(GPIO_LID_ACCEL_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
 }
diff --git a/board/trogdor/led.c b/board/trogdor/led.c
index 3af5776e12..3a7d8df108 100644
--- a/board/trogdor/led.c
+++ b/board/trogdor/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -31,15 +31,15 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static void side_led_set_color(int port, enum led_color color)
 {
 	gpio_set_level(port ? GPIO_EC_CHG_LED_Y_C1 : GPIO_EC_CHG_LED_Y_C0,
-		(color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
+		       (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF);
 	gpio_set_level(port ? GPIO_EC_CHG_LED_W_C1 : GPIO_EC_CHG_LED_W_C0,
-		(color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF);
+		       (color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF);
 }
 
 void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
@@ -90,7 +90,6 @@ static void set_active_port_color(enum led_color color)
 static void board_led_set_battery(void)
 {
 	static int battery_ticks;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
@@ -102,8 +101,9 @@ static void board_led_set_battery(void)
 	case PWR_STATE_DISCHARGE:
 		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
 			if (charge_get_percent() <= 10)
-				side_led_set_color(0,
-				   (battery_ticks & 0x4) ? LED_WHITE : LED_OFF);
+				side_led_set_color(0, (battery_ticks & 0x4) ?
+							      LED_WHITE :
+							      LED_OFF);
 			else
 				side_led_set_color(0, LED_OFF);
 		}
@@ -112,18 +112,18 @@ static void board_led_set_battery(void)
 			side_led_set_color(1, LED_OFF);
 		break;
 	case PWR_STATE_ERROR:
-		set_active_port_color((battery_ticks & 0x2) ?
-				LED_WHITE : LED_OFF);
+		set_active_port_color((battery_ticks & 0x2) ? LED_WHITE :
+							      LED_OFF);
 		break;
 	case PWR_STATE_CHARGE_NEAR_FULL:
 		set_active_port_color(LED_WHITE);
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			set_active_port_color((battery_ticks & 0x4) ?
-					LED_AMBER : LED_OFF);
-		else
-			set_active_port_color(LED_WHITE);
+		set_active_port_color(LED_WHITE);
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		set_active_port_color((battery_ticks & 0x4) ? LED_AMBER :
+							      LED_OFF);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
diff --git a/board/trogdor/switchcap.c b/board/trogdor/switchcap.c
index 16b0db6ef6..5173e27f75 100644
--- a/board/trogdor/switchcap.c
+++ b/board/trogdor/switchcap.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/trogdor/usbc_config.c b/board/trogdor/usbc_config.c
index a25b63bff9..39a54f659e 100644
--- a/board/trogdor/usbc_config.c
+++ b/board/trogdor/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,8 +25,8 @@
 #include "usbc_ocp.h"
 #include "usbc_ppc.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 const struct charger_config_t chg_chips[] = {
 	{
@@ -132,16 +132,12 @@ void ppc_interrupt(enum gpio_signal signal)
 
 /* Power Path Controller */
 struct ppc_config_t ppc_chips[] = {
-	{
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	{
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
+	{ .i2c_port = I2C_PORT_TCPC0,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
+	{ .i2c_port = I2C_PORT_TCPC1,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
 };
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
@@ -172,16 +168,22 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
  * to AP. But the TCPC chip is also needed to know the HPD status; otherwise,
  * the mux misbehaves.
  */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	},
 	{
-		.usb_port = 1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	}
 };
 
@@ -234,7 +236,7 @@ void board_tcpc_init(void)
 	 */
 	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
 		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
 DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
 
@@ -280,8 +282,7 @@ void board_overcurrent_event(int port, int is_overcurrented)
 
 int board_set_active_charge_port(int port)
 {
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	int i;
 
 	if (!is_real_port && port != CHARGE_PORT_NONE)
@@ -309,7 +310,6 @@ int board_set_active_charge_port(int port)
 		return EC_ERROR_INVAL;
 	}
 
-
 	CPRINTS("New charge port: p%d", port);
 
 	/*
@@ -333,23 +333,21 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	/*
 	 * Ignore lower charge ceiling on PD transition if our battery is
 	 * critical, as we may brownout.
 	 */
-	if (supplier == CHARGE_SUPPLIER_PD &&
-	    charge_ma < 1500 &&
+	if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 &&
 	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
 		CPRINTS("Using max ilim %d", max_ma);
 		charge_ma = max_ma;
 	}
 
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 uint16_t tcpc_get_alert_status(void)
diff --git a/board/trogdor/usbc_config.h b/board/trogdor/usbc_config.h
index 75adf93b3c..c9b676fc61 100644
--- a/board/trogdor/usbc_config.h
+++ b/board/trogdor/usbc_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/twinkie/board.c b/board/twinkie/board.c
index f3f8460c8d..97c69fb126 100644
--- a/board/twinkie/board.c
+++ b/board/twinkie/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -36,7 +36,7 @@ void board_config_pre_init(void)
 	STM32_RCC_APB2ENR |= BIT(0);
 	/* Remap USART DMA to match the USART driver and TIM2 DMA */
 	STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10) /* Remap USART1 RX/TX DMA */
-			   |  BIT(29);/* Remap TIM2 DMA */
+			      | BIT(29); /* Remap TIM2 DMA */
 	/* 40 MHz pin speed on UART PA9/PA10 */
 	STM32_GPIO_OSPEEDR(GPIO_A) |= 0x003C0000;
 	/* 40 MHz pin speed on TX clock out PB9 */
@@ -59,26 +59,24 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* USB PD CC lines sensing. Converted to mV (3300mV/4096). */
-	[ADC_CH_CC1_PD] = {"CC1_PD", 3300, 4096, 0, STM32_AIN(1)},
-	[ADC_CH_CC2_PD] = {"CC2_PD", 3300, 4096, 0, STM32_AIN(3)},
+	[ADC_CH_CC1_PD] = { "CC1_PD", 3300, 4096, 0, STM32_AIN(1) },
+	[ADC_CH_CC2_PD] = { "CC2_PD", 3300, 4096, 0, STM32_AIN(3) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "master",
-		.port = I2C_PORT_MASTER,
-		.kbps = 100,
-		.scl  = GPIO_I2C_SCL,
-		.sda  = GPIO_I2C_SDA
-	},
+	{ .name = "master",
+	  .port = I2C_PORT_MASTER,
+	  .kbps = 100,
+	  .scl = GPIO_I2C_SCL,
+	  .sda = GPIO_I2C_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
-const void * const usb_strings[] = {
+const void *const usb_strings[] = {
 	[USB_STR_DESC] = usb_string_desc,
-	[USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."),
+	[USB_STR_VENDOR] = USB_STRING_DESC("Google LLC"),
 	[USB_STR_PRODUCT] = USB_STRING_DESC("Twinkie"),
 	[USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32),
 	[USB_STR_SNIFFER] = USB_STRING_DESC("USB-PD Sniffer"),
diff --git a/board/twinkie/board.h b/board/twinkie/board.h
index 3d601ee979..b1379fb15b 100644
--- a/board/twinkie/board.h
+++ b/board/twinkie/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -54,7 +54,7 @@
 /* USB configuration */
 #define CONFIG_USB_PID 0x500A
 /* By default, enable all console messages excepted USB */
-#define CC_DEFAULT     (CC_ALL & ~CC_MASK(CC_USB))
+#define CC_DEFAULT (CC_ALL & ~CC_MASK(CC_USB))
 
 /*
  * Allow dangerous commands all the time, since we don't have a write protect
@@ -79,9 +79,9 @@ void trace_packets(void);
 void set_trace_mode(int mode);
 
 /* Timer selection */
-#define TIM_CLOCK_MSB  3
+#define TIM_CLOCK_MSB 3
 #define TIM_CLOCK_LSB 15
-#define TIM_ADC       16
+#define TIM_ADC 16
 
 #include "gpio_signal.h"
 
@@ -106,28 +106,28 @@ enum usb_strings {
 };
 
 /* Standard-current Rp */
-#define PD_SRC_VNC           PD_SRC_DEF_VNC_MV
-#define PD_SRC_RD_THRESHOLD  PD_SRC_DEF_RD_THRESH_MV
+#define PD_SRC_VNC PD_SRC_DEF_VNC_MV
+#define PD_SRC_RD_THRESHOLD PD_SRC_DEF_RD_THRESH_MV
 
 /* delay necessary for the voltage transition on the power supply */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  50000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 50000 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 50000 /* us */
 
 /* Define typical operating power and max power */
 #define PD_OPERATING_POWER_MW 15000
-#define PD_MAX_POWER_MW       60000
-#define PD_MAX_CURRENT_MA     3000
-#define PD_MAX_VOLTAGE_MV     20000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 #endif /* !__ASSEMBLER__ */
 
 /* USB interface indexes (use define rather than enum to expand them) */
 #define USB_IFACE_CONSOLE 0
-#define USB_IFACE_VENDOR  1
+#define USB_IFACE_VENDOR 1
 
 /* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL   0
-#define USB_EP_CONSOLE   1
+#define USB_EP_CONTROL 0
+#define USB_EP_CONSOLE 1
 
 /*
  * Endpoint 2 is missing because the console used to use two bidirectional
@@ -137,13 +137,13 @@ enum usb_strings {
  */
 
 #ifdef HAS_TASK_SNIFFER
-#define USB_EP_SNIFFER   3
-#define USB_EP_COUNT     4
-#define USB_IFACE_COUNT  2
+#define USB_EP_SNIFFER 3
+#define USB_EP_COUNT 4
+#define USB_IFACE_COUNT 2
 #else
-#define USB_EP_COUNT     2
+#define USB_EP_COUNT 2
 /* No IFACE_VENDOR for the sniffer */
-#define USB_IFACE_COUNT  1
+#define USB_IFACE_COUNT 1
 #endif
 
 #endif /* __CROS_EC_BOARD_H */
diff --git a/board/twinkie/build.mk b/board/twinkie/build.mk
index 3ced5f2966..f710000486 100644
--- a/board/twinkie/build.mk
+++ b/board/twinkie/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
+# Copyright 2014 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/twinkie/ec.tasklist b/board/twinkie/ec.tasklist
index 600df47c60..0dcfd38308 100644
--- a/board/twinkie/ec.tasklist
+++ b/board/twinkie/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/twinkie/gpio.inc b/board/twinkie/gpio.inc
index 551cb73748..45b34de766 100644
--- a/board/twinkie/gpio.inc
+++ b/board/twinkie/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
+ * Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/twinkie/injector.c b/board/twinkie/injector.c
index ef5bfb3e32..7688b68128 100644
--- a/board/twinkie/injector.c
+++ b/board/twinkie/injector.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -48,20 +48,25 @@ static const struct res_cfg {
 		uint32_t flags;
 	} cfgs[2];
 } res_cfg[] = {
-	[INJ_RES_NONE]  = {"NONE"},
-	[INJ_RES_RA]    = {"RA", {{GPIO_CC1_RA, GPIO_ODR_LOW},
-				  {GPIO_CC2_RA, GPIO_ODR_LOW} } },
-	[INJ_RES_RD]    = {"RD", {{GPIO_CC1_RD, GPIO_ODR_LOW},
-				  {GPIO_CC2_RD, GPIO_ODR_LOW} } },
-	[INJ_RES_RPUSB] = {"RPUSB", {{GPIO_CC1_RPUSB, GPIO_OUT_HIGH},
-				     {GPIO_CC2_RPUSB, GPIO_OUT_HIGH} } },
-	[INJ_RES_RP1A5] = {"RP1A5", {{GPIO_CC1_RP1A5, GPIO_OUT_HIGH},
-				     {GPIO_CC2_RP1A5, GPIO_OUT_HIGH} } },
-	[INJ_RES_RP3A0] = {"RP3A0", {{GPIO_CC1_RP3A0, GPIO_OUT_HIGH},
-				     {GPIO_CC2_RP3A0, GPIO_OUT_HIGH} } },
+	[INJ_RES_NONE] = { "NONE" },
+	[INJ_RES_RA] = { "RA",
+			 { { GPIO_CC1_RA, GPIO_ODR_LOW },
+			   { GPIO_CC2_RA, GPIO_ODR_LOW } } },
+	[INJ_RES_RD] = { "RD",
+			 { { GPIO_CC1_RD, GPIO_ODR_LOW },
+			   { GPIO_CC2_RD, GPIO_ODR_LOW } } },
+	[INJ_RES_RPUSB] = { "RPUSB",
+			    { { GPIO_CC1_RPUSB, GPIO_OUT_HIGH },
+			      { GPIO_CC2_RPUSB, GPIO_OUT_HIGH } } },
+	[INJ_RES_RP1A5] = { "RP1A5",
+			    { { GPIO_CC1_RP1A5, GPIO_OUT_HIGH },
+			      { GPIO_CC2_RP1A5, GPIO_OUT_HIGH } } },
+	[INJ_RES_RP3A0] = { "RP3A0",
+			    { { GPIO_CC1_RP3A0, GPIO_OUT_HIGH },
+			      { GPIO_CC2_RP3A0, GPIO_OUT_HIGH } } },
 };
 
-#define CC_RA(cc)  (cc < PD_SRC_RD_THRESHOLD)
+#define CC_RA(cc) (cc < PD_SRC_RD_THRESHOLD)
 #define CC_RD(cc) ((cc > PD_SRC_RD_THRESHOLD) && (cc < PD_SRC_VNC))
 #define GET_POLARITY(cc1, cc2) (CC_RD(cc2) || CC_RA(cc1))
 
@@ -103,8 +108,8 @@ static inline void enable_tracing_ifneeded(int flag)
 		pd_rx_enable_monitoring(0);
 }
 
-static int send_message(int polarity, uint16_t header,
-			uint8_t cnt, const uint32_t *data)
+static int send_message(int polarity, uint16_t header, uint8_t cnt,
+			const uint32_t *data)
 {
 	int bit_len;
 
@@ -215,7 +220,7 @@ static void fsm_wait(uint32_t w)
 	uint32_t timeout_ms = INJ_ARG0(w);
 	uint32_t min_edges = INJ_ARG12(w);
 
-	wait_packet(inj_polarity,  min_edges, timeout_ms * 1000);
+	wait_packet(inj_polarity, min_edges, timeout_ms * 1000);
 #endif
 }
 
@@ -224,7 +229,7 @@ static void fsm_expect(uint32_t w)
 	uint32_t timeout_ms = INJ_ARG0(w);
 	uint8_t cmd = INJ_ARG2(w);
 
-	expect_packet(inj_polarity,  cmd, timeout_ms * 1000);
+	expect_packet(inj_polarity, cmd, timeout_ms * 1000);
 }
 static void fsm_get(uint32_t w)
 {
@@ -242,11 +247,11 @@ static void fsm_get(uint32_t w)
 		break;
 	case INJ_GET_VBUS:
 		*store_ptr = (ina2xx_get_voltage(0) & 0xffff) |
-			 ((ina2xx_get_current(0) & 0xffff) << 16);
+			     ((ina2xx_get_current(0) & 0xffff) << 16);
 		break;
 	case INJ_GET_VCONN:
 		*store_ptr = (ina2xx_get_voltage(1) & 0xffff) |
-			 ((ina2xx_get_current(1) & 0xffff) << 16);
+			     ((ina2xx_get_current(1) & 0xffff) << 16);
 		break;
 	case INJ_GET_POLARITY:
 		*store_ptr = inj_polarity;
@@ -336,9 +341,9 @@ static int fsm_run(int index)
 
 /* ------ Console commands ------ */
 
-static int hex8tou32(char *str, uint32_t *val)
+static int hex8tou32(const char *str, uint32_t *val)
 {
-	char *ptr = str;
+	const char *ptr = str;
 	uint32_t tmp = 0;
 
 	while (*ptr) {
@@ -358,7 +363,7 @@ static int hex8tou32(char *str, uint32_t *val)
 	return EC_SUCCESS;
 }
 
-static int cmd_fsm(int argc, char **argv)
+static int cmd_fsm(int argc, const char **argv)
 {
 	int index;
 	char *e;
@@ -375,8 +380,7 @@ static int cmd_fsm(int argc, char **argv)
 	return EC_SUCCESS;
 }
 
-
-static int cmd_send(int argc, char **argv)
+static int cmd_send(int argc, const char **argv)
 {
 	int pol, cnt, i;
 	uint16_t header;
@@ -396,7 +400,7 @@ static int cmd_send(int argc, char **argv)
 		return EC_ERROR_PARAM3;
 
 	for (i = 0; i < cnt; i++)
-		if (hex8tou32(argv[i+2], data + i))
+		if (hex8tou32(argv[i + 2], data + i))
 			return EC_ERROR_INVAL;
 
 	bit_len = send_message(pol, header, cnt, data);
@@ -405,15 +409,15 @@ static int cmd_send(int argc, char **argv)
 	return EC_SUCCESS;
 }
 
-static int cmd_cc_level(int argc, char **argv)
+static int cmd_cc_level(int argc, const char **argv)
 {
-	ccprintf("CC1 = %d mV ; CC2 = %d mV\n",
-		pd_adc_read(0, 0), pd_adc_read(0, 1));
+	ccprintf("CC1 = %d mV ; CC2 = %d mV\n", pd_adc_read(0, 0),
+		 pd_adc_read(0, 1));
 
 	return EC_SUCCESS;
 }
 
-static int cmd_resistor(int argc, char **argv)
+static int cmd_resistor(int argc, const char **argv)
 {
 	int p, r;
 
@@ -435,7 +439,7 @@ static int cmd_resistor(int argc, char **argv)
 	return EC_SUCCESS;
 }
 
-static int cmd_tx_clock(int argc, char **argv)
+static int cmd_tx_clock(int argc, const char **argv)
 {
 	int freq;
 	char *e;
@@ -452,7 +456,7 @@ static int cmd_tx_clock(int argc, char **argv)
 	return EC_SUCCESS;
 }
 
-static int cmd_rx_threshold(int argc, char **argv)
+static int cmd_rx_threshold(int argc, const char **argv)
 {
 	int mv;
 	char *e;
@@ -471,7 +475,7 @@ static int cmd_rx_threshold(int argc, char **argv)
 	return EC_SUCCESS;
 }
 
-static int cmd_ina_dump(int argc, char **argv, int index)
+static int cmd_ina_dump(int argc, const char **argv, int index)
 {
 	if (index == 1) { /* VCONN INA is off by default, switch it on */
 		ina2xx_write(index, INA2XX_REG_CONFIG, 0x4123);
@@ -483,7 +487,7 @@ static int cmd_ina_dump(int argc, char **argv, int index)
 	}
 
 	ccprintf("%s = %d mV ; %d mA\n", index == 0 ? "VBUS" : "VCONN",
-		ina2xx_get_voltage(index), ina2xx_get_current(index));
+		 ina2xx_get_voltage(index), ina2xx_get_current(index));
 
 	if (index == 1) /* power off VCONN INA */
 		ina2xx_write(index, INA2XX_REG_CONFIG, 0);
@@ -491,7 +495,7 @@ static int cmd_ina_dump(int argc, char **argv, int index)
 	return EC_SUCCESS;
 }
 
-static int cmd_bufwr(int argc, char **argv)
+static int cmd_bufwr(int argc, const char **argv)
 {
 	int idx, cnt, i;
 	char *e;
@@ -505,13 +509,13 @@ static int cmd_bufwr(int argc, char **argv)
 		return EC_ERROR_PARAM2;
 
 	for (i = 0; i < cnt; i++)
-		if (hex8tou32(argv[i+1], inj_cmds + idx + i))
+		if (hex8tou32(argv[i + 1], inj_cmds + idx + i))
 			return EC_ERROR_INVAL;
 
 	return EC_SUCCESS;
 }
 
-static int cmd_bufrd(int argc, char **argv)
+static int cmd_bufrd(int argc, const char **argv)
 {
 	int idx, i;
 	int cnt = 1;
@@ -537,7 +541,7 @@ static int cmd_bufrd(int argc, char **argv)
 	return EC_SUCCESS;
 }
 
-static int cmd_sink(int argc, char **argv)
+static int cmd_sink(int argc, const char **argv)
 {
 	/*
 	 * Jump to the RW section which should contain a firmware acting
@@ -548,18 +552,16 @@ static int cmd_sink(int argc, char **argv)
 	return EC_SUCCESS;
 }
 
-static int cmd_trace(int argc, char **argv)
+static int cmd_trace(int argc, const char **argv)
 {
 	if (argc < 1)
 		return EC_ERROR_PARAM_COUNT;
 
-	if (!strcasecmp(argv[0], "on") ||
-	    !strcasecmp(argv[0], "1"))
+	if (!strcasecmp(argv[0], "on") || !strcasecmp(argv[0], "1"))
 		set_trace_mode(TRACE_MODE_ON);
 	else if (!strcasecmp(argv[0], "raw"))
 		set_trace_mode(TRACE_MODE_RAW);
-	else if (!strcasecmp(argv[0], "off") ||
-		 !strcasecmp(argv[0], "0"))
+	else if (!strcasecmp(argv[0], "off") || !strcasecmp(argv[0], "0"))
 		set_trace_mode(TRACE_MODE_OFF);
 	else
 		return EC_ERROR_PARAM2;
@@ -567,7 +569,7 @@ static int cmd_trace(int argc, char **argv)
 	return EC_SUCCESS;
 }
 
-static int command_tw(int argc, char **argv)
+static int command_tw(int argc, const char **argv)
 {
 	if (!strcasecmp(argv[1], "send"))
 		return cmd_send(argc - 2, argv + 2);
diff --git a/board/twinkie/injector.h b/board/twinkie/injector.h
index 4a33f8ecf0..ed39522969 100644
--- a/board/twinkie/injector.h
+++ b/board/twinkie/injector.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,50 +21,50 @@
 
 /* Macros to extract values from FSM command words */
 #define INJ_CMD(w) ((w) >> 28)
-#define INJ_ARG(w) ((w) & 0x0FFFFFFF)
-#define INJ_ARG0(w) ((w) & 0x0000FFFF)
+#define INJ_ARG(w) ((w)&0x0FFFFFFF)
+#define INJ_ARG0(w) ((w)&0x0000FFFF)
 #define INJ_ARG1(w) (((w) >> 16) & 0xFF)
 #define INJ_ARG2(w) (((w) >> 24) & 0xF)
 #define INJ_ARG12(w) (((w) >> 16) & 0xFFF)
 
 enum inj_cmd {
-	INJ_CMD_END   = 0x0, /* stop the FSM */
-	INJ_CMD_SEND  = 0x1, /* Send message on CCx */
-			     /* arg0: header arg1/2:payload index/count  */
-	INJ_CMD_WAVE  = 0x2, /* Send arbitrary waveform */
-			     /* stored at index arg1 of len arg0 */
-	INJ_CMD_HRST  = 0x3, /* Send Hard Reset on CCx */
-	INJ_CMD_WAIT  = 0x4, /* Wait for arg12 edges if arg12 != 0 */
-			     /* and timeout after arg0 ms */
-	INJ_CMD_GET   = 0x5, /* Get parameter arg1 (INJ_GET_x) at index arg0 */
-	INJ_CMD_SET   = 0x6, /* Set parameter arg1 (INJ_SET_x) with arg0 */
-	INJ_CMD_JUMP  = 0x8, /* Jump to index (as arg0) */
+	INJ_CMD_END = 0x0, /* stop the FSM */
+	INJ_CMD_SEND = 0x1, /* Send message on CCx */
+	/* arg0: header arg1/2:payload index/count  */
+	INJ_CMD_WAVE = 0x2, /* Send arbitrary waveform */
+	/* stored at index arg1 of len arg0 */
+	INJ_CMD_HRST = 0x3, /* Send Hard Reset on CCx */
+	INJ_CMD_WAIT = 0x4, /* Wait for arg12 edges if arg12 != 0 */
+	/* and timeout after arg0 ms */
+	INJ_CMD_GET = 0x5, /* Get parameter arg1 (INJ_GET_x) at index arg0 */
+	INJ_CMD_SET = 0x6, /* Set parameter arg1 (INJ_SET_x) with arg0 */
+	INJ_CMD_JUMP = 0x8, /* Jump to index (as arg0) */
 	INJ_CMD_EXPCT = 0xC, /* Expect a packet with command arg2 */
-			     /* and timeout after arg0 ms */
-	INJ_CMD_NOP   = 0xF, /* No-Operation */
+	/* and timeout after arg0 ms */
+	INJ_CMD_NOP = 0xF, /* No-Operation */
 };
 
 enum inj_set {
-	INJ_SET_RESISTOR1  = 0, /* CC1 resistor as arg0 (INJ_RES_x) */
-	INJ_SET_RESISTOR2  = 1, /* CC2 resistor as arg0 (INJ_RES_x) */
-	INJ_SET_RECORD     = 2, /* Recording on/off */
-	INJ_SET_TX_SPEED   = 3, /* TX frequency is arg0 kHz */
-	INJ_SET_RX_THRESH  = 4, /* RX voltage threshold is arg0 mV */
-	INJ_SET_POLARITY   = 5, /* Polarity for other operations (INJ_POL_CC) */
-	INJ_SET_TRACE      = 6, /* Text packet trace on/raw/off */
+	INJ_SET_RESISTOR1 = 0, /* CC1 resistor as arg0 (INJ_RES_x) */
+	INJ_SET_RESISTOR2 = 1, /* CC2 resistor as arg0 (INJ_RES_x) */
+	INJ_SET_RECORD = 2, /* Recording on/off */
+	INJ_SET_TX_SPEED = 3, /* TX frequency is arg0 kHz */
+	INJ_SET_RX_THRESH = 4, /* RX voltage threshold is arg0 mV */
+	INJ_SET_POLARITY = 5, /* Polarity for other operations (INJ_POL_CC) */
+	INJ_SET_TRACE = 6, /* Text packet trace on/raw/off */
 };
 
 enum inj_get {
-	INJ_GET_CC       = 0,  /* CC1/CC2 voltages in mV */
-	INJ_GET_VBUS     = 1,  /* VBUS voltage in mV and current in mA */
-	INJ_GET_VCONN    = 2, /* VCONN voltage in mV and current in mA */
+	INJ_GET_CC = 0, /* CC1/CC2 voltages in mV */
+	INJ_GET_VBUS = 1, /* VBUS voltage in mV and current in mA */
+	INJ_GET_VCONN = 2, /* VCONN voltage in mV and current in mA */
 	INJ_GET_POLARITY = 3, /* Current polarity (INJ_POL_CC) */
 };
 
 enum inj_res {
-	INJ_RES_NONE  = 0,
-	INJ_RES_RA    = 1,
-	INJ_RES_RD    = 2,
+	INJ_RES_NONE = 0,
+	INJ_RES_RA = 1,
+	INJ_RES_RD = 2,
 	INJ_RES_RPUSB = 3,
 	INJ_RES_RP1A5 = 4,
 	INJ_RES_RP3A0 = 5,
@@ -79,7 +79,7 @@ enum inj_pol {
 enum trace_mode {
 	TRACE_MODE_OFF = 0,
 	TRACE_MODE_RAW = 1,
-	TRACE_MODE_ON  = 2,
+	TRACE_MODE_ON = 2,
 };
 
 /* Number of words in the FSM command/data buffer  */
diff --git a/board/twinkie/simpletrace.c b/board/twinkie/simpletrace.c
index 811bd428fd..fdc4cbfbb2 100644
--- a/board/twinkie/simpletrace.c
+++ b/board/twinkie/simpletrace.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,6 +11,7 @@
 #include "hooks.h"
 #include "hwtimer.h"
 #include "injector.h"
+#include "printf.h"
 #include "registers.h"
 #include "system.h"
 #include "task.h"
@@ -25,61 +26,57 @@ int trace_mode;
 /* The FSM is waiting for the following command (0 == None) */
 uint8_t expected_cmd;
 
-static const char * const ctrl_msg_name[] = {
-	[0]                      = "RSVD-C0",
-	[PD_CTRL_GOOD_CRC]       = "GOODCRC",
-	[PD_CTRL_GOTO_MIN]       = "GOTOMIN",
-	[PD_CTRL_ACCEPT]         = "ACCEPT",
-	[PD_CTRL_REJECT]         = "REJECT",
-	[PD_CTRL_PING]           = "PING",
-	[PD_CTRL_PS_RDY]         = "PSRDY",
+static const char *const ctrl_msg_name[] = {
+	[0] = "RSVD-C0",
+	[PD_CTRL_GOOD_CRC] = "GOODCRC",
+	[PD_CTRL_GOTO_MIN] = "GOTOMIN",
+	[PD_CTRL_ACCEPT] = "ACCEPT",
+	[PD_CTRL_REJECT] = "REJECT",
+	[PD_CTRL_PING] = "PING",
+	[PD_CTRL_PS_RDY] = "PSRDY",
 	[PD_CTRL_GET_SOURCE_CAP] = "GSRCCAP",
-	[PD_CTRL_GET_SINK_CAP]   = "GSNKCAP",
-	[PD_CTRL_DR_SWAP]        = "DRSWAP",
-	[PD_CTRL_PR_SWAP]        = "PRSWAP",
-	[PD_CTRL_VCONN_SWAP]     = "VCONNSW",
-	[PD_CTRL_WAIT]           = "WAIT",
-	[PD_CTRL_SOFT_RESET]     = "SFT-RST",
-	[14]                     = "RSVD-C14",
-	[15]                     = "RSVD-C15",
+	[PD_CTRL_GET_SINK_CAP] = "GSNKCAP",
+	[PD_CTRL_DR_SWAP] = "DRSWAP",
+	[PD_CTRL_PR_SWAP] = "PRSWAP",
+	[PD_CTRL_VCONN_SWAP] = "VCONNSW",
+	[PD_CTRL_WAIT] = "WAIT",
+	[PD_CTRL_SOFT_RESET] = "SFT-RST",
+	[14] = "RSVD-C14",
+	[15] = "RSVD-C15",
 };
 
-static const char * const data_msg_name[] = {
-	[0]                      = "RSVD-D0",
-	[PD_DATA_SOURCE_CAP]     = "SRCCAP",
-	[PD_DATA_REQUEST]        = "REQUEST",
-	[PD_DATA_BIST]           = "BIST",
-	[PD_DATA_SINK_CAP]       = "SNKCAP",
+static const char *const data_msg_name[] = {
+	[0] = "RSVD-D0",
+	[PD_DATA_SOURCE_CAP] = "SRCCAP",
+	[PD_DATA_REQUEST] = "REQUEST",
+	[PD_DATA_BIST] = "BIST",
+	[PD_DATA_SINK_CAP] = "SNKCAP",
 	/* 5-14 Reserved */
-	[PD_DATA_VENDOR_DEF]     = "VDM",
+	[PD_DATA_VENDOR_DEF] = "VDM",
 };
 
-static const char * const svdm_cmd_name[] = {
-	[CMD_DISCOVER_IDENT]     = "DISCID",
-	[CMD_DISCOVER_SVID]	 = "DISCSVID",
-	[CMD_DISCOVER_MODES]	 = "DISCMODE",
-	[CMD_ENTER_MODE]	 = "ENTER",
-	[CMD_EXIT_MODE]		 = "EXIT",
-	[CMD_ATTENTION]		 = "ATTN",
-	[CMD_DP_STATUS]          = "DPSTAT",
-	[CMD_DP_CONFIG]          = "DPCFG",
+static const char *const svdm_cmd_name[] = {
+	[CMD_DISCOVER_IDENT] = "DISCID",   [CMD_DISCOVER_SVID] = "DISCSVID",
+	[CMD_DISCOVER_MODES] = "DISCMODE", [CMD_ENTER_MODE] = "ENTER",
+	[CMD_EXIT_MODE] = "EXIT",	   [CMD_ATTENTION] = "ATTN",
+	[CMD_DP_STATUS] = "DPSTAT",	   [CMD_DP_CONFIG] = "DPCFG",
 };
 
-static const char * const svdm_cmdt_name[] = {
-	[CMDT_INIT]     = "INI",
-	[CMDT_RSP_ACK]  = "ACK",
-	[CMDT_RSP_NAK]  = "NAK",
+static const char *const svdm_cmdt_name[] = {
+	[CMDT_INIT] = "INI",
+	[CMDT_RSP_ACK] = "ACK",
+	[CMDT_RSP_NAK] = "NAK",
 	[CMDT_RSP_BUSY] = "BSY",
 };
 
 static void print_pdo(uint32_t word)
 {
 	if ((word & PDO_TYPE_MASK) == PDO_TYPE_BATTERY)
-		ccprintf(" %dmV/%dmW", ((word>>10)&0x3ff)*50,
-			 (word&0x3ff)*250);
+		ccprintf(" %dmV/%dmW", ((word >> 10) & 0x3ff) * 50,
+			 (word & 0x3ff) * 250);
 	else
-		ccprintf(" %dmV/%dmA", ((word>>10)&0x3ff)*50,
-			 (word&0x3ff)*10);
+		ccprintf(" %dmV/%dmA", ((word >> 10) & 0x3ff) * 50,
+			 (word & 0x3ff) * 10);
 }
 
 static void print_rdo(uint32_t word)
@@ -109,9 +106,11 @@ static void print_packet(int head, uint32_t *payload)
 	int id = PD_HEADER_ID(head);
 	const char *name;
 	const char *prole;
+	char ts_str[PRINTF_TIMESTAMP_BUF_SIZE];
 
 	if (trace_mode == TRACE_MODE_RAW) {
-		ccprintf("%pT[%04x]", PRINTF_TIMESTAMP_NOW, head);
+		snprintf_timestamp_now(ts_str, sizeof(ts_str));
+		ccprintf("%s[%04x]", ts_str, head);
 		for (i = 0; i < cnt; i++)
 			ccprintf(" %08x", payload[i]);
 		ccputs("\n");
@@ -119,8 +118,8 @@ static void print_packet(int head, uint32_t *payload)
 	}
 	name = cnt ? data_msg_name[typ] : ctrl_msg_name[typ];
 	prole = head & (PD_ROLE_SOURCE << 8) ? "SRC" : "SNK";
-	ccprintf("%pT %s/%d [%04x]%s",
-		 PRINTF_TIMESTAMP_NOW, prole, id, head, name);
+	snprintf_timestamp_now(ts_str, sizeof(ts_str));
+	ccprintf("%s %s/%d [%04x]%s", ts_str, prole, id, head, name);
 	if (!cnt) { /* Control message : we are done */
 		ccputs("\n");
 		return;
@@ -144,18 +143,22 @@ static void print_packet(int head, uint32_t *payload)
 			break;
 		default:
 			ccprintf(" %08x", payload[i]);
-	}
+		}
 	ccputs("\n");
 }
 
 static void print_error(enum pd_rx_errors err)
 {
+	char ts_str[PRINTF_TIMESTAMP_BUF_SIZE];
+
+	snprintf_timestamp_now(ts_str, sizeof(ts_str));
+
 	if (err == PD_RX_ERR_INVAL)
-		ccprintf("%pT TMOUT\n", PRINTF_TIMESTAMP_NOW);
+		ccprintf("%s TMOUT\n", ts_str);
 	else if (err == PD_RX_ERR_HARD_RESET)
-		ccprintf("%pT HARD-RST\n", PRINTF_TIMESTAMP_NOW);
+		ccprintf("%s HARD-RST\n", ts_str);
 	else if (err == PD_RX_ERR_UNSUPPORTED_SOP)
-		ccprintf("%pT SOP*\n", PRINTF_TIMESTAMP_NOW);
+		ccprintf("%s SOP*\n", ts_str);
 	else
 		ccprintf("ERR %d\n", err);
 }
@@ -176,19 +179,20 @@ static void rx_event(void)
 		if (pending & (1 << (21 + i))) {
 			rx_edge_ts[i][rx_edge_ts_idx[i]].val = get_time().val;
 			next_idx = (rx_edge_ts_idx[i] ==
-					PD_RX_TRANSITION_COUNT - 1) ?
-						0 : rx_edge_ts_idx[i] + 1;
+				    PD_RX_TRANSITION_COUNT - 1) ?
+					   0 :
+					   rx_edge_ts_idx[i] + 1;
 
 			/*
 			 * If we have seen enough edges in a certain amount of
 			 * time, then trigger RX start.
 			 */
 			if ((rx_edge_ts[i][rx_edge_ts_idx[i]].val -
-			     rx_edge_ts[i][next_idx].val)
-			     < PD_RX_TRANSITION_WINDOW) {
+			     rx_edge_ts[i][next_idx].val) <
+			    PD_RX_TRANSITION_WINDOW) {
 				/* acquire the message only on the active CC */
-				STM32_COMP_CSR &= ~(i ? STM32_COMP_CMP1EN
-						      : STM32_COMP_CMP2EN);
+				STM32_COMP_CSR &= ~(i ? STM32_COMP_CMP1EN :
+							STM32_COMP_CMP2EN);
 				/* start sampling */
 				pd_rx_start(0);
 				/*
diff --git a/board/twinkie/sniffer.c b/board/twinkie/sniffer.c
index 7d2d8d439f..ff7ad02f87 100644
--- a/board/twinkie/sniffer.c
+++ b/board/twinkie/sniffer.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -105,8 +105,8 @@ static void ep_tx(void)
 		btable_ep[USB_EP_SNIFFER].tx_addr = usb_sram_addr(ep_buf[b]);
 	}
 	/* re-enable data transmission if we have available data */
-	btable_ep[USB_EP_SNIFFER].tx_count = (free_usb & (1<<b)) ? 0
-								 : EP_BUF_SIZE;
+	btable_ep[USB_EP_SNIFFER].tx_count =
+		(free_usb & (1 << b)) ? 0 : EP_BUF_SIZE;
 	STM32_TOGGLE_EP(USB_EP_SNIFFER, EP_TX_MASK, EP_TX_VALID, 0);
 	/* wake up the processing */
 	task_set_event(TASK_ID_SNIFFER, USB_EVENT);
@@ -127,7 +127,6 @@ static void ep_event(enum usb_ep_event evt)
 }
 USB_DECLARE_EP(USB_EP_SNIFFER, ep_tx, ep_tx, ep_event);
 
-
 /* --- RX operation using comparator linked to timer --- */
 /* RX on CC1 is using COMP1 triggering TIM1 CH1 */
 #define TIM_RX1 1
@@ -144,13 +143,13 @@ USB_DECLARE_EP(USB_EP_SNIFFER, ep_tx, ep_tx, ep_event);
 static const struct dma_option dma_tim_cc1 = {
 	DMAC_TIM_RX1, (void *)&STM32_TIM_CCRx(TIM_RX1, TIM_RX1_CCR_IDX),
 	STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
-	STM32_DMA_CCR_CIRC | STM32_DMA_CCR_TCIE | STM32_DMA_CCR_HTIE
+		STM32_DMA_CCR_CIRC | STM32_DMA_CCR_TCIE | STM32_DMA_CCR_HTIE
 };
 
 static const struct dma_option dma_tim_cc2 = {
 	DMAC_TIM_RX2, (void *)&STM32_TIM_CCRx(TIM_RX2, TIM_RX2_CCR_IDX),
 	STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
-	STM32_DMA_CCR_CIRC | STM32_DMA_CCR_TCIE | STM32_DMA_CCR_HTIE
+		STM32_DMA_CCR_CIRC | STM32_DMA_CCR_TCIE | STM32_DMA_CCR_HTIE
 };
 
 /* sequence number for sample buffers */
@@ -161,7 +160,7 @@ static uint32_t oflow;
 #define SNIFFER_CHANNEL_CC1 0
 #define SNIFFER_CHANNEL_CC2 1
 
-#define get_channel(b)   (((b) >> 12) & 0x1)
+#define get_channel(b) (((b) >> 12) & 0x1)
 
 void tim_rx1_handler(uint32_t stat)
 {
@@ -171,8 +170,7 @@ void tim_rx1_handler(uint32_t stat)
 	uint32_t next = idx ? 0x0001 : 0x0100;
 
 	sample_tstamp[idx] = __hw_clock_source_read();
-	sample_seq[idx] = ((seq++ << 3) & 0x0ff8) |
-			(SNIFFER_CHANNEL_CC1<<12);
+	sample_seq[idx] = ((seq++ << 3) & 0x0ff8) | (SNIFFER_CHANNEL_CC1 << 12);
 	if (filled_dma & next) {
 		oflow++;
 		sample_seq[idx] |= 0x8000;
@@ -193,8 +191,7 @@ void tim_rx2_handler(uint32_t stat)
 
 	idx += 2;
 	sample_tstamp[idx] = __hw_clock_source_read();
-	sample_seq[idx] = ((seq++ << 3) & 0x0ff8) |
-			(SNIFFER_CHANNEL_CC2<<12);
+	sample_seq[idx] = ((seq++ << 3) & 0x0ff8) | (SNIFFER_CHANNEL_CC2 << 12);
 	if (filled_dma & next) {
 		oflow++;
 		sample_seq[idx] |= 0x8000;
@@ -209,10 +206,10 @@ void tim_rx2_handler(uint32_t stat)
 static void tim_dma_handler(void)
 {
 	stm32_dma_regs_t *dma = STM32_DMA1_REGS;
-	uint32_t stat = dma->isr & (STM32_DMA_ISR_HTIF(DMAC_TIM_RX1)
-				  | STM32_DMA_ISR_TCIF(DMAC_TIM_RX1)
-				  | STM32_DMA_ISR_HTIF(DMAC_TIM_RX2)
-				  | STM32_DMA_ISR_TCIF(DMAC_TIM_RX2));
+	uint32_t stat = dma->isr & (STM32_DMA_ISR_HTIF(DMAC_TIM_RX1) |
+				    STM32_DMA_ISR_TCIF(DMAC_TIM_RX1) |
+				    STM32_DMA_ISR_HTIF(DMAC_TIM_RX2) |
+				    STM32_DMA_ISR_TCIF(DMAC_TIM_RX2));
 	if (stat & STM32_DMA_ISR_ALL(DMAC_TIM_RX2))
 		tim_rx2_handler(stat);
 	else
@@ -251,30 +248,26 @@ static void rx_timer_init(int tim_id, timer_ctlr_t *tim, int ch_idx, int up_idx)
 	tim->sr = 0;
 }
 
-
-
 void sniffer_init(void)
 {
 	/* remap TIM1 CH1/2/3 to DMA channel 6 */
 	STM32_SYSCFG_CFGR1 |= BIT(28);
 
 	/* TIM1 CH1 for CC1 RX */
-	rx_timer_init(TIM_RX1, (void *)STM32_TIM_BASE(TIM_RX1),
-		      TIM_RX1_CCR_IDX, 2);
+	rx_timer_init(TIM_RX1, (void *)STM32_TIM_BASE(TIM_RX1), TIM_RX1_CCR_IDX,
+		      2);
 	/* TIM3 CH4 for CC2 RX */
-	rx_timer_init(TIM_RX2, (void *)STM32_TIM_BASE(TIM_RX2),
-		      TIM_RX2_CCR_IDX, 2);
+	rx_timer_init(TIM_RX2, (void *)STM32_TIM_BASE(TIM_RX2), TIM_RX2_CCR_IDX,
+		      2);
 
 	/* turn on COMP/SYSCFG */
 	STM32_RCC_APB2ENR |= BIT(0);
-	STM32_COMP_CSR = STM32_COMP_CMP1EN | STM32_COMP_CMP1MODE_HSPEED |
-			 STM32_COMP_CMP1INSEL_VREF12 |
-			 STM32_COMP_CMP1OUTSEL_TIM1_IC1 |
-			 STM32_COMP_CMP1HYST_HI |
-			 STM32_COMP_CMP2EN | STM32_COMP_CMP2MODE_HSPEED |
-			 STM32_COMP_CMP2INSEL_VREF12 |
-			 STM32_COMP_CMP2OUTSEL_TIM2_IC4 |
-			 STM32_COMP_CMP2HYST_HI;
+	STM32_COMP_CSR =
+		STM32_COMP_CMP1EN | STM32_COMP_CMP1MODE_HSPEED |
+		STM32_COMP_CMP1INSEL_VREF12 | STM32_COMP_CMP1OUTSEL_TIM1_IC1 |
+		STM32_COMP_CMP1HYST_HI | STM32_COMP_CMP2EN |
+		STM32_COMP_CMP2MODE_HSPEED | STM32_COMP_CMP2INSEL_VREF12 |
+		STM32_COMP_CMP2OUTSEL_TIM2_IC4 | STM32_COMP_CMP2HYST_HI;
 
 	/* start sampling the edges on the CC lines using the RX timers */
 	dma_start_rx(&dma_tim_cc1, RX_COUNT, samples[0]);
@@ -311,11 +304,11 @@ void sniffer_task(void)
 			ep_buf[u][0] = sample_seq[d >> 3] | (d & 7);
 			ep_buf[u][1] = sample_tstamp[d >> 3];
 
-			memcpy_to_usbram(
-					((void *)usb_sram_addr(ep_buf[u]
-						+ (EP_PACKET_HEADER_SIZE>>1))),
-					samples[d >> 4]+off,
-					EP_PAYLOAD_SIZE);
+			memcpy_to_usbram(((void *)usb_sram_addr(
+						 ep_buf[u] +
+						 (EP_PACKET_HEADER_SIZE >> 1))),
+					 samples[d >> 4] + off,
+					 EP_PAYLOAD_SIZE);
 			atomic_clear_bits((atomic_t *)&free_usb, 1 << u);
 			u = !u;
 			atomic_clear_bits((atomic_t *)&filled_dma, 1 << d);
@@ -332,8 +325,8 @@ void sniffer_task(void)
 
 int wait_packet(int pol, uint32_t min_edges, uint32_t timeout_us)
 {
-	stm32_dma_chan_t *chan = dma_get_channel(pol ? DMAC_TIM_RX2
-						     : DMAC_TIM_RX1);
+	stm32_dma_chan_t *chan =
+		dma_get_channel(pol ? DMAC_TIM_RX2 : DMAC_TIM_RX1);
 	uint32_t t0 = __hw_clock_source_read();
 	uint32_t c0 = chan->cndtr;
 	uint32_t t_gap = t0;
@@ -355,7 +348,7 @@ int wait_packet(int pol, uint32_t min_edges, uint32_t timeout_us)
 				total_edges += nb;
 			} else {
 				if ((t - t_gap) > 20 &&
-				    (total_edges - (t - t0)/256) >= min_edges)
+				    (total_edges - (t - t0) / 256) >= min_edges)
 					/* real gap after the packet */
 					break;
 			}
@@ -392,11 +385,10 @@ static void sniffer_sysjump(void)
 }
 DECLARE_HOOK(HOOK_SYSJUMP, sniffer_sysjump, HOOK_PRIO_DEFAULT);
 
-static int command_sniffer(int argc, char **argv)
+static int command_sniffer(int argc, const char **argv)
 {
 	ccprintf("Seq number:%d Overflows: %d\n", seq, oflow);
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(sniffer, command_sniffer,
-			"[]", "Buffering status");
+DECLARE_CONSOLE_COMMAND(sniffer, command_sniffer, "[]", "Buffering status");
diff --git a/board/twinkie/usb_pd_config.h b/board/twinkie/usb_pd_config.h
index 1c20a9df77..062c174d8a 100644
--- a/board/twinkie/usb_pd_config.h
+++ b/board/twinkie/usb_pd_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -50,7 +50,7 @@ static inline void spi_enable_clock(int port)
 #define DMAC_TIM_RX(p) STM32_DMAC_CH2
 #define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
 #define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
-#define TIM_CCR_CS  1
+#define TIM_CCR_CS 1
 #define EXTI_COMP_MASK(p) (BIT(21) | BIT(22))
 #define IRQ_COMP STM32_IRQ_COMP
 /* triggers packet detection on comparator falling edge */
@@ -102,11 +102,11 @@ static inline void pd_tx_enable(int port, int polarity)
 static inline void pd_tx_disable(int port, int polarity)
 {
 	/* TX_DATA on PB4 is an output low GPIO to disable the FET */
-	STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B) & ~(3 << (2*4)))
-							     |  (1 << (2*4));
+	STM32_GPIO_MODER(GPIO_B) =
+		(STM32_GPIO_MODER(GPIO_B) & ~(3 << (2 * 4))) | (1 << (2 * 4));
 	/* TX_DATA on PA6 is an output low GPIO to disable the FET */
-	STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) & ~(3 << (2*6)))
-							     |  (1 << (2*6));
+	STM32_GPIO_MODER(GPIO_A) =
+		(STM32_GPIO_MODER(GPIO_A) & ~(3 << (2 * 6))) | (1 << (2 * 6));
 	/*
 	 * Tri-state the low side after the high side
 	 * to ensure we are not going above Vnc
@@ -119,11 +119,12 @@ static inline void pd_tx_disable(int port, int polarity)
 static inline void pd_select_polarity(int port, int polarity)
 {
 	/* use the right comparator */
-	STM32_COMP_CSR = (STM32_COMP_CSR
-		& ~(STM32_COMP_CMP1INSEL_MASK | STM32_COMP_CMP2INSEL_MASK
-		  |STM32_COMP_CMP1EN | STM32_COMP_CMP2EN))
-		| STM32_COMP_CMP1INSEL_INM4 | STM32_COMP_CMP2INSEL_INM4
-		| (polarity ? STM32_COMP_CMP2EN : STM32_COMP_CMP1EN);
+	STM32_COMP_CSR =
+		(STM32_COMP_CSR &
+		 ~(STM32_COMP_CMP1INSEL_MASK | STM32_COMP_CMP2INSEL_MASK |
+		   STM32_COMP_CMP1EN | STM32_COMP_CMP2EN)) |
+		STM32_COMP_CMP1INSEL_INM4 | STM32_COMP_CMP2INSEL_INM4 |
+		(polarity ? STM32_COMP_CMP2EN : STM32_COMP_CMP1EN);
 }
 
 /* Initialize pins used for clocking */
diff --git a/board/twinkie/usb_pd_pdo.c b/board/twinkie/usb_pd_pdo.c
index 120c13125b..fbc0624f80 100644
--- a/board/twinkie/usb_pd_pdo.c
+++ b/board/twinkie/usb_pd_pdo.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,15 +10,15 @@
 #define PDO_FIXED_FLAGS (PDO_FIXED_UNCONSTRAINED | PDO_FIXED_DATA_SWAP)
 
 const uint32_t pd_src_pdo[] = {
-		PDO_FIXED(5000,  3000, PDO_FIXED_FLAGS),
-		PDO_FIXED(12000, 3000, PDO_FIXED_FLAGS),
-		PDO_FIXED(20000, 3000, PDO_FIXED_FLAGS),
+	PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS),
+	PDO_FIXED(12000, 3000, PDO_FIXED_FLAGS),
+	PDO_FIXED(20000, 3000, PDO_FIXED_FLAGS),
 };
 const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
 
 const uint32_t pd_snk_pdo[] = {
-		PDO_FIXED(5000, 500, PDO_FIXED_FLAGS),
-		PDO_BATT(4750, 21000, 15000),
-		PDO_VAR(4750, 21000, 3000),
+	PDO_FIXED(5000, 500, PDO_FIXED_FLAGS),
+	PDO_BATT(4750, 21000, 15000),
+	PDO_VAR(4750, 21000, 3000),
 };
 const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
diff --git a/board/twinkie/usb_pd_pdo.h b/board/twinkie/usb_pd_pdo.h
index 377ccce1b5..0badd0f7bf 100644
--- a/board/twinkie/usb_pd_pdo.h
+++ b/board/twinkie/usb_pd_pdo.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/twinkie/usb_pd_policy.c b/board/twinkie/usb_pd_policy.c
index a8f76b40e5..c99dfb5750 100644
--- a/board/twinkie/usb_pd_policy.c
+++ b/board/twinkie/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,8 +15,8 @@
 #include "usb_pd.h"
 #include "usb_pd_pdo.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 void pd_set_input_current_limit(int port, uint32_t max_ma,
 				uint32_t supply_voltage)
@@ -50,27 +50,23 @@ __override int pd_check_power_swap(int port)
 	return 0;
 }
 
-__override int pd_check_data_swap(int port,
-				  enum pd_data_role data_role)
+__override int pd_check_data_swap(int port, enum pd_data_role data_role)
 {
 	/* Always allow data swap */
 	return 1;
 }
 
-__override void pd_check_pr_role(int port,
-				 enum pd_power_role pr_role,
+__override void pd_check_pr_role(int port, enum pd_power_role pr_role,
 				 int flags)
 {
 }
 
-__override void pd_check_dr_role(int port,
-				 enum pd_data_role dr_role,
-				 int flags)
+__override void pd_check_dr_role(int port, enum pd_data_role dr_role, int flags)
 {
 }
 
 __override int pd_custom_vdm(int port, int cnt, uint32_t *payload,
-		  uint32_t **rpayload)
+			     uint32_t **rpayload)
 {
 	return 0;
 }
diff --git a/board/vell/battery.c b/board/vell/battery.c
index 15041415a1..0ffb7fb015 100644
--- a/board/vell/battery.c
+++ b/board/vell/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/vell/board.c b/board/vell/board.c
index 47774afec5..7496df1b86 100644
--- a/board/vell/board.c
+++ b/board/vell/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,6 +17,7 @@
 #include "fw_config.h"
 #include "hooks.h"
 #include "lid_switch.h"
+#include "panic.h"
 #include "power_button.h"
 #include "power.h"
 #include "registers.h"
@@ -27,8 +28,8 @@
 #include "gpio_list.h" /* Must come after other header files. */
 
 /* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 static void board_chipset_startup(void)
 {
diff --git a/board/vell/board.h b/board/vell/board.h
index eabb09d75a..a17be43a50 100644
--- a/board/vell/board.h
+++ b/board/vell/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -45,13 +45,14 @@
 /* Sensors without hardware FIFO are in forced mode */
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(CLEAR_ALS)
 
-
 /* USB Type C and USB PD defines */
 #define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
 
 #define CONFIG_IO_EXPANDER
 #define CONFIG_IO_EXPANDER_NCT38XX
-#define CONFIG_IO_EXPANDER_PORT_COUNT		4
+#define CONFIG_IO_EXPANDER_PORT_COUNT 4
+
+#define CONFIG_USB_PD_FRS_PPC
 
 #define CONFIG_USBC_RETIMER_INTEL_BB
 
@@ -61,16 +62,16 @@
 #define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_5_50
 
 /* TODO: b/177608416 - measure and check these values on brya */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
 
 /* USB Type C and USB PD defines */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_CURRENT_MA	5000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_CURRENT_MA 5000
+#define PD_MAX_VOLTAGE_MV 20000
 /* Max Power = 100 W */
-#define PD_MAX_POWER_MW	((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
+#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
 
 /*
  * Macros for GPIO signals used in common code that don't match the
@@ -78,84 +79,78 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT		GPIO_EC_EN_EDP_BL
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_GSC_PACKET_MODE
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SYS_SLP_S0IX_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_TEMP_SENSOR_POWER	GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
 
 /*
  * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
  * signal.
  */
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_SEQ_EC_ALL_SYS_PG
-#define GPIO_PG_EC_DSW_PWROK		GPIO_SEQ_EC_DSW_PWROK
-#define GPIO_PG_EC_RSMRST_ODL		GPIO_SEQ_EC_RSMRST_ODL
-#define GPIO_POWER_BUTTON_L		GPIO_GSC_EC_PWR_BTN_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_ODL
-#define GPIO_RIGHT_LED_AMBER_L		GPIO_LED_1_L
-#define GPIO_RIGHT_LED_WHITE_L		GPIO_LED_2_L
-#define GPIO_LEFT_LED_AMBER_L		GPIO_LED_3_L
-#define GPIO_LEFT_LED_WHITE_L		GPIO_LED_4_L
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
+#define GPIO_RIGHT_LED_AMBER_L GPIO_LED_1_L
+#define GPIO_RIGHT_LED_WHITE_L GPIO_LED_2_L
+#define GPIO_LEFT_LED_AMBER_L GPIO_LED_3_L
+#define GPIO_LEFT_LED_WHITE_L GPIO_LED_4_L
 
 /* System has back-lit keyboard */
 #define CONFIG_PWM_KBLIGHT
 
 /* I2C Bus Configuration */
 
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
 
-#define I2C_PORT_USB_C0_C1_TCPC	NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C2_C3_TCPC	NPCX_I2C_PORT4_1
+#define I2C_PORT_USB_C0_C1_TCPC NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C2_C3_TCPC NPCX_I2C_PORT4_1
 
-#define I2C_PORT_USB_C0_C1_PPC	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C2_C3_PPC	NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C0_C1_PPC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C2_C3_PPC NPCX_I2C_PORT6_1
 
-#define I2C_PORT_USB_C0_C1_BC12	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C2_C3_BC12	NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C0_C1_BC12 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C2_C3_BC12 NPCX_I2C_PORT6_1
 
-#define I2C_PORT_USB_C0_C1_MUX	NPCX_I2C_PORT3_0
-#define I2C_PORT_USB_C2_C3_MUX	NPCX_I2C_PORT3_0
+#define I2C_PORT_USB_C0_C1_MUX NPCX_I2C_PORT3_0
+#define I2C_PORT_USB_C2_C3_MUX NPCX_I2C_PORT3_0
 
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT5_0
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT7_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
 
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 
 /*
  * see b/174768555#comment22
  */
-#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR	0x56
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x57
-#define USBC_PORT_C2_BB_RETIMER_I2C_ADDR	0x58
-#define USBC_PORT_C3_BB_RETIMER_I2C_ADDR	0x59
+#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x56
+#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x57
+#define USBC_PORT_C2_BB_RETIMER_I2C_ADDR 0x58
+#define USBC_PORT_C3_BB_RETIMER_I2C_ADDR 0x59
 
 /* Enabling Thunderbolt-compatible mode */
 #define CONFIG_USB_PD_TBT_COMPAT_MODE
 
 /* Enabling USB4 mode */
 #define CONFIG_USB_PD_USB4
+#define CONFIG_USB_PD_DATA_RESET_MSG
 
-/*
- * TODO: b/220634230, Disable BBR firmware update temporally,
- * revert this patch once confirm BBR firmware update is ready
- * on kernel.
- */
 /* Retimer */
-#if 0
 #define CONFIG_USBC_RETIMER_FW_UPDATE
-#endif
 
 /* Thermal features */
 #define CONFIG_THERMISTOR
@@ -164,22 +159,23 @@
 #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
 
 /* Fan features */
-#define CONFIG_FANS			FAN_CH_COUNT
+#define CONFIG_FANS FAN_CH_COUNT
+#define CONFIG_FAN_BYPASS_SLOW_RESPONSE
 #define CONFIG_CUSTOM_FAN_CONTROL
-#define RPM_DEVIATION	1
+#define RPM_DEVIATION 1
 
 /* Charger defines */
 #define CONFIG_CHARGER_ISL9241
 #define CONFIG_CHARGE_RAMP_SW
-#define CONFIG_CHARGER_SENSE_RESISTOR		5
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_SENSE_RESISTOR 5
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 
 /* Keyboard features */
 #define CONFIG_KEYBOARD_FACTORY_TEST
 #define CONFIG_KEYBOARD_REFRESH_ROW3
 
 #undef CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE
-#define CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE	3
+#define CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE 3
 
 /*
  * Older boards have a different ADC assignment.
@@ -189,7 +185,7 @@
 
 #ifndef __ASSEMBLER__
 
-#include "gpio_signal.h"	/* needed by registers.h */
+#include "gpio_signal.h" /* needed by registers.h */
 #include "registers.h"
 #include "usbc_config.h"
 
@@ -211,11 +207,7 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum sensor_id {
-	CLEAR_ALS = 0,
-	RGB_ALS,
-	SENSOR_COUNT
-};
+enum sensor_id { CLEAR_ALS = 0, RGB_ALS, SENSOR_COUNT };
 
 enum ioex_port {
 	IOEX_C0_NCT38XX = 0,
@@ -232,20 +224,14 @@ enum battery_type {
 };
 
 enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,		/* PWM3 */
-	PWM_CH_FAN,			/* PWM5 */
+	PWM_CH_KBLIGHT = 0, /* PWM3 */
+	PWM_CH_FAN, /* PWM5 */
 	PWM_CH_COUNT
 };
 
-enum fan_channel {
-	FAN_CH_0 = 0,
-	FAN_CH_COUNT
-};
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT };
 
-enum mft_channel {
-	MFT_CH_0 = 0,
-	MFT_CH_COUNT
-};
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT };
 
 #ifdef CONFIG_KEYBOARD_FACTORY_TEST
 extern const int keyboard_factory_scan_pins[][2];
diff --git a/board/vell/build.mk b/board/vell/build.mk
index c43f37b4dd..cad0da2a4e 100644
--- a/board/vell/build.mk
+++ b/board/vell/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/vell/charger.c b/board/vell/charger.c
index 0b35b7ba29..e33a0ed44a 100644
--- a/board/vell/charger.c
+++ b/board/vell/charger.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,9 +16,8 @@
 #include "usb_pd.h"
 #include "util.h"
 
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* Charger Chip Configuration */
 const struct charger_config_t chg_chips[] = {
@@ -82,17 +81,16 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-					  int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	/*
 	 * Limit the input current to 96% negotiated limit,
 	 * to account for the charger chip margin.
 	 */
 	charge_ma = charge_ma * 96 / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 static void set_ac_prochot(void)
diff --git a/board/vell/ec.tasklist b/board/vell/ec.tasklist
index 924d708a6b..0bae104a07 100644
--- a/board/vell/ec.tasklist
+++ b/board/vell/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/vell/fans.c b/board/vell/fans.c
index fb2b29f502..b3fc2f8585 100644
--- a/board/vell/fans.c
+++ b/board/vell/fans.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,7 +25,7 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 static const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
diff --git a/board/vell/fw_config.c b/board/vell/fw_config.c
index 9c28c3ca58..bf5e29fe05 100644
--- a/board/vell/fw_config.c
+++ b/board/vell/fw_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,7 +10,7 @@
 #include "cros_board_info.h"
 #include "fw_config.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 static union brya_cbi_fw_config fw_config;
 BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
diff --git a/board/vell/fw_config.h b/board/vell/fw_config.h
index 6e4eb3ef58..fea6c9a8da 100644
--- a/board/vell/fw_config.h
+++ b/board/vell/fw_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,12 +27,12 @@ enum ec_cfg_keyboard_backlight_type {
 
 union brya_cbi_fw_config {
 	struct {
-		enum ec_cfg_usb_db_type			usb_db : 4;
-		uint32_t				sd_db : 2;
-		uint32_t				lte_db : 1;
-		enum ec_cfg_keyboard_backlight_type	kb_bl : 1;
-		uint32_t				audio : 3;
-		uint32_t				reserved_1 : 21;
+		enum ec_cfg_usb_db_type usb_db : 4;
+		uint32_t sd_db : 2;
+		uint32_t lte_db : 1;
+		enum ec_cfg_keyboard_backlight_type kb_bl : 1;
+		uint32_t audio : 3;
+		uint32_t reserved_1 : 21;
 	};
 	uint32_t raw_value;
 };
diff --git a/board/vell/gpio.inc b/board/vell/gpio.inc
index 4c5b630658..9f6ce7cc7e 100644
--- a/board/vell/gpio.inc
+++ b/board/vell/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -142,23 +142,23 @@ GPIO(EC_KSO_02_INV,               PIN(1, 7), GPIO_OUT_LOW)
 /* GPIO02_P1 to PU */
 /* GPIO03_P1 to PU */
 IOEX(USB_C0_OC_ODL,          EXPIN(IOEX_C0_NCT38XX, 0, 4), GPIO_ODR_HIGH)
-IOEX(USB_C0_FRS_EN,          EXPIN(IOEX_C0_NCT38XX, 0, 6), GPIO_LOW)
+IOEX(USB_C0_FRS_EN,          EXPIN(IOEX_C0_NCT38XX, 0, 6), GPIO_OUT_LOW)
 IOEX(USB_C0_RT_RST_ODL,      EXPIN(IOEX_C0_NCT38XX, 0, 7), GPIO_ODR_LOW)
 
 IOEX(USB_C1_RT_RST_ODL,      EXPIN(IOEX_C1_NCT38XX, 0, 2), GPIO_ODR_LOW)
 /* GPIO03_P2 to PU */
 IOEX(USB_C1_OC_ODL,          EXPIN(IOEX_C1_NCT38XX, 0, 4), GPIO_ODR_HIGH)
-IOEX(USB_C1_FRS_EN,          EXPIN(IOEX_C1_NCT38XX, 0, 6), GPIO_LOW)
+IOEX(USB_C1_FRS_EN,          EXPIN(IOEX_C1_NCT38XX, 0, 6), GPIO_OUT_LOW)
 /* GPIO07_P2 to PU */
 
 /* GPIO02_P1 to PU */
 /* GPIO03_P1 to PU */
 IOEX(USB_C2_OC_ODL,          EXPIN(IOEX_C2_NCT38XX, 0, 4), GPIO_ODR_HIGH)
-IOEX(USB_C2_FRS_EN,          EXPIN(IOEX_C2_NCT38XX, 0, 6), GPIO_LOW)
+IOEX(USB_C2_FRS_EN,          EXPIN(IOEX_C2_NCT38XX, 0, 6), GPIO_OUT_LOW)
 IOEX(USB_C2_RT_RST_ODL,      EXPIN(IOEX_C2_NCT38XX, 0, 7), GPIO_ODR_LOW)
 
 IOEX(USB_C3_RT_RST_ODL,      EXPIN(IOEX_C3_NCT38XX, 0, 2), GPIO_ODR_LOW)
 /* GPIO03_P2 to PU */
 IOEX(USB_C3_OC_ODL,          EXPIN(IOEX_C3_NCT38XX, 0, 4), GPIO_ODR_HIGH)
-IOEX(USB_C3_FRS_EN,          EXPIN(IOEX_C3_NCT38XX, 0, 6), GPIO_LOW)
+IOEX(USB_C3_FRS_EN,          EXPIN(IOEX_C3_NCT38XX, 0, 6), GPIO_OUT_LOW)
 /* GPIO07_P2 to PU */
diff --git a/board/vell/i2c.c b/board/vell/i2c.c
index 4f505d74c7..822de9a0d1 100644
--- a/board/vell/i2c.c
+++ b/board/vell/i2c.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/vell/keyboard.c b/board/vell/keyboard.c
index 7a51f8dd39..f541f51e3b 100644
--- a/board/vell/keyboard.c
+++ b/board/vell/keyboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -48,7 +48,6 @@ __override const struct ec_response_keybd_config *
 board_vivaldi_keybd_config(void)
 {
 	return &keybd1;
-
 }
 
 #ifdef CONFIG_KEYBOARD_FACTORY_TEST
@@ -58,13 +57,13 @@ board_vivaldi_keybd_config(void)
  * The connector has 24 pins total, and there is no pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-		{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-		{0, 7}, {1, 4}, {1, 3}, {1, 6}, {1, 7},
-		{3, 1}, {2, 0}, {1, 5}, {2, 6}, {2, 7},
-		{2, 1}, {2, 4}, {2, 5}, {1, 2}, {2, 3},
-		{2, 2}, {3, 0}, {-1, -1}, {-1, -1}, {-1, -1},
+	{ -1, -1 }, { 0, 5 }, { 1, 1 },	  { 1, 0 },   { 0, 6 },
+	{ 0, 7 },   { 1, 4 }, { 1, 3 },	  { 1, 6 },   { 1, 7 },
+	{ 3, 1 },   { 2, 0 }, { 1, 5 },	  { 2, 6 },   { 2, 7 },
+	{ 2, 1 },   { 2, 4 }, { 2, 5 },	  { 1, 2 },   { 2, 3 },
+	{ 2, 2 },   { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 },
 };
 
 const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 #endif
diff --git a/board/vell/led.c b/board/vell/led.c
index 4387d1a6d7..cd9304b2cf 100644
--- a/board/vell/led.c
+++ b/board/vell/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -22,15 +22,13 @@
 #define BATT_LOW_BCT 10
 
 #define LED_TICK_INTERVAL_MS (500 * MSEC)
-#define LED_CYCLE_TIME_MS    (2000 * MSEC)
-#define LED_TICKS_PER_CYCLE  (LED_CYCLE_TIME_MS / LED_TICK_INTERVAL_MS)
-#define LED_ON_TIME_MS       (1000 * MSEC)
-#define LED_ON_TICKS         (LED_ON_TIME_MS / LED_TICK_INTERVAL_MS)
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_LEFT_LED,
-	EC_LED_ID_RIGHT_LED
-};
+#define LED_CYCLE_TIME_MS (2000 * MSEC)
+#define LED_TICKS_PER_CYCLE (LED_CYCLE_TIME_MS / LED_TICK_INTERVAL_MS)
+#define LED_ON_TIME_MS (1000 * MSEC)
+#define LED_ON_TICKS (LED_ON_TIME_MS / LED_TICK_INTERVAL_MS)
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_LEFT_LED,
+					     EC_LED_ID_RIGHT_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -38,13 +36,10 @@ enum led_color {
 	LED_OFF = 0,
 	LED_AMBER,
 	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
-enum led_port {
-	RIGHT_PORT = 0,
-	LEFT_PORT
-};
+enum led_port { RIGHT_PORT = 0, LEFT_PORT };
 
 uint8_t bat_led_on;
 uint8_t bat_led_off;
@@ -66,9 +61,9 @@ static void led_set_color_battery(int port, enum led_color color)
 	enum gpio_signal amber_led, white_led;
 
 	amber_led = (port == RIGHT_PORT ? GPIO_RIGHT_LED_AMBER_L :
-				 GPIO_LEFT_LED_AMBER_L);
+					  GPIO_LEFT_LED_AMBER_L);
 	white_led = (port == RIGHT_PORT ? GPIO_RIGHT_LED_WHITE_L :
-				 GPIO_LEFT_LED_WHITE_L);
+					  GPIO_LEFT_LED_WHITE_L);
 
 	switch (color) {
 	case LED_WHITE:
@@ -148,16 +143,15 @@ static void set_active_port_color(enum led_color color)
 
 	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
 		led_set_color_battery(RIGHT_PORT,
-				(port == RIGHT_PORT) ? color : LED_OFF);
+				      (port == RIGHT_PORT) ? color : LED_OFF);
 	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
 		led_set_color_battery(LEFT_PORT,
-				(port == LEFT_PORT) ? color : LED_OFF);
+				      (port == LEFT_PORT) ? color : LED_OFF);
 }
 
 static void led_set_battery(void)
 {
 	static unsigned int battery_ticks;
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
@@ -173,43 +167,52 @@ static void led_set_battery(void)
 		 */
 		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
 			if (charge_get_percent() < BATT_LOW_BCT)
-				led_set_color_battery(RIGHT_PORT,
-					(battery_ticks % LED_TICKS_PER_CYCLE
-					 < LED_ON_TICKS) ? LED_AMBER : LED_OFF);
+				led_set_color_battery(
+					RIGHT_PORT,
+					(battery_ticks % LED_TICKS_PER_CYCLE <
+					 LED_ON_TICKS) ?
+						LED_AMBER :
+						LED_OFF);
 			else
 				led_set_color_battery(RIGHT_PORT, LED_OFF);
 		}
 
 		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) {
 			if (charge_get_percent() < BATT_LOW_BCT)
-				led_set_color_battery(LEFT_PORT,
-					(battery_ticks % LED_TICKS_PER_CYCLE
-					 < LED_ON_TICKS) ? LED_AMBER : LED_OFF);
+				led_set_color_battery(
+					LEFT_PORT,
+					(battery_ticks % LED_TICKS_PER_CYCLE <
+					 LED_ON_TICKS) ?
+						LED_AMBER :
+						LED_OFF);
 			else
 				led_set_color_battery(LEFT_PORT, LED_OFF);
 		}
 		break;
 	case PWR_STATE_ERROR:
 		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
-			led_set_color_battery(RIGHT_PORT, (battery_ticks & 0x1)
-				? LED_AMBER : LED_OFF);
+			led_set_color_battery(
+				RIGHT_PORT,
+				(battery_ticks & 0x1) ? LED_AMBER : LED_OFF);
 		}
 
 		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) {
-			led_set_color_battery(LEFT_PORT, (battery_ticks & 0x1)
-				? LED_AMBER : LED_OFF);
+			led_set_color_battery(LEFT_PORT, (battery_ticks & 0x1) ?
+								 LED_AMBER :
+								 LED_OFF);
 		}
 		break;
 	case PWR_STATE_CHARGE_NEAR_FULL:
 		set_active_port_color(LED_WHITE);
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			set_active_port_color((battery_ticks %
-				LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
-				LED_AMBER : LED_OFF);
-		else
-			set_active_port_color(LED_WHITE);
+		set_active_port_color(LED_WHITE);
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		set_active_port_color(
+			(battery_ticks % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
+				LED_AMBER :
+				LED_OFF);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
diff --git a/board/vell/pwm.c b/board/vell/pwm.c
index 90fb4dac68..94fb4e8929 100644
--- a/board/vell/pwm.c
+++ b/board/vell/pwm.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/vell/sensors.c b/board/vell/sensors.c
index 0528a62717..f088fc8867 100644
--- a/board/vell/sensors.c
+++ b/board/vell/sensors.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -61,7 +61,7 @@ static struct als_drv_data_t g_tcs3400_data = {
 	.als_cal.offset = 0,
 	.als_cal.channel_scale = {
 		.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kc from VPD */
-		.cover_scale = ALS_CHANNEL_SCALE(1.0),     /* CT */
+		.cover_scale = ALS_CHANNEL_SCALE(0.23),     /* CT */
 	},
 };
 
@@ -71,39 +71,39 @@ static struct als_drv_data_t g_tcs3400_data = {
  */
 static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
 	.calibration.rgb_cal[X] = {
-		.offset = 0,
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(1.0),
+		.offset = 448, /* 447.5509362 */
+		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(-0.45511034),
+		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(-0.21956361),
+		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0.32628044),
+		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0.3610898),
 		.scale = {
 			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kr */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
+			.cover_scale = ALS_CHANNEL_SCALE(0.08)
 		}
 	},
 	.calibration.rgb_cal[Y] = {
-		.offset = 0,
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(1.0),
+		.offset = 436, /* 435.9025807*/
+		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(-0.50765776),
+		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(-0.34142269),
+		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0.55352908),
+		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0.35923454),
 		.scale = {
 			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kg */
 			.cover_scale = ALS_CHANNEL_SCALE(1.0)
 		},
 	},
 	.calibration.rgb_cal[Z] = {
-		.offset = 0,
-		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(0),
-		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(1.0),
+		.offset = 287, /* 286.51472391*/
+		.coeff[TCS_RED_COEFF_IDX] = FLOAT_TO_FP(-0.11635731),
+		.coeff[TCS_GREEN_COEFF_IDX] = FLOAT_TO_FP(-0.76700456),
+		.coeff[TCS_BLUE_COEFF_IDX] = FLOAT_TO_FP(1.36663521),
+		.coeff[TCS_CLEAR_COEFF_IDX] = FLOAT_TO_FP(0.18494607),
 		.scale = {
 			.k_channel_scale = ALS_CHANNEL_SCALE(1.0), /* kb */
-			.cover_scale = ALS_CHANNEL_SCALE(1.0)
+			.cover_scale = ALS_CHANNEL_SCALE(0.54)
 		}
 	},
-	.calibration.irt = INT_TO_FP(1),
+	.calibration.irt = FLOAT_TO_FP(0.06),
 	.saturation.again = TCS_DEFAULT_AGAIN,
 	.saturation.atime = TCS_DEFAULT_ATIME,
 };
@@ -207,8 +207,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CPU \
-	{ \
+#define THERMAL_CPU              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(90), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(95), \
@@ -225,8 +225,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CHARGER \
-	{ \
+#define THERMAL_CHARGER          \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(90), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(95), \
@@ -244,8 +244,8 @@ __maybe_unused static const struct ec_thermal_config thermal_charger =
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_WWAN \
-	{ \
+#define THERMAL_WWAN             \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
@@ -264,8 +264,8 @@ __maybe_unused static const struct ec_thermal_config thermal_wwan =
  * TODO(b/202062363): Remove when clang is fixed.
  */
 
-#define THERMAL_DDR \
-	{ \
+#define THERMAL_DDR              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(80), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(85), \
@@ -274,8 +274,7 @@ __maybe_unused static const struct ec_thermal_config thermal_wwan =
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
 		}, \
 	}
-__maybe_unused static const struct ec_thermal_config thermal_ddr =
-	THERMAL_DDR;
+__maybe_unused static const struct ec_thermal_config thermal_ddr = THERMAL_DDR;
 
 /*
  * TODO(b/203839956): update for Alder Lake/vell
@@ -284,8 +283,8 @@ __maybe_unused static const struct ec_thermal_config thermal_ddr =
  * TODO(b/202062363): Remove when clang is fixed.
  */
 
-#define THERMAL_REGULATOR \
-	{ \
+#define THERMAL_REGULATOR        \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(80), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(85), \
@@ -299,7 +298,7 @@ __maybe_unused static const struct ec_thermal_config thermal_regulator =
 
 struct ec_thermal_config thermal_params[] = {
 	[TEMP_SENSOR_1_SOC] = thermal_cpu,
-	[TEMP_SENSOR_2_CHARGER]	= thermal_charger,
+	[TEMP_SENSOR_2_CHARGER] = thermal_charger,
 	[TEMP_SENSOR_3_WWAN] = thermal_wwan,
 	[TEMP_SENSOR_4_DDR] = thermal_ddr,
 	[TEMP_SENSOR_5_REGULATOR] = thermal_regulator,
diff --git a/board/vell/thermal.c b/board/vell/thermal.c
index e72b86e3b1..29d438761b 100644
--- a/board/vell/thermal.c
+++ b/board/vell/thermal.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,7 +15,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_THERMAL, outstr)
-#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
 
 struct fan_step {
 	/*
@@ -37,27 +37,27 @@ struct fan_step {
 static const struct fan_step fan_table[] = {
 	{
 		/* level 0 */
-		.on = {48, 60, 48, 47, -1},
-		.off = {99, 99, 99, 99, -1},
-		.rpm = {0},
+		.on = { 48, 62, 48, 50, -1 },
+		.off = { 99, 99, 99, 99, -1 },
+		.rpm = { 0 },
 	},
 	{
 		/* level 1 */
-		.on = {50, 60, 50, 49, -1},
-		.off = {47, 99, 47, 46, -1},
-		.rpm = {3600},
+		.on = { 50, 62, 50, 52, -1 },
+		.off = { 47, 99, 47, 49, -1 },
+		.rpm = { 3200 },
 	},
 	{
 		/* level 2 */
-		.on = {53, 60, 53, 52, -1},
-		.off = {49, 99, 49, 48, -1},
-		.rpm = {4100},
+		.on = { 53, 62, 53, 54, -1 },
+		.off = { 49, 99, 49, 51, -1 },
+		.rpm = { 4050 },
 	},
 	{
 		/* level 3 */
-		.on = {100, 100, 100, 100, -1},
-		.off = {51, 59, 51, 50, -1},
-		.rpm = {5500},
+		.on = { 100, 100, 100, 100, -1 },
+		.off = { 51, 60, 51, 52, -1 },
+		.rpm = { 5800 },
 	},
 };
 
@@ -82,33 +82,31 @@ static int fan_table_to_rpm(int fan, int *temp)
 	    temp[TEMP_SENSOR_4_DDR] < prev_tmp[TEMP_SENSOR_4_DDR]) {
 		for (i = current_level; i > 0; i--) {
 			if (temp[TEMP_SENSOR_1_SOC] <
-				fan_table[i].off[TEMP_SENSOR_1_SOC] &&
+				    fan_table[i].off[TEMP_SENSOR_1_SOC] &&
 			    temp[TEMP_SENSOR_2_CHARGER] <
-				fan_table[i].off[TEMP_SENSOR_2_CHARGER] &&
+				    fan_table[i].off[TEMP_SENSOR_2_CHARGER] &&
 			    temp[TEMP_SENSOR_3_WWAN] <
-				fan_table[i].off[TEMP_SENSOR_3_WWAN] &&
+				    fan_table[i].off[TEMP_SENSOR_3_WWAN] &&
 			    temp[TEMP_SENSOR_4_DDR] <
-				fan_table[i].off[TEMP_SENSOR_4_DDR])
+				    fan_table[i].off[TEMP_SENSOR_4_DDR])
 				current_level = i - 1;
 			else
 				break;
 		}
 	} else if (temp[TEMP_SENSOR_1_SOC] > prev_tmp[TEMP_SENSOR_1_SOC] ||
 		   temp[TEMP_SENSOR_2_CHARGER] >
-			prev_tmp[TEMP_SENSOR_2_CHARGER] ||
-		   temp[TEMP_SENSOR_3_WWAN] >
-			prev_tmp[TEMP_SENSOR_3_WWAN] ||
-		   temp[TEMP_SENSOR_4_DDR] >
-			prev_tmp[TEMP_SENSOR_4_DDR]) {
+			   prev_tmp[TEMP_SENSOR_2_CHARGER] ||
+		   temp[TEMP_SENSOR_3_WWAN] > prev_tmp[TEMP_SENSOR_3_WWAN] ||
+		   temp[TEMP_SENSOR_4_DDR] > prev_tmp[TEMP_SENSOR_4_DDR]) {
 		for (i = current_level; i < NUM_FAN_LEVELS; i++) {
 			if (temp[TEMP_SENSOR_1_SOC] >
-				fan_table[i].on[TEMP_SENSOR_1_SOC] ||
+				    fan_table[i].on[TEMP_SENSOR_1_SOC] ||
 			    (temp[TEMP_SENSOR_2_CHARGER] >
-				fan_table[i].on[TEMP_SENSOR_2_CHARGER] &&
-			    temp[TEMP_SENSOR_3_WWAN] >
-				fan_table[i].on[TEMP_SENSOR_3_WWAN]) ||
+				     fan_table[i].on[TEMP_SENSOR_2_CHARGER] &&
+			     temp[TEMP_SENSOR_3_WWAN] >
+				     fan_table[i].on[TEMP_SENSOR_3_WWAN]) ||
 			    temp[TEMP_SENSOR_4_DDR] >
-				fan_table[i].on[TEMP_SENSOR_4_DDR])
+				    fan_table[i].on[TEMP_SENSOR_4_DDR])
 				current_level = i + 1;
 			else
 				break;
@@ -129,10 +127,8 @@ static int fan_table_to_rpm(int fan, int *temp)
 
 void board_override_fan_control(int fan, int *tmp)
 {
-	if (chipset_in_state(CHIPSET_STATE_ON |
-		CHIPSET_STATE_ANY_SUSPEND)) {
+	if (chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND)) {
 		fan_set_rpm_mode(FAN_CH(fan), 1);
-		fan_set_rpm_target(FAN_CH(fan),
-			fan_table_to_rpm(fan, tmp));
+		fan_set_rpm_target(FAN_CH(fan), fan_table_to_rpm(fan, tmp));
 	}
 }
diff --git a/board/vell/usbc_config.c b/board/vell/usbc_config.c
index 6da618b42e..694ce202d1 100644
--- a/board/vell/usbc_config.c
+++ b/board/vell/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -35,8 +35,8 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 /* USBC TCPC configuration */
 const struct tcpc_config_t tcpc_config[] = {
@@ -85,21 +85,25 @@ struct ppc_config_t ppc_chips[] = {
 	[USBC_PORT_C0] = {
 		.i2c_port = I2C_PORT_USB_C0_C1_PPC,
 		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.frs_en = IOEX_USB_C0_FRS_EN,
 		.drv = &syv682x_drv,
 	},
 	[USBC_PORT_C1] = {
 		.i2c_port = I2C_PORT_USB_C0_C1_PPC,
 		.i2c_addr_flags = SYV682X_ADDR1_FLAGS,
+		.frs_en = IOEX_USB_C1_FRS_EN,
 		.drv = &syv682x_drv,
 	},
 	[USBC_PORT_C2] = {
 		.i2c_port = I2C_PORT_USB_C2_C3_PPC,
 		.i2c_addr_flags = SYV682X_ADDR2_FLAGS,
+		.frs_en = IOEX_USB_C2_FRS_EN,
 		.drv = &syv682x_drv,
 	},
 	[USBC_PORT_C3] = {
 		.i2c_port = I2C_PORT_USB_C2_C3_PPC,
 		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
+		.frs_en = IOEX_USB_C3_FRS_EN,
 		.drv = &syv682x_drv,
 	},
 };
@@ -110,63 +114,84 @@ unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 struct ppc_config_t ppc_chips_old_c3 = {
 	.i2c_port = I2C_PORT_USB_C2_C3_PPC,
 	.i2c_addr_flags = SYV682X_ADDR3_FLAGS,
+	.frs_en = IOEX_USB_C3_FRS_EN,
 	.drv = &syv682x_drv,
 };
 
 /* USBC mux configuration - Alder Lake includes internal mux */
-static const struct usb_mux usbc0_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+static const struct usb_mux_chain usbc0_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
-static const struct usb_mux usbc1_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+static const struct usb_mux_chain usbc1_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
-static const struct usb_mux usbc2_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C2,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+static const struct usb_mux_chain usbc2_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C2,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
-static const struct usb_mux usbc3_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C3,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+static const struct usb_mux_chain usbc3_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C3,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
 
-const struct usb_mux usb_muxes[] = {
+const struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C0_C1_MUX,
-		.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc0_tcss_usb_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C0_C1_MUX,
+			.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc0_tcss_usb_mux,
 	},
 	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C0_C1_MUX,
-		.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc1_tcss_usb_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C0_C1_MUX,
+			.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc1_tcss_usb_mux,
 	},
 	[USBC_PORT_C2] = {
-		.usb_port = USBC_PORT_C2,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C2_C3_MUX,
-		.i2c_addr_flags = USBC_PORT_C2_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc2_tcss_usb_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C2,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C2_C3_MUX,
+			.i2c_addr_flags = USBC_PORT_C2_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc2_tcss_usb_mux,
 	},
 	[USBC_PORT_C3] = {
-		.usb_port = USBC_PORT_C3,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_C2_C3_MUX,
-		.i2c_addr_flags = USBC_PORT_C3_BB_RETIMER_I2C_ADDR,
-		.next_mux = &usbc3_tcss_usb_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C3,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C2_C3_MUX,
+			.i2c_addr_flags = USBC_PORT_C3_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc3_tcss_usb_mux,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
@@ -253,8 +278,8 @@ int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
 	}
 
 	if (voltage < BC12_MIN_VOLTAGE) {
-		CPRINTS("%s: port %d: vbus %d lower than %d", __func__,
-			port, voltage, BC12_MIN_VOLTAGE);
+		CPRINTS("%s: port %d: vbus %d lower than %d", __func__, port,
+			voltage, BC12_MIN_VOLTAGE);
 		return 1;
 	}
 
diff --git a/board/vell/usbc_config.h b/board/vell/usbc_config.h
index 447c03efb3..694b316ee8 100644
--- a/board/vell/usbc_config.h
+++ b/board/vell/usbc_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,7 +8,7 @@
 #ifndef __CROS_EC_USBC_CONFIG_H
 #define __CROS_EC_USBC_CONFIG_H
 
-#define CONFIG_USB_PD_PORT_MAX_COUNT	4
+#define CONFIG_USB_PD_PORT_MAX_COUNT 4
 
 enum usbc_port {
 	USBC_PORT_C0 = 0,
diff --git a/board/vilboz/battery.c b/board/vilboz/battery.c
index 6f6bca7662..a119ce38e8 100644
--- a/board/vilboz/battery.c
+++ b/board/vilboz/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -387,9 +387,9 @@ struct chg_curr_step {
 };
 
 static const struct chg_curr_step chg_curr_table[] = {
-	{.on = 0, .off = 35, .curr_ma = 2800},
-	{.on = 36, .off = 35, .curr_ma = 1500},
-	{.on = 39, .off = 38, .curr_ma = 1000},
+	{ .on = 0, .off = 35, .curr_ma = 2800 },
+	{ .on = 36, .off = 35, .curr_ma = 1500 },
+	{ .on = 39, .off = 38, .curr_ma = 1000 },
 };
 
 /* All charge current tables must have the same number of levels */
diff --git a/board/vilboz/board.c b/board/vilboz/board.c
index 4e0461469d..7c74794d9d 100644
--- a/board/vilboz/board.c
+++ b/board/vilboz/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,7 +11,7 @@
 #include "driver/accelgyro_lsm6dsm.h"
 #include "driver/bc12/pi3usb9201.h"
 #include "driver/ioexpander/pcal6408.h"
-#include "driver/ppc/aoz1380.h"
+#include "driver/ppc/aoz1380_public.h"
 #include "driver/tcpm/nct38xx.h"
 #include "driver/usb_mux/amd_fp5.h"
 #include "extpower.h"
@@ -33,8 +33,8 @@
 #include "usb_mux.h"
 #include "usbc_ppc.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* This I2C moved. Temporarily detect and support the V0 HW. */
 int I2C_PORT_BATTERY = I2C_PORT_BATTERY_V1;
@@ -55,17 +55,13 @@ static struct stprivate_data g_lis2dwl_data;
 static struct lsm6dsm_data g_lsm6dsm_data = LSM6DSM_DATA;
 
 /* Matrix to rotate accelrator into standard reference frame */
-static const mat33_fp_t base_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, FLOAT_TO_FP(-1), 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
 
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
 /* TODO(gcc >= 5.0) Remove the casts to const pointer at rot_standard_ref */
 struct motion_sensor_t motion_sensors[] = {
@@ -180,18 +176,23 @@ const struct usb_mux_driver usbc0_sbu_mux_driver = {
  * Since FSUSB42UMX is not a i2c device, .i2c_port and
  * .i2c_addr_flags are not required here.
  */
-const struct usb_mux usbc0_sbu_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &usbc0_sbu_mux_driver,
+const struct usb_mux_chain usbc0_sbu_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &usbc0_sbu_mux_driver,
+		},
 };
 
-const struct usb_mux usb_muxes[] = {
+const struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.i2c_port = I2C_PORT_USB_AP_MUX,
-		.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
-		.driver = &amd_fp5_usb_mux_driver,
-		.next_mux = &usbc0_sbu_mux,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.i2c_port = I2C_PORT_USB_AP_MUX,
+			.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
+			.driver = &amd_fp5_usb_mux_driver,
+		},
+		.next = &usbc0_sbu_mux,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
@@ -219,8 +220,7 @@ void ppc_interrupt(enum gpio_signal signal)
 
 int board_set_active_charge_port(int port)
 {
-	int is_valid_port = (port >= 0 &&
-			     port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	int i;
 
 	if (port == CHARGE_PORT_NONE) {
@@ -241,7 +241,6 @@ int board_set_active_charge_port(int port)
 		return EC_ERROR_INVAL;
 	}
 
-
 	/* Check if the port is sourcing VBUS. */
 	if (ppc_is_sourcing_vbus(port)) {
 		CPRINTFUSB("Skip enable C%d", port);
@@ -323,7 +322,6 @@ static void reset_nct38xx_port(int port)
 		msleep(NCT3807_RESET_POST_DELAY_MS);
 }
 
-
 void board_reset_pd_mcu(void)
 {
 	/* Reset TCPC0 */
@@ -367,8 +365,7 @@ int board_pd_set_frs_enable(int port, int enable)
 
 	/* Use the TCPC to enable fast switch when FRS included */
 	if (port == USBC_PORT_C0) {
-		rv = ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN,
-				    !!enable);
+		rv = ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN, !!enable);
 	}
 
 	return rv;
@@ -509,7 +506,7 @@ const int usb_port_enable[USBA_PORT_COUNT] = {
 };
 
 __override void board_set_charge_limit(int port, int supplier, int charge_ma,
-			int max_ma, int charge_mv)
+				       int max_ma, int charge_mv)
 {
 	/*
 	 * Limit the input current to 95% negotiated limit,
@@ -517,7 +514,6 @@ __override void board_set_charge_limit(int port, int supplier, int charge_ma,
 	 */
 	charge_ma = charge_ma * 95 / 100;
 
-	charge_set_input_current_limit(MAX(charge_ma,
-				CONFIG_CHARGER_INPUT_CURRENT),
-				charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
diff --git a/board/vilboz/board.h b/board/vilboz/board.h
index 91a7d6e868..5160abbc26 100644
--- a/board/vilboz/board.h
+++ b/board/vilboz/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -42,39 +42,35 @@
 #define CONFIG_POWER_BUTTON_INIT_TIMEOUT 4
 
 /* GPIO mapping from board specific name to EC common name. */
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_EC_BATT_PRES_ODL
-#define CONFIG_SCI_GPIO			GPIO_EC_FCH_SCI_ODL
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_AP_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT_L		GPIO_EC_EDP_BL_DISABLE
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_FCH_PWR_BTN_L
-#define GPIO_PCH_RSMRST_L		GPIO_EC_FCH_RSMRST_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S5_L		GPIO_SLP_S5_L
-#define GPIO_PCH_SYS_PWROK		GPIO_EC_FCH_PWROK
-#define GPIO_PCH_WAKE_L			GPIO_EC_FCH_WAKE_L
-#define GPIO_POWER_BUTTON_L		GPIO_EC_PWR_BTN_ODL
-#define GPIO_S0_PGOOD			GPIO_S0_PWROK_OD
-#define GPIO_S5_PGOOD			GPIO_EC_PWROK_OD
-#define GPIO_SYS_RESET_L		GPIO_EC_SYS_RST_L
-#define GPIO_VOLUME_DOWN_L		GPIO_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
+#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL
+#define CONFIG_SCI_GPIO GPIO_EC_FCH_SCI_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_AP_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_EDP_BL_DISABLE
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PCH_PWRBTN_L GPIO_EC_FCH_PWR_BTN_L
+#define GPIO_PCH_RSMRST_L GPIO_EC_FCH_RSMRST_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L
+#define GPIO_PCH_SYS_PWROK GPIO_EC_FCH_PWROK
+#define GPIO_PCH_WAKE_L GPIO_EC_FCH_WAKE_L
+#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL
+#define GPIO_S0_PGOOD GPIO_S0_PWROK_OD
+#define GPIO_S5_PGOOD GPIO_EC_PWROK_OD
+#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L
+#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
 
 #ifndef __ASSEMBLER__
 
 /* This I2C moved. Temporarily detect and support the V0 HW. */
 extern int I2C_PORT_BATTERY;
 
-enum adc_channel {
-	ADC_TEMP_SENSOR_CHARGER,
-	ADC_TEMP_SENSOR_SOC,
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_TEMP_SENSOR_CHARGER, ADC_TEMP_SENSOR_SOC, ADC_CH_COUNT };
 
 enum battery_type {
 	BATTERY_SMP,
@@ -91,19 +87,11 @@ enum battery_type {
 	BATTERY_TYPE_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_COUNT };
 
-enum ioex_port {
-	IOEX_C0_NCT3807 = 0,
-	IOEX_PORT_COUNT
-};
+enum ioex_port { IOEX_C0_NCT3807 = 0, IOEX_PORT_COUNT };
 
-#define PORT_TO_HPD(port) ((port == 0) \
-	? GPIO_USB3_C0_DP2_HPD \
-	: GPIO_DP1_HPD)
+#define PORT_TO_HPD(port) ((port == 0) ? GPIO_USB3_C0_DP2_HPD : GPIO_DP1_HPD)
 
 enum temp_sensor_id {
 	TEMP_SENSOR_CHARGER = 0,
@@ -112,16 +100,9 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum usba_port {
-	USBA_PORT_A0 = 0,
-	USBA_PORT_A1,
-	USBA_PORT_COUNT
-};
+enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT };
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_COUNT };
 
 /*****************************************************************************
  * CBI EC FW Configuration
diff --git a/board/vilboz/build.mk b/board/vilboz/build.mk
index 1c0cbc4f63..45c71f962c 100644
--- a/board/vilboz/build.mk
+++ b/board/vilboz/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/vilboz/ec.tasklist b/board/vilboz/ec.tasklist
index 08801d1786..864ca42492 100644
--- a/board/vilboz/ec.tasklist
+++ b/board/vilboz/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/vilboz/gpio.inc b/board/vilboz/gpio.inc
index 78baa0eccc..6897f16890 100644
--- a/board/vilboz/gpio.inc
+++ b/board/vilboz/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/vilboz/led.c b/board/vilboz/led.c
index 4e9697ddbb..fa28eb5f40 100644
--- a/board/vilboz/led.c
+++ b/board/vilboz/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,44 +8,49 @@
 #include "led_common.h"
 #include "led_onoff_states.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
 __override const int led_charge_lvl_1 = 5;
 __override const int led_charge_lvl_2 = 97;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]       = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,  1 * LED_ONE_SEC},
-					{LED_OFF, 1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,  2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
 
 BUILD_ASSERT(ARRAY_SIZE(led_bat_state_table) == LED_NUM_STATES);
 
 __override const struct led_descriptor
-			led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-				{LED_OFF,          0.5 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-				{LED_OFF,          0.5 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 3 * LED_ONE_SEC },
+					       { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    3 * LED_ONE_SEC },
+						  { LED_OFF,
+						    0.5 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
 BUILD_ASSERT(ARRAY_SIZE(led_pwr_state_table) == PWR_LED_NUM_STATES);
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
diff --git a/board/voema/battery.c b/board/voema/battery.c
index d345cb72ec..dcd45d31fd 100644
--- a/board/voema/battery.c
+++ b/board/voema/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/voema/board.c b/board/voema/board.c
index c5afc2dee7..c4563df105 100644
--- a/board/voema/board.c
+++ b/board/voema/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -42,7 +42,7 @@
 
 #include "gpio_list.h" /* Must come after other header files. */
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 /* Keyboard scan setting */
 __override struct keyboard_scan_config keyscan_config = {
@@ -77,8 +77,8 @@ static const struct ec_response_keybd_config voema_kb = {
 	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
 };
 
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	return &voema_kb;
 }
@@ -89,16 +89,15 @@ __override const struct ec_response_keybd_config
  * that we don't have pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-	{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-	{0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3},
-	{-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0},
-	{1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4},
-	{2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0},
-	{-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1},
-	{-1, -1},
+	{ -1, -1 }, { 0, 5 },	{ 1, 1 }, { 1, 0 },   { 0, 6 },	  { 0, 7 },
+	{ -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 },   { -1, -1 }, { 1, 6 },
+	{ 1, 7 },   { 3, 1 },	{ 2, 0 }, { 1, 5 },   { 2, 6 },	  { 2, 7 },
+	{ 2, 1 },   { 2, 4 },	{ 2, 5 }, { 1, 2 },   { 2, 3 },	  { 2, 2 },
+	{ 3, 0 },   { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 },	  { -1, -1 },
+	{ -1, -1 },
 };
 const int keyboard_factory_scan_pins_used =
-		ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 
 /******************************************************************************/
 /*
@@ -124,8 +123,8 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CPU \
-	{ \
+#define THERMAL_CPU              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
@@ -150,8 +149,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_INDUCTOR \
-	{ \
+#define THERMAL_INDUCTOR         \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
@@ -241,8 +240,7 @@ static void ps8815_reset(void)
 	int val;
 
 	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 0);
-	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS,
-			   PS8815_PWR_H_RST_H_DELAY_MS));
+	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS));
 	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 1);
 	msleep(PS8815_FW_INIT_DELAY_MS);
 
@@ -253,16 +251,16 @@ static void ps8815_reset(void)
 
 	CPRINTS("%s: patching ps8815 registers", __func__);
 
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
+	if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) ==
+	    EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f was %02x", val);
 
-	if (i2c_write8(I2C_PORT_USB_C1,
-		       PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) == EC_SUCCESS)
+	if (i2c_write8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f,
+		       0x31) == EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f set to 0x31");
 
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
+	if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) ==
+	    EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f now %02x", val);
 }
 
@@ -272,7 +270,7 @@ void board_reset_pd_mcu(void)
 	/* Daughterboard specific reset for port 1 */
 	ps8815_reset();
 	usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
 
 __override void board_cbi_init(void)
@@ -360,26 +358,33 @@ BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
  * virtual_usb_mux_driver so the AP gets notified of mux changes and updates
  * the TCSS configuration on state changes.
  */
-static const struct usb_mux usbc1_usb3_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	.next_mux = NULL,
+static const struct usb_mux_chain usbc1_usb3_db_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
+	.next = NULL,
 };
 
 /******************************************************************************/
 /* USBC mux configuration - Tiger Lake includes internal mux */
-const struct usb_mux usb_muxes[] = {
+const struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 	},
 	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc1_usb3_db_retimer,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc1_usb3_db_retimer,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
diff --git a/board/voema/board.h b/board/voema/board.h
index b5f8dc4ec8..f10192b0b6 100644
--- a/board/voema/board.h
+++ b/board/voema/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -45,7 +45,7 @@
 
 /* TCS3400 ALS */
 #define CONFIG_ALS
-#define ALS_COUNT		1
+#define ALS_COUNT 1
 #define CONFIG_ALS_TCS3400
 #define CONFIG_ALS_TCS3400_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS)
@@ -55,36 +55,36 @@
 
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE		BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID		LID_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
 
 /* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
 
 /* TODO: b/144165680 - measure and check these values on Volteer */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
 
 /*
  * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
  * cables only support up to 60W.
  */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		65000
-#define PD_MAX_CURRENT_MA	3250
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 65000
+#define PD_MAX_CURRENT_MA 3250
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Enabling Thunderbolt-compatible mode */
 #define CONFIG_USB_PD_TBT_COMPAT_MODE
 
 /* USB Type A Features */
-#define USB_PORT_COUNT			1
+#define USB_PORT_COUNT 1
 #define CONFIG_USB_PORT_POWER_DUMB
 
 /* USBC PPC*/
 #undef CONFIG_SYV682X_HV_ILIM
 #define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_5_50
-#define CONFIG_USBC_PPC_SYV682X		/* USBC port C0/C1 */
+#define CONFIG_USBC_PPC_SYV682X /* USBC port C0/C1 */
 #define CONFIG_USB_PD_FRS_PPC
 #undef CONFIG_USB_PD_TCPC_RUNTIME_CONFIG
 #undef CONFIG_USB_PD_TCPM_TUSB422
@@ -98,8 +98,8 @@
 #undef CONFIG_FANS
 
 /* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 
 /* Retimer */
 #undef CONFIG_USBC_RETIMER_INTEL_BB
@@ -111,45 +111,44 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_DSW_PWROK		GPIO_EC_PCH_DSW_PWROK
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_LID_OPEN GPIO_EC_LID_OPEN
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
 
 /* I2C Bus Configuration */
 #define CONFIG_I2C
-#define I2C_PORT_ACCEL		I2C_PORT_SENSOR
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_1_MIX	NPCX_I2C_PORT3_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT3_0
+#define I2C_PORT_POWER NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+
+#define I2C_PORT_BATTERY I2C_PORT_POWER
+#define I2C_PORT_CHARGER I2C_PORT_EEPROM
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 #define CONFIG_I2C_CONTROLLER
 
-
 #ifndef __ASSEMBLER__
 
 #include "gpio_signal.h"
@@ -161,10 +160,7 @@ enum battery_type {
 	BATTERY_TYPE_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_COUNT };
 
 enum sensor_id {
 	LID_ACCEL = 0,
@@ -175,11 +171,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 void board_reset_pd_mcu(void);
 void motion_interrupt(enum gpio_signal signal);
diff --git a/board/voema/build.mk b/board/voema/build.mk
index d7d771ebab..7d375fe291 100644
--- a/board/voema/build.mk
+++ b/board/voema/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/voema/ec.tasklist b/board/voema/ec.tasklist
index 3e20d8ae39..c29125d517 100644
--- a/board/voema/ec.tasklist
+++ b/board/voema/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/voema/gpio.inc b/board/voema/gpio.inc
index 7506ccdbd1..e1a931094c 100644
--- a/board/voema/gpio.inc
+++ b/board/voema/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,7 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
diff --git a/board/voema/led.c b/board/voema/led.c
index 25e71c262d..bb808e6d72 100644
--- a/board/voema/led.c
+++ b/board/voema/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,23 +19,28 @@ __override const int led_charge_lvl_1 = 5;
 __override const int led_charge_lvl_2 = 95;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
diff --git a/board/voema/sensors.c b/board/voema/sensors.c
index b55890b074..d532a64148 100644
--- a/board/voema/sensors.c
+++ b/board/voema/sensors.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -90,23 +90,17 @@ static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
 };
 
 /* Rotation matrix for the lid accelerometer */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
 
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+				       { FLOAT_TO_FP(-1), 0, 0 },
+				       { 0, 0, FLOAT_TO_FP(-1) } };
 
-const mat33_fp_t base_icm_ref = {
-	{ FLOAT_TO_FP(1), 0,  0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0,  FLOAT_TO_FP(-1)}
-};
+const mat33_fp_t base_icm_ref = { { FLOAT_TO_FP(1), 0, 0 },
+				  { 0, FLOAT_TO_FP(-1), 0 },
+				  { 0, 0, FLOAT_TO_FP(-1) } };
 
 struct motion_sensor_t kx022_lid_accel = {
 	.name = "Lid Accel",
@@ -256,20 +250,20 @@ struct motion_sensor_t icm_base_accel = {
 };
 
 struct motion_sensor_t icm_base_gyro = {
-		 .name = "Base Gyro",
-		 .active_mask = SENSOR_ACTIVE_S0_S3,
-		 .chip = MOTIONSENSE_CHIP_ICM426XX,
-		 .type = MOTIONSENSE_TYPE_GYRO,
-		 .location = MOTIONSENSE_LOC_BASE,
-		 .drv = &icm426xx_drv,
-		 .mutex = &g_base_mutex,
-		 .drv_data = &g_icm426xx_data,
-		 .port = I2C_PORT_SENSOR,
-		 .i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
-		 .default_range = 1000, /* dps */
-		 .rot_standard_ref = &base_icm_ref,
-		 .min_frequency = ICM426XX_GYRO_MIN_FREQ,
-		 .max_frequency = ICM426XX_GYRO_MAX_FREQ,
+	.name = "Base Gyro",
+	.active_mask = SENSOR_ACTIVE_S0_S3,
+	.chip = MOTIONSENSE_CHIP_ICM426XX,
+	.type = MOTIONSENSE_TYPE_GYRO,
+	.location = MOTIONSENSE_LOC_BASE,
+	.drv = &icm426xx_drv,
+	.mutex = &g_base_mutex,
+	.drv_data = &g_icm426xx_data,
+	.port = I2C_PORT_SENSOR,
+	.i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS,
+	.default_range = 1000, /* dps */
+	.rot_standard_ref = &base_icm_ref,
+	.min_frequency = ICM426XX_GYRO_MIN_FREQ,
+	.max_frequency = ICM426XX_GYRO_MAX_FREQ,
 };
 
 /* ALS instances when LPC mapping is needed. Each entry directs to a sensor. */
diff --git a/board/volet/battery.c b/board/volet/battery.c
index 2e4fb7dc71..89769e8364 100644
--- a/board/volet/battery.c
+++ b/board/volet/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/volet/board.c b/board/volet/board.c
index 94bfa447b4..474ec9cb0e 100644
--- a/board/volet/board.c
+++ b/board/volet/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -44,7 +44,7 @@
 
 #include "gpio_list.h" /* Must come after other header files. */
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 static const struct ec_response_keybd_config volet_kb = {
 	.num_top_row_keys = 10,
@@ -80,8 +80,8 @@ static const struct ec_response_keybd_config volet_kb_num = {
 	.capabilities = KEYBD_CAP_SCRNLOCK_KEY | KEYBD_CAP_NUMERIC_KEYPAD,
 };
 
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	if (!ec_cfg_has_numeric_pad())
 		return &volet_kb;
@@ -112,16 +112,15 @@ __override struct keyboard_scan_config keyscan_config = {
  * that we don't have pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-	{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-	{0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3},
-	{-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0},
-	{1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4},
-	{2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0},
-	{-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1},
-	{-1, -1},
+	{ -1, -1 }, { 0, 5 },	{ 1, 1 }, { 1, 0 },   { 0, 6 },	  { 0, 7 },
+	{ -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 },   { -1, -1 }, { 1, 6 },
+	{ 1, 7 },   { 3, 1 },	{ 2, 0 }, { 1, 5 },   { 2, 6 },	  { 2, 7 },
+	{ 2, 1 },   { 2, 4 },	{ 2, 5 }, { 1, 2 },   { 2, 3 },	  { 2, 2 },
+	{ 3, 0 },   { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 },	  { -1, -1 },
+	{ -1, -1 },
 };
 const int keyboard_factory_scan_pins_used =
-		ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 
 __override uint32_t board_override_feature_flags0(uint32_t flags0)
 {
@@ -147,7 +146,7 @@ union volteer_cbi_fw_config fw_config_defaults = {
 
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
@@ -184,8 +183,8 @@ const struct fan_t fans[FAN_CH_COUNT] = {
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CPU \
-	{ \
+#define THERMAL_CPU              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(85), \
@@ -299,8 +298,7 @@ static void ps8815_reset(void)
 	int val;
 
 	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 0);
-	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS,
-			   PS8815_PWR_H_RST_H_DELAY_MS));
+	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS));
 	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 1);
 	msleep(PS8815_FW_INIT_DELAY_MS);
 
@@ -311,16 +309,16 @@ static void ps8815_reset(void)
 
 	CPRINTS("%s: patching ps8815 registers", __func__);
 
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
+	if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) ==
+	    EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f was %02x", val);
 
-	if (i2c_write8(I2C_PORT_USB_C1,
-		       PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) == EC_SUCCESS)
+	if (i2c_write8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f,
+		       0x31) == EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f set to 0x31");
 
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
+	if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) ==
+	    EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f now %02x", val);
 }
 
@@ -332,7 +330,7 @@ void board_reset_pd_mcu(void)
 	 */
 	ps8815_reset();
 	usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
 
 /******************************************************************************/
@@ -432,26 +430,33 @@ BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
  * virtual_usb_mux_driver so the AP gets notified of mux changes and updates
  * the TCSS configuration on state changes.
  */
-static const struct usb_mux usbc1_usb3_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	.next_mux = NULL,
+static const struct usb_mux_chain usbc1_usb3_db_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
+	.next = NULL,
 };
 
 /******************************************************************************/
 /* USBC mux configuration - Tiger Lake includes internal mux */
-const struct usb_mux usb_muxes[] = {
+const struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 	},
 	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc1_usb3_db_retimer,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc1_usb3_db_retimer,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
diff --git a/board/volet/board.h b/board/volet/board.h
index c75eeed31f..c616b1cbe1 100644
--- a/board/volet/board.h
+++ b/board/volet/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,7 +13,7 @@
 
 /* Optional features */
 #undef NPCX7_PWM1_SEL
-#define NPCX7_PWM1_SEL    0    /* GPIO C2 is not used as PWM1. */
+#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */
 
 /*
  * The RAM and flash size combination on the the NPCX797FC does not leave
@@ -47,7 +47,7 @@
 #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
 /* BMI160 Base accel/gyro */
 #define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCELGYRO_ICM426XX	/* Base accel second source*/
+#define CONFIG_ACCELGYRO_ICM426XX /* Base accel second source*/
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 #define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
@@ -57,27 +57,27 @@
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
 
 /* BMA253 Lid accel */
-#define CONFIG_ACCEL_KX022	/* Lid accel */
+#define CONFIG_ACCEL_KX022 /* Lid accel */
 #define CONFIG_ACCEL_BMA255
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE	BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID	LID_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
 
 /* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
 
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
 
 /*
  * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
  * cables only support up to 60W.
  */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 #define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
 #ifdef BOARD_VOXEL_ECMODEENTRY
@@ -88,11 +88,11 @@
 #define CONFIG_USB_PD_TBT_COMPAT_MODE
 
 /* USB Type A Features */
-#define USB_PORT_COUNT			1
+#define USB_PORT_COUNT 1
 #define CONFIG_USB_PORT_POWER_DUMB
 
 /* USBC PPC*/
-#define CONFIG_USBC_PPC_SYV682X		/* USBC port C0/C1 */
+#define CONFIG_USBC_PPC_SYV682X /* USBC port C0/C1 */
 #define CONFIG_USB_PD_FRS_PPC
 #undef CONFIG_USB_PD_TCPC_RUNTIME_CONFIG
 #undef CONFIG_USB_PD_TCPM_TUSB422
@@ -105,8 +105,8 @@
 /* Fan features */
 
 /* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 
 /* Retimer */
 #undef CONFIG_USBC_RETIMER_INTEL_BB
@@ -118,44 +118,43 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_DSW_PWROK		GPIO_EC_PCH_DSW_PWROK
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_LID_OPEN GPIO_EC_LID_OPEN
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
 
 /* I2C Bus Configuration */
 #define CONFIG_I2C
-#define I2C_PORT_ACCEL		I2C_PORT_SENSOR
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0
+#define I2C_PORT_POWER NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
 
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
+#define I2C_PORT_BATTERY I2C_PORT_POWER
+#define I2C_PORT_CHARGER I2C_PORT_EEPROM
 
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 #define CONFIG_I2C_CONTROLLER
 
-
 #ifndef __ASSEMBLER__
 
 #include "gpio_signal.h"
@@ -168,11 +167,7 @@ enum battery_type {
 	BATTERY_TYPE_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_FAN,
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_FAN, PWM_CH_KBLIGHT, PWM_CH_COUNT };
 
 enum sensor_id {
 	LID_ACCEL = 0,
@@ -181,11 +176,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 void board_reset_pd_mcu(void);
 
diff --git a/board/volet/build.mk b/board/volet/build.mk
index 546bcba8d2..18397fdec3 100644
--- a/board/volet/build.mk
+++ b/board/volet/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/volet/ec.tasklist b/board/volet/ec.tasklist
index ca6d9fbf14..07a91894ed 100644
--- a/board/volet/ec.tasklist
+++ b/board/volet/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/volet/gpio.inc b/board/volet/gpio.inc
index 16471d0817..079c731785 100644
--- a/board/volet/gpio.inc
+++ b/board/volet/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,7 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
diff --git a/board/volet/led.c b/board/volet/led.c
index ba4af36163..dceadd416f 100644
--- a/board/volet/led.c
+++ b/board/volet/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,23 +19,28 @@ __override const int led_charge_lvl_1 = 5;
 __override const int led_charge_lvl_2 = 95;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
diff --git a/board/volet/sensors.c b/board/volet/sensors.c
index fb093729d3..0ea3f4b74a 100644
--- a/board/volet/sensors.c
+++ b/board/volet/sensors.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,7 +24,7 @@
 #include "tablet_mode.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ##args)
 /******************************************************************************/
 /* Sensors */
 static struct mutex g_lid_accel_mutex;
@@ -39,23 +39,17 @@ static struct bmi_drv_data_t g_bmi160_data;
 static struct icm_drv_data_t g_icm426xx_data;
 
 /* Rotation matrix for the lid accelerometer */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
 
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+				       { FLOAT_TO_FP(-1), 0, 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
 
-static const mat33_fp_t base_icm_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t base_icm_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					 { 0, FLOAT_TO_FP(1), 0 },
+					 { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t kx022_lid_accel = {
 	.name = "Lid Accel",
@@ -228,8 +222,7 @@ static void board_sensors_init(void)
 		motion_sensor_count = 0;
 		gmr_tablet_switch_disable();
 		/* Base accel is not stuffed, don't allow line to float */
-		gpio_set_flags(GPIO_EC_IMU_INT_L,
-			       GPIO_INPUT | GPIO_PULL_DOWN);
+		gpio_set_flags(GPIO_EC_IMU_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
 	}
 }
 DECLARE_HOOK(HOOK_INIT, board_sensors_init, HOOK_PRIO_DEFAULT);
diff --git a/board/volmar/battery.c b/board/volmar/battery.c
index 3832fd8edf..852ed4b137 100644
--- a/board/volmar/battery.c
+++ b/board/volmar/battery.c
@@ -1,12 +1,16 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Battery pack vendor provided charging profile
  */
 
+#include "battery.h"
 #include "battery_fuel_gauge.h"
 #include "cbi.h"
+#include "charge_ramp.h"
+#include "charge_state.h"
+#include "charger_profile_override.h"
 #include "common.h"
 #include "compile_time_macros.h"
 #include "gpio.h"
@@ -64,6 +68,37 @@ const struct board_batt_params board_battery_info[] = {
 			.discharging_max_c      = 75,
 		},
 	},
+	/* COSMX AP20CBL Battery Information (new firmware ver) */
+	[BATTERY_COSMX_AP20CBL_004] = {
+		.fuel_gauge = {
+			.manuf_name = "COSMX KT0030B004",
+			.device_name = "AP20CBL",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.mfgacc_support = 1,
+				.reg_addr = 0x0,
+				.reg_mask = 0x2000,
+				.disconnect_val = 0x2000,
+				.cfet_mask = 0x4000,
+				.cfet_off_val = 0x4000,
+			},
+		},
+		.batt_info = {
+			.voltage_max            = 13200,
+			.voltage_normal         = 11550,
+			.voltage_min            = 9000,
+			.precharge_current      = 256,
+			.start_charging_min_c   = 0,
+			.start_charging_max_c   = 50,
+			.charging_min_c         = 0,
+			.charging_max_c         = 60,
+			.discharging_min_c      = -20,
+			.discharging_max_c      = 75,
+		},
+	},
 	/* LGC AP18C8K Battery Information */
 	[BATTERY_LGC_AP18C8K] = {
 		.fuel_gauge = {
@@ -131,3 +166,73 @@ enum battery_present battery_hw_present(void)
 	/* The GPIO is low when the battery is physically present */
 	return gpio_get_level(GPIO_EC_BATT_PRES_ODL) ? BP_NO : BP_YES;
 }
+
+static int charger_should_discharge_on_ac(struct charge_state_data *curr)
+{
+	/* can not discharge on AC without battery */
+	if (curr->batt.is_present != BP_YES)
+		return 0;
+
+	/* Do not discharge when battery disconnect */
+	if (battery_get_disconnect_state() != BATTERY_NOT_DISCONNECTED)
+		return 0;
+
+	/* Do not discharge on AC if the battery is still waking up */
+	if ((curr->batt.flags & BATT_FLAG_BAD_STATUS) ||
+	    (!(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
+	     !(curr->batt.status & STATUS_FULLY_CHARGED)))
+		return 0;
+
+	/*
+	 * In heavy load (>3A being withdrawn from VSYS) the DCDC of the
+	 * charger operates on hybrid mode. This causes a slight voltage
+	 * ripple on VSYS that falls in the audible noise frequency (single
+	 * digit kHz range). This small ripple generates audible noise in
+	 * the output ceramic capacitors (caps on VSYS and any input of
+	 * DCDC under VSYS).
+	 *
+	 * To overcome this issue, force battery discharging when battery
+	 * full, So the battery MOS of NVDC charger will turn on always,
+	 * it make the Vsys same as Vbat and the noise has been improved.
+	 */
+	if (!battery_is_cut_off() &&
+	    !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) &&
+	    (curr->batt.status & STATUS_FULLY_CHARGED))
+		return 1;
+
+	return 0;
+}
+
+/*
+ * This can override the smart battery's charging profile. To make a change,
+ * modify one or more of requested_voltage, requested_current, or state.
+ * Leave everything else unchanged.
+ *
+ * Return the next poll period in usec, or zero to use the default (which is
+ * state dependent).
+ */
+int charger_profile_override(struct charge_state_data *curr)
+{
+	int disch_on_ac = charger_should_discharge_on_ac(curr);
+
+	charger_discharge_on_ac(disch_on_ac);
+
+	if (disch_on_ac) {
+		curr->state = ST_DISCHARGE;
+		return 0;
+	}
+
+	return 0;
+}
+
+enum ec_status charger_profile_override_get_param(uint32_t param,
+						  uint32_t *value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+enum ec_status charger_profile_override_set_param(uint32_t param,
+						  uint32_t value)
+{
+	return EC_RES_INVALID_PARAM;
+}
diff --git a/board/volmar/board.c b/board/volmar/board.c
index 8875d49caf..865e1ce5bb 100644
--- a/board/volmar/board.c
+++ b/board/volmar/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,15 +20,14 @@
 #include "power.h"
 #include "registers.h"
 #include "switch.h"
-#include "tablet_mode.h"
 #include "throttle_ap.h"
 #include "usbc_config.h"
 
 #include "gpio_list.h" /* Must come after other header files. */
 
 /* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 __override void board_cbi_init(void)
 {
@@ -53,7 +52,6 @@ static void board_chipset_suspend(void)
 }
 DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
 
-
 /* keyboard factory test */
 #ifdef CONFIG_KEYBOARD_FACTORY_TEST
 /*
@@ -62,15 +60,14 @@ DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
  * that we don't have pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-	{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-	{0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3},
-	{-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0},
-	{1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4},
-	{2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0},
-	{-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1},
-	{-1, -1},
+	{ -1, -1 }, { 0, 5 },	{ 1, 1 }, { 1, 0 },   { 0, 6 },	  { 0, 7 },
+	{ -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 },   { -1, -1 }, { 1, 6 },
+	{ 1, 7 },   { 3, 1 },	{ 2, 0 }, { 1, 5 },   { 2, 6 },	  { 2, 7 },
+	{ 2, 1 },   { 2, 4 },	{ 2, 5 }, { 1, 2 },   { 2, 3 },	  { 2, 2 },
+	{ 3, 0 },   { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 },	  { -1, -1 },
+	{ -1, -1 },
 };
 
 const int keyboard_factory_scan_pins_used =
-			ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 #endif
diff --git a/board/volmar/board.h b/board/volmar/board.h
index e8b355d4b5..12561dc314 100644
--- a/board/volmar/board.h
+++ b/board/volmar/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,11 +21,16 @@
 
 #define CONFIG_MP2964
 
+/* Tablet mode is not supported */
+#undef CONFIG_TABLET_MODE
+#undef CONFIG_TABLET_MODE_SWITCH
+#undef CONFIG_LID_ANGLE
+
 /* LED */
 #define CONFIG_LED_ONOFF_STATES
 
 /* USB Type A Features */
-#define USB_PORT_COUNT			1
+#define USB_PORT_COUNT 1
 #define CONFIG_USB_PORT_POWER_DUMB
 
 /* USB Type C and USB PD defines */
@@ -46,17 +51,20 @@
 #define CONFIG_USBC_PPC_SYV682X
 
 /* TODO: b/177608416 - measure and check these values on brya */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-#define PD_VCONN_SWAP_DELAY		5000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
 
 /*
  * Passive USB-C cables only support up to 60W.
  */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
+
+#define CONFIG_CHARGER_PROFILE_OVERRIDE
+#define CONFIG_PWR_STATE_DISCHARGE_FULL
 
 /*
  * Macros for GPIO signals used in common code that don't match the
@@ -64,60 +72,60 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT		GPIO_EC_EN_EDP_BL
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_GSC_PACKET_MODE
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_L
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SYS_SLP_S0IX_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_TEMP_SENSOR_POWER		GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK
 
 /*
  * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup
  * signal.
  */
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_SEQ_EC_ALL_SYS_PG
-#define GPIO_PG_EC_DSW_PWROK		GPIO_SEQ_EC_DSW_PWROK
-#define GPIO_PG_EC_RSMRST_ODL		GPIO_SEQ_EC_RSMRST_ODL
-#define GPIO_POWER_BUTTON_L		GPIO_GSC_EC_PWR_BTN_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_ODL
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL
+#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG
+#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK
+#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL
+#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_WP_L GPIO_EC_WP_ODL
 
 /* System has back-lit keyboard */
 #define CONFIG_PWM_KBLIGHT
 
 /* I2C Bus Configuration */
 
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
 
-#define I2C_PORT_USB_C0_C2_TCPC	NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1_TCPC	NPCX_I2C_PORT4_1
+#define I2C_PORT_USB_C0_C2_TCPC NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1
 
-#define I2C_PORT_USB_C0_C2_PPC	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_PPC	NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C0_C2_PPC NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1
 
-#define I2C_PORT_USB_C0_C2_BC12	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_C1_BC12	NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C0_C2_BC12 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1
 
-#define I2C_PORT_USB_C1_MUX	NPCX_I2C_PORT6_1
+#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1
 
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT5_0
-#define I2C_PORT_CHARGER	NPCX_I2C_PORT7_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-#define I2C_PORT_MP2964		NPCX_I2C_PORT7_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0
 
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 
-#define I2C_ADDR_MP2964_FLAGS	0x20
+#define I2C_ADDR_MP2964_FLAGS 0x20
 
 /* Thermal features */
 #define CONFIG_THERMISTOR
@@ -125,15 +133,15 @@
 #define CONFIG_TEMP_SENSOR_POWER
 #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
 
-#define CONFIG_FANS			FAN_CH_COUNT
+#define CONFIG_FANS FAN_CH_COUNT
 
 /* Charger defines */
 #define CONFIG_CHARGER_ISL9241
 #define CONFIG_CHARGE_RAMP_SW
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 
-#undef  CONFIG_POWER_BUTTON_INIT_TIMEOUT
+#undef CONFIG_POWER_BUTTON_INIT_TIMEOUT
 #define CONFIG_POWER_BUTTON_INIT_TIMEOUT 2
 
 /* Keyboard */
@@ -142,7 +150,7 @@
 
 #ifndef __ASSEMBLER__
 
-#include "gpio_signal.h"	/* needed by registers.h */
+#include "gpio_signal.h" /* needed by registers.h */
 #include "registers.h"
 #include "usbc_config.h"
 
@@ -162,26 +170,21 @@ enum temp_sensor_id {
 
 enum battery_type {
 	BATTERY_COSMX_AP20CBL,
+	BATTERY_COSMX_AP20CBL_004,
 	BATTERY_LGC_AP18C8K,
 	BATTERY_AP19B8M,
 	BATTERY_TYPE_COUNT
 };
 
 enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,		/* PWM3 */
-	PWM_CH_FAN,			/* PWM5 */
+	PWM_CH_KBLIGHT = 0, /* PWM3 */
+	PWM_CH_FAN, /* PWM5 */
 	PWM_CH_COUNT
 };
 
-enum fan_channel {
-	FAN_CH_0 = 0,
-	FAN_CH_COUNT
-};
+enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT };
 
-enum mft_channel {
-	MFT_CH_0 = 0,
-	MFT_CH_COUNT
-};
+enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT };
 
 #ifdef CONFIG_KEYBOARD_FACTORY_TEST
 extern const int keyboard_factory_scan_pins[][2];
diff --git a/board/volmar/build.mk b/board/volmar/build.mk
index 82ffaa9fe2..ed25f9c9aa 100644
--- a/board/volmar/build.mk
+++ b/board/volmar/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/volmar/charger.c b/board/volmar/charger.c
index 85e0de90fe..88f5b85a41 100644
--- a/board/volmar/charger.c
+++ b/board/volmar/charger.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,9 +15,8 @@
 #include "usb_pd.h"
 #include "util.h"
 
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* Charger Chip Configuration */
 const struct charger_config_t chg_chips[] = {
@@ -84,7 +83,6 @@ int board_set_active_charge_port(int port)
 __overridable void board_set_charge_limit(int port, int supplier, int charge_ma,
 					  int max_ma, int charge_mv)
 {
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
diff --git a/board/volmar/ec.tasklist b/board/volmar/ec.tasklist
index b6470bf76b..70b64bc757 100644
--- a/board/volmar/ec.tasklist
+++ b/board/volmar/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/volmar/fans.c b/board/volmar/fans.c
index 4fb92f2cf4..404e6f60df 100644
--- a/board/volmar/fans.c
+++ b/board/volmar/fans.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,7 +25,7 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
 
 static const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
@@ -38,9 +38,9 @@ static const struct fan_conf fan_conf_0 = {
  * boards as well.
  */
 static const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 0,
-	.rpm_start = 5000,
-	.rpm_max = 6500,
+	.rpm_min = 3000,
+	.rpm_start = 3000,
+	.rpm_max = 6000,
 };
 
 const struct fan_t fans[FAN_CH_COUNT] = {
diff --git a/board/volmar/fw_config.c b/board/volmar/fw_config.c
index da56362496..5c62ed17b8 100644
--- a/board/volmar/fw_config.c
+++ b/board/volmar/fw_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,7 +10,7 @@
 #include "cros_board_info.h"
 #include "fw_config.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 static union volmar_cbi_fw_config fw_config;
 BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t));
diff --git a/board/volmar/fw_config.h b/board/volmar/fw_config.h
index ba8c807a66..4dddec9273 100644
--- a/board/volmar/fw_config.h
+++ b/board/volmar/fw_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,12 +27,12 @@ enum ec_cfg_keyboard_backlight_type {
 
 union volmar_cbi_fw_config {
 	struct {
-		enum ec_cfg_usb_db_type			usb_db : 4;
-		enum ec_cfg_keyboard_backlight_type	kb_bl : 1;
-		uint32_t				audio : 3;
-		uint32_t				boot_nvme_mask : 1;
-		uint32_t				boot_emmc_mask : 1;
-		uint32_t				reserved_1 : 22;
+		enum ec_cfg_usb_db_type usb_db : 4;
+		enum ec_cfg_keyboard_backlight_type kb_bl : 1;
+		uint32_t audio : 3;
+		uint32_t boot_nvme_mask : 1;
+		uint32_t boot_emmc_mask : 1;
+		uint32_t reserved_1 : 22;
 	};
 	uint32_t raw_value;
 };
diff --git a/board/volmar/gpio.inc b/board/volmar/gpio.inc
index ac5be5fb17..b1d4e8c3dc 100644
--- a/board/volmar/gpio.inc
+++ b/board/volmar/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2022 The Chromium OS Authors. All rights reserved.
+ * Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,7 +21,6 @@ GPIO_INT(SEQ_EC_RSMRST_ODL,              PIN(E, 2), GPIO_INT_BOTH, power_signal_
 GPIO_INT(SLP_S3_L,                       PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 GPIO_INT(SLP_SUS_L,                      PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
 GPIO_INT(SYS_SLP_S0IX_L,                 PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-GPIO_INT(TABLET_MODE_L,                  PIN(9, 5), GPIO_INT_BOTH, gmr_tablet_switch_isr)
 GPIO_INT(USB_C0_BC12_INT_ODL,            PIN(C, 6), GPIO_INT_FALLING, bc12_interrupt)
 GPIO_INT(USB_C0_C2_TCPC_INT_ODL,         PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event)
 GPIO_INT(USB_C0_PPC_INT_ODL,             PIN(6, 2), GPIO_INT_FALLING, ppc_interrupt)
@@ -124,6 +123,7 @@ UNUSED(PIN(5, 6))       /* GPIO56 */
 UNUSED(PIN(B, 1))       /* GPIOB1 */
 UNUSED(PIN(D, 0))       /* GPIOD0/I2C3_SDA0 */
 UNUSED(PIN(D, 1))       /* GPIOD1/I2C3_SCL0 */
+UNUSED(PIN(9, 5))       /* GPIO95 */
 
 /* Pre-configured PSL balls:  J8  K6 */
 
diff --git a/board/volmar/i2c.c b/board/volmar/i2c.c
index 890a578788..29dd2904c1 100644
--- a/board/volmar/i2c.c
+++ b/board/volmar/i2c.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,7 +8,7 @@
 #include "hooks.h"
 #include "i2c.h"
 
-#define BOARD_ID_FAST_PLUS_CAPABLE	2
+#define BOARD_ID_FAST_PLUS_CAPABLE 2
 
 /* I2C port map configuration */
 const struct i2c_port_t i2c_ports[] = {
diff --git a/board/volmar/keyboard.c b/board/volmar/keyboard.c
index 598e187d00..16857b53c9 100644
--- a/board/volmar/keyboard.c
+++ b/board/volmar/keyboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -40,8 +40,8 @@ static const struct ec_response_keybd_config volmar_kb = {
 	},
 	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
 };
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	return &volmar_kb;
 }
diff --git a/board/volmar/led.c b/board/volmar/led.c
index 7634437b0d..6c8c20299b 100644
--- a/board/volmar/led.c
+++ b/board/volmar/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  * Power and battery LED control for volmar
@@ -21,23 +21,28 @@ __override const int led_charge_lvl_1 = 5;
 __override const int led_charge_lvl_2 = 95;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
diff --git a/board/volmar/pwm.c b/board/volmar/pwm.c
index 47986f1ec8..ad4093ed0e 100644
--- a/board/volmar/pwm.c
+++ b/board/volmar/pwm.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/volmar/sensors.c b/board/volmar/sensors.c
index 720771c360..f03469cef4 100644
--- a/board/volmar/sensors.c
+++ b/board/volmar/sensors.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -70,17 +70,17 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CPU \
-	{ \
+#define THERMAL_CPU              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(85), \
 		}, \
 		.temp_host_release = { \
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
 		}, \
-		.temp_fan_off = C_TO_K(25), \
-		.temp_fan_max = C_TO_K(50), \
+		.temp_fan_off = C_TO_K(30), \
+		.temp_fan_max = C_TO_K(84), \
 	}
 __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 
@@ -100,17 +100,17 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_FAN \
-	{ \
+#define THERMAL_FAN              \
+	{                        \
 		.temp_host = { \
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
-			[EC_TEMP_THRESH_HALT] = C_TO_K(85), \
+			[EC_TEMP_THRESH_HIGH] = 0, \
+			[EC_TEMP_THRESH_HALT] = 0, \
 		}, \
 		.temp_host_release = { \
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+			[EC_TEMP_THRESH_HIGH] = 0, \
 		}, \
-		.temp_fan_off = C_TO_K(25), \
-		.temp_fan_max = C_TO_K(50), \
+		.temp_fan_off = 0, \
+		.temp_fan_max = 0, \
 	}
 __maybe_unused static const struct ec_thermal_config thermal_fan = THERMAL_FAN;
 
@@ -128,25 +128,25 @@ __maybe_unused static const struct ec_thermal_config thermal_fan = THERMAL_FAN;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CHARGER \
-	{ \
+#define THERMAL_CHARGER          \
+	{                        \
 		.temp_host = { \
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
-			[EC_TEMP_THRESH_HALT] = C_TO_K(85), \
+			[EC_TEMP_THRESH_HIGH] = 0, \
+			[EC_TEMP_THRESH_HALT] = 0, \
 		}, \
 		.temp_host_release = { \
-			[EC_TEMP_THRESH_HIGH] = C_TO_K(65), \
+			[EC_TEMP_THRESH_HIGH] = 0, \
 		}, \
-		.temp_fan_off = C_TO_K(25), \
-		.temp_fan_max = C_TO_K(50), \
+		.temp_fan_off = 0, \
+		.temp_fan_max = 0, \
 	}
 __maybe_unused static const struct ec_thermal_config thermal_charger =
-							THERMAL_CHARGER;
+	THERMAL_CHARGER;
 
 /* this should really be "const" */
 struct ec_thermal_config thermal_params[] = {
 	[TEMP_SENSOR_1_DDR_SOC] = THERMAL_CPU,
 	[TEMP_SENSOR_2_FAN] = THERMAL_FAN,
-	[TEMP_SENSOR_3_CHARGER]	= THERMAL_CHARGER,
+	[TEMP_SENSOR_3_CHARGER] = THERMAL_CHARGER,
 };
 BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
diff --git a/board/volmar/usbc_config.c b/board/volmar/usbc_config.c
index 5f70a16c21..6a6c5c709f 100644
--- a/board/volmar/usbc_config.c
+++ b/board/volmar/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -34,8 +34,8 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 /* USBC TCPC configuration */
 const struct tcpc_config_t tcpc_config[] = {
@@ -97,24 +97,31 @@ unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
  * to the virtual_usb_mux_driver so the AP gets notified of mux changes
  * and updates the TCSS configuration on state changes.
  */
-static const struct usb_mux usbc1_usb3_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+static const struct usb_mux_chain usbc1_usb3_db_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
 };
 
-const struct usb_mux usb_muxes[] = {
+const struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 	},
 	[USBC_PORT_C1] = {
-		/* PS8815 DB */
-		.usb_port = USBC_PORT_C1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-		.next_mux = &usbc1_usb3_db_retimer,
+		.mux = &(const struct usb_mux) {
+			/* PS8815 DB */
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+		.next = &usbc1_usb3_db_retimer,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
@@ -156,8 +163,8 @@ int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
 	}
 
 	if (voltage < BC12_MIN_VOLTAGE) {
-		CPRINTS("%s: port %d: vbus %d lower than %d", __func__,
-			port, voltage, BC12_MIN_VOLTAGE);
+		CPRINTS("%s: port %d: vbus %d lower than %d", __func__, port,
+			voltage, BC12_MIN_VOLTAGE);
 		return 1;
 	}
 
@@ -177,7 +184,6 @@ void config_usb_db_type(void)
 	CPRINTS("Configured USB DB type number is %d", db_type);
 }
 
-
 void board_reset_pd_mcu(void)
 {
 	/*
diff --git a/board/volmar/usbc_config.h b/board/volmar/usbc_config.h
index 69300a9354..0722d00d6b 100644
--- a/board/volmar/usbc_config.h
+++ b/board/volmar/usbc_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,13 +8,9 @@
 #ifndef __CROS_EC_USBC_CONFIG_H
 #define __CROS_EC_USBC_CONFIG_H
 
-#define CONFIG_USB_PD_PORT_MAX_COUNT	2
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 void config_usb_db_type(void);
 
diff --git a/board/volteer/battery.c b/board/volteer/battery.c
index 1c24e1ec24..31cb7faaf9 100644
--- a/board/volteer/battery.c
+++ b/board/volteer/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/volteer/board.c b/board/volteer/board.c
index 0e7a1d21e0..ecf3e12e5e 100644
--- a/board/volteer/board.c
+++ b/board/volteer/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -64,7 +64,7 @@ __override struct keyboard_scan_config keyscan_config = {
 
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
@@ -100,8 +100,8 @@ const struct fan_t fans[FAN_CH_COUNT] = {
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CPU \
-	{ \
+#define THERMAL_CPU              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
@@ -128,8 +128,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_INDUCTOR \
-	{ \
+#define THERMAL_INDUCTOR         \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(80), \
diff --git a/board/volteer/board.h b/board/volteer/board.h
index 936bc9ddc5..bf46543e90 100644
--- a/board/volteer/board.h
+++ b/board/volteer/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,7 +23,7 @@
 #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
 
 /* Remove PRL state names to free flash space */
-#define CONFIG_USB_PD_DEBUG_LEVEL 1
+#define CONFIG_USB_PD_DEBUG_LEVEL 0
 
 #define CONFIG_VBOOT_EFS2
 
@@ -54,51 +54,53 @@
 
 /* TCS3400 ALS */
 #define CONFIG_ALS
-#define ALS_COUNT		1
+#define ALS_COUNT 1
 #define CONFIG_ALS_TCS3400
 #define CONFIG_ALS_TCS3400_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS)
 
 /* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
-	(BIT(LID_ACCEL) | BIT(CLEAR_ALS))
+#define CONFIG_ACCEL_FORCE_MODE_MASK (BIT(LID_ACCEL) | BIT(CLEAR_ALS))
 
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE		BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID		LID_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
 
 /* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
 
 /* TODO: b/144165680 - measure and check these values on Volteer */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
 /*
  * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
  * cables only support up to 60W.
  */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 60000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Enabling Thunderbolt-compatible mode */
 #define CONFIG_USB_PD_TBT_COMPAT_MODE
 
 /* Enabling USB4 mode */
 #define CONFIG_USB_PD_USB4
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x40
+#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x40
 
 /* USB Type A Features */
-#define USB_PORT_COUNT			1
+#define USB_PORT_COUNT 1
 #define CONFIG_USB_PORT_POWER_DUMB
 
 /* USBC PPC*/
-#define CONFIG_USBC_PPC_SN5S330		/* USBC port C0 */
-#define CONFIG_USBC_PPC_SYV682X		/* USBC port C1 */
+#define CONFIG_USBC_PPC_SN5S330 /* USBC port C0 */
+#define CONFIG_USBC_PPC_SYV682X /* USBC port C1 */
 #define CONFIG_USB_PD_FRS_PPC
 
+/* Disable PPC logging to reduce EC image size */
+#undef CONFIG_USBC_PPC_LOGGING
+
 /* BC 1.2 */
 
 /* Volume Button feature */
@@ -106,8 +108,8 @@
 /* Fan features */
 
 /* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 
 /*
  * Macros for GPIO signals used in common code that don't match the
@@ -115,42 +117,42 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_DSW_PWROK		GPIO_EC_PCH_DSW_PWROK
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_LID_OPEN GPIO_EC_LID_OPEN
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
 
 /* I2C Bus Configuration */
 #define CONFIG_I2C
-#define I2C_PORT_ACCEL		I2C_PORT_SENSOR
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_1_MIX	NPCX_I2C_PORT3_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT3_0
+#define I2C_PORT_POWER NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+
+#define I2C_PORT_BATTERY I2C_PORT_POWER
+#define I2C_PORT_CHARGER I2C_PORT_EEPROM
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 #define CONFIG_I2C_CONTROLLER
 
 #define CONFIG_DEBUG_ASSERT_BRIEF
@@ -163,7 +165,11 @@
 #undef CONFIG_CMD_CBI
 #undef CONFIG_CMD_CHARGER
 #undef CONFIG_CMD_CHARGE_SUPPLIER_INFO
+#undef CONFIG_CMD_CRASH
+#undef CONFIG_CMD_DEVICE_EVENT
+#undef CONFIG_CMD_FLASH_WP
 #undef CONFIG_CMD_HASH
+#undef CONFIG_CMD_I2C_XFER
 #undef CONFIG_CMD_IDLE_STATS
 #undef CONFIG_CMD_INA
 #undef CONFIG_CMD_MFALLOW
@@ -173,6 +179,7 @@
 #undef CONFIG_CMD_REGULATOR
 #undef CONFIG_CMD_USB_PD_CABLE
 #undef CONFIG_CONSOLE_CMDHELP
+#undef CONFIG_CONSOLE_HISTORY
 
 /* Disable volume button in ectool */
 #undef CONFIG_HOSTCMD_BUTTON
diff --git a/board/volteer/build.mk b/board/volteer/build.mk
index 5adcffff56..fc7828e29b 100644
--- a/board/volteer/build.mk
+++ b/board/volteer/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/volteer/cbi.c b/board/volteer/cbi.c
index b39f0d7d2f..46c7dae7bf 100644
--- a/board/volteer/cbi.c
+++ b/board/volteer/cbi.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/volteer/ec.tasklist b/board/volteer/ec.tasklist
index d94a4445b9..0492fcc3c0 100644
--- a/board/volteer/ec.tasklist
+++ b/board/volteer/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/volteer/gpio.inc b/board/volteer/gpio.inc
index 45aa5b28c4..04982595fe 100644
--- a/board/volteer/gpio.inc
+++ b/board/volteer/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,7 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
diff --git a/board/volteer/led.c b/board/volteer/led.c
index 52a6b9d890..adc8f7b4a6 100644
--- a/board/volteer/led.c
+++ b/board/volteer/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,16 +19,16 @@ const enum ec_led_id supported_led_ids[] = {
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = {
-				/* Red, Green, Blue */
-	[EC_LED_COLOR_RED] =    {  100,   0,     0 },
-	[EC_LED_COLOR_GREEN] =  {    0, 100,     0 },
-	[EC_LED_COLOR_BLUE] =   {    0,   0,   100 },
+	/* Red, Green, Blue */
+	[EC_LED_COLOR_RED] = { 100, 0, 0 },
+	[EC_LED_COLOR_GREEN] = { 0, 100, 0 },
+	[EC_LED_COLOR_BLUE] = { 0, 0, 100 },
 	/* The green LED seems to be brighter than the others, so turn down
 	 * green from its natural level for these secondary colors.
 	 */
-	[EC_LED_COLOR_YELLOW] = {  100,  70,     0 },
-	[EC_LED_COLOR_WHITE] =  {  100,  70,   100 },
-	[EC_LED_COLOR_AMBER] =  {  100,  20,     0 },
+	[EC_LED_COLOR_YELLOW] = { 100, 70, 0 },
+	[EC_LED_COLOR_WHITE] = { 100, 70, 100 },
+	[EC_LED_COLOR_AMBER] = { 100, 20, 0 },
 };
 
 struct pwm_led pwm_leds[] = {
diff --git a/board/volteer/sensors.c b/board/volteer/sensors.c
index c3e42cbf05..b6ed795777 100644
--- a/board/volteer/sensors.c
+++ b/board/volteer/sensors.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -84,17 +84,13 @@ static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = {
 };
 
 /* Rotation matrix for the lid accelerometer */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+				       { FLOAT_TO_FP(-1), 0, 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t motion_sensors[] = {
 	[LID_ACCEL] = {
diff --git a/board/volteer/usbc_config.c b/board/volteer/usbc_config.c
index 748e1e9599..f5e21cb9f4 100644
--- a/board/volteer/usbc_config.c
+++ b/board/volteer/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -41,24 +41,33 @@ static const struct tcpc_config_t tcpc_config_p1_usb3 = {
  * virtual_usb_mux_driver so the AP gets notified of mux changes and updates
  * the TCSS configuration on state changes.
  */
-static const struct usb_mux usbc1_usb3_db_retimer = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &tcpci_tcpm_usb_mux_driver,
-	.hpd_update = &ps8xxx_tcpc_update_hpd_status,
-	.next_mux = NULL,
+static const struct usb_mux_chain usbc1_usb3_db_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		},
+	.next = NULL,
 };
 
-static const struct usb_mux mux_config_p1_usb3_active = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-	.next_mux = &usbc1_usb3_db_retimer,
+static const struct usb_mux_chain mux_config_p1_usb3_active = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
+	.next = &usbc1_usb3_db_retimer,
 };
 
-static const struct usb_mux mux_config_p1_usb3_passive = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+static const struct usb_mux_chain mux_config_p1_usb3_passive = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		}
 };
 
 /*
@@ -208,25 +217,32 @@ const int usb_port_enable[USB_PORT_COUNT] = {
 
 /******************************************************************************/
 /* USBC mux configuration - Tiger Lake includes internal mux */
-struct usb_mux usbc1_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+struct usb_mux_chain usbc1_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		}
 };
 
-struct usb_mux usb_muxes[] = {
+struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 	},
 	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.next_mux = &usbc1_tcss_usb_mux,
-		.i2c_port = I2C_PORT_USB_1_MIX,
-		.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_1_MIX,
+			.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc1_tcss_usb_mux,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
@@ -279,8 +295,8 @@ __override bool board_is_tbt_usb4_port(int port)
 	 * TODO (b/147732807): All the USB-C ports need to support same
 	 * features. Need to fix once USB-C feature set is known for Volteer.
 	 */
-	return ((port == USBC_PORT_C1)
-		&& ((usb_db == DB_USB4_GEN2) || (usb_db == DB_USB4_GEN3)));
+	return ((port == USBC_PORT_C1) &&
+		((usb_db == DB_USB4_GEN2) || (usb_db == DB_USB4_GEN3)));
 }
 
 static void ps8815_reset(void)
@@ -288,8 +304,7 @@ static void ps8815_reset(void)
 	int val;
 
 	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 0);
-	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS,
-			   PS8815_PWR_H_RST_H_DELAY_MS));
+	msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS));
 	gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 1);
 	msleep(PS8815_FW_INIT_DELAY_MS);
 
@@ -300,16 +315,16 @@ static void ps8815_reset(void)
 
 	CPRINTS("%s: patching ps8815 registers", __func__);
 
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
+	if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) ==
+	    EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f was %02x", val);
 
-	if (i2c_write8(I2C_PORT_USB_C1,
-		       PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) == EC_SUCCESS)
+	if (i2c_write8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f,
+		       0x31) == EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f set to 0x31");
 
-	if (i2c_read8(I2C_PORT_USB_C1,
-		      PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS)
+	if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) ==
+	    EC_SUCCESS)
 		CPRINTS("ps8815: reg 0x0f now %02x", val);
 }
 
@@ -321,8 +336,9 @@ void board_reset_pd_mcu(void)
 	/* Daughterboard specific reset for port 1 */
 	if (usb_db == DB_USB3_ACTIVE) {
 		ps8815_reset();
-		usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED |
-						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+		usb_mux_hpd_update(USBC_PORT_C1,
+				   USB_PD_MUX_HPD_LVL_DEASSERTED |
+					   USB_PD_MUX_HPD_IRQ_DEASSERTED);
 	}
 }
 
diff --git a/board/volteer/usbc_config.h b/board/volteer/usbc_config.h
index 55dfce7621..7428d0c436 100644
--- a/board/volteer/usbc_config.h
+++ b/board/volteer/usbc_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,11 +8,7 @@
 #ifndef __CROS_EC_USBC_CONFIG_H
 #define __CROS_EC_USBC_CONFIG_H
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 /* Configure the USB3 daughterboard type */
 void config_usb3_db_type(void);
diff --git a/board/volteer_ish/board.c b/board/volteer_ish/board.c
index 76c127056b..1f209dfb4d 100644
--- a/board/volteer_ish/board.c
+++ b/board/volteer_ish/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,11 +20,7 @@
 
 /* I2C port map */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 1000
-	},
+	{ .name = "sensor", .port = I2C_PORT_SENSOR, .kbps = 1000 },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
diff --git a/board/volteer_ish/board.h b/board/volteer_ish/board.h
index 2e2b7e7276..6f7d3bd1b7 100644
--- a/board/volteer_ish/board.h
+++ b/board/volteer_ish/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,7 +22,7 @@
 #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
 
 /* ISH specific */
-#undef  CONFIG_DEBUG_ASSERT
+#undef CONFIG_DEBUG_ASSERT
 #define CONFIG_CLOCK_CRYSTAL
 #define CONFIG_ISH_UART_0
 /* EC */
@@ -40,7 +40,6 @@
 #define CONFIG_MKBP_EVENT
 #define CONFIG_MKBP_USE_HECI
 
-
 /* Enable sensor fifo, must also define the _SIZE and _THRES */
 #define CONFIG_ACCEL_FIFO
 /* FIFO size is in power of 2. */
@@ -87,10 +86,7 @@
 #include "registers.h"
 
 /* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, SENSOR_COUNT };
 
 #endif /* !__ASSEMBLER__ */
 
diff --git a/board/volteer_ish/build.mk b/board/volteer_ish/build.mk
index 74ec3c865f..4a84a1f475 100644
--- a/board/volteer_ish/build.mk
+++ b/board/volteer_ish/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/volteer_ish/ec.tasklist b/board/volteer_ish/ec.tasklist
index a4db486e9a..de7d256324 100644
--- a/board/volteer_ish/ec.tasklist
+++ b/board/volteer_ish/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/volteer_ish/gpio.inc b/board/volteer_ish/gpio.inc
index 286309e388..8b25af63cb 100644
--- a/board/volteer_ish/gpio.inc
+++ b/board/volteer_ish/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/voxel/battery.c b/board/voxel/battery.c
index 4f51b79ad9..887ba27344 100644
--- a/board/voxel/battery.c
+++ b/board/voxel/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/voxel/board.c b/board/voxel/board.c
index c57d03b9d3..40dfbe8dc4 100644
--- a/board/voxel/board.c
+++ b/board/voxel/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -44,7 +44,7 @@
 
 #include "gpio_list.h" /* Must come after other header files. */
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 static const struct ec_response_keybd_config zbu_new_kb = {
 	.num_top_row_keys = 10,
@@ -80,8 +80,8 @@ static const struct ec_response_keybd_config zbu_old_kb = {
 	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
 };
 
-__override
-const struct ec_response_keybd_config *board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	if (get_board_id() > 2)
 		return &zbu_new_kb;
@@ -111,16 +111,15 @@ __override struct keyboard_scan_config keyscan_config = {
  * that we don't have pin 0.
  */
 const int keyboard_factory_scan_pins[][2] = {
-	{-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6},
-	{0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3},
-	{-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0},
-	{1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4},
-	{2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0},
-	{-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1},
-	{-1, -1},
+	{ -1, -1 }, { 0, 5 },	{ 1, 1 }, { 1, 0 },   { 0, 6 },	  { 0, 7 },
+	{ -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 },   { -1, -1 }, { 1, 6 },
+	{ 1, 7 },   { 3, 1 },	{ 2, 0 }, { 1, 5 },   { 2, 6 },	  { 2, 7 },
+	{ 2, 1 },   { 2, 4 },	{ 2, 5 }, { 1, 2 },   { 2, 3 },	  { 2, 2 },
+	{ 3, 0 },   { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 },	  { -1, -1 },
+	{ -1, -1 },
 };
 const int keyboard_factory_scan_pins_used =
-		ARRAY_SIZE(keyboard_factory_scan_pins);
+	ARRAY_SIZE(keyboard_factory_scan_pins);
 
 __override uint32_t board_override_feature_flags0(uint32_t flags0)
 {
@@ -146,7 +145,7 @@ union volteer_cbi_fw_config fw_config_defaults = {
 
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = GPIO_EN_PP5000_FAN,
 };
@@ -183,8 +182,8 @@ const struct fan_t fans[FAN_CH_COUNT] = {
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CPU \
-	{ \
+#define THERMAL_CPU              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(75), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(85), \
@@ -314,12 +313,12 @@ static void setup_board_tcpc(void)
 
 	if (board_id == 0) {
 		/* config typec C0 prot TUSB422 TCPC */
-		tcpc_config[USBC_PORT_C0].i2c_info.addr_flags
-			= TUSB422_I2C_ADDR_FLAGS;
+		tcpc_config[USBC_PORT_C0].i2c_info.addr_flags =
+			TUSB422_I2C_ADDR_FLAGS;
 		tcpc_config[USBC_PORT_C0].drv = &tusb422_tcpm_drv;
 		/* config typec C1 prot TUSB422 TCPC */
-		tcpc_config[USBC_PORT_C1].i2c_info.addr_flags
-			= TUSB422_I2C_ADDR_FLAGS;
+		tcpc_config[USBC_PORT_C1].i2c_info.addr_flags =
+			TUSB422_I2C_ADDR_FLAGS;
 		tcpc_config[USBC_PORT_C1].drv = &tusb422_tcpm_drv;
 	}
 }
@@ -429,33 +428,43 @@ BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
 
 /******************************************************************************/
 /* USBC mux configuration - Tiger Lake includes internal mux */
-struct usb_mux usbc0_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+struct usb_mux_chain usbc0_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
-struct usb_mux usbc1_tcss_usb_mux = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+struct usb_mux_chain usbc1_tcss_usb_mux = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
 
-struct usb_mux usb_muxes[] = {
+struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.next_mux = &usbc0_tcss_usb_mux,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_0_MIX,
-		.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_0_MIX,
+			.i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc0_tcss_usb_mux,
 	},
 	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.next_mux = &usbc1_tcss_usb_mux,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.i2c_port = I2C_PORT_USB_1_MIX,
-		.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C1,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_1_MIX,
+			.i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR,
+		},
+		.next = &usbc1_tcss_usb_mux,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
diff --git a/board/voxel/board.h b/board/voxel/board.h
index 7d7109330c..1b866a5749 100644
--- a/board/voxel/board.h
+++ b/board/voxel/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,7 +13,7 @@
 
 /* Optional features */
 #undef NPCX7_PWM1_SEL
-#define NPCX7_PWM1_SEL    0    /* GPIO C2 is not used as PWM1. */
+#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */
 
 /*
  * The RAM and flash size combination on the the NPCX797FC does not leave
@@ -47,8 +47,8 @@
 #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
 /* BMI160 Base accel/gyro */
 #define CONFIG_ACCELGYRO_BMI160
-#define CONFIG_ACCELGYRO_ICM426XX	/* Base accel second source*/
-#define CONFIG_ACCELGYRO_ICM42607	/* Base accel second source*/
+#define CONFIG_ACCELGYRO_ICM426XX /* Base accel second source*/
+#define CONFIG_ACCELGYRO_ICM42607 /* Base accel second source*/
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 #define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \
@@ -60,27 +60,27 @@
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
 
 /* BMA253 Lid accel */
-#define CONFIG_ACCEL_KX022	/* Lid accel */
+#define CONFIG_ACCEL_KX022 /* Lid accel */
 #define CONFIG_ACCEL_BMA255
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE	BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID	LID_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
 
 /* USB Type C and USB PD defines */
-#define CONFIG_USB_PD_PORT_MAX_COUNT			2
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
 
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
 
 /*
  * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
  * cables only support up to 60W.
  */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		45000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 45000
+#define PD_MAX_CURRENT_MA 3000
+#define PD_MAX_VOLTAGE_MV 20000
 
 #define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY
 #ifdef BOARD_VOXEL_ECMODEENTRY
@@ -92,16 +92,16 @@
 
 /* Enabling USB4 mode */
 #define CONFIG_USB_PD_USB4
-#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR	0x40
-#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR	0x41
+#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x40
+#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x41
 #define CONFIG_USB_PD_DATA_RESET_MSG
 
 /* USB Type A Features */
-#define USB_PORT_COUNT			1
+#define USB_PORT_COUNT 1
 #define CONFIG_USB_PORT_POWER_DUMB
 
 /* USBC PPC*/
-#define CONFIG_USBC_PPC_SYV682X		/* USBC port C0/C1 */
+#define CONFIG_USBC_PPC_SYV682X /* USBC port C0/C1 */
 #define CONFIG_USB_PD_FRS_PPC
 
 /* BC 1.2 */
@@ -114,8 +114,8 @@
 /* Fan features */
 
 /* charger defines */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 
 /*
  * Macros for GPIO signals used in common code that don't match the
@@ -123,46 +123,45 @@
  * then redefined here to so it's more clear which signal is being used for
  * which purpose.
  */
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_EC_INT_L			GPIO_EC_PCH_INT_ODL
-#define GPIO_EN_PP5000			GPIO_EN_PP5000_A
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_LID_OPEN			GPIO_EC_LID_OPEN
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
-#define GPIO_PCH_WAKE_L			GPIO_EC_PCH_WAKE_ODL
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_PCH_PWR_BTN_ODL
-#define GPIO_PCH_RSMRST_L		GPIO_EC_PCH_RSMRST_ODL
-#define GPIO_PCH_RTCRST			GPIO_EC_PCH_RTCRST
-#define GPIO_PCH_SLP_S0_L		GPIO_SLP_S0_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_DSW_PWROK		GPIO_EC_PCH_DSW_PWROK
-#define GPIO_POWER_BUTTON_L		GPIO_H1_EC_PWR_BTN_ODL
-#define GPIO_CPU_PROCHOT		GPIO_EC_PROCHOT_ODL
-#define GPIO_SYS_RESET_L		GPIO_SYS_RST_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_USB_C1_BC12_INT_ODL	GPIO_USB_C1_MIX_INT_ODL
-#define GPIO_VOLUME_UP_L		GPIO_EC_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_EC_VOLDN_BTN_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL
+#define GPIO_EN_PP5000 GPIO_EN_PP5000_A
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_LID_OPEN GPIO_EC_LID_OPEN
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
+#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL
+#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL
+#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK
+#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL
+#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL
+#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL
 
 /* I2C Bus Configuration */
 #define CONFIG_I2C
-#define I2C_PORT_ACCEL		I2C_PORT_SENSOR
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0		NPCX_I2C_PORT1_0
-#define I2C_PORT_USB_C1		NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_0_MIX	NPCX_I2C_PORT3_0
-#define I2C_PORT_USB_1_MIX	NPCX_I2C_PORT4_1
-#define I2C_PORT_POWER		NPCX_I2C_PORT5_0
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
-
-#define I2C_PORT_BATTERY	I2C_PORT_POWER
-#define I2C_PORT_CHARGER	I2C_PORT_EEPROM
-
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
+#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_0_MIX NPCX_I2C_PORT3_0
+#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT4_1
+#define I2C_PORT_POWER NPCX_I2C_PORT5_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+
+#define I2C_PORT_BATTERY I2C_PORT_POWER
+#define I2C_PORT_CHARGER I2C_PORT_EEPROM
+
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 #define CONFIG_I2C_CONTROLLER
 
-
 #ifndef __ASSEMBLER__
 
 #include "gpio_signal.h"
@@ -175,11 +174,7 @@ enum battery_type {
 	BATTERY_TYPE_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_FAN,
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_FAN, PWM_CH_KBLIGHT, PWM_CH_COUNT };
 
 enum sensor_id {
 	LID_ACCEL = 0,
@@ -188,11 +183,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 void board_reset_pd_mcu(void);
 
diff --git a/board/voxel/build.mk b/board/voxel/build.mk
index 838d6a16ce..c994631759 100644
--- a/board/voxel/build.mk
+++ b/board/voxel/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/voxel/ec.tasklist b/board/voxel/ec.tasklist
index 174a47eea3..ebcf47c499 100644
--- a/board/voxel/ec.tasklist
+++ b/board/voxel/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/voxel/gpio.inc b/board/voxel/gpio.inc
index 3b0c04d21d..171288a639 100644
--- a/board/voxel/gpio.inc
+++ b/board/voxel/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,7 @@ GPIO_INT(ACOK_OD,              PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, ex
 
 /* Power sequencing interrupts */
 GPIO_INT(SLP_S0_L,             PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt)
-#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifndef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 GPIO_INT(SLP_S3_L,             PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt)
 #endif
 GPIO_INT(SLP_SUS_L,            PIN(D, 7), GPIO_INT_BOTH, power_signal_interrupt)
diff --git a/board/voxel/led.c b/board/voxel/led.c
index 4be69689f7..5b15c9620f 100644
--- a/board/voxel/led.c
+++ b/board/voxel/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,23 +19,28 @@ __override const int led_charge_lvl_1 = 5;
 __override const int led_charge_lvl_2 = 95;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
diff --git a/board/voxel/sensors.c b/board/voxel/sensors.c
index ac444ad840..c3c074da9d 100644
--- a/board/voxel/sensors.c
+++ b/board/voxel/sensors.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,7 +25,7 @@
 #include "tablet_mode.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ##args)
 /******************************************************************************/
 /* Sensors */
 static struct mutex g_lid_accel_mutex;
@@ -40,23 +40,17 @@ static struct bmi_drv_data_t g_bmi160_data;
 static struct icm_drv_data_t g_icm426xx_data;
 
 /* Rotation matrix for the lid accelerometer */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
 
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+				       { FLOAT_TO_FP(-1), 0, 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
 
-static const mat33_fp_t base_icm_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t base_icm_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					 { 0, FLOAT_TO_FP(1), 0 },
+					 { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t kx022_lid_accel = {
 	.name = "Lid Accel",
@@ -283,8 +277,7 @@ static void board_sensors_init(void)
 		motion_sensor_count = 0;
 		gmr_tablet_switch_disable();
 		/* Base accel is not stuffed, don't allow line to float */
-		gpio_set_flags(GPIO_EC_IMU_INT_L,
-			       GPIO_INPUT | GPIO_PULL_DOWN);
+		gpio_set_flags(GPIO_EC_IMU_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
 	}
 }
 DECLARE_HOOK(HOOK_INIT, board_sensors_init, HOOK_PRIO_DEFAULT);
diff --git a/board/waddledee/battery.c b/board/waddledee/battery.c
index 8f1ccc1ade..37b2dd2e3d 100644
--- a/board/waddledee/battery.c
+++ b/board/waddledee/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/waddledee/board.c b/board/waddledee/board.c
index 90d1f7f2bd..d7abda740c 100644
--- a/board/waddledee/board.c
+++ b/board/waddledee/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -40,7 +40,7 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
 
 #define INT_RECHECK_US 5000
 
@@ -127,34 +127,26 @@ static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH0
-	},
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH2
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH3
-	},
-	[ADC_SUB_ANALOG] = {
-		.name = "SUB_ANALOG",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH13
-	},
+	[ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH0 },
+	[ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH2 },
+	[ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH3 },
+	[ADC_SUB_ANALOG] = { .name = "SUB_ANALOG",
+			     .factor_mul = ADC_MAX_MVOLT,
+			     .factor_div = ADC_READ_MAX + 1,
+			     .shift = 0,
+			     .channel = CHIP_ADC_CH13 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
@@ -204,27 +196,36 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 };
 
 /* USB Retimer */
-const struct usb_mux usbc1_retimer = {
-	.usb_port = 1,
-	.i2c_port = I2C_PORT_SUB_USB_C1,
-	.i2c_addr_flags = TUSB544_I2C_ADDR_FLAGS0,
-	.driver = &tusb544_drv,
+const struct usb_mux_chain usbc1_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = 1,
+			.i2c_port = I2C_PORT_SUB_USB_C1,
+			.i2c_addr_flags = TUSB544_I2C_ADDR_FLAGS0,
+			.driver = &tusb544_drv,
+		},
 };
 
 /* USB Muxes */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+			},
 	},
 	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = AN7447_TCPC0_I2C_ADDR_FLAGS,
-		.driver = &anx7447_usb_mux_driver,
-		.next_mux = &usbc1_retimer,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_SUB_USB_C1,
+				.i2c_addr_flags = AN7447_TCPC0_I2C_ADDR_FLAGS,
+				.driver = &anx7447_usb_mux_driver,
+			},
+		.next = &usbc1_retimer,
 	},
 };
 
@@ -239,7 +240,6 @@ void board_init(void)
 		c1_int_line = GPIO_USB_C1_INT_V1_ODL;
 	}
 
-
 	gpio_enable_interrupt(GPIO_USB_C0_INT_ODL);
 	gpio_enable_interrupt(c1_int_line);
 
@@ -403,9 +403,8 @@ void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
 		gpio_set_level(GPIO_EN_USB_C0_CC2_VCONN, !!enabled);
 }
 
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
+__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+				       int *ki_div, int *kd, int *kd_div)
 {
 	*kp = 3;
 	*kp_div = 14;
@@ -463,7 +462,7 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Sensor Data */
-static struct kionix_accel_data  g_kx022_data;
+static struct kionix_accel_data g_kx022_data;
 static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA;
 
 /* Drivers */
@@ -543,14 +542,14 @@ const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
 /* Thermistors */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
diff --git a/board/waddledee/board.h b/board/waddledee/board.h
index 9cdfcc1e06..1ac3fc76da 100644
--- a/board/waddledee/board.h
+++ b/board/waddledee/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,13 +24,16 @@
 #define CONFIG_BC12_DETECT_PI3USB9201
 
 /* Charger */
-#define CONFIG_CHARGER_SM5803		/* C0 and C1: Charger */
+#define CONFIG_CHARGER_SM5803 /* C0 and C1: Charger */
+#define PD_MAX_VOLTAGE_MV 15000
 #define CONFIG_USB_PD_VBUS_DETECT_CHARGER
 #define CONFIG_USB_PD_5V_CHARGER_CTRL
 #define CONFIG_CHARGER_OTG
-#undef  CONFIG_CHARGER_SINGLE_CHIP
+#undef CONFIG_CHARGER_SINGLE_CHIP
 #define CONFIG_OCPC
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr */
+#define CONFIG_OCPC_DEF_RBATT_MOHMS               \
+	21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr \
+	    */
 
 /*
  * GPIO for C1 interrupts, for baseboard use
@@ -47,8 +50,8 @@
 #define CONFIG_PWM
 
 /* Sensors */
-#define CONFIG_ACCEL_KX022		/* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM	/* Base accel */
+#define CONFIG_ACCEL_KX022 /* Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
 #define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 /* Sensors without hardware FIFO are in forced mode */
@@ -71,8 +74,8 @@
 
 /* TCPC */
 #define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP	/* C0: ITE EC TCPC */
-#define CONFIG_USB_PD_TCPM_ANX7447	/* C1: ANX TCPC + Mux */
+#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0: ITE EC TCPC */
+#define CONFIG_USB_PD_TCPM_ANX7447 /* C1: ANX TCPC + Mux */
 #define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1
 
 /* Thermistors */
@@ -81,10 +84,10 @@
 #define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
 
 /* USB Mux and Retimer */
-#define CONFIG_USB_MUX_IT5205			/* C1: ITE Mux */
-#define I2C_PORT_USB_MUX I2C_PORT_USB_C0	/* Required for ITE Mux */
+#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */
 
-#define CONFIG_USBC_RETIMER_TUSB544		/* C1 Redriver: TUSB544 */
+#define CONFIG_USBC_RETIMER_TUSB544 /* C1 Redriver: TUSB544 */
 
 #ifndef __ASSEMBLER__
 
@@ -106,27 +109,18 @@ enum pwm_channel {
 };
 
 /* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
 /* ADC channels */
 enum adc_channel {
-	ADC_VSNS_PP3300_A,     /* ADC0 */
-	ADC_TEMP_SENSOR_1,     /* ADC2 */
-	ADC_TEMP_SENSOR_2,     /* ADC3 */
-	ADC_SUB_ANALOG,        /* ADC13 */
+	ADC_VSNS_PP3300_A, /* ADC0 */
+	ADC_TEMP_SENSOR_1, /* ADC2 */
+	ADC_TEMP_SENSOR_2, /* ADC3 */
+	ADC_SUB_ANALOG, /* ADC13 */
 	ADC_CH_COUNT
 };
 
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_COUNT
-};
+enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
diff --git a/board/waddledee/build.mk b/board/waddledee/build.mk
index 806168ea0d..9b862c7624 100644
--- a/board/waddledee/build.mk
+++ b/board/waddledee/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/waddledee/cbi_ssfc.c b/board/waddledee/cbi_ssfc.c
index c4b859f133..81f3ee0dad 100644
--- a/board/waddledee/cbi_ssfc.c
+++ b/board/waddledee/cbi_ssfc.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
 
 enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
 {
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
 }
 
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
 {
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
 }
diff --git a/board/waddledee/cbi_ssfc.h b/board/waddledee/cbi_ssfc.h
index 935049b6ae..bf8853a43a 100644
--- a/board/waddledee/cbi_ssfc.h
+++ b/board/waddledee/cbi_ssfc.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -56,5 +56,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
  */
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
 
-
 #endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/waddledee/ec.tasklist b/board/waddledee/ec.tasklist
index 2edf48ee05..c3c360febb 100644
--- a/board/waddledee/ec.tasklist
+++ b/board/waddledee/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/waddledee/gpio.inc b/board/waddledee/gpio.inc
index 63e0055199..b0c8d8cd03 100644
--- a/board/waddledee/gpio.inc
+++ b/board/waddledee/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/waddledee/led.c b/board/waddledee/led.c
index 058d23d761..1a2bc16898 100644
--- a/board/waddledee/led.c
+++ b/board/waddledee/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,13 +20,13 @@ const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
  * Board has one physical LED with red, green, and blue
  */
 struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = {
-				/* Red, Green, Blue */
-	[EC_LED_COLOR_RED]    = { 100,   0,   0 },
-	[EC_LED_COLOR_GREEN]  = {   0, 100,   0 },
-	[EC_LED_COLOR_BLUE]   = {   0,   0, 100 },
-	[EC_LED_COLOR_YELLOW] = {  50,  50,   0 },
-	[EC_LED_COLOR_WHITE]  = {  50,  50,  50 },
-	[EC_LED_COLOR_AMBER]  = {  70,  30,   0 },
+	/* Red, Green, Blue */
+	[EC_LED_COLOR_RED] = { 100, 0, 0 },
+	[EC_LED_COLOR_GREEN] = { 0, 100, 0 },
+	[EC_LED_COLOR_BLUE] = { 0, 0, 100 },
+	[EC_LED_COLOR_YELLOW] = { 50, 50, 0 },
+	[EC_LED_COLOR_WHITE] = { 50, 50, 50 },
+	[EC_LED_COLOR_AMBER] = { 70, 30, 0 },
 };
 
 /* One logical LED with red, green, and blue channels. */
diff --git a/board/waddledee/usb_pd_policy.c b/board/waddledee/usb_pd_policy.c
index 7046e25d6c..2433b25431 100644
--- a/board/waddledee/usb_pd_policy.c
+++ b/board/waddledee/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,8 +13,8 @@
 #include "driver/tcpm/tcpci.h"
 #include "usb_pd.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
@@ -65,18 +65,7 @@ int pd_set_power_supply_ready(int port)
 
 __override bool pd_check_vbus_level(int port, enum vbus_level level)
 {
-	int vbus_voltage;
-
-	/* If we're unable to speak to the charger, best to guess false */
-	if (charger_get_vbus_voltage(port, &vbus_voltage))
-		return false;
-
-	if (level == VBUS_SAFE0V)
-		return vbus_voltage < PD_V_SAFE0V_MAX;
-	else if (level == VBUS_PRESENT)
-		return vbus_voltage > PD_V_SAFE5V_MIN;
-	else
-		return vbus_voltage < PD_V_SINK_DISCONNECT_MAX;
+	return sm5803_check_vbus_level(port, level);
 }
 
 int pd_snk_is_vbus_provided(int port)
diff --git a/board/waddledoo/battery.c b/board/waddledoo/battery.c
index 64af3b4302..29eac40158 100644
--- a/board/waddledoo/battery.c
+++ b/board/waddledoo/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/waddledoo/board.c b/board/waddledoo/board.c
index 3dcfc29bdc..e207e59456 100644
--- a/board/waddledoo/board.c
+++ b/board/waddledoo/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -42,8 +42,8 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 #define INT_RECHECK_US 5000
 
@@ -83,7 +83,6 @@ static void usb_c0_interrupt(enum gpio_signal s)
 
 	/* Check the line again in 5ms */
 	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-
 }
 
 /* C1 interrupt line shared by BC 1.2, TCPC, and charger */
@@ -118,7 +117,6 @@ static void sub_usb_c1_interrupt(enum gpio_signal s)
 
 	/* Check the line again in 5ms */
 	hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
-
 }
 
 static void sub_hdmi_hpd_interrupt(enum gpio_signal s)
@@ -173,16 +171,17 @@ void board_init(void)
 
 	if (get_cbi_fw_config_db() == DB_1A_HDMI) {
 		/* Disable i2c on HDMI pins */
-		gpio_config_pin(MODULE_I2C,
-				GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL, 0);
-		gpio_config_pin(MODULE_I2C,
-				GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL, 0);
+		gpio_config_pin(MODULE_I2C, GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL,
+				0);
+		gpio_config_pin(MODULE_I2C, GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL,
+				0);
 
 		/* Set HDMI and sub-rail enables to output */
 		gpio_set_flags(GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL,
 			       chipset_in_state(CHIPSET_STATE_ON) ?
-						GPIO_ODR_LOW : GPIO_ODR_HIGH);
-		gpio_set_flags(GPIO_SUB_C1_INT_EN_RAILS_ODL,   GPIO_ODR_HIGH);
+				       GPIO_ODR_LOW :
+				       GPIO_ODR_HIGH);
+		gpio_set_flags(GPIO_SUB_C1_INT_EN_RAILS_ODL, GPIO_ODR_HIGH);
 
 		/* Select HDMI option */
 		gpio_set_level(GPIO_HDMI_SEL_L, 0);
@@ -191,8 +190,7 @@ void board_init(void)
 		gpio_enable_interrupt(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL);
 	} else {
 		/* Set SDA as an input */
-		gpio_set_flags(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL,
-			       GPIO_INPUT);
+		gpio_set_flags(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL, GPIO_INPUT);
 
 		/* Enable C1 interrupt and check if it needs processing */
 		gpio_enable_interrupt(GPIO_SUB_C1_INT_EN_RAILS_ODL);
@@ -256,7 +254,7 @@ static void reconfigure_5v_gpio(void)
 		gpio_set_flags(GPIO_VOLUP_BTN_ODL, GPIO_OUT_LOW);
 	}
 }
-DECLARE_HOOK(HOOK_INIT, reconfigure_5v_gpio, HOOK_PRIO_INIT_I2C+1);
+DECLARE_HOOK(HOOK_INIT, reconfigure_5v_gpio, HOOK_PRIO_INIT_I2C + 1);
 #endif /* BOARD_WADDLEDOO */
 
 static void set_5v_gpio(int level)
@@ -297,10 +295,9 @@ __override void board_power_5v_enable(int enable)
 		gpio_set_level(GPIO_SUB_C1_INT_EN_RAILS_ODL, !enable);
 	} else {
 		if (isl923x_set_comparator_inversion(1, !!enable))
-			CPRINTS("Failed to %sable sub rails!", enable ?
-								"en" : "dis");
+			CPRINTS("Failed to %sable sub rails!",
+				enable ? "en" : "dis");
 	}
-
 }
 
 __override uint8_t board_get_usb_pd_port_count(void)
@@ -325,13 +322,11 @@ int board_is_sourcing_vbus(int port)
 
 	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
 	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
-
 }
 
 int board_set_active_charge_port(int port)
 {
-	int is_real_port = (port >= 0 &&
-			    port < board_get_usb_pd_port_count());
+	int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count());
 	int i;
 	int old_port;
 
@@ -395,8 +390,8 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
 
@@ -421,17 +416,13 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrices to rotate accelerometers into the standard reference. */
-static const mat33_fp_t lid_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					     { FLOAT_TO_FP(-1), 0, 0 },
+					     { 0, 0, FLOAT_TO_FP(1) } };
 
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					      { FLOAT_TO_FP(-1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
 
 static struct accelgyro_saved_data_t g_bma253_data;
 static struct bmi_drv_data_t g_bmi160_data;
@@ -507,9 +498,8 @@ struct motion_sensor_t motion_sensors[] = {
 
 const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
+__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+				       int *ki_div, int *kd, int *kd_div)
 {
 	*kp = 1;
 	*kp_div = 20;
@@ -596,25 +586,34 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usbc1_retimer = {
-	.usb_port = 1,
-	.i2c_port = I2C_PORT_SUB_USB_C1,
-	.i2c_addr_flags = NB7V904M_I2C_ADDR0,
-	.driver = &nb7v904m_usb_redriver_drv,
+const struct usb_mux_chain usbc1_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = 1,
+			.i2c_port = I2C_PORT_SUB_USB_C1,
+			.i2c_addr_flags = NB7V904M_I2C_ADDR0,
+			.driver = &nb7v904m_usb_redriver_drv,
+		},
 };
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
-		.driver = &pi3usb3x532_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
+				.driver = &pi3usb3x532_usb_mux_driver,
+			},
 	},
 	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
-		.driver = &pi3usb3x532_usb_mux_driver,
-		.next_mux = &usbc1_retimer,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_SUB_USB_C1,
+				.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
+				.driver = &pi3usb3x532_usb_mux_driver,
+			},
+		.next = &usbc1_retimer,
 	}
 };
 
@@ -640,7 +639,7 @@ uint16_t tcpc_get_alert_status(void)
 	}
 
 	if (board_get_usb_pd_port_count() > 1 &&
-				!gpio_get_level(GPIO_SUB_C1_INT_EN_RAILS_ODL)) {
+	    !gpio_get_level(GPIO_SUB_C1_INT_EN_RAILS_ODL)) {
 		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
 			/* TCPCI spec Rev 1.0 says to ignore bits 14:12. */
 			if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0))
diff --git a/board/waddledoo/board.h b/board/waddledoo/board.h
index 37004c2efe..727f1bdb33 100644
--- a/board/waddledoo/board.h
+++ b/board/waddledoo/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,7 +19,7 @@
 
 /* Save some flash space */
 #define CONFIG_CHIP_INIT_ROM_REGION
-#undef  CONFIG_CONSOLE_CMDHELP
+#undef CONFIG_CONSOLE_CMDHELP
 #define CONFIG_DEBUG_ASSERT_BRIEF
 #define CONFIG_USB_PD_DEBUG_LEVEL 2
 
@@ -35,11 +35,14 @@
 
 /* Charger */
 #define CONFIG_CHARGER_RAA489000
+#define PD_MAX_VOLTAGE_MV 20000
 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 #define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */
+#define CONFIG_OCPC_DEF_RBATT_MOHMS               \
+	22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \
+	    */
 #define CONFIG_OCPC
-#undef  CONFIG_CHARGER_SINGLE_CHIP
+#undef CONFIG_CHARGER_SINGLE_CHIP
 #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
 #define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
 
@@ -68,7 +71,7 @@
 
 /* PWM */
 #define CONFIG_PWM
-#define NPCX7_PWM1_SEL    1  /* GPIO C2 is used as PWM1. */
+#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */
 
 /* USB */
 #define CONFIG_BC12_DETECT_PI3USB9201
@@ -91,23 +94,22 @@
 #undef PD_POWER_SUPPLY_TURN_OFF_DELAY
 #undef CONFIG_USBC_VCONN_SWAP_DELAY_US
 /* 20% margin added for these timings */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	13080	/* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	16080	/* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 13080 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 16080 /* us */
 #undef CONFIG_USBC_VCONN_SWAP_DELAY_US
-#define CONFIG_USBC_VCONN_SWAP_DELAY_US		787	/* us */
-
+#define CONFIG_USBC_VCONN_SWAP_DELAY_US 787 /* us */
 
 /* I2C configuration */
-#define I2C_PORT_EEPROM     NPCX_I2C_PORT7_0
-#define I2C_PORT_BATTERY    NPCX_I2C_PORT5_0
-#define I2C_PORT_SENSOR     NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0     NPCX_I2C_PORT1_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
 #define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_MUX    I2C_PORT_USB_C0
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0
 /* TODO(b:147440290): Need to handle multiple charger ICs */
-#define I2C_PORT_CHARGER    I2C_PORT_USB_C0
+#define I2C_PORT_CHARGER I2C_PORT_USB_C0
 
-#define I2C_PORT_ACCEL      I2C_PORT_SENSOR
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
 
 #define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */
 
@@ -124,13 +126,13 @@
 #define CONFIG_CMD_ACCELS
 #define CONFIG_CMD_ACCEL_INFO
 
-#define CONFIG_ACCEL_BMA255		/* Lid accel */
-#define CONFIG_ACCELGYRO_BMI160		/* Base accel */
+#define CONFIG_ACCEL_BMA255 /* Lid accel */
+#define CONFIG_ACCELGYRO_BMI160 /* Base accel */
 
 /* Lid operates in forced mode, base in FIFO */
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
 #define CONFIG_ACCEL_FIFO
-#define CONFIG_ACCEL_FIFO_SIZE 256	/* Must be a power of 2 */
+#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */
 #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
 
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
@@ -157,19 +159,14 @@ enum chg_id {
 };
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_1,     /* ADC0 */
-	ADC_TEMP_SENSOR_2,     /* ADC1 */
-	ADC_SUB_ANALOG,	       /* ADC2 */
-	ADC_VSNS_PP3300_A,     /* ADC9 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
+	ADC_SUB_ANALOG, /* ADC2 */
+	ADC_VSNS_PP3300_A, /* ADC9 */
 	ADC_CH_COUNT
 };
 
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
 enum pwm_channel {
 	PWM_CH_KBLIGHT,
diff --git a/board/waddledoo/build.mk b/board/waddledoo/build.mk
index d467fee6e6..6f205ebcf4 100644
--- a/board/waddledoo/build.mk
+++ b/board/waddledoo/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/waddledoo/cbi_ssfc.c b/board/waddledoo/cbi_ssfc.c
index c4b859f133..81f3ee0dad 100644
--- a/board/waddledoo/cbi_ssfc.c
+++ b/board/waddledoo/cbi_ssfc.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
 
 enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
 {
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
 }
 
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
 {
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
 }
diff --git a/board/waddledoo/cbi_ssfc.h b/board/waddledoo/cbi_ssfc.h
index 935049b6ae..bf8853a43a 100644
--- a/board/waddledoo/cbi_ssfc.h
+++ b/board/waddledoo/cbi_ssfc.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -56,5 +56,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
  */
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
 
-
 #endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/waddledoo/ec.tasklist b/board/waddledoo/ec.tasklist
index 0aba1fabeb..ba5855412d 100644
--- a/board/waddledoo/ec.tasklist
+++ b/board/waddledoo/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/waddledoo/gpio.inc b/board/waddledoo/gpio.inc
index 69f6bc6307..6b55d890b2 100644
--- a/board/waddledoo/gpio.inc
+++ b/board/waddledoo/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/waddledoo/led.c b/board/waddledoo/led.c
index b9ff2e74e8..4315e0b87d 100644
--- a/board/waddledoo/led.c
+++ b/board/waddledoo/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,13 +20,10 @@ const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
  * both LEDs being off.
  */
 struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = {
-				/* Amber, White */
-	[EC_LED_COLOR_RED]    = {   0,   0 },
-	[EC_LED_COLOR_GREEN]  = {   0,   0 },
-	[EC_LED_COLOR_BLUE]   = {   0,   0 },
-	[EC_LED_COLOR_YELLOW] = {   0,   0 },
-	[EC_LED_COLOR_WHITE]  = {   0, 100 },
-	[EC_LED_COLOR_AMBER]  = {  100,  0 },
+	/* Amber, White */
+	[EC_LED_COLOR_RED] = { 0, 0 },	   [EC_LED_COLOR_GREEN] = { 0, 0 },
+	[EC_LED_COLOR_BLUE] = { 0, 0 },	   [EC_LED_COLOR_YELLOW] = { 0, 0 },
+	[EC_LED_COLOR_WHITE] = { 0, 100 }, [EC_LED_COLOR_AMBER] = { 100, 0 },
 };
 
 /* One logical LED with amber and white channels. */
diff --git a/board/waddledoo/usb_pd_policy.c b/board/waddledoo/usb_pd_policy.c
index 3190595596..23166f7fca 100644
--- a/board/waddledoo/usb_pd_policy.c
+++ b/board/waddledoo/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,8 @@
 #include "driver/tcpm/tcpci.h"
 #include "usb_pd.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
diff --git a/board/waddledoo2/battery.c b/board/waddledoo2/battery.c
index 887c66e355..3696d4e38c 100644
--- a/board/waddledoo2/battery.c
+++ b/board/waddledoo2/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/waddledoo2/board.c b/board/waddledoo2/board.c
index 1f7ad2da92..fd12aec449 100644
--- a/board/waddledoo2/board.c
+++ b/board/waddledoo2/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -51,13 +51,13 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 #define INT_RECHECK_US 5000
 
-#define ADC_VOL_UP_MASK     BIT(0)
-#define ADC_VOL_DOWN_MASK   BIT(1)
+#define ADC_VOL_UP_MASK BIT(0)
+#define ADC_VOL_DOWN_MASK BIT(1)
 
 static uint8_t new_adc_key_state;
 
@@ -110,8 +110,8 @@ static const struct ec_response_keybd_config waddledoo2_keybd = {
 	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
 };
 
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	return &waddledoo2_keybd;
 }
@@ -152,7 +152,6 @@ static void usb_c0_interrupt(enum gpio_signal s)
 
 	/* Check the line again in 5ms */
 	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
-
 }
 
 /* C1 interrupt line shared by BC 1.2, TCPC, and charger */
@@ -226,22 +225,22 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /* Thermistors */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_A \
-	{ \
+#define THERMAL_A                \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = 0, \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(70), \
@@ -258,8 +257,8 @@ __maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A;
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_B \
-	{ \
+#define THERMAL_B                \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_WARN] = 0, \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(73), \
@@ -334,13 +333,11 @@ int board_is_sourcing_vbus(int port)
 
 	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
 	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
-
 }
 
 int board_set_active_charge_port(int port)
 {
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	int i;
 	int old_port;
 
@@ -400,8 +397,8 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
 
@@ -426,18 +423,13 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrices to rotate accelerometers into the standard reference. */
-static const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
-
-static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					     { 0, FLOAT_TO_FP(-1), 0 },
+					     { 0, 0, FLOAT_TO_FP(-1) } };
 
+static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 },
+					      { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, 0, FLOAT_TO_FP(-1) } };
 
 /* BMA253 private data */
 static struct accelgyro_saved_data_t g_bma253_data;
@@ -445,11 +437,9 @@ static struct accelgyro_saved_data_t g_bma253_data;
 /* BMI160 private data */
 static struct bmi_drv_data_t g_bmi160_data;
 
-static const mat33_fp_t base_icm_ref = {
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t base_icm_ref = { { FLOAT_TO_FP(-1), 0, 0 },
+					 { 0, FLOAT_TO_FP(1), 0 },
+					 { 0, 0, FLOAT_TO_FP(-1) } };
 
 /* ICM426 private data */
 static struct icm_drv_data_t g_icm426xx_data;
@@ -633,7 +623,7 @@ void board_init(void)
 		gmr_tablet_switch_disable();
 		/* Base accel is not stuffed, don't allow line to float */
 		gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L,
-		GPIO_INPUT | GPIO_PULL_DOWN);
+			       GPIO_INPUT | GPIO_PULL_DOWN);
 	}
 
 	/* Turn on 5V if the system is on, otherwise turn it off. */
@@ -648,20 +638,19 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
 void motion_interrupt(enum gpio_signal signal)
 {
-		switch (get_cbi_ssfc_base_sensor()) {
-		case SSFC_SENSOR_ICM426XX:
-			icm426xx_interrupt(signal);
-			break;
-		case SSFC_SENSOR_BMI160:
-		default:
-			bmi160_interrupt(signal);
-			break;
-		}
+	switch (get_cbi_ssfc_base_sensor()) {
+	case SSFC_SENSOR_ICM426XX:
+		icm426xx_interrupt(signal);
+		break;
+	case SSFC_SENSOR_BMI160:
+	default:
+		bmi160_interrupt(signal);
+		break;
+	}
 }
 
-__override void ocpc_get_pid_constants(int *kp, int *kp_div,
-				       int *ki, int *ki_div,
-				       int *kd, int *kd_div)
+__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+				       int *ki_div, int *kd, int *kd_div)
 {
 	*kp = 1;
 	*kp_div = 20;
@@ -737,18 +726,24 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
-		.driver = &pi3usb3x532_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = PI3USB3X532_I2C_ADDR0,
+				.driver = &pi3usb3x532_usb_mux_driver,
+			},
 	},
 	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = PS8802_I2C_ADDR_FLAGS_CUSTOM,
-		.driver = &ps8802_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_SUB_USB_C1,
+				.i2c_addr_flags = PS8802_I2C_ADDR_FLAGS_CUSTOM,
+				.driver = &ps8802_usb_mux_driver,
+			},
 	}
 };
 
diff --git a/board/waddledoo2/board.h b/board/waddledoo2/board.h
index e55539bc3e..93f0a0f108 100644
--- a/board/waddledoo2/board.h
+++ b/board/waddledoo2/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,11 +22,14 @@
 
 /* Charger */
 #define CONFIG_CHARGER_RAA489000
+#define PD_MAX_VOLTAGE_MV 20000
 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 #define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */
+#define CONFIG_OCPC_DEF_RBATT_MOHMS               \
+	22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \
+	    */
 #define CONFIG_OCPC
-#undef  CONFIG_CHARGER_SINGLE_CHIP
+#undef CONFIG_CHARGER_SINGLE_CHIP
 #undef CONFIG_CMD_CHARGER_DUMP
 #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE
 #define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC)
@@ -44,7 +47,7 @@
 
 /* PWM */
 #define CONFIG_PWM
-#define NPCX7_PWM1_SEL    1  /* GPIO C2 is used as PWM1. */
+#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */
 
 /* Temp sensor */
 #define CONFIG_TEMP_SENSOR
@@ -81,16 +84,16 @@
 #define CONFIG_USB_PD_5V_EN_CUSTOM
 
 /* I2C configuration */
-#define I2C_PORT_EEPROM     NPCX_I2C_PORT7_0
-#define I2C_PORT_BATTERY    NPCX_I2C_PORT5_0
-#define I2C_PORT_SENSOR     NPCX_I2C_PORT0_0
-#define I2C_PORT_USB_C0     NPCX_I2C_PORT1_0
+#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0
+#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0
 #define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_MUX    I2C_PORT_USB_C0
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0
 /* TODO(b:147440290): Need to handle multiple charger ICs */
-#define I2C_PORT_CHARGER    I2C_PORT_USB_C0
+#define I2C_PORT_CHARGER I2C_PORT_USB_C0
 
-#define I2C_PORT_ACCEL      I2C_PORT_SENSOR
+#define I2C_PORT_ACCEL I2C_PORT_SENSOR
 
 #define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */
 
@@ -99,15 +102,15 @@
 #define CONFIG_CMD_ACCEL_INFO
 #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
 
-#define CONFIG_ACCEL_BMA255		/* Lid accel */
-#define CONFIG_ACCELGYRO_BMI160		/* Base accel */
-#define CONFIG_ACCEL_KX022		/* Lid accel */
-#define CONFIG_ACCELGYRO_ICM426XX	/* Base accel second source*/
+#define CONFIG_ACCEL_BMA255 /* Lid accel */
+#define CONFIG_ACCELGYRO_BMI160 /* Base accel */
+#define CONFIG_ACCEL_KX022 /* Lid accel */
+#define CONFIG_ACCELGYRO_ICM426XX /* Base accel second source*/
 
 /* Lid operates in forced mode, base in FIFO */
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
 #define CONFIG_ACCEL_FIFO
-#define CONFIG_ACCEL_FIFO_SIZE 256	/* Must be a power of 2 */
+#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */
 #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
 
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
@@ -143,25 +146,16 @@ enum chg_id {
 };
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_1,     /* ADC0 */
-	ADC_TEMP_SENSOR_2,     /* ADC1 */
-	ADC_SUB_ANALOG,	       /* ADC2 */
-	ADC_VSNS_PP3300_A,     /* ADC9 */
+	ADC_TEMP_SENSOR_1, /* ADC0 */
+	ADC_TEMP_SENSOR_2, /* ADC1 */
+	ADC_SUB_ANALOG, /* ADC2 */
+	ADC_VSNS_PP3300_A, /* ADC9 */
 	ADC_CH_COUNT
 };
 
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_COUNT
-};
+enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT };
 
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
 enum pwm_channel {
 	PWM_CH_KBLIGHT,
diff --git a/board/waddledoo2/build.mk b/board/waddledoo2/build.mk
index b012d8d502..eb422dae93 100644
--- a/board/waddledoo2/build.mk
+++ b/board/waddledoo2/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/waddledoo2/cbi_ssfc.c b/board/waddledoo2/cbi_ssfc.c
index c4b859f133..81f3ee0dad 100644
--- a/board/waddledoo2/cbi_ssfc.c
+++ b/board/waddledoo2/cbi_ssfc.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
 
 enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
 {
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
 }
 
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
 {
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
 }
diff --git a/board/waddledoo2/cbi_ssfc.h b/board/waddledoo2/cbi_ssfc.h
index 935049b6ae..bf8853a43a 100644
--- a/board/waddledoo2/cbi_ssfc.h
+++ b/board/waddledoo2/cbi_ssfc.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -56,5 +56,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
  */
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
 
-
 #endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/waddledoo2/ec.tasklist b/board/waddledoo2/ec.tasklist
index d4fb416bce..29666dd959 100644
--- a/board/waddledoo2/ec.tasklist
+++ b/board/waddledoo2/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/waddledoo2/gpio.inc b/board/waddledoo2/gpio.inc
index f0e345a81c..f2a95f9762 100644
--- a/board/waddledoo2/gpio.inc
+++ b/board/waddledoo2/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/waddledoo2/led.c b/board/waddledoo2/led.c
index 85bd75ce99..33e900f2ca 100644
--- a/board/waddledoo2/led.c
+++ b/board/waddledoo2/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,23 +19,28 @@ __override const int led_charge_lvl_1 = 5;
 __override const int led_charge_lvl_2 = 95;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
diff --git a/board/waddledoo2/usb_pd_policy.c b/board/waddledoo2/usb_pd_policy.c
index fd9018a3f0..3410726e87 100644
--- a/board/waddledoo2/usb_pd_policy.c
+++ b/board/waddledoo2/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,8 +10,8 @@
 #include "driver/tcpm/tcpci.h"
 #include "usb_pd.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
diff --git a/board/wheelie/battery.c b/board/wheelie/battery.c
index 96d967abec..bc2c5bec4d 100644
--- a/board/wheelie/battery.c
+++ b/board/wheelie/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/wheelie/board.c b/board/wheelie/board.c
index 0ad7590a31..9708dcca82 100644
--- a/board/wheelie/board.c
+++ b/board/wheelie/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -40,7 +40,7 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
 
 /* C0 interrupt line shared by BC 1.2 and charger */
 static void usb_c0_interrupt(enum gpio_signal s)
@@ -68,34 +68,26 @@ static void c0_ccsbu_ovp_interrupt(enum gpio_signal s)
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_VSNS_PP3300_A] = {
-		.name = "PP3300_A_PGOOD",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH0
-	},
-	[ADC_TEMP_SENSOR_1] = {
-		.name = "TEMP_SENSOR1",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH2
-	},
-	[ADC_TEMP_SENSOR_2] = {
-		.name = "TEMP_SENSOR2",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH3
-	},
-	[ADC_SUB_ANALOG] = {
-		.name = "SUB_ANALOG",
-		.factor_mul = ADC_MAX_MVOLT,
-		.factor_div = ADC_READ_MAX + 1,
-		.shift = 0,
-		.channel = CHIP_ADC_CH13
-	},
+	[ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH0 },
+	[ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH2 },
+	[ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2",
+				.factor_mul = ADC_MAX_MVOLT,
+				.factor_div = ADC_READ_MAX + 1,
+				.shift = 0,
+				.channel = CHIP_ADC_CH3 },
+	[ADC_SUB_ANALOG] = { .name = "SUB_ANALOG",
+			     .factor_mul = ADC_MAX_MVOLT,
+			     .factor_div = ADC_READ_MAX + 1,
+			     .shift = 0,
+			     .channel = CHIP_ADC_CH13 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
@@ -143,27 +135,36 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 };
 
 /* USB Retimer */
-const struct usb_mux usbc1_retimer = {
-	.usb_port = 1,
-	.i2c_port = I2C_PORT_SUB_USB_C1,
-	.i2c_addr_flags = TUSB544_I2C_ADDR_FLAGS0,
-	.driver = &tusb544_drv,
+const struct usb_mux_chain usbc1_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = 1,
+			.i2c_port = I2C_PORT_SUB_USB_C1,
+			.i2c_addr_flags = TUSB544_I2C_ADDR_FLAGS0,
+			.driver = &tusb544_drv,
+		},
 };
 
 /* USB Muxes */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_C0,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+			},
 	},
 	{
-		.usb_port = 1,
-		.i2c_port = I2C_PORT_SUB_USB_C1,
-		.i2c_addr_flags = AN7447_TCPC0_I2C_ADDR_FLAGS,
-		.driver = &anx7447_usb_mux_driver,
-		.next_mux = &usbc1_retimer,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.i2c_port = I2C_PORT_SUB_USB_C1,
+				.i2c_addr_flags = AN7447_TCPC0_I2C_ADDR_FLAGS,
+				.driver = &anx7447_usb_mux_driver,
+			},
+		.next = &usbc1_retimer,
 	},
 };
 
@@ -445,14 +446,14 @@ const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
 /* Thermistors */
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_1] = {.name = "Memory",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_1},
-	[TEMP_SENSOR_2] = {.name = "Ambient",
-			   .type = TEMP_SENSOR_TYPE_BOARD,
-			   .read = get_temp_3v3_51k1_47k_4050b,
-			   .idx = ADC_TEMP_SENSOR_2},
+	[TEMP_SENSOR_1] = { .name = "Memory",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_1 },
+	[TEMP_SENSOR_2] = { .name = "Ambient",
+			    .type = TEMP_SENSOR_TYPE_BOARD,
+			    .read = get_temp_3v3_51k1_47k_4050b,
+			    .idx = ADC_TEMP_SENSOR_2 },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
diff --git a/board/wheelie/board.h b/board/wheelie/board.h
index 194c49adb6..c53f22b512 100644
--- a/board/wheelie/board.h
+++ b/board/wheelie/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,12 +22,13 @@
 #define CONFIG_BC12_DETECT_PI3USB9201
 
 /* Charger */
-#define CONFIG_CHARGER_SM5803		/* C0 and C1: Charger */
-#define CONFIG_FPU			/* For charger calculations */
+#define CONFIG_CHARGER_SM5803 /* C0 and C1: Charger */
+#define PD_MAX_VOLTAGE_MV 15000
+#define CONFIG_FPU /* For charger calculations */
 #define CONFIG_USB_PD_VBUS_DETECT_CHARGER
 #define CONFIG_USB_PD_5V_CHARGER_CTRL
 #define CONFIG_CHARGER_OTG
-#undef  CONFIG_CHARGER_SINGLE_CHIP
+#undef CONFIG_CHARGER_SINGLE_CHIP
 
 /* LED */
 #define CONFIG_LED_PWM
@@ -37,9 +38,9 @@
 #define CONFIG_PWM
 
 /* Sensors */
-#define CONFIG_ACCEL_LIS2DE		/* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM	/* Base accel */
-#define CONFIG_SYNC			/* Camera VSYNC */
+#define CONFIG_ACCEL_LIS2DE /* Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
+#define CONFIG_SYNC /* Camera VSYNC */
 #define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
 /* Sensors without hardware FIFO are in forced mode */
@@ -56,8 +57,7 @@
 #define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
 #define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
 
-#define CONFIG_SYNC_INT_EVENT \
-	TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
+#define CONFIG_SYNC_INT_EVENT TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC)
 
 #define CONFIG_TABLET_MODE
 #define CONFIG_TABLET_MODE_SWITCH
@@ -65,8 +65,8 @@
 
 /* TCPC */
 #define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP	/* C0: ITE EC TCPC */
-#define CONFIG_USB_PD_TCPM_ANX7447	/* C1: ANX TCPC + Mux */
+#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0: ITE EC TCPC */
+#define CONFIG_USB_PD_TCPM_ANX7447 /* C1: ANX TCPC + Mux */
 #define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1
 
 /* Thermistors */
@@ -75,10 +75,10 @@
 #define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B
 
 /* USB Mux and Retimer */
-#define CONFIG_USB_MUX_IT5205			/* C1: ITE Mux */
-#define I2C_PORT_USB_MUX I2C_PORT_USB_C0	/* Required for ITE Mux */
+#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */
+#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */
 
-#define CONFIG_USBC_RETIMER_TUSB544		/* C1 Redriver: TUSB544 */
+#define CONFIG_USBC_RETIMER_TUSB544 /* C1 Redriver: TUSB544 */
 
 #ifndef __ASSEMBLER__
 
@@ -100,28 +100,18 @@ enum pwm_channel {
 };
 
 /* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	VSYNC,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, VSYNC, SENSOR_COUNT };
 
 /* ADC channels */
 enum adc_channel {
-	ADC_VSNS_PP3300_A,     /* ADC0 */
-	ADC_TEMP_SENSOR_1,     /* ADC2 */
-	ADC_TEMP_SENSOR_2,     /* ADC3 */
-	ADC_SUB_ANALOG,        /* ADC13 */
+	ADC_VSNS_PP3300_A, /* ADC0 */
+	ADC_TEMP_SENSOR_1, /* ADC2 */
+	ADC_TEMP_SENSOR_2, /* ADC3 */
+	ADC_SUB_ANALOG, /* ADC13 */
 	ADC_CH_COUNT
 };
 
-enum temp_sensor_id {
-	TEMP_SENSOR_1,
-	TEMP_SENSOR_2,
-	TEMP_SENSOR_COUNT
-};
+enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
diff --git a/board/wheelie/build.mk b/board/wheelie/build.mk
index 806168ea0d..9b862c7624 100644
--- a/board/wheelie/build.mk
+++ b/board/wheelie/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/wheelie/cbi_ssfc.c b/board/wheelie/cbi_ssfc.c
index c4b859f133..81f3ee0dad 100644
--- a/board/wheelie/cbi_ssfc.c
+++ b/board/wheelie/cbi_ssfc.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST);
 
 enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void)
 {
-	return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor;
+	return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor;
 }
 
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void)
 {
-	return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor;
+	return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor;
 }
diff --git a/board/wheelie/cbi_ssfc.h b/board/wheelie/cbi_ssfc.h
index 935049b6ae..bf8853a43a 100644
--- a/board/wheelie/cbi_ssfc.h
+++ b/board/wheelie/cbi_ssfc.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -56,5 +56,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void);
  */
 enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void);
 
-
 #endif /* _DEDEDE_CBI_SSFC__H_ */
diff --git a/board/wheelie/ec.tasklist b/board/wheelie/ec.tasklist
index 75181a4531..701c1fa099 100644
--- a/board/wheelie/ec.tasklist
+++ b/board/wheelie/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/wheelie/gpio.inc b/board/wheelie/gpio.inc
index 8979ca6ab9..eb96828e07 100644
--- a/board/wheelie/gpio.inc
+++ b/board/wheelie/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/wheelie/led.c b/board/wheelie/led.c
index 9524a68a84..59518dbe6c 100644
--- a/board/wheelie/led.c
+++ b/board/wheelie/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,13 +20,13 @@ const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
  * Board has one physical LED with red, green, and blue
  */
 struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = {
-				/* Red, Green, Blue */
-	[EC_LED_COLOR_RED]    = { 100,   0,   0 },
-	[EC_LED_COLOR_GREEN]  = {   0, 100,   0 },
-	[EC_LED_COLOR_BLUE]   = {   0,   0, 100 },
-	[EC_LED_COLOR_YELLOW] = {  50,  50,   0 },
-	[EC_LED_COLOR_WHITE]  = {  50,  50,  50 },
-	[EC_LED_COLOR_AMBER]  = {  70,  30,   0 },
+	/* Red, Green, Blue */
+	[EC_LED_COLOR_RED] = { 100, 0, 0 },
+	[EC_LED_COLOR_GREEN] = { 0, 100, 0 },
+	[EC_LED_COLOR_BLUE] = { 0, 0, 100 },
+	[EC_LED_COLOR_YELLOW] = { 50, 50, 0 },
+	[EC_LED_COLOR_WHITE] = { 50, 50, 50 },
+	[EC_LED_COLOR_AMBER] = { 70, 30, 0 },
 };
 
 /* One logical LED with red, green, and blue channels. */
diff --git a/board/wheelie/usb_pd_policy.c b/board/wheelie/usb_pd_policy.c
index 02ae21a420..3c7564fa12 100644
--- a/board/wheelie/usb_pd_policy.c
+++ b/board/wheelie/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,8 +13,8 @@
 #include "driver/tcpm/tcpci.h"
 #include "usb_pd.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
diff --git a/board/willow/battery.c b/board/willow/battery.c
index cc97838f48..a79785aaf8 100644
--- a/board/willow/battery.c
+++ b/board/willow/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/willow/board.c b/board/willow/board.c
index fcf679f108..826df6940c 100644
--- a/board/willow/board.c
+++ b/board/willow/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -30,6 +30,7 @@
 #include "it8801.h"
 #include "keyboard_scan.h"
 #include "lid_switch.h"
+#include "panic.h"
 #include "power.h"
 #include "power_button.h"
 #include "registers.h"
@@ -43,8 +44,8 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static void tcpc_alert_event(enum gpio_signal signal)
 {
@@ -56,40 +57,34 @@ static void tcpc_alert_event(enum gpio_signal signal)
 /******************************************************************************/
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
 const struct adc_t adc_channels[] = {
-	[ADC_BOARD_ID] =  {"BOARD_ID",  3300, 4096, 0, STM32_AIN(10)},
-	[ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)},
+	[ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(10) },
+	[ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8) },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 /******************************************************************************/
 /* I2C ports */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "typec",
-		.port = 0,
-		.kbps = 400,
-		.scl  = GPIO_I2C1_SCL,
-		.sda  = GPIO_I2C1_SDA
-	},
-	{
-		.name = "other",
-		.port = 1,
-		.kbps = 400,
-		.scl  = GPIO_I2C2_SCL,
-		.sda  = GPIO_I2C2_SDA
-	},
+	{ .name = "typec",
+	  .port = 0,
+	  .kbps = 400,
+	  .scl = GPIO_I2C1_SCL,
+	  .sda = GPIO_I2C1_SDA },
+	{ .name = "other",
+	  .port = 1,
+	  .kbps = 400,
+	  .scl = GPIO_I2C2_SCL,
+	  .sda = GPIO_I2C2_SDA },
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
 const struct i2c_port_t i2c_bitbang_ports[] = {
-	{
-		.name = "battery",
-		.port = 2,
-		.kbps = 100,
-		.scl  = GPIO_I2C3_SCL,
-		.sda  = GPIO_I2C3_SDA,
-		.drv = &bitbang_drv
-	},
+	{ .name = "battery",
+	  .port = 2,
+	  .kbps = 100,
+	  .scl = GPIO_I2C3_SCL,
+	  .sda = GPIO_I2C3_SDA,
+	  .drv = &bitbang_drv },
 };
 const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
 
@@ -97,8 +92,8 @@ const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports);
 
 /* power signal list.  Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_IN_SLEEP_L,   POWER_SIGNAL_ACTIVE_LOW,  "AP_IN_S3_L"},
-	{GPIO_PMIC_EC_RESETB,  POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
+	{ GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" },
+	{ GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" },
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
@@ -154,8 +149,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-static void board_hpd_status(const struct usb_mux *me,
-			     mux_state_t mux_state,
+static void board_hpd_status(const struct usb_mux *me, mux_state_t mux_state,
 			     bool *ack_required)
 {
 	/* This driver does not use host command ACKs */
@@ -168,13 +162,16 @@ static void board_hpd_status(const struct usb_mux *me,
 	host_set_single_event(EC_HOST_EVENT_USB_MUX);
 }
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
-		.driver = &it5205_usb_mux_driver,
-		.hpd_update = &board_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.i2c_port = I2C_PORT_USB_MUX,
+				.i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS,
+				.driver = &it5205_usb_mux_driver,
+				.hpd_update = &board_hpd_status,
+			},
 	},
 };
 
@@ -237,12 +234,12 @@ int board_set_active_charge_port(int charge_port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	charge_ma = (charge_ma * 95) / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-			       CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 int board_discharge_on_ac(int enable)
@@ -299,8 +296,7 @@ static void board_spi_enable(void)
 	/* Pin mux spi peripheral toward the sensor. */
 	gpio_config_module(MODULE_SPI_CONTROLLER, 1);
 }
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP,
-	     board_spi_enable,
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_spi_enable,
 	     MOTION_SENSE_HOOK_PRIO - 1);
 
 static void board_spi_disable(void)
@@ -314,8 +310,7 @@ static void board_spi_disable(void)
 	spi_enable(&spi_devices[0], 0);
 	STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
 }
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN,
-	     board_spi_disable,
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_spi_disable,
 	     MOTION_SENSE_HOOK_PRIO + 1);
 #endif /* !VARIANT_KUKUI_NO_SENSORS */
 
@@ -354,11 +349,9 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Rotation matrixes */
-static const mat33_fp_t base_standard_ref = {
-	{FLOAT_TO_FP(1), 0, 0},
-	{0, FLOAT_TO_FP(1), 0},
-	{0, 0, FLOAT_TO_FP(1)}
-};
+static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+					      { 0, FLOAT_TO_FP(1), 0 },
+					      { 0, 0, FLOAT_TO_FP(1) } };
 
 /* sensor private data */
 static struct kionix_accel_data g_kx022_data;
diff --git a/board/willow/board.h b/board/willow/board.h
index 5bfc06d615..18745a07a4 100644
--- a/board/willow/board.h
+++ b/board/willow/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -50,7 +50,7 @@
 
 /* Motion Sensors */
 #ifndef VARIANT_KUKUI_NO_SENSORS
-#define CONFIG_ACCEL_KX022	/* Lid accel */
+#define CONFIG_ACCEL_KX022 /* Lid accel */
 #define CONFIG_ACCELGYRO_BMI160 /* Base accel */
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
@@ -67,20 +67,20 @@
 #endif /* VARIANT_KUKUI_NO_SENSORS */
 
 /* I2C ports */
-#define I2C_PORT_BC12               0
-#define I2C_PORT_TCPC0              0
-#define I2C_PORT_USB_MUX            0
-#define I2C_PORT_CHARGER            board_get_charger_i2c()
-#define I2C_PORT_SENSORS            1
-#define I2C_PORT_KB_DISCRETE        1
-#define I2C_PORT_VIRTUAL_BATTERY    I2C_PORT_BATTERY
-#define I2C_PORT_BATTERY            2
+#define I2C_PORT_BC12 0
+#define I2C_PORT_TCPC0 0
+#define I2C_PORT_USB_MUX 0
+#define I2C_PORT_CHARGER board_get_charger_i2c()
+#define I2C_PORT_SENSORS 1
+#define I2C_PORT_KB_DISCRETE 1
+#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
+#define I2C_PORT_BATTERY 2
 
 /* IT8801 I2C address */
-#define KB_DISCRETE_I2C_ADDR_FLAGS  IT8801_I2C_ADDR1
+#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1
 
 /* Enable Accel over SPI */
-#define CONFIG_SPI_ACCEL_PORT    0  /* The first SPI controller port (SPI2) */
+#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */
 
 #define CONFIG_KEYBOARD_PROTOCOL_MKBP
 #define CONFIG_MKBP_EVENT
diff --git a/board/willow/build.mk b/board/willow/build.mk
index a6e1c010d7..f583684804 100644
--- a/board/willow/build.mk
+++ b/board/willow/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/willow/ec.tasklist b/board/willow/ec.tasklist
index c1330b86f8..fb131b8eb4 100644
--- a/board/willow/ec.tasklist
+++ b/board/willow/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/willow/gpio.inc b/board/willow/gpio.inc
index 9c1bffe194..684e1997c9 100644
--- a/board/willow/gpio.inc
+++ b/board/willow/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/willow/led.c b/board/willow/led.c
index c579cb6165..fc74d4ba8b 100644
--- a/board/willow/led.c
+++ b/board/willow/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -15,22 +15,27 @@
 __override const int led_charge_lvl_1 = 5;
 __override const int led_charge_lvl_2 = 95;
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 __override void led_set_color_battery(enum ec_led_colors color)
 {
diff --git a/board/woomax/battery.c b/board/woomax/battery.c
index bd46c51cc7..0bed2f03f5 100644
--- a/board/woomax/battery.c
+++ b/board/woomax/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/woomax/board.c b/board/woomax/board.c
index e45fd91623..747c576fc2 100644
--- a/board/woomax/board.c
+++ b/board/woomax/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,7 +19,7 @@
 #include "driver/retimer/pi3hdx1204.h"
 #include "driver/retimer/ps8802.h"
 #include "driver/retimer/ps8811.h"
-#include "driver/retimer/ps8818.h"
+#include "driver/retimer/ps8818_public.h"
 #include "driver/temp_sensor/sb_tsi.h"
 #include "driver/usb_mux/amd_fp5.h"
 #include "extpower.h"
@@ -44,8 +44,8 @@
 
 #include "gpio_list.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* Motion sensors */
 static struct mutex g_lid_mutex;
@@ -64,15 +64,15 @@ static const mat33_fp_t lid_standard_ref = {
 };
 
 static const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)},
+	{ 0, FLOAT_TO_FP(-1), 0 },
+	{ FLOAT_TO_FP(-1), 0, 0 },
+	{ 0, 0, FLOAT_TO_FP(-1) },
 };
 
 static const mat33_fp_t base_standard_ref_icm = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ 0, 0, FLOAT_TO_FP(-1)},
+	{ FLOAT_TO_FP(1), 0, 0 },
+	{ 0, FLOAT_TO_FP(-1), 0 },
+	{ 0, 0, FLOAT_TO_FP(-1) },
 };
 
 /* TODO(gcc >= 5.0) Remove the casts to const pointer at rot_standard_ref */
@@ -294,8 +294,8 @@ static void board_chipset_resume(void)
 		int val;
 
 		rv = i2c_read8(I2C_PORT_USBA0,
-				PS8811_I2C_ADDR_FLAGS3 + PS8811_REG_PAGE1,
-				PS8811_REG1_USB_BEQ_LEVEL, &val);
+			       PS8811_I2C_ADDR_FLAGS3 + PS8811_REG_PAGE1,
+			       PS8811_REG1_USB_BEQ_LEVEL, &val);
 		if (!rv)
 			break;
 	}
@@ -307,8 +307,7 @@ static void board_chipset_resume(void)
 	if (ec_config_has_hdmi_retimer_pi3hdx1204()) {
 		ioex_set_level(IOEX_HDMI_POWER_EN_DB, 1);
 		msleep(PI3HDX1204_POWER_ON_DELAY_MS);
-		pi3hdx1204_enable(I2C_PORT_TCPC1,
-				  PI3HDX1204_I2C_ADDR_FLAGS,
+		pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS,
 				  hpd);
 	}
 }
@@ -319,9 +318,7 @@ static void board_chipset_suspend(void)
 	ioex_set_level(IOEX_USB_A0_RETIMER_EN, 0);
 
 	if (ec_config_has_hdmi_retimer_pi3hdx1204()) {
-		pi3hdx1204_enable(I2C_PORT_TCPC1,
-				  PI3HDX1204_I2C_ADDR_FLAGS,
-				  0);
+		pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS, 0);
 		ioex_set_level(IOEX_HDMI_POWER_EN_DB, 0);
 	}
 
@@ -340,35 +337,31 @@ static int woomax_ps8818_mux_set(const struct usb_mux *me,
 	/* USB specific config */
 	if (mux_state & USB_PD_MUX_USB_ENABLED) {
 		/* Boost the USB gain */
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX1EQ_10G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_18DB);
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_APTX1EQ_10G_LEVEL,
+					      PS8818_EQ_LEVEL_UP_MASK,
+					      PS8818_EQ_LEVEL_UP_18DB);
 		if (rv)
 			return rv;
 
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX2EQ_10G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_18DB);
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_APTX2EQ_10G_LEVEL,
+					      PS8818_EQ_LEVEL_UP_MASK,
+					      PS8818_EQ_LEVEL_UP_18DB);
 		if (rv)
 			return rv;
 
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX1EQ_5G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_19DB);
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_APTX1EQ_5G_LEVEL,
+					      PS8818_EQ_LEVEL_UP_MASK,
+					      PS8818_EQ_LEVEL_UP_19DB);
 		if (rv)
 			return rv;
 
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_APTX2EQ_5G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_19DB);
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_APTX2EQ_5G_LEVEL,
+					      PS8818_EQ_LEVEL_UP_MASK,
+					      PS8818_EQ_LEVEL_UP_19DB);
 		if (rv)
 			return rv;
 	}
@@ -376,11 +369,10 @@ static int woomax_ps8818_mux_set(const struct usb_mux *me,
 	/* DP specific config */
 	if (mux_state & USB_PD_MUX_DP_ENABLED) {
 		/* Boost the DP gain */
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_DPEQ_LEVEL,
-					PS8818_DPEQ_LEVEL_UP_MASK,
-					PS8818_DPEQ_LEVEL_UP_19DB);
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_DPEQ_LEVEL,
+					      PS8818_DPEQ_LEVEL_UP_MASK,
+					      PS8818_DPEQ_LEVEL_UP_19DB);
 		if (rv)
 			return rv;
 
@@ -391,21 +383,18 @@ static int woomax_ps8818_mux_set(const struct usb_mux *me,
 	}
 
 	if (!(mux_state & USB_PD_MUX_POLARITY_INVERTED)) {
-		rv = ps8818_i2c_field_update8(me,
-					PS8818_REG_PAGE1,
-					PS8818_REG1_CRX1EQ_10G_LEVEL,
-					PS8818_EQ_LEVEL_UP_MASK,
-					PS8818_EQ_LEVEL_UP_19DB);
+		rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1,
+					      PS8818_REG1_CRX1EQ_10G_LEVEL,
+					      PS8818_EQ_LEVEL_UP_MASK,
+					      PS8818_EQ_LEVEL_UP_19DB);
 		rv |= ps8818_i2c_write(me, PS8818_REG_PAGE1,
-					PS8818_REG1_APRX1_DE_LEVEL, 0x02);
+				       PS8818_REG1_APRX1_DE_LEVEL, 0x02);
 	}
 
 	/* set the RX input termination */
-	rv |= ps8818_i2c_field_update8(me,
-				PS8818_REG_PAGE1,
-				PS8818_REG1_RX_PHY,
-				PS8818_RX_INPUT_TERM_MASK,
-				PS8818_RX_INPUT_TERM_85_OHM);
+	rv |= ps8818_i2c_field_update8(me, PS8818_REG_PAGE1, PS8818_REG1_RX_PHY,
+				       PS8818_RX_INPUT_TERM_MASK,
+				       PS8818_RX_INPUT_TERM_85_OHM);
 	/* set register 0x40 ICP1 for 1G PD loop */
 	rv |= ps8818_i2c_write(me, PS8818_REG_PAGE1, 0x40, 0x84);
 
@@ -425,11 +414,10 @@ static int woomax_ps8802_mux_set(const struct usb_mux *me,
 	/* USB specific config */
 	if (mux_state & USB_PD_MUX_USB_ENABLED) {
 		/* Boost the USB gain */
-		rv = ps8802_i2c_field_update16(me,
-					PS8802_REG_PAGE2,
-					PS8802_REG2_USB_SSEQ_LEVEL,
-					PS8802_USBEQ_LEVEL_UP_MASK,
-					PS8802_USBEQ_LEVEL_UP_19DB);
+		rv = ps8802_i2c_field_update16(me, PS8802_REG_PAGE2,
+					       PS8802_REG2_USB_SSEQ_LEVEL,
+					       PS8802_USBEQ_LEVEL_UP_MASK,
+					       PS8802_USBEQ_LEVEL_UP_19DB);
 		if (rv)
 			return rv;
 	}
@@ -437,11 +425,10 @@ static int woomax_ps8802_mux_set(const struct usb_mux *me,
 	/* DP specific config */
 	if (mux_state & USB_PD_MUX_DP_ENABLED) {
 		/*Boost the DP gain */
-		rv = ps8802_i2c_field_update16(me,
-					PS8802_REG_PAGE2,
-					PS8802_REG2_DPEQ_LEVEL,
-					PS8802_DPEQ_LEVEL_UP_MASK,
-					PS8802_DPEQ_LEVEL_UP_19DB);
+		rv = ps8802_i2c_field_update16(me, PS8802_REG_PAGE2,
+					       PS8802_REG2_DPEQ_LEVEL,
+					       PS8802_DPEQ_LEVEL_UP_MASK,
+					       PS8802_DPEQ_LEVEL_UP_19DB);
 		if (rv)
 			return rv;
 
@@ -453,11 +440,10 @@ static int woomax_ps8802_mux_set(const struct usb_mux *me,
 	}
 
 	/* Set extra swing level tuning at 800mV/P0 */
-	rv = ps8802_i2c_field_update8(me,
-				PS8802_REG_PAGE1,
-				PS8802_800MV_LEVEL_TUNING,
-				PS8802_EXTRA_SWING_LEVEL_P0_MASK,
-				PS8802_EXTRA_SWING_LEVEL_P0_UP_1);
+	rv = ps8802_i2c_field_update8(me, PS8802_REG_PAGE1,
+				      PS8802_800MV_LEVEL_TUNING,
+				      PS8802_EXTRA_SWING_LEVEL_P0_MASK,
+				      PS8802_EXTRA_SWING_LEVEL_P0_UP_1);
 
 	return rv;
 }
@@ -470,6 +456,9 @@ const struct usb_mux usbc1_woomax_ps8818 = {
 	.board_set = &woomax_ps8818_mux_set,
 };
 
+/* Place holder for second mux in USBC1 chain */
+struct usb_mux_chain usbc1_mux1;
+
 static void setup_mux(void)
 {
 	if (ec_config_has_usbc1_retimer_ps8802()) {
@@ -481,13 +470,11 @@ static void setup_mux(void)
 		 * Replace usb_muxes[USBC_PORT_C1] with the PS8802
 		 * table entry.
 		 */
-		memcpy(&usb_muxes[USBC_PORT_C1],
-		       &usbc1_ps8802,
-		       sizeof(struct usb_mux));
+		usb_muxes[USBC_PORT_C1].mux = &usbc1_ps8802;
 
 		/* Set the AMD FP5 as the secondary MUX */
-		usb_muxes[USBC_PORT_C1].next_mux = &usbc1_amd_fp5_usb_mux;
-		usb_muxes[USBC_PORT_C1].board_set = &woomax_ps8802_mux_set;
+		usbc1_mux1.mux = &usbc1_amd_fp5_usb_mux;
+		usbc1_ps8802.board_set = &woomax_ps8802_mux_set;
 
 		/* Don't have the AMD FP5 flip */
 		usbc1_amd_fp5_usb_mux.flags = USB_MUX_FLAG_SET_WITHOUT_FLIP;
@@ -501,91 +488,213 @@ static void setup_mux(void)
 		 * Replace usb_muxes[USBC_PORT_C1] with the AMD FP5
 		 * table entry.
 		 */
-		memcpy(&usb_muxes[USBC_PORT_C1],
-		       &usbc1_amd_fp5_usb_mux,
-		       sizeof(struct usb_mux));
+		usb_muxes[USBC_PORT_C1].mux = &usbc1_amd_fp5_usb_mux;
 
 		/* Set the PS8818 as the secondary MUX */
-		usb_muxes[USBC_PORT_C1].next_mux = &usbc1_woomax_ps8818;
+		usbc1_mux1.mux = &usbc1_woomax_ps8818;
 	}
 }
 
-enum pi3dpx1207_usb_conf {
-	USB_DP = 0,
-	USB_DP_INV,
-	USB,
-	USB_INV,
-	DP,
-	DP_INV
-};
+enum pi3dpx1207_usb_conf { USB_DP = 0, USB_DP_INV, USB, USB_INV, DP, DP_INV };
 
 static uint8_t pi3dpx1207_picasso_eq[] = {
 	/*usb_dp*/
-	0x13, 0x11, 0x20, 0x62, 0x06, 0x5B, 0x5B,
-	0x07, 0x03, 0x40, 0xFC, 0x42, 0x71,
+	0x13,
+	0x11,
+	0x20,
+	0x62,
+	0x06,
+	0x5B,
+	0x5B,
+	0x07,
+	0x03,
+	0x40,
+	0xFC,
+	0x42,
+	0x71,
 	/*usb_dp_inv */
-	0x13, 0x11, 0x20, 0x72, 0x06, 0x03, 0x07,
-	0x5B, 0x5B, 0x23, 0xFC, 0x42, 0x71,
+	0x13,
+	0x11,
+	0x20,
+	0x72,
+	0x06,
+	0x03,
+	0x07,
+	0x5B,
+	0x5B,
+	0x23,
+	0xFC,
+	0x42,
+	0x71,
 	/*usb*/
-	0x13, 0x11, 0x20, 0x42, 0x00, 0x03, 0x07,
-	0x07, 0x03, 0x00, 0x42, 0x42, 0x71,
+	0x13,
+	0x11,
+	0x20,
+	0x42,
+	0x00,
+	0x03,
+	0x07,
+	0x07,
+	0x03,
+	0x00,
+	0x42,
+	0x42,
+	0x71,
 	/*usb_inv*/
-	0x13, 0x11, 0x20, 0x52, 0x00, 0x03, 0x07,
-	0x07, 0x03, 0x02, 0x42, 0x42, 0x71,
+	0x13,
+	0x11,
+	0x20,
+	0x52,
+	0x00,
+	0x03,
+	0x07,
+	0x07,
+	0x03,
+	0x02,
+	0x42,
+	0x42,
+	0x71,
 	/*dp*/
-	0x13, 0x11, 0x20, 0x22, 0x06, 0x5B, 0x5B,
-	0x5B, 0x5B, 0x60, 0xFC, 0xFC, 0x71,
+	0x13,
+	0x11,
+	0x20,
+	0x22,
+	0x06,
+	0x5B,
+	0x5B,
+	0x5B,
+	0x5B,
+	0x60,
+	0xFC,
+	0xFC,
+	0x71,
 	/*dp_inv*/
-	0x13, 0x11, 0x20, 0x32, 0x06, 0x5B, 0x5B,
-	0x5B, 0x5B, 0x63, 0xFC, 0xFC, 0x71,
+	0x13,
+	0x11,
+	0x20,
+	0x32,
+	0x06,
+	0x5B,
+	0x5B,
+	0x5B,
+	0x5B,
+	0x63,
+	0xFC,
+	0xFC,
+	0x71,
 };
 static uint8_t pi3dpx1207_dali_eq[] = {
 	/*usb_dp*/
-	0x13, 0x11, 0x20, 0x62, 0x06, 0x5B, 0x5B,
-	0x07, 0x07, 0x40, 0xFC, 0x42, 0x71,
+	0x13,
+	0x11,
+	0x20,
+	0x62,
+	0x06,
+	0x5B,
+	0x5B,
+	0x07,
+	0x07,
+	0x40,
+	0xFC,
+	0x42,
+	0x71,
 	/*usb_dp_inv*/
-	0x13, 0x11, 0x20, 0x72, 0x06, 0x07, 0x07,
-	0x5B, 0x5B, 0x23, 0xFC, 0x42, 0x71,
+	0x13,
+	0x11,
+	0x20,
+	0x72,
+	0x06,
+	0x07,
+	0x07,
+	0x5B,
+	0x5B,
+	0x23,
+	0xFC,
+	0x42,
+	0x71,
 	/*usb*/
-	0x13, 0x11, 0x20, 0x42, 0x00, 0x07, 0x07,
-	0x07, 0x07, 0x00, 0x42, 0x42, 0x71,
+	0x13,
+	0x11,
+	0x20,
+	0x42,
+	0x00,
+	0x07,
+	0x07,
+	0x07,
+	0x07,
+	0x00,
+	0x42,
+	0x42,
+	0x71,
 	/*usb_inv*/
-	0x13, 0x11, 0x20, 0x52, 0x00, 0x07, 0x07,
-	0x07, 0x07, 0x02, 0x42, 0x42, 0x71,
+	0x13,
+	0x11,
+	0x20,
+	0x52,
+	0x00,
+	0x07,
+	0x07,
+	0x07,
+	0x07,
+	0x02,
+	0x42,
+	0x42,
+	0x71,
 	/*dp*/
-	0x13, 0x11, 0x20, 0x22, 0x06, 0x5B, 0x5B,
-	0x5B, 0x5B, 0x60, 0xFC, 0xFC, 0x71,
+	0x13,
+	0x11,
+	0x20,
+	0x22,
+	0x06,
+	0x5B,
+	0x5B,
+	0x5B,
+	0x5B,
+	0x60,
+	0xFC,
+	0xFC,
+	0x71,
 	/*dp_inv*/
-	0x13, 0x11, 0x20, 0x32, 0x06, 0x5B, 0x5B,
-	0x5B, 0x5B, 0x63, 0xFC, 0xFC, 0x71,
+	0x13,
+	0x11,
+	0x20,
+	0x32,
+	0x06,
+	0x5B,
+	0x5B,
+	0x5B,
+	0x5B,
+	0x63,
+	0xFC,
+	0xFC,
+	0x71,
 };
 
 static int board_pi3dpx1207_mux_set(const struct usb_mux *me,
-		mux_state_t mux_state)
+				    mux_state_t mux_state)
 {
-	int  rv = EC_SUCCESS;
+	int rv = EC_SUCCESS;
 	enum pi3dpx1207_usb_conf usb_mode = 0;
 
 	/* USB */
 	if (mux_state & USB_PD_MUX_USB_ENABLED) {
 		/* USB with DP */
 		if (mux_state & USB_PD_MUX_DP_ENABLED) {
-			usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-					? USB_DP_INV
-					: USB_DP;
+			usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ?
+					   USB_DP_INV :
+					   USB_DP;
 		}
 		/* USB without DP */
 		else {
-			usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-					? USB_INV
-					: USB;
+			usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ?
+					   USB_INV :
+					   USB;
 		}
 	}
 	/* DP without USB */
 	else if (mux_state & USB_PD_MUX_DP_ENABLED) {
-		usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-				? DP_INV
-				: DP;
+		usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ? DP_INV :
+									DP;
 	}
 	/* Nothing enabled */
 	else
@@ -594,10 +703,11 @@ static int board_pi3dpx1207_mux_set(const struct usb_mux *me,
 	/* Write the retimer config byte */
 	if (ec_config_has_usbc1_retimer_ps8802())
 		rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags,
-			&pi3dpx1207_dali_eq[usb_mode*13], 13, NULL, 0);
+			      &pi3dpx1207_dali_eq[usb_mode * 13], 13, NULL, 0);
 	else
 		rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags,
-			&pi3dpx1207_picasso_eq[usb_mode*13], 13, NULL, 0);
+			      &pi3dpx1207_picasso_eq[usb_mode * 13], 13, NULL,
+			      0);
 
 	return rv;
 }
@@ -612,24 +722,30 @@ const struct pi3dpx1207_usb_control pi3dpx1207_controls[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(pi3dpx1207_controls) == USBC_PORT_COUNT);
 
-const struct usb_mux usbc0_pi3dpx1207_usb_retimer = {
-	.usb_port = USBC_PORT_C0,
-	.i2c_port = I2C_PORT_TCPC0,
-	.i2c_addr_flags = PI3DPX1207_I2C_ADDR_FLAGS,
-	.driver = &pi3dpx1207_usb_retimer,
-	.board_set = &board_pi3dpx1207_mux_set,
+const struct usb_mux_chain usbc0_pi3dpx1207_usb_retimer = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.i2c_port = I2C_PORT_TCPC0,
+			.i2c_addr_flags = PI3DPX1207_I2C_ADDR_FLAGS,
+			.driver = &pi3dpx1207_usb_retimer,
+			.board_set = &board_pi3dpx1207_mux_set,
+		},
 };
 
-struct usb_mux usb_muxes[] = {
+struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.i2c_port = I2C_PORT_USB_AP_MUX,
-		.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
-		.driver = &amd_fp5_usb_mux_driver,
-		.next_mux = &usbc0_pi3dpx1207_usb_retimer,
+		.mux = &(const struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.i2c_port = I2C_PORT_USB_AP_MUX,
+			.i2c_addr_flags = AMD_FP5_MUX_I2C_ADDR_FLAGS,
+			.driver = &amd_fp5_usb_mux_driver,
+		},
+		.next = &usbc0_pi3dpx1207_usb_retimer,
 	},
 	[USBC_PORT_C1] = {
 		/* Filled in dynamically at startup */
+		.next = &usbc1_mux1,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
@@ -667,7 +783,7 @@ DECLARE_HOOK(HOOK_INIT, setup_fw_config, HOOK_PRIO_INIT_I2C + 2);
 /* Physical fans. These are logically separate from pwm_channels. */
 const struct fan_conf fan_conf_0 = {
 	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
+	.ch = MFT_CH_0, /* Use MFT id to control fan */
 	.pgood_gpio = -1,
 	.enable_gpio = -1,
 };
@@ -758,8 +874,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_THERMISTOR \
-	{ \
+#define THERMAL_THERMISTOR       \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(95), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(100), \
@@ -774,8 +890,8 @@ __maybe_unused static const struct ec_thermal_config thermal_thermistor =
 /*
  * TODO(b/202062363): Remove when clang is fixed.
  */
-#define THERMAL_CPU \
-	{ \
+#define THERMAL_CPU              \
+	{                        \
 		.temp_host = { \
 			[EC_TEMP_THRESH_HIGH] = C_TO_K(95), \
 			[EC_TEMP_THRESH_HALT] = C_TO_K(100), \
@@ -813,8 +929,8 @@ static const struct ec_response_keybd_config woomax_kb = {
 	.capabilities = KEYBD_CAP_SCRNLOCK_KEY | KEYBD_CAP_NUMERIC_KEYPAD,
 };
 
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	return &woomax_kb;
 }
@@ -833,10 +949,9 @@ static void hdmi_hpd_handler(void)
 {
 	int hpd = gpio_get_level(GPIO_DP1_HPD_EC_IN);
 
-	pi3hdx1204_enable(I2C_PORT_TCPC1,
-			  PI3HDX1204_I2C_ADDR_FLAGS,
-			  chipset_in_or_transitioning_to_state(CHIPSET_STATE_ON)
-			  && hpd);
+	pi3hdx1204_enable(
+		I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS,
+		chipset_in_or_transitioning_to_state(CHIPSET_STATE_ON) && hpd);
 }
 DECLARE_DEFERRED(hdmi_hpd_handler);
 
@@ -856,9 +971,8 @@ int board_usbc_port_to_hpd_gpio_or_ioex(int port)
 	 * USB-C1 OPT3 DB use GPIO_USB_C1_HPD_IN_DB for board version 2
 	 */
 	else if (ec_config_has_mst_hub_rtd2141b())
-		return (board_ver >= 2)
-			? GPIO_USB_C1_HPD_IN_DB
-			: IOEX_USB_C1_HPD_IN_DB;
+		return (board_ver >= 2) ? GPIO_USB_C1_HPD_IN_DB :
+					  IOEX_USB_C1_HPD_IN_DB;
 
 	/* USB-C1 OPT1 DB use DP2_HPD. */
 	return GPIO_DP2_HPD;
diff --git a/board/woomax/board.h b/board/woomax/board.h
index 2c249d7781..20bbb8417a 100644
--- a/board/woomax/board.h
+++ b/board/woomax/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -50,36 +50,32 @@
 #define CONFIG_CUSTOM_FAN_CONTROL
 
 /* GPIO mapping from board specific name to EC common name. */
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_EC_BATT_PRES_ODL
-#define CONFIG_SCI_GPIO			GPIO_EC_FCH_SCI_ODL
-#define GPIO_AC_PRESENT			GPIO_ACOK_OD
-#define GPIO_CPU_PROCHOT		GPIO_PROCHOT_ODL
-#define GPIO_EC_INT_L			GPIO_EC_AP_INT_ODL
-#define GPIO_ENABLE_BACKLIGHT_L		GPIO_EC_EDP_BL_DISABLE
-#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-#define GPIO_PCH_PWRBTN_L		GPIO_EC_FCH_PWR_BTN_L
-#define GPIO_PCH_RSMRST_L		GPIO_EC_FCH_RSMRST_L
-#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S5_L		GPIO_SLP_S5_L
-#define GPIO_PCH_SYS_PWROK		GPIO_EC_FCH_PWROK
-#define GPIO_PCH_WAKE_L			GPIO_EC_FCH_WAKE_L
-#define GPIO_POWER_BUTTON_L		GPIO_EC_PWR_BTN_ODL
-#define GPIO_S0_PGOOD			GPIO_S0_PWROK_OD
-#define GPIO_S5_PGOOD			GPIO_EC_PWROK_OD
-#define GPIO_SYS_RESET_L		GPIO_EC_SYS_RST_L
-#define GPIO_VOLUME_DOWN_L		GPIO_VOLDN_BTN_ODL
-#define GPIO_VOLUME_UP_L		GPIO_VOLUP_BTN_ODL
-#define GPIO_WP_L			GPIO_EC_WP_L
-#define GPIO_PACKET_MODE_EN		GPIO_EC_H1_PACKET_MODE
+#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL
+#define CONFIG_SCI_GPIO GPIO_EC_FCH_SCI_ODL
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL
+#define GPIO_EC_INT_L GPIO_EC_AP_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_EDP_BL_DISABLE
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
+#define GPIO_PCH_PWRBTN_L GPIO_EC_FCH_PWR_BTN_L
+#define GPIO_PCH_RSMRST_L GPIO_EC_FCH_RSMRST_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L
+#define GPIO_PCH_SYS_PWROK GPIO_EC_FCH_PWROK
+#define GPIO_PCH_WAKE_L GPIO_EC_FCH_WAKE_L
+#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL
+#define GPIO_S0_PGOOD GPIO_S0_PWROK_OD
+#define GPIO_S5_PGOOD GPIO_EC_PWROK_OD
+#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L
+#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL
+#define GPIO_WP_L GPIO_EC_WP_L
+#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE
 
 #ifndef __ASSEMBLER__
 
-enum adc_channel {
-	ADC_TEMP_SENSOR_CHARGER,
-	ADC_TEMP_SENSOR_SOC,
-	ADC_CH_COUNT
-};
+enum adc_channel { ADC_TEMP_SENSOR_CHARGER, ADC_TEMP_SENSOR_SOC, ADC_CH_COUNT };
 
 enum battery_type {
 	BATTERY_C536,
@@ -92,11 +88,7 @@ enum mft_channel {
 	MFT_CH_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT = 0,
-	PWM_CH_FAN,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_FAN, PWM_CH_COUNT };
 
 enum temp_sensor_id {
 	TEMP_SENSOR_CHARGER = 0,
@@ -105,10 +97,7 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum usba_port {
-	USBA_PORT_A0 = 0,
-	USBA_PORT_COUNT
-};
+enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_COUNT };
 
 /*****************************************************************************
  * CBI EC FW Configuration
@@ -156,40 +145,32 @@ enum ec_cfg_usb_db_type {
 
 #include "cbi_ec_fw_config.h"
 
-#define HAS_USBC1_RETIMER_PS8802 \
-			 (BIT(WOOMAX_DB_T_OPT3_USBAC_HDMI_MSTHUB))
+#define HAS_USBC1_RETIMER_PS8802 (BIT(WOOMAX_DB_T_OPT3_USBAC_HDMI_MSTHUB))
 
 static inline bool ec_config_has_usbc1_retimer_ps8802(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_USBC1_RETIMER_PS8802);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_USBC1_RETIMER_PS8802);
 }
 
-#define HAS_USBC1_RETIMER_PS8818 \
-			(BIT(WOOMAX_DB_T_OPT1_USBAC_HMDI))
+#define HAS_USBC1_RETIMER_PS8818 (BIT(WOOMAX_DB_T_OPT1_USBAC_HMDI))
 
 static inline bool ec_config_has_usbc1_retimer_ps8818(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_USBC1_RETIMER_PS8818);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_USBC1_RETIMER_PS8818);
 }
 
-#define HAS_HDMI_RETIMER_PI3HDX1204 \
-			(BIT(WOOMAX_DB_T_OPT1_USBAC_HMDI))
+#define HAS_HDMI_RETIMER_PI3HDX1204 (BIT(WOOMAX_DB_T_OPT1_USBAC_HMDI))
 
 static inline bool ec_config_has_hdmi_retimer_pi3hdx1204(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_HDMI_RETIMER_PI3HDX1204);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_HDMI_RETIMER_PI3HDX1204);
 }
 
-#define HAS_MST_HUB_RTD2141B \
-			(BIT(WOOMAX_DB_T_OPT3_USBAC_HDMI_MSTHUB))
+#define HAS_MST_HUB_RTD2141B (BIT(WOOMAX_DB_T_OPT3_USBAC_HDMI_MSTHUB))
 
 static inline bool ec_config_has_mst_hub_rtd2141b(void)
 {
-	return !!(BIT(ec_config_get_usb_db()) &
-		  HAS_MST_HUB_RTD2141B);
+	return !!(BIT(ec_config_get_usb_db()) & HAS_MST_HUB_RTD2141B);
 }
 
 /**
@@ -206,9 +187,9 @@ static inline bool ec_config_has_mst_hub_rtd2141b(void)
 int board_usbc_port_to_hpd_gpio_or_ioex(int port);
 #define PORT_TO_HPD(port) board_usbc_port_to_hpd_gpio_or_ioex(port)
 
-extern const struct usb_mux usbc0_pi3dpx1207_usb_retimer;
-extern const struct usb_mux usbc1_ps8802;
+extern const struct usb_mux_chain usbc0_pi3dpx1207_usb_retimer;
 extern const struct usb_mux usbc1_ps8818;
+extern struct usb_mux usbc1_ps8802;
 extern struct usb_mux usbc1_amd_fp5_usb_mux;
 void hdmi_hpd_interrupt(enum gpio_signal signal);
 void motion_interrupt(enum gpio_signal signal);
diff --git a/board/woomax/build.mk b/board/woomax/build.mk
index a674573a4d..61be1882bf 100644
--- a/board/woomax/build.mk
+++ b/board/woomax/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/woomax/ec.tasklist b/board/woomax/ec.tasklist
index d9c1606eb2..abc796f74f 100644
--- a/board/woomax/ec.tasklist
+++ b/board/woomax/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/woomax/gpio.inc b/board/woomax/gpio.inc
index ade15d3d4a..f085134b2e 100644
--- a/board/woomax/gpio.inc
+++ b/board/woomax/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/woomax/led.c b/board/woomax/led.c
index 4c229d86f5..9a761bde38 100644
--- a/board/woomax/led.c
+++ b/board/woomax/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,29 +17,37 @@ __override const int led_charge_lvl_1 = 5;
 __override const int led_charge_lvl_2 = 95;
 
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC } },
+	};
 
 __override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	     3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	     3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    1 * LED_ONE_SEC },
+						  { LED_OFF,
+						    3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
 const enum ec_led_id supported_led_ids[] = {
 	EC_LED_ID_BATTERY_LED,
diff --git a/board/woomax/thermal.c b/board/woomax/thermal.c
index 98a46aad11..a2ab52cc74 100644
--- a/board/woomax/thermal.c
+++ b/board/woomax/thermal.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_THERMAL, outstr)
-#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
 
 struct fan_step {
 	/*
@@ -38,56 +38,56 @@ struct fan_step {
 static const struct fan_step fan_step_table[] = {
 	{
 		/* level 0 */
-		.on = {-1, -1, 36},
-		.off = {-1, -1, 99},
+		.on = { -1, -1, 36 },
+		.off = { -1, -1, 99 },
 		.rpm = 0,
 	},
 	{
 		/* level 1 */
-		.on = {-1, -1, 40},
-		.off = {-1, -1, 32},
+		.on = { -1, -1, 40 },
+		.off = { -1, -1, 32 },
 		.rpm = 2244,
 	},
 	{
 		/* level 2 */
-		.on = {-1, -1, 45},
-		.off = {-1, -1, 35},
+		.on = { -1, -1, 45 },
+		.off = { -1, -1, 35 },
 		.rpm = 2580,
 	},
 	{
 		/* level 3 */
-		.on = {-1, -1, 50},
-		.off = {-1, -1, 40},
+		.on = { -1, -1, 50 },
+		.off = { -1, -1, 40 },
 		.rpm = 2824,
 	},
 	{
 		/* level 4 */
-		.on = {-1, -1, 55},
-		.off = {-1, -1, 45},
+		.on = { -1, -1, 55 },
+		.off = { -1, -1, 45 },
 		.rpm = 3120,
 	},
 	{
 		/* level 5 */
-		.on = {-1, -1, 60},
-		.off = {-1, -1, 50},
+		.on = { -1, -1, 60 },
+		.off = { -1, -1, 50 },
 		.rpm = 3321,
 	},
 	{
 		/* level 6 */
-		.on = {-1, -1, 70},
-		.off = {-1, -1, 55},
+		.on = { -1, -1, 70 },
+		.off = { -1, -1, 55 },
 		.rpm = 3780,
 	},
 	{
 		/* level 7 */
-		.on = {-1, -1, 80},
-		.off = {-1, -1, 60},
+		.on = { -1, -1, 80 },
+		.off = { -1, -1, 60 },
 		.rpm = 4330,
 	},
 	{
 		/* level 8 */
-		.on = {-1, -1, 99},
-		.off = {-1, -1, 74},
+		.on = { -1, -1, 99 },
+		.off = { -1, -1, 74 },
 		.rpm = 4915,
 	},
 };
@@ -109,11 +109,11 @@ int fan_table_to_rpm(int fan, int *temp)
 	 */
 	if (temp[TEMP_SENSOR_CPU] < prev_tmp[TEMP_SENSOR_CPU]) {
 		if (temp[TEMP_SENSOR_CPU] <
-			fan_step_table[current_level].off[TEMP_SENSOR_CPU])
+		    fan_step_table[current_level].off[TEMP_SENSOR_CPU])
 			current_level = current_level - 1;
 	} else if (temp[TEMP_SENSOR_CPU] > prev_tmp[TEMP_SENSOR_CPU]) {
 		if (temp[TEMP_SENSOR_CPU] >
-			fan_step_table[current_level].on[TEMP_SENSOR_CPU])
+		    fan_step_table[current_level].on[TEMP_SENSOR_CPU])
 			current_level = current_level + 1;
 	}
 
@@ -130,10 +130,8 @@ int fan_table_to_rpm(int fan, int *temp)
 
 void board_override_fan_control(int fan, int *tmp)
 {
-	if (chipset_in_state(CHIPSET_STATE_ON |
-		CHIPSET_STATE_ANY_SUSPEND)) {
+	if (chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND)) {
 		fan_set_rpm_mode(FAN_CH(fan), 1);
-		fan_set_rpm_target(FAN_CH(fan),
-			fan_table_to_rpm(fan, tmp));
+		fan_set_rpm_target(FAN_CH(fan), fan_table_to_rpm(fan, tmp));
 	}
 }
diff --git a/board/wormdingler/base_detect.c b/board/wormdingler/base_detect.c
index 87d6ab8046..dca23b4d2e 100644
--- a/board/wormdingler/base_detect.c
+++ b/board/wormdingler/base_detect.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,8 +19,8 @@
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
 /* Make sure POGO VBUS starts later then PP3300_HUB when power on  */
 #define BASE_DETECT_EN_LATER_US (600 * MSEC)
@@ -95,8 +95,8 @@ static uint32_t pulse_width;
 
 static void print_base_detect_value(int v, int tmp_pulse_width)
 {
-	CPRINTS("%s = %d (pulse %d)", adc_channels[ADC_BASE_DET].name,
-			v, tmp_pulse_width);
+	CPRINTS("%s = %d (pulse %d)", adc_channels[ADC_BASE_DET].name, v,
+		tmp_pulse_width);
 }
 
 static void base_detect_deferred(void)
@@ -187,8 +187,7 @@ static void base_enable(void)
 {
 	/* Enable base detection interrupt. */
 	base_detect_debounce_time = get_time().val;
-	hook_call_deferred(&base_detect_deferred_data,
-			BASE_DETECT_EN_LATER_US);
+	hook_call_deferred(&base_detect_deferred_data, BASE_DETECT_EN_LATER_US);
 	gpio_enable_interrupt(GPIO_BASE_DET_L);
 }
 DECLARE_HOOK(HOOK_CHIPSET_STARTUP, base_enable, HOOK_PRIO_DEFAULT);
@@ -214,7 +213,7 @@ static void base_init(void)
 	if (system_jumped_late() && chipset_in_state(CHIPSET_STATE_ON))
 		base_enable();
 }
-DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT+1);
+DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT + 1);
 
 void base_force_state(enum ec_set_base_state_cmd state)
 {
diff --git a/board/wormdingler/battery.c b/board/wormdingler/battery.c
index bb444e59ee..001cd0474b 100644
--- a/board/wormdingler/battery.c
+++ b/board/wormdingler/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/wormdingler/board.c b/board/wormdingler/board.c
index 4ece983255..3c4dfe4b3c 100644
--- a/board/wormdingler/board.c
+++ b/board/wormdingler/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -39,10 +39,10 @@
 #include "task.h"
 #include "usbc_ppc.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define KS_DEBOUNCE_US    (30 * MSEC)  /* Debounce time for kickstand switch */
+#define KS_DEBOUNCE_US (30 * MSEC) /* Debounce time for kickstand switch */
 
 /* Forward declaration */
 static void tcpc_alert_event(enum gpio_signal signal);
@@ -119,41 +119,31 @@ static void switchcap_interrupt(enum gpio_signal signal)
 
 /* I2C port map */
 const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "power",
-		.port = I2C_PORT_POWER,
-		.kbps = 100,
-		.scl  = GPIO_EC_I2C_POWER_SCL,
-		.sda  = GPIO_EC_I2C_POWER_SDA
-	},
-	{
-		.name = "tcpc0",
-		.port = I2C_PORT_TCPC0,
-		.kbps = 1000,
-		.scl  = GPIO_EC_I2C_USB_C0_PD_SCL,
-		.sda  = GPIO_EC_I2C_USB_C0_PD_SDA
-	},
-	{
-		.name = "tcpc1",
-		.port = I2C_PORT_TCPC1,
-		.kbps = 1000,
-		.scl  = GPIO_EC_I2C_USB_C1_PD_SCL,
-		.sda  = GPIO_EC_I2C_USB_C1_PD_SDA
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_EEPROM_SCL,
-		.sda  = GPIO_EC_I2C_EEPROM_SDA
-	},
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl  = GPIO_EC_I2C_SENSOR_SCL,
-		.sda  = GPIO_EC_I2C_SENSOR_SDA
-	},
+	{ .name = "power",
+	  .port = I2C_PORT_POWER,
+	  .kbps = 100,
+	  .scl = GPIO_EC_I2C_POWER_SCL,
+	  .sda = GPIO_EC_I2C_POWER_SDA },
+	{ .name = "tcpc0",
+	  .port = I2C_PORT_TCPC0,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C0_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C0_PD_SDA },
+	{ .name = "tcpc1",
+	  .port = I2C_PORT_TCPC1,
+	  .kbps = 1000,
+	  .scl = GPIO_EC_I2C_USB_C1_PD_SCL,
+	  .sda = GPIO_EC_I2C_USB_C1_PD_SDA },
+	{ .name = "eeprom",
+	  .port = I2C_PORT_EEPROM,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_EEPROM_SCL,
+	  .sda = GPIO_EC_I2C_EEPROM_SDA },
+	{ .name = "sensor",
+	  .port = I2C_PORT_SENSOR,
+	  .kbps = 400,
+	  .scl = GPIO_EC_I2C_SENSOR_SCL,
+	  .sda = GPIO_EC_I2C_SENSOR_SDA },
 };
 
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
@@ -161,45 +151,25 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* Measure VBUS through a 1/10 voltage divider */
-	[ADC_VBUS] = {
-		"VBUS",
-		NPCX_ADC_CH1,
-		ADC_MAX_VOLT * 10,
-		ADC_READ_MAX + 1,
-		0
-	},
+	[ADC_VBUS] = { "VBUS", NPCX_ADC_CH1, ADC_MAX_VOLT * 10,
+		       ADC_READ_MAX + 1, 0 },
 	/*
 	 * Adapter current output or battery charging/discharging current (uV)
 	 * 18x amplification on charger side.
 	 */
-	[ADC_AMON_BMON] = {
-		"AMON_BMON",
-		NPCX_ADC_CH2,
-		ADC_MAX_VOLT * 1000 / 18,
-		ADC_READ_MAX + 1,
-		0
-	},
+	[ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH2, ADC_MAX_VOLT * 1000 / 18,
+			    ADC_READ_MAX + 1, 0 },
 	/*
 	 * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read
 	 * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and
 	 * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we
 	 * only divide by 2 (enough to avoid precision issues).
 	 */
-	[ADC_PSYS] = {
-		"PSYS",
-		NPCX_ADC_CH3,
-		ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1),
-		2,
-		0
-	},
+	[ADC_PSYS] = { "PSYS", NPCX_ADC_CH3,
+		       ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), 2, 0 },
 	/* Base detection */
-	[ADC_BASE_DET] = {
-		"BASE_DET",
-		NPCX_ADC_CH5,
-		ADC_MAX_VOLT,
-		ADC_READ_MAX + 1,
-		0
-	},
+	[ADC_BASE_DET] = { "BASE_DET", NPCX_ADC_CH5, ADC_MAX_VOLT,
+			   ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
@@ -217,16 +187,12 @@ const struct ln9310_config_t ln9310_config = {
 
 /* Power Path Controller */
 struct ppc_config_t ppc_chips[] = {
-	{
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-	{
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
+	{ .i2c_port = I2C_PORT_TCPC0,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
+	{ .i2c_port = I2C_PORT_TCPC1,
+	  .i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+	  .drv = &sn5s330_drv },
 };
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
@@ -257,16 +223,22 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
  * to AP. But the TCPC chip is also needed to know the HPD status; otherwise,
  * the mux misbehaves.
  */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	},
 	{
-		.usb_port = 1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	}
 };
 
@@ -297,17 +269,13 @@ enum lid_accelgyro_type {
 static enum lid_accelgyro_type lid_accelgyro_config;
 
 /* Matrix to rotate accelerometer into standard reference frame */
-const mat33_fp_t lid_standard_ref = {
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 },
+				      { 0, FLOAT_TO_FP(1), 0 },
+				      { 0, 0, FLOAT_TO_FP(1) } };
 
-const mat33_fp_t lid_standard_ref_icm42607 = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0, 0},
-	{ 0,  0, FLOAT_TO_FP(1)}
-};
+const mat33_fp_t lid_standard_ref_icm42607 = { { 0, FLOAT_TO_FP(-1), 0 },
+					       { FLOAT_TO_FP(1), 0, 0 },
+					       { 0, 0, FLOAT_TO_FP(1) } };
 
 struct motion_sensor_t icm42607_lid_accel = {
 	.name = "Lid Accel",
@@ -501,7 +469,7 @@ void board_tcpc_init(void)
 	 */
 	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
 		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
 DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
 
@@ -513,8 +481,7 @@ void board_hibernate(void)
 	 * Sensors are unpowered in hibernate. Apply PD to the
 	 * interrupt lines such that they don't float.
 	 */
-	gpio_set_flags(GPIO_ACCEL_GYRO_INT_L,
-		       GPIO_INPUT | GPIO_PULL_DOWN);
+	gpio_set_flags(GPIO_ACCEL_GYRO_INT_L, GPIO_INPUT | GPIO_PULL_DOWN);
 
 	/*
 	 * Board rev 1+ has the hardware fix. Don't need the following
@@ -611,8 +578,7 @@ void board_overcurrent_event(int port, int is_overcurrented)
 
 int board_set_active_charge_port(int port)
 {
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	int i;
 
 	if (!is_real_port && port != CHARGE_PORT_NONE)
@@ -663,24 +629,22 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	/*
 	 * Ignore lower charge ceiling on PD transition if our battery is
 	 * critical, as we may brownout.
 	 */
-	if (supplier == CHARGE_SUPPLIER_PD &&
-	    charge_ma < 1500 &&
+	if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 &&
 	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
 		CPRINTS("Using max ilim %d", max_ma);
 		charge_ma = max_ma;
 	}
 
 	charge_ma = charge_ma * 95 / 100;
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 uint16_t tcpc_get_alert_status(void)
diff --git a/board/wormdingler/board.h b/board/wormdingler/board.h
index e6415bccce..3c3ba6ead5 100644
--- a/board/wormdingler/board.h
+++ b/board/wormdingler/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,13 +13,13 @@
 #define CONFIG_BUTTON_TRIGGERED_RECOVERY
 
 /* Internal SPI flash on NPCX7 */
-#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)  /* 512KB internal spi flash */
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */
 
 /* Switchcap */
 #define CONFIG_LN9310
 
 /* Battery */
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY  "LION"
+#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION"
 #define CONFIG_BATTERY_REVIVE_DISCONNECT
 #define CONFIG_BATTERY_FUEL_GAUGE
 #define CONFIG_BATTERY_VENDOR_PARAM
@@ -80,10 +80,7 @@ enum sensor_id {
 	SENSOR_COUNT,
 };
 
-enum pwm_channel {
-	PWM_CH_DISPLIGHT = 0,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_DISPLIGHT = 0, PWM_CH_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
diff --git a/board/wormdingler/build.mk b/board/wormdingler/build.mk
index 452abeb591..363ef59a16 100644
--- a/board/wormdingler/build.mk
+++ b/board/wormdingler/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/wormdingler/ec.tasklist b/board/wormdingler/ec.tasklist
index ea2aaa97f5..8fc8115afc 100644
--- a/board/wormdingler/ec.tasklist
+++ b/board/wormdingler/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/wormdingler/gpio.inc b/board/wormdingler/gpio.inc
index 77a69a5faa..37e71977ac 100644
--- a/board/wormdingler/gpio.inc
+++ b/board/wormdingler/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/wormdingler/led.c b/board/wormdingler/led.c
index 40de6257fa..c314d584c3 100644
--- a/board/wormdingler/led.c
+++ b/board/wormdingler/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -36,15 +36,15 @@ enum led_color {
 	LED_RED,
 	LED_GREEN,
 	LED_AMBER,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static void led_set_color(enum led_color color)
 {
 	gpio_set_level(GPIO_EC_CHG_LED_R_C0,
-		(color == LED_RED) ? BAT_LED_ON : BAT_LED_OFF);
+		       (color == LED_RED) ? BAT_LED_ON : BAT_LED_OFF);
 	gpio_set_level(GPIO_EC_CHG_LED_G_C0,
-		(color == LED_GREEN) ? BAT_LED_ON : BAT_LED_OFF);
+		       (color == LED_GREEN) ? BAT_LED_ON : BAT_LED_OFF);
 	if (color == LED_AMBER) {
 		gpio_set_level(GPIO_EC_CHG_LED_R_C0, BAT_LED_ON);
 		gpio_set_level(GPIO_EC_CHG_LED_G_C0, BAT_LED_ON);
@@ -78,7 +78,6 @@ static void board_led_set_battery(void)
 	int color = LED_OFF;
 	int period = 0;
 	int percent = DIV_ROUND_NEAREST(charge_get_display_charge(), 10);
-	uint32_t chflags = charge_get_flags();
 
 	battery_ticks++;
 
@@ -86,13 +85,13 @@ static void board_led_set_battery(void)
 	case PWR_STATE_CHARGE:
 	case PWR_STATE_CHARGE_NEAR_FULL:
 		if (chipset_in_state(CHIPSET_STATE_ON |
-					CHIPSET_STATE_ANY_SUSPEND |
-					CHIPSET_STATE_ANY_OFF)) {
+				     CHIPSET_STATE_ANY_SUSPEND |
+				     CHIPSET_STATE_ANY_OFF)) {
 			if (percent <= BATTERY_LEVEL_CRITICAL) {
 				/* battery capa <= 5%, Red */
 				color = LED_RED;
 			} else if (percent > BATTERY_LEVEL_CRITICAL &&
-					percent < BATTERY_LEVEL_NEAR_FULL) {
+				   percent < BATTERY_LEVEL_NEAR_FULL) {
 				/* 5% < battery capa < 97%, Orange */
 				color = LED_AMBER;
 			} else {
@@ -102,8 +101,8 @@ static void board_led_set_battery(void)
 		}
 		break;
 	case PWR_STATE_DISCHARGE:
-			/* Always indicate off on when discharging */
-			color = LED_OFF;
+		/* Always indicate off on when discharging */
+		color = LED_OFF;
 		break;
 	case PWR_STATE_ERROR:
 		/* Battery error, Red on 1sec off 1sec */
@@ -115,16 +114,16 @@ static void board_led_set_battery(void)
 			color = LED_OFF;
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE) {
-			/* Factory mode, Red 2 sec, green 2 sec */
-			period = (2 + 2) * LED_ONE_SEC;
-			battery_ticks = battery_ticks % period;
-			if (battery_ticks < 2 * LED_ONE_SEC)
-				color = LED_RED;
-			else
-				color = LED_GREEN;
-		} else
+		color = LED_RED;
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		/* Factory mode, Red 2 sec, green 2 sec */
+		period = (2 + 2) * LED_ONE_SEC;
+		battery_ticks = battery_ticks % period;
+		if (battery_ticks < 2 * LED_ONE_SEC)
 			color = LED_RED;
+		else
+			color = LED_GREEN;
 		break;
 	default:
 		/* Other states don't alter LED behavior */
@@ -147,7 +146,7 @@ void led_control(enum ec_led_id led_id, enum ec_led_state state)
 	enum led_color color;
 
 	if ((led_id != EC_LED_ID_RECOVERY_HW_REINIT_LED) &&
-		(led_id != EC_LED_ID_SYSRQ_DEBUG_LED))
+	    (led_id != EC_LED_ID_SYSRQ_DEBUG_LED))
 		return;
 
 	if (state == LED_STATE_RESET) {
diff --git a/board/wormdingler/usbc_config.c b/board/wormdingler/usbc_config.c
index aac136415d..5d30adb6e2 100644
--- a/board/wormdingler/usbc_config.c
+++ b/board/wormdingler/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,8 @@
 #include "console.h"
 #include "usb_pd.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 const struct charger_config_t chg_chips[] = {
 	{
diff --git a/board/yorp/battery.c b/board/yorp/battery.c
index 1d8ec33d3d..d391942ab3 100644
--- a/board/yorp/battery.c
+++ b/board/yorp/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/board/yorp/board.c b/board/yorp/board.c
index 137100aec3..475ced087c 100644
--- a/board/yorp/board.c
+++ b/board/yorp/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -38,10 +38,10 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 static void ppc_interrupt(enum gpio_signal signal)
 {
@@ -64,26 +64,26 @@ static void ppc_interrupt(enum gpio_signal signal)
 
 /* ADC channels */
 const struct adc_t adc_channels[] = {
-	[ADC_TEMP_SENSOR_AMB] = {
-		"TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
-	[ADC_TEMP_SENSOR_CHARGER] = {
-		"TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0},
+	[ADC_TEMP_SENSOR_AMB] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT,
+				  ADC_READ_MAX + 1, 0 },
+	[ADC_TEMP_SENSOR_CHARGER] = { "TEMP_CHARGER", NPCX_ADC_CH1,
+				      ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
 
 const struct temp_sensor_t temp_sensors[] = {
-	[TEMP_SENSOR_BATTERY] = {.name = "Battery",
-				 .type = TEMP_SENSOR_TYPE_BATTERY,
-				 .read = charge_get_battery_temp,
-				 .idx = 0},
-	[TEMP_SENSOR_AMBIENT] = {.name = "Ambient",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_51k1_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_AMB},
-	[TEMP_SENSOR_CHARGER] = {.name = "Charger",
-				 .type = TEMP_SENSOR_TYPE_BOARD,
-				 .read = get_temp_3v3_13k7_47k_4050b,
-				 .idx = ADC_TEMP_SENSOR_CHARGER},
+	[TEMP_SENSOR_BATTERY] = { .name = "Battery",
+				  .type = TEMP_SENSOR_TYPE_BATTERY,
+				  .read = charge_get_battery_temp,
+				  .idx = 0 },
+	[TEMP_SENSOR_AMBIENT] = { .name = "Ambient",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_51k1_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_AMB },
+	[TEMP_SENSOR_CHARGER] = { .name = "Charger",
+				  .type = TEMP_SENSOR_TYPE_BOARD,
+				  .read = get_temp_3v3_13k7_47k_4050b,
+				  .idx = ADC_TEMP_SENSOR_CHARGER },
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
@@ -93,11 +93,9 @@ static struct mutex g_lid_mutex;
 static struct mutex g_base_mutex;
 
 /* Matrix to rotate accelrator into standard reference frame */
-const mat33_fp_t base_standard_ref = {
-	{ 0, FLOAT_TO_FP(-1), 0},
-	{ FLOAT_TO_FP(1), 0,  0},
-	{ 0, 0,  FLOAT_TO_FP(1)}
-};
+const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 },
+				       { FLOAT_TO_FP(1), 0, 0 },
+				       { 0, 0, FLOAT_TO_FP(1) } };
 
 /* sensor private data */
 static struct kionix_accel_data g_kx022_data;
@@ -191,14 +189,14 @@ static void board_init(void)
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
-void board_hibernate_late(void) {
-
+void board_hibernate_late(void)
+{
 	int i;
 
 	const uint32_t hibernate_pins[][2] = {
 		/* Turn off LEDs before going to hibernate */
-		{GPIO_BAT_LED_BLUE_L, GPIO_INPUT | GPIO_PULL_UP},
-		{GPIO_BAT_LED_ORANGE_L, GPIO_INPUT | GPIO_PULL_UP},
+		{ GPIO_BAT_LED_BLUE_L, GPIO_INPUT | GPIO_PULL_UP },
+		{ GPIO_BAT_LED_ORANGE_L, GPIO_INPUT | GPIO_PULL_UP },
 	};
 
 	for (i = 0; i < ARRAY_SIZE(hibernate_pins); ++i)
@@ -220,7 +218,7 @@ static void post_old_board_warning(void)
 	 * warning.
 	 */
 	CPRINTS("\n\n\n ***** BOARD ID 0 is not officially supported!!! *****"
-			"\n\n\n");
+		"\n\n\n");
 }
 DECLARE_HOOK(HOOK_INIT, post_old_board_warning, HOOK_PRIO_INIT_I2C + 1);
 #endif
diff --git a/board/yorp/board.h b/board/yorp/board.h
index 7e4dea76df..8ffb6d2781 100644
--- a/board/yorp/board.h
+++ b/board/yorp/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,8 +26,8 @@
 #define CONFIG_USB_PD_VBUS_MEASURE_NOT_PRESENT
 
 /* Sensors */
-#define CONFIG_ACCEL_KX022		/* Lid accel */
-#define CONFIG_ACCELGYRO_LSM6DSM	/* Base accel */
+#define CONFIG_ACCEL_KX022 /* Lid accel */
+#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */
 /* Sensors without hardware FIFO are in forced mode */
 #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL)
 
@@ -50,8 +50,8 @@
 #include "registers.h"
 
 enum adc_channel {
-	ADC_TEMP_SENSOR_AMB,		/* ADC0 */
-	ADC_TEMP_SENSOR_CHARGER,	/* ADC1 */
+	ADC_TEMP_SENSOR_AMB, /* ADC0 */
+	ADC_TEMP_SENSOR_CHARGER, /* ADC1 */
 	ADC_CH_COUNT
 };
 
@@ -62,18 +62,10 @@ enum temp_sensor_id {
 	TEMP_SENSOR_COUNT
 };
 
-enum pwm_channel {
-	PWM_CH_KBLIGHT,
-	PWM_CH_COUNT
-};
+enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_COUNT };
 
 /* Motion sensors */
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
 /* List of possible batteries */
 enum battery_type {
diff --git a/board/yorp/build.mk b/board/yorp/build.mk
index 3d04b75731..998a65a3de 100644
--- a/board/yorp/build.mk
+++ b/board/yorp/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/yorp/ec.tasklist b/board/yorp/ec.tasklist
index d98db145e7..977b8b01be 100644
--- a/board/yorp/ec.tasklist
+++ b/board/yorp/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/yorp/gpio.inc b/board/yorp/gpio.inc
index 9edd6107c6..b3dbf60ab8 100644
--- a/board/yorp/gpio.inc
+++ b/board/yorp/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/yorp/led.c b/board/yorp/led.c
index 37ce7446b0..f8b9898046 100644
--- a/board/yorp/led.c
+++ b/board/yorp/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,8 +10,8 @@
 #include "led_common.h"
 #include "led_onoff_states.h"
 
-#define LED_OFF_LVL	1
-#define LED_ON_LVL	0
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
 
 __override const int led_charge_lvl_1;
 
@@ -19,19 +19,28 @@ __override const int led_charge_lvl_2 = 100;
 
 /* Yorp: Note there is only LED for charge / power */
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]       = {{EC_LED_COLOR_BLUE,  2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_BLUE,  2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_BLUE,
+					     2 * LED_ONE_SEC },
+					   { EC_LED_COLOR_AMBER,
+					     2 * LED_ONE_SEC } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_BLUE,
+					    2 * LED_ONE_SEC },
+					  { EC_LED_COLOR_AMBER,
+					    2 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+	};
 BUILD_ASSERT(ARRAY_SIZE(led_bat_state_table) == LED_NUM_STATES);
 
 const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
diff --git a/board/zinger/board.c b/board/zinger/board.c
index f1249d6917..41d91ab438 100644
--- a/board/zinger/board.c
+++ b/board/zinger/board.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,8 +21,8 @@
 static uint32_t rsa_workbuf[3 * RSANUMWORDS];
 
 /* RW firmware reset vector */
-static uint32_t * const rw_rst =
-	(uint32_t *)(CONFIG_PROGRAM_MEMORY_BASE+CONFIG_RW_MEM_OFF+4);
+static uint32_t *const rw_rst =
+	(uint32_t *)(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RW_MEM_OFF + 4);
 
 /* External interrupt EXTINT7 for external comparator on PA7 */
 static void pd_rx_interrupt(void)
@@ -57,8 +57,8 @@ static int check_rw_valid(void *rw_hash)
 		return 0;
 
 	good = rsa_verify((const struct rsa_public_key *)CONFIG_RO_PUBKEY_ADDR,
-			  (const uint8_t *)CONFIG_RW_SIG_ADDR,
-			  rw_hash, rsa_workbuf);
+			  (const uint8_t *)CONFIG_RW_SIG_ADDR, rw_hash,
+			  rsa_workbuf);
 	if (!good) {
 		debug_printf("RSA FAILED\n");
 		pd_log_event(PD_EVENT_ACC_RW_FAIL, 0, 0, NULL);
@@ -75,8 +75,7 @@ int main(void)
 	void *rw_hash;
 
 	hardware_init();
-	debug_printf("%s started\n",
-		is_ro_mode() ? "RO" : "RW");
+	debug_printf("%s started\n", is_ro_mode() ? "RO" : "RW");
 
 	/* the RO partition protection is not enabled : do it */
 	if (!flash_physical_is_permanently_protected())
diff --git a/board/zinger/board.h b/board/zinger/board.h
index 0be755eb5c..1ca83354bc 100644
--- a/board/zinger/board.h
+++ b/board/zinger/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -41,7 +41,7 @@
 #undef CONFIG_FLASH_PHYSICAL
 #undef CONFIG_FMAP
 /* Not using pstate but keep some space for the public key */
-#undef  CONFIG_FW_PSTATE_SIZE
+#undef CONFIG_FW_PSTATE_SIZE
 #define CONFIG_FW_PSTATE_SIZE 544
 #define CONFIG_HIBERNATE
 #define CONFIG_HIBERNATE_WAKEUP_PINS STM32_PWR_CSR_EWUP1
@@ -59,7 +59,7 @@
 #undef CONFIG_USB_PD_DUAL_ROLE
 #undef CONFIG_USB_PD_INTERNAL_COMP
 #define CONFIG_USB_PD_LOGGING
-#undef  CONFIG_EVENT_LOG_SIZE
+#undef CONFIG_EVENT_LOG_SIZE
 #define CONFIG_EVENT_LOG_SIZE 256
 #define CONFIG_USB_PD_LOW_POWER_IDLE_WHEN_CONNECTED
 #define CONFIG_USB_PD_PORT_MAX_COUNT 1
@@ -105,10 +105,11 @@ enum adc_channel {
 #define ADC_CH_CC2_PD ADC_CH_CC1_PD
 
 /* 3.0A Rp */
-#define PD_SRC_VNC (PD_SRC_3_0_VNC_MV * 4096 / 3300/* 12-bit ADC, 3.3V range */)
+#define PD_SRC_VNC \
+	(PD_SRC_3_0_VNC_MV * 4096 / 3300 /* 12-bit ADC, 3.3V range */)
 
 /* delay necessary for the voltage transition on the power supply */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY  50000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 50000 /* us */
 #define PD_POWER_SUPPLY_TURN_OFF_DELAY 50000 /* us */
 
 /* Initialize all useful registers */
diff --git a/board/zinger/build.mk b/board/zinger/build.mk
index c85eb9df4b..da1878efe9 100644
--- a/board/zinger/build.mk
+++ b/board/zinger/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
+# Copyright 2014 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/board/zinger/ec.irqlist b/board/zinger/ec.irqlist
index 690fa950fc..186c0f6338 100644
--- a/board/zinger/ec.irqlist
+++ b/board/zinger/ec.irqlist
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/zinger/ec.tasklist b/board/zinger/ec.tasklist
index 091eb90a22..89d9ffab76 100644
--- a/board/zinger/ec.tasklist
+++ b/board/zinger/ec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/zinger/gpio.inc b/board/zinger/gpio.inc
index 6b96e08645..65e3066695 100644
--- a/board/zinger/gpio.inc
+++ b/board/zinger/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2022 The Chromium OS Authors. All rights reserved.
+ * Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/zinger/hardware.c b/board/zinger/hardware.c
index 7e6e1f8f4c..0ad5b7ff94 100644
--- a/board/zinger/hardware.c
+++ b/board/zinger/hardware.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -39,16 +39,16 @@ static void power_init(void)
 	/* enable TIM2, TIM3, TIM14, PWR */
 	STM32_RCC_APB1ENR = 0x10000103;
 	/* enable DMA, SRAM, CRC, GPA, GPB, GPF */
-	STM32_RCC_AHBENR  = 0x460045;
+	STM32_RCC_AHBENR = 0x460045;
 }
 
 /* GPIO setting helpers */
-#define OUT(n) (1 << ((n) * 2))
-#define AF(n) (2 << ((n) * 2))
-#define ANALOG(n) (3 << ((n) * 2))
+#define OUT(n) (1 << ((n)*2))
+#define AF(n) (2 << ((n)*2))
+#define ANALOG(n) (3 << ((n)*2))
 #define HIGH(n) (1 << (n))
 #define ODR(n) (1 << (n))
-#define HISPEED(n) (3 << ((n) * 2))
+#define HISPEED(n) (3 << ((n)*2))
 #define AFx(n, x) (x << (((n) % 8) * 4))
 
 static void pins_init(void)
@@ -83,9 +83,9 @@ static void pins_init(void)
 	STM32_GPIO_AFRH(GPIO_A) = AFx(9, 1) | AFx(10, 1);
 	STM32_GPIO_OTYPER(GPIO_A) = ODR(4);
 	STM32_GPIO_OSPEEDR(GPIO_A) = HISPEED(5) | HISPEED(6) | HISPEED(7);
-	STM32_GPIO_MODER(GPIO_A) = OUT(0) | ANALOG(1) | ANALOG(2) | ANALOG(3)
-				 | OUT(4) | AF(5) /*| AF(6)*/ | AF(7) | AF(9)
-				 | AF(10) | OUT(13) | OUT(14);
+	STM32_GPIO_MODER(GPIO_A) = OUT(0) | ANALOG(1) | ANALOG(2) | ANALOG(3) |
+				   OUT(4) | AF(5) /*| AF(6)*/ | AF(7) | AF(9) |
+				   AF(10) | OUT(13) | OUT(14);
 	/* set PF0 / PF1 as output */
 	STM32_GPIO_ODR(GPIO_F) = 0;
 	STM32_GPIO_MODER(GPIO_F) = OUT(0) | OUT(1);
@@ -107,7 +107,8 @@ static void adc_init(void)
 			;
 	}
 	/* Single conversion, right aligned, 12-bit */
-	STM32_ADC_CFGR1 = BIT(12); /* BIT(15) => AUTOOFF */;
+	STM32_ADC_CFGR1 = BIT(12); /* BIT(15) => AUTOOFF */
+	;
 	/* clock is ADCCLK (ADEN must be off when writing this reg) */
 	STM32_ADC_CFGR2 = 0;
 	/* Sampling time : 71.5 ADC clock cycles, about 5us */
@@ -132,8 +133,8 @@ static void uart_init(void)
 	STM32_USART_BRR(UARTN_BASE) =
 		DIV_ROUND_NEAREST(CPU_CLOCK, CONFIG_UART_BAUD_RATE);
 	/* UART enabled, 8 Data bits, oversampling x16, no parity */
-	STM32_USART_CR1(UARTN_BASE) =
-		STM32_USART_CR1_UE | STM32_USART_CR1_TE | STM32_USART_CR1_RE;
+	STM32_USART_CR1(UARTN_BASE) = STM32_USART_CR1_UE | STM32_USART_CR1_TE |
+				      STM32_USART_CR1_RE;
 	/* 1 stop bit, no fancy stuff */
 	STM32_USART_CR2(UARTN_BASE) = 0x0000;
 	/* DMA disabled, special modes disabled, error interrupt disabled */
@@ -200,7 +201,7 @@ static int watchdog_ain_id, watchdog_ain_high, watchdog_ain_low;
 static int adc_enable_last_watchdog(void)
 {
 	return adc_enable_watchdog(watchdog_ain_id, watchdog_ain_high,
-			    watchdog_ain_low);
+				   watchdog_ain_low);
 }
 
 static inline int adc_watchdog_enabled(void)
@@ -248,8 +249,7 @@ int adc_enable_watchdog(int ch, int high, int low)
 	/* Clear flags */
 	STM32_ADC_ISR = 0x8e;
 	/* Set Watchdog enable bit on a single channel / continuous mode */
-	STM32_ADC_CFGR1 = (ch << 26) | BIT(23) | BIT(22)
-			|  BIT(13) | BIT(12);
+	STM32_ADC_CFGR1 = (ch << 26) | BIT(23) | BIT(22) | BIT(13) | BIT(12);
 	/* Enable watchdog interrupt */
 	STM32_ADC_IER = BIT(7);
 	/* Start continuous conversion */
@@ -289,17 +289,17 @@ int adc_disable_watchdog(void)
 	(FLASH_TIMEOUT_US * (CPU_CLOCK / SECOND) / CYCLE_PER_FLASH_LOOP)
 
 /* Flash unlocking keys */
-#define KEY1    0x45670123
-#define KEY2    0xCDEF89AB
+#define KEY1 0x45670123
+#define KEY2 0xCDEF89AB
 
 /* Lock bits for FLASH_CR register */
-#define PG       BIT(0)
-#define PER      BIT(1)
-#define OPTPG    BIT(4)
-#define OPTER    BIT(5)
-#define STRT     BIT(6)
-#define CR_LOCK  BIT(7)
-#define OPTWRE   BIT(9)
+#define PG BIT(0)
+#define PER BIT(1)
+#define OPTPG BIT(4)
+#define OPTER BIT(5)
+#define STRT BIT(6)
+#define CR_LOCK BIT(7)
+#define OPTWRE BIT(9)
 
 int crec_flash_physical_write(int offset, int size, const char *data)
 {
@@ -369,14 +369,13 @@ int crec_flash_physical_erase(int offset, int size)
 	STM32_FLASH_CR |= PER;
 
 	for (; size > 0; size -= CONFIG_FLASH_ERASE_SIZE,
-	     offset += CONFIG_FLASH_ERASE_SIZE) {
+			 offset += CONFIG_FLASH_ERASE_SIZE) {
 		int i;
 		/* select page to erase */
 		STM32_FLASH_AR = CONFIG_PROGRAM_MEMORY_BASE + offset;
 		/* set STRT bit : start erase */
 		STM32_FLASH_CR |= STRT;
 
-
 		/* Wait for erase to complete */
 		for (i = 0; (STM32_FLASH_SR & 1) && (i < FLASH_TIMEOUT_LOOP);
 		     i++)
@@ -434,7 +433,6 @@ static void unlock_erase_optb(void)
 	STM32_FLASH_CR = OPTWRE;
 }
 
-
 static void write_optb(int byte, uint8_t value)
 {
 	volatile int16_t *hword = (uint16_t *)(STM32_OPTB_BASE + byte);
@@ -475,6 +473,6 @@ int flash_physical_is_permanently_protected(void)
 {
 	/* if RDP is still at level 0, the flash protection is not in place */
 	return (STM32_FLASH_OBR & STM32_FLASH_OBR_RDP_MASK) &&
-		/* the low 16KB (RO partition) are write-protected */
-		!(STM32_FLASH_WRPR & 0xF);
+	       /* the low 16KB (RO partition) are write-protected */
+	       !(STM32_FLASH_WRPR & 0xF);
 }
diff --git a/board/zinger/runtime.c b/board/zinger/runtime.c
index 900c7b8c2f..19c33c7f0f 100644
--- a/board/zinger/runtime.c
+++ b/board/zinger/runtime.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -106,7 +106,7 @@ static void zinger_config_hispeed_clock(void)
 	STM32_RCC_CR |= BIT(24);
 	/* Wait for PLL to be ready */
 	while (!(STM32_RCC_CR & BIT(25)))
-			;
+		;
 
 	/* switch SYSCLK to PLL */
 	STM32_RCC_CFGR = 0x00288002;
@@ -135,7 +135,7 @@ void runtime_init(void)
  * SET_RTC_MATCH_DELAY: max time to set RTC match alarm. if we set the alarm
  * in the past, it will never wake up and cause a watchdog.
  */
-#define STOP_MODE_LATENCY 300   /* us */
+#define STOP_MODE_LATENCY 300 /* us */
 #define SET_RTC_MATCH_DELAY 200 /* us */
 #define MAX_LATENCY (STOP_MODE_LATENCY + SET_RTC_MATCH_DELAY)
 
@@ -161,10 +161,10 @@ uint32_t task_wait_event(int timeout_us)
 	while (1) {
 		/* set timeout on timer */
 		if (timeout_us < 0) {
-			asm volatile ("wfi");
+			asm volatile("wfi");
 		} else if (timeout_us <= MAX_LATENCY ||
-			  t1.le.lo - timeout_us > t1.le.lo + MAX_LATENCY ||
-			  !DEEP_SLEEP_ALLOWED) {
+			   t1.le.lo - timeout_us > t1.le.lo + MAX_LATENCY ||
+			   !DEEP_SLEEP_ALLOWED) {
 			STM32_TIM32_CCR1(2) = STM32_TIM32_CNT(2) + timeout_us;
 			STM32_TIM_DIER(2) = 3; /*  match interrupt and UIE */
 
@@ -177,8 +177,8 @@ uint32_t task_wait_event(int timeout_us)
 			/* set deep sleep bit */
 			CPU_SCB_SYSCTRL |= 0x4;
 
-			set_rtc_alarm(0, timeout_us - STOP_MODE_LATENCY,
-				      &rtc0, 0);
+			set_rtc_alarm(0, timeout_us - STOP_MODE_LATENCY, &rtc0,
+				      0);
 
 			asm volatile("wfi");
 
@@ -233,8 +233,7 @@ uint32_t task_wait_event_mask(uint32_t event_mask, int timeout_us)
 	return evt & event_mask;
 }
 
-noreturn
-void __keep cpu_reset(void)
+noreturn void __keep cpu_reset(void)
 {
 	/* Disable interrupts */
 	interrupt_disable();
@@ -267,7 +266,8 @@ void exception_panic(void)
 		"bl debug_printf\n"
 #endif
 		"bl cpu_reset\n"
-	: : "r"("PANIC PC=%08x LR=%08x\n\n"));
+		:
+		: "r"("PANIC PC=%08x LR=%08x\n\n"));
 }
 
 void panic_reboot(void)
@@ -286,7 +286,9 @@ enum ec_image system_get_image_copy(void)
 
 /* --- stubs --- */
 void __hw_timer_enable_clock(int n, int enable)
-{ /* Done in hardware init */ }
+{ /* Done in hardware init */
+}
 
 void usleep(unsigned us)
-{ /* Used only as a workaround */ }
+{ /* Used only as a workaround */
+}
diff --git a/board/zinger/usb_pd_config.h b/board/zinger/usb_pd_config.h
index d0797b3d80..c3d86e2c2b 100644
--- a/board/zinger/usb_pd_config.h
+++ b/board/zinger/usb_pd_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,7 +10,7 @@
 
 /* Timer selection for baseband PD communication */
 #define TIM_CLOCK_PD_TX_C0 14
-#define TIM_CLOCK_PD_RX_C0  3
+#define TIM_CLOCK_PD_RX_C0 3
 
 #define TIM_CLOCK_PD_TX(p) TIM_CLOCK_PD_TX_C0
 #define TIM_CLOCK_PD_RX(p) TIM_CLOCK_PD_RX_C0
@@ -46,7 +46,7 @@ static inline void spi_enable_clock(int port)
 #define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
 #define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
 /* connect TIM3 CH1 to TIM3_CH2 input */
-#define TIM_CCR_CS  2
+#define TIM_CCR_CS 2
 #define EXTI_COMP_MASK(p) BIT(7)
 #define IRQ_COMP STM32_IRQ_EXTI4_15
 /* the RX is inverted, triggers on rising edge */
@@ -72,7 +72,7 @@ static inline void pd_tx_spi_reset(int port)
 static inline void pd_tx_enable(int port, int polarity)
 {
 	/* Drive SPI MISO on PA6 by putting it in AF mode  */
-	STM32_GPIO_MODER(GPIO_A) |= 0x2 << (2*6);
+	STM32_GPIO_MODER(GPIO_A) |= 0x2 << (2 * 6);
 	/* Drive TX GND on PA4 */
 	STM32_GPIO_BSRR(GPIO_A) = 1 << (4 + 16 /* Reset */);
 }
@@ -83,7 +83,7 @@ static inline void pd_tx_disable(int port, int polarity)
 	/* Put TX GND (PA4) in Hi-Z state */
 	STM32_GPIO_BSRR(GPIO_A) = BIT(4) /* Set */;
 	/* Put SPI MISO (PA6) in Hi-Z by putting it in input mode  */
-	STM32_GPIO_MODER(GPIO_A) &= ~(0x3 << (2*6));
+	STM32_GPIO_MODER(GPIO_A) &= ~(0x3 << (2 * 6));
 }
 
 /* we know the plug polarity, do the right configuration */
@@ -98,7 +98,9 @@ static inline void pd_tx_init(void)
 	/* Already done in hardware_init() */
 }
 
-static inline void pd_config_init(int port, uint8_t power_role) {}
+static inline void pd_config_init(int port, uint8_t power_role)
+{
+}
 
 static inline int pd_adc_read(int port, int cc)
 {
diff --git a/board/zinger/usb_pd_pdo.c b/board/zinger/usb_pd_pdo.c
index 13f8407d6d..36be87bd78 100644
--- a/board/zinger/usb_pd_pdo.c
+++ b/board/zinger/usb_pd_pdo.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,7 +9,7 @@
 
 /* Power Delivery Objects */
 const uint32_t pd_src_pdo[] = {
-	[PDO_IDX_5V]  = PDO_FIXED(5000,  RATED_CURRENT, PDO_FIXED_FLAGS),
+	[PDO_IDX_5V] = PDO_FIXED(5000, RATED_CURRENT, PDO_FIXED_FLAGS),
 	[PDO_IDX_12V] = PDO_FIXED(12000, RATED_CURRENT, PDO_FIXED_FLAGS),
 	[PDO_IDX_20V] = PDO_FIXED(20000, RATED_CURRENT, PDO_FIXED_FLAGS),
 };
diff --git a/board/zinger/usb_pd_pdo.h b/board/zinger/usb_pd_pdo.h
index 07b7129202..45f6668077 100644
--- a/board/zinger/usb_pd_pdo.h
+++ b/board/zinger/usb_pd_pdo.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/board/zinger/usb_pd_policy.c b/board/zinger/usb_pd_policy.c
index 08314e7aa6..7f60ce8772 100644
--- a/board/zinger/usb_pd_policy.c
+++ b/board/zinger/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,6 +9,7 @@
 #include "debug_printf.h"
 #include "ec_commands.h"
 #include "hooks.h"
+#include "printf.h"
 #include "registers.h"
 #include "system.h"
 #include "task.h"
@@ -20,15 +21,15 @@
 /* ------------------------- Power supply control ------------------------ */
 
 /* GPIO level setting helpers through BSRR register */
-#define GPIO_SET(n)   (1 << (n))
+#define GPIO_SET(n) (1 << (n))
 #define GPIO_RESET(n) (1 << ((n) + 16))
 
 /* Output voltage selection */
 enum volt {
-	VO_5V  = GPIO_RESET(13) | GPIO_RESET(14),
-	VO_12V = GPIO_SET(13)   | GPIO_RESET(14),
+	VO_5V = GPIO_RESET(13) | GPIO_RESET(14),
+	VO_12V = GPIO_SET(13) | GPIO_RESET(14),
 	VO_13V = GPIO_RESET(13) | GPIO_SET(14),
-	VO_20V = GPIO_SET(13)   | GPIO_SET(14),
+	VO_20V = GPIO_SET(13) | GPIO_SET(14),
 };
 
 static inline void set_output_voltage(enum volt v)
@@ -73,26 +74,27 @@ static timestamp_t fault_deadline;
 /* ADC in 12-bit mode */
 #define ADC_SCALE BIT(12)
 /* ADC power supply : VDDA = 3.3V */
-#define VDDA_MV   3300
+#define VDDA_MV 3300
 /* Current sense resistor : 5 milliOhm */
-#define R_SENSE   5
+#define R_SENSE 5
 /* VBUS voltage is measured through 10k / 100k voltage divider = /11 */
-#define VOLT_DIV  ((10+100)/10)
+#define VOLT_DIV ((10 + 100) / 10)
 /* The current sensing op-amp has a x100 gain */
 #define CURR_GAIN 100
 /* convert VBUS voltage in raw ADC value */
-#define VBUS_MV(mv) ((mv)*ADC_SCALE/VOLT_DIV/VDDA_MV)
+#define VBUS_MV(mv) ((mv)*ADC_SCALE / VOLT_DIV / VDDA_MV)
 /* convert VBUS current in raw ADC value */
-#define VBUS_MA(ma) ((ma)*ADC_SCALE*R_SENSE/1000*CURR_GAIN/VDDA_MV)
+#define VBUS_MA(ma) ((ma)*ADC_SCALE * R_SENSE / 1000 * CURR_GAIN / VDDA_MV)
 /* convert raw ADC value to mA */
-#define ADC_TO_CURR_MA(vbus) ((vbus)*1000/(ADC_SCALE*R_SENSE)*VDDA_MV/CURR_GAIN)
+#define ADC_TO_CURR_MA(vbus) \
+	((vbus)*1000 / (ADC_SCALE * R_SENSE) * VDDA_MV / CURR_GAIN)
 /* convert raw ADC value to mV */
-#define ADC_TO_VOLT_MV(vbus) ((vbus)*VOLT_DIV*VDDA_MV/ADC_SCALE)
+#define ADC_TO_VOLT_MV(vbus) ((vbus)*VOLT_DIV * VDDA_MV / ADC_SCALE)
 
 /* Max current : 20% over rated current */
-#define MAX_CURRENT VBUS_MA(RATED_CURRENT * 6/5)
+#define MAX_CURRENT VBUS_MA(RATED_CURRENT * 6 / 5)
 /* Fast short circuit protection : 50% over rated current */
-#define MAX_CURRENT_FAST VBUS_MA(RATED_CURRENT * 3/2)
+#define MAX_CURRENT_FAST VBUS_MA(RATED_CURRENT * 3 / 2)
 /* reset over-current after 1 second */
 #define OCP_TIMEOUT SECOND
 
@@ -100,19 +102,19 @@ static timestamp_t fault_deadline;
 #define SINK_IDLE_CURRENT VBUS_MA(500 /* mA */)
 
 /* Under-voltage limit is 0.8x Vnom */
-#define UVP_MV(mv)  VBUS_MV((mv) * 8 / 10)
+#define UVP_MV(mv) VBUS_MV((mv)*8 / 10)
 /* Over-voltage limit is 1.2x Vnom */
-#define OVP_MV(mv)  VBUS_MV((mv) * 12 / 10)
+#define OVP_MV(mv) VBUS_MV((mv)*12 / 10)
 /* Over-voltage recovery threshold is 1.1x Vnom */
-#define OVP_REC_MV(mv)  VBUS_MV((mv) * 11 / 10)
+#define OVP_REC_MV(mv) VBUS_MV((mv)*11 / 10)
 
 /* Maximum discharging delay */
-#define DISCHARGE_TIMEOUT (275*MSEC)
+#define DISCHARGE_TIMEOUT (275 * MSEC)
 /* Voltage overshoot below the OVP threshold for discharging to avoid OVP */
 #define DISCHARGE_OVERSHOOT_MV VBUS_MV(200)
 
 /* Time to wait after last RX edge interrupt before allowing deep sleep */
-#define PD_RX_SLEEP_TIMEOUT (100*MSEC)
+#define PD_RX_SLEEP_TIMEOUT (100 * MSEC)
 
 /* ----- output voltage discharging ----- */
 
@@ -151,16 +153,15 @@ static void discharge_voltage(int target_volt)
 /* PDO voltages (should match the table above) */
 static const struct {
 	enum volt select; /* GPIO configuration to select the voltage */
-	int       uvp;    /* under-voltage limit in mV */
-	int       ovp;    /* over-voltage limit in mV */
-	int       ovp_rec;/* over-voltage recovery threshold in mV */
+	int uvp; /* under-voltage limit in mV */
+	int ovp; /* over-voltage limit in mV */
+	int ovp_rec; /* over-voltage recovery threshold in mV */
 } voltages[ARRAY_SIZE(pd_src_pdo)] = {
-	[PDO_IDX_5V]  = {VO_5V,  UVP_MV(5000),  OVP_MV(5000),
-						OVP_REC_MV(5000)},
-	[PDO_IDX_12V] = {VO_12V, UVP_MV(12000), OVP_MV(12000),
-						OVP_REC_MV(12000)},
-	[PDO_IDX_20V] = {VO_20V, UVP_MV(20000), OVP_MV(20000),
-						OVP_REC_MV(20000)},
+	[PDO_IDX_5V] = { VO_5V, UVP_MV(5000), OVP_MV(5000), OVP_REC_MV(5000) },
+	[PDO_IDX_12V] = { VO_12V, UVP_MV(12000), OVP_MV(12000),
+			  OVP_REC_MV(12000) },
+	[PDO_IDX_20V] = { VO_20V, UVP_MV(20000), OVP_MV(20000),
+			  OVP_REC_MV(20000) },
 };
 
 /* current and previous selected PDO entry */
@@ -199,8 +200,8 @@ void pd_transition_voltage(int idx)
 			/* Make sure discharging is disabled */
 			discharge_disable();
 			/* Enable over-current monitoring */
-			adc_enable_watchdog(ADC_CH_A_SENSE,
-					    MAX_CURRENT_FAST, 0);
+			adc_enable_watchdog(ADC_CH_A_SENSE, MAX_CURRENT_FAST,
+					    0);
 		}
 	}
 	set_output_voltage(voltages[volt_idx].select);
@@ -241,28 +242,22 @@ void pd_power_supply_reset(int port)
 	}
 }
 
-int pd_check_data_swap(int port,
-		       enum pd_data_role data_role)
+int pd_check_data_swap(int port, enum pd_data_role data_role)
 {
 	/* Allow data swap if we are a DFP, otherwise don't allow */
 	return (data_role == PD_ROLE_DFP) ? 1 : 0;
 }
 
-void pd_execute_data_swap(int port,
-			  enum pd_data_role data_role)
+void pd_execute_data_swap(int port, enum pd_data_role data_role)
 {
 	/* Do nothing */
 }
 
-void pd_check_pr_role(int port,
-		      enum pd_power_role pr_role,
-		      int flags)
+void pd_check_pr_role(int port, enum pd_power_role pr_role, int flags)
 {
 }
 
-void pd_check_dr_role(int port,
-		      enum pd_data_role dr_role,
-		      int flags)
+void pd_check_dr_role(int port, enum pd_data_role dr_role, int flags)
 {
 	/* If DFP, try to switch to UFP */
 	if ((flags & PD_FLAGS_PARTNER_DR_DATA) && dr_role == PD_ROLE_DFP)
@@ -289,7 +284,7 @@ int pd_board_checks(void)
 			__enter_hibernate(0, 0);
 		}
 	} else {
-		hib_to.val = get_time().val + 60*SECOND;
+		hib_to.val = get_time().val + 60 * SECOND;
 		hib_to_ready = 1;
 	}
 #endif
@@ -319,8 +314,8 @@ int pd_board_checks(void)
 		/* trigger the slow OCP iff all 4 samples are above the max */
 		if (count == 3) {
 			debug_printf("OCP %d mA\n",
-			  vbus_amp * VDDA_MV / CURR_GAIN * 1000
-				   / R_SENSE / ADC_SCALE);
+				     vbus_amp * VDDA_MV / CURR_GAIN * 1000 /
+					     R_SENSE / ADC_SCALE);
 			pd_log_event(PD_EVENT_PS_FAULT, 0, PS_FAULT_OCP, NULL);
 			fault = FAULT_OCP;
 			/* reset over-current after 1 second */
@@ -349,8 +344,7 @@ int pd_board_checks(void)
 	if ((output_is_enabled() && (vbus_volt > voltages[ovp_idx].ovp)) ||
 	    (fault && (vbus_volt > voltages[ovp_idx].ovp_rec))) {
 		if (!fault) {
-			debug_printf("OVP %d mV\n",
-				     ADC_TO_VOLT_MV(vbus_volt));
+			debug_printf("OVP %d mV\n", ADC_TO_VOLT_MV(vbus_volt));
 			pd_log_event(PD_EVENT_PS_FAULT, 0, PS_FAULT_OVP, NULL);
 		}
 		fault = FAULT_OVP;
@@ -361,7 +355,7 @@ int pd_board_checks(void)
 
 	/* the discharge did not work properly */
 	if (discharge_is_enabled() &&
-		(get_time().val > discharge_deadline.val)) {
+	    (get_time().val > discharge_deadline.val)) {
 		/* ensure we always finish a 2-step discharge */
 		volt_idx = discharge_volt_idx;
 		set_output_voltage(voltages[volt_idx].select);
@@ -369,8 +363,7 @@ int pd_board_checks(void)
 		discharge_disable();
 		/* enable over-current monitoring */
 		adc_enable_watchdog(ADC_CH_A_SENSE, MAX_CURRENT_FAST, 0);
-		debug_printf("Disch FAIL %d mV\n",
-			     ADC_TO_VOLT_MV(vbus_volt));
+		debug_printf("Disch FAIL %d mV\n", ADC_TO_VOLT_MV(vbus_volt));
 		pd_log_event(PD_EVENT_PS_FAULT, 0, PS_FAULT_DISCH, NULL);
 		fault = FAULT_DISCHARGE;
 		/* reset it after 1 second */
@@ -390,7 +383,6 @@ int pd_board_checks(void)
 	}
 
 	return EC_SUCCESS;
-
 }
 
 static void pd_adc_interrupt(void)
@@ -407,10 +399,10 @@ static void pd_adc_interrupt(void)
 		} else { /* discharge complete */
 			discharge_disable();
 			/* enable over-current monitoring */
-			adc_enable_watchdog(ADC_CH_A_SENSE,
-					    MAX_CURRENT_FAST, 0);
+			adc_enable_watchdog(ADC_CH_A_SENSE, MAX_CURRENT_FAST,
+					    0);
 		}
-	} else {/* Over-current detection */
+	} else { /* Over-current detection */
 		/* cut the power output */
 		pd_power_supply_reset(0);
 		/* record a special fault */
@@ -453,9 +445,7 @@ static int svdm_response_svids(int port, uint32_t *payload)
 #define MODE_CNT 1
 #define OPOS 1
 
-const uint32_t vdo_dp_mode[MODE_CNT] =  {
-	VDO_MODE_GOOGLE(MODE_GOOGLE_FU)
-};
+const uint32_t vdo_dp_mode[MODE_CNT] = { VDO_MODE_GOOGLE(MODE_GOOGLE_FU) };
 
 static int svdm_response_modes(int port, uint32_t *payload)
 {
@@ -499,16 +489,17 @@ const struct svdm_response svdm_rsp = {
 };
 
 __override int pd_custom_vdm(int port, int cnt, uint32_t *payload,
-		  uint32_t **rpayload)
+			     uint32_t **rpayload)
 {
 	int cmd = PD_VDO_CMD(payload[0]);
 	int rsize;
+	char ts_str[PRINTF_TIMESTAMP_BUF_SIZE];
 
 	if (PD_VDO_VID(payload[0]) != USB_VID_GOOGLE || !gfu_mode)
 		return 0;
 
-	debug_printf("%pT] VDM/%d [%d] %08x\n",
-		     PRINTF_TIMESTAMP_NOW, cnt, cmd, payload[0]);
+	snprintf_timestamp_now(ts_str, sizeof(ts_str));
+	debug_printf("%s] VDM/%d [%d] %08x\n", ts_str, cnt, cmd, payload[0]);
 	*rpayload = payload;
 
 	rsize = pd_custom_flash_vdm(port, cnt, payload);
diff --git a/builtin/assert.h b/builtin/assert.h
index 010198fd1b..b667a0d2a2 100644
--- a/builtin/assert.h
+++ b/builtin/assert.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,6 +11,8 @@
 /* Include CONFIG definitions for EC sources. */
 #ifndef THIRD_PARTY
 #include "common.h"
+#else
+#define test_mockable_noreturn noreturn
 #endif
 
 #ifdef __cplusplus
@@ -21,7 +23,7 @@ extern "C" {
 #ifdef CONFIG_DEBUG_ASSERT_REBOOTS
 
 #ifdef CONFIG_DEBUG_ASSERT_BRIEF
-noreturn void panic_assert_fail(const char *fname, int linenum);
+test_mockable_noreturn void panic_assert_fail(const char *fname, int linenum);
 #define ASSERT(cond)                                           \
 	do {                                                   \
 		if (!(cond))                                   \
@@ -30,8 +32,8 @@ noreturn void panic_assert_fail(const char *fname, int linenum);
 
 #else /* !CONFIG_DEBUG_ASSERT_BRIEF */
 
-noreturn void panic_assert_fail(const char *msg, const char *func,
-				const char *fname, int linenum);
+test_mockable_noreturn void panic_assert_fail(const char *msg, const char *func,
+					      const char *fname, int linenum);
 #define ASSERT(cond)                                                 \
 	do {                                                         \
 		if (!(cond))                                         \
diff --git a/builtin/build.mk b/builtin/build.mk
new file mode 100644
index 0000000000..6613bfec05
--- /dev/null
+++ b/builtin/build.mk
@@ -0,0 +1,6 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Build for EC's standard library implementation.
+builtin-y=stdlib.o
diff --git a/builtin/ctype.h b/builtin/ctype.h
new file mode 100644
index 0000000000..8844adca67
--- /dev/null
+++ b/builtin/ctype.h
@@ -0,0 +1,16 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_CTYPE_H__
+#define __CROS_EC_CTYPE_H__
+
+int isdigit(int c);
+int isspace(int c);
+int isalpha(int c);
+int isupper(int c);
+int isprint(int c);
+int tolower(int c);
+
+#endif /* __CROS_EC_CTYPE_H__ */
diff --git a/builtin/endian.h b/builtin/endian.h
index 65c064bb78..0220836dca 100644
--- a/builtin/endian.h
+++ b/builtin/endian.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,7 +17,7 @@ extern "C" {
  * host byte order. Note that the code currently does not require functions
  * for converting little endian integers.
  */
-#if (__BYTE_ORDER__  == __ORDER_LITTLE_ENDIAN__)
+#if (__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__)
 
 static inline uint16_t be16toh(uint16_t in)
 {
@@ -40,10 +40,10 @@ static inline uint64_t be64toh(uint64_t in)
 #define htole32(x) (uint32_t)(x)
 #define htole64(x) (uint64_t)(x)
 
-#endif  /* __BYTE_ORDER__  == __ORDER_LITTLE_ENDIAN__ */
+#endif /* __BYTE_ORDER__  == __ORDER_LITTLE_ENDIAN__ */
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif  /* __EC_BUILTIN_ENDIAN_H */
+#endif /* __EC_BUILTIN_ENDIAN_H */
diff --git a/builtin/inttypes.h b/builtin/inttypes.h
index c442fbe499..1ef305548b 100644
--- a/builtin/inttypes.h
+++ b/builtin/inttypes.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/builtin/limits.h b/builtin/limits.h
index e5deb70291..0e185614ae 100644
--- a/builtin/limits.h
+++ b/builtin/limits.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/builtin/math.h b/builtin/math.h
index 9292ac8b34..c015d9d18d 100644
--- a/builtin/math.h
+++ b/builtin/math.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/builtin/stdarg.h b/builtin/stdarg.h
index 66ab940b16..5bf0aa8aa2 100644
--- a/builtin/stdarg.h
+++ b/builtin/stdarg.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,10 +13,10 @@
  */
 
 #ifdef __GNUC__
-#define va_start(v, l)		__builtin_va_start(v, l)
-#define va_end(v)		__builtin_va_end(v)
-#define va_arg(v, l)		__builtin_va_arg(v, l)
-typedef __builtin_va_list	va_list;
+#define va_start(v, l) __builtin_va_start(v, l)
+#define va_end(v) __builtin_va_end(v)
+#define va_arg(v, l) __builtin_va_arg(v, l)
+typedef __builtin_va_list va_list;
 #else
 #include_next <stdarg.h>
 #endif
diff --git a/builtin/stdbool.h b/builtin/stdbool.h
index 6e0f92dfc0..72d4927484 100644
--- a/builtin/stdbool.h
+++ b/builtin/stdbool.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,8 +6,8 @@
 #ifndef __CROS_EC_STDBOOL_H__
 #define __CROS_EC_STDBOOL_H__
 
-#define bool    _Bool
-#define true    1
-#define false   0
+#define bool _Bool
+#define true 1
+#define false 0
 
 #endif /* __CROS_EC_STDBOOL_H__ */
diff --git a/builtin/stddef.h b/builtin/stddef.h
index 69fb1982c7..9e69ba55ad 100644
--- a/builtin/stddef.h
+++ b/builtin/stddef.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,12 +11,6 @@
 #endif
 
 typedef __SIZE_TYPE__ size_t;
-/* There is a GCC macro for a size_t type, but not for a ssize_t type.
- * The following construct convinces GCC to make __SIZE_TYPE__ signed.
- */
-#define unsigned signed
-typedef __SIZE_TYPE__ ssize_t;
-#undef unsigned
 
 #ifndef NULL
 #define NULL ((void *)0)
@@ -36,7 +30,7 @@ typedef __WCHAR_TYPE__ wchar_t;
  * check for safety.
  */
 #ifndef offsetof
-#define offsetof(TYPE, MEMBER) __builtin_offsetof (TYPE, MEMBER)
+#define offsetof(TYPE, MEMBER) __builtin_offsetof(TYPE, MEMBER)
 #endif
 
 #endif /* __CROS_EC_STDDEF_H__ */
diff --git a/builtin/stdint.h b/builtin/stdint.h
index dedc9de475..5a107e1730 100644
--- a/builtin/stdint.h
+++ b/builtin/stdint.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,43 +6,43 @@
 #ifndef __CROS_EC_STDINT_H__
 #define __CROS_EC_STDINT_H__
 
-typedef unsigned char      uint8_t;
-typedef signed char        int8_t;
+typedef unsigned char uint8_t;
+typedef signed char int8_t;
 
-typedef unsigned short     uint16_t;
-typedef signed short       int16_t;
+typedef unsigned short uint16_t;
+typedef signed short int16_t;
 
-typedef unsigned int       uint32_t;
-typedef signed int         int32_t;
+typedef unsigned int uint32_t;
+typedef signed int int32_t;
 
 typedef unsigned long long uint64_t;
-typedef signed long long   int64_t;
+typedef signed long long int64_t;
 
-typedef unsigned int       uintptr_t;
-typedef int                intptr_t;
+typedef unsigned int uintptr_t;
+typedef int intptr_t;
 
 /* uint_leastX_t represents the smallest type available with at least X bits.
  * uint_fastX_t represents the fastest type available with at least X bits.
  */
-typedef uint8_t            uint_least8_t;
-typedef uint16_t           uint_least16_t;
-typedef uint32_t           uint_least32_t;
-typedef uint64_t           uint_least64_t;
-
-typedef int8_t             int_least8_t;
-typedef int16_t            int_least16_t;
-typedef int32_t            int_least32_t;
-typedef int64_t            int_least64_t;
-
-typedef uint8_t            uint_fast8_t;
-typedef uint16_t           uint_fast16_t;
-typedef uint32_t           uint_fast32_t;
-typedef uint64_t           uint_fast64_t;
-
-typedef int8_t             int_fast8_t;
-typedef int16_t            int_fast16_t;
-typedef int32_t            int_fast32_t;
-typedef int64_t            int_fast64_t;
+typedef uint8_t uint_least8_t;
+typedef uint16_t uint_least16_t;
+typedef uint32_t uint_least32_t;
+typedef uint64_t uint_least64_t;
+
+typedef int8_t int_least8_t;
+typedef int16_t int_least16_t;
+typedef int32_t int_least32_t;
+typedef int64_t int_least64_t;
+
+typedef uint8_t uint_fast8_t;
+typedef uint16_t uint_fast16_t;
+typedef uint32_t uint_fast32_t;
+typedef uint64_t uint_fast64_t;
+
+typedef int8_t int_fast8_t;
+typedef int16_t int_fast16_t;
+typedef int32_t int_fast32_t;
+typedef int64_t int_fast64_t;
 
 #ifndef UINT8_MAX
 #define UINT8_MAX (255U)
@@ -67,12 +67,15 @@ typedef int64_t            int_fast64_t;
 #ifndef INT32_MAX
 #define INT32_MAX (2147483647U)
 #endif
+#ifndef INT32_MIN
+#define INT32_MIN (-2147483648)
+#endif
 
 #ifndef UINT64_C
-#define UINT64_C(c)	c ## ULL
+#define UINT64_C(c) c##ULL
 #endif
 #ifndef INT64_C
-#define INT64_C(c)	c ## LL
+#define INT64_C(c) c##LL
 #endif
 
 #ifndef UINT64_MAX
@@ -81,5 +84,8 @@ typedef int64_t            int_fast64_t;
 #ifndef INT64_MAX
 #define INT64_MAX INT64_C(9223372036854775807)
 #endif
+#ifndef INT64_MIN
+#define INT64_MIN (INT64_C(-9223372036854775807) - 1)
+#endif
 
 #endif /* __CROS_EC_STDINT_H__ */
diff --git a/builtin/stdio.h b/builtin/stdio.h
new file mode 100644
index 0000000000..7536499feb
--- /dev/null
+++ b/builtin/stdio.h
@@ -0,0 +1,61 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_STDIO_H__
+#define __CROS_EC_STDIO_H__
+
+#include <stddef.h>
+#include <stdarg.h>
+
+#include "common.h"
+
+/**
+ * Print formatted outut to a string.
+ *
+ * Guarantees null-termination if size!=0.
+ *
+ * @param str           Destination string
+ * @param size          Size of destination in bytes
+ * @param format        Format string
+ * @return EC_SUCCESS, or EC_ERROR_OVERFLOW if the output was truncated.
+ */
+__attribute__((__format__(__printf__, 3, 4)))
+__warn_unused_result __stdlib_compat int
+crec_snprintf(char *str, size_t size, const char *format, ...);
+
+/**
+ * Print formatted output to a string.
+ *
+ * Guarantees null-termination if size!=0.
+ *
+ * @param str           Destination string
+ * @param size          Size of destination in bytes
+ * @param format        Format string
+ * @param args          Parameters
+ * @return The string length written to str, or a negative value on error.
+ *         The negative values can be -EC_ERROR_INVAL or -EC_ERROR_OVERFLOW.
+ */
+__warn_unused_result __stdlib_compat int
+crec_vsnprintf(char *str, size_t size, const char *format, va_list args);
+
+/*
+ * Create weak aliases to the crec_* printf functions. This lets us call the
+ * crec_* printf functions in tests that link the C standard library.
+ */
+
+/**
+ * Alias to crec_snprintf.
+ */
+__attribute__((__format__(__printf__, 3, 4)))
+__warn_unused_result __stdlib_compat int
+snprintf(char *str, size_t size, const char *format, ...);
+
+/**
+ * Alias to crec_vsnprintf.
+ */
+__warn_unused_result __stdlib_compat int
+vsnprintf(char *str, size_t size, const char *format, va_list args);
+
+#endif /* __CROS_EC_STDIO_H__ */
diff --git a/common/util_stdlib.c b/builtin/stdlib.c
index 7e59b0fbc5..0d654f0395 100644
--- a/common/util_stdlib.c
+++ b/builtin/stdlib.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,8 +7,107 @@
 
 #include "common.h"
 #include "console.h"
+#include "printf.h"
 #include "util.h"
 
+#include <stdio.h>
+
+/*
+ * The following macros are defined in stdlib.h in the C standard library, which
+ * conflict with the definitions in this file.
+ */
+#undef isspace
+#undef isdigit
+#undef isalpha
+#undef isupper
+#undef isprint
+#undef tolower
+
+/* Context for snprintf() */
+struct snprintf_context {
+	char *str;
+	int size;
+};
+
+/**
+ * Add a character to the string context.
+ *
+ * @param context	Context receiving character
+ * @param c		Character to add
+ * @return 0 if character added, 1 if character dropped because no space.
+ */
+static int snprintf_addchar(void *context, int c)
+{
+	struct snprintf_context *ctx = (struct snprintf_context *)context;
+
+	if (!ctx->size)
+		return 1;
+
+	*(ctx->str++) = c;
+	ctx->size--;
+	return 0;
+}
+
+int crec_vsnprintf(char *str, size_t size, const char *format, va_list args)
+{
+	struct snprintf_context ctx;
+	int rv;
+
+	if (!str || !format || size <= 0)
+		return -EC_ERROR_INVAL;
+
+	ctx.str = str;
+	ctx.size = size - 1; /* Reserve space for terminating '\0' */
+
+	rv = vfnprintf(snprintf_addchar, &ctx, format, args);
+
+	/* Terminate string */
+	*ctx.str = '\0';
+
+	return (rv == EC_SUCCESS) ? (ctx.str - str) : -rv;
+}
+#ifndef CONFIG_ZEPHYR
+int vsnprintf(char *str, size_t size, const char *format, va_list args)
+	__attribute__((weak, alias("crec_vsnprintf")));
+#endif /* CONFIG_ZEPHYR */
+
+int crec_snprintf(char *str, size_t size, const char *format, ...)
+{
+	va_list args;
+	int rv;
+
+	va_start(args, format);
+	rv = crec_vsnprintf(str, size, format, args);
+	va_end(args);
+
+	return rv;
+}
+#ifndef CONFIG_ZEPHYR
+int snprintf(char *str, size_t size, const char *format, ...)
+	__attribute__((weak, alias("crec_snprintf")));
+#endif /* CONFIG_ZEPHYR */
+
+/*
+ * TODO(b/237712836): Zephyr's libc should provide strcasecmp. For now we'll
+ * use the EC implementation.
+ */
+__stdlib_compat int strcasecmp(const char *s1, const char *s2)
+{
+	int diff;
+
+	do {
+		diff = tolower(*s1) - tolower(*s2);
+		if (diff)
+			return diff;
+	} while (*(s1++) && *(s2++));
+	return 0;
+}
+
+/*
+ * TODO(b/237712836): Remove this conditional once strcasecmp is added to
+ * Zephyr's libc.
+ */
+#ifndef CONFIG_ZEPHYR
 __stdlib_compat size_t strlen(const char *s)
 {
 	int len = 0;
@@ -112,6 +211,44 @@ __stdlib_compat char *strstr(const char *s1, const char *s2)
 	return NULL;
 }
 
+__stdlib_compat unsigned long long int strtoull(const char *nptr, char **endptr,
+						int base)
+{
+	uint64_t result = 0;
+	int c = '\0';
+
+	while ((c = *nptr++) && isspace(c))
+		;
+
+	if (c == '+') {
+		c = *nptr++;
+	} else if (c == '-') {
+		if (endptr)
+			*endptr = (char *)nptr - 1;
+		return result;
+	}
+
+	base = find_base(base, &c, &nptr);
+
+	while (c) {
+		if (c >= '0' && c < '0' + MIN(base, 10))
+			result = result * base + (c - '0');
+		else if (c >= 'A' && c < 'A' + base - 10)
+			result = result * base + (c - 'A' + 10);
+		else if (c >= 'a' && c < 'a' + base - 10)
+			result = result * base + (c - 'a' + 10);
+		else
+			break;
+
+		c = *nptr++;
+	}
+
+	if (endptr)
+		*endptr = (char *)nptr - 1;
+	return result;
+}
+BUILD_ASSERT(sizeof(unsigned long long int) == sizeof(uint64_t));
+
 __stdlib_compat int atoi(const char *nptr)
 {
 	int result = 0;
@@ -134,8 +271,7 @@ __stdlib_compat int atoi(const char *nptr)
 	return neg ? -result : result;
 }
 
-__keep
-__stdlib_compat int memcmp(const void *s1, const void *s2, size_t len)
+__keep __stdlib_compat int memcmp(const void *s1, const void *s2, size_t len)
 {
 	const char *sa = s1;
 	const char *sb = s2;
@@ -151,17 +287,16 @@ __stdlib_compat int memcmp(const void *s1, const void *s2, size_t len)
 }
 
 #if !(__has_feature(address_sanitizer) || __has_feature(memory_sanitizer))
-__keep
-__stdlib_compat void *memcpy(void *dest, const void *src, size_t len)
+__keep __stdlib_compat void *memcpy(void *dest, const void *src, size_t len)
 {
 	char *d = (char *)dest;
 	const char *s = (const char *)src;
 	uint32_t *dw;
 	const uint32_t *sw;
 	char *head;
-	char * const tail = (char *)dest + len;
+	char *const tail = (char *)dest + len;
 	/* Set 'body' to the last word boundary */
-	uint32_t * const body = (uint32_t *)((uintptr_t)tail & ~3);
+	uint32_t *const body = (uint32_t *)((uintptr_t)tail & ~3);
 
 	if (((uintptr_t)dest & 3) != ((uintptr_t)src & 3)) {
 		/* Misaligned. no body, no tail. */
@@ -197,18 +332,17 @@ __stdlib_compat void *memcpy(void *dest, const void *src, size_t len)
 #endif /* address_sanitizer || memory_sanitizer */
 
 #if !(__has_feature(address_sanitizer) || __has_feature(memory_sanitizer))
-__keep
-__stdlib_compat __visible void *memset(void *dest, int c, size_t len)
+__keep __stdlib_compat __visible void *memset(void *dest, int c, size_t len)
 {
 	char *d = (char *)dest;
 	uint32_t cccc;
 	uint32_t *dw;
 	char *head;
-	char * const tail = (char *)dest + len;
+	char *const tail = (char *)dest + len;
 	/* Set 'body' to the last word boundary */
-	uint32_t * const body = (uint32_t *)((uintptr_t)tail & ~3);
+	uint32_t *const body = (uint32_t *)((uintptr_t)tail & ~3);
 
-	c &= 0xff;	/* Clear upper bits before ORing below */
+	c &= 0xff; /* Clear upper bits before ORing below */
 	cccc = c | (c << 8) | (c << 16) | (c << 24);
 
 	if ((uintptr_t)tail < (((uintptr_t)d + 3) & ~3))
@@ -237,8 +371,7 @@ __stdlib_compat __visible void *memset(void *dest, int c, size_t len)
 #endif /* address_sanitizer || memory_sanitizer */
 
 #if !(__has_feature(address_sanitizer) || __has_feature(memory_sanitizer))
-__keep
-__stdlib_compat void *memmove(void *dest, const void *src, size_t len)
+__keep __stdlib_compat void *memmove(void *dest, const void *src, size_t len)
 {
 	if ((uintptr_t)dest <= (uintptr_t)src ||
 	    (uintptr_t)dest >= (uintptr_t)src + len) {
@@ -253,9 +386,9 @@ __stdlib_compat void *memmove(void *dest, const void *src, size_t len)
 		uint32_t *dw;
 		const uint32_t *sw;
 		char *head;
-		char * const tail = (char *)dest;
+		char *const tail = (char *)dest;
 		/* Set 'body' to the last word boundary */
-		uint32_t * const body = (uint32_t *)(((uintptr_t)tail+3) & ~3);
+		uint32_t *const body = (uint32_t *)(((uintptr_t)tail + 3) & ~3);
 
 		if (((uintptr_t)dest & 3) != ((uintptr_t)src & 3)) {
 			/* Misaligned. no body, no tail. */
@@ -326,7 +459,7 @@ __stdlib_compat int strncmp(const char *s1, const char *s2, size_t n)
 			break;
 		s1++;
 		s2++;
-
 	}
 	return 0;
 }
+#endif /* !CONFIG_ZEPHYR */
diff --git a/builtin/stdlib.h b/builtin/stdlib.h
new file mode 100644
index 0000000000..fcce72ee8d
--- /dev/null
+++ b/builtin/stdlib.h
@@ -0,0 +1,11 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_STDLIB_H__
+#define __CROS_EC_STDLIB_H__
+
+int atoi(const char *nptr);
+
+#endif /* __CROS_EC_STDLIB_H__ */
diff --git a/builtin/stdnoreturn.h b/builtin/stdnoreturn.h
index 659d3c540f..078a0d6698 100644
--- a/builtin/stdnoreturn.h
+++ b/builtin/stdnoreturn.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,7 +9,8 @@
 /*
  * Only defined for C: https://en.cppreference.com/w/c/language/_Noreturn
  *
- * C++ uses [[noreturn]]: https://en.cppreference.com/w/cpp/language/attributes/noreturn
+ * C++ uses [[noreturn]]:
+ * https://en.cppreference.com/w/cpp/language/attributes/noreturn
  */
 #ifndef __cplusplus
 #ifndef noreturn
diff --git a/builtin/string.h b/builtin/string.h
index 8c9a71bd75..742d75a478 100644
--- a/builtin/string.h
+++ b/builtin/string.h
@@ -1,12 +1,10 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-/* This header is only needed for CR50 compatibility */
-
-#ifndef __CROS_EC_STRINGS_H__
-#define __CROS_EC_STRINGS_H__
+#ifndef __CROS_EC_STRING_H__
+#define __CROS_EC_STRING_H__
 
 #include <stddef.h>
 
@@ -20,12 +18,28 @@ void *memmove(void *dest, const void *src, size_t n);
 void *memset(void *dest, int c, size_t len);
 void *memchr(const void *buffer, int c, size_t n);
 
+size_t strlen(const char *s);
 size_t strnlen(const char *s, size_t maxlen);
 char *strncpy(char *dest, const char *src, size_t n);
 int strncmp(const char *s1, const char *s2, size_t n);
 
+/**
+ * Calculates the length of the initial segment of s which consists
+ * entirely of bytes not in reject.
+ */
+size_t strcspn(const char *s, const char *reject);
+
+/**
+ * Find the first occurrence of the substring <s2> in the string <s1>
+ *
+ * @param s1	String where <s2> is searched.
+ * @param s2	Substring to be located in <s1>
+ * @return	Pointer to the located substring or NULL if not found.
+ */
+char *strstr(const char *s1, const char *s2);
+
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* __CROS_EC_STRINGS_H__ */
+#endif /* __CROS_EC_STRING_H__ */
diff --git a/builtin/strings.h b/builtin/strings.h
new file mode 100644
index 0000000000..cbcc858c36
--- /dev/null
+++ b/builtin/strings.h
@@ -0,0 +1,14 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_STRINGS_H__
+#define __CROS_EC_STRINGS_H__
+
+#include <stddef.h>
+
+int strcasecmp(const char *s1, const char *s2);
+int strncasecmp(const char *s1, const char *s2, size_t size);
+
+#endif /* __CROS_EC_STRINGS_H__ */
diff --git a/builtin/sys/types.h b/builtin/sys/types.h
index 3f8de955e0..01fc1a7749 100644
--- a/builtin/sys/types.h
+++ b/builtin/sys/types.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The ChromiumOS Authors.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,4 +9,11 @@
 /* Data type for POSIX style clock() implementation */
 typedef long clock_t;
 
+/* There is a GCC macro for a size_t type, but not for a ssize_t type.
+ * The following construct convinces GCC to make __SIZE_TYPE__ signed.
+ */
+#define unsigned signed
+typedef __SIZE_TYPE__ ssize_t;
+#undef unsigned
+
 #endif /* __CROS_EC_SYS_TYPES_H__ */
diff --git a/builtin/time.h b/builtin/time.h
index a069ae18c9..36b07b4721 100644
--- a/builtin/time.h
+++ b/builtin/time.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/host/adc_chip.h b/chip/host/adc_chip.h
index 8754be266e..cd55e1b5fb 100644
--- a/chip/host/adc_chip.h
+++ b/chip/host/adc_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/host/build.mk b/chip/host/build.mk
index ce4fc8f704..b4a75cf3c6 100644
--- a/chip/host/build.mk
+++ b/chip/host/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
+# Copyright 2013 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/chip/host/clock.c b/chip/host/clock.c
index 2c3c48661e..4f90067f3a 100644
--- a/chip/host/clock.c
+++ b/chip/host/clock.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/chip/host/config_chip.h b/chip/host/config_chip.h
index 84e254d8a0..323fb83d33 100644
--- a/chip/host/config_chip.h
+++ b/chip/host/config_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,11 +20,11 @@
 extern char __host_flash[CONFIG_FLASH_SIZE_BYTES];
 
 #define CONFIG_PROGRAM_MEMORY_BASE ((uintptr_t)__host_flash)
-#define CONFIG_FLASH_ERASE_SIZE 0x0010	     /* erase bank size */
-#define CONFIG_FLASH_WRITE_SIZE 0x0002	     /* minimum write size */
+#define CONFIG_FLASH_ERASE_SIZE 0x0010 /* erase bank size */
+#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */
 #define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0080 /* ideal write size */
-#define CONFIG_RAM_BASE 0x0		     /* Not supported */
-#define CONFIG_RAM_SIZE                0x0 /* Not supported */
+#define CONFIG_RAM_BASE 0x0 /* Not supported */
+#define CONFIG_RAM_SIZE 0x0 /* Not supported */
 
 #define CONFIG_FPU
 
@@ -43,7 +43,7 @@ extern char __host_flash[CONFIG_FLASH_SIZE_BYTES];
 
 /* Interval between HOOK_TICK notifications */
 #define HOOK_TICK_INTERVAL_MS 250
-#define HOOK_TICK_INTERVAL    (HOOK_TICK_INTERVAL_MS * MSEC)
+#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC)
 
 /* Do NOT use common panic code (designed to output information on the UART) */
 #undef CONFIG_COMMON_PANIC_OUTPUT
diff --git a/chip/host/flash.c b/chip/host/flash.c
index 75212737e0..209489162c 100644
--- a/chip/host/flash.c
+++ b/chip/host/flash.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,6 +7,7 @@
 
 #include <stdio.h>
 
+#include "builtin/assert.h"
 #include "common.h"
 #include "config_chip.h"
 #include "flash.h"
@@ -26,8 +27,7 @@ test_mockable int flash_pre_op(void)
 static int flash_check_protect(int offset, int size)
 {
 	int first_bank = offset / CONFIG_FLASH_BANK_SIZE;
-	int last_bank = DIV_ROUND_UP(offset + size,
-				     CONFIG_FLASH_BANK_SIZE);
+	int last_bank = DIV_ROUND_UP(offset + size, CONFIG_FLASH_BANK_SIZE);
 	int bank;
 
 	for (bank = first_bank; bank < last_bank; ++bank)
@@ -124,8 +124,7 @@ int crec_flash_physical_protect_now(int all)
 
 uint32_t crec_flash_physical_get_valid_flags(void)
 {
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-	       EC_FLASH_PROTECT_RO_NOW |
+	return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW |
 	       EC_FLASH_PROTECT_ALL_NOW;
 }
 
@@ -163,8 +162,9 @@ int crec_flash_pre_init(void)
 		 */
 		if ((prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT) &&
 		    !(prot_flags & EC_FLASH_PROTECT_RO_NOW)) {
-			int rv = crec_flash_set_protect(EC_FLASH_PROTECT_RO_NOW,
-						   EC_FLASH_PROTECT_RO_NOW);
+			int rv =
+				crec_flash_set_protect(EC_FLASH_PROTECT_RO_NOW,
+						       EC_FLASH_PROTECT_RO_NOW);
 			if (rv)
 				return rv;
 
diff --git a/chip/host/gpio.c b/chip/host/gpio.c
index 3c15205ad5..b74bec52a1 100644
--- a/chip/host/gpio.c
+++ b/chip/host/gpio.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,8 +19,8 @@ static int gpio_interrupt_enabled[GPIO_COUNT];
 /* Create a dictionary of names for debug console print */
 #define GPIO_INT(name, pin, flags, signal) #name,
 #define GPIO(name, pin, flags) #name,
-const char * gpio_names[GPIO_COUNT] = {
-	#include "gpio.wrap"
+const char *gpio_names[GPIO_COUNT] = {
+#include "gpio.wrap"
 };
 #undef GPIO
 #undef GPIO_INT
@@ -92,7 +92,7 @@ test_mockable void gpio_set_flags_by_mask(uint32_t port, uint32_t mask,
 }
 
 test_mockable void gpio_set_alternate_function(uint32_t port, uint32_t mask,
-						enum gpio_alternate_func func)
+					       enum gpio_alternate_func func)
 {
 	/* Nothing */
 }
diff --git a/chip/host/host_test.h b/chip/host/host_test.h
index e2bf5448c3..39516f751e 100644
--- a/chip/host/host_test.h
+++ b/chip/host/host_test.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,4 +14,4 @@
 /* Get emulator executable name */
 const char *__get_prog_name(void);
 
-#endif  /* __CROS_EC_HOST_TEST_H */
+#endif /* __CROS_EC_HOST_TEST_H */
diff --git a/chip/host/i2c.c b/chip/host/i2c.c
index ba4ab376d2..3fddbbbac5 100644
--- a/chip/host/i2c.c
+++ b/chip/host/i2c.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -52,8 +52,7 @@ int test_attach_i2c(const int port, const uint16_t addr_flags)
 	int i;
 
 	for (i = 0; i < MAX_DETACHED_DEV_COUNT; ++i)
-		if (detached_devs[i].valid &&
-		    detached_devs[i].port == port &&
+		if (detached_devs[i].valid && detached_devs[i].port == port &&
 		    detached_devs[i].addr_flags == addr_flags)
 			break;
 
@@ -64,22 +63,19 @@ int test_attach_i2c(const int port, const uint16_t addr_flags)
 	return EC_SUCCESS;
 }
 
-static int test_check_detached(const int port,
-			       const uint16_t addr_flags)
+static int test_check_detached(const int port, const uint16_t addr_flags)
 {
 	int i;
 
 	for (i = 0; i < MAX_DETACHED_DEV_COUNT; ++i)
-		if (detached_devs[i].valid &&
-		    detached_devs[i].port == port &&
+		if (detached_devs[i].valid && detached_devs[i].port == port &&
 		    detached_devs[i].addr_flags == addr_flags)
 			return 1;
 	return 0;
 }
 
-int chip_i2c_xfer(const int port, const uint16_t addr_flags,
-		  const uint8_t *out, int out_size,
-		  uint8_t *in, int in_size, int flags)
+int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out,
+		  int out_size, uint8_t *in, int in_size, int flags)
 {
 	const struct test_i2c_xfer *p;
 	int rv;
@@ -87,9 +83,8 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags,
 	if (test_check_detached(port, addr_flags))
 		return EC_ERROR_UNKNOWN;
 	for (p = __test_i2c_xfer; p < __test_i2c_xfer_end; ++p) {
-		rv = p->routine(port, addr_flags,
-				out, out_size,
-				in, in_size, flags);
+		rv = p->routine(port, addr_flags, out, out_size, in, in_size,
+				flags);
 		if (rv != EC_ERROR_INVAL)
 			return rv;
 	}
diff --git a/chip/host/keyboard_raw.c b/chip/host/keyboard_raw.c
index 3e1f755f7f..47b9a7dda0 100644
--- a/chip/host/keyboard_raw.c
+++ b/chip/host/keyboard_raw.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/host/lpc.c b/chip/host/lpc.c
index dd64be9275..78619c5b75 100644
--- a/chip/host/lpc.c
+++ b/chip/host/lpc.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/host/persistence.c b/chip/host/persistence.c
index 44d60f1bb8..4d8ef09df1 100644
--- a/chip/host/persistence.c
+++ b/chip/host/persistence.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,6 +23,7 @@
 #include <stdio.h>
 #include <string.h>
 
+#include "builtin/assert.h"
 #include "util.h"
 
 /* The longest path in a chroot seems to be about 280 characters (as of
@@ -60,9 +61,10 @@ static void get_storage_path(char *out)
 		current = strchr(current, '/');
 	}
 
+	sz = snprintf(out, PATH_MAX - 1, "/dev/shm/EC_persist_%.*s", max_len,
+		      buf);
+	ASSERT(sz > 0);
 
-	sz = snprintf(out, PATH_MAX - 1, "/dev/shm/EC_persist_%.*s",
-		max_len, buf);
 	out[PATH_MAX - 1] = '\0';
 
 	ASSERT(sz <= max_len + max_prefix_len);
@@ -72,6 +74,7 @@ FILE *get_persistent_storage(const char *tag, const char *mode)
 {
 	char buf[PATH_MAX];
 	char path[PATH_MAX];
+	int sz;
 
 	/* There's no longer tag in use right now, and there shouldn't be. */
 	ASSERT(strlen(tag) < 32);
@@ -81,8 +84,9 @@ FILE *get_persistent_storage(const char *tag, const char *mode)
 	 * be named 'bar_persist_foo'
 	 */
 	get_storage_path(buf);
-	snprintf(path, PATH_MAX - 1, "%.*s_%32s",
-		max_len + max_prefix_len, buf, tag);
+	sz = snprintf(path, PATH_MAX - 1, "%.*s_%32s", max_len + max_prefix_len,
+		      buf, tag);
+	ASSERT(sz > 0);
 	path[PATH_MAX - 1] = '\0';
 
 	return fopen(path, mode);
@@ -97,13 +101,15 @@ void remove_persistent_storage(const char *tag)
 {
 	char buf[PATH_MAX];
 	char path[PATH_MAX];
+	int sz;
 
 	/* There's no longer tag in use right now, and there shouldn't be. */
 	ASSERT(strlen(tag) < 32);
 
 	get_storage_path(buf);
-	snprintf(path, PATH_MAX - 1, "%.*s_%32s",
-		max_len + max_prefix_len, buf, tag);
+	sz = snprintf(path, PATH_MAX - 1, "%.*s_%32s", max_len + max_prefix_len,
+		      buf, tag);
+	ASSERT(sz > 0);
 	path[PATH_MAX - 1] = '\0';
 
 	unlink(path);
diff --git a/chip/host/persistence.h b/chip/host/persistence.h
index a473f8dfb0..479788815f 100644
--- a/chip/host/persistence.h
+++ b/chip/host/persistence.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/host/reboot.c b/chip/host/reboot.c
index e932c5f11a..24d90d943d 100644
--- a/chip/host/reboot.c
+++ b/chip/host/reboot.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,10 +20,9 @@ void emulator_reboot(void)
 	ccprints("Emulator would reboot here. Fuzzing: doing nothing.");
 }
 #else /* !TEST_FUZZ */
-noreturn
-void emulator_reboot(void)
+noreturn void emulator_reboot(void)
 {
-	char *argv[] = {strdup(__get_prog_name()), NULL};
+	char *argv[] = { strdup(__get_prog_name()), NULL };
 	emulator_flush();
 	execv(__get_prog_name(), argv);
 	while (1)
diff --git a/chip/host/reboot.h b/chip/host/reboot.h
index 1c1201f451..1541e42334 100644
--- a/chip/host/reboot.h
+++ b/chip/host/reboot.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,6 +13,7 @@
 #ifndef TEST_FUZZ
 noreturn
 #endif
-void emulator_reboot(void);
+	void
+	emulator_reboot(void);
 
 #endif
diff --git a/chip/host/registers.h b/chip/host/registers.h
index 7347ce04d3..3c75686b40 100644
--- a/chip/host/registers.h
+++ b/chip/host/registers.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/host/spi_controller.c b/chip/host/spi_controller.c
index c7afea5d39..a1df53d935 100644
--- a/chip/host/spi_controller.c
+++ b/chip/host/spi_controller.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/chip/host/system.c b/chip/host/system.c
index bf63af8bf0..4a480faf77 100644
--- a/chip/host/system.c
+++ b/chip/host/system.c
@@ -1,10 +1,11 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* System module for emulator */
 
+#include "builtin/assert.h"
 #include "common.h"
 #include "ec_commands.h"
 #include "host_test.h"
@@ -44,8 +45,7 @@ static void ramdata_get_persistent(void)
 	FILE *f = get_persistent_storage("ramdata", "rb");
 
 	if ((f == NULL) || (fread(__ram_data, RAM_DATA_SIZE, 1, f) != 1)) {
-		fprintf(stderr,
-			"No RAM data found. Initializing to 0x00.\n");
+		fprintf(stderr, "No RAM data found. Initializing to 0x00.\n");
 		memset(__ram_data, 0, RAM_DATA_SIZE);
 		return;
 	}
@@ -129,14 +129,14 @@ static int load_time(timestamp_t *t)
 
 test_mockable struct panic_data *panic_get_data(void)
 {
-	return (struct panic_data *)
-		(__ram_data + RAM_DATA_SIZE - sizeof(struct panic_data));
+	return (struct panic_data *)(__ram_data + RAM_DATA_SIZE -
+				     sizeof(struct panic_data));
 }
 
 test_mockable uintptr_t get_panic_data_start(void)
 {
-	return (uintptr_t)
-		(__ram_data + RAM_DATA_SIZE - sizeof(struct panic_data));
+	return (uintptr_t)(__ram_data + RAM_DATA_SIZE -
+			   sizeof(struct panic_data));
 }
 
 test_mockable void system_reset(int flags)
diff --git a/chip/host/trng.c b/chip/host/trng.c
index 8407aa6ea1..ef3df1ad5f 100644
--- a/chip/host/trng.c
+++ b/chip/host/trng.c
@@ -1,5 +1,5 @@
 
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -21,20 +21,20 @@
 
 static unsigned int seed;
 
-test_mockable void init_trng(void)
+test_mockable void trng_init(void)
 {
 	seed = 0;
 	srand(seed);
 }
 
-test_mockable void exit_trng(void)
+test_mockable void trng_exit(void)
 {
 }
 
-test_mockable void rand_bytes(void *buffer, size_t len)
+test_mockable void trng_rand_bytes(void *buffer, size_t len)
 {
 	uint8_t *b, *end;
 
-	for (b = buffer, end = b+len; b != end; b++)
+	for (b = buffer, end = b + len; b != end; b++)
 		*b = (uint8_t)rand_r(&seed);
 }
diff --git a/chip/host/uart.c b/chip/host/uart.c
index 578924612f..9e70a6005c 100644
--- a/chip/host/uart.c
+++ b/chip/host/uart.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,6 +11,7 @@
 #include <termio.h>
 #include <unistd.h>
 
+#include "builtin/assert.h"
 #include "common.h"
 #include "queue.h"
 #include "task.h"
@@ -55,7 +56,6 @@ static void test_capture_char(char c)
 	capture_buf[capture_size++] = c;
 }
 
-
 const char *test_get_captured_console(void)
 {
 	return (const char *)capture_buf;
@@ -190,6 +190,6 @@ void uart_init(void)
 	pthread_mutex_unlock(&mutex);
 #endif
 
-	stopped = 1;  /* Not transmitting yet */
+	stopped = 1; /* Not transmitting yet */
 	init_done = 1;
 }
diff --git a/chip/host/usb_pd_phy.c b/chip/host/usb_pd_phy.c
index ba81b986ad..aa5f022f3e 100644
--- a/chip/host/usb_pd_phy.c
+++ b/chip/host/usb_pd_phy.c
@@ -1,8 +1,9 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
 #include "crc.h"
@@ -37,9 +38,9 @@ static struct pd_physical {
 	int verified_idx;
 } pd_phy[CONFIG_USB_PD_PORT_MAX_COUNT];
 
-static const uint16_t enc4b5b[] = {
-	0x1E, 0x09, 0x14, 0x15, 0x0A, 0x0B, 0x0E, 0x0F, 0x12, 0x13, 0x16,
-	0x17, 0x1A, 0x1B, 0x1C, 0x1D};
+static const uint16_t enc4b5b[] = { 0x1E, 0x09, 0x14, 0x15, 0x0A, 0x0B,
+				    0x0E, 0x0F, 0x12, 0x13, 0x16, 0x17,
+				    0x1A, 0x1B, 0x1C, 0x1D };
 
 /* Test utilities */
 static void pd_test_reset_phy(int port)
@@ -216,7 +217,6 @@ int pd_test_tx_msg_verify_crc(int port)
 	return pd_test_tx_msg_verify_word(port, crc32_result());
 }
 
-
 /* Mock functions */
 
 void pd_init_dequeue(int port)
diff --git a/chip/ish/aontaskfw/ipapg.S b/chip/ish/aontaskfw/ipapg.S
index f0d3f8c554..305b9a0fb6 100755
--- a/chip/ish/aontaskfw/ipapg.S
+++ b/chip/ish/aontaskfw/ipapg.S
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/ish/aontaskfw/ish_aon_defs.h b/chip/ish/aontaskfw/ish_aon_defs.h
index 3cc3a491c0..0b3990100a 100644
--- a/chip/ish/aontaskfw/ish_aon_defs.h
+++ b/chip/ish/aontaskfw/ish_aon_defs.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/ish/aontaskfw/ish_aon_share.h b/chip/ish/aontaskfw/ish_aon_share.h
index 20b36ec2b2..b986150b73 100644
--- a/chip/ish/aontaskfw/ish_aon_share.h
+++ b/chip/ish/aontaskfw/ish_aon_share.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,13 +11,12 @@
 #include "power_mgt.h"
 
 /* magic ID for valid aontask image check */
-#define AON_MAGIC_ID			        0x544E4F41  /*"AONT"*/
+#define AON_MAGIC_ID 0x544E4F41 /*"AONT"*/
 
 /* aontask error code  */
-#define AON_SUCCESS				0
-#define AON_ERROR_NOT_SUPPORT_POWER_MODE	1
-#define AON_ERROR_DMA_FAILED			2
-
+#define AON_SUCCESS 0
+#define AON_ERROR_NOT_SUPPORT_POWER_MODE 1
+#define AON_ERROR_DMA_FAILED 2
 
 /* shared data structure between main FW and aontask */
 struct ish_aon_share {
diff --git a/chip/ish/aontaskfw/ish_aontask.c b/chip/ish/aontaskfw/ish_aontask.c
index e2106abf0a..d167f3f5df 100644
--- a/chip/ish/aontaskfw/ish_aontask.c
+++ b/chip/ish/aontaskfw/ish_aontask.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -64,9 +64,9 @@
  * AON_IDT_ENTRY_VEC_FIRST ~  AON_IDT_ENTRY_VEC_LAST
  */
 #ifdef CONFIG_ISH_NEW_PM
-#define AON_IDT_ENTRY_VEC_LAST		ISH_PMU_WAKEUP_VEC
+#define AON_IDT_ENTRY_VEC_LAST ISH_PMU_WAKEUP_VEC
 #else
-#define AON_IDT_ENTRY_VEC_FIRST		ISH_PMU_WAKEUP_VEC
+#define AON_IDT_ENTRY_VEC_FIRST ISH_PMU_WAKEUP_VEC
 #endif
 
 #ifdef CONFIG_ISH_PM_RESET_PREP
@@ -76,16 +76,16 @@
  * (if CONFIG_ISH_PM_RESET_PREP defined)
  */
 #ifdef CONFIG_ISH_NEW_PM
-#define AON_IDT_ENTRY_VEC_FIRST		ISH_RESET_PREP_VEC
+#define AON_IDT_ENTRY_VEC_FIRST ISH_RESET_PREP_VEC
 #else
-#define AON_IDT_ENTRY_VEC_LAST		ISH_RESET_PREP_VEC
+#define AON_IDT_ENTRY_VEC_LAST ISH_RESET_PREP_VEC
 #endif
 #else
 /* only need handle single PMU wakeup interrupt */
 #ifdef CONFIG_ISH_NEW_PM
-#define AON_IDT_ENTRY_VEC_FIRST		ISH_PMU_WAKEUP_VEC
+#define AON_IDT_ENTRY_VEC_FIRST ISH_PMU_WAKEUP_VEC
 #else
-#define AON_IDT_ENTRY_VEC_LAST		ISH_PMU_WAKEUP_VEC
+#define AON_IDT_ENTRY_VEC_LAST ISH_PMU_WAKEUP_VEC
 #endif
 #endif
 
@@ -101,7 +101,7 @@ static void pmu_wakeup_isr(void)
 	IOAPIC_EOI_REG = ISH_PMU_WAKEUP_VEC;
 	LAPIC_EOI_REG = 0x0;
 
-	__asm__ volatile ("iret;");
+	__asm__ volatile("iret;");
 
 	__builtin_unreachable();
 }
@@ -157,14 +157,15 @@ static void reset_prep_isr(void)
  *                     ---------------------------
  */
 
-static struct idt_entry aon_idt[AON_IDT_ENTRY_VEC_LAST -
-				AON_IDT_ENTRY_VEC_FIRST + 1];
+static struct idt_entry
+	aon_idt[AON_IDT_ENTRY_VEC_LAST - AON_IDT_ENTRY_VEC_FIRST + 1];
 
 static struct idt_header aon_idt_hdr = {
 
 	.limit = (sizeof(struct idt_entry) * (AON_IDT_ENTRY_VEC_LAST + 1)) - 1,
 	.entries = (struct idt_entry *)((uint32_t)&aon_idt -
-			(sizeof(struct idt_entry) * AON_IDT_ENTRY_VEC_FIRST))
+					(sizeof(struct idt_entry) *
+					 AON_IDT_ENTRY_VEC_FIRST))
 };
 
 /**
@@ -245,13 +246,9 @@ static ldt_entry aon_ldt[2] = {
 	 * limit: 0xFFFFFFFF
 	 * flag: 0x9B, Present = 1, DPL = 0, code segment
 	 */
-	{
-		.dword_lo = GEN_GDT_DESC_LO(0x0, 0xFFFFFFFF,
-				GDT_DESC_CODE_FLAGS),
+	{ .dword_lo = GEN_GDT_DESC_LO(0x0, 0xFFFFFFFF, GDT_DESC_CODE_FLAGS),
 
-		.dword_up = GEN_GDT_DESC_UP(0x0, 0xFFFFFFFF,
-				GDT_DESC_CODE_FLAGS)
-	},
+	  .dword_up = GEN_GDT_DESC_UP(0x0, 0xFFFFFFFF, GDT_DESC_CODE_FLAGS) },
 
 	/**
 	 * entry 1 for data segment
@@ -259,16 +256,11 @@ static ldt_entry aon_ldt[2] = {
 	 * limit: 0xFFFFFFFF
 	 * flag: 0x93, Present = 1, DPL = 0, data segment
 	 */
-	{
-		.dword_lo = GEN_GDT_DESC_LO(0x0, 0xFFFFFFFF,
-				GDT_DESC_DATA_FLAGS),
+	{ .dword_lo = GEN_GDT_DESC_LO(0x0, 0xFFFFFFFF, GDT_DESC_DATA_FLAGS),
 
-		.dword_up = GEN_GDT_DESC_UP(0x0, 0xFFFFFFFF,
-				GDT_DESC_DATA_FLAGS)
-	}
+	  .dword_up = GEN_GDT_DESC_UP(0x0, 0xFFFFFFFF, GDT_DESC_DATA_FLAGS) }
 };
 
-
 /* shared data structure between main FW and aon task */
 struct ish_aon_share aon_share = {
 	.magic_id = AON_MAGIC_ID,
@@ -282,15 +274,14 @@ struct ish_aon_share aon_share = {
 /* snowball structure */
 #if defined(CHIP_FAMILY_ISH3)
 /* on ISH3, reused ISH2PMC IPC message registers */
-#define SNOWBALL_BASE	IPC_ISH2PMC_MSG_BASE
+#define SNOWBALL_BASE IPC_ISH2PMC_MSG_BASE
 #else
 /* from ISH4, used reserved rom part of AON memory */
-#define SNOWBALL_BASE	(CONFIG_AON_PERSISTENT_BASE + 256)
+#define SNOWBALL_BASE (CONFIG_AON_PERSISTENT_BASE + 256)
 #endif
 
 struct snowball_struct *snowball = (void *)SNOWBALL_BASE;
 
-
 /* In IMR DDR, ISH FW image has a manifest header */
 #define ISH_FW_IMAGE_MANIFEST_HEADER_SIZE (0x1000)
 
@@ -324,30 +315,24 @@ static int store_main_fw(void)
 	uint64_t imr_fw_rw_addr;
 
 	imr_fw_addr = (((uint64_t)snowball->uma_base_hi << 32) +
-		       snowball->uma_base_lo +
-		       snowball->fw_offset +
+		       snowball->uma_base_lo + snowball->fw_offset +
 		       ISH_FW_IMAGE_MANIFEST_HEADER_SIZE);
 
-	imr_fw_rw_addr = (imr_fw_addr
-			  + aon_share.main_fw_rw_addr
-			  - CONFIG_RAM_BASE);
+	imr_fw_rw_addr =
+		(imr_fw_addr + aon_share.main_fw_rw_addr - CONFIG_RAM_BASE);
 
 	/* disable BCG (Block Clock Gating) for DMA, DMA can be accessed now */
 	disable_dma_bcg();
 
 	/* store main FW's read and write data region to IMR/UMA DDR */
-	ret = ish_dma_copy(
-		PAGING_CHAN,
-		imr_fw_rw_addr,
-		aon_share.main_fw_rw_addr,
-		aon_share.main_fw_rw_size,
-		SRAM_TO_UMA);
+	ret = ish_dma_copy(PAGING_CHAN, imr_fw_rw_addr,
+			   aon_share.main_fw_rw_addr, aon_share.main_fw_rw_size,
+			   SRAM_TO_UMA);
 
 	/* enable BCG for DMA, DMA can't be accessed now */
 	enable_dma_bcg();
 
 	if (ret != DMA_RC_OK) {
-
 		aon_share.last_error = AON_ERROR_DMA_FAILED;
 		aon_share.error_count++;
 
@@ -365,31 +350,24 @@ static int restore_main_fw(void)
 	uint64_t imr_fw_rw_addr;
 
 	imr_fw_addr = (((uint64_t)snowball->uma_base_hi << 32) +
-		       snowball->uma_base_lo +
-		       snowball->fw_offset +
+		       snowball->uma_base_lo + snowball->fw_offset +
 		       ISH_FW_IMAGE_MANIFEST_HEADER_SIZE);
 
-	imr_fw_ro_addr = (imr_fw_addr
-			  + aon_share.main_fw_ro_addr
-			  - CONFIG_RAM_BASE);
+	imr_fw_ro_addr =
+		(imr_fw_addr + aon_share.main_fw_ro_addr - CONFIG_RAM_BASE);
 
-	imr_fw_rw_addr = (imr_fw_addr
-			  + aon_share.main_fw_rw_addr
-			  - CONFIG_RAM_BASE);
+	imr_fw_rw_addr =
+		(imr_fw_addr + aon_share.main_fw_rw_addr - CONFIG_RAM_BASE);
 
 	/* disable BCG (Block Clock Gating) for DMA, DMA can be accessed now */
 	disable_dma_bcg();
 
 	/* restore main FW's read only code and data region from IMR/UMA DDR */
-	ret = ish_dma_copy(
-		PAGING_CHAN,
-		aon_share.main_fw_ro_addr,
-		imr_fw_ro_addr,
-		aon_share.main_fw_ro_size,
-		UMA_TO_SRAM);
+	ret = ish_dma_copy(PAGING_CHAN, aon_share.main_fw_ro_addr,
+			   imr_fw_ro_addr, aon_share.main_fw_ro_size,
+			   UMA_TO_SRAM);
 
 	if (ret != DMA_RC_OK) {
-
 		aon_share.last_error = AON_ERROR_DMA_FAILED;
 		aon_share.error_count++;
 
@@ -400,19 +378,14 @@ static int restore_main_fw(void)
 	}
 
 	/* restore main FW's read and write data region from IMR/UMA DDR */
-	ret = ish_dma_copy(
-			PAGING_CHAN,
-			aon_share.main_fw_rw_addr,
-			imr_fw_rw_addr,
-			aon_share.main_fw_rw_size,
-			UMA_TO_SRAM
-			);
+	ret = ish_dma_copy(PAGING_CHAN, aon_share.main_fw_rw_addr,
+			   imr_fw_rw_addr, aon_share.main_fw_rw_size,
+			   UMA_TO_SRAM);
 
 	/* enable BCG for DMA, DMA can't be accessed now */
 	enable_dma_bcg();
 
 	if (ret != DMA_RC_OK) {
-
 		aon_share.last_error = AON_ERROR_DMA_FAILED;
 		aon_share.error_count++;
 
@@ -424,10 +397,10 @@ static int restore_main_fw(void)
 
 #if defined(CHIP_FAMILY_ISH3)
 /* on ISH3, the last SRAM bank is reserved for AON use */
-#define SRAM_POWER_OFF_BANKS	(CONFIG_RAM_BANKS - 1)
+#define SRAM_POWER_OFF_BANKS (CONFIG_RAM_BANKS - 1)
 #elif defined(CHIP_FAMILY_ISH4) || defined(CHIP_FAMILY_ISH5)
 /* ISH4 and ISH5 have separate AON memory, can power off entire main SRAM */
-#define SRAM_POWER_OFF_BANKS	CONFIG_RAM_BANKS
+#define SRAM_POWER_OFF_BANKS CONFIG_RAM_BANKS
 #else
 #error "CHIP_FAMILY_ISH(3|4|5) must be defined"
 #endif
@@ -436,33 +409,33 @@ static int restore_main_fw(void)
  * check SRAM bank i power gated status in PMU_SRAM_PG_EN register
  * 1: power gated 0: not power gated
  */
-#define BANK_PG_STATUS(i)	(PMU_SRAM_PG_EN & (0x1 << (i)))
+#define BANK_PG_STATUS(i) (PMU_SRAM_PG_EN & (0x1 << (i)))
 
 /* enable power gate of a SRAM bank */
-#define BANK_PG_ENABLE(i)	(PMU_SRAM_PG_EN |= (0x1 << (i)))
+#define BANK_PG_ENABLE(i) (PMU_SRAM_PG_EN |= (0x1 << (i)))
 
 /* disable power gate of a SRAM bank */
-#define BANK_PG_DISABLE(i)	(PMU_SRAM_PG_EN &= ~(0x1 << (i)))
+#define BANK_PG_DISABLE(i) (PMU_SRAM_PG_EN &= ~(0x1 << (i)))
 
 /**
  * check SRAM bank i disabled status in ISH_SRAM_CTRL_CSFGR register
  * 1: disabled 0: enabled
  */
-#define BANK_DISABLE_STATUS(i)	(ISH_SRAM_CTRL_CSFGR & (0x1 << ((i) + 4)))
+#define BANK_DISABLE_STATUS(i) (ISH_SRAM_CTRL_CSFGR & (0x1 << ((i) + 4)))
 
 /* enable a SRAM bank in ISH_SRAM_CTRL_CSFGR register */
-#define BANK_ENABLE(i)		(ISH_SRAM_CTRL_CSFGR &= ~(0x1 << ((i) + 4)))
+#define BANK_ENABLE(i) (ISH_SRAM_CTRL_CSFGR &= ~(0x1 << ((i) + 4)))
 
 /* disable a SRAM bank in ISH_SRAM_CTRL_CSFGR register */
-#define BANK_DISABLE(i)		(ISH_SRAM_CTRL_CSFGR |= (0x1 << ((i) + 4)))
+#define BANK_DISABLE(i) (ISH_SRAM_CTRL_CSFGR |= (0x1 << ((i) + 4)))
 
 /* SRAM needs time to warm up after power on */
-#define SRAM_WARM_UP_DELAY_CNT		10
+#define SRAM_WARM_UP_DELAY_CNT 10
 
 /* SRAM needs time to enter retention mode */
-#define CYCLES_PER_US                  100
-#define SRAM_RETENTION_US_DELAY	       5
-#define SRAM_RETENTION_CYCLES_DELAY    (SRAM_RETENTION_US_DELAY * CYCLES_PER_US)
+#define CYCLES_PER_US 100
+#define SRAM_RETENTION_US_DELAY 5
+#define SRAM_RETENTION_CYCLES_DELAY (SRAM_RETENTION_US_DELAY * CYCLES_PER_US)
 
 static void sram_power(int on)
 {
@@ -485,10 +458,9 @@ static void sram_power(int on)
 		erase_cfg = (((bank_size - 4) >> 2) << 2) | 0x1;
 
 	for (i = 0; i < SRAM_POWER_OFF_BANKS; i++) {
-
-		if (on && (BANK_PG_STATUS(i) || (!IS_ENABLED(CONFIG_ISH_NEW_PM)
-						&& BANK_DISABLE_STATUS(i)))) {
-
+		if (on &&
+		    (BANK_PG_STATUS(i) || (!IS_ENABLED(CONFIG_ISH_NEW_PM) &&
+					   BANK_DISABLE_STATUS(i)))) {
 			/* power on and enable a bank */
 			BANK_PG_DISABLE(i);
 
@@ -519,13 +491,12 @@ static void sram_power(int on)
 		 * booting ISH
 		 */
 		ISH_SRAM_CTRL_INTR = 0xFFFFFFFF;
-
 	}
 }
 
 #define RTC_TICKS_IN_SECOND 32768
 
-static  __maybe_unused uint64_t get_rtc(void)
+static __maybe_unused uint64_t get_rtc(void)
 {
 	uint32_t lower;
 	uint32_t upper;
@@ -645,8 +616,7 @@ static void handle_d0i2(void)
 	}
 
 	/* set main SRAM into retention mode*/
-	PMU_LDO_CTRL = PMU_LDO_ENABLE_BIT
-		| PMU_LDO_RETENTION_BIT;
+	PMU_LDO_CTRL = PMU_LDO_ENABLE_BIT | PMU_LDO_RETENTION_BIT;
 
 	/* delay some cycles before halt */
 	delay(SRAM_RETENTION_CYCLES_DELAY);
@@ -670,7 +640,8 @@ static void handle_d0i2(void)
 
 	clear_vnnred_aoncg();
 
-	if (IS_ENABLED(CONFIG_ISH_NEW_PM) && (PMU_RST_PREP & PMU_RST_PREP_AVAIL))
+	if (IS_ENABLED(CONFIG_ISH_NEW_PM) &&
+	    (PMU_RST_PREP & PMU_RST_PREP_AVAIL))
 		handle_reset(ISH_PM_STATE_RESET_PREP);
 
 	/* set main SRAM intto normal mode */
@@ -728,7 +699,8 @@ static void handle_d0i3(void)
 
 	clear_vnnred_aoncg();
 
-	if (IS_ENABLED(CONFIG_ISH_NEW_PM) && (PMU_RST_PREP & PMU_RST_PREP_AVAIL))
+	if (IS_ENABLED(CONFIG_ISH_NEW_PM) &&
+	    (PMU_RST_PREP & PMU_RST_PREP_AVAIL))
 		handle_reset(ISH_PM_STATE_RESET_PREP);
 
 	/* power on main SRAM */
@@ -809,7 +781,6 @@ static void handle_reset(enum ish_pm_state pm_state)
 		 */
 		if (IS_ENABLED(CONFIG_ISH_NEW_PM) ||
 		    (IPC_ISH_RMP2 & DMA_ENABLED_MASK)) {
-
 			/* clear ISH2HOST doorbell register */
 			*IPC_ISH2HOST_DOORBELL_ADDR = 0;
 
@@ -834,7 +805,6 @@ static void handle_reset(enum ish_pm_state pm_state)
 
 		ish_mia_halt();
 	}
-
 }
 
 static void handle_unknown_state(void)
@@ -847,22 +817,21 @@ static void handle_unknown_state(void)
 
 void ish_aon_main(void)
 {
-
 	/* set PMU wakeup interrupt gate using LDT code segment selector(0x4) */
 	if (IS_ENABLED(CONFIG_ISH_NEW_PM)) {
-		aon_idt[AON_IDT_ENTRY_VEC_LAST -
-			AON_IDT_ENTRY_VEC_FIRST].dword_lo =
+		aon_idt[AON_IDT_ENTRY_VEC_LAST - AON_IDT_ENTRY_VEC_FIRST]
+			.dword_lo =
 			GEN_IDT_DESC_LO(&pmu_wakeup_isr, 0x4, IDT_DESC_FLAGS);
 
-		aon_idt[AON_IDT_ENTRY_VEC_LAST -
-			AON_IDT_ENTRY_VEC_FIRST].dword_up =
+		aon_idt[AON_IDT_ENTRY_VEC_LAST - AON_IDT_ENTRY_VEC_FIRST]
+			.dword_up =
 			GEN_IDT_DESC_UP(&pmu_wakeup_isr, 0x4, IDT_DESC_FLAGS);
 	} else {
-		aon_idt[0].dword_lo = GEN_IDT_DESC_LO(&pmu_wakeup_isr, 0x4,
-			IDT_DESC_FLAGS);
+		aon_idt[0].dword_lo =
+			GEN_IDT_DESC_LO(&pmu_wakeup_isr, 0x4, IDT_DESC_FLAGS);
 
-		aon_idt[0].dword_up = GEN_IDT_DESC_UP(&pmu_wakeup_isr, 0x4,
-			IDT_DESC_FLAGS);
+		aon_idt[0].dword_up =
+			GEN_IDT_DESC_UP(&pmu_wakeup_isr, 0x4, IDT_DESC_FLAGS);
 	}
 
 	if (IS_ENABLED(CONFIG_ISH_PM_RESET_PREP)) {
@@ -871,39 +840,34 @@ void ish_aon_main(void)
 		 * selector(0x4)
 		 */
 		if (IS_ENABLED(CONFIG_ISH_NEW_PM)) {
-			aon_idt[0].dword_lo = GEN_IDT_DESC_LO(&reset_prep_isr,
-				0x4, IDT_DESC_FLAGS);
+			aon_idt[0].dword_lo = GEN_IDT_DESC_LO(
+				&reset_prep_isr, 0x4, IDT_DESC_FLAGS);
 
-			aon_idt[0].dword_up = GEN_IDT_DESC_UP(&reset_prep_isr,
-				0x4, IDT_DESC_FLAGS);
+			aon_idt[0].dword_up = GEN_IDT_DESC_UP(
+				&reset_prep_isr, 0x4, IDT_DESC_FLAGS);
 		} else {
-			aon_idt[AON_IDT_ENTRY_VEC_LAST -
-				AON_IDT_ENTRY_VEC_FIRST].dword_lo =
-				GEN_IDT_DESC_LO(&reset_prep_isr, 0x4,
-				IDT_DESC_FLAGS);
-
-			aon_idt[AON_IDT_ENTRY_VEC_LAST -
-				AON_IDT_ENTRY_VEC_FIRST].dword_up =
-				GEN_IDT_DESC_UP(&reset_prep_isr, 0x4,
-				IDT_DESC_FLAGS);
+			aon_idt[AON_IDT_ENTRY_VEC_LAST - AON_IDT_ENTRY_VEC_FIRST]
+				.dword_lo = GEN_IDT_DESC_LO(
+				&reset_prep_isr, 0x4, IDT_DESC_FLAGS);
+
+			aon_idt[AON_IDT_ENTRY_VEC_LAST - AON_IDT_ENTRY_VEC_FIRST]
+				.dword_up = GEN_IDT_DESC_UP(
+				&reset_prep_isr, 0x4, IDT_DESC_FLAGS);
 		}
 	}
 
 	while (1) {
-
 		/**
 		 *  will start to run from here when switched to aontask from
 		 *  the second time
 		 */
 
 		/* save main FW's IDT and load aontask's IDT */
-		__asm__ volatile (
-				"sidtl %0;\n"
-				"lidtl %1;\n"
-				:
-				: "m" (aon_share.main_fw_idt_hdr),
-				  "m" (aon_idt_hdr)
-				);
+		__asm__ volatile("sidtl %0;\n"
+				 "lidtl %1;\n"
+				 :
+				 : "m"(aon_share.main_fw_idt_hdr),
+				   "m"(aon_idt_hdr));
 
 		aon_share.last_error = AON_SUCCESS;
 
@@ -934,11 +898,9 @@ void ish_aon_main(void)
 		}
 
 		/* restore main FW's IDT and switch back to main FW */
-		__asm__ volatile(
-				"lidtl %0;\n"
-				:
-				: "m" (aon_share.main_fw_idt_hdr)
-				);
+		__asm__ volatile("lidtl %0;\n"
+				 :
+				 : "m"(aon_share.main_fw_idt_hdr));
 
 		if (IS_ENABLED(CONFIG_ISH_IPAPG) && aon_share.pg_exit) {
 			mainfw_gdt.entries[tr / sizeof(struct gdt_entry)]
@@ -946,6 +908,6 @@ void ish_aon_main(void)
 			pg_exit_restore_ctx();
 		}
 
-		__asm__ volatile ("iret;");
+		__asm__ volatile("iret;");
 	}
 }
diff --git a/chip/ish/aontaskfw/ish_aontask.lds.S b/chip/ish/aontaskfw/ish_aontask.lds.S
index ca5f54f705..306beef5e9 100644
--- a/chip/ish/aontaskfw/ish_aontask.lds.S
+++ b/chip/ish/aontaskfw/ish_aontask.lds.S
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/ish/build.mk b/chip/ish/build.mk
index 8072a20791..3777f9f4ce 100644
--- a/chip/ish/build.mk
+++ b/chip/ish/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/chip/ish/clock.c b/chip/ish/clock.c
index ac818f5733..e46c4278b7 100644
--- a/chip/ish/clock.c
+++ b/chip/ish/clock.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,8 +12,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
-
+#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args)
 
 void clock_init(void)
 {
diff --git a/chip/ish/config_chip.h b/chip/ish/config_chip.h
index 4c884d00cc..b76c302f4e 100644
--- a/chip/ish/config_chip.h
+++ b/chip/ish/config_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,18 +15,18 @@
 #endif
 
 /* Number of IRQ vectors on the ISH */
-#define CONFIG_IRQ_COUNT	(VEC_TO_IRQ(255) + 1)
+#define CONFIG_IRQ_COUNT (VEC_TO_IRQ(255) + 1)
 
 /* Use a bigger console output buffer */
 #undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE	2048
+#define CONFIG_UART_TX_BUF_SIZE 2048
 
 /* Interval between HOOK_TICK notifications */
-#define HOOK_TICK_INTERVAL_MS	250
-#define HOOK_TICK_INTERVAL	(HOOK_TICK_INTERVAL_MS * MSEC)
+#define HOOK_TICK_INTERVAL_MS 250
+#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC)
 
 /* Maximum number of deferrable functions */
-#define DEFERRABLE_MAX_COUNT	8
+#define DEFERRABLE_MAX_COUNT 8
 
 /* this macro causes 'pause' and reduces loop counts inside loop. */
 #define CPU_RELAX() asm volatile("rep; nop" ::: "memory")
@@ -36,49 +36,48 @@
 /*****************************************************************************/
 
 #ifdef CHIP_VARIANT_ISH5P4
-#define CONFIG_RAM_BASE		0xFF200000
+#define CONFIG_RAM_BASE 0xFF200000
 #else
-#define CONFIG_RAM_BASE		0xFF000000
+#define CONFIG_RAM_BASE 0xFF000000
 #endif
-#define CONFIG_RAM_SIZE		0x000A0000
+#define CONFIG_RAM_SIZE 0x000A0000
 #ifdef CHIP_VARIANT_ISH5P4
-#define CONFIG_RAM_BANK_SIZE	0x00010000
+#define CONFIG_RAM_BANK_SIZE 0x00010000
 #else
-#define CONFIG_RAM_BANK_SIZE	0x00008000
+#define CONFIG_RAM_BANK_SIZE 0x00008000
 #endif
 
 #if defined(CHIP_FAMILY_ISH3)
 /* On ISH3, there is no separate AON memory; use last 4KB of SRAM */
-#define CONFIG_AON_RAM_BASE		0xFF09F000
-#define CONFIG_AON_RAM_SIZE		0x00001000
+#define CONFIG_AON_RAM_BASE 0xFF09F000
+#define CONFIG_AON_RAM_SIZE 0x00001000
 #elif defined(CHIP_FAMILY_ISH4)
-#define CONFIG_AON_RAM_BASE		0xFF800000
-#define CONFIG_AON_RAM_SIZE		0x00001000
+#define CONFIG_AON_RAM_BASE 0xFF800000
+#define CONFIG_AON_RAM_SIZE 0x00001000
 #elif defined(CHIP_FAMILY_ISH5)
-#define CONFIG_AON_RAM_BASE		0xFF800000
-#define CONFIG_AON_RAM_SIZE		0x00002000
+#define CONFIG_AON_RAM_BASE 0xFF800000
+#define CONFIG_AON_RAM_SIZE 0x00002000
 #else
 #error "CHIP_FAMILY_ISH(3|4|5) must be defined"
 #endif
 
 /* The end of the AON memory is reserved for read-only use */
-#define CONFIG_AON_PERSISTENT_SIZE	0x180
-#define CONFIG_AON_PERSISTENT_BASE	(CONFIG_AON_RAM_BASE	\
-					 + CONFIG_AON_RAM_SIZE	\
-					 - CONFIG_AON_PERSISTENT_SIZE)
+#define CONFIG_AON_PERSISTENT_SIZE 0x180
+#define CONFIG_AON_PERSISTENT_BASE \
+	(CONFIG_AON_RAM_BASE + CONFIG_AON_RAM_SIZE - CONFIG_AON_PERSISTENT_SIZE)
 
 /* Store persistent panic data in AON memory. */
-#define CONFIG_PANIC_DATA_BASE		(&(ish_persistent_data.panic_data))
+#define CONFIG_PANIC_DATA_BASE (&(ish_persistent_data.panic_data))
 
 /* System stack size */
-#define CONFIG_STACK_SIZE		1024
+#define CONFIG_STACK_SIZE 1024
 
 /* non-standard task stack sizes */
-#define IDLE_TASK_STACK_SIZE		640
-#define LARGER_TASK_STACK_SIZE		1024
-#define HUGE_TASK_STACK_SIZE		2048
+#define IDLE_TASK_STACK_SIZE 640
+#define LARGER_TASK_STACK_SIZE 1024
+#define HUGE_TASK_STACK_SIZE 2048
 /* Default task stack size */
-#define TASK_STACK_SIZE			640
+#define TASK_STACK_SIZE 640
 
 /****************************************************************************/
 /* Define our flash layout. */
@@ -87,13 +86,13 @@
  */
 
 /* Protect bank size 4K bytes */
-#define CONFIG_FLASH_BANK_SIZE		0x00001000
+#define CONFIG_FLASH_BANK_SIZE 0x00001000
 /* Sector erase size 4K bytes */
-#define CONFIG_FLASH_ERASE_SIZE		0x00000000
+#define CONFIG_FLASH_ERASE_SIZE 0x00000000
 /* Minimum write size */
-#define CONFIG_FLASH_WRITE_SIZE		0x00000000
+#define CONFIG_FLASH_WRITE_SIZE 0x00000000
 /* Program memory base address */
-#define CONFIG_PROGRAM_MEMORY_BASE	0x00100000
+#define CONFIG_PROGRAM_MEMORY_BASE 0x00100000
 
 #include "config_flash_layout.h"
 
@@ -101,16 +100,16 @@
 /*                        Watchdog Timer Configuration                       */
 /*****************************************************************************/
 #if defined(CHIP_FAMILY_ISH3) || defined(CHIP_FAMILY_ISH5)
-#define WDT_CLOCK_HZ		(120000000) /* 120 MHz */
+#define WDT_CLOCK_HZ (120000000) /* 120 MHz */
 #elif defined(CHIP_FAMILY_ISH4)
-#define WDT_CLOCK_HZ		(100000000) /* 100 MHz */
+#define WDT_CLOCK_HZ (100000000) /* 100 MHz */
 #else
 #error "CHIP_FAMILY_ISH(3|4|5) must be defined"
 #endif
 
 /* Provide WDT vec number to Minute-IA core implementation */
 #undef CONFIG_MIA_WDT_VEC
-#define CONFIG_MIA_WDT_VEC	ISH_WDT_VEC
+#define CONFIG_MIA_WDT_VEC ISH_WDT_VEC
 
 /****************************************************************************/
 /* Customize the build */
@@ -133,4 +132,4 @@
 #define CONFIG_ISH_CLEAR_FABRIC_ERRORS
 #endif
 
-#endif  /* __CROS_EC_CONFIG_CHIP_H */
+#endif /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/chip/ish/config_flash_layout.h b/chip/ish/config_flash_layout.h
index 9a6cc4f28b..4e4b7ad90b 100644
--- a/chip/ish/config_flash_layout.h
+++ b/chip/ish/config_flash_layout.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,14 +8,14 @@
 
 /* Mem-mapped, No external SPI for ISH */
 #undef CONFIG_EXTERNAL_STORAGE
-#define  CONFIG_MAPPED_STORAGE
-#undef  CONFIG_FLASH_PSTATE
+#define CONFIG_MAPPED_STORAGE
+#undef CONFIG_FLASH_PSTATE
 #undef CONFIG_SPI_FLASH
 
 #ifdef CHIP_VARIANT_ISH5P4
-#define CONFIG_ISH_BOOT_START		0xFF200000
+#define CONFIG_ISH_BOOT_START 0xFF200000
 #else
-#define CONFIG_ISH_BOOT_START		0xFF000000
+#define CONFIG_ISH_BOOT_START 0xFF000000
 #endif
 
 /*****************************************************************************/
@@ -24,40 +24,37 @@
  * turn off SPI and flash, making these unnecessary.
  */
 
-#define CONFIG_MAPPED_STORAGE_BASE	0x0
+#define CONFIG_MAPPED_STORAGE_BASE 0x0
 
-#define CONFIG_EC_PROTECTED_STORAGE_OFF  (CONFIG_FLASH_SIZE_BYTES - 0x20000)
+#define CONFIG_EC_PROTECTED_STORAGE_OFF (CONFIG_FLASH_SIZE_BYTES - 0x20000)
 #define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x20000
-#define CONFIG_EC_WRITABLE_STORAGE_OFF   (CONFIG_FLASH_SIZE_BYTES - 0x40000)
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE  0x20000
+#define CONFIG_EC_WRITABLE_STORAGE_OFF (CONFIG_FLASH_SIZE_BYTES - 0x40000)
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x20000
 
 /* Unused for ISH - loader is external to ISH FW */
-#define CONFIG_LOADER_MEM_OFF		0
-#define CONFIG_LOADER_SIZE		0xC00
-
+#define CONFIG_LOADER_MEM_OFF 0
+#define CONFIG_LOADER_SIZE 0xC00
 
 /* RO/RW images - not relevant for ISH
  */
-#define CONFIG_RO_MEM_OFF		(CONFIG_LOADER_MEM_OFF + \
-					CONFIG_LOADER_SIZE)
-#define CONFIG_RO_SIZE			(97 * 1024)
-#define CONFIG_RW_MEM_OFF		CONFIG_RO_MEM_OFF
-#define CONFIG_RW_SIZE			CONFIG_RO_SIZE
+#define CONFIG_RO_MEM_OFF (CONFIG_LOADER_MEM_OFF + CONFIG_LOADER_SIZE)
+#define CONFIG_RO_SIZE (97 * 1024)
+#define CONFIG_RW_MEM_OFF CONFIG_RO_MEM_OFF
+#define CONFIG_RW_SIZE CONFIG_RO_SIZE
 
 /*****************************************************************************/
 
 /* Not relevant for ISH */
-#define CONFIG_BOOT_HEADER_STORAGE_OFF	0
-#define CONFIG_BOOT_HEADER_STORAGE_SIZE	0x240
+#define CONFIG_BOOT_HEADER_STORAGE_OFF 0
+#define CONFIG_BOOT_HEADER_STORAGE_SIZE 0x240
 
-#define CONFIG_LOADER_STORAGE_OFF	(CONFIG_BOOT_HEADER_STORAGE_OFF + \
-					CONFIG_BOOT_HEADER_STORAGE_SIZE)
+#define CONFIG_LOADER_STORAGE_OFF \
+	(CONFIG_BOOT_HEADER_STORAGE_OFF + CONFIG_BOOT_HEADER_STORAGE_SIZE)
 
 /* RO image immediately follows the loader image */
-#define CONFIG_RO_STORAGE_OFF		(CONFIG_LOADER_STORAGE_OFF + \
-					CONFIG_LOADER_SIZE)
+#define CONFIG_RO_STORAGE_OFF (CONFIG_LOADER_STORAGE_OFF + CONFIG_LOADER_SIZE)
 
 /* RW image starts at the beginning of SPI */
-#define CONFIG_RW_STORAGE_OFF		0
+#define CONFIG_RW_STORAGE_OFF 0
 
 #endif /* __CROS_EC_CONFIG_FLASH_LAYOUT_H */
diff --git a/chip/ish/dma.c b/chip/ish/dma.c
index b9744fd234..48a27a0463 100644
--- a/chip/ish/dma.c
+++ b/chip/ish/dma.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -112,8 +112,8 @@ int ish_dma_copy(uint32_t chan, uint32_t dst, uint32_t src, uint32_t length,
 	mode |= NON_SNOOP;
 	MISC_DMA_CTL_REG(chan) = mode; /* Set transfer direction */
 
-	DMA_CFG_REG = DMA_ENABLE;  /* Enable DMA module */
-	DMA_LLP(chan_reg) = 0;     /* Linked lists are not used */
+	DMA_CFG_REG = DMA_ENABLE; /* Enable DMA module */
+	DMA_LLP(chan_reg) = 0; /* Linked lists are not used */
 	DMA_CTL_LOW(chan_reg) =
 		0 /* Set transfer parameters */ |
 		(DMA_CTL_TT_FC_M2M_DMAC << DMA_CTL_TT_FC_SHIFT) |
@@ -126,24 +126,27 @@ int ish_dma_copy(uint32_t chan, uint32_t dst, uint32_t src, uint32_t length,
 
 	interrupt_unlock(eflags);
 	while (length) {
-		chunk = (length > DMA_MAX_BLOCK_SIZE) ? DMA_MAX_BLOCK_SIZE
-						      : length;
+		chunk = (length > DMA_MAX_BLOCK_SIZE) ? DMA_MAX_BLOCK_SIZE :
+							length;
 
 		if (rc != DMA_RC_OK)
 			break;
 
 		eflags = interrupt_lock();
 		MISC_CHID_CFG_REG = chan; /* Set channel to configure */
-		DMA_CTL_HIGH(chan_reg) =
-			chunk;		 /* Set number of bytes to transfer */
+		DMA_CTL_HIGH(chan_reg) = chunk; /* Set number of bytes to
+						   transfer */
 		DMA_DAR(chan_reg) = dst; /* Destination address */
 		DMA_SAR(chan_reg) = src; /* Source address */
 		DMA_EN_REG = DMA_CH_EN_BIT(chan) |
-			     DMA_CH_EN_WE_BIT(chan); /* Enable the channel */
+			     DMA_CH_EN_WE_BIT(chan); /* Enable
+							the
+							channel
+						      */
 		interrupt_unlock(eflags);
 
-		rc = ish_wait_for_dma_done(
-			chan); /* Wait for trans completion */
+		rc = ish_wait_for_dma_done(chan); /* Wait for trans completion
+						   */
 
 		dst += chunk;
 		src += chunk;
diff --git a/chip/ish/flash.c b/chip/ish/flash.c
index 2a1b9c0793..c9c4a132d9 100644
--- a/chip/ish/flash.c
+++ b/chip/ish/flash.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,6 @@
 #include "common.h"
 #include "flash.h"
 
-
 /**
  * Initialize the module.
  *
diff --git a/chip/ish/gpio.c b/chip/ish/gpio.c
index 6c7a27e1e7..287e7a375b 100644
--- a/chip/ish/gpio.c
+++ b/chip/ish/gpio.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,7 +24,7 @@ test_mockable int gpio_get_level(enum gpio_signal signal)
 	if (g->port == UNIMPLEMENTED_GPIO_BANK)
 		return 0;
 
-	return  !!(ISH_GPIO_GPLR & g->mask);
+	return !!(ISH_GPIO_GPLR & g->mask);
 }
 
 void gpio_set_level(enum gpio_signal signal, int value)
@@ -55,8 +55,8 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
 	}
 
 	/* ISH 3 can't support both rising and falling edge */
-	if (IS_ENABLED(CHIP_FAMILY_ISH3) &&
-	    (flags & GPIO_INT_F_RISING) && (flags & GPIO_INT_F_FALLING)) {
+	if (IS_ENABLED(CHIP_FAMILY_ISH3) && (flags & GPIO_INT_F_RISING) &&
+	    (flags & GPIO_INT_F_FALLING)) {
 		ccprintf("\n\nISH 2/3 does not support both rising & falling "
 			 "edge for %d 0x%02x\n\n",
 			 port, mask);
@@ -65,7 +65,7 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
 	/* GPSR/GPCR Output high/low */
 	if (flags & GPIO_HIGH) /* Output high */
 		ISH_GPIO_GPSR |= mask;
-	else if (flags & GPIO_LOW)  /* output low */
+	else if (flags & GPIO_LOW) /* output low */
 		ISH_GPIO_GPCR |= mask;
 
 	/* GPDR pin direction 1 = output, 0 = input*/
@@ -123,7 +123,6 @@ void gpio_pre_init(void)
 	const struct gpio_info *g = gpio_list;
 
 	for (i = 0; i < GPIO_COUNT; i++, g++) {
-
 		flags = g->flags;
 
 		if (flags & GPIO_DEFAULT)
diff --git a/chip/ish/hbm.h b/chip/ish/hbm.h
index edfb587d21..d666f748c8 100644
--- a/chip/ish/hbm.h
+++ b/chip/ish/hbm.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,65 +11,64 @@
 
 #include "heci_client.h"
 
-#define HBM_MAJOR_VERSION			1
+#define HBM_MAJOR_VERSION 1
 #ifdef HECI_ENABLE_DMA
-#define HBM_MINOR_VERSION			2
+#define HBM_MINOR_VERSION 2
 #else
-#define HBM_MINOR_VERSION			0
+#define HBM_MINOR_VERSION 0
 #endif
 
 #define __packed __attribute__((packed))
 
-#define HECI_MSG_REPONSE_FLAG			0x80
+#define HECI_MSG_REPONSE_FLAG 0x80
 
 enum HECI_BUS_MSG {
 	/* requests */
-	HECI_BUS_MSG_VERSION_REQ		= 1,
-	HECI_BUS_MSG_HOST_STOP_REQ		= 2,
-	HECI_BUS_MSG_ME_STOP_REQ		= 3,
-	HECI_BUS_MSG_HOST_ENUM_REQ		= 4,
-	HECI_BUS_MSG_HOST_CLIENT_PROP_REQ	= 5,
-	HECI_BUS_MSG_CLIENT_CONNECT_REQ		= 6,
-	HECI_BUS_MSG_CLIENT_DISCONNECT_REQ	= 7,
-	HECI_BUS_MSG_FLOW_CONTROL		= 8,
-	HECI_BUS_MSG_RESET_REQ			= 9,
-	HECI_BUS_MSG_ADD_CLIENT_REQ		= 0x0A,
-	HECI_BUS_MSG_DMA_REQ			= 0x10,
-	HECI_BUS_MSG_DMA_ALLOC_NOTIFY		= 0x11,
-	HECI_BUS_MSG_DMA_XFER_REQ		= 0x12,
+	HECI_BUS_MSG_VERSION_REQ = 1,
+	HECI_BUS_MSG_HOST_STOP_REQ = 2,
+	HECI_BUS_MSG_ME_STOP_REQ = 3,
+	HECI_BUS_MSG_HOST_ENUM_REQ = 4,
+	HECI_BUS_MSG_HOST_CLIENT_PROP_REQ = 5,
+	HECI_BUS_MSG_CLIENT_CONNECT_REQ = 6,
+	HECI_BUS_MSG_CLIENT_DISCONNECT_REQ = 7,
+	HECI_BUS_MSG_FLOW_CONTROL = 8,
+	HECI_BUS_MSG_RESET_REQ = 9,
+	HECI_BUS_MSG_ADD_CLIENT_REQ = 0x0A,
+	HECI_BUS_MSG_DMA_REQ = 0x10,
+	HECI_BUS_MSG_DMA_ALLOC_NOTIFY = 0x11,
+	HECI_BUS_MSG_DMA_XFER_REQ = 0x12,
 
 	/* responses */
-	HECI_BUS_MSG_VERSION_RESP		=
+	HECI_BUS_MSG_VERSION_RESP =
 		(HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_VERSION_REQ),
-	HECI_BUS_MSG_HOST_STOP_RESP		=
+	HECI_BUS_MSG_HOST_STOP_RESP =
 		(HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_HOST_STOP_REQ),
-	HECI_BUS_MSG_HOST_ENUM_RESP		=
+	HECI_BUS_MSG_HOST_ENUM_RESP =
 		(HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_HOST_ENUM_REQ),
-	HECI_BUS_MSG_HOST_CLIENT_PROP_RESP	=
+	HECI_BUS_MSG_HOST_CLIENT_PROP_RESP =
 		(HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_HOST_CLIENT_PROP_REQ),
-	HECI_BUS_MSG_CLIENT_CONNECT_RESP	=
+	HECI_BUS_MSG_CLIENT_CONNECT_RESP =
 		(HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_CLIENT_CONNECT_REQ),
-	HECI_BUS_MSG_CLIENT_DISCONNECT_RESP	= 
+	HECI_BUS_MSG_CLIENT_DISCONNECT_RESP =
 		(HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_CLIENT_DISCONNECT_REQ),
-	HECI_BUS_MSG_RESET_RESP			=
+	HECI_BUS_MSG_RESET_RESP =
 		(HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_RESET_REQ),
-	HECI_BUS_MSG_ADD_CLIENT_RESP		=
+	HECI_BUS_MSG_ADD_CLIENT_RESP =
 		(HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_ADD_CLIENT_REQ),
-	HECI_BUS_MSG_DMA_RESP			=
-		(HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_DMA_REQ),
-	HECI_BUS_MSG_DMA_ALLOC_RESP		=
+	HECI_BUS_MSG_DMA_RESP = (HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_DMA_REQ),
+	HECI_BUS_MSG_DMA_ALLOC_RESP =
 		(HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_DMA_ALLOC_NOTIFY),
-	HECI_BUS_MSG_DMA_XFER_RESP		=
+	HECI_BUS_MSG_DMA_XFER_RESP =
 		(HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_DMA_XFER_REQ)
 };
 
 enum {
-	HECI_CONNECT_STATUS_SUCCESS           = 0,
-	HECI_CONNECT_STATUS_CLIENT_NOT_FOUND  = 1,
-	HECI_CONNECT_STATUS_ALREADY_EXISTS    = 2,
-	HECI_CONNECT_STATUS_REJECTED          = 3,
+	HECI_CONNECT_STATUS_SUCCESS = 0,
+	HECI_CONNECT_STATUS_CLIENT_NOT_FOUND = 1,
+	HECI_CONNECT_STATUS_ALREADY_EXISTS = 2,
+	HECI_CONNECT_STATUS_REJECTED = 3,
 	HECI_CONNECT_STATUS_INVALID_PARAMETER = 4,
-	HECI_CONNECT_STATUS_INACTIVE_CLIENT   = 5,
+	HECI_CONNECT_STATUS_INACTIVE_CLIENT = 5,
 };
 
 struct hbm_version {
@@ -101,14 +100,14 @@ struct hbm_client_prop_req {
 	uint8_t reserved[2];
 } __packed;
 
-#define CLIENT_DMA_ENABLE	0x80
+#define CLIENT_DMA_ENABLE 0x80
 
 struct hbm_client_properties {
 	struct heci_guid protocol_name; /* heci client protocol ID */
-	uint8_t protocol_version;	/* protocol version */
+	uint8_t protocol_version; /* protocol version */
 	/* max connection from host to client. currently only 1 is allowed */
 	uint8_t max_number_of_connections;
-	uint8_t fixed_address;	/* not yet supported */
+	uint8_t fixed_address; /* not yet supported */
 	uint8_t single_recv_buf; /* not yet supported */
 	uint32_t max_msg_length; /* max payload size */
 	/* not yet supported. [7] enable/disable, [6:0] dma length */
@@ -168,13 +167,13 @@ struct hbm_host_stop_res {
 struct hbm_h2i {
 	uint8_t cmd;
 	union {
-		struct hbm_version_req			ver_req;
-		struct hbm_enum_req			enum_req;
-		struct hbm_client_prop_req		client_prop_req;
-		struct hbm_client_connect_req		client_connect_req;
-		struct hbm_flow_control			flow_ctrl;
-		struct hbm_client_disconnect_req	client_disconnect_req;
-		struct hbm_host_stop_req		host_stop_req;
+		struct hbm_version_req ver_req;
+		struct hbm_enum_req enum_req;
+		struct hbm_client_prop_req client_prop_req;
+		struct hbm_client_connect_req client_connect_req;
+		struct hbm_flow_control flow_ctrl;
+		struct hbm_client_disconnect_req client_disconnect_req;
+		struct hbm_host_stop_req host_stop_req;
 	} data;
 } __packed;
 
@@ -182,13 +181,13 @@ struct hbm_h2i {
 struct hbm_i2h {
 	uint8_t cmd;
 	union {
-		struct hbm_version_res			ver_res;
-		struct hbm_enum_res			enum_res;
-		struct hbm_client_prop_res		client_prop_res;
-		struct hbm_client_connect_res		client_connect_res;
-		struct hbm_flow_control			flow_ctrl;
-		struct hbm_client_disconnect_res	client_disconnect_res;
-		struct hbm_host_stop_res		host_stop_res;
+		struct hbm_version_res ver_res;
+		struct hbm_enum_res enum_res;
+		struct hbm_client_prop_res client_prop_res;
+		struct hbm_client_connect_res client_connect_res;
+		struct hbm_flow_control flow_ctrl;
+		struct hbm_client_disconnect_res client_disconnect_res;
+		struct hbm_host_stop_res host_stop_res;
 	} data;
 } __packed;
 
diff --git a/chip/ish/heci.c b/chip/ish/heci.c
index 4a9bc9551b..6f99a486e7 100644
--- a/chip/ish/heci.c
+++ b/chip/ish/heci.c
@@ -1,9 +1,10 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "atomic.h"
+#include "builtin/assert.h"
 #include "compile_time_macros.h"
 #include "console.h"
 #include "hbm.h"
@@ -15,19 +16,19 @@
 #include "util.h"
 
 #define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_LPC, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_LPC, format, ##args)
 
 struct heci_header {
 	uint8_t fw_addr;
 	uint8_t host_addr;
 	uint16_t length; /* [8:0] length, [14:9] reserved, [15] msg_complete */
 } __packed;
-#define HECI_MSG_CMPL_SHIFT		15
-#define HECI_MSG_LENGTH_MASK		0x01FF
-#define HECI_MSG_LENGTH(length)		((length) & HECI_MSG_LENGTH_MASK)
+#define HECI_MSG_CMPL_SHIFT 15
+#define HECI_MSG_LENGTH_MASK 0x01FF
+#define HECI_MSG_LENGTH(length) ((length)&HECI_MSG_LENGTH_MASK)
 #define HECI_MSG_IS_COMPLETED(length) \
-				(!!((length) & (0x01 << HECI_MSG_CMPL_SHIFT)))
+	(!!((length) & (0x01 << HECI_MSG_CMPL_SHIFT)))
 
 BUILD_ASSERT(HECI_IPC_PAYLOAD_SIZE ==
 	     (IPC_MAX_PAYLOAD_SIZE - sizeof(struct heci_header)));
@@ -38,26 +39,26 @@ struct heci_msg {
 } __packed;
 
 /* HECI addresses */
-#define HECI_HBM_ADDRESS		0	/* HECI Bus Message */
-#define HECI_DYN_CLIENT_ADDR_START	0x20	/* Dynamic client start addr */
+#define HECI_HBM_ADDRESS 0 /* HECI Bus Message */
+#define HECI_DYN_CLIENT_ADDR_START 0x20 /* Dynamic client start addr */
 
 /* A fw client has the same value for both handle and fw address */
-#define TO_FW_ADDR(handle)		((uintptr_t)(handle))
-#define TO_HECI_HANDLE(fw_addr)		((heci_handle_t)(uintptr_t)(fw_addr))
+#define TO_FW_ADDR(handle) ((uintptr_t)(handle))
+#define TO_HECI_HANDLE(fw_addr) ((heci_handle_t)(uintptr_t)(fw_addr))
 /* convert client fw address to client context index */
-#define TO_CLIENT_CTX_IDX(fw_addr)	((fw_addr) - HECI_DYN_CLIENT_ADDR_START)
+#define TO_CLIENT_CTX_IDX(fw_addr) ((fw_addr)-HECI_DYN_CLIENT_ADDR_START)
 
 /* should be less than HECI_INVALID_HANDLE - 1 */
 BUILD_ASSERT(HECI_MAX_NUM_OF_CLIENTS < 0x0FE);
 
 struct heci_client_connect {
-	uint8_t is_connected;	/* client is connected to host */
-	uint8_t host_addr;	/* connected host address */
+	uint8_t is_connected; /* client is connected to host */
+	uint8_t host_addr; /* connected host address */
 
 	/* receiving message */
 	uint8_t ignore_rx_msg;
-	uint8_t	rx_msg[HECI_MAX_MSG_SIZE];
-	size_t  rx_msg_length;
+	uint8_t rx_msg[HECI_MAX_MSG_SIZE];
+	size_t rx_msg_length;
 
 	uint32_t flow_ctrl_creds; /* flow control */
 	struct mutex lock; /* protects against 2 writers */
@@ -67,7 +68,7 @@ struct heci_client_connect {
 
 struct heci_client_context {
 	const struct heci_client *client;
-	void *data;	/* client specific data */
+	void *data; /* client specific data */
 
 	struct heci_client_connect connect; /* connection context */
 	struct ss_subsys_device ss_device; /* system state receiver device */
@@ -82,7 +83,7 @@ struct heci_bus_context {
 
 /* declare heci bus */
 struct heci_bus_context heci_bus_ctx = {
-		.ipc_handle = IPC_INVALID_HANDLE,
+	.ipc_handle = IPC_INVALID_HANDLE,
 };
 
 static inline struct heci_client_context *
@@ -118,11 +119,14 @@ static inline int heci_is_valid_handle(const heci_handle_t handle)
 
 /* find heci device that contains this system state device in it */
 #define ss_device_to_heci_client_context(ss_dev) \
-	((struct heci_client_context *)((void *)(ss_dev) - \
-	(void *)(&(((struct heci_client_context *)0)->ss_device))))
-#define client_context_to_handle(cli_ctx) \
-	((heci_handle_t)((uint32_t)((cli_ctx) - &heci_bus_ctx.client_ctxs[0]) \
-	/ sizeof(heci_bus_ctx.client_ctxs[0]) + 1))
+	((struct heci_client_context             \
+		  *)((void *)(ss_dev) -          \
+		     (void *)(&(                 \
+			     ((struct heci_client_context *)0)->ss_device))))
+#define client_context_to_handle(cli_ctx)                                       \
+	((heci_handle_t)((uint32_t)((cli_ctx) - &heci_bus_ctx.client_ctxs[0]) / \
+				 sizeof(heci_bus_ctx.client_ctxs[0]) +          \
+			 1))
 
 /*
  * each heci device registered as system state device which gets
@@ -132,7 +136,7 @@ static inline int heci_is_valid_handle(const heci_handle_t handle)
 static int heci_client_suspend(struct ss_subsys_device *ss_device)
 {
 	struct heci_client_context *cli_ctx =
-			ss_device_to_heci_client_context(ss_device);
+		ss_device_to_heci_client_context(ss_device);
 	heci_handle_t handle = client_context_to_handle(cli_ctx);
 
 	if (cli_ctx->client->cbs->suspend)
@@ -144,7 +148,7 @@ static int heci_client_suspend(struct ss_subsys_device *ss_device)
 static int heci_client_resume(struct ss_subsys_device *ss_device)
 {
 	struct heci_client_context *cli_ctx =
-			ss_device_to_heci_client_context(ss_device);
+		ss_device_to_heci_client_context(ss_device);
 	heci_handle_t handle = client_context_to_handle(cli_ctx);
 
 	if (cli_ctx->client->cbs->resume)
@@ -239,8 +243,8 @@ static int heci_send_heci_msg_timestamp(struct heci_msg *msg,
 				      timestamp);
 
 	if (written != length) {
-		CPRINTF("%s error : len = %d err = %d\n", __func__,
-			(int)length, written);
+		CPRINTF("%s error : len = %d err = %d\n", __func__, (int)length,
+			written);
 		return -EC_ERROR_UNKNOWN;
 	}
 
@@ -381,7 +385,6 @@ int heci_send_msg(const heci_handle_t handle, uint8_t *buf,
 	return heci_send_msg_timestamp(handle, buf, buf_size, NULL);
 }
 
-
 int heci_send_msgs(const heci_handle_t handle,
 		   const struct heci_msg_list *msg_list)
 {
@@ -453,8 +456,8 @@ int heci_send_msgs(const heci_handle_t handle,
 
 			/* no leftovers, send the last msg here */
 			if (msg_sent == total_size) {
-				msg.hdr.length |=
-					(uint16_t)1 << HECI_MSG_CMPL_SHIFT;
+				msg.hdr.length |= (uint16_t)1
+						  << HECI_MSG_CMPL_SHIFT;
 			}
 
 			heci_send_heci_msg(&msg);
@@ -488,7 +491,6 @@ err_locked:
 	mutex_unlock(&connect->lock);
 
 	return total_size;
-
 }
 
 /* For now, we only support fixed client payload size < IPC payload size */
@@ -535,9 +537,9 @@ static int handle_version_req(struct hbm_version_req *ver_req)
 	return EC_SUCCESS;
 }
 
-#define BITS_PER_BYTE			8
+#define BITS_PER_BYTE 8
 /* get number of bits for one element of "valid_addresses" array */
-#define	BITS_PER_ELEMENT \
+#define BITS_PER_ELEMENT \
 	(sizeof(((struct hbm_enum_res *)0)->valid_addresses[0]) * BITS_PER_BYTE)
 
 static int handle_enum_req(struct hbm_enum_req *enum_req)
@@ -604,11 +606,11 @@ static int handle_client_prop_req(struct hbm_client_prop_req *client_prop_req)
 		client_prop->protocol_name = client->protocol_id;
 		client_prop->protocol_version = client->protocol_ver;
 		client_prop->max_number_of_connections =
-						client->max_n_of_connections;
+			client->max_n_of_connections;
 		client_prop->max_msg_length = client->max_msg_size;
 		client_prop->dma_hdr_len = client->dma_header_length;
-		client_prop->dma_hdr_len |= client->dma_enabled ?
-					    CLIENT_DMA_ENABLE : 0;
+		client_prop->dma_hdr_len |=
+			client->dma_enabled ? CLIENT_DMA_ENABLE : 0;
 	}
 
 	heci_send_heci_msg(&heci_msg);
@@ -642,8 +644,8 @@ static int heci_send_flow_control(uint8_t fw_addr)
 	return EC_SUCCESS;
 }
 
-static int handle_client_connect_req(
-			struct hbm_client_connect_req *client_connect_req)
+static int
+handle_client_connect_req(struct hbm_client_connect_req *client_connect_req)
 {
 	struct hbm_client_connect_res *client_connect_res;
 	struct heci_msg heci_msg;
@@ -663,7 +665,7 @@ static int handle_client_connect_req(
 	client_connect_res->host_addr = client_connect_req->host_addr;
 	if (!heci_is_valid_client_addr(client_connect_req->fw_addr)) {
 		client_connect_res->status =
-					HECI_CONNECT_STATUS_CLIENT_NOT_FOUND;
+			HECI_CONNECT_STATUS_CLIENT_NOT_FOUND;
 	} else if (!client_connect_req->host_addr) {
 		client_connect_res->status =
 			HECI_CONNECT_STATUS_INVALID_PARAMETER;
@@ -671,7 +673,7 @@ static int handle_client_connect_req(
 		connect = heci_get_client_connect(client_connect_req->fw_addr);
 		if (connect->is_connected) {
 			client_connect_res->status =
-					HECI_CONNECT_STATUS_ALREADY_EXISTS;
+				HECI_CONNECT_STATUS_ALREADY_EXISTS;
 		} else {
 			connect->is_connected = 1;
 			connect->host_addr = client_connect_req->host_addr;
@@ -729,8 +731,7 @@ static void heci_handle_client_msg(struct heci_msg *msg, size_t length)
 	connect = &cli_ctx->connect;
 
 	payload_size = HECI_MSG_LENGTH(msg->hdr.length);
-	if (connect->is_connected &&
-	    msg->hdr.host_addr == connect->host_addr) {
+	if (connect->is_connected && msg->hdr.host_addr == connect->host_addr) {
 		if (!connect->ignore_rx_msg &&
 		    connect->rx_msg_length + payload_size > HECI_MAX_MSG_SIZE) {
 			connect->ignore_rx_msg = 1; /* too big. discard */
@@ -760,7 +761,7 @@ static void heci_handle_client_msg(struct heci_msg *msg, size_t length)
 }
 
 static int handle_client_disconnect_req(
-			struct hbm_client_disconnect_req *client_disconnect_req)
+	struct hbm_client_disconnect_req *client_disconnect_req)
 {
 	struct hbm_client_disconnect_res *client_disconnect_res;
 	struct heci_msg heci_msg;
@@ -772,8 +773,9 @@ static int handle_client_disconnect_req(
 
 	CPRINTS("Got HECI disconnect request");
 
-	heci_build_hbm_header(&heci_msg.hdr, sizeof(i2h->cmd) +
-					     sizeof(*client_disconnect_res));
+	heci_build_hbm_header(&heci_msg.hdr,
+			      sizeof(i2h->cmd) +
+				      sizeof(*client_disconnect_res));
 
 	i2h = (struct hbm_i2h *)heci_msg.payload;
 	i2h->cmd = HECI_BUS_MSG_CLIENT_DISCONNECT_RESP;
@@ -789,7 +791,7 @@ static int handle_client_disconnect_req(
 	if (!heci_is_valid_client_addr(fw_addr) ||
 	    !heci_is_client_connected(fw_addr)) {
 		client_disconnect_res->status =
-					HECI_CONNECT_STATUS_CLIENT_NOT_FOUND;
+			HECI_CONNECT_STATUS_CLIENT_NOT_FOUND;
 	} else {
 		connect = heci_get_client_connect(fw_addr);
 		if (connect->host_addr != host_addr) {
@@ -891,8 +893,8 @@ static int is_hbm_validity(struct hbm_h2i *h2i, size_t length)
 	}
 
 	if (valid_msg_len != length) {
-		CPRINTF("invalid cmd(%d) valid : %d, cur : %zd\n",
-			h2i->cmd, valid_msg_len, length);
+		CPRINTF("invalid cmd(%d) valid : %d, cur : %zd\n", h2i->cmd,
+			valid_msg_len, length);
 		/* TODO: invalid cmd. not sure to reply with error ? */
 		return 0;
 	}
@@ -922,7 +924,7 @@ static void heci_handle_hbm(struct hbm_h2i *h2i, size_t length)
 
 	case HECI_BUS_MSG_CLIENT_CONNECT_REQ:
 		handle_client_connect_req(
-					(struct hbm_client_connect_req *)data);
+			(struct hbm_client_connect_req *)data);
 		break;
 
 	case HECI_BUS_MSG_FLOW_CONTROL:
@@ -931,7 +933,7 @@ static void heci_handle_hbm(struct hbm_h2i *h2i, size_t length)
 
 	case HECI_BUS_MSG_CLIENT_DISCONNECT_REQ:
 		handle_client_disconnect_req(
-				(struct hbm_client_disconnect_req *)data);
+			(struct hbm_client_disconnect_req *)data);
 		break;
 
 	case HECI_BUS_MSG_HOST_STOP_REQ:
@@ -991,7 +993,7 @@ static void heci_handle_heci_msg(struct heci_msg *heci_msg, size_t msg_length)
 }
 
 /* event flag for HECI msg */
-#define EVENT_FLAG_BIT_HECI_MSG			TASK_EVENT_CUSTOM_BIT(0)
+#define EVENT_FLAG_BIT_HECI_MSG TASK_EVENT_CUSTOM_BIT(0)
 
 void heci_rx_task(void)
 {
@@ -1017,8 +1019,9 @@ void heci_rx_task(void)
 			continue;
 		}
 
-		if (HECI_MSG_LENGTH(heci_msg.hdr.length) + sizeof(heci_msg.hdr)
-		    == msg_len)
+		if (HECI_MSG_LENGTH(heci_msg.hdr.length) +
+			    sizeof(heci_msg.hdr) ==
+		    msg_len)
 			heci_handle_heci_msg(&heci_msg, msg_len);
 		else
 			CPRINTS("msg len mismatch.. discard..");
diff --git a/chip/ish/heci_client.h b/chip/ish/heci_client.h
index 9dca4bff90..951b82c6d9 100644
--- a/chip/ish/heci_client.h
+++ b/chip/ish/heci_client.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,21 +11,21 @@
 
 #include "hooks.h"
 
-#define HECI_MAX_NUM_OF_CLIENTS			2
+#define HECI_MAX_NUM_OF_CLIENTS 2
 
-#define HECI_MAX_MSG_SIZE			4960
-#define HECI_IPC_PAYLOAD_SIZE   (IPC_MAX_PAYLOAD_SIZE - 4)
-#define HECI_MAX_MSGS				3
+#define HECI_MAX_MSG_SIZE 4960
+#define HECI_IPC_PAYLOAD_SIZE (IPC_MAX_PAYLOAD_SIZE - 4)
+#define HECI_MAX_MSGS 3
 
 enum HECI_ERR {
-	HECI_ERR_TOO_MANY_MSG_ITEMS		= EC_ERROR_INTERNAL_FIRST + 0,
-	HECI_ERR_NO_CRED_FROM_CLIENT_IN_HOST	= EC_ERROR_INTERNAL_FIRST + 1,
-	HECI_ERR_CLIENT_IS_NOT_CONNECTED	= EC_ERROR_INTERNAL_FIRST + 2,
+	HECI_ERR_TOO_MANY_MSG_ITEMS = EC_ERROR_INTERNAL_FIRST + 0,
+	HECI_ERR_NO_CRED_FROM_CLIENT_IN_HOST = EC_ERROR_INTERNAL_FIRST + 1,
+	HECI_ERR_CLIENT_IS_NOT_CONNECTED = EC_ERROR_INTERNAL_FIRST + 2,
 };
 
-typedef void *					heci_handle_t;
+typedef void *heci_handle_t;
 
-#define HECI_INVALID_HANDLE			NULL
+#define HECI_INVALID_HANDLE NULL
 
 struct heci_guid {
 	uint32_t data1;
@@ -57,8 +57,8 @@ struct heci_client {
 	uint32_t max_msg_size;
 	uint8_t protocol_ver;
 	uint8_t max_n_of_connections;
-	uint8_t dma_header_length :7;
-	uint8_t dma_enabled :1;
+	uint8_t dma_header_length : 7;
+	uint8_t dma_enabled : 1;
 
 	const struct heci_client_callbacks *cbs;
 };
@@ -91,7 +91,7 @@ void *heci_get_client_data(const heci_handle_t handle);
 int heci_send_msg(const heci_handle_t handle, uint8_t *buf,
 		  const size_t buf_size);
 int heci_send_msg_timestamp(const heci_handle_t handle, uint8_t *buf,
-		  const size_t buf_size, uint32_t *timestamp);
+			    const size_t buf_size, uint32_t *timestamp);
 /*
  * send client msgs(using list of buffer&size).
  * heci_msg_item with size == 0 is not acceptable.
@@ -102,11 +102,11 @@ int heci_send_msgs(const heci_handle_t handle,
 int heci_send_fixed_client_msg(const uint8_t fw_addr, uint8_t *buf,
 			       const size_t buf_size);
 
-#define HECI_CLIENT_ENTRY(heci_client) \
-	void _heci_entry_##heci_client(void) \
-	{ \
+#define HECI_CLIENT_ENTRY(heci_client)                \
+	void _heci_entry_##heci_client(void)          \
+	{                                             \
 		heci_register_client(&(heci_client)); \
-	} \
+	}                                             \
 	DECLARE_HOOK(HOOK_INIT, _heci_entry_##heci_client, HOOK_PRIO_LAST - 1)
 
 #endif /* __HECI_CLIENT_H */
diff --git a/chip/ish/hid_device.h b/chip/ish/hid_device.h
index 0a32e305af..ba7722f5bb 100644
--- a/chip/ish/hid_device.h
+++ b/chip/ish/hid_device.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,15 +11,15 @@
 
 #include "hooks.h"
 
-#define HID_SUBSYS_MAX_PAYLOAD_SIZE			4954
+#define HID_SUBSYS_MAX_PAYLOAD_SIZE 4954
 
 enum HID_SUBSYS_ERR {
-	HID_SUBSYS_ERR_NOT_READY		= EC_ERROR_INTERNAL_FIRST + 0,
-	HID_SUBSYS_ERR_TOO_MANY_HID_DEVICES	= EC_ERROR_INTERNAL_FIRST + 1,
+	HID_SUBSYS_ERR_NOT_READY = EC_ERROR_INTERNAL_FIRST + 0,
+	HID_SUBSYS_ERR_TOO_MANY_HID_DEVICES = EC_ERROR_INTERNAL_FIRST + 1,
 };
 
-typedef void *					hid_handle_t;
-#define HID_INVALID_HANDLE			NULL
+typedef void *hid_handle_t;
+#define HID_INVALID_HANDLE NULL
 
 struct hid_callbacks {
 	/*
@@ -73,11 +73,11 @@ int hid_subsys_set_device_data(const hid_handle_t handle, void *data);
 /* retrieve HID device specific data */
 void *hid_subsys_get_device_data(const hid_handle_t handle);
 
-#define HID_DEVICE_ENTRY(hid_dev) \
-	void _hid_dev_entry_##hid_dev(void) \
-	{ \
+#define HID_DEVICE_ENTRY(hid_dev)                       \
+	void _hid_dev_entry_##hid_dev(void)             \
+	{                                               \
 		hid_subsys_register_device(&(hid_dev)); \
-	} \
+	}                                               \
 	DECLARE_HOOK(HOOK_INIT, _hid_dev_entry_##hid_dev, HOOK_PRIO_LAST - 2)
 
 #endif /* __HID_DEVICE_H */
diff --git a/chip/ish/hid_subsys.c b/chip/ish/hid_subsys.c
index bd3f331fdc..555af9046a 100644
--- a/chip/ish/hid_subsys.c
+++ b/chip/ish/hid_subsys.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,8 @@
 
 #ifdef HID_SUBSYS_DEBUG
 #define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_LPC, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_LPC, format, ##args)
 #else
 #define CPUTS(outstr)
 #define CPRINTS(format, args...)
@@ -21,10 +21,15 @@
 
 #define __packed __attribute__((packed))
 
-#define HECI_CLIENT_HID_GUID { 0x33AECD58, 0xB679, 0x4E54,\
-			 { 0x9B, 0xD9, 0xA0, 0x4D, 0x34, 0xF0, 0xC2, 0x26 } }
+#define HECI_CLIENT_HID_GUID                                           \
+	{                                                              \
+		0x33AECD58, 0xB679, 0x4E54,                            \
+		{                                                      \
+			0x9B, 0xD9, 0xA0, 0x4D, 0x34, 0xF0, 0xC2, 0x26 \
+		}                                                      \
+	}
 
-#define HID_SUBSYS_MAX_HID_DEVICES			3
+#define HID_SUBSYS_MAX_HID_DEVICES 3
 
 /*
  * the following enum values and data structures with __packed are used for
@@ -55,13 +60,13 @@ struct hid_device_info {
 	uint16_t vid;
 } __packed;
 
-struct hid_enum_payload	{
+struct hid_enum_payload {
 	uint8_t num_of_hid_devices;
 	struct hid_device_info dev_info[0];
 } __packed;
 
-#define COMMAND_MASK			0x7F
-#define RESPONSE_FLAG			0x80
+#define COMMAND_MASK 0x7F
+#define RESPONSE_FLAG 0x80
 struct hid_msg_hdr {
 	uint8_t command; /* bit 7 is used to indicate "response" */
 	uint8_t device_id;
@@ -94,8 +99,8 @@ static struct hid_subsystem hid_subsys_ctx = {
 	.heci_handle = HECI_INVALID_HANDLE,
 };
 
-#define handle_to_dev_id(_handle)	((uintptr_t)(_handle))
-#define dev_id_to_handle(_dev_id)	((hid_handle_t)(uintptr_t)(_dev_id))
+#define handle_to_dev_id(_handle) ((uintptr_t)(_handle))
+#define dev_id_to_handle(_dev_id) ((hid_handle_t)(uintptr_t)(_dev_id))
 
 static inline hid_handle_t device_index_to_handle(int device_index)
 {
@@ -108,8 +113,8 @@ static inline int is_valid_handle(hid_handle_t handle)
 	       (uintptr_t)handle <= hid_subsys_ctx.num_of_hid_devices;
 }
 
-static inline
-struct hid_subsys_hid_device *handle_to_hid_device(hid_handle_t handle)
+static inline struct hid_subsys_hid_device *
+handle_to_hid_device(hid_handle_t handle)
 {
 	if (!is_valid_handle(handle))
 		return NULL;
@@ -117,7 +122,6 @@ struct hid_subsys_hid_device *handle_to_hid_device(hid_handle_t handle)
 	return &hid_subsys_ctx.hid_devices[(uintptr_t)handle - 1];
 }
 
-
 hid_handle_t hid_subsys_register_device(const struct hid_device *dev_info)
 {
 	struct hid_subsys_hid_device *hid_device;
@@ -156,7 +160,7 @@ int hid_subsys_send_input_report(const hid_handle_t handle, uint8_t *buf,
 				 const size_t buf_size)
 {
 	struct hid_subsys_hid_device *hid_device;
-	struct hid_msg_hdr hid_msg_hdr = {0};
+	struct hid_msg_hdr hid_msg_hdr = { 0 };
 	struct heci_msg_item msg_item[2];
 	struct heci_msg_list msg_list;
 
@@ -253,7 +257,7 @@ static int handle_hid_device_msg(struct hid_msg *hid_msg)
 	 * re-use hid_msg from host for reply.
 	 */
 	switch (hid_msg->hdr.command & COMMAND_MASK) {
-	case  HID_GET_HID_DESCRIPTOR:
+	case HID_GET_HID_DESCRIPTOR:
 		if (cbs->get_hid_descriptor)
 			ret = cbs->get_hid_descriptor(handle, payload,
 						      buf_size);
@@ -277,10 +281,8 @@ static int handle_hid_device_msg(struct hid_msg *hid_msg)
 
 	case HID_SET_FEATURE_REPORT:
 		if (cbs->set_feature_report) {
-			ret = cbs->set_feature_report(handle,
-						      payload[0],
-						      payload,
-						      payload_size);
+			ret = cbs->set_feature_report(handle, payload[0],
+						      payload, payload_size);
 			/*
 			 * if no error, reply only with the report id.
 			 * re-use the first byte of payload
@@ -293,8 +295,8 @@ static int handle_hid_device_msg(struct hid_msg *hid_msg)
 		break;
 	case HID_GET_INPUT_REPORT:
 		if (cbs->get_input_report)
-			ret = cbs->get_input_report(handle, payload[0],
-						    payload, buf_size);
+			ret = cbs->get_input_report(handle, payload[0], payload,
+						    buf_size);
 
 		break;
 
@@ -331,21 +333,21 @@ static int handle_hid_subsys_msg(struct hid_msg *hid_msg)
 	struct hid_enum_payload *enum_payload;
 
 	switch (hid_msg->hdr.command & COMMAND_MASK) {
-	case  HID_DM_ENUM_DEVICES:
+	case HID_DM_ENUM_DEVICES:
 		enum_payload = (struct hid_enum_payload *)hid_msg->payload;
 
 		for (i = 0; i < hid_subsys_ctx.num_of_hid_devices; i++) {
 			enum_payload->dev_info[i] =
-					hid_subsys_ctx.hid_devices[i].info;
+				hid_subsys_ctx.hid_devices[i].info;
 		}
 
 		enum_payload->num_of_hid_devices =
-					hid_subsys_ctx.num_of_hid_devices;
+			hid_subsys_ctx.num_of_hid_devices;
 
 		/* reply payload size */
 		size = sizeof(enum_payload->num_of_hid_devices);
 		size += enum_payload->num_of_hid_devices *
-					sizeof(enum_payload->dev_info[0]);
+			sizeof(enum_payload->dev_info[0]);
 
 		break;
 
@@ -408,7 +410,7 @@ static int hid_subsys_resume(const heci_handle_t heci_handle)
 	for (i = 0; i < hid_subsys_ctx.num_of_hid_devices; i++) {
 		if (hid_subsys_ctx.hid_devices[i].cbs->resume)
 			ret |= hid_subsys_ctx.hid_devices[i].cbs->resume(
-					device_index_to_handle(i));
+				device_index_to_handle(i));
 	}
 
 	return ret;
@@ -422,7 +424,7 @@ static int hid_subsys_suspend(const heci_handle_t heci_handle)
 	for (i = hid_subsys_ctx.num_of_hid_devices - 1; i >= 0; i--) {
 		if (hid_subsys_ctx.hid_devices[i].cbs->suspend)
 			ret |= hid_subsys_ctx.hid_devices[i].cbs->suspend(
-					device_index_to_handle(i));
+				device_index_to_handle(i));
 	}
 
 	return ret;
diff --git a/chip/ish/host_command_heci.c b/chip/ish/host_command_heci.c
index de1485417b..ede615804c 100644
--- a/chip/ish/host_command_heci.c
+++ b/chip/ish/host_command_heci.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,11 +13,16 @@
 #include "util.h"
 
 #define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_LPC, format, ## args)
-
-#define HECI_CLIENT_CROS_EC_ISH_GUID { 0x7b7154d0, 0x56f4, 0x4bdc,\
-			 { 0xb0, 0xd8, 0x9e, 0x7c, 0xda, 0xe0, 0xd6, 0xa0 } }
+#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_LPC, format, ##args)
+
+#define HECI_CLIENT_CROS_EC_ISH_GUID                                   \
+	{                                                              \
+		0x7b7154d0, 0x56f4, 0x4bdc,                            \
+		{                                                      \
+			0xb0, 0xd8, 0x9e, 0x7c, 0xda, 0xe0, 0xd6, 0xa0 \
+		}                                                      \
+	}
 
 /* Handle for all heci cros_ec interactions */
 static heci_handle_t heci_cros_ec_handle = HECI_INVALID_HANDLE;
@@ -33,7 +38,7 @@ static heci_handle_t heci_cros_ec_handle = HECI_INVALID_HANDLE;
 struct cros_ec_ishtp_msg_hdr {
 	uint8_t channel;
 	uint8_t status;
-	uint8_t id;	/* Pairs up request and responses */
+	uint8_t id; /* Pairs up request and responses */
 	uint8_t reserved;
 } __ec_align4;
 
@@ -88,10 +93,11 @@ static void heci_send_hostcmd_response(struct host_packet *pkt)
 }
 
 static void cros_ec_ishtp_subsys_new_msg_received(const heci_handle_t handle,
-					uint8_t *msg, const size_t msg_size)
+						  uint8_t *msg,
+						  const size_t msg_size)
 {
-	struct cros_ec_ishtp_msg *in = (void *) msg;
-	struct cros_ec_ishtp_msg *out = (void *) response_buffer;
+	struct cros_ec_ishtp_msg *in = (void *)msg;
+	struct cros_ec_ishtp_msg *out = (void *)response_buffer;
 
 	if (in->hdr.channel != CROS_EC_COMMAND) {
 		CPRINTS("Unknown HECI packet 0x%02x", in->hdr.channel);
@@ -140,7 +146,7 @@ static enum ec_status heci_get_protocol_info(struct host_cmd_handler_args *args)
 	return EC_RES_SUCCESS;
 }
 DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, heci_get_protocol_info,
-EC_VER_MASK(0));
+		     EC_VER_MASK(0));
 
 static int cros_ec_ishtp_subsys_initialize(const heci_handle_t heci_handle)
 {
diff --git a/chip/ish/hpet.h b/chip/ish/hpet.h
index 06738fafb1..7438f42949 100644
--- a/chip/ish/hpet.h
+++ b/chip/ish/hpet.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,61 +10,58 @@
 
 /* ISH HPET config and timer registers */
 
-#define TIMER0_CONF_CAP_REG		0x100
-#define TIMER0_COMP_VAL_REG		0x108
-
+#define TIMER0_CONF_CAP_REG 0x100
+#define TIMER0_COMP_VAL_REG 0x108
 
 /* HPET_GENERAL_CONFIG settings  */
-#define HPET_GENERAL_CONFIG		REG32(ISH_HPET_BASE + 0x10)
-#define HPET_ENABLE_CNF		BIT(0)
-#define HPET_LEGACY_RT_CNF	BIT(1)
+#define HPET_GENERAL_CONFIG REG32(ISH_HPET_BASE + 0x10)
+#define HPET_ENABLE_CNF BIT(0)
+#define HPET_LEGACY_RT_CNF BIT(1)
 
 /* Interrupt status acknowledge register */
-#define HPET_INTR_CLEAR		REG32(ISH_HPET_BASE + 0x20)
+#define HPET_INTR_CLEAR REG32(ISH_HPET_BASE + 0x20)
 
 /* Main counter register. 64-bit */
-#define HPET_MAIN_COUNTER_64	REG64(ISH_HPET_BASE + 0xF0)
-#define HPET_MAIN_COUNTER_64_LO	REG32(ISH_HPET_BASE + 0xF0)
-#define HPET_MAIN_COUNTER_64_HI	REG32(ISH_HPET_BASE + 0xF4)
+#define HPET_MAIN_COUNTER_64 REG64(ISH_HPET_BASE + 0xF0)
+#define HPET_MAIN_COUNTER_64_LO REG32(ISH_HPET_BASE + 0xF0)
+#define HPET_MAIN_COUNTER_64_HI REG32(ISH_HPET_BASE + 0xF4)
 
 /* HPET Timer 0/1/2 configuration*/
-#define HPET_TIMER_CONF_CAP(x)	REG32(ISH_HPET_BASE + 0x100 + ((x) * 0x20))
-#define HPET_Tn_INT_TYPE_CNF		BIT(1)
-#define HPET_Tn_INT_ENB_CNF		BIT(2)
-#define HPET_Tn_TYPE_CNF		BIT(3)
-#define HPET_Tn_VAL_SET_CNF		BIT(6)
-#define HPET_Tn_32MODE_CNF		BIT(8)
-#define HPET_Tn_INT_ROUTE_CNF_SHIFT	0x9
-#define HPET_Tn_INT_ROUTE_CNF_MASK	(0x1f << 9)
+#define HPET_TIMER_CONF_CAP(x) REG32(ISH_HPET_BASE + 0x100 + ((x)*0x20))
+#define HPET_Tn_INT_TYPE_CNF BIT(1)
+#define HPET_Tn_INT_ENB_CNF BIT(2)
+#define HPET_Tn_TYPE_CNF BIT(3)
+#define HPET_Tn_VAL_SET_CNF BIT(6)
+#define HPET_Tn_32MODE_CNF BIT(8)
+#define HPET_Tn_INT_ROUTE_CNF_SHIFT 0x9
+#define HPET_Tn_INT_ROUTE_CNF_MASK (0x1f << 9)
 
 /*
  * HPET Timer 0/1/2 comparator values. 1/2 are always 32-bit. 0 can be
  * configured as 64-bit.
  */
-#define HPET_TIMER_COMP(x)	REG32(ISH_HPET_BASE + 0x108 + ((x) * 0x20))
-#define HPET_TIMER0_COMP_64	REG64(ISH_HPET_BASE + 0x108)
+#define HPET_TIMER_COMP(x) REG32(ISH_HPET_BASE + 0x108 + ((x)*0x20))
+#define HPET_TIMER0_COMP_64 REG64(ISH_HPET_BASE + 0x108)
 
 /* ISH 4/5: Special status register
  * Use this register to see HPET timer are settled after a write.
  */
-#define HPET_CTRL_STATUS		REG32(ISH_HPET_BASE + 0x160)
-#define HPET_INT_STATUS_SETTLING	BIT(1)
-#define HPET_MAIN_COUNTER_SETTLING	(BIT(2) | BIT(3))
-#define HPET_T0_CAP_SETTLING		BIT(4)
-#define HPET_T1_CAP_SETTLING		BIT(5)
-#define HPET_T0_CMP_SETTLING		(BIT(7) | BIT(8))
-#define HPET_T1_CMP_SETTLING		BIT(9)
-#define HPET_MAIN_COUNTER_VALID		BIT(13)
-#define HPET_T1_SETTLING		(HPET_T1_CAP_SETTLING | \
-					 HPET_T1_CMP_SETTLING)
-#define HPET_T0_SETTLING		(HPET_T0_CAP_SETTLING | \
-					 HPET_T0_CMP_SETTLING)
-#define HPET_ANY_SETTLING		(BIT(12) - 1)
+#define HPET_CTRL_STATUS REG32(ISH_HPET_BASE + 0x160)
+#define HPET_INT_STATUS_SETTLING BIT(1)
+#define HPET_MAIN_COUNTER_SETTLING (BIT(2) | BIT(3))
+#define HPET_T0_CAP_SETTLING BIT(4)
+#define HPET_T1_CAP_SETTLING BIT(5)
+#define HPET_T0_CMP_SETTLING (BIT(7) | BIT(8))
+#define HPET_T1_CMP_SETTLING BIT(9)
+#define HPET_MAIN_COUNTER_VALID BIT(13)
+#define HPET_T1_SETTLING (HPET_T1_CAP_SETTLING | HPET_T1_CMP_SETTLING)
+#define HPET_T0_SETTLING (HPET_T0_CAP_SETTLING | HPET_T0_CMP_SETTLING)
+#define HPET_ANY_SETTLING (BIT(12) - 1)
 
 #if defined(CHIP_FAMILY_ISH3)
-#define ISH_HPET_CLK_FREQ		12000000	/* 12 MHz clock */
+#define ISH_HPET_CLK_FREQ 12000000 /* 12 MHz clock */
 #elif defined(CHIP_FAMILY_ISH4) || defined(CHIP_FAMILY_ISH5)
-#define ISH_HPET_CLK_FREQ		32768		/* 32.768 KHz clock */
+#define ISH_HPET_CLK_FREQ 32768 /* 32.768 KHz clock */
 #endif
 
 #endif /* __CROS_EC_HPET_H */
diff --git a/chip/ish/hwtimer.c b/chip/ish/hwtimer.c
index 1259dae7f4..57049a63b3 100644
--- a/chip/ish/hwtimer.c
+++ b/chip/ish/hwtimer.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,8 +14,8 @@
 #include "util.h"
 
 #define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ##args)
 
 static uint32_t last_deadline;
 
@@ -37,7 +37,7 @@ static uint32_t last_deadline;
 /* Scaling helper methods for different ISH chip variants */
 #ifdef CHIP_FAMILY_ISH3
 #define CLOCK_FACTOR 12
-BUILD_ASSERT(CLOCK_FACTOR * SECOND == ISH_HPET_CLK_FREQ);
+BUILD_ASSERT(CLOCK_FACTOR *SECOND == ISH_HPET_CLK_FREQ);
 
 static inline uint64_t scale_us2ticks(uint64_t us)
 {
@@ -239,8 +239,7 @@ int __hw_clock_source_init64(uint64_t start_t)
 
 	/* Timer 1 - IRQ routing */
 	timer1_config &= ~HPET_Tn_INT_ROUTE_CNF_MASK;
-	timer1_config |= (ISH_HPET_TIMER1_IRQ <<
-			  HPET_Tn_INT_ROUTE_CNF_SHIFT);
+	timer1_config |= (ISH_HPET_TIMER1_IRQ << HPET_Tn_INT_ROUTE_CNF_SHIFT);
 
 	/* Level triggered interrupt */
 	timer1_config |= HPET_Tn_INT_TYPE_CNF;
diff --git a/chip/ish/i2c.c b/chip/ish/i2c.c
index 11f3e0a0b1..e26bcd70e5 100644
--- a/chip/ish/i2c.c
+++ b/chip/ish/i2c.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,65 +19,53 @@
 #include "util.h"
 
 #define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args)
 
 /*25MHz, 50MHz, 100MHz, 120MHz, 40MHz, 20MHz, 37MHz*/
-static uint16_t default_hcnt_scl_100[] = {
-	4000, 4420, 4920, 4400, 4000, 4000, 4300
-};
+static uint16_t default_hcnt_scl_100[] = { 4000, 4420, 4920, 4400,
+					   4000, 4000, 4300 };
 
-static uint16_t default_lcnt_scl_100[] = {
-	4720, 5180, 4990, 5333, 4700, 5200, 4950
-};
+static uint16_t default_lcnt_scl_100[] = { 4720, 5180, 4990, 5333,
+					   4700, 5200, 4950 };
 
-static uint16_t default_hcnt_scl_400[] = {
-	600, 820, 1120, 800, 600, 600, 450
-};
+static uint16_t default_hcnt_scl_400[] = { 600, 820, 1120, 800, 600, 600, 450 };
 
-static uint16_t default_lcnt_scl_400[] = {
-	1320, 1380, 1300, 1550, 1300, 1200, 1250
-};
+static uint16_t default_lcnt_scl_400[] = { 1320, 1380, 1300, 1550,
+					   1300, 1200, 1250 };
 
-static uint16_t default_hcnt_scl_1000[] = {
-	260, 260, 260, 305, 260, 260, 260
-};
+static uint16_t default_hcnt_scl_1000[] = { 260, 260, 260, 305, 260, 260, 260 };
 
-static uint16_t default_lcnt_scl_1000[] = {
-	500, 500, 500, 525, 500, 500, 500
-};
+static uint16_t default_lcnt_scl_1000[] = { 500, 500, 500, 525, 500, 500, 500 };
 
 static uint16_t default_hcnt_scl_hs[] = { 160, 300, 160, 166, 175, 150, 162 };
 static uint16_t default_lcnt_scl_hs[] = { 320, 340, 320, 325, 325, 300, 297 };
 
-
 #ifdef CHIP_VARIANT_ISH5P4
 /* Change to I2C_FREQ_100 in real silicon platform */
-static uint8_t bus_freq[ISH_I2C_PORT_COUNT] = {
-	I2C_FREQ_100, I2C_FREQ_100, I2C_FREQ_100
-};
+static uint8_t bus_freq[ISH_I2C_PORT_COUNT] = { I2C_FREQ_100, I2C_FREQ_100,
+						I2C_FREQ_100 };
 #else
-static uint8_t bus_freq[ISH_I2C_PORT_COUNT] = {
-	I2C_FREQ_120, I2C_FREQ_120, I2C_FREQ_120
-};
+static uint8_t bus_freq[ISH_I2C_PORT_COUNT] = { I2C_FREQ_120, I2C_FREQ_120,
+						I2C_FREQ_120 };
 #endif
 
 static struct i2c_context i2c_ctxs[ISH_I2C_PORT_COUNT] = {
 	{
 		.bus = 0,
-		.base = (uint32_t *) ISH_I2C0_BASE,
+		.base = (uint32_t *)ISH_I2C0_BASE,
 		.speed = I2C_SPEED_400KHZ,
 		.int_pin = ISH_I2C0_IRQ,
 	},
 	{
 		.bus = 1,
-		.base = (uint32_t *) ISH_I2C1_BASE,
+		.base = (uint32_t *)ISH_I2C1_BASE,
 		.speed = I2C_SPEED_400KHZ,
 		.int_pin = ISH_I2C1_IRQ,
 	},
 	{
 		.bus = 2,
-		.base = (uint32_t *) ISH_I2C2_BASE,
+		.base = (uint32_t *)ISH_I2C2_BASE,
 		.speed = I2C_SPEED_400KHZ,
 		.int_pin = ISH_I2C2_IRQ,
 	},
@@ -104,22 +92,20 @@ static struct i2c_bus_info board_config[ISH_I2C_PORT_COUNT] = {
 		.fast_speed.sda_hold = DEFAULT_SDA_HOLD_FAST,
 		.fast_plus_speed.sda_hold = DEFAULT_SDA_HOLD_FAST_PLUS,
 		.high_speed.sda_hold = DEFAULT_SDA_HOLD_HIGH,
-	 },
+	},
 };
 
-static inline void i2c_mmio_write(uint32_t *base, uint8_t offset,
-				  uint32_t data)
+static inline void i2c_mmio_write(uint32_t *base, uint8_t offset, uint32_t data)
 {
-	REG32((uint32_t) ((uint8_t *)base + offset)) = data;
+	REG32((uint32_t)((uint8_t *)base + offset)) = data;
 }
 
 static inline uint32_t i2c_mmio_read(uint32_t *base, uint8_t offset)
 {
-	return REG32((uint32_t) ((uint8_t *)base + offset));
+	return REG32((uint32_t)((uint8_t *)base + offset));
 }
 
-static inline uint8_t i2c_read_byte(uint32_t *addr, uint8_t reg,
-					  uint8_t offset)
+static inline uint8_t i2c_read_byte(uint32_t *addr, uint8_t reg, uint8_t offset)
 {
 	uint32_t ret = i2c_mmio_read(addr, reg) >> offset;
 
@@ -129,7 +115,6 @@ static inline uint8_t i2c_read_byte(uint32_t *addr, uint8_t reg,
 static void i2c_intr_switch(uint32_t *base, int mode)
 {
 	switch (mode) {
-
 	case ENABLE_WRITE_INT:
 		i2c_mmio_write(base, IC_INTR_MASK, IC_INTR_WRITE_MASK_VAL);
 		break;
@@ -157,8 +142,8 @@ static void i2c_intr_switch(uint32_t *base, int mode)
 	}
 }
 
-static void i2c_init_transaction(struct i2c_context *ctx,
-				 uint16_t addr, uint8_t flags)
+static void i2c_init_transaction(struct i2c_context *ctx, uint16_t addr,
+				 uint8_t flags)
 {
 	uint32_t con_value;
 	uint32_t *base = ctx->base;
@@ -169,64 +154,64 @@ static void i2c_init_transaction(struct i2c_context *ctx,
 	i2c_intr_switch(base, DISABLE_INT);
 
 	i2c_mmio_write(base, IC_ENABLE, IC_ENABLE_DISABLE);
-	i2c_mmio_write(base, IC_TAR, (addr << IC_TAR_OFFSET) |
-			TAR_SPECIAL_VAL | IC_10BITADDR_MASTER_VAL);
+	i2c_mmio_write(base, IC_TAR,
+		       (addr << IC_TAR_OFFSET) | TAR_SPECIAL_VAL |
+			       IC_10BITADDR_MASTER_VAL);
 
 	/* set Clock SCL Count */
 	switch (ctx->speed) {
-
 	case I2C_SPEED_100KHZ:
 		i2c_mmio_write(base, IC_SS_SCL_HCNT,
-				NS_2_COUNTERS(bus_info->std_speed.hcnt,
+			       NS_2_COUNTERS(bus_info->std_speed.hcnt,
 					     clk_in_val));
 		i2c_mmio_write(base, IC_SS_SCL_LCNT,
-				NS_2_COUNTERS(bus_info->std_speed.lcnt,
+			       NS_2_COUNTERS(bus_info->std_speed.lcnt,
 					     clk_in_val));
 		i2c_mmio_write(base, IC_SDA_HOLD,
-				NS_2_COUNTERS(bus_info->std_speed.sda_hold,
+			       NS_2_COUNTERS(bus_info->std_speed.sda_hold,
 					     clk_in_val));
 		break;
 
 	case I2C_SPEED_400KHZ:
 		i2c_mmio_write(base, IC_FS_SCL_HCNT,
-				NS_2_COUNTERS(bus_info->fast_speed.hcnt,
+			       NS_2_COUNTERS(bus_info->fast_speed.hcnt,
 					     clk_in_val));
 		i2c_mmio_write(base, IC_FS_SCL_LCNT,
-				NS_2_COUNTERS(bus_info->fast_speed.lcnt,
+			       NS_2_COUNTERS(bus_info->fast_speed.lcnt,
 					     clk_in_val));
 		i2c_mmio_write(base, IC_SDA_HOLD,
-				NS_2_COUNTERS(bus_info->fast_speed.sda_hold,
+			       NS_2_COUNTERS(bus_info->fast_speed.sda_hold,
 					     clk_in_val));
 		break;
 
 	case I2C_SPEED_1MHZ:
 		i2c_mmio_write(base, IC_FS_SCL_HCNT,
-				NS_2_COUNTERS(bus_info->fast_plus_speed.hcnt,
+			       NS_2_COUNTERS(bus_info->fast_plus_speed.hcnt,
 					     clk_in_val));
 		i2c_mmio_write(base, IC_FS_SCL_LCNT,
-				NS_2_COUNTERS(bus_info->fast_plus_speed.lcnt,
+			       NS_2_COUNTERS(bus_info->fast_plus_speed.lcnt,
 					     clk_in_val));
 		i2c_mmio_write(base, IC_SDA_HOLD,
-				NS_2_COUNTERS(bus_info->fast_plus_speed.sda_hold,
+			       NS_2_COUNTERS(bus_info->fast_plus_speed.sda_hold,
 					     clk_in_val));
 		break;
 
 	case I2C_SPEED_3M4HZ:
 		i2c_mmio_write(base, IC_HS_SCL_HCNT,
-				NS_2_COUNTERS(bus_info->high_speed.hcnt,
+			       NS_2_COUNTERS(bus_info->high_speed.hcnt,
 					     clk_in_val));
 		i2c_mmio_write(base, IC_HS_SCL_LCNT,
-				NS_2_COUNTERS(bus_info->high_speed.lcnt,
+			       NS_2_COUNTERS(bus_info->high_speed.lcnt,
 					     clk_in_val));
 		i2c_mmio_write(base, IC_SDA_HOLD,
-				NS_2_COUNTERS(bus_info->high_speed.sda_hold,
+			       NS_2_COUNTERS(bus_info->high_speed.sda_hold,
 					     clk_in_val));
 
 		i2c_mmio_write(base, IC_FS_SCL_HCNT,
-				NS_2_COUNTERS(bus_info->fast_speed.hcnt,
+			       NS_2_COUNTERS(bus_info->fast_speed.hcnt,
 					     clk_in_val));
 		i2c_mmio_write(base, IC_FS_SCL_LCNT,
-				NS_2_COUNTERS(bus_info->fast_speed.lcnt,
+			       NS_2_COUNTERS(bus_info->fast_speed.lcnt,
 					     clk_in_val));
 		break;
 
@@ -248,15 +233,13 @@ static void i2c_init_transaction(struct i2c_context *ctx,
 	i2c_mmio_write(base, IC_ENABLE, IC_ENABLE_ENABLE);
 }
 
-static void i2c_write_buffer(uint32_t *base, uint8_t len,
-			     const uint8_t *buffer, ssize_t *cur_index,
-			     ssize_t total_len)
+static void i2c_write_buffer(uint32_t *base, uint8_t len, const uint8_t *buffer,
+			     ssize_t *cur_index, ssize_t total_len)
 {
 	int i;
 	uint16_t out;
 
 	for (i = 0; i < len; i++) {
-
 		++(*cur_index);
 		out = (buffer[i] << DATA_CMD_DAT_OFFSET) | DATA_CMD_WRITE_VAL;
 
@@ -270,7 +253,7 @@ static void i2c_write_buffer(uint32_t *base, uint8_t len,
 }
 
 static void i2c_write_read_commands(uint32_t *base, uint8_t len, int more_data,
-					unsigned restart_flag)
+				    unsigned restart_flag)
 {
 	/* this routine just set RX FIFO's control bit(s),
 	 * READ command or RESTART */
@@ -293,9 +276,8 @@ static void i2c_write_read_commands(uint32_t *base, uint8_t len, int more_data,
 	}
 }
 
-int chip_i2c_xfer(const int port, const uint16_t addr_flags,
-		  const uint8_t *out, int out_size,
-		  uint8_t *in, int in_size, int flags)
+int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out,
+		  int out_size, uint8_t *in, int in_size, int flags)
 {
 	int i;
 	ssize_t total_len;
@@ -333,8 +315,8 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags,
 
 	/* Write W data */
 	if (out_size)
-		i2c_write_buffer(ctx->base, out_size, out,
-				&curr_index, total_len);
+		i2c_write_buffer(ctx->base, out_size, out, &curr_index,
+				 total_len);
 
 	/* Wait here until Tx is completed so that FIFO becomes empty.
 	 * This is optimized for smaller Tx data size.
@@ -344,10 +326,8 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags,
 	 * */
 	expire_ts = __hw_clock_source_read() + I2C_TX_FLUSH_TIMEOUT_USEC;
 	if (in_size > (ISH_I2C_FIFO_SIZE - out_size)) {
-
 		while ((i2c_mmio_read(ctx->base, IC_STATUS) &
 			BIT(IC_STATUS_TFE)) == 0) {
-
 			if (__hw_clock_source_read() >= expire_ts) {
 				ctx->error_flag = 1;
 				break;
@@ -358,7 +338,7 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags,
 
 	begin_indx = 0;
 	while (in_size) {
-		int rd_size;  /* read size for on i2c transaction */
+		int rd_size; /* read size for on i2c transaction */
 
 		/*
 		 * check if in_size > ISH_I2C_FIFO_SIZE, then try to read
@@ -383,11 +363,11 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags,
 		 * set R commands bit, start to read
 		 */
 		i2c_write_read_commands(ctx->base, rd_size, in_size,
-				(begin_indx == 0) && (repeat_start != 0));
-
+					(begin_indx == 0) &&
+						(repeat_start != 0));
 
 		/* need timeout in case no ACK from peripheral */
-		task_wait_event_mask(TASK_EVENT_I2C_IDLE, 2*MSEC);
+		task_wait_event_mask(TASK_EVENT_I2C_IDLE, 2 * MSEC);
 
 		if (ctx->interrupts & M_TX_ABRT) {
 			ctx->error_flag = 1;
@@ -396,8 +376,7 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags,
 
 		/* read data */
 		for (i = begin_indx; i < begin_indx + rd_size; i++)
-			in[i] = i2c_read_byte(ctx->base,
-					IC_DATA_CMD, 0);
+			in[i] = i2c_read_byte(ctx->base, IC_DATA_CMD, 0);
 
 		begin_indx += rd_size;
 	} /* while (in_size) */
@@ -411,7 +390,6 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags,
 	while ((i2c_mmio_read(ctx->base, IC_STATUS) &
 		(BIT(IC_STATUS_MASTER_ACTIVITY) | BIT(IC_STATUS_TFE))) !=
 	       BIT(IC_STATUS_TFE)) {
-
 		if (__hw_clock_source_read() >= expire_ts) {
 			ctx->error_flag = 1;
 			break;
@@ -432,12 +410,12 @@ static void i2c_interrupt_handler(struct i2c_context *ctx)
 	uint32_t raw_intr;
 
 	if (IS_ENABLED(INTR_DEBUG))
-		raw_intr = 0x0000FFFF & i2c_mmio_read(ctx->base,
-						      IC_RAW_INTR_STAT);
+		raw_intr = 0x0000FFFF &
+			   i2c_mmio_read(ctx->base, IC_RAW_INTR_STAT);
 
 	/* check interrupts */
 	ctx->interrupts = i2c_mmio_read(ctx->base, IC_INTR_STAT);
-	ctx->reason = (uint16_t) i2c_mmio_read(ctx->base, IC_TX_ABRT_SOURCE);
+	ctx->reason = (uint16_t)i2c_mmio_read(ctx->base, IC_TX_ABRT_SOURCE);
 
 	if (IS_ENABLED(INTR_DEBUG))
 		CPRINTS("INTR_STAT = 0x%04x, TX_ABORT_SRC = 0x%04x, "
@@ -467,9 +445,8 @@ static void i2c_isr_bus2(void)
 }
 DECLARE_IRQ(ISH_I2C2_IRQ, i2c_isr_bus2);
 
-static void  i2c_config_speed(struct i2c_context *ctx, int kbps)
+static void i2c_config_speed(struct i2c_context *ctx, int kbps)
 {
-
 	if (kbps > 1000)
 		ctx->speed = I2C_SPEED_3M4HZ;
 	else if (kbps > 400)
@@ -478,7 +455,6 @@ static void  i2c_config_speed(struct i2c_context *ctx, int kbps)
 		ctx->speed = I2C_SPEED_400KHZ;
 	else
 		ctx->speed = I2C_SPEED_100KHZ;
-
 }
 
 static void i2c_init_hardware(struct i2c_context *ctx)
@@ -486,8 +462,8 @@ static void i2c_init_hardware(struct i2c_context *ctx)
 	static const uint8_t speed_val_arr[] = {
 		[I2C_SPEED_100KHZ] = STD_SPEED_VAL,
 		[I2C_SPEED_400KHZ] = FAST_SPEED_VAL,
-		[I2C_SPEED_1MHZ]   = FAST_SPEED_VAL,
-		[I2C_SPEED_3M4HZ]  = HIGH_SPEED_VAL,
+		[I2C_SPEED_1MHZ] = FAST_SPEED_VAL,
+		[I2C_SPEED_3M4HZ] = HIGH_SPEED_VAL,
 	};
 
 	uint32_t *base = ctx->base;
@@ -495,19 +471,20 @@ static void i2c_init_hardware(struct i2c_context *ctx)
 	/* disable interrupts */
 	i2c_intr_switch(base, DISABLE_INT);
 	i2c_mmio_write(base, IC_ENABLE, IC_ENABLE_DISABLE);
-	i2c_mmio_write(base, IC_CON, (MASTER_MODE_VAL
-				| speed_val_arr[ctx->speed]
-				| IC_RESTART_EN_VAL
-				| IC_SLAVE_DISABLE_VAL));
+	i2c_mmio_write(base, IC_CON,
+		       (MASTER_MODE_VAL | speed_val_arr[ctx->speed] |
+			IC_RESTART_EN_VAL | IC_SLAVE_DISABLE_VAL));
 
 	i2c_mmio_write(base, IC_FS_SPKLEN, spkln[bus_freq[ctx->bus]]);
 	i2c_mmio_write(base, IC_HS_SPKLEN, spkln[bus_freq[ctx->bus]]);
 
 	/* get RX_FIFO and TX_FIFO depth */
-	ctx->max_rx_depth = i2c_read_byte(base, IC_COMP_PARAM_1,
-					RX_BUFFER_DEPTH_OFFSET) + 1;
-	ctx->max_tx_depth = i2c_read_byte(base, IC_COMP_PARAM_1,
-					TX_BUFFER_DEPTH_OFFSET) + 1;
+	ctx->max_rx_depth =
+		i2c_read_byte(base, IC_COMP_PARAM_1, RX_BUFFER_DEPTH_OFFSET) +
+		1;
+	ctx->max_tx_depth =
+		i2c_read_byte(base, IC_COMP_PARAM_1, TX_BUFFER_DEPTH_OFFSET) +
+		1;
 }
 
 static void i2c_initial_board_config(struct i2c_context *ctx)
diff --git a/chip/ish/ipc_heci.c b/chip/ish/ipc_heci.c
index 9553e195c4..1fd81e3d3f 100644
--- a/chip/ish/ipc_heci.c
+++ b/chip/ish/ipc_heci.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,6 +23,7 @@
  *  - Doorbell Clear Status Register (DB CSR)
  */
 
+#include "builtin/assert.h"
 #include "registers.h"
 #include "console.h"
 #include "task.h"
@@ -34,8 +35,8 @@
 #include "hwtimer.h"
 
 #define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_LPC, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_LPC, format, ##args)
 
 /*
  * comminucation protocol is defined in Linux Documentation
@@ -44,57 +45,55 @@
 
 /* MNG commands */
 /* The ipc_mng_task manages IPC link. It should be the highest priority */
-#define MNG_RX_CMPL_ENABLE              0
-#define MNG_RX_CMPL_DISABLE             1
-#define MNG_RX_CMPL_INDICATION          2
-#define MNG_RESET_NOTIFY                3
-#define MNG_RESET_NOTIFY_ACK            4
-#define MNG_SYNC_FW_CLOCK               5
-#define MNG_ILLEGAL_CMD                 0xFF
+#define MNG_RX_CMPL_ENABLE 0
+#define MNG_RX_CMPL_DISABLE 1
+#define MNG_RX_CMPL_INDICATION 2
+#define MNG_RESET_NOTIFY 3
+#define MNG_RESET_NOTIFY_ACK 4
+#define MNG_SYNC_FW_CLOCK 5
+#define MNG_ILLEGAL_CMD 0xFF
 
 /* Doorbell */
-#define IPC_DB_MSG_LENGTH_FIELD		0x3FF
-#define IPC_DB_MSG_LENGTH_SHIFT		0
+#define IPC_DB_MSG_LENGTH_FIELD 0x3FF
+#define IPC_DB_MSG_LENGTH_SHIFT 0
 #define IPC_DB_MSG_LENGTH_MASK \
-	  (IPC_DB_MSG_LENGTH_FIELD << IPC_DB_MSG_LENGTH_SHIFT)
+	(IPC_DB_MSG_LENGTH_FIELD << IPC_DB_MSG_LENGTH_SHIFT)
 
-#define IPC_DB_PROTOCOL_FIELD		0x0F
-#define IPC_DB_PROTOCOL_SHIFT		10
+#define IPC_DB_PROTOCOL_FIELD 0x0F
+#define IPC_DB_PROTOCOL_SHIFT 10
 #define IPC_DB_PROTOCOL_MASK (IPC_DB_PROTOCOL_FIELD << IPC_DB_PROTOCOL_SHIFT)
 
-#define IPC_DB_CMD_FIELD		0x0F
-#define IPC_DB_CMD_SHIFT		16
-#define IPC_DB_CMD_MASK			(IPC_DB_CMD_FIELD << IPC_DB_CMD_SHIFT)
+#define IPC_DB_CMD_FIELD 0x0F
+#define IPC_DB_CMD_SHIFT 16
+#define IPC_DB_CMD_MASK (IPC_DB_CMD_FIELD << IPC_DB_CMD_SHIFT)
 
-#define IPC_DB_BUSY_SHIFT		31
-#define IPC_DB_BUSY_MASK		BIT(IPC_DB_BUSY_SHIFT)
+#define IPC_DB_BUSY_SHIFT 31
+#define IPC_DB_BUSY_MASK BIT(IPC_DB_BUSY_SHIFT)
 
 #define IPC_DB_MSG_LENGTH(drbl) \
-	  (((drbl) & IPC_DB_MSG_LENGTH_MASK) >> IPC_DB_MSG_LENGTH_SHIFT)
+	(((drbl)&IPC_DB_MSG_LENGTH_MASK) >> IPC_DB_MSG_LENGTH_SHIFT)
 #define IPC_DB_PROTOCOL(drbl) \
-	  (((drbl) & IPC_DB_PROTOCOL_MASK) >> IPC_DB_PROTOCOL_SHIFT)
-#define IPC_DB_CMD(drbl) \
-	  (((drbl) & IPC_DB_CMD_MASK) >> IPC_DB_CMD_SHIFT)
-#define IPC_DB_BUSY(drbl)		(!!((drbl) & IPC_DB_BUSY_MASK))
+	(((drbl)&IPC_DB_PROTOCOL_MASK) >> IPC_DB_PROTOCOL_SHIFT)
+#define IPC_DB_CMD(drbl) (((drbl)&IPC_DB_CMD_MASK) >> IPC_DB_CMD_SHIFT)
+#define IPC_DB_BUSY(drbl) (!!((drbl)&IPC_DB_BUSY_MASK))
 
-#define IPC_BUILD_DB(length, proto, cmd, busy) \
+#define IPC_BUILD_DB(length, proto, cmd, busy)                         \
 	(((busy) << IPC_DB_BUSY_SHIFT) | ((cmd) << IPC_DB_CMD_SHIFT) | \
-	((proto) << IPC_DB_PROTOCOL_SHIFT) | \
-		((length) << IPC_DB_MSG_LENGTH_SHIFT))
+	 ((proto) << IPC_DB_PROTOCOL_SHIFT) |                          \
+	 ((length) << IPC_DB_MSG_LENGTH_SHIFT))
 
 #define IPC_BUILD_MNG_DB(cmd, length) \
 	IPC_BUILD_DB(length, IPC_PROTOCOL_MNG, cmd, 1)
 
-#define IPC_BUILD_HECI_DB(length) \
-	IPC_BUILD_DB(length, IPC_PROTOCOL_HECI, 0, 1)
+#define IPC_BUILD_HECI_DB(length) IPC_BUILD_DB(length, IPC_PROTOCOL_HECI, 0, 1)
 
-#define IPC_MSG_MAX_SIZE		0x80
-#define IPC_HOST_MSG_QUEUE_SIZE		8
-#define IPC_PMC_MSG_QUEUE_SIZE		2
+#define IPC_MSG_MAX_SIZE 0x80
+#define IPC_HOST_MSG_QUEUE_SIZE 8
+#define IPC_PMC_MSG_QUEUE_SIZE 2
 
-#define IPC_HANDLE_PEER_ID_SHIFT	4
-#define IPC_HANDLE_PROTOCOL_SHIFT	0
-#define IPC_HANDLE_PROTOCOL_MASK	0x0F
+#define IPC_HANDLE_PEER_ID_SHIFT 4
+#define IPC_HANDLE_PROTOCOL_SHIFT 0
+#define IPC_HANDLE_PROTOCOL_MASK 0x0F
 #define IPC_BUILD_HANDLE(peer_id, protocol) \
 	((ipc_handle_t)(((peer_id) << IPC_HANDLE_PEER_ID_SHIFT) | (protocol)))
 #define IPC_BUILD_MNG_HANDLE(peer_id) \
@@ -103,10 +102,10 @@
 #define IPC_HANDLE_PEER_ID(handle) \
 	((uint32_t)(handle) >> IPC_HANDLE_PEER_ID_SHIFT)
 #define IPC_HANDLE_PROTOCOL(handle) \
-	((uint32_t)(handle) & IPC_HANDLE_PROTOCOL_MASK)
-#define IPC_IS_VALID_HANDLE(handle) \
+	((uint32_t)(handle)&IPC_HANDLE_PROTOCOL_MASK)
+#define IPC_IS_VALID_HANDLE(handle)                      \
 	(IPC_HANDLE_PEER_ID(handle) < IPC_PEERS_COUNT && \
-	    IPC_HANDLE_PROTOCOL(handle) < IPC_PROTOCOL_COUNT)
+	 IPC_HANDLE_PROTOCOL(handle) < IPC_PROTOCOL_COUNT)
 
 struct ipc_msg {
 	uint32_t drbl;
@@ -191,21 +190,20 @@ static inline void ipc_disable_pimr_db_interrupt(const struct ipc_if_ctx *ctx)
 	IPC_PIMR &= ~ctx->pimr_2ish_bit;
 }
 
-static inline void ipc_enable_pimr_clearing_interrupt(
-						const struct ipc_if_ctx *ctx)
+static inline void
+ipc_enable_pimr_clearing_interrupt(const struct ipc_if_ctx *ctx)
 {
 	IPC_PIMR |= ctx->pimr_2host_clearing_bit;
 }
 
-static inline void ipc_disable_pimr_clearing_interrupt(
-						const struct ipc_if_ctx *ctx)
+static inline void
+ipc_disable_pimr_clearing_interrupt(const struct ipc_if_ctx *ctx)
 {
 	IPC_PIMR &= ~ctx->pimr_2host_clearing_bit;
 }
 
 static void write_payload_and_ring_drbl(const struct ipc_if_ctx *ctx,
-					uint32_t drbl,
-					const uint8_t *payload,
+					uint32_t drbl, const uint8_t *payload,
 					size_t payload_size)
 {
 	memcpy((void *)(ctx->out_msg_reg), payload, payload_size);
@@ -280,7 +278,7 @@ static int ipc_send_reset_notify(const ipc_handle_t handle)
 
 static int ipc_send_cmpl_indication(struct ipc_if_ctx *ctx)
 {
-	struct ipc_msg msg = {0};
+	struct ipc_msg msg = { 0 };
 
 	msg.drbl = IPC_BUILD_MNG_DB(MNG_RX_CMPL_INDICATION, 0);
 	ipc_write_raw(ctx, msg.drbl, msg.payload, IPC_DB_MSG_LENGTH(msg.drbl));
@@ -289,8 +287,8 @@ static int ipc_send_cmpl_indication(struct ipc_if_ctx *ctx)
 }
 
 static int ipc_get_protocol_data(const struct ipc_if_ctx *ctx,
-				 const uint32_t protocol,
-				 uint8_t *buf, const size_t buf_size)
+				 const uint32_t protocol, uint8_t *buf,
+				 const size_t buf_size)
 {
 	int len = 0, payload_size;
 	uint8_t *src = NULL, *dest = NULL;
@@ -325,9 +323,8 @@ static int ipc_get_protocol_data(const struct ipc_if_ctx *ctx,
 	}
 
 	if (IS_ENABLED(IPC_HECI_DEBUG))
-		CPRINTF("ipc p=%d, db=0x%0x, payload_size=%d\n",
-			protocol, drbl_val,
-			IPC_DB_MSG_LENGTH(drbl_val));
+		CPRINTF("ipc p=%d, db=0x%0x, payload_size=%d\n", protocol,
+			drbl_val, IPC_DB_MSG_LENGTH(drbl_val));
 
 	switch (protocol) {
 	case IPC_PROTOCOL_HECI:
@@ -340,7 +337,7 @@ static int ipc_get_protocol_data(const struct ipc_if_ctx *ctx,
 		msg->drbl = drbl_val;
 		dest = msg->payload;
 		break;
-	default :
+	default:
 		break;
 	}
 
@@ -544,13 +541,11 @@ int ipc_write_timestamp(const ipc_handle_t handle, const void *buf,
 }
 
 ipc_handle_t ipc_open(const enum ipc_peer_id peer_id,
-		      const enum ipc_protocol protocol,
-		      const uint32_t event)
+		      const enum ipc_protocol protocol, const uint32_t event)
 {
 	struct ipc_if_ctx *ctx;
 
-	if (protocol >= IPC_PROTOCOL_COUNT ||
-	    peer_id >= IPC_PEERS_COUNT)
+	if (protocol >= IPC_PROTOCOL_COUNT || peer_id >= IPC_PEERS_COUNT)
 		return IPC_INVALID_HANDLE;
 
 	ctx = ipc_get_if_ctx(peer_id);
@@ -564,9 +559,9 @@ ipc_handle_t ipc_open(const enum ipc_peer_id peer_id,
 	ctx->msg_events[protocol].enabled = 1;
 	ctx->msg_events[protocol].event = event;
 
-	 /* For HECI protocol, set HECI UP status when IPC link is ready */
-	if (peer_id == IPC_PEER_ID_HOST &&
-	    protocol == IPC_PROTOCOL_HECI && ish_fwst_is_ilup_set())
+	/* For HECI protocol, set HECI UP status when IPC link is ready */
+	if (peer_id == IPC_PEER_ID_HOST && protocol == IPC_PROTOCOL_HECI &&
+	    ish_fwst_is_ilup_set())
 		ish_fwst_set_hup();
 
 	if (ctx->initialized == 0) {
@@ -686,7 +681,7 @@ int ipc_read(const ipc_handle_t handle, void *buf, const size_t buf_size,
 }
 
 /* event flag for MNG msg */
-#define EVENT_FLAG_BIT_MNG_MSG			TASK_EVENT_CUSTOM_BIT(0)
+#define EVENT_FLAG_BIT_MNG_MSG TASK_EVENT_CUSTOM_BIT(0)
 
 /*
  * This task handles MNG messages
diff --git a/chip/ish/ipc_heci.h b/chip/ish/ipc_heci.h
index 183e6a2c6b..f9372aefa3 100644
--- a/chip/ish/ipc_heci.h
+++ b/chip/ish/ipc_heci.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,16 +8,16 @@
 #define __IPC_HECI_H
 
 enum IPC_ERR {
-	IPC_ERR_IPC_IS_NOT_READY	= EC_ERROR_INTERNAL_FIRST + 0,
-	IPC_ERR_TOO_SMALL_BUFFER	= EC_ERROR_INTERNAL_FIRST + 1,
-	IPC_ERR_TX_QUEUE_FULL		= EC_ERROR_INTERNAL_FIRST + 2,
-	IPC_ERR_INVALID_TASK		= EC_ERROR_INTERNAL_FIRST + 3,
-	IPC_ERR_MSG_NOT_AVAILABLE	= EC_ERROR_INTERNAL_FIRST + 4,
-	IPC_ERR_INVALID_MSG		= EC_ERROR_INTERNAL_FIRST + 5,
+	IPC_ERR_IPC_IS_NOT_READY = EC_ERROR_INTERNAL_FIRST + 0,
+	IPC_ERR_TOO_SMALL_BUFFER = EC_ERROR_INTERNAL_FIRST + 1,
+	IPC_ERR_TX_QUEUE_FULL = EC_ERROR_INTERNAL_FIRST + 2,
+	IPC_ERR_INVALID_TASK = EC_ERROR_INTERNAL_FIRST + 3,
+	IPC_ERR_MSG_NOT_AVAILABLE = EC_ERROR_INTERNAL_FIRST + 4,
+	IPC_ERR_INVALID_MSG = EC_ERROR_INTERNAL_FIRST + 5,
 };
 
 enum ipc_peer_id {
-	IPC_PEER_ID_HOST	= 0, /* x64 host */
+	IPC_PEER_ID_HOST = 0, /* x64 host */
 #if 0 /* other peers are not implemented yet */
 	IPC_PEER_ID_PMC		= 1, /* Power Management Controller */
 	IPC_PEER_ID_CSME	= 2, /* Converged Security Management Engine */
@@ -33,11 +33,11 @@ enum ipc_peer_id {
 BUILD_ASSERT(IPC_PEERS_COUNT <= 0x0F);
 
 enum ipc_protocol {
-	IPC_PROTOCOL_BOOT = 0,	/* Not supported */
-	IPC_PROTOCOL_HECI,	/* Host Embedded Controller Interface */
-	IPC_PROTOCOL_MCTP,	/* not supported */
-	IPC_PROTOCOL_MNG,	/* Management protocol */
-	IPC_PROTOCOL_ECP,	/* EC Protocol. not supported */
+	IPC_PROTOCOL_BOOT = 0, /* Not supported */
+	IPC_PROTOCOL_HECI, /* Host Embedded Controller Interface */
+	IPC_PROTOCOL_MCTP, /* not supported */
+	IPC_PROTOCOL_MNG, /* Management protocol */
+	IPC_PROTOCOL_ECP, /* EC Protocol. not supported */
 	IPC_PROTOCOL_COUNT
 };
 /*
@@ -46,10 +46,10 @@ enum ipc_protocol {
  */
 BUILD_ASSERT(IPC_PROTOCOL_COUNT <= 0x0F);
 
-typedef void *				ipc_handle_t;
+typedef void *ipc_handle_t;
 
-#define IPC_MAX_PAYLOAD_SIZE		128
-#define IPC_INVALID_HANDLE		NULL
+#define IPC_MAX_PAYLOAD_SIZE 128
+#define IPC_INVALID_HANDLE NULL
 
 /*
  * Open ipc channel
@@ -61,8 +61,7 @@ typedef void *				ipc_handle_t;
  * @return		ipc handle or IPC_INVALID_HANDLE if there's error
  */
 ipc_handle_t ipc_open(const enum ipc_peer_id peer_id,
-		      const enum ipc_protocol protocol,
-		      const uint32_t event);
+		      const enum ipc_protocol protocol, const uint32_t event);
 void ipc_close(const ipc_handle_t handle);
 
 /*
@@ -74,10 +73,10 @@ void ipc_close(const ipc_handle_t handle);
  *			if > 0, wait for the specified microsecond duration time
  */
 int ipc_read(const ipc_handle_t handle, void *buf, const size_t buf_size,
-             int timeout_us);
+	     int timeout_us);
 
 /* Write message to ipc channel. */
 int ipc_write_timestamp(const ipc_handle_t handle, const void *buf,
-	      const size_t buf_size, uint32_t *timestamp);
+			const size_t buf_size, uint32_t *timestamp);
 
 #endif /* __IPC_HECI_H */
diff --git a/chip/ish/ish_dma.h b/chip/ish/ish_dma.h
index 2c76c7d319..fb9c4f4f06 100644
--- a/chip/ish/ish_dma.h
+++ b/chip/ish/ish_dma.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/ish/ish_fwst.h b/chip/ish/ish_fwst.h
index c114db3241..999546ca34 100644
--- a/chip/ish/ish_fwst.h
+++ b/chip/ish/ish_fwst.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,84 +17,84 @@
  * IPC link is up(ready)
  * IPC can be used by other protocols
  */
-#define IPC_ISH_FWSTS_ILUP_FIELD		0x01
-#define IPC_ISH_FWSTS_ILUP_SHIFT		0
-#define IPC_ISH_FWSTS_ILUP_MASK	\
-	  (IPC_ISH_FWSTS_ILUP_FIELD << IPC_ISH_FWSTS_ILUP_SHIFT)
+#define IPC_ISH_FWSTS_ILUP_FIELD 0x01
+#define IPC_ISH_FWSTS_ILUP_SHIFT 0
+#define IPC_ISH_FWSTS_ILUP_MASK \
+	(IPC_ISH_FWSTS_ILUP_FIELD << IPC_ISH_FWSTS_ILUP_SHIFT)
 
 /*
  * HECI layer is up(ready)
  */
-#define IPC_ISH_FWSTS_HUP_FIELD			0x01
-#define IPC_ISH_FWSTS_HUP_SHIFT			1
+#define IPC_ISH_FWSTS_HUP_FIELD 0x01
+#define IPC_ISH_FWSTS_HUP_SHIFT 1
 #define IPC_ISH_FWSTS_HUP_MASK \
-	  (IPC_ISH_FWSTS_HUP_FIELD << IPC_ISH_FWSTS_HUP_SHIFT)
+	(IPC_ISH_FWSTS_HUP_FIELD << IPC_ISH_FWSTS_HUP_SHIFT)
 
 /*
  * ISH FW reason reason
  */
-#define IPC_ISH_FWSTS_FAIL_REASON_FIELD		0x0F
-#define IPC_ISH_FWSTS_FAIL_REASON_SHIFT		2
+#define IPC_ISH_FWSTS_FAIL_REASON_FIELD 0x0F
+#define IPC_ISH_FWSTS_FAIL_REASON_SHIFT 2
 #define IPC_ISH_FWSTS_FAIL_REASON_MASK \
-	  (IPC_ISH_FWSTS_FAIL_REASON_FIELD << IPC_ISH_FWSTS_FAIL_REASON_SHIFT)
+	(IPC_ISH_FWSTS_FAIL_REASON_FIELD << IPC_ISH_FWSTS_FAIL_REASON_SHIFT)
 
 /*
  * ISH FW reset ID
  */
-#define IPC_ISH_FWSTS_RESET_ID_FIELD		0x0F
-#define IPC_ISH_FWSTS_RESET_ID_SHIFT		8
+#define IPC_ISH_FWSTS_RESET_ID_FIELD 0x0F
+#define IPC_ISH_FWSTS_RESET_ID_SHIFT 8
 #define IPC_ISH_FWSTS_RESET_ID_MASK \
-	  (IPC_ISH_FWSTS_RESET_ID_FIELD << IPC_ISH_FWSTS_RESET_ID_SHIFT)
+	(IPC_ISH_FWSTS_RESET_ID_FIELD << IPC_ISH_FWSTS_RESET_ID_SHIFT)
 
 /*
  * ISH FW status type
  */
 enum {
-	FWSTS_AFTER_RESET               = 0,
-	FWSTS_WAIT_FOR_HOST             = 4,
-	FWSTS_START_KERNEL_DMA          = 5,
-	FWSTS_FW_IS_RUNNING             = 7,
-	FWSTS_SENSOR_APP_LOADED         = 8,
-	FWSTS_SENSOR_APP_RUNNING        = 15
+	FWSTS_AFTER_RESET = 0,
+	FWSTS_WAIT_FOR_HOST = 4,
+	FWSTS_START_KERNEL_DMA = 5,
+	FWSTS_FW_IS_RUNNING = 7,
+	FWSTS_SENSOR_APP_LOADED = 8,
+	FWSTS_SENSOR_APP_RUNNING = 15
 };
 
 /*
  * General ISH FW status
  */
-#define IPC_ISH_FWSTS_FW_STATUS_FIELD		0x0F
-#define IPC_ISH_FWSTS_FW_STATUS_SHIFT		12
+#define IPC_ISH_FWSTS_FW_STATUS_FIELD 0x0F
+#define IPC_ISH_FWSTS_FW_STATUS_SHIFT 12
 #define IPC_ISH_FWSTS_FW_STATUS_MASK \
-	  (IPC_ISH_FWSTS_FW_STATUS_FIELD << IPC_ISH_FWSTS_FW_STATUS_SHIFT)
+	(IPC_ISH_FWSTS_FW_STATUS_FIELD << IPC_ISH_FWSTS_FW_STATUS_SHIFT)
 
-#define IPC_ISH_FWSTS_DMA0_IN_USE_FIELD		0x01
-#define IPC_ISH_FWSTS_DMA0_IN_USE_SHIFT		16
+#define IPC_ISH_FWSTS_DMA0_IN_USE_FIELD 0x01
+#define IPC_ISH_FWSTS_DMA0_IN_USE_SHIFT 16
 #define IPC_ISH_FWSTS_DMA0_IN_USE_MASK \
-	  (IPC_ISH_FWSTS_DMA0_IN_USE_FIELD << IPC_ISH_FWSTS_DMA0_IN_USE_SHIFT)
+	(IPC_ISH_FWSTS_DMA0_IN_USE_FIELD << IPC_ISH_FWSTS_DMA0_IN_USE_SHIFT)
 
-#define IPC_ISH_FWSTS_DMA1_IN_USE_FIELD		0x01
-#define IPC_ISH_FWSTS_DMA1_IN_USE_SHIFT		17
+#define IPC_ISH_FWSTS_DMA1_IN_USE_FIELD 0x01
+#define IPC_ISH_FWSTS_DMA1_IN_USE_SHIFT 17
 #define IPC_ISH_FWSTS_DMA1_IN_USE_MASK \
-	  (IPC_ISH_FWSTS_DMA1_IN_USE_FIELD << IPC_ISH_FWSTS_DMA1_IN_USE_SHIFT)
+	(IPC_ISH_FWSTS_DMA1_IN_USE_FIELD << IPC_ISH_FWSTS_DMA1_IN_USE_SHIFT)
 
-#define IPC_ISH_FWSTS_DMA2_IN_USE_FIELD		0x01
-#define IPC_ISH_FWSTS_DMA2_IN_USE_SHIFT		18
+#define IPC_ISH_FWSTS_DMA2_IN_USE_FIELD 0x01
+#define IPC_ISH_FWSTS_DMA2_IN_USE_SHIFT 18
 #define IPC_ISH_FWSTS_DMA2_IN_USE_MASK \
-	  (IPC_ISH_FWSTS_DMA2_IN_USE_FIELD << IPC_ISH_FWSTS_DMA2_IN_USE_SHIFT)
+	(IPC_ISH_FWSTS_DMA2_IN_USE_FIELD << IPC_ISH_FWSTS_DMA2_IN_USE_SHIFT)
 
-#define IPC_ISH_FWSTS_DMA3_IN_USE_FIELD		0x01
-#define IPC_ISH_FWSTS_DMA3_IN_USE_SHIFT		19
+#define IPC_ISH_FWSTS_DMA3_IN_USE_FIELD 0x01
+#define IPC_ISH_FWSTS_DMA3_IN_USE_SHIFT 19
 #define IPC_ISH_FWSTS_DMA3_IN_USE_MASK \
-	  (IPC_ISH_FWSTS_DMA3_IN_USE_FIELD << IPC_ISH_FWSTS_DMA3_IN_USE_SHIFT)
+	(IPC_ISH_FWSTS_DMA3_IN_USE_FIELD << IPC_ISH_FWSTS_DMA3_IN_USE_SHIFT)
 
-#define IPC_ISH_FWSTS_POWER_STATE_FIELD		0x0F
-#define IPC_ISH_FWSTS_POWER_STATE_SHIFT		20
+#define IPC_ISH_FWSTS_POWER_STATE_FIELD 0x0F
+#define IPC_ISH_FWSTS_POWER_STATE_SHIFT 20
 #define IPC_ISH_FWSTS_POWER_STATE_MASK \
-	  (IPC_ISH_FWSTS_POWER_STATE_FIELD << IPC_ISH_FWSTS_POWER_STATE_SHIFT)
+	(IPC_ISH_FWSTS_POWER_STATE_FIELD << IPC_ISH_FWSTS_POWER_STATE_SHIFT)
 
-#define IPC_ISH_FWSTS_AON_CHECK_FIELD		0x07
-#define IPC_ISH_FWSTS_AON_CHECK_SHIFT		24
+#define IPC_ISH_FWSTS_AON_CHECK_FIELD 0x07
+#define IPC_ISH_FWSTS_AON_CHECK_SHIFT 24
 #define IPC_ISH_FWSTS_AON_CHECK_MASK \
-	  (IPC_ISH_FWSTS_AON_CHECK_FIELD << IPC_ISH_FWSTS_AON_CHECK_SHIFT)
+	(IPC_ISH_FWSTS_AON_CHECK_FIELD << IPC_ISH_FWSTS_AON_CHECK_SHIFT)
 
 /* get ISH FW status register */
 static inline uint32_t ish_fwst_get(void)
@@ -105,7 +105,7 @@ static inline uint32_t ish_fwst_get(void)
 /* set IPC link up */
 static inline void ish_fwst_set_ilup(void)
 {
-	IPC_ISH_FWSTS |= (1<<IPC_ISH_FWSTS_ILUP_SHIFT);
+	IPC_ISH_FWSTS |= (1 << IPC_ISH_FWSTS_ILUP_SHIFT);
 }
 
 /* clear IPC link up */
@@ -123,7 +123,7 @@ static inline int ish_fwst_is_ilup_set(void)
 /* set HECI up */
 static inline void ish_fwst_set_hup(void)
 {
-	IPC_ISH_FWSTS |= (1<<IPC_ISH_FWSTS_HUP_SHIFT);
+	IPC_ISH_FWSTS |= (1 << IPC_ISH_FWSTS_HUP_SHIFT);
 }
 
 /* clear HECI up */
@@ -144,14 +144,14 @@ static inline void ish_fwst_set_fail_reason(uint32_t val)
 	uint32_t fwst = IPC_ISH_FWSTS;
 
 	IPC_ISH_FWSTS = (fwst & ~IPC_ISH_FWSTS_FAIL_REASON_MASK) |
-		(val << IPC_ISH_FWSTS_FAIL_REASON_SHIFT);
+			(val << IPC_ISH_FWSTS_FAIL_REASON_SHIFT);
 }
 
 /* get fw failure reason */
 static inline uint32_t ish_fwst_get_fail_reason(void)
 {
-	return (IPC_ISH_FWSTS & IPC_ISH_FWSTS_FAIL_REASON_MASK)
-		>> IPC_ISH_FWSTS_FAIL_REASON_SHIFT;
+	return (IPC_ISH_FWSTS & IPC_ISH_FWSTS_FAIL_REASON_MASK) >>
+	       IPC_ISH_FWSTS_FAIL_REASON_SHIFT;
 }
 
 /* set reset id */
@@ -160,14 +160,14 @@ static inline void ish_fwst_set_reset_id(uint32_t val)
 	uint32_t fwst = IPC_ISH_FWSTS;
 
 	IPC_ISH_FWSTS = (fwst & ~IPC_ISH_FWSTS_RESET_ID_MASK) |
-		(val << IPC_ISH_FWSTS_RESET_ID_SHIFT);
+			(val << IPC_ISH_FWSTS_RESET_ID_SHIFT);
 }
 
 /* get reset id */
 static inline uint32_t ish_fwst_get_reset_id(void)
 {
-	return (IPC_ISH_FWSTS & IPC_ISH_FWSTS_RESET_ID_MASK)
-		>> IPC_ISH_FWSTS_RESET_ID_SHIFT;
+	return (IPC_ISH_FWSTS & IPC_ISH_FWSTS_RESET_ID_MASK) >>
+	       IPC_ISH_FWSTS_RESET_ID_SHIFT;
 }
 
 /* set general fw status */
@@ -176,14 +176,14 @@ static inline void ish_fwst_set_fw_status(uint32_t val)
 	uint32_t fwst = IPC_ISH_FWSTS;
 
 	IPC_ISH_FWSTS = (fwst & ~IPC_ISH_FWSTS_FW_STATUS_MASK) |
-		(val << IPC_ISH_FWSTS_FW_STATUS_SHIFT);
+			(val << IPC_ISH_FWSTS_FW_STATUS_SHIFT);
 }
 
 /* get general fw status */
 static inline uint32_t ish_fwst_get_fw_status(void)
 {
-	return (IPC_ISH_FWSTS & IPC_ISH_FWSTS_FW_STATUS_MASK)
-		>> IPC_ISH_FWSTS_FW_STATUS_SHIFT;
+	return (IPC_ISH_FWSTS & IPC_ISH_FWSTS_FW_STATUS_MASK) >>
+	       IPC_ISH_FWSTS_FW_STATUS_SHIFT;
 }
 
 #endif /* __ISH_FWST_H */
diff --git a/chip/ish/ish_i2c.h b/chip/ish/ish_i2c.h
index 5b30de775c..c24f4e0cdc 100644
--- a/chip/ish/ish_i2c.h
+++ b/chip/ish/ish_i2c.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,23 +9,22 @@
 #include <stdint.h>
 #include "task.h"
 
-#define I2C_TSC_TIMEOUT			2000000
-#define I2C_CALIB_ADDRESS		0x3
-#define I2C_INTERRUPT_TIMEOUT		(TICKFREQ / 20)
-#define NS_IN_SEC			1000
-#define DEFAULT_SDA_HOLD		240
-#define DEFAULT_SDA_HOLD_STD		2400
-#define DEFAULT_SDA_HOLD_FAST		600
-#define DEFAULT_SDA_HOLD_FAST_PLUS	300
-#define DEFAULT_SDA_HOLD_HIGH		140
-#define NS_2_COUNTERS(ns, clk)		((ns * clk)/NS_IN_SEC)
-#define COUNTERS_2_NS(counters, clk)	(counters * (NANOSECONDS_IN_SEC / \
-					(clk * HZ_IN_MEGAHZ)))
-#define I2C_TX_FLUSH_TIMEOUT_USEC	200
+#define I2C_TSC_TIMEOUT 2000000
+#define I2C_CALIB_ADDRESS 0x3
+#define I2C_INTERRUPT_TIMEOUT (TICKFREQ / 20)
+#define NS_IN_SEC 1000
+#define DEFAULT_SDA_HOLD 240
+#define DEFAULT_SDA_HOLD_STD 2400
+#define DEFAULT_SDA_HOLD_FAST 600
+#define DEFAULT_SDA_HOLD_FAST_PLUS 300
+#define DEFAULT_SDA_HOLD_HIGH 140
+#define NS_2_COUNTERS(ns, clk) ((ns * clk) / NS_IN_SEC)
+#define COUNTERS_2_NS(counters, clk) \
+	(counters * (NANOSECONDS_IN_SEC / (clk * HZ_IN_MEGAHZ)))
+#define I2C_TX_FLUSH_TIMEOUT_USEC 200
 
 #define ISH_I2C_FIFO_SIZE 64
 
-
 enum {
 	/* freq mode values */
 	I2C_FREQ_25 = 0,
@@ -38,29 +37,18 @@ enum {
 };
 
 const unsigned int clk_in[] = {
-	[I2C_FREQ_25] = 25,
-	[I2C_FREQ_50] = 50,
-	[I2C_FREQ_100] = 100,
-	[I2C_FREQ_120] = 120,
-	[I2C_FREQ_40] = 40,
-	[I2C_FREQ_20] = 20,
+	[I2C_FREQ_25] = 25,   [I2C_FREQ_50] = 50, [I2C_FREQ_100] = 100,
+	[I2C_FREQ_120] = 120, [I2C_FREQ_40] = 40, [I2C_FREQ_20] = 20,
 	[I2C_FREQ_37] = 37,
 };
 
 const uint8_t spkln[] = {
-	[I2C_FREQ_25] = 2,
-	[I2C_FREQ_50] = 3,
-	[I2C_FREQ_100] = 5,
-	[I2C_FREQ_120] = 6,
-	[I2C_FREQ_40] = 2,
-	[I2C_FREQ_20] = 1,
+	[I2C_FREQ_25] = 2,  [I2C_FREQ_50] = 3, [I2C_FREQ_100] = 5,
+	[I2C_FREQ_120] = 6, [I2C_FREQ_40] = 2, [I2C_FREQ_20] = 1,
 	[I2C_FREQ_37] = 2,
 };
 
-enum {
-	I2C_READ,
-	I2C_WRITE
-};
+enum { I2C_READ, I2C_WRITE };
 
 enum {
 	/* REGISTERS */
@@ -125,7 +113,7 @@ enum {
 	IC_10BITADDR_MASTER = 0,
 	/* IC_TAR WRITE VALUES */
 	IC_10BITADDR_MASTER_VAL =
-	    (IC_10BITADDR_MASTER << IC_10BITADDR_MASTER_OFFSET),
+		(IC_10BITADDR_MASTER << IC_10BITADDR_MASTER_OFFSET),
 	TAR_SPECIAL_VAL = (TAR_SPECIAL << SPECIAL_OFFSET),
 	/* IC_DATA_CMD OFFSETS */
 	DATA_CMD_DAT_OFFSET = 0,
@@ -180,13 +168,13 @@ struct i2c_bus_info {
 	struct i2c_bus_data fast_speed;
 	struct i2c_bus_data fast_plus_speed;
 	struct i2c_bus_data high_speed;
-} __attribute__ ((__packed__));
+} __attribute__((__packed__));
 
 enum i2c_speed {
-	I2C_SPEED_100KHZ,	/* 100kHz */
-	I2C_SPEED_400KHZ,	/* 400kHz */
-	I2C_SPEED_1MHZ,		/*   1MHz */
-	I2C_SPEED_3M4HZ,	/* 3.4MHz */
+	I2C_SPEED_100KHZ, /* 100kHz */
+	I2C_SPEED_400KHZ, /* 400kHz */
+	I2C_SPEED_1MHZ, /*   1MHz */
+	I2C_SPEED_3M4HZ, /* 3.4MHz */
 };
 
 struct i2c_context {
diff --git a/chip/ish/ish_persistent_data.c b/chip/ish/ish_persistent_data.c
index 003f781d5f..149acaeade 100644
--- a/chip/ish/ish_persistent_data.c
+++ b/chip/ish/ish_persistent_data.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,7 @@ struct ish_persistent_data ish_persistent_data = {
 	.magic = PERSISTENT_DATA_MAGIC,
 	.reset_flags = EC_RESET_FLAG_POWER_ON,
 	.watchdog_counter = 0,
-	.panic_data = {0},
+	.panic_data = { 0 },
 };
 
 /*
@@ -40,8 +40,7 @@ void ish_persistent_data_init(void)
 {
 	if (ish_persistent_data_aon.magic == PERSISTENT_DATA_MAGIC) {
 		/* Stored data is valid, load a copy */
-		memcpy(&ish_persistent_data,
-		       &ish_persistent_data_aon,
+		memcpy(&ish_persistent_data, &ish_persistent_data_aon,
 		       sizeof(struct ish_persistent_data));
 
 		/* Invalidate stored data, in case commit fails to happen */
@@ -54,7 +53,6 @@ void ish_persistent_data_init(void)
 
 void ish_persistent_data_commit(void)
 {
-	memcpy(&ish_persistent_data_aon,
-	       &ish_persistent_data,
+	memcpy(&ish_persistent_data_aon, &ish_persistent_data,
 	       sizeof(struct ish_persistent_data));
 }
diff --git a/chip/ish/ish_persistent_data.h b/chip/ish/ish_persistent_data.h
index 0fd973e1bb..60aa6b94ae 100644
--- a/chip/ish/ish_persistent_data.h
+++ b/chip/ish/ish_persistent_data.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/ish/power_mgt.c b/chip/ish/power_mgt.c
index 70c3b35aa5..83ef0fc91b 100644
--- a/chip/ish/power_mgt.c
+++ b/chip/ish/power_mgt.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -52,7 +52,7 @@ static void pg_exit_restore_hw(void)
  * fixed amount of time to keep the console in use flag true after boot in
  * order to give a permanent window in which the low speed clock is not used.
  */
-#define CONSOLE_IN_USE_ON_BOOT_TIME (15*SECOND)
+#define CONSOLE_IN_USE_ON_BOOT_TIME (15 * SECOND)
 
 /* power management internal context data structure */
 struct pm_context {
@@ -172,20 +172,20 @@ static void init_aon_task(void)
 	 * limit: 0x67
 	 * Present = 1, DPL = 0
 	 */
-	desc_lo = GEN_GDT_DESC_LO((uint32_t)&main_tss,
-			GDT_DESC_TSS_LIMIT, GDT_DESC_TSS_FLAGS);
-	desc_up = GEN_GDT_DESC_UP((uint32_t)&main_tss,
-			GDT_DESC_TSS_LIMIT, GDT_DESC_TSS_FLAGS);
+	desc_lo = GEN_GDT_DESC_LO((uint32_t)&main_tss, GDT_DESC_TSS_LIMIT,
+				  GDT_DESC_TSS_FLAGS);
+	desc_up = GEN_GDT_DESC_UP((uint32_t)&main_tss, GDT_DESC_TSS_LIMIT,
+				  GDT_DESC_TSS_FLAGS);
 	add_gdt_entry(desc_lo, desc_up);
 
 	/* set GDT entry 4 for TSS descriptor of aontask
 	 * limit: 0x67
 	 * Present = 1, DPL = 0, Accessed = 1
 	 */
-	desc_lo = GEN_GDT_DESC_LO((uint32_t)aon_tss,
-			GDT_DESC_TSS_LIMIT, GDT_DESC_TSS_FLAGS);
-	desc_up = GEN_GDT_DESC_UP((uint32_t)aon_tss,
-			GDT_DESC_TSS_LIMIT, GDT_DESC_TSS_FLAGS);
+	desc_lo = GEN_GDT_DESC_LO((uint32_t)aon_tss, GDT_DESC_TSS_LIMIT,
+				  GDT_DESC_TSS_FLAGS);
+	desc_up = GEN_GDT_DESC_UP((uint32_t)aon_tss, GDT_DESC_TSS_LIMIT,
+				  GDT_DESC_TSS_FLAGS);
 	pm_ctx.aon_tss_selector[1] = add_gdt_entry(desc_lo, desc_up);
 
 	/* set GDT entry 5 for LDT descriptor of aontask
@@ -205,12 +205,12 @@ static void init_aon_task(void)
 			 "pop %eax;");
 
 	aon_share->main_fw_ro_addr = (uint32_t)&__aon_ro_start;
-	aon_share->main_fw_ro_size = (uint32_t)&__aon_ro_end -
-				     (uint32_t)&__aon_ro_start;
+	aon_share->main_fw_ro_size =
+		(uint32_t)&__aon_ro_end - (uint32_t)&__aon_ro_start;
 
 	aon_share->main_fw_rw_addr = (uint32_t)&__aon_rw_start;
-	aon_share->main_fw_rw_size = (uint32_t)&__aon_rw_end -
-				     (uint32_t)&__aon_rw_start;
+	aon_share->main_fw_rw_size =
+		(uint32_t)&__aon_rw_end - (uint32_t)&__aon_rw_start;
 
 	aon_share->uma_msb = IPC_UMA_RANGE_LOWER_1;
 
@@ -258,8 +258,7 @@ static void switch_to_aontask(void)
 	interrupt_enable();
 }
 
-noreturn
-static void handle_reset_in_aontask(enum ish_pm_state pm_state)
+noreturn static void handle_reset_in_aontask(enum ish_pm_state pm_state)
 {
 	pm_ctx.aon_share->pm_state = pm_state;
 
@@ -318,10 +317,8 @@ static uint32_t convert_both_edge_gpio_to_single_edge(void)
 	 * interrupt trigger mode enabled pins.
 	 */
 	for (i = 0; i < 32; i++) {
-		if (ISH_GPIO_GIMR & BIT(i) &&
-		    ISH_GPIO_GRER & BIT(i) &&
+		if (ISH_GPIO_GIMR & BIT(i) && ISH_GPIO_GRER & BIT(i) &&
 		    ISH_GPIO_GFER & BIT(i)) {
-
 			/* Record the pin so we can restore it later */
 			both_edge_pins |= BIT(i);
 
@@ -513,7 +510,6 @@ static int d0ix_decide(timestamp_t cur_time, uint32_t idle_us)
 	int pm_state = ISH_PM_STATE_D0I0;
 
 	if (DEEP_SLEEP_ALLOWED) {
-
 		/* check if the console use has expired. */
 		if (sleep_mask & SLEEP_MASK_CONSOLE) {
 			if (cur_time.val > pm_ctx.console_expire_time.val) {
@@ -525,8 +521,7 @@ static int d0ix_decide(timestamp_t cur_time, uint32_t idle_us)
 		}
 
 		if (IS_ENABLED(CONFIG_ISH_PM_D0I3) &&
-		    idle_us >= CONFIG_ISH_D0I3_MIN_USEC &&
-		    pm_ctx.aon_valid)
+		    idle_us >= CONFIG_ISH_D0I3_MIN_USEC && pm_ctx.aon_valid)
 			pm_state = ISH_PM_STATE_D0I3;
 
 		else if (IS_ENABLED(CONFIG_ISH_PM_D0I2) &&
@@ -633,7 +628,8 @@ void ish_pm_init(void)
 	PMU_MASK_EVENT = ~PMU_MASK_EVENT_BIT_ALL;
 
 	if (IS_ENABLED(CONFIG_ISH_NEW_PM)) {
-		PMU_ISH_FABRIC_CNT = (PMU_ISH_FABRIC_CNT & 0xffff0000) | FABRIC_IDLE_COUNT;
+		PMU_ISH_FABRIC_CNT = (PMU_ISH_FABRIC_CNT & 0xffff0000) |
+				     FABRIC_IDLE_COUNT;
 		PMU_PGCB_CLKGATE_CTRL = TRUNK_CLKGATE_COUNT;
 	}
 
@@ -656,11 +652,9 @@ void ish_pm_init(void)
 	}
 }
 
-noreturn
-void ish_pm_reset(enum ish_pm_state pm_state)
+noreturn void ish_pm_reset(enum ish_pm_state pm_state)
 {
-	if (IS_ENABLED(CONFIG_ISH_PM_AONTASK) &&
-	    pm_ctx.aon_valid) {
+	if (IS_ENABLED(CONFIG_ISH_PM_AONTASK) && pm_ctx.aon_valid) {
 		handle_reset_in_aontask(pm_state);
 	} else {
 		ish_mia_reset();
@@ -679,8 +673,8 @@ void __idle(void)
 	 * time in order to give a fixed window on boot
 	 */
 	disable_sleep(SLEEP_MASK_CONSOLE);
-	pm_ctx.console_expire_time.val = get_time().val +
-					 CONSOLE_IN_USE_ON_BOOT_TIME;
+	pm_ctx.console_expire_time.val =
+		get_time().val + CONSOLE_IN_USE_ON_BOOT_TIME;
 
 	while (1) {
 		t0 = get_time();
@@ -714,7 +708,7 @@ static void print_stats(const char *name, const struct pm_stat *stat)
 /**
  * Print low power idle statistics
  */
-static int command_idle_stats(int argc, char **argv)
+static int command_idle_stats(int argc, const char **argv)
 {
 	struct ish_aon_share *aon_share = pm_ctx.aon_share;
 
@@ -742,13 +736,11 @@ static int command_idle_stats(int argc, char **argv)
 DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, "",
 			"Print power management statistics");
 
-
 /**
  * main FW only need handle PMU wakeup interrupt for D0i1 state, aontask will
  * handle PMU wakeup interrupt for other low power states
  */
-__maybe_unused
-static void pmu_wakeup_isr(void)
+__maybe_unused static void pmu_wakeup_isr(void)
 {
 	/* at current nothing need to do */
 }
@@ -763,8 +755,7 @@ DECLARE_IRQ(ISH_PMU_WAKEUP_IRQ, pmu_wakeup_isr);
  *
  */
 
-__maybe_unused noreturn
-static void reset_prep_isr(void)
+__maybe_unused noreturn static void reset_prep_isr(void)
 {
 	/* mask reset prep avail interrupt */
 	PMU_RST_PREP = PMU_RST_PREP_INT_MASK;
@@ -784,8 +775,7 @@ static void reset_prep_isr(void)
 DECLARE_IRQ(ISH_RESET_PREP_IRQ, reset_prep_isr);
 #endif
 
-__maybe_unused
-static void handle_d3(uint32_t irq_vec)
+__maybe_unused static void handle_d3(uint32_t irq_vec)
 {
 	PMU_D3_STATUS = PMU_D3_STATUS;
 
@@ -839,5 +829,5 @@ void ish_pm_refresh_console_in_use(void)
 	/* Set console in use expire time. */
 	pm_ctx.console_expire_time = get_time();
 	pm_ctx.console_expire_time.val +=
-				pm_ctx.console_in_use_timeout_sec * SECOND;
+		pm_ctx.console_in_use_timeout_sec * SECOND;
 }
diff --git a/chip/ish/power_mgt.h b/chip/ish/power_mgt.h
index a1fd5aabb6..851529ffb1 100644
--- a/chip/ish/power_mgt.h
+++ b/chip/ish/power_mgt.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,8 +17,8 @@ extern void clear_fabric_error(void);
 extern void i2c_port_restore(void);
 extern void lapic_restore(void);
 
-#define FABRIC_IDLE_COUNT	50
-#define TRUNK_CLKGATE_COUNT	0xf
+#define FABRIC_IDLE_COUNT 50
+#define TRUNK_CLKGATE_COUNT 0xf
 
 /* power states for ISH */
 enum ish_pm_state {
@@ -58,8 +58,7 @@ static inline void ish_mia_halt(void)
 }
 
 /* reset ISH mintue-ia cpu core  */
-noreturn
-static inline void ish_mia_reset(void)
+noreturn static inline void ish_mia_reset(void)
 {
 	/**
 	 * ISH HW looks at the rising edge of this bit to
diff --git a/chip/ish/registers.h b/chip/ish/registers.h
index 08f1ce6ea3..bdd04a7cb2 100644
--- a/chip/ish/registers.h
+++ b/chip/ish/registers.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,99 +19,99 @@
  * ISH3.0 has 3 controllers. Locking must occur by-controller (not by-port).
  */
 enum ish_i2c_port {
-	ISH_I2C0   = 0,      /* Controller 0 */
-	ISH_I2C1   = 1,      /* Controller 1 */
-	ISH_I2C2   = 2,      /* Controller 2 */
+	ISH_I2C0 = 0, /* Controller 0 */
+	ISH_I2C1 = 1, /* Controller 1 */
+	ISH_I2C2 = 2, /* Controller 2 */
 	I2C_PORT_COUNT,
 };
 
 #endif
 
-#define ISH_I2C_PORT_COUNT	I2C_PORT_COUNT
+#define ISH_I2C_PORT_COUNT I2C_PORT_COUNT
 
 /* In ISH, the devices are mapped to pre-defined addresses in the 32-bit
  * linear address space.
  */
 #ifdef CHIP_VARIANT_ISH5P4
-#define ISH_I2C0_BASE     0x00000000
-#define ISH_I2C1_BASE     0x00002000
-#define ISH_I2C2_BASE     0x00004000
-#define ISH_UART_BASE     0x08100000
-#define ISH_GPIO_BASE     0x00100000
-#define ISH_PMU_BASE      0x04200000
-#define ISH_OCP_BASE      0xFFFFFFFF
-#define ISH_MISC_BASE     0x04400000
-#define ISH_DMA_BASE      0x10100000
-#define ISH_CCU_BASE      0x04300000
-#define ISH_IPC_BASE      0x04100000
-#define ISH_WDT_BASE      0x04900000
-#define ISH_IOAPIC_BASE   0xFEC00000
-#define ISH_HPET_BASE     0x04700000
-#define ISH_LAPIC_BASE    0xFEE00000
+#define ISH_I2C0_BASE 0x00000000
+#define ISH_I2C1_BASE 0x00002000
+#define ISH_I2C2_BASE 0x00004000
+#define ISH_UART_BASE 0x08100000
+#define ISH_GPIO_BASE 0x00100000
+#define ISH_PMU_BASE 0x04200000
+#define ISH_OCP_BASE 0xFFFFFFFF
+#define ISH_MISC_BASE 0x04400000
+#define ISH_DMA_BASE 0x10100000
+#define ISH_CCU_BASE 0x04300000
+#define ISH_IPC_BASE 0x04100000
+#define ISH_WDT_BASE 0x04900000
+#define ISH_IOAPIC_BASE 0xFEC00000
+#define ISH_HPET_BASE 0x04700000
+#define ISH_LAPIC_BASE 0xFEE00000
 #else
-#define ISH_I2C0_BASE     0x00100000
-#define ISH_I2C1_BASE     0x00102000
-#define ISH_I2C2_BASE     0x00105000
-#define ISH_UART_BASE     0x00103000
-#define ISH_GPIO_BASE     0x001F0000
-#define ISH_PMU_BASE      0x00800000
-#define ISH_OCP_BASE      0x00700000
-#define ISH_MISC_BASE     0x00C00000
-#define ISH_DMA_BASE      0x00400000
-#define ISH_CCU_BASE      0x00900000
-#define ISH_IPC_BASE      0x00B00000
-#define ISH_WDT_BASE      0xFDE00000
-#define ISH_IOAPIC_BASE   0xFEC00000
-#define ISH_HPET_BASE     0xFED00000
-#define ISH_LAPIC_BASE    0xFEE00000
+#define ISH_I2C0_BASE 0x00100000
+#define ISH_I2C1_BASE 0x00102000
+#define ISH_I2C2_BASE 0x00105000
+#define ISH_UART_BASE 0x00103000
+#define ISH_GPIO_BASE 0x001F0000
+#define ISH_PMU_BASE 0x00800000
+#define ISH_OCP_BASE 0x00700000
+#define ISH_MISC_BASE 0x00C00000
+#define ISH_DMA_BASE 0x00400000
+#define ISH_CCU_BASE 0x00900000
+#define ISH_IPC_BASE 0x00B00000
+#define ISH_WDT_BASE 0xFDE00000
+#define ISH_IOAPIC_BASE 0xFEC00000
+#define ISH_HPET_BASE 0xFED00000
+#define ISH_LAPIC_BASE 0xFEE00000
 #endif
 
 /* HW interrupt pins mapped to IOAPIC, from I/O sources */
 #ifdef CHIP_VARIANT_ISH5P4
-#define ISH_I2C0_IRQ               15
-#define ISH_I2C1_IRQ               16
-#define ISH_FABRIC_IRQ             12
-#define ISH_I2C2_IRQ               17
-#define ISH_WDT_IRQ                26
-#define ISH_GPIO_IRQ               13
-#define ISH_HPET_TIMER1_IRQ        14
-#define ISH_IPC_HOST2ISH_IRQ       0
-#define ISH_PMU_WAKEUP_IRQ         10
-#define ISH_D3_RISE_IRQ            9
-#define ISH_D3_FALL_IRQ            9
-#define ISH_BME_RISE_IRQ           9
-#define ISH_BME_FALL_IRQ           9
-#define ISH_IPC_ISH2HOST_CLR_IRQ   0
-#define ISH_UART0_IRQ              23
-#define ISH_UART1_IRQ              24
-#define ISH_RESET_PREP_IRQ         6
+#define ISH_I2C0_IRQ 15
+#define ISH_I2C1_IRQ 16
+#define ISH_FABRIC_IRQ 12
+#define ISH_I2C2_IRQ 17
+#define ISH_WDT_IRQ 26
+#define ISH_GPIO_IRQ 13
+#define ISH_HPET_TIMER1_IRQ 14
+#define ISH_IPC_HOST2ISH_IRQ 0
+#define ISH_PMU_WAKEUP_IRQ 10
+#define ISH_D3_RISE_IRQ 9
+#define ISH_D3_FALL_IRQ 9
+#define ISH_BME_RISE_IRQ 9
+#define ISH_BME_FALL_IRQ 9
+#define ISH_IPC_ISH2HOST_CLR_IRQ 0
+#define ISH_UART0_IRQ 23
+#define ISH_UART1_IRQ 24
+#define ISH_RESET_PREP_IRQ 6
 #else
-#define ISH_I2C0_IRQ               0
-#define ISH_I2C1_IRQ               1
-#define ISH_FABRIC_IRQ             5
-#define ISH_I2C2_IRQ               40
-#define ISH_WDT_IRQ                6
-#define ISH_GPIO_IRQ               7
-#define ISH_HPET_TIMER1_IRQ        8
-#define ISH_IPC_HOST2ISH_IRQ       12
-#define ISH_PMU_WAKEUP_IRQ         18
-#define ISH_D3_RISE_IRQ            19
-#define ISH_D3_FALL_IRQ            29
-#define ISH_BME_RISE_IRQ           50
-#define ISH_BME_FALL_IRQ           51
-#define ISH_IPC_ISH2HOST_CLR_IRQ   24
-#define ISH_UART0_IRQ              34
-#define ISH_UART1_IRQ              35
-#define ISH_RESET_PREP_IRQ         62
+#define ISH_I2C0_IRQ 0
+#define ISH_I2C1_IRQ 1
+#define ISH_FABRIC_IRQ 5
+#define ISH_I2C2_IRQ 40
+#define ISH_WDT_IRQ 6
+#define ISH_GPIO_IRQ 7
+#define ISH_HPET_TIMER1_IRQ 8
+#define ISH_IPC_HOST2ISH_IRQ 12
+#define ISH_PMU_WAKEUP_IRQ 18
+#define ISH_D3_RISE_IRQ 19
+#define ISH_D3_FALL_IRQ 29
+#define ISH_BME_RISE_IRQ 50
+#define ISH_BME_FALL_IRQ 51
+#define ISH_IPC_ISH2HOST_CLR_IRQ 24
+#define ISH_UART0_IRQ 34
+#define ISH_UART1_IRQ 35
+#define ISH_RESET_PREP_IRQ 62
 #endif
 
 /* Interrupt vectors 0-31 are architecture reserved.
  * Vectors 32-255 are user-defined.
  */
-#define USER_VEC_START   32
+#define USER_VEC_START 32
 /* Map IRQs to vectors after offset 10 for certain APIC interrupts */
-#define IRQ_TO_VEC(irq)  ((irq) + USER_VEC_START + 10)
-#define VEC_TO_IRQ(vec)  ((vec) - USER_VEC_START - 10)
+#define IRQ_TO_VEC(irq) ((irq) + USER_VEC_START + 10)
+#define VEC_TO_IRQ(vec) ((vec)-USER_VEC_START - 10)
 
 /* ISH GPIO Registers */
 #define ISH_GPIO_GCCR REG32(ISH_GPIO_BASE + 0x000) /* Direction lock */
@@ -129,322 +129,322 @@ enum ish_i2c_port {
 #define ISH_GPIO_GSEC REG32(ISH_GPIO_BASE + 0x130) /* Secure Input */
 
 /* APIC interrupt vectors */
-#define ISH_TS_VECTOR              0x20  /* Task switch vector */
-#define LAPIC_LVT_ERROR_VECTOR     0x21  /* Clears IOAPIC/LAPIC sync errors */
-#define SOFTIRQ_VECTOR             0x22  /* Handles software generated IRQs */
-#define LAPIC_SPURIOUS_INT_VECTOR  0xff
+#define ISH_TS_VECTOR 0x20 /* Task switch vector */
+#define LAPIC_LVT_ERROR_VECTOR 0x21 /* Clears IOAPIC/LAPIC sync errors */
+#define SOFTIRQ_VECTOR 0x22 /* Handles software generated IRQs */
+#define LAPIC_SPURIOUS_INT_VECTOR 0xff
 
 /* Interrupt to vector mapping. To be programmed into IOAPIC */
-#define ISH_I2C0_VEC               IRQ_TO_VEC(ISH_I2C0_IRQ)
-#define ISH_I2C1_VEC               IRQ_TO_VEC(ISH_I2C1_IRQ)
-#define ISH_I2C2_VEC               IRQ_TO_VEC(ISH_I2C2_IRQ)
-#define ISH_WDT_VEC                IRQ_TO_VEC(ISH_WDT_IRQ)
-#define ISH_GPIO_VEC               IRQ_TO_VEC(ISH_GPIO_IRQ)
-#define ISH_HPET_TIMER1_VEC        IRQ_TO_VEC(ISH_HPET_TIMER1_IRQ)
-#define ISH_IPC_ISH2HOST_CLR_VEC   IRQ_TO_VEC(ISH_IPC_ISH2HOST_CLR_IRQ)
-#define ISH_UART0_VEC              IRQ_TO_VEC(ISH_UART0_IRQ)
-#define ISH_UART1_VEC              IRQ_TO_VEC(ISH_UART1_IRQ)
-#define ISH_IPC_VEC                IRQ_TO_VEC(ISH_IPC_HOST2ISH_IRQ)
-#define ISH_RESET_PREP_VEC         IRQ_TO_VEC(ISH_RESET_PREP_IRQ)
-#define ISH_PMU_WAKEUP_VEC         IRQ_TO_VEC(ISH_PMU_WAKEUP_IRQ)
-#define ISH_D3_RISE_VEC            IRQ_TO_VEC(ISH_D3_RISE_IRQ)
-#define ISH_D3_FALL_VEC            IRQ_TO_VEC(ISH_D3_FALL_IRQ)
-#define ISH_BME_RISE_VEC           IRQ_TO_VEC(ISH_BME_RISE_IRQ)
-#define ISH_BME_FALL_VEC           IRQ_TO_VEC(ISH_BME_FALL_IRQ)
-#define ISH_FABRIC_VEC             IRQ_TO_VEC(ISH_FABRIC_IRQ)
-
-#define ISH_DEBUG_UART			UART_PORT_0
-#define ISH_DEBUG_UART_IRQ		ISH_UART0_IRQ
-#define ISH_DEBUG_UART_VEC		ISH_UART0_VEC
+#define ISH_I2C0_VEC IRQ_TO_VEC(ISH_I2C0_IRQ)
+#define ISH_I2C1_VEC IRQ_TO_VEC(ISH_I2C1_IRQ)
+#define ISH_I2C2_VEC IRQ_TO_VEC(ISH_I2C2_IRQ)
+#define ISH_WDT_VEC IRQ_TO_VEC(ISH_WDT_IRQ)
+#define ISH_GPIO_VEC IRQ_TO_VEC(ISH_GPIO_IRQ)
+#define ISH_HPET_TIMER1_VEC IRQ_TO_VEC(ISH_HPET_TIMER1_IRQ)
+#define ISH_IPC_ISH2HOST_CLR_VEC IRQ_TO_VEC(ISH_IPC_ISH2HOST_CLR_IRQ)
+#define ISH_UART0_VEC IRQ_TO_VEC(ISH_UART0_IRQ)
+#define ISH_UART1_VEC IRQ_TO_VEC(ISH_UART1_IRQ)
+#define ISH_IPC_VEC IRQ_TO_VEC(ISH_IPC_HOST2ISH_IRQ)
+#define ISH_RESET_PREP_VEC IRQ_TO_VEC(ISH_RESET_PREP_IRQ)
+#define ISH_PMU_WAKEUP_VEC IRQ_TO_VEC(ISH_PMU_WAKEUP_IRQ)
+#define ISH_D3_RISE_VEC IRQ_TO_VEC(ISH_D3_RISE_IRQ)
+#define ISH_D3_FALL_VEC IRQ_TO_VEC(ISH_D3_FALL_IRQ)
+#define ISH_BME_RISE_VEC IRQ_TO_VEC(ISH_BME_RISE_IRQ)
+#define ISH_BME_FALL_VEC IRQ_TO_VEC(ISH_BME_FALL_IRQ)
+#define ISH_FABRIC_VEC IRQ_TO_VEC(ISH_FABRIC_IRQ)
+
+#define ISH_DEBUG_UART UART_PORT_0
+#define ISH_DEBUG_UART_IRQ ISH_UART0_IRQ
+#define ISH_DEBUG_UART_VEC ISH_UART0_VEC
 
 /* IPC_Registers */
-#define IPC_PISR			REG32(ISH_IPC_BASE + 0x0)
-#define IPC_PISR_HOST2ISH_BIT		BIT(0)
-
-#define IPC_PIMR			REG32(ISH_IPC_BASE + 0x4)
-#define IPC_PIMR_HOST2ISH_BIT		BIT(0)
-#define IPC_PIMR_ISH2HOST_CLR_BIT	BIT(11)
-#define IPC_PIMR_CSME_CSR_BIT		BIT(23)
-#define IPC_ISH2HOST_MSG_BASE		REG8_ADDR(ISH_IPC_BASE + 0x60)
-#define IPC_ISH_FWSTS			REG32(ISH_IPC_BASE + 0x34)
-#define IPC_HOST2ISH_DOORBELL_ADDR	REG32_ADDR(ISH_IPC_BASE + 0x48)
-#define IPC_HOST2ISH_MSG_BASE		REG8_ADDR(ISH_IPC_BASE + 0xE0)
-#define IPC_ISH2HOST_DOORBELL_ADDR	REG32_ADDR(ISH_IPC_BASE + 0x54)
-#define IPC_ISH2PMC_DOORBELL		REG32(ISH_IPC_BASE + 0x58)
-#define IPC_ISH2PMC_MSG_BASE		(ISH_IPC_BASE + 0x260)
-#define IPC_ISH_RMP0			REG32(ISH_IPC_BASE + 0x360)
-#define IPC_ISH_RMP1			REG32(ISH_IPC_BASE + 0x364)
-#define IPC_ISH_RMP2			REG32(ISH_IPC_BASE + 0x368)
-#define DMA_ENABLED_MASK		BIT(0)
-#define IPC_BUSY_CLEAR			REG32(ISH_IPC_BASE + 0x378)
-#define IPC_DB_CLR_STS_ISH2HOST_BIT	BIT(0)
-
-#define IPC_UMA_RANGE_LOWER_0		REG32(ISH_IPC_BASE + 0x380)
-#define IPC_UMA_RANGE_LOWER_1		REG32(ISH_IPC_BASE + 0x384)
-#define IPC_UMA_RANGE_UPPER_0		REG32(ISH_IPC_BASE + 0x388)
-#define IPC_UMA_RANGE_UPPER_1		REG32(ISH_IPC_BASE + 0x38C)
+#define IPC_PISR REG32(ISH_IPC_BASE + 0x0)
+#define IPC_PISR_HOST2ISH_BIT BIT(0)
+
+#define IPC_PIMR REG32(ISH_IPC_BASE + 0x4)
+#define IPC_PIMR_HOST2ISH_BIT BIT(0)
+#define IPC_PIMR_ISH2HOST_CLR_BIT BIT(11)
+#define IPC_PIMR_CSME_CSR_BIT BIT(23)
+#define IPC_ISH2HOST_MSG_BASE REG8_ADDR(ISH_IPC_BASE + 0x60)
+#define IPC_ISH_FWSTS REG32(ISH_IPC_BASE + 0x34)
+#define IPC_HOST2ISH_DOORBELL_ADDR REG32_ADDR(ISH_IPC_BASE + 0x48)
+#define IPC_HOST2ISH_MSG_BASE REG8_ADDR(ISH_IPC_BASE + 0xE0)
+#define IPC_ISH2HOST_DOORBELL_ADDR REG32_ADDR(ISH_IPC_BASE + 0x54)
+#define IPC_ISH2PMC_DOORBELL REG32(ISH_IPC_BASE + 0x58)
+#define IPC_ISH2PMC_MSG_BASE (ISH_IPC_BASE + 0x260)
+#define IPC_ISH_RMP0 REG32(ISH_IPC_BASE + 0x360)
+#define IPC_ISH_RMP1 REG32(ISH_IPC_BASE + 0x364)
+#define IPC_ISH_RMP2 REG32(ISH_IPC_BASE + 0x368)
+#define DMA_ENABLED_MASK BIT(0)
+#define IPC_BUSY_CLEAR REG32(ISH_IPC_BASE + 0x378)
+#define IPC_DB_CLR_STS_ISH2HOST_BIT BIT(0)
+
+#define IPC_UMA_RANGE_LOWER_0 REG32(ISH_IPC_BASE + 0x380)
+#define IPC_UMA_RANGE_LOWER_1 REG32(ISH_IPC_BASE + 0x384)
+#define IPC_UMA_RANGE_UPPER_0 REG32(ISH_IPC_BASE + 0x388)
+#define IPC_UMA_RANGE_UPPER_1 REG32(ISH_IPC_BASE + 0x38C)
 
 /* PMU Registers */
-#define PMU_SRAM_PG_EN			REG32(ISH_PMU_BASE + 0x0)
+#define PMU_SRAM_PG_EN REG32(ISH_PMU_BASE + 0x0)
 #ifndef CHIP_VARIANT_ISH5P4
-#define PMU_D3_STATUS			REG32(ISH_PMU_BASE + 0x4)
-#define PMU_D3_BIT_SET			BIT(0)
-#define PMU_D3_BIT_RISING_EDGE_STATUS	BIT(1)
-#define PMU_D3_BIT_FALLING_EDGE_STATUS	BIT(2)
-#define PMU_D3_BIT_RISING_EDGE_MASK	BIT(3)
-#define PMU_D3_BIT_FALLING_EDGE_MASK	BIT(4)
-#define PMU_BME_BIT_SET		BIT(5)
-#define PMU_BME_BIT_RISING_EDGE_STATUS	BIT(6)
+#define PMU_D3_STATUS REG32(ISH_PMU_BASE + 0x4)
+#define PMU_D3_BIT_SET BIT(0)
+#define PMU_D3_BIT_RISING_EDGE_STATUS BIT(1)
+#define PMU_D3_BIT_FALLING_EDGE_STATUS BIT(2)
+#define PMU_D3_BIT_RISING_EDGE_MASK BIT(3)
+#define PMU_D3_BIT_FALLING_EDGE_MASK BIT(4)
+#define PMU_BME_BIT_SET BIT(5)
+#define PMU_BME_BIT_RISING_EDGE_STATUS BIT(6)
 #define PMU_BME_BIT_FALLING_EDGE_STATUS BIT(7)
-#define PMU_BME_BIT_RISING_EDGE_MASK	BIT(8)
-#define PMU_BME_BIT_FALLING_EDGE_MASK	BIT(9)
+#define PMU_BME_BIT_RISING_EDGE_MASK BIT(8)
+#define PMU_BME_BIT_FALLING_EDGE_MASK BIT(9)
 #else
-#define PMU_STATUS_REG_ADDR		(ISH_PMU_BASE + 0xF00)
-#define PMU_SCRATCHPAD0_REG_ADDR	(ISH_PMU_BASE + 0xF04)
-#define PMU_SCRATCHPAD1_REG_ADDR	(ISH_PMU_BASE + 0xF08)
-#define PMU_PG_EN_REG_ADDR		(ISH_PMU_BASE + 0xF10)
-#define PMU_PMC_HOST_RST_CTL		REG32(ISH_PMU_BASE + 0xF20)
-#define PMU_SW_PG_REQ			REG32(ISH_PMU_BASE + 0xF14)
-#define PMU_PMC_PG_WAKE			REG32(ISH_PMU_BASE + 0xF18)
-#define PMU_INTERNAL_PCE		REG32(ISH_PMU_BASE + 0xF30)
-#define PMU_D3_STATUS			REG32(ISH_PMU_BASE + 0x100)
-#define PMU_HOST_RST_B			BIT(0)
-#define PMU_PCE_SHADOW_MASK		0x1F
-#define PMU_PCE_PG_ALLOWED		BIT(4)
-#define PMU_PCE_CHANGE_MASK		BIT(9)
-#define PMU_PCE_CHANGE_DETECTED		BIT(8)
-#define PMU_PCE_PMCRE			BIT(0)
-#define PMU_SW_PG_REQ_B_VAL		BIT(0)
-#define PMU_SW_PG_REQ_B_RISE		BIT(1)
-#define PMU_SW_PG_REQ_B_FALL		BIT(2)
-#define PMU_PMC_PG_WAKE_VAL		BIT(0)
-#define PMU_PMC_PG_WAKE_RISE		BIT(1)
-#define PMU_PMC_PG_WAKE_FALL		BIT(2)
-#define PMU_PCE_PG_ALLOWED		BIT(4)
-#define PMU_D0I3_ENABLE_MASK		BIT(23)
-#define PMU_D3_BIT_SET			BIT(16)
-#define PMU_D3_BIT_RISING_EDGE_STATUS	BIT(17)
-#define PMU_D3_BIT_FALLING_EDGE_STATUS	BIT(18)
-#define PMU_D3_BIT_RISING_EDGE_MASK	BIT(19)
-#define PMU_D3_BIT_FALLING_EDGE_MASK	BIT(20)
-#define PMU_BME_BIT_SET			BIT(24)
-#define PMU_BME_BIT_RISING_EDGE_STATUS	BIT(25)
-#define PMU_BME_BIT_FALLING_EDGE_STATUS	BIT(26)
-#define PMU_BME_BIT_RISING_EDGE_MASK	BIT(27)
-#define PMU_BME_BIT_FALLING_EDGE_MASK	BIT(28)
+#define PMU_STATUS_REG_ADDR (ISH_PMU_BASE + 0xF00)
+#define PMU_SCRATCHPAD0_REG_ADDR (ISH_PMU_BASE + 0xF04)
+#define PMU_SCRATCHPAD1_REG_ADDR (ISH_PMU_BASE + 0xF08)
+#define PMU_PG_EN_REG_ADDR (ISH_PMU_BASE + 0xF10)
+#define PMU_PMC_HOST_RST_CTL REG32(ISH_PMU_BASE + 0xF20)
+#define PMU_SW_PG_REQ REG32(ISH_PMU_BASE + 0xF14)
+#define PMU_PMC_PG_WAKE REG32(ISH_PMU_BASE + 0xF18)
+#define PMU_INTERNAL_PCE REG32(ISH_PMU_BASE + 0xF30)
+#define PMU_D3_STATUS REG32(ISH_PMU_BASE + 0x100)
+#define PMU_HOST_RST_B BIT(0)
+#define PMU_PCE_SHADOW_MASK 0x1F
+#define PMU_PCE_PG_ALLOWED BIT(4)
+#define PMU_PCE_CHANGE_MASK BIT(9)
+#define PMU_PCE_CHANGE_DETECTED BIT(8)
+#define PMU_PCE_PMCRE BIT(0)
+#define PMU_SW_PG_REQ_B_VAL BIT(0)
+#define PMU_SW_PG_REQ_B_RISE BIT(1)
+#define PMU_SW_PG_REQ_B_FALL BIT(2)
+#define PMU_PMC_PG_WAKE_VAL BIT(0)
+#define PMU_PMC_PG_WAKE_RISE BIT(1)
+#define PMU_PMC_PG_WAKE_FALL BIT(2)
+#define PMU_PCE_PG_ALLOWED BIT(4)
+#define PMU_D0I3_ENABLE_MASK BIT(23)
+#define PMU_D3_BIT_SET BIT(16)
+#define PMU_D3_BIT_RISING_EDGE_STATUS BIT(17)
+#define PMU_D3_BIT_FALLING_EDGE_STATUS BIT(18)
+#define PMU_D3_BIT_RISING_EDGE_MASK BIT(19)
+#define PMU_D3_BIT_FALLING_EDGE_MASK BIT(20)
+#define PMU_BME_BIT_SET BIT(24)
+#define PMU_BME_BIT_RISING_EDGE_STATUS BIT(25)
+#define PMU_BME_BIT_FALLING_EDGE_STATUS BIT(26)
+#define PMU_BME_BIT_RISING_EDGE_MASK BIT(27)
+#define PMU_BME_BIT_FALLING_EDGE_MASK BIT(28)
 #endif
 
-#define PMU_GPIO_WAKE_MASK0		REG32(ISH_PMU_BASE + 0x250)
-#define PMU_GPIO_WAKE_MASK1		REG32(ISH_PMU_BASE + 0x254)
+#define PMU_GPIO_WAKE_MASK0 REG32(ISH_PMU_BASE + 0x250)
+#define PMU_GPIO_WAKE_MASK1 REG32(ISH_PMU_BASE + 0x254)
 
-#define PMU_ISH_FABRIC_CNT		REG32(ISH_PMU_BASE + 0x18)
+#define PMU_ISH_FABRIC_CNT REG32(ISH_PMU_BASE + 0x18)
 
-#define PMU_PGCB_CLKGATE_CTRL		REG32(ISH_PMU_BASE + 0x54)
+#define PMU_PGCB_CLKGATE_CTRL REG32(ISH_PMU_BASE + 0x54)
 
-#define PMU_VNN_REQ			REG32(ISH_PMU_BASE + 0x3c)
-#define VNN_REQ_IPC_HOST_WRITE		BIT(3) /* Power for IPC host write */
+#define PMU_VNN_REQ REG32(ISH_PMU_BASE + 0x3c)
+#define VNN_REQ_IPC_HOST_WRITE BIT(3) /* Power for IPC host write */
 
-#define PMU_VNN_REQ_ACK		REG32(ISH_PMU_BASE + 0x40)
-#define PMU_VNN_REQ_ACK_STATUS		BIT(0) /* VNN req and ack status */
+#define PMU_VNN_REQ_ACK REG32(ISH_PMU_BASE + 0x40)
+#define PMU_VNN_REQ_ACK_STATUS BIT(0) /* VNN req and ack status */
 
-#define PMU_VNNAON_RED			REG32(ISH_PMU_BASE + 0x58)
+#define PMU_VNNAON_RED REG32(ISH_PMU_BASE + 0x58)
 
-#define PMU_RST_PREP			REG32(ISH_PMU_BASE + 0x5c)
-#define PMU_RST_PREP_GET		BIT(0)
-#define PMU_RST_PREP_AVAIL		BIT(1)
-#define PMU_RST_PREP_INT_MASK		BIT(31)
+#define PMU_RST_PREP REG32(ISH_PMU_BASE + 0x5c)
+#define PMU_RST_PREP_GET BIT(0)
+#define PMU_RST_PREP_AVAIL BIT(1)
+#define PMU_RST_PREP_INT_MASK BIT(31)
 
-#define VNN_ID_DMA0             4
-#define VNN_ID_DMA(chan)        (VNN_ID_DMA0 + chan)
+#define VNN_ID_DMA0 4
+#define VNN_ID_DMA(chan) (VNN_ID_DMA0 + chan)
 
 /* OCP registers */
-#define OCP_IOSF2OCP_BRIDGE      (ISH_OCP_BASE + 0x9400)
-#define OCP_AGENT_CONTROL        REG32(OCP_IOSF2OCP_BRIDGE + 0x20)
-#define OCP_RESPONSE_TO_DISABLE  0xFFFFF8FF
+#define OCP_IOSF2OCP_BRIDGE (ISH_OCP_BASE + 0x9400)
+#define OCP_AGENT_CONTROL REG32(OCP_IOSF2OCP_BRIDGE + 0x20)
+#define OCP_RESPONSE_TO_DISABLE 0xFFFFF8FF
 
 /* MISC registers */
-#define MISC_REG_BASE            ISH_MISC_BASE
-#define DMA_REG_BASE             ISH_DMA_BASE
+#define MISC_REG_BASE ISH_MISC_BASE
+#define DMA_REG_BASE ISH_DMA_BASE
 #ifndef CHIP_VARIANT_ISH5P4
-#define MISC_CHID_CFG_REG        REG32(MISC_REG_BASE + 0x40)
-#define MISC_DMA_CTL_REG(ch)     REG32(MISC_REG_BASE + (4 * (ch)))
-#define MISC_SRC_FILLIN_DMA(ch)  REG32(MISC_REG_BASE + 0x20 + (4 * (ch)))
-#define MISC_DST_FILLIN_DMA(ch)  REG32(MISC_REG_BASE + 0x80 + (4 * (ch)))
-#define MISC_ISH_ECC_ERR_SRESP   REG32(MISC_REG_BASE + 0x94)
+#define MISC_CHID_CFG_REG REG32(MISC_REG_BASE + 0x40)
+#define MISC_DMA_CTL_REG(ch) REG32(MISC_REG_BASE + (4 * (ch)))
+#define MISC_SRC_FILLIN_DMA(ch) REG32(MISC_REG_BASE + 0x20 + (4 * (ch)))
+#define MISC_DST_FILLIN_DMA(ch) REG32(MISC_REG_BASE + 0x80 + (4 * (ch)))
+#define MISC_ISH_ECC_ERR_SRESP REG32(MISC_REG_BASE + 0x94)
 #else
-#define DMA_MISC_OFFSET          0x1000
-#define DMA_MISC_BASE            (DMA_REG_BASE + DMA_MISC_OFFSET)
-#define MISC_CHID_CFG_REG        REG32(DMA_MISC_BASE + 0x400)
-#define MISC_DMA_CTL_REG(ch)     REG32(DMA_MISC_BASE + (4 * (ch)))
-#define MISC_SRC_FILLIN_DMA(ch)  REG32(DMA_MISC_BASE + 0x100 + (4 * (ch)))
-#define MISC_DST_FILLIN_DMA(ch)  REG32(DMA_MISC_BASE + 0x200 + (4 * (ch)))
-#define MISC_ISH_ECC_ERR_SRESP   REG32(DMA_MISC_BASE + 0x404)
+#define DMA_MISC_OFFSET 0x1000
+#define DMA_MISC_BASE (DMA_REG_BASE + DMA_MISC_OFFSET)
+#define MISC_CHID_CFG_REG REG32(DMA_MISC_BASE + 0x400)
+#define MISC_DMA_CTL_REG(ch) REG32(DMA_MISC_BASE + (4 * (ch)))
+#define MISC_SRC_FILLIN_DMA(ch) REG32(DMA_MISC_BASE + 0x100 + (4 * (ch)))
+#define MISC_DST_FILLIN_DMA(ch) REG32(DMA_MISC_BASE + 0x200 + (4 * (ch)))
+#define MISC_ISH_ECC_ERR_SRESP REG32(DMA_MISC_BASE + 0x404)
 #endif
-#define MISC_ISH_RTC_COUNTER0	REG32(ISH_MISC_BASE + 0x70)
-#define MISC_ISH_RTC_COUNTER1	REG32(ISH_MISC_BASE + 0x74)
+#define MISC_ISH_RTC_COUNTER0 REG32(ISH_MISC_BASE + 0x70)
+#define MISC_ISH_RTC_COUNTER1 REG32(ISH_MISC_BASE + 0x74)
 
 /* DMA registers */
-#define DMA_CH_REGS_SIZE              0x58
-#define DMA_CLR_BLOCK_REG             REG32(DMA_REG_BASE + 0x340)
-#define DMA_CLR_ERR_REG               REG32(DMA_REG_BASE + 0x358)
-#define DMA_EN_REG_ADDR               (DMA_REG_BASE + 0x3A0)
-#define DMA_EN_REG                    REG32(DMA_EN_REG_ADDR)
-#define DMA_CFG_REG                   REG32(DMA_REG_BASE + 0x398)
-#define DMA_PSIZE_01                  REG32(DMA_REG_BASE + 0x400)
-#define DMA_PSIZE_CHAN0_SIZE          512
-#define DMA_PSIZE_CHAN0_OFFSET        0
-#define DMA_PSIZE_CHAN1_SIZE          128
-#define DMA_PSIZE_CHAN1_OFFSET        13
-#define DMA_PSIZE_UPDATE	      BIT(26)
-#define DMA_MAX_CHANNEL               4
-#define DMA_SAR(chan)                 REG32(chan + 0x000)
-#define DMA_DAR(chan)                 REG32(chan + 0x008)
-#define DMA_LLP(chan)                 REG32(chan + 0x010)
-#define DMA_CTL_LOW(chan)             REG32(chan + 0x018)
-#define DMA_CTL_HIGH(chan)            REG32(chan + 0x018 + 0x4)
-#define DMA_CTL_INT_ENABLE	      BIT(0)
-#define DMA_CTL_DST_TR_WIDTH_SHIFT    1
-#define DMA_CTL_SRC_TR_WIDTH_SHIFT    4
-#define DMA_CTL_DINC_SHIFT            7
-#define DMA_CTL_SINC_SHIFT            9
-#define DMA_CTL_ADDR_INC              0
-#define DMA_CTL_DEST_MSIZE_SHIFT      11
-#define DMA_CTL_SRC_MSIZE_SHIFT       14
-#define DMA_CTL_TT_FC_SHIFT           20
-#define DMA_CTL_TT_FC_M2M_DMAC        0
-#define DMA_ENABLE		      BIT(0)
-#define DMA_CH_EN_BIT(n)	      BIT(n)
-#define DMA_CH_EN_WE_BIT(n)	      BIT(8 + (n))
-#define DMA_MAX_BLOCK_SIZE	      (4096)
-#define SRC_TR_WIDTH                  2
-#define SRC_BURST_SIZE                3
-#define DEST_TR_WIDTH                 2
-#define DEST_BURST_SIZE               3
-
-#define PMU_MASK_EVENT			REG32(ISH_PMU_BASE + 0x10)
-#define PMU_MASK_EVENT_BIT_GPIO(pin)	BIT(pin)
-#define PMU_MASK_EVENT_BIT_HPET	BIT(16)
-#define PMU_MASK_EVENT_BIT_IPC		BIT(17)
-#define PMU_MASK_EVENT_BIT_D3		BIT(18)
-#define PMU_MASK_EVENT_BIT_DMA		BIT(19)
-#define PMU_MASK_EVENT_BIT_I2C0	BIT(20)
-#define PMU_MASK_EVENT_BIT_I2C1	BIT(21)
-#define PMU_MASK_EVENT_BIT_SPI		BIT(22)
-#define PMU_MASK_EVENT_BIT_UART	BIT(23)
-#define PMU_MASK_EVENT_BIT_ALL		(0xffffffff)
-
-#define PMU_RF_ROM_PWR_CTRL		REG32(ISH_PMU_BASE + 0x30)
-
-#define PMU_LDO_CTRL			REG32(ISH_PMU_BASE + 0x44)
-#define PMU_LDO_ENABLE_BIT		BIT(0)
-#define PMU_LDO_RETENTION_BIT		BIT(1)
-#define PMU_LDO_CALIBRATION_BIT	BIT(2)
-#define PMU_LDO_READY_BIT		BIT(3)
+#define DMA_CH_REGS_SIZE 0x58
+#define DMA_CLR_BLOCK_REG REG32(DMA_REG_BASE + 0x340)
+#define DMA_CLR_ERR_REG REG32(DMA_REG_BASE + 0x358)
+#define DMA_EN_REG_ADDR (DMA_REG_BASE + 0x3A0)
+#define DMA_EN_REG REG32(DMA_EN_REG_ADDR)
+#define DMA_CFG_REG REG32(DMA_REG_BASE + 0x398)
+#define DMA_PSIZE_01 REG32(DMA_REG_BASE + 0x400)
+#define DMA_PSIZE_CHAN0_SIZE 512
+#define DMA_PSIZE_CHAN0_OFFSET 0
+#define DMA_PSIZE_CHAN1_SIZE 128
+#define DMA_PSIZE_CHAN1_OFFSET 13
+#define DMA_PSIZE_UPDATE BIT(26)
+#define DMA_MAX_CHANNEL 4
+#define DMA_SAR(chan) REG32(chan + 0x000)
+#define DMA_DAR(chan) REG32(chan + 0x008)
+#define DMA_LLP(chan) REG32(chan + 0x010)
+#define DMA_CTL_LOW(chan) REG32(chan + 0x018)
+#define DMA_CTL_HIGH(chan) REG32(chan + 0x018 + 0x4)
+#define DMA_CTL_INT_ENABLE BIT(0)
+#define DMA_CTL_DST_TR_WIDTH_SHIFT 1
+#define DMA_CTL_SRC_TR_WIDTH_SHIFT 4
+#define DMA_CTL_DINC_SHIFT 7
+#define DMA_CTL_SINC_SHIFT 9
+#define DMA_CTL_ADDR_INC 0
+#define DMA_CTL_DEST_MSIZE_SHIFT 11
+#define DMA_CTL_SRC_MSIZE_SHIFT 14
+#define DMA_CTL_TT_FC_SHIFT 20
+#define DMA_CTL_TT_FC_M2M_DMAC 0
+#define DMA_ENABLE BIT(0)
+#define DMA_CH_EN_BIT(n) BIT(n)
+#define DMA_CH_EN_WE_BIT(n) BIT(8 + (n))
+#define DMA_MAX_BLOCK_SIZE (4096)
+#define SRC_TR_WIDTH 2
+#define SRC_BURST_SIZE 3
+#define DEST_TR_WIDTH 2
+#define DEST_BURST_SIZE 3
+
+#define PMU_MASK_EVENT REG32(ISH_PMU_BASE + 0x10)
+#define PMU_MASK_EVENT_BIT_GPIO(pin) BIT(pin)
+#define PMU_MASK_EVENT_BIT_HPET BIT(16)
+#define PMU_MASK_EVENT_BIT_IPC BIT(17)
+#define PMU_MASK_EVENT_BIT_D3 BIT(18)
+#define PMU_MASK_EVENT_BIT_DMA BIT(19)
+#define PMU_MASK_EVENT_BIT_I2C0 BIT(20)
+#define PMU_MASK_EVENT_BIT_I2C1 BIT(21)
+#define PMU_MASK_EVENT_BIT_SPI BIT(22)
+#define PMU_MASK_EVENT_BIT_UART BIT(23)
+#define PMU_MASK_EVENT_BIT_ALL (0xffffffff)
+
+#define PMU_RF_ROM_PWR_CTRL REG32(ISH_PMU_BASE + 0x30)
+
+#define PMU_LDO_CTRL REG32(ISH_PMU_BASE + 0x44)
+#define PMU_LDO_ENABLE_BIT BIT(0)
+#define PMU_LDO_RETENTION_BIT BIT(1)
+#define PMU_LDO_CALIBRATION_BIT BIT(2)
+#define PMU_LDO_READY_BIT BIT(3)
 
 /* CCU Registers */
-#define CCU_TCG_EN		REG32(ISH_CCU_BASE + 0x0)
-#define CCU_BCG_EN		REG32(ISH_CCU_BASE + 0x4)
+#define CCU_TCG_EN REG32(ISH_CCU_BASE + 0x0)
+#define CCU_BCG_EN REG32(ISH_CCU_BASE + 0x4)
 #ifndef CHIP_VARIANT_ISH5P4
-#define CCU_WDT_CD		REG32(ISH_CCU_BASE + 0x8)
-#define CCU_RST_HST		REG32(ISH_CCU_BASE + 0x34) /* Reset history */
-#define CCU_TCG_ENABLE		REG32(ISH_CCU_BASE + 0x38)
-#define CCU_BCG_ENABLE		REG32(ISH_CCU_BASE + 0x3c)
+#define CCU_WDT_CD REG32(ISH_CCU_BASE + 0x8)
+#define CCU_RST_HST REG32(ISH_CCU_BASE + 0x34) /* Reset history */
+#define CCU_TCG_ENABLE REG32(ISH_CCU_BASE + 0x38)
+#define CCU_BCG_ENABLE REG32(ISH_CCU_BASE + 0x3c)
 #else
-#define CCU_WDT_CD		REG32(ISH_CCU_BASE + 0x7c)
-#define CCU_RST_HST		REG32(ISH_CCU_BASE + 0x3c) /* Reset history */
-#define CCU_TCG_ENABLE		REG32(ISH_CCU_BASE + 0x40)
-#define CCU_BCG_ENABLE		REG32(ISH_CCU_BASE + 0x44)
+#define CCU_WDT_CD REG32(ISH_CCU_BASE + 0x7c)
+#define CCU_RST_HST REG32(ISH_CCU_BASE + 0x3c) /* Reset history */
+#define CCU_TCG_ENABLE REG32(ISH_CCU_BASE + 0x40)
+#define CCU_BCG_ENABLE REG32(ISH_CCU_BASE + 0x44)
 #endif
-#define CCU_BCG_MIA		REG32(ISH_CCU_BASE + 0x4)
-#define CCU_BCG_UART		REG32(ISH_CCU_BASE + 0x8)
-#define CCU_BCG_I2C		REG32(ISH_CCU_BASE + 0xc)
-#define CCU_BCG_SPI		REG32(ISH_CCU_BASE + 0x10)
-#define CCU_BCG_GPIO		REG32(ISH_CCU_BASE + 0x14)
-#define CCU_BCG_DMA		REG32(ISH_CCU_BASE + 0x28)
-#define CCU_AONCG_EN		REG32(ISH_CCU_BASE + 0xdc)
-#define CCU_BCG_BIT_MIA	BIT(0)
-#define CCU_BCG_BIT_DMA	BIT(1)
-#define CCU_BCG_BIT_I2C0	BIT(2)
-#define CCU_BCG_BIT_I2C1	BIT(3)
-#define CCU_BCG_BIT_SPI	BIT(4)
-#define CCU_BCG_BIT_SRAM	BIT(5)
-#define CCU_BCG_BIT_HPET	BIT(6)
-#define CCU_BCG_BIT_UART	BIT(7)
-#define CCU_BCG_BIT_GPIO	BIT(8)
-#define CCU_BCG_BIT_I2C2	BIT(9)
-#define CCU_BCG_BIT_SPI2	BIT(10)
-#define CCU_BCG_BIT_ALL	(0x7ff)
+#define CCU_BCG_MIA REG32(ISH_CCU_BASE + 0x4)
+#define CCU_BCG_UART REG32(ISH_CCU_BASE + 0x8)
+#define CCU_BCG_I2C REG32(ISH_CCU_BASE + 0xc)
+#define CCU_BCG_SPI REG32(ISH_CCU_BASE + 0x10)
+#define CCU_BCG_GPIO REG32(ISH_CCU_BASE + 0x14)
+#define CCU_BCG_DMA REG32(ISH_CCU_BASE + 0x28)
+#define CCU_AONCG_EN REG32(ISH_CCU_BASE + 0xdc)
+#define CCU_BCG_BIT_MIA BIT(0)
+#define CCU_BCG_BIT_DMA BIT(1)
+#define CCU_BCG_BIT_I2C0 BIT(2)
+#define CCU_BCG_BIT_I2C1 BIT(3)
+#define CCU_BCG_BIT_SPI BIT(4)
+#define CCU_BCG_BIT_SRAM BIT(5)
+#define CCU_BCG_BIT_HPET BIT(6)
+#define CCU_BCG_BIT_UART BIT(7)
+#define CCU_BCG_BIT_GPIO BIT(8)
+#define CCU_BCG_BIT_I2C2 BIT(9)
+#define CCU_BCG_BIT_SPI2 BIT(10)
+#define CCU_BCG_BIT_ALL (0x7ff)
 
 /* Bitmasks for CCU_RST_HST */
-#define CCU_SW_RST	BIT(0)  /* Used to indicate SW reset */
-#define CCU_WDT_RST	BIT(1)  /* Used to indicate WDT reset */
-#define CCU_MIASS_RST	BIT(2)  /* Used to indicate UIA shutdown reset */
-#define CCU_SRECC_RST	BIT(3)  /* Used to indicate SRAM ECC reset */
+#define CCU_SW_RST BIT(0) /* Used to indicate SW reset */
+#define CCU_WDT_RST BIT(1) /* Used to indicate WDT reset */
+#define CCU_MIASS_RST BIT(2) /* Used to indicate UIA shutdown reset */
+#define CCU_SRECC_RST BIT(3) /* Used to indicate SRAM ECC reset */
 
 /* Fabric Agent Status register */
-#define FABRIC_AGENT_STATUS		REG32(ISH_OCP_BASE + 0x7828)
+#define FABRIC_AGENT_STATUS REG32(ISH_OCP_BASE + 0x7828)
 #define FABRIC_INBAND_ERR_SECONDARY_BIT BIT(29)
-#define FABRIC_INBAND_ERR_PRIMARY_BIT	BIT(28)
-#define FABRIC_M_ERR_BIT		BIT(24)
-#define FABRIC_MIA_STATUS_BIT_ERR	(FABRIC_INBAND_ERR_SECONDARY_BIT | \
-					 FABRIC_INBAND_ERR_PRIMARY_BIT | \
-					 FABRIC_M_ERR_BIT)
+#define FABRIC_INBAND_ERR_PRIMARY_BIT BIT(28)
+#define FABRIC_M_ERR_BIT BIT(24)
+#define FABRIC_MIA_STATUS_BIT_ERR                                          \
+	(FABRIC_INBAND_ERR_SECONDARY_BIT | FABRIC_INBAND_ERR_PRIMARY_BIT | \
+	 FABRIC_M_ERR_BIT)
 
 /* CSME Registers */
 #ifdef CHIP_VARIANT_ISH5P4
-#define SEC_OFFSET			0x10000
+#define SEC_OFFSET 0x10000
 #else
-#define SEC_OFFSET			0x0
+#define SEC_OFFSET 0x0
 #endif
-#define ISH_RST_REG			REG32(ISH_IPC_BASE + SEC_OFFSET + 0x44)
-#define IPC_PIMR_CIM_SEC		(ISH_IPC_BASE + SEC_OFFSET + 0x10)
+#define ISH_RST_REG REG32(ISH_IPC_BASE + SEC_OFFSET + 0x44)
+#define IPC_PIMR_CIM_SEC (ISH_IPC_BASE + SEC_OFFSET + 0x10)
 
 /* IOAPIC registers */
-#define IOAPIC_IDX			REG32(ISH_IOAPIC_BASE + 0x0)
-#define IOAPIC_WDW			REG32(ISH_IOAPIC_BASE + 0x10)
+#define IOAPIC_IDX REG32(ISH_IOAPIC_BASE + 0x0)
+#define IOAPIC_WDW REG32(ISH_IOAPIC_BASE + 0x10)
 /* Bare address needed for assembler (ISH_IOAPIC_BASE + 0x40) */
-#define IOAPIC_EOI_REG_ADDR		0xFEC00040
-#define IOAPIC_EOI_REG			REG32(IOAPIC_EOI_REG_ADDR)
-
-#define IOAPIC_VERSION			(0x1)
-#define IOAPIC_IOREDTBL			(0x10)
-#define IOAPIC_REDTBL_DELMOD_FIXED	(0x00000000)
-#define IOAPIC_REDTBL_DESTMOD_PHYS	(0x00000000)
-#define IOAPIC_REDTBL_INTPOL_HIGH	(0x00000000)
-#define IOAPIC_REDTBL_INTPOL_LOW	(0x00002000)
-#define IOAPIC_REDTBL_IRR		(0x00004000)
-#define IOAPIC_REDTBL_TRIGGER_EDGE	(0x00000000)
-#define IOAPIC_REDTBL_TRIGGER_LEVEL	(0x00008000)
-#define IOAPIC_REDTBL_MASK		(0x00010000)
+#define IOAPIC_EOI_REG_ADDR 0xFEC00040
+#define IOAPIC_EOI_REG REG32(IOAPIC_EOI_REG_ADDR)
+
+#define IOAPIC_VERSION (0x1)
+#define IOAPIC_IOREDTBL (0x10)
+#define IOAPIC_REDTBL_DELMOD_FIXED (0x00000000)
+#define IOAPIC_REDTBL_DESTMOD_PHYS (0x00000000)
+#define IOAPIC_REDTBL_INTPOL_HIGH (0x00000000)
+#define IOAPIC_REDTBL_INTPOL_LOW (0x00002000)
+#define IOAPIC_REDTBL_IRR (0x00004000)
+#define IOAPIC_REDTBL_TRIGGER_EDGE (0x00000000)
+#define IOAPIC_REDTBL_TRIGGER_LEVEL (0x00008000)
+#define IOAPIC_REDTBL_MASK (0x00010000)
 
 /* WDT (Watchdog Timer) Registers */
-#define WDT_CONTROL			REG32(ISH_WDT_BASE + 0x0)
-#define WDT_RELOAD			REG32(ISH_WDT_BASE + 0x4)
-#define WDT_VALUES			REG32(ISH_WDT_BASE + 0x8)
-#define WDT_CONTROL_ENABLE_BIT		BIT(17)
+#define WDT_CONTROL REG32(ISH_WDT_BASE + 0x0)
+#define WDT_RELOAD REG32(ISH_WDT_BASE + 0x4)
+#define WDT_VALUES REG32(ISH_WDT_BASE + 0x8)
+#define WDT_CONTROL_ENABLE_BIT BIT(17)
 
 /* LAPIC registers */
 /* Bare address needed for assembler (ISH_LAPIC_BASE + 0xB0) */
-#define LAPIC_EOI_REG_ADDR		0xFEE000B0
-#define LAPIC_EOI_REG			REG32(LAPIC_EOI_REG_ADDR)
-#define LAPIC_ISR_REG			REG32(ISH_LAPIC_BASE + 0x100)
-#define LAPIC_ISR_LAST_REG		REG32(ISH_LAPIC_BASE + 0x170)
-#define LAPIC_IRR_REG			REG32(ISH_LAPIC_BASE + 0x200)
-#define LAPIC_ESR_REG			REG32(ISH_LAPIC_BASE + 0x280)
-#define LAPIC_ERR_RECV_ILLEGAL		BIT(6)
-#define LAPIC_ICR_REG			REG32(ISH_LAPIC_BASE + 0x300)
+#define LAPIC_EOI_REG_ADDR 0xFEE000B0
+#define LAPIC_EOI_REG REG32(LAPIC_EOI_REG_ADDR)
+#define LAPIC_ISR_REG REG32(ISH_LAPIC_BASE + 0x100)
+#define LAPIC_ISR_LAST_REG REG32(ISH_LAPIC_BASE + 0x170)
+#define LAPIC_IRR_REG REG32(ISH_LAPIC_BASE + 0x200)
+#define LAPIC_ESR_REG REG32(ISH_LAPIC_BASE + 0x280)
+#define LAPIC_ERR_RECV_ILLEGAL BIT(6)
+#define LAPIC_ICR_REG REG32(ISH_LAPIC_BASE + 0x300)
 
 /* SRAM control registers */
 #ifndef CHIP_VARIANT_ISH5P4
-#define ISH_SRAM_CTRL_BASE		0x00500000
+#define ISH_SRAM_CTRL_BASE 0x00500000
 #else
-#define ISH_SRAM_CTRL_BASE		0x10500000
+#define ISH_SRAM_CTRL_BASE 0x10500000
 #endif
-#define ISH_SRAM_CTRL_CSFGR		REG32(ISH_SRAM_CTRL_BASE + 0x00)
-#define ISH_SRAM_CTRL_INTR		REG32(ISH_SRAM_CTRL_BASE + 0x04)
-#define ISH_SRAM_CTRL_INTR_MASK	REG32(ISH_SRAM_CTRL_BASE + 0x08)
-#define ISH_SRAM_CTRL_ERASE_CTRL	REG32(ISH_SRAM_CTRL_BASE + 0x0c)
-#define ISH_SRAM_CTRL_ERASE_ADDR	REG32(ISH_SRAM_CTRL_BASE + 0x10)
-#define ISH_SRAM_CTRL_BANK_STATUS	REG32(ISH_SRAM_CTRL_BASE + 0x2c)
+#define ISH_SRAM_CTRL_CSFGR REG32(ISH_SRAM_CTRL_BASE + 0x00)
+#define ISH_SRAM_CTRL_INTR REG32(ISH_SRAM_CTRL_BASE + 0x04)
+#define ISH_SRAM_CTRL_INTR_MASK REG32(ISH_SRAM_CTRL_BASE + 0x08)
+#define ISH_SRAM_CTRL_ERASE_CTRL REG32(ISH_SRAM_CTRL_BASE + 0x0c)
+#define ISH_SRAM_CTRL_ERASE_ADDR REG32(ISH_SRAM_CTRL_BASE + 0x10)
+#define ISH_SRAM_CTRL_BANK_STATUS REG32(ISH_SRAM_CTRL_BASE + 0x2c)
 
 #endif /* __CROS_EC_REGISTERS_H */
diff --git a/chip/ish/system.c b/chip/ish/system.c
index 30a2576e5e..22af124cd9 100644
--- a/chip/ish/system.c
+++ b/chip/ish/system.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,8 +23,8 @@
 #include "util.h"
 
 #define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 int system_is_reboot_warm(void)
 {
@@ -57,8 +57,7 @@ uint32_t chip_read_reset_flags(void)
  * Used when the watchdog timer exceeds max retries and we want to
  * disable ISH completely.
  */
-noreturn
-static void system_halt(void)
+noreturn static void system_halt(void)
 {
 	cflush();
 
@@ -66,9 +65,8 @@ static void system_halt(void)
 		disable_all_interrupts();
 		WDT_CONTROL = 0;
 		CCU_TCG_EN = 1;
-		__asm__ volatile (
-			"cli\n"
-			"hlt\n");
+		__asm__ volatile("cli\n"
+				 "hlt\n");
 	}
 }
 
@@ -90,8 +88,8 @@ void system_reset(int flags)
 	if (flags & SYSTEM_RESET_AP_WATCHDOG) {
 		save_flags |= EC_RESET_FLAG_WATCHDOG;
 		ish_persistent_data.watchdog_counter += 1;
-		if (ish_persistent_data.watchdog_counter
-		    >= CONFIG_WATCHDOG_MAX_RETRIES) {
+		if (ish_persistent_data.watchdog_counter >=
+		    CONFIG_WATCHDOG_MAX_RETRIES) {
 			CPRINTS("Halting ISH due to max watchdog resets");
 			system_halt();
 		}
@@ -175,19 +173,13 @@ void system_set_image_copy(enum ec_image copy)
 {
 }
 
-#define HBW_FABRIC_BASE		0x10000000
-#define PER0_FABRIC_BASE	0x04000000
-#define AGENT_STS		0x28
-#define ERROR_LOG		0x58
+#define HBW_FABRIC_BASE 0x10000000
+#define PER0_FABRIC_BASE 0x04000000
+#define AGENT_STS 0x28
+#define ERROR_LOG 0x58
 
-static uint16_t hbw_ia_offset[] = {
-	0x1000,
-	0x3400,
-	0x3800,
-	0x5000,
-	0x5800,
-	0x6000
-};
+static uint16_t hbw_ia_offset[] = { 0x1000, 0x3400, 0x3800,
+				    0x5000, 0x5800, 0x6000 };
 
 static inline void clear_register(uint32_t reg)
 {
diff --git a/chip/ish/system_state.h b/chip/ish/system_state.h
index 20de1aaf4b..bcffcf49ee 100644
--- a/chip/ish/system_state.h
+++ b/chip/ish/system_state.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,7 @@
 #ifndef __SYSTEM_STATE_H
 #define __SYSTEM_STATE_H
 
-#define HECI_FIXED_SYSTEM_STATE_ADDR				13
+#define HECI_FIXED_SYSTEM_STATE_ADDR 13
 
 struct ss_subsys_device;
 
diff --git a/chip/ish/system_state_subsys.c b/chip/ish/system_state_subsys.c
index 36b79c747a..bfc120ff9b 100644
--- a/chip/ish/system_state_subsys.c
+++ b/chip/ish/system_state_subsys.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,24 +10,23 @@
 
 #ifdef SS_SUBSYSTEM_DEBUG
 #define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_LPC, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_LPC, format, ##args)
 #else
 #define CPUTS(outstr)
 #define CPRINTS(format, args...)
 #define CPRINTF(format, args...)
 #endif
 
-
 /* the following "define"s and structures are from host driver
  * and they are slightly modified for look&feel purpose.
  */
-#define SYSTEM_STATE_SUBSCRIBE		0x1
-#define SYSTEM_STATE_STATUS		0x2
-#define SYSTEM_STATE_QUERY_SUBSCRIBERS	0x3
-#define SYSTEM_STATE_STATE_CHANGE_REQ	0x4
+#define SYSTEM_STATE_SUBSCRIBE 0x1
+#define SYSTEM_STATE_STATUS 0x2
+#define SYSTEM_STATE_QUERY_SUBSCRIBERS 0x3
+#define SYSTEM_STATE_STATE_CHANGE_REQ 0x4
 
-#define SUSPEND_STATE_BIT		BIT(1) /* suspend/resume */
+#define SUSPEND_STATE_BIT BIT(1) /* suspend/resume */
 
 /* Cached state of ISH's requested power rails when AP suspends */
 static uint32_t cached_vnn_request;
@@ -67,7 +66,7 @@ struct ss_state_change_req {
  * "struct ss_subsys_device" in it and calls ss_subsys_register_client() like
  * HECI client.
  */
-#define MAX_SS_CLIENTS				HECI_MAX_NUM_OF_CLIENTS
+#define MAX_SS_CLIENTS HECI_MAX_NUM_OF_CLIENTS
 
 struct ss_subsystem_context {
 	uint32_t registered_state;
@@ -103,7 +102,7 @@ static int ss_subsys_suspend(void)
 	for (i = ss_subsys_ctx.num_of_ss_client - 1; i >= 0; i--) {
 		if (ss_subsys_ctx.clients[i]->cbs->suspend)
 			ss_subsys_ctx.clients[i]->cbs->suspend(
-						ss_subsys_ctx.clients[i]);
+				ss_subsys_ctx.clients[i]);
 	}
 
 	/*
@@ -126,8 +125,7 @@ static int ss_subsys_resume(void)
 	/*
 	 * Restore VNN power request from before suspend.
 	 */
-	if (IS_ENABLED(CHIP_FAMILY_ISH5) &&
-	    cached_vnn_request) {
+	if (IS_ENABLED(CHIP_FAMILY_ISH5) && cached_vnn_request) {
 		/* Request all cached power rails that are not already on. */
 		PMU_VNN_REQ = cached_vnn_request & ~PMU_VNN_REQ;
 		/* Wait for power request to get acknowledged */
@@ -138,7 +136,7 @@ static int ss_subsys_resume(void)
 	for (i = 0; i < ss_subsys_ctx.num_of_ss_client; i++) {
 		if (ss_subsys_ctx.clients[i]->cbs->resume)
 			ss_subsys_ctx.clients[i]->cbs->resume(
-						ss_subsys_ctx.clients[i]);
+				ss_subsys_ctx.clients[i]);
 	}
 
 	return EC_SUCCESS;
diff --git a/chip/ish/uart.c b/chip/ish/uart.c
index 71d8a41397..b1c9493869 100644
--- a/chip/ish/uart.c
+++ b/chip/ish/uart.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,20 +17,14 @@
 #include "system.h"
 
 #define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_LPC, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_LPC, format, ##args)
 
 static const uint32_t baud_conf[][BAUD_TABLE_MAX] = {
-	{B9600, 9600},
-	{B57600, 57600},
-	{B115200, 115200},
-	{B921600, 921600},
-	{B2000000, 2000000},
-	{B3000000, 3000000},
-	{B3250000, 3250000},
-	{B3500000, 3500000},
-	{B4000000, 4000000},
-	{B19200, 19200},
+	{ B9600, 9600 },       { B57600, 57600 },     { B115200, 115200 },
+	{ B921600, 921600 },   { B2000000, 2000000 }, { B3000000, 3000000 },
+	{ B3250000, 3250000 }, { B3500000, 3500000 }, { B4000000, 4000000 },
+	{ B19200, 19200 },
 };
 
 static struct uart_ctx uart_ctx[UART_DEVICES] = {
@@ -146,7 +140,7 @@ static int uart_return_baud_rate_by_id(int baud_rate_id)
 
 static void uart_hw_init(enum UART_PORT id)
 {
-	uint32_t divisor;	/* baud rate divisor */
+	uint32_t divisor; /* baud rate divisor */
 	uint8_t mcr = 0;
 	uint8_t fcr = 0;
 	struct uart_ctx *ctx = &uart_ctx[id];
@@ -156,7 +150,8 @@ static void uart_hw_init(enum UART_PORT id)
 	divisor = (ctx->input_freq / ctx->baud_rate) >> 4;
 	if (IS_ENABLED(CONFIG_ISH_DW_UART)) {
 		/* calculate the fractional part */
-		fraction = ceil_for(ctx->input_freq, ctx->baud_rate) - (divisor << 4);
+		fraction = ceil_for(ctx->input_freq, ctx->baud_rate) -
+			   (divisor << 4);
 	} else {
 		MUL(ctx->id) = (divisor * ctx->baud_rate);
 		DIV(ctx->id) = (ctx->input_freq / 16);
@@ -189,8 +184,7 @@ static void uart_hw_init(enum UART_PORT id)
 		fcr = FCR_FIFO_SIZE_64 | FCR_ITL_FIFO_64_BYTES_1;
 
 	/* configure FIFOs */
-	FCR(ctx->id) = (fcr | FCR_FIFO_ENABLE
-			| FCR_RESET_RX | FCR_RESET_TX);
+	FCR(ctx->id) = (fcr | FCR_FIFO_ENABLE | FCR_RESET_RX | FCR_RESET_TX);
 
 	if (!IS_ENABLED(CONFIG_ISH_DW_UART))
 		/* enable UART unit */
@@ -229,8 +223,8 @@ static void uart_stop_hw(enum UART_PORT id)
 
 	if (!IS_ENABLED(CONFIG_ISH_DW_UART)) {
 		/* Manually clearing the fifo from possible noise.
-	 	 * Entering D0i3 when fifo is not cleared may result in a hang.
-	 	 */
+		 * Entering D0i3 when fifo is not cleared may result in a hang.
+		 */
 		fifo_len = (FOR(id) & FOR_OCCUPANCY_MASK) >> FOR_OCCUPANCY_OFFS;
 
 		for (i = 0; i < fifo_len; i++)
@@ -280,10 +274,10 @@ static void uart_drv_init(void)
 
 	if (!IS_ENABLED(CONFIG_ISH_DW_UART))
 		/* Enable HSU global interrupts (DMA/U0/U1) and set PMEN bit
-	 	 * to allow PMU to clock gate ISH
-	 	 */
-		HSU_REG_GIEN = (GIEN_DMA_EN | GIEN_UART0_EN
-				| GIEN_UART1_EN | GIEN_PWR_MGMT);
+		 * to allow PMU to clock gate ISH
+		 */
+		HSU_REG_GIEN = (GIEN_DMA_EN | GIEN_UART0_EN | GIEN_UART1_EN |
+				GIEN_PWR_MGMT);
 
 	task_enable_irq(ISH_DEBUG_UART_IRQ);
 }
diff --git a/chip/ish/uart_defs.h b/chip/ish/uart_defs.h
index 5bfc7b9a6b..1fc36b7adc 100644
--- a/chip/ish/uart_defs.h
+++ b/chip/ish/uart_defs.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,344 +12,331 @@
 #include <stddef.h>
 #include "atomic.h"
 
-#define UART_ERROR		-1
-#define UART_BUSY		-2
+#define UART_ERROR -1
+#define UART_BUSY -2
 #ifdef CHIP_VARIANT_ISH5P4
-#define UART0_OFFS		(0x00)
-#define UART1_OFFS		(0x2000)
-#define UART2_OFFS		(0x4000)
+#define UART0_OFFS (0x00)
+#define UART1_OFFS (0x2000)
+#define UART2_OFFS (0x4000)
 #else
-#define UART0_OFFS		(0x80)
-#define UART1_OFFS		(0x100)
-#define UART2_OFFS		(0x180)
+#define UART0_OFFS (0x80)
+#define UART1_OFFS (0x100)
+#define UART2_OFFS (0x180)
 #endif
 
-#define HSU_BASE		ISH_UART_BASE
-#define UART0_BASE		(ISH_UART_BASE + UART0_OFFS)
-#define UART1_BASE		(ISH_UART_BASE + UART1_OFFS)
-#define UART2_BASE		(ISH_UART_BASE + UART2_OFFS)
+#define HSU_BASE ISH_UART_BASE
+#define UART0_BASE (ISH_UART_BASE + UART0_OFFS)
+#define UART1_BASE (ISH_UART_BASE + UART1_OFFS)
+#define UART2_BASE (ISH_UART_BASE + UART2_OFFS)
 
-#define UART_REG(size, name, n)					\
-	REG##size(uart_ctx[n].base +					\
+#define UART_REG(size, name, n)      \
+	REG##size(uart_ctx[n].base + \
 		  UART_OFFSET_##name * uart_ctx[n].addr_interval)
 
 /* Register accesses */
-#define LSR(n)			UART_REG(8, LSR, n)
-#define THR(n)			UART_REG(8, THR, n)
-#define RBR(n)			UART_REG(8, RBR, n)
-#define DLL(n)			UART_REG(8, DLL, n)
-#define DLH(n)			UART_REG(8, DLH, n)
-#define IER(n)			UART_REG(8, IER, n)
-#define IIR(n)			UART_REG(8, IIR, n)
-#define FCR(n)			UART_REG(8, FCR, n)
-#define LCR(n)			UART_REG(8, LCR, n)
-#define MCR(n)			UART_REG(8, MCR, n)
-#define MSR(n)			UART_REG(8, MSR, n)
-#define DLF(n)			UART_REG(8, DLF, n)
-#define FOR(n)			UART_REG(32, FOR, n)
-#define ABR(n)			UART_REG(32, ABR, n)
-#define PS(n)			UART_REG(32, PS, n)
-#define MUL(n)			UART_REG(32, MUL, n)
-#define DIV(n)			UART_REG(32, DIV, n)
+#define LSR(n) UART_REG(8, LSR, n)
+#define THR(n) UART_REG(8, THR, n)
+#define RBR(n) UART_REG(8, RBR, n)
+#define DLL(n) UART_REG(8, DLL, n)
+#define DLH(n) UART_REG(8, DLH, n)
+#define IER(n) UART_REG(8, IER, n)
+#define IIR(n) UART_REG(8, IIR, n)
+#define FCR(n) UART_REG(8, FCR, n)
+#define LCR(n) UART_REG(8, LCR, n)
+#define MCR(n) UART_REG(8, MCR, n)
+#define MSR(n) UART_REG(8, MSR, n)
+#define DLF(n) UART_REG(8, DLF, n)
+#define FOR(n) UART_REG(32, FOR, n)
+#define ABR(n) UART_REG(32, ABR, n)
+#define PS(n) UART_REG(32, PS, n)
+#define MUL(n) UART_REG(32, MUL, n)
+#define DIV(n) UART_REG(32, DIV, n)
 
 #ifdef CONFIG_ISH_DW_UART
 /*
  * RBR: Receive Buffer register     (BLAB bit = 0)
  */
-#define UART_OFFSET_RBR		(0x00)
+#define UART_OFFSET_RBR (0x00)
 
 /*
  * THR: Transmit Holding register   (BLAB bit = 0)
  */
-#define UART_OFFSET_THR		(0x00)
+#define UART_OFFSET_THR (0x00)
 
 /*
  * DLL: Divisor Latch Reg. low byte  (BLAB bit = 1)
  * baud rate = (serial clock freq) / (16 * divisor)
  */
-#define UART_OFFSET_DLL		(0x00)
+#define UART_OFFSET_DLL (0x00)
 
 /*
  * DLH: Divisor Latch Reg. high byte (BLAB bit = 1)
  */
-#define UART_OFFSET_DLH		(0x04)
+#define UART_OFFSET_DLH (0x04)
 
 /*
  * IER: Interrupt Enable register   (BLAB bit = 0)
  */
-#define UART_OFFSET_IER		(0x04)
+#define UART_OFFSET_IER (0x04)
 
-#define IER_RECV		(0x01)  /* Receive Data Available */
-#define IER_TDRQ		(0x02)  /* Transmit Holding Register Empty */
-#define IER_LINE_STAT		(0x04)  /* Receiver Line Status */
-#define IER_MODEM		(0x08)  /* Modem Status */
-#define IER_PTIME		(0x80)  /* Programmable THRE Interrupt Mode Enable */
+#define IER_RECV (0x01) /* Receive Data Available */
+#define IER_TDRQ (0x02) /* Transmit Holding Register Empty */
+#define IER_LINE_STAT (0x04) /* Receiver Line Status */
+#define IER_MODEM (0x08) /* Modem Status */
+#define IER_PTIME (0x80) /* Programmable THRE Interrupt Mode Enable */
 
 /*
  * IIR: Interrupt ID register
  */
-#define UART_OFFSET_IIR		(0x08)
-
-#define IIR_MODEM		(0x00)  /* Prio: 4 */
-#define IIR_NO_INTR		(0x01)
-#define IIR_THRE		(0x02)  /* Prio: 3 */
-#define IIR_RECV_DATA		(0x04)  /* Prio: 2 */
-#define IIR_LINE_STAT		(0x06)  /* Prio: 1 */
-#define IIR_BUSY		(0x07)  /* Prio: 5 */
-#define IIR_TIME_OUT		(0x0C)  /* Prio: 2 */
-#define IIR_SOURCE		(0x0F)
+#define UART_OFFSET_IIR (0x08)
 
+#define IIR_MODEM (0x00) /* Prio: 4 */
+#define IIR_NO_INTR (0x01)
+#define IIR_THRE (0x02) /* Prio: 3 */
+#define IIR_RECV_DATA (0x04) /* Prio: 2 */
+#define IIR_LINE_STAT (0x06) /* Prio: 1 */
+#define IIR_BUSY (0x07) /* Prio: 5 */
+#define IIR_TIME_OUT (0x0C) /* Prio: 2 */
+#define IIR_SOURCE (0x0F)
 
 /*
  * FCR: FIFO Control register (FIFO_MODE != NONE)
  */
-#define UART_OFFSET_FCR		(0x08)
+#define UART_OFFSET_FCR (0x08)
 
-#define FIFO_SIZE		64
-#define FCR_FIFO_ENABLE		(0x01)
-#define FCR_RESET_RX		(0x02)
-#define FCR_RESET_TX		(0x04)
-#define FCR_DMA_MODE		(0x08)
+#define FIFO_SIZE 64
+#define FCR_FIFO_ENABLE (0x01)
+#define FCR_RESET_RX (0x02)
+#define FCR_RESET_TX (0x04)
+#define FCR_DMA_MODE (0x08)
 
 /*
  * LCR: Line Control register
  */
-#define UART_OFFSET_LCR		(0x0c)
+#define UART_OFFSET_LCR (0x0c)
 
-#define LCR_5BIT_CHR		(0x00)
-#define LCR_6BIT_CHR		(0x01)
-#define LCR_7BIT_CHR		(0x02)
-#define LCR_8BIT_CHR		(0x03)
-#define LCR_BIT_CHR_MASK	(0x03)
+#define LCR_5BIT_CHR (0x00)
+#define LCR_6BIT_CHR (0x01)
+#define LCR_7BIT_CHR (0x02)
+#define LCR_8BIT_CHR (0x03)
+#define LCR_BIT_CHR_MASK (0x03)
 
-#define LCR_STOP		BIT(2)  /* 0: 1 stop bit, 1: 1.5/2 */
-#define LCR_PEN			BIT(3)  /* Parity Enable */
-#define LCR_EPS			BIT(4)  /* Even Parity Select */
-#define LCR_SP			BIT(5)  /* Stick Parity */
-#define LCR_BC			BIT(6)  /* Break Control */
-#define LCR_DLAB		BIT(7)  /* Divisor Latch Access */
+#define LCR_STOP BIT(2) /* 0: 1 stop bit, 1: 1.5/2 */
+#define LCR_PEN BIT(3) /* Parity Enable */
+#define LCR_EPS BIT(4) /* Even Parity Select */
+#define LCR_SP BIT(5) /* Stick Parity */
+#define LCR_BC BIT(6) /* Break Control */
+#define LCR_DLAB BIT(7) /* Divisor Latch Access */
 
 /*
  * MCR: Modem Control register
  */
-#define UART_OFFSET_MCR		(0x10)
-#define MCR_DTR			(0x1)     /* Data terminal ready */
-#define MCR_RTS			(0x2)     /* Request to send */
-#define MCR_LOOP		(0x10)    /* LoopBack bit*/
+#define UART_OFFSET_MCR (0x10)
+#define MCR_DTR (0x1) /* Data terminal ready */
+#define MCR_RTS (0x2) /* Request to send */
+#define MCR_LOOP (0x10) /* LoopBack bit*/
 
-#define MCR_INTR_ENABLE		(0x08)    /* User-designated OUT2 */
-#define MCR_AUTO_FLOW_EN	(0x20)
+#define MCR_INTR_ENABLE (0x08) /* User-designated OUT2 */
+#define MCR_AUTO_FLOW_EN (0x20)
 
 /*
  * LSR: Line Status register
  */
-#define UART_OFFSET_LSR		(0x14)
+#define UART_OFFSET_LSR (0x14)
 
-#define LSR_DR			(0x01)         /* Data Ready */
-#define LSR_OE			(0x02)         /* Overrun error */
-#define LSR_PE			(0x04)         /* Parity error */
-#define LSR_FE			(0x08)         /* Framing error */
-#define LSR_BI			(0x10)         /* Breaking interrupt */
-#define LSR_TDRQ		(0x20)       /* Transmit Holding Register Empty */
-#define LSR_TEMT		(0x40)       /* Transmitter empty */
+#define LSR_DR (0x01) /* Data Ready */
+#define LSR_OE (0x02) /* Overrun error */
+#define LSR_PE (0x04) /* Parity error */
+#define LSR_FE (0x08) /* Framing error */
+#define LSR_BI (0x10) /* Breaking interrupt */
+#define LSR_TDRQ (0x20) /* Transmit Holding Register Empty */
+#define LSR_TEMT (0x40) /* Transmitter empty */
 
 /*
  * MSR: Modem Status register
  */
-#define UART_OFFSET_MSR		(0x18)
+#define UART_OFFSET_MSR (0x18)
 
-#define MSR_CTS			BIT(4) /* Clear To Send signal */
+#define MSR_CTS BIT(4) /* Clear To Send signal */
 
 /*
  * TFL: Transmit FIFO Level
  */
-#define UART_OFFSET_TFL		(0x80)
+#define UART_OFFSET_TFL (0x80)
 
 /*
  * RFL: Receive FIFO Level
  */
-#define UART_OFFSET_RFL		(0x84)
+#define UART_OFFSET_RFL (0x84)
 #else
 /* RBR: Receive Buffer register     (BLAB bit = 0)  */
-#define UART_OFFSET_RBR	(0)
+#define UART_OFFSET_RBR (0)
 /* THR: Transmit Holding register   (BLAB bit = 0)  */
-#define UART_OFFSET_THR	(0)
+#define UART_OFFSET_THR (0)
 /* IER: Interrupt Enable register   (BLAB bit = 0)  */
-#define UART_OFFSET_IER	(1)
+#define UART_OFFSET_IER (1)
 
 /* FCR: FIFO Control register */
-#define UART_OFFSET_FCR	(2)
-#define FCR_FIFO_ENABLE	BIT(0)
-#define FCR_RESET_RX		BIT(1)
-#define FCR_RESET_TX		BIT(2)
+#define UART_OFFSET_FCR (2)
+#define FCR_FIFO_ENABLE BIT(0)
+#define FCR_RESET_RX BIT(1)
+#define FCR_RESET_TX BIT(2)
 
 /* LCR: Line Control register */
-#define UART_OFFSET_LCR	(3)
-#define LCR_DLAB		(0x80)
-#define LCR_5BIT_CHR		(0x00)
-#define LCR_6BIT_CHR		(0x01)
-#define LCR_7BIT_CHR		(0x02)
-#define LCR_8BIT_CHR		(0x03)
-#define LCR_BIT_CHR_MASK	(0x03)
-#define LCR_SB			(0x40)	/* Set Break */
+#define UART_OFFSET_LCR (3)
+#define LCR_DLAB (0x80)
+#define LCR_5BIT_CHR (0x00)
+#define LCR_6BIT_CHR (0x01)
+#define LCR_7BIT_CHR (0x02)
+#define LCR_8BIT_CHR (0x03)
+#define LCR_BIT_CHR_MASK (0x03)
+#define LCR_SB (0x40) /* Set Break */
 
 /* MCR: Modem Control register */
-#define UART_OFFSET_MCR	(4)
-#define MCR_DTR		BIT(0)
-#define MCR_RTS		BIT(1)
-#define MCR_LOO		BIT(4)
-#define MCR_INTR_ENABLE	BIT(3)
-#define MCR_AUTO_FLOW_EN	BIT(5)
+#define UART_OFFSET_MCR (4)
+#define MCR_DTR BIT(0)
+#define MCR_RTS BIT(1)
+#define MCR_LOO BIT(4)
+#define MCR_INTR_ENABLE BIT(3)
+#define MCR_AUTO_FLOW_EN BIT(5)
 
 /* LSR: Line Status register */
-#define UART_OFFSET_LSR	(5)
-#define LSR_DR			BIT(0)	/* Data Ready */
-#define LSR_OE			BIT(1)	/* Overrun error */
-#define LSR_PE			BIT(2)	/* Parity error */
-#define LSR_FE			BIT(3)	/* Framing error */
-#define LSR_BI			BIT(4)	/* Breaking interrupt */
-#define LSR_THR_EMPTY		BIT(5)	/* Non FIFO mode: Transmit holding
-					 * register empty
-					 */
-#define LSR_TDRQ		BIT(5)	/* FIFO mode: Transmit Data request */
-#define LSR_TEMT		BIT(6)	/* Transmitter empty */
+#define UART_OFFSET_LSR (5)
+#define LSR_DR BIT(0) /* Data Ready */
+#define LSR_OE BIT(1) /* Overrun error */
+#define LSR_PE BIT(2) /* Parity error */
+#define LSR_FE BIT(3) /* Framing error */
+#define LSR_BI BIT(4) /* Breaking interrupt */
+#define LSR_THR_EMPTY                             \
+	BIT(5) /* Non FIFO mode: Transmit holding \
+		* register empty                  \
+		*/
+#define LSR_TDRQ BIT(5) /* FIFO mode: Transmit Data request */
+#define LSR_TEMT BIT(6) /* Transmitter empty */
 
 #define FCR_ITL_FIFO_64_BYTES_56 (BIT(6) | BIT(7))
 
-#define IER_RECV		BIT(0)
-#define IER_TDRQ		BIT(1)
-#define IER_LINE_STAT		BIT(2)
+#define IER_RECV BIT(0)
+#define IER_TDRQ BIT(1)
+#define IER_LINE_STAT BIT(2)
 
-#define UART_OFFSET_IIR	(2)
+#define UART_OFFSET_IIR (2)
 /* MSR: Modem Status register */
-#define UART_OFFSET_MSR	(6)
+#define UART_OFFSET_MSR (6)
 
 /* DLL: Divisor Latch Reg. low byte  (BLAB bit = 1) */
-#define UART_OFFSET_DLL	(0)
+#define UART_OFFSET_DLL (0)
 
 /* DLH: Divisor Latch Reg. high byte (BLAB bit = 1) */
-#define UART_OFFSET_DLH	(1)
+#define UART_OFFSET_DLH (1)
 #endif
 
 /*
  * DLF: Divisor Latch Fraction Register
  */
-#define UART_OFFSET_DLF		(0xC0)
+#define UART_OFFSET_DLF (0xC0)
 
 /* FOR: Fifo O Register (ISH only) */
-#define UART_OFFSET_FOR	(0x20)
-#define FOR_OCCUPANCY_OFFS	0
-#define FOR_OCCUPANCY_MASK	0x7F
+#define UART_OFFSET_FOR (0x20)
+#define FOR_OCCUPANCY_OFFS 0
+#define FOR_OCCUPANCY_MASK 0x7F
 
 /* ABR: Auto-Baud Control Register (ISH only) */
-#define UART_OFFSET_ABR	(0x24)
-#define ABR_UUE		BIT(4)
+#define UART_OFFSET_ABR (0x24)
+#define ABR_UUE BIT(4)
 
 /* Pre-Scalar Register (ISH only) */
-#define UART_OFFSET_PS		(0x30)
+#define UART_OFFSET_PS (0x30)
 
 /* DDS registers (ISH only) */
-#define UART_OFFSET_MUL	(0x34)
-#define UART_OFFSET_DIV	(0x38)
+#define UART_OFFSET_MUL (0x34)
+#define UART_OFFSET_DIV (0x38)
 
-#define FCR_FIFO_SIZE_16	(0x00)
-#define FCR_FIFO_SIZE_64	(0x20)
-#define FCR_ITL_FIFO_64_BYTES_1	(0x00)
+#define FCR_FIFO_SIZE_16 (0x00)
+#define FCR_FIFO_SIZE_64 (0x20)
+#define FCR_ITL_FIFO_64_BYTES_1 (0x00)
 
 /* tx empty trigger(TET) */
-#define FCR_TET_EMPTY		(0x00)
-#define FCR_TET_2CHAR		(0x10)
-#define FCR_TET_QTR_FULL	(0x20)
-#define FCR_TET_HALF_FULL	(0x30)
+#define FCR_TET_EMPTY (0x00)
+#define FCR_TET_2CHAR (0x10)
+#define FCR_TET_QTR_FULL (0x20)
+#define FCR_TET_HALF_FULL (0x30)
 
 /* receive trigger(RT) */
-#define FCR_RT_1CHAR		(0x00)
-#define FCR_RT_QTR_FULL		(0x40)
-#define FCR_RT_HALF_FULL	(0x80)
-#define FCR_RT_2LESS_FULL	(0xc0)
+#define FCR_RT_1CHAR (0x00)
+#define FCR_RT_QTR_FULL (0x40)
+#define FCR_RT_HALF_FULL (0x80)
+#define FCR_RT_2LESS_FULL (0xc0)
 
 /* G_IEN: Global Interrupt Enable  (ISH only) */
-#define HSU_REG_GIEN		REG32(HSU_BASE + 0x0)
-#define HSU_REG_GIST		REG32(HSU_BASE + 0x4)
-
-#define GIEN_PWR_MGMT		BIT(24)
-#define GIEN_DMA_EN		BIT(5)
-#define GIEN_UART2_EN		BIT(2)
-#define GIEN_UART1_EN		BIT(1)
-#define GIEN_UART0_EN		BIT(0)
-#define GIST_DMA_EN		BIT(5)
-#define GIST_UART2_EN		BIT(2)
-#define GIST_UART1_EN		BIT(1)
-#define GIST_UART0_EN		BIT(0)
-#define GIST_UARTx_EN		(GIST_UART0_EN|GIST_UART1_EN|GIST_UART2_EN)
+#define HSU_REG_GIEN REG32(HSU_BASE + 0x0)
+#define HSU_REG_GIST REG32(HSU_BASE + 0x4)
+
+#define GIEN_PWR_MGMT BIT(24)
+#define GIEN_DMA_EN BIT(5)
+#define GIEN_UART2_EN BIT(2)
+#define GIEN_UART1_EN BIT(1)
+#define GIEN_UART0_EN BIT(0)
+#define GIST_DMA_EN BIT(5)
+#define GIST_UART2_EN BIT(2)
+#define GIST_UART1_EN BIT(1)
+#define GIST_UART0_EN BIT(0)
+#define GIST_UARTx_EN (GIST_UART0_EN | GIST_UART1_EN | GIST_UART2_EN)
 
 /* UART config flag, send to sc_io_control if the current UART line has HW
  * flow control lines connected.
  */
-#define UART_CONFIG_HW_FLOW_CONTROL		BIT(0)
+#define UART_CONFIG_HW_FLOW_CONTROL BIT(0)
 
 /* UART config flag for sc_io_control.  If defined a sc_io_event_rx_msg is
  * raised only when the rx buffer is completely full. Otherwise, the event
  * is raised after a timeout is received on the UART line,
  * and all data received until now is provided.
  */
-#define UART_CONFIG_DELIVER_FULL_RX_BUF	BIT(1)
+#define UART_CONFIG_DELIVER_FULL_RX_BUF BIT(1)
 
 /* UART config flag for sc_io_control.  If defined a sc_io_event_rx_buf_depleted
  * is raised when all rx buffers that were added are full. Otherwise, no
  * event is raised.
  */
-#define UART_CONFIG_ANNOUNCE_DEPLETED_BUF	BIT(2)
-
-#define UART_INT_DEVICES		3
-#define UART_EXT_DEVICES		8
-#define UART_DEVICES			UART_INT_DEVICES
-#define UART_ISH_ADDR_INTERVAL		1
-
-#define B9600				0x0000d
-#define B57600				0x00000018
-#define B115200			0x00000011
-#define B921600			0x00000012
-#define B2000000			0x00000013
-#define B3000000			0x00000014
-#define B3250000			0x00000015
-#define B3500000			0x00000016
-#define B4000000			0x00000017
-#define B19200				0x0000e
-#define B38400				0x0000f
+#define UART_CONFIG_ANNOUNCE_DEPLETED_BUF BIT(2)
+
+#define UART_INT_DEVICES 3
+#define UART_EXT_DEVICES 8
+#define UART_DEVICES UART_INT_DEVICES
+#define UART_ISH_ADDR_INTERVAL 1
+
+#define B9600 0x0000d
+#define B57600 0x00000018
+#define B115200 0x00000011
+#define B921600 0x00000012
+#define B2000000 0x00000013
+#define B3000000 0x00000014
+#define B3250000 0x00000015
+#define B3500000 0x00000016
+#define B4000000 0x00000017
+#define B19200 0x0000e
+#define B38400 0x0000f
 
 /* KHZ, MHZ */
-#define KHZ(x)				((x) * 1000)
-#define MHZ(x)				(KHZ(x) * 1000)
+#define KHZ(x) ((x)*1000)
+#define MHZ(x) (KHZ(x) * 1000)
 #if defined(CHIP_VARIANT_ISH5P4)
 /* Change to 100MHZ in real silicon platform */
-#define UART_ISH_INPUT_FREQ		MHZ(100)
+#define UART_ISH_INPUT_FREQ MHZ(100)
 #elif defined(CHIP_FAMILY_ISH3) || defined(CHIP_FAMILY_ISH5)
-#define UART_ISH_INPUT_FREQ		MHZ(120)
+#define UART_ISH_INPUT_FREQ MHZ(120)
 #elif defined(CHIP_FAMILY_ISH4)
-#define UART_ISH_INPUT_FREQ		MHZ(100)
+#define UART_ISH_INPUT_FREQ MHZ(100)
 #endif
-#define UART_DEFAULT_BAUD_RATE		115200
-#define UART_STATE_CG			BIT(UART_OP_CG)
+#define UART_DEFAULT_BAUD_RATE 115200
+#define UART_STATE_CG BIT(UART_OP_CG)
 
-enum UART_PORT {
-	UART_PORT_0,
-	UART_PORT_1,
-	UART_PORT_MAX
-};
+enum UART_PORT { UART_PORT_0, UART_PORT_1, UART_PORT_MAX };
 
-enum UART_OP {
-	UART_OP_READ,
-	UART_OP_WRITE,
-	UART_OP_CG,
-	UART_OP_MAX
-};
+enum UART_OP { UART_OP_READ, UART_OP_WRITE, UART_OP_CG, UART_OP_MAX };
 
-enum {
-	BAUD_IDX,
-	BAUD_SPEED,
-	BAUD_TABLE_MAX
-};
+enum { BAUD_IDX, BAUD_SPEED, BAUD_TABLE_MAX };
 
 struct uart_ctx {
 	uint32_t id;
diff --git a/chip/ish/util/pack_ec.py b/chip/ish/util/pack_ec.py
index bd9b823cab..7f381005f0 100755
--- a/chip/ish/util/pack_ec.py
+++ b/chip/ish/util/pack_ec.py
@@ -1,13 +1,9 @@
 #!/usr/bin/env python3
 # -*- coding: utf-8 -*-"
 
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
 
 # A script to pack EC binary with manifest header according to
 # Based on 607297_Host_ISH_Firmware_Load_Chrome_OS_SAS_Rev0p5.pdf,
@@ -28,85 +24,104 @@ MANIFEST_ENTRY_SIZE = 0x80
 HEADER_SIZE = 0x1000
 PAGE_SIZE = 0x1000
 
+
 def parseargs():
-  parser = argparse.ArgumentParser()
-  parser.add_argument("-k", "--kernel",
-                      help="EC kernel binary to pack, \
-                      usually ec.RW.bin or ec.RW.flat.",
-                      required=True)
-  parser.add_argument("--kernel-size", type=int,
-                      help="Size of EC kernel image",
-                      required=True)
-  parser.add_argument("-a", "--aon",
-                      help="EC aontask binary to pack, \
-                      usually ish_aontask.bin.",
-                      required=False)
-  parser.add_argument("--aon-size", type=int,
-                      help="Size of EC aontask image",
-                      required=False)
-  parser.add_argument("-o", "--output",
-                      help="Output flash binary file")
-
-  return parser.parse_args()
+    parser = argparse.ArgumentParser()
+    parser.add_argument(
+        "-k",
+        "--kernel",
+        help="EC kernel binary to pack, usually ec.RW.bin or ec.RW.flat.",
+        required=True,
+    )
+    parser.add_argument(
+        "--kernel-size", type=int, help="Size of EC kernel image", required=True
+    )
+    parser.add_argument(
+        "-a",
+        "--aon",
+        help="EC aontask binary to pack, usually ish_aontask.bin.",
+        required=False,
+    )
+    parser.add_argument(
+        "--aon-size", type=int, help="Size of EC aontask image", required=False
+    )
+    parser.add_argument("-o", "--output", help="Output flash binary file")
+
+    return parser.parse_args()
+
 
 def gen_manifest(ext_id, comp_app_name, code_offset, module_size):
-  """Returns a binary blob that represents a manifest entry"""
-  m = bytearray(MANIFEST_ENTRY_SIZE)
+    """Returns a binary blob that represents a manifest entry"""
+    m = bytearray(MANIFEST_ENTRY_SIZE)
 
-  # 4 bytes of ASCII encode ID (little endian)
-  struct.pack_into('<4s', m, 0, ext_id)
-  # 8 bytes of ASCII encode ID (little endian)
-  struct.pack_into('<8s', m, 32, comp_app_name)
-  # 4 bytes of code offset (little endian)
-  struct.pack_into('<I', m, 96, code_offset)
-  # 2 bytes of module in page size increments (little endian)
-  struct.pack_into('<H', m, 100, module_size)
+    # 4 bytes of ASCII encode ID (little endian)
+    struct.pack_into("<4s", m, 0, ext_id)
+    # 8 bytes of ASCII encode ID (little endian)
+    struct.pack_into("<8s", m, 32, comp_app_name)
+    # 4 bytes of code offset (little endian)
+    struct.pack_into("<I", m, 96, code_offset)
+    # 2 bytes of module in page size increments (little endian)
+    struct.pack_into("<H", m, 100, module_size)
+
+    return m
 
-  return m
 
 def roundup_page(size):
-  """Returns roundup-ed page size from size of bytes"""
-  return int(size / PAGE_SIZE) + (size % PAGE_SIZE > 0)
+    """Returns roundup-ed page size from size of bytes"""
+    return int(size / PAGE_SIZE) + (size % PAGE_SIZE > 0)
+
 
 def main():
-  args = parseargs()
-  print("    Packing EC image file for ISH")
-
-  with open(args.output, 'wb') as f:
-    print("      kernel binary size:", args.kernel_size)
-    kern_rdup_pg_size = roundup_page(args.kernel_size)
-    # Add manifest for main ISH binary
-    f.write(gen_manifest(b'ISHM', b'ISH_KERN', HEADER_SIZE, kern_rdup_pg_size))
-
-    if args.aon is not None:
-      print("      AON binary size:   ", args.aon_size)
-      aon_rdup_pg_size = roundup_page(args.aon_size)
-      # Add manifest for aontask binary
-      f.write(gen_manifest(b'ISHM', b'AON_TASK',
-                           (HEADER_SIZE + kern_rdup_pg_size * PAGE_SIZE -
-                            MANIFEST_ENTRY_SIZE), aon_rdup_pg_size))
-
-    # Add manifest that signals end of manifests
-    f.write(gen_manifest(b'ISHE', b'', 0, 0))
-
-    # Pad the remaining HEADER with 0s
-    if args.aon is not None:
-      f.write(b'\x00' * (HEADER_SIZE - (MANIFEST_ENTRY_SIZE * 3)))
-    else:
-      f.write(b'\x00' * (HEADER_SIZE - (MANIFEST_ENTRY_SIZE * 2)))
-
-    # Append original kernel image
-    with open(args.kernel, 'rb') as in_file:
-      f.write(in_file.read())
-    # Filling padings due to size round up as pages
-    f.write(b'\x00' * (kern_rdup_pg_size * PAGE_SIZE - args.kernel_size))
-
-    if args.aon is not None:
-      # Append original aon image
-      with open(args.aon, 'rb') as in_file:
-        f.write(in_file.read())
-      # Filling padings due to size round up as pages
-      f.write(b'\x00' * (aon_rdup_pg_size * PAGE_SIZE - args.aon_size))
-
-if __name__ == '__main__':
-  main()
+    args = parseargs()
+    print("    Packing EC image file for ISH")
+
+    with open(args.output, "wb") as f:
+        print("      kernel binary size:", args.kernel_size)
+        kern_rdup_pg_size = roundup_page(args.kernel_size)
+        # Add manifest for main ISH binary
+        f.write(
+            gen_manifest(b"ISHM", b"ISH_KERN", HEADER_SIZE, kern_rdup_pg_size)
+        )
+
+        if args.aon is not None:
+            print("      AON binary size:   ", args.aon_size)
+            aon_rdup_pg_size = roundup_page(args.aon_size)
+            # Add manifest for aontask binary
+            f.write(
+                gen_manifest(
+                    b"ISHM",
+                    b"AON_TASK",
+                    (
+                        HEADER_SIZE
+                        + kern_rdup_pg_size * PAGE_SIZE
+                        - MANIFEST_ENTRY_SIZE
+                    ),
+                    aon_rdup_pg_size,
+                )
+            )
+
+        # Add manifest that signals end of manifests
+        f.write(gen_manifest(b"ISHE", b"", 0, 0))
+
+        # Pad the remaining HEADER with 0s
+        if args.aon is not None:
+            f.write(b"\x00" * (HEADER_SIZE - (MANIFEST_ENTRY_SIZE * 3)))
+        else:
+            f.write(b"\x00" * (HEADER_SIZE - (MANIFEST_ENTRY_SIZE * 2)))
+
+        # Append original kernel image
+        with open(args.kernel, "rb") as in_file:
+            f.write(in_file.read())
+        # Filling padings due to size round up as pages
+        f.write(b"\x00" * (kern_rdup_pg_size * PAGE_SIZE - args.kernel_size))
+
+        if args.aon is not None:
+            # Append original aon image
+            with open(args.aon, "rb") as in_file:
+                f.write(in_file.read())
+            # Filling padings due to size round up as pages
+            f.write(b"\x00" * (aon_rdup_pg_size * PAGE_SIZE - args.aon_size))
+
+
+if __name__ == "__main__":
+    main()
diff --git a/chip/ish/watchdog.c b/chip/ish/watchdog.c
index bf78f49312..7b32133619 100644
--- a/chip/ish/watchdog.c
+++ b/chip/ish/watchdog.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -29,8 +29,8 @@
 #include "watchdog.h"
 
 /* Units are hundreds of milliseconds */
-#define WDT_T1_PERIOD		(100) /* 10 seconds */
-#define WDT_T2_PERIOD		(10)  /* 1 second */
+#define WDT_T1_PERIOD (100) /* 10 seconds */
+#define WDT_T2_PERIOD (10) /* 1 second */
 
 int watchdog_init(void)
 {
@@ -45,9 +45,8 @@ int watchdog_init(void)
 	CCU_WDT_CD = WDT_CLOCK_HZ / 10; /* 10 Hz => 100 ms period */
 
 	/* Enable the watchdog timer and set initial T1/T2 values */
-	WDT_CONTROL = WDT_CONTROL_ENABLE_BIT
-		| (WDT_T2_PERIOD << 8)
-		| WDT_T1_PERIOD;
+	WDT_CONTROL = WDT_CONTROL_ENABLE_BIT | (WDT_T2_PERIOD << 8) |
+		      WDT_T1_PERIOD;
 
 	task_enable_irq(ISH_WDT_IRQ);
 
diff --git a/chip/it83xx/adc.c b/chip/it83xx/adc.c
index 2839da5af2..9f9fa27f41 100644
--- a/chip/it83xx/adc.c
+++ b/chip/it83xx/adc.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,7 +17,7 @@
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 /* Global variables */
 static struct mutex adc_lock;
@@ -26,42 +26,42 @@ static volatile task_id_t task_waiting;
 
 /* Data structure of ADC channel control registers. */
 const struct adc_ctrl_t adc_ctrl_regs[] = {
-	{&IT83XX_ADC_VCH0CTL, &IT83XX_ADC_VCH0DATM, &IT83XX_ADC_VCH0DATL},
-	{&IT83XX_ADC_VCH1CTL, &IT83XX_ADC_VCH1DATM, &IT83XX_ADC_VCH1DATL},
-	{&IT83XX_ADC_VCH2CTL, &IT83XX_ADC_VCH2DATM, &IT83XX_ADC_VCH2DATL},
-	{&IT83XX_ADC_VCH3CTL, &IT83XX_ADC_VCH3DATM, &IT83XX_ADC_VCH3DATL},
-	{&IT83XX_ADC_VCH4CTL, &IT83XX_ADC_VCH4DATM, &IT83XX_ADC_VCH4DATL},
-	{&IT83XX_ADC_VCH5CTL, &IT83XX_ADC_VCH5DATM, &IT83XX_ADC_VCH5DATL},
-	{&IT83XX_ADC_VCH6CTL, &IT83XX_ADC_VCH6DATM, &IT83XX_ADC_VCH6DATL},
-	{&IT83XX_ADC_VCH7CTL, &IT83XX_ADC_VCH7DATM, &IT83XX_ADC_VCH7DATL},
-	{&IT83XX_ADC_VCH13CTL, &IT83XX_ADC_VCH13DATM, &IT83XX_ADC_VCH13DATL},
-	{&IT83XX_ADC_VCH14CTL, &IT83XX_ADC_VCH14DATM, &IT83XX_ADC_VCH14DATL},
-	{&IT83XX_ADC_VCH15CTL, &IT83XX_ADC_VCH15DATM, &IT83XX_ADC_VCH15DATL},
-	{&IT83XX_ADC_VCH16CTL, &IT83XX_ADC_VCH16DATM, &IT83XX_ADC_VCH16DATL},
+	{ &IT83XX_ADC_VCH0CTL, &IT83XX_ADC_VCH0DATM, &IT83XX_ADC_VCH0DATL },
+	{ &IT83XX_ADC_VCH1CTL, &IT83XX_ADC_VCH1DATM, &IT83XX_ADC_VCH1DATL },
+	{ &IT83XX_ADC_VCH2CTL, &IT83XX_ADC_VCH2DATM, &IT83XX_ADC_VCH2DATL },
+	{ &IT83XX_ADC_VCH3CTL, &IT83XX_ADC_VCH3DATM, &IT83XX_ADC_VCH3DATL },
+	{ &IT83XX_ADC_VCH4CTL, &IT83XX_ADC_VCH4DATM, &IT83XX_ADC_VCH4DATL },
+	{ &IT83XX_ADC_VCH5CTL, &IT83XX_ADC_VCH5DATM, &IT83XX_ADC_VCH5DATL },
+	{ &IT83XX_ADC_VCH6CTL, &IT83XX_ADC_VCH6DATM, &IT83XX_ADC_VCH6DATL },
+	{ &IT83XX_ADC_VCH7CTL, &IT83XX_ADC_VCH7DATM, &IT83XX_ADC_VCH7DATL },
+	{ &IT83XX_ADC_VCH13CTL, &IT83XX_ADC_VCH13DATM, &IT83XX_ADC_VCH13DATL },
+	{ &IT83XX_ADC_VCH14CTL, &IT83XX_ADC_VCH14DATM, &IT83XX_ADC_VCH14DATL },
+	{ &IT83XX_ADC_VCH15CTL, &IT83XX_ADC_VCH15DATM, &IT83XX_ADC_VCH15DATL },
+	{ &IT83XX_ADC_VCH16CTL, &IT83XX_ADC_VCH16DATM, &IT83XX_ADC_VCH16DATL },
 };
 BUILD_ASSERT(ARRAY_SIZE(adc_ctrl_regs) == CHIP_ADC_COUNT);
 
 #ifdef CONFIG_ADC_VOLTAGE_COMPARATOR
-#define VCMP_ADC_CH_MASK_H           BIT(3)
-#define VCMP_ADC_CH_MASK_L           0x7
+#define VCMP_ADC_CH_MASK_H BIT(3)
+#define VCMP_ADC_CH_MASK_L 0x7
 /* 10-bits resolution */
-#define VCMP_RESOLUTION              BIT(10)
-#define VCMP_MAX_MVOLT               3000
+#define VCMP_RESOLUTION BIT(10)
+#define VCMP_MAX_MVOLT 3000
 
 /* Data structure of voltage comparator control registers. */
 const struct vcmp_ctrl_t vcmp_ctrl_regs[] = {
-	{&IT83XX_ADC_VCMP0CTL, &IT83XX_ADC_VCMP0CSELM, &IT83XX_ADC_CMP0THRDATM,
-		&IT83XX_ADC_CMP0THRDATL},
-	{&IT83XX_ADC_VCMP1CTL, &IT83XX_ADC_VCMP1CSELM, &IT83XX_ADC_CMP1THRDATM,
-		&IT83XX_ADC_CMP1THRDATL},
-	{&IT83XX_ADC_VCMP2CTL, &IT83XX_ADC_VCMP2CSELM, &IT83XX_ADC_CMP2THRDATM,
-		&IT83XX_ADC_CMP2THRDATL},
-	{&IT83XX_ADC_VCMP3CTL, &IT83XX_ADC_VCMP3CSELM, &IT83XX_ADC_CMP3THRDATM,
-		&IT83XX_ADC_CMP3THRDATL},
-	{&IT83XX_ADC_VCMP4CTL, &IT83XX_ADC_VCMP4CSELM, &IT83XX_ADC_CMP4THRDATM,
-		&IT83XX_ADC_CMP4THRDATL},
-	{&IT83XX_ADC_VCMP5CTL, &IT83XX_ADC_VCMP5CSELM, &IT83XX_ADC_CMP5THRDATM,
-		&IT83XX_ADC_CMP5THRDATL},
+	{ &IT83XX_ADC_VCMP0CTL, &IT83XX_ADC_VCMP0CSELM, &IT83XX_ADC_CMP0THRDATM,
+	  &IT83XX_ADC_CMP0THRDATL },
+	{ &IT83XX_ADC_VCMP1CTL, &IT83XX_ADC_VCMP1CSELM, &IT83XX_ADC_CMP1THRDATM,
+	  &IT83XX_ADC_CMP1THRDATL },
+	{ &IT83XX_ADC_VCMP2CTL, &IT83XX_ADC_VCMP2CSELM, &IT83XX_ADC_CMP2THRDATM,
+	  &IT83XX_ADC_CMP2THRDATL },
+	{ &IT83XX_ADC_VCMP3CTL, &IT83XX_ADC_VCMP3CSELM, &IT83XX_ADC_CMP3THRDATM,
+	  &IT83XX_ADC_CMP3THRDATL },
+	{ &IT83XX_ADC_VCMP4CTL, &IT83XX_ADC_VCMP4CSELM, &IT83XX_ADC_CMP4THRDATM,
+	  &IT83XX_ADC_CMP4THRDATL },
+	{ &IT83XX_ADC_VCMP5CTL, &IT83XX_ADC_VCMP5CSELM, &IT83XX_ADC_CMP5THRDATM,
+	  &IT83XX_ADC_CMP5THRDATL },
 };
 BUILD_ASSERT(ARRAY_SIZE(vcmp_ctrl_regs) == CHIP_VCMP_COUNT);
 #endif
@@ -120,8 +120,8 @@ static void adc_disable_channel(int ch)
 static int adc_data_valid(enum chip_adc_channel adc_ch)
 {
 	return (adc_ch <= CHIP_ADC_CH7) ?
-		(IT83XX_ADC_ADCDVSTS & BIT(adc_ch)) :
-		(IT83XX_ADC_ADCDVSTS2 & (1 << (adc_ch - CHIP_ADC_CH13)));
+		       (IT83XX_ADC_ADCDVSTS & BIT(adc_ch)) :
+		       (IT83XX_ADC_ADCDVSTS2 & (1 << (adc_ch - CHIP_ADC_CH13)));
 }
 
 int adc_read_channel(enum adc_channel ch)
@@ -153,13 +153,13 @@ int adc_read_channel(enum adc_channel ch)
 	 * next read.
 	 */
 	atomic_clear_bits(task_get_event_bitmap(task_get_current()),
-		TASK_EVENT_ADC_DONE);
+			  TASK_EVENT_ADC_DONE);
 
 	/* data valid of adc channel[x] */
 	if (adc_data_valid(adc_ch)) {
 		/* read adc raw data msb and lsb */
 		adc_raw_data = (*adc_ctrl_regs[adc_ch].adc_datm << 8) +
-			*adc_ctrl_regs[adc_ch].adc_datl;
+			       *adc_ctrl_regs[adc_ch].adc_datl;
 
 		/* W/C data valid flag */
 		if (adc_ch <= CHIP_ADC_CH7)
@@ -168,15 +168,15 @@ int adc_read_channel(enum adc_channel ch)
 			IT83XX_ADC_ADCDVSTS2 = (1 << (adc_ch - CHIP_ADC_CH13));
 
 		mv = adc_raw_data * adc_channels[ch].factor_mul /
-			adc_channels[ch].factor_div + adc_channels[ch].shift;
+			     adc_channels[ch].factor_div +
+		     adc_channels[ch].shift;
 		valid = 1;
 	}
 
 	if (!valid) {
 		CPRINTS("ADC failed to read!!! (regs=%x, %x, ch=%d, evt=%x)",
-			IT83XX_ADC_ADCDVSTS,
-			IT83XX_ADC_ADCDVSTS2,
-			adc_ch, events);
+			IT83XX_ADC_ADCDVSTS, IT83XX_ADC_ADCDVSTS2, adc_ch,
+			events);
 	}
 
 	adc_disable_channel(adc_ch);
@@ -292,8 +292,8 @@ static void voltage_comparator_init(void)
 		 */
 
 		/* Select which ADC channel output voltage into comparator */
-		*vcmp_ctrl_regs[idx].vcmp_ctrl |=
-			vcmp_list[idx].adc_ch & VCMP_ADC_CH_MASK_L;
+		*vcmp_ctrl_regs[idx].vcmp_ctrl |= vcmp_list[idx].adc_ch &
+						  VCMP_ADC_CH_MASK_L;
 		if (vcmp_list[idx].adc_ch & VCMP_ADC_CH_MASK_H)
 			*vcmp_ctrl_regs[idx].vcmp_adc_chm |= ADC_VCMP_VCMPCSELM;
 
diff --git a/chip/it83xx/adc_chip.h b/chip/it83xx/adc_chip.h
index 15a8e68e94..99e84624e0 100644
--- a/chip/it83xx/adc_chip.h
+++ b/chip/it83xx/adc_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -61,13 +61,13 @@ enum vcmp_scan_period {
 	VCMP_SCAN_PERIOD_400US = 0x30,
 	VCMP_SCAN_PERIOD_600US = 0x40,
 	VCMP_SCAN_PERIOD_800US = 0x50,
-	VCMP_SCAN_PERIOD_1MS   = 0x60,
+	VCMP_SCAN_PERIOD_1MS = 0x60,
 	VCMP_SCAN_PERIOD_1_5MS = 0x70,
-	VCMP_SCAN_PERIOD_2MS   = 0x80,
+	VCMP_SCAN_PERIOD_2MS = 0x80,
 	VCMP_SCAN_PERIOD_2_5MS = 0x90,
-	VCMP_SCAN_PERIOD_3MS   = 0xA0,
-	VCMP_SCAN_PERIOD_4MS   = 0xB0,
-	VCMP_SCAN_PERIOD_5MS   = 0xC0,
+	VCMP_SCAN_PERIOD_3MS = 0xA0,
+	VCMP_SCAN_PERIOD_4MS = 0xB0,
+	VCMP_SCAN_PERIOD_5MS = 0xC0,
 };
 
 /* Data structure to define ADC channel control registers. */
@@ -95,8 +95,8 @@ struct vcmp_ctrl_t {
 };
 
 /* supported flags (member "flag" in struct vcmp_t) for voltage comparator */
-#define GREATER_THRESHOLD         BIT(0)
-#define LESS_EQUAL_THRESHOLD      BIT(1)
+#define GREATER_THRESHOLD BIT(0)
+#define LESS_EQUAL_THRESHOLD BIT(1)
 
 /* Data structure for board to define voltage comparator list. */
 struct vcmp_t {
diff --git a/chip/it83xx/build.mk b/chip/it83xx/build.mk
index 888bc92121..afa9b193f5 100644
--- a/chip/it83xx/build.mk
+++ b/chip/it83xx/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
+# Copyright 2013 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/chip/it83xx/clock.c b/chip/it83xx/clock.c
index f548867d12..ab1da3b68a 100644
--- a/chip/it83xx/clock.c
+++ b/chip/it83xx/clock.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,11 +24,11 @@
 
 /* Console output macros. */
 #define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args)
 
 #ifdef CONFIG_LOW_POWER_IDLE
 #define SLEEP_SET_HTIMER_DELAY_USEC 250
-#define SLEEP_FTIMER_SKIP_USEC      (HOOK_TICK_INTERVAL * 2)
+#define SLEEP_FTIMER_SKIP_USEC (HOOK_TICK_INTERVAL * 2)
 
 static timestamp_t sleep_mode_t0;
 static timestamp_t sleep_mode_t1;
@@ -40,13 +40,13 @@ static uint32_t ec_sleep;
  * Fixed amount of time to keep the console in use flag true after boot in
  * order to give a permanent window in which the heavy sleep mode is not used.
  */
-#define CONSOLE_IN_USE_ON_BOOT_TIME (15*SECOND)
+#define CONSOLE_IN_USE_ON_BOOT_TIME (15 * SECOND)
 static int console_in_use_timeout_sec = 5;
 static timestamp_t console_expire_time;
 
 /* clock source is 32.768KHz */
-#define TIMER_32P768K_CNT_TO_US(cnt) ((uint64_t)(cnt) * 1000000 / 32768)
-#define TIMER_CNT_8M_32P768K(cnt)    (((cnt) / (8000000 / 32768)) + 1)
+#define TIMER_32P768K_CNT_TO_US(cnt) ((uint64_t)(cnt)*1000000 / 32768)
+#define TIMER_CNT_8M_32P768K(cnt) (((cnt) / (8000000 / 32768)) + 1)
 #endif /*CONFIG_LOW_POWER_IDLE */
 
 static int freq;
@@ -66,10 +66,11 @@ static void clock_module_disable(void)
 	IT83XX_GCTRL_MCCR &= ~BIT(7);
 	clock_disable_peripheral((CGC_OFFSET_EGPC | CGC_OFFSET_CIR), 0, 0);
 	clock_disable_peripheral((CGC_OFFSET_SMBA | CGC_OFFSET_SMBB |
-		CGC_OFFSET_SMBC | CGC_OFFSET_SMBD | CGC_OFFSET_SMBE |
-		CGC_OFFSET_SMBF), 0, 0);
-	clock_disable_peripheral((CGC_OFFSET_SSPI | CGC_OFFSET_PECI |
-		CGC_OFFSET_USB), 0, 0);
+				  CGC_OFFSET_SMBC | CGC_OFFSET_SMBD |
+				  CGC_OFFSET_SMBE | CGC_OFFSET_SMBF),
+				 0, 0);
+	clock_disable_peripheral(
+		(CGC_OFFSET_SSPI | CGC_OFFSET_PECI | CGC_OFFSET_USB), 0, 0);
 }
 
 enum pll_freq_idx {
@@ -78,19 +79,11 @@ enum pll_freq_idx {
 	PLL_96_MHZ = 4,
 };
 
-static const uint8_t pll_to_idx[8] = {
-	0,
-	0,
-	PLL_24_MHZ,
-	0,
-	PLL_48_MHZ,
-	0,
-	0,
-	PLL_96_MHZ
-};
+static const uint8_t pll_to_idx[8] = { 0,	   0, PLL_24_MHZ, 0,
+				       PLL_48_MHZ, 0, 0,	  PLL_96_MHZ };
 
 struct clock_pll_t {
-	int     pll_freq;
+	int pll_freq;
 	uint8_t pll_setting;
 	uint8_t div_fnd;
 	uint8_t div_uart;
@@ -114,17 +107,17 @@ const struct clock_pll_t clock_pll_ctrl[] = {
 	 * SSPI:  48MHz(24MHz if PLL=24MHz)
 	 */
 	/* PLL:24MHz, MCU:24MHz, Fnd(e-flash):24MHz */
-	[PLL_24_MHZ] = {24000000, 2, 0, 0, 0, 0, 0, 2, 0, 0, 0x2},
+	[PLL_24_MHZ] = { 24000000, 2, 0, 0, 0, 0, 0, 2, 0, 0, 0x2 },
 #ifdef CONFIG_IT83XX_FLASH_CLOCK_48MHZ
 	/* PLL:48MHz, MCU:48MHz, Fnd:48MHz */
-	[PLL_48_MHZ] = {48000000, 4, 0, 1, 0, 1, 0, 6, 1, 0, 0x5},
+	[PLL_48_MHZ] = { 48000000, 4, 0, 1, 0, 1, 0, 6, 1, 0, 0x5 },
 	/* PLL:96MHz, MCU:96MHz, Fnd:48MHz */
-	[PLL_96_MHZ] = {96000000, 7, 1, 3, 1, 3, 1, 6, 3, 1, 0xb},
+	[PLL_96_MHZ] = { 96000000, 7, 1, 3, 1, 3, 1, 6, 3, 1, 0xb },
 #else
 	/* PLL:48MHz, MCU:48MHz, Fnd:24MHz */
-	[PLL_48_MHZ] = {48000000, 4, 1, 1, 0, 1, 0, 2, 1, 0, 0x5},
+	[PLL_48_MHZ] = { 48000000, 4, 1, 1, 0, 1, 0, 2, 1, 0, 0x5 },
 	/* PLL:96MHz, MCU:96MHz, Fnd:32MHz */
-	[PLL_96_MHZ] = {96000000, 7, 2, 3, 1, 3, 1, 4, 3, 1, 0xb},
+	[PLL_96_MHZ] = { 96000000, 7, 2, 3, 1, 3, 1, 4, 3, 1, 0xb },
 #endif
 };
 
@@ -196,18 +189,18 @@ void __ram_code clock_pll_changed(void)
 	clock_ec_pll_ctrl(EC_PLL_SLEEP);
 	if (IS_ENABLED(CHIP_CORE_NDS32)) {
 		/* Global interrupt enable */
-		asm volatile ("setgie.e");
+		asm volatile("setgie.e");
 		/* EC sleep */
 		asm("standby wake_grant");
 		/* Global interrupt disable */
-		asm volatile ("setgie.d");
+		asm volatile("setgie.d");
 	} else if (IS_ENABLED(CHIP_CORE_RISCV)) {
 		/* Global interrupt enable */
-		asm volatile ("csrsi mstatus, 0x8");
+		asm volatile("csrsi mstatus, 0x8");
 		/* EC sleep */
 		asm("wfi");
 		/* Global interrupt disable */
-		asm volatile ("csrci mstatus, 0x8");
+		asm volatile("csrci mstatus, 0x8");
 	}
 	/* New FND clock frequency */
 	IT83XX_ECPM_SCDCR0 = (pll_div_fnd << 4);
@@ -220,18 +213,18 @@ static void clock_set_pll(enum pll_freq_idx idx)
 {
 	int pll;
 
-	pll_div_fnd  = clock_pll_ctrl[idx].div_fnd;
-	pll_div_ec   = clock_pll_ctrl[idx].div_ec;
+	pll_div_fnd = clock_pll_ctrl[idx].div_fnd;
+	pll_div_ec = clock_pll_ctrl[idx].div_ec;
 	pll_div_jtag = clock_pll_ctrl[idx].div_jtag;
-	pll_setting  = clock_pll_ctrl[idx].pll_setting;
+	pll_setting = clock_pll_ctrl[idx].pll_setting;
 
 	/* Update PLL settings or not */
 	if (((IT83XX_ECPM_PLLFREQR & 0xf) != pll_setting) ||
-		((IT83XX_ECPM_SCDCR0 & 0xf0) != (pll_div_fnd << 4)) ||
-		((IT83XX_ECPM_SCDCR3 & 0xf) != pll_div_ec)) {
+	    ((IT83XX_ECPM_SCDCR0 & 0xf0) != (pll_div_fnd << 4)) ||
+	    ((IT83XX_ECPM_SCDCR3 & 0xf) != pll_div_ec)) {
 		/* Enable hw timer to wakeup EC from the sleep mode */
-		ext_timer_ms(LOW_POWER_EXT_TIMER, EXT_PSR_32P768K_HZ,
-				1, 1, 5, 1, 0);
+		ext_timer_ms(LOW_POWER_EXT_TIMER, EXT_PSR_32P768K_HZ, 1, 1, 5,
+			     1, 0);
 		task_clear_pending_irq(et_ctrl_regs[LOW_POWER_EXT_TIMER].irq);
 #ifdef CONFIG_HOST_INTERFACE_ESPI
 		/*
@@ -264,13 +257,13 @@ static void clock_set_pll(enum pll_freq_idx idx)
 	pll = pll_to_idx[IT83XX_ECPM_PLLFREQR & 0xf];
 	/* USB and UART */
 	IT83XX_ECPM_SCDCR1 = (clock_pll_ctrl[pll].div_usb << 4) |
-				clock_pll_ctrl[pll].div_uart;
+			     clock_pll_ctrl[pll].div_uart;
 	/* SSPI and SMB */
 	IT83XX_ECPM_SCDCR2 = (clock_pll_ctrl[pll].div_sspi << 4) |
-				clock_pll_ctrl[pll].div_smb;
+			     clock_pll_ctrl[pll].div_smb;
 	/* USBPD and PWM */
 	IT83XX_ECPM_SCDCR4 = (clock_pll_ctrl[pll].div_usbpd << 4) |
-				clock_pll_ctrl[pll].div_pwm;
+			     clock_pll_ctrl[pll].div_pwm;
 	/* Current PLL frequency  */
 	freq = clock_pll_ctrl[pll].pll_freq;
 }
@@ -284,8 +277,7 @@ void clock_init(void)
 		/* Interrupt Vector Table Base Address, in 64k Byte unit */
 		IT83XX_GCTRL_IVTBAR = (CONFIG_RW_MEM_OFF >> 16) & 0xFF;
 
-#if (PLL_CLOCK == 24000000)     || \
-	(PLL_CLOCK == 48000000) || \
+#if (PLL_CLOCK == 24000000) || (PLL_CLOCK == 48000000) || \
 	(PLL_CLOCK == 96000000)
 	/* Set PLL frequency */
 	clock_set_pll(PLL_CLOCK / 24000000);
@@ -345,8 +337,8 @@ int clock_get_freq(void)
  */
 void clock_enable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode)
 {
-	volatile uint8_t *reg = (volatile uint8_t *)
-			(IT83XX_ECPM_BASE + (offset >> 8));
+	volatile uint8_t *reg =
+		(volatile uint8_t *)(IT83XX_ECPM_BASE + (offset >> 8));
 	uint8_t reg_mask = offset & 0xff;
 
 	/*
@@ -368,8 +360,8 @@ void clock_enable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode)
  */
 void clock_disable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode)
 {
-	volatile uint8_t *reg = (volatile uint8_t *)
-			(IT83XX_ECPM_BASE + (offset >> 8));
+	volatile uint8_t *reg =
+		(volatile uint8_t *)(IT83XX_ECPM_BASE + (offset >> 8));
 	uint8_t reg_mask = offset & 0xff;
 	uint8_t tmp_mask = 0;
 
@@ -388,7 +380,7 @@ void clock_refresh_console_in_use(void)
 }
 
 static void clock_event_timer_clock_change(enum ext_timer_clock_source clock,
-					uint32_t count)
+					   uint32_t count)
 {
 	IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) &= ~BIT(0);
 	IT83XX_ETWD_ETXPSR(EVENT_EXT_TIMER) = clock;
@@ -420,19 +412,19 @@ static int clock_allow_low_power_idle(void)
 
 	/* If timer interrupt status is set, don't go to sleep mode. */
 	if (*et_ctrl_regs[EVENT_EXT_TIMER].isr &
-		et_ctrl_regs[EVENT_EXT_TIMER].mask)
+	    et_ctrl_regs[EVENT_EXT_TIMER].mask)
 		return 0;
 
-	/*
-	 * If timer is less than 250us to expire, then we don't go to sleep
-	 * mode.
-	 */
+		/*
+		 * If timer is less than 250us to expire, then we don't go to
+		 * sleep mode.
+		 */
 #ifdef IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES
 	if (EVENT_TIMER_COUNT_TO_US(ext_observation_reg_read(EVENT_EXT_TIMER)) <
 #else
 	if (EVENT_TIMER_COUNT_TO_US(IT83XX_ETWD_ETXCNTOR(EVENT_EXT_TIMER)) <
 #endif
-		SLEEP_SET_HTIMER_DELAY_USEC)
+	    SLEEP_SET_HTIMER_DELAY_USEC)
 		return 0;
 
 	/*
@@ -442,7 +434,7 @@ static int clock_allow_low_power_idle(void)
 	 */
 	sleep_mode_t0 = get_time();
 	if ((sleep_mode_t0.le.lo > (0xffffffff - SLEEP_FTIMER_SKIP_USEC)) ||
-		(sleep_mode_t0.le.lo < SLEEP_FTIMER_SKIP_USEC))
+	    (sleep_mode_t0.le.lo < SLEEP_FTIMER_SKIP_USEC))
 		return 0;
 
 	/* If we are waked up by console, then keep awake at least 5s. */
@@ -541,7 +533,7 @@ void __enter_hibernate(uint32_t seconds, uint32_t microseconds)
 	/* EC sleep */
 	ec_sleep = 1;
 #if defined(IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED) && \
-defined(CONFIG_HOST_INTERFACE_ESPI)
+	defined(CONFIG_HOST_INTERFACE_ESPI)
 	/* Disable eSPI pad. */
 	espi_enable_pad(0);
 #endif
@@ -567,7 +559,7 @@ void clock_sleep_mode_wakeup_isr(void)
 	/* trigger a reboot if wake up EC from sleep mode (system hibernate) */
 	if (clock_ec_wake_from_sleep()) {
 #if defined(IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED) && \
-defined(CONFIG_HOST_INTERFACE_ESPI)
+	defined(CONFIG_HOST_INTERFACE_ESPI)
 		/*
 		 * Enable eSPI pad.
 		 * We will not need to enable eSPI pad here if Dx is able to
@@ -587,7 +579,7 @@ defined(CONFIG_HOST_INTERFACE_ESPI)
 		clock_ec_pll_ctrl(EC_PLL_DOZE);
 		/* update free running timer */
 		c = LOW_POWER_TIMER_MASK -
-			IT83XX_ETWD_ETXCNTOR(LOW_POWER_EXT_TIMER);
+		    IT83XX_ETWD_ETXCNTOR(LOW_POWER_EXT_TIMER);
 		st_us = TIMER_32P768K_CNT_TO_US(c);
 		sleep_mode_t1.val = sleep_mode_t0.val + st_us;
 		__hw_clock_source_set(sleep_mode_t1.le.lo);
@@ -613,8 +605,8 @@ void __keep __idle_init(void)
 {
 	console_expire_time.val = get_time().val + CONSOLE_IN_USE_ON_BOOT_TIME;
 	/* init hw timer and clock source is 32.768 KHz */
-	ext_timer_ms(LOW_POWER_EXT_TIMER, EXT_PSR_32P768K_HZ, 1, 0,
-		0xffffffff, 1, 1);
+	ext_timer_ms(LOW_POWER_EXT_TIMER, EXT_PSR_32P768K_HZ, 1, 0, 0xffffffff,
+		     1, 1);
 
 	/*
 	 * Print when the idle task starts.  This is the lowest priority task,
@@ -689,7 +681,7 @@ void __ram_code __idle(void)
 /**
  * Print low power idle statistics
  */
-static int command_idle_stats(int argc, char **argv)
+static int command_idle_stats(int argc, const char **argv)
 {
 	timestamp_t ts = get_time();
 
@@ -697,12 +689,11 @@ static int command_idle_stats(int argc, char **argv)
 	ccprintf("Num idle calls that sleep:           %d\n", idle_sleep_cnt);
 
 	ccprintf("Total Time spent in sleep(sec):      %.6lld(s)\n",
-						total_idle_sleep_time_us);
+		 total_idle_sleep_time_us);
 	ccprintf("Total time on:                       %.6llds\n\n", ts.val);
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats,
-			"",
+DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, "",
 			"Print last idle stats");
 
 #endif /* CONFIG_CMD_IDLE_STATS */
diff --git a/chip/it83xx/config_chip.h b/chip/it83xx/config_chip.h
index 2f552c794a..537069972f 100644
--- a/chip/it83xx/config_chip.h
+++ b/chip/it83xx/config_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,7 @@
 #ifndef __CROS_EC_CONFIG_CHIP_H
 #define __CROS_EC_CONFIG_CHIP_H
 
-#if defined(CHIP_FAMILY_IT8320)    /* N8 core */
+#if defined(CHIP_FAMILY_IT8320) /* N8 core */
 #include "config_chip_it8320.h"
 #elif defined(CHIP_FAMILY_IT8XXX2) /* RISCV core */
 #include "config_chip_it8xxx2.h"
@@ -19,7 +19,7 @@
 
 /* Interval between HOOK_TICK notifications */
 #define HOOK_TICK_INTERVAL_MS 500
-#define HOOK_TICK_INTERVAL    (HOOK_TICK_INTERVAL_MS * MSEC)
+#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC)
 
 /* Default PLL frequency. */
 #define PLL_CLOCK 48000000
@@ -35,34 +35,34 @@
 #define I2C_ENHANCED_PORT_COUNT 3
 
 /* System stack size */
-#define CONFIG_STACK_SIZE           1024
+#define CONFIG_STACK_SIZE 1024
 
 /* non-standard task stack sizes */
-#define SMALLER_TASK_STACK_SIZE     (384 + CHIP_EXTRA_STACK_SPACE)
-#define IDLE_TASK_STACK_SIZE        (512 + CHIP_EXTRA_STACK_SPACE)
-#define LARGER_TASK_STACK_SIZE      (768 + CHIP_EXTRA_STACK_SPACE)
-#define VENTI_TASK_STACK_SIZE       (896 + CHIP_EXTRA_STACK_SPACE)
-#define ULTRA_TASK_STACK_SIZE       (1056 + CHIP_EXTRA_STACK_SPACE)
-#define TRENTA_TASK_STACK_SIZE      (1184 + CHIP_EXTRA_STACK_SPACE)
+#define SMALLER_TASK_STACK_SIZE (384 + CHIP_EXTRA_STACK_SPACE)
+#define IDLE_TASK_STACK_SIZE (512 + CHIP_EXTRA_STACK_SPACE)
+#define LARGER_TASK_STACK_SIZE (768 + CHIP_EXTRA_STACK_SPACE)
+#define VENTI_TASK_STACK_SIZE (896 + CHIP_EXTRA_STACK_SPACE)
+#define ULTRA_TASK_STACK_SIZE (1056 + CHIP_EXTRA_STACK_SPACE)
+#define TRENTA_TASK_STACK_SIZE (1184 + CHIP_EXTRA_STACK_SPACE)
 
 /* Default task stack size */
-#define TASK_STACK_SIZE             (512 + CHIP_EXTRA_STACK_SPACE)
+#define TASK_STACK_SIZE (512 + CHIP_EXTRA_STACK_SPACE)
 
 #ifdef IT83XX_CHIP_FLASH_IS_KGD
-#define CONFIG_FLASH_BANK_SIZE      0x00001000  /* protect bank size */
-#define CONFIG_FLASH_ERASE_SIZE     0x00001000  /* erase bank size */
+#define CONFIG_FLASH_BANK_SIZE 0x00001000 /* protect bank size */
+#define CONFIG_FLASH_ERASE_SIZE 0x00001000 /* erase bank size */
 #else
-#define CONFIG_FLASH_BANK_SIZE      0x00000800  /* protect bank size */
-#define CONFIG_FLASH_ERASE_SIZE     0x00000400  /* erase bank size */
+#define CONFIG_FLASH_BANK_SIZE 0x00000800 /* protect bank size */
+#define CONFIG_FLASH_ERASE_SIZE 0x00000400 /* erase bank size */
 #endif
-#define CONFIG_FLASH_WRITE_SIZE     0x00000004  /* minimum write size */
+#define CONFIG_FLASH_WRITE_SIZE 0x00000004 /* minimum write size */
 
 /*
  * This is the block size of the ILM on the it83xx chip.
  * The ILM for static code cache, CPU fetch instruction from
  * ILM(ILM -> CPU)instead of flash(flash -> IMMU -> CPU) if enabled.
  */
-#define IT83XX_ILM_BLOCK_SIZE       0x00001000
+#define IT83XX_ILM_BLOCK_SIZE 0x00001000
 
 #ifdef IT83XX_CHIP_FLASH_IS_KGD
 /*
@@ -101,9 +101,9 @@
  * IT8xxx2 series support mapping LPC/eSPI I/O cycle 800h ~ 9FFh
  * to 0x80081800 ~ 0x800819FF of DLM1.
  */
-#define CONFIG_H2RAM_BASE               (CHIP_H2RAM_BASE)
-#define CONFIG_H2RAM_SIZE               0x00001000
-#define CONFIG_H2RAM_HOST_LPC_IO_BASE   0x800
+#define CONFIG_H2RAM_BASE (CHIP_H2RAM_BASE)
+#define CONFIG_H2RAM_SIZE 0x00001000
+#define CONFIG_H2RAM_HOST_LPC_IO_BASE 0x800
 
 /****************************************************************************/
 /* Customize the build */
@@ -123,4 +123,4 @@
 
 #define __RAM_CODE_SECTION_NAME ".ram_code"
 
-#endif  /* __CROS_EC_CONFIG_CHIP_H */
+#endif /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/chip/it83xx/config_chip_it8320.h b/chip/it83xx/config_chip_it8320.h
index 53f4a1cbd3..0e5c48c96a 100644
--- a/chip/it83xx/config_chip_it8320.h
+++ b/chip/it83xx/config_chip_it8320.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,19 +12,19 @@
 /* N8 core */
 #define CHIP_CORE_NDS32
 /* The base address of EC interrupt controller registers. */
-#define CHIP_EC_INTC_BASE           0x00F01100
+#define CHIP_EC_INTC_BASE 0x00F01100
 
 /****************************************************************************/
 /* Memory mapping */
 
-#define CHIP_H2RAM_BASE             0x0008D000 /* 0x0008D000~0x0008DFFF */
-#define CHIP_RAMCODE_BASE           0x0008E000 /* 0x0008E000~0x0008EFFF */
-#define CHIP_EXTRA_STACK_SPACE      0
+#define CHIP_H2RAM_BASE 0x0008D000 /* 0x0008D000~0x0008DFFF */
+#define CHIP_RAMCODE_BASE 0x0008E000 /* 0x0008E000~0x0008EFFF */
+#define CHIP_EXTRA_STACK_SPACE 0
 
-#define CONFIG_RAM_BASE             0x00080000
-#define CONFIG_RAM_SIZE             0x0000C000
+#define CONFIG_RAM_BASE 0x00080000
+#define CONFIG_RAM_SIZE 0x0000C000
 
-#define CONFIG_PROGRAM_MEMORY_BASE  0x00000000
+#define CONFIG_PROGRAM_MEMORY_BASE 0x00000000
 
 /****************************************************************************/
 /* Chip IT8320 is used with IT83XX TCPM driver */
@@ -36,7 +36,7 @@
  * doesn't support a write-protect pin, and if we make the write-protection
  * permanent, it can't be undone easily enough to support RMA.
  */
-#define CONFIG_FLASH_SIZE_BYTES  0x00040000
+#define CONFIG_FLASH_SIZE_BYTES 0x00040000
 /* For IT8320BX, we have to reload cc parameters after ec softreset. */
 #define IT83XX_USBPD_CC_PARAMETER_RELOAD
 /*
@@ -45,7 +45,7 @@
  */
 #define IT83XX_USBPD_CC_VOLTAGE_DETECTOR_INDEPENDENT
 /* Chip IT8320BX actually has TCPC physical port count */
-#define IT83XX_USBPD_PHY_PORT_COUNT    2
+#define IT83XX_USBPD_PHY_PORT_COUNT 2
 /* For IT8320BX, we have to write 0xff to clear pending bit.*/
 #define IT83XX_ESPI_VWCTRL1_WRITE_FF_CLEAR
 /* For IT8320BX, we have to read observation register of external timer two
@@ -53,7 +53,7 @@
  */
 #define IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES
 #elif defined(CHIP_VARIANT_IT8320DX)
-#define CONFIG_FLASH_SIZE_BYTES  0x00080000
+#define CONFIG_FLASH_SIZE_BYTES 0x00080000
 #define CONFIG_IT83XX_FLASH_CLOCK_48MHZ
 /*
  * Disable eSPI pad, then PLL change
@@ -96,9 +96,9 @@
 /* Chip Dx transmit status bit of PD register is different from Bx. */
 #define IT83XX_PD_TX_ERROR_STATUS_BIT5
 /* Chip IT8320DX actually has TCPC physical port count */
-#define IT83XX_USBPD_PHY_PORT_COUNT    2
+#define IT83XX_USBPD_PHY_PORT_COUNT 2
 #else
 #error "Unsupported chip variant!"
 #endif
 
-#endif  /* __CROS_EC_CONFIG_CHIP_IT8320_H */
+#endif /* __CROS_EC_CONFIG_CHIP_IT8320_H */
diff --git a/chip/it83xx/config_chip_it8xxx2.h b/chip/it83xx/config_chip_it8xxx2.h
index 0bbfe89b59..cbbbd0bd55 100644
--- a/chip/it83xx/config_chip_it8xxx2.h
+++ b/chip/it83xx/config_chip_it8xxx2.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,7 +15,7 @@
 #define CHIP_CORE_RISCV
 #define CHIP_ILM_DLM_ORDER
 /* The base address of EC interrupt controller registers. */
-#define CHIP_EC_INTC_BASE           0x00F03F00
+#define CHIP_EC_INTC_BASE 0x00F03F00
 #define CONFIG_IT83XX_FLASH_CLOCK_48MHZ
 /*
  * ILM/DLM size register.
@@ -27,11 +27,11 @@
 /****************************************************************************/
 /* Memory mapping */
 
-#define CHIP_ILM_BASE               0x80000000
-#define CHIP_EXTRA_STACK_SPACE      128
+#define CHIP_ILM_BASE 0x80000000
+#define CHIP_EXTRA_STACK_SPACE 128
 /* We reserve 12KB space for ramcode, h2ram, and immu sections. */
-#define CHIP_RAM_SPACE_RESERVED     0x3000
-#define CONFIG_PROGRAM_MEMORY_BASE  (CHIP_ILM_BASE)
+#define CHIP_RAM_SPACE_RESERVED 0x3000
+#define CONFIG_PROGRAM_MEMORY_BASE (CHIP_ILM_BASE)
 
 /****************************************************************************/
 /* Chip IT83202 is used with IT8XXX2 TCPM driver */
@@ -39,9 +39,9 @@
 
 #if defined(CHIP_VARIANT_IT83202BX)
 /* TODO(b/133460224): enable properly chip config option. */
-#define CONFIG_FLASH_SIZE_BYTES           0x00080000
-#define CONFIG_RAM_BASE             0x80080000
-#define CONFIG_RAM_SIZE             0x00010000
+#define CONFIG_FLASH_SIZE_BYTES 0x00080000
+#define CONFIG_RAM_BASE 0x80080000
+#define CONFIG_RAM_SIZE 0x00010000
 
 /* Embedded flash is KGD */
 #define IT83XX_CHIP_FLASH_IS_KGD
@@ -80,12 +80,12 @@
 /* Enable detect type-c plug in and out interrupt. */
 #define IT83XX_INTC_PLUG_IN_OUT_SUPPORT
 /* Chip IT83202BX actually has TCPC physical port count. */
-#define IT83XX_USBPD_PHY_PORT_COUNT    3
-#elif defined(CHIP_VARIANT_IT81302AX_1024) \
-|| defined(CHIP_VARIANT_IT81202AX_1024) \
-|| defined(CHIP_VARIANT_IT81302BX_1024) \
-|| defined(CHIP_VARIANT_IT81302BX_512) \
-|| defined(CHIP_VARIANT_IT81202BX_1024)
+#define IT83XX_USBPD_PHY_PORT_COUNT 3
+#elif defined(CHIP_VARIANT_IT81302AX_1024) ||   \
+	defined(CHIP_VARIANT_IT81202AX_1024) || \
+	defined(CHIP_VARIANT_IT81302BX_1024) || \
+	defined(CHIP_VARIANT_IT81302BX_512) ||  \
+	defined(CHIP_VARIANT_IT81202BX_1024)
 
 /*
  * Workaround mul instruction bug, see:
@@ -95,16 +95,16 @@
 #define CONFIG_IT8XXX2_MUL_WORKAROUND
 
 #if defined(CHIP_VARIANT_IT81302BX_512)
-#define CONFIG_FLASH_SIZE_BYTES     0x00080000
-#define CONFIG_RAM_BASE             0x80080000
+#define CONFIG_FLASH_SIZE_BYTES 0x00080000
+#define CONFIG_RAM_BASE 0x80080000
 #else
-#define CONFIG_FLASH_SIZE_BYTES     0x00100000
-#define CONFIG_RAM_BASE             0x80100000
+#define CONFIG_FLASH_SIZE_BYTES 0x00100000
+#define CONFIG_RAM_BASE 0x80100000
 /* Set ILM (instruction local memory) size up to 1M bytes */
 #define IT83XX_CHIP_FLASH_SIZE_1MB
 #endif
 
-#define CONFIG_RAM_SIZE             0x0000f000
+#define CONFIG_RAM_SIZE 0x0000f000
 
 /* Embedded flash is KGD */
 #define IT83XX_CHIP_FLASH_IS_KGD
@@ -151,14 +151,16 @@
 /* Individual setting CC1 and CC2 resistance. */
 #define IT83XX_USBPD_CC1_CC2_RESISTANCE_SEPARATE
 /* Chip actually has TCPC physical port count. */
-#define IT83XX_USBPD_PHY_PORT_COUNT    2
+#define IT83XX_USBPD_PHY_PORT_COUNT 2
 #else
 #error "Unsupported chip variant!"
 #endif
 
-#define CHIP_RAMCODE_ILM0 (CONFIG_RAM_BASE + 0)      /* base+0000h~base+0FFF */
-#define CHIP_H2RAM_BASE   (CONFIG_RAM_BASE + 0x1000) /* base+1000h~base+1FFF */
-#define CHIP_RAMCODE_BASE (CONFIG_RAM_BASE + 0x2000) /* base+2000h~base+2FFF */
+#define CHIP_RAMCODE_ILM0 (CONFIG_RAM_BASE + 0) /* base+0000h~base+0FFF */
+#define CHIP_H2RAM_BASE (CONFIG_RAM_BASE + 0x1000) /* base+1000h~base+1FFF */
+#define CHIP_RAMCODE_BASE                                  \
+	(CONFIG_RAM_BASE + 0x2000) /* base+2000h~base+2FFF \
+				    */
 
 #ifdef BASEBOARD_KUKUI
 /*
@@ -173,4 +175,4 @@
 #define CONFIG_FLASH_SIZE_BYTES CHIP_FLASH_PRESERVE_LOGS_BASE
 #endif
 
-#endif  /* __CROS_EC_CONFIG_CHIP_IT8XXX2_H */
+#endif /* __CROS_EC_CONFIG_CHIP_IT8XXX2_H */
diff --git a/chip/it83xx/dac.c b/chip/it83xx/dac.c
index 695d1cbc68..2e563f7557 100644
--- a/chip/it83xx/dac.c
+++ b/chip/it83xx/dac.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -44,7 +44,7 @@ static void dac_init(void)
 }
 DECLARE_HOOK(HOOK_INIT, dac_init, HOOK_PRIO_INIT_DAC);
 
-static int command_dac(int argc, char **argv)
+static int command_dac(int argc, const char **argv)
 {
 	char *e;
 	int ch, mv, rv;
@@ -85,6 +85,5 @@ static int command_dac(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(dac, command_dac,
-			"[ch2-5] [0-3300mV]",
+DECLARE_CONSOLE_COMMAND(dac, command_dac, "[ch2-5] [0-3300mV]",
 			"Enable or disable(0mV) DAC output voltage.");
diff --git a/chip/it83xx/dac_chip.h b/chip/it83xx/dac_chip.h
index 12e16eea0a..07e44e2e79 100644
--- a/chip/it83xx/dac_chip.h
+++ b/chip/it83xx/dac_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/it83xx/ec2i.c b/chip/it83xx/ec2i.c
index 5542d455a9..52f96b95d7 100644
--- a/chip/it83xx/ec2i.c
+++ b/chip/it83xx/ec2i.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,10 +16,10 @@
 
 static const struct ec2i_t keyboard_settings[] = {
 	/* Select logical device 06h(keyboard) */
-	{HOST_INDEX_LDN, LDN_KBC_KEYBOARD},
+	{ HOST_INDEX_LDN, LDN_KBC_KEYBOARD },
 	/* Set IRQ=01h for logical device */
-	{HOST_INDEX_IRQNUMX, 0x01},
-	/* Configure IRQTP for KBC. */
+	{ HOST_INDEX_IRQNUMX, 0x01 },
+/* Configure IRQTP for KBC. */
 #ifdef CONFIG_HOST_INTERFACE_ESPI
 	/*
 	 * Interrupt request type select (IRQTP) for KBC.
@@ -39,55 +39,55 @@ static const struct ec2i_t keyboard_settings[] = {
 	 * Additionally, this interrupt is configured as edge-triggered on the
 	 * host side. So, match the trigger mode on the EC side as well.
 	 */
-	{HOST_INDEX_IRQTP, 0x02},
+	{ HOST_INDEX_IRQTP, 0x02 },
 #endif
 	/* Enable logical device */
-	{HOST_INDEX_LDA, 0x01},
+	{ HOST_INDEX_LDA, 0x01 },
 };
 
 #ifdef CONFIG_IT83XX_ENABLE_MOUSE_DEVICE
 static const struct ec2i_t mouse_settings[] = {
 	/* Select logical device 05h(mouse) */
-	{HOST_INDEX_LDN, LDN_KBC_MOUSE},
+	{ HOST_INDEX_LDN, LDN_KBC_MOUSE },
 	/* Set IRQ=0Ch for logical device */
-	{HOST_INDEX_IRQNUMX, 0x0C},
+	{ HOST_INDEX_IRQNUMX, 0x0C },
 	/* Enable logical device */
-	{HOST_INDEX_LDA, 0x01},
+	{ HOST_INDEX_LDA, 0x01 },
 };
 #endif
 
 static const struct ec2i_t pm1_settings[] = {
 	/* Select logical device 11h(PM1 ACPI) */
-	{HOST_INDEX_LDN, LDN_PMC1},
+	{ HOST_INDEX_LDN, LDN_PMC1 },
 	/* Set IRQ=00h for logical device */
-	{HOST_INDEX_IRQNUMX, 0x00},
+	{ HOST_INDEX_IRQNUMX, 0x00 },
 	/* Enable logical device */
-	{HOST_INDEX_LDA, 0x01},
+	{ HOST_INDEX_LDA, 0x01 },
 };
 
 static const struct ec2i_t pm2_settings[] = {
 	/* Select logical device 12h(PM2) */
-	{HOST_INDEX_LDN, LDN_PMC2},
+	{ HOST_INDEX_LDN, LDN_PMC2 },
 	/* I/O Port Base Address 200h/204h */
-	{HOST_INDEX_IOBAD0_MSB, 0x02},
-	{HOST_INDEX_IOBAD0_LSB, 0x00},
-	{HOST_INDEX_IOBAD1_MSB, 0x02},
-	{HOST_INDEX_IOBAD1_LSB, 0x04},
+	{ HOST_INDEX_IOBAD0_MSB, 0x02 },
+	{ HOST_INDEX_IOBAD0_LSB, 0x00 },
+	{ HOST_INDEX_IOBAD1_MSB, 0x02 },
+	{ HOST_INDEX_IOBAD1_LSB, 0x04 },
 	/* Set IRQ=00h for logical device */
-	{HOST_INDEX_IRQNUMX, 0x00},
+	{ HOST_INDEX_IRQNUMX, 0x00 },
 	/* Enable logical device */
-	{HOST_INDEX_LDA, 0x01},
+	{ HOST_INDEX_LDA, 0x01 },
 };
 
 static const struct ec2i_t smfi_settings[] = {
 	/* Select logical device 0Fh(SMFI) */
-	{HOST_INDEX_LDN, LDN_SMFI},
+	{ HOST_INDEX_LDN, LDN_SMFI },
 	/* H2RAM LPC I/O cycle Dxxx */
-	{HOST_INDEX_DSLDC6, 0x00},
+	{ HOST_INDEX_DSLDC6, 0x00 },
 	/* Enable H2RAM LPC I/O cycle */
-	{HOST_INDEX_DSLDC7, 0x01},
+	{ HOST_INDEX_DSLDC7, 0x01 },
 	/* Enable logical device */
-	{HOST_INDEX_LDA, 0x01},
+	{ HOST_INDEX_LDA, 0x01 },
 };
 
 /*
@@ -96,16 +96,16 @@ static const struct ec2i_t smfi_settings[] = {
  */
 static const struct ec2i_t pm3_settings[] = {
 	/* Select logical device 17h(PM3) */
-	{HOST_INDEX_LDN, LDN_PMC3},
+	{ HOST_INDEX_LDN, LDN_PMC3 },
 	/* I/O Port Base Address 80h */
-	{HOST_INDEX_IOBAD0_MSB, 0x00},
-	{HOST_INDEX_IOBAD0_LSB, 0x80},
-	{HOST_INDEX_IOBAD1_MSB, 0x00},
-	{HOST_INDEX_IOBAD1_LSB, 0x00},
+	{ HOST_INDEX_IOBAD0_MSB, 0x00 },
+	{ HOST_INDEX_IOBAD0_LSB, 0x80 },
+	{ HOST_INDEX_IOBAD1_MSB, 0x00 },
+	{ HOST_INDEX_IOBAD1_LSB, 0x00 },
 	/* Set IRQ=00h for logical device */
-	{HOST_INDEX_IRQNUMX, 0x00},
+	{ HOST_INDEX_IRQNUMX, 0x00 },
 	/* Enable logical device */
-	{HOST_INDEX_LDA, 0x01},
+	{ HOST_INDEX_LDA, 0x01 },
 };
 
 /*
@@ -115,28 +115,28 @@ static const struct ec2i_t pm3_settings[] = {
  */
 static const struct ec2i_t rtct_settings[] = {
 	/* Select logical device 10h(RTCT) */
-	{HOST_INDEX_LDN, LDN_RTCT},
+	{ HOST_INDEX_LDN, LDN_RTCT },
 	/* P80L Begin Index */
-	{HOST_INDEX_DSLDC4, P80L_P80LB},
+	{ HOST_INDEX_DSLDC4, P80L_P80LB },
 	/* P80L End Index */
-	{HOST_INDEX_DSLDC5, P80L_P80LE},
+	{ HOST_INDEX_DSLDC5, P80L_P80LE },
 	/* P80L Current Index */
-	{HOST_INDEX_DSLDC6, P80L_P80LC},
+	{ HOST_INDEX_DSLDC6, P80L_P80LC },
 };
 
 #ifdef CONFIG_UART_HOST
 static const struct ec2i_t uart2_settings[] = {
 	/* Select logical device 2h(UART2) */
-	{HOST_INDEX_LDN, LDN_UART2},
+	{ HOST_INDEX_LDN, LDN_UART2 },
 	/*
 	 * I/O port base address is 2F8h.
 	 * Host can use LPC I/O port 0x2F8 ~ 0x2FF to access UART2.
 	 * See specification 7.24.4 for more detial.
 	 */
-	{HOST_INDEX_IOBAD0_MSB, 0x02},
-	{HOST_INDEX_IOBAD0_LSB, 0xF8},
+	{ HOST_INDEX_IOBAD0_MSB, 0x02 },
+	{ HOST_INDEX_IOBAD0_LSB, 0xF8 },
 	/* IRQ number is 3 */
-	{HOST_INDEX_IRQNUMX, 0x03},
+	{ HOST_INDEX_IRQNUMX, 0x03 },
 	/*
 	 * Interrupt Request Type Select
 	 * bit1, 0: IRQ request is buffered and applied to SERIRQ.
@@ -144,9 +144,9 @@ static const struct ec2i_t uart2_settings[] = {
 	 * bit0, 0: Edge triggered mode.
 	 *       1: Level triggered mode.
 	 */
-	{HOST_INDEX_IRQTP, 0x02},
+	{ HOST_INDEX_IRQTP, 0x02 },
 	/* Enable logical device */
-	{HOST_INDEX_LDA, 0x01},
+	{ HOST_INDEX_LDA, 0x01 },
 };
 #endif
 
@@ -163,7 +163,7 @@ enum ec2i_status_mask {
 	EC2I_STATUS_CRIB = BIT(1),
 	/* 1: EC write-access is still processing with IHD register. */
 	EC2I_STATUS_CWIB = BIT(2),
-	EC2I_STATUS_ALL  = (EC2I_STATUS_CRIB | EC2I_STATUS_CWIB),
+	EC2I_STATUS_ALL = (EC2I_STATUS_CRIB | EC2I_STATUS_CWIB),
 };
 
 static int ec2i_wait_status_bit_cleared(enum ec2i_status_mask mask)
@@ -288,8 +288,7 @@ static void pnpcfg_configure(const struct ec2i_t *settings, size_t entries)
 	}
 }
 
-#define PNPCFG(_s)						\
-	pnpcfg_configure(_s##_settings, ARRAY_SIZE(_s##_settings))
+#define PNPCFG(_s) pnpcfg_configure(_s##_settings, ARRAY_SIZE(_s##_settings))
 
 static void pnpcfg_init(void)
 {
diff --git a/chip/it83xx/ec2i_chip.h b/chip/it83xx/ec2i_chip.h
index c8069f4ff5..73eeaa31f7 100644
--- a/chip/it83xx/ec2i_chip.h
+++ b/chip/it83xx/ec2i_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,9 +8,9 @@
 #ifndef __CROS_EC_EC2I_CHIP_H
 #define __CROS_EC_EC2I_CHIP_H
 
-#define P80L_P80LB               0
-#define P80L_P80LE               0x3F
-#define P80L_P80LC               0
+#define P80L_P80LB 0
+#define P80L_P80LE 0x3F
+#define P80L_P80LC 0
 #define P80L_BRAM_BANK1_SIZE_MASK 0x3F
 
 /* Index list of the host interface registers of PNPCFG */
diff --git a/chip/it83xx/espi.c b/chip/it83xx/espi.c
index bef877449e..bf52b87404 100644
--- a/chip/it83xx/espi.c
+++ b/chip/it83xx/espi.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,151 +18,119 @@
 #include "util.h"
 
 /* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args)
 
 struct vw_channel_t {
-	uint8_t  index;         /* VW index of signal */
-	uint8_t  level_mask;    /* level bit of signal */
-	uint8_t  valid_mask;    /* valid bit of signal */
+	uint8_t index; /* VW index of signal */
+	uint8_t level_mask; /* level bit of signal */
+	uint8_t valid_mask; /* valid bit of signal */
 };
 
 /* VW settings after the controller enables the VW channel. */
 static const struct vw_channel_t en_vw_setting[] = {
-	/* EC sends SUS_ACK# = 1 VW to PCH. That does not apply to GLK SoC. */
+/* EC sends SUS_ACK# = 1 VW to PCH. That does not apply to GLK SoC. */
 #ifndef CONFIG_CHIPSET_GEMINILAKE
-	{ESPI_SYSTEM_EVENT_VW_IDX_40,
-		VW_LEVEL_FIELD(0),
-		VW_VALID_FIELD(VW_IDX_40_SUS_ACK)},
+	{ ESPI_SYSTEM_EVENT_VW_IDX_40, VW_LEVEL_FIELD(0),
+	  VW_VALID_FIELD(VW_IDX_40_SUS_ACK) },
 #endif
 };
 
 /* VW settings after the controller enables the OOB channel. */
 static const struct vw_channel_t en_oob_setting[] = {
-	{ESPI_SYSTEM_EVENT_VW_IDX_4,
-		VW_LEVEL_FIELD(0),
-		VW_VALID_FIELD(VW_IDX_4_OOB_RST_ACK)},
+	{ ESPI_SYSTEM_EVENT_VW_IDX_4, VW_LEVEL_FIELD(0),
+	  VW_VALID_FIELD(VW_IDX_4_OOB_RST_ACK) },
 };
 
 /* VW settings after the controller enables the flash channel. */
 static const struct vw_channel_t en_flash_setting[] = {
-	{ESPI_SYSTEM_EVENT_VW_IDX_5,
-		VW_LEVEL_FIELD(VW_IDX_5_BTLD_STATUS_DONE),
-		VW_VALID_FIELD(VW_IDX_5_BTLD_STATUS_DONE)},
+	{ ESPI_SYSTEM_EVENT_VW_IDX_5, VW_LEVEL_FIELD(VW_IDX_5_BTLD_STATUS_DONE),
+	  VW_VALID_FIELD(VW_IDX_5_BTLD_STATUS_DONE) },
 };
 
 /* VW settings at host startup */
 static const struct vw_channel_t vw_host_startup_setting[] = {
-	{ESPI_SYSTEM_EVENT_VW_IDX_6,
-		VW_LEVEL_FIELD(VW_IDX_6_SCI | VW_IDX_6_SMI |
-				VW_IDX_6_RCIN | VW_IDX_6_HOST_RST_ACK),
-		VW_VALID_FIELD(VW_IDX_6_SCI | VW_IDX_6_SMI |
-				VW_IDX_6_RCIN | VW_IDX_6_HOST_RST_ACK)},
+	{ ESPI_SYSTEM_EVENT_VW_IDX_6,
+	  VW_LEVEL_FIELD(VW_IDX_6_SCI | VW_IDX_6_SMI | VW_IDX_6_RCIN |
+			 VW_IDX_6_HOST_RST_ACK),
+	  VW_VALID_FIELD(VW_IDX_6_SCI | VW_IDX_6_SMI | VW_IDX_6_RCIN |
+			 VW_IDX_6_HOST_RST_ACK) },
 };
 
 #define VW_CHAN(name, idx, level, valid) \
-	[(name - VW_SIGNAL_START)] = {idx, level, valid}
+	[(name - VW_SIGNAL_START)] = { idx, level, valid }
 
 /* VW signals used in eSPI (NOTE: must match order of enum espi_vw_signal). */
 static const struct vw_channel_t vw_channel_list[] = {
 	/* index 02h: controller to peripheral. */
-	VW_CHAN(VW_SLP_S3_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_2,
+	VW_CHAN(VW_SLP_S3_L, ESPI_SYSTEM_EVENT_VW_IDX_2,
 		VW_LEVEL_FIELD(VW_IDX_2_SLP_S3),
 		VW_VALID_FIELD(VW_IDX_2_SLP_S3)),
-	VW_CHAN(VW_SLP_S4_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_2,
+	VW_CHAN(VW_SLP_S4_L, ESPI_SYSTEM_EVENT_VW_IDX_2,
 		VW_LEVEL_FIELD(VW_IDX_2_SLP_S4),
 		VW_VALID_FIELD(VW_IDX_2_SLP_S4)),
-	VW_CHAN(VW_SLP_S5_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_2,
+	VW_CHAN(VW_SLP_S5_L, ESPI_SYSTEM_EVENT_VW_IDX_2,
 		VW_LEVEL_FIELD(VW_IDX_2_SLP_S5),
 		VW_VALID_FIELD(VW_IDX_2_SLP_S5)),
 	/* index 03h: controller to peripheral. */
-	VW_CHAN(VW_SUS_STAT_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_3,
+	VW_CHAN(VW_SUS_STAT_L, ESPI_SYSTEM_EVENT_VW_IDX_3,
 		VW_LEVEL_FIELD(VW_IDX_3_SUS_STAT),
 		VW_VALID_FIELD(VW_IDX_3_SUS_STAT)),
-	VW_CHAN(VW_PLTRST_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_3,
+	VW_CHAN(VW_PLTRST_L, ESPI_SYSTEM_EVENT_VW_IDX_3,
 		VW_LEVEL_FIELD(VW_IDX_3_PLTRST),
 		VW_VALID_FIELD(VW_IDX_3_PLTRST)),
-	VW_CHAN(VW_OOB_RST_WARN,
-		ESPI_SYSTEM_EVENT_VW_IDX_3,
+	VW_CHAN(VW_OOB_RST_WARN, ESPI_SYSTEM_EVENT_VW_IDX_3,
 		VW_LEVEL_FIELD(VW_IDX_3_OOB_RST_WARN),
 		VW_VALID_FIELD(VW_IDX_3_OOB_RST_WARN)),
 	/* index 04h: peripheral to controller. */
-	VW_CHAN(VW_OOB_RST_ACK,
-		ESPI_SYSTEM_EVENT_VW_IDX_4,
+	VW_CHAN(VW_OOB_RST_ACK, ESPI_SYSTEM_EVENT_VW_IDX_4,
 		VW_LEVEL_FIELD(VW_IDX_4_OOB_RST_ACK),
 		VW_VALID_FIELD(VW_IDX_4_OOB_RST_ACK)),
-	VW_CHAN(VW_WAKE_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_4,
-		VW_LEVEL_FIELD(VW_IDX_4_WAKE),
-		VW_VALID_FIELD(VW_IDX_4_WAKE)),
-	VW_CHAN(VW_PME_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_4,
-		VW_LEVEL_FIELD(VW_IDX_4_PME),
-		VW_VALID_FIELD(VW_IDX_4_PME)),
+	VW_CHAN(VW_WAKE_L, ESPI_SYSTEM_EVENT_VW_IDX_4,
+		VW_LEVEL_FIELD(VW_IDX_4_WAKE), VW_VALID_FIELD(VW_IDX_4_WAKE)),
+	VW_CHAN(VW_PME_L, ESPI_SYSTEM_EVENT_VW_IDX_4,
+		VW_LEVEL_FIELD(VW_IDX_4_PME), VW_VALID_FIELD(VW_IDX_4_PME)),
 	/* index 05h: peripheral to controller. */
-	VW_CHAN(VW_ERROR_FATAL,
-		ESPI_SYSTEM_EVENT_VW_IDX_5,
-		VW_LEVEL_FIELD(VW_IDX_5_FATAL),
-		VW_VALID_FIELD(VW_IDX_5_FATAL)),
-	VW_CHAN(VW_ERROR_NON_FATAL,
-		ESPI_SYSTEM_EVENT_VW_IDX_5,
+	VW_CHAN(VW_ERROR_FATAL, ESPI_SYSTEM_EVENT_VW_IDX_5,
+		VW_LEVEL_FIELD(VW_IDX_5_FATAL), VW_VALID_FIELD(VW_IDX_5_FATAL)),
+	VW_CHAN(VW_ERROR_NON_FATAL, ESPI_SYSTEM_EVENT_VW_IDX_5,
 		VW_LEVEL_FIELD(VW_IDX_5_NON_FATAL),
 		VW_VALID_FIELD(VW_IDX_5_NON_FATAL)),
-	VW_CHAN(VW_PERIPHERAL_BTLD_STATUS_DONE,
-		ESPI_SYSTEM_EVENT_VW_IDX_5,
+	VW_CHAN(VW_PERIPHERAL_BTLD_STATUS_DONE, ESPI_SYSTEM_EVENT_VW_IDX_5,
 		VW_LEVEL_FIELD(VW_IDX_5_BTLD_STATUS_DONE),
 		VW_VALID_FIELD(VW_IDX_5_BTLD_STATUS_DONE)),
 	/* index 06h: peripheral to controller. */
-	VW_CHAN(VW_SCI_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_6,
-		VW_LEVEL_FIELD(VW_IDX_6_SCI),
-		VW_VALID_FIELD(VW_IDX_6_SCI)),
-	VW_CHAN(VW_SMI_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_6,
-		VW_LEVEL_FIELD(VW_IDX_6_SMI),
-		VW_VALID_FIELD(VW_IDX_6_SMI)),
-	VW_CHAN(VW_RCIN_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_6,
-		VW_LEVEL_FIELD(VW_IDX_6_RCIN),
-		VW_VALID_FIELD(VW_IDX_6_RCIN)),
-	VW_CHAN(VW_HOST_RST_ACK,
-		ESPI_SYSTEM_EVENT_VW_IDX_6,
+	VW_CHAN(VW_SCI_L, ESPI_SYSTEM_EVENT_VW_IDX_6,
+		VW_LEVEL_FIELD(VW_IDX_6_SCI), VW_VALID_FIELD(VW_IDX_6_SCI)),
+	VW_CHAN(VW_SMI_L, ESPI_SYSTEM_EVENT_VW_IDX_6,
+		VW_LEVEL_FIELD(VW_IDX_6_SMI), VW_VALID_FIELD(VW_IDX_6_SMI)),
+	VW_CHAN(VW_RCIN_L, ESPI_SYSTEM_EVENT_VW_IDX_6,
+		VW_LEVEL_FIELD(VW_IDX_6_RCIN), VW_VALID_FIELD(VW_IDX_6_RCIN)),
+	VW_CHAN(VW_HOST_RST_ACK, ESPI_SYSTEM_EVENT_VW_IDX_6,
 		VW_LEVEL_FIELD(VW_IDX_6_HOST_RST_ACK),
 		VW_VALID_FIELD(VW_IDX_6_HOST_RST_ACK)),
 	/* index 07h: controller to peripheral. */
-	VW_CHAN(VW_HOST_RST_WARN,
-		ESPI_SYSTEM_EVENT_VW_IDX_7,
+	VW_CHAN(VW_HOST_RST_WARN, ESPI_SYSTEM_EVENT_VW_IDX_7,
 		VW_LEVEL_FIELD(VW_IDX_7_HOST_RST_WARN),
 		VW_VALID_FIELD(VW_IDX_7_HOST_RST_WARN)),
 	/* index 40h: peripheral to controller. */
-	VW_CHAN(VW_SUS_ACK,
-		ESPI_SYSTEM_EVENT_VW_IDX_40,
+	VW_CHAN(VW_SUS_ACK, ESPI_SYSTEM_EVENT_VW_IDX_40,
 		VW_LEVEL_FIELD(VW_IDX_40_SUS_ACK),
 		VW_VALID_FIELD(VW_IDX_40_SUS_ACK)),
 	/* index 41h: controller to peripheral. */
-	VW_CHAN(VW_SUS_WARN_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_41,
+	VW_CHAN(VW_SUS_WARN_L, ESPI_SYSTEM_EVENT_VW_IDX_41,
 		VW_LEVEL_FIELD(VW_IDX_41_SUS_WARN),
 		VW_VALID_FIELD(VW_IDX_41_SUS_WARN)),
-	VW_CHAN(VW_SUS_PWRDN_ACK_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_41,
+	VW_CHAN(VW_SUS_PWRDN_ACK_L, ESPI_SYSTEM_EVENT_VW_IDX_41,
 		VW_LEVEL_FIELD(VW_IDX_41_SUS_PWRDN_ACK),
 		VW_VALID_FIELD(VW_IDX_41_SUS_PWRDN_ACK)),
-	VW_CHAN(VW_SLP_A_L,
-		ESPI_SYSTEM_EVENT_VW_IDX_41,
+	VW_CHAN(VW_SLP_A_L, ESPI_SYSTEM_EVENT_VW_IDX_41,
 		VW_LEVEL_FIELD(VW_IDX_41_SLP_A),
 		VW_VALID_FIELD(VW_IDX_41_SLP_A)),
 	/* index 42h: controller to peripheral. */
-	VW_CHAN(VW_SLP_LAN,
-		ESPI_SYSTEM_EVENT_VW_IDX_42,
+	VW_CHAN(VW_SLP_LAN, ESPI_SYSTEM_EVENT_VW_IDX_42,
 		VW_LEVEL_FIELD(VW_IDX_42_SLP_LAN),
 		VW_VALID_FIELD(VW_IDX_42_SLP_LAN)),
-	VW_CHAN(VW_SLP_WLAN,
-		ESPI_SYSTEM_EVENT_VW_IDX_42,
+	VW_CHAN(VW_SLP_WLAN, ESPI_SYSTEM_EVENT_VW_IDX_42,
 		VW_LEVEL_FIELD(VW_IDX_42_SLP_WLAN),
 		VW_VALID_FIELD(VW_IDX_42_SLP_WLAN)),
 };
@@ -221,11 +189,11 @@ int espi_vw_get_wire(enum espi_vw_signal signal)
 
 	/* Not valid */
 	if (!(IT83XX_ESPI_VWIDX(vw_channel_list[i].index) &
-		vw_channel_list[i].valid_mask))
+	      vw_channel_list[i].valid_mask))
 		return 0;
 
 	return !!(IT83XX_ESPI_VWIDX(vw_channel_list[i].index) &
-		vw_channel_list[i].level_mask);
+		  vw_channel_list[i].level_mask);
 }
 
 /**
@@ -265,7 +233,7 @@ int espi_vw_disable_wire_int(enum espi_vw_signal signal)
 
 /* Configure virtual wire outputs */
 static void espi_configure_vw(const struct vw_channel_t *settings,
-						size_t entries)
+			      size_t entries)
 {
 	size_t i;
 
@@ -277,13 +245,13 @@ static void espi_configure_vw(const struct vw_channel_t *settings,
 static void espi_vw_host_startup(void)
 {
 	espi_configure_vw(vw_host_startup_setting,
-				ARRAY_SIZE(vw_host_startup_setting));
+			  ARRAY_SIZE(vw_host_startup_setting));
 }
 
 static void espi_vw_no_isr(uint8_t flag_changed, uint8_t vw_evt)
 {
 	CPRINTS("espi VW interrupt event is ignored! (bit%d at VWCTRL1)",
-								vw_evt);
+		vw_evt);
 }
 
 #ifndef CONFIG_CHIPSET_GEMINILAKE
@@ -298,7 +266,7 @@ static void espi_vw_idx7_isr(uint8_t flag_changed, uint8_t vw_evt)
 {
 	if (flag_changed & VW_LEVEL_FIELD(VW_IDX_7_HOST_RST_WARN))
 		espi_vw_set_wire(VW_HOST_RST_ACK,
-			espi_vw_get_wire(VW_HOST_RST_WARN));
+				 espi_vw_get_wire(VW_HOST_RST_WARN));
 }
 
 #ifdef CONFIG_CHIPSET_RESET_HOOK
@@ -329,7 +297,7 @@ static void espi_vw_idx3_isr(uint8_t flag_changed, uint8_t vw_evt)
 
 	if (flag_changed & VW_LEVEL_FIELD(VW_IDX_3_OOB_RST_WARN))
 		espi_vw_set_wire(VW_OOB_RST_ACK,
-			espi_vw_get_wire(VW_OOB_RST_WARN));
+				 espi_vw_get_wire(VW_OOB_RST_WARN));
 }
 
 static void espi_vw_idx2_isr(uint8_t flag_changed, uint8_t vw_evt)
@@ -353,25 +321,25 @@ struct vw_interrupt_t {
  */
 #ifdef CONFIG_CHIPSET_GEMINILAKE
 static const struct vw_interrupt_t vw_isr_list[] = {
-	[0] = {espi_vw_idx2_isr,  ESPI_SYSTEM_EVENT_VW_IDX_2},
-	[1] = {espi_vw_idx3_isr,  ESPI_SYSTEM_EVENT_VW_IDX_3},
-	[2] = {espi_vw_idx7_isr,  ESPI_SYSTEM_EVENT_VW_IDX_7},
-	[3] = {espi_vw_no_isr,    ESPI_SYSTEM_EVENT_VW_IDX_41},
-	[4] = {espi_vw_no_isr,    ESPI_SYSTEM_EVENT_VW_IDX_42},
-	[5] = {espi_vw_no_isr,    ESPI_SYSTEM_EVENT_VW_IDX_43},
-	[6] = {espi_vw_no_isr,    ESPI_SYSTEM_EVENT_VW_IDX_44},
-	[7] = {espi_vw_no_isr,    ESPI_SYSTEM_EVENT_VW_IDX_47},
+	[0] = { espi_vw_idx2_isr, ESPI_SYSTEM_EVENT_VW_IDX_2 },
+	[1] = { espi_vw_idx3_isr, ESPI_SYSTEM_EVENT_VW_IDX_3 },
+	[2] = { espi_vw_idx7_isr, ESPI_SYSTEM_EVENT_VW_IDX_7 },
+	[3] = { espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_41 },
+	[4] = { espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_42 },
+	[5] = { espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_43 },
+	[6] = { espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_44 },
+	[7] = { espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_47 },
 };
 #else
 static const struct vw_interrupt_t vw_isr_list[] = {
-	[0] = {espi_vw_idx2_isr,  ESPI_SYSTEM_EVENT_VW_IDX_2},
-	[1] = {espi_vw_idx3_isr,  ESPI_SYSTEM_EVENT_VW_IDX_3},
-	[2] = {espi_vw_idx7_isr,  ESPI_SYSTEM_EVENT_VW_IDX_7},
-	[3] = {espi_vw_idx41_isr, ESPI_SYSTEM_EVENT_VW_IDX_41},
-	[4] = {espi_vw_no_isr,    ESPI_SYSTEM_EVENT_VW_IDX_42},
-	[5] = {espi_vw_no_isr,    ESPI_SYSTEM_EVENT_VW_IDX_43},
-	[6] = {espi_vw_no_isr,    ESPI_SYSTEM_EVENT_VW_IDX_44},
-	[7] = {espi_vw_no_isr,    ESPI_SYSTEM_EVENT_VW_IDX_47},
+	[0] = { espi_vw_idx2_isr, ESPI_SYSTEM_EVENT_VW_IDX_2 },
+	[1] = { espi_vw_idx3_isr, ESPI_SYSTEM_EVENT_VW_IDX_3 },
+	[2] = { espi_vw_idx7_isr, ESPI_SYSTEM_EVENT_VW_IDX_7 },
+	[3] = { espi_vw_idx41_isr, ESPI_SYSTEM_EVENT_VW_IDX_41 },
+	[4] = { espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_42 },
+	[5] = { espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_43 },
+	[6] = { espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_44 },
+	[7] = { espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_47 },
 };
 #endif
 
@@ -490,7 +458,7 @@ static void espi_enable_reset(void)
 
 #endif
 	IT83XX_GPIO_GCR = (IT83XX_GPIO_GCR & ~0x6) |
-		(config << IT83XX_GPIO_GCR_LPC_RST_POS);
+			  (config << IT83XX_GPIO_GCR_LPC_RST_POS);
 
 	/* enable interrupt of EC's espi_reset pin */
 	gpio_clear_pending_interrupt(GPIO_ESPI_RESET_L);
@@ -537,14 +505,10 @@ static void espi_no_isr(uint8_t evt)
  * IT83XX_ESPI_ESGCTRL0 register.
  */
 static void (*espi_isr[])(uint8_t evt) = {
-	[0] = espi_no_isr,
-	[1] = espi_vw_en_asserted,
-	[2] = espi_oob_en_asserted,
-	[3] = espi_flash_en_asserted,
-	[4] = espi_no_isr,
-	[5] = espi_no_isr,
-	[6] = espi_no_isr,
-	[7] = espi_no_isr,
+	[0] = espi_no_isr,	    [1] = espi_vw_en_asserted,
+	[2] = espi_oob_en_asserted, [3] = espi_flash_en_asserted,
+	[4] = espi_no_isr,	    [5] = espi_no_isr,
+	[6] = espi_no_isr,	    [7] = espi_no_isr,
 };
 
 void espi_interrupt(void)
diff --git a/chip/it83xx/fan.c b/chip/it83xx/fan.c
index adb3985025..b8b805453e 100644
--- a/chip/it83xx/fan.c
+++ b/chip/it83xx/fan.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,12 +18,12 @@
 #include "task.h"
 #include "util.h"
 
-#define TACH_EC_FREQ                8000000
-#define FAN_CTRL_BASED_MS           10
-#define FAN_CTRL_INTERVAL_MAX_MS    60
+#define TACH_EC_FREQ 8000000
+#define FAN_CTRL_BASED_MS 10
+#define FAN_CTRL_INTERVAL_MAX_MS 60
 
 /* The sampling rate (fs) is FreqEC / 128 */
-#define TACH_DATA_VALID_TIMEOUT_MS  (0xFFFF * 128 / (TACH_EC_FREQ / 1000))
+#define TACH_DATA_VALID_TIMEOUT_MS (0xFFFF * 128 / (TACH_EC_FREQ / 1000))
 
 /*
  * Fan Speed (RPM) = 60 / (1/fs sec * {FnTMRR, FnTLRR} * P)
@@ -37,25 +37,25 @@
 #define TACH1_TO_RPM(pulse, raw) (raw * 120 / (pulse * 2))
 
 enum fan_output_s {
-	FAN_DUTY_I  = 0x01,
-	FAN_DUTY_R  = 0x02,
+	FAN_DUTY_I = 0x01,
+	FAN_DUTY_R = 0x02,
 	FAN_DUTY_OV = 0x03,
 	FAN_DUTY_DONE = 0x04,
 };
 
 struct fan_info {
-	unsigned int    flags;
-	int             fan_mode;
-	int             fan_p;
-	int             rpm_target;
-	int             rpm_actual;
-	int             tach_valid_ms;
-	int             rpm_re;
-	int             fan_ms;
-	int             fan_ms_idx;
-	int             startup_duty;
+	unsigned int flags;
+	int fan_mode;
+	int fan_p;
+	int rpm_target;
+	int rpm_actual;
+	int tach_valid_ms;
+	int rpm_re;
+	int fan_ms;
+	int fan_ms_idx;
+	int startup_duty;
 	enum fan_status fan_sts;
-	int             enabled;
+	int enabled;
 };
 static struct fan_info fan_info_data[TACH_CH_COUNT];
 
@@ -72,7 +72,8 @@ static void fan_set_interval(int ch)
 	tach_ch = tach_bind(ch);
 
 	diff = ABS(fan_info_data[tach_ch].rpm_target -
-		fan_info_data[tach_ch].rpm_actual) / 100;
+		   fan_info_data[tach_ch].rpm_actual) /
+	       100;
 
 	fan_ms = FAN_CTRL_INTERVAL_MAX_MS;
 
@@ -122,7 +123,7 @@ void fan_set_enabled(int ch, int enabled)
 		disable_sleep(SLEEP_MASK_FAN);
 		/* enable timer interrupt for fan control */
 		ext_timer_start(FAN_CTRL_EXT_TIMER, 1);
-	/* disable */
+		/* disable */
 	} else {
 		fan_set_duty(ch, 0);
 
@@ -245,9 +246,8 @@ enum fan_status fan_get_status(int ch)
 int fan_is_stalled(int ch)
 {
 	/* Must be enabled with non-zero target to stall */
-	if (!fan_get_enabled(ch) ||
-		fan_get_rpm_target(ch) == 0 ||
-		!fan_get_duty(ch))
+	if (!fan_get_enabled(ch) || fan_get_rpm_target(ch) == 0 ||
+	    !fan_get_duty(ch))
 		return 0;
 
 	/* Check for stall condition */
@@ -273,8 +273,7 @@ static void fan_ctrl(int ch)
 	tach_ch = tach_bind(ch);
 
 	fan_info_data[tach_ch].fan_ms_idx += FAN_CTRL_BASED_MS;
-	if (fan_info_data[tach_ch].fan_ms_idx >
-		fan_info_data[tach_ch].fan_ms) {
+	if (fan_info_data[tach_ch].fan_ms_idx > fan_info_data[tach_ch].fan_ms) {
 		fan_info_data[tach_ch].fan_ms_idx = 0x00;
 		adjust = 1;
 	}
@@ -411,7 +410,7 @@ static void proc_tach(int ch)
 	} else {
 		fan_info_data[tach_ch].tach_valid_ms += FAN_CTRL_BASED_MS;
 		if (fan_info_data[tach_ch].tach_valid_ms >
-			TACH_DATA_VALID_TIMEOUT_MS)
+		    TACH_DATA_VALID_TIMEOUT_MS)
 			fan_info_data[tach_ch].rpm_actual = 0;
 	}
 }
@@ -436,14 +435,12 @@ static void fan_init(void)
 	enum tach_ch_sel tach_ch;
 
 	for (ch = 0; ch < fan_get_count(); ch++) {
-
 		rpm_re = fan_tach[pwm_channels[FAN_CH(ch)].channel].rpm_re;
 		fan_p = fan_tach[pwm_channels[FAN_CH(ch)].channel].fan_p;
 		s_duty = fan_tach[pwm_channels[FAN_CH(ch)].channel].s_duty;
 		tach_ch = tach_bind(FAN_CH(ch));
 
 		if (tach_ch < TACH_CH_COUNT) {
-
 			if (tach_ch == TACH_CH_TACH0B) {
 				/* GPJ2 will select TACH0B as its alt. */
 				IT83XX_GPIO_GRC5 |= 0x01;
@@ -473,6 +470,6 @@ static void fan_init(void)
 
 	/* init external timer for fan control */
 	ext_timer_ms(FAN_CTRL_EXT_TIMER, EXT_PSR_32P768K_HZ, 0, 0,
-			FAN_CTRL_BASED_MS, 1, 0);
+		     FAN_CTRL_BASED_MS, 1, 0);
 }
 DECLARE_HOOK(HOOK_INIT, fan_init, HOOK_PRIO_INIT_FAN);
diff --git a/chip/it83xx/flash.c b/chip/it83xx/flash.c
index ed02aa882f..25aefa2f66 100644
--- a/chip/it83xx/flash.c
+++ b/chip/it83xx/flash.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,45 +17,45 @@
 #include "shared_mem.h"
 #include "uart.h"
 
-#define FLASH_DMA_START ((uint32_t) &__flash_dma_start)
+#define FLASH_DMA_START ((uint32_t)&__flash_dma_start)
 #define FLASH_DMA_CODE __attribute__((section(".flash_direct_map")))
-#define FLASH_ILM0_ADDR ((uint32_t) &__ilm0_ram_code)
+#define FLASH_ILM0_ADDR ((uint32_t)&__ilm0_ram_code)
 
 /* erase size of sector is 1KB or 4KB */
 #define FLASH_SECTOR_ERASE_SIZE CONFIG_FLASH_ERASE_SIZE
 
 #ifdef IT83XX_CHIP_FLASH_IS_KGD
 /* page program command  */
-#define FLASH_CMD_PAGE_WRITE    0x2
+#define FLASH_CMD_PAGE_WRITE 0x2
 /* ector erase command (erase size is 4KB) */
-#define FLASH_CMD_SECTOR_ERASE  0x20
+#define FLASH_CMD_SECTOR_ERASE 0x20
 /* command for flash write */
-#define FLASH_CMD_WRITE         FLASH_CMD_PAGE_WRITE
+#define FLASH_CMD_WRITE FLASH_CMD_PAGE_WRITE
 #else
 /* Auto address increment programming */
-#define FLASH_CMD_AAI_WORD      0xAD
+#define FLASH_CMD_AAI_WORD 0xAD
 /* Flash sector erase (1K bytes) command */
-#define FLASH_CMD_SECTOR_ERASE  0xD7
+#define FLASH_CMD_SECTOR_ERASE 0xD7
 /* command for flash write */
-#define FLASH_CMD_WRITE         FLASH_CMD_AAI_WORD
+#define FLASH_CMD_WRITE FLASH_CMD_AAI_WORD
 #endif
 /* Write status register */
-#define FLASH_CMD_WRSR         0x01
+#define FLASH_CMD_WRSR 0x01
 /* Write disable */
-#define FLASH_CMD_WRDI         0x04
+#define FLASH_CMD_WRDI 0x04
 /* Write enable */
-#define FLASH_CMD_WREN         0x06
+#define FLASH_CMD_WREN 0x06
 /* Read status register */
-#define FLASH_CMD_RS           0x05
+#define FLASH_CMD_RS 0x05
 
 #if (CONFIG_FLASH_SIZE_BYTES == 0x80000) && defined(CHIP_CORE_NDS32)
-#define FLASH_TEXT_START ((uint32_t) &__flash_text_start)
+#define FLASH_TEXT_START ((uint32_t)&__flash_text_start)
 /* Apply workaround of the issue (b:111808417) */
 #define IMMU_CACHE_TAG_INVALID
 /* The default tag index of immu. */
 #define IMMU_TAG_INDEX_BY_DEFAULT 0x7E000
 /* immu cache size is 8K bytes. */
-#define IMMU_SIZE                 0x2000
+#define IMMU_SIZE 0x2000
 #endif
 
 static int stuck_locked;
@@ -88,18 +88,18 @@ enum flash_status_mask {
 };
 
 enum dlm_address_view {
-	SCAR0_ILM0_DLM13   = 0x8D000, /* DLM ~ 0x8DFFF H2RAM map LPC I/O */
-	SCAR1_ILM1_DLM11   = 0x8B000, /* DLM ~ 0x8BFFF ram 44K ~ 48K */
-	SCAR2_ILM2_DLM14   = 0x8E000, /* DLM ~ 0x8EFFF RO/RW flash code DMA */
-	SCAR3_ILM3_DLM6    = 0x86000, /* DLM ~ 0x86FFF ram 24K ~ 28K */
-	SCAR4_ILM4_DLM7    = 0x87000, /* DLM ~ 0x87FFF ram 28K ~ 32K */
-	SCAR5_ILM5_DLM8    = 0x88000, /* DLM ~ 0x88FFF ram 32K ~ 36K */
-	SCAR6_ILM6_DLM9    = 0x89000, /* DLM ~ 0x89FFF ram 36K ~ 40K */
-	SCAR7_ILM7_DLM10   = 0x8A000, /* DLM ~ 0x8AFFF ram 40K ~ 44K */
-	SCAR8_ILM8_DLM4    = 0x84000, /* DLM ~ 0x84FFF ram 16K ~ 20K */
-	SCAR9_ILM9_DLM5    = 0x85000, /* DLM ~ 0x85FFF ram 20K ~ 24K */
-	SCAR10_ILM10_DLM2  = 0x82000, /* DLM ~ 0x82FFF ram 8K ~ 12K */
-	SCAR11_ILM11_DLM3  = 0x83000, /* DLM ~ 0x83FFF ram 12K ~ 16K */
+	SCAR0_ILM0_DLM13 = 0x8D000, /* DLM ~ 0x8DFFF H2RAM map LPC I/O */
+	SCAR1_ILM1_DLM11 = 0x8B000, /* DLM ~ 0x8BFFF ram 44K ~ 48K */
+	SCAR2_ILM2_DLM14 = 0x8E000, /* DLM ~ 0x8EFFF RO/RW flash code DMA */
+	SCAR3_ILM3_DLM6 = 0x86000, /* DLM ~ 0x86FFF ram 24K ~ 28K */
+	SCAR4_ILM4_DLM7 = 0x87000, /* DLM ~ 0x87FFF ram 28K ~ 32K */
+	SCAR5_ILM5_DLM8 = 0x88000, /* DLM ~ 0x88FFF ram 32K ~ 36K */
+	SCAR6_ILM6_DLM9 = 0x89000, /* DLM ~ 0x89FFF ram 36K ~ 40K */
+	SCAR7_ILM7_DLM10 = 0x8A000, /* DLM ~ 0x8AFFF ram 40K ~ 44K */
+	SCAR8_ILM8_DLM4 = 0x84000, /* DLM ~ 0x84FFF ram 16K ~ 20K */
+	SCAR9_ILM9_DLM5 = 0x85000, /* DLM ~ 0x85FFF ram 20K ~ 24K */
+	SCAR10_ILM10_DLM2 = 0x82000, /* DLM ~ 0x82FFF ram 8K ~ 12K */
+	SCAR11_ILM11_DLM3 = 0x83000, /* DLM ~ 0x83FFF ram 12K ~ 16K */
 	SCAR12_ILM12_DLM12 = 0x8C000, /* DLM ~ 0x8CFFF immu cache */
 };
 
@@ -177,8 +177,8 @@ void FLASH_DMA_CODE dma_flash_write_dat(uint8_t wdata)
 	IT83XX_SMFI_ECINDDR = wdata;
 }
 
-void FLASH_DMA_CODE dma_flash_transaction(int wlen, uint8_t *wbuf,
-					int rlen, uint8_t *rbuf, int cmd_end)
+void FLASH_DMA_CODE dma_flash_transaction(int wlen, uint8_t *wbuf, int rlen,
+					  uint8_t *rbuf, int cmd_end)
 {
 	int i;
 
@@ -197,10 +197,10 @@ void FLASH_DMA_CODE dma_flash_transaction(int wlen, uint8_t *wbuf,
 }
 
 void FLASH_DMA_CODE dma_flash_cmd_read_status(enum flash_status_mask mask,
-						enum flash_status_mask target)
+					      enum flash_status_mask target)
 {
 	uint8_t status[1];
-	uint8_t cmd_rs[] = {FLASH_CMD_RS};
+	uint8_t cmd_rs[] = { FLASH_CMD_RS };
 
 	/*
 	 * We prefer no timeout here. We can always get the status
@@ -220,7 +220,7 @@ void FLASH_DMA_CODE dma_flash_cmd_read_status(enum flash_status_mask mask,
 
 void FLASH_DMA_CODE dma_flash_cmd_write_enable(void)
 {
-	uint8_t cmd_we[] = {FLASH_CMD_WREN};
+	uint8_t cmd_we[] = { FLASH_CMD_WREN };
 
 	/* enter EC-indirect follow mode */
 	dma_flash_follow_mode();
@@ -234,7 +234,7 @@ void FLASH_DMA_CODE dma_flash_cmd_write_enable(void)
 
 void FLASH_DMA_CODE dma_flash_cmd_write_disable(void)
 {
-	uint8_t cmd_wd[] = {FLASH_CMD_WRDI};
+	uint8_t cmd_wd[] = { FLASH_CMD_WRDI };
 
 	/* enter EC-indirect follow mode */
 	dma_flash_follow_mode();
@@ -248,8 +248,8 @@ void FLASH_DMA_CODE dma_flash_cmd_write_disable(void)
 
 void FLASH_DMA_CODE dma_flash_cmd_erase(int addr, int cmd)
 {
-	uint8_t cmd_erase[] = {cmd, ((addr >> 16) & 0xFF),
-				((addr >> 8) & 0xFF), (addr & 0xFF)};
+	uint8_t cmd_erase[] = { cmd, ((addr >> 16) & 0xFF),
+				((addr >> 8) & 0xFF), (addr & 0xFF) };
 
 	/* enter EC-indirect follow mode */
 	dma_flash_follow_mode();
@@ -264,8 +264,8 @@ void FLASH_DMA_CODE dma_flash_cmd_erase(int addr, int cmd)
 void FLASH_DMA_CODE dma_flash_cmd_write(int addr, int wlen, uint8_t *wbuf)
 {
 	int i;
-	uint8_t flash_write[] = {FLASH_CMD_WRITE, ((addr >> 16) & 0xFF),
-				((addr >> 8) & 0xFF), (addr & 0xFF)};
+	uint8_t flash_write[] = { FLASH_CMD_WRITE, ((addr >> 16) & 0xFF),
+				  ((addr >> 8) & 0xFF), (addr & 0xFF) };
 
 	/* enter EC-indirect follow mode */
 	dma_flash_follow_mode();
@@ -281,12 +281,12 @@ void FLASH_DMA_CODE dma_flash_cmd_write(int addr, int wlen, uint8_t *wbuf)
 		 * chunk worth of data.
 		 */
 		if (!(++addr % CONFIG_FLASH_WRITE_IDEAL_SIZE)) {
-			uint8_t w_en[] = {FLASH_CMD_WREN};
+			uint8_t w_en[] = { FLASH_CMD_WREN };
 
 			dma_flash_fsce_high();
 			/* make sure busy bit cleared. */
 			dma_flash_cmd_read_status(FLASH_SR_BUSY,
-							FLASH_SR_NO_BUSY);
+						  FLASH_SR_NO_BUSY);
 			/* send write enable command */
 			dma_flash_transaction(sizeof(w_en), w_en, 0, NULL, 1);
 			/* make sure busy bit cleared and write enabled. */
@@ -296,7 +296,7 @@ void FLASH_DMA_CODE dma_flash_cmd_write(int addr, int wlen, uint8_t *wbuf)
 			flash_write[2] = (addr >> 8) & 0xff;
 			flash_write[3] = addr & 0xff;
 			dma_flash_transaction(sizeof(flash_write), flash_write,
-				0, NULL, 0);
+					      0, NULL, 0);
 		}
 	}
 	dma_flash_fsce_high();
@@ -340,7 +340,7 @@ int FLASH_DMA_CODE dma_flash_verify(int addr, int size, const char *data)
 			if (flash[i] != 0xFF)
 				return EC_ERROR_UNKNOWN;
 		}
-	/* verify for write */
+		/* verify for write */
 	} else {
 		for (i = 0; i < size; i++) {
 			if (flash[i] != wbuf[i])
@@ -395,8 +395,7 @@ static enum flash_wp_status flash_check_wp(void)
  * @param start_bank    Start bank to protect
  * @param bank_count    Number of banks to protect
  */
-static void flash_protect_banks(int start_bank,
-				int bank_count,
+static void flash_protect_banks(int start_bank, int bank_count,
 				enum flash_wp_interface wp_if)
 {
 	int bank;
@@ -507,13 +506,12 @@ int FLASH_DMA_CODE crec_flash_physical_erase(int offset, int size)
 		 */
 		if (IS_ENABLED(IT83XX_CHIP_FLASH_IS_KGD) && (size > 0x10000))
 			watchdog_reload();
-		/*
-		 * EC still need to handle AP's EC_CMD_GET_COMMS_STATUS command
-		 * during erasing.
-		 */
+			/*
+			 * EC still need to handle AP's EC_CMD_GET_COMMS_STATUS
+			 * command during erasing.
+			 */
 #ifdef IT83XX_IRQ_SPI_PERIPHERAL
-		if (IS_ENABLED(CONFIG_SPI) &&
-		    IS_ENABLED(HAS_TASK_HOSTCMD) &&
+		if (IS_ENABLED(CONFIG_SPI) && IS_ENABLED(HAS_TASK_HOSTCMD) &&
 		    IS_ENABLED(CONFIG_HOST_COMMAND_STATUS)) {
 			if (IT83XX_SPI_RX_VLISR & IT83XX_SPI_RVLI)
 				task_trigger_irq(IT83XX_IRQ_SPI_PERIPHERAL);
@@ -555,17 +553,16 @@ int crec_flash_physical_protect_now(int all)
 {
 	if (all) {
 		/* Protect the entire flash */
-		flash_protect_banks(0,
-			CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE,
+		flash_protect_banks(
+			0, CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE,
 			FLASH_WP_EC);
 		all_protected = 1;
 	} else {
 		/* Protect the read-only section and persistent state */
-		flash_protect_banks(WP_BANK_OFFSET,
-			WP_BANK_COUNT, FLASH_WP_EC);
+		flash_protect_banks(WP_BANK_OFFSET, WP_BANK_COUNT, FLASH_WP_EC);
 #ifdef PSTATE_BANK
-		flash_protect_banks(PSTATE_BANK,
-			PSTATE_BANK_COUNT, FLASH_WP_EC);
+		flash_protect_banks(PSTATE_BANK, PSTATE_BANK_COUNT,
+				    FLASH_WP_EC);
 #endif
 	}
 
@@ -612,8 +609,7 @@ uint32_t crec_flash_physical_get_protect_flags(void)
  */
 uint32_t crec_flash_physical_get_valid_flags(void)
 {
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-	       EC_FLASH_PROTECT_RO_NOW |
+	return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW |
 	       EC_FLASH_PROTECT_ALL_NOW;
 }
 
@@ -652,9 +648,8 @@ static void flash_enable_second_ilm(void)
 	IT83XX_GCTRL_RVILMCR0 &= ~ILMCR_ILM0_ENABLE;
 	IT83XX_SMFI_SCAR0H = BIT(3);
 	/* copy code to ram */
-	memcpy((void *)CHIP_RAMCODE_ILM0,
-		(const void *)FLASH_ILM0_ADDR,
-		IT83XX_ILM_BLOCK_SIZE);
+	memcpy((void *)CHIP_RAMCODE_ILM0, (const void *)FLASH_ILM0_ADDR,
+	       IT83XX_ILM_BLOCK_SIZE);
 	/*
 	 * Set the logic memory address(flash code of RO/RW) in flash
 	 * by programming the register SCAR0x bit19-bit0.
@@ -675,7 +670,6 @@ static void flash_enable_second_ilm(void)
 
 static void flash_code_static_dma(void)
 {
-
 	/* Make sure no interrupt while enable static DMA */
 	interrupt_disable();
 
@@ -688,7 +682,7 @@ static void flash_code_static_dma(void)
 	if (IS_ENABLED(CHIP_CORE_NDS32))
 		IT83XX_GCTRL_MCCR2 |= IT83XX_DLM14_ENABLE;
 	memcpy((void *)CHIP_RAMCODE_BASE, (const void *)FLASH_DMA_START,
-		IT83XX_ILM_BLOCK_SIZE);
+	       IT83XX_ILM_BLOCK_SIZE);
 	if (IS_ENABLED(CHIP_CORE_RISCV))
 		IT83XX_GCTRL_RVILMCR0 |= ILMCR_ILM2_ENABLE;
 	/* Disable DLM 56k~60k region and be the ram code section */
@@ -745,7 +739,7 @@ int crec_flash_pre_init(void)
 	reset_flags = system_get_reset_flags();
 	prot_flags = crec_flash_get_protect();
 	unwanted_prot_flags = EC_FLASH_PROTECT_ALL_NOW |
-		EC_FLASH_PROTECT_ERROR_INCONSISTENT;
+			      EC_FLASH_PROTECT_ERROR_INCONSISTENT;
 
 	/*
 	 * If we have already jumped between images, an earlier image could
@@ -756,12 +750,12 @@ int crec_flash_pre_init(void)
 
 	if (prot_flags & EC_FLASH_PROTECT_GPIO_ASSERTED) {
 		/* Protect the entire flash of host interface */
-		flash_protect_banks(0,
-			CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE,
+		flash_protect_banks(
+			0, CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE,
 			FLASH_WP_HOST);
 		/* Protect the entire flash of DBGR interface */
-		flash_protect_banks(0,
-			CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE,
+		flash_protect_banks(
+			0, CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE,
 			FLASH_WP_DBGR);
 		/*
 		 * Write protect is asserted.  If we want RO flash protected,
@@ -769,8 +763,9 @@ int crec_flash_pre_init(void)
 		 */
 		if ((prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT) &&
 		    !(prot_flags & EC_FLASH_PROTECT_RO_NOW)) {
-			int rv = crec_flash_set_protect(EC_FLASH_PROTECT_RO_NOW,
-						   EC_FLASH_PROTECT_RO_NOW);
+			int rv =
+				crec_flash_set_protect(EC_FLASH_PROTECT_RO_NOW,
+						       EC_FLASH_PROTECT_RO_NOW);
 			if (rv)
 				return rv;
 
diff --git a/chip/it83xx/flash_chip.h b/chip/it83xx/flash_chip.h
index c1262da116..c1cb44bdf2 100644
--- a/chip/it83xx/flash_chip.h
+++ b/chip/it83xx/flash_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/it83xx/gpio.c b/chip/it83xx/gpio.c
index bace7eb663..2b1b8283be 100644
--- a/chip/it83xx/gpio.c
+++ b/chip/it83xx/gpio.c
@@ -1,10 +1,11 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* GPIO module for Chrome EC */
 
+#include "builtin/assert.h"
 #include "clock.h"
 #include "common.h"
 #include "gpio.h"
@@ -29,11 +30,11 @@ struct kbs_gpio_ctrl_t {
 
 static const struct kbs_gpio_ctrl_t kbs_gpio_ctrl_regs[] = {
 	/* KSI pins 7:0 */
-	{&IT83XX_KBS_KSIGCTRL, &IT83XX_KBS_KSIGOEN},
+	{ &IT83XX_KBS_KSIGCTRL, &IT83XX_KBS_KSIGOEN },
 	/* KSO pins 15:8 */
-	{&IT83XX_KBS_KSOHGCTRL, &IT83XX_KBS_KSOHGOEN},
+	{ &IT83XX_KBS_KSOHGCTRL, &IT83XX_KBS_KSOHGOEN },
 	/* KSO pins 7:0 */
-	{&IT83XX_KBS_KSOLGCTRL, &IT83XX_KBS_KSOLGOEN},
+	{ &IT83XX_KBS_KSOLGCTRL, &IT83XX_KBS_KSOLGOEN },
 };
 
 /**
@@ -51,8 +52,8 @@ static volatile uint8_t *wuesr(uint8_t grp)
 	 * the address increases by fours.
 	 */
 	return (grp <= 4) ?
-			(volatile uint8_t *)(IT83XX_WUC_WUESR1 + grp-1) :
-			(volatile uint8_t *)(IT83XX_WUC_WUESR5 + 4*(grp-5));
+		       (volatile uint8_t *)(IT83XX_WUC_WUESR1 + grp - 1) :
+		       (volatile uint8_t *)(IT83XX_WUC_WUESR5 + 4 * (grp - 5));
 }
 
 /**
@@ -70,8 +71,8 @@ static volatile uint8_t *wuemr(uint8_t grp)
 	 * the address increases by fours.
 	 */
 	return (grp <= 4) ?
-			(volatile uint8_t *)(IT83XX_WUC_WUEMR1 + grp-1) :
-			(volatile uint8_t *)(IT83XX_WUC_WUEMR5 + 4*(grp-5));
+		       (volatile uint8_t *)(IT83XX_WUC_WUEMR1 + grp - 1) :
+		       (volatile uint8_t *)(IT83XX_WUC_WUEMR5 + 4 * (grp - 5));
 }
 
 /**
@@ -90,8 +91,8 @@ static volatile uint8_t *wubemr(uint8_t grp)
 	 * the address increases by fours.
 	 */
 	return (grp <= 4) ?
-			(volatile uint8_t *)(IT83XX_WUC_WUBEMR1 + grp-1) :
-			(volatile uint8_t *)(IT83XX_WUC_WUBEMR5 + 4*(grp-5));
+		       (volatile uint8_t *)(IT83XX_WUC_WUBEMR1 + grp - 1) :
+		       (volatile uint8_t *)(IT83XX_WUC_WUBEMR5 + 4 * (grp - 5));
 }
 #endif
 
@@ -112,140 +113,140 @@ static const struct {
 	uint8_t wuc_mask;
 } gpio_irqs[] = {
 	/*     irq           gpio_port,gpio_mask,wuc_group,wuc_mask */
-	[IT83XX_IRQ_WKO20] =    {GPIO_D, BIT(0),        2, BIT(0)},
-	[IT83XX_IRQ_WKO21] =    {GPIO_D, BIT(1),        2, BIT(1)},
-	[IT83XX_IRQ_WKO22] =    {GPIO_C, BIT(4),        2, BIT(2)},
-	[IT83XX_IRQ_WKO23] =    {GPIO_C, BIT(6),        2, BIT(3)},
-	[IT83XX_IRQ_WKO24] =    {GPIO_D, BIT(2),        2, BIT(4)},
+	[IT83XX_IRQ_WKO20] = { GPIO_D, BIT(0), 2, BIT(0) },
+	[IT83XX_IRQ_WKO21] = { GPIO_D, BIT(1), 2, BIT(1) },
+	[IT83XX_IRQ_WKO22] = { GPIO_C, BIT(4), 2, BIT(2) },
+	[IT83XX_IRQ_WKO23] = { GPIO_C, BIT(6), 2, BIT(3) },
+	[IT83XX_IRQ_WKO24] = { GPIO_D, BIT(2), 2, BIT(4) },
 #ifdef IT83XX_GPIO_INT_FLEXIBLE
-	[IT83XX_IRQ_WKO40] =    {GPIO_E, BIT(5),        4, BIT(0)},
-	[IT83XX_IRQ_WKO45] =    {GPIO_E, BIT(6),        4, BIT(5)},
-	[IT83XX_IRQ_WKO46] =    {GPIO_E, BIT(7),        4, BIT(6)},
+	[IT83XX_IRQ_WKO40] = { GPIO_E, BIT(5), 4, BIT(0) },
+	[IT83XX_IRQ_WKO45] = { GPIO_E, BIT(6), 4, BIT(5) },
+	[IT83XX_IRQ_WKO46] = { GPIO_E, BIT(7), 4, BIT(6) },
 #endif
-	[IT83XX_IRQ_WKO50] =    {GPIO_K, BIT(0),        5, BIT(0)},
-	[IT83XX_IRQ_WKO51] =    {GPIO_K, BIT(1),        5, BIT(1)},
-	[IT83XX_IRQ_WKO52] =    {GPIO_K, BIT(2),        5, BIT(2)},
-	[IT83XX_IRQ_WKO53] =    {GPIO_K, BIT(3),        5, BIT(3)},
-	[IT83XX_IRQ_WKO54] =    {GPIO_K, BIT(4),        5, BIT(4)},
-	[IT83XX_IRQ_WKO55] =    {GPIO_K, BIT(5),        5, BIT(5)},
-	[IT83XX_IRQ_WKO56] =    {GPIO_K, BIT(6),        5, BIT(6)},
-	[IT83XX_IRQ_WKO57] =    {GPIO_K, BIT(7),        5, BIT(7)},
-	[IT83XX_IRQ_WKO60] =    {GPIO_H, BIT(0),        6, BIT(0)},
-	[IT83XX_IRQ_WKO61] =    {GPIO_H, BIT(1),        6, BIT(1)},
-	[IT83XX_IRQ_WKO62] =    {GPIO_H, BIT(2),        6, BIT(2)},
-	[IT83XX_IRQ_WKO63] =    {GPIO_H, BIT(3),        6, BIT(3)},
-	[IT83XX_IRQ_WKO64] =    {GPIO_F, BIT(4),        6, BIT(4)},
-	[IT83XX_IRQ_WKO65] =    {GPIO_F, BIT(5),        6, BIT(5)},
-	[IT83XX_IRQ_WKO65] =    {GPIO_F, BIT(6),        6, BIT(6)},
-	[IT83XX_IRQ_WKO67] =    {GPIO_F, BIT(7),        6, BIT(7)},
-	[IT83XX_IRQ_WKO70] =    {GPIO_E, BIT(0),        7, BIT(0)},
-	[IT83XX_IRQ_WKO71] =    {GPIO_E, BIT(1),        7, BIT(1)},
-	[IT83XX_IRQ_WKO72] =    {GPIO_E, BIT(2),        7, BIT(2)},
-	[IT83XX_IRQ_WKO73] =    {GPIO_E, BIT(3),        7, BIT(3)},
-	[IT83XX_IRQ_WKO74] =    {GPIO_I, BIT(4),        7, BIT(4)},
-	[IT83XX_IRQ_WKO75] =    {GPIO_I, BIT(5),        7, BIT(5)},
-	[IT83XX_IRQ_WKO76] =    {GPIO_I, BIT(6),        7, BIT(6)},
-	[IT83XX_IRQ_WKO77] =    {GPIO_I, BIT(7),        7, BIT(7)},
-	[IT83XX_IRQ_WKO80] =    {GPIO_A, BIT(3),        8, BIT(0)},
-	[IT83XX_IRQ_WKO81] =    {GPIO_A, BIT(4),        8, BIT(1)},
-	[IT83XX_IRQ_WKO82] =    {GPIO_A, BIT(5),        8, BIT(2)},
-	[IT83XX_IRQ_WKO83] =    {GPIO_A, BIT(6),        8, BIT(3)},
-	[IT83XX_IRQ_WKO84] =    {GPIO_B, BIT(2),        8, BIT(4)},
-	[IT83XX_IRQ_WKO85] =    {GPIO_C, BIT(0),        8, BIT(5)},
-	[IT83XX_IRQ_WKO86] =    {GPIO_C, BIT(7),        8, BIT(6)},
-	[IT83XX_IRQ_WKO87] =    {GPIO_D, BIT(7),        8, BIT(7)},
-	[IT83XX_IRQ_WKO88] =    {GPIO_H, BIT(4),        9, BIT(0)},
-	[IT83XX_IRQ_WKO89] =    {GPIO_H, BIT(5),        9, BIT(1)},
-	[IT83XX_IRQ_WKO90] =    {GPIO_H, BIT(6),        9, BIT(2)},
-	[IT83XX_IRQ_WKO91] =    {GPIO_A, BIT(0),        9, BIT(3)},
-	[IT83XX_IRQ_WKO92] =    {GPIO_A, BIT(1),        9, BIT(4)},
-	[IT83XX_IRQ_WKO93] =    {GPIO_A, BIT(2),        9, BIT(5)},
-	[IT83XX_IRQ_WKO94] =    {GPIO_B, BIT(4),        9, BIT(6)},
-	[IT83XX_IRQ_WKO95] =    {GPIO_C, BIT(2),        9, BIT(7)},
-	[IT83XX_IRQ_WKO96] =    {GPIO_F, BIT(0),        10, BIT(0)},
-	[IT83XX_IRQ_WKO97] =    {GPIO_F, BIT(1),        10, BIT(1)},
-	[IT83XX_IRQ_WKO98] =    {GPIO_F, BIT(2),        10, BIT(2)},
-	[IT83XX_IRQ_WKO99] =    {GPIO_F, BIT(3),        10, BIT(3)},
-	[IT83XX_IRQ_WKO100] =   {GPIO_A, BIT(7),        10, BIT(4)},
-	[IT83XX_IRQ_WKO101] =   {GPIO_B, BIT(0),        10, BIT(5)},
-	[IT83XX_IRQ_WKO102] =   {GPIO_B, BIT(1),        10, BIT(6)},
-	[IT83XX_IRQ_WKO103] =   {GPIO_B, BIT(3),        10, BIT(7)},
-	[IT83XX_IRQ_WKO104] =   {GPIO_B, BIT(5),        11, BIT(0)},
-	[IT83XX_IRQ_WKO105] =   {GPIO_B, BIT(6),        11, BIT(1)},
-	[IT83XX_IRQ_WKO106] =   {GPIO_B, BIT(7),        11, BIT(2)},
-	[IT83XX_IRQ_WKO107] =   {GPIO_C, BIT(1),        11, BIT(3)},
-	[IT83XX_IRQ_WKO108] =   {GPIO_C, BIT(3),        11, BIT(4)},
-	[IT83XX_IRQ_WKO109] =   {GPIO_C, BIT(5),        11, BIT(5)},
-	[IT83XX_IRQ_WKO110] =   {GPIO_D, BIT(3),        11, BIT(6)},
-	[IT83XX_IRQ_WKO111] =   {GPIO_D, BIT(4),        11, BIT(7)},
-	[IT83XX_IRQ_WKO112] =   {GPIO_D, BIT(5),        12, BIT(0)},
-	[IT83XX_IRQ_WKO113] =   {GPIO_D, BIT(6),        12, BIT(1)},
-	[IT83XX_IRQ_WKO114] =   {GPIO_E, BIT(4),        12, BIT(2)},
-	[IT83XX_IRQ_WKO115] =   {GPIO_G, BIT(0),        12, BIT(3)},
-	[IT83XX_IRQ_WKO116] =   {GPIO_G, BIT(1),        12, BIT(4)},
-	[IT83XX_IRQ_WKO117] =   {GPIO_G, BIT(2),        12, BIT(5)},
-	[IT83XX_IRQ_WKO118] =   {GPIO_G, BIT(6),        12, BIT(6)},
-	[IT83XX_IRQ_WKO119] =   {GPIO_I, BIT(0),        12, BIT(7)},
-	[IT83XX_IRQ_WKO120] =   {GPIO_I, BIT(1),        13, BIT(0)},
-	[IT83XX_IRQ_WKO121] =   {GPIO_I, BIT(2),        13, BIT(1)},
-	[IT83XX_IRQ_WKO122] =   {GPIO_I, BIT(3),        13, BIT(2)},
+	[IT83XX_IRQ_WKO50] = { GPIO_K, BIT(0), 5, BIT(0) },
+	[IT83XX_IRQ_WKO51] = { GPIO_K, BIT(1), 5, BIT(1) },
+	[IT83XX_IRQ_WKO52] = { GPIO_K, BIT(2), 5, BIT(2) },
+	[IT83XX_IRQ_WKO53] = { GPIO_K, BIT(3), 5, BIT(3) },
+	[IT83XX_IRQ_WKO54] = { GPIO_K, BIT(4), 5, BIT(4) },
+	[IT83XX_IRQ_WKO55] = { GPIO_K, BIT(5), 5, BIT(5) },
+	[IT83XX_IRQ_WKO56] = { GPIO_K, BIT(6), 5, BIT(6) },
+	[IT83XX_IRQ_WKO57] = { GPIO_K, BIT(7), 5, BIT(7) },
+	[IT83XX_IRQ_WKO60] = { GPIO_H, BIT(0), 6, BIT(0) },
+	[IT83XX_IRQ_WKO61] = { GPIO_H, BIT(1), 6, BIT(1) },
+	[IT83XX_IRQ_WKO62] = { GPIO_H, BIT(2), 6, BIT(2) },
+	[IT83XX_IRQ_WKO63] = { GPIO_H, BIT(3), 6, BIT(3) },
+	[IT83XX_IRQ_WKO64] = { GPIO_F, BIT(4), 6, BIT(4) },
+	[IT83XX_IRQ_WKO65] = { GPIO_F, BIT(5), 6, BIT(5) },
+	[IT83XX_IRQ_WKO65] = { GPIO_F, BIT(6), 6, BIT(6) },
+	[IT83XX_IRQ_WKO67] = { GPIO_F, BIT(7), 6, BIT(7) },
+	[IT83XX_IRQ_WKO70] = { GPIO_E, BIT(0), 7, BIT(0) },
+	[IT83XX_IRQ_WKO71] = { GPIO_E, BIT(1), 7, BIT(1) },
+	[IT83XX_IRQ_WKO72] = { GPIO_E, BIT(2), 7, BIT(2) },
+	[IT83XX_IRQ_WKO73] = { GPIO_E, BIT(3), 7, BIT(3) },
+	[IT83XX_IRQ_WKO74] = { GPIO_I, BIT(4), 7, BIT(4) },
+	[IT83XX_IRQ_WKO75] = { GPIO_I, BIT(5), 7, BIT(5) },
+	[IT83XX_IRQ_WKO76] = { GPIO_I, BIT(6), 7, BIT(6) },
+	[IT83XX_IRQ_WKO77] = { GPIO_I, BIT(7), 7, BIT(7) },
+	[IT83XX_IRQ_WKO80] = { GPIO_A, BIT(3), 8, BIT(0) },
+	[IT83XX_IRQ_WKO81] = { GPIO_A, BIT(4), 8, BIT(1) },
+	[IT83XX_IRQ_WKO82] = { GPIO_A, BIT(5), 8, BIT(2) },
+	[IT83XX_IRQ_WKO83] = { GPIO_A, BIT(6), 8, BIT(3) },
+	[IT83XX_IRQ_WKO84] = { GPIO_B, BIT(2), 8, BIT(4) },
+	[IT83XX_IRQ_WKO85] = { GPIO_C, BIT(0), 8, BIT(5) },
+	[IT83XX_IRQ_WKO86] = { GPIO_C, BIT(7), 8, BIT(6) },
+	[IT83XX_IRQ_WKO87] = { GPIO_D, BIT(7), 8, BIT(7) },
+	[IT83XX_IRQ_WKO88] = { GPIO_H, BIT(4), 9, BIT(0) },
+	[IT83XX_IRQ_WKO89] = { GPIO_H, BIT(5), 9, BIT(1) },
+	[IT83XX_IRQ_WKO90] = { GPIO_H, BIT(6), 9, BIT(2) },
+	[IT83XX_IRQ_WKO91] = { GPIO_A, BIT(0), 9, BIT(3) },
+	[IT83XX_IRQ_WKO92] = { GPIO_A, BIT(1), 9, BIT(4) },
+	[IT83XX_IRQ_WKO93] = { GPIO_A, BIT(2), 9, BIT(5) },
+	[IT83XX_IRQ_WKO94] = { GPIO_B, BIT(4), 9, BIT(6) },
+	[IT83XX_IRQ_WKO95] = { GPIO_C, BIT(2), 9, BIT(7) },
+	[IT83XX_IRQ_WKO96] = { GPIO_F, BIT(0), 10, BIT(0) },
+	[IT83XX_IRQ_WKO97] = { GPIO_F, BIT(1), 10, BIT(1) },
+	[IT83XX_IRQ_WKO98] = { GPIO_F, BIT(2), 10, BIT(2) },
+	[IT83XX_IRQ_WKO99] = { GPIO_F, BIT(3), 10, BIT(3) },
+	[IT83XX_IRQ_WKO100] = { GPIO_A, BIT(7), 10, BIT(4) },
+	[IT83XX_IRQ_WKO101] = { GPIO_B, BIT(0), 10, BIT(5) },
+	[IT83XX_IRQ_WKO102] = { GPIO_B, BIT(1), 10, BIT(6) },
+	[IT83XX_IRQ_WKO103] = { GPIO_B, BIT(3), 10, BIT(7) },
+	[IT83XX_IRQ_WKO104] = { GPIO_B, BIT(5), 11, BIT(0) },
+	[IT83XX_IRQ_WKO105] = { GPIO_B, BIT(6), 11, BIT(1) },
+	[IT83XX_IRQ_WKO106] = { GPIO_B, BIT(7), 11, BIT(2) },
+	[IT83XX_IRQ_WKO107] = { GPIO_C, BIT(1), 11, BIT(3) },
+	[IT83XX_IRQ_WKO108] = { GPIO_C, BIT(3), 11, BIT(4) },
+	[IT83XX_IRQ_WKO109] = { GPIO_C, BIT(5), 11, BIT(5) },
+	[IT83XX_IRQ_WKO110] = { GPIO_D, BIT(3), 11, BIT(6) },
+	[IT83XX_IRQ_WKO111] = { GPIO_D, BIT(4), 11, BIT(7) },
+	[IT83XX_IRQ_WKO112] = { GPIO_D, BIT(5), 12, BIT(0) },
+	[IT83XX_IRQ_WKO113] = { GPIO_D, BIT(6), 12, BIT(1) },
+	[IT83XX_IRQ_WKO114] = { GPIO_E, BIT(4), 12, BIT(2) },
+	[IT83XX_IRQ_WKO115] = { GPIO_G, BIT(0), 12, BIT(3) },
+	[IT83XX_IRQ_WKO116] = { GPIO_G, BIT(1), 12, BIT(4) },
+	[IT83XX_IRQ_WKO117] = { GPIO_G, BIT(2), 12, BIT(5) },
+	[IT83XX_IRQ_WKO118] = { GPIO_G, BIT(6), 12, BIT(6) },
+	[IT83XX_IRQ_WKO119] = { GPIO_I, BIT(0), 12, BIT(7) },
+	[IT83XX_IRQ_WKO120] = { GPIO_I, BIT(1), 13, BIT(0) },
+	[IT83XX_IRQ_WKO121] = { GPIO_I, BIT(2), 13, BIT(1) },
+	[IT83XX_IRQ_WKO122] = { GPIO_I, BIT(3), 13, BIT(2) },
 #ifdef IT83XX_GPIO_INT_FLEXIBLE
-	[IT83XX_IRQ_WKO123] =   {GPIO_G, BIT(3),        13, BIT(3)},
-	[IT83XX_IRQ_WKO124] =   {GPIO_G, BIT(4),        13, BIT(4)},
-	[IT83XX_IRQ_WKO125] =   {GPIO_G, BIT(5),        13, BIT(5)},
-	[IT83XX_IRQ_WKO126] =   {GPIO_G, BIT(7),        13, BIT(6)},
+	[IT83XX_IRQ_WKO123] = { GPIO_G, BIT(3), 13, BIT(3) },
+	[IT83XX_IRQ_WKO124] = { GPIO_G, BIT(4), 13, BIT(4) },
+	[IT83XX_IRQ_WKO125] = { GPIO_G, BIT(5), 13, BIT(5) },
+	[IT83XX_IRQ_WKO126] = { GPIO_G, BIT(7), 13, BIT(6) },
 #endif
-	[IT83XX_IRQ_WKO128] =   {GPIO_J, BIT(0),        14, BIT(0)},
-	[IT83XX_IRQ_WKO129] =   {GPIO_J, BIT(1),        14, BIT(1)},
-	[IT83XX_IRQ_WKO130] =   {GPIO_J, BIT(2),        14, BIT(2)},
-	[IT83XX_IRQ_WKO131] =   {GPIO_J, BIT(3),        14, BIT(3)},
-	[IT83XX_IRQ_WKO132] =   {GPIO_J, BIT(4),        14, BIT(4)},
-	[IT83XX_IRQ_WKO133] =   {GPIO_J, BIT(5),        14, BIT(5)},
-	[IT83XX_IRQ_WKO134] =   {GPIO_J, BIT(6),        14, BIT(6)},
-	[IT83XX_IRQ_WKO135] =   {GPIO_J, BIT(7),        14, BIT(7)},
-	[IT83XX_IRQ_WKO136] =   {GPIO_L, BIT(0),        15, BIT(0)},
-	[IT83XX_IRQ_WKO137] =   {GPIO_L, BIT(1),        15, BIT(1)},
-	[IT83XX_IRQ_WKO138] =   {GPIO_L, BIT(2),        15, BIT(2)},
-	[IT83XX_IRQ_WKO139] =   {GPIO_L, BIT(3),        15, BIT(3)},
-	[IT83XX_IRQ_WKO140] =   {GPIO_L, BIT(4),        15, BIT(4)},
-	[IT83XX_IRQ_WKO141] =   {GPIO_L, BIT(5),        15, BIT(5)},
-	[IT83XX_IRQ_WKO142] =   {GPIO_L, BIT(6),        15, BIT(6)},
-	[IT83XX_IRQ_WKO143] =   {GPIO_L, BIT(7),        15, BIT(7)},
+	[IT83XX_IRQ_WKO128] = { GPIO_J, BIT(0), 14, BIT(0) },
+	[IT83XX_IRQ_WKO129] = { GPIO_J, BIT(1), 14, BIT(1) },
+	[IT83XX_IRQ_WKO130] = { GPIO_J, BIT(2), 14, BIT(2) },
+	[IT83XX_IRQ_WKO131] = { GPIO_J, BIT(3), 14, BIT(3) },
+	[IT83XX_IRQ_WKO132] = { GPIO_J, BIT(4), 14, BIT(4) },
+	[IT83XX_IRQ_WKO133] = { GPIO_J, BIT(5), 14, BIT(5) },
+	[IT83XX_IRQ_WKO134] = { GPIO_J, BIT(6), 14, BIT(6) },
+	[IT83XX_IRQ_WKO135] = { GPIO_J, BIT(7), 14, BIT(7) },
+	[IT83XX_IRQ_WKO136] = { GPIO_L, BIT(0), 15, BIT(0) },
+	[IT83XX_IRQ_WKO137] = { GPIO_L, BIT(1), 15, BIT(1) },
+	[IT83XX_IRQ_WKO138] = { GPIO_L, BIT(2), 15, BIT(2) },
+	[IT83XX_IRQ_WKO139] = { GPIO_L, BIT(3), 15, BIT(3) },
+	[IT83XX_IRQ_WKO140] = { GPIO_L, BIT(4), 15, BIT(4) },
+	[IT83XX_IRQ_WKO141] = { GPIO_L, BIT(5), 15, BIT(5) },
+	[IT83XX_IRQ_WKO142] = { GPIO_L, BIT(6), 15, BIT(6) },
+	[IT83XX_IRQ_WKO143] = { GPIO_L, BIT(7), 15, BIT(7) },
 #ifdef IT83XX_GPIO_INT_FLEXIBLE
-	[IT83XX_IRQ_WKO144] =   {GPIO_M, BIT(0),        16, BIT(0)},
-	[IT83XX_IRQ_WKO145] =   {GPIO_M, BIT(1),        16, BIT(1)},
-	[IT83XX_IRQ_WKO146] =   {GPIO_M, BIT(2),        16, BIT(2)},
-	[IT83XX_IRQ_WKO147] =   {GPIO_M, BIT(3),        16, BIT(3)},
-	[IT83XX_IRQ_WKO148] =   {GPIO_M, BIT(4),        16, BIT(4)},
-	[IT83XX_IRQ_WKO149] =   {GPIO_M, BIT(5),        16, BIT(5)},
-	[IT83XX_IRQ_WKO150] =   {GPIO_M, BIT(6),        16, BIT(6)},
+	[IT83XX_IRQ_WKO144] = { GPIO_M, BIT(0), 16, BIT(0) },
+	[IT83XX_IRQ_WKO145] = { GPIO_M, BIT(1), 16, BIT(1) },
+	[IT83XX_IRQ_WKO146] = { GPIO_M, BIT(2), 16, BIT(2) },
+	[IT83XX_IRQ_WKO147] = { GPIO_M, BIT(3), 16, BIT(3) },
+	[IT83XX_IRQ_WKO148] = { GPIO_M, BIT(4), 16, BIT(4) },
+	[IT83XX_IRQ_WKO149] = { GPIO_M, BIT(5), 16, BIT(5) },
+	[IT83XX_IRQ_WKO150] = { GPIO_M, BIT(6), 16, BIT(6) },
 #endif
 #if defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2)
-	[IT83XX_IRQ_GPO0]   =   {GPIO_O, BIT(0),        19, BIT(0)},
-	[IT83XX_IRQ_GPO1]   =   {GPIO_O, BIT(1),        19, BIT(1)},
-	[IT83XX_IRQ_GPO2]   =   {GPIO_O, BIT(2),        19, BIT(2)},
-	[IT83XX_IRQ_GPO3]   =   {GPIO_O, BIT(3),        19, BIT(3)},
-	[IT83XX_IRQ_GPP0]   =   {GPIO_P, BIT(0),        20, BIT(0)},
-	[IT83XX_IRQ_GPP1]   =   {GPIO_P, BIT(1),        20, BIT(1)},
-	[IT83XX_IRQ_GPP2]   =   {GPIO_P, BIT(2),        20, BIT(2)},
-	[IT83XX_IRQ_GPP3]   =   {GPIO_P, BIT(3),        20, BIT(3)},
-	[IT83XX_IRQ_GPP4]   =   {GPIO_P, BIT(4),        20, BIT(4)},
-	[IT83XX_IRQ_GPP5]   =   {GPIO_P, BIT(5),        20, BIT(5)},
-	[IT83XX_IRQ_GPP6]   =   {GPIO_P, BIT(6),        20, BIT(6)},
-	[IT83XX_IRQ_GPQ0]   =   {GPIO_Q, BIT(0),        21, BIT(0)},
-	[IT83XX_IRQ_GPQ1]   =   {GPIO_Q, BIT(1),        21, BIT(1)},
-	[IT83XX_IRQ_GPQ2]   =   {GPIO_Q, BIT(2),        21, BIT(2)},
-	[IT83XX_IRQ_GPQ3]   =   {GPIO_Q, BIT(3),        21, BIT(3)},
-	[IT83XX_IRQ_GPQ4]   =   {GPIO_Q, BIT(4),        21, BIT(4)},
-	[IT83XX_IRQ_GPQ5]   =   {GPIO_Q, BIT(5),        21, BIT(5)},
-	[IT83XX_IRQ_GPR0]   =   {GPIO_R, BIT(0),        22, BIT(0)},
-	[IT83XX_IRQ_GPR1]   =   {GPIO_R, BIT(1),        22, BIT(1)},
-	[IT83XX_IRQ_GPR2]   =   {GPIO_R, BIT(2),        22, BIT(2)},
-	[IT83XX_IRQ_GPR3]   =   {GPIO_R, BIT(3),        22, BIT(3)},
-	[IT83XX_IRQ_GPR4]   =   {GPIO_R, BIT(4),        22, BIT(4)},
-	[IT83XX_IRQ_GPR5]   =   {GPIO_R, BIT(5),        22, BIT(5)},
+	[IT83XX_IRQ_GPO0] = { GPIO_O, BIT(0), 19, BIT(0) },
+	[IT83XX_IRQ_GPO1] = { GPIO_O, BIT(1), 19, BIT(1) },
+	[IT83XX_IRQ_GPO2] = { GPIO_O, BIT(2), 19, BIT(2) },
+	[IT83XX_IRQ_GPO3] = { GPIO_O, BIT(3), 19, BIT(3) },
+	[IT83XX_IRQ_GPP0] = { GPIO_P, BIT(0), 20, BIT(0) },
+	[IT83XX_IRQ_GPP1] = { GPIO_P, BIT(1), 20, BIT(1) },
+	[IT83XX_IRQ_GPP2] = { GPIO_P, BIT(2), 20, BIT(2) },
+	[IT83XX_IRQ_GPP3] = { GPIO_P, BIT(3), 20, BIT(3) },
+	[IT83XX_IRQ_GPP4] = { GPIO_P, BIT(4), 20, BIT(4) },
+	[IT83XX_IRQ_GPP5] = { GPIO_P, BIT(5), 20, BIT(5) },
+	[IT83XX_IRQ_GPP6] = { GPIO_P, BIT(6), 20, BIT(6) },
+	[IT83XX_IRQ_GPQ0] = { GPIO_Q, BIT(0), 21, BIT(0) },
+	[IT83XX_IRQ_GPQ1] = { GPIO_Q, BIT(1), 21, BIT(1) },
+	[IT83XX_IRQ_GPQ2] = { GPIO_Q, BIT(2), 21, BIT(2) },
+	[IT83XX_IRQ_GPQ3] = { GPIO_Q, BIT(3), 21, BIT(3) },
+	[IT83XX_IRQ_GPQ4] = { GPIO_Q, BIT(4), 21, BIT(4) },
+	[IT83XX_IRQ_GPQ5] = { GPIO_Q, BIT(5), 21, BIT(5) },
+	[IT83XX_IRQ_GPR0] = { GPIO_R, BIT(0), 22, BIT(0) },
+	[IT83XX_IRQ_GPR1] = { GPIO_R, BIT(1), 22, BIT(1) },
+	[IT83XX_IRQ_GPR2] = { GPIO_R, BIT(2), 22, BIT(2) },
+	[IT83XX_IRQ_GPR3] = { GPIO_R, BIT(3), 22, BIT(3) },
+	[IT83XX_IRQ_GPR4] = { GPIO_R, BIT(4), 22, BIT(4) },
+	[IT83XX_IRQ_GPR5] = { GPIO_R, BIT(5), 22, BIT(5) },
 #endif
-	[IT83XX_IRQ_COUNT]  =   {     0,      0,         0,      0},
+	[IT83XX_IRQ_COUNT] = { 0, 0, 0, 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(gpio_irqs) == IT83XX_IRQ_COUNT + 1);
 
@@ -263,7 +264,7 @@ static int gpio_to_irq(uint8_t port, uint8_t mask)
 
 	for (i = 0; i < IT83XX_IRQ_COUNT; i++) {
 		if (gpio_irqs[i].gpio_port == port &&
-				gpio_irqs[i].gpio_mask == mask)
+		    gpio_irqs[i].gpio_mask == mask)
 			return i;
 	}
 
@@ -277,133 +278,133 @@ struct gpio_1p8v_t {
 
 static const struct gpio_1p8v_t gpio_1p8v_sel[GPIO_PORT_COUNT][8] = {
 #ifdef IT83XX_GPIO_1P8V_PIN_EXTENDED
-	[GPIO_A] = { [4] = {&IT83XX_GPIO_GRC24, BIT(0)},
-		     [5] = {&IT83XX_GPIO_GRC24, BIT(1)},
-		     [6] = {&IT83XX_GPIO_GRC24, BIT(5)},
-		     [7] = {&IT83XX_GPIO_GRC24, BIT(6)} },
-	[GPIO_B] = { [3] = {&IT83XX_GPIO_GRC22, BIT(1)},
-		     [4] = {&IT83XX_GPIO_GRC22, BIT(0)},
-		     [5] = {&IT83XX_GPIO_GRC19, BIT(7)},
-		     [6] = {&IT83XX_GPIO_GRC19, BIT(6)},
-		     [7] = {&IT83XX_GPIO_GRC24, BIT(4)} },
-	[GPIO_C] = { [0] = {&IT83XX_GPIO_GRC22, BIT(7)},
-		     [1] = {&IT83XX_GPIO_GRC19, BIT(5)},
-		     [2] = {&IT83XX_GPIO_GRC19, BIT(4)},
-		     [4] = {&IT83XX_GPIO_GRC24, BIT(2)},
-		     [6] = {&IT83XX_GPIO_GRC24, BIT(3)},
-		     [7] = {&IT83XX_GPIO_GRC19, BIT(3)} },
-	[GPIO_D] = { [0] = {&IT83XX_GPIO_GRC19, BIT(2)},
-		     [1] = {&IT83XX_GPIO_GRC19, BIT(1)},
-		     [2] = {&IT83XX_GPIO_GRC19, BIT(0)},
-		     [3] = {&IT83XX_GPIO_GRC20, BIT(7)},
-		     [4] = {&IT83XX_GPIO_GRC20, BIT(6)},
-		     [5] = {&IT83XX_GPIO_GRC22, BIT(4)},
-		     [6] = {&IT83XX_GPIO_GRC22, BIT(5)},
-		     [7] = {&IT83XX_GPIO_GRC22, BIT(6)} },
-	[GPIO_E] = { [0] = {&IT83XX_GPIO_GRC20, BIT(5)},
-		     [1] = {&IT83XX_GPIO_GCR28, BIT(6)},
-		     [2] = {&IT83XX_GPIO_GCR28, BIT(7)},
-		     [4] = {&IT83XX_GPIO_GRC22, BIT(2)},
-		     [5] = {&IT83XX_GPIO_GRC22, BIT(3)},
-		     [6] = {&IT83XX_GPIO_GRC20, BIT(4)},
-		     [7] = {&IT83XX_GPIO_GRC20, BIT(3)} },
-	[GPIO_F] = { [0] = {&IT83XX_GPIO_GCR28, BIT(4)},
-		     [1] = {&IT83XX_GPIO_GCR28, BIT(5)},
-		     [2] = {&IT83XX_GPIO_GRC20, BIT(2)},
-		     [3] = {&IT83XX_GPIO_GRC20, BIT(1)},
-		     [4] = {&IT83XX_GPIO_GRC20, BIT(0)},
-		     [5] = {&IT83XX_GPIO_GRC21, BIT(7)},
-		     [6] = {&IT83XX_GPIO_GRC21, BIT(6)},
-		     [7] = {&IT83XX_GPIO_GRC21, BIT(5)} },
-	[GPIO_G] = { [0] = {&IT83XX_GPIO_GCR28, BIT(2)},
-		     [1] = {&IT83XX_GPIO_GRC21, BIT(4)},
-		     [2] = {&IT83XX_GPIO_GCR28, BIT(3)},
-		     [6] = {&IT83XX_GPIO_GRC21, BIT(3)} },
-	[GPIO_H] = { [0] = {&IT83XX_GPIO_GRC21, BIT(2)},
-		     [1] = {&IT83XX_GPIO_GRC21, BIT(1)},
-		     [2] = {&IT83XX_GPIO_GRC21, BIT(0)},
-		     [5] = {&IT83XX_GPIO_GCR27, BIT(7)},
-		     [6] = {&IT83XX_GPIO_GCR28, BIT(0)} },
-	[GPIO_I] = { [0] = {&IT83XX_GPIO_GCR27, BIT(3)},
-		     [1] = {&IT83XX_GPIO_GRC23, BIT(4)},
-		     [2] = {&IT83XX_GPIO_GRC23, BIT(5)},
-		     [3] = {&IT83XX_GPIO_GRC23, BIT(6)},
-		     [4] = {&IT83XX_GPIO_GRC23, BIT(7)},
-		     [5] = {&IT83XX_GPIO_GCR27, BIT(4)},
-		     [6] = {&IT83XX_GPIO_GCR27, BIT(5)},
-		     [7] = {&IT83XX_GPIO_GCR27, BIT(6)} },
-	[GPIO_J] = { [0] = {&IT83XX_GPIO_GRC23, BIT(0)},
-		     [1] = {&IT83XX_GPIO_GRC23, BIT(1)},
-		     [2] = {&IT83XX_GPIO_GRC23, BIT(2)},
-		     [3] = {&IT83XX_GPIO_GRC23, BIT(3)},
-		     [4] = {&IT83XX_GPIO_GCR27, BIT(0)},
-		     [5] = {&IT83XX_GPIO_GCR27, BIT(1)},
-		     [6] = {&IT83XX_GPIO_GCR27, BIT(2)},
-		     [7] = {&IT83XX_GPIO_GCR33, BIT(2)} },
-	[GPIO_K] = { [0] = {&IT83XX_GPIO_GCR26, BIT(0)},
-		     [1] = {&IT83XX_GPIO_GCR26, BIT(1)},
-		     [2] = {&IT83XX_GPIO_GCR26, BIT(2)},
-		     [3] = {&IT83XX_GPIO_GCR26, BIT(3)},
-		     [4] = {&IT83XX_GPIO_GCR26, BIT(4)},
-		     [5] = {&IT83XX_GPIO_GCR26, BIT(5)},
-		     [6] = {&IT83XX_GPIO_GCR26, BIT(6)},
-		     [7] = {&IT83XX_GPIO_GCR26, BIT(7)} },
-	[GPIO_L] = { [0] = {&IT83XX_GPIO_GCR25, BIT(0)},
-		     [1] = {&IT83XX_GPIO_GCR25, BIT(1)},
-		     [2] = {&IT83XX_GPIO_GCR25, BIT(2)},
-		     [3] = {&IT83XX_GPIO_GCR25, BIT(3)},
-		     [4] = {&IT83XX_GPIO_GCR25, BIT(4)},
-		     [5] = {&IT83XX_GPIO_GCR25, BIT(5)},
-		     [6] = {&IT83XX_GPIO_GCR25, BIT(6)},
-		     [7] = {&IT83XX_GPIO_GCR25, BIT(7)} },
+	[GPIO_A] = { [4] = { &IT83XX_GPIO_GRC24, BIT(0) },
+		     [5] = { &IT83XX_GPIO_GRC24, BIT(1) },
+		     [6] = { &IT83XX_GPIO_GRC24, BIT(5) },
+		     [7] = { &IT83XX_GPIO_GRC24, BIT(6) } },
+	[GPIO_B] = { [3] = { &IT83XX_GPIO_GRC22, BIT(1) },
+		     [4] = { &IT83XX_GPIO_GRC22, BIT(0) },
+		     [5] = { &IT83XX_GPIO_GRC19, BIT(7) },
+		     [6] = { &IT83XX_GPIO_GRC19, BIT(6) },
+		     [7] = { &IT83XX_GPIO_GRC24, BIT(4) } },
+	[GPIO_C] = { [0] = { &IT83XX_GPIO_GRC22, BIT(7) },
+		     [1] = { &IT83XX_GPIO_GRC19, BIT(5) },
+		     [2] = { &IT83XX_GPIO_GRC19, BIT(4) },
+		     [4] = { &IT83XX_GPIO_GRC24, BIT(2) },
+		     [6] = { &IT83XX_GPIO_GRC24, BIT(3) },
+		     [7] = { &IT83XX_GPIO_GRC19, BIT(3) } },
+	[GPIO_D] = { [0] = { &IT83XX_GPIO_GRC19, BIT(2) },
+		     [1] = { &IT83XX_GPIO_GRC19, BIT(1) },
+		     [2] = { &IT83XX_GPIO_GRC19, BIT(0) },
+		     [3] = { &IT83XX_GPIO_GRC20, BIT(7) },
+		     [4] = { &IT83XX_GPIO_GRC20, BIT(6) },
+		     [5] = { &IT83XX_GPIO_GRC22, BIT(4) },
+		     [6] = { &IT83XX_GPIO_GRC22, BIT(5) },
+		     [7] = { &IT83XX_GPIO_GRC22, BIT(6) } },
+	[GPIO_E] = { [0] = { &IT83XX_GPIO_GRC20, BIT(5) },
+		     [1] = { &IT83XX_GPIO_GCR28, BIT(6) },
+		     [2] = { &IT83XX_GPIO_GCR28, BIT(7) },
+		     [4] = { &IT83XX_GPIO_GRC22, BIT(2) },
+		     [5] = { &IT83XX_GPIO_GRC22, BIT(3) },
+		     [6] = { &IT83XX_GPIO_GRC20, BIT(4) },
+		     [7] = { &IT83XX_GPIO_GRC20, BIT(3) } },
+	[GPIO_F] = { [0] = { &IT83XX_GPIO_GCR28, BIT(4) },
+		     [1] = { &IT83XX_GPIO_GCR28, BIT(5) },
+		     [2] = { &IT83XX_GPIO_GRC20, BIT(2) },
+		     [3] = { &IT83XX_GPIO_GRC20, BIT(1) },
+		     [4] = { &IT83XX_GPIO_GRC20, BIT(0) },
+		     [5] = { &IT83XX_GPIO_GRC21, BIT(7) },
+		     [6] = { &IT83XX_GPIO_GRC21, BIT(6) },
+		     [7] = { &IT83XX_GPIO_GRC21, BIT(5) } },
+	[GPIO_G] = { [0] = { &IT83XX_GPIO_GCR28, BIT(2) },
+		     [1] = { &IT83XX_GPIO_GRC21, BIT(4) },
+		     [2] = { &IT83XX_GPIO_GCR28, BIT(3) },
+		     [6] = { &IT83XX_GPIO_GRC21, BIT(3) } },
+	[GPIO_H] = { [0] = { &IT83XX_GPIO_GRC21, BIT(2) },
+		     [1] = { &IT83XX_GPIO_GRC21, BIT(1) },
+		     [2] = { &IT83XX_GPIO_GRC21, BIT(0) },
+		     [5] = { &IT83XX_GPIO_GCR27, BIT(7) },
+		     [6] = { &IT83XX_GPIO_GCR28, BIT(0) } },
+	[GPIO_I] = { [0] = { &IT83XX_GPIO_GCR27, BIT(3) },
+		     [1] = { &IT83XX_GPIO_GRC23, BIT(4) },
+		     [2] = { &IT83XX_GPIO_GRC23, BIT(5) },
+		     [3] = { &IT83XX_GPIO_GRC23, BIT(6) },
+		     [4] = { &IT83XX_GPIO_GRC23, BIT(7) },
+		     [5] = { &IT83XX_GPIO_GCR27, BIT(4) },
+		     [6] = { &IT83XX_GPIO_GCR27, BIT(5) },
+		     [7] = { &IT83XX_GPIO_GCR27, BIT(6) } },
+	[GPIO_J] = { [0] = { &IT83XX_GPIO_GRC23, BIT(0) },
+		     [1] = { &IT83XX_GPIO_GRC23, BIT(1) },
+		     [2] = { &IT83XX_GPIO_GRC23, BIT(2) },
+		     [3] = { &IT83XX_GPIO_GRC23, BIT(3) },
+		     [4] = { &IT83XX_GPIO_GCR27, BIT(0) },
+		     [5] = { &IT83XX_GPIO_GCR27, BIT(1) },
+		     [6] = { &IT83XX_GPIO_GCR27, BIT(2) },
+		     [7] = { &IT83XX_GPIO_GCR33, BIT(2) } },
+	[GPIO_K] = { [0] = { &IT83XX_GPIO_GCR26, BIT(0) },
+		     [1] = { &IT83XX_GPIO_GCR26, BIT(1) },
+		     [2] = { &IT83XX_GPIO_GCR26, BIT(2) },
+		     [3] = { &IT83XX_GPIO_GCR26, BIT(3) },
+		     [4] = { &IT83XX_GPIO_GCR26, BIT(4) },
+		     [5] = { &IT83XX_GPIO_GCR26, BIT(5) },
+		     [6] = { &IT83XX_GPIO_GCR26, BIT(6) },
+		     [7] = { &IT83XX_GPIO_GCR26, BIT(7) } },
+	[GPIO_L] = { [0] = { &IT83XX_GPIO_GCR25, BIT(0) },
+		     [1] = { &IT83XX_GPIO_GCR25, BIT(1) },
+		     [2] = { &IT83XX_GPIO_GCR25, BIT(2) },
+		     [3] = { &IT83XX_GPIO_GCR25, BIT(3) },
+		     [4] = { &IT83XX_GPIO_GCR25, BIT(4) },
+		     [5] = { &IT83XX_GPIO_GCR25, BIT(5) },
+		     [6] = { &IT83XX_GPIO_GCR25, BIT(6) },
+		     [7] = { &IT83XX_GPIO_GCR25, BIT(7) } },
 #if defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2)
-	[GPIO_O] = { [0] = {&IT83XX_GPIO_GCR31, BIT(0)},
-		     [1] = {&IT83XX_GPIO_GCR31, BIT(1)},
-		     [2] = {&IT83XX_GPIO_GCR31, BIT(2)},
-		     [3] = {&IT83XX_GPIO_GCR31, BIT(3)} },
-	[GPIO_P] = { [0] = {&IT83XX_GPIO_GCR32, BIT(0)},
-		     [1] = {&IT83XX_GPIO_GCR32, BIT(1)},
-		     [2] = {&IT83XX_GPIO_GCR32, BIT(2)},
-		     [3] = {&IT83XX_GPIO_GCR32, BIT(3)},
-		     [4] = {&IT83XX_GPIO_GCR32, BIT(4)},
-		     [5] = {&IT83XX_GPIO_GCR32, BIT(5)},
-		     [6] = {&IT83XX_GPIO_GCR32, BIT(6)} },
+	[GPIO_O] = { [0] = { &IT83XX_GPIO_GCR31, BIT(0) },
+		     [1] = { &IT83XX_GPIO_GCR31, BIT(1) },
+		     [2] = { &IT83XX_GPIO_GCR31, BIT(2) },
+		     [3] = { &IT83XX_GPIO_GCR31, BIT(3) } },
+	[GPIO_P] = { [0] = { &IT83XX_GPIO_GCR32, BIT(0) },
+		     [1] = { &IT83XX_GPIO_GCR32, BIT(1) },
+		     [2] = { &IT83XX_GPIO_GCR32, BIT(2) },
+		     [3] = { &IT83XX_GPIO_GCR32, BIT(3) },
+		     [4] = { &IT83XX_GPIO_GCR32, BIT(4) },
+		     [5] = { &IT83XX_GPIO_GCR32, BIT(5) },
+		     [6] = { &IT83XX_GPIO_GCR32, BIT(6) } },
 #endif
 #else
-	[GPIO_A] = { [4] = {&IT83XX_GPIO_GRC24, BIT(0)},
-		     [5] = {&IT83XX_GPIO_GRC24, BIT(1)} },
-	[GPIO_B] = { [3] = {&IT83XX_GPIO_GRC22, BIT(1)},
-		     [4] = {&IT83XX_GPIO_GRC22, BIT(0)},
-		     [5] = {&IT83XX_GPIO_GRC19, BIT(7)},
-		     [6] = {&IT83XX_GPIO_GRC19, BIT(6)} },
-	[GPIO_C] = { [1] = {&IT83XX_GPIO_GRC19, BIT(5)},
-		     [2] = {&IT83XX_GPIO_GRC19, BIT(4)},
-		     [7] = {&IT83XX_GPIO_GRC19, BIT(3)} },
-	[GPIO_D] = { [0] = {&IT83XX_GPIO_GRC19, BIT(2)},
-		     [1] = {&IT83XX_GPIO_GRC19, BIT(1)},
-		     [2] = {&IT83XX_GPIO_GRC19, BIT(0)},
-		     [3] = {&IT83XX_GPIO_GRC20, BIT(7)},
-		     [4] = {&IT83XX_GPIO_GRC20, BIT(6)} },
-	[GPIO_E] = { [0] = {&IT83XX_GPIO_GRC20, BIT(5)},
-		     [6] = {&IT83XX_GPIO_GRC20, BIT(4)},
-		     [7] = {&IT83XX_GPIO_GRC20, BIT(3)} },
-	[GPIO_F] = { [2] = {&IT83XX_GPIO_GRC20, BIT(2)},
-		     [3] = {&IT83XX_GPIO_GRC20, BIT(1)},
-		     [4] = {&IT83XX_GPIO_GRC20, BIT(0)},
-		     [5] = {&IT83XX_GPIO_GRC21, BIT(7)},
-		     [6] = {&IT83XX_GPIO_GRC21, BIT(6)},
-		     [7] = {&IT83XX_GPIO_GRC21, BIT(5)} },
-	[GPIO_H] = { [0] = {&IT83XX_GPIO_GRC21, BIT(2)},
-		     [1] = {&IT83XX_GPIO_GRC21, BIT(1)},
-		     [2] = {&IT83XX_GPIO_GRC21, BIT(0)} },
-	[GPIO_I] = { [1] = {&IT83XX_GPIO_GRC23, BIT(4)},
-		     [2] = {&IT83XX_GPIO_GRC23, BIT(5)},
-		     [3] = {&IT83XX_GPIO_GRC23, BIT(6)},
-		     [4] = {&IT83XX_GPIO_GRC23, BIT(7)} },
-	[GPIO_J] = { [0] = {&IT83XX_GPIO_GRC23, BIT(0)},
-		     [1] = {&IT83XX_GPIO_GRC23, BIT(1)},
-		     [2] = {&IT83XX_GPIO_GRC23, BIT(2)},
-		     [3] = {&IT83XX_GPIO_GRC23, BIT(3)} },
+	[GPIO_A] = { [4] = { &IT83XX_GPIO_GRC24, BIT(0) },
+		     [5] = { &IT83XX_GPIO_GRC24, BIT(1) } },
+	[GPIO_B] = { [3] = { &IT83XX_GPIO_GRC22, BIT(1) },
+		     [4] = { &IT83XX_GPIO_GRC22, BIT(0) },
+		     [5] = { &IT83XX_GPIO_GRC19, BIT(7) },
+		     [6] = { &IT83XX_GPIO_GRC19, BIT(6) } },
+	[GPIO_C] = { [1] = { &IT83XX_GPIO_GRC19, BIT(5) },
+		     [2] = { &IT83XX_GPIO_GRC19, BIT(4) },
+		     [7] = { &IT83XX_GPIO_GRC19, BIT(3) } },
+	[GPIO_D] = { [0] = { &IT83XX_GPIO_GRC19, BIT(2) },
+		     [1] = { &IT83XX_GPIO_GRC19, BIT(1) },
+		     [2] = { &IT83XX_GPIO_GRC19, BIT(0) },
+		     [3] = { &IT83XX_GPIO_GRC20, BIT(7) },
+		     [4] = { &IT83XX_GPIO_GRC20, BIT(6) } },
+	[GPIO_E] = { [0] = { &IT83XX_GPIO_GRC20, BIT(5) },
+		     [6] = { &IT83XX_GPIO_GRC20, BIT(4) },
+		     [7] = { &IT83XX_GPIO_GRC20, BIT(3) } },
+	[GPIO_F] = { [2] = { &IT83XX_GPIO_GRC20, BIT(2) },
+		     [3] = { &IT83XX_GPIO_GRC20, BIT(1) },
+		     [4] = { &IT83XX_GPIO_GRC20, BIT(0) },
+		     [5] = { &IT83XX_GPIO_GRC21, BIT(7) },
+		     [6] = { &IT83XX_GPIO_GRC21, BIT(6) },
+		     [7] = { &IT83XX_GPIO_GRC21, BIT(5) } },
+	[GPIO_H] = { [0] = { &IT83XX_GPIO_GRC21, BIT(2) },
+		     [1] = { &IT83XX_GPIO_GRC21, BIT(1) },
+		     [2] = { &IT83XX_GPIO_GRC21, BIT(0) } },
+	[GPIO_I] = { [1] = { &IT83XX_GPIO_GRC23, BIT(4) },
+		     [2] = { &IT83XX_GPIO_GRC23, BIT(5) },
+		     [3] = { &IT83XX_GPIO_GRC23, BIT(6) },
+		     [4] = { &IT83XX_GPIO_GRC23, BIT(7) } },
+	[GPIO_J] = { [0] = { &IT83XX_GPIO_GRC23, BIT(0) },
+		     [1] = { &IT83XX_GPIO_GRC23, BIT(1) },
+		     [2] = { &IT83XX_GPIO_GRC23, BIT(2) },
+		     [3] = { &IT83XX_GPIO_GRC23, BIT(3) } },
 #endif
 };
 
@@ -422,23 +423,23 @@ static void gpio_1p8v_3p3v_sel_by_pin(uint8_t port, uint8_t pin, int sel_1p8v)
 }
 
 static inline void it83xx_set_alt_func(uint32_t port, uint32_t pin,
-				enum gpio_alternate_func func)
+				       enum gpio_alternate_func func)
 {
 	/*
 	 * If func is not ALT_FUNC_NONE, set for alternate function.
 	 * Otherwise, turn the pin into an input as it's default.
 	 */
 	if (func != GPIO_ALT_FUNC_NONE)
-		IT83XX_GPIO_CTRL(port, pin) &= ~(GPCR_PORT_PIN_MODE_OUTPUT |
-			GPCR_PORT_PIN_MODE_INPUT);
+		IT83XX_GPIO_CTRL(port, pin) &=
+			~(GPCR_PORT_PIN_MODE_OUTPUT | GPCR_PORT_PIN_MODE_INPUT);
 	else
-		IT83XX_GPIO_CTRL(port, pin) =
-			(IT83XX_GPIO_CTRL(port, pin) | GPCR_PORT_PIN_MODE_INPUT)
-			& ~GPCR_PORT_PIN_MODE_OUTPUT;
+		IT83XX_GPIO_CTRL(port, pin) = (IT83XX_GPIO_CTRL(port, pin) |
+					       GPCR_PORT_PIN_MODE_INPUT) &
+					      ~GPCR_PORT_PIN_MODE_OUTPUT;
 }
 
 void gpio_set_alternate_function(uint32_t port, uint32_t mask,
-				enum gpio_alternate_func func)
+				 enum gpio_alternate_func func)
 {
 	uint32_t pin = 0;
 
@@ -473,7 +474,9 @@ void gpio_set_alternate_function(uint32_t port, uint32_t mask,
 test_mockable int gpio_get_level(enum gpio_signal signal)
 {
 	return (IT83XX_GPIO_DATA_MIRROR(gpio_list[signal].port) &
-			gpio_list[signal].mask) ? 1 : 0;
+		gpio_list[signal].mask) ?
+		       1 :
+		       0;
 }
 
 void gpio_set_level(enum gpio_signal signal, int value)
@@ -483,10 +486,10 @@ void gpio_set_level(enum gpio_signal signal, int value)
 
 	if (value)
 		IT83XX_GPIO_DATA(gpio_list[signal].port) |=
-				 gpio_list[signal].mask;
+			gpio_list[signal].mask;
 	else
 		IT83XX_GPIO_DATA(gpio_list[signal].port) &=
-				~gpio_list[signal].mask;
+			~gpio_list[signal].mask;
 	/* restore interrupts */
 	set_int_mask(int_mask);
 }
@@ -591,26 +594,26 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
 			/* Set input or output. */
 			if (flags & GPIO_OUTPUT)
 				IT83XX_GPIO_CTRL(port, pin) =
-				(IT83XX_GPIO_CTRL(port, pin) |
-				 GPCR_PORT_PIN_MODE_OUTPUT) &
-				~GPCR_PORT_PIN_MODE_INPUT;
+					(IT83XX_GPIO_CTRL(port, pin) |
+					 GPCR_PORT_PIN_MODE_OUTPUT) &
+					~GPCR_PORT_PIN_MODE_INPUT;
 			else
 				IT83XX_GPIO_CTRL(port, pin) =
-				(IT83XX_GPIO_CTRL(port, pin) |
-				 GPCR_PORT_PIN_MODE_INPUT) &
-				~GPCR_PORT_PIN_MODE_OUTPUT;
+					(IT83XX_GPIO_CTRL(port, pin) |
+					 GPCR_PORT_PIN_MODE_INPUT) &
+					~GPCR_PORT_PIN_MODE_OUTPUT;
 
 			/* Handle pullup / pulldown */
 			if (flags & GPIO_PULL_UP) {
 				IT83XX_GPIO_CTRL(port, pin) =
-				(IT83XX_GPIO_CTRL(port, pin) |
-				 GPCR_PORT_PIN_MODE_PULLUP) &
-				~GPCR_PORT_PIN_MODE_PULLDOWN;
+					(IT83XX_GPIO_CTRL(port, pin) |
+					 GPCR_PORT_PIN_MODE_PULLUP) &
+					~GPCR_PORT_PIN_MODE_PULLDOWN;
 			} else if (flags & GPIO_PULL_DOWN) {
 				IT83XX_GPIO_CTRL(port, pin) =
-				(IT83XX_GPIO_CTRL(port, pin) |
-				 GPCR_PORT_PIN_MODE_PULLDOWN) &
-				~GPCR_PORT_PIN_MODE_PULLUP;
+					(IT83XX_GPIO_CTRL(port, pin) |
+					 GPCR_PORT_PIN_MODE_PULLDOWN) &
+					~GPCR_PORT_PIN_MODE_PULLUP;
 			} else {
 				/* No pull up/down */
 				IT83XX_GPIO_CTRL(port, pin) &=
@@ -620,7 +623,7 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
 
 			/* To select 1.8v or 3.3v support. */
 			gpio_1p8v_3p3v_sel_by_pin(port, pin,
-						(flags & GPIO_SEL_1P8V));
+						  (flags & GPIO_SEL_1P8V));
 		}
 
 		pin++;
@@ -804,10 +807,12 @@ void gpio_pre_init(void)
 	 */
 	if (IS_ENABLED(IT83XX_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN)) {
 		for (i = 0; i < 8; i++) {
-			IT83XX_GPIO_CTRL(GPIO_K, i) = (GPCR_PORT_PIN_MODE_INPUT
-				| GPCR_PORT_PIN_MODE_PULLDOWN);
-			IT83XX_GPIO_CTRL(GPIO_L, i) = (GPCR_PORT_PIN_MODE_INPUT
-				| GPCR_PORT_PIN_MODE_PULLDOWN);
+			IT83XX_GPIO_CTRL(GPIO_K, i) =
+				(GPCR_PORT_PIN_MODE_INPUT |
+				 GPCR_PORT_PIN_MODE_PULLDOWN);
+			IT83XX_GPIO_CTRL(GPIO_L, i) =
+				(GPCR_PORT_PIN_MODE_INPUT |
+				 GPCR_PORT_PIN_MODE_PULLDOWN);
 		}
 	}
 
diff --git a/chip/it83xx/hwtimer.c b/chip/it83xx/hwtimer.c
index 291751a1cb..b9add82b5a 100644
--- a/chip/it83xx/hwtimer.c
+++ b/chip/it83xx/hwtimer.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -55,18 +55,18 @@
 #define MS_TO_COUNT(hz, ms) ((hz) * (ms) / 1000)
 
 const struct ext_timer_ctrl_t et_ctrl_regs[] = {
-	{&IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x08,
-		IT83XX_IRQ_EXT_TIMER3},
-	{&IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x10,
-		IT83XX_IRQ_EXT_TIMER4},
-	{&IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x20,
-		IT83XX_IRQ_EXT_TIMER5},
-	{&IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x40,
-		IT83XX_IRQ_EXT_TIMER6},
-	{&IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x80,
-		IT83XX_IRQ_EXT_TIMER7},
-	{&IT83XX_INTC_IELMR10, &IT83XX_INTC_IPOLR10, &IT83XX_INTC_ISR10, 0x01,
-		IT83XX_IRQ_EXT_TMR8},
+	{ &IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x08,
+	  IT83XX_IRQ_EXT_TIMER3 },
+	{ &IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x10,
+	  IT83XX_IRQ_EXT_TIMER4 },
+	{ &IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x20,
+	  IT83XX_IRQ_EXT_TIMER5 },
+	{ &IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x40,
+	  IT83XX_IRQ_EXT_TIMER6 },
+	{ &IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x80,
+	  IT83XX_IRQ_EXT_TIMER7 },
+	{ &IT83XX_INTC_IELMR10, &IT83XX_INTC_IPOLR10, &IT83XX_INTC_ISR10, 0x01,
+	  IT83XX_IRQ_EXT_TMR8 },
 };
 BUILD_ASSERT(ARRAY_SIZE(et_ctrl_regs) == EXT_TIMER_COUNT);
 
@@ -128,7 +128,8 @@ void __hw_clock_event_set(uint32_t deadline)
 	wait = deadline - __hw_clock_source_read();
 	IT83XX_ETWD_ETXCNTLR(EVENT_EXT_TIMER) =
 		wait < EVENT_TIMER_COUNT_TO_US(0xffffffff) ?
-		EVENT_TIMER_US_TO_COUNT(wait) : 0xffffffff;
+			EVENT_TIMER_US_TO_COUNT(wait) :
+			0xffffffff;
 	/* enable and re-start timer */
 	IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) |= 0x03;
 	task_enable_irq(et_ctrl_regs[EVENT_EXT_TIMER].irq);
@@ -225,7 +226,7 @@ DECLARE_IRQ(CPU_INT_GROUP_3, __hw_clock_source_irq, 1);
 
 #ifdef IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES
 /* Number of CPU cycles in 125 us */
-#define CYCLES_125NS (125*(PLL_CLOCK/SECOND) / 1000)
+#define CYCLES_125NS (125 * (PLL_CLOCK / SECOND) / 1000)
 uint32_t __ram_code ext_observation_reg_read(enum ext_timer_sel ext_timer)
 {
 	uint32_t prev_mask = read_clear_int_mask();
@@ -245,8 +246,8 @@ uint32_t __ram_code ext_observation_reg_read(enum ext_timer_sel ext_timer)
 		/* read for the second time */
 		"lwi %0,[%1]\n\t"
 		: "=&r"(val)
-		: "r"((uintptr_t) &IT83XX_ETWD_ETXCNTOR(ext_timer)),
-			"i"(CYCLES_125NS));
+		: "r"((uintptr_t)&IT83XX_ETWD_ETXCNTOR(ext_timer)),
+		  "i"(CYCLES_125NS));
 	/* restore interrupts */
 	set_int_mask(prev_mask);
 
@@ -275,10 +276,8 @@ void ext_timer_stop(enum ext_timer_sel ext_timer, int dis_irq)
 }
 
 static void ext_timer_ctrl(enum ext_timer_sel ext_timer,
-		enum ext_timer_clock_source ext_timer_clock,
-		int start,
-		int with_int,
-		int32_t count)
+			   enum ext_timer_clock_source ext_timer_clock,
+			   int start, int with_int, int32_t count)
 {
 	uint8_t intc_mask;
 
@@ -307,12 +306,8 @@ static void ext_timer_ctrl(enum ext_timer_sel ext_timer,
 }
 
 int ext_timer_ms(enum ext_timer_sel ext_timer,
-		enum ext_timer_clock_source ext_timer_clock,
-		int start,
-		int with_int,
-		int32_t ms,
-		int first_time_enable,
-		int raw)
+		 enum ext_timer_clock_source ext_timer_clock, int start,
+		 int with_int, int32_t ms, int first_time_enable, int raw)
 {
 	uint32_t count;
 
diff --git a/chip/it83xx/hwtimer_chip.h b/chip/it83xx/hwtimer_chip.h
index 2ccdce1d96..675c49cc40 100644
--- a/chip/it83xx/hwtimer_chip.h
+++ b/chip/it83xx/hwtimer_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,17 +8,17 @@
 #ifndef __CROS_EC_HWTIMER_CHIP_H
 #define __CROS_EC_HWTIMER_CHIP_H
 
-#define TIMER_COUNT_1US_SHIFT      3
+#define TIMER_COUNT_1US_SHIFT 3
 
 /* Microseconds to event timer counter setting register */
-#define EVENT_TIMER_US_TO_COUNT(us)  ((us) << TIMER_COUNT_1US_SHIFT)
+#define EVENT_TIMER_US_TO_COUNT(us) ((us) << TIMER_COUNT_1US_SHIFT)
 /* Event timer counter observation value to microseconds */
 #define EVENT_TIMER_COUNT_TO_US(cnt) ((cnt) >> TIMER_COUNT_1US_SHIFT)
 
-#define FREE_EXT_TIMER_L     EXT_TIMER_3
-#define FREE_EXT_TIMER_H     EXT_TIMER_4
-#define FAN_CTRL_EXT_TIMER   EXT_TIMER_5
-#define EVENT_EXT_TIMER      EXT_TIMER_6
+#define FREE_EXT_TIMER_L EXT_TIMER_3
+#define FREE_EXT_TIMER_H EXT_TIMER_4
+#define FAN_CTRL_EXT_TIMER EXT_TIMER_5
+#define EVENT_EXT_TIMER EXT_TIMER_6
 /*
  * The low power timer is used to continue system time when EC goes into low
  * power in idle task. Timer 7 is 24bit timer and configured at 32.768khz.
@@ -30,15 +30,15 @@
  * mask of observation register in clock_sleep_mode_wakeup_isr() or EC will get
  * wrong system time after resume.
  */
-#define LOW_POWER_EXT_TIMER  EXT_TIMER_7
+#define LOW_POWER_EXT_TIMER EXT_TIMER_7
 #define LOW_POWER_TIMER_MASK (BIT(24) - 1)
-#define WDT_EXT_TIMER        EXT_TIMER_8
+#define WDT_EXT_TIMER EXT_TIMER_8
 
 enum ext_timer_clock_source {
 	EXT_PSR_32P768K_HZ = 0,
-	EXT_PSR_1P024K_HZ  = 1,
-	EXT_PSR_32_HZ      = 2,
-	EXT_PSR_8M_HZ      = 3
+	EXT_PSR_1P024K_HZ = 1,
+	EXT_PSR_32_HZ = 2,
+	EXT_PSR_8M_HZ = 3
 };
 
 /*
@@ -83,11 +83,7 @@ void update_exc_start_time(void);
  * @param raw	(!=0) timer count equal to param "ms" no conversion.
  */
 int ext_timer_ms(enum ext_timer_sel ext_timer,
-		enum ext_timer_clock_source ext_timer_clock,
-		int start,
-		int et_int,
-		int32_t ms,
-		int first_time_enable,
-		int raw);
+		 enum ext_timer_clock_source ext_timer_clock, int start,
+		 int et_int, int32_t ms, int first_time_enable, int raw);
 
 #endif /* __CROS_EC_HWTIMER_CHIP_H */
diff --git a/chip/it83xx/i2c.c b/chip/it83xx/i2c.c
index 836ee7a82f..701f2a9576 100644
--- a/chip/it83xx/i2c.c
+++ b/chip/it83xx/i2c.c
@@ -1,10 +1,11 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* I2C module for Chrome EC */
 
+#include "builtin/assert.h"
 #include "clock.h"
 #include "common.h"
 #include "console.h"
@@ -16,7 +17,7 @@
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
 
 /* Default maximum time we allow for an I2C transfer */
 #define I2C_TIMEOUT_DEFAULT_US (100 * MSEC)
@@ -28,13 +29,13 @@
 #endif
 
 /* It is allowed to configure the size up to 2K bytes. */
-#define I2C_CQ_MODE_MAX_PAYLOAD_SIZE     128
+#define I2C_CQ_MODE_MAX_PAYLOAD_SIZE 128
 /* reserved 5 bytes for ID and CMD_x */
-#define I2C_CQ_MODE_TX_MAX_PAYLOAD_SIZE  (I2C_CQ_MODE_MAX_PAYLOAD_SIZE - 5)
+#define I2C_CQ_MODE_TX_MAX_PAYLOAD_SIZE (I2C_CQ_MODE_MAX_PAYLOAD_SIZE - 5)
 uint8_t i2c_cq_mode_tx_dlm[I2C_ENHANCED_PORT_COUNT]
-			[I2C_CQ_MODE_MAX_PAYLOAD_SIZE] __aligned(4);
+			  [I2C_CQ_MODE_MAX_PAYLOAD_SIZE] __aligned(4);
 uint8_t i2c_cq_mode_rx_dlm[I2C_ENHANCED_PORT_COUNT]
-			[I2C_CQ_MODE_MAX_PAYLOAD_SIZE] __aligned(4);
+			  [I2C_CQ_MODE_MAX_PAYLOAD_SIZE] __aligned(4);
 
 /* Repeat Start */
 #define I2C_CQ_CMD_L_RS BIT(7)
@@ -44,9 +45,9 @@ uint8_t i2c_cq_mode_rx_dlm[I2C_ENHANCED_PORT_COUNT]
  */
 #define I2C_CQ_CMD_L_RW BIT(6)
 /* P (STOP) is the I2C STOP condition */
-#define I2C_CQ_CMD_L_P  BIT(5)
+#define I2C_CQ_CMD_L_P BIT(5)
 /* E (End) is this device end flag */
-#define I2C_CQ_CMD_L_E  BIT(4)
+#define I2C_CQ_CMD_L_E BIT(4)
 /* LA (Last ACK) is Last ACK in master receiver */
 #define I2C_CQ_CMD_L_LA BIT(3)
 /* bit[2:0] are number of transfer out or receive data which depends on R/W. */
@@ -86,8 +87,8 @@ enum i2c_host_status {
 	/* Byte done status */
 	HOSTA_BDS = 0x80,
 	/* Error bit is set */
-	HOSTA_ANY_ERROR = (HOSTA_DVER | HOSTA_BSER |
-				HOSTA_FAIL | HOSTA_NACK | HOSTA_TMOE),
+	HOSTA_ANY_ERROR = (HOSTA_DVER | HOSTA_BSER | HOSTA_FAIL | HOSTA_NACK |
+			   HOSTA_TMOE),
 	/* W/C for next byte */
 	HOSTA_NEXT_BYTE = HOSTA_BDS,
 	/* W/C host status register */
@@ -155,10 +156,10 @@ struct i2c_ch_freq {
 };
 
 static const struct i2c_ch_freq i2c_freq_select[] = {
-	{ 50,   1},
-	{ 100,  2},
-	{ 400,  3},
-	{ 1000, 4},
+	{ 50, 1 },
+	{ 100, 2 },
+	{ 400, 3 },
+	{ 1000, 4 },
 };
 
 struct i2c_pin {
@@ -173,37 +174,30 @@ struct i2c_pin {
 };
 
 static const struct i2c_pin i2c_pin_regs[] = {
-	{ &IT83XX_GPIO_GPCRB3, &IT83XX_GPIO_GPCRB4,
-		&IT83XX_GPIO_GPDRB, &IT83XX_GPIO_GPDRB,
-		&IT83XX_GPIO_GPDMRB, &IT83XX_GPIO_GPDMRB,
-		0x08, 0x10},
-	{ &IT83XX_GPIO_GPCRC1, &IT83XX_GPIO_GPCRC2,
-		&IT83XX_GPIO_GPDRC, &IT83XX_GPIO_GPDRC,
-		&IT83XX_GPIO_GPDMRC, &IT83XX_GPIO_GPDMRC,
-		0x02, 0x04},
+	{ &IT83XX_GPIO_GPCRB3, &IT83XX_GPIO_GPCRB4, &IT83XX_GPIO_GPDRB,
+	  &IT83XX_GPIO_GPDRB, &IT83XX_GPIO_GPDMRB, &IT83XX_GPIO_GPDMRB, 0x08,
+	  0x10 },
+	{ &IT83XX_GPIO_GPCRC1, &IT83XX_GPIO_GPCRC2, &IT83XX_GPIO_GPDRC,
+	  &IT83XX_GPIO_GPDRC, &IT83XX_GPIO_GPDMRC, &IT83XX_GPIO_GPDMRC, 0x02,
+	  0x04 },
 #ifdef CONFIG_IT83XX_SMCLK2_ON_GPC7
-	{ &IT83XX_GPIO_GPCRC7, &IT83XX_GPIO_GPCRF7,
-		&IT83XX_GPIO_GPDRC, &IT83XX_GPIO_GPDRF,
-		&IT83XX_GPIO_GPDMRC, &IT83XX_GPIO_GPDMRF,
-		0x80, 0x80},
+	{ &IT83XX_GPIO_GPCRC7, &IT83XX_GPIO_GPCRF7, &IT83XX_GPIO_GPDRC,
+	  &IT83XX_GPIO_GPDRF, &IT83XX_GPIO_GPDMRC, &IT83XX_GPIO_GPDMRF, 0x80,
+	  0x80 },
 #else
-	{ &IT83XX_GPIO_GPCRF6, &IT83XX_GPIO_GPCRF7,
-		&IT83XX_GPIO_GPDRF, &IT83XX_GPIO_GPDRF,
-		&IT83XX_GPIO_GPDMRF, &IT83XX_GPIO_GPDMRF,
-		0x40, 0x80},
+	{ &IT83XX_GPIO_GPCRF6, &IT83XX_GPIO_GPCRF7, &IT83XX_GPIO_GPDRF,
+	  &IT83XX_GPIO_GPDRF, &IT83XX_GPIO_GPDMRF, &IT83XX_GPIO_GPDMRF, 0x40,
+	  0x80 },
 #endif
-	{ &IT83XX_GPIO_GPCRH1, &IT83XX_GPIO_GPCRH2,
-		&IT83XX_GPIO_GPDRH, &IT83XX_GPIO_GPDRH,
-		&IT83XX_GPIO_GPDMRH, &IT83XX_GPIO_GPDMRH,
-		0x02, 0x04},
-	{ &IT83XX_GPIO_GPCRE0, &IT83XX_GPIO_GPCRE7,
-		&IT83XX_GPIO_GPDRE, &IT83XX_GPIO_GPDRE,
-		&IT83XX_GPIO_GPDMRE, &IT83XX_GPIO_GPDMRE,
-		0x01, 0x80},
-	{ &IT83XX_GPIO_GPCRA4, &IT83XX_GPIO_GPCRA5,
-		&IT83XX_GPIO_GPDRA, &IT83XX_GPIO_GPDRA,
-		&IT83XX_GPIO_GPDMRA, &IT83XX_GPIO_GPDMRA,
-		0x10, 0x20},
+	{ &IT83XX_GPIO_GPCRH1, &IT83XX_GPIO_GPCRH2, &IT83XX_GPIO_GPDRH,
+	  &IT83XX_GPIO_GPDRH, &IT83XX_GPIO_GPDMRH, &IT83XX_GPIO_GPDMRH, 0x02,
+	  0x04 },
+	{ &IT83XX_GPIO_GPCRE0, &IT83XX_GPIO_GPCRE7, &IT83XX_GPIO_GPDRE,
+	  &IT83XX_GPIO_GPDRE, &IT83XX_GPIO_GPDMRE, &IT83XX_GPIO_GPDMRE, 0x01,
+	  0x80 },
+	{ &IT83XX_GPIO_GPCRA4, &IT83XX_GPIO_GPCRA5, &IT83XX_GPIO_GPDRA,
+	  &IT83XX_GPIO_GPDRA, &IT83XX_GPIO_GPDMRA, &IT83XX_GPIO_GPDMRA, 0x10,
+	  0x20 },
 };
 
 struct i2c_ctrl_t {
@@ -213,12 +207,12 @@ struct i2c_ctrl_t {
 };
 
 const struct i2c_ctrl_t i2c_ctrl_regs[] = {
-	{IT83XX_IRQ_SMB_A, CGC_OFFSET_SMBA, -1},
-	{IT83XX_IRQ_SMB_B, CGC_OFFSET_SMBB, -1},
-	{IT83XX_IRQ_SMB_C, CGC_OFFSET_SMBC, -1},
-	{IT83XX_IRQ_SMB_D, CGC_OFFSET_SMBD, 3},
-	{IT83XX_IRQ_SMB_E, CGC_OFFSET_SMBE, 0},
-	{IT83XX_IRQ_SMB_F, CGC_OFFSET_SMBF, 1},
+	{ IT83XX_IRQ_SMB_A, CGC_OFFSET_SMBA, -1 },
+	{ IT83XX_IRQ_SMB_B, CGC_OFFSET_SMBB, -1 },
+	{ IT83XX_IRQ_SMB_C, CGC_OFFSET_SMBC, -1 },
+	{ IT83XX_IRQ_SMB_D, CGC_OFFSET_SMBD, 3 },
+	{ IT83XX_IRQ_SMB_E, CGC_OFFSET_SMBE, 0 },
+	{ IT83XX_IRQ_SMB_F, CGC_OFFSET_SMBF, 1 },
 };
 
 enum i2c_ch_status {
@@ -230,17 +224,17 @@ enum i2c_ch_status {
 
 /* I2C port state data */
 struct i2c_port_data {
-	const uint8_t *out;  /* Output data pointer */
-	int out_size;        /* Output data to transfer, in bytes */
-	uint8_t *in;         /* Input data pointer */
-	int in_size;         /* Input data to transfer, in bytes */
-	int flags;           /* Flags (I2C_XFER_*) */
-	int widx;            /* Index into output data */
-	int ridx;            /* Index into input data */
-	int err;             /* Error code, if any */
-	uint8_t addr_8bit;   /* address of device */
+	const uint8_t *out; /* Output data pointer */
+	int out_size; /* Output data to transfer, in bytes */
+	uint8_t *in; /* Input data pointer */
+	int in_size; /* Input data to transfer, in bytes */
+	int flags; /* Flags (I2C_XFER_*) */
+	int widx; /* Index into output data */
+	int ridx; /* Index into input data */
+	int err; /* Error code, if any */
+	uint8_t addr_8bit; /* address of device */
 	uint32_t timeout_us; /* Transaction timeout, or 0 to use default */
-	uint8_t freq;        /* Frequency setting */
+	uint8_t freq; /* Frequency setting */
 
 	enum i2c_ch_status i2ccs;
 	/* Task waiting on port, or TASK_ID_INVALID if none. */
@@ -329,8 +323,8 @@ static void i2c_pio_trans_data(int p, enum enhanced_i2c_transfer_direct direct,
 
 	if (first_byte) {
 		/* First byte must be peripheral address. */
-		IT83XX_I2C_DTR(p_ch) =
-			data | (direct == RX_DIRECT ? BIT(0) : 0);
+		IT83XX_I2C_DTR(p_ch) = data |
+				       (direct == RX_DIRECT ? BIT(0) : 0);
 		/* start or repeat start signal. */
 		IT83XX_I2C_CTR(p_ch) = E_START_ID;
 	} else {
@@ -343,12 +337,12 @@ static void i2c_pio_trans_data(int p, enum enhanced_i2c_transfer_direct direct,
 			 * Last byte should be NACK in the end of read cycle
 			 */
 			if (((pd->ridx + 1) == pd->in_size) &&
-				(pd->flags & I2C_XFER_STOP))
+			    (pd->flags & I2C_XFER_STOP))
 				nack = 1;
 		}
 		/* Set hardware reset to start next transmission */
-		IT83XX_I2C_CTR(p_ch) =
-			E_INT_EN | E_MODE_SEL | E_HW_RST | (nack ? 0 : E_ACK);
+		IT83XX_I2C_CTR(p_ch) = E_INT_EN | E_MODE_SEL | E_HW_RST |
+				       (nack ? 0 : E_ACK);
 	}
 }
 
@@ -439,7 +433,7 @@ static int i2c_tran_read(int p)
 			IT83XX_SMB_HOCTL(p) = 0x5D;
 	} else {
 		if ((pd->i2ccs == I2C_CH_REPEAT_START) ||
-			(pd->i2ccs == I2C_CH_WAIT_READ)) {
+		    (pd->i2ccs == I2C_CH_WAIT_READ)) {
 			if (pd->i2ccs == I2C_CH_REPEAT_START) {
 				/* write to read */
 				i2c_w2r_change_direction(p);
@@ -532,8 +526,8 @@ static int enhanced_i2c_tran_write(int p)
 				/* Write to read protocol */
 				pd->i2ccs = I2C_CH_REPEAT_START;
 				/* Repeat Start */
-				i2c_pio_trans_data(p, RX_DIRECT,
-						   pd->addr_8bit, 1);
+				i2c_pio_trans_data(p, RX_DIRECT, pd->addr_8bit,
+						   1);
 			} else {
 				if (pd->flags & I2C_XFER_STOP) {
 					IT83XX_I2C_CTR(p_ch) = E_FINISH;
@@ -582,8 +576,8 @@ static int enhanced_i2c_tran_read(int p)
 				/* Write to read */
 				pd->i2ccs = I2C_CH_WAIT_READ;
 				/* Send ID */
-				i2c_pio_trans_data(p, RX_DIRECT,
-						   pd->addr_8bit, 1);
+				i2c_pio_trans_data(p, RX_DIRECT, pd->addr_8bit,
+						   1);
 				task_enable_irq(i2c_ctrl_regs[p].irq);
 			}
 		} else {
@@ -622,7 +616,7 @@ static int enhanced_i2c_error(int p)
 
 	if (i2c_str & E_HOSTA_ANY_ERROR) {
 		pd->err = i2c_str & E_HOSTA_ANY_ERROR;
-	/* device does not respond ACK */
+		/* device does not respond ACK */
 	} else if ((i2c_str & E_HOSTA_BDS_AND_ACK) == E_HOSTA_BDS) {
 		if (IT83XX_I2C_CTR(p_ch) & E_ACK)
 			pd->err = E_HOSTA_ACK;
@@ -666,14 +660,14 @@ uint32_t i2c_idle_not_allowed(void)
 	return i2c_idle_disabled;
 }
 
-static int command_i2c_idle_mask(int argc, char **argv)
+static int command_i2c_idle_mask(int argc, const char **argv)
 {
 	ccprintf("i2c idle mask: %08x\n", i2c_idle_disabled);
 
 	return EC_SUCCESS;
 }
-DECLARE_SAFE_CONSOLE_COMMAND(i2cidlemask, command_i2c_idle_mask,
-			     NULL, "Display i2c idle mask");
+DECLARE_SAFE_CONSOLE_COMMAND(i2cidlemask, command_i2c_idle_mask, NULL,
+			     "Display i2c idle mask");
 
 static void enhanced_i2c_cq_write(int p)
 {
@@ -703,8 +697,8 @@ static void enhanced_i2c_cq_read(int p)
 	i2c_cq_pckt = (struct i2c_cq_packet *)&i2c_cq_mode_tx_dlm[dlm_index];
 	/* Set commands in RAM. */
 	i2c_cq_pckt->id = pd->addr_8bit;
-	i2c_cq_pckt->cmd_l = I2C_CQ_CMD_L_RW | I2C_CQ_CMD_L_P |
-				I2C_CQ_CMD_L_E | num_bit_2_0;
+	i2c_cq_pckt->cmd_l = I2C_CQ_CMD_L_RW | I2C_CQ_CMD_L_P | I2C_CQ_CMD_L_E |
+			     num_bit_2_0;
 	i2c_cq_pckt->cmd_h = num_bit_10_3;
 }
 
@@ -728,7 +722,7 @@ static void enhanced_i2c_cq_write_to_read(int p)
 	num_bit_2_0 = (pd->in_size - 1) & I2C_CQ_CMD_L_NUM_BIT_2_0;
 	num_bit_10_3 = ((pd->in_size - 1) >> 3) & 0xff;
 	i2c_cq_pckt->wdata[i++] = I2C_CQ_CMD_L_RS | I2C_CQ_CMD_L_RW |
-				I2C_CQ_CMD_L_P | I2C_CQ_CMD_L_E | num_bit_2_0;
+				  I2C_CQ_CMD_L_P | I2C_CQ_CMD_L_E | num_bit_2_0;
 	i2c_cq_pckt->wdata[i] = num_bit_10_3;
 }
 
@@ -751,7 +745,7 @@ static int enhanced_i2c_cmd_queue_trans(int p)
 				pd->err = E_HOSTA_ACK;
 			else
 				pd->err = IT83XX_I2C_STR(p_ch) &
-						E_HOSTA_ANY_ERROR;
+					  E_HOSTA_ANY_ERROR;
 		}
 		/* reset bus */
 		IT83XX_I2C_CTR(p_ch) = E_STS_AND_HW_RST;
@@ -761,7 +755,7 @@ static int enhanced_i2c_cmd_queue_trans(int p)
 	}
 
 	if ((pd->out_size > I2C_CQ_MODE_TX_MAX_PAYLOAD_SIZE) ||
-		(pd->in_size > I2C_CQ_MODE_MAX_PAYLOAD_SIZE)) {
+	    (pd->in_size > I2C_CQ_MODE_MAX_PAYLOAD_SIZE)) {
 		pd->err = EC_ERROR_INVAL;
 		return 0;
 	}
@@ -868,9 +862,8 @@ int i2c_is_busy(int port)
 	return (IT83XX_I2C_STR(p_ch) & E_HOSTA_BB);
 }
 
-int chip_i2c_xfer(int port, uint16_t addr_flags,
-		  const uint8_t *out, int out_size,
-		  uint8_t *in, int in_size, int flags)
+int chip_i2c_xfer(int port, uint16_t addr_flags, const uint8_t *out,
+		  int out_size, uint8_t *in, int in_size, int flags)
 {
 	struct i2c_port_data *pd = pdata + port;
 	uint32_t events = 0;
@@ -900,9 +893,9 @@ int chip_i2c_xfer(int port, uint16_t addr_flags,
 	pd->addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1;
 
 	/* Make sure we're in a good state to start */
-	if ((flags & I2C_XFER_START) && (i2c_is_busy(port)
-		|| (i2c_get_line_levels(port) != I2C_LINE_IDLE))) {
-
+	if ((flags & I2C_XFER_START) &&
+	    (i2c_is_busy(port) ||
+	     (i2c_get_line_levels(port) != I2C_LINE_IDLE))) {
 		/* Attempt to unwedge the port. */
 		pd->err = i2c_unwedge(port);
 
@@ -953,7 +946,7 @@ int i2c_raw_get_scl(int port)
 
 	if (get_scl_from_i2c_port(port, &g) == EC_SUCCESS)
 		return !!(*i2c_pin_regs[port].mirror_clk &
-			i2c_pin_regs[port].clk_mask);
+			  i2c_pin_regs[port].clk_mask);
 
 	/* If no SCL pin defined for this port, then return 1 to appear idle */
 	return 1;
@@ -965,7 +958,7 @@ int i2c_raw_get_sda(int port)
 
 	if (get_sda_from_i2c_port(port, &g) == EC_SUCCESS)
 		return !!(*i2c_pin_regs[port].mirror_data &
-			i2c_pin_regs[port].data_mask);
+			  i2c_pin_regs[port].data_mask);
 
 	/* If no SDA pin defined for this port, then return 1 to appear idle */
 	return 1;
@@ -1041,7 +1034,7 @@ static void i2c_standard_port_set_frequency(int port, int freq_khz)
 		for (int f = ARRAY_SIZE(i2c_freq_select) - 1; f >= 0; f--) {
 			if (freq_khz >= i2c_freq_select[f].kbps) {
 				IT83XX_SMB_SCLKTS(port) =
-						i2c_freq_select[f].freq_set;
+					i2c_freq_select[f].freq_set;
 				break;
 			}
 		}
@@ -1143,10 +1136,10 @@ void i2c_init(void)
 			p_ch = i2c_ch_reg_shift(p);
 			switch (p) {
 			case IT83XX_I2C_CH_D:
-				#ifndef CONFIG_UART_HOST
+#ifndef CONFIG_UART_HOST
 				/* Enable SMBus D channel */
 				IT83XX_GPIO_GRC2 |= 0x20;
-				#endif
+#endif
 				break;
 			case IT83XX_I2C_CH_E:
 				/* Enable SMBus E channel */
diff --git a/chip/it83xx/i2c_peripheral.c b/chip/it83xx/i2c_peripheral.c
index 1590c39bca..80fea907fd 100644
--- a/chip/it83xx/i2c_peripheral.c
+++ b/chip/it83xx/i2c_peripheral.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,13 +10,14 @@
 #include "gpio.h"
 #include "hooks.h"
 #include "i2c_peripheral.h"
+#include "printf.h"
 #include "registers.h"
 #include <stddef.h>
 #include <string.h>
 #include "task.h"
 
 /* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
 
 /* The size must be a power of 2 */
 #define I2C_MAX_BUFFER_SIZE 0x100
@@ -27,10 +28,10 @@
 
 /* Store controller to peripheral data of channel D, E, F by DMA */
 static uint8_t in_data[I2C_ENHANCED_PORT_COUNT][I2C_MAX_BUFFER_SIZE]
-			__attribute__((section(".h2ram.pool.i2cslv")));
+	__attribute__((section(".h2ram.pool.i2cslv")));
 /* Store peripheral to controller data of channel D, E, F by DMA */
 static uint8_t out_data[I2C_ENHANCED_PORT_COUNT][I2C_MAX_BUFFER_SIZE]
-			__attribute__((section(".h2ram.pool.i2cslv")));
+	__attribute__((section(".h2ram.pool.i2cslv")));
 /* Store read and write data of channel A by FIFO mode */
 static uint8_t pbuffer[I2C_MAX_BUFFER_SIZE];
 
@@ -48,7 +49,7 @@ void buffer_index_reset(void)
 
 /* Data structure to define I2C peripheral control configuration. */
 struct i2c_periph_ctrl_t {
-	int irq;              /* peripheral irq */
+	int irq; /* peripheral irq */
 	/* offset from base 0x00F03500 register; -1 means unused. */
 	int offset;
 	enum clock_gate_offsets clock_gate;
@@ -57,14 +58,22 @@ struct i2c_periph_ctrl_t {
 
 /* I2C peripheral control */
 const struct i2c_periph_ctrl_t i2c_periph_ctrl[] = {
-	[IT83XX_I2C_CH_A] = {.irq = IT83XX_IRQ_SMB_A, .offset = -1,
-		.clock_gate = CGC_OFFSET_SMBA, .dma_index = -1},
-	[IT83XX_I2C_CH_D] = {.irq = IT83XX_IRQ_SMB_D, .offset = 0x180,
-		.clock_gate = CGC_OFFSET_SMBD, .dma_index = 0},
-	[IT83XX_I2C_CH_E] = {.irq = IT83XX_IRQ_SMB_E, .offset = 0x0,
-		.clock_gate = CGC_OFFSET_SMBE, .dma_index = 1},
-	[IT83XX_I2C_CH_F] = {.irq = IT83XX_IRQ_SMB_F, .offset = 0x80,
-		.clock_gate = CGC_OFFSET_SMBF, .dma_index = 2},
+	[IT83XX_I2C_CH_A] = { .irq = IT83XX_IRQ_SMB_A,
+			      .offset = -1,
+			      .clock_gate = CGC_OFFSET_SMBA,
+			      .dma_index = -1 },
+	[IT83XX_I2C_CH_D] = { .irq = IT83XX_IRQ_SMB_D,
+			      .offset = 0x180,
+			      .clock_gate = CGC_OFFSET_SMBD,
+			      .dma_index = 0 },
+	[IT83XX_I2C_CH_E] = { .irq = IT83XX_IRQ_SMB_E,
+			      .offset = 0x0,
+			      .clock_gate = CGC_OFFSET_SMBE,
+			      .dma_index = 1 },
+	[IT83XX_I2C_CH_F] = { .irq = IT83XX_IRQ_SMB_F,
+			      .offset = 0x80,
+			      .clock_gate = CGC_OFFSET_SMBF,
+			      .dma_index = 2 },
 };
 
 void i2c_peripheral_read_write_data(int port)
@@ -87,7 +96,8 @@ void i2c_peripheral_read_write_data(int port)
 				for (i = 0; i < I2C_READ_MAXFIFO_DATA; i++)
 					/* Return buffer data to controller */
 					IT83XX_SMB_SLDA =
-					pbuffer[(i + r_index) & I2C_SIZE_MASK];
+						pbuffer[(i + r_index) &
+							I2C_SIZE_MASK];
 
 				/* Index to next 16 bytes of read buffer */
 				r_index += I2C_READ_MAXFIFO_DATA;
@@ -97,9 +107,11 @@ void i2c_peripheral_read_write_data(int port)
 				/* FIFO Full */
 				if (IT83XX_SMB_SFFSTA & IT83XX_SMB_SFFFULL) {
 					for (i = 0; i < count; i++)
-				/* Get data from controller to buffer */
+						/* Get data from controller to
+						 * buffer */
 						pbuffer[(w_index + i) &
-					I2C_SIZE_MASK] = IT83XX_SMB_SLDA;
+							I2C_SIZE_MASK] =
+							IT83XX_SMB_SLDA;
 				}
 
 				/* Index to next byte of write buffer */
@@ -120,8 +132,8 @@ void i2c_peripheral_read_write_data(int port)
 			else {
 				for (i = 0; i < count; i++)
 					/* Get data from controller to buffer */
-					pbuffer[(i + w_index) &
-					I2C_SIZE_MASK] = IT83XX_SMB_SLDA;
+					pbuffer[(i + w_index) & I2C_SIZE_MASK] =
+						IT83XX_SMB_SLDA;
 			}
 
 			/* Reset read and write buffer index */
@@ -147,16 +159,15 @@ void i2c_peripheral_read_write_data(int port)
 
 		/* Interrupt pending */
 		if (IT83XX_I2C_STR(ch) & IT83XX_I2C_INTPEND) {
-
 			periph_status = IT83XX_I2C_IRQ_ST(ch);
 
 			/* Controller to read data */
 			if (periph_status & IT83XX_I2C_IDR_CLR) {
-			/*
-			 * TODO(b:129360157): Return buffer data by
-			 * "out_data" array.
-			 * Ex: Write data to buffer from 0x00 to 0xFF
-			 */
+				/*
+				 * TODO(b:129360157): Return buffer data by
+				 * "out_data" array.
+				 * Ex: Write data to buffer from 0x00 to 0xFF
+				 */
 				for (i = 0; i < I2C_MAX_BUFFER_SIZE; i++)
 					out_data[idx][i] = i;
 			}
@@ -168,13 +179,17 @@ void i2c_peripheral_read_write_data(int port)
 			/* Peripheral finish */
 			if (periph_status & IT83XX_I2C_P_CLR) {
 				if (wr_done[idx]) {
-			/*
-			 * TODO(b:129360157): Handle controller write
-			 * data by "in_data" array.
-			 */
-					CPRINTS("WData: %ph",
+					char str_buf[hex_str_buf_size(
+						I2C_MAX_BUFFER_SIZE)];
+					/*
+					 * TODO(b:129360157): Handle controller
+					 * write data by "in_data" array.
+					 */
+					snprintf_hex_buffer(
+						str_buf, sizeof(str_buf),
 						HEX_BUF(in_data[idx],
 							I2C_MAX_BUFFER_SIZE));
+					CPRINTS("WData: %s", str_buf);
 					wr_done[idx] = 0;
 				}
 			}
@@ -199,12 +214,10 @@ void i2c_periph_interrupt(int port)
 
 void i2c_peripheral_enable(int port, uint8_t periph_addr)
 {
-
 	clock_enable_peripheral(i2c_periph_ctrl[port].clock_gate, 0, 0);
 
 	/* I2C peripheral channel A FIFO mode */
 	if (port < I2C_STANDARD_PORT_COUNT) {
-
 		/* This field defines the SMCLK0/1/2 clock/data low timeout. */
 		IT83XX_SMB_25MS = I2C_CLK_LOW_TIMEOUT;
 
@@ -266,8 +279,8 @@ void i2c_peripheral_enable(int port, uint8_t periph_addr)
 		IT83XX_I2C_IDR(ch) = periph_addr << 1;
 
 		/* I2C interrupt enable and set acknowledge */
-		IT83XX_I2C_CTR(ch) = IT83XX_I2C_HALT |
-			IT83XX_I2C_INTEN | IT83XX_I2C_ACK;
+		IT83XX_I2C_CTR(ch) = IT83XX_I2C_HALT | IT83XX_I2C_INTEN |
+				     IT83XX_I2C_ACK;
 
 		/*
 		 * bit3 : Peripheral ID write flag
@@ -313,21 +326,19 @@ void i2c_peripheral_enable(int port, uint8_t periph_addr)
 		}
 
 		/* I2C module enable and command queue mode */
-		IT83XX_I2C_CTR1(ch) = IT83XX_I2C_COMQ_EN |
-			IT83XX_I2C_MDL_EN;
+		IT83XX_I2C_CTR1(ch) = IT83XX_I2C_COMQ_EN | IT83XX_I2C_MDL_EN;
 	}
 }
 
 static void i2c_peripheral_init(void)
 {
-	int  i, p;
+	int i, p;
 
 	/* DLM 52k~56k size select enable */
 	IT83XX_GCTRL_MCCR2 |= (1 << 4);
 
 	/* Enable I2C Peripheral function */
 	for (i = 0; i < i2c_periphs_used; i++) {
-
 		/* I2c peripheral port mapping. */
 		p = i2c_periph_ports[i].port;
 
diff --git a/chip/it83xx/intc.c b/chip/it83xx/intc.c
index 45fff30c1e..89e5d70a01 100644
--- a/chip/it83xx/intc.c
+++ b/chip/it83xx/intc.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/it83xx/intc.h b/chip/it83xx/intc.h
index 50d31999f9..43adb3784d 100644
--- a/chip/it83xx/intc.h
+++ b/chip/it83xx/intc.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,7 +15,7 @@
 static inline void data_serialization_barrier(void)
 {
 	if (IS_ENABLED(CHIP_CORE_NDS32))
-		asm volatile ("dsb");
+		asm volatile("dsb");
 }
 
 int intc_get_ec_int(void);
diff --git a/chip/it83xx/irq.c b/chip/it83xx/irq.c
index fb01309721..21e8070f06 100644
--- a/chip/it83xx/irq.c
+++ b/chip/it83xx/irq.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,56 +10,59 @@
 #include "registers.h"
 #include "util.h"
 
-#define IRQ_GROUP(n, cpu_ints...) \
-	{(uint32_t)&CONCAT2(IT83XX_INTC_ISR, n) - IT83XX_INTC_BASE, \
-	 (uint32_t)&CONCAT2(IT83XX_INTC_IER, n) - IT83XX_INTC_BASE, \
-	 ##cpu_ints}
+#define IRQ_GROUP(n, cpu_ints...)                                            \
+	{                                                                    \
+		(uint32_t) & CONCAT2(IT83XX_INTC_ISR, n) - IT83XX_INTC_BASE, \
+			(uint32_t)&CONCAT2(IT83XX_INTC_IER, n) -             \
+				IT83XX_INTC_BASE,                            \
+			##cpu_ints                                           \
+	}
 
 static const struct {
 	uint8_t isr_off;
 	uint8_t ier_off;
 	uint8_t cpu_int[8];
 } irq_groups[] = {
-	IRQ_GROUP(0,  {-1,  2,  5,  4,  6,  2,  2,  4}),
-	IRQ_GROUP(1,  { 7,  6,  6,  5,  2,  2,  2,  8}),
-	IRQ_GROUP(2,  { 6,  2,  8,  8,  8,  2, 12, 12}),
-	IRQ_GROUP(3,  { 5,  4,  4,  4, 11, 11,  3,  2}),
-	IRQ_GROUP(4,  {11, 11, 11, 11,  8,  9,  9,  9}),
-	IRQ_GROUP(5,  { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(6,  { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(7,  {10, 10,  3, 12,  3,  3,  3,  3}),
-	IRQ_GROUP(8,  { 4,  4,  4,  4,  4,  4, -1, 12}),
-	IRQ_GROUP(9,  { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(10, { 3,  6, 12, 12,  5,  2,  2,  2}),
-	IRQ_GROUP(11, { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(12, { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(13, { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(14, { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(15, { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(16, { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(17, { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(18, { 2,  2,  2,  2, -1,  4,  4,  7}),
-	IRQ_GROUP(19, { 6,  6, 12,  3,  3,  3,  3,  3}),
-	IRQ_GROUP(20, {12, 12, 12, 12, 12, 12, 12, -1}),
+	IRQ_GROUP(0, { -1, 2, 5, 4, 6, 2, 2, 4 }),
+	IRQ_GROUP(1, { 7, 6, 6, 5, 2, 2, 2, 8 }),
+	IRQ_GROUP(2, { 6, 2, 8, 8, 8, 2, 12, 12 }),
+	IRQ_GROUP(3, { 5, 4, 4, 4, 11, 11, 3, 2 }),
+	IRQ_GROUP(4, { 11, 11, 11, 11, 8, 9, 9, 9 }),
+	IRQ_GROUP(5, { 2, 2, 2, 2, 2, 2, 2, 2 }),
+	IRQ_GROUP(6, { 2, 2, 2, 2, 2, 2, 2, 2 }),
+	IRQ_GROUP(7, { 10, 10, 3, 12, 3, 3, 3, 3 }),
+	IRQ_GROUP(8, { 4, 4, 4, 4, 4, 4, -1, 12 }),
+	IRQ_GROUP(9, { 2, 2, 2, 2, 2, 2, 2, 2 }),
+	IRQ_GROUP(10, { 3, 6, 12, 12, 5, 2, 2, 2 }),
+	IRQ_GROUP(11, { 2, 2, 2, 2, 2, 2, 2, 2 }),
+	IRQ_GROUP(12, { 2, 2, 2, 2, 2, 2, 2, 2 }),
+	IRQ_GROUP(13, { 2, 2, 2, 2, 2, 2, 2, 2 }),
+	IRQ_GROUP(14, { 2, 2, 2, 2, 2, 2, 2, 2 }),
+	IRQ_GROUP(15, { 2, 2, 2, 2, 2, 2, 2, 2 }),
+	IRQ_GROUP(16, { 2, 2, 2, 2, 2, 2, 2, 2 }),
+	IRQ_GROUP(17, { 2, 2, 2, 2, 2, 2, 2, 2 }),
+	IRQ_GROUP(18, { 2, 2, 2, 2, -1, 4, 4, 7 }),
+	IRQ_GROUP(19, { 6, 6, 12, 3, 3, 3, 3, 3 }),
+	IRQ_GROUP(20, { 12, 12, 12, 12, 12, 12, 12, -1 }),
 #if defined(IT83XX_INTC_GROUP_21_22_SUPPORT)
-	IRQ_GROUP(21, { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(22, { 2,  2, -1, -1, -1, -1, -1, -1}),
+	IRQ_GROUP(21, { 2, 2, 2, 2, 2, 2, 2, 2 }),
+	IRQ_GROUP(22, { 2, 2, -1, -1, -1, -1, -1, -1 }),
 #elif defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2)
-	IRQ_GROUP(21, {-1, -1, 12, 12, 12, 12, 12, 12}),
-	IRQ_GROUP(22, { 2,  2,  2,  2,  2,  2,  2,  2}),
+	IRQ_GROUP(21, { -1, -1, 12, 12, 12, 12, 12, 12 }),
+	IRQ_GROUP(22, { 2, 2, 2, 2, 2, 2, 2, 2 }),
 #else
-	IRQ_GROUP(21, {-1, -1, -1, -1, -1, -1, -1, -1}),
-	IRQ_GROUP(22, {-1, -1, -1, -1, -1, -1, -1, -1}),
+	IRQ_GROUP(21, { -1, -1, -1, -1, -1, -1, -1, -1 }),
+	IRQ_GROUP(22, { -1, -1, -1, -1, -1, -1, -1, -1 }),
 #endif
-	IRQ_GROUP(23, { 2,  2, -1, -1, -1, -1, -1,  2}),
-	IRQ_GROUP(24, { 2,  2,  2,  2,  2,  2, -1,  2}),
-	IRQ_GROUP(25, { 2,  2,  2,  2, -1, -1, -1, -1}),
-	IRQ_GROUP(26, { 2,  2,  2,  2,  2,  2,  2, -1}),
-	IRQ_GROUP(27, { 2,  2,  2,  2,  2,  2, -1, -1}),
-	IRQ_GROUP(28, { 2,  2,  2,  2,  2,  2, -1, -1}),
+	IRQ_GROUP(23, { 2, 2, -1, -1, -1, -1, -1, 2 }),
+	IRQ_GROUP(24, { 2, 2, 2, 2, 2, 2, -1, 2 }),
+	IRQ_GROUP(25, { 2, 2, 2, 2, -1, -1, -1, -1 }),
+	IRQ_GROUP(26, { 2, 2, 2, 2, 2, 2, 2, -1 }),
+	IRQ_GROUP(27, { 2, 2, 2, 2, 2, 2, -1, -1 }),
+	IRQ_GROUP(28, { 2, 2, 2, 2, 2, 2, -1, -1 }),
 };
 
-#if defined(CHIP_FAMILY_IT8320)    /* N8 core */
+#if defined(CHIP_FAMILY_IT8320) /* N8 core */
 /* Number of CPU hardware interrupts (HW0 ~ HW15) */
 int cpu_int_entry_number;
 #endif
@@ -68,7 +71,7 @@ int chip_get_ec_int(void)
 {
 	extern volatile int ec_int;
 
-#if defined(CHIP_FAMILY_IT8320)    /* N8 core */
+#if defined(CHIP_FAMILY_IT8320) /* N8 core */
 	int i;
 
 	for (i = 0; i < IT83XX_IRQ_COUNT; i++) {
diff --git a/chip/it83xx/it83xx_fpu.S b/chip/it83xx/it83xx_fpu.S
index 5265eb7253..a75145c835 100644
--- a/chip/it83xx/it83xx_fpu.S
+++ b/chip/it83xx/it83xx_fpu.S
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/it83xx/keyboard_raw.c b/chip/it83xx/keyboard_raw.c
index 6c7a10c463..0d2f048deb 100644
--- a/chip/it83xx/keyboard_raw.c
+++ b/chip/it83xx/keyboard_raw.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -111,7 +111,7 @@ test_mockable void keyboard_raw_drive_column(int col)
 	 * we are using).
 	 */
 	IT83XX_KBS_KSOH1 = (IT83XX_KBS_KSOH1 & ~KSOH_PIN_MASK) |
-		((mask >> 8) & KSOH_PIN_MASK);
+			   ((mask >> 8) & KSOH_PIN_MASK);
 	/* restore interrupts */
 	set_int_mask(int_mask);
 }
diff --git a/chip/it83xx/kmsc_chip.h b/chip/it83xx/kmsc_chip.h
index cf4169a1c4..84f781c0a6 100644
--- a/chip/it83xx/kmsc_chip.h
+++ b/chip/it83xx/kmsc_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/it83xx/lpc.c b/chip/it83xx/lpc.c
index 29f92e9b94..03606c6085 100644
--- a/chip/it83xx/lpc.c
+++ b/chip/it83xx/lpc.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -30,7 +30,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args)
 
 /* LPC PM channels */
 enum lpc_pm_ch {
@@ -48,25 +48,25 @@ enum pm_ctrl_mask {
 	PM_CTRL_OBEIE = 0x02,
 };
 
-#define LPC_ACPI_CMD      LPC_PM1   /* ACPI commands 62h/66h port */
-#define LPC_HOST_CMD      LPC_PM2   /* Host commands 200h/204h port */
-#define LPC_HOST_PORT_80H LPC_PM3   /* Host 80h port */
+#define LPC_ACPI_CMD LPC_PM1 /* ACPI commands 62h/66h port */
+#define LPC_HOST_CMD LPC_PM2 /* Host commands 200h/204h port */
+#define LPC_HOST_PORT_80H LPC_PM3 /* Host 80h port */
 
 static uint8_t acpi_ec_memmap[EC_MEMMAP_SIZE]
-			__attribute__((section(".h2ram.pool.acpiec")));
+	__attribute__((section(".h2ram.pool.acpiec")));
 static uint8_t host_cmd_memmap[256]
-			__attribute__((section(".h2ram.pool.hostcmd")));
+	__attribute__((section(".h2ram.pool.hostcmd")));
 
 static struct host_packet lpc_packet;
 static struct host_cmd_handler_args host_cmd_args;
-static uint8_t host_cmd_flags;   /* Flags from host command */
+static uint8_t host_cmd_flags; /* Flags from host command */
 
 /* Params must be 32-bit aligned */
 static uint8_t params_copy[EC_LPC_HOST_PACKET_SIZE] __aligned(4);
 static int init_done;
 static int p80l_index;
 
-static struct ec_lpc_host_args * const lpc_host_args =
+static struct ec_lpc_host_args *const lpc_host_args =
 	(struct ec_lpc_host_args *)host_cmd_memmap;
 
 static void pm_set_ctrl(enum lpc_pm_ch ch, enum pm_ctrl_mask ctrl, int set)
@@ -138,7 +138,7 @@ static void lpc_generate_smi(void)
 {
 #ifdef CONFIG_HOST_INTERFACE_ESPI
 	espi_vw_set_wire(VW_SMI_L, 0);
-	udelay(CONFIG_ESPI_DEFAULT_VW_WIDTH_US);
+	udelay(CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US);
 	espi_vw_set_wire(VW_SMI_L, 1);
 #else
 	gpio_set_level(GPIO_PCH_SMI_L, 0);
@@ -151,7 +151,7 @@ static void lpc_generate_sci(void)
 {
 #ifdef CONFIG_HOST_INTERFACE_ESPI
 	espi_vw_set_wire(VW_SCI_L, 0);
-	udelay(CONFIG_ESPI_DEFAULT_VW_WIDTH_US);
+	udelay(CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US);
 	espi_vw_set_wire(VW_SCI_L, 1);
 #else
 	gpio_set_level(GPIO_PCH_SCI_L, 0);
@@ -195,15 +195,13 @@ static void lpc_send_response(struct host_cmd_handler_args *args)
 	}
 
 	/* New-style response */
-	lpc_host_args->flags =
-		(host_cmd_flags & ~EC_HOST_ARGS_FLAG_FROM_HOST) |
-		EC_HOST_ARGS_FLAG_TO_HOST;
+	lpc_host_args->flags = (host_cmd_flags & ~EC_HOST_ARGS_FLAG_FROM_HOST) |
+			       EC_HOST_ARGS_FLAG_TO_HOST;
 
 	lpc_host_args->data_size = size;
 
 	csum = args->command + lpc_host_args->flags +
-		lpc_host_args->command_version +
-		lpc_host_args->data_size;
+	       lpc_host_args->command_version + lpc_host_args->data_size;
 
 	for (i = 0, out = (uint8_t *)args->response; i < size; i++, out++)
 		csum += *out;
@@ -251,7 +249,7 @@ void lpc_update_host_event_status(void)
 
 	/* Copy host events to mapped memory */
 	*(host_event_t *)host_get_memmap(EC_MEMMAP_HOST_EVENTS) =
-				lpc_get_host_events();
+		lpc_get_host_events();
 
 	task_enable_irq(IT83XX_IRQ_PMC_IN);
 
@@ -390,7 +388,7 @@ void lpc_kbc_ibf_interrupt(void)
 {
 	if (lpc_keyboard_input_pending()) {
 		keyboard_host_write(IT83XX_KBC_KBHIDIR,
-			(IT83XX_KBC_KBHISR & 0x08) ? 1 : 0);
+				    (IT83XX_KBC_KBHISR & 0x08) ? 1 : 0);
 		/* bit7, write-1 clear IBF */
 		IT83XX_KBC_KBHICR |= BIT(7);
 		IT83XX_KBC_KBHICR &= ~BIT(7);
@@ -733,8 +731,7 @@ void lpcrst_interrupt(enum gpio_signal signal)
 		/* Store port 80 reset event */
 		port_80_write(PORT_80_EVENT_RESET);
 
-	CPRINTS("LPC RESET# %sasserted",
-		lpc_get_pltrst_asserted() ? "" : "de");
+	CPRINTS("LPC RESET# %sasserted", lpc_get_pltrst_asserted() ? "" : "de");
 }
 #endif
 
@@ -765,6 +762,5 @@ static enum ec_status lpc_get_protocol_info(struct host_cmd_handler_args *args)
 
 	return EC_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO,
-		lpc_get_protocol_info,
-		EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, lpc_get_protocol_info,
+		     EC_VER_MASK(0));
diff --git a/chip/it83xx/peci.c b/chip/it83xx/peci.c
index 07336eaaf6..e5f172ce80 100644
--- a/chip/it83xx/peci.c
+++ b/chip/it83xx/peci.c
@@ -1,10 +1,11 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* PECI interface for Chrome EC */
 
+#include "builtin/assert.h"
 #include "clock.h"
 #include "hooks.h"
 #include "peci.h"
@@ -14,22 +15,20 @@
 #include "task.h"
 
 enum peci_status {
-	PECI_STATUS_NO_ERR        = 0x00,
-	PECI_STATUS_HOBY          = 0x01,
-	PECI_STATUS_FINISH        = 0x02,
-	PECI_STATUS_RD_FCS_ERR    = 0x04,
-	PECI_STATUS_WR_FCS_ERR    = 0x08,
-	PECI_STATUS_EXTERR        = 0x20,
-	PECI_STATUS_BUSERR        = 0x40,
-	PECI_STATUS_RCV_ERRCODE   = 0x80,
-	PECI_STATUS_ERR_NEED_RST  = (PECI_STATUS_BUSERR | PECI_STATUS_EXTERR),
-	PECI_STATUS_ANY_ERR       = (PECI_STATUS_RCV_ERRCODE |
-					PECI_STATUS_BUSERR |
-					PECI_STATUS_EXTERR |
-					PECI_STATUS_WR_FCS_ERR |
-					PECI_STATUS_RD_FCS_ERR),
-	PECI_STATUS_ANY_BIT       = 0xFE,
-	PECI_STATUS_TIMEOUT       = 0xFF,
+	PECI_STATUS_NO_ERR = 0x00,
+	PECI_STATUS_HOBY = 0x01,
+	PECI_STATUS_FINISH = 0x02,
+	PECI_STATUS_RD_FCS_ERR = 0x04,
+	PECI_STATUS_WR_FCS_ERR = 0x08,
+	PECI_STATUS_EXTERR = 0x20,
+	PECI_STATUS_BUSERR = 0x40,
+	PECI_STATUS_RCV_ERRCODE = 0x80,
+	PECI_STATUS_ERR_NEED_RST = (PECI_STATUS_BUSERR | PECI_STATUS_EXTERR),
+	PECI_STATUS_ANY_ERR = (PECI_STATUS_RCV_ERRCODE | PECI_STATUS_BUSERR |
+			       PECI_STATUS_EXTERR | PECI_STATUS_WR_FCS_ERR |
+			       PECI_STATUS_RD_FCS_ERR),
+	PECI_STATUS_ANY_BIT = 0xFE,
+	PECI_STATUS_TIMEOUT = 0xFF,
 };
 
 static task_id_t peci_current_task;
@@ -106,10 +105,9 @@ int peci_transaction(struct peci_data *peci)
 		IT83XX_PECI_HOWRLR = 0x00;
 	} else {
 		if ((peci->cmd_code == PECI_CMD_WR_PKG_CFG) ||
-			(peci->cmd_code == PECI_CMD_WR_IAMSR) ||
-			(peci->cmd_code == PECI_CMD_WR_PCI_CFG) ||
-			(peci->cmd_code == PECI_CMD_WR_PCI_CFG_LOCAL)) {
-
+		    (peci->cmd_code == PECI_CMD_WR_IAMSR) ||
+		    (peci->cmd_code == PECI_CMD_WR_PCI_CFG) ||
+		    (peci->cmd_code == PECI_CMD_WR_PCI_CFG_LOCAL)) {
 			/* write length include Cmd Code + AW FCS */
 			IT83XX_PECI_HOWRLR = peci->w_len + 2;
 
@@ -157,17 +155,14 @@ int peci_transaction(struct peci_data *peci)
 	peci_current_task = TASK_ID_INVALID;
 
 	if (index < peci->timeout_us) {
-
 		status = IT83XX_PECI_HOSTAR;
 
 		/* any error */
 		if (IT83XX_PECI_HOSTAR & PECI_STATUS_ANY_ERR) {
-
 			if (IT83XX_PECI_HOSTAR & PECI_STATUS_ERR_NEED_RST)
 				peci_reset();
 
 		} else if (IT83XX_PECI_HOSTAR & PECI_STATUS_FINISH) {
-
 			/* The read data field of the PECI protocol. */
 			for (index = 0x00; index < peci->r_len; index++)
 				peci->r_buf[index] = IT83XX_PECI_HORDDR;
diff --git a/chip/it83xx/pwm.c b/chip/it83xx/pwm.c
index fda8dd23d6..07165dea77 100644
--- a/chip/it83xx/pwm.c
+++ b/chip/it83xx/pwm.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,28 +15,28 @@
 #include "math_util.h"
 
 #define PWM_CTRX_MIN 100
-#define PWM_EC_FREQ  8000000
+#define PWM_EC_FREQ 8000000
 
 const struct pwm_ctrl_t pwm_ctrl_regs[] = {
-	{ &IT83XX_PWM_DCR0, &IT83XX_PWM_PCSSGL, &IT83XX_GPIO_GPCRA0},
-	{ &IT83XX_PWM_DCR1, &IT83XX_PWM_PCSSGL, &IT83XX_GPIO_GPCRA1},
-	{ &IT83XX_PWM_DCR2, &IT83XX_PWM_PCSSGL, &IT83XX_GPIO_GPCRA2},
-	{ &IT83XX_PWM_DCR3, &IT83XX_PWM_PCSSGL, &IT83XX_GPIO_GPCRA3},
-	{ &IT83XX_PWM_DCR4, &IT83XX_PWM_PCSSGH, &IT83XX_GPIO_GPCRA4},
-	{ &IT83XX_PWM_DCR5, &IT83XX_PWM_PCSSGH, &IT83XX_GPIO_GPCRA5},
-	{ &IT83XX_PWM_DCR6, &IT83XX_PWM_PCSSGH, &IT83XX_GPIO_GPCRA6},
-	{ &IT83XX_PWM_DCR7, &IT83XX_PWM_PCSSGH, &IT83XX_GPIO_GPCRA7},
+	{ &IT83XX_PWM_DCR0, &IT83XX_PWM_PCSSGL, &IT83XX_GPIO_GPCRA0 },
+	{ &IT83XX_PWM_DCR1, &IT83XX_PWM_PCSSGL, &IT83XX_GPIO_GPCRA1 },
+	{ &IT83XX_PWM_DCR2, &IT83XX_PWM_PCSSGL, &IT83XX_GPIO_GPCRA2 },
+	{ &IT83XX_PWM_DCR3, &IT83XX_PWM_PCSSGL, &IT83XX_GPIO_GPCRA3 },
+	{ &IT83XX_PWM_DCR4, &IT83XX_PWM_PCSSGH, &IT83XX_GPIO_GPCRA4 },
+	{ &IT83XX_PWM_DCR5, &IT83XX_PWM_PCSSGH, &IT83XX_GPIO_GPCRA5 },
+	{ &IT83XX_PWM_DCR6, &IT83XX_PWM_PCSSGH, &IT83XX_GPIO_GPCRA6 },
+	{ &IT83XX_PWM_DCR7, &IT83XX_PWM_PCSSGH, &IT83XX_GPIO_GPCRA7 },
 };
 
 const struct pwm_ctrl_t2 pwm_clock_ctrl_regs[] = {
 	{ &IT83XX_PWM_CTR, &IT83XX_PWM_C0CPRS, &IT83XX_PWM_C0CPRS,
-		&IT83XX_PWM_PCFSR, 0x01},
+	  &IT83XX_PWM_PCFSR, 0x01 },
 	{ &IT83XX_PWM_CTR1, &IT83XX_PWM_C4CPRS, &IT83XX_PWM_C4MCPRS,
-		&IT83XX_PWM_PCFSR, 0x02},
+	  &IT83XX_PWM_PCFSR, 0x02 },
 	{ &IT83XX_PWM_CTR2, &IT83XX_PWM_C6CPRS, &IT83XX_PWM_C6MCPRS,
-		&IT83XX_PWM_PCFSR, 0x04},
+	  &IT83XX_PWM_PCFSR, 0x04 },
 	{ &IT83XX_PWM_CTR3, &IT83XX_PWM_C7CPRS, &IT83XX_PWM_C7MCPRS,
-		&IT83XX_PWM_PCFSR, 0x08},
+	  &IT83XX_PWM_PCFSR, 0x08 },
 };
 
 static int pwm_get_cycle_time(enum pwm_channel ch)
@@ -76,9 +76,10 @@ void pwm_enable(enum pwm_channel ch, int enabled)
 	if (enabled)
 		*pwm_ctrl_regs[pwm_reg_index].pwm_pin = 0x00;
 	else
-		*pwm_ctrl_regs[pwm_reg_index].pwm_pin = 0x80 |
-			((pwm_channels[ch].flags & PWM_CONFIG_ACTIVE_LOW) ?
-			4 : 2);
+		*pwm_ctrl_regs[pwm_reg_index].pwm_pin =
+			0x80 |
+			((pwm_channels[ch].flags & PWM_CONFIG_ACTIVE_LOW) ? 4 :
+									    2);
 }
 
 int pwm_get_enabled(enum pwm_channel ch)
@@ -88,7 +89,9 @@ int pwm_get_enabled(enum pwm_channel ch)
 
 	/* pin is PWM function and PWMs clock counter was enabled */
 	return ((*pwm_ctrl_regs[ch].pwm_pin & ~0x04) == 0x00 &&
-		IT83XX_PWM_ZTIER & 0x02) ? 1 : 0;
+		IT83XX_PWM_ZTIER & 0x02) ?
+		       1 :
+		       0;
 }
 
 void pwm_set_duty(enum pwm_channel ch, int percent)
@@ -202,7 +205,8 @@ static int pwm_ch_freq(enum pwm_channel ch)
 	int actual_freq = -1, targe_freq, deviation;
 	int pcfsr, ctr, pcfsr_sel, pcs_shift, pcs_mask;
 	int pwm_clk_src = (pwm_channels[ch].flags & PWM_CONFIG_DSLEEP) ?
-							32768 : PWM_EC_FREQ;
+				  32768 :
+				  PWM_EC_FREQ;
 
 	targe_freq = pwm_channels[ch].freq_hz;
 	deviation = (targe_freq / 100) + 1;
@@ -251,8 +255,8 @@ static int pwm_ch_freq(enum pwm_channel ch)
 		*pwm_ctrl_regs[ch].pwm_clock_source |= pcs_mask;
 
 		*pwm_clock_ctrl_regs[pcfsr_sel].pwm_cpr_lsb = pcfsr & 0xFF;
-		*pwm_clock_ctrl_regs[pcfsr_sel].pwm_cpr_msb =
-			(pcfsr >> 8) & 0xFF;
+		*pwm_clock_ctrl_regs[pcfsr_sel].pwm_cpr_msb = (pcfsr >> 8) &
+							      0xFF;
 	}
 
 	return actual_freq;
diff --git a/chip/it83xx/pwm_chip.h b/chip/it83xx/pwm_chip.h
index 4e8aba1c62..03435d03f6 100644
--- a/chip/it83xx/pwm_chip.h
+++ b/chip/it83xx/pwm_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h
index b752f012d8..025daeb61a 100644
--- a/chip/it83xx/registers.h
+++ b/chip/it83xx/registers.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -15,772 +15,772 @@
 
 /* IRQ numbers */
 /* Group 0 */
-#define IT83XX_IRQ_WKO20           1
-#define IT83XX_IRQ_KBC_OUT         2
-#define IT83XX_IRQ_PMC_OUT         3
-#define IT83XX_IRQ_SMB_D           4
-#define IT83XX_IRQ_WKINTAD         5
-#define IT83XX_IRQ_WKO23           6
-#define IT83XX_IRQ_PWM             7
+#define IT83XX_IRQ_WKO20 1
+#define IT83XX_IRQ_KBC_OUT 2
+#define IT83XX_IRQ_PMC_OUT 3
+#define IT83XX_IRQ_SMB_D 4
+#define IT83XX_IRQ_WKINTAD 5
+#define IT83XX_IRQ_WKO23 6
+#define IT83XX_IRQ_PWM 7
 /* Group 1 */
-#define IT83XX_IRQ_ADC             8
-#define IT83XX_IRQ_SMB_A           9
-#define IT83XX_IRQ_SMB_B          10
-#define IT83XX_IRQ_KB_MATRIX      11
-#define IT83XX_IRQ_WKO26          12
-#define IT83XX_IRQ_WKINTC         13
-#define IT83XX_IRQ_WKO25          14
-#define IT83XX_IRQ_CIR            15
+#define IT83XX_IRQ_ADC 8
+#define IT83XX_IRQ_SMB_A 9
+#define IT83XX_IRQ_SMB_B 10
+#define IT83XX_IRQ_KB_MATRIX 11
+#define IT83XX_IRQ_WKO26 12
+#define IT83XX_IRQ_WKINTC 13
+#define IT83XX_IRQ_WKO25 14
+#define IT83XX_IRQ_CIR 15
 /* Group 2 */
-#define IT83XX_IRQ_SMB_C          16
-#define IT83XX_IRQ_WKO24          17
-#define IT83XX_IRQ_PS2_2          18
-#define IT83XX_IRQ_PS2_1          19
-#define IT83XX_IRQ_PS2_0          20
-#define IT83XX_IRQ_WKO22          21
-#define IT83XX_IRQ_SMFI           22
-#define IT83XX_IRQ_USB            23
+#define IT83XX_IRQ_SMB_C 16
+#define IT83XX_IRQ_WKO24 17
+#define IT83XX_IRQ_PS2_2 18
+#define IT83XX_IRQ_PS2_1 19
+#define IT83XX_IRQ_PS2_0 20
+#define IT83XX_IRQ_WKO22 21
+#define IT83XX_IRQ_SMFI 22
+#define IT83XX_IRQ_USB 23
 /* Group 3 */
-#define IT83XX_IRQ_KBC_IN         24
-#define IT83XX_IRQ_PMC_IN         25
-#define IT83XX_IRQ_PMC2_OUT       26
-#define IT83XX_IRQ_PMC2_IN        27
-#define IT83XX_IRQ_GINT           28
-#define IT83XX_IRQ_EGPC           29
-#define IT83XX_IRQ_EXT_TIMER1     30
-#define IT83XX_IRQ_WKO21          31
+#define IT83XX_IRQ_KBC_IN 24
+#define IT83XX_IRQ_PMC_IN 25
+#define IT83XX_IRQ_PMC2_OUT 26
+#define IT83XX_IRQ_PMC2_IN 27
+#define IT83XX_IRQ_GINT 28
+#define IT83XX_IRQ_EGPC 29
+#define IT83XX_IRQ_EXT_TIMER1 30
+#define IT83XX_IRQ_WKO21 31
 /* Group 4 */
-#define IT83XX_IRQ_GPINT0         32
-#define IT83XX_IRQ_GPINT1         33
-#define IT83XX_IRQ_GPINT2         34
-#define IT83XX_IRQ_GPINT3         35
-#define IT83XX_IRQ_CIR_GPINT      36
-#define IT83XX_IRQ_SSPI           37
-#define IT83XX_IRQ_UART1          38
-#define IT83XX_IRQ_UART2          39
+#define IT83XX_IRQ_GPINT0 32
+#define IT83XX_IRQ_GPINT1 33
+#define IT83XX_IRQ_GPINT2 34
+#define IT83XX_IRQ_GPINT3 35
+#define IT83XX_IRQ_CIR_GPINT 36
+#define IT83XX_IRQ_SSPI 37
+#define IT83XX_IRQ_UART1 38
+#define IT83XX_IRQ_UART2 39
 /* Group 5 */
-#define IT83XX_IRQ_WKO50          40
-#define IT83XX_IRQ_WKO51          41
-#define IT83XX_IRQ_WKO52          42
-#define IT83XX_IRQ_WKO53          43
-#define IT83XX_IRQ_WKO54          44
-#define IT83XX_IRQ_WKO55          45
-#define IT83XX_IRQ_WKO56          46
-#define IT83XX_IRQ_WKO57          47
+#define IT83XX_IRQ_WKO50 40
+#define IT83XX_IRQ_WKO51 41
+#define IT83XX_IRQ_WKO52 42
+#define IT83XX_IRQ_WKO53 43
+#define IT83XX_IRQ_WKO54 44
+#define IT83XX_IRQ_WKO55 45
+#define IT83XX_IRQ_WKO56 46
+#define IT83XX_IRQ_WKO57 47
 /* Group 6 */
-#define IT83XX_IRQ_WKO60          48
-#define IT83XX_IRQ_WKO61          49
-#define IT83XX_IRQ_WKO62          50
-#define IT83XX_IRQ_WKO63          51
-#define IT83XX_IRQ_WKO64          52
-#define IT83XX_IRQ_WKO65          53
-#define IT83XX_IRQ_WKO66          54
-#define IT83XX_IRQ_WKO67          55
+#define IT83XX_IRQ_WKO60 48
+#define IT83XX_IRQ_WKO61 49
+#define IT83XX_IRQ_WKO62 50
+#define IT83XX_IRQ_WKO63 51
+#define IT83XX_IRQ_WKO64 52
+#define IT83XX_IRQ_WKO65 53
+#define IT83XX_IRQ_WKO66 54
+#define IT83XX_IRQ_WKO67 55
 /* Group 7 */
-#define IT83XX_IRQ_RTCT_ALARM1    56
-#define IT83XX_IRQ_RTCT_ALARM2    57
-#define IT83XX_IRQ_EXT_TIMER2     58
-#define IT83XX_IRQ_DEFERRED_SPI   59
-#define IT83XX_IRQ_TMR_A0         60
-#define IT83XX_IRQ_TMR_A1         61
-#define IT83XX_IRQ_TMR_B0         62
-#define IT83XX_IRQ_TMR_B1         63
+#define IT83XX_IRQ_RTCT_ALARM1 56
+#define IT83XX_IRQ_RTCT_ALARM2 57
+#define IT83XX_IRQ_EXT_TIMER2 58
+#define IT83XX_IRQ_DEFERRED_SPI 59
+#define IT83XX_IRQ_TMR_A0 60
+#define IT83XX_IRQ_TMR_A1 61
+#define IT83XX_IRQ_TMR_B0 62
+#define IT83XX_IRQ_TMR_B1 63
 /* Group 8 */
-#define IT83XX_IRQ_PMC2EX_OUT     64
-#define IT83XX_IRQ_PMC2EX_IN      65
-#define IT83XX_IRQ_PMC3_OUT       66
-#define IT83XX_IRQ_PMC3_IN        67
-#define IT83XX_IRQ_PMC4_OUT       68
-#define IT83XX_IRQ_PMC4_IN        69
-#define IT83XX_IRQ_I2BRAM         71
+#define IT83XX_IRQ_PMC2EX_OUT 64
+#define IT83XX_IRQ_PMC2EX_IN 65
+#define IT83XX_IRQ_PMC3_OUT 66
+#define IT83XX_IRQ_PMC3_IN 67
+#define IT83XX_IRQ_PMC4_OUT 68
+#define IT83XX_IRQ_PMC4_IN 69
+#define IT83XX_IRQ_I2BRAM 71
 /* Group 9 */
-#define IT83XX_IRQ_WKO70          72
-#define IT83XX_IRQ_WKO71          73
-#define IT83XX_IRQ_WKO72          74
-#define IT83XX_IRQ_WKO73          75
-#define IT83XX_IRQ_WKO74          76
-#define IT83XX_IRQ_WKO75          77
-#define IT83XX_IRQ_WKO76          78
-#define IT83XX_IRQ_WKO77          79
+#define IT83XX_IRQ_WKO70 72
+#define IT83XX_IRQ_WKO71 73
+#define IT83XX_IRQ_WKO72 74
+#define IT83XX_IRQ_WKO73 75
+#define IT83XX_IRQ_WKO74 76
+#define IT83XX_IRQ_WKO75 77
+#define IT83XX_IRQ_WKO76 78
+#define IT83XX_IRQ_WKO77 79
 /* Group 10 */
-#define IT83XX_IRQ_EXT_TMR8       80
+#define IT83XX_IRQ_EXT_TMR8 80
 #define IT83XX_IRQ_SMB_CLOCK_HELD 81
-#define IT83XX_IRQ_CEC            82
-#define IT83XX_IRQ_H2RAM_LPC      83
-#define IT83XX_IRQ_HW_KB_SCAN     84
-#define IT83XX_IRQ_WKO88          85
-#define IT83XX_IRQ_WKO89          86
-#define IT83XX_IRQ_WKO90          87
+#define IT83XX_IRQ_CEC 82
+#define IT83XX_IRQ_H2RAM_LPC 83
+#define IT83XX_IRQ_HW_KB_SCAN 84
+#define IT83XX_IRQ_WKO88 85
+#define IT83XX_IRQ_WKO89 86
+#define IT83XX_IRQ_WKO90 87
 /* Group 11 */
-#define IT83XX_IRQ_WKO80          88
-#define IT83XX_IRQ_WKO81          89
-#define IT83XX_IRQ_WKO82          90
-#define IT83XX_IRQ_WKO83          91
-#define IT83XX_IRQ_WKO84          92
-#define IT83XX_IRQ_WKO85          93
-#define IT83XX_IRQ_WKO86          94
-#define IT83XX_IRQ_WKO87          95
+#define IT83XX_IRQ_WKO80 88
+#define IT83XX_IRQ_WKO81 89
+#define IT83XX_IRQ_WKO82 90
+#define IT83XX_IRQ_WKO83 91
+#define IT83XX_IRQ_WKO84 92
+#define IT83XX_IRQ_WKO85 93
+#define IT83XX_IRQ_WKO86 94
+#define IT83XX_IRQ_WKO87 95
 /* Group 12 */
-#define IT83XX_IRQ_WKO91          96
-#define IT83XX_IRQ_WKO92          97
-#define IT83XX_IRQ_WKO93          98
-#define IT83XX_IRQ_WKO94          99
-#define IT83XX_IRQ_WKO95          100
-#define IT83XX_IRQ_WKO96          101
-#define IT83XX_IRQ_WKO97          102
-#define IT83XX_IRQ_WKO98          103
+#define IT83XX_IRQ_WKO91 96
+#define IT83XX_IRQ_WKO92 97
+#define IT83XX_IRQ_WKO93 98
+#define IT83XX_IRQ_WKO94 99
+#define IT83XX_IRQ_WKO95 100
+#define IT83XX_IRQ_WKO96 101
+#define IT83XX_IRQ_WKO97 102
+#define IT83XX_IRQ_WKO98 103
 /* Group 13 */
-#define IT83XX_IRQ_WKO99          104
-#define IT83XX_IRQ_WKO100         105
-#define IT83XX_IRQ_WKO101         106
-#define IT83XX_IRQ_WKO102         107
-#define IT83XX_IRQ_WKO103         108
-#define IT83XX_IRQ_WKO104         109
-#define IT83XX_IRQ_WKO105         110
-#define IT83XX_IRQ_WKO106         111
+#define IT83XX_IRQ_WKO99 104
+#define IT83XX_IRQ_WKO100 105
+#define IT83XX_IRQ_WKO101 106
+#define IT83XX_IRQ_WKO102 107
+#define IT83XX_IRQ_WKO103 108
+#define IT83XX_IRQ_WKO104 109
+#define IT83XX_IRQ_WKO105 110
+#define IT83XX_IRQ_WKO106 111
 /* Group 14 */
-#define IT83XX_IRQ_WKO107         112
-#define IT83XX_IRQ_WKO108         113
-#define IT83XX_IRQ_WKO109         114
-#define IT83XX_IRQ_WKO110         115
-#define IT83XX_IRQ_WKO111         116
-#define IT83XX_IRQ_WKO112         117
-#define IT83XX_IRQ_WKO113         118
-#define IT83XX_IRQ_WKO114         119
+#define IT83XX_IRQ_WKO107 112
+#define IT83XX_IRQ_WKO108 113
+#define IT83XX_IRQ_WKO109 114
+#define IT83XX_IRQ_WKO110 115
+#define IT83XX_IRQ_WKO111 116
+#define IT83XX_IRQ_WKO112 117
+#define IT83XX_IRQ_WKO113 118
+#define IT83XX_IRQ_WKO114 119
 /* Group 15 */
-#define IT83XX_IRQ_WKO115         120
-#define IT83XX_IRQ_WKO116         121
-#define IT83XX_IRQ_WKO117         122
-#define IT83XX_IRQ_WKO118         123
-#define IT83XX_IRQ_WKO119         124
-#define IT83XX_IRQ_WKO120         125
-#define IT83XX_IRQ_WKO121         126
-#define IT83XX_IRQ_WKO122         127
+#define IT83XX_IRQ_WKO115 120
+#define IT83XX_IRQ_WKO116 121
+#define IT83XX_IRQ_WKO117 122
+#define IT83XX_IRQ_WKO118 123
+#define IT83XX_IRQ_WKO119 124
+#define IT83XX_IRQ_WKO120 125
+#define IT83XX_IRQ_WKO121 126
+#define IT83XX_IRQ_WKO122 127
 /* Group 16 */
-#define IT83XX_IRQ_WKO128         128
-#define IT83XX_IRQ_WKO129         129
-#define IT83XX_IRQ_WKO130         130
-#define IT83XX_IRQ_WKO131         131
-#define IT83XX_IRQ_WKO132         132
-#define IT83XX_IRQ_WKO133         133
-#define IT83XX_IRQ_WKO134         134
-#define IT83XX_IRQ_WKO135         135
+#define IT83XX_IRQ_WKO128 128
+#define IT83XX_IRQ_WKO129 129
+#define IT83XX_IRQ_WKO130 130
+#define IT83XX_IRQ_WKO131 131
+#define IT83XX_IRQ_WKO132 132
+#define IT83XX_IRQ_WKO133 133
+#define IT83XX_IRQ_WKO134 134
+#define IT83XX_IRQ_WKO135 135
 /* Group 17 */
-#define IT83XX_IRQ_WKO136         136
-#define IT83XX_IRQ_WKO137         137
-#define IT83XX_IRQ_WKO138         138
-#define IT83XX_IRQ_WKO139         139
-#define IT83XX_IRQ_WKO140         140
-#define IT83XX_IRQ_WKO141         141
-#define IT83XX_IRQ_WKO142         142
-#define IT83XX_IRQ_WKO143         143
+#define IT83XX_IRQ_WKO136 136
+#define IT83XX_IRQ_WKO137 137
+#define IT83XX_IRQ_WKO138 138
+#define IT83XX_IRQ_WKO139 139
+#define IT83XX_IRQ_WKO140 140
+#define IT83XX_IRQ_WKO141 141
+#define IT83XX_IRQ_WKO142 142
+#define IT83XX_IRQ_WKO143 143
 /* Group 18 */
-#define IT83XX_IRQ_WKO123         144
-#define IT83XX_IRQ_WKO124         145
-#define IT83XX_IRQ_WKO125         146
-#define IT83XX_IRQ_WKO126         147
-#define IT83XX_IRQ_PMC5_OUT       149
-#define IT83XX_IRQ_PMC5_IN        150
-#define IT83XX_IRQ_V_COMP         151
+#define IT83XX_IRQ_WKO123 144
+#define IT83XX_IRQ_WKO124 145
+#define IT83XX_IRQ_WKO125 146
+#define IT83XX_IRQ_WKO126 147
+#define IT83XX_IRQ_PMC5_OUT 149
+#define IT83XX_IRQ_PMC5_IN 150
+#define IT83XX_IRQ_V_COMP 151
 /* Group 19 */
-#define IT83XX_IRQ_SMB_E          152
-#define IT83XX_IRQ_SMB_F          153
-#define IT83XX_IRQ_OSC_DMA        154
-#define IT83XX_IRQ_EXT_TIMER3     155
-#define IT83XX_IRQ_EXT_TIMER4     156
-#define IT83XX_IRQ_EXT_TIMER5     157
-#define IT83XX_IRQ_EXT_TIMER6     158
-#define IT83XX_IRQ_EXT_TIMER7     159
+#define IT83XX_IRQ_SMB_E 152
+#define IT83XX_IRQ_SMB_F 153
+#define IT83XX_IRQ_OSC_DMA 154
+#define IT83XX_IRQ_EXT_TIMER3 155
+#define IT83XX_IRQ_EXT_TIMER4 156
+#define IT83XX_IRQ_EXT_TIMER5 157
+#define IT83XX_IRQ_EXT_TIMER6 158
+#define IT83XX_IRQ_EXT_TIMER7 159
 /* Group 20 */
-#define IT83XX_IRQ_PECI           160
-#define IT83XX_IRQ_SOFTWARE       161
-#define IT83XX_IRQ_ESPI           162
-#define IT83XX_IRQ_ESPI_VW        163
-#define IT83XX_IRQ_PCH_P80        164
-#define IT83XX_IRQ_USBPD0         165
-#define IT83XX_IRQ_USBPD1         166
+#define IT83XX_IRQ_PECI 160
+#define IT83XX_IRQ_SOFTWARE 161
+#define IT83XX_IRQ_ESPI 162
+#define IT83XX_IRQ_ESPI_VW 163
+#define IT83XX_IRQ_PCH_P80 164
+#define IT83XX_IRQ_USBPD0 165
+#define IT83XX_IRQ_USBPD1 166
 /* Group 21 */
 #if defined(CHIP_FAMILY_IT8320)
-#define IT83XX_IRQ_WKO40          168
-#define IT83XX_IRQ_WKO45          169
-#define IT83XX_IRQ_WKO46          170
-#define IT83XX_IRQ_WKO144         171
-#define IT83XX_IRQ_WKO145         172
-#define IT83XX_IRQ_WKO146         173
-#define IT83XX_IRQ_WKO147         174
-#define IT83XX_IRQ_WKO148         175
+#define IT83XX_IRQ_WKO40 168
+#define IT83XX_IRQ_WKO45 169
+#define IT83XX_IRQ_WKO46 170
+#define IT83XX_IRQ_WKO144 171
+#define IT83XX_IRQ_WKO145 172
+#define IT83XX_IRQ_WKO146 173
+#define IT83XX_IRQ_WKO147 174
+#define IT83XX_IRQ_WKO148 175
 /* Group 22 */
-#define IT83XX_IRQ_WKO149         176
-#define IT83XX_IRQ_WKO150         177
+#define IT83XX_IRQ_WKO149 176
+#define IT83XX_IRQ_WKO150 177
 
-#define IT83XX_IRQ_COUNT          178
+#define IT83XX_IRQ_COUNT 178
 #elif defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2)
 /* Group 21 */
-#define IT83XX_IRQ_AUDIO_IF       170
+#define IT83XX_IRQ_AUDIO_IF 170
 #define IT83XX_IRQ_SPI_PERIPHERAL 171
-#define IT83XX_IRQ_DSP_ENGINE     172
-#define IT83XX_IRQ_NN_ENGINE      173
-#define IT83XX_IRQ_USBPD2         174
-#define IT83XX_IRQ_CRYPTO         175
+#define IT83XX_IRQ_DSP_ENGINE 172
+#define IT83XX_IRQ_NN_ENGINE 173
+#define IT83XX_IRQ_USBPD2 174
+#define IT83XX_IRQ_CRYPTO 175
 /* Group 22 */
-#define IT83XX_IRQ_WKO40          176
-#define IT83XX_IRQ_WKO45          177
-#define IT83XX_IRQ_WKO46          178
-#define IT83XX_IRQ_WKO144         179
-#define IT83XX_IRQ_WKO145         180
-#define IT83XX_IRQ_WKO146         181
-#define IT83XX_IRQ_WKO147         182
-#define IT83XX_IRQ_WKO148         183
+#define IT83XX_IRQ_WKO40 176
+#define IT83XX_IRQ_WKO45 177
+#define IT83XX_IRQ_WKO46 178
+#define IT83XX_IRQ_WKO144 179
+#define IT83XX_IRQ_WKO145 180
+#define IT83XX_IRQ_WKO146 181
+#define IT83XX_IRQ_WKO147 182
+#define IT83XX_IRQ_WKO148 183
 /* Group 23 */
-#define IT83XX_IRQ_WKO149         184
-#define IT83XX_IRQ_WKO150         185
-#define IT83XX_IRQ_SSPI1          191
+#define IT83XX_IRQ_WKO149 184
+#define IT83XX_IRQ_WKO150 185
+#define IT83XX_IRQ_SSPI1 191
 /* Group 24 */
-#define IT83XX_IRQ_XLPIN0         192
-#define IT83XX_IRQ_XLPIN1         193
-#define IT83XX_IRQ_XLPIN2         194
-#define IT83XX_IRQ_XLPIN3         195
-#define IT83XX_IRQ_XLPIN4         196
-#define IT83XX_IRQ_XLPIN5         197
-#define IT83XX_IRQ_WEEK_ALARM     199
+#define IT83XX_IRQ_XLPIN0 192
+#define IT83XX_IRQ_XLPIN1 193
+#define IT83XX_IRQ_XLPIN2 194
+#define IT83XX_IRQ_XLPIN3 195
+#define IT83XX_IRQ_XLPIN4 196
+#define IT83XX_IRQ_XLPIN5 197
+#define IT83XX_IRQ_WEEK_ALARM 199
 /* Group 25 */
-#define IT83XX_IRQ_GPO0           200
-#define IT83XX_IRQ_GPO1           201
-#define IT83XX_IRQ_GPO2           202
-#define IT83XX_IRQ_GPO3           203
+#define IT83XX_IRQ_GPO0 200
+#define IT83XX_IRQ_GPO1 201
+#define IT83XX_IRQ_GPO2 202
+#define IT83XX_IRQ_GPO3 203
 /* Group 26 */
-#define IT83XX_IRQ_GPP0           208
-#define IT83XX_IRQ_GPP1           209
-#define IT83XX_IRQ_GPP2           210
-#define IT83XX_IRQ_GPP3           211
-#define IT83XX_IRQ_GPP4           212
-#define IT83XX_IRQ_GPP5           213
-#define IT83XX_IRQ_GPP6           214
+#define IT83XX_IRQ_GPP0 208
+#define IT83XX_IRQ_GPP1 209
+#define IT83XX_IRQ_GPP2 210
+#define IT83XX_IRQ_GPP3 211
+#define IT83XX_IRQ_GPP4 212
+#define IT83XX_IRQ_GPP5 213
+#define IT83XX_IRQ_GPP6 214
 /* Group 27 */
-#define IT83XX_IRQ_GPQ0           216
-#define IT83XX_IRQ_GPQ1           217
-#define IT83XX_IRQ_GPQ2           218
-#define IT83XX_IRQ_GPQ3           219
-#define IT83XX_IRQ_GPQ4           220
-#define IT83XX_IRQ_GPQ5           221
+#define IT83XX_IRQ_GPQ0 216
+#define IT83XX_IRQ_GPQ1 217
+#define IT83XX_IRQ_GPQ2 218
+#define IT83XX_IRQ_GPQ3 219
+#define IT83XX_IRQ_GPQ4 220
+#define IT83XX_IRQ_GPQ5 221
 /* Group 28 */
-#define IT83XX_IRQ_GPR0           224
-#define IT83XX_IRQ_GPR1           225
-#define IT83XX_IRQ_GPR2           226
-#define IT83XX_IRQ_GPR3           227
-#define IT83XX_IRQ_GPR4           228
-#define IT83XX_IRQ_GPR5           229
-
-#define IT83XX_IRQ_COUNT          230
+#define IT83XX_IRQ_GPR0 224
+#define IT83XX_IRQ_GPR1 225
+#define IT83XX_IRQ_GPR2 226
+#define IT83XX_IRQ_GPR3 227
+#define IT83XX_IRQ_GPR4 228
+#define IT83XX_IRQ_GPR5 229
+
+#define IT83XX_IRQ_COUNT 230
 #endif /* !defined(CHIP_FAMILY_IT8320) */
 
 /* IRQ dispatching to CPU INT vectors */
-#define IT83XX_CPU_INT_IRQ_1       2
-#define IT83XX_CPU_INT_IRQ_2       5
-#define IT83XX_CPU_INT_IRQ_3       4
-#define IT83XX_CPU_INT_IRQ_4       6
-#define IT83XX_CPU_INT_IRQ_5       2
-#define IT83XX_CPU_INT_IRQ_6       2
-#define IT83XX_CPU_INT_IRQ_7       4
-#define IT83XX_CPU_INT_IRQ_8       7
-#define IT83XX_CPU_INT_IRQ_9       6
-#define IT83XX_CPU_INT_IRQ_10      6
-#define IT83XX_CPU_INT_IRQ_11      5
-#define IT83XX_CPU_INT_IRQ_12      2
-#define IT83XX_CPU_INT_IRQ_13      2
-#define IT83XX_CPU_INT_IRQ_14      2
-#define IT83XX_CPU_INT_IRQ_15      8
-#define IT83XX_CPU_INT_IRQ_16      6
-#define IT83XX_CPU_INT_IRQ_17      2
-#define IT83XX_CPU_INT_IRQ_18      8
-#define IT83XX_CPU_INT_IRQ_19      8
-#define IT83XX_CPU_INT_IRQ_20      8
-#define IT83XX_CPU_INT_IRQ_21      2
-#define IT83XX_CPU_INT_IRQ_22     12
-#define IT83XX_CPU_INT_IRQ_23     12
-#define IT83XX_CPU_INT_IRQ_24      5
-#define IT83XX_CPU_INT_IRQ_25      4
-#define IT83XX_CPU_INT_IRQ_26      4
-#define IT83XX_CPU_INT_IRQ_27      4
-#define IT83XX_CPU_INT_IRQ_28     11
-#define IT83XX_CPU_INT_IRQ_29     11
-#define IT83XX_CPU_INT_IRQ_30      3
-#define IT83XX_CPU_INT_IRQ_31      2
-#define IT83XX_CPU_INT_IRQ_32     11
-#define IT83XX_CPU_INT_IRQ_33     11
-#define IT83XX_CPU_INT_IRQ_34     11
-#define IT83XX_CPU_INT_IRQ_35     11
-#define IT83XX_CPU_INT_IRQ_36      8
-#define IT83XX_CPU_INT_IRQ_37      9
-#define IT83XX_CPU_INT_IRQ_38      9
-#define IT83XX_CPU_INT_IRQ_39      9
-#define IT83XX_CPU_INT_IRQ_40      2
-#define IT83XX_CPU_INT_IRQ_41      2
-#define IT83XX_CPU_INT_IRQ_42      2
-#define IT83XX_CPU_INT_IRQ_43      2
-#define IT83XX_CPU_INT_IRQ_44      2
-#define IT83XX_CPU_INT_IRQ_45      2
-#define IT83XX_CPU_INT_IRQ_46      2
-#define IT83XX_CPU_INT_IRQ_47      2
-#define IT83XX_CPU_INT_IRQ_48      2
-#define IT83XX_CPU_INT_IRQ_49      2
-#define IT83XX_CPU_INT_IRQ_50      2
-#define IT83XX_CPU_INT_IRQ_51      2
-#define IT83XX_CPU_INT_IRQ_52      2
-#define IT83XX_CPU_INT_IRQ_53      2
-#define IT83XX_CPU_INT_IRQ_54      2
-#define IT83XX_CPU_INT_IRQ_55      2
-#define IT83XX_CPU_INT_IRQ_56     10
-#define IT83XX_CPU_INT_IRQ_57     10
-#define IT83XX_CPU_INT_IRQ_58      3
-#define IT83XX_CPU_INT_IRQ_59     12
-#define IT83XX_CPU_INT_IRQ_60      3
-#define IT83XX_CPU_INT_IRQ_61      3
-#define IT83XX_CPU_INT_IRQ_62      3
-#define IT83XX_CPU_INT_IRQ_63      3
-#define IT83XX_CPU_INT_IRQ_64      4
-#define IT83XX_CPU_INT_IRQ_65      4
-#define IT83XX_CPU_INT_IRQ_66      4
-#define IT83XX_CPU_INT_IRQ_67      4
-#define IT83XX_CPU_INT_IRQ_68      4
-#define IT83XX_CPU_INT_IRQ_69      4
-#define IT83XX_CPU_INT_IRQ_71     12
-#define IT83XX_CPU_INT_IRQ_72      2
-#define IT83XX_CPU_INT_IRQ_73      2
-#define IT83XX_CPU_INT_IRQ_74      2
-#define IT83XX_CPU_INT_IRQ_75      2
-#define IT83XX_CPU_INT_IRQ_76      2
-#define IT83XX_CPU_INT_IRQ_77      2
-#define IT83XX_CPU_INT_IRQ_78      2
-#define IT83XX_CPU_INT_IRQ_79      2
-#define IT83XX_CPU_INT_IRQ_80      3
-#define IT83XX_CPU_INT_IRQ_81      6
-#define IT83XX_CPU_INT_IRQ_82     12
-#define IT83XX_CPU_INT_IRQ_83     12
-#define IT83XX_CPU_INT_IRQ_84      5
-#define IT83XX_CPU_INT_IRQ_85      2
-#define IT83XX_CPU_INT_IRQ_86      2
-#define IT83XX_CPU_INT_IRQ_87      2
-#define IT83XX_CPU_INT_IRQ_88      2
-#define IT83XX_CPU_INT_IRQ_89      2
-#define IT83XX_CPU_INT_IRQ_90      2
-#define IT83XX_CPU_INT_IRQ_91      2
-#define IT83XX_CPU_INT_IRQ_92      2
-#define IT83XX_CPU_INT_IRQ_93      2
-#define IT83XX_CPU_INT_IRQ_94      2
-#define IT83XX_CPU_INT_IRQ_95      2
-#define IT83XX_CPU_INT_IRQ_96      2
-#define IT83XX_CPU_INT_IRQ_97      2
-#define IT83XX_CPU_INT_IRQ_98      2
-#define IT83XX_CPU_INT_IRQ_99      2
-#define IT83XX_CPU_INT_IRQ_100     2
-#define IT83XX_CPU_INT_IRQ_101     2
-#define IT83XX_CPU_INT_IRQ_102     2
-#define IT83XX_CPU_INT_IRQ_103     2
-#define IT83XX_CPU_INT_IRQ_104     2
-#define IT83XX_CPU_INT_IRQ_105     2
-#define IT83XX_CPU_INT_IRQ_106     2
-#define IT83XX_CPU_INT_IRQ_107     2
-#define IT83XX_CPU_INT_IRQ_108     2
-#define IT83XX_CPU_INT_IRQ_109     2
-#define IT83XX_CPU_INT_IRQ_110     2
-#define IT83XX_CPU_INT_IRQ_111     2
-#define IT83XX_CPU_INT_IRQ_112     2
-#define IT83XX_CPU_INT_IRQ_113     2
-#define IT83XX_CPU_INT_IRQ_114     2
-#define IT83XX_CPU_INT_IRQ_115     2
-#define IT83XX_CPU_INT_IRQ_116     2
-#define IT83XX_CPU_INT_IRQ_117     2
-#define IT83XX_CPU_INT_IRQ_118     2
-#define IT83XX_CPU_INT_IRQ_119     2
-#define IT83XX_CPU_INT_IRQ_120     2
-#define IT83XX_CPU_INT_IRQ_121     2
-#define IT83XX_CPU_INT_IRQ_122     2
-#define IT83XX_CPU_INT_IRQ_123     2
-#define IT83XX_CPU_INT_IRQ_124     2
-#define IT83XX_CPU_INT_IRQ_125     2
-#define IT83XX_CPU_INT_IRQ_126     2
-#define IT83XX_CPU_INT_IRQ_127     2
-#define IT83XX_CPU_INT_IRQ_128     2
-#define IT83XX_CPU_INT_IRQ_129     2
-#define IT83XX_CPU_INT_IRQ_130     2
-#define IT83XX_CPU_INT_IRQ_131     2
-#define IT83XX_CPU_INT_IRQ_132     2
-#define IT83XX_CPU_INT_IRQ_133     2
-#define IT83XX_CPU_INT_IRQ_134     2
-#define IT83XX_CPU_INT_IRQ_135     2
-#define IT83XX_CPU_INT_IRQ_136     2
-#define IT83XX_CPU_INT_IRQ_137     2
-#define IT83XX_CPU_INT_IRQ_138     2
-#define IT83XX_CPU_INT_IRQ_139     2
-#define IT83XX_CPU_INT_IRQ_140     2
-#define IT83XX_CPU_INT_IRQ_141     2
-#define IT83XX_CPU_INT_IRQ_142     2
-#define IT83XX_CPU_INT_IRQ_143     2
-#define IT83XX_CPU_INT_IRQ_144     2
-#define IT83XX_CPU_INT_IRQ_145     2
-#define IT83XX_CPU_INT_IRQ_146     2
-#define IT83XX_CPU_INT_IRQ_147     2
-#define IT83XX_CPU_INT_IRQ_149     4
-#define IT83XX_CPU_INT_IRQ_150     4
-#define IT83XX_CPU_INT_IRQ_151     7
-#define IT83XX_CPU_INT_IRQ_152     6
-#define IT83XX_CPU_INT_IRQ_153     6
-#define IT83XX_CPU_INT_IRQ_154    12
-#define IT83XX_CPU_INT_IRQ_155     3
-#define IT83XX_CPU_INT_IRQ_156     3
-#define IT83XX_CPU_INT_IRQ_157     3
-#define IT83XX_CPU_INT_IRQ_158     3
-#define IT83XX_CPU_INT_IRQ_159     3
-#define IT83XX_CPU_INT_IRQ_160    12
-#define IT83XX_CPU_INT_IRQ_161    12
-#define IT83XX_CPU_INT_IRQ_162    12
-#define IT83XX_CPU_INT_IRQ_163    12
-#define IT83XX_CPU_INT_IRQ_164    12
-#define IT83XX_CPU_INT_IRQ_165    12
-#define IT83XX_CPU_INT_IRQ_166    12
-#define IT83XX_CPU_INT_IRQ_167    12
-#define IT83XX_CPU_INT_IRQ_168     2
-#define IT83XX_CPU_INT_IRQ_169     2
+#define IT83XX_CPU_INT_IRQ_1 2
+#define IT83XX_CPU_INT_IRQ_2 5
+#define IT83XX_CPU_INT_IRQ_3 4
+#define IT83XX_CPU_INT_IRQ_4 6
+#define IT83XX_CPU_INT_IRQ_5 2
+#define IT83XX_CPU_INT_IRQ_6 2
+#define IT83XX_CPU_INT_IRQ_7 4
+#define IT83XX_CPU_INT_IRQ_8 7
+#define IT83XX_CPU_INT_IRQ_9 6
+#define IT83XX_CPU_INT_IRQ_10 6
+#define IT83XX_CPU_INT_IRQ_11 5
+#define IT83XX_CPU_INT_IRQ_12 2
+#define IT83XX_CPU_INT_IRQ_13 2
+#define IT83XX_CPU_INT_IRQ_14 2
+#define IT83XX_CPU_INT_IRQ_15 8
+#define IT83XX_CPU_INT_IRQ_16 6
+#define IT83XX_CPU_INT_IRQ_17 2
+#define IT83XX_CPU_INT_IRQ_18 8
+#define IT83XX_CPU_INT_IRQ_19 8
+#define IT83XX_CPU_INT_IRQ_20 8
+#define IT83XX_CPU_INT_IRQ_21 2
+#define IT83XX_CPU_INT_IRQ_22 12
+#define IT83XX_CPU_INT_IRQ_23 12
+#define IT83XX_CPU_INT_IRQ_24 5
+#define IT83XX_CPU_INT_IRQ_25 4
+#define IT83XX_CPU_INT_IRQ_26 4
+#define IT83XX_CPU_INT_IRQ_27 4
+#define IT83XX_CPU_INT_IRQ_28 11
+#define IT83XX_CPU_INT_IRQ_29 11
+#define IT83XX_CPU_INT_IRQ_30 3
+#define IT83XX_CPU_INT_IRQ_31 2
+#define IT83XX_CPU_INT_IRQ_32 11
+#define IT83XX_CPU_INT_IRQ_33 11
+#define IT83XX_CPU_INT_IRQ_34 11
+#define IT83XX_CPU_INT_IRQ_35 11
+#define IT83XX_CPU_INT_IRQ_36 8
+#define IT83XX_CPU_INT_IRQ_37 9
+#define IT83XX_CPU_INT_IRQ_38 9
+#define IT83XX_CPU_INT_IRQ_39 9
+#define IT83XX_CPU_INT_IRQ_40 2
+#define IT83XX_CPU_INT_IRQ_41 2
+#define IT83XX_CPU_INT_IRQ_42 2
+#define IT83XX_CPU_INT_IRQ_43 2
+#define IT83XX_CPU_INT_IRQ_44 2
+#define IT83XX_CPU_INT_IRQ_45 2
+#define IT83XX_CPU_INT_IRQ_46 2
+#define IT83XX_CPU_INT_IRQ_47 2
+#define IT83XX_CPU_INT_IRQ_48 2
+#define IT83XX_CPU_INT_IRQ_49 2
+#define IT83XX_CPU_INT_IRQ_50 2
+#define IT83XX_CPU_INT_IRQ_51 2
+#define IT83XX_CPU_INT_IRQ_52 2
+#define IT83XX_CPU_INT_IRQ_53 2
+#define IT83XX_CPU_INT_IRQ_54 2
+#define IT83XX_CPU_INT_IRQ_55 2
+#define IT83XX_CPU_INT_IRQ_56 10
+#define IT83XX_CPU_INT_IRQ_57 10
+#define IT83XX_CPU_INT_IRQ_58 3
+#define IT83XX_CPU_INT_IRQ_59 12
+#define IT83XX_CPU_INT_IRQ_60 3
+#define IT83XX_CPU_INT_IRQ_61 3
+#define IT83XX_CPU_INT_IRQ_62 3
+#define IT83XX_CPU_INT_IRQ_63 3
+#define IT83XX_CPU_INT_IRQ_64 4
+#define IT83XX_CPU_INT_IRQ_65 4
+#define IT83XX_CPU_INT_IRQ_66 4
+#define IT83XX_CPU_INT_IRQ_67 4
+#define IT83XX_CPU_INT_IRQ_68 4
+#define IT83XX_CPU_INT_IRQ_69 4
+#define IT83XX_CPU_INT_IRQ_71 12
+#define IT83XX_CPU_INT_IRQ_72 2
+#define IT83XX_CPU_INT_IRQ_73 2
+#define IT83XX_CPU_INT_IRQ_74 2
+#define IT83XX_CPU_INT_IRQ_75 2
+#define IT83XX_CPU_INT_IRQ_76 2
+#define IT83XX_CPU_INT_IRQ_77 2
+#define IT83XX_CPU_INT_IRQ_78 2
+#define IT83XX_CPU_INT_IRQ_79 2
+#define IT83XX_CPU_INT_IRQ_80 3
+#define IT83XX_CPU_INT_IRQ_81 6
+#define IT83XX_CPU_INT_IRQ_82 12
+#define IT83XX_CPU_INT_IRQ_83 12
+#define IT83XX_CPU_INT_IRQ_84 5
+#define IT83XX_CPU_INT_IRQ_85 2
+#define IT83XX_CPU_INT_IRQ_86 2
+#define IT83XX_CPU_INT_IRQ_87 2
+#define IT83XX_CPU_INT_IRQ_88 2
+#define IT83XX_CPU_INT_IRQ_89 2
+#define IT83XX_CPU_INT_IRQ_90 2
+#define IT83XX_CPU_INT_IRQ_91 2
+#define IT83XX_CPU_INT_IRQ_92 2
+#define IT83XX_CPU_INT_IRQ_93 2
+#define IT83XX_CPU_INT_IRQ_94 2
+#define IT83XX_CPU_INT_IRQ_95 2
+#define IT83XX_CPU_INT_IRQ_96 2
+#define IT83XX_CPU_INT_IRQ_97 2
+#define IT83XX_CPU_INT_IRQ_98 2
+#define IT83XX_CPU_INT_IRQ_99 2
+#define IT83XX_CPU_INT_IRQ_100 2
+#define IT83XX_CPU_INT_IRQ_101 2
+#define IT83XX_CPU_INT_IRQ_102 2
+#define IT83XX_CPU_INT_IRQ_103 2
+#define IT83XX_CPU_INT_IRQ_104 2
+#define IT83XX_CPU_INT_IRQ_105 2
+#define IT83XX_CPU_INT_IRQ_106 2
+#define IT83XX_CPU_INT_IRQ_107 2
+#define IT83XX_CPU_INT_IRQ_108 2
+#define IT83XX_CPU_INT_IRQ_109 2
+#define IT83XX_CPU_INT_IRQ_110 2
+#define IT83XX_CPU_INT_IRQ_111 2
+#define IT83XX_CPU_INT_IRQ_112 2
+#define IT83XX_CPU_INT_IRQ_113 2
+#define IT83XX_CPU_INT_IRQ_114 2
+#define IT83XX_CPU_INT_IRQ_115 2
+#define IT83XX_CPU_INT_IRQ_116 2
+#define IT83XX_CPU_INT_IRQ_117 2
+#define IT83XX_CPU_INT_IRQ_118 2
+#define IT83XX_CPU_INT_IRQ_119 2
+#define IT83XX_CPU_INT_IRQ_120 2
+#define IT83XX_CPU_INT_IRQ_121 2
+#define IT83XX_CPU_INT_IRQ_122 2
+#define IT83XX_CPU_INT_IRQ_123 2
+#define IT83XX_CPU_INT_IRQ_124 2
+#define IT83XX_CPU_INT_IRQ_125 2
+#define IT83XX_CPU_INT_IRQ_126 2
+#define IT83XX_CPU_INT_IRQ_127 2
+#define IT83XX_CPU_INT_IRQ_128 2
+#define IT83XX_CPU_INT_IRQ_129 2
+#define IT83XX_CPU_INT_IRQ_130 2
+#define IT83XX_CPU_INT_IRQ_131 2
+#define IT83XX_CPU_INT_IRQ_132 2
+#define IT83XX_CPU_INT_IRQ_133 2
+#define IT83XX_CPU_INT_IRQ_134 2
+#define IT83XX_CPU_INT_IRQ_135 2
+#define IT83XX_CPU_INT_IRQ_136 2
+#define IT83XX_CPU_INT_IRQ_137 2
+#define IT83XX_CPU_INT_IRQ_138 2
+#define IT83XX_CPU_INT_IRQ_139 2
+#define IT83XX_CPU_INT_IRQ_140 2
+#define IT83XX_CPU_INT_IRQ_141 2
+#define IT83XX_CPU_INT_IRQ_142 2
+#define IT83XX_CPU_INT_IRQ_143 2
+#define IT83XX_CPU_INT_IRQ_144 2
+#define IT83XX_CPU_INT_IRQ_145 2
+#define IT83XX_CPU_INT_IRQ_146 2
+#define IT83XX_CPU_INT_IRQ_147 2
+#define IT83XX_CPU_INT_IRQ_149 4
+#define IT83XX_CPU_INT_IRQ_150 4
+#define IT83XX_CPU_INT_IRQ_151 7
+#define IT83XX_CPU_INT_IRQ_152 6
+#define IT83XX_CPU_INT_IRQ_153 6
+#define IT83XX_CPU_INT_IRQ_154 12
+#define IT83XX_CPU_INT_IRQ_155 3
+#define IT83XX_CPU_INT_IRQ_156 3
+#define IT83XX_CPU_INT_IRQ_157 3
+#define IT83XX_CPU_INT_IRQ_158 3
+#define IT83XX_CPU_INT_IRQ_159 3
+#define IT83XX_CPU_INT_IRQ_160 12
+#define IT83XX_CPU_INT_IRQ_161 12
+#define IT83XX_CPU_INT_IRQ_162 12
+#define IT83XX_CPU_INT_IRQ_163 12
+#define IT83XX_CPU_INT_IRQ_164 12
+#define IT83XX_CPU_INT_IRQ_165 12
+#define IT83XX_CPU_INT_IRQ_166 12
+#define IT83XX_CPU_INT_IRQ_167 12
+#define IT83XX_CPU_INT_IRQ_168 2
+#define IT83XX_CPU_INT_IRQ_169 2
 #if defined(CHIP_FAMILY_IT8320)
-#define IT83XX_CPU_INT_IRQ_170     2
-#define IT83XX_CPU_INT_IRQ_171     2
-#define IT83XX_CPU_INT_IRQ_172     2
-#define IT83XX_CPU_INT_IRQ_173     2
-#define IT83XX_CPU_INT_IRQ_174     2
-#define IT83XX_CPU_INT_IRQ_175     2
+#define IT83XX_CPU_INT_IRQ_170 2
+#define IT83XX_CPU_INT_IRQ_171 2
+#define IT83XX_CPU_INT_IRQ_172 2
+#define IT83XX_CPU_INT_IRQ_173 2
+#define IT83XX_CPU_INT_IRQ_174 2
+#define IT83XX_CPU_INT_IRQ_175 2
 #elif defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2)
-#define IT83XX_CPU_INT_IRQ_170    12
-#define IT83XX_CPU_INT_IRQ_171    12
-#define IT83XX_CPU_INT_IRQ_172    12
-#define IT83XX_CPU_INT_IRQ_173    12
-#define IT83XX_CPU_INT_IRQ_174    12
-#define IT83XX_CPU_INT_IRQ_175    12
+#define IT83XX_CPU_INT_IRQ_170 12
+#define IT83XX_CPU_INT_IRQ_171 12
+#define IT83XX_CPU_INT_IRQ_172 12
+#define IT83XX_CPU_INT_IRQ_173 12
+#define IT83XX_CPU_INT_IRQ_174 12
+#define IT83XX_CPU_INT_IRQ_175 12
 #endif
-#define IT83XX_CPU_INT_IRQ_176     2
-#define IT83XX_CPU_INT_IRQ_177     2
-#define IT83XX_CPU_INT_IRQ_178     2
-#define IT83XX_CPU_INT_IRQ_179     2
-#define IT83XX_CPU_INT_IRQ_180     2
-#define IT83XX_CPU_INT_IRQ_181     2
-#define IT83XX_CPU_INT_IRQ_182     2
-#define IT83XX_CPU_INT_IRQ_183     2
-#define IT83XX_CPU_INT_IRQ_184     2
-#define IT83XX_CPU_INT_IRQ_185     2
-#define IT83XX_CPU_INT_IRQ_191     2
-#define IT83XX_CPU_INT_IRQ_192     2
-#define IT83XX_CPU_INT_IRQ_193     2
-#define IT83XX_CPU_INT_IRQ_194     2
-#define IT83XX_CPU_INT_IRQ_195     2
-#define IT83XX_CPU_INT_IRQ_196     2
-#define IT83XX_CPU_INT_IRQ_197     2
-#define IT83XX_CPU_INT_IRQ_199     2
-#define IT83XX_CPU_INT_IRQ_200     2
-#define IT83XX_CPU_INT_IRQ_201     2
-#define IT83XX_CPU_INT_IRQ_202     2
-#define IT83XX_CPU_INT_IRQ_203     2
-#define IT83XX_CPU_INT_IRQ_208     2
-#define IT83XX_CPU_INT_IRQ_209     2
-#define IT83XX_CPU_INT_IRQ_210     2
-#define IT83XX_CPU_INT_IRQ_211     2
-#define IT83XX_CPU_INT_IRQ_212     2
-#define IT83XX_CPU_INT_IRQ_213     2
-#define IT83XX_CPU_INT_IRQ_214     2
-#define IT83XX_CPU_INT_IRQ_216     2
-#define IT83XX_CPU_INT_IRQ_217     2
-#define IT83XX_CPU_INT_IRQ_218     2
-#define IT83XX_CPU_INT_IRQ_219     2
-#define IT83XX_CPU_INT_IRQ_220     2
-#define IT83XX_CPU_INT_IRQ_221     2
-#define IT83XX_CPU_INT_IRQ_224     2
-#define IT83XX_CPU_INT_IRQ_225     2
-#define IT83XX_CPU_INT_IRQ_226     2
-#define IT83XX_CPU_INT_IRQ_227     2
-#define IT83XX_CPU_INT_IRQ_228     2
-#define IT83XX_CPU_INT_IRQ_229     2
+#define IT83XX_CPU_INT_IRQ_176 2
+#define IT83XX_CPU_INT_IRQ_177 2
+#define IT83XX_CPU_INT_IRQ_178 2
+#define IT83XX_CPU_INT_IRQ_179 2
+#define IT83XX_CPU_INT_IRQ_180 2
+#define IT83XX_CPU_INT_IRQ_181 2
+#define IT83XX_CPU_INT_IRQ_182 2
+#define IT83XX_CPU_INT_IRQ_183 2
+#define IT83XX_CPU_INT_IRQ_184 2
+#define IT83XX_CPU_INT_IRQ_185 2
+#define IT83XX_CPU_INT_IRQ_191 2
+#define IT83XX_CPU_INT_IRQ_192 2
+#define IT83XX_CPU_INT_IRQ_193 2
+#define IT83XX_CPU_INT_IRQ_194 2
+#define IT83XX_CPU_INT_IRQ_195 2
+#define IT83XX_CPU_INT_IRQ_196 2
+#define IT83XX_CPU_INT_IRQ_197 2
+#define IT83XX_CPU_INT_IRQ_199 2
+#define IT83XX_CPU_INT_IRQ_200 2
+#define IT83XX_CPU_INT_IRQ_201 2
+#define IT83XX_CPU_INT_IRQ_202 2
+#define IT83XX_CPU_INT_IRQ_203 2
+#define IT83XX_CPU_INT_IRQ_208 2
+#define IT83XX_CPU_INT_IRQ_209 2
+#define IT83XX_CPU_INT_IRQ_210 2
+#define IT83XX_CPU_INT_IRQ_211 2
+#define IT83XX_CPU_INT_IRQ_212 2
+#define IT83XX_CPU_INT_IRQ_213 2
+#define IT83XX_CPU_INT_IRQ_214 2
+#define IT83XX_CPU_INT_IRQ_216 2
+#define IT83XX_CPU_INT_IRQ_217 2
+#define IT83XX_CPU_INT_IRQ_218 2
+#define IT83XX_CPU_INT_IRQ_219 2
+#define IT83XX_CPU_INT_IRQ_220 2
+#define IT83XX_CPU_INT_IRQ_221 2
+#define IT83XX_CPU_INT_IRQ_224 2
+#define IT83XX_CPU_INT_IRQ_225 2
+#define IT83XX_CPU_INT_IRQ_226 2
+#define IT83XX_CPU_INT_IRQ_227 2
+#define IT83XX_CPU_INT_IRQ_228 2
+#define IT83XX_CPU_INT_IRQ_229 2
 
 /* "Fake" IRQ to declare in readable fashion all WKO IRQ routed to INT#2 */
-#define CPU_INT_2_ALL_GPIOS      255
-#define IT83XX_CPU_INT_IRQ_255     2
+#define CPU_INT_2_ALL_GPIOS 255
+#define IT83XX_CPU_INT_IRQ_255 2
 
-#define CPU_INT_GROUP_5          254
-#define IT83XX_CPU_INT_IRQ_254     5
+#define CPU_INT_GROUP_5 254
+#define IT83XX_CPU_INT_IRQ_254 5
 
-#define CPU_INT_GROUP_4          252
-#define IT83XX_CPU_INT_IRQ_252     4
+#define CPU_INT_GROUP_4 252
+#define IT83XX_CPU_INT_IRQ_252 4
 
-#define CPU_INT_GROUP_12         253
-#define IT83XX_CPU_INT_IRQ_253    12
+#define CPU_INT_GROUP_12 253
+#define IT83XX_CPU_INT_IRQ_253 12
 
-#define CPU_INT_GROUP_3          251
-#define IT83XX_CPU_INT_IRQ_251     3
+#define CPU_INT_GROUP_3 251
+#define IT83XX_CPU_INT_IRQ_251 3
 
-#define CPU_INT_GROUP_6          250
-#define IT83XX_CPU_INT_IRQ_250     6
+#define CPU_INT_GROUP_6 250
+#define IT83XX_CPU_INT_IRQ_250 6
 
-#define CPU_INT_GROUP_9          249
-#define IT83XX_CPU_INT_IRQ_249     9
+#define CPU_INT_GROUP_9 249
+#define IT83XX_CPU_INT_IRQ_249 9
 
-#define CPU_INT_GROUP_7          248
-#define IT83XX_CPU_INT_IRQ_248     7
+#define CPU_INT_GROUP_7 248
+#define IT83XX_CPU_INT_IRQ_248 7
 
 #define CPU_INT(irq) CONCAT2(IT83XX_CPU_INT_IRQ_, irq)
 
 /* --- INTC --- */
-#define IT83XX_INTC_BASE    CHIP_EC_INTC_BASE
-
-#define IT83XX_INTC_REG(n)  REG8(IT83XX_INTC_BASE+(n))
-
-#define IT83XX_INTC_AIVCT   REG8(IT83XX_INTC_BASE+0x10)
-
-#define IT83XX_INTC_IER0    REG8(IT83XX_INTC_BASE+0x04)
-#define IT83XX_INTC_IER1    REG8(IT83XX_INTC_BASE+0x05)
-#define IT83XX_INTC_IER2    REG8(IT83XX_INTC_BASE+0x06)
-#define IT83XX_INTC_IER3    REG8(IT83XX_INTC_BASE+0x07)
-#define IT83XX_INTC_IER4    REG8(IT83XX_INTC_BASE+0x15)
-#define IT83XX_INTC_IER5    REG8(IT83XX_INTC_BASE+0x19)
-#define IT83XX_INTC_IER6    REG8(IT83XX_INTC_BASE+0x1d)
-#define IT83XX_INTC_IER7    REG8(IT83XX_INTC_BASE+0x21)
-#define IT83XX_INTC_IER8    REG8(IT83XX_INTC_BASE+0x25)
-#define IT83XX_INTC_IER9    REG8(IT83XX_INTC_BASE+0x29)
-#define IT83XX_INTC_IER10   REG8(IT83XX_INTC_BASE+0x2d)
-#define IT83XX_INTC_IER11   REG8(IT83XX_INTC_BASE+0x31)
-#define IT83XX_INTC_IER12   REG8(IT83XX_INTC_BASE+0x35)
-#define IT83XX_INTC_IER13   REG8(IT83XX_INTC_BASE+0x39)
-#define IT83XX_INTC_IER14   REG8(IT83XX_INTC_BASE+0x3d)
-#define IT83XX_INTC_IER15   REG8(IT83XX_INTC_BASE+0x41)
-#define IT83XX_INTC_IER16   REG8(IT83XX_INTC_BASE+0x45)
-#define IT83XX_INTC_IER17   REG8(IT83XX_INTC_BASE+0x49)
-#define IT83XX_INTC_IER18   REG8(IT83XX_INTC_BASE+0x4d)
-#define IT83XX_INTC_IER19   REG8(IT83XX_INTC_BASE+0x51)
-#define IT83XX_INTC_IER20   REG8(IT83XX_INTC_BASE+0x55)
-#define IT83XX_INTC_IER21   REG8(IT83XX_INTC_BASE+0x59)
-#define IT83XX_INTC_IER22   REG8(IT83XX_INTC_BASE+0x5d)
-#define IT83XX_INTC_IER23   REG8(IT83XX_INTC_BASE+0x91)
-#define IT83XX_INTC_IER24   REG8(IT83XX_INTC_BASE+0x95)
-#define IT83XX_INTC_IER25   REG8(IT83XX_INTC_BASE+0x99)
-#define IT83XX_INTC_IER26   REG8(IT83XX_INTC_BASE+0x9d)
-#define IT83XX_INTC_IER27   REG8(IT83XX_INTC_BASE+0xa1)
-#define IT83XX_INTC_IER28   REG8(IT83XX_INTC_BASE+0xa5)
-
-#define IT83XX_INTC_ISR0    REG8(IT83XX_INTC_BASE+0x00)
-#define IT83XX_INTC_ISR1    REG8(IT83XX_INTC_BASE+0x01)
-#define IT83XX_INTC_ISR2    REG8(IT83XX_INTC_BASE+0x02)
-#define IT83XX_INTC_ISR3    REG8(IT83XX_INTC_BASE+0x03)
-#define IT83XX_INTC_ISR4    REG8(IT83XX_INTC_BASE+0x14)
-#define IT83XX_INTC_ISR5    REG8(IT83XX_INTC_BASE+0x18)
-#define IT83XX_INTC_ISR6    REG8(IT83XX_INTC_BASE+0x1c)
-#define IT83XX_INTC_ISR7    REG8(IT83XX_INTC_BASE+0x20)
-#define IT83XX_INTC_ISR8    REG8(IT83XX_INTC_BASE+0x24)
-#define IT83XX_INTC_ISR9    REG8(IT83XX_INTC_BASE+0x28)
-#define IT83XX_INTC_ISR10   REG8(IT83XX_INTC_BASE+0x2c)
-#define IT83XX_INTC_ISR11   REG8(IT83XX_INTC_BASE+0x30)
-#define IT83XX_INTC_ISR12   REG8(IT83XX_INTC_BASE+0x34)
-#define IT83XX_INTC_ISR13   REG8(IT83XX_INTC_BASE+0x38)
-#define IT83XX_INTC_ISR14   REG8(IT83XX_INTC_BASE+0x3c)
-#define IT83XX_INTC_ISR15   REG8(IT83XX_INTC_BASE+0x40)
-#define IT83XX_INTC_ISR16   REG8(IT83XX_INTC_BASE+0x44)
-#define IT83XX_INTC_ISR17   REG8(IT83XX_INTC_BASE+0x48)
-#define IT83XX_INTC_ISR18   REG8(IT83XX_INTC_BASE+0x4c)
-#define IT83XX_INTC_ISR19   REG8(IT83XX_INTC_BASE+0x50)
-#define IT83XX_INTC_ISR20   REG8(IT83XX_INTC_BASE+0x54)
-#define IT83XX_INTC_ISR21   REG8(IT83XX_INTC_BASE+0x58)
-#define IT83XX_INTC_ISR22   REG8(IT83XX_INTC_BASE+0x5c)
-#define IT83XX_INTC_ISR23   REG8(IT83XX_INTC_BASE+0x90)
-#define IT83XX_INTC_ISR24   REG8(IT83XX_INTC_BASE+0x94)
-#define IT83XX_INTC_ISR25   REG8(IT83XX_INTC_BASE+0x98)
-#define IT83XX_INTC_ISR26   REG8(IT83XX_INTC_BASE+0x9c)
-#define IT83XX_INTC_ISR27   REG8(IT83XX_INTC_BASE+0xa0)
-#define IT83XX_INTC_ISR28   REG8(IT83XX_INTC_BASE+0xa4)
-
-#define IT83XX_INTC_IELMR10 REG8(IT83XX_INTC_BASE+0x2E)
-#define IT83XX_INTC_IPOLR10 REG8(IT83XX_INTC_BASE+0x2F)
-#define IT83XX_INTC_IELMR19 REG8(IT83XX_INTC_BASE+0x52)
-#define IT83XX_INTC_IPOLR19 REG8(IT83XX_INTC_BASE+0x53)
+#define IT83XX_INTC_BASE CHIP_EC_INTC_BASE
+
+#define IT83XX_INTC_REG(n) REG8(IT83XX_INTC_BASE + (n))
+
+#define IT83XX_INTC_AIVCT REG8(IT83XX_INTC_BASE + 0x10)
+
+#define IT83XX_INTC_IER0 REG8(IT83XX_INTC_BASE + 0x04)
+#define IT83XX_INTC_IER1 REG8(IT83XX_INTC_BASE + 0x05)
+#define IT83XX_INTC_IER2 REG8(IT83XX_INTC_BASE + 0x06)
+#define IT83XX_INTC_IER3 REG8(IT83XX_INTC_BASE + 0x07)
+#define IT83XX_INTC_IER4 REG8(IT83XX_INTC_BASE + 0x15)
+#define IT83XX_INTC_IER5 REG8(IT83XX_INTC_BASE + 0x19)
+#define IT83XX_INTC_IER6 REG8(IT83XX_INTC_BASE + 0x1d)
+#define IT83XX_INTC_IER7 REG8(IT83XX_INTC_BASE + 0x21)
+#define IT83XX_INTC_IER8 REG8(IT83XX_INTC_BASE + 0x25)
+#define IT83XX_INTC_IER9 REG8(IT83XX_INTC_BASE + 0x29)
+#define IT83XX_INTC_IER10 REG8(IT83XX_INTC_BASE + 0x2d)
+#define IT83XX_INTC_IER11 REG8(IT83XX_INTC_BASE + 0x31)
+#define IT83XX_INTC_IER12 REG8(IT83XX_INTC_BASE + 0x35)
+#define IT83XX_INTC_IER13 REG8(IT83XX_INTC_BASE + 0x39)
+#define IT83XX_INTC_IER14 REG8(IT83XX_INTC_BASE + 0x3d)
+#define IT83XX_INTC_IER15 REG8(IT83XX_INTC_BASE + 0x41)
+#define IT83XX_INTC_IER16 REG8(IT83XX_INTC_BASE + 0x45)
+#define IT83XX_INTC_IER17 REG8(IT83XX_INTC_BASE + 0x49)
+#define IT83XX_INTC_IER18 REG8(IT83XX_INTC_BASE + 0x4d)
+#define IT83XX_INTC_IER19 REG8(IT83XX_INTC_BASE + 0x51)
+#define IT83XX_INTC_IER20 REG8(IT83XX_INTC_BASE + 0x55)
+#define IT83XX_INTC_IER21 REG8(IT83XX_INTC_BASE + 0x59)
+#define IT83XX_INTC_IER22 REG8(IT83XX_INTC_BASE + 0x5d)
+#define IT83XX_INTC_IER23 REG8(IT83XX_INTC_BASE + 0x91)
+#define IT83XX_INTC_IER24 REG8(IT83XX_INTC_BASE + 0x95)
+#define IT83XX_INTC_IER25 REG8(IT83XX_INTC_BASE + 0x99)
+#define IT83XX_INTC_IER26 REG8(IT83XX_INTC_BASE + 0x9d)
+#define IT83XX_INTC_IER27 REG8(IT83XX_INTC_BASE + 0xa1)
+#define IT83XX_INTC_IER28 REG8(IT83XX_INTC_BASE + 0xa5)
+
+#define IT83XX_INTC_ISR0 REG8(IT83XX_INTC_BASE + 0x00)
+#define IT83XX_INTC_ISR1 REG8(IT83XX_INTC_BASE + 0x01)
+#define IT83XX_INTC_ISR2 REG8(IT83XX_INTC_BASE + 0x02)
+#define IT83XX_INTC_ISR3 REG8(IT83XX_INTC_BASE + 0x03)
+#define IT83XX_INTC_ISR4 REG8(IT83XX_INTC_BASE + 0x14)
+#define IT83XX_INTC_ISR5 REG8(IT83XX_INTC_BASE + 0x18)
+#define IT83XX_INTC_ISR6 REG8(IT83XX_INTC_BASE + 0x1c)
+#define IT83XX_INTC_ISR7 REG8(IT83XX_INTC_BASE + 0x20)
+#define IT83XX_INTC_ISR8 REG8(IT83XX_INTC_BASE + 0x24)
+#define IT83XX_INTC_ISR9 REG8(IT83XX_INTC_BASE + 0x28)
+#define IT83XX_INTC_ISR10 REG8(IT83XX_INTC_BASE + 0x2c)
+#define IT83XX_INTC_ISR11 REG8(IT83XX_INTC_BASE + 0x30)
+#define IT83XX_INTC_ISR12 REG8(IT83XX_INTC_BASE + 0x34)
+#define IT83XX_INTC_ISR13 REG8(IT83XX_INTC_BASE + 0x38)
+#define IT83XX_INTC_ISR14 REG8(IT83XX_INTC_BASE + 0x3c)
+#define IT83XX_INTC_ISR15 REG8(IT83XX_INTC_BASE + 0x40)
+#define IT83XX_INTC_ISR16 REG8(IT83XX_INTC_BASE + 0x44)
+#define IT83XX_INTC_ISR17 REG8(IT83XX_INTC_BASE + 0x48)
+#define IT83XX_INTC_ISR18 REG8(IT83XX_INTC_BASE + 0x4c)
+#define IT83XX_INTC_ISR19 REG8(IT83XX_INTC_BASE + 0x50)
+#define IT83XX_INTC_ISR20 REG8(IT83XX_INTC_BASE + 0x54)
+#define IT83XX_INTC_ISR21 REG8(IT83XX_INTC_BASE + 0x58)
+#define IT83XX_INTC_ISR22 REG8(IT83XX_INTC_BASE + 0x5c)
+#define IT83XX_INTC_ISR23 REG8(IT83XX_INTC_BASE + 0x90)
+#define IT83XX_INTC_ISR24 REG8(IT83XX_INTC_BASE + 0x94)
+#define IT83XX_INTC_ISR25 REG8(IT83XX_INTC_BASE + 0x98)
+#define IT83XX_INTC_ISR26 REG8(IT83XX_INTC_BASE + 0x9c)
+#define IT83XX_INTC_ISR27 REG8(IT83XX_INTC_BASE + 0xa0)
+#define IT83XX_INTC_ISR28 REG8(IT83XX_INTC_BASE + 0xa4)
+
+#define IT83XX_INTC_IELMR10 REG8(IT83XX_INTC_BASE + 0x2E)
+#define IT83XX_INTC_IPOLR10 REG8(IT83XX_INTC_BASE + 0x2F)
+#define IT83XX_INTC_IELMR19 REG8(IT83XX_INTC_BASE + 0x52)
+#define IT83XX_INTC_IPOLR19 REG8(IT83XX_INTC_BASE + 0x53)
 
 #define IT83XX_INTC_EXT_IER_OFF(n) (0x60 + (n))
-#define IT83XX_INTC_IVCT(i)     REG8(IT83XX_INTC_BASE+0x80+(i))
+#define IT83XX_INTC_IVCT(i) REG8(IT83XX_INTC_BASE + 0x80 + (i))
 
 /* --- EC Access to the Host Controlled Modules (EC2I Bridge) --- */
-#define IT83XX_EC2I_BASE  0x00F01200
+#define IT83XX_EC2I_BASE 0x00F01200
 
-#define IT83XX_EC2I_IHIOA       REG8(IT83XX_EC2I_BASE+0x00)
-#define IT83XX_EC2I_IHD         REG8(IT83XX_EC2I_BASE+0x01)
-#define IT83XX_EC2I_LSIOHA      REG8(IT83XX_EC2I_BASE+0x02)
-#define IT83XX_EC2I_SIOLV       REG8(IT83XX_EC2I_BASE+0x03)
-#define IT83XX_EC2I_IBMAE       REG8(IT83XX_EC2I_BASE+0x04)
-#define IT83XX_EC2I_IBCTL       REG8(IT83XX_EC2I_BASE+0x05)
+#define IT83XX_EC2I_IHIOA REG8(IT83XX_EC2I_BASE + 0x00)
+#define IT83XX_EC2I_IHD REG8(IT83XX_EC2I_BASE + 0x01)
+#define IT83XX_EC2I_LSIOHA REG8(IT83XX_EC2I_BASE + 0x02)
+#define IT83XX_EC2I_SIOLV REG8(IT83XX_EC2I_BASE + 0x03)
+#define IT83XX_EC2I_IBMAE REG8(IT83XX_EC2I_BASE + 0x04)
+#define IT83XX_EC2I_IBCTL REG8(IT83XX_EC2I_BASE + 0x05)
 
 /* --- System Wake-UP Control (SWUC) --- */
-#define IT83XX_SWUC_BASE  0x00F01400
-#define IT83XX_SWUC_SWCTL1      REG8(IT83XX_SWUC_BASE+0x00)
+#define IT83XX_SWUC_BASE 0x00F01400
+#define IT83XX_SWUC_SWCTL1 REG8(IT83XX_SWUC_BASE + 0x00)
 
 /* --- Wake-Up Control (WUC) --- */
-#define IT83XX_WUC_BASE   0x00F01B00
+#define IT83XX_WUC_BASE 0x00F01B00
 
-#define IT83XX_WUC_WUEMR1 (IT83XX_WUC_BASE+0x00)
-#define IT83XX_WUC_WUEMR5 (IT83XX_WUC_BASE+0x0c)
-#define IT83XX_WUC_WUESR1 (IT83XX_WUC_BASE+0x04)
-#define IT83XX_WUC_WUESR5 (IT83XX_WUC_BASE+0x0d)
-#define IT83XX_WUC_WUBEMR1 (IT83XX_WUC_BASE+0x3c)
-#define IT83XX_WUC_WUBEMR5 (IT83XX_WUC_BASE+0x0f)
+#define IT83XX_WUC_WUEMR1 (IT83XX_WUC_BASE + 0x00)
+#define IT83XX_WUC_WUEMR5 (IT83XX_WUC_BASE + 0x0c)
+#define IT83XX_WUC_WUESR1 (IT83XX_WUC_BASE + 0x04)
+#define IT83XX_WUC_WUESR5 (IT83XX_WUC_BASE + 0x0d)
+#define IT83XX_WUC_WUBEMR1 (IT83XX_WUC_BASE + 0x3c)
+#define IT83XX_WUC_WUBEMR5 (IT83XX_WUC_BASE + 0x0f)
 
-#define IT83XX_WUC_WUESR10    REG8(IT83XX_WUC_BASE+0x21)
-#define IT83XX_WUC_WUESR11    REG8(IT83XX_WUC_BASE+0x25)
+#define IT83XX_WUC_WUESR10 REG8(IT83XX_WUC_BASE + 0x21)
+#define IT83XX_WUC_WUESR11 REG8(IT83XX_WUC_BASE + 0x25)
 
-#define IT83XX_WUC_WUEMR3     REG8(IT83XX_WUC_BASE+0x02)
-#define IT83XX_WUC_WUESR3     REG8(IT83XX_WUC_BASE+0x06)
-#define IT83XX_WUC_WUENR3     REG8(IT83XX_WUC_BASE+0x0A)
+#define IT83XX_WUC_WUEMR3 REG8(IT83XX_WUC_BASE + 0x02)
+#define IT83XX_WUC_WUESR3 REG8(IT83XX_WUC_BASE + 0x06)
+#define IT83XX_WUC_WUENR3 REG8(IT83XX_WUC_BASE + 0x0A)
 
-#define IT83XX_WUC_WUEMR4     REG8(IT83XX_WUC_BASE+0x03)
-#define IT83XX_WUC_WUESR4     REG8(IT83XX_WUC_BASE+0x07)
-#define IT83XX_WUC_WUENR4     REG8(IT83XX_WUC_BASE+0x0B)
+#define IT83XX_WUC_WUEMR4 REG8(IT83XX_WUC_BASE + 0x03)
+#define IT83XX_WUC_WUESR4 REG8(IT83XX_WUC_BASE + 0x07)
+#define IT83XX_WUC_WUENR4 REG8(IT83XX_WUC_BASE + 0x0B)
 
 /* --- UART --- */
 #define IT83XX_UART0_BASE 0x00F02700
 #define IT83XX_UART1_BASE 0x00F02800
 
-#define IT83XX_UART_BASE(n)        CONCAT3(IT83XX_UART, n, _BASE)
+#define IT83XX_UART_BASE(n) CONCAT3(IT83XX_UART, n, _BASE)
 #define IT83XX_UART_REG(n, offset) REG8(IT83XX_UART_BASE(n) + (offset))
 
-#define IT83XX_UART_DLL(n)         IT83XX_UART_REG(n, 0x00)
-#define IT83XX_UART_DLM(n)         IT83XX_UART_REG(n, 0x01)
-#define IT83XX_UART_RBR(n)         IT83XX_UART_REG(n, 0x00)
-#define IT83XX_UART_THR(n)         IT83XX_UART_REG(n, 0x00)
-#define IT83XX_UART_IER(n)         IT83XX_UART_REG(n, 0x01)
-#define IT83XX_UART_IIR(n)         IT83XX_UART_REG(n, 0x02)
-#define IT83XX_UART_FCR(n)         IT83XX_UART_REG(n, 0x02)
-#define IT83XX_UART_LCR(n)         IT83XX_UART_REG(n, 0x03)
-#define IT83XX_UART_MCR(n)         IT83XX_UART_REG(n, 0x04)
-#define IT83XX_UART_LSR(n)         IT83XX_UART_REG(n, 0x05)
-#define IT83XX_UART_MSR(n)         IT83XX_UART_REG(n, 0x06)
-#define IT83XX_UART_SCR(n)         IT83XX_UART_REG(n, 0x07)
-#define IT83XX_UART_ECSMPR(n)      IT83XX_UART_REG(n, 0x08)
-#define IT83XX_UART_CSSR(n)        IT83XX_UART_REG(n, 0x09)
+#define IT83XX_UART_DLL(n) IT83XX_UART_REG(n, 0x00)
+#define IT83XX_UART_DLM(n) IT83XX_UART_REG(n, 0x01)
+#define IT83XX_UART_RBR(n) IT83XX_UART_REG(n, 0x00)
+#define IT83XX_UART_THR(n) IT83XX_UART_REG(n, 0x00)
+#define IT83XX_UART_IER(n) IT83XX_UART_REG(n, 0x01)
+#define IT83XX_UART_IIR(n) IT83XX_UART_REG(n, 0x02)
+#define IT83XX_UART_FCR(n) IT83XX_UART_REG(n, 0x02)
+#define IT83XX_UART_LCR(n) IT83XX_UART_REG(n, 0x03)
+#define IT83XX_UART_MCR(n) IT83XX_UART_REG(n, 0x04)
+#define IT83XX_UART_LSR(n) IT83XX_UART_REG(n, 0x05)
+#define IT83XX_UART_MSR(n) IT83XX_UART_REG(n, 0x06)
+#define IT83XX_UART_SCR(n) IT83XX_UART_REG(n, 0x07)
+#define IT83XX_UART_ECSMPR(n) IT83XX_UART_REG(n, 0x08)
+#define IT83XX_UART_CSSR(n) IT83XX_UART_REG(n, 0x09)
 
 /* --- GPIO --- */
 
-#define IT83XX_GPIO_BASE  0x00F01600
+#define IT83XX_GPIO_BASE 0x00F01600
 #define IT83XX_GPIO2_BASE 0x00F03E00
 
-#define IT83XX_GPIO_GCR         REG8(IT83XX_GPIO_BASE+0x00)
-#define IT83XX_GPIO_GCR_LPC_RST_B7      0x1
-#define IT83XX_GPIO_GCR_LPC_RST_D2      0x2
+#define IT83XX_GPIO_GCR REG8(IT83XX_GPIO_BASE + 0x00)
+#define IT83XX_GPIO_GCR_LPC_RST_B7 0x1
+#define IT83XX_GPIO_GCR_LPC_RST_D2 0x2
 #define IT83XX_GPIO_GCR_LPC_RST_DISABLE 0x3
-#define IT83XX_GPIO_GCR_LPC_RST_POS     1
-
-#define IT83XX_GPIO_GPDRA       REG8(IT83XX_GPIO_BASE+0x01)
-#define IT83XX_GPIO_GPDRB       REG8(IT83XX_GPIO_BASE+0x02)
-#define IT83XX_GPIO_GPDRC       REG8(IT83XX_GPIO_BASE+0x03)
-#define IT83XX_GPIO_GPDRE       REG8(IT83XX_GPIO_BASE+0x05)
-#define IT83XX_GPIO_GPDRF       REG8(IT83XX_GPIO_BASE+0x06)
-#define IT83XX_GPIO_GPDRH       REG8(IT83XX_GPIO_BASE+0x08)
-
-#define IT83XX_GPIO_GPCRA0      REG8(IT83XX_GPIO_BASE+0x10)
-#define IT83XX_GPIO_GPCRA1      REG8(IT83XX_GPIO_BASE+0x11)
-#define IT83XX_GPIO_GPCRA2      REG8(IT83XX_GPIO_BASE+0x12)
-#define IT83XX_GPIO_GPCRA3      REG8(IT83XX_GPIO_BASE+0x13)
-#define IT83XX_GPIO_GPCRA4      REG8(IT83XX_GPIO_BASE+0x14)
-#define IT83XX_GPIO_GPCRA5      REG8(IT83XX_GPIO_BASE+0x15)
-#define IT83XX_GPIO_GPCRA6      REG8(IT83XX_GPIO_BASE+0x16)
-#define IT83XX_GPIO_GPCRA7      REG8(IT83XX_GPIO_BASE+0x17)
-
-#define IT83XX_GPIO_GPCRB0      REG8(IT83XX_GPIO_BASE+0x18)
-#define IT83XX_GPIO_GPCRB1      REG8(IT83XX_GPIO_BASE+0x19)
-#define IT83XX_GPIO_GPCRB2      REG8(IT83XX_GPIO_BASE+0x1A)
-#define IT83XX_GPIO_GPCRB3      REG8(IT83XX_GPIO_BASE+0x1B)
-#define IT83XX_GPIO_GPCRB4      REG8(IT83XX_GPIO_BASE+0x1C)
-#define IT83XX_GPIO_GPCRB5      REG8(IT83XX_GPIO_BASE+0x1D)
-#define IT83XX_GPIO_GPCRB6      REG8(IT83XX_GPIO_BASE+0x1E)
-#define IT83XX_GPIO_GPCRB7      REG8(IT83XX_GPIO_BASE+0x1F)
-
-#define IT83XX_GPIO_GPCRC0      REG8(IT83XX_GPIO_BASE+0x20)
-#define IT83XX_GPIO_GPCRC1      REG8(IT83XX_GPIO_BASE+0x21)
-#define IT83XX_GPIO_GPCRC2      REG8(IT83XX_GPIO_BASE+0x22)
-#define IT83XX_GPIO_GPCRC3      REG8(IT83XX_GPIO_BASE+0x23)
-#define IT83XX_GPIO_GPCRC4      REG8(IT83XX_GPIO_BASE+0x24)
-#define IT83XX_GPIO_GPCRC5      REG8(IT83XX_GPIO_BASE+0x25)
-#define IT83XX_GPIO_GPCRC6      REG8(IT83XX_GPIO_BASE+0x26)
-#define IT83XX_GPIO_GPCRC7      REG8(IT83XX_GPIO_BASE+0x27)
-
-#define IT83XX_GPIO_GPCRE0      REG8(IT83XX_GPIO_BASE+0x30)
-#define IT83XX_GPIO_GPCRE1      REG8(IT83XX_GPIO_BASE+0x31)
-#define IT83XX_GPIO_GPCRE2      REG8(IT83XX_GPIO_BASE+0x32)
-#define IT83XX_GPIO_GPCRE3      REG8(IT83XX_GPIO_BASE+0x33)
-#define IT83XX_GPIO_GPCRE4      REG8(IT83XX_GPIO_BASE+0x34)
-#define IT83XX_GPIO_GPCRE5      REG8(IT83XX_GPIO_BASE+0x35)
-#define IT83XX_GPIO_GPCRE6      REG8(IT83XX_GPIO_BASE+0x36)
-#define IT83XX_GPIO_GPCRE7      REG8(IT83XX_GPIO_BASE+0x37)
-
-#define IT83XX_GPIO_GPCRF0      REG8(IT83XX_GPIO_BASE+0x38)
-#define IT83XX_GPIO_GPCRF1      REG8(IT83XX_GPIO_BASE+0x39)
-#define IT83XX_GPIO_GPCRF2      REG8(IT83XX_GPIO_BASE+0x3A)
-#define IT83XX_GPIO_GPCRF3      REG8(IT83XX_GPIO_BASE+0x3B)
-#define IT83XX_GPIO_GPCRF4      REG8(IT83XX_GPIO_BASE+0x3C)
-#define IT83XX_GPIO_GPCRF5      REG8(IT83XX_GPIO_BASE+0x3D)
-#define IT83XX_GPIO_GPCRF6      REG8(IT83XX_GPIO_BASE+0x3E)
-#define IT83XX_GPIO_GPCRF7      REG8(IT83XX_GPIO_BASE+0x3F)
-
-#define IT83XX_GPIO_GPCRH0      REG8(IT83XX_GPIO_BASE+0x48)
-#define IT83XX_GPIO_GPCRH1      REG8(IT83XX_GPIO_BASE+0x49)
-#define IT83XX_GPIO_GPCRH2      REG8(IT83XX_GPIO_BASE+0x4A)
-#define IT83XX_GPIO_GPCRH3      REG8(IT83XX_GPIO_BASE+0x4B)
-#define IT83XX_GPIO_GPCRH4      REG8(IT83XX_GPIO_BASE+0x4C)
-#define IT83XX_GPIO_GPCRH5      REG8(IT83XX_GPIO_BASE+0x4D)
-#define IT83XX_GPIO_GPCRH6      REG8(IT83XX_GPIO_BASE+0x4E)
-#define IT83XX_GPIO_GPCRH7      REG8(IT83XX_GPIO_BASE+0x4F)
-
-#define IT83XX_GPIO_GPCRI0      REG8(IT83XX_GPIO_BASE+0x50)
-#define IT83XX_GPIO_GPCRI1      REG8(IT83XX_GPIO_BASE+0x51)
-#define IT83XX_GPIO_GPCRI2      REG8(IT83XX_GPIO_BASE+0x52)
-#define IT83XX_GPIO_GPCRI3      REG8(IT83XX_GPIO_BASE+0x53)
-#define IT83XX_GPIO_GPCRI4      REG8(IT83XX_GPIO_BASE+0x54)
-#define IT83XX_GPIO_GPCRI5      REG8(IT83XX_GPIO_BASE+0x55)
-#define IT83XX_GPIO_GPCRI6      REG8(IT83XX_GPIO_BASE+0x56)
-#define IT83XX_GPIO_GPCRI7      REG8(IT83XX_GPIO_BASE+0x57)
-
-#define IT83XX_GPIO_GPCRM5      REG8(IT83XX_GPIO_BASE+0xA5)
-
-#define IT83XX_GPIO_GPDMRA      REG8(IT83XX_GPIO_BASE+0x61)
-#define IT83XX_GPIO_GPDMRB      REG8(IT83XX_GPIO_BASE+0x62)
-#define IT83XX_GPIO_GPDMRC      REG8(IT83XX_GPIO_BASE+0x63)
-#define IT83XX_GPIO_GPDMRE      REG8(IT83XX_GPIO_BASE+0x65)
-#define IT83XX_GPIO_GPDMRF      REG8(IT83XX_GPIO_BASE+0x66)
-#define IT83XX_GPIO_GPDMRH      REG8(IT83XX_GPIO_BASE+0x68)
-
-#define IT83XX_GPIO_GPCRL0      REG8(IT83XX_GPIO_BASE+0x98)
-#define IT83XX_GPIO_GPCRL1      REG8(IT83XX_GPIO_BASE+0x99)
-#define IT83XX_GPIO_GPCRL2      REG8(IT83XX_GPIO_BASE+0x9A)
-#define IT83XX_GPIO_GPCRL3      REG8(IT83XX_GPIO_BASE+0x9B)
-#define IT83XX_GPIO_GPCRP0      REG8(IT83XX_GPIO2_BASE+0x18)
-#define IT83XX_GPIO_GPCRP1      REG8(IT83XX_GPIO2_BASE+0x19)
-
-#define IT83XX_GPIO_GRC1        REG8(IT83XX_GPIO_BASE+0xF0)
-#define IT83XX_GPIO_GRC2        REG8(IT83XX_GPIO_BASE+0xF1)
-#define IT83XX_GPIO_GRC3        REG8(IT83XX_GPIO_BASE+0xF2)
-#define IT83XX_GPIO_GRC4        REG8(IT83XX_GPIO_BASE+0xF3)
-#define IT83XX_GPIO_GRC5        REG8(IT83XX_GPIO_BASE+0xF4)
-#define IT83XX_GPIO_GRC6        REG8(IT83XX_GPIO_BASE+0xF5)
-#define IT83XX_GPIO_GRC7        REG8(IT83XX_GPIO_BASE+0xF6)
-#define IT83XX_GPIO_GRC8        REG8(IT83XX_GPIO_BASE+0xF7)
-#define IT83XX_GPIO_GRC19       REG8(IT83XX_GPIO_BASE+0xE4)
-#define IT83XX_GPIO_GRC20       REG8(IT83XX_GPIO_BASE+0xE5)
-#define IT83XX_GPIO_GRC21       REG8(IT83XX_GPIO_BASE+0xE6)
-#define IT83XX_GPIO_GRC22       REG8(IT83XX_GPIO_BASE+0xE7)
-#define IT83XX_GPIO_GRC23       REG8(IT83XX_GPIO_BASE+0xE8)
-#define IT83XX_GPIO_GRC24       REG8(IT83XX_GPIO_BASE+0xE9)
-#define IT83XX_GPIO_GCR25       REG8(IT83XX_GPIO_BASE+0xD1)
-#define IT83XX_GPIO_GCR26       REG8(IT83XX_GPIO_BASE+0xD2)
-#define IT83XX_GPIO_GCR27       REG8(IT83XX_GPIO_BASE+0xD3)
-#define IT83XX_GPIO_GCR28       REG8(IT83XX_GPIO_BASE+0xD4)
-#define IT83XX_GPIO_GCR29       REG8(IT83XX_GPIO_BASE+0xEE)
-#define IT83XX_GPIO_GCR30       REG8(IT83XX_GPIO_BASE+0xED)
-#define IT83XX_GPIO_GCR31       REG8(IT83XX_GPIO_BASE+0xD5)
-#define IT83XX_GPIO_GCR32       REG8(IT83XX_GPIO_BASE+0xD6)
-#define IT83XX_GPIO_GCR33       REG8(IT83XX_GPIO_BASE+0xD7)
-
-#define IT83XX_VBATPC_BGPOPSCR  REG8(IT83XX_GPIO2_BASE+0xF0)
-#define IT83XX_VBATPC_XLPIER    REG8(IT83XX_GPIO2_BASE+0xF5)
+#define IT83XX_GPIO_GCR_LPC_RST_POS 1
+
+#define IT83XX_GPIO_GPDRA REG8(IT83XX_GPIO_BASE + 0x01)
+#define IT83XX_GPIO_GPDRB REG8(IT83XX_GPIO_BASE + 0x02)
+#define IT83XX_GPIO_GPDRC REG8(IT83XX_GPIO_BASE + 0x03)
+#define IT83XX_GPIO_GPDRE REG8(IT83XX_GPIO_BASE + 0x05)
+#define IT83XX_GPIO_GPDRF REG8(IT83XX_GPIO_BASE + 0x06)
+#define IT83XX_GPIO_GPDRH REG8(IT83XX_GPIO_BASE + 0x08)
+
+#define IT83XX_GPIO_GPCRA0 REG8(IT83XX_GPIO_BASE + 0x10)
+#define IT83XX_GPIO_GPCRA1 REG8(IT83XX_GPIO_BASE + 0x11)
+#define IT83XX_GPIO_GPCRA2 REG8(IT83XX_GPIO_BASE + 0x12)
+#define IT83XX_GPIO_GPCRA3 REG8(IT83XX_GPIO_BASE + 0x13)
+#define IT83XX_GPIO_GPCRA4 REG8(IT83XX_GPIO_BASE + 0x14)
+#define IT83XX_GPIO_GPCRA5 REG8(IT83XX_GPIO_BASE + 0x15)
+#define IT83XX_GPIO_GPCRA6 REG8(IT83XX_GPIO_BASE + 0x16)
+#define IT83XX_GPIO_GPCRA7 REG8(IT83XX_GPIO_BASE + 0x17)
+
+#define IT83XX_GPIO_GPCRB0 REG8(IT83XX_GPIO_BASE + 0x18)
+#define IT83XX_GPIO_GPCRB1 REG8(IT83XX_GPIO_BASE + 0x19)
+#define IT83XX_GPIO_GPCRB2 REG8(IT83XX_GPIO_BASE + 0x1A)
+#define IT83XX_GPIO_GPCRB3 REG8(IT83XX_GPIO_BASE + 0x1B)
+#define IT83XX_GPIO_GPCRB4 REG8(IT83XX_GPIO_BASE + 0x1C)
+#define IT83XX_GPIO_GPCRB5 REG8(IT83XX_GPIO_BASE + 0x1D)
+#define IT83XX_GPIO_GPCRB6 REG8(IT83XX_GPIO_BASE + 0x1E)
+#define IT83XX_GPIO_GPCRB7 REG8(IT83XX_GPIO_BASE + 0x1F)
+
+#define IT83XX_GPIO_GPCRC0 REG8(IT83XX_GPIO_BASE + 0x20)
+#define IT83XX_GPIO_GPCRC1 REG8(IT83XX_GPIO_BASE + 0x21)
+#define IT83XX_GPIO_GPCRC2 REG8(IT83XX_GPIO_BASE + 0x22)
+#define IT83XX_GPIO_GPCRC3 REG8(IT83XX_GPIO_BASE + 0x23)
+#define IT83XX_GPIO_GPCRC4 REG8(IT83XX_GPIO_BASE + 0x24)
+#define IT83XX_GPIO_GPCRC5 REG8(IT83XX_GPIO_BASE + 0x25)
+#define IT83XX_GPIO_GPCRC6 REG8(IT83XX_GPIO_BASE + 0x26)
+#define IT83XX_GPIO_GPCRC7 REG8(IT83XX_GPIO_BASE + 0x27)
+
+#define IT83XX_GPIO_GPCRE0 REG8(IT83XX_GPIO_BASE + 0x30)
+#define IT83XX_GPIO_GPCRE1 REG8(IT83XX_GPIO_BASE + 0x31)
+#define IT83XX_GPIO_GPCRE2 REG8(IT83XX_GPIO_BASE + 0x32)
+#define IT83XX_GPIO_GPCRE3 REG8(IT83XX_GPIO_BASE + 0x33)
+#define IT83XX_GPIO_GPCRE4 REG8(IT83XX_GPIO_BASE + 0x34)
+#define IT83XX_GPIO_GPCRE5 REG8(IT83XX_GPIO_BASE + 0x35)
+#define IT83XX_GPIO_GPCRE6 REG8(IT83XX_GPIO_BASE + 0x36)
+#define IT83XX_GPIO_GPCRE7 REG8(IT83XX_GPIO_BASE + 0x37)
+
+#define IT83XX_GPIO_GPCRF0 REG8(IT83XX_GPIO_BASE + 0x38)
+#define IT83XX_GPIO_GPCRF1 REG8(IT83XX_GPIO_BASE + 0x39)
+#define IT83XX_GPIO_GPCRF2 REG8(IT83XX_GPIO_BASE + 0x3A)
+#define IT83XX_GPIO_GPCRF3 REG8(IT83XX_GPIO_BASE + 0x3B)
+#define IT83XX_GPIO_GPCRF4 REG8(IT83XX_GPIO_BASE + 0x3C)
+#define IT83XX_GPIO_GPCRF5 REG8(IT83XX_GPIO_BASE + 0x3D)
+#define IT83XX_GPIO_GPCRF6 REG8(IT83XX_GPIO_BASE + 0x3E)
+#define IT83XX_GPIO_GPCRF7 REG8(IT83XX_GPIO_BASE + 0x3F)
+
+#define IT83XX_GPIO_GPCRH0 REG8(IT83XX_GPIO_BASE + 0x48)
+#define IT83XX_GPIO_GPCRH1 REG8(IT83XX_GPIO_BASE + 0x49)
+#define IT83XX_GPIO_GPCRH2 REG8(IT83XX_GPIO_BASE + 0x4A)
+#define IT83XX_GPIO_GPCRH3 REG8(IT83XX_GPIO_BASE + 0x4B)
+#define IT83XX_GPIO_GPCRH4 REG8(IT83XX_GPIO_BASE + 0x4C)
+#define IT83XX_GPIO_GPCRH5 REG8(IT83XX_GPIO_BASE + 0x4D)
+#define IT83XX_GPIO_GPCRH6 REG8(IT83XX_GPIO_BASE + 0x4E)
+#define IT83XX_GPIO_GPCRH7 REG8(IT83XX_GPIO_BASE + 0x4F)
+
+#define IT83XX_GPIO_GPCRI0 REG8(IT83XX_GPIO_BASE + 0x50)
+#define IT83XX_GPIO_GPCRI1 REG8(IT83XX_GPIO_BASE + 0x51)
+#define IT83XX_GPIO_GPCRI2 REG8(IT83XX_GPIO_BASE + 0x52)
+#define IT83XX_GPIO_GPCRI3 REG8(IT83XX_GPIO_BASE + 0x53)
+#define IT83XX_GPIO_GPCRI4 REG8(IT83XX_GPIO_BASE + 0x54)
+#define IT83XX_GPIO_GPCRI5 REG8(IT83XX_GPIO_BASE + 0x55)
+#define IT83XX_GPIO_GPCRI6 REG8(IT83XX_GPIO_BASE + 0x56)
+#define IT83XX_GPIO_GPCRI7 REG8(IT83XX_GPIO_BASE + 0x57)
+
+#define IT83XX_GPIO_GPCRM5 REG8(IT83XX_GPIO_BASE + 0xA5)
+
+#define IT83XX_GPIO_GPDMRA REG8(IT83XX_GPIO_BASE + 0x61)
+#define IT83XX_GPIO_GPDMRB REG8(IT83XX_GPIO_BASE + 0x62)
+#define IT83XX_GPIO_GPDMRC REG8(IT83XX_GPIO_BASE + 0x63)
+#define IT83XX_GPIO_GPDMRE REG8(IT83XX_GPIO_BASE + 0x65)
+#define IT83XX_GPIO_GPDMRF REG8(IT83XX_GPIO_BASE + 0x66)
+#define IT83XX_GPIO_GPDMRH REG8(IT83XX_GPIO_BASE + 0x68)
+
+#define IT83XX_GPIO_GPCRL0 REG8(IT83XX_GPIO_BASE + 0x98)
+#define IT83XX_GPIO_GPCRL1 REG8(IT83XX_GPIO_BASE + 0x99)
+#define IT83XX_GPIO_GPCRL2 REG8(IT83XX_GPIO_BASE + 0x9A)
+#define IT83XX_GPIO_GPCRL3 REG8(IT83XX_GPIO_BASE + 0x9B)
+#define IT83XX_GPIO_GPCRP0 REG8(IT83XX_GPIO2_BASE + 0x18)
+#define IT83XX_GPIO_GPCRP1 REG8(IT83XX_GPIO2_BASE + 0x19)
+
+#define IT83XX_GPIO_GRC1 REG8(IT83XX_GPIO_BASE + 0xF0)
+#define IT83XX_GPIO_GRC2 REG8(IT83XX_GPIO_BASE + 0xF1)
+#define IT83XX_GPIO_GRC3 REG8(IT83XX_GPIO_BASE + 0xF2)
+#define IT83XX_GPIO_GRC4 REG8(IT83XX_GPIO_BASE + 0xF3)
+#define IT83XX_GPIO_GRC5 REG8(IT83XX_GPIO_BASE + 0xF4)
+#define IT83XX_GPIO_GRC6 REG8(IT83XX_GPIO_BASE + 0xF5)
+#define IT83XX_GPIO_GRC7 REG8(IT83XX_GPIO_BASE + 0xF6)
+#define IT83XX_GPIO_GRC8 REG8(IT83XX_GPIO_BASE + 0xF7)
+#define IT83XX_GPIO_GRC19 REG8(IT83XX_GPIO_BASE + 0xE4)
+#define IT83XX_GPIO_GRC20 REG8(IT83XX_GPIO_BASE + 0xE5)
+#define IT83XX_GPIO_GRC21 REG8(IT83XX_GPIO_BASE + 0xE6)
+#define IT83XX_GPIO_GRC22 REG8(IT83XX_GPIO_BASE + 0xE7)
+#define IT83XX_GPIO_GRC23 REG8(IT83XX_GPIO_BASE + 0xE8)
+#define IT83XX_GPIO_GRC24 REG8(IT83XX_GPIO_BASE + 0xE9)
+#define IT83XX_GPIO_GCR25 REG8(IT83XX_GPIO_BASE + 0xD1)
+#define IT83XX_GPIO_GCR26 REG8(IT83XX_GPIO_BASE + 0xD2)
+#define IT83XX_GPIO_GCR27 REG8(IT83XX_GPIO_BASE + 0xD3)
+#define IT83XX_GPIO_GCR28 REG8(IT83XX_GPIO_BASE + 0xD4)
+#define IT83XX_GPIO_GCR29 REG8(IT83XX_GPIO_BASE + 0xEE)
+#define IT83XX_GPIO_GCR30 REG8(IT83XX_GPIO_BASE + 0xED)
+#define IT83XX_GPIO_GCR31 REG8(IT83XX_GPIO_BASE + 0xD5)
+#define IT83XX_GPIO_GCR32 REG8(IT83XX_GPIO_BASE + 0xD6)
+#define IT83XX_GPIO_GCR33 REG8(IT83XX_GPIO_BASE + 0xD7)
+
+#define IT83XX_VBATPC_BGPOPSCR REG8(IT83XX_GPIO2_BASE + 0xF0)
+#define IT83XX_VBATPC_XLPIER REG8(IT83XX_GPIO2_BASE + 0xF5)
 
 enum {
 	/* GPIO group index */
@@ -839,26 +839,26 @@ struct gpio_reg_t {
 /* GPIO group index convert to GPIO data/output type/ctrl group address */
 static const struct gpio_reg_t gpio_group_to_reg[] = {
 	/*               GPDR(set),  GPDMR(get), GPOTR,      GPCR      */
-	[GPIO_A]     = { 0x00F01601, 0x00F01661, 0x00F01671, 0x00F01610 },
-	[GPIO_B]     = { 0x00F01602, 0x00F01662, 0x00F01672, 0x00F01618 },
-	[GPIO_C]     = { 0x00F01603, 0x00F01663, 0x00F01673, 0x00F01620 },
-	[GPIO_D]     = { 0x00F01604, 0x00F01664, 0x00F01674, 0x00F01628 },
-	[GPIO_E]     = { 0x00F01605, 0x00F01665, 0x00F01675, 0x00F01630 },
-	[GPIO_F]     = { 0x00F01606, 0x00F01666, 0x00F01676, 0x00F01638 },
-	[GPIO_G]     = { 0x00F01607, 0x00F01667, 0x00F01677, 0x00F01640 },
-	[GPIO_H]     = { 0x00F01608, 0x00F01668, 0x00F01678, 0x00F01648 },
-	[GPIO_I]     = { 0x00F01609, 0x00F01669, 0x00F01679, 0x00F01650 },
-	[GPIO_J]     = { 0x00F0160A, 0x00F0166A, 0x00F0167A, 0x00F01658 },
-	[GPIO_K]     = { 0x00F0160B, 0x00F0166B, 0x00F0167B, 0x00F01690 },
-	[GPIO_L]     = { 0x00F0160C, 0x00F0166C, 0x00F0167C, 0x00F01698 },
-	[GPIO_M]     = { 0x00F0160D, 0x00F0166D, 0x00F0167D, 0x00F016a0 },
+	[GPIO_A] = { 0x00F01601, 0x00F01661, 0x00F01671, 0x00F01610 },
+	[GPIO_B] = { 0x00F01602, 0x00F01662, 0x00F01672, 0x00F01618 },
+	[GPIO_C] = { 0x00F01603, 0x00F01663, 0x00F01673, 0x00F01620 },
+	[GPIO_D] = { 0x00F01604, 0x00F01664, 0x00F01674, 0x00F01628 },
+	[GPIO_E] = { 0x00F01605, 0x00F01665, 0x00F01675, 0x00F01630 },
+	[GPIO_F] = { 0x00F01606, 0x00F01666, 0x00F01676, 0x00F01638 },
+	[GPIO_G] = { 0x00F01607, 0x00F01667, 0x00F01677, 0x00F01640 },
+	[GPIO_H] = { 0x00F01608, 0x00F01668, 0x00F01678, 0x00F01648 },
+	[GPIO_I] = { 0x00F01609, 0x00F01669, 0x00F01679, 0x00F01650 },
+	[GPIO_J] = { 0x00F0160A, 0x00F0166A, 0x00F0167A, 0x00F01658 },
+	[GPIO_K] = { 0x00F0160B, 0x00F0166B, 0x00F0167B, 0x00F01690 },
+	[GPIO_L] = { 0x00F0160C, 0x00F0166C, 0x00F0167C, 0x00F01698 },
+	[GPIO_M] = { 0x00F0160D, 0x00F0166D, 0x00F0167D, 0x00F016a0 },
 #if defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2)
-	[GPIO_O]     = { 0x00F03E01, 0x00F03E61, 0x00F03E71, 0x00F03E10 },
-	[GPIO_P]     = { 0x00F03E02, 0x00F03E62, 0x00F03E72, 0x00F03E18 },
-	[GPIO_Q]     = { 0x00F03E03, 0x00F03E63, 0x00F03E73, 0x00F03E20 },
-	[GPIO_R]     = { 0x00F03E04, 0x00F03E64, 0x00F03E74, 0x00F03E28 },
+	[GPIO_O] = { 0x00F03E01, 0x00F03E61, 0x00F03E71, 0x00F03E10 },
+	[GPIO_P] = { 0x00F03E02, 0x00F03E62, 0x00F03E72, 0x00F03E18 },
+	[GPIO_Q] = { 0x00F03E03, 0x00F03E63, 0x00F03E73, 0x00F03E20 },
+	[GPIO_R] = { 0x00F03E04, 0x00F03E64, 0x00F03E74, 0x00F03E28 },
 #endif
-	[GPIO_KSI]   = { 0x00F01D08, 0x00F01D09, 0x00F01D26, 0xFFFFFFFF },
+	[GPIO_KSI] = { 0x00F01D08, 0x00F01D09, 0x00F01D26, 0xFFFFFFFF },
 	[GPIO_KSO_H] = { 0x00F01D01, 0x00F01D0C, 0x00F01D27, 0xFFFFFFFF },
 	[GPIO_KSO_L] = { 0x00F01D00, 0x00F01D0F, 0x00F01D28, 0xFFFFFFFF },
 };
@@ -866,43 +866,40 @@ BUILD_ASSERT(ARRAY_SIZE(gpio_group_to_reg) == (COUNT));
 
 #define UNIMPLEMENTED_GPIO_BANK GPIO_A
 
-#define IT83XX_GPIO_DATA(port)                 \
-	REG8(gpio_group_to_reg[port].reg_gpdr)
-#define IT83XX_GPIO_DATA_MIRROR(port)          \
-	REG8(gpio_group_to_reg[port].reg_gpdmr)
-#define IT83XX_GPIO_GPOT(port)                 \
-	REG8(gpio_group_to_reg[port].reg_gpotr)
-#define IT83XX_GPIO_CTRL(port, pin_offset)     \
+#define IT83XX_GPIO_DATA(port) REG8(gpio_group_to_reg[port].reg_gpdr)
+#define IT83XX_GPIO_DATA_MIRROR(port) REG8(gpio_group_to_reg[port].reg_gpdmr)
+#define IT83XX_GPIO_GPOT(port) REG8(gpio_group_to_reg[port].reg_gpotr)
+#define IT83XX_GPIO_CTRL(port, pin_offset) \
 	REG8(gpio_group_to_reg[port].reg_gpcr + pin_offset)
-#define GPCR_PORT_PIN_MODE_INPUT          BIT(7)
-#define GPCR_PORT_PIN_MODE_OUTPUT         BIT(6)
-#define GPCR_PORT_PIN_MODE_PULLUP         BIT(2)
-#define GPCR_PORT_PIN_MODE_PULLDOWN       BIT(1)
+#define GPCR_PORT_PIN_MODE_INPUT BIT(7)
+#define GPCR_PORT_PIN_MODE_OUTPUT BIT(6)
+#define GPCR_PORT_PIN_MODE_PULLUP BIT(2)
+#define GPCR_PORT_PIN_MODE_PULLDOWN BIT(1)
 
 /* --- Clock and Power Management (ECPM) --- */
 
-#define IT83XX_ECPM_BASE  0x00F01E00
+#define IT83XX_ECPM_BASE 0x00F01E00
 
 #define IT83XX_ECPM_CGCTRL1R_OFF 0x01
 #define IT83XX_ECPM_CGCTRL2R_OFF 0x02
 #define IT83XX_ECPM_CGCTRL3R_OFF 0x05
 #define IT83XX_ECPM_CGCTRL4R_OFF 0x09
 
-#define IT83XX_ECPM_PLLCTRL	REG8(IT83XX_ECPM_BASE+0x03)
+#define IT83XX_ECPM_PLLCTRL REG8(IT83XX_ECPM_BASE + 0x03)
 enum ec_pll_ctrl {
 	EC_PLL_DOZE = 0,
 	EC_PLL_SLEEP = 1,
 	EC_PLL_DEEP_DOZE = 3,
 };
 
-#define IT83XX_ECPM_AUTOCG	REG8(IT83XX_ECPM_BASE+0x04)
-#define IT83XX_ECPM_PLLFREQR	REG8(IT83XX_ECPM_BASE+0x06)
-#define IT83XX_ECPM_PLLCSS	REG8(IT83XX_ECPM_BASE+0x08)
-#define IT83XX_ECPM_SCDCR0	REG8(IT83XX_ECPM_BASE+0x0c)
-#define IT83XX_ECPM_SCDCR1	REG8(IT83XX_ECPM_BASE+0x0d)
-#define IT83XX_ECPM_SCDCR2	REG8(IT83XX_ECPM_BASE+0x0e)
-#define IT83XX_ECPM_SCDCR3	REG8(IT83XX_ECPM_BASE+0x0f)
-#define IT83XX_ECPM_SCDCR4	REG8(IT83XX_ECPM_BASE+0x10)
+#define IT83XX_ECPM_AUTOCG REG8(IT83XX_ECPM_BASE + 0x04)
+#define IT83XX_ECPM_PLLFREQR REG8(IT83XX_ECPM_BASE + 0x06)
+#define IT83XX_ECPM_PLLCSS REG8(IT83XX_ECPM_BASE + 0x08)
+#define IT83XX_ECPM_SCDCR0 REG8(IT83XX_ECPM_BASE + 0x0c)
+#define IT83XX_ECPM_SCDCR1 REG8(IT83XX_ECPM_BASE + 0x0d)
+#define IT83XX_ECPM_SCDCR2 REG8(IT83XX_ECPM_BASE + 0x0e)
+#define IT83XX_ECPM_SCDCR3 REG8(IT83XX_ECPM_BASE + 0x0f)
+#define IT83XX_ECPM_SCDCR4 REG8(IT83XX_ECPM_BASE + 0x10)
 
 /*
  * The clock gate offsets combine the register offset from ECPM_BASE and the
@@ -910,528 +907,528 @@ enum ec_pll_ctrl {
  * clock_enable_peripheral() and clock_disable_peripheral()
  */
 enum clock_gate_offsets {
-	CGC_OFFSET_EGPC  = ((IT83XX_ECPM_CGCTRL2R_OFF << 8) | 0x40),
-	CGC_OFFSET_CIR   = ((IT83XX_ECPM_CGCTRL2R_OFF << 8) | 0x20),
-	CGC_OFFSET_SWUC  = ((IT83XX_ECPM_CGCTRL2R_OFF << 8) | 0x10),
-	CGC_OFFSET_USB   = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x20),
-	CGC_OFFSET_PECI  = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x08),
-	CGC_OFFSET_UART  = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x04),
-	CGC_OFFSET_SSPI  = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x02),
-	CGC_OFFSET_DBGR  = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x01),
-	CGC_OFFSET_SMBF  = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x80),
-	CGC_OFFSET_SMBE  = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x40),
-	CGC_OFFSET_SMBD  = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x20),
-	CGC_OFFSET_SMBC  = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x10),
-	CGC_OFFSET_SMBB  = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x08),
-	CGC_OFFSET_SMBA  = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x04),
-	CGC_OFFSET_SMB   = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x02),
-	CGC_OFFSET_CEC   = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x01)
+	CGC_OFFSET_EGPC = ((IT83XX_ECPM_CGCTRL2R_OFF << 8) | 0x40),
+	CGC_OFFSET_CIR = ((IT83XX_ECPM_CGCTRL2R_OFF << 8) | 0x20),
+	CGC_OFFSET_SWUC = ((IT83XX_ECPM_CGCTRL2R_OFF << 8) | 0x10),
+	CGC_OFFSET_USB = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x20),
+	CGC_OFFSET_PECI = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x08),
+	CGC_OFFSET_UART = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x04),
+	CGC_OFFSET_SSPI = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x02),
+	CGC_OFFSET_DBGR = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x01),
+	CGC_OFFSET_SMBF = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x80),
+	CGC_OFFSET_SMBE = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x40),
+	CGC_OFFSET_SMBD = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x20),
+	CGC_OFFSET_SMBC = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x10),
+	CGC_OFFSET_SMBB = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x08),
+	CGC_OFFSET_SMBA = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x04),
+	CGC_OFFSET_SMB = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x02),
+	CGC_OFFSET_CEC = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x01)
 };
 
 /* --- Timer (TMR) --- */
-#define IT83XX_TMR_BASE         0x00F02900
-
-#define IT83XX_TMR_PRSC         REG8(IT83XX_TMR_BASE+0x00)
-#define IT83XX_TMR_GCSMS        REG8(IT83XX_TMR_BASE+0x01)
-#define IT83XX_TMR_CTR_A0       REG8(IT83XX_TMR_BASE+0x02)
-#define IT83XX_TMR_CTR_A1       REG8(IT83XX_TMR_BASE+0x03)
-#define IT83XX_TMR_CTR_B0       REG8(IT83XX_TMR_BASE+0x04)
-#define IT83XX_TMR_CTR_B1       REG8(IT83XX_TMR_BASE+0x05)
-#define IT83XX_TMR_DCR_A0       REG8(IT83XX_TMR_BASE+0x06)
-#define IT83XX_TMR_DCR_A1       REG8(IT83XX_TMR_BASE+0x07)
-#define IT83XX_TMR_DCR_B0       REG8(IT83XX_TMR_BASE+0x08)
-#define IT83XX_TMR_DCR_B1       REG8(IT83XX_TMR_BASE+0x09)
-#define IT83XX_TMR_CCGSR        REG8(IT83XX_TMR_BASE+0x0A)
-#define IT83XX_TMR_TMRCE        REG8(IT83XX_TMR_BASE+0x0B)
-#define IT83XX_TMR_TMRIE        REG8(IT83XX_TMR_BASE+0x0C)
+#define IT83XX_TMR_BASE 0x00F02900
+
+#define IT83XX_TMR_PRSC REG8(IT83XX_TMR_BASE + 0x00)
+#define IT83XX_TMR_GCSMS REG8(IT83XX_TMR_BASE + 0x01)
+#define IT83XX_TMR_CTR_A0 REG8(IT83XX_TMR_BASE + 0x02)
+#define IT83XX_TMR_CTR_A1 REG8(IT83XX_TMR_BASE + 0x03)
+#define IT83XX_TMR_CTR_B0 REG8(IT83XX_TMR_BASE + 0x04)
+#define IT83XX_TMR_CTR_B1 REG8(IT83XX_TMR_BASE + 0x05)
+#define IT83XX_TMR_DCR_A0 REG8(IT83XX_TMR_BASE + 0x06)
+#define IT83XX_TMR_DCR_A1 REG8(IT83XX_TMR_BASE + 0x07)
+#define IT83XX_TMR_DCR_B0 REG8(IT83XX_TMR_BASE + 0x08)
+#define IT83XX_TMR_DCR_B1 REG8(IT83XX_TMR_BASE + 0x09)
+#define IT83XX_TMR_CCGSR REG8(IT83XX_TMR_BASE + 0x0A)
+#define IT83XX_TMR_TMRCE REG8(IT83XX_TMR_BASE + 0x0B)
+#define IT83XX_TMR_TMRIE REG8(IT83XX_TMR_BASE + 0x0C)
 
 /* --- External Timer and Watchdog (ETWD) --- */
-#define IT83XX_ETWD_BASE  0x00F01F00
-
-#define IT83XX_ETWD_ETWCFG        REG8(IT83XX_ETWD_BASE+0x01)
-#define IT83XX_ETWD_ET1PSR        REG8(IT83XX_ETWD_BASE+0x02)
-#define IT83XX_ETWD_ET1CNTLHR     REG8(IT83XX_ETWD_BASE+0x03)
-#define IT83XX_ETWD_ET1CNTLLR     REG8(IT83XX_ETWD_BASE+0x04)
-#define IT83XX_ETWD_ETWCTRL       REG8(IT83XX_ETWD_BASE+0x05)
-#define IT83XX_ETWD_EWDCNTLLR     REG8(IT83XX_ETWD_BASE+0x06)
-#define IT83XX_ETWD_EWDKEYR       REG8(IT83XX_ETWD_BASE+0x07)
-#define IT83XX_ETWD_EWDCNTLHR     REG8(IT83XX_ETWD_BASE+0x09)
-#define IT83XX_ETWD_ETXCTRL(n)    REG8(IT83XX_ETWD_BASE + 0x10 + (n << 3))
-#define IT83XX_ETWD_ETXPSR(n)     REG8(IT83XX_ETWD_BASE + 0x11 + (n << 3))
-#define IT83XX_ETWD_ETXCNTLR(n)   REG32(IT83XX_ETWD_BASE + 0x14 + (n << 3))
-#define IT83XX_ETWD_ETXCNTOR(n)   REG32(IT83XX_ETWD_BASE + 0x48 + (n << 2))
+#define IT83XX_ETWD_BASE 0x00F01F00
+
+#define IT83XX_ETWD_ETWCFG REG8(IT83XX_ETWD_BASE + 0x01)
+#define IT83XX_ETWD_ET1PSR REG8(IT83XX_ETWD_BASE + 0x02)
+#define IT83XX_ETWD_ET1CNTLHR REG8(IT83XX_ETWD_BASE + 0x03)
+#define IT83XX_ETWD_ET1CNTLLR REG8(IT83XX_ETWD_BASE + 0x04)
+#define IT83XX_ETWD_ETWCTRL REG8(IT83XX_ETWD_BASE + 0x05)
+#define IT83XX_ETWD_EWDCNTLLR REG8(IT83XX_ETWD_BASE + 0x06)
+#define IT83XX_ETWD_EWDKEYR REG8(IT83XX_ETWD_BASE + 0x07)
+#define IT83XX_ETWD_EWDCNTLHR REG8(IT83XX_ETWD_BASE + 0x09)
+#define IT83XX_ETWD_ETXCTRL(n) REG8(IT83XX_ETWD_BASE + 0x10 + (n << 3))
+#define IT83XX_ETWD_ETXPSR(n) REG8(IT83XX_ETWD_BASE + 0x11 + (n << 3))
+#define IT83XX_ETWD_ETXCNTLR(n) REG32(IT83XX_ETWD_BASE + 0x14 + (n << 3))
+#define IT83XX_ETWD_ETXCNTOR(n) REG32(IT83XX_ETWD_BASE + 0x48 + (n << 2))
 
 /* --- General Control (GCTRL) --- */
 #define IT83XX_GCTRL_BASE 0x00F02000
 
 #ifdef IT83XX_CHIP_ID_3BYTES
-#define IT83XX_GCTRL_CHIPID1      REG8(IT83XX_GCTRL_BASE+0x85)
-#define IT83XX_GCTRL_CHIPID2      REG8(IT83XX_GCTRL_BASE+0x86)
-#define IT83XX_GCTRL_CHIPID3      REG8(IT83XX_GCTRL_BASE+0x87)
+#define IT83XX_GCTRL_CHIPID1 REG8(IT83XX_GCTRL_BASE + 0x85)
+#define IT83XX_GCTRL_CHIPID2 REG8(IT83XX_GCTRL_BASE + 0x86)
+#define IT83XX_GCTRL_CHIPID3 REG8(IT83XX_GCTRL_BASE + 0x87)
 #else
-#define IT83XX_GCTRL_CHIPID1      REG8(IT83XX_GCTRL_BASE+0x00)
-#define IT83XX_GCTRL_CHIPID2      REG8(IT83XX_GCTRL_BASE+0x01)
+#define IT83XX_GCTRL_CHIPID1 REG8(IT83XX_GCTRL_BASE + 0x00)
+#define IT83XX_GCTRL_CHIPID2 REG8(IT83XX_GCTRL_BASE + 0x01)
 #endif
-#define IT83XX_GCTRL_CHIPVER      REG8(IT83XX_GCTRL_BASE+0x02)
-#define IT83XX_GCTRL_DBGROS       REG8(IT83XX_GCTRL_BASE+0x03)
-#define IT83XX_SMB_DBGR           BIT(0)
-#define IT83XX_GCTRL_WNCKR        REG8(IT83XX_GCTRL_BASE+0x0B)
-#define IT83XX_GCTRL_RSTS         REG8(IT83XX_GCTRL_BASE+0x06)
-#define IT83XX_GCTRL_BADRSEL      REG8(IT83XX_GCTRL_BASE+0x0A)
-#define IT83XX_GCTRL_SPCTRL1      REG8(IT83XX_GCTRL_BASE+0x0D)
-#define IT83XX_GCTRL_RSTDMMC      REG8(IT83XX_GCTRL_BASE+0x10)
-#define IT83XX_GCTRL_RSTC4        REG8(IT83XX_GCTRL_BASE+0x11)
-#define IT83XX_GCTRL_SPCTRL4      REG8(IT83XX_GCTRL_BASE+0x1C)
-#define IT83XX_GCTRL_MCCR3        REG8(IT83XX_GCTRL_BASE+0x20)
-#define IT83XX_GCTRL_SPISLVPFE    BIT(6)
-#define IT83XX_GCTRL_RSTC5        REG8(IT83XX_GCTRL_BASE+0x21)
-#define IT83XX_GCTRL_MCCR         REG8(IT83XX_GCTRL_BASE+0x30)
-#define IT83XX_GCTRL_PMER1        REG8(IT83XX_GCTRL_BASE+0x32)
-#define IT83XX_GCTRL_PMER2        REG8(IT83XX_GCTRL_BASE+0x33)
-#define IT83XX_GCTRL_EPLR         REG8(IT83XX_GCTRL_BASE+0x37)
-#define IT83XX_GCTRL_IVTBAR       REG8(IT83XX_GCTRL_BASE+0x41)
-#define IT83XX_GCTRL_MCCR2        REG8(IT83XX_GCTRL_BASE+0x44)
-#define IT83XX_GCTRL_PIN_MUX0     REG8(IT83XX_GCTRL_BASE+0x46)
-#define IT83XX_DLM14_ENABLE       BIT(5)
-#define IT83XX_GCTRL_SSCR         REG8(IT83XX_GCTRL_BASE+0x4A)
-#define IT83XX_GCTRL_ETWDUARTCR   REG8(IT83XX_GCTRL_BASE+0x4B)
-#define IT83XX_GCTRL_WMCR         REG8(IT83XX_GCTRL_BASE+0x4C)
-#define IT83XX_GCTRL_H2ROFSR      REG8(IT83XX_GCTRL_BASE+0x53)
+#define IT83XX_GCTRL_CHIPVER REG8(IT83XX_GCTRL_BASE + 0x02)
+#define IT83XX_GCTRL_DBGROS REG8(IT83XX_GCTRL_BASE + 0x03)
+#define IT83XX_SMB_DBGR BIT(0)
+#define IT83XX_GCTRL_WNCKR REG8(IT83XX_GCTRL_BASE + 0x0B)
+#define IT83XX_GCTRL_RSTS REG8(IT83XX_GCTRL_BASE + 0x06)
+#define IT83XX_GCTRL_BADRSEL REG8(IT83XX_GCTRL_BASE + 0x0A)
+#define IT83XX_GCTRL_SPCTRL1 REG8(IT83XX_GCTRL_BASE + 0x0D)
+#define IT83XX_GCTRL_RSTDMMC REG8(IT83XX_GCTRL_BASE + 0x10)
+#define IT83XX_GCTRL_RSTC4 REG8(IT83XX_GCTRL_BASE + 0x11)
+#define IT83XX_GCTRL_SPCTRL4 REG8(IT83XX_GCTRL_BASE + 0x1C)
+#define IT83XX_GCTRL_MCCR3 REG8(IT83XX_GCTRL_BASE + 0x20)
+#define IT83XX_GCTRL_SPISLVPFE BIT(6)
+#define IT83XX_GCTRL_RSTC5 REG8(IT83XX_GCTRL_BASE + 0x21)
+#define IT83XX_GCTRL_MCCR REG8(IT83XX_GCTRL_BASE + 0x30)
+#define IT83XX_GCTRL_PMER1 REG8(IT83XX_GCTRL_BASE + 0x32)
+#define IT83XX_GCTRL_PMER2 REG8(IT83XX_GCTRL_BASE + 0x33)
+#define IT83XX_GCTRL_EPLR REG8(IT83XX_GCTRL_BASE + 0x37)
+#define IT83XX_GCTRL_IVTBAR REG8(IT83XX_GCTRL_BASE + 0x41)
+#define IT83XX_GCTRL_MCCR2 REG8(IT83XX_GCTRL_BASE + 0x44)
+#define IT83XX_GCTRL_PIN_MUX0 REG8(IT83XX_GCTRL_BASE + 0x46)
+#define IT83XX_DLM14_ENABLE BIT(5)
+#define IT83XX_GCTRL_SSCR REG8(IT83XX_GCTRL_BASE + 0x4A)
+#define IT83XX_GCTRL_ETWDUARTCR REG8(IT83XX_GCTRL_BASE + 0x4B)
+#define IT83XX_GCTRL_WMCR REG8(IT83XX_GCTRL_BASE + 0x4C)
+#define IT83XX_GCTRL_H2ROFSR REG8(IT83XX_GCTRL_BASE + 0x53)
 /* bit[0] = 0 or 1 : disable or enable ETWD hardware reset */
-#define ETWD_HW_RST_EN            BIT(0)
-#define IT83XX_GCTRL_RVILMCR0     REG8(IT83XX_GCTRL_BASE+0x5D)
-#define ILMCR_ILM0_ENABLE         BIT(0)
-#define ILMCR_ILM2_ENABLE         BIT(2)
-#define IT83XX_GCTRL_EWPR0PFH(i)  REG8(IT83XX_GCTRL_BASE+0x60+i)
-#define IT83XX_GCTRL_EWPR0PFD(i)  REG8(IT83XX_GCTRL_BASE+0xA0+i)
-#define IT83XX_GCTRL_EWPR0PFEC(i) REG8(IT83XX_GCTRL_BASE+0xC0+i)
+#define ETWD_HW_RST_EN BIT(0)
+#define IT83XX_GCTRL_RVILMCR0 REG8(IT83XX_GCTRL_BASE + 0x5D)
+#define ILMCR_ILM0_ENABLE BIT(0)
+#define ILMCR_ILM2_ENABLE BIT(2)
+#define IT83XX_GCTRL_EWPR0PFH(i) REG8(IT83XX_GCTRL_BASE + 0x60 + i)
+#define IT83XX_GCTRL_EWPR0PFD(i) REG8(IT83XX_GCTRL_BASE + 0xA0 + i)
+#define IT83XX_GCTRL_EWPR0PFEC(i) REG8(IT83XX_GCTRL_BASE + 0xC0 + i)
 
 /* --- Pulse Width Modulation (PWM) --- */
-#define IT83XX_PWM_BASE   0x00F01800
-
-#define IT83XX_PWM_C0CPRS       REG8(IT83XX_PWM_BASE+0x00)
-#define IT83XX_PWM_CTR          REG8(IT83XX_PWM_BASE+0x01)
-#define IT83XX_PWM_DCR0         REG8(IT83XX_PWM_BASE+0x02)
-#define IT83XX_PWM_DCR1         REG8(IT83XX_PWM_BASE+0x03)
-#define IT83XX_PWM_DCR2         REG8(IT83XX_PWM_BASE+0x04)
-#define IT83XX_PWM_DCR3         REG8(IT83XX_PWM_BASE+0x05)
-#define IT83XX_PWM_DCR4         REG8(IT83XX_PWM_BASE+0x06)
-#define IT83XX_PWM_DCR5         REG8(IT83XX_PWM_BASE+0x07)
-#define IT83XX_PWM_DCR6         REG8(IT83XX_PWM_BASE+0x08)
-#define IT83XX_PWM_DCR7         REG8(IT83XX_PWM_BASE+0x09)
-#define IT83XX_PWM_PWMPOL       REG8(IT83XX_PWM_BASE+0x0A)
-#define IT83XX_PWM_PCFSR        REG8(IT83XX_PWM_BASE+0x0B)
-#define IT83XX_PWM_PCSSGL       REG8(IT83XX_PWM_BASE+0x0C)
-#define IT83XX_PWM_PCSSGH       REG8(IT83XX_PWM_BASE+0x0D)
-#define IT83XX_PWM_CR256PCSSG   REG8(IT83XX_PWM_BASE+0x0E)
-#define IT83XX_PWM_PCSGR        REG8(IT83XX_PWM_BASE+0x0F)
-#define IT83XX_PWM_CTR1M        REG8(IT83XX_PWM_BASE+0x10)
-#define IT83XX_PWM_F1TLRR       REG8(IT83XX_PWM_BASE+0x1E)
-#define IT83XX_PWM_F1TMRR       REG8(IT83XX_PWM_BASE+0x1F)
-#define IT83XX_PWM_F2TLRR       REG8(IT83XX_PWM_BASE+0x20)
-#define IT83XX_PWM_F2TMRR       REG8(IT83XX_PWM_BASE+0x21)
-#define IT83XX_PWM_ZINTSCR      REG8(IT83XX_PWM_BASE+0x22)
-#define IT83XX_PWM_ZTIER        REG8(IT83XX_PWM_BASE+0x23)
-#define IT83XX_PWM_TSWCTLR      REG8(IT83XX_PWM_BASE+0x24)
-#define IT83XX_PWM_C4CPRS       REG8(IT83XX_PWM_BASE+0x27)
-#define IT83XX_PWM_C4MCPRS      REG8(IT83XX_PWM_BASE+0x28)
-#define IT83XX_PWM_C6CPRS       REG8(IT83XX_PWM_BASE+0x2B)
-#define IT83XX_PWM_C6MCPRS      REG8(IT83XX_PWM_BASE+0x2C)
-#define IT83XX_PWM_C7CPRS       REG8(IT83XX_PWM_BASE+0x2D)
-#define IT83XX_PWM_C7MCPRS      REG8(IT83XX_PWM_BASE+0x2E)
-#define IT83XX_PWM_CLK6MSEL     REG8(IT83XX_PWM_BASE+0x40)
-#define IT83XX_PWM_CTR1         REG8(IT83XX_PWM_BASE+0x41)
-#define IT83XX_PWM_CTR2         REG8(IT83XX_PWM_BASE+0x42)
-#define IT83XX_PWM_CTR3         REG8(IT83XX_PWM_BASE+0x43)
-#define IT83XX_PWM_PWM5TOCTRL   REG8(IT83XX_PWM_BASE+0x44)
-#define IT83XX_PWM_CFLRR        REG8(IT83XX_PWM_BASE+0x45)
-#define IT83XX_PWM_CFMRR        REG8(IT83XX_PWM_BASE+0x46)
-#define IT83XX_PWM_CFINTCTRL    REG8(IT83XX_PWM_BASE+0x47)
-#define IT83XX_PWM_TSWCTRL      REG8(IT83XX_PWM_BASE+0x48)
-#define IT83XX_PWM_PWMODENR     REG8(IT83XX_PWM_BASE+0x49)
+#define IT83XX_PWM_BASE 0x00F01800
+
+#define IT83XX_PWM_C0CPRS REG8(IT83XX_PWM_BASE + 0x00)
+#define IT83XX_PWM_CTR REG8(IT83XX_PWM_BASE + 0x01)
+#define IT83XX_PWM_DCR0 REG8(IT83XX_PWM_BASE + 0x02)
+#define IT83XX_PWM_DCR1 REG8(IT83XX_PWM_BASE + 0x03)
+#define IT83XX_PWM_DCR2 REG8(IT83XX_PWM_BASE + 0x04)
+#define IT83XX_PWM_DCR3 REG8(IT83XX_PWM_BASE + 0x05)
+#define IT83XX_PWM_DCR4 REG8(IT83XX_PWM_BASE + 0x06)
+#define IT83XX_PWM_DCR5 REG8(IT83XX_PWM_BASE + 0x07)
+#define IT83XX_PWM_DCR6 REG8(IT83XX_PWM_BASE + 0x08)
+#define IT83XX_PWM_DCR7 REG8(IT83XX_PWM_BASE + 0x09)
+#define IT83XX_PWM_PWMPOL REG8(IT83XX_PWM_BASE + 0x0A)
+#define IT83XX_PWM_PCFSR REG8(IT83XX_PWM_BASE + 0x0B)
+#define IT83XX_PWM_PCSSGL REG8(IT83XX_PWM_BASE + 0x0C)
+#define IT83XX_PWM_PCSSGH REG8(IT83XX_PWM_BASE + 0x0D)
+#define IT83XX_PWM_CR256PCSSG REG8(IT83XX_PWM_BASE + 0x0E)
+#define IT83XX_PWM_PCSGR REG8(IT83XX_PWM_BASE + 0x0F)
+#define IT83XX_PWM_CTR1M REG8(IT83XX_PWM_BASE + 0x10)
+#define IT83XX_PWM_F1TLRR REG8(IT83XX_PWM_BASE + 0x1E)
+#define IT83XX_PWM_F1TMRR REG8(IT83XX_PWM_BASE + 0x1F)
+#define IT83XX_PWM_F2TLRR REG8(IT83XX_PWM_BASE + 0x20)
+#define IT83XX_PWM_F2TMRR REG8(IT83XX_PWM_BASE + 0x21)
+#define IT83XX_PWM_ZINTSCR REG8(IT83XX_PWM_BASE + 0x22)
+#define IT83XX_PWM_ZTIER REG8(IT83XX_PWM_BASE + 0x23)
+#define IT83XX_PWM_TSWCTLR REG8(IT83XX_PWM_BASE + 0x24)
+#define IT83XX_PWM_C4CPRS REG8(IT83XX_PWM_BASE + 0x27)
+#define IT83XX_PWM_C4MCPRS REG8(IT83XX_PWM_BASE + 0x28)
+#define IT83XX_PWM_C6CPRS REG8(IT83XX_PWM_BASE + 0x2B)
+#define IT83XX_PWM_C6MCPRS REG8(IT83XX_PWM_BASE + 0x2C)
+#define IT83XX_PWM_C7CPRS REG8(IT83XX_PWM_BASE + 0x2D)
+#define IT83XX_PWM_C7MCPRS REG8(IT83XX_PWM_BASE + 0x2E)
+#define IT83XX_PWM_CLK6MSEL REG8(IT83XX_PWM_BASE + 0x40)
+#define IT83XX_PWM_CTR1 REG8(IT83XX_PWM_BASE + 0x41)
+#define IT83XX_PWM_CTR2 REG8(IT83XX_PWM_BASE + 0x42)
+#define IT83XX_PWM_CTR3 REG8(IT83XX_PWM_BASE + 0x43)
+#define IT83XX_PWM_PWM5TOCTRL REG8(IT83XX_PWM_BASE + 0x44)
+#define IT83XX_PWM_CFLRR REG8(IT83XX_PWM_BASE + 0x45)
+#define IT83XX_PWM_CFMRR REG8(IT83XX_PWM_BASE + 0x46)
+#define IT83XX_PWM_CFINTCTRL REG8(IT83XX_PWM_BASE + 0x47)
+#define IT83XX_PWM_TSWCTRL REG8(IT83XX_PWM_BASE + 0x48)
+#define IT83XX_PWM_PWMODENR REG8(IT83XX_PWM_BASE + 0x49)
 
 /* Analog to Digital Converter (ADC) */
-#define IT83XX_ADC_BASE   0x00F01900
-
-#define IT83XX_ADC_ADCSTS       REG8(IT83XX_ADC_BASE+0x00)
-#define IT83XX_ADC_ADCCFG       REG8(IT83XX_ADC_BASE+0x01)
-#define IT83XX_ADC_ADCCTL       REG8(IT83XX_ADC_BASE+0x02)
-#define IT83XX_ADC_ADCGCR       REG8(IT83XX_ADC_BASE+0x03)
-#define IT83XX_ADC_DBKEN            BIT(7) /* ADC data buffer keep enable. */
-#define IT83XX_ADC_VCH0CTL      REG8(IT83XX_ADC_BASE+0x04)
-#define IT83XX_ADC_KDCTL        REG8(IT83XX_ADC_BASE+0x05)
-#define IT83XX_ADC_AHCE             BIT(7)
-#define IT83XX_ADC_VCH1CTL      REG8(IT83XX_ADC_BASE+0x06)
-#define IT83XX_ADC_VCH1DATL     REG8(IT83XX_ADC_BASE+0x07)
-#define IT83XX_ADC_VCH1DATM     REG8(IT83XX_ADC_BASE+0x08)
-#define IT83XX_ADC_VCH2CTL      REG8(IT83XX_ADC_BASE+0x09)
-#define IT83XX_ADC_VCH2DATL     REG8(IT83XX_ADC_BASE+0x0A)
-#define IT83XX_ADC_VCH2DATM     REG8(IT83XX_ADC_BASE+0x0B)
-#define IT83XX_ADC_VCH3CTL      REG8(IT83XX_ADC_BASE+0x0C)
-#define IT83XX_ADC_VCH3DATL     REG8(IT83XX_ADC_BASE+0x0D)
-#define IT83XX_ADC_VCH3DATM     REG8(IT83XX_ADC_BASE+0x0E)
-#define IT83XX_ADC_VHSCDBL      REG8(IT83XX_ADC_BASE+0x14)
-#define IT83XX_ADC_VHSCDBM      REG8(IT83XX_ADC_BASE+0x15)
-#define IT83XX_ADC_VCH0DATL     REG8(IT83XX_ADC_BASE+0x18)
-#define IT83XX_ADC_VCH0DATM     REG8(IT83XX_ADC_BASE+0x19)
-#define IT83XX_ADC_VHSGCDBL     REG8(IT83XX_ADC_BASE+0x1C)
-#define IT83XX_ADC_VHSGCDBM     REG8(IT83XX_ADC_BASE+0x1D)
-#define IT83XX_ADC_ADCSAR       REG8(IT83XX_ADC_BASE+0x32)
-#define IT83XX_ADC_VCMPSCP      REG8(IT83XX_ADC_BASE+0x37)
-#define IT83XX_ADC_VCH4CTL      REG8(IT83XX_ADC_BASE+0x38)
-#define IT83XX_ADC_VCH4DATM     REG8(IT83XX_ADC_BASE+0x39)
-#define IT83XX_ADC_VCH4DATL     REG8(IT83XX_ADC_BASE+0x3A)
-#define IT83XX_ADC_VCH5CTL      REG8(IT83XX_ADC_BASE+0x3B)
-#define IT83XX_ADC_VCH5DATM     REG8(IT83XX_ADC_BASE+0x3C)
-#define IT83XX_ADC_VCH5DATL     REG8(IT83XX_ADC_BASE+0x3D)
-#define IT83XX_ADC_VCH6CTL      REG8(IT83XX_ADC_BASE+0x3E)
-#define IT83XX_ADC_VCH6DATM     REG8(IT83XX_ADC_BASE+0x3F)
-#define IT83XX_ADC_VCH6DATL     REG8(IT83XX_ADC_BASE+0x40)
-#define IT83XX_ADC_VCH7CTL      REG8(IT83XX_ADC_BASE+0x41)
-#define IT83XX_ADC_VCH7DATM     REG8(IT83XX_ADC_BASE+0x42)
-#define IT83XX_ADC_VCH7DATL     REG8(IT83XX_ADC_BASE+0x43)
-#define IT83XX_ADC_ADCDVSTS     REG8(IT83XX_ADC_BASE+0x44)
-#define IT83XX_ADC_VCMPSTS      REG8(IT83XX_ADC_BASE+0x45)
-#define IT83XX_ADC_VCMP0CTL     REG8(IT83XX_ADC_BASE+0x46)
-#define ADC_VCMP_CMPEN              BIT(7)
-#define ADC_VCMP_CMPINTEN           BIT(6)
-#define ADC_VCMP_GREATER_THRESHOLD  BIT(5)
-#define ADC_VCMP_EDGE_TRIGGER       BIT(4)
-#define ADC_VCMP_GPIO_ACTIVE_LOW    BIT(3)
-#define IT83XX_ADC_CMP0THRDATM  REG8(IT83XX_ADC_BASE+0x47)
-#define IT83XX_ADC_CMP0THRDATL  REG8(IT83XX_ADC_BASE+0x48)
-#define IT83XX_ADC_VCMP1CTL     REG8(IT83XX_ADC_BASE+0x49)
-#define IT83XX_ADC_CMP1THRDATM  REG8(IT83XX_ADC_BASE+0x4A)
-#define IT83XX_ADC_CMP1THRDATL  REG8(IT83XX_ADC_BASE+0x4B)
-#define IT83XX_ADC_VCMP2CTL     REG8(IT83XX_ADC_BASE+0x4C)
-#define IT83XX_ADC_CMP2THRDATM  REG8(IT83XX_ADC_BASE+0x4D)
-#define IT83XX_ADC_CMP2THRDATL  REG8(IT83XX_ADC_BASE+0x4E)
-#define IT83XX_ADC_VCH13CTL     REG8(IT83XX_ADC_BASE+0x60)
-#define IT83XX_ADC_VCH13DATM    REG8(IT83XX_ADC_BASE+0x61)
-#define IT83XX_ADC_VCH13DATL    REG8(IT83XX_ADC_BASE+0x62)
-#define IT83XX_ADC_VCH14CTL     REG8(IT83XX_ADC_BASE+0x63)
-#define IT83XX_ADC_VCH14DATM    REG8(IT83XX_ADC_BASE+0x64)
-#define IT83XX_ADC_VCH14DATL    REG8(IT83XX_ADC_BASE+0x65)
-#define IT83XX_ADC_VCH15CTL     REG8(IT83XX_ADC_BASE+0x66)
-#define IT83XX_ADC_VCH15DATM    REG8(IT83XX_ADC_BASE+0x67)
-#define IT83XX_ADC_VCH15DATL    REG8(IT83XX_ADC_BASE+0x68)
-#define IT83XX_ADC_VCH16CTL     REG8(IT83XX_ADC_BASE+0x69)
-#define IT83XX_ADC_VCH16DATM    REG8(IT83XX_ADC_BASE+0x6A)
-#define IT83XX_ADC_VCH16DATL    REG8(IT83XX_ADC_BASE+0x6B)
-#define IT83XX_ADC_ADCDVSTS2    REG8(IT83XX_ADC_BASE+0x6C)
-#define IT83XX_ADC_VCMPSTS2     REG8(IT83XX_ADC_BASE+0x6D)
-#define IT83XX_ADC_VCMP3CTL     REG8(IT83XX_ADC_BASE+0x6E)
-#define IT83XX_ADC_CMP3THRDATM  REG8(IT83XX_ADC_BASE+0x6F)
-#define IT83XX_ADC_CMP3THRDATL  REG8(IT83XX_ADC_BASE+0x70)
-#define IT83XX_ADC_VCMP4CTL     REG8(IT83XX_ADC_BASE+0x71)
-#define IT83XX_ADC_CMP4THRDATM  REG8(IT83XX_ADC_BASE+0x72)
-#define IT83XX_ADC_CMP4THRDATL  REG8(IT83XX_ADC_BASE+0x73)
-#define IT83XX_ADC_VCMP5CTL     REG8(IT83XX_ADC_BASE+0x74)
-#define IT83XX_ADC_CMP5THRDATM  REG8(IT83XX_ADC_BASE+0x75)
-#define IT83XX_ADC_CMP5THRDATL  REG8(IT83XX_ADC_BASE+0x76)
-#define IT83XX_ADC_VCMP0CSELM   REG8(IT83XX_ADC_BASE+0x77)
-#define ADC_VCMP_VCMPCSELM          BIT(0)
-#define IT83XX_ADC_VCMP1CSELM   REG8(IT83XX_ADC_BASE+0x78)
-#define IT83XX_ADC_VCMP2CSELM   REG8(IT83XX_ADC_BASE+0x79)
-#define IT83XX_ADC_VCMP3CSELM   REG8(IT83XX_ADC_BASE+0x7A)
-#define IT83XX_ADC_VCMP4CSELM   REG8(IT83XX_ADC_BASE+0x7B)
-#define IT83XX_ADC_VCMP5CSELM   REG8(IT83XX_ADC_BASE+0x7C)
+#define IT83XX_ADC_BASE 0x00F01900
+
+#define IT83XX_ADC_ADCSTS REG8(IT83XX_ADC_BASE + 0x00)
+#define IT83XX_ADC_ADCCFG REG8(IT83XX_ADC_BASE + 0x01)
+#define IT83XX_ADC_ADCCTL REG8(IT83XX_ADC_BASE + 0x02)
+#define IT83XX_ADC_ADCGCR REG8(IT83XX_ADC_BASE + 0x03)
+#define IT83XX_ADC_DBKEN BIT(7) /* ADC data buffer keep enable. */
+#define IT83XX_ADC_VCH0CTL REG8(IT83XX_ADC_BASE + 0x04)
+#define IT83XX_ADC_KDCTL REG8(IT83XX_ADC_BASE + 0x05)
+#define IT83XX_ADC_AHCE BIT(7)
+#define IT83XX_ADC_VCH1CTL REG8(IT83XX_ADC_BASE + 0x06)
+#define IT83XX_ADC_VCH1DATL REG8(IT83XX_ADC_BASE + 0x07)
+#define IT83XX_ADC_VCH1DATM REG8(IT83XX_ADC_BASE + 0x08)
+#define IT83XX_ADC_VCH2CTL REG8(IT83XX_ADC_BASE + 0x09)
+#define IT83XX_ADC_VCH2DATL REG8(IT83XX_ADC_BASE + 0x0A)
+#define IT83XX_ADC_VCH2DATM REG8(IT83XX_ADC_BASE + 0x0B)
+#define IT83XX_ADC_VCH3CTL REG8(IT83XX_ADC_BASE + 0x0C)
+#define IT83XX_ADC_VCH3DATL REG8(IT83XX_ADC_BASE + 0x0D)
+#define IT83XX_ADC_VCH3DATM REG8(IT83XX_ADC_BASE + 0x0E)
+#define IT83XX_ADC_VHSCDBL REG8(IT83XX_ADC_BASE + 0x14)
+#define IT83XX_ADC_VHSCDBM REG8(IT83XX_ADC_BASE + 0x15)
+#define IT83XX_ADC_VCH0DATL REG8(IT83XX_ADC_BASE + 0x18)
+#define IT83XX_ADC_VCH0DATM REG8(IT83XX_ADC_BASE + 0x19)
+#define IT83XX_ADC_VHSGCDBL REG8(IT83XX_ADC_BASE + 0x1C)
+#define IT83XX_ADC_VHSGCDBM REG8(IT83XX_ADC_BASE + 0x1D)
+#define IT83XX_ADC_ADCSAR REG8(IT83XX_ADC_BASE + 0x32)
+#define IT83XX_ADC_VCMPSCP REG8(IT83XX_ADC_BASE + 0x37)
+#define IT83XX_ADC_VCH4CTL REG8(IT83XX_ADC_BASE + 0x38)
+#define IT83XX_ADC_VCH4DATM REG8(IT83XX_ADC_BASE + 0x39)
+#define IT83XX_ADC_VCH4DATL REG8(IT83XX_ADC_BASE + 0x3A)
+#define IT83XX_ADC_VCH5CTL REG8(IT83XX_ADC_BASE + 0x3B)
+#define IT83XX_ADC_VCH5DATM REG8(IT83XX_ADC_BASE + 0x3C)
+#define IT83XX_ADC_VCH5DATL REG8(IT83XX_ADC_BASE + 0x3D)
+#define IT83XX_ADC_VCH6CTL REG8(IT83XX_ADC_BASE + 0x3E)
+#define IT83XX_ADC_VCH6DATM REG8(IT83XX_ADC_BASE + 0x3F)
+#define IT83XX_ADC_VCH6DATL REG8(IT83XX_ADC_BASE + 0x40)
+#define IT83XX_ADC_VCH7CTL REG8(IT83XX_ADC_BASE + 0x41)
+#define IT83XX_ADC_VCH7DATM REG8(IT83XX_ADC_BASE + 0x42)
+#define IT83XX_ADC_VCH7DATL REG8(IT83XX_ADC_BASE + 0x43)
+#define IT83XX_ADC_ADCDVSTS REG8(IT83XX_ADC_BASE + 0x44)
+#define IT83XX_ADC_VCMPSTS REG8(IT83XX_ADC_BASE + 0x45)
+#define IT83XX_ADC_VCMP0CTL REG8(IT83XX_ADC_BASE + 0x46)
+#define ADC_VCMP_CMPEN BIT(7)
+#define ADC_VCMP_CMPINTEN BIT(6)
+#define ADC_VCMP_GREATER_THRESHOLD BIT(5)
+#define ADC_VCMP_EDGE_TRIGGER BIT(4)
+#define ADC_VCMP_GPIO_ACTIVE_LOW BIT(3)
+#define IT83XX_ADC_CMP0THRDATM REG8(IT83XX_ADC_BASE + 0x47)
+#define IT83XX_ADC_CMP0THRDATL REG8(IT83XX_ADC_BASE + 0x48)
+#define IT83XX_ADC_VCMP1CTL REG8(IT83XX_ADC_BASE + 0x49)
+#define IT83XX_ADC_CMP1THRDATM REG8(IT83XX_ADC_BASE + 0x4A)
+#define IT83XX_ADC_CMP1THRDATL REG8(IT83XX_ADC_BASE + 0x4B)
+#define IT83XX_ADC_VCMP2CTL REG8(IT83XX_ADC_BASE + 0x4C)
+#define IT83XX_ADC_CMP2THRDATM REG8(IT83XX_ADC_BASE + 0x4D)
+#define IT83XX_ADC_CMP2THRDATL REG8(IT83XX_ADC_BASE + 0x4E)
+#define IT83XX_ADC_VCH13CTL REG8(IT83XX_ADC_BASE + 0x60)
+#define IT83XX_ADC_VCH13DATM REG8(IT83XX_ADC_BASE + 0x61)
+#define IT83XX_ADC_VCH13DATL REG8(IT83XX_ADC_BASE + 0x62)
+#define IT83XX_ADC_VCH14CTL REG8(IT83XX_ADC_BASE + 0x63)
+#define IT83XX_ADC_VCH14DATM REG8(IT83XX_ADC_BASE + 0x64)
+#define IT83XX_ADC_VCH14DATL REG8(IT83XX_ADC_BASE + 0x65)
+#define IT83XX_ADC_VCH15CTL REG8(IT83XX_ADC_BASE + 0x66)
+#define IT83XX_ADC_VCH15DATM REG8(IT83XX_ADC_BASE + 0x67)
+#define IT83XX_ADC_VCH15DATL REG8(IT83XX_ADC_BASE + 0x68)
+#define IT83XX_ADC_VCH16CTL REG8(IT83XX_ADC_BASE + 0x69)
+#define IT83XX_ADC_VCH16DATM REG8(IT83XX_ADC_BASE + 0x6A)
+#define IT83XX_ADC_VCH16DATL REG8(IT83XX_ADC_BASE + 0x6B)
+#define IT83XX_ADC_ADCDVSTS2 REG8(IT83XX_ADC_BASE + 0x6C)
+#define IT83XX_ADC_VCMPSTS2 REG8(IT83XX_ADC_BASE + 0x6D)
+#define IT83XX_ADC_VCMP3CTL REG8(IT83XX_ADC_BASE + 0x6E)
+#define IT83XX_ADC_CMP3THRDATM REG8(IT83XX_ADC_BASE + 0x6F)
+#define IT83XX_ADC_CMP3THRDATL REG8(IT83XX_ADC_BASE + 0x70)
+#define IT83XX_ADC_VCMP4CTL REG8(IT83XX_ADC_BASE + 0x71)
+#define IT83XX_ADC_CMP4THRDATM REG8(IT83XX_ADC_BASE + 0x72)
+#define IT83XX_ADC_CMP4THRDATL REG8(IT83XX_ADC_BASE + 0x73)
+#define IT83XX_ADC_VCMP5CTL REG8(IT83XX_ADC_BASE + 0x74)
+#define IT83XX_ADC_CMP5THRDATM REG8(IT83XX_ADC_BASE + 0x75)
+#define IT83XX_ADC_CMP5THRDATL REG8(IT83XX_ADC_BASE + 0x76)
+#define IT83XX_ADC_VCMP0CSELM REG8(IT83XX_ADC_BASE + 0x77)
+#define ADC_VCMP_VCMPCSELM BIT(0)
+#define IT83XX_ADC_VCMP1CSELM REG8(IT83XX_ADC_BASE + 0x78)
+#define IT83XX_ADC_VCMP2CSELM REG8(IT83XX_ADC_BASE + 0x79)
+#define IT83XX_ADC_VCMP3CSELM REG8(IT83XX_ADC_BASE + 0x7A)
+#define IT83XX_ADC_VCMP4CSELM REG8(IT83XX_ADC_BASE + 0x7B)
+#define IT83XX_ADC_VCMP5CSELM REG8(IT83XX_ADC_BASE + 0x7C)
 
 /* Digital to Analog Converter (DAC) */
-#define IT83XX_DAC_BASE   0x00F01A00
+#define IT83XX_DAC_BASE 0x00F01A00
 
-#define IT83XX_DAC_DACPDREG     REG8(IT83XX_DAC_BASE+0x01)
-#define IT83XX_DAC_POWDN(ch)    BIT(ch)
-#define IT83XX_DAC_DACDAT(ch)   REG8(IT83XX_DAC_BASE+0x02+ch)
+#define IT83XX_DAC_DACPDREG REG8(IT83XX_DAC_BASE + 0x01)
+#define IT83XX_DAC_POWDN(ch) BIT(ch)
+#define IT83XX_DAC_DACDAT(ch) REG8(IT83XX_DAC_BASE + 0x02 + ch)
 
 /* Keyboard Controller (KBC) */
-#define IT83XX_KBC_BASE   0x00F01300
+#define IT83XX_KBC_BASE 0x00F01300
 
-#define IT83XX_KBC_KBHICR       REG8(IT83XX_KBC_BASE+0x00)
-#define IT83XX_KBC_KBIRQR       REG8(IT83XX_KBC_BASE+0x02)
-#define IT83XX_KBC_KBHISR       REG8(IT83XX_KBC_BASE+0x04)
-#define IT83XX_KBC_KBHIKDOR     REG8(IT83XX_KBC_BASE+0x06)
-#define IT83XX_KBC_KBHIMDOR     REG8(IT83XX_KBC_BASE+0x08)
-#define IT83XX_KBC_KBHIDIR      REG8(IT83XX_KBC_BASE+0x0A)
+#define IT83XX_KBC_KBHICR REG8(IT83XX_KBC_BASE + 0x00)
+#define IT83XX_KBC_KBIRQR REG8(IT83XX_KBC_BASE + 0x02)
+#define IT83XX_KBC_KBHISR REG8(IT83XX_KBC_BASE + 0x04)
+#define IT83XX_KBC_KBHIKDOR REG8(IT83XX_KBC_BASE + 0x06)
+#define IT83XX_KBC_KBHIMDOR REG8(IT83XX_KBC_BASE + 0x08)
+#define IT83XX_KBC_KBHIDIR REG8(IT83XX_KBC_BASE + 0x0A)
 
 /* Power Management Channel (PMC) */
-#define IT83XX_PMC_BASE   0x00F01500
-
-#define IT83XX_PMC_PM1STS       REG8(IT83XX_PMC_BASE+0x00)
-#define IT83XX_PMC_PM1DO        REG8(IT83XX_PMC_BASE+0x01)
-#define IT83XX_PMC_PM1DOSCI     REG8(IT83XX_PMC_BASE+0x02)
-#define IT83XX_PMC_PM1DOSMI     REG8(IT83XX_PMC_BASE+0x03)
-#define IT83XX_PMC_PM1DI        REG8(IT83XX_PMC_BASE+0x04)
-#define IT83XX_PMC_PM1DISCI     REG8(IT83XX_PMC_BASE+0x05)
-#define IT83XX_PMC_PM1CTL       REG8(IT83XX_PMC_BASE+0x06)
-#define IT83XX_PMC_PM1IC        REG8(IT83XX_PMC_BASE+0x07)
-#define IT83XX_PMC_PM1IE        REG8(IT83XX_PMC_BASE+0x08)
-#define IT83XX_PMC_PM2STS       REG8(IT83XX_PMC_BASE+0x10)
-#define IT83XX_PMC_PM2DO        REG8(IT83XX_PMC_BASE+0x11)
-#define IT83XX_PMC_PM2DOSCI     REG8(IT83XX_PMC_BASE+0x12)
-#define IT83XX_PMC_PM2DOSMI     REG8(IT83XX_PMC_BASE+0x13)
-#define IT83XX_PMC_PM2DI        REG8(IT83XX_PMC_BASE+0x14)
-#define IT83XX_PMC_PM2DISCI     REG8(IT83XX_PMC_BASE+0x15)
-#define IT83XX_PMC_PM2CTL       REG8(IT83XX_PMC_BASE+0x16)
-#define IT83XX_PMC_PM2IC        REG8(IT83XX_PMC_BASE+0x17)
-#define IT83XX_PMC_PM2IE        REG8(IT83XX_PMC_BASE+0x18)
-#define IT83XX_PMC_PM3STS       REG8(IT83XX_PMC_BASE+0x20)
-#define IT83XX_PMC_PM3DO        REG8(IT83XX_PMC_BASE+0x21)
-#define IT83XX_PMC_PM3DI        REG8(IT83XX_PMC_BASE+0x22)
-#define IT83XX_PMC_PM3CTL       REG8(IT83XX_PMC_BASE+0x23)
-#define IT83XX_PMC_PM3IC        REG8(IT83XX_PMC_BASE+0x24)
-#define IT83XX_PMC_PM3IE        REG8(IT83XX_PMC_BASE+0x25)
-#define IT83XX_PMC_PM4STS       REG8(IT83XX_PMC_BASE+0x30)
-#define IT83XX_PMC_PM4DO        REG8(IT83XX_PMC_BASE+0x31)
-#define IT83XX_PMC_PM4DI        REG8(IT83XX_PMC_BASE+0x32)
-#define IT83XX_PMC_PM4CTL       REG8(IT83XX_PMC_BASE+0x33)
-#define IT83XX_PMC_PM4IC        REG8(IT83XX_PMC_BASE+0x34)
-#define IT83XX_PMC_PM4IE        REG8(IT83XX_PMC_BASE+0x35)
-#define IT83XX_PMC_PM5STS       REG8(IT83XX_PMC_BASE+0x40)
-#define IT83XX_PMC_PM5DO        REG8(IT83XX_PMC_BASE+0x41)
-#define IT83XX_PMC_PM5DI        REG8(IT83XX_PMC_BASE+0x42)
-#define IT83XX_PMC_PM5CTL       REG8(IT83XX_PMC_BASE+0x43)
-#define IT83XX_PMC_PM5IC        REG8(IT83XX_PMC_BASE+0x44)
-#define IT83XX_PMC_PM5IE        REG8(IT83XX_PMC_BASE+0x45)
-#define IT83XX_PMC_MBXCTRL      REG8(IT83XX_PMC_BASE+0x19)
-#define IT83XX_PMC_MBXEC_00     REG8(IT83XX_PMC_BASE+0xF0)
-#define IT83XX_PMC_MBXEC_01     REG8(IT83XX_PMC_BASE+0xF1)
-#define IT83XX_PMC_MBXEC_02     REG8(IT83XX_PMC_BASE+0xF2)
-#define IT83XX_PMC_MBXEC_03     REG8(IT83XX_PMC_BASE+0xF3)
-#define IT83XX_PMC_MBXEC_04     REG8(IT83XX_PMC_BASE+0xF4)
-#define IT83XX_PMC_MBXEC_05     REG8(IT83XX_PMC_BASE+0xF5)
-#define IT83XX_PMC_MBXEC_06     REG8(IT83XX_PMC_BASE+0xF6)
-#define IT83XX_PMC_MBXEC_07     REG8(IT83XX_PMC_BASE+0xF7)
-#define IT83XX_PMC_MBXEC_08     REG8(IT83XX_PMC_BASE+0xF8)
-#define IT83XX_PMC_MBXEC_09     REG8(IT83XX_PMC_BASE+0xF9)
-#define IT83XX_PMC_MBXEC_10     REG8(IT83XX_PMC_BASE+0xFA)
-#define IT83XX_PMC_MBXEC_11     REG8(IT83XX_PMC_BASE+0xFB)
-#define IT83XX_PMC_MBXEC_12     REG8(IT83XX_PMC_BASE+0xFC)
-#define IT83XX_PMC_MBXEC_13     REG8(IT83XX_PMC_BASE+0xFD)
-#define IT83XX_PMC_MBXEC_14     REG8(IT83XX_PMC_BASE+0xFE)
-#define IT83XX_PMC_MBXEC_15     REG8(IT83XX_PMC_BASE+0xFF)
-#define IT83XX_PMC_PMSTS(ch)    REG8(IT83XX_PMC_BASE + 0x00 + (ch << 4))
-#define IT83XX_PMC_PMDO(ch)     REG8(IT83XX_PMC_BASE + 0x01 + (ch << 4))
-#define IT83XX_PMC_PMDI(ch)     \
-REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 2 : 4) + (ch << 4))
-#define IT83XX_PMC_PMCTL(ch)     \
-REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 3 : 6) + (ch << 4))
-#define IT83XX_PMC_PMIE(ch)     \
-REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 5 : 8) + (ch << 4))
+#define IT83XX_PMC_BASE 0x00F01500
+
+#define IT83XX_PMC_PM1STS REG8(IT83XX_PMC_BASE + 0x00)
+#define IT83XX_PMC_PM1DO REG8(IT83XX_PMC_BASE + 0x01)
+#define IT83XX_PMC_PM1DOSCI REG8(IT83XX_PMC_BASE + 0x02)
+#define IT83XX_PMC_PM1DOSMI REG8(IT83XX_PMC_BASE + 0x03)
+#define IT83XX_PMC_PM1DI REG8(IT83XX_PMC_BASE + 0x04)
+#define IT83XX_PMC_PM1DISCI REG8(IT83XX_PMC_BASE + 0x05)
+#define IT83XX_PMC_PM1CTL REG8(IT83XX_PMC_BASE + 0x06)
+#define IT83XX_PMC_PM1IC REG8(IT83XX_PMC_BASE + 0x07)
+#define IT83XX_PMC_PM1IE REG8(IT83XX_PMC_BASE + 0x08)
+#define IT83XX_PMC_PM2STS REG8(IT83XX_PMC_BASE + 0x10)
+#define IT83XX_PMC_PM2DO REG8(IT83XX_PMC_BASE + 0x11)
+#define IT83XX_PMC_PM2DOSCI REG8(IT83XX_PMC_BASE + 0x12)
+#define IT83XX_PMC_PM2DOSMI REG8(IT83XX_PMC_BASE + 0x13)
+#define IT83XX_PMC_PM2DI REG8(IT83XX_PMC_BASE + 0x14)
+#define IT83XX_PMC_PM2DISCI REG8(IT83XX_PMC_BASE + 0x15)
+#define IT83XX_PMC_PM2CTL REG8(IT83XX_PMC_BASE + 0x16)
+#define IT83XX_PMC_PM2IC REG8(IT83XX_PMC_BASE + 0x17)
+#define IT83XX_PMC_PM2IE REG8(IT83XX_PMC_BASE + 0x18)
+#define IT83XX_PMC_PM3STS REG8(IT83XX_PMC_BASE + 0x20)
+#define IT83XX_PMC_PM3DO REG8(IT83XX_PMC_BASE + 0x21)
+#define IT83XX_PMC_PM3DI REG8(IT83XX_PMC_BASE + 0x22)
+#define IT83XX_PMC_PM3CTL REG8(IT83XX_PMC_BASE + 0x23)
+#define IT83XX_PMC_PM3IC REG8(IT83XX_PMC_BASE + 0x24)
+#define IT83XX_PMC_PM3IE REG8(IT83XX_PMC_BASE + 0x25)
+#define IT83XX_PMC_PM4STS REG8(IT83XX_PMC_BASE + 0x30)
+#define IT83XX_PMC_PM4DO REG8(IT83XX_PMC_BASE + 0x31)
+#define IT83XX_PMC_PM4DI REG8(IT83XX_PMC_BASE + 0x32)
+#define IT83XX_PMC_PM4CTL REG8(IT83XX_PMC_BASE + 0x33)
+#define IT83XX_PMC_PM4IC REG8(IT83XX_PMC_BASE + 0x34)
+#define IT83XX_PMC_PM4IE REG8(IT83XX_PMC_BASE + 0x35)
+#define IT83XX_PMC_PM5STS REG8(IT83XX_PMC_BASE + 0x40)
+#define IT83XX_PMC_PM5DO REG8(IT83XX_PMC_BASE + 0x41)
+#define IT83XX_PMC_PM5DI REG8(IT83XX_PMC_BASE + 0x42)
+#define IT83XX_PMC_PM5CTL REG8(IT83XX_PMC_BASE + 0x43)
+#define IT83XX_PMC_PM5IC REG8(IT83XX_PMC_BASE + 0x44)
+#define IT83XX_PMC_PM5IE REG8(IT83XX_PMC_BASE + 0x45)
+#define IT83XX_PMC_MBXCTRL REG8(IT83XX_PMC_BASE + 0x19)
+#define IT83XX_PMC_MBXEC_00 REG8(IT83XX_PMC_BASE + 0xF0)
+#define IT83XX_PMC_MBXEC_01 REG8(IT83XX_PMC_BASE + 0xF1)
+#define IT83XX_PMC_MBXEC_02 REG8(IT83XX_PMC_BASE + 0xF2)
+#define IT83XX_PMC_MBXEC_03 REG8(IT83XX_PMC_BASE + 0xF3)
+#define IT83XX_PMC_MBXEC_04 REG8(IT83XX_PMC_BASE + 0xF4)
+#define IT83XX_PMC_MBXEC_05 REG8(IT83XX_PMC_BASE + 0xF5)
+#define IT83XX_PMC_MBXEC_06 REG8(IT83XX_PMC_BASE + 0xF6)
+#define IT83XX_PMC_MBXEC_07 REG8(IT83XX_PMC_BASE + 0xF7)
+#define IT83XX_PMC_MBXEC_08 REG8(IT83XX_PMC_BASE + 0xF8)
+#define IT83XX_PMC_MBXEC_09 REG8(IT83XX_PMC_BASE + 0xF9)
+#define IT83XX_PMC_MBXEC_10 REG8(IT83XX_PMC_BASE + 0xFA)
+#define IT83XX_PMC_MBXEC_11 REG8(IT83XX_PMC_BASE + 0xFB)
+#define IT83XX_PMC_MBXEC_12 REG8(IT83XX_PMC_BASE + 0xFC)
+#define IT83XX_PMC_MBXEC_13 REG8(IT83XX_PMC_BASE + 0xFD)
+#define IT83XX_PMC_MBXEC_14 REG8(IT83XX_PMC_BASE + 0xFE)
+#define IT83XX_PMC_MBXEC_15 REG8(IT83XX_PMC_BASE + 0xFF)
+#define IT83XX_PMC_PMSTS(ch) REG8(IT83XX_PMC_BASE + 0x00 + (ch << 4))
+#define IT83XX_PMC_PMDO(ch) REG8(IT83XX_PMC_BASE + 0x01 + (ch << 4))
+#define IT83XX_PMC_PMDI(ch) \
+	REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 2 : 4) + (ch << 4))
+#define IT83XX_PMC_PMCTL(ch) \
+	REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 3 : 6) + (ch << 4))
+#define IT83XX_PMC_PMIE(ch) \
+	REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 5 : 8) + (ch << 4))
 
 /* Keyboard Matrix Scan control (KBS) */
-#define IT83XX_KBS_BASE   0x00F01D00
-
-#define IT83XX_KBS_KSOL         REG8(IT83XX_KBS_BASE+0x00)
-#define IT83XX_KBS_KSOH1        REG8(IT83XX_KBS_BASE+0x01)
-#define IT83XX_KBS_KSOCTRL      REG8(IT83XX_KBS_BASE+0x02)
-#define IT83XX_KBS_KSOH2        REG8(IT83XX_KBS_BASE+0x03)
-#define IT83XX_KBS_KSI          REG8(IT83XX_KBS_BASE+0x04)
-#define IT83XX_KBS_KSICTRL      REG8(IT83XX_KBS_BASE+0x05)
-#define IT83XX_KBS_KSIGCTRL     REG8(IT83XX_KBS_BASE+0x06)
-#define IT83XX_KBS_KSIGOEN      REG8(IT83XX_KBS_BASE+0x07)
-#define IT83XX_KBS_KSIGDAT      REG8(IT83XX_KBS_BASE+0x08)
-#define IT83XX_KBS_KSIGDMRR     REG8(IT83XX_KBS_BASE+0x09)
-#define IT83XX_KBS_KSOHGCTRL    REG8(IT83XX_KBS_BASE+0x0A)
-#define IT83XX_KBS_KSOHGOEN     REG8(IT83XX_KBS_BASE+0x0B)
-#define IT83XX_KBS_KSOHGDMRR    REG8(IT83XX_KBS_BASE+0x0C)
-#define IT83XX_KBS_KSOLGCTRL    REG8(IT83XX_KBS_BASE+0x0D)
-#define IT83XX_KBS_KSOLGOEN     REG8(IT83XX_KBS_BASE+0x0E)
-#define IT83XX_KBS_KSOLGDMRR    REG8(IT83XX_KBS_BASE+0x0F)
-#define IT83XX_KBS_KSO0LSDR     REG8(IT83XX_KBS_BASE+0x10)
-#define IT83XX_KBS_KSO1LSDR     REG8(IT83XX_KBS_BASE+0x11)
-#define IT83XX_KBS_KSO2LSDR     REG8(IT83XX_KBS_BASE+0x12)
-#define IT83XX_KBS_KSO3LSDR     REG8(IT83XX_KBS_BASE+0x13)
-#define IT83XX_KBS_KSO4LSDR     REG8(IT83XX_KBS_BASE+0x14)
-#define IT83XX_KBS_KSO5LSDR     REG8(IT83XX_KBS_BASE+0x15)
-#define IT83XX_KBS_KSO6LSDR     REG8(IT83XX_KBS_BASE+0x16)
-#define IT83XX_KBS_KSO7LSDR     REG8(IT83XX_KBS_BASE+0x17)
-#define IT83XX_KBS_KSO8LSDR     REG8(IT83XX_KBS_BASE+0x18)
-#define IT83XX_KBS_KSO9LSDR     REG8(IT83XX_KBS_BASE+0x19)
-#define IT83XX_KBS_KSO10LSDR    REG8(IT83XX_KBS_BASE+0x1A)
-#define IT83XX_KBS_KSO11LSDR    REG8(IT83XX_KBS_BASE+0x1B)
-#define IT83XX_KBS_KSO12LSDR    REG8(IT83XX_KBS_BASE+0x1C)
-#define IT83XX_KBS_KSO13LSDR    REG8(IT83XX_KBS_BASE+0x1D)
-#define IT83XX_KBS_KSO14LSDR    REG8(IT83XX_KBS_BASE+0x1E)
-#define IT83XX_KBS_KSO15LSDR    REG8(IT83XX_KBS_BASE+0x1F)
-#define IT83XX_KBS_KSO16LSDR    REG8(IT83XX_KBS_BASE+0x20)
-#define IT83XX_KBS_KSO17LSDR    REG8(IT83XX_KBS_BASE+0x21)
-#define IT83XX_KBS_SDC1R        REG8(IT83XX_KBS_BASE+0x22)
-#define IT83XX_KBS_SDC2R        REG8(IT83XX_KBS_BASE+0x23)
-#define IT83XX_KBS_SDC3R        REG8(IT83XX_KBS_BASE+0x24)
-#define IT83XX_KBS_SDSR         REG8(IT83XX_KBS_BASE+0x25)
-#define IT83XX_KBS_KSIGPODR     REG8(IT83XX_KBS_BASE+0x26)
-#define IT83XX_KBS_KSOHGPODR    REG8(IT83XX_KBS_BASE+0x27)
-#define IT83XX_KBS_KSOLGPODR    REG8(IT83XX_KBS_BASE+0x28)
+#define IT83XX_KBS_BASE 0x00F01D00
+
+#define IT83XX_KBS_KSOL REG8(IT83XX_KBS_BASE + 0x00)
+#define IT83XX_KBS_KSOH1 REG8(IT83XX_KBS_BASE + 0x01)
+#define IT83XX_KBS_KSOCTRL REG8(IT83XX_KBS_BASE + 0x02)
+#define IT83XX_KBS_KSOH2 REG8(IT83XX_KBS_BASE + 0x03)
+#define IT83XX_KBS_KSI REG8(IT83XX_KBS_BASE + 0x04)
+#define IT83XX_KBS_KSICTRL REG8(IT83XX_KBS_BASE + 0x05)
+#define IT83XX_KBS_KSIGCTRL REG8(IT83XX_KBS_BASE + 0x06)
+#define IT83XX_KBS_KSIGOEN REG8(IT83XX_KBS_BASE + 0x07)
+#define IT83XX_KBS_KSIGDAT REG8(IT83XX_KBS_BASE + 0x08)
+#define IT83XX_KBS_KSIGDMRR REG8(IT83XX_KBS_BASE + 0x09)
+#define IT83XX_KBS_KSOHGCTRL REG8(IT83XX_KBS_BASE + 0x0A)
+#define IT83XX_KBS_KSOHGOEN REG8(IT83XX_KBS_BASE + 0x0B)
+#define IT83XX_KBS_KSOHGDMRR REG8(IT83XX_KBS_BASE + 0x0C)
+#define IT83XX_KBS_KSOLGCTRL REG8(IT83XX_KBS_BASE + 0x0D)
+#define IT83XX_KBS_KSOLGOEN REG8(IT83XX_KBS_BASE + 0x0E)
+#define IT83XX_KBS_KSOLGDMRR REG8(IT83XX_KBS_BASE + 0x0F)
+#define IT83XX_KBS_KSO0LSDR REG8(IT83XX_KBS_BASE + 0x10)
+#define IT83XX_KBS_KSO1LSDR REG8(IT83XX_KBS_BASE + 0x11)
+#define IT83XX_KBS_KSO2LSDR REG8(IT83XX_KBS_BASE + 0x12)
+#define IT83XX_KBS_KSO3LSDR REG8(IT83XX_KBS_BASE + 0x13)
+#define IT83XX_KBS_KSO4LSDR REG8(IT83XX_KBS_BASE + 0x14)
+#define IT83XX_KBS_KSO5LSDR REG8(IT83XX_KBS_BASE + 0x15)
+#define IT83XX_KBS_KSO6LSDR REG8(IT83XX_KBS_BASE + 0x16)
+#define IT83XX_KBS_KSO7LSDR REG8(IT83XX_KBS_BASE + 0x17)
+#define IT83XX_KBS_KSO8LSDR REG8(IT83XX_KBS_BASE + 0x18)
+#define IT83XX_KBS_KSO9LSDR REG8(IT83XX_KBS_BASE + 0x19)
+#define IT83XX_KBS_KSO10LSDR REG8(IT83XX_KBS_BASE + 0x1A)
+#define IT83XX_KBS_KSO11LSDR REG8(IT83XX_KBS_BASE + 0x1B)
+#define IT83XX_KBS_KSO12LSDR REG8(IT83XX_KBS_BASE + 0x1C)
+#define IT83XX_KBS_KSO13LSDR REG8(IT83XX_KBS_BASE + 0x1D)
+#define IT83XX_KBS_KSO14LSDR REG8(IT83XX_KBS_BASE + 0x1E)
+#define IT83XX_KBS_KSO15LSDR REG8(IT83XX_KBS_BASE + 0x1F)
+#define IT83XX_KBS_KSO16LSDR REG8(IT83XX_KBS_BASE + 0x20)
+#define IT83XX_KBS_KSO17LSDR REG8(IT83XX_KBS_BASE + 0x21)
+#define IT83XX_KBS_SDC1R REG8(IT83XX_KBS_BASE + 0x22)
+#define IT83XX_KBS_SDC2R REG8(IT83XX_KBS_BASE + 0x23)
+#define IT83XX_KBS_SDC3R REG8(IT83XX_KBS_BASE + 0x24)
+#define IT83XX_KBS_SDSR REG8(IT83XX_KBS_BASE + 0x25)
+#define IT83XX_KBS_KSIGPODR REG8(IT83XX_KBS_BASE + 0x26)
+#define IT83XX_KBS_KSOHGPODR REG8(IT83XX_KBS_BASE + 0x27)
+#define IT83XX_KBS_KSOLGPODR REG8(IT83XX_KBS_BASE + 0x28)
 
 /* Shared Memory Flash Interface Bridge (SMFI) */
-#define IT83XX_SMFI_BASE  0x00F01000
-
-#define IT83XX_SMFI_SMECCS      REG8(IT83XX_SMFI_BASE+0x20)
-#define IT83XX_SMFI_MASK_HOSTWA 	BIT(5)
-#define IT83XX_SMFI_HRAMWC      REG8(IT83XX_SMFI_BASE+0x5A)
-#define IT83XX_SMFI_HRAMW0BA    REG8(IT83XX_SMFI_BASE+0x5B)
-#define IT83XX_SMFI_HRAMW1BA    REG8(IT83XX_SMFI_BASE+0x5C)
-#define IT83XX_SMFI_HRAMW0AAS   REG8(IT83XX_SMFI_BASE+0x5D)
-#define IT83XX_SMFI_HRAMW1AAS   REG8(IT83XX_SMFI_BASE+0x5E)
-#define IT83XX_SMFI_HRAMW2BA    REG8(IT83XX_SMFI_BASE+0x76)
-#define IT83XX_SMFI_HRAMW3BA    REG8(IT83XX_SMFI_BASE+0x77)
-#define IT83XX_SMFI_HRAMW2AAS   REG8(IT83XX_SMFI_BASE+0x78)
-#define IT83XX_SMFI_HRAMW3AAS   REG8(IT83XX_SMFI_BASE+0x79)
-#define IT83XX_SMFI_H2RAMECSIE  REG8(IT83XX_SMFI_BASE+0x7A)
-#define IT83XX_SMFI_H2RAMECSA   REG8(IT83XX_SMFI_BASE+0x7B)
-#define IT83XX_SMFI_H2RAMHSS    REG8(IT83XX_SMFI_BASE+0x7C)
-#define IT83XX_SMFI_ECINDAR0    REG8(IT83XX_SMFI_BASE+0x3B)
-#define IT83XX_SMFI_ECINDAR1    REG8(IT83XX_SMFI_BASE+0x3C)
-#define IT83XX_SMFI_ECINDAR2    REG8(IT83XX_SMFI_BASE+0x3D)
-#define IT83XX_SMFI_ECINDAR3    REG8(IT83XX_SMFI_BASE+0x3E)
+#define IT83XX_SMFI_BASE 0x00F01000
+
+#define IT83XX_SMFI_SMECCS REG8(IT83XX_SMFI_BASE + 0x20)
+#define IT83XX_SMFI_MASK_HOSTWA BIT(5)
+#define IT83XX_SMFI_HRAMWC REG8(IT83XX_SMFI_BASE + 0x5A)
+#define IT83XX_SMFI_HRAMW0BA REG8(IT83XX_SMFI_BASE + 0x5B)
+#define IT83XX_SMFI_HRAMW1BA REG8(IT83XX_SMFI_BASE + 0x5C)
+#define IT83XX_SMFI_HRAMW0AAS REG8(IT83XX_SMFI_BASE + 0x5D)
+#define IT83XX_SMFI_HRAMW1AAS REG8(IT83XX_SMFI_BASE + 0x5E)
+#define IT83XX_SMFI_HRAMW2BA REG8(IT83XX_SMFI_BASE + 0x76)
+#define IT83XX_SMFI_HRAMW3BA REG8(IT83XX_SMFI_BASE + 0x77)
+#define IT83XX_SMFI_HRAMW2AAS REG8(IT83XX_SMFI_BASE + 0x78)
+#define IT83XX_SMFI_HRAMW3AAS REG8(IT83XX_SMFI_BASE + 0x79)
+#define IT83XX_SMFI_H2RAMECSIE REG8(IT83XX_SMFI_BASE + 0x7A)
+#define IT83XX_SMFI_H2RAMECSA REG8(IT83XX_SMFI_BASE + 0x7B)
+#define IT83XX_SMFI_H2RAMHSS REG8(IT83XX_SMFI_BASE + 0x7C)
+#define IT83XX_SMFI_ECINDAR0 REG8(IT83XX_SMFI_BASE + 0x3B)
+#define IT83XX_SMFI_ECINDAR1 REG8(IT83XX_SMFI_BASE + 0x3C)
+#define IT83XX_SMFI_ECINDAR2 REG8(IT83XX_SMFI_BASE + 0x3D)
+#define IT83XX_SMFI_ECINDAR3 REG8(IT83XX_SMFI_BASE + 0x3E)
 #define EC_INDIRECT_READ_INTERNAL_FLASH BIT(6)
-#define IT83XX_SMFI_ECINDDR     REG8(IT83XX_SMFI_BASE+0x3F)
-#define IT83XX_SMFI_SCAR0L      REG8(IT83XX_SMFI_BASE+0x40)
-#define IT83XX_SMFI_SCAR0M      REG8(IT83XX_SMFI_BASE+0x41)
-#define IT83XX_SMFI_SCAR0H      REG8(IT83XX_SMFI_BASE+0x42)
-#define IT83XX_SMFI_SCAR2L      REG8(IT83XX_SMFI_BASE+0x46)
-#define IT83XX_SMFI_SCAR2M      REG8(IT83XX_SMFI_BASE+0x47)
-#define IT83XX_SMFI_SCAR2H      REG8(IT83XX_SMFI_BASE+0x48)
-#define IT83XX_SMFI_FLHCTRL3R   REG8(IT83XX_SMFI_BASE+0x63)
-#define IT83XX_SMFI_STCDMACR    REG8(IT83XX_SMFI_BASE+0x80)
-#define IT83XX_SMFI_FLHCTRL6R   REG8(IT83XX_SMFI_BASE+0xA2)
+#define IT83XX_SMFI_ECINDDR REG8(IT83XX_SMFI_BASE + 0x3F)
+#define IT83XX_SMFI_SCAR0L REG8(IT83XX_SMFI_BASE + 0x40)
+#define IT83XX_SMFI_SCAR0M REG8(IT83XX_SMFI_BASE + 0x41)
+#define IT83XX_SMFI_SCAR0H REG8(IT83XX_SMFI_BASE + 0x42)
+#define IT83XX_SMFI_SCAR2L REG8(IT83XX_SMFI_BASE + 0x46)
+#define IT83XX_SMFI_SCAR2M REG8(IT83XX_SMFI_BASE + 0x47)
+#define IT83XX_SMFI_SCAR2H REG8(IT83XX_SMFI_BASE + 0x48)
+#define IT83XX_SMFI_FLHCTRL3R REG8(IT83XX_SMFI_BASE + 0x63)
+#define IT83XX_SMFI_STCDMACR REG8(IT83XX_SMFI_BASE + 0x80)
+#define IT83XX_SMFI_FLHCTRL6R REG8(IT83XX_SMFI_BASE + 0xA2)
 /* Enable EC-indirect page program command */
 #define IT83XX_SMFI_MASK_ECINDPP BIT(3)
 
 /* Serial Peripheral Interface (SSPI) */
-#define IT83XX_SSPI_BASE  0x00F02600
+#define IT83XX_SSPI_BASE 0x00F02600
 
-#define IT83XX_SSPI_SPIDATA     REG8(IT83XX_SSPI_BASE+0x00)
-#define IT83XX_SSPI_SPICTRL1    REG8(IT83XX_SSPI_BASE+0x01)
-#define IT83XX_SSPI_SPICTRL2    REG8(IT83XX_SSPI_BASE+0x02)
-#define IT83XX_SSPI_SPISTS      REG8(IT83XX_SSPI_BASE+0x03)
-#define IT83XX_SSPI_SPICTRL3    REG8(IT83XX_SSPI_BASE+0x04)
+#define IT83XX_SSPI_SPIDATA REG8(IT83XX_SSPI_BASE + 0x00)
+#define IT83XX_SSPI_SPICTRL1 REG8(IT83XX_SSPI_BASE + 0x01)
+#define IT83XX_SSPI_SPICTRL2 REG8(IT83XX_SSPI_BASE + 0x02)
+#define IT83XX_SSPI_SPISTS REG8(IT83XX_SSPI_BASE + 0x03)
+#define IT83XX_SSPI_SPICTRL3 REG8(IT83XX_SSPI_BASE + 0x04)
 
 /* Serial Peripheral Interface (SPI) */
-#define IT83XX_SPI_BASE  0x00F03A00
-
-#define IT83XX_SPI_SPISGCR      REG8(IT83XX_SPI_BASE+0x00)
-#define IT83XX_SPI_SPISCEN         BIT(0)
-#define IT83XX_SPI_TXRXFAR      REG8(IT83XX_SPI_BASE+0x01)
-#define IT83XX_SPI_CPURXF2A        BIT(4)
-#define IT83XX_SPI_CPURXF1A        BIT(3)
-#define IT83XX_SPI_CPUTFA          BIT(1)
-#define IT83XX_SPI_TXFCR        REG8(IT83XX_SPI_BASE+0x02)
-#define IT83XX_SPI_TXFCMR          BIT(2)
-#define IT83XX_SPI_TXFR            BIT(1)
-#define IT83XX_SPI_TXFS            BIT(0)
-#define IT83XX_SPI_GCR2         REG8(IT83XX_SPI_BASE+0x03)
-#define IT83XX_SPI_RXF2OC          BIT(4)
-#define IT83XX_SPI_RXF1OC          BIT(3)
-#define IT83XX_SPI_RXFAR           BIT(0)
-#define IT83XX_SPI_IMR          REG8(IT83XX_SPI_BASE+0x04)
-#define IT83XX_SPI_RX_FIFO_FULL    BIT(7)
-#define IT83XX_SPI_RX_REACH        BIT(5)
-#define IT83XX_SPI_EDIM            BIT(2)
-#define IT83XX_SPI_ISR          REG8(IT83XX_SPI_BASE+0x05)
-#define IT83XX_SPI_TXFSR        REG8(IT83XX_SPI_BASE+0x06)
-#define IT83XX_SPI_ENDDETECTINT    BIT(2)
-#define IT83XX_SPI_RXFSR        REG8(IT83XX_SPI_BASE+0x07)
-#define IT83XX_SPI_RXFFSM          (BIT(4) | BIT(3))
-#define IT83XX_SPI_RXF2FS          BIT(2)
-#define IT83XX_SPI_RXF1FS          BIT(1)
+#define IT83XX_SPI_BASE 0x00F03A00
+
+#define IT83XX_SPI_SPISGCR REG8(IT83XX_SPI_BASE + 0x00)
+#define IT83XX_SPI_SPISCEN BIT(0)
+#define IT83XX_SPI_TXRXFAR REG8(IT83XX_SPI_BASE + 0x01)
+#define IT83XX_SPI_CPURXF2A BIT(4)
+#define IT83XX_SPI_CPURXF1A BIT(3)
+#define IT83XX_SPI_CPUTFA BIT(1)
+#define IT83XX_SPI_TXFCR REG8(IT83XX_SPI_BASE + 0x02)
+#define IT83XX_SPI_TXFCMR BIT(2)
+#define IT83XX_SPI_TXFR BIT(1)
+#define IT83XX_SPI_TXFS BIT(0)
+#define IT83XX_SPI_GCR2 REG8(IT83XX_SPI_BASE + 0x03)
+#define IT83XX_SPI_RXF2OC BIT(4)
+#define IT83XX_SPI_RXF1OC BIT(3)
+#define IT83XX_SPI_RXFAR BIT(0)
+#define IT83XX_SPI_IMR REG8(IT83XX_SPI_BASE + 0x04)
+#define IT83XX_SPI_RX_FIFO_FULL BIT(7)
+#define IT83XX_SPI_RX_REACH BIT(5)
+#define IT83XX_SPI_EDIM BIT(2)
+#define IT83XX_SPI_ISR REG8(IT83XX_SPI_BASE + 0x05)
+#define IT83XX_SPI_TXFSR REG8(IT83XX_SPI_BASE + 0x06)
+#define IT83XX_SPI_ENDDETECTINT BIT(2)
+#define IT83XX_SPI_RXFSR REG8(IT83XX_SPI_BASE + 0x07)
+#define IT83XX_SPI_RXFFSM (BIT(4) | BIT(3))
+#define IT83XX_SPI_RXF2FS BIT(2)
+#define IT83XX_SPI_RXF1FS BIT(1)
 #ifdef CHIP_VARIANT_IT83202BX
-#define IT83XX_SPI_SPISRDR      REG8(IT83XX_SPI_BASE+0x08)
+#define IT83XX_SPI_SPISRDR REG8(IT83XX_SPI_BASE + 0x08)
 #else
-#define IT83XX_SPI_SPISRDR      REG8(IT83XX_SPI_BASE+0x0b)
+#define IT83XX_SPI_SPISRDR REG8(IT83XX_SPI_BASE + 0x0b)
 #endif
-#define IT83XX_SPI_CPUWTFDB0    REG32(IT83XX_SPI_BASE+0x08)
-#define IT83XX_SPI_FCR          REG8(IT83XX_SPI_BASE+0x09)
-#define IT83XX_SPI_SPISRTXF        BIT(2)
-#define IT83XX_SPI_RXFR            BIT(1)
-#define IT83XX_SPI_RXFCMR          BIT(0)
-#define IT83XX_SPI_RXFRDRB0     REG32(IT83XX_SPI_BASE+0x0C)
-#define IT83XX_SPI_FTCB0R       REG8(IT83XX_SPI_BASE+0x18)
-#define IT83XX_SPI_FTCB1R       REG8(IT83XX_SPI_BASE+0x19)
-#define IT83XX_SPI_TCCB0        REG8(IT83XX_SPI_BASE+0x1A)
-#define IT83XX_SPI_TCCB1        REG8(IT83XX_SPI_BASE+0x1B)
-#define IT83XX_SPI_HPR2         REG8(IT83XX_SPI_BASE+0x1E)
-#define IT83XX_SPI_EMMCBMR      REG8(IT83XX_SPI_BASE+0x21)
-#define IT83XX_SPI_EMMCABM         BIT(1) /* eMMC Alternative Boot Mode */
-#define IT83XX_SPI_RX_VLISMR    REG8(IT83XX_SPI_BASE+0x26)
-#define IT83XX_SPI_RVLIM           BIT(0)
-#define IT83XX_SPI_RX_VLISR     REG8(IT83XX_SPI_BASE+0x27)
-#define IT83XX_SPI_RVLI            BIT(0)
+#define IT83XX_SPI_CPUWTFDB0 REG32(IT83XX_SPI_BASE + 0x08)
+#define IT83XX_SPI_FCR REG8(IT83XX_SPI_BASE + 0x09)
+#define IT83XX_SPI_SPISRTXF BIT(2)
+#define IT83XX_SPI_RXFR BIT(1)
+#define IT83XX_SPI_RXFCMR BIT(0)
+#define IT83XX_SPI_RXFRDRB0 REG32(IT83XX_SPI_BASE + 0x0C)
+#define IT83XX_SPI_FTCB0R REG8(IT83XX_SPI_BASE + 0x18)
+#define IT83XX_SPI_FTCB1R REG8(IT83XX_SPI_BASE + 0x19)
+#define IT83XX_SPI_TCCB0 REG8(IT83XX_SPI_BASE + 0x1A)
+#define IT83XX_SPI_TCCB1 REG8(IT83XX_SPI_BASE + 0x1B)
+#define IT83XX_SPI_HPR2 REG8(IT83XX_SPI_BASE + 0x1E)
+#define IT83XX_SPI_EMMCBMR REG8(IT83XX_SPI_BASE + 0x21)
+#define IT83XX_SPI_EMMCABM BIT(1) /* eMMC Alternative Boot Mode */
+#define IT83XX_SPI_RX_VLISMR REG8(IT83XX_SPI_BASE + 0x26)
+#define IT83XX_SPI_RVLIM BIT(0)
+#define IT83XX_SPI_RX_VLISR REG8(IT83XX_SPI_BASE + 0x27)
+#define IT83XX_SPI_RVLI BIT(0)
 
 /* Platform Environment Control Interface (PECI) */
-#define IT83XX_PECI_BASE  0x00F02C00
-
-#define IT83XX_PECI_HOSTAR      REG8(IT83XX_PECI_BASE+0x00)
-#define IT83XX_PECI_HOCTLR      REG8(IT83XX_PECI_BASE+0x01)
-#define IT83XX_PECI_HOCMDR      REG8(IT83XX_PECI_BASE+0x02)
-#define IT83XX_PECI_HOTRADDR    REG8(IT83XX_PECI_BASE+0x03)
-#define IT83XX_PECI_HOWRLR      REG8(IT83XX_PECI_BASE+0x04)
-#define IT83XX_PECI_HORDLR      REG8(IT83XX_PECI_BASE+0x05)
-#define IT83XX_PECI_HOWRDR      REG8(IT83XX_PECI_BASE+0x06)
-#define IT83XX_PECI_HORDDR      REG8(IT83XX_PECI_BASE+0x07)
-#define IT83XX_PECI_HOCTL2R     REG8(IT83XX_PECI_BASE+0x08)
-#define IT83XX_PECI_RWFCSV      REG8(IT83XX_PECI_BASE+0x09)
-#define IT83XX_PECI_RRFCSV      REG8(IT83XX_PECI_BASE+0x0A)
-#define IT83XX_PECI_WFCSV       REG8(IT83XX_PECI_BASE+0x0B)
-#define IT83XX_PECI_RFCSV       REG8(IT83XX_PECI_BASE+0x0C)
-#define IT83XX_PECI_AWFCSV      REG8(IT83XX_PECI_BASE+0x0D)
-#define IT83XX_PECI_PADCTLR     REG8(IT83XX_PECI_BASE+0x0E)
+#define IT83XX_PECI_BASE 0x00F02C00
+
+#define IT83XX_PECI_HOSTAR REG8(IT83XX_PECI_BASE + 0x00)
+#define IT83XX_PECI_HOCTLR REG8(IT83XX_PECI_BASE + 0x01)
+#define IT83XX_PECI_HOCMDR REG8(IT83XX_PECI_BASE + 0x02)
+#define IT83XX_PECI_HOTRADDR REG8(IT83XX_PECI_BASE + 0x03)
+#define IT83XX_PECI_HOWRLR REG8(IT83XX_PECI_BASE + 0x04)
+#define IT83XX_PECI_HORDLR REG8(IT83XX_PECI_BASE + 0x05)
+#define IT83XX_PECI_HOWRDR REG8(IT83XX_PECI_BASE + 0x06)
+#define IT83XX_PECI_HORDDR REG8(IT83XX_PECI_BASE + 0x07)
+#define IT83XX_PECI_HOCTL2R REG8(IT83XX_PECI_BASE + 0x08)
+#define IT83XX_PECI_RWFCSV REG8(IT83XX_PECI_BASE + 0x09)
+#define IT83XX_PECI_RRFCSV REG8(IT83XX_PECI_BASE + 0x0A)
+#define IT83XX_PECI_WFCSV REG8(IT83XX_PECI_BASE + 0x0B)
+#define IT83XX_PECI_RFCSV REG8(IT83XX_PECI_BASE + 0x0C)
+#define IT83XX_PECI_AWFCSV REG8(IT83XX_PECI_BASE + 0x0D)
+#define IT83XX_PECI_PADCTLR REG8(IT83XX_PECI_BASE + 0x0E)
 
 /*
  * The count number of the counter for 25 ms register.
  * The 25 ms register is calculated by (count number *1.024 kHz).
  */
-#define I2C_CLK_LOW_TIMEOUT  255 /* ~=249 ms */
+#define I2C_CLK_LOW_TIMEOUT 255 /* ~=249 ms */
 
 /* SMBus/I2C Interface (SMB/I2C) */
-#define IT83XX_SMB_BASE   0x00F01C00
-
-#define IT83XX_SMB_4P7USL       REG8(IT83XX_SMB_BASE+0x00)
-#define IT83XX_SMB_4P0USL       REG8(IT83XX_SMB_BASE+0x01)
-#define IT83XX_SMB_300NS        REG8(IT83XX_SMB_BASE+0x02)
-#define IT83XX_SMB_250NS        REG8(IT83XX_SMB_BASE+0x03)
-#define IT83XX_SMB_25MS         REG8(IT83XX_SMB_BASE+0x04)
-#define IT83XX_SMB_45P3USL      REG8(IT83XX_SMB_BASE+0x05)
-#define IT83XX_SMB_45P3USH      REG8(IT83XX_SMB_BASE+0x06)
-#define IT83XX_SMB_4P7A4P0H     REG8(IT83XX_SMB_BASE+0x07)
-#define IT83XX_SMB_SLVISELR     REG8(IT83XX_SMB_BASE+0x08)
-#define IT83XX_SMB_SCLKTS(ch)   REG8(IT83XX_SMB_BASE+0x09+ch)
-#define IT83XX_SMB_CHSEF        REG8(IT83XX_SMB_BASE+0x11)
-#define IT83XX_SMB_CHSAB        REG8(IT83XX_SMB_BASE+0x20)
-#define IT83XX_SMB_CHSCD        REG8(IT83XX_SMB_BASE+0x21)
-#define IT83XX_SMB_HOSTA(ch)    REG8(IT83XX_SMB_BASE+0x40+(ch << 6))
-#define IT83XX_SMB_HOCTL(ch)    REG8(IT83XX_SMB_BASE+0x41+(ch << 6))
-#define IT83XX_SMB_HOCMD(ch)    REG8(IT83XX_SMB_BASE+0x42+(ch << 6))
-#define IT83XX_SMB_TRASLA(ch)   REG8(IT83XX_SMB_BASE+0x43+(ch << 6))
-#define IT83XX_SMB_D0REG(ch)    REG8(IT83XX_SMB_BASE+0x44+(ch << 6))
-#define IT83XX_SMB_D1REG(ch)    REG8(IT83XX_SMB_BASE+0x45+(ch << 6))
-#define IT83XX_SMB_HOBDB(ch)    REG8(IT83XX_SMB_BASE+0x46+(ch << 6))
-#define IT83XX_SMB_PECERC(ch)   REG8(IT83XX_SMB_BASE+0x47+(ch << 6))
-#define IT83XX_SMB_SMBPCTL(ch)  REG8(IT83XX_SMB_BASE+0x4A+(ch << 6))
-#define IT83XX_SMB_HOCTL2(ch)   REG8(IT83XX_SMB_BASE+0x50+(ch << 6))
-#define IT83XX_SMB_SLVEN        (1 << 5)
-#define IT83XX_SMB_RESLADR      REG8(IT83XX_SMB_BASE+0x48)
-#define IT83XX_SMB_SLDA         REG8(IT83XX_SMB_BASE+0x49)
-#define IT83XX_SMB_SLSTA        REG8(IT83XX_SMB_BASE+0x4B)
-#define IT83XX_SMB_SPDS         (1 << 5)
-#define IT83XX_SMB_RCS          (1 << 3)
-#define IT83XX_SMB_STS          (1 << 2)
-#define IT83XX_SMB_SDS          (1 << 1)
-#define IT83XX_SMB_SICR         REG8(IT83XX_SMB_BASE+0x4C)
-#define IT83XX_SMB_RESLADR2     REG8(IT83XX_SMB_BASE+0x51)
-#define IT83XX_SMB_ENADDR2      (1 << 7)
-#define IT83XX_SMB_SFFCTL       REG8(IT83XX_SMB_BASE+0x55)
-#define IT83XX_SMB_HSAPE        BIT(1)
-#define IT83XX_SMB_SAFE         (1 << 0)
-#define IT83XX_SMB_SFFSTA       REG8(IT83XX_SMB_BASE+0x56)
-#define IT83XX_SMB_SFFFULL      (1 << 6)
+#define IT83XX_SMB_BASE 0x00F01C00
+
+#define IT83XX_SMB_4P7USL REG8(IT83XX_SMB_BASE + 0x00)
+#define IT83XX_SMB_4P0USL REG8(IT83XX_SMB_BASE + 0x01)
+#define IT83XX_SMB_300NS REG8(IT83XX_SMB_BASE + 0x02)
+#define IT83XX_SMB_250NS REG8(IT83XX_SMB_BASE + 0x03)
+#define IT83XX_SMB_25MS REG8(IT83XX_SMB_BASE + 0x04)
+#define IT83XX_SMB_45P3USL REG8(IT83XX_SMB_BASE + 0x05)
+#define IT83XX_SMB_45P3USH REG8(IT83XX_SMB_BASE + 0x06)
+#define IT83XX_SMB_4P7A4P0H REG8(IT83XX_SMB_BASE + 0x07)
+#define IT83XX_SMB_SLVISELR REG8(IT83XX_SMB_BASE + 0x08)
+#define IT83XX_SMB_SCLKTS(ch) REG8(IT83XX_SMB_BASE + 0x09 + ch)
+#define IT83XX_SMB_CHSEF REG8(IT83XX_SMB_BASE + 0x11)
+#define IT83XX_SMB_CHSAB REG8(IT83XX_SMB_BASE + 0x20)
+#define IT83XX_SMB_CHSCD REG8(IT83XX_SMB_BASE + 0x21)
+#define IT83XX_SMB_HOSTA(ch) REG8(IT83XX_SMB_BASE + 0x40 + (ch << 6))
+#define IT83XX_SMB_HOCTL(ch) REG8(IT83XX_SMB_BASE + 0x41 + (ch << 6))
+#define IT83XX_SMB_HOCMD(ch) REG8(IT83XX_SMB_BASE + 0x42 + (ch << 6))
+#define IT83XX_SMB_TRASLA(ch) REG8(IT83XX_SMB_BASE + 0x43 + (ch << 6))
+#define IT83XX_SMB_D0REG(ch) REG8(IT83XX_SMB_BASE + 0x44 + (ch << 6))
+#define IT83XX_SMB_D1REG(ch) REG8(IT83XX_SMB_BASE + 0x45 + (ch << 6))
+#define IT83XX_SMB_HOBDB(ch) REG8(IT83XX_SMB_BASE + 0x46 + (ch << 6))
+#define IT83XX_SMB_PECERC(ch) REG8(IT83XX_SMB_BASE + 0x47 + (ch << 6))
+#define IT83XX_SMB_SMBPCTL(ch) REG8(IT83XX_SMB_BASE + 0x4A + (ch << 6))
+#define IT83XX_SMB_HOCTL2(ch) REG8(IT83XX_SMB_BASE + 0x50 + (ch << 6))
+#define IT83XX_SMB_SLVEN (1 << 5)
+#define IT83XX_SMB_RESLADR REG8(IT83XX_SMB_BASE + 0x48)
+#define IT83XX_SMB_SLDA REG8(IT83XX_SMB_BASE + 0x49)
+#define IT83XX_SMB_SLSTA REG8(IT83XX_SMB_BASE + 0x4B)
+#define IT83XX_SMB_SPDS (1 << 5)
+#define IT83XX_SMB_RCS (1 << 3)
+#define IT83XX_SMB_STS (1 << 2)
+#define IT83XX_SMB_SDS (1 << 1)
+#define IT83XX_SMB_SICR REG8(IT83XX_SMB_BASE + 0x4C)
+#define IT83XX_SMB_RESLADR2 REG8(IT83XX_SMB_BASE + 0x51)
+#define IT83XX_SMB_ENADDR2 (1 << 7)
+#define IT83XX_SMB_SFFCTL REG8(IT83XX_SMB_BASE + 0x55)
+#define IT83XX_SMB_HSAPE BIT(1)
+#define IT83XX_SMB_SAFE (1 << 0)
+#define IT83XX_SMB_SFFSTA REG8(IT83XX_SMB_BASE + 0x56)
+#define IT83XX_SMB_SFFFULL (1 << 6)
 
 /* BRAM */
-#define IT83XX_BRAM_BASE  0x00F02200
+#define IT83XX_BRAM_BASE 0x00F02200
 
 /* offset 0 ~ 0x7f */
-#define IT83XX_BRAM_BANK0(i)    REG8(IT83XX_BRAM_BASE + i)
+#define IT83XX_BRAM_BANK0(i) REG8(IT83XX_BRAM_BASE + i)
 /* Battery backed RAM indices. */
 enum bram_indices {
 	/* reset flags uses 4 bytes */
@@ -1441,21 +1438,21 @@ enum bram_indices {
 	BRAM_IDX_RESET_FLAGS3 = 3,
 
 	/* PD state data for CONFIG_USB_PD_DUAL_ROLE uses 1 byte per port */
-	BRAM_IDX_PD0 =           4,
-	BRAM_IDX_PD1 =           5,
-	BRAM_IDX_PD2 =           6,
+	BRAM_IDX_PD0 = 4,
+	BRAM_IDX_PD1 = 5,
+	BRAM_IDX_PD2 = 6,
 
 	/* index 7 is reserved */
 
-	BRAM_IDX_SCRATCHPAD0  = 8,
-	BRAM_IDX_SCRATCHPAD1  = 9,
-	BRAM_IDX_SCRATCHPAD2  = 0xa,
-	BRAM_IDX_SCRATCHPAD3  = 0xb,
+	BRAM_IDX_SCRATCHPAD0 = 8,
+	BRAM_IDX_SCRATCHPAD1 = 9,
+	BRAM_IDX_SCRATCHPAD2 = 0xa,
+	BRAM_IDX_SCRATCHPAD3 = 0xb,
 
 	/* EC logs status */
 	BRAM_IDX_EC_LOG_STATUS = 0xc,
 
-	/* offset 0x0d ~ 0x1f are reserved for future use. */
+/* offset 0x0d ~ 0x1f are reserved for future use. */
 #if defined(CONFIG_HOST_INTERFACE_LPC) || defined(CONFIG_HOST_INTERFACE_ESPI)
 	/*
 	 * offset 0x20 ~ 0x7b are reserved for future use.
@@ -1463,45 +1460,42 @@ enum bram_indices {
 	 */
 
 	/* This field is used to indicate BRAM is valid or not. */
-	BRAM_IDX_VALID_FLAGS0  = 0x7c,
-	BRAM_IDX_VALID_FLAGS1  = 0x7d,
-	BRAM_IDX_VALID_FLAGS2  = 0x7e,
-	BRAM_IDX_VALID_FLAGS3  = 0x7f
-	/* offset 0x7f is the end of BRAM bank 0. */
+	BRAM_IDX_VALID_FLAGS0 = 0x7c,
+	BRAM_IDX_VALID_FLAGS1 = 0x7d,
+	BRAM_IDX_VALID_FLAGS2 = 0x7e,
+	BRAM_IDX_VALID_FLAGS3 = 0x7f
+/* offset 0x7f is the end of BRAM bank 0. */
 #else
 
 	/* panic data uses 144 bytes (offset 0x20 ~ 0xaf) */
-	BRAM_PANIC_DATA_START  = 0x20,
-	BRAM_PANIC_DATA_END    = 0xaf,
+	BRAM_PANIC_DATA_START = 0x20,
+	BRAM_PANIC_DATA_END = 0xaf,
 
 	/* This field is used to indicate BRAM is valid or not. */
-	BRAM_IDX_VALID_FLAGS0  = 0xbc,
-	BRAM_IDX_VALID_FLAGS1  = 0xbd,
-	BRAM_IDX_VALID_FLAGS2  = 0xbe,
-	BRAM_IDX_VALID_FLAGS3  = 0xbf
-	/* offset 0xbf is the end of BRAM bank 1. */
+	BRAM_IDX_VALID_FLAGS0 = 0xbc,
+	BRAM_IDX_VALID_FLAGS1 = 0xbd,
+	BRAM_IDX_VALID_FLAGS2 = 0xbe,
+	BRAM_IDX_VALID_FLAGS3 = 0xbf
+/* offset 0xbf is the end of BRAM bank 1. */
 #endif
 };
-#define BRAM_RESET_FLAGS0       IT83XX_BRAM_BANK0(BRAM_IDX_RESET_FLAGS0)
-#define BRAM_RESET_FLAGS1       IT83XX_BRAM_BANK0(BRAM_IDX_RESET_FLAGS1)
-#define BRAM_RESET_FLAGS2       IT83XX_BRAM_BANK0(BRAM_IDX_RESET_FLAGS2)
-#define BRAM_RESET_FLAGS3       IT83XX_BRAM_BANK0(BRAM_IDX_RESET_FLAGS3)
-
-#define BRAM_SCRATCHPAD0        IT83XX_BRAM_BANK0(BRAM_IDX_SCRATCHPAD0)
-#define BRAM_SCRATCHPAD1        IT83XX_BRAM_BANK0(BRAM_IDX_SCRATCHPAD1)
-#define BRAM_SCRATCHPAD2        IT83XX_BRAM_BANK0(BRAM_IDX_SCRATCHPAD2)
-#define BRAM_SCRATCHPAD3        IT83XX_BRAM_BANK0(BRAM_IDX_SCRATCHPAD3)
-
-#define BRAM_EC_LOG_STATUS      IT83XX_BRAM_BANK0(BRAM_IDX_EC_LOG_STATUS)
-enum bram_ec_logs_status {
-	EC_LOG_SAVED_IN_FLASH = 1,
-	EC_LOG_SAVED_IN_MEMORY
-};
+#define BRAM_RESET_FLAGS0 IT83XX_BRAM_BANK0(BRAM_IDX_RESET_FLAGS0)
+#define BRAM_RESET_FLAGS1 IT83XX_BRAM_BANK0(BRAM_IDX_RESET_FLAGS1)
+#define BRAM_RESET_FLAGS2 IT83XX_BRAM_BANK0(BRAM_IDX_RESET_FLAGS2)
+#define BRAM_RESET_FLAGS3 IT83XX_BRAM_BANK0(BRAM_IDX_RESET_FLAGS3)
+
+#define BRAM_SCRATCHPAD0 IT83XX_BRAM_BANK0(BRAM_IDX_SCRATCHPAD0)
+#define BRAM_SCRATCHPAD1 IT83XX_BRAM_BANK0(BRAM_IDX_SCRATCHPAD1)
+#define BRAM_SCRATCHPAD2 IT83XX_BRAM_BANK0(BRAM_IDX_SCRATCHPAD2)
+#define BRAM_SCRATCHPAD3 IT83XX_BRAM_BANK0(BRAM_IDX_SCRATCHPAD3)
+
+#define BRAM_EC_LOG_STATUS IT83XX_BRAM_BANK0(BRAM_IDX_EC_LOG_STATUS)
+enum bram_ec_logs_status { EC_LOG_SAVED_IN_FLASH = 1, EC_LOG_SAVED_IN_MEMORY };
 
-#define BRAM_VALID_FLAGS0       IT83XX_BRAM_BANK0(BRAM_IDX_VALID_FLAGS0)
-#define BRAM_VALID_FLAGS1       IT83XX_BRAM_BANK0(BRAM_IDX_VALID_FLAGS1)
-#define BRAM_VALID_FLAGS2       IT83XX_BRAM_BANK0(BRAM_IDX_VALID_FLAGS2)
-#define BRAM_VALID_FLAGS3       IT83XX_BRAM_BANK0(BRAM_IDX_VALID_FLAGS3)
+#define BRAM_VALID_FLAGS0 IT83XX_BRAM_BANK0(BRAM_IDX_VALID_FLAGS0)
+#define BRAM_VALID_FLAGS1 IT83XX_BRAM_BANK0(BRAM_IDX_VALID_FLAGS1)
+#define BRAM_VALID_FLAGS2 IT83XX_BRAM_BANK0(BRAM_IDX_VALID_FLAGS2)
+#define BRAM_VALID_FLAGS3 IT83XX_BRAM_BANK0(BRAM_IDX_VALID_FLAGS3)
 
 /*
  * These 128 bytes are use to latch port 80h data on x86 platform.
@@ -1510,7 +1504,7 @@ enum bram_ec_logs_status {
  */
 #if defined(CONFIG_HOST_INTERFACE_LPC) || defined(CONFIG_HOST_INTERFACE_ESPI)
 /* offset 0x80 ~ 0xbf */
-#define IT83XX_BRAM_BANK1(i)    REG8(IT83XX_BRAM_BASE + 0x80 + i)
+#define IT83XX_BRAM_BANK1(i) REG8(IT83XX_BRAM_BASE + 0x80 + i)
 #else
 /* Length of bram panic data */
 #define BRAM_PANIC_LEN (BRAM_PANIC_DATA_END - BRAM_PANIC_DATA_START + 1)
@@ -1521,153 +1515,153 @@ enum bram_ec_logs_status {
  * Ch_D: 0x00F03680 , Ch_E: 0x00F03500 , Ch_F: 0x00F03580
  * Ch_D: ch = 0x03  , Ch_E: ch = 0x00  , Ch_F: ch = 0x01
  */
-#define IT83XX_I2C_BASE   0x00F03500
-
-#define IT83XX_I2C_DRR(ch)           REG8(IT83XX_I2C_BASE+0x00+(ch << 7))
-#define IT83XX_I2C_PSR(ch)           REG8(IT83XX_I2C_BASE+0x01+(ch << 7))
-#define IT83XX_I2C_HSPR(ch)          REG8(IT83XX_I2C_BASE+0x02+(ch << 7))
-#define IT83XX_I2C_STR(ch)           REG8(IT83XX_I2C_BASE+0x03+(ch << 7))
-#define IT83XX_I2C_BB                (1 << 5)
-#define IT83XX_I2C_TIME_OUT          (1 << 3)
-#define IT83XX_I2C_RW                (1 << 2)
-#define IT83XX_I2C_INTPEND           (1 << 1)
-#define IT83XX_I2C_DHTR(ch)          REG8(IT83XX_I2C_BASE+0x04+(ch << 7))
-#define IT83XX_I2C_TOR(ch)           REG8(IT83XX_I2C_BASE+0x05+(ch << 7))
-#define IT83XX_I2C_DTR(ch)           REG8(IT83XX_I2C_BASE+0x08+(ch << 7))
-#define IT83XX_I2C_CTR(ch)           REG8(IT83XX_I2C_BASE+0x09+(ch << 7))
-#define IT83XX_I2C_INTEN             (1 << 6)
-#define IT83XX_I2C_MODE              (1 << 5)
-#define IT83XX_I2C_STARST            (1 << 4)
-#define IT83XX_I2C_ACK               (1 << 3)
-#define IT83XX_I2C_HALT              (1 << 0)
-#define IT83XX_I2C_CTR1(ch)          REG8(IT83XX_I2C_BASE+0x0A+(ch << 7))
-#define IT83XX_I2C_COMQ_EN           (1 << 7)
-#define IT83XX_I2C_MDL_EN            (1 << 1)
-#define IT83XX_I2C_BYTE_CNT_L(ch)    REG8(IT83XX_I2C_BASE+0x0C+(ch << 7))
-#define IT83XX_I2C_IRQ_ST(ch)        REG8(IT83XX_I2C_BASE+0x0D+(ch << 7))
-#define IT83XX_I2C_IDW_CLR           (1 << 3)
-#define IT83XX_I2C_IDR_CLR           (1 << 2)
-#define IT83XX_I2C_SLVDATAFLG        (1 << 1)
-#define IT83XX_I2C_P_CLR             (1 << 0)
-#define IT83XX_I2C_IDR(ch)           REG8(IT83XX_I2C_BASE+0x06+(ch << 7))
-#define IT83XX_I2C_TOS(ch)           REG8(IT83XX_I2C_BASE+0x07+(ch << 7))
-#define IT83XX_I2C_CLK_STR           (1 << 7)
-#define IT83XX_I2C_STR2(ch)          REG8(IT83XX_I2C_BASE+0x12+(ch << 7))
-#define IT83XX_I2C_NST(ch)           REG8(IT83XX_I2C_BASE+0x13+(ch << 7))
-#define IT83XX_I2C_NST_CNS           BIT(7)
-#define IT83XX_I2C_NST_ID_NACK       BIT(3)
-#define IT83XX_I2C_TO_ARB_ST(ch)     REG8(IT83XX_I2C_BASE+0x18+(ch << 7))
-#define IT83XX_I2C_ERR_ST(ch)        REG8(IT83XX_I2C_BASE+0x19+(ch << 7))
-#define IT83XX_I2C_ERR_ST_DEV1_EIRQ  BIT(0)
-#define IT83XX_I2C_FST(ch)           REG8(IT83XX_I2C_BASE+0x1b+(ch << 7))
-#define IT83XX_I2C_FST_DEV1_IRQ      BIT(4)
-#define IT83XX_I2C_EM(ch)            REG8(IT83XX_I2C_BASE+0x1c+(ch << 7))
-#define IT83XX_I2C_EM_DEV1_IRQ       BIT(4)
-#define IT83XX_I2C_MODE_SEL(ch)      REG8(IT83XX_I2C_BASE+0x1d+(ch << 7))
-#define IT83XX_I2C_IDR2(ch)          REG8(IT83XX_I2C_BASE+0x1F+(ch << 7))
-#define IT83XX_I2C_CTR2(ch)          REG8(IT83XX_I2C_BASE+0x20+(ch << 7))
-#define IT83XX_I2C_RAMHA(ch)         REG8(IT83XX_I2C_BASE+0x23+(ch << 7))
-#define IT83XX_I2C_RAMLA(ch)         REG8(IT83XX_I2C_BASE+0x24+(ch << 7))
-#define IT83XX_I2C_RAMHA2(ch)        REG8(IT83XX_I2C_BASE+0x2B+(ch << 7))
-#define IT83XX_I2C_RAMLA2(ch)        REG8(IT83XX_I2C_BASE+0x2C+(ch << 7))
-#define IT83XX_I2C_CMD_ADDH(ch)      REG8(IT83XX_I2C_BASE+0x25+(ch << 7))
-#define IT83XX_I2C_CMD_ADDL(ch)      REG8(IT83XX_I2C_BASE+0x26+(ch << 7))
-#define IT83XX_I2C_RAMH2A(ch)        REG8(IT83XX_I2C_BASE+0x50+(ch << 7))
-#define IT83XX_I2C_CMD_ADDH2(ch)     REG8(IT83XX_I2C_BASE+0x52+(ch << 7))
+#define IT83XX_I2C_BASE 0x00F03500
+
+#define IT83XX_I2C_DRR(ch) REG8(IT83XX_I2C_BASE + 0x00 + (ch << 7))
+#define IT83XX_I2C_PSR(ch) REG8(IT83XX_I2C_BASE + 0x01 + (ch << 7))
+#define IT83XX_I2C_HSPR(ch) REG8(IT83XX_I2C_BASE + 0x02 + (ch << 7))
+#define IT83XX_I2C_STR(ch) REG8(IT83XX_I2C_BASE + 0x03 + (ch << 7))
+#define IT83XX_I2C_BB (1 << 5)
+#define IT83XX_I2C_TIME_OUT (1 << 3)
+#define IT83XX_I2C_RW (1 << 2)
+#define IT83XX_I2C_INTPEND (1 << 1)
+#define IT83XX_I2C_DHTR(ch) REG8(IT83XX_I2C_BASE + 0x04 + (ch << 7))
+#define IT83XX_I2C_TOR(ch) REG8(IT83XX_I2C_BASE + 0x05 + (ch << 7))
+#define IT83XX_I2C_DTR(ch) REG8(IT83XX_I2C_BASE + 0x08 + (ch << 7))
+#define IT83XX_I2C_CTR(ch) REG8(IT83XX_I2C_BASE + 0x09 + (ch << 7))
+#define IT83XX_I2C_INTEN (1 << 6)
+#define IT83XX_I2C_MODE (1 << 5)
+#define IT83XX_I2C_STARST (1 << 4)
+#define IT83XX_I2C_ACK (1 << 3)
+#define IT83XX_I2C_HALT (1 << 0)
+#define IT83XX_I2C_CTR1(ch) REG8(IT83XX_I2C_BASE + 0x0A + (ch << 7))
+#define IT83XX_I2C_COMQ_EN (1 << 7)
+#define IT83XX_I2C_MDL_EN (1 << 1)
+#define IT83XX_I2C_BYTE_CNT_L(ch) REG8(IT83XX_I2C_BASE + 0x0C + (ch << 7))
+#define IT83XX_I2C_IRQ_ST(ch) REG8(IT83XX_I2C_BASE + 0x0D + (ch << 7))
+#define IT83XX_I2C_IDW_CLR (1 << 3)
+#define IT83XX_I2C_IDR_CLR (1 << 2)
+#define IT83XX_I2C_SLVDATAFLG (1 << 1)
+#define IT83XX_I2C_P_CLR (1 << 0)
+#define IT83XX_I2C_IDR(ch) REG8(IT83XX_I2C_BASE + 0x06 + (ch << 7))
+#define IT83XX_I2C_TOS(ch) REG8(IT83XX_I2C_BASE + 0x07 + (ch << 7))
+#define IT83XX_I2C_CLK_STR (1 << 7)
+#define IT83XX_I2C_STR2(ch) REG8(IT83XX_I2C_BASE + 0x12 + (ch << 7))
+#define IT83XX_I2C_NST(ch) REG8(IT83XX_I2C_BASE + 0x13 + (ch << 7))
+#define IT83XX_I2C_NST_CNS BIT(7)
+#define IT83XX_I2C_NST_ID_NACK BIT(3)
+#define IT83XX_I2C_TO_ARB_ST(ch) REG8(IT83XX_I2C_BASE + 0x18 + (ch << 7))
+#define IT83XX_I2C_ERR_ST(ch) REG8(IT83XX_I2C_BASE + 0x19 + (ch << 7))
+#define IT83XX_I2C_ERR_ST_DEV1_EIRQ BIT(0)
+#define IT83XX_I2C_FST(ch) REG8(IT83XX_I2C_BASE + 0x1b + (ch << 7))
+#define IT83XX_I2C_FST_DEV1_IRQ BIT(4)
+#define IT83XX_I2C_EM(ch) REG8(IT83XX_I2C_BASE + 0x1c + (ch << 7))
+#define IT83XX_I2C_EM_DEV1_IRQ BIT(4)
+#define IT83XX_I2C_MODE_SEL(ch) REG8(IT83XX_I2C_BASE + 0x1d + (ch << 7))
+#define IT83XX_I2C_IDR2(ch) REG8(IT83XX_I2C_BASE + 0x1F + (ch << 7))
+#define IT83XX_I2C_CTR2(ch) REG8(IT83XX_I2C_BASE + 0x20 + (ch << 7))
+#define IT83XX_I2C_RAMHA(ch) REG8(IT83XX_I2C_BASE + 0x23 + (ch << 7))
+#define IT83XX_I2C_RAMLA(ch) REG8(IT83XX_I2C_BASE + 0x24 + (ch << 7))
+#define IT83XX_I2C_RAMHA2(ch) REG8(IT83XX_I2C_BASE + 0x2B + (ch << 7))
+#define IT83XX_I2C_RAMLA2(ch) REG8(IT83XX_I2C_BASE + 0x2C + (ch << 7))
+#define IT83XX_I2C_CMD_ADDH(ch) REG8(IT83XX_I2C_BASE + 0x25 + (ch << 7))
+#define IT83XX_I2C_CMD_ADDL(ch) REG8(IT83XX_I2C_BASE + 0x26 + (ch << 7))
+#define IT83XX_I2C_RAMH2A(ch) REG8(IT83XX_I2C_BASE + 0x50 + (ch << 7))
+#define IT83XX_I2C_CMD_ADDH2(ch) REG8(IT83XX_I2C_BASE + 0x52 + (ch << 7))
 
 enum i2c_channels {
-	IT83XX_I2C_CH_A,  /* GPIO.B3/B4 */
-	IT83XX_I2C_CH_B,  /* GPIO.C1/C2 */
-	IT83XX_I2C_CH_C,  /* GPIO.F6/F7 or GPIO.C7/F7 */
-	IT83XX_I2C_CH_D,  /* GPIO.H1/H2 */
-	IT83XX_I2C_CH_E,  /* GPIO.E0/E7 */
-	IT83XX_I2C_CH_F,  /* GPIO.A4/A5 (for util/iteflash) */
+	IT83XX_I2C_CH_A, /* GPIO.B3/B4 */
+	IT83XX_I2C_CH_B, /* GPIO.C1/C2 */
+	IT83XX_I2C_CH_C, /* GPIO.F6/F7 or GPIO.C7/F7 */
+	IT83XX_I2C_CH_D, /* GPIO.H1/H2 */
+	IT83XX_I2C_CH_E, /* GPIO.E0/E7 */
+	IT83XX_I2C_CH_F, /* GPIO.A4/A5 (for util/iteflash) */
 	IT83XX_I2C_PORT_COUNT,
 };
 
 #define USB_VID_ITE 0x048d
 
-#define IT83XX_ESPI_BASE  0x00F03100
+#define IT83XX_ESPI_BASE 0x00F03100
 
-#define IT83XX_ESPI_GCAC1      REG8(IT83XX_ESPI_BASE+0x05)
-#define IT83XX_ESPI_ESPCTRL0   REG8(IT83XX_ESPI_BASE+0x90)
-#define IT83XX_ESPI_ESGCTRL0   REG8(IT83XX_ESPI_BASE+0xA0)
-#define IT83XX_ESPI_ESGCTRL1   REG8(IT83XX_ESPI_BASE+0xA1)
-#define IT83XX_ESPI_ESGCTRL2   REG8(IT83XX_ESPI_BASE+0xA2)
+#define IT83XX_ESPI_GCAC1 REG8(IT83XX_ESPI_BASE + 0x05)
+#define IT83XX_ESPI_ESPCTRL0 REG8(IT83XX_ESPI_BASE + 0x90)
+#define IT83XX_ESPI_ESGCTRL0 REG8(IT83XX_ESPI_BASE + 0xA0)
+#define IT83XX_ESPI_ESGCTRL1 REG8(IT83XX_ESPI_BASE + 0xA1)
+#define IT83XX_ESPI_ESGCTRL2 REG8(IT83XX_ESPI_BASE + 0xA2)
 
 /* eSPI VW */
-#define IT83XX_ESPI_VW_BASE  0x00F03200
-#define IT83XX_ESPI_VWIDX(i)   REG8(IT83XX_ESPI_VW_BASE+(i))
+#define IT83XX_ESPI_VW_BASE 0x00F03200
+#define IT83XX_ESPI_VWIDX(i) REG8(IT83XX_ESPI_VW_BASE + (i))
 
-#define VW_LEVEL_FIELD(f)          ((f) << 0)
-#define VW_VALID_FIELD(f)          ((f) << 4)
+#define VW_LEVEL_FIELD(f) ((f) << 0)
+#define VW_VALID_FIELD(f) ((f) << 4)
 
 #define ESPI_SYSTEM_EVENT_VW_IDX_2 0x2
-#define VW_IDX_2_SLP_S3            BIT(0)
-#define VW_IDX_2_SLP_S4            BIT(1)
-#define VW_IDX_2_SLP_S5            BIT(2)
+#define VW_IDX_2_SLP_S3 BIT(0)
+#define VW_IDX_2_SLP_S4 BIT(1)
+#define VW_IDX_2_SLP_S5 BIT(2)
 
 #define ESPI_SYSTEM_EVENT_VW_IDX_3 0x3
-#define VW_IDX_3_SUS_STAT          BIT(0)
-#define VW_IDX_3_PLTRST            BIT(1)
-#define VW_IDX_3_OOB_RST_WARN      BIT(2)
+#define VW_IDX_3_SUS_STAT BIT(0)
+#define VW_IDX_3_PLTRST BIT(1)
+#define VW_IDX_3_OOB_RST_WARN BIT(2)
 
 #define ESPI_SYSTEM_EVENT_VW_IDX_4 0x4
-#define VW_IDX_4_OOB_RST_ACK       BIT(0)
-#define VW_IDX_4_WAKE              BIT(2)
-#define VW_IDX_4_PME               BIT(3)
+#define VW_IDX_4_OOB_RST_ACK BIT(0)
+#define VW_IDX_4_WAKE BIT(2)
+#define VW_IDX_4_PME BIT(3)
 
 #define ESPI_SYSTEM_EVENT_VW_IDX_5 0x5
-#define VW_IDX_5_SLAVE_BTLD_DONE   BIT(0)
-#define VW_IDX_5_FATAL             BIT(1)
-#define VW_IDX_5_NON_FATAL         BIT(2)
+#define VW_IDX_5_SLAVE_BTLD_DONE BIT(0)
+#define VW_IDX_5_FATAL BIT(1)
+#define VW_IDX_5_NON_FATAL BIT(2)
 #define VW_IDX_5_SLAVE_BTLD_STATUS BIT(3)
-#define VW_IDX_5_BTLD_STATUS_DONE  (VW_IDX_5_SLAVE_BTLD_DONE | \
-					VW_IDX_5_SLAVE_BTLD_STATUS)
+#define VW_IDX_5_BTLD_STATUS_DONE \
+	(VW_IDX_5_SLAVE_BTLD_DONE | VW_IDX_5_SLAVE_BTLD_STATUS)
 
 #define ESPI_SYSTEM_EVENT_VW_IDX_6 0x6
-#define VW_IDX_6_SCI               BIT(0)
-#define VW_IDX_6_SMI               BIT(1)
-#define VW_IDX_6_RCIN              BIT(2)
-#define VW_IDX_6_HOST_RST_ACK      BIT(3)
+#define VW_IDX_6_SCI BIT(0)
+#define VW_IDX_6_SMI BIT(1)
+#define VW_IDX_6_RCIN BIT(2)
+#define VW_IDX_6_HOST_RST_ACK BIT(3)
 
 #define ESPI_SYSTEM_EVENT_VW_IDX_7 0x7
-#define VW_IDX_7_HOST_RST_WARN     BIT(0)
+#define VW_IDX_7_HOST_RST_WARN BIT(0)
 
 #define ESPI_SYSTEM_EVENT_VW_IDX_40 0x40
-#define VW_IDX_40_SUS_ACK           BIT(0)
+#define VW_IDX_40_SUS_ACK BIT(0)
 
 #define ESPI_SYSTEM_EVENT_VW_IDX_41 0x41
-#define VW_IDX_41_SUS_WARN          BIT(0)
-#define VW_IDX_41_SUS_PWRDN_ACK     BIT(1)
-#define VW_IDX_41_SLP_A             BIT(3)
+#define VW_IDX_41_SUS_WARN BIT(0)
+#define VW_IDX_41_SUS_PWRDN_ACK BIT(1)
+#define VW_IDX_41_SLP_A BIT(3)
 
 #define ESPI_SYSTEM_EVENT_VW_IDX_42 0x42
-#define VW_IDX_42_SLP_LAN           BIT(0)
-#define VW_IDX_42_SLP_WLAN          BIT(1)
+#define VW_IDX_42_SLP_LAN BIT(0)
+#define VW_IDX_42_SLP_WLAN BIT(1)
 
 #define ESPI_SYSTEM_EVENT_VW_IDX_43 0x43
 #define ESPI_SYSTEM_EVENT_VW_IDX_44 0x44
 #define ESPI_SYSTEM_EVENT_VW_IDX_47 0x47
 
-#define IT83XX_ESPI_VWCTRL0    REG8(IT83XX_ESPI_VW_BASE+0x90)
+#define IT83XX_ESPI_VWCTRL0 REG8(IT83XX_ESPI_VW_BASE + 0x90)
 #define ESPI_INTERRUPT_EVENT_PUT_PC BIT(7)
 
-#define IT83XX_ESPI_VWCTRL1    REG8(IT83XX_ESPI_VW_BASE+0x91)
-#define IT83XX_ESPI_VWCTRL2    REG8(IT83XX_ESPI_VW_BASE+0x92)
-#define IT83XX_ESPI_VWCTRL3    REG8(IT83XX_ESPI_VW_BASE+0x93)
+#define IT83XX_ESPI_VWCTRL1 REG8(IT83XX_ESPI_VW_BASE + 0x91)
+#define IT83XX_ESPI_VWCTRL2 REG8(IT83XX_ESPI_VW_BASE + 0x92)
+#define IT83XX_ESPI_VWCTRL3 REG8(IT83XX_ESPI_VW_BASE + 0x93)
 
 /* eSPI Queue 0 */
-#define IT83XX_ESPI_QUEUE_BASE  0x00F03300
+#define IT83XX_ESPI_QUEUE_BASE 0x00F03300
 /* PUT_PC data byte 0 - 63 */
-#define IT83XX_ESPI_QUEUE_PUT_PC(i)  REG8(IT83XX_ESPI_QUEUE_BASE+(i))
+#define IT83XX_ESPI_QUEUE_PUT_PC(i) REG8(IT83XX_ESPI_QUEUE_BASE + (i))
 /* PUT_OOB data byte 0 - 79 */
-#define IT83XX_ESPI_QUEUE_PUT_OOB(i) REG8(IT83XX_ESPI_QUEUE_BASE+0x80+(i))
+#define IT83XX_ESPI_QUEUE_PUT_OOB(i) REG8(IT83XX_ESPI_QUEUE_BASE + 0x80 + (i))
 
 /* USB Controller */
-#define IT83XX_USB_BASE   0x00F02F00
+#define IT83XX_USB_BASE 0x00F02F00
 
-#define IT83XX_USB_P0MCR  REG8(IT83XX_USB_BASE+0xE4)
+#define IT83XX_USB_P0MCR REG8(IT83XX_USB_BASE + 0xE4)
 #define USB_DP_DM_PULL_DOWN_EN BIT(4)
 
 /* Wake pin definitions, defined at board-level */
@@ -1681,11 +1675,11 @@ extern int hibernate_wake_pins_used;
 
 /* --- MISC (not implemented yet) --- */
 
-#define IT83XX_PS2_BASE   0x00F01700
+#define IT83XX_PS2_BASE 0x00F01700
 #define IT83XX_EGPIO_BASE 0x00F02100
-#define IT83XX_CIR_BASE   0x00F02300
-#define IT83XX_DBGR_BASE  0x00F02500
-#define IT83XX_OW_BASE    0x00F02A00
-#define IT83XX_CEC_BASE   0x00F02E00
+#define IT83XX_CIR_BASE 0x00F02300
+#define IT83XX_DBGR_BASE 0x00F02500
+#define IT83XX_OW_BASE 0x00F02A00
+#define IT83XX_CEC_BASE 0x00F02E00
 
 #endif /* __CROS_EC_REGISTERS_H */
diff --git a/chip/it83xx/spi.c b/chip/it83xx/spi.c
index 23885f41a3..c172e9fca9 100644
--- a/chip/it83xx/spi.c
+++ b/chip/it83xx/spi.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -20,8 +20,8 @@
 #include "util.h"
 
 /* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SPI, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SPI, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SPI, format, ##args)
 
 #define SPI_RX_MAX_FIFO_SIZE 256
 #define SPI_TX_MAX_FIFO_SIZE 256
@@ -31,8 +31,8 @@
 
 /* Max data size for a version 3 request/response packet. */
 #define SPI_MAX_REQUEST_SIZE SPI_RX_MAX_FIFO_SIZE
-#define SPI_MAX_RESPONSE_SIZE (SPI_TX_MAX_FIFO_SIZE - \
-	EC_SPI_PREAMBLE_LENGTH - EC_SPI_PAST_END_LENGTH)
+#define SPI_MAX_RESPONSE_SIZE \
+	(SPI_TX_MAX_FIFO_SIZE - EC_SPI_PREAMBLE_LENGTH - EC_SPI_PAST_END_LENGTH)
 
 static const uint8_t out_preamble[EC_SPI_PREAMBLE_LENGTH] = {
 	EC_SPI_PROCESSING,
@@ -64,9 +64,9 @@ enum spi_peripheral_state_machine {
 
 static const int spi_response_state[] = {
 	[SPI_STATE_READY_TO_RECV] = EC_SPI_RX_READY,
-	[SPI_STATE_RECEIVING]     = EC_SPI_RECEIVING,
-	[SPI_STATE_PROCESSING]    = EC_SPI_PROCESSING,
-	[SPI_STATE_RX_BAD]        = EC_SPI_RX_BAD_DATA,
+	[SPI_STATE_RECEIVING] = EC_SPI_RECEIVING,
+	[SPI_STATE_PROCESSING] = EC_SPI_PROCESSING,
+	[SPI_STATE_RX_BAD] = EC_SPI_RX_BAD_DATA,
 };
 BUILD_ASSERT(ARRAY_SIZE(spi_response_state) == SPI_STATE_COUNT);
 
@@ -145,11 +145,11 @@ static void spi_send_response_packet(struct host_packet *pkt)
 
 	/* Append our past-end byte, which we reserved space for. */
 	for (i = 0; i < EC_SPI_PAST_END_LENGTH; i++)
-		((uint8_t *)pkt->response)[pkt->response_size + i]
-			= EC_SPI_PAST_END;
+		((uint8_t *)pkt->response)[pkt->response_size + i] =
+			EC_SPI_PAST_END;
 
 	tx_size = pkt->response_size + EC_SPI_PREAMBLE_LENGTH +
-			EC_SPI_PAST_END_LENGTH;
+		  EC_SPI_PAST_END_LENGTH;
 
 	/* Transmit the reply */
 	spi_response_host_data(out_msg, tx_size);
@@ -194,7 +194,7 @@ static void spi_parse_header(void)
 
 		/* Store request data from Rx FIFO to in_msg buffer */
 		spi_host_request_data(in_msg + sizeof(*r),
-			pkt_size - sizeof(*r));
+				      pkt_size - sizeof(*r));
 
 		/* Set up parameters for host request */
 		spi_packet.send_response = spi_send_response_packet;
@@ -327,8 +327,8 @@ static void spi_init(void)
 	 * bit3 : Rx FIFO1 will not be overwrited once it's full.
 	 * bit0 : Rx FIFO1/FIFO2 will reset after each CS_N goes high.
 	 */
-	IT83XX_SPI_GCR2 = IT83XX_SPI_RXF2OC | IT83XX_SPI_RXF1OC
-				| IT83XX_SPI_RXFAR;
+	IT83XX_SPI_GCR2 = IT83XX_SPI_RXF2OC | IT83XX_SPI_RXF1OC |
+			  IT83XX_SPI_RXFAR;
 	/*
 	 * Interrupt mask register (0b:Enable, 1b:Mask)
 	 * bit5 : Rx byte reach interrupt mask
@@ -395,9 +395,8 @@ static enum ec_status _spi_get_protocol_info(struct host_cmd_handler_args *args)
 
 	return EC_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO,
-		_spi_get_protocol_info,
-		EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, _spi_get_protocol_info,
+		     EC_VER_MASK(0));
 
 enum ec_status spi_get_protocol_info(struct host_cmd_handler_args *args)
 {
diff --git a/chip/it83xx/spi_controller.c b/chip/it83xx/spi_controller.c
index d3898deef6..aaab27e138 100644
--- a/chip/it83xx/spi_controller.c
+++ b/chip/it83xx/spi_controller.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,7 +17,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_SPI, outstr)
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SPI, format, ##args)
 
 enum sspi_clk_sel {
 	sspi_clk_24mhz = 0,
@@ -106,8 +106,8 @@ int spi_enable(const struct spi_device_t *spi_device, int enable)
 }
 
 int spi_transaction(const struct spi_device_t *spi_device,
-		const uint8_t *txdata, int txlen,
-		uint8_t *rxdata, int rxlen)
+		    const uint8_t *txdata, int txlen, uint8_t *rxdata,
+		    int rxlen)
 {
 	int idx;
 	uint8_t port = spi_device->port;
diff --git a/chip/it83xx/system.c b/chip/it83xx/system.c
index ae7fd627bf..09c5678cd4 100644
--- a/chip/it83xx/system.c
+++ b/chip/it83xx/system.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,6 +14,7 @@
 #include "host_command.h"
 #include "intc.h"
 #include "link_defs.h"
+#include "panic.h"
 #include "registers.h"
 #include "system.h"
 #include "task.h"
@@ -44,7 +45,7 @@ static int delayed_clear_reset_flags;
 static void clear_reset_flags(void)
 {
 	if (IS_ENABLED(CONFIG_BOARD_RESET_AFTER_POWER_ON) &&
-			delayed_clear_reset_flags) {
+	    delayed_clear_reset_flags) {
 		chip_save_reset_flags(0);
 	}
 }
@@ -68,8 +69,12 @@ static void system_restore_panic_data_from_bram(void)
 }
 BUILD_ASSERT(BRAM_PANIC_LEN >= CONFIG_PANIC_DATA_SIZE);
 #else
-static void system_save_panic_data_to_bram(void) {}
-static void system_restore_panic_data_from_bram(void) {}
+static void system_save_panic_data_to_bram(void)
+{
+}
+static void system_restore_panic_data_from_bram(void)
+{
+}
 #endif
 
 static void system_reset_ec_by_gpg1(void)
@@ -132,7 +137,7 @@ static void check_reset_cause(void)
 	 * we know this is the first reset.
 	 */
 	if (IS_ENABLED(CONFIG_BOARD_RESET_AFTER_POWER_ON) &&
-			(flags & EC_RESET_FLAG_POWER_ON)) {
+	    (flags & EC_RESET_FLAG_POWER_ON)) {
 		if (flags & EC_RESET_FLAG_INITIAL_PWR) {
 			/* Second boot, clear the flag immediately */
 			chip_save_reset_flags(0);
@@ -146,7 +151,7 @@ static void check_reset_cause(void)
 			 * fine because we will have the correct flag anyway.
 			 */
 			chip_save_reset_flags(chip_read_reset_flags() |
-						EC_RESET_FLAG_INITIAL_PWR);
+					      EC_RESET_FLAG_INITIAL_PWR);
 
 			/*
 			 * Schedule chip_save_reset_flags(0) later.
@@ -163,13 +168,13 @@ static void check_reset_cause(void)
 
 	/* Clear PD contract recorded in bram if this is a power-on reset. */
 	if (IS_ENABLED(CONFIG_IT83XX_RESET_PD_CONTRACT_IN_BRAM) &&
-	   (flags == (EC_RESET_FLAG_POWER_ON | EC_RESET_FLAG_RESET_PIN))) {
+	    (flags == (EC_RESET_FLAG_POWER_ON | EC_RESET_FLAG_RESET_PIN))) {
 		for (int i = 0; i < MAX_SYSTEM_BBRAM_IDX_PD_PORTS; i++)
 			system_set_bbram((SYSTEM_BBRAM_IDX_PD0 + i), 0);
 	}
 
 	if ((IS_ENABLED(CONFIG_IT83XX_HARD_RESET_BY_GPG1)) &&
-		(flags & ~(EC_RESET_FLAG_POWER_ON | EC_RESET_FLAG_RESET_PIN)))
+	    (flags & ~(EC_RESET_FLAG_POWER_ON | EC_RESET_FLAG_RESET_PIN)))
 		system_restore_panic_data_from_bram();
 }
 
@@ -183,7 +188,7 @@ static void system_reset_cause_is_unknown(void)
 		 * eg: Andes core (jral5: LP=PC+2, jal: LP=PC+4)
 		 */
 		ccprintf("===Unknown reset! jump from %x or %x===\n",
-				ec_reset_lp - 4, ec_reset_lp - 2);
+			 ec_reset_lp - 4, ec_reset_lp - 2);
 }
 DECLARE_HOOK(HOOK_INIT, system_reset_cause_is_unknown, HOOK_PRIO_FIRST);
 
@@ -239,7 +244,7 @@ void chip_pre_init(void)
 		IT83XX_GCTRL_WMCR |= BIT(7);
 }
 
-#define BRAM_VALID_MAGIC        0x4252414D  /* "BRAM" */
+#define BRAM_VALID_MAGIC 0x4252414D /* "BRAM" */
 #define BRAM_VALID_MAGIC_FIELD0 (BRAM_VALID_MAGIC & 0xff)
 #define BRAM_VALID_MAGIC_FIELD1 ((BRAM_VALID_MAGIC >> 8) & 0xff)
 #define BRAM_VALID_MAGIC_FIELD2 ((BRAM_VALID_MAGIC >> 16) & 0xff)
@@ -269,8 +274,8 @@ void chip_bram_valid(void)
 	if (BRAM_EC_LOG_STATUS == EC_LOG_SAVED_IN_FLASH) {
 		/* Restore EC logs from flash. */
 		memcpy((void *)__preserved_logs_start,
-			(const void *)CHIP_FLASH_PRESERVE_LOGS_BASE,
-			(uintptr_t)__preserved_logs_size);
+		       (const void *)CHIP_FLASH_PRESERVE_LOGS_BASE,
+		       (uintptr_t)__preserved_logs_size);
 	}
 	BRAM_EC_LOG_STATUS = 0;
 #endif
@@ -279,7 +284,6 @@ void chip_bram_valid(void)
 void system_pre_init(void)
 {
 	/* No initialization required */
-
 }
 
 uint32_t chip_read_reset_flags(void)
@@ -313,9 +317,10 @@ void system_reset(int flags)
 #if defined(CONFIG_PRESERVE_LOGS) && defined(CONFIG_IT83XX_HARD_RESET_BY_GPG1)
 	/* Saving EC logs into flash before reset. */
 	crec_flash_physical_erase(CHIP_FLASH_PRESERVE_LOGS_BASE,
-		CHIP_FLASH_PRESERVE_LOGS_SIZE);
+				  CHIP_FLASH_PRESERVE_LOGS_SIZE);
 	crec_flash_physical_write(CHIP_FLASH_PRESERVE_LOGS_BASE,
-		(uintptr_t)__preserved_logs_size, __preserved_logs_start);
+				  (uintptr_t)__preserved_logs_size,
+				  __preserved_logs_start);
 	BRAM_EC_LOG_STATUS = EC_LOG_SAVED_IN_FLASH;
 #endif
 
@@ -384,7 +389,7 @@ static uint32_t system_get_chip_id(void)
 {
 #ifdef IT83XX_CHIP_ID_3BYTES
 	return (IT83XX_GCTRL_CHIPID1 << 16) | (IT83XX_GCTRL_CHIPID2 << 8) |
-		IT83XX_GCTRL_CHIPID3;
+	       IT83XX_GCTRL_CHIPID3;
 #else
 	return (IT83XX_GCTRL_CHIPID1 << 8) | IT83XX_GCTRL_CHIPID2;
 #endif
@@ -410,7 +415,7 @@ const char *system_get_chip_vendor(void)
 
 const char *system_get_chip_name(void)
 {
-	static char buf[8] = {'i', 't'};
+	static char buf[8] = { 'i', 't' };
 	int num = (IS_ENABLED(IT83XX_CHIP_ID_3BYTES) ? 4 : 3);
 	uint32_t chip_id = system_get_chip_id();
 
diff --git a/chip/it83xx/uart.c b/chip/it83xx/uart.c
index d0b645e68c..6635c5966e 100644
--- a/chip/it83xx/uart.c
+++ b/chip/it83xx/uart.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,7 +17,7 @@
 #include "util.h"
 
 /* Traces on UART1 */
-#define UART_PORT      0
+#define UART_PORT 0
 #define UART_PORT_HOST 1
 
 static int init_done;
diff --git a/chip/it83xx/watchdog.c b/chip/it83xx/watchdog.c
index f0e200c4ac..b1e45127f0 100644
--- a/chip/it83xx/watchdog.c
+++ b/chip/it83xx/watchdog.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,9 +24,9 @@ static int wdt_warning_fired;
  */
 
 /* Magic value to tickle the watchdog register. */
-#define ITE83XX_WATCHDOG_MAGIC_WORD  0x5C
+#define ITE83XX_WATCHDOG_MAGIC_WORD 0x5C
 /* Start to print warning message. */
-#define ITE83XX_WATCHDOG_WARNING_MS  CONFIG_AUX_TIMER_PERIOD_MS
+#define ITE83XX_WATCHDOG_WARNING_MS CONFIG_AUX_TIMER_PERIOD_MS
 /* The interval to print warning message at critical period. */
 #define ITE83XX_WATCHDOG_CRITICAL_MS 30
 
@@ -39,7 +39,7 @@ static void watchdog_set_warning_timer(int32_t ms, int init)
 void watchdog_warning_irq(void)
 {
 #ifdef CONFIG_SOFTWARE_PANIC
-	struct panic_data * const pdata_ptr = get_panic_data_write();
+	struct panic_data *const pdata_ptr = get_panic_data_write();
 
 #if defined(CHIP_CORE_NDS32)
 	pdata_ptr->nds_n8.ipc = get_ipc();
@@ -64,10 +64,10 @@ void watchdog_warning_irq(void)
 	 * LP = PC+4 after a jump and link instruction (jal).
 	 */
 	panic_printf("Pre-WDT warning! IPC:%08x LP:%08x TASK_ID:%d\n",
-		get_ipc(), ilp, task_get_current());
+		     get_ipc(), ilp, task_get_current());
 #elif defined(CHIP_CORE_RISCV)
 	panic_printf("Pre-WDT warning! MEPC:%08x RA:%08x TASK_ID:%d\n",
-		get_mepc(), ira, task_get_current());
+		     get_mepc(), ira, task_get_current());
 #endif
 
 	if (!wdt_warning_fired++)
@@ -93,6 +93,7 @@ void watchdog_reload(void)
 	}
 }
 DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_SYSJUMP, watchdog_reload, HOOK_PRIO_LAST);
 
 int watchdog_init(void)
 {
diff --git a/chip/max32660/build.mk b/chip/max32660/build.mk
index ea1ea6c330..e0db8bc646 100644
--- a/chip/max32660/build.mk
+++ b/chip/max32660/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/chip/max32660/clock_chip.c b/chip/max32660/clock_chip.c
index 901c5d559c..93a5f862d8 100644
--- a/chip/max32660/clock_chip.c
+++ b/chip/max32660/clock_chip.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,9 +26,9 @@
 typedef enum {
 	SYS_CLOCK_NANORING = MXC_V_GCR_CLKCN_CLKSEL_NANORING, /**< 8KHz nanoring
 								 on MAX32660 */
-	SYS_CLOCK_HFXIN =
-		MXC_V_GCR_CLKCN_CLKSEL_HFXIN, /**< 32KHz on MAX32660 */
-	SYS_CLOCK_HFXIN_DIGITAL = 0x9,	/**< External Clock Input*/
+	SYS_CLOCK_HFXIN = MXC_V_GCR_CLKCN_CLKSEL_HFXIN, /**< 32KHz on MAX32660
+							 */
+	SYS_CLOCK_HFXIN_DIGITAL = 0x9, /**< External Clock Input*/
 	SYS_CLOCK_HIRC = MXC_V_GCR_CLKCN_CLKSEL_HIRC, /**< High Frequency
 							 Internal Oscillator */
 } sys_system_clock_t;
diff --git a/chip/max32660/config_chip.h b/chip/max32660/config_chip.h
index c97c246bb7..9fa939a918 100644
--- a/chip/max32660/config_chip.h
+++ b/chip/max32660/config_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -50,7 +50,7 @@
 #define TASK_STACK_SIZE 512
 
 #define CONFIG_PROGRAM_MEMORY_BASE 0x00000000
-#define CONFIG_FLASH_BANK_SIZE 0x00002000  /* protect bank size */
+#define CONFIG_FLASH_BANK_SIZE 0x00002000 /* protect bank size */
 #define CONFIG_FLASH_ERASE_SIZE 0x00002000 /* erase bank size */
 #define CONFIG_FLASH_WRITE_SIZE 0x00000004 /* minimum write size */
 
diff --git a/chip/max32660/flash_chip.c b/chip/max32660/flash_chip.c
index 747d7dcc58..eb702799b0 100644
--- a/chip/max32660/flash_chip.c
+++ b/chip/max32660/flash_chip.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,7 +25,7 @@
 #define MXC_FLASH_PAGE_MASK ~(MXC_FLASH_PAGE_SIZE - 1)
 
 /// Calculate the address of a page in flash from the page number
-#define MXC_FLASH_PAGE_ADDR(page)                                              \
+#define MXC_FLASH_PAGE_ADDR(page) \
 	(MXC_FLASH_MEM_BASE + ((unsigned long)page * MXC_FLASH_PAGE_SIZE))
 
 void flash_operation(void)
@@ -123,7 +123,6 @@ int crec_flash_physical_write(int offset, int size, const char *data)
 
 	// Align the address and read/write if we have to
 	if (offset & 0x3) {
-
 		// Figure out how many bytes we have to write to round up the
 		// address
 		bytes_written = 4 - (offset & 0x3);
@@ -163,7 +162,6 @@ int crec_flash_physical_write(int offset, int size, const char *data)
 	}
 
 	if (size >= 16) {
-
 		// write in 128-bit bursts while we can
 		MXC_FLC->cn &= ~MXC_F_FLC_CN_WDTH;
 
@@ -308,7 +306,7 @@ int crec_flash_pre_init(void)
  * NOTE: This is a DESTRUCTIVE test for the range of flash pages tested
  *       make sure that PAGE_START is beyond your flash code.
  */
-static int command_flash_test1(int argc, char **argv)
+static int command_flash_test1(int argc, const char **argv)
 {
 	int i;
 	uint8_t *ptr;
@@ -330,8 +328,8 @@ static int command_flash_test1(int argc, char **argv)
 		/*
 		 * erase page
 		 */
-		error_status = crec_flash_physical_erase(flash_address,
-						    CONFIG_FLASH_ERASE_SIZE);
+		error_status = crec_flash_physical_erase(
+			flash_address, CONFIG_FLASH_ERASE_SIZE);
 		if (error_status != EC_SUCCESS) {
 			CPRINTS("Error with crec_flash_physical_erase\n");
 			return EC_ERROR_UNKNOWN;
@@ -389,8 +387,8 @@ static int command_flash_test1(int argc, char **argv)
 	 */
 	for (page = PAGE_START; page <= PAGE_END; page++) {
 		flash_address = page * CONFIG_FLASH_ERASE_SIZE;
-		error_status = crec_flash_physical_erase(flash_address,
-						    CONFIG_FLASH_ERASE_SIZE);
+		error_status = crec_flash_physical_erase(
+			flash_address, CONFIG_FLASH_ERASE_SIZE);
 		if (error_status != EC_SUCCESS) {
 			CPRINTS("Error with crec_flash_physical_erase\n");
 			return EC_ERROR_UNKNOWN;
diff --git a/chip/max32660/flc_regs.h b/chip/max32660/flc_regs.h
index a484763c0b..fb7691e759 100644
--- a/chip/max32660/flc_regs.h
+++ b/chip/max32660/flc_regs.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -43,14 +43,14 @@ extern "C" {
  * Structure type to access the FLC Registers.
  */
 typedef struct {
-	__IO uint32_t addr;   /**< <tt>\b 0x00:<\tt> FLC ADDR Register */
+	__IO uint32_t addr; /**< <tt>\b 0x00:<\tt> FLC ADDR Register */
 	__IO uint32_t clkdiv; /**< <tt>\b 0x04:<\tt> FLC CLKDIV Register */
-	__IO uint32_t cn;     /**< <tt>\b 0x08:<\tt> FLC CN Register */
+	__IO uint32_t cn; /**< <tt>\b 0x08:<\tt> FLC CN Register */
 	__R uint32_t rsv_0xc_0x23[6];
 	__IO uint32_t intr; /**< <tt>\b 0x024:<\tt> FLC INTR Register */
 	__R uint32_t rsv_0x28_0x2f[2];
 	__IO uint32_t data[4]; /**< <tt>\b 0x30:<\tt> FLC DATA Register */
-	__O uint32_t acntl;    /**< <tt>\b 0x40:<\tt> FLC ACNTL Register */
+	__O uint32_t acntl; /**< <tt>\b 0x40:<\tt> FLC ACNTL Register */
 } mxc_flc_regs_t;
 
 /* Register offsets for module FLC */
@@ -58,32 +58,32 @@ typedef struct {
  * FLC Peripheral Register Offsets from the FLC Base Peripheral
  * Address.
  */
-#define MXC_R_FLC_ADDR                                                         \
-	((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: <tt>       \
+#define MXC_R_FLC_ADDR                                                   \
+	((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: <tt> \
 				    0x0x000 */
-#define MXC_R_FLC_CLKDIV                                                       \
-	((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: <tt>       \
+#define MXC_R_FLC_CLKDIV                                                 \
+	((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: <tt> \
 				    0x0x004 */
-#define MXC_R_FLC_CN                                                           \
-	((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: <tt>       \
+#define MXC_R_FLC_CN                                                     \
+	((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: <tt> \
 				    0x0x008 */
-#define MXC_R_FLC_INTR                                                         \
-	((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: <tt>       \
+#define MXC_R_FLC_INTR                                                   \
+	((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: <tt> \
 				    0x0x024 */
-#define MXC_R_FLC_DATA                                                         \
-	((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: <tt>       \
+#define MXC_R_FLC_DATA                                                   \
+	((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: <tt> \
 				    0x0x030 */
-#define MXC_R_FLC_ACNTL                                                        \
-	((uint32_t)0x00000040UL) /**< Offset from FLC Base Address: <tt>       \
+#define MXC_R_FLC_ACNTL                                                  \
+	((uint32_t)0x00000040UL) /**< Offset from FLC Base Address: <tt> \
 				    0x0x040 */
 
 /**
  * Flash Write Address.
  */
 #define MXC_F_FLC_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */
-#define MXC_F_FLC_ADDR_ADDR                                                    \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_FLC_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */
+#define MXC_F_FLC_ADDR_ADDR                                                  \
+	((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ADDR_ADDR_POS)) /**< ADDR_ADDR \
+								 Mask */
 
 /**
  * Flash Clock Divide. The clock (PLL0) is divided by this value to
@@ -91,177 +91,200 @@ typedef struct {
  */
 #define MXC_F_FLC_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */
 #define MXC_F_FLC_CLKDIV_CLKDIV                                                \
-	((uint32_t)(                                                           \
-		0xFFUL                                                         \
-		<< MXC_F_FLC_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */
+	((uint32_t)(0xFFUL << MXC_F_FLC_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV \
+							       Mask */
 
 /**
  * Flash Control Register.
  */
 #define MXC_F_FLC_CN_WR_POS 0 /**< CN_WR Position */
-#define MXC_F_FLC_CN_WR                                                        \
+#define MXC_F_FLC_CN_WR \
 	((uint32_t)(0x1UL << MXC_F_FLC_CN_WR_POS)) /**< CN_WR Mask */
-#define MXC_V_FLC_CN_WR_COMPLETE                                               \
-	((uint32_t)0x0UL) /**< CN_WR_COMPLETE Value                            \
+#define MXC_V_FLC_CN_WR_COMPLETE                    \
+	((uint32_t)0x0UL) /**< CN_WR_COMPLETE Value \
 			   */
-#define MXC_S_FLC_CN_WR_COMPLETE                                               \
-	(MXC_V_FLC_CN_WR_COMPLETE                                              \
-	 << MXC_F_FLC_CN_WR_POS)		/**< CN_WR_COMPLETE Setting */
+#define MXC_S_FLC_CN_WR_COMPLETE                                              \
+	(MXC_V_FLC_CN_WR_COMPLETE << MXC_F_FLC_CN_WR_POS) /**< CN_WR_COMPLETE \
+							     Setting */
 #define MXC_V_FLC_CN_WR_START ((uint32_t)0x1UL) /**< CN_WR_START Value */
-#define MXC_S_FLC_CN_WR_START                                                  \
-	(MXC_V_FLC_CN_WR_START                                                 \
-	 << MXC_F_FLC_CN_WR_POS) /**< CN_WR_START Setting */
+#define MXC_S_FLC_CN_WR_START                                           \
+	(MXC_V_FLC_CN_WR_START << MXC_F_FLC_CN_WR_POS) /**< CN_WR_START \
+							  Setting */
 
 #define MXC_F_FLC_CN_ME_POS 1 /**< CN_ME Position */
-#define MXC_F_FLC_CN_ME                                                        \
+#define MXC_F_FLC_CN_ME \
 	((uint32_t)(0x1UL << MXC_F_FLC_CN_ME_POS)) /**< CN_ME Mask */
 
 #define MXC_F_FLC_CN_PGE_POS 2 /**< CN_PGE Position */
-#define MXC_F_FLC_CN_PGE                                                       \
+#define MXC_F_FLC_CN_PGE \
 	((uint32_t)(0x1UL << MXC_F_FLC_CN_PGE_POS)) /**< CN_PGE Mask */
 
 #define MXC_F_FLC_CN_WDTH_POS 4 /**< CN_WDTH Position */
-#define MXC_F_FLC_CN_WDTH                                                      \
+#define MXC_F_FLC_CN_WDTH \
 	((uint32_t)(0x1UL << MXC_F_FLC_CN_WDTH_POS)) /**< CN_WDTH Mask */
-#define MXC_V_FLC_CN_WDTH_SIZE128                                              \
+#define MXC_V_FLC_CN_WDTH_SIZE128 \
 	((uint32_t)0x0UL) /**< CN_WDTH_SIZE128 Value */
-#define MXC_S_FLC_CN_WDTH_SIZE128                                              \
-	(MXC_V_FLC_CN_WDTH_SIZE128                                             \
-	 << MXC_F_FLC_CN_WDTH_POS) /**< CN_WDTH_SIZE128 Setting */
-#define MXC_V_FLC_CN_WDTH_SIZE32                                               \
-	((uint32_t)0x1UL) /**< CN_WDTH_SIZE32 Value                            \
+#define MXC_S_FLC_CN_WDTH_SIZE128                     \
+	(MXC_V_FLC_CN_WDTH_SIZE128                    \
+	 << MXC_F_FLC_CN_WDTH_POS) /**<               \
+				      CN_WDTH_SIZE128 \
+				      Setting */
+#define MXC_V_FLC_CN_WDTH_SIZE32                    \
+	((uint32_t)0x1UL) /**< CN_WDTH_SIZE32 Value \
 			   */
-#define MXC_S_FLC_CN_WDTH_SIZE32                                               \
-	(MXC_V_FLC_CN_WDTH_SIZE32                                              \
-	 << MXC_F_FLC_CN_WDTH_POS) /**< CN_WDTH_SIZE32 Setting */
+#define MXC_S_FLC_CN_WDTH_SIZE32                                              \
+	(MXC_V_FLC_CN_WDTH_SIZE32 << MXC_F_FLC_CN_WDTH_POS) /**<              \
+							       CN_WDTH_SIZE32 \
+							       Setting */
 
 #define MXC_F_FLC_CN_ERASE_CODE_POS 8 /**< CN_ERASE_CODE Position */
 #define MXC_F_FLC_CN_ERASE_CODE                                                \
-	((uint32_t)(                                                           \
-		0xFFUL                                                         \
-		<< MXC_F_FLC_CN_ERASE_CODE_POS)) /**< CN_ERASE_CODE Mask */
-#define MXC_V_FLC_CN_ERASE_CODE_NOP                                            \
+	((uint32_t)(0xFFUL << MXC_F_FLC_CN_ERASE_CODE_POS)) /**< CN_ERASE_CODE \
+							       Mask */
+#define MXC_V_FLC_CN_ERASE_CODE_NOP \
 	((uint32_t)0x0UL) /**< CN_ERASE_CODE_NOP Value */
-#define MXC_S_FLC_CN_ERASE_CODE_NOP                                            \
-	(MXC_V_FLC_CN_ERASE_CODE_NOP                                           \
-	 << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_NOP Setting */
-#define MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE                                      \
+#define MXC_S_FLC_CN_ERASE_CODE_NOP                           \
+	(MXC_V_FLC_CN_ERASE_CODE_NOP                          \
+	 << MXC_F_FLC_CN_ERASE_CODE_POS) /**<                 \
+					    CN_ERASE_CODE_NOP \
+					    Setting           \
+					  */
+#define MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE \
 	((uint32_t)0x55UL) /**< CN_ERASE_CODE_ERASEPAGE Value */
-#define MXC_S_FLC_CN_ERASE_CODE_ERASEPAGE                                      \
-	(MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE                                     \
-	 << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_ERASEPAGE Setting  \
+#define MXC_S_FLC_CN_ERASE_CODE_ERASEPAGE                                     \
+	(MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE                                    \
+	 << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_ERASEPAGE Setting \
 					  */
-#define MXC_V_FLC_CN_ERASE_CODE_ERASEALL                                       \
+#define MXC_V_FLC_CN_ERASE_CODE_ERASEALL \
 	((uint32_t)0xAAUL) /**< CN_ERASE_CODE_ERASEALL Value */
-#define MXC_S_FLC_CN_ERASE_CODE_ERASEALL                                       \
-	(MXC_V_FLC_CN_ERASE_CODE_ERASEALL                                      \
-	 << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_ERASEALL Setting   \
+#define MXC_S_FLC_CN_ERASE_CODE_ERASEALL                                     \
+	(MXC_V_FLC_CN_ERASE_CODE_ERASEALL                                    \
+	 << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_ERASEALL Setting \
 					  */
 
 #define MXC_F_FLC_CN_PEND_POS 24 /**< CN_PEND Position */
-#define MXC_F_FLC_CN_PEND                                                      \
+#define MXC_F_FLC_CN_PEND \
 	((uint32_t)(0x1UL << MXC_F_FLC_CN_PEND_POS)) /**< CN_PEND Mask */
-#define MXC_V_FLC_CN_PEND_IDLE ((uint32_t)0x0UL)     /**< CN_PEND_IDLE Value */
-#define MXC_S_FLC_CN_PEND_IDLE                                                 \
-	(MXC_V_FLC_CN_PEND_IDLE                                                \
-	 << MXC_F_FLC_CN_PEND_POS)		 /**< CN_PEND_IDLE Setting */
+#define MXC_V_FLC_CN_PEND_IDLE ((uint32_t)0x0UL) /**< CN_PEND_IDLE Value */
+#define MXC_S_FLC_CN_PEND_IDLE                                              \
+	(MXC_V_FLC_CN_PEND_IDLE << MXC_F_FLC_CN_PEND_POS) /**< CN_PEND_IDLE \
+							     Setting */
 #define MXC_V_FLC_CN_PEND_BUSY ((uint32_t)0x1UL) /**< CN_PEND_BUSY Value */
-#define MXC_S_FLC_CN_PEND_BUSY                                                 \
-	(MXC_V_FLC_CN_PEND_BUSY                                                \
-	 << MXC_F_FLC_CN_PEND_POS) /**< CN_PEND_BUSY Setting */
+#define MXC_S_FLC_CN_PEND_BUSY                                              \
+	(MXC_V_FLC_CN_PEND_BUSY << MXC_F_FLC_CN_PEND_POS) /**< CN_PEND_BUSY \
+							     Setting */
 
 #define MXC_F_FLC_CN_LVE_POS 25 /**< CN_LVE Position */
-#define MXC_F_FLC_CN_LVE                                                       \
+#define MXC_F_FLC_CN_LVE \
 	((uint32_t)(0x1UL << MXC_F_FLC_CN_LVE_POS)) /**< CN_LVE Mask */
-#define MXC_V_FLC_CN_LVE_DIS ((uint32_t)0x0UL)      /**< CN_LVE_DIS Value */
+#define MXC_V_FLC_CN_LVE_DIS ((uint32_t)0x0UL) /**< CN_LVE_DIS Value */
 #define MXC_S_FLC_CN_LVE_DIS                                                   \
-	(MXC_V_FLC_CN_LVE_DIS                                                  \
-	 << MXC_F_FLC_CN_LVE_POS)	     /**< CN_LVE_DIS Setting */
+	(MXC_V_FLC_CN_LVE_DIS << MXC_F_FLC_CN_LVE_POS) /**< CN_LVE_DIS Setting \
+							*/
 #define MXC_V_FLC_CN_LVE_EN ((uint32_t)0x1UL) /**< CN_LVE_EN Value */
-#define MXC_S_FLC_CN_LVE_EN                                                    \
-	(MXC_V_FLC_CN_LVE_EN << MXC_F_FLC_CN_LVE_POS) /**< CN_LVE_EN Setting   \
+#define MXC_S_FLC_CN_LVE_EN                                                  \
+	(MXC_V_FLC_CN_LVE_EN << MXC_F_FLC_CN_LVE_POS) /**< CN_LVE_EN Setting \
 						       */
 
 #define MXC_F_FLC_CN_BRST_POS 27 /**< CN_BRST Position */
-#define MXC_F_FLC_CN_BRST                                                      \
+#define MXC_F_FLC_CN_BRST \
 	((uint32_t)(0x1UL << MXC_F_FLC_CN_BRST_POS)) /**< CN_BRST Mask */
-#define MXC_V_FLC_CN_BRST_DISABLE                                              \
+#define MXC_V_FLC_CN_BRST_DISABLE \
 	((uint32_t)0x0UL) /**< CN_BRST_DISABLE Value */
-#define MXC_S_FLC_CN_BRST_DISABLE                                              \
-	(MXC_V_FLC_CN_BRST_DISABLE                                             \
-	 << MXC_F_FLC_CN_BRST_POS) /**< CN_BRST_DISABLE Setting */
-#define MXC_V_FLC_CN_BRST_ENABLE                                               \
-	((uint32_t)0x1UL) /**< CN_BRST_ENABLE Value                            \
+#define MXC_S_FLC_CN_BRST_DISABLE                     \
+	(MXC_V_FLC_CN_BRST_DISABLE                    \
+	 << MXC_F_FLC_CN_BRST_POS) /**<               \
+				      CN_BRST_DISABLE \
+				      Setting */
+#define MXC_V_FLC_CN_BRST_ENABLE                    \
+	((uint32_t)0x1UL) /**< CN_BRST_ENABLE Value \
 			   */
-#define MXC_S_FLC_CN_BRST_ENABLE                                               \
-	(MXC_V_FLC_CN_BRST_ENABLE                                              \
-	 << MXC_F_FLC_CN_BRST_POS) /**< CN_BRST_ENABLE Setting */
+#define MXC_S_FLC_CN_BRST_ENABLE                                              \
+	(MXC_V_FLC_CN_BRST_ENABLE << MXC_F_FLC_CN_BRST_POS) /**<              \
+							       CN_BRST_ENABLE \
+							       Setting */
 
 #define MXC_F_FLC_CN_UNLOCK_POS 28 /**< CN_UNLOCK Position */
-#define MXC_F_FLC_CN_UNLOCK                                                    \
+#define MXC_F_FLC_CN_UNLOCK \
 	((uint32_t)(0xFUL << MXC_F_FLC_CN_UNLOCK_POS)) /**< CN_UNLOCK Mask */
-#define MXC_V_FLC_CN_UNLOCK_UNLOCKED                                           \
+#define MXC_V_FLC_CN_UNLOCK_UNLOCKED \
 	((uint32_t)0x2UL) /**< CN_UNLOCK_UNLOCKED Value */
-#define MXC_S_FLC_CN_UNLOCK_UNLOCKED                                           \
-	(MXC_V_FLC_CN_UNLOCK_UNLOCKED                                          \
-	 << MXC_F_FLC_CN_UNLOCK_POS) /**< CN_UNLOCK_UNLOCKED Setting */
+#define MXC_S_FLC_CN_UNLOCK_UNLOCKED                       \
+	(MXC_V_FLC_CN_UNLOCK_UNLOCKED                      \
+	 << MXC_F_FLC_CN_UNLOCK_POS) /**<                  \
+					CN_UNLOCK_UNLOCKED \
+					Setting            \
+				      */
 
 /**
  * Flash Interrupt Register.
  */
 #define MXC_F_FLC_INTR_DONE_POS 0 /**< INTR_DONE Position */
-#define MXC_F_FLC_INTR_DONE                                                    \
+#define MXC_F_FLC_INTR_DONE \
 	((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_POS)) /**< INTR_DONE Mask */
-#define MXC_V_FLC_INTR_DONE_INACTIVE                                           \
+#define MXC_V_FLC_INTR_DONE_INACTIVE \
 	((uint32_t)0x0UL) /**< INTR_DONE_INACTIVE Value */
-#define MXC_S_FLC_INTR_DONE_INACTIVE                                           \
-	(MXC_V_FLC_INTR_DONE_INACTIVE                                          \
-	 << MXC_F_FLC_INTR_DONE_POS) /**< INTR_DONE_INACTIVE Setting */
-#define MXC_V_FLC_INTR_DONE_PENDING                                            \
+#define MXC_S_FLC_INTR_DONE_INACTIVE                       \
+	(MXC_V_FLC_INTR_DONE_INACTIVE                      \
+	 << MXC_F_FLC_INTR_DONE_POS) /**<                  \
+					INTR_DONE_INACTIVE \
+					Setting            \
+				      */
+#define MXC_V_FLC_INTR_DONE_PENDING \
 	((uint32_t)0x1UL) /**< INTR_DONE_PENDING Value */
-#define MXC_S_FLC_INTR_DONE_PENDING                                            \
-	(MXC_V_FLC_INTR_DONE_PENDING                                           \
-	 << MXC_F_FLC_INTR_DONE_POS) /**< INTR_DONE_PENDING Setting */
+#define MXC_S_FLC_INTR_DONE_PENDING                       \
+	(MXC_V_FLC_INTR_DONE_PENDING                      \
+	 << MXC_F_FLC_INTR_DONE_POS) /**<                 \
+					INTR_DONE_PENDING \
+					Setting */
 
 #define MXC_F_FLC_INTR_AF_POS 1 /**< INTR_AF Position */
-#define MXC_F_FLC_INTR_AF                                                      \
+#define MXC_F_FLC_INTR_AF \
 	((uint32_t)(0x1UL << MXC_F_FLC_INTR_AF_POS)) /**< INTR_AF Mask */
-#define MXC_V_FLC_INTR_AF_NOERROR                                              \
+#define MXC_V_FLC_INTR_AF_NOERROR \
 	((uint32_t)0x0UL) /**< INTR_AF_NOERROR Value */
-#define MXC_S_FLC_INTR_AF_NOERROR                                              \
-	(MXC_V_FLC_INTR_AF_NOERROR                                             \
-	 << MXC_F_FLC_INTR_AF_POS) /**< INTR_AF_NOERROR Setting */
+#define MXC_S_FLC_INTR_AF_NOERROR                     \
+	(MXC_V_FLC_INTR_AF_NOERROR                    \
+	 << MXC_F_FLC_INTR_AF_POS) /**<               \
+				      INTR_AF_NOERROR \
+				      Setting */
 #define MXC_V_FLC_INTR_AF_ERROR ((uint32_t)0x1UL) /**< INTR_AF_ERROR Value */
-#define MXC_S_FLC_INTR_AF_ERROR                                                \
-	(MXC_V_FLC_INTR_AF_ERROR                                               \
-	 << MXC_F_FLC_INTR_AF_POS) /**< INTR_AF_ERROR Setting */
+#define MXC_S_FLC_INTR_AF_ERROR                                               \
+	(MXC_V_FLC_INTR_AF_ERROR << MXC_F_FLC_INTR_AF_POS) /**< INTR_AF_ERROR \
+							      Setting */
 
 #define MXC_F_FLC_INTR_DONEIE_POS 8 /**< INTR_DONEIE Position */
 #define MXC_F_FLC_INTR_DONEIE                                                  \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_FLC_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask */
-#define MXC_V_FLC_INTR_DONEIE_DISABLE                                          \
+	((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask \
+							  */
+#define MXC_V_FLC_INTR_DONEIE_DISABLE \
 	((uint32_t)0x0UL) /**< INTR_DONEIE_DISABLE Value */
-#define MXC_S_FLC_INTR_DONEIE_DISABLE                                          \
-	(MXC_V_FLC_INTR_DONEIE_DISABLE                                         \
-	 << MXC_F_FLC_INTR_DONEIE_POS) /**< INTR_DONEIE_DISABLE Setting */
-#define MXC_V_FLC_INTR_DONEIE_ENABLE                                           \
+#define MXC_S_FLC_INTR_DONEIE_DISABLE                         \
+	(MXC_V_FLC_INTR_DONEIE_DISABLE                        \
+	 << MXC_F_FLC_INTR_DONEIE_POS) /**<                   \
+					  INTR_DONEIE_DISABLE \
+					  Setting             \
+					*/
+#define MXC_V_FLC_INTR_DONEIE_ENABLE \
 	((uint32_t)0x1UL) /**< INTR_DONEIE_ENABLE Value */
-#define MXC_S_FLC_INTR_DONEIE_ENABLE                                           \
-	(MXC_V_FLC_INTR_DONEIE_ENABLE                                          \
-	 << MXC_F_FLC_INTR_DONEIE_POS) /**< INTR_DONEIE_ENABLE Setting */
+#define MXC_S_FLC_INTR_DONEIE_ENABLE                         \
+	(MXC_V_FLC_INTR_DONEIE_ENABLE                        \
+	 << MXC_F_FLC_INTR_DONEIE_POS) /**<                  \
+					  INTR_DONEIE_ENABLE \
+					  Setting            \
+					*/
 
 #define MXC_F_FLC_INTR_AFIE_POS 9 /**< INTR_AFIE Position */
-#define MXC_F_FLC_INTR_AFIE                                                    \
+#define MXC_F_FLC_INTR_AFIE \
 	((uint32_t)(0x1UL << MXC_F_FLC_INTR_AFIE_POS)) /**< INTR_AFIE Mask */
 
 /**
  * Flash Write Data.
  */
 #define MXC_F_FLC_DATA_DATA_POS 0 /**< DATA_DATA Position */
-#define MXC_F_FLC_DATA_DATA                                                    \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_FLC_DATA_DATA_POS)) /**< DATA_DATA Mask */
+#define MXC_F_FLC_DATA_DATA                                                  \
+	((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_DATA_DATA_POS)) /**< DATA_DATA \
+								 Mask */
 
 /**
  * Access Control Register. Writing the ACNTL register with the
@@ -273,8 +296,9 @@ typedef struct {
  */
 #define MXC_F_FLC_ACNTL_ACNTL_POS 0 /**< ACNTL_ACNTL Position */
 #define MXC_F_FLC_ACNTL_ACNTL                                                  \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_FLC_ACNTL_ACNTL_POS)) /**< ACNTL_ACNTL Mask */
+	((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ACNTL_ACNTL_POS)) /**<           \
+								   ACNTL_ACNTL \
+								   Mask */
 
 #ifdef __cplusplus
 }
diff --git a/chip/max32660/gcr_regs.h b/chip/max32660/gcr_regs.h
index c9de13812c..bed6cf4550 100644
--- a/chip/max32660/gcr_regs.h
+++ b/chip/max32660/gcr_regs.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -39,118 +39,123 @@
  * Structure type to access the GCR Registers.
  */
 typedef struct {
-	__IO uint32_t scon;  /**< <tt>\b 0x00:<\tt> GCR SCON Register */
+	__IO uint32_t scon; /**< <tt>\b 0x00:<\tt> GCR SCON Register */
 	__IO uint32_t rstr0; /**< <tt>\b 0x04:<\tt> GCR RSTR0 Register */
 	__IO uint32_t clkcn; /**< <tt>\b 0x08:<\tt> GCR CLKCN Register */
-	__IO uint32_t pm;    /**< <tt>\b 0x0C:<\tt> GCR PM Register */
+	__IO uint32_t pm; /**< <tt>\b 0x0C:<\tt> GCR PM Register */
 	__R uint32_t rsv_0x10_0x17[2];
 	__IO uint32_t pckdiv; /**< <tt>\b 0x18:<\tt> GCR PCKDIV Register */
 	__R uint32_t rsv_0x1c_0x23[2];
 	__IO uint32_t perckcn0; /**< <tt>\b 0x24:<\tt> GCR PERCKCN0 Register */
-	__IO uint32_t memckcn;  /**< <tt>\b 0x28:<\tt> GCR MEMCKCN Register */
-	__IO uint32_t memzcn;   /**< <tt>\b 0x2C:<\tt> GCR MEMZCN Register */
+	__IO uint32_t memckcn; /**< <tt>\b 0x28:<\tt> GCR MEMCKCN Register */
+	__IO uint32_t memzcn; /**< <tt>\b 0x2C:<\tt> GCR MEMZCN Register */
 	__R uint32_t rsv_0x30;
-	__IO uint32_t scck;     /**< <tt>\b 0x34:<\tt> GCR SCCK Register */
-	__IO uint32_t mpri0;    /**< <tt>\b 0x38:<\tt> GCR MPRI0 Register */
-	__IO uint32_t mpri1;    /**< <tt>\b 0x3C:<\tt> GCR MPRI1 Register */
-	__IO uint32_t sysst;    /**< <tt>\b 0x40:<\tt> GCR SYSST Register */
-	__IO uint32_t rstr1;    /**< <tt>\b 0x44:<\tt> GCR RSTR1 Register */
+	__IO uint32_t scck; /**< <tt>\b 0x34:<\tt> GCR SCCK Register */
+	__IO uint32_t mpri0; /**< <tt>\b 0x38:<\tt> GCR MPRI0 Register */
+	__IO uint32_t mpri1; /**< <tt>\b 0x3C:<\tt> GCR MPRI1 Register */
+	__IO uint32_t sysst; /**< <tt>\b 0x40:<\tt> GCR SYSST Register */
+	__IO uint32_t rstr1; /**< <tt>\b 0x44:<\tt> GCR RSTR1 Register */
 	__IO uint32_t perckcn1; /**< <tt>\b 0x48:<\tt> GCR PERCKCN1 Register */
-	__IO uint32_t evten;    /**< <tt>\b 0x4C:<\tt> GCR EVTEN Register */
-	__I uint32_t revision;  /**< <tt>\b 0x50:<\tt> GCR REVISION Register */
-	__IO uint32_t syssie;   /**< <tt>\b 0x54:<\tt> GCR SYSSIE Register */
+	__IO uint32_t evten; /**< <tt>\b 0x4C:<\tt> GCR EVTEN Register */
+	__I uint32_t revision; /**< <tt>\b 0x50:<\tt> GCR REVISION Register */
+	__IO uint32_t syssie; /**< <tt>\b 0x54:<\tt> GCR SYSSIE Register */
 } mxc_gcr_regs_t;
 
 /**
  * GCR Peripheral Register Offsets from the GCR Base Peripheral
  * Address.
  */
-#define MXC_R_GCR_SCON                                                         \
-	((uint32_t)0x00000000UL) /**< Offset from GCR Base Address: <tt>       \
+#define MXC_R_GCR_SCON                                                   \
+	((uint32_t)0x00000000UL) /**< Offset from GCR Base Address: <tt> \
 				    0x0x000 */
-#define MXC_R_GCR_RSTR0                                                        \
-	((uint32_t)0x00000004UL) /**< Offset from GCR Base Address: <tt>       \
+#define MXC_R_GCR_RSTR0                                                  \
+	((uint32_t)0x00000004UL) /**< Offset from GCR Base Address: <tt> \
 				    0x0x004 */
-#define MXC_R_GCR_CLKCN                                                        \
-	((uint32_t)0x00000008UL) /**< Offset from GCR Base Address: <tt>       \
+#define MXC_R_GCR_CLKCN                                                  \
+	((uint32_t)0x00000008UL) /**< Offset from GCR Base Address: <tt> \
 				    0x0x008 */
-#define MXC_R_GCR_PM                                                           \
-	((uint32_t)0x0000000CUL) /**< Offset from GCR Base Address: <tt>       \
+#define MXC_R_GCR_PM                                                     \
+	((uint32_t)0x0000000CUL) /**< Offset from GCR Base Address: <tt> \
 				    0x0x00C */
-#define MXC_R_GCR_PCKDIV                                                       \
-	((uint32_t)0x00000018UL) /**< Offset from GCR Base Address: <tt>       \
+#define MXC_R_GCR_PCKDIV                                                 \
+	((uint32_t)0x00000018UL) /**< Offset from GCR Base Address: <tt> \
 				    0x0x018 */
-#define MXC_R_GCR_PERCKCN0                                                     \
-	((uint32_t)0x00000024UL) /**< Offset from GCR Base Address: <tt>       \
+#define MXC_R_GCR_PERCKCN0                                               \
+	((uint32_t)0x00000024UL) /**< Offset from GCR Base Address: <tt> \
 				    0x0x024 */
-#define MXC_R_GCR_MEMCKCN                                                      \
-	((uint32_t)0x00000028UL) /**< Offset from GCR Base Address: <tt>       \
+#define MXC_R_GCR_MEMCKCN                                                \
+	((uint32_t)0x00000028UL) /**< Offset from GCR Base Address: <tt> \
 				    0x0x028 */
-#define MXC_R_GCR_MEMZCN                                                       \
-	((uint32_t)0x0000002CUL) /**< Offset from GCR Base Address: <tt>       \
+#define MXC_R_GCR_MEMZCN                                                 \
+	((uint32_t)0x0000002CUL) /**< Offset from GCR Base Address: <tt> \
 				    0x0x02C */
-#define MXC_R_GCR_SCCK                                                         \
-	((uint32_t)0x00000034UL) /**< Offset from GCR Base Address: <tt>       \
+#define MXC_R_GCR_SCCK                                                   \
+	((uint32_t)0x00000034UL) /**< Offset from GCR Base Address: <tt> \
 				    0x0x034 */
-#define MXC_R_GCR_MPRI0                                                        \
-	((uint32_t)0x00000038UL) /**< Offset from GCR Base Address: <tt>       \
+#define MXC_R_GCR_MPRI0                                                  \
+	((uint32_t)0x00000038UL) /**< Offset from GCR Base Address: <tt> \
 				    0x0x038 */
-#define MXC_R_GCR_MPRI1                                                        \
-	((uint32_t)0x0000003CUL) /**< Offset from GCR Base Address: <tt>       \
+#define MXC_R_GCR_MPRI1                                                  \
+	((uint32_t)0x0000003CUL) /**< Offset from GCR Base Address: <tt> \
 				    0x0x03C */
-#define MXC_R_GCR_SYSST                                                        \
-	((uint32_t)0x00000040UL) /**< Offset from GCR Base Address: <tt>       \
+#define MXC_R_GCR_SYSST                                                  \
+	((uint32_t)0x00000040UL) /**< Offset from GCR Base Address: <tt> \
 				    0x0x040 */
-#define MXC_R_GCR_RSTR1                                                        \
-	((uint32_t)0x00000044UL) /**< Offset from GCR Base Address: <tt>       \
+#define MXC_R_GCR_RSTR1                                                  \
+	((uint32_t)0x00000044UL) /**< Offset from GCR Base Address: <tt> \
 				    0x0x044 */
-#define MXC_R_GCR_PERCKCN1                                                     \
-	((uint32_t)0x00000048UL) /**< Offset from GCR Base Address: <tt>       \
+#define MXC_R_GCR_PERCKCN1                                               \
+	((uint32_t)0x00000048UL) /**< Offset from GCR Base Address: <tt> \
 				    0x0x048 */
-#define MXC_R_GCR_EVTEN                                                        \
-	((uint32_t)0x0000004CUL) /**< Offset from GCR Base Address: <tt>       \
+#define MXC_R_GCR_EVTEN                                                  \
+	((uint32_t)0x0000004CUL) /**< Offset from GCR Base Address: <tt> \
 				    0x0x04C */
-#define MXC_R_GCR_REVISION                                                     \
-	((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: <tt>       \
+#define MXC_R_GCR_REVISION                                               \
+	((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: <tt> \
 				    0x0x050 */
-#define MXC_R_GCR_SYSSIE                                                       \
-	((uint32_t)0x00000054UL) /**< Offset from GCR Base Address: <tt>       \
+#define MXC_R_GCR_SYSSIE                                                 \
+	((uint32_t)0x00000054UL) /**< Offset from GCR Base Address: <tt> \
 				    0x0x054 */
 
 /**
  * System Control.
  */
 #define MXC_F_GCR_SCON_SBUSARB_POS 1 /**< SCON_SBUSARB Position */
-#define MXC_F_GCR_SCON_SBUSARB                                                 \
-	((uint32_t)(0x3UL                                                      \
-		    << MXC_F_GCR_SCON_SBUSARB_POS)) /**< SCON_SBUSARB Mask */
-#define MXC_V_GCR_SCON_SBUSARB_FIX                                             \
+#define MXC_F_GCR_SCON_SBUSARB                                              \
+	((uint32_t)(0x3UL << MXC_F_GCR_SCON_SBUSARB_POS)) /**< SCON_SBUSARB \
+							     Mask */
+#define MXC_V_GCR_SCON_SBUSARB_FIX \
 	((uint32_t)0x0UL) /**< SCON_SBUSARB_FIX Value */
-#define MXC_S_GCR_SCON_SBUSARB_FIX                                             \
-	(MXC_V_GCR_SCON_SBUSARB_FIX                                            \
-	 << MXC_F_GCR_SCON_SBUSARB_POS) /**< SCON_SBUSARB_FIX Setting */
-#define MXC_V_GCR_SCON_SBUSARB_ROUND                                           \
+#define MXC_S_GCR_SCON_SBUSARB_FIX                          \
+	(MXC_V_GCR_SCON_SBUSARB_FIX                         \
+	 << MXC_F_GCR_SCON_SBUSARB_POS) /**<                \
+					   SCON_SBUSARB_FIX \
+					   Setting          \
+					 */
+#define MXC_V_GCR_SCON_SBUSARB_ROUND \
 	((uint32_t)0x1UL) /**< SCON_SBUSARB_ROUND Value */
-#define MXC_S_GCR_SCON_SBUSARB_ROUND                                           \
-	(MXC_V_GCR_SCON_SBUSARB_ROUND                                          \
-	 << MXC_F_GCR_SCON_SBUSARB_POS) /**< SCON_SBUSARB_ROUND Setting */
+#define MXC_S_GCR_SCON_SBUSARB_ROUND                          \
+	(MXC_V_GCR_SCON_SBUSARB_ROUND                         \
+	 << MXC_F_GCR_SCON_SBUSARB_POS) /**<                  \
+					   SCON_SBUSARB_ROUND \
+					   Setting            \
+					 */
 
-#define MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS                                     \
+#define MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS \
 	4 /**< SCON_FLASH_PAGE_FLIP Position */
-#define MXC_F_GCR_SCON_FLASH_PAGE_FLIP                                          \
-	((uint32_t)(                                                            \
-		0x1UL                                                           \
-		<< MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS)) /**<                    \
-							   SCON_FLASH_PAGE_FLIP \
-							   Mask */
-#define MXC_V_GCR_SCON_FLASH_PAGE_FLIP_NORMAL                                  \
+#define MXC_F_GCR_SCON_FLASH_PAGE_FLIP                                              \
+	((uint32_t)(0x1UL                                                           \
+		    << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS)) /**<                    \
+							       SCON_FLASH_PAGE_FLIP \
+							       Mask */
+#define MXC_V_GCR_SCON_FLASH_PAGE_FLIP_NORMAL \
 	((uint32_t)0x0UL) /**< SCON_FLASH_PAGE_FLIP_NORMAL Value */
 #define MXC_S_GCR_SCON_FLASH_PAGE_FLIP_NORMAL                                  \
 	(MXC_V_GCR_SCON_FLASH_PAGE_FLIP_NORMAL                                 \
 	 << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS) /**<                           \
 						   SCON_FLASH_PAGE_FLIP_NORMAL \
 						   Setting */
-#define MXC_V_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED                                 \
+#define MXC_V_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED \
 	((uint32_t)0x1UL) /**< SCON_FLASH_PAGE_FLIP_SWAPPED Value */
 #define MXC_S_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED                                  \
 	(MXC_V_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED                                 \
@@ -159,1053 +164,1360 @@ typedef struct {
 						   Setting */
 
 #define MXC_F_GCR_SCON_FPU_DIS_POS 5 /**< SCON_FPU_DIS Position */
-#define MXC_F_GCR_SCON_FPU_DIS                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_SCON_FPU_DIS_POS)) /**< SCON_FPU_DIS Mask */
-#define MXC_V_GCR_SCON_FPU_DIS_ENABLE                                          \
+#define MXC_F_GCR_SCON_FPU_DIS                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_SCON_FPU_DIS_POS)) /**< SCON_FPU_DIS \
+							     Mask */
+#define MXC_V_GCR_SCON_FPU_DIS_ENABLE \
 	((uint32_t)0x0UL) /**< SCON_FPU_DIS_ENABLE Value */
-#define MXC_S_GCR_SCON_FPU_DIS_ENABLE                                          \
-	(MXC_V_GCR_SCON_FPU_DIS_ENABLE                                         \
-	 << MXC_F_GCR_SCON_FPU_DIS_POS) /**< SCON_FPU_DIS_ENABLE Setting */
-#define MXC_V_GCR_SCON_FPU_DIS_DISABLE                                         \
+#define MXC_S_GCR_SCON_FPU_DIS_ENABLE                          \
+	(MXC_V_GCR_SCON_FPU_DIS_ENABLE                         \
+	 << MXC_F_GCR_SCON_FPU_DIS_POS) /**<                   \
+					   SCON_FPU_DIS_ENABLE \
+					   Setting             \
+					 */
+#define MXC_V_GCR_SCON_FPU_DIS_DISABLE \
 	((uint32_t)0x1UL) /**< SCON_FPU_DIS_DISABLE Value */
-#define MXC_S_GCR_SCON_FPU_DIS_DISABLE                                         \
-	(MXC_V_GCR_SCON_FPU_DIS_DISABLE                                        \
-	 << MXC_F_GCR_SCON_FPU_DIS_POS) /**< SCON_FPU_DIS_DISABLE Setting */
+#define MXC_S_GCR_SCON_FPU_DIS_DISABLE                          \
+	(MXC_V_GCR_SCON_FPU_DIS_DISABLE                         \
+	 << MXC_F_GCR_SCON_FPU_DIS_POS) /**<                    \
+					   SCON_FPU_DIS_DISABLE \
+					   Setting              \
+					 */
 
 #define MXC_F_GCR_SCON_CCACHE_FLUSH_POS 6 /**< SCON_CCACHE_FLUSH Position */
-#define MXC_F_GCR_SCON_CCACHE_FLUSH                                            \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_SCON_CCACHE_FLUSH_POS)) /**< SCON_CCACHE_FLUSH    \
-							Mask */
-#define MXC_V_GCR_SCON_CCACHE_FLUSH_NORMAL                                     \
+#define MXC_F_GCR_SCON_CCACHE_FLUSH                                           \
+	((uint32_t)(0x1UL                                                     \
+		    << MXC_F_GCR_SCON_CCACHE_FLUSH_POS)) /**<                 \
+							    SCON_CCACHE_FLUSH \
+							    Mask */
+#define MXC_V_GCR_SCON_CCACHE_FLUSH_NORMAL \
 	((uint32_t)0x0UL) /**< SCON_CCACHE_FLUSH_NORMAL Value */
-#define MXC_S_GCR_SCON_CCACHE_FLUSH_NORMAL                                     \
-	(MXC_V_GCR_SCON_CCACHE_FLUSH_NORMAL                                    \
-	 << MXC_F_GCR_SCON_CCACHE_FLUSH_POS) /**< SCON_CCACHE_FLUSH_NORMAL     \
+#define MXC_S_GCR_SCON_CCACHE_FLUSH_NORMAL                                 \
+	(MXC_V_GCR_SCON_CCACHE_FLUSH_NORMAL                                \
+	 << MXC_F_GCR_SCON_CCACHE_FLUSH_POS) /**< SCON_CCACHE_FLUSH_NORMAL \
 						Setting */
-#define MXC_V_GCR_SCON_CCACHE_FLUSH_FLUSH                                      \
+#define MXC_V_GCR_SCON_CCACHE_FLUSH_FLUSH \
 	((uint32_t)0x1UL) /**< SCON_CCACHE_FLUSH_FLUSH Value */
-#define MXC_S_GCR_SCON_CCACHE_FLUSH_FLUSH                                      \
-	(MXC_V_GCR_SCON_CCACHE_FLUSH_FLUSH                                     \
-	 << MXC_F_GCR_SCON_CCACHE_FLUSH_POS) /**< SCON_CCACHE_FLUSH_FLUSH      \
+#define MXC_S_GCR_SCON_CCACHE_FLUSH_FLUSH                                 \
+	(MXC_V_GCR_SCON_CCACHE_FLUSH_FLUSH                                \
+	 << MXC_F_GCR_SCON_CCACHE_FLUSH_POS) /**< SCON_CCACHE_FLUSH_FLUSH \
 						Setting */
 
 #define MXC_F_GCR_SCON_SWD_DIS_POS 14 /**< SCON_SWD_DIS Position */
-#define MXC_F_GCR_SCON_SWD_DIS                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_SCON_SWD_DIS_POS)) /**< SCON_SWD_DIS Mask */
-#define MXC_V_GCR_SCON_SWD_DIS_ENABLE                                          \
+#define MXC_F_GCR_SCON_SWD_DIS                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_SCON_SWD_DIS_POS)) /**< SCON_SWD_DIS \
+							     Mask */
+#define MXC_V_GCR_SCON_SWD_DIS_ENABLE \
 	((uint32_t)0x0UL) /**< SCON_SWD_DIS_ENABLE Value */
-#define MXC_S_GCR_SCON_SWD_DIS_ENABLE                                          \
-	(MXC_V_GCR_SCON_SWD_DIS_ENABLE                                         \
-	 << MXC_F_GCR_SCON_SWD_DIS_POS) /**< SCON_SWD_DIS_ENABLE Setting */
-#define MXC_V_GCR_SCON_SWD_DIS_DISABLE                                         \
+#define MXC_S_GCR_SCON_SWD_DIS_ENABLE                          \
+	(MXC_V_GCR_SCON_SWD_DIS_ENABLE                         \
+	 << MXC_F_GCR_SCON_SWD_DIS_POS) /**<                   \
+					   SCON_SWD_DIS_ENABLE \
+					   Setting             \
+					 */
+#define MXC_V_GCR_SCON_SWD_DIS_DISABLE \
 	((uint32_t)0x1UL) /**< SCON_SWD_DIS_DISABLE Value */
-#define MXC_S_GCR_SCON_SWD_DIS_DISABLE                                         \
-	(MXC_V_GCR_SCON_SWD_DIS_DISABLE                                        \
-	 << MXC_F_GCR_SCON_SWD_DIS_POS) /**< SCON_SWD_DIS_DISABLE Setting */
+#define MXC_S_GCR_SCON_SWD_DIS_DISABLE                          \
+	(MXC_V_GCR_SCON_SWD_DIS_DISABLE                         \
+	 << MXC_F_GCR_SCON_SWD_DIS_POS) /**<                    \
+					   SCON_SWD_DIS_DISABLE \
+					   Setting              \
+					 */
 
 /**
  * Reset Register 0.
  */
 #define MXC_F_GCR_RSTR0_DMA_POS 0 /**< RSTR0_DMA Position */
-#define MXC_F_GCR_RSTR0_DMA                                                    \
+#define MXC_F_GCR_RSTR0_DMA \
 	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_DMA_POS)) /**< RSTR0_DMA Mask */
 #define MXC_V_GCR_RSTR0_DMA_RFU ((uint32_t)0x0UL) /**< RSTR0_DMA_RFU Value */
-#define MXC_S_GCR_RSTR0_DMA_RFU                                                \
-	(MXC_V_GCR_RSTR0_DMA_RFU                                               \
-	 << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_RFU Setting */
-#define MXC_V_GCR_RSTR0_DMA_RESET                                              \
+#define MXC_S_GCR_RSTR0_DMA_RFU                                               \
+	(MXC_V_GCR_RSTR0_DMA_RFU << MXC_F_GCR_RSTR0_DMA_POS) /**<             \
+								RSTR0_DMA_RFU \
+								Setting */
+#define MXC_V_GCR_RSTR0_DMA_RESET \
 	((uint32_t)0x1UL) /**< RSTR0_DMA_RESET Value */
-#define MXC_S_GCR_RSTR0_DMA_RESET                                              \
-	(MXC_V_GCR_RSTR0_DMA_RESET                                             \
-	 << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_RESET Setting */
-#define MXC_V_GCR_RSTR0_DMA_RESET_DONE                                         \
+#define MXC_S_GCR_RSTR0_DMA_RESET                       \
+	(MXC_V_GCR_RSTR0_DMA_RESET                      \
+	 << MXC_F_GCR_RSTR0_DMA_POS) /**<               \
+					RSTR0_DMA_RESET \
+					Setting */
+#define MXC_V_GCR_RSTR0_DMA_RESET_DONE \
 	((uint32_t)0x0UL) /**< RSTR0_DMA_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_DMA_RESET_DONE                                         \
-	(MXC_V_GCR_RSTR0_DMA_RESET_DONE                                        \
-	 << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_DMA_BUSY                                               \
-	((uint32_t)0x1UL) /**< RSTR0_DMA_BUSY Value                            \
+#define MXC_S_GCR_RSTR0_DMA_RESET_DONE                       \
+	(MXC_V_GCR_RSTR0_DMA_RESET_DONE                      \
+	 << MXC_F_GCR_RSTR0_DMA_POS) /**<                    \
+					RSTR0_DMA_RESET_DONE \
+					Setting              \
+				      */
+#define MXC_V_GCR_RSTR0_DMA_BUSY                    \
+	((uint32_t)0x1UL) /**< RSTR0_DMA_BUSY Value \
 			   */
-#define MXC_S_GCR_RSTR0_DMA_BUSY                                               \
-	(MXC_V_GCR_RSTR0_DMA_BUSY                                              \
-	 << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_BUSY Setting */
+#define MXC_S_GCR_RSTR0_DMA_BUSY                       \
+	(MXC_V_GCR_RSTR0_DMA_BUSY                      \
+	 << MXC_F_GCR_RSTR0_DMA_POS) /**<              \
+					RSTR0_DMA_BUSY \
+					Setting */
 
 #define MXC_F_GCR_RSTR0_WDT_POS 1 /**< RSTR0_WDT Position */
-#define MXC_F_GCR_RSTR0_WDT                                                    \
+#define MXC_F_GCR_RSTR0_WDT \
 	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_WDT_POS)) /**< RSTR0_WDT Mask */
 #define MXC_V_GCR_RSTR0_WDT_RFU ((uint32_t)0x0UL) /**< RSTR0_WDT_RFU Value */
-#define MXC_S_GCR_RSTR0_WDT_RFU                                                \
-	(MXC_V_GCR_RSTR0_WDT_RFU                                               \
-	 << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_RFU Setting */
-#define MXC_V_GCR_RSTR0_WDT_RESET                                              \
+#define MXC_S_GCR_RSTR0_WDT_RFU                                               \
+	(MXC_V_GCR_RSTR0_WDT_RFU << MXC_F_GCR_RSTR0_WDT_POS) /**<             \
+								RSTR0_WDT_RFU \
+								Setting */
+#define MXC_V_GCR_RSTR0_WDT_RESET \
 	((uint32_t)0x1UL) /**< RSTR0_WDT_RESET Value */
-#define MXC_S_GCR_RSTR0_WDT_RESET                                              \
-	(MXC_V_GCR_RSTR0_WDT_RESET                                             \
-	 << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_RESET Setting */
-#define MXC_V_GCR_RSTR0_WDT_RESET_DONE                                         \
+#define MXC_S_GCR_RSTR0_WDT_RESET                       \
+	(MXC_V_GCR_RSTR0_WDT_RESET                      \
+	 << MXC_F_GCR_RSTR0_WDT_POS) /**<               \
+					RSTR0_WDT_RESET \
+					Setting */
+#define MXC_V_GCR_RSTR0_WDT_RESET_DONE \
 	((uint32_t)0x0UL) /**< RSTR0_WDT_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_WDT_RESET_DONE                                         \
-	(MXC_V_GCR_RSTR0_WDT_RESET_DONE                                        \
-	 << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_WDT_BUSY                                               \
-	((uint32_t)0x1UL) /**< RSTR0_WDT_BUSY Value                            \
+#define MXC_S_GCR_RSTR0_WDT_RESET_DONE                       \
+	(MXC_V_GCR_RSTR0_WDT_RESET_DONE                      \
+	 << MXC_F_GCR_RSTR0_WDT_POS) /**<                    \
+					RSTR0_WDT_RESET_DONE \
+					Setting              \
+				      */
+#define MXC_V_GCR_RSTR0_WDT_BUSY                    \
+	((uint32_t)0x1UL) /**< RSTR0_WDT_BUSY Value \
 			   */
-#define MXC_S_GCR_RSTR0_WDT_BUSY                                               \
-	(MXC_V_GCR_RSTR0_WDT_BUSY                                              \
-	 << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_BUSY Setting */
+#define MXC_S_GCR_RSTR0_WDT_BUSY                       \
+	(MXC_V_GCR_RSTR0_WDT_BUSY                      \
+	 << MXC_F_GCR_RSTR0_WDT_POS) /**<              \
+					RSTR0_WDT_BUSY \
+					Setting */
 
 #define MXC_F_GCR_RSTR0_GPIO0_POS 2 /**< RSTR0_GPIO0 Position */
 #define MXC_F_GCR_RSTR0_GPIO0                                                  \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_GCR_RSTR0_GPIO0_POS)) /**< RSTR0_GPIO0 Mask */
-#define MXC_V_GCR_RSTR0_GPIO0_RFU                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_GPIO0_POS)) /**< RSTR0_GPIO0 Mask \
+							  */
+#define MXC_V_GCR_RSTR0_GPIO0_RFU \
 	((uint32_t)0x0UL) /**< RSTR0_GPIO0_RFU Value */
-#define MXC_S_GCR_RSTR0_GPIO0_RFU                                              \
-	(MXC_V_GCR_RSTR0_GPIO0_RFU                                             \
-	 << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_RFU Setting */
-#define MXC_V_GCR_RSTR0_GPIO0_RESET                                            \
+#define MXC_S_GCR_RSTR0_GPIO0_RFU                         \
+	(MXC_V_GCR_RSTR0_GPIO0_RFU                        \
+	 << MXC_F_GCR_RSTR0_GPIO0_POS) /**<               \
+					  RSTR0_GPIO0_RFU \
+					  Setting */
+#define MXC_V_GCR_RSTR0_GPIO0_RESET \
 	((uint32_t)0x1UL) /**< RSTR0_GPIO0_RESET Value */
-#define MXC_S_GCR_RSTR0_GPIO0_RESET                                            \
-	(MXC_V_GCR_RSTR0_GPIO0_RESET                                           \
-	 << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_RESET Setting */
-#define MXC_V_GCR_RSTR0_GPIO0_RESET_DONE                                       \
+#define MXC_S_GCR_RSTR0_GPIO0_RESET                         \
+	(MXC_V_GCR_RSTR0_GPIO0_RESET                        \
+	 << MXC_F_GCR_RSTR0_GPIO0_POS) /**<                 \
+					  RSTR0_GPIO0_RESET \
+					  Setting           \
+					*/
+#define MXC_V_GCR_RSTR0_GPIO0_RESET_DONE \
 	((uint32_t)0x0UL) /**< RSTR0_GPIO0_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_GPIO0_RESET_DONE                                       \
-	(MXC_V_GCR_RSTR0_GPIO0_RESET_DONE                                      \
-	 << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_GPIO0_BUSY                                             \
+#define MXC_S_GCR_RSTR0_GPIO0_RESET_DONE                         \
+	(MXC_V_GCR_RSTR0_GPIO0_RESET_DONE                        \
+	 << MXC_F_GCR_RSTR0_GPIO0_POS) /**<                      \
+					  RSTR0_GPIO0_RESET_DONE \
+					  Setting                \
+					*/
+#define MXC_V_GCR_RSTR0_GPIO0_BUSY \
 	((uint32_t)0x1UL) /**< RSTR0_GPIO0_BUSY Value */
-#define MXC_S_GCR_RSTR0_GPIO0_BUSY                                             \
-	(MXC_V_GCR_RSTR0_GPIO0_BUSY                                            \
-	 << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_BUSY Setting */
+#define MXC_S_GCR_RSTR0_GPIO0_BUSY                         \
+	(MXC_V_GCR_RSTR0_GPIO0_BUSY                        \
+	 << MXC_F_GCR_RSTR0_GPIO0_POS) /**<                \
+					  RSTR0_GPIO0_BUSY \
+					  Setting          \
+					*/
 
 #define MXC_F_GCR_RSTR0_TIMER0_POS 5 /**< RSTR0_TIMER0 Position */
-#define MXC_F_GCR_RSTR0_TIMER0                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_RSTR0_TIMER0_POS)) /**< RSTR0_TIMER0 Mask */
-#define MXC_V_GCR_RSTR0_TIMER0_RFU                                             \
+#define MXC_F_GCR_RSTR0_TIMER0                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER0_POS)) /**< RSTR0_TIMER0 \
+							     Mask */
+#define MXC_V_GCR_RSTR0_TIMER0_RFU \
 	((uint32_t)0x0UL) /**< RSTR0_TIMER0_RFU Value */
-#define MXC_S_GCR_RSTR0_TIMER0_RFU                                             \
-	(MXC_V_GCR_RSTR0_TIMER0_RFU                                            \
-	 << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_RFU Setting */
-#define MXC_V_GCR_RSTR0_TIMER0_RESET                                           \
+#define MXC_S_GCR_RSTR0_TIMER0_RFU                          \
+	(MXC_V_GCR_RSTR0_TIMER0_RFU                         \
+	 << MXC_F_GCR_RSTR0_TIMER0_POS) /**<                \
+					   RSTR0_TIMER0_RFU \
+					   Setting          \
+					 */
+#define MXC_V_GCR_RSTR0_TIMER0_RESET \
 	((uint32_t)0x1UL) /**< RSTR0_TIMER0_RESET Value */
-#define MXC_S_GCR_RSTR0_TIMER0_RESET                                           \
-	(MXC_V_GCR_RSTR0_TIMER0_RESET                                          \
-	 << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_RESET Setting */
-#define MXC_V_GCR_RSTR0_TIMER0_RESET_DONE                                      \
+#define MXC_S_GCR_RSTR0_TIMER0_RESET                          \
+	(MXC_V_GCR_RSTR0_TIMER0_RESET                         \
+	 << MXC_F_GCR_RSTR0_TIMER0_POS) /**<                  \
+					   RSTR0_TIMER0_RESET \
+					   Setting            \
+					 */
+#define MXC_V_GCR_RSTR0_TIMER0_RESET_DONE \
 	((uint32_t)0x0UL) /**< RSTR0_TIMER0_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_TIMER0_RESET_DONE                                      \
-	(MXC_V_GCR_RSTR0_TIMER0_RESET_DONE                                     \
-	 << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_RESET_DONE Setting   \
+#define MXC_S_GCR_RSTR0_TIMER0_RESET_DONE                                    \
+	(MXC_V_GCR_RSTR0_TIMER0_RESET_DONE                                   \
+	 << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_RESET_DONE Setting \
 					 */
-#define MXC_V_GCR_RSTR0_TIMER0_BUSY                                            \
+#define MXC_V_GCR_RSTR0_TIMER0_BUSY \
 	((uint32_t)0x1UL) /**< RSTR0_TIMER0_BUSY Value */
-#define MXC_S_GCR_RSTR0_TIMER0_BUSY                                            \
-	(MXC_V_GCR_RSTR0_TIMER0_BUSY                                           \
-	 << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_BUSY Setting */
+#define MXC_S_GCR_RSTR0_TIMER0_BUSY                          \
+	(MXC_V_GCR_RSTR0_TIMER0_BUSY                         \
+	 << MXC_F_GCR_RSTR0_TIMER0_POS) /**<                 \
+					   RSTR0_TIMER0_BUSY \
+					   Setting           \
+					 */
 
 #define MXC_F_GCR_RSTR0_TIMER1_POS 6 /**< RSTR0_TIMER1 Position */
-#define MXC_F_GCR_RSTR0_TIMER1                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_RSTR0_TIMER1_POS)) /**< RSTR0_TIMER1 Mask */
-#define MXC_V_GCR_RSTR0_TIMER1_RFU                                             \
+#define MXC_F_GCR_RSTR0_TIMER1                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER1_POS)) /**< RSTR0_TIMER1 \
+							     Mask */
+#define MXC_V_GCR_RSTR0_TIMER1_RFU \
 	((uint32_t)0x0UL) /**< RSTR0_TIMER1_RFU Value */
-#define MXC_S_GCR_RSTR0_TIMER1_RFU                                             \
-	(MXC_V_GCR_RSTR0_TIMER1_RFU                                            \
-	 << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_RFU Setting */
-#define MXC_V_GCR_RSTR0_TIMER1_RESET                                           \
+#define MXC_S_GCR_RSTR0_TIMER1_RFU                          \
+	(MXC_V_GCR_RSTR0_TIMER1_RFU                         \
+	 << MXC_F_GCR_RSTR0_TIMER1_POS) /**<                \
+					   RSTR0_TIMER1_RFU \
+					   Setting          \
+					 */
+#define MXC_V_GCR_RSTR0_TIMER1_RESET \
 	((uint32_t)0x1UL) /**< RSTR0_TIMER1_RESET Value */
-#define MXC_S_GCR_RSTR0_TIMER1_RESET                                           \
-	(MXC_V_GCR_RSTR0_TIMER1_RESET                                          \
-	 << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_RESET Setting */
-#define MXC_V_GCR_RSTR0_TIMER1_RESET_DONE                                      \
+#define MXC_S_GCR_RSTR0_TIMER1_RESET                          \
+	(MXC_V_GCR_RSTR0_TIMER1_RESET                         \
+	 << MXC_F_GCR_RSTR0_TIMER1_POS) /**<                  \
+					   RSTR0_TIMER1_RESET \
+					   Setting            \
+					 */
+#define MXC_V_GCR_RSTR0_TIMER1_RESET_DONE \
 	((uint32_t)0x0UL) /**< RSTR0_TIMER1_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_TIMER1_RESET_DONE                                      \
-	(MXC_V_GCR_RSTR0_TIMER1_RESET_DONE                                     \
-	 << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_RESET_DONE Setting   \
+#define MXC_S_GCR_RSTR0_TIMER1_RESET_DONE                                    \
+	(MXC_V_GCR_RSTR0_TIMER1_RESET_DONE                                   \
+	 << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_RESET_DONE Setting \
 					 */
-#define MXC_V_GCR_RSTR0_TIMER1_BUSY                                            \
+#define MXC_V_GCR_RSTR0_TIMER1_BUSY \
 	((uint32_t)0x1UL) /**< RSTR0_TIMER1_BUSY Value */
-#define MXC_S_GCR_RSTR0_TIMER1_BUSY                                            \
-	(MXC_V_GCR_RSTR0_TIMER1_BUSY                                           \
-	 << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_BUSY Setting */
+#define MXC_S_GCR_RSTR0_TIMER1_BUSY                          \
+	(MXC_V_GCR_RSTR0_TIMER1_BUSY                         \
+	 << MXC_F_GCR_RSTR0_TIMER1_POS) /**<                 \
+					   RSTR0_TIMER1_BUSY \
+					   Setting           \
+					 */
 
 #define MXC_F_GCR_RSTR0_TIMER2_POS 7 /**< RSTR0_TIMER2 Position */
-#define MXC_F_GCR_RSTR0_TIMER2                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_RSTR0_TIMER2_POS)) /**< RSTR0_TIMER2 Mask */
-#define MXC_V_GCR_RSTR0_TIMER2_RFU                                             \
+#define MXC_F_GCR_RSTR0_TIMER2                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER2_POS)) /**< RSTR0_TIMER2 \
+							     Mask */
+#define MXC_V_GCR_RSTR0_TIMER2_RFU \
 	((uint32_t)0x0UL) /**< RSTR0_TIMER2_RFU Value */
-#define MXC_S_GCR_RSTR0_TIMER2_RFU                                             \
-	(MXC_V_GCR_RSTR0_TIMER2_RFU                                            \
-	 << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_RFU Setting */
-#define MXC_V_GCR_RSTR0_TIMER2_RESET                                           \
+#define MXC_S_GCR_RSTR0_TIMER2_RFU                          \
+	(MXC_V_GCR_RSTR0_TIMER2_RFU                         \
+	 << MXC_F_GCR_RSTR0_TIMER2_POS) /**<                \
+					   RSTR0_TIMER2_RFU \
+					   Setting          \
+					 */
+#define MXC_V_GCR_RSTR0_TIMER2_RESET \
 	((uint32_t)0x1UL) /**< RSTR0_TIMER2_RESET Value */
-#define MXC_S_GCR_RSTR0_TIMER2_RESET                                           \
-	(MXC_V_GCR_RSTR0_TIMER2_RESET                                          \
-	 << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_RESET Setting */
-#define MXC_V_GCR_RSTR0_TIMER2_RESET_DONE                                      \
+#define MXC_S_GCR_RSTR0_TIMER2_RESET                          \
+	(MXC_V_GCR_RSTR0_TIMER2_RESET                         \
+	 << MXC_F_GCR_RSTR0_TIMER2_POS) /**<                  \
+					   RSTR0_TIMER2_RESET \
+					   Setting            \
+					 */
+#define MXC_V_GCR_RSTR0_TIMER2_RESET_DONE \
 	((uint32_t)0x0UL) /**< RSTR0_TIMER2_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_TIMER2_RESET_DONE                                      \
-	(MXC_V_GCR_RSTR0_TIMER2_RESET_DONE                                     \
-	 << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_RESET_DONE Setting   \
+#define MXC_S_GCR_RSTR0_TIMER2_RESET_DONE                                    \
+	(MXC_V_GCR_RSTR0_TIMER2_RESET_DONE                                   \
+	 << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_RESET_DONE Setting \
 					 */
-#define MXC_V_GCR_RSTR0_TIMER2_BUSY                                            \
+#define MXC_V_GCR_RSTR0_TIMER2_BUSY \
 	((uint32_t)0x1UL) /**< RSTR0_TIMER2_BUSY Value */
-#define MXC_S_GCR_RSTR0_TIMER2_BUSY                                            \
-	(MXC_V_GCR_RSTR0_TIMER2_BUSY                                           \
-	 << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_BUSY Setting */
+#define MXC_S_GCR_RSTR0_TIMER2_BUSY                          \
+	(MXC_V_GCR_RSTR0_TIMER2_BUSY                         \
+	 << MXC_F_GCR_RSTR0_TIMER2_POS) /**<                 \
+					   RSTR0_TIMER2_BUSY \
+					   Setting           \
+					 */
 
 #define MXC_F_GCR_RSTR0_UART0_POS 11 /**< RSTR0_UART0 Position */
 #define MXC_F_GCR_RSTR0_UART0                                                  \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_GCR_RSTR0_UART0_POS)) /**< RSTR0_UART0 Mask */
-#define MXC_V_GCR_RSTR0_UART0_RFU                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_UART0_POS)) /**< RSTR0_UART0 Mask \
+							  */
+#define MXC_V_GCR_RSTR0_UART0_RFU \
 	((uint32_t)0x0UL) /**< RSTR0_UART0_RFU Value */
-#define MXC_S_GCR_RSTR0_UART0_RFU                                              \
-	(MXC_V_GCR_RSTR0_UART0_RFU                                             \
-	 << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_RFU Setting */
-#define MXC_V_GCR_RSTR0_UART0_RESET                                            \
+#define MXC_S_GCR_RSTR0_UART0_RFU                         \
+	(MXC_V_GCR_RSTR0_UART0_RFU                        \
+	 << MXC_F_GCR_RSTR0_UART0_POS) /**<               \
+					  RSTR0_UART0_RFU \
+					  Setting */
+#define MXC_V_GCR_RSTR0_UART0_RESET \
 	((uint32_t)0x1UL) /**< RSTR0_UART0_RESET Value */
-#define MXC_S_GCR_RSTR0_UART0_RESET                                            \
-	(MXC_V_GCR_RSTR0_UART0_RESET                                           \
-	 << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_RESET Setting */
-#define MXC_V_GCR_RSTR0_UART0_RESET_DONE                                       \
+#define MXC_S_GCR_RSTR0_UART0_RESET                         \
+	(MXC_V_GCR_RSTR0_UART0_RESET                        \
+	 << MXC_F_GCR_RSTR0_UART0_POS) /**<                 \
+					  RSTR0_UART0_RESET \
+					  Setting           \
+					*/
+#define MXC_V_GCR_RSTR0_UART0_RESET_DONE \
 	((uint32_t)0x0UL) /**< RSTR0_UART0_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_UART0_RESET_DONE                                       \
-	(MXC_V_GCR_RSTR0_UART0_RESET_DONE                                      \
-	 << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_UART0_BUSY                                             \
+#define MXC_S_GCR_RSTR0_UART0_RESET_DONE                         \
+	(MXC_V_GCR_RSTR0_UART0_RESET_DONE                        \
+	 << MXC_F_GCR_RSTR0_UART0_POS) /**<                      \
+					  RSTR0_UART0_RESET_DONE \
+					  Setting                \
+					*/
+#define MXC_V_GCR_RSTR0_UART0_BUSY \
 	((uint32_t)0x1UL) /**< RSTR0_UART0_BUSY Value */
-#define MXC_S_GCR_RSTR0_UART0_BUSY                                             \
-	(MXC_V_GCR_RSTR0_UART0_BUSY                                            \
-	 << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_BUSY Setting */
+#define MXC_S_GCR_RSTR0_UART0_BUSY                         \
+	(MXC_V_GCR_RSTR0_UART0_BUSY                        \
+	 << MXC_F_GCR_RSTR0_UART0_POS) /**<                \
+					  RSTR0_UART0_BUSY \
+					  Setting          \
+					*/
 
 #define MXC_F_GCR_RSTR0_UART1_POS 12 /**< RSTR0_UART1 Position */
 #define MXC_F_GCR_RSTR0_UART1                                                  \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_GCR_RSTR0_UART1_POS)) /**< RSTR0_UART1 Mask */
-#define MXC_V_GCR_RSTR0_UART1_RFU                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_UART1_POS)) /**< RSTR0_UART1 Mask \
+							  */
+#define MXC_V_GCR_RSTR0_UART1_RFU \
 	((uint32_t)0x0UL) /**< RSTR0_UART1_RFU Value */
-#define MXC_S_GCR_RSTR0_UART1_RFU                                              \
-	(MXC_V_GCR_RSTR0_UART1_RFU                                             \
-	 << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_RFU Setting */
-#define MXC_V_GCR_RSTR0_UART1_RESET                                            \
+#define MXC_S_GCR_RSTR0_UART1_RFU                         \
+	(MXC_V_GCR_RSTR0_UART1_RFU                        \
+	 << MXC_F_GCR_RSTR0_UART1_POS) /**<               \
+					  RSTR0_UART1_RFU \
+					  Setting */
+#define MXC_V_GCR_RSTR0_UART1_RESET \
 	((uint32_t)0x1UL) /**< RSTR0_UART1_RESET Value */
-#define MXC_S_GCR_RSTR0_UART1_RESET                                            \
-	(MXC_V_GCR_RSTR0_UART1_RESET                                           \
-	 << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_RESET Setting */
-#define MXC_V_GCR_RSTR0_UART1_RESET_DONE                                       \
+#define MXC_S_GCR_RSTR0_UART1_RESET                         \
+	(MXC_V_GCR_RSTR0_UART1_RESET                        \
+	 << MXC_F_GCR_RSTR0_UART1_POS) /**<                 \
+					  RSTR0_UART1_RESET \
+					  Setting           \
+					*/
+#define MXC_V_GCR_RSTR0_UART1_RESET_DONE \
 	((uint32_t)0x0UL) /**< RSTR0_UART1_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_UART1_RESET_DONE                                       \
-	(MXC_V_GCR_RSTR0_UART1_RESET_DONE                                      \
-	 << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_UART1_BUSY                                             \
+#define MXC_S_GCR_RSTR0_UART1_RESET_DONE                         \
+	(MXC_V_GCR_RSTR0_UART1_RESET_DONE                        \
+	 << MXC_F_GCR_RSTR0_UART1_POS) /**<                      \
+					  RSTR0_UART1_RESET_DONE \
+					  Setting                \
+					*/
+#define MXC_V_GCR_RSTR0_UART1_BUSY \
 	((uint32_t)0x1UL) /**< RSTR0_UART1_BUSY Value */
-#define MXC_S_GCR_RSTR0_UART1_BUSY                                             \
-	(MXC_V_GCR_RSTR0_UART1_BUSY                                            \
-	 << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_BUSY Setting */
+#define MXC_S_GCR_RSTR0_UART1_BUSY                         \
+	(MXC_V_GCR_RSTR0_UART1_BUSY                        \
+	 << MXC_F_GCR_RSTR0_UART1_POS) /**<                \
+					  RSTR0_UART1_BUSY \
+					  Setting          \
+					*/
 
 #define MXC_F_GCR_RSTR0_SPI0_POS 13 /**< RSTR0_SPI0 Position */
-#define MXC_F_GCR_RSTR0_SPI0                                                   \
-	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI0_POS)) /**< RSTR0_SPI0 Mask   \
+#define MXC_F_GCR_RSTR0_SPI0                                                 \
+	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI0_POS)) /**< RSTR0_SPI0 Mask \
 							 */
-#define MXC_V_GCR_RSTR0_SPI0_RFU                                               \
-	((uint32_t)0x0UL) /**< RSTR0_SPI0_RFU Value                            \
+#define MXC_V_GCR_RSTR0_SPI0_RFU                    \
+	((uint32_t)0x0UL) /**< RSTR0_SPI0_RFU Value \
 			   */
-#define MXC_S_GCR_RSTR0_SPI0_RFU                                               \
-	(MXC_V_GCR_RSTR0_SPI0_RFU                                              \
-	 << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_RFU Setting */
-#define MXC_V_GCR_RSTR0_SPI0_RESET                                             \
+#define MXC_S_GCR_RSTR0_SPI0_RFU                        \
+	(MXC_V_GCR_RSTR0_SPI0_RFU                       \
+	 << MXC_F_GCR_RSTR0_SPI0_POS) /**<              \
+					 RSTR0_SPI0_RFU \
+					 Setting */
+#define MXC_V_GCR_RSTR0_SPI0_RESET \
 	((uint32_t)0x1UL) /**< RSTR0_SPI0_RESET Value */
-#define MXC_S_GCR_RSTR0_SPI0_RESET                                             \
-	(MXC_V_GCR_RSTR0_SPI0_RESET                                            \
-	 << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_RESET Setting */
-#define MXC_V_GCR_RSTR0_SPI0_RESET_DONE                                        \
+#define MXC_S_GCR_RSTR0_SPI0_RESET                        \
+	(MXC_V_GCR_RSTR0_SPI0_RESET                       \
+	 << MXC_F_GCR_RSTR0_SPI0_POS) /**<                \
+					 RSTR0_SPI0_RESET \
+					 Setting */
+#define MXC_V_GCR_RSTR0_SPI0_RESET_DONE \
 	((uint32_t)0x0UL) /**< RSTR0_SPI0_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_SPI0_RESET_DONE                                        \
-	(MXC_V_GCR_RSTR0_SPI0_RESET_DONE                                       \
-	 << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_SPI0_BUSY                                              \
+#define MXC_S_GCR_RSTR0_SPI0_RESET_DONE                        \
+	(MXC_V_GCR_RSTR0_SPI0_RESET_DONE                       \
+	 << MXC_F_GCR_RSTR0_SPI0_POS) /**<                     \
+					 RSTR0_SPI0_RESET_DONE \
+					 Setting               \
+				       */
+#define MXC_V_GCR_RSTR0_SPI0_BUSY \
 	((uint32_t)0x1UL) /**< RSTR0_SPI0_BUSY Value */
-#define MXC_S_GCR_RSTR0_SPI0_BUSY                                              \
-	(MXC_V_GCR_RSTR0_SPI0_BUSY                                             \
-	 << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_BUSY Setting */
+#define MXC_S_GCR_RSTR0_SPI0_BUSY                        \
+	(MXC_V_GCR_RSTR0_SPI0_BUSY                       \
+	 << MXC_F_GCR_RSTR0_SPI0_POS) /**<               \
+					 RSTR0_SPI0_BUSY \
+					 Setting */
 
 #define MXC_F_GCR_RSTR0_SPI1_POS 14 /**< RSTR0_SPI1 Position */
-#define MXC_F_GCR_RSTR0_SPI1                                                   \
-	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI1_POS)) /**< RSTR0_SPI1 Mask   \
+#define MXC_F_GCR_RSTR0_SPI1                                                 \
+	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI1_POS)) /**< RSTR0_SPI1 Mask \
 							 */
-#define MXC_V_GCR_RSTR0_SPI1_RFU                                               \
-	((uint32_t)0x0UL) /**< RSTR0_SPI1_RFU Value                            \
+#define MXC_V_GCR_RSTR0_SPI1_RFU                    \
+	((uint32_t)0x0UL) /**< RSTR0_SPI1_RFU Value \
 			   */
-#define MXC_S_GCR_RSTR0_SPI1_RFU                                               \
-	(MXC_V_GCR_RSTR0_SPI1_RFU                                              \
-	 << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_RFU Setting */
-#define MXC_V_GCR_RSTR0_SPI1_RESET                                             \
+#define MXC_S_GCR_RSTR0_SPI1_RFU                        \
+	(MXC_V_GCR_RSTR0_SPI1_RFU                       \
+	 << MXC_F_GCR_RSTR0_SPI1_POS) /**<              \
+					 RSTR0_SPI1_RFU \
+					 Setting */
+#define MXC_V_GCR_RSTR0_SPI1_RESET \
 	((uint32_t)0x1UL) /**< RSTR0_SPI1_RESET Value */
-#define MXC_S_GCR_RSTR0_SPI1_RESET                                             \
-	(MXC_V_GCR_RSTR0_SPI1_RESET                                            \
-	 << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_RESET Setting */
-#define MXC_V_GCR_RSTR0_SPI1_RESET_DONE                                        \
+#define MXC_S_GCR_RSTR0_SPI1_RESET                        \
+	(MXC_V_GCR_RSTR0_SPI1_RESET                       \
+	 << MXC_F_GCR_RSTR0_SPI1_POS) /**<                \
+					 RSTR0_SPI1_RESET \
+					 Setting */
+#define MXC_V_GCR_RSTR0_SPI1_RESET_DONE \
 	((uint32_t)0x0UL) /**< RSTR0_SPI1_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_SPI1_RESET_DONE                                        \
-	(MXC_V_GCR_RSTR0_SPI1_RESET_DONE                                       \
-	 << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_SPI1_BUSY                                              \
+#define MXC_S_GCR_RSTR0_SPI1_RESET_DONE                        \
+	(MXC_V_GCR_RSTR0_SPI1_RESET_DONE                       \
+	 << MXC_F_GCR_RSTR0_SPI1_POS) /**<                     \
+					 RSTR0_SPI1_RESET_DONE \
+					 Setting               \
+				       */
+#define MXC_V_GCR_RSTR0_SPI1_BUSY \
 	((uint32_t)0x1UL) /**< RSTR0_SPI1_BUSY Value */
-#define MXC_S_GCR_RSTR0_SPI1_BUSY                                              \
-	(MXC_V_GCR_RSTR0_SPI1_BUSY                                             \
-	 << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_BUSY Setting */
+#define MXC_S_GCR_RSTR0_SPI1_BUSY                        \
+	(MXC_V_GCR_RSTR0_SPI1_BUSY                       \
+	 << MXC_F_GCR_RSTR0_SPI1_POS) /**<               \
+					 RSTR0_SPI1_BUSY \
+					 Setting */
 
 #define MXC_F_GCR_RSTR0_I2C0_POS 16 /**< RSTR0_I2C0 Position */
-#define MXC_F_GCR_RSTR0_I2C0                                                   \
-	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_I2C0_POS)) /**< RSTR0_I2C0 Mask   \
+#define MXC_F_GCR_RSTR0_I2C0                                                 \
+	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_I2C0_POS)) /**< RSTR0_I2C0 Mask \
 							 */
-#define MXC_V_GCR_RSTR0_I2C0_RFU                                               \
-	((uint32_t)0x0UL) /**< RSTR0_I2C0_RFU Value                            \
+#define MXC_V_GCR_RSTR0_I2C0_RFU                    \
+	((uint32_t)0x0UL) /**< RSTR0_I2C0_RFU Value \
 			   */
-#define MXC_S_GCR_RSTR0_I2C0_RFU                                               \
-	(MXC_V_GCR_RSTR0_I2C0_RFU                                              \
-	 << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_RFU Setting */
-#define MXC_V_GCR_RSTR0_I2C0_RESET                                             \
+#define MXC_S_GCR_RSTR0_I2C0_RFU                        \
+	(MXC_V_GCR_RSTR0_I2C0_RFU                       \
+	 << MXC_F_GCR_RSTR0_I2C0_POS) /**<              \
+					 RSTR0_I2C0_RFU \
+					 Setting */
+#define MXC_V_GCR_RSTR0_I2C0_RESET \
 	((uint32_t)0x1UL) /**< RSTR0_I2C0_RESET Value */
-#define MXC_S_GCR_RSTR0_I2C0_RESET                                             \
-	(MXC_V_GCR_RSTR0_I2C0_RESET                                            \
-	 << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_RESET Setting */
-#define MXC_V_GCR_RSTR0_I2C0_RESET_DONE                                        \
+#define MXC_S_GCR_RSTR0_I2C0_RESET                        \
+	(MXC_V_GCR_RSTR0_I2C0_RESET                       \
+	 << MXC_F_GCR_RSTR0_I2C0_POS) /**<                \
+					 RSTR0_I2C0_RESET \
+					 Setting */
+#define MXC_V_GCR_RSTR0_I2C0_RESET_DONE \
 	((uint32_t)0x0UL) /**< RSTR0_I2C0_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_I2C0_RESET_DONE                                        \
-	(MXC_V_GCR_RSTR0_I2C0_RESET_DONE                                       \
-	 << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_I2C0_BUSY                                              \
+#define MXC_S_GCR_RSTR0_I2C0_RESET_DONE                        \
+	(MXC_V_GCR_RSTR0_I2C0_RESET_DONE                       \
+	 << MXC_F_GCR_RSTR0_I2C0_POS) /**<                     \
+					 RSTR0_I2C0_RESET_DONE \
+					 Setting               \
+				       */
+#define MXC_V_GCR_RSTR0_I2C0_BUSY \
 	((uint32_t)0x1UL) /**< RSTR0_I2C0_BUSY Value */
-#define MXC_S_GCR_RSTR0_I2C0_BUSY                                              \
-	(MXC_V_GCR_RSTR0_I2C0_BUSY                                             \
-	 << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_BUSY Setting */
+#define MXC_S_GCR_RSTR0_I2C0_BUSY                        \
+	(MXC_V_GCR_RSTR0_I2C0_BUSY                       \
+	 << MXC_F_GCR_RSTR0_I2C0_POS) /**<               \
+					 RSTR0_I2C0_BUSY \
+					 Setting */
 
 #define MXC_F_GCR_RSTR0_RTC_POS 17 /**< RSTR0_RTC Position */
-#define MXC_F_GCR_RSTR0_RTC                                                    \
+#define MXC_F_GCR_RSTR0_RTC \
 	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_RTC_POS)) /**< RSTR0_RTC Mask */
 #define MXC_V_GCR_RSTR0_RTC_RFU ((uint32_t)0x0UL) /**< RSTR0_RTC_RFU Value */
-#define MXC_S_GCR_RSTR0_RTC_RFU                                                \
-	(MXC_V_GCR_RSTR0_RTC_RFU                                               \
-	 << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_RFU Setting */
-#define MXC_V_GCR_RSTR0_RTC_RESET                                              \
+#define MXC_S_GCR_RSTR0_RTC_RFU                                               \
+	(MXC_V_GCR_RSTR0_RTC_RFU << MXC_F_GCR_RSTR0_RTC_POS) /**<             \
+								RSTR0_RTC_RFU \
+								Setting */
+#define MXC_V_GCR_RSTR0_RTC_RESET \
 	((uint32_t)0x1UL) /**< RSTR0_RTC_RESET Value */
-#define MXC_S_GCR_RSTR0_RTC_RESET                                              \
-	(MXC_V_GCR_RSTR0_RTC_RESET                                             \
-	 << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_RESET Setting */
-#define MXC_V_GCR_RSTR0_RTC_RESET_DONE                                         \
+#define MXC_S_GCR_RSTR0_RTC_RESET                       \
+	(MXC_V_GCR_RSTR0_RTC_RESET                      \
+	 << MXC_F_GCR_RSTR0_RTC_POS) /**<               \
+					RSTR0_RTC_RESET \
+					Setting */
+#define MXC_V_GCR_RSTR0_RTC_RESET_DONE \
 	((uint32_t)0x0UL) /**< RSTR0_RTC_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_RTC_RESET_DONE                                         \
-	(MXC_V_GCR_RSTR0_RTC_RESET_DONE                                        \
-	 << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_RTC_BUSY                                               \
-	((uint32_t)0x1UL) /**< RSTR0_RTC_BUSY Value                            \
+#define MXC_S_GCR_RSTR0_RTC_RESET_DONE                       \
+	(MXC_V_GCR_RSTR0_RTC_RESET_DONE                      \
+	 << MXC_F_GCR_RSTR0_RTC_POS) /**<                    \
+					RSTR0_RTC_RESET_DONE \
+					Setting              \
+				      */
+#define MXC_V_GCR_RSTR0_RTC_BUSY                    \
+	((uint32_t)0x1UL) /**< RSTR0_RTC_BUSY Value \
 			   */
-#define MXC_S_GCR_RSTR0_RTC_BUSY                                               \
-	(MXC_V_GCR_RSTR0_RTC_BUSY                                              \
-	 << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_BUSY Setting */
+#define MXC_S_GCR_RSTR0_RTC_BUSY                       \
+	(MXC_V_GCR_RSTR0_RTC_BUSY                      \
+	 << MXC_F_GCR_RSTR0_RTC_POS) /**<              \
+					RSTR0_RTC_BUSY \
+					Setting */
 
 #define MXC_F_GCR_RSTR0_SRST_POS 29 /**< RSTR0_SRST Position */
-#define MXC_F_GCR_RSTR0_SRST                                                   \
-	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SRST_POS)) /**< RSTR0_SRST Mask   \
+#define MXC_F_GCR_RSTR0_SRST                                                 \
+	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SRST_POS)) /**< RSTR0_SRST Mask \
 							 */
-#define MXC_V_GCR_RSTR0_SRST_RFU                                               \
-	((uint32_t)0x0UL) /**< RSTR0_SRST_RFU Value                            \
+#define MXC_V_GCR_RSTR0_SRST_RFU                    \
+	((uint32_t)0x0UL) /**< RSTR0_SRST_RFU Value \
 			   */
-#define MXC_S_GCR_RSTR0_SRST_RFU                                               \
-	(MXC_V_GCR_RSTR0_SRST_RFU                                              \
-	 << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_RFU Setting */
-#define MXC_V_GCR_RSTR0_SRST_RESET                                             \
+#define MXC_S_GCR_RSTR0_SRST_RFU                        \
+	(MXC_V_GCR_RSTR0_SRST_RFU                       \
+	 << MXC_F_GCR_RSTR0_SRST_POS) /**<              \
+					 RSTR0_SRST_RFU \
+					 Setting */
+#define MXC_V_GCR_RSTR0_SRST_RESET \
 	((uint32_t)0x1UL) /**< RSTR0_SRST_RESET Value */
-#define MXC_S_GCR_RSTR0_SRST_RESET                                             \
-	(MXC_V_GCR_RSTR0_SRST_RESET                                            \
-	 << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_RESET Setting */
-#define MXC_V_GCR_RSTR0_SRST_RESET_DONE                                        \
+#define MXC_S_GCR_RSTR0_SRST_RESET                        \
+	(MXC_V_GCR_RSTR0_SRST_RESET                       \
+	 << MXC_F_GCR_RSTR0_SRST_POS) /**<                \
+					 RSTR0_SRST_RESET \
+					 Setting */
+#define MXC_V_GCR_RSTR0_SRST_RESET_DONE \
 	((uint32_t)0x0UL) /**< RSTR0_SRST_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_SRST_RESET_DONE                                        \
-	(MXC_V_GCR_RSTR0_SRST_RESET_DONE                                       \
-	 << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_SRST_BUSY                                              \
+#define MXC_S_GCR_RSTR0_SRST_RESET_DONE                        \
+	(MXC_V_GCR_RSTR0_SRST_RESET_DONE                       \
+	 << MXC_F_GCR_RSTR0_SRST_POS) /**<                     \
+					 RSTR0_SRST_RESET_DONE \
+					 Setting               \
+				       */
+#define MXC_V_GCR_RSTR0_SRST_BUSY \
 	((uint32_t)0x1UL) /**< RSTR0_SRST_BUSY Value */
-#define MXC_S_GCR_RSTR0_SRST_BUSY                                              \
-	(MXC_V_GCR_RSTR0_SRST_BUSY                                             \
-	 << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_BUSY Setting */
+#define MXC_S_GCR_RSTR0_SRST_BUSY                        \
+	(MXC_V_GCR_RSTR0_SRST_BUSY                       \
+	 << MXC_F_GCR_RSTR0_SRST_POS) /**<               \
+					 RSTR0_SRST_BUSY \
+					 Setting */
 
 #define MXC_F_GCR_RSTR0_PRST_POS 30 /**< RSTR0_PRST Position */
-#define MXC_F_GCR_RSTR0_PRST                                                   \
-	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_PRST_POS)) /**< RSTR0_PRST Mask   \
+#define MXC_F_GCR_RSTR0_PRST                                                 \
+	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_PRST_POS)) /**< RSTR0_PRST Mask \
 							 */
-#define MXC_V_GCR_RSTR0_PRST_RFU                                               \
-	((uint32_t)0x0UL) /**< RSTR0_PRST_RFU Value                            \
+#define MXC_V_GCR_RSTR0_PRST_RFU                    \
+	((uint32_t)0x0UL) /**< RSTR0_PRST_RFU Value \
 			   */
-#define MXC_S_GCR_RSTR0_PRST_RFU                                               \
-	(MXC_V_GCR_RSTR0_PRST_RFU                                              \
-	 << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_RFU Setting */
-#define MXC_V_GCR_RSTR0_PRST_RESET                                             \
+#define MXC_S_GCR_RSTR0_PRST_RFU                        \
+	(MXC_V_GCR_RSTR0_PRST_RFU                       \
+	 << MXC_F_GCR_RSTR0_PRST_POS) /**<              \
+					 RSTR0_PRST_RFU \
+					 Setting */
+#define MXC_V_GCR_RSTR0_PRST_RESET \
 	((uint32_t)0x1UL) /**< RSTR0_PRST_RESET Value */
-#define MXC_S_GCR_RSTR0_PRST_RESET                                             \
-	(MXC_V_GCR_RSTR0_PRST_RESET                                            \
-	 << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_RESET Setting */
-#define MXC_V_GCR_RSTR0_PRST_RESET_DONE                                        \
+#define MXC_S_GCR_RSTR0_PRST_RESET                        \
+	(MXC_V_GCR_RSTR0_PRST_RESET                       \
+	 << MXC_F_GCR_RSTR0_PRST_POS) /**<                \
+					 RSTR0_PRST_RESET \
+					 Setting */
+#define MXC_V_GCR_RSTR0_PRST_RESET_DONE \
 	((uint32_t)0x0UL) /**< RSTR0_PRST_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_PRST_RESET_DONE                                        \
-	(MXC_V_GCR_RSTR0_PRST_RESET_DONE                                       \
-	 << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR0_PRST_BUSY                                              \
+#define MXC_S_GCR_RSTR0_PRST_RESET_DONE                        \
+	(MXC_V_GCR_RSTR0_PRST_RESET_DONE                       \
+	 << MXC_F_GCR_RSTR0_PRST_POS) /**<                     \
+					 RSTR0_PRST_RESET_DONE \
+					 Setting               \
+				       */
+#define MXC_V_GCR_RSTR0_PRST_BUSY \
 	((uint32_t)0x1UL) /**< RSTR0_PRST_BUSY Value */
-#define MXC_S_GCR_RSTR0_PRST_BUSY                                              \
-	(MXC_V_GCR_RSTR0_PRST_BUSY                                             \
-	 << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_BUSY Setting */
+#define MXC_S_GCR_RSTR0_PRST_BUSY                        \
+	(MXC_V_GCR_RSTR0_PRST_BUSY                       \
+	 << MXC_F_GCR_RSTR0_PRST_POS) /**<               \
+					 RSTR0_PRST_BUSY \
+					 Setting */
 
 #define MXC_F_GCR_RSTR0_SYSTEM_POS 31 /**< RSTR0_SYSTEM Position */
-#define MXC_F_GCR_RSTR0_SYSTEM                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_RSTR0_SYSTEM_POS)) /**< RSTR0_SYSTEM Mask */
-#define MXC_V_GCR_RSTR0_SYSTEM_RFU                                             \
+#define MXC_F_GCR_RSTR0_SYSTEM                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SYSTEM_POS)) /**< RSTR0_SYSTEM \
+							     Mask */
+#define MXC_V_GCR_RSTR0_SYSTEM_RFU \
 	((uint32_t)0x0UL) /**< RSTR0_SYSTEM_RFU Value */
-#define MXC_S_GCR_RSTR0_SYSTEM_RFU                                             \
-	(MXC_V_GCR_RSTR0_SYSTEM_RFU                                            \
-	 << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_RFU Setting */
-#define MXC_V_GCR_RSTR0_SYSTEM_RESET                                           \
+#define MXC_S_GCR_RSTR0_SYSTEM_RFU                          \
+	(MXC_V_GCR_RSTR0_SYSTEM_RFU                         \
+	 << MXC_F_GCR_RSTR0_SYSTEM_POS) /**<                \
+					   RSTR0_SYSTEM_RFU \
+					   Setting          \
+					 */
+#define MXC_V_GCR_RSTR0_SYSTEM_RESET \
 	((uint32_t)0x1UL) /**< RSTR0_SYSTEM_RESET Value */
-#define MXC_S_GCR_RSTR0_SYSTEM_RESET                                           \
-	(MXC_V_GCR_RSTR0_SYSTEM_RESET                                          \
-	 << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_RESET Setting */
-#define MXC_V_GCR_RSTR0_SYSTEM_RESET_DONE                                      \
+#define MXC_S_GCR_RSTR0_SYSTEM_RESET                          \
+	(MXC_V_GCR_RSTR0_SYSTEM_RESET                         \
+	 << MXC_F_GCR_RSTR0_SYSTEM_POS) /**<                  \
+					   RSTR0_SYSTEM_RESET \
+					   Setting            \
+					 */
+#define MXC_V_GCR_RSTR0_SYSTEM_RESET_DONE \
 	((uint32_t)0x0UL) /**< RSTR0_SYSTEM_RESET_DONE Value */
-#define MXC_S_GCR_RSTR0_SYSTEM_RESET_DONE                                      \
-	(MXC_V_GCR_RSTR0_SYSTEM_RESET_DONE                                     \
-	 << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_RESET_DONE Setting   \
+#define MXC_S_GCR_RSTR0_SYSTEM_RESET_DONE                                    \
+	(MXC_V_GCR_RSTR0_SYSTEM_RESET_DONE                                   \
+	 << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_RESET_DONE Setting \
 					 */
-#define MXC_V_GCR_RSTR0_SYSTEM_BUSY                                            \
+#define MXC_V_GCR_RSTR0_SYSTEM_BUSY \
 	((uint32_t)0x1UL) /**< RSTR0_SYSTEM_BUSY Value */
-#define MXC_S_GCR_RSTR0_SYSTEM_BUSY                                            \
-	(MXC_V_GCR_RSTR0_SYSTEM_BUSY                                           \
-	 << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_BUSY Setting */
+#define MXC_S_GCR_RSTR0_SYSTEM_BUSY                          \
+	(MXC_V_GCR_RSTR0_SYSTEM_BUSY                         \
+	 << MXC_F_GCR_RSTR0_SYSTEM_POS) /**<                 \
+					   RSTR0_SYSTEM_BUSY \
+					   Setting           \
+					 */
 
 /**
  * Clock Control.
  */
 #define MXC_F_GCR_CLKCN_PSC_POS 6 /**< CLKCN_PSC Position */
-#define MXC_F_GCR_CLKCN_PSC                                                    \
+#define MXC_F_GCR_CLKCN_PSC \
 	((uint32_t)(0x7UL << MXC_F_GCR_CLKCN_PSC_POS)) /**< CLKCN_PSC Mask */
-#define MXC_V_GCR_CLKCN_PSC_DIV1                                               \
-	((uint32_t)0x0UL) /**< CLKCN_PSC_DIV1 Value                            \
+#define MXC_V_GCR_CLKCN_PSC_DIV1                    \
+	((uint32_t)0x0UL) /**< CLKCN_PSC_DIV1 Value \
 			   */
-#define MXC_S_GCR_CLKCN_PSC_DIV1                                               \
-	(MXC_V_GCR_CLKCN_PSC_DIV1                                              \
-	 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV1 Setting */
-#define MXC_V_GCR_CLKCN_PSC_DIV2                                               \
-	((uint32_t)0x1UL) /**< CLKCN_PSC_DIV2 Value                            \
+#define MXC_S_GCR_CLKCN_PSC_DIV1                       \
+	(MXC_V_GCR_CLKCN_PSC_DIV1                      \
+	 << MXC_F_GCR_CLKCN_PSC_POS) /**<              \
+					CLKCN_PSC_DIV1 \
+					Setting */
+#define MXC_V_GCR_CLKCN_PSC_DIV2                    \
+	((uint32_t)0x1UL) /**< CLKCN_PSC_DIV2 Value \
 			   */
-#define MXC_S_GCR_CLKCN_PSC_DIV2                                               \
-	(MXC_V_GCR_CLKCN_PSC_DIV2                                              \
-	 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV2 Setting */
-#define MXC_V_GCR_CLKCN_PSC_DIV4                                               \
-	((uint32_t)0x2UL) /**< CLKCN_PSC_DIV4 Value                            \
+#define MXC_S_GCR_CLKCN_PSC_DIV2                       \
+	(MXC_V_GCR_CLKCN_PSC_DIV2                      \
+	 << MXC_F_GCR_CLKCN_PSC_POS) /**<              \
+					CLKCN_PSC_DIV2 \
+					Setting */
+#define MXC_V_GCR_CLKCN_PSC_DIV4                    \
+	((uint32_t)0x2UL) /**< CLKCN_PSC_DIV4 Value \
 			   */
-#define MXC_S_GCR_CLKCN_PSC_DIV4                                               \
-	(MXC_V_GCR_CLKCN_PSC_DIV4                                              \
-	 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV4 Setting */
-#define MXC_V_GCR_CLKCN_PSC_DIV8                                               \
-	((uint32_t)0x3UL) /**< CLKCN_PSC_DIV8 Value                            \
+#define MXC_S_GCR_CLKCN_PSC_DIV4                       \
+	(MXC_V_GCR_CLKCN_PSC_DIV4                      \
+	 << MXC_F_GCR_CLKCN_PSC_POS) /**<              \
+					CLKCN_PSC_DIV4 \
+					Setting */
+#define MXC_V_GCR_CLKCN_PSC_DIV8                    \
+	((uint32_t)0x3UL) /**< CLKCN_PSC_DIV8 Value \
 			   */
-#define MXC_S_GCR_CLKCN_PSC_DIV8                                               \
-	(MXC_V_GCR_CLKCN_PSC_DIV8                                              \
-	 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV8 Setting */
-#define MXC_V_GCR_CLKCN_PSC_DIV16                                              \
+#define MXC_S_GCR_CLKCN_PSC_DIV8                       \
+	(MXC_V_GCR_CLKCN_PSC_DIV8                      \
+	 << MXC_F_GCR_CLKCN_PSC_POS) /**<              \
+					CLKCN_PSC_DIV8 \
+					Setting */
+#define MXC_V_GCR_CLKCN_PSC_DIV16 \
 	((uint32_t)0x4UL) /**< CLKCN_PSC_DIV16 Value */
-#define MXC_S_GCR_CLKCN_PSC_DIV16                                              \
-	(MXC_V_GCR_CLKCN_PSC_DIV16                                             \
-	 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV16 Setting */
-#define MXC_V_GCR_CLKCN_PSC_DIV32                                              \
+#define MXC_S_GCR_CLKCN_PSC_DIV16                       \
+	(MXC_V_GCR_CLKCN_PSC_DIV16                      \
+	 << MXC_F_GCR_CLKCN_PSC_POS) /**<               \
+					CLKCN_PSC_DIV16 \
+					Setting */
+#define MXC_V_GCR_CLKCN_PSC_DIV32 \
 	((uint32_t)0x5UL) /**< CLKCN_PSC_DIV32 Value */
-#define MXC_S_GCR_CLKCN_PSC_DIV32                                              \
-	(MXC_V_GCR_CLKCN_PSC_DIV32                                             \
-	 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV32 Setting */
-#define MXC_V_GCR_CLKCN_PSC_DIV64                                              \
+#define MXC_S_GCR_CLKCN_PSC_DIV32                       \
+	(MXC_V_GCR_CLKCN_PSC_DIV32                      \
+	 << MXC_F_GCR_CLKCN_PSC_POS) /**<               \
+					CLKCN_PSC_DIV32 \
+					Setting */
+#define MXC_V_GCR_CLKCN_PSC_DIV64 \
 	((uint32_t)0x6UL) /**< CLKCN_PSC_DIV64 Value */
-#define MXC_S_GCR_CLKCN_PSC_DIV64                                              \
-	(MXC_V_GCR_CLKCN_PSC_DIV64                                             \
-	 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV64 Setting */
-#define MXC_V_GCR_CLKCN_PSC_DIV128                                             \
+#define MXC_S_GCR_CLKCN_PSC_DIV64                       \
+	(MXC_V_GCR_CLKCN_PSC_DIV64                      \
+	 << MXC_F_GCR_CLKCN_PSC_POS) /**<               \
+					CLKCN_PSC_DIV64 \
+					Setting */
+#define MXC_V_GCR_CLKCN_PSC_DIV128 \
 	((uint32_t)0x7UL) /**< CLKCN_PSC_DIV128 Value */
-#define MXC_S_GCR_CLKCN_PSC_DIV128                                             \
-	(MXC_V_GCR_CLKCN_PSC_DIV128                                            \
-	 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV128 Setting */
+#define MXC_S_GCR_CLKCN_PSC_DIV128                       \
+	(MXC_V_GCR_CLKCN_PSC_DIV128                      \
+	 << MXC_F_GCR_CLKCN_PSC_POS) /**<                \
+					CLKCN_PSC_DIV128 \
+					Setting */
 
 #define MXC_F_GCR_CLKCN_CLKSEL_POS 9 /**< CLKCN_CLKSEL Position */
-#define MXC_F_GCR_CLKCN_CLKSEL                                                 \
-	((uint32_t)(0x7UL                                                      \
-		    << MXC_F_GCR_CLKCN_CLKSEL_POS)) /**< CLKCN_CLKSEL Mask */
-#define MXC_V_GCR_CLKCN_CLKSEL_HIRC                                            \
+#define MXC_F_GCR_CLKCN_CLKSEL                                              \
+	((uint32_t)(0x7UL << MXC_F_GCR_CLKCN_CLKSEL_POS)) /**< CLKCN_CLKSEL \
+							     Mask */
+#define MXC_V_GCR_CLKCN_CLKSEL_HIRC \
 	((uint32_t)0x0UL) /**< CLKCN_CLKSEL_HIRC Value */
-#define MXC_S_GCR_CLKCN_CLKSEL_HIRC                                            \
-	(MXC_V_GCR_CLKCN_CLKSEL_HIRC                                           \
-	 << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_HIRC Setting */
-#define MXC_V_GCR_CLKCN_CLKSEL_NANORING                                        \
+#define MXC_S_GCR_CLKCN_CLKSEL_HIRC                          \
+	(MXC_V_GCR_CLKCN_CLKSEL_HIRC                         \
+	 << MXC_F_GCR_CLKCN_CLKSEL_POS) /**<                 \
+					   CLKCN_CLKSEL_HIRC \
+					   Setting           \
+					 */
+#define MXC_V_GCR_CLKCN_CLKSEL_NANORING \
 	((uint32_t)0x3UL) /**< CLKCN_CLKSEL_NANORING Value */
-#define MXC_S_GCR_CLKCN_CLKSEL_NANORING                                        \
-	(MXC_V_GCR_CLKCN_CLKSEL_NANORING                                       \
-	 << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_NANORING Setting */
-#define MXC_V_GCR_CLKCN_CLKSEL_HFXIN                                           \
+#define MXC_S_GCR_CLKCN_CLKSEL_NANORING                          \
+	(MXC_V_GCR_CLKCN_CLKSEL_NANORING                         \
+	 << MXC_F_GCR_CLKCN_CLKSEL_POS) /**<                     \
+					   CLKCN_CLKSEL_NANORING \
+					   Setting               \
+					 */
+#define MXC_V_GCR_CLKCN_CLKSEL_HFXIN \
 	((uint32_t)0x6UL) /**< CLKCN_CLKSEL_HFXIN Value */
-#define MXC_S_GCR_CLKCN_CLKSEL_HFXIN                                           \
-	(MXC_V_GCR_CLKCN_CLKSEL_HFXIN                                          \
-	 << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_HFXIN Setting */
+#define MXC_S_GCR_CLKCN_CLKSEL_HFXIN                          \
+	(MXC_V_GCR_CLKCN_CLKSEL_HFXIN                         \
+	 << MXC_F_GCR_CLKCN_CLKSEL_POS) /**<                  \
+					   CLKCN_CLKSEL_HFXIN \
+					   Setting            \
+					 */
 
 #define MXC_F_GCR_CLKCN_CKRDY_POS 13 /**< CLKCN_CKRDY Position */
 #define MXC_F_GCR_CLKCN_CKRDY                                                  \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_GCR_CLKCN_CKRDY_POS)) /**< CLKCN_CKRDY Mask */
-#define MXC_V_GCR_CLKCN_CKRDY_BUSY                                             \
+	((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_CKRDY_POS)) /**< CLKCN_CKRDY Mask \
+							  */
+#define MXC_V_GCR_CLKCN_CKRDY_BUSY \
 	((uint32_t)0x0UL) /**< CLKCN_CKRDY_BUSY Value */
-#define MXC_S_GCR_CLKCN_CKRDY_BUSY                                             \
-	(MXC_V_GCR_CLKCN_CKRDY_BUSY                                            \
-	 << MXC_F_GCR_CLKCN_CKRDY_POS) /**< CLKCN_CKRDY_BUSY Setting */
-#define MXC_V_GCR_CLKCN_CKRDY_READY                                            \
+#define MXC_S_GCR_CLKCN_CKRDY_BUSY                         \
+	(MXC_V_GCR_CLKCN_CKRDY_BUSY                        \
+	 << MXC_F_GCR_CLKCN_CKRDY_POS) /**<                \
+					  CLKCN_CKRDY_BUSY \
+					  Setting          \
+					*/
+#define MXC_V_GCR_CLKCN_CKRDY_READY \
 	((uint32_t)0x1UL) /**< CLKCN_CKRDY_READY Value */
-#define MXC_S_GCR_CLKCN_CKRDY_READY                                            \
-	(MXC_V_GCR_CLKCN_CKRDY_READY                                           \
-	 << MXC_F_GCR_CLKCN_CKRDY_POS) /**< CLKCN_CKRDY_READY Setting */
+#define MXC_S_GCR_CLKCN_CKRDY_READY                         \
+	(MXC_V_GCR_CLKCN_CKRDY_READY                        \
+	 << MXC_F_GCR_CLKCN_CKRDY_POS) /**<                 \
+					  CLKCN_CKRDY_READY \
+					  Setting           \
+					*/
 
 #define MXC_F_GCR_CLKCN_X32K_EN_POS 17 /**< CLKCN_X32K_EN Position */
-#define MXC_F_GCR_CLKCN_X32K_EN                                                \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_CLKCN_X32K_EN_POS)) /**< CLKCN_X32K_EN Mask */
-#define MXC_V_GCR_CLKCN_X32K_EN_DIS                                            \
+#define MXC_F_GCR_CLKCN_X32K_EN                                               \
+	((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_X32K_EN_POS)) /**< CLKCN_X32K_EN \
+							      Mask */
+#define MXC_V_GCR_CLKCN_X32K_EN_DIS \
 	((uint32_t)0x0UL) /**< CLKCN_X32K_EN_DIS Value */
-#define MXC_S_GCR_CLKCN_X32K_EN_DIS                                            \
-	(MXC_V_GCR_CLKCN_X32K_EN_DIS                                           \
-	 << MXC_F_GCR_CLKCN_X32K_EN_POS) /**< CLKCN_X32K_EN_DIS Setting */
-#define MXC_V_GCR_CLKCN_X32K_EN_EN                                             \
+#define MXC_S_GCR_CLKCN_X32K_EN_DIS                           \
+	(MXC_V_GCR_CLKCN_X32K_EN_DIS                          \
+	 << MXC_F_GCR_CLKCN_X32K_EN_POS) /**<                 \
+					    CLKCN_X32K_EN_DIS \
+					    Setting           \
+					  */
+#define MXC_V_GCR_CLKCN_X32K_EN_EN \
 	((uint32_t)0x1UL) /**< CLKCN_X32K_EN_EN Value */
-#define MXC_S_GCR_CLKCN_X32K_EN_EN                                             \
-	(MXC_V_GCR_CLKCN_X32K_EN_EN                                            \
-	 << MXC_F_GCR_CLKCN_X32K_EN_POS) /**< CLKCN_X32K_EN_EN Setting */
+#define MXC_S_GCR_CLKCN_X32K_EN_EN                           \
+	(MXC_V_GCR_CLKCN_X32K_EN_EN                          \
+	 << MXC_F_GCR_CLKCN_X32K_EN_POS) /**<                \
+					    CLKCN_X32K_EN_EN \
+					    Setting          \
+					  */
 
 #define MXC_F_GCR_CLKCN_HIRC_EN_POS 18 /**< CLKCN_HIRC_EN Position */
-#define MXC_F_GCR_CLKCN_HIRC_EN                                                \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_CLKCN_HIRC_EN_POS)) /**< CLKCN_HIRC_EN Mask */
-#define MXC_V_GCR_CLKCN_HIRC_EN_DIS                                            \
+#define MXC_F_GCR_CLKCN_HIRC_EN                                               \
+	((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC_EN_POS)) /**< CLKCN_HIRC_EN \
+							      Mask */
+#define MXC_V_GCR_CLKCN_HIRC_EN_DIS \
 	((uint32_t)0x0UL) /**< CLKCN_HIRC_EN_DIS Value */
-#define MXC_S_GCR_CLKCN_HIRC_EN_DIS                                            \
-	(MXC_V_GCR_CLKCN_HIRC_EN_DIS                                           \
-	 << MXC_F_GCR_CLKCN_HIRC_EN_POS) /**< CLKCN_HIRC_EN_DIS Setting */
-#define MXC_V_GCR_CLKCN_HIRC_EN_EN                                             \
+#define MXC_S_GCR_CLKCN_HIRC_EN_DIS                           \
+	(MXC_V_GCR_CLKCN_HIRC_EN_DIS                          \
+	 << MXC_F_GCR_CLKCN_HIRC_EN_POS) /**<                 \
+					    CLKCN_HIRC_EN_DIS \
+					    Setting           \
+					  */
+#define MXC_V_GCR_CLKCN_HIRC_EN_EN \
 	((uint32_t)0x1UL) /**< CLKCN_HIRC_EN_EN Value */
-#define MXC_S_GCR_CLKCN_HIRC_EN_EN                                             \
-	(MXC_V_GCR_CLKCN_HIRC_EN_EN                                            \
-	 << MXC_F_GCR_CLKCN_HIRC_EN_POS) /**< CLKCN_HIRC_EN_EN Setting */
+#define MXC_S_GCR_CLKCN_HIRC_EN_EN                           \
+	(MXC_V_GCR_CLKCN_HIRC_EN_EN                          \
+	 << MXC_F_GCR_CLKCN_HIRC_EN_POS) /**<                \
+					    CLKCN_HIRC_EN_EN \
+					    Setting          \
+					  */
 
 #define MXC_F_GCR_CLKCN_X32K_RDY_POS 25 /**< CLKCN_X32K_RDY Position */
-#define MXC_F_GCR_CLKCN_X32K_RDY                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_CLKCN_X32K_RDY_POS)) /**< CLKCN_X32K_RDY Mask */
-#define MXC_V_GCR_CLKCN_X32K_RDY_NOT                                           \
+#define MXC_F_GCR_CLKCN_X32K_RDY                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_X32K_RDY_POS)) /**<              \
+							       CLKCN_X32K_RDY \
+							       Mask */
+#define MXC_V_GCR_CLKCN_X32K_RDY_NOT \
 	((uint32_t)0x0UL) /**< CLKCN_X32K_RDY_NOT Value */
-#define MXC_S_GCR_CLKCN_X32K_RDY_NOT                                           \
-	(MXC_V_GCR_CLKCN_X32K_RDY_NOT                                          \
-	 << MXC_F_GCR_CLKCN_X32K_RDY_POS) /**< CLKCN_X32K_RDY_NOT Setting */
-#define MXC_V_GCR_CLKCN_X32K_RDY_READY                                         \
+#define MXC_S_GCR_CLKCN_X32K_RDY_NOT                            \
+	(MXC_V_GCR_CLKCN_X32K_RDY_NOT                           \
+	 << MXC_F_GCR_CLKCN_X32K_RDY_POS) /**<                  \
+					     CLKCN_X32K_RDY_NOT \
+					     Setting            \
+					   */
+#define MXC_V_GCR_CLKCN_X32K_RDY_READY \
 	((uint32_t)0x1UL) /**< CLKCN_X32K_RDY_READY Value */
-#define MXC_S_GCR_CLKCN_X32K_RDY_READY                                         \
-	(MXC_V_GCR_CLKCN_X32K_RDY_READY                                        \
-	 << MXC_F_GCR_CLKCN_X32K_RDY_POS) /**< CLKCN_X32K_RDY_READY Setting */
+#define MXC_S_GCR_CLKCN_X32K_RDY_READY                            \
+	(MXC_V_GCR_CLKCN_X32K_RDY_READY                           \
+	 << MXC_F_GCR_CLKCN_X32K_RDY_POS) /**<                    \
+					     CLKCN_X32K_RDY_READY \
+					     Setting              \
+					   */
 
 #define MXC_F_GCR_CLKCN_HIRC_RDY_POS 26 /**< CLKCN_HIRC_RDY Position */
-#define MXC_F_GCR_CLKCN_HIRC_RDY                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_CLKCN_HIRC_RDY_POS)) /**< CLKCN_HIRC_RDY Mask */
-#define MXC_V_GCR_CLKCN_HIRC_RDY_NOT                                           \
+#define MXC_F_GCR_CLKCN_HIRC_RDY                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC_RDY_POS)) /**<              \
+							       CLKCN_HIRC_RDY \
+							       Mask */
+#define MXC_V_GCR_CLKCN_HIRC_RDY_NOT \
 	((uint32_t)0x0UL) /**< CLKCN_HIRC_RDY_NOT Value */
-#define MXC_S_GCR_CLKCN_HIRC_RDY_NOT                                           \
-	(MXC_V_GCR_CLKCN_HIRC_RDY_NOT                                          \
-	 << MXC_F_GCR_CLKCN_HIRC_RDY_POS) /**< CLKCN_HIRC_RDY_NOT Setting */
-#define MXC_V_GCR_CLKCN_HIRC_RDY_READY                                         \
+#define MXC_S_GCR_CLKCN_HIRC_RDY_NOT                            \
+	(MXC_V_GCR_CLKCN_HIRC_RDY_NOT                           \
+	 << MXC_F_GCR_CLKCN_HIRC_RDY_POS) /**<                  \
+					     CLKCN_HIRC_RDY_NOT \
+					     Setting            \
+					   */
+#define MXC_V_GCR_CLKCN_HIRC_RDY_READY \
 	((uint32_t)0x1UL) /**< CLKCN_HIRC_RDY_READY Value */
-#define MXC_S_GCR_CLKCN_HIRC_RDY_READY                                         \
-	(MXC_V_GCR_CLKCN_HIRC_RDY_READY                                        \
-	 << MXC_F_GCR_CLKCN_HIRC_RDY_POS) /**< CLKCN_HIRC_RDY_READY Setting */
+#define MXC_S_GCR_CLKCN_HIRC_RDY_READY                            \
+	(MXC_V_GCR_CLKCN_HIRC_RDY_READY                           \
+	 << MXC_F_GCR_CLKCN_HIRC_RDY_POS) /**<                    \
+					     CLKCN_HIRC_RDY_READY \
+					     Setting              \
+					   */
 
 #define MXC_F_GCR_CLKCN_LIRC8K_RDY_POS 29 /**< CLKCN_LIRC8K_RDY Position */
-#define MXC_F_GCR_CLKCN_LIRC8K_RDY                                             \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS)) /**< CLKCN_LIRC8K_RDY  \
+#define MXC_F_GCR_CLKCN_LIRC8K_RDY                                            \
+	((uint32_t)(0x1UL                                                     \
+		    << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS)) /**< CLKCN_LIRC8K_RDY \
 							   Mask */
-#define MXC_V_GCR_CLKCN_LIRC8K_RDY_NOT                                         \
+#define MXC_V_GCR_CLKCN_LIRC8K_RDY_NOT \
 	((uint32_t)0x0UL) /**< CLKCN_LIRC8K_RDY_NOT Value */
-#define MXC_S_GCR_CLKCN_LIRC8K_RDY_NOT                                         \
-	(MXC_V_GCR_CLKCN_LIRC8K_RDY_NOT                                        \
-	 << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS) /**< CLKCN_LIRC8K_RDY_NOT Setting  \
+#define MXC_S_GCR_CLKCN_LIRC8K_RDY_NOT                                        \
+	(MXC_V_GCR_CLKCN_LIRC8K_RDY_NOT                                       \
+	 << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS) /**< CLKCN_LIRC8K_RDY_NOT Setting \
 					     */
-#define MXC_V_GCR_CLKCN_LIRC8K_RDY_READY                                       \
+#define MXC_V_GCR_CLKCN_LIRC8K_RDY_READY \
 	((uint32_t)0x1UL) /**< CLKCN_LIRC8K_RDY_READY Value */
-#define MXC_S_GCR_CLKCN_LIRC8K_RDY_READY                                       \
-	(MXC_V_GCR_CLKCN_LIRC8K_RDY_READY                                      \
-	 << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS) /**< CLKCN_LIRC8K_RDY_READY        \
+#define MXC_S_GCR_CLKCN_LIRC8K_RDY_READY                                \
+	(MXC_V_GCR_CLKCN_LIRC8K_RDY_READY                               \
+	 << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS) /**< CLKCN_LIRC8K_RDY_READY \
 					       Setting */
 
 /**
  * Power Management.
  */
 #define MXC_F_GCR_PM_MODE_POS 0 /**< PM_MODE Position */
-#define MXC_F_GCR_PM_MODE                                                      \
+#define MXC_F_GCR_PM_MODE \
 	((uint32_t)(0x7UL << MXC_F_GCR_PM_MODE_POS)) /**< PM_MODE Mask */
-#define MXC_V_GCR_PM_MODE_ACTIVE                                               \
-	((uint32_t)0x0UL) /**< PM_MODE_ACTIVE Value                            \
+#define MXC_V_GCR_PM_MODE_ACTIVE                    \
+	((uint32_t)0x0UL) /**< PM_MODE_ACTIVE Value \
 			   */
-#define MXC_S_GCR_PM_MODE_ACTIVE                                               \
-	(MXC_V_GCR_PM_MODE_ACTIVE                                              \
-	 << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_ACTIVE Setting */
-#define MXC_V_GCR_PM_MODE_SHUTDOWN                                             \
+#define MXC_S_GCR_PM_MODE_ACTIVE                                              \
+	(MXC_V_GCR_PM_MODE_ACTIVE << MXC_F_GCR_PM_MODE_POS) /**<              \
+							       PM_MODE_ACTIVE \
+							       Setting */
+#define MXC_V_GCR_PM_MODE_SHUTDOWN \
 	((uint32_t)0x3UL) /**< PM_MODE_SHUTDOWN Value */
-#define MXC_S_GCR_PM_MODE_SHUTDOWN                                             \
-	(MXC_V_GCR_PM_MODE_SHUTDOWN                                            \
-	 << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_SHUTDOWN Setting */
-#define MXC_V_GCR_PM_MODE_BACKUP                                               \
-	((uint32_t)0x4UL) /**< PM_MODE_BACKUP Value                            \
+#define MXC_S_GCR_PM_MODE_SHUTDOWN                     \
+	(MXC_V_GCR_PM_MODE_SHUTDOWN                    \
+	 << MXC_F_GCR_PM_MODE_POS) /**<                \
+				      PM_MODE_SHUTDOWN \
+				      Setting */
+#define MXC_V_GCR_PM_MODE_BACKUP                    \
+	((uint32_t)0x4UL) /**< PM_MODE_BACKUP Value \
 			   */
-#define MXC_S_GCR_PM_MODE_BACKUP                                               \
-	(MXC_V_GCR_PM_MODE_BACKUP                                              \
-	 << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_BACKUP Setting */
+#define MXC_S_GCR_PM_MODE_BACKUP                                              \
+	(MXC_V_GCR_PM_MODE_BACKUP << MXC_F_GCR_PM_MODE_POS) /**<              \
+							       PM_MODE_BACKUP \
+							       Setting */
 
 #define MXC_F_GCR_PM_GPIOWKEN_POS 4 /**< PM_GPIOWKEN Position */
 #define MXC_F_GCR_PM_GPIOWKEN                                                  \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_GCR_PM_GPIOWKEN_POS)) /**< PM_GPIOWKEN Mask */
-#define MXC_V_GCR_PM_GPIOWKEN_DIS                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_PM_GPIOWKEN_POS)) /**< PM_GPIOWKEN Mask \
+							  */
+#define MXC_V_GCR_PM_GPIOWKEN_DIS \
 	((uint32_t)0x0UL) /**< PM_GPIOWKEN_DIS Value */
-#define MXC_S_GCR_PM_GPIOWKEN_DIS                                              \
-	(MXC_V_GCR_PM_GPIOWKEN_DIS                                             \
-	 << MXC_F_GCR_PM_GPIOWKEN_POS) /**< PM_GPIOWKEN_DIS Setting */
-#define MXC_V_GCR_PM_GPIOWKEN_EN                                               \
-	((uint32_t)0x1UL) /**< PM_GPIOWKEN_EN Value                            \
+#define MXC_S_GCR_PM_GPIOWKEN_DIS                         \
+	(MXC_V_GCR_PM_GPIOWKEN_DIS                        \
+	 << MXC_F_GCR_PM_GPIOWKEN_POS) /**<               \
+					  PM_GPIOWKEN_DIS \
+					  Setting */
+#define MXC_V_GCR_PM_GPIOWKEN_EN                    \
+	((uint32_t)0x1UL) /**< PM_GPIOWKEN_EN Value \
 			   */
-#define MXC_S_GCR_PM_GPIOWKEN_EN                                               \
-	(MXC_V_GCR_PM_GPIOWKEN_EN                                              \
-	 << MXC_F_GCR_PM_GPIOWKEN_POS) /**< PM_GPIOWKEN_EN Setting */
+#define MXC_S_GCR_PM_GPIOWKEN_EN                         \
+	(MXC_V_GCR_PM_GPIOWKEN_EN                        \
+	 << MXC_F_GCR_PM_GPIOWKEN_POS) /**<              \
+					  PM_GPIOWKEN_EN \
+					  Setting */
 
 #define MXC_F_GCR_PM_RTCWKEN_POS 5 /**< PM_RTCWKEN Position */
-#define MXC_F_GCR_PM_RTCWKEN                                                   \
-	((uint32_t)(0x1UL << MXC_F_GCR_PM_RTCWKEN_POS)) /**< PM_RTCWKEN Mask   \
+#define MXC_F_GCR_PM_RTCWKEN                                                 \
+	((uint32_t)(0x1UL << MXC_F_GCR_PM_RTCWKEN_POS)) /**< PM_RTCWKEN Mask \
 							 */
-#define MXC_V_GCR_PM_RTCWKEN_DIS                                               \
-	((uint32_t)0x0UL) /**< PM_RTCWKEN_DIS Value                            \
+#define MXC_V_GCR_PM_RTCWKEN_DIS                    \
+	((uint32_t)0x0UL) /**< PM_RTCWKEN_DIS Value \
 			   */
-#define MXC_S_GCR_PM_RTCWKEN_DIS                                               \
-	(MXC_V_GCR_PM_RTCWKEN_DIS                                              \
-	 << MXC_F_GCR_PM_RTCWKEN_POS)		  /**< PM_RTCWKEN_DIS Setting */
+#define MXC_S_GCR_PM_RTCWKEN_DIS                        \
+	(MXC_V_GCR_PM_RTCWKEN_DIS                       \
+	 << MXC_F_GCR_PM_RTCWKEN_POS) /**<              \
+					 PM_RTCWKEN_DIS \
+					 Setting */
 #define MXC_V_GCR_PM_RTCWKEN_EN ((uint32_t)0x1UL) /**< PM_RTCWKEN_EN Value */
 #define MXC_S_GCR_PM_RTCWKEN_EN                                                \
-	(MXC_V_GCR_PM_RTCWKEN_EN                                               \
-	 << MXC_F_GCR_PM_RTCWKEN_POS) /**< PM_RTCWKEN_EN Setting */
+	(MXC_V_GCR_PM_RTCWKEN_EN << MXC_F_GCR_PM_RTCWKEN_POS) /**<             \
+								 PM_RTCWKEN_EN \
+								 Setting */
 
 #define MXC_F_GCR_PM_HIRCPD_POS 15 /**< PM_HIRCPD Position */
-#define MXC_F_GCR_PM_HIRCPD                                                    \
+#define MXC_F_GCR_PM_HIRCPD \
 	((uint32_t)(0x1UL << MXC_F_GCR_PM_HIRCPD_POS)) /**< PM_HIRCPD Mask */
-#define MXC_V_GCR_PM_HIRCPD_ACTIVE                                             \
+#define MXC_V_GCR_PM_HIRCPD_ACTIVE \
 	((uint32_t)0x0UL) /**< PM_HIRCPD_ACTIVE Value */
-#define MXC_S_GCR_PM_HIRCPD_ACTIVE                                             \
-	(MXC_V_GCR_PM_HIRCPD_ACTIVE                                            \
-	 << MXC_F_GCR_PM_HIRCPD_POS) /**< PM_HIRCPD_ACTIVE Setting */
-#define MXC_V_GCR_PM_HIRCPD_DEEPSLEEP                                          \
+#define MXC_S_GCR_PM_HIRCPD_ACTIVE                       \
+	(MXC_V_GCR_PM_HIRCPD_ACTIVE                      \
+	 << MXC_F_GCR_PM_HIRCPD_POS) /**<                \
+					PM_HIRCPD_ACTIVE \
+					Setting */
+#define MXC_V_GCR_PM_HIRCPD_DEEPSLEEP \
 	((uint32_t)0x1UL) /**< PM_HIRCPD_DEEPSLEEP Value */
-#define MXC_S_GCR_PM_HIRCPD_DEEPSLEEP                                          \
-	(MXC_V_GCR_PM_HIRCPD_DEEPSLEEP                                         \
-	 << MXC_F_GCR_PM_HIRCPD_POS) /**< PM_HIRCPD_DEEPSLEEP Setting */
+#define MXC_S_GCR_PM_HIRCPD_DEEPSLEEP                       \
+	(MXC_V_GCR_PM_HIRCPD_DEEPSLEEP                      \
+	 << MXC_F_GCR_PM_HIRCPD_POS) /**<                   \
+					PM_HIRCPD_DEEPSLEEP \
+					Setting             \
+				      */
 
 /**
  * Peripheral Clock Divider.
  */
 #define MXC_F_GCR_PCKDIV_AONCD_POS 0 /**< PCKDIV_AONCD Position */
-#define MXC_F_GCR_PCKDIV_AONCD                                                 \
-	((uint32_t)(0x3UL                                                      \
-		    << MXC_F_GCR_PCKDIV_AONCD_POS)) /**< PCKDIV_AONCD Mask */
-#define MXC_V_GCR_PCKDIV_AONCD_DIV_4                                           \
+#define MXC_F_GCR_PCKDIV_AONCD                                              \
+	((uint32_t)(0x3UL << MXC_F_GCR_PCKDIV_AONCD_POS)) /**< PCKDIV_AONCD \
+							     Mask */
+#define MXC_V_GCR_PCKDIV_AONCD_DIV_4 \
 	((uint32_t)0x0UL) /**< PCKDIV_AONCD_DIV_4 Value */
-#define MXC_S_GCR_PCKDIV_AONCD_DIV_4                                           \
-	(MXC_V_GCR_PCKDIV_AONCD_DIV_4                                          \
-	 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_4 Setting */
-#define MXC_V_GCR_PCKDIV_AONCD_DIV_8                                           \
+#define MXC_S_GCR_PCKDIV_AONCD_DIV_4                          \
+	(MXC_V_GCR_PCKDIV_AONCD_DIV_4                         \
+	 << MXC_F_GCR_PCKDIV_AONCD_POS) /**<                  \
+					   PCKDIV_AONCD_DIV_4 \
+					   Setting            \
+					 */
+#define MXC_V_GCR_PCKDIV_AONCD_DIV_8 \
 	((uint32_t)0x1UL) /**< PCKDIV_AONCD_DIV_8 Value */
-#define MXC_S_GCR_PCKDIV_AONCD_DIV_8                                           \
-	(MXC_V_GCR_PCKDIV_AONCD_DIV_8                                          \
-	 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_8 Setting */
-#define MXC_V_GCR_PCKDIV_AONCD_DIV_16                                          \
+#define MXC_S_GCR_PCKDIV_AONCD_DIV_8                          \
+	(MXC_V_GCR_PCKDIV_AONCD_DIV_8                         \
+	 << MXC_F_GCR_PCKDIV_AONCD_POS) /**<                  \
+					   PCKDIV_AONCD_DIV_8 \
+					   Setting            \
+					 */
+#define MXC_V_GCR_PCKDIV_AONCD_DIV_16 \
 	((uint32_t)0x2UL) /**< PCKDIV_AONCD_DIV_16 Value */
-#define MXC_S_GCR_PCKDIV_AONCD_DIV_16                                          \
-	(MXC_V_GCR_PCKDIV_AONCD_DIV_16                                         \
-	 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_16 Setting */
-#define MXC_V_GCR_PCKDIV_AONCD_DIV_32                                          \
+#define MXC_S_GCR_PCKDIV_AONCD_DIV_16                          \
+	(MXC_V_GCR_PCKDIV_AONCD_DIV_16                         \
+	 << MXC_F_GCR_PCKDIV_AONCD_POS) /**<                   \
+					   PCKDIV_AONCD_DIV_16 \
+					   Setting             \
+					 */
+#define MXC_V_GCR_PCKDIV_AONCD_DIV_32 \
 	((uint32_t)0x3UL) /**< PCKDIV_AONCD_DIV_32 Value */
-#define MXC_S_GCR_PCKDIV_AONCD_DIV_32                                          \
-	(MXC_V_GCR_PCKDIV_AONCD_DIV_32                                         \
-	 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_32 Setting */
+#define MXC_S_GCR_PCKDIV_AONCD_DIV_32                          \
+	(MXC_V_GCR_PCKDIV_AONCD_DIV_32                         \
+	 << MXC_F_GCR_PCKDIV_AONCD_POS) /**<                   \
+					   PCKDIV_AONCD_DIV_32 \
+					   Setting             \
+					 */
 
 /**
  * Peripheral Clock Disable.
  */
 #define MXC_F_GCR_PERCKCN0_GPIO0D_POS 0 /**< PERCKCN0_GPIO0D Position */
-#define MXC_F_GCR_PERCKCN0_GPIO0D                                              \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_GCR_PERCKCN0_GPIO0D_POS)) /**< PERCKCN0_GPIO0D  \
-							    Mask */
-#define MXC_V_GCR_PERCKCN0_GPIO0D_EN                                           \
+#define MXC_F_GCR_PERCKCN0_GPIO0D                                           \
+	((uint32_t)(0x1UL                                                   \
+		    << MXC_F_GCR_PERCKCN0_GPIO0D_POS)) /**< PERCKCN0_GPIO0D \
+							  Mask */
+#define MXC_V_GCR_PERCKCN0_GPIO0D_EN \
 	((uint32_t)0x0UL) /**< PERCKCN0_GPIO0D_EN Value */
-#define MXC_S_GCR_PERCKCN0_GPIO0D_EN                                           \
-	(MXC_V_GCR_PERCKCN0_GPIO0D_EN                                          \
-	 << MXC_F_GCR_PERCKCN0_GPIO0D_POS) /**< PERCKCN0_GPIO0D_EN Setting */
-#define MXC_V_GCR_PERCKCN0_GPIO0D_DIS                                          \
+#define MXC_S_GCR_PERCKCN0_GPIO0D_EN                             \
+	(MXC_V_GCR_PERCKCN0_GPIO0D_EN                            \
+	 << MXC_F_GCR_PERCKCN0_GPIO0D_POS) /**<                  \
+					      PERCKCN0_GPIO0D_EN \
+					      Setting            \
+					    */
+#define MXC_V_GCR_PERCKCN0_GPIO0D_DIS \
 	((uint32_t)0x1UL) /**< PERCKCN0_GPIO0D_DIS Value */
-#define MXC_S_GCR_PERCKCN0_GPIO0D_DIS                                          \
-	(MXC_V_GCR_PERCKCN0_GPIO0D_DIS                                         \
-	 << MXC_F_GCR_PERCKCN0_GPIO0D_POS) /**< PERCKCN0_GPIO0D_DIS Setting */
+#define MXC_S_GCR_PERCKCN0_GPIO0D_DIS                             \
+	(MXC_V_GCR_PERCKCN0_GPIO0D_DIS                            \
+	 << MXC_F_GCR_PERCKCN0_GPIO0D_POS) /**<                   \
+					      PERCKCN0_GPIO0D_DIS \
+					      Setting             \
+					    */
 
 #define MXC_F_GCR_PERCKCN0_DMAD_POS 5 /**< PERCKCN0_DMAD Position */
-#define MXC_F_GCR_PERCKCN0_DMAD                                                \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_PERCKCN0_DMAD_POS)) /**< PERCKCN0_DMAD Mask */
-#define MXC_V_GCR_PERCKCN0_DMAD_EN                                             \
+#define MXC_F_GCR_PERCKCN0_DMAD                                               \
+	((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_DMAD_POS)) /**< PERCKCN0_DMAD \
+							      Mask */
+#define MXC_V_GCR_PERCKCN0_DMAD_EN \
 	((uint32_t)0x0UL) /**< PERCKCN0_DMAD_EN Value */
-#define MXC_S_GCR_PERCKCN0_DMAD_EN                                             \
-	(MXC_V_GCR_PERCKCN0_DMAD_EN                                            \
-	 << MXC_F_GCR_PERCKCN0_DMAD_POS) /**< PERCKCN0_DMAD_EN Setting */
-#define MXC_V_GCR_PERCKCN0_DMAD_DIS                                            \
+#define MXC_S_GCR_PERCKCN0_DMAD_EN                           \
+	(MXC_V_GCR_PERCKCN0_DMAD_EN                          \
+	 << MXC_F_GCR_PERCKCN0_DMAD_POS) /**<                \
+					    PERCKCN0_DMAD_EN \
+					    Setting          \
+					  */
+#define MXC_V_GCR_PERCKCN0_DMAD_DIS \
 	((uint32_t)0x1UL) /**< PERCKCN0_DMAD_DIS Value */
-#define MXC_S_GCR_PERCKCN0_DMAD_DIS                                            \
-	(MXC_V_GCR_PERCKCN0_DMAD_DIS                                           \
-	 << MXC_F_GCR_PERCKCN0_DMAD_POS) /**< PERCKCN0_DMAD_DIS Setting */
+#define MXC_S_GCR_PERCKCN0_DMAD_DIS                           \
+	(MXC_V_GCR_PERCKCN0_DMAD_DIS                          \
+	 << MXC_F_GCR_PERCKCN0_DMAD_POS) /**<                 \
+					    PERCKCN0_DMAD_DIS \
+					    Setting           \
+					  */
 
 #define MXC_F_GCR_PERCKCN0_SPI0D_POS 6 /**< PERCKCN0_SPI0D Position */
-#define MXC_F_GCR_PERCKCN0_SPI0D                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_PERCKCN0_SPI0D_POS)) /**< PERCKCN0_SPI0D Mask */
-#define MXC_V_GCR_PERCKCN0_SPI0D_EN                                            \
+#define MXC_F_GCR_PERCKCN0_SPI0D                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_SPI0D_POS)) /**<              \
+							       PERCKCN0_SPI0D \
+							       Mask */
+#define MXC_V_GCR_PERCKCN0_SPI0D_EN \
 	((uint32_t)0x0UL) /**< PERCKCN0_SPI0D_EN Value */
-#define MXC_S_GCR_PERCKCN0_SPI0D_EN                                            \
-	(MXC_V_GCR_PERCKCN0_SPI0D_EN                                           \
-	 << MXC_F_GCR_PERCKCN0_SPI0D_POS) /**< PERCKCN0_SPI0D_EN Setting */
-#define MXC_V_GCR_PERCKCN0_SPI0D_DIS                                           \
+#define MXC_S_GCR_PERCKCN0_SPI0D_EN                            \
+	(MXC_V_GCR_PERCKCN0_SPI0D_EN                           \
+	 << MXC_F_GCR_PERCKCN0_SPI0D_POS) /**<                 \
+					     PERCKCN0_SPI0D_EN \
+					     Setting           \
+					   */
+#define MXC_V_GCR_PERCKCN0_SPI0D_DIS \
 	((uint32_t)0x1UL) /**< PERCKCN0_SPI0D_DIS Value */
-#define MXC_S_GCR_PERCKCN0_SPI0D_DIS                                           \
-	(MXC_V_GCR_PERCKCN0_SPI0D_DIS                                          \
-	 << MXC_F_GCR_PERCKCN0_SPI0D_POS) /**< PERCKCN0_SPI0D_DIS Setting */
+#define MXC_S_GCR_PERCKCN0_SPI0D_DIS                            \
+	(MXC_V_GCR_PERCKCN0_SPI0D_DIS                           \
+	 << MXC_F_GCR_PERCKCN0_SPI0D_POS) /**<                  \
+					     PERCKCN0_SPI0D_DIS \
+					     Setting            \
+					   */
 
 #define MXC_F_GCR_PERCKCN0_SPI1D_POS 7 /**< PERCKCN0_SPI1D Position */
-#define MXC_F_GCR_PERCKCN0_SPI1D                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_PERCKCN0_SPI1D_POS)) /**< PERCKCN0_SPI1D Mask */
-#define MXC_V_GCR_PERCKCN0_SPI1D_EN                                            \
+#define MXC_F_GCR_PERCKCN0_SPI1D                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_SPI1D_POS)) /**<              \
+							       PERCKCN0_SPI1D \
+							       Mask */
+#define MXC_V_GCR_PERCKCN0_SPI1D_EN \
 	((uint32_t)0x0UL) /**< PERCKCN0_SPI1D_EN Value */
-#define MXC_S_GCR_PERCKCN0_SPI1D_EN                                            \
-	(MXC_V_GCR_PERCKCN0_SPI1D_EN                                           \
-	 << MXC_F_GCR_PERCKCN0_SPI1D_POS) /**< PERCKCN0_SPI1D_EN Setting */
-#define MXC_V_GCR_PERCKCN0_SPI1D_DIS                                           \
+#define MXC_S_GCR_PERCKCN0_SPI1D_EN                            \
+	(MXC_V_GCR_PERCKCN0_SPI1D_EN                           \
+	 << MXC_F_GCR_PERCKCN0_SPI1D_POS) /**<                 \
+					     PERCKCN0_SPI1D_EN \
+					     Setting           \
+					   */
+#define MXC_V_GCR_PERCKCN0_SPI1D_DIS \
 	((uint32_t)0x1UL) /**< PERCKCN0_SPI1D_DIS Value */
-#define MXC_S_GCR_PERCKCN0_SPI1D_DIS                                           \
-	(MXC_V_GCR_PERCKCN0_SPI1D_DIS                                          \
-	 << MXC_F_GCR_PERCKCN0_SPI1D_POS) /**< PERCKCN0_SPI1D_DIS Setting */
+#define MXC_S_GCR_PERCKCN0_SPI1D_DIS                            \
+	(MXC_V_GCR_PERCKCN0_SPI1D_DIS                           \
+	 << MXC_F_GCR_PERCKCN0_SPI1D_POS) /**<                  \
+					     PERCKCN0_SPI1D_DIS \
+					     Setting            \
+					   */
 
 #define MXC_F_GCR_PERCKCN0_UART0D_POS 9 /**< PERCKCN0_UART0D Position */
-#define MXC_F_GCR_PERCKCN0_UART0D                                              \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_GCR_PERCKCN0_UART0D_POS)) /**< PERCKCN0_UART0D  \
-							    Mask */
-#define MXC_V_GCR_PERCKCN0_UART0D_EN                                           \
+#define MXC_F_GCR_PERCKCN0_UART0D                                           \
+	((uint32_t)(0x1UL                                                   \
+		    << MXC_F_GCR_PERCKCN0_UART0D_POS)) /**< PERCKCN0_UART0D \
+							  Mask */
+#define MXC_V_GCR_PERCKCN0_UART0D_EN \
 	((uint32_t)0x0UL) /**< PERCKCN0_UART0D_EN Value */
-#define MXC_S_GCR_PERCKCN0_UART0D_EN                                           \
-	(MXC_V_GCR_PERCKCN0_UART0D_EN                                          \
-	 << MXC_F_GCR_PERCKCN0_UART0D_POS) /**< PERCKCN0_UART0D_EN Setting */
-#define MXC_V_GCR_PERCKCN0_UART0D_DIS                                          \
+#define MXC_S_GCR_PERCKCN0_UART0D_EN                             \
+	(MXC_V_GCR_PERCKCN0_UART0D_EN                            \
+	 << MXC_F_GCR_PERCKCN0_UART0D_POS) /**<                  \
+					      PERCKCN0_UART0D_EN \
+					      Setting            \
+					    */
+#define MXC_V_GCR_PERCKCN0_UART0D_DIS \
 	((uint32_t)0x1UL) /**< PERCKCN0_UART0D_DIS Value */
-#define MXC_S_GCR_PERCKCN0_UART0D_DIS                                          \
-	(MXC_V_GCR_PERCKCN0_UART0D_DIS                                         \
-	 << MXC_F_GCR_PERCKCN0_UART0D_POS) /**< PERCKCN0_UART0D_DIS Setting */
+#define MXC_S_GCR_PERCKCN0_UART0D_DIS                             \
+	(MXC_V_GCR_PERCKCN0_UART0D_DIS                            \
+	 << MXC_F_GCR_PERCKCN0_UART0D_POS) /**<                   \
+					      PERCKCN0_UART0D_DIS \
+					      Setting             \
+					    */
 
 #define MXC_F_GCR_PERCKCN0_UART1D_POS 10 /**< PERCKCN0_UART1D Position */
-#define MXC_F_GCR_PERCKCN0_UART1D                                              \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_GCR_PERCKCN0_UART1D_POS)) /**< PERCKCN0_UART1D  \
-							    Mask */
-#define MXC_V_GCR_PERCKCN0_UART1D_EN                                           \
+#define MXC_F_GCR_PERCKCN0_UART1D                                           \
+	((uint32_t)(0x1UL                                                   \
+		    << MXC_F_GCR_PERCKCN0_UART1D_POS)) /**< PERCKCN0_UART1D \
+							  Mask */
+#define MXC_V_GCR_PERCKCN0_UART1D_EN \
 	((uint32_t)0x0UL) /**< PERCKCN0_UART1D_EN Value */
-#define MXC_S_GCR_PERCKCN0_UART1D_EN                                           \
-	(MXC_V_GCR_PERCKCN0_UART1D_EN                                          \
-	 << MXC_F_GCR_PERCKCN0_UART1D_POS) /**< PERCKCN0_UART1D_EN Setting */
-#define MXC_V_GCR_PERCKCN0_UART1D_DIS                                          \
+#define MXC_S_GCR_PERCKCN0_UART1D_EN                             \
+	(MXC_V_GCR_PERCKCN0_UART1D_EN                            \
+	 << MXC_F_GCR_PERCKCN0_UART1D_POS) /**<                  \
+					      PERCKCN0_UART1D_EN \
+					      Setting            \
+					    */
+#define MXC_V_GCR_PERCKCN0_UART1D_DIS \
 	((uint32_t)0x1UL) /**< PERCKCN0_UART1D_DIS Value */
-#define MXC_S_GCR_PERCKCN0_UART1D_DIS                                          \
-	(MXC_V_GCR_PERCKCN0_UART1D_DIS                                         \
-	 << MXC_F_GCR_PERCKCN0_UART1D_POS) /**< PERCKCN0_UART1D_DIS Setting */
+#define MXC_S_GCR_PERCKCN0_UART1D_DIS                             \
+	(MXC_V_GCR_PERCKCN0_UART1D_DIS                            \
+	 << MXC_F_GCR_PERCKCN0_UART1D_POS) /**<                   \
+					      PERCKCN0_UART1D_DIS \
+					      Setting             \
+					    */
 
 #define MXC_F_GCR_PERCKCN0_I2C0D_POS 13 /**< PERCKCN0_I2C0D Position */
-#define MXC_F_GCR_PERCKCN0_I2C0D                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_PERCKCN0_I2C0D_POS)) /**< PERCKCN0_I2C0D Mask */
-#define MXC_V_GCR_PERCKCN0_I2C0D_EN                                            \
+#define MXC_F_GCR_PERCKCN0_I2C0D                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_I2C0D_POS)) /**<              \
+							       PERCKCN0_I2C0D \
+							       Mask */
+#define MXC_V_GCR_PERCKCN0_I2C0D_EN \
 	((uint32_t)0x0UL) /**< PERCKCN0_I2C0D_EN Value */
-#define MXC_S_GCR_PERCKCN0_I2C0D_EN                                            \
-	(MXC_V_GCR_PERCKCN0_I2C0D_EN                                           \
-	 << MXC_F_GCR_PERCKCN0_I2C0D_POS) /**< PERCKCN0_I2C0D_EN Setting */
-#define MXC_V_GCR_PERCKCN0_I2C0D_DIS                                           \
+#define MXC_S_GCR_PERCKCN0_I2C0D_EN                            \
+	(MXC_V_GCR_PERCKCN0_I2C0D_EN                           \
+	 << MXC_F_GCR_PERCKCN0_I2C0D_POS) /**<                 \
+					     PERCKCN0_I2C0D_EN \
+					     Setting           \
+					   */
+#define MXC_V_GCR_PERCKCN0_I2C0D_DIS \
 	((uint32_t)0x1UL) /**< PERCKCN0_I2C0D_DIS Value */
-#define MXC_S_GCR_PERCKCN0_I2C0D_DIS                                           \
-	(MXC_V_GCR_PERCKCN0_I2C0D_DIS                                          \
-	 << MXC_F_GCR_PERCKCN0_I2C0D_POS) /**< PERCKCN0_I2C0D_DIS Setting */
+#define MXC_S_GCR_PERCKCN0_I2C0D_DIS                            \
+	(MXC_V_GCR_PERCKCN0_I2C0D_DIS                           \
+	 << MXC_F_GCR_PERCKCN0_I2C0D_POS) /**<                  \
+					     PERCKCN0_I2C0D_DIS \
+					     Setting            \
+					   */
 
 #define MXC_F_GCR_PERCKCN0_T0D_POS 15 /**< PERCKCN0_T0D Position */
-#define MXC_F_GCR_PERCKCN0_T0D                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_PERCKCN0_T0D_POS)) /**< PERCKCN0_T0D Mask */
-#define MXC_V_GCR_PERCKCN0_T0D_EN                                              \
+#define MXC_F_GCR_PERCKCN0_T0D                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T0D_POS)) /**< PERCKCN0_T0D \
+							     Mask */
+#define MXC_V_GCR_PERCKCN0_T0D_EN \
 	((uint32_t)0x0UL) /**< PERCKCN0_T0D_EN Value */
-#define MXC_S_GCR_PERCKCN0_T0D_EN                                              \
-	(MXC_V_GCR_PERCKCN0_T0D_EN                                             \
-	 << MXC_F_GCR_PERCKCN0_T0D_POS) /**< PERCKCN0_T0D_EN Setting */
-#define MXC_V_GCR_PERCKCN0_T0D_DIS                                             \
+#define MXC_S_GCR_PERCKCN0_T0D_EN                          \
+	(MXC_V_GCR_PERCKCN0_T0D_EN                         \
+	 << MXC_F_GCR_PERCKCN0_T0D_POS) /**<               \
+					   PERCKCN0_T0D_EN \
+					   Setting         \
+					 */
+#define MXC_V_GCR_PERCKCN0_T0D_DIS \
 	((uint32_t)0x1UL) /**< PERCKCN0_T0D_DIS Value */
-#define MXC_S_GCR_PERCKCN0_T0D_DIS                                             \
-	(MXC_V_GCR_PERCKCN0_T0D_DIS                                            \
-	 << MXC_F_GCR_PERCKCN0_T0D_POS) /**< PERCKCN0_T0D_DIS Setting */
+#define MXC_S_GCR_PERCKCN0_T0D_DIS                          \
+	(MXC_V_GCR_PERCKCN0_T0D_DIS                         \
+	 << MXC_F_GCR_PERCKCN0_T0D_POS) /**<                \
+					   PERCKCN0_T0D_DIS \
+					   Setting          \
+					 */
 
 #define MXC_F_GCR_PERCKCN0_T1D_POS 16 /**< PERCKCN0_T1D Position */
-#define MXC_F_GCR_PERCKCN0_T1D                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_PERCKCN0_T1D_POS)) /**< PERCKCN0_T1D Mask */
-#define MXC_V_GCR_PERCKCN0_T1D_EN                                              \
+#define MXC_F_GCR_PERCKCN0_T1D                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T1D_POS)) /**< PERCKCN0_T1D \
+							     Mask */
+#define MXC_V_GCR_PERCKCN0_T1D_EN \
 	((uint32_t)0x0UL) /**< PERCKCN0_T1D_EN Value */
-#define MXC_S_GCR_PERCKCN0_T1D_EN                                              \
-	(MXC_V_GCR_PERCKCN0_T1D_EN                                             \
-	 << MXC_F_GCR_PERCKCN0_T1D_POS) /**< PERCKCN0_T1D_EN Setting */
-#define MXC_V_GCR_PERCKCN0_T1D_DIS                                             \
+#define MXC_S_GCR_PERCKCN0_T1D_EN                          \
+	(MXC_V_GCR_PERCKCN0_T1D_EN                         \
+	 << MXC_F_GCR_PERCKCN0_T1D_POS) /**<               \
+					   PERCKCN0_T1D_EN \
+					   Setting         \
+					 */
+#define MXC_V_GCR_PERCKCN0_T1D_DIS \
 	((uint32_t)0x1UL) /**< PERCKCN0_T1D_DIS Value */
-#define MXC_S_GCR_PERCKCN0_T1D_DIS                                             \
-	(MXC_V_GCR_PERCKCN0_T1D_DIS                                            \
-	 << MXC_F_GCR_PERCKCN0_T1D_POS) /**< PERCKCN0_T1D_DIS Setting */
+#define MXC_S_GCR_PERCKCN0_T1D_DIS                          \
+	(MXC_V_GCR_PERCKCN0_T1D_DIS                         \
+	 << MXC_F_GCR_PERCKCN0_T1D_POS) /**<                \
+					   PERCKCN0_T1D_DIS \
+					   Setting          \
+					 */
 
 #define MXC_F_GCR_PERCKCN0_T2D_POS 17 /**< PERCKCN0_T2D Position */
-#define MXC_F_GCR_PERCKCN0_T2D                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_PERCKCN0_T2D_POS)) /**< PERCKCN0_T2D Mask */
-#define MXC_V_GCR_PERCKCN0_T2D_EN                                              \
+#define MXC_F_GCR_PERCKCN0_T2D                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T2D_POS)) /**< PERCKCN0_T2D \
+							     Mask */
+#define MXC_V_GCR_PERCKCN0_T2D_EN \
 	((uint32_t)0x0UL) /**< PERCKCN0_T2D_EN Value */
-#define MXC_S_GCR_PERCKCN0_T2D_EN                                              \
-	(MXC_V_GCR_PERCKCN0_T2D_EN                                             \
-	 << MXC_F_GCR_PERCKCN0_T2D_POS) /**< PERCKCN0_T2D_EN Setting */
-#define MXC_V_GCR_PERCKCN0_T2D_DIS                                             \
+#define MXC_S_GCR_PERCKCN0_T2D_EN                          \
+	(MXC_V_GCR_PERCKCN0_T2D_EN                         \
+	 << MXC_F_GCR_PERCKCN0_T2D_POS) /**<               \
+					   PERCKCN0_T2D_EN \
+					   Setting         \
+					 */
+#define MXC_V_GCR_PERCKCN0_T2D_DIS \
 	((uint32_t)0x1UL) /**< PERCKCN0_T2D_DIS Value */
-#define MXC_S_GCR_PERCKCN0_T2D_DIS                                             \
-	(MXC_V_GCR_PERCKCN0_T2D_DIS                                            \
-	 << MXC_F_GCR_PERCKCN0_T2D_POS) /**< PERCKCN0_T2D_DIS Setting */
+#define MXC_S_GCR_PERCKCN0_T2D_DIS                          \
+	(MXC_V_GCR_PERCKCN0_T2D_DIS                         \
+	 << MXC_F_GCR_PERCKCN0_T2D_POS) /**<                \
+					   PERCKCN0_T2D_DIS \
+					   Setting          \
+					 */
 
 #define MXC_F_GCR_PERCKCN0_I2C1D_POS 28 /**< PERCKCN0_I2C1D Position */
-#define MXC_F_GCR_PERCKCN0_I2C1D                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_PERCKCN0_I2C1D_POS)) /**< PERCKCN0_I2C1D Mask */
-#define MXC_V_GCR_PERCKCN0_I2C1D_EN                                            \
+#define MXC_F_GCR_PERCKCN0_I2C1D                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_I2C1D_POS)) /**<              \
+							       PERCKCN0_I2C1D \
+							       Mask */
+#define MXC_V_GCR_PERCKCN0_I2C1D_EN \
 	((uint32_t)0x0UL) /**< PERCKCN0_I2C1D_EN Value */
-#define MXC_S_GCR_PERCKCN0_I2C1D_EN                                            \
-	(MXC_V_GCR_PERCKCN0_I2C1D_EN                                           \
-	 << MXC_F_GCR_PERCKCN0_I2C1D_POS) /**< PERCKCN0_I2C1D_EN Setting */
-#define MXC_V_GCR_PERCKCN0_I2C1D_DIS                                           \
+#define MXC_S_GCR_PERCKCN0_I2C1D_EN                            \
+	(MXC_V_GCR_PERCKCN0_I2C1D_EN                           \
+	 << MXC_F_GCR_PERCKCN0_I2C1D_POS) /**<                 \
+					     PERCKCN0_I2C1D_EN \
+					     Setting           \
+					   */
+#define MXC_V_GCR_PERCKCN0_I2C1D_DIS \
 	((uint32_t)0x1UL) /**< PERCKCN0_I2C1D_DIS Value */
-#define MXC_S_GCR_PERCKCN0_I2C1D_DIS                                           \
-	(MXC_V_GCR_PERCKCN0_I2C1D_DIS                                          \
-	 << MXC_F_GCR_PERCKCN0_I2C1D_POS) /**< PERCKCN0_I2C1D_DIS Setting */
+#define MXC_S_GCR_PERCKCN0_I2C1D_DIS                            \
+	(MXC_V_GCR_PERCKCN0_I2C1D_DIS                           \
+	 << MXC_F_GCR_PERCKCN0_I2C1D_POS) /**<                  \
+					     PERCKCN0_I2C1D_DIS \
+					     Setting            \
+					   */
 
 /**
  * Memory Clock Control Register.
  */
 #define MXC_F_GCR_MEMCKCN_FWS_POS 0 /**< MEMCKCN_FWS Position */
 #define MXC_F_GCR_MEMCKCN_FWS                                                  \
-	((uint32_t)(                                                           \
-		0x7UL << MXC_F_GCR_MEMCKCN_FWS_POS)) /**< MEMCKCN_FWS Mask */
+	((uint32_t)(0x7UL << MXC_F_GCR_MEMCKCN_FWS_POS)) /**< MEMCKCN_FWS Mask \
+							  */
 
 #define MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS 8 /**< MEMCKCN_SYSRAM0LS Position */
-#define MXC_F_GCR_MEMCKCN_SYSRAM0LS                                            \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS)) /**< MEMCKCN_SYSRAM0LS    \
-							Mask */
-#define MXC_V_GCR_MEMCKCN_SYSRAM0LS_ACTIVE                                     \
+#define MXC_F_GCR_MEMCKCN_SYSRAM0LS                                           \
+	((uint32_t)(0x1UL                                                     \
+		    << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS)) /**<                 \
+							    MEMCKCN_SYSRAM0LS \
+							    Mask */
+#define MXC_V_GCR_MEMCKCN_SYSRAM0LS_ACTIVE \
 	((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM0LS_ACTIVE Value */
-#define MXC_S_GCR_MEMCKCN_SYSRAM0LS_ACTIVE                                     \
-	(MXC_V_GCR_MEMCKCN_SYSRAM0LS_ACTIVE                                    \
-	 << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS) /**< MEMCKCN_SYSRAM0LS_ACTIVE     \
+#define MXC_S_GCR_MEMCKCN_SYSRAM0LS_ACTIVE                                 \
+	(MXC_V_GCR_MEMCKCN_SYSRAM0LS_ACTIVE                                \
+	 << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS) /**< MEMCKCN_SYSRAM0LS_ACTIVE \
 						Setting */
-#define MXC_V_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP                                \
+#define MXC_V_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP \
 	((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM0LS_LIGHT_SLEEP Value */
-#define MXC_S_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP                                \
-	(MXC_V_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP                               \
-	 << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS) /**<                              \
-						MEMCKCN_SYSRAM0LS_LIGHT_SLEEP  \
+#define MXC_S_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP                               \
+	(MXC_V_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP                              \
+	 << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS) /**<                             \
+						MEMCKCN_SYSRAM0LS_LIGHT_SLEEP \
 						Setting */
 
 #define MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS 9 /**< MEMCKCN_SYSRAM1LS Position */
-#define MXC_F_GCR_MEMCKCN_SYSRAM1LS                                            \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS)) /**< MEMCKCN_SYSRAM1LS    \
-							Mask */
-#define MXC_V_GCR_MEMCKCN_SYSRAM1LS_ACTIVE                                     \
+#define MXC_F_GCR_MEMCKCN_SYSRAM1LS                                           \
+	((uint32_t)(0x1UL                                                     \
+		    << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS)) /**<                 \
+							    MEMCKCN_SYSRAM1LS \
+							    Mask */
+#define MXC_V_GCR_MEMCKCN_SYSRAM1LS_ACTIVE \
 	((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM1LS_ACTIVE Value */
-#define MXC_S_GCR_MEMCKCN_SYSRAM1LS_ACTIVE                                     \
-	(MXC_V_GCR_MEMCKCN_SYSRAM1LS_ACTIVE                                    \
-	 << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS) /**< MEMCKCN_SYSRAM1LS_ACTIVE     \
+#define MXC_S_GCR_MEMCKCN_SYSRAM1LS_ACTIVE                                 \
+	(MXC_V_GCR_MEMCKCN_SYSRAM1LS_ACTIVE                                \
+	 << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS) /**< MEMCKCN_SYSRAM1LS_ACTIVE \
 						Setting */
-#define MXC_V_GCR_MEMCKCN_SYSRAM1LS_LIGHT_SLEEP                                \
+#define MXC_V_GCR_MEMCKCN_SYSRAM1LS_LIGHT_SLEEP \
 	((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM1LS_LIGHT_SLEEP Value */
-#define MXC_S_GCR_MEMCKCN_SYSRAM1LS_LIGHT_SLEEP                                \
-	(MXC_V_GCR_MEMCKCN_SYSRAM1LS_LIGHT_SLEEP                               \
-	 << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS) /**<                              \
-						MEMCKCN_SYSRAM1LS_LIGHT_SLEEP  \
+#define MXC_S_GCR_MEMCKCN_SYSRAM1LS_LIGHT_SLEEP                               \
+	(MXC_V_GCR_MEMCKCN_SYSRAM1LS_LIGHT_SLEEP                              \
+	 << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS) /**<                             \
+						MEMCKCN_SYSRAM1LS_LIGHT_SLEEP \
 						Setting */
 
 #define MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS 10 /**< MEMCKCN_SYSRAM2LS Position */
-#define MXC_F_GCR_MEMCKCN_SYSRAM2LS                                            \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS)) /**< MEMCKCN_SYSRAM2LS    \
-							Mask */
-#define MXC_V_GCR_MEMCKCN_SYSRAM2LS_ACTIVE                                     \
+#define MXC_F_GCR_MEMCKCN_SYSRAM2LS                                           \
+	((uint32_t)(0x1UL                                                     \
+		    << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS)) /**<                 \
+							    MEMCKCN_SYSRAM2LS \
+							    Mask */
+#define MXC_V_GCR_MEMCKCN_SYSRAM2LS_ACTIVE \
 	((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM2LS_ACTIVE Value */
-#define MXC_S_GCR_MEMCKCN_SYSRAM2LS_ACTIVE                                     \
-	(MXC_V_GCR_MEMCKCN_SYSRAM2LS_ACTIVE                                    \
-	 << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS) /**< MEMCKCN_SYSRAM2LS_ACTIVE     \
+#define MXC_S_GCR_MEMCKCN_SYSRAM2LS_ACTIVE                                 \
+	(MXC_V_GCR_MEMCKCN_SYSRAM2LS_ACTIVE                                \
+	 << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS) /**< MEMCKCN_SYSRAM2LS_ACTIVE \
 						Setting */
-#define MXC_V_GCR_MEMCKCN_SYSRAM2LS_LIGHT_SLEEP                                \
+#define MXC_V_GCR_MEMCKCN_SYSRAM2LS_LIGHT_SLEEP \
 	((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM2LS_LIGHT_SLEEP Value */
-#define MXC_S_GCR_MEMCKCN_SYSRAM2LS_LIGHT_SLEEP                                \
-	(MXC_V_GCR_MEMCKCN_SYSRAM2LS_LIGHT_SLEEP                               \
-	 << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS) /**<                              \
-						MEMCKCN_SYSRAM2LS_LIGHT_SLEEP  \
+#define MXC_S_GCR_MEMCKCN_SYSRAM2LS_LIGHT_SLEEP                               \
+	(MXC_V_GCR_MEMCKCN_SYSRAM2LS_LIGHT_SLEEP                              \
+	 << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS) /**<                             \
+						MEMCKCN_SYSRAM2LS_LIGHT_SLEEP \
 						Setting */
 
 #define MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS 11 /**< MEMCKCN_SYSRAM3LS Position */
-#define MXC_F_GCR_MEMCKCN_SYSRAM3LS                                            \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS)) /**< MEMCKCN_SYSRAM3LS    \
-							Mask */
-#define MXC_V_GCR_MEMCKCN_SYSRAM3LS_ACTIVE                                     \
+#define MXC_F_GCR_MEMCKCN_SYSRAM3LS                                           \
+	((uint32_t)(0x1UL                                                     \
+		    << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS)) /**<                 \
+							    MEMCKCN_SYSRAM3LS \
+							    Mask */
+#define MXC_V_GCR_MEMCKCN_SYSRAM3LS_ACTIVE \
 	((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM3LS_ACTIVE Value */
-#define MXC_S_GCR_MEMCKCN_SYSRAM3LS_ACTIVE                                     \
-	(MXC_V_GCR_MEMCKCN_SYSRAM3LS_ACTIVE                                    \
-	 << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS) /**< MEMCKCN_SYSRAM3LS_ACTIVE     \
+#define MXC_S_GCR_MEMCKCN_SYSRAM3LS_ACTIVE                                 \
+	(MXC_V_GCR_MEMCKCN_SYSRAM3LS_ACTIVE                                \
+	 << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS) /**< MEMCKCN_SYSRAM3LS_ACTIVE \
 						Setting */
-#define MXC_V_GCR_MEMCKCN_SYSRAM3LS_LIGHT_SLEEP                                \
+#define MXC_V_GCR_MEMCKCN_SYSRAM3LS_LIGHT_SLEEP \
 	((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM3LS_LIGHT_SLEEP Value */
-#define MXC_S_GCR_MEMCKCN_SYSRAM3LS_LIGHT_SLEEP                                \
-	(MXC_V_GCR_MEMCKCN_SYSRAM3LS_LIGHT_SLEEP                               \
-	 << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS) /**<                              \
-						MEMCKCN_SYSRAM3LS_LIGHT_SLEEP  \
+#define MXC_S_GCR_MEMCKCN_SYSRAM3LS_LIGHT_SLEEP                               \
+	(MXC_V_GCR_MEMCKCN_SYSRAM3LS_LIGHT_SLEEP                              \
+	 << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS) /**<                             \
+						MEMCKCN_SYSRAM3LS_LIGHT_SLEEP \
 						Setting */
 
 #define MXC_F_GCR_MEMCKCN_ICACHELS_POS 12 /**< MEMCKCN_ICACHELS Position */
-#define MXC_F_GCR_MEMCKCN_ICACHELS                                             \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_MEMCKCN_ICACHELS_POS)) /**< MEMCKCN_ICACHELS  \
+#define MXC_F_GCR_MEMCKCN_ICACHELS                                            \
+	((uint32_t)(0x1UL                                                     \
+		    << MXC_F_GCR_MEMCKCN_ICACHELS_POS)) /**< MEMCKCN_ICACHELS \
 							   Mask */
-#define MXC_V_GCR_MEMCKCN_ICACHELS_ACTIVE                                      \
+#define MXC_V_GCR_MEMCKCN_ICACHELS_ACTIVE \
 	((uint32_t)0x0UL) /**< MEMCKCN_ICACHELS_ACTIVE Value */
-#define MXC_S_GCR_MEMCKCN_ICACHELS_ACTIVE                                      \
-	(MXC_V_GCR_MEMCKCN_ICACHELS_ACTIVE                                     \
-	 << MXC_F_GCR_MEMCKCN_ICACHELS_POS) /**< MEMCKCN_ICACHELS_ACTIVE       \
+#define MXC_S_GCR_MEMCKCN_ICACHELS_ACTIVE                                \
+	(MXC_V_GCR_MEMCKCN_ICACHELS_ACTIVE                               \
+	 << MXC_F_GCR_MEMCKCN_ICACHELS_POS) /**< MEMCKCN_ICACHELS_ACTIVE \
 					       Setting */
-#define MXC_V_GCR_MEMCKCN_ICACHELS_LIGHT_SLEEP                                 \
+#define MXC_V_GCR_MEMCKCN_ICACHELS_LIGHT_SLEEP \
 	((uint32_t)0x1UL) /**< MEMCKCN_ICACHELS_LIGHT_SLEEP Value */
-#define MXC_S_GCR_MEMCKCN_ICACHELS_LIGHT_SLEEP                                 \
-	(MXC_V_GCR_MEMCKCN_ICACHELS_LIGHT_SLEEP                                \
-	 << MXC_F_GCR_MEMCKCN_ICACHELS_POS) /**< MEMCKCN_ICACHELS_LIGHT_SLEEP  \
+#define MXC_S_GCR_MEMCKCN_ICACHELS_LIGHT_SLEEP                                \
+	(MXC_V_GCR_MEMCKCN_ICACHELS_LIGHT_SLEEP                               \
+	 << MXC_F_GCR_MEMCKCN_ICACHELS_POS) /**< MEMCKCN_ICACHELS_LIGHT_SLEEP \
 					       Setting */
 
 /**
  * Memory Zeroize Control.
  */
 #define MXC_F_GCR_MEMZCN_SRAM0Z_POS 0 /**< MEMZCN_SRAM0Z Position */
-#define MXC_F_GCR_MEMZCN_SRAM0Z                                                \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_MEMZCN_SRAM0Z_POS)) /**< MEMZCN_SRAM0Z Mask */
-#define MXC_V_GCR_MEMZCN_SRAM0Z_NOP                                            \
+#define MXC_F_GCR_MEMZCN_SRAM0Z                                               \
+	((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SRAM0Z_POS)) /**< MEMZCN_SRAM0Z \
+							      Mask */
+#define MXC_V_GCR_MEMZCN_SRAM0Z_NOP \
 	((uint32_t)0x0UL) /**< MEMZCN_SRAM0Z_NOP Value */
-#define MXC_S_GCR_MEMZCN_SRAM0Z_NOP                                            \
-	(MXC_V_GCR_MEMZCN_SRAM0Z_NOP                                           \
-	 << MXC_F_GCR_MEMZCN_SRAM0Z_POS) /**< MEMZCN_SRAM0Z_NOP Setting */
-#define MXC_V_GCR_MEMZCN_SRAM0Z_START                                          \
+#define MXC_S_GCR_MEMZCN_SRAM0Z_NOP                           \
+	(MXC_V_GCR_MEMZCN_SRAM0Z_NOP                          \
+	 << MXC_F_GCR_MEMZCN_SRAM0Z_POS) /**<                 \
+					    MEMZCN_SRAM0Z_NOP \
+					    Setting           \
+					  */
+#define MXC_V_GCR_MEMZCN_SRAM0Z_START \
 	((uint32_t)0x1UL) /**< MEMZCN_SRAM0Z_START Value */
-#define MXC_S_GCR_MEMZCN_SRAM0Z_START                                          \
-	(MXC_V_GCR_MEMZCN_SRAM0Z_START                                         \
-	 << MXC_F_GCR_MEMZCN_SRAM0Z_POS) /**< MEMZCN_SRAM0Z_START Setting */
+#define MXC_S_GCR_MEMZCN_SRAM0Z_START                           \
+	(MXC_V_GCR_MEMZCN_SRAM0Z_START                          \
+	 << MXC_F_GCR_MEMZCN_SRAM0Z_POS) /**<                   \
+					    MEMZCN_SRAM0Z_START \
+					    Setting             \
+					  */
 
 #define MXC_F_GCR_MEMZCN_ICACHEZ_POS 1 /**< MEMZCN_ICACHEZ Position */
-#define MXC_F_GCR_MEMZCN_ICACHEZ                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_MEMZCN_ICACHEZ_POS)) /**< MEMZCN_ICACHEZ Mask */
-#define MXC_V_GCR_MEMZCN_ICACHEZ_NOP                                           \
+#define MXC_F_GCR_MEMZCN_ICACHEZ                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_ICACHEZ_POS)) /**<              \
+							       MEMZCN_ICACHEZ \
+							       Mask */
+#define MXC_V_GCR_MEMZCN_ICACHEZ_NOP \
 	((uint32_t)0x0UL) /**< MEMZCN_ICACHEZ_NOP Value */
-#define MXC_S_GCR_MEMZCN_ICACHEZ_NOP                                           \
-	(MXC_V_GCR_MEMZCN_ICACHEZ_NOP                                          \
-	 << MXC_F_GCR_MEMZCN_ICACHEZ_POS) /**< MEMZCN_ICACHEZ_NOP Setting */
-#define MXC_V_GCR_MEMZCN_ICACHEZ_START                                         \
+#define MXC_S_GCR_MEMZCN_ICACHEZ_NOP                            \
+	(MXC_V_GCR_MEMZCN_ICACHEZ_NOP                           \
+	 << MXC_F_GCR_MEMZCN_ICACHEZ_POS) /**<                  \
+					     MEMZCN_ICACHEZ_NOP \
+					     Setting            \
+					   */
+#define MXC_V_GCR_MEMZCN_ICACHEZ_START \
 	((uint32_t)0x1UL) /**< MEMZCN_ICACHEZ_START Value */
-#define MXC_S_GCR_MEMZCN_ICACHEZ_START                                         \
-	(MXC_V_GCR_MEMZCN_ICACHEZ_START                                        \
-	 << MXC_F_GCR_MEMZCN_ICACHEZ_POS) /**< MEMZCN_ICACHEZ_START Setting */
+#define MXC_S_GCR_MEMZCN_ICACHEZ_START                            \
+	(MXC_V_GCR_MEMZCN_ICACHEZ_START                           \
+	 << MXC_F_GCR_MEMZCN_ICACHEZ_POS) /**<                    \
+					     MEMZCN_ICACHEZ_START \
+					     Setting              \
+					   */
 
 /**
  * System Status Register.
  */
 #define MXC_F_GCR_SYSST_ICECLOCK_POS 0 /**< SYSST_ICECLOCK Position */
-#define MXC_F_GCR_SYSST_ICECLOCK                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_SYSST_ICECLOCK_POS)) /**< SYSST_ICECLOCK Mask */
-#define MXC_V_GCR_SYSST_ICECLOCK_UNLOCKED                                      \
+#define MXC_F_GCR_SYSST_ICECLOCK                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_SYSST_ICECLOCK_POS)) /**<              \
+							       SYSST_ICECLOCK \
+							       Mask */
+#define MXC_V_GCR_SYSST_ICECLOCK_UNLOCKED \
 	((uint32_t)0x0UL) /**< SYSST_ICECLOCK_UNLOCKED Value */
 #define MXC_S_GCR_SYSST_ICECLOCK_UNLOCKED                                      \
 	(MXC_V_GCR_SYSST_ICECLOCK_UNLOCKED                                     \
 	 << MXC_F_GCR_SYSST_ICECLOCK_POS) /**< SYSST_ICECLOCK_UNLOCKED Setting \
 					   */
-#define MXC_V_GCR_SYSST_ICECLOCK_LOCKED                                        \
+#define MXC_V_GCR_SYSST_ICECLOCK_LOCKED \
 	((uint32_t)0x1UL) /**< SYSST_ICECLOCK_LOCKED Value */
-#define MXC_S_GCR_SYSST_ICECLOCK_LOCKED                                        \
-	(MXC_V_GCR_SYSST_ICECLOCK_LOCKED                                       \
-	 << MXC_F_GCR_SYSST_ICECLOCK_POS) /**< SYSST_ICECLOCK_LOCKED Setting   \
+#define MXC_S_GCR_SYSST_ICECLOCK_LOCKED                                      \
+	(MXC_V_GCR_SYSST_ICECLOCK_LOCKED                                     \
+	 << MXC_F_GCR_SYSST_ICECLOCK_POS) /**< SYSST_ICECLOCK_LOCKED Setting \
 					   */
 
 #define MXC_F_GCR_SYSST_CODEINTERR_POS 1 /**< SYSST_CODEINTERR Position */
-#define MXC_F_GCR_SYSST_CODEINTERR                                             \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_SYSST_CODEINTERR_POS)) /**< SYSST_CODEINTERR  \
+#define MXC_F_GCR_SYSST_CODEINTERR                                            \
+	((uint32_t)(0x1UL                                                     \
+		    << MXC_F_GCR_SYSST_CODEINTERR_POS)) /**< SYSST_CODEINTERR \
 							   Mask */
-#define MXC_V_GCR_SYSST_CODEINTERR_NORM                                        \
+#define MXC_V_GCR_SYSST_CODEINTERR_NORM \
 	((uint32_t)0x0UL) /**< SYSST_CODEINTERR_NORM Value */
 #define MXC_S_GCR_SYSST_CODEINTERR_NORM                                        \
 	(MXC_V_GCR_SYSST_CODEINTERR_NORM                                       \
 	 << MXC_F_GCR_SYSST_CODEINTERR_POS) /**< SYSST_CODEINTERR_NORM Setting \
 					     */
-#define MXC_V_GCR_SYSST_CODEINTERR_CODE                                        \
+#define MXC_V_GCR_SYSST_CODEINTERR_CODE \
 	((uint32_t)0x1UL) /**< SYSST_CODEINTERR_CODE Value */
 #define MXC_S_GCR_SYSST_CODEINTERR_CODE                                        \
 	(MXC_V_GCR_SYSST_CODEINTERR_CODE                                       \
@@ -1213,153 +1525,187 @@ typedef struct {
 					     */
 
 #define MXC_F_GCR_SYSST_SCMEMF_POS 5 /**< SYSST_SCMEMF Position */
-#define MXC_F_GCR_SYSST_SCMEMF                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_SYSST_SCMEMF_POS)) /**< SYSST_SCMEMF Mask */
-#define MXC_V_GCR_SYSST_SCMEMF_NORM                                            \
+#define MXC_F_GCR_SYSST_SCMEMF                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_SYSST_SCMEMF_POS)) /**< SYSST_SCMEMF \
+							     Mask */
+#define MXC_V_GCR_SYSST_SCMEMF_NORM \
 	((uint32_t)0x0UL) /**< SYSST_SCMEMF_NORM Value */
-#define MXC_S_GCR_SYSST_SCMEMF_NORM                                            \
-	(MXC_V_GCR_SYSST_SCMEMF_NORM                                           \
-	 << MXC_F_GCR_SYSST_SCMEMF_POS) /**< SYSST_SCMEMF_NORM Setting */
-#define MXC_V_GCR_SYSST_SCMEMF_MEMORY                                          \
+#define MXC_S_GCR_SYSST_SCMEMF_NORM                          \
+	(MXC_V_GCR_SYSST_SCMEMF_NORM                         \
+	 << MXC_F_GCR_SYSST_SCMEMF_POS) /**<                 \
+					   SYSST_SCMEMF_NORM \
+					   Setting           \
+					 */
+#define MXC_V_GCR_SYSST_SCMEMF_MEMORY \
 	((uint32_t)0x1UL) /**< SYSST_SCMEMF_MEMORY Value */
-#define MXC_S_GCR_SYSST_SCMEMF_MEMORY                                          \
-	(MXC_V_GCR_SYSST_SCMEMF_MEMORY                                         \
-	 << MXC_F_GCR_SYSST_SCMEMF_POS) /**< SYSST_SCMEMF_MEMORY Setting */
+#define MXC_S_GCR_SYSST_SCMEMF_MEMORY                          \
+	(MXC_V_GCR_SYSST_SCMEMF_MEMORY                         \
+	 << MXC_F_GCR_SYSST_SCMEMF_POS) /**<                   \
+					   SYSST_SCMEMF_MEMORY \
+					   Setting             \
+					 */
 
 /**
  * Reset Register.
  */
 #define MXC_F_GCR_RSTR1_I2C1_POS 0 /**< RSTR1_I2C1 Position */
-#define MXC_F_GCR_RSTR1_I2C1                                                   \
-	((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_I2C1_POS)) /**< RSTR1_I2C1 Mask   \
+#define MXC_F_GCR_RSTR1_I2C1                                                 \
+	((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_I2C1_POS)) /**< RSTR1_I2C1 Mask \
 							 */
-#define MXC_V_GCR_RSTR1_I2C1_RESET                                             \
+#define MXC_V_GCR_RSTR1_I2C1_RESET \
 	((uint32_t)0x1UL) /**< RSTR1_I2C1_RESET Value */
-#define MXC_S_GCR_RSTR1_I2C1_RESET                                             \
-	(MXC_V_GCR_RSTR1_I2C1_RESET                                            \
-	 << MXC_F_GCR_RSTR1_I2C1_POS) /**< RSTR1_I2C1_RESET Setting */
-#define MXC_V_GCR_RSTR1_I2C1_RESET_DONE                                        \
+#define MXC_S_GCR_RSTR1_I2C1_RESET                        \
+	(MXC_V_GCR_RSTR1_I2C1_RESET                       \
+	 << MXC_F_GCR_RSTR1_I2C1_POS) /**<                \
+					 RSTR1_I2C1_RESET \
+					 Setting */
+#define MXC_V_GCR_RSTR1_I2C1_RESET_DONE \
 	((uint32_t)0x0UL) /**< RSTR1_I2C1_RESET_DONE Value */
-#define MXC_S_GCR_RSTR1_I2C1_RESET_DONE                                        \
-	(MXC_V_GCR_RSTR1_I2C1_RESET_DONE                                       \
-	 << MXC_F_GCR_RSTR1_I2C1_POS) /**< RSTR1_I2C1_RESET_DONE Setting */
-#define MXC_V_GCR_RSTR1_I2C1_BUSY                                              \
+#define MXC_S_GCR_RSTR1_I2C1_RESET_DONE                        \
+	(MXC_V_GCR_RSTR1_I2C1_RESET_DONE                       \
+	 << MXC_F_GCR_RSTR1_I2C1_POS) /**<                     \
+					 RSTR1_I2C1_RESET_DONE \
+					 Setting               \
+				       */
+#define MXC_V_GCR_RSTR1_I2C1_BUSY \
 	((uint32_t)0x1UL) /**< RSTR1_I2C1_BUSY Value */
-#define MXC_S_GCR_RSTR1_I2C1_BUSY                                              \
-	(MXC_V_GCR_RSTR1_I2C1_BUSY                                             \
-	 << MXC_F_GCR_RSTR1_I2C1_POS) /**< RSTR1_I2C1_BUSY Setting */
+#define MXC_S_GCR_RSTR1_I2C1_BUSY                        \
+	(MXC_V_GCR_RSTR1_I2C1_BUSY                       \
+	 << MXC_F_GCR_RSTR1_I2C1_POS) /**<               \
+					 RSTR1_I2C1_BUSY \
+					 Setting */
 
 /**
  * Peripheral Clock Disable.
  */
 #define MXC_F_GCR_PERCKCN1_FLCD_POS 3 /**< PERCKCN1_FLCD Position */
-#define MXC_F_GCR_PERCKCN1_FLCD                                                \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_PERCKCN1_FLCD_POS)) /**< PERCKCN1_FLCD Mask */
-#define MXC_V_GCR_PERCKCN1_FLCD_EN                                             \
+#define MXC_F_GCR_PERCKCN1_FLCD                                               \
+	((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_FLCD_POS)) /**< PERCKCN1_FLCD \
+							      Mask */
+#define MXC_V_GCR_PERCKCN1_FLCD_EN \
 	((uint32_t)0x0UL) /**< PERCKCN1_FLCD_EN Value */
-#define MXC_S_GCR_PERCKCN1_FLCD_EN                                             \
-	(MXC_V_GCR_PERCKCN1_FLCD_EN                                            \
-	 << MXC_F_GCR_PERCKCN1_FLCD_POS) /**< PERCKCN1_FLCD_EN Setting */
-#define MXC_V_GCR_PERCKCN1_FLCD_DIS                                            \
+#define MXC_S_GCR_PERCKCN1_FLCD_EN                           \
+	(MXC_V_GCR_PERCKCN1_FLCD_EN                          \
+	 << MXC_F_GCR_PERCKCN1_FLCD_POS) /**<                \
+					    PERCKCN1_FLCD_EN \
+					    Setting          \
+					  */
+#define MXC_V_GCR_PERCKCN1_FLCD_DIS \
 	((uint32_t)0x1UL) /**< PERCKCN1_FLCD_DIS Value */
-#define MXC_S_GCR_PERCKCN1_FLCD_DIS                                            \
-	(MXC_V_GCR_PERCKCN1_FLCD_DIS                                           \
-	 << MXC_F_GCR_PERCKCN1_FLCD_POS) /**< PERCKCN1_FLCD_DIS Setting */
+#define MXC_S_GCR_PERCKCN1_FLCD_DIS                           \
+	(MXC_V_GCR_PERCKCN1_FLCD_DIS                          \
+	 << MXC_F_GCR_PERCKCN1_FLCD_POS) /**<                 \
+					    PERCKCN1_FLCD_DIS \
+					    Setting           \
+					  */
 
 #define MXC_F_GCR_PERCKCN1_ICACHED_POS 11 /**< PERCKCN1_ICACHED Position */
-#define MXC_F_GCR_PERCKCN1_ICACHED                                             \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_PERCKCN1_ICACHED_POS)) /**< PERCKCN1_ICACHED  \
+#define MXC_F_GCR_PERCKCN1_ICACHED                                            \
+	((uint32_t)(0x1UL                                                     \
+		    << MXC_F_GCR_PERCKCN1_ICACHED_POS)) /**< PERCKCN1_ICACHED \
 							   Mask */
-#define MXC_V_GCR_PERCKCN1_ICACHED_EN                                          \
+#define MXC_V_GCR_PERCKCN1_ICACHED_EN \
 	((uint32_t)0x0UL) /**< PERCKCN1_ICACHED_EN Value */
-#define MXC_S_GCR_PERCKCN1_ICACHED_EN                                          \
-	(MXC_V_GCR_PERCKCN1_ICACHED_EN                                         \
-	 << MXC_F_GCR_PERCKCN1_ICACHED_POS) /**< PERCKCN1_ICACHED_EN Setting   \
+#define MXC_S_GCR_PERCKCN1_ICACHED_EN                                        \
+	(MXC_V_GCR_PERCKCN1_ICACHED_EN                                       \
+	 << MXC_F_GCR_PERCKCN1_ICACHED_POS) /**< PERCKCN1_ICACHED_EN Setting \
 					     */
-#define MXC_V_GCR_PERCKCN1_ICACHED_DIS                                         \
+#define MXC_V_GCR_PERCKCN1_ICACHED_DIS \
 	((uint32_t)0x1UL) /**< PERCKCN1_ICACHED_DIS Value */
-#define MXC_S_GCR_PERCKCN1_ICACHED_DIS                                         \
-	(MXC_V_GCR_PERCKCN1_ICACHED_DIS                                        \
-	 << MXC_F_GCR_PERCKCN1_ICACHED_POS) /**< PERCKCN1_ICACHED_DIS Setting  \
+#define MXC_S_GCR_PERCKCN1_ICACHED_DIS                                        \
+	(MXC_V_GCR_PERCKCN1_ICACHED_DIS                                       \
+	 << MXC_F_GCR_PERCKCN1_ICACHED_POS) /**< PERCKCN1_ICACHED_DIS Setting \
 					     */
 
 /**
  * Event Enable Register.
  */
 #define MXC_F_GCR_EVTEN_DMAEVENT_POS 0 /**< EVTEN_DMAEVENT Position */
-#define MXC_F_GCR_EVTEN_DMAEVENT                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_EVTEN_DMAEVENT_POS)) /**< EVTEN_DMAEVENT Mask */
+#define MXC_F_GCR_EVTEN_DMAEVENT                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_DMAEVENT_POS)) /**<              \
+							       EVTEN_DMAEVENT \
+							       Mask */
 
 #define MXC_F_GCR_EVTEN_RXEVENT_POS 1 /**< EVTEN_RXEVENT Position */
-#define MXC_F_GCR_EVTEN_RXEVENT                                                \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_EVTEN_RXEVENT_POS)) /**< EVTEN_RXEVENT Mask */
+#define MXC_F_GCR_EVTEN_RXEVENT                                               \
+	((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_RXEVENT_POS)) /**< EVTEN_RXEVENT \
+							      Mask */
 
 /**
  * Revision Register.
  */
 #define MXC_F_GCR_REVISION_REVISION_POS 0 /**< REVISION_REVISION Position */
-#define MXC_F_GCR_REVISION_REVISION                                            \
-	((uint32_t)(                                                           \
-		0xFFFFUL                                                       \
-		<< MXC_F_GCR_REVISION_REVISION_POS)) /**< REVISION_REVISION    \
-							Mask */
+#define MXC_F_GCR_REVISION_REVISION                                           \
+	((uint32_t)(0xFFFFUL                                                  \
+		    << MXC_F_GCR_REVISION_REVISION_POS)) /**<                 \
+							    REVISION_REVISION \
+							    Mask */
 
 /**
  * System Status Interrupt Enable Register.
  */
 #define MXC_F_GCR_SYSSIE_ICEULIE_POS 0 /**< SYSSIE_ICEULIE Position */
-#define MXC_F_GCR_SYSSIE_ICEULIE                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_SYSSIE_ICEULIE_POS)) /**< SYSSIE_ICEULIE Mask */
-#define MXC_V_GCR_SYSSIE_ICEULIE_DIS                                           \
+#define MXC_F_GCR_SYSSIE_ICEULIE                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_SYSSIE_ICEULIE_POS)) /**<              \
+							       SYSSIE_ICEULIE \
+							       Mask */
+#define MXC_V_GCR_SYSSIE_ICEULIE_DIS \
 	((uint32_t)0x0UL) /**< SYSSIE_ICEULIE_DIS Value */
-#define MXC_S_GCR_SYSSIE_ICEULIE_DIS                                           \
-	(MXC_V_GCR_SYSSIE_ICEULIE_DIS                                          \
-	 << MXC_F_GCR_SYSSIE_ICEULIE_POS) /**< SYSSIE_ICEULIE_DIS Setting */
-#define MXC_V_GCR_SYSSIE_ICEULIE_EN                                            \
+#define MXC_S_GCR_SYSSIE_ICEULIE_DIS                            \
+	(MXC_V_GCR_SYSSIE_ICEULIE_DIS                           \
+	 << MXC_F_GCR_SYSSIE_ICEULIE_POS) /**<                  \
+					     SYSSIE_ICEULIE_DIS \
+					     Setting            \
+					   */
+#define MXC_V_GCR_SYSSIE_ICEULIE_EN \
 	((uint32_t)0x1UL) /**< SYSSIE_ICEULIE_EN Value */
-#define MXC_S_GCR_SYSSIE_ICEULIE_EN                                            \
-	(MXC_V_GCR_SYSSIE_ICEULIE_EN                                           \
-	 << MXC_F_GCR_SYSSIE_ICEULIE_POS) /**< SYSSIE_ICEULIE_EN Setting */
+#define MXC_S_GCR_SYSSIE_ICEULIE_EN                            \
+	(MXC_V_GCR_SYSSIE_ICEULIE_EN                           \
+	 << MXC_F_GCR_SYSSIE_ICEULIE_POS) /**<                 \
+					     SYSSIE_ICEULIE_EN \
+					     Setting           \
+					   */
 
 #define MXC_F_GCR_SYSSIE_CIEIE_POS 1 /**< SYSSIE_CIEIE Position */
-#define MXC_F_GCR_SYSSIE_CIEIE                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_GCR_SYSSIE_CIEIE_POS)) /**< SYSSIE_CIEIE Mask */
-#define MXC_V_GCR_SYSSIE_CIEIE_DIS                                             \
+#define MXC_F_GCR_SYSSIE_CIEIE                                              \
+	((uint32_t)(0x1UL << MXC_F_GCR_SYSSIE_CIEIE_POS)) /**< SYSSIE_CIEIE \
+							     Mask */
+#define MXC_V_GCR_SYSSIE_CIEIE_DIS \
 	((uint32_t)0x0UL) /**< SYSSIE_CIEIE_DIS Value */
-#define MXC_S_GCR_SYSSIE_CIEIE_DIS                                             \
-	(MXC_V_GCR_SYSSIE_CIEIE_DIS                                            \
-	 << MXC_F_GCR_SYSSIE_CIEIE_POS) /**< SYSSIE_CIEIE_DIS Setting */
-#define MXC_V_GCR_SYSSIE_CIEIE_EN                                              \
+#define MXC_S_GCR_SYSSIE_CIEIE_DIS                          \
+	(MXC_V_GCR_SYSSIE_CIEIE_DIS                         \
+	 << MXC_F_GCR_SYSSIE_CIEIE_POS) /**<                \
+					   SYSSIE_CIEIE_DIS \
+					   Setting          \
+					 */
+#define MXC_V_GCR_SYSSIE_CIEIE_EN \
 	((uint32_t)0x1UL) /**< SYSSIE_CIEIE_EN Value */
-#define MXC_S_GCR_SYSSIE_CIEIE_EN                                              \
-	(MXC_V_GCR_SYSSIE_CIEIE_EN                                             \
-	 << MXC_F_GCR_SYSSIE_CIEIE_POS) /**< SYSSIE_CIEIE_EN Setting */
+#define MXC_S_GCR_SYSSIE_CIEIE_EN                          \
+	(MXC_V_GCR_SYSSIE_CIEIE_EN                         \
+	 << MXC_F_GCR_SYSSIE_CIEIE_POS) /**<               \
+					   SYSSIE_CIEIE_EN \
+					   Setting         \
+					 */
 
 #define MXC_F_GCR_SYSSIE_SCMFIE_POS 5 /**< SYSSIE_SCMFIE Position */
-#define MXC_F_GCR_SYSSIE_SCMFIE                                                \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_GCR_SYSSIE_SCMFIE_POS)) /**< SYSSIE_SCMFIE Mask */
-#define MXC_V_GCR_SYSSIE_SCMFIE_DIS                                            \
+#define MXC_F_GCR_SYSSIE_SCMFIE                                               \
+	((uint32_t)(0x1UL << MXC_F_GCR_SYSSIE_SCMFIE_POS)) /**< SYSSIE_SCMFIE \
+							      Mask */
+#define MXC_V_GCR_SYSSIE_SCMFIE_DIS \
 	((uint32_t)0x0UL) /**< SYSSIE_SCMFIE_DIS Value */
-#define MXC_S_GCR_SYSSIE_SCMFIE_DIS                                            \
-	(MXC_V_GCR_SYSSIE_SCMFIE_DIS                                           \
-	 << MXC_F_GCR_SYSSIE_SCMFIE_POS) /**< SYSSIE_SCMFIE_DIS Setting */
-#define MXC_V_GCR_SYSSIE_SCMFIE_EN                                             \
+#define MXC_S_GCR_SYSSIE_SCMFIE_DIS                           \
+	(MXC_V_GCR_SYSSIE_SCMFIE_DIS                          \
+	 << MXC_F_GCR_SYSSIE_SCMFIE_POS) /**<                 \
+					    SYSSIE_SCMFIE_DIS \
+					    Setting           \
+					  */
+#define MXC_V_GCR_SYSSIE_SCMFIE_EN \
 	((uint32_t)0x1UL) /**< SYSSIE_SCMFIE_EN Value */
-#define MXC_S_GCR_SYSSIE_SCMFIE_EN                                             \
-	(MXC_V_GCR_SYSSIE_SCMFIE_EN                                            \
-	 << MXC_F_GCR_SYSSIE_SCMFIE_POS) /**< SYSSIE_SCMFIE_EN Setting */
+#define MXC_S_GCR_SYSSIE_SCMFIE_EN                           \
+	(MXC_V_GCR_SYSSIE_SCMFIE_EN                          \
+	 << MXC_F_GCR_SYSSIE_SCMFIE_POS) /**<                \
+					    SYSSIE_SCMFIE_EN \
+					    Setting          \
+					  */
 
 #endif /* _GCR_REGS_H_ */
diff --git a/chip/max32660/gpio_chip.c b/chip/max32660/gpio_chip.c
index 1ef73890ec..cc54f9055f 100644
--- a/chip/max32660/gpio_chip.c
+++ b/chip/max32660/gpio_chip.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,10 +21,10 @@
 #define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
 
 /* 0-terminated list of GPIO base addresses */
-static mxc_gpio_regs_t *gpio_bases[] = {MXC_GPIO0, 0};
+static mxc_gpio_regs_t *gpio_bases[] = { MXC_GPIO0, 0 };
 
 void gpio_set_alternate_function(uint32_t port, uint32_t mask,
-			enum gpio_alternate_func func)
+				 enum gpio_alternate_func func)
 {
 	mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(port);
 
@@ -42,7 +42,7 @@ void gpio_set_alternate_function(uint32_t port, uint32_t mask,
 		gpio->en1_set = mask;
 		break;
 	default:
-	    /* Default as input */
+		/* Default as input */
 		gpio->out_en_clr = mask;
 		gpio->en_set = mask;
 		gpio->en1_clr = mask;
@@ -184,7 +184,7 @@ void gpio_pre_init(void)
 
 		/* Use as GPIO, not alternate function */
 		gpio_set_alternate_function(g->port, g->mask,
-					GPIO_ALT_FUNC_NONE);
+					    GPIO_ALT_FUNC_NONE);
 
 		/* Set up GPIO based on flags */
 		gpio_set_flags_by_mask(g->port, g->mask, flags);
@@ -194,8 +194,8 @@ void gpio_pre_init(void)
 static void gpio_init(void)
 {
 	/*
-	 * Enable global GPIO0 Port interrupt. Note that interrupts still need to be
-	 * enabled at the per pin level.
+	 * Enable global GPIO0 Port interrupt. Note that interrupts still need
+	 * to be enabled at the per pin level.
 	 */
 	task_enable_irq(EC_GPIO0_IRQn);
 }
@@ -227,13 +227,13 @@ static void gpio_interrupt(int port, uint32_t mis)
  * Handlers for each GPIO port. Read the interrupt status, call the common GPIO
  * interrupt handler and clear the GPIO hardware interrupt status.
  */
-#define GPIO_IRQ_FUNC(irqfunc, gpiobase)                                       \
-	static void irqfunc(void)                                              \
-	{                                                                      \
-		mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(gpiobase);           \
-		uint32_t mis = gpio->int_stat;                                 \
-		gpio_interrupt(gpiobase, mis);                                 \
-		gpio->int_clr = mis;                                           \
+#define GPIO_IRQ_FUNC(irqfunc, gpiobase)                             \
+	static void irqfunc(void)                                    \
+	{                                                            \
+		mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(gpiobase); \
+		uint32_t mis = gpio->int_stat;                       \
+		gpio_interrupt(gpiobase, mis);                       \
+		gpio->int_clr = mis;                                 \
 	}
 
 GPIO_IRQ_FUNC(__gpio_0_interrupt, PORT_0);
diff --git a/chip/max32660/gpio_regs.h b/chip/max32660/gpio_regs.h
index 1c6fcf7a71..70b706b2c0 100644
--- a/chip/max32660/gpio_regs.h
+++ b/chip/max32660/gpio_regs.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -40,65 +40,65 @@
  * Structure type to access the GPIO Registers.
  */
 typedef struct {
-	__IO uint32_t en;     /**< <tt>\b 0x00:<\tt> GPIO EN Register */
+	__IO uint32_t en; /**< <tt>\b 0x00:<\tt> GPIO EN Register */
 	__IO uint32_t en_set; /**< <tt>\b 0x04:<\tt> GPIO EN_SET Register */
 	__IO uint32_t en_clr; /**< <tt>\b 0x08:<\tt> GPIO EN_CLR Register */
 	__IO uint32_t out_en; /**< <tt>\b 0x0C:<\tt> GPIO OUT_EN Register */
-	__IO uint32_t
-		out_en_set; /**< <tt>\b 0x10:<\tt> GPIO OUT_EN_SET Register */
-	__IO uint32_t
-		out_en_clr;   /**< <tt>\b 0x14:<\tt> GPIO OUT_EN_CLR Register */
-	__IO uint32_t out;    /**< <tt>\b 0x18:<\tt> GPIO OUT Register */
+	__IO uint32_t out_en_set; /**< <tt>\b 0x10:<\tt> GPIO OUT_EN_SET
+				     Register */
+	__IO uint32_t out_en_clr; /**< <tt>\b 0x14:<\tt> GPIO OUT_EN_CLR
+				     Register */
+	__IO uint32_t out; /**< <tt>\b 0x18:<\tt> GPIO OUT Register */
 	__O uint32_t out_set; /**< <tt>\b 0x1C:<\tt> GPIO OUT_SET Register */
 	__O uint32_t out_clr; /**< <tt>\b 0x20:<\tt> GPIO OUT_CLR Register */
-	__I uint32_t in;      /**< <tt>\b 0x24:<\tt> GPIO IN Register */
+	__I uint32_t in; /**< <tt>\b 0x24:<\tt> GPIO IN Register */
 	__IO uint32_t int_mod; /**< <tt>\b 0x28:<\tt> GPIO INT_MOD Register */
 	__IO uint32_t int_pol; /**< <tt>\b 0x2C:<\tt> GPIO INT_POL Register */
 	__R uint32_t rsv_0x30;
 	__IO uint32_t int_en; /**< <tt>\b 0x34:<\tt> GPIO INT_EN Register */
-	__IO uint32_t
-		int_en_set; /**< <tt>\b 0x38:<\tt> GPIO INT_EN_SET Register */
-	__IO uint32_t
-		int_en_clr; /**< <tt>\b 0x3C:<\tt> GPIO INT_EN_CLR Register */
+	__IO uint32_t int_en_set; /**< <tt>\b 0x38:<\tt> GPIO INT_EN_SET
+				     Register */
+	__IO uint32_t int_en_clr; /**< <tt>\b 0x3C:<\tt> GPIO INT_EN_CLR
+				     Register */
 	__I uint32_t int_stat; /**< <tt>\b 0x40:<\tt> GPIO INT_STAT Register */
 	__R uint32_t rsv_0x44;
 	__IO uint32_t int_clr; /**< <tt>\b 0x48:<\tt> GPIO INT_CLR Register */
 	__IO uint32_t wake_en; /**< <tt>\b 0x4C:<\tt> GPIO WAKE_EN Register */
-	__IO uint32_t
-		wake_en_set; /**< <tt>\b 0x50:<\tt> GPIO WAKE_EN_SET Register */
-	__IO uint32_t
-		wake_en_clr; /**< <tt>\b 0x54:<\tt> GPIO WAKE_EN_CLR Register */
+	__IO uint32_t wake_en_set; /**< <tt>\b 0x50:<\tt> GPIO WAKE_EN_SET
+				      Register */
+	__IO uint32_t wake_en_clr; /**< <tt>\b 0x54:<\tt> GPIO WAKE_EN_CLR
+				      Register */
 	__R uint32_t rsv_0x58;
 	__IO uint32_t int_dual_edge; /**< <tt>\b 0x5C:<\tt> GPIO INT_DUAL_EDGE
 					Register */
 	__IO uint32_t pad_cfg1; /**< <tt>\b 0x60:<\tt> GPIO PAD_CFG1 Register */
 	__IO uint32_t pad_cfg2; /**< <tt>\b 0x64:<\tt> GPIO PAD_CFG2 Register */
-	__IO uint32_t en1;      /**< <tt>\b 0x68:<\tt> GPIO EN1 Register */
-	__IO uint32_t en1_set;  /**< <tt>\b 0x6C:<\tt> GPIO EN1_SET Register */
-	__IO uint32_t en1_clr;  /**< <tt>\b 0x70:<\tt> GPIO EN1_CLR Register */
-	__IO uint32_t en2;      /**< <tt>\b 0x74:<\tt> GPIO EN2 Register */
-	__IO uint32_t en2_set;  /**< <tt>\b 0x78:<\tt> GPIO EN2_SET Register */
-	__IO uint32_t en2_clr;  /**< <tt>\b 0x7C:<\tt> GPIO EN2_CLR Register */
+	__IO uint32_t en1; /**< <tt>\b 0x68:<\tt> GPIO EN1 Register */
+	__IO uint32_t en1_set; /**< <tt>\b 0x6C:<\tt> GPIO EN1_SET Register */
+	__IO uint32_t en1_clr; /**< <tt>\b 0x70:<\tt> GPIO EN1_CLR Register */
+	__IO uint32_t en2; /**< <tt>\b 0x74:<\tt> GPIO EN2 Register */
+	__IO uint32_t en2_set; /**< <tt>\b 0x78:<\tt> GPIO EN2_SET Register */
+	__IO uint32_t en2_clr; /**< <tt>\b 0x7C:<\tt> GPIO EN2_CLR Register */
 	__R uint32_t rsv_0x80_0xa7[10];
-	__IO uint32_t is;  /**< <tt>\b 0xA8:<\tt> GPIO IS Register */
-	__IO uint32_t sr;  /**< <tt>\b 0xAC:<\tt> GPIO SR Register */
-	__IO uint32_t ds;  /**< <tt>\b 0xB0:<\tt> GPIO DS Register */
+	__IO uint32_t is; /**< <tt>\b 0xA8:<\tt> GPIO IS Register */
+	__IO uint32_t sr; /**< <tt>\b 0xAC:<\tt> GPIO SR Register */
+	__IO uint32_t ds; /**< <tt>\b 0xB0:<\tt> GPIO DS Register */
 	__IO uint32_t ds1; /**< <tt>\b 0xB4:<\tt> GPIO DS1 Register */
-	__IO uint32_t ps;  /**< <tt>\b 0xB8:<\tt> GPIO PS Register */
+	__IO uint32_t ps; /**< <tt>\b 0xB8:<\tt> GPIO PS Register */
 	__R uint32_t rsv_0xbc;
 	__IO uint32_t vssel; /**< <tt>\b 0xC0:<\tt> GPIO VSSEL Register */
 } mxc_gpio_regs_t;
 
-#define PIN_0 ((uint32_t)(1UL << 0))   /**< Pin 0 Define */
-#define PIN_1 ((uint32_t)(1UL << 1))   /**< Pin 1 Define */
-#define PIN_2 ((uint32_t)(1UL << 2))   /**< Pin 2 Define */
-#define PIN_3 ((uint32_t)(1UL << 3))   /**< Pin 3 Define */
-#define PIN_4 ((uint32_t)(1UL << 4))   /**< Pin 4 Define */
-#define PIN_5 ((uint32_t)(1UL << 5))   /**< Pin 5 Define */
-#define PIN_6 ((uint32_t)(1UL << 6))   /**< Pin 6 Define */
-#define PIN_7 ((uint32_t)(1UL << 7))   /**< Pin 7 Define */
-#define PIN_8 ((uint32_t)(1UL << 8))   /**< Pin 8 Define */
-#define PIN_9 ((uint32_t)(1UL << 9))   /**< Pin 9 Define */
+#define PIN_0 ((uint32_t)(1UL << 0)) /**< Pin 0 Define */
+#define PIN_1 ((uint32_t)(1UL << 1)) /**< Pin 1 Define */
+#define PIN_2 ((uint32_t)(1UL << 2)) /**< Pin 2 Define */
+#define PIN_3 ((uint32_t)(1UL << 3)) /**< Pin 3 Define */
+#define PIN_4 ((uint32_t)(1UL << 4)) /**< Pin 4 Define */
+#define PIN_5 ((uint32_t)(1UL << 5)) /**< Pin 5 Define */
+#define PIN_6 ((uint32_t)(1UL << 6)) /**< Pin 6 Define */
+#define PIN_7 ((uint32_t)(1UL << 7)) /**< Pin 7 Define */
+#define PIN_8 ((uint32_t)(1UL << 8)) /**< Pin 8 Define */
+#define PIN_9 ((uint32_t)(1UL << 9)) /**< Pin 9 Define */
 #define PIN_10 ((uint32_t)(1UL << 10)) /**< Pin 10 Define */
 #define PIN_11 ((uint32_t)(1UL << 11)) /**< Pin 11 Define */
 #define PIN_12 ((uint32_t)(1UL << 12)) /**< Pin 12 Define */
@@ -126,8 +126,8 @@ typedef struct {
  * Enumeration type for the GPIO Function Type
  */
 typedef enum {
-	GPIO_FUNC_IN,   /**< GPIO Input */
-	GPIO_FUNC_OUT,  /**< GPIO Output */
+	GPIO_FUNC_IN, /**< GPIO Input */
+	GPIO_FUNC_OUT, /**< GPIO Output */
 	GPIO_FUNC_ALT1, /**< Alternate Function Selection */
 	GPIO_FUNC_ALT2, /**< Alternate Function Selection */
 	GPIO_FUNC_ALT3, /**< Alternate Function Selection */
@@ -138,8 +138,8 @@ typedef enum {
  * Enumeration type for the type of GPIO pad on a given pin.
  */
 typedef enum {
-	GPIO_PAD_NONE,      /**< No pull-up or pull-down */
-	GPIO_PAD_PULL_UP,   /**< Set pad to weak pull-up */
+	GPIO_PAD_NONE, /**< No pull-up or pull-down */
+	GPIO_PAD_PULL_UP, /**< Set pad to weak pull-up */
 	GPIO_PAD_PULL_DOWN, /**< Set pad to weak pull-down */
 } gpio_pad_t;
 
@@ -147,10 +147,10 @@ typedef enum {
  * Structure type for configuring a GPIO port.
  */
 typedef struct {
-	uint32_t port;    /**< Index of GPIO port */
-	uint32_t mask;    /**< Pin mask (multiple pins may be set) */
+	uint32_t port; /**< Index of GPIO port */
+	uint32_t mask; /**< Pin mask (multiple pins may be set) */
 	gpio_func_t func; /**< Function type */
-	gpio_pad_t pad;   /**< Pad type */
+	gpio_pad_t pad; /**< Pad type */
 } gpio_cfg_t;
 
 typedef enum { GPIO_INTERRUPT_LEVEL, GPIO_INTERRUPT_EDGE } gpio_int_mode_t;
@@ -166,110 +166,110 @@ typedef enum {
 } gpio_int_pol_t;
 
 /* Register offsets for module GPIO */
-#define MXC_R_GPIO_EN                                                          \
-	((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_EN                                                     \
+	((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x000 */
-#define MXC_R_GPIO_EN_SET                                                      \
-	((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_EN_SET                                                 \
+	((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x004 */
-#define MXC_R_GPIO_EN_CLR                                                      \
-	((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_EN_CLR                                                 \
+	((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x008 */
-#define MXC_R_GPIO_OUT_EN                                                      \
-	((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_OUT_EN                                                 \
+	((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x00C */
-#define MXC_R_GPIO_OUT_EN_SET                                                  \
-	((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_OUT_EN_SET                                             \
+	((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x010 */
-#define MXC_R_GPIO_OUT_EN_CLR                                                  \
-	((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_OUT_EN_CLR                                             \
+	((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x014 */
-#define MXC_R_GPIO_OUT                                                         \
-	((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_OUT                                                    \
+	((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x018 */
-#define MXC_R_GPIO_OUT_SET                                                     \
-	((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_OUT_SET                                                \
+	((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x01C */
-#define MXC_R_GPIO_OUT_CLR                                                     \
-	((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_OUT_CLR                                                \
+	((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x020 */
-#define MXC_R_GPIO_IN                                                          \
-	((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_IN                                                     \
+	((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x024 */
-#define MXC_R_GPIO_INT_MOD                                                     \
-	((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_INT_MOD                                                \
+	((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x028 */
-#define MXC_R_GPIO_INT_POL                                                     \
-	((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_INT_POL                                                \
+	((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x02C */
-#define MXC_R_GPIO_INT_EN                                                      \
-	((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_INT_EN                                                 \
+	((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x034 */
-#define MXC_R_GPIO_INT_EN_SET                                                  \
-	((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_INT_EN_SET                                             \
+	((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x038 */
-#define MXC_R_GPIO_INT_EN_CLR                                                  \
-	((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_INT_EN_CLR                                             \
+	((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x03C */
-#define MXC_R_GPIO_INT_STAT                                                    \
-	((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_INT_STAT                                               \
+	((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x040 */
-#define MXC_R_GPIO_INT_CLR                                                     \
-	((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_INT_CLR                                                \
+	((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x048 */
-#define MXC_R_GPIO_WAKE_EN                                                     \
-	((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_WAKE_EN                                                \
+	((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x04C */
-#define MXC_R_GPIO_WAKE_EN_SET                                                 \
-	((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_WAKE_EN_SET                                            \
+	((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x050 */
-#define MXC_R_GPIO_WAKE_EN_CLR                                                 \
-	((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_WAKE_EN_CLR                                            \
+	((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x054 */
-#define MXC_R_GPIO_INT_DUAL_EDGE                                               \
-	((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_INT_DUAL_EDGE                                          \
+	((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x05C */
-#define MXC_R_GPIO_PAD_CFG1                                                    \
-	((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_PAD_CFG1                                               \
+	((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x060 */
-#define MXC_R_GPIO_PAD_CFG2                                                    \
-	((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_PAD_CFG2                                               \
+	((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x064 */
-#define MXC_R_GPIO_EN1                                                         \
-	((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_EN1                                                    \
+	((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x068 */
-#define MXC_R_GPIO_EN1_SET                                                     \
-	((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_EN1_SET                                                \
+	((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x06C */
-#define MXC_R_GPIO_EN1_CLR                                                     \
-	((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_EN1_CLR                                                \
+	((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x070 */
-#define MXC_R_GPIO_EN2                                                         \
-	((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_EN2                                                    \
+	((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x074 */
-#define MXC_R_GPIO_EN2_SET                                                     \
-	((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_EN2_SET                                                \
+	((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x078 */
-#define MXC_R_GPIO_EN2_CLR                                                     \
-	((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_EN2_CLR                                                \
+	((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x07C */
-#define MXC_R_GPIO_IS                                                          \
-	((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_IS                                                     \
+	((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x0A8 */
-#define MXC_R_GPIO_SR                                                          \
-	((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_SR                                                     \
+	((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x0AC */
-#define MXC_R_GPIO_DS                                                          \
-	((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_DS                                                     \
+	((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x0B0 */
-#define MXC_R_GPIO_DS1                                                         \
-	((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_DS1                                                    \
+	((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x0B4 */
-#define MXC_R_GPIO_PS                                                          \
-	((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_PS                                                     \
+	((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x0B8 */
-#define MXC_R_GPIO_VSSEL                                                       \
-	((uint32_t)0x000000C0UL) /**< Offset from GPIO Base Address: <tt>      \
+#define MXC_R_GPIO_VSSEL                                                  \
+	((uint32_t)0x000000C0UL) /**< Offset from GPIO Base Address: <tt> \
 				    0x0x0C0 */
 
 /**
@@ -277,19 +277,26 @@ typedef enum {
  * setting for one GPIO pin on the associated port.
  */
 #define MXC_F_GPIO_EN_GPIO_EN_POS 0 /**< EN_GPIO_EN Position */
-#define MXC_F_GPIO_EN_GPIO_EN                                                  \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_EN_GPIO_EN_POS)) /**< EN_GPIO_EN Mask */
-#define MXC_V_GPIO_EN_GPIO_EN_ALTERNATE                                        \
+#define MXC_F_GPIO_EN_GPIO_EN                                                 \
+	((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN_GPIO_EN_POS)) /**<          \
+								   EN_GPIO_EN \
+								   Mask */
+#define MXC_V_GPIO_EN_GPIO_EN_ALTERNATE \
 	((uint32_t)0x0UL) /**< EN_GPIO_EN_ALTERNATE Value */
-#define MXC_S_GPIO_EN_GPIO_EN_ALTERNATE                                        \
-	(MXC_V_GPIO_EN_GPIO_EN_ALTERNATE                                       \
-	 << MXC_F_GPIO_EN_GPIO_EN_POS) /**< EN_GPIO_EN_ALTERNATE Setting */
-#define MXC_V_GPIO_EN_GPIO_EN_GPIO                                             \
+#define MXC_S_GPIO_EN_GPIO_EN_ALTERNATE                        \
+	(MXC_V_GPIO_EN_GPIO_EN_ALTERNATE                       \
+	 << MXC_F_GPIO_EN_GPIO_EN_POS) /**<                    \
+					  EN_GPIO_EN_ALTERNATE \
+					  Setting              \
+					*/
+#define MXC_V_GPIO_EN_GPIO_EN_GPIO \
 	((uint32_t)0x1UL) /**< EN_GPIO_EN_GPIO Value */
-#define MXC_S_GPIO_EN_GPIO_EN_GPIO                                             \
-	(MXC_V_GPIO_EN_GPIO_EN_GPIO                                            \
-	 << MXC_F_GPIO_EN_GPIO_EN_POS) /**< EN_GPIO_EN_GPIO Setting */
+#define MXC_S_GPIO_EN_GPIO_EN_GPIO                        \
+	(MXC_V_GPIO_EN_GPIO_EN_GPIO                       \
+	 << MXC_F_GPIO_EN_GPIO_EN_POS) /**<               \
+					  EN_GPIO_EN_GPIO \
+					  Setting         \
+					*/
 
 /**
  * GPIO Set Function Enable Register. Writing a 1 to one or more bits
@@ -297,9 +304,10 @@ typedef enum {
  * affecting other bits in that register.
  */
 #define MXC_F_GPIO_EN_SET_ALL_POS 0 /**< EN_SET_ALL Position */
-#define MXC_F_GPIO_EN_SET_ALL                                                  \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_EN_SET_ALL_POS)) /**< EN_SET_ALL Mask */
+#define MXC_F_GPIO_EN_SET_ALL                                                 \
+	((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN_SET_ALL_POS)) /**<          \
+								   EN_SET_ALL \
+								   Mask */
 
 /**
  * GPIO Clear Function Enable Register. Writing a 1 to one or more
@@ -307,33 +315,34 @@ typedef enum {
  * without affecting other bits in that register.
  */
 #define MXC_F_GPIO_EN_CLR_ALL_POS 0 /**< EN_CLR_ALL Position */
-#define MXC_F_GPIO_EN_CLR_ALL                                                  \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_EN_CLR_ALL_POS)) /**< EN_CLR_ALL Mask */
+#define MXC_F_GPIO_EN_CLR_ALL                                                 \
+	((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN_CLR_ALL_POS)) /**<          \
+								   EN_CLR_ALL \
+								   Mask */
 
 /**
  * GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN
  * setting for one GPIO pin in the associated port.
  */
-#define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS                                      \
-	0 /**< OUT_EN_GPIO_OUT_EN Position                                     \
+#define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS  \
+	0 /**< OUT_EN_GPIO_OUT_EN Position \
 	   */
-#define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN                                          \
-	((uint32_t)(                                                           \
-		0xFFFFFFFFUL                                                   \
-		<< MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS)) /**< OUT_EN_GPIO_OUT_EN \
-							  Mask */
-#define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS                                      \
+#define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN                                            \
+	((uint32_t)(0xFFFFFFFFUL                                                 \
+		    << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS)) /**<                  \
+							      OUT_EN_GPIO_OUT_EN \
+							      Mask */
+#define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS \
 	((uint32_t)0x0UL) /**< OUT_EN_GPIO_OUT_EN_DIS Value */
-#define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_DIS                                      \
-	(MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS                                     \
-	 << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_DIS     \
+#define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_DIS                                  \
+	(MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS                                 \
+	 << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_DIS \
 						  Setting */
-#define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN                                       \
+#define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN \
 	((uint32_t)0x1UL) /**< OUT_EN_GPIO_OUT_EN_EN Value */
-#define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_EN                                       \
-	(MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN                                      \
-	 << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_EN      \
+#define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_EN                                  \
+	(MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN                                 \
+	 << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_EN \
 						  Setting */
 
 /**
@@ -342,10 +351,11 @@ typedef enum {
  * GPIO_OUT_EN to 1, without affecting other bits in that register.
  */
 #define MXC_F_GPIO_OUT_EN_SET_ALL_POS 0 /**< OUT_EN_SET_ALL Position */
-#define MXC_F_GPIO_OUT_EN_SET_ALL                                              \
-	((uint32_t)(                                                           \
-		0xFFFFFFFFUL                                                   \
-		<< MXC_F_GPIO_OUT_EN_SET_ALL_POS)) /**< OUT_EN_SET_ALL Mask */
+#define MXC_F_GPIO_OUT_EN_SET_ALL                                        \
+	((uint32_t)(0xFFFFFFFFUL                                         \
+		    << MXC_F_GPIO_OUT_EN_SET_ALL_POS)) /**<              \
+							  OUT_EN_SET_ALL \
+							  Mask */
 
 /**
  * GPIO Output Enable Clear Function Enable Register. Writing a 1 to
@@ -353,10 +363,11 @@ typedef enum {
  * GPIO_OUT_EN to 0, without affecting other bits in that register.
  */
 #define MXC_F_GPIO_OUT_EN_CLR_ALL_POS 0 /**< OUT_EN_CLR_ALL Position */
-#define MXC_F_GPIO_OUT_EN_CLR_ALL                                              \
-	((uint32_t)(                                                           \
-		0xFFFFFFFFUL                                                   \
-		<< MXC_F_GPIO_OUT_EN_CLR_ALL_POS)) /**< OUT_EN_CLR_ALL Mask */
+#define MXC_F_GPIO_OUT_EN_CLR_ALL                                        \
+	((uint32_t)(0xFFFFFFFFUL                                         \
+		    << MXC_F_GPIO_OUT_EN_CLR_ALL_POS)) /**<              \
+							  OUT_EN_CLR_ALL \
+							  Mask */
 
 /**
  * GPIO Output Register. Each bit controls the GPIO_OUT setting for
@@ -364,40 +375,47 @@ typedef enum {
  * directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers.
  */
 #define MXC_F_GPIO_OUT_GPIO_OUT_POS 0 /**< OUT_GPIO_OUT Position */
-#define MXC_F_GPIO_OUT_GPIO_OUT                                                \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_OUT_GPIO_OUT_POS)) /**< OUT_GPIO_OUT Mask */
-#define MXC_V_GPIO_OUT_GPIO_OUT_LOW                                            \
+#define MXC_F_GPIO_OUT_GPIO_OUT                                      \
+	((uint32_t)(0xFFFFFFFFUL                                     \
+		    << MXC_F_GPIO_OUT_GPIO_OUT_POS)) /**<            \
+							OUT_GPIO_OUT \
+							Mask */
+#define MXC_V_GPIO_OUT_GPIO_OUT_LOW \
 	((uint32_t)0x0UL) /**< OUT_GPIO_OUT_LOW Value */
-#define MXC_S_GPIO_OUT_GPIO_OUT_LOW                                            \
-	(MXC_V_GPIO_OUT_GPIO_OUT_LOW                                           \
-	 << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_LOW Setting */
-#define MXC_V_GPIO_OUT_GPIO_OUT_HIGH                                           \
+#define MXC_S_GPIO_OUT_GPIO_OUT_LOW                          \
+	(MXC_V_GPIO_OUT_GPIO_OUT_LOW                         \
+	 << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**<                \
+					    OUT_GPIO_OUT_LOW \
+					    Setting          \
+					  */
+#define MXC_V_GPIO_OUT_GPIO_OUT_HIGH \
 	((uint32_t)0x1UL) /**< OUT_GPIO_OUT_HIGH Value */
-#define MXC_S_GPIO_OUT_GPIO_OUT_HIGH                                           \
-	(MXC_V_GPIO_OUT_GPIO_OUT_HIGH                                          \
-	 << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_HIGH Setting */
+#define MXC_S_GPIO_OUT_GPIO_OUT_HIGH                          \
+	(MXC_V_GPIO_OUT_GPIO_OUT_HIGH                         \
+	 << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**<                 \
+					    OUT_GPIO_OUT_HIGH \
+					    Setting           \
+					  */
 
 /**
  * GPIO Output Set. Writing a 1 to one or more bits in this register
  * sets the bits in the same positions in GPIO_OUT to 1, without affecting other
  * bits in that register.
  */
-#define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS                                    \
+#define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS \
 	0 /**< OUT_SET_GPIO_OUT_SET Position */
-#define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET                                          \
-	((uint32_t)(                                                             \
-		0xFFFFFFFFUL                                                     \
-		<< MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS)) /**<                    \
-							    OUT_SET_GPIO_OUT_SET \
-							    Mask */
-#define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO                                     \
+#define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET                                              \
+	((uint32_t)(0xFFFFFFFFUL                                                     \
+		    << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS)) /**<                    \
+								OUT_SET_GPIO_OUT_SET \
+								Mask */
+#define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO \
 	((uint32_t)0x0UL) /**< OUT_SET_GPIO_OUT_SET_NO Value */
-#define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_NO                                     \
-	(MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO                                    \
-	 << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_NO  \
+#define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_NO                                    \
+	(MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO                                   \
+	 << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_NO \
 						    Setting */
-#define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET                                    \
+#define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET \
 	((uint32_t)0x1UL) /**< OUT_SET_GPIO_OUT_SET_SET Value */
 #define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_SET                                    \
 	(MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET                                   \
@@ -408,49 +426,48 @@ typedef enum {
  * clears the bits in the same positions in GPIO_OUT to 0, without affecting
  * other bits in that register.
  */
-#define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS                                    \
+#define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS \
 	0 /**< OUT_CLR_GPIO_OUT_CLR Position */
-#define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR                                          \
-	((uint32_t)(                                                             \
-		0xFFFFFFFFUL                                                     \
-		<< MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS)) /**<                    \
-							    OUT_CLR_GPIO_OUT_CLR \
-							    Mask */
+#define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR                                              \
+	((uint32_t)(0xFFFFFFFFUL                                                     \
+		    << MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS)) /**<                    \
+								OUT_CLR_GPIO_OUT_CLR \
+								Mask */
 
 /**
  * GPIO Input Register. Read-only register to read from the logic
  * states of the GPIO pins on this port.
  */
 #define MXC_F_GPIO_IN_GPIO_IN_POS 0 /**< IN_GPIO_IN Position */
-#define MXC_F_GPIO_IN_GPIO_IN                                                  \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_IN_GPIO_IN_POS)) /**< IN_GPIO_IN Mask */
+#define MXC_F_GPIO_IN_GPIO_IN                                                 \
+	((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IN_GPIO_IN_POS)) /**<          \
+								   IN_GPIO_IN \
+								   Mask */
 
 /**
  * GPIO Interrupt Mode Register. Each bit in this register controls
  * the interrupt mode setting for the associated GPIO pin on this port.
  */
-#define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS                                    \
+#define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS \
 	0 /**< INT_MOD_GPIO_INT_MOD Position */
-#define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD                                          \
-	((uint32_t)(                                                             \
-		0xFFFFFFFFUL                                                     \
-		<< MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS)) /**<                    \
-							    INT_MOD_GPIO_INT_MOD \
-							    Mask */
-#define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL                                  \
+#define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD                                              \
+	((uint32_t)(0xFFFFFFFFUL                                                     \
+		    << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS)) /**<                    \
+								INT_MOD_GPIO_INT_MOD \
+								Mask */
+#define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL \
 	((uint32_t)0x0UL) /**< INT_MOD_GPIO_INT_MOD_LEVEL Value */
 #define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL                                  \
 	(MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL                                 \
 	 << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**<                          \
 						    INT_MOD_GPIO_INT_MOD_LEVEL \
 						    Setting */
-#define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE                                   \
+#define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE \
 	((uint32_t)0x1UL) /**< INT_MOD_GPIO_INT_MOD_EDGE Value */
-#define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_EDGE                                   \
-	(MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE                                  \
-	 << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**<                          \
-						    INT_MOD_GPIO_INT_MOD_EDGE  \
+#define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_EDGE                                  \
+	(MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE                                 \
+	 << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**<                         \
+						    INT_MOD_GPIO_INT_MOD_EDGE \
 						    Setting */
 
 /**
@@ -458,22 +475,21 @@ typedef enum {
  * controls the interrupt polarity setting for one GPIO pin in the associated
  * port.
  */
-#define MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS                                    \
+#define MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS \
 	0 /**< INT_POL_GPIO_INT_POL Position */
-#define MXC_F_GPIO_INT_POL_GPIO_INT_POL                                          \
-	((uint32_t)(                                                             \
-		0xFFFFFFFFUL                                                     \
-		<< MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS)) /**<                    \
-							    INT_POL_GPIO_INT_POL \
-							    Mask */
-#define MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING                                \
+#define MXC_F_GPIO_INT_POL_GPIO_INT_POL                                              \
+	((uint32_t)(0xFFFFFFFFUL                                                     \
+		    << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS)) /**<                    \
+								INT_POL_GPIO_INT_POL \
+								Mask */
+#define MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING \
 	((uint32_t)0x0UL) /**< INT_POL_GPIO_INT_POL_FALLING Value */
 #define MXC_S_GPIO_INT_POL_GPIO_INT_POL_FALLING                                  \
 	(MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING                                 \
 	 << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) /**<                            \
 						    INT_POL_GPIO_INT_POL_FALLING \
 						    Setting */
-#define MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING                                 \
+#define MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING \
 	((uint32_t)0x1UL) /**< INT_POL_GPIO_INT_POL_RISING Value */
 #define MXC_S_GPIO_INT_POL_GPIO_INT_POL_RISING                                  \
 	(MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING                                 \
@@ -485,25 +501,25 @@ typedef enum {
  * GPIO Interrupt Enable Register. Each bit in this register controls
  * the GPIO interrupt enable for the associated pin on the GPIO port.
  */
-#define MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS                                      \
-	0 /**< INT_EN_GPIO_INT_EN Position                                     \
+#define MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS  \
+	0 /**< INT_EN_GPIO_INT_EN Position \
 	   */
-#define MXC_F_GPIO_INT_EN_GPIO_INT_EN                                          \
-	((uint32_t)(                                                           \
-		0xFFFFFFFFUL                                                   \
-		<< MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS)) /**< INT_EN_GPIO_INT_EN \
-							  Mask */
-#define MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS                                      \
+#define MXC_F_GPIO_INT_EN_GPIO_INT_EN                                            \
+	((uint32_t)(0xFFFFFFFFUL                                                 \
+		    << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS)) /**<                  \
+							      INT_EN_GPIO_INT_EN \
+							      Mask */
+#define MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS \
 	((uint32_t)0x0UL) /**< INT_EN_GPIO_INT_EN_DIS Value */
-#define MXC_S_GPIO_INT_EN_GPIO_INT_EN_DIS                                      \
-	(MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS                                     \
-	 << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_DIS     \
+#define MXC_S_GPIO_INT_EN_GPIO_INT_EN_DIS                                  \
+	(MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS                                 \
+	 << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_DIS \
 						  Setting */
-#define MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN                                       \
+#define MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN \
 	((uint32_t)0x1UL) /**< INT_EN_GPIO_INT_EN_EN Value */
-#define MXC_S_GPIO_INT_EN_GPIO_INT_EN_EN                                       \
-	(MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN                                      \
-	 << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_EN      \
+#define MXC_S_GPIO_INT_EN_GPIO_INT_EN_EN                                  \
+	(MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN                                 \
+	 << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_EN \
 						  Setting */
 
 /**
@@ -511,22 +527,21 @@ typedef enum {
  * register sets the bits in the same positions in GPIO_INT_EN to 1, without
  * affecting other bits in that register.
  */
-#define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS                              \
+#define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS \
 	0 /**< INT_EN_SET_GPIO_INT_EN_SET Position */
-#define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET                                                \
-	((uint32_t)(                                                                         \
-		0xFFFFFFFFUL                                                                 \
-		<< MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS)) /**<                          \
-								  INT_EN_SET_GPIO_INT_EN_SET \
-								  Mask */
-#define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO                               \
+#define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET                                                    \
+	((uint32_t)(0xFFFFFFFFUL                                                                 \
+		    << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS)) /**<                          \
+								      INT_EN_SET_GPIO_INT_EN_SET \
+								      Mask */
+#define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO \
 	((uint32_t)0x0UL) /**< INT_EN_SET_GPIO_INT_EN_SET_NO Value */
 #define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO                                        \
 	(MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO                                       \
 	 << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) /**<                             \
 							  INT_EN_SET_GPIO_INT_EN_SET_NO \
 							  Setting */
-#define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET                              \
+#define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET \
 	((uint32_t)0x1UL) /**< INT_EN_SET_GPIO_INT_EN_SET_SET Value */
 #define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET                                        \
 	(MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET                                       \
@@ -538,22 +553,21 @@ typedef enum {
  * this register clears the bits in the same positions in GPIO_INT_EN to 0,
  * without affecting other bits in that register.
  */
-#define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS                              \
+#define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS \
 	0 /**< INT_EN_CLR_GPIO_INT_EN_CLR Position */
-#define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR                                                \
-	((uint32_t)(                                                                         \
-		0xFFFFFFFFUL                                                                 \
-		<< MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS)) /**<                          \
-								  INT_EN_CLR_GPIO_INT_EN_CLR \
-								  Mask */
-#define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO                               \
+#define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR                                                    \
+	((uint32_t)(0xFFFFFFFFUL                                                                 \
+		    << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS)) /**<                          \
+								      INT_EN_CLR_GPIO_INT_EN_CLR \
+								      Mask */
+#define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO \
 	((uint32_t)0x0UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_NO Value */
 #define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO                                        \
 	(MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO                                       \
 	 << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) /**<                             \
 							  INT_EN_CLR_GPIO_INT_EN_CLR_NO \
 							  Setting */
-#define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR                            \
+#define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR \
 	((uint32_t)0x1UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR Value */
 #define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR                                        \
 	(MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR                                       \
@@ -564,22 +578,21 @@ typedef enum {
  * GPIO Interrupt Status Register. Each bit in this register contains
  * the pending interrupt status for the associated GPIO pin in this port.
  */
-#define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS                                  \
+#define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS \
 	0 /**< INT_STAT_GPIO_INT_STAT Position */
-#define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT                                            \
-	((uint32_t)(                                                                 \
-		0xFFFFFFFFUL                                                         \
-		<< MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS)) /**<                      \
-							      INT_STAT_GPIO_INT_STAT \
-							      Mask */
-#define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO                                   \
+#define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT                                                \
+	((uint32_t)(0xFFFFFFFFUL                                                         \
+		    << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS)) /**<                      \
+								  INT_STAT_GPIO_INT_STAT \
+								  Mask */
+#define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO \
 	((uint32_t)0x0UL) /**< INT_STAT_GPIO_INT_STAT_NO Value */
 #define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_NO                                    \
 	(MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO                                   \
 	 << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) /**<                         \
 						      INT_STAT_GPIO_INT_STAT_NO \
 						      Setting */
-#define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING                              \
+#define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING \
 	((uint32_t)0x1UL) /**< INT_STAT_GPIO_INT_STAT_PENDING Value */
 #define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_PENDING                                    \
 	(MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING                                   \
@@ -593,33 +606,34 @@ typedef enum {
  * affecting other bits in that register.
  */
 #define MXC_F_GPIO_INT_CLR_ALL_POS 0 /**< INT_CLR_ALL Position */
-#define MXC_F_GPIO_INT_CLR_ALL                                                 \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_INT_CLR_ALL_POS)) /**< INT_CLR_ALL Mask */
+#define MXC_F_GPIO_INT_CLR_ALL                                     \
+	((uint32_t)(0xFFFFFFFFUL                                   \
+		    << MXC_F_GPIO_INT_CLR_ALL_POS)) /**<           \
+						       INT_CLR_ALL \
+						       Mask */
 
 /**
  * GPIO Wake Enable Register. Each bit in this register controls the
  * PMU wakeup enable for the associated GPIO pin in this port.
  */
-#define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS                                    \
+#define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS \
 	0 /**< WAKE_EN_GPIO_WAKE_EN Position */
-#define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN                                          \
-	((uint32_t)(                                                             \
-		0xFFFFFFFFUL                                                     \
-		<< MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS)) /**<                    \
-							    WAKE_EN_GPIO_WAKE_EN \
-							    Mask */
-#define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS                                    \
+#define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN                                              \
+	((uint32_t)(0xFFFFFFFFUL                                                     \
+		    << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS)) /**<                    \
+								WAKE_EN_GPIO_WAKE_EN \
+								Mask */
+#define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS \
 	((uint32_t)0x0UL) /**< WAKE_EN_GPIO_WAKE_EN_DIS Value */
 #define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS                                    \
 	(MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS                                   \
 	 << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_DIS \
 						    Setting */
-#define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN                                     \
+#define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN \
 	((uint32_t)0x1UL) /**< WAKE_EN_GPIO_WAKE_EN_EN Value */
-#define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_EN                                     \
-	(MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN                                    \
-	 << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_EN  \
+#define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_EN                                    \
+	(MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN                                   \
+	 << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_EN \
 						    Setting */
 
 /**
@@ -628,9 +642,9 @@ typedef enum {
  * affecting other bits in that register.
  */
 #define MXC_F_GPIO_WAKE_EN_SET_ALL_POS 0 /**< WAKE_EN_SET_ALL Position */
-#define MXC_F_GPIO_WAKE_EN_SET_ALL                                             \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_WAKE_EN_SET_ALL_POS)) /**< WAKE_EN_SET_ALL   \
+#define MXC_F_GPIO_WAKE_EN_SET_ALL                                           \
+	((uint32_t)(0xFFFFFFFFUL                                             \
+		    << MXC_F_GPIO_WAKE_EN_SET_ALL_POS)) /**< WAKE_EN_SET_ALL \
 							   Mask */
 
 /**
@@ -639,32 +653,31 @@ typedef enum {
  * affecting other bits in that register.
  */
 #define MXC_F_GPIO_WAKE_EN_CLR_ALL_POS 0 /**< WAKE_EN_CLR_ALL Position */
-#define MXC_F_GPIO_WAKE_EN_CLR_ALL                                             \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_WAKE_EN_CLR_ALL_POS)) /**< WAKE_EN_CLR_ALL   \
+#define MXC_F_GPIO_WAKE_EN_CLR_ALL                                           \
+	((uint32_t)(0xFFFFFFFFUL                                             \
+		    << MXC_F_GPIO_WAKE_EN_CLR_ALL_POS)) /**< WAKE_EN_CLR_ALL \
 							   Mask */
 
 /**
  * GPIO Interrupt Dual Edge Mode Register. Each bit in this register
  * selects dual edge mode for the associated GPIO pin in this port.
  */
-#define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS                        \
+#define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS \
 	0 /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE Position */
-#define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE                                                      \
-	((uint32_t)(                                                                                     \
-		0xFFFFFFFFUL                                                                             \
-		<< MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS)) /**<                                \
-									INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE \
-									Mask                             \
-								      */
-#define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO                         \
+#define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE                                                          \
+	((uint32_t)(0xFFFFFFFFUL                                                                             \
+		    << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS)) /**<                                \
+									    INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE \
+									    Mask                             \
+									  */
+#define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO \
 	((uint32_t)0x0UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO Value */
 #define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO                                              \
 	(MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO                                             \
 	 << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) /**<                                   \
 								INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO \
 								Setting */
-#define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN                         \
+#define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN \
 	((uint32_t)0x1UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN Value */
 #define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN                                              \
 	(MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN                                             \
@@ -676,29 +689,28 @@ typedef enum {
  * GPIO Input Mode Config 1. Each bit in this register enables the
  * weak pull-up for the associated GPIO pin in this port.
  */
-#define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS                                  \
+#define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS \
 	0 /**< PAD_CFG1_GPIO_PAD_CFG1 Position */
-#define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1                                            \
-	((uint32_t)(                                                                 \
-		0xFFFFFFFFUL                                                         \
-		<< MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS)) /**<                      \
-							      PAD_CFG1_GPIO_PAD_CFG1 \
-							      Mask */
-#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE                            \
+#define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1                                                \
+	((uint32_t)(0xFFFFFFFFUL                                                         \
+		    << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS)) /**<                      \
+								  PAD_CFG1_GPIO_PAD_CFG1 \
+								  Mask */
+#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE \
 	((uint32_t)0x0UL) /**< PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE Value */
 #define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE                                    \
 	(MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE                                   \
 	 << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**<                                \
 						      PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE \
 						      Setting */
-#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU                                   \
+#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU \
 	((uint32_t)0x1UL) /**< PAD_CFG1_GPIO_PAD_CFG1_PU Value */
 #define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU                                    \
 	(MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU                                   \
 	 << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**<                         \
 						      PAD_CFG1_GPIO_PAD_CFG1_PU \
 						      Setting */
-#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD                                   \
+#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD \
 	((uint32_t)0x2UL) /**< PAD_CFG1_GPIO_PAD_CFG1_PD Value */
 #define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD                                    \
 	(MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD                                   \
@@ -710,29 +722,28 @@ typedef enum {
  * GPIO Input Mode Config 2. Each bit in this register enables the
  * weak pull-up for the associated GPIO pin in this port.
  */
-#define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS                                  \
+#define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS \
 	0 /**< PAD_CFG2_GPIO_PAD_CFG2 Position */
-#define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2                                            \
-	((uint32_t)(                                                                 \
-		0xFFFFFFFFUL                                                         \
-		<< MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS)) /**<                      \
-							      PAD_CFG2_GPIO_PAD_CFG2 \
-							      Mask */
-#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE                            \
+#define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2                                                \
+	((uint32_t)(0xFFFFFFFFUL                                                         \
+		    << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS)) /**<                      \
+								  PAD_CFG2_GPIO_PAD_CFG2 \
+								  Mask */
+#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE \
 	((uint32_t)0x0UL) /**< PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE Value */
 #define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE                                    \
 	(MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE                                   \
 	 << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**<                                \
 						      PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE \
 						      Setting */
-#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU                                   \
+#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU \
 	((uint32_t)0x1UL) /**< PAD_CFG2_GPIO_PAD_CFG2_PU Value */
 #define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU                                    \
 	(MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU                                   \
 	 << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**<                         \
 						      PAD_CFG2_GPIO_PAD_CFG2_PU \
 						      Setting */
-#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD                                   \
+#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD \
 	((uint32_t)0x2UL) /**< PAD_CFG2_GPIO_PAD_CFG2_PD Value */
 #define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD                                    \
 	(MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD                                   \
@@ -746,19 +757,24 @@ typedef enum {
  * this port.
  */
 #define MXC_F_GPIO_EN1_GPIO_EN1_POS 0 /**< EN1_GPIO_EN1 Position */
-#define MXC_F_GPIO_EN1_GPIO_EN1                                                \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_EN1_GPIO_EN1_POS)) /**< EN1_GPIO_EN1 Mask */
-#define MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY                                        \
+#define MXC_F_GPIO_EN1_GPIO_EN1                                      \
+	((uint32_t)(0xFFFFFFFFUL                                     \
+		    << MXC_F_GPIO_EN1_GPIO_EN1_POS)) /**<            \
+							EN1_GPIO_EN1 \
+							Mask */
+#define MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY \
 	((uint32_t)0x0UL) /**< EN1_GPIO_EN1_PRIMARY Value */
-#define MXC_S_GPIO_EN1_GPIO_EN1_PRIMARY                                        \
-	(MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY                                       \
-	 << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_PRIMARY Setting */
-#define MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY                                      \
+#define MXC_S_GPIO_EN1_GPIO_EN1_PRIMARY                          \
+	(MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY                         \
+	 << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**<                    \
+					    EN1_GPIO_EN1_PRIMARY \
+					    Setting              \
+					  */
+#define MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY \
 	((uint32_t)0x1UL) /**< EN1_GPIO_EN1_SECONDARY Value */
-#define MXC_S_GPIO_EN1_GPIO_EN1_SECONDARY                                      \
-	(MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY                                     \
-	 << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_SECONDARY Setting   \
+#define MXC_S_GPIO_EN1_GPIO_EN1_SECONDARY                                    \
+	(MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY                                   \
+	 << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_SECONDARY Setting \
 					  */
 
 /**
@@ -767,9 +783,11 @@ typedef enum {
  * affecting other bits in that register.
  */
 #define MXC_F_GPIO_EN1_SET_ALL_POS 0 /**< EN1_SET_ALL Position */
-#define MXC_F_GPIO_EN1_SET_ALL                                                 \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_EN1_SET_ALL_POS)) /**< EN1_SET_ALL Mask */
+#define MXC_F_GPIO_EN1_SET_ALL                                     \
+	((uint32_t)(0xFFFFFFFFUL                                   \
+		    << MXC_F_GPIO_EN1_SET_ALL_POS)) /**<           \
+						       EN1_SET_ALL \
+						       Mask */
 
 /**
  * GPIO Alternate Function Clear. Writing a 1 to one or more bits in
@@ -777,9 +795,11 @@ typedef enum {
  * affecting other bits in that register.
  */
 #define MXC_F_GPIO_EN1_CLR_ALL_POS 0 /**< EN1_CLR_ALL Position */
-#define MXC_F_GPIO_EN1_CLR_ALL                                                 \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_EN1_CLR_ALL_POS)) /**< EN1_CLR_ALL Mask */
+#define MXC_F_GPIO_EN1_CLR_ALL                                     \
+	((uint32_t)(0xFFFFFFFFUL                                   \
+		    << MXC_F_GPIO_EN1_CLR_ALL_POS)) /**<           \
+						       EN1_CLR_ALL \
+						       Mask */
 
 /**
  * GPIO Alternate Function Enable Register. Each bit in this register
@@ -787,19 +807,24 @@ typedef enum {
  * this port.
  */
 #define MXC_F_GPIO_EN2_GPIO_EN2_POS 0 /**< EN2_GPIO_EN2 Position */
-#define MXC_F_GPIO_EN2_GPIO_EN2                                                \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_EN2_GPIO_EN2_POS)) /**< EN2_GPIO_EN2 Mask */
-#define MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY                                        \
+#define MXC_F_GPIO_EN2_GPIO_EN2                                      \
+	((uint32_t)(0xFFFFFFFFUL                                     \
+		    << MXC_F_GPIO_EN2_GPIO_EN2_POS)) /**<            \
+							EN2_GPIO_EN2 \
+							Mask */
+#define MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY \
 	((uint32_t)0x0UL) /**< EN2_GPIO_EN2_PRIMARY Value */
-#define MXC_S_GPIO_EN2_GPIO_EN2_PRIMARY                                        \
-	(MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY                                       \
-	 << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_PRIMARY Setting */
-#define MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY                                      \
+#define MXC_S_GPIO_EN2_GPIO_EN2_PRIMARY                          \
+	(MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY                         \
+	 << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**<                    \
+					    EN2_GPIO_EN2_PRIMARY \
+					    Setting              \
+					  */
+#define MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY \
 	((uint32_t)0x1UL) /**< EN2_GPIO_EN2_SECONDARY Value */
-#define MXC_S_GPIO_EN2_GPIO_EN2_SECONDARY                                      \
-	(MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY                                     \
-	 << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_SECONDARY Setting   \
+#define MXC_S_GPIO_EN2_GPIO_EN2_SECONDARY                                    \
+	(MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY                                   \
+	 << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_SECONDARY Setting \
 					  */
 
 /**
@@ -808,9 +833,11 @@ typedef enum {
  * affecting other bits in that register.
  */
 #define MXC_F_GPIO_EN2_SET_ALL_POS 0 /**< EN2_SET_ALL Position */
-#define MXC_F_GPIO_EN2_SET_ALL                                                 \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_EN2_SET_ALL_POS)) /**< EN2_SET_ALL Mask */
+#define MXC_F_GPIO_EN2_SET_ALL                                     \
+	((uint32_t)(0xFFFFFFFFUL                                   \
+		    << MXC_F_GPIO_EN2_SET_ALL_POS)) /**<           \
+						       EN2_SET_ALL \
+						       Mask */
 
 /**
  * GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits
@@ -818,9 +845,11 @@ typedef enum {
  * without affecting other bits in that register.
  */
 #define MXC_F_GPIO_EN2_CLR_ALL_POS 0 /**< EN2_CLR_ALL Position */
-#define MXC_F_GPIO_EN2_CLR_ALL                                                 \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_EN2_CLR_ALL_POS)) /**< EN2_CLR_ALL Mask */
+#define MXC_F_GPIO_EN2_CLR_ALL                                     \
+	((uint32_t)(0xFFFFFFFFUL                                   \
+		    << MXC_F_GPIO_EN2_CLR_ALL_POS)) /**<           \
+						       EN2_CLR_ALL \
+						       Mask */
 
 /**
  * GPIO Drive Strength  Register. Each bit in this register selects
@@ -828,13 +857,13 @@ typedef enum {
  * Datasheet for sink/source current of GPIO pins in each mode.
  */
 #define MXC_F_GPIO_DS_DS_POS 0 /**< DS_DS Position */
-#define MXC_F_GPIO_DS_DS                                                       \
+#define MXC_F_GPIO_DS_DS \
 	((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS_DS_POS)) /**< DS_DS Mask */
 #define MXC_V_GPIO_DS_DS_LD ((uint32_t)0x0UL) /**< DS_DS_LD Value */
-#define MXC_S_GPIO_DS_DS_LD                                                    \
+#define MXC_S_GPIO_DS_DS_LD \
 	(MXC_V_GPIO_DS_DS_LD << MXC_F_GPIO_DS_DS_POS) /**< DS_DS_LD Setting */
-#define MXC_V_GPIO_DS_DS_HD ((uint32_t)0x1UL)	 /**< DS_DS_HD Value */
-#define MXC_S_GPIO_DS_DS_HD                                                    \
+#define MXC_V_GPIO_DS_DS_HD ((uint32_t)0x1UL) /**< DS_DS_HD Value */
+#define MXC_S_GPIO_DS_DS_HD \
 	(MXC_V_GPIO_DS_DS_HD << MXC_F_GPIO_DS_DS_POS) /**< DS_DS_HD Setting */
 
 /**
@@ -844,23 +873,23 @@ typedef enum {
  */
 #define MXC_F_GPIO_DS1_ALL_POS 0 /**< DS1_ALL Position */
 #define MXC_F_GPIO_DS1_ALL                                                     \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_DS1_ALL_POS)) /**< DS1_ALL Mask */
+	((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS1_ALL_POS)) /**< DS1_ALL Mask \
+							      */
 
 /**
  * GPIO Pull Select Mode.
  */
 #define MXC_F_GPIO_PS_ALL_POS 0 /**< PS_ALL Position */
-#define MXC_F_GPIO_PS_ALL                                                      \
-	((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PS_ALL_POS)) /**< PS_ALL Mask   \
+#define MXC_F_GPIO_PS_ALL                                                    \
+	((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PS_ALL_POS)) /**< PS_ALL Mask \
 							     */
 
 /**
  * GPIO Voltage Select.
  */
 #define MXC_F_GPIO_VSSEL_ALL_POS 0 /**< VSSEL_ALL Position */
-#define MXC_F_GPIO_VSSEL_ALL                                                   \
-	((uint32_t)(0xFFFFFFFFUL                                               \
-		    << MXC_F_GPIO_VSSEL_ALL_POS)) /**< VSSEL_ALL Mask */
+#define MXC_F_GPIO_VSSEL_ALL                                                  \
+	((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_VSSEL_ALL_POS)) /**< VSSEL_ALL \
+								  Mask */
 
 #endif /* _GPIO_REGS_H_ */
diff --git a/chip/max32660/hwtimer_chip.c b/chip/max32660/hwtimer_chip.c
index 5417e161b2..a6469ae795 100644
--- a/chip/max32660/hwtimer_chip.c
+++ b/chip/max32660/hwtimer_chip.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -41,36 +41,36 @@ static uint32_t last_deadline;
 
 /* brief Timer prescaler values */
 enum tmr_pres {
-	TMR_PRES_1 = MXC_V_TMR_CN_PRES_DIV1,     /// Divide input clock by 1
-	TMR_PRES_2 = MXC_V_TMR_CN_PRES_DIV2,     /// Divide input clock by 2
-	TMR_PRES_4 = MXC_V_TMR_CN_PRES_DIV4,     /// Divide input clock by 4
-	TMR_PRES_8 = MXC_V_TMR_CN_PRES_DIV8,     /// Divide input clock by 8
-	TMR_PRES_16 = MXC_V_TMR_CN_PRES_DIV16,   /// Divide input clock by 16
-	TMR_PRES_32 = MXC_V_TMR_CN_PRES_DIV32,   /// Divide input clock by 32
-	TMR_PRES_64 = MXC_V_TMR_CN_PRES_DIV64,   /// Divide input clock by 64
+	TMR_PRES_1 = MXC_V_TMR_CN_PRES_DIV1, /// Divide input clock by 1
+	TMR_PRES_2 = MXC_V_TMR_CN_PRES_DIV2, /// Divide input clock by 2
+	TMR_PRES_4 = MXC_V_TMR_CN_PRES_DIV4, /// Divide input clock by 4
+	TMR_PRES_8 = MXC_V_TMR_CN_PRES_DIV8, /// Divide input clock by 8
+	TMR_PRES_16 = MXC_V_TMR_CN_PRES_DIV16, /// Divide input clock by 16
+	TMR_PRES_32 = MXC_V_TMR_CN_PRES_DIV32, /// Divide input clock by 32
+	TMR_PRES_64 = MXC_V_TMR_CN_PRES_DIV64, /// Divide input clock by 64
 	TMR_PRES_128 = MXC_V_TMR_CN_PRES_DIV128, /// Divide input clock by 128
-	TMR_PRES_256 =
-		(0x20 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock by 256
-	TMR_PRES_512 =
-		(0x21 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock by 512
-	TMR_PRES_1024 =
-		(0x22 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock by 1024
-	TMR_PRES_2048 =
-		(0x23 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock by 2048
-	TMR_PRES_4096 =
-		(0x24 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock by 4096
+	TMR_PRES_256 = (0x20 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock
+							/// by 256
+	TMR_PRES_512 = (0x21 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock
+							/// by 512
+	TMR_PRES_1024 = (0x22 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock
+							 /// by 1024
+	TMR_PRES_2048 = (0x23 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock
+							 /// by 2048
+	TMR_PRES_4096 = (0x24 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock
+							 /// by 4096
 };
 
 /* Timer modes */
 enum tmr_mode {
 	TMR_MODE_ONESHOT = MXC_V_TMR_CN_TMODE_ONESHOT, /// Timer Mode ONESHOT
-	TMR_MODE_CONTINUOUS =
-		MXC_V_TMR_CN_TMODE_CONTINUOUS,	 /// Timer Mode CONTINUOUS
+	TMR_MODE_CONTINUOUS = MXC_V_TMR_CN_TMODE_CONTINUOUS, /// Timer Mode
+							     /// CONTINUOUS
 	TMR_MODE_COUNTER = MXC_V_TMR_CN_TMODE_COUNTER, /// Timer Mode COUNTER
-	TMR_MODE_PWM = MXC_V_TMR_CN_TMODE_PWM,	 /// Timer Mode PWM
+	TMR_MODE_PWM = MXC_V_TMR_CN_TMODE_PWM, /// Timer Mode PWM
 	TMR_MODE_CAPTURE = MXC_V_TMR_CN_TMODE_CAPTURE, /// Timer Mode CAPTURE
 	TMR_MODE_COMPARE = MXC_V_TMR_CN_TMODE_COMPARE, /// Timer Mode COMPARE
-	TMR_MODE_GATED = MXC_V_TMR_CN_TMODE_GATED,     /// Timer Mode GATED
+	TMR_MODE_GATED = MXC_V_TMR_CN_TMODE_GATED, /// Timer Mode GATED
 	TMR_MODE_CAPTURE_COMPARE =
 		MXC_V_TMR_CN_TMODE_CAPTURECOMPARE /// Timer Mode CAPTURECOMPARE
 };
@@ -220,7 +220,7 @@ int __hw_clock_source_init(uint32_t start_t)
 	return TMR_EVENT_IRQ;
 }
 
-static int hwtimer_display(int argc, char **argv)
+static int hwtimer_display(int argc, const char **argv)
 {
 	CPRINTS(" TMR_EVENT count 0x%08x", TMR_EVENT->cnt);
 	CPRINTS(" TMR_ROLLOVER count 0x%08x", TMR_ROLLOVER->cnt);
diff --git a/chip/max32660/i2c_chip.c b/chip/max32660/i2c_chip.c
index 4daaf31207..bb116f4d8a 100644
--- a/chip/max32660/i2c_chip.c
+++ b/chip/max32660/i2c_chip.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,9 +25,9 @@
 #define EC_PADDING_BYTE 0xec
 
 /* **** Definitions **** */
-#define I2C_ERROR \
-	(MXC_F_I2C_INT_FL0_ARB_ER | MXC_F_I2C_INT_FL0_TO_ER | \
-	 MXC_F_I2C_INT_FL0_ADDR_NACK_ER | MXC_F_I2C_INT_FL0_DATA_ER | \
+#define I2C_ERROR                                                        \
+	(MXC_F_I2C_INT_FL0_ARB_ER | MXC_F_I2C_INT_FL0_TO_ER |            \
+	 MXC_F_I2C_INT_FL0_ADDR_NACK_ER | MXC_F_I2C_INT_FL0_DATA_ER |    \
 	 MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER | MXC_F_I2C_INT_FL0_START_ER | \
 	 MXC_F_I2C_INT_FL0_STOP_ER)
 
@@ -35,7 +35,7 @@
 #define T_HIGH_MIN (60) /* tHIGH minimum in nanoseconds */
 #define T_R_MAX_HS (40) /* tR maximum for high speed mode in nanoseconds */
 #define T_F_MAX_HS (40) /* tF maximum for high speed mode in nanoseconds */
-#define T_AF_MIN (10)	/* tAF minimun in nanoseconds */
+#define T_AF_MIN (10) /* tAF minimun in nanoseconds */
 
 /**
  * typedef i2c_speed_t - I2C speed modes.
@@ -170,10 +170,10 @@ static struct i2c_port_data pdata[I2C_PORT_COUNT];
 /* **** Function Prototypes **** */
 static int i2c_init_peripheral(mxc_i2c_regs_t *i2c, i2c_speed_t i2cspeed);
 static int i2c_controller_write(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
-			    int stop, const uint8_t *data, int len,
-			    int restart);
+				int stop, const uint8_t *data, int len,
+				int restart);
 static int i2c_controller_read(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
-			   int stop, uint8_t *data, int len, int restart);
+			       int stop, uint8_t *data, int len, int restart);
 
 #ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
 static void init_i2cs(int port);
@@ -182,7 +182,7 @@ static void i2c_target_handler(mxc_i2c_regs_t *i2c);
 #endif /* CONFIG_HOSTCMD_I2C_ADDR_FLAGS */
 
 /* Port address for each I2C */
-static mxc_i2c_regs_t *i2c_bus_ports[] = {MXC_I2C0, MXC_I2C1};
+static mxc_i2c_regs_t *i2c_bus_ports[] = { MXC_I2C0, MXC_I2C1 };
 
 #ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
 
@@ -224,15 +224,16 @@ int chip_i2c_xfer(int port, const uint16_t addr_flags, const uint8_t *out,
 
 	if (out_size) {
 		status = i2c_controller_write(i2c_bus_ports[port], addr_flags,
-					  xfer_start, xfer_stop, out, out_size,
-					  1);
+					      xfer_start, xfer_stop, out,
+					      out_size, 1);
 		if (status != EC_SUCCESS) {
 			return status;
 		}
 	}
 	if (in_size) {
 		status = i2c_controller_read(i2c_bus_ports[port], addr_flags,
-					 xfer_start, xfer_stop, in, in_size, 0);
+					     xfer_start, xfer_stop, in, in_size,
+					     0);
 		if (status != EC_SUCCESS) {
 			return status;
 		}
@@ -301,7 +302,6 @@ void i2c_init(void)
 		CONFIG_BOARD_I2C_ADDR_FLAGS;
 #endif /* CONFIG_BOARD_I2C_ADDR_FLAGS */
 #endif /* CONFIG_HOSTCMD_I2C_ADDR_FLAGS */
-
 }
 
 /**
@@ -309,7 +309,7 @@ void i2c_init(void)
  */
 #ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
 /* IRQ for each I2C */
-static uint32_t i2c_bus_irqs[] = {EC_I2C0_IRQn, EC_I2C1_IRQn};
+static uint32_t i2c_bus_irqs[] = { EC_I2C0_IRQn, EC_I2C1_IRQn };
 
 /**
  * Buffer for received host command packets (including prefix byte on request,
@@ -398,9 +398,9 @@ void i2c_target_service(i2c_req_t *req)
 		req->tx_remain = -1;
 #ifdef CONFIG_BOARD_I2C_ADDR_FLAGS
 		if (req->addr_match_flag != 0x1) {
-			i2c_process_board_command(
-				0, CONFIG_BOARD_I2C_ADDR_FLAGS,
-				req->received_count);
+			i2c_process_board_command(0,
+						  CONFIG_BOARD_I2C_ADDR_FLAGS,
+						  req->received_count);
 		} else
 #endif /* CONFIG_BOARD_I2C_ADDR_FLAGS */
 		{
@@ -440,8 +440,9 @@ static void i2c_target_service_read(mxc_i2c_regs_t *i2c, i2c_req_t *req)
 	 * a possible done bit, address match, or multiple target address
 	 * flags.
 	 */
-	i2c->int_fl0 = i2c->int_fl0 & ~(MXC_F_I2C_INT_FL0_ADDR_MATCH |
-		MXC_F_I2C_INT_FL0_MAMI_MASK | MXC_F_I2C_INT_FL0_DONE);
+	i2c->int_fl0 = i2c->int_fl0 &
+		       ~(MXC_F_I2C_INT_FL0_ADDR_MATCH |
+			 MXC_F_I2C_INT_FL0_MAMI_MASK | MXC_F_I2C_INT_FL0_DONE);
 	i2c->int_fl1 = i2c->int_fl1;
 	/*
 	 * If there is nothing to transmit to the EC HOST, then default
@@ -459,7 +460,7 @@ static void i2c_target_service_read(mxc_i2c_regs_t *i2c, i2c_req_t *req)
 		req->response_pending = false;
 		/* Fill the FIFO with data to transimit to the I2C Controller */
 		while ((req->tx_remain > 0) &&
-			!(i2c->status & MXC_F_I2C_STATUS_TX_FULL)) {
+		       !(i2c->status & MXC_F_I2C_STATUS_TX_FULL)) {
 			i2c->fifo = *(req->tx_data)++;
 			req->tx_remain--;
 		}
@@ -477,10 +478,10 @@ static void i2c_target_service_read(mxc_i2c_regs_t *i2c, i2c_req_t *req)
 	}
 	/* Set the threshold for TX, the threshold is a four bit field. */
 	i2c->tx_ctrl0 = ((i2c->tx_ctrl0 & ~(MXC_F_I2C_TX_CTRL0_TX_THRESH)) |
-			(2 << MXC_F_I2C_TX_CTRL0_TX_THRESH_POS));
+			 (2 << MXC_F_I2C_TX_CTRL0_TX_THRESH_POS));
 	/* Enable interrupts of interest. */
 	i2c->int_en0 = MXC_F_I2C_INT_EN0_TX_THRESH | MXC_F_I2C_INT_EN0_DONE |
-			I2C_ERROR | MXC_F_I2C_INT_EN0_ADDR_MATCH;
+		       I2C_ERROR | MXC_F_I2C_INT_EN0_ADDR_MATCH;
 }
 
 /**
@@ -491,8 +492,9 @@ static void i2c_target_service_read(mxc_i2c_regs_t *i2c, i2c_req_t *req)
 static void i2c_target_service_write(mxc_i2c_regs_t *i2c, i2c_req_t *req)
 {
 	/* Clear all flags except address matching and done. */
-	i2c->int_fl0 = i2c->int_fl0 & ~(MXC_F_I2C_INT_FL0_ADDR_MATCH |
-		MXC_F_I2C_INT_FL0_MAMI_MASK | MXC_F_I2C_INT_FL0_DONE);
+	i2c->int_fl0 = i2c->int_fl0 &
+		       ~(MXC_F_I2C_INT_FL0_ADDR_MATCH |
+			 MXC_F_I2C_INT_FL0_MAMI_MASK | MXC_F_I2C_INT_FL0_DONE);
 	i2c->int_fl1 = i2c->int_fl1;
 	/* Read out any data in the RX FIFO. */
 	while (!(i2c->status & MXC_F_I2C_STATUS_RX_EMPTY)) {
@@ -500,13 +502,12 @@ static void i2c_target_service_write(mxc_i2c_regs_t *i2c, i2c_req_t *req)
 		req->received_count++;
 	}
 	/* Set the RX threshold interrupt level. */
-	i2c->rx_ctrl0 = ((i2c->rx_ctrl0 &
-			~(MXC_F_I2C_RX_CTRL0_RX_THRESH)) |
-			(MXC_I2C_FIFO_DEPTH - 1)
-				<< MXC_F_I2C_RX_CTRL0_RX_THRESH_POS);
+	i2c->rx_ctrl0 =
+		((i2c->rx_ctrl0 & ~(MXC_F_I2C_RX_CTRL0_RX_THRESH)) |
+		 (MXC_I2C_FIFO_DEPTH - 1) << MXC_F_I2C_RX_CTRL0_RX_THRESH_POS);
 	/* Enable interrupts of interest. */
 	i2c->int_en0 = MXC_F_I2C_INT_EN0_RX_THRESH | MXC_F_I2C_INT_EN0_DONE |
-			I2C_ERROR | MXC_F_I2C_INT_EN0_ADDR_MATCH;
+		       I2C_ERROR | MXC_F_I2C_INT_EN0_ADDR_MATCH;
 }
 
 /**
@@ -525,15 +526,15 @@ static void i2c_target_handler(mxc_i2c_regs_t *i2c)
 	/* Get the request context for this interrupt. */
 	req = states[MXC_I2C_GET_IDX(i2c)].req;
 
-
 	/* Check for an address match flag. */
-	if ((req->expecting_start) && (i2c->int_fl0 & MXC_F_I2C_INT_FL0_ADDR_MATCH)) {
+	if ((req->expecting_start) &&
+	    (i2c->int_fl0 & MXC_F_I2C_INT_FL0_ADDR_MATCH)) {
 		req->expecting_done = true;
 		req->expecting_start = false;
 		/*
-		* Save the address match index to identify
-		* targeted target address.
-		*/
+		 * Save the address match index to identify
+		 * targeted target address.
+		 */
 		req->addr_match_flag =
 			(i2c->int_fl0 & MXC_F_I2C_INT_FL0_MAMI_MASK) >>
 			MXC_F_I2C_INT_FL0_MAMI_POS;
@@ -543,8 +544,8 @@ static void i2c_target_handler(mxc_i2c_regs_t *i2c)
 		i2c->int_fl1 = i2c->int_fl1;
 
 		/* Only enable done, error and address match interrupts. */
-		i2c->int_en0 = MXC_F_I2C_INT_EN0_DONE |
-			I2C_ERROR | MXC_F_I2C_INT_EN0_ADDR_MATCH;
+		i2c->int_en0 = MXC_F_I2C_INT_EN0_DONE | I2C_ERROR |
+			       MXC_F_I2C_INT_EN0_ADDR_MATCH;
 
 		/* Check if Controller is writing to the target. */
 		if (!(i2c->ctrl & MXC_F_I2C_CTRL_READ)) {
@@ -564,10 +565,11 @@ static void i2c_target_handler(mxc_i2c_regs_t *i2c)
 			 */
 			req->response_pending = false;
 			/* Set the RX threshold interrupt level. */
-			i2c->rx_ctrl0 = ((i2c->rx_ctrl0 &
-					~(MXC_F_I2C_RX_CTRL0_RX_THRESH)) |
-					(MXC_I2C_FIFO_DEPTH - 2)
-						<< MXC_F_I2C_RX_CTRL0_RX_THRESH_POS);
+			i2c->rx_ctrl0 =
+				((i2c->rx_ctrl0 &
+				  ~(MXC_F_I2C_RX_CTRL0_RX_THRESH)) |
+				 (MXC_I2C_FIFO_DEPTH - 2)
+					 << MXC_F_I2C_RX_CTRL0_RX_THRESH_POS);
 		} else {
 			/*
 			 * The Controller is reading from the target.
@@ -576,25 +578,28 @@ static void i2c_target_handler(mxc_i2c_regs_t *i2c)
 			 */
 			req->tx_data = host_buffer;
 			req->state = I2C_TARGET_ADDR_MATCH_READ;
-			/* Set the threshold for TX, the threshold is a four bit field. */
-			i2c->tx_ctrl0 = ((i2c->tx_ctrl0 & ~(MXC_F_I2C_TX_CTRL0_TX_THRESH)) |
-				(2 << MXC_F_I2C_TX_CTRL0_TX_THRESH_POS));
+			/* Set the threshold for TX, the threshold is a four bit
+			 * field. */
+			i2c->tx_ctrl0 =
+				((i2c->tx_ctrl0 &
+				  ~(MXC_F_I2C_TX_CTRL0_TX_THRESH)) |
+				 (2 << MXC_F_I2C_TX_CTRL0_TX_THRESH_POS));
 #ifdef CONFIG_BOARD_I2C_ADDR_FLAGS
 			/*
-			* If this is a board address match and there is not
-			* already a pending response to the I2C Controller then
-			* fulfill this board read request.
-			*/
+			 * If this is a board address match and there is not
+			 * already a pending response to the I2C Controller then
+			 * fulfill this board read request.
+			 */
 			if ((req->response_pending == 0) &&
-				(req->addr_match_flag != 0x1)) {
+			    (req->addr_match_flag != 0x1)) {
 				i2c_process_board_command(
 					1, CONFIG_BOARD_I2C_ADDR_FLAGS, 0);
 			}
 #endif /* CONFIG_BOARD_I2C_ADDR_FLAGS */
 		}
 		/* Only enable done, error and address match interrupts. */
-		i2c->int_en0 = MXC_F_I2C_INT_EN0_DONE |
-			I2C_ERROR | MXC_F_I2C_INT_EN0_ADDR_MATCH;
+		i2c->int_en0 = MXC_F_I2C_INT_EN0_DONE | I2C_ERROR |
+			       MXC_F_I2C_INT_EN0_ADDR_MATCH;
 		/* Inhibit sleep mode when addressed until STOPF flag is set. */
 		disable_sleep(SLEEP_MASK_I2C_PERIPHERAL);
 	}
@@ -605,14 +610,15 @@ static void i2c_target_handler(mxc_i2c_regs_t *i2c)
 		req->expecting_done = false;
 		/* Clear all interrupts except a possible address match. */
 		i2c->int_fl0 = i2c->int_fl0 & ~(MXC_F_I2C_INT_FL0_ADDR_MATCH |
-			MXC_F_I2C_INT_FL0_MAMI_MASK);
+						MXC_F_I2C_INT_FL0_MAMI_MASK);
 		i2c->int_fl1 = i2c->int_fl1;
 
 		/* Only enable done, error and address match interrupts. */
-		i2c->int_en0 = MXC_F_I2C_INT_EN0_DONE |
-			I2C_ERROR | MXC_F_I2C_INT_EN0_ADDR_MATCH;
+		i2c->int_en0 = MXC_F_I2C_INT_EN0_DONE | I2C_ERROR |
+			       MXC_F_I2C_INT_EN0_ADDR_MATCH;
 		i2c->int_en1 = 0;
-		/* If this was a DONE after a write then read the fifo until empty. */
+		/* If this was a DONE after a write then read the fifo until
+		 * empty. */
 		if (req->state == I2C_TARGET_ADDR_MATCH_WRITE) {
 			/* Read out any data in the RX FIFO. */
 			while (!(i2c->status & MXC_F_I2C_STATUS_RX_EMPTY)) {
@@ -654,7 +660,6 @@ static void i2c_target_handler(mxc_i2c_regs_t *i2c)
 		/* Service a write request from the I2C Controller. */
 		i2c_target_service_write(i2c, req);
 	}
-
 }
 
 /**
@@ -713,10 +718,9 @@ static int i2c_target_async(mxc_i2c_regs_t *i2c, i2c_req_t *req)
 	i2c->int_fl1 = i2c->int_fl1;
 
 	/* Set the RX threshold interrupt level. */
-	i2c->rx_ctrl0 = ((i2c->rx_ctrl0 &
-			~(MXC_F_I2C_RX_CTRL0_RX_THRESH)) |
-			(MXC_I2C_FIFO_DEPTH - 2)
-				<< MXC_F_I2C_RX_CTRL0_RX_THRESH_POS);
+	i2c->rx_ctrl0 =
+		((i2c->rx_ctrl0 & ~(MXC_F_I2C_RX_CTRL0_RX_THRESH)) |
+		 (MXC_I2C_FIFO_DEPTH - 2) << MXC_F_I2C_RX_CTRL0_RX_THRESH_POS);
 
 	/* Only enable the I2C Address match interrupt. */
 	i2c->int_en0 = MXC_F_I2C_INT_EN0_ADDR_MATCH;
@@ -734,7 +738,6 @@ static void i2c_send_board_response(int len)
 	req_target.response_pending = true;
 }
 
-
 static void i2c_process_board_command(int read, int addr, int len)
 {
 	board_i2c_process(read, addr, len, &host_buffer[0],
@@ -774,15 +777,17 @@ static int i2c_set_speed(mxc_i2c_regs_t *i2c, i2c_speed_t i2cspeed)
 		time_scl_min = 1000000 / (target_bus_freq / 1000);
 		clock_low_min =
 			((T_LOW_MIN + T_F_MAX_HS + (time_pclk - 1) - T_AF_MIN) /
-			 time_pclk) - 1;
+			 time_pclk) -
+			1;
 		clock_high_min = ((T_HIGH_MIN + T_R_MAX_HS + (time_pclk - 1) -
-				  T_AF_MIN) /
-				  time_pclk) - 1;
+				   T_AF_MIN) /
+				  time_pclk) -
+				 1;
 		clock_min = ((time_scl_min + (time_pclk - 1)) / time_pclk) - 2;
 
-		ticks_lo = (clock_low_min > (clock_min - clock_high_min))
-				   ? (clock_low_min)
-				   : (clock_min - clock_high_min);
+		ticks_lo = (clock_low_min > (clock_min - clock_high_min)) ?
+				   (clock_low_min) :
+				   (clock_min - clock_high_min);
 		ticks_hi = clock_high_min;
 
 		if ((ticks_lo > (MXC_F_I2C_HS_CLK_HS_CLK_LO >>
@@ -900,7 +905,8 @@ static int i2c_init_peripheral(mxc_i2c_regs_t *i2c, i2c_speed_t i2cspeed)
  * Return  EC_SUCCESS, or non-zero if error.
  */
 static int i2c_controller_write(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
-			    int stop, const uint8_t *data, int len, int restart)
+				int stop, const uint8_t *data, int len,
+				int restart)
 {
 	if (len == 0) {
 		return EC_SUCCESS;
@@ -1019,7 +1025,7 @@ static int i2c_controller_write(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
  * Return:     EC_SUCCESS if successful, otherwise returns a common error code
  */
 static int i2c_controller_read(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
-			   int stop, uint8_t *data, int len, int restart)
+			       int stop, uint8_t *data, int len, int restart)
 {
 	volatile int length = len;
 	int interactive_receive_mode;
@@ -1077,7 +1083,8 @@ static int i2c_controller_read(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
 			return EC_ERROR_UNKNOWN;
 		}
 
-		/* If in interactive receive mode then ack each received byte. */
+		/* If in interactive receive mode then ack each received byte.
+		 */
 		if (interactive_receive_mode) {
 			while (!(i2c->int_fl0 & MXC_F_I2C_INT_EN0_RX_MODE))
 				;
diff --git a/chip/max32660/i2c_regs.h b/chip/max32660/i2c_regs.h
index f6d2a6c0db..4d8daf63c7 100644
--- a/chip/max32660/i2c_regs.h
+++ b/chip/max32660/i2c_regs.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -34,50 +34,50 @@
  * typedef mxc_i2c_regs_t - Structure type to access the I2C Registers.
  */
 typedef struct {
-	__IO uint32_t ctrl;		/* 0x00: I2C CTRL Register */
-	__IO uint32_t status;		/* 0x04: I2C STATUS Register */
-	__IO uint32_t int_fl0;		/* 0x08: I2C INT_FL0 Register */
-	__IO uint32_t int_en0;		/* 0x0C: I2C INT_EN0 Register */
-	__IO uint32_t int_fl1;		/* 0x10: I2C INT_FL1 Register */
-	__IO uint32_t int_en1;		/* 0x14: I2C INT_EN1 Register */
-	__IO uint32_t fifo_len;		/* 0x18: I2C FIFO_LEN Register */
-	__IO uint32_t rx_ctrl0;		/* 0x1C: I2C RX_CTRL0 Register */
-	__IO uint32_t rx_ctrl1;		/* 0x20: I2C RX_CTRL1 Register */
-	__IO uint32_t tx_ctrl0;		/* 0x24: I2C TX_CTRL0 Register */
-	__IO uint32_t tx_ctrl1;		/* 0x28: I2C TX_CTRL1 Register */
-	__IO uint32_t fifo;		/* 0x2C: I2C FIFO Register */
-	__IO uint32_t controller_ctrl;	/* 0x30: I2C CONTROLLER_CTRL Register */
-	__IO uint32_t clk_lo;		/* 0x34: I2C CLK_LO Register */
-	__IO uint32_t clk_hi;		/* 0x38: I2C CLK_HI Register */
-	__IO uint32_t hs_clk;		/* 0x3C: I2C HS_CLK Register */
-	__IO uint32_t timeout;		/* 0x40: I2C TIMEOUT Register */
-	__IO uint32_t target_addr;	/* 0x44: I2C TARGET_ADDR Register */
-	__IO uint32_t dma;		/* 0x48: I2C DMA Register */
+	__IO uint32_t ctrl; /* 0x00: I2C CTRL Register */
+	__IO uint32_t status; /* 0x04: I2C STATUS Register */
+	__IO uint32_t int_fl0; /* 0x08: I2C INT_FL0 Register */
+	__IO uint32_t int_en0; /* 0x0C: I2C INT_EN0 Register */
+	__IO uint32_t int_fl1; /* 0x10: I2C INT_FL1 Register */
+	__IO uint32_t int_en1; /* 0x14: I2C INT_EN1 Register */
+	__IO uint32_t fifo_len; /* 0x18: I2C FIFO_LEN Register */
+	__IO uint32_t rx_ctrl0; /* 0x1C: I2C RX_CTRL0 Register */
+	__IO uint32_t rx_ctrl1; /* 0x20: I2C RX_CTRL1 Register */
+	__IO uint32_t tx_ctrl0; /* 0x24: I2C TX_CTRL0 Register */
+	__IO uint32_t tx_ctrl1; /* 0x28: I2C TX_CTRL1 Register */
+	__IO uint32_t fifo; /* 0x2C: I2C FIFO Register */
+	__IO uint32_t controller_ctrl; /* 0x30: I2C CONTROLLER_CTRL Register */
+	__IO uint32_t clk_lo; /* 0x34: I2C CLK_LO Register */
+	__IO uint32_t clk_hi; /* 0x38: I2C CLK_HI Register */
+	__IO uint32_t hs_clk; /* 0x3C: I2C HS_CLK Register */
+	__IO uint32_t timeout; /* 0x40: I2C TIMEOUT Register */
+	__IO uint32_t target_addr; /* 0x44: I2C TARGET_ADDR Register */
+	__IO uint32_t dma; /* 0x48: I2C DMA Register */
 } mxc_i2c_regs_t;
 
 /* Register offsets for module I2C */
 /*
  * I2C Peripheral Register Offsets from the I2C Base Peripheral Address.
  */
-#define MXC_R_I2C_CTRL			0x00000000UL
-#define MXC_R_I2C_STATUS		0x00000004UL
-#define MXC_R_I2C_INT_FL0		0x00000008UL
-#define MXC_R_I2C_INT_EN0		0x0000000CUL
-#define MXC_R_I2C_INT_FL1		0x00000010UL
-#define MXC_R_I2C_INT_EN1		0x00000014UL
-#define MXC_R_I2C_FIFO_LEN		0x00000018UL
-#define MXC_R_I2C_RX_CTRL0		0x0000001CUL
-#define MXC_R_I2C_RX_CTRL1		0x00000020UL
-#define MXC_R_I2C_TX_CTRL0		0x00000024UL
-#define MXC_R_I2C_TX_CTRL1		0x00000028UL
-#define MXC_R_I2C_FIFO			0x0000002CUL
-#define MXC_R_I2C_CONTROLLER_CTRL	0x00000030UL
-#define MXC_R_I2C_CLK_LO		0x00000034UL
-#define MXC_R_I2C_CLK_HI		0x00000038UL
-#define MXC_R_I2C_HS_CLK		0x0000003CUL
-#define MXC_R_I2C_TIMEOUT		0x00000040UL
-#define MXC_R_I2C_TARGET_ADDR		0x00000044UL
-#define MXC_R_I2C_DMA			0x00000048UL
+#define MXC_R_I2C_CTRL 0x00000000UL
+#define MXC_R_I2C_STATUS 0x00000004UL
+#define MXC_R_I2C_INT_FL0 0x00000008UL
+#define MXC_R_I2C_INT_EN0 0x0000000CUL
+#define MXC_R_I2C_INT_FL1 0x00000010UL
+#define MXC_R_I2C_INT_EN1 0x00000014UL
+#define MXC_R_I2C_FIFO_LEN 0x00000018UL
+#define MXC_R_I2C_RX_CTRL0 0x0000001CUL
+#define MXC_R_I2C_RX_CTRL1 0x00000020UL
+#define MXC_R_I2C_TX_CTRL0 0x00000024UL
+#define MXC_R_I2C_TX_CTRL1 0x00000028UL
+#define MXC_R_I2C_FIFO 0x0000002CUL
+#define MXC_R_I2C_CONTROLLER_CTRL 0x00000030UL
+#define MXC_R_I2C_CLK_LO 0x00000034UL
+#define MXC_R_I2C_CLK_HI 0x00000038UL
+#define MXC_R_I2C_HS_CLK 0x0000003CUL
+#define MXC_R_I2C_TIMEOUT 0x00000040UL
+#define MXC_R_I2C_TARGET_ADDR 0x00000044UL
+#define MXC_R_I2C_DMA 0x00000048UL
 
 /**
  * Control Register0.
diff --git a/chip/max32660/icc_regs.h b/chip/max32660/icc_regs.h
index 5f40e4203d..b2dbc75ec3 100644
--- a/chip/max32660/icc_regs.h
+++ b/chip/max32660/icc_regs.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -32,112 +32,110 @@
  */
 typedef struct {
 	__I uint32_t cache_id; /**< <tt>\b 0x0000:<\tt> ICC CACHE_ID Register */
-	__I uint32_t memcfg;   /**< <tt>\b 0x0004:<\tt> ICC MEMCFG Register */
+	__I uint32_t memcfg; /**< <tt>\b 0x0004:<\tt> ICC MEMCFG Register */
 	__R uint32_t rsv_0x8_0xff[62];
-	__IO uint32_t
-		cache_ctrl; /**< <tt>\b 0x0100:<\tt> ICC CACHE_CTRL Register */
+	__IO uint32_t cache_ctrl; /**< <tt>\b 0x0100:<\tt> ICC CACHE_CTRL
+				     Register */
 	__R uint32_t rsv_0x104_0x6ff[383];
-	__IO uint32_t
-		invalidate; /**< <tt>\b 0x0700:<\tt> ICC INVALIDATE Register */
+	__IO uint32_t invalidate; /**< <tt>\b 0x0700:<\tt> ICC INVALIDATE
+				     Register */
 } mxc_icc_regs_t;
 
 /**
  * ICC Peripheral Register Offsets from the ICC Base Peripheral
  * Address.
  */
-#define MXC_R_ICC_CACHE_ID                                                     \
-	((uint32_t)0x00000000UL) /**< Offset from ICC Base Address: <tt>       \
+#define MXC_R_ICC_CACHE_ID                                               \
+	((uint32_t)0x00000000UL) /**< Offset from ICC Base Address: <tt> \
 				    0x0x000 */
-#define MXC_R_ICC_MEMCFG                                                       \
-	((uint32_t)0x00000004UL) /**< Offset from ICC Base Address: <tt>       \
+#define MXC_R_ICC_MEMCFG                                                 \
+	((uint32_t)0x00000004UL) /**< Offset from ICC Base Address: <tt> \
 				    0x0x004 */
-#define MXC_R_ICC_CACHE_CTRL                                                   \
-	((uint32_t)0x00000100UL) /**< Offset from ICC Base Address: <tt>       \
+#define MXC_R_ICC_CACHE_CTRL                                             \
+	((uint32_t)0x00000100UL) /**< Offset from ICC Base Address: <tt> \
 				    0x0x100 */
-#define MXC_R_ICC_INVALIDATE                                                   \
-	((uint32_t)0x00000700UL) /**< Offset from ICC Base Address: <tt>       \
+#define MXC_R_ICC_INVALIDATE                                             \
+	((uint32_t)0x00000700UL) /**< Offset from ICC Base Address: <tt> \
 				    0x0x700 */
 
 /**
  * Cache ID Register.
  */
 #define MXC_F_ICC_CACHE_ID_RELNUM_POS 0 /**< CACHE_ID_RELNUM Position */
-#define MXC_F_ICC_CACHE_ID_RELNUM                                              \
-	((uint32_t)(                                                           \
-		0x3FUL << MXC_F_ICC_CACHE_ID_RELNUM_POS)) /**< CACHE_ID_RELNUM \
-							     Mask */
+#define MXC_F_ICC_CACHE_ID_RELNUM                                           \
+	((uint32_t)(0x3FUL                                                  \
+		    << MXC_F_ICC_CACHE_ID_RELNUM_POS)) /**< CACHE_ID_RELNUM \
+							  Mask */
 
 #define MXC_F_ICC_CACHE_ID_PARTNUM_POS 6 /**< CACHE_ID_PARTNUM Position */
-#define MXC_F_ICC_CACHE_ID_PARTNUM                                             \
-	((uint32_t)(0xFUL                                                      \
-		    << MXC_F_ICC_CACHE_ID_PARTNUM_POS)) /**< CACHE_ID_PARTNUM  \
+#define MXC_F_ICC_CACHE_ID_PARTNUM                                            \
+	((uint32_t)(0xFUL                                                     \
+		    << MXC_F_ICC_CACHE_ID_PARTNUM_POS)) /**< CACHE_ID_PARTNUM \
 							   Mask */
 
 #define MXC_F_ICC_CACHE_ID_CCHID_POS 10 /**< CACHE_ID_CCHID Position */
 #define MXC_F_ICC_CACHE_ID_CCHID                                               \
-	((uint32_t)(                                                           \
-		0x3FUL                                                         \
-		<< MXC_F_ICC_CACHE_ID_CCHID_POS)) /**< CACHE_ID_CCHID Mask */
+	((uint32_t)(0x3FUL << MXC_F_ICC_CACHE_ID_CCHID_POS)) /**<              \
+								CACHE_ID_CCHID \
+								Mask */
 
 /**
  * Memory Configuration Register.
  */
 #define MXC_F_ICC_MEMCFG_CCHSZ_POS 0 /**< MEMCFG_CCHSZ Position */
 #define MXC_F_ICC_MEMCFG_CCHSZ                                                 \
-	((uint32_t)(0xFFFFUL                                                   \
-		    << MXC_F_ICC_MEMCFG_CCHSZ_POS)) /**< MEMCFG_CCHSZ Mask */
+	((uint32_t)(0xFFFFUL << MXC_F_ICC_MEMCFG_CCHSZ_POS)) /**< MEMCFG_CCHSZ \
+								Mask */
 
 #define MXC_F_ICC_MEMCFG_MEMSZ_POS 16 /**< MEMCFG_MEMSZ Position */
 #define MXC_F_ICC_MEMCFG_MEMSZ                                                 \
-	((uint32_t)(0xFFFFUL                                                   \
-		    << MXC_F_ICC_MEMCFG_MEMSZ_POS)) /**< MEMCFG_MEMSZ Mask */
+	((uint32_t)(0xFFFFUL << MXC_F_ICC_MEMCFG_MEMSZ_POS)) /**< MEMCFG_MEMSZ \
+								Mask */
 
 /**
  * Cache Control and Status Register.
  */
-#define MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS                                      \
-	0 /**< CACHE_CTRL_CACHE_EN Position                                    \
+#define MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS   \
+	0 /**< CACHE_CTRL_CACHE_EN Position \
 	   */
-#define MXC_F_ICC_CACHE_CTRL_CACHE_EN                                          \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS)) /**<                    \
-							  CACHE_CTRL_CACHE_EN  \
-							  Mask */
-#define MXC_V_ICC_CACHE_CTRL_CACHE_EN_DIS                                      \
+#define MXC_F_ICC_CACHE_CTRL_CACHE_EN                                             \
+	((uint32_t)(0x1UL                                                         \
+		    << MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS)) /**<                   \
+							      CACHE_CTRL_CACHE_EN \
+							      Mask */
+#define MXC_V_ICC_CACHE_CTRL_CACHE_EN_DIS \
 	((uint32_t)0x0UL) /**< CACHE_CTRL_CACHE_EN_DIS Value */
-#define MXC_S_ICC_CACHE_CTRL_CACHE_EN_DIS                                      \
-	(MXC_V_ICC_CACHE_CTRL_CACHE_EN_DIS                                     \
-	 << MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS) /**< CACHE_CTRL_CACHE_EN_DIS    \
+#define MXC_S_ICC_CACHE_CTRL_CACHE_EN_DIS                                   \
+	(MXC_V_ICC_CACHE_CTRL_CACHE_EN_DIS                                  \
+	 << MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS) /**< CACHE_CTRL_CACHE_EN_DIS \
 						  Setting */
-#define MXC_V_ICC_CACHE_CTRL_CACHE_EN_EN                                       \
+#define MXC_V_ICC_CACHE_CTRL_CACHE_EN_EN \
 	((uint32_t)0x1UL) /**< CACHE_CTRL_CACHE_EN_EN Value */
-#define MXC_S_ICC_CACHE_CTRL_CACHE_EN_EN                                       \
-	(MXC_V_ICC_CACHE_CTRL_CACHE_EN_EN                                      \
-	 << MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS) /**< CACHE_CTRL_CACHE_EN_EN     \
+#define MXC_S_ICC_CACHE_CTRL_CACHE_EN_EN                                   \
+	(MXC_V_ICC_CACHE_CTRL_CACHE_EN_EN                                  \
+	 << MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS) /**< CACHE_CTRL_CACHE_EN_EN \
 						  Setting */
 
-#define MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS                                     \
+#define MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS \
 	16 /**< CACHE_CTRL_CACHE_RDY Position */
-#define MXC_F_ICC_CACHE_CTRL_CACHE_RDY                                          \
-	((uint32_t)(                                                            \
-		0x1UL                                                           \
-		<< MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS)) /**<                    \
-							   CACHE_CTRL_CACHE_RDY \
-							   Mask */
-#define MXC_V_ICC_CACHE_CTRL_CACHE_RDY_NOTREADY                                \
+#define MXC_F_ICC_CACHE_CTRL_CACHE_RDY                                              \
+	((uint32_t)(0x1UL                                                           \
+		    << MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS)) /**<                    \
+							       CACHE_CTRL_CACHE_RDY \
+							       Mask */
+#define MXC_V_ICC_CACHE_CTRL_CACHE_RDY_NOTREADY \
 	((uint32_t)0x0UL) /**< CACHE_CTRL_CACHE_RDY_NOTREADY Value */
 #define MXC_S_ICC_CACHE_CTRL_CACHE_RDY_NOTREADY                                  \
 	(MXC_V_ICC_CACHE_CTRL_CACHE_RDY_NOTREADY                                 \
 	 << MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS) /**<                             \
 						   CACHE_CTRL_CACHE_RDY_NOTREADY \
 						   Setting */
-#define MXC_V_ICC_CACHE_CTRL_CACHE_RDY_READY                                   \
+#define MXC_V_ICC_CACHE_CTRL_CACHE_RDY_READY \
 	((uint32_t)0x1UL) /**< CACHE_CTRL_CACHE_RDY_READY Value */
-#define MXC_S_ICC_CACHE_CTRL_CACHE_RDY_READY                                   \
-	(MXC_V_ICC_CACHE_CTRL_CACHE_RDY_READY                                  \
-	 << MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS) /**<                           \
-						   CACHE_CTRL_CACHE_RDY_READY  \
+#define MXC_S_ICC_CACHE_CTRL_CACHE_RDY_READY                                  \
+	(MXC_V_ICC_CACHE_CTRL_CACHE_RDY_READY                                 \
+	 << MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS) /**<                          \
+						   CACHE_CTRL_CACHE_RDY_READY \
 						   Setting */
 
 #endif /* _ICC_REGS_H_ */
diff --git a/chip/max32660/pwrseq_regs.h b/chip/max32660/pwrseq_regs.h
index 1ac0686aa6..e42ab8fd9d 100644
--- a/chip/max32660/pwrseq_regs.h
+++ b/chip/max32660/pwrseq_regs.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -53,8 +53,8 @@ extern "C" {
  */
 typedef struct {
 	__IO uint32_t lp_ctrl; /**< <tt>\b 0x00:</tt> PWRSEQ LP_CTRL Register */
-	__IO uint32_t
-		lp_wakefl; /**< <tt>\b 0x04:</tt> PWRSEQ LP_WAKEFL Register */
+	__IO uint32_t lp_wakefl; /**< <tt>\b 0x04:</tt> PWRSEQ LP_WAKEFL
+				    Register */
 	__IO uint32_t lpwk_en; /**< <tt>\b 0x08:</tt> PWRSEQ LPWK_EN Register */
 	__R uint32_t rsv_0xc_0x3f[13];
 	__IO uint32_t lpmemsd; /**< <tt>\b 0x40:</tt> PWRSEQ LPMEMSD Register */
@@ -64,234 +64,243 @@ typedef struct {
  * Register offsets for module PWRSEQ
  * PWRSEQ Peripheral Register Offsets from the PWRSEQ Base
  */
-#define MXC_R_PWRSEQ_LP_CTRL                                                   \
-	((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: <tt> \  \
+#define MXC_R_PWRSEQ_LP_CTRL                                                  \
+	((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: <tt> \ \
 				    \ \ \ 0x0000</tt> */
-#define MXC_R_PWRSEQ_LP_WAKEFL                                                 \
-	((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: <tt> \  \
+#define MXC_R_PWRSEQ_LP_WAKEFL                                                \
+	((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: <tt> \ \
 				    \ \ \ 0x0004</tt> */
-#define MXC_R_PWRSEQ_LPWK_EN                                                   \
-	((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: <tt> \  \
+#define MXC_R_PWRSEQ_LPWK_EN                                                  \
+	((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: <tt> \ \
 				    \ \ \ 0x0008</tt> */
-#define MXC_R_PWRSEQ_LPMEMSD                                                   \
-	((uint32_t)0x00000040UL) /**< Offset from PWRSEQ Base Address: <tt> \  \
+#define MXC_R_PWRSEQ_LPMEMSD                                                  \
+	((uint32_t)0x00000040UL) /**< Offset from PWRSEQ Base Address: <tt> \ \
 				    \ \ \ 0x0040</tt> */
 
 /**
  * pwrseq_registers
  * Low Power Control Register.
  */
-#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS                                   \
+#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS \
 	0 /**< LP_CTRL_RAMRET_SEL0 Position */
-#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0                                         \
-	((uint32_t)(                                                             \
-		0x1UL                                                            \
-		<< MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS)) /**< \ \ \ \                                                                               \
-							     LP_CTRL_RAMRET_SEL0 \
-							     \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS                                   \
+#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0                                             \
+	((uint32_t)(0x1UL                                                            \
+		    << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS)) /**< \ \ \ \           \
+								 LP_CTRL_RAMRET_SEL0 \
+								 \ \ \ \ Mask        \
+							       */
+#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS \
 	((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL0_DIS Value */
 #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS                                   \
 	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS                                  \
 	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS) /**< LP_CTRL_RAMRET_SEL0_DIS \
 						     \ \ \ \ Setting */
-#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN                                    \
+#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN \
 	((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL0_EN Value */
-#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN                                    \
-	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN                                   \
-	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS) /**< LP_CTRL_RAMRET_SEL0_EN  \
+#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN                                   \
+	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN                                  \
+	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS) /**< LP_CTRL_RAMRET_SEL0_EN \
 						     \ \ \ \ Setting */
 
-#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS                                   \
+#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS \
 	1 /**< LP_CTRL_RAMRET_SEL1 Position */
-#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1                                         \
-	((uint32_t)(                                                             \
-		0x1UL                                                            \
-		<< MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS)) /**< \ \ \ \                                                                               \
-							     LP_CTRL_RAMRET_SEL1 \
-							     \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS                                   \
+#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1                                             \
+	((uint32_t)(0x1UL                                                            \
+		    << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS)) /**< \ \ \ \           \
+								 LP_CTRL_RAMRET_SEL1 \
+								 \ \ \ \ Mask        \
+							       */
+#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS \
 	((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL1_DIS Value */
 #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS                                   \
 	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS                                  \
 	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS) /**< LP_CTRL_RAMRET_SEL1_DIS \
 						     \ \ \ \ Setting */
-#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN                                    \
+#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN \
 	((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL1_EN Value */
-#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN                                    \
-	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN                                   \
-	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS) /**< LP_CTRL_RAMRET_SEL1_EN  \
+#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN                                   \
+	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN                                  \
+	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS) /**< LP_CTRL_RAMRET_SEL1_EN \
 						     \ \ \ \ Setting */
 
-#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS                                   \
+#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS \
 	2 /**< LP_CTRL_RAMRET_SEL2 Position */
-#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2                                         \
-	((uint32_t)(                                                             \
-		0x1UL                                                            \
-		<< MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS)) /**< \ \ \ \                                                                               \
-							     LP_CTRL_RAMRET_SEL2 \
-							     \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS                                   \
+#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2                                             \
+	((uint32_t)(0x1UL                                                            \
+		    << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS)) /**< \ \ \ \           \
+								 LP_CTRL_RAMRET_SEL2 \
+								 \ \ \ \ Mask        \
+							       */
+#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS \
 	((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL2_DIS Value */
 #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS                                   \
 	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS                                  \
 	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS) /**< LP_CTRL_RAMRET_SEL2_DIS \
 						     \ \ \ \ Setting */
-#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN                                    \
+#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN \
 	((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL2_EN Value */
-#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN                                    \
-	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN                                   \
-	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS) /**< LP_CTRL_RAMRET_SEL2_EN  \
+#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN                                   \
+	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN                                  \
+	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS) /**< LP_CTRL_RAMRET_SEL2_EN \
 						     \ \ \ \ Setting */
 
-#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS                                   \
+#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS \
 	3 /**< LP_CTRL_RAMRET_SEL3 Position */
-#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3                                         \
-	((uint32_t)(                                                             \
-		0x1UL                                                            \
-		<< MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS)) /**< \ \ \ \                                                                               \
-							     LP_CTRL_RAMRET_SEL3 \
-							     \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS                                   \
+#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3                                             \
+	((uint32_t)(0x1UL                                                            \
+		    << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS)) /**< \ \ \ \           \
+								 LP_CTRL_RAMRET_SEL3 \
+								 \ \ \ \ Mask        \
+							       */
+#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS \
 	((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL3_DIS Value */
 #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS                                   \
 	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS                                  \
 	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS) /**< LP_CTRL_RAMRET_SEL3_DIS \
 						     \ \ \ \ Setting */
-#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN                                    \
+#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN \
 	((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL3_EN Value */
-#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN                                    \
-	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN                                   \
-	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS) /**< LP_CTRL_RAMRET_SEL3_EN  \
+#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN                                   \
+	(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN                                  \
+	 << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS) /**< LP_CTRL_RAMRET_SEL3_EN \
 						     \ \ \ \ Setting */
 
 #define MXC_F_PWRSEQ_LP_CTRL_OVR_POS 4 /**< LP_CTRL_OVR Position */
-#define MXC_F_PWRSEQ_LP_CTRL_OVR                                               \
-	((uint32_t)(0x3UL                                                      \
-		    << MXC_F_PWRSEQ_LP_CTRL_OVR_POS)) /**< LP_CTRL_OVR Mask */
-#define MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V                                          \
+#define MXC_F_PWRSEQ_LP_CTRL_OVR                                             \
+	((uint32_t)(0x3UL << MXC_F_PWRSEQ_LP_CTRL_OVR_POS)) /**< LP_CTRL_OVR \
+							       Mask */
+#define MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V \
 	((uint32_t)0x0UL) /**< LP_CTRL_OVR_0_9V Value */
-#define MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V                                          \
-	(MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V                                         \
-	 << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_0_9V Setting */
-#define MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V                                          \
+#define MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V                         \
+	(MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V                        \
+	 << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**<                \
+					     LP_CTRL_OVR_0_9V \
+					     Setting          \
+					   */
+#define MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V \
 	((uint32_t)0x1UL) /**< LP_CTRL_OVR_1_0V Value */
-#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V                                          \
-	(MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V                                         \
-	 << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_1_0V Setting */
-#define MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V                                          \
+#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V                         \
+	(MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V                        \
+	 << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**<                \
+					     LP_CTRL_OVR_1_0V \
+					     Setting          \
+					   */
+#define MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V \
 	((uint32_t)0x2UL) /**< LP_CTRL_OVR_1_1V Value */
-#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_1V                                          \
-	(MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V                                         \
-	 << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_1_1V Setting */
-
-#define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS                              \
+#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_1V                         \
+	(MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V                        \
+	 << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**<                \
+					     LP_CTRL_OVR_1_1V \
+					     Setting          \
+					   */
+
+#define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS \
 	6 /**< LP_CTRL_VCORE_DET_BYPASS Position */
-#define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS                                              \
-	((uint32_t)(                                                                       \
-		0x1UL                                                                      \
-		<< MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS)) /**< \ \ \ \                                                                                         \
-								  LP_CTRL_VCORE_DET_BYPASS \
-								  \                        \
-								  \ \ \ \                                                                                         \
-								  Mask */
-#define MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED                          \
+#define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS                                                  \
+	((uint32_t)(0x1UL                                                                      \
+		    << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS)) /**<                        \
+								      \ \ \ \                  \
+								      LP_CTRL_VCORE_DET_BYPASS \
+								      \                        \
+								      \ \ \ \                  \
+								      Mask */
+#define MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED \
 	((uint32_t)0x0UL) /**< LP_CTRL_VCORE_DET_BYPASS_ENABLED Value */
 #define MXC_S_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED                                      \
 	(MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED                                     \
-	 << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS) /**< \ \ \ \                                                                                         \
+	 << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS) /**< \ \ \ \                        \
 							  LP_CTRL_VCORE_DET_BYPASS_ENABLED \
 							  \ \ \ \ Setting */
-#define MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE                          \
+#define MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE \
 	((uint32_t)0x1UL) /**< LP_CTRL_VCORE_DET_BYPASS_DISABLE Value */
 #define MXC_S_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE                                      \
 	(MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE                                     \
-	 << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS) /**< \ \ \ \                                                                                         \
+	 << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS) /**< \ \ \ \                        \
 							  LP_CTRL_VCORE_DET_BYPASS_DISABLE \
 							  \ \ \ \ Setting */
 
-#define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS                                     \
-	8 /**< LP_CTRL_RETREG_EN Position   \ \ \ \                                                                             \
+#define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS          \
+	8 /**< LP_CTRL_RETREG_EN Position   \ \ \ \ \
 	   */
-#define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN                                         \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS)) /**< LP_CTRL_RETREG_EN \
-							   \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_DIS                                     \
+#define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN                                           \
+	((uint32_t)(0x1UL                                                        \
+		    << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS)) /**<                 \
+							       LP_CTRL_RETREG_EN \
+							       \ \ \ \ Mask */
+#define MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_DIS \
 	((uint32_t)0x0UL) /**< LP_CTRL_RETREG_EN_DIS Value */
 #define MXC_S_PWRSEQ_LP_CTRL_RETREG_EN_DIS                                     \
 	(MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_DIS                                    \
 	 << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS) /**< LP_CTRL_RETREG_EN_DIS \ \ \
 						   \ \ Setting */
-#define MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_EN                                      \
+#define MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_EN \
 	((uint32_t)0x1UL) /**< LP_CTRL_RETREG_EN_EN Value */
-#define MXC_S_PWRSEQ_LP_CTRL_RETREG_EN_EN                                      \
-	(MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_EN                                     \
-	 << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS) /**< LP_CTRL_RETREG_EN_EN \ \  \
+#define MXC_S_PWRSEQ_LP_CTRL_RETREG_EN_EN                                     \
+	(MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_EN                                    \
+	 << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS) /**< LP_CTRL_RETREG_EN_EN \ \ \
 						   \ \ Setting */
 
-#define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS                                    \
+#define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS \
 	10 /**< LP_CTRL_FAST_WK_EN Position */
-#define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN                                        \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS)) /**< \ \ \ \                                                                             \
-							    LP_CTRL_FAST_WK_EN \
-							    \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS                                    \
+#define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN                                            \
+	((uint32_t)(0x1UL                                                          \
+		    << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS)) /**< \ \ \ \          \
+								LP_CTRL_FAST_WK_EN \
+								\ \ \ \ Mask       \
+							      */
+#define MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS \
 	((uint32_t)0x0UL) /**< LP_CTRL_FAST_WK_EN_DIS Value */
 #define MXC_S_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS                                    \
 	(MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS                                   \
 	 << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS) /**< LP_CTRL_FAST_WK_EN_DIS \ \
 						    \ \ \ Setting */
-#define MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_EN                                     \
+#define MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_EN \
 	((uint32_t)0x1UL) /**< LP_CTRL_FAST_WK_EN_EN Value */
-#define MXC_S_PWRSEQ_LP_CTRL_FAST_WK_EN_EN                                     \
-	(MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_EN                                    \
-	 << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS) /**< LP_CTRL_FAST_WK_EN_EN \  \
+#define MXC_S_PWRSEQ_LP_CTRL_FAST_WK_EN_EN                                    \
+	(MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_EN                                   \
+	 << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS) /**< LP_CTRL_FAST_WK_EN_EN \ \
 						    \ \ \ Setting */
 
 #define MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS 11 /**< LP_CTRL_BG_OFF Position */
-#define MXC_F_PWRSEQ_LP_CTRL_BG_OFF                                            \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS)) /**< LP_CTRL_BG_OFF \
-							      \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LP_CTRL_BG_OFF_ON                                         \
+#define MXC_F_PWRSEQ_LP_CTRL_BG_OFF                                          \
+	((uint32_t)(0x1UL                                                    \
+		    << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS)) /**< LP_CTRL_BG_OFF \
+							    \ \ \ \ Mask */
+#define MXC_V_PWRSEQ_LP_CTRL_BG_OFF_ON \
 	((uint32_t)0x0UL) /**< LP_CTRL_BG_OFF_ON Value */
-#define MXC_S_PWRSEQ_LP_CTRL_BG_OFF_ON                                         \
-	(MXC_V_PWRSEQ_LP_CTRL_BG_OFF_ON                                        \
+#define MXC_S_PWRSEQ_LP_CTRL_BG_OFF_ON  \
+	(MXC_V_PWRSEQ_LP_CTRL_BG_OFF_ON \
 	 << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS) /**< LP_CTRL_BG_OFF_ON Setting */
-#define MXC_V_PWRSEQ_LP_CTRL_BG_OFF_OFF                                        \
+#define MXC_V_PWRSEQ_LP_CTRL_BG_OFF_OFF \
 	((uint32_t)0x1UL) /**< LP_CTRL_BG_OFF_OFF Value */
 #define MXC_S_PWRSEQ_LP_CTRL_BG_OFF_OFF                                        \
 	(MXC_V_PWRSEQ_LP_CTRL_BG_OFF_OFF                                       \
 	 << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS) /**< LP_CTRL_BG_OFF_OFF Setting \ \
 					      * \                              \
-					      * \ \                                                                             \
-					      * \ \ \                                                                             \
+					      * \ \                            \
+					      * \ \ \                          \
 					      */
 
-#define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS                                 \
+#define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS \
 	12 /**< LP_CTRL_VCORE_POR_DIS Position */
-#define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS                                           \
-	((uint32_t)(                                                                 \
-		0x1UL                                                                \
-		<< MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS)) /**< \ \ \ \                                                                                   \
-							       LP_CTRL_VCORE_POR_DIS \
-							       \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS                                 \
+#define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS                                               \
+	((uint32_t)(0x1UL                                                                \
+		    << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS)) /**< \ \ \ \             \
+								   LP_CTRL_VCORE_POR_DIS \
+								   \ \ \ \ Mask          \
+								 */
+#define MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS \
 	((uint32_t)0x0UL) /**< LP_CTRL_VCORE_POR_DIS_DIS Value */
 #define MXC_S_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS                                   \
 	(MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS                                  \
-	 << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS) /**< \ \ \ \                                                                               \
+	 << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS) /**< \ \ \ \                 \
 						       LP_CTRL_VCORE_POR_DIS_DIS \
 						       \ \ \ \ Setting */
-#define MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN                                  \
+#define MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN \
 	((uint32_t)0x1UL) /**< LP_CTRL_VCORE_POR_DIS_EN Value */
 #define MXC_S_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN                                   \
 	(MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN                                  \
-	 << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS) /**< \ \ \ \                                                                              \
+	 << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS) /**< \ \ \ \                \
 						       LP_CTRL_VCORE_POR_DIS_EN \
 						       \ \ \ \ Setting */
 
@@ -300,70 +309,70 @@ typedef struct {
 	((uint32_t)(0x1UL                                                      \
 		    << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS)) /**< LP_CTRL_LDO_DIS \
 							     \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_EN                                        \
+#define MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_EN \
 	((uint32_t)0x0UL) /**< LP_CTRL_LDO_DIS_EN Value */
-#define MXC_S_PWRSEQ_LP_CTRL_LDO_DIS_EN                                        \
-	(MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_EN                                       \
-	 << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS) /**< LP_CTRL_LDO_DIS_EN Setting  \
-					       * \                             \
-					       * \ \                                                                             \
-					       * \ \ \                                                                             \
-					       * \ \ \ \                                                                             \
+#define MXC_S_PWRSEQ_LP_CTRL_LDO_DIS_EN                                       \
+	(MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_EN                                      \
+	 << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS) /**< LP_CTRL_LDO_DIS_EN Setting \
+					       * \                            \
+					       * \ \                          \
+					       * \ \ \                        \
+					       * \ \ \ \                      \
 					       */
-#define MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_DIS                                       \
+#define MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_DIS \
 	((uint32_t)0x1UL) /**< LP_CTRL_LDO_DIS_DIS Value */
 #define MXC_S_PWRSEQ_LP_CTRL_LDO_DIS_DIS                                       \
 	(MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_DIS                                      \
 	 << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS) /**< LP_CTRL_LDO_DIS_DIS Setting \
 					       * \                             \
-					       * \ \                                                                             \
-					       * \ \ \                                                                             \
-					       * \ \ \ \                                                                             \
+					       * \ \                           \
+					       * \ \ \                         \
+					       * \ \ \ \                       \
 					       */
 
-#define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS                                 \
+#define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS \
 	20 /**< LP_CTRL_VCORE_SVM_DIS Position */
-#define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS                                           \
-	((uint32_t)(                                                                 \
-		0x1UL                                                                \
-		<< MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS)) /**< \ \ \ \                                                                                   \
-							       LP_CTRL_VCORE_SVM_DIS \
-							       \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN                                  \
+#define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS                                               \
+	((uint32_t)(0x1UL                                                                \
+		    << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS)) /**< \ \ \ \             \
+								   LP_CTRL_VCORE_SVM_DIS \
+								   \ \ \ \ Mask          \
+								 */
+#define MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN \
 	((uint32_t)0x0UL) /**< LP_CTRL_VCORE_SVM_DIS_EN Value */
 #define MXC_S_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN                                   \
 	(MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN                                  \
-	 << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS) /**< \ \ \ \                                                                              \
+	 << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS) /**< \ \ \ \                \
 						       LP_CTRL_VCORE_SVM_DIS_EN \
 						       \ \ \ \ Setting */
-#define MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS                                 \
+#define MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS \
 	((uint32_t)0x1UL) /**< LP_CTRL_VCORE_SVM_DIS_DIS Value */
 #define MXC_S_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS                                   \
 	(MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS                                  \
-	 << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS) /**< \ \ \ \                                                                               \
+	 << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS) /**< \ \ \ \                 \
 						       LP_CTRL_VCORE_SVM_DIS_DIS \
 						       \ \ \ \ Setting */
 
-#define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS                                 \
+#define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS \
 	25 /**< LP_CTRL_VDDIO_POR_DIS Position */
-#define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS                                           \
-	((uint32_t)(                                                                 \
-		0x1UL                                                                \
-		<< MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS)) /**< \ \ \ \                                                                                   \
-							       LP_CTRL_VDDIO_POR_DIS \
-							       \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN                                  \
+#define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS                                               \
+	((uint32_t)(0x1UL                                                                \
+		    << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS)) /**< \ \ \ \             \
+								   LP_CTRL_VDDIO_POR_DIS \
+								   \ \ \ \ Mask          \
+								 */
+#define MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN \
 	((uint32_t)0x0UL) /**< LP_CTRL_VDDIO_POR_DIS_EN Value */
 #define MXC_S_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN                                   \
 	(MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN                                  \
-	 << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS) /**< \ \ \ \                                                                              \
+	 << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS) /**< \ \ \ \                \
 						       LP_CTRL_VDDIO_POR_DIS_EN \
 						       \ \ \ \ Setting */
-#define MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS                                 \
+#define MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS \
 	((uint32_t)0x1UL) /**< LP_CTRL_VDDIO_POR_DIS_DIS Value */
 #define MXC_S_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS                                   \
 	(MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS                                  \
-	 << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS) /**< \ \ \ \                                                                               \
+	 << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS) /**< \ \ \ \                 \
 						       LP_CTRL_VDDIO_POR_DIS_DIS \
 						       \ \ \ \ Setting */
 
@@ -373,10 +382,12 @@ typedef struct {
  */
 #define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS 0 /**< LP_WAKEFL_WAKEST Position */
 #define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST                                          \
-	((uint32_t)(                                                           \
-		0x3FFFUL                                                       \
-		<< MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS)) /**< LP_WAKEFL_WAKEST \ \
-							  \ \ \ Mask */
+	((uint32_t)(0x3FFFUL                                                   \
+		    << MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS)) /**<                \
+							      LP_WAKEFL_WAKEST \
+							      \                \
+							      \ \ \ Mask       \
+							    */
 
 /**
  * pwrseq_registers
@@ -384,104 +395,106 @@ typedef struct {
  * power wakeup functionality for GPIO0.
  */
 #define MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS 0 /**< LPWK_EN_WAKEEN Position */
-#define MXC_F_PWRSEQ_LPWK_EN_WAKEEN                                            \
-	((uint32_t)(0x3FFFUL                                                   \
-		    << MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS)) /**< LPWK_EN_WAKEEN \ \
-							    \ \ \ Mask */
+#define MXC_F_PWRSEQ_LPWK_EN_WAKEEN                                        \
+	((uint32_t)(0x3FFFUL                                               \
+		    << MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS)) /**<              \
+							    LPWK_EN_WAKEEN \
+							    \              \
+							    \ \ \ Mask     \
+							  */
 
 /**
  * pwrseq_registers
  * Low Power Memory Shutdown Control.
  */
-#define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS                                     \
-	0 /**< LPMEMSD_SRAM0_OFF Position   \ \ \ \                                                                             \
+#define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS          \
+	0 /**< LPMEMSD_SRAM0_OFF Position   \ \ \ \ \
 	   */
-#define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF                                         \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS)) /**< LPMEMSD_SRAM0_OFF \
-							   \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL                                  \
+#define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF                                           \
+	((uint32_t)(0x1UL                                                        \
+		    << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS)) /**<                 \
+							       LPMEMSD_SRAM0_OFF \
+							       \ \ \ \ Mask */
+#define MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL \
 	((uint32_t)0x0UL) /**< LPMEMSD_SRAM0_OFF_NORMAL Value */
-#define MXC_S_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL                                  \
-	(MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL                                 \
-	 << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS) /**< LPMEMSD_SRAM0_OFF_NORMAL  \
+#define MXC_S_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL                                 \
+	(MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL                                \
+	 << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS) /**< LPMEMSD_SRAM0_OFF_NORMAL \
 						   \ \ \ \ Setting */
-#define MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN                                \
+#define MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN \
 	((uint32_t)0x1UL) /**< LPMEMSD_SRAM0_OFF_SHUTDOWN Value */
-#define MXC_S_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN                                \
-	(MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN                               \
-	 << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS) /**< \ \ \ \                                                                             \
-						   LPMEMSD_SRAM0_OFF_SHUTDOWN  \
+#define MXC_S_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN                               \
+	(MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN                              \
+	 << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS) /**< \ \ \ \                  \
+						   LPMEMSD_SRAM0_OFF_SHUTDOWN \
 						   \ \ \ \ Setting */
 
-#define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS                                     \
-	1 /**< LPMEMSD_SRAM1_OFF Position   \ \ \ \                                                                             \
+#define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS          \
+	1 /**< LPMEMSD_SRAM1_OFF Position   \ \ \ \ \
 	   */
-#define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF                                         \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS)) /**< LPMEMSD_SRAM1_OFF \
-							   \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL                                  \
+#define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF                                           \
+	((uint32_t)(0x1UL                                                        \
+		    << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS)) /**<                 \
+							       LPMEMSD_SRAM1_OFF \
+							       \ \ \ \ Mask */
+#define MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL \
 	((uint32_t)0x0UL) /**< LPMEMSD_SRAM1_OFF_NORMAL Value */
-#define MXC_S_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL                                  \
-	(MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL                                 \
-	 << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS) /**< LPMEMSD_SRAM1_OFF_NORMAL  \
+#define MXC_S_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL                                 \
+	(MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL                                \
+	 << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS) /**< LPMEMSD_SRAM1_OFF_NORMAL \
 						   \ \ \ \ Setting */
-#define MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN                                \
+#define MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN \
 	((uint32_t)0x1UL) /**< LPMEMSD_SRAM1_OFF_SHUTDOWN Value */
-#define MXC_S_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN                                \
-	(MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN                               \
-	 << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS) /**< \ \ \ \                                                                             \
-						   LPMEMSD_SRAM1_OFF_SHUTDOWN  \
+#define MXC_S_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN                               \
+	(MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN                              \
+	 << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS) /**< \ \ \ \                  \
+						   LPMEMSD_SRAM1_OFF_SHUTDOWN \
 						   \ \ \ \ Setting */
 
-#define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS                                     \
-	2 /**< LPMEMSD_SRAM2_OFF Position   \ \ \ \                                                                             \
+#define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS          \
+	2 /**< LPMEMSD_SRAM2_OFF Position   \ \ \ \ \
 	   */
-#define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF                                         \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS)) /**< LPMEMSD_SRAM2_OFF \
-							   \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL                                  \
+#define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF                                           \
+	((uint32_t)(0x1UL                                                        \
+		    << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS)) /**<                 \
+							       LPMEMSD_SRAM2_OFF \
+							       \ \ \ \ Mask */
+#define MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL \
 	((uint32_t)0x0UL) /**< LPMEMSD_SRAM2_OFF_NORMAL Value */
-#define MXC_S_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL                                  \
-	(MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL                                 \
-	 << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS) /**< LPMEMSD_SRAM2_OFF_NORMAL  \
+#define MXC_S_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL                                 \
+	(MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL                                \
+	 << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS) /**< LPMEMSD_SRAM2_OFF_NORMAL \
 						   \ \ \ \ Setting */
-#define MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN                                \
+#define MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN \
 	((uint32_t)0x1UL) /**< LPMEMSD_SRAM2_OFF_SHUTDOWN Value */
-#define MXC_S_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN                                \
-	(MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN                               \
-	 << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS) /**< \ \ \ \                                                                             \
-						   LPMEMSD_SRAM2_OFF_SHUTDOWN  \
+#define MXC_S_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN                               \
+	(MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN                              \
+	 << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS) /**< \ \ \ \                  \
+						   LPMEMSD_SRAM2_OFF_SHUTDOWN \
 						   \ \ \ \ Setting */
 
-#define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS                                     \
-	3 /**< LPMEMSD_SRAM3_OFF Position   \ \ \ \                                                                             \
+#define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS          \
+	3 /**< LPMEMSD_SRAM3_OFF Position   \ \ \ \ \
 	   */
-#define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF                                         \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS)) /**< LPMEMSD_SRAM3_OFF \
-							   \ \ \ \ Mask */
-#define MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL                                  \
+#define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF                                           \
+	((uint32_t)(0x1UL                                                        \
+		    << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS)) /**<                 \
+							       LPMEMSD_SRAM3_OFF \
+							       \ \ \ \ Mask */
+#define MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL \
 	((uint32_t)0x0UL) /**< LPMEMSD_SRAM3_OFF_NORMAL Value */
-#define MXC_S_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL                                  \
-	(MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL                                 \
-	 << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS) /**< LPMEMSD_SRAM3_OFF_NORMAL  \
+#define MXC_S_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL                                 \
+	(MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL                                \
+	 << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS) /**< LPMEMSD_SRAM3_OFF_NORMAL \
 						   \ \ \ \ Setting */
-#define MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN                                \
+#define MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN \
 	((uint32_t)0x1UL) /**< LPMEMSD_SRAM3_OFF_SHUTDOWN Value */
-#define MXC_S_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN                                \
-	(MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN                               \
-	 << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS) /**< \ \ \ \                                                                             \
-						   LPMEMSD_SRAM3_OFF_SHUTDOWN  \
+#define MXC_S_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN                               \
+	(MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN                              \
+	 << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS) /**< \ \ \ \                  \
+						   LPMEMSD_SRAM3_OFF_SHUTDOWN \
 						   \ \ \ \ Setting */
 
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/chip/max32660/registers.h b/chip/max32660/registers.h
index e444888fa0..72118bf744 100644
--- a/chip/max32660/registers.h
+++ b/chip/max32660/registers.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -72,9 +72,8 @@
 
 extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)  */
 #ifndef PeripheralClock
-#define PeripheralClock    \
-	(SystemCoreClock / \
-	 2) /*!< Peripheral Clock Frequency                  \
+#define PeripheralClock                                       \
+	(SystemCoreClock / 2) /*!< Peripheral Clock Frequency \
 			       */
 #endif
 
@@ -173,14 +172,17 @@ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)  */
 #define MXC_BASE_TMR2 ((uint32_t)0x40012000UL)
 #define MXC_TMR2 ((mxc_tmr_regs_t *)MXC_BASE_TMR2)
 
-#define MXC_TMR_GET_IRQ(i)              \
-	(IRQn_Type)((i) == 0 ?          \
-			    TMR0_IRQn : \
-			    (i) == 1 ? TMR1_IRQn : (i) == 2 ? TMR2_IRQn : 0)
+#define MXC_TMR_GET_IRQ(i)                 \
+	(IRQn_Type)((i) == 0 ? TMR0_IRQn : \
+		    (i) == 1 ? TMR1_IRQn : \
+		    (i) == 2 ? TMR2_IRQn : \
+			       0)
 
 #define MXC_TMR_GET_BASE(i)         \
 	((i) == 0 ? MXC_BASE_TMR0 : \
-		    (i) == 1 ? MXC_BASE_TMR1 : (i) == 2 ? MXC_BASE_TMR2 : 0)
+	 (i) == 1 ? MXC_BASE_TMR1 : \
+	 (i) == 2 ? MXC_BASE_TMR2 : \
+		    0)
 
 #define MXC_TMR_GET_TMR(i) \
 	((i) == 0 ? MXC_TMR0 : (i) == 1 ? MXC_TMR1 : (i) == 2 ? MXC_TMR2 : 0)
diff --git a/chip/max32660/system_chip.c b/chip/max32660/system_chip.c
index 07127dc8c5..8679881102 100644
--- a/chip/max32660/system_chip.c
+++ b/chip/max32660/system_chip.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/max32660/tmr_regs.h b/chip/max32660/tmr_regs.h
index 946cacbc50..ab3ac5c5ed 100644
--- a/chip/max32660/tmr_regs.h
+++ b/chip/max32660/tmr_regs.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -42,11 +42,11 @@ extern "C" {
  * Structure type to access the TMR Registers.
  */
 typedef struct {
-	__IO uint32_t cnt;    /**< <tt>\b 0x00:<\tt> TMR CNT Register */
-	__IO uint32_t cmp;    /**< <tt>\b 0x04:<\tt> TMR CMP Register */
-	__IO uint32_t pwm;    /**< <tt>\b 0x08:<\tt> TMR PWM Register */
-	__IO uint32_t intr;   /**< <tt>\b 0x0C:<\tt> TMR INTR Register */
-	__IO uint32_t cn;     /**< <tt>\b 0x10:<\tt> TMR CN Register */
+	__IO uint32_t cnt; /**< <tt>\b 0x00:<\tt> TMR CNT Register */
+	__IO uint32_t cmp; /**< <tt>\b 0x04:<\tt> TMR CMP Register */
+	__IO uint32_t pwm; /**< <tt>\b 0x08:<\tt> TMR PWM Register */
+	__IO uint32_t intr; /**< <tt>\b 0x0C:<\tt> TMR INTR Register */
+	__IO uint32_t cn; /**< <tt>\b 0x10:<\tt> TMR CN Register */
 	__IO uint32_t nolcmp; /**< <tt>\b 0x14:<\tt> TMR NOLCMP Register */
 } mxc_tmr_regs_t;
 
@@ -54,23 +54,23 @@ typedef struct {
  * TMR Peripheral Register Offsets from the TMR Base Peripheral
  * Address.
  */
-#define MXC_R_TMR_CNT                                                          \
-	((uint32_t)0x00000000UL) /**< Offset from TMR Base Address: <tt>       \
+#define MXC_R_TMR_CNT                                                    \
+	((uint32_t)0x00000000UL) /**< Offset from TMR Base Address: <tt> \
 				    0x0x000 */
-#define MXC_R_TMR_CMP                                                          \
-	((uint32_t)0x00000004UL) /**< Offset from TMR Base Address: <tt>       \
+#define MXC_R_TMR_CMP                                                    \
+	((uint32_t)0x00000004UL) /**< Offset from TMR Base Address: <tt> \
 				    0x0x004 */
-#define MXC_R_TMR_PWM                                                          \
-	((uint32_t)0x00000008UL) /**< Offset from TMR Base Address: <tt>       \
+#define MXC_R_TMR_PWM                                                    \
+	((uint32_t)0x00000008UL) /**< Offset from TMR Base Address: <tt> \
 				    0x0x008 */
-#define MXC_R_TMR_INTR                                                         \
-	((uint32_t)0x0000000CUL) /**< Offset from TMR Base Address: <tt>       \
+#define MXC_R_TMR_INTR                                                   \
+	((uint32_t)0x0000000CUL) /**< Offset from TMR Base Address: <tt> \
 				    0x0x00C */
-#define MXC_R_TMR_CN                                                           \
-	((uint32_t)0x00000010UL) /**< Offset from TMR Base Address: <tt>       \
+#define MXC_R_TMR_CN                                                     \
+	((uint32_t)0x00000010UL) /**< Offset from TMR Base Address: <tt> \
 				    0x0x010 */
-#define MXC_R_TMR_NOLCMP                                                       \
-	((uint32_t)0x00000014UL) /**< Offset from TMR Base Address: <tt>       \
+#define MXC_R_TMR_NOLCMP                                                 \
+	((uint32_t)0x00000014UL) /**< Offset from TMR Base Address: <tt> \
 				    0x0x014 */
 
 /**
@@ -78,199 +78,231 @@ typedef struct {
  * clears the associated interrupt.
  */
 #define MXC_F_TMR_INTR_IRQ_CLR_POS 0 /**< INTR_IRQ_CLR Position */
-#define MXC_F_TMR_INTR_IRQ_CLR                                                 \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_TMR_INTR_IRQ_CLR_POS)) /**< INTR_IRQ_CLR Mask */
+#define MXC_F_TMR_INTR_IRQ_CLR                                              \
+	((uint32_t)(0x1UL << MXC_F_TMR_INTR_IRQ_CLR_POS)) /**< INTR_IRQ_CLR \
+							     Mask */
 
 /**
  * Timer Control Register.
  */
 #define MXC_F_TMR_CN_TMODE_POS 0 /**< CN_TMODE Position */
-#define MXC_F_TMR_CN_TMODE                                                     \
+#define MXC_F_TMR_CN_TMODE \
 	((uint32_t)(0x7UL << MXC_F_TMR_CN_TMODE_POS)) /**< CN_TMODE Mask */
-#define MXC_V_TMR_CN_TMODE_ONESHOT                                             \
+#define MXC_V_TMR_CN_TMODE_ONESHOT \
 	((uint32_t)0x0UL) /**< CN_TMODE_ONESHOT Value */
-#define MXC_S_TMR_CN_TMODE_ONESHOT                                             \
-	(MXC_V_TMR_CN_TMODE_ONESHOT                                            \
-	 << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_ONESHOT Setting */
-#define MXC_V_TMR_CN_TMODE_CONTINUOUS                                          \
+#define MXC_S_TMR_CN_TMODE_ONESHOT                      \
+	(MXC_V_TMR_CN_TMODE_ONESHOT                     \
+	 << MXC_F_TMR_CN_TMODE_POS) /**<                \
+				       CN_TMODE_ONESHOT \
+				       Setting */
+#define MXC_V_TMR_CN_TMODE_CONTINUOUS \
 	((uint32_t)0x1UL) /**< CN_TMODE_CONTINUOUS Value */
-#define MXC_S_TMR_CN_TMODE_CONTINUOUS                                          \
-	(MXC_V_TMR_CN_TMODE_CONTINUOUS                                         \
-	 << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CONTINUOUS Setting */
-#define MXC_V_TMR_CN_TMODE_COUNTER                                             \
+#define MXC_S_TMR_CN_TMODE_CONTINUOUS                      \
+	(MXC_V_TMR_CN_TMODE_CONTINUOUS                     \
+	 << MXC_F_TMR_CN_TMODE_POS) /**<                   \
+				       CN_TMODE_CONTINUOUS \
+				       Setting             \
+				     */
+#define MXC_V_TMR_CN_TMODE_COUNTER \
 	((uint32_t)0x2UL) /**< CN_TMODE_COUNTER Value */
-#define MXC_S_TMR_CN_TMODE_COUNTER                                             \
-	(MXC_V_TMR_CN_TMODE_COUNTER                                            \
-	 << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_COUNTER Setting */
+#define MXC_S_TMR_CN_TMODE_COUNTER                      \
+	(MXC_V_TMR_CN_TMODE_COUNTER                     \
+	 << MXC_F_TMR_CN_TMODE_POS) /**<                \
+				       CN_TMODE_COUNTER \
+				       Setting */
 #define MXC_V_TMR_CN_TMODE_PWM ((uint32_t)0x3UL) /**< CN_TMODE_PWM Value */
-#define MXC_S_TMR_CN_TMODE_PWM                                                 \
-	(MXC_V_TMR_CN_TMODE_PWM                                                \
-	 << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_PWM Setting */
-#define MXC_V_TMR_CN_TMODE_CAPTURE                                             \
+#define MXC_S_TMR_CN_TMODE_PWM                                               \
+	(MXC_V_TMR_CN_TMODE_PWM << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_PWM \
+							      Setting */
+#define MXC_V_TMR_CN_TMODE_CAPTURE \
 	((uint32_t)0x4UL) /**< CN_TMODE_CAPTURE Value */
-#define MXC_S_TMR_CN_TMODE_CAPTURE                                             \
-	(MXC_V_TMR_CN_TMODE_CAPTURE                                            \
-	 << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CAPTURE Setting */
-#define MXC_V_TMR_CN_TMODE_COMPARE                                             \
+#define MXC_S_TMR_CN_TMODE_CAPTURE                      \
+	(MXC_V_TMR_CN_TMODE_CAPTURE                     \
+	 << MXC_F_TMR_CN_TMODE_POS) /**<                \
+				       CN_TMODE_CAPTURE \
+				       Setting */
+#define MXC_V_TMR_CN_TMODE_COMPARE \
 	((uint32_t)0x5UL) /**< CN_TMODE_COMPARE Value */
-#define MXC_S_TMR_CN_TMODE_COMPARE                                             \
-	(MXC_V_TMR_CN_TMODE_COMPARE                                            \
-	 << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_COMPARE Setting */
-#define MXC_V_TMR_CN_TMODE_GATED                                               \
-	((uint32_t)0x6UL) /**< CN_TMODE_GATED Value                            \
+#define MXC_S_TMR_CN_TMODE_COMPARE                      \
+	(MXC_V_TMR_CN_TMODE_COMPARE                     \
+	 << MXC_F_TMR_CN_TMODE_POS) /**<                \
+				       CN_TMODE_COMPARE \
+				       Setting */
+#define MXC_V_TMR_CN_TMODE_GATED                    \
+	((uint32_t)0x6UL) /**< CN_TMODE_GATED Value \
 			   */
 #define MXC_S_TMR_CN_TMODE_GATED                                               \
-	(MXC_V_TMR_CN_TMODE_GATED                                              \
-	 << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_GATED Setting */
-#define MXC_V_TMR_CN_TMODE_CAPTURECOMPARE                                      \
+	(MXC_V_TMR_CN_TMODE_GATED << MXC_F_TMR_CN_TMODE_POS) /**<              \
+								CN_TMODE_GATED \
+								Setting */
+#define MXC_V_TMR_CN_TMODE_CAPTURECOMPARE \
 	((uint32_t)0x7UL) /**< CN_TMODE_CAPTURECOMPARE Value */
-#define MXC_S_TMR_CN_TMODE_CAPTURECOMPARE                                      \
-	(MXC_V_TMR_CN_TMODE_CAPTURECOMPARE                                     \
-	 << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CAPTURECOMPARE Setting */
+#define MXC_S_TMR_CN_TMODE_CAPTURECOMPARE                      \
+	(MXC_V_TMR_CN_TMODE_CAPTURECOMPARE                     \
+	 << MXC_F_TMR_CN_TMODE_POS) /**<                       \
+				       CN_TMODE_CAPTURECOMPARE \
+				       Setting                 \
+				     */
 
 #define MXC_F_TMR_CN_PRES_POS 3 /**< CN_PRES Position */
-#define MXC_F_TMR_CN_PRES                                                      \
+#define MXC_F_TMR_CN_PRES \
 	((uint32_t)(0x7UL << MXC_F_TMR_CN_PRES_POS)) /**< CN_PRES Mask */
-#define MXC_V_TMR_CN_PRES_DIV1 ((uint32_t)0x0UL)     /**< CN_PRES_DIV1 Value */
-#define MXC_S_TMR_CN_PRES_DIV1                                                 \
-	(MXC_V_TMR_CN_PRES_DIV1                                                \
-	 << MXC_F_TMR_CN_PRES_POS)		 /**< CN_PRES_DIV1 Setting */
+#define MXC_V_TMR_CN_PRES_DIV1 ((uint32_t)0x0UL) /**< CN_PRES_DIV1 Value */
+#define MXC_S_TMR_CN_PRES_DIV1                                              \
+	(MXC_V_TMR_CN_PRES_DIV1 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV1 \
+							     Setting */
 #define MXC_V_TMR_CN_PRES_DIV2 ((uint32_t)0x1UL) /**< CN_PRES_DIV2 Value */
-#define MXC_S_TMR_CN_PRES_DIV2                                                 \
-	(MXC_V_TMR_CN_PRES_DIV2                                                \
-	 << MXC_F_TMR_CN_PRES_POS)		 /**< CN_PRES_DIV2 Setting */
+#define MXC_S_TMR_CN_PRES_DIV2                                              \
+	(MXC_V_TMR_CN_PRES_DIV2 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV2 \
+							     Setting */
 #define MXC_V_TMR_CN_PRES_DIV4 ((uint32_t)0x2UL) /**< CN_PRES_DIV4 Value */
-#define MXC_S_TMR_CN_PRES_DIV4                                                 \
-	(MXC_V_TMR_CN_PRES_DIV4                                                \
-	 << MXC_F_TMR_CN_PRES_POS)		 /**< CN_PRES_DIV4 Setting */
+#define MXC_S_TMR_CN_PRES_DIV4                                              \
+	(MXC_V_TMR_CN_PRES_DIV4 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV4 \
+							     Setting */
 #define MXC_V_TMR_CN_PRES_DIV8 ((uint32_t)0x3UL) /**< CN_PRES_DIV8 Value */
-#define MXC_S_TMR_CN_PRES_DIV8                                                 \
-	(MXC_V_TMR_CN_PRES_DIV8                                                \
-	 << MXC_F_TMR_CN_PRES_POS)		  /**< CN_PRES_DIV8 Setting */
+#define MXC_S_TMR_CN_PRES_DIV8                                              \
+	(MXC_V_TMR_CN_PRES_DIV8 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV8 \
+							     Setting */
 #define MXC_V_TMR_CN_PRES_DIV16 ((uint32_t)0x4UL) /**< CN_PRES_DIV16 Value */
-#define MXC_S_TMR_CN_PRES_DIV16                                                \
-	(MXC_V_TMR_CN_PRES_DIV16                                               \
-	 << MXC_F_TMR_CN_PRES_POS)		  /**< CN_PRES_DIV16 Setting */
+#define MXC_S_TMR_CN_PRES_DIV16                                               \
+	(MXC_V_TMR_CN_PRES_DIV16 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV16 \
+							      Setting */
 #define MXC_V_TMR_CN_PRES_DIV32 ((uint32_t)0x5UL) /**< CN_PRES_DIV32 Value */
-#define MXC_S_TMR_CN_PRES_DIV32                                                \
-	(MXC_V_TMR_CN_PRES_DIV32                                               \
-	 << MXC_F_TMR_CN_PRES_POS)		  /**< CN_PRES_DIV32 Setting */
+#define MXC_S_TMR_CN_PRES_DIV32                                               \
+	(MXC_V_TMR_CN_PRES_DIV32 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV32 \
+							      Setting */
 #define MXC_V_TMR_CN_PRES_DIV64 ((uint32_t)0x6UL) /**< CN_PRES_DIV64 Value */
-#define MXC_S_TMR_CN_PRES_DIV64                                                \
-	(MXC_V_TMR_CN_PRES_DIV64                                               \
-	 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV64 Setting */
-#define MXC_V_TMR_CN_PRES_DIV128                                               \
-	((uint32_t)0x7UL) /**< CN_PRES_DIV128 Value                            \
+#define MXC_S_TMR_CN_PRES_DIV64                                               \
+	(MXC_V_TMR_CN_PRES_DIV64 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV64 \
+							      Setting */
+#define MXC_V_TMR_CN_PRES_DIV128                    \
+	((uint32_t)0x7UL) /**< CN_PRES_DIV128 Value \
 			   */
-#define MXC_S_TMR_CN_PRES_DIV128                                               \
-	(MXC_V_TMR_CN_PRES_DIV128                                              \
-	 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV128 Setting */
+#define MXC_S_TMR_CN_PRES_DIV128                                              \
+	(MXC_V_TMR_CN_PRES_DIV128 << MXC_F_TMR_CN_PRES_POS) /**<              \
+							       CN_PRES_DIV128 \
+							       Setting */
 
 #define MXC_F_TMR_CN_TPOL_POS 6 /**< CN_TPOL Position */
-#define MXC_F_TMR_CN_TPOL                                                      \
+#define MXC_F_TMR_CN_TPOL \
 	((uint32_t)(0x1UL << MXC_F_TMR_CN_TPOL_POS)) /**< CN_TPOL Mask */
-#define MXC_V_TMR_CN_TPOL_ACTIVEHI                                             \
+#define MXC_V_TMR_CN_TPOL_ACTIVEHI \
 	((uint32_t)0x0UL) /**< CN_TPOL_ACTIVEHI Value */
-#define MXC_S_TMR_CN_TPOL_ACTIVEHI                                             \
-	(MXC_V_TMR_CN_TPOL_ACTIVEHI                                            \
-	 << MXC_F_TMR_CN_TPOL_POS) /**< CN_TPOL_ACTIVEHI Setting */
-#define MXC_V_TMR_CN_TPOL_ACTIVELO                                             \
+#define MXC_S_TMR_CN_TPOL_ACTIVEHI                     \
+	(MXC_V_TMR_CN_TPOL_ACTIVEHI                    \
+	 << MXC_F_TMR_CN_TPOL_POS) /**<                \
+				      CN_TPOL_ACTIVEHI \
+				      Setting */
+#define MXC_V_TMR_CN_TPOL_ACTIVELO \
 	((uint32_t)0x1UL) /**< CN_TPOL_ACTIVELO Value */
-#define MXC_S_TMR_CN_TPOL_ACTIVELO                                             \
-	(MXC_V_TMR_CN_TPOL_ACTIVELO                                            \
-	 << MXC_F_TMR_CN_TPOL_POS) /**< CN_TPOL_ACTIVELO Setting */
+#define MXC_S_TMR_CN_TPOL_ACTIVELO                     \
+	(MXC_V_TMR_CN_TPOL_ACTIVELO                    \
+	 << MXC_F_TMR_CN_TPOL_POS) /**<                \
+				      CN_TPOL_ACTIVELO \
+				      Setting */
 
 #define MXC_F_TMR_CN_TEN_POS 7 /**< CN_TEN Position */
-#define MXC_F_TMR_CN_TEN                                                       \
+#define MXC_F_TMR_CN_TEN \
 	((uint32_t)(0x1UL << MXC_F_TMR_CN_TEN_POS)) /**< CN_TEN Mask */
-#define MXC_V_TMR_CN_TEN_DIS ((uint32_t)0x0UL)      /**< CN_TEN_DIS Value */
+#define MXC_V_TMR_CN_TEN_DIS ((uint32_t)0x0UL) /**< CN_TEN_DIS Value */
 #define MXC_S_TMR_CN_TEN_DIS                                                   \
-	(MXC_V_TMR_CN_TEN_DIS                                                  \
-	 << MXC_F_TMR_CN_TEN_POS)	     /**< CN_TEN_DIS Setting */
+	(MXC_V_TMR_CN_TEN_DIS << MXC_F_TMR_CN_TEN_POS) /**< CN_TEN_DIS Setting \
+							*/
 #define MXC_V_TMR_CN_TEN_EN ((uint32_t)0x1UL) /**< CN_TEN_EN Value */
-#define MXC_S_TMR_CN_TEN_EN                                                    \
-	(MXC_V_TMR_CN_TEN_EN << MXC_F_TMR_CN_TEN_POS) /**< CN_TEN_EN Setting   \
+#define MXC_S_TMR_CN_TEN_EN                                                  \
+	(MXC_V_TMR_CN_TEN_EN << MXC_F_TMR_CN_TEN_POS) /**< CN_TEN_EN Setting \
 						       */
 
 #define MXC_F_TMR_CN_PRES3_POS 8 /**< CN_PRES3 Position */
-#define MXC_F_TMR_CN_PRES3                                                     \
+#define MXC_F_TMR_CN_PRES3 \
 	((uint32_t)(0x1UL << MXC_F_TMR_CN_PRES3_POS)) /**< CN_PRES3 Mask */
 
 #define MXC_F_TMR_CN_PWMSYNC_POS 9 /**< CN_PWMSYNC Position */
-#define MXC_F_TMR_CN_PWMSYNC                                                   \
-	((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMSYNC_POS)) /**< CN_PWMSYNC Mask   \
+#define MXC_F_TMR_CN_PWMSYNC                                                 \
+	((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMSYNC_POS)) /**< CN_PWMSYNC Mask \
 							 */
-#define MXC_V_TMR_CN_PWMSYNC_DIS                                               \
-	((uint32_t)0x0UL) /**< CN_PWMSYNC_DIS Value                            \
+#define MXC_V_TMR_CN_PWMSYNC_DIS                    \
+	((uint32_t)0x0UL) /**< CN_PWMSYNC_DIS Value \
 			   */
-#define MXC_S_TMR_CN_PWMSYNC_DIS                                               \
-	(MXC_V_TMR_CN_PWMSYNC_DIS                                              \
-	 << MXC_F_TMR_CN_PWMSYNC_POS)		  /**< CN_PWMSYNC_DIS Setting */
+#define MXC_S_TMR_CN_PWMSYNC_DIS                        \
+	(MXC_V_TMR_CN_PWMSYNC_DIS                       \
+	 << MXC_F_TMR_CN_PWMSYNC_POS) /**<              \
+					 CN_PWMSYNC_DIS \
+					 Setting */
 #define MXC_V_TMR_CN_PWMSYNC_EN ((uint32_t)0x1UL) /**< CN_PWMSYNC_EN Value */
 #define MXC_S_TMR_CN_PWMSYNC_EN                                                \
-	(MXC_V_TMR_CN_PWMSYNC_EN                                               \
-	 << MXC_F_TMR_CN_PWMSYNC_POS) /**< CN_PWMSYNC_EN Setting */
+	(MXC_V_TMR_CN_PWMSYNC_EN << MXC_F_TMR_CN_PWMSYNC_POS) /**<             \
+								 CN_PWMSYNC_EN \
+								 Setting */
 
 #define MXC_F_TMR_CN_NOLHPOL_POS 10 /**< CN_NOLHPOL Position */
-#define MXC_F_TMR_CN_NOLHPOL                                                   \
-	((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLHPOL_POS)) /**< CN_NOLHPOL Mask   \
+#define MXC_F_TMR_CN_NOLHPOL                                                 \
+	((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLHPOL_POS)) /**< CN_NOLHPOL Mask \
 							 */
-#define MXC_V_TMR_CN_NOLHPOL_DIS                                               \
-	((uint32_t)0x0UL) /**< CN_NOLHPOL_DIS Value                            \
+#define MXC_V_TMR_CN_NOLHPOL_DIS                    \
+	((uint32_t)0x0UL) /**< CN_NOLHPOL_DIS Value \
 			   */
-#define MXC_S_TMR_CN_NOLHPOL_DIS                                               \
-	(MXC_V_TMR_CN_NOLHPOL_DIS                                              \
-	 << MXC_F_TMR_CN_NOLHPOL_POS)		  /**< CN_NOLHPOL_DIS Setting */
+#define MXC_S_TMR_CN_NOLHPOL_DIS                        \
+	(MXC_V_TMR_CN_NOLHPOL_DIS                       \
+	 << MXC_F_TMR_CN_NOLHPOL_POS) /**<              \
+					 CN_NOLHPOL_DIS \
+					 Setting */
 #define MXC_V_TMR_CN_NOLHPOL_EN ((uint32_t)0x1UL) /**< CN_NOLHPOL_EN Value */
 #define MXC_S_TMR_CN_NOLHPOL_EN                                                \
-	(MXC_V_TMR_CN_NOLHPOL_EN                                               \
-	 << MXC_F_TMR_CN_NOLHPOL_POS) /**< CN_NOLHPOL_EN Setting */
+	(MXC_V_TMR_CN_NOLHPOL_EN << MXC_F_TMR_CN_NOLHPOL_POS) /**<             \
+								 CN_NOLHPOL_EN \
+								 Setting */
 
 #define MXC_F_TMR_CN_NOLLPOL_POS 11 /**< CN_NOLLPOL Position */
-#define MXC_F_TMR_CN_NOLLPOL                                                   \
-	((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLLPOL_POS)) /**< CN_NOLLPOL Mask   \
+#define MXC_F_TMR_CN_NOLLPOL                                                 \
+	((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLLPOL_POS)) /**< CN_NOLLPOL Mask \
 							 */
-#define MXC_V_TMR_CN_NOLLPOL_DIS                                               \
-	((uint32_t)0x0UL) /**< CN_NOLLPOL_DIS Value                            \
+#define MXC_V_TMR_CN_NOLLPOL_DIS                    \
+	((uint32_t)0x0UL) /**< CN_NOLLPOL_DIS Value \
 			   */
-#define MXC_S_TMR_CN_NOLLPOL_DIS                                               \
-	(MXC_V_TMR_CN_NOLLPOL_DIS                                              \
-	 << MXC_F_TMR_CN_NOLLPOL_POS)		  /**< CN_NOLLPOL_DIS Setting */
+#define MXC_S_TMR_CN_NOLLPOL_DIS                        \
+	(MXC_V_TMR_CN_NOLLPOL_DIS                       \
+	 << MXC_F_TMR_CN_NOLLPOL_POS) /**<              \
+					 CN_NOLLPOL_DIS \
+					 Setting */
 #define MXC_V_TMR_CN_NOLLPOL_EN ((uint32_t)0x1UL) /**< CN_NOLLPOL_EN Value */
 #define MXC_S_TMR_CN_NOLLPOL_EN                                                \
-	(MXC_V_TMR_CN_NOLLPOL_EN                                               \
-	 << MXC_F_TMR_CN_NOLLPOL_POS) /**< CN_NOLLPOL_EN Setting */
+	(MXC_V_TMR_CN_NOLLPOL_EN << MXC_F_TMR_CN_NOLLPOL_POS) /**<             \
+								 CN_NOLLPOL_EN \
+								 Setting */
 
 #define MXC_F_TMR_CN_PWMCKBD_POS 12 /**< CN_PWMCKBD Position */
-#define MXC_F_TMR_CN_PWMCKBD                                                   \
-	((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMCKBD_POS)) /**< CN_PWMCKBD Mask   \
+#define MXC_F_TMR_CN_PWMCKBD                                                 \
+	((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMCKBD_POS)) /**< CN_PWMCKBD Mask \
 							 */
-#define MXC_V_TMR_CN_PWMCKBD_DIS                                               \
-	((uint32_t)0x1UL) /**< CN_PWMCKBD_DIS Value                            \
+#define MXC_V_TMR_CN_PWMCKBD_DIS                    \
+	((uint32_t)0x1UL) /**< CN_PWMCKBD_DIS Value \
 			   */
-#define MXC_S_TMR_CN_PWMCKBD_DIS                                               \
-	(MXC_V_TMR_CN_PWMCKBD_DIS                                              \
-	 << MXC_F_TMR_CN_PWMCKBD_POS)		  /**< CN_PWMCKBD_DIS Setting */
+#define MXC_S_TMR_CN_PWMCKBD_DIS                        \
+	(MXC_V_TMR_CN_PWMCKBD_DIS                       \
+	 << MXC_F_TMR_CN_PWMCKBD_POS) /**<              \
+					 CN_PWMCKBD_DIS \
+					 Setting */
 #define MXC_V_TMR_CN_PWMCKBD_EN ((uint32_t)0x0UL) /**< CN_PWMCKBD_EN Value */
 #define MXC_S_TMR_CN_PWMCKBD_EN                                                \
-	(MXC_V_TMR_CN_PWMCKBD_EN                                               \
-	 << MXC_F_TMR_CN_PWMCKBD_POS) /**< CN_PWMCKBD_EN Setting */
+	(MXC_V_TMR_CN_PWMCKBD_EN << MXC_F_TMR_CN_PWMCKBD_POS) /**<             \
+								 CN_PWMCKBD_EN \
+								 Setting */
 
 /**
  * Timer Non-Overlapping Compare Register.
  */
 #define MXC_F_TMR_NOLCMP_NOLLCMP_POS 0 /**< NOLCMP_NOLLCMP Position */
 #define MXC_F_TMR_NOLCMP_NOLLCMP                                               \
-	((uint32_t)(                                                           \
-		0xFFUL                                                         \
-		<< MXC_F_TMR_NOLCMP_NOLLCMP_POS)) /**< NOLCMP_NOLLCMP Mask */
+	((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_NOLLCMP_POS)) /**<              \
+								NOLCMP_NOLLCMP \
+								Mask */
 
 #define MXC_F_TMR_NOLCMP_NOLHCMP_POS 8 /**< NOLCMP_NOLHCMP Position */
 #define MXC_F_TMR_NOLCMP_NOLHCMP                                               \
-	((uint32_t)(                                                           \
-		0xFFUL                                                         \
-		<< MXC_F_TMR_NOLCMP_NOLHCMP_POS)) /**< NOLCMP_NOLHCMP Mask */
+	((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_NOLHCMP_POS)) /**<              \
+								NOLCMP_NOLHCMP \
+								Mask */
 
 #ifdef __cplusplus
 }
diff --git a/chip/max32660/uart_chip.c b/chip/max32660/uart_chip.c
index 7d323650ae..87ba59e629 100644
--- a/chip/max32660/uart_chip.c
+++ b/chip/max32660/uart_chip.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -35,24 +35,24 @@ static int done_uart_init_yet;
 
 #define UART_BAUD 115200
 
-#define UART_ER_IF                                                             \
-	(MXC_F_UART_INT_FL_RX_FRAME_ERROR |                                    \
+#define UART_ER_IF                          \
+	(MXC_F_UART_INT_FL_RX_FRAME_ERROR | \
 	 MXC_F_UART_INT_FL_RX_PARITY_ERROR | MXC_F_UART_INT_FL_RX_OVERRUN)
 
-#define UART_ER_IE                                                             \
-	(MXC_F_UART_INT_EN_RX_FRAME_ERROR |                                    \
+#define UART_ER_IE                          \
+	(MXC_F_UART_INT_EN_RX_FRAME_ERROR | \
 	 MXC_F_UART_INT_EN_RX_PARITY_ERROR | MXC_F_UART_INT_EN_RX_OVERRUN)
 
 #define UART_RX_IF (UART_ER_IF | MXC_F_UART_INT_FL_RX_FIFO_THRESH)
 
 #define UART_RX_IE (UART_ER_IE | MXC_F_UART_INT_EN_RX_FIFO_THRESH)
 
-#define UART_TX_IF                                                             \
-	(UART_ER_IF | MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY |                 \
+#define UART_TX_IF                                             \
+	(UART_ER_IF | MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY | \
 	 MXC_F_UART_INT_FL_TX_FIFO_THRESH)
 
-#define UART_TX_IE                                                             \
-	(UART_ER_IE | MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY |                 \
+#define UART_TX_IE                                             \
+	(UART_ER_IE | MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY | \
 	 MXC_F_UART_INT_EN_TX_FIFO_THRESH)
 
 #define UART_RX_THRESHOLD_LEVEL 1
@@ -242,19 +242,20 @@ void uart_init(void)
 	gpio_config_module(MODULE_UART, 1);
 
 	/* Drain FIFOs and enable UART and set configuration */
-	MXC_UART->ctrl = (MXC_F_UART_CTRL_ENABLE | MXC_S_UART_CTRL_CHAR_SIZE_8 | 1);
+	MXC_UART->ctrl =
+		(MXC_F_UART_CTRL_ENABLE | MXC_S_UART_CTRL_CHAR_SIZE_8 | 1);
 
 	/* Set the baud rate */
-	div = PeripheralClock / (UART_BAUD); 	// constant part of DIV (i.e. DIV
-					     					// * (Baudrate*factor_int))
+	div = PeripheralClock / (UART_BAUD); // constant part of DIV (i.e. DIV
+					     // * (Baudrate*factor_int))
 
 	do {
 		factor += 1;
-		baud0 = div >> (7 - factor); 	// divide by 128,64,32,16 to
-					     				// extract integer part
-		baud1 = ((div << factor) -
-			 (baud0 << 7)); 			// subtract factor corrected div -
-										// integer parts
+		baud0 = div >> (7 - factor); // divide by 128,64,32,16 to
+					     // extract integer part
+		baud1 = ((div << factor) - (baud0 << 7)); // subtract factor
+							  // corrected div -
+							  // integer parts
 
 	} while ((baud0 == 0) && (factor < 4));
 
@@ -262,7 +263,7 @@ void uart_init(void)
 	MXC_UART->baud1 = baud1;
 
 	MXC_UART->thresh_ctrl = UART_RX_THRESHOLD_LEVEL
-			    << MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS;
+				<< MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS;
 
 	/* Clear Interrupt Flags */
 	flags = MXC_UART->int_fl;
diff --git a/chip/max32660/uart_regs.h b/chip/max32660/uart_regs.h
index a2de0cc0a0..64d4ac5654 100644
--- a/chip/max32660/uart_regs.h
+++ b/chip/max32660/uart_regs.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -32,15 +32,15 @@
  */
 typedef struct {
 	__IO uint32_t ctrl; /**< <tt>\b 0x00:<\tt> UART CTRL Register */
-	__IO uint32_t
-		thresh_ctrl; /**< <tt>\b 0x04:<\tt> UART THRESH_CTRL Register */
+	__IO uint32_t thresh_ctrl; /**< <tt>\b 0x04:<\tt> UART THRESH_CTRL
+				      Register */
 	__I uint32_t status; /**< <tt>\b 0x08:<\tt> UART STATUS Register */
-	__IO uint32_t int_en;  /**< <tt>\b 0x0C:<\tt> UART INT_EN Register */
-	__IO uint32_t int_fl;  /**< <tt>\b 0x10:<\tt> UART INT_FL Register */
-	__IO uint32_t baud0;   /**< <tt>\b 0x14:<\tt> UART BAUD0 Register */
-	__IO uint32_t baud1;   /**< <tt>\b 0x18:<\tt> UART BAUD1 Register */
-	__IO uint32_t fifo;    /**< <tt>\b 0x1C:<\tt> UART FIFO Register */
-	__IO uint32_t dma;     /**< <tt>\b 0x20:<\tt> UART DMA Register */
+	__IO uint32_t int_en; /**< <tt>\b 0x0C:<\tt> UART INT_EN Register */
+	__IO uint32_t int_fl; /**< <tt>\b 0x10:<\tt> UART INT_FL Register */
+	__IO uint32_t baud0; /**< <tt>\b 0x14:<\tt> UART BAUD0 Register */
+	__IO uint32_t baud1; /**< <tt>\b 0x18:<\tt> UART BAUD1 Register */
+	__IO uint32_t fifo; /**< <tt>\b 0x1C:<\tt> UART FIFO Register */
+	__IO uint32_t dma; /**< <tt>\b 0x20:<\tt> UART DMA Register */
 	__IO uint32_t tx_fifo; /**< <tt>\b 0x24:<\tt> UART TX_FIFO Register */
 } mxc_uart_regs_t;
 
@@ -48,630 +48,707 @@ typedef struct {
  * UART Peripheral Register Offsets from the UART Base Peripheral
  * Address.
  */
-#define MXC_R_UART_CTRL                                                        \
-	((uint32_t)0x00000000UL) /**< Offset from UART Base Address: <tt>      \
+#define MXC_R_UART_CTRL                                                   \
+	((uint32_t)0x00000000UL) /**< Offset from UART Base Address: <tt> \
 				    0x0x000 */
-#define MXC_R_UART_THRESH_CTRL                                                 \
-	((uint32_t)0x00000004UL) /**< Offset from UART Base Address: <tt>      \
+#define MXC_R_UART_THRESH_CTRL                                            \
+	((uint32_t)0x00000004UL) /**< Offset from UART Base Address: <tt> \
 				    0x0x004 */
-#define MXC_R_UART_STATUS                                                      \
-	((uint32_t)0x00000008UL) /**< Offset from UART Base Address: <tt>      \
+#define MXC_R_UART_STATUS                                                 \
+	((uint32_t)0x00000008UL) /**< Offset from UART Base Address: <tt> \
 				    0x0x008 */
-#define MXC_R_UART_INT_EN                                                      \
-	((uint32_t)0x0000000CUL) /**< Offset from UART Base Address: <tt>      \
+#define MXC_R_UART_INT_EN                                                 \
+	((uint32_t)0x0000000CUL) /**< Offset from UART Base Address: <tt> \
 				    0x0x00C */
-#define MXC_R_UART_INT_FL                                                      \
-	((uint32_t)0x00000010UL) /**< Offset from UART Base Address: <tt>      \
+#define MXC_R_UART_INT_FL                                                 \
+	((uint32_t)0x00000010UL) /**< Offset from UART Base Address: <tt> \
 				    0x0x010 */
-#define MXC_R_UART_BAUD0                                                       \
-	((uint32_t)0x00000014UL) /**< Offset from UART Base Address: <tt>      \
+#define MXC_R_UART_BAUD0                                                  \
+	((uint32_t)0x00000014UL) /**< Offset from UART Base Address: <tt> \
 				    0x0x014 */
-#define MXC_R_UART_BAUD1                                                       \
-	((uint32_t)0x00000018UL) /**< Offset from UART Base Address: <tt>      \
+#define MXC_R_UART_BAUD1                                                  \
+	((uint32_t)0x00000018UL) /**< Offset from UART Base Address: <tt> \
 				    0x0x018 */
-#define MXC_R_UART_FIFO                                                        \
-	((uint32_t)0x0000001CUL) /**< Offset from UART Base Address: <tt>      \
+#define MXC_R_UART_FIFO                                                   \
+	((uint32_t)0x0000001CUL) /**< Offset from UART Base Address: <tt> \
 				    0x0x01C */
-#define MXC_R_UART_DMA                                                         \
-	((uint32_t)0x00000020UL) /**< Offset from UART Base Address: <tt>      \
+#define MXC_R_UART_DMA                                                    \
+	((uint32_t)0x00000020UL) /**< Offset from UART Base Address: <tt> \
 				    0x0x020 */
-#define MXC_R_UART_TX_FIFO                                                     \
-	((uint32_t)0x00000024UL) /**< Offset from UART Base Address: <tt>      \
+#define MXC_R_UART_TX_FIFO                                                \
+	((uint32_t)0x00000024UL) /**< Offset from UART Base Address: <tt> \
 				    0x0x024 */
 
 /**
  * Control Register.
  */
 #define MXC_F_UART_CTRL_ENABLE_POS 0 /**< CTRL_ENABLE Position */
-#define MXC_F_UART_CTRL_ENABLE                                                 \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_UART_CTRL_ENABLE_POS)) /**< CTRL_ENABLE Mask */
-#define MXC_V_UART_CTRL_ENABLE_DIS                                             \
+#define MXC_F_UART_CTRL_ENABLE                                             \
+	((uint32_t)(0x1UL << MXC_F_UART_CTRL_ENABLE_POS)) /**< CTRL_ENABLE \
+							     Mask */
+#define MXC_V_UART_CTRL_ENABLE_DIS \
 	((uint32_t)0x0UL) /**< CTRL_ENABLE_DIS Value */
-#define MXC_S_UART_CTRL_ENABLE_DIS                                             \
-	(MXC_V_UART_CTRL_ENABLE_DIS                                            \
-	 << MXC_F_UART_CTRL_ENABLE_POS) /**< CTRL_ENABLE_DIS Setting */
-#define MXC_V_UART_CTRL_ENABLE_EN                                              \
-	((uint32_t)0x1UL) /**< CTRL_ENABLE_EN Value                            \
+#define MXC_S_UART_CTRL_ENABLE_DIS                         \
+	(MXC_V_UART_CTRL_ENABLE_DIS                        \
+	 << MXC_F_UART_CTRL_ENABLE_POS) /**<               \
+					   CTRL_ENABLE_DIS \
+					   Setting         \
+					 */
+#define MXC_V_UART_CTRL_ENABLE_EN                   \
+	((uint32_t)0x1UL) /**< CTRL_ENABLE_EN Value \
 			   */
-#define MXC_S_UART_CTRL_ENABLE_EN                                              \
-	(MXC_V_UART_CTRL_ENABLE_EN                                             \
-	 << MXC_F_UART_CTRL_ENABLE_POS) /**< CTRL_ENABLE_EN Setting */
+#define MXC_S_UART_CTRL_ENABLE_EN                         \
+	(MXC_V_UART_CTRL_ENABLE_EN                        \
+	 << MXC_F_UART_CTRL_ENABLE_POS) /**<              \
+					   CTRL_ENABLE_EN \
+					   Setting        \
+					 */
 
 #define MXC_F_UART_CTRL_PARITY_EN_POS 1 /**< CTRL_PARITY_EN Position */
 #define MXC_F_UART_CTRL_PARITY_EN                                              \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_CTRL_PARITY_EN_POS)) /**< CTRL_PARITY_EN Mask */
-#define MXC_V_UART_CTRL_PARITY_EN_DIS                                          \
+	((uint32_t)(0x1UL << MXC_F_UART_CTRL_PARITY_EN_POS)) /**<              \
+								CTRL_PARITY_EN \
+								Mask */
+#define MXC_V_UART_CTRL_PARITY_EN_DIS \
 	((uint32_t)0x0UL) /**< CTRL_PARITY_EN_DIS Value */
-#define MXC_S_UART_CTRL_PARITY_EN_DIS                                          \
-	(MXC_V_UART_CTRL_PARITY_EN_DIS                                         \
-	 << MXC_F_UART_CTRL_PARITY_EN_POS) /**< CTRL_PARITY_EN_DIS Setting */
-#define MXC_V_UART_CTRL_PARITY_EN_EN                                           \
+#define MXC_S_UART_CTRL_PARITY_EN_DIS                            \
+	(MXC_V_UART_CTRL_PARITY_EN_DIS                           \
+	 << MXC_F_UART_CTRL_PARITY_EN_POS) /**<                  \
+					      CTRL_PARITY_EN_DIS \
+					      Setting            \
+					    */
+#define MXC_V_UART_CTRL_PARITY_EN_EN \
 	((uint32_t)0x1UL) /**< CTRL_PARITY_EN_EN Value */
-#define MXC_S_UART_CTRL_PARITY_EN_EN                                           \
-	(MXC_V_UART_CTRL_PARITY_EN_EN                                          \
-	 << MXC_F_UART_CTRL_PARITY_EN_POS) /**< CTRL_PARITY_EN_EN Setting */
+#define MXC_S_UART_CTRL_PARITY_EN_EN                            \
+	(MXC_V_UART_CTRL_PARITY_EN_EN                           \
+	 << MXC_F_UART_CTRL_PARITY_EN_POS) /**<                 \
+					      CTRL_PARITY_EN_EN \
+					      Setting           \
+					    */
 
 #define MXC_F_UART_CTRL_PARITY_POS 2 /**< CTRL_PARITY Position */
-#define MXC_F_UART_CTRL_PARITY                                                 \
-	((uint32_t)(                                                           \
-		0x3UL << MXC_F_UART_CTRL_PARITY_POS)) /**< CTRL_PARITY Mask */
-#define MXC_V_UART_CTRL_PARITY_EVEN                                            \
+#define MXC_F_UART_CTRL_PARITY                                             \
+	((uint32_t)(0x3UL << MXC_F_UART_CTRL_PARITY_POS)) /**< CTRL_PARITY \
+							     Mask */
+#define MXC_V_UART_CTRL_PARITY_EVEN \
 	((uint32_t)0x0UL) /**< CTRL_PARITY_EVEN Value */
-#define MXC_S_UART_CTRL_PARITY_EVEN                                            \
-	(MXC_V_UART_CTRL_PARITY_EVEN                                           \
-	 << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_EVEN Setting */
-#define MXC_V_UART_CTRL_PARITY_ODD                                             \
+#define MXC_S_UART_CTRL_PARITY_EVEN                         \
+	(MXC_V_UART_CTRL_PARITY_EVEN                        \
+	 << MXC_F_UART_CTRL_PARITY_POS) /**<                \
+					   CTRL_PARITY_EVEN \
+					   Setting          \
+					 */
+#define MXC_V_UART_CTRL_PARITY_ODD \
 	((uint32_t)0x1UL) /**< CTRL_PARITY_ODD Value */
-#define MXC_S_UART_CTRL_PARITY_ODD                                             \
-	(MXC_V_UART_CTRL_PARITY_ODD                                            \
-	 << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_ODD Setting */
-#define MXC_V_UART_CTRL_PARITY_MARK                                            \
+#define MXC_S_UART_CTRL_PARITY_ODD                         \
+	(MXC_V_UART_CTRL_PARITY_ODD                        \
+	 << MXC_F_UART_CTRL_PARITY_POS) /**<               \
+					   CTRL_PARITY_ODD \
+					   Setting         \
+					 */
+#define MXC_V_UART_CTRL_PARITY_MARK \
 	((uint32_t)0x2UL) /**< CTRL_PARITY_MARK Value */
-#define MXC_S_UART_CTRL_PARITY_MARK                                            \
-	(MXC_V_UART_CTRL_PARITY_MARK                                           \
-	 << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_MARK Setting */
-#define MXC_V_UART_CTRL_PARITY_SPACE                                           \
+#define MXC_S_UART_CTRL_PARITY_MARK                         \
+	(MXC_V_UART_CTRL_PARITY_MARK                        \
+	 << MXC_F_UART_CTRL_PARITY_POS) /**<                \
+					   CTRL_PARITY_MARK \
+					   Setting          \
+					 */
+#define MXC_V_UART_CTRL_PARITY_SPACE \
 	((uint32_t)0x3UL) /**< CTRL_PARITY_SPACE Value */
-#define MXC_S_UART_CTRL_PARITY_SPACE                                           \
-	(MXC_V_UART_CTRL_PARITY_SPACE                                          \
-	 << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_SPACE Setting */
+#define MXC_S_UART_CTRL_PARITY_SPACE                         \
+	(MXC_V_UART_CTRL_PARITY_SPACE                        \
+	 << MXC_F_UART_CTRL_PARITY_POS) /**<                 \
+					   CTRL_PARITY_SPACE \
+					   Setting           \
+					 */
 
 #define MXC_F_UART_CTRL_PARMD_POS 4 /**< CTRL_PARMD Position */
-#define MXC_F_UART_CTRL_PARMD                                                  \
-	((uint32_t)(0x1UL << MXC_F_UART_CTRL_PARMD_POS)) /**< CTRL_PARMD Mask  \
+#define MXC_F_UART_CTRL_PARMD                                                 \
+	((uint32_t)(0x1UL << MXC_F_UART_CTRL_PARMD_POS)) /**< CTRL_PARMD Mask \
 							  */
 #define MXC_V_UART_CTRL_PARMD_1 ((uint32_t)0x0UL) /**< CTRL_PARMD_1 Value */
 #define MXC_S_UART_CTRL_PARMD_1                                                \
-	(MXC_V_UART_CTRL_PARMD_1                                               \
-	 << MXC_F_UART_CTRL_PARMD_POS)		  /**< CTRL_PARMD_1 Setting */
+	(MXC_V_UART_CTRL_PARMD_1 << MXC_F_UART_CTRL_PARMD_POS) /**<            \
+								  CTRL_PARMD_1 \
+								  Setting */
 #define MXC_V_UART_CTRL_PARMD_0 ((uint32_t)0x1UL) /**< CTRL_PARMD_0 Value */
 #define MXC_S_UART_CTRL_PARMD_0                                                \
-	(MXC_V_UART_CTRL_PARMD_0                                               \
-	 << MXC_F_UART_CTRL_PARMD_POS) /**< CTRL_PARMD_0 Setting */
+	(MXC_V_UART_CTRL_PARMD_0 << MXC_F_UART_CTRL_PARMD_POS) /**<            \
+								  CTRL_PARMD_0 \
+								  Setting */
 
 #define MXC_F_UART_CTRL_TX_FLUSH_POS 5 /**< CTRL_TX_FLUSH Position */
 #define MXC_F_UART_CTRL_TX_FLUSH                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_CTRL_TX_FLUSH_POS)) /**< CTRL_TX_FLUSH Mask */
+	((uint32_t)(0x1UL << MXC_F_UART_CTRL_TX_FLUSH_POS)) /**< CTRL_TX_FLUSH \
+							       Mask */
 
 #define MXC_F_UART_CTRL_RX_FLUSH_POS 6 /**< CTRL_RX_FLUSH Position */
 #define MXC_F_UART_CTRL_RX_FLUSH                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_CTRL_RX_FLUSH_POS)) /**< CTRL_RX_FLUSH Mask */
+	((uint32_t)(0x1UL << MXC_F_UART_CTRL_RX_FLUSH_POS)) /**< CTRL_RX_FLUSH \
+							       Mask */
 
 #define MXC_F_UART_CTRL_BITACC_POS 7 /**< CTRL_BITACC Position */
-#define MXC_F_UART_CTRL_BITACC                                                 \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_UART_CTRL_BITACC_POS)) /**< CTRL_BITACC Mask */
-#define MXC_V_UART_CTRL_BITACC_FRAME                                           \
+#define MXC_F_UART_CTRL_BITACC                                             \
+	((uint32_t)(0x1UL << MXC_F_UART_CTRL_BITACC_POS)) /**< CTRL_BITACC \
+							     Mask */
+#define MXC_V_UART_CTRL_BITACC_FRAME \
 	((uint32_t)0x0UL) /**< CTRL_BITACC_FRAME Value */
-#define MXC_S_UART_CTRL_BITACC_FRAME                                           \
-	(MXC_V_UART_CTRL_BITACC_FRAME                                          \
-	 << MXC_F_UART_CTRL_BITACC_POS) /**< CTRL_BITACC_FRAME Setting */
-#define MXC_V_UART_CTRL_BITACC_BIT                                             \
+#define MXC_S_UART_CTRL_BITACC_FRAME                         \
+	(MXC_V_UART_CTRL_BITACC_FRAME                        \
+	 << MXC_F_UART_CTRL_BITACC_POS) /**<                 \
+					   CTRL_BITACC_FRAME \
+					   Setting           \
+					 */
+#define MXC_V_UART_CTRL_BITACC_BIT \
 	((uint32_t)0x1UL) /**< CTRL_BITACC_BIT Value */
-#define MXC_S_UART_CTRL_BITACC_BIT                                             \
-	(MXC_V_UART_CTRL_BITACC_BIT                                            \
-	 << MXC_F_UART_CTRL_BITACC_POS) /**< CTRL_BITACC_BIT Setting */
+#define MXC_S_UART_CTRL_BITACC_BIT                         \
+	(MXC_V_UART_CTRL_BITACC_BIT                        \
+	 << MXC_F_UART_CTRL_BITACC_POS) /**<               \
+					   CTRL_BITACC_BIT \
+					   Setting         \
+					 */
 
 #define MXC_F_UART_CTRL_CHAR_SIZE_POS 8 /**< CTRL_CHAR_SIZE Position */
 #define MXC_F_UART_CTRL_CHAR_SIZE                                              \
-	((uint32_t)(                                                           \
-		0x3UL                                                          \
-		<< MXC_F_UART_CTRL_CHAR_SIZE_POS)) /**< CTRL_CHAR_SIZE Mask */
-#define MXC_V_UART_CTRL_CHAR_SIZE_5                                            \
+	((uint32_t)(0x3UL << MXC_F_UART_CTRL_CHAR_SIZE_POS)) /**<              \
+								CTRL_CHAR_SIZE \
+								Mask */
+#define MXC_V_UART_CTRL_CHAR_SIZE_5 \
 	((uint32_t)0x0UL) /**< CTRL_CHAR_SIZE_5 Value */
-#define MXC_S_UART_CTRL_CHAR_SIZE_5                                            \
-	(MXC_V_UART_CTRL_CHAR_SIZE_5                                           \
-	 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_5 Setting */
-#define MXC_V_UART_CTRL_CHAR_SIZE_6                                            \
+#define MXC_S_UART_CTRL_CHAR_SIZE_5                            \
+	(MXC_V_UART_CTRL_CHAR_SIZE_5                           \
+	 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**<                \
+					      CTRL_CHAR_SIZE_5 \
+					      Setting          \
+					    */
+#define MXC_V_UART_CTRL_CHAR_SIZE_6 \
 	((uint32_t)0x1UL) /**< CTRL_CHAR_SIZE_6 Value */
-#define MXC_S_UART_CTRL_CHAR_SIZE_6                                            \
-	(MXC_V_UART_CTRL_CHAR_SIZE_6                                           \
-	 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_6 Setting */
-#define MXC_V_UART_CTRL_CHAR_SIZE_7                                            \
+#define MXC_S_UART_CTRL_CHAR_SIZE_6                            \
+	(MXC_V_UART_CTRL_CHAR_SIZE_6                           \
+	 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**<                \
+					      CTRL_CHAR_SIZE_6 \
+					      Setting          \
+					    */
+#define MXC_V_UART_CTRL_CHAR_SIZE_7 \
 	((uint32_t)0x2UL) /**< CTRL_CHAR_SIZE_7 Value */
-#define MXC_S_UART_CTRL_CHAR_SIZE_7                                            \
-	(MXC_V_UART_CTRL_CHAR_SIZE_7                                           \
-	 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_7 Setting */
-#define MXC_V_UART_CTRL_CHAR_SIZE_8                                            \
+#define MXC_S_UART_CTRL_CHAR_SIZE_7                            \
+	(MXC_V_UART_CTRL_CHAR_SIZE_7                           \
+	 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**<                \
+					      CTRL_CHAR_SIZE_7 \
+					      Setting          \
+					    */
+#define MXC_V_UART_CTRL_CHAR_SIZE_8 \
 	((uint32_t)0x3UL) /**< CTRL_CHAR_SIZE_8 Value */
-#define MXC_S_UART_CTRL_CHAR_SIZE_8                                            \
-	(MXC_V_UART_CTRL_CHAR_SIZE_8                                           \
-	 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_8 Setting */
+#define MXC_S_UART_CTRL_CHAR_SIZE_8                            \
+	(MXC_V_UART_CTRL_CHAR_SIZE_8                           \
+	 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**<                \
+					      CTRL_CHAR_SIZE_8 \
+					      Setting          \
+					    */
 
 #define MXC_F_UART_CTRL_STOPBITS_POS 10 /**< CTRL_STOPBITS Position */
 #define MXC_F_UART_CTRL_STOPBITS                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_CTRL_STOPBITS_POS)) /**< CTRL_STOPBITS Mask */
-#define MXC_V_UART_CTRL_STOPBITS_1                                             \
+	((uint32_t)(0x1UL << MXC_F_UART_CTRL_STOPBITS_POS)) /**< CTRL_STOPBITS \
+							       Mask */
+#define MXC_V_UART_CTRL_STOPBITS_1 \
 	((uint32_t)0x0UL) /**< CTRL_STOPBITS_1 Value */
-#define MXC_S_UART_CTRL_STOPBITS_1                                             \
-	(MXC_V_UART_CTRL_STOPBITS_1                                            \
-	 << MXC_F_UART_CTRL_STOPBITS_POS) /**< CTRL_STOPBITS_1 Setting */
-#define MXC_V_UART_CTRL_STOPBITS_1_5                                           \
+#define MXC_S_UART_CTRL_STOPBITS_1                           \
+	(MXC_V_UART_CTRL_STOPBITS_1                          \
+	 << MXC_F_UART_CTRL_STOPBITS_POS) /**<               \
+					     CTRL_STOPBITS_1 \
+					     Setting         \
+					   */
+#define MXC_V_UART_CTRL_STOPBITS_1_5 \
 	((uint32_t)0x1UL) /**< CTRL_STOPBITS_1_5 Value */
-#define MXC_S_UART_CTRL_STOPBITS_1_5                                           \
-	(MXC_V_UART_CTRL_STOPBITS_1_5                                          \
-	 << MXC_F_UART_CTRL_STOPBITS_POS) /**< CTRL_STOPBITS_1_5 Setting */
+#define MXC_S_UART_CTRL_STOPBITS_1_5                           \
+	(MXC_V_UART_CTRL_STOPBITS_1_5                          \
+	 << MXC_F_UART_CTRL_STOPBITS_POS) /**<                 \
+					     CTRL_STOPBITS_1_5 \
+					     Setting           \
+					   */
 
 #define MXC_F_UART_CTRL_FLOW_CTRL_POS 11 /**< CTRL_FLOW_CTRL Position */
 #define MXC_F_UART_CTRL_FLOW_CTRL                                              \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_CTRL_FLOW_CTRL_POS)) /**< CTRL_FLOW_CTRL Mask */
-#define MXC_V_UART_CTRL_FLOW_CTRL_EN                                           \
+	((uint32_t)(0x1UL << MXC_F_UART_CTRL_FLOW_CTRL_POS)) /**<              \
+								CTRL_FLOW_CTRL \
+								Mask */
+#define MXC_V_UART_CTRL_FLOW_CTRL_EN \
 	((uint32_t)0x1UL) /**< CTRL_FLOW_CTRL_EN Value */
-#define MXC_S_UART_CTRL_FLOW_CTRL_EN                                           \
-	(MXC_V_UART_CTRL_FLOW_CTRL_EN                                          \
-	 << MXC_F_UART_CTRL_FLOW_CTRL_POS) /**< CTRL_FLOW_CTRL_EN Setting */
-#define MXC_V_UART_CTRL_FLOW_CTRL_DIS                                          \
+#define MXC_S_UART_CTRL_FLOW_CTRL_EN                            \
+	(MXC_V_UART_CTRL_FLOW_CTRL_EN                           \
+	 << MXC_F_UART_CTRL_FLOW_CTRL_POS) /**<                 \
+					      CTRL_FLOW_CTRL_EN \
+					      Setting           \
+					    */
+#define MXC_V_UART_CTRL_FLOW_CTRL_DIS \
 	((uint32_t)0x0UL) /**< CTRL_FLOW_CTRL_DIS Value */
-#define MXC_S_UART_CTRL_FLOW_CTRL_DIS                                          \
-	(MXC_V_UART_CTRL_FLOW_CTRL_DIS                                         \
-	 << MXC_F_UART_CTRL_FLOW_CTRL_POS) /**< CTRL_FLOW_CTRL_DIS Setting */
+#define MXC_S_UART_CTRL_FLOW_CTRL_DIS                            \
+	(MXC_V_UART_CTRL_FLOW_CTRL_DIS                           \
+	 << MXC_F_UART_CTRL_FLOW_CTRL_POS) /**<                  \
+					      CTRL_FLOW_CTRL_DIS \
+					      Setting            \
+					    */
 
 #define MXC_F_UART_CTRL_FLOW_POL_POS 12 /**< CTRL_FLOW_POL Position */
 #define MXC_F_UART_CTRL_FLOW_POL                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_CTRL_FLOW_POL_POS)) /**< CTRL_FLOW_POL Mask */
-#define MXC_V_UART_CTRL_FLOW_POL_0                                             \
+	((uint32_t)(0x1UL << MXC_F_UART_CTRL_FLOW_POL_POS)) /**< CTRL_FLOW_POL \
+							       Mask */
+#define MXC_V_UART_CTRL_FLOW_POL_0 \
 	((uint32_t)0x0UL) /**< CTRL_FLOW_POL_0 Value */
-#define MXC_S_UART_CTRL_FLOW_POL_0                                             \
-	(MXC_V_UART_CTRL_FLOW_POL_0                                            \
-	 << MXC_F_UART_CTRL_FLOW_POL_POS) /**< CTRL_FLOW_POL_0 Setting */
-#define MXC_V_UART_CTRL_FLOW_POL_1                                             \
+#define MXC_S_UART_CTRL_FLOW_POL_0                           \
+	(MXC_V_UART_CTRL_FLOW_POL_0                          \
+	 << MXC_F_UART_CTRL_FLOW_POL_POS) /**<               \
+					     CTRL_FLOW_POL_0 \
+					     Setting         \
+					   */
+#define MXC_V_UART_CTRL_FLOW_POL_1 \
 	((uint32_t)0x1UL) /**< CTRL_FLOW_POL_1 Value */
-#define MXC_S_UART_CTRL_FLOW_POL_1                                             \
-	(MXC_V_UART_CTRL_FLOW_POL_1                                            \
-	 << MXC_F_UART_CTRL_FLOW_POL_POS) /**< CTRL_FLOW_POL_1 Setting */
+#define MXC_S_UART_CTRL_FLOW_POL_1                           \
+	(MXC_V_UART_CTRL_FLOW_POL_1                          \
+	 << MXC_F_UART_CTRL_FLOW_POL_POS) /**<               \
+					     CTRL_FLOW_POL_1 \
+					     Setting         \
+					   */
 
 #define MXC_F_UART_CTRL_NULL_MODEM_POS 13 /**< CTRL_NULL_MODEM Position */
-#define MXC_F_UART_CTRL_NULL_MODEM                                             \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_UART_CTRL_NULL_MODEM_POS)) /**< CTRL_NULL_MODEM \
-							     Mask */
-#define MXC_V_UART_CTRL_NULL_MODEM_DIS                                         \
+#define MXC_F_UART_CTRL_NULL_MODEM                                           \
+	((uint32_t)(0x1UL                                                    \
+		    << MXC_F_UART_CTRL_NULL_MODEM_POS)) /**< CTRL_NULL_MODEM \
+							   Mask */
+#define MXC_V_UART_CTRL_NULL_MODEM_DIS \
 	((uint32_t)0x0UL) /**< CTRL_NULL_MODEM_DIS Value */
-#define MXC_S_UART_CTRL_NULL_MODEM_DIS                                         \
-	(MXC_V_UART_CTRL_NULL_MODEM_DIS                                        \
-	 << MXC_F_UART_CTRL_NULL_MODEM_POS) /**< CTRL_NULL_MODEM_DIS Setting   \
+#define MXC_S_UART_CTRL_NULL_MODEM_DIS                                       \
+	(MXC_V_UART_CTRL_NULL_MODEM_DIS                                      \
+	 << MXC_F_UART_CTRL_NULL_MODEM_POS) /**< CTRL_NULL_MODEM_DIS Setting \
 					     */
-#define MXC_V_UART_CTRL_NULL_MODEM_EN                                          \
+#define MXC_V_UART_CTRL_NULL_MODEM_EN \
 	((uint32_t)0x1UL) /**< CTRL_NULL_MODEM_EN Value */
-#define MXC_S_UART_CTRL_NULL_MODEM_EN                                          \
-	(MXC_V_UART_CTRL_NULL_MODEM_EN                                         \
+#define MXC_S_UART_CTRL_NULL_MODEM_EN  \
+	(MXC_V_UART_CTRL_NULL_MODEM_EN \
 	 << MXC_F_UART_CTRL_NULL_MODEM_POS) /**< CTRL_NULL_MODEM_EN Setting */
 
 #define MXC_F_UART_CTRL_BREAK_POS 14 /**< CTRL_BREAK Position */
-#define MXC_F_UART_CTRL_BREAK                                                  \
-	((uint32_t)(0x1UL << MXC_F_UART_CTRL_BREAK_POS)) /**< CTRL_BREAK Mask  \
+#define MXC_F_UART_CTRL_BREAK                                                 \
+	((uint32_t)(0x1UL << MXC_F_UART_CTRL_BREAK_POS)) /**< CTRL_BREAK Mask \
 							  */
-#define MXC_V_UART_CTRL_BREAK_DIS                                              \
-	((uint32_t)0x0UL) /**< CTRL_BREAK_DIS Value                            \
+#define MXC_V_UART_CTRL_BREAK_DIS                   \
+	((uint32_t)0x0UL) /**< CTRL_BREAK_DIS Value \
 			   */
-#define MXC_S_UART_CTRL_BREAK_DIS                                              \
-	(MXC_V_UART_CTRL_BREAK_DIS                                             \
-	 << MXC_F_UART_CTRL_BREAK_POS) /**< CTRL_BREAK_DIS Setting */
+#define MXC_S_UART_CTRL_BREAK_DIS                        \
+	(MXC_V_UART_CTRL_BREAK_DIS                       \
+	 << MXC_F_UART_CTRL_BREAK_POS) /**<              \
+					  CTRL_BREAK_DIS \
+					  Setting */
 #define MXC_V_UART_CTRL_BREAK_EN ((uint32_t)0x1UL) /**< CTRL_BREAK_EN Value */
-#define MXC_S_UART_CTRL_BREAK_EN                                               \
-	(MXC_V_UART_CTRL_BREAK_EN                                              \
-	 << MXC_F_UART_CTRL_BREAK_POS) /**< CTRL_BREAK_EN Setting */
+#define MXC_S_UART_CTRL_BREAK_EN                        \
+	(MXC_V_UART_CTRL_BREAK_EN                       \
+	 << MXC_F_UART_CTRL_BREAK_POS) /**<             \
+					  CTRL_BREAK_EN \
+					  Setting */
 
 #define MXC_F_UART_CTRL_CLKSEL_POS 15 /**< CTRL_CLKSEL Position */
-#define MXC_F_UART_CTRL_CLKSEL                                                 \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_UART_CTRL_CLKSEL_POS)) /**< CTRL_CLKSEL Mask */
-#define MXC_V_UART_CTRL_CLKSEL_SYSTEM                                          \
+#define MXC_F_UART_CTRL_CLKSEL                                             \
+	((uint32_t)(0x1UL << MXC_F_UART_CTRL_CLKSEL_POS)) /**< CTRL_CLKSEL \
+							     Mask */
+#define MXC_V_UART_CTRL_CLKSEL_SYSTEM \
 	((uint32_t)0x0UL) /**< CTRL_CLKSEL_SYSTEM Value */
-#define MXC_S_UART_CTRL_CLKSEL_SYSTEM                                          \
-	(MXC_V_UART_CTRL_CLKSEL_SYSTEM                                         \
-	 << MXC_F_UART_CTRL_CLKSEL_POS) /**< CTRL_CLKSEL_SYSTEM Setting */
-#define MXC_V_UART_CTRL_CLKSEL_ALTERNATE                                       \
+#define MXC_S_UART_CTRL_CLKSEL_SYSTEM                         \
+	(MXC_V_UART_CTRL_CLKSEL_SYSTEM                        \
+	 << MXC_F_UART_CTRL_CLKSEL_POS) /**<                  \
+					   CTRL_CLKSEL_SYSTEM \
+					   Setting            \
+					 */
+#define MXC_V_UART_CTRL_CLKSEL_ALTERNATE \
 	((uint32_t)0x1UL) /**< CTRL_CLKSEL_ALTERNATE Value */
-#define MXC_S_UART_CTRL_CLKSEL_ALTERNATE                                       \
-	(MXC_V_UART_CTRL_CLKSEL_ALTERNATE                                      \
-	 << MXC_F_UART_CTRL_CLKSEL_POS) /**< CTRL_CLKSEL_ALTERNATE Setting */
+#define MXC_S_UART_CTRL_CLKSEL_ALTERNATE                         \
+	(MXC_V_UART_CTRL_CLKSEL_ALTERNATE                        \
+	 << MXC_F_UART_CTRL_CLKSEL_POS) /**<                     \
+					   CTRL_CLKSEL_ALTERNATE \
+					   Setting               \
+					 */
 
 #define MXC_F_UART_CTRL_RX_TO_POS 16 /**< CTRL_RX_TO Position */
 #define MXC_F_UART_CTRL_RX_TO                                                  \
-	((uint32_t)(                                                           \
-		0xFFUL << MXC_F_UART_CTRL_RX_TO_POS)) /**< CTRL_RX_TO Mask */
+	((uint32_t)(0xFFUL << MXC_F_UART_CTRL_RX_TO_POS)) /**< CTRL_RX_TO Mask \
+							   */
 
 /**
  * Threshold Control register.
  */
-#define MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS                              \
+#define MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS \
 	0 /**< THRESH_CTRL_RX_FIFO_THRESH Position */
-#define MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH                                                \
-	((uint32_t)(                                                                         \
-		0x3FUL                                                                       \
-		<< MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS)) /**<                          \
-								  THRESH_CTRL_RX_FIFO_THRESH \
-								  Mask */
+#define MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH                                                    \
+	((uint32_t)(0x3FUL                                                                       \
+		    << MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS)) /**<                          \
+								      THRESH_CTRL_RX_FIFO_THRESH \
+								      Mask */
 
-#define MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH_POS                              \
+#define MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH_POS \
 	8 /**< THRESH_CTRL_TX_FIFO_THRESH Position */
-#define MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH                                                \
-	((uint32_t)(                                                                         \
-		0x3FUL                                                                       \
-		<< MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH_POS)) /**<                          \
-								  THRESH_CTRL_TX_FIFO_THRESH \
-								  Mask */
+#define MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH                                                    \
+	((uint32_t)(0x3FUL                                                                       \
+		    << MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH_POS)) /**<                          \
+								      THRESH_CTRL_TX_FIFO_THRESH \
+								      Mask */
 
-#define MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH_POS                             \
+#define MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH_POS \
 	16 /**< THRESH_CTRL_RTS_FIFO_THRESH Position */
-#define MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH                                                 \
-	((uint32_t)(                                                                           \
-		0x3FUL                                                                         \
-		<< MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH_POS)) /**<                           \
-								   THRESH_CTRL_RTS_FIFO_THRESH \
-								   Mask */
+#define MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH                                                     \
+	((uint32_t)(0x3FUL                                                                         \
+		    << MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH_POS)) /**<                           \
+								       THRESH_CTRL_RTS_FIFO_THRESH \
+								       Mask */
 
 /**
  * Status Register.
  */
 #define MXC_F_UART_STATUS_TX_BUSY_POS 0 /**< STATUS_TX_BUSY Position */
 #define MXC_F_UART_STATUS_TX_BUSY                                              \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_STATUS_TX_BUSY_POS)) /**< STATUS_TX_BUSY Mask */
+	((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_BUSY_POS)) /**<              \
+								STATUS_TX_BUSY \
+								Mask */
 
 #define MXC_F_UART_STATUS_RX_BUSY_POS 1 /**< STATUS_RX_BUSY Position */
 #define MXC_F_UART_STATUS_RX_BUSY                                              \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_STATUS_RX_BUSY_POS)) /**< STATUS_RX_BUSY Mask */
+	((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_BUSY_POS)) /**<              \
+								STATUS_RX_BUSY \
+								Mask */
 
 #define MXC_F_UART_STATUS_PARITY_POS 2 /**< STATUS_PARITY Position */
 #define MXC_F_UART_STATUS_PARITY                                               \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_STATUS_PARITY_POS)) /**< STATUS_PARITY Mask */
+	((uint32_t)(0x1UL << MXC_F_UART_STATUS_PARITY_POS)) /**< STATUS_PARITY \
+							       Mask */
 
 #define MXC_F_UART_STATUS_BREAK_POS 3 /**< STATUS_BREAK Position */
-#define MXC_F_UART_STATUS_BREAK                                                \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_UART_STATUS_BREAK_POS)) /**< STATUS_BREAK Mask */
+#define MXC_F_UART_STATUS_BREAK                                              \
+	((uint32_t)(0x1UL << MXC_F_UART_STATUS_BREAK_POS)) /**< STATUS_BREAK \
+							      Mask */
 
 #define MXC_F_UART_STATUS_RX_EMPTY_POS 4 /**< STATUS_RX_EMPTY Position */
-#define MXC_F_UART_STATUS_RX_EMPTY                                             \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_UART_STATUS_RX_EMPTY_POS)) /**< STATUS_RX_EMPTY \
-							     Mask */
+#define MXC_F_UART_STATUS_RX_EMPTY                                           \
+	((uint32_t)(0x1UL                                                    \
+		    << MXC_F_UART_STATUS_RX_EMPTY_POS)) /**< STATUS_RX_EMPTY \
+							   Mask */
 
 #define MXC_F_UART_STATUS_RX_FULL_POS 5 /**< STATUS_RX_FULL Position */
 #define MXC_F_UART_STATUS_RX_FULL                                              \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */
+	((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_FULL_POS)) /**<              \
+								STATUS_RX_FULL \
+								Mask */
 
 #define MXC_F_UART_STATUS_TX_EMPTY_POS 6 /**< STATUS_TX_EMPTY Position */
-#define MXC_F_UART_STATUS_TX_EMPTY                                             \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_UART_STATUS_TX_EMPTY_POS)) /**< STATUS_TX_EMPTY \
-							     Mask */
+#define MXC_F_UART_STATUS_TX_EMPTY                                           \
+	((uint32_t)(0x1UL                                                    \
+		    << MXC_F_UART_STATUS_TX_EMPTY_POS)) /**< STATUS_TX_EMPTY \
+							   Mask */
 
 #define MXC_F_UART_STATUS_TX_FULL_POS 7 /**< STATUS_TX_FULL Position */
 #define MXC_F_UART_STATUS_TX_FULL                                              \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */
+	((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_FULL_POS)) /**<              \
+								STATUS_TX_FULL \
+								Mask */
 
-#define MXC_F_UART_STATUS_RX_FIFO_CNT_POS                                      \
-	8 /**< STATUS_RX_FIFO_CNT Position                                     \
+#define MXC_F_UART_STATUS_RX_FIFO_CNT_POS  \
+	8 /**< STATUS_RX_FIFO_CNT Position \
 	   */
-#define MXC_F_UART_STATUS_RX_FIFO_CNT                                          \
-	((uint32_t)(                                                           \
-		0x3FUL                                                         \
-		<< MXC_F_UART_STATUS_RX_FIFO_CNT_POS)) /**< STATUS_RX_FIFO_CNT \
-							  Mask */
-
-#define MXC_F_UART_STATUS_TX_FIFO_CNT_POS                                      \
-	16 /**< STATUS_TX_FIFO_CNT Position                                    \
+#define MXC_F_UART_STATUS_RX_FIFO_CNT                                            \
+	((uint32_t)(0x3FUL                                                       \
+		    << MXC_F_UART_STATUS_RX_FIFO_CNT_POS)) /**<                  \
+							      STATUS_RX_FIFO_CNT \
+							      Mask */
+
+#define MXC_F_UART_STATUS_TX_FIFO_CNT_POS   \
+	16 /**< STATUS_TX_FIFO_CNT Position \
 	    */
-#define MXC_F_UART_STATUS_TX_FIFO_CNT                                          \
-	((uint32_t)(                                                           \
-		0x3FUL                                                         \
-		<< MXC_F_UART_STATUS_TX_FIFO_CNT_POS)) /**< STATUS_TX_FIFO_CNT \
-							  Mask */
+#define MXC_F_UART_STATUS_TX_FIFO_CNT                                            \
+	((uint32_t)(0x3FUL                                                       \
+		    << MXC_F_UART_STATUS_TX_FIFO_CNT_POS)) /**<                  \
+							      STATUS_TX_FIFO_CNT \
+							      Mask */
 
 #define MXC_F_UART_STATUS_RX_TO_POS 24 /**< STATUS_RX_TO Position */
-#define MXC_F_UART_STATUS_RX_TO                                                \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_UART_STATUS_RX_TO_POS)) /**< STATUS_RX_TO Mask */
+#define MXC_F_UART_STATUS_RX_TO                                              \
+	((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_TO_POS)) /**< STATUS_RX_TO \
+							      Mask */
 
 /**
  * Interrupt Enable Register.
  */
-#define MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS                                   \
+#define MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS \
 	0 /**< INT_EN_RX_FRAME_ERROR Position */
-#define MXC_F_UART_INT_EN_RX_FRAME_ERROR                                           \
-	((uint32_t)(                                                               \
-		0x1UL                                                              \
-		<< MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS)) /**<                     \
-							     INT_EN_RX_FRAME_ERROR \
-							     Mask */
+#define MXC_F_UART_INT_EN_RX_FRAME_ERROR                                               \
+	((uint32_t)(0x1UL                                                              \
+		    << MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS)) /**<                     \
+								 INT_EN_RX_FRAME_ERROR \
+								 Mask */
 
-#define MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS                                  \
+#define MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS \
 	1 /**< INT_EN_RX_PARITY_ERROR Position */
-#define MXC_F_UART_INT_EN_RX_PARITY_ERROR                                            \
-	((uint32_t)(                                                                 \
-		0x1UL                                                                \
-		<< MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS)) /**<                      \
-							      INT_EN_RX_PARITY_ERROR \
-							      Mask */
+#define MXC_F_UART_INT_EN_RX_PARITY_ERROR                                                \
+	((uint32_t)(0x1UL                                                                \
+		    << MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS)) /**<                      \
+								  INT_EN_RX_PARITY_ERROR \
+								  Mask */
 
 #define MXC_F_UART_INT_EN_CTS_CHANGE_POS 2 /**< INT_EN_CTS_CHANGE Position */
 #define MXC_F_UART_INT_EN_CTS_CHANGE                                           \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_INT_EN_CTS_CHANGE_POS)) /**< INT_EN_CTS_CHANGE   \
-							 Mask */
+	((uint32_t)(0x1UL                                                      \
+		    << MXC_F_UART_INT_EN_CTS_CHANGE_POS)) /**<                 \
+							     INT_EN_CTS_CHANGE \
+							     Mask */
 
 #define MXC_F_UART_INT_EN_RX_OVERRUN_POS 3 /**< INT_EN_RX_OVERRUN Position */
 #define MXC_F_UART_INT_EN_RX_OVERRUN                                           \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_INT_EN_RX_OVERRUN_POS)) /**< INT_EN_RX_OVERRUN   \
-							 Mask */
+	((uint32_t)(0x1UL                                                      \
+		    << MXC_F_UART_INT_EN_RX_OVERRUN_POS)) /**<                 \
+							     INT_EN_RX_OVERRUN \
+							     Mask */
 
-#define MXC_F_UART_INT_EN_RX_FIFO_THRESH_POS                                   \
+#define MXC_F_UART_INT_EN_RX_FIFO_THRESH_POS \
 	4 /**< INT_EN_RX_FIFO_THRESH Position */
-#define MXC_F_UART_INT_EN_RX_FIFO_THRESH                                           \
-	((uint32_t)(                                                               \
-		0x1UL                                                              \
-		<< MXC_F_UART_INT_EN_RX_FIFO_THRESH_POS)) /**<                     \
-							     INT_EN_RX_FIFO_THRESH \
-							     Mask */
+#define MXC_F_UART_INT_EN_RX_FIFO_THRESH                                               \
+	((uint32_t)(0x1UL                                                              \
+		    << MXC_F_UART_INT_EN_RX_FIFO_THRESH_POS)) /**<                     \
+								 INT_EN_RX_FIFO_THRESH \
+								 Mask */
 
-#define MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY_POS                             \
+#define MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY_POS \
 	5 /**< INT_EN_TX_FIFO_ALMOST_EMPTY Position */
-#define MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY                                                 \
-	((uint32_t)(                                                                           \
-		0x1UL                                                                          \
-		<< MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY_POS)) /**<                           \
-								   INT_EN_TX_FIFO_ALMOST_EMPTY \
-								   Mask */
-
-#define MXC_F_UART_INT_EN_TX_FIFO_THRESH_POS                                   \
+#define MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY                                                     \
+	((uint32_t)(0x1UL                                                                          \
+		    << MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY_POS)) /**<                           \
+								       INT_EN_TX_FIFO_ALMOST_EMPTY \
+								       Mask */
+
+#define MXC_F_UART_INT_EN_TX_FIFO_THRESH_POS \
 	6 /**< INT_EN_TX_FIFO_THRESH Position */
-#define MXC_F_UART_INT_EN_TX_FIFO_THRESH                                           \
-	((uint32_t)(                                                               \
-		0x1UL                                                              \
-		<< MXC_F_UART_INT_EN_TX_FIFO_THRESH_POS)) /**<                     \
-							     INT_EN_TX_FIFO_THRESH \
-							     Mask */
+#define MXC_F_UART_INT_EN_TX_FIFO_THRESH                                               \
+	((uint32_t)(0x1UL                                                              \
+		    << MXC_F_UART_INT_EN_TX_FIFO_THRESH_POS)) /**<                     \
+								 INT_EN_TX_FIFO_THRESH \
+								 Mask */
 
 #define MXC_F_UART_INT_EN_BREAK_POS 7 /**< INT_EN_BREAK Position */
-#define MXC_F_UART_INT_EN_BREAK                                                \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_UART_INT_EN_BREAK_POS)) /**< INT_EN_BREAK Mask */
+#define MXC_F_UART_INT_EN_BREAK                                              \
+	((uint32_t)(0x1UL << MXC_F_UART_INT_EN_BREAK_POS)) /**< INT_EN_BREAK \
+							      Mask */
 
 #define MXC_F_UART_INT_EN_RX_TIMEOUT_POS 8 /**< INT_EN_RX_TIMEOUT Position */
 #define MXC_F_UART_INT_EN_RX_TIMEOUT                                           \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_INT_EN_RX_TIMEOUT_POS)) /**< INT_EN_RX_TIMEOUT   \
-							 Mask */
+	((uint32_t)(0x1UL                                                      \
+		    << MXC_F_UART_INT_EN_RX_TIMEOUT_POS)) /**<                 \
+							     INT_EN_RX_TIMEOUT \
+							     Mask */
 
 #define MXC_F_UART_INT_EN_LAST_BREAK_POS 9 /**< INT_EN_LAST_BREAK Position */
 #define MXC_F_UART_INT_EN_LAST_BREAK                                           \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_INT_EN_LAST_BREAK_POS)) /**< INT_EN_LAST_BREAK   \
-							 Mask */
+	((uint32_t)(0x1UL                                                      \
+		    << MXC_F_UART_INT_EN_LAST_BREAK_POS)) /**<                 \
+							     INT_EN_LAST_BREAK \
+							     Mask */
 
 /**
  * Interrupt Status Flags.
  */
-#define MXC_F_UART_INT_FL_RX_FRAME_ERROR_POS                                   \
+#define MXC_F_UART_INT_FL_RX_FRAME_ERROR_POS \
 	0 /**< INT_FL_RX_FRAME_ERROR Position */
-#define MXC_F_UART_INT_FL_RX_FRAME_ERROR                                           \
-	((uint32_t)(                                                               \
-		0x1UL                                                              \
-		<< MXC_F_UART_INT_FL_RX_FRAME_ERROR_POS)) /**<                     \
-							     INT_FL_RX_FRAME_ERROR \
-							     Mask */
+#define MXC_F_UART_INT_FL_RX_FRAME_ERROR                                               \
+	((uint32_t)(0x1UL                                                              \
+		    << MXC_F_UART_INT_FL_RX_FRAME_ERROR_POS)) /**<                     \
+								 INT_FL_RX_FRAME_ERROR \
+								 Mask */
 
-#define MXC_F_UART_INT_FL_RX_PARITY_ERROR_POS                                  \
+#define MXC_F_UART_INT_FL_RX_PARITY_ERROR_POS \
 	1 /**< INT_FL_RX_PARITY_ERROR Position */
-#define MXC_F_UART_INT_FL_RX_PARITY_ERROR                                            \
-	((uint32_t)(                                                                 \
-		0x1UL                                                                \
-		<< MXC_F_UART_INT_FL_RX_PARITY_ERROR_POS)) /**<                      \
-							      INT_FL_RX_PARITY_ERROR \
-							      Mask */
+#define MXC_F_UART_INT_FL_RX_PARITY_ERROR                                                \
+	((uint32_t)(0x1UL                                                                \
+		    << MXC_F_UART_INT_FL_RX_PARITY_ERROR_POS)) /**<                      \
+								  INT_FL_RX_PARITY_ERROR \
+								  Mask */
 
 #define MXC_F_UART_INT_FL_CTS_CHANGE_POS 2 /**< INT_FL_CTS_CHANGE Position */
 #define MXC_F_UART_INT_FL_CTS_CHANGE                                           \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_INT_FL_CTS_CHANGE_POS)) /**< INT_FL_CTS_CHANGE   \
-							 Mask */
+	((uint32_t)(0x1UL                                                      \
+		    << MXC_F_UART_INT_FL_CTS_CHANGE_POS)) /**<                 \
+							     INT_FL_CTS_CHANGE \
+							     Mask */
 
 #define MXC_F_UART_INT_FL_RX_OVERRUN_POS 3 /**< INT_FL_RX_OVERRUN Position */
 #define MXC_F_UART_INT_FL_RX_OVERRUN                                           \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_INT_FL_RX_OVERRUN_POS)) /**< INT_FL_RX_OVERRUN   \
-							 Mask */
+	((uint32_t)(0x1UL                                                      \
+		    << MXC_F_UART_INT_FL_RX_OVERRUN_POS)) /**<                 \
+							     INT_FL_RX_OVERRUN \
+							     Mask */
 
-#define MXC_F_UART_INT_FL_RX_FIFO_THRESH_POS                                   \
+#define MXC_F_UART_INT_FL_RX_FIFO_THRESH_POS \
 	4 /**< INT_FL_RX_FIFO_THRESH Position */
-#define MXC_F_UART_INT_FL_RX_FIFO_THRESH                                           \
-	((uint32_t)(                                                               \
-		0x1UL                                                              \
-		<< MXC_F_UART_INT_FL_RX_FIFO_THRESH_POS)) /**<                     \
-							     INT_FL_RX_FIFO_THRESH \
-							     Mask */
+#define MXC_F_UART_INT_FL_RX_FIFO_THRESH                                               \
+	((uint32_t)(0x1UL                                                              \
+		    << MXC_F_UART_INT_FL_RX_FIFO_THRESH_POS)) /**<                     \
+								 INT_FL_RX_FIFO_THRESH \
+								 Mask */
 
-#define MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY_POS                             \
+#define MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY_POS \
 	5 /**< INT_FL_TX_FIFO_ALMOST_EMPTY Position */
-#define MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY                                                 \
-	((uint32_t)(                                                                           \
-		0x1UL                                                                          \
-		<< MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY_POS)) /**<                           \
-								   INT_FL_TX_FIFO_ALMOST_EMPTY \
-								   Mask */
-
-#define MXC_F_UART_INT_FL_TX_FIFO_THRESH_POS                                   \
+#define MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY                                                     \
+	((uint32_t)(0x1UL                                                                          \
+		    << MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY_POS)) /**<                           \
+								       INT_FL_TX_FIFO_ALMOST_EMPTY \
+								       Mask */
+
+#define MXC_F_UART_INT_FL_TX_FIFO_THRESH_POS \
 	6 /**< INT_FL_TX_FIFO_THRESH Position */
-#define MXC_F_UART_INT_FL_TX_FIFO_THRESH                                           \
-	((uint32_t)(                                                               \
-		0x1UL                                                              \
-		<< MXC_F_UART_INT_FL_TX_FIFO_THRESH_POS)) /**<                     \
-							     INT_FL_TX_FIFO_THRESH \
-							     Mask */
+#define MXC_F_UART_INT_FL_TX_FIFO_THRESH                                               \
+	((uint32_t)(0x1UL                                                              \
+		    << MXC_F_UART_INT_FL_TX_FIFO_THRESH_POS)) /**<                     \
+								 INT_FL_TX_FIFO_THRESH \
+								 Mask */
 
 #define MXC_F_UART_INT_FL_BREAK_POS 7 /**< INT_FL_BREAK Position */
-#define MXC_F_UART_INT_FL_BREAK                                                \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_UART_INT_FL_BREAK_POS)) /**< INT_FL_BREAK Mask */
+#define MXC_F_UART_INT_FL_BREAK                                              \
+	((uint32_t)(0x1UL << MXC_F_UART_INT_FL_BREAK_POS)) /**< INT_FL_BREAK \
+							      Mask */
 
 #define MXC_F_UART_INT_FL_RX_TIMEOUT_POS 8 /**< INT_FL_RX_TIMEOUT Position */
 #define MXC_F_UART_INT_FL_RX_TIMEOUT                                           \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_INT_FL_RX_TIMEOUT_POS)) /**< INT_FL_RX_TIMEOUT   \
-							 Mask */
+	((uint32_t)(0x1UL                                                      \
+		    << MXC_F_UART_INT_FL_RX_TIMEOUT_POS)) /**<                 \
+							     INT_FL_RX_TIMEOUT \
+							     Mask */
 
 #define MXC_F_UART_INT_FL_LAST_BREAK_POS 9 /**< INT_FL_LAST_BREAK Position */
 #define MXC_F_UART_INT_FL_LAST_BREAK                                           \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_UART_INT_FL_LAST_BREAK_POS)) /**< INT_FL_LAST_BREAK   \
-							 Mask */
+	((uint32_t)(0x1UL                                                      \
+		    << MXC_F_UART_INT_FL_LAST_BREAK_POS)) /**<                 \
+							     INT_FL_LAST_BREAK \
+							     Mask */
 
 /**
  * Baud rate register. Integer portion.
  */
 #define MXC_F_UART_BAUD0_IBAUD_POS 0 /**< BAUD0_IBAUD Position */
-#define MXC_F_UART_BAUD0_IBAUD                                                 \
-	((uint32_t)(0xFFFUL                                                    \
-		    << MXC_F_UART_BAUD0_IBAUD_POS)) /**< BAUD0_IBAUD Mask */
+#define MXC_F_UART_BAUD0_IBAUD                                               \
+	((uint32_t)(0xFFFUL << MXC_F_UART_BAUD0_IBAUD_POS)) /**< BAUD0_IBAUD \
+							       Mask */
 
 #define MXC_F_UART_BAUD0_FACTOR_POS 16 /**< BAUD0_FACTOR Position */
-#define MXC_F_UART_BAUD0_FACTOR                                                \
-	((uint32_t)(0x3UL                                                      \
-		    << MXC_F_UART_BAUD0_FACTOR_POS)) /**< BAUD0_FACTOR Mask */
-#define MXC_V_UART_BAUD0_FACTOR_128                                            \
+#define MXC_F_UART_BAUD0_FACTOR                                              \
+	((uint32_t)(0x3UL << MXC_F_UART_BAUD0_FACTOR_POS)) /**< BAUD0_FACTOR \
+							      Mask */
+#define MXC_V_UART_BAUD0_FACTOR_128 \
 	((uint32_t)0x0UL) /**< BAUD0_FACTOR_128 Value */
-#define MXC_S_UART_BAUD0_FACTOR_128                                            \
-	(MXC_V_UART_BAUD0_FACTOR_128                                           \
-	 << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_128 Setting */
-#define MXC_V_UART_BAUD0_FACTOR_64                                             \
+#define MXC_S_UART_BAUD0_FACTOR_128                          \
+	(MXC_V_UART_BAUD0_FACTOR_128                         \
+	 << MXC_F_UART_BAUD0_FACTOR_POS) /**<                \
+					    BAUD0_FACTOR_128 \
+					    Setting          \
+					  */
+#define MXC_V_UART_BAUD0_FACTOR_64 \
 	((uint32_t)0x1UL) /**< BAUD0_FACTOR_64 Value */
-#define MXC_S_UART_BAUD0_FACTOR_64                                             \
-	(MXC_V_UART_BAUD0_FACTOR_64                                            \
-	 << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_64 Setting */
-#define MXC_V_UART_BAUD0_FACTOR_32                                             \
+#define MXC_S_UART_BAUD0_FACTOR_64                          \
+	(MXC_V_UART_BAUD0_FACTOR_64                         \
+	 << MXC_F_UART_BAUD0_FACTOR_POS) /**<               \
+					    BAUD0_FACTOR_64 \
+					    Setting         \
+					  */
+#define MXC_V_UART_BAUD0_FACTOR_32 \
 	((uint32_t)0x2UL) /**< BAUD0_FACTOR_32 Value */
-#define MXC_S_UART_BAUD0_FACTOR_32                                             \
-	(MXC_V_UART_BAUD0_FACTOR_32                                            \
-	 << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_32 Setting */
-#define MXC_V_UART_BAUD0_FACTOR_16                                             \
+#define MXC_S_UART_BAUD0_FACTOR_32                          \
+	(MXC_V_UART_BAUD0_FACTOR_32                         \
+	 << MXC_F_UART_BAUD0_FACTOR_POS) /**<               \
+					    BAUD0_FACTOR_32 \
+					    Setting         \
+					  */
+#define MXC_V_UART_BAUD0_FACTOR_16 \
 	((uint32_t)0x3UL) /**< BAUD0_FACTOR_16 Value */
-#define MXC_S_UART_BAUD0_FACTOR_16                                             \
-	(MXC_V_UART_BAUD0_FACTOR_16                                            \
-	 << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_16 Setting */
+#define MXC_S_UART_BAUD0_FACTOR_16                          \
+	(MXC_V_UART_BAUD0_FACTOR_16                         \
+	 << MXC_F_UART_BAUD0_FACTOR_POS) /**<               \
+					    BAUD0_FACTOR_16 \
+					    Setting         \
+					  */
 
 /**
  * Baud rate register. Decimal Setting.
  */
 #define MXC_F_UART_BAUD1_DBAUD_POS 0 /**< BAUD1_DBAUD Position */
-#define MXC_F_UART_BAUD1_DBAUD                                                 \
-	((uint32_t)(0xFFFUL                                                    \
-		    << MXC_F_UART_BAUD1_DBAUD_POS)) /**< BAUD1_DBAUD Mask */
+#define MXC_F_UART_BAUD1_DBAUD                                               \
+	((uint32_t)(0xFFFUL << MXC_F_UART_BAUD1_DBAUD_POS)) /**< BAUD1_DBAUD \
+							       Mask */
 
 /**
  * FIFO Data buffer.
  */
 #define MXC_F_UART_FIFO_FIFO_POS 0 /**< FIFO_FIFO Position */
-#define MXC_F_UART_FIFO_FIFO                                                   \
-	((uint32_t)(0xFFUL << MXC_F_UART_FIFO_FIFO_POS)) /**< FIFO_FIFO Mask   \
+#define MXC_F_UART_FIFO_FIFO                                                 \
+	((uint32_t)(0xFFUL << MXC_F_UART_FIFO_FIFO_POS)) /**< FIFO_FIFO Mask \
 							  */
 
-
 /**
  * DMA Configuration.
  */
 #define MXC_F_UART_DMA_TDMA_EN_POS 0 /**< DMA_TDMA_EN Position */
-#define MXC_F_UART_DMA_TDMA_EN                                                 \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_UART_DMA_TDMA_EN_POS)) /**< DMA_TDMA_EN Mask */
-#define MXC_V_UART_DMA_TDMA_EN_DIS                                             \
+#define MXC_F_UART_DMA_TDMA_EN                                             \
+	((uint32_t)(0x1UL << MXC_F_UART_DMA_TDMA_EN_POS)) /**< DMA_TDMA_EN \
+							     Mask */
+#define MXC_V_UART_DMA_TDMA_EN_DIS \
 	((uint32_t)0x0UL) /**< DMA_TDMA_EN_DIS Value */
-#define MXC_S_UART_DMA_TDMA_EN_DIS                                             \
-	(MXC_V_UART_DMA_TDMA_EN_DIS                                            \
-	 << MXC_F_UART_DMA_TDMA_EN_POS) /**< DMA_TDMA_EN_DIS Setting */
-#define MXC_V_UART_DMA_TDMA_EN_EN                                              \
-	((uint32_t)0x1UL) /**< DMA_TDMA_EN_EN Value                            \
+#define MXC_S_UART_DMA_TDMA_EN_DIS                         \
+	(MXC_V_UART_DMA_TDMA_EN_DIS                        \
+	 << MXC_F_UART_DMA_TDMA_EN_POS) /**<               \
+					   DMA_TDMA_EN_DIS \
+					   Setting         \
+					 */
+#define MXC_V_UART_DMA_TDMA_EN_EN                   \
+	((uint32_t)0x1UL) /**< DMA_TDMA_EN_EN Value \
 			   */
-#define MXC_S_UART_DMA_TDMA_EN_EN                                              \
-	(MXC_V_UART_DMA_TDMA_EN_EN                                             \
-	 << MXC_F_UART_DMA_TDMA_EN_POS) /**< DMA_TDMA_EN_EN Setting */
+#define MXC_S_UART_DMA_TDMA_EN_EN                         \
+	(MXC_V_UART_DMA_TDMA_EN_EN                        \
+	 << MXC_F_UART_DMA_TDMA_EN_POS) /**<              \
+					   DMA_TDMA_EN_EN \
+					   Setting        \
+					 */
 
 #define MXC_F_UART_DMA_RXDMA_EN_POS 1 /**< DMA_RXDMA_EN Position */
-#define MXC_F_UART_DMA_RXDMA_EN                                                \
-	((uint32_t)(0x1UL                                                      \
-		    << MXC_F_UART_DMA_RXDMA_EN_POS)) /**< DMA_RXDMA_EN Mask */
-#define MXC_V_UART_DMA_RXDMA_EN_DIS                                            \
+#define MXC_F_UART_DMA_RXDMA_EN                                              \
+	((uint32_t)(0x1UL << MXC_F_UART_DMA_RXDMA_EN_POS)) /**< DMA_RXDMA_EN \
+							      Mask */
+#define MXC_V_UART_DMA_RXDMA_EN_DIS \
 	((uint32_t)0x0UL) /**< DMA_RXDMA_EN_DIS Value */
-#define MXC_S_UART_DMA_RXDMA_EN_DIS                                            \
-	(MXC_V_UART_DMA_RXDMA_EN_DIS                                           \
-	 << MXC_F_UART_DMA_RXDMA_EN_POS) /**< DMA_RXDMA_EN_DIS Setting */
-#define MXC_V_UART_DMA_RXDMA_EN_EN                                             \
+#define MXC_S_UART_DMA_RXDMA_EN_DIS                          \
+	(MXC_V_UART_DMA_RXDMA_EN_DIS                         \
+	 << MXC_F_UART_DMA_RXDMA_EN_POS) /**<                \
+					    DMA_RXDMA_EN_DIS \
+					    Setting          \
+					  */
+#define MXC_V_UART_DMA_RXDMA_EN_EN \
 	((uint32_t)0x1UL) /**< DMA_RXDMA_EN_EN Value */
-#define MXC_S_UART_DMA_RXDMA_EN_EN                                             \
-	(MXC_V_UART_DMA_RXDMA_EN_EN                                            \
-	 << MXC_F_UART_DMA_RXDMA_EN_POS) /**< DMA_RXDMA_EN_EN Setting */
+#define MXC_S_UART_DMA_RXDMA_EN_EN                          \
+	(MXC_V_UART_DMA_RXDMA_EN_EN                         \
+	 << MXC_F_UART_DMA_RXDMA_EN_POS) /**<               \
+					    DMA_RXDMA_EN_EN \
+					    Setting         \
+					  */
 
 #define MXC_F_UART_DMA_TXDMA_LEVEL_POS 8 /**< DMA_TXDMA_LEVEL Position */
-#define MXC_F_UART_DMA_TXDMA_LEVEL                                             \
-	((uint32_t)(0x3FUL                                                     \
-		    << MXC_F_UART_DMA_TXDMA_LEVEL_POS)) /**< DMA_TXDMA_LEVEL   \
+#define MXC_F_UART_DMA_TXDMA_LEVEL                                           \
+	((uint32_t)(0x3FUL                                                   \
+		    << MXC_F_UART_DMA_TXDMA_LEVEL_POS)) /**< DMA_TXDMA_LEVEL \
 							   Mask */
 
 #define MXC_F_UART_DMA_RXDMA_LEVEL_POS 16 /**< DMA_RXDMA_LEVEL Position */
-#define MXC_F_UART_DMA_RXDMA_LEVEL                                             \
-	((uint32_t)(0x3FUL                                                     \
-		    << MXC_F_UART_DMA_RXDMA_LEVEL_POS)) /**< DMA_RXDMA_LEVEL   \
+#define MXC_F_UART_DMA_RXDMA_LEVEL                                           \
+	((uint32_t)(0x3FUL                                                   \
+		    << MXC_F_UART_DMA_RXDMA_LEVEL_POS)) /**< DMA_RXDMA_LEVEL \
 							   Mask */
 
 /**
  * Transmit FIFO Status register.
  */
 #define MXC_F_UART_TX_FIFO_DATA_POS 0 /**< TX_FIFO_DATA Position */
-#define MXC_F_UART_TX_FIFO_DATA                                                \
-	((uint32_t)(0x7FUL                                                     \
-		    << MXC_F_UART_TX_FIFO_DATA_POS)) /**< TX_FIFO_DATA Mask */
+#define MXC_F_UART_TX_FIFO_DATA                                               \
+	((uint32_t)(0x7FUL << MXC_F_UART_TX_FIFO_DATA_POS)) /**< TX_FIFO_DATA \
+							       Mask */
 
 #endif /* _UART_REGS_H_ */
diff --git a/chip/max32660/wdt_chip.c b/chip/max32660/wdt_chip.c
index 1c99c798fc..03cd2bd009 100644
--- a/chip/max32660/wdt_chip.c
+++ b/chip/max32660/wdt_chip.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,7 +20,7 @@
 #define CPUTS(outstr) cputs(CC_COMMAND, outstr)
 #define CPRINTS(format, args...) cprints(CC_COMMAND, format, ##args)
 
-/* For a System clock of 96MHz, 
+/* For a System clock of 96MHz,
  *     Time in seconds = 96000000 / 2 * 2^power
  * Example for MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW29
  *     Time in seconds = 96000000 / 2 * 2^29
@@ -56,7 +56,7 @@ int watchdog_init(void)
 	return EC_SUCCESS;
 }
 
-static int command_watchdog_test(int argc, char **argv)
+static int command_watchdog_test(int argc, const char **argv)
 {
 	starve_dog = 1;
 
diff --git a/chip/max32660/wdt_regs.h b/chip/max32660/wdt_regs.h
index 32d6fe0925..440e8e8b0d 100644
--- a/chip/max32660/wdt_regs.h
+++ b/chip/max32660/wdt_regs.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -31,325 +31,347 @@
  */
 typedef struct {
 	__IO uint32_t ctrl; /**< <tt>\b 0x00:<\tt> WDT CTRL Register */
-	__O uint32_t rst;   /**< <tt>\b 0x04:<\tt> WDT RST Register */
+	__O uint32_t rst; /**< <tt>\b 0x04:<\tt> WDT RST Register */
 } mxc_wdt_regs_t;
 
 /**
  * WDT Peripheral Register Offsets from the WDT Base Peripheral
  * Address.
  */
-#define MXC_R_WDT_CTRL                                                         \
-	((uint32_t)0x00000000UL) /**< Offset from WDT Base Address: <tt>       \
+#define MXC_R_WDT_CTRL                                                   \
+	((uint32_t)0x00000000UL) /**< Offset from WDT Base Address: <tt> \
 				    0x0x000 */
-#define MXC_R_WDT_RST                                                          \
-	((uint32_t)0x00000004UL) /**< Offset from WDT Base Address: <tt>       \
+#define MXC_R_WDT_RST                                                    \
+	((uint32_t)0x00000004UL) /**< Offset from WDT Base Address: <tt> \
 				    0x0x004 */
 
 /**
  * Watchdog Timer Control Register.
  */
 #define MXC_F_WDT_CTRL_INT_PERIOD_POS 0 /**< CTRL_INT_PERIOD Position */
-#define MXC_F_WDT_CTRL_INT_PERIOD                                              \
-	((uint32_t)(                                                           \
-		0xFUL << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< CTRL_INT_PERIOD  \
-							    Mask */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW31                                    \
+#define MXC_F_WDT_CTRL_INT_PERIOD                                           \
+	((uint32_t)(0xFUL                                                   \
+		    << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< CTRL_INT_PERIOD \
+							  Mask */
+#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW31 \
 	((uint32_t)0x0UL) /**< CTRL_INT_PERIOD_WDT2POW31 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW31                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW31                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW31      \
+#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW31                               \
+	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW31                              \
+	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW31 \
 					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW30                                    \
+#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW30 \
 	((uint32_t)0x1UL) /**< CTRL_INT_PERIOD_WDT2POW30 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW30                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW30                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW30      \
+#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW30                               \
+	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW30                              \
+	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW30 \
 					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW29                                    \
+#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW29 \
 	((uint32_t)0x2UL) /**< CTRL_INT_PERIOD_WDT2POW29 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW29                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW29                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW29      \
+#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW29                               \
+	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW29                              \
+	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW29 \
 					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW28                                    \
+#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW28 \
 	((uint32_t)0x3UL) /**< CTRL_INT_PERIOD_WDT2POW28 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW28                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW28                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW28      \
+#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW28                               \
+	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW28                              \
+	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW28 \
 					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW27                                    \
+#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW27 \
 	((uint32_t)0x4UL) /**< CTRL_INT_PERIOD_WDT2POW27 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW27                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW27                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW27      \
+#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW27                               \
+	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW27                              \
+	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW27 \
 					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW26                                    \
+#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW26 \
 	((uint32_t)0x5UL) /**< CTRL_INT_PERIOD_WDT2POW26 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW26                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW26                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW26      \
+#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW26                               \
+	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW26                              \
+	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW26 \
 					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW25                                    \
+#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW25 \
 	((uint32_t)0x6UL) /**< CTRL_INT_PERIOD_WDT2POW25 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW25                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW25                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW25      \
+#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW25                               \
+	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW25                              \
+	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW25 \
 					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW24                                    \
+#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW24 \
 	((uint32_t)0x7UL) /**< CTRL_INT_PERIOD_WDT2POW24 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW24                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW24                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW24      \
+#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW24                               \
+	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW24                              \
+	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW24 \
 					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW23                                    \
+#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW23 \
 	((uint32_t)0x8UL) /**< CTRL_INT_PERIOD_WDT2POW23 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW23                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW23                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW23      \
+#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW23                               \
+	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW23                              \
+	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW23 \
 					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW22                                    \
+#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW22 \
 	((uint32_t)0x9UL) /**< CTRL_INT_PERIOD_WDT2POW22 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW22                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW22                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW22      \
+#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW22                               \
+	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW22                              \
+	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW22 \
 					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW21                                    \
+#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW21 \
 	((uint32_t)0xAUL) /**< CTRL_INT_PERIOD_WDT2POW21 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW21                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW21                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW21      \
+#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW21                               \
+	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW21                              \
+	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW21 \
 					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW20                                    \
+#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW20 \
 	((uint32_t)0xBUL) /**< CTRL_INT_PERIOD_WDT2POW20 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW20                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW20                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW20      \
+#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW20                               \
+	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW20                              \
+	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW20 \
 					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW19                                    \
+#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW19 \
 	((uint32_t)0xCUL) /**< CTRL_INT_PERIOD_WDT2POW19 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW19                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW19                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW19      \
+#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW19                               \
+	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW19                              \
+	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW19 \
 					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW18                                    \
+#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW18 \
 	((uint32_t)0xDUL) /**< CTRL_INT_PERIOD_WDT2POW18 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW18                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW18                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW18      \
+#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW18                               \
+	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW18                              \
+	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW18 \
 					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW17                                    \
+#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW17 \
 	((uint32_t)0xEUL) /**< CTRL_INT_PERIOD_WDT2POW17 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW17                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW17                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW17      \
+#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW17                               \
+	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW17                              \
+	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW17 \
 					      Setting */
-#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW16                                    \
+#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW16 \
 	((uint32_t)0xFUL) /**< CTRL_INT_PERIOD_WDT2POW16 Value */
-#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW16                                    \
-	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW16                                   \
-	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW16      \
+#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW16                               \
+	(MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW16                              \
+	 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW16 \
 					      Setting */
 
 #define MXC_F_WDT_CTRL_RST_PERIOD_POS 4 /**< CTRL_RST_PERIOD Position */
-#define MXC_F_WDT_CTRL_RST_PERIOD                                              \
-	((uint32_t)(                                                           \
-		0xFUL << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< CTRL_RST_PERIOD  \
-							    Mask */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW31                                    \
+#define MXC_F_WDT_CTRL_RST_PERIOD                                           \
+	((uint32_t)(0xFUL                                                   \
+		    << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< CTRL_RST_PERIOD \
+							  Mask */
+#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW31 \
 	((uint32_t)0x0UL) /**< CTRL_RST_PERIOD_WDT2POW31 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW31                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW31                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW31      \
+#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW31                               \
+	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW31                              \
+	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW31 \
 					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW30                                    \
+#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW30 \
 	((uint32_t)0x1UL) /**< CTRL_RST_PERIOD_WDT2POW30 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW30                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW30                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW30      \
+#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW30                               \
+	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW30                              \
+	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW30 \
 					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW29                                    \
+#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW29 \
 	((uint32_t)0x2UL) /**< CTRL_RST_PERIOD_WDT2POW29 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW29                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW29                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW29      \
+#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW29                               \
+	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW29                              \
+	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW29 \
 					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW28                                    \
+#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW28 \
 	((uint32_t)0x3UL) /**< CTRL_RST_PERIOD_WDT2POW28 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW28                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW28                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW28      \
+#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW28                               \
+	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW28                              \
+	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW28 \
 					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW27                                    \
+#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW27 \
 	((uint32_t)0x4UL) /**< CTRL_RST_PERIOD_WDT2POW27 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW27                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW27                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW27      \
+#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW27                               \
+	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW27                              \
+	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW27 \
 					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW26                                    \
+#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW26 \
 	((uint32_t)0x5UL) /**< CTRL_RST_PERIOD_WDT2POW26 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW26                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW26                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW26      \
+#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW26                               \
+	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW26                              \
+	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW26 \
 					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW25                                    \
+#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW25 \
 	((uint32_t)0x6UL) /**< CTRL_RST_PERIOD_WDT2POW25 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW25                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW25                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW25      \
+#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW25                               \
+	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW25                              \
+	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW25 \
 					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW24                                    \
+#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW24 \
 	((uint32_t)0x7UL) /**< CTRL_RST_PERIOD_WDT2POW24 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW24                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW24                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW24      \
+#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW24                               \
+	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW24                              \
+	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW24 \
 					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW23                                    \
+#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW23 \
 	((uint32_t)0x8UL) /**< CTRL_RST_PERIOD_WDT2POW23 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW23                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW23                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW23      \
+#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW23                               \
+	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW23                              \
+	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW23 \
 					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW22                                    \
+#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW22 \
 	((uint32_t)0x9UL) /**< CTRL_RST_PERIOD_WDT2POW22 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW22                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW22                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW22      \
+#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW22                               \
+	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW22                              \
+	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW22 \
 					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW21                                    \
+#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW21 \
 	((uint32_t)0xAUL) /**< CTRL_RST_PERIOD_WDT2POW21 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW21                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW21                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW21      \
+#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW21                               \
+	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW21                              \
+	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW21 \
 					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW20                                    \
+#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW20 \
 	((uint32_t)0xBUL) /**< CTRL_RST_PERIOD_WDT2POW20 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW20                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW20                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW20      \
+#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW20                               \
+	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW20                              \
+	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW20 \
 					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW19                                    \
+#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW19 \
 	((uint32_t)0xCUL) /**< CTRL_RST_PERIOD_WDT2POW19 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW19                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW19                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW19      \
+#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW19                               \
+	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW19                              \
+	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW19 \
 					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW18                                    \
+#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW18 \
 	((uint32_t)0xDUL) /**< CTRL_RST_PERIOD_WDT2POW18 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW18                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW18                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW18      \
+#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW18                               \
+	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW18                              \
+	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW18 \
 					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW17                                    \
+#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW17 \
 	((uint32_t)0xEUL) /**< CTRL_RST_PERIOD_WDT2POW17 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW17                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW17                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW17      \
+#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW17                               \
+	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW17                              \
+	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW17 \
 					      Setting */
-#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW16                                    \
+#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW16 \
 	((uint32_t)0xFUL) /**< CTRL_RST_PERIOD_WDT2POW16 Value */
-#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW16                                    \
-	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW16                                   \
-	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW16      \
+#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW16                               \
+	(MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW16                              \
+	 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW16 \
 					      Setting */
 
 #define MXC_F_WDT_CTRL_WDT_EN_POS 8 /**< CTRL_WDT_EN Position */
 #define MXC_F_WDT_CTRL_WDT_EN                                                  \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_WDT_CTRL_WDT_EN_POS)) /**< CTRL_WDT_EN Mask */
-#define MXC_V_WDT_CTRL_WDT_EN_DIS                                              \
+	((uint32_t)(0x1UL << MXC_F_WDT_CTRL_WDT_EN_POS)) /**< CTRL_WDT_EN Mask \
+							  */
+#define MXC_V_WDT_CTRL_WDT_EN_DIS \
 	((uint32_t)0x0UL) /**< CTRL_WDT_EN_DIS Value */
-#define MXC_S_WDT_CTRL_WDT_EN_DIS                                              \
-	(MXC_V_WDT_CTRL_WDT_EN_DIS                                             \
-	 << MXC_F_WDT_CTRL_WDT_EN_POS) /**< CTRL_WDT_EN_DIS Setting */
-#define MXC_V_WDT_CTRL_WDT_EN_EN                                               \
-	((uint32_t)0x1UL) /**< CTRL_WDT_EN_EN Value                            \
+#define MXC_S_WDT_CTRL_WDT_EN_DIS                         \
+	(MXC_V_WDT_CTRL_WDT_EN_DIS                        \
+	 << MXC_F_WDT_CTRL_WDT_EN_POS) /**<               \
+					  CTRL_WDT_EN_DIS \
+					  Setting */
+#define MXC_V_WDT_CTRL_WDT_EN_EN                    \
+	((uint32_t)0x1UL) /**< CTRL_WDT_EN_EN Value \
 			   */
-#define MXC_S_WDT_CTRL_WDT_EN_EN                                               \
-	(MXC_V_WDT_CTRL_WDT_EN_EN                                              \
-	 << MXC_F_WDT_CTRL_WDT_EN_POS) /**< CTRL_WDT_EN_EN Setting */
+#define MXC_S_WDT_CTRL_WDT_EN_EN                         \
+	(MXC_V_WDT_CTRL_WDT_EN_EN                        \
+	 << MXC_F_WDT_CTRL_WDT_EN_POS) /**<              \
+					  CTRL_WDT_EN_EN \
+					  Setting */
 
 #define MXC_F_WDT_CTRL_INT_FLAG_POS 9 /**< CTRL_INT_FLAG Position */
-#define MXC_F_WDT_CTRL_INT_FLAG                                                \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_WDT_CTRL_INT_FLAG_POS)) /**< CTRL_INT_FLAG Mask */
-#define MXC_V_WDT_CTRL_INT_FLAG_INACTIVE                                       \
+#define MXC_F_WDT_CTRL_INT_FLAG                                               \
+	((uint32_t)(0x1UL << MXC_F_WDT_CTRL_INT_FLAG_POS)) /**< CTRL_INT_FLAG \
+							      Mask */
+#define MXC_V_WDT_CTRL_INT_FLAG_INACTIVE \
 	((uint32_t)0x0UL) /**< CTRL_INT_FLAG_INACTIVE Value */
-#define MXC_S_WDT_CTRL_INT_FLAG_INACTIVE                                       \
-	(MXC_V_WDT_CTRL_INT_FLAG_INACTIVE                                      \
-	 << MXC_F_WDT_CTRL_INT_FLAG_POS) /**< CTRL_INT_FLAG_INACTIVE Setting   \
+#define MXC_S_WDT_CTRL_INT_FLAG_INACTIVE                                     \
+	(MXC_V_WDT_CTRL_INT_FLAG_INACTIVE                                    \
+	 << MXC_F_WDT_CTRL_INT_FLAG_POS) /**< CTRL_INT_FLAG_INACTIVE Setting \
 					  */
-#define MXC_V_WDT_CTRL_INT_FLAG_PENDING                                        \
+#define MXC_V_WDT_CTRL_INT_FLAG_PENDING \
 	((uint32_t)0x1UL) /**< CTRL_INT_FLAG_PENDING Value */
-#define MXC_S_WDT_CTRL_INT_FLAG_PENDING                                        \
-	(MXC_V_WDT_CTRL_INT_FLAG_PENDING                                       \
-	 << MXC_F_WDT_CTRL_INT_FLAG_POS) /**< CTRL_INT_FLAG_PENDING Setting */
+#define MXC_S_WDT_CTRL_INT_FLAG_PENDING                           \
+	(MXC_V_WDT_CTRL_INT_FLAG_PENDING                          \
+	 << MXC_F_WDT_CTRL_INT_FLAG_POS) /**<                     \
+					    CTRL_INT_FLAG_PENDING \
+					    Setting               \
+					  */
 
 #define MXC_F_WDT_CTRL_INT_EN_POS 10 /**< CTRL_INT_EN Position */
 #define MXC_F_WDT_CTRL_INT_EN                                                  \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_WDT_CTRL_INT_EN_POS)) /**< CTRL_INT_EN Mask */
-#define MXC_V_WDT_CTRL_INT_EN_DIS                                              \
+	((uint32_t)(0x1UL << MXC_F_WDT_CTRL_INT_EN_POS)) /**< CTRL_INT_EN Mask \
+							  */
+#define MXC_V_WDT_CTRL_INT_EN_DIS \
 	((uint32_t)0x0UL) /**< CTRL_INT_EN_DIS Value */
-#define MXC_S_WDT_CTRL_INT_EN_DIS                                              \
-	(MXC_V_WDT_CTRL_INT_EN_DIS                                             \
-	 << MXC_F_WDT_CTRL_INT_EN_POS) /**< CTRL_INT_EN_DIS Setting */
-#define MXC_V_WDT_CTRL_INT_EN_EN                                               \
-	((uint32_t)0x1UL) /**< CTRL_INT_EN_EN Value                            \
+#define MXC_S_WDT_CTRL_INT_EN_DIS                         \
+	(MXC_V_WDT_CTRL_INT_EN_DIS                        \
+	 << MXC_F_WDT_CTRL_INT_EN_POS) /**<               \
+					  CTRL_INT_EN_DIS \
+					  Setting */
+#define MXC_V_WDT_CTRL_INT_EN_EN                    \
+	((uint32_t)0x1UL) /**< CTRL_INT_EN_EN Value \
 			   */
-#define MXC_S_WDT_CTRL_INT_EN_EN                                               \
-	(MXC_V_WDT_CTRL_INT_EN_EN                                              \
-	 << MXC_F_WDT_CTRL_INT_EN_POS) /**< CTRL_INT_EN_EN Setting */
+#define MXC_S_WDT_CTRL_INT_EN_EN                         \
+	(MXC_V_WDT_CTRL_INT_EN_EN                        \
+	 << MXC_F_WDT_CTRL_INT_EN_POS) /**<              \
+					  CTRL_INT_EN_EN \
+					  Setting */
 
 #define MXC_F_WDT_CTRL_RST_EN_POS 11 /**< CTRL_RST_EN Position */
 #define MXC_F_WDT_CTRL_RST_EN                                                  \
-	((uint32_t)(                                                           \
-		0x1UL << MXC_F_WDT_CTRL_RST_EN_POS)) /**< CTRL_RST_EN Mask */
-#define MXC_V_WDT_CTRL_RST_EN_DIS                                              \
+	((uint32_t)(0x1UL << MXC_F_WDT_CTRL_RST_EN_POS)) /**< CTRL_RST_EN Mask \
+							  */
+#define MXC_V_WDT_CTRL_RST_EN_DIS \
 	((uint32_t)0x0UL) /**< CTRL_RST_EN_DIS Value */
-#define MXC_S_WDT_CTRL_RST_EN_DIS                                              \
-	(MXC_V_WDT_CTRL_RST_EN_DIS                                             \
-	 << MXC_F_WDT_CTRL_RST_EN_POS) /**< CTRL_RST_EN_DIS Setting */
-#define MXC_V_WDT_CTRL_RST_EN_EN                                               \
-	((uint32_t)0x1UL) /**< CTRL_RST_EN_EN Value                            \
+#define MXC_S_WDT_CTRL_RST_EN_DIS                         \
+	(MXC_V_WDT_CTRL_RST_EN_DIS                        \
+	 << MXC_F_WDT_CTRL_RST_EN_POS) /**<               \
+					  CTRL_RST_EN_DIS \
+					  Setting */
+#define MXC_V_WDT_CTRL_RST_EN_EN                    \
+	((uint32_t)0x1UL) /**< CTRL_RST_EN_EN Value \
 			   */
-#define MXC_S_WDT_CTRL_RST_EN_EN                                               \
-	(MXC_V_WDT_CTRL_RST_EN_EN                                              \
-	 << MXC_F_WDT_CTRL_RST_EN_POS) /**< CTRL_RST_EN_EN Setting */
+#define MXC_S_WDT_CTRL_RST_EN_EN                         \
+	(MXC_V_WDT_CTRL_RST_EN_EN                        \
+	 << MXC_F_WDT_CTRL_RST_EN_POS) /**<              \
+					  CTRL_RST_EN_EN \
+					  Setting */
 
 #define MXC_F_WDT_CTRL_RST_FLAG_POS 31 /**< CTRL_RST_FLAG Position */
-#define MXC_F_WDT_CTRL_RST_FLAG                                                \
-	((uint32_t)(                                                           \
-		0x1UL                                                          \
-		<< MXC_F_WDT_CTRL_RST_FLAG_POS)) /**< CTRL_RST_FLAG Mask */
-#define MXC_V_WDT_CTRL_RST_FLAG_NOEVENT                                        \
+#define MXC_F_WDT_CTRL_RST_FLAG                                               \
+	((uint32_t)(0x1UL << MXC_F_WDT_CTRL_RST_FLAG_POS)) /**< CTRL_RST_FLAG \
+							      Mask */
+#define MXC_V_WDT_CTRL_RST_FLAG_NOEVENT \
 	((uint32_t)0x0UL) /**< CTRL_RST_FLAG_NOEVENT Value */
-#define MXC_S_WDT_CTRL_RST_FLAG_NOEVENT                                        \
-	(MXC_V_WDT_CTRL_RST_FLAG_NOEVENT                                       \
-	 << MXC_F_WDT_CTRL_RST_FLAG_POS) /**< CTRL_RST_FLAG_NOEVENT Setting */
-#define MXC_V_WDT_CTRL_RST_FLAG_OCCURRED                                       \
+#define MXC_S_WDT_CTRL_RST_FLAG_NOEVENT                           \
+	(MXC_V_WDT_CTRL_RST_FLAG_NOEVENT                          \
+	 << MXC_F_WDT_CTRL_RST_FLAG_POS) /**<                     \
+					    CTRL_RST_FLAG_NOEVENT \
+					    Setting               \
+					  */
+#define MXC_V_WDT_CTRL_RST_FLAG_OCCURRED \
 	((uint32_t)0x1UL) /**< CTRL_RST_FLAG_OCCURRED Value */
-#define MXC_S_WDT_CTRL_RST_FLAG_OCCURRED                                       \
-	(MXC_V_WDT_CTRL_RST_FLAG_OCCURRED                                      \
-	 << MXC_F_WDT_CTRL_RST_FLAG_POS) /**< CTRL_RST_FLAG_OCCURRED Setting   \
+#define MXC_S_WDT_CTRL_RST_FLAG_OCCURRED                                     \
+	(MXC_V_WDT_CTRL_RST_FLAG_OCCURRED                                    \
+	 << MXC_F_WDT_CTRL_RST_FLAG_POS) /**< CTRL_RST_FLAG_OCCURRED Setting \
 					  */
 
 /**
  * Watchdog Timer Reset Register.
  */
 #define MXC_F_WDT_RST_WDT_RST_POS 0 /**< RST_WDT_RST Position */
-#define MXC_F_WDT_RST_WDT_RST                                                  \
-	((uint32_t)(                                                           \
-		0xFFUL << MXC_F_WDT_RST_WDT_RST_POS)) /**< RST_WDT_RST Mask */
-#define MXC_V_WDT_RST_WDT_RST_SEQ0                                             \
+#define MXC_F_WDT_RST_WDT_RST                                              \
+	((uint32_t)(0xFFUL << MXC_F_WDT_RST_WDT_RST_POS)) /**< RST_WDT_RST \
+							     Mask */
+#define MXC_V_WDT_RST_WDT_RST_SEQ0 \
 	((uint32_t)0xA5UL) /**< RST_WDT_RST_SEQ0 Value */
-#define MXC_S_WDT_RST_WDT_RST_SEQ0                                             \
-	(MXC_V_WDT_RST_WDT_RST_SEQ0                                            \
-	 << MXC_F_WDT_RST_WDT_RST_POS) /**< RST_WDT_RST_SEQ0 Setting */
-#define MXC_V_WDT_RST_WDT_RST_SEQ1                                             \
+#define MXC_S_WDT_RST_WDT_RST_SEQ0                         \
+	(MXC_V_WDT_RST_WDT_RST_SEQ0                        \
+	 << MXC_F_WDT_RST_WDT_RST_POS) /**<                \
+					  RST_WDT_RST_SEQ0 \
+					  Setting          \
+					*/
+#define MXC_V_WDT_RST_WDT_RST_SEQ1 \
 	((uint32_t)0x5AUL) /**< RST_WDT_RST_SEQ1 Value */
-#define MXC_S_WDT_RST_WDT_RST_SEQ1                                             \
-	(MXC_V_WDT_RST_WDT_RST_SEQ1                                            \
-	 << MXC_F_WDT_RST_WDT_RST_POS) /**< RST_WDT_RST_SEQ1 Setting */
+#define MXC_S_WDT_RST_WDT_RST_SEQ1                         \
+	(MXC_V_WDT_RST_WDT_RST_SEQ1                        \
+	 << MXC_F_WDT_RST_WDT_RST_POS) /**<                \
+					  RST_WDT_RST_SEQ1 \
+					  Setting          \
+					*/
 
 #endif /* _WDT_REGS_H_ */
diff --git a/chip/mchp/adc.c b/chip/mchp/adc.c
index 9de5476077..621fe1f3be 100644
--- a/chip/mchp/adc.c
+++ b/chip/mchp/adc.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -53,7 +53,7 @@ static int start_single_and_wait(int timeout)
 	/* clear GIRQ single status */
 	MCHP_INT_SOURCE(MCHP_ADC_GIRQ) = MCHP_ADC_GIRQ_SINGLE_BIT;
 	/* make sure all writes are issued before starting conversion */
-	asm volatile ("dsb");
+	asm volatile("dsb");
 
 	/* Start conversion */
 	MCHP_ADC_CTRL |= BIT(1);
@@ -77,7 +77,8 @@ int adc_read_channel(enum adc_channel ch)
 
 	if (start_single_and_wait(ADC_SINGLE_READ_TIME))
 		value = (MCHP_ADC_READ(adc->channel) * adc->factor_mul) /
-			adc->factor_div + adc->shift;
+				adc->factor_div +
+			adc->shift;
 	else
 		value = ADC_READ_ERROR;
 
@@ -105,7 +106,8 @@ int adc_read_all_channels(int *data)
 	for (i = 0; i < ADC_CH_COUNT; ++i) {
 		adc = adc_channels + i;
 		data[i] = (MCHP_ADC_READ(adc->channel) * adc->factor_mul) /
-			  adc->factor_div + adc->shift;
+				  adc->factor_div +
+			  adc->shift;
 	}
 
 exit_all_channels:
diff --git a/chip/mchp/adc_chip.h b/chip/mchp/adc_chip.h
index 0f14d5a459..fa60efa960 100644
--- a/chip/mchp/adc_chip.h
+++ b/chip/mchp/adc_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/mchp/build.mk b/chip/mchp/build.mk
index 1e3de24d06..87e37b91e5 100644
--- a/chip/mchp/build.mk
+++ b/chip/mchp/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
+# Copyright 2013 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -81,9 +81,11 @@ chip-lfw-flat = $(out)/RW/$(chip-lfw)-lfw.flat
 
 # build these specifically for lfw with -lfw suffix
 objs_lfw = $(patsubst %, $(out)/RW/%-lfw.o, \
-		$(addprefix common/, util util_stdlib gpio) \
+		$(addprefix common/, util gpio) \
 		$(addprefix chip/$(CHIP)/, spi qmspi dma gpio clock hwtimer tfdp) \
-		core/$(CORE)/cpu $(chip-lfw))
+		core/$(CORE)/cpu $(chip-lfw) \
+		builtin/stdlib \
+		)
 
 # reuse version.o (and its dependencies) from main board
 objs_lfw += $(out)/RW/common/version.o
diff --git a/chip/mchp/clock.c b/chip/mchp/clock.c
index e646470ac6..4701d43b1f 100644
--- a/chip/mchp/clock.c
+++ b/chip/mchp/clock.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,17 +25,17 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args)
 
 #ifdef CONFIG_LOW_POWER_IDLE
 
-#define HTIMER_DIV_1_US_MAX	(1998848)
-#define HTIMER_DIV_1_1SEC	(0x8012)
+#define HTIMER_DIV_1_US_MAX (1998848)
+#define HTIMER_DIV_1_1SEC (0x8012)
 
 /* Recovery time for HvySlp2 is 0 us */
-#define HEAVY_SLEEP_RECOVER_TIME_USEC   75
+#define HEAVY_SLEEP_RECOVER_TIME_USEC 75
 
-#define SET_HTIMER_DELAY_USEC           200
+#define SET_HTIMER_DELAY_USEC 200
 
 static int idle_sleep_cnt;
 static int idle_dsleep_cnt;
@@ -52,7 +52,7 @@ static uint32_t ecia_result[MCHP_INT_GIRQ_NUM];
  * boot in order to give a permanent window in which the heavy sleep
  * mode is not used.
  */
-#define CONSOLE_IN_USE_ON_BOOT_TIME (15*SECOND)
+#define CONSOLE_IN_USE_ON_BOOT_TIME (15 * SECOND)
 static int console_in_use_timeout_sec = 60;
 static timestamp_t console_expire_time;
 #endif /*CONFIG_LOW_POWER_IDLE */
@@ -62,7 +62,8 @@ static int freq = 48000000;
 void clock_wait_cycles(uint32_t cycles)
 {
 	asm volatile("1: subs %0, #1\n"
-		     "   bne 1b\n" : "+r"(cycles));
+		     "   bne 1b\n"
+		     : "+r"(cycles));
 }
 
 int clock_get_freq(void)
@@ -80,15 +81,13 @@ int clock_get_freq(void)
 /* 32 KHz crystal connected in parallel */
 static inline void config_32k_src_crystal(void)
 {
-	MCHP_VBAT_CSS = MCHP_VBAT_CSS_XTAL_EN
-			| MCHP_VBAT_CSS_SRC_XTAL;
+	MCHP_VBAT_CSS = MCHP_VBAT_CSS_XTAL_EN | MCHP_VBAT_CSS_SRC_XTAL;
 }
 
 /* 32 KHz source is 32KHZ_IN pin which must be configured */
 static inline void config_32k_src_se_input(void)
 {
-	MCHP_VBAT_CSS = MCHP_VBAT_CSS_SIL32K_EN
-				| MCHP_VBAT_CSS_SRC_SWPS;
+	MCHP_VBAT_CSS = MCHP_VBAT_CSS_SIL32K_EN | MCHP_VBAT_CSS_SRC_SWPS;
 }
 
 static inline void config_32k_src_sil_osc(void)
@@ -99,21 +98,21 @@ static inline void config_32k_src_sil_osc(void)
 #else
 static void config_32k_src_crystal(void)
 {
-	MCHP_VBAT_CE = MCHP_VBAT_CE_XOSEL_PAR
-			| MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_CRYSTAL;
+	MCHP_VBAT_CE = MCHP_VBAT_CE_XOSEL_PAR |
+		       MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_CRYSTAL;
 }
 
 /* 32 KHz source is 32KHZ_IN pin which must be configured */
 static inline void config_32k_src_se_input(void)
 {
-	MCHP_VBAT_CE = MCHP_VBAT_CE_32K_DOMAIN_32KHZ_IN_PIN
-			| MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_INT;
+	MCHP_VBAT_CE = MCHP_VBAT_CE_32K_DOMAIN_32KHZ_IN_PIN |
+		       MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_INT;
 }
 
 static inline void config_32k_src_sil_osc(void)
 {
-	MCHP_VBAT_CE = ~(MCHP_VBAT_CE_32K_DOMAIN_32KHZ_IN_PIN
-			| MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_CRYSTAL);
+	MCHP_VBAT_CE = ~(MCHP_VBAT_CE_32K_DOMAIN_32KHZ_IN_PIN |
+			 MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_CRYSTAL);
 }
 #endif
 
@@ -173,9 +172,7 @@ static void clock_turbo_disable(void)
 		/* Use 12 MHz processor clock for power savings */
 		MCHP_PCR_PROC_CLK_CTL = MCHP_PCR_CLK_CTL_12MHZ;
 }
-DECLARE_HOOK(HOOK_INIT,
-		clock_turbo_disable,
-		HOOK_PRIO_INIT_VBOOT_HASH + 1);
+DECLARE_HOOK(HOOK_INIT, clock_turbo_disable, HOOK_PRIO_INIT_VBOOT_HASH + 1);
 
 /**
  * initialization of Hibernation timer 0
@@ -208,8 +205,7 @@ void htimer_init(void)
  * 1 is divide by 4096 for 0.125 s per LSB for a maximum of ~2 hours.
  *	65535 * 0.125 s ~ 8192 s = 2.27 hours
  */
-void system_set_htimer_alarm(uint32_t seconds,
-		uint32_t microseconds)
+void system_set_htimer_alarm(uint32_t seconds, uint32_t microseconds)
 {
 	uint32_t hcnt, ns;
 	uint8_t hctrl;
@@ -226,7 +222,7 @@ void system_set_htimer_alarm(uint32_t seconds,
 	}
 
 	if (seconds > 1) {
-		hcnt = (seconds << 3);	/* divide by 0.125 */
+		hcnt = (seconds << 3); /* divide by 0.125 */
 		if (hcnt > 0xfffful)
 			hcnt = 0xfffful;
 		hctrl = 1;
@@ -236,7 +232,7 @@ void system_set_htimer_alarm(uint32_t seconds,
 		 * seconds / 30.5e-6 + microseconds / 30.5
 		 */
 		hcnt = (seconds << 15) + (microseconds >> 5) +
-			(microseconds >> 10);
+		       (microseconds >> 10);
 		hctrl = 0;
 	}
 
@@ -254,19 +250,18 @@ static timestamp_t system_get_htimer(void)
 	uint16_t count;
 	timestamp_t time;
 
-	count =  MCHP_HTIMER_COUNT(0);
-
+	count = MCHP_HTIMER_COUNT(0);
 
 	if (MCHP_HTIMER_CONTROL(0) == 1) /* if > 2 sec */
 		/* 0.125 sec per count */
 		time.le.lo = (uint32_t)(count * 125000);
-	else    /* if < 2 sec */
+	else /* if < 2 sec */
 		/* 30.5(=61/2) us per count */
 		time.le.lo = (uint32_t)(count * 61 / 2);
 
 	time.le.hi = 0;
 
-	return time;  /* in uSec */
+	return time; /* in uSec */
 }
 
 /**
@@ -275,8 +270,7 @@ static timestamp_t system_get_htimer(void)
 static void system_reset_htimer_alarm(void)
 {
 	MCHP_HTIMER_PRELOAD(0) = 0;
-	MCHP_INT_SOURCE(MCHP_HTIMER_GIRQ) =
-			MCHP_HTIMER_GIRQ_BIT(0);
+	MCHP_INT_SOURCE(MCHP_HTIMER_GIRQ) = MCHP_HTIMER_GIRQ_BIT(0);
 }
 
 #ifdef CONFIG_MCHP_DEEP_SLP_DEBUG
@@ -286,10 +280,10 @@ static void print_pcr_regs(void)
 
 	trace0(0, MEC, 0, "Current PCR registers");
 	for (i = 0; i < 5; i++) {
-		trace12(0, MEC, 0, "REG  SLP_EN[%d] = 0x%08X",
-			i, MCHP_PCR_SLP_EN(i));
-		trace12(0, MEC, 0, "REG CLK_REQ[%d] = 0x%08X",
-			i, MCHP_PCR_CLK_REQ(i));
+		trace12(0, MEC, 0, "REG  SLP_EN[%d] = 0x%08X", i,
+			MCHP_PCR_SLP_EN(i));
+		trace12(0, MEC, 0, "REG CLK_REQ[%d] = 0x%08X", i,
+			MCHP_PCR_CLK_REQ(i));
 	}
 }
 
@@ -298,10 +292,9 @@ static void print_ecia_regs(void)
 	int i;
 
 	trace0(0, MEC, 0, "Current GIRQn.Result registers");
-	for (i = MCHP_INT_GIRQ_FIRST;
-			i <= MCHP_INT_GIRQ_LAST; i++)
-		trace12(0, MEC, 0, "GIRQ[%d].Result = 0x%08X",
-			i, MCHP_INT_RESULT(i));
+	for (i = MCHP_INT_GIRQ_FIRST; i <= MCHP_INT_GIRQ_LAST; i++)
+		trace12(0, MEC, 0, "GIRQ[%d].Result = 0x%08X", i,
+			MCHP_INT_RESULT(i));
 }
 
 static void save_regs(void)
@@ -314,8 +307,7 @@ static void save_regs(void)
 	}
 
 	for (i = 0; i < MCHP_INT_GIRQ_NUM; i++)
-		ecia_result[i] =
-			MCHP_INT_RESULT(MCHP_INT_GIRQ_FIRST + i);
+		ecia_result[i] = MCHP_INT_RESULT(MCHP_INT_GIRQ_FIRST + i);
 }
 
 static void print_saved_regs(void)
@@ -324,21 +316,29 @@ static void print_saved_regs(void)
 
 	trace0(0, BRD, 0, "Before sleep saved registers");
 	for (i = 0; i < MCHP_PCR_SLP_RST_REG_MAX; i++) {
-		trace12(0, BRD, 0, "PCR_SLP_EN[%d]  = 0x%08X",
-			i, pcr_slp_en[i]);
-		trace12(0, BRD, 0, "PCR_CLK_REQ[%d] = 0x%08X",
-			i, pcr_clk_req[i]);
+		trace12(0, BRD, 0, "PCR_SLP_EN[%d]  = 0x%08X", i,
+			pcr_slp_en[i]);
+		trace12(0, BRD, 0, "PCR_CLK_REQ[%d] = 0x%08X", i,
+			pcr_clk_req[i]);
 	}
 
 	for (i = 0; i < MCHP_INT_GIRQ_NUM; i++)
 		trace12(0, BRD, 0, "GIRQ[%d].Result = 0x%08X",
-			(i+MCHP_INT_GIRQ_FIRST), ecia_result[i]);
+			(i + MCHP_INT_GIRQ_FIRST), ecia_result[i]);
 }
 #else
-static __maybe_unused void print_pcr_regs(void) {}
-static __maybe_unused void print_ecia_regs(void) {}
-static __maybe_unused void save_regs(void) {}
-static __maybe_unused void print_saved_regs(void) {}
+static __maybe_unused void print_pcr_regs(void)
+{
+}
+static __maybe_unused void print_ecia_regs(void)
+{
+}
+static __maybe_unused void save_regs(void)
+{
+}
+static __maybe_unused void print_saved_regs(void)
+{
+}
 #endif /* #ifdef CONFIG_MCHP_DEEP_SLP_DEBUG */
 
 /**
@@ -377,24 +377,19 @@ static void prepare_for_deep_sleep(void)
 	MCHP_TMR32_CTL(1) &= ~1;
 #ifdef CONFIG_WATCHDOG_HELP
 	MCHP_TMR16_CTL(0) &= ~1;
-	MCHP_INT_DISABLE(MCHP_TMR16_GIRQ) =
-			MCHP_TMR16_GIRQ_BIT(0);
-	MCHP_INT_SOURCE(MCHP_TMR16_GIRQ) =
-			MCHP_TMR16_GIRQ_BIT(0);
+	MCHP_INT_DISABLE(MCHP_TMR16_GIRQ) = MCHP_TMR16_GIRQ_BIT(0);
+	MCHP_INT_SOURCE(MCHP_TMR16_GIRQ) = MCHP_TMR16_GIRQ_BIT(0);
 #endif
 	MCHP_INT_DISABLE(MCHP_TMR32_GIRQ) =
-			MCHP_TMR32_GIRQ_BIT(0) +
-			MCHP_TMR32_GIRQ_BIT(1);
+		MCHP_TMR32_GIRQ_BIT(0) + MCHP_TMR32_GIRQ_BIT(1);
 	MCHP_INT_SOURCE(MCHP_TMR32_GIRQ) =
-			MCHP_TMR32_GIRQ_BIT(0) +
-			MCHP_TMR32_GIRQ_BIT(1);
+		MCHP_TMR32_GIRQ_BIT(0) + MCHP_TMR32_GIRQ_BIT(1);
 
 #ifdef CONFIG_WATCHDOG
 	/* Stop watchdog */
 	MCHP_WDG_CTL &= ~1;
 #endif
 
-
 #ifdef CONFIG_HOST_INTERFACE_ESPI
 	MCHP_INT_SOURCE(22) = MCHP_INT22_WAKE_ONLY_ESPI;
 	MCHP_INT_ENABLE(22) = MCHP_INT22_WAKE_ONLY_ESPI;
@@ -448,7 +443,7 @@ static void prepare_for_deep_sleep(void)
 
 static void resume_from_deep_sleep(void)
 {
-	MCHP_PCR_SYS_SLP_CTL = 0x00;  /* default */
+	MCHP_PCR_SYS_SLP_CTL = 0x00; /* default */
 
 	/* Disable assertion of DeepSleep signal when core executes WFI */
 	CPU_SCB_SYSCTRL &= ~BIT(2);
@@ -476,19 +471,19 @@ static void resume_from_deep_sleep(void)
 	MCHP_PCR_SLP_EN3 |= (MCHP_PCR_SLP_EN3_HTMR0);
 
 #ifdef CONFIG_HOST_INTERFACE_ESPI
-	#ifdef CONFIG_POWER_S0IX
+#ifdef CONFIG_POWER_S0IX
 	MCHP_INT_DISABLE(22) = MCHP_INT22_WAKE_ONLY_ESPI;
 	MCHP_INT_SOURCE(22) = MCHP_INT22_WAKE_ONLY_ESPI;
-	#else
+#else
 	MCHP_ESPI_ACTIVATE |= 1;
-	#endif
+#endif
 #else
-	#ifdef CONFIG_POWER_S0IX
+#ifdef CONFIG_POWER_S0IX
 	MCHP_INT_DISABLE(22) = MCHP_INT22_WAKE_ONLY_LPC;
 	MCHP_INT_SOURCE(22) = MCHP_INT22_WAKE_ONLY_LPC;
-	#else
+#else
 	MCHP_LPC_ACT |= 1;
-	#endif
+#endif
 #endif
 
 	/* re-enable Port 80 capture */
@@ -505,10 +500,8 @@ static void resume_from_deep_sleep(void)
 	MCHP_TMR32_CTL(1) |= 1;
 	MCHP_TMR16_CTL(0) |= 1;
 	MCHP_INT_ENABLE(MCHP_TMR32_GIRQ) =
-			MCHP_TMR32_GIRQ_BIT(0) +
-			MCHP_TMR32_GIRQ_BIT(1);
-	MCHP_INT_ENABLE(MCHP_TMR16_GIRQ) =
-			MCHP_TMR16_GIRQ_BIT(0);
+		MCHP_TMR32_GIRQ_BIT(0) + MCHP_TMR32_GIRQ_BIT(1);
+	MCHP_INT_ENABLE(MCHP_TMR16_GIRQ) = MCHP_TMR16_GIRQ_BIT(0);
 
 	/* Enable watchdog */
 #ifdef CONFIG_WATCHDOG
@@ -521,7 +514,6 @@ static void resume_from_deep_sleep(void)
 #endif
 }
 
-
 void clock_refresh_console_in_use(void)
 {
 	disable_sleep(SLEEP_MASK_CONSOLE);
@@ -547,9 +539,7 @@ void __idle(void)
 	htimer_init(); /* hibernation timer initialize */
 
 	disable_sleep(SLEEP_MASK_CONSOLE);
-	console_expire_time.val = get_time().val +
-			CONSOLE_IN_USE_ON_BOOT_TIME;
-
+	console_expire_time.val = get_time().val + CONSOLE_IN_USE_ON_BOOT_TIME;
 
 	/*
 	 * Print when the idle task starts. This is the lowest priority
@@ -562,17 +552,15 @@ void __idle(void)
 		/* Disable interrupts */
 		interrupt_disable();
 
-		t0 = get_time();  /* uSec */
+		t0 = get_time(); /* uSec */
 
 		/* __hw_clock_event_get() is next programmed timer event */
 		next_delay = __hw_clock_event_get() - t0.le.lo;
 
-		time_for_dsleep = next_delay >
-			(HEAVY_SLEEP_RECOVER_TIME_USEC +
-			SET_HTIMER_DELAY_USEC);
+		time_for_dsleep = next_delay > (HEAVY_SLEEP_RECOVER_TIME_USEC +
+						SET_HTIMER_DELAY_USEC);
 
-		max_sleep_time = next_delay -
-				HEAVY_SLEEP_RECOVER_TIME_USEC;
+		max_sleep_time = next_delay - HEAVY_SLEEP_RECOVER_TIME_USEC;
 
 		/* check if there enough time for deep sleep */
 		if (DEEP_SLEEP_ALLOWED && time_for_dsleep) {
@@ -582,7 +570,7 @@ void __idle(void)
 			 * interrupt.
 			 */
 			if ((sleep_mask & SLEEP_MASK_CONSOLE) &&
-				t0.val > console_expire_time.val) {
+			    t0.val > console_expire_time.val) {
 				/* allow console to sleep. */
 				enable_sleep(SLEEP_MASK_CONSOLE);
 
@@ -598,12 +586,10 @@ void __idle(void)
 						"in deep sleep");
 			}
 
-
 			/* UART is not being used  */
 			uart_ready_for_deepsleep =
 				LOW_SPEED_DEEP_SLEEP_ALLOWED &&
-					!uart_tx_in_progress() &&
-					uart_buffer_empty();
+				!uart_tx_in_progress() && uart_buffer_empty();
 
 			/*
 			 * Since MCHP's heavy sleep mode requires all
@@ -612,7 +598,6 @@ void __idle(void)
 			 * heavy sleep of EC.
 			 */
 			if (uart_ready_for_deepsleep) {
-
 				idle_dsleep_cnt++;
 
 				/*
@@ -630,18 +615,14 @@ void __idle(void)
 				 * interrupt triggers only after 'wfi'
 				 * completes its execution.
 				 */
-				max_sleep_time -=
-					(get_time().le.lo - t0.le.lo);
+				max_sleep_time -= (get_time().le.lo - t0.le.lo);
 
 				/* setup/enable htimer wakeup interrupt */
-				system_set_htimer_alarm(0,
-						max_sleep_time);
+				system_set_htimer_alarm(0, max_sleep_time);
 
 				/* set sleep all just before WFI */
-				MCHP_PCR_SYS_SLP_CTL |=
-						MCHP_PCR_SYS_SLP_HEAVY;
-				MCHP_PCR_SYS_SLP_CTL |=
-						MCHP_PCR_SYS_SLP_ALL;
+				MCHP_PCR_SYS_SLP_CTL |= MCHP_PCR_SYS_SLP_HEAVY;
+				MCHP_PCR_SYS_SLP_CTL |= MCHP_PCR_SYS_SLP_ALL;
 
 			} else {
 				idle_sleep_cnt++;
@@ -649,12 +630,11 @@ void __idle(void)
 
 			/* Wait for interrupt: goes into deep sleep. */
 			asm("dsb");
-			asm("wfi");
+			cpu_enter_suspend_mode();
 			asm("isb");
 			asm("nop");
 
 			if (uart_ready_for_deepsleep) {
-
 				resume_from_deep_sleep();
 
 				/*
@@ -673,9 +653,8 @@ void __idle(void)
 				/* disable/clear htimer wakeup interrupt */
 				system_reset_htimer_alarm();
 
-				t1.val = t0.val +
-					(uint64_t)(max_sleep_time -
-							ht_t1.le.lo);
+				t1.val = t0.val + (uint64_t)(max_sleep_time -
+							     ht_t1.le.lo);
 
 				force_time(t1);
 
@@ -685,15 +664,14 @@ void __idle(void)
 				/* Record time spent in deep sleep. */
 				total_idle_dsleep_time_us +=
 					(uint64_t)(max_sleep_time -
-							ht_t1.le.lo);
+						   ht_t1.le.lo);
 			}
 
 		} else { /* CPU 'Sleep' mode */
 
 			idle_sleep_cnt++;
 
-			asm("wfi");
-
+			cpu_enter_suspend_mode();
 		}
 
 		interrupt_enable();
@@ -705,34 +683,30 @@ void __idle(void)
  * Print low power idle statistics
  */
 
-static int command_idle_stats(int argc, char **argv)
+static int command_idle_stats(int argc, const char **argv)
 {
 	timestamp_t ts = get_time();
 
-	ccprintf("Num idle calls that sleep:           %d\n",
-			idle_sleep_cnt);
-	ccprintf("Num idle calls that deep-sleep:      %d\n",
-			idle_dsleep_cnt);
+	ccprintf("Num idle calls that sleep:           %d\n", idle_sleep_cnt);
+	ccprintf("Num idle calls that deep-sleep:      %d\n", idle_dsleep_cnt);
 
 	ccprintf("Total Time spent in deep-sleep(sec): %.6lld(s)\n",
-			total_idle_dsleep_time_us);
-	ccprintf("Total time on:                       %.6llds\n\n",
-			ts.val);
+		 total_idle_dsleep_time_us);
+	ccprintf("Total time on:                       %.6llds\n\n", ts.val);
 
 	if (IS_ENABLED(CONFIG_MCHP_DEEP_SLP_DEBUG))
-		print_pcr_regs();	/* debug */
+		print_pcr_regs(); /* debug */
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats,
-			"",
+DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, "",
 			"Print last idle stats");
 #endif /* defined(CONFIG_CMD_IDLE_STATS) */
 
 /**
  * Configure deep sleep clock settings.
  */
-static int command_dsleep(int argc, char **argv)
+static int command_dsleep(int argc, const char **argv)
 {
 	int v;
 
@@ -742,12 +716,10 @@ static int command_dsleep(int argc, char **argv)
 			 * Force deep sleep not to use heavy sleep mode or
 			 * allow it to use the heavy sleep mode.
 			 */
-			if (v)  /* 'on' */
-				disable_sleep(
-					SLEEP_MASK_FORCE_NO_LOW_SPEED);
-			else    /* 'off' */
-				enable_sleep(
-					SLEEP_MASK_FORCE_NO_LOW_SPEED);
+			if (v) /* 'on' */
+				disable_sleep(SLEEP_MASK_FORCE_NO_LOW_SPEED);
+			else /* 'off' */
+				enable_sleep(SLEEP_MASK_FORCE_NO_LOW_SPEED);
 		} else {
 			/* Set console in use timeout. */
 			char *e;
@@ -765,16 +737,16 @@ static int command_dsleep(int argc, char **argv)
 
 	ccprintf("Sleep mask: %08x\n", (int)sleep_mask);
 	ccprintf("Console in use timeout:   %d sec\n",
-			console_in_use_timeout_sec);
+		 console_in_use_timeout_sec);
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(dsleep, command_dsleep,
-		"[ on | off | <timeout> sec]",
-		"Deep sleep clock settings:\nUse 'on' to force deep "
-		"sleep NOT to enter heavy sleep mode.\nUse 'off' to "
-		"allow deep sleep to use heavy sleep whenever conditions "
-		"allow.\n"
-		"Give a timeout value for the console in use timeout.\n"
-		"See also 'sleep mask'.");
+DECLARE_CONSOLE_COMMAND(
+	dsleep, command_dsleep, "[ on | off | <timeout> sec]",
+	"Deep sleep clock settings:\nUse 'on' to force deep "
+	"sleep NOT to enter heavy sleep mode.\nUse 'off' to "
+	"allow deep sleep to use heavy sleep whenever conditions "
+	"allow.\n"
+	"Give a timeout value for the console in use timeout.\n"
+	"See also 'sleep mask'.");
 #endif /* CONFIG_LOW_POWER_IDLE */
diff --git a/chip/mchp/clock_chip.h b/chip/mchp/clock_chip.h
index 2e7de60358..4b851aa2bd 100644
--- a/chip/mchp/clock_chip.h
+++ b/chip/mchp/clock_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,7 +11,6 @@
 #include <stdint.h>
 
 void htimer_init(void);
-void system_set_htimer_alarm(uint32_t seconds,
-		uint32_t microseconds);
+void system_set_htimer_alarm(uint32_t seconds, uint32_t microseconds);
 
 #endif /* __CROS_EC_I2C_CLOCK_H */
diff --git a/chip/mchp/config_chip.h b/chip/mchp/config_chip.h
index cf7ead512a..4d5836ef42 100644
--- a/chip/mchp/config_chip.h
+++ b/chip/mchp/config_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,11 +20,11 @@
 
 /* Use a bigger console output buffer */
 #undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE	1024
+#define CONFIG_UART_TX_BUF_SIZE 1024
 
 /* Interval between HOOK_TICK notifications */
-#define HOOK_TICK_INTERVAL_MS	250
-#define HOOK_TICK_INTERVAL	(HOOK_TICK_INTERVAL_MS * MSEC)
+#define HOOK_TICK_INTERVAL_MS 250
+#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC)
 
 /*
  * Enable chip_pre_init called from main
@@ -48,14 +48,14 @@
  * addresses. Define fake peripheral addresses that aren't used by
  * peripherals on the board.
  */
-#define CONFIG_MCHP_I2C0_SLAVE_ADDRS	0xE3E1
-#define CONFIG_MCHP_I2C1_SLAVE_ADDRS	0xE3E1
-#define CONFIG_MCHP_I2C2_SLAVE_ADDRS	0xE3E1
-#define CONFIG_MCHP_I2C3_SLAVE_ADDRS	0xE3E1
-#define CONFIG_MCHP_I2C4_SLAVE_ADDRS	0xE3E1
-#define CONFIG_MCHP_I2C5_SLAVE_ADDRS	0xE3E1
-#define CONFIG_MCHP_I2C6_SLAVE_ADDRS	0xE3E1
-#define CONFIG_MCHP_I2C7_SLAVE_ADDRS	0xE3E1
+#define CONFIG_MCHP_I2C0_SLAVE_ADDRS 0xE3E1
+#define CONFIG_MCHP_I2C1_SLAVE_ADDRS 0xE3E1
+#define CONFIG_MCHP_I2C2_SLAVE_ADDRS 0xE3E1
+#define CONFIG_MCHP_I2C3_SLAVE_ADDRS 0xE3E1
+#define CONFIG_MCHP_I2C4_SLAVE_ADDRS 0xE3E1
+#define CONFIG_MCHP_I2C5_SLAVE_ADDRS 0xE3E1
+#define CONFIG_MCHP_I2C6_SLAVE_ADDRS 0xE3E1
+#define CONFIG_MCHP_I2C7_SLAVE_ADDRS 0xE3E1
 
 /************************************************************************/
 /* Memory mapping */
@@ -74,45 +74,44 @@
 /* Define our RAM layout. */
 
 #if defined(CHIP_FAMILY_MEC172X)
-#define CONFIG_MEC_SRAM_BASE_START	0x000C0000
-#define CONFIG_MEC_SRAM_BASE_END	(0x00128000 - (2 * 1024))
+#define CONFIG_MEC_SRAM_BASE_START 0x000C0000
+#define CONFIG_MEC_SRAM_BASE_END (0x00128000 - (2 * 1024))
 #else
-#define CONFIG_MEC_SRAM_BASE_START	0x000E0000
-#define CONFIG_MEC_SRAM_BASE_END	0x00120000
+#define CONFIG_MEC_SRAM_BASE_START 0x000E0000
+#define CONFIG_MEC_SRAM_BASE_END 0x00120000
 #endif
 
-#define CONFIG_MEC_SRAM_SIZE		(CONFIG_MEC_SRAM_BASE_END - \
-					CONFIG_MEC_SRAM_BASE_START)
+#define CONFIG_MEC_SRAM_SIZE \
+	(CONFIG_MEC_SRAM_BASE_END - CONFIG_MEC_SRAM_BASE_START)
 /* 64k Data RAM for RO / RW / loader */
-#define CONFIG_RAM_SIZE			0x00010000
-#define CONFIG_RAM_BASE			(CONFIG_MEC_SRAM_BASE_END - \
-					CONFIG_RAM_SIZE)
+#define CONFIG_RAM_SIZE 0x00010000
+#define CONFIG_RAM_BASE (CONFIG_MEC_SRAM_BASE_END - CONFIG_RAM_SIZE)
 
 /* System stack size */
 /* was 1024, temporarily expanded to 2048 for debug */
-#define CONFIG_STACK_SIZE		2048
+#define CONFIG_STACK_SIZE 2048
 
 /* non-standard task stack sizes */
-#define IDLE_TASK_STACK_SIZE		672
-#define LARGER_TASK_STACK_SIZE		800
-#define VENTI_TASK_STACK_SIZE		928
-#define ULTRA_TASK_STACK_SIZE		1056
-#define TRENTA_TASK_STACK_SIZE		1184
+#define IDLE_TASK_STACK_SIZE 672
+#define LARGER_TASK_STACK_SIZE 800
+#define VENTI_TASK_STACK_SIZE 928
+#define ULTRA_TASK_STACK_SIZE 1056
+#define TRENTA_TASK_STACK_SIZE 1184
 
-#define CHARGER_TASK_STACK_SIZE		1024	/* 640 */
-#define HOOKS_TASK_STACK_SIZE		1024	/* 640 */
-#define CONSOLE_TASK_STACK_SIZE		1024	/* 640 */
-#define HOST_CMD_TASK_STACK_SIZE	1024	/* 640 */
+#define CHARGER_TASK_STACK_SIZE 1024 /* 640 */
+#define HOOKS_TASK_STACK_SIZE 1024 /* 640 */
+#define CONSOLE_TASK_STACK_SIZE 1024 /* 640 */
+#define HOST_CMD_TASK_STACK_SIZE 1024 /* 640 */
 
 /*
  * TODO: Large stack consumption
  * https://code.google.com/p/chrome-os-partner/issues/detail?id=49245
  */
 /* original = 800, if stack exceptions expand to 1024 for debug */
-#define PD_TASK_STACK_SIZE		2048
+#define PD_TASK_STACK_SIZE 2048
 
 /* Default task stack size */
-#define TASK_STACK_SIZE			672
+#define TASK_STACK_SIZE 672
 
 /************************************************************************/
 /* Define our flash layout. */
@@ -134,20 +133,20 @@
 #endif
 
 /* Protect bank size 4K bytes */
-#define CONFIG_FLASH_BANK_SIZE		0x00001000
+#define CONFIG_FLASH_BANK_SIZE 0x00001000
 /* Sector erase size 4K bytes */
-#define CONFIG_FLASH_ERASE_SIZE		0x00001000
+#define CONFIG_FLASH_ERASE_SIZE 0x00001000
 /* Minimum write size */
-#define CONFIG_FLASH_WRITE_SIZE		0x00000004
+#define CONFIG_FLASH_WRITE_SIZE 0x00000004
 
 /* One page size for write */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE	256
+#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256
 
 /* Program memory base address */
 #if defined(CHIP_FAMILY_MEC172X)
-#define CONFIG_PROGRAM_MEMORY_BASE	0x000C0000
+#define CONFIG_PROGRAM_MEMORY_BASE 0x000C0000
 #else
-#define CONFIG_PROGRAM_MEMORY_BASE	0x000E0000
+#define CONFIG_PROGRAM_MEMORY_BASE 0x000E0000
 #endif
 
 /*
@@ -232,14 +231,13 @@
  * GPIO(PCH_SLP_S0_L, PIN(0x89), GPIO_INPUT | GPIO_PULL_DOWN)
  */
 #define GPIO_BANK(index) ((index) >> 5)
-#define GPIO_BANK_MASK(index) (1ul << ((index) & 0x1F))
+#define GPIO_BANK_MASK(index) (1ul << ((index)&0x1F))
 
 #define GPIO_PIN(index) GPIO_BANK(index), GPIO_BANK_MASK(index)
 #define GPIO_PIN_MASK(p, m) .port = (p), .mask = (m)
 
 #ifndef __ASSEMBLER__
 
-
 #endif /* #ifndef __ASSEMBLER__ */
 
-#endif  /* __CROS_EC_CONFIG_CHIP_H */
+#endif /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/chip/mchp/config_flash_layout.h b/chip/mchp/config_flash_layout.h
index caa1e204e0..f495f65465 100644
--- a/chip/mchp/config_flash_layout.h
+++ b/chip/mchp/config_flash_layout.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,8 +16,8 @@
 
 /* Non-memmory mapped, external SPI */
 #define CONFIG_EXTERNAL_STORAGE
-#undef  CONFIG_MAPPED_STORAGE
-#undef  CONFIG_FLASH_PSTATE
+#undef CONFIG_MAPPED_STORAGE
+#undef CONFIG_FLASH_PSTATE
 #define CONFIG_SPI_FLASH
 
 /*
@@ -33,32 +33,30 @@
  * EC_RO and EC_RW padded sizes from the build are 188KB each.
  * Storage size is 1/2 flash size.
  */
-#define CONFIG_EC_PROTECTED_STORAGE_OFF	0
+#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
 /* Lower 256KB of flash is protected region */
 #define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x40000
 /* Writable storage for EC_RW starts at 256KB */
 #define CONFIG_EC_WRITABLE_STORAGE_OFF 0x40000
 /* Writeable storage is 256KB */
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE  0x40000
-
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x40000
 
 /* Loader resides at the beginning of program memory */
-#define CONFIG_LOADER_MEM_OFF		0
-#define CONFIG_LOADER_SIZE		0x1000
+#define CONFIG_LOADER_MEM_OFF 0
+#define CONFIG_LOADER_SIZE 0x1000
 
 /* Write protect Loader and RO Image */
-#define CONFIG_WP_STORAGE_OFF		CONFIG_EC_PROTECTED_STORAGE_OFF
+#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
 /*
  * Write protect LFW + EC_RO
  */
-#define CONFIG_WP_STORAGE_SIZE		CONFIG_EC_PROTECTED_STORAGE_SIZE
+#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
 
 /*
  * RO / RW images follow the loader in program memory. Either RO or RW
  * image will be loaded -- both cannot be loaded at the same time.
  */
-#define CONFIG_RO_MEM_OFF		(CONFIG_LOADER_MEM_OFF + \
-					CONFIG_LOADER_SIZE)
+#define CONFIG_RO_MEM_OFF (CONFIG_LOADER_MEM_OFF + CONFIG_LOADER_SIZE)
 /*
  * Total SRAM and the amount allocated for data are specified
  * by CONFIG_MEC_SRAM_SIZE and CONFIG_RAM_SIZE in config_chip.h
@@ -69,20 +67,20 @@
  * and must be located on a erase block boundary. !!!
  */
 #if (CONFIG_MEC_SRAM_SIZE > CONFIG_EC_PROTECTED_STORAGE_SIZE)
-#define CONFIG_RO_SIZE			(CONFIG_EC_PROTECTED_STORAGE_SIZE - \
-					CONFIG_LOADER_SIZE - 0x2000)
+#define CONFIG_RO_SIZE \
+	(CONFIG_EC_PROTECTED_STORAGE_SIZE - CONFIG_LOADER_SIZE - 0x2000)
 #else
-#define CONFIG_RO_SIZE			(CONFIG_MEC_SRAM_SIZE - \
-					CONFIG_RAM_SIZE - CONFIG_LOADER_SIZE)
+#define CONFIG_RO_SIZE \
+	(CONFIG_MEC_SRAM_SIZE - CONFIG_RAM_SIZE - CONFIG_LOADER_SIZE)
 #endif
 
-#define CONFIG_RW_MEM_OFF		CONFIG_RO_MEM_OFF
+#define CONFIG_RW_MEM_OFF CONFIG_RO_MEM_OFF
 /*
  * NOTE: CONFIG_RW_SIZE is passed to the SPI image generation script by
  * chip build.mk
  * LFW requires CONFIG_RW_SIZE is equal to CONFIG_RO_SIZE !!!
  */
-#define CONFIG_RW_SIZE			CONFIG_RO_SIZE
+#define CONFIG_RW_SIZE CONFIG_RO_SIZE
 
 /*
  * WP region consists of first half of SPI containing TAGs at beginning
@@ -104,7 +102,7 @@
  * greater aligned boundaries.
  */
 
-#define CONFIG_RW_BOOT_HEADER_STORAGE_OFF	0
+#define CONFIG_RW_BOOT_HEADER_STORAGE_OFF 0
 #if defined(CHIP_FAMILY_MEC172X)
 /*
  * Changed to 0x140 original 0xc0 which is incorrect
@@ -123,33 +121,31 @@
  * 0x40000 - 0x7ffff = EC_RW padded with 0xFF
  * To EC the "header" is one 4KB chunk at offset 0
  */
-#define CONFIG_BOOT_HEADER_STORAGE_OFF		0
-#define CONFIG_BOOT_HEADER_STORAGE_SIZE     0x1000
+#define CONFIG_BOOT_HEADER_STORAGE_OFF 0
+#define CONFIG_BOOT_HEADER_STORAGE_SIZE 0x1000
 #elif defined(CHIP_FAMILY_MEC152X)
-#define CONFIG_BOOT_HEADER_STORAGE_OFF		0x1000
-#define CONFIG_BOOT_HEADER_STORAGE_SIZE		0x140
+#define CONFIG_BOOT_HEADER_STORAGE_OFF 0x1000
+#define CONFIG_BOOT_HEADER_STORAGE_SIZE 0x140
 #elif defined(CHIP_FAMILY_MEC170X)
-#define CONFIG_BOOT_HEADER_STORAGE_OFF		0x1000
-#define CONFIG_BOOT_HEADER_STORAGE_SIZE		0x80
+#define CONFIG_BOOT_HEADER_STORAGE_OFF 0x1000
+#define CONFIG_BOOT_HEADER_STORAGE_SIZE 0x80
 #else
 #error "FORCED BUILD ERROR: CHIP_FAMILY_xxxx not set or invalid"
 #endif
-#define CONFIG_RW_BOOT_HEADER_STORAGE_SIZE	0
+#define CONFIG_RW_BOOT_HEADER_STORAGE_SIZE 0
 
 /* Loader / lfw image immediately follows the boot header on SPI */
-#define CONFIG_LOADER_STORAGE_OFF	(CONFIG_BOOT_HEADER_STORAGE_OFF + \
-					CONFIG_BOOT_HEADER_STORAGE_SIZE)
+#define CONFIG_LOADER_STORAGE_OFF \
+	(CONFIG_BOOT_HEADER_STORAGE_OFF + CONFIG_BOOT_HEADER_STORAGE_SIZE)
 
 /* RO image immediately follows the loader image */
-#define CONFIG_RO_STORAGE_OFF		(CONFIG_LOADER_STORAGE_OFF + \
-					CONFIG_LOADER_SIZE)
+#define CONFIG_RO_STORAGE_OFF (CONFIG_LOADER_STORAGE_OFF + CONFIG_LOADER_SIZE)
 
 /*
  * RW image starts at offset 0 of second half of SPI.
  * RW Header not needed.
  */
-#define CONFIG_RW_STORAGE_OFF		(CONFIG_RW_BOOT_HEADER_STORAGE_OFF + \
-					CONFIG_RW_BOOT_HEADER_STORAGE_SIZE)
-
+#define CONFIG_RW_STORAGE_OFF \
+	(CONFIG_RW_BOOT_HEADER_STORAGE_OFF + CONFIG_RW_BOOT_HEADER_STORAGE_SIZE)
 
 #endif /* __CROS_EC_CONFIG_FLASH_LAYOUT_H */
diff --git a/chip/mchp/dma.c b/chip/mchp/dma.c
index 982dfa8122..8a091286a7 100644
--- a/chip/mchp/dma.c
+++ b/chip/mchp/dma.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,7 +15,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_DMA, outstr)
-#define CPRINTS(format, args...) cprints(CC_DMA, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_DMA, format, ##args)
 
 dma_chan_t *dma_get_channel(enum dma_channel channel)
 {
@@ -23,7 +23,7 @@ dma_chan_t *dma_get_channel(enum dma_channel channel)
 
 	if (channel < MCHP_DMAC_COUNT) {
 		pd = (dma_chan_t *)(MCHP_DMA_BASE + MCHP_DMA_CH_OFS +
-				(channel << MCHP_DMA_CH_OFS_BITPOS));
+				    (channel << MCHP_DMA_CH_OFS_BITPOS));
 	}
 
 	return pd;
@@ -35,7 +35,7 @@ void dma_disable(enum dma_channel channel)
 		if (MCHP_DMA_CH_CTRL(channel) & MCHP_DMA_RUN)
 			MCHP_DMA_CH_CTRL(channel) &= ~(MCHP_DMA_RUN);
 
-		if (MCHP_DMA_CH_ACT(channel)	& MCHP_DMA_ACT_EN)
+		if (MCHP_DMA_CH_ACT(channel) & MCHP_DMA_ACT_EN)
 			MCHP_DMA_CH_ACT(channel) = 0;
 	}
 }
@@ -74,10 +74,9 @@ void dma_disable_all(void)
  * is the number of bytes to transfer memory start - memory end = count.
  */
 static void prepare_channel(enum dma_channel ch, unsigned int count,
-		void *periph, void *memory, unsigned int flags)
+			    void *periph, void *memory, unsigned int flags)
 {
 	if (ch < MCHP_DMAC_COUNT) {
-
 		MCHP_DMA_CH_CTRL(ch) = 0;
 		MCHP_DMA_CH_MEM_START(ch) = (uint32_t)memory;
 		MCHP_DMA_CH_MEM_END(ch) = (uint32_t)memory + count;
@@ -115,16 +114,14 @@ void dma_prepare_tx(const struct dma_option *option, unsigned count,
 		 * Cast away const for memory pointer; this is ok because
 		 * we know we're preparing the channel for transmit.
 		 */
-		prepare_channel(option->channel, count, option->periph,
-			(void *)memory,
-			MCHP_DMA_INC_MEM |
-			MCHP_DMA_TO_DEV |
-			MCHP_DMA_DEV(option->channel) |
-			option->flags);
+		prepare_channel(
+			option->channel, count, option->periph, (void *)memory,
+			MCHP_DMA_INC_MEM | MCHP_DMA_TO_DEV |
+				MCHP_DMA_DEV(option->channel) | option->flags);
 }
 
 void dma_xfr_prepare_tx(const struct dma_option *option, uint32_t count,
-		const void *memory, uint32_t dma_xfr_units)
+			const void *memory, uint32_t dma_xfr_units)
 {
 	uint32_t nflags;
 
@@ -136,23 +133,19 @@ void dma_xfr_prepare_tx(const struct dma_option *option, uint32_t count,
 		 * we know we're preparing the channel for transmit.
 		 */
 		prepare_channel(option->channel, count, option->periph,
-			(void *)memory,
-			MCHP_DMA_INC_MEM |
-			MCHP_DMA_TO_DEV |
-			MCHP_DMA_DEV(option->channel) |
-			nflags);
+				(void *)memory,
+				MCHP_DMA_INC_MEM | MCHP_DMA_TO_DEV |
+					MCHP_DMA_DEV(option->channel) | nflags);
 	}
 }
 
-void dma_start_rx(const struct dma_option *option, unsigned count,
-		  void *memory)
+void dma_start_rx(const struct dma_option *option, unsigned count, void *memory)
 {
 	if (option != NULL) {
-		prepare_channel(option->channel, count, option->periph,
-				memory,
+		prepare_channel(option->channel, count, option->periph, memory,
 				MCHP_DMA_INC_MEM |
-				MCHP_DMA_DEV(option->channel) |
-				option->flags);
+					MCHP_DMA_DEV(option->channel) |
+					option->flags);
 		dma_go_chan(option->channel);
 	}
 }
@@ -161,26 +154,21 @@ void dma_start_rx(const struct dma_option *option, unsigned count,
  * Configure and start DMA channel for read from device and write to
  * memory. Allow caller to override DMA transfer unit length.
  */
-void dma_xfr_start_rx(const struct dma_option *option,
-		uint32_t dma_xfr_ulen,
-		uint32_t count, void *memory)
+void dma_xfr_start_rx(const struct dma_option *option, uint32_t dma_xfr_ulen,
+		      uint32_t count, void *memory)
 {
 	uint32_t ch, ctrl;
 
 	if (option != NULL) {
 		ch = option->channel;
 		if (ch < MCHP_DMAC_COUNT) {
-
 			MCHP_DMA_CH_CTRL(ch) = 0;
 			MCHP_DMA_CH_MEM_START(ch) = (uint32_t)memory;
-			MCHP_DMA_CH_MEM_END(ch) = (uint32_t)memory +
-					count;
+			MCHP_DMA_CH_MEM_END(ch) = (uint32_t)memory + count;
 
-			MCHP_DMA_CH_DEV_ADDR(ch) =
-					(uint32_t)option->periph;
+			MCHP_DMA_CH_DEV_ADDR(ch) = (uint32_t)option->periph;
 
-			ctrl = option->flags &
-					~(MCHP_DMA_XFER_SIZE_MASK);
+			ctrl = option->flags & ~(MCHP_DMA_XFER_SIZE_MASK);
 			ctrl |= MCHP_DMA_INC_MEM;
 			ctrl |= MCHP_DMA_XFER_SIZE(dma_xfr_ulen);
 			ctrl |= MCHP_DMA_DEV(option->channel);
@@ -228,8 +216,8 @@ int dma_bytes_done_chan(enum dma_channel ch, uint32_t orig_count)
 	if (ch < MCHP_DMAC_COUNT)
 		if (MCHP_DMA_CH_CTRL(ch) & MCHP_DMA_RUN)
 			cnt = (uint32_t)orig_count -
-					(MCHP_DMA_CH_MEM_END(ch) -
-					 MCHP_DMA_CH_MEM_START(ch));
+			      (MCHP_DMA_CH_MEM_END(ch) -
+			       MCHP_DMA_CH_MEM_START(ch));
 
 	return (int)cnt;
 }
@@ -259,9 +247,7 @@ int dma_wait(enum dma_channel channel)
 
 		deadline.val = get_time().val + DMA_TRANSFER_TIMEOUT_US;
 
-		while (!(MCHP_DMA_CH_ISTS(channel) &
-			 MCHP_DMA_STS_DONE)) {
-
+		while (!(MCHP_DMA_CH_ISTS(channel) & MCHP_DMA_STS_DONE)) {
 			if (deadline.val <= get_time().val)
 				return EC_ERROR_TIMEOUT;
 
@@ -282,8 +268,8 @@ void dma_clear_isr(enum dma_channel channel)
 		MCHP_DMA_CH_ISTS(channel) = 0x0f;
 }
 
-void dma_cfg_buffers(enum dma_channel ch, const void *membuf,
-			uint32_t nb, const void *pdev)
+void dma_cfg_buffers(enum dma_channel ch, const void *membuf, uint32_t nb,
+		     const void *pdev)
 {
 	if (ch < MCHP_DMAC_COUNT) {
 		MCHP_DMA_CH_MEM_START(ch) = (uint32_t)membuf;
@@ -301,8 +287,8 @@ void dma_cfg_buffers(enum dma_channel ch, const void *membuf,
  *   b[2] = 1 increment device address
  *   b[3] = disable HW flow control
  */
-void dma_cfg_xfr(enum dma_channel ch, uint8_t unit_len,
-			uint8_t dev_id, uint8_t flags)
+void dma_cfg_xfr(enum dma_channel ch, uint8_t unit_len, uint8_t dev_id,
+		 uint8_t flags)
 {
 	uint32_t ctrl;
 
@@ -378,7 +364,7 @@ int dma_crc32_start(const uint8_t *mstart, const uint32_t nbytes, int ien)
 	MCHP_DMA_CH_IEN(0) = 0;
 	MCHP_DMA_CH_ISTS(0) = 0xff;
 	MCHP_DMA_CH0_CRC32_EN = 1;
-	MCHP_DMA_CH0_CRC32_DATA	= 0xfffffffful;
+	MCHP_DMA_CH0_CRC32_DATA = 0xfffffffful;
 	/* program device address to point to read-only register */
 	MCHP_DMA_CH_DEV_ADDR(0) = (uint32_t)(MCHP_DMA_CH_BASE + 0x1c);
 	MCHP_DMA_CH_MEM_START(0) = (uint32_t)mstart;
@@ -387,7 +373,7 @@ int dma_crc32_start(const uint8_t *mstart, const uint32_t nbytes, int ien)
 		MCHP_DMA_CH_IEN(0) = 0x07;
 	MCHP_DMA_CH_ACT(0) = 1;
 	MCHP_DMA_CH_CTRL(0) = MCHP_DMA_TO_DEV + MCHP_DMA_INC_MEM +
-		MCHP_DMA_DIS_HW_FLOW + MCHP_DMA_XFER_SIZE(4);
+			      MCHP_DMA_DIS_HW_FLOW + MCHP_DMA_XFER_SIZE(4);
 	MCHP_DMA_CH_CTRL(0) |= MCHP_DMA_SW_GO;
 	return EC_SUCCESS;
 }
diff --git a/chip/mchp/dma_chip.h b/chip/mchp/dma_chip.h
index 42bcb095f6..6f569a1dc7 100644
--- a/chip/mchp/dma_chip.h
+++ b/chip/mchp/dma_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -16,24 +16,22 @@
 #include <stdint.h>
 #include <stddef.h>
 
-
 #ifdef __cplusplus
 extern "C" {
 #endif
 
 /* Place any C interfaces here */
 
-void dma_xfr_start_rx(const struct dma_option *option,
-		uint32_t dma_xfr_ulen,
-		uint32_t count, void *memory);
+void dma_xfr_start_rx(const struct dma_option *option, uint32_t dma_xfr_ulen,
+		      uint32_t count, void *memory);
 
 void dma_xfr_prepare_tx(const struct dma_option *option, uint32_t count,
-		const void *memory, uint32_t dma_xfr_units);
+			const void *memory, uint32_t dma_xfr_units);
 
 void dma_clr_chan(enum dma_channel ch);
 
-void dma_cfg_buffers(enum dma_channel ch, const void *membuf,
-			uint32_t nb, const void *pdev);
+void dma_cfg_buffers(enum dma_channel ch, const void *membuf, uint32_t nb,
+		     const void *pdev);
 
 /*
  * ch = zero based DMA channel number
@@ -44,13 +42,13 @@ void dma_cfg_buffers(enum dma_channel ch, const void *membuf,
  *   b[2] = 1 increment device address
  *   b[3] = disable HW flow control
  */
-#define DMA_FLAG_D2M		0
-#define DMA_FLAG_M2D		1
-#define DMA_FLAG_INCR_MEM	2
-#define DMA_FLAG_INCR_DEV	4
-#define DMA_FLAG_SW_FLOW	8
-void dma_cfg_xfr(enum dma_channel ch, uint8_t unit_len,
-			uint8_t dev_id, uint8_t flags);
+#define DMA_FLAG_D2M 0
+#define DMA_FLAG_M2D 1
+#define DMA_FLAG_INCR_MEM 2
+#define DMA_FLAG_INCR_DEV 4
+#define DMA_FLAG_SW_FLOW 8
+void dma_cfg_xfr(enum dma_channel ch, uint8_t unit_len, uint8_t dev_id,
+		 uint8_t flags);
 
 void dma_run(enum dma_channel ch);
 
diff --git a/chip/mchp/espi.c b/chip/mchp/espi.c
index 763b82ece2..371cf09c5e 100644
--- a/chip/mchp/espi.c
+++ b/chip/mchp/espi.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -36,7 +36,7 @@
 #define CPRINTS(...)
 #else
 #define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args)
 #endif
 #else
 #define CPUTS(...)
@@ -44,28 +44,28 @@
 #endif
 
 /* Default config to use maximum frequency */
-#ifndef CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ
+#ifndef CONFIG_HOST_INTERFACE_ESPI_EC_MAX_FREQ
 #if defined(CHIP_FAMILY_MEC172X)
-#define CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ		MCHP_ESPI_CAP1_MAX_FREQ_66M
+#define CONFIG_HOST_INTERFACE_ESPI_EC_MAX_FREQ MCHP_ESPI_CAP1_MAX_FREQ_66M
 #else
-#define CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ		MCHP_ESPI_CAP1_MAX_FREQ_50M
+#define CONFIG_HOST_INTERFACE_ESPI_EC_MAX_FREQ MCHP_ESPI_CAP1_MAX_FREQ_50M
 #endif
 #endif
 
 /* Default config to support all modes */
-#ifndef CONFIG_HOSTCMD_ESPI_EC_MODE
-#define CONFIG_HOSTCMD_ESPI_EC_MODE		MCHP_ESPI_CAP1_ALL_MODE
+#ifndef CONFIG_HOST_INTERFACE_ESPI_EC_MODE
+#define CONFIG_HOST_INTERFACE_ESPI_EC_MODE MCHP_ESPI_CAP1_ALL_MODE
 #endif
 
 /* Default config to support all channels */
-#ifndef CONFIG_HOSTCMD_ESPI_EC_CHAN_BITMAP
-#define CONFIG_HOSTCMD_ESPI_EC_CHAN_BITMAP	MCHP_ESPI_CAP0_ALL_CHAN_SUPP
+#ifndef CONFIG_HOST_INTERFACE_ESPI_EC_CHAN_BITMAP
+#define CONFIG_HOST_INTERFACE_ESPI_EC_CHAN_BITMAP MCHP_ESPI_CAP0_ALL_CHAN_SUPP
 #endif
 /*
  * eSPI slave to master virtual wire pulse timeout.
  */
-#define ESPI_S2M_VW_PULSE_LOOP_CNT		50
-#define ESPI_S2M_VW_PULSE_LOOP_DLY_US		10
+#define ESPI_S2M_VW_PULSE_LOOP_CNT 50
+#define ESPI_S2M_VW_PULSE_LOOP_DLY_US 10
 
 /*
  * eSPI master enable virtual wire channel timeout.
@@ -104,16 +104,15 @@ static uint32_t espi_channels_ready;
  *
  */
 struct vw_info_t {
-	uint16_t name;		/* signal name */
-	uint8_t  host_idx;	/* Host VWire index of signal */
-	uint8_t  reset_val;	/* reset value of VWire */
-	uint8_t  flags;		/* b[0]=0(MSVW), =1(SMVW) */
-	uint8_t  reg_idx;	/* MSVW or SMVW index */
-	uint8_t  src_num;	/* SRC number */
-	uint8_t  rsvd;
+	uint16_t name; /* signal name */
+	uint8_t host_idx; /* Host VWire index of signal */
+	uint8_t reset_val; /* reset value of VWire */
+	uint8_t flags; /* b[0]=0(MSVW), =1(SMVW) */
+	uint8_t reg_idx; /* MSVW or SMVW index */
+	uint8_t src_num; /* SRC number */
+	uint8_t rsvd;
 };
 
-
 /* VW signals used in eSPI */
 /*
  * MEC1701H VWire mapping based on eSPI Spec 1.0,
@@ -193,41 +192,40 @@ static const struct vw_info_t vw_info_tbl[] = {
 	 *				index value flags index num   rsvd
 	 */
 	/* MSVW00 Host index 02h (In) */
-	{VW_SLP_S3_L,			 0x02, 0x00, 0x00, 0x00, 0x00, 0x00},
-	{VW_SLP_S4_L,			 0x02, 0x00, 0x00, 0x00, 0x01, 0x00},
-	{VW_SLP_S5_L,			 0x02, 0x00, 0x10, 0x00, 0x02, 0x00},
+	{ VW_SLP_S3_L, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00 },
+	{ VW_SLP_S4_L, 0x02, 0x00, 0x00, 0x00, 0x01, 0x00 },
+	{ VW_SLP_S5_L, 0x02, 0x00, 0x10, 0x00, 0x02, 0x00 },
 	/* MSVW01 Host index 03h (In) */
-	{VW_SUS_STAT_L,			 0x03, 0x00, 0x10, 0x01, 0x00, 0x00},
-	{VW_PLTRST_L,			 0x03, 0x00, 0x10, 0x01, 0x01, 0x00},
-	{VW_OOB_RST_WARN,		 0x03, 0x00, 0x10, 0x01, 0x02, 0x00},
+	{ VW_SUS_STAT_L, 0x03, 0x00, 0x10, 0x01, 0x00, 0x00 },
+	{ VW_PLTRST_L, 0x03, 0x00, 0x10, 0x01, 0x01, 0x00 },
+	{ VW_OOB_RST_WARN, 0x03, 0x00, 0x10, 0x01, 0x02, 0x00 },
 	/* SMVW00 Host Index 04h (Out) */
-	{VW_OOB_RST_ACK,		 0x04, 0x00, 0x01, 0x00, 0x00, 0x00},
-	{VW_WAKE_L,			 0x04, 0x01, 0x01, 0x00, 0x02, 0x00},
-	{VW_PME_L,			 0x04, 0x01, 0x01, 0x00, 0x03, 0x00},
+	{ VW_OOB_RST_ACK, 0x04, 0x00, 0x01, 0x00, 0x00, 0x00 },
+	{ VW_WAKE_L, 0x04, 0x01, 0x01, 0x00, 0x02, 0x00 },
+	{ VW_PME_L, 0x04, 0x01, 0x01, 0x00, 0x03, 0x00 },
 	/* SMVW01 Host index 05h (Out) */
-	{VW_ERROR_FATAL,		 0x05, 0x00, 0x01, 0x01, 0x01, 0x00},
-	{VW_ERROR_NON_FATAL,		 0x05, 0x00, 0x01, 0x01, 0x02, 0x00},
-	{VW_PERIPHERAL_BTLD_STATUS_DONE, 0x05, 0x00, 0x01, 0x01, 0x30, 0x00},
+	{ VW_ERROR_FATAL, 0x05, 0x00, 0x01, 0x01, 0x01, 0x00 },
+	{ VW_ERROR_NON_FATAL, 0x05, 0x00, 0x01, 0x01, 0x02, 0x00 },
+	{ VW_PERIPHERAL_BTLD_STATUS_DONE, 0x05, 0x00, 0x01, 0x01, 0x30, 0x00 },
 	/* SMVW02 Host index 06h (Out) */
-	{VW_SCI_L,			 0x06, 0x01, 0x01, 0x02, 0x00, 0x00},
-	{VW_SMI_L,			 0x06, 0x01, 0x01, 0x02, 0x01, 0x00},
-	{VW_RCIN_L,			 0x06, 0x01, 0x01, 0x02, 0x02, 0x00},
-	{VW_HOST_RST_ACK,		 0x06, 0x00, 0x01, 0x02, 0x03, 0x00},
+	{ VW_SCI_L, 0x06, 0x01, 0x01, 0x02, 0x00, 0x00 },
+	{ VW_SMI_L, 0x06, 0x01, 0x01, 0x02, 0x01, 0x00 },
+	{ VW_RCIN_L, 0x06, 0x01, 0x01, 0x02, 0x02, 0x00 },
+	{ VW_HOST_RST_ACK, 0x06, 0x00, 0x01, 0x02, 0x03, 0x00 },
 	/* MSVW02 Host index 07h (In) */
-	{VW_HOST_RST_WARN,		 0x07, 0x00, 0x10, 0x02, 0x00, 0x00},
+	{ VW_HOST_RST_WARN, 0x07, 0x00, 0x10, 0x02, 0x00, 0x00 },
 	/* SMVW03 Host Index 40h (Out) */
-	{VW_SUS_ACK,			 0x40, 0x00, 0x01, 0x03, 0x00, 0x00},
+	{ VW_SUS_ACK, 0x40, 0x00, 0x01, 0x03, 0x00, 0x00 },
 	/* MSVW03 Host Index 41h (In) */
-	{VW_SUS_WARN_L,			 0x41, 0x00, 0x10, 0x03, 0x00, 0x00},
-	{VW_SUS_PWRDN_ACK_L,		 0x41, 0x00, 0x10, 0x03, 0x01, 0x00},
-	{VW_SLP_A_L,			 0x41, 0x00, 0x10, 0x03, 0x03, 0x00},
+	{ VW_SUS_WARN_L, 0x41, 0x00, 0x10, 0x03, 0x00, 0x00 },
+	{ VW_SUS_PWRDN_ACK_L, 0x41, 0x00, 0x10, 0x03, 0x01, 0x00 },
+	{ VW_SLP_A_L, 0x41, 0x00, 0x10, 0x03, 0x03, 0x00 },
 	/* MSVW04 Host index 42h (In) */
-	{VW_SLP_LAN,			 0x42, 0x00, 0x10, 0x04, 0x00, 0x00},
-	{VW_SLP_WLAN,			 0x42, 0x00, 0x10, 0x04, 0x01, 0x00}
+	{ VW_SLP_LAN, 0x42, 0x00, 0x10, 0x04, 0x00, 0x00 },
+	{ VW_SLP_WLAN, 0x42, 0x00, 0x10, 0x04, 0x01, 0x00 }
 };
 BUILD_ASSERT(ARRAY_SIZE(vw_info_tbl) == VW_SIGNAL_COUNT);
 
-
 /************************************************************************/
 /* eSPI internal utilities */
 
@@ -244,14 +242,12 @@ static int espi_vw_get_signal_index(enum espi_vw_signal event)
 	return -1;
 }
 
-
 /*
  * Initialize eSPI hardware upon ESPI_RESET# de-assertion
  */
 #ifdef CONFIG_MCHP_ESPI_RESET_DEASSERT_INIT
 static void espi_reset_deassert_init(void)
 {
-
 }
 #endif
 
@@ -341,7 +337,6 @@ static void espi_vw_restore(void)
 
 	r = MCHP_VBAT_RAM(MCHP_VBAT_VWIRE_BACKUP);
 	MCHP_VBAT_RAM(MCHP_VBAT_VWIRE_BACKUP) = r & 0xFFFFFF00;
-
 }
 #endif
 
@@ -362,8 +357,8 @@ static uint8_t __attribute__((unused)) espi_msvw_srcs_get(uint8_t msvw_id)
 	return msvw;
 }
 
-static void __attribute__((unused)) espi_msvw_srcs_set(uint8_t msvw_id,
-						       uint8_t src_bitmap)
+static void __attribute__((unused))
+espi_msvw_srcs_set(uint8_t msvw_id, uint8_t src_bitmap)
 {
 	if (msvw_id < MSVW_MAX) {
 		uint32_t r = (src_bitmap & 0x08) << 21;
@@ -392,8 +387,8 @@ static uint8_t __attribute__((unused)) espi_smvw_srcs_get(uint8_t smvw_id)
 	return smvw;
 }
 
-static void __attribute__((unused)) espi_smvw_srcs_set(uint8_t smvw_id,
-						       uint8_t src_bitmap)
+static void __attribute__((unused))
+espi_smvw_srcs_set(uint8_t smvw_id, uint8_t src_bitmap)
 {
 	if (smvw_id < SMVW_MAX) {
 		uint32_t r = (src_bitmap & 0x08) << 21;
@@ -405,7 +400,6 @@ static void __attribute__((unused)) espi_smvw_srcs_set(uint8_t smvw_id,
 	}
 }
 
-
 /*
  * Called before releasing RSMRST#
  *	ESPI_RESET# is asserted
@@ -466,7 +460,6 @@ static void espi_vw_pre_init(void)
 	CPRINTS("eSPI VW Pre-Init Done");
 }
 
-
 /*
  * If VWire, Flash, and OOB channels have been enabled
  * then set VWires SLAVE_BOOT_LOAD_STATUS = SLAVE_BOOT_LOAD_DONE = 1
@@ -488,7 +481,6 @@ static void espi_send_boot_load_done(void)
 	CPRINTS("eSPI Send SLAVE_BOOT_LOAD_STATUS/DONE = 1");
 }
 
-
 /*
  * Called when eSPI PLTRST# VWire de-asserts
  * Re-initialize any hardware that was reset while PLTRST# was
@@ -541,7 +533,6 @@ static void espi_host_init(void)
 	/* PC enable & Mastering enable changes */
 	MCHP_ESPI_PC_IEN = (1ul << 25) + (1ul << 28);
 
-
 	/* Sufficiently initialized */
 	lpc_set_init_done(1);
 
@@ -561,7 +552,6 @@ static void espi_host_init(void)
 }
 DECLARE_HOOK(HOOK_CHIPSET_STARTUP, espi_host_init, HOOK_PRIO_FIRST);
 
-
 /*
  * Called in response to VWire OOB_RST_WARN==1 from
  * espi_vw_evt_oob_rst_warn.
@@ -573,7 +563,6 @@ static void espi_oob_flush(void)
 {
 }
 
-
 /*
  * Called in response to VWire HOST_RST_WARN==1 from
  * espi_vw_evt_host_rst_warn.
@@ -589,13 +578,12 @@ static void espi_pc_flush(void)
 void espi_vw_power_signal_interrupt(enum espi_vw_signal signal)
 {
 	CPRINTS("eSPI power signal interrupt for VW %d", signal);
-	power_signal_interrupt((enum gpio_signal) signal);
+	power_signal_interrupt((enum gpio_signal)signal);
 }
 
 /************************************************************************/
 /* IC specific low-level driver */
 
-
 /**
  * Set eSPI Virtual-Wire signal to Host
  *
@@ -632,8 +620,8 @@ int espi_vw_set_wire(enum espi_vw_signal signal, uint8_t level)
 	}
 
 #ifdef CONFIG_MCHP_ESPI_DEBUG
-	CPRINTS("eSPI VW Set Wire %s = %d",
-		espi_vw_get_wire_name(signal), level);
+	CPRINTS("eSPI VW Set Wire %s = %d", espi_vw_get_wire_name(signal),
+		level);
 #endif
 
 	return EC_SUCCESS;
@@ -649,16 +637,14 @@ int espi_vw_set_wire(enum espi_vw_signal signal, uint8_t level)
  * happen quickly is bus is idle. Poll for hardware clearing change bit
  * until timeout.
  */
-static int espi_vw_s2m_set_w4m(uint32_t ridx, uint32_t src_num,
-		uint8_t level)
+static int espi_vw_s2m_set_w4m(uint32_t ridx, uint32_t src_num, uint8_t level)
 {
 	uint32_t i;
 
 	MCHP_ESPI_VW_S2M_SRC(ridx, src_num) = level & 0x01;
 
 	for (i = 0; i < ESPI_S2M_VW_PULSE_LOOP_CNT; i++) {
-		if ((MCHP_ESPI_VW_S2M_CHANGE(ridx) &
-		     (1u << src_num)) == 0)
+		if ((MCHP_ESPI_VW_S2M_CHANGE(ridx) & (1u << src_num)) == 0)
 			return EC_SUCCESS;
 		udelay(ESPI_S2M_VW_PULSE_LOOP_DLY_US);
 	}
@@ -699,8 +685,8 @@ int espi_vw_pulse_wire(enum espi_vw_signal signal, int pulse_level)
 		level = 1;
 
 #ifdef CONFIG_MCHP_ESPI_DEBUG
-	CPRINTS("eSPI VW Pulse Wire %s to %d",
-		espi_vw_get_wire_name(signal), level);
+	CPRINTS("eSPI VW Pulse Wire %s to %d", espi_vw_get_wire_name(signal),
+		level);
 #endif
 
 	/* set requested inactive state */
@@ -709,7 +695,7 @@ int espi_vw_pulse_wire(enum espi_vw_signal signal, int pulse_level)
 		return rc;
 
 	/* Ensure a minimum pulse width is met. */
-	udelay(CONFIG_ESPI_DEFAULT_VW_WIDTH_US);
+	udelay(CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US);
 
 	/* drive to requested active state */
 	rc = espi_vw_s2m_set_w4m(ridx, src_num, level);
@@ -741,8 +727,8 @@ int espi_vw_get_wire(enum espi_vw_signal signal)
 		src_num = vw_info_tbl[tidx].src_num;
 		vw = MCHP_ESPI_VW_M2S_SRC(ridx, src_num) & 0x01;
 #ifdef CONFIG_MCHP_ESPI_DEBUG
-		CPRINTS("VW GetWire %s = %d",
-			espi_vw_get_wire_name(signal), vw);
+		CPRINTS("VW GetWire %s = %d", espi_vw_get_wire_name(signal),
+			vw);
 #endif
 	}
 
@@ -769,8 +755,7 @@ int espi_vw_enable_wire_int(enum espi_vw_signal signal)
 		return EC_ERROR_PARAM1; /* signal is Slave-to-Master */
 
 #ifdef CONFIG_MCHP_ESPI_DEBUG
-	CPRINTS("VW IntrEn for VW[%s]",
-		espi_vw_get_wire_name(signal));
+	CPRINTS("VW IntrEn for VW[%s]", espi_vw_get_wire_name(signal));
 #endif
 
 	ridx = vw_info_tbl[tidx].reg_idx;
@@ -783,7 +768,7 @@ int espi_vw_enable_wire_int(enum espi_vw_signal signal)
 	 * GIRQ25 MSVW07[0:3] through MSVW10[0:3] (bits[0:25])
 	 */
 	MCHP_ESPI_VW_M2S_IRQSEL(ridx, src_num) =
-			MCHP_ESPI_MSVW_IRQSEL_BOTH_EDGES;
+		MCHP_ESPI_MSVW_IRQSEL_BOTH_EDGES;
 
 	girq_num = 24;
 	if (ridx > 6) {
@@ -818,8 +803,7 @@ int espi_vw_disable_wire_int(enum espi_vw_signal signal)
 		return EC_ERROR_PARAM1; /* signal is Slave-to-Master */
 
 #ifdef CONFIG_MCHP_ESPI_DEBUG
-	CPRINTS("VW IntrDis for VW[%s]",
-		espi_vw_get_wire_name(signal));
+	CPRINTS("VW IntrDis for VW[%s]", espi_vw_get_wire_name(signal));
 #endif
 
 	ridx = vw_info_tbl[tidx].reg_idx;
@@ -831,8 +815,7 @@ int espi_vw_disable_wire_int(enum espi_vw_signal signal)
 	 * GIRQ24 MSVW00[0:3] through MSVW06[0:3] (bits[0:27])
 	 * GIRQ25 MSVW07[0:3] through MSVW10[0:3] (bits[0:25])
 	 */
-	MCHP_ESPI_VW_M2S_IRQSEL(ridx, src_num) =
-			MCHP_ESPI_MSVW_IRQSEL_DISABLED;
+	MCHP_ESPI_VW_M2S_IRQSEL(ridx, src_num) = MCHP_ESPI_MSVW_IRQSEL_DISABLED;
 
 	if (ridx < 7) {
 		bpos = (ridx << 2) + src_num;
@@ -857,7 +840,6 @@ static void espi_chipset_reset(void)
 DECLARE_DEFERRED(espi_chipset_reset);
 #endif
 
-
 /* SLP_Sx event handler */
 void espi_vw_evt_slp_s3_n(uint32_t wire_state, uint32_t bpos)
 {
@@ -894,7 +876,6 @@ void espi_vw_evt_pltrst_n(uint32_t wire_state, uint32_t bpos)
 #ifdef CONFIG_CHIPSET_RESET_HOOK
 		hook_call_deferred(&espi_chipset_reset_data, MSEC);
 #endif
-
 }
 
 /* OOB Reset Warn event handler */
@@ -966,7 +947,6 @@ void espi_vw_evt_slp_lan_n(uint32_t wire_state, uint32_t bpos)
 void espi_vw_evt_slp_wlan_n(uint32_t wire_state, uint32_t bpos)
 {
 	CPRINTS("VW SLP_WLAN: %d", wire_state);
-
 }
 
 void espi_vw_evt_host_c10(uint32_t wire_state, uint32_t bpos)
@@ -1024,13 +1004,13 @@ void espi_vw_evt2_dflt(uint32_t wire_state, uint32_t bpos)
 
 typedef void (*FPVW)(uint32_t, uint32_t);
 
-#define MCHP_GIRQ24_NUM_M2S	(7 * 4)
+#define MCHP_GIRQ24_NUM_M2S (7 * 4)
 const FPVW girq24_vw_handlers[MCHP_GIRQ24_NUM_M2S] = {
-	espi_vw_evt_slp_s3_n,	/* MSVW00, Host M2S 02h */
+	espi_vw_evt_slp_s3_n, /* MSVW00, Host M2S 02h */
 	espi_vw_evt_slp_s4_n,
 	espi_vw_evt_slp_s5_n,
 	espi_vw_evt1_dflt,
-	espi_vw_evt_sus_stat_n,	/* MSVW01, Host M2S 03h */
+	espi_vw_evt_sus_stat_n, /* MSVW01, Host M2S 03h */
 	espi_vw_evt_pltrst_n,
 	espi_vw_evt_oob_rst_warn,
 	espi_vw_evt1_dflt,
@@ -1038,42 +1018,34 @@ const FPVW girq24_vw_handlers[MCHP_GIRQ24_NUM_M2S] = {
 	espi_vw_evt1_dflt,
 	espi_vw_evt1_dflt,
 	espi_vw_evt1_dflt,
-	espi_vw_evt_sus_warn_n,	/* MSVW03, Host M2S 41h */
+	espi_vw_evt_sus_warn_n, /* MSVW03, Host M2S 41h */
 	espi_vw_evt_sus_pwrdn_ack,
 	espi_vw_evt1_dflt,
 	espi_vw_evt_slp_a_n,
-	espi_vw_evt_slp_lan_n,	/* MSVW04, Host M2S 42h */
+	espi_vw_evt_slp_lan_n, /* MSVW04, Host M2S 42h */
 	espi_vw_evt_slp_wlan_n,
 	espi_vw_evt1_dflt,
 	espi_vw_evt1_dflt,
-	espi_vw_evt1_dflt,	/* MSVW05, Host M2S 43h */
+	espi_vw_evt1_dflt, /* MSVW05, Host M2S 43h */
 	espi_vw_evt1_dflt,
 	espi_vw_evt1_dflt,
 	espi_vw_evt1_dflt,
-	espi_vw_evt1_dflt,	/* MSVW06, Host M2S 44h */
+	espi_vw_evt1_dflt, /* MSVW06, Host M2S 44h */
 	espi_vw_evt1_dflt,
 	espi_vw_evt1_dflt,
 	espi_vw_evt1_dflt
 };
 
-#define MCHP_GIRQ25_NUM_M2S	(4 * 4)
+#define MCHP_GIRQ25_NUM_M2S (4 * 4)
 const FPVW girq25_vw_handlers[MCHP_GIRQ25_NUM_M2S] = {
-	espi_vw_evt_host_c10,	/* MSVW07, Host M2S 47h */
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,	/* MSVW08 unassigned */
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,	/* MSVW09 unassigned */
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,	/* MSVW10 unassigned */
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,
-	espi_vw_evt2_dflt,
+	espi_vw_evt_host_c10, /* MSVW07, Host M2S 47h */
+	espi_vw_evt2_dflt,    espi_vw_evt2_dflt, espi_vw_evt2_dflt,
+	espi_vw_evt2_dflt, /* MSVW08 unassigned */
+	espi_vw_evt2_dflt,    espi_vw_evt2_dflt, espi_vw_evt2_dflt,
+	espi_vw_evt2_dflt, /* MSVW09 unassigned */
+	espi_vw_evt2_dflt,    espi_vw_evt2_dflt, espi_vw_evt2_dflt,
+	espi_vw_evt2_dflt, /* MSVW10 unassigned */
+	espi_vw_evt2_dflt,    espi_vw_evt2_dflt, espi_vw_evt2_dflt,
 };
 
 /* Interrupt handler for eSPI virtual wires in MSVW00 - MSVW01 */
@@ -1087,8 +1059,9 @@ static void espi_mswv1_interrupt(void)
 
 	bpos = __builtin_ctz(girq24_result); /* rbit, clz sequence */
 	while (bpos != 32) {
-		d = *(uint8_t *)(MCHP_ESPI_MSVW_BASE + 8 +
-				(12 * (bpos >> 2)) + (bpos & 0x03)) & 0x01;
+		d = *(uint8_t *)(MCHP_ESPI_MSVW_BASE + 8 + (12 * (bpos >> 2)) +
+				 (bpos & 0x03)) &
+		    0x01;
 		(girq24_vw_handlers[bpos])(d, bpos);
 		girq24_result &= ~(1ul << bpos);
 		bpos = __builtin_ctz(girq24_result);
@@ -1096,7 +1069,6 @@ static void espi_mswv1_interrupt(void)
 }
 DECLARE_IRQ(MCHP_IRQ_GIRQ24, espi_mswv1_interrupt, 2);
 
-
 /* Interrupt handler for eSPI virtual wires in MSVW07 - MSVW10 */
 static void espi_msvw2_interrupt(void)
 {
@@ -1109,7 +1081,8 @@ static void espi_msvw2_interrupt(void)
 	bpos = __builtin_ctz(girq25_result); /* rbit, clz sequence */
 	while (bpos != 32) {
 		d = *(uint8_t *)(MCHP_ESPI_MSVW_BASE + (12 * 7) + 8 +
-				(12 * (bpos >> 2)) + (bpos & 0x03)) & 0x01;
+				 (12 * (bpos >> 2)) + (bpos & 0x03)) &
+		    0x01;
 		(girq25_vw_handlers[bpos])(d, bpos);
 		girq25_result &= ~(1ul << bpos);
 		bpos = __builtin_ctz(girq25_result);
@@ -1117,8 +1090,6 @@ static void espi_msvw2_interrupt(void)
 }
 DECLARE_IRQ(MCHP_IRQ_GIRQ25, espi_msvw2_interrupt, 2);
 
-
-
 /*
  * NOTES:
  * While ESPI_RESET# is asserted, all eSPI blocks are held in reset and
@@ -1167,27 +1138,21 @@ static void espi_reset_isr(void)
 	MCHP_ESPI_IO_RESET_STATUS = erst;
 	MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) = MCHP_ESPI_RESET_GIRQ_BIT;
 	if (erst & (1ul << 1)) { /* rising edge - reset de-asserted */
-		MCHP_INT_ENABLE(MCHP_ESPI_GIRQ) = (
-				MCHP_ESPI_PC_GIRQ_BIT +
-				MCHP_ESPI_OOB_TX_GIRQ_BIT +
-				MCHP_ESPI_FC_GIRQ_BIT +
-				MCHP_ESPI_VW_EN_GIRQ_BIT);
+		MCHP_INT_ENABLE(MCHP_ESPI_GIRQ) =
+			(MCHP_ESPI_PC_GIRQ_BIT + MCHP_ESPI_OOB_TX_GIRQ_BIT +
+			 MCHP_ESPI_FC_GIRQ_BIT + MCHP_ESPI_VW_EN_GIRQ_BIT);
 		MCHP_ESPI_OOB_TX_IEN = (1ul << 1);
 		MCHP_ESPI_FC_IEN = (1ul << 1);
 		MCHP_ESPI_PC_IEN = (1ul << 25);
 		CPRINTS("eSPI Reset de-assert");
 
 	} else { /* falling edge - reset asserted */
-		MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) = (
-					MCHP_ESPI_PC_GIRQ_BIT +
-					MCHP_ESPI_OOB_TX_GIRQ_BIT +
-					MCHP_ESPI_FC_GIRQ_BIT +
-					MCHP_ESPI_VW_EN_GIRQ_BIT);
-		MCHP_INT_DISABLE(MCHP_ESPI_GIRQ) = (
-					MCHP_ESPI_PC_GIRQ_BIT +
-					MCHP_ESPI_OOB_TX_GIRQ_BIT +
-					MCHP_ESPI_FC_GIRQ_BIT +
-					MCHP_ESPI_VW_EN_GIRQ_BIT);
+		MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) =
+			(MCHP_ESPI_PC_GIRQ_BIT + MCHP_ESPI_OOB_TX_GIRQ_BIT +
+			 MCHP_ESPI_FC_GIRQ_BIT + MCHP_ESPI_VW_EN_GIRQ_BIT);
+		MCHP_INT_DISABLE(MCHP_ESPI_GIRQ) =
+			(MCHP_ESPI_PC_GIRQ_BIT + MCHP_ESPI_OOB_TX_GIRQ_BIT +
+			 MCHP_ESPI_FC_GIRQ_BIT + MCHP_ESPI_VW_EN_GIRQ_BIT);
 		espi_channels_ready = 0;
 
 		chipset_handle_espi_reset_assert();
@@ -1217,7 +1182,6 @@ static void espi_vw_en_isr(void)
 }
 DECLARE_IRQ(MCHP_IRQ_ESPI_VW_EN, espi_vw_en_isr, 2);
 
-
 /*
  * eSPI OOB TX and OOB channel enable change interrupt handler
  */
@@ -1246,7 +1210,6 @@ static void espi_oob_tx_isr(void)
 }
 DECLARE_IRQ(MCHP_IRQ_ESPI_OOB_UP, espi_oob_tx_isr, 2);
 
-
 /* eSPI OOB RX interrupt handler */
 static void espi_oob_rx_isr(void)
 {
@@ -1260,7 +1223,6 @@ static void espi_oob_rx_isr(void)
 }
 DECLARE_IRQ(MCHP_IRQ_ESPI_OOB_DN, espi_oob_rx_isr, 2);
 
-
 /*
  * eSPI Flash Channel enable change and data transfer
  * interrupt handler
@@ -1291,7 +1253,6 @@ static void espi_fc_isr(void)
 }
 DECLARE_IRQ(MCHP_IRQ_ESPI_FC, espi_fc_isr, 2);
 
-
 /* eSPI Peripheral Channel interrupt handler */
 static void espi_pc_isr(void)
 {
@@ -1317,7 +1278,6 @@ static void espi_pc_isr(void)
 }
 DECLARE_IRQ(MCHP_IRQ_ESPI_PC, espi_pc_isr, 2);
 
-
 /************************************************************************/
 
 /*
@@ -1328,25 +1288,21 @@ static void espi_reset_ictrl(int enable, int clr_status)
 {
 	if (enable) {
 		if (clr_status) {
-			MCHP_ESPI_IO_RESET_STATUS =
-					MCHP_ESPI_RST_CHG_STS;
+			MCHP_ESPI_IO_RESET_STATUS = MCHP_ESPI_RST_CHG_STS;
 			MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) =
-					MCHP_ESPI_RESET_GIRQ_BIT;
+				MCHP_ESPI_RESET_GIRQ_BIT;
 		}
 		MCHP_ESPI_IO_RESET_IEN |= MCHP_ESPI_RST_IEN;
-		MCHP_INT_ENABLE(MCHP_ESPI_GIRQ) =
-				MCHP_ESPI_RESET_GIRQ_BIT;
+		MCHP_INT_ENABLE(MCHP_ESPI_GIRQ) = MCHP_ESPI_RESET_GIRQ_BIT;
 		task_enable_irq(MCHP_IRQ_ESPI_RESET);
 	} else {
 		task_disable_irq(MCHP_IRQ_ESPI_RESET);
-		MCHP_INT_DISABLE(MCHP_ESPI_GIRQ) =
-				MCHP_ESPI_RESET_GIRQ_BIT;
+		MCHP_INT_DISABLE(MCHP_ESPI_GIRQ) = MCHP_ESPI_RESET_GIRQ_BIT;
 		MCHP_ESPI_IO_RESET_IEN &= ~(MCHP_ESPI_RST_IEN);
 		if (clr_status) {
-			MCHP_ESPI_IO_RESET_STATUS =
-					MCHP_ESPI_RST_CHG_STS;
+			MCHP_ESPI_IO_RESET_STATUS = MCHP_ESPI_RST_CHG_STS;
 			MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) =
-					MCHP_ESPI_RESET_GIRQ_BIT;
+				MCHP_ESPI_RESET_GIRQ_BIT;
 		}
 	}
 }
@@ -1379,15 +1335,15 @@ void espi_init(void)
 	gpio_config_module(MODULE_LPC, 1);
 
 	/* Set channel */
-	MCHP_ESPI_IO_CAP0 = CONFIG_HOSTCMD_ESPI_EC_CHAN_BITMAP;
+	MCHP_ESPI_IO_CAP0 = CONFIG_HOST_INTERFACE_ESPI_EC_CHAN_BITMAP;
 
 	/* Set eSPI frequency & mode */
-	MCHP_ESPI_IO_CAP1 = (MCHP_ESPI_IO_CAP1 &
-				(~(MCHP_ESPI_CAP1_MAX_FREQ_MASK |
-				MCHP_ESPI_CAP1_IO_MASK))) |
-				CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ |
-				(CONFIG_HOSTCMD_ESPI_EC_MODE
-				<< MCHP_ESPI_CAP1_IO_BITPOS);
+	MCHP_ESPI_IO_CAP1 =
+		(MCHP_ESPI_IO_CAP1 &
+		 (~(MCHP_ESPI_CAP1_MAX_FREQ_MASK | MCHP_ESPI_CAP1_IO_MASK))) |
+		CONFIG_HOST_INTERFACE_ESPI_EC_MAX_FREQ |
+		(CONFIG_HOST_INTERFACE_ESPI_EC_MODE
+		 << MCHP_ESPI_CAP1_IO_BITPOS);
 
 #ifdef CONFIG_HOST_INTERFACE_ESPI
 	MCHP_ESPI_IO_PLTRST_SRC = MCHP_ESPI_PLTRST_SRC_VW;
@@ -1395,8 +1351,7 @@ void espi_init(void)
 	MCHP_ESPI_IO_PLTRST_SRC = MCHP_ESPI_PLTRST_SRC_PIN;
 #endif
 
-	MCHP_PCR_PWR_RST_CTL &=
-		~(1ul << MCHP_PCR_PWR_HOST_RST_SEL_BITPOS);
+	MCHP_PCR_PWR_RST_CTL &= ~(1ul << MCHP_PCR_PWR_HOST_RST_SEL_BITPOS);
 
 	MCHP_ESPI_ACTIVATE = 1;
 
@@ -1443,16 +1398,15 @@ void espi_init(void)
 	CPRINTS("eSPI - espi_init - done");
 }
 
-
 #ifdef CONFIG_MCHP_ESPI_EC_CMD
-static int command_espi(int argc, char **argv)
+static int command_espi(int argc, const char **argv)
 {
 	uint32_t chan, w0, w1, w2;
 	char *e;
 
 	if (argc == 1) {
 		return EC_ERROR_INVAL;
-	/* Get value of eSPI registers */
+		/* Get value of eSPI registers */
 	} else if (argc == 2) {
 		int i;
 
@@ -1470,8 +1424,8 @@ static int command_espi(int argc, char **argv)
 				w0 = MSVW(i, 0);
 				w1 = MSVW(i, 1);
 				w2 = MSVW(i, 2);
-				ccprintf("MSVW%d: 0x%08x:%08x:%08x\n", i,
-					w2, w1, w0);
+				ccprintf("MSVW%d: 0x%08x:%08x:%08x\n", i, w2,
+					 w1, w0);
 			}
 		} else if (strcasecmp(argv[1], "vms") == 0) {
 			for (i = 0; i < SMVW_MAX; i++) {
@@ -1480,9 +1434,9 @@ static int command_espi(int argc, char **argv)
 				ccprintf("SMVW%d: 0x%08x:%08x\n", i, w1, w0);
 			}
 		}
-	/* Enable/Disable the channels of eSPI */
+		/* Enable/Disable the channels of eSPI */
 	} else if (argc == 3) {
-		uint32_t m = (uint32_t) strtoi(argv[2], &e, 0);
+		uint32_t m = (uint32_t)strtoi(argv[2], &e, 0);
 
 		if (*e)
 			return EC_ERROR_PARAM2;
@@ -1502,7 +1456,6 @@ static int command_espi(int argc, char **argv)
 	}
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(espi, command_espi,
-			"cfg/vms/vsm/en/dis [channel]",
+DECLARE_CONSOLE_COMMAND(espi, command_espi, "cfg/vms/vsm/en/dis [channel]",
 			"eSPI configurations");
 #endif
diff --git a/chip/mchp/fan.c b/chip/mchp/fan.c
index 17b60b703d..3f61cb4d2f 100644
--- a/chip/mchp/fan.c
+++ b/chip/mchp/fan.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -38,7 +38,6 @@ static int rpm_setting;
 static int duty_setting;
 static int in_rpm_mode = 1;
 
-
 static void clear_status(void)
 {
 	/* Clear DRIVE_FAIL, FAN_SPIN, and FAN_STALL bits */
@@ -78,14 +77,14 @@ void fan_set_duty(int ch, int percent)
 
 	duty_setting = percent;
 	MCHP_FAN_SETTING(0) = (percent * MAX_FAN_DRIVER_SETTING / 100)
-		<< FAN_DRIVER_SETTING_SHIFT;
+			      << FAN_DRIVER_SETTING_SHIFT;
 	clear_status();
 }
 
 int fan_get_duty(int ch)
 {
-	duty_setting = (MCHP_FAN_SETTING(0) >> FAN_DRIVER_SETTING_SHIFT)
-		* 100 / MAX_FAN_DRIVER_SETTING;
+	duty_setting = (MCHP_FAN_SETTING(0) >> FAN_DRIVER_SETTING_SHIFT) * 100 /
+		       MAX_FAN_DRIVER_SETTING;
 	return duty_setting;
 }
 
diff --git a/chip/mchp/flash.c b/chip/mchp/flash.c
index 1679cf92cb..4b0e407fb2 100644
--- a/chip/mchp/flash.c
+++ b/chip/mchp/flash.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -55,7 +55,7 @@ int crec_flash_physical_read(int offset, int size, char *data)
 int crec_flash_physical_write(int offset, int size, const char *data)
 {
 	int ret = EC_SUCCESS;
-	int  i, write_size;
+	int i, write_size;
 
 	trace13(0, FLASH, 0,
 		"flash_phys_write: offset=0x%08X size=0x%08X dataptr=0x%08X",
@@ -70,8 +70,7 @@ int crec_flash_physical_write(int offset, int size, const char *data)
 
 	for (i = 0; i < size; i += write_size) {
 		write_size = MIN((size - i), SPI_FLASH_MAX_WRITE_SIZE);
-		ret = spi_flash_write(offset + i,
-				      write_size,
+		ret = spi_flash_write(offset + i, write_size,
 				      (uint8_t *)data + i);
 		if (ret != EC_SUCCESS)
 			break;
@@ -94,8 +93,7 @@ int crec_flash_physical_erase(int offset, int size)
 	if (entire_flash_locked)
 		return EC_ERROR_ACCESS_DENIED;
 
-	trace12(0, FLASH, 0,
-		"flash_phys_erase: offset=0x%08X size=0x%08X",
+	trace12(0, FLASH, 0, "flash_phys_erase: offset=0x%08X size=0x%08X",
 		offset, size);
 	ret = spi_flash_erase(offset, size);
 	return ret;
@@ -110,7 +108,7 @@ int crec_flash_physical_erase(int offset, int size)
 int crec_flash_physical_get_protect(int bank)
 {
 	return spi_flash_check_protect(bank * CONFIG_FLASH_BANK_SIZE,
-			CONFIG_FLASH_BANK_SIZE);
+				       CONFIG_FLASH_BANK_SIZE);
 }
 
 /**
@@ -164,8 +162,7 @@ uint32_t crec_flash_physical_get_protect_flags(void)
  */
 uint32_t crec_flash_physical_get_valid_flags(void)
 {
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-	       EC_FLASH_PROTECT_RO_NOW |
+	return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW |
 	       EC_FLASH_PROTECT_ALL_NOW;
 }
 
@@ -182,8 +179,9 @@ uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
 
 	wp_status = spi_flash_check_wp();
 
-	if (wp_status == SPI_WP_NONE || (wp_status == SPI_WP_HARDWARE &&
-	   !(cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED)))
+	if (wp_status == SPI_WP_NONE ||
+	    (wp_status == SPI_WP_HARDWARE &&
+	     !(cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED)))
 		ret = EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW;
 
 	if (!entire_flash_locked)
@@ -253,7 +251,7 @@ int crec_flash_physical_restore_state(void)
 	 */
 	if (reset_flags & EC_RESET_FLAG_SYSJUMP) {
 		prev = (const struct flash_wp_state *)system_get_jump_tag(
-				FLASH_SYSJUMP_TAG, &version, &size);
+			FLASH_SYSJUMP_TAG, &version, &size);
 		if (prev && version == FLASH_HOOK_VERSION &&
 		    size == sizeof(*prev))
 			entire_flash_locked = prev->entire_flash_locked;
diff --git a/chip/mchp/gpio.c b/chip/mchp/gpio.c
index 5794229b34..a3cab86fcc 100644
--- a/chip/mchp/gpio.c
+++ b/chip/mchp/gpio.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,8 +18,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
-
+#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args)
 
 struct gpio_int_mapping {
 	int8_t girq_id;
@@ -38,10 +37,9 @@ struct gpio_int_mapping {
  * 4		0200 - 0235	12
  * 5		0240 - 0276	26
  */
-static const struct gpio_int_mapping int_map[] = {
-	{ 11, 0 }, { 10, 1 }, { 9, 2 },
-	{ 8, 3 }, { 12, 4 }, { 26, 5 }
-};
+static const struct gpio_int_mapping int_map[] = { { 11, 0 }, { 10, 1 },
+						   { 9, 2 },  { 8, 3 },
+						   { 12, 4 }, { 26, 5 } };
 BUILD_ASSERT(ARRAY_SIZE(int_map) == MCHP_GPIO_MAX_PORT);
 
 /*
@@ -98,7 +96,7 @@ static void disable_bgpo(uint32_t port, uint32_t mask)
  * 1-bit of val or if val == 0 returns 0
  */
 void gpio_set_alternate_function(uint32_t port, uint32_t mask,
-				enum gpio_alternate_func func)
+				 enum gpio_alternate_func func)
 {
 	int i;
 	uint32_t val;
@@ -171,16 +169,16 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
 
 #ifdef CONFIG_GPIO_POWER_DOWN
 		if (flags & GPIO_POWER_DOWN) {
-			val = (MCHP_GPIO_CTRL_PWR_OFF
-				| MCHP_GPIO_INTDET_DISABLED
-				| MCHP_GPIO_CTRL_DIS_INPUT_BIT);
+			val = (MCHP_GPIO_CTRL_PWR_OFF |
+			       MCHP_GPIO_INTDET_DISABLED |
+			       MCHP_GPIO_CTRL_DIS_INPUT_BIT);
 
 			MCHP_GPIO_CTL(port, i) = val;
 			continue;
 		}
 #endif
-		val &= ~(MCHP_GPIO_CTRL_PWR_MASK
-			| MCHP_GPIO_CTRL_DIS_INPUT_BIT);
+		val &= ~(MCHP_GPIO_CTRL_PWR_MASK |
+			 MCHP_GPIO_CTRL_DIS_INPUT_BIT);
 
 		val |= MCHP_GPIO_CTRL_PWR_VTR;
 		/*
@@ -253,9 +251,9 @@ void gpio_power_off_by_mask(uint32_t port, uint32_t mask)
 	while (mask) {
 		i = GPIO_MASK_TO_NUM(mask);
 		mask &= ~BIT(i);
-		MCHP_GPIO_CTL(port, i) = (MCHP_GPIO_CTRL_PWR_OFF
-					| MCHP_GPIO_INTDET_DISABLED
-					| MCHP_GPIO_CTRL_DIS_INPUT_BIT);
+		MCHP_GPIO_CTL(port, i) =
+			(MCHP_GPIO_CTRL_PWR_OFF | MCHP_GPIO_INTDET_DISABLED |
+			 MCHP_GPIO_CTRL_DIS_INPUT_BIT);
 	}
 }
 
@@ -268,9 +266,9 @@ int gpio_power_off(enum gpio_signal signal)
 
 	i = GPIO_MASK_TO_NUM(gpio_list[signal].mask);
 	port = gpio_list[signal].port;
-	MCHP_GPIO_CTL(port, i) = (MCHP_GPIO_CTRL_PWR_OFF
-				| MCHP_GPIO_INTDET_DISABLED
-				| MCHP_GPIO_CTRL_DIS_INPUT_BIT);
+	MCHP_GPIO_CTL(port, i) =
+		(MCHP_GPIO_CTRL_PWR_OFF | MCHP_GPIO_INTDET_DISABLED |
+		 MCHP_GPIO_CTRL_DIS_INPUT_BIT);
 
 	return EC_SUCCESS;
 }
@@ -313,7 +311,6 @@ int gpio_disable_interrupt(enum gpio_signal signal)
 	port = gpio_list[signal].port;
 	girq_id = int_map[port].girq_id;
 
-
 	MCHP_INT_DISABLE(girq_id) = BIT(i);
 
 	return EC_SUCCESS;
@@ -369,7 +366,6 @@ void gpio_pre_init(void)
 	int is_warm = system_is_reboot_warm();
 	const struct gpio_info *g = gpio_list;
 
-
 	for (i = 0; i < GPIO_COUNT; i++, g++) {
 		flags = g->flags;
 
@@ -389,7 +385,7 @@ void gpio_pre_init(void)
 
 		/* Use as GPIO, not alternate function */
 		gpio_set_alternate_function(g->port, g->mask,
-					GPIO_ALT_FUNC_NONE);
+					    GPIO_ALT_FUNC_NONE);
 	}
 }
 
@@ -405,14 +401,13 @@ void gpio_pre_init(void)
  *    assumption for the GPIO's that have been enabled.
  * 2. Clear NVIC pending to prevent ISR firing on false edge.
  */
-#define ENABLE_GPIO_GIRQ(x) \
-	do { \
-		MCHP_INT_SOURCE(x) = 0xfffffffful; \
-		task_clear_pending_irq(MCHP_IRQ_GIRQ ## x); \
-		task_enable_irq(MCHP_IRQ_GIRQ ## x); \
+#define ENABLE_GPIO_GIRQ(x)                               \
+	do {                                              \
+		MCHP_INT_SOURCE(x) = 0xfffffffful;        \
+		task_clear_pending_irq(MCHP_IRQ_GIRQ##x); \
+		task_enable_irq(MCHP_IRQ_GIRQ##x);        \
 	} while (0)
 
-
 static void gpio_init(void)
 {
 	ENABLE_GPIO_GIRQ(8);
@@ -427,7 +422,6 @@ DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
 /************************************************************************/
 /* Interrupt handlers */
 
-
 /**
  * Handler for each GIRQ interrupt. This reads and clears the interrupt
  * bits for the GIRQ interrupt, then finds and calls the corresponding
@@ -448,8 +442,8 @@ static void gpio_interrupt(int girq, int port)
 	MCHP_INT_SOURCE(girq) = sts;
 
 	trace12(0, GPIO, 0, "GPIO GIRQ %d result = 0x%08x", girq, sts);
-	trace12(0, GPIO, 0, "GPIO ParIn[%d]      = 0x%08x",
-		port, MCHP_GPIO_PARIN(port));
+	trace12(0, GPIO, 0, "GPIO ParIn[%d]      = 0x%08x", port,
+		MCHP_GPIO_PARIN(port));
 
 	for (i = 0; (i < GPIO_IH_COUNT) && sts; ++i, ++g) {
 		if (g->port != port)
@@ -459,9 +453,8 @@ static void gpio_interrupt(int girq, int port)
 		if (bit) {
 			bit--;
 			if (sts & BIT(bit)) {
-				trace12(0, GPIO, 0,
-					"Bit[%d]: handler @ 0x%08x", bit,
-					(uint32_t)gpio_irq_handlers[i]);
+				trace12(0, GPIO, 0, "Bit[%d]: handler @ 0x%08x",
+					bit, (uint32_t)gpio_irq_handlers[i]);
 				gpio_irq_handlers[i](i);
 			}
 			sts &= ~BIT(bit);
@@ -469,10 +462,10 @@ static void gpio_interrupt(int girq, int port)
 	}
 }
 
-#define GPIO_IRQ_FUNC(irqfunc, girq, port)\
-	static void irqfunc(void) \
-	{ \
-		gpio_interrupt(girq, port);\
+#define GPIO_IRQ_FUNC(irqfunc, girq, port)  \
+	static void irqfunc(void)           \
+	{                                   \
+		gpio_interrupt(girq, port); \
 	}
 
 GPIO_IRQ_FUNC(__girq_8_interrupt, 8, 3);
diff --git a/chip/mchp/gpio_chip.h b/chip/mchp/gpio_chip.h
index 53723cfd80..e092669b60 100644
--- a/chip/mchp/gpio_chip.h
+++ b/chip/mchp/gpio_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/chip/mchp/gpio_cmds.c b/chip/mchp/gpio_cmds.c
index 7263909c9c..927d6d0326 100644
--- a/chip/mchp/gpio_cmds.c
+++ b/chip/mchp/gpio_cmds.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,11 +17,9 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args)
 
-
-
-static int cmd_gp_get_config(int argc, char **argv)
+static int cmd_gp_get_config(int argc, const char **argv)
 {
 	char *e;
 	int i;
@@ -43,7 +41,7 @@ static int cmd_gp_get_config(int argc, char **argv)
 	} else { /* Otherwise print them all */
 		for (i = 0; i < GPIO_COUNT; i++) {
 			if (!gpio_is_implemented(i))
-				continue;  /* Skip unsupported signals */
+				continue; /* Skip unsupported signals */
 
 			gctrl = MCHP_GPIO_CTRL(i);
 
@@ -56,11 +54,10 @@ static int cmd_gp_get_config(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(gpgetcfg, cmd_gp_get_config,
-			"[number]",
+DECLARE_CONSOLE_COMMAND(gpgetcfg, cmd_gp_get_config, "[number]",
 			"Read GPIO config");
 
-static int cmd_gp_set_config(int argc, char **argv)
+static int cmd_gp_set_config(int argc, const char **argv)
 {
 	char *e;
 	int i;
@@ -91,6 +88,5 @@ static int cmd_gp_set_config(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(gpsetcfg, cmd_gp_set_config,
-			"gp_num val",
+DECLARE_CONSOLE_COMMAND(gpsetcfg, cmd_gp_set_config, "gp_num val",
 			"Set GPIO config");
diff --git a/chip/mchp/gpspi.c b/chip/mchp/gpspi.c
index c92813b300..0142fe0e3c 100644
--- a/chip/mchp/gpspi.c
+++ b/chip/mchp/gpspi.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,7 +20,7 @@
 #include "tfdp_chip.h"
 
 #define CPUTS(outstr) cputs(CC_SPI, outstr)
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SPI, format, ##args)
 
 #define SPI_BYTE_TRANSFER_TIMEOUT_US (3 * MSEC)
 /* One byte at 12 MHz full duplex = 0.67 us */
@@ -91,8 +91,8 @@ static int gpspi_tx(const int ctrl, const uint8_t *txdata, int txlen)
 #endif
 
 int gpspi_transaction_async(const struct spi_device_t *spi_device,
-				const uint8_t *txdata, int txlen,
-				uint8_t *rxdata, int rxlen)
+			    const uint8_t *txdata, int txlen, uint8_t *rxdata,
+			    int rxlen)
 {
 	int hw_port, ctrl;
 	int ret = EC_SUCCESS;
@@ -232,7 +232,6 @@ int gpspi_enable(int hw_port, int enable)
 	ctrl = (uint32_t)hw_port & 0x0f;
 
 	if (enable) {
-
 		if (ctrl)
 			MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_GPSPI1);
 		else
diff --git a/chip/mchp/gpspi_chip.h b/chip/mchp/gpspi_chip.h
index b48aec0976..7c1285b6cf 100644
--- a/chip/mchp/gpspi_chip.h
+++ b/chip/mchp/gpspi_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -24,8 +24,8 @@ int gpspi_transaction_flush(const struct spi_device_t *spi_device);
 int gpspi_transaction_wait(const struct spi_device_t *spi_device);
 
 int gpspi_transaction_async(const struct spi_device_t *spi_device,
-				const uint8_t *txdata, int txlen,
-				uint8_t *rxdata, int rxlen);
+			    const uint8_t *txdata, int txlen, uint8_t *rxdata,
+			    int rxlen);
 
 int gpspi_enable(int port, int enable);
 
diff --git a/chip/mchp/hwtimer.c b/chip/mchp/hwtimer.c
index 05ff69e7d9..2e9ff780fb 100644
--- a/chip/mchp/hwtimer.c
+++ b/chip/mchp/hwtimer.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,8 +16,7 @@
 
 void __hw_clock_event_set(uint32_t deadline)
 {
-	MCHP_TMR32_CNT(1) = MCHP_TMR32_CNT(0) -
-			       (0xffffffff - deadline);
+	MCHP_TMR32_CNT(1) = MCHP_TMR32_CNT(0) - (0xffffffff - deadline);
 	MCHP_TMR32_CTL(1) |= BIT(5);
 }
 
@@ -49,16 +48,21 @@ void __hw_clock_source_set(uint32_t ts)
 static void __hw_clock_source_irq(int timer_id)
 {
 	MCHP_TMR32_STS(timer_id & 0x01) |= 1;
-	MCHP_INT_SOURCE(MCHP_TMR32_GIRQ) =
-			MCHP_TMR32_GIRQ_BIT(timer_id & 0x01);
+	MCHP_INT_SOURCE(MCHP_TMR32_GIRQ) = MCHP_TMR32_GIRQ_BIT(timer_id & 0x01);
 
 	/* If IRQ is from timer 0, 32-bit timer overflowed */
 	process_timers(timer_id == 0);
 }
 
-static void __hw_clock_source_irq_0(void) { __hw_clock_source_irq(0); }
+static void __hw_clock_source_irq_0(void)
+{
+	__hw_clock_source_irq(0);
+}
 DECLARE_IRQ(MCHP_IRQ_TIMER32_0, __hw_clock_source_irq_0, 1);
-static void __hw_clock_source_irq_1(void) { __hw_clock_source_irq(1); }
+static void __hw_clock_source_irq_1(void)
+{
+	__hw_clock_source_irq(1);
+}
 DECLARE_IRQ(MCHP_IRQ_TIMER32_1, __hw_clock_source_irq_1, 1);
 
 static void configure_timer(int timer_id)
@@ -88,7 +92,7 @@ static void configure_timer(int timer_id)
 int __hw_clock_source_init(uint32_t start_t)
 {
 	MCHP_PCR_SLP_DIS_DEV_MASK(3, MCHP_PCR_SLP_EN3_BTMR32_0 +
-			MCHP_PCR_SLP_EN3_BTMR32_1);
+					     MCHP_PCR_SLP_EN3_BTMR32_1);
 
 	/*
 	 * The timer can only fire interrupt when its value reaches zero.
@@ -111,8 +115,8 @@ int __hw_clock_source_init(uint32_t start_t)
 	/* Enable interrupt */
 	task_enable_irq(MCHP_IRQ_TIMER32_0);
 	task_enable_irq(MCHP_IRQ_TIMER32_1);
-	MCHP_INT_ENABLE(MCHP_TMR32_GIRQ) = MCHP_TMR32_GIRQ_BIT(0) +
-			MCHP_TMR32_GIRQ_BIT(1);
+	MCHP_INT_ENABLE(MCHP_TMR32_GIRQ) =
+		MCHP_TMR32_GIRQ_BIT(0) + MCHP_TMR32_GIRQ_BIT(1);
 	/*
 	 * Not needed when using direct mode interrupts
 	 * MCHP_INT_BLK_EN |= BIT(MCHP_TMR32_GIRQ);
diff --git a/chip/mchp/i2c.c b/chip/mchp/i2c.c
index 2aaef83dfe..2b21d17dc4 100644
--- a/chip/mchp/i2c.c
+++ b/chip/mchp/i2c.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,77 +24,77 @@
 /*
  * MCHP I2C BAUD clock source is 16 MHz.
  */
-#define I2C_CLOCK			16000000UL
-#define MCHP_I2C_SUPPORTED_BUS_CLOCKS	6
+#define I2C_CLOCK 16000000UL
+#define MCHP_I2C_SUPPORTED_BUS_CLOCKS 6
 
 /* SMBus Timing values for 1MHz Speed */
-#define SPEED_1MHZ_BUS_CLOCK		0x0509ul
-#define SPEED_1MHZ_DATA_TIMING		0x06060601ul
-#define SPEED_1MHZ_DATA_TIMING_2	0x06ul
-#define SPEED_1MHZ_IDLE_SCALING		0x01000050ul
-#define SPEED_1MHZ_TIMEOUT_SCALING	0x149CC2C7ul
+#define SPEED_1MHZ_BUS_CLOCK 0x0509ul
+#define SPEED_1MHZ_DATA_TIMING 0x06060601ul
+#define SPEED_1MHZ_DATA_TIMING_2 0x06ul
+#define SPEED_1MHZ_IDLE_SCALING 0x01000050ul
+#define SPEED_1MHZ_TIMEOUT_SCALING 0x149CC2C7ul
 /* SMBus Timing values for 400kHz speed */
-#define SPEED_400KHZ_BUS_CLOCK		0x0F17ul
-#define SPEED_400KHZ_DATA_TIMING	0x040A0F01ul
-#define SPEED_400KHZ_DATA_TIMING_2	0x0Aul
-#define SPEED_400KHZ_IDLE_SCALING	0x01000050ul
-#define SPEED_400KHZ_TIMEOUT_SCALING	0x149CC2C7ul
+#define SPEED_400KHZ_BUS_CLOCK 0x0F17ul
+#define SPEED_400KHZ_DATA_TIMING 0x040A0F01ul
+#define SPEED_400KHZ_DATA_TIMING_2 0x0Aul
+#define SPEED_400KHZ_IDLE_SCALING 0x01000050ul
+#define SPEED_400KHZ_TIMEOUT_SCALING 0x149CC2C7ul
 /* SMBus Timing values for 100kHz speed */
-#define SPEED_100KHZ_BUS_CLOCK		0x4F4Ful
-#define SPEED_100KHZ_DATA_TIMING	0x0C4D4306ul
-#define SPEED_100KHZ_DATA_TIMING_2	0x4Dul
-#define SPEED_100KHZ_IDLE_SCALING	0x01FC01EDul
-#define SPEED_100KHZ_TIMEOUT_SCALING	0x4B9CC2C7ul
+#define SPEED_100KHZ_BUS_CLOCK 0x4F4Ful
+#define SPEED_100KHZ_DATA_TIMING 0x0C4D4306ul
+#define SPEED_100KHZ_DATA_TIMING_2 0x4Dul
+#define SPEED_100KHZ_IDLE_SCALING 0x01FC01EDul
+#define SPEED_100KHZ_TIMEOUT_SCALING 0x4B9CC2C7ul
 /* Bus clock dividers for 333, 80, and 40 kHz */
-#define SPEED_333KHZ_BUS_CLOCK		0x0F1Ful
-#define SPEED_80KHZ_BUS_CLOCK		0x6363ul
-#define SPEED_40KHZ_BUS_CLOCK		0xC7C7ul
+#define SPEED_333KHZ_BUS_CLOCK 0x0F1Ful
+#define SPEED_80KHZ_BUS_CLOCK 0x6363ul
+#define SPEED_40KHZ_BUS_CLOCK 0xC7C7ul
 
 /* Status */
-#define STS_NBB			BIT(0) /* Bus busy */
-#define STS_LAB			BIT(1) /* Arbitration lost */
-#define STS_LRB			BIT(3) /* Last received bit */
-#define STS_BER			BIT(4) /* Bus error */
-#define STS_PIN			BIT(7) /* Pending interrupt */
+#define STS_NBB BIT(0) /* Bus busy */
+#define STS_LAB BIT(1) /* Arbitration lost */
+#define STS_LRB BIT(3) /* Last received bit */
+#define STS_BER BIT(4) /* Bus error */
+#define STS_PIN BIT(7) /* Pending interrupt */
 /* Control */
-#define CTRL_ACK		BIT(0) /* Acknowledge */
-#define CTRL_STO		BIT(1) /* STOP */
-#define CTRL_STA		BIT(2) /* START */
-#define CTRL_ENI		BIT(3) /* Enable interrupt */
-#define CTRL_ESO		BIT(6) /* Enable serial output */
-#define CTRL_PIN		BIT(7) /* Pending interrupt not */
+#define CTRL_ACK BIT(0) /* Acknowledge */
+#define CTRL_STO BIT(1) /* STOP */
+#define CTRL_STA BIT(2) /* START */
+#define CTRL_ENI BIT(3) /* Enable interrupt */
+#define CTRL_ESO BIT(6) /* Enable serial output */
+#define CTRL_PIN BIT(7) /* Pending interrupt not */
 /* Completion */
-#define COMP_DTEN		BIT(2) /* enable device timeouts */
-#define COMP_MCEN		BIT(3) /* enable ctrl. cumulative timeouts */
-#define COMP_SCEN		BIT(4) /* enable periph. cumulative timeouts */
-#define COMP_BIDEN		BIT(5) /* enable Bus idle timeouts */
-#define COMP_IDLE		BIT(29) /* i2c bus is idle */
-#define COMP_RW_BITS_MASK	0x3C /* R/W bits mask */
+#define COMP_DTEN BIT(2) /* enable device timeouts */
+#define COMP_MCEN BIT(3) /* enable ctrl. cumulative timeouts */
+#define COMP_SCEN BIT(4) /* enable periph. cumulative timeouts */
+#define COMP_BIDEN BIT(5) /* enable Bus idle timeouts */
+#define COMP_IDLE BIT(29) /* i2c bus is idle */
+#define COMP_RW_BITS_MASK 0x3C /* R/W bits mask */
 /* Configuration */
-#define CFG_PORT_MASK		(0x0F) /* port selection field */
-#define CFG_TCEN		BIT(4) /* Enable HW bus timeouts */
-#define CFG_FEN			BIT(8) /* enable input filtering */
-#define CFG_RESET		BIT(9) /* reset controller */
-#define CFG_ENABLE		BIT(10) /* enable controller */
-#define CFG_GC_DIS		BIT(14) /* disable general call address */
-#define CFG_ENIDI		BIT(29) /* Enable I2C idle interrupt */
+#define CFG_PORT_MASK (0x0F) /* port selection field */
+#define CFG_TCEN BIT(4) /* Enable HW bus timeouts */
+#define CFG_FEN BIT(8) /* enable input filtering */
+#define CFG_RESET BIT(9) /* reset controller */
+#define CFG_ENABLE BIT(10) /* enable controller */
+#define CFG_GC_DIS BIT(14) /* disable general call address */
+#define CFG_ENIDI BIT(29) /* Enable I2C idle interrupt */
 /* Enable network layer controller done interrupt */
-#define CFG_ENMI		BIT(30)
+#define CFG_ENMI BIT(30)
 /* Enable network layer peripheral done interrupt */
-#define CFG_ENSI		BIT(31)
+#define CFG_ENSI BIT(31)
 /* Controller Command */
-#define MCMD_MRUN		BIT(0)
-#define MCMD_MPROCEED		BIT(1)
-#define MCMD_START0		BIT(8)
-#define MCMD_STARTN		BIT(9)
-#define MCMD_STOP		BIT(10)
-#define MCMD_READM		BIT(12)
-#define MCMD_WCNT_BITPOS	(16)
-#define MCMD_WCNT_MASK0		(0xFF)
-#define MCMD_WCNT_MASK		(0xFF << 16)
-#define MCMD_RCNT_BITPOS	(24)
-#define MCMD_RCNT_MASK0		(0xFF)
-#define MCMD_RCNT_MASK		(0xFF << 24)
+#define MCMD_MRUN BIT(0)
+#define MCMD_MPROCEED BIT(1)
+#define MCMD_START0 BIT(8)
+#define MCMD_STARTN BIT(9)
+#define MCMD_STOP BIT(10)
+#define MCMD_READM BIT(12)
+#define MCMD_WCNT_BITPOS (16)
+#define MCMD_WCNT_MASK0 (0xFF)
+#define MCMD_WCNT_MASK (0xFF << 16)
+#define MCMD_RCNT_BITPOS (24)
+#define MCMD_RCNT_MASK0 (0xFF)
+#define MCMD_RCNT_MASK (0xFF << 24)
 
 /* Maximum transfer of a SMBUS block transfer */
 #define SMBUS_MAX_BLOCK_SIZE 32
@@ -146,34 +146,37 @@ static struct {
 	uint8_t lines;
 } cdata[I2C_CONTROLLER_COUNT];
 
-static const uint16_t i2c_ctrl_nvic_id[] = {
-	MCHP_IRQ_I2C_0, MCHP_IRQ_I2C_1, MCHP_IRQ_I2C_2, MCHP_IRQ_I2C_3,
+static const uint16_t i2c_ctrl_nvic_id[] = { MCHP_IRQ_I2C_0, MCHP_IRQ_I2C_1,
+					     MCHP_IRQ_I2C_2, MCHP_IRQ_I2C_3,
 #if defined(CHIP_FAMILY_MEC172X)
-	MCHP_IRQ_I2C_4
+					     MCHP_IRQ_I2C_4
 #elif defined(CHIP_FAMILY_MEC152X)
-	MCHP_IRQ_I2C_4, MCHP_IRQ_I2C_5, MCHP_IRQ_I2C_6, MCHP_IRQ_I2C_7
+					     MCHP_IRQ_I2C_4, MCHP_IRQ_I2C_5,
+					     MCHP_IRQ_I2C_6, MCHP_IRQ_I2C_7
 #endif
 };
 BUILD_ASSERT(ARRAY_SIZE(i2c_ctrl_nvic_id) == MCHP_I2C_CTRL_MAX);
 
-static const uint16_t i2c_controller_pcr[] = {
-	MCHP_PCR_I2C0, MCHP_PCR_I2C1, MCHP_PCR_I2C2, MCHP_PCR_I2C3,
+static const uint16_t i2c_controller_pcr[] = { MCHP_PCR_I2C0, MCHP_PCR_I2C1,
+					       MCHP_PCR_I2C2, MCHP_PCR_I2C3,
 #if defined(CHIP_FAMILY_MEC172X)
-	MCHP_PCR_I2C4
+					       MCHP_PCR_I2C4
 #elif defined(CHIP_FAMILY_MEC152X)
 	MCHP_PCR_I2C4, MCHP_PCR_I2C5, MCHP_PCR_I2C6, MCHP_PCR_I2C7,
 #endif
 };
 BUILD_ASSERT(ARRAY_SIZE(i2c_controller_pcr) == MCHP_I2C_CTRL_MAX);
 
-static uintptr_t i2c_ctrl_base_addr[] = {
-	MCHP_I2C0_BASE, MCHP_I2C1_BASE, MCHP_I2C2_BASE, MCHP_I2C3_BASE,
+static uintptr_t i2c_ctrl_base_addr[] = { MCHP_I2C0_BASE, MCHP_I2C1_BASE,
+					  MCHP_I2C2_BASE, MCHP_I2C3_BASE,
 #if defined(CHIP_FAMILY_MEC172X)
-	MCHP_I2C4_BASE
+					  MCHP_I2C4_BASE
 #elif defined(CHIP_FAMILY_MEC152X)
-	MCHP_I2C4_BASE,
-	/* NOTE: 5-7 do not implement network layer hardware */
-	MCHP_I2C5_BASE, MCHP_I2C6_BASE, MCHP_I2C7_BASE
+					  MCHP_I2C4_BASE,
+					  /* NOTE: 5-7 do not implement network
+					     layer hardware */
+					  MCHP_I2C5_BASE, MCHP_I2C6_BASE,
+					  MCHP_I2C7_BASE
 #endif
 };
 BUILD_ASSERT(ARRAY_SIZE(i2c_ctrl_base_addr) == MCHP_I2C_CTRL_MAX);
@@ -230,7 +233,7 @@ struct i2c_bus_clk {
 };
 
 const struct i2c_bus_clk i2c_freq_tbl[] = {
-	{ 40, SPEED_40KHZ_BUS_CLOCK }, { 80, SPEED_80KHZ_BUS_CLOCK },
+	{ 40, SPEED_40KHZ_BUS_CLOCK },	 { 80, SPEED_80KHZ_BUS_CLOCK },
 	{ 100, SPEED_100KHZ_BUS_CLOCK }, { 333, SPEED_333KHZ_BUS_CLOCK },
 	{ 400, SPEED_400KHZ_BUS_CLOCK }, { 1000, SPEED_1MHZ_BUS_CLOCK },
 };
diff --git a/chip/mchp/i2c_chip.h b/chip/mchp/i2c_chip.h
index c8ceb98d04..b7109c4c69 100644
--- a/chip/mchp/i2c_chip.h
+++ b/chip/mchp/i2c_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/mchp/keyboard_raw.c b/chip/mchp/keyboard_raw.c
index f10cac38b6..daa0c8e64f 100644
--- a/chip/mchp/keyboard_raw.c
+++ b/chip/mchp/keyboard_raw.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/chip/mchp/lfw/ec_lfw.c b/chip/mchp/lfw/ec_lfw.c
index 6f34a33a8d..dfd9814e6e 100644
--- a/chip/mchp/lfw/ec_lfw.c
+++ b/chip/mchp/lfw/ec_lfw.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -41,15 +41,16 @@
 #define LFW_SPI_BYTE_TRANSFER_TIMEOUT_US (1 * MSEC)
 #define LFW_SPI_BYTE_TRANSFER_POLL_INTERVAL_US 100
 
-__attribute__ ((section(".intvector")))
+__attribute__((section(".intvector")))
 const struct int_vector_t hdr_int_vect = {
 	/* init sp, unused. set by MEC ROM loader */
-	(void *)lfw_stack_top,  /* preserve ROM log. was (void *)0x11FA00, */
-	&lfw_main,	/* was &lfw_main, */	  /* reset vector */
-	&fault_handler,   /* NMI handler */
-	&fault_handler,   /* HardFault handler */
-	&fault_handler,   /* MPU fault handler */
-	&fault_handler    /* Bus fault handler */
+	(void *)lfw_stack_top, /* preserve ROM log. was (void *)0x11FA00, */
+	&lfw_main,
+	/* was &lfw_main, */ /* reset vector */
+	&fault_handler, /* NMI handler */
+	&fault_handler, /* HardFault handler */
+	&fault_handler, /* MPU fault handler */
+	&fault_handler /* Bus fault handler */
 };
 
 /* SPI devices - from board.c */
@@ -123,7 +124,6 @@ void timer_init(void)
 
 	/* Start counting in timer 0 */
 	MCHP_TMR32_CTL(0) |= BIT(5);
-
 }
 
 /*
@@ -132,14 +132,11 @@ void timer_init(void)
  * before starting SPI read to minimize probability of
  * timer wrap.
  */
-static int spi_flash_readloc(uint8_t *buf_usr,
-				unsigned int offset,
-				unsigned int bytes)
+static int spi_flash_readloc(uint8_t *buf_usr, unsigned int offset,
+			     unsigned int bytes)
 {
-	uint8_t cmd[4] = {SPI_FLASH_READ,
-				(offset >> 16) & 0xFF,
-				(offset >> 8) & 0xFF,
-				offset & 0xFF};
+	uint8_t cmd[4] = { SPI_FLASH_READ, (offset >> 16) & 0xFF,
+			   (offset >> 8) & 0xFF, offset & 0xFF };
 
 	if (offset + bytes > CONFIG_FLASH_SIZE_BYTES)
 		return EC_ERROR_INVAL;
@@ -156,8 +153,8 @@ static int spi_flash_readloc(uint8_t *buf_usr,
  */
 int spi_image_load(uint32_t offset)
 {
-	uint8_t *buf = (uint8_t *) (CONFIG_RW_MEM_OFF +
-				    CONFIG_PROGRAM_MEMORY_BASE);
+	uint8_t *buf =
+		(uint8_t *)(CONFIG_RW_MEM_OFF + CONFIG_PROGRAM_MEMORY_BASE);
 	uint32_t i;
 #ifdef CONFIG_MCHP_LFW_DEBUG
 	uint32_t crc_calc, crc_exp;
@@ -172,13 +169,11 @@ int spi_image_load(uint32_t offset)
 	for (i = 0; i < CONFIG_RO_SIZE; i += SPI_CHUNK_SIZE)
 #ifdef CONFIG_MCHP_LFW_DEBUG
 		rc = spi_flash_readloc(&buf[i], offset + i, SPI_CHUNK_SIZE);
-		if (rc != EC_SUCCESS) {
-			trace2(0, LFW, 0,
-				"spi_flash_readloc block %d ret = %d",
-				i, rc);
-			while (MCHP_PCR_PROC_CLK_CTL)
-				MCHP_PCR_CHIP_OSC_ID &= 0x1FE;
-		}
+	if (rc != EC_SUCCESS) {
+		trace2(0, LFW, 0, "spi_flash_readloc block %d ret = %d", i, rc);
+		while (MCHP_PCR_PROC_CLK_CTL)
+			MCHP_PCR_CHIP_OSC_ID &= 0x1FE;
+	}
 #else
 		spi_flash_readloc(&buf[i], offset + i, SPI_CHUNK_SIZE);
 #endif
@@ -234,7 +229,7 @@ timestamp_t get_time(void)
 {
 	timestamp_t ts;
 
-	ts.le.hi = 0;	/* clksrc_high; */
+	ts.le.hi = 0; /* clksrc_high; */
 	ts.le.lo = __hw_clock_source_read();
 	return ts;
 }
@@ -297,11 +292,17 @@ void uart_init(void)
 	gpio_config_module(MODULE_UART, 1);
 }
 #else
-void uart_write_c(char c __attribute__((unused))) {}
+void uart_write_c(char c __attribute__((unused)))
+{
+}
 
-void uart_puts(const char *str __attribute__((unused))) {}
+void uart_puts(const char *str __attribute__((unused)))
+{
+}
 
-void uart_init(void) {}
+void uart_init(void)
+{
+}
 #endif /* #ifdef CONFIG_UART_CONSOLE */
 
 void fault_handler(void)
@@ -312,12 +313,11 @@ void fault_handler(void)
 	MCHP_PCR_SYS_RST = MCHP_PCR_SYS_SOFT_RESET;
 	while (1)
 		;
-
 }
 
 void jump_to_image(uintptr_t init_addr)
 {
-	void (*resetvec)(void) = (void(*)(void))init_addr;
+	void (*resetvec)(void) = (void (*)(void))init_addr;
 
 	resetvec();
 }
@@ -329,16 +329,13 @@ void jump_to_image(uintptr_t init_addr)
 void system_init(void)
 {
 	uint32_t wdt_sts = MCHP_VBAT_STS & MCHP_VBAT_STS_ANY_RST;
-	uint32_t rst_sts = MCHP_PCR_PWR_RST_STS &
-				MCHP_PWR_RST_STS_SYS;
+	uint32_t rst_sts = MCHP_PCR_PWR_RST_STS & MCHP_PWR_RST_STS_SYS;
 
-	trace12(0, LFW, 0,
-		"VBAT_STS = 0x%08x  PCR_PWR_RST_STS = 0x%08x",
+	trace12(0, LFW, 0, "VBAT_STS = 0x%08x  PCR_PWR_RST_STS = 0x%08x",
 		wdt_sts, rst_sts);
 
 	if (rst_sts || wdt_sts)
-		MCHP_VBAT_RAM(MCHP_IMAGETYPE_IDX)
-					= EC_IMAGE_UNKNOWN;
+		MCHP_VBAT_RAM(MCHP_IMAGETYPE_IDX) = EC_IMAGE_UNKNOWN;
 }
 
 enum ec_image system_get_image_copy(void)
@@ -346,7 +343,6 @@ enum ec_image system_get_image_copy(void)
 	return MCHP_VBAT_RAM(MCHP_IMAGETYPE_IDX);
 }
 
-
 /*
  * lfw_main is entered by MEC BootROM or EC_RO/RW calling it directly.
  * NOTE: Based on LFW from MEC1322
@@ -360,11 +356,10 @@ enum ec_image system_get_image_copy(void)
  */
 void lfw_main(void)
 {
-
 	uintptr_t init_addr;
 
 	/* install vector table */
-	*((uintptr_t *) 0xe000ed08) = (uintptr_t) &hdr_int_vect;
+	*((uintptr_t *)0xe000ed08) = (uintptr_t)&hdr_int_vect;
 
 	/* Use 48 MHz processor clock to power through boot */
 	MCHP_PCR_PROC_CLK_CTL = 1;
diff --git a/chip/mchp/lfw/ec_lfw.h b/chip/mchp/lfw/ec_lfw.h
index c989a3bc1b..2589638954 100644
--- a/chip/mchp/lfw/ec_lfw.h
+++ b/chip/mchp/lfw/ec_lfw.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -30,12 +30,12 @@ void fault_handler(void) __attribute__((naked));
 extern uint32_t lfw_stack_top[];
 
 struct int_vector_t {
-	void   *stack_ptr;
-	void   *reset_vector;
-	void   *nmi;
-	void   *hard_fault;
-	void   *bus_fault;
-	void   *usage_fault;
+	void *stack_ptr;
+	void *reset_vector;
+	void *nmi;
+	void *hard_fault;
+	void *bus_fault;
+	void *usage_fault;
 };
 
-#define SPI_CHUNK_SIZE			1024
+#define SPI_CHUNK_SIZE 1024
diff --git a/chip/mchp/lfw/ec_lfw.ld b/chip/mchp/lfw/ec_lfw.ld
index 8e8601a5ee..f0071a55e9 100644
--- a/chip/mchp/lfw/ec_lfw.ld
+++ b/chip/mchp/lfw/ec_lfw.ld
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/chip/mchp/lfw/ec_lfw_416kb.ld b/chip/mchp/lfw/ec_lfw_416kb.ld
index 97be2fe06a..f27d046e7d 100644
--- a/chip/mchp/lfw/ec_lfw_416kb.ld
+++ b/chip/mchp/lfw/ec_lfw_416kb.ld
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/chip/mchp/lfw/gpio.inc b/chip/mchp/lfw/gpio.inc
index 598a6044d7..76de618bf3 100644
--- a/chip/mchp/lfw/gpio.inc
+++ b/chip/mchp/lfw/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/chip/mchp/lpc.c b/chip/mchp/lpc.c
index 86cc67fb51..4dc60098c0 100644
--- a/chip/mchp/lpc.c
+++ b/chip/mchp/lpc.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,23 +27,22 @@
 /* Console output macros */
 #ifdef CONFIG_MCHP_DEBUG_LPC
 #define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args)
 #else
 #define CPUTS(...)
 #define CPRINTS(...)
 #endif
 
-static uint8_t
-mem_mapped[0x200] __attribute__((section(".bss.big_align")));
+static uint8_t mem_mapped[0x200] __attribute__((section(".bss.big_align")));
 
 static struct host_packet lpc_packet;
 static struct host_cmd_handler_args host_cmd_args;
-static uint8_t host_cmd_flags;   /* Flags from host command */
+static uint8_t host_cmd_flags; /* Flags from host command */
 
 static uint8_t params_copy[EC_LPC_HOST_PACKET_SIZE] __aligned(4);
 static int init_done;
 
-static struct ec_lpc_host_args * const lpc_host_args =
+static struct ec_lpc_host_args *const lpc_host_args =
 	(struct ec_lpc_host_args *)mem_mapped;
 
 #ifdef CONFIG_BOARD_ID_CMD_ACPI_EC1
@@ -52,7 +51,6 @@ static uint8_t custom_acpi_ec2os_cnt;
 static uint8_t custom_apci_ec2os[4];
 #endif
 
-
 static void keyboard_irq_assert(void)
 {
 #ifdef CONFIG_KEYBOARD_IRQ_GPIO
@@ -110,7 +108,7 @@ static void lpc_generate_sci(void)
 	espi_vw_pulse_wire(VW_SCI_L, 0);
 #else
 	MCHP_ACPI_PM_STS |= 1;
-	udelay(CONFIG_ESPI_DEFAULT_VW_WIDTH_US);
+	udelay(CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US);
 	MCHP_ACPI_PM_STS &= ~1;
 #endif
 #endif
@@ -142,7 +140,6 @@ static uint8_t *lpc_get_hostcmd_data_range(void)
 	return mem_mapped;
 }
 
-
 /**
  * Update the host event status.
  *
@@ -182,7 +179,7 @@ void lpc_update_host_event_status(void)
 
 	/* Copy host events to mapped memory */
 	*(uint32_t *)host_get_memmap(EC_MEMMAP_HOST_EVENTS) =
-			lpc_get_host_events();
+		lpc_get_host_events();
 
 	task_enable_irq(MCHP_IRQ_ACPIEC0_IBF);
 
@@ -216,15 +213,13 @@ static void lpc_send_response(struct host_cmd_handler_args *args)
 	}
 
 	/* New-style response */
-	lpc_host_args->flags =
-		(host_cmd_flags & ~EC_HOST_ARGS_FLAG_FROM_HOST) |
-			EC_HOST_ARGS_FLAG_TO_HOST;
+	lpc_host_args->flags = (host_cmd_flags & ~EC_HOST_ARGS_FLAG_FROM_HOST) |
+			       EC_HOST_ARGS_FLAG_TO_HOST;
 
 	lpc_host_args->data_size = size;
 
 	csum = args->command + lpc_host_args->flags +
-			lpc_host_args->command_version +
-			lpc_host_args->data_size;
+	       lpc_host_args->command_version + lpc_host_args->data_size;
 
 	for (i = 0, out = (uint8_t *)args->response; i < size; i++, out++)
 		csum += *out;
@@ -243,9 +238,7 @@ static void lpc_send_response(struct host_cmd_handler_args *args)
 	 * sticky status in interrupt aggregator.
 	 */
 	MCHP_ACPI_EC_STATUS(1) &= ~EC_LPC_STATUS_PROCESSING;
-	MCHP_INT_SOURCE(MCHP_ACPI_EC_GIRQ) =
-				MCHP_ACPI_EC_IBF_GIRQ_BIT(1);
-
+	MCHP_INT_SOURCE(MCHP_ACPI_EC_GIRQ) = MCHP_ACPI_EC_IBF_GIRQ_BIT(1);
 }
 
 static void lpc_send_response_packet(struct host_packet *pkt)
@@ -265,8 +258,7 @@ static void lpc_send_response_packet(struct host_packet *pkt)
 
 	/* Clear the busy bit, so the host knows the EC is done. */
 	MCHP_ACPI_EC_STATUS(1) &= ~EC_LPC_STATUS_PROCESSING;
-	MCHP_INT_SOURCE(MCHP_ACPI_EC_GIRQ) =
-				MCHP_ACPI_EC_IBF_GIRQ_BIT(1);
+	MCHP_INT_SOURCE(MCHP_ACPI_EC_GIRQ) = MCHP_ACPI_EC_IBF_GIRQ_BIT(1);
 }
 
 uint8_t *lpc_get_memmap_range(void)
@@ -283,10 +275,8 @@ void lpc_mem_mapped_init(void)
 }
 
 const int acpi_ec_pcr_slp[] = {
-	MCHP_PCR_ACPI_EC0,
-	MCHP_PCR_ACPI_EC1,
-	MCHP_PCR_ACPI_EC2,
-	MCHP_PCR_ACPI_EC3,
+	MCHP_PCR_ACPI_EC0, MCHP_PCR_ACPI_EC1,
+	MCHP_PCR_ACPI_EC2, MCHP_PCR_ACPI_EC3,
 #ifndef CHIP_FAMILY_MEC152X
 	MCHP_PCR_ACPI_EC4,
 #endif
@@ -294,10 +284,8 @@ const int acpi_ec_pcr_slp[] = {
 BUILD_ASSERT(ARRAY_SIZE(acpi_ec_pcr_slp) == MCHP_ACPI_EC_INSTANCES);
 
 const int acpi_ec_nvic_ibf[] = {
-	MCHP_IRQ_ACPIEC0_IBF,
-	MCHP_IRQ_ACPIEC1_IBF,
-	MCHP_IRQ_ACPIEC2_IBF,
-	MCHP_IRQ_ACPIEC3_IBF,
+	MCHP_IRQ_ACPIEC0_IBF, MCHP_IRQ_ACPIEC1_IBF,
+	MCHP_IRQ_ACPIEC2_IBF, MCHP_IRQ_ACPIEC3_IBF,
 #ifndef CHIP_FAMILY_MEC152X
 	MCHP_IRQ_ACPIEC4_IBF,
 #endif
@@ -306,10 +294,8 @@ BUILD_ASSERT(ARRAY_SIZE(acpi_ec_nvic_ibf) == MCHP_ACPI_EC_INSTANCES);
 
 #ifdef CONFIG_HOST_INTERFACE_ESPI
 const int acpi_ec_espi_bar_id[] = {
-	MCHP_ESPI_IO_BAR_ID_ACPI_EC0,
-	MCHP_ESPI_IO_BAR_ID_ACPI_EC1,
-	MCHP_ESPI_IO_BAR_ID_ACPI_EC2,
-	MCHP_ESPI_IO_BAR_ID_ACPI_EC3,
+	MCHP_ESPI_IO_BAR_ID_ACPI_EC0, MCHP_ESPI_IO_BAR_ID_ACPI_EC1,
+	MCHP_ESPI_IO_BAR_ID_ACPI_EC2, MCHP_ESPI_IO_BAR_ID_ACPI_EC3,
 #ifndef CHIP_FAMILY_MEC152X
 	MCHP_ESPI_IO_BAR_ID_ACPI_EC4,
 #endif
@@ -327,17 +313,15 @@ void chip_acpi_ec_config(int instance, uint32_t io_base, uint8_t mask)
 	MCHP_PCR_SLP_DIS_DEV(acpi_ec_pcr_slp[instance]);
 
 #ifdef CONFIG_HOST_INTERFACE_ESPI
-	MCHP_ESPI_IO_BAR_CTL_MASK(acpi_ec_espi_bar_id[instance]) =
-			mask;
+	MCHP_ESPI_IO_BAR_CTL_MASK(acpi_ec_espi_bar_id[instance]) = mask;
 	MCHP_ESPI_IO_BAR(acpi_ec_espi_bar_id[instance]) =
-			(io_base << 16) + 0x01ul;
+		(io_base << 16) + 0x01ul;
 #else
-	MCHP_LPC_ACPI_EC_BAR(instance) = (io_base << 16) +
-		(1ul << 15) + mask;
+	MCHP_LPC_ACPI_EC_BAR(instance) = (io_base << 16) + (1ul << 15) + mask;
 #endif
 	MCHP_ACPI_EC_STATUS(instance) &= ~EC_LPC_STATUS_PROCESSING;
 	MCHP_INT_ENABLE(MCHP_ACPI_EC_GIRQ) =
-			MCHP_ACPI_EC_IBF_GIRQ_BIT(instance);
+		MCHP_ACPI_EC_IBF_GIRQ_BIT(instance);
 	task_enable_irq(acpi_ec_nvic_ibf[instance]);
 }
 
@@ -352,8 +336,7 @@ void chip_8042_config(uint32_t io_base)
 
 #ifdef CONFIG_HOST_INTERFACE_ESPI
 	MCHP_ESPI_IO_BAR_CTL_MASK(MCHP_ESPI_IO_BAR_ID_8042) = 0x04;
-	MCHP_ESPI_IO_BAR(MCHP_ESPI_IO_BAR_ID_8042) =
-			(io_base << 16) + 0x01ul;
+	MCHP_ESPI_IO_BAR(MCHP_ESPI_IO_BAR_ID_8042) = (io_base << 16) + 0x01ul;
 #else
 	/* Set up 8042 interface at 0x60/0x64 */
 	MCHP_LPC_8042_BAR = (io_base << 16) + (1ul << 15);
@@ -363,8 +346,8 @@ void chip_8042_config(uint32_t io_base)
 
 	MCHP_8042_ACT |= 1;
 
-	MCHP_INT_ENABLE(MCHP_8042_GIRQ) = MCHP_8042_OBE_GIRQ_BIT +
-			MCHP_8042_IBF_GIRQ_BIT;
+	MCHP_INT_ENABLE(MCHP_8042_GIRQ) =
+		MCHP_8042_OBE_GIRQ_BIT + MCHP_8042_IBF_GIRQ_BIT;
 
 	task_enable_irq(MCHP_IRQ_8042EM_IBF);
 	task_enable_irq(MCHP_IRQ_8042EM_OBE);
@@ -394,8 +377,7 @@ void chip_emi0_config(uint32_t io_base)
 {
 #ifdef CONFIG_HOST_INTERFACE_ESPI
 	MCHP_ESPI_IO_BAR_CTL_MASK(MCHP_ESPI_IO_BAR_ID_EMI0) = 0x0F;
-	MCHP_ESPI_IO_BAR(MCHP_ESPI_IO_BAR_ID_EMI0) =
-			(io_base << 16) + 0x01ul;
+	MCHP_ESPI_IO_BAR(MCHP_ESPI_IO_BAR_ID_EMI0) = (io_base << 16) + 0x01ul;
 #else
 	MCHP_LPC_EMI0_BAR = (io_base << 16) + (1ul << 15);
 #endif
@@ -431,27 +413,23 @@ void chip_port80_config(uint32_t io_base)
 
 	/* Last: Enable Host access via eSPI IO BAR */
 	MCHP_ESPI_IO_BAR_CTL_MASK(MCHP_ESPI_IO_BAR_BDP0) = 0x00;
-	MCHP_ESPI_IO_BAR(MCHP_ESPI_IO_BAR_BDP0) =
-			(io_base << 16) + 0x01ul;
+	MCHP_ESPI_IO_BAR(MCHP_ESPI_IO_BAR_BDP0) = (io_base << 16) + 0x01ul;
 }
 #else
 void chip_port80_config(uint32_t io_base)
 {
 	MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_P80CAP0);
 
-	MCHP_P80_CFG(0) = MCHP_P80_FLUSH_FIFO_WO +
-			MCHP_P80_RESET_TIMESTAMP_WO;
+	MCHP_P80_CFG(0) = MCHP_P80_FLUSH_FIFO_WO + MCHP_P80_RESET_TIMESTAMP_WO;
 
 #ifdef CONFIG_HOST_INTERFACE_ESPI
 	MCHP_ESPI_IO_BAR_CTL_MASK(MCHP_ESPI_IO_BAR_P80_0) = 0x00;
-	MCHP_ESPI_IO_BAR(MCHP_ESPI_IO_BAR_P80_0) =
-			(io_base << 16) + 0x01ul;
+	MCHP_ESPI_IO_BAR(MCHP_ESPI_IO_BAR_P80_0) = (io_base << 16) + 0x01ul;
 #else
 	MCHP_LPC_P80DBG0_BAR = (io_base << 16) + (1ul << 15);
 #endif
-	MCHP_P80_CFG(0) = MCHP_P80_FIFO_THRHOLD_14 +
-			MCHP_P80_TIMEBASE_1500KHZ +
-			MCHP_P80_TIMER_ENABLE;
+	MCHP_P80_CFG(0) = MCHP_P80_FIFO_THRHOLD_14 + MCHP_P80_TIMEBASE_1500KHZ +
+			  MCHP_P80_TIMER_ENABLE;
 
 	MCHP_P80_ACTIVATE(0) = 1;
 
@@ -541,9 +519,9 @@ static void lpc_init(void)
 	 * NOTE: EMI doesn't have a sleep enable.
 	 */
 	MCHP_PCR_SLP_DIS_DEV_MASK(2, MCHP_PCR_SLP_EN2_GCFG +
-		MCHP_PCR_SLP_EN2_ACPI_EC0 +
-		MCHP_PCR_SLP_EN2_ACPI_EC0 +
-		MCHP_PCR_SLP_EN2_MIF8042);
+					     MCHP_PCR_SLP_EN2_ACPI_EC0 +
+					     MCHP_PCR_SLP_EN2_ACPI_EC0 +
+					     MCHP_PCR_SLP_EN2_MIF8042);
 
 #ifdef CONFIG_HOST_INTERFACE_ESPI
 
@@ -574,8 +552,7 @@ static void lpc_init(void)
 	 * clock stop and there are no pending SERIRQ
 	 * or LPC DMA.
 	 */
-	MCHP_LPC_EC_CLK_CTRL =
-		(MCHP_LPC_EC_CLK_CTRL & ~(0x03ul)) | 0x01ul;
+	MCHP_LPC_EC_CLK_CTRL = (MCHP_LPC_EC_CLK_CTRL & ~(0x03ul)) | 0x01ul;
 
 	setup_lpc();
 #endif
@@ -635,8 +612,7 @@ void lpcrst_interrupt(enum gpio_signal signal)
 #endif
 	}
 #ifdef CONFIG_MCHP_DEBUG_LPC
-	CPRINTS("LPC RESET# %sasserted",
-		lpc_get_pltrst_asserted() ? "" : "de");
+	CPRINTS("LPC RESET# %sasserted", lpc_get_pltrst_asserted() ? "" : "de");
 #endif
 #endif
 }
@@ -688,8 +664,7 @@ int port_80_read(void)
  * Some chipset CoreBoot will send read board ID command expecting
  * a two byte response.
  */
-static int acpi_ec0_custom(int is_cmd, uint8_t value,
-		uint8_t *resultptr)
+static int acpi_ec0_custom(int is_cmd, uint8_t value, uint8_t *resultptr)
 {
 	int rval;
 
@@ -699,7 +674,7 @@ static int acpi_ec0_custom(int is_cmd, uint8_t value,
 
 	if (is_cmd && (value == 0x0d)) {
 		MCHP_INT_SOURCE(MCHP_ACPI_EC_GIRQ) =
-				MCHP_ACPI_EC_OBE_GIRQ_BIT(0);
+			MCHP_ACPI_EC_OBE_GIRQ_BIT(0);
 		/* Write two bytes sequence 0xC2, 0x04 to Host */
 		if (MCHP_ACPI_EC_BYTE_CTL(0) & 0x01) {
 			/* Host enabled 4-byte mode */
@@ -715,7 +690,7 @@ static int acpi_ec0_custom(int is_cmd, uint8_t value,
 			custom_apci_ec2os[0] = 0x04;
 			MCHP_ACPI_EC_EC2OS(0, 0) = 0x02;
 			MCHP_INT_ENABLE(MCHP_ACPI_EC_GIRQ) =
-					MCHP_ACPI_EC_OBE_GIRQ_BIT(0);
+				MCHP_ACPI_EC_OBE_GIRQ_BIT(0);
 			task_enable_irq(MCHP_IRQ_ACPIEC0_OBE);
 		}
 		custom_acpi_cmd = 0;
@@ -754,8 +729,7 @@ static void acpi_0_interrupt(void)
 	MCHP_ACPI_EC_STATUS(0) &= ~EC_LPC_STATUS_PROCESSING;
 
 	/* Clear R/W1C status bit in Aggregator */
-	MCHP_INT_SOURCE(MCHP_ACPI_EC_GIRQ) =
-			MCHP_ACPI_EC_IBF_GIRQ_BIT(0);
+	MCHP_INT_SOURCE(MCHP_ACPI_EC_GIRQ) = MCHP_ACPI_EC_IBF_GIRQ_BIT(0);
 
 	/*
 	 * ACPI 5.0-12.6.1: Generate SCI for Input Buffer Empty /
@@ -775,8 +749,7 @@ static void acpi_0_obe_isr(void)
 {
 	uint8_t sts, data;
 
-	MCHP_INT_SOURCE(MCHP_ACPI_EC_GIRQ) =
-			MCHP_ACPI_EC_OBE_GIRQ_BIT(0);
+	MCHP_INT_SOURCE(MCHP_ACPI_EC_GIRQ) = MCHP_ACPI_EC_OBE_GIRQ_BIT(0);
 
 	sts = MCHP_ACPI_EC_STATUS(0);
 	data = MCHP_ACPI_EC_BYTE_CTL(0);
@@ -788,7 +761,7 @@ static void acpi_0_obe_isr(void)
 
 	if (custom_acpi_ec2os_cnt == 0) { /* was last byte? */
 		MCHP_INT_DISABLE(MCHP_ACPI_EC_GIRQ) =
-				MCHP_ACPI_EC_OBE_GIRQ_BIT(0);
+			MCHP_ACPI_EC_OBE_GIRQ_BIT(0);
 	}
 
 	lpc_generate_sci();
@@ -800,8 +773,7 @@ static void acpi_1_interrupt(void)
 {
 	uint8_t st = MCHP_ACPI_EC_STATUS(1);
 
-	if (!(st & EC_LPC_STATUS_FROM_HOST) ||
-	    !(st & EC_LPC_STATUS_LAST_CMD))
+	if (!(st & EC_LPC_STATUS_FROM_HOST) || !(st & EC_LPC_STATUS_LAST_CMD))
 		return;
 
 	/* Set the busy bit */
@@ -821,8 +793,7 @@ static void acpi_1_interrupt(void)
 	if (host_cmd_args.command == EC_COMMAND_PROTOCOL_3) {
 		lpc_packet.send_response = lpc_send_response_packet;
 
-		lpc_packet.request =
-			(const void *)lpc_get_hostcmd_data_range();
+		lpc_packet.request = (const void *)lpc_get_hostcmd_data_range();
 		lpc_packet.request_temp = params_copy;
 		lpc_packet.request_max = sizeof(params_copy);
 		/* Don't know the request size so
@@ -830,8 +801,7 @@ static void acpi_1_interrupt(void)
 		 */
 		lpc_packet.request_size = EC_LPC_HOST_PACKET_SIZE;
 
-		lpc_packet.response =
-			(void *)lpc_get_hostcmd_data_range();
+		lpc_packet.response = (void *)lpc_get_hostcmd_data_range();
 		lpc_packet.response_max = EC_LPC_HOST_PACKET_SIZE;
 		lpc_packet.response_size = 0;
 
@@ -857,8 +827,7 @@ DECLARE_IRQ(MCHP_IRQ_ACPIEC1_IBF, acpi_1_interrupt, 1);
 static void kb_ibf_interrupt(void)
 {
 	if (lpc_keyboard_input_pending())
-		keyboard_host_write(MCHP_8042_H2E,
-				    MCHP_8042_STS & BIT(3));
+		keyboard_host_write(MCHP_8042_H2E, MCHP_8042_STS & BIT(3));
 
 	MCHP_INT_SOURCE(MCHP_8042_GIRQ) = MCHP_8042_IBF_GIRQ_BIT;
 	task_wake(TASK_ID_KEYPROTO);
@@ -954,7 +923,7 @@ int lpc_get_pltrst_asserted(void)
 	return !gpio_get_level(GPIO_PCH_PLTRST_L);
 #else
 	/* assumes LPC clock is running when host changes LRESET# */
-	return (MCHP_LPC_BUS_MONITOR & (1<<1)) ? 1 : 0;
+	return (MCHP_LPC_BUS_MONITOR & (1 << 1)) ? 1 : 0;
 #endif
 #endif
 }
@@ -972,7 +941,7 @@ void lpc_disable_acpi_interrupts(void)
 }
 
 /* On boards without a host, this command is used to set up LPC */
-static int lpc_command_init(int argc, char **argv)
+static int lpc_command_init(int argc, const char **argv)
 {
 	lpc_init();
 	return EC_SUCCESS;
@@ -996,12 +965,11 @@ static enum ec_status lpc_get_protocol_info(struct host_cmd_handler_args *args)
 
 	return EC_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO,
-		lpc_get_protocol_info,
-		EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, lpc_get_protocol_info,
+		     EC_VER_MASK(0));
 
 #ifdef CONFIG_MCHP_DEBUG_LPC
-static int command_lpc(int argc, char **argv)
+static int command_lpc(int argc, const char **argv)
 {
 	if (argc == 1)
 		return EC_ERROR_PARAM1;
@@ -1016,6 +984,5 @@ static int command_lpc(int argc, char **argv)
 		return EC_ERROR_PARAM1;
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(lpc, command_lpc, "[sci|smi|wake]",
-	"Trigger SCI/SMI");
+DECLARE_CONSOLE_COMMAND(lpc, command_lpc, "[sci|smi|wake]", "Trigger SCI/SMI");
 #endif
diff --git a/chip/mchp/lpc_chip.h b/chip/mchp/lpc_chip.h
index 434b307968..7d9965f156 100644
--- a/chip/mchp/lpc_chip.h
+++ b/chip/mchp/lpc_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,7 +12,7 @@
 
 #include "espi.h"
 
-#define MCHP_HOST_IF_LPC  (0)
+#define MCHP_HOST_IF_LPC (0)
 #define MCHP_HOST_IF_ESPI (1)
 
 /* eSPI Initialization functions */
diff --git a/chip/mchp/port80.c b/chip/mchp/port80.c
index a32dc1b9c2..57ceaac8fa 100644
--- a/chip/mchp/port80.c
+++ b/chip/mchp/port80.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,7 +14,6 @@
 #include "task.h"
 #include "tfdp_chip.h"
 
-
 #if defined(CHIP_FAMILY_MEC172X)
 /*
  * MEC172x family implements a new Port 0x80 capture block.
diff --git a/chip/mchp/pwm.c b/chip/mchp/pwm.c
index ae22f13ca5..d0e88b5175 100644
--- a/chip/mchp/pwm.c
+++ b/chip/mchp/pwm.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,22 +16,16 @@
 #include "tfdp_chip.h"
 
 #define CPUTS(outstr) cputs(CC_PWM, outstr)
-#define CPRINTS(format, args...) cprints(CC_PWM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_PWM, format, ##args)
 
 /* Bit map of PWM channels that must remain active during low power idle. */
 static uint32_t pwm_keep_awake_mask;
 
 /* Table of PWM PCR sleep enable register index and bit position. */
 static const uint16_t pwm_pcr[] = {
-	MCHP_PCR_PWM0,
-	MCHP_PCR_PWM1,
-	MCHP_PCR_PWM2,
-	MCHP_PCR_PWM3,
-	MCHP_PCR_PWM4,
-	MCHP_PCR_PWM5,
-	MCHP_PCR_PWM6,
-	MCHP_PCR_PWM7,
-	MCHP_PCR_PWM8,
+	MCHP_PCR_PWM0, MCHP_PCR_PWM1, MCHP_PCR_PWM2,
+	MCHP_PCR_PWM3, MCHP_PCR_PWM4, MCHP_PCR_PWM5,
+	MCHP_PCR_PWM6, MCHP_PCR_PWM7, MCHP_PCR_PWM8,
 };
 BUILD_ASSERT(ARRAY_SIZE(pwm_pcr) == MCHP_PWM_ID_MAX);
 
@@ -90,8 +84,8 @@ void pwm_keep_awake(void)
 static void pwm_configure(int ch, int active_low, int clock_low)
 {
 	MCHP_PWM_CFG(ch) = (15 << 3) /* divider = 16 */
-		| (active_low ? BIT(2) : 0)
-		| (clock_low  ? BIT(1) : 0);
+			   | (active_low ? BIT(2) : 0) |
+			   (clock_low ? BIT(1) : 0);
 }
 
 static void pwm_slp_en(int pwm_id, int sleep_en)
diff --git a/chip/mchp/pwm_chip.h b/chip/mchp/pwm_chip.h
index f828a234a7..848656bb03 100644
--- a/chip/mchp/pwm_chip.h
+++ b/chip/mchp/pwm_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -48,4 +48,4 @@ extern const struct pwm_t pwm_channels[];
 
 void pwm_keep_awake(void);
 
-#endif  /* __CROS_EC_PWM_CHIP_H */
+#endif /* __CROS_EC_PWM_CHIP_H */
diff --git a/chip/mchp/qmspi.c b/chip/mchp/qmspi.c
index b170d75283..6979bdae6a 100644
--- a/chip/mchp/qmspi.c
+++ b/chip/mchp/qmspi.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,14 +21,12 @@
 #include "tfdp_chip.h"
 
 #define CPUTS(outstr) cputs(CC_SPI, outstr)
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SPI, format, ##args)
 
 #define QMSPI_TRANSFER_TIMEOUT (100 * MSEC)
 #define QMSPI_BYTE_TRANSFER_TIMEOUT_US (3 * MSEC)
 #define QMSPI_BYTE_TRANSFER_POLL_INTERVAL_US 20
 
-
-
 #ifndef CONFIG_MCHP_QMSPI_TX_DMA
 #ifdef LFW
 /*
@@ -137,8 +135,8 @@ static uint32_t qmspi_build_tx_descr(uint32_t ntx, uint32_t ndid)
  * value (1, 2, or 4).
  * Caller will apply close and last flags if applicable.
  */
-static uint64_t qmspi_build_rx_descr(uint32_t raddr,
-		uint32_t nrx, uint32_t ndid)
+static uint64_t qmspi_build_rx_descr(uint32_t raddr, uint32_t nrx,
+				     uint32_t ndid)
 {
 	uint32_t d, dmau, na;
 	uint64_t u;
@@ -182,9 +180,9 @@ static uint64_t qmspi_build_rx_descr(uint32_t raddr,
 
 #ifdef CONFIG_MCHP_QMSPI_TX_DMA
 
-#define QMSPI_ERR_ANY			0x80
-#define QMSPI_ERR_BAD_PTR		0x81
-#define QMSPI_ERR_OUT_OF_DESCR		0x85
+#define QMSPI_ERR_ANY 0x80
+#define QMSPI_ERR_BAD_PTR 0x81
+#define QMSPI_ERR_OUT_OF_DESCR 0x85
 
 /*
  * bits[1:0] of word
@@ -206,9 +204,9 @@ static void qmspi_descr_mode_ready(void)
 	int i;
 
 	MCHP_QMSPI0_CTRL = 0;
-	MCHP_QMSPI0_IEN  = 0;
-	MCHP_QMSPI0_EXE  = MCHP_QMSPI_EXE_CLR_FIFOS;
-	MCHP_QMSPI0_STS  = 0xfffffffful;
+	MCHP_QMSPI0_IEN = 0;
+	MCHP_QMSPI0_EXE = MCHP_QMSPI_EXE_CLR_FIFOS;
+	MCHP_QMSPI0_STS = 0xfffffffful;
 	MCHP_QMSPI0_CTRL = MCHP_QMSPI_C_DESCR_MODE_EN;
 	/* clear all descriptors */
 	for (i = 0; i < MCHP_QMSPI_MAX_DESCR; i++)
@@ -229,8 +227,7 @@ static void qmspi_descr_mode_ready(void)
  * and remaining < 16 bytes in byte unit descriptor until all bytes
  * exhausted or out of descriptors error.
  */
-static uint32_t qmspi_descr_alloc(uint32_t did,
-				uint32_t descr, uint32_t nb)
+static uint32_t qmspi_descr_alloc(uint32_t did, uint32_t descr, uint32_t nb)
 {
 	uint32_t nu;
 
@@ -238,8 +235,8 @@ static uint32_t qmspi_descr_alloc(uint32_t did,
 		if (did >= MCHP_QMSPI_MAX_DESCR)
 			return 0xffff;
 
-		descr &= ~(MCHP_QMSPI_C_NUM_UNITS_MASK +
-			MCHP_QMSPI_C_XFRU_MASK);
+		descr &=
+			~(MCHP_QMSPI_C_NUM_UNITS_MASK + MCHP_QMSPI_C_XFRU_MASK);
 
 		if (nb < (MCHP_QMSPI_C_MAX_UNITS + 1)) {
 			descr |= MCHP_QMSPI_C_XFRU_1B;
@@ -252,7 +249,7 @@ static uint32_t qmspi_descr_alloc(uint32_t did,
 			nb -= (nu << 4);
 		}
 
-		descr |= ((did+1) << MCHP_QMSPI_C_NEXT_DESCR_BITPOS);
+		descr |= ((did + 1) << MCHP_QMSPI_C_NEXT_DESCR_BITPOS);
 		MCHP_QMSPI0_DESCR(did) = descr;
 		if (nb)
 			did++;
@@ -271,9 +268,8 @@ static uint32_t qmspi_descr_alloc(uint32_t did,
  * channel and configure the DMA channel for memory to device transfer.
  */
 static uint32_t qmspi_xmit_data_descr(const struct dma_option *opdma,
-					uint32_t cfg,
-					const uint8_t *data,
-					uint32_t ndata)
+				      uint32_t cfg, const uint8_t *data,
+				      uint32_t ndata)
 {
 	uint32_t d, d2, did, dma_cfg;
 
@@ -282,7 +278,7 @@ static uint32_t qmspi_xmit_data_descr(const struct dma_option *opdma,
 
 	if (ndata <= MCHP_QMSPI_TX_FIFO_LEN) {
 		d2 = d + (ndata << MCHP_QMSPI_C_NUM_UNITS_BITPOS) +
-			MCHP_QMSPI_C_XFRU_1B + MCHP_QMSPI_C_TX_DATA;
+		     MCHP_QMSPI_C_XFRU_1B + MCHP_QMSPI_C_TX_DATA;
 		d2 += ((did + 1) << MCHP_QMSPI_C_NEXT_DESCR_BITPOS);
 		MCHP_QMSPI0_DESCR(did) = d2;
 		while (ndata--)
@@ -290,12 +286,10 @@ static uint32_t qmspi_xmit_data_descr(const struct dma_option *opdma,
 	} else { // TX DMA
 		if (((uint32_t)data | ndata) & 0x03) {
 			dma_cfg = 1;
-			d |= (MCHP_QMSPI_C_TX_DATA +
-				MCHP_QMSPI_C_TX_DMA_1B);
+			d |= (MCHP_QMSPI_C_TX_DATA + MCHP_QMSPI_C_TX_DMA_1B);
 		} else {
 			dma_cfg = 4;
-			d |= (MCHP_QMSPI_C_TX_DATA +
-				MCHP_QMSPI_C_TX_DMA_4B);
+			d |= (MCHP_QMSPI_C_TX_DATA + MCHP_QMSPI_C_TX_DMA_4B);
 		}
 		did = qmspi_descr_alloc(did, d, ndata);
 		if (did == 0xffff)
@@ -303,10 +297,9 @@ static uint32_t qmspi_xmit_data_descr(const struct dma_option *opdma,
 
 		dma_clr_chan(opdma->channel);
 		dma_cfg_buffers(opdma->channel, data, ndata,
-			(void *)MCHP_QMSPI0_TX_FIFO_ADDR);
-		dma_cfg_xfr(opdma->channel, dma_cfg,
-			MCHP_DMA_QMSPI0_TX_REQ_ID,
-			(DMA_FLAG_M2D + DMA_FLAG_INCR_MEM));
+				(void *)MCHP_QMSPI0_TX_FIFO_ADDR);
+		dma_cfg_xfr(opdma->channel, dma_cfg, MCHP_DMA_QMSPI0_TX_REQ_ID,
+			    (DMA_FLAG_M2D + DMA_FLAG_INCR_MEM));
 		dma_run(opdma->channel);
 	}
 
@@ -327,8 +320,8 @@ void qmspi_cfg_irq_start(uint8_t flags)
 	MCHP_QMSPI0_IEN = 0;
 
 	if (flags & (1u << 1)) {
-		MCHP_QMSPI0_IEN = (MCHP_QMSPI_STS_DONE +
-			MCHP_QMSPI_STS_PROG_ERR);
+		MCHP_QMSPI0_IEN =
+			(MCHP_QMSPI_STS_DONE + MCHP_QMSPI_STS_PROG_ERR);
 		MCHP_INT_ENABLE(MCHP_QMSPI_GIRQ) = MCHP_QMSPI_GIRQ_BIT;
 	}
 
@@ -349,10 +342,9 @@ void qmspi_cfg_irq_start(uint8_t flags)
  * returns last descriptor 0 <= index < MCHP_QMSPI_MAX_DESCR
  * or error (bit[7]==1)
  */
-uint8_t qmspi_xfr(const struct spi_device_t *spi_device,
-			uint32_t np_flags,
-			const uint8_t *txdata, uint32_t ntx,
-			uint8_t *rxdata, uint32_t nrx)
+uint8_t qmspi_xfr(const struct spi_device_t *spi_device, uint32_t np_flags,
+		  const uint8_t *txdata, uint32_t ntx, uint8_t *rxdata,
+		  uint32_t nrx)
 {
 	uint32_t d, did, dma_cfg;
 	const struct dma_option *opdma;
@@ -399,10 +391,9 @@ uint8_t qmspi_xfr(const struct spi_device_t *spi_device,
 		opdma = spi_dma_option(spi_device, SPI_DMA_OPTION_RD);
 		dma_clr_chan(opdma->channel);
 		dma_cfg_buffers(opdma->channel, rxdata, nrx,
-			(void *)MCHP_QMSPI0_RX_FIFO_ADDR);
-		dma_cfg_xfr(opdma->channel, dma_cfg,
-			MCHP_DMA_QMSPI0_RX_REQ_ID,
-			(DMA_FLAG_D2M + DMA_FLAG_INCR_MEM));
+				(void *)MCHP_QMSPI0_RX_FIFO_ADDR);
+		dma_cfg_xfr(opdma->channel, dma_cfg, MCHP_DMA_QMSPI0_RX_REQ_ID,
+			    (DMA_FLAG_D2M + DMA_FLAG_INCR_MEM));
 		dma_run(opdma->channel);
 	}
 
@@ -466,8 +457,8 @@ uint8_t qmspi_xfr(const struct spi_device_t *spi_device,
  */
 #ifdef CONFIG_MCHP_QMSPI_TX_DMA
 int qmspi_transaction_async(const struct spi_device_t *spi_device,
-				const uint8_t *txdata, int txlen,
-				uint8_t *rxdata, int rxlen)
+			    const uint8_t *txdata, int txlen, uint8_t *rxdata,
+			    int rxlen)
 {
 	uint32_t np_flags, ntx, nrx;
 	int ret;
@@ -482,9 +473,7 @@ int qmspi_transaction_async(const struct spi_device_t *spi_device,
 		nrx = (uint32_t)rxlen;
 
 	np_flags = 0x010105; /* b[0]=1 close on done, b[2]=1 start */
-	rc = qmspi_xfr(spi_device, np_flags,
-			txdata, ntx,
-			rxdata, nrx);
+	rc = qmspi_xfr(spi_device, np_flags, txdata, ntx, rxdata, nrx);
 
 	if (rc & QMSPI_ERR_ANY)
 		return EC_ERROR_INVAL;
@@ -498,8 +487,8 @@ int qmspi_transaction_async(const struct spi_device_t *spi_device,
  * Receive using DMA as above.
  */
 int qmspi_transaction_async(const struct spi_device_t *spi_device,
-				const uint8_t *txdata, int txlen,
-				uint8_t *rxdata, int rxlen)
+			    const uint8_t *txdata, int txlen, uint8_t *rxdata,
+			    int rxlen)
 {
 	const struct dma_option *opdma;
 	uint32_t d, did, dmau;
@@ -533,8 +522,7 @@ int qmspi_transaction_async(const struct spi_device_t *spi_device,
 		if (rxdata == NULL)
 			return EC_ERROR_PARAM4;
 
-		u = qmspi_build_rx_descr((uint32_t)rxdata,
-				(uint32_t)rxlen, 2);
+		u = qmspi_build_rx_descr((uint32_t)rxdata, (uint32_t)rxlen, 2);
 
 		d = (uint32_t)u;
 		dmau = u >> 32;
@@ -547,16 +535,16 @@ int qmspi_transaction_async(const struct spi_device_t *spi_device,
 		dma_xfr_start_rx(opdma, dmau, (uint32_t)rxlen, rxdata);
 	}
 
-	MCHP_QMSPI0_DESCR(did) |= (MCHP_QMSPI_C_CLOSE +
-			MCHP_QMSPI_C_DESCR_LAST);
+	MCHP_QMSPI0_DESCR(did) |=
+		(MCHP_QMSPI_C_CLOSE + MCHP_QMSPI_C_DESCR_LAST);
 
 	MCHP_QMSPI0_EXE = MCHP_QMSPI_EXE_START;
 
 	while (txlen--) {
 		if (MCHP_QMSPI0_STS & MCHP_QMSPI_STS_TX_BUFF_FULL) {
 			if (qmspi_wait(MCHP_QMSPI_STS_TX_BUFF_EMPTY,
-					MCHP_QMSPI_STS_TX_BUFF_EMPTY) !=
-							EC_SUCCESS) {
+				       MCHP_QMSPI_STS_TX_BUFF_EMPTY) !=
+			    EC_SUCCESS) {
 				MCHP_QMSPI0_EXE = MCHP_QMSPI_EXE_STOP;
 				return EC_ERROR_TIMEOUT;
 			}
@@ -673,8 +661,8 @@ int qmspi_enable(int hw_port, int enable)
 {
 	uint8_t unused __attribute__((unused)) = 0;
 
-	trace2(0, QMSPI, 0, "qmspi_enable: port = %d enable = %d",
-			hw_port, enable);
+	trace2(0, QMSPI, 0, "qmspi_enable: port = %d enable = %d", hw_port,
+	       enable);
 
 	if (hw_port != QMSPI0_PORT)
 		return EC_ERROR_INVAL;
@@ -685,9 +673,9 @@ int qmspi_enable(int hw_port, int enable)
 		MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_QMSPI);
 		MCHP_QMSPI0_MODE_ACT_SRST = MCHP_QMSPI_M_SOFT_RESET;
 		unused = MCHP_QMSPI0_MODE_ACT_SRST;
-		MCHP_QMSPI0_MODE = (MCHP_QMSPI_M_ACTIVATE +
-				MCHP_QMSPI_M_SPI_MODE0 +
-				MCHP_QMSPI_M_CLKDIV_12M);
+		MCHP_QMSPI0_MODE =
+			(MCHP_QMSPI_M_ACTIVATE + MCHP_QMSPI_M_SPI_MODE0 +
+			 MCHP_QMSPI_M_CLKDIV_12M);
 	} else {
 		MCHP_QMSPI0_MODE_ACT_SRST = MCHP_QMSPI_M_SOFT_RESET;
 		unused = MCHP_QMSPI0_MODE_ACT_SRST;
diff --git a/chip/mchp/qmspi_chip.h b/chip/mchp/qmspi_chip.h
index 1db440b868..5a66c34e62 100644
--- a/chip/mchp/qmspi_chip.h
+++ b/chip/mchp/qmspi_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,18 +19,17 @@
 /* struct spi_device_t */
 #include "spi.h"
 
-
 int qmspi_transaction_flush(const struct spi_device_t *spi_device);
 
 int qmspi_transaction_wait(const struct spi_device_t *spi_device);
 
 int qmspi_transaction_sync(const struct spi_device_t *spi_device,
-				const uint8_t *txdata, int txlen,
-				uint8_t *rxdata, int rxlen);
+			   const uint8_t *txdata, int txlen, uint8_t *rxdata,
+			   int rxlen);
 
 int qmspi_transaction_async(const struct spi_device_t *spi_device,
-				const uint8_t *txdata, int txlen,
-				uint8_t *rxdata, int rxlen);
+			    const uint8_t *txdata, int txlen, uint8_t *rxdata,
+			    int rxlen);
 
 int qmspi_enable(int port, int enable);
 
@@ -56,10 +55,9 @@ void qmspi_cfg_irq_start(uint8_t flags);
  * returns last descriptor 0 <= index < MCHP_QMSPI_MAX_DESCR
  * or error (bit[7]==1)
  */
-uint8_t qmspi_xfr(const struct spi_device_t *spi_device,
-			uint32_t np_flags,
-			const uint8_t *txdata, uint32_t ntx,
-			uint8_t *rxdata, uint32_t nrx);
+uint8_t qmspi_xfr(const struct spi_device_t *spi_device, uint32_t np_flags,
+		  const uint8_t *txdata, uint32_t ntx, uint8_t *rxdata,
+		  uint32_t nrx);
 
 #endif /* #ifndef _QMSPI_CHIP_H */
 /**   @}
diff --git a/chip/mchp/registers-mec152x.h b/chip/mchp/registers-mec152x.h
index 10021ede8b..166ca63310 100644
--- a/chip/mchp/registers-mec152x.h
+++ b/chip/mchp/registers-mec152x.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -14,196 +14,196 @@
  * NOTE: GIRQ22 aggregated output and its sources are not connected to
  * the NVIC.
  */
-#define MCHP_IRQ_GIRQ8		0
-#define MCHP_IRQ_GIRQ9		1
-#define MCHP_IRQ_GIRQ10		2
-#define MCHP_IRQ_GIRQ11		3
-#define MCHP_IRQ_GIRQ12		4
-#define MCHP_IRQ_GIRQ13		5
-#define MCHP_IRQ_GIRQ14		6
-#define MCHP_IRQ_GIRQ15		7
-#define MCHP_IRQ_GIRQ16		8
-#define MCHP_IRQ_GIRQ17		9
-#define MCHP_IRQ_GIRQ18		10
-#define MCHP_IRQ_GIRQ19		11
-#define MCHP_IRQ_GIRQ20		12
-#define MCHP_IRQ_GIRQ21		13
-#define MCHP_IRQ_GIRQ23		14
-#define MCHP_IRQ_GIRQ24		15
-#define MCHP_IRQ_GIRQ25		16
-#define MCHP_IRQ_GIRQ26		17
+#define MCHP_IRQ_GIRQ8 0
+#define MCHP_IRQ_GIRQ9 1
+#define MCHP_IRQ_GIRQ10 2
+#define MCHP_IRQ_GIRQ11 3
+#define MCHP_IRQ_GIRQ12 4
+#define MCHP_IRQ_GIRQ13 5
+#define MCHP_IRQ_GIRQ14 6
+#define MCHP_IRQ_GIRQ15 7
+#define MCHP_IRQ_GIRQ16 8
+#define MCHP_IRQ_GIRQ17 9
+#define MCHP_IRQ_GIRQ18 10
+#define MCHP_IRQ_GIRQ19 11
+#define MCHP_IRQ_GIRQ20 12
+#define MCHP_IRQ_GIRQ21 13
+#define MCHP_IRQ_GIRQ23 14
+#define MCHP_IRQ_GIRQ24 15
+#define MCHP_IRQ_GIRQ25 16
+#define MCHP_IRQ_GIRQ26 17
 /* GIRQ13 direct sources */
-#define MCHP_IRQ_I2C_0		20
-#define MCHP_IRQ_I2C_1		21
-#define MCHP_IRQ_I2C_2		22
-#define MCHP_IRQ_I2C_3		23
-#define MCHP_IRQ_I2C_4		158
-#define MCHP_IRQ_I2C_5		168
-#define MCHP_IRQ_I2C_6		169
-#define MCHP_IRQ_I2C_7		170
+#define MCHP_IRQ_I2C_0 20
+#define MCHP_IRQ_I2C_1 21
+#define MCHP_IRQ_I2C_2 22
+#define MCHP_IRQ_I2C_3 23
+#define MCHP_IRQ_I2C_4 158
+#define MCHP_IRQ_I2C_5 168
+#define MCHP_IRQ_I2C_6 169
+#define MCHP_IRQ_I2C_7 170
 /* GIRQ14 direct sources */
-#define MCHP_IRQ_DMA_0		24
-#define MCHP_IRQ_DMA_1		25
-#define MCHP_IRQ_DMA_2		26
-#define MCHP_IRQ_DMA_3		27
-#define MCHP_IRQ_DMA_4		28
-#define MCHP_IRQ_DMA_5		29
-#define MCHP_IRQ_DMA_6		30
-#define MCHP_IRQ_DMA_7		31
-#define MCHP_IRQ_DMA_8		32
-#define MCHP_IRQ_DMA_9		33
-#define MCHP_IRQ_DMA_10		34
-#define MCHP_IRQ_DMA_11		35
+#define MCHP_IRQ_DMA_0 24
+#define MCHP_IRQ_DMA_1 25
+#define MCHP_IRQ_DMA_2 26
+#define MCHP_IRQ_DMA_3 27
+#define MCHP_IRQ_DMA_4 28
+#define MCHP_IRQ_DMA_5 29
+#define MCHP_IRQ_DMA_6 30
+#define MCHP_IRQ_DMA_7 31
+#define MCHP_IRQ_DMA_8 32
+#define MCHP_IRQ_DMA_9 33
+#define MCHP_IRQ_DMA_10 34
+#define MCHP_IRQ_DMA_11 35
 /* GIRQ15 direct sources */
-#define MCHP_IRQ_UART0		40
-#define MCHP_IRQ_UART1		41
-#define MCHP_IRQ_EMI0		42
-#define MCHP_IRQ_EMI1		43
-#define MCHP_IRQ_UART2		44
-#define MCHP_IRQ_ACPIEC0_IBF	45
-#define MCHP_IRQ_ACPIEC0_OBE	46
-#define MCHP_IRQ_ACPIEC1_IBF	47
-#define MCHP_IRQ_ACPIEC1_OBE	48
-#define MCHP_IRQ_ACPIEC2_IBF	49
-#define MCHP_IRQ_ACPIEC2_OBE	50
-#define MCHP_IRQ_ACPIEC3_IBF	51
-#define MCHP_IRQ_ACPIEC3_OBE	52
-#define MCHP_IRQ_ACPIPM1_CTL	55
-#define MCHP_IRQ_ACPIPM1_EN	56
-#define MCHP_IRQ_ACPIPM1_STS	57
-#define MCHP_IRQ_8042EM_OBE	58
-#define MCHP_IRQ_8042EM_IBF	59
-#define MCHP_IRQ_MAILBOX_DATA	60
-#define MCHP_IRQ_PORT80DBG0	62
-#define MCHP_IRQ_PORT80DBG1	63
-#define MCHP_IRQ_LASIC		64
+#define MCHP_IRQ_UART0 40
+#define MCHP_IRQ_UART1 41
+#define MCHP_IRQ_EMI0 42
+#define MCHP_IRQ_EMI1 43
+#define MCHP_IRQ_UART2 44
+#define MCHP_IRQ_ACPIEC0_IBF 45
+#define MCHP_IRQ_ACPIEC0_OBE 46
+#define MCHP_IRQ_ACPIEC1_IBF 47
+#define MCHP_IRQ_ACPIEC1_OBE 48
+#define MCHP_IRQ_ACPIEC2_IBF 49
+#define MCHP_IRQ_ACPIEC2_OBE 50
+#define MCHP_IRQ_ACPIEC3_IBF 51
+#define MCHP_IRQ_ACPIEC3_OBE 52
+#define MCHP_IRQ_ACPIPM1_CTL 55
+#define MCHP_IRQ_ACPIPM1_EN 56
+#define MCHP_IRQ_ACPIPM1_STS 57
+#define MCHP_IRQ_8042EM_OBE 58
+#define MCHP_IRQ_8042EM_IBF 59
+#define MCHP_IRQ_MAILBOX_DATA 60
+#define MCHP_IRQ_PORT80DBG0 62
+#define MCHP_IRQ_PORT80DBG1 63
+#define MCHP_IRQ_LASIC 64
 /* GIRQ16 direct sources */
-#define MCHP_IRQ_PKE_ERR	65
-#define MCHP_IRQ_PKE_END	66
-#define MCHP_IRQ_NDRNG		67
-#define MCHP_IRQ_AES		68
-#define MCHP_IRQ_HASH		69
+#define MCHP_IRQ_PKE_ERR 65
+#define MCHP_IRQ_PKE_END 66
+#define MCHP_IRQ_NDRNG 67
+#define MCHP_IRQ_AES 68
+#define MCHP_IRQ_HASH 69
 /* GIRQ17 direct sources */
-#define MCHP_IRQ_PECI_HOST	70
-#define MCHP_IRQ_TACH_0		71
-#define MCHP_IRQ_TACH_1		72
-#define MCHP_IRQ_TACH_2		73
-#define MCHP_IRQ_TACH_3		159
-#define MCHP_IRQ_HDMI_CEC	160
-#define MCHP_IRQ_ADC_SNGL	78
-#define MCHP_IRQ_ADC_RPT	79
-#define MCHP_IRQ_LED0_WDT	83
-#define MCHP_IRQ_LED1_WDT	84
-#define MCHP_IRQ_LED2_WDT	85
-#define MCHP_IRQ_PROCHOT	87
+#define MCHP_IRQ_PECI_HOST 70
+#define MCHP_IRQ_TACH_0 71
+#define MCHP_IRQ_TACH_1 72
+#define MCHP_IRQ_TACH_2 73
+#define MCHP_IRQ_TACH_3 159
+#define MCHP_IRQ_HDMI_CEC 160
+#define MCHP_IRQ_ADC_SNGL 78
+#define MCHP_IRQ_ADC_RPT 79
+#define MCHP_IRQ_LED0_WDT 83
+#define MCHP_IRQ_LED1_WDT 84
+#define MCHP_IRQ_LED2_WDT 85
+#define MCHP_IRQ_PROCHOT 87
 /* GIRQ18 direct sources */
-#define MCHP_IRQ_SLAVE_SPI	90
-#define MCHP_IRQ_QMSPI0		91
-#define MCHP_IRQ_PS2_0		100
-#define MCHP_IRQ_PS2_1		101
-#define MCHP_IRQ_PSPI		155
-#define MCHP_IRQ_SGPIO_0	161
-#define MCHP_IRQ_SGPIO_1	162
-#define MCHP_IRQ_SGPIO_2	163
-#define MCHP_IRQ_SGPIO_3	164
-#define MCHP_IRQ_CCT_TMR	146
-#define MCHP_IRQ_CCT_CAP0	147
-#define MCHP_IRQ_CCT_CAP1	148
-#define MCHP_IRQ_CCT_CAP2	149
-#define MCHP_IRQ_CCT_CAP3	150
-#define MCHP_IRQ_CCT_CAP4	151
-#define MCHP_IRQ_CCT_CAP5	152
-#define MCHP_IRQ_CCT_CMP0	153
-#define MCHP_IRQ_CCT_CMP1	154
+#define MCHP_IRQ_SLAVE_SPI 90
+#define MCHP_IRQ_QMSPI0 91
+#define MCHP_IRQ_PS2_0 100
+#define MCHP_IRQ_PS2_1 101
+#define MCHP_IRQ_PSPI 155
+#define MCHP_IRQ_SGPIO_0 161
+#define MCHP_IRQ_SGPIO_1 162
+#define MCHP_IRQ_SGPIO_2 163
+#define MCHP_IRQ_SGPIO_3 164
+#define MCHP_IRQ_CCT_TMR 146
+#define MCHP_IRQ_CCT_CAP0 147
+#define MCHP_IRQ_CCT_CAP1 148
+#define MCHP_IRQ_CCT_CAP2 149
+#define MCHP_IRQ_CCT_CAP3 150
+#define MCHP_IRQ_CCT_CAP4 151
+#define MCHP_IRQ_CCT_CAP5 152
+#define MCHP_IRQ_CCT_CMP0 153
+#define MCHP_IRQ_CCT_CMP1 154
 /* GIRQ19 direct sources */
-#define MCHP_IRQ_ESPI_PC	103
-#define MCHP_IRQ_ESPI_BM1	104
-#define MCHP_IRQ_ESPI_BM2	105
-#define MCHP_IRQ_ESPI_LTR	106
-#define MCHP_IRQ_ESPI_OOB_UP	107
-#define MCHP_IRQ_ESPI_OOB_DN	108
-#define MCHP_IRQ_ESPI_FC	109
-#define MCHP_IRQ_ESPI_RESET	110
-#define MCHP_IRQ_ESPI_VW_EN	156
+#define MCHP_IRQ_ESPI_PC 103
+#define MCHP_IRQ_ESPI_BM1 104
+#define MCHP_IRQ_ESPI_BM2 105
+#define MCHP_IRQ_ESPI_LTR 106
+#define MCHP_IRQ_ESPI_OOB_UP 107
+#define MCHP_IRQ_ESPI_OOB_DN 108
+#define MCHP_IRQ_ESPI_FC 109
+#define MCHP_IRQ_ESPI_RESET 110
+#define MCHP_IRQ_ESPI_VW_EN 156
 /* GIRQ20 direct sources */
-#define MCHP_IRQ_OTP		173
+#define MCHP_IRQ_OTP 173
 /* GIRQ21 direct sources */
-#define MCHP_IRQ_WDG		171
-#define MCHP_IRQ_WEEK_ALARM	114
-#define MCHP_IRQ_SUBWEEK	115
-#define MCHP_IRQ_WEEK_SEC	116
-#define MCHP_IRQ_WEEK_SUBSEC	117
-#define MCHP_IRQ_WEEK_SYSPWR	118
-#define MCHP_IRQ_RTC		119
-#define MCHP_IRQ_RTC_ALARM	120
-#define MCHP_IRQ_VCI_OVRD_IN	121
-#define MCHP_IRQ_VCI_IN0	122
-#define MCHP_IRQ_VCI_IN1	123
-#define MCHP_IRQ_VCI_IN2	124
-#define MCHP_IRQ_VCI_IN3	125
-#define MCHP_IRQ_PS20A_WAKE	129
-#define MCHP_IRQ_PS20B_WAKE	130
-#define MCHP_IRQ_PS21B_WAKE	132
-#define MCHP_IRQ_KSC_INT	135
+#define MCHP_IRQ_WDG 171
+#define MCHP_IRQ_WEEK_ALARM 114
+#define MCHP_IRQ_SUBWEEK 115
+#define MCHP_IRQ_WEEK_SEC 116
+#define MCHP_IRQ_WEEK_SUBSEC 117
+#define MCHP_IRQ_WEEK_SYSPWR 118
+#define MCHP_IRQ_RTC 119
+#define MCHP_IRQ_RTC_ALARM 120
+#define MCHP_IRQ_VCI_OVRD_IN 121
+#define MCHP_IRQ_VCI_IN0 122
+#define MCHP_IRQ_VCI_IN1 123
+#define MCHP_IRQ_VCI_IN2 124
+#define MCHP_IRQ_VCI_IN3 125
+#define MCHP_IRQ_PS20A_WAKE 129
+#define MCHP_IRQ_PS20B_WAKE 130
+#define MCHP_IRQ_PS21B_WAKE 132
+#define MCHP_IRQ_KSC_INT 135
 /* GIRQ23 direct sources */
-#define MCHP_IRQ_TIMER16_0	136
-#define MCHP_IRQ_TIMER16_1	137
-#define MCHP_IRQ_TIMER32_0	140
-#define MCHP_IRQ_TIMER32_1	141
-#define MCHP_IRQ_RTOS_TIMER	111
-#define MCHP_IRQ_HTIMER0	112
-#define MCHP_IRQ_HTIMER1	113
+#define MCHP_IRQ_TIMER16_0 136
+#define MCHP_IRQ_TIMER16_1 137
+#define MCHP_IRQ_TIMER32_0 140
+#define MCHP_IRQ_TIMER32_1 141
+#define MCHP_IRQ_RTOS_TIMER 111
+#define MCHP_IRQ_HTIMER0 112
+#define MCHP_IRQ_HTIMER1 113
 /* Must match CONFIG_IRQ_COUNT in config_chip.h */
-#define MCHP_IRQ_MAX		174
+#define MCHP_IRQ_MAX 174
 
 /* Block base addresses */
-#define MCHP_WDG_BASE		0x40000400
-#define MCHP_TMR16_0_BASE	0x40000c00
-#define MCHP_TMR32_0_BASE	0x40000c80
-#define MCHP_DMA_BASE		0x40002400
-#define MCHP_PROCHOT_BASE	0x40003400
-#define MCHP_I2C0_BASE		0x40004000
-#define MCHP_I2C1_BASE		0x40004400
-#define MCHP_I2C2_BASE		0x40004800
-#define MCHP_I2C3_BASE		0x40004C00
-#define MCHP_I2C4_BASE		0x40005000
-#define MCHP_I2C5_BASE		0x40005100
-#define MCHP_I2C6_BASE		0x40005200
-#define MCHP_I2C7_BASE		0x40005300
-#define MCHP_QMSPI0_BASE	0x40070000
-#define MCHP_PWM_0_BASE		0x40005800
-#define MCHP_TACH_0_BASE	0x40006000
-#define MCHP_PECI_BASE		0x40006400
-#define MCHP_RTMR_BASE		0x40007400
-#define MCHP_ADC_BASE		0x40007c00
-#define MCHP_TFDP_BASE		0x40008c00
-#define MCHP_HTIMER_BASE	0x40009800
-#define MCHP_KEYSCAN_BASE	0x40009c00
-#define MCHP_VBAT_BASE		0x4000a400
-#define MCHP_VBAT_RAM_BASE	0x4000a800
-#define MCHP_WKTIMER_BASE	0x4000ac80
-#define MCHP_BBLED_0_BASE	0x4000B800
-#define MCHP_INT_BASE		0x4000e000
-#define MCHP_EC_BASE		0x4000fc00
-
-#define MCHP_PCR_BASE		0x40080100
-#define MCHP_GPIO_BASE		0x40081000
-
-#define MCHP_MBOX_BASE		0x400f0000
-#define MCHP_8042_BASE		0x400f0400
-#define MCHP_ACPI_EC_0_BASE	0x400f0800
-#define MCHP_ACPI_PM1_BASE	0x400f1c00
-#define MCHP_UART0_BASE		0x400f2400
-#define MCHP_UART1_BASE		0x400f2800
-#define MCHP_UART2_BASE		0x400f2c00
-#define MCHP_ESPI_IO_BASE	0x400f3400
-#define MCHP_ESPI_MEM_BASE	0x400f3800
-#define MCHP_EMI_0_BASE		0x400f4000
-#define MCHP_EMI_1_BASE		0x400f4400
-#define MCHP_P80CAP0_BASE	0x400f8000
-#define MCHP_P80CAP1_BASE	0x400f8400
-#define MCHP_ESPI_VW_BASE	0x400f9c00
-#define MCHP_CHIP_BASE		0x400fff00
+#define MCHP_WDG_BASE 0x40000400
+#define MCHP_TMR16_0_BASE 0x40000c00
+#define MCHP_TMR32_0_BASE 0x40000c80
+#define MCHP_DMA_BASE 0x40002400
+#define MCHP_PROCHOT_BASE 0x40003400
+#define MCHP_I2C0_BASE 0x40004000
+#define MCHP_I2C1_BASE 0x40004400
+#define MCHP_I2C2_BASE 0x40004800
+#define MCHP_I2C3_BASE 0x40004C00
+#define MCHP_I2C4_BASE 0x40005000
+#define MCHP_I2C5_BASE 0x40005100
+#define MCHP_I2C6_BASE 0x40005200
+#define MCHP_I2C7_BASE 0x40005300
+#define MCHP_QMSPI0_BASE 0x40070000
+#define MCHP_PWM_0_BASE 0x40005800
+#define MCHP_TACH_0_BASE 0x40006000
+#define MCHP_PECI_BASE 0x40006400
+#define MCHP_RTMR_BASE 0x40007400
+#define MCHP_ADC_BASE 0x40007c00
+#define MCHP_TFDP_BASE 0x40008c00
+#define MCHP_HTIMER_BASE 0x40009800
+#define MCHP_KEYSCAN_BASE 0x40009c00
+#define MCHP_VBAT_BASE 0x4000a400
+#define MCHP_VBAT_RAM_BASE 0x4000a800
+#define MCHP_WKTIMER_BASE 0x4000ac80
+#define MCHP_BBLED_0_BASE 0x4000B800
+#define MCHP_INT_BASE 0x4000e000
+#define MCHP_EC_BASE 0x4000fc00
+
+#define MCHP_PCR_BASE 0x40080100
+#define MCHP_GPIO_BASE 0x40081000
+
+#define MCHP_MBOX_BASE 0x400f0000
+#define MCHP_8042_BASE 0x400f0400
+#define MCHP_ACPI_EC_0_BASE 0x400f0800
+#define MCHP_ACPI_PM1_BASE 0x400f1c00
+#define MCHP_UART0_BASE 0x400f2400
+#define MCHP_UART1_BASE 0x400f2800
+#define MCHP_UART2_BASE 0x400f2c00
+#define MCHP_ESPI_IO_BASE 0x400f3400
+#define MCHP_ESPI_MEM_BASE 0x400f3800
+#define MCHP_EMI_0_BASE 0x400f4000
+#define MCHP_EMI_1_BASE 0x400f4400
+#define MCHP_P80CAP0_BASE 0x400f8000
+#define MCHP_P80CAP1_BASE 0x400f8400
+#define MCHP_ESPI_VW_BASE 0x400f9c00
+#define MCHP_CHIP_BASE 0x400fff00
 
 #ifndef __ASSEMBLER__
 
@@ -213,35 +213,34 @@
  * Cortex-M4 bit-banding does require aliasing of the
  * DATA SRAM region.
  */
-#define MCHP_RAM_ALIAS(x) \
-	((x) >= 0x118000 ? (x) - 0x118000 + 0x20000000 : (x))
+#define MCHP_RAM_ALIAS(x) ((x) >= 0x118000 ? (x)-0x118000 + 0x20000000 : (x))
 
 /* EC Chip Configuration */
 /* 16-bit Device ID */
-#define MCHP_CHIP_DEV_ID		REG16(MCHP_CHIP_BASE + 0x1E)
+#define MCHP_CHIP_DEV_ID REG16(MCHP_CHIP_BASE + 0x1E)
 /* 8-bit Device Sub ID */
-#define MCHP_CHIP_DEV_SUB_ID		REG8(MCHP_CHIP_BASE + 0x1D)
+#define MCHP_CHIP_DEV_SUB_ID REG8(MCHP_CHIP_BASE + 0x1D)
 /* 8-bit Device Revision */
-#define MCHP_CHIP_DEV_REV		REG8(MCHP_CHIP_BASE + 0x1C)
+#define MCHP_CHIP_DEV_REV REG8(MCHP_CHIP_BASE + 0x1C)
 /* All in one */
-#define MCHP_CHIP_DEVRID32		REG32(MCHP_CHIP_BASE + 0x1C)
-#define MCHP_CHIP_DEVID_POS		16
-#define MCHP_CHIP_DEVID_MASK		(0xfffful << MCHP_CHIP_DEVID_POS)
-#define MCHP_CHIP_SUBID_POS		8
-#define MCHP_CHIP_SUBID_MASK		(0xfful << MCHP_CHIP_SUBID_POS)
-#define MCHP_CHIP_REV_POS		0
-#define MCHP_CHIP_REV_MASK		(0xfful << MCHP_CHIP_REV_POS)
+#define MCHP_CHIP_DEVRID32 REG32(MCHP_CHIP_BASE + 0x1C)
+#define MCHP_CHIP_DEVID_POS 16
+#define MCHP_CHIP_DEVID_MASK (0xfffful << MCHP_CHIP_DEVID_POS)
+#define MCHP_CHIP_SUBID_POS 8
+#define MCHP_CHIP_SUBID_MASK (0xfful << MCHP_CHIP_SUBID_POS)
+#define MCHP_CHIP_REV_POS 0
+#define MCHP_CHIP_REV_MASK (0xfful << MCHP_CHIP_REV_POS)
 #define MCHP_CHIP_EXTRACT_DEVID(d) \
-	(((uint32_t)(d) & MCHP_CHIP_DEVID_MASK) >> MCHP_CHIP_DEVID_POS)
+	(((uint32_t)(d)&MCHP_CHIP_DEVID_MASK) >> MCHP_CHIP_DEVID_POS)
 #define MCHP_CHIP_EXTRACT_SUBID(d) \
-	(((uint32_t)(d) & MCHP_CHIP_SUBID_MASK) >> MCHP_CHIP_SUBID_POS)
+	(((uint32_t)(d)&MCHP_CHIP_SUBID_MASK) >> MCHP_CHIP_SUBID_POS)
 #define MCHP_CHIP_EXTRACT_REV(d) \
-	(((uint32_t)(d) & MCHP_CHIP_REV_MASK) >> MCHP_CHIP_REV_POS)
+	(((uint32_t)(d)&MCHP_CHIP_REV_MASK) >> MCHP_CHIP_REV_POS)
 
 /* PCR clock control dividers */
-#define MCHP_PCR_CLK_CTL_FASTEST	1U
-#define MCHP_PCR_CLK_CTL_48MHZ		1U
-#define MCHP_PCR_CLK_CTL_12MHZ		4U
+#define MCHP_PCR_CLK_CTL_FASTEST 1U
+#define MCHP_PCR_CLK_CTL_48MHZ 1U
+#define MCHP_PCR_CLK_CTL_12MHZ 4U
 
 /*
  * PCR Peripheral Reset Lock register
@@ -251,296 +250,295 @@
  * register, write to PCR reset enable register(s), and
  * write a lock value.
  */
-#define MCHP_PCR_RST_LOCK		REG32(MCHP_PCR_BASE + 0x84)
-#define MCHP_PCR_RST_LOCK_VAL		0xa6382d4d
-#define MCHP_PCR_RST_UNLOCK_VAL		0xa6382d4c
+#define MCHP_PCR_RST_LOCK REG32(MCHP_PCR_BASE + 0x84)
+#define MCHP_PCR_RST_LOCK_VAL 0xa6382d4d
+#define MCHP_PCR_RST_UNLOCK_VAL 0xa6382d4c
 
 /* Number of PCR Sleep Enable, Clock Required, and Reset registers */
-#define MCHP_PCR_SLP_RST_REG_MAX	5
+#define MCHP_PCR_SLP_RST_REG_MAX 5
 
 /* MC152x new bit allow sleep entry when PLL is not locked */
-#define MCHP_PCR_SYS_SLP_NO_PLL		BIT(8)
+#define MCHP_PCR_SYS_SLP_NO_PLL BIT(8)
 
 /* Sleep 0: Sleep Enable, Clock Required, and Reset bits */
-#define MCHP_PCR_JTAG	BIT(0) /* CLKREQ only */
-#define MCHP_PCR_OTP	BIT(1)
+#define MCHP_PCR_JTAG BIT(0) /* CLKREQ only */
+#define MCHP_PCR_OTP BIT(1)
 
 /* Command all blocks to sleep */
-#define MCHP_PCR_SLP_EN0_JTAG	BIT(0)
-#define MCHP_PCR_SLP_EN0_OTP	BIT(1)
-#define MCHP_PCR_SLP_EN0_SLEEP	0xffffffff
+#define MCHP_PCR_SLP_EN0_JTAG BIT(0)
+#define MCHP_PCR_SLP_EN0_OTP BIT(1)
+#define MCHP_PCR_SLP_EN0_SLEEP 0xffffffff
 
 /*
  * Encode register number and bit position
  * b[4:0] = bit number
  * b[10:8] = zero based register number
  */
-#define MCHP_PCR_ERB(rnum, bnum) \
-	((((rnum) & 0x0f) << 8) | ((bnum) & 0x1f))
+#define MCHP_PCR_ERB(rnum, bnum) ((((rnum)&0x0f) << 8) | ((bnum)&0x1f))
 
 /* PCR Sleep 1: Sleep Enable, Clock Required, and Reset bits */
-#define MCHP_PCR_BTMR16_1	MCHP_PCR_ERB(1, 31)
-#define MCHP_PCR_BTMR16_0	MCHP_PCR_ERB(1, 30)
-#define MCHP_PCR_ECS		MCHP_PCR_ERB(1, 29)
-#define MCHP_PCR_PWM8		MCHP_PCR_ERB(1, 27)
-#define MCHP_PCR_PWM7		MCHP_PCR_ERB(1, 26)
-#define MCHP_PCR_PWM6		MCHP_PCR_ERB(1, 25)
-#define MCHP_PCR_PWM5		MCHP_PCR_ERB(1, 24)
-#define MCHP_PCR_PWM4		MCHP_PCR_ERB(1, 23)
-#define MCHP_PCR_PWM3		MCHP_PCR_ERB(1, 22)
-#define MCHP_PCR_PWM2		MCHP_PCR_ERB(1, 21)
-#define MCHP_PCR_PWM1		MCHP_PCR_ERB(1, 20)
-#define MCHP_PCR_TACH3		MCHP_PCR_ERB(1, 13)
-#define MCHP_PCR_TACH2		MCHP_PCR_ERB(1, 12)
-#define MCHP_PCR_TACH1		MCHP_PCR_ERB(1, 11)
-#define MCHP_PCR_I2C0		MCHP_PCR_ERB(1, 10)
-#define MCHP_PCR_WDT		MCHP_PCR_ERB(1, 9)
-#define MCHP_PCR_CPU		MCHP_PCR_ERB(1, 8)
-#define MCHP_PCR_TFDP		MCHP_PCR_ERB(1, 7)
-#define MCHP_PCR_DMA		MCHP_PCR_ERB(1, 6)
-#define MCHP_PCR_PMC		MCHP_PCR_ERB(1, 5)
-#define MCHP_PCR_PWM0		MCHP_PCR_ERB(1, 4)
-#define MCHP_PCR_TACH0		MCHP_PCR_ERB(1, 2)
-#define MCHP_PCR_PECI		MCHP_PCR_ERB(1, 1)
-#define MCHP_PCR_ECIA		MCHP_PCR_ERB(1, 0)
+#define MCHP_PCR_BTMR16_1 MCHP_PCR_ERB(1, 31)
+#define MCHP_PCR_BTMR16_0 MCHP_PCR_ERB(1, 30)
+#define MCHP_PCR_ECS MCHP_PCR_ERB(1, 29)
+#define MCHP_PCR_PWM8 MCHP_PCR_ERB(1, 27)
+#define MCHP_PCR_PWM7 MCHP_PCR_ERB(1, 26)
+#define MCHP_PCR_PWM6 MCHP_PCR_ERB(1, 25)
+#define MCHP_PCR_PWM5 MCHP_PCR_ERB(1, 24)
+#define MCHP_PCR_PWM4 MCHP_PCR_ERB(1, 23)
+#define MCHP_PCR_PWM3 MCHP_PCR_ERB(1, 22)
+#define MCHP_PCR_PWM2 MCHP_PCR_ERB(1, 21)
+#define MCHP_PCR_PWM1 MCHP_PCR_ERB(1, 20)
+#define MCHP_PCR_TACH3 MCHP_PCR_ERB(1, 13)
+#define MCHP_PCR_TACH2 MCHP_PCR_ERB(1, 12)
+#define MCHP_PCR_TACH1 MCHP_PCR_ERB(1, 11)
+#define MCHP_PCR_I2C0 MCHP_PCR_ERB(1, 10)
+#define MCHP_PCR_WDT MCHP_PCR_ERB(1, 9)
+#define MCHP_PCR_CPU MCHP_PCR_ERB(1, 8)
+#define MCHP_PCR_TFDP MCHP_PCR_ERB(1, 7)
+#define MCHP_PCR_DMA MCHP_PCR_ERB(1, 6)
+#define MCHP_PCR_PMC MCHP_PCR_ERB(1, 5)
+#define MCHP_PCR_PWM0 MCHP_PCR_ERB(1, 4)
+#define MCHP_PCR_TACH0 MCHP_PCR_ERB(1, 2)
+#define MCHP_PCR_PECI MCHP_PCR_ERB(1, 1)
+#define MCHP_PCR_ECIA MCHP_PCR_ERB(1, 0)
 
 /* Command all blocks to sleep */
-#define MCHP_PCR_SLP_EN1_BTMR16_1	BIT(31)
-#define MCHP_PCR_SLP_EN1_BTMR16_0	BIT(30)
-#define MCHP_PCR_SLP_EN1_ECS		BIT(29)
-#define MCHP_PCR_SLP_EN1_PWM_ALL	(BIT(4) + (0xff << 20))
-#define MCHP_PCR_SLP_EN1_PWM8		BIT(27)
-#define MCHP_PCR_SLP_EN1_PWM7		BIT(26)
-#define MCHP_PCR_SLP_EN1_PWM6		BIT(25)
-#define MCHP_PCR_SLP_EN1_PWM5		BIT(24)
-#define MCHP_PCR_SLP_EN1_PWM4		BIT(23)
-#define MCHP_PCR_SLP_EN1_PWM3		BIT(22)
-#define MCHP_PCR_SLP_EN1_PWM2		BIT(21)
-#define MCHP_PCR_SLP_EN1_PWM1		BIT(20)
-#define MCHP_PCR_SLP_EN1_TACH3		BIT(13)
-#define MCHP_PCR_SLP_EN1_TACH2		BIT(12)
-#define MCHP_PCR_SLP_EN1_TACH1		BIT(11)
-#define MCHP_PCR_SLP_EN1_I2C0		BIT(10)
-#define MCHP_PCR_SLP_EN1_WDT		BIT(9)
-#define MCHP_PCR_SLP_EN1_CPU		BIT(8)
-#define MCHP_PCR_SLP_EN1_TFDP		BIT(7)
-#define MCHP_PCR_SLP_EN1_DMA		BIT(6)
-#define MCHP_PCR_SLP_EN1_PMC		BIT(5)
-#define MCHP_PCR_SLP_EN1_PWM0		BIT(4)
-#define MCHP_PCR_SLP_EN1_TACH0		BIT(2)
-#define MCHP_PCR_SLP_EN1_PECI		BIT(1)
-#define MCHP_PCR_SLP_EN1_ECIA		BIT(0)
+#define MCHP_PCR_SLP_EN1_BTMR16_1 BIT(31)
+#define MCHP_PCR_SLP_EN1_BTMR16_0 BIT(30)
+#define MCHP_PCR_SLP_EN1_ECS BIT(29)
+#define MCHP_PCR_SLP_EN1_PWM_ALL (BIT(4) + (0xff << 20))
+#define MCHP_PCR_SLP_EN1_PWM8 BIT(27)
+#define MCHP_PCR_SLP_EN1_PWM7 BIT(26)
+#define MCHP_PCR_SLP_EN1_PWM6 BIT(25)
+#define MCHP_PCR_SLP_EN1_PWM5 BIT(24)
+#define MCHP_PCR_SLP_EN1_PWM4 BIT(23)
+#define MCHP_PCR_SLP_EN1_PWM3 BIT(22)
+#define MCHP_PCR_SLP_EN1_PWM2 BIT(21)
+#define MCHP_PCR_SLP_EN1_PWM1 BIT(20)
+#define MCHP_PCR_SLP_EN1_TACH3 BIT(13)
+#define MCHP_PCR_SLP_EN1_TACH2 BIT(12)
+#define MCHP_PCR_SLP_EN1_TACH1 BIT(11)
+#define MCHP_PCR_SLP_EN1_I2C0 BIT(10)
+#define MCHP_PCR_SLP_EN1_WDT BIT(9)
+#define MCHP_PCR_SLP_EN1_CPU BIT(8)
+#define MCHP_PCR_SLP_EN1_TFDP BIT(7)
+#define MCHP_PCR_SLP_EN1_DMA BIT(6)
+#define MCHP_PCR_SLP_EN1_PMC BIT(5)
+#define MCHP_PCR_SLP_EN1_PWM0 BIT(4)
+#define MCHP_PCR_SLP_EN1_TACH0 BIT(2)
+#define MCHP_PCR_SLP_EN1_PECI BIT(1)
+#define MCHP_PCR_SLP_EN1_ECIA BIT(0)
 /* all sleep enable 1 bits */
-#define MCHP_PCR_SLP_EN1_SLEEP		0xffffffff
+#define MCHP_PCR_SLP_EN1_SLEEP 0xffffffff
 /*
  * block not used by default
  * Do not sleep ECIA, PMC, CPU and ECS
  */
-#define MCHP_PCR_SLP_EN1_UNUSED_BLOCKS	0xdffffede
+#define MCHP_PCR_SLP_EN1_UNUSED_BLOCKS 0xdffffede
 
 /* PCR Sleep 2: Sleep Enable, Clock Required 2, Reset bits */
-#define MCHP_PCR_GLUE		MCHP_PCR_ERB(2, 29)
-#define MCHP_PCR_UART2		MCHP_PCR_ERB(2, 28)
-#define MCHP_PCR_SAF		MCHP_PCR_ERB(2, 27)
-#define MCHP_PCR_P80CAP1	MCHP_PCR_ERB(2, 26)
-#define MCHP_PCR_P80CAP0	MCHP_PCR_ERB(2, 25)
-#define MCHP_PCR_ASIF		MCHP_PCR_ERB(2, 24)
-#define MCHP_PCR_ACPI_EC3	MCHP_PCR_ERB(2, 22)
-#define MCHP_PCR_ACPI_EC2	MCHP_PCR_ERB(2, 21)
-#define MCHP_PCR_ESPI_SCR	MCHP_PCR_ERB(2, 20)
-#define MCHP_PCR_ESPI		MCHP_PCR_ERB(2, 19)
-#define MCHP_PCR_RTC		MCHP_PCR_ERB(2, 18)
-#define MCHP_PCR_MBOX		MCHP_PCR_ERB(2, 17)
-#define MCHP_PCR_8042		MCHP_PCR_ERB(2, 26)
-#define MCHP_PCR_ACPI_PM1	MCHP_PCR_ERB(2, 15)
-#define MCHP_PCR_ACPI_EC1	MCHP_PCR_ERB(2, 14)
-#define MCHP_PCR_ACPI_EC0	MCHP_PCR_ERB(2, 13)
-#define MCHP_PCR_GCFG		MCHP_PCR_ERB(2, 12)
-#define MCHP_PCR_UART1		MCHP_PCR_ERB(2, 2)
-#define MCHP_PCR_UART0		MCHP_PCR_ERB(2, 1)
-#define MCHP_PCR_EMI0		MCHP_PCR_ERB(2, 0)
+#define MCHP_PCR_GLUE MCHP_PCR_ERB(2, 29)
+#define MCHP_PCR_UART2 MCHP_PCR_ERB(2, 28)
+#define MCHP_PCR_SAF MCHP_PCR_ERB(2, 27)
+#define MCHP_PCR_P80CAP1 MCHP_PCR_ERB(2, 26)
+#define MCHP_PCR_P80CAP0 MCHP_PCR_ERB(2, 25)
+#define MCHP_PCR_ASIF MCHP_PCR_ERB(2, 24)
+#define MCHP_PCR_ACPI_EC3 MCHP_PCR_ERB(2, 22)
+#define MCHP_PCR_ACPI_EC2 MCHP_PCR_ERB(2, 21)
+#define MCHP_PCR_ESPI_SCR MCHP_PCR_ERB(2, 20)
+#define MCHP_PCR_ESPI MCHP_PCR_ERB(2, 19)
+#define MCHP_PCR_RTC MCHP_PCR_ERB(2, 18)
+#define MCHP_PCR_MBOX MCHP_PCR_ERB(2, 17)
+#define MCHP_PCR_8042 MCHP_PCR_ERB(2, 26)
+#define MCHP_PCR_ACPI_PM1 MCHP_PCR_ERB(2, 15)
+#define MCHP_PCR_ACPI_EC1 MCHP_PCR_ERB(2, 14)
+#define MCHP_PCR_ACPI_EC0 MCHP_PCR_ERB(2, 13)
+#define MCHP_PCR_GCFG MCHP_PCR_ERB(2, 12)
+#define MCHP_PCR_UART1 MCHP_PCR_ERB(2, 2)
+#define MCHP_PCR_UART0 MCHP_PCR_ERB(2, 1)
+#define MCHP_PCR_EMI0 MCHP_PCR_ERB(2, 0)
 
 /* Command all blocks to sleep */
-#define MCHP_PCR_SLP_EN2_GLUE		BIT(29)
-#define MCHP_PCR_SLP_EN2_UART2		BIT(28)
-#define MCHP_PCR_SLP_EN2_SAF		BIT(27)
-#define MCHP_PCR_SLP_EN2_P80CAP1	BIT(26)
-#define MCHP_PCR_SLP_EN2_P80CAP0	BIT(25)
-#define MCHP_PCR_SLP_EN2_ASIF		BIT(24)
-#define MCHP_PCR_SLP_EN2_ACPI_EC3	BIT(22)
-#define MCHP_PCR_SLP_EN2_ACPI_EC2	BIT(21)
-#define MCHP_PCR_SLP_EN2_ESPI_SCR	BIT(20)
-#define MCHP_PCR_SLP_EN2_ESPI		BIT(19)
-#define MCHP_PCR_SLP_EN2_RTC		BIT(18)
-#define MCHP_PCR_SLP_EN2_MAILBOX	BIT(17)
-#define MCHP_PCR_SLP_EN2_MIF8042	BIT(16)
-#define MCHP_PCR_SLP_EN2_ACPI_PM1	BIT(15)
-#define MCHP_PCR_SLP_EN2_ACPI_EC1	BIT(14)
-#define MCHP_PCR_SLP_EN2_ACPI_EC0	BIT(13)
-#define MCHP_PCR_SLP_EN2_GCFG		BIT(12)
-#define MCHP_PCR_SLP_EN2_UART1		BIT(2)
-#define MCHP_PCR_SLP_EN2_UART0		BIT(1)
-#define MCHP_PCR_SLP_EN2_EMI0		BIT(0)
+#define MCHP_PCR_SLP_EN2_GLUE BIT(29)
+#define MCHP_PCR_SLP_EN2_UART2 BIT(28)
+#define MCHP_PCR_SLP_EN2_SAF BIT(27)
+#define MCHP_PCR_SLP_EN2_P80CAP1 BIT(26)
+#define MCHP_PCR_SLP_EN2_P80CAP0 BIT(25)
+#define MCHP_PCR_SLP_EN2_ASIF BIT(24)
+#define MCHP_PCR_SLP_EN2_ACPI_EC3 BIT(22)
+#define MCHP_PCR_SLP_EN2_ACPI_EC2 BIT(21)
+#define MCHP_PCR_SLP_EN2_ESPI_SCR BIT(20)
+#define MCHP_PCR_SLP_EN2_ESPI BIT(19)
+#define MCHP_PCR_SLP_EN2_RTC BIT(18)
+#define MCHP_PCR_SLP_EN2_MAILBOX BIT(17)
+#define MCHP_PCR_SLP_EN2_MIF8042 BIT(16)
+#define MCHP_PCR_SLP_EN2_ACPI_PM1 BIT(15)
+#define MCHP_PCR_SLP_EN2_ACPI_EC1 BIT(14)
+#define MCHP_PCR_SLP_EN2_ACPI_EC0 BIT(13)
+#define MCHP_PCR_SLP_EN2_GCFG BIT(12)
+#define MCHP_PCR_SLP_EN2_UART1 BIT(2)
+#define MCHP_PCR_SLP_EN2_UART0 BIT(1)
+#define MCHP_PCR_SLP_EN2_EMI0 BIT(0)
 /* all sleep enable 2 bits */
-#define MCHP_PCR_SLP_EN2_SLEEP		0xffffffff
+#define MCHP_PCR_SLP_EN2_SLEEP 0xffffffff
 
 /* PCR Sleep 3: Sleep Enable, Clock Required, and Reset */
-#define MCHP_PCR_CCT0		MCHP_PCR_ERB(3, 30)
-#define MCHP_PCR_HTMR1		MCHP_PCR_ERB(3, 29)
-#define MCHP_PCR_AESHASH	MCHP_PCR_ERB(3, 28)
-#define MCHP_PCR_RNG		MCHP_PCR_ERB(3, 27)
-#define MCHP_PCR_PKE		MCHP_PCR_ERB(3, 26)
-#define MCHP_PCR_BTMR32_1	MCHP_PCR_ERB(3, 24)
-#define MCHP_PCR_BTMR32_0	MCHP_PCR_ERB(3, 23)
-#define MCHP_PCR_I2C4		MCHP_PCR_ERB(3, 20)
-#define MCHP_PCR_LED2		MCHP_PCR_ERB(3, 18)
-#define MCHP_PCR_LED1		MCHP_PCR_ERB(3, 17)
-#define MCHP_PCR_LED0		MCHP_PCR_ERB(3, 16)
-#define MCHP_PCR_I2C3		MCHP_PCR_ERB(3, 15)
-#define MCHP_PCR_I2C2		MCHP_PCR_ERB(3, 14)
-#define MCHP_PCR_I2C1		MCHP_PCR_ERB(3, 13)
-#define MCHP_PCR_KEYSCAN	MCHP_PCR_ERB(3, 11)
-#define MCHP_PCR_HTMR0		MCHP_PCR_ERB(3, 10)
-#define MCHP_PCR_PS2_1		MCHP_PCR_ERB(3, 6)
-#define MCHP_PCR_PS2_0		MCHP_PCR_ERB(3, 5)
-#define MCHP_PCR_ADC		MCHP_PCR_ERB(3, 3)
-#define MCHP_PCR_HDMI_CEC	MCHP_PCR_ERB(3, 1)
+#define MCHP_PCR_CCT0 MCHP_PCR_ERB(3, 30)
+#define MCHP_PCR_HTMR1 MCHP_PCR_ERB(3, 29)
+#define MCHP_PCR_AESHASH MCHP_PCR_ERB(3, 28)
+#define MCHP_PCR_RNG MCHP_PCR_ERB(3, 27)
+#define MCHP_PCR_PKE MCHP_PCR_ERB(3, 26)
+#define MCHP_PCR_BTMR32_1 MCHP_PCR_ERB(3, 24)
+#define MCHP_PCR_BTMR32_0 MCHP_PCR_ERB(3, 23)
+#define MCHP_PCR_I2C4 MCHP_PCR_ERB(3, 20)
+#define MCHP_PCR_LED2 MCHP_PCR_ERB(3, 18)
+#define MCHP_PCR_LED1 MCHP_PCR_ERB(3, 17)
+#define MCHP_PCR_LED0 MCHP_PCR_ERB(3, 16)
+#define MCHP_PCR_I2C3 MCHP_PCR_ERB(3, 15)
+#define MCHP_PCR_I2C2 MCHP_PCR_ERB(3, 14)
+#define MCHP_PCR_I2C1 MCHP_PCR_ERB(3, 13)
+#define MCHP_PCR_KEYSCAN MCHP_PCR_ERB(3, 11)
+#define MCHP_PCR_HTMR0 MCHP_PCR_ERB(3, 10)
+#define MCHP_PCR_PS2_1 MCHP_PCR_ERB(3, 6)
+#define MCHP_PCR_PS2_0 MCHP_PCR_ERB(3, 5)
+#define MCHP_PCR_ADC MCHP_PCR_ERB(3, 3)
+#define MCHP_PCR_HDMI_CEC MCHP_PCR_ERB(3, 1)
 
 /* Command blocks to sleep */
-#define MCHP_PCR_SLP_EN3_CCT0		BIT(30)
-#define MCHP_PCR_SLP_EN3_HTMR1		BIT(29)
-#define MCHP_PCR_SLP_EN3_AESHASH	BIT(28)
-#define MCHP_PCR_SLP_EN3_RNG		BIT(27)
-#define MCHP_PCR_SLP_EN3_PKE		BIT(26)
-#define MCHP_PCR_SLP_EN3_BTMR32_1	BIT(24)
-#define MCHP_PCR_SLP_EN3_BTMR32_0	BIT(23)
-#define MCHP_PCR_SLP_EN3_I2C4		BIT(20)
-#define MCHP_PCR_SLP_EN3_LED2		BIT(18)
-#define MCHP_PCR_SLP_EN3_LED1		BIT(17)
-#define MCHP_PCR_SLP_EN3_LED0		BIT(16)
-#define MCHP_PCR_SLP_EN3_I2C3		BIT(15)
-#define MCHP_PCR_SLP_EN3_I2C2		BIT(14)
-#define MCHP_PCR_SLP_EN3_I2C1		BIT(13)
-#define MCHP_PCR_SLP_EN3_KEYSCAN	BIT(11)
-#define MCHP_PCR_SLP_EN3_HTMR0		BIT(10)
-#define MCHP_PCR_SLP_EN3_PS2_1		BIT(6)
-#define MCHP_PCR_SLP_EN3_PS2_0		BIT(5)
-#define MCHP_PCR_SLP_EN3_ADC		BIT(3)
-#define MCHP_PCR_SLP_EN3_HDMI_CEC	BIT(1)
-#define MCHP_PCR_SLP_EN3_ALL_CRYPTO	(0x07 << 26)
+#define MCHP_PCR_SLP_EN3_CCT0 BIT(30)
+#define MCHP_PCR_SLP_EN3_HTMR1 BIT(29)
+#define MCHP_PCR_SLP_EN3_AESHASH BIT(28)
+#define MCHP_PCR_SLP_EN3_RNG BIT(27)
+#define MCHP_PCR_SLP_EN3_PKE BIT(26)
+#define MCHP_PCR_SLP_EN3_BTMR32_1 BIT(24)
+#define MCHP_PCR_SLP_EN3_BTMR32_0 BIT(23)
+#define MCHP_PCR_SLP_EN3_I2C4 BIT(20)
+#define MCHP_PCR_SLP_EN3_LED2 BIT(18)
+#define MCHP_PCR_SLP_EN3_LED1 BIT(17)
+#define MCHP_PCR_SLP_EN3_LED0 BIT(16)
+#define MCHP_PCR_SLP_EN3_I2C3 BIT(15)
+#define MCHP_PCR_SLP_EN3_I2C2 BIT(14)
+#define MCHP_PCR_SLP_EN3_I2C1 BIT(13)
+#define MCHP_PCR_SLP_EN3_KEYSCAN BIT(11)
+#define MCHP_PCR_SLP_EN3_HTMR0 BIT(10)
+#define MCHP_PCR_SLP_EN3_PS2_1 BIT(6)
+#define MCHP_PCR_SLP_EN3_PS2_0 BIT(5)
+#define MCHP_PCR_SLP_EN3_ADC BIT(3)
+#define MCHP_PCR_SLP_EN3_HDMI_CEC BIT(1)
+#define MCHP_PCR_SLP_EN3_ALL_CRYPTO (0x07 << 26)
 /* all sleep enable 3 bits */
-#define MCHP_PCR_SLP_EN3_SLEEP		0xfffffffd
-#define MCHP_PCR_SLP_EN3_PWM_ALL	0
+#define MCHP_PCR_SLP_EN3_SLEEP 0xfffffffd
+#define MCHP_PCR_SLP_EN3_PWM_ALL 0
 
 /* PCR Sleep 4: Sleep Enable, Clock Required, Reset */
-#define MCHP_PCR_SGPIO3		MCHP_PCR_ERB(4, 20)
-#define MCHP_PCR_SGPIO2		MCHP_PCR_ERB(4, 19)
-#define MCHP_PCR_SGPIO1		MCHP_PCR_ERB(4, 18)
-#define MCHP_PCR_SGPIO0		MCHP_PCR_ERB(4, 17)
-#define MCHP_PCR_SLV_SPI	MCHP_PCR_ERB(4, 16)
-#define MCHP_PCR_PSPI		MCHP_PCR_ERB(4, 14)
-#define MCHP_PCR_PROCHOT	MCHP_PCR_ERB(4, 13)
-#define MCHP_PCR_I2C7		MCHP_PCR_ERB(4, 12)
-#define MCHP_PCR_I2C6		MCHP_PCR_ERB(4, 11)
-#define MCHP_PCR_I2C5		MCHP_PCR_ERB(4, 10)
-#define MCHP_PCR_QMSPI		MCHP_PCR_ERB(4, 8)
-#define MCHP_PCR_RTMR		MCHP_PCR_ERB(4, 6)
+#define MCHP_PCR_SGPIO3 MCHP_PCR_ERB(4, 20)
+#define MCHP_PCR_SGPIO2 MCHP_PCR_ERB(4, 19)
+#define MCHP_PCR_SGPIO1 MCHP_PCR_ERB(4, 18)
+#define MCHP_PCR_SGPIO0 MCHP_PCR_ERB(4, 17)
+#define MCHP_PCR_SLV_SPI MCHP_PCR_ERB(4, 16)
+#define MCHP_PCR_PSPI MCHP_PCR_ERB(4, 14)
+#define MCHP_PCR_PROCHOT MCHP_PCR_ERB(4, 13)
+#define MCHP_PCR_I2C7 MCHP_PCR_ERB(4, 12)
+#define MCHP_PCR_I2C6 MCHP_PCR_ERB(4, 11)
+#define MCHP_PCR_I2C5 MCHP_PCR_ERB(4, 10)
+#define MCHP_PCR_QMSPI MCHP_PCR_ERB(4, 8)
+#define MCHP_PCR_RTMR MCHP_PCR_ERB(4, 6)
 
 /* Command blocks to sleep */
-#define MCHP_PCR_SLP_EN4_SGPIO3		BIT(20)
-#define MCHP_PCR_SLP_EN4_SGPIO2		BIT(19)
-#define MCHP_PCR_SLP_EN4_SGPIO1		BIT(18)
-#define MCHP_PCR_SLP_EN4_SGPIO0		BIT(17)
-#define MCHP_PCR_SLP_EN4_SLV_SPI	BIT(16)
-#define MCHP_PCR_SLP_EN4_PSPI		BIT(14)
-#define MCHP_PCR_SLP_EN4_PROCHOT	BIT(13)
-#define MCHP_PCR_SLP_EN4_I2C7		BIT(12)
-#define MCHP_PCR_SLP_EN4_I2C6		BIT(11)
-#define MCHP_PCR_SLP_EN4_I2C5		BIT(10)
-#define MCHP_PCR_SLP_EN4_QMSPI		BIT(8)
-#define MCHP_PCR_SLP_EN4_RTMR		BIT(6)
+#define MCHP_PCR_SLP_EN4_SGPIO3 BIT(20)
+#define MCHP_PCR_SLP_EN4_SGPIO2 BIT(19)
+#define MCHP_PCR_SLP_EN4_SGPIO1 BIT(18)
+#define MCHP_PCR_SLP_EN4_SGPIO0 BIT(17)
+#define MCHP_PCR_SLP_EN4_SLV_SPI BIT(16)
+#define MCHP_PCR_SLP_EN4_PSPI BIT(14)
+#define MCHP_PCR_SLP_EN4_PROCHOT BIT(13)
+#define MCHP_PCR_SLP_EN4_I2C7 BIT(12)
+#define MCHP_PCR_SLP_EN4_I2C6 BIT(11)
+#define MCHP_PCR_SLP_EN4_I2C5 BIT(10)
+#define MCHP_PCR_SLP_EN4_QMSPI BIT(8)
+#define MCHP_PCR_SLP_EN4_RTMR BIT(6)
 /* all sleep enable 4 bits */
-#define MCHP_PCR_SLP_EN4_SLEEP		0xffffffff
-#define MCHP_PCR_SLP_EN4_PWM_ALL	0
+#define MCHP_PCR_SLP_EN4_SLEEP 0xffffffff
+#define MCHP_PCR_SLP_EN4_PWM_ALL 0
 
 /* Allow all blocks to request clocks */
-#define MCHP_PCR_SLP_EN0_WAKE	(~(MCHP_PCR_SLP_EN0_SLEEP))
-#define MCHP_PCR_SLP_EN1_WAKE	(~(MCHP_PCR_SLP_EN1_SLEEP))
-#define MCHP_PCR_SLP_EN2_WAKE	(~(MCHP_PCR_SLP_EN2_SLEEP))
-#define MCHP_PCR_SLP_EN3_WAKE	(~(MCHP_PCR_SLP_EN3_SLEEP))
-#define MCHP_PCR_SLP_EN4_WAKE	(~(MCHP_PCR_SLP_EN4_SLEEP))
+#define MCHP_PCR_SLP_EN0_WAKE (~(MCHP_PCR_SLP_EN0_SLEEP))
+#define MCHP_PCR_SLP_EN1_WAKE (~(MCHP_PCR_SLP_EN1_SLEEP))
+#define MCHP_PCR_SLP_EN2_WAKE (~(MCHP_PCR_SLP_EN2_SLEEP))
+#define MCHP_PCR_SLP_EN3_WAKE (~(MCHP_PCR_SLP_EN3_SLEEP))
+#define MCHP_PCR_SLP_EN4_WAKE (~(MCHP_PCR_SLP_EN4_SLEEP))
 
 /* Bit defines for MCHP_PCR_PWR_RST_STS */
-#define MCHP_PWR_RST_STS_MASK_RO	0xc8c
-#define MCHP_PWR_RST_STS_MASK_RWC	0x170
+#define MCHP_PWR_RST_STS_MASK_RO 0xc8c
+#define MCHP_PWR_RST_STS_MASK_RWC 0x170
 #define MCHP_PWR_RST_STS_MASK \
 	((MCHP_PWR_RST_STS_MASK_RO) | (MCHP_PWR_RST_STS_MASK_RWC))
 
-#define MCHP_PWR_RST_STS_ESPI_CLK_ACT		BIT(11) /* RO */
-#define MCHP_PWR_RST_STS_32K_ACT		BIT(10) /* RO */
-#define MCHP_PWR_RST_STS_WDT			BIT(8) /* R/WC */
-#define MCHP_PWR_RST_STS_JTAG_RSTN		BIT(7) /* RO */
-#define MCHP_PWR_RST_STS_SYS			BIT(6) /* R/WC */
-#define MCHP_PWR_RST_STS_VBAT			BIT(5) /* R/WC */
-#define MCHP_PWR_RST_STS_VTR			BIT(4) /* R/WC */
-#define MCHP_PWR_RST_STS_HOST			BIT(3) /* RO */
-#define MCHP_PWR_RST_STS_VCC_PWRGD		BIT(2) /* RO */
+#define MCHP_PWR_RST_STS_ESPI_CLK_ACT BIT(11) /* RO */
+#define MCHP_PWR_RST_STS_32K_ACT BIT(10) /* RO */
+#define MCHP_PWR_RST_STS_WDT BIT(8) /* R/WC */
+#define MCHP_PWR_RST_STS_JTAG_RSTN BIT(7) /* RO */
+#define MCHP_PWR_RST_STS_SYS BIT(6) /* R/WC */
+#define MCHP_PWR_RST_STS_VBAT BIT(5) /* R/WC */
+#define MCHP_PWR_RST_STS_VTR BIT(4) /* R/WC */
+#define MCHP_PWR_RST_STS_HOST BIT(3) /* RO */
+#define MCHP_PWR_RST_STS_VCC_PWRGD BIT(2) /* RO */
 
 /* Bit defines for MCHP_PCR_PWR_RST_CTL */
-#define MCHP_PCR_PWR_HOST_RST_SEL_BITPOS	8
-#define MCHP_PCR_PWR_HOST_RST_PCI_RESET		BIT(8)
-#define MCHP_PCR_PWR_HOST_RST_ESPI_PLTRST	(0 << 8)
-#define MCHP_PCR_PWR_OK_INV_BITPOS		0
+#define MCHP_PCR_PWR_HOST_RST_SEL_BITPOS 8
+#define MCHP_PCR_PWR_HOST_RST_PCI_RESET BIT(8)
+#define MCHP_PCR_PWR_HOST_RST_ESPI_PLTRST (0 << 8)
+#define MCHP_PCR_PWR_OK_INV_BITPOS 0
 
 /* Bit defines for MCHP_PCR_SYS_RST */
-#define MCHP_PCR_SYS_SOFT_RESET			BIT(8)
+#define MCHP_PCR_SYS_SOFT_RESET BIT(8)
 
 /* EC Subsystem */
-#define MCHP_EC_AHB_ERR				REG32(MCHP_EC_BASE + 0x04)
-#define MCHP_EC_ID_RO				REG32(MCHP_EC_BASE + 0x10)
-#define MCHP_EC_AHB_ERR_EN			REG32(MCHP_EC_BASE + 0x14)
-#define MCHP_EC_INT_CTRL			REG32(MCHP_EC_BASE + 0x18)
-#define MCHP_EC_TRACE_EN			REG32(MCHP_EC_BASE + 0x1c)
-#define MCHP_EC_JTAG_EN				REG32(MCHP_EC_BASE + 0x20)
-#define MCHP_EC_WDT_CNT				REG32(MCHP_EC_BASE + 0x28)
-#define MCHP_EC_AES_SHA_SWAP_CTRL		REG8(MCHP_EC_BASE + 0x2c)
-#define MCHP_EC_VCI_FW_OVRD			REG8(MCHP_EC_BASE + 0x50)
-#define MCHP_EC_CRYPTO_SRESET			REG8(MCHP_EC_BASE + 0x5c)
-#define MCHP_EC_GPIO_BANK_PWR			REG8(MCHP_EC_BASE + 0x64)
-#define MCHP_EC_SLP_STS_MIRROR			REG8(MCHP_EC_BASE + 0x114)
+#define MCHP_EC_AHB_ERR REG32(MCHP_EC_BASE + 0x04)
+#define MCHP_EC_ID_RO REG32(MCHP_EC_BASE + 0x10)
+#define MCHP_EC_AHB_ERR_EN REG32(MCHP_EC_BASE + 0x14)
+#define MCHP_EC_INT_CTRL REG32(MCHP_EC_BASE + 0x18)
+#define MCHP_EC_TRACE_EN REG32(MCHP_EC_BASE + 0x1c)
+#define MCHP_EC_JTAG_EN REG32(MCHP_EC_BASE + 0x20)
+#define MCHP_EC_WDT_CNT REG32(MCHP_EC_BASE + 0x28)
+#define MCHP_EC_AES_SHA_SWAP_CTRL REG8(MCHP_EC_BASE + 0x2c)
+#define MCHP_EC_VCI_FW_OVRD REG8(MCHP_EC_BASE + 0x50)
+#define MCHP_EC_CRYPTO_SRESET REG8(MCHP_EC_BASE + 0x5c)
+#define MCHP_EC_GPIO_BANK_PWR REG8(MCHP_EC_BASE + 0x64)
+#define MCHP_EC_SLP_STS_MIRROR REG8(MCHP_EC_BASE + 0x114)
 
 /* AHB ERR Enable bit[0]=0(enable), 1(disable) */
-#define MCHP_EC_AHB_ERROR_ENABLE	0
-#define MCHP_EC_AHB_ERROR_DISABLE	1
+#define MCHP_EC_AHB_ERROR_ENABLE 0
+#define MCHP_EC_AHB_ERROR_DISABLE 1
 
 /* MCHP_EC_JTAG_EN bit definitions */
-#define MCHP_JTAG_ENABLE	0x01
+#define MCHP_JTAG_ENABLE 0x01
 /* bits [2:1] */
-#define MCHP_JTAG_MODE_4PIN	0x00
+#define MCHP_JTAG_MODE_4PIN 0x00
 /* ARM 2-pin SWD plus 1-pin Serial Wire Viewer (ITM) */
-#define MCHP_JTAG_MODE_SWD_SWV	0x02
+#define MCHP_JTAG_MODE_SWD_SWV 0x02
 /* ARM 2-pin SWD with no SWV */
-#define MCHP_JTAG_MODE_SWD	0x04
+#define MCHP_JTAG_MODE_SWD 0x04
 
 /* MCHP_EC_CRYPTO_SRESET bit definitions. Bits cleared by HW */
-#define MCHP_CRYPTO_NDRNG_SRST		0x01
-#define MCHP_CRYPTO_PKE_SRST		0x02
-#define MCHP_CRYPTO_AES_SHA_SRST	0x04
-#define MCHP_CRYPTO_ALL_SRST		0x07
+#define MCHP_CRYPTO_NDRNG_SRST 0x01
+#define MCHP_CRYPTO_PKE_SRST 0x02
+#define MCHP_CRYPTO_AES_SHA_SRST 0x04
+#define MCHP_CRYPTO_ALL_SRST 0x07
 
 /* MCHP_GPIO_BANK_PWR bit definitions */
-#define MCHP_EC_GPIO_BANK_PWR_MASK	0x86
-#define MCHP_EC_GPIO_BANK_PWR_VTR2_18	0x02
-#define MCHP_EC_GPIO_BANK_PWR_VTR3_18	0x04
-#define MCHP_EC_GPIO_BANK_PWR_LOCK	0x80
+#define MCHP_EC_GPIO_BANK_PWR_MASK 0x86
+#define MCHP_EC_GPIO_BANK_PWR_VTR2_18 0x02
+#define MCHP_EC_GPIO_BANK_PWR_VTR3_18 0x04
+#define MCHP_EC_GPIO_BANK_PWR_LOCK 0x80
 
 /* EC Interrupt aggregator (ECIA) */
-#define MCHP_INT_GIRQ_LEN		20 /* 5 32-bit registers */
-#define MCHP_INT_GIRQ_FIRST		8
-#define MCHP_INT_GIRQ_LAST		26
-#define MCHP_INT_GIRQ_NUM		(26-8+1)
+#define MCHP_INT_GIRQ_LEN 20 /* 5 32-bit registers */
+#define MCHP_INT_GIRQ_FIRST 8
+#define MCHP_INT_GIRQ_LAST 26
+#define MCHP_INT_GIRQ_NUM (26 - 8 + 1)
 /* MCHP_INT_GIRQ_FIRST <= x <= MCHP_INT_GIRQ_LAST */
-#define MCHP_INTx_BASE(x) (MCHP_INT_BASE + (((x) - 8) * MCHP_INT_GIRQ_LEN))
+#define MCHP_INTx_BASE(x) (MCHP_INT_BASE + (((x)-8) * MCHP_INT_GIRQ_LEN))
 
 /*
  * GPIO GIRQ's are not direct capable
@@ -554,8 +552,8 @@
  * GIRQ22 wake peripheral clock only
  * GIRQ24, GIRQ25 eSPI host to endpoint virtual wires
  */
-#define MCHP_INT_AGGR_ONLY_BITMAP	0x07401F00U
-#define MCHP_INT_DIRECT_CAPABLE_BITMAP	0x00BFE000U
+#define MCHP_INT_AGGR_ONLY_BITMAP 0x07401F00U
+#define MCHP_INT_DIRECT_CAPABLE_BITMAP 0x00BFE000U
 
 /* GIRQ13 I2C controllers. Direct capable */
 #define MCHP_INT13_I2C(x) (1ul << (x))
@@ -564,120 +562,120 @@
 #define MCHP_INT14_DMA(x) (1ul << (x))
 
 /* GIQ15 interrupt sources. Direct capable */
-#define MCHP_INT15_UART_0		BIT(0)
-#define MCHP_INT15_UART_1		BIT(1)
-#define MCHP_INT15_UART_2		BIT(4)
-#define MCHP_INT15_EMI_0		BIT(2)
-#define MCHP_INT15_EMI_1		BIT(3)
-#define MCHP_INT15_ACPI_EC0_IBF		BIT(5)
-#define MCHP_INT15_ACPI_EC0_OBE		BIT(6)
-#define MCHP_INT15_ACPI_EC1_IBF		BIT(7)
-#define MCHP_INT15_ACPI_EC1_OBE		BIT(8)
-#define MCHP_INT15_ACPI_EC2_IBF		BIT(9)
-#define MCHP_INT15_ACPI_EC2_OBE		BIT(10)
-#define MCHP_INT15_ACPI_EC3_IBF		BIT(11)
-#define MCHP_INT15_ACPI_EC3_OBE		BIT(12)
-#define MCHP_INT15_ACPI_PM1_CTL		BIT(15)
-#define MCHP_INT15_ACPI_PM1_EN		BIT(16)
-#define MCHP_INT15_ACPI_PM1_STS		BIT(17)
-#define MCHP_INT15_8042_OBE		BIT(18)
-#define MCHP_INT15_8042_IBF		BIT(19)
-#define MCHP_INT15_MAILBOX		BIT(20)
-#define MCHP_INT15_P80_0		BIT(22)
-#define MCHP_INT15_P80_1		BIT(23)
-#define MCHP_INT15_P80(x)		BIT(22 + ((x) & 0x01U))
+#define MCHP_INT15_UART_0 BIT(0)
+#define MCHP_INT15_UART_1 BIT(1)
+#define MCHP_INT15_UART_2 BIT(4)
+#define MCHP_INT15_EMI_0 BIT(2)
+#define MCHP_INT15_EMI_1 BIT(3)
+#define MCHP_INT15_ACPI_EC0_IBF BIT(5)
+#define MCHP_INT15_ACPI_EC0_OBE BIT(6)
+#define MCHP_INT15_ACPI_EC1_IBF BIT(7)
+#define MCHP_INT15_ACPI_EC1_OBE BIT(8)
+#define MCHP_INT15_ACPI_EC2_IBF BIT(9)
+#define MCHP_INT15_ACPI_EC2_OBE BIT(10)
+#define MCHP_INT15_ACPI_EC3_IBF BIT(11)
+#define MCHP_INT15_ACPI_EC3_OBE BIT(12)
+#define MCHP_INT15_ACPI_PM1_CTL BIT(15)
+#define MCHP_INT15_ACPI_PM1_EN BIT(16)
+#define MCHP_INT15_ACPI_PM1_STS BIT(17)
+#define MCHP_INT15_8042_OBE BIT(18)
+#define MCHP_INT15_8042_IBF BIT(19)
+#define MCHP_INT15_MAILBOX BIT(20)
+#define MCHP_INT15_P80_0 BIT(22)
+#define MCHP_INT15_P80_1 BIT(23)
+#define MCHP_INT15_P80(x) BIT(22 + ((x)&0x01U))
 
 /* GIRQ16 interrupt sources. Direct capable */
-#define MCHP_INT16_PKE_ERR		BIT(0)
-#define MCHP_INT16_PKE_DONE		BIT(1)
-#define MCHP_INT16_RNG_DONE		BIT(2)
-#define MCHP_INT16_AES_DONE		BIT(3)
-#define MCHP_INT16_HASH_DONE		BIT(4)
+#define MCHP_INT16_PKE_ERR BIT(0)
+#define MCHP_INT16_PKE_DONE BIT(1)
+#define MCHP_INT16_RNG_DONE BIT(2)
+#define MCHP_INT16_AES_DONE BIT(3)
+#define MCHP_INT16_HASH_DONE BIT(4)
 
 /* GIR17 interrupt sources. Direct capable */
-#define MCHP_INT17_PECI			BIT(0)
-#define MCHP_INT17_TACH_0		BIT(1)
-#define MCHP_INT17_TACH_1		BIT(2)
-#define MCHP_INT17_TACH_2		BIT(3)
-#define MCHP_INT17_TACH_3		BIT(4)
-#define MCHP_INT17_HDMI_CEC		BIT(5)
-#define MCHP_INT17_ADC_SINGLE		BIT(8)
-#define MCHP_INT17_ADC_REPEAT		BIT(9)
-#define MCHP_INT17_LED_WDT_0		BIT(13)
-#define MCHP_INT17_LED_WDT_1		BIT(14)
-#define MCHP_INT17_LED_WDT_2		BIT(15)
-#define MCHP_INT17_PROCHOT		BIT(17)
+#define MCHP_INT17_PECI BIT(0)
+#define MCHP_INT17_TACH_0 BIT(1)
+#define MCHP_INT17_TACH_1 BIT(2)
+#define MCHP_INT17_TACH_2 BIT(3)
+#define MCHP_INT17_TACH_3 BIT(4)
+#define MCHP_INT17_HDMI_CEC BIT(5)
+#define MCHP_INT17_ADC_SINGLE BIT(8)
+#define MCHP_INT17_ADC_REPEAT BIT(9)
+#define MCHP_INT17_LED_WDT_0 BIT(13)
+#define MCHP_INT17_LED_WDT_1 BIT(14)
+#define MCHP_INT17_LED_WDT_2 BIT(15)
+#define MCHP_INT17_PROCHOT BIT(17)
 
 /* GIRQ18 interrupt sources. Direct capable */
-#define MCHP_INT18_SLV_SPI		BIT(0)
-#define MCHP_INT18_QMSPI		BIT(1)
-#define MCHP_INT18_PS2_0		BIT(10)
-#define MCHP_INT18_PS2_1		BIT(11)
-#define MCHP_INT18_CCT			BIT(20)
-#define MCHP_INT18_CCT_CAP0		BIT(21)
-#define MCHP_INT18_CCT_CAP1		BIT(22)
-#define MCHP_INT18_CCT_CAP2		BIT(23)
-#define MCHP_INT18_CCT_CAP3		BIT(24)
-#define MCHP_INT18_CCT_CAP4		BIT(25)
-#define MCHP_INT18_CCT_CAP6		BIT(26)
-#define MCHP_INT18_CCT_CMP0		BIT(27)
-#define MCHP_INT18_CCT_CMP1		BIT(28)
+#define MCHP_INT18_SLV_SPI BIT(0)
+#define MCHP_INT18_QMSPI BIT(1)
+#define MCHP_INT18_PS2_0 BIT(10)
+#define MCHP_INT18_PS2_1 BIT(11)
+#define MCHP_INT18_CCT BIT(20)
+#define MCHP_INT18_CCT_CAP0 BIT(21)
+#define MCHP_INT18_CCT_CAP1 BIT(22)
+#define MCHP_INT18_CCT_CAP2 BIT(23)
+#define MCHP_INT18_CCT_CAP3 BIT(24)
+#define MCHP_INT18_CCT_CAP4 BIT(25)
+#define MCHP_INT18_CCT_CAP6 BIT(26)
+#define MCHP_INT18_CCT_CMP0 BIT(27)
+#define MCHP_INT18_CCT_CMP1 BIT(28)
 
 /* GIRQ19 interrupt sources. Direct capable */
-#define MCHP_INT19_ESPI_PC		BIT(0)
-#define MCHP_INT19_ESPI_BM1		BIT(1)
-#define MCHP_INT19_ESPI_BM2		BIT(2)
-#define MCHP_INT19_ESPI_LTR		BIT(3)
-#define MCHP_INT19_ESPI_OOB_TX		BIT(4)
-#define MCHP_INT19_ESPI_OOB_RX		BIT(5)
-#define MCHP_INT19_ESPI_FC		BIT(6)
-#define MCHP_INT19_ESPI_RESET		BIT(7)
-#define MCHP_INT19_ESPI_VW_EN		BIT(8)
-#define MCHP_INT19_ESPI_SAF		BIT(9)
-#define MCHP_INT19_ESPI_SAF_ERR		BIT(10)
+#define MCHP_INT19_ESPI_PC BIT(0)
+#define MCHP_INT19_ESPI_BM1 BIT(1)
+#define MCHP_INT19_ESPI_BM2 BIT(2)
+#define MCHP_INT19_ESPI_LTR BIT(3)
+#define MCHP_INT19_ESPI_OOB_TX BIT(4)
+#define MCHP_INT19_ESPI_OOB_RX BIT(5)
+#define MCHP_INT19_ESPI_FC BIT(6)
+#define MCHP_INT19_ESPI_RESET BIT(7)
+#define MCHP_INT19_ESPI_VW_EN BIT(8)
+#define MCHP_INT19_ESPI_SAF BIT(9)
+#define MCHP_INT19_ESPI_SAF_ERR BIT(10)
 
 /* GIRQ20 interrupt sources. Direct capable */
-#define MCHP_INT20_OPT			BIT(3)
+#define MCHP_INT20_OPT BIT(3)
 
 /* GIRQ21 interrupt sources. Direct capable */
-#define MCHP_INT21_WDT			BIT(2)
-#define MCHP_INT21_WEEK_ALARM		BIT(3)
-#define MCHP_INT21_WEEK_SUB		BIT(4)
-#define MCHP_INT21_WEEK_1SEC		BIT(5)
-#define MCHP_INT21_WEEK_1SEC_SUB	BIT(6)
-#define MCHP_INT21_WEEK_PWR_PRES	BIT(7)
-#define MCHP_INT21_RTC			BIT(8)
-#define MCHP_INT21_RTC_ALARM		BIT(9)
-#define MCHP_INT21_VCI_OVRD		BIT(10)
-#define MCHP_INT21_VCI_IN0		BIT(11)
-#define MCHP_INT21_VCI_IN1		BIT(12)
-#define MCHP_INT21_VCI_IN2		BIT(13)
-#define MCHP_INT21_VCI_IN3		BIT(14)
-#define MCHP_INT21_PS2_0A_WAKE		BIT(18)
-#define MCHP_INT21_PS2_0B_WAKE		BIT(19)
-#define MCHP_INT21_PS2_1B_WAKE		BIT(21)
-#define MCHP_INT21_KEYSCAN		BIT(25)
+#define MCHP_INT21_WDT BIT(2)
+#define MCHP_INT21_WEEK_ALARM BIT(3)
+#define MCHP_INT21_WEEK_SUB BIT(4)
+#define MCHP_INT21_WEEK_1SEC BIT(5)
+#define MCHP_INT21_WEEK_1SEC_SUB BIT(6)
+#define MCHP_INT21_WEEK_PWR_PRES BIT(7)
+#define MCHP_INT21_RTC BIT(8)
+#define MCHP_INT21_RTC_ALARM BIT(9)
+#define MCHP_INT21_VCI_OVRD BIT(10)
+#define MCHP_INT21_VCI_IN0 BIT(11)
+#define MCHP_INT21_VCI_IN1 BIT(12)
+#define MCHP_INT21_VCI_IN2 BIT(13)
+#define MCHP_INT21_VCI_IN3 BIT(14)
+#define MCHP_INT21_PS2_0A_WAKE BIT(18)
+#define MCHP_INT21_PS2_0B_WAKE BIT(19)
+#define MCHP_INT21_PS2_1B_WAKE BIT(21)
+#define MCHP_INT21_KEYSCAN BIT(25)
 
 /* GIRQ22 peripheral wake only. GIRQ22 not connected to NVIC */
-#define MCHP_INT22_WAKE_ONLY_SLV_SPI	BIT(0)
-#define MCHP_INT22_WAKE_ONLY_I2C0	BIT(1)
-#define MCHP_INT22_WAKE_ONLY_I2C1	BIT(2)
-#define MCHP_INT22_WAKE_ONLY_I2C2	BIT(3)
-#define MCHP_INT22_WAKE_ONLY_I2C3	BIT(4)
-#define MCHP_INT22_WAKE_ONLY_I2C4	BIT(5)
-#define MCHP_INT22_WAKE_ONLY_I2C5	BIT(6)
-#define MCHP_INT22_WAKE_ONLY_I2C6	BIT(7)
-#define MCHP_INT22_WAKE_ONLY_I2C7	BIT(8)
-#define MCHP_INT22_WAKE_ONLY_ESPI	BIT(9)
+#define MCHP_INT22_WAKE_ONLY_SLV_SPI BIT(0)
+#define MCHP_INT22_WAKE_ONLY_I2C0 BIT(1)
+#define MCHP_INT22_WAKE_ONLY_I2C1 BIT(2)
+#define MCHP_INT22_WAKE_ONLY_I2C2 BIT(3)
+#define MCHP_INT22_WAKE_ONLY_I2C3 BIT(4)
+#define MCHP_INT22_WAKE_ONLY_I2C4 BIT(5)
+#define MCHP_INT22_WAKE_ONLY_I2C5 BIT(6)
+#define MCHP_INT22_WAKE_ONLY_I2C6 BIT(7)
+#define MCHP_INT22_WAKE_ONLY_I2C7 BIT(8)
+#define MCHP_INT22_WAKE_ONLY_ESPI BIT(9)
 
 /* GIRQ23 sources. Direct capable */
-#define MCHP_INT23_BTMR16_0		BIT(0)
-#define MCHP_INT23_BTMR16_1		BIT(1)
-#define MCHP_INT23_BTMR32_0		BIT(4)
-#define MCHP_INT23_BTMR32_1		BIT(5)
-#define MCHP_INT23_RTMR			BIT(10)
-#define MCHP_INT23_HTMR_0		BIT(16)
-#define MCHP_INT23_HTMR_1		BIT(17)
+#define MCHP_INT23_BTMR16_0 BIT(0)
+#define MCHP_INT23_BTMR16_1 BIT(1)
+#define MCHP_INT23_BTMR32_0 BIT(4)
+#define MCHP_INT23_BTMR32_1 BIT(5)
+#define MCHP_INT23_RTMR BIT(10)
+#define MCHP_INT23_HTMR_0 BIT(16)
+#define MCHP_INT23_HTMR_1 BIT(17)
 
 /* GIRQ24 sources. Master-to-Slave v=[0:6], Source=[0:3] */
 #define MCHP_INT24_MSVW_SRC(v, s) (1ul << ((4 * (v)) + (s)))
@@ -686,20 +684,19 @@
 #define MCHP_INT25_MSVW_SRC(v, s) (1ul << ((4 * ((v)-7)) + (s)))
 
 /* UART Peripheral 0 <= x <= 2 */
-#define MCHP_UART_INSTANCES		3
-#define MCHP_UART_SPACING		0x400
-#define MCHP_UART_CFG_OFS		0x300
+#define MCHP_UART_INSTANCES 3
+#define MCHP_UART_SPACING 0x400
+#define MCHP_UART_CFG_OFS 0x300
 #define MCHP_UART_CONFIG_BASE(x) \
-	(MCHP_UART0_BASE + MCHP_UART_CFG_OFS + ((x) * MCHP_UART_SPACING))
-#define MCHP_UART_RUNTIME_BASE(x) \
-	(MCHP_UART0_BASE + ((x) * MCHP_UART_SPACING))
-#define MCHP_UART_GIRQ			15
-#define MCHP_UART0_GIRQ_BIT		(MCHP_INT15_UART_0)
-#define MCHP_UART1_GIRQ_BIT		(MCHP_INT15_UART_1)
-#define MCHP_UART2_GIRQ_BIT		(MCHP_INT15_UART_2)
-#define MCHP_UART_GIRQ_BIT(x)		BIT(x)
+	(MCHP_UART0_BASE + MCHP_UART_CFG_OFS + ((x)*MCHP_UART_SPACING))
+#define MCHP_UART_RUNTIME_BASE(x) (MCHP_UART0_BASE + ((x)*MCHP_UART_SPACING))
+#define MCHP_UART_GIRQ 15
+#define MCHP_UART0_GIRQ_BIT (MCHP_INT15_UART_0)
+#define MCHP_UART1_GIRQ_BIT (MCHP_INT15_UART_1)
+#define MCHP_UART2_GIRQ_BIT (MCHP_INT15_UART_2)
+#define MCHP_UART_GIRQ_BIT(x) BIT(x)
 /* BIT defines for MCHP_UARTx_LSR */
-#define MCHP_LSR_TX_EMPTY		BIT(5)
+#define MCHP_LSR_TX_EMPTY BIT(5)
 
 /*
  * GPIO
@@ -729,8 +726,8 @@
  * id        = 0x9d & 0x1f = 0x1d
  * Control 1 Address = 0x40081000 + (((4 << 5) + 0x1d) << 2) = 0x40081274
  */
-#define MCHP_GPIO_CTL(port, id) REG32(MCHP_GPIO_BASE + \
-	(((port << 5) + id) << 2))
+#define MCHP_GPIO_CTL(port, id) \
+	REG32(MCHP_GPIO_BASE + (((port << 5) + id) << 2))
 
 /* MCHP implements 6 GPIO ports */
 #define MCHP_GPIO_MAX_PORT 6
@@ -740,272 +737,257 @@
  * In MECxxxx documentation GPIO numbers are octal, each control
  * register is located on a 32-bit boundary.
  */
-#define MCHP_GPIO_CTRL(gpio_num) REG32(MCHP_GPIO_BASE + \
-	((gpio_num) << 2))
+#define MCHP_GPIO_CTRL(gpio_num) REG32(MCHP_GPIO_BASE + ((gpio_num) << 2))
 
 /*
  * GPIO control register bit fields
  */
-#define MCHP_GPIO_CTRL_PUD_BITPOS		0
-#define MCHP_GPIO_CTRL_PUD_MASK0		0x03
-#define MCHP_GPIO_CTRL_PUD_MASK			0x03
-#define MCHP_GPIO_CTRL_PUD_NONE			0x00
-#define MCHP_GPIO_CTRL_PUD_PU			0x01
-#define MCHP_GPIO_CTRL_PUD_PD			0x02
-#define MCHP_GPIO_CTRL_PUD_KEEPER		0x03
-#define MCHP_GPIO_CTRL_PWR_BITPOS		2
-#define MCHP_GPIO_CTRL_PWR_MASK0		0x03
-#define MCHP_GPIO_CTRL_PWR_MASK			(0x03 << 2)
-#define MCHP_GPIO_CTRL_PWR_VTR			(0x00 << 2)
-#define MCHP_GPIO_CTRL_PWR_OFF			(0x02 << 2)
-#define MCHP_GPIO_INTDET_MASK			0xF0
-#define MCHP_GPIO_INTDET_LVL_LO			0x00
-#define MCHP_GPIO_INTDET_LVL_HI			0x10
-#define MCHP_GPIO_INTDET_DISABLED		0x40
-#define MCHP_GPIO_INTDET_EDGE_RIS		0xD0
-#define MCHP_GPIO_INTDET_EDGE_FALL		0xE0
-#define MCHP_GPIO_INTDET_EDGE_BOTH		0xF0
-#define MCHP_GPIO_INTDET_EDGE_EN		BIT(7)
-#define MCHP_GPIO_PUSH_PULL			0u
-#define MCHP_GPIO_OPEN_DRAIN			BIT(8)
-#define MCHP_GPIO_INPUT				0u
-#define MCHP_GPIO_OUTPUT			BIT(9)
-#define MCHP_GPIO_OUTSET_CTRL			0u
-#define MCHP_GPIO_OUTSEL_PAR			BIT(10)
-#define MCHP_GPIO_POLARITY_NINV			0u
-#define MCHP_GPIO_POLARITY_INV			BIT(11)
-#define MCHP_GPIO_CTRL_ALT_FUNC_BITPOS		12
-#define MCHP_GPIO_CTRL_ALT_FUNC_MASK0		0x0F
-#define MCHP_GPIO_CTRL_ALT_FUNC_MASK		(0x0F << 12)
-#define MCHP_GPIO_CTRL_FUNC_GPIO		(0 << 12)
-#define MCHP_GPIO_CTRL_FUNC_1			(1 << 12)
-#define MCHP_GPIO_CTRL_FUNC_2			(2 << 12)
-#define MCHP_GPIO_CTRL_FUNC_3			(3 << 12)
-#define MCHP_GPIO_CTRL_OUT_LVL			BIT(16)
+#define MCHP_GPIO_CTRL_PUD_BITPOS 0
+#define MCHP_GPIO_CTRL_PUD_MASK0 0x03
+#define MCHP_GPIO_CTRL_PUD_MASK 0x03
+#define MCHP_GPIO_CTRL_PUD_NONE 0x00
+#define MCHP_GPIO_CTRL_PUD_PU 0x01
+#define MCHP_GPIO_CTRL_PUD_PD 0x02
+#define MCHP_GPIO_CTRL_PUD_KEEPER 0x03
+#define MCHP_GPIO_CTRL_PWR_BITPOS 2
+#define MCHP_GPIO_CTRL_PWR_MASK0 0x03
+#define MCHP_GPIO_CTRL_PWR_MASK (0x03 << 2)
+#define MCHP_GPIO_CTRL_PWR_VTR (0x00 << 2)
+#define MCHP_GPIO_CTRL_PWR_OFF (0x02 << 2)
+#define MCHP_GPIO_INTDET_MASK 0xF0
+#define MCHP_GPIO_INTDET_LVL_LO 0x00
+#define MCHP_GPIO_INTDET_LVL_HI 0x10
+#define MCHP_GPIO_INTDET_DISABLED 0x40
+#define MCHP_GPIO_INTDET_EDGE_RIS 0xD0
+#define MCHP_GPIO_INTDET_EDGE_FALL 0xE0
+#define MCHP_GPIO_INTDET_EDGE_BOTH 0xF0
+#define MCHP_GPIO_INTDET_EDGE_EN BIT(7)
+#define MCHP_GPIO_PUSH_PULL 0u
+#define MCHP_GPIO_OPEN_DRAIN BIT(8)
+#define MCHP_GPIO_INPUT 0u
+#define MCHP_GPIO_OUTPUT BIT(9)
+#define MCHP_GPIO_OUTSET_CTRL 0u
+#define MCHP_GPIO_OUTSEL_PAR BIT(10)
+#define MCHP_GPIO_POLARITY_NINV 0u
+#define MCHP_GPIO_POLARITY_INV BIT(11)
+#define MCHP_GPIO_CTRL_ALT_FUNC_BITPOS 12
+#define MCHP_GPIO_CTRL_ALT_FUNC_MASK0 0x0F
+#define MCHP_GPIO_CTRL_ALT_FUNC_MASK (0x0F << 12)
+#define MCHP_GPIO_CTRL_FUNC_GPIO (0 << 12)
+#define MCHP_GPIO_CTRL_FUNC_1 (1 << 12)
+#define MCHP_GPIO_CTRL_FUNC_2 (2 << 12)
+#define MCHP_GPIO_CTRL_FUNC_3 (3 << 12)
+#define MCHP_GPIO_CTRL_OUT_LVL BIT(16)
 /* MEC15xx only */
-#define MCHP_GPIO_CTRL_DIS_INPUT_BITPOS		15
-#define MCHP_GPIO_CTRL_DIS_INPUT_BIT		BIT(15)
+#define MCHP_GPIO_CTRL_DIS_INPUT_BITPOS 15
+#define MCHP_GPIO_CTRL_DIS_INPUT_BIT BIT(15)
 
 /*
  * GPIO Parallel Input and Output registers.
  * gpio_bank in [0, 5]
  */
-#define MCHP_GPIO_PARIN(bank) \
-	REG32(MCHP_GPIO_BASE + 0x0300 + ((bank) << 2))
-#define MCHP_GPIO_PAROUT(bank) \
-	REG32(MCHP_GPIO_BASE + 0x0380 + ((bank) << 2))
+#define MCHP_GPIO_PARIN(bank) REG32(MCHP_GPIO_BASE + 0x0300 + ((bank) << 2))
+#define MCHP_GPIO_PAROUT(bank) REG32(MCHP_GPIO_BASE + 0x0380 + ((bank) << 2))
 
 /* Basic timers */
-#define MCHP_TMR_SPACING		0x20
-#define MCHP_TMR16_INSTANCES		2
-#define MCHP_TMR32_INSTANCES		2
-#define MCHP_TMR16_MAX			(MCHP_TMR16_INSTANCES)
-#define MCHP_TMR32_MAX			(MCHP_TMR32_INSTANCES)
-#define MCHP_TMR16_BASE(n)	\
-	(MCHP_TMR16_0_BASE + (n) * MCHP_TMR_SPACING)
-#define MCHP_TMR32_BASE(n)	\
-	(MCHP_TMR32_0_BASE + (n) * MCHP_TMR_SPACING)
-#define MCHP_TMR16_GIRQ			23
-#define MCHP_TMR16_GIRQ_BIT(n)		BIT(0 + (n))
-#define MCHP_TMR32_GIRQ			23
-#define MCHP_TMR32_GIRQ_BIT(n)		BIT(4 + (n))
+#define MCHP_TMR_SPACING 0x20
+#define MCHP_TMR16_INSTANCES 2
+#define MCHP_TMR32_INSTANCES 2
+#define MCHP_TMR16_MAX (MCHP_TMR16_INSTANCES)
+#define MCHP_TMR32_MAX (MCHP_TMR32_INSTANCES)
+#define MCHP_TMR16_BASE(n) (MCHP_TMR16_0_BASE + (n)*MCHP_TMR_SPACING)
+#define MCHP_TMR32_BASE(n) (MCHP_TMR32_0_BASE + (n)*MCHP_TMR_SPACING)
+#define MCHP_TMR16_GIRQ 23
+#define MCHP_TMR16_GIRQ_BIT(n) BIT(0 + (n))
+#define MCHP_TMR32_GIRQ 23
+#define MCHP_TMR32_GIRQ_BIT(n) BIT(4 + (n))
 
 /* RTimer */
-#define MCHP_RTMR_GIRQ			23
-#define MCHP_RTMR_GIRQ_BIT(x)		BIT(10)
+#define MCHP_RTMR_GIRQ 23
+#define MCHP_RTMR_GIRQ_BIT(x) BIT(10)
 
 /* Watchdog */
 /* MEC152x specific registers */
-#define MCHP_WDG_STATUS			REG32(MCHP_WDG_BASE + 0x10)
-#define MCHP_WDG_IEN			REG32(MCHP_WDG_BASE + 0x14)
+#define MCHP_WDG_STATUS REG32(MCHP_WDG_BASE + 0x10)
+#define MCHP_WDG_IEN REG32(MCHP_WDG_BASE + 0x14)
 /* Status */
-#define MCHP_WDG_STS_IRQ		BIT(0)
+#define MCHP_WDG_STS_IRQ BIT(0)
 /* Interrupt enable */
-#define MCHP_WDG_IEN_IRQ_EN		BIT(0)
-#define MCHP_WDG_GIRQ			21
-#define MCHP_WDG_GIRQ_BIT		BIT(2)
+#define MCHP_WDG_IEN_IRQ_EN BIT(0)
+#define MCHP_WDG_GIRQ 21
+#define MCHP_WDG_GIRQ_BIT BIT(2)
 /* Control register has a bit to enable IRQ generation */
-#define MCHP_WDG_RESET_IRQ_EN		BIT(9)
+#define MCHP_WDG_RESET_IRQ_EN BIT(9)
 
 /* VBAT */
-#define MCHP_VBAT_STS			REG32(MCHP_VBAT_BASE + 0x0)
-#define MCHP_VBAT_CE			REG32(MCHP_VBAT_BASE + 0x8)
-#define MCHP_VBAT_SHDN_DIS		REG32(MCHP_VBAT_BASE + 0xC)
-#define MCHP_VBAT_MONOTONIC_CTR_LO	REG32(MCHP_VBAT_BASE + 0x20)
-#define MCHP_VBAT_MONOTONIC_CTR_HI	REG32(MCHP_VBAT_BASE + 0x24)
+#define MCHP_VBAT_STS REG32(MCHP_VBAT_BASE + 0x0)
+#define MCHP_VBAT_CE REG32(MCHP_VBAT_BASE + 0x8)
+#define MCHP_VBAT_SHDN_DIS REG32(MCHP_VBAT_BASE + 0xC)
+#define MCHP_VBAT_MONOTONIC_CTR_LO REG32(MCHP_VBAT_BASE + 0x20)
+#define MCHP_VBAT_MONOTONIC_CTR_HI REG32(MCHP_VBAT_BASE + 0x24)
 /* read 32-bit word at 32-bit offset x where 0 <= x <= 16 */
-#define MCHP_VBAT_RAM_SIZE		64
-#define MCHP_VBAT_RAM(wnum)		REG32(MCHP_VBAT_RAM_BASE + ((wnum) * 4))
-#define MCHP_VBAT_RAM8(bnum)		REG8(MCHP_VBAT_RAM_BASE + (bnum))
-#define MCHP_VBAT_VWIRE_BACKUP		14
+#define MCHP_VBAT_RAM_SIZE 64
+#define MCHP_VBAT_RAM(wnum) REG32(MCHP_VBAT_RAM_BASE + ((wnum)*4))
+#define MCHP_VBAT_RAM8(bnum) REG8(MCHP_VBAT_RAM_BASE + (bnum))
+#define MCHP_VBAT_VWIRE_BACKUP 14
 /*
  * Miscellaneous firmware control fields
  * scratch pad index cannot be more than 32 as
  * MEC152x has 64 bytes = 16 words of scratch pad RAM
  */
-#define MCHP_IMAGETYPE_IDX	15
+#define MCHP_IMAGETYPE_IDX 15
 
 /* Bit definition for MCHP_VBAT_STS */
-#define MCHP_VBAT_STS_SOFTRESET		BIT(2)
-#define MCHP_VBAT_STS_RESETI		BIT(4)
-#define MCHP_VBAT_STS_WDT		BIT(5)
-#define MCHP_VBAT_STS_SYSRESETREQ	BIT(6)
-#define MCHP_VBAT_STS_VBAT_RST		BIT(7)
-#define MCHP_VBAT_STS_ANY_RST		0xF4u
+#define MCHP_VBAT_STS_SOFTRESET BIT(2)
+#define MCHP_VBAT_STS_RESETI BIT(4)
+#define MCHP_VBAT_STS_WDT BIT(5)
+#define MCHP_VBAT_STS_SYSRESETREQ BIT(6)
+#define MCHP_VBAT_STS_VBAT_RST BIT(7)
+#define MCHP_VBAT_STS_ANY_RST 0xF4u
 
 /* Bit definitions for MCHP_VBAT_CE */
-#define MCHP_VBAT_CE_XOSEL_BITPOS	3
-#define MCHP_VBAT_CE_XOSEL_MASK		BIT(3)
-#define MCHP_VBAT_CE_XOSEL_PAR		0
-#define MCHP_VBAT_CE_XOSEL_SE		BIT(3)
+#define MCHP_VBAT_CE_XOSEL_BITPOS 3
+#define MCHP_VBAT_CE_XOSEL_MASK BIT(3)
+#define MCHP_VBAT_CE_XOSEL_PAR 0
+#define MCHP_VBAT_CE_XOSEL_SE BIT(3)
 
-#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_BITPOS		2
-#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_MASK		BIT(2)
-#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_INT		0
-#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_CRYSTAL		BIT(2)
+#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_BITPOS 2
+#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_MASK BIT(2)
+#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_INT 0
+#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_CRYSTAL BIT(2)
 
-#define MCHP_VBAT_CE_32K_DOMAIN_SRC_BITPOS		1
-#define MCHP_VBAT_CE_32K_DOMAIN_SRC_MASK		BIT(1)
-#define MCHP_VBAT_CE_32K_DOMAIN_ALWAYS_ON		0
-#define MCHP_VBAT_CE_32K_DOMAIN_32KHZ_IN_PIN		BIT(1)
+#define MCHP_VBAT_CE_32K_DOMAIN_SRC_BITPOS 1
+#define MCHP_VBAT_CE_32K_DOMAIN_SRC_MASK BIT(1)
+#define MCHP_VBAT_CE_32K_DOMAIN_ALWAYS_ON 0
+#define MCHP_VBAT_CE_32K_DOMAIN_32KHZ_IN_PIN BIT(1)
 
 /* Blinking-Breathing LED 0 <= n <= 2 */
-#define MCHP_BBLEB_INSTANCES	3
-#define MCHP_BBLED_BASE(n)	(MCHP_BBLED_0_BASE + (((n) & 0x03) * 256))
+#define MCHP_BBLEB_INSTANCES 3
+#define MCHP_BBLED_BASE(n) (MCHP_BBLED_0_BASE + (((n)&0x03) * 256))
 
 /* EMI */
-#define MCHP_EMI_INSTANCES	2
-#define MCHP_EMI_SPACING	0x400
-#define MCHP_EMI_ECREG_OFS	0x100
+#define MCHP_EMI_INSTANCES 2
+#define MCHP_EMI_SPACING 0x400
+#define MCHP_EMI_ECREG_OFS 0x100
 /* base of EMI registers only accessible by EC */
 #define MCHP_EMI_BASE(n) \
-	(MCHP_EMI_0_BASE + MCHP_EMI_ECREG_OFS + ((n) * MCHP_EMI_SPACING))
+	(MCHP_EMI_0_BASE + MCHP_EMI_ECREG_OFS + ((n)*MCHP_EMI_SPACING))
 /* base of EMI registers accessible by EC and Host */
-#define MCHP_EMI_RT_BASE(n)	(MCHP_EMI_0_BASE + ((n) * MCHP_EMI_SPACING))
-#define MCHP_EMI_GIRQ		15
-#define MCHP_EMI_GIRQ_BIT(n)	BIT(2 + (n))
+#define MCHP_EMI_RT_BASE(n) (MCHP_EMI_0_BASE + ((n)*MCHP_EMI_SPACING))
+#define MCHP_EMI_GIRQ 15
+#define MCHP_EMI_GIRQ_BIT(n) BIT(2 + (n))
 
 /* Mailbox */
-#define MCHP_MBX_ECREGS_OFS	0x100
-#define MCHP_MBX_RT_BASE	MCHP_MBOX_BASE
-#define MCHP_MBX_BASE		(MCHP_MBOX_BASE + MCHP_MBX_ECREGS_OFS)
-#define MCHP_MBX_GIRQ		15
-#define MCHP_MBX_GIRQ_BIT	BIT(20)
+#define MCHP_MBX_ECREGS_OFS 0x100
+#define MCHP_MBX_RT_BASE MCHP_MBOX_BASE
+#define MCHP_MBX_BASE (MCHP_MBOX_BASE + MCHP_MBX_ECREGS_OFS)
+#define MCHP_MBX_GIRQ 15
+#define MCHP_MBX_GIRQ_BIT BIT(20)
 
 /* Port 80 Capture */
-#define MCHP_P80_SPACING	0x400
-#define MCHP_P80_BASE(n)	\
-	(MCHP_P80CAP0_BASE + ((n) * (MCHP_P80_SPACING)))
-#define MCHP_P80_HOST_DATA(n)	REG8(MCHP_P80_BASE(n))
+#define MCHP_P80_SPACING 0x400
+#define MCHP_P80_BASE(n) (MCHP_P80CAP0_BASE + ((n) * (MCHP_P80_SPACING)))
+#define MCHP_P80_HOST_DATA(n) REG8(MCHP_P80_BASE(n))
 /* Data capture with time stamp register */
-#define MCHP_P80_CAP(n)		REG32(MCHP_P80_BASE(n) + 0x100)
-#define MCHP_P80_CFG(n)		REG8(MCHP_P80_BASE(n) + 0x104)
-#define MCHP_P80_STS(n)		REG8(MCHP_P80_BASE(n) + 0x108)
-#define MCHP_P80_CNT(n)		REG32(MCHP_P80_BASE(n) + 0x10c)
-#define MCHP_P80_CNT_GET(n)	(REG32(MCHP_P80_BASE(n) + 0x10c) >> 8)
-#define MCHP_P80_CNT_SET(n, c)	\
-	(REG32(MCHP_P80_BASE(n) + 0x10c) = ((c) << 8))
-#define MCHP_P80_ACTIVATE(n)	REG8(MCHP_P80_BASE(n) + 0x330)
-#define MCHP_P80_GIRQ		15
-#define MCHP_P80_GIRQ_BIT(n)	BIT(22 + (n))
+#define MCHP_P80_CAP(n) REG32(MCHP_P80_BASE(n) + 0x100)
+#define MCHP_P80_CFG(n) REG8(MCHP_P80_BASE(n) + 0x104)
+#define MCHP_P80_STS(n) REG8(MCHP_P80_BASE(n) + 0x108)
+#define MCHP_P80_CNT(n) REG32(MCHP_P80_BASE(n) + 0x10c)
+#define MCHP_P80_CNT_GET(n) (REG32(MCHP_P80_BASE(n) + 0x10c) >> 8)
+#define MCHP_P80_CNT_SET(n, c) (REG32(MCHP_P80_BASE(n) + 0x10c) = ((c) << 8))
+#define MCHP_P80_ACTIVATE(n) REG8(MCHP_P80_BASE(n) + 0x330)
+#define MCHP_P80_GIRQ 15
+#define MCHP_P80_GIRQ_BIT(n) BIT(22 + (n))
 /*
  * Port 80 Data register bits
  * bits[7:0] = data captured on Host write
  * bits[31:8] = optional time stamp
  */
-#define MCHP_P80_CAP_DATA_MASK		0xFFul
-#define MCHP_P80_CAP_TS_BITPOS		8
-#define MCHP_P80_CAP_TS_MASK0		0xfffffful
-#define MCHP_P80_CAP_TS_MASK		\
+#define MCHP_P80_CAP_DATA_MASK 0xFFul
+#define MCHP_P80_CAP_TS_BITPOS 8
+#define MCHP_P80_CAP_TS_MASK0 0xfffffful
+#define MCHP_P80_CAP_TS_MASK \
 	((MCHP_P80_CAP_TS_MASK0) << (MCHP_P80_CAP_TS_BITPOS))
 
 /* Port 80 Configuration register bits */
-#define MCHP_P80_FLUSH_FIFO_WO		BIT(1)
-#define MCHP_P80_RESET_TIMESTAMP_WO	BIT(2)
-#define MCHP_P80_TIMEBASE_BITPOS	3
-#define MCHP_P80_TIMEBASE_MASK0		0x03
-#define MCHP_P80_TIMEBASE_MASK		\
+#define MCHP_P80_FLUSH_FIFO_WO BIT(1)
+#define MCHP_P80_RESET_TIMESTAMP_WO BIT(2)
+#define MCHP_P80_TIMEBASE_BITPOS 3
+#define MCHP_P80_TIMEBASE_MASK0 0x03
+#define MCHP_P80_TIMEBASE_MASK \
 	((MCHP_P80_TIMEBASE_MASK0) << (MCHP_P80_TIMEBASE_BITPOS))
-#define MCHP_P80_TIMEBASE_750KHZ	\
-	(0x03 << (MCHP_P80_TIMEBASE_BITPOS))
-#define MCHP_P80_TIMEBASE_1500KHZ	\
-	(0x02 << (MCHP_P80_TIMEBASE_BITPOS))
-#define MCHP_P80_TIMEBASE_3MHZ		\
-	(0x01 << (MCHP_P80_TIMEBASE_BITPOS))
-#define MCHP_P80_TIMEBASE_6MHZ		\
-	(0x00 << (MCHP_P80_TIMEBASE_BITPOS))
-#define MCHP_P80_TIMER_ENABLE		BIT(5)
-#define MCHP_P80_FIFO_THRHOLD_MASK	(3u << 6)
-#define MCHP_P80_FIFO_THRHOLD_1		0u
-#define MCHP_P80_FIFO_THRHOLD_4		(1u << 6)
-#define MCHP_P80_FIFO_THRHOLD_8		(2u << 6)
-#define MCHP_P80_FIFO_THRHOLD_14	(3u << 6)
-#define MCHP_P80_FIFO_LEN		16
+#define MCHP_P80_TIMEBASE_750KHZ (0x03 << (MCHP_P80_TIMEBASE_BITPOS))
+#define MCHP_P80_TIMEBASE_1500KHZ (0x02 << (MCHP_P80_TIMEBASE_BITPOS))
+#define MCHP_P80_TIMEBASE_3MHZ (0x01 << (MCHP_P80_TIMEBASE_BITPOS))
+#define MCHP_P80_TIMEBASE_6MHZ (0x00 << (MCHP_P80_TIMEBASE_BITPOS))
+#define MCHP_P80_TIMER_ENABLE BIT(5)
+#define MCHP_P80_FIFO_THRHOLD_MASK (3u << 6)
+#define MCHP_P80_FIFO_THRHOLD_1 0u
+#define MCHP_P80_FIFO_THRHOLD_4 (1u << 6)
+#define MCHP_P80_FIFO_THRHOLD_8 (2u << 6)
+#define MCHP_P80_FIFO_THRHOLD_14 (3u << 6)
+#define MCHP_P80_FIFO_LEN 16
 /* Port 80 Status register bits, read-only */
-#define MCHP_P80_STS_NOT_EMPTY		BIT(0)
-#define MCHP_P80_STS_OVERRUN		BIT(1)
+#define MCHP_P80_STS_NOT_EMPTY BIT(0)
+#define MCHP_P80_STS_OVERRUN BIT(1)
 /* Port 80 Count register bits */
-#define MCHP_P80_CNT_BITPOS		8
-#define MCHP_P80_CNT_MASK0		0xfffffful
-#define MCHP_P80_CNT_MASK	\
-	((MCHP_P80_CNT_MASK0) << (MCHP_P80_CNT_BITPOS))
+#define MCHP_P80_CNT_BITPOS 8
+#define MCHP_P80_CNT_MASK0 0xfffffful
+#define MCHP_P80_CNT_MASK ((MCHP_P80_CNT_MASK0) << (MCHP_P80_CNT_BITPOS))
 
 /* PWM */
-#define MCHP_PWM_INSTANCES	9
-#define MCHP_PWM_ID_MAX		(MCHP_PWM_INSTANCES)
-#define MCHP_PWM_SPACING	16
-#define MCHP_PWM_BASE(x)	(MCHP_PWM_0_BASE + ((x) * MCHP_PWM_SPACING))
+#define MCHP_PWM_INSTANCES 9
+#define MCHP_PWM_ID_MAX (MCHP_PWM_INSTANCES)
+#define MCHP_PWM_SPACING 16
+#define MCHP_PWM_BASE(x) (MCHP_PWM_0_BASE + ((x)*MCHP_PWM_SPACING))
 
 /* TACH */
-#define MCHP_TACH_INSTANCES	4
-#define MCHP_TACH_SPACING	16
-#define MCHP_TACH_BASE(x)	\
-	(MCHP_TACH_0_BASE + ((x) * MCHP_TACH_SPACING))
-#define MCHP_TACH_GIRQ		17
-#define MCHP_TACH_GIRQ_BIT(x)	BIT(1 + (x))
+#define MCHP_TACH_INSTANCES 4
+#define MCHP_TACH_SPACING 16
+#define MCHP_TACH_BASE(x) (MCHP_TACH_0_BASE + ((x)*MCHP_TACH_SPACING))
+#define MCHP_TACH_GIRQ 17
+#define MCHP_TACH_GIRQ_BIT(x) BIT(1 + (x))
 
 /* ACPI EC */
-#define MCHP_ACPI_EC_INSTANCES	4
-#define MCHP_ACPI_EC_MAX	(ACPI_EC_INSTANCES)
-#define MCHP_ACPI_EC_SPACING	0x400
-#define MCHP_ACPI_EC_BASE(x) \
-	(MCHP_ACPI_EC_0_BASE + ((x) * MCHP_ACPI_EC_SPACING))
-#define MCHP_ACPI_EC_GIRQ		15
-#define MCHP_ACPI_EC_IBF_GIRQ_BIT(x)	BIT(5 + ((x) * 2))
-#define MCHP_ACPI_EC_OBE_GIRQ_BIT(x)	BIT(6 + ((x) * 2))
+#define MCHP_ACPI_EC_INSTANCES 4
+#define MCHP_ACPI_EC_MAX (ACPI_EC_INSTANCES)
+#define MCHP_ACPI_EC_SPACING 0x400
+#define MCHP_ACPI_EC_BASE(x) (MCHP_ACPI_EC_0_BASE + ((x)*MCHP_ACPI_EC_SPACING))
+#define MCHP_ACPI_EC_GIRQ 15
+#define MCHP_ACPI_EC_IBF_GIRQ_BIT(x) BIT(5 + ((x)*2))
+#define MCHP_ACPI_EC_OBE_GIRQ_BIT(x) BIT(6 + ((x)*2))
 
 /* ACPI PM1 */
-#define MCHP_ACPI_PM1_ECREGS_OFS	0x100
-#define MCHP_ACPI_PM_RT_BASE		MCHP_ACPI_PM1_BASE
-#define MCHP_ACPI_PM_EC_BASE		\
-	(MCHP_ACPI_PM1_BASE + MCHP_ACPI_PM1_ECREGS_OFS)
-#define MCHP_ACPI_PM1_CTL_GIRQ_BIT	BIT(15)
-#define MCHP_ACPI_PM1_EN_GIRQ_BIT	BIT(16)
-#define MCHP_ACPI_PM1_STS_GIRQ_BIT	BIT(17)
+#define MCHP_ACPI_PM1_ECREGS_OFS 0x100
+#define MCHP_ACPI_PM_RT_BASE MCHP_ACPI_PM1_BASE
+#define MCHP_ACPI_PM_EC_BASE (MCHP_ACPI_PM1_BASE + MCHP_ACPI_PM1_ECREGS_OFS)
+#define MCHP_ACPI_PM1_CTL_GIRQ_BIT BIT(15)
+#define MCHP_ACPI_PM1_EN_GIRQ_BIT BIT(16)
+#define MCHP_ACPI_PM1_STS_GIRQ_BIT BIT(17)
 
 /* 8042 */
-#define MCHP_8042_ECREGS_OFS		0x100
-#define MCHP_8042_GIRQ			15
-#define MCHP_8042_OBE_GIRQ_BIT		BIT(18)
-#define MCHP_8042_IBF_GIRQ_BIT		BIT(19)
+#define MCHP_8042_ECREGS_OFS 0x100
+#define MCHP_8042_GIRQ 15
+#define MCHP_8042_OBE_GIRQ_BIT BIT(18)
+#define MCHP_8042_IBF_GIRQ_BIT BIT(19)
 
 /*
  * I2C controllers 0 - 4 include SMBus network layer functionality.
  * I2C controllers 5 - 7 are I2C only and include slave mode
  * promiscuous functionality.
  */
-#define MCHP_I2C_CTRL0		0
-#define MCHP_I2C_CTRL1		1
-#define MCHP_I2C_CTRL2		2
-#define MCHP_I2C_CTRL3		3
-#define MCHP_I2C_CTRL4		4
-#define MCHP_I2C_CTRL5		5
-#define MCHP_I2C_CTRL6		6
-#define MCHP_I2C_CTRL7		7
-#define MCHP_I2C_CTRL_MAX	8
-
-#define MCHP_I2C_SEP0		0x400
-#define MCHP_I2C_SEP1		0x100
+#define MCHP_I2C_CTRL0 0
+#define MCHP_I2C_CTRL1 1
+#define MCHP_I2C_CTRL2 2
+#define MCHP_I2C_CTRL3 3
+#define MCHP_I2C_CTRL4 4
+#define MCHP_I2C_CTRL5 5
+#define MCHP_I2C_CTRL6 6
+#define MCHP_I2C_CTRL7 7
+#define MCHP_I2C_CTRL_MAX 8
+
+#define MCHP_I2C_SEP0 0x400
+#define MCHP_I2C_SEP1 0x100
 
 /*
  * MEC152xH 144-pin package has eight I2C controllers and sixteen ports.
@@ -1038,10 +1020,10 @@
  * I2C15_SCL/SDA on GPIO0150 F1, GPIO0147 F1
  */
 
-#define MCHP_MEC1521SZ_I2C_PORT_MASK	0xFEFFul
-#define MCHP_MEC1523SZ_I2C_PORT_MASK	0xFFFFul
+#define MCHP_MEC1521SZ_I2C_PORT_MASK 0xFEFFul
+#define MCHP_MEC1523SZ_I2C_PORT_MASK 0xFFFFul
 
-#define MCHP_I2C_PORT_MASK	MCHP_MEC1521SZ_I2C_PORT_MASK
+#define MCHP_I2C_PORT_MASK MCHP_MEC1521SZ_I2C_PORT_MASK
 
 enum MCHP_i2c_port {
 	MCHP_I2C_PORT0 = 0,
@@ -1064,8 +1046,8 @@ enum MCHP_i2c_port {
 };
 
 /* I2C ports & Configs */
-#define I2C_CONTROLLER_COUNT	MCHP_I2C_CTRL_MAX
-#define I2C_PORT_COUNT		MCHP_I2C_PORT_COUNT
+#define I2C_CONTROLLER_COUNT MCHP_I2C_CTRL_MAX
+#define I2C_PORT_COUNT MCHP_I2C_PORT_COUNT
 
 /*
  * I2C controllers 0-4 implement network layer hardware.
@@ -1073,167 +1055,164 @@ enum MCHP_i2c_port {
  * MEC152x has I2C promiscuous mode feature in the following
  * additional registers.
  */
-#define MCHP_I2C_SLAVE_ADDR(ctrl)	REG32(MCHP_I2C_ADDR(ctrl, 0x6c))
-#define MCHP_I2C_PROM_INTR(ctrl)	REG32(MCHP_I2C_ADDR(ctrl, 0x70))
-#define MCHP_I2C_PROM_INTR_EN(ctrl)	REG32(MCHP_I2C_ADDR(ctrl, 0x74))
-#define MCHP_I2C_PROM_CTRL(ctrl)	REG32(MCHP_I2C_ADDR(ctrl, 0x78))
+#define MCHP_I2C_SLAVE_ADDR(ctrl) REG32(MCHP_I2C_ADDR(ctrl, 0x6c))
+#define MCHP_I2C_PROM_INTR(ctrl) REG32(MCHP_I2C_ADDR(ctrl, 0x70))
+#define MCHP_I2C_PROM_INTR_EN(ctrl) REG32(MCHP_I2C_ADDR(ctrl, 0x74))
+#define MCHP_I2C_PROM_CTRL(ctrl) REG32(MCHP_I2C_ADDR(ctrl, 0x78))
 
 /* All I2C controllers connected to GIRQ13 */
-#define MCHP_I2C_GIRQ		13
+#define MCHP_I2C_GIRQ 13
 /* I2C[0:7] -> GIRQ13 bits[0:7] */
-#define MCHP_I2C_GIRQ_BIT(n)	BIT((n))
+#define MCHP_I2C_GIRQ_BIT(n) BIT((n))
 
 /* Keyboard scan matrix */
-#define MCHP_KS_GIRQ			21
-#define MCHP_KS_GIRQ_BIT		BIT(25)
-#define MCHP_KS_DIRECT_NVIC		135
+#define MCHP_KS_GIRQ 21
+#define MCHP_KS_GIRQ_BIT BIT(25)
+#define MCHP_KS_DIRECT_NVIC 135
 
 /* ADC */
-#define MCHP_ADC_GIRQ				17
-#define MCHP_ADC_GIRQ_SINGLE_BIT		BIT(8)
-#define MCHP_ADC_GIRQ_REPEAT_BIT		BIT(9)
-#define MCHP_ADC_SINGLE_DIRECT_NVIC		78
-#define MCHP_ADC_REPEAT_DIRECT_NVIC		79
+#define MCHP_ADC_GIRQ 17
+#define MCHP_ADC_GIRQ_SINGLE_BIT BIT(8)
+#define MCHP_ADC_GIRQ_REPEAT_BIT BIT(9)
+#define MCHP_ADC_SINGLE_DIRECT_NVIC 78
+#define MCHP_ADC_REPEAT_DIRECT_NVIC 79
 
 /* Hibernation timer */
-#define MCHP_HTIMER_SPACING			0x20
-#define MCHP_HTIMER_ADDR(n)		\
-	(MCHP_HTIMER_BASE + ((n) * MCHP_HTIMER_SPACING))
-#define MCHP_HTIMER_GIRQ			23
+#define MCHP_HTIMER_SPACING 0x20
+#define MCHP_HTIMER_ADDR(n) (MCHP_HTIMER_BASE + ((n)*MCHP_HTIMER_SPACING))
+#define MCHP_HTIMER_GIRQ 23
 /* HTIMER[0:1] -> GIRQ23 bits[16:17] */
-#define MCHP_HTIMER_GIRQ_BIT(n)			BIT(16 + (n))
-#define MCHP_HTIMER_DIRECT_NVIC(n)		(112 + (n))
+#define MCHP_HTIMER_GIRQ_BIT(n) BIT(16 + (n))
+#define MCHP_HTIMER_DIRECT_NVIC(n) (112 + (n))
 
 /*
  * Quad Master SPI (QMSPI)
  * MEC152x implements 16 descriptors, support for two chip selects,
  * and additional SPI signal timing registers.
  */
-#define MCHP_QMSPI_MAX_DESCR	16
+#define MCHP_QMSPI_MAX_DESCR 16
 /*
  * Chip select implemented in bit[13:12] of the Mode register.
  * These bits are reserved in earlier chips.
  */
-#define MCHP_QMSPI_M_CS_POS	12
-#define MCHP_QMSPI_M_CS_MASK0	0x03
-#define MCHP_QMSPI_M_CS_MASK	(0x03 << MCHP_QMSPI_M_CS_POS)
-#define MCHP_QMSPI_M_CS0	(0x00 << MCHP_QMSPI_M_CS_POS)
-#define MCHP_QMSPI_M_CS1	(0x01 << MCHP_QMSPI_M_CS_POS)
+#define MCHP_QMSPI_M_CS_POS 12
+#define MCHP_QMSPI_M_CS_MASK0 0x03
+#define MCHP_QMSPI_M_CS_MASK (0x03 << MCHP_QMSPI_M_CS_POS)
+#define MCHP_QMSPI_M_CS0 (0x00 << MCHP_QMSPI_M_CS_POS)
+#define MCHP_QMSPI_M_CS1 (0x01 << MCHP_QMSPI_M_CS_POS)
 
 /* New QMSPI chip select timing register */
-#define MCHP_QMSPI_CS_TIMING			\
-	REG32(MCHP_QMSPI0_BASE + 0x28)
-#define MCHP_QMSPI_CST_DFLT_VAL			0x06060406
-#define MCHP_QMSPI_CST_ON2CLK_MASK		0x0f
-#define MCHP_QMSPI_CST_ON2CLK_DFLT		0x06
-#define MCHP_QMSPI_CST_DLY_CLK2OFF_POS		8
-#define MCHP_QMSPI_CST_DLY_CLK2OFF_MASK0	0x0f
-#define MCHP_QMSPI_CST_DLY_CLK2OFF_MASK		0x0f00
-#define MCHP_QMSPI_CST_DLY_CLK2OFF_DFLT		0x0400
-#define MCHP_QMSPI_CST_DLY_LDH_POS		16
-#define MCHP_QMSPI_CST_DLY_LDH_MASK0		0x0f
-#define MCHP_QMSPI_CST_DLY_LDH_MASK		0xf0000
-#define MCHP_QMSPI_CST_DLY_LDH_DFLT		0x60000
-#define MCHP_QMSPI_CST_DLY_OFF2ON_POS		24
-#define MCHP_QMSPI_CST_DLY_OFF2ON_DFLT		0x06000000
-#define MCHP_QMSPI_CST_DLY_OFF2ON_MASK0		0xff
-#define MCHP_QMSPI_CST_DLY_OFF2ON_MASK		0xff000000
-
-#define MCHP_QMSPI_GIRQ		18
-#define MCHP_QMSPI_GIRQ_BIT	BIT(1)
-#define MCHP_QMSPI_DIRECT_NVIC	91
+#define MCHP_QMSPI_CS_TIMING REG32(MCHP_QMSPI0_BASE + 0x28)
+#define MCHP_QMSPI_CST_DFLT_VAL 0x06060406
+#define MCHP_QMSPI_CST_ON2CLK_MASK 0x0f
+#define MCHP_QMSPI_CST_ON2CLK_DFLT 0x06
+#define MCHP_QMSPI_CST_DLY_CLK2OFF_POS 8
+#define MCHP_QMSPI_CST_DLY_CLK2OFF_MASK0 0x0f
+#define MCHP_QMSPI_CST_DLY_CLK2OFF_MASK 0x0f00
+#define MCHP_QMSPI_CST_DLY_CLK2OFF_DFLT 0x0400
+#define MCHP_QMSPI_CST_DLY_LDH_POS 16
+#define MCHP_QMSPI_CST_DLY_LDH_MASK0 0x0f
+#define MCHP_QMSPI_CST_DLY_LDH_MASK 0xf0000
+#define MCHP_QMSPI_CST_DLY_LDH_DFLT 0x60000
+#define MCHP_QMSPI_CST_DLY_OFF2ON_POS 24
+#define MCHP_QMSPI_CST_DLY_OFF2ON_DFLT 0x06000000
+#define MCHP_QMSPI_CST_DLY_OFF2ON_MASK0 0xff
+#define MCHP_QMSPI_CST_DLY_OFF2ON_MASK 0xff000000
+
+#define MCHP_QMSPI_GIRQ 18
+#define MCHP_QMSPI_GIRQ_BIT BIT(1)
+#define MCHP_QMSPI_DIRECT_NVIC 91
 
 /* eSPI */
 
 /* IO BAR defines. Use with MCHP_ESPI_IO_BAR_xxxx macros */
-#define MCHP_ESPI_IO_BAR_ID_CFG_PORT	0
-#define MCHP_ESPI_IO_BAR_ID_MEM_CMPNT	1
-#define MCHP_ESPI_IO_BAR_ID_MAILBOX	2
-#define MCHP_ESPI_IO_BAR_ID_8042	3
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC0	4
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC1	5
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC2	6
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC3	7
-#define MCHP_ESPI_IO_BAR_ID_ACPI_PM1	9
-#define MCHP_ESPI_IO_BAR_ID_P92		0xA
-#define MCHP_ESPI_IO_BAR_ID_UART0	0xB
-#define MCHP_ESPI_IO_BAR_ID_UART1	0xC
-#define MCHP_ESPI_IO_BAR_ID_EMI0	0xD
-#define MCHP_ESPI_IO_BAR_ID_EMI1	0xE
-#define MCHP_ESPI_IO_BAR_P80_0		0x10
-#define MCHP_ESPI_IO_BAR_P80_1		0x11
-#define MCHP_ESPI_IO_BAR_RTC		0x12
-#define MCHP_ESPI_IO_BAR_ID_UART2	0x15
+#define MCHP_ESPI_IO_BAR_ID_CFG_PORT 0
+#define MCHP_ESPI_IO_BAR_ID_MEM_CMPNT 1
+#define MCHP_ESPI_IO_BAR_ID_MAILBOX 2
+#define MCHP_ESPI_IO_BAR_ID_8042 3
+#define MCHP_ESPI_IO_BAR_ID_ACPI_EC0 4
+#define MCHP_ESPI_IO_BAR_ID_ACPI_EC1 5
+#define MCHP_ESPI_IO_BAR_ID_ACPI_EC2 6
+#define MCHP_ESPI_IO_BAR_ID_ACPI_EC3 7
+#define MCHP_ESPI_IO_BAR_ID_ACPI_PM1 9
+#define MCHP_ESPI_IO_BAR_ID_P92 0xA
+#define MCHP_ESPI_IO_BAR_ID_UART0 0xB
+#define MCHP_ESPI_IO_BAR_ID_UART1 0xC
+#define MCHP_ESPI_IO_BAR_ID_EMI0 0xD
+#define MCHP_ESPI_IO_BAR_ID_EMI1 0xE
+#define MCHP_ESPI_IO_BAR_P80_0 0x10
+#define MCHP_ESPI_IO_BAR_P80_1 0x11
+#define MCHP_ESPI_IO_BAR_RTC 0x12
+#define MCHP_ESPI_IO_BAR_ID_UART2 0x15
 
 /* Use with MCHP_ESPI_MBAR_EC_xxxx(x) macros */
-#define MCHP_ESPI_MBAR_ID_MBOX		0
-#define MCHP_ESPI_MBAR_ID_ACPI_EC_0	1
-#define MCHP_ESPI_MBAR_ID_ACPI_EC_1	2
-#define MCHP_ESPI_MBAR_ID_ACPI_EC_2	3
-#define MCHP_ESPI_MBAR_ID_ACPI_EC_3	4
-#define MCHP_ESPI_MBAR_ID_EMI_0		6
-#define MCHP_ESPI_MBAR_ID_EMI_1		7
+#define MCHP_ESPI_MBAR_ID_MBOX 0
+#define MCHP_ESPI_MBAR_ID_ACPI_EC_0 1
+#define MCHP_ESPI_MBAR_ID_ACPI_EC_1 2
+#define MCHP_ESPI_MBAR_ID_ACPI_EC_2 3
+#define MCHP_ESPI_MBAR_ID_ACPI_EC_3 4
+#define MCHP_ESPI_MBAR_ID_EMI_0 6
+#define MCHP_ESPI_MBAR_ID_EMI_1 7
 
 /* Use with MCHP_ESPI_IO_SERIRQ_REG(x) */
-#define MCHP_ESPI_SIRQ_MBOX		0 /* Host SIRQ */
-#define MCHP_ESPI_SIRQ_MBOX_SMI		1 /* Host SMI */
-#define MCHP_ESPI_SIRQ_8042_KB		2 /* KIRQ */
-#define MCHP_ESPI_SIRQ_8042_MS		3 /* MIRQ */
-#define MCHP_ESPI_SIRQ_ACPI_EC0_OBF	4
-#define MCHP_ESPI_SIRQ_ACPI_EC1_OBF	5
-#define MCHP_ESPI_SIRQ_ACPI_EC2_OBF	6
-#define MCHP_ESPI_SIRQ_ACPI_EC3_OBF	7
-#define MCHP_ESPI_SIRQ_UART0		9
-#define MCHP_ESPI_SIRQ_UART1		10
-#define MCHP_ESPI_SIRQ_EMI0_HEV		11 /* Host Event */
-#define MCHP_ESPI_SIRQ_EMI0_EC2H	12 /* EC to Host */
-#define MCHP_ESPI_SIRQ_EMI1_HEV		13
-#define MCHP_ESPI_SIRQ_EMI1_EC2H	14
-#define MCHP_ESPI_SIRQ_RTC		17
-#define MCHP_ESPI_SIRQ_EC		18
-#define MCHP_ESPI_SIRQ_UART2		19
-
-#define MCHP_ESPI_MSVW_BASE	(MCHP_ESPI_VW_BASE)
-#define MCHP_ESPI_SMVW_BASE	((MCHP_ESPI_VW_BASE) + 0x200ul)
+#define MCHP_ESPI_SIRQ_MBOX 0 /* Host SIRQ */
+#define MCHP_ESPI_SIRQ_MBOX_SMI 1 /* Host SMI */
+#define MCHP_ESPI_SIRQ_8042_KB 2 /* KIRQ */
+#define MCHP_ESPI_SIRQ_8042_MS 3 /* MIRQ */
+#define MCHP_ESPI_SIRQ_ACPI_EC0_OBF 4
+#define MCHP_ESPI_SIRQ_ACPI_EC1_OBF 5
+#define MCHP_ESPI_SIRQ_ACPI_EC2_OBF 6
+#define MCHP_ESPI_SIRQ_ACPI_EC3_OBF 7
+#define MCHP_ESPI_SIRQ_UART0 9
+#define MCHP_ESPI_SIRQ_UART1 10
+#define MCHP_ESPI_SIRQ_EMI0_HEV 11 /* Host Event */
+#define MCHP_ESPI_SIRQ_EMI0_EC2H 12 /* EC to Host */
+#define MCHP_ESPI_SIRQ_EMI1_HEV 13
+#define MCHP_ESPI_SIRQ_EMI1_EC2H 14
+#define MCHP_ESPI_SIRQ_RTC 17
+#define MCHP_ESPI_SIRQ_EC 18
+#define MCHP_ESPI_SIRQ_UART2 19
+
+#define MCHP_ESPI_MSVW_BASE (MCHP_ESPI_VW_BASE)
+#define MCHP_ESPI_SMVW_BASE ((MCHP_ESPI_VW_BASE) + 0x200ul)
 
 /*
  * eSPI RESET, channel enables and operations except Master-to-Slave
  * WWires are all on GIRQ19
  */
-#define MCHP_ESPI_GIRQ			19
-#define MCHP_ESPI_PC_GIRQ_BIT		BIT(0)
-#define MCHP_ESPI_BM1_GIRQ_BIT		BIT(1)
-#define MCHP_ESPI_BM2_GIRQ_BIT		BIT(2)
-#define MCHP_ESPI_LTR_GIRQ_BIT		BIT(3)
-#define MCHP_ESPI_OOB_TX_GIRQ_BIT	BIT(4)
-#define MCHP_ESPI_OOB_RX_GIRQ_BIT	BIT(5)
-#define MCHP_ESPI_FC_GIRQ_BIT		BIT(6)
-#define MCHP_ESPI_RESET_GIRQ_BIT	BIT(7)
-#define MCHP_ESPI_VW_EN_GIRQ_BIT	BIT(8)
-#define MCHP_ESPI_SAF_DONE_GIRQ_BIT	BIT(9)
-#define MCHP_ESPI_SAF_ERR_GIRQ_BIT	BIT(10)
+#define MCHP_ESPI_GIRQ 19
+#define MCHP_ESPI_PC_GIRQ_BIT BIT(0)
+#define MCHP_ESPI_BM1_GIRQ_BIT BIT(1)
+#define MCHP_ESPI_BM2_GIRQ_BIT BIT(2)
+#define MCHP_ESPI_LTR_GIRQ_BIT BIT(3)
+#define MCHP_ESPI_OOB_TX_GIRQ_BIT BIT(4)
+#define MCHP_ESPI_OOB_RX_GIRQ_BIT BIT(5)
+#define MCHP_ESPI_FC_GIRQ_BIT BIT(6)
+#define MCHP_ESPI_RESET_GIRQ_BIT BIT(7)
+#define MCHP_ESPI_VW_EN_GIRQ_BIT BIT(8)
+#define MCHP_ESPI_SAF_DONE_GIRQ_BIT BIT(9)
+#define MCHP_ESPI_SAF_ERR_GIRQ_BIT BIT(10)
 
 /*
  * eSPI Master-to-Slave WWire interrupts are on GIRQ24 and GIRQ25
  */
-#define MCHP_ESPI_MSVW_0_6_GIRQ		24
-#define MCHP_ESPI_MSVW_7_10_GIRQ	25
+#define MCHP_ESPI_MSVW_0_6_GIRQ 24
+#define MCHP_ESPI_MSVW_7_10_GIRQ 25
 /*
  * Four source bits, SRC[0:3] per Master-to-Slave register
  * v = MSVW [0:10]
  * n = VWire SRC bit = [0:3]
  */
-#define MCHP_ESPI_MSVW_GIRQ(v)		(24 + ((v) > 6 ? 1 : 0))
+#define MCHP_ESPI_MSVW_GIRQ(v) (24 + ((v) > 6 ? 1 : 0))
 
 #define MCHP_ESPI_MSVW_SRC_GIRQ_BIT(v, n) \
-	(((v) > 6) ? (1ul << (((v)-7)+(n))) : (1ul << ((v)+(n))))
-
+	(((v) > 6) ? (1ul << (((v)-7) + (n))) : (1ul << ((v) + (n))))
 
 /* DMA */
-#define MCHP_DMA_MAX_CHAN	12
-#define MCHP_DMA_CH_OFS		0x40
-#define MCHP_DMA_CH_OFS_BITPOS	6
-#define MCHP_DMA_CH_BASE	(MCHP_DMA_BASE + MCHP_DMA_CH_OFS)
+#define MCHP_DMA_MAX_CHAN 12
+#define MCHP_DMA_CH_OFS 0x40
+#define MCHP_DMA_CH_OFS_BITPOS 6
+#define MCHP_DMA_CH_BASE (MCHP_DMA_BASE + MCHP_DMA_CH_OFS)
 
 /*
  * Available DMA channels.
@@ -1263,18 +1242,18 @@ enum dma_channel {
  * Peripheral device DMA Device ID's for bits [15:9]
  * in DMA channel control register.
  */
-#define MCHP_DMA_I2C0_SLV_REQ_ID	0
-#define MCHP_DMA_I2C0_MTR_REQ_ID	1
-#define MCHP_DMA_I2C1_SLV_REQ_ID	2
-#define MCHP_DMA_I2C1_MTR_REQ_ID	3
-#define MCHP_DMA_I2C2_SLV_REQ_ID	4
-#define MCHP_DMA_I2C2_MTR_REQ_ID	5
-#define MCHP_DMA_I2C3_SLV_REQ_ID	6
-#define MCHP_DMA_I2C3_MTR_REQ_ID	7
-#define MCHP_DMA_I2C4_SLV_REQ_ID	8
-#define MCHP_DMA_I2C4_MTR_REQ_ID	9
-#define MCHP_DMA_QMSPI0_TX_REQ_ID	10
-#define MCHP_DMA_QMSPI0_RX_REQ_ID	11
+#define MCHP_DMA_I2C0_SLV_REQ_ID 0
+#define MCHP_DMA_I2C0_MTR_REQ_ID 1
+#define MCHP_DMA_I2C1_SLV_REQ_ID 2
+#define MCHP_DMA_I2C1_MTR_REQ_ID 3
+#define MCHP_DMA_I2C2_SLV_REQ_ID 4
+#define MCHP_DMA_I2C2_MTR_REQ_ID 5
+#define MCHP_DMA_I2C3_SLV_REQ_ID 6
+#define MCHP_DMA_I2C3_MTR_REQ_ID 7
+#define MCHP_DMA_I2C4_SLV_REQ_ID 8
+#define MCHP_DMA_I2C4_MTR_REQ_ID 9
+#define MCHP_DMA_QMSPI0_TX_REQ_ID 10
+#define MCHP_DMA_QMSPI0_RX_REQ_ID 11
 
 /*
  * Hardware delay register.
@@ -1283,7 +1262,7 @@ enum dma_channel {
  * serviced during the delay period. Reads have
  * no effect.
  */
-#define MCHP_USEC_DELAY_REG_ADDR	0x10000000
-#define MCHP_USEC_DELAY(x)		(REG8(MCHP_USEC_DELAY_REG_ADDR) = (x))
+#define MCHP_USEC_DELAY_REG_ADDR 0x10000000
+#define MCHP_USEC_DELAY(x) (REG8(MCHP_USEC_DELAY_REG_ADDR) = (x))
 
 #endif /* #ifndef __ASSEMBLER__ */
diff --git a/chip/mchp/registers-mec1701.h b/chip/mchp/registers-mec1701.h
index bfe012a0d8..6894dc4056 100644
--- a/chip/mchp/registers-mec1701.h
+++ b/chip/mchp/registers-mec1701.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -14,219 +14,219 @@
  * NOTE: GIRQ22 aggregated output and its sources are not connected to
  * the NVIC.
  */
-#define MCHP_IRQ_GIRQ8		0
-#define MCHP_IRQ_GIRQ9		1
-#define MCHP_IRQ_GIRQ10		2
-#define MCHP_IRQ_GIRQ11		3
-#define MCHP_IRQ_GIRQ12		4
-#define MCHP_IRQ_GIRQ13		5
-#define MCHP_IRQ_GIRQ14		6
-#define MCHP_IRQ_GIRQ15		7
-#define MCHP_IRQ_GIRQ16		8
-#define MCHP_IRQ_GIRQ17		9
-#define MCHP_IRQ_GIRQ18		10
-#define MCHP_IRQ_GIRQ19		11
-#define MCHP_IRQ_GIRQ20		12
-#define MCHP_IRQ_GIRQ21		13
-#define MCHP_IRQ_GIRQ23		14
-#define MCHP_IRQ_GIRQ24		15
-#define MCHP_IRQ_GIRQ25		16
-#define MCHP_IRQ_GIRQ26		17
+#define MCHP_IRQ_GIRQ8 0
+#define MCHP_IRQ_GIRQ9 1
+#define MCHP_IRQ_GIRQ10 2
+#define MCHP_IRQ_GIRQ11 3
+#define MCHP_IRQ_GIRQ12 4
+#define MCHP_IRQ_GIRQ13 5
+#define MCHP_IRQ_GIRQ14 6
+#define MCHP_IRQ_GIRQ15 7
+#define MCHP_IRQ_GIRQ16 8
+#define MCHP_IRQ_GIRQ17 9
+#define MCHP_IRQ_GIRQ18 10
+#define MCHP_IRQ_GIRQ19 11
+#define MCHP_IRQ_GIRQ20 12
+#define MCHP_IRQ_GIRQ21 13
+#define MCHP_IRQ_GIRQ23 14
+#define MCHP_IRQ_GIRQ24 15
+#define MCHP_IRQ_GIRQ25 16
+#define MCHP_IRQ_GIRQ26 17
 /* GIRQ13 direct sources */
-#define MCHP_IRQ_I2C_0		20
-#define MCHP_IRQ_I2C_1		21
-#define MCHP_IRQ_I2C_2		22
-#define MCHP_IRQ_I2C_3		23
+#define MCHP_IRQ_I2C_0 20
+#define MCHP_IRQ_I2C_1 21
+#define MCHP_IRQ_I2C_2 22
+#define MCHP_IRQ_I2C_3 23
 /* GIRQ14 direct sources */
-#define MCHP_IRQ_DMA_0		24
-#define MCHP_IRQ_DMA_1		25
-#define MCHP_IRQ_DMA_2		26
-#define MCHP_IRQ_DMA_3		27
-#define MCHP_IRQ_DMA_4		28
-#define MCHP_IRQ_DMA_5		29
-#define MCHP_IRQ_DMA_6		30
-#define MCHP_IRQ_DMA_7		31
-#define MCHP_IRQ_DMA_8		32
-#define MCHP_IRQ_DMA_9		33
-#define MCHP_IRQ_DMA_10		34
-#define MCHP_IRQ_DMA_11		35
-#define MCHP_IRQ_DMA_12		36
-#define MCHP_IRQ_DMA_13		37
+#define MCHP_IRQ_DMA_0 24
+#define MCHP_IRQ_DMA_1 25
+#define MCHP_IRQ_DMA_2 26
+#define MCHP_IRQ_DMA_3 27
+#define MCHP_IRQ_DMA_4 28
+#define MCHP_IRQ_DMA_5 29
+#define MCHP_IRQ_DMA_6 30
+#define MCHP_IRQ_DMA_7 31
+#define MCHP_IRQ_DMA_8 32
+#define MCHP_IRQ_DMA_9 33
+#define MCHP_IRQ_DMA_10 34
+#define MCHP_IRQ_DMA_11 35
+#define MCHP_IRQ_DMA_12 36
+#define MCHP_IRQ_DMA_13 37
 /* GIRQ15 direct sources */
-#define MCHP_IRQ_UART0		40
-#define MCHP_IRQ_UART1		41
-#define MCHP_IRQ_EMI0		42
-#define MCHP_IRQ_EMI1		43
-#define MCHP_IRQ_EMI2		44
-#define MCHP_IRQ_ACPIEC0_IBF	45
-#define MCHP_IRQ_ACPIEC0_OBE	46
-#define MCHP_IRQ_ACPIEC1_IBF	47
-#define MCHP_IRQ_ACPIEC1_OBE	48
-#define MCHP_IRQ_ACPIEC2_IBF	49
-#define MCHP_IRQ_ACPIEC2_OBE	50
-#define MCHP_IRQ_ACPIEC3_IBF	51
-#define MCHP_IRQ_ACPIEC3_OBE	52
-#define MCHP_IRQ_ACPIEC4_IBF	53
-#define MCHP_IRQ_ACPIEC4_OBE	54
-#define MCHP_IRQ_ACPIPM1_CTL	55
-#define MCHP_IRQ_ACPIPM1_EN	56
-#define MCHP_IRQ_ACPIPM1_STS	57
-#define MCHP_IRQ_8042EM_OBE	58
-#define MCHP_IRQ_8042EM_IBF	59
-#define MCHP_IRQ_MAILBOX_DATA	60
-#define MCHP_IRQ_PORT80DBG0	62
-#define MCHP_IRQ_PORT80DBG1	63
+#define MCHP_IRQ_UART0 40
+#define MCHP_IRQ_UART1 41
+#define MCHP_IRQ_EMI0 42
+#define MCHP_IRQ_EMI1 43
+#define MCHP_IRQ_EMI2 44
+#define MCHP_IRQ_ACPIEC0_IBF 45
+#define MCHP_IRQ_ACPIEC0_OBE 46
+#define MCHP_IRQ_ACPIEC1_IBF 47
+#define MCHP_IRQ_ACPIEC1_OBE 48
+#define MCHP_IRQ_ACPIEC2_IBF 49
+#define MCHP_IRQ_ACPIEC2_OBE 50
+#define MCHP_IRQ_ACPIEC3_IBF 51
+#define MCHP_IRQ_ACPIEC3_OBE 52
+#define MCHP_IRQ_ACPIEC4_IBF 53
+#define MCHP_IRQ_ACPIEC4_OBE 54
+#define MCHP_IRQ_ACPIPM1_CTL 55
+#define MCHP_IRQ_ACPIPM1_EN 56
+#define MCHP_IRQ_ACPIPM1_STS 57
+#define MCHP_IRQ_8042EM_OBE 58
+#define MCHP_IRQ_8042EM_IBF 59
+#define MCHP_IRQ_MAILBOX_DATA 60
+#define MCHP_IRQ_PORT80DBG0 62
+#define MCHP_IRQ_PORT80DBG1 63
 /* GIRQ16 direct sources */
-#define MCHP_IRQ_PKE_ERR	65
-#define MCHP_IRQ_PKE_END	66
-#define MCHP_IRQ_NDRNG		67
-#define MCHP_IRQ_AES		68
-#define MCHP_IRQ_HASH		69
+#define MCHP_IRQ_PKE_ERR 65
+#define MCHP_IRQ_PKE_END 66
+#define MCHP_IRQ_NDRNG 67
+#define MCHP_IRQ_AES 68
+#define MCHP_IRQ_HASH 69
 /* GIRQ17 direct sources */
-#define MCHP_IRQ_PECI_HOST	70
-#define MCHP_IRQ_TACH_0		71
-#define MCHP_IRQ_TACH_1		72
-#define MCHP_IRQ_TACH_2		73
-#define MCHP_IRQ_FAN0_FAIL	74
-#define MCHP_IRQ_FAN0_STALL	75
-#define MCHP_IRQ_FAN1_FAIL	76
-#define MCHP_IRQ_FAN1_STALL	77
-#define MCHP_IRQ_ADC_SNGL	78
-#define MCHP_IRQ_ADC_RPT	79
-#define MCHP_IRQ_RCID0		80
-#define MCHP_IRQ_RCID1		81
-#define MCHP_IRQ_RCID2		82
-#define MCHP_IRQ_LED0_WDT	83
-#define MCHP_IRQ_LED1_WDT	84
-#define MCHP_IRQ_LED2_WDT	85
-#define MCHP_IRQ_LED3_WDT	86
-#define MCHP_IRQ_PHOT		87
-#define MCHP_IRQ_PWRGRD0	88
-#define MCHP_IRQ_PWRGRD1	89
+#define MCHP_IRQ_PECI_HOST 70
+#define MCHP_IRQ_TACH_0 71
+#define MCHP_IRQ_TACH_1 72
+#define MCHP_IRQ_TACH_2 73
+#define MCHP_IRQ_FAN0_FAIL 74
+#define MCHP_IRQ_FAN0_STALL 75
+#define MCHP_IRQ_FAN1_FAIL 76
+#define MCHP_IRQ_FAN1_STALL 77
+#define MCHP_IRQ_ADC_SNGL 78
+#define MCHP_IRQ_ADC_RPT 79
+#define MCHP_IRQ_RCID0 80
+#define MCHP_IRQ_RCID1 81
+#define MCHP_IRQ_RCID2 82
+#define MCHP_IRQ_LED0_WDT 83
+#define MCHP_IRQ_LED1_WDT 84
+#define MCHP_IRQ_LED2_WDT 85
+#define MCHP_IRQ_LED3_WDT 86
+#define MCHP_IRQ_PHOT 87
+#define MCHP_IRQ_PWRGRD0 88
+#define MCHP_IRQ_PWRGRD1 89
 /* GIRQ18 direct sources */
-#define MCHP_IRQ_LPC		90
-#define MCHP_IRQ_QMSPI0		91
-#define MCHP_IRQ_SPI0_TX	92
-#define MCHP_IRQ_SPI0_RX	93
-#define MCHP_IRQ_SPI1_TX	94
-#define MCHP_IRQ_SPI1_RX	95
-#define MCHP_IRQ_BCM0_ERR	96
-#define MCHP_IRQ_BCM0_BUSY	97
-#define MCHP_IRQ_BCM1_ERR	98
-#define MCHP_IRQ_BCM1_BUSY	99
-#define MCHP_IRQ_PS2_0		100
-#define MCHP_IRQ_PS2_1		101
-#define MCHP_IRQ_PS2_2		102
-#define MCHP_IRQ_EEPROM		155
+#define MCHP_IRQ_LPC 90
+#define MCHP_IRQ_QMSPI0 91
+#define MCHP_IRQ_SPI0_TX 92
+#define MCHP_IRQ_SPI0_RX 93
+#define MCHP_IRQ_SPI1_TX 94
+#define MCHP_IRQ_SPI1_RX 95
+#define MCHP_IRQ_BCM0_ERR 96
+#define MCHP_IRQ_BCM0_BUSY 97
+#define MCHP_IRQ_BCM1_ERR 98
+#define MCHP_IRQ_BCM1_BUSY 99
+#define MCHP_IRQ_PS2_0 100
+#define MCHP_IRQ_PS2_1 101
+#define MCHP_IRQ_PS2_2 102
+#define MCHP_IRQ_EEPROM 155
 /* GIRQ19 direct sources */
-#define MCHP_IRQ_ESPI_PC	103
-#define MCHP_IRQ_ESPI_BM1	104
-#define MCHP_IRQ_ESPI_BM2	105
-#define MCHP_IRQ_ESPI_LTR	106
-#define MCHP_IRQ_ESPI_OOB_UP	107
-#define MCHP_IRQ_ESPI_OOB_DN	108
-#define MCHP_IRQ_ESPI_FC	109
-#define MCHP_IRQ_ESPI_RESET	110
-#define MCHP_IRQ_ESPI_VW_EN	156
+#define MCHP_IRQ_ESPI_PC 103
+#define MCHP_IRQ_ESPI_BM1 104
+#define MCHP_IRQ_ESPI_BM2 105
+#define MCHP_IRQ_ESPI_LTR 106
+#define MCHP_IRQ_ESPI_OOB_UP 107
+#define MCHP_IRQ_ESPI_OOB_DN 108
+#define MCHP_IRQ_ESPI_FC 109
+#define MCHP_IRQ_ESPI_RESET 110
+#define MCHP_IRQ_ESPI_VW_EN 156
 /* GIRQ21 direct sources */
-#define MCHP_IRQ_RTOS_TIMER	111
-#define MCHP_IRQ_HTIMER0	112
-#define MCHP_IRQ_HTIMER1	113
-#define MCHP_IRQ_WEEK_ALARM	114
-#define MCHP_IRQ_SUBWEEK	115
-#define MCHP_IRQ_WEEK_SEC	116
-#define MCHP_IRQ_WEEK_SUBSEC	117
-#define MCHP_IRQ_WEEK_SYSPWR	118
-#define MCHP_IRQ_RTC		119
-#define MCHP_IRQ_RTC_ALARM	120
-#define MCHP_IRQ_VCI_OVRD_IN	121
-#define MCHP_IRQ_VCI_IN0	122
-#define MCHP_IRQ_VCI_IN1	123
-#define MCHP_IRQ_VCI_IN2	124
-#define MCHP_IRQ_VCI_IN3	125
-#define MCHP_IRQ_VCI_IN4	126
-#define MCHP_IRQ_VCI_IN5	127
-#define MCHP_IRQ_VCI_IN6	128
-#define MCHP_IRQ_PS20A_WAKE	129
-#define MCHP_IRQ_PS20B_WAKE	130
-#define MCHP_IRQ_PS21A_WAKE	131
-#define MCHP_IRQ_PS21B_WAKE	132
-#define MCHP_IRQ_PS2_2_WAKE	133
-#define MCHP_IRQ_ENVMON		134
-#define MCHP_IRQ_KSC_INT	135
+#define MCHP_IRQ_RTOS_TIMER 111
+#define MCHP_IRQ_HTIMER0 112
+#define MCHP_IRQ_HTIMER1 113
+#define MCHP_IRQ_WEEK_ALARM 114
+#define MCHP_IRQ_SUBWEEK 115
+#define MCHP_IRQ_WEEK_SEC 116
+#define MCHP_IRQ_WEEK_SUBSEC 117
+#define MCHP_IRQ_WEEK_SYSPWR 118
+#define MCHP_IRQ_RTC 119
+#define MCHP_IRQ_RTC_ALARM 120
+#define MCHP_IRQ_VCI_OVRD_IN 121
+#define MCHP_IRQ_VCI_IN0 122
+#define MCHP_IRQ_VCI_IN1 123
+#define MCHP_IRQ_VCI_IN2 124
+#define MCHP_IRQ_VCI_IN3 125
+#define MCHP_IRQ_VCI_IN4 126
+#define MCHP_IRQ_VCI_IN5 127
+#define MCHP_IRQ_VCI_IN6 128
+#define MCHP_IRQ_PS20A_WAKE 129
+#define MCHP_IRQ_PS20B_WAKE 130
+#define MCHP_IRQ_PS21A_WAKE 131
+#define MCHP_IRQ_PS21B_WAKE 132
+#define MCHP_IRQ_PS2_2_WAKE 133
+#define MCHP_IRQ_ENVMON 134
+#define MCHP_IRQ_KSC_INT 135
 /* GIRQ23 direct sources */
-#define MCHP_IRQ_TIMER16_0	136
-#define MCHP_IRQ_TIMER16_1	137
-#define MCHP_IRQ_TIMER16_2	138
-#define MCHP_IRQ_TIMER16_3	139
-#define MCHP_IRQ_TIMER32_0	140
-#define MCHP_IRQ_TIMER32_1	141
-#define MCHP_IRQ_CNTR_TM0	142
-#define MCHP_IRQ_CNTR_TM1	143
-#define MCHP_IRQ_CNTR_TM2	144
-#define MCHP_IRQ_CNTR_TM3	145
-#define MCHP_IRQ_CCT_TMR	146
-#define MCHP_IRQ_CCT_CAP0	147
-#define MCHP_IRQ_CCT_CAP1	148
-#define MCHP_IRQ_CCT_CAP2	149
-#define MCHP_IRQ_CCT_CAP3	150
-#define MCHP_IRQ_CCT_CAP4	151
-#define MCHP_IRQ_CCT_CAP5	152
-#define MCHP_IRQ_CCT_CMP0	153
-#define MCHP_IRQ_CCT_CMP1	154
+#define MCHP_IRQ_TIMER16_0 136
+#define MCHP_IRQ_TIMER16_1 137
+#define MCHP_IRQ_TIMER16_2 138
+#define MCHP_IRQ_TIMER16_3 139
+#define MCHP_IRQ_TIMER32_0 140
+#define MCHP_IRQ_TIMER32_1 141
+#define MCHP_IRQ_CNTR_TM0 142
+#define MCHP_IRQ_CNTR_TM1 143
+#define MCHP_IRQ_CNTR_TM2 144
+#define MCHP_IRQ_CNTR_TM3 145
+#define MCHP_IRQ_CCT_TMR 146
+#define MCHP_IRQ_CCT_CAP0 147
+#define MCHP_IRQ_CCT_CAP1 148
+#define MCHP_IRQ_CCT_CAP2 149
+#define MCHP_IRQ_CCT_CAP3 150
+#define MCHP_IRQ_CCT_CAP4 151
+#define MCHP_IRQ_CCT_CAP5 152
+#define MCHP_IRQ_CCT_CMP0 153
+#define MCHP_IRQ_CCT_CMP1 154
 /* Must match CONFIG_IRQ_COUNT in config_chip.h */
 #define MCHP_IRQ_MAX 157
 
 /* Block base addresses */
-#define MCHP_WDG_BASE		0x40000000
-#define MCHP_TMR16_0_BASE	0x40000c00
-#define MCHP_TMR32_0_BASE	0x40000c80
-#define MCHP_CNT16_0_BASE	0x40000d00
-#define MCHP_DMA_BASE		0x40002400
-#define MCHP_PROCHOT_BASE	0x40003400
-#define MCHP_I2C0_BASE		0x40004000
-#define MCHP_I2C1_BASE		0x40004400
-#define MCHP_I2C2_BASE		0x40004800
-#define MCHP_I2C3_BASE		0x40004C00
-#define MCHP_QMSPI0_BASE	0x40005400
-#define MCHP_PWM_0_BASE		0x40005800
-#define MCHP_TACH_0_BASE	0x40006000
-#define MCHP_PECI_BASE		0x40006400
-#define MCHP_RTMR_BASE		0x40007400
-#define MCHP_ADC_BASE		0x40007c00
-#define MCHP_TFDP_BASE		0x40008c00
-#define MCHP_GPSPI0_BASE	0x40009400
-#define MCHP_GPSPI1_BASE	0x40009480
-#define MCHP_HTIMER_BASE	0x40009800
-#define MCHP_KEYSCAN_BASE	0x40009c00
-#define MCHP_RPM2PWM0_BASE	0x4000a000
-#define MCHP_RPM2PWM1_BASE	0x4000a080
-#define MCHP_VBAT_BASE		0x4000a400
-#define MCHP_VBAT_RAM_BASE	0x4000a800
-#define MCHP_WKTIMER_BASE	0x4000ac80
-#define MCHP_BBLED_0_BASE	0x4000B800
-#define MCHP_INT_BASE		0x4000e000
-#define MCHP_EC_BASE		0x4000fc00
-
-#define MCHP_PCR_BASE		0x40080100
-#define MCHP_GPIO_BASE		0x40081000
-
-#define MCHP_MBOX_BASE		0x400f0000
-#define MCHP_8042_BASE		0x400f0400
-#define MCHP_ACPI_EC_0_BASE	0x400f0800
-#define MCHP_ACPI_PM1_BASE	0x400f1c00
-#define MCHP_UART0_BASE		0x400f2400
-#define MCHP_UART1_BASE		0x400f2800
-#define MCHP_LPC_BASE		0x400f3000
-#define MCHP_ESPI_IO_BASE	0x400f3400
-#define MCHP_ESPI_MEM_BASE	0x400f3800
-#define MCHP_EMI_0_BASE		0x400f4000
-#define MCHP_EMI_1_BASE		0x400f4400
-#define MCHP_EMI_2_BASE		0x400f4800
-#define MCHP_P80CAP0_BASE	0x400f8000
-#define MCHP_P80CAP1_BASE	0x400f8400
-#define MCHP_ESPI_VW_BASE	0x400f9c00
-#define MCHP_CHIP_BASE		0x400fff00
+#define MCHP_WDG_BASE 0x40000000
+#define MCHP_TMR16_0_BASE 0x40000c00
+#define MCHP_TMR32_0_BASE 0x40000c80
+#define MCHP_CNT16_0_BASE 0x40000d00
+#define MCHP_DMA_BASE 0x40002400
+#define MCHP_PROCHOT_BASE 0x40003400
+#define MCHP_I2C0_BASE 0x40004000
+#define MCHP_I2C1_BASE 0x40004400
+#define MCHP_I2C2_BASE 0x40004800
+#define MCHP_I2C3_BASE 0x40004C00
+#define MCHP_QMSPI0_BASE 0x40005400
+#define MCHP_PWM_0_BASE 0x40005800
+#define MCHP_TACH_0_BASE 0x40006000
+#define MCHP_PECI_BASE 0x40006400
+#define MCHP_RTMR_BASE 0x40007400
+#define MCHP_ADC_BASE 0x40007c00
+#define MCHP_TFDP_BASE 0x40008c00
+#define MCHP_GPSPI0_BASE 0x40009400
+#define MCHP_GPSPI1_BASE 0x40009480
+#define MCHP_HTIMER_BASE 0x40009800
+#define MCHP_KEYSCAN_BASE 0x40009c00
+#define MCHP_RPM2PWM0_BASE 0x4000a000
+#define MCHP_RPM2PWM1_BASE 0x4000a080
+#define MCHP_VBAT_BASE 0x4000a400
+#define MCHP_VBAT_RAM_BASE 0x4000a800
+#define MCHP_WKTIMER_BASE 0x4000ac80
+#define MCHP_BBLED_0_BASE 0x4000B800
+#define MCHP_INT_BASE 0x4000e000
+#define MCHP_EC_BASE 0x4000fc00
+
+#define MCHP_PCR_BASE 0x40080100
+#define MCHP_GPIO_BASE 0x40081000
+
+#define MCHP_MBOX_BASE 0x400f0000
+#define MCHP_8042_BASE 0x400f0400
+#define MCHP_ACPI_EC_0_BASE 0x400f0800
+#define MCHP_ACPI_PM1_BASE 0x400f1c00
+#define MCHP_UART0_BASE 0x400f2400
+#define MCHP_UART1_BASE 0x400f2800
+#define MCHP_LPC_BASE 0x400f3000
+#define MCHP_ESPI_IO_BASE 0x400f3400
+#define MCHP_ESPI_MEM_BASE 0x400f3800
+#define MCHP_EMI_0_BASE 0x400f4000
+#define MCHP_EMI_1_BASE 0x400f4400
+#define MCHP_EMI_2_BASE 0x400f4800
+#define MCHP_P80CAP0_BASE 0x400f8000
+#define MCHP_P80CAP1_BASE 0x400f8400
+#define MCHP_ESPI_VW_BASE 0x400f9c00
+#define MCHP_CHIP_BASE 0x400fff00
 
 #ifndef __ASSEMBLER__
 
@@ -236,238 +236,236 @@
  * Cortex-M4 bit-banding does require aliasing of the
  * DATA SRAM region.
  */
-#define MCHP_RAM_ALIAS(x) \
-	((x) >= 0x118000 ? (x) - 0x118000 + 0x20000000 : (x))
+#define MCHP_RAM_ALIAS(x) ((x) >= 0x118000 ? (x)-0x118000 + 0x20000000 : (x))
 
 /* EC Chip Configuration */
 /* 8-bit Device ID */
-#define MCHP_CHIP_DEV_ID	REG8(MCHP_CHIP_BASE + 0x20)
+#define MCHP_CHIP_DEV_ID REG8(MCHP_CHIP_BASE + 0x20)
 /* 8-bit Device Revision */
-#define MCHP_CHIP_DEV_REV	REG8(MCHP_CHIP_BASE + 0x21)
+#define MCHP_CHIP_DEV_REV REG8(MCHP_CHIP_BASE + 0x21)
 
 /* PCR clock control dividers */
-#define MCHP_PCR_CLK_CTL_FASTEST	1U
-#define MCHP_PCR_CLK_CTL_48MHZ		1U
-#define MCHP_PCR_CLK_CTL_12MHZ		4U
+#define MCHP_PCR_CLK_CTL_FASTEST 1U
+#define MCHP_PCR_CLK_CTL_48MHZ 1U
+#define MCHP_PCR_CLK_CTL_12MHZ 4U
 
 /* Number of PCR Sleep Enable, Clock Required, and Reset registers */
 #define MCHP_PCR_SLP_RST_REG_MAX 5
 
 /* Sleep 0: Sleep Enable, Clock Required, and Reset bits */
-#define MCHP_PCR_JTAG		BIT(0) /* CLKREQ only */
-#define MCHP_PCR_OTP		BIT(1)
-#define MCHP_PCR_ISPI		BIT(2)
+#define MCHP_PCR_JTAG BIT(0) /* CLKREQ only */
+#define MCHP_PCR_OTP BIT(1)
+#define MCHP_PCR_ISPI BIT(2)
 
 /* Command all blocks to sleep */
-#define MCHP_PCR_SLP_EN0_JTAG	BIT(0)
-#define MCHP_PCR_SLP_EN0_OTP	BIT(1)
-#define MCHP_PCR_SLP_EN0_ISPI	BIT(2)
-#define MCHP_PCR_SLP_EN0_SLEEP	0xffffffff
+#define MCHP_PCR_SLP_EN0_JTAG BIT(0)
+#define MCHP_PCR_SLP_EN0_OTP BIT(1)
+#define MCHP_PCR_SLP_EN0_ISPI BIT(2)
+#define MCHP_PCR_SLP_EN0_SLEEP 0xffffffff
 
 /*
  * Encode register number and bit position
  * b[4:0] = bit number
  * b[10:8] = zero based register number
  */
-#define MCHP_PCR_ERB(rnum, bnum) \
-	((((rnum) & 0x0f) << 8) | ((bnum) & 0x1f))
+#define MCHP_PCR_ERB(rnum, bnum) ((((rnum)&0x0f) << 8) | ((bnum)&0x1f))
 
 /* PCR Sleep 1: Sleep Enable, Clock Required, and Reset bits */
-#define MCHP_PCR_BTMR16_1	MCHP_PCR_ERB(1, 31)
-#define MCHP_PCR_BTMR16_0	MCHP_PCR_ERB(1, 30)
-#define MCHP_PCR_ECS		MCHP_PCR_ERB(1, 29)
-#define MCHP_PCR_PWM8		MCHP_PCR_ERB(1, 27)
-#define MCHP_PCR_PWM7		MCHP_PCR_ERB(1, 26)
-#define MCHP_PCR_PWM6		MCHP_PCR_ERB(1, 25)
-#define MCHP_PCR_PWM5		MCHP_PCR_ERB(1, 24)
-#define MCHP_PCR_PWM4		MCHP_PCR_ERB(1, 23)
-#define MCHP_PCR_PWM3		MCHP_PCR_ERB(1, 22)
-#define MCHP_PCR_PWM2		MCHP_PCR_ERB(1, 21)
-#define MCHP_PCR_PWM1		MCHP_PCR_ERB(1, 20)
-#define MCHP_PCR_TACH2		MCHP_PCR_ERB(1, 12)
-#define MCHP_PCR_TACH1		MCHP_PCR_ERB(1, 11)
-#define MCHP_PCR_I2C0		MCHP_PCR_ERB(1, 10)
-#define MCHP_PCR_WDT		MCHP_PCR_ERB(1, 9)
-#define MCHP_PCR_CPU		MCHP_PCR_ERB(1, 8)
-#define MCHP_PCR_TFDP		MCHP_PCR_ERB(1, 7)
-#define MCHP_PCR_DMA		MCHP_PCR_ERB(1, 6)
-#define MCHP_PCR_PMC		MCHP_PCR_ERB(1, 5)
-#define MCHP_PCR_PWM0		MCHP_PCR_ERB(1, 4)
-#define MCHP_PCR_TACH0		MCHP_PCR_ERB(1, 2)
-#define MCHP_PCR_PECI		MCHP_PCR_ERB(1, 1)
-#define MCHP_PCR_ECIA		MCHP_PCR_ERB(1, 0)
+#define MCHP_PCR_BTMR16_1 MCHP_PCR_ERB(1, 31)
+#define MCHP_PCR_BTMR16_0 MCHP_PCR_ERB(1, 30)
+#define MCHP_PCR_ECS MCHP_PCR_ERB(1, 29)
+#define MCHP_PCR_PWM8 MCHP_PCR_ERB(1, 27)
+#define MCHP_PCR_PWM7 MCHP_PCR_ERB(1, 26)
+#define MCHP_PCR_PWM6 MCHP_PCR_ERB(1, 25)
+#define MCHP_PCR_PWM5 MCHP_PCR_ERB(1, 24)
+#define MCHP_PCR_PWM4 MCHP_PCR_ERB(1, 23)
+#define MCHP_PCR_PWM3 MCHP_PCR_ERB(1, 22)
+#define MCHP_PCR_PWM2 MCHP_PCR_ERB(1, 21)
+#define MCHP_PCR_PWM1 MCHP_PCR_ERB(1, 20)
+#define MCHP_PCR_TACH2 MCHP_PCR_ERB(1, 12)
+#define MCHP_PCR_TACH1 MCHP_PCR_ERB(1, 11)
+#define MCHP_PCR_I2C0 MCHP_PCR_ERB(1, 10)
+#define MCHP_PCR_WDT MCHP_PCR_ERB(1, 9)
+#define MCHP_PCR_CPU MCHP_PCR_ERB(1, 8)
+#define MCHP_PCR_TFDP MCHP_PCR_ERB(1, 7)
+#define MCHP_PCR_DMA MCHP_PCR_ERB(1, 6)
+#define MCHP_PCR_PMC MCHP_PCR_ERB(1, 5)
+#define MCHP_PCR_PWM0 MCHP_PCR_ERB(1, 4)
+#define MCHP_PCR_TACH0 MCHP_PCR_ERB(1, 2)
+#define MCHP_PCR_PECI MCHP_PCR_ERB(1, 1)
+#define MCHP_PCR_ECIA MCHP_PCR_ERB(1, 0)
 
 /* Command all blocks to sleep */
-#define MCHP_PCR_SLP_EN1_BTMR16_1	BIT(31)
-#define MCHP_PCR_SLP_EN1_BTMR16_0	BIT(30)
-#define MCHP_PCR_SLP_EN1_ECS		BIT(29)
-#define MCHP_PCR_SLP_EN1_PWM_ALL	(BIT(4) + (0xff << 20))
-#define MCHP_PCR_SLP_EN1_PWM8		BIT(27)
-#define MCHP_PCR_SLP_EN1_PWM7		BIT(26)
-#define MCHP_PCR_SLP_EN1_PWM6		BIT(25)
-#define MCHP_PCR_SLP_EN1_PWM5		BIT(24)
-#define MCHP_PCR_SLP_EN1_PWM4		BIT(23)
-#define MCHP_PCR_SLP_EN1_PWM3		BIT(22)
-#define MCHP_PCR_SLP_EN1_PWM2		BIT(21)
-#define MCHP_PCR_SLP_EN1_PWM1		BIT(20)
-#define MCHP_PCR_SLP_EN1_TACH2		BIT(12)
-#define MCHP_PCR_SLP_EN1_TACH1		BIT(11)
-#define MCHP_PCR_SLP_EN1_I2C0		BIT(10)
-#define MCHP_PCR_SLP_EN1_WDT		BIT(9)
-#define MCHP_PCR_SLP_EN1_CPU		BIT(8)
-#define MCHP_PCR_SLP_EN1_TFDP		BIT(7)
-#define MCHP_PCR_SLP_EN1_DMA		BIT(6)
-#define MCHP_PCR_SLP_EN1_PMC		BIT(5)
-#define MCHP_PCR_SLP_EN1_PWM0		BIT(4)
-#define MCHP_PCR_SLP_EN1_TACH0		BIT(2)
-#define MCHP_PCR_SLP_EN1_PECI		BIT(1)
-#define MCHP_PCR_SLP_EN1_ECIA		BIT(0)
+#define MCHP_PCR_SLP_EN1_BTMR16_1 BIT(31)
+#define MCHP_PCR_SLP_EN1_BTMR16_0 BIT(30)
+#define MCHP_PCR_SLP_EN1_ECS BIT(29)
+#define MCHP_PCR_SLP_EN1_PWM_ALL (BIT(4) + (0xff << 20))
+#define MCHP_PCR_SLP_EN1_PWM8 BIT(27)
+#define MCHP_PCR_SLP_EN1_PWM7 BIT(26)
+#define MCHP_PCR_SLP_EN1_PWM6 BIT(25)
+#define MCHP_PCR_SLP_EN1_PWM5 BIT(24)
+#define MCHP_PCR_SLP_EN1_PWM4 BIT(23)
+#define MCHP_PCR_SLP_EN1_PWM3 BIT(22)
+#define MCHP_PCR_SLP_EN1_PWM2 BIT(21)
+#define MCHP_PCR_SLP_EN1_PWM1 BIT(20)
+#define MCHP_PCR_SLP_EN1_TACH2 BIT(12)
+#define MCHP_PCR_SLP_EN1_TACH1 BIT(11)
+#define MCHP_PCR_SLP_EN1_I2C0 BIT(10)
+#define MCHP_PCR_SLP_EN1_WDT BIT(9)
+#define MCHP_PCR_SLP_EN1_CPU BIT(8)
+#define MCHP_PCR_SLP_EN1_TFDP BIT(7)
+#define MCHP_PCR_SLP_EN1_DMA BIT(6)
+#define MCHP_PCR_SLP_EN1_PMC BIT(5)
+#define MCHP_PCR_SLP_EN1_PWM0 BIT(4)
+#define MCHP_PCR_SLP_EN1_TACH0 BIT(2)
+#define MCHP_PCR_SLP_EN1_PECI BIT(1)
+#define MCHP_PCR_SLP_EN1_ECIA BIT(0)
 /* all sleep enable 1 bits */
-#define MCHP_PCR_SLP_EN1_SLEEP		0xffffffff
+#define MCHP_PCR_SLP_EN1_SLEEP 0xffffffff
 /*
  * block not used by default
  * Do not sleep ECIA, PMC, CPU and ECS
  */
-#define MCHP_PCR_SLP_EN1_UNUSED_BLOCKS	0xdffffede
+#define MCHP_PCR_SLP_EN1_UNUSED_BLOCKS 0xdffffede
 
 /* PCR Sleep 2: Sleep Enable, Clock Required 2, Reset bits */
-#define MCHP_PCR_P80CAP1	MCHP_PCR_ERB(2, 26)
-#define MCHP_PCR_P80CAP0	MCHP_PCR_ERB(2, 25)
-#define MCHP_PCR_ACPI_EC4	MCHP_PCR_ERB(2, 23)
-#define MCHP_PCR_ACPI_EC3	MCHP_PCR_ERB(2, 22)
-#define MCHP_PCR_ACPI_EC2	MCHP_PCR_ERB(2, 21)
-#define MCHP_PCR_ESPI		MCHP_PCR_ERB(2, 19)
-#define MCHP_PCR_RTC		MCHP_PCR_ERB(2, 18)
-#define MCHP_PCR_MBOX		MCHP_PCR_ERB(2, 17)
-#define MCHP_PCR_8042		MCHP_PCR_ERB(2, 26)
-#define MCHP_PCR_ACPI_PM1	MCHP_PCR_ERB(2, 15)
-#define MCHP_PCR_ACPI_EC1	MCHP_PCR_ERB(2, 14)
-#define MCHP_PCR_ACPI_EC0	MCHP_PCR_ERB(2, 13)
-#define MCHP_PCR_GCFG		MCHP_PCR_ERB(2, 12)
-#define MCHP_PCR_UART1		MCHP_PCR_ERB(2, 2)
-#define MCHP_PCR_UART0		MCHP_PCR_ERB(2, 1)
-#define MCHP_PCR_LPC		MCHP_PCR_ERB(2, 0)
+#define MCHP_PCR_P80CAP1 MCHP_PCR_ERB(2, 26)
+#define MCHP_PCR_P80CAP0 MCHP_PCR_ERB(2, 25)
+#define MCHP_PCR_ACPI_EC4 MCHP_PCR_ERB(2, 23)
+#define MCHP_PCR_ACPI_EC3 MCHP_PCR_ERB(2, 22)
+#define MCHP_PCR_ACPI_EC2 MCHP_PCR_ERB(2, 21)
+#define MCHP_PCR_ESPI MCHP_PCR_ERB(2, 19)
+#define MCHP_PCR_RTC MCHP_PCR_ERB(2, 18)
+#define MCHP_PCR_MBOX MCHP_PCR_ERB(2, 17)
+#define MCHP_PCR_8042 MCHP_PCR_ERB(2, 26)
+#define MCHP_PCR_ACPI_PM1 MCHP_PCR_ERB(2, 15)
+#define MCHP_PCR_ACPI_EC1 MCHP_PCR_ERB(2, 14)
+#define MCHP_PCR_ACPI_EC0 MCHP_PCR_ERB(2, 13)
+#define MCHP_PCR_GCFG MCHP_PCR_ERB(2, 12)
+#define MCHP_PCR_UART1 MCHP_PCR_ERB(2, 2)
+#define MCHP_PCR_UART0 MCHP_PCR_ERB(2, 1)
+#define MCHP_PCR_LPC MCHP_PCR_ERB(2, 0)
 
 /* Command all blocks to sleep */
-#define MCHP_PCR_SLP_EN2_P80CAP1	BIT(26)
-#define MCHP_PCR_SLP_EN2_P80CAP0	BIT(25)
-#define MCHP_PCR_SLP_EN2_ACPI_EC4	BIT(23)
-#define MCHP_PCR_SLP_EN2_ACPI_EC3	BIT(22)
-#define MCHP_PCR_SLP_EN2_ACPI_EC2	BIT(21)
-#define MCHP_PCR_SLP_EN2_ESPI_SCR	BIT(20)
-#define MCHP_PCR_SLP_EN2_ESPI		BIT(19)
-#define MCHP_PCR_SLP_EN2_RTC		BIT(18)
-#define MCHP_PCR_SLP_EN2_MAILBOX	BIT(17)
-#define MCHP_PCR_SLP_EN2_MIF8042	BIT(16)
-#define MCHP_PCR_SLP_EN2_ACPI_PM1	BIT(15)
-#define MCHP_PCR_SLP_EN2_ACPI_EC1	BIT(14)
-#define MCHP_PCR_SLP_EN2_ACPI_EC0	BIT(13)
-#define MCHP_PCR_SLP_EN2_GCFG		BIT(12)
-#define MCHP_PCR_SLP_EN2_UART1		BIT(2)
-#define MCHP_PCR_SLP_EN2_UART0		BIT(1)
-#define MCHP_PCR_SLP_EN2_LPC		BIT(0)
+#define MCHP_PCR_SLP_EN2_P80CAP1 BIT(26)
+#define MCHP_PCR_SLP_EN2_P80CAP0 BIT(25)
+#define MCHP_PCR_SLP_EN2_ACPI_EC4 BIT(23)
+#define MCHP_PCR_SLP_EN2_ACPI_EC3 BIT(22)
+#define MCHP_PCR_SLP_EN2_ACPI_EC2 BIT(21)
+#define MCHP_PCR_SLP_EN2_ESPI_SCR BIT(20)
+#define MCHP_PCR_SLP_EN2_ESPI BIT(19)
+#define MCHP_PCR_SLP_EN2_RTC BIT(18)
+#define MCHP_PCR_SLP_EN2_MAILBOX BIT(17)
+#define MCHP_PCR_SLP_EN2_MIF8042 BIT(16)
+#define MCHP_PCR_SLP_EN2_ACPI_PM1 BIT(15)
+#define MCHP_PCR_SLP_EN2_ACPI_EC1 BIT(14)
+#define MCHP_PCR_SLP_EN2_ACPI_EC0 BIT(13)
+#define MCHP_PCR_SLP_EN2_GCFG BIT(12)
+#define MCHP_PCR_SLP_EN2_UART1 BIT(2)
+#define MCHP_PCR_SLP_EN2_UART0 BIT(1)
+#define MCHP_PCR_SLP_EN2_LPC BIT(0)
 /* all sleep enable 2 bits */
-#define MCHP_PCR_SLP_EN2_SLEEP		0xffffffff
+#define MCHP_PCR_SLP_EN2_SLEEP 0xffffffff
 
 /* PCR Sleep 3: Sleep Enable, Clock Required, and Reset */
-#define MCHP_PCR_PWM9		MCHP_PCR_ERB(3, 31)
-#define MCHP_PCR_CCT0		MCHP_PCR_ERB(3, 30)
-#define MCHP_PCR_HTMR1		MCHP_PCR_ERB(3, 29)
-#define MCHP_PCR_AESHASH	MCHP_PCR_ERB(3, 28)
-#define MCHP_PCR_RNG		MCHP_PCR_ERB(3, 27)
-#define MCHP_PCR_PKE		MCHP_PCR_ERB(3, 26)
-#define MCHP_PCR_LED3		MCHP_PCR_ERB(3, 25)
-#define MCHP_PCR_BTMR32_1	MCHP_PCR_ERB(3, 24)
-#define MCHP_PCR_BTMR32_0	MCHP_PCR_ERB(3, 23)
-#define MCHP_PCR_BTMR16_3	MCHP_PCR_ERB(3, 22)
-#define MCHP_PCR_BTMR16_2	MCHP_PCR_ERB(3, 21)
-#define MCHP_PCR_GPSPI1		MCHP_PCR_ERB(3, 20)
-#define MCHP_PCR_BCM0		MCHP_PCR_ERB(3, 19)
-#define MCHP_PCR_LED2		MCHP_PCR_ERB(3, 18)
-#define MCHP_PCR_LED1		MCHP_PCR_ERB(3, 17)
-#define MCHP_PCR_LED0		MCHP_PCR_ERB(3, 16)
-#define MCHP_PCR_I2C3		MCHP_PCR_ERB(3, 15)
-#define MCHP_PCR_I2C2		MCHP_PCR_ERB(3, 14)
-#define MCHP_PCR_I2C1		MCHP_PCR_ERB(3, 13)
-#define MCHP_PCR_RPMPWM0	MCHP_PCR_ERB(3, 12)
-#define MCHP_PCR_KEYSCAN	MCHP_PCR_ERB(3, 11)
-#define MCHP_PCR_HTMR0		MCHP_PCR_ERB(3, 10)
-#define MCHP_PCR_GPSPI0		MCHP_PCR_ERB(3, 9)
-#define MCHP_PCR_PS2_2		MCHP_PCR_ERB(3, 7)
-#define MCHP_PCR_PS2_1		MCHP_PCR_ERB(3, 6)
-#define MCHP_PCR_PS2_0		MCHP_PCR_ERB(3, 5)
-#define MCHP_PCR_ADC		MCHP_PCR_ERB(3, 3)
+#define MCHP_PCR_PWM9 MCHP_PCR_ERB(3, 31)
+#define MCHP_PCR_CCT0 MCHP_PCR_ERB(3, 30)
+#define MCHP_PCR_HTMR1 MCHP_PCR_ERB(3, 29)
+#define MCHP_PCR_AESHASH MCHP_PCR_ERB(3, 28)
+#define MCHP_PCR_RNG MCHP_PCR_ERB(3, 27)
+#define MCHP_PCR_PKE MCHP_PCR_ERB(3, 26)
+#define MCHP_PCR_LED3 MCHP_PCR_ERB(3, 25)
+#define MCHP_PCR_BTMR32_1 MCHP_PCR_ERB(3, 24)
+#define MCHP_PCR_BTMR32_0 MCHP_PCR_ERB(3, 23)
+#define MCHP_PCR_BTMR16_3 MCHP_PCR_ERB(3, 22)
+#define MCHP_PCR_BTMR16_2 MCHP_PCR_ERB(3, 21)
+#define MCHP_PCR_GPSPI1 MCHP_PCR_ERB(3, 20)
+#define MCHP_PCR_BCM0 MCHP_PCR_ERB(3, 19)
+#define MCHP_PCR_LED2 MCHP_PCR_ERB(3, 18)
+#define MCHP_PCR_LED1 MCHP_PCR_ERB(3, 17)
+#define MCHP_PCR_LED0 MCHP_PCR_ERB(3, 16)
+#define MCHP_PCR_I2C3 MCHP_PCR_ERB(3, 15)
+#define MCHP_PCR_I2C2 MCHP_PCR_ERB(3, 14)
+#define MCHP_PCR_I2C1 MCHP_PCR_ERB(3, 13)
+#define MCHP_PCR_RPMPWM0 MCHP_PCR_ERB(3, 12)
+#define MCHP_PCR_KEYSCAN MCHP_PCR_ERB(3, 11)
+#define MCHP_PCR_HTMR0 MCHP_PCR_ERB(3, 10)
+#define MCHP_PCR_GPSPI0 MCHP_PCR_ERB(3, 9)
+#define MCHP_PCR_PS2_2 MCHP_PCR_ERB(3, 7)
+#define MCHP_PCR_PS2_1 MCHP_PCR_ERB(3, 6)
+#define MCHP_PCR_PS2_0 MCHP_PCR_ERB(3, 5)
+#define MCHP_PCR_ADC MCHP_PCR_ERB(3, 3)
 
 /* Command blocks to sleep */
-#define MCHP_PCR_SLP_EN3_PWM9		BIT(31)
-#define MCHP_PCR_SLP_EN3_CCT0		BIT(30)
-#define MCHP_PCR_SLP_EN3_HTMR1		BIT(29)
-#define MCHP_PCR_SLP_EN3_AESHASH	BIT(28)
-#define MCHP_PCR_SLP_EN3_RNG		BIT(27)
-#define MCHP_PCR_SLP_EN3_PKE		BIT(26)
-#define MCHP_PCR_SLP_EN3_LED3		BIT(25)
-#define MCHP_PCR_SLP_EN3_BTMR32_1	BIT(24)
-#define MCHP_PCR_SLP_EN3_BTMR32_0	BIT(23)
-#define MCHP_PCR_SLP_EN3_BTMR16_3	BIT(22)
-#define MCHP_PCR_SLP_EN3_BTMR16_2	BIT(21)
-#define MCHP_PCR_SLP_EN3_I2C4		BIT(20)
-#define MCHP_PCR_SLP_EN3_BCM0		BIT(19)
-#define MCHP_PCR_SLP_EN3_LED2		BIT(18)
-#define MCHP_PCR_SLP_EN3_LED1		BIT(17)
-#define MCHP_PCR_SLP_EN3_LED0		BIT(16)
-#define MCHP_PCR_SLP_EN3_I2C3		BIT(15)
-#define MCHP_PCR_SLP_EN3_I2C2		BIT(14)
-#define MCHP_PCR_SLP_EN3_I2C1		BIT(13)
-#define MCHP_PCR_SLP_EN3_RPM2PWM0	BIT(12)
-#define MCHP_PCR_SLP_EN3_KEYSCAN	BIT(11)
-#define MCHP_PCR_SLP_EN3_HTMR0		BIT(10)
-#define MCHP_PCR_SLP_EN3_GPSPI0		BIT(9)
-#define MCHP_PCR_SLP_EN3_PS2_2		BIT(7)
-#define MCHP_PCR_SLP_EN3_PS2_1		BIT(6)
-#define MCHP_PCR_SLP_EN3_PS2_0		BIT(5)
-#define MCHP_PCR_SLP_EN3_ADC		BIT(3)
-#define MCHP_PCR_SLP_EN3_ALL_CRYPTO	(0x07 << 26)
+#define MCHP_PCR_SLP_EN3_PWM9 BIT(31)
+#define MCHP_PCR_SLP_EN3_CCT0 BIT(30)
+#define MCHP_PCR_SLP_EN3_HTMR1 BIT(29)
+#define MCHP_PCR_SLP_EN3_AESHASH BIT(28)
+#define MCHP_PCR_SLP_EN3_RNG BIT(27)
+#define MCHP_PCR_SLP_EN3_PKE BIT(26)
+#define MCHP_PCR_SLP_EN3_LED3 BIT(25)
+#define MCHP_PCR_SLP_EN3_BTMR32_1 BIT(24)
+#define MCHP_PCR_SLP_EN3_BTMR32_0 BIT(23)
+#define MCHP_PCR_SLP_EN3_BTMR16_3 BIT(22)
+#define MCHP_PCR_SLP_EN3_BTMR16_2 BIT(21)
+#define MCHP_PCR_SLP_EN3_I2C4 BIT(20)
+#define MCHP_PCR_SLP_EN3_BCM0 BIT(19)
+#define MCHP_PCR_SLP_EN3_LED2 BIT(18)
+#define MCHP_PCR_SLP_EN3_LED1 BIT(17)
+#define MCHP_PCR_SLP_EN3_LED0 BIT(16)
+#define MCHP_PCR_SLP_EN3_I2C3 BIT(15)
+#define MCHP_PCR_SLP_EN3_I2C2 BIT(14)
+#define MCHP_PCR_SLP_EN3_I2C1 BIT(13)
+#define MCHP_PCR_SLP_EN3_RPM2PWM0 BIT(12)
+#define MCHP_PCR_SLP_EN3_KEYSCAN BIT(11)
+#define MCHP_PCR_SLP_EN3_HTMR0 BIT(10)
+#define MCHP_PCR_SLP_EN3_GPSPI0 BIT(9)
+#define MCHP_PCR_SLP_EN3_PS2_2 BIT(7)
+#define MCHP_PCR_SLP_EN3_PS2_1 BIT(6)
+#define MCHP_PCR_SLP_EN3_PS2_0 BIT(5)
+#define MCHP_PCR_SLP_EN3_ADC BIT(3)
+#define MCHP_PCR_SLP_EN3_ALL_CRYPTO (0x07 << 26)
 /* all sleep enable 3 bits */
-#define MCHP_PCR_SLP_EN3_SLEEP		0xffffffff
-#define MCHP_PCR_SLP_EN3_PWM_ALL	(MCHP_PCR_SLP_EN3_PWM9)
+#define MCHP_PCR_SLP_EN3_SLEEP 0xffffffff
+#define MCHP_PCR_SLP_EN3_PWM_ALL (MCHP_PCR_SLP_EN3_PWM9)
 
 /* PCR Sleep 4: Sleep Enable, Clock Required, Reset */
-#define MCHP_PCR_FJCL		MCHP_PCR_ERB(4, 15)
-#define MCHP_PCR_PSPI		MCHP_PCR_ERB(4, 14)
-#define MCHP_PCR_PROCHOT	MCHP_PCR_ERB(4, 13)
-#define MCHP_PCR_RCID2		MCHP_PCR_ERB(4, 12)
-#define MCHP_PCR_RCID1		MCHP_PCR_ERB(4, 11)
-#define MCHP_PCR_RCID0		MCHP_PCR_ERB(4, 10)
-#define MCHP_PCR_BCM1		MCHP_PCR_ERB(4, 9)
-#define MCHP_PCR_QMSPI		MCHP_PCR_ERB(4, 8)
-#define MCHP_PCR_RPMPWM1	MCHP_PCR_ERB(4, 7)
-#define MCHP_PCR_RTMR		MCHP_PCR_ERB(4, 6)
-#define MCHP_PCR_CNT16_3	MCHP_PCR_ERB(4, 5)
-#define MCHP_PCR_CNT16_2	MCHP_PCR_ERB(4, 4)
-#define MCHP_PCR_CNT16_1	MCHP_PCR_ERB(4, 3)
-#define MCHP_PCR_CNT16_0	MCHP_PCR_ERB(4, 2)
-#define MCHP_PCR_PWM11		MCHP_PCR_ERB(4, 1)
-#define MCHP_PCR_PWM10		MCHP_PCR_ERB(4, 0)
+#define MCHP_PCR_FJCL MCHP_PCR_ERB(4, 15)
+#define MCHP_PCR_PSPI MCHP_PCR_ERB(4, 14)
+#define MCHP_PCR_PROCHOT MCHP_PCR_ERB(4, 13)
+#define MCHP_PCR_RCID2 MCHP_PCR_ERB(4, 12)
+#define MCHP_PCR_RCID1 MCHP_PCR_ERB(4, 11)
+#define MCHP_PCR_RCID0 MCHP_PCR_ERB(4, 10)
+#define MCHP_PCR_BCM1 MCHP_PCR_ERB(4, 9)
+#define MCHP_PCR_QMSPI MCHP_PCR_ERB(4, 8)
+#define MCHP_PCR_RPMPWM1 MCHP_PCR_ERB(4, 7)
+#define MCHP_PCR_RTMR MCHP_PCR_ERB(4, 6)
+#define MCHP_PCR_CNT16_3 MCHP_PCR_ERB(4, 5)
+#define MCHP_PCR_CNT16_2 MCHP_PCR_ERB(4, 4)
+#define MCHP_PCR_CNT16_1 MCHP_PCR_ERB(4, 3)
+#define MCHP_PCR_CNT16_0 MCHP_PCR_ERB(4, 2)
+#define MCHP_PCR_PWM11 MCHP_PCR_ERB(4, 1)
+#define MCHP_PCR_PWM10 MCHP_PCR_ERB(4, 0)
 
 /* Command blocks to sleep */
-#define MCHP_PCR_SLP_EN4_FJCL		BIT(15)
-#define MCHP_PCR_SLP_EN4_PSPI		BIT(14)
-#define MCHP_PCR_SLP_EN4_PROCHOT	BIT(13)
-#define MCHP_PCR_SLP_EN4_RCID2		BIT(12)
-#define MCHP_PCR_SLP_EN4_RCID1		BIT(11)
-#define MCHP_PCR_SLP_EN4_RCID0		BIT(10)
-#define MCHP_PCR_SLP_EN4_QMSPI		BIT(8)
-#define MCHP_PCR_SLP_EN4_RPMPWM1	BIT(7)
-#define MCHP_PCR_SLP_EN4_RTMR		BIT(6)
-#define MCHP_PCR_SLP_EN4_CNT16_3	BIT(5)
-#define MCHP_PCR_SLP_EN4_CNT16_2	BIT(4)
-#define MCHP_PCR_SLP_EN4_CNT16_1	BIT(3)
-#define MCHP_PCR_SLP_EN4_CNT16_0	BIT(2)
-#define MCHP_PCR_SLP_EN4_PWM11		BIT(1)
-#define MCHP_PCR_SLP_EN4_PWM10		BIT(0)
+#define MCHP_PCR_SLP_EN4_FJCL BIT(15)
+#define MCHP_PCR_SLP_EN4_PSPI BIT(14)
+#define MCHP_PCR_SLP_EN4_PROCHOT BIT(13)
+#define MCHP_PCR_SLP_EN4_RCID2 BIT(12)
+#define MCHP_PCR_SLP_EN4_RCID1 BIT(11)
+#define MCHP_PCR_SLP_EN4_RCID0 BIT(10)
+#define MCHP_PCR_SLP_EN4_QMSPI BIT(8)
+#define MCHP_PCR_SLP_EN4_RPMPWM1 BIT(7)
+#define MCHP_PCR_SLP_EN4_RTMR BIT(6)
+#define MCHP_PCR_SLP_EN4_CNT16_3 BIT(5)
+#define MCHP_PCR_SLP_EN4_CNT16_2 BIT(4)
+#define MCHP_PCR_SLP_EN4_CNT16_1 BIT(3)
+#define MCHP_PCR_SLP_EN4_CNT16_0 BIT(2)
+#define MCHP_PCR_SLP_EN4_PWM11 BIT(1)
+#define MCHP_PCR_SLP_EN4_PWM10 BIT(0)
 
 /* all sleep enable 4 bits */
-#define MCHP_PCR_SLP_EN4_SLEEP		0xffffffff
+#define MCHP_PCR_SLP_EN4_SLEEP 0xffffffff
 #define MCHP_PCR_SLP_EN4_PWM_ALL \
 	(MCHP_PCR_SLP_EN4_PWM10 | MCHP_PCR_SLP_EN4_PWM11)
 
@@ -479,75 +477,75 @@
 #define MCHP_PCR_SLP_EN4_WAKE (~(MCHP_PCR_SLP_EN4_SLEEP))
 
 /* Bit defines for MCHP_PCR_PWR_RST_STS */
-#define MCHP_PWR_RST_STS_MASK_RO	0xc8c
-#define MCHP_PWR_RST_STS_MASK_RWC	0x060
+#define MCHP_PWR_RST_STS_MASK_RO 0xc8c
+#define MCHP_PWR_RST_STS_MASK_RWC 0x060
 #define MCHP_PWR_RST_STS_MASK \
 	((MCHP_PWR_RST_STS_MASK_RO) | (MCHP_PWR_RST_STS_MASK_RWC))
 
-#define MCHP_PWR_RST_STS_ESPI_CLK_ACT	BIT(11) /* RO */
-#define MCHP_PWR_RST_STS_32K_ACT	BIT(10) /* RO */
-#define MCHP_PWR_RST_STS_JTAG_RSTN	BIT(7) /* RO */
-#define MCHP_PWR_RST_STS_SYS		BIT(6) /* R/WC */
+#define MCHP_PWR_RST_STS_ESPI_CLK_ACT BIT(11) /* RO */
+#define MCHP_PWR_RST_STS_32K_ACT BIT(10) /* RO */
+#define MCHP_PWR_RST_STS_JTAG_RSTN BIT(7) /* RO */
+#define MCHP_PWR_RST_STS_SYS BIT(6) /* R/WC */
 /* same function, old bit name */
-#define MCHP_PWR_RST_STS_VTR		BIT(6)
-#define MCHP_PWR_RST_STS_VBAT		BIT(5) /* R/WC */
-#define MCHP_PWR_RST_STS_HOST		BIT(3) /* RO */
-#define MCHP_PWR_RST_STS_VCC_PWRGD	BIT(2) /* RO */
+#define MCHP_PWR_RST_STS_VTR BIT(6)
+#define MCHP_PWR_RST_STS_VBAT BIT(5) /* R/WC */
+#define MCHP_PWR_RST_STS_HOST BIT(3) /* RO */
+#define MCHP_PWR_RST_STS_VCC_PWRGD BIT(2) /* RO */
 
 /* Bit defines for MCHP_PCR_PWR_RST_CTL */
-#define MCHP_PCR_PWR_HOST_RST_SEL_BITPOS	8
-#define MCHP_PCR_PWR_HOST_RST_PCI_RESET		BIT(8)
-#define MCHP_PCR_PWR_HOST_RST_ESPI_PLTRST	(0 << 8)
-#define MCHP_PCR_PWR_OK_INV_BITPOS		0
+#define MCHP_PCR_PWR_HOST_RST_SEL_BITPOS 8
+#define MCHP_PCR_PWR_HOST_RST_PCI_RESET BIT(8)
+#define MCHP_PCR_PWR_HOST_RST_ESPI_PLTRST (0 << 8)
+#define MCHP_PCR_PWR_OK_INV_BITPOS 0
 
 /* Bit defines for MCHP_PCR_SYS_RST */
-#define MCHP_PCR_SYS_SOFT_RESET			BIT(8)
+#define MCHP_PCR_SYS_SOFT_RESET BIT(8)
 
 /* EC Subsystem */
-#define MCHP_EC_AHB_ERR			REG32(MCHP_EC_BASE + 0x04)
-#define MCHP_EC_ID_RO			REG32(MCHP_EC_BASE + 0x10)
-#define MCHP_EC_AHB_ERR_EN		REG32(MCHP_EC_BASE + 0x14)
-#define MCHP_EC_INT_CTRL		REG32(MCHP_EC_BASE + 0x18)
-#define MCHP_EC_TRACE_EN		REG32(MCHP_EC_BASE + 0x1c)
-#define MCHP_EC_JTAG_EN			REG32(MCHP_EC_BASE + 0x20)
-#define MCHP_EC_WDT_CNT			REG32(MCHP_EC_BASE + 0x28)
-#define MCHP_EC_AES_SHA_SWAP_CTRL	REG8(MCHP_EC_BASE + 0x2c)
-#define MCHP_EC_PECI_DISABLE		REG8(MCHP_EC_BASE + 0x40)
-#define MCHP_EC_CRYPTO_SRESET		REG8(MCHP_EC_BASE + 0x5c)
-#define MCHP_EC_GPIO_BANK_PWR		REG8(MCHP_EC_BASE + 0x64)
+#define MCHP_EC_AHB_ERR REG32(MCHP_EC_BASE + 0x04)
+#define MCHP_EC_ID_RO REG32(MCHP_EC_BASE + 0x10)
+#define MCHP_EC_AHB_ERR_EN REG32(MCHP_EC_BASE + 0x14)
+#define MCHP_EC_INT_CTRL REG32(MCHP_EC_BASE + 0x18)
+#define MCHP_EC_TRACE_EN REG32(MCHP_EC_BASE + 0x1c)
+#define MCHP_EC_JTAG_EN REG32(MCHP_EC_BASE + 0x20)
+#define MCHP_EC_WDT_CNT REG32(MCHP_EC_BASE + 0x28)
+#define MCHP_EC_AES_SHA_SWAP_CTRL REG8(MCHP_EC_BASE + 0x2c)
+#define MCHP_EC_PECI_DISABLE REG8(MCHP_EC_BASE + 0x40)
+#define MCHP_EC_CRYPTO_SRESET REG8(MCHP_EC_BASE + 0x5c)
+#define MCHP_EC_GPIO_BANK_PWR REG8(MCHP_EC_BASE + 0x64)
 
 /* AHB ERR Enable bit[0]=0(enable), 1(disable) */
-#define MCHP_EC_AHB_ERROR_ENABLE	0
-#define MCHP_EC_AHB_ERROR_DISABLE	1
+#define MCHP_EC_AHB_ERROR_ENABLE 0
+#define MCHP_EC_AHB_ERROR_DISABLE 1
 
 /* MCHP_EC_JTAG_EN bit definitions */
-#define MCHP_JTAG_ENABLE		0x01
+#define MCHP_JTAG_ENABLE 0x01
 /* bits [2:1] */
-#define MCHP_JTAG_MODE_4PIN		0x00
+#define MCHP_JTAG_MODE_4PIN 0x00
 /* ARM 2-pin SWD plus 1-pin Serial Wire Viewer (ITM) */
-#define MCHP_JTAG_MODE_SWD_SWV		0x02
+#define MCHP_JTAG_MODE_SWD_SWV 0x02
 /* ARM 2-pin SWD with no SWV */
-#define MCHP_JTAG_MODE_SWD		0x04
+#define MCHP_JTAG_MODE_SWD 0x04
 
 /* MCHP_EC_CRYPTO_SRESET bit definitions. Bits cleared by HW */
-#define MCHP_CRYPTO_NDRNG_SRST		0x01
-#define MCHP_CRYPTO_PKE_SRST		0x02
-#define MCHP_CRYPTO_AES_SHA_SRST	0x04
-#define MCHP_CRYPTO_ALL_SRST		0x07
+#define MCHP_CRYPTO_NDRNG_SRST 0x01
+#define MCHP_CRYPTO_PKE_SRST 0x02
+#define MCHP_CRYPTO_AES_SHA_SRST 0x04
+#define MCHP_CRYPTO_ALL_SRST 0x07
 
 /* MCHP_GPIO_BANK_PWR bit definitions */
-#define MCHP_EC_GPIO_BANK_PWR_MASK	0x86
-#define MCHP_EC_GPIO_BANK_PWR_VTR2_18	0x02
-#define MCHP_EC_GPIO_BANK_PWR_VTR3_18	0x04
-#define MCHP_EC_GPIO_BANK_PWR_LOCK	0x80
+#define MCHP_EC_GPIO_BANK_PWR_MASK 0x86
+#define MCHP_EC_GPIO_BANK_PWR_VTR2_18 0x02
+#define MCHP_EC_GPIO_BANK_PWR_VTR3_18 0x04
+#define MCHP_EC_GPIO_BANK_PWR_LOCK 0x80
 
 /* EC Interrupt aggregator (ECIA) */
-#define MCHP_INT_GIRQ_LEN	20 /* 5 32-bit registers */
-#define MCHP_INT_GIRQ_FIRST	8
-#define MCHP_INT_GIRQ_LAST	26
-#define MCHP_INT_GIRQ_NUM	(26-8+1)
+#define MCHP_INT_GIRQ_LEN 20 /* 5 32-bit registers */
+#define MCHP_INT_GIRQ_FIRST 8
+#define MCHP_INT_GIRQ_LAST 26
+#define MCHP_INT_GIRQ_NUM (26 - 8 + 1)
 /* MCHP_INT_GIRQ_FIRST <= x <= MCHP_INT_GIRQ_LAST */
-#define MCHP_INTx_BASE(x) (MCHP_INT_BASE + (((x) - 8) * MCHP_INT_GIRQ_LEN))
+#define MCHP_INTx_BASE(x) (MCHP_INT_BASE + (((x)-8) * MCHP_INT_GIRQ_LEN))
 
 /*
  * GPIO GIRQ's are not direct capable
@@ -561,8 +559,8 @@
  * GIRQ22 wake peripheral clock only
  * GIRQ24, GIRQ25 eSPI host to endpoint virtual wires
  */
-#define MCHP_INT_AGGR_ONLY_BITMAP	0x07401F00U
-#define MCHP_INT_DIRECT_CAPABLE_BITMAP	0x00BFE000U
+#define MCHP_INT_AGGR_ONLY_BITMAP 0x07401F00U
+#define MCHP_INT_DIRECT_CAPABLE_BITMAP 0x00BFE000U
 
 /* GIRQ13 I2C controllers. Direct capable */
 #define MCHP_INT13_I2C(x) (1ul << (x))
@@ -571,148 +569,148 @@
 #define MCHP_INT14_DMA(x) (1ul << (x))
 
 /* GIQ15 interrupt sources. Direct capable */
-#define MCHP_INT15_UART_0		BIT(0)
-#define MCHP_INT15_UART_1		BIT(1)
-#define MCHP_INT15_EMI_0		BIT(2)
-#define MCHP_INT15_EMI_1		BIT(3)
-#define MCHP_INT15_EMI_2		BIT(4)
-#define MCHP_INT15_ACPI_EC0_IBF		BIT(5)
-#define MCHP_INT15_ACPI_EC0_OBE		BIT(6)
-#define MCHP_INT15_ACPI_EC1_IBF		BIT(7)
-#define MCHP_INT15_ACPI_EC1_OBE		BIT(8)
-#define MCHP_INT15_ACPI_EC2_IBF		BIT(9)
-#define MCHP_INT15_ACPI_EC2_OBE		BIT(10)
-#define MCHP_INT15_ACPI_EC3_IBF		BIT(11)
-#define MCHP_INT15_ACPI_EC3_OBE		BIT(12)
-#define MCHP_INT15_ACPI_EC4_IBF		BIT(13)
-#define MCHP_INT15_ACPI_EC4_OBE		BIT(14)
-#define MCHP_INT15_ACPI_PM1_CTL		BIT(15)
-#define MCHP_INT15_ACPI_PM1_EN		BIT(16)
-#define MCHP_INT15_ACPI_PM1_STS		BIT(17)
-#define MCHP_INT15_8042_OBE		BIT(18)
-#define MCHP_INT15_8042_IBF		BIT(19)
-#define MCHP_INT15_MAILBOX		BIT(20)
-#define MCHP_INT15_P80_0		BIT(22)
-#define MCHP_INT15_P80_1		BIT(23)
-#define MCHP_INT15_P80(x)		BIT(22 + ((x) & 0x01U))
+#define MCHP_INT15_UART_0 BIT(0)
+#define MCHP_INT15_UART_1 BIT(1)
+#define MCHP_INT15_EMI_0 BIT(2)
+#define MCHP_INT15_EMI_1 BIT(3)
+#define MCHP_INT15_EMI_2 BIT(4)
+#define MCHP_INT15_ACPI_EC0_IBF BIT(5)
+#define MCHP_INT15_ACPI_EC0_OBE BIT(6)
+#define MCHP_INT15_ACPI_EC1_IBF BIT(7)
+#define MCHP_INT15_ACPI_EC1_OBE BIT(8)
+#define MCHP_INT15_ACPI_EC2_IBF BIT(9)
+#define MCHP_INT15_ACPI_EC2_OBE BIT(10)
+#define MCHP_INT15_ACPI_EC3_IBF BIT(11)
+#define MCHP_INT15_ACPI_EC3_OBE BIT(12)
+#define MCHP_INT15_ACPI_EC4_IBF BIT(13)
+#define MCHP_INT15_ACPI_EC4_OBE BIT(14)
+#define MCHP_INT15_ACPI_PM1_CTL BIT(15)
+#define MCHP_INT15_ACPI_PM1_EN BIT(16)
+#define MCHP_INT15_ACPI_PM1_STS BIT(17)
+#define MCHP_INT15_8042_OBE BIT(18)
+#define MCHP_INT15_8042_IBF BIT(19)
+#define MCHP_INT15_MAILBOX BIT(20)
+#define MCHP_INT15_P80_0 BIT(22)
+#define MCHP_INT15_P80_1 BIT(23)
+#define MCHP_INT15_P80(x) BIT(22 + ((x)&0x01U))
 
 /* GIRQ16 interrupt sources. Direct capable */
-#define MCHP_INT16_PKE_ERR		BIT(0)
-#define MCHP_INT16_PKE_DONE		BIT(1)
-#define MCHP_INT16_RNG_DONE		BIT(2)
-#define MCHP_INT16_AES_DONE		BIT(3)
-#define MCHP_INT16_HASH_DONE		BIT(4)
+#define MCHP_INT16_PKE_ERR BIT(0)
+#define MCHP_INT16_PKE_DONE BIT(1)
+#define MCHP_INT16_RNG_DONE BIT(2)
+#define MCHP_INT16_AES_DONE BIT(3)
+#define MCHP_INT16_HASH_DONE BIT(4)
 
 /* GIR17 interrupt sources. Direct capable */
-#define MCHP_INT17_PECI			BIT(0)
-#define MCHP_INT17_TACH_0		BIT(1)
-#define MCHP_INT17_TACH_1		BIT(2)
-#define MCHP_INT17_TACH_2		BIT(3)
-#define MCHP_INT17_RPM2PWM0_FAIL	BIT(4)
-#define MCHP_INT17_RPM2PWM0_STALL	BIT(5)
-#define MCHP_INT17_RPM2PWM1_FAIL	BIT(6)
-#define MCHP_INT17_RPM2PWM1_STALL	BIT(7)
-#define MCHP_INT17_ADC_SINGLE		BIT(8)
-#define MCHP_INT17_ADC_REPEAT		BIT(9)
-#define MCHP_INT17_RCID_0		BIT(10)
-#define MCHP_INT17_RCID_1		BIT(11)
-#define MCHP_INT17_RCID_2		BIT(12)
-#define MCHP_INT17_LED_WDT_0		BIT(13)
-#define MCHP_INT17_LED_WDT_1		BIT(14)
-#define MCHP_INT17_LED_WDT_2		BIT(15)
-#define MCHP_INT17_LED_WDT_3		BIT(16)
-#define MCHP_INT17_PROCHOT		BIT(17)
-#define MCHP_INT17_PWRGRD0		BIT(18)
-#define MCHP_INT17_PWRGRD1		BIT(19)
+#define MCHP_INT17_PECI BIT(0)
+#define MCHP_INT17_TACH_0 BIT(1)
+#define MCHP_INT17_TACH_1 BIT(2)
+#define MCHP_INT17_TACH_2 BIT(3)
+#define MCHP_INT17_RPM2PWM0_FAIL BIT(4)
+#define MCHP_INT17_RPM2PWM0_STALL BIT(5)
+#define MCHP_INT17_RPM2PWM1_FAIL BIT(6)
+#define MCHP_INT17_RPM2PWM1_STALL BIT(7)
+#define MCHP_INT17_ADC_SINGLE BIT(8)
+#define MCHP_INT17_ADC_REPEAT BIT(9)
+#define MCHP_INT17_RCID_0 BIT(10)
+#define MCHP_INT17_RCID_1 BIT(11)
+#define MCHP_INT17_RCID_2 BIT(12)
+#define MCHP_INT17_LED_WDT_0 BIT(13)
+#define MCHP_INT17_LED_WDT_1 BIT(14)
+#define MCHP_INT17_LED_WDT_2 BIT(15)
+#define MCHP_INT17_LED_WDT_3 BIT(16)
+#define MCHP_INT17_PROCHOT BIT(17)
+#define MCHP_INT17_PWRGRD0 BIT(18)
+#define MCHP_INT17_PWRGRD1 BIT(19)
 
 /* GIRQ18 interrupt sources. Direct capable */
-#define MCHP_INT18_LPC_ERR		BIT(0)
-#define MCHP_INT18_QMSPI		BIT(1)
-#define MCHP_INT18_GPSPI0_TXBE		BIT(2)
-#define MCHP_INT18_GPSPI0_RXBF		BIT(3)
-#define MCHP_INT18_GPSPI1_TXBE		BIT(4)
-#define MCHP_INT18_GPSPI1_RXBF		BIT(5)
-#define MCHP_INT18_BCM0_BUSY		BIT(6)
-#define MCHP_INT18_BCM0_ERR		BIT(7)
-#define MCHP_INT18_BCM1_BUSY		BIT(8)
-#define MCHP_INT18_BCM1_ERR		BIT(9)
-#define MCHP_INT18_PS2_0		BIT(10)
-#define MCHP_INT18_PS2_1		BIT(11)
-#define MCHP_INT18_PS2_2		BIT(12)
-#define MCHP_INT18_PSPI			BIT(13)
+#define MCHP_INT18_LPC_ERR BIT(0)
+#define MCHP_INT18_QMSPI BIT(1)
+#define MCHP_INT18_GPSPI0_TXBE BIT(2)
+#define MCHP_INT18_GPSPI0_RXBF BIT(3)
+#define MCHP_INT18_GPSPI1_TXBE BIT(4)
+#define MCHP_INT18_GPSPI1_RXBF BIT(5)
+#define MCHP_INT18_BCM0_BUSY BIT(6)
+#define MCHP_INT18_BCM0_ERR BIT(7)
+#define MCHP_INT18_BCM1_BUSY BIT(8)
+#define MCHP_INT18_BCM1_ERR BIT(9)
+#define MCHP_INT18_PS2_0 BIT(10)
+#define MCHP_INT18_PS2_1 BIT(11)
+#define MCHP_INT18_PS2_2 BIT(12)
+#define MCHP_INT18_PSPI BIT(13)
 
 /* GIRQ19 interrupt sources. Direct capable */
-#define MCHP_INT19_ESPI_PC		BIT(0)
-#define MCHP_INT19_ESPI_BM1		BIT(1)
-#define MCHP_INT19_ESPI_BM2		BIT(2)
-#define MCHP_INT19_ESPI_LTR		BIT(3)
-#define MCHP_INT19_ESPI_OOB_TX		BIT(4)
-#define MCHP_INT19_ESPI_OOB_RX		BIT(5)
-#define MCHP_INT19_ESPI_FC		BIT(6)
-#define MCHP_INT19_ESPI_RESET		BIT(7)
-#define MCHP_INT19_ESPI_VW_EN		BIT(8)
+#define MCHP_INT19_ESPI_PC BIT(0)
+#define MCHP_INT19_ESPI_BM1 BIT(1)
+#define MCHP_INT19_ESPI_BM2 BIT(2)
+#define MCHP_INT19_ESPI_LTR BIT(3)
+#define MCHP_INT19_ESPI_OOB_TX BIT(4)
+#define MCHP_INT19_ESPI_OOB_RX BIT(5)
+#define MCHP_INT19_ESPI_FC BIT(6)
+#define MCHP_INT19_ESPI_RESET BIT(7)
+#define MCHP_INT19_ESPI_VW_EN BIT(8)
 
 /* GIRQ20 interrupt sources. Direct capable */
-#define MCHP_INT20_STAP_OBF		BIT(0)
-#define MCHP_INT20_STAP_IBF		BIT(1)
-#define MCHP_INT20_STAP_WAKE		BIT(2)
-#define MCHP_INT20_ISPI			BIT(8)
+#define MCHP_INT20_STAP_OBF BIT(0)
+#define MCHP_INT20_STAP_IBF BIT(1)
+#define MCHP_INT20_STAP_WAKE BIT(2)
+#define MCHP_INT20_ISPI BIT(8)
 
 /* GIRQ21 interrupt sources. Direct capable */
-#define MCHP_INT21_RTMR			BIT(0)
-#define MCHP_INT21_HTMR_0		BIT(1)
-#define MCHP_INT21_HTMR_1		BIT(2)
-#define MCHP_INT21_WEEK_ALARM		BIT(3)
-#define MCHP_INT21_WEEK_SUB		BIT(4)
-#define MCHP_INT21_WEEK_1SEC		BIT(5)
-#define MCHP_INT21_WEEK_1SEC_SUB	BIT(6)
-#define MCHP_INT21_WEEK_PWR_PRES	BIT(7)
-#define MCHP_INT21_RTC			BIT(8)
-#define MCHP_INT21_RTC_ALARM		BIT(9)
-#define MCHP_INT21_VCI_OVRD		BIT(10)
-#define MCHP_INT21_VCI_IN0		BIT(11)
-#define MCHP_INT21_VCI_IN1		BIT(12)
-#define MCHP_INT21_VCI_IN2		BIT(13)
-#define MCHP_INT21_VCI_IN3		BIT(14)
-#define MCHP_INT21_VCI_IN4		BIT(15)
-#define MCHP_INT21_VCI_IN5		BIT(16)
-#define MCHP_INT21_VCI_IN6		BIT(17)
-#define MCHP_INT21_PS2_0A_WAKE		BIT(18)
-#define MCHP_INT21_PS2_0B_WAKE		BIT(19)
-#define MCHP_INT21_PS2_1A_WAKE		BIT(20)
-#define MCHP_INT21_PS2_1B_WAKE		BIT(21)
-#define MCHP_INT21_PS2_2_WAKE		BIT(22)
-#define MCHP_INT21_ENVMON		BIT(24)
-#define MCHP_INT21_KEYSCAN		BIT(25)
+#define MCHP_INT21_RTMR BIT(0)
+#define MCHP_INT21_HTMR_0 BIT(1)
+#define MCHP_INT21_HTMR_1 BIT(2)
+#define MCHP_INT21_WEEK_ALARM BIT(3)
+#define MCHP_INT21_WEEK_SUB BIT(4)
+#define MCHP_INT21_WEEK_1SEC BIT(5)
+#define MCHP_INT21_WEEK_1SEC_SUB BIT(6)
+#define MCHP_INT21_WEEK_PWR_PRES BIT(7)
+#define MCHP_INT21_RTC BIT(8)
+#define MCHP_INT21_RTC_ALARM BIT(9)
+#define MCHP_INT21_VCI_OVRD BIT(10)
+#define MCHP_INT21_VCI_IN0 BIT(11)
+#define MCHP_INT21_VCI_IN1 BIT(12)
+#define MCHP_INT21_VCI_IN2 BIT(13)
+#define MCHP_INT21_VCI_IN3 BIT(14)
+#define MCHP_INT21_VCI_IN4 BIT(15)
+#define MCHP_INT21_VCI_IN5 BIT(16)
+#define MCHP_INT21_VCI_IN6 BIT(17)
+#define MCHP_INT21_PS2_0A_WAKE BIT(18)
+#define MCHP_INT21_PS2_0B_WAKE BIT(19)
+#define MCHP_INT21_PS2_1A_WAKE BIT(20)
+#define MCHP_INT21_PS2_1B_WAKE BIT(21)
+#define MCHP_INT21_PS2_2_WAKE BIT(22)
+#define MCHP_INT21_ENVMON BIT(24)
+#define MCHP_INT21_KEYSCAN BIT(25)
 
 /* GIRQ22 peripheral wake only. GIRQ22 not connected to NVIC */
-#define MCHP_INT22_WAKE_ONLY_LPC	BIT(0)
-#define MCHP_INT22_WAKE_ONLY_I2C0	BIT(1)
-#define MCHP_INT22_WAKE_ONLY_I2C1	BIT(2)
-#define MCHP_INT22_WAKE_ONLY_I2C2	BIT(3)
-#define MCHP_INT22_WAKE_ONLY_I2C3	BIT(4)
-#define MCHP_INT22_WAKE_ONLY_ESPI	BIT(9)
+#define MCHP_INT22_WAKE_ONLY_LPC BIT(0)
+#define MCHP_INT22_WAKE_ONLY_I2C0 BIT(1)
+#define MCHP_INT22_WAKE_ONLY_I2C1 BIT(2)
+#define MCHP_INT22_WAKE_ONLY_I2C2 BIT(3)
+#define MCHP_INT22_WAKE_ONLY_I2C3 BIT(4)
+#define MCHP_INT22_WAKE_ONLY_ESPI BIT(9)
 
 /* GIRQ23 sources. Direct capable */
-#define MCHP_INT23_BTMR16_0		BIT(0)
-#define MCHP_INT23_BTMR16_1		BIT(1)
-#define MCHP_INT23_BTMR16_2		BIT(2)
-#define MCHP_INT23_BTMR16_3		BIT(3)
-#define MCHP_INT23_BTMR32_0		BIT(4)
-#define MCHP_INT23_BTMR32_1		BIT(5)
-#define MCHP_INT23_CNT16_0		BIT(6)
-#define MCHP_INT23_CNT16_1		BIT(7)
-#define MCHP_INT23_CNT16_2		BIT(8)
-#define MCHP_INT23_CNT16_3		BIT(9)
-#define MCHP_INT23_CCT			BIT(10)
-#define MCHP_INT23_CCT_CAP0		BIT(11)
-#define MCHP_INT23_CCT_CAP1		BIT(12)
-#define MCHP_INT23_CCT_CAP2		BIT(13)
-#define MCHP_INT23_CCT_CAP3		BIT(14)
-#define MCHP_INT23_CCT_CAP4		BIT(15)
-#define MCHP_INT23_CCT_CAP6		BIT(16)
-#define MCHP_INT23_CCT_CMP0		BIT(17)
-#define MCHP_INT23_CCT_CMP1		BIT(18)
+#define MCHP_INT23_BTMR16_0 BIT(0)
+#define MCHP_INT23_BTMR16_1 BIT(1)
+#define MCHP_INT23_BTMR16_2 BIT(2)
+#define MCHP_INT23_BTMR16_3 BIT(3)
+#define MCHP_INT23_BTMR32_0 BIT(4)
+#define MCHP_INT23_BTMR32_1 BIT(5)
+#define MCHP_INT23_CNT16_0 BIT(6)
+#define MCHP_INT23_CNT16_1 BIT(7)
+#define MCHP_INT23_CNT16_2 BIT(8)
+#define MCHP_INT23_CNT16_3 BIT(9)
+#define MCHP_INT23_CCT BIT(10)
+#define MCHP_INT23_CCT_CAP0 BIT(11)
+#define MCHP_INT23_CCT_CAP1 BIT(12)
+#define MCHP_INT23_CCT_CAP2 BIT(13)
+#define MCHP_INT23_CCT_CAP3 BIT(14)
+#define MCHP_INT23_CCT_CAP4 BIT(15)
+#define MCHP_INT23_CCT_CAP6 BIT(16)
+#define MCHP_INT23_CCT_CMP0 BIT(17)
+#define MCHP_INT23_CCT_CMP1 BIT(18)
 
 /* GIRQ24 sources. Master-to-Slave v=[0:6], Source=[0:3] */
 #define MCHP_INT24_MSVW_SRC(v, s) (1ul << ((4 * (v)) + (s)))
@@ -721,19 +719,18 @@
 #define MCHP_INT25_MSVW_SRC(v, s) (1ul << ((4 * ((v)-7)) + (s)))
 
 /* UART Peripheral 0 <= x <= 1 */
-#define MCHP_UART_INSTANCES	2
-#define MCHP_UART_SPACING	0x400
-#define MCHP_UART_CFG_OFS	0x300
+#define MCHP_UART_INSTANCES 2
+#define MCHP_UART_SPACING 0x400
+#define MCHP_UART_CFG_OFS 0x300
 #define MCHP_UART_CONFIG_BASE(x) \
-	(MCHP_UART0_BASE + MCHP_UART_CFG_OFS + ((x) * MCHP_UART_SPACING))
-#define MCHP_UART_RUNTIME_BASE(x) \
-	(MCHP_UART0_BASE + ((x) * MCHP_UART_SPACING))
-#define MCHP_UART_GIRQ		15
-#define MCHP_UART0_GIRQ_BIT	(MCHP_INT15_UART_0)
-#define MCHP_UART1_GIRQ_BIT	(MCHP_INT15_UART_1)
-#define MCHP_UART_GIRQ_BIT(x)	BIT(x)
+	(MCHP_UART0_BASE + MCHP_UART_CFG_OFS + ((x)*MCHP_UART_SPACING))
+#define MCHP_UART_RUNTIME_BASE(x) (MCHP_UART0_BASE + ((x)*MCHP_UART_SPACING))
+#define MCHP_UART_GIRQ 15
+#define MCHP_UART0_GIRQ_BIT (MCHP_INT15_UART_0)
+#define MCHP_UART1_GIRQ_BIT (MCHP_INT15_UART_1)
+#define MCHP_UART_GIRQ_BIT(x) BIT(x)
 /* Bit defines for MCHP_UARTx_LSR */
-#define MCHP_LSR_TX_EMPTY	BIT(5)
+#define MCHP_LSR_TX_EMPTY BIT(5)
 
 /*
  * GPIO
@@ -764,284 +761,271 @@
  * Control 1 Address = 0x40081000 + (((4 << 5) + 0x1d) << 2) = 0x40081274
  *
  */
-#define MCHP_GPIO_CTL(port, id) REG32(MCHP_GPIO_BASE + \
-	(((port << 5) + id) << 2))
+#define MCHP_GPIO_CTL(port, id) \
+	REG32(MCHP_GPIO_BASE + (((port << 5) + id) << 2))
 
 /* MCHP implements 6 GPIO ports */
-#define MCHP_GPIO_MAX_PORT	6
-#define UNIMPLEMENTED_GPIO_BANK	MCHP_GPIO_MAX_PORT
+#define MCHP_GPIO_MAX_PORT 6
+#define UNIMPLEMENTED_GPIO_BANK MCHP_GPIO_MAX_PORT
 /*
  * In MECxxxx documentation GPIO numbers are octal, each control
  * register is located on a 32-bit boundary.
  */
-#define MCHP_GPIO_CTRL(gpio_num) REG32(MCHP_GPIO_BASE + \
-	((gpio_num) << 2))
+#define MCHP_GPIO_CTRL(gpio_num) REG32(MCHP_GPIO_BASE + ((gpio_num) << 2))
 
 /*
  * GPIO control register bit fields
  */
-#define MCHP_GPIO_CTRL_PUD_BITPOS	0
-#define MCHP_GPIO_CTRL_PUD_MASK0	0x03
-#define MCHP_GPIO_CTRL_PUD_MASK		0x03
-#define MCHP_GPIO_CTRL_PUD_NONE		0x00
-#define MCHP_GPIO_CTRL_PUD_PU		0x01
-#define MCHP_GPIO_CTRL_PUD_PD		0x02
-#define MCHP_GPIO_CTRL_PUD_KEEPER	0x03
-#define MCHP_GPIO_CTRL_PWR_BITPOS	2
-#define MCHP_GPIO_CTRL_PWR_MASK0	0x03
-#define MCHP_GPIO_CTRL_PWR_MASK		(0x03 << 2)
-#define MCHP_GPIO_CTRL_PWR_VTR		0
-#define MCHP_GPIO_CTRL_PWR_OFF		(0x02 << 2)
-#define MCHP_GPIO_INTDET_MASK		0xF0
-#define MCHP_GPIO_INTDET_LVL_LO		0x00
-#define MCHP_GPIO_INTDET_LVL_HI		0x10
-#define MCHP_GPIO_INTDET_DISABLED	0x40
-#define MCHP_GPIO_INTDET_EDGE_RIS	0xD0
-#define MCHP_GPIO_INTDET_EDGE_FALL	0xE0
-#define MCHP_GPIO_INTDET_EDGE_BOTH	0xF0
-#define MCHP_GPIO_INTDET_EDGE_EN	BIT(7)
-#define MCHP_GPIO_PUSH_PULL		0u
-#define MCHP_GPIO_OPEN_DRAIN		BIT(8)
-#define MCHP_GPIO_INPUT			0u
-#define MCHP_GPIO_OUTPUT		BIT(9)
-#define MCHP_GPIO_OUTSET_CTRL		0u
-#define MCHP_GPIO_OUTSEL_PAR		BIT(10)
-#define MCHP_GPIO_POLARITY_NINV		0u
-#define MCHP_GPIO_POLARITY_INV		BIT(11)
-#define MCHP_GPIO_CTRL_ALT_FUNC_BITPOS	12
-#define MCHP_GPIO_CTRL_ALT_FUNC_MASK0	0x0F
-#define MCHP_GPIO_CTRL_ALT_FUNC_MASK	(0x0F << 12)
-#define MCHP_GPIO_CTRL_FUNC_GPIO	(0 << 12)
-#define MCHP_GPIO_CTRL_FUNC_1		(1 << 12)
-#define MCHP_GPIO_CTRL_FUNC_2		(2 << 12)
-#define MCHP_GPIO_CTRL_FUNC_3		(3 << 12)
-#define MCHP_GPIO_CTRL_OUT_LVL		BIT(16)
+#define MCHP_GPIO_CTRL_PUD_BITPOS 0
+#define MCHP_GPIO_CTRL_PUD_MASK0 0x03
+#define MCHP_GPIO_CTRL_PUD_MASK 0x03
+#define MCHP_GPIO_CTRL_PUD_NONE 0x00
+#define MCHP_GPIO_CTRL_PUD_PU 0x01
+#define MCHP_GPIO_CTRL_PUD_PD 0x02
+#define MCHP_GPIO_CTRL_PUD_KEEPER 0x03
+#define MCHP_GPIO_CTRL_PWR_BITPOS 2
+#define MCHP_GPIO_CTRL_PWR_MASK0 0x03
+#define MCHP_GPIO_CTRL_PWR_MASK (0x03 << 2)
+#define MCHP_GPIO_CTRL_PWR_VTR 0
+#define MCHP_GPIO_CTRL_PWR_OFF (0x02 << 2)
+#define MCHP_GPIO_INTDET_MASK 0xF0
+#define MCHP_GPIO_INTDET_LVL_LO 0x00
+#define MCHP_GPIO_INTDET_LVL_HI 0x10
+#define MCHP_GPIO_INTDET_DISABLED 0x40
+#define MCHP_GPIO_INTDET_EDGE_RIS 0xD0
+#define MCHP_GPIO_INTDET_EDGE_FALL 0xE0
+#define MCHP_GPIO_INTDET_EDGE_BOTH 0xF0
+#define MCHP_GPIO_INTDET_EDGE_EN BIT(7)
+#define MCHP_GPIO_PUSH_PULL 0u
+#define MCHP_GPIO_OPEN_DRAIN BIT(8)
+#define MCHP_GPIO_INPUT 0u
+#define MCHP_GPIO_OUTPUT BIT(9)
+#define MCHP_GPIO_OUTSET_CTRL 0u
+#define MCHP_GPIO_OUTSEL_PAR BIT(10)
+#define MCHP_GPIO_POLARITY_NINV 0u
+#define MCHP_GPIO_POLARITY_INV BIT(11)
+#define MCHP_GPIO_CTRL_ALT_FUNC_BITPOS 12
+#define MCHP_GPIO_CTRL_ALT_FUNC_MASK0 0x0F
+#define MCHP_GPIO_CTRL_ALT_FUNC_MASK (0x0F << 12)
+#define MCHP_GPIO_CTRL_FUNC_GPIO (0 << 12)
+#define MCHP_GPIO_CTRL_FUNC_1 (1 << 12)
+#define MCHP_GPIO_CTRL_FUNC_2 (2 << 12)
+#define MCHP_GPIO_CTRL_FUNC_3 (3 << 12)
+#define MCHP_GPIO_CTRL_OUT_LVL BIT(16)
 /* MEC170x reserved read-only 0 bit. Value set to 0 */
-#define MCHP_GPIO_CTRL_DIS_INPUT_BITPOS	15
-#define MCHP_GPIO_CTRL_DIS_INPUT_BIT	0
+#define MCHP_GPIO_CTRL_DIS_INPUT_BITPOS 15
+#define MCHP_GPIO_CTRL_DIS_INPUT_BIT 0
 
 /*
  * GPIO Parallel Input and Output registers.
  * gpio_bank in [0, 5]
  */
-#define MCHP_GPIO_PARIN(bank)	\
-	REG32(MCHP_GPIO_BASE + 0x0300 + ((bank) << 2))
-#define MCHP_GPIO_PAROUT(bank)	\
-	REG32(MCHP_GPIO_BASE + 0x0380 + ((bank) << 2))
+#define MCHP_GPIO_PARIN(bank) REG32(MCHP_GPIO_BASE + 0x0300 + ((bank) << 2))
+#define MCHP_GPIO_PAROUT(bank) REG32(MCHP_GPIO_BASE + 0x0380 + ((bank) << 2))
 
 /* Basic timers */
-#define MCHP_TMR_SPACING	0x20
-#define MCHP_TMR16_INSTANCES	4
-#define MCHP_TMR32_INSTANCES	2
-#define MCHP_TMR16_MAX		(MCHP_TMR16_INSTANCES)
-#define MCHP_TMR32_MAX		(MCHP_TMR32_INSTANCES)
-#define MCHP_TMR16_BASE(n)	(MCHP_TMR16_0_BASE + (n) * MCHP_TMR_SPACING)
-#define MCHP_TMR32_BASE(n)	(MCHP_TMR32_0_BASE + (n) * MCHP_TMR_SPACING)
-#define MCHP_TMR16_GIRQ		23
-#define MCHP_TMR16_GIRQ_BIT(n)	BIT(0 + (n))
-#define MCHP_TMR32_GIRQ		23
-#define MCHP_TMR32_GIRQ_BIT(n)	BIT(4 + (n))
+#define MCHP_TMR_SPACING 0x20
+#define MCHP_TMR16_INSTANCES 4
+#define MCHP_TMR32_INSTANCES 2
+#define MCHP_TMR16_MAX (MCHP_TMR16_INSTANCES)
+#define MCHP_TMR32_MAX (MCHP_TMR32_INSTANCES)
+#define MCHP_TMR16_BASE(n) (MCHP_TMR16_0_BASE + (n)*MCHP_TMR_SPACING)
+#define MCHP_TMR32_BASE(n) (MCHP_TMR32_0_BASE + (n)*MCHP_TMR_SPACING)
+#define MCHP_TMR16_GIRQ 23
+#define MCHP_TMR16_GIRQ_BIT(n) BIT(0 + (n))
+#define MCHP_TMR32_GIRQ 23
+#define MCHP_TMR32_GIRQ_BIT(n) BIT(4 + (n))
 
 /* 16-bit Counter/timer */
-#define MCHP_CNT16_SPACING	0x20
-#define MCHP_CNT16_INSTANCES	4
-#define MCHP_CNT16_BASE(n)	\
-	(MCHP_CNT16_0_BASE + (n) * MCHP_CNT16_SPACING)
-#define MCHP_CNT16_GIRQ		23
-#define MCHP_CNT16_GIRQ_BIT(x)	BIT(6 + (x))
+#define MCHP_CNT16_SPACING 0x20
+#define MCHP_CNT16_INSTANCES 4
+#define MCHP_CNT16_BASE(n) (MCHP_CNT16_0_BASE + (n)*MCHP_CNT16_SPACING)
+#define MCHP_CNT16_GIRQ 23
+#define MCHP_CNT16_GIRQ_BIT(x) BIT(6 + (x))
 
 /* RTimer */
-#define MCHP_RTMR_GIRQ		21
-#define MCHP_RTMR_GIRQ_BIT(x)	MCHP_INT21_RTMR
+#define MCHP_RTMR_GIRQ 21
+#define MCHP_RTMR_GIRQ_BIT(x) MCHP_INT21_RTMR
 
 /* VBAT */
-#define MCHP_VBAT_STS			REG32(MCHP_VBAT_BASE + 0x0)
-#define MCHP_VBAT_CE			REG32(MCHP_VBAT_BASE + 0x8)
-#define MCHP_VBAT_SHDN_DIS		REG32(MCHP_VBAT_BASE + 0xC)
-#define MCHP_VBAT_MONOTONIC_CTR_LO	REG32(MCHP_VBAT_BASE + 0x20)
-#define MCHP_VBAT_MONOTONIC_CTR_HI	REG32(MCHP_VBAT_BASE + 0x24)
+#define MCHP_VBAT_STS REG32(MCHP_VBAT_BASE + 0x0)
+#define MCHP_VBAT_CE REG32(MCHP_VBAT_BASE + 0x8)
+#define MCHP_VBAT_SHDN_DIS REG32(MCHP_VBAT_BASE + 0xC)
+#define MCHP_VBAT_MONOTONIC_CTR_LO REG32(MCHP_VBAT_BASE + 0x20)
+#define MCHP_VBAT_MONOTONIC_CTR_HI REG32(MCHP_VBAT_BASE + 0x24)
 /* read 32-bit word at 32-bit offset x where 0 <= x <= 32 */
-#define MCHP_VBAT_RAM_SIZE		128
-#define MCHP_VBAT_RAM(wnum)		\
-	REG32(MCHP_VBAT_RAM_BASE + ((wnum) * 4))
-#define MCHP_VBAT_RAM8(bnum)		\
-	REG8(MCHP_VBAT_RAM_BASE + (bnum))
-#define MCHP_VBAT_VWIRE_BACKUP		30
+#define MCHP_VBAT_RAM_SIZE 128
+#define MCHP_VBAT_RAM(wnum) REG32(MCHP_VBAT_RAM_BASE + ((wnum)*4))
+#define MCHP_VBAT_RAM8(bnum) REG8(MCHP_VBAT_RAM_BASE + (bnum))
+#define MCHP_VBAT_VWIRE_BACKUP 30
 /*
  * Miscellaneous firmware control fields
  * scratch pad index cannot be more than 32 as
  * MEC152x has 64 bytes = 16 words of scratch RAM
  */
-#define MCHP_IMAGETYPE_IDX	31
+#define MCHP_IMAGETYPE_IDX 31
 
 /* Bit definition for MCHP_VBAT_STS */
-#define MCHP_VBAT_STS_SOFTRESET		BIT(2)
-#define MCHP_VBAT_STS_RESETI		BIT(4)
-#define MCHP_VBAT_STS_WDT		BIT(5)
-#define MCHP_VBAT_STS_SYSRESETREQ	BIT(6)
-#define MCHP_VBAT_STS_VBAT_RST		BIT(7)
-#define MCHP_VBAT_STS_ANY_RST		0xF4u
+#define MCHP_VBAT_STS_SOFTRESET BIT(2)
+#define MCHP_VBAT_STS_RESETI BIT(4)
+#define MCHP_VBAT_STS_WDT BIT(5)
+#define MCHP_VBAT_STS_SYSRESETREQ BIT(6)
+#define MCHP_VBAT_STS_VBAT_RST BIT(7)
+#define MCHP_VBAT_STS_ANY_RST 0xF4u
 
 /* Bit definitions for MCHP_VBAT_CE */
-#define MCHP_VBAT_CE_XOSEL_BITPOS	3
-#define MCHP_VBAT_CE_XOSEL_MASK		BIT(3)
-#define MCHP_VBAT_CE_XOSEL_PAR		0
-#define MCHP_VBAT_CE_XOSEL_SE		BIT(3)
+#define MCHP_VBAT_CE_XOSEL_BITPOS 3
+#define MCHP_VBAT_CE_XOSEL_MASK BIT(3)
+#define MCHP_VBAT_CE_XOSEL_PAR 0
+#define MCHP_VBAT_CE_XOSEL_SE BIT(3)
 
-#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_BITPOS	2
-#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_MASK	BIT(2)
-#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_INT	0
-#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_CRYSTAL	BIT(2)
+#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_BITPOS 2
+#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_MASK BIT(2)
+#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_INT 0
+#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_CRYSTAL BIT(2)
 
-#define MCHP_VBAT_CE_32K_DOMAIN_SRC_BITPOS	1
-#define MCHP_VBAT_CE_32K_DOMAIN_SRC_MASK	BIT(1)
-#define MCHP_VBAT_CE_32K_DOMAIN_ALWAYS_ON	0
-#define MCHP_VBAT_CE_32K_DOMAIN_32KHZ_IN_PIN	BIT(1)
+#define MCHP_VBAT_CE_32K_DOMAIN_SRC_BITPOS 1
+#define MCHP_VBAT_CE_32K_DOMAIN_SRC_MASK BIT(1)
+#define MCHP_VBAT_CE_32K_DOMAIN_ALWAYS_ON 0
+#define MCHP_VBAT_CE_32K_DOMAIN_32KHZ_IN_PIN BIT(1)
 
 /* Blinking-Breathing LED 0 <= n <= 2 */
-#define MCHP_BBLEB_INSTANCES	4
-#define MCHP_BBLED_BASE(n)	(MCHP_BBLED_0_BASE + (((n) & 0x03) * 256))
+#define MCHP_BBLEB_INSTANCES 4
+#define MCHP_BBLED_BASE(n) (MCHP_BBLED_0_BASE + (((n)&0x03) * 256))
 
 /* EMI */
-#define MCHP_EMI_INSTANCES	3
-#define MCHP_EMI_SPACING	0x400
-#define MCHP_EMI_ECREG_OFS	0x100
+#define MCHP_EMI_INSTANCES 3
+#define MCHP_EMI_SPACING 0x400
+#define MCHP_EMI_ECREG_OFS 0x100
 /* base of EMI registers only accessible by EC */
 #define MCHP_EMI_BASE(n) \
-	(MCHP_EMI_0_BASE + MCHP_EMI_ECREG_OFS + ((n) * MCHP_EMI_SPACING))
+	(MCHP_EMI_0_BASE + MCHP_EMI_ECREG_OFS + ((n)*MCHP_EMI_SPACING))
 /* base of EMI registers accessible by EC and Host */
-#define MCHP_EMI_RT_BASE(n) (MCHP_EMI_0_BASE + ((n) * MCHP_EMI_SPACING))
-#define MCHP_EMI_GIRQ		15
-#define MCHP_EMI_GIRQ_BIT(n)	BIT(2 + (n))
+#define MCHP_EMI_RT_BASE(n) (MCHP_EMI_0_BASE + ((n)*MCHP_EMI_SPACING))
+#define MCHP_EMI_GIRQ 15
+#define MCHP_EMI_GIRQ_BIT(n) BIT(2 + (n))
 
 /* Mailbox */
-#define MCHP_MBX_ECREGS_OFS	0x100
-#define MCHP_MBX_RT_BASE	MCHP_MBOX_BASE
-#define MCHP_MBX_BASE		(MCHP_MBOX_BASE + MCHP_MBX_ECREGS_OFS)
-#define MCHP_MBX_GIRQ		15
-#define MCHP_MBX_GIRQ_BIT	BIT(20)
+#define MCHP_MBX_ECREGS_OFS 0x100
+#define MCHP_MBX_RT_BASE MCHP_MBOX_BASE
+#define MCHP_MBX_BASE (MCHP_MBOX_BASE + MCHP_MBX_ECREGS_OFS)
+#define MCHP_MBX_GIRQ 15
+#define MCHP_MBX_GIRQ_BIT BIT(20)
 
 /* Port 80 Capture */
-#define MCHP_P80_SPACING	0x400
+#define MCHP_P80_SPACING 0x400
 #define MCHP_P80_BASE(n) (MCHP_P80CAP0_BASE + ((n) * (MCHP_P80_SPACING)))
 #define MCHP_P80_HOST_DATA(n) REG8(MCHP_P80_BASE(n))
 /* Data capture with time stamp register */
-#define MCHP_P80_CAP(n)		REG32(MCHP_P80_BASE(n) + 0x100)
-#define MCHP_P80_CFG(n)		REG8(MCHP_P80_BASE(n) + 0x104)
-#define MCHP_P80_STS(n)		REG8(MCHP_P80_BASE(n) + 0x108)
-#define MCHP_P80_CNT(n)		REG32(MCHP_P80_BASE(n) + 0x10c)
-#define MCHP_P80_CNT_GET(n)	(REG32(MCHP_P80_BASE(n) + 0x10c) >> 8)
-#define MCHP_P80_CNT_SET(n, c)	\
-	(REG32(MCHP_P80_BASE(n) + 0x10c) = ((c) << 8))
-#define MCHP_P80_ACTIVATE(n)	REG8(MCHP_P80_BASE(n) + 0x330)
-#define MCHP_P80_GIRQ		15
-#define MCHP_P80_GIRQ_BIT(n)	BIT(22 + (n))
+#define MCHP_P80_CAP(n) REG32(MCHP_P80_BASE(n) + 0x100)
+#define MCHP_P80_CFG(n) REG8(MCHP_P80_BASE(n) + 0x104)
+#define MCHP_P80_STS(n) REG8(MCHP_P80_BASE(n) + 0x108)
+#define MCHP_P80_CNT(n) REG32(MCHP_P80_BASE(n) + 0x10c)
+#define MCHP_P80_CNT_GET(n) (REG32(MCHP_P80_BASE(n) + 0x10c) >> 8)
+#define MCHP_P80_CNT_SET(n, c) (REG32(MCHP_P80_BASE(n) + 0x10c) = ((c) << 8))
+#define MCHP_P80_ACTIVATE(n) REG8(MCHP_P80_BASE(n) + 0x330)
+#define MCHP_P80_GIRQ 15
+#define MCHP_P80_GIRQ_BIT(n) BIT(22 + (n))
 /*
  * Port 80 Data register bits
  * bits[7:0] = data captured on Host write
  * bits[31:8] = optional time stamp
  */
-#define MCHP_P80_CAP_DATA_MASK		0xFFul
-#define MCHP_P80_CAP_TS_BITPOS		8
-#define MCHP_P80_CAP_TS_MASK0		0xfffffful
-#define MCHP_P80_CAP_TS_MASK		\
+#define MCHP_P80_CAP_DATA_MASK 0xFFul
+#define MCHP_P80_CAP_TS_BITPOS 8
+#define MCHP_P80_CAP_TS_MASK0 0xfffffful
+#define MCHP_P80_CAP_TS_MASK \
 	((MCHP_P80_CAP_TS_MASK0) << (MCHP_P80_CAP_TS_BITPOS))
 
 /* Port 80 Configuration register bits */
-#define MCHP_P80_FLUSH_FIFO_WO		BIT(1)
-#define MCHP_P80_RESET_TIMESTAMP_WO	BIT(2)
-#define MCHP_P80_TIMEBASE_BITPOS	3
-#define MCHP_P80_TIMEBASE_MASK0		0x03
-#define MCHP_P80_TIMEBASE_MASK		\
+#define MCHP_P80_FLUSH_FIFO_WO BIT(1)
+#define MCHP_P80_RESET_TIMESTAMP_WO BIT(2)
+#define MCHP_P80_TIMEBASE_BITPOS 3
+#define MCHP_P80_TIMEBASE_MASK0 0x03
+#define MCHP_P80_TIMEBASE_MASK \
 	((MCHP_P80_TIMEBASE_MASK0) << (MCHP_P80_TIMEBASE_BITPOS))
-#define MCHP_P80_TIMEBASE_750KHZ	\
-	(0x03 << (MCHP_P80_TIMEBASE_BITPOS))
-#define MCHP_P80_TIMEBASE_1500KHZ	\
-	(0x02 << (MCHP_P80_TIMEBASE_BITPOS))
-#define MCHP_P80_TIMEBASE_3MHZ		\
-	(0x01 << (MCHP_P80_TIMEBASE_BITPOS))
-#define MCHP_P80_TIMEBASE_6MHZ		\
-	(0x00 << (MCHP_P80_TIMEBASE_BITPOS))
-#define MCHP_P80_TIMER_ENABLE		BIT(5)
-#define MCHP_P80_FIFO_THRHOLD_MASK	(3u << 6)
-#define MCHP_P80_FIFO_THRHOLD_1		0u
-#define MCHP_P80_FIFO_THRHOLD_4		(1u << 6)
-#define MCHP_P80_FIFO_THRHOLD_8		(2u << 6)
-#define MCHP_P80_FIFO_THRHOLD_14	(3u << 6)
-#define MCHP_P80_FIFO_LEN		16
+#define MCHP_P80_TIMEBASE_750KHZ (0x03 << (MCHP_P80_TIMEBASE_BITPOS))
+#define MCHP_P80_TIMEBASE_1500KHZ (0x02 << (MCHP_P80_TIMEBASE_BITPOS))
+#define MCHP_P80_TIMEBASE_3MHZ (0x01 << (MCHP_P80_TIMEBASE_BITPOS))
+#define MCHP_P80_TIMEBASE_6MHZ (0x00 << (MCHP_P80_TIMEBASE_BITPOS))
+#define MCHP_P80_TIMER_ENABLE BIT(5)
+#define MCHP_P80_FIFO_THRHOLD_MASK (3u << 6)
+#define MCHP_P80_FIFO_THRHOLD_1 0u
+#define MCHP_P80_FIFO_THRHOLD_4 (1u << 6)
+#define MCHP_P80_FIFO_THRHOLD_8 (2u << 6)
+#define MCHP_P80_FIFO_THRHOLD_14 (3u << 6)
+#define MCHP_P80_FIFO_LEN 16
 /* Port 80 Status register bits, read-only */
-#define MCHP_P80_STS_NOT_EMPTY		BIT(0)
-#define MCHP_P80_STS_OVERRUN		BIT(1)
+#define MCHP_P80_STS_NOT_EMPTY BIT(0)
+#define MCHP_P80_STS_OVERRUN BIT(1)
 /* Port 80 Count register bits */
-#define MCHP_P80_CNT_BITPOS		8
-#define MCHP_P80_CNT_MASK0		0xfffffful
+#define MCHP_P80_CNT_BITPOS 8
+#define MCHP_P80_CNT_MASK0 0xfffffful
 #define MCHP_P80_CNT_MASK ((MCHP_P80_CNT_MASK0) << (MCHP_P80_CNT_BITPOS))
 
 /* PWM SZ 144 pin package has 9 PWM's */
-#define MCHP_PWM_INSTANCES		9
-#define MCHP_PWM_ID_MAX			(MCHP_PWM_INSTANCES)
-#define MCHP_PWM_SPACING		16
-#define MCHP_PWM_BASE(x) (MCHP_PWM_0_BASE + ((x) * MCHP_PWM_SPACING))
+#define MCHP_PWM_INSTANCES 9
+#define MCHP_PWM_ID_MAX (MCHP_PWM_INSTANCES)
+#define MCHP_PWM_SPACING 16
+#define MCHP_PWM_BASE(x) (MCHP_PWM_0_BASE + ((x)*MCHP_PWM_SPACING))
 
 /* TACH */
-#define MCHP_TACH_INSTANCES	3
-#define MCHP_TACH_SPACING	16
-#define MCHP_TACH_BASE(x) (MCHP_TACH_0_BASE + ((x) * MCHP_TACH_SPACING))
-#define MCHP_TACH_GIRQ		17
-#define MCHP_TACH_GIRQ_BIT(x)	BIT(1 + (x))
+#define MCHP_TACH_INSTANCES 3
+#define MCHP_TACH_SPACING 16
+#define MCHP_TACH_BASE(x) (MCHP_TACH_0_BASE + ((x)*MCHP_TACH_SPACING))
+#define MCHP_TACH_GIRQ 17
+#define MCHP_TACH_GIRQ_BIT(x) BIT(1 + (x))
 
 /* FAN */
-#define MCHP_FAN_INSTANCES	2
-#define MCHP_FAN_SPACING	0x80U
-#define MCHP_FAN_BASE(x)	\
-	(MCHP_RPM2PWM0_BASE + ((x) * MCHP_FAN_SPACING))
-#define MCHP_FAN_SETTING(x)	REG16(MCHP_FAN_BASE(x) + 0x0)
-#define MCHP_FAN_CFG1(x)	REG8(MCHP_FAN_BASE(x) + 0x2)
-#define MCHP_FAN_CFG2(x)	REG8(MCHP_FAN_BASE(x) + 0x3)
-#define MCHP_FAN_PWM_DIVIDE(x)	REG8(MCHP_FAN_BASE(x) + 0x4)
-#define MCHP_FAN_GAIN(x)	REG8(MCHP_FAN_BASE(x) + 0x5)
-#define MCHP_FAN_SPIN_UP(x)	REG8(MCHP_FAN_BASE(x) + 0x6)
-#define MCHP_FAN_STEP(x)	REG8(MCHP_FAN_BASE(x) + 0x7)
-#define MCHP_FAN_MIN_DRV(x)	REG8(MCHP_FAN_BASE(x) + 0x8)
-#define MCHP_FAN_VALID_CNT(x)	REG8(MCHP_FAN_BASE(x) + 0x9)
-#define MCHP_FAN_DRV_FAIL(x)	REG16(MCHP_FAN_BASE(x) + 0xa)
-#define MCHP_FAN_TARGET(x)	REG16(MCHP_FAN_BASE(x) + 0xc)
-#define MCHP_FAN_READING(x)	REG16(MCHP_FAN_BASE(x) + 0xe)
-#define MCHP_FAN_BASE_FREQ(x)	REG8(MCHP_FAN_BASE(x) + 0x10)
-#define MCHP_FAN_STATUS(x)	REG8(MCHP_FAN_BASE(x) + 0x11)
+#define MCHP_FAN_INSTANCES 2
+#define MCHP_FAN_SPACING 0x80U
+#define MCHP_FAN_BASE(x) (MCHP_RPM2PWM0_BASE + ((x)*MCHP_FAN_SPACING))
+#define MCHP_FAN_SETTING(x) REG16(MCHP_FAN_BASE(x) + 0x0)
+#define MCHP_FAN_CFG1(x) REG8(MCHP_FAN_BASE(x) + 0x2)
+#define MCHP_FAN_CFG2(x) REG8(MCHP_FAN_BASE(x) + 0x3)
+#define MCHP_FAN_PWM_DIVIDE(x) REG8(MCHP_FAN_BASE(x) + 0x4)
+#define MCHP_FAN_GAIN(x) REG8(MCHP_FAN_BASE(x) + 0x5)
+#define MCHP_FAN_SPIN_UP(x) REG8(MCHP_FAN_BASE(x) + 0x6)
+#define MCHP_FAN_STEP(x) REG8(MCHP_FAN_BASE(x) + 0x7)
+#define MCHP_FAN_MIN_DRV(x) REG8(MCHP_FAN_BASE(x) + 0x8)
+#define MCHP_FAN_VALID_CNT(x) REG8(MCHP_FAN_BASE(x) + 0x9)
+#define MCHP_FAN_DRV_FAIL(x) REG16(MCHP_FAN_BASE(x) + 0xa)
+#define MCHP_FAN_TARGET(x) REG16(MCHP_FAN_BASE(x) + 0xc)
+#define MCHP_FAN_READING(x) REG16(MCHP_FAN_BASE(x) + 0xe)
+#define MCHP_FAN_BASE_FREQ(x) REG8(MCHP_FAN_BASE(x) + 0x10)
+#define MCHP_FAN_STATUS(x) REG8(MCHP_FAN_BASE(x) + 0x11)
 
 /* ACPI EC */
-#define MCHP_ACPI_EC_INSTANCES		5
-#define MCHP_ACPI_EC_MAX		(MCHP_ACPI_EC_INSTANCES)
-#define MCHP_ACPI_EC_SPACING		0x400
-#define MCHP_ACPI_EC_BASE(x) \
-	(MCHP_ACPI_EC_0_BASE + ((x) * MCHP_ACPI_EC_SPACING))
-#define MCHP_ACPI_EC_GIRQ		15
-#define MCHP_ACPI_EC_IBF_GIRQ_BIT(x)	BIT(5 + ((x) * 2))
-#define MCHP_ACPI_EC_OBE_GIRQ_BIT(x)	BIT(6 + ((x) * 2))
+#define MCHP_ACPI_EC_INSTANCES 5
+#define MCHP_ACPI_EC_MAX (MCHP_ACPI_EC_INSTANCES)
+#define MCHP_ACPI_EC_SPACING 0x400
+#define MCHP_ACPI_EC_BASE(x) (MCHP_ACPI_EC_0_BASE + ((x)*MCHP_ACPI_EC_SPACING))
+#define MCHP_ACPI_EC_GIRQ 15
+#define MCHP_ACPI_EC_IBF_GIRQ_BIT(x) BIT(5 + ((x)*2))
+#define MCHP_ACPI_EC_OBE_GIRQ_BIT(x) BIT(6 + ((x)*2))
 
 /* ACPI PM1 */
-#define MCHP_ACPI_PM1_ECREGS_OFS	0x100
-#define MCHP_ACPI_PM_RT_BASE		MCHP_ACPI_PM1_BASE
-#define MCHP_ACPI_PM_EC_BASE	(MCHP_ACPI_PM1_BASE + MCHP_ACPI_PM1_ECREGS_OFS)
-#define MCHP_ACPI_PM1_CTL_GIRQ_BIT	BIT(15)
-#define MCHP_ACPI_PM1_EN_GIRQ_BIT	BIT(16)
-#define MCHP_ACPI_PM1_STS_GIRQ_BIT	BIT(17)
+#define MCHP_ACPI_PM1_ECREGS_OFS 0x100
+#define MCHP_ACPI_PM_RT_BASE MCHP_ACPI_PM1_BASE
+#define MCHP_ACPI_PM_EC_BASE (MCHP_ACPI_PM1_BASE + MCHP_ACPI_PM1_ECREGS_OFS)
+#define MCHP_ACPI_PM1_CTL_GIRQ_BIT BIT(15)
+#define MCHP_ACPI_PM1_EN_GIRQ_BIT BIT(16)
+#define MCHP_ACPI_PM1_STS_GIRQ_BIT BIT(17)
 
 /* 8042 */
-#define MCHP_8042_ECREGS_OFS		0x100
-#define MCHP_8042_GIRQ			15
-#define MCHP_8042_OBE_GIRQ_BIT		BIT(18)
-#define MCHP_8042_IBF_GIRQ_BIT		BIT(19)
+#define MCHP_8042_ECREGS_OFS 0x100
+#define MCHP_8042_GIRQ 15
+#define MCHP_8042_OBE_GIRQ_BIT BIT(18)
+#define MCHP_8042_IBF_GIRQ_BIT BIT(19)
 
 /* I2C controllers 0 - 4 include SMBus network layer functionality. */
-#define MCHP_I2C_CTRL0		0
-#define MCHP_I2C_CTRL1		1
-#define MCHP_I2C_CTRL2		2
-#define MCHP_I2C_CTRL3		3
-#define MCHP_I2C_CTRL_MAX	4
+#define MCHP_I2C_CTRL0 0
+#define MCHP_I2C_CTRL1 1
+#define MCHP_I2C_CTRL2 2
+#define MCHP_I2C_CTRL3 3
+#define MCHP_I2C_CTRL_MAX 4
 
-#define MCHP_I2C_SEP0		0x400
+#define MCHP_I2C_SEP0 0x400
 
 /*
  * MEC1701H 144-pin package has four I2C controllers and eleven ports.
@@ -1059,7 +1043,7 @@
 #define MCHP_I2C_PORT_MASK 0x07FDul
 enum MCHP_i2c_port {
 	MCHP_I2C_PORT0 = 0,
-	MCHP_I2C_PORT1,	/* port 1, do not use. pins not present */
+	MCHP_I2C_PORT1, /* port 1, do not use. pins not present */
 	MCHP_I2C_PORT2,
 	MCHP_I2C_PORT3,
 	MCHP_I2C_PORT4,
@@ -1073,184 +1057,184 @@ enum MCHP_i2c_port {
 };
 
 /* All I2C controllers connected to GIRQ13 */
-#define MCHP_I2C_GIRQ		13
+#define MCHP_I2C_GIRQ 13
 /* I2C[0:7] -> GIRQ13 bits[0:7] */
-#define MCHP_I2C_GIRQ_BIT(n)	BIT((n))
+#define MCHP_I2C_GIRQ_BIT(n) BIT((n))
 
 /* Keyboard scan matrix */
-#define MCHP_KS_GIRQ		21
-#define MCHP_KS_GIRQ_BIT	BIT(25)
-#define MCHP_KS_DIRECT_NVIC	135
+#define MCHP_KS_GIRQ 21
+#define MCHP_KS_GIRQ_BIT BIT(25)
+#define MCHP_KS_DIRECT_NVIC 135
 
 /* ADC */
-#define MCHP_ADC_GIRQ			17
-#define MCHP_ADC_GIRQ_SINGLE_BIT	BIT(8)
-#define MCHP_ADC_GIRQ_REPEAT_BIT	BIT(9)
-#define MCHP_ADC_SINGLE_DIRECT_NVIC	78
-#define MCHP_ADC_REPEAT_DIRECT_NVIC	79
+#define MCHP_ADC_GIRQ 17
+#define MCHP_ADC_GIRQ_SINGLE_BIT BIT(8)
+#define MCHP_ADC_GIRQ_REPEAT_BIT BIT(9)
+#define MCHP_ADC_SINGLE_DIRECT_NVIC 78
+#define MCHP_ADC_REPEAT_DIRECT_NVIC 79
 
 /* Hibernation timer */
-#define MCHP_HTIMER_SPACING		0x20
-#define MCHP_HTIMER_ADDR(n) (MCHP_HTIMER_BASE + ((n) * MCHP_HTIMER_SPACING))
-#define MCHP_HTIMER_GIRQ		21
+#define MCHP_HTIMER_SPACING 0x20
+#define MCHP_HTIMER_ADDR(n) (MCHP_HTIMER_BASE + ((n)*MCHP_HTIMER_SPACING))
+#define MCHP_HTIMER_GIRQ 21
 /* HTIMER[0:1] -> GIRQ21 bits[1:2] */
-#define MCHP_HTIMER_GIRQ_BIT(n)		BIT(1 + (n))
-#define MCHP_HTIMER_DIRECT_NVIC(n)	(112 + (n))
+#define MCHP_HTIMER_GIRQ_BIT(n) BIT(1 + (n))
+#define MCHP_HTIMER_DIRECT_NVIC(n) (112 + (n))
 
 /* General Purpose SPI (GP-SPI) */
-#define MCHP_SPI_BASE(port) (MCHP_GPSPI0_BASE + ((port) * 0x80))
-#define MCHP_SPI_AR(port)	REG8(MCHP_SPI_BASE(port) + 0x00)
-#define MCHP_SPI_CR(port)	REG8(MCHP_SPI_BASE(port) + 0x04)
-#define MCHP_SPI_SR(port)	REG8(MCHP_SPI_BASE(port) + 0x08)
-#define MCHP_SPI_TD(port)	REG8(MCHP_SPI_BASE(port) + 0x0c)
-#define MCHP_SPI_RD(port)	REG8(MCHP_SPI_BASE(port) + 0x10)
-#define MCHP_SPI_CC(port)	REG8(MCHP_SPI_BASE(port) + 0x14)
-#define MCHP_SPI_CG(port)	REG8(MCHP_SPI_BASE(port) + 0x18)
+#define MCHP_SPI_BASE(port) (MCHP_GPSPI0_BASE + ((port)*0x80))
+#define MCHP_SPI_AR(port) REG8(MCHP_SPI_BASE(port) + 0x00)
+#define MCHP_SPI_CR(port) REG8(MCHP_SPI_BASE(port) + 0x04)
+#define MCHP_SPI_SR(port) REG8(MCHP_SPI_BASE(port) + 0x08)
+#define MCHP_SPI_TD(port) REG8(MCHP_SPI_BASE(port) + 0x0c)
+#define MCHP_SPI_RD(port) REG8(MCHP_SPI_BASE(port) + 0x10)
+#define MCHP_SPI_CC(port) REG8(MCHP_SPI_BASE(port) + 0x14)
+#define MCHP_SPI_CG(port) REG8(MCHP_SPI_BASE(port) + 0x18)
 /* Addresses of TX/RX register used in tables */
-#define MCHP_SPI_TD_ADDR(ctrl)	(MCHP_SPI_BASE(ctrl) + 0x0c)
-#define MCHP_SPI_RD_ADDR(ctrl)	(MCHP_SPI_BASE(ctrl) + 0x10)
+#define MCHP_SPI_TD_ADDR(ctrl) (MCHP_SPI_BASE(ctrl) + 0x0c)
+#define MCHP_SPI_RD_ADDR(ctrl) (MCHP_SPI_BASE(ctrl) + 0x10)
 /* All GP-SPI controllers connected to GIRQ18 */
-#define MCHP_SPI_GIRQ			18
-#define MCHP_SPI_GIRQ_TXBE_BIT(x)	BIT(2 + ((x) * 2))
-#define MCHP_SPI_GIRQ_RXBF_BIT(x)	BIT(3 + ((x) * 2))
-#define MCHP_GPSPI0_ID			0
-#define MCHP_GPSPI1_ID			1
+#define MCHP_SPI_GIRQ 18
+#define MCHP_SPI_GIRQ_TXBE_BIT(x) BIT(2 + ((x)*2))
+#define MCHP_SPI_GIRQ_RXBF_BIT(x) BIT(3 + ((x)*2))
+#define MCHP_GPSPI0_ID 0
+#define MCHP_GPSPI1_ID 1
 
 /*
  * Quad Master SPI (QMSPI)
  * MEC1701 implements 5 descriptors and a single chip select.
  */
-#define MCHP_QMSPI_MAX_DESCR	5
-#define MCHP_QMSPI_GIRQ		18
-#define MCHP_QMSPI_GIRQ_BIT	BIT(1)
-#define MCHP_QMSPI_DIRECT_NVIC	91
+#define MCHP_QMSPI_MAX_DESCR 5
+#define MCHP_QMSPI_GIRQ 18
+#define MCHP_QMSPI_GIRQ_BIT BIT(1)
+#define MCHP_QMSPI_DIRECT_NVIC 91
 
 /* LPC */
-#define MCHP_LPC_RT_BASE	(MCHP_LPC_BASE + 0x100)
-#define MCHP_LPC_CFG_BASE	(MCHP_LPC_BASE + 0x300)
-#define MCHP_LPC_ACT		REG8(MCHP_LPC_CFG_BASE + 0x30)
-#define MCHP_LPC_SIRQ(x)	REG8(MCHP_LPC_CFG_BASE + 0x40 + (x))
-#define MCHP_LPC_CFG_BAR	REG32(MCHP_LPC_CFG_BASE + 0x60)
-#define MCHP_LPC_MAILBOX_BAR	REG32(MCHP_LPC_CFG_BASE + 0x64)
-#define MCHP_LPC_8042_BAR	REG32(MCHP_LPC_CFG_BASE + 0x68)
-#define MCHP_LPC_ACPI_EC0_BAR	REG32(MCHP_LPC_CFG_BASE + 0x6C)
-#define MCHP_LPC_ACPI_EC1_BAR	REG32(MCHP_LPC_CFG_BASE + 0x70)
-#define MCHP_LPC_ACPI_EC2_BAR	REG32(MCHP_LPC_CFG_BASE + 0x74)
-#define MCHP_LPC_ACPI_EC3_BAR	REG32(MCHP_LPC_CFG_BASE + 0x78)
-#define MCHP_LPC_ACPI_EC4_BAR	REG32(MCHP_LPC_CFG_BASE + 0x7C)
-#define MCHP_LPC_ACPI_PM1_BAR	REG32(MCHP_LPC_CFG_BASE + 0x80)
-#define MCHP_LPC_PORT92_BAR	REG32(MCHP_LPC_CFG_BASE + 0x84)
-#define MCHP_LPC_UART0_BAR	REG32(MCHP_LPC_CFG_BASE + 0x88)
-#define MCHP_LPC_UART1_BAR	REG32(MCHP_LPC_CFG_BASE + 0x8C)
-#define MCHP_LPC_EMI0_BAR	REG32(MCHP_LPC_CFG_BASE + 0x90)
-#define MCHP_LPC_EMI1_BAR	REG32(MCHP_LPC_CFG_BASE + 0x94)
-#define MCHP_LPC_EMI2_BAR	REG32(MCHP_LPC_CFG_BASE + 0x98)
-#define MCHP_LPC_P80DBG0_BAR	REG32(MCHP_LPC_CFG_BASE + 0x9C)
-#define MCHP_LPC_P80DBG1_BAR	REG32(MCHP_LPC_CFG_BASE + 0xA0)
-#define MCHP_LPC_RTC_BAR	REG32(MCHP_LPC_CFG_BASE + 0xA4)
-#define MCHP_LPC_ACPI_EC_BAR(x)	REG32(MCHP_LPC_CFG_BASE + 0x6C + ((x)<<2))
+#define MCHP_LPC_RT_BASE (MCHP_LPC_BASE + 0x100)
+#define MCHP_LPC_CFG_BASE (MCHP_LPC_BASE + 0x300)
+#define MCHP_LPC_ACT REG8(MCHP_LPC_CFG_BASE + 0x30)
+#define MCHP_LPC_SIRQ(x) REG8(MCHP_LPC_CFG_BASE + 0x40 + (x))
+#define MCHP_LPC_CFG_BAR REG32(MCHP_LPC_CFG_BASE + 0x60)
+#define MCHP_LPC_MAILBOX_BAR REG32(MCHP_LPC_CFG_BASE + 0x64)
+#define MCHP_LPC_8042_BAR REG32(MCHP_LPC_CFG_BASE + 0x68)
+#define MCHP_LPC_ACPI_EC0_BAR REG32(MCHP_LPC_CFG_BASE + 0x6C)
+#define MCHP_LPC_ACPI_EC1_BAR REG32(MCHP_LPC_CFG_BASE + 0x70)
+#define MCHP_LPC_ACPI_EC2_BAR REG32(MCHP_LPC_CFG_BASE + 0x74)
+#define MCHP_LPC_ACPI_EC3_BAR REG32(MCHP_LPC_CFG_BASE + 0x78)
+#define MCHP_LPC_ACPI_EC4_BAR REG32(MCHP_LPC_CFG_BASE + 0x7C)
+#define MCHP_LPC_ACPI_PM1_BAR REG32(MCHP_LPC_CFG_BASE + 0x80)
+#define MCHP_LPC_PORT92_BAR REG32(MCHP_LPC_CFG_BASE + 0x84)
+#define MCHP_LPC_UART0_BAR REG32(MCHP_LPC_CFG_BASE + 0x88)
+#define MCHP_LPC_UART1_BAR REG32(MCHP_LPC_CFG_BASE + 0x8C)
+#define MCHP_LPC_EMI0_BAR REG32(MCHP_LPC_CFG_BASE + 0x90)
+#define MCHP_LPC_EMI1_BAR REG32(MCHP_LPC_CFG_BASE + 0x94)
+#define MCHP_LPC_EMI2_BAR REG32(MCHP_LPC_CFG_BASE + 0x98)
+#define MCHP_LPC_P80DBG0_BAR REG32(MCHP_LPC_CFG_BASE + 0x9C)
+#define MCHP_LPC_P80DBG1_BAR REG32(MCHP_LPC_CFG_BASE + 0xA0)
+#define MCHP_LPC_RTC_BAR REG32(MCHP_LPC_CFG_BASE + 0xA4)
+#define MCHP_LPC_ACPI_EC_BAR(x) REG32(MCHP_LPC_CFG_BASE + 0x6C + ((x) << 2))
 /* LPC BAR bits */
-#define MCHP_LPC_IO_BAR_ADDR_BITPOS	(16)
-#define MCHP_LPC_IO_BAR_EN		(1ul << 15)
+#define MCHP_LPC_IO_BAR_ADDR_BITPOS (16)
+#define MCHP_LPC_IO_BAR_EN (1ul << 15)
 /* LPC Generic Memory BAR's, 64-bit registers */
-#define MCHP_LPC_SRAM0_BAR_LO	REG32(MCHP_LPC_CFG_BASE + 0xB0)
-#define MCHP_LPC_SRAM0_BAR_HI	REG32(MCHP_LPC_CFG_BASE + 0xB4)
-#define MCHP_LPC_SRAM1_BAR_LO	REG32(MCHP_LPC_CFG_BASE + 0xB8)
-#define MCHP_LPC_SRAM1_BAR_HI	REG32(MCHP_LPC_CFG_BASE + 0xBC)
+#define MCHP_LPC_SRAM0_BAR_LO REG32(MCHP_LPC_CFG_BASE + 0xB0)
+#define MCHP_LPC_SRAM0_BAR_HI REG32(MCHP_LPC_CFG_BASE + 0xB4)
+#define MCHP_LPC_SRAM1_BAR_LO REG32(MCHP_LPC_CFG_BASE + 0xB8)
+#define MCHP_LPC_SRAM1_BAR_HI REG32(MCHP_LPC_CFG_BASE + 0xBC)
 /*
  * LPC Logical Device Memory BAR's, 48-bit registers
  * Use 16-bit aligned access
  */
-#define MCHP_LPC_MAILBOX_MEM_BAR_H0	REG32(MCHP_LPC_CFG_BASE + 0xC0)
-#define MCHP_LPC_MAILBOX_MEM_BAR_H1	REG32(MCHP_LPC_CFG_BASE + 0xC2)
-#define MCHP_LPC_MAILBOX_MEM_BAR_H2	REG32(MCHP_LPC_CFG_BASE + 0xC4)
-#define MCHP_LPC_ACPI_EC0_MEM_BAR_H0	REG32(MCHP_LPC_CFG_BASE + 0xC6)
-#define MCHP_LPC_ACPI_EC0_MEM_BAR_H1	REG32(MCHP_LPC_CFG_BASE + 0xC8)
-#define MCHP_LPC_ACPI_EC0_MEM_BAR_H2	REG32(MCHP_LPC_CFG_BASE + 0xCA)
-#define MCHP_LPC_ACPI_EC1_MEM_BAR_H0	REG32(MCHP_LPC_CFG_BASE + 0xCC)
-#define MCHP_LPC_ACPI_EC1_MEM_BAR_H1	REG32(MCHP_LPC_CFG_BASE + 0xCE)
-#define MCHP_LPC_ACPI_EC1_MEM_BAR_H2	REG32(MCHP_LPC_CFG_BASE + 0xD0)
-#define MCHP_LPC_ACPI_EC2_MEM_BAR_H0	REG32(MCHP_LPC_CFG_BASE + 0xD2)
-#define MCHP_LPC_ACPI_EC2_MEM_BAR_H1	REG32(MCHP_LPC_CFG_BASE + 0xD4)
-#define MCHP_LPC_ACPI_EC2_MEM_BAR_H2	REG32(MCHP_LPC_CFG_BASE + 0xD6)
-#define MCHP_LPC_ACPI_EC3_MEM_BAR_H0	REG32(MCHP_LPC_CFG_BASE + 0xD8)
-#define MCHP_LPC_ACPI_EC3_MEM_BAR_H1	REG32(MCHP_LPC_CFG_BASE + 0xDA)
-#define MCHP_LPC_ACPI_EC3_MEM_BAR_H2	REG32(MCHP_LPC_CFG_BASE + 0xDC)
-#define MCHP_LPC_ACPI_EC4_MEM_BAR_H0	REG32(MCHP_LPC_CFG_BASE + 0xDE)
-#define MCHP_LPC_ACPI_EC4_MEM_BAR_H1	REG32(MCHP_LPC_CFG_BASE + 0xE0)
-#define MCHP_LPC_ACPI_EC4_MEM_BAR_H2	REG32(MCHP_LPC_CFG_BASE + 0xE2)
-#define MCHP_LPC_ACPI_EMI0_MEM_BAR_H0	REG32(MCHP_LPC_CFG_BASE + 0xE4)
-#define MCHP_LPC_ACPI_EMI0_MEM_BAR_H1	REG32(MCHP_LPC_CFG_BASE + 0xE6)
-#define MCHP_LPC_ACPI_EMI0_MEM_BAR_H2	REG32(MCHP_LPC_CFG_BASE + 0xE8)
-#define MCHP_LPC_ACPI_EMI1_MEM_BAR_H0	REG32(MCHP_LPC_CFG_BASE + 0xEA)
-#define MCHP_LPC_ACPI_EMI1_MEM_BAR_H1	REG32(MCHP_LPC_CFG_BASE + 0xEC)
-#define MCHP_LPC_ACPI_EMI1_MEM_BAR_H2	REG32(MCHP_LPC_CFG_BASE + 0xEE)
-#define MCHP_LPC_ACPI_EMI2_MEM_BAR_H0	REG32(MCHP_LPC_CFG_BASE + 0xF0)
-#define MCHP_LPC_ACPI_EMI2_MEM_BAR_H1	REG32(MCHP_LPC_CFG_BASE + 0xF2)
-#define MCHP_LPC_ACPI_EMI2_MEM_BAR_H2	REG32(MCHP_LPC_CFG_BASE + 0xF4)
-
-#define MCHP_LPC_BUS_MONITOR	REG32(MCHP_LPC_RT_BASE + 0x4)
-#define MCHP_LPC_HOST_ERROR	REG32(MCHP_LPC_RT_BASE + 0x8)
-#define MCHP_LPC_EC_SERIRQ	REG32(MCHP_LPC_RT_BASE + 0xC)
-#define MCHP_LPC_EC_CLK_CTRL	REG32(MCHP_LPC_RT_BASE + 0x10)
-#define MCHP_LPC_BAR_INHIBIT	REG32(MCHP_LPC_RT_BASE + 0x20)
-#define MCHP_LPC_BAR_INIT	REG32(MCHP_LPC_RT_BASE + 0x30)
-#define MCHP_LPC_SRAM0_BAR	REG32(MCHP_LPC_RT_BASE + 0xf8)
-#define MCHP_LPC_SRAM1_BAR	REG32(MCHP_LPC_RT_BASE + 0xfc)
+#define MCHP_LPC_MAILBOX_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xC0)
+#define MCHP_LPC_MAILBOX_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xC2)
+#define MCHP_LPC_MAILBOX_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xC4)
+#define MCHP_LPC_ACPI_EC0_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xC6)
+#define MCHP_LPC_ACPI_EC0_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xC8)
+#define MCHP_LPC_ACPI_EC0_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xCA)
+#define MCHP_LPC_ACPI_EC1_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xCC)
+#define MCHP_LPC_ACPI_EC1_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xCE)
+#define MCHP_LPC_ACPI_EC1_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xD0)
+#define MCHP_LPC_ACPI_EC2_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xD2)
+#define MCHP_LPC_ACPI_EC2_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xD4)
+#define MCHP_LPC_ACPI_EC2_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xD6)
+#define MCHP_LPC_ACPI_EC3_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xD8)
+#define MCHP_LPC_ACPI_EC3_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xDA)
+#define MCHP_LPC_ACPI_EC3_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xDC)
+#define MCHP_LPC_ACPI_EC4_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xDE)
+#define MCHP_LPC_ACPI_EC4_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xE0)
+#define MCHP_LPC_ACPI_EC4_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xE2)
+#define MCHP_LPC_ACPI_EMI0_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xE4)
+#define MCHP_LPC_ACPI_EMI0_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xE6)
+#define MCHP_LPC_ACPI_EMI0_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xE8)
+#define MCHP_LPC_ACPI_EMI1_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xEA)
+#define MCHP_LPC_ACPI_EMI1_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xEC)
+#define MCHP_LPC_ACPI_EMI1_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xEE)
+#define MCHP_LPC_ACPI_EMI2_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xF0)
+#define MCHP_LPC_ACPI_EMI2_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xF2)
+#define MCHP_LPC_ACPI_EMI2_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xF4)
+
+#define MCHP_LPC_BUS_MONITOR REG32(MCHP_LPC_RT_BASE + 0x4)
+#define MCHP_LPC_HOST_ERROR REG32(MCHP_LPC_RT_BASE + 0x8)
+#define MCHP_LPC_EC_SERIRQ REG32(MCHP_LPC_RT_BASE + 0xC)
+#define MCHP_LPC_EC_CLK_CTRL REG32(MCHP_LPC_RT_BASE + 0x10)
+#define MCHP_LPC_BAR_INHIBIT REG32(MCHP_LPC_RT_BASE + 0x20)
+#define MCHP_LPC_BAR_INIT REG32(MCHP_LPC_RT_BASE + 0x30)
+#define MCHP_LPC_SRAM0_BAR REG32(MCHP_LPC_RT_BASE + 0xf8)
+#define MCHP_LPC_SRAM1_BAR REG32(MCHP_LPC_RT_BASE + 0xfc)
 
 /* eSPI */
 /* IO BAR defines. Use with MCHP_ESPI_IO_BAR_xxxx macros */
-#define MCHP_ESPI_IO_BAR_ID_CFG_PORT	0
-#define MCHP_ESPI_IO_BAR_ID_MEM_CMPNT	1
-#define MCHP_ESPI_IO_BAR_ID_MAILBOX	2
-#define MCHP_ESPI_IO_BAR_ID_8042	3
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC0	4
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC1	5
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC2	6
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC3	7
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC4	8
-#define MCHP_ESPI_IO_BAR_ID_ACPI_PM1	9
-#define MCHP_ESPI_IO_BAR_ID_P92		0xA
-#define MCHP_ESPI_IO_BAR_ID_UART0	0xB
-#define MCHP_ESPI_IO_BAR_ID_UART1	0xC
-#define MCHP_ESPI_IO_BAR_ID_EMI0	0xD
-#define MCHP_ESPI_IO_BAR_ID_EMI1	0xE
-#define MCHP_ESPI_IO_BAR_ID_EMI2	0xF
-#define MCHP_ESPI_IO_BAR_P80_0		0x10
-#define MCHP_ESPI_IO_BAR_P80_1		0x11
-#define MCHP_ESPI_IO_BAR_RTC		0x12
+#define MCHP_ESPI_IO_BAR_ID_CFG_PORT 0
+#define MCHP_ESPI_IO_BAR_ID_MEM_CMPNT 1
+#define MCHP_ESPI_IO_BAR_ID_MAILBOX 2
+#define MCHP_ESPI_IO_BAR_ID_8042 3
+#define MCHP_ESPI_IO_BAR_ID_ACPI_EC0 4
+#define MCHP_ESPI_IO_BAR_ID_ACPI_EC1 5
+#define MCHP_ESPI_IO_BAR_ID_ACPI_EC2 6
+#define MCHP_ESPI_IO_BAR_ID_ACPI_EC3 7
+#define MCHP_ESPI_IO_BAR_ID_ACPI_EC4 8
+#define MCHP_ESPI_IO_BAR_ID_ACPI_PM1 9
+#define MCHP_ESPI_IO_BAR_ID_P92 0xA
+#define MCHP_ESPI_IO_BAR_ID_UART0 0xB
+#define MCHP_ESPI_IO_BAR_ID_UART1 0xC
+#define MCHP_ESPI_IO_BAR_ID_EMI0 0xD
+#define MCHP_ESPI_IO_BAR_ID_EMI1 0xE
+#define MCHP_ESPI_IO_BAR_ID_EMI2 0xF
+#define MCHP_ESPI_IO_BAR_P80_0 0x10
+#define MCHP_ESPI_IO_BAR_P80_1 0x11
+#define MCHP_ESPI_IO_BAR_RTC 0x12
 
 /* Use with MCHP_ESPI_MBAR_EC_xxxx(x) macros */
-#define MCHP_ESPI_MBAR_ID_MBOX		0
-#define MCHP_ESPI_MBAR_ID_ACPI_EC_0	1
-#define MCHP_ESPI_MBAR_ID_ACPI_EC_1	2
-#define MCHP_ESPI_MBAR_ID_ACPI_EC_2	3
-#define MCHP_ESPI_MBAR_ID_ACPI_EC_3	4
-#define MCHP_ESPI_MBAR_ID_ACPI_EC_4	5
-#define MCHP_ESPI_MBAR_ID_EMI_0		6
-#define MCHP_ESPI_MBAR_ID_EMI_1		7
-#define MCHP_ESPI_MBAR_ID_EMI_2		8
+#define MCHP_ESPI_MBAR_ID_MBOX 0
+#define MCHP_ESPI_MBAR_ID_ACPI_EC_0 1
+#define MCHP_ESPI_MBAR_ID_ACPI_EC_1 2
+#define MCHP_ESPI_MBAR_ID_ACPI_EC_2 3
+#define MCHP_ESPI_MBAR_ID_ACPI_EC_3 4
+#define MCHP_ESPI_MBAR_ID_ACPI_EC_4 5
+#define MCHP_ESPI_MBAR_ID_EMI_0 6
+#define MCHP_ESPI_MBAR_ID_EMI_1 7
+#define MCHP_ESPI_MBAR_ID_EMI_2 8
 
 /* Use with MCHP_ESPI_IO_SERIRQ_REG(x) */
-#define MCHP_ESPI_SIRQ_MBOX		0 /* Host SIRQ */
-#define MCHP_ESPI_SIRQ_MBOX_SMI		1 /* Host SMI */
-#define MCHP_ESPI_SIRQ_8042_KB		2 /* KIRQ */
-#define MCHP_ESPI_SIRQ_8042_MS		3 /* MIRQ */
-#define MCHP_ESPI_SIRQ_ACPI_EC0_OBF	4
-#define MCHP_ESPI_SIRQ_ACPI_EC1_OBF	5
-#define MCHP_ESPI_SIRQ_ACPI_EC2_OBF	6
-#define MCHP_ESPI_SIRQ_ACPI_EC3_OBF	7
-#define MCHP_ESPI_SIRQ_ACPI_EC4_OBF	8
-#define MCHP_ESPI_SIRQ_UART0		9
-#define MCHP_ESPI_SIRQ_UART1		10
-#define MCHP_ESPI_SIRQ_EMI0_HEV		11 /* Host Event */
-#define MCHP_ESPI_SIRQ_EMI0_EC2H	12 /* EC to Host */
-#define MCHP_ESPI_SIRQ_EMI1_HEV		13
-#define MCHP_ESPI_SIRQ_EMI1_EC2H	14
-#define MCHP_ESPI_SIRQ_EMI2_HEV		15
-#define MCHP_ESPI_SIRQ_EMI2_EC2H	16
-#define MCHP_ESPI_SIRQ_RTC		17
-#define MCHP_ESPI_SIRQ_EC		18
+#define MCHP_ESPI_SIRQ_MBOX 0 /* Host SIRQ */
+#define MCHP_ESPI_SIRQ_MBOX_SMI 1 /* Host SMI */
+#define MCHP_ESPI_SIRQ_8042_KB 2 /* KIRQ */
+#define MCHP_ESPI_SIRQ_8042_MS 3 /* MIRQ */
+#define MCHP_ESPI_SIRQ_ACPI_EC0_OBF 4
+#define MCHP_ESPI_SIRQ_ACPI_EC1_OBF 5
+#define MCHP_ESPI_SIRQ_ACPI_EC2_OBF 6
+#define MCHP_ESPI_SIRQ_ACPI_EC3_OBF 7
+#define MCHP_ESPI_SIRQ_ACPI_EC4_OBF 8
+#define MCHP_ESPI_SIRQ_UART0 9
+#define MCHP_ESPI_SIRQ_UART1 10
+#define MCHP_ESPI_SIRQ_EMI0_HEV 11 /* Host Event */
+#define MCHP_ESPI_SIRQ_EMI0_EC2H 12 /* EC to Host */
+#define MCHP_ESPI_SIRQ_EMI1_HEV 13
+#define MCHP_ESPI_SIRQ_EMI1_EC2H 14
+#define MCHP_ESPI_SIRQ_EMI2_HEV 15
+#define MCHP_ESPI_SIRQ_EMI2_EC2H 16
+#define MCHP_ESPI_SIRQ_RTC 17
+#define MCHP_ESPI_SIRQ_EC 18
 
 #define MCHP_ESPI_MSVW_BASE (MCHP_ESPI_VW_BASE)
 #define MCHP_ESPI_SMVW_BASE ((MCHP_ESPI_VW_BASE) + 0x200ul)
@@ -1259,22 +1243,22 @@ enum MCHP_i2c_port {
  * eSPI RESET, channel enables and operations except Master-to-Slave
  * WWires are all on GIRQ19
  */
-#define MCHP_ESPI_GIRQ			19
-#define MCHP_ESPI_PC_GIRQ_BIT		BIT(0)
-#define MCHP_ESPI_BM1_GIRQ_BIT		BIT(1)
-#define MCHP_ESPI_BM2_GIRQ_BIT		BIT(2)
-#define MCHP_ESPI_LTR_GIRQ_BIT		BIT(3)
-#define MCHP_ESPI_OOB_TX_GIRQ_BIT	BIT(4)
-#define MCHP_ESPI_OOB_RX_GIRQ_BIT	BIT(5)
-#define MCHP_ESPI_FC_GIRQ_BIT		BIT(6)
-#define MCHP_ESPI_RESET_GIRQ_BIT	BIT(7)
-#define MCHP_ESPI_VW_EN_GIRQ_BIT	BIT(8)
+#define MCHP_ESPI_GIRQ 19
+#define MCHP_ESPI_PC_GIRQ_BIT BIT(0)
+#define MCHP_ESPI_BM1_GIRQ_BIT BIT(1)
+#define MCHP_ESPI_BM2_GIRQ_BIT BIT(2)
+#define MCHP_ESPI_LTR_GIRQ_BIT BIT(3)
+#define MCHP_ESPI_OOB_TX_GIRQ_BIT BIT(4)
+#define MCHP_ESPI_OOB_RX_GIRQ_BIT BIT(5)
+#define MCHP_ESPI_FC_GIRQ_BIT BIT(6)
+#define MCHP_ESPI_RESET_GIRQ_BIT BIT(7)
+#define MCHP_ESPI_VW_EN_GIRQ_BIT BIT(8)
 
 /*
  * eSPI Master-to-Slave WWire interrupts are on GIRQ24 and GIRQ25
  */
-#define MCHP_ESPI_MSVW_0_6_GIRQ		24
-#define MCHP_ESPI_MSVW_7_10_GIRQ	25
+#define MCHP_ESPI_MSVW_0_6_GIRQ 24
+#define MCHP_ESPI_MSVW_7_10_GIRQ 25
 /*
  * Four source bits, SRC[0:3] per Master-to-Slave register
  * v = MSVW [0:10]
@@ -1283,12 +1267,12 @@ enum MCHP_i2c_port {
 #define MCHP_ESPI_MSVW_GIRQ(v) (24 + ((v) > 6 ? 1 : 0))
 
 #define MCHP_ESPI_MSVW_SRC_GIRQ_BIT(v, n) \
-	(((v) > 6) ? (1ul << (((v)-7)+(n))) : (1ul << ((v)+(n))))
+	(((v) > 6) ? (1ul << (((v)-7) + (n))) : (1ul << ((v) + (n))))
 
 /* DMA */
-#define MCHP_DMA_MAX_CHAN	14
-#define MCHP_DMA_CH_OFS		0x40
-#define MCHP_DMA_CH_OFS_BITPOS	6
+#define MCHP_DMA_MAX_CHAN 14
+#define MCHP_DMA_CH_OFS 0x40
+#define MCHP_DMA_CH_OFS_BITPOS 6
 #define MCHP_DMA_CH_BASE (MCHP_DMA_BASE + MCHP_DMA_CH_OFS)
 
 /*
@@ -1322,20 +1306,20 @@ enum dma_channel {
  * Peripheral device DMA Device ID's for bits [15:9]
  * in DMA channel control register.
  */
-#define MCHP_DMA_I2C0_SLV_REQ_ID	0
-#define MCHP_DMA_I2C0_MTR_REQ_ID	1
-#define MCHP_DMA_I2C1_SLV_REQ_ID	2
-#define MCHP_DMA_I2C1_MTR_REQ_ID	3
-#define MCHP_DMA_I2C2_SLV_REQ_ID	4
-#define MCHP_DMA_I2C2_MTR_REQ_ID	5
-#define MCHP_DMA_I2C3_SLV_REQ_ID	6
-#define MCHP_DMA_I2C3_MTR_REQ_ID	7
-#define MCHP_DMA_SPI0_TX_REQ_ID		8
-#define MCHP_DMA_SPI0_RX_REQ_ID		9
-#define MCHP_DMA_SPI1_TX_REQ_ID		10
-#define MCHP_DMA_SPI1_RX_REQ_ID		11
-#define MCHP_DMA_QMSPI0_TX_REQ_ID	12
-#define MCHP_DMA_QMSPI0_RX_REQ_ID	13
+#define MCHP_DMA_I2C0_SLV_REQ_ID 0
+#define MCHP_DMA_I2C0_MTR_REQ_ID 1
+#define MCHP_DMA_I2C1_SLV_REQ_ID 2
+#define MCHP_DMA_I2C1_MTR_REQ_ID 3
+#define MCHP_DMA_I2C2_SLV_REQ_ID 4
+#define MCHP_DMA_I2C2_MTR_REQ_ID 5
+#define MCHP_DMA_I2C3_SLV_REQ_ID 6
+#define MCHP_DMA_I2C3_MTR_REQ_ID 7
+#define MCHP_DMA_SPI0_TX_REQ_ID 8
+#define MCHP_DMA_SPI0_RX_REQ_ID 9
+#define MCHP_DMA_SPI1_TX_REQ_ID 10
+#define MCHP_DMA_SPI1_RX_REQ_ID 11
+#define MCHP_DMA_QMSPI0_TX_REQ_ID 12
+#define MCHP_DMA_QMSPI0_RX_REQ_ID 13
 
 /*
  * Hardware delay register.
diff --git a/chip/mchp/registers-mec172x.h b/chip/mchp/registers-mec172x.h
index dc811ea3c7..0bd010ac05 100644
--- a/chip/mchp/registers-mec172x.h
+++ b/chip/mchp/registers-mec172x.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -14,227 +14,227 @@
  * NOTE: GIRQ22 aggregated output and its sources are not connected to
  * the NVIC.
  */
-#define MCHP_IRQ_GIRQ8		0
-#define MCHP_IRQ_GIRQ9		1
-#define MCHP_IRQ_GIRQ10		2
-#define MCHP_IRQ_GIRQ11		3
-#define MCHP_IRQ_GIRQ12		4
-#define MCHP_IRQ_GIRQ13		5
-#define MCHP_IRQ_GIRQ14		6
-#define MCHP_IRQ_GIRQ15		7
-#define MCHP_IRQ_GIRQ16		8
-#define MCHP_IRQ_GIRQ17		9
-#define MCHP_IRQ_GIRQ18		10
-#define MCHP_IRQ_GIRQ19		11
-#define MCHP_IRQ_GIRQ20		12
-#define MCHP_IRQ_GIRQ21		13
-#define MCHP_IRQ_GIRQ23		14
-#define MCHP_IRQ_GIRQ24		15
-#define MCHP_IRQ_GIRQ25		16
-#define MCHP_IRQ_GIRQ26		17
+#define MCHP_IRQ_GIRQ8 0
+#define MCHP_IRQ_GIRQ9 1
+#define MCHP_IRQ_GIRQ10 2
+#define MCHP_IRQ_GIRQ11 3
+#define MCHP_IRQ_GIRQ12 4
+#define MCHP_IRQ_GIRQ13 5
+#define MCHP_IRQ_GIRQ14 6
+#define MCHP_IRQ_GIRQ15 7
+#define MCHP_IRQ_GIRQ16 8
+#define MCHP_IRQ_GIRQ17 9
+#define MCHP_IRQ_GIRQ18 10
+#define MCHP_IRQ_GIRQ19 11
+#define MCHP_IRQ_GIRQ20 12
+#define MCHP_IRQ_GIRQ21 13
+#define MCHP_IRQ_GIRQ23 14
+#define MCHP_IRQ_GIRQ24 15
+#define MCHP_IRQ_GIRQ25 16
+#define MCHP_IRQ_GIRQ26 17
 /* GIRQ13 direct sources */
-#define MCHP_IRQ_I2C_0		20
-#define MCHP_IRQ_I2C_1		21
-#define MCHP_IRQ_I2C_2		22
-#define MCHP_IRQ_I2C_3		23
-#define MCHP_IRQ_I2C_4		158
+#define MCHP_IRQ_I2C_0 20
+#define MCHP_IRQ_I2C_1 21
+#define MCHP_IRQ_I2C_2 22
+#define MCHP_IRQ_I2C_3 23
+#define MCHP_IRQ_I2C_4 158
 /* GIRQ14 direct sources */
-#define MCHP_IRQ_DMA_0		24
-#define MCHP_IRQ_DMA_1		25
-#define MCHP_IRQ_DMA_2		26
-#define MCHP_IRQ_DMA_3		27
-#define MCHP_IRQ_DMA_4		28
-#define MCHP_IRQ_DMA_5		29
-#define MCHP_IRQ_DMA_6		30
-#define MCHP_IRQ_DMA_7		31
-#define MCHP_IRQ_DMA_8		32
-#define MCHP_IRQ_DMA_9		33
-#define MCHP_IRQ_DMA_10		34
-#define MCHP_IRQ_DMA_11		35
-#define MCHP_IRQ_DMA_12		36
-#define MCHP_IRQ_DMA_13		37
-#define MCHP_IRQ_DMA_14		38
-#define MCHP_IRQ_DMA_15		39
+#define MCHP_IRQ_DMA_0 24
+#define MCHP_IRQ_DMA_1 25
+#define MCHP_IRQ_DMA_2 26
+#define MCHP_IRQ_DMA_3 27
+#define MCHP_IRQ_DMA_4 28
+#define MCHP_IRQ_DMA_5 29
+#define MCHP_IRQ_DMA_6 30
+#define MCHP_IRQ_DMA_7 31
+#define MCHP_IRQ_DMA_8 32
+#define MCHP_IRQ_DMA_9 33
+#define MCHP_IRQ_DMA_10 34
+#define MCHP_IRQ_DMA_11 35
+#define MCHP_IRQ_DMA_12 36
+#define MCHP_IRQ_DMA_13 37
+#define MCHP_IRQ_DMA_14 38
+#define MCHP_IRQ_DMA_15 39
 /* GIRQ15 direct sources */
-#define MCHP_IRQ_UART0		40
-#define MCHP_IRQ_UART1		41
-#define MCHP_IRQ_EMI0		42
-#define MCHP_IRQ_EMI1		43
-#define MCHP_IRQ_EMI2		44
-#define MCHP_IRQ_ACPIEC0_IBF	45
-#define MCHP_IRQ_ACPIEC0_OBE	46
-#define MCHP_IRQ_ACPIEC1_IBF	47
-#define MCHP_IRQ_ACPIEC1_OBE	48
-#define MCHP_IRQ_ACPIEC2_IBF	49
-#define MCHP_IRQ_ACPIEC2_OBE	50
-#define MCHP_IRQ_ACPIEC3_IBF	51
-#define MCHP_IRQ_ACPIEC3_OBE	52
-#define MCHP_IRQ_ACPIEC4_IBF	53
-#define MCHP_IRQ_ACPIEC4_OBE	54
-#define MCHP_IRQ_ACPIPM1_CTL	55
-#define MCHP_IRQ_ACPIPM1_EN	56
-#define MCHP_IRQ_ACPIPM1_STS	57
-#define MCHP_IRQ_8042EM_OBE	58
-#define MCHP_IRQ_8042EM_IBF	59
-#define MCHP_IRQ_MAILBOX_DATA	60
-#define MCHP_IRQ_BDP0		62
+#define MCHP_IRQ_UART0 40
+#define MCHP_IRQ_UART1 41
+#define MCHP_IRQ_EMI0 42
+#define MCHP_IRQ_EMI1 43
+#define MCHP_IRQ_EMI2 44
+#define MCHP_IRQ_ACPIEC0_IBF 45
+#define MCHP_IRQ_ACPIEC0_OBE 46
+#define MCHP_IRQ_ACPIEC1_IBF 47
+#define MCHP_IRQ_ACPIEC1_OBE 48
+#define MCHP_IRQ_ACPIEC2_IBF 49
+#define MCHP_IRQ_ACPIEC2_OBE 50
+#define MCHP_IRQ_ACPIEC3_IBF 51
+#define MCHP_IRQ_ACPIEC3_OBE 52
+#define MCHP_IRQ_ACPIEC4_IBF 53
+#define MCHP_IRQ_ACPIEC4_OBE 54
+#define MCHP_IRQ_ACPIPM1_CTL 55
+#define MCHP_IRQ_ACPIPM1_EN 56
+#define MCHP_IRQ_ACPIPM1_STS 57
+#define MCHP_IRQ_8042EM_OBE 58
+#define MCHP_IRQ_8042EM_IBF 59
+#define MCHP_IRQ_MAILBOX_DATA 60
+#define MCHP_IRQ_BDP0 62
 /* GIRQ16 direct sources */
-#define MCHP_IRQ_PKE		65
-#define MCHP_IRQ_NDRNG		67
-#define MCHP_IRQ_AESH		68
+#define MCHP_IRQ_PKE 65
+#define MCHP_IRQ_NDRNG 67
+#define MCHP_IRQ_AESH 68
 /* GIRQ17 direct sources */
-#define MCHP_IRQ_PECI_HOST	70
-#define MCHP_IRQ_TACH_0		71
-#define MCHP_IRQ_TACH_1		72
-#define MCHP_IRQ_TACH_2		73
-#define MCHP_IRQ_TACH_3		159
-#define MCHP_IRQ_FAN0_FAIL	74
-#define MCHP_IRQ_FAN0_STALL	75
-#define MCHP_IRQ_FAN1_FAIL	76
-#define MCHP_IRQ_FAN1_STALL	77
-#define MCHP_IRQ_ADC_SNGL	78
-#define MCHP_IRQ_ADC_RPT	79
-#define MCHP_IRQ_RCID0		80
-#define MCHP_IRQ_RCID1		81
-#define MCHP_IRQ_RCID2		82
-#define MCHP_IRQ_LED0_WDT	83
-#define MCHP_IRQ_LED1_WDT	84
-#define MCHP_IRQ_LED2_WDT	85
-#define MCHP_IRQ_LED3_WDT	86
-#define MCHP_IRQ_PHOT		87
+#define MCHP_IRQ_PECI_HOST 70
+#define MCHP_IRQ_TACH_0 71
+#define MCHP_IRQ_TACH_1 72
+#define MCHP_IRQ_TACH_2 73
+#define MCHP_IRQ_TACH_3 159
+#define MCHP_IRQ_FAN0_FAIL 74
+#define MCHP_IRQ_FAN0_STALL 75
+#define MCHP_IRQ_FAN1_FAIL 76
+#define MCHP_IRQ_FAN1_STALL 77
+#define MCHP_IRQ_ADC_SNGL 78
+#define MCHP_IRQ_ADC_RPT 79
+#define MCHP_IRQ_RCID0 80
+#define MCHP_IRQ_RCID1 81
+#define MCHP_IRQ_RCID2 82
+#define MCHP_IRQ_LED0_WDT 83
+#define MCHP_IRQ_LED1_WDT 84
+#define MCHP_IRQ_LED2_WDT 85
+#define MCHP_IRQ_LED3_WDT 86
+#define MCHP_IRQ_PHOT 87
 /* GIRQ18 direct sources */
-#define MCHP_IRQ_SLAVE_SPI	90
-#define MCHP_IRQ_QMSPI0		91
-#define MCHP_IRQ_SPI0_TX	92
-#define MCHP_IRQ_SPI0_RX	93
-#define MCHP_IRQ_SPI1_TX	94
-#define MCHP_IRQ_SPI1_RX	95
-#define MCHP_IRQ_BCM0_ERR	96
-#define MCHP_IRQ_BCM0_BUSY	97
-#define MCHP_IRQ_PS2_0		100
-#define MCHP_IRQ_EEPROM		155
-#define MCHP_IRQ_CCT_TMR	146
-#define MCHP_IRQ_CCT_CAP0	147
-#define MCHP_IRQ_CCT_CAP1	148
-#define MCHP_IRQ_CCT_CAP2	149
-#define MCHP_IRQ_CCT_CAP3	150
-#define MCHP_IRQ_CCT_CAP4	151
-#define MCHP_IRQ_CCT_CAP5	152
-#define MCHP_IRQ_CCT_CMP0	153
-#define MCHP_IRQ_CCT_CMP1	154
+#define MCHP_IRQ_SLAVE_SPI 90
+#define MCHP_IRQ_QMSPI0 91
+#define MCHP_IRQ_SPI0_TX 92
+#define MCHP_IRQ_SPI0_RX 93
+#define MCHP_IRQ_SPI1_TX 94
+#define MCHP_IRQ_SPI1_RX 95
+#define MCHP_IRQ_BCM0_ERR 96
+#define MCHP_IRQ_BCM0_BUSY 97
+#define MCHP_IRQ_PS2_0 100
+#define MCHP_IRQ_EEPROM 155
+#define MCHP_IRQ_CCT_TMR 146
+#define MCHP_IRQ_CCT_CAP0 147
+#define MCHP_IRQ_CCT_CAP1 148
+#define MCHP_IRQ_CCT_CAP2 149
+#define MCHP_IRQ_CCT_CAP3 150
+#define MCHP_IRQ_CCT_CAP4 151
+#define MCHP_IRQ_CCT_CAP5 152
+#define MCHP_IRQ_CCT_CMP0 153
+#define MCHP_IRQ_CCT_CMP1 154
 /* GIRQ19 direct sources */
-#define MCHP_IRQ_ESPI_PC	103
-#define MCHP_IRQ_ESPI_BM1	104
-#define MCHP_IRQ_ESPI_BM2	105
-#define MCHP_IRQ_ESPI_LTR	106
-#define MCHP_IRQ_ESPI_OOB_UP	107
-#define MCHP_IRQ_ESPI_OOB_DN	108
-#define MCHP_IRQ_ESPI_FC	109
-#define MCHP_IRQ_ESPI_RESET	110
-#define MCHP_IRQ_ESPI_VW_EN	156
-#define MCHP_IRQ_ESPI_SAF_DONE	166
-#define MCHP_IRQ_ESPI_SAF_ERR	166
-#define MCHP_IRQ_ESPI_SAF_CACHE	169
+#define MCHP_IRQ_ESPI_PC 103
+#define MCHP_IRQ_ESPI_BM1 104
+#define MCHP_IRQ_ESPI_BM2 105
+#define MCHP_IRQ_ESPI_LTR 106
+#define MCHP_IRQ_ESPI_OOB_UP 107
+#define MCHP_IRQ_ESPI_OOB_DN 108
+#define MCHP_IRQ_ESPI_FC 109
+#define MCHP_IRQ_ESPI_RESET 110
+#define MCHP_IRQ_ESPI_VW_EN 156
+#define MCHP_IRQ_ESPI_SAF_DONE 166
+#define MCHP_IRQ_ESPI_SAF_ERR 166
+#define MCHP_IRQ_ESPI_SAF_CACHE 169
 /* GIRQ20 direct sources */
-#define MCHP_IRQ_OTP		173
-#define MCHP_IRQ_CLK32K_MON	174
+#define MCHP_IRQ_OTP 173
+#define MCHP_IRQ_CLK32K_MON 174
 /* GIRQ21 direct sources */
-#define MCHP_IRQ_WDG		171
-#define MCHP_IRQ_WEEK_ALARM	114
-#define MCHP_IRQ_SUBWEEK	115
-#define MCHP_IRQ_WEEK_SEC	116
-#define MCHP_IRQ_WEEK_SUBSEC	117
-#define MCHP_IRQ_WEEK_SYSPWR	118
-#define MCHP_IRQ_RTC		119
-#define MCHP_IRQ_RTC_ALARM	120
-#define MCHP_IRQ_VCI_OVRD_IN	121
-#define MCHP_IRQ_VCI_IN0	122
-#define MCHP_IRQ_VCI_IN1	123
-#define MCHP_IRQ_VCI_IN2	124
-#define MCHP_IRQ_VCI_IN3	125
-#define MCHP_IRQ_VCI_IN4	126
-#define MCHP_IRQ_PS20A_WAKE	129
-#define MCHP_IRQ_PS20B_WAKE	130
-#define MCHP_IRQ_KSC_INT	135
-#define MCHP_IRQ_GLUE		172
+#define MCHP_IRQ_WDG 171
+#define MCHP_IRQ_WEEK_ALARM 114
+#define MCHP_IRQ_SUBWEEK 115
+#define MCHP_IRQ_WEEK_SEC 116
+#define MCHP_IRQ_WEEK_SUBSEC 117
+#define MCHP_IRQ_WEEK_SYSPWR 118
+#define MCHP_IRQ_RTC 119
+#define MCHP_IRQ_RTC_ALARM 120
+#define MCHP_IRQ_VCI_OVRD_IN 121
+#define MCHP_IRQ_VCI_IN0 122
+#define MCHP_IRQ_VCI_IN1 123
+#define MCHP_IRQ_VCI_IN2 124
+#define MCHP_IRQ_VCI_IN3 125
+#define MCHP_IRQ_VCI_IN4 126
+#define MCHP_IRQ_PS20A_WAKE 129
+#define MCHP_IRQ_PS20B_WAKE 130
+#define MCHP_IRQ_KSC_INT 135
+#define MCHP_IRQ_GLUE 172
 /* GIRQ23 direct sources */
-#define MCHP_IRQ_TIMER16_0	136
-#define MCHP_IRQ_TIMER16_1	137
-#define MCHP_IRQ_TIMER16_2	138
-#define MCHP_IRQ_TIMER16_3	139
-#define MCHP_IRQ_TIMER32_0	140
-#define MCHP_IRQ_TIMER32_1	141
-#define MCHP_IRQ_CNTR_TM0	142
-#define MCHP_IRQ_CNTR_TM1	143
-#define MCHP_IRQ_CNTR_TM2	144
-#define MCHP_IRQ_CNTR_TM3	145
-#define MCHP_IRQ_RTOS_TIMER	111
-#define MCHP_IRQ_HTIMER0	112
-#define MCHP_IRQ_HTIMER1	113
+#define MCHP_IRQ_TIMER16_0 136
+#define MCHP_IRQ_TIMER16_1 137
+#define MCHP_IRQ_TIMER16_2 138
+#define MCHP_IRQ_TIMER16_3 139
+#define MCHP_IRQ_TIMER32_0 140
+#define MCHP_IRQ_TIMER32_1 141
+#define MCHP_IRQ_CNTR_TM0 142
+#define MCHP_IRQ_CNTR_TM1 143
+#define MCHP_IRQ_CNTR_TM2 144
+#define MCHP_IRQ_CNTR_TM3 145
+#define MCHP_IRQ_RTOS_TIMER 111
+#define MCHP_IRQ_HTIMER0 112
+#define MCHP_IRQ_HTIMER1 113
 /* Must match CONFIG_IRQ_COUNT in config_chip.h */
 #define MCHP_IRQ_MAX 180
 
 /* Block base addresses */
-#define MCHP_WDG_BASE		0x40000400
-#define MCHP_TMR16_0_BASE	0x40000c00
-#define MCHP_TMR32_0_BASE	0x40000c80
-#define MCHP_CNT16_0_BASE	0x40000d00
-#define MCHP_DMA_BASE		0x40002400
-#define MCHP_PROCHOT_BASE	0x40003400
-#define MCHP_I2C0_BASE		0x40004000
-#define MCHP_I2C1_BASE		0x40004400
-#define MCHP_I2C2_BASE		0x40004800
-#define MCHP_I2C3_BASE		0x40004C00
-#define MCHP_I2C4_BASE		0x40005000
-#define MCHP_CACHE_CTRL_BASE	0x40005400
-#define MCHP_PWM_0_BASE		0x40005800
-#define MCHP_TACH_0_BASE	0x40006000
-#define MCHP_PECI_BASE		0x40006400
-#define MCHP_SPIEP_BASE		0x40007000
-#define MCHP_RTMR_BASE		0x40007400
-#define MCHP_ADC_BASE		0x40007c00
-#define MCHP_ESPI_SAF_BASE	0x40008000
-#define MCHP_TFDP_BASE		0x40008c00
-#define MCHP_GPSPI0_BASE	0x40009400
-#define MCHP_GPSPI1_BASE	0x40009480
-#define MCHP_HTIMER_BASE	0x40009800
-#define MCHP_KEYSCAN_BASE	0x40009c00
-#define MCHP_RPM2PWM0_BASE	0x4000a000
-#define MCHP_RPM2PWM1_BASE	0x4000a080
-#define MCHP_VBAT_BASE		0x4000a400
-#define MCHP_VBAT_RAM_BASE	0x4000a800
-#define MCHP_WKTIMER_BASE	0x4000ac80
-#define MCHP_VCI_BASE		0x4000ae00
-#define MCHP_BBLED_0_BASE	0x4000B800
-#define MCHP_BCL_0_BASE		0x4000cd00
-#define MCHP_INT_BASE		0x4000e000
-#define MCHP_EC_BASE		0x4000fc00
-
-#define MCHP_QMSPI0_BASE	0x40070000
+#define MCHP_WDG_BASE 0x40000400
+#define MCHP_TMR16_0_BASE 0x40000c00
+#define MCHP_TMR32_0_BASE 0x40000c80
+#define MCHP_CNT16_0_BASE 0x40000d00
+#define MCHP_DMA_BASE 0x40002400
+#define MCHP_PROCHOT_BASE 0x40003400
+#define MCHP_I2C0_BASE 0x40004000
+#define MCHP_I2C1_BASE 0x40004400
+#define MCHP_I2C2_BASE 0x40004800
+#define MCHP_I2C3_BASE 0x40004C00
+#define MCHP_I2C4_BASE 0x40005000
+#define MCHP_CACHE_CTRL_BASE 0x40005400
+#define MCHP_PWM_0_BASE 0x40005800
+#define MCHP_TACH_0_BASE 0x40006000
+#define MCHP_PECI_BASE 0x40006400
+#define MCHP_SPIEP_BASE 0x40007000
+#define MCHP_RTMR_BASE 0x40007400
+#define MCHP_ADC_BASE 0x40007c00
+#define MCHP_ESPI_SAF_BASE 0x40008000
+#define MCHP_TFDP_BASE 0x40008c00
+#define MCHP_GPSPI0_BASE 0x40009400
+#define MCHP_GPSPI1_BASE 0x40009480
+#define MCHP_HTIMER_BASE 0x40009800
+#define MCHP_KEYSCAN_BASE 0x40009c00
+#define MCHP_RPM2PWM0_BASE 0x4000a000
+#define MCHP_RPM2PWM1_BASE 0x4000a080
+#define MCHP_VBAT_BASE 0x4000a400
+#define MCHP_VBAT_RAM_BASE 0x4000a800
+#define MCHP_WKTIMER_BASE 0x4000ac80
+#define MCHP_VCI_BASE 0x4000ae00
+#define MCHP_BBLED_0_BASE 0x4000B800
+#define MCHP_BCL_0_BASE 0x4000cd00
+#define MCHP_INT_BASE 0x4000e000
+#define MCHP_EC_BASE 0x4000fc00
+
+#define MCHP_QMSPI0_BASE 0x40070000
 #define MCHP_ESPI_SAF_COMM_BASE 0x40071000
 
-#define MCHP_PCR_BASE		0x40080100
-#define MCHP_GPIO_BASE		0x40081000
-#define MCHP_OTP_BASE		0x40082000
-
-#define MCHP_MBOX_BASE		0x400f0000
-#define MCHP_8042_BASE		0x400f0400
-#define MCHP_ACPI_EC_0_BASE	0x400f0800
-#define MCHP_ACPI_PM1_BASE	0x400f1c00
-#define MCHP_PORT92_BASE	0x400f2000
-#define MCHP_UART0_BASE		0x400f2400
-#define MCHP_UART1_BASE		0x400f2800
-#define MCHP_LPC_BASE		0x400f3000
-#define MCHP_ESPI_IO_BASE	0x400f3400
-#define MCHP_ESPI_MEM_BASE	0x400f3800
-#define MCHP_GLUE_BASE		0x400f3c00
-#define MCHP_EMI_0_BASE		0x400f4000
-#define MCHP_EMI_1_BASE		0x400f4400
-#define MCHP_EMI_2_BASE		0x400f4800
-#define MCHP_RTC_BASE		0x400f5000
-#define MCHP_BDP0_BASE		0x400f8000
-#define MCHP_ESPI_VW_BASE	0x400f9c00
-#define MCHP_CHIP_BASE		0x400fff00
+#define MCHP_PCR_BASE 0x40080100
+#define MCHP_GPIO_BASE 0x40081000
+#define MCHP_OTP_BASE 0x40082000
+
+#define MCHP_MBOX_BASE 0x400f0000
+#define MCHP_8042_BASE 0x400f0400
+#define MCHP_ACPI_EC_0_BASE 0x400f0800
+#define MCHP_ACPI_PM1_BASE 0x400f1c00
+#define MCHP_PORT92_BASE 0x400f2000
+#define MCHP_UART0_BASE 0x400f2400
+#define MCHP_UART1_BASE 0x400f2800
+#define MCHP_LPC_BASE 0x400f3000
+#define MCHP_ESPI_IO_BASE 0x400f3400
+#define MCHP_ESPI_MEM_BASE 0x400f3800
+#define MCHP_GLUE_BASE 0x400f3c00
+#define MCHP_EMI_0_BASE 0x400f4000
+#define MCHP_EMI_1_BASE 0x400f4400
+#define MCHP_EMI_2_BASE 0x400f4800
+#define MCHP_RTC_BASE 0x400f5000
+#define MCHP_BDP0_BASE 0x400f8000
+#define MCHP_ESPI_VW_BASE 0x400f9c00
+#define MCHP_CHIP_BASE 0x400fff00
 
 #ifndef __ASSEMBLER__
 
@@ -244,253 +244,252 @@
  * Cortex-M4 bit-banding does require aliasing of the
  * DATA SRAM region.
  */
-#define MCHP_RAM_ALIAS(x) \
-	((x) >= 0x118000 ? (x) - 0x118000 + 0x20000000 : (x))
+#define MCHP_RAM_ALIAS(x) ((x) >= 0x118000 ? (x)-0x118000 + 0x20000000 : (x))
 
 /* EC Chip Configuration */
 /* 16-bit Device ID */
-#define MCHP_CHIP_DEV_ID		REG16(MCHP_CHIP_BASE + 0x1E)
+#define MCHP_CHIP_DEV_ID REG16(MCHP_CHIP_BASE + 0x1E)
 /* 8-bit Device Sub ID */
-#define MCHP_CHIP_DEV_SUB_ID		REG8(MCHP_CHIP_BASE + 0x1D)
+#define MCHP_CHIP_DEV_SUB_ID REG8(MCHP_CHIP_BASE + 0x1D)
 /* 8-bit Device Revision */
-#define MCHP_CHIP_DEV_REV		REG8(MCHP_CHIP_BASE + 0x1C)
+#define MCHP_CHIP_DEV_REV REG8(MCHP_CHIP_BASE + 0x1C)
 /* All in one */
-#define MCHP_CHIP_DEVRID32		REG32(MCHP_CHIP_BASE + 0x1C)
-#define MCHP_CHIP_DEVID_POS		16
-#define MCHP_CHIP_DEVID_MASK		(0xfffful << MCHP_CHIP_DEVID_POS)
-#define MCHP_CHIP_SUBID_POS		8
-#define MCHP_CHIP_SUBID_MASK		(0xfful << MCHP_CHIP_SUBID_POS)
-#define MCHP_CHIP_REV_POS		0
-#define MCHP_CHIP_REV_MASK		(0xfful << MCHP_CHIP_REV_POS)
+#define MCHP_CHIP_DEVRID32 REG32(MCHP_CHIP_BASE + 0x1C)
+#define MCHP_CHIP_DEVID_POS 16
+#define MCHP_CHIP_DEVID_MASK (0xfffful << MCHP_CHIP_DEVID_POS)
+#define MCHP_CHIP_SUBID_POS 8
+#define MCHP_CHIP_SUBID_MASK (0xfful << MCHP_CHIP_SUBID_POS)
+#define MCHP_CHIP_REV_POS 0
+#define MCHP_CHIP_REV_MASK (0xfful << MCHP_CHIP_REV_POS)
 #define MCHP_CHIP_EXTRACT_DEVID(d) \
-	(((uint32_t)(d) & MCHP_CHIP_DEVID_MASK) >> MCHP_CHIP_DEVID_POS)
+	(((uint32_t)(d)&MCHP_CHIP_DEVID_MASK) >> MCHP_CHIP_DEVID_POS)
 #define MCHP_CHIP_EXTRACT_SUBID(d) \
-	(((uint32_t)(d) & MCHP_CHIP_SUBID_MASK) >> MCHP_CHIP_SUBID_POS)
+	(((uint32_t)(d)&MCHP_CHIP_SUBID_MASK) >> MCHP_CHIP_SUBID_POS)
 #define MCHP_CHIP_EXTRACT_REV(d) \
-	(((uint32_t)(d) & MCHP_CHIP_REV_MASK) >> MCHP_CHIP_REV_POS)
+	(((uint32_t)(d)&MCHP_CHIP_REV_MASK) >> MCHP_CHIP_REV_POS)
 
 /* PCR clock control dividers */
-#define MCHP_PCR_CLK_CTL_FASTEST	1U
-#define MCHP_PCR_CLK_CTL_96MHZ		1U
-#define MCHP_PCR_CLK_CTL_48MHZ		2U
-#define MCHP_PCR_CLK_CTL_24MHZ		4U
-#define MCHP_PCR_CLK_CTL_12MHZ		8U
+#define MCHP_PCR_CLK_CTL_FASTEST 1U
+#define MCHP_PCR_CLK_CTL_96MHZ 1U
+#define MCHP_PCR_CLK_CTL_48MHZ 2U
+#define MCHP_PCR_CLK_CTL_24MHZ 4U
+#define MCHP_PCR_CLK_CTL_12MHZ 8U
 
 /* Number of PCR Sleep Enable, Clock Required, and Reset registers */
 #define MCHP_PCR_SLP_RST_REG_MAX 5
 
 /* Sleep 0: Sleep Enable, Clock Required, and Reset bits */
-#define MCHP_PCR_JTAG		BIT(0) /* CLKREQ only */
-#define MCHP_PCR_OTP		BIT(1)
-#define MCHP_PCR_ISPI		BIT(2)
+#define MCHP_PCR_JTAG BIT(0) /* CLKREQ only */
+#define MCHP_PCR_OTP BIT(1)
+#define MCHP_PCR_ISPI BIT(2)
 
 /* Command all blocks to sleep */
-#define MCHP_PCR_SLP_EN0_JTAG	BIT(0)
-#define MCHP_PCR_SLP_EN0_OTP	BIT(1)
-#define MCHP_PCR_SLP_EN0_ISPI	BIT(2)
-#define MCHP_PCR_SLP_EN0_SLEEP	0xffffffff
+#define MCHP_PCR_SLP_EN0_JTAG BIT(0)
+#define MCHP_PCR_SLP_EN0_OTP BIT(1)
+#define MCHP_PCR_SLP_EN0_ISPI BIT(2)
+#define MCHP_PCR_SLP_EN0_SLEEP 0xffffffff
 
 /*
  * Encode register number and bit position
  * b[4:0] = bit number
  * b[10:8] = zero based register number
  */
-#define MCHP_PCR_ERB(rnum, bnum) \
-	((((rnum) & 0x0f) << 8) | ((bnum) & 0x1f))
+#define MCHP_PCR_ERB(rnum, bnum) ((((rnum)&0x0f) << 8) | ((bnum)&0x1f))
 
 /* PCR Sleep 1: Sleep Enable, Clock Required, and Reset bits */
-#define MCHP_PCR_BTMR16_1	MCHP_PCR_ERB(1, 31)
-#define MCHP_PCR_BTMR16_0	MCHP_PCR_ERB(1, 30)
-#define MCHP_PCR_ECS		MCHP_PCR_ERB(1, 29)
-#define MCHP_PCR_PWM8		MCHP_PCR_ERB(1, 27)
-#define MCHP_PCR_PWM7		MCHP_PCR_ERB(1, 26)
-#define MCHP_PCR_PWM6		MCHP_PCR_ERB(1, 25)
-#define MCHP_PCR_PWM5		MCHP_PCR_ERB(1, 24)
-#define MCHP_PCR_PWM4		MCHP_PCR_ERB(1, 23)
-#define MCHP_PCR_PWM3		MCHP_PCR_ERB(1, 22)
-#define MCHP_PCR_PWM2		MCHP_PCR_ERB(1, 21)
-#define MCHP_PCR_PWM1		MCHP_PCR_ERB(1, 20)
-#define MCHP_PCR_TACH3		MCHP_PCR_ERB(1, 13)
-#define MCHP_PCR_TACH2		MCHP_PCR_ERB(1, 12)
-#define MCHP_PCR_TACH1		MCHP_PCR_ERB(1, 11)
-#define MCHP_PCR_I2C0		MCHP_PCR_ERB(1, 10)
-#define MCHP_PCR_WDT		MCHP_PCR_ERB(1, 9)
-#define MCHP_PCR_CPU		MCHP_PCR_ERB(1, 8)
-#define MCHP_PCR_TFDP		MCHP_PCR_ERB(1, 7)
-#define MCHP_PCR_DMA		MCHP_PCR_ERB(1, 6)
-#define MCHP_PCR_PMC		MCHP_PCR_ERB(1, 5)
-#define MCHP_PCR_PWM0		MCHP_PCR_ERB(1, 4)
-#define MCHP_PCR_TACH0		MCHP_PCR_ERB(1, 2)
-#define MCHP_PCR_PECI		MCHP_PCR_ERB(1, 1)
-#define MCHP_PCR_ECIA		MCHP_PCR_ERB(1, 0)
+#define MCHP_PCR_BTMR16_1 MCHP_PCR_ERB(1, 31)
+#define MCHP_PCR_BTMR16_0 MCHP_PCR_ERB(1, 30)
+#define MCHP_PCR_ECS MCHP_PCR_ERB(1, 29)
+#define MCHP_PCR_PWM8 MCHP_PCR_ERB(1, 27)
+#define MCHP_PCR_PWM7 MCHP_PCR_ERB(1, 26)
+#define MCHP_PCR_PWM6 MCHP_PCR_ERB(1, 25)
+#define MCHP_PCR_PWM5 MCHP_PCR_ERB(1, 24)
+#define MCHP_PCR_PWM4 MCHP_PCR_ERB(1, 23)
+#define MCHP_PCR_PWM3 MCHP_PCR_ERB(1, 22)
+#define MCHP_PCR_PWM2 MCHP_PCR_ERB(1, 21)
+#define MCHP_PCR_PWM1 MCHP_PCR_ERB(1, 20)
+#define MCHP_PCR_TACH3 MCHP_PCR_ERB(1, 13)
+#define MCHP_PCR_TACH2 MCHP_PCR_ERB(1, 12)
+#define MCHP_PCR_TACH1 MCHP_PCR_ERB(1, 11)
+#define MCHP_PCR_I2C0 MCHP_PCR_ERB(1, 10)
+#define MCHP_PCR_WDT MCHP_PCR_ERB(1, 9)
+#define MCHP_PCR_CPU MCHP_PCR_ERB(1, 8)
+#define MCHP_PCR_TFDP MCHP_PCR_ERB(1, 7)
+#define MCHP_PCR_DMA MCHP_PCR_ERB(1, 6)
+#define MCHP_PCR_PMC MCHP_PCR_ERB(1, 5)
+#define MCHP_PCR_PWM0 MCHP_PCR_ERB(1, 4)
+#define MCHP_PCR_TACH0 MCHP_PCR_ERB(1, 2)
+#define MCHP_PCR_PECI MCHP_PCR_ERB(1, 1)
+#define MCHP_PCR_ECIA MCHP_PCR_ERB(1, 0)
 
 /* Command all blocks to sleep */
-#define MCHP_PCR_SLP_EN1_BTMR16_1	BIT(31)
-#define MCHP_PCR_SLP_EN1_BTMR16_0	BIT(30)
-#define MCHP_PCR_SLP_EN1_ECS		BIT(29)
-#define MCHP_PCR_SLP_EN1_PWM_ALL	(BIT(4) | BIT(20) | BIT(21) |\
-	BIT(22) | BIT(23) | BIT(24) | BIT(25) | BIT(26) | BIT(27))
-#define MCHP_PCR_SLP_EN1_PWM8		BIT(27)
-#define MCHP_PCR_SLP_EN1_PWM7		BIT(26)
-#define MCHP_PCR_SLP_EN1_PWM6		BIT(25)
-#define MCHP_PCR_SLP_EN1_PWM5		BIT(24)
-#define MCHP_PCR_SLP_EN1_PWM4		BIT(23)
-#define MCHP_PCR_SLP_EN1_PWM3		BIT(22)
-#define MCHP_PCR_SLP_EN1_PWM2		BIT(21)
-#define MCHP_PCR_SLP_EN1_PWM1		BIT(20)
-#define MCHP_PCR_SLP_EN1_TACH3		BIT(13)
-#define MCHP_PCR_SLP_EN1_TACH2		BIT(12)
-#define MCHP_PCR_SLP_EN1_TACH1		BIT(11)
-#define MCHP_PCR_SLP_EN1_I2C0		BIT(10)
-#define MCHP_PCR_SLP_EN1_WDT		BIT(9)
-#define MCHP_PCR_SLP_EN1_CPU		BIT(8)
-#define MCHP_PCR_SLP_EN1_TFDP		BIT(7)
-#define MCHP_PCR_SLP_EN1_DMA		BIT(6)
-#define MCHP_PCR_SLP_EN1_PMC		BIT(5)
-#define MCHP_PCR_SLP_EN1_PWM0		BIT(4)
-#define MCHP_PCR_SLP_EN1_TACH0		BIT(2)
-#define MCHP_PCR_SLP_EN1_PECI		BIT(1)
-#define MCHP_PCR_SLP_EN1_ECIA		BIT(0)
+#define MCHP_PCR_SLP_EN1_BTMR16_1 BIT(31)
+#define MCHP_PCR_SLP_EN1_BTMR16_0 BIT(30)
+#define MCHP_PCR_SLP_EN1_ECS BIT(29)
+#define MCHP_PCR_SLP_EN1_PWM_ALL                                              \
+	(BIT(4) | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) | BIT(25) | \
+	 BIT(26) | BIT(27))
+#define MCHP_PCR_SLP_EN1_PWM8 BIT(27)
+#define MCHP_PCR_SLP_EN1_PWM7 BIT(26)
+#define MCHP_PCR_SLP_EN1_PWM6 BIT(25)
+#define MCHP_PCR_SLP_EN1_PWM5 BIT(24)
+#define MCHP_PCR_SLP_EN1_PWM4 BIT(23)
+#define MCHP_PCR_SLP_EN1_PWM3 BIT(22)
+#define MCHP_PCR_SLP_EN1_PWM2 BIT(21)
+#define MCHP_PCR_SLP_EN1_PWM1 BIT(20)
+#define MCHP_PCR_SLP_EN1_TACH3 BIT(13)
+#define MCHP_PCR_SLP_EN1_TACH2 BIT(12)
+#define MCHP_PCR_SLP_EN1_TACH1 BIT(11)
+#define MCHP_PCR_SLP_EN1_I2C0 BIT(10)
+#define MCHP_PCR_SLP_EN1_WDT BIT(9)
+#define MCHP_PCR_SLP_EN1_CPU BIT(8)
+#define MCHP_PCR_SLP_EN1_TFDP BIT(7)
+#define MCHP_PCR_SLP_EN1_DMA BIT(6)
+#define MCHP_PCR_SLP_EN1_PMC BIT(5)
+#define MCHP_PCR_SLP_EN1_PWM0 BIT(4)
+#define MCHP_PCR_SLP_EN1_TACH0 BIT(2)
+#define MCHP_PCR_SLP_EN1_PECI BIT(1)
+#define MCHP_PCR_SLP_EN1_ECIA BIT(0)
 /* all sleep enable 1 bits */
-#define MCHP_PCR_SLP_EN1_SLEEP		0xffffffff
+#define MCHP_PCR_SLP_EN1_SLEEP 0xffffffff
 /*
  * block not used by default
  * Do not sleep ECIA, PMC, CPU and ECS
  */
-#define MCHP_PCR_SLP_EN1_UNUSED_BLOCKS	0xdffffede
+#define MCHP_PCR_SLP_EN1_UNUSED_BLOCKS 0xdffffede
 
 /* PCR Sleep 2: Sleep Enable, Clock Required 2, Reset bits */
-#define MCHP_PCR_GLUE		MCHP_PCR_ERB(2, 29)
-#define MCHP_PCR_SAF		MCHP_PCR_ERB(2, 27)
-#define MCHP_PCR_BDP0		MCHP_PCR_ERB(2, 25)
-#define MCHP_PCR_ACPI_EC4	MCHP_PCR_ERB(2, 23)
-#define MCHP_PCR_ACPI_EC3	MCHP_PCR_ERB(2, 22)
-#define MCHP_PCR_ACPI_EC2	MCHP_PCR_ERB(2, 21)
-#define MCHP_PCR_ESPI_SCR	MCHP_PCR_ERB(2, 20)
-#define MCHP_PCR_ESPI		MCHP_PCR_ERB(2, 19)
-#define MCHP_PCR_RTC		MCHP_PCR_ERB(2, 18)
-#define MCHP_PCR_MBOX		MCHP_PCR_ERB(2, 17)
-#define MCHP_PCR_8042		MCHP_PCR_ERB(2, 16)
-#define MCHP_PCR_ACPI_PM1	MCHP_PCR_ERB(2, 15)
-#define MCHP_PCR_ACPI_EC1	MCHP_PCR_ERB(2, 14)
-#define MCHP_PCR_ACPI_EC0	MCHP_PCR_ERB(2, 13)
-#define MCHP_PCR_GCFG		MCHP_PCR_ERB(2, 12)
-#define MCHP_PCR_UART1		MCHP_PCR_ERB(2, 2)
-#define MCHP_PCR_UART0		MCHP_PCR_ERB(2, 1)
-#define MCHP_PCR_EMI0		MCHP_PCR_ERB(2, 0)
+#define MCHP_PCR_GLUE MCHP_PCR_ERB(2, 29)
+#define MCHP_PCR_SAF MCHP_PCR_ERB(2, 27)
+#define MCHP_PCR_BDP0 MCHP_PCR_ERB(2, 25)
+#define MCHP_PCR_ACPI_EC4 MCHP_PCR_ERB(2, 23)
+#define MCHP_PCR_ACPI_EC3 MCHP_PCR_ERB(2, 22)
+#define MCHP_PCR_ACPI_EC2 MCHP_PCR_ERB(2, 21)
+#define MCHP_PCR_ESPI_SCR MCHP_PCR_ERB(2, 20)
+#define MCHP_PCR_ESPI MCHP_PCR_ERB(2, 19)
+#define MCHP_PCR_RTC MCHP_PCR_ERB(2, 18)
+#define MCHP_PCR_MBOX MCHP_PCR_ERB(2, 17)
+#define MCHP_PCR_8042 MCHP_PCR_ERB(2, 16)
+#define MCHP_PCR_ACPI_PM1 MCHP_PCR_ERB(2, 15)
+#define MCHP_PCR_ACPI_EC1 MCHP_PCR_ERB(2, 14)
+#define MCHP_PCR_ACPI_EC0 MCHP_PCR_ERB(2, 13)
+#define MCHP_PCR_GCFG MCHP_PCR_ERB(2, 12)
+#define MCHP_PCR_UART1 MCHP_PCR_ERB(2, 2)
+#define MCHP_PCR_UART0 MCHP_PCR_ERB(2, 1)
+#define MCHP_PCR_EMI0 MCHP_PCR_ERB(2, 0)
 
 /* Command all blocks to sleep */
-#define MCHP_PCR_SLP_EN2_GLUE		BIT(29)
-#define MCHP_PCR_SLP_EN2_SAF		BIT(27)
-#define MCHP_PCR_SLP_EN2_BDP0		BIT(25)
-#define MCHP_PCR_SLP_EN2_ACPI_EC4	BIT(23)
-#define MCHP_PCR_SLP_EN2_ACPI_EC3	BIT(22)
-#define MCHP_PCR_SLP_EN2_ACPI_EC2	BIT(21)
-#define MCHP_PCR_SLP_EN2_ESPI_SCR	BIT(20)
-#define MCHP_PCR_SLP_EN2_ESPI		BIT(19)
-#define MCHP_PCR_SLP_EN2_RTC		BIT(18)
-#define MCHP_PCR_SLP_EN2_MAILBOX	BIT(17)
-#define MCHP_PCR_SLP_EN2_MIF8042	BIT(16)
-#define MCHP_PCR_SLP_EN2_ACPI_PM1	BIT(15)
-#define MCHP_PCR_SLP_EN2_ACPI_EC1	BIT(14)
-#define MCHP_PCR_SLP_EN2_ACPI_EC0	BIT(13)
-#define MCHP_PCR_SLP_EN2_GCFG		BIT(12)
-#define MCHP_PCR_SLP_EN2_UART1		BIT(2)
-#define MCHP_PCR_SLP_EN2_UART0		BIT(1)
-#define MCHP_PCR_SLP_EN2_EMI0		BIT(0)
+#define MCHP_PCR_SLP_EN2_GLUE BIT(29)
+#define MCHP_PCR_SLP_EN2_SAF BIT(27)
+#define MCHP_PCR_SLP_EN2_BDP0 BIT(25)
+#define MCHP_PCR_SLP_EN2_ACPI_EC4 BIT(23)
+#define MCHP_PCR_SLP_EN2_ACPI_EC3 BIT(22)
+#define MCHP_PCR_SLP_EN2_ACPI_EC2 BIT(21)
+#define MCHP_PCR_SLP_EN2_ESPI_SCR BIT(20)
+#define MCHP_PCR_SLP_EN2_ESPI BIT(19)
+#define MCHP_PCR_SLP_EN2_RTC BIT(18)
+#define MCHP_PCR_SLP_EN2_MAILBOX BIT(17)
+#define MCHP_PCR_SLP_EN2_MIF8042 BIT(16)
+#define MCHP_PCR_SLP_EN2_ACPI_PM1 BIT(15)
+#define MCHP_PCR_SLP_EN2_ACPI_EC1 BIT(14)
+#define MCHP_PCR_SLP_EN2_ACPI_EC0 BIT(13)
+#define MCHP_PCR_SLP_EN2_GCFG BIT(12)
+#define MCHP_PCR_SLP_EN2_UART1 BIT(2)
+#define MCHP_PCR_SLP_EN2_UART0 BIT(1)
+#define MCHP_PCR_SLP_EN2_EMI0 BIT(0)
 /* all sleep enable 2 bits */
-#define MCHP_PCR_SLP_EN2_SLEEP		0xffffffff
+#define MCHP_PCR_SLP_EN2_SLEEP 0xffffffff
 
 /* PCR Sleep 3: Sleep Enable, Clock Required, and Reset */
-#define MCHP_PCR_PWM9		MCHP_PCR_ERB(3, 31)
-#define MCHP_PCR_CCT0		MCHP_PCR_ERB(3, 30)
-#define MCHP_PCR_HTMR1		MCHP_PCR_ERB(3, 29)
-#define MCHP_PCR_CRYPTO		MCHP_PCR_ERB(3, 26)
-#define MCHP_PCR_LED3		MCHP_PCR_ERB(3, 25)
-#define MCHP_PCR_BTMR32_1	MCHP_PCR_ERB(3, 24)
-#define MCHP_PCR_BTMR32_0	MCHP_PCR_ERB(3, 23)
-#define MCHP_PCR_BTMR16_3	MCHP_PCR_ERB(3, 22)
-#define MCHP_PCR_BTMR16_2	MCHP_PCR_ERB(3, 21)
-#define MCHP_PCR_I2C4		MCHP_PCR_ERB(3, 20)
-#define MCHP_PCR_BCM0		MCHP_PCR_ERB(3, 19)
-#define MCHP_PCR_LED2		MCHP_PCR_ERB(3, 18)
-#define MCHP_PCR_LED1		MCHP_PCR_ERB(3, 17)
-#define MCHP_PCR_LED0		MCHP_PCR_ERB(3, 16)
-#define MCHP_PCR_I2C3		MCHP_PCR_ERB(3, 15)
-#define MCHP_PCR_I2C2		MCHP_PCR_ERB(3, 14)
-#define MCHP_PCR_I2C1		MCHP_PCR_ERB(3, 13)
-#define MCHP_PCR_RPMPWM0	MCHP_PCR_ERB(3, 12)
-#define MCHP_PCR_KEYSCAN	MCHP_PCR_ERB(3, 11)
-#define MCHP_PCR_HTMR0		MCHP_PCR_ERB(3, 10)
-#define MCHP_PCR_GPSPI0		MCHP_PCR_ERB(3, 9)
-#define MCHP_PCR_PS2_0		MCHP_PCR_ERB(3, 5)
-#define MCHP_PCR_ADC		MCHP_PCR_ERB(3, 3)
+#define MCHP_PCR_PWM9 MCHP_PCR_ERB(3, 31)
+#define MCHP_PCR_CCT0 MCHP_PCR_ERB(3, 30)
+#define MCHP_PCR_HTMR1 MCHP_PCR_ERB(3, 29)
+#define MCHP_PCR_CRYPTO MCHP_PCR_ERB(3, 26)
+#define MCHP_PCR_LED3 MCHP_PCR_ERB(3, 25)
+#define MCHP_PCR_BTMR32_1 MCHP_PCR_ERB(3, 24)
+#define MCHP_PCR_BTMR32_0 MCHP_PCR_ERB(3, 23)
+#define MCHP_PCR_BTMR16_3 MCHP_PCR_ERB(3, 22)
+#define MCHP_PCR_BTMR16_2 MCHP_PCR_ERB(3, 21)
+#define MCHP_PCR_I2C4 MCHP_PCR_ERB(3, 20)
+#define MCHP_PCR_BCM0 MCHP_PCR_ERB(3, 19)
+#define MCHP_PCR_LED2 MCHP_PCR_ERB(3, 18)
+#define MCHP_PCR_LED1 MCHP_PCR_ERB(3, 17)
+#define MCHP_PCR_LED0 MCHP_PCR_ERB(3, 16)
+#define MCHP_PCR_I2C3 MCHP_PCR_ERB(3, 15)
+#define MCHP_PCR_I2C2 MCHP_PCR_ERB(3, 14)
+#define MCHP_PCR_I2C1 MCHP_PCR_ERB(3, 13)
+#define MCHP_PCR_RPMPWM0 MCHP_PCR_ERB(3, 12)
+#define MCHP_PCR_KEYSCAN MCHP_PCR_ERB(3, 11)
+#define MCHP_PCR_HTMR0 MCHP_PCR_ERB(3, 10)
+#define MCHP_PCR_GPSPI0 MCHP_PCR_ERB(3, 9)
+#define MCHP_PCR_PS2_0 MCHP_PCR_ERB(3, 5)
+#define MCHP_PCR_ADC MCHP_PCR_ERB(3, 3)
 
 /* Command blocks to sleep */
-#define MCHP_PCR_SLP_EN3_PWM9		BIT(31)
-#define MCHP_PCR_SLP_EN3_CCT0		BIT(30)
-#define MCHP_PCR_SLP_EN3_HTMR1		BIT(29)
-#define MCHP_PCR_SLP_EN3_CRYPTO		BIT(26)
-#define MCHP_PCR_SLP_EN3_LED3		BIT(25)
-#define MCHP_PCR_SLP_EN3_BTMR32_1	BIT(24)
-#define MCHP_PCR_SLP_EN3_BTMR32_0	BIT(23)
-#define MCHP_PCR_SLP_EN3_BTMR16_3	BIT(22)
-#define MCHP_PCR_SLP_EN3_BTMR16_2	BIT(21)
-#define MCHP_PCR_SLP_EN3_I2C4		BIT(20)
-#define MCHP_PCR_SLP_EN3_BCM0		BIT(19)
-#define MCHP_PCR_SLP_EN3_LED2		BIT(18)
-#define MCHP_PCR_SLP_EN3_LED1		BIT(17)
-#define MCHP_PCR_SLP_EN3_LED0		BIT(16)
-#define MCHP_PCR_SLP_EN3_I2C3		BIT(15)
-#define MCHP_PCR_SLP_EN3_I2C2		BIT(14)
-#define MCHP_PCR_SLP_EN3_I2C1		BIT(13)
-#define MCHP_PCR_SLP_EN3_RPM2PWM0	BIT(12)
-#define MCHP_PCR_SLP_EN3_KEYSCAN	BIT(11)
-#define MCHP_PCR_SLP_EN3_HTMR0		BIT(10)
-#define MCHP_PCR_SLP_EN3_GPSPI0		BIT(9)
-#define MCHP_PCR_SLP_EN3_PS2_0		BIT(5)
-#define MCHP_PCR_SLP_EN3_ADC		BIT(3)
-#define MCHP_PCR_SLP_EN3_ALL_CRYPTO	BIT(26)
+#define MCHP_PCR_SLP_EN3_PWM9 BIT(31)
+#define MCHP_PCR_SLP_EN3_CCT0 BIT(30)
+#define MCHP_PCR_SLP_EN3_HTMR1 BIT(29)
+#define MCHP_PCR_SLP_EN3_CRYPTO BIT(26)
+#define MCHP_PCR_SLP_EN3_LED3 BIT(25)
+#define MCHP_PCR_SLP_EN3_BTMR32_1 BIT(24)
+#define MCHP_PCR_SLP_EN3_BTMR32_0 BIT(23)
+#define MCHP_PCR_SLP_EN3_BTMR16_3 BIT(22)
+#define MCHP_PCR_SLP_EN3_BTMR16_2 BIT(21)
+#define MCHP_PCR_SLP_EN3_I2C4 BIT(20)
+#define MCHP_PCR_SLP_EN3_BCM0 BIT(19)
+#define MCHP_PCR_SLP_EN3_LED2 BIT(18)
+#define MCHP_PCR_SLP_EN3_LED1 BIT(17)
+#define MCHP_PCR_SLP_EN3_LED0 BIT(16)
+#define MCHP_PCR_SLP_EN3_I2C3 BIT(15)
+#define MCHP_PCR_SLP_EN3_I2C2 BIT(14)
+#define MCHP_PCR_SLP_EN3_I2C1 BIT(13)
+#define MCHP_PCR_SLP_EN3_RPM2PWM0 BIT(12)
+#define MCHP_PCR_SLP_EN3_KEYSCAN BIT(11)
+#define MCHP_PCR_SLP_EN3_HTMR0 BIT(10)
+#define MCHP_PCR_SLP_EN3_GPSPI0 BIT(9)
+#define MCHP_PCR_SLP_EN3_PS2_0 BIT(5)
+#define MCHP_PCR_SLP_EN3_ADC BIT(3)
+#define MCHP_PCR_SLP_EN3_ALL_CRYPTO BIT(26)
 /* all sleep enable 3 bits */
-#define MCHP_PCR_SLP_EN3_SLEEP		0xffffffff
-#define MCHP_PCR_SLP_EN3_PWM_ALL	(MCHP_PCR_SLP_EN3_PWM9)
+#define MCHP_PCR_SLP_EN3_SLEEP 0xffffffff
+#define MCHP_PCR_SLP_EN3_PWM_ALL (MCHP_PCR_SLP_EN3_PWM9)
 
 /* PCR Sleep 4: Sleep Enable, Clock Required, Reset */
-#define MCHP_PCR_GPSPI1		MCHP_PCR_ERB(4, 22)
-#define MCHP_PCR_PSPI		MCHP_PCR_ERB(4, 14)
-#define MCHP_PCR_PROCHOT	MCHP_PCR_ERB(4, 13)
-#define MCHP_PCR_RCID2		MCHP_PCR_ERB(4, 12)
-#define MCHP_PCR_RCID1		MCHP_PCR_ERB(4, 11)
-#define MCHP_PCR_RCID0		MCHP_PCR_ERB(4, 10)
-#define MCHP_PCR_QMSPI		MCHP_PCR_ERB(4, 8)
-#define MCHP_PCR_RPMPWM1	MCHP_PCR_ERB(4, 7)
-#define MCHP_PCR_RTMR		MCHP_PCR_ERB(4, 6)
-#define MCHP_PCR_CNT16_3	MCHP_PCR_ERB(4, 5)
-#define MCHP_PCR_CNT16_2	MCHP_PCR_ERB(4, 4)
-#define MCHP_PCR_CNT16_1	MCHP_PCR_ERB(4, 3)
-#define MCHP_PCR_CNT16_0	MCHP_PCR_ERB(4, 2)
-#define MCHP_PCR_PWM11		MCHP_PCR_ERB(4, 1)
-#define MCHP_PCR_PWM10		MCHP_PCR_ERB(4, 0)
+#define MCHP_PCR_GPSPI1 MCHP_PCR_ERB(4, 22)
+#define MCHP_PCR_PSPI MCHP_PCR_ERB(4, 14)
+#define MCHP_PCR_PROCHOT MCHP_PCR_ERB(4, 13)
+#define MCHP_PCR_RCID2 MCHP_PCR_ERB(4, 12)
+#define MCHP_PCR_RCID1 MCHP_PCR_ERB(4, 11)
+#define MCHP_PCR_RCID0 MCHP_PCR_ERB(4, 10)
+#define MCHP_PCR_QMSPI MCHP_PCR_ERB(4, 8)
+#define MCHP_PCR_RPMPWM1 MCHP_PCR_ERB(4, 7)
+#define MCHP_PCR_RTMR MCHP_PCR_ERB(4, 6)
+#define MCHP_PCR_CNT16_3 MCHP_PCR_ERB(4, 5)
+#define MCHP_PCR_CNT16_2 MCHP_PCR_ERB(4, 4)
+#define MCHP_PCR_CNT16_1 MCHP_PCR_ERB(4, 3)
+#define MCHP_PCR_CNT16_0 MCHP_PCR_ERB(4, 2)
+#define MCHP_PCR_PWM11 MCHP_PCR_ERB(4, 1)
+#define MCHP_PCR_PWM10 MCHP_PCR_ERB(4, 0)
 
 /* Command blocks to sleep */
-#define MCHP_PCR_SLP_EN4_GPSPI1		BIT(22)
-#define MCHP_PCR_SLP_EN4_PSPI		BIT(14)
-#define MCHP_PCR_SLP_EN4_PROCHOT	BIT(13)
-#define MCHP_PCR_SLP_EN4_RCID2		BIT(12)
-#define MCHP_PCR_SLP_EN4_RCID1		BIT(11)
-#define MCHP_PCR_SLP_EN4_RCID0		BIT(10)
-#define MCHP_PCR_SLP_EN4_QMSPI		BIT(8)
-#define MCHP_PCR_SLP_EN4_RPMPWM1	BIT(7)
-#define MCHP_PCR_SLP_EN4_RTMR		BIT(6)
-#define MCHP_PCR_SLP_EN4_CNT16_3	BIT(5)
-#define MCHP_PCR_SLP_EN4_CNT16_2	BIT(4)
-#define MCHP_PCR_SLP_EN4_CNT16_1	BIT(3)
-#define MCHP_PCR_SLP_EN4_CNT16_0	BIT(2)
-#define MCHP_PCR_SLP_EN4_PWM11		BIT(1)
-#define MCHP_PCR_SLP_EN4_PWM10		BIT(0)
+#define MCHP_PCR_SLP_EN4_GPSPI1 BIT(22)
+#define MCHP_PCR_SLP_EN4_PSPI BIT(14)
+#define MCHP_PCR_SLP_EN4_PROCHOT BIT(13)
+#define MCHP_PCR_SLP_EN4_RCID2 BIT(12)
+#define MCHP_PCR_SLP_EN4_RCID1 BIT(11)
+#define MCHP_PCR_SLP_EN4_RCID0 BIT(10)
+#define MCHP_PCR_SLP_EN4_QMSPI BIT(8)
+#define MCHP_PCR_SLP_EN4_RPMPWM1 BIT(7)
+#define MCHP_PCR_SLP_EN4_RTMR BIT(6)
+#define MCHP_PCR_SLP_EN4_CNT16_3 BIT(5)
+#define MCHP_PCR_SLP_EN4_CNT16_2 BIT(4)
+#define MCHP_PCR_SLP_EN4_CNT16_1 BIT(3)
+#define MCHP_PCR_SLP_EN4_CNT16_0 BIT(2)
+#define MCHP_PCR_SLP_EN4_PWM11 BIT(1)
+#define MCHP_PCR_SLP_EN4_PWM10 BIT(0)
 
 /* all sleep enable 4 bits */
-#define MCHP_PCR_SLP_EN4_SLEEP		0xffffffff
+#define MCHP_PCR_SLP_EN4_SLEEP 0xffffffff
 #define MCHP_PCR_SLP_EN4_PWM_ALL \
 	(MCHP_PCR_SLP_EN4_PWM10 | MCHP_PCR_SLP_EN4_PWM11)
 
@@ -502,29 +501,29 @@
 #define MCHP_PCR_SLP_EN4_WAKE (~(MCHP_PCR_SLP_EN4_SLEEP))
 
 /* Bit defines for MCHP_PCR_PWR_RST_STS */
-#define MCHP_PWR_RST_STS_MASK_RO	0xc8c
-#define MCHP_PWR_RST_STS_MASK_RWC	0x170
+#define MCHP_PWR_RST_STS_MASK_RO 0xc8c
+#define MCHP_PWR_RST_STS_MASK_RWC 0x170
 #define MCHP_PWR_RST_STS_MASK \
 	((MCHP_PWR_RST_STS_MASK_RO) | (MCHP_PWR_RST_STS_MASK_RWC))
 
-#define MCHP_PWR_RST_STS_ESPI_CLK_ACT	BIT(11) /* RO */
-#define MCHP_PWR_RST_STS_32K_ACT	BIT(10) /* RO */
-#define MCHP_PWR_RST_STS_WDT		BIT(8) /* R/WC */
-#define MCHP_PWR_RST_STS_JTAG_RSTN	BIT(7) /* RO */
-#define MCHP_PWR_RST_STS_SYS		BIT(6) /* R/WC */
-#define MCHP_PWR_RST_STS_VBAT		BIT(5) /* R/WC */
-#define MCHP_PWR_RST_STS_VTR		BIT(4) /* R/WC */
-#define MCHP_PWR_RST_STS_HOST		BIT(3) /* RO */
-#define MCHP_PWR_RST_STS_VCC_PWRGD	BIT(2) /* RO */
+#define MCHP_PWR_RST_STS_ESPI_CLK_ACT BIT(11) /* RO */
+#define MCHP_PWR_RST_STS_32K_ACT BIT(10) /* RO */
+#define MCHP_PWR_RST_STS_WDT BIT(8) /* R/WC */
+#define MCHP_PWR_RST_STS_JTAG_RSTN BIT(7) /* RO */
+#define MCHP_PWR_RST_STS_SYS BIT(6) /* R/WC */
+#define MCHP_PWR_RST_STS_VBAT BIT(5) /* R/WC */
+#define MCHP_PWR_RST_STS_VTR BIT(4) /* R/WC */
+#define MCHP_PWR_RST_STS_HOST BIT(3) /* RO */
+#define MCHP_PWR_RST_STS_VCC_PWRGD BIT(2) /* RO */
 
 /* Bit defines for MCHP_PCR_PWR_RST_CTL */
-#define MCHP_PCR_PWR_HOST_RST_SEL_BITPOS	8
-#define MCHP_PCR_PWR_HOST_RST_PCI_RESET		BIT(8)
-#define MCHP_PCR_PWR_HOST_RST_ESPI_PLTRST	0
-#define MCHP_PCR_PWR_OK_INV_BITPOS		0
+#define MCHP_PCR_PWR_HOST_RST_SEL_BITPOS 8
+#define MCHP_PCR_PWR_HOST_RST_PCI_RESET BIT(8)
+#define MCHP_PCR_PWR_HOST_RST_ESPI_PLTRST 0
+#define MCHP_PCR_PWR_OK_INV_BITPOS 0
 
 /* Bit defines for MCHP_PCR_SYS_RST */
-#define MCHP_PCR_SYS_SOFT_RESET			BIT(8)
+#define MCHP_PCR_SYS_SOFT_RESET BIT(8)
 
 /*
  * PCR Peripheral Reset Lock register
@@ -534,110 +533,110 @@
  * register, write to PCR reset enable register(s), and
  * write a lock value.
  */
-#define MCHP_PCR_RST_LOCK	REG32(MCHP_PCR_BASE + 0x84)
-#define MCHP_PCR_RST_LOCK_VAL	0xa6382d4d
-#define MCHP_PCR_RST_UNLOCK_VAL	0xa6382d4c
+#define MCHP_PCR_RST_LOCK REG32(MCHP_PCR_BASE + 0x84)
+#define MCHP_PCR_RST_LOCK_VAL 0xa6382d4d
+#define MCHP_PCR_RST_UNLOCK_VAL 0xa6382d4c
 
 /* PCR VBAT soft reset. Trigger a VBAT reset */
-#define MCHP_PCR_VBAT_SRST	REG32(MCHP_PCR_BASE + 0x88)
-#define MCHP_PCR_VBAT_SRST_EN	BIT(0)
+#define MCHP_PCR_VBAT_SRST REG32(MCHP_PCR_BASE + 0x88)
+#define MCHP_PCR_VBAT_SRST_EN BIT(0)
 
 /* PCR 32KHz clock source select */
-#define MCHP_PCR_CK32_SS	REG32(MCHP_PCR_BASE + 0x8c)
-#define MCHP_PCR_CK32_SEL_MASK	GENMASK(1, 0)
-#define MCHP_PCR_CK32_SEL_SIL	0
-#define MCHP_PCR_CK32_SEL_XTAL	1
-#define MCHP_PCR_CK32_SEL_PIN	2
-#define MCHP_PCR_CK32_SEL_OFF	3
+#define MCHP_PCR_CK32_SS REG32(MCHP_PCR_BASE + 0x8c)
+#define MCHP_PCR_CK32_SEL_MASK GENMASK(1, 0)
+#define MCHP_PCR_CK32_SEL_SIL 0
+#define MCHP_PCR_CK32_SEL_XTAL 1
+#define MCHP_PCR_CK32_SEL_PIN 2
+#define MCHP_PCR_CK32_SEL_OFF 3
 
 /* PCR 32KHz period count (RO) */
-#define MCHP_PCR_CK32_PER_CNT		REG32(MCHP_PCR_BASE + 0xc0)
-#define MCHP_PCR_CD32_PER_CNT_MSK	GENMASK(15, 0)
+#define MCHP_PCR_CK32_PER_CNT REG32(MCHP_PCR_BASE + 0xc0)
+#define MCHP_PCR_CD32_PER_CNT_MSK GENMASK(15, 0)
 
 /* PCR 32KHz high pulse count (RO) */
-#define MCHP_PCR_CK32_HP_CNT		REG32(MCHP_PCR_BASE + 0xc4)
-#define MCHP_PCR_CK32_HP_CNT_MSK	GENMASK(15, 0)
+#define MCHP_PCR_CK32_HP_CNT REG32(MCHP_PCR_BASE + 0xc4)
+#define MCHP_PCR_CK32_HP_CNT_MSK GENMASK(15, 0)
 
 /* PCR 32KHz minimum acceptable period count */
-#define MCHP_PCR_CK32_MIN_PER_CNT	REG32(MCHP_PCR_BASE + 0xc8)
-#define MCHP_PCR_CK32_MIN_PER_CNT_MSK	GENMASK(15, 0)
+#define MCHP_PCR_CK32_MIN_PER_CNT REG32(MCHP_PCR_BASE + 0xc8)
+#define MCHP_PCR_CK32_MIN_PER_CNT_MSK GENMASK(15, 0)
 
 /* PCR 32KHz maximum acceptable period count */
-#define MCHP_PCR_CK32_MAX_PER_CNT	REG32(MCHP_PCR_BASE + 0xcc)
-#define MCHP_PCR_CK32_MAX_PER_CNT_MSK	GENMASK(15, 0)
+#define MCHP_PCR_CK32_MAX_PER_CNT REG32(MCHP_PCR_BASE + 0xcc)
+#define MCHP_PCR_CK32_MAX_PER_CNT_MSK GENMASK(15, 0)
 
 /* PCR 32KHz duty cycle variation count (RO) */
-#define MCHP_PCR_CK32_DC_VAR_CNT	REG32(MCHP_PCR_BASE + 0xd0)
-#define MCHP_PCR_CK32_DC_VAR_CNT_MSK	GENMASK(15, 0)
+#define MCHP_PCR_CK32_DC_VAR_CNT REG32(MCHP_PCR_BASE + 0xd0)
+#define MCHP_PCR_CK32_DC_VAR_CNT_MSK GENMASK(15, 0)
 
 /* PCR 32KHz duty cycle variation acceptable maximum */
-#define MCHP_PCR_CK32_DC_VAR_MAX	REG32(MCHP_PCR_BASE + 0xd4)
-#define MCHP_PCR_CK32_DC_VAR_MAX_MSK	GENMASK(15, 0)
+#define MCHP_PCR_CK32_DC_VAR_MAX REG32(MCHP_PCR_BASE + 0xd4)
+#define MCHP_PCR_CK32_DC_VAR_MAX_MSK GENMASK(15, 0)
 
 /* PCR 32KHz valid count */
-#define MCHP_PCR_CK32_VAL_CNT		REG32(MCHP_PCR_BASE + 0xd8)
-#define MCHP_PCR_CK32_VAL_CNT_MSK	GENMASK(7, 0)
+#define MCHP_PCR_CK32_VAL_CNT REG32(MCHP_PCR_BASE + 0xd8)
+#define MCHP_PCR_CK32_VAL_CNT_MSK GENMASK(7, 0)
 
 /* PCR 32KHz valid count minimum */
-#define MCHP_PCR_CK32_MIN_VAL_CNT	REG32(MCHP_PCR_BASE + 0xdc)
-#define MCHP_PCR_CK32_MIN_VAL_CNT_MSK	GENMASK(7, 0)
+#define MCHP_PCR_CK32_MIN_VAL_CNT REG32(MCHP_PCR_BASE + 0xdc)
+#define MCHP_PCR_CK32_MIN_VAL_CNT_MSK GENMASK(7, 0)
 
 /* PCR 32KHz control */
-#define MCHP_PCR_CK32_CTRL		REG32(MCHP_PCR_BASE + 0xe0)
-#define MCHP_PCR_CK32_CTRL_MSK		(GENMASK(2, 0) | BIT(4) | BIT(24))
-#define MCHP_PCR_CK32_CTRL_PER_EN	BIT(0)
-#define MCHP_PCR_CK32_CTRL_DC_EN	BIT(1)
-#define MCHP_PCR_CK32_CTRL_VAL_EN	BIT(2)
-#define MCHP_PCR_CK32_CTRL_SRC_SIL	BIT(3)
-#define MCHP_PCR_CK32_CTRL_CLR_CNT	BIT(24)
+#define MCHP_PCR_CK32_CTRL REG32(MCHP_PCR_BASE + 0xe0)
+#define MCHP_PCR_CK32_CTRL_MSK (GENMASK(2, 0) | BIT(4) | BIT(24))
+#define MCHP_PCR_CK32_CTRL_PER_EN BIT(0)
+#define MCHP_PCR_CK32_CTRL_DC_EN BIT(1)
+#define MCHP_PCR_CK32_CTRL_VAL_EN BIT(2)
+#define MCHP_PCR_CK32_CTRL_SRC_SIL BIT(3)
+#define MCHP_PCR_CK32_CTRL_CLR_CNT BIT(24)
 
 /* PCR 32KHz interrupt status */
-#define MCHP_PCR_CK32_INTR_STS		REG8(MCHP_PCR_BASE + 0xe4)
+#define MCHP_PCR_CK32_INTR_STS REG8(MCHP_PCR_BASE + 0xe4)
 /* PCR 32KHz interrupt enable */
-#define MCHP_PCR_CK32_INTR_EN		REG8(MCHP_PCR_BASE + 0xe8)
-#define MCHP_PCR_CK32_INTR_PULSE_RDY	BIT(0)
-#define MCHP_PCR_CK32_INTR_PASS_PER	BIT(1)
-#define MCHP_PCR_CK32_INTR_PASS_DUTY	BIT(2)
-#define MCHP_PCR_CK32_INTR_FAIL		BIT(3)
-#define MCHP_PCR_CK32_INTR_STALL	BIT(4)
-#define MCHP_PCR_CK32_INTR_VALID	BIT(5)
-#define MCHP_PCR_CK32_INTR_UNWELL	BIT(6)
+#define MCHP_PCR_CK32_INTR_EN REG8(MCHP_PCR_BASE + 0xe8)
+#define MCHP_PCR_CK32_INTR_PULSE_RDY BIT(0)
+#define MCHP_PCR_CK32_INTR_PASS_PER BIT(1)
+#define MCHP_PCR_CK32_INTR_PASS_DUTY BIT(2)
+#define MCHP_PCR_CK32_INTR_FAIL BIT(3)
+#define MCHP_PCR_CK32_INTR_STALL BIT(4)
+#define MCHP_PCR_CK32_INTR_VALID BIT(5)
+#define MCHP_PCR_CK32_INTR_UNWELL BIT(6)
 
 /* EC Subsystem */
-#define MCHP_EC_AHB_ERR		REG32(MCHP_EC_BASE + 0x04)
-#define MCHP_EC_ID_RO		REG32(MCHP_EC_BASE + 0x10)
-#define MCHP_EC_AHB_ERR_EN	REG32(MCHP_EC_BASE + 0x14)
-#define MCHP_EC_INT_CTRL	REG32(MCHP_EC_BASE + 0x18)
-#define MCHP_EC_TRACE_EN	REG32(MCHP_EC_BASE + 0x1c)
-#define MCHP_EC_JTAG_EN		REG32(MCHP_EC_BASE + 0x20)
-#define MCHP_EC_WDT_CNT		REG32(MCHP_EC_BASE + 0x28)
-#define MCHP_EC_PECI_DISABLE	REG8(MCHP_EC_BASE + 0x40)
-#define MCHP_EC_VCI_FW_OVRD	REG32(MCHP_EC_BASE + 0x50)
-#define MCHP_EC_BROM_STS	REG32(MCHP_EC_BASE + 0x54)
-#define MCHP_EC_VW_SRC_CFG	REG32(MCHP_EC_BASE + 0x90)
-#define MCHP_EC_CMP_CTRL	REG32(MCHP_EC_BASE + 0x94)
-#define MCHP_EC_CMP_SLP_CTRL	REG32(MCHP_EC_BASE + 0x98)
+#define MCHP_EC_AHB_ERR REG32(MCHP_EC_BASE + 0x04)
+#define MCHP_EC_ID_RO REG32(MCHP_EC_BASE + 0x10)
+#define MCHP_EC_AHB_ERR_EN REG32(MCHP_EC_BASE + 0x14)
+#define MCHP_EC_INT_CTRL REG32(MCHP_EC_BASE + 0x18)
+#define MCHP_EC_TRACE_EN REG32(MCHP_EC_BASE + 0x1c)
+#define MCHP_EC_JTAG_EN REG32(MCHP_EC_BASE + 0x20)
+#define MCHP_EC_WDT_CNT REG32(MCHP_EC_BASE + 0x28)
+#define MCHP_EC_PECI_DISABLE REG8(MCHP_EC_BASE + 0x40)
+#define MCHP_EC_VCI_FW_OVRD REG32(MCHP_EC_BASE + 0x50)
+#define MCHP_EC_BROM_STS REG32(MCHP_EC_BASE + 0x54)
+#define MCHP_EC_VW_SRC_CFG REG32(MCHP_EC_BASE + 0x90)
+#define MCHP_EC_CMP_CTRL REG32(MCHP_EC_BASE + 0x94)
+#define MCHP_EC_CMP_SLP_CTRL REG32(MCHP_EC_BASE + 0x98)
 
 /* AHB ERR Disable bit[0]=0(enable), 1(disable) */
-#define MCHP_EC_AHB_ERROR_ENABLE	0
-#define MCHP_EC_AHB_ERROR_DISABLE	1
+#define MCHP_EC_AHB_ERROR_ENABLE 0
+#define MCHP_EC_AHB_ERROR_DISABLE 1
 
 /* MCHP_EC_JTAG_EN bit definitions */
-#define MCHP_JTAG_ENABLE		0x01
+#define MCHP_JTAG_ENABLE 0x01
 /* bits [2:1] */
-#define MCHP_JTAG_MODE_4PIN		0x00
+#define MCHP_JTAG_MODE_4PIN 0x00
 /* ARM 2-pin SWD plus 1-pin Serial Wire Viewer (ITM) */
-#define MCHP_JTAG_MODE_SWD_SWV		0x02
+#define MCHP_JTAG_MODE_SWD_SWV 0x02
 /* ARM 2-pin SWD with no SWV */
-#define MCHP_JTAG_MODE_SWD		0x04
+#define MCHP_JTAG_MODE_SWD 0x04
 
 /* EC Interrupt aggregator (ECIA) */
-#define MCHP_INT_GIRQ_LEN	20 /* 5 32-bit registers */
-#define MCHP_INT_GIRQ_FIRST	8
-#define MCHP_INT_GIRQ_LAST	26
-#define MCHP_INT_GIRQ_NUM	(26-8+1)
+#define MCHP_INT_GIRQ_LEN 20 /* 5 32-bit registers */
+#define MCHP_INT_GIRQ_FIRST 8
+#define MCHP_INT_GIRQ_LAST 26
+#define MCHP_INT_GIRQ_NUM (26 - 8 + 1)
 /* MCHP_INT_GIRQ_FIRST <= x <= MCHP_INT_GIRQ_LAST */
-#define MCHP_INTx_BASE(x) (MCHP_INT_BASE + (((x) - 8) * MCHP_INT_GIRQ_LEN))
+#define MCHP_INTx_BASE(x) (MCHP_INT_BASE + (((x)-8) * MCHP_INT_GIRQ_LEN))
 
 /*
  * GPIO GIRQ's are not direct capable
@@ -651,11 +650,13 @@
  * GIRQ22 wake peripheral clock only
  * GIRQ24, GIRQ25 eSPI host to endpoint virtual wires
  */
-#define MCHP_INT_AGGR_ONLY_BITMAP (BIT(8) | BIT(9) | BIT(10) | BIT(11) |\
-		BIT(12) | BIT(22) | BIT(24) | BIT(25) | BIT(26))
+#define MCHP_INT_AGGR_ONLY_BITMAP                                            \
+	(BIT(8) | BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(22) | BIT(24) | \
+	 BIT(25) | BIT(26))
 
-#define MCHP_INT_DIRECT_CAPABLE_BITMAP (BIT(13) | BIT(14) | BIT(15) |\
-	BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(23))
+#define MCHP_INT_DIRECT_CAPABLE_BITMAP                                         \
+	(BIT(13) | BIT(14) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) | \
+	 BIT(20) | BIT(21) | BIT(23))
 
 /* GIRQ13 I2C controllers 0 - 4. Direct capable */
 #define MCHP_INT13_I2C(x) BIT(x)
@@ -664,142 +665,142 @@
 #define MCHP_INT14_DMA(x) BIT(x)
 
 /* GIQ15 interrupt sources. Direct capable */
-#define MCHP_INT15_UART_0		BIT(0)
-#define MCHP_INT15_UART_1		BIT(1)
-#define MCHP_INT15_EMI_0		BIT(2)
-#define MCHP_INT15_EMI_1		BIT(3)
-#define MCHP_INT15_EMI_2		BIT(4)
-#define MCHP_INT15_ACPI_EC0_IBF		BIT(5)
-#define MCHP_INT15_ACPI_EC0_OBE		BIT(6)
-#define MCHP_INT15_ACPI_EC1_IBF		BIT(7)
-#define MCHP_INT15_ACPI_EC1_OBE		BIT(8)
-#define MCHP_INT15_ACPI_EC2_IBF		BIT(9)
-#define MCHP_INT15_ACPI_EC2_OBE		BIT(10)
-#define MCHP_INT15_ACPI_EC3_IBF		BIT(11)
-#define MCHP_INT15_ACPI_EC3_OBE		BIT(12)
-#define MCHP_INT15_ACPI_EC4_IBF		BIT(13)
-#define MCHP_INT15_ACPI_EC4_OBE		BIT(14)
-#define MCHP_INT15_ACPI_PM1_CTL		BIT(15)
-#define MCHP_INT15_ACPI_PM1_EN		BIT(16)
-#define MCHP_INT15_ACPI_PM1_STS		BIT(17)
-#define MCHP_INT15_8042_OBE		BIT(18)
-#define MCHP_INT15_8042_IBF		BIT(19)
-#define MCHP_INT15_MAILBOX		BIT(20)
-#define MCHP_INT15_BDP0			BIT(22)
+#define MCHP_INT15_UART_0 BIT(0)
+#define MCHP_INT15_UART_1 BIT(1)
+#define MCHP_INT15_EMI_0 BIT(2)
+#define MCHP_INT15_EMI_1 BIT(3)
+#define MCHP_INT15_EMI_2 BIT(4)
+#define MCHP_INT15_ACPI_EC0_IBF BIT(5)
+#define MCHP_INT15_ACPI_EC0_OBE BIT(6)
+#define MCHP_INT15_ACPI_EC1_IBF BIT(7)
+#define MCHP_INT15_ACPI_EC1_OBE BIT(8)
+#define MCHP_INT15_ACPI_EC2_IBF BIT(9)
+#define MCHP_INT15_ACPI_EC2_OBE BIT(10)
+#define MCHP_INT15_ACPI_EC3_IBF BIT(11)
+#define MCHP_INT15_ACPI_EC3_OBE BIT(12)
+#define MCHP_INT15_ACPI_EC4_IBF BIT(13)
+#define MCHP_INT15_ACPI_EC4_OBE BIT(14)
+#define MCHP_INT15_ACPI_PM1_CTL BIT(15)
+#define MCHP_INT15_ACPI_PM1_EN BIT(16)
+#define MCHP_INT15_ACPI_PM1_STS BIT(17)
+#define MCHP_INT15_8042_OBE BIT(18)
+#define MCHP_INT15_8042_IBF BIT(19)
+#define MCHP_INT15_MAILBOX BIT(20)
+#define MCHP_INT15_BDP0 BIT(22)
 
 /* GIRQ16 interrupt sources. Direct capable */
-#define MCHP_INT16_PKE_DONE		BIT(0)
-#define MCHP_INT16_RNG_DONE		BIT(2)
-#define MCHP_INT16_AESH_DONE		BIT(3)
+#define MCHP_INT16_PKE_DONE BIT(0)
+#define MCHP_INT16_RNG_DONE BIT(2)
+#define MCHP_INT16_AESH_DONE BIT(3)
 
 /* GIR17 interrupt sources. Direct capable */
-#define MCHP_INT17_PECI			BIT(0)
-#define MCHP_INT17_TACH_0		BIT(1)
-#define MCHP_INT17_TACH_1		BIT(2)
-#define MCHP_INT17_TACH_2		BIT(3)
-#define MCHP_INT17_TACH_3		BIT(4)
-#define MCHP_INT17_ADC_SINGLE		BIT(8)
-#define MCHP_INT17_ADC_REPEAT		BIT(9)
-#define MCHP_INT17_RCID_0		BIT(10)
-#define MCHP_INT17_RCID_1		BIT(11)
-#define MCHP_INT17_RCID_2		BIT(12)
-#define MCHP_INT17_LED_WDT_0		BIT(13)
-#define MCHP_INT17_LED_WDT_1		BIT(14)
-#define MCHP_INT17_LED_WDT_2		BIT(15)
-#define MCHP_INT17_LED_WDT_3		BIT(16)
-#define MCHP_INT17_PROCHOT		BIT(17)
-#define MCHP_INT17_RPM2PWM0_FAIL	BIT(20)
-#define MCHP_INT17_RPM2PWM0_STALL	BIT(21)
-#define MCHP_INT17_RPM2PWM1_FAIL	BIT(22)
-#define MCHP_INT17_RPM2PWM1_STALL	BIT(23)
+#define MCHP_INT17_PECI BIT(0)
+#define MCHP_INT17_TACH_0 BIT(1)
+#define MCHP_INT17_TACH_1 BIT(2)
+#define MCHP_INT17_TACH_2 BIT(3)
+#define MCHP_INT17_TACH_3 BIT(4)
+#define MCHP_INT17_ADC_SINGLE BIT(8)
+#define MCHP_INT17_ADC_REPEAT BIT(9)
+#define MCHP_INT17_RCID_0 BIT(10)
+#define MCHP_INT17_RCID_1 BIT(11)
+#define MCHP_INT17_RCID_2 BIT(12)
+#define MCHP_INT17_LED_WDT_0 BIT(13)
+#define MCHP_INT17_LED_WDT_1 BIT(14)
+#define MCHP_INT17_LED_WDT_2 BIT(15)
+#define MCHP_INT17_LED_WDT_3 BIT(16)
+#define MCHP_INT17_PROCHOT BIT(17)
+#define MCHP_INT17_RPM2PWM0_FAIL BIT(20)
+#define MCHP_INT17_RPM2PWM0_STALL BIT(21)
+#define MCHP_INT17_RPM2PWM1_FAIL BIT(22)
+#define MCHP_INT17_RPM2PWM1_STALL BIT(23)
 
 /* GIRQ18 interrupt sources. Direct capable */
-#define MCHP_INT18_SPIEP		BIT(0)
-#define MCHP_INT18_QMSPI		BIT(1)
-#define MCHP_INT18_GPSPI0_TXBE		BIT(2)
-#define MCHP_INT18_GPSPI0_RXBF		BIT(3)
-#define MCHP_INT18_GPSPI1_TXBE		BIT(4)
-#define MCHP_INT18_GPSPI1_RXBF		BIT(5)
-#define MCHP_INT18_BCM0_BUSY		BIT(6)
-#define MCHP_INT18_BCM0_ERR		BIT(7)
-#define MCHP_INT18_PS2_0		BIT(10)
-#define MCHP_INT18_PSPI			BIT(13)
-#define MCHP_INT18_CCT			BIT(20)
-#define MCHP_INT18_CCT_CAP0		BIT(21)
-#define MCHP_INT18_CCT_CAP1		BIT(22)
-#define MCHP_INT18_CCT_CAP2		BIT(23)
-#define MCHP_INT18_CCT_CAP3		BIT(24)
-#define MCHP_INT18_CCT_CAP4		BIT(25)
-#define MCHP_INT18_CCT_CAP6		BIT(26)
-#define MCHP_INT18_CCT_CMP0		BIT(27)
-#define MCHP_INT18_CCT_CMP1		BIT(28)
+#define MCHP_INT18_SPIEP BIT(0)
+#define MCHP_INT18_QMSPI BIT(1)
+#define MCHP_INT18_GPSPI0_TXBE BIT(2)
+#define MCHP_INT18_GPSPI0_RXBF BIT(3)
+#define MCHP_INT18_GPSPI1_TXBE BIT(4)
+#define MCHP_INT18_GPSPI1_RXBF BIT(5)
+#define MCHP_INT18_BCM0_BUSY BIT(6)
+#define MCHP_INT18_BCM0_ERR BIT(7)
+#define MCHP_INT18_PS2_0 BIT(10)
+#define MCHP_INT18_PSPI BIT(13)
+#define MCHP_INT18_CCT BIT(20)
+#define MCHP_INT18_CCT_CAP0 BIT(21)
+#define MCHP_INT18_CCT_CAP1 BIT(22)
+#define MCHP_INT18_CCT_CAP2 BIT(23)
+#define MCHP_INT18_CCT_CAP3 BIT(24)
+#define MCHP_INT18_CCT_CAP4 BIT(25)
+#define MCHP_INT18_CCT_CAP6 BIT(26)
+#define MCHP_INT18_CCT_CMP0 BIT(27)
+#define MCHP_INT18_CCT_CMP1 BIT(28)
 
 /* GIRQ19 interrupt sources. Direct capable */
-#define MCHP_INT19_ESPI_PC		BIT(0)
-#define MCHP_INT19_ESPI_BM1		BIT(1)
-#define MCHP_INT19_ESPI_BM2		BIT(2)
-#define MCHP_INT19_ESPI_LTR		BIT(3)
-#define MCHP_INT19_ESPI_OOB_TX		BIT(4)
-#define MCHP_INT19_ESPI_OOB_RX		BIT(5)
-#define MCHP_INT19_ESPI_FC		BIT(6)
-#define MCHP_INT19_ESPI_RESET		BIT(7)
-#define MCHP_INT19_ESPI_VW_EN		BIT(8)
-#define MCHP_INT19_ESPI_SAF		BIT(9)
-#define MCHP_INT19_ESPI_SAF_ERR		BIT(10)
-#define MCHP_INT19_ESPI_SAF_CACHE	BIT(11)
+#define MCHP_INT19_ESPI_PC BIT(0)
+#define MCHP_INT19_ESPI_BM1 BIT(1)
+#define MCHP_INT19_ESPI_BM2 BIT(2)
+#define MCHP_INT19_ESPI_LTR BIT(3)
+#define MCHP_INT19_ESPI_OOB_TX BIT(4)
+#define MCHP_INT19_ESPI_OOB_RX BIT(5)
+#define MCHP_INT19_ESPI_FC BIT(6)
+#define MCHP_INT19_ESPI_RESET BIT(7)
+#define MCHP_INT19_ESPI_VW_EN BIT(8)
+#define MCHP_INT19_ESPI_SAF BIT(9)
+#define MCHP_INT19_ESPI_SAF_ERR BIT(10)
+#define MCHP_INT19_ESPI_SAF_CACHE BIT(11)
 
 /* GIRQ20 interrupt sources. Direct capable */
-#define MCHP_INT20_STAP_OBF		BIT(0)
-#define MCHP_INT20_STAP_IBF		BIT(1)
-#define MCHP_INT20_STAP_WAKE		BIT(2)
-#define MCHP_INT20_OTP			BIT(3)
-#define MCHP_INT20_ISPI			BIT(8)
-#define MCHP_INT20_CLK32K_MON		BIT(9)
+#define MCHP_INT20_STAP_OBF BIT(0)
+#define MCHP_INT20_STAP_IBF BIT(1)
+#define MCHP_INT20_STAP_WAKE BIT(2)
+#define MCHP_INT20_OTP BIT(3)
+#define MCHP_INT20_ISPI BIT(8)
+#define MCHP_INT20_CLK32K_MON BIT(9)
 
 /* GIRQ21 interrupt sources. Direct capable */
-#define MCHP_INT21_WDG			BIT(2)
-#define MCHP_INT21_WEEK_ALARM		BIT(3)
-#define MCHP_INT21_WEEK_SUB		BIT(4)
-#define MCHP_INT21_WEEK_1SEC		BIT(5)
-#define MCHP_INT21_WEEK_1SEC_SUB	BIT(6)
-#define MCHP_INT21_WEEK_PWR_PRES	BIT(7)
-#define MCHP_INT21_RTC			BIT(8)
-#define MCHP_INT21_RTC_ALARM		BIT(9)
-#define MCHP_INT21_VCI_OVRD		BIT(10)
-#define MCHP_INT21_VCI_IN0		BIT(11)
-#define MCHP_INT21_VCI_IN1		BIT(12)
-#define MCHP_INT21_VCI_IN2		BIT(13)
-#define MCHP_INT21_VCI_IN3		BIT(14)
-#define MCHP_INT21_VCI_IN4		BIT(15)
-#define MCHP_INT21_PS2_0A_WAKE		BIT(18)
-#define MCHP_INT21_PS2_0B_WAKE		BIT(19)
-#define MCHP_INT21_KEYSCAN		BIT(25)
-#define MCHP_INT21_GLUE			BIT(26)
+#define MCHP_INT21_WDG BIT(2)
+#define MCHP_INT21_WEEK_ALARM BIT(3)
+#define MCHP_INT21_WEEK_SUB BIT(4)
+#define MCHP_INT21_WEEK_1SEC BIT(5)
+#define MCHP_INT21_WEEK_1SEC_SUB BIT(6)
+#define MCHP_INT21_WEEK_PWR_PRES BIT(7)
+#define MCHP_INT21_RTC BIT(8)
+#define MCHP_INT21_RTC_ALARM BIT(9)
+#define MCHP_INT21_VCI_OVRD BIT(10)
+#define MCHP_INT21_VCI_IN0 BIT(11)
+#define MCHP_INT21_VCI_IN1 BIT(12)
+#define MCHP_INT21_VCI_IN2 BIT(13)
+#define MCHP_INT21_VCI_IN3 BIT(14)
+#define MCHP_INT21_VCI_IN4 BIT(15)
+#define MCHP_INT21_PS2_0A_WAKE BIT(18)
+#define MCHP_INT21_PS2_0B_WAKE BIT(19)
+#define MCHP_INT21_KEYSCAN BIT(25)
+#define MCHP_INT21_GLUE BIT(26)
 
 /* GIRQ22 peripheral wake only. GIRQ22 not connected to NVIC */
-#define MCHP_INT22_WAKE_ONLY_SPIEP	BIT(0)
-#define MCHP_INT22_WAKE_ONLY_I2C0	BIT(1)
-#define MCHP_INT22_WAKE_ONLY_I2C1	BIT(2)
-#define MCHP_INT22_WAKE_ONLY_I2C2	BIT(3)
-#define MCHP_INT22_WAKE_ONLY_I2C3	BIT(4)
-#define MCHP_INT22_WAKE_ONLY_I2C4	BIT(5)
-#define MCHP_INT22_WAKE_ONLY_ESPI	BIT(9)
-#define MCHP_INT22_WAKE_ONLY_STAP	BIT(15)
+#define MCHP_INT22_WAKE_ONLY_SPIEP BIT(0)
+#define MCHP_INT22_WAKE_ONLY_I2C0 BIT(1)
+#define MCHP_INT22_WAKE_ONLY_I2C1 BIT(2)
+#define MCHP_INT22_WAKE_ONLY_I2C2 BIT(3)
+#define MCHP_INT22_WAKE_ONLY_I2C3 BIT(4)
+#define MCHP_INT22_WAKE_ONLY_I2C4 BIT(5)
+#define MCHP_INT22_WAKE_ONLY_ESPI BIT(9)
+#define MCHP_INT22_WAKE_ONLY_STAP BIT(15)
 
 /* GIRQ23 sources. Direct capable */
-#define MCHP_INT23_BTMR16_0		BIT(0)
-#define MCHP_INT23_BTMR16_1		BIT(1)
-#define MCHP_INT23_BTMR16_2		BIT(2)
-#define MCHP_INT23_BTMR16_3		BIT(3)
-#define MCHP_INT23_BTMR32_0		BIT(4)
-#define MCHP_INT23_BTMR32_1		BIT(5)
-#define MCHP_INT23_CNT16_0		BIT(6)
-#define MCHP_INT23_CNT16_1		BIT(7)
-#define MCHP_INT23_CNT16_2		BIT(8)
-#define MCHP_INT23_CNT16_3		BIT(9)
-#define MCHP_INT21_RTMR			BIT(10)
-#define MCHP_INT21_HTMR_0		BIT(16)
-#define MCHP_INT21_HTMR_1		BIT(17)
+#define MCHP_INT23_BTMR16_0 BIT(0)
+#define MCHP_INT23_BTMR16_1 BIT(1)
+#define MCHP_INT23_BTMR16_2 BIT(2)
+#define MCHP_INT23_BTMR16_3 BIT(3)
+#define MCHP_INT23_BTMR32_0 BIT(4)
+#define MCHP_INT23_BTMR32_1 BIT(5)
+#define MCHP_INT23_CNT16_0 BIT(6)
+#define MCHP_INT23_CNT16_1 BIT(7)
+#define MCHP_INT23_CNT16_2 BIT(8)
+#define MCHP_INT23_CNT16_3 BIT(9)
+#define MCHP_INT21_RTMR BIT(10)
+#define MCHP_INT21_HTMR_0 BIT(16)
+#define MCHP_INT21_HTMR_1 BIT(17)
 
 /* GIRQ24 sources. Master-to-Slave v=[0:6], Source=[0:3] */
 #define MCHP_INT24_MSVW_SRC(v, s) (1ul << ((4 * (v)) + (s)))
@@ -808,19 +809,18 @@
 #define MCHP_INT25_MSVW_SRC(v, s) (1ul << ((4 * ((v)-7)) + (s)))
 
 /* UART Peripheral 0 <= x <= 1 */
-#define MCHP_UART_INSTANCES	2
-#define MCHP_UART_SPACING	0x400
-#define MCHP_UART_CFG_OFS	0x300
+#define MCHP_UART_INSTANCES 2
+#define MCHP_UART_SPACING 0x400
+#define MCHP_UART_CFG_OFS 0x300
 #define MCHP_UART_CONFIG_BASE(x) \
-	(MCHP_UART0_BASE + MCHP_UART_CFG_OFS + ((x) * MCHP_UART_SPACING))
-#define MCHP_UART_RUNTIME_BASE(x) \
-	(MCHP_UART0_BASE + ((x) * MCHP_UART_SPACING))
-#define MCHP_UART_GIRQ		15
-#define MCHP_UART0_GIRQ_BIT	(MCHP_INT15_UART_0)
-#define MCHP_UART1_GIRQ_BIT	(MCHP_INT15_UART_1)
-#define MCHP_UART_GIRQ_BIT(x)	BIT(x)
+	(MCHP_UART0_BASE + MCHP_UART_CFG_OFS + ((x)*MCHP_UART_SPACING))
+#define MCHP_UART_RUNTIME_BASE(x) (MCHP_UART0_BASE + ((x)*MCHP_UART_SPACING))
+#define MCHP_UART_GIRQ 15
+#define MCHP_UART0_GIRQ_BIT (MCHP_INT15_UART_0)
+#define MCHP_UART1_GIRQ_BIT (MCHP_INT15_UART_1)
+#define MCHP_UART_GIRQ_BIT(x) BIT(x)
 /* Bit defines for MCHP_UARTx_LSR */
-#define MCHP_LSR_TX_EMPTY	BIT(5)
+#define MCHP_LSR_TX_EMPTY BIT(5)
 
 /*
  * GPIO
@@ -851,180 +851,174 @@
  * Control 1 Address = 0x40081000 + (((4 << 5) + 0x1d) << 2) = 0x40081274
  *
  */
-#define MCHP_GPIO_CTL(port, id) REG32(MCHP_GPIO_BASE + \
-	(((port << 5) + id) << 2))
+#define MCHP_GPIO_CTL(port, id) \
+	REG32(MCHP_GPIO_BASE + (((port << 5) + id) << 2))
 
 /* MCHP implements 6 GPIO ports */
-#define MCHP_GPIO_MAX_PORT	6
-#define UNIMPLEMENTED_GPIO_BANK	MCHP_GPIO_MAX_PORT
+#define MCHP_GPIO_MAX_PORT 6
+#define UNIMPLEMENTED_GPIO_BANK MCHP_GPIO_MAX_PORT
 /*
  * In MECxxxx documentation GPIO numbers are octal, each control
  * register is located on a 32-bit boundary.
  */
-#define MCHP_GPIO_CTRL(gpio_num) REG32(MCHP_GPIO_BASE + \
-	((gpio_num) << 2))
+#define MCHP_GPIO_CTRL(gpio_num) REG32(MCHP_GPIO_BASE + ((gpio_num) << 2))
 
 /*
  * GPIO control register bit fields
  */
-#define MCHP_GPIO_CTRL_PUD_BITPOS	0
-#define MCHP_GPIO_CTRL_PUD_MASK0	0x03
-#define MCHP_GPIO_CTRL_PUD_MASK		0x03
-#define MCHP_GPIO_CTRL_PUD_NONE		0x00
-#define MCHP_GPIO_CTRL_PUD_PU		0x01
-#define MCHP_GPIO_CTRL_PUD_PD		0x02
-#define MCHP_GPIO_CTRL_PUD_KEEPER	0x03
-#define MCHP_GPIO_CTRL_PWR_BITPOS	2
-#define MCHP_GPIO_CTRL_PWR_MASK0	0x03
-#define MCHP_GPIO_CTRL_PWR_MASK		GENMASK(2, 1)
-#define MCHP_GPIO_CTRL_PWR_VTR		0
-#define MCHP_GPIO_CTRL_PWR_OFF		(0x02U << 2)
-#define MCHP_GPIO_INTDET_MASK		0xF0U
-#define MCHP_GPIO_INTDET_LVL_LO		0x00
-#define MCHP_GPIO_INTDET_LVL_HI		0x10U
-#define MCHP_GPIO_INTDET_DISABLED	0x40U
-#define MCHP_GPIO_INTDET_EDGE_RIS	0xD0U
-#define MCHP_GPIO_INTDET_EDGE_FALL	0xE0U
-#define MCHP_GPIO_INTDET_EDGE_BOTH	0xF0U
-#define MCHP_GPIO_INTDET_EDGE_EN	BIT(7)
-#define MCHP_GPIO_PUSH_PULL		0U
-#define MCHP_GPIO_OPEN_DRAIN		BIT(8)
-#define MCHP_GPIO_INPUT			0U
-#define MCHP_GPIO_OUTPUT		BIT(9)
-#define MCHP_GPIO_OUTSET_CTRL		0U
-#define MCHP_GPIO_OUTSEL_PAR		BIT(10)
-#define MCHP_GPIO_POLARITY_NINV		0U
-#define MCHP_GPIO_POLARITY_INV		BIT(11)
-#define MCHP_GPIO_CTRL_ALT_FUNC_BITPOS	12
-#define MCHP_GPIO_CTRL_ALT_FUNC_MASK0	0x07U
-#define MCHP_GPIO_CTRL_ALT_FUNC_MASK	(0x07U << 12)
-#define MCHP_GPIO_CTRL_FUNC_GPIO	0
-#define MCHP_GPIO_CTRL_FUNC_1		(1U << 12)
-#define MCHP_GPIO_CTRL_FUNC_2		(2U << 12)
-#define MCHP_GPIO_CTRL_FUNC_3		(3U << 12)
-#define MCHP_GPIO_CTRL_FUNC_4		(4U << 12)
-#define MCHP_GPIO_CTRL_FUNC_5		(5U << 12)
-#define MCHP_GPIO_CTRL_OUT_LVL		BIT(16)
+#define MCHP_GPIO_CTRL_PUD_BITPOS 0
+#define MCHP_GPIO_CTRL_PUD_MASK0 0x03
+#define MCHP_GPIO_CTRL_PUD_MASK 0x03
+#define MCHP_GPIO_CTRL_PUD_NONE 0x00
+#define MCHP_GPIO_CTRL_PUD_PU 0x01
+#define MCHP_GPIO_CTRL_PUD_PD 0x02
+#define MCHP_GPIO_CTRL_PUD_KEEPER 0x03
+#define MCHP_GPIO_CTRL_PWR_BITPOS 2
+#define MCHP_GPIO_CTRL_PWR_MASK0 0x03
+#define MCHP_GPIO_CTRL_PWR_MASK GENMASK(2, 1)
+#define MCHP_GPIO_CTRL_PWR_VTR 0
+#define MCHP_GPIO_CTRL_PWR_OFF (0x02U << 2)
+#define MCHP_GPIO_INTDET_MASK 0xF0U
+#define MCHP_GPIO_INTDET_LVL_LO 0x00
+#define MCHP_GPIO_INTDET_LVL_HI 0x10U
+#define MCHP_GPIO_INTDET_DISABLED 0x40U
+#define MCHP_GPIO_INTDET_EDGE_RIS 0xD0U
+#define MCHP_GPIO_INTDET_EDGE_FALL 0xE0U
+#define MCHP_GPIO_INTDET_EDGE_BOTH 0xF0U
+#define MCHP_GPIO_INTDET_EDGE_EN BIT(7)
+#define MCHP_GPIO_PUSH_PULL 0U
+#define MCHP_GPIO_OPEN_DRAIN BIT(8)
+#define MCHP_GPIO_INPUT 0U
+#define MCHP_GPIO_OUTPUT BIT(9)
+#define MCHP_GPIO_OUTSET_CTRL 0U
+#define MCHP_GPIO_OUTSEL_PAR BIT(10)
+#define MCHP_GPIO_POLARITY_NINV 0U
+#define MCHP_GPIO_POLARITY_INV BIT(11)
+#define MCHP_GPIO_CTRL_ALT_FUNC_BITPOS 12
+#define MCHP_GPIO_CTRL_ALT_FUNC_MASK0 0x07U
+#define MCHP_GPIO_CTRL_ALT_FUNC_MASK (0x07U << 12)
+#define MCHP_GPIO_CTRL_FUNC_GPIO 0
+#define MCHP_GPIO_CTRL_FUNC_1 (1U << 12)
+#define MCHP_GPIO_CTRL_FUNC_2 (2U << 12)
+#define MCHP_GPIO_CTRL_FUNC_3 (3U << 12)
+#define MCHP_GPIO_CTRL_FUNC_4 (4U << 12)
+#define MCHP_GPIO_CTRL_FUNC_5 (5U << 12)
+#define MCHP_GPIO_CTRL_OUT_LVL BIT(16)
 /* MEC172x implements input pad disable */
-#define MCHP_GPIO_CTRL_DIS_INPUT_BITPOS	15
-#define MCHP_GPIO_CTRL_DIS_INPUT_BIT	BIT(15)
+#define MCHP_GPIO_CTRL_DIS_INPUT_BITPOS 15
+#define MCHP_GPIO_CTRL_DIS_INPUT_BIT BIT(15)
 
 /*
  * GPIO Parallel Input and Output registers.
  * gpio_bank in [0, 5]
  */
-#define MCHP_GPIO_PARIN(bank)	\
-	REG32(MCHP_GPIO_BASE + 0x0300 + ((bank) << 2))
-#define MCHP_GPIO_PAROUT(bank)	\
-	REG32(MCHP_GPIO_BASE + 0x0380 + ((bank) << 2))
+#define MCHP_GPIO_PARIN(bank) REG32(MCHP_GPIO_BASE + 0x0300 + ((bank) << 2))
+#define MCHP_GPIO_PAROUT(bank) REG32(MCHP_GPIO_BASE + 0x0380 + ((bank) << 2))
 
 /* Basic timers */
-#define MCHP_TMR_SPACING	0x20
-#define MCHP_TMR16_INSTANCES	4
-#define MCHP_TMR32_INSTANCES	2
-#define MCHP_TMR16_MAX		(MCHP_TMR16_INSTANCES)
-#define MCHP_TMR32_MAX		(MCHP_TMR32_INSTANCES)
-#define MCHP_TMR16_BASE(n)	(MCHP_TMR16_0_BASE + (n) * MCHP_TMR_SPACING)
-#define MCHP_TMR32_BASE(n)	(MCHP_TMR32_0_BASE + (n) * MCHP_TMR_SPACING)
-#define MCHP_TMR16_GIRQ		23
-#define MCHP_TMR16_GIRQ_BIT(n)	BIT(0 + (n))
-#define MCHP_TMR32_GIRQ		23
-#define MCHP_TMR32_GIRQ_BIT(n)	BIT(4 + (n))
+#define MCHP_TMR_SPACING 0x20
+#define MCHP_TMR16_INSTANCES 4
+#define MCHP_TMR32_INSTANCES 2
+#define MCHP_TMR16_MAX (MCHP_TMR16_INSTANCES)
+#define MCHP_TMR32_MAX (MCHP_TMR32_INSTANCES)
+#define MCHP_TMR16_BASE(n) (MCHP_TMR16_0_BASE + (n)*MCHP_TMR_SPACING)
+#define MCHP_TMR32_BASE(n) (MCHP_TMR32_0_BASE + (n)*MCHP_TMR_SPACING)
+#define MCHP_TMR16_GIRQ 23
+#define MCHP_TMR16_GIRQ_BIT(n) BIT(0 + (n))
+#define MCHP_TMR32_GIRQ 23
+#define MCHP_TMR32_GIRQ_BIT(n) BIT(4 + (n))
 
 /* 16-bit Counter/timer */
-#define MCHP_CNT16_SPACING	0x20
-#define MCHP_CNT16_INSTANCES	4
-#define MCHP_CNT16_BASE(n)	\
-	(MCHP_CNT16_0_BASE + (n) * MCHP_CNT16_SPACING)
-#define MCHP_CNT16_GIRQ		23
-#define MCHP_CNT16_GIRQ_BIT(x)	BIT(6 + (x))
+#define MCHP_CNT16_SPACING 0x20
+#define MCHP_CNT16_INSTANCES 4
+#define MCHP_CNT16_BASE(n) (MCHP_CNT16_0_BASE + (n)*MCHP_CNT16_SPACING)
+#define MCHP_CNT16_GIRQ 23
+#define MCHP_CNT16_GIRQ_BIT(x) BIT(6 + (x))
 
 /* RTimer */
-#define MCHP_RTMR_GIRQ		21
-#define MCHP_RTMR_GIRQ_BIT(x)	MCHP_INT21_RTMR
+#define MCHP_RTMR_GIRQ 21
+#define MCHP_RTMR_GIRQ_BIT(x) MCHP_INT21_RTMR
 
 /* Watchdog */
 /* MEC152x specific registers */
-#define MCHP_WDG_STATUS			REG32(MCHP_WDG_BASE + 0x10)
-#define MCHP_WDG_IEN			REG32(MCHP_WDG_BASE + 0x14)
+#define MCHP_WDG_STATUS REG32(MCHP_WDG_BASE + 0x10)
+#define MCHP_WDG_IEN REG32(MCHP_WDG_BASE + 0x14)
 /* Status */
-#define MCHP_WDG_STS_IRQ		BIT(0)
+#define MCHP_WDG_STS_IRQ BIT(0)
 /* Interrupt enable */
-#define MCHP_WDG_IEN_IRQ_EN		BIT(0)
-#define MCHP_WDG_GIRQ			21
-#define MCHP_WDG_GIRQ_BIT		BIT(2)
+#define MCHP_WDG_IEN_IRQ_EN BIT(0)
+#define MCHP_WDG_GIRQ 21
+#define MCHP_WDG_GIRQ_BIT BIT(2)
 /* Control register has a bit to enable IRQ generation */
-#define MCHP_WDG_RESET_IRQ_EN		BIT(9)
+#define MCHP_WDG_RESET_IRQ_EN BIT(9)
 
 /* VBAT */
-#define MCHP_VBAT_STS			REG32(MCHP_VBAT_BASE + 0x0)
-#define MCHP_VBAT_CSS			REG32(MCHP_VBAT_BASE + 0x8)
-#define MCHP_VBAT_MONOTONIC_CTR_LO	REG32(MCHP_VBAT_BASE + 0x20)
-#define MCHP_VBAT_MONOTONIC_CTR_HI	REG32(MCHP_VBAT_BASE + 0x24)
-#define MCHP_VBAT_ROM_FEAT		REG32(MCHP_VBAT_BASE + 0x28)
-#define MCHP_VBAT_EMB_DEBOUNCE_EN	REG32(MCHP_VBAT_BASE + 0x34)
+#define MCHP_VBAT_STS REG32(MCHP_VBAT_BASE + 0x0)
+#define MCHP_VBAT_CSS REG32(MCHP_VBAT_BASE + 0x8)
+#define MCHP_VBAT_MONOTONIC_CTR_LO REG32(MCHP_VBAT_BASE + 0x20)
+#define MCHP_VBAT_MONOTONIC_CTR_HI REG32(MCHP_VBAT_BASE + 0x24)
+#define MCHP_VBAT_ROM_FEAT REG32(MCHP_VBAT_BASE + 0x28)
+#define MCHP_VBAT_EMB_DEBOUNCE_EN REG32(MCHP_VBAT_BASE + 0x34)
 /* read 32-bit word at 32-bit offset x where 0 <= x <= 32 */
-#define MCHP_VBAT_RAM_SIZE		128
-#define MCHP_VBAT_RAM(wnum)		\
-	REG32(MCHP_VBAT_RAM_BASE + ((wnum) * 4))
-#define MCHP_VBAT_RAM8(bnum)		\
-	REG8(MCHP_VBAT_RAM_BASE + (bnum))
-#define MCHP_VBAT_VWIRE_BACKUP		30
+#define MCHP_VBAT_RAM_SIZE 128
+#define MCHP_VBAT_RAM(wnum) REG32(MCHP_VBAT_RAM_BASE + ((wnum)*4))
+#define MCHP_VBAT_RAM8(bnum) REG8(MCHP_VBAT_RAM_BASE + (bnum))
+#define MCHP_VBAT_VWIRE_BACKUP 30
 /*
  * Miscellaneous firmware control fields
  * scratch pad index cannot be more than 32 as
  * MEC152x has 64 bytes = 16 words of scratch RAM
  */
-#define MCHP_IMAGETYPE_IDX	31
+#define MCHP_IMAGETYPE_IDX 31
 
 /* Bit definition for MCHP_VBAT_STS */
-#define MCHP_VBAT_STS_SOFTRESET		BIT(2)
-#define MCHP_VBAT_STS_RESETI		BIT(4)
-#define MCHP_VBAT_STS_WDT		BIT(5)
-#define MCHP_VBAT_STS_SYSRESETREQ	BIT(6)
-#define MCHP_VBAT_STS_VBAT_RST		BIT(7)
-#define MCHP_VBAT_STS_ANY_RST		0xF4u
+#define MCHP_VBAT_STS_SOFTRESET BIT(2)
+#define MCHP_VBAT_STS_RESETI BIT(4)
+#define MCHP_VBAT_STS_WDT BIT(5)
+#define MCHP_VBAT_STS_SYSRESETREQ BIT(6)
+#define MCHP_VBAT_STS_VBAT_RST BIT(7)
+#define MCHP_VBAT_STS_ANY_RST 0xF4u
 
 /* Bit definitions for MCHP_VBAT_CSS */
-#define MCHP_VBAT_CSS_SIL32K_EN		BIT(0)
-#define MCHP_VBAT_CSS_XTAL_EN		BIT(8)
-#define MCHP_VBAT_CSS_XTAL_SINGLE	BIT(9)
-#define MCHP_VBAT_CSS_XTAL_HSC_DIS	BIT(10)
-#define MCHP_VBAT_CSS_XTAL_CNT_POS	11
-#define MCHP_VBAT_CSS_XTAL_CNT_MASK	(0x03U << 11)
-#define MCHP_VBAT_CSS_SRC_POS		16
-#define MCHP_VBAT_CSS_SRC_MASK		(0x03U << 16)
-#define MCHP_VBAT_CSS_SRC_SIL_OSC	0
-#define MCHP_VBAT_CSS_SRC_XTAL		(1U << 16)
+#define MCHP_VBAT_CSS_SIL32K_EN BIT(0)
+#define MCHP_VBAT_CSS_XTAL_EN BIT(8)
+#define MCHP_VBAT_CSS_XTAL_SINGLE BIT(9)
+#define MCHP_VBAT_CSS_XTAL_HSC_DIS BIT(10)
+#define MCHP_VBAT_CSS_XTAL_CNT_POS 11
+#define MCHP_VBAT_CSS_XTAL_CNT_MASK (0x03U << 11)
+#define MCHP_VBAT_CSS_SRC_POS 16
+#define MCHP_VBAT_CSS_SRC_MASK (0x03U << 16)
+#define MCHP_VBAT_CSS_SRC_SIL_OSC 0
+#define MCHP_VBAT_CSS_SRC_XTAL (1U << 16)
 /* Switch from 32KHZ_IN input to silicon OSC when VTR goes down */
-#define MCHP_VBAT_CSS_SRC_SWPS		(2U << 16)
+#define MCHP_VBAT_CSS_SRC_SWPS (2U << 16)
 /* Switch from 32KHZ_IN input to XTAL on VBAT when VTR goes down */
-#define MCHP_VBAT_CSS_SRC_SWPX		(3U << 16)
+#define MCHP_VBAT_CSS_SRC_SWPX (3U << 16)
 /* Disable 32Khz silicon oscillator when VBAT goes off */
-#define MCHP_VBAT_CSS_NVB_SUPS		BIT(18)
+#define MCHP_VBAT_CSS_NVB_SUPS BIT(18)
 
 /* Blinking-Breathing LED 0 <= n <= 2 */
-#define MCHP_BBLEB_INSTANCES	4
-#define MCHP_BBLED_BASE(n)	(MCHP_BBLED_0_BASE + (((n) & 0x03) * 256))
+#define MCHP_BBLEB_INSTANCES 4
+#define MCHP_BBLED_BASE(n) (MCHP_BBLED_0_BASE + (((n)&0x03) * 256))
 
 /* EMI */
-#define MCHP_EMI_INSTANCES	3
-#define MCHP_EMI_SPACING	0x400
-#define MCHP_EMI_ECREG_OFS	0x100
+#define MCHP_EMI_INSTANCES 3
+#define MCHP_EMI_SPACING 0x400
+#define MCHP_EMI_ECREG_OFS 0x100
 /* base of EMI registers only accessible by EC */
 #define MCHP_EMI_BASE(n) \
-	(MCHP_EMI_0_BASE + MCHP_EMI_ECREG_OFS + ((n) * MCHP_EMI_SPACING))
+	(MCHP_EMI_0_BASE + MCHP_EMI_ECREG_OFS + ((n)*MCHP_EMI_SPACING))
 /* base of EMI registers accessible by EC and Host */
-#define MCHP_EMI_RT_BASE(n) (MCHP_EMI_0_BASE + ((n) * MCHP_EMI_SPACING))
-#define MCHP_EMI_GIRQ		15
-#define MCHP_EMI_GIRQ_BIT(n)	BIT(2 + (n))
+#define MCHP_EMI_RT_BASE(n) (MCHP_EMI_0_BASE + ((n)*MCHP_EMI_SPACING))
+#define MCHP_EMI_GIRQ 15
+#define MCHP_EMI_GIRQ_BIT(n) BIT(2 + (n))
 
 /* Mailbox */
-#define MCHP_MBX_ECREGS_OFS	0x100
-#define MCHP_MBX_RT_BASE	MCHP_MBOX_BASE
-#define MCHP_MBX_BASE		(MCHP_MBOX_BASE + MCHP_MBX_ECREGS_OFS)
-#define MCHP_MBX_GIRQ		15
-#define MCHP_MBX_GIRQ_BIT	BIT(20)
+#define MCHP_MBX_ECREGS_OFS 0x100
+#define MCHP_MBX_RT_BASE MCHP_MBOX_BASE
+#define MCHP_MBX_BASE (MCHP_MBOX_BASE + MCHP_MBX_ECREGS_OFS)
+#define MCHP_MBX_GIRQ 15
+#define MCHP_MBX_GIRQ_BIT BIT(20)
 
 /* MEC172x includes one instance of the BIOS Debug Port
  * capable of capturing Host I/O port 0x80 and 0x90 writes.
@@ -1034,130 +1028,128 @@
  * Read with 16 or 32 access guarantees attributes/status bits
  * correspond to data in bits[7:0].
  */
-#define MCHP_BDP0_HDATA		REG32(MCHP_BDP0_BASE)
-#define MCHP_BDP0_DATTR		REG16(MCHP_BDP0_BASE + 0x100)
-#define MCHP_BDP0_CONFIG	REG32(MCHP_BDP0_BASE + 0x104)
-#define MCHP_BDP0_STATUS	REG8(MCHP_BDP0_BASE + 0x108)
-#define MCHP_BDP0_INTR_EN	REG8(MCHP_BDP0_BASE + 0x109)
-#define MCHP_BDP0_STS_IEN	REG16(MCHP_BDP0_BASE + 0x108)
-#define MCHP_BDP0_SNAPSHOT	REG32(MCHP_BDP0_BASE + 0x10C)
-#define MCHP_BDP0_CAPTURE	REG32(MCHP_BDP0_BASE + 0x110)
-#define MCHP_BDP0_ACTV		REG8(MCHP_BDP0_BASE + 0x330)
-#define MCHP_BDP0_ALIAS_HDATA	REG8(MCHP_BDP0_BASE + 0x400)
-#define MCHP_BDP0_ALIAS_ACTV	REG8(MCHP_BDP0_BASE + 0x730)
-#define MCHP_BDP0_ALIAS_BLN	REG8(MCHP_BDP0_BASE + 0x7F0)
-
-#define MCHP_BDP0_GIRQ		15
-#define MCHP_BDP0_GIRQ_BIT	BIT(22)
+#define MCHP_BDP0_HDATA REG32(MCHP_BDP0_BASE)
+#define MCHP_BDP0_DATTR REG16(MCHP_BDP0_BASE + 0x100)
+#define MCHP_BDP0_CONFIG REG32(MCHP_BDP0_BASE + 0x104)
+#define MCHP_BDP0_STATUS REG8(MCHP_BDP0_BASE + 0x108)
+#define MCHP_BDP0_INTR_EN REG8(MCHP_BDP0_BASE + 0x109)
+#define MCHP_BDP0_STS_IEN REG16(MCHP_BDP0_BASE + 0x108)
+#define MCHP_BDP0_SNAPSHOT REG32(MCHP_BDP0_BASE + 0x10C)
+#define MCHP_BDP0_CAPTURE REG32(MCHP_BDP0_BASE + 0x110)
+#define MCHP_BDP0_ACTV REG8(MCHP_BDP0_BASE + 0x330)
+#define MCHP_BDP0_ALIAS_HDATA REG8(MCHP_BDP0_BASE + 0x400)
+#define MCHP_BDP0_ALIAS_ACTV REG8(MCHP_BDP0_BASE + 0x730)
+#define MCHP_BDP0_ALIAS_BLN REG8(MCHP_BDP0_BASE + 0x7F0)
+
+#define MCHP_BDP0_GIRQ 15
+#define MCHP_BDP0_GIRQ_BIT BIT(22)
 
 /* BDP DATATR as 16-bit value bit definitions */
-#define MCHP_BDP_DATTR_POS		0
-#define MCHP_BDP_DATTR_DATA_MASK	0xff
-#define MCHP_BDP_DATTR_LANE_POS		8
-#define MCHP_BDP_DATTR_LANE_MASK	GENMASK(9, 8)
-#define MCHP_BDP_DATTR_LANE_0		0
-#define MCHP_BDP_DATTR_LANE_1		(1U << 8)
-#define MCHP_BDP_DATTR_LANE_2		(2U << 8)
-#define MCHP_BDP_DATTR_LANE_3		(3U << 8)
-#define MCHP_BDP_DATTR_LEN_POS		10
-#define MCHP_BDP_DATTR_LEN_MASK		GENMASK(11, 10)
-#define MCHP_BDP_DATTR_LEN_1		0
-#define MCHP_BDP_DATTR_LEN_2		(1U << 10)
-#define MCHP_BDP_DATTR_LEN_4		(2U << 10)
-#define MCHP_BDP_DATTR_LEN_INVAL	(3U << 10)
-#define MCHP_BDP_DATTR_NE		BIT(12)
-#define MCHP_BDP_DATTR_OVR		BIT(13)
-#define MCHP_BDP_DATTR_THRH		BIT(14)
+#define MCHP_BDP_DATTR_POS 0
+#define MCHP_BDP_DATTR_DATA_MASK 0xff
+#define MCHP_BDP_DATTR_LANE_POS 8
+#define MCHP_BDP_DATTR_LANE_MASK GENMASK(9, 8)
+#define MCHP_BDP_DATTR_LANE_0 0
+#define MCHP_BDP_DATTR_LANE_1 (1U << 8)
+#define MCHP_BDP_DATTR_LANE_2 (2U << 8)
+#define MCHP_BDP_DATTR_LANE_3 (3U << 8)
+#define MCHP_BDP_DATTR_LEN_POS 10
+#define MCHP_BDP_DATTR_LEN_MASK GENMASK(11, 10)
+#define MCHP_BDP_DATTR_LEN_1 0
+#define MCHP_BDP_DATTR_LEN_2 (1U << 10)
+#define MCHP_BDP_DATTR_LEN_4 (2U << 10)
+#define MCHP_BDP_DATTR_LEN_INVAL (3U << 10)
+#define MCHP_BDP_DATTR_NE BIT(12)
+#define MCHP_BDP_DATTR_OVR BIT(13)
+#define MCHP_BDP_DATTR_THRH BIT(14)
 
 /* BDP Configuration */
-#define MCHP_BDP_CFG_FLUSH_FIFO		BIT(0)
-#define MCHP_BDP_CFG_SNAPSHOT_CLR	BIT(1)
-#define MCHP_BDP_CFG_FIFO_THRH_POS	8
-#define MCHP_BDP_CFG_FIFO_THRH_1	0
-#define MCHP_BDP_CFG_FIFO_THRH_4	(1U << 8)
-#define MCHP_BDP_CFG_FIFO_THRH_8	(2U << 8)
-#define MCHP_BDP_CFG_FIFO_THRH_16	(3U << 8)
-#define MCHP_BDP_CFG_FIFO_THRH_20	(4U << 8)
-#define MCHP_BDP_CFG_FIFO_THRH_24	(5U << 8)
-#define MCHP_BDP_CFG_FIFO_THRH_28	(6U << 8)
-#define MCHP_BDP_CFG_FIFO_THRH_30	(7U << 8)
-#define MCHP_BDP_CFG_SRST		BIT(31)
+#define MCHP_BDP_CFG_FLUSH_FIFO BIT(0)
+#define MCHP_BDP_CFG_SNAPSHOT_CLR BIT(1)
+#define MCHP_BDP_CFG_FIFO_THRH_POS 8
+#define MCHP_BDP_CFG_FIFO_THRH_1 0
+#define MCHP_BDP_CFG_FIFO_THRH_4 (1U << 8)
+#define MCHP_BDP_CFG_FIFO_THRH_8 (2U << 8)
+#define MCHP_BDP_CFG_FIFO_THRH_16 (3U << 8)
+#define MCHP_BDP_CFG_FIFO_THRH_20 (4U << 8)
+#define MCHP_BDP_CFG_FIFO_THRH_24 (5U << 8)
+#define MCHP_BDP_CFG_FIFO_THRH_28 (6U << 8)
+#define MCHP_BDP_CFG_FIFO_THRH_30 (7U << 8)
+#define MCHP_BDP_CFG_SRST BIT(31)
 
 /* BDP Status */
-#define MCHP_BDP_STATUS_MASK		GENMASK(2, 0)
-#define MCHP_BDP_STATUS_NOT_EMPTY	BIT(0)
-#define MCHP_BDP_STATUS_OVERRUN		BIT(1)
-#define MCHP_BDP_STATUS_THRH		BIT(2)
+#define MCHP_BDP_STATUS_MASK GENMASK(2, 0)
+#define MCHP_BDP_STATUS_NOT_EMPTY BIT(0)
+#define MCHP_BDP_STATUS_OVERRUN BIT(1)
+#define MCHP_BDP_STATUS_THRH BIT(2)
 
 /* BDP Interrupt enable */
-#define MCHP_BDP_IEN_THRH		BIT(0)
+#define MCHP_BDP_IEN_THRH BIT(0)
 
 /* PWM SZ 144 pin package has 9 PWM's */
-#define MCHP_PWM_INSTANCES		9
-#define MCHP_PWM_ID_MAX			(MCHP_PWM_INSTANCES)
-#define MCHP_PWM_SPACING		16
-#define MCHP_PWM_BASE(x) (MCHP_PWM_0_BASE + ((x) * MCHP_PWM_SPACING))
+#define MCHP_PWM_INSTANCES 9
+#define MCHP_PWM_ID_MAX (MCHP_PWM_INSTANCES)
+#define MCHP_PWM_SPACING 16
+#define MCHP_PWM_BASE(x) (MCHP_PWM_0_BASE + ((x)*MCHP_PWM_SPACING))
 
 /* TACH */
-#define MCHP_TACH_INSTANCES	4
-#define MCHP_TACH_SPACING	16
-#define MCHP_TACH_BASE(x) (MCHP_TACH_0_BASE + ((x) * MCHP_TACH_SPACING))
-#define MCHP_TACH_GIRQ		17
-#define MCHP_TACH_GIRQ_BIT(x)	BIT(1 + (x))
+#define MCHP_TACH_INSTANCES 4
+#define MCHP_TACH_SPACING 16
+#define MCHP_TACH_BASE(x) (MCHP_TACH_0_BASE + ((x)*MCHP_TACH_SPACING))
+#define MCHP_TACH_GIRQ 17
+#define MCHP_TACH_GIRQ_BIT(x) BIT(1 + (x))
 
 /* FAN */
-#define MCHP_FAN_INSTANCES	2
-#define MCHP_FAN_SPACING	0x80U
-#define MCHP_FAN_BASE(x)	\
-	(MCHP_RPM2PWM0_BASE + ((x) * MCHP_FAN_SPACING))
-#define MCHP_FAN_SETTING(x)	REG16(MCHP_FAN_BASE(x) + 0x0)
-#define MCHP_FAN_CFG1(x)	REG8(MCHP_FAN_BASE(x) + 0x2)
-#define MCHP_FAN_CFG2(x)	REG8(MCHP_FAN_BASE(x) + 0x3)
-#define MCHP_FAN_PWM_DIVIDE(x)	REG8(MCHP_FAN_BASE(x) + 0x4)
-#define MCHP_FAN_GAIN(x)	REG8(MCHP_FAN_BASE(x) + 0x5)
-#define MCHP_FAN_SPIN_UP(x)	REG8(MCHP_FAN_BASE(x) + 0x6)
-#define MCHP_FAN_STEP(x)	REG8(MCHP_FAN_BASE(x) + 0x7)
-#define MCHP_FAN_MIN_DRV(x)	REG8(MCHP_FAN_BASE(x) + 0x8)
-#define MCHP_FAN_VALID_CNT(x)	REG8(MCHP_FAN_BASE(x) + 0x9)
-#define MCHP_FAN_DRV_FAIL(x)	REG16(MCHP_FAN_BASE(x) + 0xa)
-#define MCHP_FAN_TARGET(x)	REG16(MCHP_FAN_BASE(x) + 0xc)
-#define MCHP_FAN_READING(x)	REG16(MCHP_FAN_BASE(x) + 0xe)
-#define MCHP_FAN_BASE_FREQ(x)	REG8(MCHP_FAN_BASE(x) + 0x10)
-#define MCHP_FAN_STATUS(x)	REG8(MCHP_FAN_BASE(x) + 0x11)
+#define MCHP_FAN_INSTANCES 2
+#define MCHP_FAN_SPACING 0x80U
+#define MCHP_FAN_BASE(x) (MCHP_RPM2PWM0_BASE + ((x)*MCHP_FAN_SPACING))
+#define MCHP_FAN_SETTING(x) REG16(MCHP_FAN_BASE(x) + 0x0)
+#define MCHP_FAN_CFG1(x) REG8(MCHP_FAN_BASE(x) + 0x2)
+#define MCHP_FAN_CFG2(x) REG8(MCHP_FAN_BASE(x) + 0x3)
+#define MCHP_FAN_PWM_DIVIDE(x) REG8(MCHP_FAN_BASE(x) + 0x4)
+#define MCHP_FAN_GAIN(x) REG8(MCHP_FAN_BASE(x) + 0x5)
+#define MCHP_FAN_SPIN_UP(x) REG8(MCHP_FAN_BASE(x) + 0x6)
+#define MCHP_FAN_STEP(x) REG8(MCHP_FAN_BASE(x) + 0x7)
+#define MCHP_FAN_MIN_DRV(x) REG8(MCHP_FAN_BASE(x) + 0x8)
+#define MCHP_FAN_VALID_CNT(x) REG8(MCHP_FAN_BASE(x) + 0x9)
+#define MCHP_FAN_DRV_FAIL(x) REG16(MCHP_FAN_BASE(x) + 0xa)
+#define MCHP_FAN_TARGET(x) REG16(MCHP_FAN_BASE(x) + 0xc)
+#define MCHP_FAN_READING(x) REG16(MCHP_FAN_BASE(x) + 0xe)
+#define MCHP_FAN_BASE_FREQ(x) REG8(MCHP_FAN_BASE(x) + 0x10)
+#define MCHP_FAN_STATUS(x) REG8(MCHP_FAN_BASE(x) + 0x11)
 
 /* ACPI EC */
-#define MCHP_ACPI_EC_INSTANCES		5
-#define MCHP_ACPI_EC_MAX		(MCHP_ACPI_EC_INSTANCES)
-#define MCHP_ACPI_EC_SPACING		0x400
-#define MCHP_ACPI_EC_BASE(x) \
-	(MCHP_ACPI_EC_0_BASE + ((x) * MCHP_ACPI_EC_SPACING))
-#define MCHP_ACPI_EC_GIRQ		15
-#define MCHP_ACPI_EC_IBF_GIRQ_BIT(x)	BIT(5 + ((x) * 2))
-#define MCHP_ACPI_EC_OBE_GIRQ_BIT(x)	BIT(6 + ((x) * 2))
+#define MCHP_ACPI_EC_INSTANCES 5
+#define MCHP_ACPI_EC_MAX (MCHP_ACPI_EC_INSTANCES)
+#define MCHP_ACPI_EC_SPACING 0x400
+#define MCHP_ACPI_EC_BASE(x) (MCHP_ACPI_EC_0_BASE + ((x)*MCHP_ACPI_EC_SPACING))
+#define MCHP_ACPI_EC_GIRQ 15
+#define MCHP_ACPI_EC_IBF_GIRQ_BIT(x) BIT(5 + ((x)*2))
+#define MCHP_ACPI_EC_OBE_GIRQ_BIT(x) BIT(6 + ((x)*2))
 
 /* ACPI PM1 */
-#define MCHP_ACPI_PM1_ECREGS_OFS	0x100
-#define MCHP_ACPI_PM_RT_BASE		MCHP_ACPI_PM1_BASE
-#define MCHP_ACPI_PM_EC_BASE	(MCHP_ACPI_PM1_BASE + MCHP_ACPI_PM1_ECREGS_OFS)
-#define MCHP_ACPI_PM1_CTL_GIRQ_BIT	BIT(15)
-#define MCHP_ACPI_PM1_EN_GIRQ_BIT	BIT(16)
-#define MCHP_ACPI_PM1_STS_GIRQ_BIT	BIT(17)
+#define MCHP_ACPI_PM1_ECREGS_OFS 0x100
+#define MCHP_ACPI_PM_RT_BASE MCHP_ACPI_PM1_BASE
+#define MCHP_ACPI_PM_EC_BASE (MCHP_ACPI_PM1_BASE + MCHP_ACPI_PM1_ECREGS_OFS)
+#define MCHP_ACPI_PM1_CTL_GIRQ_BIT BIT(15)
+#define MCHP_ACPI_PM1_EN_GIRQ_BIT BIT(16)
+#define MCHP_ACPI_PM1_STS_GIRQ_BIT BIT(17)
 
 /* 8042 */
-#define MCHP_8042_ECREGS_OFS		0x100
-#define MCHP_8042_GIRQ			15
-#define MCHP_8042_OBE_GIRQ_BIT		BIT(18)
-#define MCHP_8042_IBF_GIRQ_BIT		BIT(19)
+#define MCHP_8042_ECREGS_OFS 0x100
+#define MCHP_8042_GIRQ 15
+#define MCHP_8042_OBE_GIRQ_BIT BIT(18)
+#define MCHP_8042_IBF_GIRQ_BIT BIT(19)
 
 /* I2C controllers 0 - 4 include SMBus network layer functionality. */
-#define MCHP_I2C_CTRL0		0
-#define MCHP_I2C_CTRL1		1
-#define MCHP_I2C_CTRL2		2
-#define MCHP_I2C_CTRL3		3
-#define MCHP_I2C_CTRL4		4
-#define MCHP_I2C_CTRL_MAX	5
+#define MCHP_I2C_CTRL0 0
+#define MCHP_I2C_CTRL1 1
+#define MCHP_I2C_CTRL2 2
+#define MCHP_I2C_CTRL3 3
+#define MCHP_I2C_CTRL4 4
+#define MCHP_I2C_CTRL_MAX 5
 
-#define MCHP_I2C_SEP0		0x400
+#define MCHP_I2C_SEP0 0x400
 
 /*
  * MEC172x SZ(144-pin) package implements 15 ports. No Port 11.
@@ -1169,8 +1161,8 @@
  * of port to controller.
  * Locking must occur by-controller (not by-port).
  */
-#if (defined(CHIP_VARIANT_MEC1721LJ) || defined(CHIP_VARIANT_MEC1723LJ)\
-		|| defined(CHIP_VARIANT_MEC1727LJ))
+#if (defined(CHIP_VARIANT_MEC1721LJ) || defined(CHIP_VARIANT_MEC1723LJ) || \
+     defined(CHIP_VARIANT_MEC1727LJ))
 #define MCHP_I2C_PORT_MASK GENMASK(15, 0)
 #else
 #define MCHP_I2C_PORT_MASK (GENMASK(15, 0) & ~BIT(11))
@@ -1196,83 +1188,83 @@ enum MCHP_i2c_port {
 };
 
 /* I2C ports & Configs */
-#define I2C_CONTROLLER_COUNT	MCHP_I2C_CTRL_MAX
-#define I2C_PORT_COUNT		MCHP_I2C_PORT_COUNT
+#define I2C_CONTROLLER_COUNT MCHP_I2C_CTRL_MAX
+#define I2C_PORT_COUNT MCHP_I2C_PORT_COUNT
 
 /* All I2C controllers connected to GIRQ13 */
-#define MCHP_I2C_GIRQ		13
+#define MCHP_I2C_GIRQ 13
 /* I2C[0:7] -> GIRQ13 bits[0:7] */
-#define MCHP_I2C_GIRQ_BIT(n)	BIT((n))
+#define MCHP_I2C_GIRQ_BIT(n) BIT((n))
 
 /* Keyboard scan matrix */
-#define MCHP_KS_GIRQ		21
-#define MCHP_KS_GIRQ_BIT	BIT(25)
-#define MCHP_KS_DIRECT_NVIC	135
+#define MCHP_KS_GIRQ 21
+#define MCHP_KS_GIRQ_BIT BIT(25)
+#define MCHP_KS_DIRECT_NVIC 135
 
 /* ADC */
-#if (defined(CHIP_VARIANT_MEC1721LJ) || defined(CHIP_VARIANT_MEC1723LJ)\
-		|| defined(CHIP_VARIANT_MEC1727LJ))
+#if (defined(CHIP_VARIANT_MEC1721LJ) || defined(CHIP_VARIANT_MEC1723LJ) || \
+     defined(CHIP_VARIANT_MEC1727LJ))
 #define MCHP_ADC_CHAN_MASK GENMASK(15, 0)
 #else
 #define MCHP_ADC_CHAN_MASK GENMASK(7, 0)
 #endif
-#define MCHP_ADC_GIRQ			17
-#define MCHP_ADC_GIRQ_SINGLE_BIT	BIT(8)
-#define MCHP_ADC_GIRQ_REPEAT_BIT	BIT(9)
-#define MCHP_ADC_SINGLE_DIRECT_NVIC	78
-#define MCHP_ADC_REPEAT_DIRECT_NVIC	79
-#define MCHP_ADC_CONFIG			REG32(MCHP_ADC_BASE + 0x7c)
-#define MCHP_ADC_CONFIG_DFLT		0x0101U
-#define MCHP_ADC_CFG_CLK_LO_TM_MSK	GENMASK(7, 0)
-#define MCHP_ADC_CFG_CLK_HI_TM_MSK	GENMASK(15, 8)
-#define MCHP_ADC_VREF_CSEL		REG32(MCHP_ADC_BASE + 0x80)
-#define MCHP_ADC_VREF_CSEL_MSK(ch)	(0x03U << ((ch) * 2U))
-#define MCHP_ADC_VREF_CSEL_GPIO(ch)	BIT((ch) * 2U)
-#define MCHP_ADC_VREF_CTRL		REG32(MCHP_ADC_BASE + 0x84)
-#define MCHP_ADC_VREF_CTRL_DFLT		0U
-#define MCHP_ADC_VCTRL_CHRG_DLY_MSK	GENMASK(15, 0)
-#define MCHP_ADC_VCTRL_SW_DLY_MSK	GENMASK(28, 16)
-#define MCHP_ADC_VCTRL_DRV_UNUSED_LO	BIT(29)
-#define MCHP_ADC_VCTRL_SEL_STS_RO_POS	30
-#define MCHP_ADC_VCTRL_SEL_STS_RO_MSK	GENMASK(31, 30)
-#define MCHP_ADC_SAR_ADC_CTRL		REG32(MCHP_ADC_BASE + 0x88)
-#define MCHP_ADC_SAR_ADC_CTRL_DFLT	((0x202U << 7) | (0x03U << 1))
-#define MCHP_ADC_SAC_DIFF_INPUT		BIT(0)
-#define MCHP_ADC_SAC_RES_POS		1
-#define MCHP_ADC_SAC_RES_MSK		GENMASK(2, 1)
-#define MCHP_ADC_SAC_RES_10BIT		(2U << 1)
-#define MCHP_ADC_SAC_RES_12BIT		(3U << 1)
-#define MCHP_ADC_SAC_RJ_10BIT		BIT(3)
-#define MCHP_ADC_SAC_WU_DLY_POS		7
-#define MCHP_ADC_SAC_WU_DLY_MSK		GENMASK(16, 7)
-#define MCHP_ADC_SAC_WU_DLY_DLFT	(0x202U << 7)
+#define MCHP_ADC_GIRQ 17
+#define MCHP_ADC_GIRQ_SINGLE_BIT BIT(8)
+#define MCHP_ADC_GIRQ_REPEAT_BIT BIT(9)
+#define MCHP_ADC_SINGLE_DIRECT_NVIC 78
+#define MCHP_ADC_REPEAT_DIRECT_NVIC 79
+#define MCHP_ADC_CONFIG REG32(MCHP_ADC_BASE + 0x7c)
+#define MCHP_ADC_CONFIG_DFLT 0x0101U
+#define MCHP_ADC_CFG_CLK_LO_TM_MSK GENMASK(7, 0)
+#define MCHP_ADC_CFG_CLK_HI_TM_MSK GENMASK(15, 8)
+#define MCHP_ADC_VREF_CSEL REG32(MCHP_ADC_BASE + 0x80)
+#define MCHP_ADC_VREF_CSEL_MSK(ch) (0x03U << ((ch)*2U))
+#define MCHP_ADC_VREF_CSEL_GPIO(ch) BIT((ch)*2U)
+#define MCHP_ADC_VREF_CTRL REG32(MCHP_ADC_BASE + 0x84)
+#define MCHP_ADC_VREF_CTRL_DFLT 0U
+#define MCHP_ADC_VCTRL_CHRG_DLY_MSK GENMASK(15, 0)
+#define MCHP_ADC_VCTRL_SW_DLY_MSK GENMASK(28, 16)
+#define MCHP_ADC_VCTRL_DRV_UNUSED_LO BIT(29)
+#define MCHP_ADC_VCTRL_SEL_STS_RO_POS 30
+#define MCHP_ADC_VCTRL_SEL_STS_RO_MSK GENMASK(31, 30)
+#define MCHP_ADC_SAR_ADC_CTRL REG32(MCHP_ADC_BASE + 0x88)
+#define MCHP_ADC_SAR_ADC_CTRL_DFLT ((0x202U << 7) | (0x03U << 1))
+#define MCHP_ADC_SAC_DIFF_INPUT BIT(0)
+#define MCHP_ADC_SAC_RES_POS 1
+#define MCHP_ADC_SAC_RES_MSK GENMASK(2, 1)
+#define MCHP_ADC_SAC_RES_10BIT (2U << 1)
+#define MCHP_ADC_SAC_RES_12BIT (3U << 1)
+#define MCHP_ADC_SAC_RJ_10BIT BIT(3)
+#define MCHP_ADC_SAC_WU_DLY_POS 7
+#define MCHP_ADC_SAC_WU_DLY_MSK GENMASK(16, 7)
+#define MCHP_ADC_SAC_WU_DLY_DLFT (0x202U << 7)
 
 /* Hibernation timer */
-#define MCHP_HTIMER_SPACING		0x20
-#define MCHP_HTIMER_ADDR(n) (MCHP_HTIMER_BASE + ((n) * MCHP_HTIMER_SPACING))
-#define MCHP_HTIMER_GIRQ		21
+#define MCHP_HTIMER_SPACING 0x20
+#define MCHP_HTIMER_ADDR(n) (MCHP_HTIMER_BASE + ((n)*MCHP_HTIMER_SPACING))
+#define MCHP_HTIMER_GIRQ 21
 /* HTIMER[0:1] -> GIRQ21 bits[1:2] */
-#define MCHP_HTIMER_GIRQ_BIT(n)		BIT(1 + (n))
-#define MCHP_HTIMER_DIRECT_NVIC(n)	(112 + (n))
+#define MCHP_HTIMER_GIRQ_BIT(n) BIT(1 + (n))
+#define MCHP_HTIMER_DIRECT_NVIC(n) (112 + (n))
 
 /* General Purpose SPI (GP-SPI) */
-#define MCHP_SPI_BASE(port) (MCHP_GPSPI0_BASE + ((port) * 0x80))
-#define MCHP_SPI_AR(port)	REG8(MCHP_SPI_BASE(port) + 0x00)
-#define MCHP_SPI_CR(port)	REG8(MCHP_SPI_BASE(port) + 0x04)
-#define MCHP_SPI_SR(port)	REG8(MCHP_SPI_BASE(port) + 0x08)
-#define MCHP_SPI_TD(port)	REG8(MCHP_SPI_BASE(port) + 0x0c)
-#define MCHP_SPI_RD(port)	REG8(MCHP_SPI_BASE(port) + 0x10)
-#define MCHP_SPI_CC(port)	REG8(MCHP_SPI_BASE(port) + 0x14)
-#define MCHP_SPI_CG(port)	REG8(MCHP_SPI_BASE(port) + 0x18)
+#define MCHP_SPI_BASE(port) (MCHP_GPSPI0_BASE + ((port)*0x80))
+#define MCHP_SPI_AR(port) REG8(MCHP_SPI_BASE(port) + 0x00)
+#define MCHP_SPI_CR(port) REG8(MCHP_SPI_BASE(port) + 0x04)
+#define MCHP_SPI_SR(port) REG8(MCHP_SPI_BASE(port) + 0x08)
+#define MCHP_SPI_TD(port) REG8(MCHP_SPI_BASE(port) + 0x0c)
+#define MCHP_SPI_RD(port) REG8(MCHP_SPI_BASE(port) + 0x10)
+#define MCHP_SPI_CC(port) REG8(MCHP_SPI_BASE(port) + 0x14)
+#define MCHP_SPI_CG(port) REG8(MCHP_SPI_BASE(port) + 0x18)
 /* Addresses of TX/RX register used in tables */
-#define MCHP_SPI_TD_ADDR(ctrl)	(MCHP_SPI_BASE(ctrl) + 0x0c)
-#define MCHP_SPI_RD_ADDR(ctrl)	(MCHP_SPI_BASE(ctrl) + 0x10)
+#define MCHP_SPI_TD_ADDR(ctrl) (MCHP_SPI_BASE(ctrl) + 0x0c)
+#define MCHP_SPI_RD_ADDR(ctrl) (MCHP_SPI_BASE(ctrl) + 0x10)
 /* All GP-SPI controllers connected to GIRQ18 */
-#define MCHP_SPI_GIRQ			18
-#define MCHP_SPI_GIRQ_TXBE_BIT(x)	BIT(2 + ((x) * 2))
-#define MCHP_SPI_GIRQ_RXBF_BIT(x)	BIT(3 + ((x) * 2))
-#define MCHP_GPSPI0_ID			0
-#define MCHP_GPSPI1_ID			1
+#define MCHP_SPI_GIRQ 18
+#define MCHP_SPI_GIRQ_TXBE_BIT(x) BIT(2 + ((x)*2))
+#define MCHP_SPI_GIRQ_RXBF_BIT(x) BIT(3 + ((x)*2))
+#define MCHP_GPSPI0_ID 0
+#define MCHP_GPSPI1_ID 1
 
 /*
  * Quad Master SPI (QMSPI)
@@ -1280,43 +1272,43 @@ enum MCHP_i2c_port {
  * chip select timing and a local DMA unit with 3 RX channels and
  * 3 TX channels. It retains support of the legacy DMA block.
  */
-#define MCHP_QMSPI_MAX_DESCR	16
-#define MCHP_QMSPI_GIRQ		18
-#define MCHP_QMSPI_GIRQ_BIT	BIT(1)
+#define MCHP_QMSPI_MAX_DESCR 16
+#define MCHP_QMSPI_GIRQ 18
+#define MCHP_QMSPI_GIRQ_BIT BIT(1)
 #define MCHP_QMSPI_DIRECT_NVIC 91
 /* SAF DMA mode when QMSPI when eSPI SAF is enabled */
-#define MCHP_QMSPI_M_SAF_EN	BIT(2)
+#define MCHP_QMSPI_M_SAF_EN BIT(2)
 /* Local DMA enables in Mode register */
-#define MCHP_QMSPI_M_LDRX_EN	BIT(3)
-#define MCHP_QMSPI_M_LDTX_EN	BIT(4)
+#define MCHP_QMSPI_M_LDRX_EN BIT(3)
+#define MCHP_QMSPI_M_LDTX_EN BIT(4)
 /* Chip select implemented in bit[13:12] of the Mode register. */
-#define MCHP_QMSPI_M_CS_POS	12
-#define MCHP_QMSPI_M_CS_MASK0	0x03
-#define MCHP_QMSPI_M_CS_MASK	GENMASK(13, 12)
-#define MCHP_QMSPI_M_CS0	0U
-#define MCHP_QMSPI_M_CS1	BIT(12)
+#define MCHP_QMSPI_M_CS_POS 12
+#define MCHP_QMSPI_M_CS_MASK0 0x03
+#define MCHP_QMSPI_M_CS_MASK GENMASK(13, 12)
+#define MCHP_QMSPI_M_CS0 0U
+#define MCHP_QMSPI_M_CS1 BIT(12)
 /* QMSPI alternate clock divider when CS1 is active. */
-#define MCHP_QMSPI0_ALTM	REG32(MCHP_QMSPI0_BASE + 0xc0)
-#define MCHP_QMSPI0_ALTM_EN	BIT(0)
+#define MCHP_QMSPI0_ALTM REG32(MCHP_QMSPI0_BASE + 0xc0)
+#define MCHP_QMSPI0_ALTM_EN BIT(0)
 /* QMSPI taps select */
-#define MCHP_QMSPI0_TAPS		REG32(MCHP_QMSPI0_BASE + 0xd0)
+#define MCHP_QMSPI0_TAPS REG32(MCHP_QMSPI0_BASE + 0xd0)
 /* QMSPI Taps adjust */
-#define MCHP_QMSPI0_TAPS_ADJ		REG32(MCHP_QMSPI0_BASE + 0xd4)
-#define MCHP_QMSPI0_TAPS_SCK_POS	0
-#define MCHP_QMSPI0_TAPS_SCK_MSK	GENMASK(7, 0)
-#define MCHP_QMSPI0_TAPS_CTL_POS	8
-#define MCHP_QMSPI0_TAPS_CTL_MSK	GENMASK(15, 8)
+#define MCHP_QMSPI0_TAPS_ADJ REG32(MCHP_QMSPI0_BASE + 0xd4)
+#define MCHP_QMSPI0_TAPS_SCK_POS 0
+#define MCHP_QMSPI0_TAPS_SCK_MSK GENMASK(7, 0)
+#define MCHP_QMSPI0_TAPS_CTL_POS 8
+#define MCHP_QMSPI0_TAPS_CTL_MSK GENMASK(15, 8)
 /* QMSPI Taps control */
-#define MCHP_QMSPI0_TAPS_CTRL		REG32(MCHP_QMSPI0_BASE + 0xd4)
-#define MCHP_QMSPI0_TAPS_CTRL_MODE_POS	0
-#define MCHP_QMSPI0_TAPS_CTRL_MODE_MSK	GENMASK(1, 0)
-#define MCHP_QMSPI0_TAPS_CTRL_UPDATE	BIT(2)
-#define MCHP_QMSPI0_TAPS_CTRL_GO	BIT(8)
-#define MCHP_QMSPI0_TAPS_CTRL_MULT_POS	16
-#define MCHP_QMSPI0_TAPS_CTRL_MULT_MSK	GENMASK(18, 16)
+#define MCHP_QMSPI0_TAPS_CTRL REG32(MCHP_QMSPI0_BASE + 0xd4)
+#define MCHP_QMSPI0_TAPS_CTRL_MODE_POS 0
+#define MCHP_QMSPI0_TAPS_CTRL_MODE_MSK GENMASK(1, 0)
+#define MCHP_QMSPI0_TAPS_CTRL_UPDATE BIT(2)
+#define MCHP_QMSPI0_TAPS_CTRL_GO BIT(8)
+#define MCHP_QMSPI0_TAPS_CTRL_MULT_POS 16
+#define MCHP_QMSPI0_TAPS_CTRL_MULT_MSK GENMASK(18, 16)
 /* QMSPI LDMA descriptor enables */
-#define MCHP_QMSPI0_LDRX_DEN	REG32(MCHP_QMSPI0_BASE + 0x100)
-#define MCHP_QMSPI0_LDTX_DEN	REG32(MCHP_QMSPI0_BASE + 0x104)
+#define MCHP_QMSPI0_LDRX_DEN REG32(MCHP_QMSPI0_BASE + 0x100)
+#define MCHP_QMSPI0_LDTX_DEN REG32(MCHP_QMSPI0_BASE + 0x104)
 /*
  * QMSPI LDMA channel registers.
  * Each channel implement 3 32-bit registers:
@@ -1331,74 +1323,74 @@ enum MCHP_i2c_port {
 #define MCHP_QMSPI0_LDTX_MBASE(n) REG32(MCHP_QMSPI0_BASE + 0x144 + ((n)*16U))
 #define MCHP_QMSPI0_LDTX_LEN(n) REG32(MCHP_QMSPI0_BASE + 0x148 + ((n)*16U))
 /* LDMA RX or TX channel control register */
-#define MCHP_QMSPI_LDC_MSK		GENMASK(6, 0)
-#define MCHP_QMSPI_LDC_EN		BIT(0)
-#define MCHP_QMSPI_LDC_RSTART_EN	BIT(1)
-#define MCHP_QMSPI_LDC_RSTART_MA_EN	BIT(2)
-#define MCHP_QMSPI_LDC_LEN_EN		BIT(3)
-#define MCHP_QMSPI_LDC_ACC_SZ_POS	4
-#define MCHP_QMSPI_LDC_ACC_SZ_MSK	GENMASK(5, 4)
-#define MCHP_QMSPI_LDC_ACC_1BYTE	0
-#define MCHP_QMSPI_LDC_ACC_2BYTES	(1U << 4)
-#define MCHP_QMSPI_LDC_ACC_4BYTES	(2U << 4)
-#define MCHP_QMSPI_LDC_INCR_ADDR	BIT(6)
+#define MCHP_QMSPI_LDC_MSK GENMASK(6, 0)
+#define MCHP_QMSPI_LDC_EN BIT(0)
+#define MCHP_QMSPI_LDC_RSTART_EN BIT(1)
+#define MCHP_QMSPI_LDC_RSTART_MA_EN BIT(2)
+#define MCHP_QMSPI_LDC_LEN_EN BIT(3)
+#define MCHP_QMSPI_LDC_ACC_SZ_POS 4
+#define MCHP_QMSPI_LDC_ACC_SZ_MSK GENMASK(5, 4)
+#define MCHP_QMSPI_LDC_ACC_1BYTE 0
+#define MCHP_QMSPI_LDC_ACC_2BYTES (1U << 4)
+#define MCHP_QMSPI_LDC_ACC_4BYTES (2U << 4)
+#define MCHP_QMSPI_LDC_INCR_ADDR BIT(6)
 
 /* eSPI */
 /* IO BAR defines. Use with MCHP_ESPI_IO_BAR_xxxx macros */
-#define MCHP_ESPI_IO_BAR_ID_CFG_PORT	0
-#define MCHP_ESPI_IO_BAR_ID_MEM_CMPNT	1
-#define MCHP_ESPI_IO_BAR_ID_MAILBOX	2
-#define MCHP_ESPI_IO_BAR_ID_8042	3
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC0	4
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC1	5
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC2	6
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC3	7
-#define MCHP_ESPI_IO_BAR_ID_ACPI_EC4	8
-#define MCHP_ESPI_IO_BAR_ID_ACPI_PM1	9
-#define MCHP_ESPI_IO_BAR_ID_P92		0xA
-#define MCHP_ESPI_IO_BAR_ID_UART0	0xB
-#define MCHP_ESPI_IO_BAR_ID_UART1	0xC
-#define MCHP_ESPI_IO_BAR_ID_EMI0	0xD
-#define MCHP_ESPI_IO_BAR_ID_EMI1	0xE
-#define MCHP_ESPI_IO_BAR_ID_EMI2	0xF
-#define MCHP_ESPI_IO_BAR_BDP0		0x10
-#define MCHP_ESPI_IO_BAR_BDP0_ALT	0x11
-#define MCHP_ESPI_IO_BAR_RTC		0x12
-#define MCHP_ESPI_IO_BAR_TB32		0x14
-#define MCHP_ESPI_IO_BAR_GLUE		0x16
+#define MCHP_ESPI_IO_BAR_ID_CFG_PORT 0
+#define MCHP_ESPI_IO_BAR_ID_MEM_CMPNT 1
+#define MCHP_ESPI_IO_BAR_ID_MAILBOX 2
+#define MCHP_ESPI_IO_BAR_ID_8042 3
+#define MCHP_ESPI_IO_BAR_ID_ACPI_EC0 4
+#define MCHP_ESPI_IO_BAR_ID_ACPI_EC1 5
+#define MCHP_ESPI_IO_BAR_ID_ACPI_EC2 6
+#define MCHP_ESPI_IO_BAR_ID_ACPI_EC3 7
+#define MCHP_ESPI_IO_BAR_ID_ACPI_EC4 8
+#define MCHP_ESPI_IO_BAR_ID_ACPI_PM1 9
+#define MCHP_ESPI_IO_BAR_ID_P92 0xA
+#define MCHP_ESPI_IO_BAR_ID_UART0 0xB
+#define MCHP_ESPI_IO_BAR_ID_UART1 0xC
+#define MCHP_ESPI_IO_BAR_ID_EMI0 0xD
+#define MCHP_ESPI_IO_BAR_ID_EMI1 0xE
+#define MCHP_ESPI_IO_BAR_ID_EMI2 0xF
+#define MCHP_ESPI_IO_BAR_BDP0 0x10
+#define MCHP_ESPI_IO_BAR_BDP0_ALT 0x11
+#define MCHP_ESPI_IO_BAR_RTC 0x12
+#define MCHP_ESPI_IO_BAR_TB32 0x14
+#define MCHP_ESPI_IO_BAR_GLUE 0x16
 
 /* Use with MCHP_ESPI_MBAR_EC_xxxx(x) macros */
-#define MCHP_ESPI_MBAR_ID_MBOX		0
-#define MCHP_ESPI_MBAR_ID_ACPI_EC_0	1
-#define MCHP_ESPI_MBAR_ID_ACPI_EC_1	2
-#define MCHP_ESPI_MBAR_ID_ACPI_EC_2	3
-#define MCHP_ESPI_MBAR_ID_ACPI_EC_3	4
-#define MCHP_ESPI_MBAR_ID_ACPI_EC_4	5
-#define MCHP_ESPI_MBAR_ID_EMI_0		6
-#define MCHP_ESPI_MBAR_ID_EMI_1		7
-#define MCHP_ESPI_MBAR_ID_EMI_2		8
-#define MCHP_ESPI_MBAR_ID_TB32		9
+#define MCHP_ESPI_MBAR_ID_MBOX 0
+#define MCHP_ESPI_MBAR_ID_ACPI_EC_0 1
+#define MCHP_ESPI_MBAR_ID_ACPI_EC_1 2
+#define MCHP_ESPI_MBAR_ID_ACPI_EC_2 3
+#define MCHP_ESPI_MBAR_ID_ACPI_EC_3 4
+#define MCHP_ESPI_MBAR_ID_ACPI_EC_4 5
+#define MCHP_ESPI_MBAR_ID_EMI_0 6
+#define MCHP_ESPI_MBAR_ID_EMI_1 7
+#define MCHP_ESPI_MBAR_ID_EMI_2 8
+#define MCHP_ESPI_MBAR_ID_TB32 9
 
 /* Use with MCHP_ESPI_IO_SERIRQ_REG(x) */
-#define MCHP_ESPI_SIRQ_MBOX		0 /* Host SIRQ */
-#define MCHP_ESPI_SIRQ_MBOX_SMI		1 /* Host SMI */
-#define MCHP_ESPI_SIRQ_8042_KB		2 /* KIRQ */
-#define MCHP_ESPI_SIRQ_8042_MS		3 /* MIRQ */
-#define MCHP_ESPI_SIRQ_ACPI_EC0_OBF	4
-#define MCHP_ESPI_SIRQ_ACPI_EC1_OBF	5
-#define MCHP_ESPI_SIRQ_ACPI_EC2_OBF	6
-#define MCHP_ESPI_SIRQ_ACPI_EC3_OBF	7
-#define MCHP_ESPI_SIRQ_ACPI_EC4_OBF	8
-#define MCHP_ESPI_SIRQ_UART0		9
-#define MCHP_ESPI_SIRQ_UART1		10
-#define MCHP_ESPI_SIRQ_EMI0_HEV		11 /* Host Event */
-#define MCHP_ESPI_SIRQ_EMI0_EC2H	12 /* EC to Host */
-#define MCHP_ESPI_SIRQ_EMI1_HEV		13
-#define MCHP_ESPI_SIRQ_EMI1_EC2H	14
-#define MCHP_ESPI_SIRQ_EMI2_HEV		15
-#define MCHP_ESPI_SIRQ_EMI2_EC2H	16
-#define MCHP_ESPI_SIRQ_RTC		17
-#define MCHP_ESPI_SIRQ_EC		18
+#define MCHP_ESPI_SIRQ_MBOX 0 /* Host SIRQ */
+#define MCHP_ESPI_SIRQ_MBOX_SMI 1 /* Host SMI */
+#define MCHP_ESPI_SIRQ_8042_KB 2 /* KIRQ */
+#define MCHP_ESPI_SIRQ_8042_MS 3 /* MIRQ */
+#define MCHP_ESPI_SIRQ_ACPI_EC0_OBF 4
+#define MCHP_ESPI_SIRQ_ACPI_EC1_OBF 5
+#define MCHP_ESPI_SIRQ_ACPI_EC2_OBF 6
+#define MCHP_ESPI_SIRQ_ACPI_EC3_OBF 7
+#define MCHP_ESPI_SIRQ_ACPI_EC4_OBF 8
+#define MCHP_ESPI_SIRQ_UART0 9
+#define MCHP_ESPI_SIRQ_UART1 10
+#define MCHP_ESPI_SIRQ_EMI0_HEV 11 /* Host Event */
+#define MCHP_ESPI_SIRQ_EMI0_EC2H 12 /* EC to Host */
+#define MCHP_ESPI_SIRQ_EMI1_HEV 13
+#define MCHP_ESPI_SIRQ_EMI1_EC2H 14
+#define MCHP_ESPI_SIRQ_EMI2_HEV 15
+#define MCHP_ESPI_SIRQ_EMI2_EC2H 16
+#define MCHP_ESPI_SIRQ_RTC 17
+#define MCHP_ESPI_SIRQ_EC 18
 
 #define MCHP_ESPI_MSVW_BASE (MCHP_ESPI_VW_BASE)
 #define MCHP_ESPI_SMVW_BASE ((MCHP_ESPI_VW_BASE) + 0x200ul)
@@ -1407,23 +1399,23 @@ enum MCHP_i2c_port {
  * eSPI RESET, channel enables and operations except Master-to-Slave
  * WWires are all on GIRQ19
  */
-#define MCHP_ESPI_GIRQ			19
-#define MCHP_ESPI_PC_GIRQ_BIT		BIT(0)
-#define MCHP_ESPI_BM1_GIRQ_BIT		BIT(1)
-#define MCHP_ESPI_BM2_GIRQ_BIT		BIT(2)
-#define MCHP_ESPI_LTR_GIRQ_BIT		BIT(3)
-#define MCHP_ESPI_OOB_TX_GIRQ_BIT	BIT(4)
-#define MCHP_ESPI_OOB_RX_GIRQ_BIT	BIT(5)
-#define MCHP_ESPI_FC_GIRQ_BIT		BIT(6)
-#define MCHP_ESPI_RESET_GIRQ_BIT	BIT(7)
-#define MCHP_ESPI_VW_EN_GIRQ_BIT	BIT(8)
-#define MCHP_ESPI_SAF_DONE_GIRQ_BIT	BIT(9)
-#define MCHP_ESPI_SAF_ERR_GIRQ_BIT	BIT(10)
-#define MCHP_ESPI_SAF_CACHE_GIRQ_BIT	BIT(11)
+#define MCHP_ESPI_GIRQ 19
+#define MCHP_ESPI_PC_GIRQ_BIT BIT(0)
+#define MCHP_ESPI_BM1_GIRQ_BIT BIT(1)
+#define MCHP_ESPI_BM2_GIRQ_BIT BIT(2)
+#define MCHP_ESPI_LTR_GIRQ_BIT BIT(3)
+#define MCHP_ESPI_OOB_TX_GIRQ_BIT BIT(4)
+#define MCHP_ESPI_OOB_RX_GIRQ_BIT BIT(5)
+#define MCHP_ESPI_FC_GIRQ_BIT BIT(6)
+#define MCHP_ESPI_RESET_GIRQ_BIT BIT(7)
+#define MCHP_ESPI_VW_EN_GIRQ_BIT BIT(8)
+#define MCHP_ESPI_SAF_DONE_GIRQ_BIT BIT(9)
+#define MCHP_ESPI_SAF_ERR_GIRQ_BIT BIT(10)
+#define MCHP_ESPI_SAF_CACHE_GIRQ_BIT BIT(11)
 
 /* eSPI Master-to-Slave WWire interrupts are on GIRQ24 and GIRQ25 */
-#define MCHP_ESPI_MSVW_0_6_GIRQ		24
-#define MCHP_ESPI_MSVW_7_10_GIRQ	25
+#define MCHP_ESPI_MSVW_0_6_GIRQ 24
+#define MCHP_ESPI_MSVW_7_10_GIRQ 25
 /*
  * Four source bits, SRC[0:3] per Master-to-Slave register
  * v = MSVW [0:10]
@@ -1432,12 +1424,12 @@ enum MCHP_i2c_port {
 #define MCHP_ESPI_MSVW_GIRQ(v) (24 + ((v) > 6 ? 1 : 0))
 
 #define MCHP_ESPI_MSVW_SRC_GIRQ_BIT(v, n) \
-	(((v) > 6) ? (1ul << (((v)-7)+(n))) : (1ul << ((v)+(n))))
+	(((v) > 6) ? (1ul << (((v)-7) + (n))) : (1ul << ((v) + (n))))
 
 /* DMA */
-#define MCHP_DMA_MAX_CHAN	16
-#define MCHP_DMA_CH_OFS		0x40
-#define MCHP_DMA_CH_OFS_BITPOS	6
+#define MCHP_DMA_MAX_CHAN 16
+#define MCHP_DMA_CH_OFS 0x40
+#define MCHP_DMA_CH_OFS_BITPOS 6
 #define MCHP_DMA_CH_BASE (MCHP_DMA_BASE + MCHP_DMA_CH_OFS)
 
 /*
@@ -1473,22 +1465,22 @@ enum dma_channel {
  * Peripheral device DMA Device ID's for bits [15:9]
  * in DMA channel control register.
  */
-#define MCHP_DMA_I2C0_SLV_REQ_ID	0
-#define MCHP_DMA_I2C0_MTR_REQ_ID	1
-#define MCHP_DMA_I2C1_SLV_REQ_ID	2
-#define MCHP_DMA_I2C1_MTR_REQ_ID	3
-#define MCHP_DMA_I2C2_SLV_REQ_ID	4
-#define MCHP_DMA_I2C2_MTR_REQ_ID	5
-#define MCHP_DMA_I2C3_SLV_REQ_ID	6
-#define MCHP_DMA_I2C3_MTR_REQ_ID	7
-#define MCHP_DMA_I2C4_SLV_REQ_ID	8
-#define MCHP_DMA_I2C4_MTR_REQ_ID	9
-#define MCHP_DMA_QMSPI0_TX_REQ_ID	10
-#define MCHP_DMA_QMSPI0_RX_REQ_ID	11
-#define MCHP_DMA_SPI0_TX_REQ_ID		12
-#define MCHP_DMA_SPI0_RX_REQ_ID		13
-#define MCHP_DMA_SPI1_TX_REQ_ID		14
-#define MCHP_DMA_SPI1_RX_REQ_ID		15
+#define MCHP_DMA_I2C0_SLV_REQ_ID 0
+#define MCHP_DMA_I2C0_MTR_REQ_ID 1
+#define MCHP_DMA_I2C1_SLV_REQ_ID 2
+#define MCHP_DMA_I2C1_MTR_REQ_ID 3
+#define MCHP_DMA_I2C2_SLV_REQ_ID 4
+#define MCHP_DMA_I2C2_MTR_REQ_ID 5
+#define MCHP_DMA_I2C3_SLV_REQ_ID 6
+#define MCHP_DMA_I2C3_MTR_REQ_ID 7
+#define MCHP_DMA_I2C4_SLV_REQ_ID 8
+#define MCHP_DMA_I2C4_MTR_REQ_ID 9
+#define MCHP_DMA_QMSPI0_TX_REQ_ID 10
+#define MCHP_DMA_QMSPI0_RX_REQ_ID 11
+#define MCHP_DMA_SPI0_TX_REQ_ID 12
+#define MCHP_DMA_SPI0_RX_REQ_ID 13
+#define MCHP_DMA_SPI1_TX_REQ_ID 14
+#define MCHP_DMA_SPI1_RX_REQ_ID 15
 
 /*
  * Hardware delay register.
diff --git a/chip/mchp/registers.h b/chip/mchp/registers.h
index 65936caa2d..7b541b18da 100644
--- a/chip/mchp/registers.h
+++ b/chip/mchp/registers.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,7 +10,6 @@
 #include "common.h"
 #include "compile_time_macros.h"
 
-
 #if defined(CHIP_FAMILY_MEC152X)
 #include "registers-mec152x.h"
 #elif defined(CHIP_FAMILY_MEC170X)
@@ -23,530 +22,526 @@
 
 /* Common registers */
 /* EC Interrupt aggregator (ECIA) */
-#define MCHP_INT_SOURCE(x)		REG32(MCHP_INTx_BASE(x) + 0x0)
-#define MCHP_INT_ENABLE(x)		REG32(MCHP_INTx_BASE(x) + 0x4)
-#define MCHP_INT_RESULT(x)		REG32(MCHP_INTx_BASE(x) + 0x8)
-#define MCHP_INT_DISABLE(x)		REG32(MCHP_INTx_BASE(x) + 0xc)
-#define MCHP_INT_BLK_EN			REG32(MCHP_INT_BASE + 0x200)
-#define MCHP_INT_BLK_DIS		REG32(MCHP_INT_BASE + 0x204)
-#define MCHP_INT_BLK_IRQ		REG32(MCHP_INT_BASE + 0x208)
+#define MCHP_INT_SOURCE(x) REG32(MCHP_INTx_BASE(x) + 0x0)
+#define MCHP_INT_ENABLE(x) REG32(MCHP_INTx_BASE(x) + 0x4)
+#define MCHP_INT_RESULT(x) REG32(MCHP_INTx_BASE(x) + 0x8)
+#define MCHP_INT_DISABLE(x) REG32(MCHP_INTx_BASE(x) + 0xc)
+#define MCHP_INT_BLK_EN REG32(MCHP_INT_BASE + 0x200)
+#define MCHP_INT_BLK_DIS REG32(MCHP_INT_BASE + 0x204)
+#define MCHP_INT_BLK_IRQ REG32(MCHP_INT_BASE + 0x208)
 
 /* EC Chip Configuration */
-#define MCHP_CHIP_LEGACY_DEV_ID		REG8(MCHP_CHIP_BASE + 0x20)
-#define MCHP_CHIP_LEGACY_DEV_REV	REG8(MCHP_CHIP_BASE + 0x21)
+#define MCHP_CHIP_LEGACY_DEV_ID REG8(MCHP_CHIP_BASE + 0x20)
+#define MCHP_CHIP_LEGACY_DEV_REV REG8(MCHP_CHIP_BASE + 0x21)
 
 /* Power/Clocks/Resets */
-#define MCHP_PCR_SYS_SLP_CTL		REG32(MCHP_PCR_BASE + 0x00)
-#define MCHP_PCR_PROC_CLK_CTL		REG32(MCHP_PCR_BASE + 0x04)
-#define MCHP_PCR_SLOW_CLK_CTL		REG32(MCHP_PCR_BASE + 0x08)
-#define MCHP_PCR_CHIP_OSC_ID		REG32(MCHP_PCR_BASE + 0x0C)
-#define MCHP_PCR_PWR_RST_STS		REG32(MCHP_PCR_BASE + 0x10)
-#define MCHP_PCR_PWR_RST_CTL		REG32(MCHP_PCR_BASE + 0x14)
-#define MCHP_PCR_SYS_RST		REG32(MCHP_PCR_BASE + 0x18)
-#define MCHP_PCR_SLP_EN0		REG32(MCHP_PCR_BASE + 0x30)
-#define MCHP_PCR_SLP_EN1		REG32(MCHP_PCR_BASE + 0x34)
-#define MCHP_PCR_SLP_EN2		REG32(MCHP_PCR_BASE + 0x38)
-#define MCHP_PCR_SLP_EN3		REG32(MCHP_PCR_BASE + 0x3C)
-#define MCHP_PCR_SLP_EN4		REG32(MCHP_PCR_BASE + 0x40)
-#define MCHP_PCR_CLK_REQ0		REG32(MCHP_PCR_BASE + 0x50)
-#define MCHP_PCR_CLK_REQ1		REG32(MCHP_PCR_BASE + 0x54)
-#define MCHP_PCR_CLK_REQ2		REG32(MCHP_PCR_BASE + 0x58)
-#define MCHP_PCR_CLK_REQ3		REG32(MCHP_PCR_BASE + 0x5C)
-#define MCHP_PCR_CLK_REQ4		REG32(MCHP_PCR_BASE + 0x60)
-#define MCHP_PCR_RST_EN0		REG32(MCHP_PCR_BASE + 0x70)
-#define MCHP_PCR_RST_EN1		REG32(MCHP_PCR_BASE + 0x74)
-#define MCHP_PCR_RST_EN2		REG32(MCHP_PCR_BASE + 0x78)
-#define MCHP_PCR_RST_EN3		REG32(MCHP_PCR_BASE + 0x7C)
-#define MCHP_PCR_RST_EN4		REG32(MCHP_PCR_BASE + 0x80)
-#define MCHP_PCR_SLP_EN(x)		REG32(MCHP_PCR_BASE + 0x30 + ((x)<<2))
-#define MCHP_PCR_CLK_REQ(x)		REG32(MCHP_PCR_BASE + 0x50 + ((x)<<2))
-#define MCHP_PCR_RST_EN(x)		REG32(MCHP_PCR_BASE + 0x70 + ((x)<<2))
+#define MCHP_PCR_SYS_SLP_CTL REG32(MCHP_PCR_BASE + 0x00)
+#define MCHP_PCR_PROC_CLK_CTL REG32(MCHP_PCR_BASE + 0x04)
+#define MCHP_PCR_SLOW_CLK_CTL REG32(MCHP_PCR_BASE + 0x08)
+#define MCHP_PCR_CHIP_OSC_ID REG32(MCHP_PCR_BASE + 0x0C)
+#define MCHP_PCR_PWR_RST_STS REG32(MCHP_PCR_BASE + 0x10)
+#define MCHP_PCR_PWR_RST_CTL REG32(MCHP_PCR_BASE + 0x14)
+#define MCHP_PCR_SYS_RST REG32(MCHP_PCR_BASE + 0x18)
+#define MCHP_PCR_SLP_EN0 REG32(MCHP_PCR_BASE + 0x30)
+#define MCHP_PCR_SLP_EN1 REG32(MCHP_PCR_BASE + 0x34)
+#define MCHP_PCR_SLP_EN2 REG32(MCHP_PCR_BASE + 0x38)
+#define MCHP_PCR_SLP_EN3 REG32(MCHP_PCR_BASE + 0x3C)
+#define MCHP_PCR_SLP_EN4 REG32(MCHP_PCR_BASE + 0x40)
+#define MCHP_PCR_CLK_REQ0 REG32(MCHP_PCR_BASE + 0x50)
+#define MCHP_PCR_CLK_REQ1 REG32(MCHP_PCR_BASE + 0x54)
+#define MCHP_PCR_CLK_REQ2 REG32(MCHP_PCR_BASE + 0x58)
+#define MCHP_PCR_CLK_REQ3 REG32(MCHP_PCR_BASE + 0x5C)
+#define MCHP_PCR_CLK_REQ4 REG32(MCHP_PCR_BASE + 0x60)
+#define MCHP_PCR_RST_EN0 REG32(MCHP_PCR_BASE + 0x70)
+#define MCHP_PCR_RST_EN1 REG32(MCHP_PCR_BASE + 0x74)
+#define MCHP_PCR_RST_EN2 REG32(MCHP_PCR_BASE + 0x78)
+#define MCHP_PCR_RST_EN3 REG32(MCHP_PCR_BASE + 0x7C)
+#define MCHP_PCR_RST_EN4 REG32(MCHP_PCR_BASE + 0x80)
+#define MCHP_PCR_SLP_EN(x) REG32(MCHP_PCR_BASE + 0x30 + ((x) << 2))
+#define MCHP_PCR_CLK_REQ(x) REG32(MCHP_PCR_BASE + 0x50 + ((x) << 2))
+#define MCHP_PCR_RST_EN(x) REG32(MCHP_PCR_BASE + 0x70 + ((x) << 2))
 
 /* Bit definitions for MCHP_PCR_SYS_SLP_CTL */
-#define MCHP_PCR_SYS_SLP_LIGHT		(0ul << 0)
-#define MCHP_PCR_SYS_SLP_HEAVY		(1ul << 0)
-#define MCHP_PCR_SYS_SLP_ALL		(1ul << 3)
+#define MCHP_PCR_SYS_SLP_LIGHT (0ul << 0)
+#define MCHP_PCR_SYS_SLP_HEAVY (1ul << 0)
+#define MCHP_PCR_SYS_SLP_ALL (1ul << 3)
 /*
  * Set/clear PCR sleep enable bit for single device
  * d bits[10:8] = register 0 - 4
  * d bits[4:0] = register bit position
  */
 #define MCHP_PCR_SLP_EN_DEV(d) \
-	(MCHP_PCR_SLP_EN(((d) >> 8) & 0x07) |= (1ul << ((d) & 0x1f)))
+	(MCHP_PCR_SLP_EN(((d) >> 8) & 0x07) |= (1ul << ((d)&0x1f)))
 #define MCHP_PCR_SLP_DIS_DEV(d) \
-	(MCHP_PCR_SLP_EN(((d) >> 8) & 0x07) &= ~(1ul << ((d) & 0x1f)))
+	(MCHP_PCR_SLP_EN(((d) >> 8) & 0x07) &= ~(1ul << ((d)&0x1f)))
 /*
  * Set/clear bit pattern specified by mask in a single PCR sleep enable
  * register.
  * id = zero based ID of sleep enable register (0-4)
  * m = bit mask of bits to change
  */
-#define MCHP_PCR_SLP_EN_DEV_MASK(id, m)		(MCHP_PCR_SLP_EN((id)) |= (m))
-#define MCHP_PCR_SLP_DIS_DEV_MASK(id, m)	(MCHP_PCR_SLP_EN((id)) &= ~(m))
+#define MCHP_PCR_SLP_EN_DEV_MASK(id, m) (MCHP_PCR_SLP_EN((id)) |= (m))
+#define MCHP_PCR_SLP_DIS_DEV_MASK(id, m) (MCHP_PCR_SLP_EN((id)) &= ~(m))
 /* Slow Clock Control Mask */
-#define MCHP_PCR_SLOW_CLK_CTL_MASK		0x03FFul
+#define MCHP_PCR_SLOW_CLK_CTL_MASK 0x03FFul
 
 /* TFDP */
-#define MCHP_TFDP_DATA		REG8(MCHP_TFDP_BASE + 0x00)
-#define MCHP_TFDP_CTRL		REG8(MCHP_TFDP_BASE + 0x04)
+#define MCHP_TFDP_DATA REG8(MCHP_TFDP_BASE + 0x00)
+#define MCHP_TFDP_CTRL REG8(MCHP_TFDP_BASE + 0x04)
 
 /* UART */
-#define MCHP_UART_ACT(x)	REG8(MCHP_UART_CONFIG_BASE(x) + 0x30)
-#define MCHP_UART_CFG(x)	REG8(MCHP_UART_CONFIG_BASE(x) + 0xf0)
+#define MCHP_UART_ACT(x) REG8(MCHP_UART_CONFIG_BASE(x) + 0x30)
+#define MCHP_UART_CFG(x) REG8(MCHP_UART_CONFIG_BASE(x) + 0xf0)
 /* DLAB=0 */
-#define MCHP_UART_RB(x) /*R*/	REG8(MCHP_UART_RUNTIME_BASE(x) + 0x0)
-#define MCHP_UART_TB(x) /*W*/	REG8(MCHP_UART_RUNTIME_BASE(x) + 0x0)
-#define MCHP_UART_IER(x)	REG8(MCHP_UART_RUNTIME_BASE(x) + 0x1)
+#define MCHP_UART_RB(x) /*R*/ REG8(MCHP_UART_RUNTIME_BASE(x) + 0x0)
+#define MCHP_UART_TB(x) /*W*/ REG8(MCHP_UART_RUNTIME_BASE(x) + 0x0)
+#define MCHP_UART_IER(x) REG8(MCHP_UART_RUNTIME_BASE(x) + 0x1)
 /* DLAB=1 */
-#define MCHP_UART_PBRG0(x)	REG8(MCHP_UART_RUNTIME_BASE(x) + 0x0)
-#define MCHP_UART_PBRG1(x)	REG8(MCHP_UART_RUNTIME_BASE(x) + 0x1)
-#define MCHP_UART_FCR(x) /*W*/	REG8(MCHP_UART_RUNTIME_BASE(x) + 0x2)
-#define MCHP_UART_IIR(x) /*R*/	REG8(MCHP_UART_RUNTIME_BASE(x) + 0x2)
-#define MCHP_UART_LCR(x)	REG8(MCHP_UART_RUNTIME_BASE(x) + 0x3)
-#define MCHP_UART_MCR(x)	REG8(MCHP_UART_RUNTIME_BASE(x) + 0x4)
-#define MCHP_UART_LSR(x)	REG8(MCHP_UART_RUNTIME_BASE(x) + 0x5)
-#define MCHP_UART_MSR(x)	REG8(MCHP_UART_RUNTIME_BASE(x) + 0x6)
-#define MCHP_UART_SCR(x)	REG8(MCHP_UART_RUNTIME_BASE(x) + 0x7)
+#define MCHP_UART_PBRG0(x) REG8(MCHP_UART_RUNTIME_BASE(x) + 0x0)
+#define MCHP_UART_PBRG1(x) REG8(MCHP_UART_RUNTIME_BASE(x) + 0x1)
+#define MCHP_UART_FCR(x) /*W*/ REG8(MCHP_UART_RUNTIME_BASE(x) + 0x2)
+#define MCHP_UART_IIR(x) /*R*/ REG8(MCHP_UART_RUNTIME_BASE(x) + 0x2)
+#define MCHP_UART_LCR(x) REG8(MCHP_UART_RUNTIME_BASE(x) + 0x3)
+#define MCHP_UART_MCR(x) REG8(MCHP_UART_RUNTIME_BASE(x) + 0x4)
+#define MCHP_UART_LSR(x) REG8(MCHP_UART_RUNTIME_BASE(x) + 0x5)
+#define MCHP_UART_MSR(x) REG8(MCHP_UART_RUNTIME_BASE(x) + 0x6)
+#define MCHP_UART_SCR(x) REG8(MCHP_UART_RUNTIME_BASE(x) + 0x7)
 /* Bit defines for MCHP_UARTx_LSR */
-#define MCHP_LSR_TX_EMPTY	BIT(5)
+#define MCHP_LSR_TX_EMPTY BIT(5)
 
 /* Timer */
-#define MCHP_TMR16_CNT(x)	REG32(MCHP_TMR16_BASE(x) + 0x0)
-#define MCHP_TMR16_PRE(x)	REG32(MCHP_TMR16_BASE(x) + 0x4)
-#define MCHP_TMR16_STS(x)	REG32(MCHP_TMR16_BASE(x) + 0x8)
-#define MCHP_TMR16_IEN(x)	REG32(MCHP_TMR16_BASE(x) + 0xc)
-#define MCHP_TMR16_CTL(x)	REG32(MCHP_TMR16_BASE(x) + 0x10)
-#define MCHP_TMR32_CNT(x)	REG32(MCHP_TMR32_BASE(x) + 0x0)
-#define MCHP_TMR32_PRE(x)	REG32(MCHP_TMR32_BASE(x) + 0x4)
-#define MCHP_TMR32_STS(x)	REG32(MCHP_TMR32_BASE(x) + 0x8)
-#define MCHP_TMR32_IEN(x)	REG32(MCHP_TMR32_BASE(x) + 0xc)
-#define MCHP_TMR32_CTL(x)	REG32(MCHP_TMR32_BASE(x) + 0x10)
+#define MCHP_TMR16_CNT(x) REG32(MCHP_TMR16_BASE(x) + 0x0)
+#define MCHP_TMR16_PRE(x) REG32(MCHP_TMR16_BASE(x) + 0x4)
+#define MCHP_TMR16_STS(x) REG32(MCHP_TMR16_BASE(x) + 0x8)
+#define MCHP_TMR16_IEN(x) REG32(MCHP_TMR16_BASE(x) + 0xc)
+#define MCHP_TMR16_CTL(x) REG32(MCHP_TMR16_BASE(x) + 0x10)
+#define MCHP_TMR32_CNT(x) REG32(MCHP_TMR32_BASE(x) + 0x0)
+#define MCHP_TMR32_PRE(x) REG32(MCHP_TMR32_BASE(x) + 0x4)
+#define MCHP_TMR32_STS(x) REG32(MCHP_TMR32_BASE(x) + 0x8)
+#define MCHP_TMR32_IEN(x) REG32(MCHP_TMR32_BASE(x) + 0xc)
+#define MCHP_TMR32_CTL(x) REG32(MCHP_TMR32_BASE(x) + 0x10)
 
 /* RTimer */
-#define MCHP_RTMR_COUNTER	REG32(MCHP_RTMR_BASE + 0x00)
-#define MCHP_RTMR_PRELOAD	REG32(MCHP_RTMR_BASE + 0x04)
-#define MCHP_RTMR_CONTROL	REG8(MCHP_RTMR_BASE + 0x08)
-#define MCHP_RTMR_SOFT_INTR	REG8(MCHP_RTMR_BASE + 0x0c)
+#define MCHP_RTMR_COUNTER REG32(MCHP_RTMR_BASE + 0x00)
+#define MCHP_RTMR_PRELOAD REG32(MCHP_RTMR_BASE + 0x04)
+#define MCHP_RTMR_CONTROL REG8(MCHP_RTMR_BASE + 0x08)
+#define MCHP_RTMR_SOFT_INTR REG8(MCHP_RTMR_BASE + 0x0c)
 
 /* Watch dog timer */
-#define MCHP_WDG_LOAD			REG16(MCHP_WDG_BASE + 0x0)
-#define MCHP_WDG_CTL			REG16(MCHP_WDG_BASE + 0x4)
-#define MCHP_WDG_KICK			REG8(MCHP_WDG_BASE + 0x8)
-#define MCHP_WDG_CNT			REG16(MCHP_WDG_BASE + 0xc)
-#define MCHP_WDT_CTL_ENABLE		BIT(0)
-#define MCHP_WDT_CTL_HTMR_STALL_EN	BIT(2)
-#define MCHP_WDT_CTL_WKTMR_STALL_EN	BIT(3)
-#define MCHP_WDT_CTL_JTAG_STALL_EN	BIT(4)
+#define MCHP_WDG_LOAD REG16(MCHP_WDG_BASE + 0x0)
+#define MCHP_WDG_CTL REG16(MCHP_WDG_BASE + 0x4)
+#define MCHP_WDG_KICK REG8(MCHP_WDG_BASE + 0x8)
+#define MCHP_WDG_CNT REG16(MCHP_WDG_BASE + 0xc)
+#define MCHP_WDT_CTL_ENABLE BIT(0)
+#define MCHP_WDT_CTL_HTMR_STALL_EN BIT(2)
+#define MCHP_WDT_CTL_WKTMR_STALL_EN BIT(3)
+#define MCHP_WDT_CTL_JTAG_STALL_EN BIT(4)
 
 /* Blinking-Breathing LED */
-#define MCHP_BBLED_CONFIG(x)		REG32(MCHP_BBLED_BASE(x) + 0x00)
-#define MCHP_BBLED_LIMITS(x)		REG32(MCHP_BBLED_BASE(x) + 0x04)
-#define MCHP_BBLED_LIMIT_MIN(x)		REG8(MCHP_BBLED_BASE(x) + 0x04)
-#define MCHP_BBLED_LIMIT_MAX(x)		REG8(MCHP_BBLED_BASE(x) + 0x06)
-#define MCHP_BBLED_DELAY(x)		REG32(MCHP_BBLED_BASE(x) + 0x08)
-#define MCHP_BBLED_UPDATE_STEP(x)	REG32(MCHP_BBLED_BASE(x) + 0x0C)
-#define MCHP_BBLED_UPDATE_INTV(x)	REG32(MCHP_BBLED_BASE(x) + 0x10)
-#define MCHP_BBLED_OUTPUT_DLY(x)	REG8(MCHP_BBLED_BASE(x) + 0x14)
+#define MCHP_BBLED_CONFIG(x) REG32(MCHP_BBLED_BASE(x) + 0x00)
+#define MCHP_BBLED_LIMITS(x) REG32(MCHP_BBLED_BASE(x) + 0x04)
+#define MCHP_BBLED_LIMIT_MIN(x) REG8(MCHP_BBLED_BASE(x) + 0x04)
+#define MCHP_BBLED_LIMIT_MAX(x) REG8(MCHP_BBLED_BASE(x) + 0x06)
+#define MCHP_BBLED_DELAY(x) REG32(MCHP_BBLED_BASE(x) + 0x08)
+#define MCHP_BBLED_UPDATE_STEP(x) REG32(MCHP_BBLED_BASE(x) + 0x0C)
+#define MCHP_BBLED_UPDATE_INTV(x) REG32(MCHP_BBLED_BASE(x) + 0x10)
+#define MCHP_BBLED_OUTPUT_DLY(x) REG8(MCHP_BBLED_BASE(x) + 0x14)
 /* BBLED Configuration Register */
-#define MCHP_BBLED_ASYMMETRIC		BIT(16)
-#define MCHP_BBLED_WDT_RELOAD_BITPOS	8
-#define MCHP_BBLED_WDT_RELOAD_MASK0	0xFFul
-#define MCHP_BBLED_WDT_RELOAD_MASK	(0xFFul << 8)
-#define MCHP_BBLED_RESET		BIT(7)
-#define MCHP_BBLED_EN_UPDATE		BIT(6)
-#define MCHP_BBLED_PWM_SIZE_BITPOS	4
-#define MCHP_BBLED_PWM_SIZE_MASK0	0x03ul
-#define MCHP_BBLED_PWM_SIZE_MASK	(0x03ul << 4)
-#define MCHP_BBLED_PWM_SIZE_6BIT	(0x02ul << 4)
-#define MCHP_BBLED_PWM_SIZE_7BIT	(0x01ul << 4)
-#define MCHP_BBLED_PWM_SIZE_8BIT	(0x00ul << 4)
-#define MCHP_BBLED_SYNC			BIT(3)
-#define MCHP_BBLED_CLK_48M		BIT(2)
-#define MCHP_BBLED_CLK_32K		0
-#define MCHP_BBLED_CTRL_MASK		0x03ul
-#define MCHP_BBLED_CTRL_ALWAYS_ON	0x03ul
-#define MCHP_BBLED_CTRL_BLINK		0x02ul
-#define MCHP_BBLED_CTRL_BREATHE		0x01ul
-#define MCHP_BBLED_CTRL_OFF		0x00ul
+#define MCHP_BBLED_ASYMMETRIC BIT(16)
+#define MCHP_BBLED_WDT_RELOAD_BITPOS 8
+#define MCHP_BBLED_WDT_RELOAD_MASK0 0xFFul
+#define MCHP_BBLED_WDT_RELOAD_MASK (0xFFul << 8)
+#define MCHP_BBLED_RESET BIT(7)
+#define MCHP_BBLED_EN_UPDATE BIT(6)
+#define MCHP_BBLED_PWM_SIZE_BITPOS 4
+#define MCHP_BBLED_PWM_SIZE_MASK0 0x03ul
+#define MCHP_BBLED_PWM_SIZE_MASK (0x03ul << 4)
+#define MCHP_BBLED_PWM_SIZE_6BIT (0x02ul << 4)
+#define MCHP_BBLED_PWM_SIZE_7BIT (0x01ul << 4)
+#define MCHP_BBLED_PWM_SIZE_8BIT (0x00ul << 4)
+#define MCHP_BBLED_SYNC BIT(3)
+#define MCHP_BBLED_CLK_48M BIT(2)
+#define MCHP_BBLED_CLK_32K 0
+#define MCHP_BBLED_CTRL_MASK 0x03ul
+#define MCHP_BBLED_CTRL_ALWAYS_ON 0x03ul
+#define MCHP_BBLED_CTRL_BLINK 0x02ul
+#define MCHP_BBLED_CTRL_BREATHE 0x01ul
+#define MCHP_BBLED_CTRL_OFF 0x00ul
 /* BBLED Delay Register */
-#define MCHP_BBLED_DLY_MASK		0x0FFFul
-#define MCHP_BBLED_DLY_LO_BITPOS	0
-#define MCHP_BBLED_DLY_LO_MASK		0x0FFFul
-#define MCHP_BBLED_DLY_HI_BITPOS	12
-#define MCHP_BBLED_DLY_HI_MASK		(0x0FFFul << 12)
+#define MCHP_BBLED_DLY_MASK 0x0FFFul
+#define MCHP_BBLED_DLY_LO_BITPOS 0
+#define MCHP_BBLED_DLY_LO_MASK 0x0FFFul
+#define MCHP_BBLED_DLY_HI_BITPOS 12
+#define MCHP_BBLED_DLY_HI_MASK (0x0FFFul << 12)
 /*
  * BBLED Update Step Register
  * 8 update fields numbered 0 - 7
  */
-#define MCHP_BBLED_UPD_STEP_MASK0	0x0Ful
-#define MCHP_BBLED_UPD_STEP_MASK(u)	(0x0Ful << (((u) & 0x07) + 4))
+#define MCHP_BBLED_UPD_STEP_MASK0 0x0Ful
+#define MCHP_BBLED_UPD_STEP_MASK(u) (0x0Ful << (((u)&0x07) + 4))
 /*
  * BBLED Update Interval Register
  * 8 interval fields numbered 0 - 7
  */
-#define MCHP_BBLED_UPD_INTV_MASK0	0x0Ful
-#define MCHP_BBLED_UPD_INTV_MASK(i)	(0x0Ful << (((i) & 0x07) + 4))
+#define MCHP_BBLED_UPD_INTV_MASK0 0x0Ful
+#define MCHP_BBLED_UPD_INTV_MASK(i) (0x0Ful << (((i)&0x07) + 4))
 
 /* EMI */
-#define MCHP_EMI_H2E_MBX(n)		REG8(MCHP_EMI_BASE(n) + 0x0)
-#define MCHP_EMI_E2H_MBX(n)		REG8(MCHP_EMI_BASE(n) + 0x1)
-#define MCHP_EMI_MBA0(n)		REG32(MCHP_EMI_BASE(n) + 0x4)
-#define MCHP_EMI_MRL0(n)		REG16(MCHP_EMI_BASE(n) + 0x8)
-#define MCHP_EMI_MWL0(n)		REG16(MCHP_EMI_BASE(n) + 0xa)
-#define MCHP_EMI_MBA1(n)		REG32(MCHP_EMI_BASE(n) + 0xc)
-#define MCHP_EMI_MRL1(n)		REG16(MCHP_EMI_BASE(n) + 0x10)
-#define MCHP_EMI_MWL1(n)		REG16(MCHP_EMI_BASE(n) + 0x12)
-#define MCHP_EMI_ISR(n)			REG16(MCHP_EMI_BASE(n) + 0x14)
-#define MCHP_EMI_HCE(n)			REG16(MCHP_EMI_BASE(n) + 0x16)
-#define MCHP_EMI_ISR_B0(n)		REG8(MCHP_EMI_RT_BASE(n) + 0x8)
-#define MCHP_EMI_ISR_B1(n)		REG8(MCHP_EMI_RT_BASE(n) + 0x9)
-#define MCHP_EMI_IMR_B0(n)		REG8(MCHP_EMI_RT_BASE(n) + 0xa)
-#define MCHP_EMI_IMR_B1(n)		REG8(MCHP_EMI_RT_BASE(n) + 0xb)
+#define MCHP_EMI_H2E_MBX(n) REG8(MCHP_EMI_BASE(n) + 0x0)
+#define MCHP_EMI_E2H_MBX(n) REG8(MCHP_EMI_BASE(n) + 0x1)
+#define MCHP_EMI_MBA0(n) REG32(MCHP_EMI_BASE(n) + 0x4)
+#define MCHP_EMI_MRL0(n) REG16(MCHP_EMI_BASE(n) + 0x8)
+#define MCHP_EMI_MWL0(n) REG16(MCHP_EMI_BASE(n) + 0xa)
+#define MCHP_EMI_MBA1(n) REG32(MCHP_EMI_BASE(n) + 0xc)
+#define MCHP_EMI_MRL1(n) REG16(MCHP_EMI_BASE(n) + 0x10)
+#define MCHP_EMI_MWL1(n) REG16(MCHP_EMI_BASE(n) + 0x12)
+#define MCHP_EMI_ISR(n) REG16(MCHP_EMI_BASE(n) + 0x14)
+#define MCHP_EMI_HCE(n) REG16(MCHP_EMI_BASE(n) + 0x16)
+#define MCHP_EMI_ISR_B0(n) REG8(MCHP_EMI_RT_BASE(n) + 0x8)
+#define MCHP_EMI_ISR_B1(n) REG8(MCHP_EMI_RT_BASE(n) + 0x9)
+#define MCHP_EMI_IMR_B0(n) REG8(MCHP_EMI_RT_BASE(n) + 0xa)
+#define MCHP_EMI_IMR_B1(n) REG8(MCHP_EMI_RT_BASE(n) + 0xb)
 
 /* Mailbox */
-#define MCHP_MBX_INDEX			REG8(MCHP_MBX_RT_BASE + 0x0)
-#define MCHP_MBX_DATA			REG8(MCHP_MBX_RT_BASE + 0x1)
-#define MCHP_MBX_H2E_MBX		REG8(MCHP_MBX_BASE + 0x0)
-#define MCHP_MBX_E2H_MBX		REG8(MCHP_MBX_BASE + 0x4)
-#define MCHP_MBX_ISR			REG8(MCHP_MBX_BASE + 0x8)
-#define MCHP_MBX_IMR			REG8(MCHP_MBX_BASE + 0xc)
-#define MCHP_MBX_REG(x)			REG8(MCHP_MBX_BASE + 0x10 + (x))
+#define MCHP_MBX_INDEX REG8(MCHP_MBX_RT_BASE + 0x0)
+#define MCHP_MBX_DATA REG8(MCHP_MBX_RT_BASE + 0x1)
+#define MCHP_MBX_H2E_MBX REG8(MCHP_MBX_BASE + 0x0)
+#define MCHP_MBX_E2H_MBX REG8(MCHP_MBX_BASE + 0x4)
+#define MCHP_MBX_ISR REG8(MCHP_MBX_BASE + 0x8)
+#define MCHP_MBX_IMR REG8(MCHP_MBX_BASE + 0xc)
+#define MCHP_MBX_REG(x) REG8(MCHP_MBX_BASE + 0x10 + (x))
 
 /* PWM */
-#define MCHP_PWM_ON(x)			REG32(MCHP_PWM_BASE(x) + 0x00)
-#define MCHP_PWM_OFF(x)			REG32(MCHP_PWM_BASE(x) + 0x04)
-#define MCHP_PWM_CFG(x)			REG32(MCHP_PWM_BASE(x) + 0x08)
+#define MCHP_PWM_ON(x) REG32(MCHP_PWM_BASE(x) + 0x00)
+#define MCHP_PWM_OFF(x) REG32(MCHP_PWM_BASE(x) + 0x04)
+#define MCHP_PWM_CFG(x) REG32(MCHP_PWM_BASE(x) + 0x08)
 
 /* TACH */
-#define MCHP_TACH_CTRL(x)		REG32(MCHP_TACH_BASE(x))
-#define MCHP_TACH_CTRL_LO(x)		REG16(MCHP_TACH_BASE(x) + 0x00)
-#define MCHP_TACH_CTRL_CNT(x)		REG16(MCHP_TACH_BASE(x) + 0x02)
-#define MCHP_TACH_STATUS(x)		REG8(MCHP_TACH_BASE(x) + 0x04)
-#define MCHP_TACH_LIMIT_HI(x)		REG16(MCHP_TACH_BASE(x) + 0x08)
-#define MCHP_TACH_LIMIT_LO(x)		REG16(MCHP_TACH_BASE(x) + 0x0C)
+#define MCHP_TACH_CTRL(x) REG32(MCHP_TACH_BASE(x))
+#define MCHP_TACH_CTRL_LO(x) REG16(MCHP_TACH_BASE(x) + 0x00)
+#define MCHP_TACH_CTRL_CNT(x) REG16(MCHP_TACH_BASE(x) + 0x02)
+#define MCHP_TACH_STATUS(x) REG8(MCHP_TACH_BASE(x) + 0x04)
+#define MCHP_TACH_LIMIT_HI(x) REG16(MCHP_TACH_BASE(x) + 0x08)
+#define MCHP_TACH_LIMIT_LO(x) REG16(MCHP_TACH_BASE(x) + 0x0C)
 
 /* ACPI */
-#define MCHP_ACPI_EC_EC2OS(x, y)	REG8(MCHP_ACPI_EC_BASE(x) + 0x100 + (y))
-#define MCHP_ACPI_EC_STATUS(x)		REG8(MCHP_ACPI_EC_BASE(x) + 0x104)
-#define MCHP_ACPI_EC_BYTE_CTL(x)	REG8(MCHP_ACPI_EC_BASE(x) + 0x105)
-#define MCHP_ACPI_EC_OS2EC(x, y)	REG8(MCHP_ACPI_EC_BASE(x) + 0x108 + (y))
-#define MCHP_ACPI_PM1_STS1		REG8(MCHP_ACPI_PM_RT_BASE + 0x0)
-#define MCHP_ACPI_PM1_STS2		REG8(MCHP_ACPI_PM_RT_BASE + 0x1)
-#define MCHP_ACPI_PM1_EN1		REG8(MCHP_ACPI_PM_RT_BASE + 0x2)
-#define MCHP_ACPI_PM1_EN2		REG8(MCHP_ACPI_PM_RT_BASE + 0x3)
-#define MCHP_ACPI_PM1_CTL1		REG8(MCHP_ACPI_PM_RT_BASE + 0x4)
-#define MCHP_ACPI_PM1_CTL2		REG8(MCHP_ACPI_PM_RT_BASE + 0x5)
-#define MCHP_ACPI_PM2_CTL1		REG8(MCHP_ACPI_PM_RT_BASE + 0x6)
-#define MCHP_ACPI_PM2_CTL2		REG8(MCHP_ACPI_PM_RT_BASE + 0x7)
-#define MCHP_ACPI_PM_STS		REG8(MCHP_ACPI_PM_EC_BASE + 0x10)
+#define MCHP_ACPI_EC_EC2OS(x, y) REG8(MCHP_ACPI_EC_BASE(x) + 0x100 + (y))
+#define MCHP_ACPI_EC_STATUS(x) REG8(MCHP_ACPI_EC_BASE(x) + 0x104)
+#define MCHP_ACPI_EC_BYTE_CTL(x) REG8(MCHP_ACPI_EC_BASE(x) + 0x105)
+#define MCHP_ACPI_EC_OS2EC(x, y) REG8(MCHP_ACPI_EC_BASE(x) + 0x108 + (y))
+#define MCHP_ACPI_PM1_STS1 REG8(MCHP_ACPI_PM_RT_BASE + 0x0)
+#define MCHP_ACPI_PM1_STS2 REG8(MCHP_ACPI_PM_RT_BASE + 0x1)
+#define MCHP_ACPI_PM1_EN1 REG8(MCHP_ACPI_PM_RT_BASE + 0x2)
+#define MCHP_ACPI_PM1_EN2 REG8(MCHP_ACPI_PM_RT_BASE + 0x3)
+#define MCHP_ACPI_PM1_CTL1 REG8(MCHP_ACPI_PM_RT_BASE + 0x4)
+#define MCHP_ACPI_PM1_CTL2 REG8(MCHP_ACPI_PM_RT_BASE + 0x5)
+#define MCHP_ACPI_PM2_CTL1 REG8(MCHP_ACPI_PM_RT_BASE + 0x6)
+#define MCHP_ACPI_PM2_CTL2 REG8(MCHP_ACPI_PM_RT_BASE + 0x7)
+#define MCHP_ACPI_PM_STS REG8(MCHP_ACPI_PM_EC_BASE + 0x10)
 
 /* 8042 */
-#define MCHP_8042_OBF_CLR		REG8(MCHP_8042_BASE + 0x0)
-#define MCHP_8042_H2E			REG8(MCHP_8042_BASE + 0x100)
-#define MCHP_8042_E2H			REG8(MCHP_8042_BASE + 0x100)
-#define MCHP_8042_STS			REG8(MCHP_8042_BASE + 0x104)
-#define MCHP_8042_KB_CTRL		REG8(MCHP_8042_BASE + 0x108)
-#define MCHP_8042_PCOBF			REG8(MCHP_8042_BASE + 0x114)
-#define MCHP_8042_ACT			REG8(MCHP_8042_BASE + 0x330)
+#define MCHP_8042_OBF_CLR REG8(MCHP_8042_BASE + 0x0)
+#define MCHP_8042_H2E REG8(MCHP_8042_BASE + 0x100)
+#define MCHP_8042_E2H REG8(MCHP_8042_BASE + 0x100)
+#define MCHP_8042_STS REG8(MCHP_8042_BASE + 0x104)
+#define MCHP_8042_KB_CTRL REG8(MCHP_8042_BASE + 0x108)
+#define MCHP_8042_PCOBF REG8(MCHP_8042_BASE + 0x114)
+#define MCHP_8042_ACT REG8(MCHP_8042_BASE + 0x330)
 
 /* PROCHOT */
-#define MCHP_PCHOT_CUM_CNT		REG32(MCHP_PROCHOT_BASE + 0x00)
-#define MCHP_PCHOT_DTY_CYC_CNT		REG32(MCHP_PROCHOT_BASE + 0x04)
-#define MCHP_PCHOT_DTY_PRD_CNT		REG32(MCHP_PROCHOT_BASE + 0x08)
-#define MCHP_PCHOT_STS_CTRL		REG32(MCHP_PROCHOT_BASE + 0x0C)
-#define MCHP_PCHOT_ASERT_CNT		REG32(MCHP_PROCHOT_BASE + 0x10)
-#define MCHP_PCHOT_ASERT_CNT_LMT	REG32(MCHP_PROCHOT_BASE + 0x14)
-#define MCHP_PCHOT_TEST			REG32(MCHP_PROCHOT_BASE + 0x18)
+#define MCHP_PCHOT_CUM_CNT REG32(MCHP_PROCHOT_BASE + 0x00)
+#define MCHP_PCHOT_DTY_CYC_CNT REG32(MCHP_PROCHOT_BASE + 0x04)
+#define MCHP_PCHOT_DTY_PRD_CNT REG32(MCHP_PROCHOT_BASE + 0x08)
+#define MCHP_PCHOT_STS_CTRL REG32(MCHP_PROCHOT_BASE + 0x0C)
+#define MCHP_PCHOT_ASERT_CNT REG32(MCHP_PROCHOT_BASE + 0x10)
+#define MCHP_PCHOT_ASERT_CNT_LMT REG32(MCHP_PROCHOT_BASE + 0x14)
+#define MCHP_PCHOT_TEST REG32(MCHP_PROCHOT_BASE + 0x18)
 
 /* I2C registers access given controller base address */
-#define MCHP_I2C_CTRL(addr)		REG8(addr)
-#define MCHP_I2C_STATUS(addr)		REG8(addr)
-#define MCHP_I2C_OWN_ADDR(addr)		REG16(addr + 0x4)
-#define MCHP_I2C_DATA(addr)		REG8(addr + 0x8)
-#define MCHP_I2C_MASTER_CMD(addr)	REG32(addr + 0xc)
-#define MCHP_I2C_SLAVE_CMD(addr)	REG32(addr + 0x10)
-#define MCHP_I2C_PEC(addr)		REG8(addr + 0x14)
-#define MCHP_I2C_DATA_TIM_2(addr)	REG8(addr + 0x18)
-#define MCHP_I2C_COMPLETE(addr)		REG32(addr + 0x20)
-#define MCHP_I2C_IDLE_SCALE(addr)	REG32(addr + 0x24)
-#define MCHP_I2C_CONFIG(addr)		REG32(addr + 0x28)
-#define MCHP_I2C_BUS_CLK(addr)		REG16(addr + 0x2c)
-#define MCHP_I2C_BLK_ID(addr)		REG8(addr + 0x30)
-#define MCHP_I2C_REV(addr)		REG8(addr + 0x34)
-#define MCHP_I2C_BB_CTRL(addr)		REG8(addr + 0x38)
-#define MCHP_I2C_TST_DATA_TIM(addr)	REG32(addr + 0x3c)
-#define MCHP_I2C_DATA_TIM(addr)		REG32(addr + 0x40)
-#define MCHP_I2C_TOUT_SCALE(addr)	REG32(addr + 0x44)
-#define MCHP_I2C_SLAVE_TX_BUF(addr)	REG8(addr + 0x48)
-#define MCHP_I2C_SLAVE_RX_BUF(addr)	REG8(addr + 0x4c)
-#define MCHP_I2C_MASTER_TX_BUF(addr)	REG8(addr + 0x50)
-#define MCHP_I2C_MASTER_RX_BUF(addr)	REG8(addr + 0x54)
-#define MCHP_I2C_TEST_1(addr)		REG32(addr + 0x58)
-#define MCHP_I2C_TEST_2(addr)		REG32(addr + 0x5c)
-#define MCHP_I2C_WAKE_STS(addr)		REG8(addr + 0x60)
-#define MCHP_I2C_WAKE_EN(addr)		REG8(addr + 0x64)
-#define MCHP_I2C_TEST_3(addr)		REG32(addr + 0x68)
+#define MCHP_I2C_CTRL(addr) REG8(addr)
+#define MCHP_I2C_STATUS(addr) REG8(addr)
+#define MCHP_I2C_OWN_ADDR(addr) REG16(addr + 0x4)
+#define MCHP_I2C_DATA(addr) REG8(addr + 0x8)
+#define MCHP_I2C_MASTER_CMD(addr) REG32(addr + 0xc)
+#define MCHP_I2C_SLAVE_CMD(addr) REG32(addr + 0x10)
+#define MCHP_I2C_PEC(addr) REG8(addr + 0x14)
+#define MCHP_I2C_DATA_TIM_2(addr) REG8(addr + 0x18)
+#define MCHP_I2C_COMPLETE(addr) REG32(addr + 0x20)
+#define MCHP_I2C_IDLE_SCALE(addr) REG32(addr + 0x24)
+#define MCHP_I2C_CONFIG(addr) REG32(addr + 0x28)
+#define MCHP_I2C_BUS_CLK(addr) REG16(addr + 0x2c)
+#define MCHP_I2C_BLK_ID(addr) REG8(addr + 0x30)
+#define MCHP_I2C_REV(addr) REG8(addr + 0x34)
+#define MCHP_I2C_BB_CTRL(addr) REG8(addr + 0x38)
+#define MCHP_I2C_TST_DATA_TIM(addr) REG32(addr + 0x3c)
+#define MCHP_I2C_DATA_TIM(addr) REG32(addr + 0x40)
+#define MCHP_I2C_TOUT_SCALE(addr) REG32(addr + 0x44)
+#define MCHP_I2C_SLAVE_TX_BUF(addr) REG8(addr + 0x48)
+#define MCHP_I2C_SLAVE_RX_BUF(addr) REG8(addr + 0x4c)
+#define MCHP_I2C_MASTER_TX_BUF(addr) REG8(addr + 0x50)
+#define MCHP_I2C_MASTER_RX_BUF(addr) REG8(addr + 0x54)
+#define MCHP_I2C_TEST_1(addr) REG32(addr + 0x58)
+#define MCHP_I2C_TEST_2(addr) REG32(addr + 0x5c)
+#define MCHP_I2C_WAKE_STS(addr) REG8(addr + 0x60)
+#define MCHP_I2C_WAKE_EN(addr) REG8(addr + 0x64)
+#define MCHP_I2C_TEST_3(addr) REG32(addr + 0x68)
 
 /* Keyboard scan matrix */
-#define MCHP_KS_KSO_SEL			REG32(MCHP_KEYSCAN_BASE + 0x4)
-#define MCHP_KS_KSI_INPUT		REG32(MCHP_KEYSCAN_BASE + 0x8)
-#define MCHP_KS_KSI_STATUS		REG32(MCHP_KEYSCAN_BASE + 0xc)
-#define MCHP_KS_KSI_INT_EN		REG32(MCHP_KEYSCAN_BASE + 0x10)
-#define MCHP_KS_EXT_CTRL		REG32(MCHP_KEYSCAN_BASE + 0x14)
+#define MCHP_KS_KSO_SEL REG32(MCHP_KEYSCAN_BASE + 0x4)
+#define MCHP_KS_KSI_INPUT REG32(MCHP_KEYSCAN_BASE + 0x8)
+#define MCHP_KS_KSI_STATUS REG32(MCHP_KEYSCAN_BASE + 0xc)
+#define MCHP_KS_KSI_INT_EN REG32(MCHP_KEYSCAN_BASE + 0x10)
+#define MCHP_KS_EXT_CTRL REG32(MCHP_KEYSCAN_BASE + 0x14)
 
 /* ADC */
-#define MCHP_ADC_CTRL		REG32(MCHP_ADC_BASE + 0x0)
-#define MCHP_ADC_DELAY		REG32(MCHP_ADC_BASE + 0x4)
-#define MCHP_ADC_STS		REG32(MCHP_ADC_BASE + 0x8)
-#define MCHP_ADC_SINGLE		REG32(MCHP_ADC_BASE + 0xc)
-#define MCHP_ADC_REPEAT		REG32(MCHP_ADC_BASE + 0x10)
-#define MCHP_ADC_READ(x)	REG32(MCHP_ADC_BASE + 0x14 + ((x) * 0x4))
+#define MCHP_ADC_CTRL REG32(MCHP_ADC_BASE + 0x0)
+#define MCHP_ADC_DELAY REG32(MCHP_ADC_BASE + 0x4)
+#define MCHP_ADC_STS REG32(MCHP_ADC_BASE + 0x8)
+#define MCHP_ADC_SINGLE REG32(MCHP_ADC_BASE + 0xc)
+#define MCHP_ADC_REPEAT REG32(MCHP_ADC_BASE + 0x10)
+#define MCHP_ADC_READ(x) REG32(MCHP_ADC_BASE + 0x14 + ((x)*0x4))
 
 /* Hibernation timer */
-#define MCHP_HTIMER_PRELOAD(x)		REG16(MCHP_HTIMER_ADDR(x) + 0x0)
-#define MCHP_HTIMER_CONTROL(x)		REG16(MCHP_HTIMER_ADDR(x) + 0x4)
-#define MCHP_HTIMER_COUNT(x)		REG16(MCHP_HTIMER_ADDR(x) + 0x8)
+#define MCHP_HTIMER_PRELOAD(x) REG16(MCHP_HTIMER_ADDR(x) + 0x0)
+#define MCHP_HTIMER_CONTROL(x) REG16(MCHP_HTIMER_ADDR(x) + 0x4)
+#define MCHP_HTIMER_COUNT(x) REG16(MCHP_HTIMER_ADDR(x) + 0x8)
 
 /* Week timer and BGPO control */
-#define MCHP_WKTIMER_CTRL		REG32(MCHP_WKTIMER_BASE + 0)
-#define MCHP_WKTIMER_ALARM_CNT		REG32(MCHP_WKTIMER_BASE + 0x04)
-#define MCHP_WKTIMER_COMPARE		REG32(MCHP_WKTIMER_BASE + 0x08)
-#define MCHP_WKTIMER_CLK_DIV		REG32(MCHP_WKTIMER_BASE + 0x0c)
-#define MCHP_WKTIMER_SUBSEC_ISEL	REG32(MCHP_WKTIMER_BASE + 0x10)
-#define MCHP_WKTIMER_SUBWK_CTRL		REG32(MCHP_WKTIMER_BASE + 0x14)
-#define MCHP_WKTIMER_SUBWK_ALARM	REG32(MCHP_WKTIMER_BASE + 0x18)
-#define MCHP_WKTIMER_BGPO_DATA		REG32(MCHP_WKTIMER_BASE + 0x1c)
-#define MCHP_WKTIMER_BGPO_POWER		REG32(MCHP_WKTIMER_BASE + 0x20)
-#define MCHP_WKTIMER_BGPO_RESET		REG32(MCHP_WKTIMER_BASE + 0x24)
+#define MCHP_WKTIMER_CTRL REG32(MCHP_WKTIMER_BASE + 0)
+#define MCHP_WKTIMER_ALARM_CNT REG32(MCHP_WKTIMER_BASE + 0x04)
+#define MCHP_WKTIMER_COMPARE REG32(MCHP_WKTIMER_BASE + 0x08)
+#define MCHP_WKTIMER_CLK_DIV REG32(MCHP_WKTIMER_BASE + 0x0c)
+#define MCHP_WKTIMER_SUBSEC_ISEL REG32(MCHP_WKTIMER_BASE + 0x10)
+#define MCHP_WKTIMER_SUBWK_CTRL REG32(MCHP_WKTIMER_BASE + 0x14)
+#define MCHP_WKTIMER_SUBWK_ALARM REG32(MCHP_WKTIMER_BASE + 0x18)
+#define MCHP_WKTIMER_BGPO_DATA REG32(MCHP_WKTIMER_BASE + 0x1c)
+#define MCHP_WKTIMER_BGPO_POWER REG32(MCHP_WKTIMER_BASE + 0x20)
+#define MCHP_WKTIMER_BGPO_RESET REG32(MCHP_WKTIMER_BASE + 0x24)
 
 /* Quad Master SPI (QMSPI) */
-#define MCHP_QMSPI0_MODE		REG32(MCHP_QMSPI0_BASE + 0x00)
-#define MCHP_QMSPI0_MODE_ACT_SRST	REG8(MCHP_QMSPI0_BASE + 0x00)
-#define MCHP_QMSPI0_MODE_SPI_MODE	REG8(MCHP_QMSPI0_BASE + 0x01)
-#define MCHP_QMSPI0_MODE_FDIV		REG8(MCHP_QMSPI0_BASE + 0x02)
-#define MCHP_QMSPI0_CTRL		REG32(MCHP_QMSPI0_BASE + 0x04)
-#define MCHP_QMSPI0_EXE			REG8(MCHP_QMSPI0_BASE + 0x08)
-#define MCHP_QMSPI0_IFCTRL		REG8(MCHP_QMSPI0_BASE + 0x0C)
-#define MCHP_QMSPI0_STS			REG32(MCHP_QMSPI0_BASE + 0x10)
-#define MCHP_QMSPI0_BUFCNT_STS		REG32(MCHP_QMSPI0_BASE + 0x14)
-#define MCHP_QMSPI0_IEN			REG32(MCHP_QMSPI0_BASE + 0x18)
-#define MCHP_QMSPI0_BUFCNT_TRIG		REG32(MCHP_QMSPI0_BASE + 0x1C)
-#define MCHP_QMSPI0_TX_FIFO_ADDR	(MCHP_QMSPI0_BASE + 0x20)
-#define MCHP_QMSPI0_TX_FIFO8		REG8(MCHP_QMSPI0_BASE + 0x20)
-#define MCHP_QMSPI0_TX_FIFO16		REG16(MCHP_QMSPI0_BASE + 0x20)
-#define MCHP_QMSPI0_TX_FIFO32		REG32(MCHP_QMSPI0_BASE + 0x20)
-#define MCHP_QMSPI0_RX_FIFO_ADDR	(MCHP_QMSPI0_BASE + 0x24)
-#define MCHP_QMSPI0_RX_FIFO8		REG8(MCHP_QMSPI0_BASE + 0x24)
-#define MCHP_QMSPI0_RX_FIFO16		REG16(MCHP_QMSPI0_BASE + 0x24)
-#define MCHP_QMSPI0_RX_FIFO32		REG32(MCHP_QMSPI0_BASE + 0x24)
-#define MCHP_QMSPI0_DESCR(x)		\
-	REG32(MCHP_QMSPI0_BASE + 0x30 + ((x) * 4))
+#define MCHP_QMSPI0_MODE REG32(MCHP_QMSPI0_BASE + 0x00)
+#define MCHP_QMSPI0_MODE_ACT_SRST REG8(MCHP_QMSPI0_BASE + 0x00)
+#define MCHP_QMSPI0_MODE_SPI_MODE REG8(MCHP_QMSPI0_BASE + 0x01)
+#define MCHP_QMSPI0_MODE_FDIV REG8(MCHP_QMSPI0_BASE + 0x02)
+#define MCHP_QMSPI0_CTRL REG32(MCHP_QMSPI0_BASE + 0x04)
+#define MCHP_QMSPI0_EXE REG8(MCHP_QMSPI0_BASE + 0x08)
+#define MCHP_QMSPI0_IFCTRL REG8(MCHP_QMSPI0_BASE + 0x0C)
+#define MCHP_QMSPI0_STS REG32(MCHP_QMSPI0_BASE + 0x10)
+#define MCHP_QMSPI0_BUFCNT_STS REG32(MCHP_QMSPI0_BASE + 0x14)
+#define MCHP_QMSPI0_IEN REG32(MCHP_QMSPI0_BASE + 0x18)
+#define MCHP_QMSPI0_BUFCNT_TRIG REG32(MCHP_QMSPI0_BASE + 0x1C)
+#define MCHP_QMSPI0_TX_FIFO_ADDR (MCHP_QMSPI0_BASE + 0x20)
+#define MCHP_QMSPI0_TX_FIFO8 REG8(MCHP_QMSPI0_BASE + 0x20)
+#define MCHP_QMSPI0_TX_FIFO16 REG16(MCHP_QMSPI0_BASE + 0x20)
+#define MCHP_QMSPI0_TX_FIFO32 REG32(MCHP_QMSPI0_BASE + 0x20)
+#define MCHP_QMSPI0_RX_FIFO_ADDR (MCHP_QMSPI0_BASE + 0x24)
+#define MCHP_QMSPI0_RX_FIFO8 REG8(MCHP_QMSPI0_BASE + 0x24)
+#define MCHP_QMSPI0_RX_FIFO16 REG16(MCHP_QMSPI0_BASE + 0x24)
+#define MCHP_QMSPI0_RX_FIFO32 REG32(MCHP_QMSPI0_BASE + 0x24)
+#define MCHP_QMSPI0_DESCR(x) REG32(MCHP_QMSPI0_BASE + 0x30 + ((x)*4))
 /* Bits in MCHP_QMSPI0_MODE */
-#define MCHP_QMSPI_M_ACTIVATE		BIT(0)
-#define MCHP_QMSPI_M_SOFT_RESET		BIT(1)
-#define MCHP_QMSPI_M_SPI_MODE_MASK	(0x7ul << 8)
-#define MCHP_QMSPI_M_SPI_MODE0		(0x0ul << 8)
-#define MCHP_QMSPI_M_SPI_MODE3		(0x3ul << 8)
-#define MCHP_QMSPI_M_SPI_MODE0_48M	(0x4ul << 8)
-#define MCHP_QMSPI_M_SPI_MODE3_48M	(0x7ul << 8)
+#define MCHP_QMSPI_M_ACTIVATE BIT(0)
+#define MCHP_QMSPI_M_SOFT_RESET BIT(1)
+#define MCHP_QMSPI_M_SPI_MODE_MASK (0x7ul << 8)
+#define MCHP_QMSPI_M_SPI_MODE0 (0x0ul << 8)
+#define MCHP_QMSPI_M_SPI_MODE3 (0x3ul << 8)
+#define MCHP_QMSPI_M_SPI_MODE0_48M (0x4ul << 8)
+#define MCHP_QMSPI_M_SPI_MODE3_48M (0x7ul << 8)
 /*
  * clock divider is 8-bit field in bits[23:16]
  * [1, 255] -> 48MHz / [1, 255], 0 -> 48MHz / 256
  */
-#define MCHP_QMSPI_M_CLKDIV_BITPOS	16
-#define MCHP_QMSPI_M_CLKDIV_48M		(1ul << 16)
-#define MCHP_QMSPI_M_CLKDIV_24M		(2ul << 16)
-#define MCHP_QMSPI_M_CLKDIV_16M		(3ul << 16)
-#define MCHP_QMSPI_M_CLKDIV_12M		(4ul << 16)
-#define MCHP_QMSPI_M_CLKDIV_8M		(6ul << 16)
-#define MCHP_QMSPI_M_CLKDIV_6M		(8ul << 16)
-#define MCHP_QMSPI_M_CLKDIV_1M		(48ul << 16)
-#define MCHP_QMSPI_M_CLKDIV_188K	(0x100ul << 16)
+#define MCHP_QMSPI_M_CLKDIV_BITPOS 16
+#define MCHP_QMSPI_M_CLKDIV_48M (1ul << 16)
+#define MCHP_QMSPI_M_CLKDIV_24M (2ul << 16)
+#define MCHP_QMSPI_M_CLKDIV_16M (3ul << 16)
+#define MCHP_QMSPI_M_CLKDIV_12M (4ul << 16)
+#define MCHP_QMSPI_M_CLKDIV_8M (6ul << 16)
+#define MCHP_QMSPI_M_CLKDIV_6M (8ul << 16)
+#define MCHP_QMSPI_M_CLKDIV_1M (48ul << 16)
+#define MCHP_QMSPI_M_CLKDIV_188K (0x100ul << 16)
 /* Bits in MCHP_QMSPI0_CTRL and MCHP_QMSPI_DESCR(x) */
-#define MCHP_QMSPI_C_1X			(0ul << 0) /* Full Duplex */
-#define MCHP_QMSPI_C_2X			(1ul << 0) /* Dual IO */
-#define MCHP_QMSPI_C_4X			(2ul << 0) /* Quad IO */
-#define MCHP_QMSPI_C_TX_DIS		(0ul << 2)
-#define MCHP_QMSPI_C_TX_DATA		(1ul << 2)
-#define MCHP_QMSPI_C_TX_ZEROS		(2ul << 2)
-#define MCHP_QMSPI_C_TX_ONES		(3ul << 2)
-#define MCHP_QMSPI_C_TX_DMA_DIS		(0ul << 4)
-#define MCHP_QMSPI_C_TX_DMA_1B		(1ul << 4)
-#define MCHP_QMSPI_C_TX_DMA_2B		(2ul << 4)
-#define MCHP_QMSPI_C_TX_DMA_4B		(3ul << 4)
-#define MCHP_QMSPI_C_TX_DMA_MASK	(3ul << 4)
-#define MCHP_QMSPI_C_RX_DIS		0
-#define MCHP_QMSPI_C_RX_EN		BIT(6)
-#define MCHP_QMSPI_C_RX_DMA_DIS		(0ul << 7)
-#define MCHP_QMSPI_C_RX_DMA_1B		(1ul << 7)
-#define MCHP_QMSPI_C_RX_DMA_2B		(2ul << 7)
-#define MCHP_QMSPI_C_RX_DMA_4B		(3ul << 7)
-#define MCHP_QMSPI_C_RX_DMA_MASK	(3ul << 7)
-#define MCHP_QMSPI_C_NO_CLOSE		0
-#define MCHP_QMSPI_C_CLOSE		BIT(9)
-#define MCHP_QMSPI_C_XFRU_BITS		(0ul << 10)
-#define MCHP_QMSPI_C_XFRU_1B		(1ul << 10)
-#define MCHP_QMSPI_C_XFRU_4B		(2ul << 10)
-#define MCHP_QMSPI_C_XFRU_16B		(3ul << 10)
-#define MCHP_QMSPI_C_XFRU_MASK		(3ul << 10)
+#define MCHP_QMSPI_C_1X (0ul << 0) /* Full Duplex */
+#define MCHP_QMSPI_C_2X (1ul << 0) /* Dual IO */
+#define MCHP_QMSPI_C_4X (2ul << 0) /* Quad IO */
+#define MCHP_QMSPI_C_TX_DIS (0ul << 2)
+#define MCHP_QMSPI_C_TX_DATA (1ul << 2)
+#define MCHP_QMSPI_C_TX_ZEROS (2ul << 2)
+#define MCHP_QMSPI_C_TX_ONES (3ul << 2)
+#define MCHP_QMSPI_C_TX_DMA_DIS (0ul << 4)
+#define MCHP_QMSPI_C_TX_DMA_1B (1ul << 4)
+#define MCHP_QMSPI_C_TX_DMA_2B (2ul << 4)
+#define MCHP_QMSPI_C_TX_DMA_4B (3ul << 4)
+#define MCHP_QMSPI_C_TX_DMA_MASK (3ul << 4)
+#define MCHP_QMSPI_C_RX_DIS 0
+#define MCHP_QMSPI_C_RX_EN BIT(6)
+#define MCHP_QMSPI_C_RX_DMA_DIS (0ul << 7)
+#define MCHP_QMSPI_C_RX_DMA_1B (1ul << 7)
+#define MCHP_QMSPI_C_RX_DMA_2B (2ul << 7)
+#define MCHP_QMSPI_C_RX_DMA_4B (3ul << 7)
+#define MCHP_QMSPI_C_RX_DMA_MASK (3ul << 7)
+#define MCHP_QMSPI_C_NO_CLOSE 0
+#define MCHP_QMSPI_C_CLOSE BIT(9)
+#define MCHP_QMSPI_C_XFRU_BITS (0ul << 10)
+#define MCHP_QMSPI_C_XFRU_1B (1ul << 10)
+#define MCHP_QMSPI_C_XFRU_4B (2ul << 10)
+#define MCHP_QMSPI_C_XFRU_16B (3ul << 10)
+#define MCHP_QMSPI_C_XFRU_MASK (3ul << 10)
 /* Control */
-#define MCHP_QMSPI_C_START_DESCR_BITPOS	12
-#define MCHP_QMSPI_C_START_DESCR_MASK	(0xFul << 12)
-#define MCHP_QMSPI_C_DESCR_MODE_EN	BIT(16)
+#define MCHP_QMSPI_C_START_DESCR_BITPOS 12
+#define MCHP_QMSPI_C_START_DESCR_MASK (0xFul << 12)
+#define MCHP_QMSPI_C_DESCR_MODE_EN BIT(16)
 /* Descriptors, indicates the current descriptor is the last */
-#define MCHP_QMSPI_C_NEXT_DESCR_BITPOS	12
-#define MCHP_QMSPI_C_NEXT_DESCR_MASK0	0xFul
-#define MCHP_QMSPI_C_NEXT_DESCR_MASK \
-	((MCHP_QMSPI_C_NEXT_DESCR_MASK0) << 12)
+#define MCHP_QMSPI_C_NEXT_DESCR_BITPOS 12
+#define MCHP_QMSPI_C_NEXT_DESCR_MASK0 0xFul
+#define MCHP_QMSPI_C_NEXT_DESCR_MASK ((MCHP_QMSPI_C_NEXT_DESCR_MASK0) << 12)
 #define MCHP_QMSPI_C_NXTD(n) ((n) << 12)
-#define MCHP_QMSPI_C_DESCR_LAST		BIT(16)
+#define MCHP_QMSPI_C_DESCR_LAST BIT(16)
 /*
  * Total transfer length is the count in this field
  * scaled by units in MCHP_QMSPI_CTRL_XFRU_xxxx
  */
-#define MCHP_QMSPI_C_NUM_UNITS_BITPOS	17
-#define MCHP_QMSPI_C_MAX_UNITS		0x7ffful
-#define MCHP_QMSPI_C_NUM_UNITS_MASK0	0x7ffful
-#define MCHP_QMSPI_C_NUM_UNITS_MASK \
-	((MCHP_QMSPI_C_NUM_UNITS_MASK0) << 17)
+#define MCHP_QMSPI_C_NUM_UNITS_BITPOS 17
+#define MCHP_QMSPI_C_MAX_UNITS 0x7ffful
+#define MCHP_QMSPI_C_NUM_UNITS_MASK0 0x7ffful
+#define MCHP_QMSPI_C_NUM_UNITS_MASK ((MCHP_QMSPI_C_NUM_UNITS_MASK0) << 17)
 /* Bits in MCHP_QMSPI0_EXE */
-#define MCHP_QMSPI_EXE_START		BIT(0)
-#define MCHP_QMSPI_EXE_STOP		BIT(1)
-#define MCHP_QMSPI_EXE_CLR_FIFOS	BIT(2)
+#define MCHP_QMSPI_EXE_START BIT(0)
+#define MCHP_QMSPI_EXE_STOP BIT(1)
+#define MCHP_QMSPI_EXE_CLR_FIFOS BIT(2)
 /* MCHP QMSPI FIFO Sizes */
-#define MCHP_QMSPI_TX_FIFO_LEN		8
-#define MCHP_QMSPI_RX_FIFO_LEN		8
+#define MCHP_QMSPI_TX_FIFO_LEN 8
+#define MCHP_QMSPI_RX_FIFO_LEN 8
 /* Bits in MCHP_QMSPI0_STS and MCHP_QMSPI0_IEN */
-#define MCHP_QMSPI_STS_DONE		BIT(0)
-#define MCHP_QMSPI_STS_DMA_DONE		BIT(1)
-#define MCHP_QMSPI_STS_TX_BUFF_ERR	BIT(2)
-#define MCHP_QMSPI_STS_RX_BUFF_ERR	BIT(3)
-#define MCHP_QMSPI_STS_PROG_ERR		BIT(4)
-#define MCHP_QMSPI_STS_TX_BUFF_FULL	BIT(8)
-#define MCHP_QMSPI_STS_TX_BUFF_EMPTY	BIT(9)
-#define MCHP_QMSPI_STS_TX_BUFF_REQ	BIT(10)
-#define MCHP_QMSPI_STS_TX_BUFF_STALL	BIT(11) /* status only */
-#define MCHP_QMSPI_STS_RX_BUFF_FULL	BIT(12)
-#define MCHP_QMSPI_STS_RX_BUFF_EMPTY	BIT(13)
-#define MCHP_QMSPI_STS_RX_BUFF_REQ	BIT(14)
-#define MCHP_QMSPI_STS_RX_BUFF_STALL	BIT(15) /* status only */
-#define MCHP_QMSPI_STS_ACTIVE		BIT(16) /* status only */
+#define MCHP_QMSPI_STS_DONE BIT(0)
+#define MCHP_QMSPI_STS_DMA_DONE BIT(1)
+#define MCHP_QMSPI_STS_TX_BUFF_ERR BIT(2)
+#define MCHP_QMSPI_STS_RX_BUFF_ERR BIT(3)
+#define MCHP_QMSPI_STS_PROG_ERR BIT(4)
+#define MCHP_QMSPI_STS_TX_BUFF_FULL BIT(8)
+#define MCHP_QMSPI_STS_TX_BUFF_EMPTY BIT(9)
+#define MCHP_QMSPI_STS_TX_BUFF_REQ BIT(10)
+#define MCHP_QMSPI_STS_TX_BUFF_STALL BIT(11) /* status only */
+#define MCHP_QMSPI_STS_RX_BUFF_FULL BIT(12)
+#define MCHP_QMSPI_STS_RX_BUFF_EMPTY BIT(13)
+#define MCHP_QMSPI_STS_RX_BUFF_REQ BIT(14)
+#define MCHP_QMSPI_STS_RX_BUFF_STALL BIT(15) /* status only */
+#define MCHP_QMSPI_STS_ACTIVE BIT(16) /* status only */
 /* Bits in MCHP_QMSPI0_BUFCNT (read-only) */
-#define MCHP_QMSPI_BUFCNT_TX_BITPOS	0
-#define MCHP_QMSPI_BUFCNT_TX_MASK	0xFFFFul
-#define MCHP_QMSPI_BUFCNT_RX_BITPOS	16
-#define MCHP_QMSPI_BUFCNT_RX_MASK	(0xFFFFul << 16)
-#define MCHP_QMSPI0_ID			0
+#define MCHP_QMSPI_BUFCNT_TX_BITPOS 0
+#define MCHP_QMSPI_BUFCNT_TX_MASK 0xFFFFul
+#define MCHP_QMSPI_BUFCNT_RX_BITPOS 16
+#define MCHP_QMSPI_BUFCNT_RX_MASK (0xFFFFul << 16)
+#define MCHP_QMSPI0_ID 0
 
 /* eSPI */
 /* eSPI IO Component */
 /* Peripheral Channel Registers */
-#define MCHP_ESPI_PC_STATUS		REG32(MCHP_ESPI_IO_BASE + 0x114)
-#define MCHP_ESPI_PC_IEN		REG32(MCHP_ESPI_IO_BASE + 0x118)
-#define MCHP_ESPI_PC_BAR_INHIBIT_LO	REG32(MCHP_ESPI_IO_BASE + 0x120)
-#define MCHP_ESPI_PC_BAR_INHIBIT_HI	REG32(MCHP_ESPI_IO_BASE + 0x124)
-#define MCHP_ESPI_PC_BAR_INIT_LD_0C	REG16(MCHP_ESPI_IO_BASE + 0x128)
-#define MCHP_ESPI_PC_EC_IRQ		REG8(MCHP_ESPI_IO_BASE + 0x12C)
+#define MCHP_ESPI_PC_STATUS REG32(MCHP_ESPI_IO_BASE + 0x114)
+#define MCHP_ESPI_PC_IEN REG32(MCHP_ESPI_IO_BASE + 0x118)
+#define MCHP_ESPI_PC_BAR_INHIBIT_LO REG32(MCHP_ESPI_IO_BASE + 0x120)
+#define MCHP_ESPI_PC_BAR_INHIBIT_HI REG32(MCHP_ESPI_IO_BASE + 0x124)
+#define MCHP_ESPI_PC_BAR_INIT_LD_0C REG16(MCHP_ESPI_IO_BASE + 0x128)
+#define MCHP_ESPI_PC_EC_IRQ REG8(MCHP_ESPI_IO_BASE + 0x12C)
 /* LTR Registers */
-#define MCHP_ESPI_IO_LTR_STATUS		REG16(MCHP_ESPI_IO_BASE + 0x220)
-#define MCHP_ESPI_IO_LTR_IEN		REG8(MCHP_ESPI_IO_BASE + 0x224)
-#define MCHP_ESPI_IO_LTR_CTRL		REG16(MCHP_ESPI_IO_BASE + 0x228)
-#define MCHP_ESPI_IO_LTR_MSG		REG16(MCHP_ESPI_IO_BASE + 0x22C)
+#define MCHP_ESPI_IO_LTR_STATUS REG16(MCHP_ESPI_IO_BASE + 0x220)
+#define MCHP_ESPI_IO_LTR_IEN REG8(MCHP_ESPI_IO_BASE + 0x224)
+#define MCHP_ESPI_IO_LTR_CTRL REG16(MCHP_ESPI_IO_BASE + 0x228)
+#define MCHP_ESPI_IO_LTR_MSG REG16(MCHP_ESPI_IO_BASE + 0x22C)
 /* OOB Channel Registers */
-#define MCHP_ESPI_OOB_RX_ADDR_LO	REG32(MCHP_ESPI_IO_BASE + 0x240)
-#define MCHP_ESPI_OOB_RX_ADDR_HI	REG32(MCHP_ESPI_IO_BASE + 0x244)
-#define MCHP_ESPI_OOB_TX_ADDR_LO	REG32(MCHP_ESPI_IO_BASE + 0x248)
-#define MCHP_ESPI_OOB_TX_ADDR_HI	REG32(MCHP_ESPI_IO_BASE + 0x24C)
-#define MCHP_ESPI_OOB_RX_LEN		REG32(MCHP_ESPI_IO_BASE + 0x250)
-#define MCHP_ESPI_OOB_TX_LEN		REG32(MCHP_ESPI_IO_BASE + 0x254)
-#define MCHP_ESPI_OOB_RX_CTL		REG32(MCHP_ESPI_IO_BASE + 0x258)
-#define MCHP_ESPI_OOB_RX_IEN		REG8(MCHP_ESPI_IO_BASE + 0x25C)
-#define MCHP_ESPI_OOB_RX_STATUS		REG32(MCHP_ESPI_IO_BASE + 0x260)
-#define MCHP_ESPI_OOB_TX_CTL		REG32(MCHP_ESPI_IO_BASE + 0x264)
-#define MCHP_ESPI_OOB_TX_IEN		REG8(MCHP_ESPI_IO_BASE + 0x268)
-#define MCHP_ESPI_OOB_TX_STATUS		REG32(MCHP_ESPI_IO_BASE + 0x26C)
+#define MCHP_ESPI_OOB_RX_ADDR_LO REG32(MCHP_ESPI_IO_BASE + 0x240)
+#define MCHP_ESPI_OOB_RX_ADDR_HI REG32(MCHP_ESPI_IO_BASE + 0x244)
+#define MCHP_ESPI_OOB_TX_ADDR_LO REG32(MCHP_ESPI_IO_BASE + 0x248)
+#define MCHP_ESPI_OOB_TX_ADDR_HI REG32(MCHP_ESPI_IO_BASE + 0x24C)
+#define MCHP_ESPI_OOB_RX_LEN REG32(MCHP_ESPI_IO_BASE + 0x250)
+#define MCHP_ESPI_OOB_TX_LEN REG32(MCHP_ESPI_IO_BASE + 0x254)
+#define MCHP_ESPI_OOB_RX_CTL REG32(MCHP_ESPI_IO_BASE + 0x258)
+#define MCHP_ESPI_OOB_RX_IEN REG8(MCHP_ESPI_IO_BASE + 0x25C)
+#define MCHP_ESPI_OOB_RX_STATUS REG32(MCHP_ESPI_IO_BASE + 0x260)
+#define MCHP_ESPI_OOB_TX_CTL REG32(MCHP_ESPI_IO_BASE + 0x264)
+#define MCHP_ESPI_OOB_TX_IEN REG8(MCHP_ESPI_IO_BASE + 0x268)
+#define MCHP_ESPI_OOB_TX_STATUS REG32(MCHP_ESPI_IO_BASE + 0x26C)
 /* Flash Channel Registers */
-#define MCHP_ESPI_FC_ADDR_LO		REG32(MCHP_ESPI_IO_BASE + 0x280)
-#define MCHP_ESPI_FC_ADDR_HI		REG32(MCHP_ESPI_IO_BASE + 0x284)
-#define MCHP_ESPI_FC_BUF_ADDR_LO	REG32(MCHP_ESPI_IO_BASE + 0x288)
-#define MCHP_ESPI_FC_BUF_ADDR_HI	REG32(MCHP_ESPI_IO_BASE + 0x28C)
-#define MCHP_ESPI_FC_XFR_LEN		REG32(MCHP_ESPI_IO_BASE + 0x290)
-#define MCHP_ESPI_FC_CTL		REG32(MCHP_ESPI_IO_BASE + 0x294)
-#define MCHP_ESPI_FC_IEN		REG8(MCHP_ESPI_IO_BASE + 0x298)
-#define MCHP_ESPI_FC_CONFIG		REG32(MCHP_ESPI_IO_BASE + 0x29C)
-#define MCHP_ESPI_FC_STATUS		REG32(MCHP_ESPI_IO_BASE + 0x2A0)
+#define MCHP_ESPI_FC_ADDR_LO REG32(MCHP_ESPI_IO_BASE + 0x280)
+#define MCHP_ESPI_FC_ADDR_HI REG32(MCHP_ESPI_IO_BASE + 0x284)
+#define MCHP_ESPI_FC_BUF_ADDR_LO REG32(MCHP_ESPI_IO_BASE + 0x288)
+#define MCHP_ESPI_FC_BUF_ADDR_HI REG32(MCHP_ESPI_IO_BASE + 0x28C)
+#define MCHP_ESPI_FC_XFR_LEN REG32(MCHP_ESPI_IO_BASE + 0x290)
+#define MCHP_ESPI_FC_CTL REG32(MCHP_ESPI_IO_BASE + 0x294)
+#define MCHP_ESPI_FC_IEN REG8(MCHP_ESPI_IO_BASE + 0x298)
+#define MCHP_ESPI_FC_CONFIG REG32(MCHP_ESPI_IO_BASE + 0x29C)
+#define MCHP_ESPI_FC_STATUS REG32(MCHP_ESPI_IO_BASE + 0x2A0)
 /* VWire Channel Registers */
-#define MCHP_ESPI_VW_STATUS		REG8(MCHP_ESPI_IO_BASE + 0x2B0)
+#define MCHP_ESPI_VW_STATUS REG8(MCHP_ESPI_IO_BASE + 0x2B0)
 /* Global Registers */
 /* 32-bit register containing CAP_ID/CAP0/CAP1/PC_CAP */
-#define MCHP_ESPI_IO_REG32_A		REG32(MCHP_ESPI_IO_BASE + 0x2E0)
-#define MCHP_ESPI_IO_CAP_ID		REG8(MCHP_ESPI_IO_BASE + 0x2E0)
-#define MCHP_ESPI_IO_CAP0		REG8(MCHP_ESPI_IO_BASE + 0x2E1)
-#define MCHP_ESPI_IO_CAP1		REG8(MCHP_ESPI_IO_BASE + 0x2E2)
-#define MCHP_ESPI_IO_PC_CAP		REG8(MCHP_ESPI_IO_BASE + 0x2E3)
+#define MCHP_ESPI_IO_REG32_A REG32(MCHP_ESPI_IO_BASE + 0x2E0)
+#define MCHP_ESPI_IO_CAP_ID REG8(MCHP_ESPI_IO_BASE + 0x2E0)
+#define MCHP_ESPI_IO_CAP0 REG8(MCHP_ESPI_IO_BASE + 0x2E1)
+#define MCHP_ESPI_IO_CAP1 REG8(MCHP_ESPI_IO_BASE + 0x2E2)
+#define MCHP_ESPI_IO_PC_CAP REG8(MCHP_ESPI_IO_BASE + 0x2E3)
 /* 32-bit register containing VW_CAP/OOB_CAP/FC_CAP/PC_READY */
-#define MCHP_ESPI_IO_REG32_B		REG32(MCHP_ESPI_IO_BASE + 0x2E4)
-#define MCHP_ESPI_IO_VW_CAP		REG8(MCHP_ESPI_IO_BASE + 0x2E4)
-#define MCHP_ESPI_IO_OOB_CAP		REG8(MCHP_ESPI_IO_BASE + 0x2E5)
-#define MCHP_ESPI_IO_FC_CAP		REG8(MCHP_ESPI_IO_BASE + 0x2E6)
-#define MCHP_ESPI_IO_PC_READY		REG8(MCHP_ESPI_IO_BASE + 0x2E7)
+#define MCHP_ESPI_IO_REG32_B REG32(MCHP_ESPI_IO_BASE + 0x2E4)
+#define MCHP_ESPI_IO_VW_CAP REG8(MCHP_ESPI_IO_BASE + 0x2E4)
+#define MCHP_ESPI_IO_OOB_CAP REG8(MCHP_ESPI_IO_BASE + 0x2E5)
+#define MCHP_ESPI_IO_FC_CAP REG8(MCHP_ESPI_IO_BASE + 0x2E6)
+#define MCHP_ESPI_IO_PC_READY REG8(MCHP_ESPI_IO_BASE + 0x2E7)
 /* 32-bit register containing OOB_READY/FC_READY/RESET_STATUS/RESET_IEN */
-#define MCHP_ESPI_IO_REG32_C		REG32(MCHP_ESPI_IO_BASE + 0x2E8)
-#define MCHP_ESPI_IO_OOB_READY		REG8(MCHP_ESPI_IO_BASE + 0x2E8)
-#define MCHP_ESPI_IO_FC_READY		REG8(MCHP_ESPI_IO_BASE + 0x2E9)
-#define MCHP_ESPI_IO_RESET_STATUS	REG8(MCHP_ESPI_IO_BASE + 0x2EA)
-#define MCHP_ESPI_IO_RESET_IEN		REG8(MCHP_ESPI_IO_BASE + 0x2EB)
+#define MCHP_ESPI_IO_REG32_C REG32(MCHP_ESPI_IO_BASE + 0x2E8)
+#define MCHP_ESPI_IO_OOB_READY REG8(MCHP_ESPI_IO_BASE + 0x2E8)
+#define MCHP_ESPI_IO_FC_READY REG8(MCHP_ESPI_IO_BASE + 0x2E9)
+#define MCHP_ESPI_IO_RESET_STATUS REG8(MCHP_ESPI_IO_BASE + 0x2EA)
+#define MCHP_ESPI_IO_RESET_IEN REG8(MCHP_ESPI_IO_BASE + 0x2EB)
 /* 32-bit register containing PLTRST_SRC/VW_READY */
-#define MCHP_ESPI_IO_REG32_D		REG32(MCHP_ESPI_IO_BASE + 0x2EC)
-#define MCHP_ESPI_IO_PLTRST_SRC		REG8(MCHP_ESPI_IO_BASE + 0x2EC)
-#define MCHP_ESPI_IO_VW_READY		REG8(MCHP_ESPI_IO_BASE + 0x2ED)
+#define MCHP_ESPI_IO_REG32_D REG32(MCHP_ESPI_IO_BASE + 0x2EC)
+#define MCHP_ESPI_IO_PLTRST_SRC REG8(MCHP_ESPI_IO_BASE + 0x2EC)
+#define MCHP_ESPI_IO_VW_READY REG8(MCHP_ESPI_IO_BASE + 0x2ED)
 /* Bits in MCHP_ESPI_IO_CAP0 */
-#define MCHP_ESPI_CAP0_PC_SUPP		0x01
-#define MCHP_ESPI_CAP0_VW_SUPP		0x02
-#define MCHP_ESPI_CAP0_OOB_SUPP		0x04
-#define MCHP_ESPI_CAP0_FC_SUPP		0x08
-#define MCHP_ESPI_CAP0_ALL_CHAN_SUPP	(MCHP_ESPI_CAP0_PC_SUPP | \
-					MCHP_ESPI_CAP0_VW_SUPP | \
-					MCHP_ESPI_CAP0_OOB_SUPP | \
-					MCHP_ESPI_CAP0_FC_SUPP)
+#define MCHP_ESPI_CAP0_PC_SUPP 0x01
+#define MCHP_ESPI_CAP0_VW_SUPP 0x02
+#define MCHP_ESPI_CAP0_OOB_SUPP 0x04
+#define MCHP_ESPI_CAP0_FC_SUPP 0x08
+#define MCHP_ESPI_CAP0_ALL_CHAN_SUPP                       \
+	(MCHP_ESPI_CAP0_PC_SUPP | MCHP_ESPI_CAP0_VW_SUPP | \
+	 MCHP_ESPI_CAP0_OOB_SUPP | MCHP_ESPI_CAP0_FC_SUPP)
 /* Bits in MCHP_ESPI_IO_CAP1 */
-#define MCHP_ESPI_CAP1_RW_MASK		0x37
-#define MCHP_ESPI_CAP1_MAX_FREQ_MASK	0x07
-#define MCHP_ESPI_CAP1_MAX_FREQ_20M	0
-#define MCHP_ESPI_CAP1_MAX_FREQ_25M	1
-#define MCHP_ESPI_CAP1_MAX_FREQ_33M	2
-#define MCHP_ESPI_CAP1_MAX_FREQ_50M	3
-#define MCHP_ESPI_CAP1_MAX_FREQ_66M	4
-#define MCHP_ESPI_CAP1_SINGLE_MODE	0
-#define MCHP_ESPI_CAP1_SINGLE_DUAL_MODE	BIT(0)
-#define MCHP_ESPI_CAP1_SINGLE_QUAD_MODE	BIT(1)
-#define MCHP_ESPI_CAP1_ALL_MODE		(MCHP_ESPI_CAP1_SINGLE_MODE | \
-					MCHP_ESPI_CAP1_SINGLE_DUAL_MODE | \
-					MCHP_ESPI_CAP1_SINGLE_QUAD_MODE)
-#define MCHP_ESPI_CAP1_IO_BITPOS	4
-#define MCHP_ESPI_CAP1_IO_MASK0		0x03
-#define MCHP_ESPI_CAP1_IO_MASK		(0x03ul << MCHP_ESPI_CAP1_IO_BITPOS)
-#define MCHP_ESPI_CAP1_IO1_VAL		0x00
-#define MCHP_ESPI_CAP1_IO12_VAL		0x01
-#define MCHP_ESPI_CAP1_IO24_VAL		0x02
-#define MCHP_ESPI_CAP1_IO124_VAL	0x03
-#define MCHP_ESPI_CAP1_IO1		(0x00 << 4)
-#define MCHP_ESPI_CAP1_IO12		(0x01 << 4)
-#define MCHP_ESPI_CAP1_IO24		(0x02 << 4)
-#define MCHP_ESPI_CAP1_IO124		(0x03 << 4)
+#define MCHP_ESPI_CAP1_RW_MASK 0x37
+#define MCHP_ESPI_CAP1_MAX_FREQ_MASK 0x07
+#define MCHP_ESPI_CAP1_MAX_FREQ_20M 0
+#define MCHP_ESPI_CAP1_MAX_FREQ_25M 1
+#define MCHP_ESPI_CAP1_MAX_FREQ_33M 2
+#define MCHP_ESPI_CAP1_MAX_FREQ_50M 3
+#define MCHP_ESPI_CAP1_MAX_FREQ_66M 4
+#define MCHP_ESPI_CAP1_SINGLE_MODE 0
+#define MCHP_ESPI_CAP1_SINGLE_DUAL_MODE BIT(0)
+#define MCHP_ESPI_CAP1_SINGLE_QUAD_MODE BIT(1)
+#define MCHP_ESPI_CAP1_ALL_MODE                                         \
+	(MCHP_ESPI_CAP1_SINGLE_MODE | MCHP_ESPI_CAP1_SINGLE_DUAL_MODE | \
+	 MCHP_ESPI_CAP1_SINGLE_QUAD_MODE)
+#define MCHP_ESPI_CAP1_IO_BITPOS 4
+#define MCHP_ESPI_CAP1_IO_MASK0 0x03
+#define MCHP_ESPI_CAP1_IO_MASK (0x03ul << MCHP_ESPI_CAP1_IO_BITPOS)
+#define MCHP_ESPI_CAP1_IO1_VAL 0x00
+#define MCHP_ESPI_CAP1_IO12_VAL 0x01
+#define MCHP_ESPI_CAP1_IO24_VAL 0x02
+#define MCHP_ESPI_CAP1_IO124_VAL 0x03
+#define MCHP_ESPI_CAP1_IO1 (0x00 << 4)
+#define MCHP_ESPI_CAP1_IO12 (0x01 << 4)
+#define MCHP_ESPI_CAP1_IO24 (0x02 << 4)
+#define MCHP_ESPI_CAP1_IO124 (0x03 << 4)
 /* Bits in MCHP_ESPI_IO_RESET_STATUS and MCHP_ESPI_IO_RESET_IEN */
-#define MCHP_ESPI_RST_PIN_MASK		BIT(1)
-#define MCHP_ESPI_RST_CHG_STS		BIT(0)
-#define MCHP_ESPI_RST_IEN		BIT(0)
+#define MCHP_ESPI_RST_PIN_MASK BIT(1)
+#define MCHP_ESPI_RST_CHG_STS BIT(0)
+#define MCHP_ESPI_RST_IEN BIT(0)
 /* Bits in MCHP_ESPI_IO_PLTRST_SRC */
-#define MCHP_ESPI_PLTRST_SRC_VW		0
-#define MCHP_ESPI_PLTRST_SRC_PIN	1
+#define MCHP_ESPI_PLTRST_SRC_VW 0
+#define MCHP_ESPI_PLTRST_SRC_PIN 1
 /*
  * eSPI Slave Activate Register
  * bit[0] = 0 de-active block is clock-gates
  * bit[0] = 1 block is powered and functional
  */
-#define MCHP_ESPI_ACTIVATE		REG8(MCHP_ESPI_IO_BASE + 0x330)
+#define MCHP_ESPI_ACTIVATE REG8(MCHP_ESPI_IO_BASE + 0x330)
 /*
  * IO BAR's starting at offset 0x134
  * b[16]=virtualized R/W
@@ -554,30 +549,24 @@
  * b[13:8]=Logical Device Number RO
  * b[7:0]=mask
  */
-#define MCHP_ESPI_IO_BAR_CTL(x)	\
-	REG32(MCHP_ESPI_IO_BASE + ((x) * 4) + 0x134)
+#define MCHP_ESPI_IO_BAR_CTL(x) REG32(MCHP_ESPI_IO_BASE + ((x)*4) + 0x134)
 /* access mask field of eSPI IO BAR Control register */
-#define MCHP_ESPI_IO_BAR_CTL_MASK(x) \
-	REG8(MCHP_ESPI_IO_BASE + ((x) * 4) + 0x134)
+#define MCHP_ESPI_IO_BAR_CTL_MASK(x) REG8(MCHP_ESPI_IO_BASE + ((x)*4) + 0x134)
 /*
  * IO BAR's starting at offset 0x334
  * b[31:16] = I/O address
  * b[15:1]=0 reserved
  * b[0] = valid
  */
-#define MCHP_ESPI_IO_BAR(x) REG32(MCHP_ESPI_IO_BASE + ((x) * 4) + 0x334)
-#define MCHP_ESPI_IO_BAR_VALID(x) \
-	REG8(MCHP_ESPI_IO_BASE + ((x) * 4) + 0x334)
-#define MCHP_ESPI_IO_BAR_ADDR_LSB(x) \
-	REG8(MCHP_ESPI_IO_BASE + ((x) * 4) + 0x336)
-#define MCHP_ESPI_IO_BAR_ADDR_MSB(x) \
-	REG8(MCHP_ESPI_IO_BASE + ((x) * 4) + 0x337)
-#define MCHP_ESPI_IO_BAR_ADDR(x) \
-	REG16(MCHP_ESPI_IO_BASE + ((x) * 4) + 0x336)
+#define MCHP_ESPI_IO_BAR(x) REG32(MCHP_ESPI_IO_BASE + ((x)*4) + 0x334)
+#define MCHP_ESPI_IO_BAR_VALID(x) REG8(MCHP_ESPI_IO_BASE + ((x)*4) + 0x334)
+#define MCHP_ESPI_IO_BAR_ADDR_LSB(x) REG8(MCHP_ESPI_IO_BASE + ((x)*4) + 0x336)
+#define MCHP_ESPI_IO_BAR_ADDR_MSB(x) REG8(MCHP_ESPI_IO_BASE + ((x)*4) + 0x337)
+#define MCHP_ESPI_IO_BAR_ADDR(x) REG16(MCHP_ESPI_IO_BASE + ((x)*4) + 0x336)
 /* eSPI Serial IRQ registers */
-#define MCHP_ESPI_IO_SERIRQ_REG(x)	REG8(MCHP_ESPI_IO_BASE + 0x3ac + (x))
+#define MCHP_ESPI_IO_SERIRQ_REG(x) REG8(MCHP_ESPI_IO_BASE + 0x3ac + (x))
 /* eSPI Virtual Wire Error Register */
-#define MCHP_ESPI_IO_VW_ERROR		REG8(MCHP_ESPI_IO_BASE + 0x3f0)
+#define MCHP_ESPI_IO_VW_ERROR REG8(MCHP_ESPI_IO_BASE + 0x3f0)
 /*
  * eSPI Logical Device Memory Host BAR's to specify Host memory
  * base address and valid bit.
@@ -586,16 +575,15 @@
  * b[15:1]=0(reserved)
  * b[79:16]=eSPI bus memory address(Host address space)
  */
-#define MCHP_ESPI_MBAR_VALID(x) \
-	REG8(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x130)
+#define MCHP_ESPI_MBAR_VALID(x) REG8(MCHP_ESPI_MEM_BASE + ((x)*10) + 0x130)
 #define MCHP_ESPI_MBAR_HOST_ADDR_0_15(x) \
-	REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x132)
+	REG16(MCHP_ESPI_MEM_BASE + ((x)*10) + 0x132)
 #define MCHP_ESPI_MBAR_HOST_ADDR_16_31(x) \
-	REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x134)
+	REG16(MCHP_ESPI_MEM_BASE + ((x)*10) + 0x134)
 #define MCHP_ESPI_MBAR_HOST_ADDR_32_47(x) \
-	REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x136)
+	REG16(MCHP_ESPI_MEM_BASE + ((x)*10) + 0x136)
 #define MCHP_ESPI_MBAR_HOST_ADDR_48_63(x) \
-	REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x138)
+	REG16(MCHP_ESPI_MEM_BASE + ((x)*10) + 0x138)
 /*
  * eSPI SRAM BAR's
  * b[0,3,8:15] = 0 reserved
@@ -603,28 +591,27 @@
  * b[7:4] = size
  * b[79:16] = Host address
  */
-#define MCHP_ESPI_SRAM_BAR_CFG(x) \
-	REG8(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x1ac)
+#define MCHP_ESPI_SRAM_BAR_CFG(x) REG8(MCHP_ESPI_MEM_BASE + ((x)*10) + 0x1ac)
 #define MCHP_ESPI_SRAM_BAR_ADDR_0_15(x) \
-	REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x1ae)
+	REG16(MCHP_ESPI_MEM_BASE + ((x)*10) + 0x1ae)
 #define MCHP_ESPI_SRAM_BAR_ADDR_16_31(x) \
-	REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x1b0)
+	REG16(MCHP_ESPI_MEM_BASE + ((x)*10) + 0x1b0)
 #define MCHP_ESPI_SRAM_BAR_ADDR_32_47(x) \
-	REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x1b2)
+	REG16(MCHP_ESPI_MEM_BASE + ((x)*10) + 0x1b2)
 #define MCHP_ESPI_SRAM_BAR_ADDR_48_63(x) \
-	REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x1b4)
+	REG16(MCHP_ESPI_MEM_BASE + ((x)*10) + 0x1b4)
 /* eSPI Memory Bus Master Registers */
-#define MCHP_ESPI_BM_STATUS		REG32(MCHP_ESPI_MEM_BASE + 0x200)
-#define MCHP_ESPI_BM_IEN		REG32(MCHP_ESPI_MEM_BASE + 0x204)
-#define MCHP_ESPI_BM_CONFIG		REG32(MCHP_ESPI_MEM_BASE + 0x208)
-#define MCHP_ESPI_BM1_CTL		REG32(MCHP_ESPI_MEM_BASE + 0x210)
-#define MCHP_ESPI_BM1_HOST_ADDR_LO	REG32(MCHP_ESPI_MEM_BASE + 0x214)
-#define MCHP_ESPI_BM1_HOST_ADDR_HI	REG32(MCHP_ESPI_MEM_BASE + 0x218)
-#define MCHP_ESPI_BM1_EC_ADDR		REG32(MCHP_ESPI_MEM_BASE + 0x21c)
-#define MCHP_ESPI_BM2_CTL		REG32(MCHP_ESPI_MEM_BASE + 0x224)
-#define MCHP_ESPI_BM2_HOST_ADDR_LO	REG32(MCHP_ESPI_MEM_BASE + 0x228)
-#define MCHP_ESPI_BM2_HOST_ADDR_HI	REG32(MCHP_ESPI_MEM_BASE + 0x22c)
-#define MCHP_ESPI_BM2_EC_ADDR		REG32(MCHP_ESPI_MEM_BASE + 0x230)
+#define MCHP_ESPI_BM_STATUS REG32(MCHP_ESPI_MEM_BASE + 0x200)
+#define MCHP_ESPI_BM_IEN REG32(MCHP_ESPI_MEM_BASE + 0x204)
+#define MCHP_ESPI_BM_CONFIG REG32(MCHP_ESPI_MEM_BASE + 0x208)
+#define MCHP_ESPI_BM1_CTL REG32(MCHP_ESPI_MEM_BASE + 0x210)
+#define MCHP_ESPI_BM1_HOST_ADDR_LO REG32(MCHP_ESPI_MEM_BASE + 0x214)
+#define MCHP_ESPI_BM1_HOST_ADDR_HI REG32(MCHP_ESPI_MEM_BASE + 0x218)
+#define MCHP_ESPI_BM1_EC_ADDR REG32(MCHP_ESPI_MEM_BASE + 0x21c)
+#define MCHP_ESPI_BM2_CTL REG32(MCHP_ESPI_MEM_BASE + 0x224)
+#define MCHP_ESPI_BM2_HOST_ADDR_LO REG32(MCHP_ESPI_MEM_BASE + 0x228)
+#define MCHP_ESPI_BM2_HOST_ADDR_HI REG32(MCHP_ESPI_MEM_BASE + 0x22c)
+#define MCHP_ESPI_BM2_EC_ADDR REG32(MCHP_ESPI_MEM_BASE + 0x230)
 /*
  * eSPI Memory BAR's for Logical Devices
  * b[0] = Valid
@@ -637,30 +624,29 @@
  *
  * BAR's start at offset 0x330
  */
-#define MCHP_ESPI_MBAR_EC_VSIZE(x) \
-	REG32(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x330)
+#define MCHP_ESPI_MBAR_EC_VSIZE(x) REG32(MCHP_ESPI_MEM_BASE + ((x)*10) + 0x330)
 #define MCHP_ESPI_MBAR_EC_ADDR_0_15(x) \
-	REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x332)
+	REG16(MCHP_ESPI_MEM_BASE + ((x)*10) + 0x332)
 #define MCHP_ESPI_MBAR_EC_ADDR_16_31(x) \
-	REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x334)
+	REG16(MCHP_ESPI_MEM_BASE + ((x)*10) + 0x334)
 #define MCHP_ESPI_MBAR_EC_ADDR_32_47(x) \
-	REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x336)
+	REG16(MCHP_ESPI_MEM_BASE + ((x)*10) + 0x336)
 
 /* eSPI Virtual Wire registers */
-#define MCHP_ESPI_MSVW_LEN	12
-#define MCHP_ESPI_SMVW_LEN	8
+#define MCHP_ESPI_MSVW_LEN 12
+#define MCHP_ESPI_SMVW_LEN 8
 
 #define MCHP_ESPI_MSVW_ADDR(n) \
 	((MCHP_ESPI_MSVW_BASE) + ((n) * (MCHP_ESPI_MSVW_LEN)))
 
 #define MCHP_ESPI_MSVW_MTOS_BITPOS 4
 
-#define MCHP_ESPI_MSVW_IRQSEL_LEVEL_LO		0
-#define MCHP_ESPI_MSVW_IRQSEL_LEVEL_HI		1
-#define MCHP_ESPI_MSVW_IRQSEL_DISABLED		4
-#define MCHP_ESPI_MSVW_IRQSEL_RISING		0x0d
-#define MCHP_ESPI_MSVW_IRQSEL_FALLING		0x0e
-#define MCHP_ESPI_MSVW_IRQSEL_BOTH_EDGES	0x0f
+#define MCHP_ESPI_MSVW_IRQSEL_LEVEL_LO 0
+#define MCHP_ESPI_MSVW_IRQSEL_LEVEL_HI 1
+#define MCHP_ESPI_MSVW_IRQSEL_DISABLED 4
+#define MCHP_ESPI_MSVW_IRQSEL_RISING 0x0d
+#define MCHP_ESPI_MSVW_IRQSEL_FALLING 0x0e
+#define MCHP_ESPI_MSVW_IRQSEL_BOTH_EDGES 0x0f
 
 /*
  * Mapping of eSPI Master Host VWire group indices to
@@ -668,73 +654,60 @@
  * MSVW_xy where xy = PCH VWire number.
  * Each PCH VWire number controls 4 virtual wires.
  */
-#define MSVW_H02	0
-#define MSVW_H03	1
-#define MSVW_H07	2
-#define MSVW_H41	3
-#define MSVW_H42	4
-#define MSVW_H43	5
-#define MSVW_H44	6
-#define MSVW_H47	7
-#define MSVW_H4A	8
-#define MSVW_HSPARE0	9
-#define MSVW_HSPARE1	10
-#define MSVW_MAX	11
+#define MSVW_H02 0
+#define MSVW_H03 1
+#define MSVW_H07 2
+#define MSVW_H41 3
+#define MSVW_H42 4
+#define MSVW_H43 5
+#define MSVW_H44 6
+#define MSVW_H47 7
+#define MSVW_H4A 8
+#define MSVW_HSPARE0 9
+#define MSVW_HSPARE1 10
+#define MSVW_MAX 11
 
 /* Access 32-bit word in 96-bit MSVW register. 0 <= w <= 2 */
-#define MSVW(id, w) \
-	REG32(MCHP_ESPI_MSVW_BASE + ((id) * 12) + (((w) & 0x03) * 4))
+#define MSVW(id, w) REG32(MCHP_ESPI_MSVW_BASE + ((id)*12) + (((w)&0x03) * 4))
 /* Access index value in byte 0 */
-#define MCHP_ESPI_VW_M2S_INDEX(id)	REG8(MCHP_ESPI_VW_BASE + ((id) * 12))
+#define MCHP_ESPI_VW_M2S_INDEX(id) REG8(MCHP_ESPI_VW_BASE + ((id)*12))
 /*
  * Access MTOS_SOURCE and MTOS_STATE in byte 1
  * MTOS_SOURCE = b[1:0] specifies reset source
  * MTOS_STATE = b[7:4] are states loaded into SRC[0:3] on reset event
  */
-#define MCHP_ESPI_VW_M2S_MTOS(id) \
-	REG8(MCHP_ESPI_VW_BASE + 1 + ((id) * 12))
+#define MCHP_ESPI_VW_M2S_MTOS(id) REG8(MCHP_ESPI_VW_BASE + 1 + ((id)*12))
 /*
  * Access Index, MTOS Source, and MTOS State as 16-bit quantity.
  * Index in b[7:0]
  * MTOS Source in b[9:8]
  * MTOS State in b[15:12]
  */
-#define MCHP_ESPI_VW_M2S_INDEX_MTOS(id) \
-	REG16(MCHP_ESPI_VW_BASE + ((id) * 12))
+#define MCHP_ESPI_VW_M2S_INDEX_MTOS(id) REG16(MCHP_ESPI_VW_BASE + ((id)*12))
 /* Access SRCn IRQ Select bit fields */
-#define MCHP_ESPI_VW_M2S_IRQSEL0(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 12) + 4)
-#define MCHP_ESPI_VW_M2S_IRQSEL1(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 12) + 5)
-#define MCHP_ESPI_VW_M2S_IRQSEL2(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 12) + 6)
-#define MCHP_ESPI_VW_M2S_IRQSEL3(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 12) + 7)
+#define MCHP_ESPI_VW_M2S_IRQSEL0(id) REG8(MCHP_ESPI_VW_BASE + ((id)*12) + 4)
+#define MCHP_ESPI_VW_M2S_IRQSEL1(id) REG8(MCHP_ESPI_VW_BASE + ((id)*12) + 5)
+#define MCHP_ESPI_VW_M2S_IRQSEL2(id) REG8(MCHP_ESPI_VW_BASE + ((id)*12) + 6)
+#define MCHP_ESPI_VW_M2S_IRQSEL3(id) REG8(MCHP_ESPI_VW_BASE + ((id)*12) + 7)
 #define MCHP_ESPI_VW_M2S_IRQSEL(id, src) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 12) + 4 + ((src) & 0x03))
-#define MCHP_ESPI_VW_M2S_IRQSEL_ALL(id) \
-	REG32(MCHP_ESPI_VW_BASE + ((id) * 12) + 4)
+	REG8(MCHP_ESPI_VW_BASE + ((id)*12) + 4 + ((src)&0x03))
+#define MCHP_ESPI_VW_M2S_IRQSEL_ALL(id) REG32(MCHP_ESPI_VW_BASE + ((id)*12) + 4)
 /* Access individual source bits */
-#define MCHP_ESPI_VW_M2S_SRC0(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 12) + 8)
-#define MCHP_ESPI_VW_M2S_SRC1(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 12) + 9)
-#define MCHP_ESPI_VW_M2S_SRC2(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 12) + 10)
-#define MCHP_ESPI_VW_M2S_SRC3(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 12) + 11)
+#define MCHP_ESPI_VW_M2S_SRC0(id) REG8(MCHP_ESPI_VW_BASE + ((id)*12) + 8)
+#define MCHP_ESPI_VW_M2S_SRC1(id) REG8(MCHP_ESPI_VW_BASE + ((id)*12) + 9)
+#define MCHP_ESPI_VW_M2S_SRC2(id) REG8(MCHP_ESPI_VW_BASE + ((id)*12) + 10)
+#define MCHP_ESPI_VW_M2S_SRC3(id) REG8(MCHP_ESPI_VW_BASE + ((id)*12) + 11)
 /*
  * Access all four Source bits as 32-bit value, Source bits are located
  * at bits[0, 8, 16, 24] of 32-bit word.
  */
-#define MCHP_ESPI_VW_M2S_SRC_ALL(id) \
-	REG32(MCHP_ESPI_VW_BASE + 8 + ((id) * 12))
+#define MCHP_ESPI_VW_M2S_SRC_ALL(id) REG32(MCHP_ESPI_VW_BASE + 8 + ((id)*12))
 /*
  * Access an individual Source bit as byte where
  * bit[0] contains the source bit.
  */
 #define MCHP_ESPI_VW_M2S_SRC(id, src) \
-	REG8(MCHP_ESPI_VW_BASE + 8 + ((id) * 8) + ((src) & 0x03))
+	REG8(MCHP_ESPI_VW_BASE + 8 + ((id)*8) + ((src)&0x03))
 
 /*
  * Indices of Slave to Master Virtual Wire registers.
@@ -745,124 +718,114 @@
  * MCHP maps Host indices into its Slave to Master
  * 64-bit registers.
  */
-#define SMVW_H04	0
-#define SMVW_H05	1
-#define SMVW_H06	2
-#define SMVW_H40	3
-#define SMVW_H45	4
-#define SMVW_H46	5
-#define SMVW_HSPARE6	6
-#define SMVW_HSPARE7	7
-#define SMVW_HSPARE8	8
-#define SMVW_HSPARE9	9
-#define SMVW_HSPARE10	10
-#define SMVW_MAX	11
+#define SMVW_H04 0
+#define SMVW_H05 1
+#define SMVW_H06 2
+#define SMVW_H40 3
+#define SMVW_H45 4
+#define SMVW_H46 5
+#define SMVW_HSPARE6 6
+#define SMVW_HSPARE7 7
+#define SMVW_HSPARE8 8
+#define SMVW_HSPARE9 9
+#define SMVW_HSPARE10 10
+#define SMVW_MAX 11
 
 /* Access 32-bit word of 64-bit SMVW register, 0 <= w <= 1 */
 #define SMVW(id, w) \
-	REG32(MCHP_ESPI_VW_BASE + ((id) * 8) + 0x200 + (((w) & 0x01) * 4))
+	REG32(MCHP_ESPI_VW_BASE + ((id)*8) + 0x200 + (((w)&0x01) * 4))
 /* Access Index in b[7:0] of byte 0 */
-#define MCHP_ESPI_VW_S2M_INDEX(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 8) + 0x200)
+#define MCHP_ESPI_VW_S2M_INDEX(id) REG8(MCHP_ESPI_VW_BASE + ((id)*8) + 0x200)
 /* Access STOM_SOURCE and STOM_STATE in byte 1
  * STOM_SOURCE = b[1:0]
  * STOM_STATE = b[7:4]
  */
-#define MCHP_ESPI_VW_S2M_STOM(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 8) + 0x201)
+#define MCHP_ESPI_VW_S2M_STOM(id) REG8(MCHP_ESPI_VW_BASE + ((id)*8) + 0x201)
 /* Access Index, STOM_SOURCE, and STOM_STATE in bytes[1:0]
  * Index = b[7:0]
  * STOM_SOURCE = b[9:8]
  * STOM_STATE = [15:12]
  */
 #define MCHP_ESPI_VW_S2M_INDEX_STOM(id) \
-	REG16(MCHP_ESPI_VW_BASE + ((id) * 8) + 0x200)
+	REG16(MCHP_ESPI_VW_BASE + ((id)*8) + 0x200)
 /* Access Change[0:3] RO bits. Set to 1 if any of SRC[0:3] change */
-#define MCHP_ESPI_VW_S2M_CHANGE(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 8) + 0x202)
+#define MCHP_ESPI_VW_S2M_CHANGE(id) REG8(MCHP_ESPI_VW_BASE + ((id)*8) + 0x202)
 /* Access individual SRC bits
  * bit[0] = SRCn
  */
-#define MCHP_ESPI_VW_S2M_SRC0(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 8) + 0x204)
-#define MCHP_ESPI_VW_S2M_SRC1(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 8) + 0x205)
-#define MCHP_ESPI_VW_S2M_SRC2(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 8) + 0x206)
-#define MCHP_ESPI_VW_S2M_SRC3(id) \
-	REG8(MCHP_ESPI_VW_BASE + ((id) * 8) + 0x207)
+#define MCHP_ESPI_VW_S2M_SRC0(id) REG8(MCHP_ESPI_VW_BASE + ((id)*8) + 0x204)
+#define MCHP_ESPI_VW_S2M_SRC1(id) REG8(MCHP_ESPI_VW_BASE + ((id)*8) + 0x205)
+#define MCHP_ESPI_VW_S2M_SRC2(id) REG8(MCHP_ESPI_VW_BASE + ((id)*8) + 0x206)
+#define MCHP_ESPI_VW_S2M_SRC3(id) REG8(MCHP_ESPI_VW_BASE + ((id)*8) + 0x207)
 /*
  * Access specified source bit as byte read/write.
  * Source bit is in bit[0] of byte.
  */
 #define MCHP_ESPI_VW_S2M_SRC(id, src) \
-	REG8(MCHP_ESPI_VW_BASE + 0x204 + ((id) * 8) + ((src) & 0x03))
+	REG8(MCHP_ESPI_VW_BASE + 0x204 + ((id)*8) + ((src)&0x03))
 /* Access SRC[0:3] as 32-bit word
  * SRC0 = b[0]
  * SRC1 = b[8]
  * SRC2 = b[16]
  * SRC3 = b[24]
  */
-#define MCHP_ESPI_VW_S2M_SRC_ALL(id) \
-	REG32(MCHP_ESPI_VW_BASE + ((id) * 8) + 0x204)
+#define MCHP_ESPI_VW_S2M_SRC_ALL(id) REG32(MCHP_ESPI_VW_BASE + ((id)*8) + 0x204)
 
 /* DMA */
 #define MCHP_DMA_MAIN_CTRL REG8(MCHP_DMA_BASE + 0x00)
 #define MCHP_DMA_MAIN_PKT_RO REG32(MCHP_DMA_BASE + 0x04)
 #define MCHP_DMA_MAIN_FSM_RO REG8(MCHP_DMA_BASE + 0x08)
 /* DMA Channel Registers */
-#define MCHP_DMA_CH_ACT(n) REG8(MCHP_DMA_CH_BASE + ((n) * MCHP_DMA_CH_OFS))
+#define MCHP_DMA_CH_ACT(n) REG8(MCHP_DMA_CH_BASE + ((n)*MCHP_DMA_CH_OFS))
 #define MCHP_DMA_CH_MEM_START(n) \
-	REG32(MCHP_DMA_CH_BASE + ((n) * MCHP_DMA_CH_OFS) + 0x04)
+	REG32(MCHP_DMA_CH_BASE + ((n)*MCHP_DMA_CH_OFS) + 0x04)
 #define MCHP_DMA_CH_MEM_END(n) \
-	REG32(MCHP_DMA_CH_BASE + ((n) * MCHP_DMA_CH_OFS) + 0x08)
+	REG32(MCHP_DMA_CH_BASE + ((n)*MCHP_DMA_CH_OFS) + 0x08)
 #define MCHP_DMA_CH_DEV_ADDR(n) \
-	REG32(MCHP_DMA_CH_BASE + ((n) * MCHP_DMA_CH_OFS) + 0x0c)
+	REG32(MCHP_DMA_CH_BASE + ((n)*MCHP_DMA_CH_OFS) + 0x0c)
 #define MCHP_DMA_CH_CTRL(n) \
-	REG32(MCHP_DMA_CH_BASE + ((n) * MCHP_DMA_CH_OFS) + 0x10)
+	REG32(MCHP_DMA_CH_BASE + ((n)*MCHP_DMA_CH_OFS) + 0x10)
 #define MCHP_DMA_CH_ISTS(n) \
-	REG32(MCHP_DMA_CH_BASE + ((n) * MCHP_DMA_CH_OFS) + 0x14)
+	REG32(MCHP_DMA_CH_BASE + ((n)*MCHP_DMA_CH_OFS) + 0x14)
 #define MCHP_DMA_CH_IEN(n) \
-	REG32(MCHP_DMA_CH_BASE + ((n) * MCHP_DMA_CH_OFS) + 0x18)
+	REG32(MCHP_DMA_CH_BASE + ((n)*MCHP_DMA_CH_OFS) + 0x18)
 #define MCHP_DMA_CH_FSM_RO(n) \
-	REG32(MCHP_DMA_CH_BASE + ((n) * MCHP_DMA_CH_OFS) + 0x1c)
+	REG32(MCHP_DMA_CH_BASE + ((n)*MCHP_DMA_CH_OFS) + 0x1c)
 /*
  * DMA Channel 0 implements CRC-32 feature
  */
-#define MCHP_DMA_CH0_CRC32_EN		REG8(MCHP_DMA_CH_BASE + 0x20)
-#define MCHP_DMA_CH0_CRC32_DATA		REG32(MCHP_DMA_CH_BASE + 0x24)
-#define MCHP_DMA_CH0_CRC32_POST_STS	REG8(MCHP_DMA_CH_BASE + 0x28)
+#define MCHP_DMA_CH0_CRC32_EN REG8(MCHP_DMA_CH_BASE + 0x20)
+#define MCHP_DMA_CH0_CRC32_DATA REG32(MCHP_DMA_CH_BASE + 0x24)
+#define MCHP_DMA_CH0_CRC32_POST_STS REG8(MCHP_DMA_CH_BASE + 0x28)
 /*
  * DMA Channel 1 implements memory fill feature
  */
-#define MCHP_DMA_CH1_FILL_EN \
-	REG8(MCHP_DMA_CH_BASE + MCHP_DMA_CH_OFS + 0x20)
-#define MCHP_DMA_CH1_FILL_DATA \
-	REG32(MCHP_DMA_CH_BASE + MCHP_DMA_CH_OFS + 0x24)
+#define MCHP_DMA_CH1_FILL_EN REG8(MCHP_DMA_CH_BASE + MCHP_DMA_CH_OFS + 0x20)
+#define MCHP_DMA_CH1_FILL_DATA REG32(MCHP_DMA_CH_BASE + MCHP_DMA_CH_OFS + 0x24)
 /* Bits for DMA Main Control */
-#define MCHP_DMA_MAIN_CTRL_ACT		BIT(0)
-#define MCHP_DMA_MAIN_CTRL_SRST		BIT(1)
+#define MCHP_DMA_MAIN_CTRL_ACT BIT(0)
+#define MCHP_DMA_MAIN_CTRL_SRST BIT(1)
 /* Bits for DMA channel regs */
-#define MCHP_DMA_ACT_EN			BIT(0)
+#define MCHP_DMA_ACT_EN BIT(0)
 /* DMA Channel Control */
-#define MCHP_DMA_ABORT			BIT(25)
-#define MCHP_DMA_SW_GO			BIT(24)
-#define MCHP_DMA_XFER_SIZE_MASK		(7ul << 20)
-#define MCHP_DMA_XFER_SIZE(x)		((x) << 20)
-#define MCHP_DMA_DIS_HW_FLOW		BIT(19)
-#define MCHP_DMA_INC_DEV		BIT(17)
-#define MCHP_DMA_INC_MEM		BIT(16)
-#define MCHP_DMA_DEV(x)			((x) << 9)
-#define MCHP_DMA_DEV_MASK0		(0x7f)
-#define MCHP_DMA_DEV_MASK		(0x7f << 9)
-#define MCHP_DMA_TO_DEV			BIT(8)
-#define MCHP_DMA_DONE			BIT(2)
-#define MCHP_DMA_RUN			BIT(0)
+#define MCHP_DMA_ABORT BIT(25)
+#define MCHP_DMA_SW_GO BIT(24)
+#define MCHP_DMA_XFER_SIZE_MASK (7ul << 20)
+#define MCHP_DMA_XFER_SIZE(x) ((x) << 20)
+#define MCHP_DMA_DIS_HW_FLOW BIT(19)
+#define MCHP_DMA_INC_DEV BIT(17)
+#define MCHP_DMA_INC_MEM BIT(16)
+#define MCHP_DMA_DEV(x) ((x) << 9)
+#define MCHP_DMA_DEV_MASK0 (0x7f)
+#define MCHP_DMA_DEV_MASK (0x7f << 9)
+#define MCHP_DMA_TO_DEV BIT(8)
+#define MCHP_DMA_DONE BIT(2)
+#define MCHP_DMA_RUN BIT(0)
 /* DMA Channel Status */
-#define MCHP_DMA_STS_ALU_DONE		BIT(3)
-#define MCHP_DMA_STS_DONE		BIT(2)
-#define MCHP_DMA_STS_HWFL_ERR		BIT(1)
-#define MCHP_DMA_STS_BUS_ERR		BIT(0)
+#define MCHP_DMA_STS_ALU_DONE BIT(3)
+#define MCHP_DMA_STS_DONE BIT(2)
+#define MCHP_DMA_STS_HWFL_ERR BIT(1)
+#define MCHP_DMA_STS_BUS_ERR BIT(0)
 
 /*
  * Required structure typedef for common/dma.h interface
@@ -871,19 +834,19 @@
  * We can't remove dma_chan_t as its used in DMA API header.
  */
 struct MCHP_dma_chan {
-	uint32_t act;		/* Activate */
-	uint32_t mem_start;	/* Memory start address */
-	uint32_t mem_end;	/* Memory end address */
-	uint32_t dev;		/* Device address */
-	uint32_t ctrl;		/* Control */
-	uint32_t int_status;	/* Interrupt status */
-	uint32_t int_enabled;	/* Interrupt enabled */
-	uint32_t chfsm;		/* channel fsm read-only */
-	uint32_t alu_en;	/* channels 0 & 1 only */
-	uint32_t alu_data;	/* channels 0 & 1 only */
-	uint32_t alu_sts;	/* channel 0 only */
-	uint32_t alu_ro;	/* channel 0 only */
-	uint32_t rsvd[4];	/* 0x30 - 0x3F */
+	uint32_t act; /* Activate */
+	uint32_t mem_start; /* Memory start address */
+	uint32_t mem_end; /* Memory end address */
+	uint32_t dev; /* Device address */
+	uint32_t ctrl; /* Control */
+	uint32_t int_status; /* Interrupt status */
+	uint32_t int_enabled; /* Interrupt enabled */
+	uint32_t chfsm; /* channel fsm read-only */
+	uint32_t alu_en; /* channels 0 & 1 only */
+	uint32_t alu_data; /* channels 0 & 1 only */
+	uint32_t alu_sts; /* channel 0 only */
+	uint32_t alu_ro; /* channel 0 only */
+	uint32_t rsvd[4]; /* 0x30 - 0x3F */
 };
 
 /* Common code and header file must use this */
diff --git a/chip/mchp/spi.c b/chip/mchp/spi.c
index 48712e8b7e..195c10d8a6 100644
--- a/chip/mchp/spi.c
+++ b/chip/mchp/spi.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,7 +23,7 @@
 #include "tfdp_chip.h"
 
 #define CPUTS(outstr) cputs(CC_SPI, outstr)
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SPI, format, ##args)
 
 #define SPI_BYTE_TRANSFER_TIMEOUT_US (3 * MSEC)
 #define SPI_BYTE_TRANSFER_POLL_INTERVAL_US 100
@@ -33,49 +33,31 @@
 #endif
 
 static const struct dma_option spi_rx_option[] = {
-	{
-		MCHP_DMAC_QMSPI0_RX,
-		(void *)(MCHP_QMSPI0_RX_FIFO_ADDR),
-		MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM
-	},
+	{ MCHP_DMAC_QMSPI0_RX, (void *)(MCHP_QMSPI0_RX_FIFO_ADDR),
+	  MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM },
 #if defined(CONFIG_MCHP_GPSPI) && !defined(LFW)
 #if CONFIG_MCHP_GPSPI & 0x01
-	{
-		MCHP_DMAC_SPI0_RX,
-		(void *)&MCHP_SPI_RD(0),
-		MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM
-	},
+	{ MCHP_DMAC_SPI0_RX, (void *)&MCHP_SPI_RD(0),
+	  MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM },
 #endif
 #if CONFIG_MCHP_GPSPI & 0x02
-	{
-		MCHP_DMAC_SPI1_RX,
-		(void *)&MCHP_SPI_RD(1),
-		MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM
-	},
+	{ MCHP_DMAC_SPI1_RX, (void *)&MCHP_SPI_RD(1),
+	  MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM },
 #endif
 #endif
 };
 
 static const struct dma_option spi_tx_option[] = {
-	{
-		MCHP_DMAC_QMSPI0_TX,
-		(void *)(MCHP_QMSPI0_TX_FIFO_ADDR),
-		MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM
-	},
+	{ MCHP_DMAC_QMSPI0_TX, (void *)(MCHP_QMSPI0_TX_FIFO_ADDR),
+	  MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM },
 #if defined(CONFIG_MCHP_GPSPI) && !defined(LFW)
 #if CONFIG_MCHP_GPSPI & 0x01
-	{
-		MCHP_DMAC_SPI0_TX,
-		(void *)&MCHP_SPI_TD(0),
-		MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM
-	},
+	{ MCHP_DMAC_SPI0_TX, (void *)&MCHP_SPI_TD(0),
+	  MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM },
 #endif
 #if CONFIG_MCHP_GPSPI & 0x02
-	{
-		MCHP_DMAC_SPI1_TX,
-		(void *)&MCHP_SPI_TD(1),
-		MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM
-	},
+	{ MCHP_DMAC_SPI1_TX, (void *)&MCHP_SPI_TD(1),
+	  MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM },
 #endif
 #endif
 };
@@ -131,8 +113,7 @@ static void spi_mutex_unlock(uint8_t hw_port)
  * Public SPI interface
  */
 
-const void *spi_dma_option(const struct spi_device_t *spi_device,
-				int is_tx)
+const void *spi_dma_option(const struct spi_device_t *spi_device, int is_tx)
 {
 	uint32_t n;
 
@@ -157,8 +138,8 @@ const void *spi_dma_option(const struct spi_device_t *spi_device,
 }
 
 int spi_transaction_async(const struct spi_device_t *spi_device,
-				const uint8_t *txdata, int txlen,
-				uint8_t *rxdata, int rxlen)
+			  const uint8_t *txdata, int txlen, uint8_t *rxdata,
+			  int rxlen)
 {
 	int rc;
 
@@ -169,13 +150,13 @@ int spi_transaction_async(const struct spi_device_t *spi_device,
 #if defined(CONFIG_MCHP_GPSPI) && !defined(LFW)
 	case GPSPI0_PORT:
 	case GPSPI1_PORT:
-		rc = gpspi_transaction_async(spi_device, txdata,
-				txlen, rxdata, rxlen);
+		rc = gpspi_transaction_async(spi_device, txdata, txlen, rxdata,
+					     rxlen);
 		break;
 #endif
 	case QMSPI0_PORT:
-		rc = qmspi_transaction_async(spi_device, txdata,
-				txlen, rxdata, rxlen);
+		rc = qmspi_transaction_async(spi_device, txdata, txlen, rxdata,
+					     rxlen);
 		break;
 	default:
 		rc = EC_ERROR_INVAL;
@@ -243,8 +224,8 @@ int spi_transaction_wait(const struct spi_device_t *spi_device)
  * without the overhead of DMA setup.
  */
 int spi_transaction(const struct spi_device_t *spi_device,
-		    const uint8_t *txdata, int txlen,
-		    uint8_t *rxdata, int rxlen)
+		    const uint8_t *txdata, int txlen, uint8_t *rxdata,
+		    int rxlen)
 {
 	int rc;
 
diff --git a/chip/mchp/spi_chip.h b/chip/mchp/spi_chip.h
index 167a9cdf4a..f8c4c1169c 100644
--- a/chip/mchp/spi_chip.h
+++ b/chip/mchp/spi_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,28 +19,27 @@
 /* struct spi_device_t */
 #include "spi.h"
 
-#define SPI_DMA_OPTION_RD	0
-#define SPI_DMA_OPTION_WR	1
+#define SPI_DMA_OPTION_RD 0
+#define SPI_DMA_OPTION_WR 1
 
 /*
  * bits[3:0] = controller instance
  * bits[7:4] = controller family
  * 0 = QMSPI, 1 = GPSPI
  */
-#define QMSPI0_PORT	0x00
-#define GPSPI0_PORT	0x10
-#define GPSPI1_PORT	0x11
+#define QMSPI0_PORT 0x00
+#define GPSPI0_PORT 0x10
+#define GPSPI1_PORT 0x11
 
+#define QMSPI_CLASS0 0
+#define GPSPI_CLASS0 1
 
-#define QMSPI_CLASS0	0
-#define GPSPI_CLASS0	1
+#define QMSPI_CLASS (0 << 4)
+#define GPSPI_CLASS BIT(4)
 
-#define QMSPI_CLASS	(0 << 4)
-#define GPSPI_CLASS	BIT(4)
-
-#define QMSPI_CTRL0	0
-#define GPSPI_CTRL0	0
-#define GPSPI_CTRL1	1
+#define QMSPI_CTRL0 0
+#define GPSPI_CTRL0 0
+#define GPSPI_CTRL1 1
 
 /*
  * Encode zero based controller class and instance values
@@ -51,8 +50,7 @@
 /*
  * helper to return pointer to QMSPI or GPSPI struct dma_option
  */
-const void *spi_dma_option(const struct spi_device_t *spi_device,
-				int is_tx);
+const void *spi_dma_option(const struct spi_device_t *spi_device, int is_tx);
 
 #endif /* #ifndef _QMSPI_CHIP_H */
 /**   @}
diff --git a/chip/mchp/system.c b/chip/mchp/system.c
index 72c96bef8f..bb5224c455 100644
--- a/chip/mchp/system.c
+++ b/chip/mchp/system.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,15 +26,15 @@
 #include "util.h"
 
 #define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args)
 
 /* Index values for hibernate data registers (RAM backed by VBAT) */
 enum hibdata_index {
-	HIBDATA_INDEX_SCRATCHPAD = 0,    /* General-purpose scratch pad */
+	HIBDATA_INDEX_SCRATCHPAD = 0, /* General-purpose scratch pad */
 	HIBDATA_INDEX_SAVED_RESET_FLAGS, /* Saved reset flags */
-	HIBDATA_INDEX_PD0,		/* USB-PD0 saved port state */
-	HIBDATA_INDEX_PD1,		/* USB-PD1 saved port state */
-	HIBDATA_INDEX_PD2,		/* USB-PD2 saved port state */
+	HIBDATA_INDEX_PD0, /* USB-PD0 saved port state */
+	HIBDATA_INDEX_PD1, /* USB-PD1 saved port state */
+	HIBDATA_INDEX_PD2, /* USB-PD2 saved port state */
 };
 
 /*
@@ -47,7 +47,7 @@ enum hibdata_index {
 #ifdef CHIP_FAMILY_MEC172X
 static void vtr3_voltage_select(int use18v)
 {
-	(void) use18v;
+	(void)use18v;
 }
 #else
 static void vtr3_voltage_select(int use18v)
@@ -59,7 +59,6 @@ static void vtr3_voltage_select(int use18v)
 }
 #endif
 
-
 /*
  * The current logic will set EC_RESET_FLAG_RESET_PIN flag
  * even if the reset was caused by WDT. MEC170x/MEC152x HW RESET_SYS
@@ -76,8 +75,7 @@ static void check_reset_cause(void)
 	uint32_t status = MCHP_VBAT_STS;
 	uint32_t flags = 0;
 	uint32_t rst_sts = MCHP_PCR_PWR_RST_STS &
-				(MCHP_PWR_RST_STS_SYS |
-				MCHP_PWR_RST_STS_VBAT);
+			   (MCHP_PWR_RST_STS_SYS | MCHP_PWR_RST_STS_VBAT);
 
 	/* Clear the reset causes now that we've read them */
 	MCHP_VBAT_STS |= status;
@@ -92,13 +90,12 @@ static void check_reset_cause(void)
 	if (rst_sts & MCHP_PWR_RST_STS_SYS)
 		flags |= EC_RESET_FLAG_RESET_PIN;
 
-
 	flags |= chip_read_reset_flags();
 	chip_save_reset_flags(0);
 
-	if ((status & MCHP_VBAT_STS_WDT) && !(flags & (EC_RESET_FLAG_SOFT |
-					    EC_RESET_FLAG_HARD |
-					    EC_RESET_FLAG_HIBERNATE)))
+	if ((status & MCHP_VBAT_STS_WDT) &&
+	    !(flags & (EC_RESET_FLAG_SOFT | EC_RESET_FLAG_HARD |
+		       EC_RESET_FLAG_HIBERNATE)))
 		flags |= EC_RESET_FLAG_WATCHDOG;
 
 	system_set_reset_flags(flags);
@@ -115,10 +112,10 @@ int system_is_reboot_warm(void)
 	reset_flags = system_get_reset_flags();
 
 	if ((reset_flags & EC_RESET_FLAG_RESET_PIN) ||
-		(reset_flags & EC_RESET_FLAG_POWER_ON) ||
-		(reset_flags & EC_RESET_FLAG_WATCHDOG) ||
-		(reset_flags & EC_RESET_FLAG_HARD) ||
-		(reset_flags & EC_RESET_FLAG_SOFT))
+	    (reset_flags & EC_RESET_FLAG_POWER_ON) ||
+	    (reset_flags & EC_RESET_FLAG_WATCHDOG) ||
+	    (reset_flags & EC_RESET_FLAG_HARD) ||
+	    (reset_flags & EC_RESET_FLAG_SOFT))
 		return 0;
 	else
 		return 1;
@@ -174,7 +171,7 @@ void system_pre_init(void)
 	 * Signals bus fault to Cortex-M4 core if an address presented
 	 * to AHB is not claimed by any HW block.
 	 */
-	MCHP_EC_AHB_ERR = 0;	/* write any value to clear */
+	MCHP_EC_AHB_ERR = 0; /* write any value to clear */
 	MCHP_EC_AHB_ERR_EN = 0; /* enable capture of address on error */
 
 	/* Manual voltage selection only required for MEC170x and MEC152x */
@@ -435,13 +432,12 @@ static void disable_host_ifc_clocks(void)
 #else
 static void disable_host_ifc_clocks(void)
 {
-	#ifdef CHIP_FAMILY_MEC170X
+#ifdef CHIP_FAMILY_MEC170X
 	MCHP_LPC_ACT &= ~0x1;
-	#endif
+#endif
 }
 #endif
 
-
 /*
  * Called when hibernation timer is not used in deep sleep.
  * Switch 32 KHz clock logic from external 32KHz input to
@@ -450,7 +446,9 @@ static void disable_host_ifc_clocks(void)
  * oscillator.
  */
 #ifdef CHIP_FAMILY_MEC172X
-static void switch_32k_pin2sil(void) {}
+static void switch_32k_pin2sil(void)
+{
+}
 #else
 static void switch_32k_pin2sil(void)
 {
@@ -483,7 +481,7 @@ void system_hibernate(uint32_t seconds, uint32_t microseconds)
 
 	for (i = MCHP_INT_GIRQ_FIRST; i <= MCHP_INT_GIRQ_LAST; ++i) {
 		MCHP_INT_DISABLE(i) = 0xffffffff;
-		MCHP_INT_SOURCE(i)  = 0xffffffff;
+		MCHP_INT_SOURCE(i) = 0xffffffff;
 	}
 
 	/* Disable UART */
@@ -549,7 +547,7 @@ void system_hibernate(uint32_t seconds, uint32_t microseconds)
 	MCHP_PCR_SYS_SLP_CTL = MCHP_PCR_SYS_SLP_ALL;
 
 	asm("dsb");
-	asm("wfi");
+	cpu_enter_suspend_mode();
 	asm("isb");
 	asm("nop");
 
@@ -577,14 +575,14 @@ enum ec_image system_get_shrspi_image_copy(void)
 
 uint32_t system_get_lfw_address(void)
 {
-	uint32_t * const lfw_vector =
-		(uint32_t * const)CONFIG_PROGRAM_MEMORY_BASE;
+	uint32_t *const lfw_vector =
+		(uint32_t *const)CONFIG_PROGRAM_MEMORY_BASE;
 
 	return *(lfw_vector + 1);
 }
 
 void system_set_image_copy(enum ec_image copy)
 {
-	MCHP_VBAT_RAM(MCHP_IMAGETYPE_IDX) = (copy == EC_IMAGE_RW) ?
-				EC_IMAGE_RW : EC_IMAGE_RO;
+	MCHP_VBAT_RAM(MCHP_IMAGETYPE_IDX) =
+		(copy == EC_IMAGE_RW) ? EC_IMAGE_RW : EC_IMAGE_RO;
 }
diff --git a/chip/mchp/tfdp.c b/chip/mchp/tfdp.c
index b4368b46a8..eb9b903cb5 100644
--- a/chip/mchp/tfdp.c
+++ b/chip/mchp/tfdp.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,12 +17,11 @@
 
 #ifdef CONFIG_MCHP_TFDP
 
-
 static uint32_t get_disable_intr(void)
 {
 	uint32_t m;
 
-	__asm__ __volatile__ ("mrs %0, primask;cpsid i" : "=r" (m));
+	__asm__ __volatile__("mrs %0, primask;cpsid i" : "=r"(m));
 
 	return m;
 }
@@ -30,10 +29,9 @@ static uint32_t get_disable_intr(void)
 static void restore_intr(uint32_t m)
 {
 	if (!m)
-		__asm__ __volatile__ ("cpsie i" : : : "memory");
+		__asm__ __volatile__("cpsie i" : : : "memory");
 }
 
-
 /**
  * tfdp_power - Gate clocks On/Off to TFDP block when idle
  *
@@ -48,7 +46,6 @@ void tfdp_power(uint8_t pwr_on)
 		MCHP_PCR_SLP_EN_DEV(MCHP_PCR_TFDP);
 }
 
-
 /**
  * tfdp_enable - Init Trace FIFO Data Port
  * @param uint8_t non-zero=enable TFDP, false=disable TFDP
@@ -57,8 +54,8 @@ void tfdp_power(uint8_t pwr_on)
  * Else GPIO170/171 set to GPIO input, internal pull-up enabled.
  * @note -
  */
-#define MCHP_TFDP_DATA	REG8(MCHP_TFDP_BASE + 0x00)
-#define MCHP_TFDP_CTRL	REG8(MCHP_TFDP_BASE + 0x04)
+#define MCHP_TFDP_DATA REG8(MCHP_TFDP_BASE + 0x00)
+#define MCHP_TFDP_CTRL REG8(MCHP_TFDP_BASE + 0x04)
 
 void tfdp_enable(uint8_t en, uint8_t pin_cfg)
 {
@@ -73,7 +70,6 @@ void tfdp_enable(uint8_t en, uint8_t pin_cfg)
 	}
 } /* end tfdp_enable() */
 
-
 /**
  * TFDPTrace0 - TRACE0: transmit 16-bit trace number lsb first
  * over TFDP.
@@ -106,7 +102,6 @@ void TFDPTrace0(uint16_t nbr)
 #endif
 }
 
-
 /**
  * TRDPTrace1 - TRACE1: transmit 16-bit trace number lsb first
  * and 16-bit data lsb first over TFDP.
@@ -144,7 +139,6 @@ void TFDPTrace1(uint16_t nbr, uint32_t p1)
 #endif
 }
 
-
 /**
  * TFDPTrace2 - TRACE2: transmit 16-bit trace number lsb first
  * and two 16-bit data parameters lsb first over TFDP.
@@ -187,7 +181,6 @@ void TFDPTrace2(uint16_t nbr, uint32_t p1, uint32_t p2)
 #endif
 }
 
-
 /**
  * TFDPTrace3 - TRACE3: transmit 16-bit trace number lsb first
  * and three 16-bit data parameters lsb first over TFDP.
@@ -203,8 +196,7 @@ void TFDPTrace2(uint16_t nbr, uint32_t p1, uint32_t p2)
  *       interrupts for critical section. These may use
  *       priviledged instructions.
  */
-void TFDPTrace3(uint16_t nbr, uint32_t p1,
-		uint32_t p2, uint32_t p3)
+void TFDPTrace3(uint16_t nbr, uint32_t p1, uint32_t p2, uint32_t p3)
 {
 #ifdef MCHP_TRACE_MASK_IRQ
 	uint32_t prim;
@@ -236,7 +228,6 @@ void TFDPTrace3(uint16_t nbr, uint32_t p1,
 #endif
 }
 
-
 /**
  * TFDPTrace4 - TRACE3: transmit 16-bit trace number lsb first
  * and four 16-bit data parameters lsb first over TFDP.
@@ -253,8 +244,8 @@ void TFDPTrace3(uint16_t nbr, uint32_t p1,
  *       interrupts for critical section. These may use
  *       priviledged instructions.
  */
-void TFDPTrace4(uint16_t nbr, uint32_t p1, uint32_t p2,
-		 uint32_t p3, uint32_t p4)
+void TFDPTrace4(uint16_t nbr, uint32_t p1, uint32_t p2, uint32_t p3,
+		uint32_t p4)
 {
 #ifdef MCHP_TRACE_MASK_IRQ
 	uint32_t prim;
@@ -290,7 +281,6 @@ void TFDPTrace4(uint16_t nbr, uint32_t p1, uint32_t p2,
 #endif
 }
 
-
 /**
  *  TFDPTrace11 - Transmit one 32-bit data item over TFDP
  *
@@ -327,7 +317,6 @@ void TFDPTrace11(uint16_t nbr, uint32_t p1)
 #endif
 }
 
-
 /**
  *  TFDPTrace12 - Transmit two 32-bit data items over TFDP
  *
@@ -383,8 +372,7 @@ void TFDPTrace12(uint16_t nbr, uint32_t p1, uint32_t p2)
  *  @param uint32_t p3 32-bit data3 to be transmitted
  *
  */
-void TFDPTrace13(uint16_t nbr, uint32_t p1,
-		 uint32_t p2, uint32_t p3)
+void TFDPTrace13(uint16_t nbr, uint32_t p1, uint32_t p2, uint32_t p3)
 {
 #ifdef MCHP_TRACE_MASK_IRQ
 	uint32_t prim;
@@ -438,8 +426,8 @@ void TFDPTrace13(uint16_t nbr, uint32_t p1,
  *  @param uint32_t p3 32-bit data3 to be transmitted
  *  @param uint32_t p4 32-bit data4 to be transmitted
  */
-void TFDPTrace14(uint16_t nbr, uint32_t p1, uint32_t p2,
-		 uint32_t p3, uint32_t p4)
+void TFDPTrace14(uint16_t nbr, uint32_t p1, uint32_t p2, uint32_t p3,
+		 uint32_t p4)
 {
 #ifdef MCHP_TRACE_MASK_IRQ
 	uint32_t prim;
@@ -493,7 +481,6 @@ void TFDPTrace14(uint16_t nbr, uint32_t p1, uint32_t p2,
 
 #endif /* #ifdef CONFIG_MCHP_TFDP */
 
-
 /* end tfdp.c */
 /**   @}
  */
diff --git a/chip/mchp/tfdp_chip.h b/chip/mchp/tfdp_chip.h
index 64d4d0b77e..894bfaf876 100644
--- a/chip/mchp/tfdp_chip.h
+++ b/chip/mchp/tfdp_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,7 +13,6 @@
 
 #include <stdint.h>
 
-
 #ifdef CONFIG_MCHP_TFDP
 
 #undef TRACE0
@@ -35,19 +34,19 @@
 #undef trace13
 #undef trace14
 
-#define MCHP_TFDP_BASE_ADDR	(0x40008c00ul)
+#define MCHP_TFDP_BASE_ADDR (0x40008c00ul)
 
-#define TFDP_FRAME_START   (0xFD)
+#define TFDP_FRAME_START (0xFD)
 
-#define TFDP_POWER_ON   (1u)
-#define TFDP_POWER_OFF  (0u)
+#define TFDP_POWER_ON (1u)
+#define TFDP_POWER_OFF (0u)
 
-#define TFDP_ENABLE         (1u)
-#define TFDP_DISABLE        (0u)
-#define TFDP_CFG_PINS       (1u)
-#define TFDP_NO_CFG_PINS    (0u)
+#define TFDP_ENABLE (1u)
+#define TFDP_DISABLE (0u)
+#define TFDP_CFG_PINS (1u)
+#define TFDP_NO_CFG_PINS (0u)
 
-#define  MCHP_TRACE_MASK_IRQ
+#define MCHP_TRACE_MASK_IRQ
 
 #define TFDP_DELAY()
 
@@ -59,18 +58,15 @@ void tfdp_power(uint8_t pwr_on);
 void tfdp_enable(uint8_t en, uint8_t pin_cfg);
 void TFDPTrace0(uint16_t nbr);
 void TFDPTrace1(uint16_t nbr, uint32_t p1);
-void TFDPTrace2(uint16_t nbr, uint32_t p1,
-		uint32_t p2);
-void TFDPTrace3(uint16_t nbr, uint32_t p1,
-		uint32_t p2, uint32_t p3);
-void TFDPTrace4(uint16_t nbr, uint32_t p1, uint32_t p2,
-		uint32_t p3, uint32_t p4);
+void TFDPTrace2(uint16_t nbr, uint32_t p1, uint32_t p2);
+void TFDPTrace3(uint16_t nbr, uint32_t p1, uint32_t p2, uint32_t p3);
+void TFDPTrace4(uint16_t nbr, uint32_t p1, uint32_t p2, uint32_t p3,
+		uint32_t p4);
 void TFDPTrace11(uint16_t nbr, uint32_t p1);
 void TFDPTrace12(uint16_t nbr, uint32_t p1, uint32_t p2);
-void TFDPTrace13(uint16_t nbr, uint32_t p1, uint32_t p2,
-		 uint32_t p3);
-void TFDPTrace14(uint16_t nbr, uint32_t p1, uint32_t p2,
-		 uint32_t p3, uint32_t p4);
+void TFDPTrace13(uint16_t nbr, uint32_t p1, uint32_t p2, uint32_t p3);
+void TFDPTrace14(uint16_t nbr, uint32_t p1, uint32_t p2, uint32_t p3,
+		 uint32_t p4);
 
 #ifdef __cplusplus
 }
@@ -80,15 +76,13 @@ void TFDPTrace14(uint16_t nbr, uint32_t p1, uint32_t p2,
 #define TRACE1(nbr, cat, b, str, p1) TFDPTrace1(nbr, p1)
 #define TRACE2(nbr, cat, b, str, p1, p2) TFDPTrace2(nbr, p1, p2)
 #define TRACE3(nbr, cat, b, str, p1, p2, p3) TFDPTrace3(nbr, p1, p2, p3)
-#define TRACE4(nbr, cat, b, str, p1, p2, p3, p4) TFDPTrace4(nbr, p1, p2, \
-	p3, p4)
+#define TRACE4(nbr, cat, b, str, p1, p2, p3, p4) TFDPTrace4(nbr, p1, p2, p3, p4)
 #define TRACE11(nbr, cat, b, str, p1) TFDPTrace11(nbr, p1)
 #define TRACE12(nbr, cat, b, str, p1, p2) TFDPTrace12(nbr, p1, p2)
 #define TRACE13(nbr, cat, b, str, p1, p2, p3) TFDPTrace13(nbr, p1, p2, p3)
 #define TRACE14(nbr, cat, b, str, p1, p2, p3, p4) \
 	TFDPTrace14(nbr, p1, p2, p3, p4)
 
-
 #else /* #ifdef MCHP_TRACE */
 
 /* !!! To prevent compiler warnings of unused parameters,
diff --git a/chip/mchp/uart.c b/chip/mchp/uart.c
index c274519b94..00bfc77e14 100644
--- a/chip/mchp/uart.c
+++ b/chip/mchp/uart.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,40 +17,40 @@
 #include "util.h"
 #include "tfdp_chip.h"
 
-#define TX_FIFO_SIZE	16
+#define TX_FIFO_SIZE 16
 
 BUILD_ASSERT((CONFIG_UART_CONSOLE >= 0) &&
 	     (CONFIG_UART_CONSOLE < MCHP_UART_INSTANCES));
 
 #if CONFIG_UART_CONSOLE == 2
 
-#define UART_IRQ		MCHP_IRQ_UART2
-#define UART_IRQ_BIT		MCHP_UART2_GIRQ_BIT
-#define UART_PCR		MCHP_PCR_UART2
-#define GPIO_UART_RX		GPIO_UART2_RX
+#define UART_IRQ MCHP_IRQ_UART2
+#define UART_IRQ_BIT MCHP_UART2_GIRQ_BIT
+#define UART_PCR MCHP_PCR_UART2
+#define GPIO_UART_RX GPIO_UART2_RX
 /* MEC152x only. UART2 RX Pin = GPIO 0145 GIRQ08 bit[5] */
-#define UART_RX_PIN_GIRQ	8
-#define UART_RX_PIN_BIT		BIT(5)
+#define UART_RX_PIN_GIRQ 8
+#define UART_RX_PIN_BIT BIT(5)
 
 #elif CONFIG_UART_CONSOLE == 1
 
-#define UART_IRQ		MCHP_IRQ_UART1
-#define UART_IRQ_BIT		MCHP_UART1_GIRQ_BIT
-#define UART_PCR		MCHP_PCR_UART1
-#define GPIO_UART_RX		GPIO_UART1_RX
+#define UART_IRQ MCHP_IRQ_UART1
+#define UART_IRQ_BIT MCHP_UART1_GIRQ_BIT
+#define UART_PCR MCHP_PCR_UART1
+#define GPIO_UART_RX GPIO_UART1_RX
 /* MEC152x and MEC170x UART1 RX Pin = GPIO 0171. GIRQ08 bit[25] */
-#define UART_RX_PIN_GIRQ	8
-#define UART_RX_PIN_BIT		BIT(25)
+#define UART_RX_PIN_GIRQ 8
+#define UART_RX_PIN_BIT BIT(25)
 
 #else
 
-#define UART_IRQ		MCHP_IRQ_UART0
-#define UART_IRQ_BIT		MCHP_UART0_GIRQ_BIT
-#define UART_PCR		MCHP_PCR_UART0
-#define GPIO_UART_RX		GPIO_UART0_RX
+#define UART_IRQ MCHP_IRQ_UART0
+#define UART_IRQ_BIT MCHP_UART0_GIRQ_BIT
+#define UART_PCR MCHP_PCR_UART0
+#define GPIO_UART_RX GPIO_UART0_RX
 /* MEC152x and MEC170x UART0 RX Pin = GPIO 0105. GIRQ09 bit[5] */
-#define UART_RX_PIN_GIRQ	9
-#define UART_RX_PIN_BIT		BIT(5)
+#define UART_RX_PIN_GIRQ 9
+#define UART_RX_PIN_BIT BIT(5)
 
 #endif /* CONFIG_UART_CONSOLE == 2 */
 
@@ -103,7 +103,7 @@ int uart_tx_ready(void)
 	 * this, we check transmit FIFO empty bit every 16 characters written.
 	 */
 	return tx_fifo_used != 0 ||
-		(MCHP_UART_LSR(CONFIG_UART_CONSOLE) & MCHP_LSR_TX_EMPTY);
+	       (MCHP_UART_LSR(CONFIG_UART_CONSOLE) & MCHP_LSR_TX_EMPTY);
 }
 
 int uart_tx_in_progress(void)
@@ -212,7 +212,7 @@ void uart_init(void)
 void uart_enter_dsleep(void)
 {
 	/* Disable the UART interrupt. */
-	task_disable_irq(UART_IRQ);  /* NVIC interrupt for UART=13 */
+	task_disable_irq(UART_IRQ); /* NVIC interrupt for UART=13 */
 
 	/*
 	 * Set the UART0 RX pin to be a GPIO-162(fixed pin) interrupt
@@ -233,7 +233,6 @@ void uart_enter_dsleep(void)
 	gpio_enable_interrupt(GPIO_UART_RX);
 }
 
-
 void uart_exit_dsleep(void)
 {
 	/*
diff --git a/chip/mchp/util/pack_ec.py b/chip/mchp/util/pack_ec.py
index 7908b0bf37..1b0a2e9959 100755
--- a/chip/mchp/util/pack_ec.py
+++ b/chip/mchp/util/pack_ec.py
@@ -1,12 +1,8 @@
 #!/usr/bin/env python3
 
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
+# Copyright 2013 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
 
 # A script to pack EC binary into SPI flash image for MEC17xx
 # Based on MEC170x_ROM_Description.pdf DS00002225C (07-28-17).
@@ -16,7 +12,7 @@ import os
 import struct
 import subprocess
 import tempfile
-import zlib # CRC32
+import zlib  # CRC32
 
 # MEC1701 has 256KB SRAM from 0xE0000 - 0x120000
 # SRAM is divided into contiguous CODE & DATA
@@ -30,165 +26,199 @@ LOAD_ADDR = 0x0E0000
 LOAD_ADDR_RW = 0xE1000
 HEADER_SIZE = 0x40
 SPI_CLOCK_LIST = [48, 24, 16, 12]
-SPI_READ_CMD_LIST = [0x3, 0xb, 0x3b, 0x6b]
+SPI_READ_CMD_LIST = [0x3, 0xB, 0x3B, 0x6B]
+
+CRC_TABLE = [
+    0x00,
+    0x07,
+    0x0E,
+    0x09,
+    0x1C,
+    0x1B,
+    0x12,
+    0x15,
+    0x38,
+    0x3F,
+    0x36,
+    0x31,
+    0x24,
+    0x23,
+    0x2A,
+    0x2D,
+]
 
-CRC_TABLE = [0x00, 0x07, 0x0e, 0x09, 0x1c, 0x1b, 0x12, 0x15,
-             0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d]
 
 def mock_print(*args, **kwargs):
-  pass
+    pass
+
 
 debug_print = mock_print
 
+
 def Crc8(crc, data):
-  """Update CRC8 value."""
-  for v in data:
-    crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v >> 4)]);
-    crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v & 0xf)]);
-  return crc ^ 0x55
+    """Update CRC8 value."""
+    for v in data:
+        crc = ((crc << 4) & 0xFF) ^ (CRC_TABLE[(crc >> 4) ^ (v >> 4)])
+        crc = ((crc << 4) & 0xFF) ^ (CRC_TABLE[(crc >> 4) ^ (v & 0xF)])
+    return crc ^ 0x55
+
 
 def GetEntryPoint(payload_file):
-  """Read entry point from payload EC image."""
-  with open(payload_file, 'rb') as f:
-    f.seek(4)
-    s = f.read(4)
-  return struct.unpack('<I', s)[0]
+    """Read entry point from payload EC image."""
+    with open(payload_file, "rb") as f:
+        f.seek(4)
+        s = f.read(4)
+    return struct.unpack("<I", s)[0]
+
 
 def GetPayloadFromOffset(payload_file, offset):
-  """Read payload and pad it to 64-byte aligned."""
-  with open(payload_file, 'rb') as f:
-    f.seek(offset)
-    payload = bytearray(f.read())
-  rem_len = len(payload) % 64
-  if rem_len:
-    payload += b'\0' * (64 - rem_len)
-  return payload
+    """Read payload and pad it to 64-byte aligned."""
+    with open(payload_file, "rb") as f:
+        f.seek(offset)
+        payload = bytearray(f.read())
+    rem_len = len(payload) % 64
+    if rem_len:
+        payload += b"\0" * (64 - rem_len)
+    return payload
+
 
 def GetPayload(payload_file):
-  """Read payload and pad it to 64-byte aligned."""
-  return GetPayloadFromOffset(payload_file, 0)
+    """Read payload and pad it to 64-byte aligned."""
+    return GetPayloadFromOffset(payload_file, 0)
+
 
 def GetPublicKey(pem_file):
-  """Extract public exponent and modulus from PEM file."""
-  result = subprocess.run(['openssl', 'rsa', '-in', pem_file, '-text',
-                           '-noout'], stdout=subprocess.PIPE, encoding='utf-8')
-  modulus_raw = []
-  in_modulus = False
-  for line in result.stdout.splitlines():
-    if line.startswith('modulus'):
-      in_modulus = True
-    elif not line.startswith(' '):
-      in_modulus = False
-    elif in_modulus:
-      modulus_raw.extend(line.strip().strip(':').split(':'))
-    if line.startswith('publicExponent'):
-      exp = int(line.split(' ')[1], 10)
-  modulus_raw.reverse()
-  modulus = bytearray((int(x, 16) for x in modulus_raw[:256]))
-  return struct.pack('<Q', exp), modulus
+    """Extract public exponent and modulus from PEM file."""
+    result = subprocess.run(
+        ["openssl", "rsa", "-in", pem_file, "-text", "-noout"],
+        stdout=subprocess.PIPE,
+        encoding="utf-8",
+    )
+    modulus_raw = []
+    in_modulus = False
+    for line in result.stdout.splitlines():
+        if line.startswith("modulus"):
+            in_modulus = True
+        elif not line.startswith(" "):
+            in_modulus = False
+        elif in_modulus:
+            modulus_raw.extend(line.strip().strip(":").split(":"))
+        if line.startswith("publicExponent"):
+            exp = int(line.split(" ")[1], 10)
+    modulus_raw.reverse()
+    modulus = bytearray((int(x, 16) for x in modulus_raw[:256]))
+    return struct.pack("<Q", exp), modulus
+
 
 def GetSpiClockParameter(args):
-  assert args.spi_clock in SPI_CLOCK_LIST, \
-         "Unsupported SPI clock speed %d MHz" % args.spi_clock
-  return SPI_CLOCK_LIST.index(args.spi_clock)
+    assert args.spi_clock in SPI_CLOCK_LIST, (
+        "Unsupported SPI clock speed %d MHz" % args.spi_clock
+    )
+    return SPI_CLOCK_LIST.index(args.spi_clock)
+
 
 def GetSpiReadCmdParameter(args):
-  assert args.spi_read_cmd in SPI_READ_CMD_LIST, \
-         "Unsupported SPI read command 0x%x" % args.spi_read_cmd
-  return SPI_READ_CMD_LIST.index(args.spi_read_cmd)
+    assert args.spi_read_cmd in SPI_READ_CMD_LIST, (
+        "Unsupported SPI read command 0x%x" % args.spi_read_cmd
+    )
+    return SPI_READ_CMD_LIST.index(args.spi_read_cmd)
+
 
 def PadZeroTo(data, size):
-  data.extend(b'\0' * (size - len(data)))
+    data.extend(b"\0" * (size - len(data)))
+
 
 def BuildHeader(args, payload_len, load_addr, rorofile):
-  # Identifier and header version
-  header = bytearray(b'PHCM\0')
+    # Identifier and header version
+    header = bytearray(b"PHCM\0")
 
-  # byte[5]
-  b = GetSpiClockParameter(args)
-  b |= (1 << 2)
-  header.append(b)
+    # byte[5]
+    b = GetSpiClockParameter(args)
+    b |= 1 << 2
+    header.append(b)
 
-  # byte[6]
-  b = 0
-  header.append(b)
+    # byte[6]
+    b = 0
+    header.append(b)
 
-  # byte[7]
-  header.append(GetSpiReadCmdParameter(args))
+    # byte[7]
+    header.append(GetSpiReadCmdParameter(args))
 
-  # bytes 0x08 - 0x0b
-  header.extend(struct.pack('<I', load_addr))
-  # bytes 0x0c - 0x0f
-  header.extend(struct.pack('<I', GetEntryPoint(rorofile)))
-  # bytes 0x10 - 0x13
-  header.append((payload_len >> 6) & 0xff)
-  header.append((payload_len >> 14) & 0xff)
-  PadZeroTo(header, 0x14)
-  # bytes 0x14 - 0x17
-  header.extend(struct.pack('<I', args.payload_offset))
+    # bytes 0x08 - 0x0b
+    header.extend(struct.pack("<I", load_addr))
+    # bytes 0x0c - 0x0f
+    header.extend(struct.pack("<I", GetEntryPoint(rorofile)))
+    # bytes 0x10 - 0x13
+    header.append((payload_len >> 6) & 0xFF)
+    header.append((payload_len >> 14) & 0xFF)
+    PadZeroTo(header, 0x14)
+    # bytes 0x14 - 0x17
+    header.extend(struct.pack("<I", args.payload_offset))
 
-  # bytes 0x14 - 0x3F all 0
-  PadZeroTo(header, 0x40)
+    # bytes 0x14 - 0x3F all 0
+    PadZeroTo(header, 0x40)
 
-  # header signature is appended by the caller
+    # header signature is appended by the caller
 
-  return header
+    return header
 
 
 def BuildHeader2(args, payload_len, load_addr, payload_entry):
-  # Identifier and header version
-  header = bytearray(b'PHCM\0')
+    # Identifier and header version
+    header = bytearray(b"PHCM\0")
+
+    # byte[5]
+    b = GetSpiClockParameter(args)
+    b |= 1 << 2
+    header.append(b)
 
-  # byte[5]
-  b = GetSpiClockParameter(args)
-  b |= (1 << 2)
-  header.append(b)
+    # byte[6]
+    b = 0
+    header.append(b)
 
-  # byte[6]
-  b = 0
-  header.append(b)
+    # byte[7]
+    header.append(GetSpiReadCmdParameter(args))
 
-  # byte[7]
-  header.append(GetSpiReadCmdParameter(args))
+    # bytes 0x08 - 0x0b
+    header.extend(struct.pack("<I", load_addr))
+    # bytes 0x0c - 0x0f
+    header.extend(struct.pack("<I", payload_entry))
+    # bytes 0x10 - 0x13
+    header.append((payload_len >> 6) & 0xFF)
+    header.append((payload_len >> 14) & 0xFF)
+    PadZeroTo(header, 0x14)
+    # bytes 0x14 - 0x17
+    header.extend(struct.pack("<I", args.payload_offset))
 
-  # bytes 0x08 - 0x0b
-  header.extend(struct.pack('<I', load_addr))
-  # bytes 0x0c - 0x0f
-  header.extend(struct.pack('<I', payload_entry))
-  # bytes 0x10 - 0x13
-  header.append((payload_len >> 6) & 0xff)
-  header.append((payload_len >> 14) & 0xff)
-  PadZeroTo(header, 0x14)
-  # bytes 0x14 - 0x17
-  header.extend(struct.pack('<I', args.payload_offset))
+    # bytes 0x14 - 0x3F all 0
+    PadZeroTo(header, 0x40)
 
-  # bytes 0x14 - 0x3F all 0
-  PadZeroTo(header, 0x40)
+    # header signature is appended by the caller
 
-  # header signature is appended by the caller
+    return header
 
-  return header
 
 #
 # Compute SHA-256 of data and return digest
 # as a bytearray
 #
 def HashByteArray(data):
-  hasher = hashlib.sha256()
-  hasher.update(data)
-  h = hasher.digest()
-  bah = bytearray(h)
-  return bah
+    hasher = hashlib.sha256()
+    hasher.update(data)
+    h = hasher.digest()
+    bah = bytearray(h)
+    return bah
+
 
 #
 # Return 64-byte signature of byte array data.
 # Signature is SHA256 of data with 32 0 bytes appended
 #
 def SignByteArray(data):
-  debug_print("Signature is SHA-256 of data")
-  sigb = HashByteArray(data)
-  sigb.extend(b'\0' * 32)
-  return sigb
+    debug_print("Signature is SHA-256 of data")
+    sigb = HashByteArray(data)
+    sigb.extend(b"\0" * 32)
+    return sigb
 
 
 # MEC1701H supports two 32-bit Tags located at offsets 0x0 and 0x4
@@ -201,16 +231,25 @@ def SignByteArray(data):
 # to the same flash part.
 #
 def BuildTag(args):
-  tag = bytearray([(args.header_loc >> 8) & 0xff,
-                   (args.header_loc >> 16) & 0xff,
-                   (args.header_loc >> 24) & 0xff])
-  tag.append(Crc8(0, tag))
-  return tag
+    tag = bytearray(
+        [
+            (args.header_loc >> 8) & 0xFF,
+            (args.header_loc >> 16) & 0xFF,
+            (args.header_loc >> 24) & 0xFF,
+        ]
+    )
+    tag.append(Crc8(0, tag))
+    return tag
+
 
 def BuildTagFromHdrAddr(header_loc):
-    tag = bytearray([(header_loc >> 8) & 0xff,
-                     (header_loc >> 16) & 0xff,
-                     (header_loc >> 24) & 0xff])
+    tag = bytearray(
+        [
+            (header_loc >> 8) & 0xFF,
+            (header_loc >> 16) & 0xFF,
+            (header_loc >> 24) & 0xFF,
+        ]
+    )
     tag.append(Crc8(0, tag))
     return tag
 
@@ -224,20 +263,21 @@ def BuildTagFromHdrAddr(header_loc):
 # Returns temporary file name
 #
 def PacklfwRoImage(rorw_file, loader_file, image_size):
-  """Create a temp file with the
-  first image_size bytes from the loader file and append bytes
-  from the rorw file.
-  return the filename"""
-  fo=tempfile.NamedTemporaryFile(delete=False) # Need to keep file around
-  with open(loader_file,'rb') as fin1: # read 4KB loader file
-    pro = fin1.read()
-  fo.write(pro)            # write 4KB loader data to temp file
-  with open(rorw_file, 'rb') as fin:
-    ro = fin.read(image_size)
-
-  fo.write(ro)
-  fo.close()
-  return fo.name
+    """Create a temp file with the
+    first image_size bytes from the loader file and append bytes
+    from the rorw file.
+    return the filename"""
+    fo = tempfile.NamedTemporaryFile(delete=False)  # Need to keep file around
+    with open(loader_file, "rb") as fin1:  # read 4KB loader file
+        pro = fin1.read()
+    fo.write(pro)  # write 4KB loader data to temp file
+    with open(rorw_file, "rb") as fin:
+        ro = fin.read(image_size)
+
+    fo.write(ro)
+    fo.close()
+    return fo.name
+
 
 #
 # Generate a test EC_RW image of same size
@@ -248,105 +288,152 @@ def PacklfwRoImage(rorw_file, loader_file, image_size):
 # process hash generation.
 #
 def gen_test_ecrw(pldrw):
-  debug_print("gen_test_ecrw: pldrw type =", type(pldrw))
-  debug_print("len pldrw =", len(pldrw), " = ", hex(len(pldrw)))
-  cookie1_pos = pldrw.find(b'\x99\x88\x77\xce')
-  cookie2_pos = pldrw.find(b'\xdd\xbb\xaa\xce', cookie1_pos+4)
-  t = struct.unpack("<L", pldrw[cookie1_pos+0x24:cookie1_pos+0x28])
-  size = t[0]
-  debug_print("EC_RW size =", size, " = ", hex(size))
-
-  debug_print("Found cookie1 at ", hex(cookie1_pos))
-  debug_print("Found cookie2 at ", hex(cookie2_pos))
-
-  if cookie1_pos > 0 and cookie2_pos > cookie1_pos:
-    for i in range(0, cookie1_pos):
-      pldrw[i] = 0xA5
-    for i in range(cookie2_pos+4, len(pldrw)):
-      pldrw[i] = 0xA5
-
-  with open("ec_RW_test.bin", "wb") as fecrw:
-      fecrw.write(pldrw[:size])
+    debug_print("gen_test_ecrw: pldrw type =", type(pldrw))
+    debug_print("len pldrw =", len(pldrw), " = ", hex(len(pldrw)))
+    cookie1_pos = pldrw.find(b"\x99\x88\x77\xce")
+    cookie2_pos = pldrw.find(b"\xdd\xbb\xaa\xce", cookie1_pos + 4)
+    t = struct.unpack("<L", pldrw[cookie1_pos + 0x24 : cookie1_pos + 0x28])
+    size = t[0]
+    debug_print("EC_RW size =", size, " = ", hex(size))
+
+    debug_print("Found cookie1 at ", hex(cookie1_pos))
+    debug_print("Found cookie2 at ", hex(cookie2_pos))
+
+    if cookie1_pos > 0 and cookie2_pos > cookie1_pos:
+        for i in range(0, cookie1_pos):
+            pldrw[i] = 0xA5
+        for i in range(cookie2_pos + 4, len(pldrw)):
+            pldrw[i] = 0xA5
+
+    with open("ec_RW_test.bin", "wb") as fecrw:
+        fecrw.write(pldrw[:size])
+
 
 def parseargs():
-  rpath = os.path.dirname(os.path.relpath(__file__))
-
-  parser = argparse.ArgumentParser()
-  parser.add_argument("-i", "--input",
-              help="EC binary to pack, usually ec.bin or ec.RO.flat.",
-              metavar="EC_BIN", default="ec.bin")
-  parser.add_argument("-o", "--output",
-                      help="Output flash binary file",
-                      metavar="EC_SPI_FLASH", default="ec.packed.bin")
-  parser.add_argument("--loader_file",
-                      help="EC loader binary",
-                      default="ecloader.bin")
-  parser.add_argument("-s", "--spi_size", type=int,
-                      help="Size of the SPI flash in KB",
-                      default=512)
-  parser.add_argument("-l", "--header_loc", type=int,
-                      help="Location of header in SPI flash",
-                      default=0x1000)
-  parser.add_argument("-p", "--payload_offset", type=int,
-                      help="The offset of payload from the start of header",
-                      default=0x80)
-  parser.add_argument("-r", "--rw_loc", type=int,
-                      help="Start offset of EC_RW. Default is -1 meaning 1/2 flash size",
-                      default=-1)
-  parser.add_argument("--spi_clock", type=int,
-                      help="SPI clock speed. 8, 12, 24, or 48 MHz.",
-                      default=24)
-  parser.add_argument("--spi_read_cmd", type=int,
-                      help="SPI read command. 0x3, 0xB, or 0x3B.",
-                      default=0xb)
-  parser.add_argument("--image_size", type=int,
-                      help="Size of a single image. Default 220KB",
-                      default=(220 * 1024))
-  parser.add_argument("--test_spi", action='store_true',
-                      help="Test SPI data integrity by adding CRC32 in last 4-bytes of RO/RW binaries",
-                      default=False)
-  parser.add_argument("--test_ecrw", action='store_true',
-                      help="Use fixed pattern for EC_RW but preserve image_data",
-                      default=False)
-  parser.add_argument("--verbose", action='store_true',
-                      help="Enable verbose output",
-                      default=False)
-
-  return parser.parse_args()
+    rpath = os.path.dirname(os.path.relpath(__file__))
+
+    parser = argparse.ArgumentParser()
+    parser.add_argument(
+        "-i",
+        "--input",
+        help="EC binary to pack, usually ec.bin or ec.RO.flat.",
+        metavar="EC_BIN",
+        default="ec.bin",
+    )
+    parser.add_argument(
+        "-o",
+        "--output",
+        help="Output flash binary file",
+        metavar="EC_SPI_FLASH",
+        default="ec.packed.bin",
+    )
+    parser.add_argument(
+        "--loader_file", help="EC loader binary", default="ecloader.bin"
+    )
+    parser.add_argument(
+        "-s",
+        "--spi_size",
+        type=int,
+        help="Size of the SPI flash in KB",
+        default=512,
+    )
+    parser.add_argument(
+        "-l",
+        "--header_loc",
+        type=int,
+        help="Location of header in SPI flash",
+        default=0x1000,
+    )
+    parser.add_argument(
+        "-p",
+        "--payload_offset",
+        type=int,
+        help="The offset of payload from the start of header",
+        default=0x80,
+    )
+    parser.add_argument(
+        "-r",
+        "--rw_loc",
+        type=int,
+        help="Start offset of EC_RW. Default is -1 meaning 1/2 flash size",
+        default=-1,
+    )
+    parser.add_argument(
+        "--spi_clock",
+        type=int,
+        help="SPI clock speed. 8, 12, 24, or 48 MHz.",
+        default=24,
+    )
+    parser.add_argument(
+        "--spi_read_cmd",
+        type=int,
+        help="SPI read command. 0x3, 0xB, or 0x3B.",
+        default=0xB,
+    )
+    parser.add_argument(
+        "--image_size",
+        type=int,
+        help="Size of a single image. Default 220KB",
+        default=(220 * 1024),
+    )
+    parser.add_argument(
+        "--test_spi",
+        action="store_true",
+        help="Test SPI data integrity by adding CRC32 in last 4-bytes of RO/RW binaries",
+        default=False,
+    )
+    parser.add_argument(
+        "--test_ecrw",
+        action="store_true",
+        help="Use fixed pattern for EC_RW but preserve image_data",
+        default=False,
+    )
+    parser.add_argument(
+        "--verbose",
+        action="store_true",
+        help="Enable verbose output",
+        default=False,
+    )
+
+    return parser.parse_args()
+
 
 # Debug helper routine
 def dumpsects(spi_list):
-  debug_print("spi_list has {0} entries".format(len(spi_list)))
-  for s in spi_list:
-    debug_print("0x{0:x} 0x{1:x} {2:s}".format(s[0],len(s[1]),s[2]))
+    debug_print("spi_list has {0} entries".format(len(spi_list)))
+    for s in spi_list:
+        debug_print("0x{0:x} 0x{1:x} {2:s}".format(s[0], len(s[1]), s[2]))
+
 
 def printByteArrayAsHex(ba, title):
-  debug_print(title,"= ")
-  count = 0
-  for b in ba:
-    count = count + 1
-    debug_print("0x{0:02x}, ".format(b),end="")
-    if (count % 8) == 0:
-      debug_print("")
-  debug_print("\n")
+    debug_print(title, "= ")
+    count = 0
+    for b in ba:
+        count = count + 1
+        debug_print("0x{0:02x}, ".format(b), end="")
+        if (count % 8) == 0:
+            debug_print("")
+    debug_print("\n")
+
 
 def print_args(args):
-  debug_print("parsed arguments:")
-  debug_print(".input  = ", args.input)
-  debug_print(".output = ", args.output)
-  debug_print(".loader_file = ", args.loader_file)
-  debug_print(".spi_size (KB) = ", hex(args.spi_size))
-  debug_print(".image_size = ", hex(args.image_size))
-  debug_print(".header_loc = ", hex(args.header_loc))
-  debug_print(".payload_offset = ", hex(args.payload_offset))
-  if args.rw_loc < 0:
-    debug_print(".rw_loc = ", args.rw_loc)
-  else:
-    debug_print(".rw_loc = ", hex(args.rw_loc))
-  debug_print(".spi_clock = ", args.spi_clock)
-  debug_print(".spi_read_cmd = ", args.spi_read_cmd)
-  debug_print(".test_spi = ", args.test_spi)
-  debug_print(".verbose = ", args.verbose)
+    debug_print("parsed arguments:")
+    debug_print(".input  = ", args.input)
+    debug_print(".output = ", args.output)
+    debug_print(".loader_file = ", args.loader_file)
+    debug_print(".spi_size (KB) = ", hex(args.spi_size))
+    debug_print(".image_size = ", hex(args.image_size))
+    debug_print(".header_loc = ", hex(args.header_loc))
+    debug_print(".payload_offset = ", hex(args.payload_offset))
+    if args.rw_loc < 0:
+        debug_print(".rw_loc = ", args.rw_loc)
+    else:
+        debug_print(".rw_loc = ", hex(args.rw_loc))
+    debug_print(".spi_clock = ", args.spi_clock)
+    debug_print(".spi_read_cmd = ", args.spi_read_cmd)
+    debug_print(".test_spi = ", args.test_spi)
+    debug_print(".verbose = ", args.verbose)
+
 
 #
 # Handle quiet mode build from Makefile
@@ -354,183 +441,206 @@ def print_args(args):
 # Verbose mode when V=1
 #
 def main():
-  global debug_print
-
-  args = parseargs()
-
-  if args.verbose:
-    debug_print = print
-
-  debug_print("Begin MEC17xx pack_ec.py script")
-
-
-  # MEC17xx maximum 192KB each for RO & RW
-  # mec1701 chip Makefile sets args.spi_size = 512
-  # Tags at offset 0
-  #
-  print_args(args)
-
-  spi_size = args.spi_size * 1024
-  debug_print("SPI Flash image size in bytes =", hex(spi_size))
-
-  # !!! IMPORTANT !!!
-  # These values MUST match chip/mec1701/config_flash_layout.h
-  # defines.
-  # MEC17xx Boot-ROM TAGs are at offset 0 and 4.
-  # lfw + EC_RO starts at beginning of second 4KB sector
-  # EC_RW starts at offset 0x40000 (256KB)
-
-  spi_list = []
-
-  debug_print("args.input = ",args.input)
-  debug_print("args.loader_file = ",args.loader_file)
-  debug_print("args.image_size = ",hex(args.image_size))
-
-  rorofile=PacklfwRoImage(args.input, args.loader_file, args.image_size)
-
-  payload = GetPayload(rorofile)
-  payload_len = len(payload)
-  # debug
-  debug_print("EC_LFW + EC_RO length = ",hex(payload_len))
-
-  # SPI image integrity test
-  # compute CRC32 of EC_RO except for last 4 bytes
-  # skip over 4KB LFW
-  # Store CRC32 in last 4 bytes
-  if args.test_spi == True:
-    crc = zlib.crc32(bytes(payload[LFW_SIZE:(payload_len - 4)]))
-    crc_ofs = payload_len - 4
-    debug_print("EC_RO CRC32 = 0x{0:08x} @ 0x{1:08x}".format(crc, crc_ofs))
-    for i in range(4):
-      payload[crc_ofs + i] = crc & 0xff
-      crc = crc >> 8
-
-  # Chromebooks are not using MEC BootROM ECDSA.
-  # We implemented the ECDSA disabled case where
-  # the 64-byte signature contains a SHA-256 of the binary plus
-  # 32 zeros bytes.
-  payload_signature = SignByteArray(payload)
-  # debug
-  printByteArrayAsHex(payload_signature, "LFW + EC_RO payload_signature")
-
-  # MEC17xx Header is 0x80 bytes with an 64 byte signature
-  # (32 byte SHA256 + 32 zero bytes)
-  header = BuildHeader(args, payload_len, LOAD_ADDR, rorofile)
-  # debug
-  printByteArrayAsHex(header, "Header LFW + EC_RO")
-
-  # MEC17xx payload ECDSA not used, 64 byte signature is
-  # SHA256 + 32 zero bytes
-  header_signature = SignByteArray(header)
-  # debug
-  printByteArrayAsHex(header_signature, "header_signature")
-
-  tag = BuildTag(args)
-  # MEC17xx truncate RW length to args.image_size to not overwrite LFW
-  # offset may be different due to Header size and other changes
-  # MCHP we want to append a SHA-256 to the end of the actual payload
-  # to test SPI read routines.
-  debug_print("Call to GetPayloadFromOffset")
-  debug_print("args.input = ", args.input)
-  debug_print("args.image_size = ", hex(args.image_size))
-
-  payload_rw = GetPayloadFromOffset(args.input, args.image_size)
-  debug_print("type(payload_rw) is ", type(payload_rw))
-  debug_print("len(payload_rw) is ", hex(len(payload_rw)))
-
-  # truncate to args.image_size
-  rw_len = args.image_size
-  payload_rw = payload_rw[:rw_len]
-  payload_rw_len = len(payload_rw)
-  debug_print("Truncated size of EC_RW = ", hex(payload_rw_len))
-
-  payload_entry_tuple = struct.unpack_from('<I', payload_rw, 4)
-  debug_print("payload_entry_tuple = ", payload_entry_tuple)
-
-  payload_entry = payload_entry_tuple[0]
-  debug_print("payload_entry = ", hex(payload_entry))
-
-  # Note: payload_rw is a bytearray therefore is mutable
-  if args.test_ecrw:
-    gen_test_ecrw(payload_rw)
-
-  # SPI image integrity test
-  # compute CRC32 of EC_RW except for last 4 bytes
-  # Store CRC32 in last 4 bytes
-  if args.test_spi == True:
-    crc = zlib.crc32(bytes(payload_rw[:(payload_rw_len - 32)]))
-    crc_ofs = payload_rw_len - 4
-    debug_print("EC_RW CRC32 = 0x{0:08x} at offset 0x{1:08x}".format(crc, crc_ofs))
-    for i in range(4):
-      payload_rw[crc_ofs + i] = crc & 0xff
-      crc = crc >> 8
-
-  payload_rw_sig = SignByteArray(payload_rw)
-  # debug
-  printByteArrayAsHex(payload_rw_sig, "payload_rw_sig")
-
-  os.remove(rorofile)           # clean up the temp file
-
-  # MEC170x Boot-ROM Tags are located at SPI offset 0
-  spi_list.append((0, tag, "tag"))
-
-  spi_list.append((args.header_loc, header, "header(lwf + ro)"))
-  spi_list.append((args.header_loc + HEADER_SIZE, header_signature,
-    "header(lwf + ro) signature"))
-  spi_list.append((args.header_loc + args.payload_offset, payload,
-    "payload(lfw + ro)"))
-
-  offset = args.header_loc + args.payload_offset + payload_len
-
-  # No SPI Header for EC_RW as its not loaded by BootROM
-  spi_list.append((offset, payload_signature,
-                   "payload(lfw_ro) signature"))
-
-  # EC_RW location
-  rw_offset = int(spi_size // 2)
-  if args.rw_loc >= 0:
-    rw_offset = args.rw_loc
-
-  debug_print("rw_offset = 0x{0:08x}".format(rw_offset))
-
-  if rw_offset < offset + len(payload_signature):
-    print("ERROR: EC_RW overlaps EC_RO")
-
-  spi_list.append((rw_offset, payload_rw, "payload(rw)"))
-
-  # don't add to EC_RW. We don't know if Google will process
-  # EC SPI flash binary with other tools during build of
-  # coreboot and OS.
-  #offset = rw_offset + payload_rw_len
-  #spi_list.append((offset, payload_rw_sig, "payload(rw) signature"))
-
-  spi_list = sorted(spi_list)
-
-  dumpsects(spi_list)
-
-  #
-  # MEC17xx Boot-ROM locates TAG at SPI offset 0 instead of end of SPI.
-  #
-  with open(args.output, 'wb') as f:
-    debug_print("Write spi list to file", args.output)
-    addr = 0
-    for s in spi_list:
-      if addr < s[0]:
-        debug_print("Offset ",hex(addr)," Length", hex(s[0]-addr),
-                "fill with 0xff")
-        f.write(b'\xff' * (s[0] - addr))
-        addr = s[0]
-        debug_print("Offset ",hex(addr), " Length", hex(len(s[1])), "write data")
-
-      f.write(s[1])
-      addr += len(s[1])
-
-    if addr < spi_size:
-      debug_print("Offset ",hex(addr), " Length", hex(spi_size - addr),
-              "fill with 0xff")
-      f.write(b'\xff' * (spi_size - addr))
-
-    f.flush()
-
-if __name__ == '__main__':
-  main()
+    global debug_print
+
+    args = parseargs()
+
+    if args.verbose:
+        debug_print = print
+
+    debug_print("Begin MEC17xx pack_ec.py script")
+
+    # MEC17xx maximum 192KB each for RO & RW
+    # mec1701 chip Makefile sets args.spi_size = 512
+    # Tags at offset 0
+    #
+    print_args(args)
+
+    spi_size = args.spi_size * 1024
+    debug_print("SPI Flash image size in bytes =", hex(spi_size))
+
+    # !!! IMPORTANT !!!
+    # These values MUST match chip/mec1701/config_flash_layout.h
+    # defines.
+    # MEC17xx Boot-ROM TAGs are at offset 0 and 4.
+    # lfw + EC_RO starts at beginning of second 4KB sector
+    # EC_RW starts at offset 0x40000 (256KB)
+
+    spi_list = []
+
+    debug_print("args.input = ", args.input)
+    debug_print("args.loader_file = ", args.loader_file)
+    debug_print("args.image_size = ", hex(args.image_size))
+
+    rorofile = PacklfwRoImage(args.input, args.loader_file, args.image_size)
+
+    payload = GetPayload(rorofile)
+    payload_len = len(payload)
+    # debug
+    debug_print("EC_LFW + EC_RO length = ", hex(payload_len))
+
+    # SPI image integrity test
+    # compute CRC32 of EC_RO except for last 4 bytes
+    # skip over 4KB LFW
+    # Store CRC32 in last 4 bytes
+    if args.test_spi == True:
+        crc = zlib.crc32(bytes(payload[LFW_SIZE : (payload_len - 4)]))
+        crc_ofs = payload_len - 4
+        debug_print("EC_RO CRC32 = 0x{0:08x} @ 0x{1:08x}".format(crc, crc_ofs))
+        for i in range(4):
+            payload[crc_ofs + i] = crc & 0xFF
+            crc = crc >> 8
+
+    # Chromebooks are not using MEC BootROM ECDSA.
+    # We implemented the ECDSA disabled case where
+    # the 64-byte signature contains a SHA-256 of the binary plus
+    # 32 zeros bytes.
+    payload_signature = SignByteArray(payload)
+    # debug
+    printByteArrayAsHex(payload_signature, "LFW + EC_RO payload_signature")
+
+    # MEC17xx Header is 0x80 bytes with an 64 byte signature
+    # (32 byte SHA256 + 32 zero bytes)
+    header = BuildHeader(args, payload_len, LOAD_ADDR, rorofile)
+    # debug
+    printByteArrayAsHex(header, "Header LFW + EC_RO")
+
+    # MEC17xx payload ECDSA not used, 64 byte signature is
+    # SHA256 + 32 zero bytes
+    header_signature = SignByteArray(header)
+    # debug
+    printByteArrayAsHex(header_signature, "header_signature")
+
+    tag = BuildTag(args)
+    # MEC17xx truncate RW length to args.image_size to not overwrite LFW
+    # offset may be different due to Header size and other changes
+    # MCHP we want to append a SHA-256 to the end of the actual payload
+    # to test SPI read routines.
+    debug_print("Call to GetPayloadFromOffset")
+    debug_print("args.input = ", args.input)
+    debug_print("args.image_size = ", hex(args.image_size))
+
+    payload_rw = GetPayloadFromOffset(args.input, args.image_size)
+    debug_print("type(payload_rw) is ", type(payload_rw))
+    debug_print("len(payload_rw) is ", hex(len(payload_rw)))
+
+    # truncate to args.image_size
+    rw_len = args.image_size
+    payload_rw = payload_rw[:rw_len]
+    payload_rw_len = len(payload_rw)
+    debug_print("Truncated size of EC_RW = ", hex(payload_rw_len))
+
+    payload_entry_tuple = struct.unpack_from("<I", payload_rw, 4)
+    debug_print("payload_entry_tuple = ", payload_entry_tuple)
+
+    payload_entry = payload_entry_tuple[0]
+    debug_print("payload_entry = ", hex(payload_entry))
+
+    # Note: payload_rw is a bytearray therefore is mutable
+    if args.test_ecrw:
+        gen_test_ecrw(payload_rw)
+
+    # SPI image integrity test
+    # compute CRC32 of EC_RW except for last 4 bytes
+    # Store CRC32 in last 4 bytes
+    if args.test_spi == True:
+        crc = zlib.crc32(bytes(payload_rw[: (payload_rw_len - 32)]))
+        crc_ofs = payload_rw_len - 4
+        debug_print(
+            "EC_RW CRC32 = 0x{0:08x} at offset 0x{1:08x}".format(crc, crc_ofs)
+        )
+        for i in range(4):
+            payload_rw[crc_ofs + i] = crc & 0xFF
+            crc = crc >> 8
+
+    payload_rw_sig = SignByteArray(payload_rw)
+    # debug
+    printByteArrayAsHex(payload_rw_sig, "payload_rw_sig")
+
+    os.remove(rorofile)  # clean up the temp file
+
+    # MEC170x Boot-ROM Tags are located at SPI offset 0
+    spi_list.append((0, tag, "tag"))
+
+    spi_list.append((args.header_loc, header, "header(lwf + ro)"))
+    spi_list.append(
+        (
+            args.header_loc + HEADER_SIZE,
+            header_signature,
+            "header(lwf + ro) signature",
+        )
+    )
+    spi_list.append(
+        (args.header_loc + args.payload_offset, payload, "payload(lfw + ro)")
+    )
+
+    offset = args.header_loc + args.payload_offset + payload_len
+
+    # No SPI Header for EC_RW as its not loaded by BootROM
+    spi_list.append((offset, payload_signature, "payload(lfw_ro) signature"))
+
+    # EC_RW location
+    rw_offset = int(spi_size // 2)
+    if args.rw_loc >= 0:
+        rw_offset = args.rw_loc
+
+    debug_print("rw_offset = 0x{0:08x}".format(rw_offset))
+
+    if rw_offset < offset + len(payload_signature):
+        print("ERROR: EC_RW overlaps EC_RO")
+
+    spi_list.append((rw_offset, payload_rw, "payload(rw)"))
+
+    # don't add to EC_RW. We don't know if Google will process
+    # EC SPI flash binary with other tools during build of
+    # coreboot and OS.
+    # offset = rw_offset + payload_rw_len
+    # spi_list.append((offset, payload_rw_sig, "payload(rw) signature"))
+
+    spi_list = sorted(spi_list)
+
+    dumpsects(spi_list)
+
+    #
+    # MEC17xx Boot-ROM locates TAG at SPI offset 0 instead of end of SPI.
+    #
+    with open(args.output, "wb") as f:
+        debug_print("Write spi list to file", args.output)
+        addr = 0
+        for s in spi_list:
+            if addr < s[0]:
+                debug_print(
+                    "Offset ",
+                    hex(addr),
+                    " Length",
+                    hex(s[0] - addr),
+                    "fill with 0xff",
+                )
+                f.write(b"\xff" * (s[0] - addr))
+                addr = s[0]
+                debug_print(
+                    "Offset ",
+                    hex(addr),
+                    " Length",
+                    hex(len(s[1])),
+                    "write data",
+                )
+
+            f.write(s[1])
+            addr += len(s[1])
+
+        if addr < spi_size:
+            debug_print(
+                "Offset ",
+                hex(addr),
+                " Length",
+                hex(spi_size - addr),
+                "fill with 0xff",
+            )
+            f.write(b"\xff" * (spi_size - addr))
+
+        f.flush()
+
+
+if __name__ == "__main__":
+    main()
diff --git a/chip/mchp/util/pack_ec_mec152x.py b/chip/mchp/util/pack_ec_mec152x.py
index 34846cd6ba..a463a43b6c 100755
--- a/chip/mchp/util/pack_ec_mec152x.py
+++ b/chip/mchp/util/pack_ec_mec152x.py
@@ -1,12 +1,8 @@
 #!/usr/bin/env python3
 
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
 
 # A script to pack EC binary into SPI flash image for MEC152x
 # Based on MEC1521/MEC1523_ROM_Description.pdf
@@ -16,7 +12,7 @@ import os
 import struct
 import subprocess
 import tempfile
-import zlib # CRC32
+import zlib  # CRC32
 
 # MEC152xH has 256KB SRAM from 0xE0000 - 0x120000
 # SRAM is divided into contiguous CODE & DATA
@@ -29,119 +25,159 @@ LOAD_ADDR = 0x0E0000
 LOAD_ADDR_RW = 0xE1000
 MEC152X_HEADER_SIZE = 0x140
 MEC152X_HEADER_VERSION = 0x02
-PAYLOAD_PAD_BYTE = b'\xff'
+PAYLOAD_PAD_BYTE = b"\xff"
 SPI_ERASE_BLOCK_SIZE = 0x1000
 SPI_CLOCK_LIST = [48, 24, 16, 12]
-SPI_READ_CMD_LIST = [0x3, 0xb, 0x3b, 0x6b]
-SPI_DRIVE_STR_DICT = {2:0, 4:1, 8:2, 12:3}
+SPI_READ_CMD_LIST = [0x3, 0xB, 0x3B, 0x6B]
+SPI_DRIVE_STR_DICT = {2: 0, 4: 1, 8: 2, 12: 3}
 CHIP_MAX_CODE_SRAM_KB = 224
 
 MEC152X_DICT = {
-                "HEADER_SIZE":0x140,
-                "HEADER_VER":0x02,
-                "PAYLOAD_OFFSET":0x140,
-                "PAYLOAD_GRANULARITY":128,
-                "EC_INFO_BLK_SZ":128,
-                "ENCR_KEY_HDR_SZ":128,
-                "COSIG_SZ":96,
-                "TRAILER_SZ":160,
-                "TAILER_PAD_BYTE":b'\xff',
-                "PAD_SIZE":128
-                }
-
-CRC_TABLE = [0x00, 0x07, 0x0e, 0x09, 0x1c, 0x1b, 0x12, 0x15,
-             0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d]
+    "HEADER_SIZE": 0x140,
+    "HEADER_VER": 0x02,
+    "PAYLOAD_OFFSET": 0x140,
+    "PAYLOAD_GRANULARITY": 128,
+    "EC_INFO_BLK_SZ": 128,
+    "ENCR_KEY_HDR_SZ": 128,
+    "COSIG_SZ": 96,
+    "TRAILER_SZ": 160,
+    "TAILER_PAD_BYTE": b"\xff",
+    "PAD_SIZE": 128,
+}
+
+CRC_TABLE = [
+    0x00,
+    0x07,
+    0x0E,
+    0x09,
+    0x1C,
+    0x1B,
+    0x12,
+    0x15,
+    0x38,
+    0x3F,
+    0x36,
+    0x31,
+    0x24,
+    0x23,
+    0x2A,
+    0x2D,
+]
+
 
 def mock_print(*args, **kwargs):
-  pass
+    pass
+
 
 debug_print = mock_print
 
 # Debug helper routine
 def dumpsects(spi_list):
-  debug_print("spi_list has {0} entries".format(len(spi_list)))
-  for s in spi_list:
-    debug_print("0x{0:x} 0x{1:x} {2:s}".format(s[0],len(s[1]),s[2]))
+    debug_print("spi_list has {0} entries".format(len(spi_list)))
+    for s in spi_list:
+        debug_print("0x{0:x} 0x{1:x} {2:s}".format(s[0], len(s[1]), s[2]))
+
 
 def printByteArrayAsHex(ba, title):
-  debug_print(title,"= ")
-  if ba == None:
-      debug_print("None")
-      return
-
-  count = 0
-  for b in ba:
-    count = count + 1
-    debug_print("0x{0:02x}, ".format(b),end="")
-    if (count % 8) == 0:
-      debug_print("")
-  debug_print("")
+    debug_print(title, "= ")
+    if ba == None:
+        debug_print("None")
+        return
+
+    count = 0
+    for b in ba:
+        count = count + 1
+        debug_print("0x{0:02x}, ".format(b), end="")
+        if (count % 8) == 0:
+            debug_print("")
+    debug_print("")
+
 
 def Crc8(crc, data):
-  """Update CRC8 value."""
-  for v in data:
-    crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v >> 4)]);
-    crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v & 0xf)]);
-  return crc ^ 0x55
+    """Update CRC8 value."""
+    for v in data:
+        crc = ((crc << 4) & 0xFF) ^ (CRC_TABLE[(crc >> 4) ^ (v >> 4)])
+        crc = ((crc << 4) & 0xFF) ^ (CRC_TABLE[(crc >> 4) ^ (v & 0xF)])
+    return crc ^ 0x55
+
 
 def GetEntryPoint(payload_file):
-  """Read entry point from payload EC image."""
-  with open(payload_file, 'rb') as f:
-    f.seek(4)
-    s = f.read(4)
-  return int.from_bytes(s, byteorder='little')
+    """Read entry point from payload EC image."""
+    with open(payload_file, "rb") as f:
+        f.seek(4)
+        s = f.read(4)
+    return int.from_bytes(s, byteorder="little")
 
-def GetPayloadFromOffset(payload_file, offset, padsize):
-  """Read payload and pad it to padsize."""
-  with open(payload_file, 'rb') as f:
-    f.seek(offset)
-    payload = bytearray(f.read())
-  rem_len = len(payload) % padsize
-  debug_print("GetPayload: padsize={0:0x} len(payload)={1:0x} rem={2:0x}".format(padsize,len(payload),rem_len))
 
-  if rem_len:
-    payload += PAYLOAD_PAD_BYTE * (padsize - rem_len)
-    debug_print("GetPayload: Added {0} padding bytes".format(padsize - rem_len))
+def GetPayloadFromOffset(payload_file, offset, padsize):
+    """Read payload and pad it to padsize."""
+    with open(payload_file, "rb") as f:
+        f.seek(offset)
+        payload = bytearray(f.read())
+    rem_len = len(payload) % padsize
+    debug_print(
+        "GetPayload: padsize={0:0x} len(payload)={1:0x} rem={2:0x}".format(
+            padsize, len(payload), rem_len
+        )
+    )
+
+    if rem_len:
+        payload += PAYLOAD_PAD_BYTE * (padsize - rem_len)
+        debug_print(
+            "GetPayload: Added {0} padding bytes".format(padsize - rem_len)
+        )
+
+    return payload
 
-  return payload
 
 def GetPayload(payload_file, padsize):
-  """Read payload and pad it to padsize"""
-  return GetPayloadFromOffset(payload_file, 0, padsize)
+    """Read payload and pad it to padsize"""
+    return GetPayloadFromOffset(payload_file, 0, padsize)
+
 
 def GetPublicKey(pem_file):
-  """Extract public exponent and modulus from PEM file."""
-  result = subprocess.run(['openssl', 'rsa', '-in', pem_file, '-text',
-                           '-noout'], stdout=subprocess.PIPE, encoding='utf-8')
-  modulus_raw = []
-  in_modulus = False
-  for line in result.stdout.splitlines():
-    if line.startswith('modulus'):
-      in_modulus = True
-    elif not line.startswith(' '):
-      in_modulus = False
-    elif in_modulus:
-      modulus_raw.extend(line.strip().strip(':').split(':'))
-    if line.startswith('publicExponent'):
-      exp = int(line.split(' ')[1], 10)
-  modulus_raw.reverse()
-  modulus = bytearray((int(x, 16) for x in modulus_raw[:256]))
-  return struct.pack('<Q', exp), modulus
+    """Extract public exponent and modulus from PEM file."""
+    result = subprocess.run(
+        ["openssl", "rsa", "-in", pem_file, "-text", "-noout"],
+        stdout=subprocess.PIPE,
+        encoding="utf-8",
+    )
+    modulus_raw = []
+    in_modulus = False
+    for line in result.stdout.splitlines():
+        if line.startswith("modulus"):
+            in_modulus = True
+        elif not line.startswith(" "):
+            in_modulus = False
+        elif in_modulus:
+            modulus_raw.extend(line.strip().strip(":").split(":"))
+        if line.startswith("publicExponent"):
+            exp = int(line.split(" ")[1], 10)
+    modulus_raw.reverse()
+    modulus = bytearray((int(x, 16) for x in modulus_raw[:256]))
+    return struct.pack("<Q", exp), modulus
+
 
 def GetSpiClockParameter(args):
-  assert args.spi_clock in SPI_CLOCK_LIST, \
-         "Unsupported SPI clock speed %d MHz" % args.spi_clock
-  return SPI_CLOCK_LIST.index(args.spi_clock)
+    assert args.spi_clock in SPI_CLOCK_LIST, (
+        "Unsupported SPI clock speed %d MHz" % args.spi_clock
+    )
+    return SPI_CLOCK_LIST.index(args.spi_clock)
+
 
 def GetSpiReadCmdParameter(args):
-  assert args.spi_read_cmd in SPI_READ_CMD_LIST, \
-         "Unsupported SPI read command 0x%x" % args.spi_read_cmd
-  return SPI_READ_CMD_LIST.index(args.spi_read_cmd)
+    assert args.spi_read_cmd in SPI_READ_CMD_LIST, (
+        "Unsupported SPI read command 0x%x" % args.spi_read_cmd
+    )
+    return SPI_READ_CMD_LIST.index(args.spi_read_cmd)
+
 
 def GetEncodedSpiDriveStrength(args):
-  assert args.spi_drive_str in SPI_DRIVE_STR_DICT, \
-         "Unsupported SPI drive strength %d mA" % args.spi_drive_str
-  return SPI_DRIVE_STR_DICT.get(args.spi_drive_str)
+    assert args.spi_drive_str in SPI_DRIVE_STR_DICT, (
+        "Unsupported SPI drive strength %d mA" % args.spi_drive_str
+    )
+    return SPI_DRIVE_STR_DICT.get(args.spi_drive_str)
+
 
 # Return 0=Slow slew rate or 1=Fast slew rate
 def GetSpiSlewRate(args):
@@ -149,12 +185,14 @@ def GetSpiSlewRate(args):
         return 1
     return 0
 
+
 # Return SPI CPOL = 0 or 1
 def GetSpiCpol(args):
     if args.spi_cpol == 0:
         return 0
     return 1
 
+
 # Return SPI CPHA_MOSI
 # 0 = SPI Master drives data is stable on inactive to clock edge
 # 1 = SPI Master drives data is stable on active to inactive clock edge
@@ -163,6 +201,7 @@ def GetSpiCphaMosi(args):
         return 0
     return 1
 
+
 # Return SPI CPHA_MISO 0 or 1
 # 0 = SPI Master samples data on inactive to active clock edge
 # 1 = SPI Master samples data on active to inactive clock edge
@@ -171,14 +210,10 @@ def GetSpiCphaMiso(args):
         return 0
     return 1
 
+
 def PadZeroTo(data, size):
-  data.extend(b'\0' * (size - len(data)))
+    data.extend(b"\0" * (size - len(data)))
 
-#
-# Boot-ROM SPI image encryption not used with Chromebooks
-#
-def EncryptPayload(args, chip_dict, payload):
-    return None
 
 #
 # Build SPI image header for MEC152x
@@ -237,67 +272,71 @@ def EncryptPayload(args, chip_dict, payload):
 # header[0x110:0x140] = Header ECDSA-384 signature y-coor. = 0 Auth. disabled
 #
 def BuildHeader2(args, chip_dict, payload_len, load_addr, payload_entry):
-  header_size = MEC152X_HEADER_SIZE
-
-  # allocate zero filled header
-  header = bytearray(b'\x00' * header_size)
-  debug_print("len(header) = ", len(header))
-
-  # Identifier and header version
-  header[0:4] = b'PHCM'
-  header[4] = MEC152X_HEADER_VERSION
-
-  # SPI frequency, drive strength, CPOL/CPHA encoding same for both chips
-  spiFreqMHz = GetSpiClockParameter(args)
-  header[5] = (int(spiFreqMHz // 48) - 1) & 0x03
-  header[5] |= ((GetEncodedSpiDriveStrength(args) & 0x03) << 2)
-  header[5] |= ((GetSpiSlewRate(args) & 0x01) << 4)
-  header[5] |= ((GetSpiCpol(args) & 0x01) << 5)
-  header[5] |= ((GetSpiCphaMosi(args) & 0x01) << 6)
-  header[5] |= ((GetSpiCphaMiso(args) & 0x01) << 7)
-
-  # b[0]=0 VTR1 must be 3.3V
-  # b[1]=0(VTR2 3.3V), 1(VTR2 1.8V)
-  # b[2]=0(VTR3 3.3V), 1(VTR3 1.8V)
-  # b[5:3]=111b
-  # b[6]=0 No ECDSA
-  # b[7]=0 No encrypted FW image
-  header[6] = 0x7 << 3
-  if args.vtr2_V18 == True:
-      header[6] |= 0x02
-  if args.vtr3_V18 == True:
-      header[6] |= 0x04
-
-  # SPI read command set same for both chips
-  header[7] = GetSpiReadCmdParameter(args) & 0xFF
-
-  # bytes 0x08 - 0x0b
-  header[0x08:0x0C] = load_addr.to_bytes(4, byteorder='little')
-  # bytes 0x0c - 0x0f
-  header[0x0C:0x10] = payload_entry.to_bytes(4, byteorder='little')
-  # bytes 0x10 - 0x11 payload length in units of 128 bytes
-
-  payload_units = int(payload_len // chip_dict["PAYLOAD_GRANULARITY"])
-  assert payload_units < 0x10000, \
-      print("Payload too large: len={0} units={1}".format(payload_len, payload_units))
-
-  header[0x10:0x12] = payload_units.to_bytes(2, 'little')
-
-  # bytes 0x14 - 0x17
-  header[0x14:0x18] = chip_dict["PAYLOAD_OFFSET"].to_bytes(4, 'little')
-
-  # MEC152x: Disable ECDSA and encryption
-  header[0x18] = 0
-
-  # header[0xB0:0xE0] = SHA384(header[0:0xB0])
-  header[0xB0:0xE0] = hashlib.sha384(header[0:0xB0]).digest()
-  # When ECDSA authentication is disabled MCHP SPI image generator
-  # is filling the last 48 bytes of the Header with 0xff
-  header[-48:] = b'\xff' * 48
-
-  debug_print("After hash: len(header) = ", len(header))
-
-  return header
+    header_size = MEC152X_HEADER_SIZE
+
+    # allocate zero filled header
+    header = bytearray(b"\x00" * header_size)
+    debug_print("len(header) = ", len(header))
+
+    # Identifier and header version
+    header[0:4] = b"PHCM"
+    header[4] = MEC152X_HEADER_VERSION
+
+    # SPI frequency, drive strength, CPOL/CPHA encoding same for both chips
+    spiFreqMHz = GetSpiClockParameter(args)
+    header[5] = (int(spiFreqMHz // 48) - 1) & 0x03
+    header[5] |= (GetEncodedSpiDriveStrength(args) & 0x03) << 2
+    header[5] |= (GetSpiSlewRate(args) & 0x01) << 4
+    header[5] |= (GetSpiCpol(args) & 0x01) << 5
+    header[5] |= (GetSpiCphaMosi(args) & 0x01) << 6
+    header[5] |= (GetSpiCphaMiso(args) & 0x01) << 7
+
+    # b[0]=0 VTR1 must be 3.3V
+    # b[1]=0(VTR2 3.3V), 1(VTR2 1.8V)
+    # b[2]=0(VTR3 3.3V), 1(VTR3 1.8V)
+    # b[5:3]=111b
+    # b[6]=0 No ECDSA
+    # b[7]=0 No encrypted FW image
+    header[6] = 0x7 << 3
+    if args.vtr2_V18 == True:
+        header[6] |= 0x02
+    if args.vtr3_V18 == True:
+        header[6] |= 0x04
+
+    # SPI read command set same for both chips
+    header[7] = GetSpiReadCmdParameter(args) & 0xFF
+
+    # bytes 0x08 - 0x0b
+    header[0x08:0x0C] = load_addr.to_bytes(4, byteorder="little")
+    # bytes 0x0c - 0x0f
+    header[0x0C:0x10] = payload_entry.to_bytes(4, byteorder="little")
+    # bytes 0x10 - 0x11 payload length in units of 128 bytes
+
+    payload_units = int(payload_len // chip_dict["PAYLOAD_GRANULARITY"])
+    assert payload_units < 0x10000, print(
+        "Payload too large: len={0} units={1}".format(
+            payload_len, payload_units
+        )
+    )
+
+    header[0x10:0x12] = payload_units.to_bytes(2, "little")
+
+    # bytes 0x14 - 0x17
+    header[0x14:0x18] = chip_dict["PAYLOAD_OFFSET"].to_bytes(4, "little")
+
+    # MEC152x: Disable ECDSA and encryption
+    header[0x18] = 0
+
+    # header[0xB0:0xE0] = SHA384(header[0:0xB0])
+    header[0xB0:0xE0] = hashlib.sha384(header[0:0xB0]).digest()
+    # When ECDSA authentication is disabled MCHP SPI image generator
+    # is filling the last 48 bytes of the Header with 0xff
+    header[-48:] = b"\xff" * 48
+
+    debug_print("After hash: len(header) = ", len(header))
+
+    return header
+
 
 #
 # MEC152x 128-byte EC Info Block appended to
@@ -311,8 +350,9 @@ def BuildHeader2(args, chip_dict, payload_len, load_addr, payload_entry):
 # byte 127 = customer current image revision
 #
 def GenEcInfoBlock(args, chip_dict):
-  ecinfo = bytearray(chip_dict["EC_INFO_BLK_SZ"])
-  return ecinfo
+    ecinfo = bytearray(chip_dict["EC_INFO_BLK_SZ"])
+    return ecinfo
+
 
 #
 # Generate SPI FW image co-signature.
@@ -325,7 +365,8 @@ def GenEcInfoBlock(args, chip_dict):
 # signature.
 #
 def GenCoSignature(args, chip_dict, payload):
-    return bytearray(b'\xff' * chip_dict["COSIG_SZ"])
+    return bytearray(b"\xff" * chip_dict["COSIG_SZ"])
+
 
 #
 # Generate SPI FW Image trailer.
@@ -336,22 +377,24 @@ def GenCoSignature(args, chip_dict, payload):
 #   trailer[144:160] = 0xFF. Boot-ROM spec. says these bytes should be random.
 #       Authentication & encryption are not used therefore random data
 #       is not necessary.
-def GenTrailer(args, chip_dict, payload, encryption_key_header,
-               ec_info_block, cosignature):
+def GenTrailer(
+    args, chip_dict, payload, encryption_key_header, ec_info_block, cosignature
+):
     trailer = bytearray(chip_dict["TAILER_PAD_BYTE"] * chip_dict["TRAILER_SZ"])
     hasher = hashlib.sha384()
     hasher.update(payload)
     if ec_info_block != None:
-      hasher.update(ec_info_block)
+        hasher.update(ec_info_block)
     if encryption_key_header != None:
-      hasher.update(encryption_key_header)
+        hasher.update(encryption_key_header)
     if cosignature != None:
-      hasher.update(cosignature)
+        hasher.update(cosignature)
     trailer[0:48] = hasher.digest()
-    trailer[-16:] = 16 * b'\xff'
+    trailer[-16:] = 16 * b"\xff"
 
     return trailer
 
+
 # MEC152xH supports two 32-bit Tags located at offsets 0x0 and 0x4
 # in the SPI flash.
 # Tag format:
@@ -362,16 +405,25 @@ def GenTrailer(args, chip_dict, payload, encryption_key_header,
 # to the same flash part.
 #
 def BuildTag(args):
-  tag = bytearray([(args.header_loc >> 8) & 0xff,
-                   (args.header_loc >> 16) & 0xff,
-                   (args.header_loc >> 24) & 0xff])
-  tag.append(Crc8(0, tag))
-  return tag
+    tag = bytearray(
+        [
+            (args.header_loc >> 8) & 0xFF,
+            (args.header_loc >> 16) & 0xFF,
+            (args.header_loc >> 24) & 0xFF,
+        ]
+    )
+    tag.append(Crc8(0, tag))
+    return tag
+
 
 def BuildTagFromHdrAddr(header_loc):
-    tag = bytearray([(header_loc >> 8) & 0xff,
-                     (header_loc >> 16) & 0xff,
-                     (header_loc >> 24) & 0xff])
+    tag = bytearray(
+        [
+            (header_loc >> 8) & 0xFF,
+            (header_loc >> 16) & 0xFF,
+            (header_loc >> 24) & 0xFF,
+        ]
+    )
     tag.append(Crc8(0, tag))
     return tag
 
@@ -388,12 +440,13 @@ def BuildTagFromHdrAddr(header_loc):
 # Output:
 #   bytearray of length 4
 def BuildFlashMap(secondSpiFlashBaseAddr):
-  flashmap = bytearray(4)
-  flashmap[0] = (secondSpiFlashBaseAddr >> 12) & 0xff
-  flashmap[1] = (secondSpiFlashBaseAddr >> 20) & 0xff
-  flashmap[2] = (secondSpiFlashBaseAddr >> 28) & 0xff
-  flashmap[3] = Crc8(0, flashmap)
-  return flashmap
+    flashmap = bytearray(4)
+    flashmap[0] = (secondSpiFlashBaseAddr >> 12) & 0xFF
+    flashmap[1] = (secondSpiFlashBaseAddr >> 20) & 0xFF
+    flashmap[2] = (secondSpiFlashBaseAddr >> 28) & 0xFF
+    flashmap[3] = Crc8(0, flashmap)
+    return flashmap
+
 
 #
 # Creates temporary file for read/write
@@ -404,21 +457,22 @@ def BuildFlashMap(secondSpiFlashBaseAddr):
 # Returns temporary file name
 #
 def PacklfwRoImage(rorw_file, loader_file, image_size):
-  """Create a temp file with the
-  first image_size bytes from the loader file and append bytes
-  from the rorw file.
-  return the filename"""
-  fo=tempfile.NamedTemporaryFile(delete=False) # Need to keep file around
-  with open(loader_file,'rb') as fin1: # read 4KB loader file
-    pro = fin1.read()
-  fo.write(pro)            # write 4KB loader data to temp file
-  with open(rorw_file, 'rb') as fin:
-    ro = fin.read(image_size)
-
-  fo.write(ro)
-  fo.close()
-
-  return fo.name
+    """Create a temp file with the
+    first image_size bytes from the loader file and append bytes
+    from the rorw file.
+    return the filename"""
+    fo = tempfile.NamedTemporaryFile(delete=False)  # Need to keep file around
+    with open(loader_file, "rb") as fin1:  # read 4KB loader file
+        pro = fin1.read()
+    fo.write(pro)  # write 4KB loader data to temp file
+    with open(rorw_file, "rb") as fin:
+        ro = fin.read(image_size)
+
+    fo.write(ro)
+    fo.close()
+
+    return fo.name
+
 
 #
 # Generate a test EC_RW image of same size
@@ -429,129 +483,188 @@ def PacklfwRoImage(rorw_file, loader_file, image_size):
 # process hash generation.
 #
 def gen_test_ecrw(pldrw):
-  debug_print("gen_test_ecrw: pldrw type =", type(pldrw))
-  debug_print("len pldrw =", len(pldrw), " = ", hex(len(pldrw)))
-  cookie1_pos = pldrw.find(b'\x99\x88\x77\xce')
-  cookie2_pos = pldrw.find(b'\xdd\xbb\xaa\xce', cookie1_pos+4)
-  t = struct.unpack("<L", pldrw[cookie1_pos+0x24:cookie1_pos+0x28])
-  size = t[0]
-  debug_print("EC_RW size =", size, " = ", hex(size))
-
-  debug_print("Found cookie1 at ", hex(cookie1_pos))
-  debug_print("Found cookie2 at ", hex(cookie2_pos))
-
-  if cookie1_pos > 0 and cookie2_pos > cookie1_pos:
-    for i in range(0, cookie1_pos):
-      pldrw[i] = 0xA5
-    for i in range(cookie2_pos+4, len(pldrw)):
-      pldrw[i] = 0xA5
-
-  with open("ec_RW_test.bin", "wb") as fecrw:
-      fecrw.write(pldrw[:size])
+    debug_print("gen_test_ecrw: pldrw type =", type(pldrw))
+    debug_print("len pldrw =", len(pldrw), " = ", hex(len(pldrw)))
+    cookie1_pos = pldrw.find(b"\x99\x88\x77\xce")
+    cookie2_pos = pldrw.find(b"\xdd\xbb\xaa\xce", cookie1_pos + 4)
+    t = struct.unpack("<L", pldrw[cookie1_pos + 0x24 : cookie1_pos + 0x28])
+    size = t[0]
+    debug_print("EC_RW size =", size, " = ", hex(size))
+
+    debug_print("Found cookie1 at ", hex(cookie1_pos))
+    debug_print("Found cookie2 at ", hex(cookie2_pos))
+
+    if cookie1_pos > 0 and cookie2_pos > cookie1_pos:
+        for i in range(0, cookie1_pos):
+            pldrw[i] = 0xA5
+        for i in range(cookie2_pos + 4, len(pldrw)):
+            pldrw[i] = 0xA5
+
+    with open("ec_RW_test.bin", "wb") as fecrw:
+        fecrw.write(pldrw[:size])
+
 
 def parseargs():
-  #TODO I commented this out. Why?
-  rpath = os.path.dirname(os.path.relpath(__file__))
-
-  parser = argparse.ArgumentParser()
-  parser.add_argument("-i", "--input",
-              help="EC binary to pack, usually ec.bin or ec.RO.flat.",
-              metavar="EC_BIN", default="ec.bin")
-  parser.add_argument("-o", "--output",
-                      help="Output flash binary file",
-                      metavar="EC_SPI_FLASH", default="ec.packed.bin")
-  parser.add_argument("--loader_file",
-                      help="EC loader binary",
-                      default="ecloader.bin")
-  parser.add_argument("-s", "--spi_size", type=int,
-                      help="Size of the SPI flash in KB",
-                      default=512)
-  parser.add_argument("-l", "--header_loc", type=int,
-                      help="Location of header in SPI flash",
-                      default=0x1000)
-  parser.add_argument("-r", "--rw_loc", type=int,
-                      help="Start offset of EC_RW. Default is -1 meaning 1/2 flash size",
-                      default=-1)
-  parser.add_argument("--spi_clock", type=int,
-                      help="SPI clock speed. 8, 12, 24, or 48 MHz.",
-                      default=24)
-  parser.add_argument("--spi_read_cmd", type=int,
-                      help="SPI read command. 0x3, 0xB, or 0x3B.",
-                      default=0xb)
-  parser.add_argument("--image_size", type=int,
-                      help="Size of a single image. Default 220KB",
-                      default=(220 * 1024))
-  parser.add_argument("--test_spi", action='store_true',
-                      help="Test SPI data integrity by adding CRC32 in last 4-bytes of RO/RW binaries",
-                      default=False)
-  parser.add_argument("--test_ecrw", action='store_true',
-                      help="Use fixed pattern for EC_RW but preserve image_data",
-                      default=False)
-  parser.add_argument("--verbose", action='store_true',
-                      help="Enable verbose output",
-                      default=False)
-  parser.add_argument("--tag0_loc", type=int,
-                      help="MEC152X TAG0 SPI offset",
-                      default=0)
-  parser.add_argument("--tag1_loc", type=int,
-                      help="MEC152X TAG1 SPI offset",
-                      default=4)
-  parser.add_argument("--spi_drive_str", type=int,
-                      help="Chip SPI drive strength in mA: 2, 4, 8, or 12",
-                      default=4)
-  parser.add_argument("--spi_slew_fast", action='store_true',
-                      help="SPI use fast slew rate. Default is False",
-                      default=False)
-  parser.add_argument("--spi_cpol", type=int,
-                      help="SPI clock polarity when idle. Defealt is 0(low)",
-                      default=0)
-  parser.add_argument("--spi_cpha_mosi", type=int,
-                      help="""SPI clock phase master drives data.
+    parser = argparse.ArgumentParser()
+    parser.add_argument(
+        "-i",
+        "--input",
+        help="EC binary to pack, usually ec.bin or ec.RO.flat.",
+        metavar="EC_BIN",
+        default="ec.bin",
+    )
+    parser.add_argument(
+        "-o",
+        "--output",
+        help="Output flash binary file",
+        metavar="EC_SPI_FLASH",
+        default="ec.packed.bin",
+    )
+    parser.add_argument(
+        "--loader_file", help="EC loader binary", default="ecloader.bin"
+    )
+    parser.add_argument(
+        "-s",
+        "--spi_size",
+        type=int,
+        help="Size of the SPI flash in KB",
+        default=512,
+    )
+    parser.add_argument(
+        "-l",
+        "--header_loc",
+        type=int,
+        help="Location of header in SPI flash",
+        default=0x1000,
+    )
+    parser.add_argument(
+        "-r",
+        "--rw_loc",
+        type=int,
+        help="Start offset of EC_RW. Default is -1 meaning 1/2 flash size",
+        default=-1,
+    )
+    parser.add_argument(
+        "--spi_clock",
+        type=int,
+        help="SPI clock speed. 8, 12, 24, or 48 MHz.",
+        default=24,
+    )
+    parser.add_argument(
+        "--spi_read_cmd",
+        type=int,
+        help="SPI read command. 0x3, 0xB, or 0x3B.",
+        default=0xB,
+    )
+    parser.add_argument(
+        "--image_size",
+        type=int,
+        help="Size of a single image. Default 220KB",
+        default=(220 * 1024),
+    )
+    parser.add_argument(
+        "--test_spi",
+        action="store_true",
+        help="Test SPI data integrity by adding CRC32 in last 4-bytes of RO/RW binaries",
+        default=False,
+    )
+    parser.add_argument(
+        "--test_ecrw",
+        action="store_true",
+        help="Use fixed pattern for EC_RW but preserve image_data",
+        default=False,
+    )
+    parser.add_argument(
+        "--verbose",
+        action="store_true",
+        help="Enable verbose output",
+        default=False,
+    )
+    parser.add_argument(
+        "--tag0_loc", type=int, help="MEC152X TAG0 SPI offset", default=0
+    )
+    parser.add_argument(
+        "--tag1_loc", type=int, help="MEC152X TAG1 SPI offset", default=4
+    )
+    parser.add_argument(
+        "--spi_drive_str",
+        type=int,
+        help="Chip SPI drive strength in mA: 2, 4, 8, or 12",
+        default=4,
+    )
+    parser.add_argument(
+        "--spi_slew_fast",
+        action="store_true",
+        help="SPI use fast slew rate. Default is False",
+        default=False,
+    )
+    parser.add_argument(
+        "--spi_cpol",
+        type=int,
+        help="SPI clock polarity when idle. Defealt is 0(low)",
+        default=0,
+    )
+    parser.add_argument(
+        "--spi_cpha_mosi",
+        type=int,
+        help="""SPI clock phase master drives data.
                               0=Data driven on active to inactive clock edge,
                               1=Data driven on inactive to active clock edge""",
-                      default=0)
-  parser.add_argument("--spi_cpha_miso", type=int,
-                      help="""SPI clock phase master samples data.
+        default=0,
+    )
+    parser.add_argument(
+        "--spi_cpha_miso",
+        type=int,
+        help="""SPI clock phase master samples data.
                               0=Data sampled on inactive to active clock edge,
                               1=Data sampled on active to inactive clock edge""",
-                      default=0)
+        default=0,
+    )
 
-  parser.add_argument("--vtr2_V18", action='store_true',
-                      help="Chip VTR2 rail is 1.8V. Default is False(3.3V)",
-                      default=False)
+    parser.add_argument(
+        "--vtr2_V18",
+        action="store_true",
+        help="Chip VTR2 rail is 1.8V. Default is False(3.3V)",
+        default=False,
+    )
 
-  parser.add_argument("--vtr3_V18", action='store_true',
-                      help="Chip VTR3 rail is 1.8V. Default is False(3.3V)",
-                      default=False)
+    parser.add_argument(
+        "--vtr3_V18",
+        action="store_true",
+        help="Chip VTR3 rail is 1.8V. Default is False(3.3V)",
+        default=False,
+    )
+
+    return parser.parse_args()
 
-  return parser.parse_args()
 
 def print_args(args):
-  debug_print("parsed arguments:")
-  debug_print(".input  = ", args.input)
-  debug_print(".output = ", args.output)
-  debug_print(".loader_file = ", args.loader_file)
-  debug_print(".spi_size (KB) = ", hex(args.spi_size))
-  debug_print(".image_size = ", hex(args.image_size))
-  debug_print(".tag0_loc = ", hex(args.tag0_loc))
-  debug_print(".tag1_loc = ", hex(args.tag1_loc))
-  debug_print(".header_loc = ", hex(args.header_loc))
-  if args.rw_loc < 0:
-    debug_print(".rw_loc = ", args.rw_loc)
-  else:
-    debug_print(".rw_loc = ", hex(args.rw_loc))
-  debug_print(".spi_clock (MHz) = ", args.spi_clock)
-  debug_print(".spi_read_cmd = ", hex(args.spi_read_cmd))
-  debug_print(".test_spi = ", args.test_spi)
-  debug_print(".test_ecrw = ", args.test_ecrw)
-  debug_print(".verbose = ", args.verbose)
-  debug_print(".spi_drive_str = ", args.spi_drive_str)
-  debug_print(".spi_slew_fast = ", args.spi_slew_fast)
-  debug_print(".spi_cpol = ", args.spi_cpol)
-  debug_print(".spi_cpha_mosi = ", args.spi_cpha_mosi)
-  debug_print(".spi_cpha_miso = ", args.spi_cpha_miso)
-  debug_print(".vtr2_V18 = ", args.vtr2_V18)
-  debug_print(".vtr3_V18 = ", args.vtr3_V18)
+    debug_print("parsed arguments:")
+    debug_print(".input  = ", args.input)
+    debug_print(".output = ", args.output)
+    debug_print(".loader_file = ", args.loader_file)
+    debug_print(".spi_size (KB) = ", hex(args.spi_size))
+    debug_print(".image_size = ", hex(args.image_size))
+    debug_print(".tag0_loc = ", hex(args.tag0_loc))
+    debug_print(".tag1_loc = ", hex(args.tag1_loc))
+    debug_print(".header_loc = ", hex(args.header_loc))
+    if args.rw_loc < 0:
+        debug_print(".rw_loc = ", args.rw_loc)
+    else:
+        debug_print(".rw_loc = ", hex(args.rw_loc))
+    debug_print(".spi_clock (MHz) = ", args.spi_clock)
+    debug_print(".spi_read_cmd = ", hex(args.spi_read_cmd))
+    debug_print(".test_spi = ", args.test_spi)
+    debug_print(".test_ecrw = ", args.test_ecrw)
+    debug_print(".verbose = ", args.verbose)
+    debug_print(".spi_drive_str = ", args.spi_drive_str)
+    debug_print(".spi_slew_fast = ", args.spi_slew_fast)
+    debug_print(".spi_cpol = ", args.spi_cpol)
+    debug_print(".spi_cpha_mosi = ", args.spi_cpha_mosi)
+    debug_print(".spi_cpha_miso = ", args.spi_cpha_miso)
+    debug_print(".vtr2_V18 = ", args.vtr2_V18)
+    debug_print(".vtr3_V18 = ", args.vtr3_V18)
+
 
 #
 # Handle quiet mode build from Makefile
@@ -589,215 +702,239 @@ def print_args(args):
 #                       || 48 * [0]
 #
 def main():
-  global debug_print
-
-  args = parseargs()
-
-  if args.verbose:
-    debug_print = print
+    global debug_print
+
+    args = parseargs()
+
+    if args.verbose:
+        debug_print = print
+
+    debug_print("Begin pack_ec_mec152x.py script")
+
+    print_args(args)
+
+    chip_dict = MEC152X_DICT
+
+    # Boot-ROM requires header location aligned >= 256 bytes.
+    # CrOS EC flash image update code requires EC_RO/RW location to be aligned
+    # on a flash erase size boundary and EC_RO/RW size to be a multiple of
+    # the smallest flash erase block size.
+    #
+    assert (args.header_loc % SPI_ERASE_BLOCK_SIZE) == 0, (
+        "Header location %d is not on a flash erase block boundary boundary"
+        % args.header_loc
+    )
+
+    max_image_size = CHIP_MAX_CODE_SRAM_KB - LFW_SIZE
+    if args.test_spi:
+        max_image_size -= 32  # SHA256 digest
+
+    assert args.image_size > max_image_size, (
+        "Image size exceeds maximum" % args.image_size
+    )
+
+    spi_size = args.spi_size * 1024
+    debug_print("SPI Flash image size in bytes =", hex(spi_size))
+
+    # !!! IMPORTANT !!!
+    # These values MUST match chip/mchp/config_flash_layout.h
+    # defines.
+    # MEC152x Boot-ROM TAGs are at offset 0 and 4.
+    # lfw + EC_RO starts at beginning of second 4KB sector
+    # EC_RW starts at (flash size / 2) i.e. 0x40000 for a 512KB flash.
+
+    spi_list = []
+
+    debug_print("args.input = ", args.input)
+    debug_print("args.loader_file = ", args.loader_file)
+    debug_print("args.image_size = ", hex(args.image_size))
+
+    rorofile = PacklfwRoImage(args.input, args.loader_file, args.image_size)
+    debug_print("Temporary file containing LFW + EC_RO is ", rorofile)
+
+    lfw_ecro = GetPayload(rorofile, chip_dict["PAD_SIZE"])
+    lfw_ecro_len = len(lfw_ecro)
+    debug_print("Padded LFW + EC_RO length = ", hex(lfw_ecro_len))
+
+    # SPI test mode compute CRC32 of EC_RO and store in last 4 bytes
+    if args.test_spi:
+        crc32_ecro = zlib.crc32(bytes(lfw_ecro[LFW_SIZE:-4]))
+        crc32_ecro_bytes = crc32_ecro.to_bytes(4, byteorder="little")
+        lfw_ecro[-4:] = crc32_ecro_bytes
+        debug_print("ecro len = ", hex(len(lfw_ecro) - LFW_SIZE))
+        debug_print("CRC32(ecro-4) = ", hex(crc32_ecro))
+
+    # Reads entry point from offset 4 of file.
+    # This assumes binary has Cortex-M4 vector table at offset 0.
+    # 32-bit word at offset 0x0 initial stack pointer value
+    # 32-bit word at offset 0x4 address of reset handler
+    # NOTE: reset address will have bit[0]=1 to ensure thumb mode.
+    lfw_ecro_entry = GetEntryPoint(rorofile)
+
+    # Chromebooks are not using MEC BootROM SPI header/payload authentication
+    # or payload encryption. In this case the header authentication signature
+    # is filled with the hash digest of the respective entity.
+    # BuildHeader2 computes the hash digest and stores it in the correct
+    # header location.
+    header = BuildHeader2(
+        args, chip_dict, lfw_ecro_len, LOAD_ADDR, lfw_ecro_entry
+    )
+    printByteArrayAsHex(header, "Header(lfw_ecro)")
+
+    ec_info_block = GenEcInfoBlock(args, chip_dict)
+    printByteArrayAsHex(ec_info_block, "EC Info Block")
+
+    cosignature = GenCoSignature(args, chip_dict, lfw_ecro)
+    printByteArrayAsHex(cosignature, "LFW + EC_RO cosignature")
+
+    trailer = GenTrailer(
+        args, chip_dict, lfw_ecro, None, ec_info_block, cosignature
+    )
+
+    printByteArrayAsHex(trailer, "LFW + EC_RO trailer")
+
+    # Build TAG0. Set TAG1=TAG0 Boot-ROM is allowed to load EC-RO only.
+    tag0 = BuildTag(args)
+    tag1 = tag0
+
+    debug_print("Call to GetPayloadFromOffset")
+    debug_print("args.input = ", args.input)
+    debug_print("args.image_size = ", hex(args.image_size))
+
+    ecrw = GetPayloadFromOffset(
+        args.input, args.image_size, chip_dict["PAD_SIZE"]
+    )
+    debug_print("type(ecrw) is ", type(ecrw))
+    debug_print("len(ecrw) is ", hex(len(ecrw)))
+
+    # truncate to args.image_size
+    ecrw_len = len(ecrw)
+    if ecrw_len > args.image_size:
+        debug_print(
+            "Truncate EC_RW len={0:0x} to image_size={1:0x}".format(
+                ecrw_len, args.image_size
+            )
+        )
+        ecrw = ecrw[: args.image_size]
+        ecrw_len = len(ecrw)
+
+    debug_print("len(EC_RW) = ", hex(ecrw_len))
+
+    # SPI test mode compute CRC32 of EC_RW and store in last 4 bytes
+    if args.test_spi:
+        crc32_ecrw = zlib.crc32(bytes(ecrw[0:-4]))
+        crc32_ecrw_bytes = crc32_ecrw.to_bytes(4, byteorder="little")
+        ecrw[-4:] = crc32_ecrw_bytes
+        debug_print("ecrw len = ", hex(len(ecrw)))
+        debug_print("CRC32(ecrw) = ", hex(crc32_ecrw))
+
+    # Assume FW layout is standard Cortex-M style with vector
+    # table at start of binary.
+    # 32-bit word at offset 0x0 = Initial stack pointer
+    # 32-bit word at offset 0x4 = Address of reset handler
+    ecrw_entry_tuple = struct.unpack_from("<I", ecrw, 4)
+    debug_print("ecrw_entry_tuple[0] = ", hex(ecrw_entry_tuple[0]))
+
+    ecrw_entry = ecrw_entry_tuple[0]
+    debug_print("ecrw_entry = ", hex(ecrw_entry))
+
+    # Note: payload_rw is a bytearray therefore is mutable
+    if args.test_ecrw:
+        gen_test_ecrw(ecrw)
+
+    os.remove(rorofile)  # clean up the temp file
+
+    # MEC152X Add TAG's
+    spi_list.append((args.tag0_loc, tag0, "tag0"))
+    spi_list.append((args.tag1_loc, tag1, "tag1"))
+
+    # flashmap is non-zero only for systems with two external
+    # SPI flash chips.
+    flashmap = BuildFlashMap(0)
+    spi_list.append((8, flashmap, "flashmap"))
+
+    # Boot-ROM SPI image header for LFW+EC-RO
+    spi_list.append((args.header_loc, header, "header(lfw + ro)"))
+    spi_list.append(
+        (args.header_loc + chip_dict["PAYLOAD_OFFSET"], lfw_ecro, "lfw_ecro")
+    )
+
+    offset = args.header_loc + chip_dict["PAYLOAD_OFFSET"] + lfw_ecro_len
 
-  debug_print("Begin pack_ec_mec152x.py script")
-
-  print_args(args)
-
-  chip_dict = MEC152X_DICT
-
-  # Boot-ROM requires header location aligned >= 256 bytes.
-  # CrOS EC flash image update code requires EC_RO/RW location to be aligned
-  # on a flash erase size boundary and EC_RO/RW size to be a multiple of
-  # the smallest flash erase block size.
-  #
-  assert (args.header_loc % SPI_ERASE_BLOCK_SIZE) == 0, \
-      "Header location %d is not on a flash erase block boundary boundary" % args.header_loc
-
-  max_image_size = CHIP_MAX_CODE_SRAM_KB - LFW_SIZE
-  if args.test_spi:
-      max_image_size -= 32 # SHA256 digest
-
-  assert args.image_size > max_image_size, \
-      "Image size exceeds maximum" % args.image_size
-
-  spi_size = args.spi_size * 1024
-  debug_print("SPI Flash image size in bytes =", hex(spi_size))
-
-  # !!! IMPORTANT !!!
-  # These values MUST match chip/mchp/config_flash_layout.h
-  # defines.
-  # MEC152x Boot-ROM TAGs are at offset 0 and 4.
-  # lfw + EC_RO starts at beginning of second 4KB sector
-  # EC_RW starts at (flash size / 2) i.e. 0x40000 for a 512KB flash.
-
-  spi_list = []
-
-  debug_print("args.input = ",args.input)
-  debug_print("args.loader_file = ",args.loader_file)
-  debug_print("args.image_size = ",hex(args.image_size))
-
-  rorofile=PacklfwRoImage(args.input, args.loader_file, args.image_size)
-  debug_print("Temporary file containing LFW + EC_RO is ", rorofile)
-
-  lfw_ecro = GetPayload(rorofile, chip_dict["PAD_SIZE"])
-  lfw_ecro_len = len(lfw_ecro)
-  debug_print("Padded LFW + EC_RO length = ", hex(lfw_ecro_len))
-
-  # SPI test mode compute CRC32 of EC_RO and store in last 4 bytes
-  if args.test_spi:
-      crc32_ecro = zlib.crc32(bytes(lfw_ecro[LFW_SIZE:-4]))
-      crc32_ecro_bytes = crc32_ecro.to_bytes(4, byteorder='little')
-      lfw_ecro[-4:] = crc32_ecro_bytes
-      debug_print("ecro len = ", hex(len(lfw_ecro) - LFW_SIZE))
-      debug_print("CRC32(ecro-4) = ", hex(crc32_ecro))
-
-  # Reads entry point from offset 4 of file.
-  # This assumes binary has Cortex-M4 vector table at offset 0.
-  # 32-bit word at offset 0x0 initial stack pointer value
-  # 32-bit word at offset 0x4 address of reset handler
-  # NOTE: reset address will have bit[0]=1 to ensure thumb mode.
-  lfw_ecro_entry = GetEntryPoint(rorofile)
-
-  # Chromebooks are not using MEC BootROM SPI header/payload authentication
-  # or payload encryption. In this case the header authentication signature
-  # is filled with the hash digest of the respective entity.
-  # BuildHeader2 computes the hash digest and stores it in the correct
-  # header location.
-  header = BuildHeader2(args, chip_dict, lfw_ecro_len,
-                        LOAD_ADDR, lfw_ecro_entry)
-  printByteArrayAsHex(header, "Header(lfw_ecro)")
-
-  # If payload encryption used then encrypt payload and
-  # generate Payload Key Header. If encryption not used
-  # payload is not modified and the method returns None
-  encryption_key_header = EncryptPayload(args, chip_dict, lfw_ecro)
-  printByteArrayAsHex(encryption_key_header,
-                      "LFW + EC_RO encryption_key_header")
-
-  ec_info_block = GenEcInfoBlock(args, chip_dict)
-  printByteArrayAsHex(ec_info_block, "EC Info Block")
-
-  cosignature = GenCoSignature(args, chip_dict, lfw_ecro)
-  printByteArrayAsHex(cosignature, "LFW + EC_RO cosignature")
-
-  trailer = GenTrailer(args, chip_dict, lfw_ecro, encryption_key_header,
-                       ec_info_block, cosignature)
-
-  printByteArrayAsHex(trailer, "LFW + EC_RO trailer")
-
-  # Build TAG0. Set TAG1=TAG0 Boot-ROM is allowed to load EC-RO only.
-  tag0 = BuildTag(args)
-  tag1 = tag0
-
-  debug_print("Call to GetPayloadFromOffset")
-  debug_print("args.input = ", args.input)
-  debug_print("args.image_size = ", hex(args.image_size))
-
-  ecrw = GetPayloadFromOffset(args.input, args.image_size,
-                              chip_dict["PAD_SIZE"])
-  debug_print("type(ecrw) is ", type(ecrw))
-  debug_print("len(ecrw) is ", hex(len(ecrw)))
-
-  # truncate to args.image_size
-  ecrw_len = len(ecrw)
-  if ecrw_len > args.image_size:
-      debug_print("Truncate EC_RW len={0:0x} to image_size={1:0x}".format(ecrw_len,args.image_size))
-      ecrw = ecrw[:args.image_size]
-      ecrw_len = len(ecrw)
-
-  debug_print("len(EC_RW) = ", hex(ecrw_len))
-
-  # SPI test mode compute CRC32 of EC_RW and store in last 4 bytes
-  if args.test_spi:
-      crc32_ecrw = zlib.crc32(bytes(ecrw[0:-4]))
-      crc32_ecrw_bytes = crc32_ecrw.to_bytes(4, byteorder='little')
-      ecrw[-4:] = crc32_ecrw_bytes
-      debug_print("ecrw len = ", hex(len(ecrw)))
-      debug_print("CRC32(ecrw) = ", hex(crc32_ecrw))
-
-  # Assume FW layout is standard Cortex-M style with vector
-  # table at start of binary.
-  # 32-bit word at offset 0x0 = Initial stack pointer
-  # 32-bit word at offset 0x4 = Address of reset handler
-  ecrw_entry_tuple = struct.unpack_from('<I', ecrw, 4)
-  debug_print("ecrw_entry_tuple[0] = ", hex(ecrw_entry_tuple[0]))
-
-  ecrw_entry = ecrw_entry_tuple[0]
-  debug_print("ecrw_entry = ", hex(ecrw_entry))
-
-  # Note: payload_rw is a bytearray therefore is mutable
-  if args.test_ecrw:
-    gen_test_ecrw(ecrw)
-
-  os.remove(rorofile)           # clean up the temp file
-
-  # MEC152X Add TAG's
-  spi_list.append((args.tag0_loc, tag0, "tag0"))
-  spi_list.append((args.tag1_loc, tag1, "tag1"))
-
-  # flashmap is non-zero only for systems with two external
-  # SPI flash chips.
-  flashmap = BuildFlashMap(0)
-  spi_list.append((8, flashmap, "flashmap"))
-
-  # Boot-ROM SPI image header for LFW+EC-RO
-  spi_list.append((args.header_loc, header, "header(lfw + ro)"))
-  spi_list.append((args.header_loc + chip_dict["PAYLOAD_OFFSET"], lfw_ecro,
-                   "lfw_ecro"))
-
-  offset = args.header_loc + chip_dict["PAYLOAD_OFFSET"] + lfw_ecro_len
-
-  if ec_info_block != None:
-    spi_list.append((offset, ec_info_block, "EC Info Block"))
-    offset += len(ec_info_block)
-
-  if cosignature != None:
-    spi_list.append((offset, cosignature, "ECRO Cosignature"))
-    offset += len(cosignature)
-
-  if trailer != None:
-    spi_list.append((offset, trailer, "ECRO Trailer"))
-    offset += len(trailer)
-
-  # EC_RW location
-  rw_offset = int(spi_size // 2)
-  if args.rw_loc >= 0:
-    rw_offset = args.rw_loc
-
-  debug_print("rw_offset = 0x{0:08x}".format(rw_offset))
-
-  assert rw_offset >= offset, \
-      print("""Offset of EC_RW at {0:08x} overlaps end
-               of EC_RO at {0:08x}""".format(rw_offset, offset))
-
-  spi_list.append((rw_offset, ecrw, "ecrw"))
-  offset = rw_offset + len(ecrw)
-
-  spi_list = sorted(spi_list)
-
-  dumpsects(spi_list)
-
-  #
-  # MEC152X Boot-ROM locates TAG0/1 at SPI offset 0
-  # instead of end of SPI.
-  #
-  with open(args.output, 'wb') as f:
-    debug_print("Write spi list to file", args.output)
-    addr = 0
-    for s in spi_list:
-      if addr < s[0]:
-        debug_print("Offset ",hex(addr)," Length", hex(s[0]-addr),
-                "fill with 0xff")
-        f.write(b'\xff' * (s[0] - addr))
-        addr = s[0]
-        debug_print("Offset ",hex(addr), " Length", hex(len(s[1])), "write data")
-
-      f.write(s[1])
-      addr += len(s[1])
-
-    if addr < spi_size:
-      debug_print("Offset ",hex(addr), " Length", hex(spi_size - addr),
-              "fill with 0xff")
-      f.write(b'\xff' * (spi_size - addr))
-
-    f.flush()
+    if ec_info_block != None:
+        spi_list.append((offset, ec_info_block, "EC Info Block"))
+        offset += len(ec_info_block)
 
-if __name__ == '__main__':
-  main()
+    if cosignature != None:
+        spi_list.append((offset, cosignature, "ECRO Cosignature"))
+        offset += len(cosignature)
+
+    if trailer != None:
+        spi_list.append((offset, trailer, "ECRO Trailer"))
+        offset += len(trailer)
+
+    # EC_RW location
+    rw_offset = int(spi_size // 2)
+    if args.rw_loc >= 0:
+        rw_offset = args.rw_loc
+
+    debug_print("rw_offset = 0x{0:08x}".format(rw_offset))
+
+    assert rw_offset >= offset, print(
+        """Offset of EC_RW at {0:08x} overlaps end
+               of EC_RO at {1:08x}""".format(
+            rw_offset, offset
+        )
+    )
+
+    spi_list.append((rw_offset, ecrw, "ecrw"))
+    offset = rw_offset + len(ecrw)
+
+    spi_list = sorted(spi_list)
+
+    dumpsects(spi_list)
+
+    #
+    # MEC152X Boot-ROM locates TAG0/1 at SPI offset 0
+    # instead of end of SPI.
+    #
+    with open(args.output, "wb") as f:
+        debug_print("Write spi list to file", args.output)
+        addr = 0
+        for s in spi_list:
+            if addr < s[0]:
+                debug_print(
+                    "Offset ",
+                    hex(addr),
+                    " Length",
+                    hex(s[0] - addr),
+                    "fill with 0xff",
+                )
+                f.write(b"\xff" * (s[0] - addr))
+                addr = s[0]
+                debug_print(
+                    "Offset ",
+                    hex(addr),
+                    " Length",
+                    hex(len(s[1])),
+                    "write data",
+                )
+
+            f.write(s[1])
+            addr += len(s[1])
+
+        if addr < spi_size:
+            debug_print(
+                "Offset ",
+                hex(addr),
+                " Length",
+                hex(spi_size - addr),
+                "fill with 0xff",
+            )
+            f.write(b"\xff" * (spi_size - addr))
+
+        f.flush()
+
+
+if __name__ == "__main__":
+    main()
diff --git a/chip/mchp/util/pack_ec_mec172x.py b/chip/mchp/util/pack_ec_mec172x.py
index 32747d3d9a..6bd2db984b 100755
--- a/chip/mchp/util/pack_ec_mec172x.py
+++ b/chip/mchp/util/pack_ec_mec172x.py
@@ -1,12 +1,8 @@
 #!/usr/bin/env python3
 
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
 
 # A script to pack EC binary into SPI flash image for MEC172x
 # Based on MEC172x_ROM_Description.pdf revision 6/8/2020
@@ -16,7 +12,7 @@ import os
 import struct
 import subprocess
 import tempfile
-import zlib # CRC32
+import zlib  # CRC32
 
 # MEC172x has 416KB SRAM from 0xC0000 - 0x127FFF
 # SRAM is divided into contiguous CODE & DATA
@@ -28,8 +24,8 @@ import zlib # CRC32
 #
 SPI_ERASE_BLOCK_SIZE = 0x1000
 SPI_CLOCK_LIST = [48, 24, 16, 12, 96]
-SPI_READ_CMD_LIST = [0x3, 0xb, 0x3b, 0x6b]
-SPI_DRIVE_STR_DICT = {2:0, 4:1, 8:2, 12:3}
+SPI_READ_CMD_LIST = [0x3, 0xB, 0x3B, 0x6B]
+SPI_DRIVE_STR_DICT = {2: 0, 4: 1, 8: 2, 12: 3}
 # Maximum EC_RO/EC_RW code size is based upon SPI flash erase
 # sector size, MEC172x Boot-ROM TAG, Header, Footer.
 # SPI Offset      Description
@@ -38,118 +34,159 @@ SPI_DRIVE_STR_DICT = {2:0, 4:1, 8:2, 12:3}
 # 0x1140 - 0x213F 4KB LFW
 # 0x2040 - 0x3EFFF
 # 0x3F000 - 0x3FFFF BootROM EC_INFO_BLK || COSIG || ENCR_KEY_HDR(optional) || TRAILER
-CHIP_MAX_CODE_SRAM_KB = (256 - 12)
+CHIP_MAX_CODE_SRAM_KB = 256 - 12
 
 MEC172X_DICT = {
-                "LFW_SIZE": 0x1000,
-                "LOAD_ADDR": 0xC0000,
-                "TAG_SIZE": 4,
-                "KEY_BLOB_SIZE": 1584,
-                "HEADER_SIZE":0x140,
-                "HEADER_VER":0x03,
-                "PAYLOAD_GRANULARITY":128,
-                "PAYLOAD_PAD_BYTE":b'\xff',
-                "EC_INFO_BLK_SZ":128,
-                "ENCR_KEY_HDR_SZ":128,
-                "COSIG_SZ":96,
-                "TRAILER_SZ":160,
-                "TAILER_PAD_BYTE":b'\xff',
-                "PAD_SIZE":128
-                }
-
-CRC_TABLE = [0x00, 0x07, 0x0e, 0x09, 0x1c, 0x1b, 0x12, 0x15,
-             0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d]
+    "LFW_SIZE": 0x1000,
+    "LOAD_ADDR": 0xC0000,
+    "TAG_SIZE": 4,
+    "KEY_BLOB_SIZE": 1584,
+    "HEADER_SIZE": 0x140,
+    "HEADER_VER": 0x03,
+    "PAYLOAD_GRANULARITY": 128,
+    "PAYLOAD_PAD_BYTE": b"\xff",
+    "EC_INFO_BLK_SZ": 128,
+    "ENCR_KEY_HDR_SZ": 128,
+    "COSIG_SZ": 96,
+    "TRAILER_SZ": 160,
+    "TAILER_PAD_BYTE": b"\xff",
+    "PAD_SIZE": 128,
+}
+
+CRC_TABLE = [
+    0x00,
+    0x07,
+    0x0E,
+    0x09,
+    0x1C,
+    0x1B,
+    0x12,
+    0x15,
+    0x38,
+    0x3F,
+    0x36,
+    0x31,
+    0x24,
+    0x23,
+    0x2A,
+    0x2D,
+]
+
 
 def mock_print(*args, **kwargs):
-  pass
+    pass
+
 
 debug_print = mock_print
 
 # Debug helper routine
 def dumpsects(spi_list):
-  debug_print("spi_list has {0} entries".format(len(spi_list)))
-  for s in spi_list:
-    debug_print("0x{0:x} 0x{1:x} {2:s}".format(s[0],len(s[1]),s[2]))
+    debug_print("spi_list has {0} entries".format(len(spi_list)))
+    for s in spi_list:
+        debug_print("0x{0:x} 0x{1:x} {2:s}".format(s[0], len(s[1]), s[2]))
+
 
 def printByteArrayAsHex(ba, title):
-  debug_print(title,"= ")
-  if ba == None:
-      debug_print("None")
-      return
-
-  count = 0
-  for b in ba:
-    count = count + 1
-    debug_print("0x{0:02x}, ".format(b),end="")
-    if (count % 8) == 0:
-      debug_print("")
-  debug_print("")
+    debug_print(title, "= ")
+    if ba == None:
+        debug_print("None")
+        return
+
+    count = 0
+    for b in ba:
+        count = count + 1
+        debug_print("0x{0:02x}, ".format(b), end="")
+        if (count % 8) == 0:
+            debug_print("")
+    debug_print("")
+
 
 def Crc8(crc, data):
-  """Update CRC8 value."""
-  for v in data:
-    crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v >> 4)]);
-    crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v & 0xf)]);
-  return crc ^ 0x55
+    """Update CRC8 value."""
+    for v in data:
+        crc = ((crc << 4) & 0xFF) ^ (CRC_TABLE[(crc >> 4) ^ (v >> 4)])
+        crc = ((crc << 4) & 0xFF) ^ (CRC_TABLE[(crc >> 4) ^ (v & 0xF)])
+    return crc ^ 0x55
+
 
 def GetEntryPoint(payload_file):
-  """Read entry point from payload EC image."""
-  with open(payload_file, 'rb') as f:
-    f.seek(4)
-    s = f.read(4)
-  return int.from_bytes(s, byteorder='little')
-
-def GetPayloadFromOffset(payload_file, offset, padsize):
-  """Read payload and pad it to padsize."""
-  with open(payload_file, 'rb') as f:
-    f.seek(offset)
-    payload = bytearray(f.read())
-  rem_len = len(payload) % padsize
-  debug_print("GetPayload: padsize={0:0x} len(payload)={1:0x} rem={2:0x}".format(padsize,len(payload),rem_len))
-
-  if rem_len:
-    payload += PAYLOAD_PAD_BYTE * (padsize - rem_len)
-    debug_print("GetPayload: Added {0} padding bytes".format(padsize - rem_len))
-
-  return payload
-
-def GetPayload(payload_file, padsize):
-  """Read payload and pad it to padsize"""
-  return GetPayloadFromOffset(payload_file, 0, padsize)
+    """Read entry point from payload EC image."""
+    with open(payload_file, "rb") as f:
+        f.seek(4)
+        s = f.read(4)
+    return int.from_bytes(s, byteorder="little")
+
+
+def GetPayloadFromOffset(payload_file, offset, chip_dict):
+    """Read payload and pad it to chip_dict["PAD_SIZE"]."""
+    padsize = chip_dict["PAD_SIZE"]
+    with open(payload_file, "rb") as f:
+        f.seek(offset)
+        payload = bytearray(f.read())
+    rem_len = len(payload) % padsize
+    debug_print(
+        "GetPayload: padsize={0:0x} len(payload)={1:0x} rem={2:0x}".format(
+            padsize, len(payload), rem_len
+        )
+    )
+
+    if rem_len:
+        payload += chip_dict["PAYLOAD_PAD_BYTE"] * (padsize - rem_len)
+        debug_print(
+            "GetPayload: Added {0} padding bytes".format(padsize - rem_len)
+        )
+
+    return payload
+
+
+def GetPayload(payload_file, chip_dict):
+    """Read payload and pad it to chip_dict["PAD_SIZE"]"""
+    return GetPayloadFromOffset(payload_file, 0, chip_dict)
+
 
 def GetPublicKey(pem_file):
-  """Extract public exponent and modulus from PEM file."""
-  result = subprocess.run(['openssl', 'rsa', '-in', pem_file, '-text',
-                           '-noout'], stdout=subprocess.PIPE, encoding='utf-8')
-  modulus_raw = []
-  in_modulus = False
-  for line in result.stdout.splitlines():
-    if line.startswith('modulus'):
-      in_modulus = True
-    elif not line.startswith(' '):
-      in_modulus = False
-    elif in_modulus:
-      modulus_raw.extend(line.strip().strip(':').split(':'))
-    if line.startswith('publicExponent'):
-      exp = int(line.split(' ')[1], 10)
-  modulus_raw.reverse()
-  modulus = bytearray((int(x, 16) for x in modulus_raw[:256]))
-  return struct.pack('<Q', exp), modulus
+    """Extract public exponent and modulus from PEM file."""
+    result = subprocess.run(
+        ["openssl", "rsa", "-in", pem_file, "-text", "-noout"],
+        stdout=subprocess.PIPE,
+        encoding="utf-8",
+    )
+    modulus_raw = []
+    in_modulus = False
+    for line in result.stdout.splitlines():
+        if line.startswith("modulus"):
+            in_modulus = True
+        elif not line.startswith(" "):
+            in_modulus = False
+        elif in_modulus:
+            modulus_raw.extend(line.strip().strip(":").split(":"))
+        if line.startswith("publicExponent"):
+            exp = int(line.split(" ")[1], 10)
+    modulus_raw.reverse()
+    modulus = bytearray((int(x, 16) for x in modulus_raw[:256]))
+    return struct.pack("<Q", exp), modulus
+
 
 def GetSpiClockParameter(args):
-  assert args.spi_clock in SPI_CLOCK_LIST, \
-         "Unsupported SPI clock speed %d MHz" % args.spi_clock
-  return SPI_CLOCK_LIST.index(args.spi_clock)
+    assert args.spi_clock in SPI_CLOCK_LIST, (
+        "Unsupported SPI clock speed %d MHz" % args.spi_clock
+    )
+    return SPI_CLOCK_LIST.index(args.spi_clock)
+
 
 def GetSpiReadCmdParameter(args):
-  assert args.spi_read_cmd in SPI_READ_CMD_LIST, \
-         "Unsupported SPI read command 0x%x" % args.spi_read_cmd
-  return SPI_READ_CMD_LIST.index(args.spi_read_cmd)
+    assert args.spi_read_cmd in SPI_READ_CMD_LIST, (
+        "Unsupported SPI read command 0x%x" % args.spi_read_cmd
+    )
+    return SPI_READ_CMD_LIST.index(args.spi_read_cmd)
+
 
 def GetEncodedSpiDriveStrength(args):
-  assert args.spi_drive_str in SPI_DRIVE_STR_DICT, \
-         "Unsupported SPI drive strength %d mA" % args.spi_drive_str
-  return SPI_DRIVE_STR_DICT.get(args.spi_drive_str)
+    assert args.spi_drive_str in SPI_DRIVE_STR_DICT, (
+        "Unsupported SPI drive strength %d mA" % args.spi_drive_str
+    )
+    return SPI_DRIVE_STR_DICT.get(args.spi_drive_str)
+
 
 # Return 0=Slow slew rate or 1=Fast slew rate
 def GetSpiSlewRate(args):
@@ -157,12 +194,14 @@ def GetSpiSlewRate(args):
         return 1
     return 0
 
+
 # Return SPI CPOL = 0 or 1
 def GetSpiCpol(args):
     if args.spi_cpol == 0:
         return 0
     return 1
 
+
 # Return SPI CPHA_MOSI
 # 0 = SPI Master drives data is stable on inactive to clock edge
 # 1 = SPI Master drives data is stable on active to inactive clock edge
@@ -171,6 +210,7 @@ def GetSpiCphaMosi(args):
         return 0
     return 1
 
+
 # Return SPI CPHA_MISO 0 or 1
 # 0 = SPI Master samples data on inactive to active clock edge
 # 1 = SPI Master samples data on active to inactive clock edge
@@ -179,14 +219,10 @@ def GetSpiCphaMiso(args):
         return 0
     return 1
 
+
 def PadZeroTo(data, size):
-  data.extend(b'\0' * (size - len(data)))
+    data.extend(b"\0" * (size - len(data)))
 
-#
-# Boot-ROM SPI image encryption not used with Chromebooks
-#
-def EncryptPayload(args, chip_dict, payload):
-    return None
 
 #
 # Build SPI image header for MEC172x
@@ -262,89 +298,98 @@ def EncryptPayload(args, chip_dict, payload):
 # header[0x110:0x140] = Header ECDSA-384 signature y-coor. = 0 Auth. disabled
 #
 def BuildHeader2(args, chip_dict, payload_len, load_addr, payload_entry):
-  header_size = chip_dict["HEADER_SIZE"]
-
-  # allocate zero filled header
-  header = bytearray(b'\x00' * header_size)
-  debug_print("len(header) = ", len(header))
-
-  # Identifier and header version
-  header[0:4] = b'PHCM'
-  header[4] = chip_dict["HEADER_VER"]
-
-  # SPI frequency, drive strength, CPOL/CPHA encoding same for both chips
-  spiFreqIndex = GetSpiClockParameter(args)
-  if spiFreqIndex > 3:
-    header[6] |= 0x01
-  else:
-    header[5] = spiFreqIndex
-
-  header[5] |= ((GetEncodedSpiDriveStrength(args) & 0x03) << 2)
-  header[5] |= ((GetSpiSlewRate(args) & 0x01) << 4)
-  header[5] |= ((GetSpiCpol(args) & 0x01) << 5)
-  header[5] |= ((GetSpiCphaMosi(args) & 0x01) << 6)
-  header[5] |= ((GetSpiCphaMiso(args) & 0x01) << 7)
-
-  # header[6]
-  # b[0] value set above
-  # b[2:1] = 00b, b[5:3]=111b
-  # b[7]=0 No encryption of FW payload
-  header[6] |= 0x7 << 3
-
-  # SPI read command set same for both chips
-  header[7] = GetSpiReadCmdParameter(args) & 0xFF
-
-  # bytes 0x08 - 0x0b
-  header[0x08:0x0C] = load_addr.to_bytes(4, byteorder='little')
-  # bytes 0x0c - 0x0f
-  header[0x0C:0x10] = payload_entry.to_bytes(4, byteorder='little')
-
-  # bytes 0x10 - 0x11 payload length in units of 128 bytes
-  assert payload_len % chip_dict["PAYLOAD_GRANULARITY"] == 0, \
-         print("Payload size not a multiple of {0}".format(chip_dict["PAYLOAD_GRANULARITY"]))
-
-  payload_units = int(payload_len // chip_dict["PAYLOAD_GRANULARITY"])
-  assert payload_units < 0x10000, \
-      print("Payload too large: len={0} units={1}".format(payload_len, payload_units))
-
-  header[0x10:0x12] = payload_units.to_bytes(2, 'little')
-
-  # bytes 0x14 - 0x17 TODO offset from start of payload to FW payload to be
-  # loaded by Boot-ROM. We ask Boot-ROM to load (LFW || EC_RO).
-  # LFW location provided on the command line.
-  assert (args.lfw_loc % 4096 == 0), \
-         print("LFW location not on a 4KB boundary! 0x{0:0x}".format(args.lfw_loc))
-
-  assert args.lfw_loc >= (args.header_loc + chip_dict["HEADER_SIZE"]), \
-         print("LFW location not greater than header location + header size")
-
-  lfw_ofs = args.lfw_loc - args.header_loc
-  header[0x14:0x18] = lfw_ofs.to_bytes(4, 'little')
-
-  # MEC172x: authentication key select. Authentication not used, set to 0.
-  header[0x18] = 0
-
-  # header[0x19], header[0x20:0x28]
-  # header[0x1A:0x20] reserved 0
-  # MEC172x: supports SPI flash devices with drive strength settings
-  # TODO leave these fields at 0 for now. We must add 6 command line
-  # arguments.
-
-  # header[0x28:0x48] reserve can be any value
-  # header[0x48:0x50] Customer use. TODO
-  # authentication disabled, leave these 0.
-  # header[0x50:0x80] ECDSA P384 Authentication Public key Rx
-  # header[0x80:0xB0] ECDSA P384 Authentication Public key Ry
-
-  # header[0xB0:0xE0] = SHA384(header[0:0xB0])
-  header[0xB0:0xE0] = hashlib.sha384(header[0:0xB0]).digest()
-  # When ECDSA authentication is disabled MCHP SPI image generator
-  # is filling the last 48 bytes of the Header with 0xff
-  header[-48:] = b'\xff' * 48
-
-  debug_print("After hash: len(header) = ", len(header))
-
-  return header
+    header_size = chip_dict["HEADER_SIZE"]
+
+    # allocate zero filled header
+    header = bytearray(b"\x00" * header_size)
+    debug_print("len(header) = ", len(header))
+
+    # Identifier and header version
+    header[0:4] = b"PHCM"
+    header[4] = chip_dict["HEADER_VER"]
+
+    # SPI frequency, drive strength, CPOL/CPHA encoding same for both chips
+    spiFreqIndex = GetSpiClockParameter(args)
+    if spiFreqIndex > 3:
+        header[6] |= 0x01
+    else:
+        header[5] = spiFreqIndex
+
+    header[5] |= (GetEncodedSpiDriveStrength(args) & 0x03) << 2
+    header[5] |= (GetSpiSlewRate(args) & 0x01) << 4
+    header[5] |= (GetSpiCpol(args) & 0x01) << 5
+    header[5] |= (GetSpiCphaMosi(args) & 0x01) << 6
+    header[5] |= (GetSpiCphaMiso(args) & 0x01) << 7
+
+    # header[6]
+    # b[0] value set above
+    # b[2:1] = 00b, b[5:3]=111b
+    # b[7]=0 No encryption of FW payload
+    header[6] |= 0x7 << 3
+
+    # SPI read command set same for both chips
+    header[7] = GetSpiReadCmdParameter(args) & 0xFF
+
+    # bytes 0x08 - 0x0b
+    header[0x08:0x0C] = load_addr.to_bytes(4, byteorder="little")
+    # bytes 0x0c - 0x0f
+    header[0x0C:0x10] = payload_entry.to_bytes(4, byteorder="little")
+
+    # bytes 0x10 - 0x11 payload length in units of 128 bytes
+    assert payload_len % chip_dict["PAYLOAD_GRANULARITY"] == 0, print(
+        "Payload size not a multiple of {0}".format(
+            chip_dict["PAYLOAD_GRANULARITY"]
+        )
+    )
+
+    payload_units = int(payload_len // chip_dict["PAYLOAD_GRANULARITY"])
+    assert payload_units < 0x10000, print(
+        "Payload too large: len={0} units={1}".format(
+            payload_len, payload_units
+        )
+    )
+
+    header[0x10:0x12] = payload_units.to_bytes(2, "little")
+
+    # bytes 0x14 - 0x17 TODO offset from start of payload to FW payload to be
+    # loaded by Boot-ROM. We ask Boot-ROM to load (LFW || EC_RO).
+    # LFW location provided on the command line.
+    assert args.lfw_loc % 4096 == 0, print(
+        "LFW location not on a 4KB boundary! 0x{0:0x}".format(args.lfw_loc)
+    )
+
+    assert args.lfw_loc >= (args.header_loc + chip_dict["HEADER_SIZE"]), print(
+        "LFW location not greater than header location + header size"
+    )
+
+    lfw_ofs = args.lfw_loc - args.header_loc
+    header[0x14:0x18] = lfw_ofs.to_bytes(4, "little")
+
+    # MEC172x: authentication key select. Authentication not used, set to 0.
+    header[0x18] = 0
+
+    # header[0x19], header[0x20:0x28]
+    # header[0x1A:0x20] reserved 0
+    # MEC172x: supports SPI flash devices with drive strength settings
+    # TODO leave these fields at 0 for now. We must add 6 command line
+    # arguments.
+
+    # header[0x28:0x48] reserve can be any value
+    # header[0x48:0x50] Customer use. TODO
+    # authentication disabled, leave these 0.
+    # header[0x50:0x80] ECDSA P384 Authentication Public key Rx
+    # header[0x80:0xB0] ECDSA P384 Authentication Public key Ry
+
+    # header[0xB0:0xE0] = SHA384(header[0:0xB0])
+    header[0xB0:0xE0] = hashlib.sha384(header[0:0xB0]).digest()
+    # When ECDSA authentication is disabled MCHP SPI image generator
+    # is filling the last 48 bytes of the Header with 0xff
+    header[-48:] = b"\xff" * 48
+
+    debug_print("After hash: len(header) = ", len(header))
+
+    return header
+
 
 #
 # MEC172x 128-byte EC Info Block appended to end of padded FW binary.
@@ -361,9 +406,10 @@ def BuildHeader2(args, chip_dict, payload_len, load_addr, payload_entry):
 # byte[0x7f] = current imeage revision
 #
 def GenEcInfoBlock(args, chip_dict):
-  # ecinfo = bytearray([0xff] * chip_dict["EC_INFO_BLK_SZ"])
-  ecinfo = bytearray(chip_dict["EC_INFO_BLK_SZ"])
-  return ecinfo
+    # ecinfo = bytearray([0xff] * chip_dict["EC_INFO_BLK_SZ"])
+    ecinfo = bytearray(chip_dict["EC_INFO_BLK_SZ"])
+    return ecinfo
+
 
 #
 # Generate SPI FW image co-signature.
@@ -376,7 +422,8 @@ def GenEcInfoBlock(args, chip_dict):
 # signature.
 #
 def GenCoSignature(args, chip_dict, payload):
-    return bytearray(b'\xff' * chip_dict["COSIG_SZ"])
+    return bytearray(b"\xff" * chip_dict["COSIG_SZ"])
+
 
 #
 # Generate SPI FW Image trailer.
@@ -387,27 +434,37 @@ def GenCoSignature(args, chip_dict, payload):
 #   trailer[144:160] = 0xFF. Boot-ROM spec. says these bytes should be random.
 #       Authentication & encryption are not used therefore random data
 #       is not necessary.
-def GenTrailer(args, chip_dict, payload, encryption_key_header,
-               ec_info_block, cosignature):
+def GenTrailer(
+    args, chip_dict, payload, encryption_key_header, ec_info_block, cosignature
+):
     debug_print("GenTrailer SHA384 computation")
     trailer = bytearray(chip_dict["TAILER_PAD_BYTE"] * chip_dict["TRAILER_SZ"])
     hasher = hashlib.sha384()
     hasher.update(payload)
     debug_print("  Update: payload len=0x{0:0x}".format(len(payload)))
     if ec_info_block != None:
-      hasher.update(ec_info_block)
-      debug_print("  Update: ec_info_block len=0x{0:0x}".format(len(ec_info_block)))
+        hasher.update(ec_info_block)
+        debug_print(
+            "  Update: ec_info_block len=0x{0:0x}".format(len(ec_info_block))
+        )
     if encryption_key_header != None:
-      hasher.update(encryption_key_header)
-      debug_print("  Update: encryption_key_header len=0x{0:0x}".format(len(encryption_key_header)))
+        hasher.update(encryption_key_header)
+        debug_print(
+            "  Update: encryption_key_header len=0x{0:0x}".format(
+                len(encryption_key_header)
+            )
+        )
     if cosignature != None:
-      hasher.update(cosignature)
-      debug_print("  Update: cosignature len=0x{0:0x}".format(len(cosignature)))
+        hasher.update(cosignature)
+        debug_print(
+            "  Update: cosignature len=0x{0:0x}".format(len(cosignature))
+        )
     trailer[0:48] = hasher.digest()
-    trailer[-16:] = 16 * b'\xff'
+    trailer[-16:] = 16 * b"\xff"
 
     return trailer
 
+
 # MEC172x supports two 32-bit Tags located at offsets 0x0 and 0x4
 # in the SPI flash.
 # Tag format:
@@ -418,16 +475,25 @@ def GenTrailer(args, chip_dict, payload, encryption_key_header,
 # to the same flash part.
 #
 def BuildTag(args):
-  tag = bytearray([(args.header_loc >> 8) & 0xff,
-                   (args.header_loc >> 16) & 0xff,
-                   (args.header_loc >> 24) & 0xff])
-  tag.append(Crc8(0, tag))
-  return tag
+    tag = bytearray(
+        [
+            (args.header_loc >> 8) & 0xFF,
+            (args.header_loc >> 16) & 0xFF,
+            (args.header_loc >> 24) & 0xFF,
+        ]
+    )
+    tag.append(Crc8(0, tag))
+    return tag
+
 
 def BuildTagFromHdrAddr(header_loc):
-    tag = bytearray([(header_loc >> 8) & 0xff,
-                     (header_loc >> 16) & 0xff,
-                     (header_loc >> 24) & 0xff])
+    tag = bytearray(
+        [
+            (header_loc >> 8) & 0xFF,
+            (header_loc >> 16) & 0xFF,
+            (header_loc >> 24) & 0xFF,
+        ]
+    )
     tag.append(Crc8(0, tag))
     return tag
 
@@ -444,12 +510,13 @@ def BuildTagFromHdrAddr(header_loc):
 # Output:
 #   bytearray of length 4
 def BuildFlashMap(secondSpiFlashBaseAddr):
-  flashmap = bytearray(4)
-  flashmap[0] = (secondSpiFlashBaseAddr >> 12) & 0xff
-  flashmap[1] = (secondSpiFlashBaseAddr >> 20) & 0xff
-  flashmap[2] = (secondSpiFlashBaseAddr >> 28) & 0xff
-  flashmap[3] = Crc8(0, flashmap)
-  return flashmap
+    flashmap = bytearray(4)
+    flashmap[0] = (secondSpiFlashBaseAddr >> 12) & 0xFF
+    flashmap[1] = (secondSpiFlashBaseAddr >> 20) & 0xFF
+    flashmap[2] = (secondSpiFlashBaseAddr >> 28) & 0xFF
+    flashmap[3] = Crc8(0, flashmap)
+    return flashmap
+
 
 #
 # Creates temporary file for read/write
@@ -460,21 +527,22 @@ def BuildFlashMap(secondSpiFlashBaseAddr):
 # Returns temporary file name
 #
 def PacklfwRoImage(rorw_file, loader_file, image_size):
-  """Create a temp file with the
-  first image_size bytes from the loader file and append bytes
-  from the rorw file.
-  return the filename"""
-  fo=tempfile.NamedTemporaryFile(delete=False) # Need to keep file around
-  with open(loader_file,'rb') as fin1: # read 4KB loader file
-    pro = fin1.read()
-  fo.write(pro)            # write 4KB loader data to temp file
-  with open(rorw_file, 'rb') as fin:
-    ro = fin.read(image_size)
-
-  fo.write(ro)
-  fo.close()
-
-  return fo.name
+    """Create a temp file with the
+    first image_size bytes from the loader file and append bytes
+    from the rorw file.
+    return the filename"""
+    fo = tempfile.NamedTemporaryFile(delete=False)  # Need to keep file around
+    with open(loader_file, "rb") as fin1:  # read 4KB loader file
+        pro = fin1.read()
+    fo.write(pro)  # write 4KB loader data to temp file
+    with open(rorw_file, "rb") as fin:
+        ro = fin.read(image_size)
+
+    fo.write(ro)
+    fo.close()
+
+    return fo.name
+
 
 #
 # Generate a test EC_RW image of same size
@@ -485,136 +553,200 @@ def PacklfwRoImage(rorw_file, loader_file, image_size):
 # process hash generation.
 #
 def gen_test_ecrw(pldrw):
-  debug_print("gen_test_ecrw: pldrw type =", type(pldrw))
-  debug_print("len pldrw =", len(pldrw), " = ", hex(len(pldrw)))
-  cookie1_pos = pldrw.find(b'\x99\x88\x77\xce')
-  cookie2_pos = pldrw.find(b'\xdd\xbb\xaa\xce', cookie1_pos+4)
-  t = struct.unpack("<L", pldrw[cookie1_pos+0x24:cookie1_pos+0x28])
-  size = t[0]
-  debug_print("EC_RW size =", size, " = ", hex(size))
-
-  debug_print("Found cookie1 at ", hex(cookie1_pos))
-  debug_print("Found cookie2 at ", hex(cookie2_pos))
-
-  if cookie1_pos > 0 and cookie2_pos > cookie1_pos:
-    for i in range(0, cookie1_pos):
-      pldrw[i] = 0xA5
-    for i in range(cookie2_pos+4, len(pldrw)):
-      pldrw[i] = 0xA5
-
-  with open("ec_RW_test.bin", "wb") as fecrw:
-      fecrw.write(pldrw[:size])
+    debug_print("gen_test_ecrw: pldrw type =", type(pldrw))
+    debug_print("len pldrw =", len(pldrw), " = ", hex(len(pldrw)))
+    cookie1_pos = pldrw.find(b"\x99\x88\x77\xce")
+    cookie2_pos = pldrw.find(b"\xdd\xbb\xaa\xce", cookie1_pos + 4)
+    t = struct.unpack("<L", pldrw[cookie1_pos + 0x24 : cookie1_pos + 0x28])
+    size = t[0]
+    debug_print("EC_RW size =", size, " = ", hex(size))
+
+    debug_print("Found cookie1 at ", hex(cookie1_pos))
+    debug_print("Found cookie2 at ", hex(cookie2_pos))
+
+    if cookie1_pos > 0 and cookie2_pos > cookie1_pos:
+        for i in range(0, cookie1_pos):
+            pldrw[i] = 0xA5
+        for i in range(cookie2_pos + 4, len(pldrw)):
+            pldrw[i] = 0xA5
+
+    with open("ec_RW_test.bin", "wb") as fecrw:
+        fecrw.write(pldrw[:size])
+
 
 def parseargs():
-  rpath = os.path.dirname(os.path.relpath(__file__))
-
-  parser = argparse.ArgumentParser()
-  parser.add_argument("-i", "--input",
-              help="EC binary to pack, usually ec.bin or ec.RO.flat.",
-              metavar="EC_BIN", default="ec.bin")
-  parser.add_argument("-o", "--output",
-                      help="Output flash binary file",
-                      metavar="EC_SPI_FLASH", default="ec.packed.bin")
-  parser.add_argument("--loader_file",
-                      help="EC loader binary",
-                      default="ecloader.bin")
-  parser.add_argument("--load_addr", type=int,
-                      help="EC SRAM load address",
-                      default=0xC0000)
-  parser.add_argument("-s", "--spi_size", type=int,
-                      help="Size of the SPI flash in KB",
-                      default=512)
-  parser.add_argument("-l", "--header_loc", type=int,
-                      help="Location of header in SPI flash. Must be on a 256 byte boundary",
-                      default=0x0100)
-  parser.add_argument("--lfw_loc", type=int,
-                      help="Location of LFW in SPI flash. Must be on a 4KB boundary",
-                      default=0x1000)
-  parser.add_argument("--lfw_size", type=int,
-                      help="LFW size in bytes",
-                      default=0x1000)
-  parser.add_argument("-r", "--rw_loc", type=int,
-                      help="Start offset of EC_RW. Default is -1 meaning 1/2 flash size",
-                      default=-1)
-  parser.add_argument("--spi_clock", type=int,
-                      help="SPI clock speed. 8, 12, 24, or 48 MHz.",
-                      default=24)
-  parser.add_argument("--spi_read_cmd", type=int,
-                      help="SPI read command. 0x3, 0xB, 0x3B, or 0x6B.",
-                      default=0xb)
-  parser.add_argument("--image_size", type=int,
-                      help="Size of a single image. Default 244KB",
-                      default=(244 * 1024))
-  parser.add_argument("--test_spi", action='store_true',
-                      help="Test SPI data integrity by adding CRC32 in last 4-bytes of RO/RW binaries",
-                      default=False)
-  parser.add_argument("--test_ecrw", action='store_true',
-                      help="Use fixed pattern for EC_RW but preserve image_data",
-                      default=False)
-  parser.add_argument("--verbose", action='store_true',
-                      help="Enable verbose output",
-                      default=False)
-  parser.add_argument("--tag0_loc", type=int,
-                      help="MEC172x TAG0 SPI offset",
-                      default=0)
-  parser.add_argument("--tag1_loc", type=int,
-                      help="MEC172x TAG1 SPI offset",
-                      default=4)
-  parser.add_argument("--spi_drive_str", type=int,
-                      help="Chip SPI drive strength in mA: 2, 4, 8, or 12",
-                      default=4)
-  parser.add_argument("--spi_slew_fast", action='store_true',
-                      help="SPI use fast slew rate. Default is False",
-                      default=False)
-  parser.add_argument("--spi_cpol", type=int,
-                      help="SPI clock polarity when idle. Defealt is 0(low)",
-                      default=0)
-  parser.add_argument("--spi_cpha_mosi", type=int,
-                      help="""SPI clock phase controller drives data.
+    rpath = os.path.dirname(os.path.relpath(__file__))
+
+    parser = argparse.ArgumentParser()
+    parser.add_argument(
+        "-i",
+        "--input",
+        help="EC binary to pack, usually ec.bin or ec.RO.flat.",
+        metavar="EC_BIN",
+        default="ec.bin",
+    )
+    parser.add_argument(
+        "-o",
+        "--output",
+        help="Output flash binary file",
+        metavar="EC_SPI_FLASH",
+        default="ec.packed.bin",
+    )
+    parser.add_argument(
+        "--loader_file", help="EC loader binary", default="ecloader.bin"
+    )
+    parser.add_argument(
+        "--load_addr", type=int, help="EC SRAM load address", default=0xC0000
+    )
+    parser.add_argument(
+        "-s",
+        "--spi_size",
+        type=int,
+        help="Size of the SPI flash in KB",
+        default=512,
+    )
+    parser.add_argument(
+        "-l",
+        "--header_loc",
+        type=int,
+        help="Location of header in SPI flash. Must be on a 256 byte boundary",
+        default=0x0100,
+    )
+    parser.add_argument(
+        "--lfw_loc",
+        type=int,
+        help="Location of LFW in SPI flash. Must be on a 4KB boundary",
+        default=0x1000,
+    )
+    parser.add_argument(
+        "--lfw_size", type=int, help="LFW size in bytes", default=0x1000
+    )
+    parser.add_argument(
+        "-r",
+        "--rw_loc",
+        type=int,
+        help="Start offset of EC_RW. Default is -1 meaning 1/2 flash size",
+        default=-1,
+    )
+    parser.add_argument(
+        "--spi_clock",
+        type=int,
+        help="SPI clock speed. 8, 12, 24, or 48 MHz.",
+        default=24,
+    )
+    parser.add_argument(
+        "--spi_read_cmd",
+        type=int,
+        help="SPI read command. 0x3, 0xB, 0x3B, or 0x6B.",
+        default=0xB,
+    )
+    parser.add_argument(
+        "--image_size",
+        type=int,
+        help="Size of a single image. Default 244KB",
+        default=(244 * 1024),
+    )
+    parser.add_argument(
+        "--test_spi",
+        action="store_true",
+        help="Test SPI data integrity by adding CRC32 in last 4-bytes of RO/RW binaries",
+        default=False,
+    )
+    parser.add_argument(
+        "--test_ecrw",
+        action="store_true",
+        help="Use fixed pattern for EC_RW but preserve image_data",
+        default=False,
+    )
+    parser.add_argument(
+        "--verbose",
+        action="store_true",
+        help="Enable verbose output",
+        default=False,
+    )
+    parser.add_argument(
+        "--tag0_loc", type=int, help="MEC172x TAG0 SPI offset", default=0
+    )
+    parser.add_argument(
+        "--tag1_loc", type=int, help="MEC172x TAG1 SPI offset", default=4
+    )
+    parser.add_argument(
+        "--spi_drive_str",
+        type=int,
+        help="Chip SPI drive strength in mA: 2, 4, 8, or 12",
+        default=4,
+    )
+    parser.add_argument(
+        "--spi_slew_fast",
+        action="store_true",
+        help="SPI use fast slew rate. Default is False",
+        default=False,
+    )
+    parser.add_argument(
+        "--spi_cpol",
+        type=int,
+        help="SPI clock polarity when idle. Defealt is 0(low)",
+        default=0,
+    )
+    parser.add_argument(
+        "--spi_cpha_mosi",
+        type=int,
+        help="""SPI clock phase controller drives data.
                               0=Data driven on active to inactive clock edge,
                               1=Data driven on inactive to active clock edge""",
-                      default=0)
-  parser.add_argument("--spi_cpha_miso", type=int,
-                      help="""SPI clock phase controller samples data.
+        default=0,
+    )
+    parser.add_argument(
+        "--spi_cpha_miso",
+        type=int,
+        help="""SPI clock phase controller samples data.
                               0=Data sampled on inactive to active clock edge,
                               1=Data sampled on active to inactive clock edge""",
-                      default=0)
+        default=0,
+    )
+
+    return parser.parse_args()
 
-  return parser.parse_args()
 
 def print_args(args):
-  debug_print("parsed arguments:")
-  debug_print(".input  = ", args.input)
-  debug_print(".output = ", args.output)
-  debug_print(".loader_file = ", args.loader_file)
-  debug_print(".spi_size (KB) = ", hex(args.spi_size))
-  debug_print(".image_size = ", hex(args.image_size))
-  debug_print(".load_addr", hex(args.load_addr))
-  debug_print(".tag0_loc = ", hex(args.tag0_loc))
-  debug_print(".tag1_loc = ", hex(args.tag1_loc))
-  debug_print(".header_loc = ", hex(args.header_loc))
-  debug_print(".lfw_loc = ", hex(args.lfw_loc))
-  debug_print(".lfw_size = ", hex(args.lfw_size))
-  if args.rw_loc < 0:
-    debug_print(".rw_loc = ", args.rw_loc)
-  else:
-    debug_print(".rw_loc = ", hex(args.rw_loc))
-  debug_print(".spi_clock (MHz) = ", args.spi_clock)
-  debug_print(".spi_read_cmd = ", hex(args.spi_read_cmd))
-  debug_print(".test_spi = ", args.test_spi)
-  debug_print(".test_ecrw = ", args.test_ecrw)
-  debug_print(".verbose = ", args.verbose)
-  debug_print(".spi_drive_str = ", args.spi_drive_str)
-  debug_print(".spi_slew_fast = ", args.spi_slew_fast)
-  debug_print(".spi_cpol = ", args.spi_cpol)
-  debug_print(".spi_cpha_mosi = ", args.spi_cpha_mosi)
-  debug_print(".spi_cpha_miso = ", args.spi_cpha_miso)
+    debug_print("parsed arguments:")
+    debug_print(".input  = ", args.input)
+    debug_print(".output = ", args.output)
+    debug_print(".loader_file = ", args.loader_file)
+    debug_print(".spi_size (KB) = ", hex(args.spi_size))
+    debug_print(".image_size = ", hex(args.image_size))
+    debug_print(".load_addr", hex(args.load_addr))
+    debug_print(".tag0_loc = ", hex(args.tag0_loc))
+    debug_print(".tag1_loc = ", hex(args.tag1_loc))
+    debug_print(".header_loc = ", hex(args.header_loc))
+    debug_print(".lfw_loc = ", hex(args.lfw_loc))
+    debug_print(".lfw_size = ", hex(args.lfw_size))
+    if args.rw_loc < 0:
+        debug_print(".rw_loc = ", args.rw_loc)
+    else:
+        debug_print(".rw_loc = ", hex(args.rw_loc))
+    debug_print(".spi_clock (MHz) = ", args.spi_clock)
+    debug_print(".spi_read_cmd = ", hex(args.spi_read_cmd))
+    debug_print(".test_spi = ", args.test_spi)
+    debug_print(".test_ecrw = ", args.test_ecrw)
+    debug_print(".verbose = ", args.verbose)
+    debug_print(".spi_drive_str = ", args.spi_drive_str)
+    debug_print(".spi_slew_fast = ", args.spi_slew_fast)
+    debug_print(".spi_cpol = ", args.spi_cpol)
+    debug_print(".spi_cpha_mosi = ", args.spi_cpha_mosi)
+    debug_print(".spi_cpha_miso = ", args.spi_cpha_miso)
+
 
 def spi_list_append(mylist, loc, data, description):
-  """Append SPI data block tuple to list"""
-  t = (loc, data, description)
-  mylist.append(t)
-  debug_print("Add SPI entry: offset=0x{0:08x} len=0x{1:0x} descr={2}".format(loc, len(data), description))
+    """Append SPI data block tuple to list"""
+    t = (loc, data, description)
+    mylist.append(t)
+    debug_print(
+        "Add SPI entry: offset=0x{0:08x} len=0x{1:0x} descr={2}".format(
+            loc, len(data), description
+        )
+    )
+
 
 #
 # Handle quiet mode build from Makefile
@@ -652,200 +784,217 @@ def spi_list_append(mylist, loc, data, description):
 #                       || 48 * [0]
 #
 def main():
-  global debug_print
-
-  args = parseargs()
-
-  if args.verbose:
-    debug_print = print
-
-  debug_print("Begin pack_ec_mec172x.py script")
-
-  print_args(args)
-
-  chip_dict = MEC172X_DICT
-
-  # Boot-ROM requires header location aligned >= 256 bytes.
-  # CrOS EC flash image update code requires EC_RO/RW location to be aligned
-  # on a flash erase size boundary and EC_RO/RW size to be a multiple of
-  # the smallest flash erase block size.
-
-  spi_size = args.spi_size * 1024
-  spi_image_size = spi_size // 2
-
-  rorofile=PacklfwRoImage(args.input, args.loader_file, args.image_size)
-  debug_print("Temporary file containing LFW + EC_RO is ", rorofile)
-
-  lfw_ecro = GetPayload(rorofile, chip_dict["PAD_SIZE"])
-  lfw_ecro_len = len(lfw_ecro)
-  debug_print("Padded LFW + EC_RO length = ", hex(lfw_ecro_len))
-
-  # SPI test mode compute CRC32 of EC_RO and store in last 4 bytes
-  if args.test_spi:
-      crc32_ecro = zlib.crc32(bytes(lfw_ecro[LFW_SIZE:-4]))
-      crc32_ecro_bytes = crc32_ecro.to_bytes(4, byteorder='little')
-      lfw_ecro[-4:] = crc32_ecro_bytes
-      debug_print("ecro len = ", hex(len(lfw_ecro) - LFW_SIZE))
-      debug_print("CRC32(ecro-4) = ", hex(crc32_ecro))
-
-  # Reads entry point from offset 4 of file.
-  # This assumes binary has Cortex-M4 vector table at offset 0.
-  # 32-bit word at offset 0x0 initial stack pointer value
-  # 32-bit word at offset 0x4 address of reset handler
-  # NOTE: reset address will have bit[0]=1 to ensure thumb mode.
-  lfw_ecro_entry = GetEntryPoint(rorofile)
-  debug_print("LFW Entry point from GetEntryPoint = 0x{0:08x}".format(lfw_ecro_entry))
-
-  # Chromebooks are not using MEC BootROM SPI header/payload authentication
-  # or payload encryption. In this case the header authentication signature
-  # is filled with the hash digest of the respective entity.
-  # BuildHeader2 computes the hash digest and stores it in the correct
-  # header location.
-  header = BuildHeader2(args, chip_dict, lfw_ecro_len,
-                        args.load_addr, lfw_ecro_entry)
-  printByteArrayAsHex(header, "Header(lfw_ecro)")
-
-  # If payload encryption used then encrypt payload and
-  # generate Payload Key Header. If encryption not used
-  # payload is not modified and the method returns None
-  encryption_key_header = EncryptPayload(args, chip_dict, lfw_ecro)
-  printByteArrayAsHex(encryption_key_header,
-                      "LFW + EC_RO encryption_key_header")
-
-  ec_info_block = GenEcInfoBlock(args, chip_dict)
-  printByteArrayAsHex(ec_info_block, "EC Info Block")
-
-  cosignature = GenCoSignature(args, chip_dict, lfw_ecro)
-  printByteArrayAsHex(cosignature, "LFW + EC_RO cosignature")
-
-  trailer = GenTrailer(args, chip_dict, lfw_ecro, encryption_key_header,
-                       ec_info_block, cosignature)
-
-  printByteArrayAsHex(trailer, "LFW + EC_RO trailer")
-
-  # Build TAG0. Set TAG1=TAG0 Boot-ROM is allowed to load EC-RO only.
-  tag0 = BuildTag(args)
-  tag1 = tag0
-
-  debug_print("Call to GetPayloadFromOffset")
-  debug_print("args.input = ", args.input)
-  debug_print("args.image_size = ", hex(args.image_size))
-
-  ecrw = GetPayloadFromOffset(args.input, args.image_size,
-                              chip_dict["PAD_SIZE"])
-  debug_print("type(ecrw) is ", type(ecrw))
-  debug_print("len(ecrw) is ", hex(len(ecrw)))
+    global debug_print
+
+    args = parseargs()
+
+    if args.verbose:
+        debug_print = print
+
+    debug_print("Begin pack_ec_mec172x.py script")
+
+    print_args(args)
+
+    chip_dict = MEC172X_DICT
+
+    # Boot-ROM requires header location aligned >= 256 bytes.
+    # CrOS EC flash image update code requires EC_RO/RW location to be aligned
+    # on a flash erase size boundary and EC_RO/RW size to be a multiple of
+    # the smallest flash erase block size.
+
+    spi_size = args.spi_size * 1024
+    spi_image_size = spi_size // 2
+
+    rorofile = PacklfwRoImage(args.input, args.loader_file, args.image_size)
+    debug_print("Temporary file containing LFW + EC_RO is ", rorofile)
+
+    lfw_ecro = GetPayload(rorofile, chip_dict)
+    lfw_ecro_len = len(lfw_ecro)
+    debug_print("Padded LFW + EC_RO length = ", hex(lfw_ecro_len))
+
+    # SPI test mode compute CRC32 of EC_RO and store in last 4 bytes
+    if args.test_spi:
+        crc32_ecro = zlib.crc32(bytes(lfw_ecro[args.lfw_size : -4]))
+        crc32_ecro_bytes = crc32_ecro.to_bytes(4, byteorder="little")
+        lfw_ecro[-4:] = crc32_ecro_bytes
+        debug_print("ecro len = ", hex(len(lfw_ecro) - args.lfw_size))
+        debug_print("CRC32(ecro-4) = ", hex(crc32_ecro))
+
+    # Reads entry point from offset 4 of file.
+    # This assumes binary has Cortex-M4 vector table at offset 0.
+    # 32-bit word at offset 0x0 initial stack pointer value
+    # 32-bit word at offset 0x4 address of reset handler
+    # NOTE: reset address will have bit[0]=1 to ensure thumb mode.
+    lfw_ecro_entry = GetEntryPoint(rorofile)
+    debug_print(
+        "LFW Entry point from GetEntryPoint = 0x{0:08x}".format(lfw_ecro_entry)
+    )
+
+    # Chromebooks are not using MEC BootROM SPI header/payload authentication
+    # or payload encryption. In this case the header authentication signature
+    # is filled with the hash digest of the respective entity.
+    # BuildHeader2 computes the hash digest and stores it in the correct
+    # header location.
+    header = BuildHeader2(
+        args, chip_dict, lfw_ecro_len, args.load_addr, lfw_ecro_entry
+    )
+    printByteArrayAsHex(header, "Header(lfw_ecro)")
+
+    ec_info_block = GenEcInfoBlock(args, chip_dict)
+    printByteArrayAsHex(ec_info_block, "EC Info Block")
+
+    cosignature = GenCoSignature(args, chip_dict, lfw_ecro)
+    printByteArrayAsHex(cosignature, "LFW + EC_RO cosignature")
+
+    trailer = GenTrailer(
+        args, chip_dict, lfw_ecro, None, ec_info_block, cosignature
+    )
+
+    printByteArrayAsHex(trailer, "LFW + EC_RO trailer")
+
+    # Build TAG0. Set TAG1=TAG0 Boot-ROM is allowed to load EC-RO only.
+    tag0 = BuildTag(args)
+    tag1 = tag0
+
+    debug_print("Call to GetPayloadFromOffset")
+    debug_print("args.input = ", args.input)
+    debug_print("args.image_size = ", hex(args.image_size))
+
+    ecrw = GetPayloadFromOffset(args.input, args.image_size, chip_dict)
+    debug_print("type(ecrw) is ", type(ecrw))
+    debug_print("len(ecrw) is ", hex(len(ecrw)))
+
+    # truncate to args.image_size
+    ecrw_len = len(ecrw)
+    if ecrw_len > args.image_size:
+        debug_print(
+            "Truncate EC_RW len={0:0x} to image_size={1:0x}".format(
+                ecrw_len, args.image_size
+            )
+        )
+        ecrw = ecrw[: args.image_size]
+        ecrw_len = len(ecrw)
+
+    debug_print("len(EC_RW) = ", hex(ecrw_len))
+
+    # SPI test mode compute CRC32 of EC_RW and store in last 4 bytes
+    if args.test_spi:
+        crc32_ecrw = zlib.crc32(bytes(ecrw[0:-4]))
+        crc32_ecrw_bytes = crc32_ecrw.to_bytes(4, byteorder="little")
+        ecrw[-4:] = crc32_ecrw_bytes
+        debug_print("ecrw len = ", hex(len(ecrw)))
+        debug_print("CRC32(ecrw) = ", hex(crc32_ecrw))
+
+    # Assume FW layout is standard Cortex-M style with vector
+    # table at start of binary.
+    # 32-bit word at offset 0x0 = Initial stack pointer
+    # 32-bit word at offset 0x4 = Address of reset handler
+    ecrw_entry_tuple = struct.unpack_from("<I", ecrw, 4)
+    debug_print("ecrw_entry_tuple[0] = ", hex(ecrw_entry_tuple[0]))
+
+    ecrw_entry = ecrw_entry_tuple[0]
+    debug_print("ecrw_entry = ", hex(ecrw_entry))
+
+    # Note: payload_rw is a bytearray therefore is mutable
+    if args.test_ecrw:
+        gen_test_ecrw(ecrw)
+
+    os.remove(rorofile)  # clean up the temp file
+
+    spi_list = []
+
+    # MEC172x Add TAG's
+    # spi_list.append((args.tag0_loc, tag0, "tag0"))
+    # spi_list.append((args.tag1_loc, tag1, "tag1"))
+    spi_list_append(spi_list, args.tag0_loc, tag0, "TAG0")
+    spi_list_append(spi_list, args.tag1_loc, tag1, "TAG1")
+
+    # Boot-ROM SPI image header for LFW+EC-RO
+    # spi_list.append((args.header_loc, header, "header(lfw + ro)"))
+    spi_list_append(spi_list, args.header_loc, header, "LFW-EC_RO Header")
+
+    spi_list_append(spi_list, args.lfw_loc, lfw_ecro, "LFW-EC_RO FW")
+
+    offset = args.lfw_loc + len(lfw_ecro)
+    debug_print("SPI offset after LFW_ECRO = 0x{0:08x}".format(offset))
 
-  # truncate to args.image_size
-  ecrw_len = len(ecrw)
-  if ecrw_len > args.image_size:
-      debug_print("Truncate EC_RW len={0:0x} to image_size={1:0x}".format(ecrw_len,args.image_size))
-      ecrw = ecrw[:args.image_size]
-      ecrw_len = len(ecrw)
-
-  debug_print("len(EC_RW) = ", hex(ecrw_len))
-
-  # SPI test mode compute CRC32 of EC_RW and store in last 4 bytes
-  if args.test_spi:
-      crc32_ecrw = zlib.crc32(bytes(ecrw[0:-4]))
-      crc32_ecrw_bytes = crc32_ecrw.to_bytes(4, byteorder='little')
-      ecrw[-4:] = crc32_ecrw_bytes
-      debug_print("ecrw len = ", hex(len(ecrw)))
-      debug_print("CRC32(ecrw) = ", hex(crc32_ecrw))
-
-  # Assume FW layout is standard Cortex-M style with vector
-  # table at start of binary.
-  # 32-bit word at offset 0x0 = Initial stack pointer
-  # 32-bit word at offset 0x4 = Address of reset handler
-  ecrw_entry_tuple = struct.unpack_from('<I', ecrw, 4)
-  debug_print("ecrw_entry_tuple[0] = ", hex(ecrw_entry_tuple[0]))
-
-  ecrw_entry = ecrw_entry_tuple[0]
-  debug_print("ecrw_entry = ", hex(ecrw_entry))
-
-  # Note: payload_rw is a bytearray therefore is mutable
-  if args.test_ecrw:
-    gen_test_ecrw(ecrw)
-
-  os.remove(rorofile)           # clean up the temp file
-
-  spi_list = []
-
-  # MEC172x Add TAG's
-  #spi_list.append((args.tag0_loc, tag0, "tag0"))
-  #spi_list.append((args.tag1_loc, tag1, "tag1"))
-  spi_list_append(spi_list, args.tag0_loc, tag0, "TAG0")
-  spi_list_append(spi_list, args.tag1_loc, tag1, "TAG1")
-
-  # Boot-ROM SPI image header for LFW+EC-RO
-  #spi_list.append((args.header_loc, header, "header(lfw + ro)"))
-  spi_list_append(spi_list, args.header_loc, header, "LFW-EC_RO Header")
-
-  spi_list_append(spi_list, args.lfw_loc, lfw_ecro, "LFW-EC_RO FW")
-
-  offset = args.lfw_loc + len(lfw_ecro)
-  debug_print("SPI offset after LFW_ECRO = 0x{0:08x}".format(offset))
-
-  if ec_info_block != None:
-    spi_list_append(spi_list, offset, ec_info_block, "LFW-EC_RO Info Block")
-    offset += len(ec_info_block)
-
-  debug_print("SPI offset after ec_info_block = 0x{0:08x}".format(offset))
-
-  if cosignature != None:
-    #spi_list.append((offset, co-signature, "ECRO Co-signature"))
-    spi_list_append(spi_list, offset, cosignature, "LFW-EC_RO Co-signature")
-    offset += len(cosignature)
-
-  debug_print("SPI offset after co-signature = 0x{0:08x}".format(offset))
-
-  if trailer != None:
-    #spi_list.append((offset, trailer, "ECRO Trailer"))
-    spi_list_append(spi_list, offset, trailer, "LFW-EC_RO trailer")
-    offset += len(trailer)
-
-  debug_print("SPI offset after trailer = 0x{0:08x}".format(offset))
-
-  # EC_RW location
-  rw_offset = int(spi_size // 2)
-  if args.rw_loc >= 0:
-    rw_offset = args.rw_loc
-
-  debug_print("rw_offset = 0x{0:08x}".format(rw_offset))
-
-  #spi_list.append((rw_offset, ecrw, "ecrw"))
-  spi_list_append(spi_list, rw_offset, ecrw, "EC_RW")
-  offset = rw_offset + len(ecrw)
-
-  spi_list = sorted(spi_list)
-
-  debug_print("Display spi_list:")
-  dumpsects(spi_list)
-
-  #
-  # MEC172x Boot-ROM locates TAG0/1 at SPI offset 0
-  # instead of end of SPI.
-  #
-  with open(args.output, 'wb') as f:
-    debug_print("Write spi list to file", args.output)
-    addr = 0
-    for s in spi_list:
-      if addr < s[0]:
-        debug_print("Offset ",hex(addr)," Length", hex(s[0]-addr),
-                "fill with 0xff")
-        f.write(b'\xff' * (s[0] - addr))
-        addr = s[0]
-        debug_print("Offset ",hex(addr), " Length", hex(len(s[1])), "write data")
-
-      f.write(s[1])
-      addr += len(s[1])
-
-    if addr < spi_size:
-      debug_print("Offset ",hex(addr), " Length", hex(spi_size - addr),
-              "fill with 0xff")
-      f.write(b'\xff' * (spi_size - addr))
+    if ec_info_block != None:
+        spi_list_append(spi_list, offset, ec_info_block, "LFW-EC_RO Info Block")
+        offset += len(ec_info_block)
 
-    f.flush()
+    debug_print("SPI offset after ec_info_block = 0x{0:08x}".format(offset))
 
-if __name__ == '__main__':
-  main()
+    if cosignature != None:
+        # spi_list.append((offset, co-signature, "ECRO Co-signature"))
+        spi_list_append(spi_list, offset, cosignature, "LFW-EC_RO Co-signature")
+        offset += len(cosignature)
+
+    debug_print("SPI offset after co-signature = 0x{0:08x}".format(offset))
+
+    if trailer != None:
+        # spi_list.append((offset, trailer, "ECRO Trailer"))
+        spi_list_append(spi_list, offset, trailer, "LFW-EC_RO trailer")
+        offset += len(trailer)
+
+    debug_print("SPI offset after trailer = 0x{0:08x}".format(offset))
+
+    # EC_RW location
+    rw_offset = int(spi_size // 2)
+    if args.rw_loc >= 0:
+        rw_offset = args.rw_loc
+
+    debug_print("rw_offset = 0x{0:08x}".format(rw_offset))
+
+    # spi_list.append((rw_offset, ecrw, "ecrw"))
+    spi_list_append(spi_list, rw_offset, ecrw, "EC_RW")
+    offset = rw_offset + len(ecrw)
+
+    spi_list = sorted(spi_list)
+
+    debug_print("Display spi_list:")
+    dumpsects(spi_list)
+
+    #
+    # MEC172x Boot-ROM locates TAG0/1 at SPI offset 0
+    # instead of end of SPI.
+    #
+    with open(args.output, "wb") as f:
+        debug_print("Write spi list to file", args.output)
+        addr = 0
+        for s in spi_list:
+            if addr < s[0]:
+                debug_print(
+                    "Offset ",
+                    hex(addr),
+                    " Length",
+                    hex(s[0] - addr),
+                    "fill with 0xff",
+                )
+                f.write(b"\xff" * (s[0] - addr))
+                addr = s[0]
+                debug_print(
+                    "Offset ",
+                    hex(addr),
+                    " Length",
+                    hex(len(s[1])),
+                    "write data",
+                )
+
+            f.write(s[1])
+            addr += len(s[1])
+
+        if addr < spi_size:
+            debug_print(
+                "Offset ",
+                hex(addr),
+                " Length",
+                hex(spi_size - addr),
+                "fill with 0xff",
+            )
+            f.write(b"\xff" * (spi_size - addr))
+
+        f.flush()
+
+
+if __name__ == "__main__":
+    main()
diff --git a/chip/mchp/watchdog.c b/chip/mchp/watchdog.c
index b8f986f5cd..0de4398fdb 100644
--- a/chip/mchp/watchdog.c
+++ b/chip/mchp/watchdog.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -43,11 +43,10 @@ static void wdg_intr_enable(int enable)
 #else
 static void wdg_intr_enable(int enable)
 {
-	(void) enable;
+	(void)enable;
 }
 #endif
 
-
 /*
  * MEC1701 WDG asserts chip reset on LOAD count expiration.
  * WDG interrupt is simulated using a 16-bit general purpose
@@ -81,8 +80,8 @@ int watchdog_init(void)
 		MCHP_TMR16_CTL(0) |= BIT(0);
 
 		/* Prescaler = 48000 -> 1kHz -> Period = 1 ms */
-		MCHP_TMR16_CTL(0) = (MCHP_TMR16_CTL(0) & 0xffffU)
-					| (47999 << 16);
+		MCHP_TMR16_CTL(0) = (MCHP_TMR16_CTL(0) & 0xffffU) |
+				    (47999 << 16);
 
 		/* No auto restart */
 		MCHP_TMR16_CTL(0) &= ~BIT(3);
@@ -116,8 +115,8 @@ int watchdog_init(void)
 	 * counting if a debug cable is attached to JTAG_RST#.
 	 */
 	if (IS_ENABLED(CONFIG_CHIPSET_DEBUG))
-		MCHP_WDG_CTL |= (MCHP_WDT_CTL_ENABLE
-			| MCHP_WDT_CTL_JTAG_STALL_EN);
+		MCHP_WDG_CTL |=
+			(MCHP_WDT_CTL_ENABLE | MCHP_WDT_CTL_JTAG_STALL_EN);
 	else
 		MCHP_WDG_CTL |= MCHP_WDT_CTL_ENABLE;
 
@@ -142,32 +141,29 @@ void __keep watchdog_check(uint32_t excep_lr, uint32_t excep_sp)
 	MCHP_WDG_CTL = 0; /* clear enable to allow write to load register */
 	MCHP_WDG_LOAD = 2;
 	MCHP_WDG_CTL |= MCHP_WDT_CTL_ENABLE;
-
 }
 
 /* ISR for watchdog warning naked will keep SP & LR */
-void
-IRQ_HANDLER(MCHP_IRQ_WDG)(void) __keep __attribute__((naked));
+void IRQ_HANDLER(MCHP_IRQ_WDG)(void) __keep __attribute__((naked));
 void IRQ_HANDLER(MCHP_IRQ_WDG)(void)
 {
 	/* Naked call so we can extract raw LR and SP */
 	asm volatile("mov r0, lr\n"
-			"mov r1, sp\n"
-			/*
-			 * Must push registers in pairs to keep 64-bit aligned
-			 * stack for ARM EABI.  This also conveniently saves
-			 * R0=LR so we can pass it to task_resched_if_needed.
-			 */
-			"push {r0, lr}\n"
-			"bl watchdog_check\n"
-			"pop {r0, lr}\n"
-			"b task_resched_if_needed\n");
+		     "mov r1, sp\n"
+		     /*
+		      * Must push registers in pairs to keep 64-bit aligned
+		      * stack for ARM EABI.  This also conveniently saves
+		      * R0=LR so we can pass it to task_resched_if_needed.
+		      */
+		     "push {r0, lr}\n"
+		     "bl watchdog_check\n"
+		     "pop {r0, lr}\n"
+		     "b task_resched_if_needed\n");
 }
 
 /* put the watchdog at the highest priority */
 const struct irq_priority __keep IRQ_PRIORITY(MCHP_IRQ_WDG)
-__attribute__((section(".rodata.irqprio")))
-= {MCHP_IRQ_WDG, 0};
+	__attribute__((section(".rodata.irqprio"))) = { MCHP_IRQ_WDG, 0 };
 
 #else
 /*
@@ -185,8 +181,7 @@ void __keep watchdog_check(uint32_t excep_lr, uint32_t excep_sp)
 	watchdog_trace(excep_lr, excep_sp);
 }
 
-void
-IRQ_HANDLER(MCHP_IRQ_TIMER16_0)(void) __keep __attribute__((naked));
+void IRQ_HANDLER(MCHP_IRQ_TIMER16_0)(void) __keep __attribute__((naked));
 void IRQ_HANDLER(MCHP_IRQ_TIMER16_0)(void)
 {
 	/* Naked call so we can extract raw LR and SP */
@@ -205,8 +200,7 @@ void IRQ_HANDLER(MCHP_IRQ_TIMER16_0)(void)
 
 /* Put the watchdog at the highest interrupt priority. */
 const struct irq_priority __keep IRQ_PRIORITY(MCHP_IRQ_TIMER16_0)
-	__attribute__((section(".rodata.irqprio")))
-		= {MCHP_IRQ_TIMER16_0, 0};
+	__attribute__((section(".rodata.irqprio"))) = { MCHP_IRQ_TIMER16_0, 0 };
 
 #endif /* #ifdef CONFIG_WATCHDOG_HELP */
 #endif /* #if defined(CHIP_FAMILY_MEC152X) || defined(CHIP_FAMILY_MEC172X) */
diff --git a/chip/mec1322/adc.c b/chip/mec1322/adc.c
index 9c83173777..8f5df03ee1 100644
--- a/chip/mec1322/adc.c
+++ b/chip/mec1322/adc.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -48,7 +48,8 @@ int adc_read_channel(enum adc_channel ch)
 
 	if (start_single_and_wait(ADC_SINGLE_READ_TIME))
 		value = MEC1322_ADC_READ(adc->channel) * adc->factor_mul /
-			adc->factor_div + adc->shift;
+				adc->factor_div +
+			adc->shift;
 	else
 		value = ADC_READ_ERROR;
 
diff --git a/chip/mec1322/adc_chip.h b/chip/mec1322/adc_chip.h
index a6425d6872..d8ade540a8 100644
--- a/chip/mec1322/adc_chip.h
+++ b/chip/mec1322/adc_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/mec1322/build.mk b/chip/mec1322/build.mk
index 7dadf60c88..7fa324fea1 100644
--- a/chip/mec1322/build.mk
+++ b/chip/mec1322/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
+# Copyright 2013 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/chip/mec1322/clock.c b/chip/mec1322/clock.c
index ce07284891..c9fc68d58a 100644
--- a/chip/mec1322/clock.c
+++ b/chip/mec1322/clock.c
@@ -1,10 +1,11 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Clocks and power management settings */
 
+#include "builtin/assert.h"
 #include "clock.h"
 #include "common.h"
 #include "console.h"
@@ -24,13 +25,13 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args)
 
 #ifdef CONFIG_LOW_POWER_IDLE
 /* Recovery time for HvySlp2 is 0 usec */
-#define HEAVY_SLEEP_RECOVER_TIME_USEC   75
+#define HEAVY_SLEEP_RECOVER_TIME_USEC 75
 
-#define SET_HTIMER_DELAY_USEC           200
+#define SET_HTIMER_DELAY_USEC 200
 
 static int idle_sleep_cnt;
 static int idle_dsleep_cnt;
@@ -40,7 +41,7 @@ static uint64_t total_idle_dsleep_time_us;
  * Fixed amount of time to keep the console in use flag true after boot in
  * order to give a permanent window in which the heavy sleep mode is not used.
  */
-#define CONSOLE_IN_USE_ON_BOOT_TIME (15*SECOND)
+#define CONSOLE_IN_USE_ON_BOOT_TIME (15 * SECOND)
 static int console_in_use_timeout_sec = 60;
 static timestamp_t console_expire_time;
 #endif /*CONFIG_LOW_POWER_IDLE */
@@ -50,7 +51,8 @@ static int freq = 48000000;
 void clock_wait_cycles(uint32_t cycles)
 {
 	asm volatile("1: subs %0, #1\n"
-		     "   bne 1b\n" : "+r"(cycles));
+		     "   bne 1b\n"
+		     : "+r"(cycles));
 }
 
 int clock_get_freq(void)
@@ -104,8 +106,8 @@ DECLARE_HOOK(HOOK_INIT, clock_turbo_disable, HOOK_PRIO_INIT_VBOOT_HASH + 1);
 static void htimer_init(void)
 {
 	MEC1322_INT_BLK_EN |= BIT(17);
-	MEC1322_INT_ENABLE(17) |= BIT(20);  /* GIRQ=17, aggregator bit = 20 */
-	MEC1322_HTIMER_PRELOAD = 0;  /* disable at beginning */
+	MEC1322_INT_ENABLE(17) |= BIT(20); /* GIRQ=17, aggregator bit = 20 */
+	MEC1322_HTIMER_PRELOAD = 0; /* disable at beginning */
 
 	task_enable_irq(MEC1322_IRQ_HTIMER);
 }
@@ -120,7 +122,6 @@ static void htimer_init(void)
 static void system_set_htimer_alarm(uint32_t seconds, uint32_t microseconds)
 {
 	if (seconds || microseconds) {
-
 		if (seconds > 2) {
 			/* count from 2 sec to 2 hrs, mec1322 sec 18.10.2 */
 			ASSERT(seconds <= 0xffff / 8);
@@ -154,19 +155,18 @@ static timestamp_t system_get_htimer(void)
 	uint16_t count;
 	timestamp_t time;
 
-	count =  MEC1322_HTIMER_COUNT;
-
+	count = MEC1322_HTIMER_COUNT;
 
 	if (MEC1322_HTIMER_CONTROL == 1) /* if > 2 sec */
 		/* 0.125 sec per count */
 		time.le.lo = (uint32_t)(count * 125000);
-	else    /* if < 2 sec */
+	else /* if < 2 sec */
 		/* 30.5(=61/2)usec per count */
 		time.le.lo = (uint32_t)(count * 61 / 2);
 
 	time.le.hi = 0;
 
-	return time;  /* in uSec */
+	return time; /* in uSec */
 }
 
 /**
@@ -220,7 +220,7 @@ static void prepare_for_deep_sleep(void)
 	MEC1322_LPC_ACT = 0x0;
 #endif
 
-	MEC1322_PCR_SYS_SLP_CTL = 0x2;  /* heavysleep 2 */
+	MEC1322_PCR_SYS_SLP_CTL = 0x2; /* heavysleep 2 */
 
 	CPU_NVIC_ST_CTRL &= ~ST_TICKINT; /* SYS_TICK_INT_DISABLE */
 }
@@ -248,7 +248,7 @@ static void resume_from_deep_sleep(void)
 	MEC1322_PCR_HOST_SLP_EN &= MEC1322_PCR_HOST_SLP_EN_WAKE;
 	MEC1322_PCR_EC_SLP_EN2 &= MEC1322_PCR_EC_SLP_EN2_WAKE;
 
-	MEC1322_PCR_SYS_SLP_CTL = 0xF8;  /* default */
+	MEC1322_PCR_SYS_SLP_CTL = 0xF8; /* default */
 
 #ifndef CONFIG_POWER_S0IX
 	/* Enable LPC */
@@ -256,7 +256,6 @@ static void resume_from_deep_sleep(void)
 #endif
 }
 
-
 void clock_refresh_console_in_use(void)
 {
 	disable_sleep(SLEEP_MASK_CONSOLE);
@@ -284,7 +283,6 @@ void __idle(void)
 	disable_sleep(SLEEP_MASK_CONSOLE);
 	console_expire_time.val = get_time().val + CONSOLE_IN_USE_ON_BOOT_TIME;
 
-
 	/*
 	 * Print when the idle task starts.  This is the lowest priority task,
 	 * so this only starts once all other tasks have gotten a chance to do
@@ -296,7 +294,7 @@ void __idle(void)
 		/* Disable interrupts */
 		interrupt_disable();
 
-		t0 = get_time();  /* uSec */
+		t0 = get_time(); /* uSec */
 
 		/* __hw_clock_event_get() is next programmed timer event */
 		next_delay = __hw_clock_event_get() - t0.le.lo;
@@ -308,14 +306,12 @@ void __idle(void)
 
 		/* check if there enough time for deep sleep */
 		if (DEEP_SLEEP_ALLOWED && time_for_dsleep) {
-
-
 			/*
 			 * Check if the console use has expired and console
 			 * sleep is masked by GPIO(UART-RX) interrupt.
 			 */
 			if ((sleep_mask & SLEEP_MASK_CONSOLE) &&
-					t0.val > console_expire_time.val) {
+			    t0.val > console_expire_time.val) {
 				/* allow console to sleep. */
 				enable_sleep(SLEEP_MASK_CONSOLE);
 
@@ -330,11 +326,10 @@ void __idle(void)
 					CPRINTS("Disable console in deepsleep");
 			}
 
-
 			/* UART is not being used  */
-			uart_ready_for_deepsleep = LOW_SPEED_DEEP_SLEEP_ALLOWED
-						&& !uart_tx_in_progress()
-						&& uart_buffer_empty();
+			uart_ready_for_deepsleep =
+				LOW_SPEED_DEEP_SLEEP_ALLOWED &&
+				!uart_tx_in_progress() && uart_buffer_empty();
 
 			/*
 			 * Since MEC1322's heavysleep modes requires all block
@@ -342,7 +337,6 @@ void __idle(void)
 			 * decision factor of heavysleep of EC.
 			 */
 			if (uart_ready_for_deepsleep) {
-
 				idle_dsleep_cnt++;
 
 				/*
@@ -369,10 +363,9 @@ void __idle(void)
 			}
 
 			/* Wait for interrupt: goes into deep sleep. */
-			asm("wfi");
+			cpu_enter_suspend_mode();
 
 			if (uart_ready_for_deepsleep) {
-
 				resume_from_deep_sleep();
 
 				/*
@@ -390,8 +383,8 @@ void __idle(void)
 				/* disable/clear htimer wakeup interrupt */
 				system_reset_htimer_alarm();
 
-				t1.val = t0.val +
-				       (uint64_t)(max_sleep_time - ht_t1.le.lo);
+				t1.val = t0.val + (uint64_t)(max_sleep_time -
+							     ht_t1.le.lo);
 
 				force_time(t1);
 
@@ -400,15 +393,13 @@ void __idle(void)
 
 				/* Record time spent in deep sleep. */
 				total_idle_dsleep_time_us +=
-				       (uint64_t)(max_sleep_time - ht_t1.le.lo);
+					(uint64_t)(max_sleep_time -
+						   ht_t1.le.lo);
 			}
 
 		} else { /* CPU 'Sleep' mode */
-
 			idle_sleep_cnt++;
-
-			asm("wfi");
-
+			cpu_enter_suspend_mode();
 		}
 
 		interrupt_enable();
@@ -419,7 +410,7 @@ void __idle(void)
 /**
  * Print low power idle statistics
  */
-static int command_idle_stats(int argc, char **argv)
+static int command_idle_stats(int argc, const char **argv)
 {
 	timestamp_t ts = get_time();
 
@@ -427,19 +418,18 @@ static int command_idle_stats(int argc, char **argv)
 	ccprintf("Num idle calls that deep-sleep:      %d\n", idle_dsleep_cnt);
 
 	ccprintf("Total Time spent in deep-sleep(sec): %.6lld(s)\n",
-						total_idle_dsleep_time_us);
+		 total_idle_dsleep_time_us);
 	ccprintf("Total time on:                       %.6llds\n\n", ts.val);
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats,
-			"",
+DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, "",
 			"Print last idle stats");
 #endif /* defined(CONFIG_CMD_IDLE_STATS) */
 
 /**
  * Configure deep sleep clock settings.
  */
-static int command_dsleep(int argc, char **argv)
+static int command_dsleep(int argc, const char **argv)
 {
 	int v;
 
@@ -449,9 +439,9 @@ static int command_dsleep(int argc, char **argv)
 			 * Force deep sleep not to use heavy sleep mode or
 			 * allow it to use the heavy sleep mode.
 			 */
-			if (v)  /* 'on' */
+			if (v) /* 'on' */
 				disable_sleep(SLEEP_MASK_FORCE_NO_LOW_SPEED);
-			else    /* 'off' */
+			else /* 'off' */
 				enable_sleep(SLEEP_MASK_FORCE_NO_LOW_SPEED);
 		} else {
 			/* Set console in use timeout. */
@@ -469,12 +459,11 @@ static int command_dsleep(int argc, char **argv)
 
 	ccprintf("Sleep mask: %08x\n", sleep_mask);
 	ccprintf("Console in use timeout:   %d sec\n",
-			console_in_use_timeout_sec);
+		 console_in_use_timeout_sec);
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(dsleep, command_dsleep,
-			"[ on | off | <timeout> sec]",
+DECLARE_CONSOLE_COMMAND(dsleep, command_dsleep, "[ on | off | <timeout> sec]",
 			"Deep sleep clock settings:\nUse 'on' to force deep "
 			"sleep NOT to enter heavysleep mode.\nUse 'off' to "
 			"allow deep sleep to use heavysleep whenever conditions"
diff --git a/chip/mec1322/config_chip.h b/chip/mec1322/config_chip.h
index 951de3fb4f..027109cded 100644
--- a/chip/mec1322/config_chip.h
+++ b/chip/mec1322/config_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,15 +10,15 @@
 #include "core/cortex-m/config_core.h"
 
 /* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT	93
+#define CONFIG_IRQ_COUNT 93
 
 /* Use a bigger console output buffer */
 #undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE	2048
+#define CONFIG_UART_TX_BUF_SIZE 2048
 
 /* Interval between HOOK_TICK notifications */
-#define HOOK_TICK_INTERVAL_MS	250
-#define HOOK_TICK_INTERVAL	(HOOK_TICK_INTERVAL_MS * MSEC)
+#define HOOK_TICK_INTERVAL_MS 250
+#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC)
 
 /*
  * Number of I2C controllers. Controller 0 has 2 ports, so the chip has one
@@ -26,8 +26,8 @@
  */
 #define CONFIG_I2C_MULTI_PORT_CONTROLLER
 
-#define I2C_CONTROLLER_COUNT	4
-#define I2C_PORT_COUNT		5
+#define I2C_CONTROLLER_COUNT 4
+#define I2C_PORT_COUNT 5
 
 /****************************************************************************/
 /* Memory mapping */
@@ -45,52 +45,51 @@
 /****************************************************************************/
 /* Define our RAM layout. */
 
-#define CONFIG_MEC_SRAM_BASE_START	0x00100000
-#define CONFIG_MEC_SRAM_BASE_END	0x00120000
-#define CONFIG_MEC_SRAM_SIZE		(CONFIG_MEC_SRAM_BASE_END - \
-					CONFIG_MEC_SRAM_BASE_START)
+#define CONFIG_MEC_SRAM_BASE_START 0x00100000
+#define CONFIG_MEC_SRAM_BASE_END 0x00120000
+#define CONFIG_MEC_SRAM_SIZE \
+	(CONFIG_MEC_SRAM_BASE_END - CONFIG_MEC_SRAM_BASE_START)
 
 /* 20k RAM for RO / RW / loader */
-#define CONFIG_RAM_SIZE			0x00005000
-#define CONFIG_RAM_BASE			(CONFIG_MEC_SRAM_BASE_END - \
-					CONFIG_RAM_SIZE)
+#define CONFIG_RAM_SIZE 0x00005000
+#define CONFIG_RAM_BASE (CONFIG_MEC_SRAM_BASE_END - CONFIG_RAM_SIZE)
 
 /* System stack size */
-#define CONFIG_STACK_SIZE		1024
+#define CONFIG_STACK_SIZE 1024
 
 /* non-standard task stack sizes */
-#define IDLE_TASK_STACK_SIZE		512
-#define LARGER_TASK_STACK_SIZE		640
+#define IDLE_TASK_STACK_SIZE 512
+#define LARGER_TASK_STACK_SIZE 640
 
-#define CHARGER_TASK_STACK_SIZE		640
-#define HOOKS_TASK_STACK_SIZE		640
-#define CONSOLE_TASK_STACK_SIZE		640
-#define HOST_CMD_TASK_STACK_SIZE	640
+#define CHARGER_TASK_STACK_SIZE 640
+#define HOOKS_TASK_STACK_SIZE 640
+#define CONSOLE_TASK_STACK_SIZE 640
+#define HOST_CMD_TASK_STACK_SIZE 640
 
 /*
  * TODO: Large stack consumption
  * https://code.google.com/p/chrome-os-partner/issues/detail?id=49245
  */
-#define PD_TASK_STACK_SIZE		800
+#define PD_TASK_STACK_SIZE 800
 
 /* Default task stack size */
-#define TASK_STACK_SIZE			512
+#define TASK_STACK_SIZE 512
 
 /****************************************************************************/
 /* Define our flash layout. */
 
 /* Protect bank size 4K bytes */
-#define CONFIG_FLASH_BANK_SIZE		0x00001000
+#define CONFIG_FLASH_BANK_SIZE 0x00001000
 /* Sector erase size 4K bytes */
-#define CONFIG_FLASH_ERASE_SIZE		0x00001000
+#define CONFIG_FLASH_ERASE_SIZE 0x00001000
 /* Minimum write size */
-#define CONFIG_FLASH_WRITE_SIZE		0x00000004
+#define CONFIG_FLASH_WRITE_SIZE 0x00000004
 
 /* One page size for write */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE	256
+#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256
 
 /* Program memory base address */
-#define CONFIG_PROGRAM_MEMORY_BASE	0x00100000
+#define CONFIG_PROGRAM_MEMORY_BASE 0x00100000
 
 #include "config_flash_layout.h"
 
@@ -110,4 +109,4 @@
 #define GPIO_PIN(index) (index / 10), (1 << (index % 10))
 #define GPIO_PIN_MASK(p, m) .port = (p), .mask = (m)
 
-#endif  /* __CROS_EC_CONFIG_CHIP_H */
+#endif /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/chip/mec1322/config_flash_layout.h b/chip/mec1322/config_flash_layout.h
index a5b064b8cc..3ab03325aa 100644
--- a/chip/mec1322/config_flash_layout.h
+++ b/chip/mec1322/config_flash_layout.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,51 +16,49 @@
 
 /* Non-memmapped, external SPI */
 #define CONFIG_EXTERNAL_STORAGE
-#undef  CONFIG_MAPPED_STORAGE
-#undef  CONFIG_FLASH_PSTATE
+#undef CONFIG_MAPPED_STORAGE
+#undef CONFIG_FLASH_PSTATE
 #define CONFIG_SPI_FLASH
 
 /* EC region of SPI resides at end of ROM, protected region follows writable */
-#define CONFIG_EC_PROTECTED_STORAGE_OFF  (CONFIG_FLASH_SIZE_BYTES - 0x20000)
+#define CONFIG_EC_PROTECTED_STORAGE_OFF (CONFIG_FLASH_SIZE_BYTES - 0x20000)
 #define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x20000
-#define CONFIG_EC_WRITABLE_STORAGE_OFF   (CONFIG_FLASH_SIZE_BYTES - 0x40000)
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE  0x20000
+#define CONFIG_EC_WRITABLE_STORAGE_OFF (CONFIG_FLASH_SIZE_BYTES - 0x40000)
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x20000
 
 /* Loader resides at the beginning of program memory */
-#define CONFIG_LOADER_MEM_OFF		0
-#define CONFIG_LOADER_SIZE		0xC00
+#define CONFIG_LOADER_MEM_OFF 0
+#define CONFIG_LOADER_SIZE 0xC00
 
 /* Write protect Loader and RO Image */
-#define CONFIG_WP_STORAGE_OFF		CONFIG_EC_PROTECTED_STORAGE_OFF
+#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
 /*
  * Write protect 128k section of 256k physical flash which contains loader
  * and RO Images.
  */
-#define CONFIG_WP_STORAGE_SIZE		CONFIG_EC_PROTECTED_STORAGE_SIZE
+#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
 
 /*
  * RO / RW images follow the loader in program memory. Either RO or RW
  * image will be loaded -- both cannot be loaded at the same time.
  */
-#define CONFIG_RO_MEM_OFF		(CONFIG_LOADER_MEM_OFF + \
-					CONFIG_LOADER_SIZE)
-#define CONFIG_RO_SIZE			(97 * 1024)
-#define CONFIG_RW_MEM_OFF		CONFIG_RO_MEM_OFF
-#define CONFIG_RW_SIZE			CONFIG_RO_SIZE
+#define CONFIG_RO_MEM_OFF (CONFIG_LOADER_MEM_OFF + CONFIG_LOADER_SIZE)
+#define CONFIG_RO_SIZE (97 * 1024)
+#define CONFIG_RW_MEM_OFF CONFIG_RO_MEM_OFF
+#define CONFIG_RW_SIZE CONFIG_RO_SIZE
 
 /* WP region consists of second half of SPI, and begins with the boot header */
-#define CONFIG_BOOT_HEADER_STORAGE_OFF	0
-#define CONFIG_BOOT_HEADER_STORAGE_SIZE	0x240
+#define CONFIG_BOOT_HEADER_STORAGE_OFF 0
+#define CONFIG_BOOT_HEADER_STORAGE_SIZE 0x240
 
 /* Loader / lfw image immediately follows the boot header on SPI */
-#define CONFIG_LOADER_STORAGE_OFF	(CONFIG_BOOT_HEADER_STORAGE_OFF + \
-					CONFIG_BOOT_HEADER_STORAGE_SIZE)
+#define CONFIG_LOADER_STORAGE_OFF \
+	(CONFIG_BOOT_HEADER_STORAGE_OFF + CONFIG_BOOT_HEADER_STORAGE_SIZE)
 
 /* RO image immediately follows the loader image */
-#define CONFIG_RO_STORAGE_OFF		(CONFIG_LOADER_STORAGE_OFF + \
-					CONFIG_LOADER_SIZE)
+#define CONFIG_RO_STORAGE_OFF (CONFIG_LOADER_STORAGE_OFF + CONFIG_LOADER_SIZE)
 
 /* RW image starts at the beginning of SPI */
-#define CONFIG_RW_STORAGE_OFF		0
+#define CONFIG_RW_STORAGE_OFF 0
 
 #endif /* __CROS_EC_CONFIG_FLASH_LAYOUT_H */
diff --git a/chip/mec1322/dma.c b/chip/mec1322/dma.c
index a6c6fed5ad..20ab3cf9ef 100644
--- a/chip/mec1322/dma.c
+++ b/chip/mec1322/dma.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,7 +14,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_DMA, outstr)
-#define CPRINTS(format, args...) cprints(CC_DMA, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_DMA, format, ##args)
 
 mec1322_dma_chan_t *dma_get_channel(enum dma_channel channel)
 {
@@ -65,7 +65,7 @@ void dma_disable_all(void)
  *				MEC1322_DMA_INC_MEM for rx
  */
 static void prepare_channel(mec1322_dma_chan_t *chan, unsigned count,
-		void *periph, void *memory, unsigned flags)
+			    void *periph, void *memory, unsigned flags)
 {
 	int xfer_size = (flags >> 20) & 0x7;
 
@@ -99,11 +99,11 @@ void dma_prepare_tx(const struct dma_option *option, unsigned count,
 	 */
 	prepare_channel(chan, count, option->periph, (void *)memory,
 			MEC1322_DMA_INC_MEM | MEC1322_DMA_TO_DEV |
-			MEC1322_DMA_DEV(option->channel) | option->flags);
+				MEC1322_DMA_DEV(option->channel) |
+				option->flags);
 }
 
-void dma_start_rx(const struct dma_option *option, unsigned count,
-		  void *memory)
+void dma_start_rx(const struct dma_option *option, unsigned count, void *memory)
 {
 	mec1322_dma_chan_t *chan;
 
@@ -111,7 +111,7 @@ void dma_start_rx(const struct dma_option *option, unsigned count,
 
 	prepare_channel(chan, count, option->periph, memory,
 			MEC1322_DMA_INC_MEM | MEC1322_DMA_DEV(option->channel) |
-			option->flags);
+				option->flags);
 	dma_go(chan);
 }
 
diff --git a/chip/mec1322/fan.c b/chip/mec1322/fan.c
index 1f54389fc7..543a9b8ca6 100644
--- a/chip/mec1322/fan.c
+++ b/chip/mec1322/fan.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -31,7 +31,6 @@ static int rpm_setting;
 static int duty_setting;
 static int in_rpm_mode = 1;
 
-
 static void clear_status(void)
 {
 	/* Clear DRIVE_FAIL, FAN_SPIN, and FAN_STALL bits */
diff --git a/chip/mec1322/flash.c b/chip/mec1322/flash.c
index fac5b08d8f..4b5b622389 100644
--- a/chip/mec1322/flash.c
+++ b/chip/mec1322/flash.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -51,7 +51,7 @@ int crec_flash_physical_read(int offset, int size, char *data)
 int crec_flash_physical_write(int offset, int size, const char *data)
 {
 	int ret = EC_SUCCESS;
-	int  i, write_size;
+	int i, write_size;
 
 	if (entire_flash_locked)
 		return EC_ERROR_ACCESS_DENIED;
@@ -62,8 +62,7 @@ int crec_flash_physical_write(int offset, int size, const char *data)
 
 	for (i = 0; i < size; i += write_size) {
 		write_size = MIN((size - i), SPI_FLASH_MAX_WRITE_SIZE);
-		ret = spi_flash_write(offset + i,
-				      write_size,
+		ret = spi_flash_write(offset + i, write_size,
 				      (uint8_t *)data + i);
 		if (ret != EC_SUCCESS)
 			break;
@@ -99,7 +98,7 @@ int crec_flash_physical_erase(int offset, int size)
 int crec_flash_physical_get_protect(int bank)
 {
 	return spi_flash_check_protect(bank * CONFIG_FLASH_BANK_SIZE,
-			CONFIG_FLASH_BANK_SIZE);
+				       CONFIG_FLASH_BANK_SIZE);
 }
 
 /**
@@ -153,8 +152,7 @@ uint32_t crec_flash_physical_get_protect_flags(void)
  */
 uint32_t crec_flash_physical_get_valid_flags(void)
 {
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-	       EC_FLASH_PROTECT_RO_NOW |
+	return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW |
 	       EC_FLASH_PROTECT_ALL_NOW;
 }
 
@@ -171,8 +169,9 @@ uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
 
 	wp_status = spi_flash_check_wp();
 
-	if (wp_status == SPI_WP_NONE || (wp_status == SPI_WP_HARDWARE &&
-	   !(cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED)))
+	if (wp_status == SPI_WP_NONE ||
+	    (wp_status == SPI_WP_HARDWARE &&
+	     !(cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED)))
 		ret = EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW;
 
 	if (!entire_flash_locked)
@@ -243,7 +242,7 @@ int crec_flash_physical_restore_state(void)
 	 */
 	if (reset_flags & EC_RESET_FLAG_SYSJUMP) {
 		prev = (const struct flash_wp_state *)system_get_jump_tag(
-				FLASH_SYSJUMP_TAG, &version, &size);
+			FLASH_SYSJUMP_TAG, &version, &size);
 		if (prev && version == FLASH_HOOK_VERSION &&
 		    size == sizeof(*prev))
 			entire_flash_locked = prev->entire_flash_locked;
diff --git a/chip/mec1322/gpio.c b/chip/mec1322/gpio.c
index 6435f4fe9d..09b0895376 100644
--- a/chip/mec1322/gpio.c
+++ b/chip/mec1322/gpio.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,16 +21,14 @@ struct gpio_int_mapping {
 
 /* Mapping from GPIO port to GIRQ info */
 static const struct gpio_int_mapping int_map[22] = {
-	{11, 0}, {11, 0}, {11, 0}, {11, 0},
-	{10, 4}, {10, 4}, {10, 4}, {-1, -1},
-	{-1, -1}, {-1, -1}, {9, 10}, {9, 10},
-	{9, 10}, {9, 10}, {8, 14}, {8, 14},
-	{8, 14}, {-1, -1}, {-1, -1}, {-1, -1},
-	{20, 20}, {20, 20}
+	{ 11, 0 },  { 11, 0 },	{ 11, 0 },  { 11, 0 },	{ 10, 4 }, { 10, 4 },
+	{ 10, 4 },  { -1, -1 }, { -1, -1 }, { -1, -1 }, { 9, 10 }, { 9, 10 },
+	{ 9, 10 },  { 9, 10 },	{ 8, 14 },  { 8, 14 },	{ 8, 14 }, { -1, -1 },
+	{ -1, -1 }, { -1, -1 }, { 20, 20 }, { 20, 20 }
 };
 
 void gpio_set_alternate_function(uint32_t port, uint32_t mask,
-				enum gpio_alternate_func func)
+				 enum gpio_alternate_func func)
 {
 	int i;
 	uint32_t val;
@@ -199,7 +197,6 @@ void gpio_pre_init(void)
 	int is_warm = system_is_reboot_warm();
 	const struct gpio_info *g = gpio_list;
 
-
 	for (i = 0; i < GPIO_COUNT; i++, g++) {
 		flags = g->flags;
 
@@ -217,15 +214,15 @@ void gpio_pre_init(void)
 
 		/* Use as GPIO, not alternate function */
 		gpio_set_alternate_function(g->port, g->mask,
-					GPIO_ALT_FUNC_NONE);
+					    GPIO_ALT_FUNC_NONE);
 	}
 }
 
 /* Clear any interrupt flags before enabling GPIO interrupt */
-#define ENABLE_GPIO_GIRQ(x) \
-	do { \
+#define ENABLE_GPIO_GIRQ(x)                                     \
+	do {                                                    \
 		MEC1322_INT_SOURCE(x) |= MEC1322_INT_RESULT(x); \
-		task_enable_irq(MEC1322_IRQ_GIRQ ## x); \
+		task_enable_irq(MEC1322_IRQ_GIRQ##x);           \
 	} while (0)
 
 static void gpio_init(void)
@@ -241,7 +238,6 @@ DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
 /*****************************************************************************/
 /* Interrupt handlers */
 
-
 /**
  * Handler for each GIRQ interrupt. This reads and clears the interrupt bits for
  * the GIRQ interrupt, then finds and calls the corresponding GPIO interrupt
diff --git a/chip/mec1322/hwtimer.c b/chip/mec1322/hwtimer.c
index b0405ec321..7f2d643d98 100644
--- a/chip/mec1322/hwtimer.c
+++ b/chip/mec1322/hwtimer.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,8 +15,7 @@
 
 void __hw_clock_event_set(uint32_t deadline)
 {
-	MEC1322_TMR32_CNT(1) = MEC1322_TMR32_CNT(0) -
-			       (0xffffffff - deadline);
+	MEC1322_TMR32_CNT(1) = MEC1322_TMR32_CNT(0) - (0xffffffff - deadline);
 	MEC1322_TMR32_CTL(1) |= BIT(5);
 }
 
@@ -50,9 +49,15 @@ static void __hw_clock_source_irq(int timer_id)
 	process_timers(timer_id == 0);
 }
 
-static void __hw_clock_source_irq_0(void) { __hw_clock_source_irq(0); }
+static void __hw_clock_source_irq_0(void)
+{
+	__hw_clock_source_irq(0);
+}
 DECLARE_IRQ(MEC1322_IRQ_TIMER32_0, __hw_clock_source_irq_0, 1);
-static void __hw_clock_source_irq_1(void) { __hw_clock_source_irq(1); }
+static void __hw_clock_source_irq_1(void)
+{
+	__hw_clock_source_irq(1);
+}
 DECLARE_IRQ(MEC1322_IRQ_TIMER32_1, __hw_clock_source_irq_1, 1);
 
 static void configure_timer(int timer_id)
diff --git a/chip/mec1322/i2c.c b/chip/mec1322/i2c.c
index c282714265..5068aff978 100644
--- a/chip/mec1322/i2c.c
+++ b/chip/mec1322/i2c.c
@@ -1,10 +1,11 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* I2C port module for MEC1322 */
 
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
 #include "gpio.h"
@@ -16,7 +17,7 @@
 #include "util.h"
 
 #define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
 
 #define I2C_CLOCK 16000000 /* 16 MHz */
 
@@ -36,7 +37,7 @@
 #define CTRL_PIN BIT(7) /* Pending interrupt not */
 
 /* Completion */
-#define COMP_IDLE BIT(29)    /* i2c bus is idle */
+#define COMP_IDLE BIT(29) /* i2c bus is idle */
 #define COMP_RW_BITS_MASK 0x3C /* R/W bits mask */
 
 /* Maximum transfer of a SMBUS block transfer */
@@ -68,10 +69,8 @@ static struct {
 
 /* Map port number to port name in datasheet, for debug prints. */
 static const char *i2c_port_names[MEC1322_I2C_PORT_COUNT] = {
-	[MEC1322_I2C0_0] = "0_0",
-	[MEC1322_I2C0_1] = "0_1",
-	[MEC1322_I2C1] = "1",
-	[MEC1322_I2C2] = "2",
+	[MEC1322_I2C0_0] = "0_0", [MEC1322_I2C0_1] = "0_1",
+	[MEC1322_I2C1] = "1",	  [MEC1322_I2C2] = "2",
 	[MEC1322_I2C3] = "3",
 };
 
@@ -114,8 +113,8 @@ static void configure_controller(int controller, int kbps)
 	MEC1322_I2C_CTRL(controller) = CTRL_PIN;
 	MEC1322_I2C_OWN_ADDR(controller) = 0x0;
 	configure_controller_speed(controller, kbps);
-	MEC1322_I2C_CTRL(controller) = CTRL_PIN | CTRL_ESO |
-				       CTRL_ACK | CTRL_ENI;
+	MEC1322_I2C_CTRL(controller) = CTRL_PIN | CTRL_ESO | CTRL_ACK |
+				       CTRL_ENI;
 	MEC1322_I2C_CONFIG(controller) |= BIT(10); /* ENAB */
 
 	/* Enable interrupt */
@@ -211,16 +210,15 @@ static void select_port(int port)
 
 	MEC1322_I2C_CONFIG(controller) &= ~0xf;
 	MEC1322_I2C_CONFIG(controller) |= port_sel;
-
 }
 
 static inline int get_line_level(int controller)
 {
 	int ret, ctrl;
 	/*
-	* We need to enable BB (Bit Bang) mode in order to read line level
-	* properly, othervise line levels return always idle (0x60).
-	*/
+	 * We need to enable BB (Bit Bang) mode in order to read line level
+	 * properly, othervise line levels return always idle (0x60).
+	 */
 	ctrl = MEC1322_I2C_BB_CTRL(controller);
 	MEC1322_I2C_BB_CTRL(controller) |= 1;
 	ret = (MEC1322_I2C_BB_CTRL(controller) >> 5) & 0x3;
@@ -236,10 +234,8 @@ static inline void push_in_buf(uint8_t **in, uint8_t val, int skip)
 	}
 }
 
-int chip_i2c_xfer(const int port,
-		  const uint16_t addr_flags,
-		  const uint8_t *out, int out_size,
-		  uint8_t *in, int in_size, int flags)
+int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out,
+		  int out_size, uint8_t *in, int in_size, int flags)
 {
 	int i;
 	int controller;
@@ -263,8 +259,7 @@ int chip_i2c_xfer(const int port,
 	if (send_start &&
 	    cdata[controller].transaction_state == I2C_TRANSACTION_STOPPED &&
 	    (((reg & (STS_BER | STS_LAB)) || !(reg & STS_NBB)) ||
-			    (get_line_level(controller)
-			    != I2C_LINE_IDLE))) {
+	     (get_line_level(controller) != I2C_LINE_IDLE))) {
 		CPRINTS("i2c%s bad status 0x%02x, SCL=%d, SDA=%d",
 			i2c_port_names[port], reg,
 			get_line_level(controller) & I2C_LINE_SCL_HIGH,
@@ -287,8 +282,7 @@ int chip_i2c_xfer(const int port,
 	if (out_size) {
 		if (send_start) {
 			MEC1322_I2C_DATA(controller) =
-				(uint8_t)(I2C_STRIP_FLAGS(addr_flags)
-					  << 1);
+				(uint8_t)(I2C_STRIP_FLAGS(addr_flags) << 1);
 
 			/* Clock out the slave address, sending START bit */
 			MEC1322_I2C_CTRL(controller) = CTRL_PIN | CTRL_ESO |
@@ -326,24 +320,20 @@ int chip_i2c_xfer(const int port,
 			/* Repeated start case */
 			if (cdata[controller].transaction_state ==
 			    I2C_TRANSACTION_OPEN)
-				MEC1322_I2C_CTRL(controller) = CTRL_ESO |
-							       CTRL_STA |
-							       CTRL_ACK |
-							       CTRL_ENI;
+				MEC1322_I2C_CTRL(controller) =
+					CTRL_ESO | CTRL_STA | CTRL_ACK |
+					CTRL_ENI;
 
 			MEC1322_I2C_DATA(controller) =
-				(uint8_t)(I2C_STRIP_FLAGS(addr_flags)
-					  << 1)
-				| 0x01;
+				(uint8_t)(I2C_STRIP_FLAGS(addr_flags) << 1) |
+				0x01;
 
 			/* New transaction case, clock out slave address. */
 			if (cdata[controller].transaction_state ==
 			    I2C_TRANSACTION_STOPPED)
-				MEC1322_I2C_CTRL(controller) = CTRL_ESO |
-							       CTRL_STA |
-							       CTRL_ACK |
-							       CTRL_ENI |
-							       CTRL_PIN;
+				MEC1322_I2C_CTRL(controller) =
+					CTRL_ESO | CTRL_STA | CTRL_ACK |
+					CTRL_ENI | CTRL_PIN;
 
 			cdata[controller].transaction_state =
 				I2C_TRANSACTION_OPEN;
@@ -379,8 +369,8 @@ int chip_i2c_xfer(const int port,
 				goto err_chip_i2c_xfer;
 
 			/* Send STOP */
-			MEC1322_I2C_CTRL(controller) =
-				CTRL_PIN | CTRL_ESO | CTRL_ACK | CTRL_STO;
+			MEC1322_I2C_CTRL(controller) = CTRL_PIN | CTRL_ESO |
+						       CTRL_ACK | CTRL_STO;
 
 			cdata[controller].transaction_state =
 				I2C_TRANSACTION_STOPPED;
@@ -403,8 +393,8 @@ int chip_i2c_xfer(const int port,
 	return EC_SUCCESS;
 err_chip_i2c_xfer:
 	/* Send STOP and return error */
-	MEC1322_I2C_CTRL(controller) = CTRL_PIN | CTRL_ESO |
-				       CTRL_STO | CTRL_ACK;
+	MEC1322_I2C_CTRL(controller) = CTRL_PIN | CTRL_ESO | CTRL_STO |
+				       CTRL_ACK;
 	cdata[controller].transaction_state = I2C_TRANSACTION_STOPPED;
 	if (ret_done == STS_LRB)
 		return EC_ERROR_BUSY;
@@ -417,8 +407,7 @@ err_chip_i2c_xfer:
 		 */
 		reset_controller(controller);
 		return EC_ERROR_TIMEOUT;
-	}
-	else
+	} else
 		return EC_ERROR_UNKNOWN;
 }
 
@@ -520,10 +509,22 @@ static void handle_interrupt(int controller)
 		task_set_event(id, TASK_EVENT_I2C_IDLE);
 }
 
-static void i2c0_interrupt(void) { handle_interrupt(0); }
-static void i2c1_interrupt(void) { handle_interrupt(1); }
-static void i2c2_interrupt(void) { handle_interrupt(2); }
-static void i2c3_interrupt(void) { handle_interrupt(3); }
+static void i2c0_interrupt(void)
+{
+	handle_interrupt(0);
+}
+static void i2c1_interrupt(void)
+{
+	handle_interrupt(1);
+}
+static void i2c2_interrupt(void)
+{
+	handle_interrupt(2);
+}
+static void i2c3_interrupt(void)
+{
+	handle_interrupt(3);
+}
 
 DECLARE_IRQ(MEC1322_IRQ_I2C_0, i2c0_interrupt, 2);
 DECLARE_IRQ(MEC1322_IRQ_I2C_1, i2c1_interrupt, 2);
diff --git a/chip/mec1322/keyboard_raw.c b/chip/mec1322/keyboard_raw.c
index 0f3381d79e..67200b6c04 100644
--- a/chip/mec1322/keyboard_raw.c
+++ b/chip/mec1322/keyboard_raw.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/chip/mec1322/lfw/ec_lfw.c b/chip/mec1322/lfw/ec_lfw.c
index 1fb334e144..92d3d2facc 100644
--- a/chip/mec1322/lfw/ec_lfw.c
+++ b/chip/mec1322/lfw/ec_lfw.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -25,24 +25,23 @@
 
 #include "ec_lfw.h"
 
-__attribute__ ((section(".intvector")))
+__attribute__((section(".intvector")))
 const struct int_vector_t hdr_int_vect = {
-			(void *)0x11FA00, /* init sp, unused,
-						set by MEC ROM loader*/
-			&lfw_main,	  /* reset vector */
-			&fault_handler,   /* NMI handler */
-			&fault_handler,   /* HardFault handler */
-			&fault_handler,   /* MPU fault handler */
-			&fault_handler    /* Bus fault handler */
+	(void *)0x11FA00, /* init sp, unused,
+				set by MEC ROM loader*/
+	&lfw_main, /* reset vector */
+	&fault_handler, /* NMI handler */
+	&fault_handler, /* HardFault handler */
+	&fault_handler, /* MPU fault handler */
+	&fault_handler /* Bus fault handler */
 };
 
 /* SPI devices - from glados/board.c*/
 const struct spi_device_t spi_devices[] = {
-	{ CONFIG_SPI_FLASH_PORT, 0, GPIO_PVT_CS0},
+	{ CONFIG_SPI_FLASH_PORT, 0, GPIO_PVT_CS0 },
 };
 const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
 
-
 void timer_init()
 {
 	uint32_t val = 0;
@@ -71,17 +70,13 @@ void timer_init()
 
 	/* Start counting in timer 0 */
 	MEC1322_TMR32_CTL(0) |= BIT(5);
-
 }
 
-static int spi_flash_readloc(uint8_t *buf_usr,
-				unsigned int offset,
-				unsigned int bytes)
+static int spi_flash_readloc(uint8_t *buf_usr, unsigned int offset,
+			     unsigned int bytes)
 {
-	uint8_t cmd[4] = {SPI_FLASH_READ,
-				(offset >> 16) & 0xFF,
-				(offset >> 8) & 0xFF,
-				offset & 0xFF};
+	uint8_t cmd[4] = { SPI_FLASH_READ, (offset >> 16) & 0xFF,
+			   (offset >> 8) & 0xFF, offset & 0xFF };
 
 	if (offset + bytes > CONFIG_FLASH_SIZE_BYTES)
 		return EC_ERROR_INVAL;
@@ -91,8 +86,8 @@ static int spi_flash_readloc(uint8_t *buf_usr,
 
 int spi_image_load(uint32_t offset)
 {
-	uint8_t *buf = (uint8_t *) (CONFIG_RW_MEM_OFF +
-				    CONFIG_PROGRAM_MEMORY_BASE);
+	uint8_t *buf =
+		(uint8_t *)(CONFIG_RW_MEM_OFF + CONFIG_PROGRAM_MEMORY_BASE);
 	uint32_t i;
 
 	BUILD_ASSERT(CONFIG_RO_SIZE == CONFIG_RW_SIZE);
@@ -102,7 +97,6 @@ int spi_image_load(uint32_t offset)
 		spi_flash_readloc(&buf[i], offset + i, SPI_CHUNK_SIZE);
 
 	return 0;
-
 }
 
 void udelay(unsigned us)
@@ -129,7 +123,6 @@ int timestamp_expired(timestamp_t deadline, const timestamp_t *now)
 	return now->le.lo >= deadline.le.lo;
 }
 
-
 timestamp_t get_time(void)
 {
 	timestamp_t ts;
@@ -169,12 +162,11 @@ void fault_handler(void)
 	MEC1322_WDG_CTL |= 1;
 	while (1)
 		;
-
 }
 
 void jump_to_image(uintptr_t init_addr)
 {
-	void (*resetvec)(void) = (void(*)(void))init_addr;
+	void (*resetvec)(void) = (void (*)(void))init_addr;
 	resetvec();
 }
 
@@ -212,10 +204,8 @@ void uart_init(void)
 
 void system_init(void)
 {
-
 	uint32_t wdt_sts = MEC1322_VBAT_STS & MEC1322_VBAT_STS_WDT;
-	uint32_t rst_sts = MEC1322_PCR_CHIP_PWR_RST &
-				MEC1322_PWR_RST_STS_VCC1;
+	uint32_t rst_sts = MEC1322_PCR_CHIP_PWR_RST & MEC1322_PWR_RST_STS_VCC1;
 
 	if (rst_sts || wdt_sts)
 		MEC1322_VBAT_RAM(MEC1322_IMAGETYPE_IDX) = EC_IMAGE_RO;
@@ -228,11 +218,10 @@ enum ec_image system_get_image_copy(void)
 
 void lfw_main()
 {
-
 	uintptr_t init_addr;
 
 	/* install vector table */
-	*((uintptr_t *) 0xe000ed08) = (uintptr_t) &hdr_int_vect;
+	*((uintptr_t *)0xe000ed08) = (uintptr_t)&hdr_int_vect;
 
 	/* Use 48 MHz processor clock to power through boot */
 	MEC1322_PCR_PROC_CLK_CTL = 1;
diff --git a/chip/mec1322/lfw/ec_lfw.h b/chip/mec1322/lfw/ec_lfw.h
index dd26fbd323..cdb0d1cc32 100644
--- a/chip/mec1322/lfw/ec_lfw.h
+++ b/chip/mec1322/lfw/ec_lfw.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,16 +8,16 @@
 
 #include <stdnoreturn.h>
 
-noreturn void lfw_main(void) __attribute__ ((naked));
+noreturn void lfw_main(void) __attribute__((naked));
 void fault_handler(void) __attribute__((naked));
 
 struct int_vector_t {
-	void   *stack_ptr;
-	void   *reset_vector;
-	void   *nmi;
-	void   *hard_fault;
-	void   *bus_fault;
-	void   *usage_fault;
+	void *stack_ptr;
+	void *reset_vector;
+	void *nmi;
+	void *hard_fault;
+	void *bus_fault;
+	void *usage_fault;
 };
 
-#define SPI_CHUNK_SIZE			1024
+#define SPI_CHUNK_SIZE 1024
diff --git a/chip/mec1322/lfw/ec_lfw.ld b/chip/mec1322/lfw/ec_lfw.ld
index 65e17e4941..be3d1dc768 100644
--- a/chip/mec1322/lfw/ec_lfw.ld
+++ b/chip/mec1322/lfw/ec_lfw.ld
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/chip/mec1322/lpc.c b/chip/mec1322/lpc.c
index be3b36cfef..7dc1d621af 100644
--- a/chip/mec1322/lpc.c
+++ b/chip/mec1322/lpc.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,18 +22,18 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args)
 
 static uint8_t mem_mapped[0x200] __attribute__((section(".bss.big_align")));
 
 static struct host_packet lpc_packet;
 static struct host_cmd_handler_args host_cmd_args;
-static uint8_t host_cmd_flags;   /* Flags from host command */
+static uint8_t host_cmd_flags; /* Flags from host command */
 
 static uint8_t params_copy[EC_LPC_HOST_PACKET_SIZE] __aligned(4);
 static int init_done;
 
-static struct ec_lpc_host_args * const lpc_host_args =
+static struct ec_lpc_host_args *const lpc_host_args =
 	(struct ec_lpc_host_args *)mem_mapped;
 
 static void keyboard_irq_assert(void)
@@ -83,7 +83,7 @@ static void lpc_generate_sci(void)
 	gpio_set_level(CONFIG_SCI_GPIO, 1);
 #else
 	MEC1322_ACPI_PM_STS |= 1;
-	udelay(CONFIG_ESPI_DEFAULT_VW_WIDTH_US);
+	udelay(CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US);
 	MEC1322_ACPI_PM_STS &= ~1;
 #endif
 }
@@ -152,7 +152,7 @@ void lpc_update_host_event_status(void)
 
 	/* Copy host events to mapped memory */
 	*(host_event_t *)host_get_memmap(EC_MEMMAP_HOST_EVENTS) =
-				lpc_get_host_events();
+		lpc_get_host_events();
 
 	task_enable_irq(MEC1322_IRQ_ACPIEC0_IBF);
 
@@ -267,9 +267,9 @@ static void lpc_init(void)
 	MEC1322_LPC_ACT |= 1;
 
 	/*
-	* Ring Oscillator not permitted to shut down
-	* until LPC activate bit is cleared
-	*/
+	 * Ring Oscillator not permitted to shut down
+	 * until LPC activate bit is cleared
+	 */
 	MEC1322_LPC_CLK_CTRL |= 3;
 
 	/* Initialize host args and memory map to all zero */
@@ -375,8 +375,7 @@ DECLARE_IRQ(MEC1322_IRQ_ACPIEC0_IBF, acpi_0_interrupt, 1);
 void acpi_1_interrupt(void)
 {
 	uint8_t st = MEC1322_ACPI_EC_STATUS(1);
-	if (!(st & EC_LPC_STATUS_FROM_HOST) ||
-	    !(st & EC_LPC_STATUS_LAST_CMD))
+	if (!(st & EC_LPC_STATUS_FROM_HOST) || !(st & EC_LPC_STATUS_LAST_CMD))
 		return;
 
 	/* Set the busy bit */
@@ -477,7 +476,7 @@ void lpc_clear_acpi_status_mask(uint8_t mask)
 
 int lpc_get_pltrst_asserted(void)
 {
-	return (MEC1322_LPC_BUS_MONITOR & (1<<1)) ? 1 : 0;
+	return (MEC1322_LPC_BUS_MONITOR & (1 << 1)) ? 1 : 0;
 }
 
 /* Enable LPC ACPI-EC0 interrupts */
@@ -515,6 +514,5 @@ static enum ec_status lpc_get_protocol_info(struct host_cmd_handler_args *args)
 
 	return EC_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO,
-		lpc_get_protocol_info,
-		EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, lpc_get_protocol_info,
+		     EC_VER_MASK(0));
diff --git a/chip/mec1322/port80.c b/chip/mec1322/port80.c
index e2f02c81e5..cbc87d8a88 100644
--- a/chip/mec1322/port80.c
+++ b/chip/mec1322/port80.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,9 +17,8 @@
 #define POLL_PERIOD_USEC 1000
 /* After 30 seconds of no port 80 data, disable the timer interrupt. */
 #define INTERRUPT_DISABLE_TIMEOUT_SEC 30
-#define INTERRUPT_DISABLE_IDLE_COUNT (INTERRUPT_DISABLE_TIMEOUT_SEC \
-				      * 1000000 \
-				      / POLL_PERIOD_USEC)
+#define INTERRUPT_DISABLE_IDLE_COUNT \
+	(INTERRUPT_DISABLE_TIMEOUT_SEC * 1000000 / POLL_PERIOD_USEC)
 
 /* Count the number of consecutive interrupts with no port 80 data. */
 static int idle_count;
diff --git a/chip/mec1322/pwm.c b/chip/mec1322/pwm.c
index ce94e50e7e..bcb9360638 100644
--- a/chip/mec1322/pwm.c
+++ b/chip/mec1322/pwm.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,8 +24,7 @@ void pwm_enable(enum pwm_channel ch, int enabled)
 	if (enabled) {
 		MEC1322_PWM_CFG(id) |= 0x1;
 		if (pwm_channels[ch].flags & PWM_CONFIG_DSLEEP)
-			pwm_keep_awake_mask |=
-				MEC1322_PCR_EC_SLP_EN_PWM(id);
+			pwm_keep_awake_mask |= MEC1322_PCR_EC_SLP_EN_PWM(id);
 	} else {
 		MEC1322_PWM_CFG(id) &= ~0x1;
 		pwm_keep_awake_mask &= ~MEC1322_PCR_EC_SLP_EN_PWM(id);
@@ -66,9 +65,9 @@ static void pwm_configure(int ch, int active_low, int clock_low)
 	 * clock_low=0 selects the 48MHz Ring Oscillator source
 	 * clock_low=1 selects the 100kHz_Clk source
 	 */
-	MEC1322_PWM_CFG(ch) = (15 << 3) |    /* Pre-divider = 16 */
+	MEC1322_PWM_CFG(ch) = (15 << 3) | /* Pre-divider = 16 */
 			      (active_low ? BIT(2) : 0) |
-			      (clock_low  ? BIT(1) : 0);
+			      (clock_low ? BIT(1) : 0);
 }
 
 static void pwm_init(void)
diff --git a/chip/mec1322/pwm_chip.h b/chip/mec1322/pwm_chip.h
index 9c441aaecd..69d8de094a 100644
--- a/chip/mec1322/pwm_chip.h
+++ b/chip/mec1322/pwm_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,4 +23,4 @@ extern const struct pwm_t pwm_channels[];
  * MEC1322_PCR_EC_SLP_EN bit mask.
  */
 uint32_t pwm_get_keep_awake_mask(void);
-#endif  /* __CROS_EC_PWM_CHIP_H */
+#endif /* __CROS_EC_PWM_CHIP_H */
diff --git a/chip/mec1322/registers.h b/chip/mec1322/registers.h
index 7bbd9fb068..1a758003c9 100644
--- a/chip/mec1322/registers.h
+++ b/chip/mec1322/registers.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,105 +11,102 @@
 #include "common.h"
 
 /* Helper function for RAM address aliasing */
-#define MEC1322_RAM_ALIAS(x)   \
-	((x) >= 0x118000 ? (x) - 0x118000 + 0x20000000 : (x))
+#define MEC1322_RAM_ALIAS(x) ((x) >= 0x118000 ? (x)-0x118000 + 0x20000000 : (x))
 
 /* EC Chip Configuration */
-#define MEC1322_CHIP_BASE      0x400fff00
-#define MEC1322_CHIP_DEV_ID    REG8(MEC1322_CHIP_BASE + 0x20)
-#define MEC1322_CHIP_DEV_REV   REG8(MEC1322_CHIP_BASE + 0x21)
-
+#define MEC1322_CHIP_BASE 0x400fff00
+#define MEC1322_CHIP_DEV_ID REG8(MEC1322_CHIP_BASE + 0x20)
+#define MEC1322_CHIP_DEV_REV REG8(MEC1322_CHIP_BASE + 0x21)
 
 /* Power/Clocks/Resets */
-#define MEC1322_PCR_BASE         0x40080100
-#define MEC1322_PCR_CHIP_SLP_EN  REG32(MEC1322_PCR_BASE + 0x0)
+#define MEC1322_PCR_BASE 0x40080100
+#define MEC1322_PCR_CHIP_SLP_EN REG32(MEC1322_PCR_BASE + 0x0)
 #define MEC1322_PCR_CHIP_CLK_REQ REG32(MEC1322_PCR_BASE + 0x4)
-#define MEC1322_PCR_EC_SLP_EN    REG32(MEC1322_PCR_BASE + 0x8)
+#define MEC1322_PCR_EC_SLP_EN REG32(MEC1322_PCR_BASE + 0x8)
 /* Command all blocks to sleep */
-#define  MEC1322_PCR_EC_SLP_EN_SLEEP	0xe0700ff7
-#define  MEC1322_PCR_EC_SLP_EN_PWM(n)	(1 << ((n) ? (19 + (n)) : 4))
-#define  MEC1322_PCR_EC_SLP_EN_PWM3	BIT(22)
-#define  MEC1322_PCR_EC_SLP_EN_PWM2	BIT(21)
-#define  MEC1322_PCR_EC_SLP_EN_PWM1	BIT(20)
-#define  MEC1322_PCR_EC_SLP_EN_PWM0	BIT(4)
+#define MEC1322_PCR_EC_SLP_EN_SLEEP 0xe0700ff7
+#define MEC1322_PCR_EC_SLP_EN_PWM(n) (1 << ((n) ? (19 + (n)) : 4))
+#define MEC1322_PCR_EC_SLP_EN_PWM3 BIT(22)
+#define MEC1322_PCR_EC_SLP_EN_PWM2 BIT(21)
+#define MEC1322_PCR_EC_SLP_EN_PWM1 BIT(20)
+#define MEC1322_PCR_EC_SLP_EN_PWM0 BIT(4)
 /* Allow all blocks to request clocks */
-#define  MEC1322_PCR_EC_SLP_EN_WAKE	(~0xe0700ff7)
-#define MEC1322_PCR_EC_CLK_REQ   REG32(MEC1322_PCR_BASE + 0xc)
-#define MEC1322_PCR_HOST_SLP_EN  REG32(MEC1322_PCR_BASE + 0x10)
+#define MEC1322_PCR_EC_SLP_EN_WAKE (~0xe0700ff7)
+#define MEC1322_PCR_EC_CLK_REQ REG32(MEC1322_PCR_BASE + 0xc)
+#define MEC1322_PCR_HOST_SLP_EN REG32(MEC1322_PCR_BASE + 0x10)
 /* Command all blocks to sleep */
-#define  MEC1322_PCR_HOST_SLP_EN_SLEEP	0x5f003
+#define MEC1322_PCR_HOST_SLP_EN_SLEEP 0x5f003
 /* Allow all blocks to request clocks */
-#define  MEC1322_PCR_HOST_SLP_EN_WAKE	(~0x5f003)
+#define MEC1322_PCR_HOST_SLP_EN_WAKE (~0x5f003)
 #define MEC1322_PCR_HOST_CLK_REQ REG32(MEC1322_PCR_BASE + 0x14)
-#define MEC1322_PCR_SYS_SLP_CTL  REG32(MEC1322_PCR_BASE + 0x18)
+#define MEC1322_PCR_SYS_SLP_CTL REG32(MEC1322_PCR_BASE + 0x18)
 #define MEC1322_PCR_PROC_CLK_CTL REG32(MEC1322_PCR_BASE + 0x20)
-#define MEC1322_PCR_EC_SLP_EN2   REG32(MEC1322_PCR_BASE + 0x24)
+#define MEC1322_PCR_EC_SLP_EN2 REG32(MEC1322_PCR_BASE + 0x24)
 /* Mask to command all blocks to sleep */
-#define  MEC1322_PCR_EC_SLP_EN2_SLEEP	0x1ffffff8
+#define MEC1322_PCR_EC_SLP_EN2_SLEEP 0x1ffffff8
 /* Allow all blocks to request clocks */
-#define  MEC1322_PCR_EC_SLP_EN2_WAKE	(~0x03fffff8)
-#define MEC1322_PCR_EC_CLK_REQ2  REG32(MEC1322_PCR_BASE + 0x28)
+#define MEC1322_PCR_EC_SLP_EN2_WAKE (~0x03fffff8)
+#define MEC1322_PCR_EC_CLK_REQ2 REG32(MEC1322_PCR_BASE + 0x28)
 #define MEC1322_PCR_SLOW_CLK_CTL REG32(MEC1322_PCR_BASE + 0x2c)
-#define MEC1322_PCR_CHIP_OSC_ID  REG32(MEC1322_PCR_BASE + 0x30)
+#define MEC1322_PCR_CHIP_OSC_ID REG32(MEC1322_PCR_BASE + 0x30)
 #define MEC1322_PCR_CHIP_PWR_RST REG32(MEC1322_PCR_BASE + 0x34)
-#define MEC1322_PCR_CHIP_RST_EN  REG32(MEC1322_PCR_BASE + 0x38)
-#define MEC1322_PCR_HOST_RST_EN  REG32(MEC1322_PCR_BASE + 0x3c)
-#define MEC1322_PCR_EC_RST_EN    REG32(MEC1322_PCR_BASE + 0x40)
-#define MEC1322_PCR_EC_RST_EN2   REG32(MEC1322_PCR_BASE + 0x44)
-#define MEC1322_PCR_PWR_RST_CTL  REG32(MEC1322_PCR_BASE + 0x48)
+#define MEC1322_PCR_CHIP_RST_EN REG32(MEC1322_PCR_BASE + 0x38)
+#define MEC1322_PCR_HOST_RST_EN REG32(MEC1322_PCR_BASE + 0x3c)
+#define MEC1322_PCR_EC_RST_EN REG32(MEC1322_PCR_BASE + 0x40)
+#define MEC1322_PCR_EC_RST_EN2 REG32(MEC1322_PCR_BASE + 0x44)
+#define MEC1322_PCR_PWR_RST_CTL REG32(MEC1322_PCR_BASE + 0x48)
 
 /* Bit defines for MEC1322_PCR_CHIP_PWR_RST */
 #define MEC1322_PWR_RST_STS_VCC1 BIT(6)
 #define MEC1322_PWR_RST_STS_VBAT BIT(5)
 
 /* EC Subsystem */
-#define MEC1322_EC_BASE        0x4000fc00
-#define MEC1322_EC_INT_CTRL    REG32(MEC1322_EC_BASE + 0x18)
-#define MEC1322_EC_TRACE_EN    REG32(MEC1322_EC_BASE + 0x1c)
-#define MEC1322_EC_JTAG_EN     REG32(MEC1322_EC_BASE + 0x20)
-#define MEC1322_EC_WDT_CNT     REG32(MEC1322_EC_BASE + 0x28)
+#define MEC1322_EC_BASE 0x4000fc00
+#define MEC1322_EC_INT_CTRL REG32(MEC1322_EC_BASE + 0x18)
+#define MEC1322_EC_TRACE_EN REG32(MEC1322_EC_BASE + 0x1c)
+#define MEC1322_EC_JTAG_EN REG32(MEC1322_EC_BASE + 0x20)
+#define MEC1322_EC_WDT_CNT REG32(MEC1322_EC_BASE + 0x28)
 #define MEC1322_EC_ADC_VREF_PD REG32(MEC1322_EC_BASE + 0x38)
 
 /* Interrupt aggregator */
-#define MEC1322_INT_BASE       0x4000c000
-#define MEC1322_INTx_BASE(x)   (MEC1322_INT_BASE + ((x) - 8) * 0x14)
-#define MEC1322_INT_SOURCE(x)  REG32(MEC1322_INTx_BASE(x) + 0x0)
-#define MEC1322_INT_ENABLE(x)  REG32(MEC1322_INTx_BASE(x) + 0x4)
-#define MEC1322_INT_RESULT(x)  REG32(MEC1322_INTx_BASE(x) + 0x8)
+#define MEC1322_INT_BASE 0x4000c000
+#define MEC1322_INTx_BASE(x) (MEC1322_INT_BASE + ((x)-8) * 0x14)
+#define MEC1322_INT_SOURCE(x) REG32(MEC1322_INTx_BASE(x) + 0x0)
+#define MEC1322_INT_ENABLE(x) REG32(MEC1322_INTx_BASE(x) + 0x4)
+#define MEC1322_INT_RESULT(x) REG32(MEC1322_INTx_BASE(x) + 0x8)
 #define MEC1322_INT_DISABLE(x) REG32(MEC1322_INTx_BASE(x) + 0xc)
-#define MEC1322_INT_BLK_EN     REG32(MEC1322_INT_BASE + 0x200)
-#define MEC1322_INT_BLK_DIS    REG32(MEC1322_INT_BASE + 0x204)
-#define MEC1322_INT_BLK_IRQ    REG32(MEC1322_INT_BASE + 0x208)
-
+#define MEC1322_INT_BLK_EN REG32(MEC1322_INT_BASE + 0x200)
+#define MEC1322_INT_BLK_DIS REG32(MEC1322_INT_BASE + 0x204)
+#define MEC1322_INT_BLK_IRQ REG32(MEC1322_INT_BASE + 0x208)
 
 /* UART */
-#define MEC1322_UART_CONFIG_BASE  0x400f1f00
+#define MEC1322_UART_CONFIG_BASE 0x400f1f00
 #define MEC1322_UART_RUNTIME_BASE 0x400f1c00
 
-#define MEC1322_UART_ACT       REG8(MEC1322_UART_CONFIG_BASE + 0x30)
-#define MEC1322_UART_CFG       REG8(MEC1322_UART_CONFIG_BASE + 0xf0)
+#define MEC1322_UART_ACT REG8(MEC1322_UART_CONFIG_BASE + 0x30)
+#define MEC1322_UART_CFG REG8(MEC1322_UART_CONFIG_BASE + 0xf0)
 
 /* DLAB=0 */
-#define MEC1322_UART_RB /*R*/  REG8(MEC1322_UART_RUNTIME_BASE + 0x0)
-#define MEC1322_UART_TB /*W*/  REG8(MEC1322_UART_RUNTIME_BASE + 0x0)
-#define MEC1322_UART_IER       REG8(MEC1322_UART_RUNTIME_BASE + 0x1)
+#define MEC1322_UART_RB /*R*/ REG8(MEC1322_UART_RUNTIME_BASE + 0x0)
+#define MEC1322_UART_TB /*W*/ REG8(MEC1322_UART_RUNTIME_BASE + 0x0)
+#define MEC1322_UART_IER REG8(MEC1322_UART_RUNTIME_BASE + 0x1)
 /* DLAB=1 */
-#define MEC1322_UART_PBRG0     REG8(MEC1322_UART_RUNTIME_BASE + 0x0)
-#define MEC1322_UART_PBRG1     REG8(MEC1322_UART_RUNTIME_BASE + 0x1)
+#define MEC1322_UART_PBRG0 REG8(MEC1322_UART_RUNTIME_BASE + 0x0)
+#define MEC1322_UART_PBRG1 REG8(MEC1322_UART_RUNTIME_BASE + 0x1)
 
 #define MEC1322_UART_FCR /*W*/ REG8(MEC1322_UART_RUNTIME_BASE + 0x2)
 #define MEC1322_UART_IIR /*R*/ REG8(MEC1322_UART_RUNTIME_BASE + 0x2)
-#define MEC1322_UART_LCR       REG8(MEC1322_UART_RUNTIME_BASE + 0x3)
-#define MEC1322_UART_MCR       REG8(MEC1322_UART_RUNTIME_BASE + 0x4)
-#define MEC1322_UART_LSR       REG8(MEC1322_UART_RUNTIME_BASE + 0x5)
-#define MEC1322_UART_MSR       REG8(MEC1322_UART_RUNTIME_BASE + 0x6)
-#define MEC1322_UART_SCR       REG8(MEC1322_UART_RUNTIME_BASE + 0x7)
+#define MEC1322_UART_LCR REG8(MEC1322_UART_RUNTIME_BASE + 0x3)
+#define MEC1322_UART_MCR REG8(MEC1322_UART_RUNTIME_BASE + 0x4)
+#define MEC1322_UART_LSR REG8(MEC1322_UART_RUNTIME_BASE + 0x5)
+#define MEC1322_UART_MSR REG8(MEC1322_UART_RUNTIME_BASE + 0x6)
+#define MEC1322_UART_SCR REG8(MEC1322_UART_RUNTIME_BASE + 0x7)
 
 /* Bit defines for MEC1322_UART_LSR */
-#define MEC1322_LSR_TX_EMPTY     BIT(5)
+#define MEC1322_LSR_TX_EMPTY BIT(5)
 
 /* GPIO */
-#define MEC1322_GPIO_BASE      0x40081000
+#define MEC1322_GPIO_BASE 0x40081000
 
 static inline uintptr_t gpio_port_base(int port_id)
 {
@@ -120,243 +117,230 @@ static inline uintptr_t gpio_port_base(int port_id)
 
 #define UNIMPLEMENTED_GPIO_BANK 0
 
-
 /* Timer */
-#define MEC1322_TMR16_BASE(x)  (0x40000c00 + (x) * 0x20)
-#define MEC1322_TMR32_BASE(x)  (0x40000c80 + (x) * 0x20)
-
-#define MEC1322_TMR16_CNT(x)   REG32(MEC1322_TMR16_BASE(x) + 0x0)
-#define MEC1322_TMR16_PRE(x)   REG32(MEC1322_TMR16_BASE(x) + 0x4)
-#define MEC1322_TMR16_STS(x)   REG32(MEC1322_TMR16_BASE(x) + 0x8)
-#define MEC1322_TMR16_IEN(x)   REG32(MEC1322_TMR16_BASE(x) + 0xc)
-#define MEC1322_TMR16_CTL(x)   REG32(MEC1322_TMR16_BASE(x) + 0x10)
-#define MEC1322_TMR32_CNT(x)   REG32(MEC1322_TMR32_BASE(x) + 0x0)
-#define MEC1322_TMR32_PRE(x)   REG32(MEC1322_TMR32_BASE(x) + 0x4)
-#define MEC1322_TMR32_STS(x)   REG32(MEC1322_TMR32_BASE(x) + 0x8)
-#define MEC1322_TMR32_IEN(x)   REG32(MEC1322_TMR32_BASE(x) + 0xc)
-#define MEC1322_TMR32_CTL(x)   REG32(MEC1322_TMR32_BASE(x) + 0x10)
-
+#define MEC1322_TMR16_BASE(x) (0x40000c00 + (x)*0x20)
+#define MEC1322_TMR32_BASE(x) (0x40000c80 + (x)*0x20)
+
+#define MEC1322_TMR16_CNT(x) REG32(MEC1322_TMR16_BASE(x) + 0x0)
+#define MEC1322_TMR16_PRE(x) REG32(MEC1322_TMR16_BASE(x) + 0x4)
+#define MEC1322_TMR16_STS(x) REG32(MEC1322_TMR16_BASE(x) + 0x8)
+#define MEC1322_TMR16_IEN(x) REG32(MEC1322_TMR16_BASE(x) + 0xc)
+#define MEC1322_TMR16_CTL(x) REG32(MEC1322_TMR16_BASE(x) + 0x10)
+#define MEC1322_TMR32_CNT(x) REG32(MEC1322_TMR32_BASE(x) + 0x0)
+#define MEC1322_TMR32_PRE(x) REG32(MEC1322_TMR32_BASE(x) + 0x4)
+#define MEC1322_TMR32_STS(x) REG32(MEC1322_TMR32_BASE(x) + 0x8)
+#define MEC1322_TMR32_IEN(x) REG32(MEC1322_TMR32_BASE(x) + 0xc)
+#define MEC1322_TMR32_CTL(x) REG32(MEC1322_TMR32_BASE(x) + 0x10)
 
 /* Watchdog */
-#define MEC1322_WDG_BASE       0x40000400
-#define MEC1322_WDG_LOAD       REG16(MEC1322_WDG_BASE + 0x0)
-#define MEC1322_WDG_CTL        REG8(MEC1322_WDG_BASE + 0x4)
-#define MEC1322_WDG_KICK       REG8(MEC1322_WDG_BASE + 0x8)
-#define MEC1322_WDG_CNT        REG16(MEC1322_WDG_BASE + 0xc)
-
+#define MEC1322_WDG_BASE 0x40000400
+#define MEC1322_WDG_LOAD REG16(MEC1322_WDG_BASE + 0x0)
+#define MEC1322_WDG_CTL REG8(MEC1322_WDG_BASE + 0x4)
+#define MEC1322_WDG_KICK REG8(MEC1322_WDG_BASE + 0x8)
+#define MEC1322_WDG_CNT REG16(MEC1322_WDG_BASE + 0xc)
 
 /* VBAT */
-#define MEC1322_VBAT_BASE      0x4000a400
-#define MEC1322_VBAT_STS       REG32(MEC1322_VBAT_BASE + 0x0)
-#define MEC1322_VBAT_CE        REG32(MEC1322_VBAT_BASE + 0x8)
-#define MEC1322_VBAT_RAM(x)    REG32(MEC1322_VBAT_BASE + 0x400 + 4 * (x))
+#define MEC1322_VBAT_BASE 0x4000a400
+#define MEC1322_VBAT_STS REG32(MEC1322_VBAT_BASE + 0x0)
+#define MEC1322_VBAT_CE REG32(MEC1322_VBAT_BASE + 0x8)
+#define MEC1322_VBAT_RAM(x) REG32(MEC1322_VBAT_BASE + 0x400 + 4 * (x))
 
 /* Bit definition for MEC1322_VBAT_STS */
-#define MEC1322_VBAT_STS_WDT	BIT(5)
+#define MEC1322_VBAT_STS_WDT BIT(5)
 
 /* Miscellaneous firmware control fields
  * scratch pad index cannot be more than 16 as
  * mec has 64 bytes = 16 indexes of scratchpad RAM
  */
-#define MEC1322_IMAGETYPE_IDX     15
+#define MEC1322_IMAGETYPE_IDX 15
 
 /* LPC */
-#define MEC1322_LPC_CFG_BASE     0x400f3300
-#define MEC1322_LPC_ACT          REG8(MEC1322_LPC_CFG_BASE + 0x30)
-#define MEC1322_LPC_SIRQ(x)      REG8(MEC1322_LPC_CFG_BASE + 0x40 + (x))
-#define MEC1322_LPC_CFG_BAR      REG32(MEC1322_LPC_CFG_BASE + 0x60)
-#define MEC1322_LPC_EMI_BAR      REG32(MEC1322_LPC_CFG_BASE + 0x64)
-#define MEC1322_LPC_UART_BAR     REG32(MEC1322_LPC_CFG_BASE + 0x68)
-#define MEC1322_LPC_8042_BAR     REG32(MEC1322_LPC_CFG_BASE + 0x78)
+#define MEC1322_LPC_CFG_BASE 0x400f3300
+#define MEC1322_LPC_ACT REG8(MEC1322_LPC_CFG_BASE + 0x30)
+#define MEC1322_LPC_SIRQ(x) REG8(MEC1322_LPC_CFG_BASE + 0x40 + (x))
+#define MEC1322_LPC_CFG_BAR REG32(MEC1322_LPC_CFG_BASE + 0x60)
+#define MEC1322_LPC_EMI_BAR REG32(MEC1322_LPC_CFG_BASE + 0x64)
+#define MEC1322_LPC_UART_BAR REG32(MEC1322_LPC_CFG_BASE + 0x68)
+#define MEC1322_LPC_8042_BAR REG32(MEC1322_LPC_CFG_BASE + 0x78)
 #define MEC1322_LPC_ACPI_EC0_BAR REG32(MEC1322_LPC_CFG_BASE + 0x88)
 #define MEC1322_LPC_ACPI_EC1_BAR REG32(MEC1322_LPC_CFG_BASE + 0x8c)
 #define MEC1322_LPC_ACPI_PM1_BAR REG32(MEC1322_LPC_CFG_BASE + 0x90)
-#define MEC1322_LPC_PORT92_BAR   REG32(MEC1322_LPC_CFG_BASE + 0x94)
-#define MEC1322_LPC_MAILBOX_BAR  REG32(MEC1322_LPC_CFG_BASE + 0x98)
-#define MEC1322_LPC_RTC_BAR      REG32(MEC1322_LPC_CFG_BASE + 0x9c)
-#define MEC1322_LPC_MEM_BAR      REG32(MEC1322_LPC_CFG_BASE + 0xa0)
-#define MEC1322_LPC_MEM_BAR_CFG  REG32(MEC1322_LPC_CFG_BASE + 0xa4)
-
-#define MEC1322_LPC_RT_BASE      0x400f3100
-#define MEC1322_LPC_BUS_MONITOR  REG32(MEC1322_LPC_RT_BASE + 0x4)
-#define MEC1322_LPC_CLK_CTRL     REG32(MEC1322_LPC_RT_BASE + 0x10)
+#define MEC1322_LPC_PORT92_BAR REG32(MEC1322_LPC_CFG_BASE + 0x94)
+#define MEC1322_LPC_MAILBOX_BAR REG32(MEC1322_LPC_CFG_BASE + 0x98)
+#define MEC1322_LPC_RTC_BAR REG32(MEC1322_LPC_CFG_BASE + 0x9c)
+#define MEC1322_LPC_MEM_BAR REG32(MEC1322_LPC_CFG_BASE + 0xa0)
+#define MEC1322_LPC_MEM_BAR_CFG REG32(MEC1322_LPC_CFG_BASE + 0xa4)
+
+#define MEC1322_LPC_RT_BASE 0x400f3100
+#define MEC1322_LPC_BUS_MONITOR REG32(MEC1322_LPC_RT_BASE + 0x4)
+#define MEC1322_LPC_CLK_CTRL REG32(MEC1322_LPC_RT_BASE + 0x10)
 #define MEC1322_LPC_MEM_HOST_CFG REG32(MEC1322_LPC_RT_BASE + 0xfc)
 
-
 /* EMI */
-#define MEC1322_EMI_BASE       0x400f0100
-#define MEC1322_EMI_H2E_MBX    REG8(MEC1322_EMI_BASE + 0x0)
-#define MEC1322_EMI_E2H_MBX    REG8(MEC1322_EMI_BASE + 0x1)
-#define MEC1322_EMI_MBA0       REG32(MEC1322_EMI_BASE + 0x4)
-#define MEC1322_EMI_MRL0       REG16(MEC1322_EMI_BASE + 0x8)
-#define MEC1322_EMI_MWL0       REG16(MEC1322_EMI_BASE + 0xa)
-#define MEC1322_EMI_MBA1       REG32(MEC1322_EMI_BASE + 0xc)
-#define MEC1322_EMI_MRL1       REG16(MEC1322_EMI_BASE + 0x10)
-#define MEC1322_EMI_MWL1       REG16(MEC1322_EMI_BASE + 0x12)
-#define MEC1322_EMI_ISR        REG16(MEC1322_EMI_BASE + 0x14)
-#define MEC1322_EMI_HCE        REG16(MEC1322_EMI_BASE + 0x16)
-
-#define MEC1322_EMI_RT_BASE    0x400f0000
-#define MEC1322_EMI_ISR_B0     REG8(MEC1322_EMI_RT_BASE + 0x8)
-#define MEC1322_EMI_ISR_B1     REG8(MEC1322_EMI_RT_BASE + 0x9)
-#define MEC1322_EMI_IMR_B0     REG8(MEC1322_EMI_RT_BASE + 0xa)
-#define MEC1322_EMI_IMR_B1     REG8(MEC1322_EMI_RT_BASE + 0xb)
-
+#define MEC1322_EMI_BASE 0x400f0100
+#define MEC1322_EMI_H2E_MBX REG8(MEC1322_EMI_BASE + 0x0)
+#define MEC1322_EMI_E2H_MBX REG8(MEC1322_EMI_BASE + 0x1)
+#define MEC1322_EMI_MBA0 REG32(MEC1322_EMI_BASE + 0x4)
+#define MEC1322_EMI_MRL0 REG16(MEC1322_EMI_BASE + 0x8)
+#define MEC1322_EMI_MWL0 REG16(MEC1322_EMI_BASE + 0xa)
+#define MEC1322_EMI_MBA1 REG32(MEC1322_EMI_BASE + 0xc)
+#define MEC1322_EMI_MRL1 REG16(MEC1322_EMI_BASE + 0x10)
+#define MEC1322_EMI_MWL1 REG16(MEC1322_EMI_BASE + 0x12)
+#define MEC1322_EMI_ISR REG16(MEC1322_EMI_BASE + 0x14)
+#define MEC1322_EMI_HCE REG16(MEC1322_EMI_BASE + 0x16)
+
+#define MEC1322_EMI_RT_BASE 0x400f0000
+#define MEC1322_EMI_ISR_B0 REG8(MEC1322_EMI_RT_BASE + 0x8)
+#define MEC1322_EMI_ISR_B1 REG8(MEC1322_EMI_RT_BASE + 0x9)
+#define MEC1322_EMI_IMR_B0 REG8(MEC1322_EMI_RT_BASE + 0xa)
+#define MEC1322_EMI_IMR_B1 REG8(MEC1322_EMI_RT_BASE + 0xb)
 
 /* Mailbox */
-#define MEC1322_MBX_RT_BASE    0x400f2400
-#define MEC1322_MBX_INDEX      REG8(MEC1322_MBX_RT_BASE + 0x0)
-#define MEC1322_MBX_DATA       REG8(MEC1322_MBX_RT_BASE + 0x1)
-
-#define MEC1322_MBX_BASE       0x400f2500
-#define MEC1322_MBX_H2E_MBX    REG8(MEC1322_MBX_BASE + 0x0)
-#define MEC1322_MBX_E2H_MBX    REG8(MEC1322_MBX_BASE + 0x4)
-#define MEC1322_MBX_ISR        REG8(MEC1322_MBX_BASE + 0x8)
-#define MEC1322_MBX_IMR        REG8(MEC1322_MBX_BASE + 0xc)
-#define MEC1322_MBX_REG(x)     REG8(MEC1322_MBX_BASE + 0x10 + (x))
+#define MEC1322_MBX_RT_BASE 0x400f2400
+#define MEC1322_MBX_INDEX REG8(MEC1322_MBX_RT_BASE + 0x0)
+#define MEC1322_MBX_DATA REG8(MEC1322_MBX_RT_BASE + 0x1)
 
+#define MEC1322_MBX_BASE 0x400f2500
+#define MEC1322_MBX_H2E_MBX REG8(MEC1322_MBX_BASE + 0x0)
+#define MEC1322_MBX_E2H_MBX REG8(MEC1322_MBX_BASE + 0x4)
+#define MEC1322_MBX_ISR REG8(MEC1322_MBX_BASE + 0x8)
+#define MEC1322_MBX_IMR REG8(MEC1322_MBX_BASE + 0xc)
+#define MEC1322_MBX_REG(x) REG8(MEC1322_MBX_BASE + 0x10 + (x))
 
 /* PWM */
-#define MEC1322_PWM_BASE(x)    (0x40005800 + (x) * 0x10)
-#define MEC1322_PWM_ON(x)      REG32(MEC1322_PWM_BASE(x) + 0x00)
-#define MEC1322_PWM_OFF(x)     REG32(MEC1322_PWM_BASE(x) + 0x04)
-#define MEC1322_PWM_CFG(x)     REG32(MEC1322_PWM_BASE(x) + 0x08)
-
+#define MEC1322_PWM_BASE(x) (0x40005800 + (x)*0x10)
+#define MEC1322_PWM_ON(x) REG32(MEC1322_PWM_BASE(x) + 0x00)
+#define MEC1322_PWM_OFF(x) REG32(MEC1322_PWM_BASE(x) + 0x04)
+#define MEC1322_PWM_CFG(x) REG32(MEC1322_PWM_BASE(x) + 0x08)
 
 /* ACPI */
-#define MEC1322_ACPI_EC_BASE(x)     (0x400f0c00 + (x) * 0x400)
+#define MEC1322_ACPI_EC_BASE(x) (0x400f0c00 + (x)*0x400)
 #define MEC1322_ACPI_EC_EC2OS(x, y) REG8(MEC1322_ACPI_EC_BASE(x) + 0x100 + (y))
-#define MEC1322_ACPI_EC_STATUS(x)   REG8(MEC1322_ACPI_EC_BASE(x) + 0x104)
+#define MEC1322_ACPI_EC_STATUS(x) REG8(MEC1322_ACPI_EC_BASE(x) + 0x104)
 #define MEC1322_ACPI_EC_BYTE_CTL(x) REG8(MEC1322_ACPI_EC_BASE(x) + 0x105)
 #define MEC1322_ACPI_EC_OS2EC(x, y) REG8(MEC1322_ACPI_EC_BASE(x) + 0x108 + (y))
 
-#define MEC1322_ACPI_PM_RT_BASE     0x400f1400
-#define MEC1322_ACPI_PM1_STS1       REG8(MEC1322_ACPI_PM_RT_BASE + 0x0)
-#define MEC1322_ACPI_PM1_STS2       REG8(MEC1322_ACPI_PM_RT_BASE + 0x1)
-#define MEC1322_ACPI_PM1_EN1        REG8(MEC1322_ACPI_PM_RT_BASE + 0x2)
-#define MEC1322_ACPI_PM1_EN2        REG8(MEC1322_ACPI_PM_RT_BASE + 0x3)
-#define MEC1322_ACPI_PM1_CTL1       REG8(MEC1322_ACPI_PM_RT_BASE + 0x4)
-#define MEC1322_ACPI_PM1_CTL2       REG8(MEC1322_ACPI_PM_RT_BASE + 0x5)
-#define MEC1322_ACPI_PM2_CTL1       REG8(MEC1322_ACPI_PM_RT_BASE + 0x6)
-#define MEC1322_ACPI_PM2_CTL2       REG8(MEC1322_ACPI_PM_RT_BASE + 0x7)
-#define MEC1322_ACPI_PM_EC_BASE     0x400f1500
-#define MEC1322_ACPI_PM_STS         REG8(MEC1322_ACPI_PM_EC_BASE + 0x10)
-
+#define MEC1322_ACPI_PM_RT_BASE 0x400f1400
+#define MEC1322_ACPI_PM1_STS1 REG8(MEC1322_ACPI_PM_RT_BASE + 0x0)
+#define MEC1322_ACPI_PM1_STS2 REG8(MEC1322_ACPI_PM_RT_BASE + 0x1)
+#define MEC1322_ACPI_PM1_EN1 REG8(MEC1322_ACPI_PM_RT_BASE + 0x2)
+#define MEC1322_ACPI_PM1_EN2 REG8(MEC1322_ACPI_PM_RT_BASE + 0x3)
+#define MEC1322_ACPI_PM1_CTL1 REG8(MEC1322_ACPI_PM_RT_BASE + 0x4)
+#define MEC1322_ACPI_PM1_CTL2 REG8(MEC1322_ACPI_PM_RT_BASE + 0x5)
+#define MEC1322_ACPI_PM2_CTL1 REG8(MEC1322_ACPI_PM_RT_BASE + 0x6)
+#define MEC1322_ACPI_PM2_CTL2 REG8(MEC1322_ACPI_PM_RT_BASE + 0x7)
+#define MEC1322_ACPI_PM_EC_BASE 0x400f1500
+#define MEC1322_ACPI_PM_STS REG8(MEC1322_ACPI_PM_EC_BASE + 0x10)
 
 /* 8042 */
-#define MEC1322_8042_BASE      0x400f0400
-#define MEC1322_8042_OBF_CLR   REG8(MEC1322_8042_BASE + 0x0)
-#define MEC1322_8042_H2E       REG8(MEC1322_8042_BASE + 0x100)
-#define MEC1322_8042_E2H       REG8(MEC1322_8042_BASE + 0x100)
-#define MEC1322_8042_STS       REG8(MEC1322_8042_BASE + 0x104)
-#define MEC1322_8042_KB_CTRL   REG8(MEC1322_8042_BASE + 0x108)
-#define MEC1322_8042_PCOBF     REG8(MEC1322_8042_BASE + 0x114)
-#define MEC1322_8042_ACT       REG8(MEC1322_8042_BASE + 0x330)
-
+#define MEC1322_8042_BASE 0x400f0400
+#define MEC1322_8042_OBF_CLR REG8(MEC1322_8042_BASE + 0x0)
+#define MEC1322_8042_H2E REG8(MEC1322_8042_BASE + 0x100)
+#define MEC1322_8042_E2H REG8(MEC1322_8042_BASE + 0x100)
+#define MEC1322_8042_STS REG8(MEC1322_8042_BASE + 0x104)
+#define MEC1322_8042_KB_CTRL REG8(MEC1322_8042_BASE + 0x108)
+#define MEC1322_8042_PCOBF REG8(MEC1322_8042_BASE + 0x114)
+#define MEC1322_8042_ACT REG8(MEC1322_8042_BASE + 0x330)
 
 /* FAN */
-#define MEC1322_FAN_BASE       0x4000a000
-#define MEC1322_FAN_SETTING    REG8(MEC1322_FAN_BASE + 0x0)
+#define MEC1322_FAN_BASE 0x4000a000
+#define MEC1322_FAN_SETTING REG8(MEC1322_FAN_BASE + 0x0)
 #define MEC1322_FAN_PWM_DIVIDE REG8(MEC1322_FAN_BASE + 0x1)
-#define MEC1322_FAN_CFG1       REG8(MEC1322_FAN_BASE + 0x2)
-#define MEC1322_FAN_CFG2       REG8(MEC1322_FAN_BASE + 0x3)
-#define MEC1322_FAN_GAIN       REG8(MEC1322_FAN_BASE + 0x5)
-#define MEC1322_FAN_SPIN_UP    REG8(MEC1322_FAN_BASE + 0x6)
-#define MEC1322_FAN_STEP       REG8(MEC1322_FAN_BASE + 0x7)
-#define MEC1322_FAN_MIN_DRV    REG8(MEC1322_FAN_BASE + 0x8)
-#define MEC1322_FAN_VALID_CNT  REG8(MEC1322_FAN_BASE + 0x9)
-#define MEC1322_FAN_DRV_FAIL   REG16(MEC1322_FAN_BASE + 0xa)
-#define MEC1322_FAN_TARGET     REG16(MEC1322_FAN_BASE + 0xc)
-#define MEC1322_FAN_READING    REG16(MEC1322_FAN_BASE + 0xe)
-#define MEC1322_FAN_BASE_FREQ  REG8(MEC1322_FAN_BASE + 0x10)
-#define MEC1322_FAN_STATUS     REG8(MEC1322_FAN_BASE + 0x11)
-
+#define MEC1322_FAN_CFG1 REG8(MEC1322_FAN_BASE + 0x2)
+#define MEC1322_FAN_CFG2 REG8(MEC1322_FAN_BASE + 0x3)
+#define MEC1322_FAN_GAIN REG8(MEC1322_FAN_BASE + 0x5)
+#define MEC1322_FAN_SPIN_UP REG8(MEC1322_FAN_BASE + 0x6)
+#define MEC1322_FAN_STEP REG8(MEC1322_FAN_BASE + 0x7)
+#define MEC1322_FAN_MIN_DRV REG8(MEC1322_FAN_BASE + 0x8)
+#define MEC1322_FAN_VALID_CNT REG8(MEC1322_FAN_BASE + 0x9)
+#define MEC1322_FAN_DRV_FAIL REG16(MEC1322_FAN_BASE + 0xa)
+#define MEC1322_FAN_TARGET REG16(MEC1322_FAN_BASE + 0xc)
+#define MEC1322_FAN_READING REG16(MEC1322_FAN_BASE + 0xe)
+#define MEC1322_FAN_BASE_FREQ REG8(MEC1322_FAN_BASE + 0x10)
+#define MEC1322_FAN_STATUS REG8(MEC1322_FAN_BASE + 0x11)
 
 /* I2C */
-#define MEC1322_I2C0_BASE      0x40001800
-#define MEC1322_I2C1_BASE      0x4000ac00
-#define MEC1322_I2C2_BASE      0x4000b000
-#define MEC1322_I2C3_BASE      0x4000b400
-#define MEC1322_I2C_BASESEP    0x00000400
+#define MEC1322_I2C0_BASE 0x40001800
+#define MEC1322_I2C1_BASE 0x4000ac00
+#define MEC1322_I2C2_BASE 0x4000b000
+#define MEC1322_I2C3_BASE 0x4000b400
+#define MEC1322_I2C_BASESEP 0x00000400
 #define MEC1322_I2C_ADDR(controller, offset) \
-	(offset + (controller == 0 ? MEC1322_I2C0_BASE : \
-		   MEC1322_I2C1_BASE + MEC1322_I2C_BASESEP * (controller - 1)))
+	(offset +                            \
+	 (controller == 0 ?                  \
+		  MEC1322_I2C0_BASE :        \
+		  MEC1322_I2C1_BASE + MEC1322_I2C_BASESEP * (controller - 1)))
 
 /*
  * MEC1322 has five ports distributed among four controllers. Locking must
  * occur by-controller (not by-port).
  */
 enum mec1322_i2c_port {
-	MEC1322_I2C0_0 = 0,      /* Controller 0, port 0 */
-	MEC1322_I2C0_1 = 1,      /* Controller 0, port 1 */
-	MEC1322_I2C1   = 2,      /* Controller 1 */
-	MEC1322_I2C2   = 3,      /* Controller 2 */
-	MEC1322_I2C3   = 4,      /* Controller 3 */
+	MEC1322_I2C0_0 = 0, /* Controller 0, port 0 */
+	MEC1322_I2C0_1 = 1, /* Controller 0, port 1 */
+	MEC1322_I2C1 = 2, /* Controller 1 */
+	MEC1322_I2C2 = 3, /* Controller 2 */
+	MEC1322_I2C3 = 4, /* Controller 3 */
 	MEC1322_I2C_PORT_COUNT,
 };
 
-#define MEC1322_I2C_CTRL(ctrl)          REG8(MEC1322_I2C_ADDR(ctrl, 0x0))
-#define MEC1322_I2C_STATUS(ctrl)        REG8(MEC1322_I2C_ADDR(ctrl, 0x0))
-#define MEC1322_I2C_OWN_ADDR(ctrl)      REG16(MEC1322_I2C_ADDR(ctrl, 0x4))
-#define MEC1322_I2C_DATA(ctrl)          REG8(MEC1322_I2C_ADDR(ctrl, 0x8))
-#define MEC1322_I2C_MASTER_CMD(ctrl)    REG32(MEC1322_I2C_ADDR(ctrl, 0xc))
-#define MEC1322_I2C_SLAVE_CMD(ctrl)     REG32(MEC1322_I2C_ADDR(ctrl, 0x10))
-#define MEC1322_I2C_PEC(ctrl)           REG8(MEC1322_I2C_ADDR(ctrl, 0x14))
-#define MEC1322_I2C_DATA_TIM_2(ctrl)    REG8(MEC1322_I2C_ADDR(ctrl, 0x18))
-#define MEC1322_I2C_COMPLETE(ctrl)      REG32(MEC1322_I2C_ADDR(ctrl, 0x20))
-#define MEC1322_I2C_IDLE_SCALE(ctrl)    REG32(MEC1322_I2C_ADDR(ctrl, 0x24))
-#define MEC1322_I2C_CONFIG(ctrl)        REG32(MEC1322_I2C_ADDR(ctrl, 0x28))
-#define MEC1322_I2C_BUS_CLK(ctrl)       REG16(MEC1322_I2C_ADDR(ctrl, 0x2c))
-#define MEC1322_I2C_BLK_ID(ctrl)        REG8(MEC1322_I2C_ADDR(ctrl, 0x30))
-#define MEC1322_I2C_REV(ctrl)           REG8(MEC1322_I2C_ADDR(ctrl, 0x34))
-#define MEC1322_I2C_BB_CTRL(ctrl)       REG8(MEC1322_I2C_ADDR(ctrl, 0x38))
-#define MEC1322_I2C_DATA_TIM(ctrl)      REG32(MEC1322_I2C_ADDR(ctrl, 0x40))
-#define MEC1322_I2C_TOUT_SCALE(ctrl)    REG32(MEC1322_I2C_ADDR(ctrl, 0x44))
-#define MEC1322_I2C_SLAVE_TX_BUF(ctrl)  REG8(MEC1322_I2C_ADDR(ctrl, 0x48))
-#define MEC1322_I2C_SLAVE_RX_BUF(ctrl)  REG8(MEC1322_I2C_ADDR(ctrl, 0x4c))
+#define MEC1322_I2C_CTRL(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x0))
+#define MEC1322_I2C_STATUS(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x0))
+#define MEC1322_I2C_OWN_ADDR(ctrl) REG16(MEC1322_I2C_ADDR(ctrl, 0x4))
+#define MEC1322_I2C_DATA(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x8))
+#define MEC1322_I2C_MASTER_CMD(ctrl) REG32(MEC1322_I2C_ADDR(ctrl, 0xc))
+#define MEC1322_I2C_SLAVE_CMD(ctrl) REG32(MEC1322_I2C_ADDR(ctrl, 0x10))
+#define MEC1322_I2C_PEC(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x14))
+#define MEC1322_I2C_DATA_TIM_2(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x18))
+#define MEC1322_I2C_COMPLETE(ctrl) REG32(MEC1322_I2C_ADDR(ctrl, 0x20))
+#define MEC1322_I2C_IDLE_SCALE(ctrl) REG32(MEC1322_I2C_ADDR(ctrl, 0x24))
+#define MEC1322_I2C_CONFIG(ctrl) REG32(MEC1322_I2C_ADDR(ctrl, 0x28))
+#define MEC1322_I2C_BUS_CLK(ctrl) REG16(MEC1322_I2C_ADDR(ctrl, 0x2c))
+#define MEC1322_I2C_BLK_ID(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x30))
+#define MEC1322_I2C_REV(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x34))
+#define MEC1322_I2C_BB_CTRL(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x38))
+#define MEC1322_I2C_DATA_TIM(ctrl) REG32(MEC1322_I2C_ADDR(ctrl, 0x40))
+#define MEC1322_I2C_TOUT_SCALE(ctrl) REG32(MEC1322_I2C_ADDR(ctrl, 0x44))
+#define MEC1322_I2C_SLAVE_TX_BUF(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x48))
+#define MEC1322_I2C_SLAVE_RX_BUF(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x4c))
 #define MEC1322_I2C_MASTER_TX_BUF(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x50))
 #define MEC1322_I2C_MASTER_RX_BUF(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x54))
 
-
 /* Keyboard scan matrix */
-#define MEC1322_KS_BASE        0x40009c00
-#define MEC1322_KS_KSO_SEL     REG32(MEC1322_KS_BASE + 0x4)
-#define MEC1322_KS_KSI_INPUT   REG32(MEC1322_KS_BASE + 0x8)
-#define MEC1322_KS_KSI_STATUS  REG32(MEC1322_KS_BASE + 0xc)
-#define MEC1322_KS_KSI_INT_EN  REG32(MEC1322_KS_BASE + 0x10)
-#define MEC1322_KS_EXT_CTRL    REG32(MEC1322_KS_BASE + 0x14)
-
+#define MEC1322_KS_BASE 0x40009c00
+#define MEC1322_KS_KSO_SEL REG32(MEC1322_KS_BASE + 0x4)
+#define MEC1322_KS_KSI_INPUT REG32(MEC1322_KS_BASE + 0x8)
+#define MEC1322_KS_KSI_STATUS REG32(MEC1322_KS_BASE + 0xc)
+#define MEC1322_KS_KSI_INT_EN REG32(MEC1322_KS_BASE + 0x10)
+#define MEC1322_KS_EXT_CTRL REG32(MEC1322_KS_BASE + 0x14)
 
 /* ADC */
-#define MEC1322_ADC_BASE       0x40007c00
-#define MEC1322_ADC_CTRL       REG32(MEC1322_ADC_BASE + 0x0)
-#define MEC1322_ADC_DELAY      REG32(MEC1322_ADC_BASE + 0x4)
-#define MEC1322_ADC_STS        REG32(MEC1322_ADC_BASE + 0x8)
-#define MEC1322_ADC_SINGLE     REG32(MEC1322_ADC_BASE + 0xc)
-#define MEC1322_ADC_REPEAT     REG32(MEC1322_ADC_BASE + 0x10)
-#define MEC1322_ADC_READ(x)    REG32(MEC1322_ADC_BASE + 0x14 + (x) * 0x4)
-
+#define MEC1322_ADC_BASE 0x40007c00
+#define MEC1322_ADC_CTRL REG32(MEC1322_ADC_BASE + 0x0)
+#define MEC1322_ADC_DELAY REG32(MEC1322_ADC_BASE + 0x4)
+#define MEC1322_ADC_STS REG32(MEC1322_ADC_BASE + 0x8)
+#define MEC1322_ADC_SINGLE REG32(MEC1322_ADC_BASE + 0xc)
+#define MEC1322_ADC_REPEAT REG32(MEC1322_ADC_BASE + 0x10)
+#define MEC1322_ADC_READ(x) REG32(MEC1322_ADC_BASE + 0x14 + (x)*0x4)
 
 /* Hibernation timer */
-#define MEC1322_HTIMER_BASE    0x40009800
+#define MEC1322_HTIMER_BASE 0x40009800
 #define MEC1322_HTIMER_PRELOAD REG16(MEC1322_HTIMER_BASE + 0x0)
 #define MEC1322_HTIMER_CONTROL REG16(MEC1322_HTIMER_BASE + 0x4)
-#define MEC1322_HTIMER_COUNT   REG16(MEC1322_HTIMER_BASE + 0x8)
-
+#define MEC1322_HTIMER_COUNT REG16(MEC1322_HTIMER_BASE + 0x8)
 
 /* SPI */
 #define MEC1322_SPI_BASE(port) (0x40009400 + 0x80 * (port))
-#define MEC1322_SPI_AR(port)   REG8(MEC1322_SPI_BASE(port) + 0x00)
-#define MEC1322_SPI_CR(port)   REG8(MEC1322_SPI_BASE(port) + 0x04)
-#define MEC1322_SPI_SR(port)   REG8(MEC1322_SPI_BASE(port) + 0x08)
-#define MEC1322_SPI_TD(port)   REG8(MEC1322_SPI_BASE(port) + 0x0c)
-#define MEC1322_SPI_RD(port)   REG8(MEC1322_SPI_BASE(port) + 0x10)
-#define MEC1322_SPI_CC(port)   REG8(MEC1322_SPI_BASE(port) + 0x14)
-#define MEC1322_SPI_CG(port)   REG8(MEC1322_SPI_BASE(port) + 0x18)
-
+#define MEC1322_SPI_AR(port) REG8(MEC1322_SPI_BASE(port) + 0x00)
+#define MEC1322_SPI_CR(port) REG8(MEC1322_SPI_BASE(port) + 0x04)
+#define MEC1322_SPI_SR(port) REG8(MEC1322_SPI_BASE(port) + 0x08)
+#define MEC1322_SPI_TD(port) REG8(MEC1322_SPI_BASE(port) + 0x0c)
+#define MEC1322_SPI_RD(port) REG8(MEC1322_SPI_BASE(port) + 0x10)
+#define MEC1322_SPI_CC(port) REG8(MEC1322_SPI_BASE(port) + 0x14)
+#define MEC1322_SPI_CG(port) REG8(MEC1322_SPI_BASE(port) + 0x18)
 
 /* DMA */
-#define MEC1322_DMA_BASE            0x40002400
+#define MEC1322_DMA_BASE 0x40002400
 
 /*
  * Available DMA channels.
@@ -367,31 +351,31 @@ enum mec1322_i2c_port {
  */
 enum dma_channel {
 	/* Channel numbers */
-	MEC1322_DMAC_I2C0_SLAVE =  0,
+	MEC1322_DMAC_I2C0_SLAVE = 0,
 	MEC1322_DMAC_I2C0_MASTER = 1,
-	MEC1322_DMAC_I2C1_SLAVE =  2,
+	MEC1322_DMAC_I2C1_SLAVE = 2,
 	MEC1322_DMAC_I2C1_MASTER = 3,
-	MEC1322_DMAC_I2C2_SLAVE =  4,
+	MEC1322_DMAC_I2C2_SLAVE = 4,
 	MEC1322_DMAC_I2C2_MASTER = 5,
-	MEC1322_DMAC_I2C3_SLAVE =  6,
+	MEC1322_DMAC_I2C3_SLAVE = 6,
 	MEC1322_DMAC_I2C3_MASTER = 7,
-	MEC1322_DMAC_SPI0_TX =     8,
-	MEC1322_DMAC_SPI0_RX =     9,
-	MEC1322_DMAC_SPI1_TX =    10,
-	MEC1322_DMAC_SPI1_RX =    11,
+	MEC1322_DMAC_SPI0_TX = 8,
+	MEC1322_DMAC_SPI0_RX = 9,
+	MEC1322_DMAC_SPI1_TX = 10,
+	MEC1322_DMAC_SPI1_RX = 11,
 
 	/* Channel count */
-	MEC1322_DMAC_COUNT =      12,
+	MEC1322_DMAC_COUNT = 12,
 };
 
 /* Registers for a single channel of the DMA controller */
 struct mec1322_dma_chan {
-	uint32_t act;         /* Activate */
-	uint32_t mem_start;   /* Memory start address */
-	uint32_t mem_end;     /* Memory end address */
-	uint32_t dev;         /* Device address */
-	uint32_t ctrl;        /* Control */
-	uint32_t int_status;  /* Interrupt status */
+	uint32_t act; /* Activate */
+	uint32_t mem_start; /* Memory start address */
+	uint32_t mem_end; /* Memory end address */
+	uint32_t dev; /* Device address */
+	uint32_t ctrl; /* Control */
+	uint32_t int_status; /* Interrupt status */
 	uint32_t int_enabled; /* Interrupt enabled */
 	uint32_t pad;
 };
@@ -416,87 +400,86 @@ typedef volatile struct mec1322_dma_regs mec1322_dma_regs_t;
 #define MEC1322_DMA_REGS ((mec1322_dma_regs_t *)MEC1322_DMA_BASE)
 
 /* Bits for DMA channel regs */
-#define MEC1322_DMA_ACT_EN		BIT(0)
-#define MEC1322_DMA_XFER_SIZE(x)	((x) << 20)
-#define MEC1322_DMA_INC_DEV		BIT(17)
-#define MEC1322_DMA_INC_MEM		BIT(16)
-#define MEC1322_DMA_DEV(x)		((x) << 9)
-#define MEC1322_DMA_TO_DEV		BIT(8)
-#define MEC1322_DMA_DONE		BIT(2)
-#define MEC1322_DMA_RUN			BIT(0)
-
+#define MEC1322_DMA_ACT_EN BIT(0)
+#define MEC1322_DMA_XFER_SIZE(x) ((x) << 20)
+#define MEC1322_DMA_INC_DEV BIT(17)
+#define MEC1322_DMA_INC_MEM BIT(16)
+#define MEC1322_DMA_DEV(x) ((x) << 9)
+#define MEC1322_DMA_TO_DEV BIT(8)
+#define MEC1322_DMA_DONE BIT(2)
+#define MEC1322_DMA_RUN BIT(0)
 
 /* IRQ Numbers */
-#define MEC1322_IRQ_I2C_0        0
-#define MEC1322_IRQ_I2C_1        1
-#define MEC1322_IRQ_I2C_2        2
-#define MEC1322_IRQ_I2C_3        3
-#define MEC1322_IRQ_DMA_0        4
-#define MEC1322_IRQ_DMA_1        5
-#define MEC1322_IRQ_DMA_2        6
-#define MEC1322_IRQ_DMA_3        7
-#define MEC1322_IRQ_DMA_4        8
-#define MEC1322_IRQ_DMA_5        9
-#define MEC1322_IRQ_DMA_6        10
-#define MEC1322_IRQ_DMA_7        11
-#define MEC1322_IRQ_LPC          12
-#define MEC1322_IRQ_UART         13
-#define MEC1322_IRQ_EMI          14
-#define MEC1322_IRQ_ACPIEC0_IBF  15
-#define MEC1322_IRQ_ACPIEC0_OBF  16
-#define MEC1322_IRQ_ACPIEC1_IBF  17
-#define MEC1322_IRQ_ACPIEC1_OBF  18
-#define MEC1322_IRQ_ACPIPM1_CTL  19
-#define MEC1322_IRQ_ACPIPM1_EN   20
-#define MEC1322_IRQ_ACPIPM1_STS  21
-#define MEC1322_IRQ_8042EM_OBF   22
-#define MEC1322_IRQ_8042EM_IBF   23
-#define MEC1322_IRQ_MAILBOX      24
-#define MEC1322_IRQ_PECI_HOST    25
-#define MEC1322_IRQ_TACH_0       26
-#define MEC1322_IRQ_TACH_1       27
-#define MEC1322_IRQ_ADC_SNGL     28
-#define MEC1322_IRQ_ADC_RPT      29
-#define MEC1322_IRQ_PS2_0        32
-#define MEC1322_IRQ_PS2_1        33
-#define MEC1322_IRQ_PS2_2        34
-#define MEC1322_IRQ_PS2_3        35
-#define MEC1322_IRQ_SPI0_TX      36
-#define MEC1322_IRQ_SPI0_RX      37
-#define MEC1322_IRQ_HTIMER       38
-#define MEC1322_IRQ_KSC_INT      39
+#define MEC1322_IRQ_I2C_0 0
+#define MEC1322_IRQ_I2C_1 1
+#define MEC1322_IRQ_I2C_2 2
+#define MEC1322_IRQ_I2C_3 3
+#define MEC1322_IRQ_DMA_0 4
+#define MEC1322_IRQ_DMA_1 5
+#define MEC1322_IRQ_DMA_2 6
+#define MEC1322_IRQ_DMA_3 7
+#define MEC1322_IRQ_DMA_4 8
+#define MEC1322_IRQ_DMA_5 9
+#define MEC1322_IRQ_DMA_6 10
+#define MEC1322_IRQ_DMA_7 11
+#define MEC1322_IRQ_LPC 12
+#define MEC1322_IRQ_UART 13
+#define MEC1322_IRQ_EMI 14
+#define MEC1322_IRQ_ACPIEC0_IBF 15
+#define MEC1322_IRQ_ACPIEC0_OBF 16
+#define MEC1322_IRQ_ACPIEC1_IBF 17
+#define MEC1322_IRQ_ACPIEC1_OBF 18
+#define MEC1322_IRQ_ACPIPM1_CTL 19
+#define MEC1322_IRQ_ACPIPM1_EN 20
+#define MEC1322_IRQ_ACPIPM1_STS 21
+#define MEC1322_IRQ_8042EM_OBF 22
+#define MEC1322_IRQ_8042EM_IBF 23
+#define MEC1322_IRQ_MAILBOX 24
+#define MEC1322_IRQ_PECI_HOST 25
+#define MEC1322_IRQ_TACH_0 26
+#define MEC1322_IRQ_TACH_1 27
+#define MEC1322_IRQ_ADC_SNGL 28
+#define MEC1322_IRQ_ADC_RPT 29
+#define MEC1322_IRQ_PS2_0 32
+#define MEC1322_IRQ_PS2_1 33
+#define MEC1322_IRQ_PS2_2 34
+#define MEC1322_IRQ_PS2_3 35
+#define MEC1322_IRQ_SPI0_TX 36
+#define MEC1322_IRQ_SPI0_RX 37
+#define MEC1322_IRQ_HTIMER 38
+#define MEC1322_IRQ_KSC_INT 39
 #define MEC1322_IRQ_MAILBOX_DATA 40
-#define MEC1322_IRQ_TIMER16_0    49
-#define MEC1322_IRQ_TIMER16_1    50
-#define MEC1322_IRQ_TIMER16_2    51
-#define MEC1322_IRQ_TIMER16_3    52
-#define MEC1322_IRQ_TIMER32_0    53
-#define MEC1322_IRQ_TIMER32_1    54
-#define MEC1322_IRQ_SPI1_TX      55
-#define MEC1322_IRQ_SPI1_RX      56
-#define MEC1322_IRQ_GIRQ8        57
-#define MEC1322_IRQ_GIRQ9        58
-#define MEC1322_IRQ_GIRQ10       59
-#define MEC1322_IRQ_GIRQ11       60
-#define MEC1322_IRQ_GIRQ12       61
-#define MEC1322_IRQ_GIRQ13       62
-#define MEC1322_IRQ_GIRQ14       63
-#define MEC1322_IRQ_GIRQ15       64
-#define MEC1322_IRQ_GIRQ16       65
-#define MEC1322_IRQ_GIRQ17       66
-#define MEC1322_IRQ_GIRQ18       67
-#define MEC1322_IRQ_GIRQ19       68
-#define MEC1322_IRQ_GIRQ20       69
-#define MEC1322_IRQ_GIRQ21       70
-#define MEC1322_IRQ_GIRQ22       71
-#define MEC1322_IRQ_GIRQ23       72
-#define MEC1322_IRQ_DMA_8        81
-#define MEC1322_IRQ_DMA_9        82
-#define MEC1322_IRQ_DMA_10       83
-#define MEC1322_IRQ_DMA_11       84
-#define MEC1322_IRQ_PWM_WDT3     85
-#define MEC1322_IRQ_RTC          91
-#define MEC1322_IRQ_RTC_ALARM    92
+#define MEC1322_IRQ_TIMER16_0 49
+#define MEC1322_IRQ_TIMER16_1 50
+#define MEC1322_IRQ_TIMER16_2 51
+#define MEC1322_IRQ_TIMER16_3 52
+#define MEC1322_IRQ_TIMER32_0 53
+#define MEC1322_IRQ_TIMER32_1 54
+#define MEC1322_IRQ_SPI1_TX 55
+#define MEC1322_IRQ_SPI1_RX 56
+#define MEC1322_IRQ_GIRQ8 57
+#define MEC1322_IRQ_GIRQ9 58
+#define MEC1322_IRQ_GIRQ10 59
+#define MEC1322_IRQ_GIRQ11 60
+#define MEC1322_IRQ_GIRQ12 61
+#define MEC1322_IRQ_GIRQ13 62
+#define MEC1322_IRQ_GIRQ14 63
+#define MEC1322_IRQ_GIRQ15 64
+#define MEC1322_IRQ_GIRQ16 65
+#define MEC1322_IRQ_GIRQ17 66
+#define MEC1322_IRQ_GIRQ18 67
+#define MEC1322_IRQ_GIRQ19 68
+#define MEC1322_IRQ_GIRQ20 69
+#define MEC1322_IRQ_GIRQ21 70
+#define MEC1322_IRQ_GIRQ22 71
+#define MEC1322_IRQ_GIRQ23 72
+#define MEC1322_IRQ_DMA_8 81
+#define MEC1322_IRQ_DMA_9 82
+#define MEC1322_IRQ_DMA_10 83
+#define MEC1322_IRQ_DMA_11 84
+#define MEC1322_IRQ_PWM_WDT3 85
+#define MEC1322_IRQ_RTC 91
+#define MEC1322_IRQ_RTC_ALARM 92
 
 /* Wake pin definitions, defined at board-level */
 #ifndef CONFIG_HIBERNATE_WAKE_PINS_DYNAMIC
diff --git a/chip/mec1322/spi.c b/chip/mec1322/spi.c
index 5cc25b8089..bf3c7a9fb5 100644
--- a/chip/mec1322/spi.c
+++ b/chip/mec1322/spi.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,12 +17,12 @@
 #include "task.h"
 
 #define CPUTS(outstr) cputs(CC_SPI, outstr)
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SPI, format, ##args)
 
 #define SPI_BYTE_TRANSFER_TIMEOUT_US (3 * MSEC)
 #define SPI_BYTE_TRANSFER_POLL_INTERVAL_US 100
 
-#define SPI_DMA_CHANNEL(port) (MEC1322_DMAC_SPI0_RX + (port) * 2)
+#define SPI_DMA_CHANNEL(port) (MEC1322_DMAC_SPI0_RX + (port)*2)
 
 /* only regular image needs mutex, LFW does not have scheduling */
 /* TODO: Move SPI locking to common code */
@@ -31,16 +31,10 @@ static struct mutex spi_mutex;
 #endif
 
 static const struct dma_option spi_rx_option[] = {
-	{
-		SPI_DMA_CHANNEL(0),
-		(void *)&MEC1322_SPI_RD(0),
-		MEC1322_DMA_XFER_SIZE(1)
-	},
-	{
-		SPI_DMA_CHANNEL(1),
-		(void *)&MEC1322_SPI_RD(1),
-		MEC1322_DMA_XFER_SIZE(1)
-	},
+	{ SPI_DMA_CHANNEL(0), (void *)&MEC1322_SPI_RD(0),
+	  MEC1322_DMA_XFER_SIZE(1) },
+	{ SPI_DMA_CHANNEL(1), (void *)&MEC1322_SPI_RD(1),
+	  MEC1322_DMA_XFER_SIZE(1) },
 };
 
 static int wait_byte(const int port)
@@ -74,8 +68,8 @@ static int spi_tx(const int port, const uint8_t *txdata, int txlen)
 }
 
 int spi_transaction_async(const struct spi_device_t *spi_device,
-			  const uint8_t *txdata, int txlen,
-			  uint8_t *rxdata, int rxlen)
+			  const uint8_t *txdata, int txlen, uint8_t *rxdata,
+			  int rxlen)
 {
 	int port = spi_device->port;
 	int ret = EC_SUCCESS;
@@ -129,8 +123,8 @@ int spi_transaction_flush(const struct spi_device_t *spi_device)
 }
 
 int spi_transaction(const struct spi_device_t *spi_device,
-		    const uint8_t *txdata, int txlen,
-		    uint8_t *rxdata, int rxlen)
+		    const uint8_t *txdata, int txlen, uint8_t *rxdata,
+		    int rxlen)
 {
 	int ret;
 
diff --git a/chip/mec1322/system.c b/chip/mec1322/system.c
index b672f72d2d..13fc2d9f81 100644
--- a/chip/mec1322/system.c
+++ b/chip/mec1322/system.c
@@ -1,10 +1,11 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* System module for Chrome EC : MEC1322 hardware specific implementation */
 
+#include "builtin/assert.h"
 #include "clock.h"
 #include "common.h"
 #include "console.h"
@@ -23,38 +24,37 @@
 
 /* Indices for hibernate data registers (RAM backed by VBAT) */
 enum hibdata_index {
-	HIBDATA_INDEX_SCRATCHPAD = 0,    /* General-purpose scratchpad */
+	HIBDATA_INDEX_SCRATCHPAD = 0, /* General-purpose scratchpad */
 	HIBDATA_INDEX_SAVED_RESET_FLAGS, /* Saved reset flags */
-	HIBDATA_INDEX_PD0,               /* USB-PD0 saved port state */
-	HIBDATA_INDEX_PD1,               /* USB-PD1 saved port state */
-	HIBDATA_INDEX_PD2,               /* USB-PD2 saved port state */
+	HIBDATA_INDEX_PD0, /* USB-PD0 saved port state */
+	HIBDATA_INDEX_PD1, /* USB-PD1 saved port state */
+	HIBDATA_INDEX_PD2, /* USB-PD2 saved port state */
 };
 
 static void check_reset_cause(void)
 {
 	uint32_t status = MEC1322_VBAT_STS;
 	uint32_t flags = 0;
-	uint32_t rst_sts = MEC1322_PCR_CHIP_PWR_RST &
-				(MEC1322_PWR_RST_STS_VCC1 |
-				MEC1322_PWR_RST_STS_VBAT);
+	uint32_t rst_sts =
+		MEC1322_PCR_CHIP_PWR_RST &
+		(MEC1322_PWR_RST_STS_VCC1 | MEC1322_PWR_RST_STS_VBAT);
 
 	/* Clear the reset causes now that we've read them */
 	MEC1322_VBAT_STS |= status;
 	MEC1322_PCR_CHIP_PWR_RST |= rst_sts;
 
 	/*
-	* BIT[6] determine VCC1 reset
-	*/
+	 * BIT[6] determine VCC1 reset
+	 */
 	if (rst_sts & MEC1322_PWR_RST_STS_VCC1)
 		flags |= EC_RESET_FLAG_RESET_PIN;
 
-
 	flags |= MEC1322_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS);
 	MEC1322_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS) = 0;
 
-	if ((status & MEC1322_VBAT_STS_WDT) && !(flags & (EC_RESET_FLAG_SOFT |
-					    EC_RESET_FLAG_HARD |
-					    EC_RESET_FLAG_HIBERNATE)))
+	if ((status & MEC1322_VBAT_STS_WDT) &&
+	    !(flags & (EC_RESET_FLAG_SOFT | EC_RESET_FLAG_HARD |
+		       EC_RESET_FLAG_HIBERNATE)))
 		flags |= EC_RESET_FLAG_WATCHDOG;
 
 	system_set_reset_flags(flags);
@@ -64,18 +64,18 @@ int system_is_reboot_warm(void)
 {
 	uint32_t reset_flags;
 	/*
-	* Check reset cause here,
-	* gpio_pre_init is executed faster than system_pre_init
-	*/
+	 * Check reset cause here,
+	 * gpio_pre_init is executed faster than system_pre_init
+	 */
 	check_reset_cause();
 	reset_flags = system_get_reset_flags();
 
 	if ((reset_flags & EC_RESET_FLAG_RESET_PIN) ||
-		(reset_flags & EC_RESET_FLAG_POWER_ON) ||
-		(reset_flags & EC_RESET_FLAG_WATCHDOG) ||
-		(reset_flags & EC_RESET_FLAG_HARD) ||
-		(reset_flags & EC_RESET_FLAG_SOFT) ||
-		(reset_flags & EC_RESET_FLAG_HIBERNATE))
+	    (reset_flags & EC_RESET_FLAG_POWER_ON) ||
+	    (reset_flags & EC_RESET_FLAG_WATCHDOG) ||
+	    (reset_flags & EC_RESET_FLAG_HARD) ||
+	    (reset_flags & EC_RESET_FLAG_SOFT) ||
+	    (reset_flags & EC_RESET_FLAG_HIBERNATE))
 		return 0;
 	else
 		return 1;
@@ -105,8 +105,7 @@ uint32_t chip_read_reset_flags(void)
 	return MEC1322_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS);
 }
 
-noreturn
-void _system_reset(int flags, int wake_from_hibernate)
+noreturn void _system_reset(int flags, int wake_from_hibernate)
 {
 	uint32_t save_flags = 0;
 
@@ -355,7 +354,7 @@ void system_hibernate(uint32_t seconds, uint32_t microseconds)
 		}
 	}
 
-	asm("wfi");
+	cpu_enter_suspend_mode();
 
 	/* Use 48MHz clock to speed through wake-up */
 	MEC1322_PCR_PROC_CLK_CTL = 1;
@@ -381,14 +380,14 @@ enum ec_image system_get_shrspi_image_copy(void)
 
 uint32_t system_get_lfw_address(void)
 {
-	uint32_t * const lfw_vector =
-		(uint32_t * const)CONFIG_PROGRAM_MEMORY_BASE;
+	uint32_t *const lfw_vector =
+		(uint32_t *const)CONFIG_PROGRAM_MEMORY_BASE;
 
 	return *(lfw_vector + 1);
 }
 
 void system_set_image_copy(enum ec_image copy)
 {
-	MEC1322_VBAT_RAM(MEC1322_IMAGETYPE_IDX) = (copy == EC_IMAGE_RW) ?
-				EC_IMAGE_RW : EC_IMAGE_RO;
+	MEC1322_VBAT_RAM(MEC1322_IMAGETYPE_IDX) =
+		(copy == EC_IMAGE_RW) ? EC_IMAGE_RW : EC_IMAGE_RO;
 }
diff --git a/chip/mec1322/uart.c b/chip/mec1322/uart.c
index 9118168dcd..a913cf36ab 100644
--- a/chip/mec1322/uart.c
+++ b/chip/mec1322/uart.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -163,7 +163,7 @@ void uart_init(void)
 void uart_enter_dsleep(void)
 {
 	/* Disable the UART interrupt. */
-	task_disable_irq(MEC1322_IRQ_UART);  /* NVIC interrupt for UART=13 */
+	task_disable_irq(MEC1322_IRQ_UART); /* NVIC interrupt for UART=13 */
 
 	/*
 	 * Set the UART0 RX pin to be a GPIO-162(fixed pin) interrupt
@@ -175,13 +175,12 @@ void uart_enter_dsleep(void)
 	MEC1322_UART_ACT &= ~BIT(0);
 
 	/* Clear pending interrupts on GPIO_UART0_RX(GPIO162, girq=8, bit=18) */
-	MEC1322_INT_SOURCE(8) = (1<<18);
+	MEC1322_INT_SOURCE(8) = (1 << 18);
 
 	/* Enable GPIO interrupts on the UART0 RX pin. */
 	gpio_enable_interrupt(GPIO_UART0_RX);
 }
 
-
 void uart_exit_dsleep(void)
 {
 	/*
diff --git a/chip/mec1322/util/pack_ec.py b/chip/mec1322/util/pack_ec.py
index 9783ffb2d5..9062621c9a 100755
--- a/chip/mec1322/util/pack_ec.py
+++ b/chip/mec1322/util/pack_ec.py
@@ -1,12 +1,8 @@
 #!/usr/bin/env python3
 
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
+# Copyright 2013 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
 
 # A script to pack EC binary into SPI flash image for MEC1322
 # Based on MEC1322_ROM_Doc_Rev0.5.pdf.
@@ -21,228 +17,332 @@ import tempfile
 LOAD_ADDR = 0x100000
 HEADER_SIZE = 0x140
 SPI_CLOCK_LIST = [48, 24, 12, 8]
-SPI_READ_CMD_LIST = [0x3, 0xb, 0x3b]
+SPI_READ_CMD_LIST = [0x3, 0xB, 0x3B]
+
+CRC_TABLE = [
+    0x00,
+    0x07,
+    0x0E,
+    0x09,
+    0x1C,
+    0x1B,
+    0x12,
+    0x15,
+    0x38,
+    0x3F,
+    0x36,
+    0x31,
+    0x24,
+    0x23,
+    0x2A,
+    0x2D,
+]
 
-CRC_TABLE = [0x00, 0x07, 0x0e, 0x09, 0x1c, 0x1b, 0x12, 0x15,
-             0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d]
 
 def Crc8(crc, data):
-  """Update CRC8 value."""
-  for v in data:
-    crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v >> 4)]);
-    crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v & 0xf)]);
-  return crc ^ 0x55
+    """Update CRC8 value."""
+    for v in data:
+        crc = ((crc << 4) & 0xFF) ^ (CRC_TABLE[(crc >> 4) ^ (v >> 4)])
+        crc = ((crc << 4) & 0xFF) ^ (CRC_TABLE[(crc >> 4) ^ (v & 0xF)])
+    return crc ^ 0x55
+
 
 def GetEntryPoint(payload_file):
-  """Read entry point from payload EC image."""
-  with open(payload_file, 'rb') as f:
-    f.seek(4)
-    s = f.read(4)
-  return struct.unpack('<I', s)[0]
-
-def GetPayloadFromOffset(payload_file,offset):
-  """Read payload and pad it to 64-byte aligned."""
-  with open(payload_file, 'rb') as f:
-    f.seek(offset)
-    payload = bytearray(f.read())
-  rem_len = len(payload) % 64
-  if rem_len:
-    payload += b'\0' * (64 - rem_len)
-  return payload
+    """Read entry point from payload EC image."""
+    with open(payload_file, "rb") as f:
+        f.seek(4)
+        s = f.read(4)
+    return struct.unpack("<I", s)[0]
+
+
+def GetPayloadFromOffset(payload_file, offset):
+    """Read payload and pad it to 64-byte aligned."""
+    with open(payload_file, "rb") as f:
+        f.seek(offset)
+        payload = bytearray(f.read())
+    rem_len = len(payload) % 64
+    if rem_len:
+        payload += b"\0" * (64 - rem_len)
+    return payload
+
 
 def GetPayload(payload_file):
-  """Read payload and pad it to 64-byte aligned."""
-  return GetPayloadFromOffset(payload_file, 0)
+    """Read payload and pad it to 64-byte aligned."""
+    return GetPayloadFromOffset(payload_file, 0)
+
 
 def GetPublicKey(pem_file):
-  """Extract public exponent and modulus from PEM file."""
-  result = subprocess.run(['openssl', 'rsa', '-in', pem_file, '-text',
-                           '-noout'], stdout=subprocess.PIPE, encoding='utf-8')
-  modulus_raw = []
-  in_modulus = False
-  for line in result.stdout.splitlines():
-    if line.startswith('modulus'):
-      in_modulus = True
-    elif not line.startswith(' '):
-      in_modulus = False
-    elif in_modulus:
-      modulus_raw.extend(line.strip().strip(':').split(':'))
-    if line.startswith('publicExponent'):
-      exp = int(line.split(' ')[1], 10)
-  modulus_raw.reverse()
-  modulus = bytearray((int(x, 16) for x in modulus_raw[:256]))
-  return struct.pack('<Q', exp), modulus
+    """Extract public exponent and modulus from PEM file."""
+    result = subprocess.run(
+        ["openssl", "rsa", "-in", pem_file, "-text", "-noout"],
+        stdout=subprocess.PIPE,
+        encoding="utf-8",
+    )
+    modulus_raw = []
+    in_modulus = False
+    for line in result.stdout.splitlines():
+        if line.startswith("modulus"):
+            in_modulus = True
+        elif not line.startswith(" "):
+            in_modulus = False
+        elif in_modulus:
+            modulus_raw.extend(line.strip().strip(":").split(":"))
+        if line.startswith("publicExponent"):
+            exp = int(line.split(" ")[1], 10)
+    modulus_raw.reverse()
+    modulus = bytearray((int(x, 16) for x in modulus_raw[:256]))
+    return struct.pack("<Q", exp), modulus
+
 
 def GetSpiClockParameter(args):
-  assert args.spi_clock in SPI_CLOCK_LIST, \
-         "Unsupported SPI clock speed %d MHz" % args.spi_clock
-  return SPI_CLOCK_LIST.index(args.spi_clock)
+    assert args.spi_clock in SPI_CLOCK_LIST, (
+        "Unsupported SPI clock speed %d MHz" % args.spi_clock
+    )
+    return SPI_CLOCK_LIST.index(args.spi_clock)
+
 
 def GetSpiReadCmdParameter(args):
-  assert args.spi_read_cmd in SPI_READ_CMD_LIST, \
-         "Unsupported SPI read command 0x%x" % args.spi_read_cmd
-  return SPI_READ_CMD_LIST.index(args.spi_read_cmd)
+    assert args.spi_read_cmd in SPI_READ_CMD_LIST, (
+        "Unsupported SPI read command 0x%x" % args.spi_read_cmd
+    )
+    return SPI_READ_CMD_LIST.index(args.spi_read_cmd)
+
 
 def PadZeroTo(data, size):
-  data.extend(b'\0' * (size - len(data)))
+    data.extend(b"\0" * (size - len(data)))
+
 
 def BuildHeader(args, payload_len, rorofile):
-  # Identifier and header version
-  header = bytearray(b'CSMS\0')
+    # Identifier and header version
+    header = bytearray(b"CSMS\0")
+
+    PadZeroTo(header, 0x6)
+    header.append(GetSpiClockParameter(args))
+    header.append(GetSpiReadCmdParameter(args))
 
-  PadZeroTo(header, 0x6)
-  header.append(GetSpiClockParameter(args))
-  header.append(GetSpiReadCmdParameter(args))
+    header.extend(struct.pack("<I", LOAD_ADDR))
+    header.extend(struct.pack("<I", GetEntryPoint(rorofile)))
+    header.append((payload_len >> 6) & 0xFF)
+    header.append((payload_len >> 14) & 0xFF)
+    PadZeroTo(header, 0x14)
+    header.extend(struct.pack("<I", args.payload_offset))
 
-  header.extend(struct.pack('<I', LOAD_ADDR))
-  header.extend(struct.pack('<I', GetEntryPoint(rorofile)))
-  header.append((payload_len >> 6) & 0xff)
-  header.append((payload_len >> 14) & 0xff)
-  PadZeroTo(header, 0x14)
-  header.extend(struct.pack('<I', args.payload_offset))
+    exp, modulus = GetPublicKey(args.payload_key)
+    PadZeroTo(header, 0x20)
+    header.extend(exp)
+    PadZeroTo(header, 0x30)
+    header.extend(modulus)
+    PadZeroTo(header, HEADER_SIZE)
 
-  exp, modulus = GetPublicKey(args.payload_key)
-  PadZeroTo(header, 0x20)
-  header.extend(exp)
-  PadZeroTo(header, 0x30)
-  header.extend(modulus)
-  PadZeroTo(header, HEADER_SIZE)
+    return header
 
-  return header
 
 def SignByteArray(data, pem_file):
-  hash_file = tempfile.mkstemp(prefix='pack_ec.')[1]
-  sign_file = tempfile.mkstemp(prefix='pack_ec.')[1]
-  try:
-      with open(hash_file, 'wb') as f:
-        hasher = hashlib.sha256()
-        hasher.update(data)
-        f.write(hasher.digest())
-      subprocess.run(['openssl', 'rsautl', '-sign', '-inkey', pem_file,
-                      '-keyform', 'PEM', '-in', hash_file, '-out', sign_file],
-                     check=True)
-      with open(sign_file, 'rb') as f:
-        signed = f.read()
-        return bytearray(reversed(signed))
-  finally:
-    os.remove(hash_file)
-    os.remove(sign_file)
+    hash_file = tempfile.mkstemp(prefix="pack_ec.")[1]
+    sign_file = tempfile.mkstemp(prefix="pack_ec.")[1]
+    try:
+        with open(hash_file, "wb") as f:
+            hasher = hashlib.sha256()
+            hasher.update(data)
+            f.write(hasher.digest())
+        subprocess.run(
+            [
+                "openssl",
+                "rsautl",
+                "-sign",
+                "-inkey",
+                pem_file,
+                "-keyform",
+                "PEM",
+                "-in",
+                hash_file,
+                "-out",
+                sign_file,
+            ],
+            check=True,
+        )
+        with open(sign_file, "rb") as f:
+            signed = f.read()
+            return bytearray(reversed(signed))
+    finally:
+        os.remove(hash_file)
+        os.remove(sign_file)
+
 
 def BuildTag(args):
-  tag = bytearray([(args.header_loc >> 8) & 0xff,
-                   (args.header_loc >> 16) & 0xff,
-                   (args.header_loc >> 24) & 0xff])
-  if args.chip_select != 0:
-    tag[2] |= 0x80
-  tag.append(Crc8(0, tag))
-  return tag
+    tag = bytearray(
+        [
+            (args.header_loc >> 8) & 0xFF,
+            (args.header_loc >> 16) & 0xFF,
+            (args.header_loc >> 24) & 0xFF,
+        ]
+    )
+    if args.chip_select != 0:
+        tag[2] |= 0x80
+    tag.append(Crc8(0, tag))
+    return tag
+
 
 def PacklfwRoImage(rorw_file, loader_file, image_size):
-  """TODO:Clean up to get rid of Temp file and just use memory
-  to save data"""
-  """Create a temp file with the
+    """TODO:Clean up to get rid of Temp file and just use memory
+    to save data"""
+    """Create a temp file with the
   first image_size bytes from the rorw file and the
   bytes from the loader_file appended
   return the filename"""
-  fo=tempfile.NamedTemporaryFile(delete=False) # Need to keep file around
-  with open(loader_file,'rb') as fin1:
-    pro = fin1.read()
-  fo.write(pro)
-  with open(rorw_file, 'rb') as fin:
-    ro = fin.read(image_size)
-  fo.write(ro)
-  fo.close()
-  return fo.name
+    fo = tempfile.NamedTemporaryFile(delete=False)  # Need to keep file around
+    with open(loader_file, "rb") as fin1:
+        pro = fin1.read()
+    fo.write(pro)
+    with open(rorw_file, "rb") as fin:
+        ro = fin.read(image_size)
+    fo.write(ro)
+    fo.close()
+    return fo.name
+
 
 def parseargs():
-  parser = argparse.ArgumentParser()
-  parser.add_argument("-i", "--input",
-                      help="EC binary to pack, usually ec.bin or ec.RO.flat.",
-                      metavar="EC_BIN", default="ec.bin")
-  parser.add_argument("-o", "--output",
-                      help="Output flash binary file",
-                      metavar="EC_SPI_FLASH", default="ec.packed.bin")
-  parser.add_argument("--header_key",
-                      help="PEM key file for signing header",
-                      default="rsakey_sign_header.pem")
-  parser.add_argument("--payload_key",
-                      help="PEM key file for signing payload",
-                      default="rsakey_sign_payload.pem")
-  parser.add_argument("--loader_file",
-                      help="EC loader binary",
-                      default="ecloader.bin")
-  parser.add_argument("-s", "--spi_size", type=int,
-                      help="Size of the SPI flash in MB",
-                      default=4)
-  parser.add_argument("-l", "--header_loc", type=int,
-                      help="Location of header in SPI flash",
-                      default=0x170000)
-  parser.add_argument("-p", "--payload_offset", type=int,
-                      help="The offset of payload from the header",
-                      default=0x240)
-  parser.add_argument("-r", "--rwpayload_loc", type=int,
-                      help="The offset of payload from the header",
-                      default=0x190000)
-  parser.add_argument("-z", "--romstart", type=int,
-                      help="The first location to output of the rom",
-                      default=0)
-  parser.add_argument("-c", "--chip_select", type=int,
-                      help="Chip select signal to use, either 0 or 1.",
-                      default=0)
-  parser.add_argument("--spi_clock", type=int,
-                      help="SPI clock speed. 8, 12, 24, or 48 MHz.",
-                      default=24)
-  parser.add_argument("--spi_read_cmd", type=int,
-                      help="SPI read command. 0x3, 0xB, or 0x3B.",
-                      default=0xb)
-  parser.add_argument("--image_size", type=int,
-                      help="Size of a single image.",
-                      default=(96 * 1024))
-  return parser.parse_args()
+    parser = argparse.ArgumentParser()
+    parser.add_argument(
+        "-i",
+        "--input",
+        help="EC binary to pack, usually ec.bin or ec.RO.flat.",
+        metavar="EC_BIN",
+        default="ec.bin",
+    )
+    parser.add_argument(
+        "-o",
+        "--output",
+        help="Output flash binary file",
+        metavar="EC_SPI_FLASH",
+        default="ec.packed.bin",
+    )
+    parser.add_argument(
+        "--header_key",
+        help="PEM key file for signing header",
+        default="rsakey_sign_header.pem",
+    )
+    parser.add_argument(
+        "--payload_key",
+        help="PEM key file for signing payload",
+        default="rsakey_sign_payload.pem",
+    )
+    parser.add_argument(
+        "--loader_file", help="EC loader binary", default="ecloader.bin"
+    )
+    parser.add_argument(
+        "-s",
+        "--spi_size",
+        type=int,
+        help="Size of the SPI flash in MB",
+        default=4,
+    )
+    parser.add_argument(
+        "-l",
+        "--header_loc",
+        type=int,
+        help="Location of header in SPI flash",
+        default=0x170000,
+    )
+    parser.add_argument(
+        "-p",
+        "--payload_offset",
+        type=int,
+        help="The offset of payload from the header",
+        default=0x240,
+    )
+    parser.add_argument(
+        "-r",
+        "--rwpayload_loc",
+        type=int,
+        help="The offset of payload from the header",
+        default=0x190000,
+    )
+    parser.add_argument(
+        "-z",
+        "--romstart",
+        type=int,
+        help="The first location to output of the rom",
+        default=0,
+    )
+    parser.add_argument(
+        "-c",
+        "--chip_select",
+        type=int,
+        help="Chip select signal to use, either 0 or 1.",
+        default=0,
+    )
+    parser.add_argument(
+        "--spi_clock",
+        type=int,
+        help="SPI clock speed. 8, 12, 24, or 48 MHz.",
+        default=24,
+    )
+    parser.add_argument(
+        "--spi_read_cmd",
+        type=int,
+        help="SPI read command. 0x3, 0xB, or 0x3B.",
+        default=0xB,
+    )
+    parser.add_argument(
+        "--image_size",
+        type=int,
+        help="Size of a single image.",
+        default=(96 * 1024),
+    )
+    return parser.parse_args()
+
 
 def main():
-  args = parseargs()
-
-  spi_size = args.spi_size * 1024
-  args.header_loc = spi_size - (128 * 1024)
-  args.rwpayload_loc = spi_size - (256 * 1024)
-  args.romstart = spi_size - (256 * 1024)
-
-  spi_list = []
-
-  rorofile=PacklfwRoImage(args.input, args.loader_file, args.image_size)
-  payload = GetPayload(rorofile)
-  payload_len = len(payload)
-  payload_signature = SignByteArray(payload, args.payload_key)
-  header = BuildHeader(args, payload_len, rorofile)
-  header_signature = SignByteArray(header, args.header_key)
-  tag = BuildTag(args)
-  # truncate the RW to 128k
-  payloadrw = GetPayloadFromOffset(args.input,args.image_size)[:128*1024]
-  os.remove(rorofile)           # clean up the temp file
-
-  spi_list.append((args.header_loc, header, "header"))
-  spi_list.append((args.header_loc + HEADER_SIZE, header_signature, "header_signature"))
-  spi_list.append((args.header_loc + args.payload_offset, payload, "payload"))
-  spi_list.append((args.header_loc + args.payload_offset + payload_len,
-                   payload_signature, "payload_signature"))
-  spi_list.append((spi_size - 256, tag, "tag"))
-  spi_list.append((args.rwpayload_loc, payloadrw, "payloadrw"))
-
-
-  spi_list = sorted(spi_list)
-
-  with open(args.output, 'wb') as f:
-    addr = args.romstart
-    for s in spi_list:
-      assert addr <= s[0]
-      if addr < s[0]:
-        f.write(b'\xff' * (s[0] - addr))
-        addr = s[0]
-      f.write(s[1])
-      addr += len(s[1])
-    if addr < spi_size:
-      f.write(b'\xff' * (spi_size - addr))
-
-if __name__ == '__main__':
-  main()
+    args = parseargs()
+
+    spi_size = args.spi_size * 1024
+    args.header_loc = spi_size - (128 * 1024)
+    args.rwpayload_loc = spi_size - (256 * 1024)
+    args.romstart = spi_size - (256 * 1024)
+
+    spi_list = []
+
+    rorofile = PacklfwRoImage(args.input, args.loader_file, args.image_size)
+    payload = GetPayload(rorofile)
+    payload_len = len(payload)
+    payload_signature = SignByteArray(payload, args.payload_key)
+    header = BuildHeader(args, payload_len, rorofile)
+    header_signature = SignByteArray(header, args.header_key)
+    tag = BuildTag(args)
+    # truncate the RW to 128k
+    payloadrw = GetPayloadFromOffset(args.input, args.image_size)[: 128 * 1024]
+    os.remove(rorofile)  # clean up the temp file
+
+    spi_list.append((args.header_loc, header, "header"))
+    spi_list.append(
+        (args.header_loc + HEADER_SIZE, header_signature, "header_signature")
+    )
+    spi_list.append((args.header_loc + args.payload_offset, payload, "payload"))
+    spi_list.append(
+        (
+            args.header_loc + args.payload_offset + payload_len,
+            payload_signature,
+            "payload_signature",
+        )
+    )
+    spi_list.append((spi_size - 256, tag, "tag"))
+    spi_list.append((args.rwpayload_loc, payloadrw, "payloadrw"))
+
+    spi_list = sorted(spi_list)
+
+    with open(args.output, "wb") as f:
+        addr = args.romstart
+        for s in spi_list:
+            assert addr <= s[0]
+            if addr < s[0]:
+                f.write(b"\xff" * (s[0] - addr))
+                addr = s[0]
+            f.write(s[1])
+            addr += len(s[1])
+        if addr < spi_size:
+            f.write(b"\xff" * (spi_size - addr))
+
+
+if __name__ == "__main__":
+    main()
diff --git a/chip/mec1322/watchdog.c b/chip/mec1322/watchdog.c
index ad93fb1240..a072e86e76 100644
--- a/chip/mec1322/watchdog.c
+++ b/chip/mec1322/watchdog.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -96,7 +96,8 @@ void IRQ_HANDLER(MEC1322_IRQ_TIMER16_0)(void)
 		     "b task_resched_if_needed\n");
 }
 const struct irq_priority __keep IRQ_PRIORITY(MEC1322_IRQ_TIMER16_0)
-	__attribute__((section(".rodata.irqprio")))
-		= {MEC1322_IRQ_TIMER16_0, 0}; /* put the watchdog at the
-						 highest priority */
+	__attribute__((section(".rodata.irqprio"))) = { MEC1322_IRQ_TIMER16_0,
+							0 }; /* put the watchdog
+								at the highest
+								priority */
 #endif
diff --git a/chip/mt_scp/build.mk b/chip/mt_scp/build.mk
index 42f61d3ff1..3f4baab128 100644
--- a/chip/mt_scp/build.mk
+++ b/chip/mt_scp/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/chip/mt_scp/config_chip.h b/chip/mt_scp/config_chip.h
index e9707f92a4..65d529f8e9 100644
--- a/chip/mt_scp/config_chip.h
+++ b/chip/mt_scp/config_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/mt_scp/mt818x/audio_codec_wov.c b/chip/mt_scp/mt818x/audio_codec_wov.c
index 0a4684f909..466494b53f 100644
--- a/chip/mt_scp/mt818x/audio_codec_wov.c
+++ b/chip/mt_scp/mt818x/audio_codec_wov.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -79,7 +79,7 @@ int32_t audio_codec_wov_read(void *buf, uint32_t count)
 	while (count-- && wov_fifo_level()) {
 		if (IS_ENABLED(CONFIG_AUDIO_CODEC_DMIC_SOFTWARE_GAIN))
 			*out++ = audio_codec_s16_scale_and_clip(
-					SCP_VIF_FIFO_DATA, gain);
+				SCP_VIF_FIFO_DATA, gain);
 		else
 			*out++ = SCP_VIF_FIFO_DATA;
 	}
diff --git a/chip/mt_scp/mt818x/build.mk b/chip/mt_scp/mt818x/build.mk
index e9f77a2833..39b1bce7dc 100644
--- a/chip/mt_scp/mt818x/build.mk
+++ b/chip/mt_scp/mt818x/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/chip/mt_scp/mt818x/clock_chip.h b/chip/mt_scp/mt818x/clock_chip.h
index 4ef02072e4..6568999176 100644
--- a/chip/mt_scp/mt818x/clock_chip.h
+++ b/chip/mt_scp/mt818x/clock_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,9 +18,7 @@
 #ifndef ULPOSC2_CLOCK_MHZ
 #define ULPOSC2_CLOCK_MHZ 330
 #endif
-#ifdef CHIP_VARIANT_MT8183
 void scp_enable_clock(void);
-#endif
 
 enum scp_clock_source {
 	SCP_CLK_26M = CLK_SEL_SYS_26M,
diff --git a/chip/mt_scp/mt818x/clock_mt8183.c b/chip/mt_scp/mt818x/clock_mt8183.c
index 1af0a3b893..fca89cd2a5 100644
--- a/chip/mt_scp/mt818x/clock_mt8183.c
+++ b/chip/mt_scp/mt818x/clock_mt8183.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,7 +14,7 @@
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ##args)
 
 #define ULPOSC_DIV_MAX (1 << OSC_DIV_BITS)
 #define ULPOSC_CALI_MAX (1 << OSC_CALI_BITS)
@@ -29,14 +29,14 @@ void clock_init(void)
 	SCP_SYS_CTRL |= AUTO_DDREN;
 
 	/* Initialize 26MHz system clock counter reset value to 1. */
-	SCP_CLK_SYS_VAL =
-		(SCP_CLK_SYS_VAL & ~CLK_SYS_VAL_MASK) | CLK_SYS_VAL(1);
+	SCP_CLK_SYS_VAL = (SCP_CLK_SYS_VAL & ~CLK_SYS_VAL_MASK) |
+			  CLK_SYS_VAL(1);
 	/* Initialize high frequency ULPOSC counter reset value to 1. */
-	SCP_CLK_HIGH_VAL =
-		(SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) | CLK_HIGH_VAL(1);
+	SCP_CLK_HIGH_VAL = (SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) |
+			   CLK_HIGH_VAL(1);
 	/* Initialize sleep mode control VREQ counter. */
-	SCP_CLK_SLEEP_CTRL =
-		(SCP_CLK_SLEEP_CTRL & ~VREQ_COUNTER_MASK) | VREQ_COUNTER_VAL(1);
+	SCP_CLK_SLEEP_CTRL = (SCP_CLK_SLEEP_CTRL & ~VREQ_COUNTER_MASK) |
+			     VREQ_COUNTER_VAL(1);
 
 	/* Set normal wake clock */
 	SCP_WAKE_CKSW &= ~WAKE_CKSW_SEL_NORMAL_MASK;
@@ -108,13 +108,12 @@ static unsigned int scp_measure_ulposc_freq(int osc)
 	int cnt;
 
 	/* Before select meter clock input, bit[1:0] = b00 */
-	AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_MODE_MASK) |
-			 DBG_MODE_SET_CLOCK;
+	AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_MODE_MASK) | DBG_MODE_SET_CLOCK;
 
 	/* Select source, bit[21:16] = clk_src */
-	AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_BIST_SOURCE_MASK) |
-			 (osc == 0 ? DBG_BIST_SOURCE_ULPOSC1 :
-				     DBG_BIST_SOURCE_ULPOSC2);
+	AP_CLK_DBG_CFG =
+		(AP_CLK_DBG_CFG & ~DBG_BIST_SOURCE_MASK) |
+		(osc == 0 ? DBG_BIST_SOURCE_ULPOSC1 : DBG_BIST_SOURCE_ULPOSC2);
 
 	/* Set meter divisor to 1, bit[31:24] = b00000000 */
 	AP_CLK_MISC_CFG_0 = (AP_CLK_MISC_CFG_0 & ~MISC_METER_DIVISOR_MASK) |
@@ -163,8 +162,7 @@ static int scp_ulposc_config_measure(int osc, int div, int cali)
 
 	scp_ulposc_config(osc, div, cali);
 	freq = scp_measure_ulposc_freq(osc);
-	CPRINTF("ULPOSC%d: %d %d %d (%dkHz)\n",
-		osc + 1, div, cali, freq,
+	CPRINTF("ULPOSC%d: %d %d %d (%dkHz)\n", osc + 1, div, cali, freq,
 		freq * 26 * 1000 / 1024);
 
 	return freq;
@@ -182,10 +180,10 @@ static int scp_calibrate_ulposc(int osc, int target_mhz)
 {
 	int target_freq = DIV_ROUND_NEAREST(target_mhz * 1024, 26);
 	struct ulposc {
-		int div;        /* frequency divisor/multiplier */
-		int cali;       /* variable resistor calibrator */
-		int freq;       /* frequency counter measure result */
-	} curr, prev = {0};
+		int div; /* frequency divisor/multiplier */
+		int cali; /* variable resistor calibrator */
+		int freq; /* frequency counter measure result */
+	} curr, prev = { 0 };
 	enum { STAGE_DIV, STAGE_CALI } stage = STAGE_DIV;
 	int param, param_max;
 
@@ -220,9 +218,9 @@ static int scp_calibrate_ulposc(int osc, int target_mhz)
 		 * frequency, pick the closest one.
 		 */
 		if (prev.freq && signum(target_freq - curr.freq) !=
-				 signum(target_freq - prev.freq)) {
+					 signum(target_freq - prev.freq)) {
 			if (abs(target_freq - prev.freq) <
-					abs(target_freq - curr.freq))
+			    abs(target_freq - curr.freq))
 				curr = prev;
 
 			if (stage == STAGE_CALI)
@@ -304,7 +302,7 @@ void scp_enable_clock(void)
 	SCP_SYS_CTRL |= AUTO_DDREN;
 
 	/* Set settle time */
-	SCP_CLK_SYS_VAL = 1;  /* System clock */
+	SCP_CLK_SYS_VAL = 1; /* System clock */
 	SCP_CLK_HIGH_VAL = 1; /* ULPOSC */
 	SCP_CLK_SLEEP_CTRL = (SCP_CLK_SLEEP_CTRL & ~VREQ_COUNTER_MASK) | 2;
 
@@ -355,7 +353,7 @@ static void clock_fast_wakeup_irq(void)
 }
 
 /* Console command */
-static int command_ulposc(int argc, char *argv[])
+static int command_ulposc(int argc, const char *argv[])
 {
 	if (argc > 1 && !strncmp(argv[1], "cal", 3)) {
 		scp_calibrate_ulposc(0, ULPOSC1_CLOCK_MHZ);
diff --git a/chip/mt_scp/mt818x/clock_mt8186.c b/chip/mt_scp/mt818x/clock_mt8186.c
index f5f25c773f..cb0d339b5f 100644
--- a/chip/mt_scp/mt818x/clock_mt8186.c
+++ b/chip/mt_scp/mt818x/clock_mt8186.c
@@ -1,10 +1,11 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Clocks, PLL and power settings */
 
+#include "builtin/assert.h"
 #include "clock.h"
 #include "clock_chip.h"
 #include "common.h"
@@ -14,11 +15,12 @@
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ##args)
 
-#define ULPOSC_CAL_MIN_VALUE   3
-#define ULPOSC_CAL_MAX_VALUE   60
-#define ULPOSC_CAL_START_VALUE ((ULPOSC_CAL_MIN_VALUE + ULPOSC_CAL_MAX_VALUE)/2)
+#define ULPOSC_CAL_MIN_VALUE 3
+#define ULPOSC_CAL_MAX_VALUE 60
+#define ULPOSC_CAL_START_VALUE \
+	((ULPOSC_CAL_MIN_VALUE + ULPOSC_CAL_MAX_VALUE) / 2)
 
 static struct opp_ulposc_cfg {
 	uint32_t osc;
@@ -29,11 +31,19 @@ static struct opp_ulposc_cfg {
 	uint32_t target_mhz;
 } opp[] = {
 	{
-		.osc = 1, .target_mhz = ULPOSC2_CLOCK_MHZ, .div = 16, .iband = 4, .mod = 1,
+		.osc = 1,
+		.target_mhz = ULPOSC2_CLOCK_MHZ,
+		.div = 16,
+		.iband = 4,
+		.mod = 1,
 		.cali = ULPOSC_CAL_START_VALUE,
 	},
 	{
-		.osc = 0, .target_mhz = ULPOSC1_CLOCK_MHZ, .div = 12, .iband = 4, .mod = 1,
+		.osc = 0,
+		.target_mhz = ULPOSC1_CLOCK_MHZ,
+		.div = 12,
+		.iband = 4,
+		.mod = 1,
 		.cali = ULPOSC_CAL_START_VALUE,
 	},
 };
@@ -90,17 +100,23 @@ static void clock_ulposc_config_cali(struct opp_ulposc_cfg *opp,
 
 static unsigned int clock_ulposc_measure_freq(int osc)
 {
-	unsigned int result = 0;
+	unsigned int clk_dbg_cfg, clk_misc_cfg_0, clk26cali_0, clk26cali_1,
+		result = 0;
 	int cnt;
 
+	/* backup */
+	clk_dbg_cfg = AP_CLK_DBG_CFG;
+	clk_misc_cfg_0 = AP_CLK_MISC_CFG_0;
+	clk26cali_0 = AP_SCP_CFG_0;
+	clk26cali_1 = AP_SCP_CFG_1;
+
 	/* Before select meter clock input, bit[1:0] = b00 */
-	AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_MODE_MASK) |
-			 DBG_MODE_SET_CLOCK;
+	AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_MODE_MASK) | DBG_MODE_SET_CLOCK;
 
 	/* Select source, bit[21:16] = clk_src */
-	AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_BIST_SOURCE_MASK) |
-			 (osc == 0 ? DBG_BIST_SOURCE_ULPOSC1 :
-				     DBG_BIST_SOURCE_ULPOSC2);
+	AP_CLK_DBG_CFG =
+		(AP_CLK_DBG_CFG & ~DBG_BIST_SOURCE_MASK) |
+		(osc == 0 ? DBG_BIST_SOURCE_ULPOSC1 : DBG_BIST_SOURCE_ULPOSC2);
 
 	/* Set meter divisor to 1, bit[31:24] = b00000000 */
 	AP_CLK_MISC_CFG_0 = (AP_CLK_MISC_CFG_0 & ~MISC_METER_DIVISOR_MASK) |
@@ -129,10 +145,17 @@ static unsigned int clock_ulposc_measure_freq(int osc)
 
 	/* Disable freq meter */
 	AP_SCP_CFG_0 &= ~CFG_FREQ_METER_ENABLE;
+
+	/* restore */
+	AP_CLK_DBG_CFG = clk_dbg_cfg;
+	AP_CLK_MISC_CFG_0 = clk_misc_cfg_0;
+	AP_SCP_CFG_0 = clk26cali_0;
+	AP_SCP_CFG_1 = clk26cali_1;
+
 	return result;
 }
 
-#define CAL_MIS_RATE	40
+#define CAL_MIS_RATE 40
 static int clock_ulposc_is_calibrated(struct opp_ulposc_cfg *opp)
 {
 	uint32_t curr, target;
@@ -231,13 +254,12 @@ static void clock_calibrate_ulposc(struct opp_ulposc_cfg *opp)
 	clock_ulposc_config_default(opp);
 	clock_high_enable(opp->osc);
 
-
 	/* Calibrate only if it is not accurate enough. */
 	if (!clock_ulposc_is_calibrated(opp))
 		opp->cali = clock_ulposc_process_cali(opp);
 
-	CPRINTF("osc:%u, target=%uMHz, cal:%u\n",
-		opp->osc, opp->target_mhz, opp->cali);
+	CPRINTF("osc:%u, target=%uMHz, cal:%u\n", opp->osc, opp->target_mhz,
+		opp->cali);
 }
 
 void scp_use_clock(enum scp_clock_source src)
@@ -257,13 +279,32 @@ void scp_use_clock(enum scp_clock_source src)
 
 void clock_init(void)
 {
+	/* Enable fast wakeup support */
+	SCP_CLK_ON_CTRL = (SCP_CLK_ON_CTRL & ~HIGH_FINAL_VAL_MASK) |
+			  HIGH_FINAL_VAL_DEFAULT;
+	SCP_FAST_WAKE_CNT_END =
+		(SCP_FAST_WAKE_CNT_END & ~FAST_WAKE_CNT_END_MASK) |
+		FAST_WAKE_CNT_END_DEFAULT;
+
+	/* Set slow wake clock */
+	SCP_WAKE_CKSW = (SCP_WAKE_CKSW & ~WAKE_CKSW_SEL_SLOW_MASK) |
+			WAKE_CKSW_SEL_SLOW_DEFAULT;
+
+	/* Select CLK_HIGH as wakeup clock */
+	SCP_CLK_SLOW_SEL = (SCP_CLK_SLOW_SEL &
+			    (CKSW_SEL_SLOW_MASK | CKSW_SEL_SLOW_DIV_MASK)) |
+			   CKSW_SEL_SLOW_ULPOSC2_CLK;
+}
+
+void scp_enable_clock(void)
+{
 	int i;
 
 	/* Select default CPU clock */
 	scp_use_clock(SCP_CLK_26M);
 
 	/* VREQ */
-	SCP_CPU_VREQ = VREQ_SEL | VREQ_DVFS_SEL;
+	SCP_CPU_VREQ = VREQ_DVFS_SEL;
 	SCP_SECURE_CTRL |= ENABLE_SPM_MASK_VREQ;
 	SCP_CLK_CTRL_GENERAL_CTRL &= ~VREQ_PMIC_WRAP_SEL;
 
@@ -271,17 +312,23 @@ void clock_init(void)
 	SCP_SYS_CTRL |= AUTO_DDREN;
 
 	/* Set settle time */
-	SCP_CLK_SYS_VAL =
-		(SCP_CLK_SYS_VAL & ~CLK_SYS_VAL_MASK) | CLK_SYS_VAL(1);
-	SCP_CLK_HIGH_VAL =
-		(SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) | CLK_HIGH_VAL(1);
-	SCP_CLK_SLEEP_CTRL =
-		(SCP_CLK_SLEEP_CTRL & ~VREQ_COUNTER_MASK) | VREQ_COUNTER_VAL(1);
+	SCP_CLK_SYS_VAL = (SCP_CLK_SYS_VAL & ~CLK_SYS_VAL_MASK) |
+			  CLK_SYS_VAL(1);
+	SCP_CLK_HIGH_VAL = (SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) |
+			   CLK_HIGH_VAL(1);
+	SCP_CLK_SLEEP_CTRL = (SCP_CLK_SLEEP_CTRL & ~VREQ_COUNTER_MASK) |
+			     VREQ_COUNTER_VAL(1);
+
+	/* Disable slow wake */
+	SCP_CLK_SLEEP = SLOW_WAKE_DISABLE;
+	/* Disable SPM sleep control, disable sleep mode */
+	SCP_CLK_SLEEP_CTRL &= ~(SPM_SLEEP_MODE | EN_SLEEP_CTRL);
 
 	/* Set RG MUX to SW mode */
-	AP_PLL_CON0 = LTECLKSQ_EN | LTECLKSQ_LPF_EN | LTECLKSQ_HYS_EN | LTECLKSQ_VOD_EN |
-		LTECLKSQ_HYS_SEL | CLKSQ_RESERVE | SSUSB26M_CK2_EN | SSUSB26M_CK_EN|
-		XTAL26M_CK_EN | ULPOSC_CTRL_SEL;
+	AP_PLL_CON0 = LTECLKSQ_EN | LTECLKSQ_LPF_EN | LTECLKSQ_HYS_EN |
+		      LTECLKSQ_VOD_EN | LTECLKSQ_HYS_SEL | CLKSQ_RESERVE |
+		      SSUSB26M_CK2_EN | SSUSB26M_CK_EN | XTAL26M_CK_EN |
+		      ULPOSC_CTRL_SEL;
 
 	/* Turn off ULPOSC2 */
 	SCP_CLK_ON_CTRL |= HIGH_CORE_DIS_SUB;
@@ -318,13 +365,12 @@ void clock_fast_wakeup_irq(void)
 }
 
 /* Console command */
-static int command_ulposc(int argc, char *argv[])
+static int command_ulposc(int argc, const char *argv[])
 {
 	int i;
 
 	for (i = 0; i <= 1; ++i)
-		ccprintf("ULPOSC%u frequency: %u kHz\n",
-			 i + 1,
+		ccprintf("ULPOSC%u frequency: %u kHz\n", i + 1,
 			 clock_ulposc_measure_freq(i) * 26 * 1000 / 1024);
 	return EC_SUCCESS;
 }
diff --git a/chip/mt_scp/mt818x/config_chip.h b/chip/mt_scp/mt818x/config_chip.h
index e0d7158728..e0222e33fa 100644
--- a/chip/mt_scp/mt818x/config_chip.h
+++ b/chip/mt_scp/mt818x/config_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,10 +10,15 @@
 
 /* Interval between HOOK_TICK notifications */
 #define HOOK_TICK_INTERVAL_MS 500
-#define HOOK_TICK_INTERVAL    (HOOK_TICK_INTERVAL_MS * MSEC)
+#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC)
 
+#ifdef CHIP_VARIANT_MT8186
+/* Default to UART 1 (AP UART) for EC console */
+#define CONFIG_UART_CONSOLE 1
+#else
 /* Default to UART 2 (AP UART) for EC console */
 #define CONFIG_UART_CONSOLE 2
+#endif
 
 /* Number of IRQ vectors */
 #define CONFIG_IRQ_COUNT 56
@@ -26,7 +31,7 @@
 #define MAX_EINT_PORT (MAX_NUM_EINT / 32)
 
 /* RW only, no flash */
-#undef  CONFIG_FW_INCLUDE_RO
+#undef CONFIG_FW_INCLUDE_RO
 #define CONFIG_RO_MEM_OFF 0
 #define CONFIG_RO_SIZE 0
 #define CONFIG_RW_MEM_OFF 0
diff --git a/chip/mt_scp/mt818x/gpio.c b/chip/mt_scp/mt818x/gpio.c
index 2bd4bfbb02..6d9a3b8418 100644
--- a/chip/mt_scp/mt818x/gpio.c
+++ b/chip/mt_scp/mt818x/gpio.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,7 +13,7 @@
 #include "util.h"
 
 void gpio_set_alternate_function(uint32_t port, uint32_t mask,
-				enum gpio_alternate_func func)
+				 enum gpio_alternate_func func)
 {
 	int bit, mode_reg_index, shift;
 	uint32_t mode_bits, mode_mask;
@@ -37,18 +37,16 @@ void gpio_set_alternate_function(uint32_t port, uint32_t mask,
 		shift = (bit & 7) << 2;
 		mode_bits = func << shift;
 		mode_mask = ~(0xf << shift);
-		AP_GPIO_MODE(mode_reg_index) = (AP_GPIO_MODE(mode_reg_index) &
-						mode_mask) | mode_bits;
+		AP_GPIO_MODE(mode_reg_index) =
+			(AP_GPIO_MODE(mode_reg_index) & mode_mask) | mode_bits;
 	}
 }
 
 test_mockable int gpio_get_level(enum gpio_signal signal)
 {
-	return !!(AP_GPIO_DIN(gpio_list[signal].port) &
-		  gpio_list[signal].mask);
+	return !!(AP_GPIO_DIN(gpio_list[signal].port) & gpio_list[signal].mask);
 }
 
-
 void gpio_set_level(enum gpio_signal signal, int value)
 {
 	if (value)
diff --git a/chip/mt_scp/mt818x/hrtimer.c b/chip/mt_scp/mt818x/hrtimer.c
index 89e0c1658b..e68c3e48e7 100644
--- a/chip/mt_scp/mt818x/hrtimer.c
+++ b/chip/mt_scp/mt818x/hrtimer.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -50,22 +50,22 @@ static inline uint64_t timer_read_raw_system(void)
 	 * sys_high value.
 	 */
 	if (timer_ctrl & TIMER_IRQ_STATUS)
-		sys_high_adj = sys_high ? (sys_high - 1) : (TIMER_CLOCK_MHZ-1);
+		sys_high_adj = sys_high ? (sys_high - 1) :
+					  (TIMER_CLOCK_MHZ - 1);
 
-	return OVERFLOW_TICKS - (((uint64_t)sys_high_adj << 32) |
-				 SCP_TIMER_VAL(TIMER_SYSTEM));
+	return OVERFLOW_TICKS -
+	       (((uint64_t)sys_high_adj << 32) | SCP_TIMER_VAL(TIMER_SYSTEM));
 }
 
 static inline uint64_t timer_read_raw_event(void)
 {
-	return OVERFLOW_TICKS - (((uint64_t)event_high << 32) |
-				 SCP_TIMER_VAL(TIMER_EVENT));
+	return OVERFLOW_TICKS -
+	       (((uint64_t)event_high << 32) | SCP_TIMER_VAL(TIMER_EVENT));
 }
 
 static inline void timer_set_clock(int n, uint32_t clock_source)
 {
-	SCP_TIMER_EN(n) = (SCP_TIMER_EN(n) & ~TIMER_CLK_MASK) |
-			  clock_source;
+	SCP_TIMER_EN(n) = (SCP_TIMER_EN(n) & ~TIMER_CLK_MASK) | clock_source;
 }
 
 static inline void timer_ack_irq(int n)
@@ -182,7 +182,7 @@ int __hw_clock_source_init(uint32_t start_t)
 	SCP_CLK_BCLK = CLK_BCLK_SEL_ULPOSC1_DIV8;
 
 	timer_set_clock(TIMER_SYSTEM, TIMER_CLK_BCLK);
-	sys_high = TIMER_CLOCK_MHZ-1;
+	sys_high = TIMER_CLOCK_MHZ - 1;
 	timer_set_reset_value(TIMER_SYSTEM, 0xffffffff);
 	__hw_timer_enable_clock(TIMER_SYSTEM, 1);
 	task_enable_irq(IRQ_TIMER(TIMER_SYSTEM));
@@ -200,8 +200,8 @@ uint32_t __hw_clock_source_read(void)
 
 uint32_t __hw_clock_event_get(void)
 {
-	return (timer_read_raw_event() + timer_read_raw_system())
-			/ TIMER_CLOCK_MHZ;
+	return (timer_read_raw_event() + timer_read_raw_system()) /
+	       TIMER_CLOCK_MHZ;
 }
 
 static void __hw_clock_source_irq(int n)
@@ -228,7 +228,7 @@ static void __hw_clock_source_irq(int n)
 				process_timers(0);
 			} else {
 				/* Overflow, reload system timer */
-				sys_high = TIMER_CLOCK_MHZ-1;
+				sys_high = TIMER_CLOCK_MHZ - 1;
 				process_timers(1);
 			}
 		} else {
@@ -238,10 +238,9 @@ static void __hw_clock_source_irq(int n)
 	default:
 		return;
 	}
-
 }
 
-#define DECLARE_TIMER_IRQ(n) \
+#define DECLARE_TIMER_IRQ(n)                                     \
 	DECLARE_IRQ(IRQ_TIMER(n), __hw_clock_source_irq_##n, 2); \
 	static void __hw_clock_source_irq_##n(void)              \
 	{                                                        \
diff --git a/chip/mt_scp/mt818x/ipi.c b/chip/mt_scp/mt818x/ipi.c
index 8b695d57e0..7ae4ed12a0 100644
--- a/chip/mt_scp/mt818x/ipi.c
+++ b/chip/mt_scp/mt818x/ipi.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -196,7 +196,6 @@ int ipi_send(int32_t id, const void *buf, uint32_t len, int wait)
 		return EC_ERROR_BUSY;
 	}
 
-
 	scp_send_obj->id = id;
 	scp_send_obj->len = len;
 	memcpy(scp_send_obj->buffer, buf, len);
diff --git a/chip/mt_scp/mt818x/ipi_chip.h b/chip/mt_scp/mt818x/ipi_chip.h
index 03b5572497..37be00dabb 100644
--- a/chip/mt_scp/mt818x/ipi_chip.h
+++ b/chip/mt_scp/mt818x/ipi_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -97,15 +97,15 @@ extern int *ipi_wakeup_table[];
  * handler: The IPI handler function
  * is_wakeup_src: Declare IPI ID as a wake-up source or not
  */
-#define DECLARE_IPI(_id, handler, is_wakeup_src) \
-	struct ipi_num_check##_id { \
-		int tmp1[_id < IPI_COUNT ? 1 : -1]; \
+#define DECLARE_IPI(_id, handler, is_wakeup_src)                             \
+	struct ipi_num_check##_id {                                          \
+		int tmp1[_id < IPI_COUNT ? 1 : -1];                          \
 		int tmp2[is_wakeup_src == 0 || is_wakeup_src == 1 ? 1 : -1]; \
-	};  \
-	void __keep IPI_HANDLER(_id)(int32_t id, void *buf, uint32_t len) \
-	{ \
-		handler(id, buf, len); \
-	} \
+	};                                                                   \
+	void __keep IPI_HANDLER(_id)(int32_t id, void *buf, uint32_t len)    \
+	{                                                                    \
+		handler(id, buf, len);                                       \
+	}                                                                    \
 	const int __keep IPI_WAKEUP(_id) = is_wakeup_src
 
 #endif /* __CROS_EC_IPI_CHIP_H */
diff --git a/chip/mt_scp/mt818x/ipi_table.c b/chip/mt_scp/mt818x/ipi_table.c
index 8569ab24a7..153b8b8dbc 100644
--- a/chip/mt_scp/mt818x/ipi_table.c
+++ b/chip/mt_scp/mt818x/ipi_table.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -17,21 +17,24 @@ typedef void (*ipi_handler_t)(int32_t id, void *data, uint32_t len);
 #define ipi_arguments int32_t id, void *data, uint32_t len
 
 #if PASS == 1
-void ipi_handler_undefined(ipi_arguments) { }
+void ipi_handler_undefined(ipi_arguments)
+{
+}
 
 const int ipi_wakeup_undefined;
 
 #define table(type, name, x) x
 
-#define ipi_x_func(suffix, args, number)                                       \
-	extern void __attribute__(                                             \
-		(used, weak, alias(STRINGIFY(ipi_##suffix##_undefined))))      \
+#define ipi_x_func(suffix, args, number)                                    \
+	extern void                                                         \
+		__attribute__((used, weak,                                  \
+			       alias(STRINGIFY(ipi_##suffix##_undefined)))) \
 		ipi_##number##_##suffix(args);
 
 #define ipi_x_var(suffix, number)                                              \
-	extern int __attribute__(                                              \
-		(weak, alias(STRINGIFY(ipi_##suffix##_undefined))))            \
-		ipi_##number##_##suffix;
+	extern int __attribute__((weak,                                        \
+				  alias(STRINGIFY(ipi_##suffix##_undefined)))) \
+	ipi_##number##_##suffix;
 
 #endif /* PASS == 1 */
 
@@ -41,11 +44,11 @@ const int ipi_wakeup_undefined;
 #undef ipi_x_func
 #undef ipi_x_var
 
-#define table(type, name, x)                                                   \
-	type name[] __aligned(4)                                               \
-		__attribute__((section(".rodata.ipi, \"a\" @"))) = {x}
+#define table(type, name, x)     \
+	type name[] __aligned(4) \
+		__attribute__((section(".rodata.ipi, \"a\" @"))) = { x }
 
-#define ipi_x_var(suffix, number)                                              \
+#define ipi_x_var(suffix, number) \
 	[number < IPI_COUNT ? number : -1] = &ipi_##number##_##suffix,
 
 #define ipi_x_func(suffix, args, number) ipi_x_var(suffix, number)
diff --git a/chip/mt_scp/mt818x/memmap.c b/chip/mt_scp/mt818x/memmap.c
index 6d8f2b0c87..0ecb370cf3 100644
--- a/chip/mt_scp/mt818x/memmap.c
+++ b/chip/mt_scp/mt818x/memmap.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -12,6 +12,7 @@
 #include "memmap.h"
 #include "registers.h"
 #include "util.h"
+#include "task.h"
 
 /*
  * Map SCP address (bits 31~28) to AP address
@@ -34,13 +35,13 @@
 #define MAP_INVALID 0xff
 
 static const uint8_t addr_map[16] = {
-	MAP_INVALID,			/* 0x0: SRAM */
-	MAP_INVALID,			/* 0x1: Cached access (see below) */
-	0x4, 0x5,			/* 0x2-0x3 */
-	MAP_INVALID, MAP_INVALID,	/* 0x4-0x5 (unmapped: registers) */
-	0x6, 0x7, 0x8,			/* 0x6-0x8 */
-	0x0, 0x1, 0x2, 0x3,		/* 0x9-0xc */
-	0x1, 0xa, 0x9			/* 0xd-0xf */
+	MAP_INVALID, /* 0x0: SRAM */
+	MAP_INVALID, /* 0x1: Cached access (see below) */
+	0x4,	     0x5, /* 0x2-0x3 */
+	MAP_INVALID, MAP_INVALID, /* 0x4-0x5 (unmapped: registers) */
+	0x6,	     0x7,	  0x8, /* 0x6-0x8 */
+	0x0,	     0x1,	  0x2, 0x3, /* 0x9-0xc */
+	0x1,	     0xa,	  0x9 /* 0xd-0xf */
 };
 
 /*
@@ -49,8 +50,6 @@ static const uint8_t addr_map[16] = {
  */
 #define CACHE_TRANS_AP_ADDR 0x50000000
 #define CACHE_TRANS_SCP_CACHE_ADDR 0x10000000
-/* FIXME: This should be configurable */
-#define CACHE_TRANS_AP_SIZE 0x00400000
 
 #ifdef CONFIG_DRAM_BASE
 BUILD_ASSERT(CONFIG_DRAM_BASE_LOAD == CACHE_TRANS_AP_ADDR);
@@ -60,16 +59,14 @@ BUILD_ASSERT(CONFIG_DRAM_BASE == CACHE_TRANS_SCP_CACHE_ADDR);
 static void cpu_invalidate_icache(void)
 {
 	SCP_CACHE_OP(CACHE_ICACHE) &= ~SCP_CACHE_OP_OP_MASK;
-	SCP_CACHE_OP(CACHE_ICACHE) |=
-		OP_INVALIDATE_ALL_LINES | SCP_CACHE_OP_EN;
+	SCP_CACHE_OP(CACHE_ICACHE) |= OP_INVALIDATE_ALL_LINES | SCP_CACHE_OP_EN;
 	asm volatile("dsb; isb");
 }
 
 void cpu_invalidate_dcache(void)
 {
 	SCP_CACHE_OP(CACHE_DCACHE) &= ~SCP_CACHE_OP_OP_MASK;
-	SCP_CACHE_OP(CACHE_DCACHE) |=
-		OP_INVALIDATE_ALL_LINES | SCP_CACHE_OP_EN;
+	SCP_CACHE_OP(CACHE_DCACHE) |= OP_INVALIDATE_ALL_LINES | SCP_CACHE_OP_EN;
 	/* Read is necessary to confirm the invalidation finish. */
 	REG32(CACHE_TRANS_SCP_CACHE_ADDR);
 	asm volatile("dsb;");
@@ -80,6 +77,8 @@ void cpu_invalidate_dcache_range(uintptr_t base, unsigned int length)
 	size_t pos;
 	uintptr_t addr;
 
+	interrupt_disable();
+
 	for (pos = 0; pos < length; pos += SCP_CACHE_LINE_SIZE) {
 		addr = base + pos;
 		SCP_CACHE_OP(CACHE_DCACHE) = addr & SCP_CACHE_OP_TADDR_MASK;
@@ -88,17 +87,18 @@ void cpu_invalidate_dcache_range(uintptr_t base, unsigned int length)
 		/* Read necessary to confirm the invalidation finish. */
 		REG32(addr);
 	}
+
 	asm volatile("dsb;");
+	interrupt_enable();
 }
 
 void cpu_clean_invalidate_dcache(void)
 {
 	SCP_CACHE_OP(CACHE_DCACHE) &= ~SCP_CACHE_OP_OP_MASK;
-	SCP_CACHE_OP(CACHE_DCACHE) |=
-		OP_CACHE_FLUSH_ALL_LINES | SCP_CACHE_OP_EN;
+	SCP_CACHE_OP(CACHE_DCACHE) |= OP_CACHE_FLUSH_ALL_LINES |
+				      SCP_CACHE_OP_EN;
 	SCP_CACHE_OP(CACHE_DCACHE) &= ~SCP_CACHE_OP_OP_MASK;
-	SCP_CACHE_OP(CACHE_DCACHE) |=
-		OP_INVALIDATE_ALL_LINES | SCP_CACHE_OP_EN;
+	SCP_CACHE_OP(CACHE_DCACHE) |= OP_INVALIDATE_ALL_LINES | SCP_CACHE_OP_EN;
 	/* Read necessary to confirm the invalidation finish. */
 	REG32(CACHE_TRANS_SCP_CACHE_ADDR);
 	asm volatile("dsb;");
@@ -109,6 +109,7 @@ void cpu_clean_invalidate_dcache_range(uintptr_t base, unsigned int length)
 	size_t pos;
 	uintptr_t addr;
 
+	interrupt_disable();
 	for (pos = 0; pos < length; pos += SCP_CACHE_LINE_SIZE) {
 		addr = base + pos;
 		SCP_CACHE_OP(CACHE_DCACHE) = addr & SCP_CACHE_OP_TADDR_MASK;
@@ -120,7 +121,9 @@ void cpu_clean_invalidate_dcache_range(uintptr_t base, unsigned int length)
 		/* Read necessary to confirm the invalidation finish. */
 		REG32(addr);
 	}
+
 	asm volatile("dsb;");
+	interrupt_enable();
 }
 
 static void scp_cache_init(void)
@@ -137,8 +140,8 @@ static void scp_cache_init(void)
 		 * should only be be configured in kernel driver before
 		 * laoding the firmware. b/137920815#comment18
 		 */
-		SCP_CACHE_CON(c) &= (SCP_CACHE_CON_CACHESIZE_MASK |
-				     SCP_CACHE_CON_WAYEN);
+		SCP_CACHE_CON(c) &=
+			(SCP_CACHE_CON_CACHESIZE_MASK | SCP_CACHE_CON_WAYEN);
 		SCP_CACHE_REGION_EN(c) = 0;
 		SCP_CACHE_ENTRY(c, region) = 0;
 		SCP_CACHE_END_ENTRY(c, region) = 0;
@@ -164,7 +167,7 @@ static void scp_cache_init(void)
 
 	/* Disable sleep protect */
 	SCP_SLP_PROTECT_CFG = SCP_SLP_PROTECT_CFG &
-		~(P_CACHE_SLP_PROT_EN | D_CACHE_SLP_PROT_EN);
+			      ~(P_CACHE_SLP_PROT_EN | D_CACHE_SLP_PROT_EN);
 
 	/* Enable region 0 for both I-cache and D-cache. */
 	for (c = 0; c < CACHE_COUNT; c++) {
@@ -186,16 +189,16 @@ static void scp_cache_init(void)
 	cpu_invalidate_dcache();
 }
 
-static int command_cacheinfo(int argc, char **argv)
+static int command_cacheinfo(int argc, const char **argv)
 {
-	const char cache_name[] = {'I', 'D'};
+	const char cache_name[] = { 'I', 'D' };
 	int c;
 
 	for (c = 0; c < 2; c++) {
 		uint64_t hit = ((uint64_t)SCP_CACHE_HCNT0U(c) << 32) |
-			SCP_CACHE_HCNT0L(c);
+			       SCP_CACHE_HCNT0L(c);
 		uint64_t access = ((uint64_t)SCP_CACHE_CCNT0U(c) << 32) |
-			SCP_CACHE_CCNT0L(c);
+				  SCP_CACHE_CCNT0L(c);
 
 		ccprintf("%ccache hit count:    %llu\n", cache_name[c], hit);
 		ccprintf("%ccache access count: %llu\n", cache_name[c], access);
@@ -203,8 +206,7 @@ static int command_cacheinfo(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_SAFE_CONSOLE_COMMAND(cacheinfo, command_cacheinfo,
-			     NULL,
+DECLARE_SAFE_CONSOLE_COMMAND(cacheinfo, command_cacheinfo, NULL,
 			     "Dump cache info");
 
 void scp_memmap_init(void)
@@ -221,11 +223,9 @@ void scp_memmap_init(void)
 	 * EXT_ADDR1[13:8]  remap register for addr msb 31~28 equal to 0x3
 	 * EXT_ADDR0[5:0]   remap register for addr msb 31~28 equal to 0x2
 	 */
-	SCP_REMAP_CFG1 =
-		(uint32_t)addr_map[0x7] << 24 |
-		(uint32_t)addr_map[0x6] << 16 |
-		(uint32_t)addr_map[0x3] << 8 |
-		(uint32_t)addr_map[0x2];
+	SCP_REMAP_CFG1 = (uint32_t)addr_map[0x7] << 24 |
+			 (uint32_t)addr_map[0x6] << 16 |
+			 (uint32_t)addr_map[0x3] << 8 | (uint32_t)addr_map[0x2];
 
 	/*
 	 * SCP_REMAP_CFG2
@@ -234,11 +234,9 @@ void scp_memmap_init(void)
 	 * EXT_ADDR5[13:8]  remap register for addr msb 31~28 equal to 0x9
 	 * EXT_ADDR4[5:0]   remap register for addr msb 31~28 equal to 0x8
 	 */
-	SCP_REMAP_CFG2 =
-		(uint32_t)addr_map[0xb] << 24 |
-		(uint32_t)addr_map[0xa] << 16 |
-		(uint32_t)addr_map[0x9] << 8 |
-		(uint32_t)addr_map[0x8];
+	SCP_REMAP_CFG2 = (uint32_t)addr_map[0xb] << 24 |
+			 (uint32_t)addr_map[0xa] << 16 |
+			 (uint32_t)addr_map[0x9] << 8 | (uint32_t)addr_map[0x8];
 	/*
 	 * SCP_REMAP_CFG3
 	 * AUD_ADDR[31:28]  remap register for addr msb 31~28 equal to 0xd
@@ -246,11 +244,9 @@ void scp_memmap_init(void)
 	 * EXT_ADDR9[13:8]  remap register for addr msb 31~28 equal to 0xe
 	 * EXT_ADDR8[5:0]   remap register for addr msb 31~28 equal to 0xc
 	 */
-	SCP_REMAP_CFG3 =
-		(uint32_t)addr_map[0xd] << 28 |
-		(uint32_t)addr_map[0xf] << 16 |
-		(uint32_t)addr_map[0xe] << 8 |
-		(uint32_t)addr_map[0xc];
+	SCP_REMAP_CFG3 = (uint32_t)addr_map[0xd] << 28 |
+			 (uint32_t)addr_map[0xf] << 16 |
+			 (uint32_t)addr_map[0xe] << 8 | (uint32_t)addr_map[0xc];
 
 	/* Initialize cache remapping. */
 	scp_cache_init();
@@ -266,7 +262,7 @@ int memmap_ap_to_scp(uintptr_t ap_addr, uintptr_t *scp_addr)
 			continue;
 
 		*scp_addr = (ap_addr & SCP_REMAP_ADDR_LSB_MASK) |
-			(i << SCP_REMAP_ADDR_SHIFT);
+			    (i << SCP_REMAP_ADDR_SHIFT);
 		return EC_SUCCESS;
 	}
 
@@ -281,7 +277,7 @@ int memmap_scp_to_ap(uintptr_t scp_addr, uintptr_t *ap_addr)
 		return EC_ERROR_INVAL;
 
 	*ap_addr = (scp_addr & SCP_REMAP_ADDR_LSB_MASK) |
-		(addr_map[i] << SCP_REMAP_ADDR_SHIFT);
+		   (addr_map[i] << SCP_REMAP_ADDR_SHIFT);
 	return EC_SUCCESS;
 }
 
@@ -310,7 +306,7 @@ int memmap_scp_cache_to_ap(uintptr_t scp_addr, uintptr_t *ap_addr)
 	uintptr_t lsb;
 
 	if ((scp_addr & SCP_L1_EXT_ADDR_OTHER_MSB_MASK) !=
-			CACHE_TRANS_SCP_CACHE_ADDR)
+	    CACHE_TRANS_SCP_CACHE_ADDR)
 		return EC_ERROR_INVAL;
 
 	lsb = scp_addr & SCP_L1_EXT_ADDR_OTHER_LSB_MASK;
diff --git a/chip/mt_scp/mt818x/memmap.h b/chip/mt_scp/mt818x/memmap.h
index fbecb5e8cf..b89123d57f 100644
--- a/chip/mt_scp/mt818x/memmap.h
+++ b/chip/mt_scp/mt818x/memmap.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/chip/mt_scp/mt818x/registers.h b/chip/mt_scp/mt818x/registers.h
index 36ac63ef12..7bfcf184af 100644
--- a/chip/mt_scp/mt818x/registers.h
+++ b/chip/mt_scp/mt818x/registers.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -12,90 +12,90 @@
 #include "compile_time_macros.h"
 
 /* IRQ numbers */
-#define SCP_IRQ_IPC0			0
-#define SCP_IRQ_IPC1			1
-#define SCP_IRQ_IPC2			2
-#define SCP_IRQ_IPC3			3
-#define SCP_IRQ_SPM			4
-#define SCP_IRQ_CIRQ			5
-#define SCP_IRQ_EINT			6
-#define SCP_IRQ_PMIC			7
-#define SCP_IRQ_UART0			8
-#define SCP_IRQ_UART1			9
-#define SCP_IRQ_I2C0			10
-#define SCP_IRQ_I2C1			11
-#define SCP_IRQ_I2C2			12
-#define SCP_IRQ_CLOCK			13
-#define SCP_IRQ_MAD_FIFO		14
-#define SCP_IRQ_TIMER0			15
-#define SCP_IRQ_TIMER1			16
-#define SCP_IRQ_TIMER2			17
-#define SCP_IRQ_TIMER3			18
-#define SCP_IRQ_TIMER4			19
-#define SCP_IRQ_TIMER5			20
-#define SCP_IRQ_TIMER_STATUS		21
-#define SCP_IRQ_UART0_RX		22
-#define SCP_IRQ_UART1_RX		23
-#define SCP_IRQ_DMA			24
-#define SCP_IRQ_AUDIO			25
-#define SCP_IRQ_MD1_F216		26
-#define SCP_IRQ_MD1			27
-#define SCP_IRQ_C2K			28
-#define SCP_IRQ_SPI0			29
-#define SCP_IRQ_SPI1			30
-#define SCP_IRQ_SPI2			31
-#define SCP_IRQ_AP_EINT			32
-#define SCP_IRQ_DEBUG			33
-#define SCP_CCIF0			34
-#define SCP_CCIF1			35
-#define SCP_CCIF2			36
-#define SCP_IRQ_WDT			37
-#define SCP_IRQ_USB0			38
-#define SCP_IRQ_USB1			39
-#define SCP_IRQ_TWAM			40
-#define SCP_IRQ_INFRA			41
-#define SCP_IRQ_HWDVFS_HIGH		42
-#define SCP_IRQ_HWDVFS_LOW		43
-#define SCP_IRQ_CLOCK2			44
+#define SCP_IRQ_IPC0 0
+#define SCP_IRQ_IPC1 1
+#define SCP_IRQ_IPC2 2
+#define SCP_IRQ_IPC3 3
+#define SCP_IRQ_SPM 4
+#define SCP_IRQ_CIRQ 5
+#define SCP_IRQ_EINT 6
+#define SCP_IRQ_PMIC 7
+#define SCP_IRQ_UART0 8
+#define SCP_IRQ_UART1 9
+#define SCP_IRQ_I2C0 10
+#define SCP_IRQ_I2C1 11
+#define SCP_IRQ_I2C2 12
+#define SCP_IRQ_CLOCK 13
+#define SCP_IRQ_MAD_FIFO 14
+#define SCP_IRQ_TIMER0 15
+#define SCP_IRQ_TIMER1 16
+#define SCP_IRQ_TIMER2 17
+#define SCP_IRQ_TIMER3 18
+#define SCP_IRQ_TIMER4 19
+#define SCP_IRQ_TIMER5 20
+#define SCP_IRQ_TIMER_STATUS 21
+#define SCP_IRQ_UART0_RX 22
+#define SCP_IRQ_UART1_RX 23
+#define SCP_IRQ_DMA 24
+#define SCP_IRQ_AUDIO 25
+#define SCP_IRQ_MD1_F216 26
+#define SCP_IRQ_MD1 27
+#define SCP_IRQ_C2K 28
+#define SCP_IRQ_SPI0 29
+#define SCP_IRQ_SPI1 30
+#define SCP_IRQ_SPI2 31
+#define SCP_IRQ_AP_EINT 32
+#define SCP_IRQ_DEBUG 33
+#define SCP_CCIF0 34
+#define SCP_CCIF1 35
+#define SCP_CCIF2 36
+#define SCP_IRQ_WDT 37
+#define SCP_IRQ_USB0 38
+#define SCP_IRQ_USB1 39
+#define SCP_IRQ_TWAM 40
+#define SCP_IRQ_INFRA 41
+#define SCP_IRQ_HWDVFS_HIGH 42
+#define SCP_IRQ_HWDVFS_LOW 43
+#define SCP_IRQ_CLOCK2 44
 /* RESERVED 45-52 */
-#define SCP_IRQ_AP_EINT2		53
-#define SCP_IRQ_AP_EINT_EVT		54
-#define SCP_IRQ_MAD_DATA		55
+#define SCP_IRQ_AP_EINT2 53
+#define SCP_IRQ_AP_EINT_EVT 54
+#define SCP_IRQ_MAD_DATA 55
 
-#define SCP_CFG_BASE			0x405C0000
+#define SCP_CFG_BASE 0x405C0000
 
-#define SCP_AP_RESOURCE			REG32(SCP_CFG_BASE + 0x04)
-#define SCP_BUS_RESOURCE		REG32(SCP_CFG_BASE + 0x08)
+#define SCP_AP_RESOURCE REG32(SCP_CFG_BASE + 0x04)
+#define SCP_BUS_RESOURCE REG32(SCP_CFG_BASE + 0x08)
 
 #ifdef CHIP_VARIANT_MT8186
-#define SCP_TCM_LOCK_CFG        	(CFGREG_BASE + 0x10)
+#define SCP_TCM_LOCK_CFG (CFGREG_BASE + 0x10)
 #endif
 
 /* SCP to host interrupt */
-#define SCP_HOST_INT			REG32(SCP_CFG_BASE + 0x1C)
-#define   IPC_SCP2HOST_SSHUB		0xff0000
-#define   WDT_INT			0x100
-#define   IPC_SCP2HOST                  0xff
-#define   IPC_SCP2HOST_BIT		0x1
+#define SCP_HOST_INT REG32(SCP_CFG_BASE + 0x1C)
+#define IPC_SCP2HOST_SSHUB 0xff0000
+#define WDT_INT 0x100
+#define IPC_SCP2HOST 0xff
+#define IPC_SCP2HOST_BIT 0x1
 
 /* SCP to SPM interrupt */
-#define SCP_SPM_INT			REG32(SCP_CFG_BASE + 0x20)
-#define   SPM_INT_A2SPM			BIT(0)
-#define   SPM_INT_B2SPM			BIT(1)
-#define SCP_SPM_INT2			REG32(SCP_CFG_BASE + 0x24)
+#define SCP_SPM_INT REG32(SCP_CFG_BASE + 0x20)
+#define SPM_INT_A2SPM BIT(0)
+#define SPM_INT_B2SPM BIT(1)
+#define SCP_SPM_INT2 REG32(SCP_CFG_BASE + 0x24)
 
 /*
  * AP side to SCP IPC
  * APMCU writes 1 bit to trigger ith IPC to SCP.
  * SCP writes 1 bit to ith bit to clear ith IPC.
  */
-#define SCP_GIPC_IN			REG32(SCP_CFG_BASE + 0x28)
-  #define SCP_GIPC_IN_CLEAR_IPCN(n)	(1 << (n))
-  #define SCP_GPIC_IN_CLEAR_ALL		0x7FFFF
-#define SCP_CONN_INT			REG32(SCP_CFG_BASE + 0x2C)
+#define SCP_GIPC_IN REG32(SCP_CFG_BASE + 0x28)
+#define SCP_GIPC_IN_CLEAR_IPCN(n) (1 << (n))
+#define SCP_GPIC_IN_CLEAR_ALL 0x7FFFF
+#define SCP_CONN_INT REG32(SCP_CFG_BASE + 0x2C)
 
 /* 8 general purpose registers, 0 ~ 7 */
-#define SCP_GPR				REG32_ADDR(SCP_CFG_BASE + 0x50)
+#define SCP_GPR REG32_ADDR(SCP_CFG_BASE + 0x50)
 /*
  * SCP_GPR[0]
  *   b15-b0   : scratchpad
@@ -103,44 +103,44 @@
  * SCP_GPR[1]
  *   b15-b0   : power on state
  */
-#define SCP_PWRON_STATE			SCP_GPR[1]
-#define   PWRON_DEFAULT			0xdee80000
-#define   PWRON_WATCHDOG		BIT(0)
-#define   PWRON_RESET			BIT(1)
+#define SCP_PWRON_STATE SCP_GPR[1]
+#define PWRON_DEFAULT 0xdee80000
+#define PWRON_WATCHDOG BIT(0)
+#define PWRON_RESET BIT(1)
 /* AP defined features */
-#define SCP_EXPECTED_FREQ		SCP_GPR[3]
-#define SCP_CURRENT_FREQ		SCP_GPR[4]
-#define SCP_REBOOT			SCP_GPR[5]
-#define  READY_TO_REBOOT		0x34
-#define  REBOOT_OK			1
+#define SCP_EXPECTED_FREQ SCP_GPR[3]
+#define SCP_CURRENT_FREQ SCP_GPR[4]
+#define SCP_REBOOT SCP_GPR[5]
+#define READY_TO_REBOOT 0x34
+#define REBOOT_OK 1
 
 /* Miscellaneous */
-#define SCP_SEMAPHORE			REG32(SCP_CFG_BASE + 0x90)
-#define CORE_CONTROL			REG32(SCP_CFG_BASE + 0xA0)
-#define CORE_FPU_FLAGS			REG32(SCP_CFG_BASE + 0xA4)
-#define CORE_REG_SP			REG32(SCP_CFG_BASE + 0xA8)
-#define CORE_REG_LR			REG32(SCP_CFG_BASE + 0xAC)
-#define CORE_REG_PSP			REG32(SCP_CFG_BASE + 0xB0)
-#define CORE_REG_PC			REG32(SCP_CFG_BASE + 0xB4)
-#define SCP_SLP_PROTECT_CFG		REG32(SCP_CFG_BASE + 0xC8)
-#define   P_CACHE_SLP_PROT_EN		BIT(3)
-#define   D_CACHE_SLP_PROT_EN		BIT(4)
-#define SCP_ONE_TIME_LOCK		REG32(SCP_CFG_BASE + 0xDC)
-#define SCP_SECURE_CTRL			REG32(SCP_CFG_BASE + 0xE0)
+#define SCP_SEMAPHORE REG32(SCP_CFG_BASE + 0x90)
+#define CORE_CONTROL REG32(SCP_CFG_BASE + 0xA0)
+#define CORE_FPU_FLAGS REG32(SCP_CFG_BASE + 0xA4)
+#define CORE_REG_SP REG32(SCP_CFG_BASE + 0xA8)
+#define CORE_REG_LR REG32(SCP_CFG_BASE + 0xAC)
+#define CORE_REG_PSP REG32(SCP_CFG_BASE + 0xB0)
+#define CORE_REG_PC REG32(SCP_CFG_BASE + 0xB4)
+#define SCP_SLP_PROTECT_CFG REG32(SCP_CFG_BASE + 0xC8)
+#define P_CACHE_SLP_PROT_EN BIT(3)
+#define D_CACHE_SLP_PROT_EN BIT(4)
+#define SCP_ONE_TIME_LOCK REG32(SCP_CFG_BASE + 0xDC)
+#define SCP_SECURE_CTRL REG32(SCP_CFG_BASE + 0xE0)
 
 #ifdef CHIP_VARIANT_MT8186
-#define	JTAG_DBG_REQ_BIT         	BIT(3)
-#define   DISABLE_REMAP			BIT(31)
+#define JTAG_DBG_REQ_BIT BIT(3)
+#define DISABLE_REMAP BIT(31)
 #else
-#define   DISABLE_REMAP                 BIT(22)
+#define DISABLE_REMAP BIT(22)
 #endif
 
-#define   ENABLE_SPM_MASK_VREQ		BIT(28)
-#define   DISABLE_JTAG			BIT(21)
-#define   DISABLE_AP_TCM		BIT(20)
-#define SCP_SYS_CTRL			REG32(SCP_CFG_BASE + 0xE4)
-#define   DDREN_FIX_VALUE		BIT(28)
-#define   AUTO_DDREN			BIT(18)
+#define ENABLE_SPM_MASK_VREQ BIT(28)
+#define DISABLE_JTAG BIT(21)
+#define DISABLE_AP_TCM BIT(20)
+#define SCP_SYS_CTRL REG32(SCP_CFG_BASE + 0xE4)
+#define DDREN_FIX_VALUE BIT(28)
+#define AUTO_DDREN BIT(18)
 
 /* Memory remap control */
 /*
@@ -149,515 +149,508 @@
  * EXT_ADDR1[13:8]  remap register for addr msb 31~28 equal to 0x3
  * EXT_ADDR0[5:0]   remap register for addr msb 31~28 equal to 0x2
  */
-#define SCP_REMAP_CFG1			REG32(SCP_CFG_BASE + 0x120)
+#define SCP_REMAP_CFG1 REG32(SCP_CFG_BASE + 0x120)
 /*
  * EXT_ADDR7[29:24] remap register for addr msb 31~28 equal to 0xb
  * EXT_ADDR6[21:16] remap register for addr msb 31~28 equal to 0xa
  * EXT_ADDR5[13:8]  remap register for addr msb 31~28 equal to 0x9
  * EXT_ADDR4[5:0]   remap register for addr msb 31~28 equal to 0x8
  */
-#define SCP_REMAP_CFG2			REG32(SCP_CFG_BASE + 0x124)
+#define SCP_REMAP_CFG2 REG32(SCP_CFG_BASE + 0x124)
 /*
  * AUD_ADDR[31:28]  remap register for addr msb 31~28 equal to 0xd
  * EXT_ADDR10[21:16]remap register for addr msb 31~28 equal to 0xf
  * EXT_ADDR9[13:8]  remap register for addr msb 31~28 equal to 0xe
  * EXT_ADDR8[5:0]   remap register for addr msb 31~28 equal to 0xc
  */
-#define SCP_REMAP_CFG3			REG32(SCP_CFG_BASE + 0x128)
+#define SCP_REMAP_CFG3 REG32(SCP_CFG_BASE + 0x128)
 
-#define SCP_REMAP_ADDR_SHIFT		28
-#define SCP_REMAP_ADDR_LSB_MASK		(BIT(SCP_REMAP_ADDR_SHIFT) - 1)
-#define SCP_REMAP_ADDR_MSB_MASK		((~0) << SCP_REMAP_ADDR_SHIFT)
+#define SCP_REMAP_ADDR_SHIFT 28
+#define SCP_REMAP_ADDR_LSB_MASK (BIT(SCP_REMAP_ADDR_SHIFT) - 1)
+#define SCP_REMAP_ADDR_MSB_MASK ((~0) << SCP_REMAP_ADDR_SHIFT)
 
 /* Cached memory remap control */
-#define SCP_L1_REMAP_CFG0		REG32(SCP_CFG_BASE + 0x12C)
+#define SCP_L1_REMAP_CFG0 REG32(SCP_CFG_BASE + 0x12C)
 /*
  * L1C_EXT_ADDR1[29:16] remap register for addr msb 31~20 equal to 0x401
  * L1C_EXT_ADDR0[13:0]  remap register for addr msb 31~20 equal to 0x400
  */
-#define SCP_L1_REMAP_CFG1		REG32(SCP_CFG_BASE + 0x130)
+#define SCP_L1_REMAP_CFG1 REG32(SCP_CFG_BASE + 0x130)
 /*
  * L1C_EXT_ADDR3[29:16] remap register for addr msb 31~20 equal to 0x403
  * L1C_EXT_ADDR2[13:0]  remap register for addr msb 31~20 equal to 0x402
  */
-#define SCP_L1_REMAP_CFG2		REG32(SCP_CFG_BASE + 0x134)
+#define SCP_L1_REMAP_CFG2 REG32(SCP_CFG_BASE + 0x134)
 /*
  * L1C_EXT_ADDR5[29:16] remap register for addr msb 31~20 equal to 0x405
  * L1C_EXT_ADDR4[13:0]  remap register for addr msb 31~20 equal to 0x404
  */
-#define SCP_L1_REMAP_CFG3		REG32(SCP_CFG_BASE + 0x138)
+#define SCP_L1_REMAP_CFG3 REG32(SCP_CFG_BASE + 0x138)
 /*
  * L1C_EXT_ADDR_OTHER1[13:8] Remap register for addr msb 31 to 28 equal to 0x1
  * L1C_EXT_ADDR_OTHER0[5:0] Remap register for addr msb 31 to 28 equal to 0x0
  * and not overlap with L1C_EXT_ADDR0 to L1C_EXT_ADDR7
  */
-#define SCP_L1_REMAP_OTHER		REG32(SCP_CFG_BASE + 0x13C)
+#define SCP_L1_REMAP_OTHER REG32(SCP_CFG_BASE + 0x13C)
 
-#define SCP_L1_EXT_ADDR_SHIFT		20
-#define SCP_L1_EXT_ADDR_OTHER_SHIFT	28
-#define SCP_L1_EXT_ADDR_OTHER_LSB_MASK	(BIT(SCP_REMAP_ADDR_SHIFT) - 1)
-#define SCP_L1_EXT_ADDR_OTHER_MSB_MASK	((~0) << SCP_REMAP_ADDR_SHIFT)
+#define SCP_L1_EXT_ADDR_SHIFT 20
+#define SCP_L1_EXT_ADDR_OTHER_SHIFT 28
+#define SCP_L1_EXT_ADDR_OTHER_LSB_MASK (BIT(SCP_REMAP_ADDR_SHIFT) - 1)
+#define SCP_L1_EXT_ADDR_OTHER_MSB_MASK ((~0) << SCP_REMAP_ADDR_SHIFT)
 
 /* Audio/voice FIFO */
-#define SCP_AUDIO_BASE			(SCP_CFG_BASE + 0x1000)
-#define SCP_VIF_FIFO_EN			REG32(SCP_AUDIO_BASE)
-#define   VIF_FIFO_RSTN			(1 << 0)
-#define   VIF_FIFO_IRQ_EN		(1 << 1)
-#define   VIF_FIFO_SRAM_PWR		(1 << 2)
-#define   VIF_FIFO_RSTN_STATUS		(1 << 4)
-#define SCP_VIF_FIFO_STATUS		REG32(SCP_AUDIO_BASE + 0x04)
-#define   VIF_FIFO_VALID		(1 << 0)
-#define   VIF_FIFO_FULL			(1 << 4)
-#define   VIF_FIFO_LEVEL(status)	(((status) >> 16) & 0xff)
-#define   VIF_FIFO_MAX			256
-#define SCP_VIF_FIFO_DATA		REG32(SCP_AUDIO_BASE + 0x08)
-#define SCP_VIF_FIFO_DATA_THRE		REG32(SCP_AUDIO_BASE + 0x0C)
+#define SCP_AUDIO_BASE (SCP_CFG_BASE + 0x1000)
+#define SCP_VIF_FIFO_EN REG32(SCP_AUDIO_BASE)
+#define VIF_FIFO_RSTN (1 << 0)
+#define VIF_FIFO_IRQ_EN (1 << 1)
+#define VIF_FIFO_SRAM_PWR (1 << 2)
+#define VIF_FIFO_RSTN_STATUS (1 << 4)
+#define SCP_VIF_FIFO_STATUS REG32(SCP_AUDIO_BASE + 0x04)
+#define VIF_FIFO_VALID (1 << 0)
+#define VIF_FIFO_FULL (1 << 4)
+#define VIF_FIFO_LEVEL(status) (((status) >> 16) & 0xff)
+#define VIF_FIFO_MAX 256
+#define SCP_VIF_FIFO_DATA REG32(SCP_AUDIO_BASE + 0x08)
+#define SCP_VIF_FIFO_DATA_THRE REG32(SCP_AUDIO_BASE + 0x0C)
 /* VIF IRQ status clears on read! */
-#define SCP_VIF_FIFO_IRQ_STATUS		REG32(SCP_AUDIO_BASE + 0x10)
+#define SCP_VIF_FIFO_IRQ_STATUS REG32(SCP_AUDIO_BASE + 0x10)
 /* Audio/voice serial interface */
-#define SCP_RXIF_CFG0			REG32(SCP_AUDIO_BASE + 0x14)
-#define   RXIF_CFG0_RESET_VAL		0x2A130001
-#define   RXIF_AFE_ON			(1 << 0)
-#define   RXIF_SCKINV			(1 << 1)
-#define   RXIF_RG_DL_2_IN_MODE(mode)	(((mode) & 0xf) << 8)
-#define   RXIF_RGDL2_AMIC_16K		(0x1 << 8)
-#define   RXIF_RGDL2_DMIC_16K		(0x2 << 8)
-#define   RXIF_RGDL2_DMIC_LP_16K	(0x3 << 8)
-#define   RXIF_RGDL2_AMIC_32K		(0x5 << 8)
-#define   RXIF_RGDL2_MASK		(0xf << 8)
-#define   RXIF_UP8X_RSP(p)		(((p) & 0x7) << 16)
-#define   RXIF_RG_RX_READEN		(1 << 19)
-#define   RXIF_MONO			(1 << 20)
-#define   RXIF_RG_CLK_A16P7K_EN(cnt)	(((cnt) & 0xff) << 24)
-#define SCP_RXIF_CFG1			REG32(SCP_AUDIO_BASE + 0x18)
-#define   RXIF_CFG1_RESET_VAL		0x33180014
-#define   RXIF_RG_SYNC_CNT_TBL(t)	((t) & 0x1ff)
-#define   RXIF_RG_SYNC_SEARCH_TBL(t)	(((t) & 0x1f) << 16)
-#define   RXIF_RG_SYNC_CHECK_ROUND(r)	(((r) & 0xf) << 24)
-#define   RXIF_RG_INSYNC_CHECK_ROUND(r)	(((r) & 0xf) << 28)
-#define SCP_RXIF_CFG2			REG32(SCP_AUDIO_BASE + 0x1C)
-#define   RXIF_SYNC_WORD(w)		((w) & 0xffff)
-#define SCP_RXIF_OUT			REG32(SCP_AUDIO_BASE + 0x20)
-#define SCP_RXIF_STATUS			REG32(SCP_AUDIO_BASE + 0x24)
-#define SCP_RXIF_IRQ_EN			REG32(SCP_AUDIO_BASE + 0x28)
+#define SCP_RXIF_CFG0 REG32(SCP_AUDIO_BASE + 0x14)
+#define RXIF_CFG0_RESET_VAL 0x2A130001
+#define RXIF_AFE_ON (1 << 0)
+#define RXIF_SCKINV (1 << 1)
+#define RXIF_RG_DL_2_IN_MODE(mode) (((mode)&0xf) << 8)
+#define RXIF_RGDL2_AMIC_16K (0x1 << 8)
+#define RXIF_RGDL2_DMIC_16K (0x2 << 8)
+#define RXIF_RGDL2_DMIC_LP_16K (0x3 << 8)
+#define RXIF_RGDL2_AMIC_32K (0x5 << 8)
+#define RXIF_RGDL2_MASK (0xf << 8)
+#define RXIF_UP8X_RSP(p) (((p)&0x7) << 16)
+#define RXIF_RG_RX_READEN (1 << 19)
+#define RXIF_MONO (1 << 20)
+#define RXIF_RG_CLK_A16P7K_EN(cnt) (((cnt)&0xff) << 24)
+#define SCP_RXIF_CFG1 REG32(SCP_AUDIO_BASE + 0x18)
+#define RXIF_CFG1_RESET_VAL 0x33180014
+#define RXIF_RG_SYNC_CNT_TBL(t) ((t)&0x1ff)
+#define RXIF_RG_SYNC_SEARCH_TBL(t) (((t)&0x1f) << 16)
+#define RXIF_RG_SYNC_CHECK_ROUND(r) (((r)&0xf) << 24)
+#define RXIF_RG_INSYNC_CHECK_ROUND(r) (((r)&0xf) << 28)
+#define SCP_RXIF_CFG2 REG32(SCP_AUDIO_BASE + 0x1C)
+#define RXIF_SYNC_WORD(w) ((w)&0xffff)
+#define SCP_RXIF_OUT REG32(SCP_AUDIO_BASE + 0x20)
+#define SCP_RXIF_STATUS REG32(SCP_AUDIO_BASE + 0x24)
+#define SCP_RXIF_IRQ_EN REG32(SCP_AUDIO_BASE + 0x28)
 
 /* INTC control */
-#define SCP_INTC_BASE			(SCP_CFG_BASE + 0x2000)
-#define SCP_INTC_IRQ_STATUS		REG32(SCP_INTC_BASE)
-#define SCP_INTC_IRQ_ENABLE		REG32(SCP_INTC_BASE + 0x04)
-#define   IPC0_IRQ_EN			BIT(0)
-#define SCP_INTC_IRQ_OUTPUT		REG32(SCP_INTC_BASE + 0x08)
-#define SCP_INTC_IRQ_WAKEUP		REG32(SCP_INTC_BASE + 0x0C)
-#define SCP_INTC_NMI			REG32(SCP_INTC_BASE + 0x10)
-#define SCP_INTC_SPM_WAKEUP		REG32(SCP_INTC_BASE + 0x14)
-#define SCP_INTC_SPM_WAKEUP_MSB		REG32(SCP_INTC_BASE + 0x18)
-#define SCP_INTC_UART_RX_IRQ		REG32(SCP_INTC_BASE + 0x1C)
-#define SCP_INTC_IRQ_STATUS_MSB		REG32(SCP_INTC_BASE + 0x80)
-#define SCP_INTC_IRQ_ENABLE_MSB		REG32(SCP_INTC_BASE + 0x84)
-#define SCP_INTC_IRQ_OUTPUT_MSB		REG32(SCP_INTC_BASE + 0x88)
-#define SCP_INTC_IRQ_WAKEUP_MSB		REG32(SCP_INTC_BASE + 0x8C)
+#define SCP_INTC_BASE (SCP_CFG_BASE + 0x2000)
+#define SCP_INTC_IRQ_STATUS REG32(SCP_INTC_BASE)
+#define SCP_INTC_IRQ_ENABLE REG32(SCP_INTC_BASE + 0x04)
+#define IPC0_IRQ_EN BIT(0)
+#define SCP_INTC_IRQ_OUTPUT REG32(SCP_INTC_BASE + 0x08)
+#define SCP_INTC_IRQ_WAKEUP REG32(SCP_INTC_BASE + 0x0C)
+#define SCP_INTC_NMI REG32(SCP_INTC_BASE + 0x10)
+#define SCP_INTC_SPM_WAKEUP REG32(SCP_INTC_BASE + 0x14)
+#define SCP_INTC_SPM_WAKEUP_MSB REG32(SCP_INTC_BASE + 0x18)
+#define SCP_INTC_UART_RX_IRQ REG32(SCP_INTC_BASE + 0x1C)
+#define SCP_INTC_IRQ_STATUS_MSB REG32(SCP_INTC_BASE + 0x80)
+#define SCP_INTC_IRQ_ENABLE_MSB REG32(SCP_INTC_BASE + 0x84)
+#define SCP_INTC_IRQ_OUTPUT_MSB REG32(SCP_INTC_BASE + 0x88)
+#define SCP_INTC_IRQ_WAKEUP_MSB REG32(SCP_INTC_BASE + 0x8C)
 
 /* Timer */
-#define NUM_TIMERS			6
-#define SCP_TIMER_BASE(n)		(SCP_CFG_BASE + 0x3000 + (0x10 * (n)))
-#define SCP_TIMER_EN(n)			REG32(SCP_TIMER_BASE(n))
-#define SCP_TIMER_RESET_VAL(n)		REG32(SCP_TIMER_BASE(n) + 0x04)
-#define SCP_TIMER_VAL(n)		REG32(SCP_TIMER_BASE(n) + 0x08)
-#define SCP_TIMER_IRQ_CTRL(n)		REG32(SCP_TIMER_BASE(n) + 0x0C)
-#define   TIMER_IRQ_ENABLE		BIT(0)
-#define   TIMER_IRQ_STATUS		BIT(4)
-#define   TIMER_IRQ_CLEAR		BIT(5)
-#define SCP_TIMER_CLK_SEL(n)		REG32(SCP_TIMER_BASE(n) + 0x40)
-#define   TIMER_CLK_32K			(0 << 4)
-#define   TIMER_CLK_26M			BIT(4)
-#define   TIMER_CLK_BCLK		(2 << 4)
-#define   TIMER_CLK_PCLK		(3 << 4)
-#define   TIMER_CLK_MASK		(3 << 4)
+#define NUM_TIMERS 6
+#define SCP_TIMER_BASE(n) (SCP_CFG_BASE + 0x3000 + (0x10 * (n)))
+#define SCP_TIMER_EN(n) REG32(SCP_TIMER_BASE(n))
+#define SCP_TIMER_RESET_VAL(n) REG32(SCP_TIMER_BASE(n) + 0x04)
+#define SCP_TIMER_VAL(n) REG32(SCP_TIMER_BASE(n) + 0x08)
+#define SCP_TIMER_IRQ_CTRL(n) REG32(SCP_TIMER_BASE(n) + 0x0C)
+#define TIMER_IRQ_ENABLE BIT(0)
+#define TIMER_IRQ_STATUS BIT(4)
+#define TIMER_IRQ_CLEAR BIT(5)
+#define SCP_TIMER_CLK_SEL(n) REG32(SCP_TIMER_BASE(n) + 0x40)
+#define TIMER_CLK_32K (0 << 4)
+#define TIMER_CLK_26M BIT(4)
+#define TIMER_CLK_BCLK (2 << 4)
+#define TIMER_CLK_PCLK (3 << 4)
+#define TIMER_CLK_MASK (3 << 4)
 /* OS timer */
-#define SCP_OSTIMER_BASE		(SCP_CFG_BASE + 0x3080)
-#define SCP_OSTIMER_CON			REG32(SCP_OSTIMER_BASE)
-#define SCP_OSTIMER_INIT_L		REG32(SCP_OSTIMER_BASE + 0x04)
-#define SCP_OSTIMER_INIT_H		REG32(SCP_OSTIMER_BASE + 0x08)
-#define SCP_OSTIMER_VAL_L		REG32(SCP_OSTIMER_BASE + 0x0C)
-#define SCP_OSTIMER_VAL_H		REG32(SCP_OSTIMER_BASE + 0x10)
-#define SCP_OSTIMER_TVAL		REG32(SCP_OSTIMER_BASE + 0x14)
-#define SCP_OSTIMER_IRQ_ACK		REG32(SCP_OSTIMER_BASE + 0x18)
-#define   OSTIMER_LATCH0_EN		BIT(5)
-#define   OSTIMER_LATCH1_EN		BIT(13)
-#define   OSTIMER_LATCH2_EN		BIT(21)
-#define SCP_OSTIMER_LATCH_CTRL		REG32(SCP_OSTIMER_BASE + 0x20)
-#define SCP_OSTIMER_LATCH0_L		REG32(SCP_OSTIMER_BASE + 0x24)
-#define SCP_OSTIMER_LATCH0_H		REG32(SCP_OSTIMER_BASE + 0x28)
-#define SCP_OSTIMER_LATCH1_L		REG32(SCP_OSTIMER_BASE + 0x2C)
-#define SCP_OSTIMER_LATCH1_H		REG32(SCP_OSTIMER_BASE + 0x30)
-#define SCP_OSTIMER_LATCH2_L		REG32(SCP_OSTIMER_BASE + 0x34)
-#define SCP_OSTIMER_LATCH2_H		REG32(SCP_OSTIMER_BASE + 0x38)
+#define SCP_OSTIMER_BASE (SCP_CFG_BASE + 0x3080)
+#define SCP_OSTIMER_CON REG32(SCP_OSTIMER_BASE)
+#define SCP_OSTIMER_INIT_L REG32(SCP_OSTIMER_BASE + 0x04)
+#define SCP_OSTIMER_INIT_H REG32(SCP_OSTIMER_BASE + 0x08)
+#define SCP_OSTIMER_VAL_L REG32(SCP_OSTIMER_BASE + 0x0C)
+#define SCP_OSTIMER_VAL_H REG32(SCP_OSTIMER_BASE + 0x10)
+#define SCP_OSTIMER_TVAL REG32(SCP_OSTIMER_BASE + 0x14)
+#define SCP_OSTIMER_IRQ_ACK REG32(SCP_OSTIMER_BASE + 0x18)
+#define OSTIMER_LATCH0_EN BIT(5)
+#define OSTIMER_LATCH1_EN BIT(13)
+#define OSTIMER_LATCH2_EN BIT(21)
+#define SCP_OSTIMER_LATCH_CTRL REG32(SCP_OSTIMER_BASE + 0x20)
+#define SCP_OSTIMER_LATCH0_L REG32(SCP_OSTIMER_BASE + 0x24)
+#define SCP_OSTIMER_LATCH0_H REG32(SCP_OSTIMER_BASE + 0x28)
+#define SCP_OSTIMER_LATCH1_L REG32(SCP_OSTIMER_BASE + 0x2C)
+#define SCP_OSTIMER_LATCH1_H REG32(SCP_OSTIMER_BASE + 0x30)
+#define SCP_OSTIMER_LATCH2_L REG32(SCP_OSTIMER_BASE + 0x34)
+#define SCP_OSTIMER_LATCH2_H REG32(SCP_OSTIMER_BASE + 0x38)
 
 /* Clock, PMIC wrapper, etc. */
-#define SCP_CLK_BASE			(SCP_CFG_BASE + 0x4000)
-#define SCP_CLK_SEL			REG32(SCP_CLK_BASE)
-#define   CLK_SEL_SYS_26M		0
-#define   CLK_SEL_32K			1
-#define   CLK_SEL_ULPOSC_2		2
-#define   CLK_SEL_ULPOSC_1		3
-
-#define SCP_CLK_EN			REG32(SCP_CLK_BASE + 0x04)
-#define   EN_CLK_SYS			BIT(0) /* System clock */
-#define   EN_CLK_HIGH			BIT(1) /* ULPOSC */
-#define   CG_CLK_HIGH			BIT(2)
-#define   EN_SYS_IRQ			BIT(16)
-#define   EN_HIGH_IRQ			BIT(17)
-#define SCP_CLK_SAFE_ACK		REG32(SCP_CLK_BASE + 0x08)
-#define SCP_CLK_ACK			REG32(SCP_CLK_BASE + 0x0C)
-#define SCP_CLK_IRQ_ACK			REG32(SCP_CLK_BASE + 0x10)
+#define SCP_CLK_BASE (SCP_CFG_BASE + 0x4000)
+#define SCP_CLK_SEL REG32(SCP_CLK_BASE)
+#define CLK_SEL_SYS_26M 0
+#define CLK_SEL_32K 1
+#define CLK_SEL_ULPOSC_2 2
+#define CLK_SEL_ULPOSC_1 3
+
+#define SCP_CLK_EN REG32(SCP_CLK_BASE + 0x04)
+#define EN_CLK_SYS BIT(0) /* System clock */
+#define EN_CLK_HIGH BIT(1) /* ULPOSC */
+#define CG_CLK_HIGH BIT(2)
+#define EN_SYS_IRQ BIT(16)
+#define EN_HIGH_IRQ BIT(17)
+#define SCP_CLK_SAFE_ACK REG32(SCP_CLK_BASE + 0x08)
+#define SCP_CLK_ACK REG32(SCP_CLK_BASE + 0x0C)
+#define SCP_CLK_IRQ_ACK REG32(SCP_CLK_BASE + 0x10)
 /*
  * System clock counter value.
  * CLK_SYS_VAL[9:0] System clock counter initial/reset value.
  */
-#define SCP_CLK_SYS_VAL			REG32(SCP_CLK_BASE + 0x14)
-#define   CLK_SYS_VAL_MASK		0x3ff /* 10 bits */
-#define   CLK_SYS_VAL(n)		((n) & CLK_SYS_VAL_MASK)
+#define SCP_CLK_SYS_VAL REG32(SCP_CLK_BASE + 0x14)
+#define CLK_SYS_VAL_MASK 0x3ff /* 10 bits */
+#define CLK_SYS_VAL(n) ((n)&CLK_SYS_VAL_MASK)
 /*
  * ULPOSC clock counter value.
  * CLK_HIGH_VAL[9:0] ULPOSC clock counter initial/reset value.
  */
-#define SCP_CLK_HIGH_VAL		REG32(SCP_CLK_BASE + 0x18)
-#define   CLK_HIGH_VAL_MASK		0x3ff /* 10 bits */
-#define   CLK_HIGH_VAL(n)		((n) & CLK_HIGH_VAL_MASK)
-#define SCP_CLK_SLOW_SEL		REG32(SCP_CLK_BASE + 0x1C)
-#define   CKSW_SEL_SLOW_MASK		0x3
-#define   CKSW_SEL_SLOW_DIV_MASK	0x30
-#define   CKSW_SEL_SLOW_SYS_CLK		0
-#define   CKSW_SEL_SLOW_32K_CLK		1
-#define   CKSW_SEL_SLOW_ULPOSC2_CLK	2
-#define   CKSW_SEL_SLOW_ULPOSC1_CLK	3
+#define SCP_CLK_HIGH_VAL REG32(SCP_CLK_BASE + 0x18)
+#define CLK_HIGH_VAL_MASK 0x3ff /* 10 bits */
+#define CLK_HIGH_VAL(n) ((n)&CLK_HIGH_VAL_MASK)
+#define SCP_CLK_SLOW_SEL REG32(SCP_CLK_BASE + 0x1C)
+#define CKSW_SEL_SLOW_MASK 0x3
+#define CKSW_SEL_SLOW_DIV_MASK 0x30
+#define CKSW_SEL_SLOW_SYS_CLK 0
+#define CKSW_SEL_SLOW_32K_CLK 1
+#define CKSW_SEL_SLOW_ULPOSC2_CLK 2
+#define CKSW_SEL_SLOW_ULPOSC1_CLK 3
 /*
  * Sleep mode control.
  * VREQ_COUNT[7:1] Number of cycles to wait when requesting PMIC to raise the
  *     voltage after returning from  sleep mode.
  */
-#define SCP_CLK_SLEEP_CTRL		REG32(SCP_CLK_BASE + 0x20)
-#define   EN_SLEEP_CTRL			BIT(0)
+#define SCP_CLK_SLEEP_CTRL REG32(SCP_CLK_BASE + 0x20)
+#define EN_SLEEP_CTRL BIT(0)
 
 #ifdef CHIP_VARIANT_MT8186
-#define   VREQ_COUNTER_MASK		0x7F
+#define VREQ_COUNTER_MASK 0x7F
 #else
-#define   VREQ_COUNTER_MASK		0xfe
+#define VREQ_COUNTER_MASK 0xfe
 #endif
 
-#define   VREQ_COUNTER_VAL(v)		(((v) << 1) & VREQ_COUNTER_MASK)
-#define   SPM_SLEEP_MODE		BIT(8)
-#define   SPM_SLEEP_MODE_CLK_AO		BIT(9)
-#define SCP_CLK_DIV_SEL			REG32(SCP_CLK_BASE + 0x24)
-#define   CLK_DIV1			0
-#define   CLK_DIV2			1
-#define   CLK_DIV4			2
-#define   CLK_DIV8			3
-#define SCP_CLK_DEBUG			REG32(SCP_CLK_BASE + 0x28)
-#define SCP_CLK_SRAM_POWERDOWN		REG32(SCP_CLK_BASE + 0x2C)
-#define SCP_CLK_GATE			REG32(SCP_CLK_BASE + 0x30)
-#define   CG_TIMER_M			BIT(0)
-#define   CG_TIMER_B			BIT(1)
-#define   CG_MAD_M			BIT(2)
-#define   CG_I2C_M			BIT(3)
-#define   CG_I2C_B			BIT(4)
-#define   CG_GPIO_M			BIT(5)
-#define   CG_AP2P_M			BIT(6)
-#define   CG_UART_M			BIT(7)
-#define   CG_UART_B			BIT(8)
-#define   CG_UART_RSTN			BIT(9)
-#define   CG_UART1_M			BIT(10)
-#define   CG_UART1_B			BIT(11)
-#define   CG_UART1_RSTN			BIT(12)
-#define   CG_SPI0			BIT(13)
-#define   CG_SPI1			BIT(14)
-#define   CG_SPI2			BIT(15)
-#define   CG_DMA_CH0			BIT(16)
-#define   CG_DMA_CH1			BIT(17)
-#define   CG_DMA_CH2			BIT(18)
-#define   CG_DMA_CH3			BIT(19)
-#define   CG_TWAM			BIT(20)
-#define   CG_CACHE_I_CTRL		BIT(21)
-#define   CG_CACHE_D_CTRL		BIT(22)
-#define SCP_PMICW_CTRL			REG32(SCP_CLK_BASE + 0x34)
-#define   PMICW_SLEEP_REQ		BIT(0)
-#define   PMICW_SLEEP_ACK		BIT(4)
-#define   PMICW_CLK_MUX			BIT(8)
-#define   PMICW_DCM			BIT(9)
-#define SCP_SLEEP_WAKE_DEBUG		REG32(SCP_CLK_BASE + 0x38)
-#define SCP_DCM_EN			REG32(SCP_CLK_BASE + 0x3C)
-#define SCP_WAKE_CKSW			REG32(SCP_CLK_BASE + 0x40)
-
-#ifdef CHIP_VARIANT_MT8186
-#define WAKE_CKSW_SEL_NORMAL_BIT    0
-#define WAKE_CKSW_SEL_SLOW_BIT      4
-#define WAKE_CKSW_SEL_SLOW_MASK     0x3
-#else
-#define   WAKE_CKSW_SEL_SLOW_MASK       0x30
-#define   WAKE_CKSW_SEL_SLOW_DEFAULT	0x10
-#endif
-
-#define   WAKE_CKSW_SEL_NORMAL_MASK	0x3
-#define SCP_CLK_UART			REG32(SCP_CLK_BASE + 0x44)
-#define   CLK_UART_SEL_MASK		0x3
-#define   CLK_UART_SEL_26M		0x0
-#define   CLK_UART_SEL_32K		0x1
+#define VREQ_COUNTER_VAL(v) (((v) << 1) & VREQ_COUNTER_MASK)
+#define SPM_SLEEP_MODE BIT(8)
+#define SPM_SLEEP_MODE_CLK_AO BIT(9)
+#define SCP_CLK_DIV_SEL REG32(SCP_CLK_BASE + 0x24)
+#define CLK_DIV1 0
+#define CLK_DIV2 1
+#define CLK_DIV4 2
+#define CLK_DIV8 3
+#define SCP_CLK_DEBUG REG32(SCP_CLK_BASE + 0x28)
+#define SCP_CLK_SRAM_POWERDOWN REG32(SCP_CLK_BASE + 0x2C)
+#define SCP_CLK_GATE REG32(SCP_CLK_BASE + 0x30)
+#define CG_TIMER_M BIT(0)
+#define CG_TIMER_B BIT(1)
+#define CG_MAD_M BIT(2)
+#define CG_I2C_M BIT(3)
+#define CG_I2C_B BIT(4)
+#define CG_GPIO_M BIT(5)
+#define CG_AP2P_M BIT(6)
+#define CG_UART_M BIT(7)
+#define CG_UART_B BIT(8)
+#define CG_UART_RSTN BIT(9)
+#define CG_UART1_M BIT(10)
+#define CG_UART1_B BIT(11)
+#define CG_UART1_RSTN BIT(12)
+#define CG_SPI0 BIT(13)
+#define CG_SPI1 BIT(14)
+#define CG_SPI2 BIT(15)
+#define CG_DMA_CH0 BIT(16)
+#define CG_DMA_CH1 BIT(17)
+#define CG_DMA_CH2 BIT(18)
+#define CG_DMA_CH3 BIT(19)
+#define CG_TWAM BIT(20)
+#define CG_CACHE_I_CTRL BIT(21)
+#define CG_CACHE_D_CTRL BIT(22)
+#define SCP_PMICW_CTRL REG32(SCP_CLK_BASE + 0x34)
+#define PMICW_SLEEP_REQ BIT(0)
+#define PMICW_SLEEP_ACK BIT(4)
+#define PMICW_CLK_MUX BIT(8)
+#define PMICW_DCM BIT(9)
+#define SCP_SLEEP_WAKE_DEBUG REG32(SCP_CLK_BASE + 0x38)
+#define SCP_DCM_EN REG32(SCP_CLK_BASE + 0x3C)
+#define SCP_WAKE_CKSW REG32(SCP_CLK_BASE + 0x40)
+
+#define WAKE_CKSW_SEL_SLOW_MASK 0x30
+#define WAKE_CKSW_SEL_SLOW_DEFAULT 0x10
+
+#define WAKE_CKSW_SEL_NORMAL_MASK 0x3
+#define SCP_CLK_UART REG32(SCP_CLK_BASE + 0x44)
+#define CLK_UART_SEL_MASK 0x3
+#define CLK_UART_SEL_26M 0x0
+#define CLK_UART_SEL_32K 0x1
 /* This is named ulposc_div_to_26m in datasheet */
-#define   CLK_UART_SEL_ULPOSC1_DIV10	0x2
-#define   CLK_UART1_SEL_MASK		(0x3 << 16)
-#define   CLK_UART1_SEL_26M		(0x0 << 16)
-#define   CLK_UART1_SEL_32K		(0x1 << 16)
+#define CLK_UART_SEL_ULPOSC1_DIV10 0x2
+#define CLK_UART1_SEL_MASK (0x3 << 16)
+#define CLK_UART1_SEL_26M (0x0 << 16)
+#define CLK_UART1_SEL_32K (0x1 << 16)
 /* This is named ulposc_div_to_26m in datasheet */
-#define   CLK_UART1_SEL_ULPOSC1_DIV10	(0x2 << 16)
-#define SCP_CLK_BCLK			REG32(SCP_CLK_BASE + 0x48)
-#define   CLK_BCLK_SEL_MASK		0x3
-#define   CLK_BCLK_SEL_SYS_DIV8		0x0
-#define   CLK_BCLK_SEL_32K		0x1
-#define   CLK_BCLK_SEL_ULPOSC1_DIV8	0x2
-#define SCP_CLK_SPI_BCK			REG32(SCP_CLK_BASE + 0x4C)
-#define SCP_CLK_DIV_CNT			REG32(SCP_CLK_BASE + 0x50)
-#define SCP_CPU_VREQ			REG32(SCP_CLK_BASE + 0x54)
-#define   CPU_VREQ_HW_MODE		0x10001
+#define CLK_UART1_SEL_ULPOSC1_DIV10 (0x2 << 16)
+#define SCP_CLK_BCLK REG32(SCP_CLK_BASE + 0x48)
+#define CLK_BCLK_SEL_MASK 0x3
+#define CLK_BCLK_SEL_SYS_DIV8 0x0
+#define CLK_BCLK_SEL_32K 0x1
+#define CLK_BCLK_SEL_ULPOSC1_DIV8 0x2
+#define SCP_CLK_SPI_BCK REG32(SCP_CLK_BASE + 0x4C)
+#define SCP_CLK_DIV_CNT REG32(SCP_CLK_BASE + 0x50)
+#define SCP_CPU_VREQ REG32(SCP_CLK_BASE + 0x54)
+#define CPU_VREQ_HW_MODE 0x10001
 
 #ifdef CHIP_VARIANT_MT8186
-#define   VREQ_SEL			BIT(0)
-#define   VREQ_PMIC_WRAP_SEL		BIT(1)
-#define   VREQ_VALUE			BIT(4)
-#define   VREQ_EXT_SEL			BIT(8)
-#define   VREQ_DVFS_SEL			BIT(16)
-#define   VREQ_DVFS_VALUE		BIT(20)
-#define   VREQ_DVFS_EXT_SEL		BIT(24)
-#define   VREQ_SRCLKEN_SEL		BIT(27)
-#define   VREQ_SRCLKEN_VALUE		BIT(28)
+#define VREQ_SEL BIT(0)
+#define VREQ_PMIC_WRAP_SEL BIT(1)
+#define VREQ_VALUE BIT(4)
+#define VREQ_EXT_SEL BIT(8)
+#define VREQ_DVFS_SEL BIT(16)
+#define VREQ_DVFS_VALUE BIT(20)
+#define VREQ_DVFS_EXT_SEL BIT(24)
+#define VREQ_SRCLKEN_SEL BIT(27)
+#define VREQ_SRCLKEN_VALUE BIT(28)
 #endif
 
-#define SCP_CLK_CLEAR			REG32(SCP_CLK_BASE + 0x58)
-#define SCP_CLK_HIGH_CORE		REG32(SCP_CLK_BASE + 0x5C)
-#define   CLK_HIGH_CORE_CG		(1 << 1)
-#define SCP_SLEEP_IRQ2			REG32(SCP_CLK_BASE + 0x64)
-#define SCP_CLK_ON_CTRL			REG32(SCP_CLK_BASE + 0x6C)
-#define   HIGH_AO			BIT(0)
-#define   HIGH_CG_AO			BIT(2)
-#define   HIGH_CORE_AO			BIT(4)
-#define   HIGH_CORE_DIS_SUB		BIT(5)
-#define   HIGH_CORE_CG_AO		BIT(6)
-#define   HIGH_FINAL_VAL_MASK		0x1f00
-#define   HIGH_FINAL_VAL_DEFAULT	0x300
-#define SCP_CLK_L1_SRAM_PD		REG32(SCP_CLK_BASE + 0x80)
-#define SCP_CLK_TCM_TAIL_SRAM_PD	REG32(SCP_CLK_BASE + 0x94)
+#define SCP_CLK_CLEAR REG32(SCP_CLK_BASE + 0x58)
+#define SCP_CLK_HIGH_CORE REG32(SCP_CLK_BASE + 0x5C)
+#define CLK_HIGH_CORE_CG (1 << 1)
+#define SCP_SLEEP_IRQ2 REG32(SCP_CLK_BASE + 0x64)
+#define SCP_CLK_ON_CTRL REG32(SCP_CLK_BASE + 0x6C)
+#define HIGH_AO BIT(0)
+#define HIGH_CG_AO BIT(2)
+#define HIGH_CORE_AO BIT(4)
+#define HIGH_CORE_DIS_SUB BIT(5)
+#define HIGH_CORE_CG_AO BIT(6)
+#define HIGH_FINAL_VAL_MASK 0x1f00
+#define HIGH_FINAL_VAL_DEFAULT 0x300
+#define SCP_CLK_L1_SRAM_PD REG32(SCP_CLK_BASE + 0x80)
+#define SCP_CLK_TCM_TAIL_SRAM_PD REG32(SCP_CLK_BASE + 0x94)
 
 #ifdef CHIP_VARIANT_MT8186
-#define SCP_CLK_CTRL_GENERAL_CTRL	REG32(SCP_CLK_BASE + 0x9C)
+#define SCP_CLK_CTRL_GENERAL_CTRL REG32(SCP_CLK_BASE + 0x9C)
 #endif
 
-#define SCP_CLK_SLEEP			REG32(SCP_CLK_BASE + 0xA0)
-#define   SLOW_WAKE_DISABLE		1
-#define SCP_FAST_WAKE_CNT_END		REG32(SCP_CLK_BASE + 0xA4)
-#define   FAST_WAKE_CNT_END_MASK	0xfff
-#define   FAST_WAKE_CNT_END_DEFAULT	0x18
-#define   MEM_CK_CS_ISO_CNT_END_MASK	0x7f0000
+#define SCP_CLK_SLEEP REG32(SCP_CLK_BASE + 0xA0)
+#define SLOW_WAKE_DISABLE 1
+#define SCP_FAST_WAKE_CNT_END REG32(SCP_CLK_BASE + 0xA4)
+#define FAST_WAKE_CNT_END_MASK 0xfff
+#define FAST_WAKE_CNT_END_DEFAULT 0x18
+#define MEM_CK_CS_ISO_CNT_END_MASK 0x7f0000
 
 /* Peripherals */
-#define SCP_I2C0_BASE			(SCP_CFG_BASE + 0x5000)
-#define SCP_I2C1_BASE			(SCP_CFG_BASE + 0x6000)
-#define SCP_I2C2_BASE			(SCP_CFG_BASE + 0x7000)
+#define SCP_I2C0_BASE (SCP_CFG_BASE + 0x5000)
+#define SCP_I2C1_BASE (SCP_CFG_BASE + 0x6000)
+#define SCP_I2C2_BASE (SCP_CFG_BASE + 0x7000)
 
-#define SCP_GPIO_BASE			(SCP_CFG_BASE + 0x8000)
-#define SCP_UART0_BASE			(SCP_CFG_BASE + 0x9000)
-#define SCP_UART1_BASE			(SCP_CFG_BASE + 0xE000)
-#define SCP_UART_COUNT			2
+#define SCP_GPIO_BASE (SCP_CFG_BASE + 0x8000)
+#define SCP_UART0_BASE (SCP_CFG_BASE + 0x9000)
+#define SCP_UART1_BASE (SCP_CFG_BASE + 0xE000)
+#define SCP_UART_COUNT 2
 
 /* External GPIO interrupt */
-#define SCP_EINT_BASE			(SCP_CFG_BASE + 0xA000)
-#define SCP_EINT_STATUS			REG32_ADDR(SCP_EINT_BASE)
-#define SCP_EINT_ACK			REG32_ADDR(SCP_EINT_BASE + 0x040)
-#define SCP_EINT_MASK_GET		REG32_ADDR(SCP_EINT_BASE + 0x080)
-#define SCP_EINT_MASK_SET		REG32_ADDR(SCP_EINT_BASE + 0x0C0)
-#define SCP_EINT_MASK_CLR		REG32_ADDR(SCP_EINT_BASE + 0x100)
-#define SCP_EINT_SENS_GET		REG32_ADDR(SCP_EINT_BASE + 0x140)
-#define SCP_EINT_SENS_SET		REG32_ADDR(SCP_EINT_BASE + 0x180)
-#define SCP_EINT_SENS_CLR		REG32_ADDR(SCP_EINT_BASE + 0x1C0)
-#define SCP_EINT_SOFT_GET		REG32_ADDR(SCP_EINT_BASE + 0x200)
-#define SCP_EINT_SOFT_SET		REG32_ADDR(SCP_EINT_BASE + 0x240)
-#define SCP_EINT_SOFT_CLR		REG32_ADDR(SCP_EINT_BASE + 0x280)
-#define SCP_EINT_POLARITY_GET		REG32_ADDR(SCP_EINT_BASE + 0x300)
-#define SCP_EINT_POLARITY_SET		REG32_ADDR(SCP_EINT_BASE + 0x340)
-#define SCP_EINT_POLARITY_CLR		REG32_ADDR(SCP_EINT_BASE + 0x380)
-#define SCP_EINT_D0_EN			REG32_ADDR(SCP_EINT_BASE + 0x400)
-#define SCP_EINT_D1_EN			REG32_ADDR(SCP_EINT_BASE + 0x420)
-#define SCP_EINT_DBNC_GET		REG32_ADDR(SCP_EINT_BASE + 0x500)
-#define SCP_EINT_DBNC_SET		REG32_ADDR(SCP_EINT_BASE + 0x600)
-#define SCP_EINT_DBNC_CLR		REG32_ADDR(SCP_EINT_BASE + 0x700)
-
-#define SCP_PMICWP2P_BASE		(SCP_CFG_BASE + 0xB000)
-#define   PMICW_WACS_CMD		REG32(SCP_PMICWP2P_BASE + 0x200)
-#define   PMICW_WACS_RDATA		REG32(SCP_PMICWP2P_BASE + 0x204)
-#define   PMICW_WACS_VLDCLR		REG32(SCP_PMICWP2P_BASE + 0x208)
-#define SCP_SPMP2P_BASE			(SCP_CFG_BASE + 0xC000)
-#define SCP_DMA_BASE			(SCP_CFG_BASE + 0xD000)
-#define   DMA_ACKINT_CHX		REG32(SCP_DMA_BASE + 0x20)
-#define SCP_SPI0_BASE			(SCP_CFG_BASE + 0xF000)
-#define SCP_SPI1_BASE			(SCP_CFG_BASE + 0x10000)
-#define SCP_SPI2_BASE			(SCP_CFG_BASE + 0x11000)
+#define SCP_EINT_BASE (SCP_CFG_BASE + 0xA000)
+#define SCP_EINT_STATUS REG32_ADDR(SCP_EINT_BASE)
+#define SCP_EINT_ACK REG32_ADDR(SCP_EINT_BASE + 0x040)
+#define SCP_EINT_MASK_GET REG32_ADDR(SCP_EINT_BASE + 0x080)
+#define SCP_EINT_MASK_SET REG32_ADDR(SCP_EINT_BASE + 0x0C0)
+#define SCP_EINT_MASK_CLR REG32_ADDR(SCP_EINT_BASE + 0x100)
+#define SCP_EINT_SENS_GET REG32_ADDR(SCP_EINT_BASE + 0x140)
+#define SCP_EINT_SENS_SET REG32_ADDR(SCP_EINT_BASE + 0x180)
+#define SCP_EINT_SENS_CLR REG32_ADDR(SCP_EINT_BASE + 0x1C0)
+#define SCP_EINT_SOFT_GET REG32_ADDR(SCP_EINT_BASE + 0x200)
+#define SCP_EINT_SOFT_SET REG32_ADDR(SCP_EINT_BASE + 0x240)
+#define SCP_EINT_SOFT_CLR REG32_ADDR(SCP_EINT_BASE + 0x280)
+#define SCP_EINT_POLARITY_GET REG32_ADDR(SCP_EINT_BASE + 0x300)
+#define SCP_EINT_POLARITY_SET REG32_ADDR(SCP_EINT_BASE + 0x340)
+#define SCP_EINT_POLARITY_CLR REG32_ADDR(SCP_EINT_BASE + 0x380)
+#define SCP_EINT_D0_EN REG32_ADDR(SCP_EINT_BASE + 0x400)
+#define SCP_EINT_D1_EN REG32_ADDR(SCP_EINT_BASE + 0x420)
+#define SCP_EINT_DBNC_GET REG32_ADDR(SCP_EINT_BASE + 0x500)
+#define SCP_EINT_DBNC_SET REG32_ADDR(SCP_EINT_BASE + 0x600)
+#define SCP_EINT_DBNC_CLR REG32_ADDR(SCP_EINT_BASE + 0x700)
+
+#define SCP_PMICWP2P_BASE (SCP_CFG_BASE + 0xB000)
+#define PMICW_WACS_CMD REG32(SCP_PMICWP2P_BASE + 0x200)
+#define PMICW_WACS_RDATA REG32(SCP_PMICWP2P_BASE + 0x204)
+#define PMICW_WACS_VLDCLR REG32(SCP_PMICWP2P_BASE + 0x208)
+#define SCP_SPMP2P_BASE (SCP_CFG_BASE + 0xC000)
+#define SCP_DMA_BASE (SCP_CFG_BASE + 0xD000)
+#define DMA_ACKINT_CHX REG32(SCP_DMA_BASE + 0x20)
+#define SCP_SPI0_BASE (SCP_CFG_BASE + 0xF000)
+#define SCP_SPI1_BASE (SCP_CFG_BASE + 0x10000)
+#define SCP_SPI2_BASE (SCP_CFG_BASE + 0x11000)
 
 #define CACHE_ICACHE 0
 #define CACHE_DCACHE 1
 #define CACHE_COUNT 2
-#define SCP_CACHE_BASE			(SCP_CFG_BASE + 0x14000)
-#define SCP_CACHE_SEL(x)		(SCP_CACHE_BASE + (x)*0x3000)
-#define SCP_CACHE_CON(x)		REG32(SCP_CACHE_SEL(x))
-#define SCP_CACHE_CON_MCEN		BIT(0)
-#define SCP_CACHE_CON_CNTEN0		BIT(2)
-#define SCP_CACHE_CON_CNTEN1		BIT(3)
-#define SCP_CACHE_CON_CACHESIZE_SHIFT	8
-#define SCP_CACHE_CON_CACHESIZE_MASK	(0x3 << SCP_CACHE_CON_CACHESIZE_SHIFT)
-#define SCP_CACHE_CON_CACHESIZE_0KB	(0x0 << SCP_CACHE_CON_CACHESIZE_SHIFT)
-#define SCP_CACHE_CON_CACHESIZE_8KB	(0x1 << SCP_CACHE_CON_CACHESIZE_SHIFT)
-#define SCP_CACHE_CON_CACHESIZE_16KB	(0x2 << SCP_CACHE_CON_CACHESIZE_SHIFT)
-#define SCP_CACHE_CON_CACHESIZE_32KB	(0x3 << SCP_CACHE_CON_CACHESIZE_SHIFT)
-#define SCP_CACHE_CON_WAYEN		BIT(10)
-
-#define SCP_CACHE_OP(x)			REG32(SCP_CACHE_SEL(x) + 0x04)
-#define SCP_CACHE_OP_EN			BIT(0)
-#define SCP_CACHE_OP_OP_SHIFT		1
-#define SCP_CACHE_OP_OP_MASK		(0xf << SCP_CACHE_OP_OP_SHIFT)
-
-#define   OP_INVALIDATE_ALL_LINES		(0x1 << SCP_CACHE_OP_OP_SHIFT)
-#define   OP_INVALIDATE_ONE_LINE_BY_ADDRESS	(0x2 << SCP_CACHE_OP_OP_SHIFT)
-#define   OP_INVALIDATE_ONE_LINE_BY_SET_WAY	(0x4 << SCP_CACHE_OP_OP_SHIFT)
-#define   OP_CACHE_FLUSH_ALL_LINES		(0x9 << SCP_CACHE_OP_OP_SHIFT)
-#define   OP_CACHE_FLUSH_ONE_LINE_BY_ADDRESS	(0xa << SCP_CACHE_OP_OP_SHIFT)
-#define   OP_CACHE_FLUSH_ONE_LINE_BY_SET_WAY	(0xc << SCP_CACHE_OP_OP_SHIFT)
-
-#define SCP_CACHE_OP_TADDR_SHIFT	5
-#define SCP_CACHE_OP_TADDR_MASK		(0x7ffffff << SCP_CACHE_OP_TADDR_SHIFT)
-#define SCP_CACHE_LINE_SIZE		BIT(SCP_CACHE_OP_TADDR_SHIFT)
+#define SCP_CACHE_BASE (SCP_CFG_BASE + 0x14000)
+#define SCP_CACHE_SEL(x) (SCP_CACHE_BASE + (x)*0x3000)
+#define SCP_CACHE_CON(x) REG32(SCP_CACHE_SEL(x))
+#define SCP_CACHE_CON_MCEN BIT(0)
+#define SCP_CACHE_CON_CNTEN0 BIT(2)
+#define SCP_CACHE_CON_CNTEN1 BIT(3)
+#define SCP_CACHE_CON_CACHESIZE_SHIFT 8
+#define SCP_CACHE_CON_CACHESIZE_MASK (0x3 << SCP_CACHE_CON_CACHESIZE_SHIFT)
+#define SCP_CACHE_CON_CACHESIZE_0KB (0x0 << SCP_CACHE_CON_CACHESIZE_SHIFT)
+#define SCP_CACHE_CON_CACHESIZE_8KB (0x1 << SCP_CACHE_CON_CACHESIZE_SHIFT)
+#define SCP_CACHE_CON_CACHESIZE_16KB (0x2 << SCP_CACHE_CON_CACHESIZE_SHIFT)
+#define SCP_CACHE_CON_CACHESIZE_32KB (0x3 << SCP_CACHE_CON_CACHESIZE_SHIFT)
+#define SCP_CACHE_CON_WAYEN BIT(10)
+
+#define SCP_CACHE_OP(x) REG32(SCP_CACHE_SEL(x) + 0x04)
+#define SCP_CACHE_OP_EN BIT(0)
+#define SCP_CACHE_OP_OP_SHIFT 1
+#define SCP_CACHE_OP_OP_MASK (0xf << SCP_CACHE_OP_OP_SHIFT)
+
+#define OP_INVALIDATE_ALL_LINES (0x1 << SCP_CACHE_OP_OP_SHIFT)
+#define OP_INVALIDATE_ONE_LINE_BY_ADDRESS (0x2 << SCP_CACHE_OP_OP_SHIFT)
+#define OP_INVALIDATE_ONE_LINE_BY_SET_WAY (0x4 << SCP_CACHE_OP_OP_SHIFT)
+#define OP_CACHE_FLUSH_ALL_LINES (0x9 << SCP_CACHE_OP_OP_SHIFT)
+#define OP_CACHE_FLUSH_ONE_LINE_BY_ADDRESS (0xa << SCP_CACHE_OP_OP_SHIFT)
+#define OP_CACHE_FLUSH_ONE_LINE_BY_SET_WAY (0xc << SCP_CACHE_OP_OP_SHIFT)
+
+#define SCP_CACHE_OP_TADDR_SHIFT 5
+#define SCP_CACHE_OP_TADDR_MASK (0x7ffffff << SCP_CACHE_OP_TADDR_SHIFT)
+#define SCP_CACHE_LINE_SIZE BIT(SCP_CACHE_OP_TADDR_SHIFT)
 
 /* Cache statistics */
-#define SCP_CACHE_HCNT0L(x)		REG32(SCP_CACHE_SEL(x) + 0x08)
-#define SCP_CACHE_HCNT0U(x)		REG32(SCP_CACHE_SEL(x) + 0x0c)
-#define SCP_CACHE_CCNT0L(x)		REG32(SCP_CACHE_SEL(x) + 0x10)
-#define SCP_CACHE_CCNT0U(x)		REG32(SCP_CACHE_SEL(x) + 0x14)
-#define SCP_CACHE_HCNT1L(x)		REG32(SCP_CACHE_SEL(x) + 0x18)
-#define SCP_CACHE_HCNT1U(x)		REG32(SCP_CACHE_SEL(x) + 0x1c)
-#define SCP_CACHE_CCNT1L(x)		REG32(SCP_CACHE_SEL(x) + 0x20)
-#define SCP_CACHE_CCNT1U(x)		REG32(SCP_CACHE_SEL(x) + 0x24)
-
-#define SCP_CACHE_REGION_EN(x)		REG32(SCP_CACHE_SEL(x) + 0x2c)
-
-#define SCP_CACHE_ENTRY_BASE(x)		(SCP_CACHE_SEL(x) + 0x2000)
-#define SCP_CACHE_ENTRY(x, reg)		REG32(SCP_CACHE_ENTRY_BASE(x) + (reg)*4)
-#define SCP_CACHE_END_ENTRY_BASE(x)	(SCP_CACHE_SEL(x) + 0x2040)
-#define SCP_CACHE_END_ENTRY(x, reg)	REG32(SCP_CACHE_END_ENTRY_BASE(x) + \
-						(reg)*4)
-#define SCP_CACHE_ENTRY_C		BIT(8)
-#define SCP_CACHE_ENTRY_BASEADDR_MASK	(0xfffff << 12)
+#define SCP_CACHE_HCNT0L(x) REG32(SCP_CACHE_SEL(x) + 0x08)
+#define SCP_CACHE_HCNT0U(x) REG32(SCP_CACHE_SEL(x) + 0x0c)
+#define SCP_CACHE_CCNT0L(x) REG32(SCP_CACHE_SEL(x) + 0x10)
+#define SCP_CACHE_CCNT0U(x) REG32(SCP_CACHE_SEL(x) + 0x14)
+#define SCP_CACHE_HCNT1L(x) REG32(SCP_CACHE_SEL(x) + 0x18)
+#define SCP_CACHE_HCNT1U(x) REG32(SCP_CACHE_SEL(x) + 0x1c)
+#define SCP_CACHE_CCNT1L(x) REG32(SCP_CACHE_SEL(x) + 0x20)
+#define SCP_CACHE_CCNT1U(x) REG32(SCP_CACHE_SEL(x) + 0x24)
+
+#define SCP_CACHE_REGION_EN(x) REG32(SCP_CACHE_SEL(x) + 0x2c)
+
+#define SCP_CACHE_ENTRY_BASE(x) (SCP_CACHE_SEL(x) + 0x2000)
+#define SCP_CACHE_ENTRY(x, reg) REG32(SCP_CACHE_ENTRY_BASE(x) + (reg)*4)
+#define SCP_CACHE_END_ENTRY_BASE(x) (SCP_CACHE_SEL(x) + 0x2040)
+#define SCP_CACHE_END_ENTRY(x, reg) REG32(SCP_CACHE_END_ENTRY_BASE(x) + (reg)*4)
+#define SCP_CACHE_ENTRY_C BIT(8)
+#define SCP_CACHE_ENTRY_BASEADDR_MASK (0xfffff << 12)
 
 /* ARMV7 regs */
-#define ARM_SCB_SCR			REG32(0xE000ED10)
-#define   SCR_DEEPSLEEP			BIT(2)
+#define ARM_SCB_SCR REG32(0xE000ED10)
+#define SCR_DEEPSLEEP BIT(2)
 
 /* AP regs */
-#define AP_BASE				0xA0000000
-#define TOPCK_BASE			AP_BASE /* Top clock */
-#define SCP_UART2_BASE			(AP_BASE + 0x01002000) /* AP UART0 */
+#define AP_BASE 0xA0000000
+#define TOPCK_BASE AP_BASE /* Top clock */
+#define SCP_UART2_BASE (AP_BASE + 0x01002000) /* AP UART0 */
 
 /* CLK_CFG_5 regs */
-#define AP_CLK_CFG_5		REG32(TOPCK_BASE + 0x0090)
-#define   PWRAP_ULPOSC_MASK	(0x3000000)
-#define   CLK26M			(0 << 24)
-#define   OSC_D16			(1 << 24)
-#define   OSC_D4			(2 << 24)
-#define   OSC_D8			(3 << 24)
-#define AP_CLK_CFG_5_CLR	REG32(TOPCK_BASE + 0x0098)
-#define   PWRAP_ULPOSC_CG	BIT(31)
+#define AP_CLK_CFG_5 REG32(TOPCK_BASE + 0x0090)
+#define PWRAP_ULPOSC_MASK (0x3000000)
+#define CLK26M (0 << 24)
+#define OSC_D16 (1 << 24)
+#define OSC_D4 (2 << 24)
+#define OSC_D8 (3 << 24)
+#define AP_CLK_CFG_5_CLR REG32(TOPCK_BASE + 0x0098)
+#define PWRAP_ULPOSC_CG BIT(31)
 
 #ifdef CHIP_VARIANT_MT8186
 /* SCP PLL MUX RG */
-#define CLK_CFG_UPDATE          (TOPCK_BASE + 0x0004)
-#define SCP_CK_UPDATE_SHFT      1
-#define CLK_CFG_0               (TOPCK_BASE + 0x0040)
-#define CLK_CFG_0_SET           (TOPCK_BASE + 0x0044)
-#define CLK_CFG_0_CLR           (TOPCK_BASE + 0x0048)
-#define CLK_SCP_SEL_MSK     0x7
-#define CLK_SCP_SEL_SHFT    8
+#define CLK_CFG_UPDATE (TOPCK_BASE + 0x0004)
+#define SCP_CK_UPDATE_SHFT 1
+#define CLK_CFG_0 (TOPCK_BASE + 0x0040)
+#define CLK_CFG_0_SET (TOPCK_BASE + 0x0044)
+#define CLK_CFG_0_CLR (TOPCK_BASE + 0x0048)
+#define CLK_SCP_SEL_MSK 0x7
+#define CLK_SCP_SEL_SHFT 8
 #endif
 
 /* OSC meter */
 #ifdef CHIP_VARIANT_MT8186
-#define AP_CLK_MISC_CFG_0		REG32(TOPCK_BASE + 0x0140)
-#define AP_CLK_DBG_CFG			REG32(TOPCK_BASE + 0x017C)
+#define AP_CLK_MISC_CFG_0 REG32(TOPCK_BASE + 0x0140)
+#define AP_CLK_DBG_CFG REG32(TOPCK_BASE + 0x017C)
 #else
-#define AP_CLK_MISC_CFG_0		REG32(TOPCK_BASE + 0x0104)
-#define AP_CLK_DBG_CFG                  REG32(TOPCK_BASE + 0x010C)
+#define AP_CLK_MISC_CFG_0 REG32(TOPCK_BASE + 0x0104)
+#define AP_CLK_DBG_CFG REG32(TOPCK_BASE + 0x010C)
 #endif
 
-#define   MISC_METER_DIVISOR_MASK	0xff000000
-#define   MISC_METER_DIV_1		0
-#define   DBG_MODE_MASK			3
-#define   DBG_MODE_SET_CLOCK            0
-#define   DBG_BIST_SOURCE_MASK		(0x3f << 16)
+#define MISC_METER_DIVISOR_MASK 0xff000000
+#define MISC_METER_DIV_1 0
+#define DBG_MODE_MASK 3
+#define DBG_MODE_SET_CLOCK 0
+#define DBG_BIST_SOURCE_MASK (0x3f << 16)
 
 #ifdef CHIP_VARIANT_MT8186
-#define   DBG_BIST_SOURCE_ULPOSC1	(35 << 16)
-#define   DBG_BIST_SOURCE_ULPOSC2	(34 << 16)
+#define DBG_BIST_SOURCE_ULPOSC1 (35 << 16)
+#define DBG_BIST_SOURCE_ULPOSC2 (34 << 16)
 #else
-#define   DBG_BIST_SOURCE_ULPOSC1	(0x26 << 16)
-#define   DBG_BIST_SOURCE_ULPOSC2	(0x25 << 16)
+#define DBG_BIST_SOURCE_ULPOSC1 (0x26 << 16)
+#define DBG_BIST_SOURCE_ULPOSC2 (0x25 << 16)
 #endif
 
-#define AP_SCP_CFG_0			REG32(TOPCK_BASE + 0x0220)
-#define   CFG_FREQ_METER_RUN		(1 << 4)
-#define   CFG_FREQ_METER_ENABLE		(1 << 12)
-#define AP_SCP_CFG_1			REG32(TOPCK_BASE + 0x0224)
-#define   CFG_FREQ_COUNTER(CFG1)	((CFG1) & 0xFFFF)
+#define AP_SCP_CFG_0 REG32(TOPCK_BASE + 0x0220)
+#define CFG_FREQ_METER_RUN (1 << 4)
+#define CFG_FREQ_METER_ENABLE (1 << 12)
+#define AP_SCP_CFG_1 REG32(TOPCK_BASE + 0x0224)
+#define CFG_FREQ_COUNTER(CFG1) ((CFG1)&0xFFFF)
 
 /* GPIO */
-#define AP_GPIO_BASE			(AP_BASE + 0x00005000)
+#define AP_GPIO_BASE (AP_BASE + 0x00005000)
 /*
  * AP_GPIO_DIR
  * GPIO input/out direction, 1 bit per pin.
  * 0:input 1:output
  */
-#define AP_GPIO_DIR(n)			REG32(AP_GPIO_BASE + ((n) << 4))
+#define AP_GPIO_DIR(n) REG32(AP_GPIO_BASE + ((n) << 4))
 /*
  * AP_GPIO_DOUT, n in [0..5]
  * GPIO output level, 1 bit per pin
  * 0:low 1:high
  */
-#define AP_GPIO_DOUT(n)			REG32(AP_GPIO_BASE + 0x100 + ((n) << 4))
+#define AP_GPIO_DOUT(n) REG32(AP_GPIO_BASE + 0x100 + ((n) << 4))
 /*
  * AP_GPIO_DIN, n in [0..5]
  * GPIO input level, 1 bit per pin
  * 0:low 1:high
  */
-#define AP_GPIO_DIN(n)			REG32(AP_GPIO_BASE + 0x200 + ((n) << 4))
+#define AP_GPIO_DIN(n) REG32(AP_GPIO_BASE + 0x200 + ((n) << 4))
 /*
  * AP_GPIO_MODE, n in [0..22]
  * Pin mode selection, 4 bit per pin
  * bit3   - write enable, set to 1 for hw to fetch bit2,1,0.
  * bit2-0 - mode 0 ~ 7
  */
-#define AP_GPIO_MODE(n)			REG32(AP_GPIO_BASE + 0x300 + ((n) << 4))
-#define AP_GPIO_TRAP			REG32(AP_GPIO_BASE + 0x6B0)
-#define AP_GPIO_UNIMPLEMENTED		REG32(AP_GPIO_BASE + 0x6C0)
-#define AP_GPIO_DBG			REG32(AP_GPIO_BASE + 0x6D0)
-#define AP_GPIO_BANK			REG32(AP_GPIO_BASE + 0x6E0)
+#define AP_GPIO_MODE(n) REG32(AP_GPIO_BASE + 0x300 + ((n) << 4))
+#define AP_GPIO_TRAP REG32(AP_GPIO_BASE + 0x6B0)
+#define AP_GPIO_UNIMPLEMENTED REG32(AP_GPIO_BASE + 0x6C0)
+#define AP_GPIO_DBG REG32(AP_GPIO_BASE + 0x6D0)
+#define AP_GPIO_BANK REG32(AP_GPIO_BASE + 0x6E0)
 /* AP_GPIO_SEC, n in [0..5] */
-#define AP_GPIO_SEC(n)			REG32(AP_GPIO_BASE + 0xF00 + ((n) << 4))
+#define AP_GPIO_SEC(n) REG32(AP_GPIO_BASE + 0xF00 + ((n) << 4))
 
 #ifdef CHIP_VARIANT_MT8186
-#define AP_PLL_CON0			REG32(AP_BASE + 0xC000)
-#define LTECLKSQ_EN			BIT(0)
-#define LTECLKSQ_LPF_EN			BIT(1)
-#define LTECLKSQ_HYS_EN			BIT(2)
-#define LTECLKSQ_VOD_EN			BIT(3)
-#define LTECLKSQ_HYS_SEL		(0x1 << 4)
-#define CLKSQ_RESERVE			(0x1 << 10)
-#define SSUSB26M_CK2_EN			BIT(13)
-#define SSUSB26M_CK_EN			BIT(14)
-#define XTAL26M_CK_EN			BIT(15)
-#define ULPOSC_CTRL_SEL			(0xf << 16)
+#define AP_PLL_CON0 REG32(AP_BASE + 0xC000)
+#define LTECLKSQ_EN BIT(0)
+#define LTECLKSQ_LPF_EN BIT(1)
+#define LTECLKSQ_HYS_EN BIT(2)
+#define LTECLKSQ_VOD_EN BIT(3)
+#define LTECLKSQ_HYS_SEL (0x1 << 4)
+#define CLKSQ_RESERVE (0x1 << 10)
+#define SSUSB26M_CK2_EN BIT(13)
+#define SSUSB26M_CK_EN BIT(14)
+#define XTAL26M_CK_EN BIT(15)
+#define ULPOSC_CTRL_SEL (0xf << 16)
 #endif
 
 /*
@@ -667,15 +660,15 @@
  * osc: 0 for ULPOSC1, 1 for ULPSOC2.
  */
 #ifdef CHIP_VARIANT_MT8186
-#define AP_ULPOSC_BASE0			(AP_BASE + 0xC500)
-#define AP_ULPOSC_BASE1			(AP_BASE + 0xC504)
-#define AP_ULPOSC_CON02(osc)		REG32(AP_ULPOSC_BASE0 + (osc) * 0x80)
-#define AP_ULPOSC_CON13(osc)		REG32(AP_ULPOSC_BASE1 + (osc) * 0x80)
+#define AP_ULPOSC_BASE0 (AP_BASE + 0xC500)
+#define AP_ULPOSC_BASE1 (AP_BASE + 0xC504)
+#define AP_ULPOSC_CON02(osc) REG32(AP_ULPOSC_BASE0 + (osc)*0x80)
+#define AP_ULPOSC_CON13(osc) REG32(AP_ULPOSC_BASE1 + (osc)*0x80)
 #else
-#define AP_ULPOSC_BASE0			(AP_BASE + 0xC700)
-#define AP_ULPOSC_BASE1			(AP_BASE + 0xC704)
-#define AP_ULPOSC_CON02(osc)		REG32(AP_ULPOSC_BASE0 + (osc) * 0x8)
-#define AP_ULPOSC_CON13(osc)		REG32(AP_ULPOSC_BASE1 + (osc) * 0x8)
+#define AP_ULPOSC_BASE0 (AP_BASE + 0xC700)
+#define AP_ULPOSC_BASE1 (AP_BASE + 0xC704)
+#define AP_ULPOSC_CON02(osc) REG32(AP_ULPOSC_BASE0 + (osc)*0x8)
+#define AP_ULPOSC_CON13(osc) REG32(AP_ULPOSC_BASE1 + (osc)*0x8)
 #endif
 /*
  * AP_ULPOSC_CON[0,2]
@@ -687,25 +680,25 @@
  * bit24-31: reserved
  */
 #ifdef CHIP_VARIANT_MT8186
-#define OSC_CALI_MASK			0x3f
-#define OSC_IBAND_SHIFT			6
-#define OSC_FBAND_MASK			0xf
-#define OSC_FBAND_SHIFT			13
-#define OSC_DIV_SHIFT			17
+#define OSC_CALI_MASK 0x3f
+#define OSC_IBAND_SHIFT 6
+#define OSC_FBAND_MASK 0xf
+#define OSC_FBAND_SHIFT 13
+#define OSC_DIV_SHIFT 17
 #else
-#define OSC_CALI_MSK			(0x3f << 0)
-#define OSC_CALI_BITS			6
-#define OSC_IBAND_MASK			(0x7f << 6)
-#define OSC_FBAND_MASK			(0x0f << 13)
-#define OSC_DIV_MASK			(0x1f << 17)
-#define OSC_DIV_BITS			5
-#define OSC_RESERVED_MASK		(0xff << 24)
+#define OSC_CALI_MSK (0x3f << 0)
+#define OSC_CALI_BITS 6
+#define OSC_IBAND_MASK (0x7f << 6)
+#define OSC_FBAND_MASK (0x0f << 13)
+#define OSC_DIV_MASK (0x1f << 17)
+#define OSC_DIV_BITS 5
+#define OSC_RESERVED_MASK (0xff << 24)
 #endif
 
-#define OSC_CP_EN			BIT(23)
+#define OSC_CP_EN BIT(23)
 /* AP_ULPOSC_CON[1,3] */
-#define OSC_MOD_MASK			(0x03 << 0)
-#define OSC_DIV2_EN			BIT(2)
+#define OSC_MOD_MASK (0x03 << 0)
+#define OSC_DIV2_EN BIT(2)
 
 #define UNIMPLEMENTED_GPIO_BANK 0
 
@@ -719,24 +712,24 @@
  * 3. Trace clk disable - gate trace clock
  * 4. DCM for CPU stall - gate CPU clock when CPU stall
  */
-#define CM4_MODIFICATION		REG32(0xE00FE000)
-#define CM4_DCM_FEATURE			REG32(0xE00FE004)
+#define CM4_MODIFICATION REG32(0xE00FE000)
+#define CM4_DCM_FEATURE REG32(0xE00FE004)
 /* UART, 16550 compatible */
-#define SCP_UART_BASE(n)		CONCAT3(SCP_UART, n, _BASE)
-#define UART_REG(n, offset)		REG32_ADDR(SCP_UART_BASE(n))[offset]
-#define UART_IRQ(n)			CONCAT2(SCP_IRQ_UART, n)
-#define UART_RX_IRQ(n)			CONCAT3(SCP_IRQ_UART, n, _RX)
+#define SCP_UART_BASE(n) CONCAT3(SCP_UART, n, _BASE)
+#define UART_REG(n, offset) REG32_ADDR(SCP_UART_BASE(n))[offset]
+#define UART_IRQ(n) CONCAT2(SCP_IRQ_UART, n)
+#define UART_RX_IRQ(n) CONCAT3(SCP_IRQ_UART, n, _RX)
 
 /* Watchdog */
-#define SCP_WDT_BASE			(SCP_CFG_BASE + 0x84)
-#define SCP_WDT_REG(offset)		REG32(SCP_WDT_BASE + offset)
-#define SCP_WDT_CFG			SCP_WDT_REG(0)
-#define   SCP_WDT_FREQ			33825
-#define   SCP_WDT_MAX_PERIOD		0xFFFFF /* 31 seconds */
-#define   SCP_WDT_PERIOD(ms)		(SCP_WDT_FREQ * (ms) / 1000)
-#define   SCP_WDT_ENABLE		BIT(31)
-#define SCP_WDT_RELOAD			SCP_WDT_REG(4)
-#define   SCP_WDT_RELOAD_VALUE		1
+#define SCP_WDT_BASE (SCP_CFG_BASE + 0x84)
+#define SCP_WDT_REG(offset) REG32(SCP_WDT_BASE + offset)
+#define SCP_WDT_CFG SCP_WDT_REG(0)
+#define SCP_WDT_FREQ 33825
+#define SCP_WDT_MAX_PERIOD 0xFFFFF /* 31 seconds */
+#define SCP_WDT_PERIOD(ms) (SCP_WDT_FREQ * (ms) / 1000)
+#define SCP_WDT_ENABLE BIT(31)
+#define SCP_WDT_RELOAD SCP_WDT_REG(4)
+#define SCP_WDT_RELOAD_VALUE 1
 
 #endif /* !__ASSEMBLER__ */
 #endif /* __CROS_EC_REGISTERS_H */
diff --git a/chip/mt_scp/mt818x/serial_reg.h b/chip/mt_scp/mt818x/serial_reg.h
index 5344566272..8dd2864a98 100644
--- a/chip/mt_scp/mt818x/serial_reg.h
+++ b/chip/mt_scp/mt818x/serial_reg.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,72 +19,72 @@
  *   (Read) Rcvr buffer register
  *   (Write) Xmit holding register
  */
-#define UART_DATA(n)			UART_REG(n, 0)
+#define UART_DATA(n) UART_REG(n, 0)
 /* (Write) Interrupt enable register */
-#define UART_IER(n)			UART_REG(n, 1)
-#define UART_IER_RDI			BIT(0) /* Recv data int */
-#define UART_IER_THRI			BIT(1) /* Xmit holding register int */
-#define UART_IER_RLSI			BIT(2) /* Rcvr line status int */
-#define UART_IER_MSI			BIT(3) /* Modem status int */
+#define UART_IER(n) UART_REG(n, 1)
+#define UART_IER_RDI BIT(0) /* Recv data int */
+#define UART_IER_THRI BIT(1) /* Xmit holding register int */
+#define UART_IER_RLSI BIT(2) /* Rcvr line status int */
+#define UART_IER_MSI BIT(3) /* Modem status int */
 /* (Read) Interrupt ID register */
-#define UART_IIR(n)			UART_REG(n, 2)
-#define UART_IIR_NO_INT			BIT(0) /* No int pending */
-#define UART_IIR_ID_MASK		0x0e /* Interrupt ID mask */
-#define UART_IIR_MSI			0x00
-#define UART_IIR_THRI			0x02
-#define UART_IIR_RDI			0x04
-#define UART_IIR_RLSI			0x06
-#define UART_IIR_BUSY			0x07 /* DW APB busy */
+#define UART_IIR(n) UART_REG(n, 2)
+#define UART_IIR_NO_INT BIT(0) /* No int pending */
+#define UART_IIR_ID_MASK 0x0e /* Interrupt ID mask */
+#define UART_IIR_MSI 0x00
+#define UART_IIR_THRI 0x02
+#define UART_IIR_RDI 0x04
+#define UART_IIR_RLSI 0x06
+#define UART_IIR_BUSY 0x07 /* DW APB busy */
 /* (Write) FIFO control register */
-#define UART_FCR(n)			UART_REG(n, 2)
-#define UART_FCR_ENABLE_FIFO		BIT(0) /* Enable FIFO */
-#define UART_FCR_CLEAR_RCVR		BIT(1) /* Clear rcvr FIFO */
-#define UART_FCR_CLEAR_XMIT		BIT(2) /* Clear xmit FIFO */
-#define UART_FCR_DMA_SELECT		BIT(3)
+#define UART_FCR(n) UART_REG(n, 2)
+#define UART_FCR_ENABLE_FIFO BIT(0) /* Enable FIFO */
+#define UART_FCR_CLEAR_RCVR BIT(1) /* Clear rcvr FIFO */
+#define UART_FCR_CLEAR_XMIT BIT(2) /* Clear xmit FIFO */
+#define UART_FCR_DMA_SELECT BIT(3)
 /* FIFO trigger levels */
-#define UART_FCR_T_TRIG_00		0x00
-#define UART_FCR_T_TRIG_01		0x10
-#define UART_FCR_T_TRIG_10		0x20
-#define UART_FCR_T_TRIG_11		0x30
-#define UART_FCR_R_TRIG_00		0x00
-#define UART_FCR_R_TRIG_01		0x40
-#define UART_FCR_R_TRIG_10		0x80
-#define UART_FCR_R_TRIG_11		0x80
+#define UART_FCR_T_TRIG_00 0x00
+#define UART_FCR_T_TRIG_01 0x10
+#define UART_FCR_T_TRIG_10 0x20
+#define UART_FCR_T_TRIG_11 0x30
+#define UART_FCR_R_TRIG_00 0x00
+#define UART_FCR_R_TRIG_01 0x40
+#define UART_FCR_R_TRIG_10 0x80
+#define UART_FCR_R_TRIG_11 0x80
 /* (Write) Line control register */
-#define UART_LCR(n)			UART_REG(n, 3)
-#define UART_LCR_WLEN5			0 /* Word length 5 bits */
-#define UART_LCR_WLEN6			1
-#define UART_LCR_WLEN7			2
-#define UART_LCR_WLEN8			3
-#define UART_LCR_STOP			BIT(2) /* Stop bits: 1bit, 2bits */
-#define UART_LCR_PARITY			BIT(3) /* Parity enable */
-#define UART_LCR_EPAR			BIT(4) /* Even parity */
-#define UART_LCR_SPAR			BIT(5) /* Stick parity */
-#define UART_LCR_SBC			BIT(6) /* Set break control */
-#define UART_LCR_DLAB			BIT(7) /* Divisor latch access */
+#define UART_LCR(n) UART_REG(n, 3)
+#define UART_LCR_WLEN5 0 /* Word length 5 bits */
+#define UART_LCR_WLEN6 1
+#define UART_LCR_WLEN7 2
+#define UART_LCR_WLEN8 3
+#define UART_LCR_STOP BIT(2) /* Stop bits: 1bit, 2bits */
+#define UART_LCR_PARITY BIT(3) /* Parity enable */
+#define UART_LCR_EPAR BIT(4) /* Even parity */
+#define UART_LCR_SPAR BIT(5) /* Stick parity */
+#define UART_LCR_SBC BIT(6) /* Set break control */
+#define UART_LCR_DLAB BIT(7) /* Divisor latch access */
 /* (Write) Modem control register */
-#define UART_MCR(n)			UART_REG(n, 4)
+#define UART_MCR(n) UART_REG(n, 4)
 /* (Read) Line status register */
-#define UART_LSR(n)			UART_REG(n, 5)
-#define UART_LSR_DR			BIT(0) /* Data ready */
-#define UART_LSR_OE			BIT(1) /* Overrun error */
-#define UART_LSR_PE			BIT(2) /* Parity error */
-#define UART_LSR_FE			BIT(3) /* Frame error */
-#define UART_LSR_BI			BIT(4) /* Break interrupt */
-#define UART_LSR_THRE			BIT(5) /* Xmit-hold-register empty */
-#define UART_LSR_TEMT			BIT(6) /* Xmit empty */
-#define UART_LSR_FIFOE			BIT(7) /* FIFO error */
+#define UART_LSR(n) UART_REG(n, 5)
+#define UART_LSR_DR BIT(0) /* Data ready */
+#define UART_LSR_OE BIT(1) /* Overrun error */
+#define UART_LSR_PE BIT(2) /* Parity error */
+#define UART_LSR_FE BIT(3) /* Frame error */
+#define UART_LSR_BI BIT(4) /* Break interrupt */
+#define UART_LSR_THRE BIT(5) /* Xmit-hold-register empty */
+#define UART_LSR_TEMT BIT(6) /* Xmit empty */
+#define UART_LSR_FIFOE BIT(7) /* FIFO error */
 
 /* DLAB == 1 */
 
 /* (Write) Divisor latch */
-#define UART_DLL(n)			UART_REG(n, 0) /* Low */
-#define UART_DLH(n)			UART_REG(n, 1) /* High */
+#define UART_DLL(n) UART_REG(n, 0) /* Low */
+#define UART_DLH(n) UART_REG(n, 1) /* High */
 
 /* MTK extension */
-#define UART_HIGHSPEED(n)		UART_REG(n, 9)
-#define UART_SAMPLE_COUNT(n)		UART_REG(n, 10)
-#define UART_SAMPLE_POINT(n)		UART_REG(n, 11)
-#define UART_RATE_FIX(n)		UART_REG(n, 13)
+#define UART_HIGHSPEED(n) UART_REG(n, 9)
+#define UART_SAMPLE_COUNT(n) UART_REG(n, 10)
+#define UART_SAMPLE_POINT(n) UART_REG(n, 11)
+#define UART_RATE_FIX(n) UART_REG(n, 13)
 
 #endif /* __CROS_EC_SERIAL_REG_H */
diff --git a/chip/mt_scp/mt818x/system.c b/chip/mt_scp/mt818x/system.c
index d07bd394a0..8bf523c0f7 100644
--- a/chip/mt_scp/mt818x/system.c
+++ b/chip/mt_scp/mt818x/system.c
@@ -1,10 +1,11 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* System : hardware specific implementation */
 
+#include "builtin/assert.h"
 #include "clock_chip.h"
 #include "console.h"
 #include "cpu.h"
@@ -80,9 +81,7 @@ void system_pre_init(void)
 	scp_cm4_mod();
 
 	/* Clock */
-	#ifdef CHIP_VARIANT_MT8183
 	scp_enable_clock();
-	#endif
 
 	/* Peripheral IRQ */
 	scp_enable_pirq();
@@ -127,7 +126,8 @@ void system_reset(int flags)
 		}
 	}
 
-	/* Set watchdog timer to small value, and spin wait for watchdog reset */
+	/* Set watchdog timer to small value, and spin wait for watchdog reset
+	 */
 	SCP_WDT_CFG = 0;
 	SCP_WDT_CFG = SCP_WDT_ENABLE | SCP_WDT_PERIOD(1);
 	watchdog_reload();
@@ -162,12 +162,9 @@ static void check_reset_cause(void)
 int system_is_reboot_warm(void)
 {
 	const uint32_t cold_flags =
-		EC_RESET_FLAG_RESET_PIN |
-		EC_RESET_FLAG_POWER_ON  |
-		EC_RESET_FLAG_WATCHDOG  |
-		EC_RESET_FLAG_HARD      |
-		EC_RESET_FLAG_SOFT      |
-		EC_RESET_FLAG_HIBERNATE;
+		EC_RESET_FLAG_RESET_PIN | EC_RESET_FLAG_POWER_ON |
+		EC_RESET_FLAG_WATCHDOG | EC_RESET_FLAG_HARD |
+		EC_RESET_FLAG_SOFT | EC_RESET_FLAG_HIBERNATE;
 
 	check_reset_cause();
 
diff --git a/chip/mt_scp/mt818x/uart.c b/chip/mt_scp/mt818x/uart.c
index 109f8b595b..6bcfa89d9b 100644
--- a/chip/mt_scp/mt818x/uart.c
+++ b/chip/mt_scp/mt818x/uart.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,7 @@
 #include "util.h"
 
 /* Console UART index */
-#define UARTN           CONFIG_UART_CONSOLE
+#define UARTN CONFIG_UART_CONSOLE
 #define UART_IDLE_WAIT_US 500
 
 static uint8_t uart_done, tx_started;
@@ -155,9 +155,8 @@ void uart_init(void)
 #endif
 
 	/* Init and clear FIFO */
-	UART_FCR(UARTN) = UART_FCR_ENABLE_FIFO
-		| UART_FCR_CLEAR_RCVR
-		| UART_FCR_CLEAR_XMIT;
+	UART_FCR(UARTN) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR |
+			  UART_FCR_CLEAR_XMIT;
 	/* Line control: parity none, 8 bit, 1 stop bit */
 	UART_LCR(UARTN) = UART_LCR_WLEN8;
 	/* For baud rate <= 115200 */
@@ -175,6 +174,5 @@ void uart_init(void)
 	/* UART RX IRQ needs an extra enable */
 	SCP_INTC_UART_RX_IRQ |= 1 << UARTN;
 #endif
-	gpio_config_module(MODULE_UART, 1);
 	uart_done = 1;
 }
diff --git a/chip/mt_scp/mt818x/watchdog.c b/chip/mt_scp/mt818x/watchdog.c
index 74e2cad8e5..efadeab0fd 100644
--- a/chip/mt_scp/mt818x/watchdog.c
+++ b/chip/mt_scp/mt818x/watchdog.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/mt_scp/mt8192/build.mk b/chip/mt_scp/mt8192/build.mk
index e61cdafb01..c188ea6d17 100644
--- a/chip/mt_scp/mt8192/build.mk
+++ b/chip/mt_scp/mt8192/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/chip/mt_scp/mt8192/clock.c b/chip/mt_scp/mt8192/clock.c
index 43f570fc62..665695a7a2 100644
--- a/chip/mt_scp/mt8192/clock.c
+++ b/chip/mt_scp/mt8192/clock.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -36,19 +36,35 @@ static struct opp_ulposc_cfg {
 	uint32_t target_mhz;
 } opp[] = {
 	{
-		.osc = 1, .target_mhz = 196, .div = 20, .fband = 10, .mod = 3,
+		.osc = 1,
+		.target_mhz = 196,
+		.div = 20,
+		.fband = 10,
+		.mod = 3,
 		.cali = 64,
 	},
 	{
-		.osc = 0, .target_mhz = 260, .div = 14, .fband = 2, .mod = 0,
+		.osc = 0,
+		.target_mhz = 260,
+		.div = 14,
+		.fband = 2,
+		.mod = 0,
 		.cali = 64,
 	},
 	{
-		.osc = 1, .target_mhz = 280, .div = 20, .fband = 2, .mod = 0,
+		.osc = 1,
+		.target_mhz = 280,
+		.div = 20,
+		.fband = 2,
+		.mod = 0,
 		.cali = 64,
 	},
 	{
-		.osc = 1, .target_mhz = 360, .div = 20, .fband = 10, .mod = 0,
+		.osc = 1,
+		.target_mhz = 360,
+		.div = 20,
+		.fband = 10,
+		.mod = 0,
 		.cali = 64,
 	},
 };
@@ -112,13 +128,12 @@ static uint32_t clock_ulposc_measure_freq(uint32_t osc)
 	int cnt;
 
 	/* before select meter clock input, bit[1:0] = b00 */
-	AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_MODE_MASK) |
-			 DBG_MODE_SET_CLOCK;
+	AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_MODE_MASK) | DBG_MODE_SET_CLOCK;
 
 	/* select source, bit[21:16] = clk_src */
-	AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_BIST_SOURCE_MASK) |
-			 (osc == 0 ? DBG_BIST_SOURCE_ULPOSC1 :
-				     DBG_BIST_SOURCE_ULPOSC2);
+	AP_CLK_DBG_CFG =
+		(AP_CLK_DBG_CFG & ~DBG_BIST_SOURCE_MASK) |
+		(osc == 0 ? DBG_BIST_SOURCE_ULPOSC1 : DBG_BIST_SOURCE_ULPOSC2);
 
 	/* set meter divisor to 1, bit[31:24] = b00000000 */
 	AP_CLK_MISC_CFG_0 = (AP_CLK_MISC_CFG_0 & ~MISC_METER_DIVISOR_MASK) |
@@ -152,7 +167,7 @@ static uint32_t clock_ulposc_measure_freq(uint32_t osc)
 	return result;
 }
 
-#define CAL_MIS_RATE	40
+#define CAL_MIS_RATE 40
 static int clock_ulposc_is_calibrated(struct opp_ulposc_cfg *opp)
 {
 	uint32_t curr, target;
@@ -278,8 +293,8 @@ static void clock_calibrate_ulposc(struct opp_ulposc_cfg *opp)
 		opp->cali = clock_ulposc_process_cali(opp);
 
 #ifdef DEBUG
-	CPRINTF("osc:%u, target=%uMHz, cal:%u\n",
-		opp->osc, opp->target_mhz, opp->cali);
+	CPRINTF("osc:%u, target=%uMHz, cal:%u\n", opp->osc, opp->target_mhz,
+		opp->cali);
 #endif
 }
 
@@ -327,12 +342,12 @@ void clock_init(void)
 	SCP_SYS_CTRL |= AUTO_DDREN;
 
 	/* set settle time */
-	SCP_CLK_SYS_VAL =
-		(SCP_CLK_SYS_VAL & ~CLK_SYS_VAL_MASK) | CLK_SYS_VAL_VAL(1);
-	SCP_CLK_HIGH_VAL =
-		(SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) | CLK_HIGH_VAL_VAL(1);
-	SCP_SLEEP_CTRL =
-		(SCP_SLEEP_CTRL & ~VREQ_COUNT_MASK) | VREQ_COUNT_VAL(1);
+	SCP_CLK_SYS_VAL = (SCP_CLK_SYS_VAL & ~CLK_SYS_VAL_MASK) |
+			  CLK_SYS_VAL_VAL(1);
+	SCP_CLK_HIGH_VAL = (SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) |
+			   CLK_HIGH_VAL_VAL(1);
+	SCP_SLEEP_CTRL = (SCP_SLEEP_CTRL & ~VREQ_COUNT_MASK) |
+			 VREQ_COUNT_VAL(1);
 
 	/* turn off ULPOSC2 */
 	SCP_CLK_ON_CTRL |= HIGH_CORE_DIS_SUB;
@@ -349,17 +364,16 @@ void clock_init(void)
 
 	/* enable default clock gate */
 	SCP_SET_CLK_CG |= CG_DMA_CH3 | CG_DMA_CH2 | CG_DMA_CH1 | CG_DMA_CH0 |
-		CG_I2C_MCLK | CG_MAD_MCLK | CG_AP2P_MCLK;
+			  CG_I2C_MCLK | CG_MAD_MCLK | CG_AP2P_MCLK;
 }
 
 #ifdef DEBUG
-int command_ulposc(int argc, char *argv[])
+int command_ulposc(int argc, const char *argv[])
 {
 	int i;
 
 	for (i = 0; i <= 1; ++i)
-		ccprintf("ULPOSC%u frequency: %u kHz\n",
-			 i + 1,
+		ccprintf("ULPOSC%u frequency: %u kHz\n", i + 1,
 			 clock_ulposc_measure_freq(i) * 26 * 1000 / 1024);
 
 	return EC_SUCCESS;
diff --git a/chip/mt_scp/mt8192/clock_regs.h b/chip/mt_scp/mt8192/clock_regs.h
index 5928ca0473..7e1f77e92d 100644
--- a/chip/mt_scp/mt8192/clock_regs.h
+++ b/chip/mt_scp/mt8192/clock_regs.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,48 +9,45 @@
 #define __CROS_EC_CLOCK_REGS_H
 
 /* clock source select */
-#define SCP_CLK_SW_SEL			REG32(SCP_CLK_CTRL_BASE + 0x0000)
-#define   CLK_SW_SEL_26M		0
-#define   CLK_SW_SEL_32K		1
-#define   CLK_SW_SEL_ULPOSC2		2
-#define   CLK_SW_SEL_ULPOSC1		3
-#define SCP_CLK_ENABLE			REG32(SCP_CLK_CTRL_BASE + 0x0004)
-#define   CLK_HIGH_EN			BIT(1) /* ULPOSC */
-#define   CLK_HIGH_CG			BIT(2)
+#define SCP_CLK_SW_SEL REG32(SCP_CLK_CTRL_BASE + 0x0000)
+#define CLK_SW_SEL_26M 0
+#define CLK_SW_SEL_32K 1
+#define CLK_SW_SEL_ULPOSC2 2
+#define CLK_SW_SEL_ULPOSC1 3
+#define SCP_CLK_ENABLE REG32(SCP_CLK_CTRL_BASE + 0x0004)
+#define CLK_HIGH_EN BIT(1) /* ULPOSC */
+#define CLK_HIGH_CG BIT(2)
 /* clock general control */
-#define SCP_CLK_CTRL_GENERAL_CTRL	REG32(SCP_CLK_CTRL_BASE + 0x009C)
-#define   VREQ_PMIC_WRAP_SEL		(0x2)
+#define SCP_CLK_CTRL_GENERAL_CTRL REG32(SCP_CLK_CTRL_BASE + 0x009C)
+#define VREQ_PMIC_WRAP_SEL (0x2)
 
 /* TOPCK clk */
-#define TOPCK_BASE			AP_REG_BASE
-#define AP_CLK_MISC_CFG_0		REG32(TOPCK_BASE + 0x0140)
-#define   MISC_METER_DIVISOR_MASK	0xff000000
-#define   MISC_METER_DIV_1		0
+#define TOPCK_BASE AP_REG_BASE
+#define AP_CLK_MISC_CFG_0 REG32(TOPCK_BASE + 0x0140)
+#define MISC_METER_DIVISOR_MASK 0xff000000
+#define MISC_METER_DIV_1 0
 /* OSC meter */
-#define AP_CLK_DBG_CFG			REG32(TOPCK_BASE + 0x017C)
-#define   DBG_MODE_MASK			3
-#define   DBG_MODE_SET_CLOCK		0
-#define   DBG_BIST_SOURCE_MASK		(0x3f << 16)
-#define   DBG_BIST_SOURCE_ULPOSC1	(0x25 << 16)
-#define   DBG_BIST_SOURCE_ULPOSC2	(0x24 << 16)
-#define AP_SCP_CFG_0			REG32(TOPCK_BASE + 0x0220)
-#define   CFG_FREQ_METER_RUN		BIT(4)
-#define   CFG_FREQ_METER_ENABLE		BIT(12)
-#define AP_SCP_CFG_1			REG32(TOPCK_BASE + 0x0224)
-#define   CFG_FREQ_COUNTER(CFG1)	((CFG1) & 0xFFFF)
+#define AP_CLK_DBG_CFG REG32(TOPCK_BASE + 0x017C)
+#define DBG_MODE_MASK 3
+#define DBG_MODE_SET_CLOCK 0
+#define DBG_BIST_SOURCE_MASK (0x3f << 16)
+#define DBG_BIST_SOURCE_ULPOSC1 (0x25 << 16)
+#define DBG_BIST_SOURCE_ULPOSC2 (0x24 << 16)
+#define AP_SCP_CFG_0 REG32(TOPCK_BASE + 0x0220)
+#define CFG_FREQ_METER_RUN BIT(4)
+#define CFG_FREQ_METER_ENABLE BIT(12)
+#define AP_SCP_CFG_1 REG32(TOPCK_BASE + 0x0224)
+#define CFG_FREQ_COUNTER(CFG1) ((CFG1)&0xFFFF)
 /*
  * ULPOSC
  * osc: 0 for ULPOSC1, 1 for ULPOSC2.
  */
-#define AP_ULPOSC_CON0_BASE		(AP_REG_BASE + 0xC2B0)
-#define AP_ULPOSC_CON1_BASE		(AP_REG_BASE + 0xC2B4)
-#define AP_ULPOSC_CON2_BASE		(AP_REG_BASE + 0xC2B8)
-#define AP_ULPOSC_CON0(osc) \
-		REG32(AP_ULPOSC_CON0_BASE + (osc) * 0x10)
-#define AP_ULPOSC_CON1(osc) \
-		REG32(AP_ULPOSC_CON1_BASE + (osc) * 0x10)
-#define AP_ULPOSC_CON2(osc) \
-		REG32(AP_ULPOSC_CON2_BASE + (osc) * 0x10)
+#define AP_ULPOSC_CON0_BASE (AP_REG_BASE + 0xC2B0)
+#define AP_ULPOSC_CON1_BASE (AP_REG_BASE + 0xC2B4)
+#define AP_ULPOSC_CON2_BASE (AP_REG_BASE + 0xC2B8)
+#define AP_ULPOSC_CON0(osc) REG32(AP_ULPOSC_CON0_BASE + (osc)*0x10)
+#define AP_ULPOSC_CON1(osc) REG32(AP_ULPOSC_CON1_BASE + (osc)*0x10)
+#define AP_ULPOSC_CON2(osc) REG32(AP_ULPOSC_CON2_BASE + (osc)*0x10)
 /*
  * AP_ULPOSC_CON0
  * bit0-6: calibration
@@ -60,11 +57,11 @@
  * bit24: cp_en
  * bit25-31: reserved
  */
-#define OSC_CALI_MASK			0x7f
-#define OSC_IBAND_SHIFT			7
-#define OSC_FBAND_SHIFT			14
-#define OSC_DIV_SHIFT			18
-#define OSC_CP_EN			BIT(24)
+#define OSC_CALI_MASK 0x7f
+#define OSC_IBAND_SHIFT 7
+#define OSC_FBAND_SHIFT 14
+#define OSC_DIV_SHIFT 18
+#define OSC_CP_EN BIT(24)
 /* AP_ULPOSC_CON1
  * bit0-7: 32K calibration
  * bit 8-15: rsv1
@@ -73,10 +70,10 @@
  * bit26: div2_en
  * bit27-31: reserved
  */
-#define OSC_RSV1_SHIFT			8
-#define OSC_RSV2_SHIFT			16
-#define OSC_MOD_SHIFT			24
-#define OSC_DIV2_EN			BIT(26)
+#define OSC_RSV1_SHIFT 8
+#define OSC_RSV2_SHIFT 16
+#define OSC_MOD_SHIFT 24
+#define OSC_DIV2_EN BIT(26)
 /* AP_ULPOSC_CON2
  * bit0-7: bias
  * bit8-31: reserved
diff --git a/chip/mt_scp/mt8192/intc.h b/chip/mt_scp/mt8192/intc.h
index 63eb1243b3..6c1d3c549c 100644
--- a/chip/mt_scp/mt8192/intc.h
+++ b/chip/mt_scp/mt8192/intc.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,120 +7,120 @@
 #define __CROS_EC_INTC_H
 
 /* INTC */
-#define SCP_INTC_IRQ_POL0		0xef001f20
-#define SCP_INTC_IRQ_POL1		0x0800001d
-#define SCP_INTC_IRQ_POL2		0x00000020
-#define SCP_INTC_GRP_LEN		3
-#define SCP_INTC_IRQ_COUNT		96
+#define SCP_INTC_IRQ_POL0 0xef001f20
+#define SCP_INTC_IRQ_POL1 0x0800001d
+#define SCP_INTC_IRQ_POL2 0x00000020
+#define SCP_INTC_GRP_LEN 3
+#define SCP_INTC_IRQ_COUNT 96
 
 /* IRQ numbers */
-#define SCP_IRQ_GIPC_IN0		0
-#define SCP_IRQ_GIPC_IN1		1
-#define SCP_IRQ_GIPC_IN2		2
-#define SCP_IRQ_GIPC_IN3		3
+#define SCP_IRQ_GIPC_IN0 0
+#define SCP_IRQ_GIPC_IN1 1
+#define SCP_IRQ_GIPC_IN2 2
+#define SCP_IRQ_GIPC_IN3 3
 /* 4 */
-#define SCP_IRQ_SPM			4
-#define SCP_IRQ_AP_CIRQ			5
-#define SCP_IRQ_EINT			6
-#define SCP_IRQ_PMIC			7
+#define SCP_IRQ_SPM 4
+#define SCP_IRQ_AP_CIRQ 5
+#define SCP_IRQ_EINT 6
+#define SCP_IRQ_PMIC 7
 /* 8 */
-#define SCP_IRQ_UART0_TX		8
-#define SCP_IRQ_UART1_TX		9
-#define SCP_IRQ_I2C0			10
-#define SCP_IRQ_I2C1_0			11
+#define SCP_IRQ_UART0_TX 8
+#define SCP_IRQ_UART1_TX 9
+#define SCP_IRQ_I2C0 10
+#define SCP_IRQ_I2C1_0 11
 /* 12 */
-#define SCP_IRQ_BUS_DBG_TRACKER		12
-#define SCP_IRQ_CLK_CTRL		13
-#define SCP_IRQ_VOW			14
-#define SCP_IRQ_TIMER0			15
+#define SCP_IRQ_BUS_DBG_TRACKER 12
+#define SCP_IRQ_CLK_CTRL 13
+#define SCP_IRQ_VOW 14
+#define SCP_IRQ_TIMER0 15
 /* 16 */
-#define SCP_IRQ_TIMER1			16
-#define SCP_IRQ_TIMER2			17
-#define SCP_IRQ_TIMER3			18
-#define SCP_IRQ_TIMER4			19
+#define SCP_IRQ_TIMER1 16
+#define SCP_IRQ_TIMER2 17
+#define SCP_IRQ_TIMER3 18
+#define SCP_IRQ_TIMER4 19
 /* 20 */
-#define SCP_IRQ_TIMER5			20
-#define SCP_IRQ_OS_TIMER		21
-#define SCP_IRQ_UART0_RX		22
-#define SCP_IRQ_UART1_RX		23
+#define SCP_IRQ_TIMER5 20
+#define SCP_IRQ_OS_TIMER 21
+#define SCP_IRQ_UART0_RX 22
+#define SCP_IRQ_UART1_RX 23
 /* 24 */
-#define SCP_IRQ_GDMA			24
-#define SCP_IRQ_AUDIO			25
-#define SCP_IRQ_MD_DSP			26
-#define SCP_IRQ_ADSP			27
+#define SCP_IRQ_GDMA 24
+#define SCP_IRQ_AUDIO 25
+#define SCP_IRQ_MD_DSP 26
+#define SCP_IRQ_ADSP 27
 /* 28 */
-#define SCP_IRQ_CPU_TICK		28
-#define SCP_IRQ_SPI0			29
-#define SCP_IRQ_SPI1			30
-#define SCP_IRQ_SPI2			31
+#define SCP_IRQ_CPU_TICK 28
+#define SCP_IRQ_SPI0 29
+#define SCP_IRQ_SPI1 30
+#define SCP_IRQ_SPI2 31
 /* 32 */
-#define SCP_IRQ_NEW_INFRA_SYS_CIRQ	32
-#define SCP_IRQ_DBG			33
-#define SCP_IRQ_CCIF0			34
-#define SCP_IRQ_CCIF1			35
+#define SCP_IRQ_NEW_INFRA_SYS_CIRQ 32
+#define SCP_IRQ_DBG 33
+#define SCP_IRQ_CCIF0 34
+#define SCP_IRQ_CCIF1 35
 /* 36 */
-#define SCP_IRQ_CCIF2			36
-#define SCP_IRQ_WDT			37
-#define SCP_IRQ_USB0			38
-#define SCP_IRQ_USB1			39
+#define SCP_IRQ_CCIF2 36
+#define SCP_IRQ_WDT 37
+#define SCP_IRQ_USB0 38
+#define SCP_IRQ_USB1 39
 /* 40 */
-#define SCP_IRQ_DPMAIF			40
-#define SCP_IRQ_INFRA			41
-#define SCP_IRQ_CLK_CTRL_CORE		42
-#define SCP_IRQ_CLK_CTRL2_CORE		43
+#define SCP_IRQ_DPMAIF 40
+#define SCP_IRQ_INFRA 41
+#define SCP_IRQ_CLK_CTRL_CORE 42
+#define SCP_IRQ_CLK_CTRL2_CORE 43
 /* 44 */
-#define SCP_IRQ_CLK_CTRL2		44
-#define SCP_IRQ_GIPC_IN4		45 /* HALT */
-#define SCP_IRQ_PERIBUS_TIMEOUT		46
-#define SCP_IRQ_INFRABUS_TIMEOUT	47
+#define SCP_IRQ_CLK_CTRL2 44
+#define SCP_IRQ_GIPC_IN4 45 /* HALT */
+#define SCP_IRQ_PERIBUS_TIMEOUT 46
+#define SCP_IRQ_INFRABUS_TIMEOUT 47
 /* 48 */
-#define SCP_IRQ_MET0			48
-#define SCP_IRQ_MET1			49
-#define SCP_IRQ_MET2			50
-#define SCP_IRQ_MET3			51
+#define SCP_IRQ_MET0 48
+#define SCP_IRQ_MET1 49
+#define SCP_IRQ_MET2 50
+#define SCP_IRQ_MET3 51
 /* 52 */
-#define SCP_IRQ_AP_WDT			52
-#define SCP_IRQ_L2TCM_SEC_VIO		53
-#define SCP_IRQ_CPU_TICK1		54
-#define SCP_IRQ_MAD_DATAIN		55
+#define SCP_IRQ_AP_WDT 52
+#define SCP_IRQ_L2TCM_SEC_VIO 53
+#define SCP_IRQ_CPU_TICK1 54
+#define SCP_IRQ_MAD_DATAIN 55
 /* 56 */
-#define SCP_IRQ_I3C0_IBI_WAKE		56
-#define SCP_IRQ_I3C1_IBI_WAKE		57
-#define SCP_IRQ_I3C2_IBI_WAKE		58
-#define SCP_IRQ_APU_ENGINE		59
+#define SCP_IRQ_I3C0_IBI_WAKE 56
+#define SCP_IRQ_I3C1_IBI_WAKE 57
+#define SCP_IRQ_I3C2_IBI_WAKE 58
+#define SCP_IRQ_APU_ENGINE 59
 /* 60 */
-#define SCP_IRQ_MBOX0			60
-#define SCP_IRQ_MBOX1			61
-#define SCP_IRQ_MBOX2			62
-#define SCP_IRQ_MBOX3			63
+#define SCP_IRQ_MBOX0 60
+#define SCP_IRQ_MBOX1 61
+#define SCP_IRQ_MBOX2 62
+#define SCP_IRQ_MBOX3 63
 /* 64 */
-#define SCP_IRQ_MBOX4			64
-#define SCP_IRQ_SYS_CLK_REQ		65
-#define SCP_IRQ_BUS_REQ			66
-#define SCP_IRQ_APSRC_REQ		67
+#define SCP_IRQ_MBOX4 64
+#define SCP_IRQ_SYS_CLK_REQ 65
+#define SCP_IRQ_BUS_REQ 66
+#define SCP_IRQ_APSRC_REQ 67
 /* 68 */
-#define SCP_IRQ_APU_MBOX		68
-#define SCP_IRQ_DEVAPC_SECURE_VIO	69
+#define SCP_IRQ_APU_MBOX 68
+#define SCP_IRQ_DEVAPC_SECURE_VIO 69
 /* 72 */
 /* 76 */
-#define SCP_IRQ_I2C1_2			78
-#define SCP_IRQ_I2C2			79
+#define SCP_IRQ_I2C1_2 78
+#define SCP_IRQ_I2C2 79
 /* 80 */
-#define SCP_IRQ_AUD2AUDIODSP		80
-#define SCP_IRQ_AUD2AUDIODSP_2		81
-#define SCP_IRQ_CONN2ADSP_A2DPOL	82
-#define SCP_IRQ_CONN2ADSP_BTCVSD	83
+#define SCP_IRQ_AUD2AUDIODSP 80
+#define SCP_IRQ_AUD2AUDIODSP_2 81
+#define SCP_IRQ_CONN2ADSP_A2DPOL 82
+#define SCP_IRQ_CONN2ADSP_BTCVSD 83
 /* 84 */
-#define SCP_IRQ_CONN2ADSP_BLEISO	84
-#define SCP_IRQ_PCIE2ADSP		85
-#define SCP_IRQ_APU2ADSP_ENGINE		86
-#define SCP_IRQ_APU2ADSP_MBOX		87
+#define SCP_IRQ_CONN2ADSP_BLEISO 84
+#define SCP_IRQ_PCIE2ADSP 85
+#define SCP_IRQ_APU2ADSP_ENGINE 86
+#define SCP_IRQ_APU2ADSP_MBOX 87
 /* 88 */
-#define SCP_IRQ_CCIF3			88
-#define SCP_IRQ_I2C_DMA0		89
-#define SCP_IRQ_I2C_DMA1		90
-#define SCP_IRQ_I2C_DMA2		91
+#define SCP_IRQ_CCIF3 88
+#define SCP_IRQ_I2C_DMA0 89
+#define SCP_IRQ_I2C_DMA1 90
+#define SCP_IRQ_I2C_DMA2 91
 /* 92 */
-#define SCP_IRQ_I2C_DMA3		92
+#define SCP_IRQ_I2C_DMA3 92
 
 #endif /* __CROS_EC_INTC_H */
diff --git a/chip/mt_scp/mt8192/uart.c b/chip/mt_scp/mt8192/uart.c
index 0ebb93cbb4..da17857edf 100644
--- a/chip/mt_scp/mt8192/uart.c
+++ b/chip/mt_scp/mt8192/uart.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,10 +19,6 @@ void uart_init_pinmux(void)
 #if UARTN == 0
 	SCP_UART_CK_SEL |= UART0_CK_SEL_VAL(UART_CK_SEL_ULPOSC);
 	SCP_SET_CLK_CG |= CG_UART0_MCLK | CG_UART0_BCLK | CG_UART0_RST;
-
-	/* set AP GPIO164 and GPIO165 to alt func 3 */
-	AP_GPIO_MODE20_CLR = 0x00770000;
-	AP_GPIO_MODE20_SET = 0x00330000;
 #elif UARTN == 1
 	SCP_UART_CK_SEL |= UART1_CK_SEL_VAL(UART_CK_SEL_ULPOSC);
 	SCP_SET_CLK_CG |= CG_UART1_MCLK | CG_UART1_BCLK | CG_UART1_RST;
diff --git a/chip/mt_scp/mt8192/video.c b/chip/mt_scp/mt8192/video.c
index 2f9b9a7808..8cb4f9588e 100644
--- a/chip/mt_scp/mt8192/video.c
+++ b/chip/mt_scp/mt8192/video.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,7 +13,6 @@ uint32_t video_get_enc_capability(void)
 
 uint32_t video_get_dec_capability(void)
 {
-	return VDEC_CAP_4K_DISABLED | VDEC_CAP_MM21 |
-		VDEC_CAP_H264_SLICE | VDEC_CAP_VP8_FRAME |
-		VDEC_CAP_VP9_FRAME;
+	return VDEC_CAP_4K_DISABLED | VDEC_CAP_MM21 | VDEC_CAP_H264_SLICE |
+	       VDEC_CAP_VP8_FRAME | VDEC_CAP_VP9_FRAME;
 }
diff --git a/chip/mt_scp/mt8195/build.mk b/chip/mt_scp/mt8195/build.mk
index e61cdafb01..c188ea6d17 100644
--- a/chip/mt_scp/mt8195/build.mk
+++ b/chip/mt_scp/mt8195/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/chip/mt_scp/mt8195/clock.c b/chip/mt_scp/mt8195/clock.c
index f3b32ab52e..2ed3fab4a1 100644
--- a/chip/mt_scp/mt8195/clock.c
+++ b/chip/mt_scp/mt8195/clock.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -106,8 +106,8 @@ static void clock_ulposc_config_default(struct opp_ulposc_cfg *opp)
 	AP_ULPOSC_CON1(opp->osc) = val;
 
 	/* set settle time */
-	SCP_CLK_HIGH_VAL =
-		(SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) | CLK_HIGH_VAL_VAL(2);
+	SCP_CLK_HIGH_VAL = (SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) |
+			   CLK_HIGH_VAL_VAL(2);
 }
 
 static void clock_ulposc_config_cali(struct opp_ulposc_cfg *opp,
@@ -137,13 +137,12 @@ static uint32_t clock_ulposc_measure_freq(uint32_t osc)
 	AP_CLK26CALI_1 = CFG_CKGEN_LOAD_CNT;
 
 	/* before select meter clock input, bit[1:0] = b00 */
-	AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_MODE_MASK) |
-			 DBG_MODE_SET_CLOCK;
+	AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_MODE_MASK) | DBG_MODE_SET_CLOCK;
 
 	/* select monclk_ext2fqmtr_sel: AP_CLK_DBG_CFG[14:8] */
-	AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_BIST_SOURCE_MASK) |
-			 (osc == 0 ? DBG_BIST_SOURCE_ULPOSC1 :
-				     DBG_BIST_SOURCE_ULPOSC2);
+	AP_CLK_DBG_CFG =
+		(AP_CLK_DBG_CFG & ~DBG_BIST_SOURCE_MASK) |
+		(osc == 0 ? DBG_BIST_SOURCE_ULPOSC1 : DBG_BIST_SOURCE_ULPOSC2);
 
 	/* set meter divisor to 1, bit[31:24] = b00000000 */
 	AP_CLK_MISC_CFG_0 = (AP_CLK_MISC_CFG_0 & ~MISC_METER_DIVISOR_MASK) |
@@ -176,7 +175,7 @@ static uint32_t clock_ulposc_measure_freq(uint32_t osc)
 	return result;
 }
 
-#define CAL_MIS_RATE	40
+#define CAL_MIS_RATE 40
 static int clock_ulposc_is_calibrated(struct opp_ulposc_cfg *opp)
 {
 	uint32_t curr, target;
@@ -185,8 +184,8 @@ static int clock_ulposc_is_calibrated(struct opp_ulposc_cfg *opp)
 	target = opp->target_mhz * 512 / 26;
 
 #ifdef DEBUG
-	CPRINTF("osc:%u, target=%uMHz, curr=%uMHz, cali:%u\n",
-		opp->osc, opp->target_mhz, (curr * 26) / 512, opp->cali);
+	CPRINTF("osc:%u, target=%uMHz, curr=%uMHz, cali:%u\n", opp->osc,
+		opp->target_mhz, (curr * 26) / 512, opp->cali);
 #endif
 
 	/* check if calibrated value is in the range of target value +- 4% */
@@ -401,7 +400,7 @@ void sr_task(void *u)
 	uint32_t event;
 	uint32_t prev, now;
 
-	while(1) {
+	while (1) {
 		switch (state) {
 		case SR_S0:
 			event = task_wait_event(-1);
@@ -463,12 +462,12 @@ void clock_init(void)
 	SCP_SYS_CTRL |= AUTO_DDREN;
 
 	/* set settle time */
-	SCP_CLK_SYS_VAL =
-		(SCP_CLK_SYS_VAL & ~CLK_SYS_VAL_MASK) | CLK_SYS_VAL_VAL(1);
-	SCP_CLK_HIGH_VAL =
-		(SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) | CLK_HIGH_VAL_VAL(1);
-	SCP_SLEEP_CTRL =
-		(SCP_SLEEP_CTRL & ~VREQ_COUNT_MASK) | VREQ_COUNT_VAL(1);
+	SCP_CLK_SYS_VAL = (SCP_CLK_SYS_VAL & ~CLK_SYS_VAL_MASK) |
+			  CLK_SYS_VAL_VAL(1);
+	SCP_CLK_HIGH_VAL = (SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) |
+			   CLK_HIGH_VAL_VAL(1);
+	SCP_SLEEP_CTRL = (SCP_SLEEP_CTRL & ~VREQ_COUNT_MASK) |
+			 VREQ_COUNT_VAL(1);
 
 	/* turn off ULPOSC2 */
 	SCP_CLK_ON_CTRL |= HIGH_CORE_DIS_SUB;
@@ -489,7 +488,7 @@ void clock_init(void)
 }
 
 #ifdef DEBUG
-int command_ulposc(int argc, char *argv[])
+int command_ulposc(int argc, const char *argv[])
 {
 	uint32_t osc;
 
diff --git a/chip/mt_scp/mt8195/clock_regs.h b/chip/mt_scp/mt8195/clock_regs.h
index 6e7ec6bdbb..7744c3df54 100644
--- a/chip/mt_scp/mt8195/clock_regs.h
+++ b/chip/mt_scp/mt8195/clock_regs.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,55 +9,53 @@
 #define __CROS_EC_CLOCK_REGS_H
 
 /* clock source select */
-#define SCP_CLK_SW_SEL			REG32(SCP_CLK_CTRL_BASE + 0x0000)
-#define   CLK_SW_SEL_SYSTEM		0
-#define   CLK_SW_SEL_32K		1
-#define   CLK_SW_SEL_ULPOSC2		2
-#define   CLK_SW_SEL_ULPOSC1		3
-#define SCP_CLK_ENABLE			REG32(SCP_CLK_CTRL_BASE + 0x0004)
-#define   CLK_HIGH_EN			BIT(1) /* ULPOSC */
-#define   CLK_HIGH_CG			BIT(2)
+#define SCP_CLK_SW_SEL REG32(SCP_CLK_CTRL_BASE + 0x0000)
+#define CLK_SW_SEL_SYSTEM 0
+#define CLK_SW_SEL_32K 1
+#define CLK_SW_SEL_ULPOSC2 2
+#define CLK_SW_SEL_ULPOSC1 3
+#define SCP_CLK_ENABLE REG32(SCP_CLK_CTRL_BASE + 0x0004)
+#define CLK_HIGH_EN BIT(1) /* ULPOSC */
+#define CLK_HIGH_CG BIT(2)
 /* clock general control */
-#define SCP_CLK_CTRL_GENERAL_CTRL	REG32(SCP_CLK_CTRL_BASE + 0x009C)
-#define   VREQ_PMIC_WRAP_SEL		(0x3)
+#define SCP_CLK_CTRL_GENERAL_CTRL REG32(SCP_CLK_CTRL_BASE + 0x009C)
+#define VREQ_PMIC_WRAP_SEL (0x3)
 
 /* TOPCK clk */
-#define TOPCK_BASE			AP_REG_BASE
-#define AP_CLK_CFG_UPDATE3		REG32(TOPCK_BASE + 0x0010)
-#define   F_ULPOSC_CK_UPDATE		BIT(21)
-#define   F_ULPOSC_CORE_CK_UPDATE	BIT(22)
-#define AP_CLK_CFG_29_SET		REG32(TOPCK_BASE + 0x0180)
-#define AP_CLK_CFG_29_CLR		REG32(TOPCK_BASE + 0x0184)
-#define   ULPOSC1_CLK_SEL		(0x3 << 8)
-#define   PDN_F_ULPOSC_CK		BIT(15)
-#define   ULPOSC2_CLK_SEL		(0x3 << 16)
-#define   PDN_F_ULPOSC_CORE_CK		BIT(23)
+#define TOPCK_BASE AP_REG_BASE
+#define AP_CLK_CFG_UPDATE3 REG32(TOPCK_BASE + 0x0010)
+#define F_ULPOSC_CK_UPDATE BIT(21)
+#define F_ULPOSC_CORE_CK_UPDATE BIT(22)
+#define AP_CLK_CFG_29_SET REG32(TOPCK_BASE + 0x0180)
+#define AP_CLK_CFG_29_CLR REG32(TOPCK_BASE + 0x0184)
+#define ULPOSC1_CLK_SEL (0x3 << 8)
+#define PDN_F_ULPOSC_CK BIT(15)
+#define ULPOSC2_CLK_SEL (0x3 << 16)
+#define PDN_F_ULPOSC_CORE_CK BIT(23)
 /* OSC meter */
-#define AP_CLK_DBG_CFG			REG32(TOPCK_BASE + 0x020C)
-#define   DBG_MODE_MASK			3
-#define   DBG_MODE_SET_CLOCK		0
-#define   DBG_BIST_SOURCE_MASK		(0x7f << 8)
-#define   DBG_BIST_SOURCE_ULPOSC1	(0x30 << 8)
-#define   DBG_BIST_SOURCE_ULPOSC2	(0x32 << 8)
-#define AP_CLK26CALI_0			REG32(TOPCK_BASE + 0x0218)
-#define   CFG_FREQ_METER_RUN		BIT(4)
-#define   CFG_FREQ_METER_ENABLE		BIT(7)
-#define AP_CLK26CALI_1			REG32(TOPCK_BASE + 0x021C)
-#define   CFG_CKGEN_LOAD_CNT		0x01ff0000
-#define   CFG_FREQ_COUNTER(CFG1)	((CFG1) & 0xFFFF)
-#define AP_CLK_MISC_CFG_0		REG32(TOPCK_BASE + 0x022C)
-#define   MISC_METER_DIVISOR_MASK	0xff000000
-#define   MISC_METER_DIV_1		0
+#define AP_CLK_DBG_CFG REG32(TOPCK_BASE + 0x020C)
+#define DBG_MODE_MASK 3
+#define DBG_MODE_SET_CLOCK 0
+#define DBG_BIST_SOURCE_MASK (0x7f << 8)
+#define DBG_BIST_SOURCE_ULPOSC1 (0x30 << 8)
+#define DBG_BIST_SOURCE_ULPOSC2 (0x32 << 8)
+#define AP_CLK26CALI_0 REG32(TOPCK_BASE + 0x0218)
+#define CFG_FREQ_METER_RUN BIT(4)
+#define CFG_FREQ_METER_ENABLE BIT(7)
+#define AP_CLK26CALI_1 REG32(TOPCK_BASE + 0x021C)
+#define CFG_CKGEN_LOAD_CNT 0x01ff0000
+#define CFG_FREQ_COUNTER(CFG1) ((CFG1)&0xFFFF)
+#define AP_CLK_MISC_CFG_0 REG32(TOPCK_BASE + 0x022C)
+#define MISC_METER_DIVISOR_MASK 0xff000000
+#define MISC_METER_DIV_1 0
 /*
  * ULPOSC
  * osc: 0 for ULPOSC1, 1 for ULPOSC2.
  */
-#define AP_ULPOSC_CON0_BASE		(AP_REG_BASE + 0xC2B0)
-#define AP_ULPOSC_CON1_BASE		(AP_REG_BASE + 0xC2B4)
-#define AP_ULPOSC_CON0(osc) \
-		REG32(AP_ULPOSC_CON0_BASE + (osc) * 0x10)
-#define AP_ULPOSC_CON1(osc) \
-		REG32(AP_ULPOSC_CON1_BASE + (osc) * 0x10)
+#define AP_ULPOSC_CON0_BASE (AP_REG_BASE + 0xC2B0)
+#define AP_ULPOSC_CON1_BASE (AP_REG_BASE + 0xC2B4)
+#define AP_ULPOSC_CON0(osc) REG32(AP_ULPOSC_CON0_BASE + (osc)*0x10)
+#define AP_ULPOSC_CON1(osc) REG32(AP_ULPOSC_CON1_BASE + (osc)*0x10)
 /*
  * AP_ULPOSC_CON0
  * bit0-6: calibration
@@ -69,14 +67,14 @@
  * bit27: div2_en
  * bit28-31: reserved
  */
-#define OSC_CALI_SHIFT			0
-#define OSC_CALI_MASK			0x7f
-#define OSC_IBAND_SHIFT			7
-#define OSC_FBAND_SHIFT			14
-#define OSC_DIV_SHIFT			18
-#define OSC_CP_EN			BIT(24)
-#define OSC_MOD_SHIFT			25
-#define OSC_DIV2_EN			BIT(27)
+#define OSC_CALI_SHIFT 0
+#define OSC_CALI_MASK 0x7f
+#define OSC_IBAND_SHIFT 7
+#define OSC_FBAND_SHIFT 14
+#define OSC_DIV_SHIFT 18
+#define OSC_CP_EN BIT(24)
+#define OSC_MOD_SHIFT 25
+#define OSC_DIV2_EN BIT(27)
 /*
  * AP_ULPOSC_CON1
  * bit0-7: rsv1
@@ -84,9 +82,9 @@
  * bit16-23: 32K calibration
  * bit24-31: bias
  */
-#define OSC_RSV1_SHIFT			0
-#define OSC_RSV2_SHIFT			8
-#define OSC_32KCALI_SHIFT		16
-#define OSC_BIAS_SHIFT			24
+#define OSC_RSV1_SHIFT 0
+#define OSC_RSV2_SHIFT 8
+#define OSC_32KCALI_SHIFT 16
+#define OSC_BIAS_SHIFT 24
 
 #endif /* __CROS_EC_CLOCK_REGS_H */
diff --git a/chip/mt_scp/mt8195/intc.h b/chip/mt_scp/mt8195/intc.h
index ba77f069f2..dd3874718e 100644
--- a/chip/mt_scp/mt8195/intc.h
+++ b/chip/mt_scp/mt8195/intc.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,160 +7,160 @@
 #define __CROS_EC_INTC_H
 
 /* INTC */
-#define SCP_INTC_IRQ_POL0		0xef001f20
-#define SCP_INTC_IRQ_POL1		0x044001dd
-#define SCP_INTC_IRQ_POL2		0xffffdfe0
-#define SCP_INTC_IRQ_POL3		0xfffffff3
-#define SCP_INTC_GRP_LEN		4
-#define SCP_INTC_IRQ_COUNT		127
+#define SCP_INTC_IRQ_POL0 0xef001f20
+#define SCP_INTC_IRQ_POL1 0x044001dd
+#define SCP_INTC_IRQ_POL2 0xffffdfe0
+#define SCP_INTC_IRQ_POL3 0xfffffff3
+#define SCP_INTC_GRP_LEN 4
+#define SCP_INTC_IRQ_COUNT 127
 
 /* IRQ numbers */
-#define SCP_IRQ_GIPC_IN0		0
-#define SCP_IRQ_GIPC_IN1		1
-#define SCP_IRQ_GIPC_IN2		2
-#define SCP_IRQ_GIPC_IN3		3
+#define SCP_IRQ_GIPC_IN0 0
+#define SCP_IRQ_GIPC_IN1 1
+#define SCP_IRQ_GIPC_IN2 2
+#define SCP_IRQ_GIPC_IN3 3
 /* 4 */
-#define SCP_IRQ_SPM			4
-#define SCP_IRQ_AP_CIRQ			5
-#define SCP_IRQ_EINT			6
-#define SCP_IRQ_PMIC			7
+#define SCP_IRQ_SPM 4
+#define SCP_IRQ_AP_CIRQ 5
+#define SCP_IRQ_EINT 6
+#define SCP_IRQ_PMIC 7
 /* 8 */
-#define SCP_IRQ_UART0_TX		8
-#define SCP_IRQ_UART1_TX		9
-#define SCP_IRQ_I2C0			10
-#define SCP_IRQ_I2C1_0			11
+#define SCP_IRQ_UART0_TX 8
+#define SCP_IRQ_UART1_TX 9
+#define SCP_IRQ_I2C0 10
+#define SCP_IRQ_I2C1_0 11
 /* 12 */
-#define SCP_IRQ_BUS_DBG_TRACKER		12
-#define SCP_IRQ_CLK_CTRL		13
-#define SCP_IRQ_VOW			14
-#define SCP_IRQ_TIMER0			15
+#define SCP_IRQ_BUS_DBG_TRACKER 12
+#define SCP_IRQ_CLK_CTRL 13
+#define SCP_IRQ_VOW 14
+#define SCP_IRQ_TIMER0 15
 /* 16 */
-#define SCP_IRQ_TIMER1			16
-#define SCP_IRQ_TIMER2			17
-#define SCP_IRQ_TIMER3			18
-#define SCP_IRQ_TIMER4			19
+#define SCP_IRQ_TIMER1 16
+#define SCP_IRQ_TIMER2 17
+#define SCP_IRQ_TIMER3 18
+#define SCP_IRQ_TIMER4 19
 /* 20 */
-#define SCP_IRQ_TIMER5			20
-#define SCP_IRQ_OS_TIMER		21
-#define SCP_IRQ_UART0_RX		22
-#define SCP_IRQ_UART1_RX		23
+#define SCP_IRQ_TIMER5 20
+#define SCP_IRQ_OS_TIMER 21
+#define SCP_IRQ_UART0_RX 22
+#define SCP_IRQ_UART1_RX 23
 /* 24 */
-#define SCP_IRQ_GDMA			24
-#define SCP_IRQ_AUDIO			25
-#define SCP_IRQ_MD_DSP			26
-#define SCP_IRQ_ADSP			27
+#define SCP_IRQ_GDMA 24
+#define SCP_IRQ_AUDIO 25
+#define SCP_IRQ_MD_DSP 26
+#define SCP_IRQ_ADSP 27
 /* 28 */
-#define SCP_IRQ_CPU_TICK		28
-#define SCP_IRQ_SPI0			29
-#define SCP_IRQ_SPI1			30
-#define SCP_IRQ_SPI2			31
+#define SCP_IRQ_CPU_TICK 28
+#define SCP_IRQ_SPI0 29
+#define SCP_IRQ_SPI1 30
+#define SCP_IRQ_SPI2 31
 /* 32 */
-#define SCP_IRQ_NEW_INFRA_SYS_CIRQ	32
-#define SCP_IRQ_DBG			33
-#define SCP_IRQ_GCE			34
-#define SCP_IRQ_MDP_GCE			35
+#define SCP_IRQ_NEW_INFRA_SYS_CIRQ 32
+#define SCP_IRQ_DBG 33
+#define SCP_IRQ_GCE 34
+#define SCP_IRQ_MDP_GCE 35
 /* 36 */
-#define SCP_IRQ_VDEC			36
-#define SCP_IRQ_WDT			37
-#define SCP_IRQ_VDEC_LAT		38
-#define SCP_IRQ_VDEC1			39
+#define SCP_IRQ_VDEC 36
+#define SCP_IRQ_WDT 37
+#define SCP_IRQ_VDEC_LAT 38
+#define SCP_IRQ_VDEC1 39
 /* 40 */
-#define SCP_IRQ_VDEC1_LAT		40
-#define SCP_IRQ_INFRA			41
-#define SCP_IRQ_CLK_CTRL_CORE		42
-#define SCP_IRQ_CLK_CTRL2_CORE		43
+#define SCP_IRQ_VDEC1_LAT 40
+#define SCP_IRQ_INFRA 41
+#define SCP_IRQ_CLK_CTRL_CORE 42
+#define SCP_IRQ_CLK_CTRL2_CORE 43
 /* 44 */
-#define SCP_IRQ_CLK_CTRL2		44
-#define SCP_IRQ_GIPC_IN4		45 /* HALT */
-#define SCP_IRQ_PERIBUS_TIMEOUT		46
-#define SCP_IRQ_INFRABUS_TIMEOUT	47
+#define SCP_IRQ_CLK_CTRL2 44
+#define SCP_IRQ_GIPC_IN4 45 /* HALT */
+#define SCP_IRQ_PERIBUS_TIMEOUT 46
+#define SCP_IRQ_INFRABUS_TIMEOUT 47
 /* 48 */
-#define SCP_IRQ_MET0			48
-#define SCP_IRQ_MET1			49
-#define SCP_IRQ_MET2			50
-#define SCP_IRQ_MET3			51
+#define SCP_IRQ_MET0 48
+#define SCP_IRQ_MET1 49
+#define SCP_IRQ_MET2 50
+#define SCP_IRQ_MET3 51
 /* 52 */
-#define SCP_IRQ_AP_WDT			52
-#define SCP_IRQ_L2TCM_SEC_VIO		53
-#define SCP_IRQ_VDEC_INT_LINE_CNT	54
-#define SCP_IRQ_VOW_DATAIN		55
+#define SCP_IRQ_AP_WDT 52
+#define SCP_IRQ_L2TCM_SEC_VIO 53
+#define SCP_IRQ_VDEC_INT_LINE_CNT 54
+#define SCP_IRQ_VOW_DATAIN 55
 /* 56 */
-#define SCP_IRQ_I3C0_IBI_WAKE		56
-#define SCP_IRQ_I3C1_IBI_WAKE		57
-#define SCP_IRQ_VENC			58
-#define SCP_IRQ_APU_ENGINE		59
+#define SCP_IRQ_I3C0_IBI_WAKE 56
+#define SCP_IRQ_I3C1_IBI_WAKE 57
+#define SCP_IRQ_VENC 58
+#define SCP_IRQ_APU_ENGINE 59
 /* 60 */
-#define SCP_IRQ_MBOX0			60
-#define SCP_IRQ_MBOX1			61
-#define SCP_IRQ_MBOX2			62
-#define SCP_IRQ_MBOX3			63
+#define SCP_IRQ_MBOX0 60
+#define SCP_IRQ_MBOX1 61
+#define SCP_IRQ_MBOX2 62
+#define SCP_IRQ_MBOX3 63
 /* 64 */
-#define SCP_IRQ_MBOX4			64
-#define SCP_IRQ_SYS_CLK_REQ		65
-#define SCP_IRQ_BUS_REQ			66
-#define SCP_IRQ_APSRC_REQ		67
+#define SCP_IRQ_MBOX4 64
+#define SCP_IRQ_SYS_CLK_REQ 65
+#define SCP_IRQ_BUS_REQ 66
+#define SCP_IRQ_APSRC_REQ 67
 /* 68 */
-#define SCP_IRQ_APU_MBOX		68
-#define SCP_IRQ_DEVAPC_SECURE_VIO	69
-#define SCP_IRQ_APDMA0			70
-#define SCP_IRQ_APDMA1			71
+#define SCP_IRQ_APU_MBOX 68
+#define SCP_IRQ_DEVAPC_SECURE_VIO 69
+#define SCP_IRQ_APDMA0 70
+#define SCP_IRQ_APDMA1 71
 /* 72 */
-#define SCP_IRQ_APDMA2			72
-#define SCP_IRQ_APDMA3			73
-#define SCP_IRQ_APDMA4			74
-#define SCP_IRQ_APDMA5			75
+#define SCP_IRQ_APDMA2 72
+#define SCP_IRQ_APDMA3 73
+#define SCP_IRQ_APDMA4 74
+#define SCP_IRQ_APDMA5 75
 /* 76 */
-#define SCP_IRQ_HDMIRX_PM_DVI_SQH	76
-#define SCP_IRQ_HDMIRX_RESERVED		77
-#define SCP_IRQ_NNA0_0			78
-#define SCP_IRQ_NNA0_1			79
+#define SCP_IRQ_HDMIRX_PM_DVI_SQH 76
+#define SCP_IRQ_HDMIRX_RESERVED 77
+#define SCP_IRQ_NNA0_0 78
+#define SCP_IRQ_NNA0_1 79
 /* 80 */
-#define SCP_IRQ_NNA0_2			80
-#define SCP_IRQ_NNA1_0			81
-#define SCP_IRQ_NNA1_1			82
-#define SCP_IRQ_NNA1_2			83
+#define SCP_IRQ_NNA0_2 80
+#define SCP_IRQ_NNA1_0 81
+#define SCP_IRQ_NNA1_1 82
+#define SCP_IRQ_NNA1_2 83
 /* 84 */
-#define SCP_IRQ_JPEGENC			84
-#define SCP_IRQ_JPEGDEC			85
-#define SCP_IRQ_JPEGDEC_C2		86
-#define SCP_IRQ_VENC_C1			87
+#define SCP_IRQ_JPEGENC 84
+#define SCP_IRQ_JPEGDEC 85
+#define SCP_IRQ_JPEGDEC_C2 86
+#define SCP_IRQ_VENC_C1 87
 /* 88 */
-#define SCP_IRQ_JPEGENC_C1		88
-#define SCP_IRQ_JPEGDEC_C1		89
-#define SCP_IRQ_HDMITX			90
-#define SCP_IRQ_HDMI2			91
+#define SCP_IRQ_JPEGENC_C1 88
+#define SCP_IRQ_JPEGDEC_C1 89
+#define SCP_IRQ_HDMITX 90
+#define SCP_IRQ_HDMI2 91
 /* 92 */
-#define SCP_IRQ_EARC			92
-#define SCP_IRQ_CEC			93
-#define SCP_IRQ_HDMI_DEV_DET		94
-#define SCP_IRQ_HDMIRX_OUT_ARM_PHY	95
+#define SCP_IRQ_EARC 92
+#define SCP_IRQ_CEC 93
+#define SCP_IRQ_HDMI_DEV_DET 94
+#define SCP_IRQ_HDMIRX_OUT_ARM_PHY 95
 /* 96 */
-#define SCP_IRQ_I2C2			96
-#define SCP_IRQ_I2C3			97
-#define SCP_IRQ_I3C2_IBI_WAKE		98
-#define SCP_IRQ_I3C3_IBI_WAKE		99
+#define SCP_IRQ_I2C2 96
+#define SCP_IRQ_I2C3 97
+#define SCP_IRQ_I3C2_IBI_WAKE 98
+#define SCP_IRQ_I3C3_IBI_WAKE 99
 /* 100 */
-#define SCP_IRQ_SYS_I2C_0		100
-#define SCP_IRQ_SYS_I2C_1		101
-#define SCP_IRQ_SYS_I2C_2		102
-#define SCP_IRQ_SYS_I2C_3		103
+#define SCP_IRQ_SYS_I2C_0 100
+#define SCP_IRQ_SYS_I2C_1 101
+#define SCP_IRQ_SYS_I2C_2 102
+#define SCP_IRQ_SYS_I2C_3 103
 /* 104 */
-#define SCP_IRQ_SYS_I2C_4		104
-#define SCP_IRQ_SYS_I2C_5		105
-#define SCP_IRQ_SYS_I2C_6		106
-#define SCP_IRQ_SYS_I2C_7		107
+#define SCP_IRQ_SYS_I2C_4 104
+#define SCP_IRQ_SYS_I2C_5 105
+#define SCP_IRQ_SYS_I2C_6 106
+#define SCP_IRQ_SYS_I2C_7 107
 /* 108 */
-#define SCP_IRQ_DISP2ADSP_0		108
-#define SCP_IRQ_DISP2ADSP_1		109
-#define SCP_IRQ_DISP2ADSP_2		110
-#define SCP_IRQ_DISP2ADSP_3		111
+#define SCP_IRQ_DISP2ADSP_0 108
+#define SCP_IRQ_DISP2ADSP_1 109
+#define SCP_IRQ_DISP2ADSP_2 110
+#define SCP_IRQ_DISP2ADSP_3 111
 /* 112 */
-#define SCP_IRQ_DISP2ADSP_4		112
-#define SCP_IRQ_VDO1_DISP_MON2ADSP_0	113
-#define SCP_IRQ_VDO1_DISP_MON2ADSP_1	114
-#define SCP_IRQ_VDO1_DISP_MON2ADSP_2	115
+#define SCP_IRQ_DISP2ADSP_4 112
+#define SCP_IRQ_VDO1_DISP_MON2ADSP_0 113
+#define SCP_IRQ_VDO1_DISP_MON2ADSP_1 114
+#define SCP_IRQ_VDO1_DISP_MON2ADSP_2 115
 /* 116 */
-#define SCP_IRQ_GCE1_SECURE		116
-#define SCP_IRQ_GCE_SECURE		117
+#define SCP_IRQ_GCE1_SECURE 116
+#define SCP_IRQ_GCE_SECURE 117
 
 #endif /* __CROS_EC_INTC_H */
diff --git a/chip/mt_scp/mt8195/uart.c b/chip/mt_scp/mt8195/uart.c
index 76674fa7d3..faad1a41a4 100644
--- a/chip/mt_scp/mt8195/uart.c
+++ b/chip/mt_scp/mt8195/uart.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,9 +19,5 @@ void uart_init_pinmux(void)
 #if UARTN == 0
 	SCP_UART_CK_SEL |= UART0_CK_SEL_VAL(UART_CK_SEL_ULPOSC);
 	SCP_SET_CLK_CG |= CG_UART0_MCLK | CG_UART0_BCLK | CG_UART0_RST;
-
-	/* set AP GPIO102 and GPIO103 to alt func 5 */
-	AP_GPIO_MODE12_CLR = 0x77000000;
-	AP_GPIO_MODE12_SET = 0x55000000;
 #endif
 }
diff --git a/chip/mt_scp/mt8195/video.c b/chip/mt_scp/mt8195/video.c
index cc62f051df..f90a2c4764 100644
--- a/chip/mt_scp/mt8195/video.c
+++ b/chip/mt_scp/mt8195/video.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,6 +13,6 @@ uint32_t video_get_enc_capability(void)
 
 uint32_t video_get_dec_capability(void)
 {
-	return VDEC_CAP_MM21 | VDEC_CAP_H264_SLICE |
-		VDEC_CAP_VP8_FRAME | VDEC_CAP_VP9_FRAME;
+	return VDEC_CAP_INNER_RACING | VDEC_CAP_MM21 | VDEC_CAP_H264_SLICE |
+	       VDEC_CAP_VP8_FRAME | VDEC_CAP_VP9_FRAME;
 }
diff --git a/chip/mt_scp/rv32i_common/build.mk b/chip/mt_scp/rv32i_common/build.mk
index ac7e13db77..eff299f98d 100644
--- a/chip/mt_scp/rv32i_common/build.mk
+++ b/chip/mt_scp/rv32i_common/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/chip/mt_scp/rv32i_common/cache.c b/chip/mt_scp/rv32i_common/cache.c
index 62147590fe..b04f28ebae 100644
--- a/chip/mt_scp/rv32i_common/cache.c
+++ b/chip/mt_scp/rv32i_common/cache.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -33,8 +33,9 @@ void cache_init(void)
 #pragma GCC unroll 16
 	for (i = 0; i < NR_MPU_ENTRIES; ++i) {
 		if (mpu_entries[i].end_addr - mpu_entries[i].start_addr) {
-			write_csr(CSR_MPU_L(i), mpu_entries[i].start_addr |
-						mpu_entries[i].attribute);
+			write_csr(CSR_MPU_L(i),
+				  mpu_entries[i].start_addr |
+					  mpu_entries[i].attribute);
 			write_csr(CSR_MPU_H(i), mpu_entries[i].end_addr);
 			mpu_en |= BIT(i);
 		}
@@ -47,7 +48,7 @@ void cache_init(void)
 	set_csr(CSR_MCTREN, CSR_MCTREN_MPU);
 
 	/* fence */
-	asm volatile ("fence.i" ::: "memory");
+	asm volatile("fence.i" ::: "memory");
 }
 
 #ifdef DEBUG
@@ -56,15 +57,11 @@ void cache_init(void)
  * D for D-cache
  * C for control transfer instructions (branch, jump, ret, interrupt, ...)
  */
-static enum {
-	PMU_SELECT_I = 0,
-	PMU_SELECT_D,
-	PMU_SELECT_C
-} pmu_select;
+static enum { PMU_SELECT_I = 0, PMU_SELECT_D, PMU_SELECT_C } pmu_select;
 
-int command_enable_pmu(int argc, char **argv)
+int command_enable_pmu(int argc, const char **argv)
 {
-	static const char * const selectors[] = {
+	static const char *const selectors[] = {
 		[PMU_SELECT_I] = "I",
 		[PMU_SELECT_D] = "D",
 		[PMU_SELECT_C] = "C",
@@ -87,9 +84,8 @@ int command_enable_pmu(int argc, char **argv)
 
 	/* disable all PMU */
 	clear_csr(CSR_PMU_MPMUCTR,
-		  CSR_PMU_MPMUCTR_C | CSR_PMU_MPMUCTR_I |
-		  CSR_PMU_MPMUCTR_H3 | CSR_PMU_MPMUCTR_H4 |
-		  CSR_PMU_MPMUCTR_H5);
+		  CSR_PMU_MPMUCTR_C | CSR_PMU_MPMUCTR_I | CSR_PMU_MPMUCTR_H3 |
+			  CSR_PMU_MPMUCTR_H4 | CSR_PMU_MPMUCTR_H5);
 
 	/* reset cycle count */
 	write_csr(CSR_PMU_MCYCLE, 0);
@@ -138,45 +134,43 @@ int command_enable_pmu(int argc, char **argv)
 
 	/* enable all PMU */
 	set_csr(CSR_PMU_MPMUCTR,
-		CSR_PMU_MPMUCTR_C | CSR_PMU_MPMUCTR_I |
-		CSR_PMU_MPMUCTR_H3 | CSR_PMU_MPMUCTR_H4 |
-		CSR_PMU_MPMUCTR_H5);
+		CSR_PMU_MPMUCTR_C | CSR_PMU_MPMUCTR_I | CSR_PMU_MPMUCTR_H3 |
+			CSR_PMU_MPMUCTR_H4 | CSR_PMU_MPMUCTR_H5);
 
 	return EC_SUCCESS;
 }
-DECLARE_SAFE_CONSOLE_COMMAND(enable_pmu, command_enable_pmu,
-			     "[I | D | C]", "Enable PMU");
+DECLARE_SAFE_CONSOLE_COMMAND(enable_pmu, command_enable_pmu, "[I | D | C]",
+			     "Enable PMU");
 
-int command_disable_pmu(int argc, char **argv)
+int command_disable_pmu(int argc, const char **argv)
 {
 	clear_csr(CSR_PMU_MPMUCTR,
-		  CSR_PMU_MPMUCTR_C | CSR_PMU_MPMUCTR_I |
-		  CSR_PMU_MPMUCTR_H3 | CSR_PMU_MPMUCTR_H4 |
-		  CSR_PMU_MPMUCTR_H5);
+		  CSR_PMU_MPMUCTR_C | CSR_PMU_MPMUCTR_I | CSR_PMU_MPMUCTR_H3 |
+			  CSR_PMU_MPMUCTR_H4 | CSR_PMU_MPMUCTR_H5);
 	return EC_SUCCESS;
 }
-DECLARE_SAFE_CONSOLE_COMMAND(disable_pmu, command_disable_pmu,
-			     NULL, "Disable PMU");
+DECLARE_SAFE_CONSOLE_COMMAND(disable_pmu, command_disable_pmu, NULL,
+			     "Disable PMU");
 
-int command_show_pmu(int argc, char **argv)
+int command_show_pmu(int argc, const char **argv)
 {
 	uint64_t val3, val4, val5;
 	uint32_t p;
 
 	val3 = ((uint64_t)read_csr(CSR_PMU_MCYCLEH) << 32) |
-			read_csr(CSR_PMU_MCYCLE);
+	       read_csr(CSR_PMU_MCYCLE);
 	ccprintf("cycles: %lld\n", val3);
 
 	val3 = ((uint64_t)read_csr(CSR_PMU_MINSTRETH) << 32) |
-			read_csr(CSR_PMU_MINSTRET);
+	       read_csr(CSR_PMU_MINSTRET);
 	ccprintf("retired instructions: %lld\n", val3);
 
 	val3 = ((uint64_t)read_csr(CSR_PMU_MHPMCOUNTER3H) << 32) |
-			read_csr(CSR_PMU_MHPMCOUNTER3);
+	       read_csr(CSR_PMU_MHPMCOUNTER3);
 	val4 = ((uint64_t)read_csr(CSR_PMU_MHPMCOUNTER4H) << 32) |
-			read_csr(CSR_PMU_MHPMCOUNTER4);
+	       read_csr(CSR_PMU_MHPMCOUNTER4);
 	val5 = ((uint64_t)read_csr(CSR_PMU_MHPMCOUNTER5H) << 32) |
-			read_csr(CSR_PMU_MHPMCOUNTER5);
+	       read_csr(CSR_PMU_MHPMCOUNTER5);
 
 	if (val3)
 		p = val4 * 10000 / val3;
@@ -199,8 +193,8 @@ int command_show_pmu(int argc, char **argv)
 	case PMU_SELECT_C:
 		ccprintf("control transfer instruction:\n");
 		ccprintf("  total: %lld\n", val3);
-		ccprintf("  miss-predict: %lld (%d.%d%%)\n",
-			 val4, p / 100, p % 100);
+		ccprintf("  miss-predict: %lld (%d.%d%%)\n", val4, p / 100,
+			 p % 100);
 		ccprintf("interrupts: %lld\n", val5);
 		break;
 	}
diff --git a/chip/mt_scp/rv32i_common/cache.h b/chip/mt_scp/rv32i_common/cache.h
index 13e5ad1a42..15572962ac 100644
--- a/chip/mt_scp/rv32i_common/cache.h
+++ b/chip/mt_scp/rv32i_common/cache.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,23 +14,23 @@
 /* rs1 0~31 register X0~X31 */
 #define COP(rs1) (((rs1) << 15) | 0x400f)
 
-#define COP_OP_BARRIER_ICACHE		0x0
-#define COP_OP_INVALIDATE_ICACHE	0x8
-#define COP_OP_INVALIDATE_ICACHE_ADDR	0x9
+#define COP_OP_BARRIER_ICACHE 0x0
+#define COP_OP_INVALIDATE_ICACHE 0x8
+#define COP_OP_INVALIDATE_ICACHE_ADDR 0x9
 
-#define COP_OP_BARRIER_DCACHE		0x10
-#define COP_OP_WRITEBACK_DCACHE		0x14
-#define COP_OP_WRITEBACK_DCACHE_ADDR	0x15
-#define COP_OP_INVALIDATE_DCACHE	0x18
-#define COP_OP_INVALIDATE_DCACHE_ADDR	0x19
+#define COP_OP_BARRIER_DCACHE 0x10
+#define COP_OP_WRITEBACK_DCACHE 0x14
+#define COP_OP_WRITEBACK_DCACHE_ADDR 0x15
+#define COP_OP_INVALIDATE_DCACHE 0x18
+#define COP_OP_INVALIDATE_DCACHE_ADDR 0x19
 /* FLUSH = WRITEBACK + INVALIDATE */
-#define COP_OP_FLUSH_DCACHE		0x1C
-#define COP_OP_FLUSH_DCACHE_ADDR	0x1D
+#define COP_OP_FLUSH_DCACHE 0x1C
+#define COP_OP_FLUSH_DCACHE_ADDR 0x1D
 
 static inline void cache_op_all(uint32_t op)
 {
 	register int t0 asm("t0") = op;
-	asm volatile (".word "STRINGIFY(COP(5)) :: "r"(t0));
+	asm volatile(".word " STRINGIFY(COP(5))::"r"(t0));
 }
 
 static inline int cache_op_addr(uintptr_t addr, uint32_t length, uint32_t op)
@@ -44,7 +44,7 @@ static inline int cache_op_addr(uintptr_t addr, uint32_t length, uint32_t op)
 
 	for (offset = 0; offset < length; offset += 4) {
 		t0 = addr + offset + op;
-		asm volatile (".word "STRINGIFY(COP(5)) :: "r"(t0));
+		asm volatile(".word " STRINGIFY(COP(5))::"r"(t0));
 	}
 
 	return EC_SUCCESS;
@@ -132,9 +132,9 @@ struct mpu_entry {
 void cache_init(void);
 
 #ifdef DEBUG
-int command_enable_pmu(int argc, char **argv);
-int command_disable_pmu(int argc, char **argv);
-int command_show_pmu(int argc, char **argv);
+int command_enable_pmu(int argc, const char **argv);
+int command_disable_pmu(int argc, const char **argv);
+int command_show_pmu(int argc, const char **argv);
 #endif
 
 #endif /* #ifndef __CROS_EC_CACHE_H */
diff --git a/chip/mt_scp/rv32i_common/config_chip.h b/chip/mt_scp/rv32i_common/config_chip.h
index ac53d51732..775dd02461 100644
--- a/chip/mt_scp/rv32i_common/config_chip.h
+++ b/chip/mt_scp/rv32i_common/config_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,10 +10,10 @@
 
 /* Interval between HOOK_TICK notifications */
 #define HOOK_TICK_INTERVAL_MS 500
-#define HOOK_TICK_INTERVAL    (HOOK_TICK_INTERVAL_MS * MSEC)
+#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC)
 
 /* RW only, no flash */
-#undef  CONFIG_FW_INCLUDE_RO
+#undef CONFIG_FW_INCLUDE_RO
 #define CONFIG_RO_MEM_OFF 0
 #define CONFIG_RO_SIZE 0
 #define CONFIG_RW_MEM_OFF 0
diff --git a/chip/mt_scp/rv32i_common/csr.h b/chip/mt_scp/rv32i_common/csr.h
index 7c767d0592..88ea869cbd 100644
--- a/chip/mt_scp/rv32i_common/csr.h
+++ b/chip/mt_scp/rv32i_common/csr.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,14 +22,14 @@ static inline uint32_t read_csr(uint32_t reg)
 
 static inline void write_csr(uint32_t reg, uint32_t val)
 {
-	asm volatile ("csrw %0, %1" :: "i"(reg), "r"(val));
+	asm volatile("csrw %0, %1" ::"i"(reg), "r"(val));
 }
 
 static inline uint32_t set_csr(uint32_t reg, uint32_t bit)
 {
 	uint32_t val;
 
-	asm volatile ("csrrs %0, %1, %2" : "=r"(val) : "i"(reg), "r"(bit));
+	asm volatile("csrrs %0, %1, %2" : "=r"(val) : "i"(reg), "r"(bit));
 	return val;
 }
 
@@ -37,75 +37,75 @@ static inline uint32_t clear_csr(uint32_t reg, uint32_t bit)
 {
 	uint32_t val;
 
-	asm volatile ("csrrc %0, %1, %2" : "=r"(val) : "i"(reg), "r"(bit));
+	asm volatile("csrrc %0, %1, %2" : "=r"(val) : "i"(reg), "r"(bit));
 	return val;
 }
 
 /* VIC */
-#define CSR_VIC_MICAUSE		(0x5c0)
-#define CSR_VIC_MIEMS		(0x5c2)
-#define CSR_VIC_MIPEND_G0	(0x5d0)
-#define CSR_VIC_MIMASK_G0	(0x5d8)
-#define CSR_VIC_MIWAKEUP_G0	(0x5e0)
-#define CSR_VIC_MILSEL_G0	(0x5e8)
-#define CSR_VIC_MIEMASK_G0	(0x5f0)
+#define CSR_VIC_MICAUSE (0x5c0)
+#define CSR_VIC_MIEMS (0x5c2)
+#define CSR_VIC_MIPEND_G0 (0x5d0)
+#define CSR_VIC_MIMASK_G0 (0x5d8)
+#define CSR_VIC_MIWAKEUP_G0 (0x5e0)
+#define CSR_VIC_MILSEL_G0 (0x5e8)
+#define CSR_VIC_MIEMASK_G0 (0x5f0)
 
 /* centralized control enable */
-#define CSR_MCTREN		(0x7c0)
+#define CSR_MCTREN (0x7c0)
 /* I$, D$, ITCM, DTCM, BTB, RAS, VIC, CG, mpu */
-#define   CSR_MCTREN_ICACHE	BIT(0)
-#define   CSR_MCTREN_DCACHE	BIT(1)
-#define   CSR_MCTREN_ITCM	BIT(2)
-#define   CSR_MCTREN_DTCM	BIT(3)
-#define   CSR_MCTREN_BTB	BIT(4)
-#define   CSR_MCTREN_RAS	BIT(5)
-#define   CSR_MCTREN_VIC	BIT(6)
-#define   CSR_MCTREN_CG		BIT(7)
-#define   CSR_MCTREN_MPU	BIT(8)
+#define CSR_MCTREN_ICACHE BIT(0)
+#define CSR_MCTREN_DCACHE BIT(1)
+#define CSR_MCTREN_ITCM BIT(2)
+#define CSR_MCTREN_DTCM BIT(3)
+#define CSR_MCTREN_BTB BIT(4)
+#define CSR_MCTREN_RAS BIT(5)
+#define CSR_MCTREN_VIC BIT(6)
+#define CSR_MCTREN_CG BIT(7)
+#define CSR_MCTREN_MPU BIT(8)
 
 /* MPU */
-#define CSR_MPU_ENTRY_EN	(0x9c0)
-#define CSR_MPU_LITCM		(0x9dc)
-#define CSR_MPU_LDTCM		(0x9dd)
-#define CSR_MPU_HITCM		(0x9de)
-#define CSR_MPU_HDTCM		(0x9df)
-#define CSR_MPU_L(n)		(0x9e0 + (n))
-#define CSR_MPU_H(n)		(0x9f0 + (n))
+#define CSR_MPU_ENTRY_EN (0x9c0)
+#define CSR_MPU_LITCM (0x9dc)
+#define CSR_MPU_LDTCM (0x9dd)
+#define CSR_MPU_HITCM (0x9de)
+#define CSR_MPU_HDTCM (0x9df)
+#define CSR_MPU_L(n) (0x9e0 + (n))
+#define CSR_MPU_H(n) (0x9f0 + (n))
 /* MPU attributes: set if permitted */
 /* Privilege, machine mode in RISC-V.  We don't use the flag because
  * we don't separate user / machine mode in EC OS. */
-#define   MPU_ATTR_P		BIT(5)
+#define MPU_ATTR_P BIT(5)
 /* Readable */
-#define   MPU_ATTR_R		BIT(6)
+#define MPU_ATTR_R BIT(6)
 /* Writable */
-#define   MPU_ATTR_W		BIT(7)
+#define MPU_ATTR_W BIT(7)
 /* Cacheable */
-#define   MPU_ATTR_C		BIT(8)
+#define MPU_ATTR_C BIT(8)
 /* Bufferable */
-#define   MPU_ATTR_B		BIT(9)
+#define MPU_ATTR_B BIT(9)
 
 /* PMU */
-#define CSR_PMU_MPMUCTR		(0xbc0)
-#define   CSR_PMU_MPMUCTR_C	BIT(0)
-#define   CSR_PMU_MPMUCTR_I	BIT(1)
-#define   CSR_PMU_MPMUCTR_H3	BIT(2)
-#define   CSR_PMU_MPMUCTR_H4	BIT(3)
-#define   CSR_PMU_MPMUCTR_H5	BIT(4)
-
-#define CSR_PMU_MCYCLE		(0xb00)
-#define CSR_PMU_MINSTRET	(0xb02)
-#define CSR_PMU_MHPMCOUNTER3	(0xb03)
-#define CSR_PMU_MHPMCOUNTER4	(0xb04)
-#define CSR_PMU_MHPMCOUNTER5	(0xb05)
-
-#define CSR_PMU_MCYCLEH		(0xb80)
-#define CSR_PMU_MINSTRETH	(0xb82)
-#define CSR_PMU_MHPMCOUNTER3H	(0xb83)
-#define CSR_PMU_MHPMCOUNTER4H	(0xb84)
-#define CSR_PMU_MHPMCOUNTER5H	(0xb85)
-
-#define CSR_PMU_MHPMEVENT3	(0x323)
-#define CSR_PMU_MHPMEVENT4	(0x324)
-#define CSR_PMU_MHPMEVENT5	(0x325)
+#define CSR_PMU_MPMUCTR (0xbc0)
+#define CSR_PMU_MPMUCTR_C BIT(0)
+#define CSR_PMU_MPMUCTR_I BIT(1)
+#define CSR_PMU_MPMUCTR_H3 BIT(2)
+#define CSR_PMU_MPMUCTR_H4 BIT(3)
+#define CSR_PMU_MPMUCTR_H5 BIT(4)
+
+#define CSR_PMU_MCYCLE (0xb00)
+#define CSR_PMU_MINSTRET (0xb02)
+#define CSR_PMU_MHPMCOUNTER3 (0xb03)
+#define CSR_PMU_MHPMCOUNTER4 (0xb04)
+#define CSR_PMU_MHPMCOUNTER5 (0xb05)
+
+#define CSR_PMU_MCYCLEH (0xb80)
+#define CSR_PMU_MINSTRETH (0xb82)
+#define CSR_PMU_MHPMCOUNTER3H (0xb83)
+#define CSR_PMU_MHPMCOUNTER4H (0xb84)
+#define CSR_PMU_MHPMCOUNTER5H (0xb85)
+
+#define CSR_PMU_MHPMEVENT3 (0x323)
+#define CSR_PMU_MHPMEVENT4 (0x324)
+#define CSR_PMU_MHPMEVENT5 (0x325)
 
 #endif /* __CROS_EC_CSR_H */
diff --git a/chip/mt_scp/rv32i_common/gpio.c b/chip/mt_scp/rv32i_common/gpio.c
index 0ca3e3ac25..d56cff97fb 100644
--- a/chip/mt_scp/rv32i_common/gpio.c
+++ b/chip/mt_scp/rv32i_common/gpio.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/mt_scp/rv32i_common/hostcmd.c b/chip/mt_scp/rv32i_common/hostcmd.c
index 42a463ee56..fee1ce110a 100644
--- a/chip/mt_scp/rv32i_common/hostcmd.c
+++ b/chip/mt_scp/rv32i_common/hostcmd.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -97,7 +97,8 @@ DECLARE_IPI(SCP_IPI_HOST_COMMAND, hostcmd_handler, 0);
 /*
  * Get protocol information
  */
-static enum ec_status hostcmd_get_protocol_info(struct host_cmd_handler_args *args)
+static enum ec_status
+hostcmd_get_protocol_info(struct host_cmd_handler_args *args)
 {
 	struct ec_response_get_protocol_info *r = args->response;
 
diff --git a/chip/mt_scp/rv32i_common/hostcmd.h b/chip/mt_scp/rv32i_common/hostcmd.h
index b93f1e725d..067a4c14ab 100644
--- a/chip/mt_scp/rv32i_common/hostcmd.h
+++ b/chip/mt_scp/rv32i_common/hostcmd.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/mt_scp/rv32i_common/hrtimer.c b/chip/mt_scp/rv32i_common/hrtimer.c
index a844527494..fff5fb6436 100644
--- a/chip/mt_scp/rv32i_common/hrtimer.c
+++ b/chip/mt_scp/rv32i_common/hrtimer.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -65,8 +65,8 @@ static void timer_set_reset_value(int n, uint32_t reset_value)
 
 static void timer_set_clock(int n, uint32_t clock_source)
 {
-	SCP_CORE0_TIMER_EN(n) =
-		(SCP_CORE0_TIMER_EN(n) & ~TIMER_CLK_SRC_MASK) | clock_source;
+	SCP_CORE0_TIMER_EN(n) = (SCP_CORE0_TIMER_EN(n) & ~TIMER_CLK_SRC_MASK) |
+				clock_source;
 }
 
 static void timer_reset(int n)
@@ -88,8 +88,8 @@ static uint64_t timer_read_raw_system(void)
 	 * sys_high value.
 	 */
 	if (timer_ctrl & TIMER_IRQ_STATUS)
-		sys_high_adj = sys_high ? (sys_high - 1)
-					: (TIMER_CLOCK_MHZ - 1);
+		sys_high_adj = sys_high ? (sys_high - 1) :
+					  (TIMER_CLOCK_MHZ - 1);
 
 	return OVERFLOW_TICKS - (((uint64_t)sys_high_adj << 32) |
 				 SCP_CORE0_TIMER_CUR_VAL(TIMER_SYSTEM));
@@ -159,8 +159,8 @@ uint32_t __hw_clock_source_read(void)
 
 uint32_t __hw_clock_event_get(void)
 {
-	return (timer_read_raw_event() + timer_read_raw_system())
-			/ TIMER_CLOCK_MHZ;
+	return (timer_read_raw_event() + timer_read_raw_system()) /
+	       TIMER_CLOCK_MHZ;
 }
 
 void __hw_clock_event_clear(void)
diff --git a/chip/mt_scp/rv32i_common/intc.c b/chip/mt_scp/rv32i_common/intc.c
index 606f487ed5..641d0cf516 100644
--- a/chip/mt_scp/rv32i_common/intc.c
+++ b/chip/mt_scp/rv32i_common/intc.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -39,114 +39,114 @@ static struct {
 	uint8_t group;
 } irqs[SCP_INTC_IRQ_COUNT] = {
 	/* 0 */
-	[SCP_IRQ_GIPC_IN0]		= { INTC_GRP_7 },
-	[SCP_IRQ_GIPC_IN1]		= { INTC_GRP_0 },
-	[SCP_IRQ_GIPC_IN2]		= { INTC_GRP_0 },
-	[SCP_IRQ_GIPC_IN3]		= { INTC_GRP_0 },
+	[SCP_IRQ_GIPC_IN0] = { INTC_GRP_7 },
+	[SCP_IRQ_GIPC_IN1] = { INTC_GRP_0 },
+	[SCP_IRQ_GIPC_IN2] = { INTC_GRP_0 },
+	[SCP_IRQ_GIPC_IN3] = { INTC_GRP_0 },
 	/* 4 */
-	[SCP_IRQ_SPM]			= { INTC_GRP_0 },
-	[SCP_IRQ_AP_CIRQ]		= { INTC_GRP_0 },
-	[SCP_IRQ_EINT]			= { INTC_GRP_0 },
-	[SCP_IRQ_PMIC]			= { INTC_GRP_0 },
+	[SCP_IRQ_SPM] = { INTC_GRP_0 },
+	[SCP_IRQ_AP_CIRQ] = { INTC_GRP_0 },
+	[SCP_IRQ_EINT] = { INTC_GRP_0 },
+	[SCP_IRQ_PMIC] = { INTC_GRP_0 },
 	/* 8 */
-	[SCP_IRQ_UART0_TX]		= { INTC_GRP_12 },
-	[SCP_IRQ_UART1_TX]		= { INTC_GRP_12 },
-	[SCP_IRQ_I2C0]			= { INTC_GRP_0 },
-	[SCP_IRQ_I2C1_0]		= { INTC_GRP_0 },
+	[SCP_IRQ_UART0_TX] = { INTC_GRP_12 },
+	[SCP_IRQ_UART1_TX] = { INTC_GRP_12 },
+	[SCP_IRQ_I2C0] = { INTC_GRP_0 },
+	[SCP_IRQ_I2C1_0] = { INTC_GRP_0 },
 	/* 12 */
-	[SCP_IRQ_BUS_DBG_TRACKER]	= { INTC_GRP_0 },
-	[SCP_IRQ_CLK_CTRL]		= { INTC_GRP_0 },
-	[SCP_IRQ_VOW]			= { INTC_GRP_0 },
-	[SCP_IRQ_TIMER0]		= { INTC_GRP_6 },
+	[SCP_IRQ_BUS_DBG_TRACKER] = { INTC_GRP_0 },
+	[SCP_IRQ_CLK_CTRL] = { INTC_GRP_0 },
+	[SCP_IRQ_VOW] = { INTC_GRP_0 },
+	[SCP_IRQ_TIMER0] = { INTC_GRP_6 },
 	/* 16 */
-	[SCP_IRQ_TIMER1]		= { INTC_GRP_6 },
-	[SCP_IRQ_TIMER2]		= { INTC_GRP_6 },
-	[SCP_IRQ_TIMER3]		= { INTC_GRP_6 },
-	[SCP_IRQ_TIMER4]		= { INTC_GRP_6 },
+	[SCP_IRQ_TIMER1] = { INTC_GRP_6 },
+	[SCP_IRQ_TIMER2] = { INTC_GRP_6 },
+	[SCP_IRQ_TIMER3] = { INTC_GRP_6 },
+	[SCP_IRQ_TIMER4] = { INTC_GRP_6 },
 	/* 20 */
-	[SCP_IRQ_TIMER5]		= { INTC_GRP_6 },
-	[SCP_IRQ_OS_TIMER]		= { INTC_GRP_0 },
-	[SCP_IRQ_UART0_RX]		= { INTC_GRP_12 },
-	[SCP_IRQ_UART1_RX]		= { INTC_GRP_12 },
+	[SCP_IRQ_TIMER5] = { INTC_GRP_6 },
+	[SCP_IRQ_OS_TIMER] = { INTC_GRP_0 },
+	[SCP_IRQ_UART0_RX] = { INTC_GRP_12 },
+	[SCP_IRQ_UART1_RX] = { INTC_GRP_12 },
 	/* 24 */
-	[SCP_IRQ_GDMA]			= { INTC_GRP_0 },
-	[SCP_IRQ_AUDIO]			= { INTC_GRP_0 },
-	[SCP_IRQ_MD_DSP]		= { INTC_GRP_0 },
-	[SCP_IRQ_ADSP]			= { INTC_GRP_0 },
+	[SCP_IRQ_GDMA] = { INTC_GRP_0 },
+	[SCP_IRQ_AUDIO] = { INTC_GRP_0 },
+	[SCP_IRQ_MD_DSP] = { INTC_GRP_0 },
+	[SCP_IRQ_ADSP] = { INTC_GRP_0 },
 	/* 28 */
-	[SCP_IRQ_CPU_TICK]		= { INTC_GRP_0 },
-	[SCP_IRQ_SPI0]			= { INTC_GRP_0 },
-	[SCP_IRQ_SPI1]			= { INTC_GRP_0 },
-	[SCP_IRQ_SPI2]			= { INTC_GRP_0 },
+	[SCP_IRQ_CPU_TICK] = { INTC_GRP_0 },
+	[SCP_IRQ_SPI0] = { INTC_GRP_0 },
+	[SCP_IRQ_SPI1] = { INTC_GRP_0 },
+	[SCP_IRQ_SPI2] = { INTC_GRP_0 },
 	/* 32 */
-	[SCP_IRQ_NEW_INFRA_SYS_CIRQ]	= { INTC_GRP_0 },
-	[SCP_IRQ_DBG]			= { INTC_GRP_0 },
-	[SCP_IRQ_CCIF0]			= { INTC_GRP_0 },
-	[SCP_IRQ_CCIF1]			= { INTC_GRP_0 },
+	[SCP_IRQ_NEW_INFRA_SYS_CIRQ] = { INTC_GRP_0 },
+	[SCP_IRQ_DBG] = { INTC_GRP_0 },
+	[SCP_IRQ_CCIF0] = { INTC_GRP_0 },
+	[SCP_IRQ_CCIF1] = { INTC_GRP_0 },
 	/* 36 */
-	[SCP_IRQ_CCIF2]			= { INTC_GRP_0 },
-	[SCP_IRQ_WDT]			= { INTC_GRP_0 },
-	[SCP_IRQ_USB0]			= { INTC_GRP_0 },
-	[SCP_IRQ_USB1]			= { INTC_GRP_0 },
+	[SCP_IRQ_CCIF2] = { INTC_GRP_0 },
+	[SCP_IRQ_WDT] = { INTC_GRP_0 },
+	[SCP_IRQ_USB0] = { INTC_GRP_0 },
+	[SCP_IRQ_USB1] = { INTC_GRP_0 },
 	/* 40 */
-	[SCP_IRQ_DPMAIF]		= { INTC_GRP_0 },
-	[SCP_IRQ_INFRA]			= { INTC_GRP_0 },
-	[SCP_IRQ_CLK_CTRL_CORE]		= { INTC_GRP_0 },
-	[SCP_IRQ_CLK_CTRL2_CORE]	= { INTC_GRP_0 },
+	[SCP_IRQ_DPMAIF] = { INTC_GRP_0 },
+	[SCP_IRQ_INFRA] = { INTC_GRP_0 },
+	[SCP_IRQ_CLK_CTRL_CORE] = { INTC_GRP_0 },
+	[SCP_IRQ_CLK_CTRL2_CORE] = { INTC_GRP_0 },
 	/* 44 */
-	[SCP_IRQ_CLK_CTRL2]		= { INTC_GRP_0 },
-	[SCP_IRQ_GIPC_IN4]		= { INTC_GRP_0 },
-	[SCP_IRQ_PERIBUS_TIMEOUT]	= { INTC_GRP_0 },
-	[SCP_IRQ_INFRABUS_TIMEOUT]	= { INTC_GRP_0 },
+	[SCP_IRQ_CLK_CTRL2] = { INTC_GRP_0 },
+	[SCP_IRQ_GIPC_IN4] = { INTC_GRP_0 },
+	[SCP_IRQ_PERIBUS_TIMEOUT] = { INTC_GRP_0 },
+	[SCP_IRQ_INFRABUS_TIMEOUT] = { INTC_GRP_0 },
 	/* 48 */
-	[SCP_IRQ_MET0]			= { INTC_GRP_0 },
-	[SCP_IRQ_MET1]			= { INTC_GRP_0 },
-	[SCP_IRQ_MET2]			= { INTC_GRP_0 },
-	[SCP_IRQ_MET3]			= { INTC_GRP_0 },
+	[SCP_IRQ_MET0] = { INTC_GRP_0 },
+	[SCP_IRQ_MET1] = { INTC_GRP_0 },
+	[SCP_IRQ_MET2] = { INTC_GRP_0 },
+	[SCP_IRQ_MET3] = { INTC_GRP_0 },
 	/* 52 */
-	[SCP_IRQ_AP_WDT]		= { INTC_GRP_0 },
-	[SCP_IRQ_L2TCM_SEC_VIO]		= { INTC_GRP_0 },
-	[SCP_IRQ_CPU_TICK1]		= { INTC_GRP_0 },
-	[SCP_IRQ_MAD_DATAIN]		= { INTC_GRP_0 },
+	[SCP_IRQ_AP_WDT] = { INTC_GRP_0 },
+	[SCP_IRQ_L2TCM_SEC_VIO] = { INTC_GRP_0 },
+	[SCP_IRQ_CPU_TICK1] = { INTC_GRP_0 },
+	[SCP_IRQ_MAD_DATAIN] = { INTC_GRP_0 },
 	/* 56 */
-	[SCP_IRQ_I3C0_IBI_WAKE]		= { INTC_GRP_0 },
-	[SCP_IRQ_I3C1_IBI_WAKE]		= { INTC_GRP_0 },
-	[SCP_IRQ_I3C2_IBI_WAKE]		= { INTC_GRP_0 },
-	[SCP_IRQ_APU_ENGINE]		= { INTC_GRP_0 },
+	[SCP_IRQ_I3C0_IBI_WAKE] = { INTC_GRP_0 },
+	[SCP_IRQ_I3C1_IBI_WAKE] = { INTC_GRP_0 },
+	[SCP_IRQ_I3C2_IBI_WAKE] = { INTC_GRP_0 },
+	[SCP_IRQ_APU_ENGINE] = { INTC_GRP_0 },
 	/* 60 */
-	[SCP_IRQ_MBOX0]			= { INTC_GRP_0 },
-	[SCP_IRQ_MBOX1]			= { INTC_GRP_0 },
-	[SCP_IRQ_MBOX2]			= { INTC_GRP_0 },
-	[SCP_IRQ_MBOX3]			= { INTC_GRP_0 },
+	[SCP_IRQ_MBOX0] = { INTC_GRP_0 },
+	[SCP_IRQ_MBOX1] = { INTC_GRP_0 },
+	[SCP_IRQ_MBOX2] = { INTC_GRP_0 },
+	[SCP_IRQ_MBOX3] = { INTC_GRP_0 },
 	/* 64 */
-	[SCP_IRQ_MBOX4]			= { INTC_GRP_0 },
-	[SCP_IRQ_SYS_CLK_REQ]		= { INTC_GRP_0 },
-	[SCP_IRQ_BUS_REQ]		= { INTC_GRP_0 },
-	[SCP_IRQ_APSRC_REQ]		= { INTC_GRP_0 },
+	[SCP_IRQ_MBOX4] = { INTC_GRP_0 },
+	[SCP_IRQ_SYS_CLK_REQ] = { INTC_GRP_0 },
+	[SCP_IRQ_BUS_REQ] = { INTC_GRP_0 },
+	[SCP_IRQ_APSRC_REQ] = { INTC_GRP_0 },
 	/* 68 */
-	[SCP_IRQ_APU_MBOX]		= { INTC_GRP_0 },
-	[SCP_IRQ_DEVAPC_SECURE_VIO]	= { INTC_GRP_0 },
+	[SCP_IRQ_APU_MBOX] = { INTC_GRP_0 },
+	[SCP_IRQ_DEVAPC_SECURE_VIO] = { INTC_GRP_0 },
 	/* 72 */
 	/* 76 */
-	[SCP_IRQ_I2C1_2]		= { INTC_GRP_0 },
-	[SCP_IRQ_I2C2]			= { INTC_GRP_0 },
+	[SCP_IRQ_I2C1_2] = { INTC_GRP_0 },
+	[SCP_IRQ_I2C2] = { INTC_GRP_0 },
 	/* 80 */
-	[SCP_IRQ_AUD2AUDIODSP]		= { INTC_GRP_0 },
-	[SCP_IRQ_AUD2AUDIODSP_2]	= { INTC_GRP_0 },
-	[SCP_IRQ_CONN2ADSP_A2DPOL]	= { INTC_GRP_0 },
-	[SCP_IRQ_CONN2ADSP_BTCVSD]	= { INTC_GRP_0 },
+	[SCP_IRQ_AUD2AUDIODSP] = { INTC_GRP_0 },
+	[SCP_IRQ_AUD2AUDIODSP_2] = { INTC_GRP_0 },
+	[SCP_IRQ_CONN2ADSP_A2DPOL] = { INTC_GRP_0 },
+	[SCP_IRQ_CONN2ADSP_BTCVSD] = { INTC_GRP_0 },
 	/* 84 */
-	[SCP_IRQ_CONN2ADSP_BLEISO]	= { INTC_GRP_0 },
-	[SCP_IRQ_PCIE2ADSP]		= { INTC_GRP_0 },
-	[SCP_IRQ_APU2ADSP_ENGINE]	= { INTC_GRP_0 },
-	[SCP_IRQ_APU2ADSP_MBOX]		= { INTC_GRP_0 },
+	[SCP_IRQ_CONN2ADSP_BLEISO] = { INTC_GRP_0 },
+	[SCP_IRQ_PCIE2ADSP] = { INTC_GRP_0 },
+	[SCP_IRQ_APU2ADSP_ENGINE] = { INTC_GRP_0 },
+	[SCP_IRQ_APU2ADSP_MBOX] = { INTC_GRP_0 },
 	/* 88 */
-	[SCP_IRQ_CCIF3]			= { INTC_GRP_0 },
-	[SCP_IRQ_I2C_DMA0]		= { INTC_GRP_0 },
-	[SCP_IRQ_I2C_DMA1]		= { INTC_GRP_0 },
-	[SCP_IRQ_I2C_DMA2]		= { INTC_GRP_0 },
+	[SCP_IRQ_CCIF3] = { INTC_GRP_0 },
+	[SCP_IRQ_I2C_DMA0] = { INTC_GRP_0 },
+	[SCP_IRQ_I2C_DMA1] = { INTC_GRP_0 },
+	[SCP_IRQ_I2C_DMA2] = { INTC_GRP_0 },
 	/* 92 */
-	[SCP_IRQ_I2C_DMA3]		= { INTC_GRP_0 },
+	[SCP_IRQ_I2C_DMA3] = { INTC_GRP_0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(irqs) == SCP_INTC_IRQ_COUNT);
 #endif
@@ -156,153 +156,153 @@ static struct {
 	uint8_t group;
 } irqs[SCP_INTC_IRQ_COUNT] = {
 	/* 0 */
-	[SCP_IRQ_GIPC_IN0]		= { INTC_GRP_7 },
-	[SCP_IRQ_GIPC_IN1]		= { INTC_GRP_0 },
-	[SCP_IRQ_GIPC_IN2]		= { INTC_GRP_0 },
-	[SCP_IRQ_GIPC_IN3]		= { INTC_GRP_0 },
+	[SCP_IRQ_GIPC_IN0] = { INTC_GRP_7 },
+	[SCP_IRQ_GIPC_IN1] = { INTC_GRP_0 },
+	[SCP_IRQ_GIPC_IN2] = { INTC_GRP_0 },
+	[SCP_IRQ_GIPC_IN3] = { INTC_GRP_0 },
 	/* 4 */
-	[SCP_IRQ_SPM]			= { INTC_GRP_0 },
-	[SCP_IRQ_AP_CIRQ]		= { INTC_GRP_0 },
-	[SCP_IRQ_EINT]			= { INTC_GRP_0 },
-	[SCP_IRQ_PMIC]			= { INTC_GRP_0 },
+	[SCP_IRQ_SPM] = { INTC_GRP_0 },
+	[SCP_IRQ_AP_CIRQ] = { INTC_GRP_0 },
+	[SCP_IRQ_EINT] = { INTC_GRP_0 },
+	[SCP_IRQ_PMIC] = { INTC_GRP_0 },
 	/* 8 */
-	[SCP_IRQ_UART0_TX]		= { INTC_GRP_12 },
-	[SCP_IRQ_UART1_TX]		= { INTC_GRP_12 },
-	[SCP_IRQ_I2C0]			= { INTC_GRP_0 },
-	[SCP_IRQ_I2C1_0]		= { INTC_GRP_0 },
+	[SCP_IRQ_UART0_TX] = { INTC_GRP_12 },
+	[SCP_IRQ_UART1_TX] = { INTC_GRP_12 },
+	[SCP_IRQ_I2C0] = { INTC_GRP_0 },
+	[SCP_IRQ_I2C1_0] = { INTC_GRP_0 },
 	/* 12 */
-	[SCP_IRQ_BUS_DBG_TRACKER]	= { INTC_GRP_0 },
-	[SCP_IRQ_CLK_CTRL]		= { INTC_GRP_0 },
-	[SCP_IRQ_VOW]			= { INTC_GRP_0 },
-	[SCP_IRQ_TIMER0]		= { INTC_GRP_6 },
+	[SCP_IRQ_BUS_DBG_TRACKER] = { INTC_GRP_0 },
+	[SCP_IRQ_CLK_CTRL] = { INTC_GRP_0 },
+	[SCP_IRQ_VOW] = { INTC_GRP_0 },
+	[SCP_IRQ_TIMER0] = { INTC_GRP_6 },
 	/* 16 */
-	[SCP_IRQ_TIMER1]		= { INTC_GRP_6 },
-	[SCP_IRQ_TIMER2]		= { INTC_GRP_6 },
-	[SCP_IRQ_TIMER3]		= { INTC_GRP_6 },
-	[SCP_IRQ_TIMER4]		= { INTC_GRP_6 },
+	[SCP_IRQ_TIMER1] = { INTC_GRP_6 },
+	[SCP_IRQ_TIMER2] = { INTC_GRP_6 },
+	[SCP_IRQ_TIMER3] = { INTC_GRP_6 },
+	[SCP_IRQ_TIMER4] = { INTC_GRP_6 },
 	/* 20 */
-	[SCP_IRQ_TIMER5]		= { INTC_GRP_6 },
-	[SCP_IRQ_OS_TIMER]		= { INTC_GRP_0 },
-	[SCP_IRQ_UART0_RX]		= { INTC_GRP_12 },
-	[SCP_IRQ_UART1_RX]		= { INTC_GRP_12 },
+	[SCP_IRQ_TIMER5] = { INTC_GRP_6 },
+	[SCP_IRQ_OS_TIMER] = { INTC_GRP_0 },
+	[SCP_IRQ_UART0_RX] = { INTC_GRP_12 },
+	[SCP_IRQ_UART1_RX] = { INTC_GRP_12 },
 	/* 24 */
-	[SCP_IRQ_GDMA]			= { INTC_GRP_0 },
-	[SCP_IRQ_AUDIO]			= { INTC_GRP_0 },
-	[SCP_IRQ_MD_DSP]		= { INTC_GRP_0 },
-	[SCP_IRQ_ADSP]			= { INTC_GRP_0 },
+	[SCP_IRQ_GDMA] = { INTC_GRP_0 },
+	[SCP_IRQ_AUDIO] = { INTC_GRP_0 },
+	[SCP_IRQ_MD_DSP] = { INTC_GRP_0 },
+	[SCP_IRQ_ADSP] = { INTC_GRP_0 },
 	/* 28 */
-	[SCP_IRQ_CPU_TICK]		= { INTC_GRP_0 },
-	[SCP_IRQ_SPI0]			= { INTC_GRP_0 },
-	[SCP_IRQ_SPI1]			= { INTC_GRP_0 },
-	[SCP_IRQ_SPI2]			= { INTC_GRP_0 },
+	[SCP_IRQ_CPU_TICK] = { INTC_GRP_0 },
+	[SCP_IRQ_SPI0] = { INTC_GRP_0 },
+	[SCP_IRQ_SPI1] = { INTC_GRP_0 },
+	[SCP_IRQ_SPI2] = { INTC_GRP_0 },
 	/* 32 */
-	[SCP_IRQ_NEW_INFRA_SYS_CIRQ]	= { INTC_GRP_0 },
-	[SCP_IRQ_DBG]			= { INTC_GRP_0 },
-	[SCP_IRQ_GCE]			= { INTC_GRP_0 },
-	[SCP_IRQ_MDP_GCE]		= { INTC_GRP_0 },
+	[SCP_IRQ_NEW_INFRA_SYS_CIRQ] = { INTC_GRP_0 },
+	[SCP_IRQ_DBG] = { INTC_GRP_0 },
+	[SCP_IRQ_GCE] = { INTC_GRP_0 },
+	[SCP_IRQ_MDP_GCE] = { INTC_GRP_0 },
 	/* 36 */
-	[SCP_IRQ_VDEC]			= { INTC_GRP_8 },
-	[SCP_IRQ_WDT]			= { INTC_GRP_0 },
-	[SCP_IRQ_VDEC_LAT]		= { INTC_GRP_8 },
-	[SCP_IRQ_VDEC1]			= { INTC_GRP_8 },
+	[SCP_IRQ_VDEC] = { INTC_GRP_8 },
+	[SCP_IRQ_WDT] = { INTC_GRP_0 },
+	[SCP_IRQ_VDEC_LAT] = { INTC_GRP_8 },
+	[SCP_IRQ_VDEC1] = { INTC_GRP_8 },
 	/* 40 */
-	[SCP_IRQ_VDEC1_LAT]		= { INTC_GRP_8 },
-	[SCP_IRQ_INFRA]			= { INTC_GRP_0 },
-	[SCP_IRQ_CLK_CTRL_CORE]		= { INTC_GRP_0 },
-	[SCP_IRQ_CLK_CTRL2_CORE]	= { INTC_GRP_0 },
+	[SCP_IRQ_VDEC1_LAT] = { INTC_GRP_8 },
+	[SCP_IRQ_INFRA] = { INTC_GRP_0 },
+	[SCP_IRQ_CLK_CTRL_CORE] = { INTC_GRP_0 },
+	[SCP_IRQ_CLK_CTRL2_CORE] = { INTC_GRP_0 },
 	/* 44 */
-	[SCP_IRQ_CLK_CTRL2]		= { INTC_GRP_0 },
-	[SCP_IRQ_GIPC_IN4]		= { INTC_GRP_0 },
-	[SCP_IRQ_PERIBUS_TIMEOUT]	= { INTC_GRP_0 },
-	[SCP_IRQ_INFRABUS_TIMEOUT]	= { INTC_GRP_0 },
+	[SCP_IRQ_CLK_CTRL2] = { INTC_GRP_0 },
+	[SCP_IRQ_GIPC_IN4] = { INTC_GRP_0 },
+	[SCP_IRQ_PERIBUS_TIMEOUT] = { INTC_GRP_0 },
+	[SCP_IRQ_INFRABUS_TIMEOUT] = { INTC_GRP_0 },
 	/* 48 */
-	[SCP_IRQ_MET0]			= { INTC_GRP_0 },
-	[SCP_IRQ_MET1]			= { INTC_GRP_0 },
-	[SCP_IRQ_MET2]			= { INTC_GRP_0 },
-	[SCP_IRQ_MET3]			= { INTC_GRP_0 },
+	[SCP_IRQ_MET0] = { INTC_GRP_0 },
+	[SCP_IRQ_MET1] = { INTC_GRP_0 },
+	[SCP_IRQ_MET2] = { INTC_GRP_0 },
+	[SCP_IRQ_MET3] = { INTC_GRP_0 },
 	/* 52 */
-	[SCP_IRQ_AP_WDT]		= { INTC_GRP_0 },
-	[SCP_IRQ_L2TCM_SEC_VIO]		= { INTC_GRP_0 },
-	[SCP_IRQ_VDEC_INT_LINE_CNT]	= { INTC_GRP_0 },
-	[SCP_IRQ_VOW_DATAIN]		= { INTC_GRP_0 },
+	[SCP_IRQ_AP_WDT] = { INTC_GRP_0 },
+	[SCP_IRQ_L2TCM_SEC_VIO] = { INTC_GRP_0 },
+	[SCP_IRQ_VDEC_INT_LINE_CNT] = { INTC_GRP_0 },
+	[SCP_IRQ_VOW_DATAIN] = { INTC_GRP_0 },
 	/* 56 */
-	[SCP_IRQ_I3C0_IBI_WAKE]		= { INTC_GRP_0 },
-	[SCP_IRQ_I3C1_IBI_WAKE]		= { INTC_GRP_0 },
-	[SCP_IRQ_VENC]			= { INTC_GRP_8 },
-	[SCP_IRQ_APU_ENGINE]		= { INTC_GRP_0 },
+	[SCP_IRQ_I3C0_IBI_WAKE] = { INTC_GRP_0 },
+	[SCP_IRQ_I3C1_IBI_WAKE] = { INTC_GRP_0 },
+	[SCP_IRQ_VENC] = { INTC_GRP_8 },
+	[SCP_IRQ_APU_ENGINE] = { INTC_GRP_0 },
 	/* 60 */
-	[SCP_IRQ_MBOX0]			= { INTC_GRP_0 },
-	[SCP_IRQ_MBOX1]			= { INTC_GRP_0 },
-	[SCP_IRQ_MBOX2]			= { INTC_GRP_0 },
-	[SCP_IRQ_MBOX3]			= { INTC_GRP_0 },
+	[SCP_IRQ_MBOX0] = { INTC_GRP_0 },
+	[SCP_IRQ_MBOX1] = { INTC_GRP_0 },
+	[SCP_IRQ_MBOX2] = { INTC_GRP_0 },
+	[SCP_IRQ_MBOX3] = { INTC_GRP_0 },
 	/* 64 */
-	[SCP_IRQ_MBOX4]			= { INTC_GRP_0 },
-	[SCP_IRQ_SYS_CLK_REQ]		= { INTC_GRP_0 },
-	[SCP_IRQ_BUS_REQ]		= { INTC_GRP_0 },
-	[SCP_IRQ_APSRC_REQ]		= { INTC_GRP_0 },
+	[SCP_IRQ_MBOX4] = { INTC_GRP_0 },
+	[SCP_IRQ_SYS_CLK_REQ] = { INTC_GRP_0 },
+	[SCP_IRQ_BUS_REQ] = { INTC_GRP_0 },
+	[SCP_IRQ_APSRC_REQ] = { INTC_GRP_0 },
 	/* 68 */
-	[SCP_IRQ_APU_MBOX]		= { INTC_GRP_0 },
-	[SCP_IRQ_DEVAPC_SECURE_VIO]	= { INTC_GRP_0 },
-	[SCP_IRQ_APDMA0]		= { INTC_GRP_0 },
-	[SCP_IRQ_APDMA1]		= { INTC_GRP_0 },
+	[SCP_IRQ_APU_MBOX] = { INTC_GRP_0 },
+	[SCP_IRQ_DEVAPC_SECURE_VIO] = { INTC_GRP_0 },
+	[SCP_IRQ_APDMA0] = { INTC_GRP_0 },
+	[SCP_IRQ_APDMA1] = { INTC_GRP_0 },
 	/* 72 */
-	[SCP_IRQ_APDMA2]		= { INTC_GRP_0 },
-	[SCP_IRQ_APDMA3]		= { INTC_GRP_0 },
-	[SCP_IRQ_APDMA4]		= { INTC_GRP_0 },
-	[SCP_IRQ_APDMA5]		= { INTC_GRP_0 },
+	[SCP_IRQ_APDMA2] = { INTC_GRP_0 },
+	[SCP_IRQ_APDMA3] = { INTC_GRP_0 },
+	[SCP_IRQ_APDMA4] = { INTC_GRP_0 },
+	[SCP_IRQ_APDMA5] = { INTC_GRP_0 },
 	/* 76 */
-	[SCP_IRQ_HDMIRX_PM_DVI_SQH]	= { INTC_GRP_0 },
-	[SCP_IRQ_HDMIRX_RESERVED]	= { INTC_GRP_0 },
-	[SCP_IRQ_NNA0_0]		= { INTC_GRP_0 },
-	[SCP_IRQ_NNA0_1]		= { INTC_GRP_0 },
+	[SCP_IRQ_HDMIRX_PM_DVI_SQH] = { INTC_GRP_0 },
+	[SCP_IRQ_HDMIRX_RESERVED] = { INTC_GRP_0 },
+	[SCP_IRQ_NNA0_0] = { INTC_GRP_0 },
+	[SCP_IRQ_NNA0_1] = { INTC_GRP_0 },
 	/* 80 */
-	[SCP_IRQ_NNA0_2]		= { INTC_GRP_0 },
-	[SCP_IRQ_NNA1_0]		= { INTC_GRP_0 },
-	[SCP_IRQ_NNA1_1]		= { INTC_GRP_0 },
-	[SCP_IRQ_NNA1_2]		= { INTC_GRP_0 },
+	[SCP_IRQ_NNA0_2] = { INTC_GRP_0 },
+	[SCP_IRQ_NNA1_0] = { INTC_GRP_0 },
+	[SCP_IRQ_NNA1_1] = { INTC_GRP_0 },
+	[SCP_IRQ_NNA1_2] = { INTC_GRP_0 },
 	/* 84 */
-	[SCP_IRQ_JPEGENC]		= { INTC_GRP_0 },
-	[SCP_IRQ_JPEGDEC]		= { INTC_GRP_0 },
-	[SCP_IRQ_JPEGDEC_C2]		= { INTC_GRP_0 },
-	[SCP_IRQ_VENC_C1]		= { INTC_GRP_8 },
+	[SCP_IRQ_JPEGENC] = { INTC_GRP_0 },
+	[SCP_IRQ_JPEGDEC] = { INTC_GRP_0 },
+	[SCP_IRQ_JPEGDEC_C2] = { INTC_GRP_0 },
+	[SCP_IRQ_VENC_C1] = { INTC_GRP_8 },
 	/* 88 */
-	[SCP_IRQ_JPEGENC_C1]		= { INTC_GRP_0 },
-	[SCP_IRQ_JPEGDEC_C1]		= { INTC_GRP_0 },
-	[SCP_IRQ_HDMITX]		= { INTC_GRP_0 },
-	[SCP_IRQ_HDMI2]			= { INTC_GRP_0 },
+	[SCP_IRQ_JPEGENC_C1] = { INTC_GRP_0 },
+	[SCP_IRQ_JPEGDEC_C1] = { INTC_GRP_0 },
+	[SCP_IRQ_HDMITX] = { INTC_GRP_0 },
+	[SCP_IRQ_HDMI2] = { INTC_GRP_0 },
 	/* 92 */
-	[SCP_IRQ_EARC]			= { INTC_GRP_0 },
-	[SCP_IRQ_CEC]			= { INTC_GRP_0 },
-	[SCP_IRQ_HDMI_DEV_DET]		= { INTC_GRP_0 },
-	[SCP_IRQ_HDMIRX_OUT_ARM_PHY]	= { INTC_GRP_0 },
+	[SCP_IRQ_EARC] = { INTC_GRP_0 },
+	[SCP_IRQ_CEC] = { INTC_GRP_0 },
+	[SCP_IRQ_HDMI_DEV_DET] = { INTC_GRP_0 },
+	[SCP_IRQ_HDMIRX_OUT_ARM_PHY] = { INTC_GRP_0 },
 	/* 96 */
-	[SCP_IRQ_I2C2]			= { INTC_GRP_0 },
-	[SCP_IRQ_I2C3]			= { INTC_GRP_0 },
-	[SCP_IRQ_I3C2_IBI_WAKE]		= { INTC_GRP_0 },
-	[SCP_IRQ_I3C3_IBI_WAKE]		= { INTC_GRP_0 },
+	[SCP_IRQ_I2C2] = { INTC_GRP_0 },
+	[SCP_IRQ_I2C3] = { INTC_GRP_0 },
+	[SCP_IRQ_I3C2_IBI_WAKE] = { INTC_GRP_0 },
+	[SCP_IRQ_I3C3_IBI_WAKE] = { INTC_GRP_0 },
 	/* 100 */
-	[SCP_IRQ_SYS_I2C_0]		= { INTC_GRP_0 },
-	[SCP_IRQ_SYS_I2C_1]		= { INTC_GRP_0 },
-	[SCP_IRQ_SYS_I2C_2]		= { INTC_GRP_0 },
-	[SCP_IRQ_SYS_I2C_3]		= { INTC_GRP_0 },
+	[SCP_IRQ_SYS_I2C_0] = { INTC_GRP_0 },
+	[SCP_IRQ_SYS_I2C_1] = { INTC_GRP_0 },
+	[SCP_IRQ_SYS_I2C_2] = { INTC_GRP_0 },
+	[SCP_IRQ_SYS_I2C_3] = { INTC_GRP_0 },
 	/* 104 */
-	[SCP_IRQ_SYS_I2C_4]		= { INTC_GRP_0 },
-	[SCP_IRQ_SYS_I2C_5]		= { INTC_GRP_0 },
-	[SCP_IRQ_SYS_I2C_6]		= { INTC_GRP_0 },
-	[SCP_IRQ_SYS_I2C_7]		= { INTC_GRP_0 },
+	[SCP_IRQ_SYS_I2C_4] = { INTC_GRP_0 },
+	[SCP_IRQ_SYS_I2C_5] = { INTC_GRP_0 },
+	[SCP_IRQ_SYS_I2C_6] = { INTC_GRP_0 },
+	[SCP_IRQ_SYS_I2C_7] = { INTC_GRP_0 },
 	/* 108 */
-	[SCP_IRQ_DISP2ADSP_0]		= { INTC_GRP_0 },
-	[SCP_IRQ_DISP2ADSP_1]		= { INTC_GRP_0 },
-	[SCP_IRQ_DISP2ADSP_2]		= { INTC_GRP_0 },
-	[SCP_IRQ_DISP2ADSP_3]		= { INTC_GRP_0 },
+	[SCP_IRQ_DISP2ADSP_0] = { INTC_GRP_0 },
+	[SCP_IRQ_DISP2ADSP_1] = { INTC_GRP_0 },
+	[SCP_IRQ_DISP2ADSP_2] = { INTC_GRP_0 },
+	[SCP_IRQ_DISP2ADSP_3] = { INTC_GRP_0 },
 	/* 112 */
-	[SCP_IRQ_DISP2ADSP_4]		= { INTC_GRP_0 },
-	[SCP_IRQ_VDO1_DISP_MON2ADSP_0]	= { INTC_GRP_0 },
-	[SCP_IRQ_VDO1_DISP_MON2ADSP_1]	= { INTC_GRP_0 },
-	[SCP_IRQ_VDO1_DISP_MON2ADSP_2]	= { INTC_GRP_0 },
+	[SCP_IRQ_DISP2ADSP_4] = { INTC_GRP_0 },
+	[SCP_IRQ_VDO1_DISP_MON2ADSP_0] = { INTC_GRP_0 },
+	[SCP_IRQ_VDO1_DISP_MON2ADSP_1] = { INTC_GRP_0 },
+	[SCP_IRQ_VDO1_DISP_MON2ADSP_2] = { INTC_GRP_0 },
 	/* 116 */
-	[SCP_IRQ_GCE1_SECURE]		= { INTC_GRP_0 },
-	[SCP_IRQ_GCE_SECURE]		= { INTC_GRP_0 },
+	[SCP_IRQ_GCE1_SECURE] = { INTC_GRP_0 },
+	[SCP_IRQ_GCE_SECURE] = { INTC_GRP_0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(irqs) == SCP_INTC_IRQ_COUNT);
 #endif
diff --git a/chip/mt_scp/rv32i_common/ipi.c b/chip/mt_scp/rv32i_common/ipi.c
index a7fc720d42..b8db16b9ea 100644
--- a/chip/mt_scp/rv32i_common/ipi.c
+++ b/chip/mt_scp/rv32i_common/ipi.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -177,7 +177,7 @@ static void irq_group7_handler(void)
 	if (SCP_GIPC_IN_SET & GIPC_IN(0)) {
 		ipi_handler();
 		SCP_GIPC_IN_CLR = GIPC_IN(0);
-		asm volatile ("fence.i" ::: "memory");
+		asm volatile("fence.i" ::: "memory");
 		task_clear_pending_irq(ec_int);
 	}
 }
diff --git a/chip/mt_scp/rv32i_common/ipi_chip.h b/chip/mt_scp/rv32i_common/ipi_chip.h
index 47a9434b09..22ab85b39e 100644
--- a/chip/mt_scp/rv32i_common/ipi_chip.h
+++ b/chip/mt_scp/rv32i_common/ipi_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -72,15 +72,15 @@ extern int *const ipi_wakeup_table[];
  * handler: The IPI handler function
  * is_wakeup_src: Declare IPI ID as a wake-up source or not
  */
-#define DECLARE_IPI(_id, handler, is_wakeup_src) \
-	struct ipi_num_check##_id { \
-		int tmp1[_id < IPI_COUNT ? 1 : -1]; \
+#define DECLARE_IPI(_id, handler, is_wakeup_src)                             \
+	struct ipi_num_check##_id {                                          \
+		int tmp1[_id < IPI_COUNT ? 1 : -1];                          \
 		int tmp2[is_wakeup_src == 0 || is_wakeup_src == 1 ? 1 : -1]; \
-	};  \
-	void __keep IPI_HANDLER(_id)(int32_t id, void *buf, uint32_t len) \
-	{ \
-		handler(id, buf, len); \
-	} \
+	};                                                                   \
+	void __keep IPI_HANDLER(_id)(int32_t id, void *buf, uint32_t len)    \
+	{                                                                    \
+		handler(id, buf, len);                                       \
+	}                                                                    \
 	const int __keep IPI_WAKEUP(_id) = is_wakeup_src
 
 #endif /* __CROS_EC_IPI_CHIP_H */
diff --git a/chip/mt_scp/rv32i_common/ipi_table.c b/chip/mt_scp/rv32i_common/ipi_table.c
index 8fe3f1e598..3a6411d4d2 100644
--- a/chip/mt_scp/rv32i_common/ipi_table.c
+++ b/chip/mt_scp/rv32i_common/ipi_table.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -17,21 +17,24 @@ typedef void (*ipi_handler_t)(int32_t id, void *data, uint32_t len);
 #define ipi_arguments int32_t id, void *data, uint32_t len
 
 #if PASS == 1
-void ipi_handler_undefined(ipi_arguments) { }
+void ipi_handler_undefined(ipi_arguments)
+{
+}
 
 const int ipi_wakeup_undefined;
 
 #define table(type, name, x) x
 
-#define ipi_x_func(suffix, args, number)                                       \
-	extern void __attribute__(                                             \
-		(used, weak, alias(STRINGIFY(ipi_##suffix##_undefined))))      \
+#define ipi_x_func(suffix, args, number)                                    \
+	extern void                                                         \
+		__attribute__((used, weak,                                  \
+			       alias(STRINGIFY(ipi_##suffix##_undefined)))) \
 		ipi_##number##_##suffix(args);
 
 #define ipi_x_var(suffix, number)                                              \
-	extern int __attribute__(                                              \
-		(weak, alias(STRINGIFY(ipi_##suffix##_undefined))))            \
-		ipi_##number##_##suffix;
+	extern int __attribute__((weak,                                        \
+				  alias(STRINGIFY(ipi_##suffix##_undefined)))) \
+	ipi_##number##_##suffix;
 
 #endif /* PASS == 1 */
 
@@ -41,11 +44,11 @@ const int ipi_wakeup_undefined;
 #undef ipi_x_func
 #undef ipi_x_var
 
-#define table(type, name, x)                                                   \
-	type const name[]                                                      \
-		__attribute__((aligned(4), used, section(".rodata.ipi"))) = {x}
+#define table(type, name, x)                               \
+	type const name[] __attribute__((aligned(4), used, \
+					 section(".rodata.ipi"))) = { x }
 
-#define ipi_x_var(suffix, number)                                              \
+#define ipi_x_var(suffix, number) \
 	[number < IPI_COUNT ? number : -1] = &ipi_##number##_##suffix,
 
 #define ipi_x_func(suffix, args, number) ipi_x_var(suffix, number)
diff --git a/chip/mt_scp/rv32i_common/memmap.c b/chip/mt_scp/rv32i_common/memmap.c
index a666bb23d7..8ae64cf585 100644
--- a/chip/mt_scp/rv32i_common/memmap.c
+++ b/chip/mt_scp/rv32i_common/memmap.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -33,53 +33,48 @@
  * 0xf000_0000	0x6000_0000
  */
 
-#define REMAP_ADDR_SHIFT		28
-#define REMAP_ADDR_LSB_MASK		(BIT(REMAP_ADDR_SHIFT) - 1)
-#define REMAP_ADDR_MSB_MASK		((~0) << REMAP_ADDR_SHIFT)
+#define REMAP_ADDR_SHIFT 28
+#define REMAP_ADDR_LSB_MASK (BIT(REMAP_ADDR_SHIFT) - 1)
+#define REMAP_ADDR_MSB_MASK ((~0) << REMAP_ADDR_SHIFT)
 #define MAP_INVALID 0xff
 
 static const uint8_t addr_map[16] = {
-	MAP_INVALID,	/* SRAM */
-	0x5,		/* ext_addr_0x1 */
-	0x7,		/* ext_addr_0x2 */
-	MAP_INVALID,	/* no ext_addr_0x3 */
-
-	MAP_INVALID,	/* no ext_addr_0x4 */
-	0x0,		/* ext_addr_0x5 */
-	0x1,		/* ext_addr_0x6 */
-	0xa,		/* ext_addr_0x7 */
-
-	MAP_INVALID,	/* no ext_addr_0x8 */
-	0x8,		/* ext_addr_0x9 */
-	0x9,		/* ext_addr_0xa */
-	MAP_INVALID,	/* no ext_addr_0xb */
-
-	0x8,		/* ext_addr_0xc */
-	0x2,		/* ext_addr_0xd */
-	0x3,		/* ext_addr_0xe */
-	0x6,		/* ext_addr_0xf */
+	MAP_INVALID, /* SRAM */
+	0x5, /* ext_addr_0x1 */
+	0x7, /* ext_addr_0x2 */
+	MAP_INVALID, /* no ext_addr_0x3 */
+
+	MAP_INVALID, /* no ext_addr_0x4 */
+	0x0, /* ext_addr_0x5 */
+	0x1, /* ext_addr_0x6 */
+	0xa, /* ext_addr_0x7 */
+
+	MAP_INVALID, /* no ext_addr_0x8 */
+	0x8, /* ext_addr_0x9 */
+	0x9, /* ext_addr_0xa */
+	MAP_INVALID, /* no ext_addr_0xb */
+
+	0x8, /* ext_addr_0xc */
+	0x2, /* ext_addr_0xd */
+	0x3, /* ext_addr_0xe */
+	0x6, /* ext_addr_0xf */
 };
 
 void memmap_init(void)
 {
-	SCP_R_REMAP_0X0123 =
-		(uint32_t)addr_map[0x1] << 8 |
-		(uint32_t)addr_map[0x2] << 16;
+	SCP_R_REMAP_0X0123 = (uint32_t)addr_map[0x1] << 8 |
+			     (uint32_t)addr_map[0x2] << 16;
 
-	SCP_R_REMAP_0X4567 =
-		(uint32_t)addr_map[0x5] << 8 |
-		(uint32_t)addr_map[0x6] << 16 |
-		(uint32_t)addr_map[0x7] << 24;
+	SCP_R_REMAP_0X4567 = (uint32_t)addr_map[0x5] << 8 |
+			     (uint32_t)addr_map[0x6] << 16 |
+			     (uint32_t)addr_map[0x7] << 24;
 
-	SCP_R_REMAP_0X89AB =
-		(uint32_t)addr_map[0x9] << 8 |
-		(uint32_t)addr_map[0xa] << 16;
+	SCP_R_REMAP_0X89AB = (uint32_t)addr_map[0x9] << 8 |
+			     (uint32_t)addr_map[0xa] << 16;
 
 	SCP_R_REMAP_0XCDEF =
-		(uint32_t)addr_map[0xc] |
-		(uint32_t)addr_map[0xd] << 8 |
-		(uint32_t)addr_map[0xe] << 16 |
-		(uint32_t)addr_map[0xf] << 24;
+		(uint32_t)addr_map[0xc] | (uint32_t)addr_map[0xd] << 8 |
+		(uint32_t)addr_map[0xe] << 16 | (uint32_t)addr_map[0xf] << 24;
 
 	cache_init();
 }
@@ -94,7 +89,7 @@ int memmap_ap_to_scp(uintptr_t ap_addr, uintptr_t *scp_addr)
 			continue;
 
 		*scp_addr = (ap_addr & REMAP_ADDR_LSB_MASK) |
-			(i << REMAP_ADDR_SHIFT);
+			    (i << REMAP_ADDR_SHIFT);
 		return EC_SUCCESS;
 	}
 
@@ -109,6 +104,6 @@ int memmap_scp_to_ap(uintptr_t scp_addr, uintptr_t *ap_addr)
 		return EC_ERROR_INVAL;
 
 	*ap_addr = (scp_addr & REMAP_ADDR_LSB_MASK) |
-		(addr_map[i] << REMAP_ADDR_SHIFT);
+		   (addr_map[i] << REMAP_ADDR_SHIFT);
 	return EC_SUCCESS;
 }
diff --git a/chip/mt_scp/rv32i_common/memmap.h b/chip/mt_scp/rv32i_common/memmap.h
index 0857c9a89e..2c043fbe9c 100644
--- a/chip/mt_scp/rv32i_common/memmap.h
+++ b/chip/mt_scp/rv32i_common/memmap.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/mt_scp/rv32i_common/registers.h b/chip/mt_scp/rv32i_common/registers.h
index afe706948e..8688bbc033 100644
--- a/chip/mt_scp/rv32i_common/registers.h
+++ b/chip/mt_scp/rv32i_common/registers.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,200 +14,202 @@
 
 #define UNIMPLEMENTED_GPIO_BANK 0
 
-#define SCP_REG_BASE			0x70000000
+#define SCP_REG_BASE 0x70000000
 
 /* clock control */
-#define SCP_CLK_CTRL_BASE		(SCP_REG_BASE + 0x21000)
+#define SCP_CLK_CTRL_BASE (SCP_REG_BASE + 0x21000)
 /* system clock counter value */
-#define SCP_CLK_SYS_VAL			REG32(SCP_CLK_CTRL_BASE + 0x0014)
-#define   CLK_SYS_VAL_MASK		(0x3ff << 0)
-#define   CLK_SYS_VAL_VAL(v)		((v) & CLK_SYS_VAL_MASK)
+#define SCP_CLK_SYS_VAL REG32(SCP_CLK_CTRL_BASE + 0x0014)
+#define CLK_SYS_VAL_MASK (0x3ff << 0)
+#define CLK_SYS_VAL_VAL(v) ((v)&CLK_SYS_VAL_MASK)
 /* ULPOSC clock counter value */
-#define SCP_CLK_HIGH_VAL		REG32(SCP_CLK_CTRL_BASE + 0x0018)
-#define   CLK_HIGH_VAL_MASK             (0x1f << 0)
-#define   CLK_HIGH_VAL_VAL(v)		((v) & CLK_HIGH_VAL_MASK)
+#define SCP_CLK_HIGH_VAL REG32(SCP_CLK_CTRL_BASE + 0x0018)
+#define CLK_HIGH_VAL_MASK (0x1f << 0)
+#define CLK_HIGH_VAL_VAL(v) ((v)&CLK_HIGH_VAL_MASK)
 /* sleep mode control */
-#define SCP_SLEEP_CTRL                  REG32(SCP_CLK_CTRL_BASE + 0x0020)
-#define   SLP_CTRL_EN			BIT(0)
-#define   VREQ_COUNT_MASK		(0x7F << 1)
-#define   VREQ_COUNT_VAL(v)		(((v) << 1) & VREQ_COUNT_MASK)
-#define   SPM_SLP_MODE			BIT(8)
+#define SCP_SLEEP_CTRL REG32(SCP_CLK_CTRL_BASE + 0x0020)
+#define SLP_CTRL_EN BIT(0)
+#define VREQ_COUNT_MASK (0x7F << 1)
+#define VREQ_COUNT_VAL(v) (((v) << 1) & VREQ_COUNT_MASK)
+#define SPM_SLP_MODE BIT(8)
 /* clock divider select */
-#define SCP_CLK_DIV_SEL			REG32(SCP_CLK_CTRL_BASE + 0x0024)
-#define   CLK_DIV_SEL1			0
-#define   CLK_DIV_SEL2			1
-#define   CLK_DIV_SEL4			2
-#define   CLK_DIV_SEL3			3
+#define SCP_CLK_DIV_SEL REG32(SCP_CLK_CTRL_BASE + 0x0024)
+#define CLK_DIV_SEL1 0
+#define CLK_DIV_SEL2 1
+#define CLK_DIV_SEL4 2
+#define CLK_DIV_SEL3 3
 /* clock gate */
-#define SCP_SET_CLK_CG			REG32(SCP_CLK_CTRL_BASE + 0x0030)
-#define   CG_TIMER_MCLK			BIT(0)
-#define   CG_TIMER_BCLK			BIT(1)
-#define   CG_MAD_MCLK			BIT(2)
-#define   CG_I2C_MCLK			BIT(3)
-#define   CG_I2C_BCLK			BIT(4)
-#define   CG_GPIO_MCLK			BIT(5)
-#define   CG_AP2P_MCLK			BIT(6)
-#define   CG_UART0_MCLK			BIT(7)
-#define   CG_UART0_BCLK			BIT(8)
-#define   CG_UART0_RST			BIT(9)
-#define   CG_UART1_MCLK			BIT(10)
-#define   CG_UART1_BCLK			BIT(11)
-#define   CG_UART1_RST			BIT(12)
-#define   CG_SPI0			BIT(13)
-#define   CG_SPI1			BIT(14)
-#define   CG_SPI2			BIT(15)
-#define   CG_DMA_CH0			BIT(16)
-#define   CG_DMA_CH1			BIT(17)
-#define   CG_DMA_CH2			BIT(18)
-#define   CG_DMA_CH3			BIT(19)
-#define   CG_I3C0			BIT(21)
-#define   CG_I3C1			BIT(22)
-#define   CG_DMA2_CH0			BIT(23)
-#define   CG_DMA2_CH1			BIT(24)
-#define   CG_DMA2_CH2			BIT(25)
-#define   CG_DMA2_CH3			BIT(26)
+#define SCP_SET_CLK_CG REG32(SCP_CLK_CTRL_BASE + 0x0030)
+#define CG_TIMER_MCLK BIT(0)
+#define CG_TIMER_BCLK BIT(1)
+#define CG_MAD_MCLK BIT(2)
+#define CG_I2C_MCLK BIT(3)
+#define CG_I2C_BCLK BIT(4)
+#define CG_GPIO_MCLK BIT(5)
+#define CG_AP2P_MCLK BIT(6)
+#define CG_UART0_MCLK BIT(7)
+#define CG_UART0_BCLK BIT(8)
+#define CG_UART0_RST BIT(9)
+#define CG_UART1_MCLK BIT(10)
+#define CG_UART1_BCLK BIT(11)
+#define CG_UART1_RST BIT(12)
+#define CG_SPI0 BIT(13)
+#define CG_SPI1 BIT(14)
+#define CG_SPI2 BIT(15)
+#define CG_DMA_CH0 BIT(16)
+#define CG_DMA_CH1 BIT(17)
+#define CG_DMA_CH2 BIT(18)
+#define CG_DMA_CH3 BIT(19)
+#define CG_I3C0 BIT(21)
+#define CG_I3C1 BIT(22)
+#define CG_DMA2_CH0 BIT(23)
+#define CG_DMA2_CH1 BIT(24)
+#define CG_DMA2_CH2 BIT(25)
+#define CG_DMA2_CH3 BIT(26)
 /* UART clock select */
-#define SCP_UART_CK_SEL			REG32(SCP_CLK_CTRL_BASE + 0x0044)
-#define   UART0_CK_SEL_SHIFT		0
-#define   UART0_CK_SEL_MASK		(0x3 << UART0_CK_SEL_SHIFT)
-#define   UART0_CK_SEL_VAL(v)		((v) & UART0_CK_SEL_MASK)
-#define   UART0_CK_SW_STATUS_MASK	(0xf << 8)
-#define   UART0_CK_SW_STATUS_VAL(v)	((v) & UART0_CK_SW_STATUS_MASK)
-#define   UART1_CK_SEL_SHIFT		16
-#define   UART1_CK_SEL_MASK		(0x3 << UART1_CK_SEL_SHIFT)
-#define   UART1_CK_SEL_VAL(v)		((v) & UART1_CK_SEL_MASK)
-#define   UART1_CK_SW_STATUS_MASK	(0xf << 24)
-#define   UART1_CK_SW_STATUS_VAL(v)	((v) & UART1_CK_SW_STATUS_MASK)
-#define     UART_CK_SEL_26M		0
-#define     UART_CK_SEL_32K		1
-#define     UART_CK_SEL_ULPOSC		2
-#define     UART_CK_SW_STATUS_26M	BIT(0)
-#define     UART_CK_SW_STATUS_32K	BIT(1)
-#define     UART_CK_SW_STATUS_ULPOS	BIT(2)
+#define SCP_UART_CK_SEL REG32(SCP_CLK_CTRL_BASE + 0x0044)
+#define UART0_CK_SEL_SHIFT 0
+#define UART0_CK_SEL_MASK (0x3 << UART0_CK_SEL_SHIFT)
+#define UART0_CK_SEL_VAL(v) ((v)&UART0_CK_SEL_MASK)
+#define UART0_CK_SW_STATUS_MASK (0xf << 8)
+#define UART0_CK_SW_STATUS_VAL(v) ((v)&UART0_CK_SW_STATUS_MASK)
+#define UART1_CK_SEL_SHIFT 16
+#define UART1_CK_SEL_MASK (0x3 << UART1_CK_SEL_SHIFT)
+#define UART1_CK_SEL_VAL(v) ((v)&UART1_CK_SEL_MASK)
+#define UART1_CK_SW_STATUS_MASK (0xf << 24)
+#define UART1_CK_SW_STATUS_VAL(v) ((v)&UART1_CK_SW_STATUS_MASK)
+#define UART_CK_SEL_26M 0
+#define UART_CK_SEL_32K 1
+#define UART_CK_SEL_ULPOSC 2
+#define UART_CK_SW_STATUS_26M BIT(0)
+#define UART_CK_SW_STATUS_32K BIT(1)
+#define UART_CK_SW_STATUS_ULPOS BIT(2)
 /* BCLK clock select */
-#define SCP_BCLK_CK_SEL			REG32(SCP_CLK_CTRL_BASE + 0x0048)
-#define   BCLK_CK_SEL_SYS_DIV8		0
-#define   BCLK_CK_SEL_32K		1
-#define   BCLK_CK_SEL_ULPOSC_DIV8	2
+#define SCP_BCLK_CK_SEL REG32(SCP_CLK_CTRL_BASE + 0x0048)
+#define BCLK_CK_SEL_SYS_DIV8 0
+#define BCLK_CK_SEL_32K 1
+#define BCLK_CK_SEL_ULPOSC_DIV8 2
 /* VREQ control */
-#define SCP_CPU_VREQ_CTRL		REG32(SCP_CLK_CTRL_BASE + 0x0054)
-#define   VREQ_SEL			BIT(0)
-#define   VREQ_VALUE			BIT(4)
-#define   VREQ_EXT_SEL			BIT(8)
-#define   VREQ_DVFS_SEL			BIT(16)
-#define   VREQ_DVFS_VALUE		BIT(20)
-#define   VREQ_DVFS_EXT_SEL		BIT(24)
-#define   VREQ_SRCLKEN_SEL		BIT(27)
-#define   VREQ_SRCLKEN_VALUE		BIT(28)
+#define SCP_CPU_VREQ_CTRL REG32(SCP_CLK_CTRL_BASE + 0x0054)
+#define VREQ_SEL BIT(0)
+#define VREQ_VALUE BIT(4)
+#define VREQ_EXT_SEL BIT(8)
+#define VREQ_DVFS_SEL BIT(16)
+#define VREQ_DVFS_VALUE BIT(20)
+#define VREQ_DVFS_EXT_SEL BIT(24)
+#define VREQ_SRCLKEN_SEL BIT(27)
+#define VREQ_SRCLKEN_VALUE BIT(28)
 /* clock on control */
-#define SCP_CLK_HIGH_CORE_CG		REG32(SCP_CLK_CTRL_BASE + 0x005C)
-#define   HIGH_CORE_CG			BIT(1)
-#define SCP_CLK_ON_CTRL			REG32(SCP_CLK_CTRL_BASE + 0x006C)
-#define   HIGH_AO			BIT(0)
-#define   HIGH_DIS_SUB			BIT(1)
-#define   HIGH_CG_AO			BIT(2)
-#define   HIGH_CORE_AO			BIT(4)
-#define   HIGH_CORE_DIS_SUB		BIT(5)
-#define   HIGH_CORE_CG_AO		BIT(6)
+#define SCP_CLK_HIGH_CORE_CG REG32(SCP_CLK_CTRL_BASE + 0x005C)
+#define HIGH_CORE_CG BIT(1)
+#define SCP_CLK_ON_CTRL REG32(SCP_CLK_CTRL_BASE + 0x006C)
+#define HIGH_AO BIT(0)
+#define HIGH_DIS_SUB BIT(1)
+#define HIGH_CG_AO BIT(2)
+#define HIGH_CORE_AO BIT(4)
+#define HIGH_CORE_DIS_SUB BIT(5)
+#define HIGH_CORE_CG_AO BIT(6)
 
 /* system control */
-#define SCP_SYS_CTRL			REG32(SCP_REG_BASE + 0x24000)
-#define   AUTO_DDREN			BIT(9)
+#define SCP_SYS_CTRL REG32(SCP_REG_BASE + 0x24000)
+#define AUTO_DDREN BIT(9)
 
 /* IPC */
-#define SCP_SCP2APMCU_IPC_SET		REG32(SCP_REG_BASE + 0x24080)
-#define SCP_SCP2SPM_IPC_SET		REG32(SCP_REG_BASE + 0x24090)
-#define   IPC_SCP2HOST			BIT(0)
-#define SCP_GIPC_IN_SET			REG32(SCP_REG_BASE + 0x24098)
-#define SCP_GIPC_IN_CLR			REG32(SCP_REG_BASE + 0x2409C)
-#define   GIPC_IN(n)			BIT(n)
+#define SCP_SCP2APMCU_IPC_SET REG32(SCP_REG_BASE + 0x24080)
+#define SCP_SCP2SPM_IPC_SET REG32(SCP_REG_BASE + 0x24090)
+#define IPC_SCP2HOST BIT(0)
+#define SCP_GIPC_IN_SET REG32(SCP_REG_BASE + 0x24098)
+#define SCP_GIPC_IN_CLR REG32(SCP_REG_BASE + 0x2409C)
+#define GIPC_IN(n) BIT(n)
 
 /* UART */
-#define SCP_UART_COUNT			2
-#define UART_TX_IRQ(n)			CONCAT3(SCP_IRQ_UART, n, _TX)
-#define UART_RX_IRQ(n)			CONCAT3(SCP_IRQ_UART, n, _RX)
-#define SCP_UART0_BASE			(SCP_REG_BASE + 0x26000)
-#define SCP_UART1_BASE			(SCP_REG_BASE + 0x27000)
-#define SCP_UART_BASE(n)		CONCAT3(SCP_UART, n, _BASE)
-#define UART_REG(n, offset)		REG32_ADDR(SCP_UART_BASE(n))[offset]
+#define SCP_UART_COUNT 2
+#define UART_TX_IRQ(n) CONCAT3(SCP_IRQ_UART, n, _TX)
+#define UART_RX_IRQ(n) CONCAT3(SCP_IRQ_UART, n, _RX)
+#define SCP_UART0_BASE (SCP_REG_BASE + 0x26000)
+#define SCP_UART1_BASE (SCP_REG_BASE + 0x27000)
+#define SCP_UART_BASE(n) CONCAT3(SCP_UART, n, _BASE)
+#define UART_REG(n, offset) REG32_ADDR(SCP_UART_BASE(n))[offset]
 
 /* WDT */
-#define SCP_CORE0_WDT_IRQ		REG32(SCP_REG_BASE + 0x30030)
-#define SCP_CORE0_WDT_CFG		REG32(SCP_REG_BASE + 0x30034)
-#define   WDT_FREQ			33825 /* 0xFFFFF / 31 */
-#define   WDT_MAX_PERIOD		0xFFFFF /* 31 seconds */
-#define   WDT_PERIOD(ms)		(WDT_FREQ * (ms) / 1000)
-#define   WDT_EN			BIT(31)
-#define SCP_CORE0_WDT_KICK		REG32(SCP_REG_BASE + 0x30038)
-#define SCP_CORE0_WDT_CUR_VAL		REG32(SCP_REG_BASE + 0x3003C)
-#define SCP_CORE0_MON_PC_LATCH		REG32(SCP_REG_BASE + 0x300D0)
-#define SCP_CORE0_MON_LR_LATCH		REG32(SCP_REG_BASE + 0x300D4)
-#define SCP_CORE0_MON_SP_LATCH		REG32(SCP_REG_BASE + 0x300D8)
+#define SCP_CORE0_WDT_IRQ REG32(SCP_REG_BASE + 0x30030)
+#define SCP_CORE0_WDT_CFG REG32(SCP_REG_BASE + 0x30034)
+#define WDT_FREQ 33825 /* 0xFFFFF / 31 */
+#define WDT_MAX_PERIOD 0xFFFFF /* 31 seconds */
+#define WDT_PERIOD(ms) (WDT_FREQ * (ms) / 1000)
+#define WDT_EN BIT(31)
+#define SCP_CORE0_WDT_KICK REG32(SCP_REG_BASE + 0x30038)
+#define SCP_CORE0_WDT_CUR_VAL REG32(SCP_REG_BASE + 0x3003C)
+#define SCP_CORE0_MON_PC_LATCH REG32(SCP_REG_BASE + 0x300D0)
+#define SCP_CORE0_MON_LR_LATCH REG32(SCP_REG_BASE + 0x300D4)
+#define SCP_CORE0_MON_SP_LATCH REG32(SCP_REG_BASE + 0x300D8)
 
 /* INTC */
-#define SCP_INTC_WORD(irq)		((irq) >> 5) /* word length = 2^5 */
-#define SCP_INTC_BIT(irq)		((irq) & 0x1F) /* bit shift =LSB[0:4] */
-#define SCP_INTC_GRP_COUNT		15
-#define SCP_INTC_GRP_GAP		4
+#define SCP_INTC_WORD(irq) ((irq) >> 5) /* word length = 2^5 */
+#define SCP_INTC_BIT(irq) ((irq)&0x1F) /* bit shift =LSB[0:4] */
+#define SCP_INTC_GRP_COUNT 15
+#define SCP_INTC_GRP_GAP 4
 
-#define SCP_CORE0_INTC_IRQ_BASE		(SCP_REG_BASE + 0x32000)
+#define SCP_CORE0_INTC_IRQ_BASE (SCP_REG_BASE + 0x32000)
 #define SCP_CORE0_INTC_IRQ_STA(w) \
-		REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0010)[(w)]
+	REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0010)[(w)]
 #define SCP_CORE0_INTC_IRQ_EN(w) \
-		REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0020)[(w)]
+	REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0020)[(w)]
 #define SCP_CORE0_INTC_IRQ_POL(w) \
-		REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0040)[(w)]
-#define SCP_CORE0_INTC_IRQ_GRP(g, w) \
-		REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0050 + \
-			   ((g) << SCP_INTC_GRP_GAP))[(w)]
-#define SCP_CORE0_INTC_IRQ_GRP_STA(g, w) \
-		REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0150 + \
-			   ((g) << SCP_INTC_GRP_GAP))[(w)]
+	REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0040)[(w)]
+#define SCP_CORE0_INTC_IRQ_GRP(g, w)                  \
+	REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0050 + \
+		   ((g) << SCP_INTC_GRP_GAP))         \
+	[(w)]
+#define SCP_CORE0_INTC_IRQ_GRP_STA(g, w)              \
+	REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0150 + \
+		   ((g) << SCP_INTC_GRP_GAP))         \
+	[(w)]
 #define SCP_CORE0_INTC_SLP_WAKE_EN(w) \
-		REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0240)[(w)]
-#define SCP_CORE0_INTC_IRQ_OUT		REG32(SCP_CORE0_INTC_IRQ_BASE + 0x0250)
+	REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0240)[(w)]
+#define SCP_CORE0_INTC_IRQ_OUT REG32(SCP_CORE0_INTC_IRQ_BASE + 0x0250)
 /* UART */
-#define SCP_CORE0_INTC_UART0_RX_IRQ	REG32(SCP_CORE0_INTC_IRQ_BASE + 0x0258)
-#define SCP_CORE0_INTC_UART1_RX_IRQ	REG32(SCP_CORE0_INTC_IRQ_BASE + 0x025C)
-#define SCP_CORE0_INTC_UART_RX_IRQ(n)	CONCAT3(SCP_CORE0_INTC_UART, n, _RX_IRQ)
+#define SCP_CORE0_INTC_UART0_RX_IRQ REG32(SCP_CORE0_INTC_IRQ_BASE + 0x0258)
+#define SCP_CORE0_INTC_UART1_RX_IRQ REG32(SCP_CORE0_INTC_IRQ_BASE + 0x025C)
+#define SCP_CORE0_INTC_UART_RX_IRQ(n) CONCAT3(SCP_CORE0_INTC_UART, n, _RX_IRQ)
 
 /* XGPT (general purpose timer) */
-#define NUM_TIMERS			6
-#define SCP_CORE0_TIMER_BASE(n)		(SCP_REG_BASE + 0x33000 + (0x10 * (n)))
-#define SCP_CORE0_TIMER_EN(n)		REG32(SCP_CORE0_TIMER_BASE(n) + 0x0000)
-#define   TIMER_EN			BIT(0)
-#define   TIMER_CLK_SRC_32K		(0 << 4)
-#define   TIMER_CLK_SRC_26M		(1 << 4)
-#define   TIMER_CLK_SRC_BCLK		(2 << 4)
-#define   TIMER_CLK_SRC_MCLK		(3 << 4)
-#define   TIMER_CLK_SRC_MASK		(3 << 4)
-#define SCP_CORE0_TIMER_RST_VAL(n)	REG32(SCP_CORE0_TIMER_BASE(n) + 0x0004)
-#define SCP_CORE0_TIMER_CUR_VAL(n)	REG32(SCP_CORE0_TIMER_BASE(n) + 0x0008)
-#define SCP_CORE0_TIMER_IRQ_CTRL(n)	REG32(SCP_CORE0_TIMER_BASE(n) + 0x000C)
-#define   TIMER_IRQ_EN			BIT(0)
-#define   TIMER_IRQ_STATUS		BIT(4)
-#define   TIMER_IRQ_CLR			BIT(5)
-#define SCP_IRQ_TIMER(n)		CONCAT2(SCP_IRQ_TIMER, n)
+#define NUM_TIMERS 6
+#define SCP_CORE0_TIMER_BASE(n) (SCP_REG_BASE + 0x33000 + (0x10 * (n)))
+#define SCP_CORE0_TIMER_EN(n) REG32(SCP_CORE0_TIMER_BASE(n) + 0x0000)
+#define TIMER_EN BIT(0)
+#define TIMER_CLK_SRC_32K (0 << 4)
+#define TIMER_CLK_SRC_26M (1 << 4)
+#define TIMER_CLK_SRC_BCLK (2 << 4)
+#define TIMER_CLK_SRC_MCLK (3 << 4)
+#define TIMER_CLK_SRC_MASK (3 << 4)
+#define SCP_CORE0_TIMER_RST_VAL(n) REG32(SCP_CORE0_TIMER_BASE(n) + 0x0004)
+#define SCP_CORE0_TIMER_CUR_VAL(n) REG32(SCP_CORE0_TIMER_BASE(n) + 0x0008)
+#define SCP_CORE0_TIMER_IRQ_CTRL(n) REG32(SCP_CORE0_TIMER_BASE(n) + 0x000C)
+#define TIMER_IRQ_EN BIT(0)
+#define TIMER_IRQ_STATUS BIT(4)
+#define TIMER_IRQ_CLR BIT(5)
+#define SCP_IRQ_TIMER(n) CONCAT2(SCP_IRQ_TIMER, n)
 
 /* secure control */
-#define SCP_SEC_CTRL			REG32(SCP_REG_BASE + 0xA5000)
-#define   VREQ_SECURE_DIS		BIT(4)
+#define SCP_SEC_CTRL REG32(SCP_REG_BASE + 0xA5000)
+#define VREQ_SECURE_DIS BIT(4)
 /* memory remap */
-#define SCP_R_REMAP_0X0123		REG32(SCP_REG_BASE + 0xA5060)
-#define SCP_R_REMAP_0X4567		REG32(SCP_REG_BASE + 0xA5064)
-#define SCP_R_REMAP_0X89AB		REG32(SCP_REG_BASE + 0xA5068)
-#define SCP_R_REMAP_0XCDEF		REG32(SCP_REG_BASE + 0xA506C)
+#define SCP_R_REMAP_0X0123 REG32(SCP_REG_BASE + 0xA5060)
+#define SCP_R_REMAP_0X4567 REG32(SCP_REG_BASE + 0xA5064)
+#define SCP_R_REMAP_0X89AB REG32(SCP_REG_BASE + 0xA5068)
+#define SCP_R_REMAP_0XCDEF REG32(SCP_REG_BASE + 0xA506C)
 
 /* external address: AP */
-#define AP_REG_BASE			0x60000000 /* 0x10000000 remap to 0x6 */
+#define AP_REG_BASE 0x60000000 /* 0x10000000 remap to 0x6 */
 /* AP GPIO */
-#define AP_GPIO_BASE			(AP_REG_BASE + 0x5000)
-#define AP_GPIO_MODE11_SET		REG32(AP_GPIO_BASE + 0x03B4)
-#define AP_GPIO_MODE11_CLR		REG32(AP_GPIO_BASE + 0x03B8)
-#define AP_GPIO_MODE12_SET		REG32(AP_GPIO_BASE + 0x03C4)
-#define AP_GPIO_MODE12_CLR		REG32(AP_GPIO_BASE + 0x03C8)
-#define AP_GPIO_MODE20_SET		REG32(AP_GPIO_BASE + 0x0444)
-#define AP_GPIO_MODE20_CLR		REG32(AP_GPIO_BASE + 0x0448)
+#define AP_GPIO_BASE (AP_REG_BASE + 0x5000)
+#define AP_GPIO_MODE11_SET REG32(AP_GPIO_BASE + 0x03B4)
+#define AP_GPIO_MODE11_CLR REG32(AP_GPIO_BASE + 0x03B8)
+#define AP_GPIO_MODE12_SET REG32(AP_GPIO_BASE + 0x03C4)
+#define AP_GPIO_MODE12_CLR REG32(AP_GPIO_BASE + 0x03C8)
+#define AP_GPIO_MODE20_SET REG32(AP_GPIO_BASE + 0x0444)
+#define AP_GPIO_MODE20_CLR REG32(AP_GPIO_BASE + 0x0448)
 
 #include "clock_regs.h"
 
diff --git a/chip/mt_scp/rv32i_common/scp_timer.h b/chip/mt_scp/rv32i_common/scp_timer.h
index 5c0650f913..1eed1d7792 100644
--- a/chip/mt_scp/rv32i_common/scp_timer.h
+++ b/chip/mt_scp/rv32i_common/scp_timer.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/mt_scp/rv32i_common/scp_watchdog.h b/chip/mt_scp/rv32i_common/scp_watchdog.h
index 87309a2f82..2a8225c047 100644
--- a/chip/mt_scp/rv32i_common/scp_watchdog.h
+++ b/chip/mt_scp/rv32i_common/scp_watchdog.h
@@ -1,5 +1,5 @@
 
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/mt_scp/rv32i_common/system.c b/chip/mt_scp/rv32i_common/system.c
index 0e12154f6d..0eed2ae3ff 100644
--- a/chip/mt_scp/rv32i_common/system.c
+++ b/chip/mt_scp/rv32i_common/system.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/mt_scp/rv32i_common/uart.c b/chip/mt_scp/rv32i_common/uart.c
index 35b4003c9f..a67a0bb276 100644
--- a/chip/mt_scp/rv32i_common/uart.c
+++ b/chip/mt_scp/rv32i_common/uart.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -31,9 +31,8 @@ void uart_init(void)
 	uart_init_pinmux();
 
 	/* Clear FIFO */
-	UART_FCR(UARTN) = UART_FCR_ENABLE_FIFO
-		| UART_FCR_CLEAR_RCVR
-		| UART_FCR_CLEAR_XMIT;
+	UART_FCR(UARTN) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR |
+			  UART_FCR_CLEAR_XMIT;
 	/* Line control: parity none, 8 bit, 1 stop bit */
 	UART_LCR(UARTN) = UART_LCR_WLEN8;
 	/* For baud rate <= 115200 */
@@ -137,7 +136,7 @@ static void uart_irq_handler(void)
 	case UART_RX_IRQ(UARTN):
 		uart_process();
 		SCP_CORE0_INTC_UART_RX_IRQ(UARTN) = BIT(0);
-		asm volatile ("fence.i" ::: "memory");
+		asm volatile("fence.i" ::: "memory");
 		task_clear_pending_irq(ec_int);
 		break;
 	}
diff --git a/chip/mt_scp/rv32i_common/uart_regs.h b/chip/mt_scp/rv32i_common/uart_regs.h
index c88b9c758b..d0eeaa81c2 100644
--- a/chip/mt_scp/rv32i_common/uart_regs.h
+++ b/chip/mt_scp/rv32i_common/uart_regs.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,65 +16,65 @@ void uart_init_pinmux(void);
 /* DLAB (Divisor Latch Access Bit) == 0 */
 
 /* (Read) receiver buffer register */
-#define UART_RBR(n)			UART_REG(n, 0)
+#define UART_RBR(n) UART_REG(n, 0)
 /* (Write) transmitter holding register */
-#define UART_THR(n)			UART_REG(n, 0)
+#define UART_THR(n) UART_REG(n, 0)
 /* (Write) interrupt enable register */
-#define UART_IER(n)			UART_REG(n, 1)
-#define   UART_IER_RDI			BIT(0) /* received data */
-#define   UART_IER_THRI			BIT(1) /* THR empty */
-#define   UART_IER_RLSI			BIT(2) /* receiver LSR change */
-#define   UART_IER_MSI			BIT(3) /* MSR change */
+#define UART_IER(n) UART_REG(n, 1)
+#define UART_IER_RDI BIT(0) /* received data */
+#define UART_IER_THRI BIT(1) /* THR empty */
+#define UART_IER_RLSI BIT(2) /* receiver LSR change */
+#define UART_IER_MSI BIT(3) /* MSR change */
 /* (Read) interrupt identification register */
-#define UART_IIR(n)			UART_REG(n, 2)
-#define   UART_IIR_ID_MASK		0x0e
-#define   UART_IIR_MSI			0x00 /* modem status change */
-#define   UART_IIR_NO_INT		0x01 /* no int pending */
-#define   UART_IIR_THRI			0x02 /* THR empty */
-#define   UART_IIR_RDI			0x04 /* received data available */
-#define   UART_IIR_RLSI			0x06 /* line status change */
+#define UART_IIR(n) UART_REG(n, 2)
+#define UART_IIR_ID_MASK 0x0e
+#define UART_IIR_MSI 0x00 /* modem status change */
+#define UART_IIR_NO_INT 0x01 /* no int pending */
+#define UART_IIR_THRI 0x02 /* THR empty */
+#define UART_IIR_RDI 0x04 /* received data available */
+#define UART_IIR_RLSI 0x06 /* line status change */
 /* (Write) FIFO control register */
-#define UART_FCR(n)			UART_REG(n, 2)
-#define   UART_FCR_ENABLE_FIFO		BIT(0) /* enable FIFO */
-#define   UART_FCR_CLEAR_RCVR		BIT(1) /* clear receive FIFO */
-#define   UART_FCR_CLEAR_XMIT		BIT(2) /* clear transmit FIFO */
-#define   UART_FCR_DMA_SELECT		BIT(3) /* select DMA mode */
+#define UART_FCR(n) UART_REG(n, 2)
+#define UART_FCR_ENABLE_FIFO BIT(0) /* enable FIFO */
+#define UART_FCR_CLEAR_RCVR BIT(1) /* clear receive FIFO */
+#define UART_FCR_CLEAR_XMIT BIT(2) /* clear transmit FIFO */
+#define UART_FCR_DMA_SELECT BIT(3) /* select DMA mode */
 /* (Write) line control register */
-#define UART_LCR(n)			UART_REG(n, 3)
-#define   UART_LCR_WLEN5		0 /* word length 5 bits */
-#define   UART_LCR_WLEN6		1
-#define   UART_LCR_WLEN7		2
-#define   UART_LCR_WLEN8		3
-#define   UART_LCR_STOP			BIT(2) /* stop bits: 1bit, 2bits */
-#define   UART_LCR_PARITY		BIT(3) /* parity enable */
-#define   UART_LCR_EPAR			BIT(4) /* even parity */
-#define   UART_LCR_SPAR			BIT(5) /* stick parity */
-#define   UART_LCR_SBC			BIT(6) /* set break control */
-#define   UART_LCR_DLAB			BIT(7) /* divisor latch access */
+#define UART_LCR(n) UART_REG(n, 3)
+#define UART_LCR_WLEN5 0 /* word length 5 bits */
+#define UART_LCR_WLEN6 1
+#define UART_LCR_WLEN7 2
+#define UART_LCR_WLEN8 3
+#define UART_LCR_STOP BIT(2) /* stop bits: 1bit, 2bits */
+#define UART_LCR_PARITY BIT(3) /* parity enable */
+#define UART_LCR_EPAR BIT(4) /* even parity */
+#define UART_LCR_SPAR BIT(5) /* stick parity */
+#define UART_LCR_SBC BIT(6) /* set break control */
+#define UART_LCR_DLAB BIT(7) /* divisor latch access */
 /* (Write) modem control register */
-#define UART_MCR(n)			UART_REG(n, 4)
+#define UART_MCR(n) UART_REG(n, 4)
 /* (Read) line status register */
-#define UART_LSR(n)			UART_REG(n, 5)
-#define   UART_LSR_DR			BIT(0) /* data ready */
-#define   UART_LSR_OE			BIT(1) /* overrun error */
-#define   UART_LSR_PE			BIT(2) /* parity error */
-#define   UART_LSR_FE			BIT(3) /* frame error */
-#define   UART_LSR_BI			BIT(4) /* break interrupt */
-#define   UART_LSR_THRE			BIT(5) /* THR empty */
-#define   UART_LSR_TEMT			BIT(6) /* THR empty, line idle */
-#define   UART_LSR_FIFOE		BIT(7) /* FIFO error */
+#define UART_LSR(n) UART_REG(n, 5)
+#define UART_LSR_DR BIT(0) /* data ready */
+#define UART_LSR_OE BIT(1) /* overrun error */
+#define UART_LSR_PE BIT(2) /* parity error */
+#define UART_LSR_FE BIT(3) /* frame error */
+#define UART_LSR_BI BIT(4) /* break interrupt */
+#define UART_LSR_THRE BIT(5) /* THR empty */
+#define UART_LSR_TEMT BIT(6) /* THR empty, line idle */
+#define UART_LSR_FIFOE BIT(7) /* FIFO error */
 /* (Read) modem status register */
-#define UART_MSR(n)			UART_REG(n, 6)
+#define UART_MSR(n) UART_REG(n, 6)
 /* (Read/Write) scratch register */
-#define UART_SCR(n)			UART_REG(n, 7)
+#define UART_SCR(n) UART_REG(n, 7)
 
 /* DLAB == 1 */
 
 /* (Write) divisor latch */
-#define UART_DLL(n)			UART_REG(n, 0)
-#define UART_DLH(n)			UART_REG(n, 1)
+#define UART_DLL(n) UART_REG(n, 0)
+#define UART_DLH(n) UART_REG(n, 1)
 
 /* MTK extension */
-#define UART_HIGHSPEED(n)		UART_REG(n, 9)
+#define UART_HIGHSPEED(n) UART_REG(n, 9)
 
 #endif /* __CROS_EC_UART_REGS_H */
diff --git a/chip/mt_scp/rv32i_common/video.h b/chip/mt_scp/rv32i_common/video.h
index e4538c4456..d5bb49ceac 100644
--- a/chip/mt_scp/rv32i_common/video.h
+++ b/chip/mt_scp/rv32i_common/video.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,7 +17,9 @@
 #define VDEC_CAP_H264_SLICE BIT(8)
 #define VDEC_CAP_VP8_FRAME BIT(9)
 #define VDEC_CAP_VP9_FRAME BIT(10)
+#define VDEC_CAP_AV1_FRAME BIT(11)
 #define VDEC_CAP_IRQ_IN_SCP BIT(16)
+#define VDEC_CAP_INNER_RACING BIT(17)
 
 /*
  * Video encoder supported capability:
diff --git a/chip/mt_scp/rv32i_common/watchdog.c b/chip/mt_scp/rv32i_common/watchdog.c
index f77a948da3..e8f5b5c3f9 100644
--- a/chip/mt_scp/rv32i_common/watchdog.c
+++ b/chip/mt_scp/rv32i_common/watchdog.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/npcx/adc.c b/chip/npcx/adc.c
index a31a0376dd..f01419bf67 100644
--- a/chip/npcx/adc.c
+++ b/chip/npcx/adc.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,11 +19,11 @@
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
 /* Maximum time we allow for an ADC conversion */
-#define ADC_TIMEOUT_US            SECOND
+#define ADC_TIMEOUT_US SECOND
 /*
  * ADC basic clock is from APB1.
  * In npcx5, APB1 clock frequency is (15 MHz / 4).
@@ -34,23 +34,23 @@
  * 7.5 MHz.
  */
 #if defined(CHIP_FAMILY_NPCX5)
-#define ADC_CLK                   2000000
-#define ADC_DLY                   0x03
-#define ADC_ADCCNF2               0x8B07
-#define ADC_GENDLY                0x0100
-#define ADC_MEAST                 0x0001
+#define ADC_CLK 2000000
+#define ADC_DLY 0x03
+#define ADC_ADCCNF2 0x8B07
+#define ADC_GENDLY 0x0100
+#define ADC_MEAST 0x0001
 #else
-#define ADC_CLK                   7500000
-#define ADC_DLY                   0x02
-#define ADC_ADCCNF2               0x8901
-#define ADC_GENDLY                0x0100
-#define ADC_MEAST                 0x0405
+#define ADC_CLK 7500000
+#define ADC_DLY 0x02
+#define ADC_ADCCNF2 0x8901
+#define ADC_GENDLY 0x0100
+#define ADC_MEAST 0x0405
 #endif
 
 /* ADC conversion mode */
 enum npcx_adc_conversion_mode {
-	ADC_CHN_CONVERSION_MODE   = 0,
-	ADC_SCAN_CONVERSION_MODE  = 1
+	ADC_CHN_CONVERSION_MODE = 0,
+	ADC_SCAN_CONVERSION_MODE = 1
 };
 
 /* Global variables */
@@ -69,7 +69,7 @@ static volatile bool adc_done;
  */
 void adc_freq_changed(void)
 {
-	uint8_t prescaler_divider    = 0;
+	uint8_t prescaler_divider = 0;
 
 	/* Set clock prescaler divider to ADC module*/
 	prescaler_divider = (uint8_t)(clock_get_apb1_freq() / ADC_CLK);
@@ -91,8 +91,8 @@ DECLARE_HOOK(HOOK_FREQ_CHANGE, adc_freq_changed, HOOK_PRIO_DEFAULT);
  * @return  TRUE/FALSE  success/fail
  * @notes   set SW-triggered interrupt conversion and one-shot mode in npcx chip
  */
-static int start_single_and_wait(enum npcx_adc_input_channel input_ch
-		, int timeout)
+static int start_single_and_wait(enum npcx_adc_input_channel input_ch,
+				 int timeout)
 {
 	int event;
 
@@ -107,7 +107,7 @@ static int start_single_and_wait(enum npcx_adc_input_channel input_ch
 
 	/* Set ADC conversion code to SW conversion mode */
 	SET_FIELD(NPCX_ADCCNF, NPCX_ADCCNF_ADCMD_FIELD,
-			ADC_CHN_CONVERSION_MODE);
+		  ADC_CHN_CONVERSION_MODE);
 
 	/* Set conversion type to one-shot type */
 	CLEAR_BIT(NPCX_ADCCNF, NPCX_ADCCNF_ADCRPTC);
@@ -124,13 +124,12 @@ static int start_single_and_wait(enum npcx_adc_input_channel input_ch
 	/* Start conversion */
 	SET_BIT(NPCX_ADCCNF, NPCX_ADCCNF_START);
 
-/*
- * If tasks have started, we can suspend to the task that called us.
- * If not, we need to busy poll for adc to finish before proceeding
- */
+	/*
+	 * If tasks have started, we can suspend to the task that called us.
+	 * If not, we need to busy poll for adc to finish before proceeding
+	 */
 	if (IS_ENABLED(CONFIG_KEYBOARD_SCAN_ADC)) {
 		if (!task_start_called()) {
-
 			/* Wait for the ADC interrupt to set the flag */
 			do {
 				usleep(10);
@@ -142,7 +141,7 @@ static int start_single_and_wait(enum npcx_adc_input_channel input_ch
 		} else {
 			/* Wait for interrupt */
 			event = task_wait_event_mask(TASK_EVENT_ADC_DONE,
-								timeout);
+						     timeout);
 
 			task_waiting = TASK_ID_INVALID;
 		}
@@ -213,8 +212,9 @@ int adc_read_data(enum npcx_adc_input_channel input_ch)
 	uint16_t chn_data;
 
 	chn_data = NPCX_CHNDAT(adc->input_ch);
-	value = GET_FIELD(chn_data, NPCX_CHNDAT_CHDAT_FIELD) *
-		 adc->factor_mul / adc->factor_div + adc->shift;
+	value = GET_FIELD(chn_data, NPCX_CHNDAT_CHDAT_FIELD) * adc->factor_mul /
+			adc->factor_div +
+		adc->shift;
 	return value;
 }
 
@@ -241,11 +241,11 @@ int adc_read_channel(enum adc_channel ch)
 	if (start_single_and_wait(adc->input_ch, ADC_TIMEOUT_US)) {
 		chn_data = NPCX_CHNDAT(adc->input_ch);
 		if ((adc->input_ch ==
-			GET_FIELD(NPCX_ASCADD, NPCX_ASCADD_SADDR_FIELD))
-			&& (IS_BIT_SET(chn_data,
-					NPCX_CHNDAT_NEW))) {
+		     GET_FIELD(NPCX_ASCADD, NPCX_ASCADD_SADDR_FIELD)) &&
+		    (IS_BIT_SET(chn_data, NPCX_CHNDAT_NEW))) {
 			value = GET_FIELD(chn_data, NPCX_CHNDAT_CHDAT_FIELD) *
-				adc->factor_mul / adc->factor_div + adc->shift;
+					adc->factor_mul / adc->factor_div +
+				adc->shift;
 		} else {
 			value = ADC_READ_ERROR;
 		}
@@ -261,7 +261,7 @@ int adc_read_channel(enum adc_channel ch)
 	} else {
 		/* Set ADC conversion code to SW conversion mode */
 		SET_FIELD(NPCX_ADCCNF, NPCX_ADCCNF_ADCMD_FIELD,
-		  ADC_SCAN_CONVERSION_MODE);
+			  ADC_SCAN_CONVERSION_MODE);
 		/* Set conversion type to repetitive (runs continuously) */
 		SET_BIT(NPCX_ADCCNF, NPCX_ADCCNF_ADCRPTC);
 		/* Start conversion */
@@ -283,8 +283,7 @@ void npcx_adc_thresh_int_enable(int threshold_idx, int enable)
 	enable = !!enable;
 
 	if ((threshold_idx < 1) || (threshold_idx > NPCX_ADC_THRESH_CNT)) {
-		CPRINTS("Invalid ADC thresh index! (%d)",
-			threshold_idx);
+		CPRINTS("Invalid ADC thresh index! (%d)", threshold_idx);
 		return;
 	}
 	threshold_idx--; /* convert to 0-based */
@@ -313,24 +312,21 @@ void npcx_adc_register_thresh_irq(int threshold_idx,
 	int shift;
 
 	if ((threshold_idx < 1) || (threshold_idx > NPCX_ADC_THRESH_CNT)) {
-		CPRINTS("Invalid ADC thresh index! (%d)",
-			threshold_idx);
+		CPRINTS("Invalid ADC thresh index! (%d)", threshold_idx);
 		return;
 	}
 	npcx_adc_ch = adc_channels[thresh_cfg->adc_ch].input_ch;
 
 	if (!thresh_cfg->adc_thresh_cb) {
-		CPRINTS("No callback for ADC Threshold %d!",
-			threshold_idx);
+		CPRINTS("No callback for ADC Threshold %d!", threshold_idx);
 		return;
 	}
 
 	/* Fill in the table */
-	adc_thresh_irqs[threshold_idx-1] = thresh_cfg->adc_thresh_cb;
+	adc_thresh_irqs[threshold_idx - 1] = thresh_cfg->adc_thresh_cb;
 
 	/* Select the channel */
-	SET_FIELD(NPCX_THRCTL(threshold_idx), NPCX_THRCTL_CHNSEL,
-		  npcx_adc_ch);
+	SET_FIELD(NPCX_THRCTL(threshold_idx), NPCX_THRCTL_CHNSEL, npcx_adc_ch);
 
 	if (thresh_cfg->lower_or_higher)
 		SET_BIT(NPCX_THRCTL(threshold_idx), NPCX_THRCTL_L_H);
@@ -345,8 +341,7 @@ void npcx_adc_register_thresh_irq(int threshold_idx,
 	raw_val = (thresh_cfg->thresh_assert - shift) * div / mul;
 	CPRINTS("ADC THR%d: Setting THRVAL = %d, L_H: %d", threshold_idx,
 		raw_val, thresh_cfg->lower_or_higher);
-	SET_FIELD(NPCX_THRCTL(threshold_idx), NPCX_THRCTL_THRVAL,
-		  raw_val);
+	SET_FIELD(NPCX_THRCTL(threshold_idx), NPCX_THRCTL_THRVAL, raw_val);
 
 #if NPCX_FAMILY_VERSION <= NPCX_FAMILY_NPCX7
 	/* Disable deassertion threshold function */
@@ -396,7 +391,7 @@ static void adc_interrupt(void)
 		    IS_BIT_SET(NPCX_THRCTS, i)) {
 			/* avoid clearing other threshold status */
 			thrcts = NPCX_THRCTS &
-					~GENMASK(NPCX_ADC_THRESH_CNT - 1, 0);
+				 ~GENMASK(NPCX_ADC_THRESH_CNT - 1, 0);
 			/* Clear threshold status */
 			SET_BIT(thrcts, i);
 			NPCX_THRCTS = thrcts;
@@ -430,7 +425,7 @@ void adc_init(void)
 
 	/* Enable ADC clock (bit4 mask = 0x10) */
 	clock_enable_peripheral(CGC_OFFSET_ADC, CGC_ADC_MASK,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
+				CGC_MODE_RUN | CGC_MODE_SLEEP);
 
 	/* Set Core Clock Division Factor in order to obtain the ADC clock */
 	adc_freq_changed();
diff --git a/chip/npcx/adc_chip.h b/chip/npcx/adc_chip.h
index 300447df16..5f3862829a 100644
--- a/chip/npcx/adc_chip.h
+++ b/chip/npcx/adc_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -32,7 +32,7 @@ enum npcx_adc_input_channel {
 #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
 	NPCX_ADC_CH10,
 	NPCX_ADC_CH11,
- #endif
+#endif
 	NPCX_ADC_CH_COUNT
 };
 
diff --git a/chip/npcx/apm.c b/chip/npcx/apm.c
index 4ab64774c1..b66a77a276 100644
--- a/chip/npcx/apm.c
+++ b/chip/npcx/apm.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,13 +12,12 @@
 #include "wov_chip.h"
 
 static struct apm_config apm_conf;
-static struct apm_auto_gain_config	apm_gain_conf;
-
+static struct apm_auto_gain_config apm_gain_conf;
 
 static uint32_t apm_indirect_reg[][3] = {
-	{(NPCX_APM_BASE_ADDR + 0x034), (NPCX_APM_BASE_ADDR + 0x038)},
-	{(NPCX_APM_BASE_ADDR + 0x04C), (NPCX_APM_BASE_ADDR + 0x050)},
-	{(NPCX_APM_BASE_ADDR + 0x05C), (NPCX_APM_BASE_ADDR + 0x060)}
+	{ (NPCX_APM_BASE_ADDR + 0x034), (NPCX_APM_BASE_ADDR + 0x038) },
+	{ (NPCX_APM_BASE_ADDR + 0x04C), (NPCX_APM_BASE_ADDR + 0x050) },
+	{ (NPCX_APM_BASE_ADDR + 0x05C), (NPCX_APM_BASE_ADDR + 0x060) }
 };
 
 #define APM_CNTRL_REG 0
@@ -37,11 +36,11 @@ static uint8_t apm_read_indirect_data(enum apm_indirect_reg_offset reg_offset,
 {
 	/* Set the indirect access address. */
 	SET_FIELD(REG8(apm_indirect_reg[reg_offset][APM_CNTRL_REG]),
-			NPCX_APM_CONTROL_ADD, indirect_addr);
+		  NPCX_APM_CONTROL_ADD, indirect_addr);
 
 	/* Read command. */
 	CLEAR_BIT(REG8(apm_indirect_reg[reg_offset][APM_CNTRL_REG]),
-			NPCX_APM_CONTROL_LOAD);
+		  NPCX_APM_CONTROL_LOAD);
 
 	/* Get the data. */
 	return REG8(apm_indirect_reg[reg_offset][APM_DATA_REG]);
@@ -57,20 +56,20 @@ static uint8_t apm_read_indirect_data(enum apm_indirect_reg_offset reg_offset,
  * @return  None
  */
 static void apm_write_indirect_data(enum apm_indirect_reg_offset reg_offset,
-				uint8_t indirect_addr, uint8_t value)
+				    uint8_t indirect_addr, uint8_t value)
 {
 	/* Set the data. */
 	REG8(apm_indirect_reg[reg_offset][APM_DATA_REG]) = value;
 
 	/* Set the indirect access address. */
 	SET_FIELD(REG8(apm_indirect_reg[reg_offset][APM_CNTRL_REG]),
-			NPCX_APM_CONTROL_ADD, indirect_addr);
+		  NPCX_APM_CONTROL_ADD, indirect_addr);
 
 	/* Write command. */
 	SET_BIT(REG8(apm_indirect_reg[reg_offset][APM_CNTRL_REG]),
-			NPCX_APM_CONTROL_LOAD);
+		NPCX_APM_CONTROL_LOAD);
 	CLEAR_BIT(REG8(apm_indirect_reg[reg_offset][APM_CNTRL_REG]),
-			NPCX_APM_CONTROL_LOAD);
+		  NPCX_APM_CONTROL_LOAD);
 }
 
 /**
@@ -83,13 +82,13 @@ void apm_set_adc_dmic_config_l(enum apm_dmic_rate rate)
 {
 	if (rate == APM_DMIC_RATE_0_75)
 		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_RATE,
-			APM_DMIC_RATE_3_0);
+			  APM_DMIC_RATE_3_0);
 	else if (rate == APM_DMIC_RATE_1_2)
 		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_RATE,
-			APM_DMIC_RATE_2_4);
+			  APM_DMIC_RATE_2_4);
 	else
 		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_RATE,
-			rate);
+			  rate);
 }
 
 /**
@@ -108,7 +107,7 @@ void apm_set_vad_dmic_rate_l(enum apm_dmic_rate rate)
 	/* Set VAD_0 register. */
 	if (rate == APM_DMIC_RATE_0_75)
 		SET_FIELD(vad_data, NPCX_VAD_0_VAD_DMIC_FREQ,
-				APM_DMIC_RATE_3_0);
+			  APM_DMIC_RATE_3_0);
 	else if (rate == APM_DMIC_RATE_1_2)
 		SET_FIELD(vad_data, NPCX_VAD_0_VAD_DMIC_FREQ,
 			  APM_DMIC_RATE_2_4);
@@ -172,15 +171,15 @@ void apm_init(void)
 	apm_conf.left_chan_gain = 0;
 	apm_conf.right_chan_gain = 0;
 
-	apm_gain_conf.stereo_enable	 = 0;
-	apm_gain_conf.agc_target	 = APM_ADC_MAX_TARGET_LEVEL_19_5;
-	apm_gain_conf.nois_gate_en	 = 0;
+	apm_gain_conf.stereo_enable = 0;
+	apm_gain_conf.agc_target = APM_ADC_MAX_TARGET_LEVEL_19_5;
+	apm_gain_conf.nois_gate_en = 0;
 	apm_gain_conf.nois_gate_thold = APM_MIN_NOISE_GET_THRESHOLD;
-	apm_gain_conf.hold_time	 = APM_HOLD_TIME_128;
-	apm_gain_conf.attack_time	 = APM_GAIN_RAMP_TIME_160;
-	apm_gain_conf.decay_time	 = APM_GAIN_RAMP_TIME_160;
-	apm_gain_conf.gain_max	 = APM_GAIN_VALUE_42_5;
-	apm_gain_conf.gain_min	 = APM_GAIN_VALUE_0_0;
+	apm_gain_conf.hold_time = APM_HOLD_TIME_128;
+	apm_gain_conf.attack_time = APM_GAIN_RAMP_TIME_160;
+	apm_gain_conf.decay_time = APM_GAIN_RAMP_TIME_160;
+	apm_gain_conf.gain_max = APM_GAIN_VALUE_42_5;
+	apm_gain_conf.gain_min = APM_GAIN_VALUE_0_0;
 }
 
 /**
@@ -226,11 +225,11 @@ void apm_enable_vad_interrupt(int enable)
 void apm_adc_wov_enable(int enable)
 {
 	if (enable) {
-		SET_FIELD(NPCX_APM_AICR_ADC,
-				NPCX_APM_AICR_ADC_ADC_AUDIOIF, 0x00);
+		SET_FIELD(NPCX_APM_AICR_ADC, NPCX_APM_AICR_ADC_ADC_AUDIOIF,
+			  0x00);
 	} else {
-		SET_FIELD(NPCX_APM_AICR_ADC,
-				NPCX_APM_AICR_ADC_ADC_AUDIOIF, 0x03);
+		SET_FIELD(NPCX_APM_AICR_ADC, NPCX_APM_AICR_ADC_ADC_AUDIOIF,
+			  0x03);
 	}
 }
 
@@ -244,12 +243,12 @@ void apm_adc_enable(int enable)
 {
 	if (enable) {
 		CLEAR_BIT(NPCX_APM_AICR_ADC, NPCX_APM_AICR_ADC_PD_AICR_ADC);
-		SET_FIELD(NPCX_APM_AICR_ADC,
-				NPCX_APM_AICR_ADC_ADC_AUDIOIF, 0x00);
+		SET_FIELD(NPCX_APM_AICR_ADC, NPCX_APM_AICR_ADC_ADC_AUDIOIF,
+			  0x00);
 	} else {
 		SET_BIT(NPCX_APM_AICR_ADC, NPCX_APM_AICR_ADC_PD_AICR_ADC);
-		SET_FIELD(NPCX_APM_AICR_ADC,
-				NPCX_APM_AICR_ADC_ADC_AUDIOIF, 0x03);
+		SET_FIELD(NPCX_APM_AICR_ADC, NPCX_APM_AICR_ADC_ADC_AUDIOIF,
+			  0x03);
 	}
 }
 
@@ -273,8 +272,8 @@ void apm_adc_set_freq(enum apm_adc_frequency adc_freq)
  * @return  None
  */
 void apm_adc_config(int hpf_enable,
-		enum apm_adc_wind_noise_filter_mode filter_mode,
-		enum apm_adc_frequency adc_freq)
+		    enum apm_adc_wind_noise_filter_mode filter_mode,
+		    enum apm_adc_frequency adc_freq)
 {
 	if (hpf_enable)
 		SET_BIT(NPCX_APM_FCR_ADC, NPCX_APM_FCR_ADC_ADC_HPF);
@@ -491,7 +490,8 @@ void apm_vad_restart(void)
  * @return  EC_ERROR_INVAL or EC_SUCCESS
  */
 enum ec_error_list apm_adc_gain_config(enum apm_adc_gain_coupling gain_coupling,
-		uint8_t left_chan_gain, uint8_t right_chan_gain)
+				       uint8_t left_chan_gain,
+				       uint8_t right_chan_gain)
 {
 	/* Check parameters validity. */
 	if ((left_chan_gain > 0x2B) || (right_chan_gain > 0x2B))
@@ -538,8 +538,8 @@ void apm_auto_gain_cntrl_enable(int enable)
  * @param   gain_cfg - struct of apm auto gain config
  * @return  EC_ERROR_INVAL or EC_SUCCESS
  */
-enum ec_error_list apm_adc_auto_gain_config(
-				struct apm_auto_gain_config *gain_cfg)
+enum ec_error_list
+apm_adc_auto_gain_config(struct apm_auto_gain_config *gain_cfg)
 {
 	uint8_t gain_data = 0;
 
@@ -668,9 +668,8 @@ void apm_set_mode(enum wov_modes wov_mode)
 		break;
 	}
 
-	apm_adc_gain_config(apm_conf.gain_coupling,
-				apm_conf.left_chan_gain,
-				apm_conf.right_chan_gain);
+	apm_adc_gain_config(apm_conf.gain_coupling, apm_conf.left_chan_gain,
+			    apm_conf.right_chan_gain);
 
 	apm_adc_auto_gain_config(&apm_gain_conf);
 
diff --git a/chip/npcx/apm_chip.h b/chip/npcx/apm_chip.h
index ad62538374..9b330321ea 100644
--- a/chip/npcx/apm_chip.h
+++ b/chip/npcx/apm_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,31 +9,27 @@
 #include "common.h"
 
 /* MIX indirect registers. */
-#define APM_INDIRECT_MIX_2_REG      0x02
+#define APM_INDIRECT_MIX_2_REG 0x02
 
 /* ADC_AGC indirect registers. */
-#define APM_INDIRECT_ADC_AGC_0_REG  0x00
-#define APM_INDIRECT_ADC_AGC_1_REG  0x01
-#define APM_INDIRECT_ADC_AGC_2_REG  0x02
-#define APM_INDIRECT_ADC_AGC_3_REG  0x03
-#define APM_INDIRECT_ADC_AGC_4_REG  0x04
+#define APM_INDIRECT_ADC_AGC_0_REG 0x00
+#define APM_INDIRECT_ADC_AGC_1_REG 0x01
+#define APM_INDIRECT_ADC_AGC_2_REG 0x02
+#define APM_INDIRECT_ADC_AGC_3_REG 0x03
+#define APM_INDIRECT_ADC_AGC_4_REG 0x04
 
 /* APM_VAD_REG indirect registers. */
-#define APM_INDIRECT_VAD_0_REG       0x00
-#define APM_INDIRECT_VAD_1_REG       0x01
+#define APM_INDIRECT_VAD_0_REG 0x00
+#define APM_INDIRECT_VAD_1_REG 0x01
 
 /* APM macros. */
-#define APM_IS_IRQ_PENDING    IS_BIT_SET(NPCX_APM_SR, NPCX_APM_SR_IRQ_PEND)
+#define APM_IS_IRQ_PENDING IS_BIT_SET(NPCX_APM_SR, NPCX_APM_SR_IRQ_PEND)
 #define APM_IS_VOICE_ACTIVITY_DETECTED \
 	IS_BIT_SET(NPCX_APM_IFR, NPCX_APM_IFR_VAD_DTC)
-#define APM_CLEAR_VAD_INTERRUPT    SET_BIT(NPCX_APM_IFR, NPCX_APM_IFR_VAD_DTC)
+#define APM_CLEAR_VAD_INTERRUPT SET_BIT(NPCX_APM_IFR, NPCX_APM_IFR_VAD_DTC)
 
 /* Indirect registers. */
-enum apm_indirect_reg_offset {
-	APM_MIX_REG = 0,
-	APM_ADC_AGC_REG,
-	APM_VAD_REG
-};
+enum apm_indirect_reg_offset { APM_MIX_REG = 0, APM_ADC_AGC_REG, APM_VAD_REG };
 
 /* ADC wind noise filter modes. */
 enum apm_adc_wind_noise_filter_mode {
@@ -60,22 +56,22 @@ enum apm_adc_frequency {
 /* DMIC source. */
 enum apm_dmic_src {
 	APM_CURRENT_DMIC_CHANNEL = 0x01, /* Current channel, left or rigth. */
-	APM_AVERAGE_DMIC_CHANNEL = 0x02  /* Average between left & right.   */
+	APM_AVERAGE_DMIC_CHANNEL = 0x02 /* Average between left & right.   */
 };
 
 /* ADC digital microphone rate. */
 enum apm_dmic_rate {
 	/* 3.0, 2.4 & 1.0 must be 0, 1 & 2 respectively */
-	APM_DMIC_RATE_3_0 = 0,   /* 3.0 -3.25 MHz (default). */
-	APM_DMIC_RATE_2_4,       /* 2.4 -2.6 MHz.            */
-	APM_DMIC_RATE_1_0,       /* 1.0 -1.08 MHz.           */
-	APM_DMIC_RATE_1_2,       /* 1.2 MHz.                        */
-	APM_DMIC_RATE_0_75       /* 750 KHz.                 */
+	APM_DMIC_RATE_3_0 = 0, /* 3.0 -3.25 MHz (default). */
+	APM_DMIC_RATE_2_4, /* 2.4 -2.6 MHz.            */
+	APM_DMIC_RATE_1_0, /* 1.0 -1.08 MHz.           */
+	APM_DMIC_RATE_1_2, /* 1.2 MHz.                        */
+	APM_DMIC_RATE_0_75 /* 750 KHz.                 */
 };
 
 /* Digitla mixer output. */
 enum apm_dig_mix {
-	APM_OUT_MIX_NORMAL_INPUT = 0,    /* Default. */
+	APM_OUT_MIX_NORMAL_INPUT = 0, /* Default. */
 	APM_OUT_MIX_CROSS_INPUT,
 	APM_OUT_MIX_MIXED_INPUT,
 	APM_OUT_MIX_NO_INPUT
@@ -341,8 +337,8 @@ void apm_adc_set_freq(enum apm_adc_frequency adc_freq);
  * @return  None
  */
 void apm_adc_config(int hpf_enable,
-		enum apm_adc_wind_noise_filter_mode filter_mode,
-		enum apm_adc_frequency adc_freq);
+		    enum apm_adc_wind_noise_filter_mode filter_mode,
+		    enum apm_adc_frequency adc_freq);
 
 /**
  * Enables/Disables Digital Microphone.
@@ -360,7 +356,7 @@ void apm_dmic_enable(int enable);
  * @return  None
  */
 void apm_digital_mixer_config(enum apm_dig_mix mix_left,
-		enum apm_dig_mix mix_right);
+			      enum apm_dig_mix mix_right);
 
 /**
  * Enables/Disables the VAD functionality.
@@ -422,7 +418,8 @@ void apm_vad_restart(void);
  * @return  EC_ERROR_INVAL or EC_SUCCESS
  */
 enum ec_error_list apm_adc_gain_config(enum apm_adc_gain_coupling gain_coupling,
-			uint8_t left_chan_gain, uint8_t right_chan_gain);
+				       uint8_t left_chan_gain,
+				       uint8_t right_chan_gain);
 
 /**
  * Enables/Disables the automatic gain.
@@ -438,8 +435,8 @@ void apm_auto_gain_cntrl_enable(int enable);
  * @param   gain_cfg - struct of apm auto gain config
  * @return  EC_ERROR_INVAL or EC_SUCCESS
  */
-enum ec_error_list apm_adc_auto_gain_config(
-				struct apm_auto_gain_config *gain_cfg);
+enum ec_error_list
+apm_adc_auto_gain_config(struct apm_auto_gain_config *gain_cfg);
 
 /**
  * Sets APM mode (enables & disables APN sub modules accordingly
diff --git a/chip/npcx/audio_codec_dmic.c b/chip/npcx/audio_codec_dmic.c
index e242a8b2d2..7e1bfa9bce 100644
--- a/chip/npcx/audio_codec_dmic.c
+++ b/chip/npcx/audio_codec_dmic.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/npcx/audio_codec_i2s_rx.c b/chip/npcx/audio_codec_i2s_rx.c
index 12c4173048..02224be437 100644
--- a/chip/npcx/audio_codec_i2s_rx.c
+++ b/chip/npcx/audio_codec_i2s_rx.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,7 +8,7 @@
 #include "ec_commands.h"
 #include "wov_chip.h"
 
-#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ##args)
 
 int audio_codec_i2s_rx_enable(void)
 {
diff --git a/chip/npcx/build.mk b/chip/npcx/build.mk
index d7e61de4de..9e046be7ec 100644
--- a/chip/npcx/build.mk
+++ b/chip/npcx/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
+# Copyright 2014 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/chip/npcx/cec.c b/chip/npcx/cec.c
index eb1cfefa0f..39f353b0e3 100644
--- a/chip/npcx/cec.c
+++ b/chip/npcx/cec.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,21 +22,21 @@
 #define CPRINTF(...)
 #define CPRINTS(...)
 #else
-#define CPRINTF(format, args...) cprintf(CC_CEC, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CEC, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CEC, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CEC, format, ##args)
 #endif
 
 /* Time in us to timer clock ticks */
-#define APB1_TICKS(t) ((t) * apb1_freq_div_10k / 100)
+#define APB1_TICKS(t) ((t)*apb1_freq_div_10k / 100)
 #if DEBUG_CEC
 /* Timer clock ticks to us */
-#define APB1_US(ticks) (100*(ticks)/apb1_freq_div_10k)
+#define APB1_US(ticks) (100 * (ticks) / apb1_freq_div_10k)
 #endif
 
 /* Notification from interrupt to CEC task that data has been received */
 #define TASK_EVENT_RECEIVED_DATA TASK_EVENT_CUSTOM_BIT(0)
-#define TASK_EVENT_OKAY          TASK_EVENT_CUSTOM_BIT(1)
-#define TASK_EVENT_FAILED        TASK_EVENT_CUSTOM_BIT(2)
+#define TASK_EVENT_OKAY TASK_EVENT_CUSTOM_BIT(1)
+#define TASK_EVENT_FAILED TASK_EVENT_CUSTOM_BIT(2)
 
 /* CEC broadcast address. Also the highest possible CEC address */
 #define CEC_BROADCAST_ADDR 15
@@ -56,7 +56,7 @@
  * free-time period less than in the spec.
  */
 #define NOMINAL_BIT_TICKS APB1_TICKS(2400)
- /* Resend */
+/* Resend */
 #define FREE_TIME_RS_TICKS (2 * (NOMINAL_BIT_TICKS))
 /* New initiator */
 #define FREE_TIME_NI_TICKS (4 * (NOMINAL_BIT_TICKS))
@@ -64,33 +64,33 @@
 #define FREE_TIME_PI_TICKS (6 * (NOMINAL_BIT_TICKS))
 
 /* Start bit timing */
-#define START_BIT_LOW_TICKS		APB1_TICKS(3700)
-#define START_BIT_MIN_LOW_TICKS		APB1_TICKS(3500)
-#define START_BIT_MAX_LOW_TICKS		APB1_TICKS(3900)
-#define START_BIT_HIGH_TICKS		APB1_TICKS(800)
-#define START_BIT_MIN_DURATION_TICKS	APB1_TICKS(4300)
-#define START_BIT_MAX_DURATION_TICKS	APB1_TICKS(5700)
+#define START_BIT_LOW_TICKS APB1_TICKS(3700)
+#define START_BIT_MIN_LOW_TICKS APB1_TICKS(3500)
+#define START_BIT_MAX_LOW_TICKS APB1_TICKS(3900)
+#define START_BIT_HIGH_TICKS APB1_TICKS(800)
+#define START_BIT_MIN_DURATION_TICKS APB1_TICKS(4300)
+#define START_BIT_MAX_DURATION_TICKS APB1_TICKS(5700)
 
 /* Data bit timing */
-#define DATA_ZERO_LOW_TICKS		APB1_TICKS(1500)
-#define DATA_ZERO_MIN_LOW_TICKS		APB1_TICKS(1300)
-#define DATA_ZERO_MAX_LOW_TICKS		APB1_TICKS(1700)
-#define DATA_ZERO_HIGH_TICKS		APB1_TICKS(900)
-#define DATA_ZERO_MIN_DURATION_TICKS	APB1_TICKS(2050)
-#define DATA_ZERO_MAX_DURATION_TICKS	APB1_TICKS(2750)
-
-#define DATA_ONE_LOW_TICKS		APB1_TICKS(600)
-#define DATA_ONE_MIN_LOW_TICKS		APB1_TICKS(400)
-#define DATA_ONE_MAX_LOW_TICKS		APB1_TICKS(800)
-#define DATA_ONE_HIGH_TICKS		APB1_TICKS(1800)
-#define DATA_ONE_MIN_DURATION_TICKS	APB1_TICKS(2050)
-#define DATA_ONE_MAX_DURATION_TICKS	APB1_TICKS(2750)
+#define DATA_ZERO_LOW_TICKS APB1_TICKS(1500)
+#define DATA_ZERO_MIN_LOW_TICKS APB1_TICKS(1300)
+#define DATA_ZERO_MAX_LOW_TICKS APB1_TICKS(1700)
+#define DATA_ZERO_HIGH_TICKS APB1_TICKS(900)
+#define DATA_ZERO_MIN_DURATION_TICKS APB1_TICKS(2050)
+#define DATA_ZERO_MAX_DURATION_TICKS APB1_TICKS(2750)
+
+#define DATA_ONE_LOW_TICKS APB1_TICKS(600)
+#define DATA_ONE_MIN_LOW_TICKS APB1_TICKS(400)
+#define DATA_ONE_MAX_LOW_TICKS APB1_TICKS(800)
+#define DATA_ONE_HIGH_TICKS APB1_TICKS(1800)
+#define DATA_ONE_MIN_DURATION_TICKS APB1_TICKS(2050)
+#define DATA_ONE_MAX_DURATION_TICKS APB1_TICKS(2750)
 
 /* Time from low that it should be safe to sample an ACK */
 #define NOMINAL_SAMPLE_TIME_TICKS APB1_TICKS(1050)
 
-#define DATA_TIME(type, data) ((data) ? (DATA_ONE_ ## type ## _TICKS) : \
-					(DATA_ZERO_ ## type ## _TICKS))
+#define DATA_TIME(type, data) \
+	((data) ? (DATA_ONE_##type##_TICKS) : (DATA_ZERO_##type##_TICKS))
 #define DATA_HIGH(data) DATA_TIME(HIGH, data)
 #define DATA_LOW(data) DATA_TIME(LOW, data)
 
@@ -119,26 +119,26 @@
  * sure that if we get a timeout, something is wrong.
  */
 #define CAP_START_LOW_TICKS (START_BIT_MAX_LOW_TICKS + VALID_TOLERANCE_TICKS)
-#define CAP_START_HIGH_TICKS (START_BIT_MAX_DURATION_TICKS - \
-			      START_BIT_MIN_LOW_TICKS +	\
-			      VALID_TOLERANCE_TICKS)
+#define CAP_START_HIGH_TICKS                                      \
+	(START_BIT_MAX_DURATION_TICKS - START_BIT_MIN_LOW_TICKS + \
+	 VALID_TOLERANCE_TICKS)
 #define CAP_DATA_LOW_TICKS (DATA_ZERO_MAX_LOW_TICKS + VALID_TOLERANCE_TICKS)
-#define CAP_DATA_HIGH_TICKS (DATA_ONE_MAX_DURATION_TICKS - \
-			     DATA_ONE_MIN_LOW_TICKS + \
-			     VALID_TOLERANCE_TICKS)
+#define CAP_DATA_HIGH_TICKS                                     \
+	(DATA_ONE_MAX_DURATION_TICKS - DATA_ONE_MIN_LOW_TICKS + \
+	 VALID_TOLERANCE_TICKS)
 
-#define VALID_TIME(type, bit, t) \
-	((t) >= ((bit ## _MIN_ ## type ## _TICKS) - (VALID_TOLERANCE_TICKS)) \
-	 && (t) <=  (bit ##_MAX_ ## type ## _TICKS) + (VALID_TOLERANCE_TICKS))
+#define VALID_TIME(type, bit, t)                                          \
+	((t) >= ((bit##_MIN_##type##_TICKS) - (VALID_TOLERANCE_TICKS)) && \
+	 (t) <= (bit##_MAX_##type##_TICKS) + (VALID_TOLERANCE_TICKS))
 #define VALID_LOW(bit, t) VALID_TIME(LOW, bit, t)
-#define VALID_HIGH(bit, low_time, high_time) \
-	(((low_time) + (high_time) <= \
-	  bit ## _MAX_DURATION_TICKS + VALID_TOLERANCE_TICKS) && \
-	 ((low_time) + (high_time) >= \
-	  bit ## _MIN_DURATION_TICKS - VALID_TOLERANCE_TICKS))
-#define VALID_DATA_HIGH(data, low_time, high_time) ((data) ? \
-				VALID_HIGH(DATA_ONE, low_time, high_time) : \
-				VALID_HIGH(DATA_ZERO, low_time, high_time))
+#define VALID_HIGH(bit, low_time, high_time)                   \
+	(((low_time) + (high_time) <=                          \
+	  bit##_MAX_DURATION_TICKS + VALID_TOLERANCE_TICKS) && \
+	 ((low_time) + (high_time) >=                          \
+	  bit##_MIN_DURATION_TICKS - VALID_TOLERANCE_TICKS))
+#define VALID_DATA_HIGH(data, low_time, high_time)            \
+	((data) ? VALID_HIGH(DATA_ONE, low_time, high_time) : \
+		  VALID_HIGH(DATA_ZERO, low_time, high_time))
 
 /*
  * CEC state machine states. Each state typically takes action on entry and
@@ -179,10 +179,7 @@ enum cec_state {
 };
 
 /* Edge to trigger capture timer interrupt on */
-enum cap_edge {
-	CAP_EDGE_FALLING,
-	CAP_EDGE_RISING
-};
+enum cap_edge { CAP_EDGE_FALLING, CAP_EDGE_RISING };
 
 /* Receive buffer and states */
 struct cec_rx {
@@ -408,13 +405,13 @@ void enter_state(enum cec_state new_state)
 		break;
 	case CEC_STATE_INITIATOR_EOM_LOW:
 		gpio = 0;
-		timeout = DATA_LOW(cec_transfer_is_eom(&cec_tx.transfer,
-						       cec_tx.len));
+		timeout = DATA_LOW(
+			cec_transfer_is_eom(&cec_tx.transfer, cec_tx.len));
 		break;
 	case CEC_STATE_INITIATOR_EOM_HIGH:
 		gpio = 1;
-		timeout = DATA_HIGH(cec_transfer_is_eom(&cec_tx.transfer,
-							cec_tx.len));
+		timeout = DATA_HIGH(
+			cec_transfer_is_eom(&cec_tx.transfer, cec_tx.len));
 		break;
 	case CEC_STATE_INITIATOR_ACK_LOW:
 		gpio = 0;
@@ -423,8 +420,8 @@ void enter_state(enum cec_state new_state)
 	case CEC_STATE_INITIATOR_ACK_HIGH:
 		gpio = 1;
 		/* Aim for the middle of the safe sample time */
-		timeout = (DATA_ONE_LOW_TICKS + DATA_ZERO_LOW_TICKS)/2 -
-							DATA_ONE_LOW_TICKS;
+		timeout = (DATA_ONE_LOW_TICKS + DATA_ZERO_LOW_TICKS) / 2 -
+			  DATA_ONE_LOW_TICKS;
 		break;
 	case CEC_STATE_INITIATOR_ACK_VERIFY:
 		cec_tx.ack = !gpio_get_level(CEC_GPIO_OUT);
@@ -523,7 +520,8 @@ void enter_state(enum cec_state new_state)
 		cap_edge = CAP_EDGE_FALLING;
 		timeout = CAP_DATA_HIGH_TICKS;
 		break;
-	/* No default case, since all states must be handled explicitly */
+		/* No default case, since all states must be handled explicitly
+		 */
 	}
 
 	if (gpio >= 0)
@@ -594,8 +592,7 @@ static void cec_event_timeout(void)
 				cec_tx.len = 0;
 				cec_tx.resends = 0;
 				enter_state(CEC_STATE_IDLE);
-				task_set_event(TASK_ID_CEC,
-					       TASK_EVENT_OKAY);
+				task_set_event(TASK_ID_CEC, TASK_EVENT_OKAY);
 			}
 		} else {
 			if (cec_tx.resends < CEC_MAX_RESENDS) {
@@ -607,8 +604,7 @@ static void cec_event_timeout(void)
 				cec_tx.len = 0;
 				cec_tx.resends = 0;
 				enter_state(CEC_STATE_IDLE);
-				task_set_event(TASK_ID_CEC,
-					       TASK_EVENT_FAILED);
+				task_set_event(TASK_ID_CEC, TASK_EVENT_FAILED);
 			}
 		}
 		break;
@@ -645,7 +641,6 @@ static void cec_event_timeout(void)
 	case CEC_STATE_FOLLOWER_DATA_HIGH:
 		enter_state(CEC_STATE_IDLE);
 		break;
-
 	}
 }
 
@@ -672,7 +667,7 @@ static void cec_event_cap(void)
 		break;
 	case CEC_STATE_FOLLOWER_START_LOW:
 		/* Rising edge of start bit, validate low time */
-		t =  tmr_cap_get();
+		t = tmr_cap_get();
 		if (VALID_LOW(START_BIT, t)) {
 			cec_rx.low_ticks = t;
 			enter_state(CEC_STATE_FOLLOWER_START_HIGH);
@@ -942,7 +937,6 @@ static enum ec_status hc_cec_set(struct host_cmd_handler_args *args)
 }
 DECLARE_HOST_COMMAND(EC_CMD_CEC_SET, hc_cec_set, EC_VER_MASK(0));
 
-
 static enum ec_status hc_cec_get(struct host_cmd_handler_args *args)
 {
 	struct ec_response_cec_get *response = args->response;
@@ -990,13 +984,12 @@ static int cec_get_next_msg(uint8_t *out)
 }
 DECLARE_EVENT_SOURCE(EC_MKBP_EVENT_CEC_MESSAGE, cec_get_next_msg);
 
-
 static void cec_init(void)
 {
 	int mdl = NPCX_MFT_MODULE_1;
 
 	/* APB1 is the clock we base the timers on */
-	apb1_freq_div_10k = clock_get_apb1_freq()/10000;
+	apb1_freq_div_10k = clock_get_apb1_freq() / 10000;
 
 	/* Ensure Multi-Function timer is powered up. */
 	CLEAR_BIT(NPCX_PWDWN_CTL(mdl), NPCX_PWDWN_CTL1_MFT1_PD);
diff --git a/chip/npcx/clock.c b/chip/npcx/clock.c
index 4656e83a52..1ab4d1063a 100644
--- a/chip/npcx/clock.c
+++ b/chip/npcx/clock.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,10 +26,10 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args)
 
-#define WAKE_INTERVAL   61        /* Unit: 61 usec */
-#define IDLE_PARAMS     0x7       /* Support deep idle, instant wake-up */
+#define WAKE_INTERVAL 61 /* Unit: 61 usec */
+#define IDLE_PARAMS 0x7 /* Support deep idle, instant wake-up */
 
 /* Low power idle statistics */
 #ifdef CONFIG_LOW_POWER_IDLE
@@ -40,7 +40,7 @@ static uint64_t idle_dsleep_time_us;
  * Fixed amount of time to keep the console in use flag true after boot in
  * order to give a permanent window in which the low speed clock is not used.
  */
-#define CONSOLE_IN_USE_ON_BOOT_TIME (15*SECOND)
+#define CONSOLE_IN_USE_ON_BOOT_TIME (15 * SECOND)
 static int console_in_use_timeout_sec = 15;
 static timestamp_t console_expire_time;
 #endif
@@ -79,7 +79,6 @@ void clock_disable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode)
 
 	/* Set PD bit to 1 */
 	NPCX_PWDWN_CTL(offset) |= reg_mask;
-
 }
 
 /*****************************************************************************/
@@ -100,13 +99,13 @@ void clock_init(void)
 	 * unstable for a little which can affect peripheral communication like
 	 * eSPI. Skip this if not needed (e.g. RW jump)
 	 */
-	if (NPCX_HFCGN != HFCGN || NPCX_HFCGML != HFCGML
-				|| NPCX_HFCGMH != HFCGMH) {
+	if (NPCX_HFCGN != HFCGN || NPCX_HFCGML != HFCGML ||
+	    NPCX_HFCGMH != HFCGMH) {
 		/*
 		 * Configure frequency multiplier M/N values according to
 		 * the requested OSC_CLK (Unit:Hz).
 		 */
-		NPCX_HFCGN  = HFCGN;
+		NPCX_HFCGN = HFCGN;
 		NPCX_HFCGML = HFCGML;
 		NPCX_HFCGMH = HFCGMH;
 
@@ -119,11 +118,11 @@ void clock_init(void)
 
 	/* Set all clock prescalers of core and peripherals. */
 #if defined(CHIP_FAMILY_NPCX5)
-	NPCX_HFCGP  = (FPRED << 4);
+	NPCX_HFCGP = (FPRED << 4);
 	NPCX_HFCBCD = (NPCX_HFCBCD & 0xF0) | (APB1DIV | (APB2DIV << 2));
 #elif NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-	NPCX_HFCGP   = ((FPRED << 4) | AHB6DIV);
-	NPCX_HFCBCD  = (FIUDIV << 4);
+	NPCX_HFCGP = ((FPRED << 4) | AHB6DIV);
+	NPCX_HFCBCD = (FIUDIV << 4);
 	NPCX_HFCBCD1 = (APB1DIV | (APB2DIV << 4));
 #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
 	NPCX_HFCBCD2 = (APB3DIV | (APB4DIV << 4));
@@ -143,7 +142,7 @@ void clock_init(void)
 void clock_turbo(void)
 {
 	/* Configure Frequency multiplier values to 50MHz */
-	NPCX_HFCGN  = 0x02;
+	NPCX_HFCGN = 0x02;
 	NPCX_HFCGML = 0xEC;
 	NPCX_HFCGMH = 0x0B;
 
@@ -255,7 +254,8 @@ int clock_get_apb3_freq(void)
 void clock_wait_cycles(uint32_t cycles)
 {
 	asm volatile("1: subs %0, #1\n"
-		     "   bne 1b\n" : "+r"(cycles));
+		     "   bne 1b\n"
+		     : "+r"(cycles));
 }
 
 #ifdef CONFIG_LOW_POWER_IDLE
@@ -378,12 +378,11 @@ void __idle(void)
 			 * more detail.
 			 * Workaround: Apply the same bypass of idle.
 			 */
-			asm ("push {r0-r5}\n"
-			     "wfi\n"
-			     "ldm %0, {r0-r5}\n"
-			     "pop {r0-r5}\n"
-			     "isb\n" :: "r" (0x100A8000)
-			);
+			asm("push {r0-r5}\n"
+			    "wfi\n"
+			    "ldm %0, {r0-r5}\n"
+			    "pop {r0-r5}\n"
+			    "isb\n" ::"r"(0x100A8000));
 
 			/* Get time delay cause of deep idle */
 			next_evt_us = __hw_clock_get_sleep_time(evt_count);
@@ -431,12 +430,11 @@ void __idle(void)
 			 * TODO (ML): Workaround method for wfi issue.
 			 * Please see task.c for more detail
 			 */
-			asm ("push {r0-r5}\n"
-			     "wfi\n"
-			     "ldm %0, {r0-r5}\n"
-			     "pop {r0-r5}\n"
-			     "isb\n" :: "r" (0x100A8000)
-			);
+			asm("push {r0-r5}\n"
+			    "wfi\n"
+			    "ldm %0, {r0-r5}\n"
+			    "pop {r0-r5}\n"
+			    "isb\n" ::"r"(0x100A8000));
 		}
 
 		/*
@@ -448,30 +446,28 @@ void __idle(void)
 }
 #endif /* CONFIG_LOW_POWER_IDLE */
 
-
 #ifdef CONFIG_LOW_POWER_IDLE
 /**
  * Print low power idle statistics
  */
-static int command_idle_stats(int argc, char **argv)
+static int command_idle_stats(int argc, const char **argv)
 {
 	timestamp_t ts = get_time();
 
 	ccprintf("Num idle calls that sleep:           %d\n", idle_sleep_cnt);
 	ccprintf("Num idle calls that deep-sleep:      %d\n", idle_dsleep_cnt);
 	ccprintf("Time spent in deep-sleep:            %.6llds\n",
-			idle_dsleep_time_us);
+		 idle_dsleep_time_us);
 	ccprintf("Total time on:                       %.6llds\n", ts.val);
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats,
-		"",
-		"Print last idle stats");
+DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, "",
+			"Print last idle stats");
 
 /**
  * Configure deep sleep clock settings.
  */
-static int command_dsleep(int argc, char **argv)
+static int command_dsleep(int argc, const char **argv)
 {
 	int v;
 
@@ -501,17 +497,16 @@ static int command_dsleep(int argc, char **argv)
 
 	ccprintf("Sleep mask: %08x\n", (int)sleep_mask);
 	ccprintf("Console in use timeout:   %d sec\n",
-			console_in_use_timeout_sec);
+		 console_in_use_timeout_sec);
 	ccprintf("PMCSR register:      0x%02x\n", NPCX_PMCSR);
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(dsleep, command_dsleep,
-		"[ on | off | <timeout> sec]",
-		"Deep sleep clock settings:\nUse 'on' to force deep "
-		"sleep not to use low speed clock.\nUse 'off' to "
-		"allow deep sleep to auto-select using the low speed "
-		"clock.\n"
-		"Give a timeout value for the console in use timeout.\n"
-		"See also 'sleepmask'.");
+DECLARE_CONSOLE_COMMAND(dsleep, command_dsleep, "[ on | off | <timeout> sec]",
+			"Deep sleep clock settings:\nUse 'on' to force deep "
+			"sleep not to use low speed clock.\nUse 'off' to "
+			"allow deep sleep to auto-select using the low speed "
+			"clock.\n"
+			"Give a timeout value for the console in use timeout.\n"
+			"See also 'sleepmask'.");
 #endif /* CONFIG_LOW_POWER_IDLE */
diff --git a/chip/npcx/clock_chip.h b/chip/npcx/clock_chip.h
index 702b55c52a..c105194fdf 100644
--- a/chip/npcx/clock_chip.h
+++ b/chip/npcx/clock_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -95,40 +95,40 @@
  * OSC_CLK (Unit:Hz).
  */
 #if (OSC_CLK > 80000000)
-#define HFCGN    0x82 /* Set XF_RANGE as 1 if OSC_CLK >= 80MHz */
+#define HFCGN 0x82 /* Set XF_RANGE as 1 if OSC_CLK >= 80MHz */
 #else
-#define HFCGN    0x02
+#define HFCGN 0x02
 #endif
-#if   (OSC_CLK == 100000000)
-#define HFCGMH   0x0B
-#define HFCGML   0xEC
+#if (OSC_CLK == 100000000)
+#define HFCGMH 0x0B
+#define HFCGML 0xEC
 #elif (OSC_CLK == 90000000)
-#define HFCGMH   0x0A
-#define HFCGML   0xBA
+#define HFCGMH 0x0A
+#define HFCGML 0xBA
 #elif (OSC_CLK == 80000000)
-#define HFCGMH   0x09
-#define HFCGML   0x89
+#define HFCGMH 0x09
+#define HFCGML 0x89
 #elif (OSC_CLK == 66000000)
-#define HFCGMH   0x0F
-#define HFCGML   0xBC
+#define HFCGMH 0x0F
+#define HFCGML 0xBC
 #elif (OSC_CLK == 50000000)
-#define HFCGMH   0x0B
-#define HFCGML   0xEC
+#define HFCGMH 0x0B
+#define HFCGML 0xEC
 #elif (OSC_CLK == 48000000)
-#define HFCGMH   0x0B
-#define HFCGML   0x72
+#define HFCGMH 0x0B
+#define HFCGML 0x72
 #elif (OSC_CLK == 40000000)
-#define HFCGMH   0x09
-#define HFCGML   0x89
+#define HFCGMH 0x09
+#define HFCGML 0x89
 #elif (OSC_CLK == 33000000)
-#define HFCGMH   0x07
-#define HFCGML   0xDE
+#define HFCGMH 0x07
+#define HFCGML 0xDE
 #elif (OSC_CLK == 30000000)
-#define HFCGMH   0x07
-#define HFCGML   0x27
+#define HFCGMH 0x07
+#define HFCGML 0x27
 #elif (OSC_CLK == 26000000)
-#define HFCGMH   0x06
-#define HFCGML   0x33
+#define HFCGMH 0x06
+#define HFCGML 0x33
 #else
 #error "Unsupported OSC_CLK Frequency"
 #endif
diff --git a/chip/npcx/config_chip-npcx5.h b/chip/npcx/config_chip-npcx5.h
index 434caba1d8..53713b2dfb 100644
--- a/chip/npcx/config_chip-npcx5.h
+++ b/chip/npcx/config_chip-npcx5.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,10 +14,10 @@
  */
 
 /* Chip ID for all variants */
-#define NPCX585G_CHIP_ID		0x12
-#define NPCX575G_CHIP_ID		0x13
-#define NPCX586G_CHIP_ID		0x16
-#define NPCX576G_CHIP_ID		0x17
+#define NPCX585G_CHIP_ID 0x12
+#define NPCX575G_CHIP_ID 0x13
+#define NPCX586G_CHIP_ID 0x16
+#define NPCX576G_CHIP_ID 0x17
 
 /*****************************************************************************/
 /* Hardware features */
@@ -37,18 +37,18 @@
  */
 #define CONFIG_I2C_MULTI_PORT_CONTROLLER
 /* Number of I2C controllers */
-#define I2C_CONTROLLER_COUNT	4
+#define I2C_CONTROLLER_COUNT 4
 /* Number of I2C ports */
-#define I2C_PORT_COUNT		5
+#define I2C_PORT_COUNT 5
 
 /*****************************************************************************/
 /* Memory mapping */
-#define NPCX_BTRAM_SIZE		0x800 /* 2KB data ram used by booter. */
-#define CONFIG_RAM_BASE		0x200C0000 /* memory address of data ram */
-#define CONFIG_DATA_RAM_SIZE	0x00008000 /* Size of data RAM */
-#define CONFIG_RAM_SIZE		(CONFIG_DATA_RAM_SIZE - NPCX_BTRAM_SIZE)
-#define CONFIG_LPRAM_BASE	0x40001600 /* memory address of lpwr ram */
-#define CONFIG_LPRAM_SIZE	0x00000620 /* 1568B low power ram */
+#define NPCX_BTRAM_SIZE 0x800 /* 2KB data ram used by booter. */
+#define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */
+#define CONFIG_DATA_RAM_SIZE 0x00008000 /* Size of data RAM */
+#define CONFIG_RAM_SIZE (CONFIG_DATA_RAM_SIZE - NPCX_BTRAM_SIZE)
+#define CONFIG_LPRAM_BASE 0x40001600 /* memory address of lpwr ram */
+#define CONFIG_LPRAM_SIZE 0x00000620 /* 1568B low power ram */
 
 /* Use chip variant to specify the size and start address of program memory */
 #if defined(CHIP_VARIANT_NPCX5M5G)
diff --git a/chip/npcx/config_chip-npcx7.h b/chip/npcx/config_chip-npcx7.h
index 8404f16635..e44aebe6cf 100644
--- a/chip/npcx/config_chip-npcx7.h
+++ b/chip/npcx/config_chip-npcx7.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,26 +16,27 @@
  */
 
 /* Chip ID for all variants */
-#define NPCX787G_CHIP_ID		0x1F
-#define NPCX796F_A_B_CHIP_ID		0x21
-#define NPCX796F_C_CHIP_ID		0x29
-#define NPCX797F_C_CHIP_ID		0x20
-#define NPCX797W_B_CHIP_ID		0x24
-#define NPCX797W_C_CHIP_ID		0x2C
+#define NPCX787G_CHIP_ID 0x1F
+#define NPCX796F_A_B_CHIP_ID 0x21
+#define NPCX796F_C_CHIP_ID 0x29
+#define NPCX797F_C_CHIP_ID 0x20
+#define NPCX797W_B_CHIP_ID 0x24
+#define NPCX797W_C_CHIP_ID 0x2C
 
 /*****************************************************************************/
 /* Hardware features */
 
 /* The optional hardware features depend on chip variant */
-#if defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \
+#if defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) ||      \
 	defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M7FC) || \
 	defined(CHIP_VARIANT_NPCX7M7WB) || defined(CHIP_VARIANT_NPCX7M7WC)
 #define NPCX_INT_FLASH_SUPPORT /* Internal flash support */
-#define NPCX_PSL_MODE_SUPPORT /* Power switch logic mode for ultra-low power */
+#define NPCX_PSL_MODE_SUPPORT /* Power switch logic mode for ultra-low power \
+			       */
 #define NPCX_EXT32K_OSC_SUPPORT /* External 32KHz crytal osc. input support */
 #endif
 
-#if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) || \
+#if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) ||     \
 	defined(CHIP_VARIANT_NPCX7M7FC) || defined(CHIP_VARIANT_NPCX7M7WB) || \
 	defined(CHIP_VARIANT_NPCX7M7WC)
 #define NPCX_UART_FIFO_SUPPORT
@@ -90,68 +91,68 @@
 
 /*****************************************************************************/
 /* Memory mapping */
-#define NPCX_BTRAM_SIZE    0x800 /* 2KB data ram used by booter. */
+#define NPCX_BTRAM_SIZE 0x800 /* 2KB data ram used by booter. */
 
 #define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + NPCX_PROGRAM_MEMORY_SIZE)
 
 #if defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \
 	defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M6G)
-	/* 192KB RAM for FW code */
-#	define NPCX_PROGRAM_MEMORY_SIZE (192 * 1024)
-	/* program memory base address for Code RAM (0x100C0000 - 192KB) */
-#	define CONFIG_PROGRAM_MEMORY_BASE 0x10090000
-#	define CONFIG_RAM_BASE    0x200C0000 /* memory address of data ram */
-	/* 62 KB data RAM + 2 KB BT RAM size */
-#	define CONFIG_DATA_RAM_SIZE    0x00010000
+/* 192KB RAM for FW code */
+#define NPCX_PROGRAM_MEMORY_SIZE (192 * 1024)
+/* program memory base address for Code RAM (0x100C0000 - 192KB) */
+#define CONFIG_PROGRAM_MEMORY_BASE 0x10090000
+#define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */
+/* 62 KB data RAM + 2 KB BT RAM size */
+#define CONFIG_DATA_RAM_SIZE 0x00010000
 #elif defined(CHIP_VARIANT_NPCX7M7WB)
-	/* 256KB RAM for FW code */
-#	define NPCX_PROGRAM_MEMORY_SIZE (256 * 1024)
-	/* program memory base address for Code RAM (0x100B0000 - 256KB) */
-#	define CONFIG_PROGRAM_MEMORY_BASE 0x10070000
-#	define CONFIG_RAM_BASE    0x200B0000 /* memory address of data ram */
-	/* 126 KB data RAM + 2 KB BT RAM size */
-#	define CONFIG_DATA_RAM_SIZE    0x00020000
+/* 256KB RAM for FW code */
+#define NPCX_PROGRAM_MEMORY_SIZE (256 * 1024)
+/* program memory base address for Code RAM (0x100B0000 - 256KB) */
+#define CONFIG_PROGRAM_MEMORY_BASE 0x10070000
+#define CONFIG_RAM_BASE 0x200B0000 /* memory address of data ram */
+/* 126 KB data RAM + 2 KB BT RAM size */
+#define CONFIG_DATA_RAM_SIZE 0x00020000
 #elif defined(CHIP_VARIANT_NPCX7M7FC) || defined(CHIP_VARIANT_NPCX7M7WC)
-	/*
-	 * Code RAM is normally assumed to be same as image size, but since
-	 * we exclude 4k from the image (see NPCX_PROGRAM_MEMORY_SIZE) we
-	 * need to explicitly configure it. This is the actual size of code
-	 * RAM on-chip.
-	 */
-#	define CONFIG_CODE_RAM_SIZE (256 * 1024)
-	/*
-	 * In npcx797wc and npcx797fc, the code RAM size is limited by the
-	 * internal flash size (i.e. 512 KB/2=256 KB.) The driver has to
-	 * re-organize the memory to:
-	 * 1. the overall memory (RAM) layout is re-organized against the
-	 * datasheet:
-	 *     In datasheet: 320 KB code RAM + 64 KB data RAM
-	 *     After re-organization: 256 KB code RAM + 128 KB data RAM.
-	 * 2. 256KB program RAM, but only 512K of Flash (vs 1M for the
-	 * -WB). After the boot header is added, a 256K image would be
-	 * too large to fit in either RO or RW sections of Flash (each
-	 * of which is half of it). Because other code assumes that
-	 * image size is a multiple of Flash erase granularity, we
-	 * sacrifice a whole sector.
-	 */
-#	define NPCX_PROGRAM_MEMORY_SIZE (CONFIG_CODE_RAM_SIZE - 0x1000)
-	/* program memory base address for Code RAM (0x100B0000 - 256KB) */
-#	define CONFIG_PROGRAM_MEMORY_BASE 0x10070000
-#	define CONFIG_RAM_BASE    0x200B0000 /* memory address of data ram */
-	/* 126 KB data RAM + 2 KB BT RAM size */
-#	define CONFIG_DATA_RAM_SIZE    0x00020000
-
-	/*
-	 * Override default NPCX_RAM_SIZE because NPCX_PROGRAM_MEMORY_SIZE
-	 * is not the actual size of code RAM.
-	 */
-#	undef NPCX_RAM_SIZE
-#	define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + CONFIG_CODE_RAM_SIZE)
+/*
+ * Code RAM is normally assumed to be same as image size, but since
+ * we exclude 4k from the image (see NPCX_PROGRAM_MEMORY_SIZE) we
+ * need to explicitly configure it. This is the actual size of code
+ * RAM on-chip.
+ */
+#define CONFIG_CODE_RAM_SIZE (256 * 1024)
+/*
+ * In npcx797wc and npcx797fc, the code RAM size is limited by the
+ * internal flash size (i.e. 512 KB/2=256 KB.) The driver has to
+ * re-organize the memory to:
+ * 1. the overall memory (RAM) layout is re-organized against the
+ * datasheet:
+ *     In datasheet: 320 KB code RAM + 64 KB data RAM
+ *     After re-organization: 256 KB code RAM + 128 KB data RAM.
+ * 2. 256KB program RAM, but only 512K of Flash (vs 1M for the
+ * -WB). After the boot header is added, a 256K image would be
+ * too large to fit in either RO or RW sections of Flash (each
+ * of which is half of it). Because other code assumes that
+ * image size is a multiple of Flash erase granularity, we
+ * sacrifice a whole sector.
+ */
+#define NPCX_PROGRAM_MEMORY_SIZE (CONFIG_CODE_RAM_SIZE - 0x1000)
+/* program memory base address for Code RAM (0x100B0000 - 256KB) */
+#define CONFIG_PROGRAM_MEMORY_BASE 0x10070000
+#define CONFIG_RAM_BASE 0x200B0000 /* memory address of data ram */
+/* 126 KB data RAM + 2 KB BT RAM size */
+#define CONFIG_DATA_RAM_SIZE 0x00020000
+
+/*
+ * Override default NPCX_RAM_SIZE because NPCX_PROGRAM_MEMORY_SIZE
+ * is not the actual size of code RAM.
+ */
+#undef NPCX_RAM_SIZE
+#define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + CONFIG_CODE_RAM_SIZE)
 #else
-#	error "Unsupported chip variant"
+#error "Unsupported chip variant"
 #endif
 
-#define CONFIG_RAM_SIZE         (CONFIG_DATA_RAM_SIZE - NPCX_BTRAM_SIZE)
+#define CONFIG_RAM_SIZE (CONFIG_DATA_RAM_SIZE - NPCX_BTRAM_SIZE)
 /* no low power ram in npcx7 series */
 
 #endif /* __CROS_EC_CONFIG_CHIP_NPCX7_H */
diff --git a/chip/npcx/config_chip-npcx9.h b/chip/npcx/config_chip-npcx9.h
index 7f154dbe42..736aef8a1c 100644
--- a/chip/npcx/config_chip-npcx9.h
+++ b/chip/npcx/config_chip-npcx9.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,8 +16,8 @@
  */
 
 /* Chip ID for all variants */
-#define NPCX996F_CHIP_ID		0x21
-#define NPCX993F_CHIP_ID		0x25
+#define NPCX996F_CHIP_ID 0x21
+#define NPCX993F_CHIP_ID 0x25
 
 /*****************************************************************************/
 /* Hardware features */
@@ -25,7 +25,8 @@
 #define NPCX_EXT32K_OSC_SUPPORT /* External 32KHz crytal osc. input support */
 #define NPCX_INT_FLASH_SUPPORT /* Internal flash support */
 #define NPCX_LCT_SUPPORT /* Long Countdown Timer support */
-#define NPCX_PSL_MODE_SUPPORT /* Power switch logic mode for ultra-low power */
+#define NPCX_PSL_MODE_SUPPORT /* Power switch logic mode for ultra-low power \
+			       */
 
 #define NPCX_UART_FIFO_SUPPORT
 /* Number of UART modules. */
@@ -55,10 +56,10 @@
 
 /* PSL_OUT optional configuration */
 /* Set PSL_OUT mode to pulse mode */
-#define NPCX_PSL_CFG_PSL_OUT_PULSE	BIT(0)
+#define NPCX_PSL_CFG_PSL_OUT_PULSE BIT(0)
 /* set PSL_OUT to open-drain */
-#define NPCX_PSL_CFG_PSL_OUT_OD		BIT(1)
-#define CONFIG_HIBERNATE_PSL_OUT_FLAGS	0
+#define NPCX_PSL_CFG_PSL_OUT_OD BIT(1)
+#define CONFIG_HIBERNATE_PSL_OUT_FLAGS 0
 
 /*
  * Workaound the issue 3.10 in the NPCX99nF errata rev1.2
@@ -75,36 +76,35 @@
 #define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + NPCX_PROGRAM_MEMORY_SIZE)
 
 #if defined(CHIP_VARIANT_NPCX9M3F)
-	/*
-	 * 256KB program RAM, but only 512K of Flash. After the boot header is
-	 * added, a 256K image would be too large to fit in either RO or RW
-	 * sections of Flash (each of which is half of it). Because other code
-	 * assumes that image size is a multiple of Flash erase granularity, we
-	 * sacrifice a whole sector.
-	 */
-#	define NPCX_PROGRAM_MEMORY_SIZE (256 * 1024 - 0x1000)
-	/* program memory base address for Code RAM (0x100C0000 - 256KB) */
-#	define CONFIG_PROGRAM_MEMORY_BASE 0x10080000
-#	define CONFIG_RAM_BASE    0x200C0000 /* memory address of data ram */
-	/* Two blocks of data RAM - total size is 64KB */
-#	define CONFIG_DATA_RAM_SIZE    0x00010000
-#	define CONFIG_RAM_SIZE         CONFIG_DATA_RAM_SIZE
-
-	/* Override default NPCX_RAM_SIZE because we're excluding a block. */
-#	undef NPCX_RAM_SIZE
-#	define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + \
-			      NPCX_PROGRAM_MEMORY_SIZE + 0x1000)
+/*
+ * 256KB program RAM, but only 512K of Flash. After the boot header is
+ * added, a 256K image would be too large to fit in either RO or RW
+ * sections of Flash (each of which is half of it). Because other code
+ * assumes that image size is a multiple of Flash erase granularity, we
+ * sacrifice a whole sector.
+ */
+#define NPCX_PROGRAM_MEMORY_SIZE (256 * 1024 - 0x1000)
+/* program memory base address for Code RAM (0x100C0000 - 256KB) */
+#define CONFIG_PROGRAM_MEMORY_BASE 0x10080000
+#define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */
+/* Two blocks of data RAM - total size is 64KB */
+#define CONFIG_DATA_RAM_SIZE 0x00010000
+#define CONFIG_RAM_SIZE CONFIG_DATA_RAM_SIZE
+
+/* Override default NPCX_RAM_SIZE because we're excluding a block. */
+#undef NPCX_RAM_SIZE
+#define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + NPCX_PROGRAM_MEMORY_SIZE + 0x1000)
 #elif defined(CHIP_VARIANT_NPCX9M6F)
-	/* 192KB RAM for FW code */
-#	define NPCX_PROGRAM_MEMORY_SIZE (192 * 1024)
-	/* program memory base address for Code RAM (0x100C0000 - 192KB) */
-#	define CONFIG_PROGRAM_MEMORY_BASE 0x10090000
-#	define CONFIG_RAM_BASE    0x200C0000 /* memory address of data ram */
-	/* Two blocks of data RAM - total size is 64KB */
-#	define CONFIG_DATA_RAM_SIZE    0x00010000
-#	define CONFIG_RAM_SIZE         CONFIG_DATA_RAM_SIZE
+/* 192KB RAM for FW code */
+#define NPCX_PROGRAM_MEMORY_SIZE (192 * 1024)
+/* program memory base address for Code RAM (0x100C0000 - 192KB) */
+#define CONFIG_PROGRAM_MEMORY_BASE 0x10090000
+#define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */
+/* Two blocks of data RAM - total size is 64KB */
+#define CONFIG_DATA_RAM_SIZE 0x00010000
+#define CONFIG_RAM_SIZE CONFIG_DATA_RAM_SIZE
 #else
-#	error "Unsupported chip variant"
+#error "Unsupported chip variant"
 #endif
 
 /* Internal spi-flash setting */
@@ -112,5 +112,4 @@
 #define CONFIG_SPI_FLASH_W25Q40 /* Internal spi flash type */
 #define CONFIG_FLASH_SIZE_BYTES 0x00080000 /* 512 KB internal spi flash */
 
-
 #endif /* __CROS_EC_CONFIG_CHIP_NPCX9_H */
diff --git a/chip/npcx/config_chip.h b/chip/npcx/config_chip.h
index c397161e07..d0bfe0a767 100644
--- a/chip/npcx/config_chip.h
+++ b/chip/npcx/config_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,20 +13,20 @@
  * Set the chip family version to 4 digits to keep the flexibility in case
  * we need the minor version for chip variants in a family.
  */
-#define NPCX_FAMILY_NPCX5        5000
-#define NPCX_FAMILY_NPCX7        7000
-#define NPCX_FAMILY_NPCX9        9000
+#define NPCX_FAMILY_NPCX5 5000
+#define NPCX_FAMILY_NPCX7 7000
+#define NPCX_FAMILY_NPCX9 9000
 
 /* Features depend on chip family */
 #if defined(CHIP_FAMILY_NPCX5)
 #include "config_chip-npcx5.h"
-#define NPCX_FAMILY_VERSION      NPCX_FAMILY_NPCX5
+#define NPCX_FAMILY_VERSION NPCX_FAMILY_NPCX5
 #elif defined(CHIP_FAMILY_NPCX7)
 #include "config_chip-npcx7.h"
-#define NPCX_FAMILY_VERSION      NPCX_FAMILY_NPCX7
+#define NPCX_FAMILY_VERSION NPCX_FAMILY_NPCX7
 #elif defined(CHIP_FAMILY_NPCX9)
 #include "config_chip-npcx9.h"
-#define NPCX_FAMILY_VERSION      NPCX_FAMILY_NPCX9
+#define NPCX_FAMILY_VERSION NPCX_FAMILY_NPCX9
 #else
 #error "Unsupported chip family"
 #endif
@@ -46,27 +46,27 @@
  * Notice instant wake-up from deep-idle cannot exceed 200 ms
  */
 #define HOOK_TICK_INTERVAL_MS 200
-#define HOOK_TICK_INTERVAL    (HOOK_TICK_INTERVAL_MS * MSEC)
+#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC)
 
 /* System stack size */
-#define CONFIG_STACK_SIZE       1024
+#define CONFIG_STACK_SIZE 1024
 
 /* non-standard task stack sizes */
-#define IDLE_TASK_STACK_SIZE		672
-#define LARGER_TASK_STACK_SIZE		800
-#define VENTI_TASK_STACK_SIZE		928
-#define ULTRA_TASK_STACK_SIZE		1056
-#define TRENTA_TASK_STACK_SIZE		1184
+#define IDLE_TASK_STACK_SIZE 672
+#define LARGER_TASK_STACK_SIZE 800
+#define VENTI_TASK_STACK_SIZE 928
+#define ULTRA_TASK_STACK_SIZE 1056
+#define TRENTA_TASK_STACK_SIZE 1184
 
-#define CHARGER_TASK_STACK_SIZE		800
-#define HOOKS_TASK_STACK_SIZE		800
-#define CONSOLE_TASK_STACK_SIZE		800
+#define CHARGER_TASK_STACK_SIZE 800
+#define HOOKS_TASK_STACK_SIZE 800
+#define CONSOLE_TASK_STACK_SIZE 800
 
 /* Default task stack size */
-#define TASK_STACK_SIZE			672
+#define TASK_STACK_SIZE 672
 
 /* Address of RAM log used by Booter */
-#define ADDR_BOOT_RAMLOG        0x100C7FC0
+#define ADDR_BOOT_RAMLOG 0x100C7FC0
 
 #include "config_flash_layout.h"
 
@@ -79,7 +79,7 @@
 /* Chip needs to do custom pre-init */
 #define CONFIG_CHIP_PRE_INIT
 /* Default use UART1 as console */
-#define CONFIG_CONSOLE_UART    0
+#define CONFIG_CONSOLE_UART 0
 
 #define GPIO_PIN(port, index) GPIO_##port, BIT(index)
 #define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m)
@@ -88,4 +88,4 @@
 #define NPCX_SELECT_KSI_TO_GPIO
 #endif
 
-#endif  /* __CROS_EC_CONFIG_CHIP_H */
+#endif /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/chip/npcx/config_flash_layout.h b/chip/npcx/config_flash_layout.h
index 79961548c9..926a03bb3c 100644
--- a/chip/npcx/config_flash_layout.h
+++ b/chip/npcx/config_flash_layout.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,56 +18,56 @@
 #define CONFIG_MAPPED_STORAGE
 /* Storage is memory-mapped, but program runs from SRAM */
 #define CONFIG_MAPPED_STORAGE_BASE 0x64000000
-#undef  CONFIG_FLASH_PSTATE
+#undef CONFIG_FLASH_PSTATE
 
 #if defined(CHIP_VARIANT_NPCX5M5G)
-#define CONFIG_EC_PROTECTED_STORAGE_OFF  0
+#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
 #define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x20000
-#define CONFIG_EC_WRITABLE_STORAGE_OFF   0x20000
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE  0x20000
+#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x20000
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x20000
 #elif defined(CHIP_VARIANT_NPCX5M6G)
-#define CONFIG_EC_PROTECTED_STORAGE_OFF  0
+#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
 #define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x40000
-#define CONFIG_EC_WRITABLE_STORAGE_OFF   0x40000
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE  0x40000
-#elif defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \
+#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x40000
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x40000
+#elif defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) ||   \
 	defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M6G) || \
 	defined(CHIP_VARIANT_NPCX7M7FC) || defined(CHIP_VARIANT_NPCX7M7WC)
-#define CONFIG_EC_PROTECTED_STORAGE_OFF  0
+#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
 #define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x40000
-#define CONFIG_EC_WRITABLE_STORAGE_OFF   0x40000
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE  0x40000
+#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x40000
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x40000
 #elif defined(CHIP_VARIANT_NPCX7M7WB)
-#define CONFIG_EC_PROTECTED_STORAGE_OFF  0
+#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
 #define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x80000
-#define CONFIG_EC_WRITABLE_STORAGE_OFF   0x80000
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE  0x80000
+#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x80000
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x80000
 #elif defined(CHIP_VARIANT_NPCX9M3F) || defined(CHIP_VARIANT_NPCX9M6F)
-#define CONFIG_EC_PROTECTED_STORAGE_OFF  0
+#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
 #define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x40000
-#define CONFIG_EC_WRITABLE_STORAGE_OFF   0x40000
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE  0x40000
+#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x40000
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x40000
 #else
 #error "Unsupported chip variant"
 #endif
 
 /* Header support which is used by booter to copy FW from flash to code ram */
 #define NPCX_RO_HEADER
-#define CONFIG_RO_HDR_MEM_OFF	0x0
-#define CONFIG_RO_HDR_SIZE	0x40
+#define CONFIG_RO_HDR_MEM_OFF 0x0
+#define CONFIG_RO_HDR_SIZE 0x40
 
-#define CONFIG_WP_STORAGE_OFF	CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE	CONFIG_EC_PROTECTED_STORAGE_SIZE
+#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
+#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
 
 /* RO firmware in program memory - use all of program memory */
-#define CONFIG_RO_MEM_OFF	0
-#define CONFIG_RO_SIZE		NPCX_PROGRAM_MEMORY_SIZE
+#define CONFIG_RO_MEM_OFF 0
+#define CONFIG_RO_SIZE NPCX_PROGRAM_MEMORY_SIZE
 
 /*
  * ROM resident area in flash used to store data objects that are not copied
  * into code RAM. Enable using the CONFIG_CHIP_INIT_ROM_REGION option.
  */
-#define CONFIG_RO_ROM_RESIDENT_MEM_OFF	CONFIG_RO_SIZE
+#define CONFIG_RO_ROM_RESIDENT_MEM_OFF CONFIG_RO_SIZE
 #define CONFIG_RO_ROM_RESIDENT_SIZE \
 	(CONFIG_EC_PROTECTED_STORAGE_SIZE - CONFIG_RO_SIZE)
 
@@ -75,10 +75,10 @@
  * RW firmware in program memory - Identical to RO, only one image loaded at
  * a time.
  */
-#define CONFIG_RW_MEM_OFF	CONFIG_RO_MEM_OFF
-#define CONFIG_RW_SIZE		CONFIG_RO_SIZE
+#define CONFIG_RW_MEM_OFF CONFIG_RO_MEM_OFF
+#define CONFIG_RW_SIZE CONFIG_RO_SIZE
 
-#define CONFIG_RW_ROM_RESIDENT_MEM_OFF	CONFIG_RW_SIZE
+#define CONFIG_RW_ROM_RESIDENT_MEM_OFF CONFIG_RW_SIZE
 #define CONFIG_RW_ROM_RESIDENT_SIZE \
 	(CONFIG_EC_WRITABLE_STORAGE_SIZE - CONFIG_RW_SIZE)
 
@@ -102,8 +102,8 @@
  * writable flash regions are not a multiple of 64 KiB, then support
  * for CONFIG_FLASH_MULTIPLE_REGION must be added.
  */
-#define CONFIG_FLASH_ERASE_SIZE		0x10000
-#define NPCX_ERASE_COMMAND		CMD_BLOCK_64K_ERASE
+#define CONFIG_FLASH_ERASE_SIZE 0x10000
+#define NPCX_ERASE_COMMAND CMD_BLOCK_64K_ERASE
 
 #if (CONFIG_WP_STORAGE_SIZE != CONFIG_EC_WRITABLE_STORAGE_SIZE)
 #error "NPCX flash support assumes CONFIG_WP_STORAGE_SIZE and " \
@@ -120,16 +120,16 @@
 	"size or add support for CONFIG_FLASH_MULTIPLE_REGION."
 #endif
 
-#define CONFIG_FLASH_BANK_SIZE		CONFIG_FLASH_ERASE_SIZE
-#define CONFIG_FLASH_WRITE_SIZE		0x1  /* minimum write size */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE	256   /* one page size for write */
+#define CONFIG_FLASH_BANK_SIZE CONFIG_FLASH_ERASE_SIZE
+#define CONFIG_FLASH_WRITE_SIZE 0x1 /* minimum write size */
+#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* one page size for write */
 
 /* Use 4k sector erase for NPCX monitor flash erase operations. */
-#define NPCX_MONITOR_FLASH_ERASE_SIZE	0x1000
+#define NPCX_MONITOR_FLASH_ERASE_SIZE 0x1000
 
 /* RO image resides at start of protected region, right after header */
-#define CONFIG_RO_STORAGE_OFF	CONFIG_RO_HDR_SIZE
+#define CONFIG_RO_STORAGE_OFF CONFIG_RO_HDR_SIZE
 /* RW image resides at start of writable region */
-#define CONFIG_RW_STORAGE_OFF	0
+#define CONFIG_RW_STORAGE_OFF 0
 
 #endif /* __CROS_EC_CONFIG_FLASH_LAYOUT_H */
diff --git a/chip/npcx/espi.c b/chip/npcx/espi.c
index 7248c7711f..d64a22860d 100644
--- a/chip/npcx/espi.c
+++ b/chip/npcx/espi.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,114 +24,114 @@
 #define CPRINTS(...)
 #else
 #define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args)
 #endif
 
 /* Default eSPI configuration for VW events */
 struct vwevms_config_t {
-	uint8_t idx;        /* VW index */
-	uint8_t idx_en;     /* Index enable */
-	uint8_t pltrst_en;  /* Enable reset by PLTRST assert */
+	uint8_t idx; /* VW index */
+	uint8_t idx_en; /* Index enable */
+	uint8_t pltrst_en; /* Enable reset by PLTRST assert */
 	uint8_t espirst_en; /* Enable reset by eSPI_RST assert */
-	uint8_t int_en;     /* Interrupt/Wake-up enable */
+	uint8_t int_en; /* Interrupt/Wake-up enable */
 };
 
 struct vwevsm_config_t {
-	uint8_t idx;        /* VW index */
-	uint8_t idx_en;     /* Index enable */
-	uint8_t pltrst_en;  /* Enable reset by PLTRST assert */
-	uint8_t cdrst_en;   /* Enable cold reset */
-	uint8_t valid;      /* Valid VW mask */
+	uint8_t idx; /* VW index */
+	uint8_t idx_en; /* Index enable */
+	uint8_t pltrst_en; /* Enable reset by PLTRST assert */
+	uint8_t cdrst_en; /* Enable cold reset */
+	uint8_t valid; /* Valid VW mask */
 };
 
 /* Default MIWU configurations for VW events */
 struct host_wui_item {
 	uint16_t table : 2; /* MIWU table 0-2 */
 	uint16_t group : 3; /* MIWU group 0-7 */
-	uint16_t num   : 3; /* MIWU bit   0-7 */
-	uint16_t edge  : 4; /* MIWU edge trigger type rising/falling/any */
+	uint16_t num : 3; /* MIWU bit   0-7 */
+	uint16_t edge : 4; /* MIWU edge trigger type rising/falling/any */
 };
 
 /* Mapping item between VW signal, index and value */
 struct vw_event_t {
-	uint16_t name;     /* Name of signal */
-	uint8_t  evt_idx;  /* VW index of signal */
-	uint8_t  evt_val;  /* VW value of signal */
+	uint16_t name; /* Name of signal */
+	uint8_t evt_idx; /* VW index of signal */
+	uint8_t evt_val; /* VW value of signal */
 };
 
 /* Default settings of VWEVMS registers (Please refer Table.43/44) */
 static const struct vwevms_config_t espi_in_list[] = {
-	/* IDX EN ENPL ENESP IE/WE          VW Event Bit 0 - 3 (M->S)         */
-#ifdef CONFIG_HOSTCMD_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST
-	{0x02,  1,  0,  1,  1},  /* SLP_S3#,   SLP_S4#,    SLP_S5#,   Reserve */
+/* IDX EN ENPL ENESP IE/WE          VW Event Bit 0 - 3 (M->S)         */
+#ifdef CONFIG_HOST_INTERFACE_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST
+	{ 0x02, 1, 0, 1, 1 }, /* SLP_S3#,   SLP_S4#,    SLP_S5#,   Reserve */
 #else
-	{0x02,  1,  0,  0,  1},  /* SLP_S3#,   SLP_S4#,    SLP_S5#,   Reserve */
+	{ 0x02, 1, 0, 0, 1 }, /* SLP_S3#,   SLP_S4#,    SLP_S5#,   Reserve */
 #endif
-	{0x03,  1,  0,  1,  1},  /* SUS_STAT#, PLTRST#,    ORST_WARN, Reserve */
-	{0x07,  1,  1,  1,  1},  /* HRST_WARN, SMIOUT#,    NMIOUT#,   Reserve */
-	{0x41,  1,  0,  1,  1},  /* SUS_WARN#, SPWRDN_ACK, Reserve,   SLP_A#  */
-	{0x42,  1,  0,  0,  1},  /* SLP_LAN#,  SLP_WAN#,   Reserve,   Reserve */
-	{0x47,  1,  1,  1,  1},  /* HOST_C10,  Reserve,    Reserve,   Reserve */
+	{ 0x03, 1, 0, 1, 1 }, /* SUS_STAT#, PLTRST#,    ORST_WARN, Reserve */
+	{ 0x07, 1, 1, 1, 1 }, /* HRST_WARN, SMIOUT#,    NMIOUT#,   Reserve */
+	{ 0x41, 1, 0, 1, 1 }, /* SUS_WARN#, SPWRDN_ACK, Reserve,   SLP_A#  */
+	{ 0x42, 1, 0, 0, 1 }, /* SLP_LAN#,  SLP_WAN#,   Reserve,   Reserve */
+	{ 0x47, 1, 1, 1, 1 }, /* HOST_C10,  Reserve,    Reserve,   Reserve */
 };
 
 /* Default settings of VWEVSM registers (Please refer Table.43/44) */
 static const struct vwevsm_config_t espi_out_list[] = {
 	/* IDX EN ENPL ENCDR VDMASK         VW Event Bit 0 - 3 (S->M)         */
-	{0x04,  1,  0,  0, 0x0D}, /* ORST_ACK,   Reserve, WAKE#,   PME#       */
-	{0x05,  1,  0,  0, 0x0F}, /* SLV_BL_DNE, ERR_F,   ERR_NF,  SLV_BL_STS */
+	{ 0x04, 1, 0, 0, 0x0D }, /* ORST_ACK,   Reserve, WAKE#,   PME#       */
+	{ 0x05, 1, 0, 0, 0x0F }, /* SLV_BL_DNE, ERR_F,   ERR_NF,  SLV_BL_STS */
 #ifdef CONFIG_SCI_GPIO
-	{0x06,  1,  1,  0, 0x0C}, /* SCI#,       SMI#,    RCIN#,   HRST_ACK   */
+	{ 0x06, 1, 1, 0, 0x0C }, /* SCI#,       SMI#,    RCIN#,   HRST_ACK   */
 #else
-	{0x06,  1,  1,  0, 0x0F}, /* SCI#,       SMI#,    RCIN#,   HRST_ACK   */
+	{ 0x06, 1, 1, 0, 0x0F }, /* SCI#,       SMI#,    RCIN#,   HRST_ACK   */
 #endif
-	{0x40,  1,  0,  0, 0x01}, /* SUS_ACK,    Reserve, Reserve, Reserve    */
+	{ 0x40, 1, 0, 0, 0x01 }, /* SUS_ACK,    Reserve, Reserve, Reserve    */
 };
 
 /* eSPI interrupts used in MIWU */
 static const struct host_wui_item espi_vw_int_list[] = {
 	/* ESPI_RESET  */
-	{MIWU_TABLE_0, MIWU_GROUP_5, 5, MIWU_EDGE_FALLING},
+	{ MIWU_TABLE_0, MIWU_GROUP_5, 5, MIWU_EDGE_FALLING },
 	/* SLP_S3 */
-	{MIWU_TABLE_2, MIWU_GROUP_1, 0, MIWU_EDGE_ANYING},
+	{ MIWU_TABLE_2, MIWU_GROUP_1, 0, MIWU_EDGE_ANYING },
 	/* SLP_S4 */
-	{MIWU_TABLE_2, MIWU_GROUP_1, 1, MIWU_EDGE_ANYING},
+	{ MIWU_TABLE_2, MIWU_GROUP_1, 1, MIWU_EDGE_ANYING },
 	/* SLP_S5 */
-	{MIWU_TABLE_2, MIWU_GROUP_1, 2, MIWU_EDGE_ANYING},
+	{ MIWU_TABLE_2, MIWU_GROUP_1, 2, MIWU_EDGE_ANYING },
 	/* VW_WIRE_PLTRST */
-	{MIWU_TABLE_2, MIWU_GROUP_1, 5, MIWU_EDGE_ANYING},
+	{ MIWU_TABLE_2, MIWU_GROUP_1, 5, MIWU_EDGE_ANYING },
 	/* VW_WIRE_OOB_RST_WARN */
-	{MIWU_TABLE_2, MIWU_GROUP_1, 6, MIWU_EDGE_ANYING},
+	{ MIWU_TABLE_2, MIWU_GROUP_1, 6, MIWU_EDGE_ANYING },
 	/* VW_WIRE_HOST_RST_WARN */
-	{MIWU_TABLE_2, MIWU_GROUP_2, 0, MIWU_EDGE_ANYING},
+	{ MIWU_TABLE_2, MIWU_GROUP_2, 0, MIWU_EDGE_ANYING },
 	/* VW_WIRE_SUS_WARN */
-	{MIWU_TABLE_2, MIWU_GROUP_2, 4, MIWU_EDGE_ANYING},
+	{ MIWU_TABLE_2, MIWU_GROUP_2, 4, MIWU_EDGE_ANYING },
 };
 
 /* VW signals used in eSPI */
 static const struct vw_event_t vw_events_list[] = {
-	{VW_SLP_S3_L,                    0x02,   0x01},	/* index 02h (In)  */
-	{VW_SLP_S4_L,                    0x02,   0x02},
-	{VW_SLP_S5_L,                    0x02,   0x04},
-	{VW_SUS_STAT_L,                  0x03,   0x01},	/* index 03h (In)  */
-	{VW_PLTRST_L,                    0x03,   0x02},
-	{VW_OOB_RST_WARN,                0x03,   0x04},
-	{VW_OOB_RST_ACK,                 0x04,   0x01},	/* index 04h (Out) */
-	{VW_WAKE_L,                      0x04,   0x04},
-	{VW_PME_L,                       0x04,   0x08},
-	{VW_ERROR_FATAL,                 0x05,   0x02},	/* index 05h (Out) */
-	{VW_ERROR_NON_FATAL,             0x05,   0x04},
-	{VW_PERIPHERAL_BTLD_STATUS_DONE, 0x05,   0x09},
-	{VW_SCI_L,                       0x06,   0x01},	/* index 06h (Out) */
-	{VW_SMI_L,                       0x06,   0x02},
-	{VW_RCIN_L,                      0x06,   0x04},
-	{VW_HOST_RST_ACK,                0x06,   0x08},
-	{VW_HOST_RST_WARN,               0x07,   0x01},	/* index 07h (In)  */
-	{VW_SUS_ACK,                     0x40,   0x01},	/* index 40h (Out) */
-	{VW_SUS_WARN_L,                  0x41,   0x01},	/* index 41h (In)  */
-	{VW_SUS_PWRDN_ACK_L,             0x41,   0x02},
-	{VW_SLP_A_L,                     0x41,   0x08},
-	{VW_SLP_LAN,                     0x42,   0x01},	/* index 42h (In)  */
-	{VW_SLP_WLAN,                    0x42,   0x02},
+	{ VW_SLP_S3_L, 0x02, 0x01 }, /* index 02h (In)  */
+	{ VW_SLP_S4_L, 0x02, 0x02 },
+	{ VW_SLP_S5_L, 0x02, 0x04 },
+	{ VW_SUS_STAT_L, 0x03, 0x01 }, /* index 03h (In)  */
+	{ VW_PLTRST_L, 0x03, 0x02 },
+	{ VW_OOB_RST_WARN, 0x03, 0x04 },
+	{ VW_OOB_RST_ACK, 0x04, 0x01 }, /* index 04h (Out) */
+	{ VW_WAKE_L, 0x04, 0x04 },
+	{ VW_PME_L, 0x04, 0x08 },
+	{ VW_ERROR_FATAL, 0x05, 0x02 }, /* index 05h (Out) */
+	{ VW_ERROR_NON_FATAL, 0x05, 0x04 },
+	{ VW_PERIPHERAL_BTLD_STATUS_DONE, 0x05, 0x09 },
+	{ VW_SCI_L, 0x06, 0x01 }, /* index 06h (Out) */
+	{ VW_SMI_L, 0x06, 0x02 },
+	{ VW_RCIN_L, 0x06, 0x04 },
+	{ VW_HOST_RST_ACK, 0x06, 0x08 },
+	{ VW_HOST_RST_WARN, 0x07, 0x01 }, /* index 07h (In)  */
+	{ VW_SUS_ACK, 0x40, 0x01 }, /* index 40h (Out) */
+	{ VW_SUS_WARN_L, 0x41, 0x01 }, /* index 41h (In)  */
+	{ VW_SUS_PWRDN_ACK_L, 0x41, 0x02 },
+	{ VW_SLP_A_L, 0x41, 0x08 },
+	{ VW_SLP_LAN, 0x42, 0x01 }, /* index 42h (In)  */
+	{ VW_SLP_WLAN, 0x42, 0x02 },
 };
 
 /* Flag for boot load signals */
@@ -153,7 +153,7 @@ static void espi_reset_recovery(void)
 static void espi_vw_config_in(const struct vwevms_config_t *config)
 {
 	uint32_t val;
-	uint8_t  i, index;
+	uint8_t i, index;
 
 	switch (VM_TYPE(config->idx)) {
 	case ESPI_VW_TYPE_SYS_EV:
@@ -164,11 +164,10 @@ static void espi_vw_config_in(const struct vwevms_config_t *config)
 			if (index == config->idx) {
 				/* Get Wire field */
 				val = NPCX_VWEVMS(i) & 0x0F;
-				val |= VWEVMS_FIELD(config->idx,
-						config->idx_en,
-						config->pltrst_en,
-						config->int_en,
-						config->espirst_en);
+				val |= VWEVMS_FIELD(config->idx, config->idx_en,
+						    config->pltrst_en,
+						    config->int_en,
+						    config->espirst_en);
 				NPCX_VWEVMS(i) = val;
 				return;
 			}
@@ -196,11 +195,10 @@ static void espi_vw_config_out(const struct vwevsm_config_t *config)
 			if (index == config->idx) {
 				/* Preserve WIRE(3-0) and HW_WIRE (27-24). */
 				val = NPCX_VWEVSM(i) & 0x0F00000F;
-				val |= VWEVSM_FIELD(config->idx,
-						config->idx_en,
-						config->valid,
-						config->pltrst_en,
-						config->cdrst_en);
+				val |= VWEVSM_FIELD(config->idx, config->idx_en,
+						    config->valid,
+						    config->pltrst_en,
+						    config->cdrst_en);
 				NPCX_VWEVSM(i) = val;
 				return;
 			}
@@ -218,8 +216,8 @@ static void espi_enable_vw_int(const struct host_wui_item *vwire_int)
 {
 	uint8_t table = vwire_int->table;
 	uint8_t group = vwire_int->group;
-	uint8_t num   = vwire_int->num;
-	uint8_t edge  = vwire_int->edge;
+	uint8_t num = vwire_int->num;
+	uint8_t edge = vwire_int->edge;
 
 	/* Set detection mode to edge */
 	CLEAR_BIT(NPCX_WKMOD(table, group), num);
@@ -266,7 +264,7 @@ void espi_vw_power_signal_interrupt(enum espi_vw_signal signal)
 {
 	if (IS_ENABLED(CONFIG_HOST_ESPI_VW_POWER_SIGNAL))
 		/* TODO: Add VW handler in power/common.c */
-		power_signal_interrupt((enum gpio_signal) signal);
+		power_signal_interrupt((enum gpio_signal)signal);
 }
 
 void espi_wait_vw_not_dirty(enum espi_vw_signal signal, unsigned int timeout_us)
@@ -289,7 +287,7 @@ void espi_wait_vw_not_dirty(enum espi_vw_signal signal, unsigned int timeout_us)
 
 	timeout = get_time().val + (uint64_t)timeout_us;
 	while ((NPCX_VWEVSM(offset) & VWEVSM_DIRTY(1)) &&
-		(get_time().val < timeout)) {
+	       (get_time().val < timeout)) {
 		udelay(10);
 	}
 }
@@ -609,12 +607,12 @@ static void espi_interrupt(void)
 			 * handled by PLTRST separately.
 			 */
 			for (chan = NPCX_ESPI_CH_VW; chan < NPCX_ESPI_CH_COUNT;
-					chan++) {
+			     chan++) {
 				if (!IS_PERIPHERAL_CHAN_ENABLE(chan) &&
-						IS_HOST_CHAN_EN(chan))
+				    IS_HOST_CHAN_EN(chan))
 					ENABLE_ESPI_CHAN(chan);
 				else if (IS_PERIPHERAL_CHAN_ENABLE(chan) &&
-						!IS_HOST_CHAN_EN(chan))
+					 !IS_HOST_CHAN_EN(chan))
 					DISABLE_ESPI_CHAN(chan);
 			}
 
@@ -625,9 +623,8 @@ static void espi_interrupt(void)
 			 */
 			if (boot_load_done == 0 &&
 			    IS_PERIPHERAL_CHAN_ENABLE(NPCX_ESPI_CH_VW)) {
-
-				espi_vw_set_wire(
-					VW_PERIPHERAL_BTLD_STATUS_DONE, 1);
+				espi_vw_set_wire(VW_PERIPHERAL_BTLD_STATUS_DONE,
+						 1);
 				boot_load_done = 1;
 			}
 		}
@@ -662,7 +659,7 @@ void espi_init(void)
 
 	/* Support all I/O modes */
 	SET_FIELD(NPCX_ESPICFG, NPCX_ESPICFG_IOMODE_FIELD,
-		NPCX_ESPI_IO_MODE_ALL);
+		  NPCX_ESPI_IO_MODE_ALL);
 
 	/* Set eSPI speed to max supported */
 	SET_FIELD(NPCX_ESPICFG, NPCX_ESPICFG_MAXFREQ_FIELD,
@@ -681,14 +678,14 @@ void espi_init(void)
 		espi_enable_vw_int(&espi_vw_int_list[i]);
 }
 
-static int command_espi(int argc, char **argv)
+static int command_espi(int argc, const char **argv)
 {
 	uint32_t chan;
 	char *e;
 
 	if (argc == 1) {
 		return EC_ERROR_INVAL;
-	/* Get value of eSPI registers */
+		/* Get value of eSPI registers */
 	} else if (argc == 2) {
 		int i;
 
@@ -697,23 +694,23 @@ static int command_espi(int argc, char **argv)
 		} else if (strcasecmp(argv[1], "vsm") == 0) {
 			for (i = 0; i < ESPI_VWEVSM_NUM; i++) {
 				uint32_t val = NPCX_VWEVSM(i);
-				uint8_t  idx = VWEVSM_IDX_GET(val);
+				uint8_t idx = VWEVSM_IDX_GET(val);
 
 				ccprintf("VWEVSM%d: %02x [0x%08x]\n", i, idx,
-						val);
+					 val);
 			}
 		} else if (strcasecmp(argv[1], "vms") == 0) {
 			for (i = 0; i < ESPI_VWEVMS_NUM; i++) {
 				uint32_t val = NPCX_VWEVMS(i);
-				uint8_t  idx = VWEVMS_IDX_GET(val);
+				uint8_t idx = VWEVMS_IDX_GET(val);
 
 				ccprintf("VWEVMS%d: %02x [0x%08x]\n", i, idx,
-						val);
+					 val);
 			}
 		}
-	/* Enable/Disable the channels of eSPI */
+		/* Enable/Disable the channels of eSPI */
 	} else if (argc == 3) {
-		uint32_t m = (uint32_t) strtoi(argv[2], &e, 0);
+		uint32_t m = (uint32_t)strtoi(argv[2], &e, 0);
 
 		if (*e)
 			return EC_ERROR_PARAM2;
@@ -733,6 +730,5 @@ static int command_espi(int argc, char **argv)
 	}
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(espi, command_espi,
-			"cfg/vms/vsm/en/dis [channel]",
+DECLARE_CONSOLE_COMMAND(espi, command_espi, "cfg/vms/vsm/en/dis [channel]",
 			"eSPI configurations");
diff --git a/chip/npcx/fan.c b/chip/npcx/fan.c
index 5b56f33edf..6a246f5c6a 100644
--- a/chip/npcx/fan.c
+++ b/chip/npcx/fan.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,7 +25,7 @@
 #if !(DEBUG_FAN)
 #define CPRINTS(...)
 #else
-#define CPRINTS(format, args...) cprints(CC_PWM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_PWM, format, ##args)
 #endif
 
 /* Tacho measurement state */
@@ -92,7 +92,7 @@ static int rpm_pre[FAN_CH_COUNT];
 #define TACHO_MAX_CNT (BIT(16) - 1)
 
 /* Margin of target rpm */
-#define RPM_MARGIN(rpm_target) (((rpm_target) * RPM_DEVIATION) / 100)
+#define RPM_MARGIN(rpm_target) (((rpm_target)*RPM_DEVIATION) / 100)
 
 /**
  * MFT get fan rpm value
@@ -144,7 +144,7 @@ static int mft_fan_rpm(int ch)
 /**
  * Set fan prescaler based on apb1 clock
  *
- * @param   none
+ * @param   ch      operation channel
  * @return  none
  * @notes   changed when initial or HOOK_FREQ_CHANGE command
  */
@@ -154,14 +154,14 @@ void mft_set_apb1_prescaler(int ch)
 	uint16_t prescaler_divider = 0;
 
 	/* Set clock prescaler divider to MFT module*/
-	prescaler_divider = (uint16_t)(clock_get_apb1_freq()
-			/ fan_status[ch].mft_freq);
+	prescaler_divider =
+		(uint16_t)(clock_get_apb1_freq() / fan_status[ch].mft_freq);
 	if (prescaler_divider >= 1)
 		prescaler_divider = prescaler_divider - 1;
 	if (prescaler_divider > 0xFF)
 		prescaler_divider = 0xFF;
 
-	NPCX_TPRSC(mdl) = (uint8_t) prescaler_divider;
+	NPCX_TPRSC(mdl) = (uint8_t)prescaler_divider;
 }
 
 /**
@@ -184,7 +184,6 @@ static void fan_config(int ch, int enable_mft_read_rpm)
 
 	/* Need to initialize MFT or not */
 	if (enable_mft_read_rpm) {
-
 		/* Initialize tacho sampling rate */
 		if (clk_src == TCKC_LFCLK)
 			p_status->mft_freq = INT_32K_CLOCK;
@@ -195,7 +194,7 @@ static void fan_config(int ch, int enable_mft_read_rpm)
 
 		/* Set mode 5 to MFT module */
 		SET_FIELD(NPCX_TMCTRL(mdl), NPCX_TMCTRL_MDSEL_FIELD,
-				NPCX_MFT_MDSEL_5);
+			  NPCX_MFT_MDSEL_5);
 
 		/* Set MFT operation frequency */
 		if (clk_src == TCKC_PRESCALE_APB1_CLK)
@@ -203,11 +202,11 @@ static void fan_config(int ch, int enable_mft_read_rpm)
 
 		/* Set the low power mode or not. */
 		UPDATE_BIT(NPCX_TCKC(mdl), NPCX_TCKC_LOW_PWR,
-				clk_src == TCKC_LFCLK);
+			   clk_src == TCKC_LFCLK);
 
 		/* Set the default count-down timer. */
 		NPCX_TCNT1(mdl) = TACHO_MAX_CNT;
-		NPCX_TCRA(mdl)  = TACHO_MAX_CNT;
+		NPCX_TCRA(mdl) = TACHO_MAX_CNT;
 
 		/* Set the edge polarity to rising. */
 		SET_BIT(NPCX_TMCTRL(mdl), NPCX_TMCTRL_TAEDG);
@@ -300,7 +299,8 @@ enum fan_status fan_smart_control(int ch, int rpm_actual, int rpm_target)
 	 * In this case, don't step the PWM duty too aggressively.
 	 * See b:225208265 for more detail.
 	 */
-	if (rpm_pre[ch] == 0 && rpm_actual == 0)  {
+	if (rpm_pre[ch] == 0 && rpm_actual == 0 &&
+	    IS_ENABLED(CONFIG_FAN_BYPASS_SLOW_RESPONSE)) {
 		rpm_diff = RPM_MARGIN(rpm_target) + 1;
 	} else {
 		rpm_diff = rpm_target - rpm_actual;
@@ -319,7 +319,7 @@ enum fan_status fan_smart_control(int ch, int rpm_actual, int rpm_target)
 
 		fan_adjust_duty(ch, rpm_diff, duty);
 		return FAN_STATUS_CHANGING;
-	/* Decrease PWM duty */
+		/* Decrease PWM duty */
 	} else if (rpm_diff < -RPM_MARGIN(rpm_target)) {
 		if (duty == 1 && rpm_target != 0)
 			return FAN_STATUS_FRUSTRATED;
@@ -340,11 +340,12 @@ void fan_tick_func(void)
 {
 	int ch;
 
-	for (ch = 0; ch < FAN_CH_COUNT ; ch++) {
+	for (ch = 0; ch < FAN_CH_COUNT; ch++) {
 		volatile struct fan_status_t *p_status = fan_status + ch;
 		/* Make sure rpm mode is enabled */
 		if (p_status->fan_mode != TACHO_FAN_RPM) {
-		/* Fan in duty mode still want rpm_actual being updated. */
+			/* Fan in duty mode still want rpm_actual being updated.
+			 */
 			p_status->rpm_actual = mft_fan_rpm(ch);
 			if (p_status->rpm_actual > 0)
 				p_status->auto_status = FAN_STATUS_LOCKED;
@@ -357,8 +358,8 @@ void fan_tick_func(void)
 		/* Get actual rpm */
 		p_status->rpm_actual = mft_fan_rpm(ch);
 		/* Do smart fan stuff */
-		p_status->auto_status = fan_smart_control(ch,
-				p_status->rpm_actual, p_status->rpm_target);
+		p_status->auto_status = fan_smart_control(
+			ch, p_status->rpm_actual, p_status->rpm_target);
 	}
 }
 DECLARE_HOOK(HOOK_TICK, fan_tick_func, HOOK_PRIO_DEFAULT);
@@ -530,7 +531,7 @@ enum fan_status fan_get_status(int ch)
 int fan_is_stalled(int ch)
 {
 	return fan_get_enabled(ch) && fan_get_duty(ch) &&
-			fan_status[ch].cur_state == TACHO_UNDERFLOW;
+	       fan_status[ch].cur_state == TACHO_UNDERFLOW;
 }
 
 /**
diff --git a/chip/npcx/fan_chip.h b/chip/npcx/fan_chip.h
index 6fc228ec84..36eb13f4cb 100644
--- a/chip/npcx/fan_chip.h
+++ b/chip/npcx/fan_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/npcx/flash.c b/chip/npcx/flash.c
index 768c2ced29..390cb1fa64 100644
--- a/chip/npcx/flash.c
+++ b/chip/npcx/flash.c
@@ -1,10 +1,11 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Flash memory module for Chrome EC */
 
+#include "builtin/assert.h"
 #include "flash.h"
 #include "host_command.h"
 #include "registers.h"
@@ -68,7 +69,7 @@ static void flash_execute_cmd(uint8_t code, uint8_t cts)
 	/* set UMA_CODE */
 	NPCX_UMA_CODE = code;
 	/* execute UMA flash transaction */
-	NPCX_UMA_CTS  = cts;
+	NPCX_UMA_CTS = cts;
 	while (IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE))
 		;
 }
@@ -94,7 +95,7 @@ static int flash_wait_ready(void)
 	flash_execute_cmd(CMD_READ_STATUS_REG, MASK_CMD_ONLY);
 	do {
 		/* Read status register */
-		NPCX_UMA_CTS  = MASK_RD_1BYTE;
+		NPCX_UMA_CTS = MASK_RD_1BYTE;
 		while (IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE))
 			;
 		/* Busy bit is clear */
@@ -316,8 +317,8 @@ static int flash_set_status_for_prot(int reg1, int reg2)
 #endif
 	flash_set_status(reg1, reg2);
 
-	spi_flash_reg_to_protect(reg1, reg2,
-				 &addr_prot_start, &addr_prot_length);
+	spi_flash_reg_to_protect(reg1, reg2, &addr_prot_start,
+				 &addr_prot_length);
 
 	return EC_SUCCESS;
 }
@@ -328,8 +329,8 @@ static int flash_check_prot_range(unsigned int offset, unsigned int bytes)
 	if (offset + bytes > CONFIG_FLASH_SIZE_BYTES)
 		return EC_ERROR_INVAL;
 	/* Check if ranges overlap */
-	if (MAX(addr_prot_start, offset) < MIN(addr_prot_start +
-		addr_prot_length, offset + bytes))
+	if (MAX(addr_prot_start, offset) <
+	    MIN(addr_prot_start + addr_prot_length, offset + bytes))
 		return EC_ERROR_ACCESS_DENIED;
 
 	return EC_SUCCESS;
@@ -369,7 +370,6 @@ static int flash_check_prot_reg(unsigned int offset, unsigned int bytes)
 		return EC_ERROR_ACCESS_DENIED;
 
 	return EC_SUCCESS;
-
 }
 
 static int flash_write_prot_reg(unsigned int offset, unsigned int bytes,
@@ -395,7 +395,7 @@ static int flash_write_prot_reg(unsigned int offset, unsigned int bytes,
 }
 
 static void flash_burst_write(unsigned int dest_addr, unsigned int bytes,
-		const char *data)
+			      const char *data)
 {
 	unsigned int i;
 	/* Chip Select down */
@@ -413,15 +413,17 @@ static void flash_burst_write(unsigned int dest_addr, unsigned int bytes,
 }
 
 static int flash_program_bytes(uint32_t offset, uint32_t bytes,
-	const uint8_t *data)
+			       const uint8_t *data)
 {
 	int write_size;
 	int rv;
 
 	while (bytes > 0) {
 		/* Write length can not go beyond the end of the flash page */
-		write_size = MIN(bytes, CONFIG_FLASH_WRITE_IDEAL_SIZE -
-		(offset & (CONFIG_FLASH_WRITE_IDEAL_SIZE - 1)));
+		write_size = MIN(bytes,
+				 CONFIG_FLASH_WRITE_IDEAL_SIZE -
+					 (offset &
+					  (CONFIG_FLASH_WRITE_IDEAL_SIZE - 1)));
 
 		/* Enable write */
 		rv = flash_write_enable();
@@ -436,9 +438,9 @@ static int flash_program_bytes(uint32_t offset, uint32_t bytes,
 		if (rv)
 			return rv;
 
-		data   += write_size;
+		data += write_size;
 		offset += write_size;
-		bytes  -= write_size;
+		bytes -= write_size;
 	}
 
 	return rv;
@@ -467,7 +469,7 @@ int crec_flash_physical_read(int offset, int size, char *data)
 	/* Burst read transaction */
 	for (idx = 0; idx < size; idx++) {
 		/* 1101 0101 - EXEC, RD, NO CMD, NO ADDR, 4 bytes */
-		NPCX_UMA_CTS  = MASK_RD_1BYTE;
+		NPCX_UMA_CTS = MASK_RD_1BYTE;
 		/* wait for UMA to complete */
 		while (IS_BIT_SET(NPCX_UMA_CTS, EXEC_DONE))
 			;
@@ -493,8 +495,8 @@ int crec_flash_physical_write(int offset, int size, const char *data)
 	int rv;
 
 	/* Fail if offset, size, and data aren't at least word-aligned */
-	if ((offset | size
-	     | (uint32_t)(uintptr_t)data) & (CONFIG_FLASH_WRITE_SIZE - 1))
+	if ((offset | size | (uint32_t)(uintptr_t)data) &
+	    (CONFIG_FLASH_WRITE_SIZE - 1))
 		return EC_ERROR_INVAL;
 
 	/* check protection */
@@ -510,7 +512,8 @@ int crec_flash_physical_write(int offset, int size, const char *data)
 	while (size > 0) {
 		/* First write multiples of 256, then (size % 256) last */
 		write_len = ((size % CONFIG_FLASH_WRITE_IDEAL_SIZE) == size) ?
-					size : CONFIG_FLASH_WRITE_IDEAL_SIZE;
+				    size :
+				    CONFIG_FLASH_WRITE_IDEAL_SIZE;
 
 		/* check protection */
 		if (flash_check_prot_range(dest_addr, write_len)) {
@@ -522,9 +525,9 @@ int crec_flash_physical_write(int offset, int size, const char *data)
 		if (rv)
 			break;
 
-		data      += write_len;
+		data += write_len;
 		dest_addr += write_len;
-		size      -= write_len;
+		size -= write_len;
 	}
 
 	/* Enable tri-state */
@@ -551,7 +554,7 @@ int crec_flash_physical_erase(int offset, int size)
 
 	/* Alignment has been checked in upper layer */
 	for (; size > 0; size -= CONFIG_FLASH_ERASE_SIZE,
-		offset += CONFIG_FLASH_ERASE_SIZE) {
+			 offset += CONFIG_FLASH_ERASE_SIZE) {
 		/* check protection */
 		if (flash_check_prot_range(offset, CONFIG_FLASH_ERASE_SIZE)) {
 			rv = EC_ERROR_ACCESS_DENIED;
@@ -645,7 +648,6 @@ int crec_flash_physical_protect_now(int all)
 	return EC_SUCCESS;
 }
 
-
 int crec_flash_physical_protect_at_boot(uint32_t new_flags)
 {
 	int ret;
@@ -657,8 +659,7 @@ int crec_flash_physical_protect_at_boot(uint32_t new_flags)
 	}
 
 	ret = flash_write_prot_reg(CONFIG_WP_STORAGE_OFF,
-				   CONFIG_WP_STORAGE_SIZE,
-				   1);
+				   CONFIG_WP_STORAGE_SIZE, 1);
 
 	/*
 	 * Set UMA_LOCK bit for locking all UMA transaction.
@@ -672,9 +673,8 @@ int crec_flash_physical_protect_at_boot(uint32_t new_flags)
 
 uint32_t crec_flash_physical_get_valid_flags(void)
 {
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-			EC_FLASH_PROTECT_RO_NOW |
-			EC_FLASH_PROTECT_ALL_NOW;
+	return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW |
+	       EC_FLASH_PROTECT_ALL_NOW;
 }
 
 uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
@@ -690,7 +690,7 @@ uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
 	 * the WP GPIO is asserted.
 	 */
 	if (!(cur_flags & EC_FLASH_PROTECT_ALL_NOW) &&
-			(cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED))
+	    (cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED))
 		ret |= EC_FLASH_PROTECT_ALL_NOW;
 
 	return ret;
@@ -759,8 +759,7 @@ static enum ec_status flash_command_spi_info(struct host_cmd_handler_args *args)
 	args->response_size = sizeof(*r);
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_FLASH_SPI_INFO,
-		     flash_command_spi_info,
+DECLARE_HOST_COMMAND(EC_CMD_FLASH_SPI_INFO, flash_command_spi_info,
 		     EC_VER_MASK(0));
 
 #endif
@@ -788,7 +787,7 @@ static int flash_spi_sel_lock(int enable)
 /*****************************************************************************/
 /* Console commands */
 
-static int command_flash_spi_sel_lock(int argc, char **argv)
+static int command_flash_spi_sel_lock(int argc, const char **argv)
 {
 	int ena;
 
@@ -801,10 +800,9 @@ static int command_flash_spi_sel_lock(int argc, char **argv)
 	return EC_SUCCESS;
 }
 DECLARE_CONSOLE_COMMAND(flash_spi_lock, command_flash_spi_sel_lock,
-			"[on | off]",
-			"Lock spi flash interface selection");
+			"[on | off]", "Lock spi flash interface selection");
 
-static int command_flash_tristate(int argc, char **argv)
+static int command_flash_tristate(int argc, const char **argv)
 {
 	int ena;
 
@@ -817,12 +815,11 @@ static int command_flash_tristate(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(flash_tristate, command_flash_tristate,
-			"[on | off]",
+DECLARE_CONSOLE_COMMAND(flash_tristate, command_flash_tristate, "[on | off]",
 			"Tristate spi flash pins");
 #endif /* CONFIG_CMD_FLASH_TRISTATE */
 
-static int command_flash_chip(int argc, char **argv)
+static int command_flash_chip(int argc, const char **argv)
 {
 	uint8_t jedec_id[3];
 	uint8_t sr1, sr2;
@@ -832,10 +829,9 @@ static int command_flash_chip(int argc, char **argv)
 
 	flash_get_jedec_id(jedec_id);
 	ccprintf("Manufacturer: 0x%02x, DID: 0x%02x%02x\n", jedec_id[0],
-			jedec_id[1], jedec_id[2]);
+		 jedec_id[1], jedec_id[2]);
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(flashchip, command_flash_chip,
-			NULL,
+DECLARE_CONSOLE_COMMAND(flashchip, command_flash_chip, NULL,
 			"Print flash chip info");
diff --git a/chip/npcx/gpio-npcx5.c b/chip/npcx/gpio-npcx5.c
index 6742f19369..2201bb65c2 100644
--- a/chip/npcx/gpio-npcx5.c
+++ b/chip/npcx/gpio-npcx5.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -48,11 +48,11 @@ DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
  * the port, then call the master handler above.
  */
 
-#define GPIO_IRQ_FUNC(_irq_func, wui_int)		\
-static void _irq_func(void)				\
-{							\
-	gpio_interrupt(wui_int);			\
-}
+#define GPIO_IRQ_FUNC(_irq_func, wui_int) \
+	static void _irq_func(void)       \
+	{                                 \
+		gpio_interrupt(wui_int);  \
+	}
 
 /* If we need to handle the other type interrupts except GPIO, add code here */
 static void __gpio_wk0efgh_interrupt(void)
@@ -60,7 +60,7 @@ static void __gpio_wk0efgh_interrupt(void)
 	if (IS_ENABLED(CONFIG_HOSTCMD_X86)) {
 		/* Pending bit 7 or 6 or 5? */
 		if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6) &&
-			IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 6)) {
+		    IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 6)) {
 			/* Disable host wake-up */
 			CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6);
 			/* Clear pending bit of WUI */
@@ -68,16 +68,18 @@ static void __gpio_wk0efgh_interrupt(void)
 			return;
 		}
 		if (IS_ENABLED(CONFIG_HOST_INTERFACE_ESPI)) {
-			if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 5)
-				&&
-			IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 5)) {
+			if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5),
+				       5) &&
+			    IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5),
+				       5)) {
 				espi_espirst_handler();
 				return;
 			}
 		} else {
-			if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 7)
-				&&
-			IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 7)) {
+			if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5),
+				       7) &&
+			    IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5),
+				       7)) {
 				lpc_lreset_pltrst_handler();
 				return;
 			}
@@ -169,30 +171,30 @@ GPIO_IRQ_FUNC(__gpio_wk2fg_interrupt, WUI_INT(MIWU_TABLE_2, MIWU_GROUP_6));
 #endif
 
 DECLARE_IRQ(NPCX_IRQ_MTC_WKINTAD_0, __gpio_rtc_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_TWD_WKINTB_0,  __gpio_wk0b_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTC_0,      __gpio_wk0c_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTEFGH_0,   __gpio_wk0efgh_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTA_1,      __gpio_wk1a_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTB_1,      __gpio_wk1b_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_TWD_WKINTB_0, __gpio_wk0b_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTC_0, __gpio_wk0c_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTEFGH_0, __gpio_wk0efgh_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTA_1, __gpio_wk1a_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTB_1, __gpio_wk1b_interrupt, 3);
 #ifdef NPCX_SELECT_KSI_TO_GPIO
-DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1,  __gpio_wk1c_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1, __gpio_wk1c_interrupt, 3);
 #endif
-DECLARE_IRQ(NPCX_IRQ_WKINTD_1,      __gpio_wk1d_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTE_1,      __gpio_wk1e_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTD_1, __gpio_wk1d_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTE_1, __gpio_wk1e_interrupt, 3);
 #ifdef CONFIG_HOST_INTERFACE_SHI
 /*
  * HACK: Make CS GPIO P2 to improve SHI reliability.
  * TODO: Increase CS-assertion-to-transaction-start delay on host to
  * accommodate P3 CS interrupt.
  */
-DECLARE_IRQ(NPCX_IRQ_WKINTF_1,      __gpio_wk1f_interrupt, 2);
+DECLARE_IRQ(NPCX_IRQ_WKINTF_1, __gpio_wk1f_interrupt, 2);
 #else
-DECLARE_IRQ(NPCX_IRQ_WKINTF_1,      __gpio_wk1f_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTF_1, __gpio_wk1f_interrupt, 3);
 #endif
-DECLARE_IRQ(NPCX_IRQ_WKINTG_1,      __gpio_wk1g_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTH_1,      __gpio_wk1h_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTG_1, __gpio_wk1g_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTH_1, __gpio_wk1h_interrupt, 3);
 #if defined(CHIP_FAMILY_NPCX7)
-DECLARE_IRQ(NPCX_IRQ_WKINTFG_2,     __gpio_wk2fg_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTFG_2, __gpio_wk2fg_interrupt, 3);
 #endif
 
 #undef GPIO_IRQ_FUNC
diff --git a/chip/npcx/gpio-npcx7.c b/chip/npcx/gpio-npcx7.c
index 39b939f44c..2201bb65c2 120000..100644
--- a/chip/npcx/gpio-npcx7.c
+++ b/chip/npcx/gpio-npcx7.c
@@ -1 +1,200 @@
-gpio-npcx5.c
\ No newline at end of file
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* GPIO module for Chrome EC */
+
+#include "clock.h"
+#include "common.h"
+#include "ec_commands.h"
+#include "gpio_chip.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "lpc_chip.h"
+#include "registers.h"
+#include "task.h"
+
+/*
+ * List of GPIO IRQs to enable. Don't automatically enable interrupts for
+ * the keyboard input GPIO bank - that's handled separately. Of course the
+ * bank is different for different systems.
+ */
+static void gpio_init(void)
+{
+	/* Enable IRQs now that pins are set up */
+	task_enable_irq(NPCX_IRQ_MTC_WKINTAD_0);
+	task_enable_irq(NPCX_IRQ_WKINTEFGH_0);
+	task_enable_irq(NPCX_IRQ_WKINTC_0);
+	task_enable_irq(NPCX_IRQ_TWD_WKINTB_0);
+	task_enable_irq(NPCX_IRQ_WKINTA_1);
+	task_enable_irq(NPCX_IRQ_WKINTB_1);
+#ifdef NPCX_SELECT_KSI_TO_GPIO
+	task_enable_irq(NPCX_IRQ_KSI_WKINTC_1);
+#endif
+	task_enable_irq(NPCX_IRQ_WKINTD_1);
+	task_enable_irq(NPCX_IRQ_WKINTE_1);
+	task_enable_irq(NPCX_IRQ_WKINTF_1);
+	task_enable_irq(NPCX_IRQ_WKINTG_1);
+	task_enable_irq(NPCX_IRQ_WKINTH_1);
+#if defined(CHIP_FAMILY_NPCX7)
+	task_enable_irq(NPCX_IRQ_WKINTFG_2);
+#endif
+}
+DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
+
+/**
+ * Handlers for each GPIO port.  These read and clear the interrupt bits for
+ * the port, then call the master handler above.
+ */
+
+#define GPIO_IRQ_FUNC(_irq_func, wui_int) \
+	static void _irq_func(void)       \
+	{                                 \
+		gpio_interrupt(wui_int);  \
+	}
+
+/* If we need to handle the other type interrupts except GPIO, add code here */
+static void __gpio_wk0efgh_interrupt(void)
+{
+	if (IS_ENABLED(CONFIG_HOSTCMD_X86)) {
+		/* Pending bit 7 or 6 or 5? */
+		if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6) &&
+		    IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 6)) {
+			/* Disable host wake-up */
+			CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6);
+			/* Clear pending bit of WUI */
+			SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_5), 6);
+			return;
+		}
+		if (IS_ENABLED(CONFIG_HOST_INTERFACE_ESPI)) {
+			if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5),
+				       5) &&
+			    IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5),
+				       5)) {
+				espi_espirst_handler();
+				return;
+			}
+		} else {
+			if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5),
+				       7) &&
+			    IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5),
+				       7)) {
+				lpc_lreset_pltrst_handler();
+				return;
+			}
+		}
+	}
+	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_5));
+	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_6));
+	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_7));
+	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_8));
+}
+
+#ifdef CONFIG_HOSTCMD_RTC
+static void set_rtc_host_event(void)
+{
+	host_set_single_event(EC_HOST_EVENT_RTC);
+}
+DECLARE_DEFERRED(set_rtc_host_event);
+#endif
+
+static void __gpio_rtc_interrupt(void)
+{
+	/* Check pending bit 7 */
+#ifdef CONFIG_HOSTCMD_RTC
+	if (NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_4) & 0x80) {
+		/* Clear pending bit for WUI */
+		SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_4), 7);
+		hook_call_deferred(&set_rtc_host_event_data, 0);
+		return;
+	}
+#endif
+#if defined(CHIP_FAMILY_NPCX7) && defined(CONFIG_LOW_POWER_IDLE) && \
+	(CONFIG_CONSOLE_UART == 1)
+	/* Handle the interrupt from UART wakeup event */
+	if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_1), 6) &&
+	    IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_1), 6)) {
+		/*
+		 * Disable WKEN bit to avoid the other unnecessary interrupts
+		 * from the coming data bits after the start bit. (Pending bit
+		 * of CR_SIN is set when a high-to-low transaction occurs.)
+		 */
+		CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_1), 6);
+		/* Clear pending bit for WUI */
+		SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_1), 6);
+		/* Notify the clock module that the console is in use. */
+		clock_refresh_console_in_use();
+		return;
+	}
+#endif
+	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_1));
+	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_4));
+}
+
+static void __gpio_wk1h_interrupt(void)
+{
+#if defined(CHIP_FAMILY_NPCX7) && defined(CONFIG_LOW_POWER_IDLE) && \
+	(CONFIG_CONSOLE_UART == 0)
+	/* Handle the interrupt from UART wakeup event */
+	if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_1, MIWU_GROUP_8), 7) &&
+	    IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_1, MIWU_GROUP_8), 7)) {
+		/*
+		 * Disable WKEN bit to avoid the other unnecessary interrupts
+		 * from the coming data bits after the start bit. (Pending bit
+		 * of CR_SIN is set when a high-to-low transaction occurs.)
+		 */
+		CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_1, MIWU_GROUP_8), 7);
+		/* Clear pending bit for WUI */
+		SET_BIT(NPCX_WKPCL(MIWU_TABLE_1, MIWU_GROUP_8), 7);
+		/* Notify the clock module that the console is in use. */
+		clock_refresh_console_in_use();
+	} else
+#endif
+		gpio_interrupt(WUI_INT(MIWU_TABLE_1, MIWU_GROUP_8));
+}
+
+GPIO_IRQ_FUNC(__gpio_wk0b_interrupt, WUI_INT(MIWU_TABLE_0, MIWU_GROUP_2));
+GPIO_IRQ_FUNC(__gpio_wk0c_interrupt, WUI_INT(MIWU_TABLE_0, MIWU_GROUP_3));
+GPIO_IRQ_FUNC(__gpio_wk1a_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_1));
+GPIO_IRQ_FUNC(__gpio_wk1b_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_2));
+#ifdef NPCX_SELECT_KSI_TO_GPIO
+/* Declare GPIO irq functions for KSI pins if there's no keyboard scan task, */
+GPIO_IRQ_FUNC(__gpio_wk1c_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_3));
+#endif
+GPIO_IRQ_FUNC(__gpio_wk1d_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_4));
+GPIO_IRQ_FUNC(__gpio_wk1e_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_5));
+GPIO_IRQ_FUNC(__gpio_wk1f_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_6));
+GPIO_IRQ_FUNC(__gpio_wk1g_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_7));
+#if defined(CHIP_FAMILY_NPCX7)
+GPIO_IRQ_FUNC(__gpio_wk2fg_interrupt, WUI_INT(MIWU_TABLE_2, MIWU_GROUP_6));
+#endif
+
+DECLARE_IRQ(NPCX_IRQ_MTC_WKINTAD_0, __gpio_rtc_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_TWD_WKINTB_0, __gpio_wk0b_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTC_0, __gpio_wk0c_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTEFGH_0, __gpio_wk0efgh_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTA_1, __gpio_wk1a_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTB_1, __gpio_wk1b_interrupt, 3);
+#ifdef NPCX_SELECT_KSI_TO_GPIO
+DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1, __gpio_wk1c_interrupt, 3);
+#endif
+DECLARE_IRQ(NPCX_IRQ_WKINTD_1, __gpio_wk1d_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTE_1, __gpio_wk1e_interrupt, 3);
+#ifdef CONFIG_HOST_INTERFACE_SHI
+/*
+ * HACK: Make CS GPIO P2 to improve SHI reliability.
+ * TODO: Increase CS-assertion-to-transaction-start delay on host to
+ * accommodate P3 CS interrupt.
+ */
+DECLARE_IRQ(NPCX_IRQ_WKINTF_1, __gpio_wk1f_interrupt, 2);
+#else
+DECLARE_IRQ(NPCX_IRQ_WKINTF_1, __gpio_wk1f_interrupt, 3);
+#endif
+DECLARE_IRQ(NPCX_IRQ_WKINTG_1, __gpio_wk1g_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTH_1, __gpio_wk1h_interrupt, 3);
+#if defined(CHIP_FAMILY_NPCX7)
+DECLARE_IRQ(NPCX_IRQ_WKINTFG_2, __gpio_wk2fg_interrupt, 3);
+#endif
+
+#undef GPIO_IRQ_FUNC
diff --git a/chip/npcx/gpio-npcx9.c b/chip/npcx/gpio-npcx9.c
index b567f1d1c8..5de8ea3b0a 100644
--- a/chip/npcx/gpio-npcx9.c
+++ b/chip/npcx/gpio-npcx9.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -51,11 +51,11 @@ DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
  * the port, then call the master handler above.
  */
 
-#define GPIO_IRQ_FUNC(_irq_func, wui_int)		\
-static void _irq_func(void)				\
-{							\
-	gpio_interrupt(wui_int);			\
-}
+#define GPIO_IRQ_FUNC(_irq_func, wui_int) \
+	static void _irq_func(void)       \
+	{                                 \
+		gpio_interrupt(wui_int);  \
+	}
 
 /* If we need to handle the other type interrupts except GPIO, add code here */
 static void __gpio_host_interrupt(void)
@@ -63,7 +63,7 @@ static void __gpio_host_interrupt(void)
 	if (IS_ENABLED(CONFIG_HOSTCMD_X86)) {
 		/* Pending bit 7 or 6 or 5? */
 		if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6) &&
-			IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 6)) {
+		    IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 6)) {
 			/* Disable host wake-up */
 			CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6);
 			/* Clear pending bit of WUI */
@@ -71,16 +71,18 @@ static void __gpio_host_interrupt(void)
 			return;
 		}
 		if (IS_ENABLED(CONFIG_HOST_INTERFACE_ESPI)) {
-			if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 5)
-					&&
-			IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 5)) {
+			if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5),
+				       5) &&
+			    IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5),
+				       5)) {
 				espi_espirst_handler();
 				return;
 			}
 		} else {
-			if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 7)
-					&&
-			IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 7)) {
+			if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5),
+				       7) &&
+			    IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5),
+				       7)) {
 				lpc_lreset_pltrst_handler();
 				return;
 			}
@@ -130,7 +132,6 @@ static void __gpio_cr_sin2_interrupt(void)
 	}
 #endif
 	gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_1));
-
 }
 
 static void __gpio_wk1h_interrupt(void)
@@ -181,32 +182,32 @@ GPIO_IRQ_FUNC(__gpio_wk1f_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_6));
 GPIO_IRQ_FUNC(__gpio_wk1g_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_7));
 
 DECLARE_IRQ(NPCX_IRQ_CR_SIN2_WKINTA_0, __gpio_cr_sin2_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_TWD_WKINTB_0,     __gpio_wk0b_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTC_0,         __gpio_wk0c_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_MTC_WKINTD_0,     __gpio_rtc_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTE_0,         __gpio_host_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTF_0,         __gpio_wk0f_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTG_0,         __gpio_wk0g_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTH_0,         __gpio_wk0h_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTA_1,         __gpio_wk1a_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTB_1,         __gpio_wk1b_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_TWD_WKINTB_0, __gpio_wk0b_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTC_0, __gpio_wk0c_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_MTC_WKINTD_0, __gpio_rtc_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTE_0, __gpio_host_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTF_0, __gpio_wk0f_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTG_0, __gpio_wk0g_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTH_0, __gpio_wk0h_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTA_1, __gpio_wk1a_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTB_1, __gpio_wk1b_interrupt, 3);
 #ifdef NPCX_SELECT_KSI_TO_GPIO
-DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1,     __gpio_wk1c_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1, __gpio_wk1c_interrupt, 3);
 #endif
-DECLARE_IRQ(NPCX_IRQ_WKINTD_1,         __gpio_wk1d_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTE_1,         __gpio_wk1e_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTD_1, __gpio_wk1d_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTE_1, __gpio_wk1e_interrupt, 3);
 #ifdef CONFIG_HOST_INTERFACE_SHI
 /*
  * HACK: Make CS GPIO P2 to improve SHI reliability.
  * TODO: Increase CS-assertion-to-transaction-start delay on host to
  * accommodate P3 CS interrupt.
  */
-DECLARE_IRQ(NPCX_IRQ_WKINTF_1,         __gpio_wk1f_interrupt, 2);
+DECLARE_IRQ(NPCX_IRQ_WKINTF_1, __gpio_wk1f_interrupt, 2);
 #else
-DECLARE_IRQ(NPCX_IRQ_WKINTF_1,         __gpio_wk1f_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTF_1, __gpio_wk1f_interrupt, 3);
 #endif
-DECLARE_IRQ(NPCX_IRQ_WKINTG_1,         __gpio_wk1g_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_WKINTH_1,         __gpio_wk1h_interrupt, 3);
-DECLARE_IRQ(NPCX_IRQ_LCT_WKINTF_2,     __gpio_lct_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTG_1, __gpio_wk1g_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_WKINTH_1, __gpio_wk1h_interrupt, 3);
+DECLARE_IRQ(NPCX_IRQ_LCT_WKINTF_2, __gpio_lct_interrupt, 3);
 
 #undef GPIO_IRQ_FUNC
diff --git a/chip/npcx/gpio.c b/chip/npcx/gpio.c
index 5f1e3c78b6..690615729d 100644
--- a/chip/npcx/gpio.c
+++ b/chip/npcx/gpio.c
@@ -1,10 +1,11 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* GPIO module for Chrome EC */
 
+#include "builtin/assert.h"
 #include "common.h"
 #include "gpio.h"
 #include "gpio_chip.h"
@@ -25,7 +26,7 @@
 #define CPRINTS(...)
 #else
 #define CPUTS(outstr) cputs(CC_GPIO, outstr)
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
 #endif
 
 /* Constants for GPIO interrupt mapping */
@@ -40,12 +41,12 @@
 #define UNIMPLEMENTED(name)
 #endif
 static const struct npcx_wui gpio_wui_table[] = {
-	#include "gpio.wrap"
+#include "gpio.wrap"
 };
 
 struct npcx_gpio {
-	uint8_t port  : 4;
-	uint8_t bit   : 3;
+	uint8_t port : 4;
+	uint8_t bit : 3;
 	uint8_t valid : 1;
 };
 
@@ -54,21 +55,21 @@ BUILD_ASSERT(sizeof(struct npcx_gpio) == 1);
 #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
 struct npcx_alt {
 	uint8_t group;
-	uint8_t bit       : 3;
-	uint8_t inverted  : 1;
-	uint8_t reserved  : 4;
+	uint8_t bit : 3;
+	uint8_t inverted : 1;
+	uint8_t reserved : 4;
 };
 #else
 struct npcx_alt {
-	uint8_t group     : 4;
-	uint8_t bit       : 3;
-	uint8_t inverted  : 1;
+	uint8_t group : 4;
+	uint8_t bit : 3;
+	uint8_t inverted : 1;
 };
 #endif
 
 struct gpio_alt_map {
 	struct npcx_gpio gpio;
-	struct npcx_alt  alt;
+	struct npcx_alt alt;
 };
 
 #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
@@ -101,8 +102,7 @@ static uint8_t gpio_is_alt_sel(uint8_t port, uint8_t bit)
 	struct gpio_alt_map const *map;
 	uint8_t alt_mask, devalt;
 
-	for (map = ARRAY_BEGIN(gpio_alt_table);
-	     map < ARRAY_END(gpio_alt_table);
+	for (map = ARRAY_BEGIN(gpio_alt_table); map < ARRAY_END(gpio_alt_table);
 	     map++) {
 		if (gpio_match(port, bit, map->gpio)) {
 			alt_mask = 1 << map->alt.bit;
@@ -127,8 +127,7 @@ static int gpio_alt_sel(uint8_t port, uint8_t bit,
 {
 	struct gpio_alt_map const *map;
 
-	for (map = ARRAY_BEGIN(gpio_alt_table);
-	     map < ARRAY_END(gpio_alt_table);
+	for (map = ARRAY_BEGIN(gpio_alt_table); map < ARRAY_END(gpio_alt_table);
 	     map++) {
 		if (gpio_match(port, bit, map->gpio)) {
 			uint8_t alt_mask = 1 << map->alt.bit;
@@ -140,7 +139,7 @@ static int gpio_alt_sel(uint8_t port, uint8_t bit,
 			if ((func < GPIO_ALT_FUNC_DEFAULT) ^ map->alt.inverted)
 				NPCX_DEVALT(map->alt.group) &= ~alt_mask;
 			else
-				NPCX_DEVALT(map->alt.group) |=  alt_mask;
+				NPCX_DEVALT(map->alt.group) |= alt_mask;
 
 			return 1;
 		}
@@ -183,7 +182,7 @@ static void gpio_interrupt_type_sel(enum gpio_signal signal, uint32_t flags)
 		NPCX_WKMOD(table, group) &= ~pmask;
 		/* Handle interrupting on both edges */
 		if ((flags & GPIO_INT_F_RISING) &&
-			(flags & GPIO_INT_F_FALLING)) {
+		    (flags & GPIO_INT_F_FALLING)) {
 			/* Enable any edge */
 			NPCX_WKAEDG(table, group) |= pmask;
 		}
@@ -252,7 +251,7 @@ void gpio_low_voltage_level_sel(uint8_t port, uint8_t bit, uint8_t low_voltage)
 
 	if (low_voltage)
 		CPRINTS("Warn! No low voltage support in port:0x%x, bit:%d",
-								port, bit);
+			port, bit);
 }
 
 /* Set the low voltage detection level by mask */
@@ -290,7 +289,7 @@ static void gpio_enable_wake_up_input(enum gpio_signal signal, int enable)
 			SET_BIT(NPCX_WKINEN(wui->table, wui->group), wui->bit);
 		else
 			CLEAR_BIT(NPCX_WKINEN(wui->table, wui->group),
-						wui->bit);
+				  wui->bit);
 	}
 }
 
@@ -317,7 +316,7 @@ BUILD_ASSERT(ARRAY_SIZE(gpio_lvol_table[0].lvol_gpio) == 8);
 /* IC specific low-level driver */
 
 void gpio_set_alternate_function(uint32_t port, uint32_t mask,
-				enum gpio_alternate_func func)
+				 enum gpio_alternate_func func)
 {
 	/* Enable alternative pins by func */
 	int pin;
@@ -340,7 +339,7 @@ void gpio_set_level(enum gpio_signal signal, int value)
 	ASSERT(signal_is_gpio(signal));
 
 	if (value)
-		NPCX_PDOUT(gpio_list[signal].port) |=  gpio_list[signal].mask;
+		NPCX_PDOUT(gpio_list[signal].port) |= gpio_list[signal].mask;
 	else
 		NPCX_PDOUT(gpio_list[signal].port) &= ~gpio_list[signal].mask;
 }
@@ -410,14 +409,14 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
 	if (flags & GPIO_PULL_UP) {
 		if (flags & GPIO_SEL_1P8V) {
 			CPRINTS("Warn! enable internal PU and low voltage mode"
-					" at the same time is illegal. port 0x%x, mask 0x%x",
-					port, mask);
+				" at the same time is illegal. port 0x%x, mask 0x%x",
+				port, mask);
 		} else {
-			NPCX_PPUD(port)  &= ~mask;
+			NPCX_PPUD(port) &= ~mask;
 			NPCX_PPULL(port) |= mask; /* enable pull down/up */
 		}
 	} else if (flags & GPIO_PULL_DOWN) {
-		NPCX_PPUD(port)  |= mask;
+		NPCX_PPUD(port) |= mask;
 		NPCX_PPULL(port) |= mask; /* enable pull down/up */
 	} else {
 		/* No pull up/down */
@@ -455,7 +454,7 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
 	if (flags & GPIO_OUTPUT)
 		NPCX_PDIR(port) |= mask;
 
-	/* Lock GPIO output and configuration if need */
+		/* Lock GPIO output and configuration if need */
 #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
 	if (flags & GPIO_LOCKED)
 		NPCX_PLOCK_CTL(port) |= mask;
@@ -598,7 +597,7 @@ void gpio_pre_init(void)
 		 * which may or may not be as a GPIO.
 		 */
 		gpio_set_alternate_function(g->port, g->mask,
-					GPIO_ALT_FUNC_NONE);
+					    GPIO_ALT_FUNC_NONE);
 	}
 
 	/* The bypass of low voltage IOs for better power consumption */
@@ -649,8 +648,8 @@ void gpio_interrupt(struct npcx_wui wui_int)
 		uint8_t pin_mask = 1 << gpio_wui_table[i].bit;
 
 		if ((gpio_wui_table[i].table == table) &&
-			(gpio_wui_table[i].group == group) &&
-			(wui_mask & pin_mask)) {
+		    (gpio_wui_table[i].group == group) &&
+		    (wui_mask & pin_mask)) {
 			/* Clear pending bit of GPIO */
 			NPCX_WKPCL(table, group) = pin_mask;
 			/* Execute GPIO's ISR */
@@ -671,7 +670,7 @@ void gpio_interrupt(struct npcx_wui wui_int)
  * Command used to disable input buffer of gpios one by one to
  * investigate power consumption
  */
-static int command_gpiodisable(int argc, char **argv)
+static int command_gpiodisable(int argc, const char **argv)
 {
 	uint8_t i;
 	uint8_t offset;
@@ -691,7 +690,7 @@ static int command_gpiodisable(int argc, char **argv)
 
 			ccprintf("Total GPIO declaration: %d\n", GPIO_COUNT);
 			ccprintf("Total Non-ISR GPIO declaration: %d\n",
-						non_isr_gpio_num);
+				 non_isr_gpio_num);
 			ccprintf("Next GPIO Num to check by ");
 			ccprintf("\"gpiodisable next\"\n");
 			ccprintf("  offset: %d\n", offset);
@@ -714,8 +713,8 @@ static int command_gpiodisable(int argc, char **argv)
 				offset = idx + GPIO_IH_COUNT;
 				g_list = gpio_list + offset;
 				flags = g_list->flags;
-				ccprintf("current GPIO : %d %s --> ",
-							offset, g_list->name);
+				ccprintf("current GPIO : %d %s --> ", offset,
+					 g_list->name);
 				if (gpio_is_i2c_pin(offset)) {
 					ccprintf("Ignore I2C pin!\n");
 					idx++;
@@ -726,10 +725,10 @@ static int command_gpiodisable(int argc, char **argv)
 					continue;
 				} else {
 					if ((flags & GPIO_INPUT) ||
-						    (flags & GPIO_OPEN_DRAIN)) {
+					    (flags & GPIO_OPEN_DRAIN)) {
 						ccprintf("Disable WKINEN!\n");
 						gpio_enable_wake_up_input(
-								offset, 0);
+							offset, 0);
 						idx++;
 						break;
 					}
@@ -759,7 +758,7 @@ static int command_gpiodisable(int argc, char **argv)
 	}
 	return EC_ERROR_INVAL;
 }
-DECLARE_CONSOLE_COMMAND(gpiodisable, command_gpiodisable,
-		"info/list/next/<num> on|off",
-		"Disable GPIO input buffer to investigate power consumption");
+DECLARE_CONSOLE_COMMAND(
+	gpiodisable, command_gpiodisable, "info/list/next/<num> on|off",
+	"Disable GPIO input buffer to investigate power consumption");
 #endif
diff --git a/chip/npcx/gpio_chip-npcx5.h b/chip/npcx/gpio_chip-npcx5.h
index 83916a421b..81ef957236 100644
--- a/chip/npcx/gpio_chip-npcx5.h
+++ b/chip/npcx/gpio_chip-npcx5.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -245,7 +245,7 @@
 #define NPCX_ALT_GPIO_B_1 ALT(B, 1, NPCX_ALT_INV(A, NO_KSO17_SL)) /* KSO17 */
 
 /* Clock module */
-#define NPCX_ALT_GPIO_7_5 ALT(7, 5, NPCX_ALT(A, 32K_OUT_SL))  /* 32KHZ_OUT */
+#define NPCX_ALT_GPIO_7_5 ALT(7, 5, NPCX_ALT(A, 32K_OUT_SL)) /* 32KHZ_OUT */
 #define NPCX_ALT_GPIO_E_7 ALT(E, 7, NPCX_ALT(A, 32KCLKIN_SL)) /* 32KCLKIN */
 
 /* PS/2 module */
@@ -261,6 +261,7 @@
 #define NPCX_ALT_GPIO_A_7
 #endif
 
+/* clang-format off */
 #define NPCX_ALT_TABLE { \
 	NPCX_ALT_GPIO_0_3  /* KSO16 */               \
 	NPCX_ALT_GPIO_0_4  /* KSO13 */               \
@@ -331,54 +332,66 @@
 	NPCX_ALT_GPIO_D_1  /* SMB3SCL */             \
 	NPCX_ALT_GPIO_E_7  /* 32KCLKIN */            \
 }
+/* clang-format on */
 
 /*****************************************************************************/
 /* Macro functions for Low-Voltage mapping table */
 
 /* Low-Voltage GPIO Control 0 */
-#define NPCX_LVOL_CTRL_0_0  NPCX_GPIO(B, 5)
-#define NPCX_LVOL_CTRL_0_1  NPCX_GPIO(B, 4)
-#define NPCX_LVOL_CTRL_0_2  NPCX_GPIO(B, 3)
-#define NPCX_LVOL_CTRL_0_3  NPCX_GPIO(B, 2)
-#define NPCX_LVOL_CTRL_0_4  NPCX_GPIO(9, 0)
-#define NPCX_LVOL_CTRL_0_5  NPCX_GPIO(8, 7)
-#define NPCX_LVOL_CTRL_0_6  NPCX_GPIO(0, 0)
-#define NPCX_LVOL_CTRL_0_7  NPCX_GPIO(3, 3)
+#define NPCX_LVOL_CTRL_0_0 NPCX_GPIO(B, 5)
+#define NPCX_LVOL_CTRL_0_1 NPCX_GPIO(B, 4)
+#define NPCX_LVOL_CTRL_0_2 NPCX_GPIO(B, 3)
+#define NPCX_LVOL_CTRL_0_3 NPCX_GPIO(B, 2)
+#define NPCX_LVOL_CTRL_0_4 NPCX_GPIO(9, 0)
+#define NPCX_LVOL_CTRL_0_5 NPCX_GPIO(8, 7)
+#define NPCX_LVOL_CTRL_0_6 NPCX_GPIO(0, 0)
+#define NPCX_LVOL_CTRL_0_7 NPCX_GPIO(3, 3)
 
 /* Low-Voltage GPIO Control 1 */
-#define NPCX_LVOL_CTRL_1_0  NPCX_GPIO(9, 2)
-#define NPCX_LVOL_CTRL_1_1  NPCX_GPIO(9, 1)
-#define NPCX_LVOL_CTRL_1_2  NPCX_GPIO(D, 1)
-#define NPCX_LVOL_CTRL_1_3  NPCX_GPIO(D, 0)
-#define NPCX_LVOL_CTRL_1_4  NPCX_GPIO(3, 6)
-#define NPCX_LVOL_CTRL_1_5  NPCX_GPIO(6, 4)
-#define NPCX_LVOL_CTRL_1_6  NPCX_GPIO(6, 5)
-#define NPCX_LVOL_CTRL_1_7  NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_1_0 NPCX_GPIO(9, 2)
+#define NPCX_LVOL_CTRL_1_1 NPCX_GPIO(9, 1)
+#define NPCX_LVOL_CTRL_1_2 NPCX_GPIO(D, 1)
+#define NPCX_LVOL_CTRL_1_3 NPCX_GPIO(D, 0)
+#define NPCX_LVOL_CTRL_1_4 NPCX_GPIO(3, 6)
+#define NPCX_LVOL_CTRL_1_5 NPCX_GPIO(6, 4)
+#define NPCX_LVOL_CTRL_1_6 NPCX_GPIO(6, 5)
+#define NPCX_LVOL_CTRL_1_7 NPCX_GPIO_NONE
 
 /* Low-Voltage GPIO Control 2 */
-#define NPCX_LVOL_CTRL_2_0  NPCX_GPIO(7, 4)
-#define NPCX_LVOL_CTRL_2_1  NPCX_GPIO(8, 4)
-#define NPCX_LVOL_CTRL_2_2  NPCX_GPIO(8, 5)
-#define NPCX_LVOL_CTRL_2_3  NPCX_GPIO(7, 3)
-#define NPCX_LVOL_CTRL_2_4  NPCX_GPIO(C, 1)
-#define NPCX_LVOL_CTRL_2_5  NPCX_GPIO(C, 7)
-#define NPCX_LVOL_CTRL_2_6  NPCX_GPIO(E, 7)
-#define NPCX_LVOL_CTRL_2_7  NPCX_GPIO(3, 4)
+#define NPCX_LVOL_CTRL_2_0 NPCX_GPIO(7, 4)
+#define NPCX_LVOL_CTRL_2_1 NPCX_GPIO(8, 4)
+#define NPCX_LVOL_CTRL_2_2 NPCX_GPIO(8, 5)
+#define NPCX_LVOL_CTRL_2_3 NPCX_GPIO(7, 3)
+#define NPCX_LVOL_CTRL_2_4 NPCX_GPIO(C, 1)
+#define NPCX_LVOL_CTRL_2_5 NPCX_GPIO(C, 7)
+#define NPCX_LVOL_CTRL_2_6 NPCX_GPIO(E, 7)
+#define NPCX_LVOL_CTRL_2_7 NPCX_GPIO(3, 4)
 
 /* Low-Voltage GPIO Control 3 */
-#define NPCX_LVOL_CTRL_3_0  NPCX_GPIO(C, 6)
-#define NPCX_LVOL_CTRL_3_1  NPCX_GPIO(3, 7)
-#define NPCX_LVOL_CTRL_3_2  NPCX_GPIO(4, 0)
-#define NPCX_LVOL_CTRL_3_3  NPCX_GPIO(7, 1)
-#define NPCX_LVOL_CTRL_3_4  NPCX_GPIO(8, 2)
-#define NPCX_LVOL_CTRL_3_5  NPCX_GPIO(7, 5)
-#define NPCX_LVOL_CTRL_3_6  NPCX_GPIO(8, 0)
-#define NPCX_LVOL_CTRL_3_7  NPCX_GPIO(C, 5)
+#define NPCX_LVOL_CTRL_3_0 NPCX_GPIO(C, 6)
+#define NPCX_LVOL_CTRL_3_1 NPCX_GPIO(3, 7)
+#define NPCX_LVOL_CTRL_3_2 NPCX_GPIO(4, 0)
+#define NPCX_LVOL_CTRL_3_3 NPCX_GPIO(7, 1)
+#define NPCX_LVOL_CTRL_3_4 NPCX_GPIO(8, 2)
+#define NPCX_LVOL_CTRL_3_5 NPCX_GPIO(7, 5)
+#define NPCX_LVOL_CTRL_3_6 NPCX_GPIO(8, 0)
+#define NPCX_LVOL_CTRL_3_7 NPCX_GPIO(C, 5)
 
 /* 4 Low-Voltage Control Groups on npcx5 */
-#define NPCX_LVOL_TABLE { { NPCX_LVOL_CTRL_ITEMS(0), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(1), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(2), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(3), }, }
+#define NPCX_LVOL_TABLE                                  \
+	{                                                \
+		{                                        \
+			NPCX_LVOL_CTRL_ITEMS(0),         \
+		},                                       \
+			{                                \
+				NPCX_LVOL_CTRL_ITEMS(1), \
+			},                               \
+			{                                \
+				NPCX_LVOL_CTRL_ITEMS(2), \
+			},                               \
+			{                                \
+				NPCX_LVOL_CTRL_ITEMS(3), \
+			},                               \
+	}
 
 #endif /* __CROS_EC_GPIO_CHIP_NPCX5_H */
diff --git a/chip/npcx/gpio_chip-npcx7.h b/chip/npcx/gpio_chip-npcx7.h
index 7f815e6d30..39654bc09e 100644
--- a/chip/npcx/gpio_chip-npcx7.h
+++ b/chip/npcx/gpio_chip-npcx7.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -82,7 +82,9 @@
 #define NPCX_WUI_GPIO_F_0 WUI(0, MIWU_GROUP_8, 5)
 #define NPCX_WUI_GPIO_F_3 WUI(0, MIWU_GROUP_8, 6)
 #ifndef NPCX_EXT32K_OSC_SUPPORT
-#define NPCX_WUI_GPIO_E_7 WUI(0, MIWU_GROUP_8, 7) /* Used as CLKIN if support */
+#define NPCX_WUI_GPIO_E_7                                   \
+	WUI(0, MIWU_GROUP_8, 7) /* Used as CLKIN if support \
+				 */
 #endif
 
 /* MIWU1 */
@@ -151,7 +153,9 @@
 #define NPCX_WUI_GPIO_6_3 WUI(1, MIWU_GROUP_7, 3)
 #define NPCX_WUI_GPIO_6_4 WUI(1, MIWU_GROUP_7, 4)
 #ifndef NPCX_EXT32K_OSC_SUPPORT
-#define NPCX_WUI_GPIO_7_1 WUI(1, MIWU_GROUP_7, 7) /* Used as CLKOUT if support*/
+#define NPCX_WUI_GPIO_7_1                            \
+	WUI(1, MIWU_GROUP_7, 7) /* Used as CLKOUT if \
+				   support*/
 #endif
 
 /* Group H: NPCX_IRQ_WKINTH_1 */
@@ -194,7 +198,7 @@
 /* Pin-Mux for PSL/UART2/SMB4_0 */
 #ifdef NPCX_PSL_MODE_SUPPORT
 #if defined(NPCX_SECOND_UART) && (CONFIG_CONSOLE_UART == 1)
-#define NPCX_ALT_GPIO_8_6 ALT(8, 6, NPCX_ALT(A, UART2_SL))  /* CR_SOUT2 */
+#define NPCX_ALT_GPIO_8_6 ALT(8, 6, NPCX_ALT(A, UART2_SL)) /* CR_SOUT2 */
 #define NPCX_ALT_GPIO_8_5 /* Used as PSL_OUT */
 #else
 #define NPCX_ALT_GPIO_8_6 /* No I2CSDA since GPIO85 used as PSL_OUT */
@@ -214,7 +218,7 @@
 /* Pin-Mux for PWM1/SMB6_0 */
 #if NPCX7_PWM1_SEL
 #define NPCX_ALT_GPIO_C_1 /* No I2CSDA since GPIOC2 used as PWM1 */
-#define NPCX_ALT_GPIO_C_2 ALT(C, 2, NPCX_ALT(4, PWM1_SL))   /* PWM1 */
+#define NPCX_ALT_GPIO_C_2 ALT(C, 2, NPCX_ALT(4, PWM1_SL)) /* PWM1 */
 #else
 #define NPCX_ALT_GPIO_C_1 ALT(C, 1, NPCX_ALT(2, I2C6_0_SL)) /* SMB6SDA0 */
 #define NPCX_ALT_GPIO_C_2 ALT(C, 2, NPCX_ALT(2, I2C6_0_SL)) /* SMB6SCL0 */
@@ -289,7 +293,7 @@
 #define NPCX_ALT_GPIO_1_2 ALT(1, 2, NPCX_ALT_INV(8, NO_KSO07_SL)) /* KSO07 */
 /* KSO08 & CR_SOUT */
 #define NPCX_ALT_GPIO_1_1 ALT(1, 1, NPCX_ALT_INV(9, NO_KSO08_SL))
- /* KSO09 & CR_SIN */
+/* KSO09 & CR_SIN */
 #define NPCX_ALT_GPIO_1_0 ALT(1, 0, NPCX_ALT_INV(9, NO_KSO09_SL))
 #define NPCX_ALT_GPIO_0_7 ALT(0, 7, NPCX_ALT_INV(9, NO_KSO10_SL)) /* KSO10 */
 #define NPCX_ALT_GPIO_0_6 ALT(0, 6, NPCX_ALT_INV(9, NO_KSO11_SL)) /* KSO11 */
@@ -309,17 +313,21 @@
 
 /* Pin-Mux for UART2/32KHZ_OUT */
 #if defined(NPCX_SECOND_UART) && (CONFIG_CONSOLE_UART == 1)
-#define NPCX_ALT_GPIO_7_5 ALT(7, 5, NPCX_ALT(A, UART2_SL))    /* CR_SIN2 */
+#define NPCX_ALT_GPIO_7_5 ALT(7, 5, NPCX_ALT(A, UART2_SL)) /* CR_SIN2 */
 #else
-#define NPCX_ALT_GPIO_7_5 ALT(7, 5, NPCX_ALT(A, 32K_OUT_SL))  /* 32KHZ_OUT */
+#define NPCX_ALT_GPIO_7_5 ALT(7, 5, NPCX_ALT(A, 32K_OUT_SL)) /* 32KHZ_OUT */
 #endif
 
 /* PSL module (Optional) */
 #ifdef NPCX_PSL_MODE_SUPPORT
-#define NPCX_ALT_GPIO_D_2 ALT(D, 2, NPCX_ALT_INV(D, NPSL_IN1_SL)) /* PSL_IN1 */
-#define NPCX_ALT_GPIO_0_0 ALT(0, 0, NPCX_ALT_INV(D, NPSL_IN2_SL)) /* PSL_IN2 */
-#define NPCX_ALT_GPIO_0_1 ALT(0, 1, NPCX_ALT(D, PSL_IN3_SL))      /* PSL_IN3 */
-#define NPCX_ALT_GPIO_0_2 ALT(0, 2, NPCX_ALT(D, PSL_IN4_SL))      /* PSL_IN4 */
+#define NPCX_ALT_GPIO_D_2                                  \
+	ALT(D, 2, NPCX_ALT_INV(D, NPSL_IN1_SL)) /* PSL_IN1 \
+						 */
+#define NPCX_ALT_GPIO_0_0                                  \
+	ALT(0, 0, NPCX_ALT_INV(D, NPSL_IN2_SL)) /* PSL_IN2 \
+						 */
+#define NPCX_ALT_GPIO_0_1 ALT(0, 1, NPCX_ALT(D, PSL_IN3_SL)) /* PSL_IN3 */
+#define NPCX_ALT_GPIO_0_2 ALT(0, 2, NPCX_ALT(D, PSL_IN4_SL)) /* PSL_IN4 */
 #else
 #define NPCX_ALT_GPIO_D_2 /* NO PSL in NPCX7mnG series */
 #define NPCX_ALT_GPIO_0_0 /* NO PSL in NPCX7mnG series */
@@ -328,8 +336,8 @@
 #endif
 
 /* WOV module (Optional) */
-#if defined(NPCX_WOV_SUPPORT) && \
-	(defined(CONFIG_AUDIO_CODEC_I2S_RX) || defined(CONFIG_AUDIO_CODEC_WOV))
+#if defined(NPCX_WOV_SUPPORT) && (defined(CONFIG_AUDIO_CODEC_I2S_RX) || \
+				  defined(CONFIG_AUDIO_CODEC_WOV))
 #define NPCX_ALT_GPIO_9_5 /* Disable SPIP module if WOV is supported */
 #define NPCX_ALT_GPIO_A_3 /* Disable SPIP module if WOV is supported */
 #define NPCX_ALT_GPIO_A_1 /* Disable SPIP module if WOV is supported */
@@ -356,6 +364,7 @@
 #define NPCX_ALT_GPIO_9_7
 #endif
 
+/* clang-format off */
 #define NPCX_ALT_TABLE { \
 	NPCX_ALT_GPIO_0_0 /* PSL_IN2 */               \
 	NPCX_ALT_GPIO_0_1 /* PSL_IN3 */               \
@@ -447,90 +456,110 @@
 	NPCX_ALT_GPIO_F_4 /* SMB5SDA1 */              \
 	NPCX_ALT_GPIO_F_5 /* SMB5SCL1 */              \
 }
+/* clang-format on */
 
 /*****************************************************************************/
 /* Macro functions for Low-Voltage mapping table */
 
 /* Low-Voltage GPIO Control 0 */
-#define NPCX_LVOL_CTRL_0_0  NPCX_GPIO(B, 5)
-#define NPCX_LVOL_CTRL_0_1  NPCX_GPIO(B, 4)
-#define NPCX_LVOL_CTRL_0_2  NPCX_GPIO(B, 3)
-#define NPCX_LVOL_CTRL_0_3  NPCX_GPIO(B, 2)
-#define NPCX_LVOL_CTRL_0_4  NPCX_GPIO(9, 0)
-#define NPCX_LVOL_CTRL_0_5  NPCX_GPIO(8, 7)
-#define NPCX_LVOL_CTRL_0_6  NPCX_GPIO(0, 0)
-#define NPCX_LVOL_CTRL_0_7  NPCX_GPIO(3, 3)
+#define NPCX_LVOL_CTRL_0_0 NPCX_GPIO(B, 5)
+#define NPCX_LVOL_CTRL_0_1 NPCX_GPIO(B, 4)
+#define NPCX_LVOL_CTRL_0_2 NPCX_GPIO(B, 3)
+#define NPCX_LVOL_CTRL_0_3 NPCX_GPIO(B, 2)
+#define NPCX_LVOL_CTRL_0_4 NPCX_GPIO(9, 0)
+#define NPCX_LVOL_CTRL_0_5 NPCX_GPIO(8, 7)
+#define NPCX_LVOL_CTRL_0_6 NPCX_GPIO(0, 0)
+#define NPCX_LVOL_CTRL_0_7 NPCX_GPIO(3, 3)
 
 /* Low-Voltage GPIO Control 1 */
-#define NPCX_LVOL_CTRL_1_0  NPCX_GPIO(9, 2)
-#define NPCX_LVOL_CTRL_1_1  NPCX_GPIO(9, 1)
-#define NPCX_LVOL_CTRL_1_2  NPCX_GPIO(D, 1)
-#define NPCX_LVOL_CTRL_1_3  NPCX_GPIO(D, 0)
-#define NPCX_LVOL_CTRL_1_4  NPCX_GPIO(3, 6)
-#define NPCX_LVOL_CTRL_1_5  NPCX_GPIO(6, 4)
-#define NPCX_LVOL_CTRL_1_6  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_1_7  NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_1_0 NPCX_GPIO(9, 2)
+#define NPCX_LVOL_CTRL_1_1 NPCX_GPIO(9, 1)
+#define NPCX_LVOL_CTRL_1_2 NPCX_GPIO(D, 1)
+#define NPCX_LVOL_CTRL_1_3 NPCX_GPIO(D, 0)
+#define NPCX_LVOL_CTRL_1_4 NPCX_GPIO(3, 6)
+#define NPCX_LVOL_CTRL_1_5 NPCX_GPIO(6, 4)
+#define NPCX_LVOL_CTRL_1_6 NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_1_7 NPCX_GPIO_NONE
 
 /* Low-Voltage GPIO Control 2 */
-#define NPCX_LVOL_CTRL_2_0  NPCX_GPIO(7, 4)
+#define NPCX_LVOL_CTRL_2_0 NPCX_GPIO(7, 4)
 #ifdef NPCX_PSL_MODE_SUPPORT
-#define NPCX_LVOL_CTRL_2_1  NPCX_GPIO_NONE /* Remove 1.8V support since PSL */
-#define NPCX_LVOL_CTRL_2_2  NPCX_GPIO_NONE /* Remove 1.8V support since PSL */
+#define NPCX_LVOL_CTRL_2_1 NPCX_GPIO_NONE /* Remove 1.8V support since PSL */
+#define NPCX_LVOL_CTRL_2_2 NPCX_GPIO_NONE /* Remove 1.8V support since PSL */
 #else
-#define NPCX_LVOL_CTRL_2_1  NPCX_GPIO(8, 4)
-#define NPCX_LVOL_CTRL_2_2  NPCX_GPIO(8, 5)
+#define NPCX_LVOL_CTRL_2_1 NPCX_GPIO(8, 4)
+#define NPCX_LVOL_CTRL_2_2 NPCX_GPIO(8, 5)
 #endif
 
-#define NPCX_LVOL_CTRL_2_3  NPCX_GPIO(7, 3)
-#define NPCX_LVOL_CTRL_2_4  NPCX_GPIO(C, 1)
-#define NPCX_LVOL_CTRL_2_5  NPCX_GPIO(C, 7)
+#define NPCX_LVOL_CTRL_2_3 NPCX_GPIO(7, 3)
+#define NPCX_LVOL_CTRL_2_4 NPCX_GPIO(C, 1)
+#define NPCX_LVOL_CTRL_2_5 NPCX_GPIO(C, 7)
 #ifdef NPCX_EXT32K_OSC_SUPPORT
-#define NPCX_LVOL_CTRL_2_6  NPCX_GPIO_NONE /* Remove 1.8V support since CLKIN */
+#define NPCX_LVOL_CTRL_2_6                                \
+	NPCX_GPIO_NONE /* Remove 1.8V support since CLKIN \
+			*/
 #else
-#define NPCX_LVOL_CTRL_2_6  NPCX_GPIO(E, 7)
+#define NPCX_LVOL_CTRL_2_6 NPCX_GPIO(E, 7)
 #endif
-#define NPCX_LVOL_CTRL_2_7  NPCX_GPIO(3, 4)
+#define NPCX_LVOL_CTRL_2_7 NPCX_GPIO(3, 4)
 
 /* Low-Voltage GPIO Control 3 */
-#define NPCX_LVOL_CTRL_3_0  NPCX_GPIO(C, 6)
-#define NPCX_LVOL_CTRL_3_1  NPCX_GPIO(3, 7)
-#define NPCX_LVOL_CTRL_3_2  NPCX_GPIO(4, 0)
+#define NPCX_LVOL_CTRL_3_0 NPCX_GPIO(C, 6)
+#define NPCX_LVOL_CTRL_3_1 NPCX_GPIO(3, 7)
+#define NPCX_LVOL_CTRL_3_2 NPCX_GPIO(4, 0)
 #ifdef NPCX_EXT32K_OSC_SUPPORT
-#define NPCX_LVOL_CTRL_3_3  NPCX_GPIO_NONE /* Remove 1.8V support since CLKOUT*/
+#define NPCX_LVOL_CTRL_3_3                          \
+	NPCX_GPIO_NONE /* Remove 1.8V support since \
+			  CLKOUT*/
 #else
-#define NPCX_LVOL_CTRL_3_3  NPCX_GPIO(7, 1)
+#define NPCX_LVOL_CTRL_3_3 NPCX_GPIO(7, 1)
 #endif
-#define NPCX_LVOL_CTRL_3_4  NPCX_GPIO(8, 2)
-#define NPCX_LVOL_CTRL_3_5  NPCX_GPIO(7, 5)
-#define NPCX_LVOL_CTRL_3_6  NPCX_GPIO(8, 0)
-#define NPCX_LVOL_CTRL_3_7  NPCX_GPIO(C, 5)
+#define NPCX_LVOL_CTRL_3_4 NPCX_GPIO(8, 2)
+#define NPCX_LVOL_CTRL_3_5 NPCX_GPIO(7, 5)
+#define NPCX_LVOL_CTRL_3_6 NPCX_GPIO(8, 0)
+#define NPCX_LVOL_CTRL_3_7 NPCX_GPIO(C, 5)
 
 /* Low-Voltage GPIO Control 4 */
-#define NPCX_LVOL_CTRL_4_0  NPCX_GPIO(8, 6)
-#define NPCX_LVOL_CTRL_4_1  NPCX_GPIO(C, 2)
-#define NPCX_LVOL_CTRL_4_2  NPCX_GPIO(F, 3)
-#define NPCX_LVOL_CTRL_4_3  NPCX_GPIO(F, 2)
-#define NPCX_LVOL_CTRL_4_4  NPCX_GPIO(F, 5)
-#define NPCX_LVOL_CTRL_4_5  NPCX_GPIO(F, 4)
-#define NPCX_LVOL_CTRL_4_6  NPCX_GPIO(E, 4)
-#define NPCX_LVOL_CTRL_4_7  NPCX_GPIO(E, 3)
+#define NPCX_LVOL_CTRL_4_0 NPCX_GPIO(8, 6)
+#define NPCX_LVOL_CTRL_4_1 NPCX_GPIO(C, 2)
+#define NPCX_LVOL_CTRL_4_2 NPCX_GPIO(F, 3)
+#define NPCX_LVOL_CTRL_4_3 NPCX_GPIO(F, 2)
+#define NPCX_LVOL_CTRL_4_4 NPCX_GPIO(F, 5)
+#define NPCX_LVOL_CTRL_4_5 NPCX_GPIO(F, 4)
+#define NPCX_LVOL_CTRL_4_6 NPCX_GPIO(E, 4)
+#define NPCX_LVOL_CTRL_4_7 NPCX_GPIO(E, 3)
 
 /* Low-Voltage GPIO Control 5 */
-#define NPCX_LVOL_CTRL_5_0  NPCX_GPIO(7, 2)
-#define NPCX_LVOL_CTRL_5_1  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_5_2  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_5_3  NPCX_GPIO(5, 0)
-#define NPCX_LVOL_CTRL_5_4  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_5_5  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_5_6  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_5_7  NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_5_0 NPCX_GPIO(7, 2)
+#define NPCX_LVOL_CTRL_5_1 NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_5_2 NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_5_3 NPCX_GPIO(5, 0)
+#define NPCX_LVOL_CTRL_5_4 NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_5_5 NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_5_6 NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_5_7 NPCX_GPIO_NONE
 
 /* 6 Low-Voltage Control Groups on npcx7 */
-#define NPCX_LVOL_TABLE { { NPCX_LVOL_CTRL_ITEMS(0), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(1), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(2), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(3), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(4), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(5), }, }
+#define NPCX_LVOL_TABLE                                  \
+	{                                                \
+		{                                        \
+			NPCX_LVOL_CTRL_ITEMS(0),         \
+		},                                       \
+			{                                \
+				NPCX_LVOL_CTRL_ITEMS(1), \
+			},                               \
+			{                                \
+				NPCX_LVOL_CTRL_ITEMS(2), \
+			},                               \
+			{                                \
+				NPCX_LVOL_CTRL_ITEMS(3), \
+			},                               \
+			{                                \
+				NPCX_LVOL_CTRL_ITEMS(4), \
+			},                               \
+			{                                \
+				NPCX_LVOL_CTRL_ITEMS(5), \
+			},                               \
+	}
 
 #endif /* __CROS_EC_GPIO_CHIP_NPCX7_H */
diff --git a/chip/npcx/gpio_chip-npcx9.h b/chip/npcx/gpio_chip-npcx9.h
index 005a03d83e..aef2f4f044 100644
--- a/chip/npcx/gpio_chip-npcx9.h
+++ b/chip/npcx/gpio_chip-npcx9.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -200,7 +200,7 @@
 /* Pin-Mux for PWM1/SMB6_0 */
 #if NPCX9_PWM1_SEL
 #define NPCX_ALT_GPIO_C_1 /* No I2CSDA since GPIOC2 used as PWM1 */
-#define NPCX_ALT_GPIO_C_2 ALT(C, 2, NPCX_ALT(4, PWM1_SL))   /* PWM1 */
+#define NPCX_ALT_GPIO_C_2 ALT(C, 2, NPCX_ALT(4, PWM1_SL)) /* PWM1 */
 #else
 #define NPCX_ALT_GPIO_C_1 ALT(C, 1, NPCX_ALT(2, I2C6_0_SL)) /* SMB6SDA0 */
 #define NPCX_ALT_GPIO_C_2 ALT(C, 2, NPCX_ALT(2, I2C6_0_SL)) /* SMB6SCL0 */
@@ -219,17 +219,17 @@
 #define NPCX_ALT_GPIO_3_7 ALT(3, 7, NPCX_ALT(F, ADC5_SL)) /* ADC5  */
 #define NPCX_ALT_GPIO_3_4 ALT(3, 4, NPCX_ALT(F, ADC6_SL)) /* ADC6  */
 #endif
-#define NPCX_ALT_GPIO_F_1 ALT(F, 1, NPCX_ALT(F, ADC8_SL))  /* ADC8  */
-#define NPCX_ALT_GPIO_E_1 ALT(E, 1, NPCX_ALT(F, ADC7_SL))  /* ADC7  */
-#define NPCX_ALT_GPIO_F_0 ALT(F, 0, NPCX_ALT(F, ADC9_SL))  /* ADC9  */
+#define NPCX_ALT_GPIO_F_1 ALT(F, 1, NPCX_ALT(F, ADC8_SL)) /* ADC8  */
+#define NPCX_ALT_GPIO_E_1 ALT(E, 1, NPCX_ALT(F, ADC7_SL)) /* ADC7  */
+#define NPCX_ALT_GPIO_F_0 ALT(F, 0, NPCX_ALT(F, ADC9_SL)) /* ADC9  */
 #define NPCX_ALT_GPIO_E_0 ALT(E, 0, NPCX_ALT(F, ADC10_SL)) /* AD10  */
 #define NPCX_ALT_GPIO_C_7 ALT(C, 7, NPCX_ALT(F, ADC11_SL)) /* AD11  */
 
 /* PS/2 Module */
-#define NPCX_ALT_GPIO_6_7 ALT(6, 7, NPCX_ALT(3, PS2_0_SL))  /* PS2_CLK0 */
-#define NPCX_ALT_GPIO_7_0 ALT(7, 0, NPCX_ALT(3, PS2_0_SL))  /* PS2_DATA0 */
-#define NPCX_ALT_GPIO_6_2 ALT(6, 2, NPCX_ALT(3, PS2_1_SL))  /* PS2_CLK1 */
-#define NPCX_ALT_GPIO_6_3 ALT(6, 3, NPCX_ALT(3, PS2_1_SL))  /* PS2_DATA1 */
+#define NPCX_ALT_GPIO_6_7 ALT(6, 7, NPCX_ALT(3, PS2_0_SL)) /* PS2_CLK0 */
+#define NPCX_ALT_GPIO_7_0 ALT(7, 0, NPCX_ALT(3, PS2_0_SL)) /* PS2_DATA0 */
+#define NPCX_ALT_GPIO_6_2 ALT(6, 2, NPCX_ALT(3, PS2_1_SL)) /* PS2_CLK1 */
+#define NPCX_ALT_GPIO_6_3 ALT(6, 3, NPCX_ALT(3, PS2_1_SL)) /* PS2_DATA1 */
 #if defined(CONFIG_PS2) && defined(NPCX_PS2_MODULE_3)
 #define NPCX_ALT_GPIO_A_7 ALT(A, 7, NPCX_ALT(C, PS2_3_SL2)) /* PS2_DAT3 */
 #else
@@ -237,12 +237,19 @@
 #endif
 
 /* UART Module */
-#define NPCX_ALT_GPIO_6_4 ALT(6, 4, NPCX_ALT(J, CR_SIN1_SL2)) /* CR_SIN1_SL2 */
-#define NPCX_ALT_GPIO_6_5 ALT(6, 5, NPCX_ALT(J, CR_SOUT1_SL2))/* CR_SOUT1_SL2 */
-#define NPCX_ALT_GPIO_7_5 ALT(7, 5, NPCX_ALT(J, CR_SIN2_SL))  /* CR_SIN2_SL */
-#define NPCX_ALT_GPIO_8_6 ALT(8, 6, NPCX_ALT(J, CR_SOUT2_SL)) /* CR_SOUT2_SL */
-#define NPCX_ALT_GPIO_D_4 ALT(D, 4, NPCX_ALT(J, CR_SIN3_SL))  /* CR_SIN3_SL */
-#define NPCX_ALT_GPIO_D_6 ALT(D, 6, NPCX_ALT(J, CR_SOUT3_SL)) /* CR_SOUT3_SL */
+#define NPCX_ALT_GPIO_6_4                                  \
+	ALT(6, 4, NPCX_ALT(J, CR_SIN1_SL2)) /* CR_SIN1_SL2 \
+					     */
+#define NPCX_ALT_GPIO_6_5 \
+	ALT(6, 5, NPCX_ALT(J, CR_SOUT1_SL2)) /* CR_SOUT1_SL2 */
+#define NPCX_ALT_GPIO_7_5 ALT(7, 5, NPCX_ALT(J, CR_SIN2_SL)) /* CR_SIN2_SL */
+#define NPCX_ALT_GPIO_8_6                                  \
+	ALT(8, 6, NPCX_ALT(J, CR_SOUT2_SL)) /* CR_SOUT2_SL \
+					     */
+#define NPCX_ALT_GPIO_D_4 ALT(D, 4, NPCX_ALT(J, CR_SIN3_SL)) /* CR_SIN3_SL */
+#define NPCX_ALT_GPIO_D_6                                  \
+	ALT(D, 6, NPCX_ALT(J, CR_SOUT3_SL)) /* CR_SOUT3_SL \
+					     */
 
 /* PWM Module */
 #define NPCX_ALT_GPIO_C_3 ALT(C, 3, NPCX_ALT(4, PWM0_SL)) /* PWM0 */
@@ -282,7 +289,7 @@
 #define NPCX_ALT_GPIO_1_2 ALT(1, 2, NPCX_ALT_INV(8, NO_KSO07_SL)) /* KSO07 */
 /* KSO08 & CR_SOUT */
 #define NPCX_ALT_GPIO_1_1 ALT(1, 1, NPCX_ALT_INV(9, NO_KSO08_SL))
- /* KSO09 & CR_SIN */
+/* KSO09 & CR_SIN */
 #define NPCX_ALT_GPIO_1_0 ALT(1, 0, NPCX_ALT_INV(9, NO_KSO09_SL))
 #define NPCX_ALT_GPIO_0_7 ALT(0, 7, NPCX_ALT_INV(9, NO_KSO10_SL)) /* KSO10 */
 #define NPCX_ALT_GPIO_0_6 ALT(0, 6, NPCX_ALT_INV(9, NO_KSO11_SL)) /* KSO11 */
@@ -294,17 +301,22 @@
 #define NPCX_ALT_GPIO_B_1 ALT(B, 1, NPCX_ALT_INV(A, NO_KSO17_SL)) /* KSO17 */
 
 /* PSL module */
-#define NPCX_ALT_GPIO_D_2 ALT(D, 2, NPCX_ALT_INV(D, NPSL_IN1_SL)) /* PSL_IN1 */
-#define NPCX_ALT_GPIO_0_0 ALT(0, 0, NPCX_ALT_INV(D, NPSL_IN2_SL)) /* PSL_IN2 */
-#define NPCX_ALT_GPIO_0_1 ALT(0, 1, NPCX_ALT(D, PSL_IN3_SL))      /* PSL_IN3 */
-#define NPCX_ALT_GPIO_0_2 ALT(0, 2, NPCX_ALT(D, PSL_IN4_SL))      /* PSL_IN4 */
-#define NPCX_ALT_GPIO_D_7 ALT(D, 7, NPCX_ALT(G, PSL_GPO_SL))      /* PSL_GPO */
+#define NPCX_ALT_GPIO_D_2                                  \
+	ALT(D, 2, NPCX_ALT_INV(D, NPSL_IN1_SL)) /* PSL_IN1 \
+						 */
+#define NPCX_ALT_GPIO_0_0                                  \
+	ALT(0, 0, NPCX_ALT_INV(D, NPSL_IN2_SL)) /* PSL_IN2 \
+						 */
+#define NPCX_ALT_GPIO_0_1 ALT(0, 1, NPCX_ALT(D, PSL_IN3_SL)) /* PSL_IN3 */
+#define NPCX_ALT_GPIO_0_2 ALT(0, 2, NPCX_ALT(D, PSL_IN4_SL)) /* PSL_IN4 */
+#define NPCX_ALT_GPIO_D_7 ALT(D, 7, NPCX_ALT(G, PSL_GPO_SL)) /* PSL_GPO */
 
 /* SPI Module */
 #define NPCX_ALT_GPIO_9_5 ALT(9, 5, NPCX_ALT(0, SPIP_SL)) /* SPIP_MISO */
 #define NPCX_ALT_GPIO_A_3 ALT(A, 3, NPCX_ALT(0, SPIP_SL)) /* SPIP_MOSI */
 #define NPCX_ALT_GPIO_A_1 ALT(A, 1, NPCX_ALT(0, SPIP_SL)) /* SPIP_SCLK */
 
+/* clang-format off */
 #define NPCX_ALT_TABLE { \
 	NPCX_ALT_GPIO_0_0 /* PSL_IN2 */               \
 	NPCX_ALT_GPIO_0_1 /* PSL_IN3 */               \
@@ -395,76 +407,92 @@
 	NPCX_ALT_GPIO_F_4 /* SMB5SDA1 */              \
 	NPCX_ALT_GPIO_F_5 /* SMB5SCL1 */              \
 }
+/* clang-format on */
 
 /*****************************************************************************/
 /* Macro functions for Low-Voltage mapping table */
 
 /* Low-Voltage GPIO Control 0 */
-#define NPCX_LVOL_CTRL_0_0  NPCX_GPIO(B, 5)
-#define NPCX_LVOL_CTRL_0_1  NPCX_GPIO(B, 4)
-#define NPCX_LVOL_CTRL_0_2  NPCX_GPIO(B, 3)
-#define NPCX_LVOL_CTRL_0_3  NPCX_GPIO(B, 2)
-#define NPCX_LVOL_CTRL_0_4  NPCX_GPIO(9, 0)
-#define NPCX_LVOL_CTRL_0_5  NPCX_GPIO(8, 7)
-#define NPCX_LVOL_CTRL_0_6  NPCX_GPIO(0, 0)
-#define NPCX_LVOL_CTRL_0_7  NPCX_GPIO(3, 3)
+#define NPCX_LVOL_CTRL_0_0 NPCX_GPIO(B, 5)
+#define NPCX_LVOL_CTRL_0_1 NPCX_GPIO(B, 4)
+#define NPCX_LVOL_CTRL_0_2 NPCX_GPIO(B, 3)
+#define NPCX_LVOL_CTRL_0_3 NPCX_GPIO(B, 2)
+#define NPCX_LVOL_CTRL_0_4 NPCX_GPIO(9, 0)
+#define NPCX_LVOL_CTRL_0_5 NPCX_GPIO(8, 7)
+#define NPCX_LVOL_CTRL_0_6 NPCX_GPIO(0, 0)
+#define NPCX_LVOL_CTRL_0_7 NPCX_GPIO(3, 3)
 
 /* Low-Voltage GPIO Control 1 */
-#define NPCX_LVOL_CTRL_1_0  NPCX_GPIO(9, 2)
-#define NPCX_LVOL_CTRL_1_1  NPCX_GPIO(9, 1)
-#define NPCX_LVOL_CTRL_1_2  NPCX_GPIO(D, 1)
-#define NPCX_LVOL_CTRL_1_3  NPCX_GPIO(D, 0)
-#define NPCX_LVOL_CTRL_1_4  NPCX_GPIO(3, 6)
-#define NPCX_LVOL_CTRL_1_5  NPCX_GPIO(6, 4)
-#define NPCX_LVOL_CTRL_1_6  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_1_7  NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_1_0 NPCX_GPIO(9, 2)
+#define NPCX_LVOL_CTRL_1_1 NPCX_GPIO(9, 1)
+#define NPCX_LVOL_CTRL_1_2 NPCX_GPIO(D, 1)
+#define NPCX_LVOL_CTRL_1_3 NPCX_GPIO(D, 0)
+#define NPCX_LVOL_CTRL_1_4 NPCX_GPIO(3, 6)
+#define NPCX_LVOL_CTRL_1_5 NPCX_GPIO(6, 4)
+#define NPCX_LVOL_CTRL_1_6 NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_1_7 NPCX_GPIO_NONE
 
 /* Low-Voltage GPIO Control 2 */
-#define NPCX_LVOL_CTRL_2_0  NPCX_GPIO(7, 4)
-#define NPCX_LVOL_CTRL_2_1  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_2_2  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_2_3  NPCX_GPIO(7, 3)
-#define NPCX_LVOL_CTRL_2_4  NPCX_GPIO(C, 1)
-#define NPCX_LVOL_CTRL_2_5  NPCX_GPIO(C, 7)
-#define NPCX_LVOL_CTRL_2_6  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_2_7  NPCX_GPIO(3, 4)
+#define NPCX_LVOL_CTRL_2_0 NPCX_GPIO(7, 4)
+#define NPCX_LVOL_CTRL_2_1 NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_2_2 NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_2_3 NPCX_GPIO(7, 3)
+#define NPCX_LVOL_CTRL_2_4 NPCX_GPIO(C, 1)
+#define NPCX_LVOL_CTRL_2_5 NPCX_GPIO(C, 7)
+#define NPCX_LVOL_CTRL_2_6 NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_2_7 NPCX_GPIO(3, 4)
 
 /* Low-Voltage GPIO Control 3 */
-#define NPCX_LVOL_CTRL_3_0  NPCX_GPIO(C, 6)
-#define NPCX_LVOL_CTRL_3_1  NPCX_GPIO(3, 7)
-#define NPCX_LVOL_CTRL_3_2  NPCX_GPIO(4, 0)
-#define NPCX_LVOL_CTRL_3_3  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_3_4  NPCX_GPIO(8, 2)
-#define NPCX_LVOL_CTRL_3_5  NPCX_GPIO(7, 5)
-#define NPCX_LVOL_CTRL_3_6  NPCX_GPIO(8, 0)
-#define NPCX_LVOL_CTRL_3_7  NPCX_GPIO(C, 5)
+#define NPCX_LVOL_CTRL_3_0 NPCX_GPIO(C, 6)
+#define NPCX_LVOL_CTRL_3_1 NPCX_GPIO(3, 7)
+#define NPCX_LVOL_CTRL_3_2 NPCX_GPIO(4, 0)
+#define NPCX_LVOL_CTRL_3_3 NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_3_4 NPCX_GPIO(8, 2)
+#define NPCX_LVOL_CTRL_3_5 NPCX_GPIO(7, 5)
+#define NPCX_LVOL_CTRL_3_6 NPCX_GPIO(8, 0)
+#define NPCX_LVOL_CTRL_3_7 NPCX_GPIO(C, 5)
 
 /* Low-Voltage GPIO Control 4 */
-#define NPCX_LVOL_CTRL_4_0  NPCX_GPIO(8, 6)
-#define NPCX_LVOL_CTRL_4_1  NPCX_GPIO(C, 2)
-#define NPCX_LVOL_CTRL_4_2  NPCX_GPIO(F, 3)
-#define NPCX_LVOL_CTRL_4_3  NPCX_GPIO(F, 2)
-#define NPCX_LVOL_CTRL_4_4  NPCX_GPIO(F, 5)
-#define NPCX_LVOL_CTRL_4_5  NPCX_GPIO(F, 4)
-#define NPCX_LVOL_CTRL_4_6  NPCX_GPIO(E, 4)
-#define NPCX_LVOL_CTRL_4_7  NPCX_GPIO(E, 3)
+#define NPCX_LVOL_CTRL_4_0 NPCX_GPIO(8, 6)
+#define NPCX_LVOL_CTRL_4_1 NPCX_GPIO(C, 2)
+#define NPCX_LVOL_CTRL_4_2 NPCX_GPIO(F, 3)
+#define NPCX_LVOL_CTRL_4_3 NPCX_GPIO(F, 2)
+#define NPCX_LVOL_CTRL_4_4 NPCX_GPIO(F, 5)
+#define NPCX_LVOL_CTRL_4_5 NPCX_GPIO(F, 4)
+#define NPCX_LVOL_CTRL_4_6 NPCX_GPIO(E, 4)
+#define NPCX_LVOL_CTRL_4_7 NPCX_GPIO(E, 3)
 
 /* Low-Voltage GPIO Control 5 */
-#define NPCX_LVOL_CTRL_5_0  NPCX_GPIO(7, 2)
-#define NPCX_LVOL_CTRL_5_1  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_5_2  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_5_3  NPCX_GPIO(5, 0)
-#define NPCX_LVOL_CTRL_5_4  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_5_5  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_5_6  NPCX_GPIO_NONE
-#define NPCX_LVOL_CTRL_5_7  NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_5_0 NPCX_GPIO(7, 2)
+#define NPCX_LVOL_CTRL_5_1 NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_5_2 NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_5_3 NPCX_GPIO(5, 0)
+#define NPCX_LVOL_CTRL_5_4 NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_5_5 NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_5_6 NPCX_GPIO_NONE
+#define NPCX_LVOL_CTRL_5_7 NPCX_GPIO_NONE
 
 /* 6 Low-Voltage Control Groups on npcx7 */
-#define NPCX_LVOL_TABLE { { NPCX_LVOL_CTRL_ITEMS(0), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(1), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(2), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(3), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(4), }, \
-			  { NPCX_LVOL_CTRL_ITEMS(5), }, }
+#define NPCX_LVOL_TABLE                                  \
+	{                                                \
+		{                                        \
+			NPCX_LVOL_CTRL_ITEMS(0),         \
+		},                                       \
+			{                                \
+				NPCX_LVOL_CTRL_ITEMS(1), \
+			},                               \
+			{                                \
+				NPCX_LVOL_CTRL_ITEMS(2), \
+			},                               \
+			{                                \
+				NPCX_LVOL_CTRL_ITEMS(3), \
+			},                               \
+			{                                \
+				NPCX_LVOL_CTRL_ITEMS(4), \
+			},                               \
+			{                                \
+				NPCX_LVOL_CTRL_ITEMS(5), \
+			},                               \
+	}
 
 #endif /* __CROS_EC_GPIO_CHIP_NPCX9_H */
diff --git a/chip/npcx/gpio_chip.h b/chip/npcx/gpio_chip.h
index 2d0b2b4e9b..5f60cdfb40 100644
--- a/chip/npcx/gpio_chip.h
+++ b/chip/npcx/gpio_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,37 +9,40 @@
 struct npcx_wui {
 	uint8_t table : 2;
 	uint8_t group : 3;
-	uint8_t bit   : 3;
+	uint8_t bit : 3;
 };
 
 /* Macros to initialize the MIWU mapping table. */
 #define NPCX_WUI_GPIO_PIN(port, index) NPCX_WUI_GPIO_##port##_##index
-#define WUI(tbl, grp, idx) ((struct npcx_wui) { .table = tbl, .group = grp, \
-						.bit = idx })
-#define WUI_INT(tbl, grp)  WUI(tbl, grp, 0)
-#define WUI_NONE ((struct npcx_wui) { .table = MIWU_TABLE_COUNT, .group = 0, \
-				      .bit = 0 })
+#define WUI(tbl, grp, idx) \
+	((struct npcx_wui){ .table = tbl, .group = grp, .bit = idx })
+#define WUI_INT(tbl, grp) WUI(tbl, grp, 0)
+#define WUI_NONE \
+	((struct npcx_wui){ .table = MIWU_TABLE_COUNT, .group = 0, .bit = 0 })
 
 /* Macros to initialize the alternative and low voltage mapping table. */
-#define NPCX_GPIO_NONE ((struct npcx_gpio) {.port = 0, .bit = 0, .valid = 0})
-#define NPCX_GPIO(grp, pin) ((struct npcx_gpio) {.port = GPIO_PORT_##grp, \
-							.bit = pin, .valid = 1})
+#define NPCX_GPIO_NONE ((struct npcx_gpio){ .port = 0, .bit = 0, .valid = 0 })
+#define NPCX_GPIO(grp, pin) \
+	((struct npcx_gpio){ .port = GPIO_PORT_##grp, .bit = pin, .valid = 1 })
 
-#define NPCX_ALT(grp, pin) ((struct npcx_alt) {.group = ALT_GROUP_##grp, \
-			.bit = NPCX_DEVALT##grp##_##pin, .inverted = 0 })
-#define NPCX_ALT_INV(grp, pin) ((struct npcx_alt) {.group = ALT_GROUP_##grp, \
-			.bit = NPCX_DEVALT##grp##_##pin, .inverted = 1 })
-#define ALT(port, index, _alt) { .gpio = NPCX_GPIO(port, index), \
-			.alt = (_alt) },
+#define NPCX_ALT(grp, pin)                                   \
+	((struct npcx_alt){ .group = ALT_GROUP_##grp,        \
+			    .bit = NPCX_DEVALT##grp##_##pin, \
+			    .inverted = 0 })
+#define NPCX_ALT_INV(grp, pin)                               \
+	((struct npcx_alt){ .group = ALT_GROUP_##grp,        \
+			    .bit = NPCX_DEVALT##grp##_##pin, \
+			    .inverted = 1 })
+#define ALT(port, index, _alt) \
+	{ .gpio = NPCX_GPIO(port, index), .alt = (_alt) },
 
-#define NPCX_LVOL_CTRL_ITEMS(ctrl) { NPCX_LVOL_CTRL_##ctrl##_0, \
-				     NPCX_LVOL_CTRL_##ctrl##_1, \
-				     NPCX_LVOL_CTRL_##ctrl##_2, \
-				     NPCX_LVOL_CTRL_##ctrl##_3, \
-				     NPCX_LVOL_CTRL_##ctrl##_4, \
-				     NPCX_LVOL_CTRL_##ctrl##_5, \
-				     NPCX_LVOL_CTRL_##ctrl##_6, \
-				     NPCX_LVOL_CTRL_##ctrl##_7, }
+#define NPCX_LVOL_CTRL_ITEMS(ctrl)                                            \
+	{                                                                     \
+		NPCX_LVOL_CTRL_##ctrl##_0, NPCX_LVOL_CTRL_##ctrl##_1,         \
+			NPCX_LVOL_CTRL_##ctrl##_2, NPCX_LVOL_CTRL_##ctrl##_3, \
+			NPCX_LVOL_CTRL_##ctrl##_4, NPCX_LVOL_CTRL_##ctrl##_5, \
+			NPCX_LVOL_CTRL_##ctrl##_6, NPCX_LVOL_CTRL_##ctrl##_7, \
+	}
 
 /**
  * Switch NPCX UART pins back to normal GPIOs.
diff --git a/chip/npcx/header.c b/chip/npcx/header.c
index 0ba3ee59d6..2db7d9094c 100644
--- a/chip/npcx/header.c
+++ b/chip/npcx/header.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,59 +16,60 @@
 #include "registers.h"
 
 /* Signature used by fw header */
-#define SIG_FW_EC           0x2A3B4D5E
+#define SIG_FW_EC 0x2A3B4D5E
 
 /* Definition used by error detection configuration */
-#define CHECK_CRC	    0x00
-#define CHECK_CHECKSUM	    0x01
-#define ERROR_DETECTION_EN  0x02
+#define CHECK_CRC 0x00
+#define CHECK_CHECKSUM 0x01
+#define ERROR_DETECTION_EN 0x02
 #define ERROR_DETECTION_DIS 0x00
 
 /* Code RAM addresses use by header */
 /* Put FW at the begin of CODE RAM */
-#define FW_START_ADDR  CONFIG_PROGRAM_MEMORY_BASE
+#define FW_START_ADDR CONFIG_PROGRAM_MEMORY_BASE
 
 /* TODO: It will be filled automatically by ECST */
 /* The entry point of reset handler (filled by ECST tool)*/
-#define FW_ENTRY_ADDR  0x100A8169
+#define FW_ENTRY_ADDR 0x100A8169
 
 /* Error detection addresses use by header (A offset relative to flash image) */
-#define ERRCHK_START_ADDR  0x0
-#define ERRCHK_END_ADDR    0x0
+#define ERRCHK_START_ADDR 0x0
+#define ERRCHK_END_ADDR 0x0
 
 /* Firmware Size -> Booter loads RO region after hard reset (16 bytes aligned)*/
-#define FW_SIZE            CONFIG_RO_SIZE
+#define FW_SIZE CONFIG_RO_SIZE
 
 /* FW Header used by NPCX5M5G Booter */
 struct __packed fw_header_t {
-	uint32_t anchor;         /* A constant used to verify FW header       */
-	uint16_t ext_anchor;     /* Enable/disable firmware header CRC check  */
-	uint8_t  spi_max_freq;   /* Spi maximum allowable clock frequency     */
-	uint8_t  spi_read_mode;  /* Spi read mode used for firmware loading   */
-	uint8_t  cfg_err_detect; /* FW load error detection configuration     */
-	uint32_t fw_load_addr;   /* Firmware load start address               */
-	uint32_t fw_entry;       /* Firmware entry point                      */
+	uint32_t anchor; /* A constant used to verify FW header       */
+	uint16_t ext_anchor; /* Enable/disable firmware header CRC check  */
+	uint8_t spi_max_freq; /* Spi maximum allowable clock frequency     */
+	uint8_t spi_read_mode; /* Spi read mode used for firmware loading   */
+	uint8_t cfg_err_detect; /* FW load error detection configuration     */
+	uint32_t fw_load_addr; /* Firmware load start address               */
+	uint32_t fw_entry; /* Firmware entry point                      */
 	uint32_t err_detect_start_addr; /* FW error detect start address      */
-	uint32_t err_detect_end_addr;   /* FW error detect end address        */
-	uint32_t fw_length;      /* Firmware length in bytes                  */
-	uint8_t  flash_size;     /* Indicate SPI flash size                   */
-	uint8_t  reserved[26];   /* Reserved bytes                            */
-	uint32_t sig_header;     /* The CRC signature of the firmware header  */
-	uint32_t sig_fw_image;   /* The CRC or Checksum of the firmware image */
+	uint32_t err_detect_end_addr; /* FW error detect end address        */
+	uint32_t fw_length; /* Firmware length in bytes                  */
+	uint8_t flash_size; /* Indicate SPI flash size                   */
+	uint8_t reserved[26]; /* Reserved bytes                            */
+	uint32_t sig_header; /* The CRC signature of the firmware header  */
+	uint32_t sig_fw_image; /* The CRC or Checksum of the firmware image */
 } __aligned(1);
 
-__keep  __attribute__ ((section(".header")))
+__keep __attribute__((section(".header")))
 const struct fw_header_t fw_header = {
 	/* 00 */ SIG_FW_EC,
 	/* 04 */ 0x54E1, /* Header CRC check Enable/Disable -> AB1Eh/54E1h    */
-	/* 06 */ 0x04,   /* 20/25/33/40/50 MHz -> 00/01/02/03/04h             */
-	/* 07 */ 0x03,   /* Normal/Fast/Rev/D_IO/Q_IO Mode -> 00/01/02/03/04h */
-	/* 08 */ 0x00,   /* Disable CRC check functionality */
+	/* 06 */ 0x04, /* 20/25/33/40/50 MHz -> 00/01/02/03/04h             */
+	/* 07 */ 0x03, /* Normal/Fast/Rev/D_IO/Q_IO Mode -> 00/01/02/03/04h */
+	/* 08 */ 0x00, /* Disable CRC check functionality */
 	/* 09 */ FW_START_ADDR,
-	/* 0D */ FW_ENTRY_ADDR,/* Filling by ECST tool with -usearmrst option */
+	/* 0D */ FW_ENTRY_ADDR, /* Filling by ECST tool with -usearmrst option
+				 */
 	/* 11 */ ERRCHK_START_ADDR,
 	/* 15 */ ERRCHK_END_ADDR,
-	/* 19 */ FW_SIZE,/* Filling by ECST tool */
-	/* 1D */ 0x0F,   /* Flash Size 1/2/4/8/16 Mbytes -> 01/03/07/0F/1Fh   */
+	/* 19 */ FW_SIZE, /* Filling by ECST tool */
+	/* 1D */ 0x0F, /* Flash Size 1/2/4/8/16 Mbytes -> 01/03/07/0F/1Fh   */
 	/* 1E-3F Other fields are filled by ECST tool or reserved         */
 };
diff --git a/chip/npcx/hwtimer.c b/chip/npcx/hwtimer.c
index b479f237c0..dfa06f69b2 100644
--- a/chip/npcx/hwtimer.c
+++ b/chip/npcx/hwtimer.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,10 +19,10 @@
 #include "util.h"
 
 /* Depth of event timer */
-#define TICK_EVT_DEPTH         16 /* Depth of event timer Unit: bits */
-#define TICK_EVT_INTERVAL      BIT(TICK_EVT_DEPTH) /* Unit: us */
+#define TICK_EVT_DEPTH 16 /* Depth of event timer Unit: bits */
+#define TICK_EVT_INTERVAL BIT(TICK_EVT_DEPTH) /* Unit: us */
 #define TICK_EVT_INTERVAL_MASK (TICK_EVT_INTERVAL - 1) /* Mask of interval */
-#define TICK_EVT_MAX_CNT     (TICK_EVT_INTERVAL - 1) /* Maximum event counter */
+#define TICK_EVT_MAX_CNT (TICK_EVT_INTERVAL - 1) /* Maximum event counter */
 
 /* Time when event will be expired unit:us */
 static volatile uint32_t evt_expired_us;
@@ -39,7 +39,7 @@ static volatile uint32_t cur_cnt_us_dbg;
 #define CPRINTS(...)
 #else
 #define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args)
 #endif
 
 /*****************************************************************************/
@@ -48,7 +48,7 @@ void init_hw_timer(int itim_no, enum ITIM_SOURCE_CLOCK_T source)
 {
 	/* Select which clock to use for this timer */
 	UPDATE_BIT(NPCX_ITCTS(itim_no), NPCX_ITCTS_CKSEL,
-			source != ITIM_SOURCE_CLOCK_APB2);
+		   source != ITIM_SOURCE_CLOCK_APB2);
 
 	/* Clear timeout status */
 	SET_BIT(NPCX_ITCTS(itim_no), NPCX_ITCTS_TO_STS);
@@ -64,8 +64,8 @@ void init_hw_timer(int itim_no, enum ITIM_SOURCE_CLOCK_T source)
 /* HWTimer event handlers */
 void __hw_clock_event_set(uint32_t deadline)
 {
-	fp_t inv_evt_tick = FLOAT_TO_FP(INT_32K_CLOCK/(float)SECOND);
-	int32_t  evt_cnt_us;
+	fp_t inv_evt_tick = FLOAT_TO_FP(INT_32K_CLOCK / (float)SECOND);
+	int32_t evt_cnt_us;
 	/* Is deadline min value? */
 	if (evt_expired_us != 0 && evt_expired_us < deadline)
 		return;
@@ -87,10 +87,10 @@ void __hw_clock_event_set(uint32_t deadline)
 	 * ITIM count down : event expired : Unit: 1/32768 sec
 	 * It must exceed evt_expired_us for process_timers function
 	 */
-	evt_cnt = FP_TO_INT((fp_inter_t)(evt_cnt_us) * inv_evt_tick);
+	evt_cnt = FP_TO_INT((fp_inter_t)(evt_cnt_us)*inv_evt_tick);
 	if (evt_cnt > TICK_EVT_MAX_CNT) {
-		CPRINTS("Event overflow! 0x%08x, us is %d",
-				evt_cnt, evt_cnt_us);
+		CPRINTS("Event overflow! 0x%08x, us is %d", evt_cnt,
+			evt_cnt_us);
 		evt_cnt = TICK_EVT_MAX_CNT;
 	}
 
@@ -136,16 +136,17 @@ uint16_t __hw_clock_event_count(void)
 /* Returns time delay cause of deep idle */
 uint32_t __hw_clock_get_sleep_time(uint16_t pre_evt_cnt)
 {
-	fp_t evt_tick = FLOAT_TO_FP(SECOND/(float)INT_32K_CLOCK);
+	fp_t evt_tick = FLOAT_TO_FP(SECOND / (float)INT_32K_CLOCK);
 	uint32_t sleep_time;
 	uint16_t cnt = __hw_clock_event_count();
 
 	/* Event has been triggered but timer ISR doesn't handle it */
 	if (IS_BIT_SET(NPCX_ITCTS(ITIM_EVENT_NO), NPCX_ITCTS_TO_STS))
-		sleep_time = FP_TO_INT((fp_inter_t)(pre_evt_cnt+1) * evt_tick);
+		sleep_time =
+			FP_TO_INT((fp_inter_t)(pre_evt_cnt + 1) * evt_tick);
 	/* Event hasn't been triggered */
 	else
-		sleep_time = FP_TO_INT((fp_inter_t)(pre_evt_cnt+1 - cnt) *
+		sleep_time = FP_TO_INT((fp_inter_t)(pre_evt_cnt + 1 - cnt) *
 				       evt_tick);
 
 	return sleep_time;
@@ -194,7 +195,6 @@ static void __hw_clock_event_irq(void)
 	if (evt_expired_us == 0)
 		__hw_clock_event_set(EVT_MAX_EXPIRED_US);
 #endif
-
 }
 DECLARE_IRQ(ITIM_INT(ITIM_EVENT_NO), __hw_clock_event_irq, 3);
 
@@ -295,10 +295,9 @@ static void update_prescaler(void)
 	 * Ttick_unit = (PRE_8+1) * Tapb2_clk
 	 * PRE_8 = (Ttick_unit/Tapb2_clk) -1
 	 */
-	NPCX_ITPRE(ITIM_SYSTEM_NO)  = (clock_get_apb2_freq() / SECOND) - 1;
+	NPCX_ITPRE(ITIM_SYSTEM_NO) = (clock_get_apb2_freq() / SECOND) - 1;
 	/* Set event tick unit = 1/32768 sec */
 	NPCX_ITPRE(ITIM_EVENT_NO) = 0;
-
 }
 DECLARE_HOOK(HOOK_FREQ_CHANGE, update_prescaler, HOOK_PRIO_DEFAULT);
 
@@ -311,10 +310,10 @@ void __hw_early_init_hwtimer(uint32_t start_t)
 
 	/* Enable clock for ITIM peripheral */
 	clock_enable_peripheral(CGC_OFFSET_TIMER, CGC_TIMER_MASK,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
+				CGC_MODE_RUN | CGC_MODE_SLEEP);
 
 	/* init tick & event timer first */
-	init_hw_timer(ITIM_SYSTEM_NO,  ITIM_SOURCE_CLOCK_APB2);
+	init_hw_timer(ITIM_SYSTEM_NO, ITIM_SOURCE_CLOCK_APB2);
 	init_hw_timer(ITIM_EVENT_NO, ITIM_SOURCE_CLOCK_32K);
 
 	/* Set initial prescaler */
diff --git a/chip/npcx/hwtimer_chip.h b/chip/npcx/hwtimer_chip.h
index 987f3b52bd..7964d9619b 100644
--- a/chip/npcx/hwtimer_chip.h
+++ b/chip/npcx/hwtimer_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,14 +9,14 @@
 #define __CROS_EC_HWTIMER_CHIP_H
 
 /* Use ITIM32 as main hardware timer */
-#define TICK_ITIM32_MAX_CNT  0xFFFFFFFF
+#define TICK_ITIM32_MAX_CNT 0xFFFFFFFF
 /* Maximum deadline of event */
-#define EVT_MAX_EXPIRED_US   TICK_ITIM32_MAX_CNT
+#define EVT_MAX_EXPIRED_US TICK_ITIM32_MAX_CNT
 
 /* Clock source for ITIM16 */
 enum ITIM_SOURCE_CLOCK_T {
 	ITIM_SOURCE_CLOCK_APB2 = 0,
-	ITIM_SOURCE_CLOCK_32K  = 1,
+	ITIM_SOURCE_CLOCK_32K = 1,
 };
 
 /**
diff --git a/chip/npcx/i2c-npcx5.c b/chip/npcx/i2c-npcx5.c
index 89b5ec8072..ef04b447c6 100644
--- a/chip/npcx/i2c-npcx5.c
+++ b/chip/npcx/i2c-npcx5.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -32,7 +32,7 @@ void i2c_select_port(int port)
 
 	/* Select IO pins for multi-ports I2C controllers */
 	UPDATE_BIT(NPCX_GLUE_SMBSEL, NPCX_SMBSEL_SMB0SEL,
-			(port == NPCX_I2C_PORT0_1));
+		   (port == NPCX_I2C_PORT0_1));
 }
 
 int i2c_is_raw_mode(int port)
diff --git a/chip/npcx/i2c-npcx7.c b/chip/npcx/i2c-npcx7.c
index 3f27aff49e..427b9cae9f 100644
--- a/chip/npcx/i2c-npcx7.c
+++ b/chip/npcx/i2c-npcx7.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -37,13 +37,13 @@ void i2c_select_port(int port)
 	/* Select I2C ports for the same controller */
 	else if (port <= NPCX_I2C_PORT4_1) {
 		UPDATE_BIT(NPCX_GLUE_SMBSEL, NPCX_SMBSEL_SMB4SEL,
-			(port == NPCX_I2C_PORT4_1));
+			   (port == NPCX_I2C_PORT4_1));
 	} else if (port <= NPCX_I2C_PORT5_1) {
 		UPDATE_BIT(NPCX_GLUE_SMBSEL, NPCX_SMBSEL_SMB5SEL,
-			(port == NPCX_I2C_PORT5_1));
+			   (port == NPCX_I2C_PORT5_1));
 	} else {
 		UPDATE_BIT(NPCX_GLUE_SMBSEL, NPCX_SMBSEL_SMB6SEL,
-			(port == NPCX_I2C_PORT6_1));
+			   (port == NPCX_I2C_PORT6_1));
 	}
 }
 
@@ -52,7 +52,7 @@ int i2c_is_raw_mode(int port)
 	int group, bit;
 
 	if (port == NPCX_I2C_PORT4_1 || port == NPCX_I2C_PORT5_1 ||
-			port == NPCX_I2C_PORT6_1) {
+	    port == NPCX_I2C_PORT6_1) {
 		group = 6;
 		bit = 7 - (port - NPCX_I2C_PORT4_1) / 2;
 	} else {
diff --git a/chip/npcx/i2c-npcx9.c b/chip/npcx/i2c-npcx9.c
index b1b16a3198..427b9cae9f 120000..100644
--- a/chip/npcx/i2c-npcx9.c
+++ b/chip/npcx/i2c-npcx9.c
@@ -1 +1,70 @@
-i2c-npcx7.c
\ No newline at end of file
+/* Copyright 2017 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* I2C module driver depends on chip series for Chrome EC */
+
+#include "common.h"
+#include "i2c.h"
+#include "i2c_chip.h"
+#include "registers.h"
+#include "util.h"
+
+/*****************************************************************************/
+/* IC specific low-level driver depends on chip series */
+
+int i2c_port_to_controller(int port)
+{
+	if (port < 0 || port >= I2C_PORT_COUNT)
+		return -1;
+
+	if (port <= NPCX_I2C_PORT3_0)
+		return port;
+#ifndef NPCX_PSL_MODE_SUPPORT
+	else if (port == NPCX_I2C_PORT4_0)
+		return 4;
+#endif
+	else /* If port >= NPCX_I2C_PORT4_1 */
+		return 4 + ((port - NPCX_I2C_PORT4_1 + 1) / 2);
+}
+
+void i2c_select_port(int port)
+{
+	/* Only I2C 4/5/6 have multiple ports in series npcx7 */
+	if (port <= NPCX_I2C_PORT3_0 || port >= NPCX_I2C_PORT7_0)
+		return;
+	/* Select I2C ports for the same controller */
+	else if (port <= NPCX_I2C_PORT4_1) {
+		UPDATE_BIT(NPCX_GLUE_SMBSEL, NPCX_SMBSEL_SMB4SEL,
+			   (port == NPCX_I2C_PORT4_1));
+	} else if (port <= NPCX_I2C_PORT5_1) {
+		UPDATE_BIT(NPCX_GLUE_SMBSEL, NPCX_SMBSEL_SMB5SEL,
+			   (port == NPCX_I2C_PORT5_1));
+	} else {
+		UPDATE_BIT(NPCX_GLUE_SMBSEL, NPCX_SMBSEL_SMB6SEL,
+			   (port == NPCX_I2C_PORT6_1));
+	}
+}
+
+int i2c_is_raw_mode(int port)
+{
+	int group, bit;
+
+	if (port == NPCX_I2C_PORT4_1 || port == NPCX_I2C_PORT5_1 ||
+	    port == NPCX_I2C_PORT6_1) {
+		group = 6;
+		bit = 7 - (port - NPCX_I2C_PORT4_1) / 2;
+	} else {
+		group = 2;
+		if (port <= NPCX_I2C_PORT3_0)
+			bit = 2 * port;
+		else
+			bit = I2C_PORT_COUNT - port;
+	}
+
+	if (IS_BIT_SET(NPCX_DEVALT(group), bit))
+		return 0;
+	else
+		return 1;
+}
diff --git a/chip/npcx/i2c.c b/chip/npcx/i2c.c
index a7c389f1b3..ebfba26c58 100644
--- a/chip/npcx/i2c.c
+++ b/chip/npcx/i2c.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,8 +24,8 @@
 #define CPRINTF(...)
 #else
 #define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args)
 #endif
 
 /* Timeout for device should be available after reset (SMBus spec. unit:ms) */
@@ -41,54 +41,54 @@
  * I2C module that supports FIFO mode has 32 bytes Tx FIFO and
  * 32 bytes Rx FIFO.
  */
-#define NPCX_I2C_FIFO_MAX_SIZE    32
+#define NPCX_I2C_FIFO_MAX_SIZE 32
 
 /* Macro functions of I2C */
 #define I2C_START(ctrl) SET_BIT(NPCX_SMBCTL1(ctrl), NPCX_SMBCTL1_START)
-#define I2C_STOP(ctrl)  SET_BIT(NPCX_SMBCTL1(ctrl), NPCX_SMBCTL1_STOP)
-#define I2C_NACK(ctrl)  SET_BIT(NPCX_SMBCTL1(ctrl), NPCX_SMBCTL1_ACK)
+#define I2C_STOP(ctrl) SET_BIT(NPCX_SMBCTL1(ctrl), NPCX_SMBCTL1_STOP)
+#define I2C_NACK(ctrl) SET_BIT(NPCX_SMBCTL1(ctrl), NPCX_SMBCTL1_ACK)
 /* I2C module automatically stall bus after sending peripheral address */
 #define I2C_STALL(ctrl) SET_BIT(NPCX_SMBCTL1(ctrl), NPCX_SMBCTL1_STASTRE)
 #define I2C_WRITE_BYTE(ctrl, data) (NPCX_SMBSDA(ctrl) = data)
-#define I2C_READ_BYTE(ctrl, data)  (data = NPCX_SMBSDA(ctrl))
+#define I2C_READ_BYTE(ctrl, data) (data = NPCX_SMBSDA(ctrl))
 #define I2C_TX_FIFO_OCCUPIED(ctrl) (NPCX_SMBTXF_STS(ctrl) & 0x3F)
 #define I2C_TX_FIFO_AVAILABLE(ctrl) \
-		(NPCX_I2C_FIFO_MAX_SIZE - I2C_TX_FIFO_OCCUPIED(ctrl))
+	(NPCX_I2C_FIFO_MAX_SIZE - I2C_TX_FIFO_OCCUPIED(ctrl))
 
 #define I2C_RX_FIFO_OCCUPIED(ctrl) (NPCX_SMBRXF_STS(ctrl) & 0x3F)
 #define I2C_RX_FIFO_AVAILABLE(ctrl) \
-			(NPCX_I2C_FIFO_MAX_SIZE - I2C_RX_FIFO_OCCUPIED(ctrl))
+	(NPCX_I2C_FIFO_MAX_SIZE - I2C_RX_FIFO_OCCUPIED(ctrl))
 /* Drive the SCL signal to low */
-#define I2C_SCL_STALL(ctrl) \
-		(NPCX_SMBCTL3(ctrl) = \
-			(NPCX_SMBCTL3(ctrl) & ~BIT(NPCX_SMBCTL3_SCL_LVL)) | \
-			 BIT(NPCX_SMBCTL3_SDA_LVL))
+#define I2C_SCL_STALL(ctrl)                                          \
+	(NPCX_SMBCTL3(ctrl) =                                        \
+		 (NPCX_SMBCTL3(ctrl) & ~BIT(NPCX_SMBCTL3_SCL_LVL)) | \
+		 BIT(NPCX_SMBCTL3_SDA_LVL))
 /*
  * Release the SCL signal to be pulled up to high level.
  * Note: The SCL might be still driven low either by I2C module or external
  * devices connected to ths bus.
  */
-#define I2C_SCL_FREE(ctrl) \
-		(NPCX_SMBCTL3(ctrl) |= BIT(NPCX_SMBCTL3_SCL_LVL) | \
-			 BIT(NPCX_SMBCTL3_SDA_LVL))
+#define I2C_SCL_FREE(ctrl)                                 \
+	(NPCX_SMBCTL3(ctrl) |= BIT(NPCX_SMBCTL3_SCL_LVL) | \
+			       BIT(NPCX_SMBCTL3_SDA_LVL))
 
 /* Error values that functions can return */
 enum smb_error {
-	SMB_OK = 0,                 /* No error                           */
-	SMB_CH_OCCUPIED,            /* Channel is already occupied        */
-	SMB_MEM_POOL_INIT_ERROR,    /* Memory pool initialization error   */
-	SMB_BUS_FREQ_ERROR,         /* SMbus freq was not valid           */
-	SMB_INVLAID_REGVALUE,       /* Invalid SMbus register value       */
-	SMB_UNEXIST_CH_ERROR,       /* Channel does not exist             */
-	SMB_NO_SUPPORT_PTL,         /* Not support SMBus Protocol         */
-	SMB_BUS_ERROR,              /* Encounter bus error                */
-	SMB_NO_ADDRESS_MATCH,       /* No peripheral address match        */
-				    /*  (Controller Mode)                 */
-	SMB_READ_DATA_ERROR,        /* Read data for SDA error            */
-	SMB_READ_OVERFLOW_ERROR,    /* Read data over than we predict     */
-	SMB_TIMEOUT_ERROR,          /* Timeout expired                    */
-	SMB_MODULE_ISBUSY,          /* Module is occupied by other device */
-	SMB_BUS_BUSY,               /* SMBus is occupied by other device  */
+	SMB_OK = 0, /* No error                           */
+	SMB_CH_OCCUPIED, /* Channel is already occupied        */
+	SMB_MEM_POOL_INIT_ERROR, /* Memory pool initialization error   */
+	SMB_BUS_FREQ_ERROR, /* SMbus freq was not valid           */
+	SMB_INVLAID_REGVALUE, /* Invalid SMbus register value       */
+	SMB_UNEXIST_CH_ERROR, /* Channel does not exist             */
+	SMB_NO_SUPPORT_PTL, /* Not support SMBus Protocol         */
+	SMB_BUS_ERROR, /* Encounter bus error                */
+	SMB_NO_ADDRESS_MATCH, /* No peripheral address match        */
+	/*  (Controller Mode)                 */
+	SMB_READ_DATA_ERROR, /* Read data for SDA error            */
+	SMB_READ_OVERFLOW_ERROR, /* Read data over than we predict     */
+	SMB_TIMEOUT_ERROR, /* Timeout expired                    */
+	SMB_MODULE_ISBUSY, /* Module is occupied by other device */
+	SMB_BUS_BUSY, /* SMBus is occupied by other device  */
 };
 
 /*
@@ -108,18 +108,18 @@ enum smb_oper_state_t {
 
 /* I2C controller state data */
 struct i2c_status {
-	int                   flags;     /* Flags (I2C_XFER_*) */
-	const uint8_t        *tx_buf;    /* Entry pointer of transmit buffer */
-	uint8_t              *rx_buf;    /* Entry pointer of receive buffer  */
-	uint16_t              sz_txbuf;  /* Size of Tx buffer in bytes */
-	uint16_t              sz_rxbuf;  /* Size of rx buffer in bytes */
-	uint16_t              idx_buf;   /* Current index of Tx/Rx buffer */
-	uint16_t              addr_flags;/* Target address */
-	enum smb_oper_state_t oper_state;/* Smbus operation state */
-	enum smb_error        err_code;  /* Error code */
-	int                   task_waiting; /* Task waiting on controller */
-	uint32_t              timeout_us;/* Transaction timeout */
-	uint16_t              kbps;      /* Speed */
+	int flags; /* Flags (I2C_XFER_*) */
+	const uint8_t *tx_buf; /* Entry pointer of transmit buffer */
+	uint8_t *rx_buf; /* Entry pointer of receive buffer  */
+	uint16_t sz_txbuf; /* Size of Tx buffer in bytes */
+	uint16_t sz_rxbuf; /* Size of rx buffer in bytes */
+	uint16_t idx_buf; /* Current index of Tx/Rx buffer */
+	uint16_t addr_flags; /* Target address */
+	enum smb_oper_state_t oper_state; /* Smbus operation state */
+	enum smb_error err_code; /* Error code */
+	int task_waiting; /* Task waiting on controller */
+	uint32_t timeout_us; /* Transaction timeout */
+	uint16_t kbps; /* Speed */
 };
 /* I2C controller state data array */
 static struct i2c_status i2c_stsobjs[I2C_CONTROLLER_COUNT];
@@ -127,27 +127,29 @@ static struct i2c_status i2c_stsobjs[I2C_CONTROLLER_COUNT];
 /* I2C timing setting */
 struct i2c_timing {
 	uint8_t clock; /* I2C source clock. (Unit: MHz)*/
-	uint8_t HLDT;  /* I2C hold-time. (Unit: clocks) */
-	uint8_t k1;    /* k1 = SCL low-time (Unit: clocks) */
-	uint8_t k2;    /* k2 = SCL high-time (Unit: clocks) */
+	uint8_t HLDT; /* I2C hold-time. (Unit: clocks) */
+	uint8_t k1; /* k1 = SCL low-time (Unit: clocks) */
+	uint8_t k2; /* k2 = SCL high-time (Unit: clocks) */
 };
 
 /* I2C timing setting array of 400K & 1M Hz */
 static const struct i2c_timing i2c_400k_timings[] = {
-	{20,  7, 32, 22},
-	{15,  7, 24, 18},};
+	{ 20, 7, 32, 22 },
+	{ 15, 7, 24, 18 },
+};
 const unsigned int i2c_400k_timing_used = ARRAY_SIZE(i2c_400k_timings);
 
 static const struct i2c_timing i2c_1m_timings[] = {
-	{20, 7, 16, 10},
-	{15, 7, 14, 10},};
+	{ 20, 7, 16, 10 },
+	{ 15, 7, 14, 10 },
+};
 const unsigned int i2c_1m_timing_used = ARRAY_SIZE(i2c_1m_timings);
 
 /* IRQ for each port */
 const uint32_t i2c_irqs[I2C_CONTROLLER_COUNT] = {
-		NPCX_IRQ_SMB1, NPCX_IRQ_SMB2, NPCX_IRQ_SMB3, NPCX_IRQ_SMB4,
+	NPCX_IRQ_SMB1, NPCX_IRQ_SMB2, NPCX_IRQ_SMB3, NPCX_IRQ_SMB4,
 #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-		NPCX_IRQ_SMB5, NPCX_IRQ_SMB6, NPCX_IRQ_SMB7, NPCX_IRQ_SMB8,
+	NPCX_IRQ_SMB5, NPCX_IRQ_SMB6, NPCX_IRQ_SMB7, NPCX_IRQ_SMB8,
 #endif
 };
 BUILD_ASSERT(ARRAY_SIZE(i2c_irqs) == I2C_CONTROLLER_COUNT);
@@ -198,8 +200,8 @@ static void i2c_abort_data(int controller)
 	SET_BIT(NPCX_SMBST(controller), NPCX_SMBST_NEGACK);
 
 	/* Wait till STOP condition is generated */
-	if (i2c_wait_stop_completed(controller, I2C_MAX_TIMEOUT)
-			!= EC_SUCCESS) {
+	if (i2c_wait_stop_completed(controller, I2C_MAX_TIMEOUT) !=
+	    EC_SUCCESS) {
 		cprintf(CC_I2C, "Abort i2c %02x fail!\n", controller);
 		/* Clear BB (BUS BUSY) bit */
 		SET_BIT(NPCX_SMBCST(controller), NPCX_SMBCST_BB);
@@ -219,8 +221,9 @@ static int i2c_reset(int controller)
 
 	while (--timeout) {
 		/* WAIT FOR SCL & SDA IS HIGH */
-		if (IS_BIT_SET(NPCX_SMBCTL3(controller), NPCX_SMBCTL3_SCL_LVL)
-		  && IS_BIT_SET(NPCX_SMBCTL3(controller), NPCX_SMBCTL3_SDA_LVL))
+		if (IS_BIT_SET(NPCX_SMBCTL3(controller),
+			       NPCX_SMBCTL3_SCL_LVL) &&
+		    IS_BIT_SET(NPCX_SMBCTL3(controller), NPCX_SMBCTL3_SDA_LVL))
 			break;
 		msleep(1);
 	}
@@ -306,9 +309,8 @@ static void i2c_fifo_write_data(int controller)
 	}
 	for (i = 0; i < len; i++) {
 		I2C_WRITE_BYTE(controller,
-				p_status->tx_buf[p_status->idx_buf++]);
-		CPRINTF("%02x ",
-				p_status->tx_buf[p_status->idx_buf - 1]);
+			       p_status->tx_buf[p_status->idx_buf++]);
+		CPRINTF("%02x ", p_status->tx_buf[p_status->idx_buf - 1]);
 	}
 	CPRINTF("\n");
 }
@@ -355,7 +357,7 @@ enum smb_error i2c_controller_transaction(int controller)
 			 * is set simultaneously.
 			 */
 			if (p_status->sz_rxbuf == 1 &&
-					(p_status->flags & I2C_XFER_STOP)) {
+			    (p_status->flags & I2C_XFER_STOP)) {
 				/*
 				 * Since SCL is released after reading last
 				 * byte from previous transaction, adding a
@@ -375,30 +377,30 @@ enum smb_error i2c_controller_transaction(int controller)
 		}
 	} else
 		cprintf(CC_I2C, "Unexpected i2c state machine! %d\n",
-				p_status->oper_state);
+			p_status->oper_state);
 
 	if (IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) {
 		if (p_status->sz_rxbuf > 0) {
 			if (p_status->sz_rxbuf > NPCX_I2C_FIFO_MAX_SIZE) {
 				/* Set RX threshold = FIFO_MAX_SIZE */
 				SET_FIELD(NPCX_SMBRXF_CTL(controller),
-						NPCX_SMBRXF_CTL_RX_THR,
-						NPCX_I2C_FIFO_MAX_SIZE);
+					  NPCX_SMBRXF_CTL_RX_THR,
+					  NPCX_I2C_FIFO_MAX_SIZE);
 			} else {
 				/*
 				 * set RX threshold = remaining data bytes
 				 * (it should be <= FIFO_MAX_SIZE)
 				 */
 				SET_FIELD(NPCX_SMBRXF_CTL(controller),
-						NPCX_SMBRXF_CTL_RX_THR,
-						p_status->sz_rxbuf);
+					  NPCX_SMBRXF_CTL_RX_THR,
+					  p_status->sz_rxbuf);
 				/*
 				 * Set LAST bit generate the NACK at the
 				 * last byte of the data group in FIFO
 				 */
 				if (p_status->flags & I2C_XFER_STOP) {
 					SET_BIT(NPCX_SMBRXF_CTL(controller),
-							NPCX_SMBRXF_CTL_LAST);
+						NPCX_SMBRXF_CTL_LAST);
 				}
 			}
 
@@ -412,7 +414,7 @@ enum smb_error i2c_controller_transaction(int controller)
 
 	/* Generate a START condition */
 	if (p_status->oper_state == SMB_CONTROLLER_START ||
-			p_status->oper_state == SMB_REPEAT_START) {
+	    p_status->oper_state == SMB_REPEAT_START) {
 		I2C_START(controller);
 		CPUTS("ST");
 	}
@@ -421,8 +423,8 @@ enum smb_error i2c_controller_transaction(int controller)
 	task_enable_irq(i2c_irqs[controller]);
 
 	/* Wait for transfer complete or timeout */
-	events = task_wait_event_mask(TASK_EVENT_I2C_IDLE,
-			p_status->timeout_us);
+	events =
+		task_wait_event_mask(TASK_EVENT_I2C_IDLE, p_status->timeout_us);
 
 	/* Disable event and error interrupts */
 	task_disable_irq(i2c_irqs[controller]);
@@ -452,8 +454,9 @@ enum smb_error i2c_controller_transaction(int controller)
 		i2c_recovery(controller, p_status);
 
 	/* Wait till STOP condition is generated for normal transaction */
-	if (p_status->err_code == SMB_OK && i2c_wait_stop_completed(controller,
-			I2C_MIN_TIMEOUT) != EC_SUCCESS) {
+	if (p_status->err_code == SMB_OK &&
+	    i2c_wait_stop_completed(controller, I2C_MIN_TIMEOUT) !=
+		    EC_SUCCESS) {
 		cprintf(CC_I2C,
 			"STOP fail! scl %02x is held by slave device!\n",
 			controller);
@@ -476,7 +479,7 @@ void i2c_done(int controller)
 		/* Clear RXF_TXE bit (RX FIFO full/TX FIFO empty) */
 		if (IS_ENABLED(NPCX_I2C_FIFO_SUPPORT))
 			NPCX_SMBFIF_CTS(controller) =
-						BIT(NPCX_SMBFIF_CTS_RXF_TXE);
+				BIT(NPCX_SMBFIF_CTS_RXF_TXE);
 
 		/* Clear SDAST by writing mock byte */
 		I2C_WRITE_BYTE(controller, 0xFF);
@@ -485,8 +488,9 @@ void i2c_done(int controller)
 	/* Set error code */
 	p_status->err_code = SMB_OK;
 	/* Set SMB status if we need stall bus */
-	p_status->oper_state = (p_status->flags & I2C_XFER_STOP)
-				? SMB_IDLE : SMB_WRITE_SUSPEND;
+	p_status->oper_state = (p_status->flags & I2C_XFER_STOP) ?
+				       SMB_IDLE :
+				       SMB_WRITE_SUSPEND;
 	/*
 	 * Disable interrupt for i2c controller stall SCL
 	 * and forbid SDAST generate interrupt
@@ -540,7 +544,7 @@ static void i2c_handle_receive(int controller)
 
 	/* Read to buf. Skip last byte if meet SMB_FAKE_READ_OPER */
 	if (p_status->oper_state == SMB_FAKE_READ_OPER &&
-			p_status->idx_buf == (p_status->sz_rxbuf - 1))
+	    p_status->idx_buf == (p_status->sz_rxbuf - 1))
 		p_status->idx_buf++;
 	else
 		p_status->rx_buf[p_status->idx_buf++] = data;
@@ -548,8 +552,9 @@ static void i2c_handle_receive(int controller)
 	/* last byte is read - end of transaction */
 	if (p_status->idx_buf == p_status->sz_rxbuf) {
 		/* Set current status */
-		p_status->oper_state = (p_status->flags & I2C_XFER_STOP)
-				? SMB_IDLE : SMB_READ_SUSPEND;
+		p_status->oper_state = (p_status->flags & I2C_XFER_STOP) ?
+					       SMB_IDLE :
+					       SMB_READ_SUSPEND;
 		/* Set error code */
 		p_status->err_code = SMB_OK;
 		/* Notify upper layer of missing data */
@@ -623,35 +628,33 @@ static void i2c_fifo_handle_receive(int controller)
 		if (remaining_bytes > 0) {
 			if (remaining_bytes > NPCX_I2C_FIFO_MAX_SIZE) {
 				SET_FIELD(NPCX_SMBRXF_CTL(controller),
-						NPCX_SMBRXF_CTL_RX_THR,
-						NPCX_I2C_FIFO_MAX_SIZE);
+					  NPCX_SMBRXF_CTL_RX_THR,
+					  NPCX_I2C_FIFO_MAX_SIZE);
 			} else {
 				SET_FIELD(NPCX_SMBRXF_CTL(controller),
-						NPCX_SMBRXF_CTL_RX_THR,
-						remaining_bytes);
+					  NPCX_SMBRXF_CTL_RX_THR,
+					  remaining_bytes);
 				if (p_status->flags & I2C_XFER_STOP) {
 					SET_BIT(NPCX_SMBRXF_CTL(controller),
-							NPCX_SMBRXF_CTL_LAST);
+						NPCX_SMBRXF_CTL_LAST);
 					CPRINTS("-FGNA");
 				}
 			}
-
 		}
 		i2c_stall_bus(controller, 0);
-
 	}
 	/* last byte is read - end of transaction */
 	if (p_status->idx_buf == p_status->sz_rxbuf) {
 		/* Set current status */
-		p_status->oper_state = (p_status->flags & I2C_XFER_STOP)
-				? SMB_IDLE : SMB_READ_SUSPEND;
+		p_status->oper_state = (p_status->flags & I2C_XFER_STOP) ?
+					       SMB_IDLE :
+					       SMB_READ_SUSPEND;
 		/* Set error code */
 		p_status->err_code = SMB_OK;
 		/* Notify upper layer of missing data */
 		task_set_event(p_status->task_waiting, TASK_EVENT_I2C_IDLE);
 		CPUTS("-END");
 	}
-
 }
 
 static void i2c_handle_sda_irq(int controller)
@@ -660,10 +663,10 @@ static void i2c_handle_sda_irq(int controller)
 	uint8_t addr_8bit = I2C_STRIP_FLAGS(p_status->addr_flags) << 1;
 
 	/* 1 Issue Start is successful ie. write address byte */
-	if (p_status->oper_state == SMB_CONTROLLER_START
-			|| p_status->oper_state == SMB_REPEAT_START) {
+	if (p_status->oper_state == SMB_CONTROLLER_START ||
+	    p_status->oper_state == SMB_REPEAT_START) {
 		/* Prepare address byte */
-		if (p_status->sz_txbuf == 0) {/* Receive mode */
+		if (p_status->sz_txbuf == 0) { /* Receive mode */
 			p_status->oper_state = SMB_READ_OPER;
 			/*
 			 * Receiving one or zero bytes - stall bus after
@@ -676,7 +679,7 @@ static void i2c_handle_sda_irq(int controller)
 			/* Write the address to the bus R bit*/
 			I2C_WRITE_BYTE(controller, (addr_8bit | 0x1));
 			CPRINTS("-ARR-0x%02x", addr_8bit);
-		} else {/* Transmit mode */
+		} else { /* Transmit mode */
 			p_status->oper_state = SMB_WRITE_OPER;
 			/* Write the address to the bus W bit*/
 			I2C_WRITE_BYTE(controller, addr_8bit);
@@ -720,14 +723,13 @@ static void i2c_handle_sda_irq(int controller)
 				 * in the SMBnTXF_CTL register.
 				 */
 				if (p_status->sz_rxbuf == 1 &&
-					(p_status->flags & I2C_XFER_STOP) &&
-					!IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) {
+				    (p_status->flags & I2C_XFER_STOP) &&
+				    !IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) {
 					I2C_NACK(controller);
 					CPUTS("-GNA");
 				}
 				/* Write the address to the bus R bit*/
-				I2C_WRITE_BYTE(controller,
-					       (addr_8bit | 0x1));
+				I2C_WRITE_BYTE(controller, (addr_8bit | 0x1));
 				CPUTS("-ARR");
 			}
 		}
@@ -749,7 +751,7 @@ static void i2c_handle_sda_irq(int controller)
 	 * operation)
 	 */
 	else if (p_status->oper_state == SMB_READ_OPER ||
-			p_status->oper_state == SMB_FAKE_READ_OPER) {
+		 p_status->oper_state == SMB_FAKE_READ_OPER) {
 		if (IS_ENABLED(NPCX_I2C_FIFO_SUPPORT))
 			i2c_fifo_handle_receive(controller);
 		else
@@ -826,7 +828,7 @@ static void i2c_controller_int_handler(int controller)
 		 * register.
 		 */
 		else if ((p_status->flags & I2C_XFER_STOP) &&
-				 !IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) {
+			 !IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) {
 			I2C_NACK(controller);
 		}
 
@@ -840,9 +842,10 @@ static void i2c_controller_int_handler(int controller)
 #if DEBUG_I2C
 		/* SDAST still issued with unexpected state machine */
 		if (IS_BIT_SET(NPCX_SMBST(controller), NPCX_SMBST_SDAST) &&
-				p_status->oper_state != SMB_WRITE_SUSPEND) {
+		    p_status->oper_state != SMB_WRITE_SUSPEND) {
 			cprints(CC_I2C, "i2c %d unknown state %d, error %d\n",
-			  controller, p_status->oper_state, p_status->err_code);
+				controller, p_status->oper_state,
+				p_status->err_code);
 		}
 #endif
 	}
@@ -858,15 +861,39 @@ void handle_interrupt(int controller)
 	i2c_controller_int_handler(controller);
 }
 
-static void i2c0_interrupt(void) { handle_interrupt(0); }
-static void i2c1_interrupt(void) { handle_interrupt(1); }
-static void i2c2_interrupt(void) { handle_interrupt(2); }
-static void i2c3_interrupt(void) { handle_interrupt(3); }
+static void i2c0_interrupt(void)
+{
+	handle_interrupt(0);
+}
+static void i2c1_interrupt(void)
+{
+	handle_interrupt(1);
+}
+static void i2c2_interrupt(void)
+{
+	handle_interrupt(2);
+}
+static void i2c3_interrupt(void)
+{
+	handle_interrupt(3);
+}
 #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
-static void i2c4_interrupt(void) { handle_interrupt(4); }
-static void i2c5_interrupt(void) { handle_interrupt(5); }
-static void i2c6_interrupt(void) { handle_interrupt(6); }
-static void i2c7_interrupt(void) { handle_interrupt(7); }
+static void i2c4_interrupt(void)
+{
+	handle_interrupt(4);
+}
+static void i2c5_interrupt(void)
+{
+	handle_interrupt(5);
+}
+static void i2c6_interrupt(void)
+{
+	handle_interrupt(6);
+}
+static void i2c7_interrupt(void)
+{
+	handle_interrupt(7);
+}
 #endif
 
 DECLARE_IRQ(NPCX_IRQ_SMB1, i2c0_interrupt, 4);
@@ -892,14 +919,12 @@ void i2c_set_timeout(int port, uint32_t timeout)
 		return;
 
 	/* Param is port, but timeout is stored by-controller. */
-	i2c_stsobjs[ctrl].timeout_us =
-		timeout ? timeout : I2C_TIMEOUT_DEFAULT_US;
+	i2c_stsobjs[ctrl].timeout_us = timeout ? timeout :
+						 I2C_TIMEOUT_DEFAULT_US;
 }
 
-int chip_i2c_xfer(const int port,
-		  const uint16_t addr_flags,
-		  const uint8_t *out, int out_size,
-		  uint8_t *in, int in_size, int flags)
+int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out,
+		  int out_size, uint8_t *in, int in_size, int flags)
 {
 	volatile struct i2c_status *p_status;
 	int ctrl = i2c_port_to_controller(port);
@@ -921,23 +946,23 @@ int chip_i2c_xfer(const int port,
 	i2c_select_port(port);
 
 	/* Copy data to controller struct */
-	p_status->flags      = flags;
-	p_status->tx_buf     = out;
-	p_status->sz_txbuf   = out_size;
-	p_status->rx_buf     = in;
-	p_status->sz_rxbuf   = in_size;
+	p_status->flags = flags;
+	p_status->tx_buf = out;
+	p_status->sz_txbuf = out_size;
+	p_status->rx_buf = in;
+	p_status->sz_rxbuf = in_size;
 	p_status->addr_flags = addr_flags;
 
 	/* Reset index & error */
-	p_status->idx_buf     = 0;
-	p_status->err_code    = SMB_OK;
+	p_status->idx_buf = 0;
+	p_status->err_code = SMB_OK;
 
 	/* Make sure we're in a good state to start */
 	if ((flags & I2C_XFER_START) &&
-	     /* Ignore busy bus for repeated start */
-	     p_status->oper_state != SMB_WRITE_SUSPEND &&
-	     (i2c_bus_busy(ctrl)
-	     || (i2c_get_line_levels(port) != I2C_LINE_IDLE))) {
+	    /* Ignore busy bus for repeated start */
+	    p_status->oper_state != SMB_WRITE_SUSPEND &&
+	    (i2c_bus_busy(ctrl) ||
+	     (i2c_get_line_levels(port) != I2C_LINE_IDLE))) {
 		int ret;
 
 		/* Attempt to unwedge the i2c port */
@@ -974,7 +999,7 @@ int chip_i2c_xfer(const int port,
 int i2c_get_line_levels(int port)
 {
 	return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) |
-		   (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
+	       (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
 }
 
 int i2c_raw_get_scl(int port)
@@ -989,8 +1014,9 @@ int i2c_raw_get_scl(int port)
 		if (i2c_is_raw_mode(port))
 			return gpio_get_level(g);
 		else
-			return IS_BIT_SET(NPCX_SMBCTL3(
-			i2c_port_to_controller(port)), NPCX_SMBCTL3_SCL_LVL);
+			return IS_BIT_SET(
+				NPCX_SMBCTL3(i2c_port_to_controller(port)),
+				NPCX_SMBCTL3_SCL_LVL);
 	}
 
 	/* If no SCL pin defined for this port, then return 1 to appear idle */
@@ -1009,11 +1035,11 @@ int i2c_raw_get_sda(int port)
 		if (i2c_is_raw_mode(port))
 			return gpio_get_level(g);
 		else
-			return IS_BIT_SET(NPCX_SMBCTL3(
-			i2c_port_to_controller(port)), NPCX_SMBCTL3_SDA_LVL);
+			return IS_BIT_SET(
+				NPCX_SMBCTL3(i2c_port_to_controller(port)),
+				NPCX_SMBCTL3_SDA_LVL);
 	}
 
-
 	/* If no SDA pin defined for this port, then return 1 to appear idle */
 	return 1;
 }
@@ -1032,8 +1058,8 @@ static void i2c_port_set_freq(const int ctrl, const int bus_freq_kbps)
 	 * SMB0/1/4/5/6/7 use APB3 clock
 	 * SMB2/3 use APB2 clock
 	 */
-	freq = (ctrl < 2 || ctrl > 3) ?
-		clock_get_apb3_freq() : clock_get_apb2_freq();
+	freq = (ctrl < 2 || ctrl > 3) ? clock_get_apb3_freq() :
+					clock_get_apb2_freq();
 #else /* CHIP_FAMILY_NPCX5 */
 	/*
 	 * SMB0/1 use core clock
@@ -1051,7 +1077,7 @@ static void i2c_port_set_freq(const int ctrl, const int bus_freq_kbps)
 	 * fSCL = fCLK / (4*SCLFRQ)
 	 * SCLFRQ = ceil(fCLK/(4*fSCL))
 	 */
-	scl_freq = DIV_ROUND_UP(freq, bus_freq_kbps*4000); /* Unit in bps */
+	scl_freq = DIV_ROUND_UP(freq, bus_freq_kbps * 4000); /* Unit in bps */
 
 	/* Normal mode if I2C freq is under 100kHz */
 	if (bus_freq_kbps <= 100) {
@@ -1089,19 +1115,19 @@ static void i2c_port_set_freq(const int ctrl, const int bus_freq_kbps)
 	}
 
 	for (j = 0; j < i2c_timing_used; j++, pTiming++) {
-		if (pTiming->clock == (freq/SECOND)) {
+		if (pTiming->clock == (freq / SECOND)) {
 			i2c_stsobjs[ctrl].kbps = bus_freq_kbps;
 			/* Set SCLH(L)T and hold-time */
-			NPCX_SMBSCLLT(ctrl) = pTiming->k1/2;
-			NPCX_SMBSCLHT(ctrl) = pTiming->k2/2;
-			SET_FIELD(NPCX_SMBCTL4(ctrl),
-				  NPCX_SMBCTL4_HLDT_FIELD, pTiming->HLDT);
+			NPCX_SMBSCLLT(ctrl) = pTiming->k1 / 2;
+			NPCX_SMBSCLHT(ctrl) = pTiming->k2 / 2;
+			SET_FIELD(NPCX_SMBCTL4(ctrl), NPCX_SMBCTL4_HLDT_FIELD,
+				  pTiming->HLDT);
 			break;
 		}
 	}
 	if (j == i2c_timing_used)
-		cprints(CC_I2C, "Error: I2C %d: src clk %d not supported",
-			ctrl, freq / SECOND);
+		cprints(CC_I2C, "Error: I2C %d: src clk %d not supported", ctrl,
+			freq / SECOND);
 }
 
 /* Hooks */
@@ -1187,10 +1213,10 @@ void i2c_init(void)
 
 	/* Enable clock for I2C peripheral */
 	clock_enable_peripheral(CGC_OFFSET_I2C, CGC_I2C_MASK,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
+				CGC_MODE_RUN | CGC_MODE_SLEEP);
 #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
 	clock_enable_peripheral(CGC_OFFSET_I2C2, CGC_I2C_MASK2,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
+				CGC_MODE_RUN | CGC_MODE_SLEEP);
 #endif
 
 	/* Set I2C freq */
diff --git a/chip/npcx/i2c_chip.h b/chip/npcx/i2c_chip.h
index 014e6cddf2..d1a7cf6851 100644
--- a/chip/npcx/i2c_chip.h
+++ b/chip/npcx/i2c_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/npcx/keyboard_raw.c b/chip/npcx/keyboard_raw.c
index 5d73765bff..cb2be7911e 100644
--- a/chip/npcx/keyboard_raw.c
+++ b/chip/npcx/keyboard_raw.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,7 +20,7 @@ void keyboard_raw_init(void)
 {
 	/* Enable clock for KBS peripheral */
 	clock_enable_peripheral(CGC_OFFSET_KBS, CGC_KBS_MASK,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
+				CGC_MODE_RUN | CGC_MODE_SLEEP);
 
 	/* Ensure top-level interrupt is disabled */
 	keyboard_raw_enable_interrupt(0);
@@ -63,7 +63,7 @@ void keyboard_raw_init(void)
 	NPCX_WKEN(MIWU_TABLE_WKKEY, MIWU_GROUP_WKKEY) = 0xFF;
 
 	/* Select high to low transition (falling edge) */
-	NPCX_WKEDG(MIWU_TABLE_WKKEY, MIWU_GROUP_WKKEY) =  0xFF;
+	NPCX_WKEDG(MIWU_TABLE_WKKEY, MIWU_GROUP_WKKEY) = 0xFF;
 
 	/* Enable interrupt of WK KBS */
 	keyboard_raw_enable_interrupt(1);
diff --git a/chip/npcx/lct.c b/chip/npcx/lct.c
index e23fa3bf6a..19568cac44 100644
--- a/chip/npcx/lct.c
+++ b/chip/npcx/lct.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,10 +13,10 @@
 #include "timer.h"
 #include "util.h"
 
-#define LCT_CLK_ENABLE_DELAY_USEC    150
+#define LCT_CLK_ENABLE_DELAY_USEC 150
 
-#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args)
 
 void npcx_lct_sel_power_src(enum NPCX_LCT_PWR_SRC pwr_src)
 {
@@ -93,7 +93,6 @@ void npcx_lct_config(int seconds, int psl_ena, int int_ena)
 
 	if (int_ena)
 		SET_BIT(NPCX_LCTCONT, NPCX_LCTCONT_EVEN);
-
 }
 
 uint32_t npcx_lct_get_time(void)
@@ -102,21 +101,17 @@ uint32_t npcx_lct_get_time(void)
 	uint8_t week, day, hour, minute;
 
 	do {
-		week   = NPCX_LCTWEEK;
-		day    = NPCX_LCTDAY;
-		hour   = NPCX_LCTHOUR;
+		week = NPCX_LCTWEEK;
+		day = NPCX_LCTDAY;
+		hour = NPCX_LCTHOUR;
 		minute = NPCX_LCTMINUTE;
 		second = NPCX_LCTSECOND;
-	} while (week   != NPCX_LCTWEEK   ||
-		 day    != NPCX_LCTDAY    ||
-		 hour   != NPCX_LCTHOUR   ||
-		 minute != NPCX_LCTMINUTE ||
+	} while (week != NPCX_LCTWEEK || day != NPCX_LCTDAY ||
+		 hour != NPCX_LCTHOUR || minute != NPCX_LCTMINUTE ||
 		 second != NPCX_LCTSECOND);
 
-	second += minute * SECS_PER_MINUTE +
-		  hour * SECS_PER_HOUR +
-		  day * SECS_PER_DAY +
-		  week * SECS_PER_WEEK;
+	second += minute * SECS_PER_MINUTE + hour * SECS_PER_HOUR +
+		  day * SECS_PER_DAY + week * SECS_PER_WEEK;
 
 	return second;
 }
@@ -148,7 +143,7 @@ static void npcx_lct_init(void)
 DECLARE_HOOK(HOOK_INIT, npcx_lct_init, HOOK_PRIO_DEFAULT);
 
 #ifdef CONFIG_CMD_RTC_ALARM
-static int command_lctalarm(int argc, char **argv)
+static int command_lctalarm(int argc, const char **argv)
 {
 	char *e;
 	int seconds;
@@ -164,9 +159,9 @@ static int command_lctalarm(int argc, char **argv)
 	npcx_lct_config(seconds, 0, 1);
 	task_disable_irq(NPCX_IRQ_LCT_WKINTF_2);
 	/* Enable wake-up input sources & clear pending bit */
-	NPCX_WKPCL(MIWU_TABLE_2, LCT_WUI_GROUP)  |= LCT_WUI_MASK;
+	NPCX_WKPCL(MIWU_TABLE_2, LCT_WUI_GROUP) |= LCT_WUI_MASK;
 	NPCX_WKINEN(MIWU_TABLE_2, LCT_WUI_GROUP) |= LCT_WUI_MASK;
-	NPCX_WKEN(MIWU_TABLE_2, LCT_WUI_GROUP)   |= LCT_WUI_MASK;
+	NPCX_WKEN(MIWU_TABLE_2, LCT_WUI_GROUP) |= LCT_WUI_MASK;
 	task_enable_irq(NPCX_IRQ_LCT_WKINTF_2);
 	npcx_lct_enable(1);
 
diff --git a/chip/npcx/lct_chip.h b/chip/npcx/lct_chip.h
index 197c189f43..8b4ee804cf 100644
--- a/chip/npcx/lct_chip.h
+++ b/chip/npcx/lct_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,10 +10,7 @@
 
 #define NPCX_LCT_MAX (16 * SECS_PER_WEEK - 1)
 
-enum NPCX_LCT_PWR_SRC {
-	NPCX_LCT_PWR_SRC_VCC1,
-	NPCX_LCT_PWR_SRC_VSBY
-};
+enum NPCX_LCT_PWR_SRC { NPCX_LCT_PWR_SRC_VCC1, NPCX_LCT_PWR_SRC_VSBY };
 
 void npcx_lct_config(int seconds, int psl_ena, int int_ena);
 void npcx_lct_enable(uint8_t enable);
@@ -25,4 +22,4 @@ int npcx_lct_is_event_set(void);
 /* return the current time of LCT in second */
 uint32_t npcx_lct_get_time(void);
 
-#endif  /* __CROS_EC_LCT_CHIP_H */
+#endif /* __CROS_EC_LCT_CHIP_H */
diff --git a/chip/npcx/lfw/ec_lfw.h b/chip/npcx/lfw/ec_lfw.h
index 88c0a9ed83..3b7e4da459 100644
--- a/chip/npcx/lfw/ec_lfw.h
+++ b/chip/npcx/lfw/ec_lfw.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c
index ec99df9eb3..48e094f3fc 100644
--- a/chip/npcx/lpc.c
+++ b/chip/npcx/lpc.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -33,30 +33,30 @@
 #define CPRINTS(...)
 #else
 #define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args)
 #endif
 
 /* PM channel definitions */
-#define PMC_ACPI     PM_CHAN_1
+#define PMC_ACPI PM_CHAN_1
 #define PMC_HOST_CMD PM_CHAN_2
 
 /* Microseconds to wait for eSPI VW changes to propagate */
-#define ESPI_DIRTY_WAIT_TIME_US	150
+#define ESPI_DIRTY_WAIT_TIME_US 150
 
-#define PORT80_MAX_BUF_SIZE    16
+#define PORT80_MAX_BUF_SIZE 16
 static uint16_t port80_buf[PORT80_MAX_BUF_SIZE];
 
-static struct	host_packet lpc_packet;
-static struct	host_cmd_handler_args host_cmd_args;
-static uint8_t	host_cmd_flags;         /* Flags from host command */
-static uint8_t	shm_mem_host_cmd[256] __aligned(8);
-static uint8_t	shm_memmap[256] __aligned(8);
+static struct host_packet lpc_packet;
+static struct host_cmd_handler_args host_cmd_args;
+static uint8_t host_cmd_flags; /* Flags from host command */
+static uint8_t shm_mem_host_cmd[256] __aligned(8);
+static uint8_t shm_memmap[256] __aligned(8);
 /* Params must be 32-bit aligned */
 static uint8_t params_copy[EC_LPC_HOST_PACKET_SIZE] __aligned(4);
 static int init_done;
 
-static struct ec_lpc_host_args * const lpc_host_args =
-		(struct ec_lpc_host_args *)shm_mem_host_cmd;
+static struct ec_lpc_host_args *const lpc_host_args =
+	(struct ec_lpc_host_args *)shm_mem_host_cmd;
 
 /*****************************************************************************/
 /* IC specific low-level driver */
@@ -152,7 +152,7 @@ static void lpc_generate_smi(void)
 	/* Generate a falling edge */
 	espi_wait_vw_not_dirty(VW_SMI_L, ESPI_DIRTY_WAIT_TIME_US);
 	NPCX_HIPMIC(PMC_ACPI) = NPCX_VW_SMI(0);
-	udelay(CONFIG_ESPI_DEFAULT_VW_WIDTH_US);
+	udelay(CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US);
 	espi_wait_vw_not_dirty(VW_SMI_L, ESPI_DIRTY_WAIT_TIME_US);
 
 	/* Set signal high */
@@ -160,10 +160,10 @@ static void lpc_generate_smi(void)
 #else
 	/* SET SMIB bit to pull SMI_L to high.*/
 	SET_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SMIB);
-	udelay(CONFIG_ESPI_DEFAULT_VW_WIDTH_US);
+	udelay(CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US);
 	/* Generate a falling edge */
 	CLEAR_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SMIB);
-	udelay(CONFIG_ESPI_DEFAULT_VW_WIDTH_US);
+	udelay(CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US);
 	/* Set signal high */
 	SET_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SMIB);
 #endif
@@ -199,7 +199,7 @@ static void lpc_generate_sci(void)
 	/* Generate a falling edge */
 	espi_wait_vw_not_dirty(VW_SCI_L, ESPI_DIRTY_WAIT_TIME_US);
 	NPCX_HIPMIC(PMC_ACPI) = NPCX_VW_SCI(0);
-	udelay(CONFIG_ESPI_DEFAULT_VW_WIDTH_US);
+	udelay(CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US);
 	espi_wait_vw_not_dirty(VW_SCI_L, ESPI_DIRTY_WAIT_TIME_US);
 
 	/* Set signal high */
@@ -207,10 +207,10 @@ static void lpc_generate_sci(void)
 #else
 	/* Set SCIB bit to pull SCI_L to high.*/
 	SET_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SCIB);
-	udelay(CONFIG_ESPI_DEFAULT_VW_WIDTH_US);
+	udelay(CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US);
 	/* Generate a falling edge */
 	CLEAR_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SCIB);
-	udelay(CONFIG_ESPI_DEFAULT_VW_WIDTH_US);
+	udelay(CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US);
 	/* Set signal high */
 	SET_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SCIB);
 #endif
@@ -260,15 +260,13 @@ static void lpc_send_response(struct host_cmd_handler_args *args)
 	}
 
 	/* New-style response */
-	lpc_host_args->flags =
-			(host_cmd_flags & ~EC_HOST_ARGS_FLAG_FROM_HOST) |
-			EC_HOST_ARGS_FLAG_TO_HOST;
+	lpc_host_args->flags = (host_cmd_flags & ~EC_HOST_ARGS_FLAG_FROM_HOST) |
+			       EC_HOST_ARGS_FLAG_TO_HOST;
 
 	lpc_host_args->data_size = size;
 
 	csum = args->command + lpc_host_args->flags +
-			lpc_host_args->command_version +
-			lpc_host_args->data_size;
+	       lpc_host_args->command_version + lpc_host_args->data_size;
 
 	for (i = 0, out = (uint8_t *)args->response; i < size; i++, out++)
 		csum += *out;
@@ -300,13 +298,13 @@ static void lpc_send_response_packet(struct host_packet *pkt)
 int lpc_keyboard_has_char(void)
 {
 	/* if OBF bit is '1', that mean still have a data in DBBOUT */
-	return (NPCX_HIKMST&0x01) ? 1 : 0;
+	return (NPCX_HIKMST & 0x01) ? 1 : 0;
 }
 
 int lpc_keyboard_input_pending(void)
 {
 	/* if IBF bit is '1', that mean still have a data in DBBIN */
-	return (NPCX_HIKMST&0x02) ? 1 : 0;
+	return (NPCX_HIKMST & 0x02) ? 1 : 0;
 }
 
 /* Put a char to host buffer by HIKDO and send IRQ if specified. */
@@ -407,7 +405,7 @@ void lpc_update_host_event_status(void)
 
 	/* Copy host events to mapped memory */
 	*(host_event_t *)host_get_memmap(EC_MEMMAP_HOST_EVENTS) =
-				lpc_get_host_events();
+		lpc_get_host_events();
 
 	lpc_task_enable_irq();
 
@@ -571,9 +569,9 @@ static void lpc_pmc_ibf_interrupt(void)
 	/* Channel-2 for Host Command usage , so the argument data had been
 	 * put on the share memory firstly*/
 	if (NPCX_HIPMST(PMC_ACPI) & 0x02)
-		handle_acpi_write((NPCX_HIPMST(PMC_ACPI)&0x08) ? 1 : 0);
+		handle_acpi_write((NPCX_HIPMST(PMC_ACPI) & 0x08) ? 1 : 0);
 	else if (NPCX_HIPMST(PMC_HOST_CMD) & 0x02)
-		handle_host_write((NPCX_HIPMST(PMC_HOST_CMD)&0x08) ? 1 : 0);
+		handle_host_write((NPCX_HIPMST(PMC_HOST_CMD) & 0x08) ? 1 : 0);
 }
 DECLARE_IRQ(NPCX_IRQ_PM_CHAN_IBF, lpc_pmc_ibf_interrupt, 4);
 
@@ -591,7 +589,7 @@ static void lpc_port80_interrupt(void)
 
 	/* buffer Port80 data to the local buffer if FIFO is not empty */
 	while (IS_BIT_SET(NPCX_DP80STS, NPCX_DP80STS_FNE) &&
-		   (count < ARRAY_SIZE(port80_buf)))
+	       (count < ARRAY_SIZE(port80_buf)))
 		port80_buf[count++] = NPCX_DP80BUF;
 
 	for (i = 0; i < count; i++) {
@@ -690,8 +688,7 @@ void host_register_init(void)
 	/* LDN register = 0x0F(SHM) */
 	sib_write_reg(SIO_OFFSET, 0x07, 0x0F);
 	/* WIN1&2 mapping to IO */
-	sib_write_reg(SIO_OFFSET, 0xF1,
-			sib_read_reg(SIO_OFFSET, 0xF1) | 0x30);
+	sib_write_reg(SIO_OFFSET, 0xF1, sib_read_reg(SIO_OFFSET, 0xF1) | 0x30);
 	/* WIN1 as Host Command on the IO:0x0800 */
 	sib_write_reg(SIO_OFFSET, 0xF5, 0x08);
 	sib_write_reg(SIO_OFFSET, 0xF4, 0x00);
@@ -711,7 +708,6 @@ void host_register_init(void)
 	sib_write_reg(SIO_OFFSET, 0x30, 0x01);
 
 	CPRINTS("Host settings are done!");
-
 }
 
 #ifdef CONFIG_CHIPSET_RESET_HOOK
@@ -735,7 +731,7 @@ void lpc_lreset_pltrst_handler(void)
 	int pltrst_asserted;
 
 	/* Clear pending bit of WUI */
-	SET_BIT(NPCX_WKPCL(MIWU_TABLE_0 , MIWU_GROUP_5), 7);
+	SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_5), 7);
 
 	/* Ignore PLTRST# from SOC if it is not valid */
 	if (chipset_pltrst_is_valid && !chipset_pltrst_is_valid())
@@ -770,7 +766,7 @@ static void lpc_init(void)
 {
 	/* Enable clock for LPC peripheral */
 	clock_enable_peripheral(CGC_OFFSET_LPC, CGC_LPC_MASK,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
+				CGC_MODE_RUN | CGC_MODE_SLEEP);
 	/*
 	 * In npcx5/7, the host interface type (HIF_TYP_SEL in the DEVCNT
 	 * register) is updated by booter after VCC1 Power-Up reset according to
@@ -839,8 +835,8 @@ static void lpc_init(void)
 
 	/* We support LPC args and version 3 protocol */
 	*(lpc_get_memmap_range() + EC_MEMMAP_HOST_CMD_FLAGS) =
-			EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED |
-			EC_HOST_CMD_FLAG_VERSION_3;
+		EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED |
+		EC_HOST_CMD_FLAG_VERSION_3;
 
 	/*
 	 * Clear processing flag before enabling lpc's interrupts in case
@@ -854,7 +850,7 @@ static void lpc_init(void)
 	/*
 	 * Set required control value (avoid setting HOSTWAIT bit at this stage)
 	 */
-	NPCX_SMC_CTL = NPCX_SMC_CTL&~0x7F;
+	NPCX_SMC_CTL = NPCX_SMC_CTL & ~0x7F;
 	/* Clear status */
 	NPCX_SMC_STS = NPCX_SMC_STS;
 
@@ -903,8 +899,8 @@ static void lpc_init(void)
 	CLEAR_BIT(NPCX_HIPMCTL(PMC_ACPI), NPCX_HIPMCTL_SCIPOL);
 	CLEAR_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SMIPOL);
 	/* Set SMIB/SCIB to make sure SMI/SCI are high at init */
-	NPCX_HIPMIC(PMC_ACPI) = NPCX_HIPMIC(PMC_ACPI)
-			| BIT(NPCX_HIPMIC_SMIB) | BIT(NPCX_HIPMIC_SCIB);
+	NPCX_HIPMIC(PMC_ACPI) = NPCX_HIPMIC(PMC_ACPI) | BIT(NPCX_HIPMIC_SMIB) |
+				BIT(NPCX_HIPMIC_SCIB);
 #ifndef CONFIG_SCI_GPIO
 	/*
 	 * Allow SMI/SCI generated from PM module.
@@ -973,12 +969,11 @@ static enum ec_status lpc_get_protocol_info(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO,
-		lpc_get_protocol_info,
-		EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, lpc_get_protocol_info,
+		     EC_VER_MASK(0));
 
 #if DEBUG_LPC
-static int command_lpc(int argc, char **argv)
+static int command_lpc(int argc, const char **argv)
 {
 	if (argc == 1)
 		return EC_ERROR_PARAM1;
diff --git a/chip/npcx/lpc_chip.h b/chip/npcx/lpc_chip.h
index 607fdde5fa..872b20f915 100644
--- a/chip/npcx/lpc_chip.h
+++ b/chip/npcx/lpc_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/npcx/peci.c b/chip/npcx/peci.c
index 6f82b932b0..7c213648f4 100644
--- a/chip/npcx/peci.c
+++ b/chip/npcx/peci.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,31 +19,29 @@
 #include "temp_sensor.h"
 #include "util.h"
 
-
 /* Initial PECI baud rate */
-#define PECI_BAUD_RATE        750000
-
-#define TEMP_AVG_LENGTH       4  /* Should be power of 2 */
+#define PECI_BAUD_RATE 750000
 
+#define TEMP_AVG_LENGTH 4 /* Should be power of 2 */
 
 /* PECI Time-out */
-#define PECI_DONE_TIMEOUT_US  (10*MSEC)
+#define PECI_DONE_TIMEOUT_US (10 * MSEC)
 
-#define NULL_PENDING_TASK_ID  0xFFFFFFFF
-#define PECI_MAX_FIFO_SIZE    16
-#define PROC_SOCKET           0x30
+#define NULL_PENDING_TASK_ID 0xFFFFFFFF
+#define PECI_MAX_FIFO_SIZE 16
+#define PROC_SOCKET 0x30
 /* PECI Command Code */
 enum peci_command_t {
-	PECI_COMMAND_PING               = 0x00,
-	PECI_COMMAND_GET_DIB            = 0xF7,
-	PECI_COMMAND_GET_TEMP           = 0x01,
-	PECI_COMMAND_RD_PKG_CFG         = 0xA1,
-	PECI_COMMAND_WR_PKG_CFG         = 0xA5,
-	PECI_COMMAND_RD_IAMSR           = 0xB1,
-	PECI_COMMAND_RD_PCI_CFG         = 0x61,
-	PECI_COMMAND_RD_PCI_CFG_LOCAL   = 0xE1,
-	PECI_COMMAND_WR_PCI_CFG_LOCAL   = 0xE5,
-	PECI_COMMAND_NONE               = 0xFF
+	PECI_COMMAND_PING = 0x00,
+	PECI_COMMAND_GET_DIB = 0xF7,
+	PECI_COMMAND_GET_TEMP = 0x01,
+	PECI_COMMAND_RD_PKG_CFG = 0xA1,
+	PECI_COMMAND_WR_PKG_CFG = 0xA5,
+	PECI_COMMAND_RD_IAMSR = 0xB1,
+	PECI_COMMAND_RD_PCI_CFG = 0x61,
+	PECI_COMMAND_RD_PCI_CFG_LOCAL = 0xE1,
+	PECI_COMMAND_WR_PCI_CFG_LOCAL = 0xE5,
+	PECI_COMMAND_NONE = 0xFF
 };
 
 #define PECI_COMMAND_GET_TEMP_WR_LENS 0x00
@@ -68,12 +66,8 @@ static int peci_pending_task_id;
  * @param   *wr_data  Buffer pointer of write data
  * @return  TASK_EVENT_PECI_DONE that mean slave had a response
  */
-static uint32_t peci_trans(
-		uint8_t             wr_length,
-		uint8_t             rd_length,
-		enum peci_command_t cmd_code,
-		uint8_t            *wr_data
-)
+static uint32_t peci_trans(uint8_t wr_length, uint8_t rd_length,
+			   enum peci_command_t cmd_code, uint8_t *wr_data)
 {
 	uint32_t events;
 	/* Ensure no PECI transaction is in progress */
@@ -100,7 +94,7 @@ static uint32_t peci_trans(
 	/* Write-Length */
 	if (cmd_code != PECI_COMMAND_PING) {
 		if ((cmd_code == PECI_COMMAND_WR_PKG_CFG) ||
-				(cmd_code == PECI_COMMAND_WR_PCI_CFG_LOCAL)) {
+		    (cmd_code == PECI_COMMAND_WR_PCI_CFG_LOCAL)) {
 			/*CMD+AWFCS*/
 			NPCX_PECI_WR_LENGTH = wr_length + 2;
 			/* Enable AWFCS */
@@ -110,7 +104,7 @@ static uint32_t peci_trans(
 			NPCX_PECI_WR_LENGTH = wr_length + 1;
 			/* Enable AWFCS */
 			CLEAR_BIT(NPCX_PECI_CTL_STS,
-					NPCX_PECI_CTL_STS_AWFCS_EN);
+				  NPCX_PECI_CTL_STS_AWFCS_EN);
 		}
 	}
 
@@ -119,9 +113,7 @@ static uint32_t peci_trans(
 
 	/* It should be using a interrupt , don't waste cpu computing power */
 	peci_pending_task_id = task_get_current();
-	return task_wait_event_mask(TASK_EVENT_PECI_DONE,
-					PECI_DONE_TIMEOUT_US);
-
+	return task_wait_event_mask(TASK_EVENT_PECI_DONE, PECI_DONE_TIMEOUT_US);
 }
 
 /**
@@ -143,8 +135,8 @@ int peci_get_cpu_temp(void)
 
 	/* Start PECI trans */
 	events = peci_trans(PECI_COMMAND_GET_TEMP_WR_LENS,
-				PECI_COMMAND_GET_TEMP_RD_LENS,
-				PECI_COMMAND_GET_TEMP, NULL);
+			    PECI_COMMAND_GET_TEMP_RD_LENS,
+			    PECI_COMMAND_GET_TEMP, NULL);
 	/* if return DONE , that mean slave had a PECI response */
 	if ((events & TASK_EVENT_PECI_DONE) == TASK_EVENT_PECI_DONE) {
 		/* check CRC & ABRT */
@@ -223,7 +215,7 @@ static void peci_freq_changed(void)
 	 * Maximum bit rate should not extend the field's boundaries.
 	 */
 	if (freq != 0) {
-		baud = (uint8_t)(freq  / (4 * PECI_BAUD_RATE)) - 1;
+		baud = (uint8_t)(freq / (4 * PECI_BAUD_RATE)) - 1;
 		/* Set maximum PECI baud rate (bit0 - bit4) */
 		if (baud > 0x1F)
 			baud = 0x1F;
@@ -247,7 +239,7 @@ static void peci_init(void)
 
 	/* Enable clock for PECI peripheral */
 	clock_enable_peripheral(CGC_OFFSET_PECI, CGC_PECI_MASK,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
+				CGC_MODE_RUN | CGC_MODE_SLEEP);
 	/* Set PECI freq */
 	peci_freq_changed();
 
@@ -269,7 +261,8 @@ static void peci_init(void)
 DECLARE_HOOK(HOOK_INIT, peci_init, HOOK_PRIO_DEFAULT);
 
 /* If received a PECI DONE interrupt, post the event to PECI task */
-static void peci_done_interrupt(void){
+static void peci_done_interrupt(void)
+{
 	if (peci_pending_task_id != NULL_PENDING_TASK_ID)
 		task_set_event(peci_pending_task_id, TASK_EVENT_PECI_DONE);
 	peci_sts = NPCX_PECI_CTL_STS & 0x18;
@@ -283,7 +276,7 @@ DECLARE_IRQ(NPCX_IRQ_PECI, peci_done_interrupt, 4);
 /*****************************************************************************/
 /* Console commands */
 
-static int command_peci_temp(int argc, char **argv)
+static int command_peci_temp(int argc, const char **argv)
 {
 	int t = peci_get_cpu_temp();
 	if (t == -1) {
@@ -293,6 +286,5 @@ static int command_peci_temp(int argc, char **argv)
 	ccprintf("CPU temp = %d K = %d\n", t, K_TO_C(t));
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(pecitemp, command_peci_temp,
-		NULL,
-		"Print CPU temperature");
+DECLARE_CONSOLE_COMMAND(pecitemp, command_peci_temp, NULL,
+			"Print CPU temperature");
diff --git a/chip/npcx/ps2.c b/chip/npcx/ps2.c
index 13a1ff6d57..a8a65e63ea 100644
--- a/chip/npcx/ps2.c
+++ b/chip/npcx/ps2.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,25 +16,25 @@
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_PS2, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_PS2, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_PS2, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_PS2, format, ##args)
 
 #if !(DEBUG_PS2)
 #define DEBUG_CPRINTS(...)
 #define DEBUG_CPRINTF(...)
 #else
-#define DEBUG_CPRINTS(format, args...) cprints(CC_PS2, format, ## args)
-#define DEBUG_CPRINTF(format, args...) cprintf(CC_PS2, format, ## args)
+#define DEBUG_CPRINTS(format, args...) cprints(CC_PS2, format, ##args)
+#define DEBUG_CPRINTF(format, args...) cprintf(CC_PS2, format, ##args)
 #endif
 
 /*
  * Set WDAT3-0 and clear CLK3-0 in the PSOSIG register to
  * reset the shift mechanism.
  */
-#define PS2_SHIFT_MECH_RESET       0x47
+#define PS2_SHIFT_MECH_RESET 0x47
 
-#define PS2_TRANSACTION_TIMEOUT    (20 * MSEC)
-#define PS2_BUSY_RETRY             10
+#define PS2_TRANSACTION_TIMEOUT (20 * MSEC)
+#define PS2_BUSY_RETRY 10
 
 enum ps2_input_debounce_cycle {
 	PS2_IDB_1_CYCLE,
@@ -60,7 +60,7 @@ struct ps2_data {
 	void (*rx_handler_cb)(uint8_t data);
 };
 static struct ps2_data ps2_ch_data[NPCX_PS2_CH_COUNT] = {
-	 [0 ... (NPCX_PS2_CH_COUNT - 1)] =  { PS2_RX_MODE, NULL }
+	[0 ...(NPCX_PS2_CH_COUNT - 1)] = { PS2_RX_MODE, NULL }
 };
 
 /*
@@ -76,7 +76,7 @@ static void ps2_init(void)
 {
 	/* Disable the power down bit of PS/2 */
 	clock_enable_peripheral(CGC_OFFSET_PS2, CGC_PS2_MASK,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
+				CGC_MODE_RUN | CGC_MODE_SLEEP);
 
 	/* Disable shift mechanism and configure PS/2 to received mode. */
 	NPCX_PS2_PSCON = 0x0;
@@ -90,10 +90,9 @@ static void ps2_init(void)
 	 * [4] - : WUE     = 1: Wake-Up Enable
 	 * [7] - : CLK_SEL = 1: Select Free-Run clock as the basic clock
 	 */
-	NPCX_PS2_PSIEN = BIT(NPCX_PS2_PSIEN_SOTIE) |
-				BIT(NPCX_PS2_PSIEN_EOTIE) |
-				BIT(NPCX_PS2_PSIEN_PS2_WUE) |
-				BIT(NPCX_PS2_PSIEN_PS2_CLK_SEL);
+	NPCX_PS2_PSIEN = BIT(NPCX_PS2_PSIEN_SOTIE) | BIT(NPCX_PS2_PSIEN_EOTIE) |
+			 BIT(NPCX_PS2_PSIEN_PS2_WUE) |
+			 BIT(NPCX_PS2_PSIEN_PS2_CLK_SEL);
 
 	/* Enable weak internal pull-up */
 	SET_BIT(NPCX_PS2_PSCON, NPCX_PS2_PSCON_WPUED);
@@ -106,8 +105,7 @@ static void ps2_init(void)
 }
 DECLARE_HOOK(HOOK_INIT, ps2_init, HOOK_PRIO_DEFAULT);
 
-void ps2_enable_channel(int channel, int enable,
-					void (*callback)(uint8_t data))
+void ps2_enable_channel(int channel, int enable, void (*callback)(uint8_t data))
 {
 	if (channel >= NPCX_PS2_CH_COUNT) {
 		CPRINTS("Err:PS/2 CH exceed %d", NPCX_PS2_CH_COUNT);
@@ -125,7 +123,7 @@ void ps2_enable_channel(int channel, int enable,
 		/* Enable the relevant channel clock */
 		SET_BIT(NPCX_PS2_PSOSIG, NPCX_PS2_PSOSIG_CLK(channel));
 	} else {
-		channel_enabled_mask &=  ~BIT(NPCX_PS2_PSOSIG_CLK(channel));
+		channel_enabled_mask &= ~BIT(NPCX_PS2_PSOSIG_CLK(channel));
 		/* Disable the relevant channel clock */
 		CLEAR_BIT(NPCX_PS2_PSOSIG, NPCX_PS2_PSOSIG_CLK(channel));
 		ps2_ch_data[channel].rx_handler_cb = NULL;
@@ -144,7 +142,9 @@ static int ps2_is_busy(void)
 	 * (due to Shift Mechanism is reset)
 	 */
 	return (IS_BIT_SET(NPCX_PS2_PSTAT, NPCX_PS2_PSTAT_SOT) |
-		IS_BIT_SET(NPCX_PS2_PSTAT, NPCX_PS2_PSTAT_EOT)) ? 1 : 0;
+		IS_BIT_SET(NPCX_PS2_PSTAT, NPCX_PS2_PSTAT_EOT)) ?
+		       1 :
+		       0;
 }
 
 int ps2_transmit_byte(int channel, uint8_t data)
@@ -194,7 +194,7 @@ int ps2_transmit_byte(int channel, uint8_t data)
 
 	/* Wait for interrupt */
 	event = task_wait_event_mask(TASK_EVENT_PS2_DONE,
-					PS2_TRANSACTION_TIMEOUT);
+				     PS2_TRANSACTION_TIMEOUT);
 	task_waiting = TASK_ID_INVALID;
 
 	if (event == TASK_EVENT_TIMER) {
@@ -216,7 +216,6 @@ int ps2_transmit_byte(int channel, uint8_t data)
 
 	DEBUG_CPRINTF("Evt:0x%08x\n", event);
 	return (event == TASK_EVENT_PS2_DONE) ? EC_SUCCESS : EC_ERROR_TIMEOUT;
-
 }
 
 static void ps2_stop_inactive_ch_clk(uint8_t active_ch)
@@ -224,20 +223,17 @@ static void ps2_stop_inactive_ch_clk(uint8_t active_ch)
 	uint8_t mask;
 
 	mask = ~NPCX_PS2_PSOSIG_CLK_MASK_ALL |
-					BIT(NPCX_PS2_PSOSIG_CLK(active_ch));
+	       BIT(NPCX_PS2_PSOSIG_CLK(active_ch));
 	NPCX_PS2_PSOSIG &= mask;
-
 }
 
 static int ps2_is_rx_error(uint8_t ch)
 {
-	uint8_t	status;
+	uint8_t status;
 
 	status = NPCX_PS2_PSTAT &
-				(BIT(NPCX_PS2_PSTAT_PERR) |
-				 BIT(NPCX_PS2_PSTAT_RFERR));
+		 (BIT(NPCX_PS2_PSTAT_PERR) | BIT(NPCX_PS2_PSTAT_RFERR));
 	if (status) {
-
 		if (status & BIT(NPCX_PS2_PSTAT_PERR))
 			CPRINTF("PS2 CH %d RX parity error\n", ch);
 		if (status & BIT(NPCX_PS2_PSTAT_RFERR))
@@ -270,7 +266,7 @@ static void ps2_int_handler(void)
 
 	/* PS/2 Start of Transaction */
 	if (IS_BIT_SET(NPCX_PS2_PSTAT, NPCX_PS2_PSTAT_SOT) &&
-			IS_BIT_SET(NPCX_PS2_PSIEN, NPCX_PS2_PSIEN_SOTIE)) {
+	    IS_BIT_SET(NPCX_PS2_PSIEN, NPCX_PS2_PSIEN_SOTIE)) {
 		DEBUG_CPRINTF("SOT-");
 		/*
 		 * Once set, SOT is not cleared until the shift mechanism
@@ -278,7 +274,7 @@ static void ps2_int_handler(void)
 		 * first occurrence of an SOT interrupt.
 		 */
 		CLEAR_BIT(NPCX_PS2_PSIEN, NPCX_PS2_PSIEN_SOTIE);
-	/* PS/2 End of Transaction */
+		/* PS/2 End of Transaction */
 	} else if (IS_BIT_SET(NPCX_PS2_PSTAT, NPCX_PS2_PSTAT_EOT)) {
 		DEBUG_CPRINTF("EOT-");
 		CLEAR_BIT(NPCX_PS2_PSIEN, NPCX_PS2_PSIEN_EOTIE);
@@ -298,7 +294,7 @@ static void ps2_int_handler(void)
 			if (!ps2_is_rx_error(active_ch)) {
 				uint8_t data_read = NPCX_PS2_PSDAT;
 				struct ps2_data *ps2_ptr =
-							&ps2_ch_data[active_ch];
+					&ps2_ch_data[active_ch];
 
 				DEBUG_CPRINTF("Recv:0x%02x", data_read);
 				if (ps2_ptr->rx_handler_cb)
@@ -316,12 +312,11 @@ static void ps2_int_handler(void)
 		SET_BIT(NPCX_PS2_PSIEN, NPCX_PS2_PSIEN_EOTIE);
 	}
 	DEBUG_CPRINTF("\n");
-
 }
 DECLARE_IRQ(NPCX_IRQ_PS2, ps2_int_handler, 5);
 
 #ifdef CONFIG_CMD_PS2
-static int command_ps2ench(int argc, char **argv)
+static int command_ps2ench(int argc, const char **argv)
 {
 	uint8_t ch;
 	uint8_t enable;
@@ -341,11 +336,10 @@ static int command_ps2ench(int argc, char **argv)
 
 	return 0;
 }
-DECLARE_CONSOLE_COMMAND(ps2ench, command_ps2ench,
-			"ps2_ench channel 1|0",
+DECLARE_CONSOLE_COMMAND(ps2ench, command_ps2ench, "ps2_ench channel 1|0",
 			"Enable/Disable PS/2 channel");
 
-static int command_ps2write(int argc, char **argv)
+static int command_ps2write(int argc, const char **argv)
 {
 	uint8_t ch, data;
 	char *e;
@@ -360,7 +354,6 @@ static int command_ps2write(int argc, char **argv)
 	ps2_transmit_byte(ch, data);
 	return 0;
 }
-DECLARE_CONSOLE_COMMAND(ps2write, command_ps2write,
-		"ps2_write channel data",
-		"Write data byte to PS/2 channel ");
+DECLARE_CONSOLE_COMMAND(ps2write, command_ps2write, "ps2_write channel data",
+			"Write data byte to PS/2 channel ");
 #endif
diff --git a/chip/npcx/ps2_chip.h b/chip/npcx/ps2_chip.h
index d88e6791ad..871b1ab6e5 100644
--- a/chip/npcx/ps2_chip.h
+++ b/chip/npcx/ps2_chip.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,4 +21,4 @@ void ps2_enable_channel(int channel, int enable,
 			void (*callback)(uint8_t data));
 int ps2_transmit_byte(int channel, uint8_t data);
 
-#endif  /* __CROS_EC_PS2_CHIP_H */
+#endif /* __CROS_EC_PS2_CHIP_H */
diff --git a/chip/npcx/pwm.c b/chip/npcx/pwm.c
index b2016906b3..53a278a0ba 100644
--- a/chip/npcx/pwm.c
+++ b/chip/npcx/pwm.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,7 +8,7 @@
  * On this chip, the PWM logic is implemented by the hardware FAN modules.
  */
 
-#include "assert.h"
+#include "builtin/assert.h"
 #include "clock.h"
 #include "clock_chip.h"
 #include "console.h"
@@ -23,7 +23,7 @@
 #if !(DEBUG_PWM)
 #define CPRINTS(...)
 #else
-#define CPRINTS(format, args...) cprints(CC_PWM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_PWM, format, ##args)
 #endif
 
 /* pwm resolution for each channel */
@@ -31,20 +31,20 @@ static uint32_t pwm_res[PWM_CH_COUNT];
 
 /* PWM clock source */
 enum npcx_pwm_source_clock {
-	NPCX_PWM_CLOCK_APB2_LFCLK  = 0,
-	NPCX_PWM_CLOCK_FX          = 1,
-	NPCX_PWM_CLOCK_FR          = 2,
-	NPCX_PWM_CLOCK_RESERVED    = 3,
-	NPCX_PWM_CLOCK_UNDEF       = 0xFF
+	NPCX_PWM_CLOCK_APB2_LFCLK = 0,
+	NPCX_PWM_CLOCK_FX = 1,
+	NPCX_PWM_CLOCK_FR = 2,
+	NPCX_PWM_CLOCK_RESERVED = 3,
+	NPCX_PWM_CLOCK_UNDEF = 0xFF
 };
 
 /* PWM heartbeat mode */
 enum npcx_pwm_heartbeat_mode {
-	NPCX_PWM_HBM_NORMAL    = 0,
-	NPCX_PWM_HBM_25        = 1,
-	NPCX_PWM_HBM_50        = 2,
-	NPCX_PWM_HBM_100       = 3,
-	NPCX_PWM_HBM_UNDEF     = 0xFF
+	NPCX_PWM_HBM_NORMAL = 0,
+	NPCX_PWM_HBM_25 = 1,
+	NPCX_PWM_HBM_50 = 2,
+	NPCX_PWM_HBM_100 = 3,
+	NPCX_PWM_HBM_UNDEF = 0xFF
 };
 
 /**
@@ -146,7 +146,7 @@ void pwm_set_raw_duty(enum pwm_channel ch, uint16_t duty)
 
 	/* Assume the fan control is active high and invert it ourselves */
 	UPDATE_BIT(NPCX_PWMCTL(mdl), NPCX_PWMCTL_INVP,
-			(pwm_channels[ch].flags & PWM_CONFIG_ACTIVE_LOW));
+		   (pwm_channels[ch].flags & PWM_CONFIG_ACTIVE_LOW));
 
 	CPRINTS("initial freq=0x%x", pwm_channels[ch].freq);
 	CPRINTS("duty_cycle_cnt=%d", duty);
@@ -189,7 +189,7 @@ uint16_t pwm_get_raw_duty(enum pwm_channel ch)
 		 * so scale to 0 - 0xffff
 		 */
 		return DIV_ROUND_NEAREST(NPCX_DCR(mdl) * EC_PWM_MAX_DUTY,
-						pwm_res[ch]);
+					 pwm_res[ch]);
 }
 
 /**
@@ -206,22 +206,22 @@ void pwm_config(enum pwm_channel ch)
 
 	/* Set PWM heartbeat mode is no heartbeat */
 	SET_FIELD(NPCX_PWMCTL(mdl), NPCX_PWMCTL_HB_DC_CTL_FIELD,
-			NPCX_PWM_HBM_NORMAL);
+		  NPCX_PWM_HBM_NORMAL);
 
 	/* Select default CLK or LFCLK clock input to PWM module */
 	SET_FIELD(NPCX_PWMCTLEX(mdl), NPCX_PWMCTLEX_FCK_SEL_FIELD,
-			NPCX_PWM_CLOCK_APB2_LFCLK);
+		  NPCX_PWM_CLOCK_APB2_LFCLK);
 
 	/* Set PWM polarity normal first */
 	CLEAR_BIT(NPCX_PWMCTL(mdl), NPCX_PWMCTL_INVP);
 
 	/* Select PWM clock source */
 	UPDATE_BIT(NPCX_PWMCTL(mdl), NPCX_PWMCTL_CKSEL,
-			(pwm_channels[ch].flags & PWM_CONFIG_DSLEEP));
+		   (pwm_channels[ch].flags & PWM_CONFIG_DSLEEP));
 
 	/* Select PWM IO type */
 	UPDATE_BIT(NPCX_PWMCTLEX(mdl), NPCX_PWMCTLEX_OD_OUT,
-			(pwm_channels[ch].flags & PWM_CONFIG_OPEN_DRAIN));
+		   (pwm_channels[ch].flags & PWM_CONFIG_OPEN_DRAIN));
 
 	/* Set PWM operation frequency */
 	pwm_set_freq(ch, pwm_channels[ch].freq);
diff --git a/chip/npcx/pwm_chip.h b/chip/npcx/pwm_chip.h
index 7acfef81e5..714ecfb4a3 100644
--- a/chip/npcx/pwm_chip.h
+++ b/chip/npcx/pwm_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/npcx/registers-npcx5.h b/chip/npcx/registers-npcx5.h
index c441c1c926..b7302bdd13 100644
--- a/chip/npcx/registers-npcx5.h
+++ b/chip/npcx/registers-npcx5.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,87 +19,87 @@
 #endif
 
 /* NPCX-IRQ numbers */
-#define NPCX_IRQ0_NOUSED		NPCX_IRQ_0
-#define NPCX_IRQ1_NOUSED		NPCX_IRQ_1
-#define NPCX_IRQ_KBSCAN			NPCX_IRQ_2
-#define NPCX_IRQ_PM_CHAN_OBE		NPCX_IRQ_3
-#define NPCX_IRQ_PECI			NPCX_IRQ_4
-#define NPCX_IRQ5_NOUSED		NPCX_IRQ_5
-#define NPCX_IRQ_PORT80			NPCX_IRQ_6
-#define NPCX_IRQ_MTC_WKINTAD_0		NPCX_IRQ_7
-#define NPCX_IRQ_MTC			NPCX_IRQ_MTC_WKINTAD_0
-#define NPCX_IRQ8_NOUSED		NPCX_IRQ_8
-#define NPCX_IRQ_MFT_1			NPCX_IRQ_9
-#define NPCX_IRQ_ADC			NPCX_IRQ_10
-#define NPCX_IRQ_WKINTEFGH_0		NPCX_IRQ_11
-#define NPCX_IRQ_GDMA			NPCX_IRQ_12
-#define NPCX_IRQ_SMB1			NPCX_IRQ_13
-#define NPCX_IRQ_SMB2			NPCX_IRQ_14
-#define NPCX_IRQ_WKINTC_0		NPCX_IRQ_15
-#define NPCX_IRQ16_NOUSED		NPCX_IRQ_16
-#define NPCX_IRQ_ITIM16_3		NPCX_IRQ_17
-#define NPCX_IRQ_SHI			NPCX_IRQ_18
-#define NPCX_IRQ_ESPI			NPCX_IRQ_18
-#define NPCX_IRQ19_NOUSED		NPCX_IRQ_19
-#define NPCX_IRQ20_NOUSED		NPCX_IRQ_20
-#define NPCX_IRQ_PS2			NPCX_IRQ_21
-#define NPCX_IRQ22_NOUSED		NPCX_IRQ_22
-#define NPCX_IRQ_MFT_2			NPCX_IRQ_23
-#define NPCX_IRQ_SHM			NPCX_IRQ_24
-#define NPCX_IRQ_KBC_IBF		NPCX_IRQ_25
-#define NPCX_IRQ_PM_CHAN_IBF		NPCX_IRQ_26
-#define NPCX_IRQ_ITIM16_2		NPCX_IRQ_27
-#define NPCX_IRQ_ITIM16_1		NPCX_IRQ_28
-#define NPCX_IRQ29_NOUSED		NPCX_IRQ_29
-#define NPCX_IRQ30_NOUSED		NPCX_IRQ_30
-#define NPCX_IRQ_TWD_WKINTB_0		NPCX_IRQ_31
-#define NPCX_IRQ32_NOUSED		NPCX_IRQ_32
-#define NPCX_IRQ_UART			NPCX_IRQ_33
-#define NPCX_IRQ34_NOUSED		NPCX_IRQ_34
-#define NPCX_IRQ35_NOUSED		NPCX_IRQ_35
-#define NPCX_IRQ_SMB3			NPCX_IRQ_36
-#define NPCX_IRQ_SMB4			NPCX_IRQ_37
-#define NPCX_IRQ38_NOUSED		NPCX_IRQ_38
-#define NPCX_IRQ39_NOUSED		NPCX_IRQ_39
-#define NPCX_IRQ40_NOUSED		NPCX_IRQ_40
-#define NPCX_IRQ_MFT_3			NPCX_IRQ_41
-#define NPCX_IRQ42_NOUSED		NPCX_IRQ_42
-#define NPCX_IRQ_ITIM16_4		NPCX_IRQ_43
-#define NPCX_IRQ_ITIM16_5		NPCX_IRQ_44
-#define NPCX_IRQ_ITIM16_6		NPCX_IRQ_45
-#define NPCX_IRQ_ITIM32			NPCX_IRQ_46
-#define NPCX_IRQ_WKINTA_1		NPCX_IRQ_47
-#define NPCX_IRQ_WKINTB_1		NPCX_IRQ_48
-#define NPCX_IRQ_KSI_WKINTC_1		NPCX_IRQ_49
-#define NPCX_IRQ_WKINTD_1		NPCX_IRQ_50
-#define NPCX_IRQ_WKINTE_1		NPCX_IRQ_51
-#define NPCX_IRQ_WKINTF_1		NPCX_IRQ_52
-#define NPCX_IRQ_WKINTG_1		NPCX_IRQ_53
-#define NPCX_IRQ_WKINTH_1		NPCX_IRQ_54
-#define NPCX_IRQ55_NOUSED		NPCX_IRQ_55
-#define NPCX_IRQ_KBC_OBE		NPCX_IRQ_56
-#define NPCX_IRQ_SPI			NPCX_IRQ_57
-#define NPCX_IRQ58_NOUSED		NPCX_IRQ_58
-#define NPCX_IRQ_WKINTFG_2		NPCX_IRQ_59
-#define NPCX_IRQ_WKINTA_2		NPCX_IRQ_60
-#define NPCX_IRQ_WKINTB_2		NPCX_IRQ_61
-#define NPCX_IRQ_WKINTC_2		NPCX_IRQ_62
-#define NPCX_IRQ_WKINTD_2		NPCX_IRQ_63
+#define NPCX_IRQ0_NOUSED NPCX_IRQ_0
+#define NPCX_IRQ1_NOUSED NPCX_IRQ_1
+#define NPCX_IRQ_KBSCAN NPCX_IRQ_2
+#define NPCX_IRQ_PM_CHAN_OBE NPCX_IRQ_3
+#define NPCX_IRQ_PECI NPCX_IRQ_4
+#define NPCX_IRQ5_NOUSED NPCX_IRQ_5
+#define NPCX_IRQ_PORT80 NPCX_IRQ_6
+#define NPCX_IRQ_MTC_WKINTAD_0 NPCX_IRQ_7
+#define NPCX_IRQ_MTC NPCX_IRQ_MTC_WKINTAD_0
+#define NPCX_IRQ8_NOUSED NPCX_IRQ_8
+#define NPCX_IRQ_MFT_1 NPCX_IRQ_9
+#define NPCX_IRQ_ADC NPCX_IRQ_10
+#define NPCX_IRQ_WKINTEFGH_0 NPCX_IRQ_11
+#define NPCX_IRQ_GDMA NPCX_IRQ_12
+#define NPCX_IRQ_SMB1 NPCX_IRQ_13
+#define NPCX_IRQ_SMB2 NPCX_IRQ_14
+#define NPCX_IRQ_WKINTC_0 NPCX_IRQ_15
+#define NPCX_IRQ16_NOUSED NPCX_IRQ_16
+#define NPCX_IRQ_ITIM16_3 NPCX_IRQ_17
+#define NPCX_IRQ_SHI NPCX_IRQ_18
+#define NPCX_IRQ_ESPI NPCX_IRQ_18
+#define NPCX_IRQ19_NOUSED NPCX_IRQ_19
+#define NPCX_IRQ20_NOUSED NPCX_IRQ_20
+#define NPCX_IRQ_PS2 NPCX_IRQ_21
+#define NPCX_IRQ22_NOUSED NPCX_IRQ_22
+#define NPCX_IRQ_MFT_2 NPCX_IRQ_23
+#define NPCX_IRQ_SHM NPCX_IRQ_24
+#define NPCX_IRQ_KBC_IBF NPCX_IRQ_25
+#define NPCX_IRQ_PM_CHAN_IBF NPCX_IRQ_26
+#define NPCX_IRQ_ITIM16_2 NPCX_IRQ_27
+#define NPCX_IRQ_ITIM16_1 NPCX_IRQ_28
+#define NPCX_IRQ29_NOUSED NPCX_IRQ_29
+#define NPCX_IRQ30_NOUSED NPCX_IRQ_30
+#define NPCX_IRQ_TWD_WKINTB_0 NPCX_IRQ_31
+#define NPCX_IRQ32_NOUSED NPCX_IRQ_32
+#define NPCX_IRQ_UART NPCX_IRQ_33
+#define NPCX_IRQ34_NOUSED NPCX_IRQ_34
+#define NPCX_IRQ35_NOUSED NPCX_IRQ_35
+#define NPCX_IRQ_SMB3 NPCX_IRQ_36
+#define NPCX_IRQ_SMB4 NPCX_IRQ_37
+#define NPCX_IRQ38_NOUSED NPCX_IRQ_38
+#define NPCX_IRQ39_NOUSED NPCX_IRQ_39
+#define NPCX_IRQ40_NOUSED NPCX_IRQ_40
+#define NPCX_IRQ_MFT_3 NPCX_IRQ_41
+#define NPCX_IRQ42_NOUSED NPCX_IRQ_42
+#define NPCX_IRQ_ITIM16_4 NPCX_IRQ_43
+#define NPCX_IRQ_ITIM16_5 NPCX_IRQ_44
+#define NPCX_IRQ_ITIM16_6 NPCX_IRQ_45
+#define NPCX_IRQ_ITIM32 NPCX_IRQ_46
+#define NPCX_IRQ_WKINTA_1 NPCX_IRQ_47
+#define NPCX_IRQ_WKINTB_1 NPCX_IRQ_48
+#define NPCX_IRQ_KSI_WKINTC_1 NPCX_IRQ_49
+#define NPCX_IRQ_WKINTD_1 NPCX_IRQ_50
+#define NPCX_IRQ_WKINTE_1 NPCX_IRQ_51
+#define NPCX_IRQ_WKINTF_1 NPCX_IRQ_52
+#define NPCX_IRQ_WKINTG_1 NPCX_IRQ_53
+#define NPCX_IRQ_WKINTH_1 NPCX_IRQ_54
+#define NPCX_IRQ55_NOUSED NPCX_IRQ_55
+#define NPCX_IRQ_KBC_OBE NPCX_IRQ_56
+#define NPCX_IRQ_SPI NPCX_IRQ_57
+#define NPCX_IRQ58_NOUSED NPCX_IRQ_58
+#define NPCX_IRQ_WKINTFG_2 NPCX_IRQ_59
+#define NPCX_IRQ_WKINTA_2 NPCX_IRQ_60
+#define NPCX_IRQ_WKINTB_2 NPCX_IRQ_61
+#define NPCX_IRQ_WKINTC_2 NPCX_IRQ_62
+#define NPCX_IRQ_WKINTD_2 NPCX_IRQ_63
 
 /* Modules Map */
 
 /* Miscellaneous Device Control (MDC) registers */
-#define NPCX_FWCTRL			REG8(NPCX_MDC_BASE_ADDR + 0x007)
+#define NPCX_FWCTRL REG8(NPCX_MDC_BASE_ADDR + 0x007)
 
 /* MDC register fields */
-#define NPCX_FWCTRL_RO_REGION		0
-#define NPCX_FWCTRL_FW_SLOT		1
+#define NPCX_FWCTRL_RO_REGION 0
+#define NPCX_FWCTRL_FW_SLOT 1
 
-#define NPCX_ITIM32_BASE_ADDR		0x400BC000
-#define NPCX_CR_UART_BASE_ADDR(mdl)	(0x400C4000 + ((mdl) * 0x2000L))
-#define NPCX_SMB_BASE_ADDR(mdl)	(((mdl) < 2) ? \
-				(0x40009000 + ((mdl) * 0x2000L)) : \
-				(0x400C0000 + (((mdl) - 2) * 0x2000L)))
+#define NPCX_ITIM32_BASE_ADDR 0x400BC000
+#define NPCX_CR_UART_BASE_ADDR(mdl) (0x400C4000 + ((mdl)*0x2000L))
+#define NPCX_SMB_BASE_ADDR(mdl)                         \
+	(((mdl) < 2) ? (0x40009000 + ((mdl)*0x2000L)) : \
+		       (0x400C0000 + (((mdl)-2) * 0x2000L)))
 
 enum {
 	NPCX_UART_PORT0 = 0, /* UART port 0 */
@@ -129,39 +129,39 @@ enum {
 	ALT_GROUP_COUNT
 };
 
-#define NPCX_DEVALT(n)			REG8(NPCX_SCFG_BASE_ADDR + 0x010 + (n))
+#define NPCX_DEVALT(n) REG8(NPCX_SCFG_BASE_ADDR + 0x010 + (n))
 
-#define NPCX_LV_GPIO_CTL(n)		REG8(NPCX_SCFG_BASE_ADDR + 0x02A + (n))
+#define NPCX_LV_GPIO_CTL(n) REG8(NPCX_SCFG_BASE_ADDR + 0x02A + (n))
 
 /* pin-mux for JTAG */
-#define NPCX_DEVALT5_NJEN1_EN		1
-#define NPCX_DEVALT5_NJEN0_EN		2
+#define NPCX_DEVALT5_NJEN1_EN 1
+#define NPCX_DEVALT5_NJEN0_EN 2
 
 /* pin-mux for I2C */
-#define NPCX_DEVALT2_I2C0_0_SL		0
-#define NPCX_DEVALT2_I2C0_1_SL		1
-#define NPCX_DEVALT2_I2C1_0_SL		2
-#define NPCX_DEVALT2_I2C2_0_SL		4
-#define NPCX_DEVALT2_I2C3_0_SL		6
+#define NPCX_DEVALT2_I2C0_0_SL 0
+#define NPCX_DEVALT2_I2C0_1_SL 1
+#define NPCX_DEVALT2_I2C1_0_SL 2
+#define NPCX_DEVALT2_I2C2_0_SL 4
+#define NPCX_DEVALT2_I2C3_0_SL 6
 
 /* pin-mux for UART */
-#define NPCX_DEVALTA_UART_SL1		7
-#define NPCX_DEVALTC_UART_SL2		0
+#define NPCX_DEVALTA_UART_SL1 7
+#define NPCX_DEVALTC_UART_SL2 0
 
 /* pin-mux for Misc. */
 /* External 32KHz crytal osc. input support */
-#define NPCX_DEVALTA_32KCLKIN_SL	3
+#define NPCX_DEVALTA_32KCLKIN_SL 3
 
 /* SMBus register fields */
-#define NPCX_SMBSEL_SMB0SEL		0
+#define NPCX_SMBSEL_SMB0SEL 0
 
 /* SMB enumeration: I2C port definitions. */
 enum {
-	NPCX_I2C_PORT0_0 = 0,	/* I2C port 0, bus 0 */
-	NPCX_I2C_PORT0_1,	/* I2C port 0, bus 1 */
-	NPCX_I2C_PORT1,		/* I2C port 1 */
-	NPCX_I2C_PORT2,		/* I2C port 2 */
-	NPCX_I2C_PORT3,		/* I2C port 3 */
+	NPCX_I2C_PORT0_0 = 0, /* I2C port 0, bus 0 */
+	NPCX_I2C_PORT0_1, /* I2C port 0, bus 1 */
+	NPCX_I2C_PORT1, /* I2C port 1 */
+	NPCX_I2C_PORT2, /* I2C port 2 */
+	NPCX_I2C_PORT3, /* I2C port 3 */
 	NPCX_I2C_COUNT,
 };
 
@@ -195,32 +195,31 @@ enum NPCX_PMC_PWDWN_CTL_T {
 	NPCX_PMC_PWDWN_CNT,
 };
 
-#define CGC_I2C_MASK			(BIT(NPCX_PWDWN_CTL3_SMB0_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB1_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB2_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB3_PD))
+#define CGC_I2C_MASK                                                   \
+	(BIT(NPCX_PWDWN_CTL3_SMB0_PD) | BIT(NPCX_PWDWN_CTL3_SMB1_PD) | \
+	 BIT(NPCX_PWDWN_CTL3_SMB2_PD) | BIT(NPCX_PWDWN_CTL3_SMB3_PD))
 
 /* BBRAM register fields */
 #define NPCX_BKUP_STS_ALL_MASK BIT(NPCX_BKUP_STS_IBBR)
-#define NPCX_BBRAM_SIZE			64 /* Size of BBRAM */
+#define NPCX_BBRAM_SIZE 64 /* Size of BBRAM */
 
 /* ITIM registers */
-#define NPCX_ITCNT8(n)			REG8(NPCX_ITIM_BASE_ADDR(n) + 0x000)
-#define NPCX_ITCNT16(n)			REG16(NPCX_ITIM_BASE_ADDR(n) + 0x002)
+#define NPCX_ITCNT8(n) REG8(NPCX_ITIM_BASE_ADDR(n) + 0x000)
+#define NPCX_ITCNT16(n) REG16(NPCX_ITIM_BASE_ADDR(n) + 0x002)
 /* ITIM32 registers */
-#define NPCX_ITCNT32			REG32(NPCX_ITIM32_BASE_ADDR + 0x008)
+#define NPCX_ITCNT32 REG32(NPCX_ITIM32_BASE_ADDR + 0x008)
 
 /* Timer counter register used for 1 micro-second system tick */
-#define NPCX_ITCNT_SYSTEM		NPCX_ITCNT32
+#define NPCX_ITCNT_SYSTEM NPCX_ITCNT32
 /* Timer counter register used for others */
-#define NPCX_ITCNT			NPCX_ITCNT16
+#define NPCX_ITCNT NPCX_ITCNT16
 
 /* ITIM module No. used for event */
-#define ITIM_EVENT_NO			ITIM16_1
+#define ITIM_EVENT_NO ITIM16_1
 /* ITIM module No. used for watchdog */
-#define ITIM_WDG_NO			ITIM16_5
+#define ITIM_WDG_NO ITIM16_5
 /* ITIM module No. used for 1 micro-second system tick */
-#define ITIM_SYSTEM_NO			ITIM32
+#define ITIM_SYSTEM_NO ITIM32
 
 /* ITIM enumeration */
 enum ITIM_MODULE_T {
@@ -235,11 +234,11 @@ enum ITIM_MODULE_T {
 };
 
 /* Serial Host Interface (SHI) Registers */
-#define NPCX_OBUF(n)			REG8(NPCX_SHI_BASE_ADDR + 0x020 + (n))
-#define NPCX_IBUF(n)			REG8(NPCX_SHI_BASE_ADDR + 0x060 + (n))
+#define NPCX_OBUF(n) REG8(NPCX_SHI_BASE_ADDR + 0x020 + (n))
+#define NPCX_IBUF(n) REG8(NPCX_SHI_BASE_ADDR + 0x060 + (n))
 
 /* Bit field manipulation for VWEVMS Value */
-#define VWEVMS_INTWK_EN			VWEVMS_INT_EN
+#define VWEVMS_INTWK_EN VWEVMS_INT_EN
 
 /* eSPI max supported frequency */
 enum {
@@ -253,35 +252,35 @@ enum {
 
 /* eSPI max frequency support per FMCLK */
 #if (FMCLK <= 33000000)
-#define NPCX_ESPI_MAXFREQ_MAX		NPCX_ESPI_MAXFREQ_33
+#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_33
 #elif (FMCLK <= 48000000)
-#define NPCX_ESPI_MAXFREQ_MAX		NPCX_ESPI_MAXFREQ_50
+#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_50
 #else
-#define NPCX_ESPI_MAXFREQ_MAX		NPCX_ESPI_MAXFREQ_66
+#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_66
 #endif
 
 /* MIWU registers */
-#define NPCX_WKEDG_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x00 + \
-					((n) * 2L) + ((n) < 5 ? 0 : 0x1E))
-#define NPCX_WKAEDG_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x01 + \
-					((n) * 2L) + ((n) < 5 ? 0 : 0x1E))
-#define NPCX_WKPND_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x0A + \
-					((n) * 4L) + ((n) < 5 ? 0 : 0x10))
-#define NPCX_WKPCL_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x0C + \
-					((n) * 4L) + ((n) < 5 ? 0 : 0x10))
-#define NPCX_WKEN_ADDR(port, n)		(NPCX_MIWU_BASE_ADDR(port) + 0x1E + \
-					((n) * 2L) + ((n) < 5 ? 0 : 0x12))
-#define NPCX_WKINEN_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x1F + \
-					((n) * 2L) + ((n) < 5 ? 0 : 0x12))
-#define NPCX_WKMOD_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x70 + (n))
-
-#define NPCX_WKEDG(port, n)		REG8(NPCX_WKEDG_ADDR(port, n))
-#define NPCX_WKAEDG(port, n)		REG8(NPCX_WKAEDG_ADDR(port, n))
-#define NPCX_WKPND(port, n)		REG8(NPCX_WKPND_ADDR(port, n))
-#define NPCX_WKPCL(port, n)		REG8(NPCX_WKPCL_ADDR(port, n))
-#define NPCX_WKEN(port, n)		REG8(NPCX_WKEN_ADDR(port, n))
-#define NPCX_WKINEN(port, n)		REG8(NPCX_WKINEN_ADDR(port, n))
-#define NPCX_WKMOD(port, n)		REG8(NPCX_WKMOD_ADDR(port, n))
+#define NPCX_WKEDG_ADDR(port, n) \
+	(NPCX_MIWU_BASE_ADDR(port) + 0x00 + ((n)*2L) + ((n) < 5 ? 0 : 0x1E))
+#define NPCX_WKAEDG_ADDR(port, n) \
+	(NPCX_MIWU_BASE_ADDR(port) + 0x01 + ((n)*2L) + ((n) < 5 ? 0 : 0x1E))
+#define NPCX_WKPND_ADDR(port, n) \
+	(NPCX_MIWU_BASE_ADDR(port) + 0x0A + ((n)*4L) + ((n) < 5 ? 0 : 0x10))
+#define NPCX_WKPCL_ADDR(port, n) \
+	(NPCX_MIWU_BASE_ADDR(port) + 0x0C + ((n)*4L) + ((n) < 5 ? 0 : 0x10))
+#define NPCX_WKEN_ADDR(port, n) \
+	(NPCX_MIWU_BASE_ADDR(port) + 0x1E + ((n)*2L) + ((n) < 5 ? 0 : 0x12))
+#define NPCX_WKINEN_ADDR(port, n) \
+	(NPCX_MIWU_BASE_ADDR(port) + 0x1F + ((n)*2L) + ((n) < 5 ? 0 : 0x12))
+#define NPCX_WKMOD_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x70 + (n))
+
+#define NPCX_WKEDG(port, n) REG8(NPCX_WKEDG_ADDR(port, n))
+#define NPCX_WKAEDG(port, n) REG8(NPCX_WKAEDG_ADDR(port, n))
+#define NPCX_WKPND(port, n) REG8(NPCX_WKPND_ADDR(port, n))
+#define NPCX_WKPCL(port, n) REG8(NPCX_WKPCL_ADDR(port, n))
+#define NPCX_WKEN(port, n) REG8(NPCX_WKEN_ADDR(port, n))
+#define NPCX_WKINEN(port, n) REG8(NPCX_WKINEN_ADDR(port, n))
+#define NPCX_WKMOD(port, n) REG8(NPCX_WKMOD_ADDR(port, n))
 
 /* UART registers and functions */
 #if NPCX_UART_MODULE2
@@ -289,22 +288,22 @@ enum {
  * To be used as 2nd parameter to NPCX_WK*() macro, table (1st parameter) is
  * always 1 == MIWU_TABLE_1.
  */
-#define NPCX_UART_WK_GROUP		6
-#define NPCX_UART_WK_BIT		4
-#define NPCX_UART_MIWU_IRQ		NPCX_IRQ_WKINTG_1
-#define NPCX_UART_DEVALT		NPCX_DEVALT(0x0C)
-#define NPCX_UART_DEVALT_SL		NPCX_DEVALTC_UART_SL2
-#define NPCX_UART_ALT_DEVALT		NPCX_DEVALT(0x0A)
-#define NPCX_UART_ALT_DEVALT_SL		NPCX_DEVALTA_UART_SL1
+#define NPCX_UART_WK_GROUP 6
+#define NPCX_UART_WK_BIT 4
+#define NPCX_UART_MIWU_IRQ NPCX_IRQ_WKINTG_1
+#define NPCX_UART_DEVALT NPCX_DEVALT(0x0C)
+#define NPCX_UART_DEVALT_SL NPCX_DEVALTC_UART_SL2
+#define NPCX_UART_ALT_DEVALT NPCX_DEVALT(0x0A)
+#define NPCX_UART_ALT_DEVALT_SL NPCX_DEVALTA_UART_SL1
 #else /* !NPCX_UART_MODULE2 */
 
-#define NPCX_UART_WK_GROUP		1
-#define NPCX_UART_WK_BIT		0
-#define NPCX_UART_MIWU_IRQ		NPCX_IRQ_WKINTB_1
-#define NPCX_UART_DEVALT		NPCX_DEVALT(0x0A)
-#define NPCX_UART_DEVALT_SL		NPCX_DEVALTA_UART_SL1
-#define NPCX_UART_ALT_DEVALT		NPCX_DEVALT(0x0C)
-#define NPCX_UART_ALT_DEVALT_SL		NPCX_DEVALTC_UART_SL2
+#define NPCX_UART_WK_GROUP 1
+#define NPCX_UART_WK_BIT 0
+#define NPCX_UART_MIWU_IRQ NPCX_IRQ_WKINTB_1
+#define NPCX_UART_DEVALT NPCX_DEVALT(0x0A)
+#define NPCX_UART_DEVALT_SL NPCX_DEVALTA_UART_SL1
+#define NPCX_UART_ALT_DEVALT NPCX_DEVALT(0x0C)
+#define NPCX_UART_ALT_DEVALT_SL NPCX_DEVALTC_UART_SL2
 #endif /* NPCX_UART_MODULE2 */
 
 /* This routine checks pending bit of GPIO wake-up functionality */
@@ -328,8 +327,7 @@ static inline void uart_clear_pending_wakeup(void)
 /* This routine enables wake-up functionality from GPIO on UART rx pin */
 static inline void uart_enable_wakeup(int enable)
 {
-	UPDATE_BIT(NPCX_WKEN(1, NPCX_UART_WK_GROUP), NPCX_UART_WK_BIT,
-		enable);
+	UPDATE_BIT(NPCX_WKEN(1, NPCX_UART_WK_GROUP), NPCX_UART_WK_BIT, enable);
 }
 
 /* This routine checks functionality is UART rx or not */
@@ -339,50 +337,50 @@ static inline int npcx_is_uart(void)
 }
 
 /* ADC Registers */
-#define NPCX_ADCSTS		REG16(NPCX_ADC_BASE_ADDR + 0x000)
-#define NPCX_ADCCNF		REG16(NPCX_ADC_BASE_ADDR + 0x002)
-#define NPCX_ATCTL		REG16(NPCX_ADC_BASE_ADDR + 0x004)
-#define NPCX_ASCADD		REG16(NPCX_ADC_BASE_ADDR + 0x006)
-#define NPCX_ADCCS		REG16(NPCX_ADC_BASE_ADDR + 0x008)
+#define NPCX_ADCSTS REG16(NPCX_ADC_BASE_ADDR + 0x000)
+#define NPCX_ADCCNF REG16(NPCX_ADC_BASE_ADDR + 0x002)
+#define NPCX_ATCTL REG16(NPCX_ADC_BASE_ADDR + 0x004)
+#define NPCX_ASCADD REG16(NPCX_ADC_BASE_ADDR + 0x006)
+#define NPCX_ADCCS REG16(NPCX_ADC_BASE_ADDR + 0x008)
 /* NOTE: These are 1-based for the threshold detectors. */
-#define NPCX_THRCTL(n)		REG16(NPCX_ADC_BASE_ADDR + 0x012 + (2L*(n)))
-#define NPCX_THRCTS		REG16(NPCX_ADC_BASE_ADDR + 0x01A)
-#define NPCX_THR_DCTL(n)	REG16(NPCX_ADC_BASE_ADDR + 0x038 + (2L*(n)))
+#define NPCX_THRCTL(n) REG16(NPCX_ADC_BASE_ADDR + 0x012 + (2L * (n)))
+#define NPCX_THRCTS REG16(NPCX_ADC_BASE_ADDR + 0x01A)
+#define NPCX_THR_DCTL(n) REG16(NPCX_ADC_BASE_ADDR + 0x038 + (2L * (n)))
 /* NOTE: This is 0-based for the ADC channels. */
-#define NPCX_CHNDAT(n)		REG16(NPCX_ADC_BASE_ADDR + 0x040 + (2L*(n)))
-#define NPCX_ADCCNF2		REG16(NPCX_ADC_BASE_ADDR + 0x020)
-#define NPCX_GENDLY		REG16(NPCX_ADC_BASE_ADDR + 0x022)
-#define NPCX_MEAST		REG16(NPCX_ADC_BASE_ADDR + 0x026)
+#define NPCX_CHNDAT(n) REG16(NPCX_ADC_BASE_ADDR + 0x040 + (2L * (n)))
+#define NPCX_ADCCNF2 REG16(NPCX_ADC_BASE_ADDR + 0x020)
+#define NPCX_GENDLY REG16(NPCX_ADC_BASE_ADDR + 0x022)
+#define NPCX_MEAST REG16(NPCX_ADC_BASE_ADDR + 0x026)
 
 /* ADC register fields */
-#define NPCX_ATCTL_SCLKDIV_FIELD	FIELD(0, 6)
-#define NPCX_ATCTL_DLY_FIELD		FIELD(8, 3)
-#define NPCX_ASCADD_SADDR_FIELD		FIELD(0, 5)
-#define NPCX_ADCSTS_EOCEV		0
-#define NPCX_ADCCNF_ADCMD_FIELD		FIELD(1, 2)
-#define NPCX_ADCCNF_ADCRPTC		3
-#define NPCX_ADCCNF_INTECEN		6
-#define NPCX_ADCCNF_START		4
-#define NPCX_ADCCNF_ADCEN		0
-#define NPCX_ADCCNF_STOP		11
-#define NPCX_CHNDAT_CHDAT_FIELD		FIELD(0, 10)
-#define NPCX_CHNDAT_NEW			15
-#define NPCX_THRCTL_THEN		15
-#define NPCX_THRCTL_L_H			14
-#define NPCX_THRCTL_CHNSEL		FIELD(10, 4)
-#define NPCX_THRCTL_THRVAL		FIELD(0, 10)
-#define NPCX_THRCTS_ADC_WKEN		15
-#define NPCX_THRCTS_THR3_IEN		10
-#define NPCX_THRCTS_THR2_IEN		9
-#define NPCX_THRCTS_THR1_IEN		8
-#define NPCX_THRCTS_ADC_EVENT		7
-#define NPCX_THRCTS_THR3_STS		2
-#define NPCX_THRCTS_THR2_STS		1
-#define NPCX_THRCTS_THR1_STS		0
-#define NPCX_THR_DCTL_THRD_EN		15
-#define NPCX_THR_DCTL_THR_DVAL		FIELD(0, 10)
-
-#define NPCX_ADC_THRESH1		1
-#define NPCX_ADC_THRESH2		2
-#define NPCX_ADC_THRESH3		3
-#define NPCX_ADC_THRESH_CNT		3
+#define NPCX_ATCTL_SCLKDIV_FIELD FIELD(0, 6)
+#define NPCX_ATCTL_DLY_FIELD FIELD(8, 3)
+#define NPCX_ASCADD_SADDR_FIELD FIELD(0, 5)
+#define NPCX_ADCSTS_EOCEV 0
+#define NPCX_ADCCNF_ADCMD_FIELD FIELD(1, 2)
+#define NPCX_ADCCNF_ADCRPTC 3
+#define NPCX_ADCCNF_INTECEN 6
+#define NPCX_ADCCNF_START 4
+#define NPCX_ADCCNF_ADCEN 0
+#define NPCX_ADCCNF_STOP 11
+#define NPCX_CHNDAT_CHDAT_FIELD FIELD(0, 10)
+#define NPCX_CHNDAT_NEW 15
+#define NPCX_THRCTL_THEN 15
+#define NPCX_THRCTL_L_H 14
+#define NPCX_THRCTL_CHNSEL FIELD(10, 4)
+#define NPCX_THRCTL_THRVAL FIELD(0, 10)
+#define NPCX_THRCTS_ADC_WKEN 15
+#define NPCX_THRCTS_THR3_IEN 10
+#define NPCX_THRCTS_THR2_IEN 9
+#define NPCX_THRCTS_THR1_IEN 8
+#define NPCX_THRCTS_ADC_EVENT 7
+#define NPCX_THRCTS_THR3_STS 2
+#define NPCX_THRCTS_THR2_STS 1
+#define NPCX_THRCTS_THR1_STS 0
+#define NPCX_THR_DCTL_THRD_EN 15
+#define NPCX_THR_DCTL_THR_DVAL FIELD(0, 10)
+
+#define NPCX_ADC_THRESH1 1
+#define NPCX_ADC_THRESH2 2
+#define NPCX_ADC_THRESH3 3
+#define NPCX_ADC_THRESH_CNT 3
diff --git a/chip/npcx/registers-npcx7.h b/chip/npcx/registers-npcx7.h
index 535abfbf0f..2a4334149f 100644
--- a/chip/npcx/registers-npcx7.h
+++ b/chip/npcx/registers-npcx7.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,106 +24,104 @@
 #endif
 
 /* NPCX-IRQ numbers */
-#define NPCX_IRQ0_NOUSED		NPCX_IRQ_0
-#define NPCX_IRQ1_NOUSED		NPCX_IRQ_1
-#define NPCX_IRQ_KBSCAN			NPCX_IRQ_2
-#define NPCX_IRQ_PM_CHAN_OBE		NPCX_IRQ_3
+#define NPCX_IRQ0_NOUSED NPCX_IRQ_0
+#define NPCX_IRQ1_NOUSED NPCX_IRQ_1
+#define NPCX_IRQ_KBSCAN NPCX_IRQ_2
+#define NPCX_IRQ_PM_CHAN_OBE NPCX_IRQ_3
 #ifdef NPCX_WOV_SUPPORT
-#define NPCX_IRQ4_NOUSED		NPCX_IRQ_4
+#define NPCX_IRQ4_NOUSED NPCX_IRQ_4
 #else
-#define NPCX_IRQ_PECI			NPCX_IRQ_4
+#define NPCX_IRQ_PECI NPCX_IRQ_4
 #endif
-#define NPCX_IRQ5_NOUSED		NPCX_IRQ_5
-#define NPCX_IRQ_PORT80			NPCX_IRQ_6
-#define NPCX_IRQ_MTC_WKINTAD_0		NPCX_IRQ_7
-#define NPCX_IRQ_MTC			NPCX_IRQ_MTC_WKINTAD_0
-#define NPCX_IRQ_SMB8			NPCX_IRQ_8
-#define NPCX_IRQ_MFT_1			NPCX_IRQ_9
-#define NPCX_IRQ_ADC			NPCX_IRQ_10
-#define NPCX_IRQ_WKINTEFGH_0		NPCX_IRQ_11
-#define NPCX_IRQ_GDMA			NPCX_IRQ_12
-#define NPCX_IRQ_SMB1			NPCX_IRQ_13
-#define NPCX_IRQ_SMB2			NPCX_IRQ_14
-#define NPCX_IRQ_WKINTC_0		NPCX_IRQ_15
-#define NPCX_IRQ_SMB7			NPCX_IRQ_16
-#define NPCX_IRQ_ITIM16_3		NPCX_IRQ_17
-#define NPCX_IRQ_SHI			NPCX_IRQ_18
-#define NPCX_IRQ_ESPI			NPCX_IRQ_18
-#define NPCX_IRQ_SMB5			NPCX_IRQ_19
-#define NPCX_IRQ_SMB6			NPCX_IRQ_20
-#define NPCX_IRQ_PS2			NPCX_IRQ_21
+#define NPCX_IRQ5_NOUSED NPCX_IRQ_5
+#define NPCX_IRQ_PORT80 NPCX_IRQ_6
+#define NPCX_IRQ_MTC_WKINTAD_0 NPCX_IRQ_7
+#define NPCX_IRQ_MTC NPCX_IRQ_MTC_WKINTAD_0
+#define NPCX_IRQ_SMB8 NPCX_IRQ_8
+#define NPCX_IRQ_MFT_1 NPCX_IRQ_9
+#define NPCX_IRQ_ADC NPCX_IRQ_10
+#define NPCX_IRQ_WKINTEFGH_0 NPCX_IRQ_11
+#define NPCX_IRQ_GDMA NPCX_IRQ_12
+#define NPCX_IRQ_SMB1 NPCX_IRQ_13
+#define NPCX_IRQ_SMB2 NPCX_IRQ_14
+#define NPCX_IRQ_WKINTC_0 NPCX_IRQ_15
+#define NPCX_IRQ_SMB7 NPCX_IRQ_16
+#define NPCX_IRQ_ITIM16_3 NPCX_IRQ_17
+#define NPCX_IRQ_SHI NPCX_IRQ_18
+#define NPCX_IRQ_ESPI NPCX_IRQ_18
+#define NPCX_IRQ_SMB5 NPCX_IRQ_19
+#define NPCX_IRQ_SMB6 NPCX_IRQ_20
+#define NPCX_IRQ_PS2 NPCX_IRQ_21
 #ifdef NPCX_WOV_SUPPORT
-#define NPCX_IRQ_WOV			NPCX_IRQ_22
+#define NPCX_IRQ_WOV NPCX_IRQ_22
 #else
-#define NPCX_IRQ22_NOUSED		NPCX_IRQ_22
+#define NPCX_IRQ22_NOUSED NPCX_IRQ_22
 #endif
-#define NPCX_IRQ_MFT_2			NPCX_IRQ_23
-#define NPCX_IRQ_SHM			NPCX_IRQ_24
-#define NPCX_IRQ_KBC_IBF		NPCX_IRQ_25
-#define NPCX_IRQ_PM_CHAN_IBF		NPCX_IRQ_26
-#define NPCX_IRQ_ITIM16_2		NPCX_IRQ_27
-#define NPCX_IRQ_ITIM16_1		NPCX_IRQ_28
-#define NPCX_IRQ29_NOUSED		NPCX_IRQ_29
-#define NPCX_IRQ30_NOUSED		NPCX_IRQ_30
-#define NPCX_IRQ_TWD_WKINTB_0		NPCX_IRQ_31
-#define NPCX_IRQ_UART2			NPCX_IRQ_32
-#define NPCX_IRQ_UART			NPCX_IRQ_33
-#define NPCX_IRQ34_NOUSED		NPCX_IRQ_34
-#define NPCX_IRQ35_NOUSED		NPCX_IRQ_35
-#define NPCX_IRQ_SMB3			NPCX_IRQ_36
-#define NPCX_IRQ_SMB4			NPCX_IRQ_37
-#define NPCX_IRQ38_NOUSED		NPCX_IRQ_38
-#define NPCX_IRQ39_NOUSED		NPCX_IRQ_39
-#define NPCX_IRQ40_NOUSED		NPCX_IRQ_40
-#define NPCX_IRQ_MFT_3			NPCX_IRQ_41
-#define NPCX_IRQ42_NOUSED		NPCX_IRQ_42
-#define NPCX_IRQ_ITIM16_4		NPCX_IRQ_43
-#define NPCX_IRQ_ITIM16_5		NPCX_IRQ_44
-#define NPCX_IRQ_ITIM16_6		NPCX_IRQ_45
-#define NPCX_IRQ_ITIM32			NPCX_IRQ_46
-#define NPCX_IRQ_WKINTA_1		NPCX_IRQ_47
-#define NPCX_IRQ_WKINTB_1		NPCX_IRQ_48
-#define NPCX_IRQ_KSI_WKINTC_1		NPCX_IRQ_49
-#define NPCX_IRQ_WKINTD_1		NPCX_IRQ_50
-#define NPCX_IRQ_WKINTE_1		NPCX_IRQ_51
-#define NPCX_IRQ_WKINTF_1		NPCX_IRQ_52
-#define NPCX_IRQ_WKINTG_1		NPCX_IRQ_53
-#define NPCX_IRQ_WKINTH_1		NPCX_IRQ_54
-#define NPCX_IRQ55_NOUSED		NPCX_IRQ_55
-#define NPCX_IRQ_KBC_OBE		NPCX_IRQ_56
-#define NPCX_IRQ_SPI			NPCX_IRQ_57
+#define NPCX_IRQ_MFT_2 NPCX_IRQ_23
+#define NPCX_IRQ_SHM NPCX_IRQ_24
+#define NPCX_IRQ_KBC_IBF NPCX_IRQ_25
+#define NPCX_IRQ_PM_CHAN_IBF NPCX_IRQ_26
+#define NPCX_IRQ_ITIM16_2 NPCX_IRQ_27
+#define NPCX_IRQ_ITIM16_1 NPCX_IRQ_28
+#define NPCX_IRQ29_NOUSED NPCX_IRQ_29
+#define NPCX_IRQ30_NOUSED NPCX_IRQ_30
+#define NPCX_IRQ_TWD_WKINTB_0 NPCX_IRQ_31
+#define NPCX_IRQ_UART2 NPCX_IRQ_32
+#define NPCX_IRQ_UART NPCX_IRQ_33
+#define NPCX_IRQ34_NOUSED NPCX_IRQ_34
+#define NPCX_IRQ35_NOUSED NPCX_IRQ_35
+#define NPCX_IRQ_SMB3 NPCX_IRQ_36
+#define NPCX_IRQ_SMB4 NPCX_IRQ_37
+#define NPCX_IRQ38_NOUSED NPCX_IRQ_38
+#define NPCX_IRQ39_NOUSED NPCX_IRQ_39
+#define NPCX_IRQ40_NOUSED NPCX_IRQ_40
+#define NPCX_IRQ_MFT_3 NPCX_IRQ_41
+#define NPCX_IRQ42_NOUSED NPCX_IRQ_42
+#define NPCX_IRQ_ITIM16_4 NPCX_IRQ_43
+#define NPCX_IRQ_ITIM16_5 NPCX_IRQ_44
+#define NPCX_IRQ_ITIM16_6 NPCX_IRQ_45
+#define NPCX_IRQ_ITIM32 NPCX_IRQ_46
+#define NPCX_IRQ_WKINTA_1 NPCX_IRQ_47
+#define NPCX_IRQ_WKINTB_1 NPCX_IRQ_48
+#define NPCX_IRQ_KSI_WKINTC_1 NPCX_IRQ_49
+#define NPCX_IRQ_WKINTD_1 NPCX_IRQ_50
+#define NPCX_IRQ_WKINTE_1 NPCX_IRQ_51
+#define NPCX_IRQ_WKINTF_1 NPCX_IRQ_52
+#define NPCX_IRQ_WKINTG_1 NPCX_IRQ_53
+#define NPCX_IRQ_WKINTH_1 NPCX_IRQ_54
+#define NPCX_IRQ55_NOUSED NPCX_IRQ_55
+#define NPCX_IRQ_KBC_OBE NPCX_IRQ_56
+#define NPCX_IRQ_SPI NPCX_IRQ_57
 #ifdef NPCX_ITIM64_SUPPORT
-#define NPCX_IRQ_ITIM64			NPCX_IRQ_58
+#define NPCX_IRQ_ITIM64 NPCX_IRQ_58
 #else
-#define NPCX_IRQ58_NOUSED		NPCX_IRQ_58
+#define NPCX_IRQ58_NOUSED NPCX_IRQ_58
 #endif
-#define NPCX_IRQ_WKINTFG_2		NPCX_IRQ_59
-#define NPCX_IRQ_WKINTA_2		NPCX_IRQ_60
-#define NPCX_IRQ_WKINTB_2		NPCX_IRQ_61
-#define NPCX_IRQ_WKINTC_2		NPCX_IRQ_62
-#define NPCX_IRQ_WKINTD_2		NPCX_IRQ_63
+#define NPCX_IRQ_WKINTFG_2 NPCX_IRQ_59
+#define NPCX_IRQ_WKINTA_2 NPCX_IRQ_60
+#define NPCX_IRQ_WKINTB_2 NPCX_IRQ_61
+#define NPCX_IRQ_WKINTC_2 NPCX_IRQ_62
+#define NPCX_IRQ_WKINTD_2 NPCX_IRQ_63
 
 /* Modules Map */
 
 /* Miscellaneous Device Control (MDC) registers */
-#define NPCX_FWCTRL			REG8(NPCX_MDC_BASE_ADDR + 0x007)
+#define NPCX_FWCTRL REG8(NPCX_MDC_BASE_ADDR + 0x007)
 
 /* MDC register fields */
-#define NPCX_FWCTRL_RO_REGION		0
-#define NPCX_FWCTRL_FW_SLOT		1
-
-#define NPCX_ITIM32_BASE_ADDR		0x400BC000
-#define NPCX_CR_UART_BASE_ADDR(mdl)	(0x400C4000 + ((mdl) * 0x2000L))
-#define NPCX_SMB_BASE_ADDR(mdl)		(((mdl) < 2) ? \
-				(0x40009000 +	((mdl) * 0x2000L)) : \
-				((mdl) < 4) ? \
-				(0x400C0000 + (((mdl) - 2) * 0x2000L)) : \
-				((mdl) == 4) ? \
-				(0x40008000) : \
-				(0x40017000 + (((mdl) - 5) * 0x1000L)))
-
-#define NPCX_HFCBCD1			REG8(NPCX_HFCG_BASE_ADDR + 0x012)
-#define NPCX_HFCBCD2			REG8(NPCX_HFCG_BASE_ADDR + 0x014)
+#define NPCX_FWCTRL_RO_REGION 0
+#define NPCX_FWCTRL_FW_SLOT 1
+
+#define NPCX_ITIM32_BASE_ADDR 0x400BC000
+#define NPCX_CR_UART_BASE_ADDR(mdl) (0x400C4000 + ((mdl)*0x2000L))
+#define NPCX_SMB_BASE_ADDR(mdl)                                \
+	(((mdl) < 2)  ? (0x40009000 + ((mdl)*0x2000L)) :       \
+	 ((mdl) < 4)  ? (0x400C0000 + (((mdl)-2) * 0x2000L)) : \
+	 ((mdl) == 4) ? (0x40008000) :                         \
+			(0x40017000 + (((mdl)-5) * 0x1000L)))
+
+#define NPCX_HFCBCD1 REG8(NPCX_HFCG_BASE_ADDR + 0x012)
+#define NPCX_HFCBCD2 REG8(NPCX_HFCG_BASE_ADDR + 0x014)
 
 enum {
 	NPCX_UART_PORT0 = 0, /* UART port 0 */
@@ -135,44 +133,44 @@ enum {
 
 #ifdef NPCX_UART_FIFO_SUPPORT
 /* UART registers only used for FIFO mode */
-#define NPCX_UFTSTS(n)			REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x020)
-#define NPCX_UFRSTS(n)			REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x022)
-#define NPCX_UFTCTL(n)			REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x024)
-#define NPCX_UFRCTL(n)			REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x026)
+#define NPCX_UFTSTS(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x020)
+#define NPCX_UFRSTS(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x022)
+#define NPCX_UFTCTL(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x024)
+#define NPCX_UFRCTL(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x026)
 
 /* UART FIFO register fields */
-#define NPCX_UMDSL_FIFO_MD		0
-
-#define NPCX_UFTSTS_TEMPTY_LVL		FIELD(0, 5)
-#define NPCX_UFTSTS_TEMPTY_LVL_STS	5
-#define NPCX_UFTSTS_TFIFO_EMPTY_STS	6
-#define NPCX_UFTSTS_NXMIP		7
-
-#define NPCX_UFRSTS_RFULL_LVL_STS	5
-#define NPCX_UFRSTS_RFIFO_NEMPTY_STS	6
-#define NPCX_UFRSTS_ERR			7
-
-#define NPCX_UFTCTL_TEMPTY_LVL_SEL	FIELD(0, 5)
-#define NPCX_UFTCTL_TEMPTY_LVL_EN	5
-#define NPCX_UFTCTL_TEMPTY_EN		6
-#define NPCX_UFTCTL_NXMIPEN		7
-
-#define NPCX_UFRCTL_RFULL_LVL_SEL	FIELD(0, 5)
-#define NPCX_UFRCTL_RFULL_LVL_EN	5
-#define NPCX_UFRCTL_RNEMPTY_EN		6
-#define NPCX_UFRCTL_ERR_EN		7
+#define NPCX_UMDSL_FIFO_MD 0
+
+#define NPCX_UFTSTS_TEMPTY_LVL FIELD(0, 5)
+#define NPCX_UFTSTS_TEMPTY_LVL_STS 5
+#define NPCX_UFTSTS_TFIFO_EMPTY_STS 6
+#define NPCX_UFTSTS_NXMIP 7
+
+#define NPCX_UFRSTS_RFULL_LVL_STS 5
+#define NPCX_UFRSTS_RFIFO_NEMPTY_STS 6
+#define NPCX_UFRSTS_ERR 7
+
+#define NPCX_UFTCTL_TEMPTY_LVL_SEL FIELD(0, 5)
+#define NPCX_UFTCTL_TEMPTY_LVL_EN 5
+#define NPCX_UFTCTL_TEMPTY_EN 6
+#define NPCX_UFTCTL_NXMIPEN 7
+
+#define NPCX_UFRCTL_RFULL_LVL_SEL FIELD(0, 5)
+#define NPCX_UFRCTL_RFULL_LVL_EN 5
+#define NPCX_UFRCTL_RNEMPTY_EN 6
+#define NPCX_UFRCTL_ERR_EN 7
 #endif
 
 /* KBSCAN register fields */
-#define NPCX_KBHDRV_FIELD		FIELD(6, 2)
+#define NPCX_KBHDRV_FIELD FIELD(6, 2)
 
 /* GLUE registers */
 #ifdef NPCX_PSL_MODE_SUPPORT
-#define NPCX_GLUE_PSL_CTS		REG8(NPCX_GLUE_REGS_BASE + 0x027)
+#define NPCX_GLUE_PSL_CTS REG8(NPCX_GLUE_REGS_BASE + 0x027)
 #endif
 
 /* GPIO registers */
-#define NPCX_PLOCK_CTL(n)		REG8(NPCX_GPIO_BASE_ADDR(n) + 0x007)
+#define NPCX_PLOCK_CTL(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x007)
 
 /* System Configuration (SCFG) Registers */
 
@@ -197,112 +195,112 @@ enum {
 	ALT_GROUP_COUNT
 };
 
-#define NPCX_DEVALT(n)			REG8(NPCX_SCFG_BASE_ADDR + 0x010 + (n))
+#define NPCX_DEVALT(n) REG8(NPCX_SCFG_BASE_ADDR + 0x010 + (n))
 
-#define NPCX_LV_GPIO_CTL_ADDR(n)	(((n) < 5) ? \
-					(NPCX_SCFG_BASE_ADDR + 0x02A + (n)) :\
-					(NPCX_SCFG_BASE_ADDR + 0x026))
-#define NPCX_LV_GPIO_CTL(n)		REG8(NPCX_LV_GPIO_CTL_ADDR(n))
+#define NPCX_LV_GPIO_CTL_ADDR(n)                           \
+	(((n) < 5) ? (NPCX_SCFG_BASE_ADDR + 0x02A + (n)) : \
+		     (NPCX_SCFG_BASE_ADDR + 0x026))
+#define NPCX_LV_GPIO_CTL(n) REG8(NPCX_LV_GPIO_CTL_ADDR(n))
 
 /* pin-mux for I2C */
-#define NPCX_DEVALT2_I2C0_0_SL		0
-#define NPCX_DEVALT2_I2C7_0_SL		1
-#define NPCX_DEVALT2_I2C1_0_SL		2
-#define NPCX_DEVALT2_I2C6_0_SL		3
-#define NPCX_DEVALT2_I2C2_0_SL		4
-#define NPCX_DEVALT2_I2C5_0_SL		5
-#define NPCX_DEVALT2_I2C3_0_SL		6
-#define NPCX_DEVALT2_I2C4_0_SL		7
-#define NPCX_DEVALT6_I2C6_1_SL		5
-#define NPCX_DEVALT6_I2C5_1_SL		6
-#define NPCX_DEVALT6_I2C4_1_SL		7
+#define NPCX_DEVALT2_I2C0_0_SL 0
+#define NPCX_DEVALT2_I2C7_0_SL 1
+#define NPCX_DEVALT2_I2C1_0_SL 2
+#define NPCX_DEVALT2_I2C6_0_SL 3
+#define NPCX_DEVALT2_I2C2_0_SL 4
+#define NPCX_DEVALT2_I2C5_0_SL 5
+#define NPCX_DEVALT2_I2C3_0_SL 6
+#define NPCX_DEVALT2_I2C4_0_SL 7
+#define NPCX_DEVALT6_I2C6_1_SL 5
+#define NPCX_DEVALT6_I2C5_1_SL 6
+#define NPCX_DEVALT6_I2C4_1_SL 7
 
 /* pin-mux for JTAG */
-#define NPCX_DEVALT5_NJEN1_EN		1
-#define NPCX_DEVALT5_NJEN0_EN		2
+#define NPCX_DEVALT5_NJEN1_EN 1
+#define NPCX_DEVALT5_NJEN0_EN 2
 
 /* pin-mux for ADC */
-#define NPCX_DEVALTF_ADC5_SL		0
-#define NPCX_DEVALTF_ADC6_SL		1
-#define NPCX_DEVALTF_ADC7_SL		2
-#define NPCX_DEVALTF_ADC8_SL		3
-#define NPCX_DEVALTF_ADC9_SL		4
+#define NPCX_DEVALTF_ADC5_SL 0
+#define NPCX_DEVALTF_ADC6_SL 1
+#define NPCX_DEVALTF_ADC7_SL 2
+#define NPCX_DEVALTF_ADC8_SL 3
+#define NPCX_DEVALTF_ADC9_SL 4
 
 /* pin-mux for PSL */
 #ifdef NPCX_PSL_MODE_SUPPORT
-#define NPCX_DEVALTD_PSL_IN1_AHI	0
-#define NPCX_DEVALTD_NPSL_IN1_SL	1
-#define NPCX_DEVALTD_PSL_IN2_AHI	2
-#define NPCX_DEVALTD_NPSL_IN2_SL	3
-#define NPCX_DEVALTD_PSL_IN3_AHI	4
-#define NPCX_DEVALTD_PSL_IN3_SL		5
-#define NPCX_DEVALTD_PSL_IN4_AHI	6
-#define NPCX_DEVALTD_PSL_IN4_SL		7
+#define NPCX_DEVALTD_PSL_IN1_AHI 0
+#define NPCX_DEVALTD_NPSL_IN1_SL 1
+#define NPCX_DEVALTD_PSL_IN2_AHI 2
+#define NPCX_DEVALTD_NPSL_IN2_SL 3
+#define NPCX_DEVALTD_PSL_IN3_AHI 4
+#define NPCX_DEVALTD_PSL_IN3_SL 5
+#define NPCX_DEVALTD_PSL_IN4_AHI 6
+#define NPCX_DEVALTD_PSL_IN4_SL 7
 #endif
 
 #ifdef CHIP_VARIANT_NPCX7M6G
 /* External 32KHz crytal osc. input support */
-#define NPCX_DEVALTA_32KCLKIN_SL	3
+#define NPCX_DEVALTA_32KCLKIN_SL 3
 #endif
 
 /* pin-mux for UART */
-#define NPCX_DEVALTA_UART_SL1		7
-#define NPCX_DEVALTC_UART_SL2		0
+#define NPCX_DEVALTA_UART_SL1 7
+#define NPCX_DEVALTC_UART_SL2 0
 #ifdef NPCX_SECOND_UART
 /* Secondary UART selection */
-#define NPCX_DEVALTA_UART2_SL		5
+#define NPCX_DEVALTA_UART2_SL 5
 #endif
 
 /* SHI module version 2 enable bit */
-#define NPCX_DEVALTF_SHI_NEW		7
+#define NPCX_DEVALTF_SHI_NEW 7
 
 #ifdef NPCX_WOV_SUPPORT
 /* pin-mux for WoV */
-#define NPCX_DEVALTE_WOV_SL		0
-#define NPCX_DEVALTE_I2S_SL		1
-#define NPCX_DEVALTE_DMCLK_FAST		2
+#define NPCX_DEVALTE_WOV_SL 0
+#define NPCX_DEVALTE_I2S_SL 1
+#define NPCX_DEVALTE_DMCLK_FAST 2
 #endif
 
 /* SMBus register fields */
-#define NPCX_SMBSEL_SMB4SEL		4
-#define NPCX_SMBSEL_SMB5SEL		5
-#define NPCX_SMBSEL_SMB6SEL		6
+#define NPCX_SMBSEL_SMB4SEL 4
+#define NPCX_SMBSEL_SMB5SEL 5
+#define NPCX_SMBSEL_SMB6SEL 6
 
 /* SMB enumeration: I2C port definitions */
 enum {
-	NPCX_I2C_PORT0_0 = 0,	/* I2C port 0, bus 0 */
-	NPCX_I2C_PORT1_0,	/* I2C port 1, bus 0 */
-	NPCX_I2C_PORT2_0,	/* I2C port 2, bus 0 */
-	NPCX_I2C_PORT3_0,	/* I2C port 3, bus 0 */
+	NPCX_I2C_PORT0_0 = 0, /* I2C port 0, bus 0 */
+	NPCX_I2C_PORT1_0, /* I2C port 1, bus 0 */
+	NPCX_I2C_PORT2_0, /* I2C port 2, bus 0 */
+	NPCX_I2C_PORT3_0, /* I2C port 3, bus 0 */
 #ifdef CHIP_VARIANT_NPCX7M6G
-	NPCX_I2C_PORT4_0,	/* I2C port 4, bus 0 */
+	NPCX_I2C_PORT4_0, /* I2C port 4, bus 0 */
 #endif
-	NPCX_I2C_PORT4_1,	/* I2C port 4, bus 1 */
-	NPCX_I2C_PORT5_0,	/* I2C port 5, bus 0 */
-	NPCX_I2C_PORT5_1,	/* I2C port 5, bus 1 */
-	NPCX_I2C_PORT6_0,	/* I2C port 6, bus 0 */
-	NPCX_I2C_PORT6_1,	/* I2C port 6, bus 1 */
-	NPCX_I2C_PORT7_0,	/* I2C port 7, bus 0 */
+	NPCX_I2C_PORT4_1, /* I2C port 4, bus 1 */
+	NPCX_I2C_PORT5_0, /* I2C port 5, bus 0 */
+	NPCX_I2C_PORT5_1, /* I2C port 5, bus 1 */
+	NPCX_I2C_PORT6_0, /* I2C port 6, bus 0 */
+	NPCX_I2C_PORT6_1, /* I2C port 6, bus 1 */
+	NPCX_I2C_PORT7_0, /* I2C port 7, bus 0 */
 	NPCX_I2C_COUNT,
 };
 
 /* Power Management Controller (PMC) Registers */
-#define NPCX_FMUL_WIN_DLY	REG8(NPCX_PMC_BASE_ADDR + 0x010)
-#define NPCX_RAM_PD(offset)	REG8(NPCX_PMC_BASE_ADDR + 0x020 + (offset))
+#define NPCX_FMUL_WIN_DLY REG8(NPCX_PMC_BASE_ADDR + 0x010)
+#define NPCX_RAM_PD(offset) REG8(NPCX_PMC_BASE_ADDR + 0x020 + (offset))
 
 /* PMC register fields */
-#define NPCX_PWDWN_CTL3_SMB4_PD		4
-#define NPCX_PWDWN_CTL7_SMB5_PD		0
-#define NPCX_PWDWN_CTL7_SMB6_PD		1
-#define NPCX_PWDWN_CTL7_SMB7_PD		2
+#define NPCX_PWDWN_CTL3_SMB4_PD 4
+#define NPCX_PWDWN_CTL7_SMB5_PD 0
+#define NPCX_PWDWN_CTL7_SMB6_PD 1
+#define NPCX_PWDWN_CTL7_SMB7_PD 2
 #ifdef NPCX_ITIM64_SUPPORT
-#define NPCX_PWDWN_CTL7_ITIM64_PD	5
+#define NPCX_PWDWN_CTL7_ITIM64_PD 5
 #endif
 #ifdef NPCX_SECOND_UART
-#define NPCX_PWDWN_CTL7_UART2_PD	6
+#define NPCX_PWDWN_CTL7_UART2_PD 6
 #endif
 #ifdef NPCX_WOV_SUPPORT
-#define NPCX_PWDWN_CTL7_WOV_PD		7
+#define NPCX_PWDWN_CTL7_WOV_PD 7
 #endif
 
 /*
@@ -328,7 +326,7 @@ enum {
 	CGC_OFFSET_UART2 = 6,
 #endif
 #ifdef NPCX_WOV_SUPPORT
-	CGC_OFFSET_WOV	= 6,
+	CGC_OFFSET_WOV = 6,
 #endif
 };
 
@@ -343,53 +341,52 @@ enum NPCX_PMC_PWDWN_CTL_T {
 	NPCX_PMC_PWDWN_CNT,
 };
 
-#define CGC_I2C_MASK			(BIT(NPCX_PWDWN_CTL3_SMB0_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB1_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB2_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB3_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB4_PD))
-#define CGC_I2C_MASK2			(BIT(NPCX_PWDWN_CTL7_SMB5_PD) | \
-					BIT(NPCX_PWDWN_CTL7_SMB6_PD) | \
-					BIT(NPCX_PWDWN_CTL7_SMB7_PD))
+#define CGC_I2C_MASK                                                   \
+	(BIT(NPCX_PWDWN_CTL3_SMB0_PD) | BIT(NPCX_PWDWN_CTL3_SMB1_PD) | \
+	 BIT(NPCX_PWDWN_CTL3_SMB2_PD) | BIT(NPCX_PWDWN_CTL3_SMB3_PD) | \
+	 BIT(NPCX_PWDWN_CTL3_SMB4_PD))
+#define CGC_I2C_MASK2                                                  \
+	(BIT(NPCX_PWDWN_CTL7_SMB5_PD) | BIT(NPCX_PWDWN_CTL7_SMB6_PD) | \
+	 BIT(NPCX_PWDWN_CTL7_SMB7_PD))
 #ifdef NPCX_SECOND_UART
-#define CGC_UART2_MASK			BIT(NPCX_PWDWN_CTL7_UART2_PD)
+#define CGC_UART2_MASK BIT(NPCX_PWDWN_CTL7_UART2_PD)
 #endif
 #ifdef NPCX_WOV_SUPPORT
-#define CGC_WOV_MASK			BIT(NPCX_PWDWN_CTL7_WOV_PD)
+#define CGC_WOV_MASK BIT(NPCX_PWDWN_CTL7_WOV_PD)
 #endif
 
 /* BBRAM register fields */
-#if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) || \
+#if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) ||     \
 	defined(CHIP_VARIANT_NPCX7M7FC) || defined(CHIP_VARIANT_NPCX7M7WB) || \
 	defined(CHIP_VARIANT_NPCX7M7WC)
-#define NPCX_BKUP_STS_VSBY_STS		1
-#define NPCX_BKUP_STS_VCC1_STS		0
-#define NPCX_BKUP_STS_ALL_MASK \
+#define NPCX_BKUP_STS_VSBY_STS 1
+#define NPCX_BKUP_STS_VCC1_STS 0
+#define NPCX_BKUP_STS_ALL_MASK                                   \
 	(BIT(NPCX_BKUP_STS_IBBR) | BIT(NPCX_BKUP_STS_VSBY_STS) | \
-	BIT(NPCX_BKUP_STS_VCC1_STS))
-#define NPCX_BBRAM_SIZE			128 /* Size of BBRAM */
+	 BIT(NPCX_BKUP_STS_VCC1_STS))
+#define NPCX_BBRAM_SIZE 128 /* Size of BBRAM */
 #else
 #define NPCX_BKUP_STS_ALL_MASK BIT(NPCX_BKUP_STS_IBBR)
-#define NPCX_BBRAM_SIZE			64 /* Size of BBRAM */
+#define NPCX_BBRAM_SIZE 64 /* Size of BBRAM */
 #endif
 
 /* ITIM16 registers */
-#define NPCX_ITCNT8(n)			REG8(NPCX_ITIM_BASE_ADDR(n) + 0x000)
-#define NPCX_ITCNT16(n)			REG16(NPCX_ITIM_BASE_ADDR(n) + 0x002)
+#define NPCX_ITCNT8(n) REG8(NPCX_ITIM_BASE_ADDR(n) + 0x000)
+#define NPCX_ITCNT16(n) REG16(NPCX_ITIM_BASE_ADDR(n) + 0x002)
 /* ITIM32 registers */
-#define NPCX_ITCNT32			REG32(NPCX_ITIM32_BASE_ADDR + 0x008)
+#define NPCX_ITCNT32 REG32(NPCX_ITIM32_BASE_ADDR + 0x008)
 
 /* Timer counter register used for 1 micro-second system tick */
-#define NPCX_ITCNT_SYSTEM		NPCX_ITCNT32
+#define NPCX_ITCNT_SYSTEM NPCX_ITCNT32
 /* Timer counter register used for others */
-#define NPCX_ITCNT			NPCX_ITCNT16
+#define NPCX_ITCNT NPCX_ITCNT16
 
 /* ITIM module No. used for event */
-#define ITIM_EVENT_NO			ITIM16_1
+#define ITIM_EVENT_NO ITIM16_1
 /* ITIM module No. used for watchdog */
-#define ITIM_WDG_NO			ITIM16_5
+#define ITIM_WDG_NO ITIM16_5
 /* ITIM module No. used for 1 micro-second system tick */
-#define ITIM_SYSTEM_NO			ITIM32
+#define ITIM_SYSTEM_NO ITIM32
 
 /* ITIM enumeration */
 enum ITIM_MODULE_T {
@@ -404,56 +401,56 @@ enum ITIM_MODULE_T {
 };
 
 /* Serial Host Interface (SHI) Registers - only available on SHI Version 2 */
-#define NPCX_SHICFG3			REG8(NPCX_SHI_BASE_ADDR + 0x00C)
-#define NPCX_SHICFG4			REG8(NPCX_SHI_BASE_ADDR + 0x00D)
-#define NPCX_SHICFG5			REG8(NPCX_SHI_BASE_ADDR + 0x00E)
-#define NPCX_EVSTAT2			REG8(NPCX_SHI_BASE_ADDR + 0x00F)
-#define NPCX_EVENABLE2			REG8(NPCX_SHI_BASE_ADDR + 0x010)
-#define NPCX_OBUF(n)			REG8(NPCX_SHI_BASE_ADDR + 0x020 + (n))
-#define NPCX_IBUF(n)			REG8(NPCX_SHI_BASE_ADDR + 0x0A0 + (n))
+#define NPCX_SHICFG3 REG8(NPCX_SHI_BASE_ADDR + 0x00C)
+#define NPCX_SHICFG4 REG8(NPCX_SHI_BASE_ADDR + 0x00D)
+#define NPCX_SHICFG5 REG8(NPCX_SHI_BASE_ADDR + 0x00E)
+#define NPCX_EVSTAT2 REG8(NPCX_SHI_BASE_ADDR + 0x00F)
+#define NPCX_EVENABLE2 REG8(NPCX_SHI_BASE_ADDR + 0x010)
+#define NPCX_OBUF(n) REG8(NPCX_SHI_BASE_ADDR + 0x020 + (n))
+#define NPCX_IBUF(n) REG8(NPCX_SHI_BASE_ADDR + 0x0A0 + (n))
 
 /* SHI register fields */
-#define NPCX_SHICFG3_OBUFLVLDIS		7
-#define NPCX_SHICFG4_IBUFLVLDIS		7
-#define NPCX_SHICFG5_IBUFLVL2		FIELD(0, 6)
-#define NPCX_SHICFG5_IBUFLVL2DIS	7
-#define NPCX_EVSTAT2_IBHF2		0
-#define NPCX_EVSTAT2_CSNRE		1
-#define NPCX_EVSTAT2_CSNFE		2
-#define NPCX_EVENABLE2_IBHF2EN		0
-#define NPCX_EVENABLE2_CSNREEN		1
-#define NPCX_EVENABLE2_CSNFEEN		2
+#define NPCX_SHICFG3_OBUFLVLDIS 7
+#define NPCX_SHICFG4_IBUFLVLDIS 7
+#define NPCX_SHICFG5_IBUFLVL2 FIELD(0, 6)
+#define NPCX_SHICFG5_IBUFLVL2DIS 7
+#define NPCX_EVSTAT2_IBHF2 0
+#define NPCX_EVSTAT2_CSNRE 1
+#define NPCX_EVSTAT2_CSNFE 2
+#define NPCX_EVENABLE2_IBHF2EN 0
+#define NPCX_EVENABLE2_CSNREEN 1
+#define NPCX_EVENABLE2_CSNFEEN 2
 
 /* eSPI register fields */
-#define NPCX_ESPIIE_BMTXDONEIE		19
-#define NPCX_ESPIIE_PBMRXIE		20
-#define NPCX_ESPIIE_PMSGRXIE		21
-#define NPCX_ESPIIE_BMBURSTERRIE	22
-#define NPCX_ESPIIE_BMBURSTDONEIE	23
-
-#define NPCX_ESPIWE_PBMRXWE		20
-#define NPCX_ESPIWE_PMSGRXWE		21
-
-#define NPCX_ESPISTS_VWUPDW		17
-#define NPCX_ESPISTS_BMTXDONE		19
-#define NPCX_ESPISTS_PBMRX		20
-#define NPCX_ESPISTS_PMSGRX		21
-#define NPCX_ESPISTS_BMBURSTERR		22
-#define NPCX_ESPISTS_BMBURSTDONE	23
-#define NPCX_ESPISTS_ESPIRST_LVL	24
-
-#define ESPIIE_BMTXDONE			BIT(NPCX_ESPIIE_BMTXDONEIE)
-#define ESPIIE_PBMRX			BIT(NPCX_ESPIIE_PBMRXIE)
-#define ESPIIE_PMSGRX			BIT(NPCX_ESPIIE_PMSGRXIE)
-#define ESPIIE_BMBURSTERR		BIT(NPCX_ESPIIE_BMBURSTERRIE)
-#define ESPIIE_BMBURSTDONE		BIT(NPCX_ESPIIE_BMBURSTDONEIE)
-
-#define ESPIWE_PBMRX			BIT(NPCX_ESPIWE_PBMRXWE)
-#define ESPIWE_PMSGRX			BIT(NPCX_ESPIWE_PMSGRXWE)
+#define NPCX_ESPIIE_BMTXDONEIE 19
+#define NPCX_ESPIIE_PBMRXIE 20
+#define NPCX_ESPIIE_PMSGRXIE 21
+#define NPCX_ESPIIE_BMBURSTERRIE 22
+#define NPCX_ESPIIE_BMBURSTDONEIE 23
+
+#define NPCX_ESPIWE_PBMRXWE 20
+#define NPCX_ESPIWE_PMSGRXWE 21
+
+#define NPCX_ESPISTS_VWUPDW 17
+#define NPCX_ESPISTS_BMTXDONE 19
+#define NPCX_ESPISTS_PBMRX 20
+#define NPCX_ESPISTS_PMSGRX 21
+#define NPCX_ESPISTS_BMBURSTERR 22
+#define NPCX_ESPISTS_BMBURSTDONE 23
+#define NPCX_ESPISTS_ESPIRST_LVL 24
+
+#define ESPIIE_BMTXDONE BIT(NPCX_ESPIIE_BMTXDONEIE)
+#define ESPIIE_PBMRX BIT(NPCX_ESPIIE_PBMRXIE)
+#define ESPIIE_PMSGRX BIT(NPCX_ESPIIE_PMSGRXIE)
+#define ESPIIE_BMBURSTERR BIT(NPCX_ESPIIE_BMBURSTERRIE)
+#define ESPIIE_BMBURSTDONE BIT(NPCX_ESPIIE_BMBURSTDONEIE)
+
+#define ESPIWE_PBMRX BIT(NPCX_ESPIWE_PBMRXWE)
+#define ESPIWE_PMSGRX BIT(NPCX_ESPIWE_PMSGRXWE)
 
 /* Bit field manipulation for VWEVMS Value */
-#define VWEVMS_WK_EN(e)			(((e)<<20) & 0x00100000)
-#define VWEVMS_INTWK_EN(e)		(VWEVMS_INT_EN(e) | VWEVMS_WK_EN(e))
+#define VWEVMS_WK_EN(e) (((e) << 20) & 0x00100000)
+#define VWEVMS_INTWK_EN(e) (VWEVMS_INT_EN(e) | VWEVMS_WK_EN(e))
 
 /* eSPI max supported frequency */
 enum {
@@ -466,41 +463,41 @@ enum {
 
 /* eSPI max frequency support per FMCLK */
 #if (FMCLK <= 33000000)
-#define NPCX_ESPI_MAXFREQ_MAX		NPCX_ESPI_MAXFREQ_33
+#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_33
 #else
-#define NPCX_ESPI_MAXFREQ_MAX		NPCX_ESPI_MAXFREQ_50
+#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_50
 #endif
 
 /* UART registers */
-#define NPCX_UART_WK_GROUP		MIWU_GROUP_8
-#define NPCX_UART_WK_BIT		7
+#define NPCX_UART_WK_GROUP MIWU_GROUP_8
+#define NPCX_UART_WK_BIT 7
 #ifdef NPCX_SECOND_UART
-#define NPCX_UART2_WK_GROUP		MIWU_GROUP_1
-#define NPCX_UART2_WK_BIT		6
+#define NPCX_UART2_WK_GROUP MIWU_GROUP_1
+#define NPCX_UART2_WK_BIT 6
 #endif
 
 /* MIWU registers */
-#define NPCX_WKEDG_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x00 + \
-					((n) * 2L) + ((n) < 5 ? 0 : 0x1E))
-#define NPCX_WKAEDG_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x01 + \
-					((n) * 2L) + ((n) < 5 ? 0 : 0x1E))
-#define NPCX_WKPND_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x0A + \
-					((n) * 4L) + ((n) < 5 ? 0 : 0x10))
-#define NPCX_WKPCL_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x0C + \
-					((n) * 4L) + ((n) < 5 ? 0 : 0x10))
-#define NPCX_WKEN_ADDR(port, n)		(NPCX_MIWU_BASE_ADDR(port) + 0x1E + \
-					((n) * 2L) + ((n) < 5 ? 0 : 0x12))
-#define NPCX_WKINEN_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x1F + \
-					((n) * 2L) + ((n) < 5 ? 0 : 0x12))
-#define NPCX_WKMOD_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x70 + (n))
-
-#define NPCX_WKEDG(port, n)		REG8(NPCX_WKEDG_ADDR(port, n))
-#define NPCX_WKAEDG(port, n)		REG8(NPCX_WKAEDG_ADDR(port, n))
-#define NPCX_WKPND(port, n)		REG8(NPCX_WKPND_ADDR(port, n))
-#define NPCX_WKPCL(port, n)		REG8(NPCX_WKPCL_ADDR(port, n))
-#define NPCX_WKEN(port, n)		REG8(NPCX_WKEN_ADDR(port, n))
-#define NPCX_WKINEN(port, n)		REG8(NPCX_WKINEN_ADDR(port, n))
-#define NPCX_WKMOD(port, n)		REG8(NPCX_WKMOD_ADDR(port, n))
+#define NPCX_WKEDG_ADDR(port, n) \
+	(NPCX_MIWU_BASE_ADDR(port) + 0x00 + ((n)*2L) + ((n) < 5 ? 0 : 0x1E))
+#define NPCX_WKAEDG_ADDR(port, n) \
+	(NPCX_MIWU_BASE_ADDR(port) + 0x01 + ((n)*2L) + ((n) < 5 ? 0 : 0x1E))
+#define NPCX_WKPND_ADDR(port, n) \
+	(NPCX_MIWU_BASE_ADDR(port) + 0x0A + ((n)*4L) + ((n) < 5 ? 0 : 0x10))
+#define NPCX_WKPCL_ADDR(port, n) \
+	(NPCX_MIWU_BASE_ADDR(port) + 0x0C + ((n)*4L) + ((n) < 5 ? 0 : 0x10))
+#define NPCX_WKEN_ADDR(port, n) \
+	(NPCX_MIWU_BASE_ADDR(port) + 0x1E + ((n)*2L) + ((n) < 5 ? 0 : 0x12))
+#define NPCX_WKINEN_ADDR(port, n) \
+	(NPCX_MIWU_BASE_ADDR(port) + 0x1F + ((n)*2L) + ((n) < 5 ? 0 : 0x12))
+#define NPCX_WKMOD_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x70 + (n))
+
+#define NPCX_WKEDG(port, n) REG8(NPCX_WKEDG_ADDR(port, n))
+#define NPCX_WKAEDG(port, n) REG8(NPCX_WKAEDG_ADDR(port, n))
+#define NPCX_WKPND(port, n) REG8(NPCX_WKPND_ADDR(port, n))
+#define NPCX_WKPCL(port, n) REG8(NPCX_WKPCL_ADDR(port, n))
+#define NPCX_WKEN(port, n) REG8(NPCX_WKEN_ADDR(port, n))
+#define NPCX_WKINEN(port, n) REG8(NPCX_WKINEN_ADDR(port, n))
+#define NPCX_WKMOD(port, n) REG8(NPCX_WKMOD_ADDR(port, n))
 
 /* UART registers and functions */
 #if NPCX_UART_MODULE2
@@ -508,64 +505,64 @@ enum {
  * To be used as 2nd parameter to NPCX_WK*() macro, table (1st parameter) is
  * always 1 == MIWU_TABLE_1.
  */
-#define NPCX_UART_MIWU_IRQ		NPCX_IRQ_WKINTG_1
-#define NPCX_UART_DEVALT		NPCX_DEVALT(0x0C)
-#define NPCX_UART_DEVALT_SL		NPCX_DEVALTC_UART_SL2
-#define NPCX_UART_ALT_DEVALT		NPCX_DEVALT(0x0A)
-#define NPCX_UART_ALT_DEVALT_SL		NPCX_DEVALTA_UART_SL1
+#define NPCX_UART_MIWU_IRQ NPCX_IRQ_WKINTG_1
+#define NPCX_UART_DEVALT NPCX_DEVALT(0x0C)
+#define NPCX_UART_DEVALT_SL NPCX_DEVALTC_UART_SL2
+#define NPCX_UART_ALT_DEVALT NPCX_DEVALT(0x0A)
+#define NPCX_UART_ALT_DEVALT_SL NPCX_DEVALTA_UART_SL1
 #else /* !NPCX_UART_MODULE2 */
-#define NPCX_UART_MIWU_IRQ		NPCX_IRQ_WKINTB_1
-#define NPCX_UART_DEVALT		NPCX_DEVALT(0x0A)
-#define NPCX_UART_DEVALT_SL		NPCX_DEVALTA_UART_SL1
-#define NPCX_UART_ALT_DEVALT		NPCX_DEVALT(0x0C)
-#define NPCX_UART_ALT_DEVALT_SL		NPCX_DEVALTC_UART_SL2
+#define NPCX_UART_MIWU_IRQ NPCX_IRQ_WKINTB_1
+#define NPCX_UART_DEVALT NPCX_DEVALT(0x0A)
+#define NPCX_UART_DEVALT_SL NPCX_DEVALTA_UART_SL1
+#define NPCX_UART_ALT_DEVALT NPCX_DEVALT(0x0C)
+#define NPCX_UART_ALT_DEVALT_SL NPCX_DEVALTC_UART_SL2
 #endif /* NPCX_UART_MODULE2 */
 
 /* ADC Registers */
-#define NPCX_ADCSTS		REG16(NPCX_ADC_BASE_ADDR + 0x000)
-#define NPCX_ADCCNF		REG16(NPCX_ADC_BASE_ADDR + 0x002)
-#define NPCX_ATCTL		REG16(NPCX_ADC_BASE_ADDR + 0x004)
-#define NPCX_ASCADD		REG16(NPCX_ADC_BASE_ADDR + 0x006)
-#define NPCX_ADCCS		REG16(NPCX_ADC_BASE_ADDR + 0x008)
+#define NPCX_ADCSTS REG16(NPCX_ADC_BASE_ADDR + 0x000)
+#define NPCX_ADCCNF REG16(NPCX_ADC_BASE_ADDR + 0x002)
+#define NPCX_ATCTL REG16(NPCX_ADC_BASE_ADDR + 0x004)
+#define NPCX_ASCADD REG16(NPCX_ADC_BASE_ADDR + 0x006)
+#define NPCX_ADCCS REG16(NPCX_ADC_BASE_ADDR + 0x008)
 /* NOTE: These are 1-based for the threshold detectors. */
-#define NPCX_THRCTL(n)		REG16(NPCX_ADC_BASE_ADDR + 0x012 + (2L*(n)))
-#define NPCX_THRCTS		REG16(NPCX_ADC_BASE_ADDR + 0x01A)
-#define NPCX_THR_DCTL(n)	REG16(NPCX_ADC_BASE_ADDR + 0x038 + (2L*(n)))
+#define NPCX_THRCTL(n) REG16(NPCX_ADC_BASE_ADDR + 0x012 + (2L * (n)))
+#define NPCX_THRCTS REG16(NPCX_ADC_BASE_ADDR + 0x01A)
+#define NPCX_THR_DCTL(n) REG16(NPCX_ADC_BASE_ADDR + 0x038 + (2L * (n)))
 /* NOTE: This is 0-based for the ADC channels. */
-#define NPCX_CHNDAT(n)		REG16(NPCX_ADC_BASE_ADDR + 0x040 + (2L*(n)))
-#define NPCX_ADCCNF2		REG16(NPCX_ADC_BASE_ADDR + 0x020)
-#define NPCX_GENDLY		REG16(NPCX_ADC_BASE_ADDR + 0x022)
-#define NPCX_MEAST		REG16(NPCX_ADC_BASE_ADDR + 0x026)
+#define NPCX_CHNDAT(n) REG16(NPCX_ADC_BASE_ADDR + 0x040 + (2L * (n)))
+#define NPCX_ADCCNF2 REG16(NPCX_ADC_BASE_ADDR + 0x020)
+#define NPCX_GENDLY REG16(NPCX_ADC_BASE_ADDR + 0x022)
+#define NPCX_MEAST REG16(NPCX_ADC_BASE_ADDR + 0x026)
 
 /* ADC register fields */
-#define NPCX_ATCTL_SCLKDIV_FIELD	FIELD(0, 6)
-#define NPCX_ATCTL_DLY_FIELD		FIELD(8, 3)
-#define NPCX_ASCADD_SADDR_FIELD		FIELD(0, 5)
-#define NPCX_ADCSTS_EOCEV		0
-#define NPCX_ADCCNF_ADCMD_FIELD		FIELD(1, 2)
-#define NPCX_ADCCNF_ADCRPTC		3
-#define NPCX_ADCCNF_INTECEN		6
-#define NPCX_ADCCNF_START		4
-#define NPCX_ADCCNF_ADCEN		0
-#define NPCX_ADCCNF_STOP		11
-#define NPCX_CHNDAT_CHDAT_FIELD		FIELD(0, 10)
-#define NPCX_CHNDAT_NEW			15
-#define NPCX_THRCTL_THEN		15
-#define NPCX_THRCTL_L_H			14
-#define NPCX_THRCTL_CHNSEL		FIELD(10, 4)
-#define NPCX_THRCTL_THRVAL		FIELD(0, 10)
-#define NPCX_THRCTS_ADC_WKEN		15
-#define NPCX_THRCTS_THR3_IEN		10
-#define NPCX_THRCTS_THR2_IEN		9
-#define NPCX_THRCTS_THR1_IEN		8
-#define NPCX_THRCTS_ADC_EVENT		7
-#define NPCX_THRCTS_THR3_STS		2
-#define NPCX_THRCTS_THR2_STS		1
-#define NPCX_THRCTS_THR1_STS		0
-#define NPCX_THR_DCTL_THRD_EN		15
-#define NPCX_THR_DCTL_THR_DVAL		FIELD(0, 10)
-
-#define NPCX_ADC_THRESH1		1
-#define NPCX_ADC_THRESH2		2
-#define NPCX_ADC_THRESH3		3
-#define NPCX_ADC_THRESH_CNT		3
+#define NPCX_ATCTL_SCLKDIV_FIELD FIELD(0, 6)
+#define NPCX_ATCTL_DLY_FIELD FIELD(8, 3)
+#define NPCX_ASCADD_SADDR_FIELD FIELD(0, 5)
+#define NPCX_ADCSTS_EOCEV 0
+#define NPCX_ADCCNF_ADCMD_FIELD FIELD(1, 2)
+#define NPCX_ADCCNF_ADCRPTC 3
+#define NPCX_ADCCNF_INTECEN 6
+#define NPCX_ADCCNF_START 4
+#define NPCX_ADCCNF_ADCEN 0
+#define NPCX_ADCCNF_STOP 11
+#define NPCX_CHNDAT_CHDAT_FIELD FIELD(0, 10)
+#define NPCX_CHNDAT_NEW 15
+#define NPCX_THRCTL_THEN 15
+#define NPCX_THRCTL_L_H 14
+#define NPCX_THRCTL_CHNSEL FIELD(10, 4)
+#define NPCX_THRCTL_THRVAL FIELD(0, 10)
+#define NPCX_THRCTS_ADC_WKEN 15
+#define NPCX_THRCTS_THR3_IEN 10
+#define NPCX_THRCTS_THR2_IEN 9
+#define NPCX_THRCTS_THR1_IEN 8
+#define NPCX_THRCTS_ADC_EVENT 7
+#define NPCX_THRCTS_THR3_STS 2
+#define NPCX_THRCTS_THR2_STS 1
+#define NPCX_THRCTS_THR1_STS 0
+#define NPCX_THR_DCTL_THRD_EN 15
+#define NPCX_THR_DCTL_THR_DVAL FIELD(0, 10)
+
+#define NPCX_ADC_THRESH1 1
+#define NPCX_ADC_THRESH2 2
+#define NPCX_ADC_THRESH3 3
+#define NPCX_ADC_THRESH_CNT 3
diff --git a/chip/npcx/registers-npcx9.h b/chip/npcx/registers-npcx9.h
index 2f2a22405a..11cac561d7 100644
--- a/chip/npcx/registers-npcx9.h
+++ b/chip/npcx/registers-npcx9.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,157 +19,155 @@
 #endif
 
 /* NPCX-IRQ numbers */
-#define NPCX_IRQ0_NOUSED		NPCX_IRQ_0
-#define NPCX_IRQ1_NOUSED		NPCX_IRQ_1
-#define NPCX_IRQ_KBSCAN			NPCX_IRQ_2
-#define NPCX_IRQ_PM_CHAN_OBE		NPCX_IRQ_3
-#define NPCX_IRQ_PECI			NPCX_IRQ_4
-#define NPCX_IRQ_MTC_WKINTD_0		NPCX_IRQ_5
-#define NPCX_IRQ_MTC			NPCX_IRQ_MTC_WKINTD_0
-#define NPCX_IRQ_PORT80			NPCX_IRQ_6
-#define NPCX_IRQ_CR_SIN2_WKINTA_0	NPCX_IRQ_7
-#define NPCX_IRQ_SMB8			NPCX_IRQ_8
-#define NPCX_IRQ_MFT_1			NPCX_IRQ_9
-#define NPCX_IRQ_ADC			NPCX_IRQ_10
-#define NPCX_IRQ_WKINTE_0		NPCX_IRQ_11
-#define NPCX_IRQ_GDMA			NPCX_IRQ_12
-#define NPCX_IRQ_SMB1			NPCX_IRQ_13
-#define NPCX_IRQ_SMB2			NPCX_IRQ_14
-#define NPCX_IRQ_WKINTC_0		NPCX_IRQ_15
-#define NPCX_IRQ_SMB7			NPCX_IRQ_16
-#define NPCX_IRQ_ITIM32_3		NPCX_IRQ_17
-#define NPCX_IRQ_SHI			NPCX_IRQ_18
-#define NPCX_IRQ_ESPI			NPCX_IRQ_18
-#define NPCX_IRQ_SMB5			NPCX_IRQ_19
-#define NPCX_IRQ_SMB6			NPCX_IRQ_20
-#define NPCX_IRQ_PS2			NPCX_IRQ_21
-#define NPCX_IRQ22_NOUSED		NPCX_IRQ_22
-#define NPCX_IRQ_MFT_2			NPCX_IRQ_23
-#define NPCX_IRQ_SHM			NPCX_IRQ_24
-#define NPCX_IRQ_KBC_IBF		NPCX_IRQ_25
-#define NPCX_IRQ_PM_CHAN_IBF		NPCX_IRQ_26
-#define NPCX_IRQ_ITIM32_2		NPCX_IRQ_27
-#define NPCX_IRQ_ITIM32_1		NPCX_IRQ_28
-#define NPCX_I3C_MDMA5			NPCX_IRQ_29
-#define NPCX_IRQ30_NOUSED		NPCX_IRQ_30
-#define NPCX_IRQ_TWD_WKINTB_0		NPCX_IRQ_31
-#define NPCX_IRQ_UART2			NPCX_IRQ_32
-#define NPCX_IRQ_UART			NPCX_IRQ_33
-#define NPCX_IRQ34_NOUSED		NPCX_IRQ_34
-#define NPCX_IRQ_WKINTF_0		NPCX_IRQ_35
-#define NPCX_IRQ_SMB3			NPCX_IRQ_36
-#define NPCX_IRQ_SMB4			NPCX_IRQ_37
-#define NPCX_IRQ_UART3			NPCX_IRQ_38
-#define NPCX_IRQ_UART4			NPCX_IRQ_39
-#define NPCX_IRQ40_NOUSED		NPCX_IRQ_40
-#define NPCX_IRQ_MFT_3			NPCX_IRQ_41
-#define NPCX_IRQ_WKINTG_0		NPCX_IRQ_42
-#define NPCX_IRQ_ITIM32_4		NPCX_IRQ_43
-#define NPCX_IRQ_ITIM32_5		NPCX_IRQ_44
-#define NPCX_IRQ_ITIM32_6		NPCX_IRQ_45
-#define NPCX_IRQ_WKINTH_0		NPCX_IRQ_46
-#define NPCX_IRQ_WKINTA_1		NPCX_IRQ_47
-#define NPCX_IRQ_WKINTB_1		NPCX_IRQ_48
-#define NPCX_IRQ_KSI_WKINTC_1		NPCX_IRQ_49
-#define NPCX_IRQ_WKINTD_1		NPCX_IRQ_50
-#define NPCX_IRQ_WKINTE_1		NPCX_IRQ_51
-#define NPCX_IRQ_WKINTF_1		NPCX_IRQ_52
-#define NPCX_IRQ_WKINTG_1		NPCX_IRQ_53
-#define NPCX_IRQ_WKINTH_1		NPCX_IRQ_54
-#define NPCX_WKINTG_2			NPCX_IRQ_55
-#define NPCX_IRQ_KBC_OBE		NPCX_IRQ_56
-#define NPCX_IRQ_SPI			NPCX_IRQ_57
-#define NPCX_IRQ_ITIM64			NPCX_IRQ_58
-#define NPCX_IRQ_LCT_WKINTF_2		NPCX_IRQ_59
-#define NPCX_IRQ_WKINTA_2		NPCX_IRQ_60
-#define NPCX_IRQ_WKINTB_2		NPCX_IRQ_61
-#define NPCX_IRQ_WKINTC_2		NPCX_IRQ_62
-#define NPCX_IRQ_WKINTD_2		NPCX_IRQ_63
+#define NPCX_IRQ0_NOUSED NPCX_IRQ_0
+#define NPCX_IRQ1_NOUSED NPCX_IRQ_1
+#define NPCX_IRQ_KBSCAN NPCX_IRQ_2
+#define NPCX_IRQ_PM_CHAN_OBE NPCX_IRQ_3
+#define NPCX_IRQ_PECI NPCX_IRQ_4
+#define NPCX_IRQ_MTC_WKINTD_0 NPCX_IRQ_5
+#define NPCX_IRQ_MTC NPCX_IRQ_MTC_WKINTD_0
+#define NPCX_IRQ_PORT80 NPCX_IRQ_6
+#define NPCX_IRQ_CR_SIN2_WKINTA_0 NPCX_IRQ_7
+#define NPCX_IRQ_SMB8 NPCX_IRQ_8
+#define NPCX_IRQ_MFT_1 NPCX_IRQ_9
+#define NPCX_IRQ_ADC NPCX_IRQ_10
+#define NPCX_IRQ_WKINTE_0 NPCX_IRQ_11
+#define NPCX_IRQ_GDMA NPCX_IRQ_12
+#define NPCX_IRQ_SMB1 NPCX_IRQ_13
+#define NPCX_IRQ_SMB2 NPCX_IRQ_14
+#define NPCX_IRQ_WKINTC_0 NPCX_IRQ_15
+#define NPCX_IRQ_SMB7 NPCX_IRQ_16
+#define NPCX_IRQ_ITIM32_3 NPCX_IRQ_17
+#define NPCX_IRQ_SHI NPCX_IRQ_18
+#define NPCX_IRQ_ESPI NPCX_IRQ_18
+#define NPCX_IRQ_SMB5 NPCX_IRQ_19
+#define NPCX_IRQ_SMB6 NPCX_IRQ_20
+#define NPCX_IRQ_PS2 NPCX_IRQ_21
+#define NPCX_IRQ22_NOUSED NPCX_IRQ_22
+#define NPCX_IRQ_MFT_2 NPCX_IRQ_23
+#define NPCX_IRQ_SHM NPCX_IRQ_24
+#define NPCX_IRQ_KBC_IBF NPCX_IRQ_25
+#define NPCX_IRQ_PM_CHAN_IBF NPCX_IRQ_26
+#define NPCX_IRQ_ITIM32_2 NPCX_IRQ_27
+#define NPCX_IRQ_ITIM32_1 NPCX_IRQ_28
+#define NPCX_I3C_MDMA5 NPCX_IRQ_29
+#define NPCX_IRQ30_NOUSED NPCX_IRQ_30
+#define NPCX_IRQ_TWD_WKINTB_0 NPCX_IRQ_31
+#define NPCX_IRQ_UART2 NPCX_IRQ_32
+#define NPCX_IRQ_UART NPCX_IRQ_33
+#define NPCX_IRQ34_NOUSED NPCX_IRQ_34
+#define NPCX_IRQ_WKINTF_0 NPCX_IRQ_35
+#define NPCX_IRQ_SMB3 NPCX_IRQ_36
+#define NPCX_IRQ_SMB4 NPCX_IRQ_37
+#define NPCX_IRQ_UART3 NPCX_IRQ_38
+#define NPCX_IRQ_UART4 NPCX_IRQ_39
+#define NPCX_IRQ40_NOUSED NPCX_IRQ_40
+#define NPCX_IRQ_MFT_3 NPCX_IRQ_41
+#define NPCX_IRQ_WKINTG_0 NPCX_IRQ_42
+#define NPCX_IRQ_ITIM32_4 NPCX_IRQ_43
+#define NPCX_IRQ_ITIM32_5 NPCX_IRQ_44
+#define NPCX_IRQ_ITIM32_6 NPCX_IRQ_45
+#define NPCX_IRQ_WKINTH_0 NPCX_IRQ_46
+#define NPCX_IRQ_WKINTA_1 NPCX_IRQ_47
+#define NPCX_IRQ_WKINTB_1 NPCX_IRQ_48
+#define NPCX_IRQ_KSI_WKINTC_1 NPCX_IRQ_49
+#define NPCX_IRQ_WKINTD_1 NPCX_IRQ_50
+#define NPCX_IRQ_WKINTE_1 NPCX_IRQ_51
+#define NPCX_IRQ_WKINTF_1 NPCX_IRQ_52
+#define NPCX_IRQ_WKINTG_1 NPCX_IRQ_53
+#define NPCX_IRQ_WKINTH_1 NPCX_IRQ_54
+#define NPCX_WKINTG_2 NPCX_IRQ_55
+#define NPCX_IRQ_KBC_OBE NPCX_IRQ_56
+#define NPCX_IRQ_SPI NPCX_IRQ_57
+#define NPCX_IRQ_ITIM64 NPCX_IRQ_58
+#define NPCX_IRQ_LCT_WKINTF_2 NPCX_IRQ_59
+#define NPCX_IRQ_WKINTA_2 NPCX_IRQ_60
+#define NPCX_IRQ_WKINTB_2 NPCX_IRQ_61
+#define NPCX_IRQ_WKINTC_2 NPCX_IRQ_62
+#define NPCX_IRQ_WKINTD_2 NPCX_IRQ_63
 /* MIWU definition */
-#define LCT_WUI_GROUP			MIWU_GROUP_6
-#define LCT_WUI_MASK			MASK_PIN7
+#define LCT_WUI_GROUP MIWU_GROUP_6
+#define LCT_WUI_MASK MASK_PIN7
 
 /* Modules Map */
 
 /* Miscellaneous Device Control (MDC) registers */
-#define NPCX_FWCTRL			REG8(NPCX_MDC_BASE_ADDR + 0x009)
+#define NPCX_FWCTRL REG8(NPCX_MDC_BASE_ADDR + 0x009)
 
 /* MDC register fields */
-#define NPCX_FWCTRL_RO_REGION		6
-#define NPCX_FWCTRL_FW_SLOT		7
-
-#define NPCX_CR_UART_BASE_ADDR(mdl)	(0x400E0000 + ((mdl) * 0x2000L))
-#define NPCX_LCT_BASE_ADDR		0x400D7000
-#define NPCX_SMB_BASE_ADDR(mdl)		(((mdl) < 2) ? \
-				(0x40009000 + ((mdl) * 0x2000L)) : \
-				((mdl) < 4) ? \
-				(0x400C0000 + (((mdl) - 2) * 0x2000L)) : \
-				((mdl) == 4) ? \
-				(0x40008000) : \
-				(0x40017000 + (((mdl) - 5) * 0x1000L)))
-
-#define NPCX_HFCBCD1			REG8(NPCX_HFCG_BASE_ADDR + 0x012)
-#define NPCX_HFCBCD2			REG8(NPCX_HFCG_BASE_ADDR + 0x014)
+#define NPCX_FWCTRL_RO_REGION 6
+#define NPCX_FWCTRL_FW_SLOT 7
+
+#define NPCX_CR_UART_BASE_ADDR(mdl) (0x400E0000 + ((mdl)*0x2000L))
+#define NPCX_LCT_BASE_ADDR 0x400D7000
+#define NPCX_SMB_BASE_ADDR(mdl)                                \
+	(((mdl) < 2)  ? (0x40009000 + ((mdl)*0x2000L)) :       \
+	 ((mdl) < 4)  ? (0x400C0000 + (((mdl)-2) * 0x2000L)) : \
+	 ((mdl) == 4) ? (0x40008000) :                         \
+			(0x40017000 + (((mdl)-5) * 0x1000L)))
+
+#define NPCX_HFCBCD1 REG8(NPCX_HFCG_BASE_ADDR + 0x012)
+#define NPCX_HFCBCD2 REG8(NPCX_HFCG_BASE_ADDR + 0x014)
 
 enum {
-	NPCX_UART_PORT0 = 0,	/* UART port 0 */
-	NPCX_UART_PORT1 = 1,	/* UART port 1 */
-	NPCX_UART_PORT2 = 2,	/* UART port 2 */
-	NPCX_UART_PORT3 = 3,	/* UART port 3 */
+	NPCX_UART_PORT0 = 0, /* UART port 0 */
+	NPCX_UART_PORT1 = 1, /* UART port 1 */
+	NPCX_UART_PORT2 = 2, /* UART port 2 */
+	NPCX_UART_PORT3 = 3, /* UART port 3 */
 	NPCX_UART_COUNT
 };
 
- /* UART registers only used for FIFO mode */
-#define NPCX_UFTSTS(n)			REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x020)
-#define NPCX_UFRSTS(n)			REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x022)
-#define NPCX_UFTCTL(n)			REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x024)
-#define NPCX_UFRCTL(n)			REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x026)
+/* UART registers only used for FIFO mode */
+#define NPCX_UFTSTS(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x020)
+#define NPCX_UFRSTS(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x022)
+#define NPCX_UFTCTL(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x024)
+#define NPCX_UFRCTL(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x026)
 
 /* UART FIFO register fields */
-#define NPCX_UMDSL_FIFO_MD		0
+#define NPCX_UMDSL_FIFO_MD 0
 
-#define NPCX_UFTSTS_TEMPTY_LVL		FIELD(0, 5)
-#define NPCX_UFTSTS_TEMPTY_LVL_STS	5
-#define NPCX_UFTSTS_TFIFO_EMPTY_STS	6
-#define NPCX_UFTSTS_NXMIP		7
+#define NPCX_UFTSTS_TEMPTY_LVL FIELD(0, 5)
+#define NPCX_UFTSTS_TEMPTY_LVL_STS 5
+#define NPCX_UFTSTS_TFIFO_EMPTY_STS 6
+#define NPCX_UFTSTS_NXMIP 7
 
-#define NPCX_UFRSTS_RFULL_LVL_STS	5
-#define NPCX_UFRSTS_RFIFO_NEMPTY_STS	6
-#define NPCX_UFRSTS_ERR			7
+#define NPCX_UFRSTS_RFULL_LVL_STS 5
+#define NPCX_UFRSTS_RFIFO_NEMPTY_STS 6
+#define NPCX_UFRSTS_ERR 7
 
-#define NPCX_UFTCTL_TEMPTY_LVL_SEL	FIELD(0, 5)
-#define NPCX_UFTCTL_TEMPTY_LVL_EN	5
-#define NPCX_UFTCTL_TEMPTY_EN		6
-#define NPCX_UFTCTL_NXMIPEN		7
+#define NPCX_UFTCTL_TEMPTY_LVL_SEL FIELD(0, 5)
+#define NPCX_UFTCTL_TEMPTY_LVL_EN 5
+#define NPCX_UFTCTL_TEMPTY_EN 6
+#define NPCX_UFTCTL_NXMIPEN 7
 
-#define NPCX_UFRCTL_RFULL_LVL_SEL	FIELD(0, 5)
-#define NPCX_UFRCTL_RFULL_LVL_EN	5
-#define NPCX_UFRCTL_RNEMPTY_EN		6
-#define NPCX_UFRCTL_ERR_EN		7
+#define NPCX_UFRCTL_RFULL_LVL_SEL FIELD(0, 5)
+#define NPCX_UFRCTL_RFULL_LVL_EN 5
+#define NPCX_UFRCTL_RNEMPTY_EN 6
+#define NPCX_UFRCTL_ERR_EN 7
 
 /* KBSCAN register fields */
-#define NPCX_KBHDRV_FIELD		FIELD(6, 2)
+#define NPCX_KBHDRV_FIELD FIELD(6, 2)
 
 /* GLUE registers */
-#define NPCX_GLUE_PSL_CTS		REG8(NPCX_GLUE_REGS_BASE + 0x027)
-#define NPCX_GLUE_PSL_MCTL1		REG8(NPCX_GLUE_REGS_BASE + 0x034)
-#define NPCX_GLUE_PSL_MCTL2		REG8(NPCX_GLUE_REGS_BASE + 0x038)
+#define NPCX_GLUE_PSL_CTS REG8(NPCX_GLUE_REGS_BASE + 0x027)
+#define NPCX_GLUE_PSL_MCTL1 REG8(NPCX_GLUE_REGS_BASE + 0x034)
+#define NPCX_GLUE_PSL_MCTL2 REG8(NPCX_GLUE_REGS_BASE + 0x038)
 
 /* PSL register fields */
-#define NPCX_GLUE_PSL_MCTL1_VCC1_RST_PSL	7
-#define NPCX_GLUE_PSL_MCTL1_PSL_GPO_CTL		6
-#define NPCX_GLUE_PSL_MCTL1_LCT_EV		4
-#define NPCX_GLUE_PSL_MCTL1_VCC1_RST_EV		3
-#define NPCX_GLUE_PSL_MCTL1_PLS_EN		1
-#define NPCX_GLUE_PSL_MCTL1_OD_EN		0
-
-#define NPCX_GLUE_PSL_MCTL2_VCC1_RST_PSL_LK	7
-#define NPCX_GLUE_PSL_MCTL2_PSL_GP_EN		6
-#define NPCX_GLUE_PSL_MCTL2_AC_IN_BLOCK_EN	3
-#define NPCX_GLUE_PSL_MCTL2_AC_IN_SEL		FIELD(0, 1)
+#define NPCX_GLUE_PSL_MCTL1_VCC1_RST_PSL 7
+#define NPCX_GLUE_PSL_MCTL1_PSL_GPO_CTL 6
+#define NPCX_GLUE_PSL_MCTL1_LCT_EV 4
+#define NPCX_GLUE_PSL_MCTL1_VCC1_RST_EV 3
+#define NPCX_GLUE_PSL_MCTL1_PLS_EN 1
+#define NPCX_GLUE_PSL_MCTL1_OD_EN 0
+
+#define NPCX_GLUE_PSL_MCTL2_VCC1_RST_PSL_LK 7
+#define NPCX_GLUE_PSL_MCTL2_PSL_GP_EN 6
+#define NPCX_GLUE_PSL_MCTL2_AC_IN_BLOCK_EN 3
+#define NPCX_GLUE_PSL_MCTL2_AC_IN_SEL FIELD(0, 1)
 
 /* GPIO registers */
-#define NPCX_PLOCK_CTL(n)		REG8(NPCX_GPIO_BASE_ADDR(n) + 0x007)
+#define NPCX_PLOCK_CTL(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x007)
 
 /* System Configuration (SCFG) Registers */
 
@@ -197,105 +195,105 @@ enum {
 	ALT_GROUP_COUNT
 };
 
-#define NPCX_DEVALT(n)			REG8(NPCX_SCFG_BASE_ADDR + 0x010 + (n))
+#define NPCX_DEVALT(n) REG8(NPCX_SCFG_BASE_ADDR + 0x010 + (n))
 
-#define NPCX_LV_GPIO_CTL_ADDR(n)	(((n) < 5) ? \
-					(NPCX_SCFG_BASE_ADDR + 0x02A + (n)) :\
-					(NPCX_SCFG_BASE_ADDR + 0x026))
-#define NPCX_LV_GPIO_CTL(n)		REG8(NPCX_LV_GPIO_CTL_ADDR(n))
+#define NPCX_LV_GPIO_CTL_ADDR(n)                           \
+	(((n) < 5) ? (NPCX_SCFG_BASE_ADDR + 0x02A + (n)) : \
+		     (NPCX_SCFG_BASE_ADDR + 0x026))
+#define NPCX_LV_GPIO_CTL(n) REG8(NPCX_LV_GPIO_CTL_ADDR(n))
 /* Device Alternate Function Lock */
-#define NPCX_DEVALT_LK(n)		REG8(NPCX_SCFG_BASE_ADDR + 0x210 + (n))
+#define NPCX_DEVALT_LK(n) REG8(NPCX_SCFG_BASE_ADDR + 0x210 + (n))
 
 /* pin-mux for I2C */
-#define NPCX_DEVALT2_I2C0_0_SL		0
-#define NPCX_DEVALT2_I2C7_0_SL		1
-#define NPCX_DEVALT2_I2C1_0_SL		2
-#define NPCX_DEVALT2_I2C6_0_SL		3
-#define NPCX_DEVALT2_I2C2_0_SL		4
-#define NPCX_DEVALT2_I2C5_0_SL		5
-#define NPCX_DEVALT2_I2C3_0_SL		6
-#define NPCX_DEVALT6_I2C6_1_SL		5
-#define NPCX_DEVALT6_I2C5_1_SL		6
-#define NPCX_DEVALT6_I2C4_1_SL		7
+#define NPCX_DEVALT2_I2C0_0_SL 0
+#define NPCX_DEVALT2_I2C7_0_SL 1
+#define NPCX_DEVALT2_I2C1_0_SL 2
+#define NPCX_DEVALT2_I2C6_0_SL 3
+#define NPCX_DEVALT2_I2C2_0_SL 4
+#define NPCX_DEVALT2_I2C5_0_SL 5
+#define NPCX_DEVALT2_I2C3_0_SL 6
+#define NPCX_DEVALT6_I2C6_1_SL 5
+#define NPCX_DEVALT6_I2C5_1_SL 6
+#define NPCX_DEVALT6_I2C4_1_SL 7
 
 /* pin-mux for ADC */
-#define NPCX_DEVALTF_ADC5_SL		0
-#define NPCX_DEVALTF_ADC6_SL		1
-#define NPCX_DEVALTF_ADC7_SL		2
-#define NPCX_DEVALTF_ADC8_SL		3
-#define NPCX_DEVALTF_ADC9_SL		4
-#define NPCX_DEVALTF_ADC10_SL		5
-#define NPCX_DEVALTF_ADC11_SL		6
+#define NPCX_DEVALTF_ADC5_SL 0
+#define NPCX_DEVALTF_ADC6_SL 1
+#define NPCX_DEVALTF_ADC7_SL 2
+#define NPCX_DEVALTF_ADC8_SL 3
+#define NPCX_DEVALTF_ADC9_SL 4
+#define NPCX_DEVALTF_ADC10_SL 5
+#define NPCX_DEVALTF_ADC11_SL 6
 
 /* pin-mux for PSL */
-#define NPCX_DEVALTD_PSL_IN1_AHI	0
-#define NPCX_DEVALTD_NPSL_IN1_SL	1
-#define NPCX_DEVALTD_PSL_IN2_AHI	2
-#define NPCX_DEVALTD_NPSL_IN2_SL	3
-#define NPCX_DEVALTD_PSL_IN3_AHI	4
-#define NPCX_DEVALTD_PSL_IN3_SL		5
-#define NPCX_DEVALTD_PSL_IN4_AHI	6
-#define NPCX_DEVALTD_PSL_IN4_SL		7
+#define NPCX_DEVALTD_PSL_IN1_AHI 0
+#define NPCX_DEVALTD_NPSL_IN1_SL 1
+#define NPCX_DEVALTD_PSL_IN2_AHI 2
+#define NPCX_DEVALTD_NPSL_IN2_SL 3
+#define NPCX_DEVALTD_PSL_IN3_AHI 4
+#define NPCX_DEVALTD_PSL_IN3_SL 5
+#define NPCX_DEVALTD_PSL_IN4_AHI 6
+#define NPCX_DEVALTD_PSL_IN4_SL 7
 
 /* pin-mux for Misc. */
 
 /* pin-mux for UART */
-#define NPCX_DEVALTJ_CR_SIN1_SL1	0
-#define NPCX_DEVALTJ_CR_SOUT1_SL1	1
-#define NPCX_DEVALTJ_CR_SIN1_SL2	2
-#define NPCX_DEVALTJ_CR_SOUT1_SL2	3
-#define NPCX_DEVALTJ_CR_SIN2_SL		4
-#define NPCX_DEVALTJ_CR_SOUT2_SL	5
-#define NPCX_DEVALTJ_CR_SIN3_SL		6
-#define NPCX_DEVALTJ_CR_SOUT3_SL	7
-#define NPCX_DEVALTE_CR_SIN4_SL		6
-#define NPCX_DEVALTE_CR_SOUT4_SL	7
+#define NPCX_DEVALTJ_CR_SIN1_SL1 0
+#define NPCX_DEVALTJ_CR_SOUT1_SL1 1
+#define NPCX_DEVALTJ_CR_SIN1_SL2 2
+#define NPCX_DEVALTJ_CR_SOUT1_SL2 3
+#define NPCX_DEVALTJ_CR_SIN2_SL 4
+#define NPCX_DEVALTJ_CR_SOUT2_SL 5
+#define NPCX_DEVALTJ_CR_SIN3_SL 6
+#define NPCX_DEVALTJ_CR_SOUT3_SL 7
+#define NPCX_DEVALTE_CR_SIN4_SL 6
+#define NPCX_DEVALTE_CR_SOUT4_SL 7
 
 /* SHI module version 2 enable bit */
-#define NPCX_DEVALTF_SHI_NEW		7
+#define NPCX_DEVALTF_SHI_NEW 7
 
 /* VCC_RST Pull-Up Disable */
-#define NPCX_DEVALTG_VCC1_RST_PUD	5
-#define NPCX_DEVALTG_PSL_OUT_SL		6
-#define NPCX_DEVALTG_PSL_GPO_SL		7
+#define NPCX_DEVALTG_VCC1_RST_PUD 5
+#define NPCX_DEVALTG_PSL_OUT_SL 6
+#define NPCX_DEVALTG_PSL_GPO_SL 7
 
 /* SMBus register fields */
-#define NPCX_SMBSEL_SMB4SEL		4
-#define NPCX_SMBSEL_SMB5SEL		5
-#define NPCX_SMBSEL_SMB6SEL		6
+#define NPCX_SMBSEL_SMB4SEL 4
+#define NPCX_SMBSEL_SMB5SEL 5
+#define NPCX_SMBSEL_SMB6SEL 6
 
 /* pin-mux for JTAG */
-#define NPCX_JEN_CTL1			REG8(NPCX_SCFG_BASE_ADDR + 0x120)
-#define NPCX_JEN_CTL1_JEN_EN_FIELD	FIELD(0, 4)
-#define NPCX_JEN_CTL1_JEN_EN_DIS	0x06
-#define NPCX_JEN_CTL1_JEN_EN_ENA	0x09
+#define NPCX_JEN_CTL1 REG8(NPCX_SCFG_BASE_ADDR + 0x120)
+#define NPCX_JEN_CTL1_JEN_EN_FIELD FIELD(0, 4)
+#define NPCX_JEN_CTL1_JEN_EN_DIS 0x06
+#define NPCX_JEN_CTL1_JEN_EN_ENA 0x09
 
 /* SMB enumeration: I2C port definitions. */
 enum {
-	NPCX_I2C_PORT0_0 = 0,	/* I2C port 0, bus 0 */
-	NPCX_I2C_PORT1_0,	/* I2C port 1, bus 0 */
-	NPCX_I2C_PORT2_0,	/* I2C port 2, bus 0 */
-	NPCX_I2C_PORT3_0,	/* I2C port 3, bus 0 */
-	NPCX_I2C_PORT4_1,	/* I2C port 4, bus 1 */
-	NPCX_I2C_PORT5_0,	/* I2C port 5, bus 0 */
-	NPCX_I2C_PORT5_1,	/* I2C port 5, bus 1 */
-	NPCX_I2C_PORT6_0,	/* I2C port 6, bus 0 */
-	NPCX_I2C_PORT6_1,	/* I2C port 6, bus 1 */
-	NPCX_I2C_PORT7_0,	/* I2C port 7, bus 0 */
+	NPCX_I2C_PORT0_0 = 0, /* I2C port 0, bus 0 */
+	NPCX_I2C_PORT1_0, /* I2C port 1, bus 0 */
+	NPCX_I2C_PORT2_0, /* I2C port 2, bus 0 */
+	NPCX_I2C_PORT3_0, /* I2C port 3, bus 0 */
+	NPCX_I2C_PORT4_1, /* I2C port 4, bus 1 */
+	NPCX_I2C_PORT5_0, /* I2C port 5, bus 0 */
+	NPCX_I2C_PORT5_1, /* I2C port 5, bus 1 */
+	NPCX_I2C_PORT6_0, /* I2C port 6, bus 0 */
+	NPCX_I2C_PORT6_1, /* I2C port 6, bus 1 */
+	NPCX_I2C_PORT7_0, /* I2C port 7, bus 0 */
 	NPCX_I2C_COUNT,
 };
 
 /* Power Management Controller (PMC) Registers */
-#define NPCX_FMUL_WIN_DLY	REG8(NPCX_PMC_BASE_ADDR + 0x010)
-#define NPCX_RAM_PD(offset)	REG8(NPCX_PMC_BASE_ADDR + 0x020 + (offset))
+#define NPCX_FMUL_WIN_DLY REG8(NPCX_PMC_BASE_ADDR + 0x010)
+#define NPCX_RAM_PD(offset) REG8(NPCX_PMC_BASE_ADDR + 0x020 + (offset))
 
 /* PMC register fields */
-#define NPCX_PWDWN_CTL3_SMB4_PD		4
-#define NPCX_PWDWN_CTL7_SMB5_PD		0
-#define NPCX_PWDWN_CTL7_SMB6_PD		1
-#define NPCX_PWDWN_CTL7_SMB7_PD		2
-#define NPCX_PWDWN_CTL7_ITIM64_PD	5
-#define NPCX_PWDWN_CTL7_UART2_PD	6
+#define NPCX_PWDWN_CTL3_SMB4_PD 4
+#define NPCX_PWDWN_CTL7_SMB5_PD 0
+#define NPCX_PWDWN_CTL7_SMB6_PD 1
+#define NPCX_PWDWN_CTL7_SMB7_PD 2
+#define NPCX_PWDWN_CTL7_ITIM64_PD 5
+#define NPCX_PWDWN_CTL7_UART2_PD 6
 
 /*
  * PMC enumeration:
@@ -331,38 +329,37 @@ enum NPCX_PMC_PWDWN_CTL_T {
 	NPCX_PMC_PWDWN_CNT,
 };
 
-#define CGC_I2C_MASK			(BIT(NPCX_PWDWN_CTL3_SMB0_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB1_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB2_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB3_PD) | \
-					BIT(NPCX_PWDWN_CTL3_SMB4_PD))
-#define CGC_I2C_MASK2			(BIT(NPCX_PWDWN_CTL7_SMB5_PD) | \
-					BIT(NPCX_PWDWN_CTL7_SMB6_PD) | \
-					BIT(NPCX_PWDWN_CTL7_SMB7_PD))
-#define CGC_UART2_MASK			BIT(NPCX_PWDWN_CTL7_UART2_PD)
+#define CGC_I2C_MASK                                                   \
+	(BIT(NPCX_PWDWN_CTL3_SMB0_PD) | BIT(NPCX_PWDWN_CTL3_SMB1_PD) | \
+	 BIT(NPCX_PWDWN_CTL3_SMB2_PD) | BIT(NPCX_PWDWN_CTL3_SMB3_PD) | \
+	 BIT(NPCX_PWDWN_CTL3_SMB4_PD))
+#define CGC_I2C_MASK2                                                  \
+	(BIT(NPCX_PWDWN_CTL7_SMB5_PD) | BIT(NPCX_PWDWN_CTL7_SMB6_PD) | \
+	 BIT(NPCX_PWDWN_CTL7_SMB7_PD))
+#define CGC_UART2_MASK BIT(NPCX_PWDWN_CTL7_UART2_PD)
 
 /* BBRAM register fields */
-#define NPCX_BKUP_STS_VSBY_STS		1
-#define NPCX_BKUP_STS_VCC1_STS		0
-#define NPCX_BKUP_STS_ALL_MASK \
+#define NPCX_BKUP_STS_VSBY_STS 1
+#define NPCX_BKUP_STS_VCC1_STS 0
+#define NPCX_BKUP_STS_ALL_MASK                                   \
 	(BIT(NPCX_BKUP_STS_IBBR) | BIT(NPCX_BKUP_STS_VSBY_STS) | \
-	BIT(NPCX_BKUP_STS_VCC1_STS))
-#define NPCX_BBRAM_SIZE			128 /* Size of BBRAM */
+	 BIT(NPCX_BKUP_STS_VCC1_STS))
+#define NPCX_BBRAM_SIZE 128 /* Size of BBRAM */
 
 /* ITIM registers */
-#define NPCX_ITCNT32(n)			REG32(NPCX_ITIM_BASE_ADDR(n) + 0x008)
+#define NPCX_ITCNT32(n) REG32(NPCX_ITIM_BASE_ADDR(n) + 0x008)
 
 /* Timer counter register used for 1 micro-second system tick */
-#define NPCX_ITCNT_SYSTEM		NPCX_ITCNT32(ITIM32_6)
+#define NPCX_ITCNT_SYSTEM NPCX_ITCNT32(ITIM32_6)
 /* Timer counter register used for others */
-#define NPCX_ITCNT			NPCX_ITCNT32
+#define NPCX_ITCNT NPCX_ITCNT32
 
 /* ITIM module No. used for event */
-#define ITIM_EVENT_NO			ITIM32_1
+#define ITIM_EVENT_NO ITIM32_1
 /* ITIM module No. used for watchdog */
-#define ITIM_WDG_NO				ITIM32_5
+#define ITIM_WDG_NO ITIM32_5
 /* ITIM module No. used for 1 micro-second system tick */
-#define ITIM_SYSTEM_NO			ITIM32_6
+#define ITIM_SYSTEM_NO ITIM32_6
 
 /* ITIM enumeration */
 enum ITIM_MODULE_T {
@@ -376,56 +373,56 @@ enum ITIM_MODULE_T {
 };
 
 /* Serial Host Interface (SHI) Registers - only available on SHI Version 2 */
-#define NPCX_SHICFG3			REG8(NPCX_SHI_BASE_ADDR + 0x00C)
-#define NPCX_SHICFG4			REG8(NPCX_SHI_BASE_ADDR + 0x00D)
-#define NPCX_SHICFG5			REG8(NPCX_SHI_BASE_ADDR + 0x00E)
-#define NPCX_EVSTAT2			REG8(NPCX_SHI_BASE_ADDR + 0x00F)
-#define NPCX_EVENABLE2			REG8(NPCX_SHI_BASE_ADDR + 0x010)
-#define NPCX_OBUF(n)			REG8(NPCX_SHI_BASE_ADDR + 0x020 + (n))
-#define NPCX_IBUF(n)			REG8(NPCX_SHI_BASE_ADDR + 0x0A0 + (n))
+#define NPCX_SHICFG3 REG8(NPCX_SHI_BASE_ADDR + 0x00C)
+#define NPCX_SHICFG4 REG8(NPCX_SHI_BASE_ADDR + 0x00D)
+#define NPCX_SHICFG5 REG8(NPCX_SHI_BASE_ADDR + 0x00E)
+#define NPCX_EVSTAT2 REG8(NPCX_SHI_BASE_ADDR + 0x00F)
+#define NPCX_EVENABLE2 REG8(NPCX_SHI_BASE_ADDR + 0x010)
+#define NPCX_OBUF(n) REG8(NPCX_SHI_BASE_ADDR + 0x020 + (n))
+#define NPCX_IBUF(n) REG8(NPCX_SHI_BASE_ADDR + 0x0A0 + (n))
 
 /* SHI register fields */
-#define NPCX_SHICFG3_OBUFLVLDIS		7
-#define NPCX_SHICFG4_IBUFLVLDIS		7
-#define NPCX_SHICFG5_IBUFLVL2		FIELD(0, 6)
-#define NPCX_SHICFG5_IBUFLVL2DIS	7
-#define NPCX_EVSTAT2_IBHF2		0
-#define NPCX_EVSTAT2_CSNRE		1
-#define NPCX_EVSTAT2_CSNFE		2
-#define NPCX_EVENABLE2_IBHF2EN		0
-#define NPCX_EVENABLE2_CSNREEN		1
-#define NPCX_EVENABLE2_CSNFEEN		2
+#define NPCX_SHICFG3_OBUFLVLDIS 7
+#define NPCX_SHICFG4_IBUFLVLDIS 7
+#define NPCX_SHICFG5_IBUFLVL2 FIELD(0, 6)
+#define NPCX_SHICFG5_IBUFLVL2DIS 7
+#define NPCX_EVSTAT2_IBHF2 0
+#define NPCX_EVSTAT2_CSNRE 1
+#define NPCX_EVSTAT2_CSNFE 2
+#define NPCX_EVENABLE2_IBHF2EN 0
+#define NPCX_EVENABLE2_CSNREEN 1
+#define NPCX_EVENABLE2_CSNFEEN 2
 
 /* eSPI register fields */
-#define NPCX_ESPIIE_BMTXDONEIE		19
-#define NPCX_ESPIIE_PBMRXIE		20
-#define NPCX_ESPIIE_PMSGRXIE		21
-#define NPCX_ESPIIE_BMBURSTERRIE	22
-#define NPCX_ESPIIE_BMBURSTDONEIE	23
-
-#define NPCX_ESPIWE_PBMRXWE		20
-#define NPCX_ESPIWE_PMSGRXWE		21
-
-#define NPCX_ESPISTS_VWUPDW		17
-#define NPCX_ESPISTS_BMTXDONE		19
-#define NPCX_ESPISTS_PBMRX		20
-#define NPCX_ESPISTS_PMSGRX		21
-#define NPCX_ESPISTS_BMBURSTERR		22
-#define NPCX_ESPISTS_BMBURSTDONE	23
-#define NPCX_ESPISTS_ESPIRST_LVL	24
-
-#define ESPIIE_BMTXDONE			BIT(NPCX_ESPIIE_BMTXDONEIE)
-#define ESPIIE_PBMRX			BIT(NPCX_ESPIIE_PBMRXIE)
-#define ESPIIE_PMSGRX			BIT(NPCX_ESPIIE_PMSGRXIE)
-#define ESPIIE_BMBURSTERR		BIT(NPCX_ESPIIE_BMBURSTERRIE)
-#define ESPIIE_BMBURSTDONE		BIT(NPCX_ESPIIE_BMBURSTDONEIE)
-
-#define ESPIWE_PBMRX			BIT(NPCX_ESPIWE_PBMRXWE)
-#define ESPIWE_PMSGRX			BIT(NPCX_ESPIWE_PMSGRXWE)
+#define NPCX_ESPIIE_BMTXDONEIE 19
+#define NPCX_ESPIIE_PBMRXIE 20
+#define NPCX_ESPIIE_PMSGRXIE 21
+#define NPCX_ESPIIE_BMBURSTERRIE 22
+#define NPCX_ESPIIE_BMBURSTDONEIE 23
+
+#define NPCX_ESPIWE_PBMRXWE 20
+#define NPCX_ESPIWE_PMSGRXWE 21
+
+#define NPCX_ESPISTS_VWUPDW 17
+#define NPCX_ESPISTS_BMTXDONE 19
+#define NPCX_ESPISTS_PBMRX 20
+#define NPCX_ESPISTS_PMSGRX 21
+#define NPCX_ESPISTS_BMBURSTERR 22
+#define NPCX_ESPISTS_BMBURSTDONE 23
+#define NPCX_ESPISTS_ESPIRST_LVL 24
+
+#define ESPIIE_BMTXDONE BIT(NPCX_ESPIIE_BMTXDONEIE)
+#define ESPIIE_PBMRX BIT(NPCX_ESPIIE_PBMRXIE)
+#define ESPIIE_PMSGRX BIT(NPCX_ESPIIE_PMSGRXIE)
+#define ESPIIE_BMBURSTERR BIT(NPCX_ESPIIE_BMBURSTERRIE)
+#define ESPIIE_BMBURSTDONE BIT(NPCX_ESPIIE_BMBURSTDONEIE)
+
+#define ESPIWE_PBMRX BIT(NPCX_ESPIWE_PBMRXWE)
+#define ESPIWE_PMSGRX BIT(NPCX_ESPIWE_PMSGRXWE)
 
 /* Bit field manipulation for VWEVMS Value */
-#define VWEVMS_WK_EN(e)			(((e)<<20) & 0x00100000)
-#define VWEVMS_INTWK_EN(e)		(VWEVMS_INT_EN(e) | VWEVMS_WK_EN(e))
+#define VWEVMS_WK_EN(e) (((e) << 20) & 0x00100000)
+#define VWEVMS_INTWK_EN(e) (VWEVMS_INT_EN(e) | VWEVMS_WK_EN(e))
 
 /* eSPI max supported frequency */
 enum {
@@ -449,61 +446,55 @@ enum {
 
 /* eSPI max frequency support per FMCLK */
 #if (FMCLK <= 33000000)
-#define NPCX_ESPI_MAXFREQ_MAX		NPCX_ESPI_MAXFREQ_33
+#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_33
 #else
-#define NPCX_ESPI_MAXFREQ_MAX		NPCX_ESPI_MAXFREQ_50
+#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_50
 #endif
 
 /* UART registers */
-#define NPCX_UART_WK_GROUP		MIWU_GROUP_8
-#define NPCX_UART_WK_BIT		7
-#define NPCX_UART2_WK_GROUP		MIWU_GROUP_1
-#define NPCX_UART2_WK_BIT		6
+#define NPCX_UART_WK_GROUP MIWU_GROUP_8
+#define NPCX_UART_WK_BIT 7
+#define NPCX_UART2_WK_GROUP MIWU_GROUP_1
+#define NPCX_UART2_WK_BIT 6
 
 /* MIWU registers */
-#define NPCX_WKEDG_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x00 + \
-					((n) * 0x10))
-#define NPCX_WKAEDG_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x01 + \
-					((n) * 0x10))
-#define NPCX_WKMOD_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x02 + \
-					((n) * 0x10))
-#define NPCX_WKPND_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x03 + \
-					((n) * 0x10))
-#define NPCX_WKPCL_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x04 + \
-					((n) * 0x10))
-#define NPCX_WKEN_ADDR(port, n)		(NPCX_MIWU_BASE_ADDR(port) + 0x05 + \
-					((n) * 0x10))
-#define NPCX_WKST_ADDR(port, n)		(NPCX_MIWU_BASE_ADDR(port) + 0x06 + \
-					((n) * 0x10))
-#define NPCX_WKINEN_ADDR(port, n)	(NPCX_MIWU_BASE_ADDR(port) + 0x07 + \
-					((n) * 0x10))
-
-#define NPCX_WKEDG(port, n)		REG8(NPCX_WKEDG_ADDR(port, n))
-#define NPCX_WKAEDG(port, n)		REG8(NPCX_WKAEDG_ADDR(port, n))
-#define NPCX_WKPND(port, n)		REG8(NPCX_WKPND_ADDR(port, n))
-#define NPCX_WKPCL(port, n)		REG8(NPCX_WKPCL_ADDR(port, n))
-#define NPCX_WKEN(port, n)		REG8(NPCX_WKEN_ADDR(port, n))
-#define NPCX_WKST(port, n)		REG8(NPCX_WKST_ADDR(port, n))
-#define NPCX_WKINEN(port, n)		REG8(NPCX_WKINEN_ADDR(port, n))
-#define NPCX_WKMOD(port, n)		REG8(NPCX_WKMOD_ADDR(port, n))
+#define NPCX_WKEDG_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x00 + ((n)*0x10))
+#define NPCX_WKAEDG_ADDR(port, n) \
+	(NPCX_MIWU_BASE_ADDR(port) + 0x01 + ((n)*0x10))
+#define NPCX_WKMOD_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x02 + ((n)*0x10))
+#define NPCX_WKPND_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x03 + ((n)*0x10))
+#define NPCX_WKPCL_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x04 + ((n)*0x10))
+#define NPCX_WKEN_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x05 + ((n)*0x10))
+#define NPCX_WKST_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x06 + ((n)*0x10))
+#define NPCX_WKINEN_ADDR(port, n) \
+	(NPCX_MIWU_BASE_ADDR(port) + 0x07 + ((n)*0x10))
+
+#define NPCX_WKEDG(port, n) REG8(NPCX_WKEDG_ADDR(port, n))
+#define NPCX_WKAEDG(port, n) REG8(NPCX_WKAEDG_ADDR(port, n))
+#define NPCX_WKPND(port, n) REG8(NPCX_WKPND_ADDR(port, n))
+#define NPCX_WKPCL(port, n) REG8(NPCX_WKPCL_ADDR(port, n))
+#define NPCX_WKEN(port, n) REG8(NPCX_WKEN_ADDR(port, n))
+#define NPCX_WKST(port, n) REG8(NPCX_WKST_ADDR(port, n))
+#define NPCX_WKINEN(port, n) REG8(NPCX_WKINEN_ADDR(port, n))
+#define NPCX_WKMOD(port, n) REG8(NPCX_WKMOD_ADDR(port, n))
 
 /* LCT register */
-#define NPCX_LCTCONT			REG8(NPCX_LCT_BASE_ADDR + 0x002)
-#define NPCX_LCTSTAT			REG8(NPCX_LCT_BASE_ADDR + 0x004)
-#define NPCX_LCTSECOND			REG8(NPCX_LCT_BASE_ADDR + 0x005)
-#define NPCX_LCTMINUTE			REG8(NPCX_LCT_BASE_ADDR + 0x006)
-#define NPCX_LCTHOUR			REG8(NPCX_LCT_BASE_ADDR + 0x008)
-#define NPCX_LCTDAY			REG8(NPCX_LCT_BASE_ADDR + 0x00A)
-#define NPCX_LCTWEEK			REG8(NPCX_LCT_BASE_ADDR + 0x00C)
+#define NPCX_LCTCONT REG8(NPCX_LCT_BASE_ADDR + 0x002)
+#define NPCX_LCTSTAT REG8(NPCX_LCT_BASE_ADDR + 0x004)
+#define NPCX_LCTSECOND REG8(NPCX_LCT_BASE_ADDR + 0x005)
+#define NPCX_LCTMINUTE REG8(NPCX_LCT_BASE_ADDR + 0x006)
+#define NPCX_LCTHOUR REG8(NPCX_LCT_BASE_ADDR + 0x008)
+#define NPCX_LCTDAY REG8(NPCX_LCT_BASE_ADDR + 0x00A)
+#define NPCX_LCTWEEK REG8(NPCX_LCT_BASE_ADDR + 0x00C)
 /* LCTCONT fields */
-#define NPCX_LCTCONT_EN			0
-#define NPCX_LCTCONT_EN_FIELD		FIELD(0, 1)
-#define NPCX_LCTCONT_EVEN		1
-#define NPCX_LCTCONT_PSL_EN		2
-#define NPCX_LCTCONT_CLK_EN		6
-#define NPCX_LCTCONT_VSBY_PWR		7
+#define NPCX_LCTCONT_EN 0
+#define NPCX_LCTCONT_EN_FIELD FIELD(0, 1)
+#define NPCX_LCTCONT_EVEN 1
+#define NPCX_LCTCONT_PSL_EN 2
+#define NPCX_LCTCONT_CLK_EN 6
+#define NPCX_LCTCONT_VSBY_PWR 7
 /* LCTSTAT fields */
-#define NPCX_LCTSTAT_EVST		0
+#define NPCX_LCTSTAT_EVST 0
 
 /* UART registers and functions */
 #if NPCX_UART_MODULE2
@@ -512,73 +503,73 @@ enum {
  * always 1 == MIWU_TABLE_1.
  */
 #define NPCX_UART_MIWU_IRQ NPCX_IRQ_WKINTG_1
-#define NPCX_UART_DEVALT		NPCX_DEVALT(ALT_GROUP_J)
-#define NPCX_UART_DEVALT_SIN_SL		NPCX_DEVALTJ_CR_SIN1_SL2
-#define NPCX_UART_DEVALT_SOUT_SL	NPCX_DEVALTJ_CR_SOUT1_SL2
-#define NPCX_UART_ALT_DEVALT		NPCX_DEVALT(ALT_GROUP_J)
-#define NPCX_UART_ALT_DEVALT_SIN_SL	NPCX_DEVALTJ_CR_SIN1_SL1
-#define NPCX_UART_ALT_DEVALT_SOUT_SL	NPCX_DEVALTJ_CR_SOUT1_SL1
+#define NPCX_UART_DEVALT NPCX_DEVALT(ALT_GROUP_J)
+#define NPCX_UART_DEVALT_SIN_SL NPCX_DEVALTJ_CR_SIN1_SL2
+#define NPCX_UART_DEVALT_SOUT_SL NPCX_DEVALTJ_CR_SOUT1_SL2
+#define NPCX_UART_ALT_DEVALT NPCX_DEVALT(ALT_GROUP_J)
+#define NPCX_UART_ALT_DEVALT_SIN_SL NPCX_DEVALTJ_CR_SIN1_SL1
+#define NPCX_UART_ALT_DEVALT_SOUT_SL NPCX_DEVALTJ_CR_SOUT1_SL1
 #else /* !NPCX_UART_MODULE2 */
-#define NPCX_UART_MIWU_IRQ		NPCX_IRQ_WKINTB_1
-#define NPCX_UART_DEVALT		NPCX_DEVALT(ALT_GROUP_J)
-#define NPCX_UART_DEVALT_SIN_SL		NPCX_DEVALTJ_CR_SIN1_SL1
-#define NPCX_UART_DEVALT_SOUT_SL	NPCX_DEVALTJ_CR_SOUT1_SL1
-#define NPCX_UART_ALT_DEVALT		NPCX_DEVALT(ALT_GROUP_J)
-#define NPCX_UART_ALT_DEVALT_SIN_SL	NPCX_DEVALTJ_CR_SIN1_SL2
-#define NPCX_UART_ALT_DEVALT_SOUT_SL	NPCX_DEVALTJ_CR_SOUT1_SL2
+#define NPCX_UART_MIWU_IRQ NPCX_IRQ_WKINTB_1
+#define NPCX_UART_DEVALT NPCX_DEVALT(ALT_GROUP_J)
+#define NPCX_UART_DEVALT_SIN_SL NPCX_DEVALTJ_CR_SIN1_SL1
+#define NPCX_UART_DEVALT_SOUT_SL NPCX_DEVALTJ_CR_SOUT1_SL1
+#define NPCX_UART_ALT_DEVALT NPCX_DEVALT(ALT_GROUP_J)
+#define NPCX_UART_ALT_DEVALT_SIN_SL NPCX_DEVALTJ_CR_SIN1_SL2
+#define NPCX_UART_ALT_DEVALT_SOUT_SL NPCX_DEVALTJ_CR_SOUT1_SL2
 #endif /* NPCX_UART_MODULE2 */
 
 /* ADC register */
-#define NPCX_ADCSTS		REG16(NPCX_ADC_BASE_ADDR + 0x000)
-#define NPCX_ADCCNF		REG16(NPCX_ADC_BASE_ADDR + 0x002)
-#define NPCX_ATCTL		REG16(NPCX_ADC_BASE_ADDR + 0x004)
-#define NPCX_ASCADD		REG16(NPCX_ADC_BASE_ADDR + 0x006)
-#define NPCX_ADCCS		REG16(NPCX_ADC_BASE_ADDR + 0x008)
-#define NPCX_THRCTS		REG16(NPCX_ADC_BASE_ADDR + 0x01A)
-#define NPCX_ADCCNF2		REG16(NPCX_ADC_BASE_ADDR + 0x020)
-#define NPCX_GENDLY		REG16(NPCX_ADC_BASE_ADDR + 0x022)
-#define NPCX_MEAST		REG16(NPCX_ADC_BASE_ADDR + 0x026)
+#define NPCX_ADCSTS REG16(NPCX_ADC_BASE_ADDR + 0x000)
+#define NPCX_ADCCNF REG16(NPCX_ADC_BASE_ADDR + 0x002)
+#define NPCX_ATCTL REG16(NPCX_ADC_BASE_ADDR + 0x004)
+#define NPCX_ASCADD REG16(NPCX_ADC_BASE_ADDR + 0x006)
+#define NPCX_ADCCS REG16(NPCX_ADC_BASE_ADDR + 0x008)
+#define NPCX_THRCTS REG16(NPCX_ADC_BASE_ADDR + 0x01A)
+#define NPCX_ADCCNF2 REG16(NPCX_ADC_BASE_ADDR + 0x020)
+#define NPCX_GENDLY REG16(NPCX_ADC_BASE_ADDR + 0x022)
+#define NPCX_MEAST REG16(NPCX_ADC_BASE_ADDR + 0x026)
 /* NOTE: This is 0-based for the ADC channels. */
-#define NPCX_CHNDAT(n)		REG16(NPCX_ADC_BASE_ADDR + 0x040 + (2L*(n)))
+#define NPCX_CHNDAT(n) REG16(NPCX_ADC_BASE_ADDR + 0x040 + (2L * (n)))
 /* NOTE: These are 1-based for the threshold detectors. */
-#define NPCX_THRCTL(n)		REG16(NPCX_ADC_BASE_ADDR + 0x05E + (2L*(n)))
+#define NPCX_THRCTL(n) REG16(NPCX_ADC_BASE_ADDR + 0x05E + (2L * (n)))
 
 /* ADC register fields */
-#define NPCX_ADCSTS_EOCEV		0
-#define NPCX_ADCCNF_ADCMD_FIELD		FIELD(1, 2)
-#define NPCX_ADCCNF_ADCRPTC		3
-#define NPCX_ADCCNF_INTECEN		6
-#define NPCX_ADCCNF_START		4
-#define NPCX_ADCCNF_ADCEN		0
-#define NPCX_ADCCNF_STOP		11
-#define NPCX_ATCTL_SCLKDIV_FIELD	FIELD(0, 6)
-#define NPCX_ATCTL_DLY_FIELD		FIELD(8, 3)
-#define NPCX_ASCADD_SADDR_FIELD		FIELD(0, 5)
-#define NPCX_THRCTS_ADC_WKEN		15
-#define NPCX_THRCTS_THR6_IEN		13
-#define NPCX_THRCTS_THR5_IEN		12
-#define NPCX_THRCTS_THR4_IEN		11
-#define NPCX_THRCTS_THR3_IEN		10
-#define NPCX_THRCTS_THR2_IEN		9
-#define NPCX_THRCTS_THR1_IEN		8
-#define NPCX_THRCTS_ADC_EVENT		7
-#define NPCX_THRCTS_THR6_STS		5
-#define NPCX_THRCTS_THR5_STS		4
-#define NPCX_THRCTS_THR4_STS		3
-#define NPCX_THRCTS_THR3_STS		2
-#define NPCX_THRCTS_THR2_STS		1
-#define NPCX_THRCTS_THR1_STS		0
-#define NPCX_CHNDAT_CHDAT_FIELD		FIELD(0, 10)
-#define NPCX_CHNDAT_NEW			15
-#define NPCX_THRCTL_THEN		15
-#define NPCX_THRCTL_L_H			14
-#define NPCX_THRCTL_CHNSEL		FIELD(10, 4)
-#define NPCX_THRCTL_THRVAL		FIELD(0, 10)
-
-#define NPCX_ADC_THRESH1		1
-#define NPCX_ADC_THRESH2		2
-#define NPCX_ADC_THRESH3		3
-#define NPCX_ADC_THRESH4		4
-#define NPCX_ADC_THRESH5		5
-#define NPCX_ADC_THRESH6		6
-#define NPCX_ADC_THRESH_CNT		6
+#define NPCX_ADCSTS_EOCEV 0
+#define NPCX_ADCCNF_ADCMD_FIELD FIELD(1, 2)
+#define NPCX_ADCCNF_ADCRPTC 3
+#define NPCX_ADCCNF_INTECEN 6
+#define NPCX_ADCCNF_START 4
+#define NPCX_ADCCNF_ADCEN 0
+#define NPCX_ADCCNF_STOP 11
+#define NPCX_ATCTL_SCLKDIV_FIELD FIELD(0, 6)
+#define NPCX_ATCTL_DLY_FIELD FIELD(8, 3)
+#define NPCX_ASCADD_SADDR_FIELD FIELD(0, 5)
+#define NPCX_THRCTS_ADC_WKEN 15
+#define NPCX_THRCTS_THR6_IEN 13
+#define NPCX_THRCTS_THR5_IEN 12
+#define NPCX_THRCTS_THR4_IEN 11
+#define NPCX_THRCTS_THR3_IEN 10
+#define NPCX_THRCTS_THR2_IEN 9
+#define NPCX_THRCTS_THR1_IEN 8
+#define NPCX_THRCTS_ADC_EVENT 7
+#define NPCX_THRCTS_THR6_STS 5
+#define NPCX_THRCTS_THR5_STS 4
+#define NPCX_THRCTS_THR4_STS 3
+#define NPCX_THRCTS_THR3_STS 2
+#define NPCX_THRCTS_THR2_STS 1
+#define NPCX_THRCTS_THR1_STS 0
+#define NPCX_CHNDAT_CHDAT_FIELD FIELD(0, 10)
+#define NPCX_CHNDAT_NEW 15
+#define NPCX_THRCTL_THEN 15
+#define NPCX_THRCTL_L_H 14
+#define NPCX_THRCTL_CHNSEL FIELD(10, 4)
+#define NPCX_THRCTL_THRVAL FIELD(0, 10)
+
+#define NPCX_ADC_THRESH1 1
+#define NPCX_ADC_THRESH2 2
+#define NPCX_ADC_THRESH3 3
+#define NPCX_ADC_THRESH4 4
+#define NPCX_ADC_THRESH5 5
+#define NPCX_ADC_THRESH6 6
+#define NPCX_ADC_THRESH_CNT 6
diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h
index 8f0c7431a6..922d787323 100644
--- a/chip/npcx/registers.h
+++ b/chip/npcx/registers.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -17,28 +17,32 @@
  * Macro Functions
  */
 /* Bit functions */
-#define SET_BIT(reg, bit)           ((reg) |= (0x1 << (bit)))
-#define CLEAR_BIT(reg, bit)         ((reg) &= (~(0x1 << (bit))))
-#define IS_BIT_SET(reg, bit)        (((reg) >> (bit)) & (0x1))
-#define UPDATE_BIT(reg, bit, cond)  {	if (cond) \
-						SET_BIT(reg, bit); \
-					else \
-						CLEAR_BIT(reg, bit); }
+#define SET_BIT(reg, bit) ((reg) |= (0x1 << (bit)))
+#define CLEAR_BIT(reg, bit) ((reg) &= (~(0x1 << (bit))))
+#define IS_BIT_SET(reg, bit) (((reg) >> (bit)) & (0x1))
+#define UPDATE_BIT(reg, bit, cond)           \
+	{                                    \
+		if (cond)                    \
+			SET_BIT(reg, bit);   \
+		else                         \
+			CLEAR_BIT(reg, bit); \
+	}
 /* Field functions */
-#define GET_POS_FIELD(pos, size)    pos
-#define GET_SIZE_FIELD(pos, size)   size
-#define FIELD_POS(field)            GET_POS_##field
-#define FIELD_SIZE(field)           GET_SIZE_##field
+#define GET_POS_FIELD(pos, size) pos
+#define GET_SIZE_FIELD(pos, size) size
+#define FIELD_POS(field) GET_POS_##field
+#define FIELD_SIZE(field) GET_SIZE_##field
 /* Read field functions */
 #define GET_FIELD(reg, field) \
 	_GET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field))
-#define _GET_FIELD_(reg, f_pos, f_size) (((reg)>>(f_pos)) & ((1<<(f_size))-1))
+#define _GET_FIELD_(reg, f_pos, f_size) \
+	(((reg) >> (f_pos)) & ((1 << (f_size)) - 1))
 /* Write field functions */
 #define SET_FIELD(reg, field, value) \
 	_SET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field), value)
-#define _SET_FIELD_(reg, f_pos, f_size, value) \
-	((reg) = ((reg) & (~(((1 << (f_size))-1) << (f_pos)))) \
-			| ((value) << (f_pos)))
+#define _SET_FIELD_(reg, f_pos, f_size, value)                     \
+	((reg) = ((reg) & (~(((1 << (f_size)) - 1) << (f_pos)))) | \
+		 ((value) << (f_pos)))
 
 /******************************************************************************/
 /*
@@ -46,216 +50,212 @@
  */
 
 /* Global Definition */
-#define I2C_7BITS_ADDR                   0
+#define I2C_7BITS_ADDR 0
 /* Switcher of features */
-#define SUPPORT_LCT                      1
-#define SUPPORT_WDG                      1
-#define SUPPORT_P80_SEG                  0 /* Note: it uses KSO10 & KSO11 */
+#define SUPPORT_LCT 1
+#define SUPPORT_WDG 1
+#define SUPPORT_P80_SEG 0 /* Note: it uses KSO10 & KSO11 */
 /* Switcher of debugging */
-#define DEBUG_GPIO                       0
-#define DEBUG_I2C                        0
-#define DEBUG_TMR                        0
-#define DEBUG_WDG                        0
-#define DEBUG_FAN                        0
-#define DEBUG_PWM                        0
-#define DEBUG_SPI                        0
-#define DEBUG_FLH                        0
-#define DEBUG_PECI                       0
-#define DEBUG_SHI                        0
-#define DEBUG_CLK                        0
-#define DEBUG_LPC                        0
-#define DEBUG_ESPI                       0
-#define DEBUG_CEC                        0
-#define DEBUG_SIB                        0
-#define DEBUG_PS2                        0
+#define DEBUG_GPIO 0
+#define DEBUG_I2C 0
+#define DEBUG_TMR 0
+#define DEBUG_WDG 0
+#define DEBUG_FAN 0
+#define DEBUG_PWM 0
+#define DEBUG_SPI 0
+#define DEBUG_FLH 0
+#define DEBUG_PECI 0
+#define DEBUG_SHI 0
+#define DEBUG_CLK 0
+#define DEBUG_LPC 0
+#define DEBUG_ESPI 0
+#define DEBUG_CEC 0
+#define DEBUG_SIB 0
+#define DEBUG_PS2 0
 
 /* Modules Map */
-#define NPCX_ESPI_BASE_ADDR              0x4000A000
-#define NPCX_MDC_BASE_ADDR               0x4000C000
-#define NPCX_PMC_BASE_ADDR               0x4000D000
-#define NPCX_SIB_BASE_ADDR               0x4000E000
-#define NPCX_SHI_BASE_ADDR               0x4000F000
-#define NPCX_SHM_BASE_ADDR               0x40010000
-#define NPCX_GDMA_BASE_ADDR              0x40011000
-#define NPCX_FIU_BASE_ADDR               0x40020000
-#define NPCX_KBSCAN_REGS_BASE            0x400A3000
-#define NPCX_WOV_BASE_ADDR               0x400A4000
-#define NPCX_APM_BASE_ADDR               0x400A4800
-#define NPCX_GLUE_REGS_BASE              0x400A5000
-#define NPCX_BBRAM_BASE_ADDR             0x400AF000
-#define NPCX_PS2_BASE_ADDR               0x400B1000
-#define NPCX_HFCG_BASE_ADDR              0x400B5000
-#define NPCX_LFCG_BASE_ADDR              0x400B5100
-#define NPCX_FMUL2_BASE_ADDR             0x400B5200
-#define NPCX_MTC_BASE_ADDR               0x400B7000
-#define NPCX_MSWC_BASE_ADDR              0x400C1000
-#define NPCX_SCFG_BASE_ADDR              0x400C3000
-#define NPCX_KBC_BASE_ADDR               0x400C7000
-#define NPCX_ADC_BASE_ADDR               0x400D1000
-#define NPCX_SPI_BASE_ADDR               0x400D2000
-#define NPCX_PECI_BASE_ADDR              0x400D4000
-#define NPCX_TWD_BASE_ADDR               0x400D8000
+#define NPCX_ESPI_BASE_ADDR 0x4000A000
+#define NPCX_MDC_BASE_ADDR 0x4000C000
+#define NPCX_PMC_BASE_ADDR 0x4000D000
+#define NPCX_SIB_BASE_ADDR 0x4000E000
+#define NPCX_SHI_BASE_ADDR 0x4000F000
+#define NPCX_SHM_BASE_ADDR 0x40010000
+#define NPCX_GDMA_BASE_ADDR 0x40011000
+#define NPCX_FIU_BASE_ADDR 0x40020000
+#define NPCX_KBSCAN_REGS_BASE 0x400A3000
+#define NPCX_WOV_BASE_ADDR 0x400A4000
+#define NPCX_APM_BASE_ADDR 0x400A4800
+#define NPCX_GLUE_REGS_BASE 0x400A5000
+#define NPCX_BBRAM_BASE_ADDR 0x400AF000
+#define NPCX_PS2_BASE_ADDR 0x400B1000
+#define NPCX_HFCG_BASE_ADDR 0x400B5000
+#define NPCX_LFCG_BASE_ADDR 0x400B5100
+#define NPCX_FMUL2_BASE_ADDR 0x400B5200
+#define NPCX_MTC_BASE_ADDR 0x400B7000
+#define NPCX_MSWC_BASE_ADDR 0x400C1000
+#define NPCX_SCFG_BASE_ADDR 0x400C3000
+#define NPCX_KBC_BASE_ADDR 0x400C7000
+#define NPCX_ADC_BASE_ADDR 0x400D1000
+#define NPCX_SPI_BASE_ADDR 0x400D2000
+#define NPCX_PECI_BASE_ADDR 0x400D4000
+#define NPCX_TWD_BASE_ADDR 0x400D8000
 
 /* Multi-Modules Map */
-#define NPCX_PWM_BASE_ADDR(mdl)          (0x40080000 + ((mdl) * 0x2000L))
-#define NPCX_GPIO_BASE_ADDR(mdl)         (0x40081000 + ((mdl) * 0x2000L))
-#define NPCX_ITIM_BASE_ADDR(mdl)         (0x400B0000 + ((mdl) * 0x2000L))
-#define NPCX_MIWU_BASE_ADDR(mdl)         (0x400BB000 + ((mdl) * 0x2000L))
-#define NPCX_MFT_BASE_ADDR(mdl)          (0x400E1000 + ((mdl) * 0x2000L))
-#define NPCX_PM_CH_BASE_ADDR(mdl)        (0x400C9000 + ((mdl) * 0x2000L))
+#define NPCX_PWM_BASE_ADDR(mdl) (0x40080000 + ((mdl)*0x2000L))
+#define NPCX_GPIO_BASE_ADDR(mdl) (0x40081000 + ((mdl)*0x2000L))
+#define NPCX_ITIM_BASE_ADDR(mdl) (0x400B0000 + ((mdl)*0x2000L))
+#define NPCX_MIWU_BASE_ADDR(mdl) (0x400BB000 + ((mdl)*0x2000L))
+#define NPCX_MFT_BASE_ADDR(mdl) (0x400E1000 + ((mdl)*0x2000L))
+#define NPCX_PM_CH_BASE_ADDR(mdl) (0x400C9000 + ((mdl)*0x2000L))
 
 /*
  * NPCX-IRQ numbers
  */
-#define NPCX_IRQ_0                       0
-#define NPCX_IRQ_1                       1
-#define NPCX_IRQ_2                       2
-#define NPCX_IRQ_3                       3
-#define NPCX_IRQ_4                       4
-#define NPCX_IRQ_5                       5
-#define NPCX_IRQ_6                       6
-#define NPCX_IRQ_7                       7
-#define NPCX_IRQ_8                       8
-#define NPCX_IRQ_9                       9
-#define NPCX_IRQ_10                      10
-#define NPCX_IRQ_11                      11
-#define NPCX_IRQ_12                      12
-#define NPCX_IRQ_13                      13
-#define NPCX_IRQ_14                      14
-#define NPCX_IRQ_15                      15
-#define NPCX_IRQ_16                      16
-#define NPCX_IRQ_17                      17
-#define NPCX_IRQ_18                      18
-#define NPCX_IRQ_19                      19
-#define NPCX_IRQ_20                      20
-#define NPCX_IRQ_21                      21
-#define NPCX_IRQ_22                      22
-#define NPCX_IRQ_23                      23
-#define NPCX_IRQ_24                      24
-#define NPCX_IRQ_25                      25
-#define NPCX_IRQ_26                      26
-#define NPCX_IRQ_27                      27
-#define NPCX_IRQ_28                      28
-#define NPCX_IRQ_29                      29
-#define NPCX_IRQ_30                      30
-#define NPCX_IRQ_31                      31
-#define NPCX_IRQ_32                      32
-#define NPCX_IRQ_33                      33
-#define NPCX_IRQ_34                      34
-#define NPCX_IRQ_35                      35
-#define NPCX_IRQ_36                      36
-#define NPCX_IRQ_37                      37
-#define NPCX_IRQ_38                      38
-#define NPCX_IRQ_39                      39
-#define NPCX_IRQ_40                      40
-#define NPCX_IRQ_41                      41
-#define NPCX_IRQ_42                      42
-#define NPCX_IRQ_43                      43
-#define NPCX_IRQ_44                      44
-#define NPCX_IRQ_45                      45
-#define NPCX_IRQ_46                      46
-#define NPCX_IRQ_47                      47
-#define NPCX_IRQ_48                      48
-#define NPCX_IRQ_49                      49
-#define NPCX_IRQ_50                      50
-#define NPCX_IRQ_51                      51
-#define NPCX_IRQ_52                      52
-#define NPCX_IRQ_53                      53
-#define NPCX_IRQ_54                      54
-#define NPCX_IRQ_55                      55
-#define NPCX_IRQ_56                      56
-#define NPCX_IRQ_57                      57
-#define NPCX_IRQ_58                      58
-#define NPCX_IRQ_59                      59
-#define NPCX_IRQ_60                      60
-#define NPCX_IRQ_61                      61
-#define NPCX_IRQ_62                      62
-#define NPCX_IRQ_63                      63
-
-#define NPCX_IRQ_COUNT                   64
+#define NPCX_IRQ_0 0
+#define NPCX_IRQ_1 1
+#define NPCX_IRQ_2 2
+#define NPCX_IRQ_3 3
+#define NPCX_IRQ_4 4
+#define NPCX_IRQ_5 5
+#define NPCX_IRQ_6 6
+#define NPCX_IRQ_7 7
+#define NPCX_IRQ_8 8
+#define NPCX_IRQ_9 9
+#define NPCX_IRQ_10 10
+#define NPCX_IRQ_11 11
+#define NPCX_IRQ_12 12
+#define NPCX_IRQ_13 13
+#define NPCX_IRQ_14 14
+#define NPCX_IRQ_15 15
+#define NPCX_IRQ_16 16
+#define NPCX_IRQ_17 17
+#define NPCX_IRQ_18 18
+#define NPCX_IRQ_19 19
+#define NPCX_IRQ_20 20
+#define NPCX_IRQ_21 21
+#define NPCX_IRQ_22 22
+#define NPCX_IRQ_23 23
+#define NPCX_IRQ_24 24
+#define NPCX_IRQ_25 25
+#define NPCX_IRQ_26 26
+#define NPCX_IRQ_27 27
+#define NPCX_IRQ_28 28
+#define NPCX_IRQ_29 29
+#define NPCX_IRQ_30 30
+#define NPCX_IRQ_31 31
+#define NPCX_IRQ_32 32
+#define NPCX_IRQ_33 33
+#define NPCX_IRQ_34 34
+#define NPCX_IRQ_35 35
+#define NPCX_IRQ_36 36
+#define NPCX_IRQ_37 37
+#define NPCX_IRQ_38 38
+#define NPCX_IRQ_39 39
+#define NPCX_IRQ_40 40
+#define NPCX_IRQ_41 41
+#define NPCX_IRQ_42 42
+#define NPCX_IRQ_43 43
+#define NPCX_IRQ_44 44
+#define NPCX_IRQ_45 45
+#define NPCX_IRQ_46 46
+#define NPCX_IRQ_47 47
+#define NPCX_IRQ_48 48
+#define NPCX_IRQ_49 49
+#define NPCX_IRQ_50 50
+#define NPCX_IRQ_51 51
+#define NPCX_IRQ_52 52
+#define NPCX_IRQ_53 53
+#define NPCX_IRQ_54 54
+#define NPCX_IRQ_55 55
+#define NPCX_IRQ_56 56
+#define NPCX_IRQ_57 57
+#define NPCX_IRQ_58 58
+#define NPCX_IRQ_59 59
+#define NPCX_IRQ_60 60
+#define NPCX_IRQ_61 61
+#define NPCX_IRQ_62 62
+#define NPCX_IRQ_63 63
+
+#define NPCX_IRQ_COUNT 64
 
 /******************************************************************************/
 /* High Frequency Clock Generator (HFCG) registers */
-#define NPCX_HFCGCTRL                     REG8(NPCX_HFCG_BASE_ADDR + 0x000)
-#define NPCX_HFCGML                       REG8(NPCX_HFCG_BASE_ADDR + 0x002)
-#define NPCX_HFCGMH                       REG8(NPCX_HFCG_BASE_ADDR + 0x004)
-#define NPCX_HFCGN                        REG8(NPCX_HFCG_BASE_ADDR + 0x006)
-#define NPCX_HFCGP                        REG8(NPCX_HFCG_BASE_ADDR + 0x008)
-#define NPCX_HFCBCD                       REG8(NPCX_HFCG_BASE_ADDR + 0x010)
+#define NPCX_HFCGCTRL REG8(NPCX_HFCG_BASE_ADDR + 0x000)
+#define NPCX_HFCGML REG8(NPCX_HFCG_BASE_ADDR + 0x002)
+#define NPCX_HFCGMH REG8(NPCX_HFCG_BASE_ADDR + 0x004)
+#define NPCX_HFCGN REG8(NPCX_HFCG_BASE_ADDR + 0x006)
+#define NPCX_HFCGP REG8(NPCX_HFCG_BASE_ADDR + 0x008)
+#define NPCX_HFCBCD REG8(NPCX_HFCG_BASE_ADDR + 0x010)
 
 /* HFCG register fields */
-#define NPCX_HFCGCTRL_LOAD               0
-#define NPCX_HFCGCTRL_LOCK               2
-#define NPCX_HFCGCTRL_CLK_CHNG           7
+#define NPCX_HFCGCTRL_LOAD 0
+#define NPCX_HFCGCTRL_LOCK 2
+#define NPCX_HFCGCTRL_CLK_CHNG 7
 
 /******************************************************************************/
 /* Low Frequency Clock Generator (LFCG) registers */
-#define NPCX_LFCGCTL                      REG8(NPCX_LFCG_BASE_ADDR + 0x000)
-#define NPCX_HFRDI                       REG16(NPCX_LFCG_BASE_ADDR + 0x002)
-#define NPCX_HFRDF                       REG16(NPCX_LFCG_BASE_ADDR + 0x004)
-#define NPCX_FRCDIV                      REG16(NPCX_LFCG_BASE_ADDR + 0x006)
-#define NPCX_DIVCOR1                     REG16(NPCX_LFCG_BASE_ADDR + 0x008)
-#define NPCX_DIVCOR2                     REG16(NPCX_LFCG_BASE_ADDR + 0x00A)
-#define NPCX_LFCGCTL2                     REG8(NPCX_LFCG_BASE_ADDR + 0x014)
+#define NPCX_LFCGCTL REG8(NPCX_LFCG_BASE_ADDR + 0x000)
+#define NPCX_HFRDI REG16(NPCX_LFCG_BASE_ADDR + 0x002)
+#define NPCX_HFRDF REG16(NPCX_LFCG_BASE_ADDR + 0x004)
+#define NPCX_FRCDIV REG16(NPCX_LFCG_BASE_ADDR + 0x006)
+#define NPCX_DIVCOR1 REG16(NPCX_LFCG_BASE_ADDR + 0x008)
+#define NPCX_DIVCOR2 REG16(NPCX_LFCG_BASE_ADDR + 0x00A)
+#define NPCX_LFCGCTL2 REG8(NPCX_LFCG_BASE_ADDR + 0x014)
 
 /* LFCG register fields */
-#define NPCX_LFCGCTL_XTCLK_VAL            7
-#define NPCX_LFCGCTL2_XT_OSC_SL_EN        6
+#define NPCX_LFCGCTL_XTCLK_VAL 7
+#define NPCX_LFCGCTL2_XT_OSC_SL_EN 6
 
 /******************************************************************************/
 /* CR UART Register */
-#define NPCX_UTBUF(n)                    REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x000)
-#define NPCX_URBUF(n)                    REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x002)
-#define NPCX_UICTRL(n)                   REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x004)
-#define NPCX_USTAT(n)                    REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x006)
-#define NPCX_UFRS(n)                     REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x008)
-#define NPCX_UMDSL(n)                    REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x00A)
-#define NPCX_UBAUD(n)                    REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x00C)
-#define NPCX_UPSR(n)                     REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x00E)
+#define NPCX_UTBUF(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x000)
+#define NPCX_URBUF(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x002)
+#define NPCX_UICTRL(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x004)
+#define NPCX_USTAT(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x006)
+#define NPCX_UFRS(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x008)
+#define NPCX_UMDSL(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x00A)
+#define NPCX_UBAUD(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x00C)
+#define NPCX_UPSR(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x00E)
 
 /******************************************************************************/
 /* KBSCAN registers */
-#define NPCX_KBSIN                        REG8(NPCX_KBSCAN_REGS_BASE + 0x04)
-#define NPCX_KBSINPU                      REG8(NPCX_KBSCAN_REGS_BASE + 0x05)
-#define NPCX_KBSOUT0                     REG16(NPCX_KBSCAN_REGS_BASE + 0x06)
-#define NPCX_KBSOUT1                     REG16(NPCX_KBSCAN_REGS_BASE + 0x08)
-#define NPCX_KBS_BUF_INDX                 REG8(NPCX_KBSCAN_REGS_BASE + 0x0A)
-#define NPCX_KBS_BUF_DATA                 REG8(NPCX_KBSCAN_REGS_BASE + 0x0B)
-#define NPCX_KBSEVT                       REG8(NPCX_KBSCAN_REGS_BASE + 0x0C)
-#define NPCX_KBSCTL                       REG8(NPCX_KBSCAN_REGS_BASE + 0x0D)
-#define NPCX_KBS_CFG_INDX                 REG8(NPCX_KBSCAN_REGS_BASE + 0x0E)
-#define NPCX_KBS_CFG_DATA                 REG8(NPCX_KBSCAN_REGS_BASE + 0x0F)
+#define NPCX_KBSIN REG8(NPCX_KBSCAN_REGS_BASE + 0x04)
+#define NPCX_KBSINPU REG8(NPCX_KBSCAN_REGS_BASE + 0x05)
+#define NPCX_KBSOUT0 REG16(NPCX_KBSCAN_REGS_BASE + 0x06)
+#define NPCX_KBSOUT1 REG16(NPCX_KBSCAN_REGS_BASE + 0x08)
+#define NPCX_KBS_BUF_INDX REG8(NPCX_KBSCAN_REGS_BASE + 0x0A)
+#define NPCX_KBS_BUF_DATA REG8(NPCX_KBSCAN_REGS_BASE + 0x0B)
+#define NPCX_KBSEVT REG8(NPCX_KBSCAN_REGS_BASE + 0x0C)
+#define NPCX_KBSCTL REG8(NPCX_KBSCAN_REGS_BASE + 0x0D)
+#define NPCX_KBS_CFG_INDX REG8(NPCX_KBSCAN_REGS_BASE + 0x0E)
+#define NPCX_KBS_CFG_DATA REG8(NPCX_KBSCAN_REGS_BASE + 0x0F)
 
 /* KBSCAN register fields */
-#define NPCX_KBSBUFINDX                  0
-#define NPCX_KBSDONE                     0
-#define NPCX_KBSERR                      1
-#define NPCX_KBSSTART                    0
-#define NPCX_KBSMODE                     1
-#define NPCX_KBSIEN                      2
-#define NPCX_KBSINC                      3
-#define NPCX_KBSCFGINDX                  0
+#define NPCX_KBSBUFINDX 0
+#define NPCX_KBSDONE 0
+#define NPCX_KBSERR 1
+#define NPCX_KBSSTART 0
+#define NPCX_KBSMODE 1
+#define NPCX_KBSIEN 2
+#define NPCX_KBSINC 3
+#define NPCX_KBSCFGINDX 0
 
 /* KBSCAN definitions */
-#define KB_ROW_NUM  8  /* Rows numbers of keyboard matrix */
-#define KB_COL_NUM  18 /* Columns numbers of keyboard matrix */
-#define KB_ROW_MASK ((1<<KB_ROW_NUM) - 1) /* Mask of rows of keyboard matrix */
+#define KB_ROW_NUM 8 /* Rows numbers of keyboard matrix */
+#define KB_COL_NUM 18 /* Columns numbers of keyboard matrix */
+#define KB_ROW_MASK \
+	((1 << KB_ROW_NUM) - 1) /* Mask of rows of keyboard matrix */
 
 /******************************************************************************/
 /* GLUE registers */
-#define NPCX_GLUE_SDPD0                   REG8(NPCX_GLUE_REGS_BASE + 0x010)
-#define NPCX_GLUE_SDPD1                   REG8(NPCX_GLUE_REGS_BASE + 0x012)
-#define NPCX_GLUE_SDP_CTS                 REG8(NPCX_GLUE_REGS_BASE + 0x014)
-#define NPCX_GLUE_SMBSEL                  REG8(NPCX_GLUE_REGS_BASE + 0x021)
+#define NPCX_GLUE_SDPD0 REG8(NPCX_GLUE_REGS_BASE + 0x010)
+#define NPCX_GLUE_SDPD1 REG8(NPCX_GLUE_REGS_BASE + 0x012)
+#define NPCX_GLUE_SDP_CTS REG8(NPCX_GLUE_REGS_BASE + 0x014)
+#define NPCX_GLUE_SMBSEL REG8(NPCX_GLUE_REGS_BASE + 0x021)
 /******************************************************************************/
 
 /* MIWU enumeration */
-enum {
-	MIWU_TABLE_0,
-	MIWU_TABLE_1,
-	MIWU_TABLE_2,
-	MIWU_TABLE_COUNT
-};
+enum { MIWU_TABLE_0, MIWU_TABLE_1, MIWU_TABLE_2, MIWU_TABLE_COUNT };
 
 enum {
 	MIWU_GROUP_1,
@@ -281,13 +281,13 @@ enum {
 
 /******************************************************************************/
 /* GPIO registers */
-#define NPCX_PDOUT(n)                     REG8(NPCX_GPIO_BASE_ADDR(n) + 0x000)
-#define NPCX_PDIN(n)                      REG8(NPCX_GPIO_BASE_ADDR(n) + 0x001)
-#define NPCX_PDIR(n)                      REG8(NPCX_GPIO_BASE_ADDR(n) + 0x002)
-#define NPCX_PPULL(n)                     REG8(NPCX_GPIO_BASE_ADDR(n) + 0x003)
-#define NPCX_PPUD(n)                      REG8(NPCX_GPIO_BASE_ADDR(n) + 0x004)
-#define NPCX_PENVDD(n)                    REG8(NPCX_GPIO_BASE_ADDR(n) + 0x005)
-#define NPCX_PTYPE(n)                     REG8(NPCX_GPIO_BASE_ADDR(n) + 0x006)
+#define NPCX_PDOUT(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x000)
+#define NPCX_PDIN(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x001)
+#define NPCX_PDIR(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x002)
+#define NPCX_PPULL(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x003)
+#define NPCX_PPUD(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x004)
+#define NPCX_PENVDD(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x005)
+#define NPCX_PTYPE(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x006)
 
 /* GPIO enumeration */
 enum {
@@ -342,954 +342,949 @@ enum {
 
 /******************************************************************************/
 /* MSWC Registers */
-#define NPCX_MSWCTL1                      REG8(NPCX_MSWC_BASE_ADDR + 0x000)
-#define NPCX_MSWCTL2                      REG8(NPCX_MSWC_BASE_ADDR + 0x002)
-#define NPCX_HCBAL                        REG8(NPCX_MSWC_BASE_ADDR + 0x008)
-#define NPCX_HCBAH                        REG8(NPCX_MSWC_BASE_ADDR + 0x00A)
-#define NPCX_SRID_CR                      REG8(NPCX_MSWC_BASE_ADDR + 0x01C)
-#define NPCX_SID_CR                       REG8(NPCX_MSWC_BASE_ADDR + 0x020)
-#define NPCX_DEVICE_ID_CR                 REG8(NPCX_MSWC_BASE_ADDR + 0x022)
+#define NPCX_MSWCTL1 REG8(NPCX_MSWC_BASE_ADDR + 0x000)
+#define NPCX_MSWCTL2 REG8(NPCX_MSWC_BASE_ADDR + 0x002)
+#define NPCX_HCBAL REG8(NPCX_MSWC_BASE_ADDR + 0x008)
+#define NPCX_HCBAH REG8(NPCX_MSWC_BASE_ADDR + 0x00A)
+#define NPCX_SRID_CR REG8(NPCX_MSWC_BASE_ADDR + 0x01C)
+#define NPCX_SID_CR REG8(NPCX_MSWC_BASE_ADDR + 0x020)
+#define NPCX_DEVICE_ID_CR REG8(NPCX_MSWC_BASE_ADDR + 0x022)
 
 /* MSWC register fields */
-#define NPCX_MSWCTL1_HRSTOB              0
-#define NPCS_MSWCTL1_HWPRON              1
-#define NPCX_MSWCTL1_PLTRST_ACT          2
-#define NPCX_MSWCTL1_VHCFGA              3
-#define NPCX_MSWCTL1_HCFGLK              4
-#define NPCX_MSWCTL1_PWROFFB             6
-#define NPCX_MSWCTL1_A20MB               7
+#define NPCX_MSWCTL1_HRSTOB 0
+#define NPCS_MSWCTL1_HWPRON 1
+#define NPCX_MSWCTL1_PLTRST_ACT 2
+#define NPCX_MSWCTL1_VHCFGA 3
+#define NPCX_MSWCTL1_HCFGLK 4
+#define NPCX_MSWCTL1_PWROFFB 6
+#define NPCX_MSWCTL1_A20MB 7
 
 /******************************************************************************/
 /* System Configuration (SCFG) Registers */
-#define NPCX_DEVCNT                       REG8(NPCX_SCFG_BASE_ADDR + 0x000)
-#define NPCX_STRPST                       REG8(NPCX_SCFG_BASE_ADDR + 0x001)
-#define NPCX_RSTCTL                       REG8(NPCX_SCFG_BASE_ADDR + 0x002)
-#define NPCX_DEV_CTL4                     REG8(NPCX_SCFG_BASE_ADDR + 0x006)
-#define NPCX_LFCGCALCNT                   REG8(NPCX_SCFG_BASE_ADDR + 0x021)
-#define NPCX_PUPD_EN0                     REG8(NPCX_SCFG_BASE_ADDR + 0x028)
-#define NPCX_PUPD_EN1                     REG8(NPCX_SCFG_BASE_ADDR + 0x029)
-#define NPCX_SCFG_VER                     REG8(NPCX_SCFG_BASE_ADDR + 0x02F)
-
-#define TEST_BKSL                         REG8(NPCX_SCFG_BASE_ADDR + 0x037)
-#define TEST0                             REG8(NPCX_SCFG_BASE_ADDR + 0x038)
-#define BLKSEL                           0
+#define NPCX_DEVCNT REG8(NPCX_SCFG_BASE_ADDR + 0x000)
+#define NPCX_STRPST REG8(NPCX_SCFG_BASE_ADDR + 0x001)
+#define NPCX_RSTCTL REG8(NPCX_SCFG_BASE_ADDR + 0x002)
+#define NPCX_DEV_CTL4 REG8(NPCX_SCFG_BASE_ADDR + 0x006)
+#define NPCX_LFCGCALCNT REG8(NPCX_SCFG_BASE_ADDR + 0x021)
+#define NPCX_PUPD_EN0 REG8(NPCX_SCFG_BASE_ADDR + 0x028)
+#define NPCX_PUPD_EN1 REG8(NPCX_SCFG_BASE_ADDR + 0x029)
+#define NPCX_SCFG_VER REG8(NPCX_SCFG_BASE_ADDR + 0x02F)
+
+#define TEST_BKSL REG8(NPCX_SCFG_BASE_ADDR + 0x037)
+#define TEST0 REG8(NPCX_SCFG_BASE_ADDR + 0x038)
+#define BLKSEL 0
 
 /* SCFG register fields */
-#define NPCX_DEVCNT_F_SPI_TRIS           6
-#define NPCX_DEVCNT_HIF_TYP_SEL_FIELD    FIELD(2, 2)
-#define NPCX_DEVCNT_JEN1_HEN             5
-#define NPCX_DEVCNT_JEN0_HEN             4
-#define NPCX_STRPST_TRIST                1
-#define NPCX_STRPST_TEST                 2
-#define NPCX_STRPST_JEN1                 4
-#define NPCX_STRPST_JEN0                 5
-#define NPCX_STRPST_SPI_COMP             7
-#define NPCX_RSTCTL_VCC1_RST_STS         0
-#define NPCX_RSTCTL_DBGRST_STS           1
-#define NPCX_RSTCTL_VCC1_RST_SCRATCH     3
-#define NPCX_RSTCTL_LRESET_PLTRST_MODE   5
-#define NPCX_RSTCTL_HIPRST_MODE          6
-#define NPCX_DEV_CTL4_F_SPI_SLLK         2
-#define NPCX_DEV_CTL4_SPI_SP_SEL         4
-#define NPCX_DEV_CTL4_WP_IF              5
-#define NPCX_DEV_CTL4_VCC1_RST_LK        6
-#define NPCX_DEVPU0_I2C0_0_PUE           0
-#define NPCX_DEVPU0_I2C0_1_PUE           1
-#define NPCX_DEVPU0_I2C1_0_PUE           2
-#define NPCX_DEVPU0_I2C2_0_PUE           4
-#define NPCX_DEVPU0_I2C3_0_PUE           6
-#define NPCX_DEVPU1_F_SPI_PUD_EN         7
+#define NPCX_DEVCNT_F_SPI_TRIS 6
+#define NPCX_DEVCNT_HIF_TYP_SEL_FIELD FIELD(2, 2)
+#define NPCX_DEVCNT_JEN1_HEN 5
+#define NPCX_DEVCNT_JEN0_HEN 4
+#define NPCX_STRPST_TRIST 1
+#define NPCX_STRPST_TEST 2
+#define NPCX_STRPST_JEN1 4
+#define NPCX_STRPST_JEN0 5
+#define NPCX_STRPST_SPI_COMP 7
+#define NPCX_RSTCTL_VCC1_RST_STS 0
+#define NPCX_RSTCTL_DBGRST_STS 1
+#define NPCX_RSTCTL_VCC1_RST_SCRATCH 3
+#define NPCX_RSTCTL_LRESET_PLTRST_MODE 5
+#define NPCX_RSTCTL_HIPRST_MODE 6
+#define NPCX_DEV_CTL4_F_SPI_SLLK 2
+#define NPCX_DEV_CTL4_SPI_SP_SEL 4
+#define NPCX_DEV_CTL4_WP_IF 5
+#define NPCX_DEV_CTL4_VCC1_RST_LK 6
+#define NPCX_DEVPU0_I2C0_0_PUE 0
+#define NPCX_DEVPU0_I2C0_1_PUE 1
+#define NPCX_DEVPU0_I2C1_0_PUE 2
+#define NPCX_DEVPU0_I2C2_0_PUE 4
+#define NPCX_DEVPU0_I2C3_0_PUE 6
+#define NPCX_DEVPU1_F_SPI_PUD_EN 7
 
 /* DEVALT */
 /* pin-mux for SPI/FIU */
-#define NPCX_DEVALT0_SPIP_SL             0
-#define NPCX_DEVALT0_GPIO_NO_SPIP        3
-#define NPCX_DEVALT0_F_SPI_CS1_2         4
-#define NPCX_DEVALT0_F_SPI_CS1_1         5
-#define NPCX_DEVALT0_F_SPI_QUAD          6
-#define NPCX_DEVALT0_NO_F_SPI            7
+#define NPCX_DEVALT0_SPIP_SL 0
+#define NPCX_DEVALT0_GPIO_NO_SPIP 3
+#define NPCX_DEVALT0_F_SPI_CS1_2 4
+#define NPCX_DEVALT0_F_SPI_CS1_1 5
+#define NPCX_DEVALT0_F_SPI_QUAD 6
+#define NPCX_DEVALT0_NO_F_SPI 7
 
 /* pin-mux for LPC/eSPI */
-#define NPCX_DEVALT1_KBRST_SL            0
-#define NPCX_DEVALT1_A20M_SL             1
-#define NPCX_DEVALT1_SMI_SL              2
-#define NPCX_DEVALT1_EC_SCI_SL           3
-#define NPCX_DEVALT1_NO_PWRGD            4
-#define NPCX_DEVALT1_RST_OUT_SL          5
-#define NPCX_DEVALT1_CLKRN_SL            6
-#define NPCX_DEVALT1_NO_LPC_ESPI         7
+#define NPCX_DEVALT1_KBRST_SL 0
+#define NPCX_DEVALT1_A20M_SL 1
+#define NPCX_DEVALT1_SMI_SL 2
+#define NPCX_DEVALT1_EC_SCI_SL 3
+#define NPCX_DEVALT1_NO_PWRGD 4
+#define NPCX_DEVALT1_RST_OUT_SL 5
+#define NPCX_DEVALT1_CLKRN_SL 6
+#define NPCX_DEVALT1_NO_LPC_ESPI 7
 
 /* pin-mux for PS2 */
-#define NPCX_DEVALT3_PS2_0_SL            0
-#define NPCX_DEVALT3_PS2_1_SL            1
-#define NPCX_DEVALT3_PS2_2_SL            2
-#define NPCX_DEVALT3_PS2_3_SL            3
-#define NPCX_DEVALTC_PS2_3_SL2           3
+#define NPCX_DEVALT3_PS2_0_SL 0
+#define NPCX_DEVALT3_PS2_1_SL 1
+#define NPCX_DEVALT3_PS2_2_SL 2
+#define NPCX_DEVALT3_PS2_3_SL 3
+#define NPCX_DEVALTC_PS2_3_SL2 3
 
 /* pin-mux for Tacho */
-#define NPCX_DEVALT3_TA1_SL1             4
-#define NPCX_DEVALT3_TB1_SL1             5
-#define NPCX_DEVALT3_TA2_SL1             6
-#define NPCX_DEVALT3_TB2_SL1             7
-#define NPCX_DEVALTC_TA1_SL2             4
-#define NPCX_DEVALTC_TB1_SL2             5
-#define NPCX_DEVALTC_TA2_SL2             6
-#define NPCX_DEVALTC_TB2_SL2             7
+#define NPCX_DEVALT3_TA1_SL1 4
+#define NPCX_DEVALT3_TB1_SL1 5
+#define NPCX_DEVALT3_TA2_SL1 6
+#define NPCX_DEVALT3_TB2_SL1 7
+#define NPCX_DEVALTC_TA1_SL2 4
+#define NPCX_DEVALTC_TB1_SL2 5
+#define NPCX_DEVALTC_TA2_SL2 6
+#define NPCX_DEVALTC_TB2_SL2 7
 
 /* pin-mux for PWM */
-#define NPCX_DEVALT4_PWM0_SL             0
-#define NPCX_DEVALT4_PWM1_SL             1
-#define NPCX_DEVALT4_PWM2_SL             2
-#define NPCX_DEVALT4_PWM3_SL             3
-#define NPCX_DEVALT4_PWM4_SL             4
-#define NPCX_DEVALT4_PWM5_SL             5
-#define NPCX_DEVALT4_PWM6_SL             6
-#define NPCX_DEVALT4_PWM7_SL             7
+#define NPCX_DEVALT4_PWM0_SL 0
+#define NPCX_DEVALT4_PWM1_SL 1
+#define NPCX_DEVALT4_PWM2_SL 2
+#define NPCX_DEVALT4_PWM3_SL 3
+#define NPCX_DEVALT4_PWM4_SL 4
+#define NPCX_DEVALT4_PWM5_SL 5
+#define NPCX_DEVALT4_PWM6_SL 6
+#define NPCX_DEVALT4_PWM7_SL 7
 
 /* pin-mux for JTAG */
-#define NPCX_DEVALT5_TRACE_EN            0
+#define NPCX_DEVALT5_TRACE_EN 0
 
 /* pin-mux for ADC */
-#define NPCX_DEVALT6_ADC0_SL             0
-#define NPCX_DEVALT6_ADC1_SL             1
-#define NPCX_DEVALT6_ADC2_SL             2
-#define NPCX_DEVALT6_ADC3_SL             3
-#define NPCX_DEVALT6_ADC4_SL             4
+#define NPCX_DEVALT6_ADC0_SL 0
+#define NPCX_DEVALT6_ADC1_SL 1
+#define NPCX_DEVALT6_ADC2_SL 2
+#define NPCX_DEVALT6_ADC3_SL 3
+#define NPCX_DEVALT6_ADC4_SL 4
 
 /* pin-mux for Keyboard */
-#define NPCX_DEVALT7_NO_KSI0_SL          0
-#define NPCX_DEVALT7_NO_KSI1_SL          1
-#define NPCX_DEVALT7_NO_KSI2_SL          2
-#define NPCX_DEVALT7_NO_KSI3_SL          3
-#define NPCX_DEVALT7_NO_KSI4_SL          4
-#define NPCX_DEVALT7_NO_KSI5_SL          5
-#define NPCX_DEVALT7_NO_KSI6_SL          6
-#define NPCX_DEVALT7_NO_KSI7_SL          7
-#define NPCX_DEVALT8_NO_KSO00_SL         0
-#define NPCX_DEVALT8_NO_KSO01_SL         1
-#define NPCX_DEVALT8_NO_KSO02_SL         2
-#define NPCX_DEVALT8_NO_KSO03_SL         3
-#define NPCX_DEVALT8_NO_KSO04_SL         4
-#define NPCX_DEVALT8_NO_KSO05_SL         5
-#define NPCX_DEVALT8_NO_KSO06_SL         6
-#define NPCX_DEVALT8_NO_KSO07_SL         7
-#define NPCX_DEVALT9_NO_KSO08_SL         0
-#define NPCX_DEVALT9_NO_KSO09_SL         1
-#define NPCX_DEVALT9_NO_KSO10_SL         2
-#define NPCX_DEVALT9_NO_KSO11_SL         3
-#define NPCX_DEVALT9_NO_KSO12_SL         4
-#define NPCX_DEVALT9_NO_KSO13_SL         5
-#define NPCX_DEVALT9_NO_KSO14_SL         6
-#define NPCX_DEVALT9_NO_KSO15_SL         7
-#define NPCX_DEVALTA_NO_KSO16_SL         0
-#define NPCX_DEVALTA_NO_KSO17_SL         1
+#define NPCX_DEVALT7_NO_KSI0_SL 0
+#define NPCX_DEVALT7_NO_KSI1_SL 1
+#define NPCX_DEVALT7_NO_KSI2_SL 2
+#define NPCX_DEVALT7_NO_KSI3_SL 3
+#define NPCX_DEVALT7_NO_KSI4_SL 4
+#define NPCX_DEVALT7_NO_KSI5_SL 5
+#define NPCX_DEVALT7_NO_KSI6_SL 6
+#define NPCX_DEVALT7_NO_KSI7_SL 7
+#define NPCX_DEVALT8_NO_KSO00_SL 0
+#define NPCX_DEVALT8_NO_KSO01_SL 1
+#define NPCX_DEVALT8_NO_KSO02_SL 2
+#define NPCX_DEVALT8_NO_KSO03_SL 3
+#define NPCX_DEVALT8_NO_KSO04_SL 4
+#define NPCX_DEVALT8_NO_KSO05_SL 5
+#define NPCX_DEVALT8_NO_KSO06_SL 6
+#define NPCX_DEVALT8_NO_KSO07_SL 7
+#define NPCX_DEVALT9_NO_KSO08_SL 0
+#define NPCX_DEVALT9_NO_KSO09_SL 1
+#define NPCX_DEVALT9_NO_KSO10_SL 2
+#define NPCX_DEVALT9_NO_KSO11_SL 3
+#define NPCX_DEVALT9_NO_KSO12_SL 4
+#define NPCX_DEVALT9_NO_KSO13_SL 5
+#define NPCX_DEVALT9_NO_KSO14_SL 6
+#define NPCX_DEVALT9_NO_KSO15_SL 7
+#define NPCX_DEVALTA_NO_KSO16_SL 0
+#define NPCX_DEVALTA_NO_KSO17_SL 1
 
 /* pin-mux for Others */
-#define NPCX_DEVALTA_32K_OUT_SL          2
-#define NPCX_DEVALTA_NO_VCC1_RST         4
-#define NPCX_DEVALTA_NO_PECI_EN          6
-#define NPCX_DEVALTC_SHI_SL              1
+#define NPCX_DEVALTA_32K_OUT_SL 2
+#define NPCX_DEVALTA_NO_VCC1_RST 4
+#define NPCX_DEVALTA_NO_PECI_EN 6
+#define NPCX_DEVALTC_SHI_SL 1
 
 /* Others bit definitions */
-#define NPCX_LFCGCALCNT_LPREG_CTL_EN     1
+#define NPCX_LFCGCALCNT_LPREG_CTL_EN 1
 
 /******************************************************************************/
 /* Development and Debug Support (DBG) Registers */
-#define NPCX_DBGCTRL                      REG8(NPCX_SCFG_BASE_ADDR + 0x074)
-#define NPCX_DBGFRZEN1                    REG8(NPCX_SCFG_BASE_ADDR + 0x076)
-#define NPCX_DBGFRZEN2                    REG8(NPCX_SCFG_BASE_ADDR + 0x077)
-#define NPCX_DBGFRZEN3                    REG8(NPCX_SCFG_BASE_ADDR + 0x078)
+#define NPCX_DBGCTRL REG8(NPCX_SCFG_BASE_ADDR + 0x074)
+#define NPCX_DBGFRZEN1 REG8(NPCX_SCFG_BASE_ADDR + 0x076)
+#define NPCX_DBGFRZEN2 REG8(NPCX_SCFG_BASE_ADDR + 0x077)
+#define NPCX_DBGFRZEN3 REG8(NPCX_SCFG_BASE_ADDR + 0x078)
 /* DBG register fields */
-#define NPCX_DBGFRZEN3_GLBL_FRZ_DIS      7
+#define NPCX_DBGFRZEN3_GLBL_FRZ_DIS 7
 
 /******************************************************************************/
 /* SMBus Registers */
-#define NPCX_SMBSDA(n)                    REG8(NPCX_SMB_BASE_ADDR(n) + 0x000)
-#define NPCX_SMBST(n)                     REG8(NPCX_SMB_BASE_ADDR(n) + 0x002)
-#define NPCX_SMBCST(n)                    REG8(NPCX_SMB_BASE_ADDR(n) + 0x004)
-#define NPCX_SMBCTL1(n)                   REG8(NPCX_SMB_BASE_ADDR(n) + 0x006)
-#define NPCX_SMBADDR1(n)                  REG8(NPCX_SMB_BASE_ADDR(n) + 0x008)
-#define NPCX_SMBTMR_ST(n)                 REG8(NPCX_SMB_BASE_ADDR(n) + 0x009)
-#define NPCX_SMBCTL2(n)                   REG8(NPCX_SMB_BASE_ADDR(n) + 0x00A)
-#define NPCX_SMBTMR_EN(n)                 REG8(NPCX_SMB_BASE_ADDR(n) + 0x00B)
-#define NPCX_SMBADDR2(n)                  REG8(NPCX_SMB_BASE_ADDR(n) + 0x00C)
-#define NPCX_SMBCTL3(n)                   REG8(NPCX_SMB_BASE_ADDR(n) + 0x00E)
+#define NPCX_SMBSDA(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x000)
+#define NPCX_SMBST(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x002)
+#define NPCX_SMBCST(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x004)
+#define NPCX_SMBCTL1(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x006)
+#define NPCX_SMBADDR1(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x008)
+#define NPCX_SMBTMR_ST(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x009)
+#define NPCX_SMBCTL2(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x00A)
+#define NPCX_SMBTMR_EN(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x00B)
+#define NPCX_SMBADDR2(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x00C)
+#define NPCX_SMBCTL3(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x00E)
 /* SMB Registers in bank 0 */
-#define NPCX_SMBADDR3(n)                  REG8(NPCX_SMB_BASE_ADDR(n) + 0x010)
-#define NPCX_SMBADDR7(n)                  REG8(NPCX_SMB_BASE_ADDR(n) + 0x011)
-#define NPCX_SMBADDR4(n)                  REG8(NPCX_SMB_BASE_ADDR(n) + 0x012)
-#define NPCX_SMBADDR8(n)                  REG8(NPCX_SMB_BASE_ADDR(n) + 0x013)
-#define NPCX_SMBADDR5(n)                  REG8(NPCX_SMB_BASE_ADDR(n) + 0x014)
-#define NPCX_SMBADDR6(n)                  REG8(NPCX_SMB_BASE_ADDR(n) + 0x016)
-#define NPCX_SMBCST2(n)                   REG8(NPCX_SMB_BASE_ADDR(n) + 0x018)
-#define NPCX_SMBCST3(n)                   REG8(NPCX_SMB_BASE_ADDR(n) + 0x019)
-#define NPCX_SMBCTL4(n)                   REG8(NPCX_SMB_BASE_ADDR(n) + 0x01A)
-#define NPCX_SMBSCLLT(n)                  REG8(NPCX_SMB_BASE_ADDR(n) + 0x01C)
-#define NPCX_SMBFIF_CTL(n)                REG8(NPCX_SMB_BASE_ADDR(n) + 0x01D)
-#define NPCX_SMBSCLHT(n)                  REG8(NPCX_SMB_BASE_ADDR(n) + 0x01E)
+#define NPCX_SMBADDR3(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x010)
+#define NPCX_SMBADDR7(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x011)
+#define NPCX_SMBADDR4(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x012)
+#define NPCX_SMBADDR8(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x013)
+#define NPCX_SMBADDR5(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x014)
+#define NPCX_SMBADDR6(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x016)
+#define NPCX_SMBCST2(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x018)
+#define NPCX_SMBCST3(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x019)
+#define NPCX_SMBCTL4(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x01A)
+#define NPCX_SMBSCLLT(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x01C)
+#define NPCX_SMBFIF_CTL(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x01D)
+#define NPCX_SMBSCLHT(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x01E)
 /* SMB Registers in bank 1 */
-#define NPCX_SMBFIF_CTS(n)                REG8(NPCX_SMB_BASE_ADDR(n) + 0x010)
-#define NPCX_SMBTXF_CTL(n)                REG8(NPCX_SMB_BASE_ADDR(n) + 0x012)
-#define NPCX_SMB_T_OUT(n)                 REG8(NPCX_SMB_BASE_ADDR(n) + 0x014)
+#define NPCX_SMBFIF_CTS(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x010)
+#define NPCX_SMBTXF_CTL(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x012)
+#define NPCX_SMB_T_OUT(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x014)
 /*
  * These two registers are the same as in bank 0
  * #define NPCX_SMBCST2(n)                REG8(NPCX_SMB_BASE_ADDR(n) + 0x018)
  * #define NPCX_SMBCST3(n)                REG8(NPCX_SMB_BASE_ADDR(n) + 0x019)
  */
-#define NPCX_SMBTXF_STS(n)                REG8(NPCX_SMB_BASE_ADDR(n) + 0x01A)
-#define NPCX_SMBRXF_STS(n)                REG8(NPCX_SMB_BASE_ADDR(n) + 0x01C)
-#define NPCX_SMBRXF_CTL(n)                REG8(NPCX_SMB_BASE_ADDR(n) + 0x01E)
+#define NPCX_SMBTXF_STS(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x01A)
+#define NPCX_SMBRXF_STS(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x01C)
+#define NPCX_SMBRXF_CTL(n) REG8(NPCX_SMB_BASE_ADDR(n) + 0x01E)
 
 /* SMBus register fields */
-#define NPCX_SMBST_XMIT                  0
-#define NPCX_SMBST_MASTER                1
-#define NPCX_SMBST_NMATCH                2
-#define NPCX_SMBST_STASTR                3
-#define NPCX_SMBST_NEGACK                4
-#define NPCX_SMBST_BER                   5
-#define NPCX_SMBST_SDAST                 6
-#define NPCX_SMBST_SLVSTP                7
-#define NPCX_SMBCST_BUSY                 0
-#define NPCX_SMBCST_BB                   1
-#define NPCX_SMBCST_MATCH                2
-#define NPCX_SMBCST_GCMATCH              3
-#define NPCX_SMBCST_TSDA                 4
-#define NPCX_SMBCST_TGSCL                5
-#define NPCX_SMBCST_MATCHAF              6
-#define NPCX_SMBCST_ARPMATCH             7
-#define NPCX_SMBCST2_MATCHA1F            0
-#define NPCX_SMBCST2_MATCHA2F            1
-#define NPCX_SMBCST2_MATCHA3F            2
-#define NPCX_SMBCST2_MATCHA4F            3
-#define NPCX_SMBCST2_MATCHA5F            4
-#define NPCX_SMBCST2_MATCHA6F            5
-#define NPCX_SMBCST2_MATCHA7F            6
-#define NPCX_SMBCST2_INTSTS              7
-#define NPCX_SMBCST3_MATCHA8F            0
-#define NPCX_SMBCST3_MATCHA9F            1
-#define NPCX_SMBCST3_MATCHA10F           2
-#define NPCX_SMBCTL1_START               0
-#define NPCX_SMBCTL1_STOP                1
-#define NPCX_SMBCTL1_INTEN               2
-#define NPCX_SMBCTL1_ACK                 4
-#define NPCX_SMBCTL1_GCMEN               5
-#define NPCX_SMBCTL1_NMINTE              6
-#define NPCX_SMBCTL1_STASTRE             7
-#define NPCX_SMBCTL2_ENABLE              0
-#define NPCX_SMBCTL2_SCLFRQ7_FIELD       FIELD(1, 7)
-#define NPCX_SMBCTL3_ARPMEN              2
-#define NPCX_SMBCTL3_SCLFRQ2_FIELD       FIELD(0, 2)
-#define NPCX_SMBCTL3_IDL_START           3
-#define NPCX_SMBCTL3_400K                4
-#define NPCX_SMBCTL3_BNK_SEL             5
-#define NPCX_SMBCTL3_SDA_LVL             6
-#define NPCX_SMBCTL3_SCL_LVL             7
-#define NPCX_SMBCTL4_HLDT_FIELD          FIELD(0, 6)
-#define NPCX_SMBCTL4_LVL_WE              7
-#define NPCX_SMBADDR1_SAEN               7
-#define NPCX_SMBADDR2_SAEN               7
-#define NPCX_SMBADDR3_SAEN               7
-#define NPCX_SMBADDR4_SAEN               7
-#define NPCX_SMBADDR5_SAEN               7
-#define NPCX_SMBADDR6_SAEN               7
-#define NPCX_SMBADDR7_SAEN               7
-#define NPCX_SMBADDR8_SAEN               7
-#define NPCX_SMBFIF_CTS_RXF_TXE          1
-#define NPCX_SMBFIF_CTS_CLR_FIFO         6
-
-#define NPCX_SMBFIF_CTL_FIFO_EN          4
-
-#define NPCX_SMBRXF_STS_RX_THST          6
+#define NPCX_SMBST_XMIT 0
+#define NPCX_SMBST_MASTER 1
+#define NPCX_SMBST_NMATCH 2
+#define NPCX_SMBST_STASTR 3
+#define NPCX_SMBST_NEGACK 4
+#define NPCX_SMBST_BER 5
+#define NPCX_SMBST_SDAST 6
+#define NPCX_SMBST_SLVSTP 7
+#define NPCX_SMBCST_BUSY 0
+#define NPCX_SMBCST_BB 1
+#define NPCX_SMBCST_MATCH 2
+#define NPCX_SMBCST_GCMATCH 3
+#define NPCX_SMBCST_TSDA 4
+#define NPCX_SMBCST_TGSCL 5
+#define NPCX_SMBCST_MATCHAF 6
+#define NPCX_SMBCST_ARPMATCH 7
+#define NPCX_SMBCST2_MATCHA1F 0
+#define NPCX_SMBCST2_MATCHA2F 1
+#define NPCX_SMBCST2_MATCHA3F 2
+#define NPCX_SMBCST2_MATCHA4F 3
+#define NPCX_SMBCST2_MATCHA5F 4
+#define NPCX_SMBCST2_MATCHA6F 5
+#define NPCX_SMBCST2_MATCHA7F 6
+#define NPCX_SMBCST2_INTSTS 7
+#define NPCX_SMBCST3_MATCHA8F 0
+#define NPCX_SMBCST3_MATCHA9F 1
+#define NPCX_SMBCST3_MATCHA10F 2
+#define NPCX_SMBCTL1_START 0
+#define NPCX_SMBCTL1_STOP 1
+#define NPCX_SMBCTL1_INTEN 2
+#define NPCX_SMBCTL1_ACK 4
+#define NPCX_SMBCTL1_GCMEN 5
+#define NPCX_SMBCTL1_NMINTE 6
+#define NPCX_SMBCTL1_STASTRE 7
+#define NPCX_SMBCTL2_ENABLE 0
+#define NPCX_SMBCTL2_SCLFRQ7_FIELD FIELD(1, 7)
+#define NPCX_SMBCTL3_ARPMEN 2
+#define NPCX_SMBCTL3_SCLFRQ2_FIELD FIELD(0, 2)
+#define NPCX_SMBCTL3_IDL_START 3
+#define NPCX_SMBCTL3_400K 4
+#define NPCX_SMBCTL3_BNK_SEL 5
+#define NPCX_SMBCTL3_SDA_LVL 6
+#define NPCX_SMBCTL3_SCL_LVL 7
+#define NPCX_SMBCTL4_HLDT_FIELD FIELD(0, 6)
+#define NPCX_SMBCTL4_LVL_WE 7
+#define NPCX_SMBADDR1_SAEN 7
+#define NPCX_SMBADDR2_SAEN 7
+#define NPCX_SMBADDR3_SAEN 7
+#define NPCX_SMBADDR4_SAEN 7
+#define NPCX_SMBADDR5_SAEN 7
+#define NPCX_SMBADDR6_SAEN 7
+#define NPCX_SMBADDR7_SAEN 7
+#define NPCX_SMBADDR8_SAEN 7
+#define NPCX_SMBFIF_CTS_RXF_TXE 1
+#define NPCX_SMBFIF_CTS_CLR_FIFO 6
+
+#define NPCX_SMBFIF_CTL_FIFO_EN 4
+
+#define NPCX_SMBRXF_STS_RX_THST 6
 
 /* RX FIFO threshold */
-#define NPCX_SMBRXF_CTL_RX_THR           FIELD(0, 6)
+#define NPCX_SMBRXF_CTL_RX_THR FIELD(0, 6)
 /*
  * In controller receiving mode, last byte in FIFO should send ACK or NACK
  */
-#define NPCX_SMBRXF_CTL_LAST             7
+#define NPCX_SMBRXF_CTL_LAST 7
 
 /******************************************************************************/
 /* Power Management Controller (PMC) Registers */
-#define NPCX_PMCSR                     REG8(NPCX_PMC_BASE_ADDR + 0x000)
-#define NPCX_ENIDL_CTL                 REG8(NPCX_PMC_BASE_ADDR + 0x003)
-#define NPCX_DISIDL_CTL                REG8(NPCX_PMC_BASE_ADDR + 0x004)
-#define NPCX_DISIDL_CTL1               REG8(NPCX_PMC_BASE_ADDR + 0x005)
-#define NPCX_PWDWN_CTL_ADDR(offset)    (((offset) < 6) ? \
-			(NPCX_PMC_BASE_ADDR + 0x008 + (offset)) : \
-			(NPCX_PMC_BASE_ADDR + 0x024 + (offset) - 6))
-#define NPCX_PWDWN_CTL(offset)         REG8(NPCX_PWDWN_CTL_ADDR(offset))
+#define NPCX_PMCSR REG8(NPCX_PMC_BASE_ADDR + 0x000)
+#define NPCX_ENIDL_CTL REG8(NPCX_PMC_BASE_ADDR + 0x003)
+#define NPCX_DISIDL_CTL REG8(NPCX_PMC_BASE_ADDR + 0x004)
+#define NPCX_DISIDL_CTL1 REG8(NPCX_PMC_BASE_ADDR + 0x005)
+#define NPCX_PWDWN_CTL_ADDR(offset)                                 \
+	(((offset) < 6) ? (NPCX_PMC_BASE_ADDR + 0x008 + (offset)) : \
+			  (NPCX_PMC_BASE_ADDR + 0x024 + (offset)-6))
+#define NPCX_PWDWN_CTL(offset) REG8(NPCX_PWDWN_CTL_ADDR(offset))
 
 /* PMC register fields */
-#define NPCX_PMCSR_DI_INSTW              0
-#define NPCX_PMCSR_DHF                   1
-#define NPCX_PMCSR_IDLE                  2
-#define NPCX_PMCSR_NWBI                  3
-#define NPCX_PMCSR_OHFC                  6
-#define NPCX_PMCSR_OLFC                  7
-#define NPCX_DISIDL_CTL_RAM_DID          5
-#define NPCX_ENIDL_CTL_ADC_LFSL          7
-#define NPCX_ENIDL_CTL_LP_WK_CTL         6
-#define NPCX_ENIDL_CTL_PECI_ENI          2
-#define NPCX_ENIDL_CTL_ADC_ACC_DIS       1
-#define NPCX_PWDWN_CTL1_KBS_PD           0
-#define NPCX_PWDWN_CTL1_SDP_PD           1
-#define NPCX_PWDWN_CTL1_FIU_PD           2
-#define NPCX_PWDWN_CTL1_PS2_PD           3
-#define NPCX_PWDWN_CTL1_UART_PD          4
-#define NPCX_PWDWN_CTL1_MFT1_PD          5
-#define NPCX_PWDWN_CTL1_MFT2_PD          6
-#define NPCX_PWDWN_CTL1_MFT3_PD          7
-#define NPCX_PWDWN_CTL2_PWM0_PD          0
-#define NPCX_PWDWN_CTL2_PWM1_PD          1
-#define NPCX_PWDWN_CTL2_PWM2_PD          2
-#define NPCX_PWDWN_CTL2_PWM3_PD          3
-#define NPCX_PWDWN_CTL2_PWM4_PD          4
-#define NPCX_PWDWN_CTL2_PWM5_PD          5
-#define NPCX_PWDWN_CTL2_PWM6_PD          6
-#define NPCX_PWDWN_CTL2_PWM7_PD          7
-#define NPCX_PWDWN_CTL3_SMB0_PD          0
-#define NPCX_PWDWN_CTL3_SMB1_PD          1
-#define NPCX_PWDWN_CTL3_SMB2_PD          2
-#define NPCX_PWDWN_CTL3_SMB3_PD          3
-#define NPCX_PWDWN_CTL3_GMDA_PD          7
-#define NPCX_PWDWN_CTL4_ITIM1_PD         0
-#define NPCX_PWDWN_CTL4_ITIM2_PD         1
-#define NPCX_PWDWN_CTL4_ITIM3_PD         2
-#define NPCX_PWDWN_CTL4_ADC_PD           4
-#define NPCX_PWDWN_CTL4_PECI_PD          5
-#define NPCX_PWDWN_CTL4_PWM6_PD          6
-#define NPCX_PWDWN_CTL4_SPIP_PD          7
-#define NPCX_PWDWN_CTL5_SHI_PD           1
-#define NPCX_PWDWN_CTL5_MRFSH_DIS        2
-#define NPCX_PWDWN_CTL5_C2HACC_PD        3
-#define NPCX_PWDWN_CTL5_SHM_REG_PD       4
-#define NPCX_PWDWN_CTL5_SHM_PD           5
-#define NPCX_PWDWN_CTL5_DP80_PD          6
-#define NPCX_PWDWN_CTL5_MSWC_PD          7
-#define NPCX_PWDWN_CTL6_ITIM4_PD         0
-#define NPCX_PWDWN_CTL6_ITIM5_PD         1
-#define NPCX_PWDWN_CTL6_ITIM6_PD         2
-#define NPCX_PWDWN_CTL6_ESPI_PD          7
+#define NPCX_PMCSR_DI_INSTW 0
+#define NPCX_PMCSR_DHF 1
+#define NPCX_PMCSR_IDLE 2
+#define NPCX_PMCSR_NWBI 3
+#define NPCX_PMCSR_OHFC 6
+#define NPCX_PMCSR_OLFC 7
+#define NPCX_DISIDL_CTL_RAM_DID 5
+#define NPCX_ENIDL_CTL_ADC_LFSL 7
+#define NPCX_ENIDL_CTL_LP_WK_CTL 6
+#define NPCX_ENIDL_CTL_PECI_ENI 2
+#define NPCX_ENIDL_CTL_ADC_ACC_DIS 1
+#define NPCX_PWDWN_CTL1_KBS_PD 0
+#define NPCX_PWDWN_CTL1_SDP_PD 1
+#define NPCX_PWDWN_CTL1_FIU_PD 2
+#define NPCX_PWDWN_CTL1_PS2_PD 3
+#define NPCX_PWDWN_CTL1_UART_PD 4
+#define NPCX_PWDWN_CTL1_MFT1_PD 5
+#define NPCX_PWDWN_CTL1_MFT2_PD 6
+#define NPCX_PWDWN_CTL1_MFT3_PD 7
+#define NPCX_PWDWN_CTL2_PWM0_PD 0
+#define NPCX_PWDWN_CTL2_PWM1_PD 1
+#define NPCX_PWDWN_CTL2_PWM2_PD 2
+#define NPCX_PWDWN_CTL2_PWM3_PD 3
+#define NPCX_PWDWN_CTL2_PWM4_PD 4
+#define NPCX_PWDWN_CTL2_PWM5_PD 5
+#define NPCX_PWDWN_CTL2_PWM6_PD 6
+#define NPCX_PWDWN_CTL2_PWM7_PD 7
+#define NPCX_PWDWN_CTL3_SMB0_PD 0
+#define NPCX_PWDWN_CTL3_SMB1_PD 1
+#define NPCX_PWDWN_CTL3_SMB2_PD 2
+#define NPCX_PWDWN_CTL3_SMB3_PD 3
+#define NPCX_PWDWN_CTL3_GMDA_PD 7
+#define NPCX_PWDWN_CTL4_ITIM1_PD 0
+#define NPCX_PWDWN_CTL4_ITIM2_PD 1
+#define NPCX_PWDWN_CTL4_ITIM3_PD 2
+#define NPCX_PWDWN_CTL4_ADC_PD 4
+#define NPCX_PWDWN_CTL4_PECI_PD 5
+#define NPCX_PWDWN_CTL4_PWM6_PD 6
+#define NPCX_PWDWN_CTL4_SPIP_PD 7
+#define NPCX_PWDWN_CTL5_SHI_PD 1
+#define NPCX_PWDWN_CTL5_MRFSH_DIS 2
+#define NPCX_PWDWN_CTL5_C2HACC_PD 3
+#define NPCX_PWDWN_CTL5_SHM_REG_PD 4
+#define NPCX_PWDWN_CTL5_SHM_PD 5
+#define NPCX_PWDWN_CTL5_DP80_PD 6
+#define NPCX_PWDWN_CTL5_MSWC_PD 7
+#define NPCX_PWDWN_CTL6_ITIM4_PD 0
+#define NPCX_PWDWN_CTL6_ITIM5_PD 1
+#define NPCX_PWDWN_CTL6_ITIM6_PD 2
+#define NPCX_PWDWN_CTL6_ESPI_PD 7
 
 /* TODO: set PD masks based upon actual peripheral usage */
-#define CGC_KBS_MASK     BIT(NPCX_PWDWN_CTL1_KBS_PD)
-#define CGC_UART_MASK    BIT(NPCX_PWDWN_CTL1_UART_PD)
-#define CGC_FAN_MASK     (BIT(NPCX_PWDWN_CTL1_MFT1_PD) | \
-			 BIT(NPCX_PWDWN_CTL1_MFT2_PD))
-#define CGC_FIU_MASK     BIT(NPCX_PWDWN_CTL1_FIU_PD)
-#define CGC_PS2_MASK     BIT(NPCX_PWDWN_CTL1_PS2_PD)
-#define CGC_ADC_MASK     BIT(NPCX_PWDWN_CTL4_ADC_PD)
-#define CGC_PECI_MASK    BIT(NPCX_PWDWN_CTL4_PECI_PD)
-#define CGC_SPI_MASK     BIT(NPCX_PWDWN_CTL4_SPIP_PD)
-#define CGC_TIMER_MASK   (BIT(NPCX_PWDWN_CTL4_ITIM1_PD) | \
-			 BIT(NPCX_PWDWN_CTL4_ITIM2_PD) | \
-			 BIT(NPCX_PWDWN_CTL4_ITIM3_PD))
-#define CGC_LPC_MASK     (BIT(NPCX_PWDWN_CTL5_C2HACC_PD) | \
-			 BIT(NPCX_PWDWN_CTL5_SHM_REG_PD) | \
-			 BIT(NPCX_PWDWN_CTL5_SHM_PD) | \
-			 BIT(NPCX_PWDWN_CTL5_DP80_PD) | \
-			 BIT(NPCX_PWDWN_CTL5_MSWC_PD))
-#define CGC_ESPI_MASK    BIT(NPCX_PWDWN_CTL6_ESPI_PD)
+#define CGC_KBS_MASK BIT(NPCX_PWDWN_CTL1_KBS_PD)
+#define CGC_UART_MASK BIT(NPCX_PWDWN_CTL1_UART_PD)
+#define CGC_FAN_MASK \
+	(BIT(NPCX_PWDWN_CTL1_MFT1_PD) | BIT(NPCX_PWDWN_CTL1_MFT2_PD))
+#define CGC_FIU_MASK BIT(NPCX_PWDWN_CTL1_FIU_PD)
+#define CGC_PS2_MASK BIT(NPCX_PWDWN_CTL1_PS2_PD)
+#define CGC_ADC_MASK BIT(NPCX_PWDWN_CTL4_ADC_PD)
+#define CGC_PECI_MASK BIT(NPCX_PWDWN_CTL4_PECI_PD)
+#define CGC_SPI_MASK BIT(NPCX_PWDWN_CTL4_SPIP_PD)
+#define CGC_TIMER_MASK                                                   \
+	(BIT(NPCX_PWDWN_CTL4_ITIM1_PD) | BIT(NPCX_PWDWN_CTL4_ITIM2_PD) | \
+	 BIT(NPCX_PWDWN_CTL4_ITIM3_PD))
+#define CGC_LPC_MASK                                                        \
+	(BIT(NPCX_PWDWN_CTL5_C2HACC_PD) | BIT(NPCX_PWDWN_CTL5_SHM_REG_PD) | \
+	 BIT(NPCX_PWDWN_CTL5_SHM_PD) | BIT(NPCX_PWDWN_CTL5_DP80_PD) |       \
+	 BIT(NPCX_PWDWN_CTL5_MSWC_PD))
+#define CGC_ESPI_MASK BIT(NPCX_PWDWN_CTL6_ESPI_PD)
 
 /******************************************************************************/
 /* Flash Interface Unit (FIU) Registers */
-#define NPCX_FIU_CFG                      REG8(NPCX_FIU_BASE_ADDR + 0x000)
-#define NPCX_BURST_CFG                    REG8(NPCX_FIU_BASE_ADDR + 0x001)
-#define NPCX_RESP_CFG                     REG8(NPCX_FIU_BASE_ADDR + 0x002)
-#define NPCX_SPI_FL_CFG                   REG8(NPCX_FIU_BASE_ADDR + 0x014)
-#define NPCX_UMA_CODE                     REG8(NPCX_FIU_BASE_ADDR + 0x016)
-#define NPCX_UMA_AB0                      REG8(NPCX_FIU_BASE_ADDR + 0x017)
-#define NPCX_UMA_AB1                      REG8(NPCX_FIU_BASE_ADDR + 0x018)
-#define NPCX_UMA_AB2                      REG8(NPCX_FIU_BASE_ADDR + 0x019)
-#define NPCX_UMA_DB0                      REG8(NPCX_FIU_BASE_ADDR + 0x01A)
-#define NPCX_UMA_DB1                      REG8(NPCX_FIU_BASE_ADDR + 0x01B)
-#define NPCX_UMA_DB2                      REG8(NPCX_FIU_BASE_ADDR + 0x01C)
-#define NPCX_UMA_DB3                      REG8(NPCX_FIU_BASE_ADDR + 0x01D)
-#define NPCX_UMA_CTS                      REG8(NPCX_FIU_BASE_ADDR + 0x01E)
-#define NPCX_UMA_ECTS                     REG8(NPCX_FIU_BASE_ADDR + 0x01F)
-#define NPCX_UMA_DB0_3                   REG32(NPCX_FIU_BASE_ADDR + 0x020)
-#define NPCX_FIU_RD_CMD                   REG8(NPCX_FIU_BASE_ADDR + 0x030)
-#define NPCX_FIU_DMM_CYC                  REG8(NPCX_FIU_BASE_ADDR + 0x032)
-#define NPCX_FIU_EXT_CFG                  REG8(NPCX_FIU_BASE_ADDR + 0x033)
-#define NPCX_FIU_UMA_AB0_3               REG32(NPCX_FIU_BASE_ADDR + 0x034)
+#define NPCX_FIU_CFG REG8(NPCX_FIU_BASE_ADDR + 0x000)
+#define NPCX_BURST_CFG REG8(NPCX_FIU_BASE_ADDR + 0x001)
+#define NPCX_RESP_CFG REG8(NPCX_FIU_BASE_ADDR + 0x002)
+#define NPCX_SPI_FL_CFG REG8(NPCX_FIU_BASE_ADDR + 0x014)
+#define NPCX_UMA_CODE REG8(NPCX_FIU_BASE_ADDR + 0x016)
+#define NPCX_UMA_AB0 REG8(NPCX_FIU_BASE_ADDR + 0x017)
+#define NPCX_UMA_AB1 REG8(NPCX_FIU_BASE_ADDR + 0x018)
+#define NPCX_UMA_AB2 REG8(NPCX_FIU_BASE_ADDR + 0x019)
+#define NPCX_UMA_DB0 REG8(NPCX_FIU_BASE_ADDR + 0x01A)
+#define NPCX_UMA_DB1 REG8(NPCX_FIU_BASE_ADDR + 0x01B)
+#define NPCX_UMA_DB2 REG8(NPCX_FIU_BASE_ADDR + 0x01C)
+#define NPCX_UMA_DB3 REG8(NPCX_FIU_BASE_ADDR + 0x01D)
+#define NPCX_UMA_CTS REG8(NPCX_FIU_BASE_ADDR + 0x01E)
+#define NPCX_UMA_ECTS REG8(NPCX_FIU_BASE_ADDR + 0x01F)
+#define NPCX_UMA_DB0_3 REG32(NPCX_FIU_BASE_ADDR + 0x020)
+#define NPCX_FIU_RD_CMD REG8(NPCX_FIU_BASE_ADDR + 0x030)
+#define NPCX_FIU_DMM_CYC REG8(NPCX_FIU_BASE_ADDR + 0x032)
+#define NPCX_FIU_EXT_CFG REG8(NPCX_FIU_BASE_ADDR + 0x033)
+#define NPCX_FIU_UMA_AB0_3 REG32(NPCX_FIU_BASE_ADDR + 0x034)
 
 /* FIU register fields */
-#define NPCX_RESP_CFG_IAD_EN             0
-#define NPCX_RESP_CFG_DEV_SIZE_EX        2
-#define NPCX_UMA_CTS_A_SIZE              3
-#define NPCX_UMA_CTS_C_SIZE              4
-#define NPCX_UMA_CTS_RD_WR               5
-#define NPCX_UMA_CTS_DEV_NUM             6
-#define NPCX_UMA_CTS_EXEC_DONE           7
-#define NPCX_UMA_ECTS_SW_CS0             0
-#define NPCX_UMA_ECTS_SW_CS1             1
-#define NPCX_UMA_ECTS_SEC_CS             2
-#define NPCX_UMA_ECTS_UMA_LOCK           3
+#define NPCX_RESP_CFG_IAD_EN 0
+#define NPCX_RESP_CFG_DEV_SIZE_EX 2
+#define NPCX_UMA_CTS_A_SIZE 3
+#define NPCX_UMA_CTS_C_SIZE 4
+#define NPCX_UMA_CTS_RD_WR 5
+#define NPCX_UMA_CTS_DEV_NUM 6
+#define NPCX_UMA_CTS_EXEC_DONE 7
+#define NPCX_UMA_ECTS_SW_CS0 0
+#define NPCX_UMA_ECTS_SW_CS1 1
+#define NPCX_UMA_ECTS_SEC_CS 2
+#define NPCX_UMA_ECTS_UMA_LOCK 3
 
 /******************************************************************************/
 /* Shared Memory (SHM) Registers */
-#define NPCX_SMC_STS                REG8(NPCX_SHM_BASE_ADDR + 0x000)
-#define NPCX_SMC_CTL                REG8(NPCX_SHM_BASE_ADDR + 0x001)
-#define NPCX_SHM_CTL                REG8(NPCX_SHM_BASE_ADDR + 0x002)
-#define NPCX_IMA_WIN_SIZE           REG8(NPCX_SHM_BASE_ADDR + 0x005)
-#define NPCX_WIN_SIZE               REG8(NPCX_SHM_BASE_ADDR + 0x007)
-#define NPCX_SHAW_SEM(win)          REG8(NPCX_SHM_BASE_ADDR + 0x008 + (win))
-#define NPCX_IMA_SEM                REG8(NPCX_SHM_BASE_ADDR + 0x00B)
-#define NPCX_SHCFG                  REG8(NPCX_SHM_BASE_ADDR + 0x00E)
-#define NPCX_WIN_WR_PROT(win)       REG8(NPCX_SHM_BASE_ADDR + 0x010 + (win*2L))
-#define NPCX_WIN_RD_PROT(win)       REG8(NPCX_SHM_BASE_ADDR + 0x011 + (win*2L))
-#define NPCX_IMA_WR_PROT            REG8(NPCX_SHM_BASE_ADDR + 0x016)
-#define NPCX_IMA_RD_PROT            REG8(NPCX_SHM_BASE_ADDR + 0x017)
-#define NPCX_WIN_BASE(win)         REG32(NPCX_SHM_BASE_ADDR + 0x020 + (win*4L))
-
-#define NPCX_PWIN_BASEI(win)       REG16(NPCX_SHM_BASE_ADDR + 0x020 + (win*4L))
-#define NPCX_PWIN_SIZEI(win)       REG16(NPCX_SHM_BASE_ADDR + 0x022 + (win*4L))
-
-#define NPCX_IMA_BASE              REG32(NPCX_SHM_BASE_ADDR + 0x02C)
-#define NPCX_RST_CFG                REG8(NPCX_SHM_BASE_ADDR + 0x03A)
-#define NPCX_DP80BUF               REG16(NPCX_SHM_BASE_ADDR + 0x040)
-#define NPCX_DP80STS                REG8(NPCX_SHM_BASE_ADDR + 0x042)
-#define NPCX_DP80CTL                REG8(NPCX_SHM_BASE_ADDR + 0x044)
-#define NPCX_HOFS_STS               REG8(NPCX_SHM_BASE_ADDR + 0x048)
-#define NPCX_HOFS_CTL               REG8(NPCX_SHM_BASE_ADDR + 0x049)
-#define NPCX_COFS2                 REG16(NPCX_SHM_BASE_ADDR + 0x04A)
-#define NPCX_COFS1                 REG16(NPCX_SHM_BASE_ADDR + 0x04C)
-#define NPCX_IHOFS2                REG16(NPCX_SHM_BASE_ADDR + 0x050)
-#define NPCX_IHOFS1                REG16(NPCX_SHM_BASE_ADDR + 0x052)
-#define NPCX_SHM_VER                REG8(NPCX_SHM_BASE_ADDR + 0x07F)
+#define NPCX_SMC_STS REG8(NPCX_SHM_BASE_ADDR + 0x000)
+#define NPCX_SMC_CTL REG8(NPCX_SHM_BASE_ADDR + 0x001)
+#define NPCX_SHM_CTL REG8(NPCX_SHM_BASE_ADDR + 0x002)
+#define NPCX_IMA_WIN_SIZE REG8(NPCX_SHM_BASE_ADDR + 0x005)
+#define NPCX_WIN_SIZE REG8(NPCX_SHM_BASE_ADDR + 0x007)
+#define NPCX_SHAW_SEM(win) REG8(NPCX_SHM_BASE_ADDR + 0x008 + (win))
+#define NPCX_IMA_SEM REG8(NPCX_SHM_BASE_ADDR + 0x00B)
+#define NPCX_SHCFG REG8(NPCX_SHM_BASE_ADDR + 0x00E)
+#define NPCX_WIN_WR_PROT(win) REG8(NPCX_SHM_BASE_ADDR + 0x010 + (win * 2L))
+#define NPCX_WIN_RD_PROT(win) REG8(NPCX_SHM_BASE_ADDR + 0x011 + (win * 2L))
+#define NPCX_IMA_WR_PROT REG8(NPCX_SHM_BASE_ADDR + 0x016)
+#define NPCX_IMA_RD_PROT REG8(NPCX_SHM_BASE_ADDR + 0x017)
+#define NPCX_WIN_BASE(win) REG32(NPCX_SHM_BASE_ADDR + 0x020 + (win * 4L))
+
+#define NPCX_PWIN_BASEI(win) REG16(NPCX_SHM_BASE_ADDR + 0x020 + (win * 4L))
+#define NPCX_PWIN_SIZEI(win) REG16(NPCX_SHM_BASE_ADDR + 0x022 + (win * 4L))
+
+#define NPCX_IMA_BASE REG32(NPCX_SHM_BASE_ADDR + 0x02C)
+#define NPCX_RST_CFG REG8(NPCX_SHM_BASE_ADDR + 0x03A)
+#define NPCX_DP80BUF REG16(NPCX_SHM_BASE_ADDR + 0x040)
+#define NPCX_DP80STS REG8(NPCX_SHM_BASE_ADDR + 0x042)
+#define NPCX_DP80CTL REG8(NPCX_SHM_BASE_ADDR + 0x044)
+#define NPCX_HOFS_STS REG8(NPCX_SHM_BASE_ADDR + 0x048)
+#define NPCX_HOFS_CTL REG8(NPCX_SHM_BASE_ADDR + 0x049)
+#define NPCX_COFS2 REG16(NPCX_SHM_BASE_ADDR + 0x04A)
+#define NPCX_COFS1 REG16(NPCX_SHM_BASE_ADDR + 0x04C)
+#define NPCX_IHOFS2 REG16(NPCX_SHM_BASE_ADDR + 0x050)
+#define NPCX_IHOFS1 REG16(NPCX_SHM_BASE_ADDR + 0x052)
+#define NPCX_SHM_VER REG8(NPCX_SHM_BASE_ADDR + 0x07F)
 
 /* SHM register fields */
-#define NPCX_SMC_STS_HRERR               0
-#define NPCX_SMC_STS_HWERR               1
-#define NPCX_SMC_STS_HSEM1W              4
-#define NPCX_SMC_STS_HSEM2W              5
-#define NPCX_SMC_STS_SHM_ACC             6
-#define NPCX_SMC_CTL_HERR_IE             2
-#define NPCX_SMC_CTL_HSEM1_IE            3
-#define NPCX_SMC_CTL_HSEM2_IE            4
-#define NPCX_SMC_CTL_ACC_IE              5
-#define NPCX_SMC_CTL_PREF_EN             6
-#define NPCX_SMC_CTL_HOSTWAIT            7
-#define NPCX_FLASH_SIZE_STALL_HOST       6
-#define NPCX_FLASH_SIZE_RD_BURST         7
-#define NPCX_WIN_PROT_RW1L_RP            0
-#define NPCX_WIN_PROT_RW1L_WP            1
-#define NPCX_WIN_PROT_RW1H_RP            2
-#define NPCX_WIN_PROT_RW1H_WP            3
-#define NPCX_WIN_PROT_RW2L_RP            4
-#define NPCX_WIN_PROT_RW2L_WP            5
-#define NPCX_WIN_PROT_RW2H_RP            6
-#define NPCX_WIN_PROT_RW2H_WP            7
-#define NPCX_PWIN_SIZEI_RPROT            13
-#define NPCX_PWIN_SIZEI_WPROT            14
-#define NPCX_CSEM2                       6
-#define NPCX_CSEM3                       7
-#define NPCX_DP80BUF_OFFS_FIELD          FIELD(8, 3)
-#define NPCX_DP80STS_FWR                 5
-#define NPCX_DP80STS_FNE                 6
-#define NPCX_DP80STS_FOR                 7
-#define NPCX_DP80CTL_DP80EN              0
-#define NPCX_DP80CTL_SYNCEN              1
-#define NPCX_DP80CTL_RFIFO               4
-#define NPCX_DP80CTL_CIEN                5
+#define NPCX_SMC_STS_HRERR 0
+#define NPCX_SMC_STS_HWERR 1
+#define NPCX_SMC_STS_HSEM1W 4
+#define NPCX_SMC_STS_HSEM2W 5
+#define NPCX_SMC_STS_SHM_ACC 6
+#define NPCX_SMC_CTL_HERR_IE 2
+#define NPCX_SMC_CTL_HSEM1_IE 3
+#define NPCX_SMC_CTL_HSEM2_IE 4
+#define NPCX_SMC_CTL_ACC_IE 5
+#define NPCX_SMC_CTL_PREF_EN 6
+#define NPCX_SMC_CTL_HOSTWAIT 7
+#define NPCX_FLASH_SIZE_STALL_HOST 6
+#define NPCX_FLASH_SIZE_RD_BURST 7
+#define NPCX_WIN_PROT_RW1L_RP 0
+#define NPCX_WIN_PROT_RW1L_WP 1
+#define NPCX_WIN_PROT_RW1H_RP 2
+#define NPCX_WIN_PROT_RW1H_WP 3
+#define NPCX_WIN_PROT_RW2L_RP 4
+#define NPCX_WIN_PROT_RW2L_WP 5
+#define NPCX_WIN_PROT_RW2H_RP 6
+#define NPCX_WIN_PROT_RW2H_WP 7
+#define NPCX_PWIN_SIZEI_RPROT 13
+#define NPCX_PWIN_SIZEI_WPROT 14
+#define NPCX_CSEM2 6
+#define NPCX_CSEM3 7
+#define NPCX_DP80BUF_OFFS_FIELD FIELD(8, 3)
+#define NPCX_DP80STS_FWR 5
+#define NPCX_DP80STS_FNE 6
+#define NPCX_DP80STS_FOR 7
+#define NPCX_DP80CTL_DP80EN 0
+#define NPCX_DP80CTL_SYNCEN 1
+#define NPCX_DP80CTL_RFIFO 4
+#define NPCX_DP80CTL_CIEN 5
 
 /******************************************************************************/
 /* KBC Registers */
-#define NPCX_HICTRL                       REG8(NPCX_KBC_BASE_ADDR + 0x000)
-#define NPCX_HIIRQC                       REG8(NPCX_KBC_BASE_ADDR + 0x002)
-#define NPCX_HIKMST                       REG8(NPCX_KBC_BASE_ADDR + 0x004)
-#define NPCX_HIKDO                        REG8(NPCX_KBC_BASE_ADDR + 0x006)
-#define NPCX_HIMDO                        REG8(NPCX_KBC_BASE_ADDR + 0x008)
-#define NPCX_KBCVER                       REG8(NPCX_KBC_BASE_ADDR + 0x009)
-#define NPCX_HIKMDI                       REG8(NPCX_KBC_BASE_ADDR + 0x00A)
-#define NPCX_SHIKMDI                      REG8(NPCX_KBC_BASE_ADDR + 0x00B)
+#define NPCX_HICTRL REG8(NPCX_KBC_BASE_ADDR + 0x000)
+#define NPCX_HIIRQC REG8(NPCX_KBC_BASE_ADDR + 0x002)
+#define NPCX_HIKMST REG8(NPCX_KBC_BASE_ADDR + 0x004)
+#define NPCX_HIKDO REG8(NPCX_KBC_BASE_ADDR + 0x006)
+#define NPCX_HIMDO REG8(NPCX_KBC_BASE_ADDR + 0x008)
+#define NPCX_KBCVER REG8(NPCX_KBC_BASE_ADDR + 0x009)
+#define NPCX_HIKMDI REG8(NPCX_KBC_BASE_ADDR + 0x00A)
+#define NPCX_SHIKMDI REG8(NPCX_KBC_BASE_ADDR + 0x00B)
 
 /* KBC register field */
-#define NPCX_HICTRL_OBFKIE               0 /* Automatic Serial IRQ1 for KBC */
-#define NPCX_HICTRL_OBFMIE               1 /* Automatic Serial IRQ12 for Mouse*/
-#define NPCX_HICTRL_OBECIE               2 /* KBC OBE interrupt enable */
-#define NPCX_HICTRL_IBFCIE               3 /* KBC IBF interrupt enable */
-#define NPCX_HICTRL_PMIHIE               4 /* Automatic Serial IRQ11 for PMC1 */
-#define NPCX_HICTRL_PMIOCIE              5 /* PMC1 OBE interrupt enable */
-#define NPCX_HICTRL_PMICIE               6 /* PMC1 IBF interrupt enable */
-#define NPCX_HICTRL_FW_OBF               7 /* Firmware control over OBF */
-
-#define NPCX_HIKMST_OBF                  0 /* KB output buffer is full */
+#define NPCX_HICTRL_OBFKIE 0 /* Automatic Serial IRQ1 for KBC */
+#define NPCX_HICTRL_OBFMIE 1 /* Automatic Serial IRQ12 for Mouse*/
+#define NPCX_HICTRL_OBECIE 2 /* KBC OBE interrupt enable */
+#define NPCX_HICTRL_IBFCIE 3 /* KBC IBF interrupt enable */
+#define NPCX_HICTRL_PMIHIE 4 /* Automatic Serial IRQ11 for PMC1 */
+#define NPCX_HICTRL_PMIOCIE 5 /* PMC1 OBE interrupt enable */
+#define NPCX_HICTRL_PMICIE 6 /* PMC1 IBF interrupt enable */
+#define NPCX_HICTRL_FW_OBF 7 /* Firmware control over OBF */
+
+#define NPCX_HIKMST_OBF 0 /* KB output buffer is full */
 /******************************************************************************/
 /* PM Channel Registers */
-#define NPCX_HIPMST(n)                    REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x000)
-#define NPCX_HIPMDO(n)                    REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x002)
-#define NPCX_HIPMDI(n)                    REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x004)
-#define NPCX_SHIPMDI(n)                   REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x005)
-#define NPCX_HIPMDOC(n)                   REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x006)
-#define NPCX_HIPMDOM(n)                   REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x008)
-#define NPCX_HIPMDIC(n)                   REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x00A)
-#define NPCX_HIPMCTL(n)                   REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x00C)
-#define NPCX_HIPMCTL2(n)                  REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x00D)
-#define NPCX_HIPMIC(n)                    REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x00E)
-#define NPCX_HIPMIE(n)                    REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x010)
+#define NPCX_HIPMST(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x000)
+#define NPCX_HIPMDO(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x002)
+#define NPCX_HIPMDI(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x004)
+#define NPCX_SHIPMDI(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x005)
+#define NPCX_HIPMDOC(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x006)
+#define NPCX_HIPMDOM(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x008)
+#define NPCX_HIPMDIC(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x00A)
+#define NPCX_HIPMCTL(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x00C)
+#define NPCX_HIPMCTL2(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x00D)
+#define NPCX_HIPMIC(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x00E)
+#define NPCX_HIPMIE(n) REG8(NPCX_PM_CH_BASE_ADDR(n) + 0x010)
 
 /* PM Channel register field */
 
 /* NPCX_HIPMIE */
-#define NPCX_HIPMIE_SCIE                 1
-#define NPCX_HIPMIE_SMIE                 2
+#define NPCX_HIPMIE_SCIE 1
+#define NPCX_HIPMIE_SMIE 2
 
 /* NPCX_HIPMCTL */
-#define NPCX_HIPMCTL_IBFIE               0
-#define NPCX_HIPMCTL_SCIPOL              6
+#define NPCX_HIPMCTL_IBFIE 0
+#define NPCX_HIPMCTL_SCIPOL 6
 
 /* NPCX_HIPMST */
-#define NPCX_HIPMST_F0                   2 /* EC_LPC_CMDR_BUSY */
-#define NPCX_HIPMST_ST0                  4 /* EC_LPC_CMDR_ACPI_BRST */
-#define NPCX_HIPMST_ST1                  5 /* EC_LPC_CMDR_SCI */
-#define NPCX_HIPMST_ST2                  6 /* EC_LPC_CMDR_SMI */
+#define NPCX_HIPMST_F0 2 /* EC_LPC_CMDR_BUSY */
+#define NPCX_HIPMST_ST0 4 /* EC_LPC_CMDR_ACPI_BRST */
+#define NPCX_HIPMST_ST1 5 /* EC_LPC_CMDR_SCI */
+#define NPCX_HIPMST_ST2 6 /* EC_LPC_CMDR_SMI */
 
 /* NPCX_HIPMIC */
-#define NPCX_HIPMIC_SMIB                 1
-#define NPCX_HIPMIC_SCIB                 2
-#define NPCX_HIPMIC_SMIPOL               6
+#define NPCX_HIPMIC_SMIB 1
+#define NPCX_HIPMIC_SCIB 2
+#define NPCX_HIPMIC_SMIPOL 6
 
 /*
  * PM Channel enumeration
  */
-enum PM_CHANNEL_T {
-	PM_CHAN_1,
-	PM_CHAN_2,
-	PM_CHAN_3,
-	PM_CHAN_4
-};
+enum PM_CHANNEL_T { PM_CHAN_1, PM_CHAN_2, PM_CHAN_3, PM_CHAN_4 };
 
 /******************************************************************************/
 /* SuperI/O Internal Bus (SIB) Registers */
-#define NPCX_IHIOA                       REG16(NPCX_SIB_BASE_ADDR + 0x000)
-#define NPCX_IHD                          REG8(NPCX_SIB_BASE_ADDR + 0x002)
-#define NPCX_LKSIOHA                     REG16(NPCX_SIB_BASE_ADDR + 0x004)
-#define NPCX_SIOLV                       REG16(NPCX_SIB_BASE_ADDR + 0x006)
-#define NPCX_CRSMAE                      REG16(NPCX_SIB_BASE_ADDR + 0x008)
-#define NPCX_SIBCTRL                      REG8(NPCX_SIB_BASE_ADDR + 0x00A)
-#define NPCX_C2H_VER                      REG8(NPCX_SIB_BASE_ADDR + 0x00E)
+#define NPCX_IHIOA REG16(NPCX_SIB_BASE_ADDR + 0x000)
+#define NPCX_IHD REG8(NPCX_SIB_BASE_ADDR + 0x002)
+#define NPCX_LKSIOHA REG16(NPCX_SIB_BASE_ADDR + 0x004)
+#define NPCX_SIOLV REG16(NPCX_SIB_BASE_ADDR + 0x006)
+#define NPCX_CRSMAE REG16(NPCX_SIB_BASE_ADDR + 0x008)
+#define NPCX_SIBCTRL REG8(NPCX_SIB_BASE_ADDR + 0x00A)
+#define NPCX_C2H_VER REG8(NPCX_SIB_BASE_ADDR + 0x00E)
 /* SIB register fields  */
-#define NPCX_SIBCTRL_CSAE                0
-#define NPCX_SIBCTRL_CSRD                1
-#define NPCX_SIBCTRL_CSWR                2
-#define NPCX_LKSIOHA_LKCFG               0
-#define NPCX_LKSIOHA_LKHIKBD            11
-#define NPCX_CRSMAE_CFGAE                0
-#define NPCX_CRSMAE_HIKBDAE             11
+#define NPCX_SIBCTRL_CSAE 0
+#define NPCX_SIBCTRL_CSRD 1
+#define NPCX_SIBCTRL_CSWR 2
+#define NPCX_LKSIOHA_LKCFG 0
+#define NPCX_LKSIOHA_LKHIKBD 11
+#define NPCX_CRSMAE_CFGAE 0
+#define NPCX_CRSMAE_HIKBDAE 11
 
 /******************************************************************************/
 /* Battery-Backed RAM (BBRAM) Registers */
-#define NPCX_BKUP_STS                REG8(NPCX_BBRAM_BASE_ADDR + 0x100)
-#define NPCX_BBRAM(offset)           REG8(NPCX_BBRAM_BASE_ADDR + offset)
+#define NPCX_BKUP_STS REG8(NPCX_BBRAM_BASE_ADDR + 0x100)
+#define NPCX_BBRAM(offset) REG8(NPCX_BBRAM_BASE_ADDR + offset)
 
 /* BBRAM register fields */
-#define NPCX_BKUP_STS_IBBR               7
+#define NPCX_BKUP_STS_IBBR 7
 
 /******************************************************************************/
 /* Timer Watch Dog (TWD) Registers */
-#define NPCX_TWCFG                        REG8(NPCX_TWD_BASE_ADDR + 0x000)
-#define NPCX_TWCP                         REG8(NPCX_TWD_BASE_ADDR + 0x002)
-#define NPCX_TWDT0                       REG16(NPCX_TWD_BASE_ADDR + 0x004)
-#define NPCX_T0CSR                        REG8(NPCX_TWD_BASE_ADDR + 0x006)
-#define NPCX_WDCNT                        REG8(NPCX_TWD_BASE_ADDR + 0x008)
-#define NPCX_WDSDM                        REG8(NPCX_TWD_BASE_ADDR + 0x00A)
-#define NPCX_TWMT0                       REG16(NPCX_TWD_BASE_ADDR + 0x00C)
-#define NPCX_TWMWD                        REG8(NPCX_TWD_BASE_ADDR + 0x00E)
-#define NPCX_WDCP                         REG8(NPCX_TWD_BASE_ADDR + 0x010)
+#define NPCX_TWCFG REG8(NPCX_TWD_BASE_ADDR + 0x000)
+#define NPCX_TWCP REG8(NPCX_TWD_BASE_ADDR + 0x002)
+#define NPCX_TWDT0 REG16(NPCX_TWD_BASE_ADDR + 0x004)
+#define NPCX_T0CSR REG8(NPCX_TWD_BASE_ADDR + 0x006)
+#define NPCX_WDCNT REG8(NPCX_TWD_BASE_ADDR + 0x008)
+#define NPCX_WDSDM REG8(NPCX_TWD_BASE_ADDR + 0x00A)
+#define NPCX_TWMT0 REG16(NPCX_TWD_BASE_ADDR + 0x00C)
+#define NPCX_TWMWD REG8(NPCX_TWD_BASE_ADDR + 0x00E)
+#define NPCX_WDCP REG8(NPCX_TWD_BASE_ADDR + 0x010)
 
 /* TWD register fields */
-#define NPCX_TWCFG_LTWCFG                0
-#define NPCX_TWCFG_LTWCP                 1
-#define NPCX_TWCFG_LTWDT0                2
-#define NPCX_TWCFG_LWDCNT                3
-#define NPCX_TWCFG_WDCT0I                4
-#define NPCX_TWCFG_WDSDME                5
-#define NPCX_TWCFG_WDRST_MODE            6
-#define NPCX_TWCFG_WDC2POR               7
-#define NPCX_T0CSR_RST                   0
-#define NPCX_T0CSR_TC                    1
-#define NPCX_T0CSR_WDLTD                 3
-#define NPCX_T0CSR_WDRST_STS             4
-#define NPCX_T0CSR_WD_RUN                5
-#define NPCX_T0CSR_TESDIS                7
+#define NPCX_TWCFG_LTWCFG 0
+#define NPCX_TWCFG_LTWCP 1
+#define NPCX_TWCFG_LTWDT0 2
+#define NPCX_TWCFG_LWDCNT 3
+#define NPCX_TWCFG_WDCT0I 4
+#define NPCX_TWCFG_WDSDME 5
+#define NPCX_TWCFG_WDRST_MODE 6
+#define NPCX_TWCFG_WDC2POR 7
+#define NPCX_T0CSR_RST 0
+#define NPCX_T0CSR_TC 1
+#define NPCX_T0CSR_WDLTD 3
+#define NPCX_T0CSR_WDRST_STS 4
+#define NPCX_T0CSR_WD_RUN 5
+#define NPCX_T0CSR_TESDIS 7
 
 /******************************************************************************/
 /* SPI Register */
-#define NPCX_SPI_DATA                    REG16(NPCX_SPI_BASE_ADDR + 0x00)
-#define NPCX_SPI_CTL1                    REG16(NPCX_SPI_BASE_ADDR + 0x02)
-#define NPCX_SPI_STAT                     REG8(NPCX_SPI_BASE_ADDR + 0x04)
+#define NPCX_SPI_DATA REG16(NPCX_SPI_BASE_ADDR + 0x00)
+#define NPCX_SPI_CTL1 REG16(NPCX_SPI_BASE_ADDR + 0x02)
+#define NPCX_SPI_STAT REG8(NPCX_SPI_BASE_ADDR + 0x04)
 
 /* SPI register fields */
-#define NPCX_SPI_CTL1_SPIEN              0
-#define NPCX_SPI_CTL1_SNM                1
-#define NPCX_SPI_CTL1_MOD                2
-#define NPCX_SPI_CTL1_EIR                5
-#define NPCX_SPI_CTL1_EIW                6
-#define NPCX_SPI_CTL1_SCM                7
-#define NPCX_SPI_CTL1_SCIDL              8
-#define NPCX_SPI_CTL1_SCDV               9
-#define NPCX_SPI_STAT_BSY                0
-#define NPCX_SPI_STAT_RBF                1
+#define NPCX_SPI_CTL1_SPIEN 0
+#define NPCX_SPI_CTL1_SNM 1
+#define NPCX_SPI_CTL1_MOD 2
+#define NPCX_SPI_CTL1_EIR 5
+#define NPCX_SPI_CTL1_EIW 6
+#define NPCX_SPI_CTL1_SCM 7
+#define NPCX_SPI_CTL1_SCIDL 8
+#define NPCX_SPI_CTL1_SCDV 9
+#define NPCX_SPI_STAT_BSY 0
+#define NPCX_SPI_STAT_RBF 1
 
 /******************************************************************************/
 /* PECI Registers */
 
-#define NPCX_PECI_CTL_STS                REG8(NPCX_PECI_BASE_ADDR + 0x000)
-#define NPCX_PECI_RD_LENGTH              REG8(NPCX_PECI_BASE_ADDR + 0x001)
-#define NPCX_PECI_ADDR                   REG8(NPCX_PECI_BASE_ADDR + 0x002)
-#define NPCX_PECI_CMD                    REG8(NPCX_PECI_BASE_ADDR + 0x003)
-#define NPCX_PECI_CTL2                   REG8(NPCX_PECI_BASE_ADDR + 0x004)
-#define NPCX_PECI_INDEX                  REG8(NPCX_PECI_BASE_ADDR + 0x005)
-#define NPCX_PECI_IDATA                  REG8(NPCX_PECI_BASE_ADDR + 0x006)
-#define NPCX_PECI_WR_LENGTH              REG8(NPCX_PECI_BASE_ADDR + 0x007)
-#define NPCX_PECI_CFG                    REG8(NPCX_PECI_BASE_ADDR + 0x009)
-#define NPCX_PECI_RATE                   REG8(NPCX_PECI_BASE_ADDR + 0x00F)
-#define NPCX_PECI_DATA_IN(i)             REG8(NPCX_PECI_BASE_ADDR + 0x010 + (i))
-#define NPCX_PECI_DATA_OUT(i)            REG8(NPCX_PECI_BASE_ADDR + 0x010 + (i))
+#define NPCX_PECI_CTL_STS REG8(NPCX_PECI_BASE_ADDR + 0x000)
+#define NPCX_PECI_RD_LENGTH REG8(NPCX_PECI_BASE_ADDR + 0x001)
+#define NPCX_PECI_ADDR REG8(NPCX_PECI_BASE_ADDR + 0x002)
+#define NPCX_PECI_CMD REG8(NPCX_PECI_BASE_ADDR + 0x003)
+#define NPCX_PECI_CTL2 REG8(NPCX_PECI_BASE_ADDR + 0x004)
+#define NPCX_PECI_INDEX REG8(NPCX_PECI_BASE_ADDR + 0x005)
+#define NPCX_PECI_IDATA REG8(NPCX_PECI_BASE_ADDR + 0x006)
+#define NPCX_PECI_WR_LENGTH REG8(NPCX_PECI_BASE_ADDR + 0x007)
+#define NPCX_PECI_CFG REG8(NPCX_PECI_BASE_ADDR + 0x009)
+#define NPCX_PECI_RATE REG8(NPCX_PECI_BASE_ADDR + 0x00F)
+#define NPCX_PECI_DATA_IN(i) REG8(NPCX_PECI_BASE_ADDR + 0x010 + (i))
+#define NPCX_PECI_DATA_OUT(i) REG8(NPCX_PECI_BASE_ADDR + 0x010 + (i))
 
 /* PECI register fields */
-#define NPCX_PECI_CTL_STS_START_BUSY     0
-#define NPCX_PECI_CTL_STS_DONE           1
-#define NPCX_PECI_CTL_STS_AVL_ERR        2
-#define NPCX_PECI_CTL_STS_CRC_ERR        3
-#define NPCX_PECI_CTL_STS_ABRT_ERR       4
-#define NPCX_PECI_CTL_STS_AWFCS_EN       5
-#define NPCX_PECI_CTL_STS_DONE_EN        6
-#define NPCX_ESTRPST_PECIST              0
-#define SFT_STRP_CFG_CK50                5
+#define NPCX_PECI_CTL_STS_START_BUSY 0
+#define NPCX_PECI_CTL_STS_DONE 1
+#define NPCX_PECI_CTL_STS_AVL_ERR 2
+#define NPCX_PECI_CTL_STS_CRC_ERR 3
+#define NPCX_PECI_CTL_STS_ABRT_ERR 4
+#define NPCX_PECI_CTL_STS_AWFCS_EN 5
+#define NPCX_PECI_CTL_STS_DONE_EN 6
+#define NPCX_ESTRPST_PECIST 0
+#define SFT_STRP_CFG_CK50 5
 
 /******************************************************************************/
 /* PWM Registers */
-#define NPCX_PRSC(n)                     REG16(NPCX_PWM_BASE_ADDR(n) + 0x000)
-#define NPCX_CTR(n)                      REG16(NPCX_PWM_BASE_ADDR(n) + 0x002)
-#define NPCX_PWMCTL(n)                    REG8(NPCX_PWM_BASE_ADDR(n) + 0x004)
-#define NPCX_DCR(n)                      REG16(NPCX_PWM_BASE_ADDR(n) + 0x006)
-#define NPCX_PWMCTLEX(n)                  REG8(NPCX_PWM_BASE_ADDR(n) + 0x00C)
+#define NPCX_PRSC(n) REG16(NPCX_PWM_BASE_ADDR(n) + 0x000)
+#define NPCX_CTR(n) REG16(NPCX_PWM_BASE_ADDR(n) + 0x002)
+#define NPCX_PWMCTL(n) REG8(NPCX_PWM_BASE_ADDR(n) + 0x004)
+#define NPCX_DCR(n) REG16(NPCX_PWM_BASE_ADDR(n) + 0x006)
+#define NPCX_PWMCTLEX(n) REG8(NPCX_PWM_BASE_ADDR(n) + 0x00C)
 
 /* PWM register fields */
-#define NPCX_PWMCTL_INVP                 0
-#define NPCX_PWMCTL_CKSEL                1
-#define NPCX_PWMCTL_HB_DC_CTL_FIELD      FIELD(2, 2)
-#define NPCX_PWMCTL_PWR                  7
-#define NPCX_PWMCTLEX_FCK_SEL_FIELD      FIELD(4, 2)
-#define NPCX_PWMCTLEX_OD_OUT             7
+#define NPCX_PWMCTL_INVP 0
+#define NPCX_PWMCTL_CKSEL 1
+#define NPCX_PWMCTL_HB_DC_CTL_FIELD FIELD(2, 2)
+#define NPCX_PWMCTL_PWR 7
+#define NPCX_PWMCTLEX_FCK_SEL_FIELD FIELD(4, 2)
+#define NPCX_PWMCTLEX_OD_OUT 7
 /******************************************************************************/
 /* MFT Registers */
-#define NPCX_TCNT1(n)                    REG16(NPCX_MFT_BASE_ADDR(n) + 0x000)
-#define NPCX_TCRA(n)                     REG16(NPCX_MFT_BASE_ADDR(n) + 0x002)
-#define NPCX_TCRB(n)                     REG16(NPCX_MFT_BASE_ADDR(n) + 0x004)
-#define NPCX_TCNT2(n)                    REG16(NPCX_MFT_BASE_ADDR(n) + 0x006)
-#define NPCX_TPRSC(n)                     REG8(NPCX_MFT_BASE_ADDR(n) + 0x008)
-#define NPCX_TCKC(n)                      REG8(NPCX_MFT_BASE_ADDR(n) + 0x00A)
-#define NPCX_TMCTRL(n)                    REG8(NPCX_MFT_BASE_ADDR(n) + 0x00C)
-#define NPCX_TECTRL(n)                    REG8(NPCX_MFT_BASE_ADDR(n) + 0x00E)
-#define NPCX_TECLR(n)                     REG8(NPCX_MFT_BASE_ADDR(n) + 0x010)
-#define NPCX_TIEN(n)                      REG8(NPCX_MFT_BASE_ADDR(n) + 0x012)
-#define NPCX_TWUEN(n)                     REG8(NPCX_MFT_BASE_ADDR(n) + 0x01A)
-#define NPCX_TCFG(n)                      REG8(NPCX_MFT_BASE_ADDR(n) + 0x01C)
+#define NPCX_TCNT1(n) REG16(NPCX_MFT_BASE_ADDR(n) + 0x000)
+#define NPCX_TCRA(n) REG16(NPCX_MFT_BASE_ADDR(n) + 0x002)
+#define NPCX_TCRB(n) REG16(NPCX_MFT_BASE_ADDR(n) + 0x004)
+#define NPCX_TCNT2(n) REG16(NPCX_MFT_BASE_ADDR(n) + 0x006)
+#define NPCX_TPRSC(n) REG8(NPCX_MFT_BASE_ADDR(n) + 0x008)
+#define NPCX_TCKC(n) REG8(NPCX_MFT_BASE_ADDR(n) + 0x00A)
+#define NPCX_TMCTRL(n) REG8(NPCX_MFT_BASE_ADDR(n) + 0x00C)
+#define NPCX_TECTRL(n) REG8(NPCX_MFT_BASE_ADDR(n) + 0x00E)
+#define NPCX_TECLR(n) REG8(NPCX_MFT_BASE_ADDR(n) + 0x010)
+#define NPCX_TIEN(n) REG8(NPCX_MFT_BASE_ADDR(n) + 0x012)
+#define NPCX_TWUEN(n) REG8(NPCX_MFT_BASE_ADDR(n) + 0x01A)
+#define NPCX_TCFG(n) REG8(NPCX_MFT_BASE_ADDR(n) + 0x01C)
 
 /* MFT register fields */
-#define NPCX_TMCTRL_MDSEL_FIELD          FIELD(0, 3)
-#define NPCX_TCKC_LOW_PWR                7
-#define NPCX_TCKC_PLS_ACC_CLK            6
-#define NPCX_TCKC_C1CSEL_FIELD           FIELD(0, 3)
-#define NPCX_TCKC_C2CSEL_FIELD           FIELD(3, 3)
-#define NPCX_TMCTRL_TAEN                 5
-#define NPCX_TMCTRL_TBEN                 6
-#define NPCX_TMCTRL_TAEDG                3
-#define NPCX_TMCTRL_TBEDG                4
-#define NPCX_TCFG_TADBEN                 6
-#define NPCX_TCFG_TBDBEN                 7
-#define NPCX_TECTRL_TAPND                0
-#define NPCX_TECTRL_TBPND                1
-#define NPCX_TECTRL_TCPND                2
-#define NPCX_TECTRL_TDPND                3
-#define NPCX_TECLR_TACLR                 0
-#define NPCX_TECLR_TBCLR                 1
-#define NPCX_TECLR_TCCLR                 2
-#define NPCX_TECLR_TDCLR                 3
-#define NPCX_TIEN_TAIEN                  0
-#define NPCX_TIEN_TBIEN                  1
-#define NPCX_TIEN_TCIEN                  2
-#define NPCX_TIEN_TDIEN                  3
-#define NPCX_TWUEN_TAWEN                 0
-#define NPCX_TWUEN_TBWEN                 1
-#define NPCX_TWUEN_TCWEN                 2
-#define NPCX_TWUEN_TDWEN                 3
+#define NPCX_TMCTRL_MDSEL_FIELD FIELD(0, 3)
+#define NPCX_TCKC_LOW_PWR 7
+#define NPCX_TCKC_PLS_ACC_CLK 6
+#define NPCX_TCKC_C1CSEL_FIELD FIELD(0, 3)
+#define NPCX_TCKC_C2CSEL_FIELD FIELD(3, 3)
+#define NPCX_TMCTRL_TAEN 5
+#define NPCX_TMCTRL_TBEN 6
+#define NPCX_TMCTRL_TAEDG 3
+#define NPCX_TMCTRL_TBEDG 4
+#define NPCX_TCFG_TADBEN 6
+#define NPCX_TCFG_TBDBEN 7
+#define NPCX_TECTRL_TAPND 0
+#define NPCX_TECTRL_TBPND 1
+#define NPCX_TECTRL_TCPND 2
+#define NPCX_TECTRL_TDPND 3
+#define NPCX_TECLR_TACLR 0
+#define NPCX_TECLR_TBCLR 1
+#define NPCX_TECLR_TCCLR 2
+#define NPCX_TECLR_TDCLR 3
+#define NPCX_TIEN_TAIEN 0
+#define NPCX_TIEN_TBIEN 1
+#define NPCX_TIEN_TCIEN 2
+#define NPCX_TIEN_TDIEN 3
+#define NPCX_TWUEN_TAWEN 0
+#define NPCX_TWUEN_TBWEN 1
+#define NPCX_TWUEN_TCWEN 2
+#define NPCX_TWUEN_TDWEN 3
 /******************************************************************************/
 /* ITIM16/32 Define */
-#define ITIM_INT(module)               CONCAT2(NPCX_IRQ_, module)
+#define ITIM_INT(module) CONCAT2(NPCX_IRQ_, module)
 
 /* ITIM16/32 register */
-#define NPCX_ITPRE(n)                    REG8(NPCX_ITIM_BASE_ADDR(n) + 0x001)
-#define NPCX_ITCTS(n)                    REG8(NPCX_ITIM_BASE_ADDR(n) + 0x004)
+#define NPCX_ITPRE(n) REG8(NPCX_ITIM_BASE_ADDR(n) + 0x001)
+#define NPCX_ITCTS(n) REG8(NPCX_ITIM_BASE_ADDR(n) + 0x004)
 
 /* ITIM16 register fields */
-#define NPCX_ITCTS_TO_STS                0
-#define NPCX_ITCTS_TO_IE                 2
-#define NPCX_ITCTS_TO_WUE                3
-#define NPCX_ITCTS_CKSEL                 4
-#define NPCX_ITCTS_ITEN                  7
+#define NPCX_ITCTS_TO_STS 0
+#define NPCX_ITCTS_TO_IE 2
+#define NPCX_ITCTS_TO_WUE 3
+#define NPCX_ITCTS_CKSEL 4
+#define NPCX_ITCTS_ITEN 7
 
 /******************************************************************************/
 /* Serial Host Interface (SHI) Registers */
-#define NPCX_SHICFG1                      REG8(NPCX_SHI_BASE_ADDR + 0x001)
-#define NPCX_SHICFG2                      REG8(NPCX_SHI_BASE_ADDR + 0x002)
-#define NPCX_I2CADDR1                     REG8(NPCX_SHI_BASE_ADDR + 0x003)
-#define NPCX_I2CADDR2                     REG8(NPCX_SHI_BASE_ADDR + 0x004)
-#define NPCX_EVENABLE                     REG8(NPCX_SHI_BASE_ADDR + 0x005)
-#define NPCX_EVSTAT                       REG8(NPCX_SHI_BASE_ADDR + 0x006)
-#define NPCX_SHI_CAPABILITY               REG8(NPCX_SHI_BASE_ADDR + 0x007)
-#define NPCX_STATUS                       REG8(NPCX_SHI_BASE_ADDR + 0x008)
-#define NPCX_IBUFSTAT                     REG8(NPCX_SHI_BASE_ADDR + 0x00A)
-#define NPCX_OBUFSTAT                     REG8(NPCX_SHI_BASE_ADDR + 0x00B)
+#define NPCX_SHICFG1 REG8(NPCX_SHI_BASE_ADDR + 0x001)
+#define NPCX_SHICFG2 REG8(NPCX_SHI_BASE_ADDR + 0x002)
+#define NPCX_I2CADDR1 REG8(NPCX_SHI_BASE_ADDR + 0x003)
+#define NPCX_I2CADDR2 REG8(NPCX_SHI_BASE_ADDR + 0x004)
+#define NPCX_EVENABLE REG8(NPCX_SHI_BASE_ADDR + 0x005)
+#define NPCX_EVSTAT REG8(NPCX_SHI_BASE_ADDR + 0x006)
+#define NPCX_SHI_CAPABILITY REG8(NPCX_SHI_BASE_ADDR + 0x007)
+#define NPCX_STATUS REG8(NPCX_SHI_BASE_ADDR + 0x008)
+#define NPCX_IBUFSTAT REG8(NPCX_SHI_BASE_ADDR + 0x00A)
+#define NPCX_OBUFSTAT REG8(NPCX_SHI_BASE_ADDR + 0x00B)
 
 /* SHI register fields */
-#define NPCX_SHICFG1_EN                  0
-#define NPCX_SHICFG1_MODE                1
-#define NPCX_SHICFG1_WEN                 2
-#define NPCX_SHICFG1_AUTIBF              3
-#define NPCX_SHICFG1_AUTOBE              4
-#define NPCX_SHICFG1_DAS                 5
-#define NPCX_SHICFG1_CPOL                6
-#define NPCX_SHICFG1_IWRAP               7
-#define NPCX_SHICFG2_SIMUL               0
-#define NPCX_SHICFG2_BUSY                1
-#define NPCX_SHICFG2_ONESHOT             2
-#define NPCX_SHICFG2_SLWU                3
-#define NPCX_SHICFG2_REEN                4
-#define NPCX_SHICFG2_RESTART             5
-#define NPCX_SHICFG2_REEVEN              6
-#define NPCX_EVENABLE_OBEEN              0
-#define NPCX_EVENABLE_OBHEEN             1
-#define NPCX_EVENABLE_IBFEN              2
-#define NPCX_EVENABLE_IBHFEN             3
-#define NPCX_EVENABLE_EOREN              4
-#define NPCX_EVENABLE_EOWEN              5
-#define NPCX_EVENABLE_STSREN             6
-#define NPCX_EVENABLE_IBOREN             7
-#define NPCX_EVSTAT_OBE                  0
-#define NPCX_EVSTAT_OBHE                 1
-#define NPCX_EVSTAT_IBF                  2
-#define NPCX_EVSTAT_IBHF                 3
-#define NPCX_EVSTAT_EOR                  4
-#define NPCX_EVSTAT_EOW                  5
-#define NPCX_EVSTAT_STSR                 6
-#define NPCX_EVSTAT_IBOR                 7
-#define NPCX_STATUS_OBES                 6
-#define NPCX_STATUS_IBFS                 7
+#define NPCX_SHICFG1_EN 0
+#define NPCX_SHICFG1_MODE 1
+#define NPCX_SHICFG1_WEN 2
+#define NPCX_SHICFG1_AUTIBF 3
+#define NPCX_SHICFG1_AUTOBE 4
+#define NPCX_SHICFG1_DAS 5
+#define NPCX_SHICFG1_CPOL 6
+#define NPCX_SHICFG1_IWRAP 7
+#define NPCX_SHICFG2_SIMUL 0
+#define NPCX_SHICFG2_BUSY 1
+#define NPCX_SHICFG2_ONESHOT 2
+#define NPCX_SHICFG2_SLWU 3
+#define NPCX_SHICFG2_REEN 4
+#define NPCX_SHICFG2_RESTART 5
+#define NPCX_SHICFG2_REEVEN 6
+#define NPCX_EVENABLE_OBEEN 0
+#define NPCX_EVENABLE_OBHEEN 1
+#define NPCX_EVENABLE_IBFEN 2
+#define NPCX_EVENABLE_IBHFEN 3
+#define NPCX_EVENABLE_EOREN 4
+#define NPCX_EVENABLE_EOWEN 5
+#define NPCX_EVENABLE_STSREN 6
+#define NPCX_EVENABLE_IBOREN 7
+#define NPCX_EVSTAT_OBE 0
+#define NPCX_EVSTAT_OBHE 1
+#define NPCX_EVSTAT_IBF 2
+#define NPCX_EVSTAT_IBHF 3
+#define NPCX_EVSTAT_EOR 4
+#define NPCX_EVSTAT_EOW 5
+#define NPCX_EVSTAT_STSR 6
+#define NPCX_EVSTAT_IBOR 7
+#define NPCX_STATUS_OBES 6
+#define NPCX_STATUS_IBFS 7
 
 /******************************************************************************/
 /* Monotonic Counter (MTC) Registers */
-#define NPCX_TTC                         REG32(NPCX_MTC_BASE_ADDR + 0x000)
-#define NPCX_WTC                         REG32(NPCX_MTC_BASE_ADDR + 0x004)
-#define NPCX_MTCTST                       REG8(NPCX_MTC_BASE_ADDR + 0x008)
-#define NPCX_MTCVER                       REG8(NPCX_MTC_BASE_ADDR + 0x00C)
+#define NPCX_TTC REG32(NPCX_MTC_BASE_ADDR + 0x000)
+#define NPCX_WTC REG32(NPCX_MTC_BASE_ADDR + 0x004)
+#define NPCX_MTCTST REG8(NPCX_MTC_BASE_ADDR + 0x008)
+#define NPCX_MTCVER REG8(NPCX_MTC_BASE_ADDR + 0x00C)
 
 /* MTC register fields */
-#define NPCX_WTC_PTO                     30
-#define NPCX_WTC_WIE                     31
+#define NPCX_WTC_PTO 30
+#define NPCX_WTC_WIE 31
 
 /******************************************************************************/
 /* Low Power RAM definitions */
-#define NPCX_LPRAM_CTRL                  REG32(0x40001044)
+#define NPCX_LPRAM_CTRL REG32(0x40001044)
 
 /******************************************************************************/
 /*  eSPI Registers */
-#define NPCX_ESPIID                 REG32(NPCX_ESPI_BASE_ADDR + 0X00)
-#define NPCX_ESPICFG                REG32(NPCX_ESPI_BASE_ADDR + 0X04)
-#define NPCX_ESPISTS                REG32(NPCX_ESPI_BASE_ADDR + 0X08)
-#define NPCX_ESPIIE                 REG32(NPCX_ESPI_BASE_ADDR + 0X0C)
-#define NPCX_ESPIWE                 REG32(NPCX_ESPI_BASE_ADDR + 0X10)
-#define NPCX_VWREGIDX               REG32(NPCX_ESPI_BASE_ADDR + 0X14)
-#define NPCX_VWREGDATA              REG32(NPCX_ESPI_BASE_ADDR + 0X18)
-#define NPCX_OOBCTL                 REG32(NPCX_ESPI_BASE_ADDR + 0X24)
-#define NPCX_FLASHRXRDHEAD          REG32(NPCX_ESPI_BASE_ADDR + 0X28)
-#define NPCX_FLASHTXWRHEAD          REG32(NPCX_ESPI_BASE_ADDR + 0X2C)
-#define NPCX_FLASHCFG               REG32(NPCX_ESPI_BASE_ADDR + 0X34)
-#define NPCX_FLASHCTL               REG32(NPCX_ESPI_BASE_ADDR + 0X38)
-#define NPCX_ESPIERR                REG32(NPCX_ESPI_BASE_ADDR + 0X3C)
-
-#define NPCX_ONLY_ESPI_REG1         REG8(NPCX_ESPI_BASE_ADDR + 0XF0)
-#define NPCX_ONLY_ESPI_REG2         REG8(NPCX_ESPI_BASE_ADDR + 0XF1)
-
-#define NPCX_ONLY_ESPI_REG1_UNLOCK_REG2         0x55
-#define NPCX_ONLY_ESPI_REG1_LOCK_REG2           0
-#define NPCX_ONLY_ESPI_REG2_TRANS_END_CONFIG    4
+#define NPCX_ESPIID REG32(NPCX_ESPI_BASE_ADDR + 0X00)
+#define NPCX_ESPICFG REG32(NPCX_ESPI_BASE_ADDR + 0X04)
+#define NPCX_ESPISTS REG32(NPCX_ESPI_BASE_ADDR + 0X08)
+#define NPCX_ESPIIE REG32(NPCX_ESPI_BASE_ADDR + 0X0C)
+#define NPCX_ESPIWE REG32(NPCX_ESPI_BASE_ADDR + 0X10)
+#define NPCX_VWREGIDX REG32(NPCX_ESPI_BASE_ADDR + 0X14)
+#define NPCX_VWREGDATA REG32(NPCX_ESPI_BASE_ADDR + 0X18)
+#define NPCX_OOBCTL REG32(NPCX_ESPI_BASE_ADDR + 0X24)
+#define NPCX_FLASHRXRDHEAD REG32(NPCX_ESPI_BASE_ADDR + 0X28)
+#define NPCX_FLASHTXWRHEAD REG32(NPCX_ESPI_BASE_ADDR + 0X2C)
+#define NPCX_FLASHCFG REG32(NPCX_ESPI_BASE_ADDR + 0X34)
+#define NPCX_FLASHCTL REG32(NPCX_ESPI_BASE_ADDR + 0X38)
+#define NPCX_ESPIERR REG32(NPCX_ESPI_BASE_ADDR + 0X3C)
+
+#define NPCX_ONLY_ESPI_REG1 REG8(NPCX_ESPI_BASE_ADDR + 0XF0)
+#define NPCX_ONLY_ESPI_REG2 REG8(NPCX_ESPI_BASE_ADDR + 0XF1)
+
+#define NPCX_ONLY_ESPI_REG1_UNLOCK_REG2 0x55
+#define NPCX_ONLY_ESPI_REG1_LOCK_REG2 0
+#define NPCX_ONLY_ESPI_REG2_TRANS_END_CONFIG 4
 
 /* eSPI Virtual Wire channel registers */
-#define NPCX_VWEVSM(n)              REG32(NPCX_ESPI_BASE_ADDR + 0x100 + (4*(n)))
-#define NPCX_VWEVMS(n)              REG32(NPCX_ESPI_BASE_ADDR + 0x140 + (4*(n)))
-#define NPCX_VWCTL                  REG32(NPCX_ESPI_BASE_ADDR + 0x2FC)
+#define NPCX_VWEVSM(n) REG32(NPCX_ESPI_BASE_ADDR + 0x100 + (4 * (n)))
+#define NPCX_VWEVMS(n) REG32(NPCX_ESPI_BASE_ADDR + 0x140 + (4 * (n)))
+#define NPCX_VWCTL REG32(NPCX_ESPI_BASE_ADDR + 0x2FC)
 
 /* eSPI register fields */
-#define NPCX_ESPICFG_PCHANEN             0
-#define NPCX_ESPICFG_VWCHANEN            1
-#define NPCX_ESPICFG_OOBCHANEN           2
-#define NPCX_ESPICFG_FLASHCHANEN         3
-#define NPCX_ESPICFG_HPCHANEN            4
-#define NPCX_ESPICFG_HVWCHANEN           5
-#define NPCX_ESPICFG_HOOBCHANEN          6
-#define NPCX_ESPICFG_HFLASHCHANEN        7
-#define NPCX_ESPICFG_IOMODE_FIELD        FIELD(8, 2)
-#define NPCX_ESPICFG_MAXFREQ_FIELD       FIELD(10, 3)
-#define NPCX_ESPICFG_OPFREQ_FIELD        FIELD(17, 3)
-#define NPCX_ESPICFG_IOMODESEL_FIELD     FIELD(20, 2)
-#define NPCX_ESPICFG_ALERT_MODE          22
-#define NPCX_ESPICFG_CRC_CHK             23
-#define NPCX_ESPICFG_PCCHN_SUPP          24
-#define NPCX_ESPICFG_VWCHN_SUPP          25
-#define NPCX_ESPICFG_OOBCHN_SUPP         26
-#define NPCX_ESPICFG_FLASHCHN_SUPP       27
-#define NPCX_ESPIERR_INVCMD              0 /* Invalid Command Type */
-#define NPCX_ESPIERR_INVCYC              1 /* Invalid Cycle Type */
-#define NPCX_ESPIERR_CRCERR              2 /* Transaction CRC Error */
-#define NPCX_ESPIERR_ABCOMP              3 /* Abnormal Completion */
-#define NPCX_ESPIERR_PROTERR             4 /* Protocol Error */
-#define NPCX_ESPIERR_BADSIZE             5 /* Bad Size */
-#define NPCX_ESPIERR_NPBADALN            6 /* NPPC Bad Address Alignment */
-#define NPCX_ESPIERR_PCBADALN            7 /* PPC Bad Address Alignment */
-#define NPCX_ESPIERR_UNCMD               9 /* Unsupported Command */
-#define NPCX_ESPIERR_EXTRACYC            10 /* Extra eSPI Clock Cycles */
-#define NPCX_ESPIERR_VWERR               11 /* Virtual Channel Access Error */
-#define NPCX_ESPIERR_UNPBM               14 /* Unsuccessful Bus Completion */
-#define NPCX_ESPIERR_UNFLASH             15 /* Unsuccessful Flash Completion */
-#define NPCX_ESPIIE_IBRSTIE              0
-#define NPCX_ESPIIE_CFGUPDIE             1
-#define NPCX_ESPIIE_BERRIE               2
-#define NPCX_ESPIIE_OOBRXIE              3
-#define NPCX_ESPIIE_FLASHRXIE            4
-#define NPCX_ESPIIE_SFLASHRDIE           5
-#define NPCX_ESPIIE_PERACCIE             6
-#define NPCX_ESPIIE_DFRDIE               7
-#define NPCX_ESPIIE_VWUPDIE              8
-#define NPCX_ESPIIE_ESPIRSTIE            9
-#define NPCX_ESPIIE_PLTRSTIE             10
-#define NPCX_ESPIIE_AMERRIE              15
-#define NPCX_ESPIIE_AMDONEIE             16
-#define NPCX_ESPIWE_IBRSTWE              0
-#define NPCX_ESPIWE_CFGUPDWE             1
-#define NPCX_ESPIWE_BERRWE               2
-#define NPCX_ESPIWE_OOBRXWE              3
-#define NPCX_ESPIWE_FLASHRXWE            4
-#define NPCX_ESPIWE_PERACCWE             6
-#define NPCX_ESPIWE_DFRDWE               7
-#define NPCX_ESPIWE_VWUPDWE              8
-#define NPCX_ESPIWE_ESPIRSTWE            9
-#define NPCX_ESPISTS_IBRST               0
-#define NPCX_ESPISTS_CFGUPD              1
-#define NPCX_ESPISTS_BERR                2
-#define NPCX_ESPISTS_OOBRX               3
-#define NPCX_ESPISTS_FLASHRX             4
-#define NPCX_ESPISTS_SFLASHRD            5
-#define NPCX_ESPISTS_PERACC              6
-#define NPCX_ESPISTS_DFRD                7
-#define NPCX_ESPISTS_VWUPD               8
-#define NPCX_ESPISTS_ESPIRST             9
-#define NPCX_ESPISTS_PLTRST              10
-#define NPCX_ESPISTS_AMERR               15
-#define NPCX_ESPISTS_AMDONE              16
+#define NPCX_ESPICFG_PCHANEN 0
+#define NPCX_ESPICFG_VWCHANEN 1
+#define NPCX_ESPICFG_OOBCHANEN 2
+#define NPCX_ESPICFG_FLASHCHANEN 3
+#define NPCX_ESPICFG_HPCHANEN 4
+#define NPCX_ESPICFG_HVWCHANEN 5
+#define NPCX_ESPICFG_HOOBCHANEN 6
+#define NPCX_ESPICFG_HFLASHCHANEN 7
+#define NPCX_ESPICFG_IOMODE_FIELD FIELD(8, 2)
+#define NPCX_ESPICFG_MAXFREQ_FIELD FIELD(10, 3)
+#define NPCX_ESPICFG_OPFREQ_FIELD FIELD(17, 3)
+#define NPCX_ESPICFG_IOMODESEL_FIELD FIELD(20, 2)
+#define NPCX_ESPICFG_ALERT_MODE 22
+#define NPCX_ESPICFG_CRC_CHK 23
+#define NPCX_ESPICFG_PCCHN_SUPP 24
+#define NPCX_ESPICFG_VWCHN_SUPP 25
+#define NPCX_ESPICFG_OOBCHN_SUPP 26
+#define NPCX_ESPICFG_FLASHCHN_SUPP 27
+#define NPCX_ESPIERR_INVCMD 0 /* Invalid Command Type */
+#define NPCX_ESPIERR_INVCYC 1 /* Invalid Cycle Type */
+#define NPCX_ESPIERR_CRCERR 2 /* Transaction CRC Error */
+#define NPCX_ESPIERR_ABCOMP 3 /* Abnormal Completion */
+#define NPCX_ESPIERR_PROTERR 4 /* Protocol Error */
+#define NPCX_ESPIERR_BADSIZE 5 /* Bad Size */
+#define NPCX_ESPIERR_NPBADALN 6 /* NPPC Bad Address Alignment */
+#define NPCX_ESPIERR_PCBADALN 7 /* PPC Bad Address Alignment */
+#define NPCX_ESPIERR_UNCMD 9 /* Unsupported Command */
+#define NPCX_ESPIERR_EXTRACYC 10 /* Extra eSPI Clock Cycles */
+#define NPCX_ESPIERR_VWERR 11 /* Virtual Channel Access Error */
+#define NPCX_ESPIERR_UNPBM 14 /* Unsuccessful Bus Completion */
+#define NPCX_ESPIERR_UNFLASH 15 /* Unsuccessful Flash Completion */
+#define NPCX_ESPIIE_IBRSTIE 0
+#define NPCX_ESPIIE_CFGUPDIE 1
+#define NPCX_ESPIIE_BERRIE 2
+#define NPCX_ESPIIE_OOBRXIE 3
+#define NPCX_ESPIIE_FLASHRXIE 4
+#define NPCX_ESPIIE_SFLASHRDIE 5
+#define NPCX_ESPIIE_PERACCIE 6
+#define NPCX_ESPIIE_DFRDIE 7
+#define NPCX_ESPIIE_VWUPDIE 8
+#define NPCX_ESPIIE_ESPIRSTIE 9
+#define NPCX_ESPIIE_PLTRSTIE 10
+#define NPCX_ESPIIE_AMERRIE 15
+#define NPCX_ESPIIE_AMDONEIE 16
+#define NPCX_ESPIWE_IBRSTWE 0
+#define NPCX_ESPIWE_CFGUPDWE 1
+#define NPCX_ESPIWE_BERRWE 2
+#define NPCX_ESPIWE_OOBRXWE 3
+#define NPCX_ESPIWE_FLASHRXWE 4
+#define NPCX_ESPIWE_PERACCWE 6
+#define NPCX_ESPIWE_DFRDWE 7
+#define NPCX_ESPIWE_VWUPDWE 8
+#define NPCX_ESPIWE_ESPIRSTWE 9
+#define NPCX_ESPISTS_IBRST 0
+#define NPCX_ESPISTS_CFGUPD 1
+#define NPCX_ESPISTS_BERR 2
+#define NPCX_ESPISTS_OOBRX 3
+#define NPCX_ESPISTS_FLASHRX 4
+#define NPCX_ESPISTS_SFLASHRD 5
+#define NPCX_ESPISTS_PERACC 6
+#define NPCX_ESPISTS_DFRD 7
+#define NPCX_ESPISTS_VWUPD 8
+#define NPCX_ESPISTS_ESPIRST 9
+#define NPCX_ESPISTS_PLTRST 10
+#define NPCX_ESPISTS_AMERR 15
+#define NPCX_ESPISTS_AMDONE 16
 /* eSPI Virtual Wire channel register fields */
-#define NPCX_VWEVSM_WIRE                 FIELD(0, 4)
-#define NPCX_VWEVMS_WIRE                 FIELD(0, 4)
-#define NPCX_VWEVSM_VALID                FIELD(4, 4)
-#define NPCX_VWEVMS_VALID                FIELD(4, 4)
+#define NPCX_VWEVSM_WIRE FIELD(0, 4)
+#define NPCX_VWEVMS_WIRE FIELD(0, 4)
+#define NPCX_VWEVSM_VALID FIELD(4, 4)
+#define NPCX_VWEVMS_VALID FIELD(4, 4)
 
 /* Macro functions for eSPI CFG & IE */
-#define IS_PERIPHERAL_CHAN_ENABLE(ch)    IS_BIT_SET(NPCX_ESPICFG, ch)
-#define IS_HOST_CHAN_EN(ch)              IS_BIT_SET(NPCX_ESPICFG, (ch+4))
-#define ENABLE_ESPI_CHAN(ch)             SET_BIT(NPCX_ESPICFG, ch)
-#define DISABLE_ESPI_CHAN(ch)            CLEAR_BIT(NPCX_ESPICFG, ch)
+#define IS_PERIPHERAL_CHAN_ENABLE(ch) IS_BIT_SET(NPCX_ESPICFG, ch)
+#define IS_HOST_CHAN_EN(ch) IS_BIT_SET(NPCX_ESPICFG, (ch + 4))
+#define ENABLE_ESPI_CHAN(ch) SET_BIT(NPCX_ESPICFG, ch)
+#define DISABLE_ESPI_CHAN(ch) CLEAR_BIT(NPCX_ESPICFG, ch)
 /* ESPI Peripheral Channel Support Definitions */
-#define ESPI_SUPP_CH_PC                  BIT(NPCX_ESPICFG_PCCHN_SUPP)
-#define ESPI_SUPP_CH_VM                  BIT(NPCX_ESPICFG_VWCHN_SUPP)
-#define ESPI_SUPP_CH_OOB                 BIT(NPCX_ESPICFG_OOBCHN_SUPP)
-#define ESPI_SUPP_CH_FLASH               BIT(NPCX_ESPICFG_FLASHCHN_SUPP)
-#define ESPI_SUPP_CH_ALL                 (ESPI_SUPP_CH_PC | ESPI_SUPP_CH_VM | \
-					  ESPI_SUPP_CH_OOB | ESPI_SUPP_CH_FLASH)
+#define ESPI_SUPP_CH_PC BIT(NPCX_ESPICFG_PCCHN_SUPP)
+#define ESPI_SUPP_CH_VM BIT(NPCX_ESPICFG_VWCHN_SUPP)
+#define ESPI_SUPP_CH_OOB BIT(NPCX_ESPICFG_OOBCHN_SUPP)
+#define ESPI_SUPP_CH_FLASH BIT(NPCX_ESPICFG_FLASHCHN_SUPP)
+#define ESPI_SUPP_CH_ALL                                        \
+	(ESPI_SUPP_CH_PC | ESPI_SUPP_CH_VM | ESPI_SUPP_CH_OOB | \
+	 ESPI_SUPP_CH_FLASH)
 /* ESPI Interrupts Enable Definitions */
-#define ESPIIE_IBRST                     BIT(NPCX_ESPIIE_IBRSTIE)
-#define ESPIIE_CFGUPD                    BIT(NPCX_ESPIIE_CFGUPDIE)
-#define ESPIIE_BERR                      BIT(NPCX_ESPIIE_BERRIE)
-#define ESPIIE_OOBRX                     BIT(NPCX_ESPIIE_OOBRXIE)
-#define ESPIIE_FLASHRX                   BIT(NPCX_ESPIIE_FLASHRXIE)
-#define ESPIIE_SFLASHRD                  BIT(NPCX_ESPIIE_SFLASHRDIE)
-#define ESPIIE_PERACC                    BIT(NPCX_ESPIIE_PERACCIE)
-#define ESPIIE_DFRD                      BIT(NPCX_ESPIIE_DFRDIE)
-#define ESPIIE_VWUPD                     BIT(NPCX_ESPIIE_VWUPDIE)
-#define ESPIIE_ESPIRST                   BIT(NPCX_ESPIIE_ESPIRSTIE)
-#define ESPIIE_PLTRST                    BIT(NPCX_ESPIIE_PLTRSTIE)
-#define ESPIIE_AMERR                     BIT(NPCX_ESPIIE_AMERRIE)
-#define ESPIIE_AMDONE                    BIT(NPCX_ESPIIE_AMDONEIE)
+#define ESPIIE_IBRST BIT(NPCX_ESPIIE_IBRSTIE)
+#define ESPIIE_CFGUPD BIT(NPCX_ESPIIE_CFGUPDIE)
+#define ESPIIE_BERR BIT(NPCX_ESPIIE_BERRIE)
+#define ESPIIE_OOBRX BIT(NPCX_ESPIIE_OOBRXIE)
+#define ESPIIE_FLASHRX BIT(NPCX_ESPIIE_FLASHRXIE)
+#define ESPIIE_SFLASHRD BIT(NPCX_ESPIIE_SFLASHRDIE)
+#define ESPIIE_PERACC BIT(NPCX_ESPIIE_PERACCIE)
+#define ESPIIE_DFRD BIT(NPCX_ESPIIE_DFRDIE)
+#define ESPIIE_VWUPD BIT(NPCX_ESPIIE_VWUPDIE)
+#define ESPIIE_ESPIRST BIT(NPCX_ESPIIE_ESPIRSTIE)
+#define ESPIIE_PLTRST BIT(NPCX_ESPIIE_PLTRSTIE)
+#define ESPIIE_AMERR BIT(NPCX_ESPIIE_AMERRIE)
+#define ESPIIE_AMDONE BIT(NPCX_ESPIIE_AMDONEIE)
 /* eSPI Interrupts for VW */
-#define ESPIIE_VW                        (ESPIIE_VWUPD | ESPIIE_PLTRST)
+#define ESPIIE_VW (ESPIIE_VWUPD | ESPIIE_PLTRST)
 /* eSPI Interrupts for Generic */
-#define ESPIIE_GENERIC                   (ESPIIE_IBRST | ESPIIE_CFGUPD | \
-					  ESPIIE_BERR | ESPIIE_ESPIRST)
+#define ESPIIE_GENERIC \
+	(ESPIIE_IBRST | ESPIIE_CFGUPD | ESPIIE_BERR | ESPIIE_ESPIRST)
 /* ESPI Wake-up Enable Definitions */
-#define ESPIWE_IBRST                     BIT(NPCX_ESPIWE_IBRSTWE)
-#define ESPIWE_CFGUPD                    BIT(NPCX_ESPIWE_CFGUPDWE)
-#define ESPIWE_BERR                      BIT(NPCX_ESPIWE_BERRWE)
-#define ESPIWE_OOBRX                     BIT(NPCX_ESPIWE_OOBRXWE)
-#define ESPIWE_FLASHRX                   BIT(NPCX_ESPIWE_FLASHRXWE)
-#define ESPIWE_PERACC                    BIT(NPCX_ESPIWE_PERACCWE)
-#define ESPIWE_DFRD                      BIT(NPCX_ESPIWE_DFRDWE)
-#define ESPIWE_VWUPD                     BIT(NPCX_ESPIWE_VWUPDWE)
-#define ESPIWE_ESPIRST                   BIT(NPCX_ESPIWE_ESPIRSTWE)
+#define ESPIWE_IBRST BIT(NPCX_ESPIWE_IBRSTWE)
+#define ESPIWE_CFGUPD BIT(NPCX_ESPIWE_CFGUPDWE)
+#define ESPIWE_BERR BIT(NPCX_ESPIWE_BERRWE)
+#define ESPIWE_OOBRX BIT(NPCX_ESPIWE_OOBRXWE)
+#define ESPIWE_FLASHRX BIT(NPCX_ESPIWE_FLASHRXWE)
+#define ESPIWE_PERACC BIT(NPCX_ESPIWE_PERACCWE)
+#define ESPIWE_DFRD BIT(NPCX_ESPIWE_DFRDWE)
+#define ESPIWE_VWUPD BIT(NPCX_ESPIWE_VWUPDWE)
+#define ESPIWE_ESPIRST BIT(NPCX_ESPIWE_ESPIRSTWE)
 /* eSPI  Wake-up enable for VW */
-#define ESPIWE_VW                        ESPIWE_VWUPD
+#define ESPIWE_VW ESPIWE_VWUPD
 /* eSPI  Wake-up enable for Generic */
-#define ESPIWE_GENERIC                   (ESPIWE_IBRST | ESPIWE_CFGUPD | \
-					  ESPIWE_BERR)
+#define ESPIWE_GENERIC (ESPIWE_IBRST | ESPIWE_CFGUPD | ESPIWE_BERR)
 /* Macro functions for eSPI VW */
-#define ESPI_VWEVMS_NUM                  12
-#define ESPI_VWEVSM_NUM                  10
-#define ESPI_VW_IDX_WIRE_NUM             4
+#define ESPI_VWEVMS_NUM 12
+#define ESPI_VWEVSM_NUM 10
+#define ESPI_VW_IDX_WIRE_NUM 4
 /* Determine Virtual Wire type */
-#define VM_TYPE(i)              ((i >= 0   && i <=  1) ? ESPI_VW_TYPE_INT_EV : \
-				 (i >= 2   && i <=  7) ? ESPI_VW_TYPE_SYS_EV : \
-				 (i >= 64  && i <= 127) ? ESPI_VW_TYPE_PLT : \
-				 (i >= 128 && i <= 255) ? ESPI_VW_TYPE_GPIO : \
-							ESPI_VW_TYPE_NONE)
+#define VM_TYPE(i)                                      \
+	((i >= 0 && i <= 1)	? ESPI_VW_TYPE_INT_EV : \
+	 (i >= 2 && i <= 7)	? ESPI_VW_TYPE_SYS_EV : \
+	 (i >= 64 && i <= 127)	? ESPI_VW_TYPE_PLT :    \
+	 (i >= 128 && i <= 255) ? ESPI_VW_TYPE_GPIO :   \
+				  ESPI_VW_TYPE_NONE)
 
 /* Bit field manipulation for VWEVMS Value */
-#define VWEVMS_INX(i)                ((i<<8)  & 0x00007F00)
-#define VWEVMS_INX_EN(n)             ((n<<15) & 0x00008000)
-#define VWEVMS_PLTRST_EN(p)          ((p<<17) & 0x00020000)
-#define VWEVMS_INT_EN(e)             ((e<<18) & 0x00040000)
-#define VWEVMS_ESPIRST_EN(r)         ((r<<19) & 0x00080000)
-#define VWEVMS_FIELD(i, n, p, e, r)  (VWEVMS_INX(i) | VWEVMS_INX_EN(n) | \
-				VWEVMS_PLTRST_EN(p) | VWEVMS_INTWK_EN(e) | \
-				VWEVMS_ESPIRST_EN(r))
-#define VWEVMS_IDX_GET(reg)          (((reg & 0x00007F00)>>8))
+#define VWEVMS_INX(i) ((i << 8) & 0x00007F00)
+#define VWEVMS_INX_EN(n) ((n << 15) & 0x00008000)
+#define VWEVMS_PLTRST_EN(p) ((p << 17) & 0x00020000)
+#define VWEVMS_INT_EN(e) ((e << 18) & 0x00040000)
+#define VWEVMS_ESPIRST_EN(r) ((r << 19) & 0x00080000)
+#define VWEVMS_FIELD(i, n, p, e, r)                               \
+	(VWEVMS_INX(i) | VWEVMS_INX_EN(n) | VWEVMS_PLTRST_EN(p) | \
+	 VWEVMS_INTWK_EN(e) | VWEVMS_ESPIRST_EN(r))
+#define VWEVMS_IDX_GET(reg) (((reg & 0x00007F00) >> 8))
 
 /* Bit field manipulation for VWEVSM Value */
-#define VWEVSM_VALID_N(v)            ((v<<4)  & 0x000000F0)
-#define VWEVSM_INX(i)                ((i<<8)  & 0x00007F00)
-#define VWEVSM_INX_EN(n)             ((n<<15) & 0x00008000)
-#define VWEVSM_DIRTY(d)              ((d<<16) & 0x00010000)
-#define VWEVSM_PLTRST_EN(p)          ((p<<17) & 0x00020000)
-#define VWEVSM_CDRST_EN(c)           ((c<<19) & 0x00080000)
-#define VWEVSM_FIELD(i, n, v, p, c)  (VWEVSM_INX(i) | VWEVSM_INX_EN(n) | \
-				VWEVSM_VALID_N(v) | VWEVSM_PLTRST_EN(p) |\
-				VWEVSM_CDRST_EN(c))
-#define VWEVSM_IDX_GET(reg)          (((reg & 0x00007F00)>>8))
+#define VWEVSM_VALID_N(v) ((v << 4) & 0x000000F0)
+#define VWEVSM_INX(i) ((i << 8) & 0x00007F00)
+#define VWEVSM_INX_EN(n) ((n << 15) & 0x00008000)
+#define VWEVSM_DIRTY(d) ((d << 16) & 0x00010000)
+#define VWEVSM_PLTRST_EN(p) ((p << 17) & 0x00020000)
+#define VWEVSM_CDRST_EN(c) ((c << 19) & 0x00080000)
+#define VWEVSM_FIELD(i, n, v, p, c)                             \
+	(VWEVSM_INX(i) | VWEVSM_INX_EN(n) | VWEVSM_VALID_N(v) | \
+	 VWEVSM_PLTRST_EN(p) | VWEVSM_CDRST_EN(c))
+#define VWEVSM_IDX_GET(reg) (((reg & 0x00007F00) >> 8))
 
 /* define macro to handle SMI/SCI Virtual Wire */
 /* Read SMI VWire status from VWEVSM(offset 2) register. */
-#define SMI_STATUS_MASK    ((uint8_t) (NPCX_VWEVSM(2) & 0x00000002))
+#define SMI_STATUS_MASK ((uint8_t)(NPCX_VWEVSM(2) & 0x00000002))
 /*
  * Read SCI VWire status from VWEVSM(offset 2) register.
  * Left shift 2 to meet the SCIB field in HIPMIC register.
  */
-#define SCI_STATUS_MASK    (((uint8_t) (NPCX_VWEVSM(2) & 0x00000001)) << 2)
-#define SCIB_MASK(v)       (v << NPCX_HIPMIC_SCIB)
-#define SMIB_MASK(v)       (v << NPCX_HIPMIC_SMIB)
-#define NPCX_VW_SCI(level)  ((NPCX_HIPMIC(PM_CHAN_1) & 0xF9) | \
-				SMI_STATUS_MASK | SCIB_MASK(level))
-#define NPCX_VW_SMI(level)  ((NPCX_HIPMIC(PM_CHAN_1) & 0xF9) | \
-				SCI_STATUS_MASK | SMIB_MASK(level))
+#define SCI_STATUS_MASK (((uint8_t)(NPCX_VWEVSM(2) & 0x00000001)) << 2)
+#define SCIB_MASK(v) (v << NPCX_HIPMIC_SCIB)
+#define SMIB_MASK(v) (v << NPCX_HIPMIC_SMIB)
+#define NPCX_VW_SCI(level) \
+	((NPCX_HIPMIC(PM_CHAN_1) & 0xF9) | SMI_STATUS_MASK | SCIB_MASK(level))
+#define NPCX_VW_SMI(level) \
+	((NPCX_HIPMIC(PM_CHAN_1) & 0xF9) | SCI_STATUS_MASK | SMIB_MASK(level))
 
 /* eSPI enumeration */
 /* eSPI channels */
@@ -1306,374 +1301,367 @@ enum {
 /* eSPI IO modes */
 enum {
 	NPCX_ESPI_IO_MODE_SINGLE = 0,
-	NPCX_ESPI_IO_MODE_DUAL   = 1,
-	NPCX_ESPI_IO_MODE_QUAD   = 2,
-	NPCX_ESPI_IO_MODE_ALL    = 3,
-	NPCX_ESPI_IO_MODE_NONE   = 0xFF
+	NPCX_ESPI_IO_MODE_DUAL = 1,
+	NPCX_ESPI_IO_MODE_QUAD = 2,
+	NPCX_ESPI_IO_MODE_ALL = 3,
+	NPCX_ESPI_IO_MODE_NONE = 0xFF
 };
 
 /* eSPI IO mode selected */
 enum {
 	NPCX_ESPI_IO_MODE_SEL_SINGLE = 0,
-	NPCX_ESPI_IO_MODE_SEL_DUAL   = 1,
-	NPCX_ESPI_IO_MODE_SEL_QUARD  = 2,
-	NPCX_ESPI_IO_MODE_SEL_NONE   = 0xFF
+	NPCX_ESPI_IO_MODE_SEL_DUAL = 1,
+	NPCX_ESPI_IO_MODE_SEL_QUARD = 2,
+	NPCX_ESPI_IO_MODE_SEL_NONE = 0xFF
 };
 
 /* VW types */
 enum {
-	ESPI_VW_TYPE_INT_EV,            /* Interrupt event */
-	ESPI_VW_TYPE_SYS_EV,            /* System Event */
-	ESPI_VW_TYPE_PLT,               /* Platform specific */
-	ESPI_VW_TYPE_GPIO,              /* General Purpose I/O Expander */
+	ESPI_VW_TYPE_INT_EV, /* Interrupt event */
+	ESPI_VW_TYPE_SYS_EV, /* System Event */
+	ESPI_VW_TYPE_PLT, /* Platform specific */
+	ESPI_VW_TYPE_GPIO, /* General Purpose I/O Expander */
 	ESPI_VW_TYPE_NUM,
 	ESPI_VW_TYPE_NONE = 0xFF
 };
 
 /******************************************************************************/
 /* GDMA (General DMA) Registers */
-#define NPCX_GDMA_CTL                    REG32(NPCX_GDMA_BASE_ADDR + 0x000)
-#define NPCX_GDMA_SRCB                   REG32(NPCX_GDMA_BASE_ADDR + 0x004)
-#define NPCX_GDMA_DSTB                   REG32(NPCX_GDMA_BASE_ADDR + 0x008)
-#define NPCX_GDMA_TCNT                   REG32(NPCX_GDMA_BASE_ADDR + 0x00C)
-#define NPCX_GDMA_CSRC                   REG32(NPCX_GDMA_BASE_ADDR + 0x010)
-#define NPCX_GDMA_CDST                   REG32(NPCX_GDMA_BASE_ADDR + 0x014)
-#define NPCX_GDMA_CTCNT                  REG32(NPCX_GDMA_BASE_ADDR + 0x018)
-
+#define NPCX_GDMA_CTL REG32(NPCX_GDMA_BASE_ADDR + 0x000)
+#define NPCX_GDMA_SRCB REG32(NPCX_GDMA_BASE_ADDR + 0x004)
+#define NPCX_GDMA_DSTB REG32(NPCX_GDMA_BASE_ADDR + 0x008)
+#define NPCX_GDMA_TCNT REG32(NPCX_GDMA_BASE_ADDR + 0x00C)
+#define NPCX_GDMA_CSRC REG32(NPCX_GDMA_BASE_ADDR + 0x010)
+#define NPCX_GDMA_CDST REG32(NPCX_GDMA_BASE_ADDR + 0x014)
+#define NPCX_GDMA_CTCNT REG32(NPCX_GDMA_BASE_ADDR + 0x018)
 
 /******************************************************************************/
 /* GDMA register fields */
-#define NPCX_GDMA_CTL_GDMAEN                         0
-#define NPCX_GDMA_CTL_GDMAMS                         FIELD(2,   2)
-#define NPCX_GDMA_CTL_DADIR                          4
-#define NPCX_GDMA_CTL_SADIR                          5
-#define NPCX_GDMA_CTL_SAFIX                          7
-#define NPCX_GDMA_CTL_SIEN                           8
-#define NPCX_GDMA_CTL_BME                            9
-#define NPCX_GDMA_CTL_SBMS                           11
-#define NPCX_GDMA_CTL_TWS                            FIELD(12,  2)
-#define NPCX_GDMA_CTL_DM                             15
-#define NPCX_GDMA_CTL_SOFTREQ                        16
-#define NPCX_GDMA_CTL_TC                             18
-#define NPCX_GDMA_CTL_GDMAERR                        20
-#define NPCX_GDMA_CTL_BLOCK_BUG_CORRECTION_DISABLE   26
+#define NPCX_GDMA_CTL_GDMAEN 0
+#define NPCX_GDMA_CTL_GDMAMS FIELD(2, 2)
+#define NPCX_GDMA_CTL_DADIR 4
+#define NPCX_GDMA_CTL_SADIR 5
+#define NPCX_GDMA_CTL_SAFIX 7
+#define NPCX_GDMA_CTL_SIEN 8
+#define NPCX_GDMA_CTL_BME 9
+#define NPCX_GDMA_CTL_SBMS 11
+#define NPCX_GDMA_CTL_TWS FIELD(12, 2)
+#define NPCX_GDMA_CTL_DM 15
+#define NPCX_GDMA_CTL_SOFTREQ 16
+#define NPCX_GDMA_CTL_TC 18
+#define NPCX_GDMA_CTL_GDMAERR 20
+#define NPCX_GDMA_CTL_BLOCK_BUG_CORRECTION_DISABLE 26
 
 /******************************************************************************/
 /* Nuvoton internal used only registers */
-#define NPCX_INTERNAL_CTRL1               REG8(0x400DB000)
-#define NPCX_INTERNAL_CTRL2               REG8(0x400DD000)
-#define NPCX_INTERNAL_CTRL3               REG8(0x400DF000)
+#define NPCX_INTERNAL_CTRL1 REG8(0x400DB000)
+#define NPCX_INTERNAL_CTRL2 REG8(0x400DD000)
+#define NPCX_INTERNAL_CTRL3 REG8(0x400DF000)
 
 /******************************************************************************/
 /* Optional M4 Registers */
-#define CPU_DHCSR                        REG32(0xE000EDF0)
-#define CPU_MPU_CTRL                     REG32(0xE000ED94)
-#define CPU_MPU_RNR                      REG32(0xE000ED98)
-#define CPU_MPU_RBAR                     REG32(0xE000ED9C)
-#define CPU_MPU_RASR                     REG32(0xE000EDA0)
-
+#define CPU_DHCSR REG32(0xE000EDF0)
+#define CPU_MPU_CTRL REG32(0xE000ED94)
+#define CPU_MPU_RNR REG32(0xE000ED98)
+#define CPU_MPU_RBAR REG32(0xE000ED9C)
+#define CPU_MPU_RASR REG32(0xE000EDA0)
 
 /******************************************************************************/
 /* Flash Utiltiy definition */
 /*
  *  Flash commands for the W25Q16CV SPI flash
  */
-#define CMD_READ_ID                      0x9F
-#define CMD_READ_MAN_DEV_ID              0x90
-#define CMD_WRITE_EN                     0x06
-#define CMD_WRITE_STATUS                 0x50
-#define CMD_READ_STATUS_REG              0x05
-#define CMD_READ_STATUS_REG2             0x35
-#define CMD_WRITE_STATUS_REG             0x01
-#define CMD_FLASH_PROGRAM                0x02
-#define CMD_SECTOR_ERASE                 0x20
-#define CMD_BLOCK_32K_ERASE              0x52
-#define CMD_BLOCK_64K_ERASE              0xd8
-#define CMD_PROGRAM_UINT_SIZE            0x08
-#define CMD_PAGE_SIZE                    0x00
-#define CMD_READ_ID_TYPE                 0x47
-#define CMD_FAST_READ                    0x0B
+#define CMD_READ_ID 0x9F
+#define CMD_READ_MAN_DEV_ID 0x90
+#define CMD_WRITE_EN 0x06
+#define CMD_WRITE_STATUS 0x50
+#define CMD_READ_STATUS_REG 0x05
+#define CMD_READ_STATUS_REG2 0x35
+#define CMD_WRITE_STATUS_REG 0x01
+#define CMD_FLASH_PROGRAM 0x02
+#define CMD_SECTOR_ERASE 0x20
+#define CMD_BLOCK_32K_ERASE 0x52
+#define CMD_BLOCK_64K_ERASE 0xd8
+#define CMD_PROGRAM_UINT_SIZE 0x08
+#define CMD_PAGE_SIZE 0x00
+#define CMD_READ_ID_TYPE 0x47
+#define CMD_FAST_READ 0x0B
 
 /*
  * Status registers for the W25Q16CV SPI flash
  */
-#define SPI_FLASH_SR2_SUS               BIT(7)
-#define SPI_FLASH_SR2_CMP               BIT(6)
-#define SPI_FLASH_SR2_LB3               BIT(5)
-#define SPI_FLASH_SR2_LB2               BIT(4)
-#define SPI_FLASH_SR2_LB1               BIT(3)
-#define SPI_FLASH_SR2_QE                BIT(1)
-#define SPI_FLASH_SR2_SRP1              BIT(0)
-#define SPI_FLASH_SR1_SRP0              BIT(7)
-#define SPI_FLASH_SR1_SEC               BIT(6)
-#define SPI_FLASH_SR1_TB                BIT(5)
-#define SPI_FLASH_SR1_BP2               BIT(4)
-#define SPI_FLASH_SR1_BP1               BIT(3)
-#define SPI_FLASH_SR1_BP0               BIT(2)
-#define SPI_FLASH_SR1_WEL               BIT(1)
-#define SPI_FLASH_SR1_BUSY              BIT(0)
-
+#define SPI_FLASH_SR2_SUS BIT(7)
+#define SPI_FLASH_SR2_CMP BIT(6)
+#define SPI_FLASH_SR2_LB3 BIT(5)
+#define SPI_FLASH_SR2_LB2 BIT(4)
+#define SPI_FLASH_SR2_LB1 BIT(3)
+#define SPI_FLASH_SR2_QE BIT(1)
+#define SPI_FLASH_SR2_SRP1 BIT(0)
+#define SPI_FLASH_SR1_SRP0 BIT(7)
+#define SPI_FLASH_SR1_SEC BIT(6)
+#define SPI_FLASH_SR1_TB BIT(5)
+#define SPI_FLASH_SR1_BP2 BIT(4)
+#define SPI_FLASH_SR1_BP1 BIT(3)
+#define SPI_FLASH_SR1_BP0 BIT(2)
+#define SPI_FLASH_SR1_WEL BIT(1)
+#define SPI_FLASH_SR1_BUSY BIT(0)
 
 /* 0: F_CS0 1: F_CS1_1(GPIO86) 2:F_CS1_2(GPIOA6) */
-#define FIU_CHIP_SELECT		0
+#define FIU_CHIP_SELECT 0
 /* Create UMA control mask */
-#define MASK(bit)       (0x1 << (bit))
-#define A_SIZE          0x03	/* 0: No ADR field 1: 3-bytes ADR field */
-#define C_SIZE          0x04	/* 0: 1-Byte CMD field 1:No CMD field */
-#define RD_WR           0x05	/* 0: Read 1: Write */
-#define DEV_NUM         0x06	/* 0: PVT is used 1: SHD is used */
-#define EXEC_DONE       0x07
-#define D_SIZE_1        0x01
-#define D_SIZE_2        0x02
-#define D_SIZE_3        0x03
-#define D_SIZE_4        0x04
-#define FLASH_SEL       MASK(DEV_NUM)
-
-#define MASK_CMD_ONLY   (MASK(EXEC_DONE) | FLASH_SEL)
-#define MASK_CMD_ADR    (MASK(EXEC_DONE) | FLASH_SEL | MASK(A_SIZE))
-#define MASK_CMD_ADR_WR (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR)  \
-			|MASK(A_SIZE) | D_SIZE_1)
-#define MASK_RD_1BYTE   (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_1)
-#define MASK_RD_2BYTE   (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_2)
-#define MASK_RD_3BYTE   (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_3)
-#define MASK_RD_4BYTE   (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_4)
-#define MASK_CMD_RD_1BYTE       (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_1)
-#define MASK_CMD_RD_2BYTE       (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_2)
-#define MASK_CMD_RD_3BYTE       (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_3)
-#define MASK_CMD_RD_4BYTE       (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_4)
-#define MASK_CMD_WR_ONLY        (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR))
-#define MASK_CMD_WR_1BYTE       (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) \
-				| MASK(C_SIZE) | D_SIZE_1)
-#define MASK_CMD_WR_2BYTE       (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) \
-				| MASK(C_SIZE) | D_SIZE_2)
-#define MASK_CMD_WR_ADR         (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) \
-				| MASK(A_SIZE))
+#define MASK(bit) (0x1 << (bit))
+#define A_SIZE 0x03 /* 0: No ADR field 1: 3-bytes ADR field */
+#define C_SIZE 0x04 /* 0: 1-Byte CMD field 1:No CMD field */
+#define RD_WR 0x05 /* 0: Read 1: Write */
+#define DEV_NUM 0x06 /* 0: PVT is used 1: SHD is used */
+#define EXEC_DONE 0x07
+#define D_SIZE_1 0x01
+#define D_SIZE_2 0x02
+#define D_SIZE_3 0x03
+#define D_SIZE_4 0x04
+#define FLASH_SEL MASK(DEV_NUM)
+
+#define MASK_CMD_ONLY (MASK(EXEC_DONE) | FLASH_SEL)
+#define MASK_CMD_ADR (MASK(EXEC_DONE) | FLASH_SEL | MASK(A_SIZE))
+#define MASK_CMD_ADR_WR \
+	(MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) | MASK(A_SIZE) | D_SIZE_1)
+#define MASK_RD_1BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_1)
+#define MASK_RD_2BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_2)
+#define MASK_RD_3BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_3)
+#define MASK_RD_4BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_4)
+#define MASK_CMD_RD_1BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_1)
+#define MASK_CMD_RD_2BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_2)
+#define MASK_CMD_RD_3BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_3)
+#define MASK_CMD_RD_4BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_4)
+#define MASK_CMD_WR_ONLY (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR))
+#define MASK_CMD_WR_1BYTE \
+	(MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) | MASK(C_SIZE) | D_SIZE_1)
+#define MASK_CMD_WR_2BYTE \
+	(MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) | MASK(C_SIZE) | D_SIZE_2)
+#define MASK_CMD_WR_ADR \
+	(MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) | MASK(A_SIZE))
 
 /******************************************************************************/
 /* APM (Audio Processing Module) Registers */
-#define NPCX_APM_SR                 REG8(NPCX_APM_BASE_ADDR + 0x000)
-#define NPCX_APM_SR2                REG8(NPCX_APM_BASE_ADDR + 0x004)
-#define NPCX_APM_ICR                REG8(NPCX_APM_BASE_ADDR + 0x008)
-#define NPCX_APM_IMR                REG8(NPCX_APM_BASE_ADDR + 0x00C)
-#define NPCX_APM_IFR                REG8(NPCX_APM_BASE_ADDR + 0x010)
-#define NPCX_APM_CR_APM             REG8(NPCX_APM_BASE_ADDR + 0x014)
-#define NPCX_APM_CR_CK              REG8(NPCX_APM_BASE_ADDR + 0x018)
-#define NPCX_APM_AICR_ADC           REG8(NPCX_APM_BASE_ADDR + 0x01C)
-#define NPCX_APM_FCR_ADC            REG8(NPCX_APM_BASE_ADDR + 0x020)
-#define NPCX_APM_CR_DMIC            REG8(NPCX_APM_BASE_ADDR + 0x02C)
-#define NPCX_APM_CR_ADC             REG8(NPCX_APM_BASE_ADDR + 0x030)
-#define NPCX_APM_CR_MIX             REG8(NPCX_APM_BASE_ADDR + 0x034)
-#define NPCX_APM_DR_MIX             REG8(NPCX_APM_BASE_ADDR + 0x038)
-#define NPCX_APM_GCR_ADCL           REG8(NPCX_APM_BASE_ADDR + 0x03C)
-#define NPCX_APM_GCR_ADCR           REG8(NPCX_APM_BASE_ADDR + 0x040)
-#define NPCX_APM_GCR_MIXADCL        REG8(NPCX_APM_BASE_ADDR + 0x044)
-#define NPCX_APM_GCR_MIXADCR        REG8(NPCX_APM_BASE_ADDR + 0x048)
-#define NPCX_APM_CR_ADC_AGC         REG8(NPCX_APM_BASE_ADDR + 0x04C)
-#define NPCX_APM_DR_ADC_AGC         REG8(NPCX_APM_BASE_ADDR + 0x050)
-#define NPCX_APM_SR_ADC_AGCDGL      REG8(NPCX_APM_BASE_ADDR + 0x054)
-#define NPCX_APM_SR_ADC_AGCDGR      REG8(NPCX_APM_BASE_ADDR + 0x058)
-#define NPCX_APM_CR_VAD             REG8(NPCX_APM_BASE_ADDR + 0x05C)
-#define NPCX_APM_DR_VAD             REG8(NPCX_APM_BASE_ADDR + 0x060)
-#define NPCX_APM_CR_VAD_CMD         REG8(NPCX_APM_BASE_ADDR + 0x064)
-#define NPCX_APM_CR_TR              REG8(NPCX_APM_BASE_ADDR + 0x068)
-#define NPCX_APM_DR_TR              REG8(NPCX_APM_BASE_ADDR + 0x06C)
-#define NPCX_APM_SR_TR1             REG8(NPCX_APM_BASE_ADDR + 0x070)
-#define NPCX_APM_SR_TR_SRCADC       REG8(NPCX_APM_BASE_ADDR + 0x074)
+#define NPCX_APM_SR REG8(NPCX_APM_BASE_ADDR + 0x000)
+#define NPCX_APM_SR2 REG8(NPCX_APM_BASE_ADDR + 0x004)
+#define NPCX_APM_ICR REG8(NPCX_APM_BASE_ADDR + 0x008)
+#define NPCX_APM_IMR REG8(NPCX_APM_BASE_ADDR + 0x00C)
+#define NPCX_APM_IFR REG8(NPCX_APM_BASE_ADDR + 0x010)
+#define NPCX_APM_CR_APM REG8(NPCX_APM_BASE_ADDR + 0x014)
+#define NPCX_APM_CR_CK REG8(NPCX_APM_BASE_ADDR + 0x018)
+#define NPCX_APM_AICR_ADC REG8(NPCX_APM_BASE_ADDR + 0x01C)
+#define NPCX_APM_FCR_ADC REG8(NPCX_APM_BASE_ADDR + 0x020)
+#define NPCX_APM_CR_DMIC REG8(NPCX_APM_BASE_ADDR + 0x02C)
+#define NPCX_APM_CR_ADC REG8(NPCX_APM_BASE_ADDR + 0x030)
+#define NPCX_APM_CR_MIX REG8(NPCX_APM_BASE_ADDR + 0x034)
+#define NPCX_APM_DR_MIX REG8(NPCX_APM_BASE_ADDR + 0x038)
+#define NPCX_APM_GCR_ADCL REG8(NPCX_APM_BASE_ADDR + 0x03C)
+#define NPCX_APM_GCR_ADCR REG8(NPCX_APM_BASE_ADDR + 0x040)
+#define NPCX_APM_GCR_MIXADCL REG8(NPCX_APM_BASE_ADDR + 0x044)
+#define NPCX_APM_GCR_MIXADCR REG8(NPCX_APM_BASE_ADDR + 0x048)
+#define NPCX_APM_CR_ADC_AGC REG8(NPCX_APM_BASE_ADDR + 0x04C)
+#define NPCX_APM_DR_ADC_AGC REG8(NPCX_APM_BASE_ADDR + 0x050)
+#define NPCX_APM_SR_ADC_AGCDGL REG8(NPCX_APM_BASE_ADDR + 0x054)
+#define NPCX_APM_SR_ADC_AGCDGR REG8(NPCX_APM_BASE_ADDR + 0x058)
+#define NPCX_APM_CR_VAD REG8(NPCX_APM_BASE_ADDR + 0x05C)
+#define NPCX_APM_DR_VAD REG8(NPCX_APM_BASE_ADDR + 0x060)
+#define NPCX_APM_CR_VAD_CMD REG8(NPCX_APM_BASE_ADDR + 0x064)
+#define NPCX_APM_CR_TR REG8(NPCX_APM_BASE_ADDR + 0x068)
+#define NPCX_APM_DR_TR REG8(NPCX_APM_BASE_ADDR + 0x06C)
+#define NPCX_APM_SR_TR1 REG8(NPCX_APM_BASE_ADDR + 0x070)
+#define NPCX_APM_SR_TR_SRCADC REG8(NPCX_APM_BASE_ADDR + 0x074)
 
 /******************************************************************************/
 /* APM register fields */
-#define NPCX_APM_SR_IRQ_PEND                    6
-#define NPCX_APM_SR2_SMUTEIP                    6
-#define NPCX_APM_ICR_INTR_MODE                  FIELD(6, 2)
-#define NPCX_APM_IMR_VAD_DTC_MASK               6
-#define NPCX_APM_IFR_VAD_DTC                    6
-#define NPCX_APM_CR_APM_PD                      0
-#define NPCX_APM_CR_APM_AGC_DIS                 FIELD(1, 2)
-#define NPCX_APM_CR_CK_MCLK_FREQ                FIELD(0, 2)
-#define NPCX_APM_AICR_ADC_ADC_AUDIOIF           FIELD(0, 2)
-#define NPCX_APM_AICR_ADC_PD_AICR_ADC           4
-#define NPCX_APM_AICR_ADC_ADC_ADWL              FIELD(6, 2)
-#define NPCX_APM_FCR_ADC_ADC_FREQ               FIELD(0, 4)
-#define NPCX_APM_FCR_ADC_ADC_WNF                FIELD(4, 2)
-#define NPCX_APM_FCR_ADC_ADC_HPF                6
-#define NPCX_APM_CR_DMIC_ADC_DMIC_SEL_RIGHT     FIELD(0, 2)
-#define NPCX_APM_CR_DMIC_ADC_DMIC_SEL_LEFT      FIELD(2, 2)
-#define NPCX_APM_CR_DMIC_ADC_DMIC_RATE          FIELD(4, 3)
-#define NPCX_APM_CR_DMIC_PD_DMIC                7
-#define NPCX_APM_CR_ADC_ADC_SOFT_MUTE           7
-#define NPCX_APM_CR_MIX_MIX_ADD                 FIELD(0, 6)
-#define NPCX_APM_CR_MIX_MIX_LOAD                6
-#define NPCX_APM_DR_MIX_MIX_DATA                FIELD(0, 8)
-#define NPCX_APM_MIX_2_AIADCR_SEL               FIELD(4, 2)
-#define NPCX_APM_MIX_2_AIADCL_SEL               FIELD(6, 2)
-#define NPCX_APM_GCR_ADCL_GIDL                  FIELD(0, 6)
-#define NPCX_APM_GCR_ADCL_LRGID                 7
-#define NPCX_APM_GCR_ADCR_GIDR                  FIELD(0, 6)
-#define NPCX_APM_GCR_MIXADCL_GIMIXL             FIELD(0, 6)
-#define NPCX_APM_GCR_MIXADCR_GIMIXR             FIELD(0, 6)
-#define NPCX_APM_CR_ADC_AGC_ADC_AGC_ADD         FIELD(0, 6)
-#define NPCX_APM_CR_ADC_AGC_ADC_AGC_LOAD        6
-#define NPCX_APM_CR_ADC_AGC_ADC_AGC_EN          7
-#define NPCX_APM_DR_ADC_AGC_ADC_AGC_DATA        FIELD(0, 8)
-#define NPCX_ADC_AGC_0_AGC_TARGET               FIELD(2, 4)
-#define NPCX_ADC_AGC_0_AGC_STEREO               6
-#define NPCX_ADC_AGC_1_HOLD                     FIELD(0, 4)
-#define NPCX_ADC_AGC_1_NG_THR                   FIELD(4, 3)
-#define NPCX_ADC_AGC_1_NG_EN                    7
-#define NPCX_ADC_AGC_2_DCY                      FIELD(0, 4)
-#define NPCX_ADC_AGC_2_ATK                      FIELD(4, 4)
-#define NPCX_ADC_AGC_3_AGC_MAX                  FIELD(0, 5)
-#define NPCX_ADC_AGC_4_AGC_MIN                  FIELD(0, 5)
-#define NPCX_APM_CR_VAD_VAD_ADD                 FIELD(0, 6)
-#define NPCX_APM_CR_VAD_VAD_LOAD                6
-#define NPCX_APM_CR_VAD_VAD_EN                  7
-#define NPCX_APM_DR_VAD_VAD_DATA                FIELD(0, 8)
-#define NPCX_APM_CR_VAD_CMD_VAD_RESTART         0
-#define NPCX_APM_CR_TR_FAST_ON                  7
-#define NPCX_VAD_0_VAD_INSEL                    FIELD(0, 2)
-#define NPCX_VAD_0_VAD_DMIC_FREQ                FIELD(2, 3)
-#define NPCX_VAD_0_VAD_ADC_WAKEUP               5
-#define NPCX_VAD_0_ZCD_EN                       6
-#define NPCX_VAD_1_VAD_POWER_SENS               FIELD(0, 5)
-#define NPCX_APM_CONTROL_ADD                    FIELD(0, 6)
-#define NPCX_APM_CONTROL_LOAD                   6
+#define NPCX_APM_SR_IRQ_PEND 6
+#define NPCX_APM_SR2_SMUTEIP 6
+#define NPCX_APM_ICR_INTR_MODE FIELD(6, 2)
+#define NPCX_APM_IMR_VAD_DTC_MASK 6
+#define NPCX_APM_IFR_VAD_DTC 6
+#define NPCX_APM_CR_APM_PD 0
+#define NPCX_APM_CR_APM_AGC_DIS FIELD(1, 2)
+#define NPCX_APM_CR_CK_MCLK_FREQ FIELD(0, 2)
+#define NPCX_APM_AICR_ADC_ADC_AUDIOIF FIELD(0, 2)
+#define NPCX_APM_AICR_ADC_PD_AICR_ADC 4
+#define NPCX_APM_AICR_ADC_ADC_ADWL FIELD(6, 2)
+#define NPCX_APM_FCR_ADC_ADC_FREQ FIELD(0, 4)
+#define NPCX_APM_FCR_ADC_ADC_WNF FIELD(4, 2)
+#define NPCX_APM_FCR_ADC_ADC_HPF 6
+#define NPCX_APM_CR_DMIC_ADC_DMIC_SEL_RIGHT FIELD(0, 2)
+#define NPCX_APM_CR_DMIC_ADC_DMIC_SEL_LEFT FIELD(2, 2)
+#define NPCX_APM_CR_DMIC_ADC_DMIC_RATE FIELD(4, 3)
+#define NPCX_APM_CR_DMIC_PD_DMIC 7
+#define NPCX_APM_CR_ADC_ADC_SOFT_MUTE 7
+#define NPCX_APM_CR_MIX_MIX_ADD FIELD(0, 6)
+#define NPCX_APM_CR_MIX_MIX_LOAD 6
+#define NPCX_APM_DR_MIX_MIX_DATA FIELD(0, 8)
+#define NPCX_APM_MIX_2_AIADCR_SEL FIELD(4, 2)
+#define NPCX_APM_MIX_2_AIADCL_SEL FIELD(6, 2)
+#define NPCX_APM_GCR_ADCL_GIDL FIELD(0, 6)
+#define NPCX_APM_GCR_ADCL_LRGID 7
+#define NPCX_APM_GCR_ADCR_GIDR FIELD(0, 6)
+#define NPCX_APM_GCR_MIXADCL_GIMIXL FIELD(0, 6)
+#define NPCX_APM_GCR_MIXADCR_GIMIXR FIELD(0, 6)
+#define NPCX_APM_CR_ADC_AGC_ADC_AGC_ADD FIELD(0, 6)
+#define NPCX_APM_CR_ADC_AGC_ADC_AGC_LOAD 6
+#define NPCX_APM_CR_ADC_AGC_ADC_AGC_EN 7
+#define NPCX_APM_DR_ADC_AGC_ADC_AGC_DATA FIELD(0, 8)
+#define NPCX_ADC_AGC_0_AGC_TARGET FIELD(2, 4)
+#define NPCX_ADC_AGC_0_AGC_STEREO 6
+#define NPCX_ADC_AGC_1_HOLD FIELD(0, 4)
+#define NPCX_ADC_AGC_1_NG_THR FIELD(4, 3)
+#define NPCX_ADC_AGC_1_NG_EN 7
+#define NPCX_ADC_AGC_2_DCY FIELD(0, 4)
+#define NPCX_ADC_AGC_2_ATK FIELD(4, 4)
+#define NPCX_ADC_AGC_3_AGC_MAX FIELD(0, 5)
+#define NPCX_ADC_AGC_4_AGC_MIN FIELD(0, 5)
+#define NPCX_APM_CR_VAD_VAD_ADD FIELD(0, 6)
+#define NPCX_APM_CR_VAD_VAD_LOAD 6
+#define NPCX_APM_CR_VAD_VAD_EN 7
+#define NPCX_APM_DR_VAD_VAD_DATA FIELD(0, 8)
+#define NPCX_APM_CR_VAD_CMD_VAD_RESTART 0
+#define NPCX_APM_CR_TR_FAST_ON 7
+#define NPCX_VAD_0_VAD_INSEL FIELD(0, 2)
+#define NPCX_VAD_0_VAD_DMIC_FREQ FIELD(2, 3)
+#define NPCX_VAD_0_VAD_ADC_WAKEUP 5
+#define NPCX_VAD_0_ZCD_EN 6
+#define NPCX_VAD_1_VAD_POWER_SENS FIELD(0, 5)
+#define NPCX_APM_CONTROL_ADD FIELD(0, 6)
+#define NPCX_APM_CONTROL_LOAD 6
 
 /******************************************************************************/
 /* FMUL2 (Frequency Multiplier Module 2) Registers */
-#define NPCX_FMUL2_FM2CTRL          REG8(NPCX_FMUL2_BASE_ADDR + 0x000)
-#define NPCX_FMUL2_FM2ML            REG8(NPCX_FMUL2_BASE_ADDR + 0x002)
-#define NPCX_FMUL2_FM2MH            REG8(NPCX_FMUL2_BASE_ADDR + 0x004)
-#define NPCX_FMUL2_FM2N             REG8(NPCX_FMUL2_BASE_ADDR + 0x006)
-#define NPCX_FMUL2_FM2P             REG8(NPCX_FMUL2_BASE_ADDR + 0x008)
-#define NPCX_FMUL2_FM2_VER          REG8(NPCX_FMUL2_BASE_ADDR + 0x00A)
+#define NPCX_FMUL2_FM2CTRL REG8(NPCX_FMUL2_BASE_ADDR + 0x000)
+#define NPCX_FMUL2_FM2ML REG8(NPCX_FMUL2_BASE_ADDR + 0x002)
+#define NPCX_FMUL2_FM2MH REG8(NPCX_FMUL2_BASE_ADDR + 0x004)
+#define NPCX_FMUL2_FM2N REG8(NPCX_FMUL2_BASE_ADDR + 0x006)
+#define NPCX_FMUL2_FM2P REG8(NPCX_FMUL2_BASE_ADDR + 0x008)
+#define NPCX_FMUL2_FM2_VER REG8(NPCX_FMUL2_BASE_ADDR + 0x00A)
 
 /******************************************************************************/
 /* FMUL2 register fields */
-#define NPCX_FMUL2_FM2CTRL_LOAD2                0
-#define NPCX_FMUL2_FM2CTRL_LOCK2                2
-#define NPCX_FMUL2_FM2CTRL_FMUL2_DIS            5
-#define NPCX_FMUL2_FM2CTRL_TUNE_DIS             6
-#define NPCX_FMUL2_FM2CTRL_CLK2_CHNG            7
-#define NPCX_FMUL2_FM2N_FM2N                    FIELD(0, 6)
-#define NPCX_FMUL2_FM2P_WFPRED                  FIELD(4, 4)
+#define NPCX_FMUL2_FM2CTRL_LOAD2 0
+#define NPCX_FMUL2_FM2CTRL_LOCK2 2
+#define NPCX_FMUL2_FM2CTRL_FMUL2_DIS 5
+#define NPCX_FMUL2_FM2CTRL_TUNE_DIS 6
+#define NPCX_FMUL2_FM2CTRL_CLK2_CHNG 7
+#define NPCX_FMUL2_FM2N_FM2N FIELD(0, 6)
+#define NPCX_FMUL2_FM2P_WFPRED FIELD(4, 4)
 
 /******************************************************************************/
 /* WOV (Wake-on-Voice) Registers */
-#define NPCX_WOV_CLOCK_CNTL         REG32(NPCX_WOV_BASE_ADDR + 0x000)
-#define NPCX_WOV_PLL_CNTL1          REG32(NPCX_WOV_BASE_ADDR + 0x004)
-#define NPCX_WOV_PLL_CNTL2          REG32(NPCX_WOV_BASE_ADDR + 0x008)
-#define NPCX_WOV_FIFO_CNT           REG32(NPCX_WOV_BASE_ADDR + 0x00C)
-#define NPCX_WOV_FIFO_OUT           REG32(NPCX_WOV_BASE_ADDR + 0x010)
-#define NPCX_WOV_STATUS             REG32(NPCX_WOV_BASE_ADDR + 0x014)
-#define NPCX_WOV_WOV_INTEN          REG32(NPCX_WOV_BASE_ADDR + 0x018)
-#define NPCX_WOV_APM_CTRL           REG32(NPCX_WOV_BASE_ADDR + 0x01C)
-#define NPCX_WOV_I2S_CNTL(n)        REG32(NPCX_WOV_BASE_ADDR + 0x020 + (4*n))
-#define NPCX_WOV_VERSION            REG32(NPCX_WOV_BASE_ADDR + 0x030)
+#define NPCX_WOV_CLOCK_CNTL REG32(NPCX_WOV_BASE_ADDR + 0x000)
+#define NPCX_WOV_PLL_CNTL1 REG32(NPCX_WOV_BASE_ADDR + 0x004)
+#define NPCX_WOV_PLL_CNTL2 REG32(NPCX_WOV_BASE_ADDR + 0x008)
+#define NPCX_WOV_FIFO_CNT REG32(NPCX_WOV_BASE_ADDR + 0x00C)
+#define NPCX_WOV_FIFO_OUT REG32(NPCX_WOV_BASE_ADDR + 0x010)
+#define NPCX_WOV_STATUS REG32(NPCX_WOV_BASE_ADDR + 0x014)
+#define NPCX_WOV_WOV_INTEN REG32(NPCX_WOV_BASE_ADDR + 0x018)
+#define NPCX_WOV_APM_CTRL REG32(NPCX_WOV_BASE_ADDR + 0x01C)
+#define NPCX_WOV_I2S_CNTL(n) REG32(NPCX_WOV_BASE_ADDR + 0x020 + (4 * n))
+#define NPCX_WOV_VERSION REG32(NPCX_WOV_BASE_ADDR + 0x030)
 
 /******************************************************************************/
 /* WOV register fields */
-#define NPCX_WOV_CLOCK_CNT_CLK_SEL              0
-#define NPCX_WOV_CLOCK_CNT_DMIC_EN              3
-#define NPCX_WOV_CLOCK_CNT_PLL_EDIV_SEL         7
-#define NPCX_WOV_CLOCK_CNT_PLL_EDIV             FIELD(8, 7)
-#define NPCX_WOV_CLOCK_CNT_PLL_EDIV_DC          FIELD(16, 7)
-#define NPCX_WOV_CLOCK_CNT_DMIC_CKDIV_EN        24
-#define NPCX_WOV_CLOCK_CNT_DMIC_CKDIV_SEL       25
-#define NPCX_WOV_FIFO_CNT_FIFO_ITHRSH           FIELD(0, 6)
-#define NPCX_WOV_FIFO_CNT_FIFO_WTHRSH           FIELD(6, 6)
-#define NPCX_WOV_FIFO_CNT_I2S_FFRST             13
-#define NPCX_WOV_FIFO_CNT_CORE_FFRST            14
-#define NPCX_WOV_FIFO_CNT_CFIFO_ISEL            FIELD(16, 3)
-#define NPCX_WOV_STATUS_CFIFO_CNT               FIELD(0, 8)
-#define NPCX_WOV_STATUS_CFIFO_NE                8
-#define NPCX_WOV_STATUS_CFIFO_OIT               9
-#define NPCX_WOV_STATUS_CFIFO_OWT               10
-#define NPCX_WOV_STATUS_CFIFO_OVRN              11
-#define NPCX_WOV_STATUS_I2S_FIFO_OVRN           12
-#define NPCX_WOV_STATUS_I2S_FIFO_UNDRN          13
-#define NPCX_WOV_STATUS_BITS			FIELD(9, 6)
-#define NPCX_WOV_INTEN_VAD_INTEN                0
-#define NPCX_WOV_INTEN_VAD_WKEN                 1
-#define NPCX_WOV_INTEN_CFIFO_NE_IE              8
-#define NPCX_WOV_INTEN_CFIFO_OIT_IE             9
-#define NPCX_WOV_INTEN_CFIFO_OWT_WE             10
-#define NPCX_WOV_INTEN_CFIFO_OVRN_IE            11
-#define NPCX_WOV_INTEN_I2S_FIFO_OVRN_IE         12
-#define NPCX_WOV_INTEN_I2S_FIFO_UNDRN_IE        13
-#define NPCX_WOV_APM_CTRL_APM_RST               0
-#define NPCX_WOV_PLL_CNTL1_PLL_PWDEN            0
-#define NPCX_WOV_PLL_CNTL1_PLL_OTDV1            FIELD(4, 4)
-#define NPCX_WOV_PLL_CNTL1_PLL_OTDV2            FIELD(8, 4)
-#define NPCX_WOV_PLL_CNTL1_PLL_LOCKI            15
-#define NPCX_WOV_PLL_CNTL2_PLL_FBDV             FIELD(0, 12)
-#define NPCX_WOV_PLL_CNTL2_PLL_INDV             FIELD(12, 4)
-#define NPCX_WOV_I2S_CNTL_I2S_BCNT              FIELD(0, 5)
-#define NPCX_WOV_I2S_CNTL_I2S_TRIG              5
-#define NPCX_WOV_I2S_CNTL_I2S_LBHIZ             6
-#define NPCX_WOV_I2S_CNTL_I2S_ST_DEL            FIELD(7, 9)
-#define NPCX_WOV_I2S_CNTL_I2S_CHAN              FIELD(0, 16)
-#define NPCX_WOV_I2S_CNTL0_I2S_HIZD             16
-#define NPCX_WOV_I2S_CNTL0_I2S_HIZ              17
-#define NPCX_WOV_I2S_CNTL0_I2S_SCLK_INV         18
-#define NPCX_WOV_I2S_CNTL0_I2S_OPS              19
-#define NPCX_WOV_I2S_CNTL0_I2S_OPE              20
-#define NPCX_WOV_I2S_CNTL0_I2S_IPS              21
-#define NPCX_WOV_I2S_CNTL0_I2S_IPE              22
-#define NPCX_WOV_I2S_CNTL0_I2S_TST              23
-#define NPCX_WOV_I2S_CNTL1_I2S_CHN1_DIS         24
+#define NPCX_WOV_CLOCK_CNT_CLK_SEL 0
+#define NPCX_WOV_CLOCK_CNT_DMIC_EN 3
+#define NPCX_WOV_CLOCK_CNT_PLL_EDIV_SEL 7
+#define NPCX_WOV_CLOCK_CNT_PLL_EDIV FIELD(8, 7)
+#define NPCX_WOV_CLOCK_CNT_PLL_EDIV_DC FIELD(16, 7)
+#define NPCX_WOV_CLOCK_CNT_DMIC_CKDIV_EN 24
+#define NPCX_WOV_CLOCK_CNT_DMIC_CKDIV_SEL 25
+#define NPCX_WOV_FIFO_CNT_FIFO_ITHRSH FIELD(0, 6)
+#define NPCX_WOV_FIFO_CNT_FIFO_WTHRSH FIELD(6, 6)
+#define NPCX_WOV_FIFO_CNT_I2S_FFRST 13
+#define NPCX_WOV_FIFO_CNT_CORE_FFRST 14
+#define NPCX_WOV_FIFO_CNT_CFIFO_ISEL FIELD(16, 3)
+#define NPCX_WOV_STATUS_CFIFO_CNT FIELD(0, 8)
+#define NPCX_WOV_STATUS_CFIFO_NE 8
+#define NPCX_WOV_STATUS_CFIFO_OIT 9
+#define NPCX_WOV_STATUS_CFIFO_OWT 10
+#define NPCX_WOV_STATUS_CFIFO_OVRN 11
+#define NPCX_WOV_STATUS_I2S_FIFO_OVRN 12
+#define NPCX_WOV_STATUS_I2S_FIFO_UNDRN 13
+#define NPCX_WOV_STATUS_BITS FIELD(9, 6)
+#define NPCX_WOV_INTEN_VAD_INTEN 0
+#define NPCX_WOV_INTEN_VAD_WKEN 1
+#define NPCX_WOV_INTEN_CFIFO_NE_IE 8
+#define NPCX_WOV_INTEN_CFIFO_OIT_IE 9
+#define NPCX_WOV_INTEN_CFIFO_OWT_WE 10
+#define NPCX_WOV_INTEN_CFIFO_OVRN_IE 11
+#define NPCX_WOV_INTEN_I2S_FIFO_OVRN_IE 12
+#define NPCX_WOV_INTEN_I2S_FIFO_UNDRN_IE 13
+#define NPCX_WOV_APM_CTRL_APM_RST 0
+#define NPCX_WOV_PLL_CNTL1_PLL_PWDEN 0
+#define NPCX_WOV_PLL_CNTL1_PLL_OTDV1 FIELD(4, 4)
+#define NPCX_WOV_PLL_CNTL1_PLL_OTDV2 FIELD(8, 4)
+#define NPCX_WOV_PLL_CNTL1_PLL_LOCKI 15
+#define NPCX_WOV_PLL_CNTL2_PLL_FBDV FIELD(0, 12)
+#define NPCX_WOV_PLL_CNTL2_PLL_INDV FIELD(12, 4)
+#define NPCX_WOV_I2S_CNTL_I2S_BCNT FIELD(0, 5)
+#define NPCX_WOV_I2S_CNTL_I2S_TRIG 5
+#define NPCX_WOV_I2S_CNTL_I2S_LBHIZ 6
+#define NPCX_WOV_I2S_CNTL_I2S_ST_DEL FIELD(7, 9)
+#define NPCX_WOV_I2S_CNTL_I2S_CHAN FIELD(0, 16)
+#define NPCX_WOV_I2S_CNTL0_I2S_HIZD 16
+#define NPCX_WOV_I2S_CNTL0_I2S_HIZ 17
+#define NPCX_WOV_I2S_CNTL0_I2S_SCLK_INV 18
+#define NPCX_WOV_I2S_CNTL0_I2S_OPS 19
+#define NPCX_WOV_I2S_CNTL0_I2S_OPE 20
+#define NPCX_WOV_I2S_CNTL0_I2S_IPS 21
+#define NPCX_WOV_I2S_CNTL0_I2S_IPE 22
+#define NPCX_WOV_I2S_CNTL0_I2S_TST 23
+#define NPCX_WOV_I2S_CNTL1_I2S_CHN1_DIS 24
 
 /******************************************************************************/
 /* PS/2 registers */
-#define NPCX_PS2_PSDAT                   REG8(NPCX_PS2_BASE_ADDR + 0x000)
-#define NPCX_PS2_PSTAT                   REG8(NPCX_PS2_BASE_ADDR + 0x002)
-#define NPCX_PS2_PSCON                   REG8(NPCX_PS2_BASE_ADDR + 0x004)
-#define NPCX_PS2_PSOSIG                  REG8(NPCX_PS2_BASE_ADDR + 0x006)
-#define NPCX_PS2_PSISIG                  REG8(NPCX_PS2_BASE_ADDR + 0x008)
-#define NPCX_PS2_PSIEN                   REG8(NPCX_PS2_BASE_ADDR + 0x00A)
+#define NPCX_PS2_PSDAT REG8(NPCX_PS2_BASE_ADDR + 0x000)
+#define NPCX_PS2_PSTAT REG8(NPCX_PS2_BASE_ADDR + 0x002)
+#define NPCX_PS2_PSCON REG8(NPCX_PS2_BASE_ADDR + 0x004)
+#define NPCX_PS2_PSOSIG REG8(NPCX_PS2_BASE_ADDR + 0x006)
+#define NPCX_PS2_PSISIG REG8(NPCX_PS2_BASE_ADDR + 0x008)
+#define NPCX_PS2_PSIEN REG8(NPCX_PS2_BASE_ADDR + 0x00A)
 
 /* PS/2 register field */
-#define NPCX_PS2_PSTAT_SOT               0
-#define NPCX_PS2_PSTAT_EOT               1
-#define NPCX_PS2_PSTAT_PERR              2
-#define NPCX_PS2_PSTAT_ACH               FIELD(3, 3)
-#define NPCX_PS2_PSTAT_RFERR             6
-
-#define NPCX_PS2_PSCON_EN                0
-#define NPCX_PS2_PSCON_XMT               1
-#define NPCX_PS2_PSCON_HDRV              FIELD(2, 2)
-#define NPCX_PS2_PSCON_IDB               FIELD(4, 3)
-#define NPCX_PS2_PSCON_WPUED             7
-
-#define NPCX_PS2_PSOSIG_WDAT0            0
-#define NPCX_PS2_PSOSIG_WDAT1            1
-#define NPCX_PS2_PSOSIG_WDAT2            2
-#define NPCX_PS2_PSOSIG_CLK0             3
-#define NPCX_PS2_PSOSIG_CLK1             4
-#define NPCX_PS2_PSOSIG_CLK2             5
-#define NPCX_PS2_PSOSIG_WDAT3            6
-#define NPCX_PS2_PSOSIG_CLK3             7
-#define NPCX_PS2_PSOSIG_CLK(n)      (((n) < NPCX_PS2_CH3) ? \
-					((n) + 3) : 7)
-#define NPCX_PS2_PSOSIG_WDAT(n)     (((n) < NPCX_PS2_CH3) ? \
-					((n) + 0) : 6)
-#define NPCX_PS2_PSOSIG_CLK_MASK_ALL \
-					(BIT(NPCX_PS2_PSOSIG_CLK0) | \
-					 BIT(NPCX_PS2_PSOSIG_CLK1) | \
-					 BIT(NPCX_PS2_PSOSIG_CLK2) | \
-					 BIT(NPCX_PS2_PSOSIG_CLK3))
-
-#define NPCX_PS2_PSISIG_RDAT0            0
-#define NPCX_PS2_PSISIG_RDAT1            1
-#define NPCX_PS2_PSISIG_RDAT2            2
-#define NPCX_PS2_PSISIG_RCLK0            3
-#define NPCX_PS2_PSISIG_RCLK1            4
-#define NPCX_PS2_PSISIG_RCLK2            5
-#define NPCX_PS2_PSISIG_RDAT3            6
-#define NPCX_PS2_PSISIG_RCLK3            7
-#define NPCX_PS2_PSIEN_SOTIE             0
-#define NPCX_PS2_PSIEN_EOTIE             1
-#define NPCX_PS2_PSIEN_PS2_WUE           4
-#define NPCX_PS2_PSIEN_PS2_CLK_SEL	     7
+#define NPCX_PS2_PSTAT_SOT 0
+#define NPCX_PS2_PSTAT_EOT 1
+#define NPCX_PS2_PSTAT_PERR 2
+#define NPCX_PS2_PSTAT_ACH FIELD(3, 3)
+#define NPCX_PS2_PSTAT_RFERR 6
+
+#define NPCX_PS2_PSCON_EN 0
+#define NPCX_PS2_PSCON_XMT 1
+#define NPCX_PS2_PSCON_HDRV FIELD(2, 2)
+#define NPCX_PS2_PSCON_IDB FIELD(4, 3)
+#define NPCX_PS2_PSCON_WPUED 7
+
+#define NPCX_PS2_PSOSIG_WDAT0 0
+#define NPCX_PS2_PSOSIG_WDAT1 1
+#define NPCX_PS2_PSOSIG_WDAT2 2
+#define NPCX_PS2_PSOSIG_CLK0 3
+#define NPCX_PS2_PSOSIG_CLK1 4
+#define NPCX_PS2_PSOSIG_CLK2 5
+#define NPCX_PS2_PSOSIG_WDAT3 6
+#define NPCX_PS2_PSOSIG_CLK3 7
+#define NPCX_PS2_PSOSIG_CLK(n) (((n) < NPCX_PS2_CH3) ? ((n) + 3) : 7)
+#define NPCX_PS2_PSOSIG_WDAT(n) (((n) < NPCX_PS2_CH3) ? ((n) + 0) : 6)
+#define NPCX_PS2_PSOSIG_CLK_MASK_ALL                             \
+	(BIT(NPCX_PS2_PSOSIG_CLK0) | BIT(NPCX_PS2_PSOSIG_CLK1) | \
+	 BIT(NPCX_PS2_PSOSIG_CLK2) | BIT(NPCX_PS2_PSOSIG_CLK3))
+
+#define NPCX_PS2_PSISIG_RDAT0 0
+#define NPCX_PS2_PSISIG_RDAT1 1
+#define NPCX_PS2_PSISIG_RDAT2 2
+#define NPCX_PS2_PSISIG_RCLK0 3
+#define NPCX_PS2_PSISIG_RCLK1 4
+#define NPCX_PS2_PSISIG_RCLK2 5
+#define NPCX_PS2_PSISIG_RDAT3 6
+#define NPCX_PS2_PSISIG_RCLK3 7
+#define NPCX_PS2_PSIEN_SOTIE 0
+#define NPCX_PS2_PSIEN_EOTIE 1
+#define NPCX_PS2_PSIEN_PS2_WUE 4
+#define NPCX_PS2_PSIEN_PS2_CLK_SEL 7
 
 #ifndef CONFIG_HIBERNATE_WAKE_PINS_DYNAMIC
 extern const enum gpio_signal hibernate_wake_pins[];
diff --git a/chip/npcx/rom_chip.h b/chip/npcx/rom_chip.h
index bb66f95e88..44c9c1a2a4 100644
--- a/chip/npcx/rom_chip.h
+++ b/chip/npcx/rom_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -42,25 +42,23 @@ enum API_RETURN_STATUS_T {
 /*
  * Macro functions of ROM api functions
  */
-#define ADDR_DOWNLOAD_FROM_FLASH (*(volatile uint32_t *) 0x40)
+#define ADDR_DOWNLOAD_FROM_FLASH (*(volatile uint32_t *)0x40)
 #define download_from_flash(src_offset, dest_addr, size, sign, exe_addr, \
-	status) \
-	(((download_from_flash_ptr) ADDR_DOWNLOAD_FROM_FLASH) \
-	(src_offset, dest_addr, size, sign, exe_addr, status))
+			    status)                                      \
+	(((download_from_flash_ptr)ADDR_DOWNLOAD_FROM_FLASH)(            \
+		src_offset, dest_addr, size, sign, exe_addr, status))
 
 /******************************************************************************/
 /*
  * Declarations of ROM api functions
  */
-typedef void (*download_from_flash_ptr) (
+typedef void (*download_from_flash_ptr)(
 	uint32_t src_offset, /* The offset of the data to be downloaded */
-	uint32_t dest_addr,  /* The address of the downloaded data in the RAM*/
-	uint32_t size,       /* Number of bytes to download */
+	uint32_t dest_addr, /* The address of the downloaded data in the RAM*/
+	uint32_t size, /* Number of bytes to download */
 	enum API_SIGN_OPTIONS_T sign, /* Need CRC check or not */
 	uint32_t exe_addr, /* jump to this address after download if not zero */
 	enum API_RETURN_STATUS_T *status /* Status fo download */
 );
 
-
-
 #endif /* __CROS_EC_ROM_CHIP_H_ */
diff --git a/chip/npcx/sha256_chip.c b/chip/npcx/sha256_chip.c
index 6d2d938895..e2590cad65 100644
--- a/chip/npcx/sha256_chip.c
+++ b/chip/npcx/sha256_chip.c
@@ -1,10 +1,11 @@
 /*
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* SHA256 module for Chrome EC */
+#include "builtin/assert.h"
 #include "common.h"
 #include "sha256.h"
 #include "util.h"
@@ -31,7 +32,7 @@ enum ncl_sha_type {
  * The base address of the table that holds the function pointer for each
  * SHA256 API in ROM.
  */
-#define NCL_SHA_BASE_ADDR          0x00000100UL
+#define NCL_SHA_BASE_ADDR 0x00000100UL
 struct ncl_sha {
 	/* Get the SHA context size required by SHA APIs. */
 	uint32_t (*get_context_size)(void);
@@ -57,7 +58,8 @@ struct ncl_sha {
 	enum ncl_status (*finish)(void *ctx, uint8_t *hashDigest);
 	/* Perform a complete SHA calculation */
 	enum ncl_status (*calc)(void *ctx, enum ncl_sha_type type,
-			const uint8_t *data, uint32_t Len, uint8_t *hashDigest);
+				const uint8_t *data, uint32_t Len,
+				uint8_t *hashDigest);
 	/* Power on/off the SHA module. */
 	enum ncl_status (*power)(void *ctx, uint8_t enable);
 	/* Reset the SHA hardware and terminate any in-progress operations. */
@@ -95,9 +97,9 @@ uint8_t *SHA256_final(struct sha256_ctx *ctx)
 	return ctx->buf;
 }
 
-static void hmac_SHA256_step(uint8_t *output, uint8_t mask,
-			const uint8_t *key, const int key_len,
-			const uint8_t *data, const int data_len)
+static void hmac_SHA256_step(uint8_t *output, uint8_t mask, const uint8_t *key,
+			     const int key_len, const uint8_t *data,
+			     const int data_len)
 {
 	struct sha256_ctx hmac_ctx;
 	uint8_t *key_pad = hmac_ctx.buf;
@@ -120,7 +122,7 @@ static void hmac_SHA256_step(uint8_t *output, uint8_t mask,
  * hmac_SHA256_step.
  */
 void hmac_SHA256(uint8_t *output, const uint8_t *key, const int key_len,
-		const uint8_t *message, const int message_len)
+		 const uint8_t *message, const int message_len)
 {
 	/* This code does not support key_len > block_size. */
 	ASSERT(key_len <= SHA256_BLOCK_SIZE);
@@ -137,5 +139,5 @@ void hmac_SHA256(uint8_t *output, const uint8_t *key, const int key_len,
 	 * output = hash(o_key_pad || output)
 	 */
 	hmac_SHA256_step(output, 0x5c, key, key_len, output,
-				SHA256_DIGEST_SIZE);
+			 SHA256_DIGEST_SIZE);
 }
diff --git a/chip/npcx/sha256_chip.h b/chip/npcx/sha256_chip.h
index 3b9586d962..3c7773d112 100644
--- a/chip/npcx/sha256_chip.h
+++ b/chip/npcx/sha256_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,7 +8,7 @@
 
 #include "common.h"
 
-#define NPCX_SHA256_HANDLE_SIZE    212
+#define NPCX_SHA256_HANDLE_SIZE 212
 struct sha256_ctx {
 	/* the context handle required for SHA256 API */
 	uint8_t handle[NPCX_SHA256_HANDLE_SIZE];
@@ -22,4 +22,4 @@ struct sha256_ctx {
 
 void SHA256_abort(struct sha256_ctx *ctx);
 
-#endif  /* __CROS_EC_SHA256_CHIP_H */
+#endif /* __CROS_EC_SHA256_CHIP_H */
diff --git a/chip/npcx/shi.c b/chip/npcx/shi.c
index 48b56d18ef..d5f19c9191 100644
--- a/chip/npcx/shi.c
+++ b/chip/npcx/shi.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,6 +10,7 @@
  * This uses Input/Output buffer to handle SPI transmission and reception.
  */
 
+#include "builtin/assert.h"
 #include "chipset.h"
 #include "clock.h"
 #include "console.h"
@@ -24,8 +25,8 @@
 #include "util.h"
 
 #define CPUTS(outstr) cputs(CC_SPI, outstr)
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SPI, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SPI, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SPI, format, ##args)
 
 #if !(DEBUG_SHI)
 #define DEBUG_CPUTS(...)
@@ -33,39 +34,42 @@
 #define DEBUG_CPRINTF(...)
 #else
 #define DEBUG_CPUTS(outstr) cputs(CC_SPI, outstr)
-#define DEBUG_CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
-#define DEBUG_CPRINTF(format, args...) cprintf(CC_SPI, format, ## args)
+#define DEBUG_CPRINTS(format, args...) cprints(CC_SPI, format, ##args)
+#define DEBUG_CPRINTF(format, args...) cprintf(CC_SPI, format, ##args)
 #endif
 
 /* SHI Bus definition */
 #ifdef NPCX_SHI_V2
-#define SHI_OBUF_FULL_SIZE  128                    /* Full output buffer size */
-#define SHI_IBUF_FULL_SIZE  128                    /* Full input buffer size  */
+#define SHI_OBUF_FULL_SIZE 128 /* Full output buffer size */
+#define SHI_IBUF_FULL_SIZE 128 /* Full input buffer size  */
 /* Configure the IBUFLVL2 = the size of V3 protocol header */
 #define SHI_IBUFLVL2_THRESHOLD (sizeof(struct ec_host_request))
 #else
-#define SHI_OBUF_FULL_SIZE  64                     /* Full output buffer size */
-#define SHI_IBUF_FULL_SIZE  64                     /* Full input buffer size  */
+#define SHI_OBUF_FULL_SIZE 64 /* Full output buffer size */
+#define SHI_IBUF_FULL_SIZE 64 /* Full input buffer size  */
 #endif
-#define SHI_OBUF_HALF_SIZE  (SHI_OBUF_FULL_SIZE/2) /* Half output buffer size */
-#define SHI_IBUF_HALF_SIZE  (SHI_IBUF_FULL_SIZE/2) /* Half input buffer size  */
+#define SHI_OBUF_HALF_SIZE \
+	(SHI_OBUF_FULL_SIZE / 2) /* Half output buffer size */
+#define SHI_IBUF_HALF_SIZE \
+	(SHI_IBUF_FULL_SIZE / 2) /* Half input buffer size  */
 
 /* Start address of SHI output buffer */
-#define SHI_OBUF_START_ADDR  (volatile uint8_t  *)(NPCX_SHI_BASE_ADDR + 0x020)
+#define SHI_OBUF_START_ADDR (volatile uint8_t *)(NPCX_SHI_BASE_ADDR + 0x020)
 /* Middle address of SHI output buffer */
-#define SHI_OBUF_HALF_ADDR   (SHI_OBUF_START_ADDR + SHI_OBUF_HALF_SIZE)
+#define SHI_OBUF_HALF_ADDR (SHI_OBUF_START_ADDR + SHI_OBUF_HALF_SIZE)
 /* Top address of SHI output buffer */
-#define SHI_OBUF_FULL_ADDR   (SHI_OBUF_START_ADDR + SHI_IBUF_FULL_SIZE)
+#define SHI_OBUF_FULL_ADDR (SHI_OBUF_START_ADDR + SHI_IBUF_FULL_SIZE)
 /*
  * Valid offset of SHI output buffer to write.
  * When SIMUL bit is set, IBUFPTR can be used instead of OBUFPTR
  */
-#define SHI_OBUF_VALID_OFFSET ((shi_read_buf_pointer() + \
-			SHI_OUT_PREAMBLE_LENGTH) % SHI_OBUF_FULL_SIZE)
+#define SHI_OBUF_VALID_OFFSET                                 \
+	((shi_read_buf_pointer() + SHI_OUT_PREAMBLE_LENGTH) % \
+	 SHI_OBUF_FULL_SIZE)
 /* Start address of SHI input buffer */
-#define SHI_IBUF_START_ADDR  (&NPCX_IBUF(0))
+#define SHI_IBUF_START_ADDR (&NPCX_IBUF(0))
 /* Current address of SHI input buffer */
-#define SHI_IBUF_CUR_ADDR    (SHI_IBUF_START_ADDR + shi_read_buf_pointer())
+#define SHI_IBUF_CUR_ADDR (SHI_IBUF_START_ADDR + shi_read_buf_pointer())
 
 /*
  * Timeout to wait for SHI request packet
@@ -106,12 +110,11 @@
  */
 #define SHI_PROTO3_OVERHEAD (EC_SPI_PAST_END_LENGTH + EC_SPI_FRAME_START_LENGTH)
 
-
 #ifdef NPCX_SHI_BYPASS_OVER_256B
 /* The boundary which SHI will output invalid data on MISO. */
 #define SHI_BYPASS_BOUNDARY 256
 /* Increase FRAME_START_LENGTH in case shi outputs invalid FRAME_START byte */
-#undef  EC_SPI_FRAME_START_LENGTH
+#undef EC_SPI_FRAME_START_LENGTH
 #define EC_SPI_FRAME_START_LENGTH 2
 #endif
 
@@ -141,10 +144,9 @@ BUILD_ASSERT(SHI_MAX_RESPONSE_SIZE <= SHI_BYPASS_BOUNDARY);
  */
 #define SHI_OUT_START_PAD (4 * (EC_SPI_FRAME_START_LENGTH / 4 + 1))
 #define SHI_OUT_END_PAD (4 * (EC_SPI_PAST_END_LENGTH / 4 + 1))
-static uint8_t out_msg_padded[SHI_OUT_START_PAD +
-			      SHI_MAX_RESPONSE_SIZE +
+static uint8_t out_msg_padded[SHI_OUT_START_PAD + SHI_MAX_RESPONSE_SIZE +
 			      SHI_OUT_END_PAD] __aligned(4);
-static uint8_t * const out_msg =
+static uint8_t *const out_msg =
 	out_msg_padded + SHI_OUT_START_PAD - EC_SPI_FRAME_START_LENGTH;
 static uint8_t in_msg[SHI_MAX_REQUEST_SIZE] __aligned(4);
 
@@ -176,18 +178,18 @@ volatile enum shi_state state;
 
 /* SHI bus parameters */
 struct shi_bus_parameters {
-	uint8_t *rx_msg;          /* Entry pointer of msg rx buffer   */
-	uint8_t *tx_msg;          /* Entry pointer of msg tx buffer   */
+	uint8_t *rx_msg; /* Entry pointer of msg rx buffer   */
+	uint8_t *tx_msg; /* Entry pointer of msg tx buffer   */
 	volatile uint8_t *rx_buf; /* Entry pointer of receive buffer  */
 	volatile uint8_t *tx_buf; /* Entry pointer of transmit buffer */
-	uint16_t sz_received;     /* Size of received data in bytes   */
-	uint16_t sz_sending;      /* Size of sending data in bytes    */
-	uint16_t sz_request;      /* request bytes need to receive    */
-	uint16_t sz_response;     /* response bytes need to receive   */
-	timestamp_t rx_deadline;  /* deadline of receiving            */
-	uint8_t  pre_ibufstat;    /* Previous IBUFSTAT value          */
+	uint16_t sz_received; /* Size of received data in bytes   */
+	uint16_t sz_sending; /* Size of sending data in bytes    */
+	uint16_t sz_request; /* request bytes need to receive    */
+	uint16_t sz_response; /* response bytes need to receive   */
+	timestamp_t rx_deadline; /* deadline of receiving            */
+	uint8_t pre_ibufstat; /* Previous IBUFSTAT value          */
 #ifdef NPCX_SHI_BYPASS_OVER_256B
-	uint16_t bytes_in_256b;   /* Sent bytes in 256 bytes boundary */
+	uint16_t bytes_in_256b; /* Sent bytes in 256 bytes boundary */
 #endif
 } shi_params;
 
@@ -222,7 +224,7 @@ static void shi_send_response_packet(struct host_packet *pkt)
 	interrupt_disable();
 	if (state == SHI_STATE_PROCESSING) {
 		/* Append our past-end byte, which we reserved space for. */
-		((uint8_t *) pkt->response)[pkt->response_size + 0] =
+		((uint8_t *)pkt->response)[pkt->response_size + 0] =
 			EC_SPI_PAST_END;
 
 		/* Computing sending bytes of response */
@@ -266,8 +268,8 @@ void shi_handle_host_package(void)
 		/* Need to receive data from buffer */
 		return;
 	else {
-		uint16_t remain_bytes = shi_params.sz_request
-					- shi_params.sz_received;
+		uint16_t remain_bytes =
+			shi_params.sz_request - shi_params.sz_received;
 
 		/* Read remaining bytes from input buffer directly */
 		if (!shi_read_inbuf_wait(remain_bytes))
@@ -287,7 +289,6 @@ void shi_handle_host_package(void)
 	shi_packet.request_max = sizeof(in_msg);
 	shi_packet.request_size = shi_params.sz_request;
 
-
 #ifdef NPCX_SHI_BYPASS_OVER_256B
 	/* Move FRAME_START to second byte */
 	out_msg[0] = EC_SPI_PROCESSING;
@@ -324,7 +325,7 @@ static void shi_parse_header(void)
 
 	if (in_msg[0] == EC_HOST_REQUEST_VERSION) {
 		/* Protocol version 3 */
-		struct ec_host_request *r = (struct ec_host_request *) in_msg;
+		struct ec_host_request *r = (struct ec_host_request *)in_msg;
 		int pkt_size;
 		/*
 		 * If request is over 32 bytes,
@@ -371,8 +372,8 @@ static void shi_fill_out_status(uint8_t status)
 	 * be done within this gap. No racing happens.
 	 */
 	start = SHI_OBUF_VALID_OFFSET;
-	end = ((start + SHI_OBUF_FULL_SIZE - SHI_OUT_PREAMBLE_LENGTH)
-	       % SHI_OBUF_FULL_SIZE);
+	end = ((start + SHI_OBUF_FULL_SIZE - SHI_OUT_PREAMBLE_LENGTH) %
+	       SHI_OBUF_FULL_SIZE);
 
 	fill_ptr = (uint8_t *)SHI_OBUF_START_ADDR + start;
 	fill_end = (uint8_t *)SHI_OBUF_START_ADDR + end;
@@ -388,17 +389,17 @@ static void shi_fill_out_status(uint8_t status)
 }
 
 #ifdef NPCX_SHI_V2
- /*
-  * This routine configures at which level the Input Buffer Half Full 2(IBHF2))
-  * event triggers an interrupt to core.
-  */
+/*
+ * This routine configures at which level the Input Buffer Half Full 2(IBHF2))
+ * event triggers an interrupt to core.
+ */
 static void shi_sec_ibf_int_enable(int enable)
 {
 	if (enable) {
 		/* Setup IBUFLVL2 threshold and enable it */
 		SET_BIT(NPCX_SHICFG5, NPCX_SHICFG5_IBUFLVL2DIS);
 		SET_FIELD(NPCX_SHICFG5, NPCX_SHICFG5_IBUFLVL2,
-				SHI_IBUFLVL2_THRESHOLD);
+			  SHI_IBUFLVL2_THRESHOLD);
 		CLEAR_BIT(NPCX_SHICFG5, NPCX_SHICFG5_IBUFLVL2DIS);
 		/* Enable IBHF2 event */
 		SET_BIT(NPCX_EVENABLE2, NPCX_EVENABLE2_IBHF2EN);
@@ -436,9 +437,9 @@ static int shi_is_cs_glitch(void)
  */
 static void shi_write_half_outbuf(void)
 {
-	const uint8_t size = MIN(SHI_OBUF_HALF_SIZE,
-				 shi_params.sz_response -
-				 shi_params.sz_sending);
+	const uint8_t size =
+		MIN(SHI_OBUF_HALF_SIZE,
+		    shi_params.sz_response - shi_params.sz_sending);
 	uint8_t *obuf_ptr = (uint8_t *)shi_params.tx_buf;
 	const uint8_t *obuf_end = obuf_ptr + size;
 	uint8_t *msg_ptr = shi_params.tx_msg;
@@ -468,8 +469,8 @@ static void shi_write_first_pkg_outbuf(uint16_t szbytes)
 	 * If response package is across 256 bytes boundary,
 	 * bypass needs to extend PROCESSING bytes after reaching the boundary.
 	 */
-	if (shi_params.bytes_in_256b + SHI_OBUF_FULL_SIZE + szbytes
-	    > SHI_BYPASS_BOUNDARY) {
+	if (shi_params.bytes_in_256b + SHI_OBUF_FULL_SIZE + szbytes >
+	    SHI_BYPASS_BOUNDARY) {
 		state = SHI_STATE_WAIT_ALIGNMENT;
 		/* Set pointer of output buffer to the start address */
 		shi_params.tx_buf = SHI_OBUF_START_ADDR;
@@ -485,7 +486,7 @@ static void shi_write_first_pkg_outbuf(uint16_t szbytes)
 
 	/* Fill up to OBUF mid point, or OBUF end */
 	size = MIN(SHI_OBUF_HALF_SIZE - (offset % SHI_OBUF_HALF_SIZE),
-					szbytes - shi_params.sz_sending);
+		   szbytes - shi_params.sz_sending);
 	obuf_end = obuf_ptr + size;
 	while (obuf_ptr != obuf_end)
 		*(obuf_ptr++) = *(msg_ptr++);
@@ -520,8 +521,8 @@ static void shi_read_half_inbuf(void)
 		/* Restore data to msg buffer */
 		*(shi_params.rx_msg++) = *(shi_params.rx_buf++);
 		shi_params.sz_received++;
-	} while (shi_params.sz_received % SHI_IBUF_HALF_SIZE
-		&& shi_params.sz_received != shi_params.sz_request);
+	} while (shi_params.sz_received % SHI_IBUF_HALF_SIZE &&
+		 shi_params.sz_received != shi_params.sz_request);
 }
 
 /*
@@ -601,7 +602,7 @@ static void shi_handle_cs_assert(void)
 	if (state == SHI_STATE_DISABLED)
 		return;
 
-	/* SHI V2 module filters cs glitch by hardware automatically */
+		/* SHI V2 module filters cs glitch by hardware automatically */
 #ifndef NPCX_SHI_V2
 	/*
 	 * IBUFSTAT resets on the 7th clock cycle after CS assertion, which
@@ -725,7 +726,7 @@ static void shi_int_handler(void)
 
 			DEBUG_CPRINTF("CNL-");
 			return;
-		/* Next transaction but we're not ready */
+			/* Next transaction but we're not ready */
 		} else if (state == SHI_STATE_CNL_RESP_NOT_RDY)
 			return;
 
@@ -754,8 +755,8 @@ static void shi_int_handler(void)
 			return shi_handle_host_package();
 		} else if (state == SHI_STATE_SENDING) {
 			/* Write data from msg buffer to output buffer */
-			if (shi_params.tx_buf == SHI_OBUF_START_ADDR +
-					SHI_OBUF_FULL_SIZE) {
+			if (shi_params.tx_buf ==
+			    SHI_OBUF_START_ADDR + SHI_OBUF_FULL_SIZE) {
 				/* Write data from bottom address again */
 				shi_params.tx_buf = SHI_OBUF_START_ADDR;
 				return shi_write_half_outbuf();
@@ -770,8 +771,8 @@ static void shi_int_handler(void)
 			 * If pointer of output buffer will reach 256 bytes
 			 * boundary soon, start to fill response data.
 			 */
-			if (shi_params.bytes_in_256b == SHI_BYPASS_BOUNDARY -
-					SHI_OBUF_FULL_SIZE) {
+			if (shi_params.bytes_in_256b ==
+			    SHI_BYPASS_BOUNDARY - SHI_OBUF_FULL_SIZE) {
 				state = SHI_STATE_SENDING;
 				DEBUG_CPRINTF("SND-");
 				return shi_write_half_outbuf();
@@ -805,8 +806,9 @@ static void shi_int_handler(void)
 	if (IS_BIT_SET(stat_reg, NPCX_EVSTAT_IBF)) {
 #ifdef NPCX_SHI_BYPASS_OVER_256B
 		/* Record the sent bytes within 256B boundary */
-		shi_params.bytes_in_256b = (shi_params.bytes_in_256b +
-				SHI_OBUF_FULL_SIZE) % SHI_BYPASS_BOUNDARY;
+		shi_params.bytes_in_256b =
+			(shi_params.bytes_in_256b + SHI_OBUF_FULL_SIZE) %
+			SHI_BYPASS_BOUNDARY;
 #endif
 		if (state == SHI_STATE_RECEIVING) {
 			/* read data from input to msg buffer */
@@ -816,16 +818,16 @@ static void shi_int_handler(void)
 			return shi_handle_host_package();
 		} else if (state == SHI_STATE_SENDING)
 			/* Write data from msg buffer to output buffer */
-			if (shi_params.tx_buf == SHI_OBUF_START_ADDR +
-					SHI_OBUF_HALF_SIZE)
+			if (shi_params.tx_buf ==
+			    SHI_OBUF_START_ADDR + SHI_OBUF_HALF_SIZE)
 				return shi_write_half_outbuf();
 			else /* ignore it */
 				return;
 		else if (state == SHI_STATE_PROCESSING
 #ifdef NPCX_SHI_BYPASS_OVER_256B
-				|| state == SHI_STATE_WAIT_ALIGNMENT
+			 || state == SHI_STATE_WAIT_ALIGNMENT
 #endif
-				)
+		)
 			/* Wait for host handles request */
 			return;
 		else
@@ -850,7 +852,6 @@ void shi_cs_event(enum gpio_signal signal)
 #else
 	shi_handle_cs_assert();
 #endif
-
 }
 
 /*****************************************************************************/
@@ -960,9 +961,7 @@ static void shi_reenable_on_sysjump(void)
 		shi_enable();
 }
 /* Call hook after chipset sets initial power state */
-DECLARE_HOOK(HOOK_INIT,
-	     shi_reenable_on_sysjump,
-	     HOOK_PRIO_POST_CHIPSET);
+DECLARE_HOOK(HOOK_INIT, shi_reenable_on_sysjump, HOOK_PRIO_POST_CHIPSET);
 
 /* Disable SHI bus */
 static void shi_disable(void)
@@ -1079,4 +1078,4 @@ static enum ec_status shi_get_protocol_info(struct host_cmd_handler_args *args)
 	return EC_RES_SUCCESS;
 }
 DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, shi_get_protocol_info,
-EC_VER_MASK(0));
+		     EC_VER_MASK(0));
diff --git a/chip/npcx/shi_chip.h b/chip/npcx/shi_chip.h
index 3fd73e8119..9d41a2dcab 100644
--- a/chip/npcx/shi_chip.h
+++ b/chip/npcx/shi_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/npcx/sib.c b/chip/npcx/sib.c
index 424048518e..e8dbd5039d 100644
--- a/chip/npcx/sib.c
+++ b/chip/npcx/sib.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -28,7 +28,7 @@
 /* Console output macros */
 #ifdef DEBUG_SIB
 #define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 #else
 #define CPUTS(...)
 #define CPRINTS(...)
@@ -110,8 +110,7 @@ uint8_t sib_read_kbc_reg(uint8_t io_offset)
 }
 
 /* Super-IO read/write function */
-void sib_write_reg(uint8_t io_offset, uint8_t index_value,
-		uint8_t io_data)
+void sib_write_reg(uint8_t io_offset, uint8_t index_value, uint8_t io_data)
 {
 	/* Disable interrupts */
 	interrupt_disable();
@@ -132,7 +131,7 @@ void sib_write_reg(uint8_t io_offset, uint8_t index_value,
 	sib_wait_host_write_done();
 
 	/* Specify the io_offset A0 = 1. the data register is accessed */
-	NPCX_IHIOA = io_offset+1;
+	NPCX_IHIOA = io_offset + 1;
 	/* Write the data. This starts the write access to the host module */
 	NPCX_IHD = io_data;
 	/* Wait while Core write operation is in progress */
@@ -170,7 +169,7 @@ uint8_t sib_read_reg(uint8_t io_offset, uint8_t index_value)
 	sib_wait_host_write_done();
 
 	/* Specify the io_offset A0 = 1. the data register is accessed */
-	NPCX_IHIOA = io_offset+1;
+	NPCX_IHIOA = io_offset + 1;
 	/* Start a Core read from host module */
 	SET_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSRD);
 	/* Wait while Core read operation is in progress */
diff --git a/chip/npcx/sib_chip.h b/chip/npcx/sib_chip.h
index 1687c90925..570fe6b0ec 100644
--- a/chip/npcx/sib_chip.h
+++ b/chip/npcx/sib_chip.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,15 +7,14 @@
 /* NPCX-specific SIB module for Chrome EC */
 
 /* Super-IO index and register definitions */
-#define INDEX_SID       0x20
-#define INDEX_CHPREV    0x24
-#define INDEX_SRID      0x27
+#define INDEX_SID 0x20
+#define INDEX_CHPREV 0x24
+#define INDEX_SRID 0x27
 
-#define SIO_OFFSET      0x4E
+#define SIO_OFFSET 0x4E
 
 /* Super-IO register write function */
-void sib_write_reg(uint8_t io_offset, uint8_t index_value,
-		uint8_t io_data);
+void sib_write_reg(uint8_t io_offset, uint8_t index_value, uint8_t io_data);
 /* Super-IO register read function */
 uint8_t sib_read_reg(uint8_t io_offset, uint8_t index_value);
 /* Emulate host to read Keyboard I/O */
diff --git a/chip/npcx/spi.c b/chip/npcx/spi.c
index 55fa8f85ab..0161ce63ef 100644
--- a/chip/npcx/spi.c
+++ b/chip/npcx/spi.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,11 +22,11 @@
 #define CPRINTS(...)
 #else
 #define CPUTS(outstr) cputs(CC_SPI, outstr)
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SPI, format, ##args)
 #endif
 
 /* SPI IP as SPI controller */
-#define SPI_CLK         8000000
+#define SPI_CLK 8000000
 /**
  * Clear SPI data buffer.
  *
@@ -49,19 +49,20 @@ static void clear_databuf(void)
  */
 void spi_freq_changed(void)
 {
-	uint8_t prescaler_divider    = 0;
+	uint8_t prescaler_divider = 0;
 
 	/* Set clock prescaler divider to SPI module*/
-	prescaler_divider = (uint8_t)((uint32_t)clock_get_apb2_freq()
-			/ 2 / SPI_CLK);
+	prescaler_divider =
+		(uint8_t)((uint32_t)clock_get_apb2_freq() / 2 / SPI_CLK);
 	if (prescaler_divider >= 1)
 		prescaler_divider = prescaler_divider - 1;
 	if (prescaler_divider > 0x7F)
 		prescaler_divider = 0x7F;
 
 	/* Set core clock division factor in order to obtain the SPI clock */
-	NPCX_SPI_CTL1 = (NPCX_SPI_CTL1&(~(((1<<7)-1)<<NPCX_SPI_CTL1_SCDV)))
-			|(prescaler_divider<<NPCX_SPI_CTL1_SCDV);
+	NPCX_SPI_CTL1 =
+		(NPCX_SPI_CTL1 & (~(((1 << 7) - 1) << NPCX_SPI_CTL1_SCDV))) |
+		(prescaler_divider << NPCX_SPI_CTL1_SCDV);
 }
 DECLARE_HOOK(HOOK_FREQ_CHANGE, spi_freq_changed, HOOK_PRIO_FIRST);
 
@@ -105,7 +106,6 @@ int spi_enable(const struct spi_device_t *spi_device, int enable)
 	return EC_SUCCESS;
 }
 
-
 /**
  * Flush an SPI transaction and receive data from peripheral.
  *
@@ -118,8 +118,8 @@ int spi_enable(const struct spi_device_t *spi_device, int enable)
  * @notes   set controller transaction mode in npcx chip
  */
 int spi_transaction(const struct spi_device_t *spi_device,
-		const uint8_t *txdata, int txlen,
-		uint8_t *rxdata, int rxlen)
+		    const uint8_t *txdata, int txlen, uint8_t *rxdata,
+		    int rxlen)
 {
 	int i = 0;
 	enum gpio_signal gpio = spi_device->gpio_cs;
@@ -143,7 +143,7 @@ int spi_transaction(const struct spi_device_t *spi_device,
 		while (IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_BSY))
 			;
 		/* Write the data */
-		NPCX_SPI_DATA =  txdata[i];
+		NPCX_SPI_DATA = txdata[i];
 		CPRINTS("txdata[i]=%x", txdata[i]);
 		/* Waiting till reading is finished */
 		while (!IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_RBF))
@@ -158,7 +158,7 @@ int spi_transaction(const struct spi_device_t *spi_device,
 		while (IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_BSY))
 			;
 		/* Write the (unused) data */
-		NPCX_SPI_DATA =  0;
+		NPCX_SPI_DATA = 0;
 		/* Wait till reading is finished */
 		while (!IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_RBF))
 			;
@@ -184,7 +184,7 @@ static void spi_init(void)
 	int i;
 	/* Enable clock for SPI peripheral */
 	clock_enable_peripheral(CGC_OFFSET_SPI, CGC_SPI_MASK,
-			CGC_MODE_RUN | CGC_MODE_SLEEP);
+				CGC_MODE_RUN | CGC_MODE_SLEEP);
 
 	/* Disabling spi module */
 	for (i = 0; i < spi_devices_used; i++)
@@ -205,8 +205,8 @@ static void spi_init(void)
 	CLEAR_BIT(NPCX_SPI_CTL1, NPCX_SPI_CTL1_SCIDL);
 
 	CPRINTS("nSPI_COMP=%x", IS_BIT_SET(NPCX_STRPST, NPCX_STRPST_SPI_COMP));
-	CPRINTS("SPI_SP_SEL=%x", IS_BIT_SET(NPCX_DEV_CTL4,
-			NPCX_DEV_CTL4_SPI_SP_SEL));
+	CPRINTS("SPI_SP_SEL=%x",
+		IS_BIT_SET(NPCX_DEV_CTL4, NPCX_DEV_CTL4_SPI_SP_SEL));
 	/* Cleaning junk data in the buffer */
 	clear_databuf();
 }
@@ -216,7 +216,7 @@ DECLARE_HOOK(HOOK_INIT, spi_init, HOOK_PRIO_INIT_SPI);
 /* Console commands */
 #ifdef CONFIG_CMD_SPI_FLASH
 static int printrx(const char *desc, const uint8_t *txdata, int txlen,
-		int rxlen)
+		   int rxlen)
 {
 	uint8_t rxdata[32];
 	int rv;
@@ -233,13 +233,13 @@ static int printrx(const char *desc, const uint8_t *txdata, int txlen,
 	return EC_SUCCESS;
 }
 
-static int command_spirom(int argc, char **argv)
+static int command_spirom(int argc, const char **argv)
 {
-	uint8_t txmandev[] = {0x90, 0x00, 0x00, 0x00};
-	uint8_t txjedec[] = {0x9f};
-	uint8_t txunique[] = {0x4b, 0x00, 0x00, 0x00, 0x00};
-	uint8_t txsr1[] = {0x05};
-	uint8_t txsr2[] = {0x35};
+	uint8_t txmandev[] = { 0x90, 0x00, 0x00, 0x00 };
+	uint8_t txjedec[] = { 0x9f };
+	uint8_t txunique[] = { 0x4b, 0x00, 0x00, 0x00, 0x00 };
+	uint8_t txsr1[] = { 0x05 };
+	uint8_t txsr2[] = { 0x35 };
 
 	spi_enable(SPI_FLASH_DEVICE, 1);
 
@@ -253,7 +253,6 @@ static int command_spirom(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(spirom, command_spirom,
-		NULL,
-		"Test reading SPI EEPROM");
+DECLARE_CONSOLE_COMMAND(spirom, command_spirom, NULL,
+			"Test reading SPI EEPROM");
 #endif
diff --git a/chip/npcx/spiflashfw/monitor_hdr.c b/chip/npcx/spiflashfw/monitor_hdr.c
index 219a037d27..09606c4c31 100644
--- a/chip/npcx/spiflashfw/monitor_hdr.c
+++ b/chip/npcx/spiflashfw/monitor_hdr.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -20,7 +20,7 @@ const struct monitor_header_tag monitor_hdr = {
 	 * programed into the SPI flash.
 	 */
 	CONFIG_PROGRAM_MEMORY_BASE,
-	/* 0x0C:The Flash start address to be programmed*/
+/* 0x0C:The Flash start address to be programmed*/
 #ifdef SECTION_IS_RO
 	/* Default: RO image is programed from the start of SPI flash */
 	CONFIG_EC_PROTECTED_STORAGE_OFF,
diff --git a/chip/npcx/spiflashfw/npcx_monitor.c b/chip/npcx/spiflashfw/npcx_monitor.c
index f22037f8de..5b7a767992 100644
--- a/chip/npcx/spiflashfw/npcx_monitor.c
+++ b/chip/npcx/spiflashfw/npcx_monitor.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -49,7 +49,7 @@ void sspi_flash_execute_cmd(uint8_t code, uint8_t cts)
 	/* set UMA_CODE */
 	NPCX_UMA_CODE = code;
 	/* execute UMA flash transaction */
-	NPCX_UMA_CTS  = cts;
+	NPCX_UMA_CTS = cts;
 	while (IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE))
 		;
 }
@@ -76,7 +76,7 @@ void sspi_flash_wait_ready(void)
 	sspi_flash_execute_cmd(CMD_READ_STATUS_REG, MASK_CMD_ONLY);
 	do {
 		/* Read status register */
-		NPCX_UMA_CTS  = MASK_RD_1BYTE;
+		NPCX_UMA_CTS = MASK_RD_1BYTE;
 		while (IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE))
 			;
 	} while (NPCX_UMA_DB0 & mask); /* Wait for Busy clear */
@@ -108,7 +108,7 @@ void sspi_flash_set_address(uint32_t dest_addr)
 }
 
 void sspi_flash_burst_write(unsigned int dest_addr, unsigned int bytes,
-		const char *data)
+			    const char *data)
 {
 	unsigned int i;
 	/* Chip Select down. */
@@ -197,7 +197,7 @@ void sspi_flash_physical_erase(int offset, int size)
 
 	/* Alignment has been checked in upper layer */
 	for (; size > 0; size -= NPCX_MONITOR_FLASH_ERASE_SIZE,
-		offset += NPCX_MONITOR_FLASH_ERASE_SIZE) {
+			 offset += NPCX_MONITOR_FLASH_ERASE_SIZE) {
 		/* Enable write */
 		sspi_flash_write_enable();
 		/* Set erase address */
@@ -221,7 +221,7 @@ int sspi_flash_verify(int offset, int size, const char *data)
 	uint8_t cmp_data;
 
 	ptr_flash = (uint8_t *)(CONFIG_MAPPED_STORAGE_BASE + offset);
-	ptr_mram  = (uint8_t *)data;
+	ptr_mram = (uint8_t *)data;
 	result = 1;
 
 	/* Disable tri-state */
@@ -255,12 +255,11 @@ int sspi_flash_get_image_used(const char *fw_base)
 	for (size--; size > 0 && image[size] != 0xea; size--)
 		;
 
-	return size ? size + 1 : 0;  /* 0xea byte IS part of the image */
-
+	return size ? size + 1 : 0; /* 0xea byte IS part of the image */
 }
 
 /* Entry function of spi upload function */
-uint32_t  __attribute__ ((section(".startup_text")))
+uint32_t __attribute__((section(".startup_text")))
 sspi_flash_upload(int spi_offset, int spi_size)
 {
 	/*
@@ -315,7 +314,7 @@ sspi_flash_upload(int spi_offset, int spi_size)
 		/* Start to write */
 		if (image_base != NULL)
 			sspi_flash_physical_write(spi_offset, sz_image,
-						image_base);
+						  image_base);
 		/* Verify data */
 		if (sspi_flash_verify(spi_offset, sz_image, image_base))
 			*flag_upload |= 0x02;
diff --git a/chip/npcx/spiflashfw/npcx_monitor.h b/chip/npcx/spiflashfw/npcx_monitor.h
index f4f30454d2..54303958d6 100644
--- a/chip/npcx/spiflashfw/npcx_monitor.h
+++ b/chip/npcx/spiflashfw/npcx_monitor.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,11 +7,11 @@
 
 #include <stdint.h>
 
-#define NPCX_MONITOR_UUT_TAG      0xA5075001
-#define NPCX_MONITOR_HEADER_ADDR  0x200C3000
+#define NPCX_MONITOR_UUT_TAG 0xA5075001
+#define NPCX_MONITOR_HEADER_ADDR 0x200C3000
 
 /* Flag to record the progress of programming SPI flash */
-#define SPI_PROGRAMMING_FLAG     0x200C4000
+#define SPI_PROGRAMMING_FLAG 0x200C4000
 
 struct monitor_header_tag {
 	/* offset 0x00: TAG NPCX_MONITOR_TAG */
@@ -23,9 +23,9 @@ struct monitor_header_tag {
 	/* offset 0x0C: The Flash address to be programmed (Absolute address) */
 	uint32_t dest_addr;
 	/* offset 0x10: Maximum allowable flash clock frequency */
-	uint8_t  max_clock;
+	uint8_t max_clock;
 	/* offset 0x11: SPI Flash read mode */
-	uint8_t  read_mode;
+	uint8_t read_mode;
 	/* offset 0x12: Reserved */
 	uint16_t reserved;
 } __packed;
diff --git a/chip/npcx/spiflashfw/npcx_monitor.ld b/chip/npcx/spiflashfw/npcx_monitor.ld
index ae7760c519..434945b04c 100644
--- a/chip/npcx/spiflashfw/npcx_monitor.ld
+++ b/chip/npcx/spiflashfw/npcx_monitor.ld
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/chip/npcx/system-npcx5.c b/chip/npcx/system-npcx5.c
index 4dd12fbae2..08aafe422d 100644
--- a/chip/npcx/system-npcx5.c
+++ b/chip/npcx/system-npcx5.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,6 +6,7 @@
 #include <stdnoreturn.h>
 
 /* System module driver depends on chip series for Chrome EC */
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
 #include "cpu.h"
@@ -39,9 +40,9 @@ void system_mpu_config(void)
 	CPU_MPU_CTRL = 0x7;
 
 	/* Create a new MPU Region to allow execution from low-power ram */
-	CPU_MPU_RNR  = REGION_CHIP_RESERVED;
+	CPU_MPU_RNR = REGION_CHIP_RESERVED;
 	CPU_MPU_RASR = CPU_MPU_RASR & 0xFFFFFFFE; /* Disable region */
-	CPU_MPU_RBAR = CONFIG_LPRAM_BASE;         /* Set region base address */
+	CPU_MPU_RBAR = CONFIG_LPRAM_BASE; /* Set region base address */
 	/*
 	 * Set region size & attribute and enable region
 	 * [31:29] - Reserved.
@@ -61,7 +62,7 @@ void system_mpu_config(void)
 /**
  * hibernate function in low power ram for npcx5 series.
  */
-noreturn void __keep __attribute__ ((section(".lowpower_ram")))
+noreturn void __keep __attribute__((section(".lowpower_ram")))
 __enter_hibernate_in_lpram(void)
 {
 	/*
@@ -69,10 +70,8 @@ __enter_hibernate_in_lpram(void)
 	 * Our bypass needs stack instructions but FW will turn off main ram
 	 * later for better power consumption.
 	 */
-	asm (
-		"ldr r0, =0x40001800\n"
-		"mov sp, r0\n"
-	);
+	asm("ldr r0, =0x40001800\n"
+	    "mov sp, r0\n");
 
 	/* Disable Code RAM first */
 	SET_BIT(NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_5), NPCX_PWDWN_CTL5_MRFSH_DIS);
@@ -88,13 +87,12 @@ __enter_hibernate_in_lpram(void)
 	 * wake-up from deep idle.
 	 * Workaround: Apply the same bypass of idle but don't enable interrupt.
 	 */
-	asm (
-		"push {r0-r5}\n"        /* Save needed registers */
-		"ldr r0, =0x40001600\n" /* Set r0 to Suspend RAM addr */
-		"wfi\n"                 /* Wait for int to enter idle */
-		"ldm r0, {r0-r5}\n"     /* Add a delay after WFI */
-		"pop {r0-r5}\n"         /* Restore regs before enabling ints */
-		"isb\n"                 /* Flush the cpu pipeline */
+	asm("push {r0-r5}\n" /* Save needed registers */
+	    "ldr r0, =0x40001600\n" /* Set r0 to Suspend RAM addr */
+	    "wfi\n" /* Wait for int to enter idle */
+	    "ldm r0, {r0-r5}\n" /* Add a delay after WFI */
+	    "pop {r0-r5}\n" /* Restore regs before enabling ints */
+	    "isb\n" /* Flush the cpu pipeline */
 	);
 
 	/* RTC wake-up */
@@ -129,7 +127,7 @@ void __hibernate_npcx_series(void)
 {
 	int i;
 	void (*__hibernate_in_lpram)(void) =
-			(void(*)(void))(__lpram_fw_start | 0x01);
+		(void (*)(void))(__lpram_fw_start | 0x01);
 
 	/* Enable power for the Low Power RAM */
 	CLEAR_BIT(NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_6), 6);
@@ -140,7 +138,7 @@ void __hibernate_npcx_series(void)
 	/* Copy the __enter_hibernate_in_lpram instructions to LPRAM */
 	for (i = 0; i < &__flash_lpfw_end - &__flash_lpfw_start; i++)
 		*((uint32_t *)__lpram_fw_start + i) =
-				*(&__flash_lpfw_start + i);
+			*(&__flash_lpfw_start + i);
 
 	/* execute hibernate func in LPRAM */
 	__hibernate_in_lpram();
@@ -148,7 +146,7 @@ void __hibernate_npcx_series(void)
 
 #ifdef CONFIG_EXTERNAL_STORAGE
 /* Sysjump utilities in low power ram for npcx5 series. */
-noreturn void __keep __attribute__ ((section(".lowpower_ram2")))
+noreturn void __keep __attribute__((section(".lowpower_ram2")))
 __start_gdma(uint32_t exeAddr)
 {
 	/* Enable GDMA now */
@@ -159,7 +157,7 @@ __start_gdma(uint32_t exeAddr)
 
 	/* Wait for transfer to complete/fail */
 	while (!IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_TC) &&
-			!IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAERR))
+	       !IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAERR))
 		;
 
 	/* Disable GDMA now */
@@ -186,7 +184,7 @@ __start_gdma(uint32_t exeAddr)
 
 /* Bypass for GMDA issue of ROM api utilities only on npcx5 series. */
 void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr,
-		uint32_t size, uint32_t exeAddr)
+				uint32_t size, uint32_t exeAddr)
 {
 	int i;
 	uint8_t chunkSize = 16; /* 4 data burst mode. ie.16 bytes */
@@ -195,7 +193,7 @@ void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr,
 	 * it's a thumb branch for cortex-m series CPU.
 	 */
 	void (*__start_gdma_in_lpram)(uint32_t) =
-			(void(*)(uint32_t))(__lpram_lfw_start | 0x01);
+		(void (*)(uint32_t))(__lpram_lfw_start | 0x01);
 
 	/*
 	 * Before enabling burst mode for better performance of GDMA, it's
@@ -203,7 +201,7 @@ void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr,
 	 * are 16 bytes aligned in case failure occurs.
 	 */
 	ASSERT((size % chunkSize) == 0 && (srcAddr % chunkSize) == 0 &&
-			(dstAddr % chunkSize) == 0);
+	       (dstAddr % chunkSize) == 0);
 
 	/* Check valid address for jumpiing */
 	ASSERT(exeAddr != 0x0);
@@ -253,7 +251,7 @@ void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr,
 	/* Copy the __start_gdma_in_lpram instructions to LPRAM */
 	for (i = 0; i < &__flash_lplfw_end - &__flash_lplfw_start; i++)
 		*((uint32_t *)__lpram_lfw_start + i) =
-				*(&__flash_lplfw_start + i);
+			*(&__flash_lplfw_start + i);
 
 	/* Start GDMA in Suspend RAM */
 	__start_gdma_in_lpram(exeAddr);
diff --git a/chip/npcx/system-npcx7.c b/chip/npcx/system-npcx7.c
index abbb6755c3..5cacbec749 100644
--- a/chip/npcx/system-npcx7.c
+++ b/chip/npcx/system-npcx7.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,6 +6,7 @@
 #include <stdnoreturn.h>
 
 /* System module driver depends on chip series for Chrome EC */
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
 #include "cpu.h"
@@ -21,13 +22,13 @@
 #include "system_chip.h"
 #include "rom_chip.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
 /* Macros for last 32K ram block */
 #define LAST_RAM_BLK ((NPCX_RAM_SIZE / (32 * 1024)) - 1)
 /* Higher bits are reserved and need to be masked */
-#define RAM_PD_MASK  (~BIT(LAST_RAM_BLK))
+#define RAM_PD_MASK (~BIT(LAST_RAM_BLK))
 
 /*****************************************************************************/
 /* IC specific low-level driver depends on chip series */
@@ -83,11 +84,11 @@ void system_enter_psl_mode(void)
 	NPCX_BBRAM(BBRM_DATA_INDEX_WAKE) = HIBERNATE_WAKE_PSL;
 
 #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
-	 /*
-	  * If pulse mode is enabled, the VCC power is turned off by the
-	  * external component (Ex: PMIC) but PSL_OUT. So we can just return
-	  * here.
-	  */
+	/*
+	 * If pulse mode is enabled, the VCC power is turned off by the
+	 * external component (Ex: PMIC) but PSL_OUT. So we can just return
+	 * here.
+	 */
 	if (IS_BIT_SET(NPCX_GLUE_PSL_MCTL1, NPCX_GLUE_PSL_MCTL1_PLS_EN))
 		return;
 #endif
@@ -113,8 +114,7 @@ static void system_psl_type_sel(enum psl_pin_t psl_pin, uint32_t flags)
 	/* Set PSL input events' type as level or edge trigger */
 	if ((flags & GPIO_INT_F_HIGH) || (flags & GPIO_INT_F_LOW))
 		CLEAR_BIT(NPCX_GLUE_PSL_CTS, psl_pin + 4);
-	else if ((flags & GPIO_INT_F_RISING) ||
-		 (flags & GPIO_INT_F_FALLING))
+	else if ((flags & GPIO_INT_F_RISING) || (flags & GPIO_INT_F_FALLING))
 		SET_BIT(NPCX_GLUE_PSL_CTS, psl_pin + 4);
 
 	/*
@@ -145,7 +145,7 @@ int system_config_psl_mode(enum gpio_signal signal)
  * Hibernate function in last 32K ram block for npcx7 series.
  * Do not use global variable since we also turn off data ram.
  */
-noreturn void __keep __attribute__ ((section(".after_init")))
+noreturn void __keep __attribute__((section(".after_init")))
 __enter_hibernate_in_last_block(void)
 {
 	/*
@@ -164,7 +164,7 @@ __enter_hibernate_in_last_block(void)
 	NPCX_PMCSR = 0x6;
 
 	/* Enter deep idle, wake-up by GPIOs or RTC */
-	asm volatile ("wfi");
+	asm volatile("wfi");
 
 	/* RTC wake-up */
 	if (IS_BIT_SET(NPCX_WTC, NPCX_WTC_PTO))
@@ -208,8 +208,8 @@ void __hibernate_npcx_series(void)
 	__enter_hibernate_in_psl();
 #else
 	/* Make sure this is located in the last 32K code RAM block */
-	ASSERT((uint32_t)(&__after_init_end) - CONFIG_PROGRAM_MEMORY_BASE
-								< (32*1024));
+	ASSERT((uint32_t)(&__after_init_end) - CONFIG_PROGRAM_MEMORY_BASE <
+	       (32 * 1024));
 
 	/* Execute hibernate func in last 32K block */
 	__enter_hibernate_in_last_block();
diff --git a/chip/npcx/system-npcx9.c b/chip/npcx/system-npcx9.c
index 48088614a0..5cacbec749 120000..100644
--- a/chip/npcx/system-npcx9.c
+++ b/chip/npcx/system-npcx9.c
@@ -1 +1,231 @@
-system-npcx7.c
\ No newline at end of file
+/* Copyright 2017 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <stdnoreturn.h>
+
+/* System module driver depends on chip series for Chrome EC */
+#include "builtin/assert.h"
+#include "common.h"
+#include "console.h"
+#include "cpu.h"
+#include "ec_commands.h"
+#include "hooks.h"
+#include "lct_chip.h"
+#include "registers.h"
+#include "system.h"
+#include "task.h"
+#include "util.h"
+#include "gpio.h"
+#include "hwtimer_chip.h"
+#include "system_chip.h"
+#include "rom_chip.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+
+/* Macros for last 32K ram block */
+#define LAST_RAM_BLK ((NPCX_RAM_SIZE / (32 * 1024)) - 1)
+/* Higher bits are reserved and need to be masked */
+#define RAM_PD_MASK (~BIT(LAST_RAM_BLK))
+
+/*****************************************************************************/
+/* IC specific low-level driver depends on chip series */
+
+void system_mpu_config(void)
+{
+}
+
+#ifdef CONFIG_HIBERNATE_PSL
+#ifndef NPCX_PSL_MODE_SUPPORT
+#error "Do not enable CONFIG_HIBERNATE_PSL if npcx ec doesn't support PSL mode!"
+#endif
+
+static enum psl_pin_t system_gpio_to_psl(enum gpio_signal signal)
+{
+	enum psl_pin_t psl_no;
+	const struct gpio_info *g = gpio_list + signal;
+
+	if (g->port == GPIO_PORT_D && g->mask == MASK_PIN2) /* GPIOD2 */
+		psl_no = PSL_IN1;
+	else if (g->port == GPIO_PORT_0 && (g->mask & 0x07)) /* GPIO00/01/02 */
+		psl_no = GPIO_MASK_TO_NUM(g->mask) + 1;
+	else
+		psl_no = PSL_NONE;
+
+	return psl_no;
+}
+
+#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
+void system_set_psl_gpo(int level)
+{
+	if (level)
+		SET_BIT(NPCX_GLUE_PSL_MCTL1, NPCX_GLUE_PSL_MCTL1_PSL_GPO_CTL);
+	else
+		CLEAR_BIT(NPCX_GLUE_PSL_MCTL1, NPCX_GLUE_PSL_MCTL1_PSL_GPO_CTL);
+}
+#endif
+
+void system_enter_psl_mode(void)
+{
+	/* Configure pins from GPIOs to PSL which rely on VSBY power rail. */
+	gpio_config_module(MODULE_PMU, 1);
+
+	/*
+	 * In npcx7, only physical PSL_IN pins can pull PSL_OUT to high and
+	 * reboot ec.
+	 * In npcx9, LCT timeout event can also pull PSL_OUT.
+	 * We won't decide the wake cause now but only mark we are entering
+	 * hibernation via PSL.
+	 * The actual wakeup cause will be checked by the PSL input event bits
+	 * when ec reboots.
+	 */
+	NPCX_BBRAM(BBRM_DATA_INDEX_WAKE) = HIBERNATE_WAKE_PSL;
+
+#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
+	/*
+	 * If pulse mode is enabled, the VCC power is turned off by the
+	 * external component (Ex: PMIC) but PSL_OUT. So we can just return
+	 * here.
+	 */
+	if (IS_BIT_SET(NPCX_GLUE_PSL_MCTL1, NPCX_GLUE_PSL_MCTL1_PLS_EN))
+		return;
+#endif
+
+	/*
+	 * Pull PSL_OUT (GPIO85) to low to cut off ec's VCC power rail by
+	 * setting bit 5 of PDOUT(8).
+	 */
+	SET_BIT(NPCX_PDOUT(GPIO_PORT_8), 5);
+}
+
+/* Hibernate function implemented by PSL (Power Switch Logic) mode. */
+noreturn void __keep __enter_hibernate_in_psl(void)
+{
+	system_enter_psl_mode();
+	/* Spin and wait for PSL cuts power; should never return */
+	while (1)
+		;
+}
+
+static void system_psl_type_sel(enum psl_pin_t psl_pin, uint32_t flags)
+{
+	/* Set PSL input events' type as level or edge trigger */
+	if ((flags & GPIO_INT_F_HIGH) || (flags & GPIO_INT_F_LOW))
+		CLEAR_BIT(NPCX_GLUE_PSL_CTS, psl_pin + 4);
+	else if ((flags & GPIO_INT_F_RISING) || (flags & GPIO_INT_F_FALLING))
+		SET_BIT(NPCX_GLUE_PSL_CTS, psl_pin + 4);
+
+	/*
+	 * Set PSL input events' polarity is low (high-to-low) active or
+	 * high (low-to-high) active
+	 */
+	if (flags & GPIO_HIB_WAKE_HIGH)
+		SET_BIT(NPCX_DEVALT(ALT_GROUP_D), 2 * psl_pin);
+	else
+		CLEAR_BIT(NPCX_DEVALT(ALT_GROUP_D), 2 * psl_pin);
+}
+
+int system_config_psl_mode(enum gpio_signal signal)
+{
+	enum psl_pin_t psl_no;
+	const struct gpio_info *g = gpio_list + signal;
+
+	psl_no = system_gpio_to_psl(signal);
+	if (psl_no == PSL_NONE)
+		return 0;
+
+	system_psl_type_sel(psl_no, g->flags);
+	return 1;
+}
+
+#else
+/**
+ * Hibernate function in last 32K ram block for npcx7 series.
+ * Do not use global variable since we also turn off data ram.
+ */
+noreturn void __keep __attribute__((section(".after_init")))
+__enter_hibernate_in_last_block(void)
+{
+	/*
+	 * The hibernate utility is located in the last block of RAM. The size
+	 * of each RAM block is 32KB. We turn off all blocks except last one
+	 * for better power consumption.
+	 */
+	NPCX_RAM_PD(0) = RAM_PD_MASK & 0xFF;
+#if defined(CHIP_FAMILY_NPCX7)
+	NPCX_RAM_PD(1) = (RAM_PD_MASK >> 8) & 0x0F;
+#elif defined(CHIP_FAMILY_NPCX9)
+	NPCX_RAM_PD(1) = (RAM_PD_MASK >> 8) & 0x7F;
+#endif
+
+	/* Set deep idle mode */
+	NPCX_PMCSR = 0x6;
+
+	/* Enter deep idle, wake-up by GPIOs or RTC */
+	asm volatile("wfi");
+
+	/* RTC wake-up */
+	if (IS_BIT_SET(NPCX_WTC, NPCX_WTC_PTO))
+		/*
+		 * Mark wake-up reason for hibernate
+		 * Do not call bbram_data_write directly cause of
+		 * no stack.
+		 */
+		NPCX_BBRAM(BBRM_DATA_INDEX_WAKE) = HIBERNATE_WAKE_MTC;
+#ifdef NPCX_LCT_SUPPORT
+	else if (IS_BIT_SET(NPCX_LCTSTAT, NPCX_LCTSTAT_EVST)) {
+		NPCX_BBRAM(BBRM_DATA_INDEX_WAKE) = HIBERNATE_WAKE_LCT;
+		/* Clear LCT event */
+		NPCX_LCTSTAT = BIT(NPCX_LCTSTAT_EVST);
+	}
+#endif
+	else
+		/* Otherwise, we treat it as GPIOs wake-up */
+		NPCX_BBRAM(BBRM_DATA_INDEX_WAKE) = HIBERNATE_WAKE_PIN;
+
+	/* Start a watchdog reset */
+	NPCX_WDCNT = 0x01;
+	/* Reload and restart Timer 0 */
+	SET_BIT(NPCX_T0CSR, NPCX_T0CSR_RST);
+	/* Wait for timer is loaded and restart */
+	while (IS_BIT_SET(NPCX_T0CSR, NPCX_T0CSR_RST))
+		;
+
+	/* Spin and wait for reboot; should never return */
+	while (1)
+		;
+}
+#endif
+
+/**
+ * Hibernate function for different Nuvoton chip series.
+ */
+void __hibernate_npcx_series(void)
+{
+#ifdef CONFIG_HIBERNATE_PSL
+	__enter_hibernate_in_psl();
+#else
+	/* Make sure this is located in the last 32K code RAM block */
+	ASSERT((uint32_t)(&__after_init_end) - CONFIG_PROGRAM_MEMORY_BASE <
+	       (32 * 1024));
+
+	/* Execute hibernate func in last 32K block */
+	__enter_hibernate_in_last_block();
+#endif
+}
+
+#if defined(CONFIG_HIBERNATE_PSL)
+static void report_psl_wake_source(void)
+{
+	if (!(system_get_reset_flags() & EC_RESET_FLAG_HIBERNATE))
+		return;
+
+	CPRINTS("PSL_CTS: 0x%x", NPCX_GLUE_PSL_CTS & 0xf);
+#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
+	CPRINTS("PSL_MCTL1 event: 0x%x", NPCX_GLUE_PSL_MCTL1 & 0x18);
+#endif
+}
+DECLARE_HOOK(HOOK_INIT, report_psl_wake_source, HOOK_PRIO_DEFAULT);
+#endif
diff --git a/chip/npcx/system.c b/chip/npcx/system.c
index 4a2450ee5f..958d873401 100644
--- a/chip/npcx/system.c
+++ b/chip/npcx/system.c
@@ -1,10 +1,11 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* System module for Chrome EC : NPCX hardware specific implementation */
 
+#include "builtin/assert.h"
 #include "clock.h"
 #include "clock_chip.h"
 #include "common.h"
@@ -15,6 +16,7 @@
 #include "host_command.h"
 #include "hwtimer_chip.h"
 #include "lct_chip.h"
+#include "panic.h"
 #include "registers.h"
 #include "rom_chip.h"
 #include "sib_chip.h"
@@ -27,27 +29,27 @@
 
 /* Delay after writing TTC for value to latch */
 #define MTC_TTC_LOAD_DELAY_US 250
-#define MTC_ALARM_MASK     (BIT(25) - 1)
-#define MTC_WUI_GROUP      MIWU_GROUP_4
-#define MTC_WUI_MASK       MASK_PIN7
+#define MTC_ALARM_MASK (BIT(25) - 1)
+#define MTC_WUI_GROUP MIWU_GROUP_4
+#define MTC_WUI_MASK MASK_PIN7
 
 /* ROM address of chip revision */
 #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
-#define CHIP_REV_ADDR             0x0000FFFC
-#define CHIP_REV_STR_SIZE         12
+#define CHIP_REV_ADDR 0x0000FFFC
+#define CHIP_REV_STR_SIZE 12
 #define PWDWN_8_RESERVED_SET_MASK 0x30
 #else
-#define CHIP_REV_ADDR        0x00007FFC
-#define CHIP_REV_STR_SIZE    6
+#define CHIP_REV_ADDR 0x00007FFC
+#define CHIP_REV_STR_SIZE 6
 #endif
 
 /*  Legacy SuperI/O Configuration D register offset */
-#define SIOCFD_REG_OFFSET    0x2D
+#define SIOCFD_REG_OFFSET 0x2D
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
 #if defined(NPCX_LCT_SUPPORT)
 /* A flag for waking up from hibernate mode by RTC overflow event */
@@ -91,8 +93,7 @@ void system_watchdog_reset(void)
 /* Return true if index is stored as a single byte in bbram */
 static int bbram_is_byte_access(enum bbram_data_index index)
 {
-	return index == BBRM_DATA_INDEX_PD0 ||
-	       index == BBRM_DATA_INDEX_PD1 ||
+	return index == BBRM_DATA_INDEX_PD0 || index == BBRM_DATA_INDEX_PD1 ||
 	       index == BBRM_DATA_INDEX_PD2 ||
 	       index == BBRM_DATA_INDEX_PANIC_FLAGS;
 }
@@ -106,7 +107,7 @@ void system_check_bbram_on_reset(void)
 		 * dropped, print a warning message.
 		 */
 		if (IS_BIT_SET(NPCX_RSTCTL, NPCX_RSTCTL_VCC1_RST_SCRATCH) ||
-			IS_BIT_SET(NPCX_RSTCTL, NPCX_RSTCTL_VCC1_RST_STS))
+		    IS_BIT_SET(NPCX_RSTCTL, NPCX_RSTCTL_VCC1_RST_STS))
 			CPRINTF("VBAT drop!\n");
 
 		/*
@@ -177,7 +178,7 @@ static int bbram_data_write(enum bbram_data_index index, uint32_t value)
 	/* Write BBRAM */
 	NPCX_BBRAM(index) = value & 0xFF;
 	if (bytes == 4) {
-		NPCX_BBRAM(index + 1) = (value >> 8)  & 0xFF;
+		NPCX_BBRAM(index + 1) = (value >> 8) & 0xFF;
 		NPCX_BBRAM(index + 2) = (value >> 16) & 0xFF;
 		NPCX_BBRAM(index + 3) = (value >> 24) & 0xFF;
 	}
@@ -260,14 +261,14 @@ void system_set_rtc(uint32_t seconds)
  * 2. LREG1, LREG3 and LREG4 store exception, reason and info in case of
  * software panic.
  */
-#define BKUP_CFSR		(BBRM_DATA_INDEX_PANIC_BKUP + 0)
-#define BKUP_HFSR		(BBRM_DATA_INDEX_PANIC_BKUP + 4)
-#define BKUP_BFAR		(BBRM_DATA_INDEX_PANIC_BKUP + 8)
-#define BKUP_LREG1		(BBRM_DATA_INDEX_PANIC_BKUP + 12)
-#define BKUP_LREG3		(BBRM_DATA_INDEX_PANIC_BKUP + 16)
-#define BKUP_LREG4		(BBRM_DATA_INDEX_PANIC_BKUP + 20)
+#define BKUP_CFSR (BBRM_DATA_INDEX_PANIC_BKUP + 0)
+#define BKUP_HFSR (BBRM_DATA_INDEX_PANIC_BKUP + 4)
+#define BKUP_BFAR (BBRM_DATA_INDEX_PANIC_BKUP + 8)
+#define BKUP_LREG1 (BBRM_DATA_INDEX_PANIC_BKUP + 12)
+#define BKUP_LREG3 (BBRM_DATA_INDEX_PANIC_BKUP + 16)
+#define BKUP_LREG4 (BBRM_DATA_INDEX_PANIC_BKUP + 20)
 
-#define BKUP_PANIC_DATA_VALID	BIT(0)
+#define BKUP_PANIC_DATA_VALID BIT(0)
 
 void chip_panic_data_backup(void)
 {
@@ -336,10 +337,10 @@ static void chip_set_hib_flag(uint32_t *flags, uint32_t hib_wake_flags)
 #ifdef NPCX_LCT_SUPPORT
 		if (npcx_lct_is_event_set()) {
 			*flags |= EC_RESET_FLAG_RTC_ALARM |
-					  EC_RESET_FLAG_HIBERNATE;
+				  EC_RESET_FLAG_HIBERNATE;
 			/* Is RTC overflow event? */
 			if (bbram_data_read(BBRM_DATA_INDEX_LCT_TIME) ==
-				NPCX_LCT_MAX) {
+			    NPCX_LCT_MAX) {
 				/*
 				 * Mark it as RTC overflow event and handle it
 				 * in hook init function later for logging info.
@@ -350,22 +351,21 @@ static void chip_set_hib_flag(uint32_t *flags, uint32_t hib_wake_flags)
 			return;
 		}
 #endif
-		*flags |= EC_RESET_FLAG_WAKE_PIN |
-				  EC_RESET_FLAG_HIBERNATE;
+		*flags |= EC_RESET_FLAG_WAKE_PIN | EC_RESET_FLAG_HIBERNATE;
 	} else { /* Hibernate via non-PSL */
 #ifdef NPCX_LCT_SUPPORT
 		if (hib_wake_flags & HIBERNATE_WAKE_LCT) {
 			*flags |= EC_RESET_FLAG_RTC_ALARM |
-					  EC_RESET_FLAG_HIBERNATE;
+				  EC_RESET_FLAG_HIBERNATE;
 			return;
 		}
 #endif
 		if (hib_wake_flags & HIBERNATE_WAKE_PIN) {
 			*flags |= EC_RESET_FLAG_WAKE_PIN |
-					  EC_RESET_FLAG_HIBERNATE;
+				  EC_RESET_FLAG_HIBERNATE;
 		} else if (hib_wake_flags & HIBERNATE_WAKE_MTC) {
 			*flags |= EC_RESET_FLAG_RTC_ALARM |
-					  EC_RESET_FLAG_HIBERNATE;
+				  EC_RESET_FLAG_HIBERNATE;
 		}
 	}
 }
@@ -420,9 +420,9 @@ static void check_reset_cause(void)
 					 * clear the flag so later code will
 					 * not wait for the second reset.
 					 */
-					flags =
-					  (flags & ~EC_RESET_FLAG_INITIAL_PWR)
-					   | EC_RESET_FLAG_POWER_ON;
+					flags = (flags &
+						 ~EC_RESET_FLAG_INITIAL_PWR) |
+						EC_RESET_FLAG_POWER_ON;
 				else
 					/*
 					 * No previous power-on flag,
@@ -452,8 +452,8 @@ static void check_reset_cause(void)
 			 * No second reset after power-on, so
 			 * set the flags according to the restart reason.
 			 */
-			flags |= reset ? EC_RESET_FLAG_RESET_PIN
-				       : EC_RESET_FLAG_POWER_ON;
+			flags |= reset ? EC_RESET_FLAG_RESET_PIN :
+					 EC_RESET_FLAG_POWER_ON;
 #endif
 	}
 	chip_save_reset_flags(chip_flags);
@@ -480,7 +480,7 @@ static void check_reset_cause(void)
 		 * cause is panic reason or not.
 		 */
 		if (!(flags & (EC_RESET_FLAG_SOFT | EC_RESET_FLAG_HARD |
-				EC_RESET_FLAG_HIBERNATE)))
+			       EC_RESET_FLAG_HIBERNATE)))
 			flags |= EC_RESET_FLAG_WATCHDOG;
 
 		/* Clear watchdog reset status initially*/
@@ -499,10 +499,10 @@ static void system_set_gpios_and_wakeup_inputs_hibernate(void)
 	int table, i;
 
 	/* Disable all MIWU inputs before entering hibernate */
-	for (table = MIWU_TABLE_0 ; table < MIWU_TABLE_2 ; table++) {
-		for (i = 0 ; i < 8 ; i++) {
+	for (table = MIWU_TABLE_0; table < MIWU_TABLE_2; table++) {
+		for (i = 0; i < 8; i++) {
 			/* Disable all wake-ups */
-			NPCX_WKEN(table, i)  = 0x00;
+			NPCX_WKEN(table, i) = 0x00;
 			/* Clear all pending bits of wake-ups */
 			NPCX_WKPCL(table, i) = 0xFF;
 			/*
@@ -515,7 +515,7 @@ static void system_set_gpios_and_wakeup_inputs_hibernate(void)
 
 #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
 	/* Disable MIWU 2 group 6 inputs which used for the additional GPIOs */
-	NPCX_WKEN(MIWU_TABLE_2, MIWU_GROUP_6)  = 0x00;
+	NPCX_WKEN(MIWU_TABLE_2, MIWU_GROUP_6) = 0x00;
 	NPCX_WKPCL(MIWU_TABLE_2, MIWU_GROUP_6) = 0xFF;
 	NPCX_WKINEN(MIWU_TABLE_2, MIWU_GROUP_6) = 0x00;
 #endif
@@ -553,9 +553,9 @@ static void system_set_lct_alarm(uint32_t seconds, uint32_t microseconds)
 	npcx_lct_config(seconds, 0, 1);
 	task_disable_irq(NPCX_IRQ_LCT_WKINTF_2);
 	/* Enable wake-up input sources & clear pending bit */
-	NPCX_WKPCL(MIWU_TABLE_2, LCT_WUI_GROUP)  |= LCT_WUI_MASK;
+	NPCX_WKPCL(MIWU_TABLE_2, LCT_WUI_GROUP) |= LCT_WUI_MASK;
 	NPCX_WKINEN(MIWU_TABLE_2, LCT_WUI_GROUP) |= LCT_WUI_MASK;
-	NPCX_WKEN(MIWU_TABLE_2, LCT_WUI_GROUP)   |= LCT_WUI_MASK;
+	NPCX_WKEN(MIWU_TABLE_2, LCT_WUI_GROUP) |= LCT_WUI_MASK;
 	task_enable_irq(NPCX_IRQ_LCT_WKINTF_2);
 #endif
 	npcx_lct_enable(1);
@@ -628,10 +628,10 @@ void __enter_hibernate(uint32_t seconds, uint32_t microseconds)
 		board_hibernate_late();
 
 	/* Clear all pending IRQ otherwise wfi will have no affect */
-	for (i = NPCX_IRQ_0 ; i < NPCX_IRQ_COUNT ; i++)
+	for (i = NPCX_IRQ_0; i < NPCX_IRQ_COUNT; i++)
 		task_clear_pending_irq(i);
 
-	/* Set the timer interrupt for wake up.  */
+		/* Set the timer interrupt for wake up.  */
 #ifdef NPCX_LCT_SUPPORT
 	if (seconds || microseconds) {
 		system_set_lct_alarm(seconds, microseconds);
@@ -726,9 +726,9 @@ void system_set_rtc_alarm(uint32_t seconds, uint32_t microseconds)
 	task_enable_irq(NPCX_IRQ_MTC);
 
 	/* Enable wake-up input sources & clear pending bit */
-	NPCX_WKPCL(MIWU_TABLE_0, MTC_WUI_GROUP)  |= MTC_WUI_MASK;
+	NPCX_WKPCL(MIWU_TABLE_0, MTC_WUI_GROUP) |= MTC_WUI_MASK;
 	NPCX_WKINEN(MIWU_TABLE_0, MTC_WUI_GROUP) |= MTC_WUI_MASK;
-	NPCX_WKEN(MIWU_TABLE_0, MTC_WUI_GROUP)   |= MTC_WUI_MASK;
+	NPCX_WKEN(MIWU_TABLE_0, MTC_WUI_GROUP) |= MTC_WUI_MASK;
 }
 
 void system_reset_rtc_alarm(void)
@@ -835,7 +835,7 @@ void chip_pre_init(void)
 	}
 #else
 	if (GET_FIELD(NPCX_JEN_CTL1, NPCX_JEN_CTL1_JEN_EN_FIELD) ==
-		      NPCX_JEN_CTL1_JEN_EN_ENA) {
+	    NPCX_JEN_CTL1_JEN_EN_ENA) {
 		SET_FIELD(NPCX_JEN_CTL1, NPCX_JEN_CTL1_JEN_EN_FIELD,
 			  NPCX_JEN_CTL1_JEN_EN_DIS);
 		system_disable_host_sel_jtag();
@@ -871,20 +871,20 @@ void system_pre_init(void)
 
 	pwdwn6 = 0x70 |
 #if NPCX_FAMILY_VERSION <= NPCX_FAMILY_NPCX7
-		/*
-		 * Don't set PD of ITIM6 for NPCX9 and later chips because
-		 * they use it as the system timer.
-		 */
-		BIT(NPCX_PWDWN_CTL6_ITIM6_PD) |
+		 /*
+		  * Don't set PD of ITIM6 for NPCX9 and later chips because
+		  * they use it as the system timer.
+		  */
+		 BIT(NPCX_PWDWN_CTL6_ITIM6_PD) |
 #endif
-		BIT(NPCX_PWDWN_CTL6_ITIM4_PD);
+		 BIT(NPCX_PWDWN_CTL6_ITIM4_PD);
 #if !defined(CONFIG_HOST_INTERFACE_ESPI)
 	pwdwn6 |= 1 << NPCX_PWDWN_CTL6_ESPI_PD;
 #endif
 	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_6) = pwdwn6;
 
 #if defined(CHIP_FAMILY_NPCX7)
-#if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) || \
+#if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) ||     \
 	defined(CHIP_VARIANT_NPCX7M7FC) || defined(CHIP_VARIANT_NPCX7M7WB) || \
 	defined(CHIP_VARIANT_NPCX7M7WC)
 	/* Power down UART2, SMB5-7, ITIM64, and WoV */
@@ -949,34 +949,34 @@ void system_pre_init(void)
 			 * hibernation.
 			 */
 			SET_BIT(NPCX_GLUE_PSL_MCTL1,
-					NPCX_GLUE_PSL_MCTL1_VCC1_RST_PSL);
+				NPCX_GLUE_PSL_MCTL1_VCC1_RST_PSL);
 			/* Disable VCC_RST Pull-Up */
 			SET_BIT(NPCX_DEVALT(ALT_GROUP_G),
-					NPCX_DEVALTG_VCC1_RST_PUD);
+				NPCX_DEVALTG_VCC1_RST_PUD);
 			/*
 			 * Lock this bit itself and VCC1_RST_PSL in the
 			 * PSL_MCTL1 register to read-only.
 			 */
 			SET_BIT(NPCX_GLUE_PSL_MCTL2,
-					NPCX_GLUE_PSL_MCTL2_VCC1_RST_PSL_LK);
+				NPCX_GLUE_PSL_MCTL2_VCC1_RST_PSL_LK);
 		}
 
 		/* Don't set PSL_OUT to open-drain if it is the level mode */
 		ASSERT((opt_flag & NPCX_PSL_CFG_PSL_OUT_PULSE) ||
-			 !(opt_flag & NPCX_PSL_CFG_PSL_OUT_OD));
+		       !(opt_flag & NPCX_PSL_CFG_PSL_OUT_OD));
 
 		if (opt_flag & NPCX_PSL_CFG_PSL_OUT_OD)
 			SET_BIT(NPCX_GLUE_PSL_MCTL1, NPCX_GLUE_PSL_MCTL1_OD_EN);
 		else
 			CLEAR_BIT(NPCX_GLUE_PSL_MCTL1,
-					NPCX_GLUE_PSL_MCTL1_OD_EN);
+				  NPCX_GLUE_PSL_MCTL1_OD_EN);
 
 		if (opt_flag & NPCX_PSL_CFG_PSL_OUT_PULSE)
 			SET_BIT(NPCX_GLUE_PSL_MCTL1,
-					NPCX_GLUE_PSL_MCTL1_PLS_EN);
+				NPCX_GLUE_PSL_MCTL1_PLS_EN);
 		else
 			CLEAR_BIT(NPCX_GLUE_PSL_MCTL1,
-					NPCX_GLUE_PSL_MCTL1_PLS_EN);
+				  NPCX_GLUE_PSL_MCTL1_PLS_EN);
 	}
 #endif
 }
@@ -1027,7 +1027,7 @@ const char *system_get_chip_vendor(void)
 	case 0x20:
 		return "Nuvoton";
 	default:
-		*p       = system_to_hex(fam_id >> 4);
+		*p = system_to_hex(fam_id >> 4);
 		*(p + 1) = system_to_hex(fam_id);
 		*(p + 2) = '\0';
 		return str;
@@ -1070,7 +1070,7 @@ const char *system_get_chip_name(void)
 		return "NPCX993F";
 #endif
 	default:
-		*p       = system_to_hex(chip_id >> 4);
+		*p = system_to_hex(chip_id >> 4);
 		*(p + 1) = system_to_hex(chip_id);
 		*(p + 2) = '\0';
 		return str;
@@ -1106,7 +1106,7 @@ const char *system_get_chip_revision(void)
 		break;
 	case 0x07:
 		if (chip_id == NPCX796F_A_B_CHIP_ID ||
-			chip_id == NPCX797W_B_CHIP_ID)
+		    chip_id == NPCX797W_B_CHIP_ID)
 			*p++ = 'B';
 		else
 			*p++ = 'C';
@@ -1188,7 +1188,7 @@ static void system_init_check_rtc_wakeup_event(void)
 	 * also supported, determine whether ec is woken up by RTC with overflow
 	 * event (16 weeks). If so, let it go to hibernate mode immediately.
 	 */
-	if (is_rtc_overflow_event){
+	if (is_rtc_overflow_event) {
 		CPRINTS("Hibernate due to RTC overflow event");
 		system_hibernate(0, 0);
 	}
@@ -1207,7 +1207,7 @@ void print_system_rtc(enum console_channel ch)
 }
 
 #ifdef CONFIG_CMD_RTC
-static int command_system_rtc(int argc, char **argv)
+static int command_system_rtc(int argc, const char **argv)
 {
 	if (argc == 3 && !strcasecmp(argv[1], "set")) {
 		char *e;
@@ -1224,15 +1224,14 @@ static int command_system_rtc(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(rtc, command_system_rtc,
-		"[set <seconds>]",
-		"Get/set real-time clock");
+DECLARE_CONSOLE_COMMAND(rtc, command_system_rtc, "[set <seconds>]",
+			"Get/set real-time clock");
 
 #ifdef CONFIG_CMD_RTC_ALARM
 /**
  * Test the RTC alarm by setting an interrupt on RTC match.
  */
-static int command_rtc_alarm_test(int argc, char **argv)
+static int command_rtc_alarm_test(int argc, const char **argv)
 {
 	int s = 1, us = 0;
 	char *e;
@@ -1244,13 +1243,11 @@ static int command_rtc_alarm_test(int argc, char **argv)
 		s = strtoi(argv[1], &e, 10);
 		if (*e)
 			return EC_ERROR_PARAM1;
-
 	}
 	if (argc > 2) {
 		us = strtoi(argv[2], &e, 10);
 		if (*e)
 			return EC_ERROR_PARAM2;
-
 	}
 
 	system_set_rtc_alarm(s, us);
@@ -1258,8 +1255,7 @@ static int command_rtc_alarm_test(int argc, char **argv)
 	return EC_SUCCESS;
 }
 DECLARE_CONSOLE_COMMAND(rtc_alarm, command_rtc_alarm_test,
-		"[seconds [microseconds]]",
-		"Test alarm");
+			"[seconds [microseconds]]", "Test alarm");
 #endif /* CONFIG_CMD_RTC_ALARM */
 #endif /* CONFIG_CMD_RTC */
 
@@ -1276,9 +1272,8 @@ static enum ec_status system_rtc_get_value(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_VALUE,
-		system_rtc_get_value,
-		EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_VALUE, system_rtc_get_value,
+		     EC_VER_MASK(0));
 
 static enum ec_status system_rtc_set_value(struct host_cmd_handler_args *args)
 {
@@ -1287,9 +1282,8 @@ static enum ec_status system_rtc_set_value(struct host_cmd_handler_args *args)
 	system_set_rtc(p->time);
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_VALUE,
-		system_rtc_set_value,
-		EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_VALUE, system_rtc_set_value,
+		     EC_VER_MASK(0));
 
 static enum ec_status system_rtc_set_alarm(struct host_cmd_handler_args *args)
 {
@@ -1298,9 +1292,8 @@ static enum ec_status system_rtc_set_alarm(struct host_cmd_handler_args *args)
 	system_set_rtc_alarm(p->time, 0);
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_ALARM,
-		system_rtc_set_alarm,
-		EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_ALARM, system_rtc_set_alarm,
+		     EC_VER_MASK(0));
 
 static enum ec_status system_rtc_get_alarm(struct host_cmd_handler_args *args)
 {
@@ -1311,9 +1304,8 @@ static enum ec_status system_rtc_get_alarm(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_ALARM,
-		system_rtc_get_alarm,
-		EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_ALARM, system_rtc_get_alarm,
+		     EC_VER_MASK(0));
 
 #endif /* CONFIG_HOSTCMD_RTC */
 #ifdef CONFIG_EXTERNAL_STORAGE
@@ -1330,28 +1322,28 @@ void system_jump_to_booter(void)
 	 */
 	switch (system_get_shrspi_image_copy()) {
 	case EC_IMAGE_RW:
-		flash_offset = CONFIG_EC_WRITABLE_STORAGE_OFF +
-				CONFIG_RW_STORAGE_OFF;
+		flash_offset =
+			CONFIG_EC_WRITABLE_STORAGE_OFF + CONFIG_RW_STORAGE_OFF;
 		flash_used = CONFIG_RW_SIZE;
 		break;
 #ifdef CONFIG_RW_B
 	case EC_IMAGE_RW_B:
 		flash_offset = CONFIG_EC_WRITABLE_STORAGE_OFF +
-				CONFIG_RW_B_STORAGE_OFF;
+			       CONFIG_RW_B_STORAGE_OFF;
 		flash_used = CONFIG_RW_SIZE;
 		break;
 #endif
 	case EC_IMAGE_RO:
 	default: /* Jump to RO by default */
-		flash_offset = CONFIG_EC_PROTECTED_STORAGE_OFF +
-				CONFIG_RO_STORAGE_OFF;
+		flash_offset =
+			CONFIG_EC_PROTECTED_STORAGE_OFF + CONFIG_RO_STORAGE_OFF;
 		flash_used = CONFIG_RO_SIZE;
 		break;
 	}
 
 	/* Make sure the reset vector is inside the destination image */
-	addr_entry = *(uintptr_t *)(flash_offset +
-				    CONFIG_MAPPED_STORAGE_BASE + 4);
+	addr_entry =
+		*(uintptr_t *)(flash_offset + CONFIG_MAPPED_STORAGE_BASE + 4);
 
 	/*
 	 * Speed up FW download time by increasing clock freq of EC. It will
@@ -1361,25 +1353,30 @@ void system_jump_to_booter(void)
 
 	/* Bypass for GMDA issue of ROM api utilities */
 #if defined(CHIP_FAMILY_NPCX5)
-	system_download_from_flash(
-		flash_offset,      /* The offset of the data in spi flash */
-		CONFIG_PROGRAM_MEMORY_BASE, /* RAM Addr of downloaded data */
-		flash_used,        /* Number of bytes to download      */
-		addr_entry         /* jump to this address after download */
+	system_download_from_flash(flash_offset, /* The offset of the data in
+						    spi flash */
+				   CONFIG_PROGRAM_MEMORY_BASE, /* RAM Addr of
+								  downloaded
+								  data */
+				   flash_used, /* Number of bytes to download */
+				   addr_entry /* jump to this address after
+						 download */
 	);
 #else
-	download_from_flash(
-		flash_offset,      /* The offset of the data in spi flash */
-		CONFIG_PROGRAM_MEMORY_BASE, /* RAM Addr of downloaded data */
-		flash_used,        /* Number of bytes to download      */
-		SIGN_NO_CHECK,     /* Need CRC check or not               */
-		addr_entry,        /* jump to this address after download */
-		&status            /* Status fo download */
+	download_from_flash(flash_offset, /* The offset of the data in spi flash
+					   */
+			    CONFIG_PROGRAM_MEMORY_BASE, /* RAM Addr of
+							   downloaded data */
+			    flash_used, /* Number of bytes to download      */
+			    SIGN_NO_CHECK, /* Need CRC check or not */
+			    addr_entry, /* jump to this address after download
+					 */
+			    &status /* Status fo download */
 	);
 #endif
 }
 
-uint32_t system_get_lfw_address()
+uint32_t system_get_lfw_address(void)
 {
 	/*
 	 * In A3 version, we don't use little FW anymore
@@ -1410,7 +1407,8 @@ void system_set_image_copy(enum ec_image copy)
 #endif
 	default:
 		CPRINTS("Invalid copy (%d) is requested as a jump destination. "
-			"Change it to %d.", copy, EC_IMAGE_RO);
+			"Change it to %d.",
+			copy, EC_IMAGE_RO);
 		/* Fall through to EC_IMAGE_RO */
 	case EC_IMAGE_RO:
 		SET_BIT(NPCX_FWCTRL, NPCX_FWCTRL_RO_REGION);
diff --git a/chip/npcx/system_chip.h b/chip/npcx/system_chip.h
index 2314f1458a..2ee5f8aff0 100644
--- a/chip/npcx/system_chip.h
+++ b/chip/npcx/system_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,34 +9,34 @@
 #define __CROS_EC_SYSTEM_CHIP_H
 
 /* Flags for BBRM_DATA_INDEX_WAKE */
-#define HIBERNATE_WAKE_MTC        BIT(0)  /* MTC alarm */
-#define HIBERNATE_WAKE_PIN        BIT(1)  /* Wake pin */
-#define HIBERNATE_WAKE_LCT        BIT(2)  /* LCT alarm */
+#define HIBERNATE_WAKE_MTC BIT(0) /* MTC alarm */
+#define HIBERNATE_WAKE_PIN BIT(1) /* Wake pin */
+#define HIBERNATE_WAKE_LCT BIT(2) /* LCT alarm */
 /*
  * Indicate that EC enters hibernation via PSL. When EC wakes up from
  * hibernation and this flag is set, it will check the related status bit to
  * know the actual wake up source. (From LCT or physical wakeup pins)
  */
-#define HIBERNATE_WAKE_PSL        BIT(3)
+#define HIBERNATE_WAKE_PSL BIT(3)
 
 /* Indices for battery-backed ram (BBRAM) data position */
 enum bbram_data_index {
-	BBRM_DATA_INDEX_SCRATCHPAD = 0,        /* General-purpose scratchpad */
+	BBRM_DATA_INDEX_SCRATCHPAD = 0, /* General-purpose scratchpad */
 	BBRM_DATA_INDEX_SAVED_RESET_FLAGS = 4, /* Saved reset flags */
-	BBRM_DATA_INDEX_WAKE = 8,	       /* Wake reasons for hibernate */
-	BBRM_DATA_INDEX_PD0 = 12,	       /* USB-PD saved port0 state */
-	BBRM_DATA_INDEX_PD1 = 13,	       /* USB-PD saved port1 state */
-	BBRM_DATA_INDEX_TRY_SLOT = 14,         /* Vboot EC try slot */
-	BBRM_DATA_INDEX_PD2 = 15,	       /* USB-PD saved port2 state */
+	BBRM_DATA_INDEX_WAKE = 8, /* Wake reasons for hibernate */
+	BBRM_DATA_INDEX_PD0 = 12, /* USB-PD saved port0 state */
+	BBRM_DATA_INDEX_PD1 = 13, /* USB-PD saved port1 state */
+	BBRM_DATA_INDEX_TRY_SLOT = 14, /* Vboot EC try slot */
+	BBRM_DATA_INDEX_PD2 = 15, /* USB-PD saved port2 state */
 	/* Index 16-31 available for future use */
-	BBRM_DATA_INDEX_RAMLOG = 32,	       /* RAM log for Booter */
-	BBRM_DATA_INDEX_PANIC_FLAGS = 35,      /* Flag to indicate validity of
-						* panic data starting at index
-						* 36.
-						*/
-	BBRM_DATA_INDEX_PANIC_BKUP = 36,       /* Panic data (index 35-63)*/
-	BBRM_DATA_INDEX_LCT_TIME = 64,         /* The start time of LCT(4 bytes)
-						*/
+	BBRM_DATA_INDEX_RAMLOG = 32, /* RAM log for Booter */
+	BBRM_DATA_INDEX_PANIC_FLAGS = 35, /* Flag to indicate validity of
+					   * panic data starting at index
+					   * 36.
+					   */
+	BBRM_DATA_INDEX_PANIC_BKUP = 36, /* Panic data (index 35-63)*/
+	BBRM_DATA_INDEX_LCT_TIME = 64, /* The start time of LCT(4 bytes)
+					*/
 };
 
 enum psl_pin_t {
@@ -69,7 +69,7 @@ void system_check_bbram_on_reset(void);
 #if defined(CHIP_FAMILY_NPCX5)
 /* Bypass for GMDA issue of ROM api utilities only on npcx5 series */
 void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr,
-		uint32_t size, uint32_t exeAddr);
+				uint32_t size, uint32_t exeAddr);
 
 /* Begin address for hibernate utility; defined in linker script */
 extern unsigned int __flash_lpfw_start;
diff --git a/chip/npcx/uart.c b/chip/npcx/uart.c
index c158049e6a..bc87b5921e 100644
--- a/chip/npcx/uart.c
+++ b/chip/npcx/uart.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,12 +21,12 @@
 #include "uartn.h"
 #include "util.h"
 
-#define CONSOLE_UART            CONFIG_CONSOLE_UART
+#define CONSOLE_UART CONFIG_CONSOLE_UART
 
 #if CONSOLE_UART
-#define CONSOLE_UART_IRQ        NPCX_IRQ_UART2
+#define CONSOLE_UART_IRQ NPCX_IRQ_UART2
 #else
-#define CONSOLE_UART_IRQ        NPCX_IRQ_UART
+#define CONSOLE_UART_IRQ NPCX_IRQ_UART
 #endif
 
 static int init_done;
@@ -54,7 +54,7 @@ static int altpad_tx_len;
  */
 static timestamp_t last_default_pad_rx_time;
 
-static const uint32_t block_alt_timeout_us = 500*MSEC;
+static const uint32_t block_alt_timeout_us = 500 * MSEC;
 
 #else
 
@@ -209,7 +209,8 @@ static void uart_ec_interrupt(void)
 		}
 		if (uartn_tx_ready(NPCX_UART_PORT0)) {
 			if (altpad_tx_pos < altpad_tx_len)
-				uartn_write_char(NPCX_UART_PORT0,
+				uartn_write_char(
+					NPCX_UART_PORT0,
 					altpad_tx_buf[altpad_tx_pos++]);
 			else
 				uart_tx_stop();
@@ -319,8 +320,8 @@ int uart_alt_pad_write_read(uint8_t *tx, int tx_len, uint8_t *rx, int rx_len,
 	uint32_t start = __hw_clock_source_read();
 	int ret = 0;
 
-	if ((get_time().val - last_default_pad_rx_time.val)
-			< block_alt_timeout_us)
+	if ((get_time().val - last_default_pad_rx_time.val) <
+	    block_alt_timeout_us)
 		return -EC_ERROR_BUSY;
 
 	cflush();
@@ -381,7 +382,6 @@ out:
 #endif
 void uart_init(void)
 {
-
 	uartn_init(CONSOLE_UART);
 	init_done = 1;
 }
diff --git a/chip/npcx/uartn.c b/chip/npcx/uartn.c
index 2269e11e7c..9bcaccd94c 100644
--- a/chip/npcx/uartn.c
+++ b/chip/npcx/uartn.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,60 +17,58 @@
 
 #ifdef NPCX_UART_FIFO_SUPPORT
 /* Enable UART Tx FIFO empty interrupt */
-#define NPCX_UART_TX_EMPTY_INT_EN(n)      \
-		(SET_BIT(NPCX_UFTCTL(n), NPCX_UFTCTL_TEMPTY_EN))
+#define NPCX_UART_TX_EMPTY_INT_EN(n) \
+	(SET_BIT(NPCX_UFTCTL(n), NPCX_UFTCTL_TEMPTY_EN))
 /* True if UART Tx FIFO empty interrupt is enabled */
-#define NPCX_UART_TX_EMPTY_INT_IS_EN(n)   \
-		(IS_BIT_SET(NPCX_UFTCTL(n), NPCX_UFTCTL_TEMPTY_EN))
+#define NPCX_UART_TX_EMPTY_INT_IS_EN(n) \
+	(IS_BIT_SET(NPCX_UFTCTL(n), NPCX_UFTCTL_TEMPTY_EN))
 /* Disable UART Tx FIFO empty interrupt */
-#define NPCX_UART_TX_EMPTY_INT_DIS(n)     \
-		(CLEAR_BIT(NPCX_UFTCTL(n), NPCX_UFTCTL_TEMPTY_EN))
+#define NPCX_UART_TX_EMPTY_INT_DIS(n) \
+	(CLEAR_BIT(NPCX_UFTCTL(n), NPCX_UFTCTL_TEMPTY_EN))
 /* True if the Tx FIFO is not completely full */
-#define NPCX_UART_TX_IS_READY(n)          \
-		(!(GET_FIELD(NPCX_UFTSTS(n), NPCX_UFTSTS_TEMPTY_LVL) == 0))
+#define NPCX_UART_TX_IS_READY(n) \
+	(!(GET_FIELD(NPCX_UFTSTS(n), NPCX_UFTSTS_TEMPTY_LVL) == 0))
 
 /* Enable UART Tx "not" in transmission interrupt */
-#define NPCX_UART_TX_NXMIP_INT_EN(n)      \
-		(SET_BIT(NPCX_UFTCTL(n), NPCX_UFTCTL_NXMIPEN))
+#define NPCX_UART_TX_NXMIP_INT_EN(n) \
+	(SET_BIT(NPCX_UFTCTL(n), NPCX_UFTCTL_NXMIPEN))
 /* Disable UART Tx "not" in transmission interrupt */
-#define NPCX_UART_TX_NXMIP_INT_DIS(n)      \
-		(CLEAR_BIT(NPCX_UFTCTL(n), NPCX_UFTCTL_NXMIPEN))
+#define NPCX_UART_TX_NXMIP_INT_DIS(n) \
+	(CLEAR_BIT(NPCX_UFTCTL(n), NPCX_UFTCTL_NXMIPEN))
 /*
  * True if Tx is in progress
  * (i.e. FIFO is not empty or last byte in TSFT (Transmit Shift register)
  * is not sent)
  */
-#define NPCX_UART_TX_IN_XMIT(n)           \
-		(!IS_BIT_SET(NPCX_UFTSTS(n), NPCX_UFTSTS_NXMIP))
+#define NPCX_UART_TX_IN_XMIT(n) (!IS_BIT_SET(NPCX_UFTSTS(n), NPCX_UFTSTS_NXMIP))
 
 /*
  * Enable to generate interrupt when there is at least one byte
  * in the receive FIFO
  */
-#define NPCX_UART_RX_INT_EN(n)            \
-		(SET_BIT(NPCX_UFRCTL(n), NPCX_UFRCTL_RNEMPTY_EN))
+#define NPCX_UART_RX_INT_EN(n) (SET_BIT(NPCX_UFRCTL(n), NPCX_UFRCTL_RNEMPTY_EN))
 /* True if at least one byte is in the receive FIFO */
-#define NPCX_UART_RX_IS_AVAILABLE(n)      \
-		(IS_BIT_SET(NPCX_UFRSTS(n), NPCX_UFRSTS_RFIFO_NEMPTY_STS))
+#define NPCX_UART_RX_IS_AVAILABLE(n) \
+	(IS_BIT_SET(NPCX_UFRSTS(n), NPCX_UFRSTS_RFIFO_NEMPTY_STS))
 #else
 /* Enable UART Tx buffer empty interrupt */
-#define NPCX_UART_TX_EMPTY_INT_EN(n)      (NPCX_UICTRL(n) |= 0x20)
+#define NPCX_UART_TX_EMPTY_INT_EN(n) (NPCX_UICTRL(n) |= 0x20)
 /* True if UART Tx buffer empty interrupt is enabled */
-#define NPCX_UART_TX_EMPTY_INT_IS_EN(n)   (NPCX_UICTRL(n) & 0x20)
+#define NPCX_UART_TX_EMPTY_INT_IS_EN(n) (NPCX_UICTRL(n) & 0x20)
 /* Disable UART Tx buffer empty interrupt */
-#define NPCX_UART_TX_EMPTY_INT_DIS(n)     (NPCX_UICTRL(n) &= ~0x20)
+#define NPCX_UART_TX_EMPTY_INT_DIS(n) (NPCX_UICTRL(n) &= ~0x20)
 /* True if 1-byte Tx buffer is empty */
-#define NPCX_UART_TX_IS_READY(n)          (NPCX_UICTRL(n) & 0x01)
+#define NPCX_UART_TX_IS_READY(n) (NPCX_UICTRL(n) & 0x01)
 /*
  * True if Tx is in progress
  * (i.e. Tx buffer is not empty or last byte in TSFT (Transmit Shift register)
  * is not sent)
  */
-#define NPCX_UART_TX_IN_XMIT(n)           (NPCX_USTAT(n) & 0x40)
- /* Enable to generate interrupt when there is data in the receive buffer */
-#define NPCX_UART_RX_INT_EN(n)            (NPCX_UICTRL(n) = 0x40)
+#define NPCX_UART_TX_IN_XMIT(n) (NPCX_USTAT(n) & 0x40)
+/* Enable to generate interrupt when there is data in the receive buffer */
+#define NPCX_UART_RX_INT_EN(n) (NPCX_UICTRL(n) = 0x40)
 /* True if there is data in the 1-byte Receive buffer */
-#define NPCX_UART_RX_IS_AVAILABLE(n)      (NPCX_UICTRL(n) & 0x02)
+#define NPCX_UART_RX_IS_AVAILABLE(n) (NPCX_UICTRL(n) & 0x02)
 #endif
 
 struct uart_configs {
@@ -79,9 +77,9 @@ struct uart_configs {
 	uint32_t clk_en_msk;
 };
 static const struct uart_configs uart_cfg[] = {
-	{NPCX_IRQ_UART, CGC_OFFSET_UART, CGC_UART_MASK},
+	{ NPCX_IRQ_UART, CGC_OFFSET_UART, CGC_UART_MASK },
 #ifdef NPCX_SECOND_UART
-	{NPCX_IRQ_UART2, CGC_OFFSET_UART2, CGC_UART2_MASK},
+	{ NPCX_IRQ_UART2, CGC_OFFSET_UART2, CGC_UART2_MASK },
 #endif
 };
 BUILD_ASSERT(ARRAY_SIZE(uart_cfg) == UART_MODULE_COUNT);
@@ -144,7 +142,7 @@ void uartn_tx_start(uint8_t uart_num)
 void uartn_enable_tx_complete_int(uint8_t uart_num, uint8_t enable)
 {
 	enable ? NPCX_UART_TX_NXMIP_INT_EN(uart_num) :
-		NPCX_UART_TX_NXMIP_INT_DIS(uart_num);
+		 NPCX_UART_TX_NXMIP_INT_DIS(uart_num);
 }
 #endif
 
@@ -198,7 +196,7 @@ int uartn_read_char(uint8_t uart_num)
 
 void uartn_clear_rx_fifo(int channel)
 {
-	int scratch __attribute__ ((unused));
+	int scratch __attribute__((unused));
 
 	/* If '1',  that means there is RX data on the FIFO register */
 	while (NPCX_UART_RX_IS_AVAILABLE(channel))
@@ -211,9 +209,9 @@ static void uartn_set_fifo_mode(uint8_t uart_num)
 	/* Enable the UART FIFO mode */
 	SET_BIT(NPCX_UMDSL(uart_num), NPCX_UMDSL_FIFO_MD);
 	/* Disable all Tx interrupts */
-	NPCX_UFTCTL(uart_num) &= ~(BIT(NPCX_UFTCTL_TEMPTY_LVL_EN) |
-					BIT(NPCX_UFTCTL_TEMPTY_EN) |
-					BIT(NPCX_UFTCTL_NXMIPEN));
+	NPCX_UFTCTL(uart_num) &=
+		~(BIT(NPCX_UFTCTL_TEMPTY_LVL_EN) | BIT(NPCX_UFTCTL_TEMPTY_EN) |
+		  BIT(NPCX_UFTCTL_NXMIPEN));
 }
 
 #endif
diff --git a/chip/npcx/uartn.h b/chip/npcx/uartn.h
index e5326f72b8..ce111f11d9 100644
--- a/chip/npcx/uartn.h
+++ b/chip/npcx/uartn.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,7 +22,7 @@ void uartn_init(uint8_t uart_num);
  */
 void uartn_tx_start(uint8_t uart_num);
 
- /* Disable the UART transmit interrupt. */
+/* Disable the UART transmit interrupt. */
 void uartn_tx_stop(uint8_t uart_num, uint8_t sleep_ena);
 
 /* Flush the transmit FIFO. */
@@ -62,4 +62,4 @@ void uartn_rx_int_en(uint8_t uart_num);
 void uartn_wui_en(uint8_t uart_num);
 /* Enable/disable Tx NXMIP (No Transmit In Progress) interrupt */
 void uartn_enable_tx_complete_int(uint8_t uart_num, uint8_t enable);
-#endif  /* __CROS_EC_UARTN_H */
+#endif /* __CROS_EC_UARTN_H */
diff --git a/chip/npcx/watchdog.c b/chip/npcx/watchdog.c
index 55b8df8c1c..8ae9ee0474 100644
--- a/chip/npcx/watchdog.c
+++ b/chip/npcx/watchdog.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -108,18 +108,18 @@ void IRQ_HANDLER(ITIM_INT(ITIM_WDG_NO))(void)
 {
 	/* Naked call so we can extract raw LR and SP */
 	asm volatile("mov r0, lr\n"
-			"mov r1, sp\n"
-			/* Must push registers in pairs to keep 64-bit aligned
-			 * stack for ARM EABI.  This also conveninently saves
-			 * R0=LR so we can pass it to task_resched_if_needed. */
-			"push {r0, lr}\n"
-			"bl watchdog_check\n"
-			"pop {r0, lr}\n"
-			"b task_resched_if_needed\n");
+		     "mov r1, sp\n"
+		     /* Must push registers in pairs to keep 64-bit aligned
+		      * stack for ARM EABI.  This also conveninently saves
+		      * R0=LR so we can pass it to task_resched_if_needed. */
+		     "push {r0, lr}\n"
+		     "bl watchdog_check\n"
+		     "pop {r0, lr}\n"
+		     "b task_resched_if_needed\n");
 }
 const struct irq_priority __keep IRQ_PRIORITY(ITIM_INT(ITIM_WDG_NO))
-__attribute__((section(".rodata.irqprio")))
-= {ITIM_INT(ITIM_WDG_NO), 0};
+	__attribute__((section(".rodata.irqprio"))) = { ITIM_INT(ITIM_WDG_NO),
+							0 };
 /* put the watchdog at the highest priority */
 
 void watchdog_reload(void)
diff --git a/chip/npcx/wov.c b/chip/npcx/wov.c
index 5c3e915200..1ae1afe71d 100644
--- a/chip/npcx/wov.c
+++ b/chip/npcx/wov.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,7 +26,7 @@
 #define CPRINTS(...)
 #else
 #define CPUTS(outstr) cputs(CC_AUDIO_CODEC, outstr)
-#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ##args)
 #endif
 
 /* WOV FIFO status. */
@@ -64,106 +64,106 @@
 #define WOV_FMUL2_CLK_TUNING_DELAY_TIME (4 * 1000)
 
 /* The size of RAM buffer to store the voice data */
-#define VOICE_BUF_SIZE    16000
+#define VOICE_BUF_SIZE 16000
 
 /* PLL setting options. */
 struct wov_pll_set_options_val {
-	uint8_t pll_indv;     /* Input Divider */
-	uint16_t pll_fbdv;    /* Feedback Divider */
-	uint8_t pll_otdv1;    /* Output devide 1. */
-	uint8_t pll_otdv2;    /* Output devide 2. */
+	uint8_t pll_indv; /* Input Divider */
+	uint16_t pll_fbdv; /* Feedback Divider */
+	uint8_t pll_otdv1; /* Output devide 1. */
+	uint8_t pll_otdv2; /* Output devide 2. */
 	uint32_t pll_ext_div; /* Index for the table pll_ext_div */
 };
 
 /* PLL External Divider Load Values. */
 struct wov_pll_ext_div_val {
-	uint8_t pll_ediv;    /* Required PLL external divider */
+	uint8_t pll_ediv; /* Required PLL external divider */
 	uint8_t pll_ediv_dc; /* Required PLL external divider DC */
 };
 
 static const struct wov_pll_ext_div_val pll_ext_div[] = {
-	{0x2F, 0x78}, /* 12 */
-	{0x57, 0x7C}, /* 13 */
-	{0x2B, 0x7C}, /* 14 */
-	{0x55, 0x7E}, /* 15 */
-	{0x2A, 0x7E}, /* 16 */
-	{0x15, 0x7F}, /* 17 */
-	{0x4A, 0x7F}, /* 18 */
-	{0x65, 0x3F}, /* 19 */
-	{0x32, 0x3F}, /* 20 */
-	{0x19, 0x5F}, /* 21 */
-	{0x4C, 0x5F}, /* 22 */
-	{0x66, 0x2F}, /* 23 */
-	{0x73, 0x2F}, /* 24 */
-	{0x39, 0x57}, /* 25 */
-	{0x5C, 0x57}, /* 26 */
-	{0x6E, 0x2B}, /* 27 */
-	{0x77, 0x2B}, /* 28 */
-	{0x3B, 0x55}, /* 29 */
-	{0x5D, 0x55}, /* 30 */
-	{0x2E, 0x2A}, /* 31 */
-	{0x17, 0x2A}, /* 32 */
-	{0x4B, 0x15}, /* 33 */
-	{0x25, 0x15}, /* 34 */
-	{0x52, 0x4A}, /* 35 */
-	{0x69, 0x4A}, /* 36 */
-	{0x34, 0x65}, /* 37 */
-	{0x1A, 0x65}, /* 38 */
-	{0x0D, 0x32}, /* 39 */
-	{0x46, 0x32}, /* 40 */
-	{0x63, 0x19}, /* 41 */
-	{0x31, 0x19}, /* 42 */
-	{0x58, 0x4C}, /* 43 */
-	{0x6C, 0x4C}, /* 44 */
-	{0x76, 0x66}, /* 45 */
-	{0x7B, 0x66}, /* 46 */
-	{0x3D, 0x73}, /* 47 */
-	{0x5E, 0x73}, /* 48 */
-	{0x6F, 0x39}, /* 49 */
-	{0x37, 0x39}, /* 50 */
-	{0x5B, 0x5C}, /* 51 */
-	{0x2D, 0x5C}, /* 52 */
-	{0x56, 0x6E}, /* 53 */
-	{0x6B, 0x6E}, /* 54 */
-	{0x35, 0x77}, /* 55 */
-	{0x5A, 0x77}, /* 56 */
-	{0x6D, 0x3B}, /* 57 */
-	{0x36, 0x3B}, /* 58 */
-	{0x1B, 0x5D}, /* 59 */
-	{0x4D, 0x5D}, /* 60 */
-	{0x26, 0x2E}, /* 61 */
-	{0x13, 0x2E}, /* 62 */
-	{0x49, 0x17}, /* 63 */
-	{0x24, 0x17}, /* 64 */
-	{0x12, 0x4B}, /* 65 */
-	{0x09, 0x4B}, /* 66 */
-	{0x44, 0x25}  /* 67 */
+	{ 0x2F, 0x78 }, /* 12 */
+	{ 0x57, 0x7C }, /* 13 */
+	{ 0x2B, 0x7C }, /* 14 */
+	{ 0x55, 0x7E }, /* 15 */
+	{ 0x2A, 0x7E }, /* 16 */
+	{ 0x15, 0x7F }, /* 17 */
+	{ 0x4A, 0x7F }, /* 18 */
+	{ 0x65, 0x3F }, /* 19 */
+	{ 0x32, 0x3F }, /* 20 */
+	{ 0x19, 0x5F }, /* 21 */
+	{ 0x4C, 0x5F }, /* 22 */
+	{ 0x66, 0x2F }, /* 23 */
+	{ 0x73, 0x2F }, /* 24 */
+	{ 0x39, 0x57 }, /* 25 */
+	{ 0x5C, 0x57 }, /* 26 */
+	{ 0x6E, 0x2B }, /* 27 */
+	{ 0x77, 0x2B }, /* 28 */
+	{ 0x3B, 0x55 }, /* 29 */
+	{ 0x5D, 0x55 }, /* 30 */
+	{ 0x2E, 0x2A }, /* 31 */
+	{ 0x17, 0x2A }, /* 32 */
+	{ 0x4B, 0x15 }, /* 33 */
+	{ 0x25, 0x15 }, /* 34 */
+	{ 0x52, 0x4A }, /* 35 */
+	{ 0x69, 0x4A }, /* 36 */
+	{ 0x34, 0x65 }, /* 37 */
+	{ 0x1A, 0x65 }, /* 38 */
+	{ 0x0D, 0x32 }, /* 39 */
+	{ 0x46, 0x32 }, /* 40 */
+	{ 0x63, 0x19 }, /* 41 */
+	{ 0x31, 0x19 }, /* 42 */
+	{ 0x58, 0x4C }, /* 43 */
+	{ 0x6C, 0x4C }, /* 44 */
+	{ 0x76, 0x66 }, /* 45 */
+	{ 0x7B, 0x66 }, /* 46 */
+	{ 0x3D, 0x73 }, /* 47 */
+	{ 0x5E, 0x73 }, /* 48 */
+	{ 0x6F, 0x39 }, /* 49 */
+	{ 0x37, 0x39 }, /* 50 */
+	{ 0x5B, 0x5C }, /* 51 */
+	{ 0x2D, 0x5C }, /* 52 */
+	{ 0x56, 0x6E }, /* 53 */
+	{ 0x6B, 0x6E }, /* 54 */
+	{ 0x35, 0x77 }, /* 55 */
+	{ 0x5A, 0x77 }, /* 56 */
+	{ 0x6D, 0x3B }, /* 57 */
+	{ 0x36, 0x3B }, /* 58 */
+	{ 0x1B, 0x5D }, /* 59 */
+	{ 0x4D, 0x5D }, /* 60 */
+	{ 0x26, 0x2E }, /* 61 */
+	{ 0x13, 0x2E }, /* 62 */
+	{ 0x49, 0x17 }, /* 63 */
+	{ 0x24, 0x17 }, /* 64 */
+	{ 0x12, 0x4B }, /* 65 */
+	{ 0x09, 0x4B }, /* 66 */
+	{ 0x44, 0x25 } /* 67 */
 };
 
 /* WOV interrupts */
 static const uint8_t wov_interupts[] = {
-	0,  /* VAD_INTEN */
-	1,  /* VAD_WKEN */
-	8,  /* CFIFO_NE_IE */
-	9,  /* CFIFO_OIT_IE */
+	0, /* VAD_INTEN */
+	1, /* VAD_WKEN */
+	8, /* CFIFO_NE_IE */
+	9, /* CFIFO_OIT_IE */
 	10, /* CFIFO_OWT_WE */
 	11, /* CFIFO_OVRN_IE */
 	12, /* I2S_FIFO_OVRN_IE */
-	13  /* I2S_FIFO_UNDRN_IE */
+	13 /* I2S_FIFO_UNDRN_IE */
 };
 
 struct wov_ppl_divider {
 	uint16_t pll_frame_len; /* PLL frame length. */
-	uint16_t pll_fbdv;      /* PLL feedback divider. */
-	uint8_t pll_indv;       /* PLL Input Divider. */
-	uint8_t pll_otdv1;      /* PLL Output Divider 1. */
-	uint8_t pll_otdv2;      /* PLL Output Divider 2. */
-	uint8_t pll_ediv;       /* PLL External Divide Factor. */
+	uint16_t pll_fbdv; /* PLL feedback divider. */
+	uint8_t pll_indv; /* PLL Input Divider. */
+	uint8_t pll_otdv1; /* PLL Output Divider 1. */
+	uint8_t pll_otdv2; /* PLL Output Divider 2. */
+	uint8_t pll_ediv; /* PLL External Divide Factor. */
 };
 
 struct wov_cfifo_buf {
 	uint32_t *buf; /* Pointer to a buffer. */
-	int size;      /* Buffer size in words. */
+	int size; /* Buffer size in words. */
 };
 
 struct wov_config wov_conf;
@@ -205,11 +205,11 @@ void wov_cfifo_read_handler_l(uint32_t num_elements)
 	cfifo_buf.size -= num_elements;
 }
 
-static enum ec_error_list wov_calc_pll_div_s(int32_t d_in,
-					int32_t total_div, int32_t vco_freq,
-					struct wov_ppl_divider *pll_div)
+static enum ec_error_list wov_calc_pll_div_s(int32_t d_in, int32_t total_div,
+					     int32_t vco_freq,
+					     struct wov_ppl_divider *pll_div)
 {
-	int32_t	 d_1, d_2, d_e;
+	int32_t d_1, d_2, d_e;
 
 	/*
 	 * Please see comments in wov_calc_pll_div_l function below.
@@ -221,10 +221,10 @@ static enum ec_error_list wov_calc_pll_div_s(int32_t d_in,
 					continue;
 
 				if (total_div == (d_in * d_e * d_1 * d_2)) {
-					pll_div->pll_indv  = d_in;
+					pll_div->pll_indv = d_in;
 					pll_div->pll_otdv1 = d_1;
 					pll_div->pll_otdv2 = d_2;
-					pll_div->pll_ediv  = d_e;
+					pll_div->pll_ediv = d_e;
 					return EC_SUCCESS;
 				}
 			}
@@ -243,7 +243,8 @@ static enum ec_error_list wov_calc_pll_div_s(int32_t d_in,
  * @return  None
  */
 static enum ec_error_list wov_calc_pll_div_l(uint32_t i2s_clk_freq,
-			uint32_t sample_rate, struct wov_ppl_divider *pll_div)
+					     uint32_t sample_rate,
+					     struct wov_ppl_divider *pll_div)
 {
 	int32_t d_f;
 	int32_t total_div;
@@ -292,12 +293,11 @@ static enum ec_error_list wov_calc_pll_div_l(uint32_t i2s_clk_freq,
 				if ((vco_freq < 500) || (vco_freq > 1600))
 					continue;
 				if (wov_calc_pll_div_s(d_in, total_div,
-						vco_freq, pll_div) ==
-						EC_SUCCESS) {
-					pll_div->pll_fbdv  = d_f;
+						       vco_freq,
+						       pll_div) == EC_SUCCESS) {
+					pll_div->pll_fbdv = d_f;
 					return EC_SUCCESS;
 				}
-
 			}
 		}
 	}
@@ -340,12 +340,13 @@ static enum ec_error_list wov_set_i2s_config_l(void)
 	int32_t start_delay_0, start_delay_1;
 
 	ret_code = wov_calc_pll_div_l(wov_conf.i2s_clock,
-				wov_conf.sample_per_sec, &pll_div);
+				      wov_conf.sample_per_sec, &pll_div);
 	if (ret_code == EC_SUCCESS) {
 		/* Configure the PLL. */
-		ret_code = wov_pll_clk_div_config(
-			pll_div.pll_otdv1, pll_div.pll_otdv2, pll_div.pll_fbdv,
-			pll_div.pll_indv);
+		ret_code = wov_pll_clk_div_config(pll_div.pll_otdv1,
+						  pll_div.pll_otdv2,
+						  pll_div.pll_fbdv,
+						  pll_div.pll_indv);
 		if (ret_code != EC_SUCCESS)
 			return ret_code;
 
@@ -414,10 +415,10 @@ static enum ec_error_list wov_set_i2s_config_l(void)
 		udelay(100);
 
 		ret_code = wov_i2s_channel_config(0, wov_conf.bit_depth,
-					trigger_0, start_delay_0);
+						  trigger_0, start_delay_0);
 
 		ret_code = wov_i2s_channel_config(1, wov_conf.bit_depth,
-					trigger_1, start_delay_1);
+						  trigger_1, start_delay_1);
 	}
 
 	return EC_SUCCESS;
@@ -471,14 +472,14 @@ static enum ec_error_list wov_set_mic_source_l(void)
 	case WOV_SRC_LEFT:
 		if (wov_conf.bit_depth == 16)
 			SET_FIELD(NPCX_WOV_FIFO_CNT,
-				NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x00);
+				  NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x00);
 		else
 			SET_FIELD(NPCX_WOV_FIFO_CNT,
-				NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x02);
+				  NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x02);
 		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_LEFT,
-				0x01);
+			  0x01);
 		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_RIGHT,
-				0x01);
+			  0x01);
 		apm_digital_mixer_config(APM_OUT_MIX_NORMAL_INPUT,
 					 APM_OUT_MIX_NO_INPUT);
 		apm_set_vad_input_channel(APM_IN_LEFT);
@@ -493,11 +494,11 @@ static enum ec_error_list wov_set_mic_source_l(void)
 			SET_FIELD(NPCX_WOV_FIFO_CNT,
 				  NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x02);
 		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_LEFT,
-				0x01);
+			  0x01);
 		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_RIGHT,
-				0x01);
+			  0x01);
 		apm_digital_mixer_config(APM_OUT_MIX_CROSS_INPUT,
-					APM_OUT_MIX_NO_INPUT);
+					 APM_OUT_MIX_NO_INPUT);
 		apm_set_vad_input_channel(APM_IN_RIGHT);
 		wov_i2s_channel1_disable(1);
 		break;
@@ -505,16 +506,16 @@ static enum ec_error_list wov_set_mic_source_l(void)
 	case WOV_SRC_MONO:
 		if (wov_conf.bit_depth == 16)
 			SET_FIELD(NPCX_WOV_FIFO_CNT,
-				NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x01);
+				  NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x01);
 		else
 			SET_FIELD(NPCX_WOV_FIFO_CNT,
-				NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x03);
+				  NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x03);
 		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_LEFT,
-				0x02);
+			  0x02);
 		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_RIGHT,
-				0x02);
+			  0x02);
 		apm_digital_mixer_config(APM_OUT_MIX_NORMAL_INPUT,
-					APM_OUT_MIX_NORMAL_INPUT);
+					 APM_OUT_MIX_NORMAL_INPUT);
 		apm_set_vad_input_channel(APM_IN_AVERAGE_LEFT_RIGHT);
 		wov_i2s_channel1_disable(0);
 		break;
@@ -522,14 +523,14 @@ static enum ec_error_list wov_set_mic_source_l(void)
 	case WOV_SRC_STEREO:
 		if (wov_conf.bit_depth == 16)
 			SET_FIELD(NPCX_WOV_FIFO_CNT,
-				NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x01);
+				  NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x01);
 		else
 			SET_FIELD(NPCX_WOV_FIFO_CNT,
-				NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x03);
+				  NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x03);
 		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_LEFT,
-				0x01);
+			  0x01);
 		SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_RIGHT,
-				0x01);
+			  0x01);
 		apm_digital_mixer_config(APM_OUT_MIX_NORMAL_INPUT,
 					 APM_OUT_MIX_NORMAL_INPUT);
 		wov_i2s_channel1_disable(0);
@@ -586,7 +587,7 @@ static void wov_interrupt_handler(void)
 
 	wov_inten = GET_FIELD(NPCX_WOV_WOV_INTEN, NPCX_WOV_STATUS_BITS);
 	wov_status = wov_inten &
-			GET_FIELD(NPCX_WOV_STATUS, NPCX_WOV_STATUS_BITS);
+		     GET_FIELD(NPCX_WOV_STATUS, NPCX_WOV_STATUS_BITS);
 
 	/*
 	 * Voice activity detected.
@@ -602,7 +603,7 @@ static void wov_interrupt_handler(void)
 		WOV_CALLBACK(WOV_EVENT_ERROR_CORE_FIFO_OVERRUN);
 		wov_core_fifo_reset();
 	} else if (WOV_IS_CFIFO_INT_THRESHOLD(wov_status) &&
-				(cfifo_buf.buf != NULL)) {
+		   (cfifo_buf.buf != NULL)) {
 		/*
 		 * Core FIFO threshold or FIFO not empty event occurred.
 		 * - Read data from core FIFO to the buffer.
@@ -635,7 +636,6 @@ static void wov_interrupt_handler(void)
 		wov_i2s_fifo_reset();
 	}
 
-
 	/* Clear the WoV status register. */
 	SET_FIELD(NPCX_WOV_STATUS, NPCX_WOV_STATUS_BITS, wov_status);
 }
@@ -651,19 +651,17 @@ DECLARE_IRQ(NPCX_IRQ_WOV, wov_interrupt_handler, 4);
 static void wov_fmul2_enable(int enable)
 {
 	if (enable) {
-
 		/* If clock disabled, then enable it. */
 		if (IS_BIT_SET(NPCX_FMUL2_FM2CTRL,
-					NPCX_FMUL2_FM2CTRL_FMUL2_DIS)) {
+			       NPCX_FMUL2_FM2CTRL_FMUL2_DIS)) {
 			/* Enable clock tuning. */
 			CLEAR_BIT(NPCX_FMUL2_FM2CTRL,
-					NPCX_FMUL2_FM2CTRL_TUNE_DIS);
+				  NPCX_FMUL2_FM2CTRL_TUNE_DIS);
 			/* Enable clock. */
 			CLEAR_BIT(NPCX_FMUL2_FM2CTRL,
-					NPCX_FMUL2_FM2CTRL_FMUL2_DIS);
+				  NPCX_FMUL2_FM2CTRL_FMUL2_DIS);
 
 			udelay(WOV_FMUL2_CLK_TUNING_DELAY_TIME);
-
 		}
 	} else
 		SET_BIT(NPCX_FMUL2_FM2CTRL, NPCX_FMUL2_FM2CTRL_FMUL2_DIS);
@@ -688,7 +686,7 @@ void wov_fmul2_conf_tuning(void)
 {
 	/* Check if FMUL2 is enabled, then do nothing. */
 	if (IS_BIT_SET(NPCX_FMUL2_FM2CTRL, NPCX_FMUL2_FM2CTRL_FMUL2_DIS) ==
-			0x00)
+	    0x00)
 		return;
 
 	/* Enable clock tuning. */
@@ -968,7 +966,6 @@ void wov_set_clk_selection(enum wov_clk_src_sel clk_src)
 		wov_fmul2_enable(0);
 	else
 		wov_pll_enable(0);
-
 }
 
 /**
@@ -981,9 +978,9 @@ void wov_set_clk_selection(enum wov_clk_src_sel clk_src)
  *                                PLL External Divider Load Values table.
  * @return  EC_ERROR_INVAL or EC_SUCCESS
  */
-enum ec_error_list wov_pll_clk_ext_div_config(
-	enum wov_pll_ext_div_sel ext_div_sel,
-	uint32_t div_factor)
+enum ec_error_list
+wov_pll_clk_ext_div_config(enum wov_pll_ext_div_sel ext_div_sel,
+			   uint32_t div_factor)
 {
 	/* Sets the clock division factor for the PLL external divider.
 	 * The divide factor should be in the range of 2 to 67.
@@ -1045,13 +1042,13 @@ void wov_pll_enable(int enable)
  * @return  EC_ERROR_INVAL or EC_SUCCESS
  */
 enum ec_error_list wov_pll_clk_div_config(uint32_t out_div_1,
-					uint32_t out_div_2,
-					uint32_t feedback_div,
-					uint32_t in_div)
+					  uint32_t out_div_2,
+					  uint32_t feedback_div,
+					  uint32_t in_div)
 {
 	/* Parameter check. */
-	if ((out_div_1 < 1) || (out_div_1 > 7) ||
-		(out_div_2 < 1) || (out_div_2 > 7))
+	if ((out_div_1 < 1) || (out_div_1 > 7) || (out_div_2 < 1) ||
+	    (out_div_2 > 7))
 		return EC_ERROR_INVAL;
 
 	/*
@@ -1255,7 +1252,7 @@ int wov_set_buffer(uint32_t *buf, int size_in_words)
 
 	cfifo_threshold = wov_get_cfifo_threshold_l();
 	if (size_in_words !=
-		((size_in_words / cfifo_threshold) * cfifo_threshold))
+	    ((size_in_words / cfifo_threshold) * cfifo_threshold))
 		return EC_ERROR_INVAL;
 
 	cfifo_buf.buf = buf;
@@ -1298,21 +1295,17 @@ void wov_apm_active(int enable)
  * @return  EC_ERROR_INVAL or EC_SUCCESS
  */
 enum ec_error_list wov_i2s_global_config(
-	enum wov_floating_mode i2s_hiz_data,
-	enum wov_floating_mode i2s_hiz,
-	enum wov_clk_inverted_mode clk_invert,
-	int out_pull_en,
-	enum wov_pull_upd_down_sel out_pull_mode,
-	int in_pull_en,
-	enum wov_pull_upd_down_sel in_pull_mode,
-	enum wov_test_mode test_mode)
+	enum wov_floating_mode i2s_hiz_data, enum wov_floating_mode i2s_hiz,
+	enum wov_clk_inverted_mode clk_invert, int out_pull_en,
+	enum wov_pull_upd_down_sel out_pull_mode, int in_pull_en,
+	enum wov_pull_upd_down_sel in_pull_mode, enum wov_test_mode test_mode)
 {
 	/* Check the parameters correctness. */
 	if ((i2s_hiz_data == WOV_FLOATING) &&
-		((GET_FIELD(NPCX_WOV_I2S_CNTL(0),
-				NPCX_WOV_I2S_CNTL_I2S_ST_DEL) == 0) ||
-		(GET_FIELD(NPCX_WOV_I2S_CNTL(1),
-				NPCX_WOV_I2S_CNTL_I2S_ST_DEL) == 0)))
+	    ((GET_FIELD(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL_I2S_ST_DEL) ==
+	      0) ||
+	     (GET_FIELD(NPCX_WOV_I2S_CNTL(1), NPCX_WOV_I2S_CNTL_I2S_ST_DEL) ==
+	      0)))
 		return EC_ERROR_INVAL;
 
 	/* Set the parameters. */
@@ -1375,9 +1368,9 @@ enum ec_error_list wov_i2s_global_config(
  * @return  EC_ERROR_INVAL or EC_SUCCESS
  */
 enum ec_error_list wov_i2s_channel_config(uint32_t channel_num,
-					uint32_t bit_count,
-					enum wov_i2s_chan_trigger trigger,
-					int32_t start_delay)
+					  uint32_t bit_count,
+					  enum wov_i2s_chan_trigger trigger,
+					  int32_t start_delay)
 {
 	/* Check the parameters correctnes. */
 	if ((channel_num != 0) && (channel_num != 1))
@@ -1392,7 +1385,7 @@ enum ec_error_list wov_i2s_channel_config(uint32_t channel_num,
 
 	/* Set the parameters. */
 	SET_FIELD(NPCX_WOV_I2S_CNTL(channel_num), NPCX_WOV_I2S_CNTL_I2S_BCNT,
-			(bit_count - 1));
+		  (bit_count - 1));
 
 	if (trigger == WOV_I2S_SAMPLED_1_AFTER_0)
 		CLEAR_BIT(NPCX_WOV_I2S_CNTL(channel_num),
@@ -1459,8 +1452,8 @@ int wov_set_sample_depth(int bits_num)
 	if (wov_conf.mode != WOV_MODE_OFF)
 		return EC_ERROR_INVALID_CONFIG;
 
-	if ((bits_num != 16) && (bits_num != 18) &&
-		(bits_num != 20) && (bits_num != 24))
+	if ((bits_num != 16) && (bits_num != 18) && (bits_num != 20) &&
+	    (bits_num != 24))
 		return EC_ERROR_INVAL;
 
 	wov_conf.bit_depth = bits_num;
@@ -1529,8 +1522,8 @@ void wov_set_gain(int left_chan_gain, int right_chan_gain)
 	wov_conf.left_chan_gain = left_chan_gain;
 	wov_conf.right_chan_gain = right_chan_gain;
 
-	(void) apm_adc_gain_config(APM_ADC_CHAN_GAINS_INDEPENDENT,
-				left_chan_gain, right_chan_gain);
+	(void)apm_adc_gain_config(APM_ADC_CHAN_GAINS_INDEPENDENT,
+				  left_chan_gain, right_chan_gain);
 }
 
 /**
@@ -1571,10 +1564,10 @@ void wov_enable_agc(int enable)
  * @param min_applied_gain      - Minimum Gain Value to apply to the ADC path.
  * @return  EC_ERROR_INVAL or EC_SUCCESS
  */
-enum ec_error_list wov_set_agc_config(int stereo, float target,
-				int noise_gate_threshold, uint8_t hold_time,
-				uint16_t attack_time, uint16_t decay_time,
-				float max_applied_gain, float min_applied_gain)
+enum ec_error_list
+wov_set_agc_config(int stereo, float target, int noise_gate_threshold,
+		   uint8_t hold_time, uint16_t attack_time, uint16_t decay_time,
+		   float max_applied_gain, float min_applied_gain)
 {
 	int target_code;
 	int ngth_code;
@@ -1607,7 +1600,7 @@ enum ec_error_list wov_set_agc_config(int stereo, float target,
 		return EC_ERROR_INVAL;
 
 	for (attack_time_code = 0; attack_time_code <= 0x0F;
-			attack_time_code++) {
+	     attack_time_code++) {
 		if (((attack_time_code + 1) * 32) == attack_time)
 			break;
 	}
@@ -1622,15 +1615,15 @@ enum ec_error_list wov_set_agc_config(int stereo, float target,
 		return EC_ERROR_INVAL;
 
 	for (max_applied_gain_code = 0; max_applied_gain_code < 16;
-			max_applied_gain_code++) {
+	     max_applied_gain_code++) {
 		if ((max_applied_gain_code * 1.5) == max_applied_gain)
 			break;
 	}
 	if (max_applied_gain_code == 16) {
 		for (max_applied_gain_code = 18; max_applied_gain_code < 32;
-				max_applied_gain_code++) {
+		     max_applied_gain_code++) {
 			if (((max_applied_gain_code * 1.5) - 4) ==
-					max_applied_gain)
+			    max_applied_gain)
 				break;
 		}
 	}
@@ -1638,15 +1631,15 @@ enum ec_error_list wov_set_agc_config(int stereo, float target,
 		return EC_ERROR_INVAL;
 
 	for (min_applied_gain_code = 0; min_applied_gain_code < 16;
-			min_applied_gain_code++) {
+	     min_applied_gain_code++) {
 		if ((min_applied_gain_code * 1.5) == min_applied_gain)
 			break;
 	}
 	if (min_applied_gain_code == 16) {
 		for (min_applied_gain_code = 18; min_applied_gain_code < 32;
-				min_applied_gain_code++) {
+		     min_applied_gain_code++) {
 			if (((min_applied_gain_code * 1.5) - 4) ==
-					min_applied_gain)
+			    min_applied_gain)
 				break;
 		}
 	}
@@ -1654,14 +1647,14 @@ enum ec_error_list wov_set_agc_config(int stereo, float target,
 		return EC_ERROR_INVAL;
 
 	gain_cfg.stereo_enable = stereo,
-	gain_cfg.agc_target = (enum apm_adc_target_out_level) target_code;
+	gain_cfg.agc_target = (enum apm_adc_target_out_level)target_code;
 	gain_cfg.nois_gate_en = (noise_gate_threshold != 0);
-	gain_cfg.nois_gate_thold = (enum apm_noise_gate_threshold) ngth_code;
-	gain_cfg.hold_time = (enum apm_agc_adj_hold_time) hold_time;
-	gain_cfg.attack_time = (enum apm_gain_ramp_time) attack_time_code;
-	gain_cfg.decay_time = (enum apm_gain_ramp_time) decay_time_code;
-	gain_cfg.gain_max = (enum apm_gain_values) max_applied_gain_code;
-	gain_cfg.gain_min = (enum apm_gain_values) min_applied_gain_code;
+	gain_cfg.nois_gate_thold = (enum apm_noise_gate_threshold)ngth_code;
+	gain_cfg.hold_time = (enum apm_agc_adj_hold_time)hold_time;
+	gain_cfg.attack_time = (enum apm_gain_ramp_time)attack_time_code;
+	gain_cfg.decay_time = (enum apm_gain_ramp_time)decay_time_code;
+	gain_cfg.gain_max = (enum apm_gain_values)max_applied_gain_code;
+	gain_cfg.gain_min = (enum apm_gain_values)min_applied_gain_code;
 
 	ret_code = apm_adc_auto_gain_config(&gain_cfg);
 
@@ -1676,7 +1669,6 @@ enum ec_error_list wov_set_agc_config(int stereo, float target,
  */
 int wov_set_vad_sensitivity(int sensitivity_db)
 {
-
 	if ((sensitivity_db < 0) || (sensitivity_db > 31))
 		return EC_ERROR_INVAL;
 
@@ -1752,27 +1744,27 @@ void wov_set_i2s_bclk(uint32_t i2s_clock)
  * @return  EC error code.
  */
 enum ec_error_list wov_set_i2s_tdm_config(int ch0_delay, int ch1_delay,
-				uint32_t flags)
+					  uint32_t flags)
 {
 	if (wov_conf.mode != WOV_MODE_OFF)
 		return EC_ERROR_INVALID_CONFIG;
 
-	if ((ch0_delay < 0) || (ch0_delay > 496) ||
-		(ch1_delay < -1) || (ch1_delay > 496))
+	if ((ch0_delay < 0) || (ch0_delay > 496) || (ch1_delay < -1) ||
+	    (ch1_delay > 496))
 		return EC_ERROR_INVAL;
 
 	wov_conf.i2s_start_delay_0 = ch0_delay;
 	wov_conf.i2s_start_delay_1 = ch1_delay;
 
 	SET_FIELD(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL_I2S_ST_DEL,
-			ch0_delay);
+		  ch0_delay);
 
 	if (ch1_delay == -1)
 		wov_i2s_channel1_disable(1);
 	else {
 		wov_i2s_channel1_disable(0);
 		SET_FIELD(NPCX_WOV_I2S_CNTL(1), NPCX_WOV_I2S_CNTL_I2S_ST_DEL,
-			ch1_delay);
+			  ch1_delay);
 	}
 
 	if (flags & 0x0001)
@@ -1820,10 +1812,10 @@ void wov_handle_event(enum wov_events event)
 }
 
 #ifdef DEBUG_AUDIO_CODEC
-static uint32_t voice_buffer[VOICE_BUF_SIZE] = {0};
+static uint32_t voice_buffer[VOICE_BUF_SIZE] = { 0 };
 
 /* voice data 16Khz 2ch 16bit 1s */
-static int command_wov(int argc, char **argv)
+static int command_wov(int argc, const char **argv)
 {
 	static int bit_clk;
 	static enum wov_dai_format i2s_fmt;
@@ -1845,8 +1837,9 @@ static int command_wov(int argc, char **argv)
 		/* Start to capature voice data and store in RAM buffer */
 		if (strcasecmp(argv[1], "capram") == 0) {
 			if (wov_set_buffer((uint32_t *)voice_buffer,
-				sizeof(voice_buffer) / sizeof(uint32_t))
-					== EC_SUCCESS) {
+					   sizeof(voice_buffer) /
+						   sizeof(uint32_t)) ==
+			    EC_SUCCESS) {
 				CPRINTS("Start RAM Catpure...");
 				wov_start_ram_capture();
 				return EC_SUCCESS;
@@ -1980,8 +1973,9 @@ static int command_wov(int argc, char **argv)
 				wov_set_mode(WOV_MODE_VAD);
 			} else if (strcasecmp(argv[2], "ram") == 0) {
 				if (wov_set_buffer((uint32_t *)voice_buffer,
-					sizeof(voice_buffer) / sizeof(uint32_t))
-						== EC_SUCCESS)
+						   sizeof(voice_buffer) /
+							   sizeof(uint32_t)) ==
+				    EC_SUCCESS)
 					wov_set_mode(WOV_MODE_RAM);
 				else
 					return EC_ERROR_INVAL;
@@ -1989,8 +1983,9 @@ static int command_wov(int argc, char **argv)
 				wov_set_mode(WOV_MODE_I2S);
 			} else if (strcasecmp(argv[2], "rami2s") == 0) {
 				if (wov_set_buffer((uint32_t *)voice_buffer,
-					sizeof(voice_buffer) / sizeof(uint32_t))
-						== EC_SUCCESS)
+						   sizeof(voice_buffer) /
+							   sizeof(uint32_t)) ==
+				    EC_SUCCESS)
 					wov_set_mode(WOV_MODE_RAM_AND_I2S);
 				else
 					return EC_ERROR_INVAL;
@@ -2013,7 +2008,7 @@ static int command_wov(int argc, char **argv)
 		if (strcasecmp(argv[1], "fmul2") == 0) {
 			if (strcasecmp(argv[2], "enable") == 0) {
 				CLEAR_BIT(NPCX_FMUL2_FM2CTRL,
-					NPCX_FMUL2_FM2CTRL_TUNE_DIS);
+					  NPCX_FMUL2_FM2CTRL_TUNE_DIS);
 				return EC_SUCCESS;
 			}
 			if (strcasecmp(argv[2], "disable") == 0) {
@@ -2050,22 +2045,22 @@ static int command_wov(int argc, char **argv)
 }
 
 DECLARE_CONSOLE_COMMAND(wov, command_wov,
-		"init\n"
-		"mute <enable|disable>\n"
-		"capram\n"
-		"cfgsrc <mono|stereo|left|right>\n"
-		"cfgbit <16|18|20|24>\n"
-		"cfgsfs <8000|12000|16000|24000|32000|48000>\n"
-		"cfgbck <32fs|48fs|64fs|128fs|256fs>\n"
-		"cfgfmt <i2s|right|left|pcma|pcmb|tdm>\n"
-		"cfgmod <off|vad|ram|i2s|rami2s>\n"
-		"cfgtdm [0~496 0~496 0~3]>\n"
-		"cfgdckV <0.75|1.0|1.2|2.4|3.0>\n"
-		"cfgdckR <0.75|1.0|1.2|2.4|3.0>\n"
-		"cfgdckI <0.75|1.0|1.2|2.4|3.0>\n"
-		"cfgget\n"
-		"fmul2 <enable|disable>\n"
-		"vadsens <0~31>\n"
-		"gain <0~31>",
-		"wov configuration");
+			"init\n"
+			"mute <enable|disable>\n"
+			"capram\n"
+			"cfgsrc <mono|stereo|left|right>\n"
+			"cfgbit <16|18|20|24>\n"
+			"cfgsfs <8000|12000|16000|24000|32000|48000>\n"
+			"cfgbck <32fs|48fs|64fs|128fs|256fs>\n"
+			"cfgfmt <i2s|right|left|pcma|pcmb|tdm>\n"
+			"cfgmod <off|vad|ram|i2s|rami2s>\n"
+			"cfgtdm [0~496 0~496 0~3]>\n"
+			"cfgdckV <0.75|1.0|1.2|2.4|3.0>\n"
+			"cfgdckR <0.75|1.0|1.2|2.4|3.0>\n"
+			"cfgdckI <0.75|1.0|1.2|2.4|3.0>\n"
+			"cfgget\n"
+			"fmul2 <enable|disable>\n"
+			"vadsens <0~31>\n"
+			"gain <0~31>",
+			"wov configuration");
 #endif
diff --git a/chip/npcx/wov_chip.h b/chip/npcx/wov_chip.h
index dce534c501..b0da9128e1 100644
--- a/chip/npcx/wov_chip.h
+++ b/chip/npcx/wov_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -34,10 +34,7 @@ enum wov_mic_source {
 };
 
 /* Clock source for APM. */
-enum wov_clk_src_sel {
-	WOV_FMUL2_CLK_SRC = 0,
-	WOV_PLL_CLK_SRC = 1
-};
+enum wov_clk_src_sel { WOV_FMUL2_CLK_SRC = 0, WOV_PLL_CLK_SRC = 1 };
 
 /* FMUL clock division factore. */
 enum wov_fmul_div {
@@ -48,10 +45,7 @@ enum wov_fmul_div {
 };
 
 /* Lock state. */
-enum wov_lock_state {
-	WOV_UNLOCK = 0,
-	WOV_LOCK = 1
-};
+enum wov_lock_state { WOV_UNLOCK = 0, WOV_LOCK = 1 };
 
 /* Reference clock source select. */
 enum wov_ref_clk_src_sel {
@@ -60,10 +54,7 @@ enum wov_ref_clk_src_sel {
 };
 
 /* PLL external divider select. */
-enum wov_ext_div_sel {
-	WOV_EXT_DIV_BINARY_CNT = 0,
-	WOV_EXT_DIV_LFSR_DIV = 1
-};
+enum wov_ext_div_sel { WOV_EXT_DIV_BINARY_CNT = 0, WOV_EXT_DIV_LFSR_DIV = 1 };
 
 /* FMUL output frequency. */
 enum wov_fmul_out_freq {
@@ -117,10 +108,7 @@ enum wov_interrupt_index {
 };
 
 /* FIFO DMA request selection. */
-enum wov_dma_req_sel {
-	WOV_DFLT_ESPI_DMA_REQ = 0,
-	WOV_FROM_FIFO_DMA_REQUEST
-};
+enum wov_dma_req_sel { WOV_DFLT_ESPI_DMA_REQ = 0, WOV_FROM_FIFO_DMA_REQUEST };
 
 /* Core FIFO input select. */
 enum wov_core_fifo_in_sel {
@@ -131,10 +119,7 @@ enum wov_core_fifo_in_sel {
 };
 
 /* PLL external divider selector. */
-enum wov_pll_ext_div_sel {
-	WOV_PLL_EXT_DIV_BIN_CNT = 0,
-	WOV_PLL_EXT_DIV_LFSR
-};
+enum wov_pll_ext_div_sel { WOV_PLL_EXT_DIV_BIN_CNT = 0, WOV_PLL_EXT_DIV_LFSR };
 
 /* Code for events for call back function. */
 enum wov_events {
@@ -144,7 +129,7 @@ enum wov_events {
 	 * need to call to wov_set_buffer to update the buffer * pointer
 	 */
 	WOV_EVENT_DATA_READY = 1,
-	WOV_EVENT_VAD,		  /* Voice activity detected */
+	WOV_EVENT_VAD, /* Voice activity detected */
 
 	WOV_EVENT_ERROR_FIRST = 128,
 	WOV_EVENT_ERROR_CORE_FIFO_OVERRUN = 128,
@@ -158,8 +143,8 @@ enum wov_events {
 enum wov_fifo_errors {
 	WOV_FIFO_NO_ERROR = 0,
 	WOV_CORE_FIFO_OVERRUN = 1, /* 2 : I2S FIFO is underrun. */
-	WOV_I2S_FIFO_OVERRUN = 2,  /* 3 : I2S FIFO is overrun.  */
-	WOV_I2S_FIFO_UNDERRUN = 3  /* 4 : I2S FIFO is underrun. */
+	WOV_I2S_FIFO_OVERRUN = 2, /* 3 : I2S FIFO is overrun.  */
+	WOV_I2S_FIFO_UNDERRUN = 3 /* 4 : I2S FIFO is underrun. */
 
 };
 
@@ -191,12 +176,12 @@ enum wov_modes {
 
 /* DAI format. */
 enum wov_dai_format {
-	WOV_DAI_FMT_I2S,     /* I2S mode			*/
+	WOV_DAI_FMT_I2S, /* I2S mode			*/
 	WOV_DAI_FMT_RIGHT_J, /* Right Justified mode		*/
-	WOV_DAI_FMT_LEFT_J,  /* Left Justified mode		*/
-	WOV_DAI_FMT_PCM_A,   /* PCM A Audio			*/
-	WOV_DAI_FMT_PCM_B,   /* PCM B Audio			*/
-	WOV_DAI_FMT_PCM_TDM  /* Time Division Multiplexing	*/
+	WOV_DAI_FMT_LEFT_J, /* Left Justified mode		*/
+	WOV_DAI_FMT_PCM_A, /* PCM A Audio			*/
+	WOV_DAI_FMT_PCM_B, /* PCM B Audio			*/
+	WOV_DAI_FMT_PCM_TDM /* Time Division Multiplexing	*/
 };
 
 struct wov_config {
@@ -375,10 +360,10 @@ void wov_enable_agc(int enable);
  * @param min_applied_gain      - Minimum Gain Value to apply to the ADC path.
  * @return  EC_ERROR_INVAL or EC_SUCCESS
  */
-enum ec_error_list wov_set_agc_config(int stereo, float target,
-		int noise_gate_threshold, uint8_t hold_time,
-		uint16_t attack_time, uint16_t decay_time,
-		float max_applied_gain, float min_applied_gain);
+enum ec_error_list
+wov_set_agc_config(int stereo, float target, int noise_gate_threshold,
+		   uint8_t hold_time, uint16_t attack_time, uint16_t decay_time,
+		   float max_applied_gain, float min_applied_gain);
 
 /**
  * Sets VAD sensitivity.
@@ -438,7 +423,7 @@ void wov_set_i2s_bclk(uint32_t i2s_clock);
  * @return  EC error code.
  */
 enum ec_error_list wov_set_i2s_tdm_config(int ch0_delay, int ch1_delay,
-				uint32_t flags);
+					  uint32_t flags);
 
 /**
  * Configure FMUL2 clock tunning.
@@ -477,8 +462,9 @@ extern void wov_set_clk_selection(enum wov_clk_src_sel clk_src);
  *                                PLL External Divider Load Values table.
  * @return  EC_ERROR_INVAL or EC_SUCCESS
  */
-enum ec_error_list wov_pll_clk_ext_div_config(
-	enum wov_pll_ext_div_sel ext_div_sel, uint32_t div_factor);
+enum ec_error_list
+wov_pll_clk_ext_div_config(enum wov_pll_ext_div_sel ext_div_sel,
+			   uint32_t div_factor);
 
 /**
  * PLL power down.
@@ -498,9 +484,9 @@ void wov_pll_enable(int enable);
  * @return  EC_ERROR_INVAL or EC_SUCCESS
  */
 enum ec_error_list wov_pll_clk_div_config(uint32_t out_div_1,
-			uint32_t out_div_2,
-			uint32_t feedback_div,
-			uint32_t in_div);
+					  uint32_t out_div_2,
+					  uint32_t feedback_div,
+					  uint32_t in_div);
 
 /**
  * Enables/Disables WoV interrupt.
@@ -521,7 +507,7 @@ void wov_interrupt_enable(enum wov_interrupt_index int_index, int enable);
  * @return  None
  */
 void wov_cfifo_config(enum wov_core_fifo_in_sel in_sel,
-			enum wov_fifo_threshold threshold);
+		      enum wov_fifo_threshold threshold);
 
 /**
  * Start the actual capturing of the Voice data to the RAM.
@@ -632,13 +618,10 @@ void wov_handle_event(enum wov_events event);
  * @return  EC_ERROR_INVAL or EC_SUCCESS
  */
 enum ec_error_list wov_i2s_global_config(
-	enum wov_floating_mode i2s_hiz_data,
-	enum wov_floating_mode i2s_hiz,
-	enum wov_clk_inverted_mode clk_invert,
-	int out_pull_en, enum wov_pull_upd_down_sel out_pull_mode,
-	int in_pull_en,
-	enum wov_pull_upd_down_sel in_pull_mode,
-	enum wov_test_mode test_mode);
+	enum wov_floating_mode i2s_hiz_data, enum wov_floating_mode i2s_hiz,
+	enum wov_clk_inverted_mode clk_invert, int out_pull_en,
+	enum wov_pull_upd_down_sel out_pull_mode, int in_pull_en,
+	enum wov_pull_upd_down_sel in_pull_mode, enum wov_test_mode test_mode);
 
 /**
  * I2S channel configuration
@@ -652,7 +635,8 @@ enum ec_error_list wov_i2s_global_config(
  * @return  EC_ERROR_INVAL or EC_SUCCESS
  */
 enum ec_error_list wov_i2s_channel_config(uint32_t channel_num,
-			uint32_t bit_count, enum wov_i2s_chan_trigger trigger,
-			int32_t start_delay);
+					  uint32_t bit_count,
+					  enum wov_i2s_chan_trigger trigger,
+					  int32_t start_delay);
 
 #endif /* __CROS_EC_WOV_CHIP_H */
diff --git a/chip/stm32/adc-stm32f0.c b/chip/stm32/adc-stm32f0.c
index b0654132cd..d1b1cc0e02 100644
--- a/chip/stm32/adc-stm32f0.c
+++ b/chip/stm32/adc-stm32f0.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,7 +21,7 @@ struct adc_profile_t {
 	/* Register values. */
 	uint32_t cfgr1_reg;
 	uint32_t cfgr2_reg;
-	uint32_t smpr_reg;	/* Default Sampling Rate */
+	uint32_t smpr_reg; /* Default Sampling Rate */
 	uint32_t ier_reg;
 	/* DMA config. */
 	const struct dma_option *dma_option;
@@ -31,7 +31,8 @@ struct adc_profile_t {
 
 #ifdef CONFIG_ADC_PROFILE_SINGLE
 static const struct dma_option dma_single = {
-	STM32_DMAC_ADC, (void *)&STM32_ADC_DR,
+	STM32_DMAC_ADC,
+	(void *)&STM32_ADC_DR,
 	STM32_DMA_CCR_MSIZE_32_BIT | STM32_DMA_CCR_PSIZE_32_BIT,
 };
 
@@ -41,12 +42,9 @@ static const struct dma_option dma_single = {
 
 static const struct adc_profile_t profile = {
 	/* Sample all channels once using DMA */
-	.cfgr1_reg = STM32_ADC_CFGR1_OVRMOD,
-	.cfgr2_reg = 0,
-	.smpr_reg = CONFIG_ADC_SAMPLE_TIME,
-	.ier_reg = 0,
-	.dma_option = &dma_single,
-	.dma_buffer_size = 1,
+	.cfgr1_reg = STM32_ADC_CFGR1_OVRMOD, .cfgr2_reg = 0,
+	.smpr_reg = CONFIG_ADC_SAMPLE_TIME,  .ier_reg = 0,
+	.dma_option = &dma_single,	     .dma_buffer_size = 1,
 };
 #endif
 
@@ -57,15 +55,15 @@ static const struct adc_profile_t profile = {
 #endif
 
 static const struct dma_option dma_continuous = {
-	STM32_DMAC_ADC, (void *)&STM32_ADC_DR,
+	STM32_DMAC_ADC,
+	(void *)&STM32_ADC_DR,
 	STM32_DMA_CCR_MSIZE_32_BIT | STM32_DMA_CCR_PSIZE_32_BIT |
-	STM32_DMA_CCR_CIRC,
+		STM32_DMA_CCR_CIRC,
 };
 
 static const struct adc_profile_t profile = {
 	/* Sample all channels continuously using DMA */
-	.cfgr1_reg = STM32_ADC_CFGR1_OVRMOD |
-		     STM32_ADC_CFGR1_CONT |
+	.cfgr1_reg = STM32_ADC_CFGR1_OVRMOD | STM32_ADC_CFGR1_CONT |
 		     STM32_ADC_CFGR1_DMACFG,
 	.cfgr2_reg = 0,
 	.smpr_reg = CONFIG_ADC_SAMPLE_TIME,
@@ -114,7 +112,7 @@ static void adc_configure(int ain_id, enum stm32_adc_smpr sample_rate)
 {
 	/* Sampling time */
 	if (sample_rate == STM32_ADC_SMPR_DEFAULT ||
-			sample_rate >= STM32_ADC_SMPR_COUNT)
+	    sample_rate >= STM32_ADC_SMPR_COUNT)
 		STM32_ADC_SMPR = profile.smpr_reg;
 	else
 		STM32_ADC_SMPR = STM32_ADC_SMPR_SMP(sample_rate);
@@ -160,12 +158,12 @@ static void adc_interval_read(int ain_id, int interval_ms)
 	adc_configure(ain_id, STM32_ADC_SMPR_DEFAULT);
 
 	/* EXTEN=01 -> hardware trigger detection on rising edge */
-	STM32_ADC_CFGR1 = (STM32_ADC_CFGR1 & ~STM32_ADC_CFGR1_EXTEN_MASK)
-		| STM32_ADC_CFGR1_EXTEN_RISE;
+	STM32_ADC_CFGR1 = (STM32_ADC_CFGR1 & ~STM32_ADC_CFGR1_EXTEN_MASK) |
+			  STM32_ADC_CFGR1_EXTEN_RISE;
 
 	/* EXTSEL=TRG3 -> Trigger on TIM3_TRGO */
 	STM32_ADC_CFGR1 = (STM32_ADC_CFGR1 & ~STM32_ADC_CFGR1_TRG_MASK) |
-		STM32_ADC_CFGR1_TRG3;
+			  STM32_ADC_CFGR1_TRG3;
 
 	__hw_timer_enable_clock(TIM_ADC, 1);
 
@@ -293,9 +291,18 @@ int adc_set_watchdog_delay(int delay_ms)
 
 #else /* CONFIG_ADC_WATCHDOG */
 
-static int adc_watchdog_enabled(void) { return 0; }
-static int adc_enable_watchdog_no_lock(void) { return 0; }
-static int adc_disable_watchdog_no_lock(void) { return 0; }
+static int adc_watchdog_enabled(void)
+{
+	return 0;
+}
+static int adc_enable_watchdog_no_lock(void)
+{
+	return 0;
+}
+static int adc_disable_watchdog_no_lock(void)
+{
+	return 0;
+}
 
 #endif /* CONFIG_ADC_WATCHDOG */
 
diff --git a/chip/stm32/adc-stm32f3.c b/chip/stm32/adc-stm32f3.c
index 543a44ab1a..605bb14b69 100644
--- a/chip/stm32/adc-stm32f3.c
+++ b/chip/stm32/adc-stm32f3.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,9 +16,9 @@
 
 #define ADC_SINGLE_READ_TIMEOUT 3000 /* 3 ms */
 
-#define SMPR1_EXPAND(v) ((v) | ((v) << 3) | ((v) << 6) | ((v) << 9) | \
-			 ((v) << 12) | ((v) << 15) | ((v) << 18) | \
-			 ((v) << 21))
+#define SMPR1_EXPAND(v)                                             \
+	((v) | ((v) << 3) | ((v) << 6) | ((v) << 9) | ((v) << 12) | \
+	 ((v) << 15) | ((v) << 18) | ((v) << 21))
 #define SMPR2_EXPAND(v) (SMPR1_EXPAND(v) | ((v) << 24) | ((v) << 27))
 
 /* Default ADC sample time = 13.5 cycles */
@@ -215,8 +215,9 @@ int adc_read_channel(enum adc_channel ch)
 		adc_enable_watchdog_no_lock();
 
 	mutex_unlock(&adc_lock);
-	return (value == ADC_READ_ERROR) ? ADC_READ_ERROR :
-	       value * adc->factor_mul / adc->factor_div + adc->shift;
+	return (value == ADC_READ_ERROR) ?
+		       ADC_READ_ERROR :
+		       value * adc->factor_mul / adc->factor_div + adc->shift;
 }
 
 static void adc_init(void)
diff --git a/chip/stm32/adc-stm32f4.c b/chip/stm32/adc-stm32f4.c
index 5e375b9dbf..605bb14b69 120000..100644
--- a/chip/stm32/adc-stm32f4.c
+++ b/chip/stm32/adc-stm32f4.c
@@ -1 +1,260 @@
-adc-stm32f3.c
\ No newline at end of file
+/* Copyright 2012 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc.h"
+#include "clock.h"
+#include "common.h"
+#include "console.h"
+#include "dma.h"
+#include "hooks.h"
+#include "registers.h"
+#include "task.h"
+#include "timer.h"
+#include "util.h"
+
+#define ADC_SINGLE_READ_TIMEOUT 3000 /* 3 ms */
+
+#define SMPR1_EXPAND(v)                                             \
+	((v) | ((v) << 3) | ((v) << 6) | ((v) << 9) | ((v) << 12) | \
+	 ((v) << 15) | ((v) << 18) | ((v) << 21))
+#define SMPR2_EXPAND(v) (SMPR1_EXPAND(v) | ((v) << 24) | ((v) << 27))
+
+/* Default ADC sample time = 13.5 cycles */
+#ifndef CONFIG_ADC_SAMPLE_TIME
+#define CONFIG_ADC_SAMPLE_TIME 2
+#endif
+
+struct mutex adc_lock;
+
+static int watchdog_ain_id;
+
+static inline void adc_set_channel(int sample_id, int channel)
+{
+	uint32_t mask, val;
+	volatile uint32_t *sqr_reg;
+
+	if (sample_id < 6) {
+		mask = 0x1f << (sample_id * 5);
+		val = channel << (sample_id * 5);
+		sqr_reg = &STM32_ADC_SQR3;
+	} else if (sample_id < 12) {
+		mask = 0x1f << ((sample_id - 6) * 5);
+		val = channel << ((sample_id - 6) * 5);
+		sqr_reg = &STM32_ADC_SQR2;
+	} else {
+		mask = 0x1f << ((sample_id - 12) * 5);
+		val = channel << ((sample_id - 12) * 5);
+		sqr_reg = &STM32_ADC_SQR1;
+	}
+
+	*sqr_reg = (*sqr_reg & ~mask) | val;
+}
+
+static void adc_configure(int ain_id)
+{
+	/* Set ADC channel */
+	adc_set_channel(0, ain_id);
+
+	/* Disable DMA */
+	STM32_ADC_CR2 &= ~BIT(8);
+
+	/* Disable scan mode */
+	STM32_ADC_CR1 &= ~BIT(8);
+}
+
+static void __attribute__((unused)) adc_configure_all(void)
+{
+	int i;
+
+	/* Set ADC channels */
+	STM32_ADC_SQR1 = (ADC_CH_COUNT - 1) << 20;
+	for (i = 0; i < ADC_CH_COUNT; ++i)
+		adc_set_channel(i, adc_channels[i].channel);
+
+	/* Enable DMA */
+	STM32_ADC_CR2 |= BIT(8);
+
+	/* Enable scan mode */
+	STM32_ADC_CR1 |= BIT(8);
+}
+
+static inline int adc_powered(void)
+{
+	return STM32_ADC_CR2 & BIT(0);
+}
+
+static inline int adc_conversion_ended(void)
+{
+	return STM32_ADC_SR & BIT(1);
+}
+
+static int adc_watchdog_enabled(void)
+{
+	return STM32_ADC_CR1 & BIT(23);
+}
+
+static int adc_enable_watchdog_no_lock(void)
+{
+	/* Fail if watchdog already enabled */
+	if (adc_watchdog_enabled())
+		return EC_ERROR_UNKNOWN;
+
+	/* Set channel */
+	STM32_ADC_SQR3 = watchdog_ain_id;
+	STM32_ADC_SQR1 = 0;
+	STM32_ADC_CR1 = (STM32_ADC_CR1 & ~0x1f) | watchdog_ain_id;
+
+	/* Clear interrupt bit */
+	STM32_ADC_SR &= ~0x1;
+
+	/* AWDSGL=1, SCAN=1, AWDIE=1, AWDEN=1 */
+	STM32_ADC_CR1 |= BIT(9) | BIT(8) | BIT(6) | BIT(23);
+
+	/* Disable DMA */
+	STM32_ADC_CR2 &= ~BIT(8);
+
+	/* CONT=1 */
+	STM32_ADC_CR2 |= BIT(1);
+
+	/* Start conversion */
+	STM32_ADC_CR2 |= BIT(0);
+
+	return EC_SUCCESS;
+}
+
+int adc_enable_watchdog(int ain_id, int high, int low)
+{
+	int ret;
+
+	if (!adc_powered())
+		return EC_ERROR_UNKNOWN;
+
+	mutex_lock(&adc_lock);
+
+	watchdog_ain_id = ain_id;
+
+	/* Set thresholds */
+	STM32_ADC_HTR = high & 0xfff;
+	STM32_ADC_LTR = low & 0xfff;
+
+	ret = adc_enable_watchdog_no_lock();
+	mutex_unlock(&adc_lock);
+	return ret;
+}
+
+static int adc_disable_watchdog_no_lock(void)
+{
+	/* Fail if watchdog not running */
+	if (!adc_watchdog_enabled())
+		return EC_ERROR_UNKNOWN;
+
+	/* AWDEN=0, AWDIE=0 */
+	STM32_ADC_CR1 &= ~BIT(23) & ~BIT(6);
+
+	/* CONT=0 */
+	STM32_ADC_CR2 &= ~BIT(1);
+
+	return EC_SUCCESS;
+}
+
+int adc_disable_watchdog(void)
+{
+	int ret;
+
+	if (!adc_powered())
+		return EC_ERROR_UNKNOWN;
+
+	mutex_lock(&adc_lock);
+	ret = adc_disable_watchdog_no_lock();
+	mutex_unlock(&adc_lock);
+	return ret;
+}
+
+int adc_read_channel(enum adc_channel ch)
+{
+	const struct adc_t *adc = adc_channels + ch;
+	int value;
+	int restore_watchdog = 0;
+	timestamp_t deadline;
+
+	if (!adc_powered())
+		return EC_ERROR_UNKNOWN;
+
+	mutex_lock(&adc_lock);
+
+	if (adc_watchdog_enabled()) {
+		restore_watchdog = 1;
+		adc_disable_watchdog_no_lock();
+	}
+
+	adc_configure(adc->channel);
+
+	/* Clear EOC bit */
+	STM32_ADC_SR &= ~BIT(1);
+
+	/* Start conversion (Note: For now only confirmed on F4) */
+#if defined(CHIP_FAMILY_STM32F4)
+	STM32_ADC_CR2 |= STM32_ADC_CR2_ADON | STM32_ADC_CR2_SWSTART;
+#else
+	STM32_ADC_CR2 |= STM32_ADC_CR2_ADON;
+#endif
+
+	/* Wait for EOC bit set */
+	deadline.val = get_time().val + ADC_SINGLE_READ_TIMEOUT;
+	value = ADC_READ_ERROR;
+	do {
+		if (adc_conversion_ended()) {
+			value = STM32_ADC_DR & ADC_READ_MAX;
+			break;
+		}
+	} while (!timestamp_expired(deadline, NULL));
+
+	if (restore_watchdog)
+		adc_enable_watchdog_no_lock();
+
+	mutex_unlock(&adc_lock);
+	return (value == ADC_READ_ERROR) ?
+		       ADC_READ_ERROR :
+		       value * adc->factor_mul / adc->factor_div + adc->shift;
+}
+
+static void adc_init(void)
+{
+	/*
+	 * Enable ADC clock.
+	 * APB2 clock is 16MHz. ADC clock prescaler is /2.
+	 * So the ADC clock is 8MHz.
+	 */
+	clock_enable_module(MODULE_ADC, 1);
+
+	/*
+	 * ADC clock is divided with respect to AHB, so no delay needed
+	 * here. If ADC clock is the same as AHB, a read on ADC
+	 * register is needed here.
+	 */
+
+	if (!adc_powered()) {
+		/* Power on ADC module */
+		STM32_ADC_CR2 |= STM32_ADC_CR2_ADON;
+
+		/* Reset calibration */
+		STM32_ADC_CR2 |= STM32_ADC_CR2_RSTCAL;
+		while (STM32_ADC_CR2 & STM32_ADC_CR2_RSTCAL)
+			;
+
+		/* A/D Calibrate */
+		STM32_ADC_CR2 |= STM32_ADC_CR2_CAL;
+		while (STM32_ADC_CR2 & STM32_ADC_CR2_CAL)
+			;
+	}
+
+	/* Set right alignment */
+	STM32_ADC_CR2 &= ~STM32_ADC_CR2_ALIGN;
+
+	/* Set sample time of all channels */
+	STM32_ADC_SMPR1 = SMPR1_EXPAND(CONFIG_ADC_SAMPLE_TIME);
+	STM32_ADC_SMPR2 = SMPR2_EXPAND(CONFIG_ADC_SAMPLE_TIME);
+}
+DECLARE_HOOK(HOOK_INIT, adc_init, HOOK_PRIO_INIT_ADC);
diff --git a/chip/stm32/adc-stm32l.c b/chip/stm32/adc-stm32l.c
index c1f1cfae4a..636710f071 100644
--- a/chip/stm32/adc-stm32l.c
+++ b/chip/stm32/adc-stm32l.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -91,7 +91,7 @@ static void adc_init(void)
 
 	if (!adc_powered())
 		/* Power on ADC module */
-		STM32_ADC_CR2 |= BIT(0);  /* ADON */
+		STM32_ADC_CR2 |= BIT(0); /* ADON */
 
 	/* Set right alignment */
 	STM32_ADC_CR2 &= ~BIT(11);
@@ -165,6 +165,7 @@ int adc_read_channel(enum adc_channel ch)
 	adc_release();
 
 	mutex_unlock(&adc_lock);
-	return (value == ADC_READ_ERROR) ? ADC_READ_ERROR :
-	       value * adc->factor_mul / adc->factor_div + adc->shift;
+	return (value == ADC_READ_ERROR) ?
+		       ADC_READ_ERROR :
+		       value * adc->factor_mul / adc->factor_div + adc->shift;
 }
diff --git a/chip/stm32/adc-stm32l4.c b/chip/stm32/adc-stm32l4.c
index 8609d44f5d..e67ae4a8fd 100644
--- a/chip/stm32/adc-stm32l4.c
+++ b/chip/stm32/adc-stm32l4.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,7 +21,7 @@ struct adc_profile_t {
 	/* Register values. */
 	uint32_t cfgr1_reg;
 	uint32_t cfgr2_reg;
-	uint32_t smpr_reg;	/* Default Sampling Rate */
+	uint32_t smpr_reg; /* Default Sampling Rate */
 	uint32_t ier_reg;
 	/* DMA config. */
 	const struct dma_option *dma_option;
@@ -36,11 +36,11 @@ struct adc_profile_t {
 #endif
 
 #if defined(CHIP_FAMILY_STM32L4)
-#define ADC_CALIBRATION_TIMEOUT_US	100000U
-#define ADC_ENABLE_TIMEOUT_US		200000U
-#define ADC_CONVERSION_TIMEOUT_US	200000U
+#define ADC_CALIBRATION_TIMEOUT_US 100000U
+#define ADC_ENABLE_TIMEOUT_US 200000U
+#define ADC_CONVERSION_TIMEOUT_US 200000U
 
-#define NUMBER_OF_ADC_CHANNEL   2
+#define NUMBER_OF_ADC_CHANNEL 2
 uint8_t adc1_initialized;
 #endif
 
@@ -51,15 +51,15 @@ uint8_t adc1_initialized;
 #endif
 
 static const struct dma_option dma_continuous = {
-	STM32_DMAC_ADC, (void *)&STM32_ADC_DR,
+	STM32_DMAC_ADC,
+	(void *)&STM32_ADC_DR,
 	STM32_DMA_CCR_MSIZE_32_BIT | STM32_DMA_CCR_PSIZE_32_BIT |
-	STM32_DMA_CCR_CIRC,
+		STM32_DMA_CCR_CIRC,
 };
 
 static const struct adc_profile_t profile = {
 	/* Sample all channels continuously using DMA */
-	.cfgr1_reg = STM32_ADC_CFGR1_OVRMOD |
-		     STM32_ADC_CFGR1_CONT |
+	.cfgr1_reg = STM32_ADC_CFGR1_OVRMOD | STM32_ADC_CFGR1_CONT |
 		     STM32_ADC_CFGR1_DMACFG,
 	.cfgr2_reg = 0,
 	.smpr_reg = CONFIG_ADC_SAMPLE_TIME,
@@ -87,7 +87,7 @@ static void adc_init(const struct adc_t *adc)
 
 	/* set ADC clock to 20MHz */
 	STM32_ADC1_CCR &= ~0x003C0000;
-	STM32_ADC1_CCR |=  0x00080000;
+	STM32_ADC1_CCR |= 0x00080000;
 
 	STM32_RCC_AHB2ENR |= STM32_RCC_HB2_GPIOA;
 	STM32_RCC_AHB2ENR |= STM32_RCC_HB2_GPIOB;
@@ -101,13 +101,13 @@ static void adc_init(const struct adc_t *adc)
 }
 
 static void adc_configure(int ain_id, int ain_rank,
-		enum stm32_adc_smpr sample_rate)
+			  enum stm32_adc_smpr sample_rate)
 {
 	/* Select Sampling time and channel to convert */
-	if (ain_id <= 10)	{
+	if (ain_id <= 10) {
 		STM32_ADC1_SMPR1 &= ~(7 << ((ain_id - 1) * 3));
 		STM32_ADC1_SMPR1 |= (sample_rate << ((ain_id - 1) * 3));
-	} else	{
+	} else {
 		STM32_ADC1_SMPR2 &= ~(7 << ((ain_id - 11) * 3));
 		STM32_ADC1_SMPR2 |= (sample_rate << ((ain_id - 11) * 3));
 	}
@@ -172,7 +172,8 @@ int adc_read_channel(enum adc_channel ch)
 
 		/* wait for the end of calibration */
 		wait_loop_index = ((ADC_CALIBRATION_TIMEOUT_US *
-				(CPU_CLOCK / (100000 * 2))) / 10);
+				    (CPU_CLOCK / (100000 * 2))) /
+				   10);
 		while (STM32_ADC1_CR & STM32_ADC1_CR_ADCAL) {
 			if (wait_loop_index-- == 0)
 				break;
@@ -181,8 +182,9 @@ int adc_read_channel(enum adc_channel ch)
 		/* Enable ADC */
 		STM32_ADC1_ISR |= STM32_ADC1_ISR_ADRDY;
 		STM32_ADC1_CR |= STM32_ADC1_CR_ADEN;
-		wait_loop_index = ((ADC_ENABLE_TIMEOUT_US *
-				(CPU_CLOCK / (100000 * 2))) / 10);
+		wait_loop_index =
+			((ADC_ENABLE_TIMEOUT_US * (CPU_CLOCK / (100000 * 2))) /
+			 10);
 		while (!(STM32_ADC1_ISR & STM32_ADC1_ISR_ADRDY)) {
 			wait_loop_index--;
 			if (wait_loop_index == 0)
@@ -196,8 +198,8 @@ int adc_read_channel(enum adc_channel ch)
 	STM32_ADC1_CR |= BIT(3); /* JADSTART */
 
 	/* Wait for end of injected conversion */
-	wait_loop_index = ((ADC_CONVERSION_TIMEOUT_US *
-			(CPU_CLOCK / (100000 * 2))) / 10);
+	wait_loop_index =
+		((ADC_CONVERSION_TIMEOUT_US * (CPU_CLOCK / (100000 * 2))) / 10);
 	while (!(STM32_ADC1_ISR & BIT(6))) {
 		if (wait_loop_index-- == 0)
 			break;
diff --git a/chip/stm32/adc_chip.h b/chip/stm32/adc_chip.h
index 7e3c688c14..2c4e726ea5 100644
--- a/chip/stm32/adc_chip.h
+++ b/chip/stm32/adc_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -48,7 +48,7 @@ struct adc_t {
 #endif
 
 #if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32L4)
-	enum stm32_adc_smpr sample_rate;  /* Sampling Rate of the channel */
+	enum stm32_adc_smpr sample_rate; /* Sampling Rate of the channel */
 #endif
 };
 
diff --git a/chip/stm32/bkpdata.c b/chip/stm32/bkpdata.c
index ded77401d6..bde026facd 100644
--- a/chip/stm32/bkpdata.c
+++ b/chip/stm32/bkpdata.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -65,7 +65,7 @@ int bkpdata_index_lookup(enum system_bbram_idx idx, int *msb)
 	return -1;
 }
 
-uint32_t bkpdata_read_reset_flags()
+uint32_t bkpdata_read_reset_flags(void)
 {
 	uint32_t flags = bkpdata_read(BKPDATA_INDEX_SAVED_RESET_FLAGS);
 
@@ -76,8 +76,7 @@ uint32_t bkpdata_read_reset_flags()
 	return flags;
 }
 
-__overridable
-void bkpdata_write_reset_flags(uint32_t save_flags)
+__overridable void bkpdata_write_reset_flags(uint32_t save_flags)
 {
 	bkpdata_write(BKPDATA_INDEX_SAVED_RESET_FLAGS, save_flags & 0xffff);
 #ifdef CONFIG_STM32_EXTENDED_RESET_FLAGS
diff --git a/chip/stm32/bkpdata.h b/chip/stm32/bkpdata.h
index 199ed213a9..14ef33483e 100644
--- a/chip/stm32/bkpdata.h
+++ b/chip/stm32/bkpdata.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,27 +20,27 @@
  * compatibility.
  */
 enum bkpdata_index {
-	BKPDATA_INDEX_SCRATCHPAD,	     /* General-purpose scratchpad */
-	BKPDATA_INDEX_SAVED_RESET_FLAGS,     /* Saved reset flags */
+	BKPDATA_INDEX_SCRATCHPAD, /* General-purpose scratchpad */
+	BKPDATA_INDEX_SAVED_RESET_FLAGS, /* Saved reset flags */
 #ifdef CONFIG_STM32_EXTENDED_RESET_FLAGS
-	BKPDATA_INDEX_SAVED_RESET_FLAGS_2,   /* Saved reset flags (cont) */
+	BKPDATA_INDEX_SAVED_RESET_FLAGS_2, /* Saved reset flags (cont) */
 #endif
 #ifdef CONFIG_SOFTWARE_PANIC
-	BKPDATA_INDEX_SAVED_PANIC_REASON,    /* Saved panic reason */
-	BKPDATA_INDEX_SAVED_PANIC_INFO,      /* Saved panic data */
+	BKPDATA_INDEX_SAVED_PANIC_REASON, /* Saved panic reason */
+	BKPDATA_INDEX_SAVED_PANIC_INFO, /* Saved panic data */
 	BKPDATA_INDEX_SAVED_PANIC_EXCEPTION, /* Saved panic exception code */
 #endif
 #ifdef CONFIG_USB_PD_DUAL_ROLE
-	BKPDATA_INDEX_PD0,		     /* USB-PD saved port0 state */
-	BKPDATA_INDEX_PD1,		     /* USB-PD saved port1 state */
-	BKPDATA_INDEX_PD2,		     /* USB-PD saved port2 state */
+	BKPDATA_INDEX_PD0, /* USB-PD saved port0 state */
+	BKPDATA_INDEX_PD1, /* USB-PD saved port1 state */
+	BKPDATA_INDEX_PD2, /* USB-PD saved port2 state */
 #endif
 #ifdef CONFIG_SOFTWARE_PANIC
 	/**
 	 * Saving the panic flags in case that AP thinks the panic is new
 	 * after a hard reset.
 	 */
-	BKPDATA_INDEX_SAVED_PANIC_FLAGS,     /* Saved panic flags */
+	BKPDATA_INDEX_SAVED_PANIC_FLAGS, /* Saved panic flags */
 #endif
 	BKPDATA_COUNT
 };
diff --git a/chip/stm32/build.mk b/chip/stm32/build.mk
index 0d47a0131a..1fc14a15fa 100644
--- a/chip/stm32/build.mk
+++ b/chip/stm32/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
+# Copyright 2013 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/chip/stm32/charger_detect.c b/chip/stm32/charger_detect.c
index b32b9f3ac0..c404fc827a 100644
--- a/chip/stm32/charger_detect.c
+++ b/chip/stm32/charger_detect.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -33,7 +33,6 @@ static uint16_t detect_type(uint16_t det_type)
 	return STM32_USB_BCDR;
 }
 
-
 int charger_detect_get_device_type(void)
 {
 	uint16_t pdet_result;
diff --git a/chip/stm32/clock-f.c b/chip/stm32/clock-f.c
index 0ae4440d78..d181397d86 100644
--- a/chip/stm32/clock-f.c
+++ b/chip/stm32/clock-f.c
@@ -1,10 +1,11 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Clocks and power management settings */
 
+#include "builtin/assert.h"
 #include "chipset.h"
 #include "clock.h"
 #include "clock-f.h"
@@ -23,7 +24,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args)
 
 /* Convert decimal to BCD */
 static uint8_t u8_to_bcd(uint8_t val)
@@ -41,8 +42,8 @@ static uint32_t rtc_tr_to_sec(uint32_t rtc_tr)
 	uint32_t sec;
 
 	/* convert the hours field */
-	sec = (((rtc_tr & 0x300000) >> 20) * 10 +
-	       ((rtc_tr & 0xf0000) >> 16)) * 3600;
+	sec = (((rtc_tr & 0x300000) >> 20) * 10 + ((rtc_tr & 0xf0000) >> 16)) *
+	      3600;
 	/* convert the minutes field */
 	sec += (((rtc_tr & 0x7000) >> 12) * 10 + ((rtc_tr & 0xf00) >> 8)) * 60;
 	/* convert the seconds field */
@@ -122,10 +123,9 @@ static uint32_t rtc_dr_to_sec(uint32_t rtc_dr)
 	struct calendar_date time;
 	uint32_t sec;
 
-	time.year = (((rtc_dr & 0xf00000) >> 20) * 10 +
-		    ((rtc_dr & 0xf0000) >> 16));
-	time.month = (((rtc_dr & 0x1000) >> 12) * 10 +
-		     ((rtc_dr & 0xf00) >> 8));
+	time.year =
+		(((rtc_dr & 0xf00000) >> 20) * 10 + ((rtc_dr & 0xf0000) >> 16));
+	time.month = (((rtc_dr & 0x1000) >> 12) * 10 + ((rtc_dr & 0xf00) >> 8));
 	time.day = ((rtc_dr & 0x30) >> 4) * 10 + (rtc_dr & 0xf);
 
 	sec = date_to_sec(time);
@@ -258,8 +258,8 @@ void set_rtc_alarm(uint32_t delay_s, uint32_t delay_us,
 	 * If the caller doesn't specify subsecond delay (e.g. host command),
 	 * just align the alarm time to second.
 	 */
-	STM32_RTC_ALRMASSR = delay_us ?
-			     (us_to_rtcss(alarm_us) | 0x0f000000) : 0;
+	STM32_RTC_ALRMASSR = delay_us ? (us_to_rtcss(alarm_us) | 0x0f000000) :
+					0;
 
 #ifdef CONFIG_HOSTCMD_RTC
 	/*
@@ -321,8 +321,7 @@ static void set_rtc_host_event(void)
 DECLARE_DEFERRED(set_rtc_host_event);
 #endif
 
-test_mockable
-void rtc_alarm_irq(void)
+test_mockable void rtc_alarm_irq(void)
 {
 	struct rtc_time_reg rtc;
 	reset_rtc_alarm(&rtc);
@@ -342,8 +341,7 @@ static void __rtc_alarm_irq(void)
 }
 DECLARE_IRQ(STM32_IRQ_RTC_ALARM, __rtc_alarm_irq, 1);
 
-__attribute__((weak))
-int clock_get_timer_freq(void)
+__attribute__((weak)) int clock_get_timer_freq(void)
 {
 	return clock_get_freq();
 }
@@ -399,7 +397,7 @@ void print_system_rtc(enum console_channel ch)
 }
 
 #ifdef CONFIG_CMD_RTC
-static int command_system_rtc(int argc, char **argv)
+static int command_system_rtc(int argc, const char **argv)
 {
 	char *e;
 	uint32_t t;
@@ -416,12 +414,11 @@ static int command_system_rtc(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(rtc, command_system_rtc,
-		"[set <seconds>]",
-		"Get/set real-time clock");
+DECLARE_CONSOLE_COMMAND(rtc, command_system_rtc, "[set <seconds>]",
+			"Get/set real-time clock");
 
 #ifdef CONFIG_CMD_RTC_ALARM
-static int command_rtc_alarm_test(int argc, char **argv)
+static int command_rtc_alarm_test(int argc, const char **argv)
 {
 	int s = 1, us = 0;
 	struct rtc_time_reg rtc;
@@ -433,7 +430,6 @@ static int command_rtc_alarm_test(int argc, char **argv)
 		s = strtoi(argv[1], &e, 10);
 		if (*e)
 			return EC_ERROR_PARAM1;
-
 	}
 	if (argc > 2) {
 		us = strtoi(argv[2], &e, 10);
@@ -445,8 +441,7 @@ static int command_rtc_alarm_test(int argc, char **argv)
 	return EC_SUCCESS;
 }
 DECLARE_CONSOLE_COMMAND(rtc_alarm, command_rtc_alarm_test,
-			"[seconds [microseconds]]",
-			"Test alarm");
+			"[seconds [microseconds]]", "Test alarm");
 #endif /* CONFIG_CMD_RTC_ALARM */
 #endif /* CONFIG_CMD_RTC */
 
@@ -465,9 +460,8 @@ static enum ec_status system_rtc_get_value(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_VALUE,
-		system_rtc_get_value,
-		EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_VALUE, system_rtc_get_value,
+		     EC_VER_MASK(0));
 
 static enum ec_status system_rtc_set_value(struct host_cmd_handler_args *args)
 {
@@ -476,9 +470,8 @@ static enum ec_status system_rtc_set_value(struct host_cmd_handler_args *args)
 	rtc_set(p->time);
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_VALUE,
-		system_rtc_set_value,
-		EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_VALUE, system_rtc_set_value,
+		     EC_VER_MASK(0));
 
 static enum ec_status system_rtc_set_alarm(struct host_cmd_handler_args *args)
 {
@@ -492,9 +485,8 @@ static enum ec_status system_rtc_set_alarm(struct host_cmd_handler_args *args)
 	set_rtc_alarm(p->time, 0, &rtc, 1);
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_ALARM,
-		system_rtc_set_alarm,
-		EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_ALARM, system_rtc_set_alarm,
+		     EC_VER_MASK(0));
 
 static enum ec_status system_rtc_get_alarm(struct host_cmd_handler_args *args)
 {
@@ -505,8 +497,7 @@ static enum ec_status system_rtc_get_alarm(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_ALARM,
-		system_rtc_get_alarm,
-		EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_ALARM, system_rtc_get_alarm,
+		     EC_VER_MASK(0));
 
 #endif /* CONFIG_HOSTCMD_RTC */
diff --git a/chip/stm32/clock-f.h b/chip/stm32/clock-f.h
index 4662b043cb..5ed302bf78 100644
--- a/chip/stm32/clock-f.h
+++ b/chip/stm32/clock-f.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -100,4 +100,4 @@ int is_host_wake_alarm_expired(timestamp_t ts);
 /* Set RTC wakeup based on the value saved in host_wake_time */
 void restore_host_wake_alarm(void);
 
-#endif  /* __CROS_EC_CLOCK_F_H */
+#endif /* __CROS_EC_CLOCK_F_H */
diff --git a/chip/stm32/clock-l4.h b/chip/stm32/clock-l4.h
index d237b84580..975d952b9f 100644
--- a/chip/stm32/clock-l4.h
+++ b/chip/stm32/clock-l4.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -107,4 +107,4 @@ void restore_host_wake_alarm(void);
 void low_power_init(void);
 #endif
 
-#endif  /* __CROS_EC_CLOCK_L4_H */
+#endif /* __CROS_EC_CLOCK_L4_H */
diff --git a/chip/stm32/clock-stm32f0.c b/chip/stm32/clock-stm32f0.c
index d791d63df3..3b56382fdb 100644
--- a/chip/stm32/clock-stm32f0.c
+++ b/chip/stm32/clock-stm32f0.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,7 +22,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args)
 
 /* use 48Mhz USB-synchronized High-speed oscillator */
 #define HSI48_CLOCK 48000000
@@ -54,13 +54,13 @@ static int dsleep_recovery_margin_us = 1000000;
  * we won't miss the host alarm.
  */
 #ifdef CHIP_VARIANT_STM32F373
-#define STOP_MODE_LATENCY 500  /* us */
+#define STOP_MODE_LATENCY 500 /* us */
 #elif defined(CHIP_VARIANT_STM32F05X)
-#define STOP_MODE_LATENCY 300  /* us */
+#define STOP_MODE_LATENCY 300 /* us */
 #elif (CPU_CLOCK == PLL_CLOCK)
-#define STOP_MODE_LATENCY 300   /* us */
+#define STOP_MODE_LATENCY 300 /* us */
 #else
-#define STOP_MODE_LATENCY 50    /* us */
+#define STOP_MODE_LATENCY 50 /* us */
 #endif
 #define SET_RTC_MATCH_DELAY 200 /* us */
 
@@ -137,9 +137,8 @@ void config_hispeed_clock(void)
 	while ((STM32_RCC_CFGR & 0xc) != 0x8)
 		;
 /* F03X and F05X and F070 don't have HSI48 */
-#elif defined(CHIP_VARIANT_STM32F03X) || \
-defined(CHIP_VARIANT_STM32F05X) || \
-defined(CHIP_VARIANT_STM32F070)
+#elif defined(CHIP_VARIANT_STM32F03X) || defined(CHIP_VARIANT_STM32F05X) || \
+	defined(CHIP_VARIANT_STM32F070)
 	/* If PLL is the clock source, PLL has already been set up. */
 	if ((STM32_RCC_CFGR & 0xc) == 0x8)
 		return;
@@ -268,7 +267,7 @@ void __enter_hibernate(uint32_t seconds, uint32_t microseconds)
 	STM32_PWR_CR |= 0xe;
 	CPU_SCB_SYSCTRL |= 0x4;
 	/* go to Standby mode */
-	asm("wfi");
+	cpu_enter_suspend_mode();
 
 	/* we should never reach that point */
 	while (1)
@@ -319,8 +318,8 @@ void __idle(void)
 		     * EC exits deep sleep mode.
 		     */
 		    !is_host_wake_alarm_expired(
-			(timestamp_t)(next_delay + t0.val + SECOND +
-				      RESTORE_HOST_ALARM_LATENCY)) &&
+			    (timestamp_t)(next_delay + t0.val + SECOND +
+					  RESTORE_HOST_ALARM_LATENCY)) &&
 #endif
 		    (next_delay > (STOP_MODE_LATENCY + SET_RTC_MATCH_DELAY))) {
 			/* Deep-sleep in STOP mode */
@@ -331,9 +330,9 @@ void __idle(void)
 			/* Set deep sleep bit */
 			CPU_SCB_SYSCTRL |= 0x4;
 
-			set_rtc_alarm(0, next_delay - STOP_MODE_LATENCY,
-				      &rtc0, 0);
-			asm("wfi");
+			set_rtc_alarm(0, next_delay - STOP_MODE_LATENCY, &rtc0,
+				      0);
+			cpu_enter_suspend_mode();
 
 			CPU_SCB_SYSCTRL &= ~0x4;
 
@@ -371,10 +370,10 @@ void __idle(void)
 			idle_sleep_cnt++;
 
 			/* Normal idle : only CPU clock stopped */
-			asm("wfi");
+			cpu_enter_suspend_mode();
 		}
 #ifdef CONFIG_LOW_POWER_IDLE_LIMITED
-en_int:
+	en_int:
 #endif
 		interrupt_enable();
 	}
@@ -482,22 +481,21 @@ void rtc_set(uint32_t sec)
 /**
  * Print low power idle statistics
  */
-static int command_idle_stats(int argc, char **argv)
+static int command_idle_stats(int argc, const char **argv)
 {
 	timestamp_t ts = get_time();
 
 	ccprintf("Num idle calls that sleep:           %d\n", idle_sleep_cnt);
 	ccprintf("Num idle calls that deep-sleep:      %d\n", idle_dsleep_cnt);
 	ccprintf("Time spent in deep-sleep:            %.6llds\n",
-			idle_dsleep_time_us);
+		 idle_dsleep_time_us);
 	ccprintf("Total time on:                       %.6llds\n", ts.val);
 	ccprintf("Deep-sleep closest to wake deadline: %dus\n",
-			dsleep_recovery_margin_us);
+		 dsleep_recovery_margin_us);
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats,
-			"",
+DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, "",
 			"Print last idle stats");
 #endif /* CONFIG_CMD_IDLE_STATS */
 #endif
diff --git a/chip/stm32/clock-stm32f3.c b/chip/stm32/clock-stm32f3.c
index be91154e52..7d2b3de7f2 120000..100644
--- a/chip/stm32/clock-stm32f3.c
+++ b/chip/stm32/clock-stm32f3.c
@@ -1 +1,501 @@
-clock-stm32f0.c
\ No newline at end of file
+/* Copyright 2014 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Clocks and power management settings */
+
+#include "chipset.h"
+#include "clock.h"
+#include "clock-f.h"
+#include "common.h"
+#include "console.h"
+#include "cpu.h"
+#include "hooks.h"
+#include "hwtimer.h"
+#include "registers.h"
+#include "system.h"
+#include "task.h"
+#include "timer.h"
+#include "uart.h"
+#include "util.h"
+
+/* Console output macros */
+#define CPUTS(outstr) cputs(CC_CLOCK, outstr)
+#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args)
+
+/* use 48Mhz USB-synchronized High-speed oscillator */
+#define HSI48_CLOCK 48000000
+
+/* use PLL at 38.4MHz as system clock. */
+#define PLL_CLOCK 38400000
+
+/* Low power idle statistics */
+#ifdef CONFIG_LOW_POWER_IDLE
+static int idle_sleep_cnt;
+static int idle_dsleep_cnt;
+static uint64_t idle_dsleep_time_us;
+static int dsleep_recovery_margin_us = 1000000;
+
+/*
+ * minimum delay to enter stop mode
+ *
+ * STOP_MODE_LATENCY: max time to wake up from STOP mode with regulator in low
+ * power mode is 5 us + PLL locking time is 200us.
+ *
+ * SET_RTC_MATCH_DELAY: max time to set RTC match alarm. If we set the alarm
+ * in the past, it will never wake up and cause a watchdog.
+ * For STM32F3, we are using HSE, which requires additional time to start up.
+ * Therefore, the latency for STM32F3 is set longer.
+ *
+ * RESTORE_HOST_ALARM_LATENCY: max latency between the deferred routine is
+ * called and the host alarm is actually restored. In practice, the max latency
+ * is measured as ~600us. 1000us should be conservative enough to guarantee
+ * we won't miss the host alarm.
+ */
+#ifdef CHIP_VARIANT_STM32F373
+#define STOP_MODE_LATENCY 500 /* us */
+#elif defined(CHIP_VARIANT_STM32F05X)
+#define STOP_MODE_LATENCY 300 /* us */
+#elif (CPU_CLOCK == PLL_CLOCK)
+#define STOP_MODE_LATENCY 300 /* us */
+#else
+#define STOP_MODE_LATENCY 50 /* us */
+#endif
+#define SET_RTC_MATCH_DELAY 200 /* us */
+
+#ifdef CONFIG_HOSTCMD_RTC
+#define RESTORE_HOST_ALARM_LATENCY 1000 /* us */
+#endif
+
+#endif /* CONFIG_LOW_POWER_IDLE */
+
+/*
+ * RTC clock frequency (By default connected to LSI clock)
+ *
+ * The LSI on any given chip can be between 30 kHz to 60 kHz.
+ * Without calibration, LSI frequency may be off by as much as 50%.
+ *
+ * Set synchronous clock freq to (RTC clock source / 2) to maximize
+ * subsecond resolution. Set asynchronous clock to 1 Hz.
+ */
+
+#define RTC_PREDIV_A 1
+#ifdef CONFIG_STM32_CLOCK_LSE
+#define RTC_FREQ (32768 / (RTC_PREDIV_A + 1)) /* Hz */
+/* GCD(RTC_FREQ, 1000000) */
+#define RTC_GCD 64
+#else /* LSI clock, 40kHz-ish */
+#define RTC_FREQ (40000 / (RTC_PREDIV_A + 1)) /* Hz */
+/* GCD(RTC_FREQ, 1000000) */
+#define RTC_GCD 20000
+#endif
+#define RTC_PREDIV_S (RTC_FREQ - 1)
+
+/*
+ * There are (1000000 / RTC_FREQ) us per RTC tick, take GCD of both terms
+ * for conversion calculations to fit in 32 bits.
+ */
+#define US_GCD (1000000 / RTC_GCD)
+#define RTC_FREQ_GCD (RTC_FREQ / RTC_GCD)
+
+int32_t rtcss_to_us(uint32_t rtcss)
+{
+	return ((RTC_PREDIV_S - (rtcss & 0x7fff)) * US_GCD) / RTC_FREQ_GCD;
+}
+
+uint32_t us_to_rtcss(int32_t us)
+{
+	return RTC_PREDIV_S - us * RTC_FREQ_GCD / US_GCD;
+}
+
+void config_hispeed_clock(void)
+{
+#ifdef CHIP_FAMILY_STM32F3
+	/* Ensure that HSE is ON */
+	wait_for_ready(&STM32_RCC_CR, BIT(16), BIT(17));
+
+	/*
+	 * HSE = 24MHz, no prescalar, no MCO, with PLL *2 => 48MHz SYSCLK
+	 * HCLK = SYSCLK, PCLK = HCLK / 2 = 24MHz
+	 * ADCCLK = PCLK / 6 = 4MHz
+	 * USB uses SYSCLK = 48MHz
+	 */
+	STM32_RCC_CFGR = 0x0041a400;
+
+	/* Enable the PLL */
+	STM32_RCC_CR |= 0x01000000;
+
+	/* Wait until the PLL is ready */
+	while (!(STM32_RCC_CR & 0x02000000))
+		;
+
+	/* Switch SYSCLK to PLL */
+	STM32_RCC_CFGR |= 0x2;
+
+	/* Wait until the PLL is the clock source */
+	while ((STM32_RCC_CFGR & 0xc) != 0x8)
+		;
+/* F03X and F05X and F070 don't have HSI48 */
+#elif defined(CHIP_VARIANT_STM32F03X) || defined(CHIP_VARIANT_STM32F05X) || \
+	defined(CHIP_VARIANT_STM32F070)
+	/* If PLL is the clock source, PLL has already been set up. */
+	if ((STM32_RCC_CFGR & 0xc) == 0x8)
+		return;
+
+	/* Ensure that HSI is ON */
+	wait_for_ready(&STM32_RCC_CR, BIT(0), BIT(1));
+
+	/*
+	 * HSI = 8MHz, HSI/2 with PLL *12 = ~48 MHz
+	 * therefore PCLK = FCLK = SYSCLK = 48MHz
+	 */
+	/* Switch the PLL source to HSI/2 */
+	STM32_RCC_CFGR &= ~(0x00018000);
+
+	/*
+	 * Specify HSI/2 clock as input clock to PLL and set PLL (*12).
+	 */
+	STM32_RCC_CFGR |= 0x00280000;
+
+	/* Enable the PLL. */
+	STM32_RCC_CR |= 0x01000000;
+
+	/* Wait until PLL is ready. */
+	while (!(STM32_RCC_CR & 0x02000000))
+		;
+
+	/* Switch SYSCLK to PLL. */
+	STM32_RCC_CFGR |= 0x2;
+
+	/* wait until the PLL is the clock source */
+	while ((STM32_RCC_CFGR & 0xc) != 0x8)
+		;
+#else
+	/* Ensure that HSI48 is ON */
+	wait_for_ready(&STM32_RCC_CR2, BIT(16), BIT(17));
+
+#if (CPU_CLOCK == HSI48_CLOCK)
+	/*
+	 * HSI48 = 48MHz, no prescaler, no MCO, no PLL
+	 * therefore PCLK = FCLK = SYSCLK = 48MHz
+	 * USB uses HSI48 = 48MHz
+	 */
+
+#ifdef CONFIG_USB
+	/*
+	 * Configure and enable Clock Recovery System
+	 *
+	 * Since we are running from the internal RC HSI48 clock, the CSR
+	 * is needed to guarantee an accurate 48MHz clock for USB.
+	 *
+	 * The default values configure the CRS to use the periodic USB SOF
+	 * as the SYNC signal for calibrating the HSI48.
+	 *
+	 */
+
+	/* Enable Clock Recovery System */
+	STM32_RCC_APB1ENR |= STM32_RCC_PB1_CRS;
+
+	/* Enable automatic trimming */
+	STM32_CRS_CR |= STM32_CRS_CR_AUTOTRIMEN;
+
+	/* Enable oscillator clock for the frequency error counter */
+	STM32_CRS_CR |= STM32_CRS_CR_CEN;
+#endif
+
+	/* switch SYSCLK to HSI48 */
+	STM32_RCC_CFGR = 0x00000003;
+
+	/* wait until the HSI48 is the clock source */
+	while ((STM32_RCC_CFGR & 0xc) != 0xc)
+		;
+
+#elif (CPU_CLOCK == PLL_CLOCK)
+	/*
+	 * HSI48 = 48MHz, no prescalar, no MCO, with PLL *4/5 => 38.4MHz SYSCLK
+	 * therefore PCLK = FCLK = SYSCLK = 38.4MHz
+	 * USB uses HSI48 = 48MHz
+	 */
+
+	/* If PLL is the clock source, PLL has already been set up. */
+	if ((STM32_RCC_CFGR & 0xc) == 0x8)
+		return;
+
+	/*
+	 * Specify HSI48 clock as input clock to PLL and set PLL multiplier
+	 * and divider.
+	 */
+	STM32_RCC_CFGR = 0x00098000;
+	STM32_RCC_CFGR2 = 0x4;
+
+	/* Enable the PLL. */
+	STM32_RCC_CR |= 0x01000000;
+
+	/* Wait until PLL is ready. */
+	while (!(STM32_RCC_CR & 0x02000000))
+		;
+
+	/* Switch SYSCLK to PLL. */
+	STM32_RCC_CFGR |= 0x2;
+
+	/* wait until the PLL is the clock source */
+	while ((STM32_RCC_CFGR & 0xc) != 0x8)
+		;
+
+#else
+#error "CPU_CLOCK must be either 48MHz or 38.4MHz"
+#endif
+#endif
+}
+
+#ifdef CONFIG_HIBERNATE
+void __enter_hibernate(uint32_t seconds, uint32_t microseconds)
+{
+	struct rtc_time_reg rtc;
+
+	if (seconds || microseconds)
+		set_rtc_alarm(seconds, microseconds, &rtc, 0);
+
+	/* interrupts off now */
+	interrupt_disable();
+
+#ifdef CONFIG_HIBERNATE_WAKEUP_PINS
+	/* enable the wake up pins */
+	STM32_PWR_CSR |= CONFIG_HIBERNATE_WAKEUP_PINS;
+#endif
+	STM32_PWR_CR |= 0xe;
+	CPU_SCB_SYSCTRL |= 0x4;
+	/* go to Standby mode */
+	asm("wfi");
+
+	/* we should never reach that point */
+	while (1)
+		;
+}
+#endif
+
+#ifdef CONFIG_HOSTCMD_RTC
+static void restore_host_wake_alarm_deferred(void)
+{
+	restore_host_wake_alarm();
+}
+DECLARE_DEFERRED(restore_host_wake_alarm_deferred);
+#endif
+
+#ifdef CONFIG_LOW_POWER_IDLE
+
+void clock_refresh_console_in_use(void)
+{
+}
+
+void __idle(void)
+{
+	timestamp_t t0;
+	uint32_t rtc_diff;
+	int next_delay, margin_us;
+	struct rtc_time_reg rtc0, rtc1;
+
+	while (1) {
+		interrupt_disable();
+
+		t0 = get_time();
+		next_delay = __hw_clock_event_get() - t0.le.lo;
+
+#ifdef CONFIG_LOW_POWER_IDLE_LIMITED
+		if (idle_is_disabled())
+			goto en_int;
+#endif
+
+		if (DEEP_SLEEP_ALLOWED &&
+#ifdef CONFIG_HOSTCMD_RTC
+		    /*
+		     * Don't go to deep sleep mode if we might miss the
+		     * wake alarm that the host requested. Note that the
+		     * host alarm always aligns to second. Considering the
+		     * worst case, we have to ensure alarm won't go off
+		     * within RESTORE_HOST_ALARM_LATENCY + 1 second after
+		     * EC exits deep sleep mode.
+		     */
+		    !is_host_wake_alarm_expired(
+			    (timestamp_t)(next_delay + t0.val + SECOND +
+					  RESTORE_HOST_ALARM_LATENCY)) &&
+#endif
+		    (next_delay > (STOP_MODE_LATENCY + SET_RTC_MATCH_DELAY))) {
+			/* Deep-sleep in STOP mode */
+			idle_dsleep_cnt++;
+
+			uart_enable_wakeup(1);
+
+			/* Set deep sleep bit */
+			CPU_SCB_SYSCTRL |= 0x4;
+
+			set_rtc_alarm(0, next_delay - STOP_MODE_LATENCY, &rtc0,
+				      0);
+			asm("wfi");
+
+			CPU_SCB_SYSCTRL &= ~0x4;
+
+			uart_enable_wakeup(0);
+
+			/*
+			 * By default only HSI 8MHz is enabled here. Re-enable
+			 * high-speed clock if in use.
+			 */
+			config_hispeed_clock();
+
+			/* Fast forward timer according to RTC counter */
+			reset_rtc_alarm(&rtc1);
+			rtc_diff = get_rtc_diff(&rtc0, &rtc1);
+			t0.val = t0.val + rtc_diff;
+			force_time(t0);
+
+#ifdef CONFIG_HOSTCMD_RTC
+			hook_call_deferred(
+				&restore_host_wake_alarm_deferred_data, 0);
+#endif
+			/* Record time spent in deep sleep. */
+			idle_dsleep_time_us += rtc_diff;
+
+			/* Calculate how close we were to missing deadline */
+			margin_us = next_delay - rtc_diff;
+			if (margin_us < 0)
+				/* Use CPUTS to save stack space */
+				CPUTS("Idle overslept!\n");
+
+			/* Record the closest to missing a deadline. */
+			if (margin_us < dsleep_recovery_margin_us)
+				dsleep_recovery_margin_us = margin_us;
+		} else {
+			idle_sleep_cnt++;
+
+			/* Normal idle : only CPU clock stopped */
+			asm("wfi");
+		}
+#ifdef CONFIG_LOW_POWER_IDLE_LIMITED
+	en_int:
+#endif
+		interrupt_enable();
+	}
+}
+#endif /* CONFIG_LOW_POWER_IDLE */
+
+int clock_get_freq(void)
+{
+	return CPU_CLOCK;
+}
+
+void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles)
+{
+	volatile uint32_t unused __attribute__((unused));
+
+	if (bus == BUS_AHB) {
+		while (cycles--)
+			unused = STM32_DMA1_REGS->isr;
+	} else { /* APB */
+		while (cycles--)
+			unused = STM32_USART_BRR(STM32_USART1_BASE);
+	}
+}
+
+void clock_enable_module(enum module_id module, int enable)
+{
+	if (module == MODULE_ADC) {
+		if (enable)
+			STM32_RCC_APB2ENR |= STM32_RCC_APB2ENR_ADCEN;
+		else
+			STM32_RCC_APB2ENR &= ~STM32_RCC_APB2ENR_ADCEN;
+		return;
+	} else if (module == MODULE_USB) {
+		if (enable)
+			STM32_RCC_APB1ENR |= STM32_RCC_PB1_USB;
+		else
+			STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_USB;
+	}
+}
+
+int clock_is_module_enabled(enum module_id module)
+{
+	if (module == MODULE_ADC)
+		return !!(STM32_RCC_APB2ENR & STM32_RCC_APB2ENR_ADCEN);
+	else if (module == MODULE_USB)
+		return !!(STM32_RCC_APB1ENR & STM32_RCC_PB1_USB);
+	return 0;
+}
+
+void rtc_init(void)
+{
+	rtc_unlock_regs();
+
+	/* Enter RTC initialize mode */
+	STM32_RTC_ISR |= STM32_RTC_ISR_INIT;
+	while (!(STM32_RTC_ISR & STM32_RTC_ISR_INITF))
+		;
+
+	/* Set clock prescalars */
+	STM32_RTC_PRER = (RTC_PREDIV_A << 16) | RTC_PREDIV_S;
+
+	/* Start RTC timer */
+	STM32_RTC_ISR &= ~STM32_RTC_ISR_INIT;
+	while (STM32_RTC_ISR & STM32_RTC_ISR_INITF)
+		;
+
+	/* Enable RTC alarm interrupt */
+	STM32_RTC_CR |= STM32_RTC_CR_ALRAIE | STM32_RTC_CR_BYPSHAD;
+	STM32_EXTI_RTSR |= EXTI_RTC_ALR_EVENT;
+	task_enable_irq(STM32_IRQ_RTC_ALARM);
+
+	rtc_lock_regs();
+}
+
+#if defined(CONFIG_CMD_RTC) || defined(CONFIG_HOSTCMD_RTC)
+void rtc_set(uint32_t sec)
+{
+	struct rtc_time_reg rtc;
+
+	sec_to_rtc(sec, &rtc);
+	rtc_unlock_regs();
+
+	/* Disable alarm */
+	STM32_RTC_CR &= ~STM32_RTC_CR_ALRAE;
+
+	/* Enter RTC initialize mode */
+	STM32_RTC_ISR |= STM32_RTC_ISR_INIT;
+	while (!(STM32_RTC_ISR & STM32_RTC_ISR_INITF))
+		;
+
+	/* Set clock prescalars */
+	STM32_RTC_PRER = (RTC_PREDIV_A << 16) | RTC_PREDIV_S;
+
+	STM32_RTC_TR = rtc.rtc_tr;
+	STM32_RTC_DR = rtc.rtc_dr;
+	/* Start RTC timer */
+	STM32_RTC_ISR &= ~STM32_RTC_ISR_INIT;
+
+	rtc_lock_regs();
+}
+#endif
+
+#if defined(CONFIG_LOW_POWER_IDLE) && defined(CONFIG_COMMON_RUNTIME)
+#ifdef CONFIG_CMD_IDLE_STATS
+/**
+ * Print low power idle statistics
+ */
+static int command_idle_stats(int argc, const char **argv)
+{
+	timestamp_t ts = get_time();
+
+	ccprintf("Num idle calls that sleep:           %d\n", idle_sleep_cnt);
+	ccprintf("Num idle calls that deep-sleep:      %d\n", idle_dsleep_cnt);
+	ccprintf("Time spent in deep-sleep:            %.6llds\n",
+		 idle_dsleep_time_us);
+	ccprintf("Total time on:                       %.6llds\n", ts.val);
+	ccprintf("Deep-sleep closest to wake deadline: %dus\n",
+		 dsleep_recovery_margin_us);
+
+	return EC_SUCCESS;
+}
+DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, "",
+			"Print last idle stats");
+#endif /* CONFIG_CMD_IDLE_STATS */
+#endif
diff --git a/chip/stm32/clock-stm32f4.c b/chip/stm32/clock-stm32f4.c
index b30edc1fa2..479faac7da 100644
--- a/chip/stm32/clock-stm32f4.c
+++ b/chip/stm32/clock-stm32f4.c
@@ -1,10 +1,11 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Clocks and power management settings */
 
+#include "builtin/assert.h"
 #include "chipset.h"
 #include "clock.h"
 #include "clock-f.h"
@@ -21,12 +22,12 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args)
 
 enum clock_osc {
-	OSC_HSI = 0,	/* High-speed internal oscillator */
-	OSC_HSE,	/* High-speed external oscillator */
-	OSC_PLL,	/* PLL */
+	OSC_HSI = 0, /* High-speed internal oscillator */
+	OSC_HSE, /* High-speed external oscillator */
+	OSC_PLL, /* PLL */
 };
 
 /*
@@ -35,10 +36,11 @@ enum clock_osc {
  * A CONFIG may be needed if other boards have different MCO
  * requirements.
  */
-#define RCC_CFGR_MCO_CONFIG ((2 << 30) | /* MCO2 <- HSE  */ \
-			     (0 << 27) | /* MCO2 div / 4 */ \
-			     (6 << 24) | /* MCO1 div / 4 */ \
-			     (3 << 21))  /* MCO1 <- PLL  */
+#define RCC_CFGR_MCO_CONFIG             \
+	((2 << 30) | /* MCO2 <- HSE  */ \
+	 (0 << 27) | /* MCO2 div / 4 */ \
+	 (6 << 24) | /* MCO1 div / 4 */ \
+	 (3 << 21)) /* MCO1 <- PLL  */
 
 #ifdef CONFIG_STM32_CLOCK_HSE_HZ
 /* RTC clock must 1 Mhz when derived from HSE */
@@ -48,7 +50,6 @@ enum clock_osc {
 #define RTC_DIV 0
 #endif /* CONFIG_STM32_CLOCK_HSE_HZ */
 
-
 /* Bus clocks dividers depending on the configuration */
 /*
  * max speed configuration with the PLL ON
@@ -56,18 +57,18 @@ enum clock_osc {
  * For STM32F446: max 45 MHz
  * For STM32F412: max AHB 100 MHz / APB2 100 Mhz / APB1 50 Mhz
  */
-#define RCC_CFGR_DIVIDERS_WITH_PLL (RCC_CFGR_MCO_CONFIG  | \
-				    CFGR_RTCPRE(RTC_DIV) | \
-				    CFGR_PPRE2(STM32F4_APB2_PRE) | \
-				    CFGR_PPRE1(STM32F4_APB1_PRE) | \
-				    CFGR_HPRE(STM32F4_AHB_PRE))
+#define RCC_CFGR_DIVIDERS_WITH_PLL                                     \
+	(RCC_CFGR_MCO_CONFIG | CFGR_RTCPRE(RTC_DIV) |                  \
+	 CFGR_PPRE2(STM32F4_APB2_PRE) | CFGR_PPRE1(STM32F4_APB1_PRE) | \
+	 CFGR_HPRE(STM32F4_AHB_PRE))
 /*
  * lower power configuration without the PLL
  * the frequency will be low (8-24Mhz), we don't want dividers to the
  * peripheral clocks, put /1 everywhere.
  */
-#define RCC_CFGR_DIVIDERS_NO_PLL (RCC_CFGR_MCO_CONFIG | CFGR_RTCPRE(0) | \
-				  CFGR_PPRE2(0) | CFGR_PPRE1(0) | CFGR_HPRE(0))
+#define RCC_CFGR_DIVIDERS_NO_PLL                                \
+	(RCC_CFGR_MCO_CONFIG | CFGR_RTCPRE(0) | CFGR_PPRE2(0) | \
+	 CFGR_PPRE1(0) | CFGR_HPRE(0))
 
 /* PLL output frequency */
 #define STM32F4_PLL_CLOCK (STM32F4_VCO_CLOCK / STM32F4_PLLP_DIV)
@@ -166,8 +167,9 @@ void clock_set_osc(enum clock_osc osc)
 		/* Switch to HSI */
 		clock_switch_osc(OSC_HSI);
 		/* optimized flash latency settings for <30Mhz clock (0-WS) */
-		STM32_FLASH_ACR = (STM32_FLASH_ACR & ~STM32_FLASH_ACR_LAT_MASK)
-				| STM32_FLASH_ACR_LATENCY_SLOW;
+		STM32_FLASH_ACR =
+			(STM32_FLASH_ACR & ~STM32_FLASH_ACR_LAT_MASK) |
+			STM32_FLASH_ACR_LATENCY_SLOW;
 		/* read-back the latency as advised by the Reference Manual */
 		unused = STM32_FLASH_ACR;
 		/* Turn off the PLL1 to save power */
@@ -182,8 +184,9 @@ void clock_set_osc(enum clock_osc osc)
 		/* Switch to HSE */
 		clock_switch_osc(OSC_HSE);
 		/* optimized flash latency settings for <30Mhz clock (0-WS) */
-		STM32_FLASH_ACR = (STM32_FLASH_ACR & ~STM32_FLASH_ACR_LAT_MASK)
-				| STM32_FLASH_ACR_LATENCY_SLOW;
+		STM32_FLASH_ACR =
+			(STM32_FLASH_ACR & ~STM32_FLASH_ACR_LAT_MASK) |
+			STM32_FLASH_ACR_LATENCY_SLOW;
 		/* read-back the latency as advised by the Reference Manual */
 		unused = STM32_FLASH_ACR;
 		/* Turn off the PLL1 to save power */
@@ -201,8 +204,9 @@ void clock_set_osc(enum clock_osc osc)
 		 * Increase flash latency before transition the clock
 		 * Use the minimum Wait States value optimized for the platform.
 		 */
-		STM32_FLASH_ACR = (STM32_FLASH_ACR & ~STM32_FLASH_ACR_LAT_MASK)
-				| STM32_FLASH_ACR_LATENCY;
+		STM32_FLASH_ACR =
+			(STM32_FLASH_ACR & ~STM32_FLASH_ACR_LAT_MASK) |
+			STM32_FLASH_ACR_LATENCY;
 		/* read-back the latency as advised by the Reference Manual */
 		unused = STM32_FLASH_ACR;
 		/* Switch to PLL */
@@ -247,17 +251,14 @@ static void clock_pll_configure(void)
 	i2sdiv = (vcoclock + (systemclock / 2)) / systemclock;
 
 	/* Set up PLL */
-	STM32_RCC_PLLCFGR =
-		PLLCFGR_PLLM(plldiv) |
-		PLLCFGR_PLLN(pllmult) |
-		PLLCFGR_PLLP(STM32F4_PLLP_DIV / 2 - 1) |
+	STM32_RCC_PLLCFGR = PLLCFGR_PLLM(plldiv) | PLLCFGR_PLLN(pllmult) |
+			    PLLCFGR_PLLP(STM32F4_PLLP_DIV / 2 - 1) |
 #if defined(CONFIG_STM32_CLOCK_HSE_HZ)
-		PLLCFGR_PLLSRC_HSE |
+			    PLLCFGR_PLLSRC_HSE |
 #else
-		PLLCFGR_PLLSRC_HSI |
+			    PLLCFGR_PLLSRC_HSI |
 #endif
-		PLLCFGR_PLLQ(usbdiv) |
-		PLLCFGR_PLLR(i2sdiv);
+			    PLLCFGR_PLLQ(usbdiv) | PLLCFGR_PLLR(i2sdiv);
 }
 
 void low_power_init(void);
@@ -300,22 +301,23 @@ void clock_enable_module(enum module_id module, int enable)
 		if (enable) {
 			STM32_RCC_AHB2ENR |= STM32_RCC_AHB2ENR_OTGFSEN;
 			STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_OTGHSEN |
-				STM32_RCC_AHB1ENR_OTGHSULPIEN;
+					     STM32_RCC_AHB1ENR_OTGHSULPIEN;
 		} else {
 			STM32_RCC_AHB2ENR &= ~STM32_RCC_AHB2ENR_OTGFSEN;
 			STM32_RCC_AHB1ENR &= ~STM32_RCC_AHB1ENR_OTGHSEN &
-				     ~STM32_RCC_AHB1ENR_OTGHSULPIEN;
+					     ~STM32_RCC_AHB1ENR_OTGHSULPIEN;
 		}
 		return;
 	} else if (module == MODULE_I2C) {
 		if (enable) {
 			/* Enable clocks to I2C modules if necessary */
 			STM32_RCC_APB1ENR |=
-				STM32_RCC_I2C1EN | STM32_RCC_I2C2EN
-				| STM32_RCC_I2C3EN | STM32_RCC_FMPI2C4EN;
+				STM32_RCC_I2C1EN | STM32_RCC_I2C2EN |
+				STM32_RCC_I2C3EN | STM32_RCC_FMPI2C4EN;
 			STM32_RCC_DCKCFGR2 =
-				(STM32_RCC_DCKCFGR2 & ~DCKCFGR2_FMPI2C1SEL_MASK)
-				| DCKCFGR2_FMPI2C1SEL(FMPI2C1SEL_APB);
+				(STM32_RCC_DCKCFGR2 &
+				 ~DCKCFGR2_FMPI2C1SEL_MASK) |
+				DCKCFGR2_FMPI2C1SEL(FMPI2C1SEL_APB);
 		} else {
 			STM32_RCC_APB1ENR &=
 				~(STM32_RCC_I2C1EN | STM32_RCC_I2C2EN |
@@ -349,12 +351,14 @@ void clock_enable_module(enum module_id module, int enable)
 
 int32_t rtcss_to_us(uint32_t rtcss)
 {
-	return ((RTC_PREDIV_S - rtcss) * (SECOND/SCALING) / (RTC_FREQ/SCALING));
+	return ((RTC_PREDIV_S - rtcss) * (SECOND / SCALING) /
+		(RTC_FREQ / SCALING));
 }
 
 uint32_t us_to_rtcss(int32_t us)
 {
-	return (RTC_PREDIV_S - (us * (RTC_FREQ/SCALING) / (SECOND/SCALING)));
+	return (RTC_PREDIV_S -
+		(us * (RTC_FREQ / SCALING) / (SECOND / SCALING)));
 }
 
 void rtc_init(void)
@@ -365,8 +369,8 @@ void rtc_init(void)
 	STM32_RCC_BDCR = STM32_RCC_BDCR_RTCEN | BDCR_RTCSEL(BDCR_SRC_HSE);
 #else
 	/* RTC clocked from the LSI, ensure first it is ON */
-	wait_for_ready(&(STM32_RCC_CSR),
-		STM32_RCC_CSR_LSION, STM32_RCC_CSR_LSIRDY);
+	wait_for_ready(&(STM32_RCC_CSR), STM32_RCC_CSR_LSION,
+		       STM32_RCC_CSR_LSIRDY);
 
 	STM32_RCC_BDCR = STM32_RCC_BDCR_RTCEN | BDCR_RTCSEL(BDCR_SRC_LSI);
 #endif
@@ -379,11 +383,10 @@ void rtc_init(void)
 		;
 
 	/* Set clock prescalars: Needs two separate writes. */
-	STM32_RTC_PRER =
-		(STM32_RTC_PRER & ~STM32_RTC_PRER_S_MASK) | RTC_PREDIV_S;
-	STM32_RTC_PRER =
-		(STM32_RTC_PRER & ~STM32_RTC_PRER_A_MASK)
-		| (RTC_PREDIV_A << 16);
+	STM32_RTC_PRER = (STM32_RTC_PRER & ~STM32_RTC_PRER_S_MASK) |
+			 RTC_PREDIV_S;
+	STM32_RTC_PRER = (STM32_RTC_PRER & ~STM32_RTC_PRER_A_MASK) |
+			 (RTC_PREDIV_A << 16);
 
 	/* Start RTC timer */
 	STM32_RTC_ISR &= ~STM32_RTC_ISR_INIT;
@@ -528,8 +531,9 @@ void __idle(void)
 			/* Set deep sleep bit */
 			CPU_SCB_SYSCTRL |= 0x4;
 
-			set_rtc_alarm(0, next_delay - STOP_MODE_LATENCY
-						    - PLL_LOCK_LATENCY,
+			set_rtc_alarm(0,
+				      next_delay - STOP_MODE_LATENCY -
+					      PLL_LOCK_LATENCY,
 				      &rtc_sleep, 0);
 
 			/* Switch to HSI */
@@ -540,7 +544,7 @@ void __idle(void)
 			/* ensure outstanding memory transactions complete */
 			asm volatile("dsb");
 
-			asm("wfi");
+			cpu_enter_suspend_mode();
 
 			CPU_SCB_SYSCTRL &= ~0x4;
 
@@ -573,30 +577,29 @@ void __idle(void)
 			idle_sleep_cnt++;
 
 			/* Normal idle : only CPU clock stopped */
-			asm("wfi");
+			cpu_enter_suspend_mode();
 		}
 		interrupt_enable();
 	}
 }
 
 /* Print low power idle statistics. */
-static int command_idle_stats(int argc, char **argv)
+static int command_idle_stats(int argc, const char **argv)
 {
 	timestamp_t ts = get_time();
 
 	ccprintf("Num idle calls that sleep:           %d\n", idle_sleep_cnt);
 	ccprintf("Num idle calls that deep-sleep:      %d\n", idle_dsleep_cnt);
 	ccprintf("Time spent in deep-sleep:            %.6llds\n",
-			idle_dsleep_time_us);
+		 idle_dsleep_time_us);
 	ccprintf("Num of prevented sleep:              %d\n",
-			idle_sleep_prevented_cnt);
+		 idle_sleep_prevented_cnt);
 	ccprintf("Total time on:                       %.6llds\n", ts.val);
 	ccprintf("Deep-sleep closest to wake deadline: %dus\n",
-			dsleep_recovery_margin_us);
+		 dsleep_recovery_margin_us);
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats,
-			"",
+DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, "",
 			"Print last idle stats");
 #endif /* CONFIG_LOW_POWER_IDLE */
diff --git a/chip/stm32/clock-stm32g4.c b/chip/stm32/clock-stm32g4.c
index b0bf56d85f..dbb8fd88cb 100644
--- a/chip/stm32/clock-stm32g4.c
+++ b/chip/stm32/clock-stm32g4.c
@@ -1,10 +1,11 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Clocks configuration routines */
 
+#include "builtin/assert.h"
 #include "chipset.h"
 #include "clock.h"
 #include "clock-f.h"
@@ -21,14 +22,14 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args)
 
-#define MHZ(x) ((x) * 1000000)
-#define WAIT_STATE_FREQ_STEP_HZ	MHZ(20)
+#define MHZ(x) ((x)*1000000)
+#define WAIT_STATE_FREQ_STEP_HZ MHZ(20)
 /* PLL configuration constants */
-#define STM32G4_SYSCLK_MAX_HZ		MHZ(170)
-#define STM32G4_HSI_CLK_HZ		MHZ(16)
-#define STM32G4_PLL_IN_FREQ_HZ		MHZ(4)
+#define STM32G4_SYSCLK_MAX_HZ MHZ(170)
+#define STM32G4_HSI_CLK_HZ MHZ(16)
+#define STM32G4_PLL_IN_FREQ_HZ MHZ(4)
 #define STM32G4_PLL_R 2
 #define STM32G4_AHB_PRE 1
 #define STM32G4_APB1_PRE 1
@@ -42,7 +43,7 @@ enum rcc_clksrc {
 };
 
 static void stm32g4_config_pll(uint32_t hclk_hz, uint32_t pll_src,
-			      uint32_t pll_clk_in_hz)
+			       uint32_t pll_clk_in_hz)
 {
 	/*
 	 * The pll output frequency (Fhclkc) is determined by:
@@ -81,20 +82,16 @@ static void stm32g4_config_pll(uint32_t hclk_hz, uint32_t pll_src,
 	ASSERT(pll_m && (pll_m <= 16));
 	ASSERT((pll_n >= 8) && (pll_n <= 127));
 
-	hclk_freq = pll_clk_in_hz * pll_n / (pll_m *
-					      STM32G4_PLL_R * STM32G4_AHB_PRE);
+	hclk_freq = pll_clk_in_hz * pll_n /
+		    (pll_m * STM32G4_PLL_R * STM32G4_AHB_PRE);
 	/* Ensure that there aren't any integer rounding errors */
 	ASSERT(hclk_freq == hclk_hz);
 
 	/* Program PLL config register */
-	STM32_RCC_PLLCFGR = PLLCFGR_PLLP(0) |
-		PLLCFGR_PLLR(STM32G4_PLL_R / 2 - 1) |
-		PLLCFGR_PLLR_EN |
-		PLLCFGR_PLLQ(0) |
-		PLLCFGR_PLLQ_EN |
-		PLLCFGR_PLLN(pll_n) |
-		PLLCFGR_PLLM(pll_m - 1) |
-		pll_src;
+	STM32_RCC_PLLCFGR =
+		PLLCFGR_PLLP(0) | PLLCFGR_PLLR(STM32G4_PLL_R / 2 - 1) |
+		PLLCFGR_PLLR_EN | PLLCFGR_PLLQ(0) | PLLCFGR_PLLQ_EN |
+		PLLCFGR_PLLN(pll_n) | PLLCFGR_PLLM(pll_m - 1) | pll_src;
 
 	/* Wait until PLL is locked */
 	wait_for_ready(&(STM32_RCC_CR), STM32_RCC_CR_PLLON,
@@ -116,8 +113,8 @@ static void stm32g4_config_pll(uint32_t hclk_hz, uint32_t pll_src,
 static void stm32g4_config_low_speed_clock(void)
 {
 	/* Ensure that LSI is ON */
-	wait_for_ready(&(STM32_RCC_CSR),
-		STM32_RCC_CSR_LSION, STM32_RCC_CSR_LSIRDY);
+	wait_for_ready(&(STM32_RCC_CSR), STM32_RCC_CSR_LSION,
+		       STM32_RCC_CSR_LSIRDY);
 
 	/* Setup RTC Clock input */
 	STM32_RCC_BDCR |= STM32_RCC_BDCR_BDRST;
@@ -163,10 +160,10 @@ void stm32g4_set_flash_ws(uint32_t freq_hz)
 	 * found in Table 9 of RM0440 - STM32G4 technical reference manual. A
 	 * table lookup is not required though as WS = HCLK (MHz) / 20
 	 */
-	ws = freq_hz /  WAIT_STATE_FREQ_STEP_HZ;
+	ws = freq_hz / WAIT_STATE_FREQ_STEP_HZ;
 	/* Enable data and instruction cache */
 	STM32_FLASH_ACR |= STM32_FLASH_ACR_DCEN | STM32_FLASH_ACR_ICEN |
-		STM32_FLASH_ACR_PRFTEN | ws;
+			   STM32_FLASH_ACR_PRFTEN | ws;
 }
 
 void clock_init(void)
@@ -255,16 +252,14 @@ void clock_enable_module(enum module_id module, int enable)
 	} else if (module == MODULE_I2C) {
 		if (enable) {
 			/* Enable clocks to I2C modules if necessary */
-			STM32_RCC_APB1ENR1 |=
-				STM32_RCC_APB1ENR1_I2C1EN |
-				STM32_RCC_APB1ENR1_I2C2EN |
-				STM32_RCC_APB1ENR1_I2C3EN;
+			STM32_RCC_APB1ENR1 |= STM32_RCC_APB1ENR1_I2C1EN |
+					      STM32_RCC_APB1ENR1_I2C2EN |
+					      STM32_RCC_APB1ENR1_I2C3EN;
 			STM32_RCC_APB1ENR2 |= STM32_RCC_APB1ENR2_I2C4EN;
 		} else {
-			STM32_RCC_APB1ENR1 &=
-				~(STM32_RCC_APB1ENR1_I2C1EN |
-				  STM32_RCC_APB1ENR1_I2C2EN |
-				  STM32_RCC_APB1ENR1_I2C3EN);
+			STM32_RCC_APB1ENR1 &= ~(STM32_RCC_APB1ENR1_I2C1EN |
+						STM32_RCC_APB1ENR1_I2C2EN |
+						STM32_RCC_APB1ENR1_I2C3EN);
 			STM32_RCC_APB1ENR2 &= ~STM32_RCC_APB1ENR2_I2C4EN;
 		}
 	} else if (module == MODULE_ADC) {
@@ -274,7 +269,7 @@ void clock_enable_module(enum module_id module, int enable)
 					      STM32_RCC_APB2ENR_ADC345EN);
 		else
 			STM32_RCC_AHB2ENR &= ~(STM32_RCC_AHB2ENR_ADC12EN |
-					      STM32_RCC_APB2ENR_ADC345EN);
+					       STM32_RCC_APB2ENR_ADC345EN);
 	} else {
 		CPRINTS("stm32g4: enable clock module %d not supported",
 			module);
diff --git a/chip/stm32/clock-stm32h7.c b/chip/stm32/clock-stm32h7.c
index 57dc170dd9..67e17f4174 100644
--- a/chip/stm32/clock-stm32h7.c
+++ b/chip/stm32/clock-stm32h7.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,9 +13,9 @@
  * but at least yields predictable behavior.
  */
 
-
 #include <stdbool.h>
 
+#include "builtin/assert.h"
 #include "chipset.h"
 #include "clock.h"
 #include "common.h"
@@ -31,7 +31,7 @@
 
 /* Check chip family and variant for compatibility */
 #ifndef CHIP_FAMILY_STM32H7
-#error  Source clock-stm32h7.c does not support this chip family.
+#error Source clock-stm32h7.c does not support this chip family.
 #endif
 #ifndef CHIP_VARIANT_STM32H7X3
 #error Unsupported chip variant.
@@ -39,13 +39,13 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ##args)
 
 enum clock_osc {
-	OSC_HSI = 0,	/* High-speed internal oscillator */
-	OSC_CSI,	/* Multi-speed internal oscillator: NOT IMPLEMENTED */
-	OSC_HSE,	/* High-speed external oscillator: NOT IMPLEMENTED */
-	OSC_PLL,	/* PLL */
+	OSC_HSI = 0, /* High-speed internal oscillator */
+	OSC_CSI, /* Multi-speed internal oscillator: NOT IMPLEMENTED */
+	OSC_HSE, /* High-speed external oscillator: NOT IMPLEMENTED */
+	OSC_PLL, /* PLL */
 };
 
 enum voltage_scale {
@@ -57,12 +57,12 @@ enum voltage_scale {
 };
 
 enum freq {
-	FREQ_1KHZ   = 1000,
-	FREQ_32KHZ  = 32  * FREQ_1KHZ,
-	FREQ_1MHZ   = 1000000,
-	FREQ_2MHZ   = 2   * FREQ_1MHZ,
-	FREQ_16MHZ  = 16  * FREQ_1MHZ,
-	FREQ_64MHZ  = 64  * FREQ_1MHZ,
+	FREQ_1KHZ = 1000,
+	FREQ_32KHZ = 32 * FREQ_1KHZ,
+	FREQ_1MHZ = 1000000,
+	FREQ_2MHZ = 2 * FREQ_1MHZ,
+	FREQ_16MHZ = 16 * FREQ_1MHZ,
+	FREQ_64MHZ = 64 * FREQ_1MHZ,
 	FREQ_140MHZ = 140 * FREQ_1MHZ,
 	FREQ_200MHZ = 200 * FREQ_1MHZ,
 	FREQ_280MHZ = 280 * FREQ_1MHZ,
@@ -144,13 +144,13 @@ static void clock_flash_latency(enum freq axi_freq, enum voltage_scale vos)
  *
  * @param output_freq The target output frequency.
  */
-static void clock_pll1_configure(enum freq output_freq) {
+static void clock_pll1_configure(enum freq output_freq)
+{
 	uint32_t divm = 4; // Input prescaler (16MHz max for PLL -- 64/4 ==> 16)
-	uint32_t divn;     // Pll multiplier
-	uint32_t divp;     // Output 1 prescaler
+	uint32_t divn; // Pll multiplier
+	uint32_t divp; // Output 1 prescaler
 
-	switch (output_freq)
-	{
+	switch (output_freq) {
 	case FREQ_400MHZ:
 		/*
 		 * PLL1 configuration:
@@ -190,8 +190,8 @@ static void clock_pll1_configure(enum freq output_freq) {
 	 * Using VCO wide-range setting, STM32_RCC_PLLCFG_PLL1VCOSEL_WIDE,
 	 * requires input frequency to be between 2MHz and 16MHz.
 	 */
-	ASSERT(FREQ_2MHZ <= (STM32_HSI_CLOCK/divm));
-	ASSERT((STM32_HSI_CLOCK/divm) <= FREQ_16MHZ);
+	ASSERT(FREQ_2MHZ <= (STM32_HSI_CLOCK / divm));
+	ASSERT((STM32_HSI_CLOCK / divm) <= FREQ_16MHZ);
 
 	/*
 	 * Ensure that we actually reach the target frequency.
@@ -199,14 +199,14 @@ static void clock_pll1_configure(enum freq output_freq) {
 	ASSERT((STM32_HSI_CLOCK / divm * divn / divp) == output_freq);
 
 	/* Configure PLL1 using 64 Mhz HSI as input */
-	STM32_RCC_PLLCKSELR = STM32_RCC_PLLCKSEL_PLLSRC_HSI
-			    | STM32_RCC_PLLCKSEL_DIVM1(divm);
+	STM32_RCC_PLLCKSELR = STM32_RCC_PLLCKSEL_PLLSRC_HSI |
+			      STM32_RCC_PLLCKSEL_DIVM1(divm);
 	/* in integer mode, wide range VCO with 16Mhz input, use divP */
-	STM32_RCC_PLLCFGR = STM32_RCC_PLLCFG_PLL1VCOSEL_WIDE
-			  | STM32_RCC_PLLCFG_PLL1RGE_8M_16M
-			  | STM32_RCC_PLLCFG_DIVP1EN;
-	STM32_RCC_PLL1DIVR = STM32_RCC_PLLDIV_DIVP(divp)
-			   | STM32_RCC_PLLDIV_DIVN(divn);
+	STM32_RCC_PLLCFGR = STM32_RCC_PLLCFG_PLL1VCOSEL_WIDE |
+			    STM32_RCC_PLLCFG_PLL1RGE_8M_16M |
+			    STM32_RCC_PLLCFG_DIVP1EN;
+	STM32_RCC_PLL1DIVR = STM32_RCC_PLLDIV_DIVP(divp) |
+			     STM32_RCC_PLLDIV_DIVN(divn);
 }
 
 /**
@@ -215,22 +215,22 @@ static void clock_pll1_configure(enum freq output_freq) {
  * @param sysclk The input system clock, after the system clock prescaler.
  * @return The bus clock speed selected and configured
  */
-static enum freq clock_peripheral_configure(enum freq sysclk) {
-	switch (sysclk)
-	{
+static enum freq clock_peripheral_configure(enum freq sysclk)
+{
+	switch (sysclk) {
 	case FREQ_64MHZ:
 		/* Restore /1 HPRE (AHB prescaler) */
 		/* Disable downstream prescalers */
-		STM32_RCC_D1CFGR = STM32_RCC_D1CFGR_HPRE_DIV1
-				 | STM32_RCC_D1CFGR_D1PPRE_DIV1
-				 | STM32_RCC_D1CFGR_D1CPRE_DIV1;
+		STM32_RCC_D1CFGR = STM32_RCC_D1CFGR_HPRE_DIV1 |
+				   STM32_RCC_D1CFGR_D1PPRE_DIV1 |
+				   STM32_RCC_D1CFGR_D1CPRE_DIV1;
 		/* TODO(b/149512910): Adjust more peripheral prescalers */
 		return FREQ_64MHZ;
 	case FREQ_400MHZ:
 		/* Put /2 on HPRE (AHB prescaler) to keep at the 200MHz max */
-		STM32_RCC_D1CFGR = STM32_RCC_D1CFGR_HPRE_DIV2
-				 | STM32_RCC_D1CFGR_D1PPRE_DIV1
-				 | STM32_RCC_D1CFGR_D1CPRE_DIV1;
+		STM32_RCC_D1CFGR = STM32_RCC_D1CFGR_HPRE_DIV2 |
+				   STM32_RCC_D1CFGR_D1PPRE_DIV1 |
+				   STM32_RCC_D1CFGR_D1CPRE_DIV1;
 		/* TODO(b/149512910): Adjust more peripheral prescalers */
 		return FREQ_200MHZ;
 	default:
@@ -293,16 +293,16 @@ static void clock_switch_osc(enum clock_osc osc)
 
 static void switch_voltage_scale(enum voltage_scale vos)
 {
-	volatile uint32_t *const vos_reg   = &STM32_PWR_D3CR;
-	const uint32_t           vos_ready = STM32_PWR_D3CR_VOSRDY;
-	const uint32_t           vos_mask  = STM32_PWR_D3CR_VOSMASK;
-	const uint32_t           vos_values[] = {
-						/* See note below about VOS0. */
-						STM32_PWR_D3CR_VOS1,
-						STM32_PWR_D3CR_VOS1,
-						STM32_PWR_D3CR_VOS2,
-						STM32_PWR_D3CR_VOS3,
-						};
+	volatile uint32_t *const vos_reg = &STM32_PWR_D3CR;
+	const uint32_t vos_ready = STM32_PWR_D3CR_VOSRDY;
+	const uint32_t vos_mask = STM32_PWR_D3CR_VOSMASK;
+	const uint32_t vos_values[] = {
+		/* See note below about VOS0. */
+		STM32_PWR_D3CR_VOS1,
+		STM32_PWR_D3CR_VOS1,
+		STM32_PWR_D3CR_VOS2,
+		STM32_PWR_D3CR_VOS3,
+	};
 	BUILD_ASSERT(ARRAY_SIZE(vos_values) == VOLTAGE_SCALE_COUNT);
 
 	/*
@@ -344,7 +344,8 @@ static void clock_set_osc(enum clock_osc osc)
 	case OSC_HSI:
 		/* Switch to HSI */
 		clock_switch_osc(osc);
-		current_bus_freq = clock_peripheral_configure(target_sysclk_freq);
+		current_bus_freq =
+			clock_peripheral_configure(target_sysclk_freq);
 		/* Use more optimized flash latency settings for 64-MHz ACLK */
 		clock_flash_latency(current_bus_freq, target_voltage_scale);
 		/* Turn off the PLL1 to save power */
@@ -368,7 +369,8 @@ static void clock_set_osc(enum clock_osc osc)
 		clock_pll1_configure(target_sysclk_freq);
 		/* turn on PLL1 and wait until it's ready */
 		clock_enable_osc(OSC_PLL, true);
-		current_bus_freq = clock_peripheral_configure(target_sysclk_freq);
+		current_bus_freq =
+			clock_peripheral_configure(target_sysclk_freq);
 		/* Increase flash latency before transition the clock */
 		clock_flash_latency(current_bus_freq, target_voltage_scale);
 
@@ -408,9 +410,9 @@ static int dsleep_recovery_margin_us = 1000000;
 static void low_power_init(void)
 {
 	/* Clock LPTIM1 on the 32-kHz LSI for STOP mode time keeping */
-	STM32_RCC_D2CCIP2R = (STM32_RCC_D2CCIP2R &
-		~STM32_RCC_D2CCIP2_LPTIM1SEL_MASK)
-		| STM32_RCC_D2CCIP2_LPTIM1SEL_LSI;
+	STM32_RCC_D2CCIP2R =
+		(STM32_RCC_D2CCIP2R & ~STM32_RCC_D2CCIP2_LPTIM1SEL_MASK) |
+		STM32_RCC_D2CCIP2_LPTIM1SEL_LSI;
 
 	/* configure LPTIM1 as our 1-Khz low power timer in STOP mode */
 	STM32_RCC_APB1LENR |= STM32_RCC_PB1_LPTIM1;
@@ -428,9 +430,8 @@ static void low_power_init(void)
 	STM32_EXTI_CPUIMR2 |= BIT(15); /* [15] wkup47: LPTIM1 wake-up */
 
 	/* optimize power vs latency in STOP mode */
-	STM32_PWR_CR = (STM32_PWR_CR & ~STM32_PWR_CR_SVOS_MASK)
-		     | STM32_PWR_CR_SVOS5
-		     | STM32_PWR_CR_FLPS;
+	STM32_PWR_CR = (STM32_PWR_CR & ~STM32_PWR_CR_SVOS_MASK) |
+		       STM32_PWR_CR_SVOS5 | STM32_PWR_CR_FLPS;
 }
 
 void clock_refresh_console_in_use(void)
@@ -544,7 +545,7 @@ void __idle(void)
 			/* ensure outstanding memory transactions complete */
 			asm volatile("dsb");
 
-			asm("wfi");
+			cpu_enter_suspend_mode();
 
 			CPU_SCB_SYSCTRL &= ~0x4;
 
@@ -579,7 +580,7 @@ void __idle(void)
 			idle_sleep_cnt++;
 
 			/* normal idle : only CPU clock stopped */
-			asm("wfi");
+			cpu_enter_suspend_mode();
 		}
 		interrupt_enable();
 	}
@@ -589,24 +590,23 @@ void __idle(void)
 /**
  * Print low power idle statistics
  */
-static int command_idle_stats(int argc, char **argv)
+static int command_idle_stats(int argc, const char **argv)
 {
 	timestamp_t ts = get_time();
 
 	ccprintf("Num idle calls that sleep:           %d\n", idle_sleep_cnt);
 	ccprintf("Num idle calls that deep-sleep:      %d\n", idle_dsleep_cnt);
 	ccprintf("Time spent in deep-sleep:            %.6llds\n",
-			idle_dsleep_time_us);
+		 idle_dsleep_time_us);
 	ccprintf("Num of prevented sleep:              %d\n",
-			idle_sleep_prevented_cnt);
+		 idle_sleep_prevented_cnt);
 	ccprintf("Total time on:                       %.6llds\n", ts.val);
 	ccprintf("Deep-sleep closest to wake deadline: %dus\n",
-			dsleep_recovery_margin_us);
+		 dsleep_recovery_margin_us);
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats,
-			"",
+DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, "",
 			"Print last idle stats");
 #endif /* CONFIG_CMD_IDLE_STATS */
 #endif /* CONFIG_LOW_POWER_IDLE */
@@ -638,11 +638,11 @@ void clock_init(void)
 	 * by putting it on the fixed 64-Mhz HSI clock.
 	 * per_ck is clocked directly by the HSI (as per the default settings).
 	 */
-	STM32_RCC_D2CCIP1R = (STM32_RCC_D2CCIP1R &
-		~(STM32_RCC_D2CCIP1R_SPI123SEL_MASK |
-		  STM32_RCC_D2CCIP1R_SPI45SEL_MASK))
-		| STM32_RCC_D2CCIP1R_SPI123SEL_PERCK
-		| STM32_RCC_D2CCIP1R_SPI45SEL_HSI;
+	STM32_RCC_D2CCIP1R =
+		(STM32_RCC_D2CCIP1R & ~(STM32_RCC_D2CCIP1R_SPI123SEL_MASK |
+					STM32_RCC_D2CCIP1R_SPI45SEL_MASK)) |
+		STM32_RCC_D2CCIP1R_SPI123SEL_PERCK |
+		STM32_RCC_D2CCIP1R_SPI45SEL_HSI;
 
 	/* Use more optimized flash latency settings for ACLK = HSI = 64 Mhz */
 	clock_flash_latency(FREQ_64MHZ, VOLTAGE_SCALE3);
@@ -657,7 +657,7 @@ void clock_init(void)
 #endif
 }
 
-static int command_clock(int argc, char **argv)
+static int command_clock(int argc, const char **argv)
 {
 	if (argc >= 2) {
 		if (!strcasecmp(argv[1], "hsi"))
@@ -670,5 +670,5 @@ static int command_clock(int argc, char **argv)
 	ccprintf("Clock frequency is now %d Hz\n", clock_get_freq());
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(clock, command_clock,
-			"hsi | pll", "Set clock frequency");
+DECLARE_CONSOLE_COMMAND(clock, command_clock, "hsi | pll",
+			"Set clock frequency");
diff --git a/chip/stm32/clock-stm32l.c b/chip/stm32/clock-stm32l.c
index bb0da42d14..1d0252302a 100644
--- a/chip/stm32/clock-stm32l.c
+++ b/chip/stm32/clock-stm32l.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -37,9 +37,9 @@ static int fake_hibernate;
 #define MSI_1MHZ_CLOCK BIT(20)
 
 enum clock_osc {
-	OSC_INIT = 0,	/* Uninitialized */
-	OSC_HSI,	/* High-speed oscillator */
-	OSC_MSI,	/* Med-speed oscillator @ 1 MHz */
+	OSC_INIT = 0, /* Uninitialized */
+	OSC_HSI, /* High-speed oscillator */
+	OSC_MSI, /* Med-speed oscillator @ 1 MHz */
 };
 
 static int freq;
@@ -86,8 +86,8 @@ static void clock_set_osc(enum clock_osc osc)
 	switch (osc) {
 	case OSC_HSI:
 		/* Ensure that HSI is ON */
-		wait_for_ready(&STM32_RCC_CR,
-			       STM32_RCC_CR_HSION, STM32_RCC_CR_HSIRDY);
+		wait_for_ready(&STM32_RCC_CR, STM32_RCC_CR_HSION,
+			       STM32_RCC_CR_HSIRDY);
 
 		/* Disable LPSDSR */
 		STM32_PWR_CR &= ~STM32_PWR_CR_LPSDSR;
@@ -122,7 +122,7 @@ static void clock_set_osc(enum clock_osc osc)
 		STM32_RCC_CFGR = STM32_RCC_CFGR_SW_HSI;
 		/* RM says to check SWS bits to make sure HSI is the sysclock */
 		while ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MASK) !=
-			STM32_RCC_CFGR_SWS_HSI)
+		       STM32_RCC_CFGR_SWS_HSI)
 			;
 
 		/* Disable MSI */
@@ -137,14 +137,14 @@ static void clock_set_osc(enum clock_osc osc)
 			(STM32_RCC_ICSCR & ~STM32_RCC_ICSCR_MSIRANGE_MASK) |
 			STM32_RCC_ICSCR_MSIRANGE_1MHZ;
 		/* Ensure that MSI is ON */
-		wait_for_ready(&STM32_RCC_CR,
-			       STM32_RCC_CR_MSION, STM32_RCC_CR_MSIRDY);
+		wait_for_ready(&STM32_RCC_CR, STM32_RCC_CR_MSION,
+			       STM32_RCC_CR_MSIRDY);
 
 		/* Switch to MSI */
 		STM32_RCC_CFGR = STM32_RCC_CFGR_SW_MSI;
 		/* RM says to check SWS bits to make sure MSI is the sysclock */
 		while ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MASK) !=
-			STM32_RCC_CFGR_SWS_MSI)
+		       STM32_RCC_CFGR_SWS_MSI)
 			;
 
 		/*
@@ -208,7 +208,6 @@ void clock_enable_module(enum module_id module, int enable)
 
 	/* Only change clock if needed */
 	if ((!!new_mask) != (!!clock_mask)) {
-
 		/* Flush UART before switching clock speed */
 		cflush();
 
@@ -314,7 +313,7 @@ static void fake_hibernate_power_button_hook(void)
 	}
 }
 DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, fake_hibernate_power_button_hook,
-	HOOK_PRIO_DEFAULT);
+	     HOOK_PRIO_DEFAULT);
 
 static void fake_hibernate_lid_hook(void)
 {
@@ -365,7 +364,7 @@ static void clock_chipset_shutdown(void)
 DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, clock_chipset_shutdown, HOOK_PRIO_DEFAULT);
 DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, clock_chipset_shutdown, HOOK_PRIO_DEFAULT);
 
-static int command_clock(int argc, char **argv)
+static int command_clock(int argc, const char **argv)
 {
 	if (argc >= 2) {
 		if (!strcasecmp(argv[1], "hsi"))
@@ -379,6 +378,5 @@ static int command_clock(int argc, char **argv)
 	ccprintf("Clock frequency is now %d Hz\n", freq);
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(clock, command_clock,
-			"hsi | msi",
+DECLARE_CONSOLE_COMMAND(clock, command_clock, "hsi | msi",
 			"Set clock frequency");
diff --git a/chip/stm32/clock-stm32l4.c b/chip/stm32/clock-stm32l4.c
index 730f5d6bb9..1c460c10fc 100644
--- a/chip/stm32/clock-stm32l4.c
+++ b/chip/stm32/clock-stm32l4.c
@@ -1,10 +1,11 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Clocks and power management settings for STM32L4xx as well as STM32L5xx. */
 
+#include "builtin/assert.h"
 #include "chipset.h"
 #include "clock.h"
 #include "clock-l4.h"
@@ -21,7 +22,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CLOCK, outstr)
-#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args)
 
 /* High-speed oscillator is 16 MHz */
 #define STM32_HSI_CLOCK 16000000
@@ -45,13 +46,13 @@
 #define SCALING 1000
 
 enum clock_osc {
-	OSC_INIT = 0,	/* Uninitialized */
-	OSC_HSI,	/* High-speed internal oscillator */
-	OSC_MSI,	/* Multi-speed internal oscillator */
-#ifdef STM32_HSE_CLOCK	/* Allows us to catch absence of HSE at comiple time */
-	OSC_HSE,	/* High-speed external oscillator */
+	OSC_INIT = 0, /* Uninitialized */
+	OSC_HSI, /* High-speed internal oscillator */
+	OSC_MSI, /* Multi-speed internal oscillator */
+#ifdef STM32_HSE_CLOCK /* Allows us to catch absence of HSE at comiple time */
+	OSC_HSE, /* High-speed external oscillator */
 #endif
-	OSC_PLL,	/* PLL */
+	OSC_PLL, /* PLL */
 };
 
 static int freq = STM32_MSI_CLOCK;
@@ -162,8 +163,8 @@ static void clock_switch_osc(enum clock_osc osc)
  * 5. Enable the desired PLL outputs by configuring PLLPEN, PLLQEN, PLLREN
  *    in RCC_PLLCFGR.
  */
-static int stm32_configure_pll(enum clock_osc osc,
-			       uint8_t m, uint8_t n, uint8_t r)
+static int stm32_configure_pll(enum clock_osc osc, uint8_t m, uint8_t n,
+			       uint8_t r)
 {
 	uint32_t val;
 	bool pll_unchanged;
@@ -323,9 +324,8 @@ static void clock_set_osc(enum clock_osc osc, enum clock_osc pll_osc)
 
 	case OSC_MSI:
 		/* Switch to MSI @ 1MHz */
-		STM32_RCC_CR =
-			(STM32_RCC_CR & ~STM32_RCC_ICSCR_MSIRANGE_MASK) |
-			STM32_RCC_ICSCR_MSIRANGE_1MHZ;
+		STM32_RCC_CR = (STM32_RCC_CR & ~STM32_RCC_ICSCR_MSIRANGE_MASK) |
+			       STM32_RCC_ICSCR_MSIRANGE_1MHZ;
 		/* Ensure that MSI is ON */
 		clock_enable_osc(osc);
 
@@ -353,7 +353,7 @@ static void clock_set_osc(enum clock_osc osc, enum clock_osc pll_osc)
 
 		/* Disable other clock sources */
 		STM32_RCC_CR &= ~(STM32_RCC_CR_MSION | STM32_RCC_CR_HSION |
-				STM32_RCC_CR_PLLON);
+				  STM32_RCC_CR_PLLON);
 
 		freq = STM32_HSE_CLOCK;
 
@@ -396,22 +396,22 @@ static void clock_set_osc(enum clock_osc osc, enum clock_osc pll_osc)
 			 */
 			val = STM32_FLASH_ACR;
 			val &= ~STM32_FLASH_ACR_LATENCY_MASK;
-			if (freq <= 16000000U)	{
+			if (freq <= 16000000U) {
 				val = val;
-			} else if (freq <= 32000000U)	{
+			} else if (freq <= 32000000U) {
 				val |= 1;
-			} else if (freq <= 48000000U)	{
+			} else if (freq <= 48000000U) {
 				val |= 2;
-			} else if (freq <= 64000000U)	{
+			} else if (freq <= 64000000U) {
 				val |= 3;
-			} else if (freq <= 80000000U)	{
+			} else if (freq <= 80000000U) {
 				val |= 4;
-			} else	{
+			} else {
 				val |= 4;
 				CPUTS("Incorrect Frequency setting in VOS1!\n");
 			}
 			STM32_FLASH_ACR = val;
-		} else	{
+		} else {
 			val = STM32_FLASH_ACR;
 			val &= ~STM32_FLASH_ACR_LATENCY_MASK;
 
@@ -423,7 +423,7 @@ static void clock_set_osc(enum clock_osc osc, enum clock_osc pll_osc)
 				val |= 2;
 			} else if (freq <= 26000000U) {
 				val |= 3;
-			} else	{
+			} else {
 				val |= 4;
 				CPUTS("Incorrect Frequency setting in VOS2!\n");
 			}
@@ -472,8 +472,8 @@ void clock_enable_module(enum module_id module, int enable)
 
 		/* ADC select bit 28/29 */
 		STM32_RCC_CCIPR &= ~STM32_RCC_CCIPR_ADCSEL_MSK;
-		STM32_RCC_CCIPR |= (STM32_RCC_CCIPR_ADCSEL_0 |
-				    STM32_RCC_CCIPR_ADCSEL_1);
+		STM32_RCC_CCIPR |=
+			(STM32_RCC_CCIPR_ADCSEL_0 | STM32_RCC_CCIPR_ADCSEL_1);
 		/* ADC clock enable */
 		if (enable)
 			STM32_RCC_AHB2ENR |= STM32_RCC_HB2_ADC1;
@@ -484,12 +484,11 @@ void clock_enable_module(enum module_id module, int enable)
 			STM32_RCC_APB1ENR1 |= STM32_RCC_PB1_SPI2;
 		else
 			STM32_RCC_APB1ENR1 &= ~STM32_RCC_PB1_SPI2;
-	} else if (module == MODULE_SPI ||
-		   module == MODULE_SPI_CONTROLLER) {
+	} else if (module == MODULE_SPI || module == MODULE_SPI_CONTROLLER) {
 		if (enable)
 			STM32_RCC_APB2ENR |= STM32_RCC_APB2ENR_SPI1EN;
-		else if ((new_mask & (BIT(MODULE_SPI) |
-				      BIT(MODULE_SPI_CONTROLLER))) == 0)
+		else if ((new_mask &
+			  (BIT(MODULE_SPI) | BIT(MODULE_SPI_CONTROLLER))) == 0)
 			STM32_RCC_APB2ENR &= ~STM32_RCC_APB2ENR_SPI1EN;
 	} else if (module == MODULE_USB) {
 #ifdef CHIP_FAMILY_STM32L5
@@ -588,7 +587,6 @@ void rtc_set(uint32_t sec)
 }
 #endif
 
-
 void clock_init(void)
 {
 #ifdef STM32_HSE_CLOCK
@@ -623,7 +621,7 @@ static void clock_chipset_shutdown(void)
 DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, clock_chipset_shutdown, HOOK_PRIO_DEFAULT);
 DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, clock_chipset_shutdown, HOOK_PRIO_DEFAULT);
 
-static int command_clock(int argc, char **argv)
+static int command_clock(int argc, const char **argv)
 {
 	if (argc >= 2) {
 		if (!strcasecmp(argv[1], "hsi"))
@@ -666,7 +664,6 @@ uint32_t us_to_rtcss(uint32_t us)
 		(us * (RTC_FREQ / SCALING) / (SECOND / SCALING)));
 }
 
-
 /* Convert decimal to BCD */
 static uint8_t u8_to_bcd(uint8_t val)
 {
@@ -684,12 +681,14 @@ static uint32_t rtc_tr_to_sec(uint32_t rtc_tr)
 
 	/* convert the hours field */
 	sec = (((rtc_tr & RTC_TR_HT) >> RTC_TR_HT_POS) * 10 +
-	       ((rtc_tr & RTC_TR_HU) >> RTC_TR_HU_POS)) * 3600;
+	       ((rtc_tr & RTC_TR_HU) >> RTC_TR_HU_POS)) *
+	      3600;
 	/* convert the minutes field */
 	sec += (((rtc_tr & RTC_TR_MNT) >> RTC_TR_MNT_POS) * 10 +
-		((rtc_tr & RTC_TR_MNU) >> RTC_TR_MNU_POS)) * 60;
+		((rtc_tr & RTC_TR_MNU) >> RTC_TR_MNU_POS)) *
+	       60;
 	/* convert the seconds field */
-	sec += ((rtc_tr & RTC_TR_ST) >> RTC_TR_ST_POS) *  10 +
+	sec += ((rtc_tr & RTC_TR_ST) >> RTC_TR_ST_POS) * 10 +
 	       (rtc_tr & RTC_TR_SU);
 	return sec;
 }
@@ -766,10 +765,9 @@ static uint32_t rtc_dr_to_sec(uint32_t rtc_dr)
 	struct calendar_date time;
 	uint32_t sec;
 
-	time.year = (((rtc_dr & 0xf00000) >> 20) * 10 +
-		    ((rtc_dr & 0xf0000) >> 16));
-	time.month = (((rtc_dr & 0x1000) >> 12) * 10 +
-		     ((rtc_dr & 0xf00) >> 8));
+	time.year =
+		(((rtc_dr & 0xf00000) >> 20) * 10 + ((rtc_dr & 0xf0000) >> 16));
+	time.month = (((rtc_dr & 0x1000) >> 12) * 10 + ((rtc_dr & 0xf00) >> 8));
 	time.day = ((rtc_dr & 0x30) >> 4) * 10 + (rtc_dr & 0xf);
 
 	sec = date_to_sec(time);
@@ -905,8 +903,8 @@ void set_rtc_alarm(uint32_t delay_s, uint32_t delay_us,
 	 * If the caller doesn't specify subsecond delay (e.g. host command),
 	 * just align the alarm time to second.
 	 */
-	STM32_RTC_ALRMASSR = delay_us ?
-			     (us_to_rtcss(alarm_us) | 0x0f000000) : 0;
+	STM32_RTC_ALRMASSR = delay_us ? (us_to_rtcss(alarm_us) | 0x0f000000) :
+					0;
 
 #ifdef CONFIG_HOSTCMD_RTC
 	/*
@@ -968,8 +966,7 @@ static void set_rtc_host_event(void)
 DECLARE_DEFERRED(set_rtc_host_event);
 #endif
 
-test_mockable_static
-void __rtc_alarm_irq(void)
+test_mockable_static void __rtc_alarm_irq(void)
 {
 	struct rtc_time_reg rtc;
 
@@ -985,7 +982,6 @@ void __rtc_alarm_irq(void)
 }
 DECLARE_IRQ(STM32_IRQ_RTC_ALARM, __rtc_alarm_irq, 1);
 
-
 void print_system_rtc(enum console_channel ch)
 {
 	uint32_t sec;
@@ -997,7 +993,6 @@ void print_system_rtc(enum console_channel ch)
 	cprintf(ch, "RTC: 0x%08x (%d.00 s)\n", sec, sec);
 }
 
-
 #ifdef CONFIG_LOW_POWER_IDLE
 /* Low power idle statistics */
 static int idle_sleep_cnt;
@@ -1015,7 +1010,6 @@ static int dsleep_recovery_margin_us = 1000000;
  */
 #define SET_RTC_MATCH_DELAY 120 /* us */
 
-
 void low_power_init(void)
 {
 	/* Enter stop1 mode */
@@ -1055,15 +1049,15 @@ void __idle(void)
 			/* Set deep sleep bit */
 			CPU_SCB_SYSCTRL |= 0x4;
 
-			set_rtc_alarm(0, next_delay - STOP_MODE_LATENCY
-						    - PLL_LOCK_LATENCY,
+			set_rtc_alarm(0,
+				      next_delay - STOP_MODE_LATENCY -
+					      PLL_LOCK_LATENCY,
 				      &rtc0, 0);
 
-
 			/* ensure outstanding memory transactions complete */
 			asm volatile("dsb");
 
-			asm("wfi");
+			cpu_enter_suspend_mode();
 
 			CPU_SCB_SYSCTRL &= ~0x4;
 
@@ -1071,8 +1065,8 @@ void __idle(void)
 			STM32_RCC_APB1ENR1 |= STM32_RCC_APB1ENR1_PWREN;
 			clock_wait_bus_cycles(BUS_APB, 2);
 
-			stm32_configure_pll(OSC_HSI, STM32_PLLM,
-						   STM32_PLLN, STM32_PLLR);
+			stm32_configure_pll(OSC_HSI, STM32_PLLM, STM32_PLLN,
+					    STM32_PLLR);
 
 			/* Switch to PLL */
 			clock_switch_osc(OSC_PLL);
@@ -1101,7 +1095,7 @@ void __idle(void)
 			idle_sleep_cnt++;
 
 			/* Normal idle : only CPU clock stopped */
-			asm("wfi");
+			cpu_enter_suspend_mode();
 		}
 		interrupt_enable();
 	}
@@ -1110,21 +1104,20 @@ void __idle(void)
 /*****************************************************************************/
 /* Console commands */
 /* Print low power idle statistics. */
-static int command_idle_stats(int argc, char **argv)
+static int command_idle_stats(int argc, const char **argv)
 {
 	timestamp_t ts = get_time();
 
 	ccprintf("Num idle calls that sleep:           %d\n", idle_sleep_cnt);
 	ccprintf("Num idle calls that deep-sleep:      %d\n", idle_dsleep_cnt);
 	ccprintf("Time spent in deep-sleep:            %.6llus\n",
-			idle_dsleep_time_us);
+		 idle_dsleep_time_us);
 	ccprintf("Total time on:                       %.6llus\n", ts.val);
 	ccprintf("Deep-sleep closest to wake deadline: %dus\n",
-			dsleep_recovery_margin_us);
+		 dsleep_recovery_margin_us);
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats,
-			"",
+DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, "",
 			"Print last idle stats");
 #endif /* CONFIG_LOW_POWER_IDLE */
diff --git a/chip/stm32/clock-stm32l5.c b/chip/stm32/clock-stm32l5.c
index 63f5b874bc..a4cf34f7b8 100644
--- a/chip/stm32/clock-stm32l5.c
+++ b/chip/stm32/clock-stm32l5.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/stm32/config-stm32f03x.h b/chip/stm32/config-stm32f03x.h
index 3c51086c26..695b16f0b3 100644
--- a/chip/stm32/config-stm32f03x.h
+++ b/chip/stm32/config-stm32f03x.h
@@ -1,25 +1,25 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #ifdef CHIP_VARIANT_STM32F03X8
 #define CONFIG_FLASH_SIZE_BYTES 0x00010000
-#define CONFIG_RAM_SIZE   0x00002000
+#define CONFIG_RAM_SIZE 0x00002000
 #else
 #define CONFIG_FLASH_SIZE_BYTES 0x00008000
-#define CONFIG_RAM_SIZE   0x00001000
+#define CONFIG_RAM_SIZE 0x00001000
 #endif
 
 /* Memory mapping */
-#define CONFIG_FLASH_BANK_SIZE  0x1000
-#define CONFIG_FLASH_ERASE_SIZE 0x0400  /* erase bank size */
-#define CONFIG_FLASH_WRITE_SIZE 0x0002  /* minimum write size */
+#define CONFIG_FLASH_BANK_SIZE 0x1000
+#define CONFIG_FLASH_ERASE_SIZE 0x0400 /* erase bank size */
+#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */
 
 /* No page mode on STM32F, so no benefit to larger write sizes */
 #define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002
 
-#define CONFIG_RAM_BASE         0x20000000
+#define CONFIG_RAM_BASE 0x20000000
 
 /* Number of IRQ vectors on the NVIC */
 #define CONFIG_IRQ_COUNT 32
diff --git a/chip/stm32/config-stm32f05x.h b/chip/stm32/config-stm32f05x.h
index 00bf45fde5..7f083b0eb2 100644
--- a/chip/stm32/config-stm32f05x.h
+++ b/chip/stm32/config-stm32f05x.h
@@ -1,19 +1,19 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Memory mapping */
 #define CONFIG_FLASH_SIZE_BYTES (64 * 1024)
-#define CONFIG_FLASH_BANK_SIZE  0x1000
-#define CONFIG_FLASH_ERASE_SIZE 0x0400  /* erase bank size */
-#define CONFIG_FLASH_WRITE_SIZE 0x0002  /* minimum write size */
+#define CONFIG_FLASH_BANK_SIZE 0x1000
+#define CONFIG_FLASH_ERASE_SIZE 0x0400 /* erase bank size */
+#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */
 
 /* No page mode on STM32F, so no benefit to larger write sizes */
 #define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002
 
-#define CONFIG_RAM_BASE         0x20000000
-#define CONFIG_RAM_SIZE         0x00002000
+#define CONFIG_RAM_BASE 0x20000000
+#define CONFIG_RAM_SIZE 0x00002000
 
 /* Number of IRQ vectors on the NVIC */
 #define CONFIG_IRQ_COUNT 32
diff --git a/chip/stm32/config-stm32f07x.h b/chip/stm32/config-stm32f07x.h
index 2aa8f6d37d..31468f656e 100644
--- a/chip/stm32/config-stm32f07x.h
+++ b/chip/stm32/config-stm32f07x.h
@@ -1,19 +1,19 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Memory mapping */
 #define CONFIG_FLASH_SIZE_BYTES (128 * 1024)
-#define CONFIG_FLASH_BANK_SIZE  0x1000
-#define CONFIG_FLASH_ERASE_SIZE 0x0800  /* erase bank size */
-#define CONFIG_FLASH_WRITE_SIZE 0x0002  /* minimum write size */
+#define CONFIG_FLASH_BANK_SIZE 0x1000
+#define CONFIG_FLASH_ERASE_SIZE 0x0800 /* erase bank size */
+#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */
 
 /* No page mode on STM32F, so no benefit to larger write sizes */
 #define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002
 
-#define CONFIG_RAM_BASE         0x20000000
-#define CONFIG_RAM_SIZE         0x00004000
+#define CONFIG_RAM_BASE 0x20000000
+#define CONFIG_RAM_SIZE 0x00004000
 
 /* Number of IRQ vectors on the NVIC */
 #define CONFIG_IRQ_COUNT 32
@@ -23,10 +23,10 @@
 #define CONFIG_CONSOLE_HISTORY 3
 
 /* USB packet ram config */
-#define CONFIG_USB_RAM_BASE        0x40006000
-#define CONFIG_USB_RAM_SIZE        1024
+#define CONFIG_USB_RAM_BASE 0x40006000
+#define CONFIG_USB_RAM_SIZE 1024
 #define CONFIG_USB_RAM_ACCESS_TYPE uint16_t
 #define CONFIG_USB_RAM_ACCESS_SIZE 2
 
 /* DFU Address */
-#define STM32_DFU_BASE              0x1fffC800
+#define STM32_DFU_BASE 0x1fffC800
diff --git a/chip/stm32/config-stm32f09x.h b/chip/stm32/config-stm32f09x.h
index 527e84db1b..405c63f3ec 100644
--- a/chip/stm32/config-stm32f09x.h
+++ b/chip/stm32/config-stm32f09x.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,15 +9,15 @@
  * Write protect sectors: 31 4KB sectors, one 132KB sector
  */
 #define CONFIG_FLASH_SIZE_BYTES 0x00040000
-#define CONFIG_FLASH_BANK_SIZE  0x1000
-#define CONFIG_FLASH_ERASE_SIZE 0x0800  /* erase bank size */
-#define CONFIG_FLASH_WRITE_SIZE 0x0002  /* minimum write size */
+#define CONFIG_FLASH_BANK_SIZE 0x1000
+#define CONFIG_FLASH_ERASE_SIZE 0x0800 /* erase bank size */
+#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */
 
 /* No page mode on STM32F, so no benefit to larger write sizes */
 #define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002
 
-#define CONFIG_RAM_BASE         0x20000000
-#define CONFIG_RAM_SIZE         0x00008000
+#define CONFIG_RAM_BASE 0x20000000
+#define CONFIG_RAM_SIZE 0x00008000
 
 /* Number of IRQ vectors on the NVIC */
 #define CONFIG_IRQ_COUNT 32
@@ -43,33 +43,33 @@
  *
  */
 
-#define _SECTOR_4KB             (4 * 1024)
-#define _SECTOR_132KB           (132 * 1024)
+#define _SECTOR_4KB (4 * 1024)
+#define _SECTOR_132KB (132 * 1024)
 
 /* The EC uses one sector to emulate persistent state */
 #define CONFIG_FLASH_PSTATE
-#define CONFIG_FW_PSTATE_SIZE   _SECTOR_4KB
-#define CONFIG_FW_PSTATE_OFF    (30 * _SECTOR_4KB)
+#define CONFIG_FW_PSTATE_SIZE _SECTOR_4KB
+#define CONFIG_FW_PSTATE_OFF (30 * _SECTOR_4KB)
 
-#define CONFIG_RO_MEM_OFF       0
-#define CONFIG_RO_STORAGE_OFF   0
-#define CONFIG_RO_SIZE          (30 * _SECTOR_4KB)
-#define CONFIG_RW_MEM_OFF       (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE + \
-				 CONFIG_FW_PSTATE_SIZE)
-#define CONFIG_RW_STORAGE_OFF	0
-#define CONFIG_RW_SIZE          _SECTOR_132KB
+#define CONFIG_RO_MEM_OFF 0
+#define CONFIG_RO_STORAGE_OFF 0
+#define CONFIG_RO_SIZE (30 * _SECTOR_4KB)
+#define CONFIG_RW_MEM_OFF \
+	(CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE + CONFIG_FW_PSTATE_SIZE)
+#define CONFIG_RW_STORAGE_OFF 0
+#define CONFIG_RW_SIZE _SECTOR_132KB
 
-#define CONFIG_EC_PROTECTED_STORAGE_OFF  0
+#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
 #define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_OFF   CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE  (CONFIG_FLASH_SIZE_BYTES - \
-					  CONFIG_EC_WRITABLE_STORAGE_OFF)
+#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE \
+	(CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF)
 
-#define CONFIG_WP_STORAGE_OFF   CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE  CONFIG_EC_PROTECTED_STORAGE_SIZE
+#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
+#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
 
 /* We map each write protect sector to a bank */
-#define PHYSICAL_BANKS          32
-#define WP_BANK_COUNT           31
-#define PSTATE_BANK             30
-#define PSTATE_BANK_COUNT       1
+#define PHYSICAL_BANKS 32
+#define WP_BANK_COUNT 31
+#define PSTATE_BANK 30
+#define PSTATE_BANK_COUNT 1
diff --git a/chip/stm32/config-stm32f373.h b/chip/stm32/config-stm32f373.h
index 7694db4421..f57350a17c 100644
--- a/chip/stm32/config-stm32f373.h
+++ b/chip/stm32/config-stm32f373.h
@@ -1,28 +1,28 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Memory mapping */
 #define CONFIG_FLASH_SIZE_BYTES 0x00040000
-#define CONFIG_FLASH_BANK_SIZE  0x2000
-#define CONFIG_FLASH_ERASE_SIZE 0x0800  /* erase bank size */
-#define CONFIG_FLASH_WRITE_SIZE 0x0002  /* minimum write size */
+#define CONFIG_FLASH_BANK_SIZE 0x2000
+#define CONFIG_FLASH_ERASE_SIZE 0x0800 /* erase bank size */
+#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */
 
 /* No page mode on STM32F, so no benefit to larger write sizes */
 #define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002
 
-#define CONFIG_RAM_BASE         0x20000000
-#define CONFIG_RAM_SIZE         0x00008000
+#define CONFIG_RAM_BASE 0x20000000
+#define CONFIG_RAM_SIZE 0x00008000
 
 /* Number of IRQ vectors on the NVIC */
 #define CONFIG_IRQ_COUNT 81
 
 /* STM32F3 uses the older 4 byte aligned access mechanism */
-#define CONFIG_USB_RAM_BASE        0x40006000
-#define CONFIG_USB_RAM_SIZE        512
+#define CONFIG_USB_RAM_BASE 0x40006000
+#define CONFIG_USB_RAM_SIZE 512
 #define CONFIG_USB_RAM_ACCESS_TYPE uint32_t
 #define CONFIG_USB_RAM_ACCESS_SIZE 4
 
 /* DFU Address */
-#define STM32_DFU_BASE              0x1fffd800
+#define STM32_DFU_BASE 0x1fffd800
diff --git a/chip/stm32/config-stm32f4.h b/chip/stm32/config-stm32f4.h
index ee1d594116..d7ef668886 100644
--- a/chip/stm32/config-stm32f4.h
+++ b/chip/stm32/config-stm32f4.h
@@ -1,13 +1,13 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Memory mapping */
 #ifdef CHIP_VARIANT_STM32F412
-#	define CONFIG_FLASH_SIZE_BYTES (1 * 1024 * 1024)
+#define CONFIG_FLASH_SIZE_BYTES (1 * 1024 * 1024)
 #else
-#	define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
+#define CONFIG_FLASH_SIZE_BYTES (512 * 1024)
 #endif
 
 /* 3 regions type: 16K, 64K and 128K */
@@ -31,33 +31,32 @@
 #define CONFIG_FLASH_WRITE_IDEAL_SIZE CONFIG_FLASH_WRITE_SIZE
 
 #ifdef CHIP_VARIANT_STM32F412
-#	define CONFIG_RAM_BASE  0x20000000
-#	define CONFIG_RAM_SIZE  0x00040000 /* 256 KB */
+#define CONFIG_RAM_BASE 0x20000000
+#define CONFIG_RAM_SIZE 0x00040000 /* 256 KB */
 #else
-#	define CONFIG_RAM_BASE  0x20000000
-#	define CONFIG_RAM_SIZE  0x00020000 /* 128 KB */
+#define CONFIG_RAM_BASE 0x20000000
+#define CONFIG_RAM_SIZE 0x00020000 /* 128 KB */
 #endif
 
-#define CONFIG_RO_MEM_OFF	0
-#define CONFIG_RO_SIZE		(256 * 1024)
-#define CONFIG_RW_MEM_OFF	(256 * 1024)
-#define CONFIG_RW_SIZE		(256 * 1024)
+#define CONFIG_RO_MEM_OFF 0
+#define CONFIG_RO_SIZE (256 * 1024)
+#define CONFIG_RW_MEM_OFF (256 * 1024)
+#define CONFIG_RW_SIZE (256 * 1024)
 
-#define CONFIG_RO_STORAGE_OFF	0
-#define CONFIG_RW_STORAGE_OFF	0
+#define CONFIG_RO_STORAGE_OFF 0
+#define CONFIG_RW_STORAGE_OFF 0
 
-#define CONFIG_EC_PROTECTED_STORAGE_OFF		0
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE	CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_OFF		CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE					\
-		 (CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF)
-
-#define CONFIG_WP_STORAGE_OFF		CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE		CONFIG_EC_PROTECTED_STORAGE_SIZE
+#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
+#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE \
+	(CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF)
 
+#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
+#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
 
 #undef I2C_PORT_COUNT
-#define I2C_PORT_COUNT	4
+#define I2C_PORT_COUNT 4
 
 /* Use PSTATE embedded in the RO image, not in its own erase block */
 #define CONFIG_FLASH_PSTATE
@@ -67,12 +66,12 @@
 #define CONFIG_OTP
 
 /* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT	97
+#define CONFIG_IRQ_COUNT 97
 
 #undef CONFIG_CMD_CHARGEN
 
 /* DFU Address */
-#define STM32_DFU_BASE              0x1fff0000
+#define STM32_DFU_BASE 0x1fff0000
 
 /*
  * SET_RTC_MATCH_DELAY: max time to set RTC match alarm. If we set the alarm
diff --git a/chip/stm32/config-stm32f76x.h b/chip/stm32/config-stm32f76x.h
index aa7f7ac5c0..e7380118f0 100644
--- a/chip/stm32/config-stm32f76x.h
+++ b/chip/stm32/config-stm32f76x.h
@@ -1,10 +1,10 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Memory mapping */
-#define CONFIG_FLASH_SIZE_BYTES       (2048 * 1024)
+#define CONFIG_FLASH_SIZE_BYTES (2048 * 1024)
 
 /* 3 regions type: 32K, 128K and 256K */
 #define SIZE_32KB (32 * 1024)
@@ -29,35 +29,35 @@
 /* DTCM-RAM: 128kB 0x20000000 - 0x2001FFFF*/
 /* SRAM1:    368kB 0x20020000 - 0x2007BFFF */
 /* SRAM2:     16kB 0x2007C000 - 0x2007FFFF */
-#define CONFIG_RAM_BASE		0x20000000
-#define CONFIG_RAM_SIZE		0x00080000
+#define CONFIG_RAM_BASE 0x20000000
+#define CONFIG_RAM_SIZE 0x00080000
 
-#define CONFIG_RO_MEM_OFF	0
-#define CONFIG_RO_SIZE		(1024 * 1024)
-#define CONFIG_RW_MEM_OFF	(1024 * 1024)
-#define CONFIG_RW_SIZE		(1024 * 1024)
+#define CONFIG_RO_MEM_OFF 0
+#define CONFIG_RO_SIZE (1024 * 1024)
+#define CONFIG_RW_MEM_OFF (1024 * 1024)
+#define CONFIG_RW_SIZE (1024 * 1024)
 
-#define CONFIG_RO_STORAGE_OFF	0
-#define CONFIG_RW_STORAGE_OFF	0
+#define CONFIG_RO_STORAGE_OFF 0
+#define CONFIG_RW_STORAGE_OFF 0
 
-#define CONFIG_EC_PROTECTED_STORAGE_OFF		0
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE	CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_OFF		CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE					\
-		 (CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF)
+#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
+#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE \
+	(CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF)
 
-#define CONFIG_WP_STORAGE_OFF		CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE		CONFIG_EC_PROTECTED_STORAGE_SIZE
+#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
+#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
 
 #undef I2C_PORT_COUNT
-#define I2C_PORT_COUNT	4
+#define I2C_PORT_COUNT 4
 
 /* Use PSTATE embedded in the RO image, not in its own erase block */
 #define CONFIG_FLASH_PSTATE
 #undef CONFIG_FLASH_PSTATE_BANK
 
 /* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT	109
+#define CONFIG_IRQ_COUNT 109
 
 /* DFU Address */
-#define STM32_DFU_BASE              0x1ff00000
+#define STM32_DFU_BASE 0x1ff00000
diff --git a/chip/stm32/config-stm32g41xb.h b/chip/stm32/config-stm32g41xb.h
index d6ec8696fb..97e9d21d25 100644
--- a/chip/stm32/config-stm32g41xb.h
+++ b/chip/stm32/config-stm32g41xb.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,12 +17,11 @@
  * PSTATE in single bank memories with a write size > 4 bytes.
  */
 
-#define CONFIG_FLASH_SIZE_BYTES       (128 * 1024)
+#define CONFIG_FLASH_SIZE_BYTES (128 * 1024)
 #define CONFIG_FLASH_WRITE_SIZE 0x0004
 #define CONFIG_FLASH_BANK_SIZE (2 * 1024)
 #define CONFIG_FLASH_ERASE_SIZE CONFIG_FLASH_BANK_SIZE
 
-
 /* Erasing 128K can take up to 2s, need to defer erase. */
 #define CONFIG_FLASH_DEFERRED_ERASE
 
@@ -37,11 +36,11 @@
  * • 10 Kbytes mapped at address 0x1000 0000 (CCM SRAM). It is also aliased
  *   at 0x2000 5800 address to be accessed by all bus controllers.
  */
-#define CONFIG_RAM_BASE		0x20000000
-#define CONFIG_RAM_SIZE		0x00008000
+#define CONFIG_RAM_BASE 0x20000000
+#define CONFIG_RAM_SIZE 0x00008000
 
 #undef I2C_PORT_COUNT
-#define I2C_PORT_COUNT	3
+#define I2C_PORT_COUNT 3
 
 /* Number of DMA channels supported (6 channels each for DMA1 and DMA2) */
 #define DMAC_COUNT 12
@@ -51,13 +50,13 @@
 #undef CONFIG_FLASH_PSTATE_BANK
 
 /* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT	101
+#define CONFIG_IRQ_COUNT 101
 
 /* USB packet ram config */
-#define CONFIG_USB_RAM_BASE        0x40006000
-#define CONFIG_USB_RAM_SIZE        1024
+#define CONFIG_USB_RAM_BASE 0x40006000
+#define CONFIG_USB_RAM_SIZE 1024
 #define CONFIG_USB_RAM_ACCESS_TYPE uint16_t
 #define CONFIG_USB_RAM_ACCESS_SIZE 2
 
 /* DFU Address */
-#define STM32_DFU_BASE              0x1fff0000
+#define STM32_DFU_BASE 0x1fff0000
diff --git a/chip/stm32/config-stm32g473xc.h b/chip/stm32/config-stm32g473xc.h
index 0317b69491..63f4c73ea0 100644
--- a/chip/stm32/config-stm32g473xc.h
+++ b/chip/stm32/config-stm32g473xc.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -42,11 +42,11 @@
  * • 32 Kbytes mapped at address 0x1000 0000 (CCM SRAM). It is also aliased
  *   at 0x2001 8000 address to be accessed by all bus controllers.
  */
-#define CONFIG_RAM_BASE		0x20000000
-#define CONFIG_RAM_SIZE		0x00020000
+#define CONFIG_RAM_BASE 0x20000000
+#define CONFIG_RAM_SIZE 0x00020000
 
 #undef I2C_PORT_COUNT
-#define I2C_PORT_COUNT	4
+#define I2C_PORT_COUNT 4
 
 /* Number of DMA channels supported (6 channels each for DMA1 and DMA2) */
 #define DMAC_COUNT 12
@@ -56,13 +56,13 @@
 #undef CONFIG_FLASH_PSTATE_BANK
 
 /* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT	101
+#define CONFIG_IRQ_COUNT 101
 
 /* USB packet ram config */
-#define CONFIG_USB_RAM_BASE        0x40006000
-#define CONFIG_USB_RAM_SIZE        1024
+#define CONFIG_USB_RAM_BASE 0x40006000
+#define CONFIG_USB_RAM_SIZE 1024
 #define CONFIG_USB_RAM_ACCESS_TYPE uint16_t
 #define CONFIG_USB_RAM_ACCESS_SIZE 2
 
 /* DFU Address */
-#define STM32_DFU_BASE              0x1fff0000
+#define STM32_DFU_BASE 0x1fff0000
diff --git a/chip/stm32/config-stm32h7x3.h b/chip/stm32/config-stm32h7x3.h
index 11da24b849..31f1d3c720 100644
--- a/chip/stm32/config-stm32h7x3.h
+++ b/chip/stm32/config-stm32h7x3.h
@@ -1,20 +1,20 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Memory mapping */
-#define CONFIG_FLASH_SIZE_BYTES       (2048 * 1024)
-#define CONFIG_FLASH_ERASE_SIZE (128 * 1024)  /* erase bank size */
+#define CONFIG_FLASH_SIZE_BYTES (2048 * 1024)
+#define CONFIG_FLASH_ERASE_SIZE (128 * 1024) /* erase bank size */
 /* always use 256-bit writes due to ECC */
-#define CONFIG_FLASH_WRITE_SIZE          32   /* minimum write size */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE    32
+#define CONFIG_FLASH_WRITE_SIZE 32 /* minimum write size */
+#define CONFIG_FLASH_WRITE_IDEAL_SIZE 32
 
 /*
  * What the code is calling 'bank' is really the size of the block used for
  * write-protected, here it's 128KB sector (same as erase size).
  */
-#define CONFIG_FLASH_BANK_SIZE  (128 * 1024)
+#define CONFIG_FLASH_BANK_SIZE (128 * 1024)
 
 /* Erasing 128K can take up to 2s, need to defer erase. */
 #define CONFIG_FLASH_DEFERRED_ERASE
@@ -27,28 +27,28 @@
 /* (D2) AHB-SRAM3:  32kB 0x30040000 - 0x30047FFF */
 /* (D3) AHB-SRAM4:  64kB 0x38000000 - 0x3800FFFF */
 /* (D3) backup RAM:  4kB 0x38800000 - 0x38800FFF */
-#define CONFIG_RAM_BASE		0x24000000
-#define CONFIG_RAM_SIZE		0x00080000
+#define CONFIG_RAM_BASE 0x24000000
+#define CONFIG_RAM_SIZE 0x00080000
 
-#define CONFIG_RO_MEM_OFF	0
-#define CONFIG_RO_SIZE		(128 * 1024)
-#define CONFIG_RW_MEM_OFF	(CONFIG_FLASH_SIZE_BYTES / 2)
-#define CONFIG_RW_SIZE		(512 * 1024)
+#define CONFIG_RO_MEM_OFF 0
+#define CONFIG_RO_SIZE (128 * 1024)
+#define CONFIG_RW_MEM_OFF (CONFIG_FLASH_SIZE_BYTES / 2)
+#define CONFIG_RW_SIZE (512 * 1024)
 
-#define CONFIG_RO_STORAGE_OFF	0
-#define CONFIG_RW_STORAGE_OFF	0
+#define CONFIG_RO_STORAGE_OFF 0
+#define CONFIG_RW_STORAGE_OFF 0
 
-#define CONFIG_EC_PROTECTED_STORAGE_OFF		0
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE	CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_OFF		CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE					\
-		 (CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF)
+#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
+#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE \
+	(CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF)
 
-#define CONFIG_WP_STORAGE_OFF		CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE		CONFIG_EC_PROTECTED_STORAGE_SIZE
+#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
+#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
 
 #undef I2C_PORT_COUNT
-#define I2C_PORT_COUNT	4
+#define I2C_PORT_COUNT 4
 
 /*
  * Cannot use PSTATE:
@@ -58,7 +58,7 @@
 #undef CONFIG_FLASH_PSTATE_BANK
 
 /* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT	150
+#define CONFIG_IRQ_COUNT 150
 
 /* the Cortex-M7 core has 'standard' ARMv7-M caches */
 #define CONFIG_ARMV7M_CACHE
@@ -68,9 +68,9 @@
 #define CONFIG_CHIP_UNCACHED_REGION ahb4
 /* Override MPU attribute settings to match the chip requirements */
 /* Code is Normal memory type / non-shareable / write-through */
-#define MPU_ATTR_FLASH_MEMORY  0x02
+#define MPU_ATTR_FLASH_MEMORY 0x02
 /* SRAM Data is Normal memory type / non-shareable / write-back, write-alloc */
 #define MPU_ATTR_INTERNAL_SRAM 0x0B
 
 /* DFU Address */
-#define STM32_DFU_BASE              0x1ff00000
+#define STM32_DFU_BASE 0x1ff00000
diff --git a/chip/stm32/config-stm32l100.h b/chip/stm32/config-stm32l100.h
index 2132fab4dd..ec28815525 100644
--- a/chip/stm32/config-stm32l100.h
+++ b/chip/stm32/config-stm32l100.h
@@ -1,12 +1,12 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Memory mapping */
 #define CONFIG_FLASH_SIZE_BYTES 0x00020000
-#define CONFIG_FLASH_BANK_SIZE  0x1000
-#define CONFIG_FLASH_ERASE_SIZE 0x0100  /* erase bank size */
+#define CONFIG_FLASH_BANK_SIZE 0x1000
+#define CONFIG_FLASH_ERASE_SIZE 0x0100 /* erase bank size */
 
 /*
  * TODO(crosbug.com/p/23805): Technically we can write in word-mode (4 bytes at
@@ -21,8 +21,8 @@
 /* Ideal write size in page-mode */
 #define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0080
 
-#define CONFIG_RAM_BASE         0x20000000
-#define CONFIG_RAM_SIZE         0x00002800
+#define CONFIG_RAM_BASE 0x20000000
+#define CONFIG_RAM_SIZE 0x00002800
 
 /* Number of IRQ vectors on the NVIC */
 #define CONFIG_IRQ_COUNT 45
@@ -37,10 +37,10 @@
 #define CONFIG_STM32L_FAKE_HIBERNATE
 
 /* USB packet ram config */
-#define CONFIG_USB_RAM_BASE        0x40006000
-#define CONFIG_USB_RAM_SIZE        512
+#define CONFIG_USB_RAM_BASE 0x40006000
+#define CONFIG_USB_RAM_SIZE 512
 #define CONFIG_USB_RAM_ACCESS_TYPE uint32_t
 #define CONFIG_USB_RAM_ACCESS_SIZE 4
 
 /* DFU Address */
-#define STM32_DFU_BASE              0x1ff00000
+#define STM32_DFU_BASE 0x1ff00000
diff --git a/chip/stm32/config-stm32l15x.h b/chip/stm32/config-stm32l15x.h
index 9f957d8981..ae069ed005 100644
--- a/chip/stm32/config-stm32l15x.h
+++ b/chip/stm32/config-stm32l15x.h
@@ -1,12 +1,12 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Memory mapping */
 #define CONFIG_FLASH_SIZE_BYTES 0x00020000
-#define CONFIG_FLASH_BANK_SIZE  0x1000
-#define CONFIG_FLASH_ERASE_SIZE 0x0100  /* erase bank size */
+#define CONFIG_FLASH_BANK_SIZE 0x1000
+#define CONFIG_FLASH_ERASE_SIZE 0x0100 /* erase bank size */
 
 /*
  * TODO(crosbug.com/p/23805): Technically we can write in word-mode (4 bytes at
@@ -21,8 +21,8 @@
 /* Ideal write size in page-mode */
 #define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0080
 
-#define CONFIG_RAM_BASE         0x20000000
-#define CONFIG_RAM_SIZE         0x00004000
+#define CONFIG_RAM_BASE 0x20000000
+#define CONFIG_RAM_SIZE 0x00004000
 
 /* Number of IRQ vectors on the NVIC */
 #define CONFIG_IRQ_COUNT 45
@@ -38,10 +38,10 @@
 #define CONFIG_FLASH_ERASED_VALUE32 0
 
 /* USB packet ram config */
-#define CONFIG_USB_RAM_BASE        0x40006000
-#define CONFIG_USB_RAM_SIZE        512
+#define CONFIG_USB_RAM_BASE 0x40006000
+#define CONFIG_USB_RAM_SIZE 512
 #define CONFIG_USB_RAM_ACCESS_TYPE uint32_t
 #define CONFIG_USB_RAM_ACCESS_SIZE 4
 
 /* DFU Address */
-#define STM32_DFU_BASE              0x1ff00000
+#define STM32_DFU_BASE 0x1ff00000
diff --git a/chip/stm32/config-stm32l431.h b/chip/stm32/config-stm32l431.h
index 64d8d39327..de3204945a 100644
--- a/chip/stm32/config-stm32l431.h
+++ b/chip/stm32/config-stm32l431.h
@@ -1,25 +1,25 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Memory mapping */
-#define CONFIG_FLASH_SIZE_BYTES  0x00040000   /* 256 kB */
+#define CONFIG_FLASH_SIZE_BYTES 0x00040000 /* 256 kB */
 #define CONFIG_FLASH_BANK_SIZE \
 	0x800 /* 2 kB. NOTE: BANK in chrome-ec means page */
-#define CONFIG_FLASH_ERASE_SIZE 0x800   /* 2 KB */
-#define CONFIG_FLASH_WRITE_SIZE 0x8     /* 64 bits */
+#define CONFIG_FLASH_ERASE_SIZE 0x800 /* 2 KB */
+#define CONFIG_FLASH_WRITE_SIZE 0x8 /* 64 bits */
 
 /* Ideal write size in page-mode */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100     /* 256 (32 double words) */
+#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100 /* 256 (32 double words) */
 
 /*
  * SRAM1 (48kB) at 0x20000000
  * SRAM2 (16kB) at 0x10000000 (and aliased at 0x2000C000)
  * so they are contiguous.
  */
-#define CONFIG_RAM_BASE         0x20000000
-#define CONFIG_RAM_SIZE         0x00010000      /* 64 kB */
+#define CONFIG_RAM_BASE 0x20000000
+#define CONFIG_RAM_SIZE 0x00010000 /* 64 kB */
 
 /* Number of IRQ vectors on the NVIC */
 #define CONFIG_IRQ_COUNT 82
@@ -45,36 +45,34 @@
  *
  */
 
-
-
 /* The EC uses one sector to emulate persistent state */
 #define CONFIG_FLASH_PSTATE
-#define CONFIG_FW_PSTATE_SIZE   CONFIG_FLASH_BANK_SIZE
-#define CONFIG_FW_PSTATE_OFF    (62 * CONFIG_FLASH_BANK_SIZE)
+#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE
+#define CONFIG_FW_PSTATE_OFF (62 * CONFIG_FLASH_BANK_SIZE)
 
-#define CONFIG_RO_MEM_OFF       0
-#define CONFIG_RO_STORAGE_OFF   0
-#define CONFIG_RO_SIZE          (62 * CONFIG_FLASH_BANK_SIZE)
-#define CONFIG_RW_MEM_OFF       (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE + \
-				 CONFIG_FW_PSTATE_SIZE)
-#define CONFIG_RW_STORAGE_OFF	0
-#define CONFIG_RW_SIZE          (CONFIG_FLASH_SIZE_BYTES - CONFIG_RW_MEM_OFF - \
-                                 CONFIG_RW_STORAGE_OFF)
+#define CONFIG_RO_MEM_OFF 0
+#define CONFIG_RO_STORAGE_OFF 0
+#define CONFIG_RO_SIZE (62 * CONFIG_FLASH_BANK_SIZE)
+#define CONFIG_RW_MEM_OFF \
+	(CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE + CONFIG_FW_PSTATE_SIZE)
+#define CONFIG_RW_STORAGE_OFF 0
+#define CONFIG_RW_SIZE \
+	(CONFIG_FLASH_SIZE_BYTES - CONFIG_RW_MEM_OFF - CONFIG_RW_STORAGE_OFF)
 
-#define CONFIG_EC_PROTECTED_STORAGE_OFF  0
+#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
 #define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_OFF   CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE  (CONFIG_FLASH_SIZE_BYTES - \
-					  CONFIG_EC_WRITABLE_STORAGE_OFF)
+#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE \
+	(CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF)
 
-#define CONFIG_WP_STORAGE_OFF   CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE  CONFIG_EC_PROTECTED_STORAGE_SIZE
+#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
+#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
 
 /* We map each write protect sector to a bank */
-#define PHYSICAL_BANKS          128
-#define WP_BANK_COUNT           63
-#define PSTATE_BANK             62
-#define PSTATE_BANK_COUNT       1
+#define PHYSICAL_BANKS 128
+#define WP_BANK_COUNT 63
+#define PSTATE_BANK 62
+#define PSTATE_BANK_COUNT 1
 
 /* DFU Address */
-#define STM32_DFU_BASE              0x1fff0000
+#define STM32_DFU_BASE 0x1fff0000
diff --git a/chip/stm32/config-stm32l442.h b/chip/stm32/config-stm32l442.h
index 8a2a284d69..b85e9b1454 100644
--- a/chip/stm32/config-stm32l442.h
+++ b/chip/stm32/config-stm32l442.h
@@ -1,27 +1,27 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Memory mapping */
-#define CONFIG_FLASH_SIZE_BYTES  0x00040000   /* 256 kB */
-#define CONFIG_FLASH_BANK_SIZE  0x800   /* 2 kB */
-#define CONFIG_FLASH_ERASE_SIZE 0x800   /* 2 KB */
-#define CONFIG_FLASH_WRITE_SIZE 0x8     /* 64 bits */
+#define CONFIG_FLASH_SIZE_BYTES 0x00040000 /* 256 kB */
+#define CONFIG_FLASH_BANK_SIZE 0x800 /* 2 kB */
+#define CONFIG_FLASH_ERASE_SIZE 0x800 /* 2 KB */
+#define CONFIG_FLASH_WRITE_SIZE 0x8 /* 64 bits */
 
 /* Ideal write size in page-mode */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100     /* 256 (32 double words) */
+#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100 /* 256 (32 double words) */
 
 /*
  * SRAM1 (48kB) at 0x20000000
  * SRAM2 (16kB) at 0x10000000 (and aliased at 0x2000C000)
  * so they are contiguous.
  */
-#define CONFIG_RAM_BASE         0x20000000
-#define CONFIG_RAM_SIZE         0x00010000      /* 64 kB */
+#define CONFIG_RAM_BASE 0x20000000
+#define CONFIG_RAM_SIZE 0x00010000 /* 64 kB */
 
 /* Number of IRQ vectors on the NVIC */
 #define CONFIG_IRQ_COUNT 82
 
 /* DFU Address */
-#define STM32_DFU_BASE              0x1fff0000
+#define STM32_DFU_BASE 0x1fff0000
diff --git a/chip/stm32/config-stm32l476.h b/chip/stm32/config-stm32l476.h
index 7f6fbb0f84..00a02e0ff9 100644
--- a/chip/stm32/config-stm32l476.h
+++ b/chip/stm32/config-stm32l476.h
@@ -1,23 +1,23 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Memory mapping */
-#define CONFIG_FLASH_SIZE_BYTES 0x00100000	/* 1 MB */
-#define CONFIG_FLASH_BANK_SIZE  0x800	/* 2 kB */
-#define CONFIG_FLASH_ERASE_SIZE 0x800	/* 2 KB */
-#define CONFIG_FLASH_WRITE_SIZE 0x8	/* 64 bits (without 8 bits ECC) */
+#define CONFIG_FLASH_SIZE_BYTES 0x00100000 /* 1 MB */
+#define CONFIG_FLASH_BANK_SIZE 0x800 /* 2 kB */
+#define CONFIG_FLASH_ERASE_SIZE 0x800 /* 2 KB */
+#define CONFIG_FLASH_WRITE_SIZE 0x8 /* 64 bits (without 8 bits ECC) */
 
 /* Ideal write size in page-mode */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100	/* 256 (32 double words) */
+#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100 /* 256 (32 double words) */
 
-#define CONFIG_RAM_BASE         0x20000000
+#define CONFIG_RAM_BASE 0x20000000
 /* Only using SRAM1. SRAM2 (32 KB) is ignored. */
-#define CONFIG_RAM_SIZE         0x00018000	/* 96 kB */
+#define CONFIG_RAM_SIZE 0x00018000 /* 96 kB */
 
 /* Number of IRQ vectors on the NVIC */
 #define CONFIG_IRQ_COUNT 82
 
 /* DFU Address */
-#define STM32_DFU_BASE              0x1fff0000
+#define STM32_DFU_BASE 0x1fff0000
diff --git a/chip/stm32/config-stm32l552xe.h b/chip/stm32/config-stm32l552xe.h
index 1b9c34c4aa..ba11b7f098 100644
--- a/chip/stm32/config-stm32l552xe.h
+++ b/chip/stm32/config-stm32l552xe.h
@@ -1,39 +1,39 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Memory mapping */
-#define CONFIG_FLASH_SIZE_BYTES  0x00080000   /* 512 kB */
-#define CONFIG_FLASH_BANK_SIZE  0x800   /* 2 kB */
-#define CONFIG_FLASH_ERASE_SIZE 0x800   /* 2 KB */
-#define CONFIG_FLASH_WRITE_SIZE 0x8     /* 64 bits */
+#define CONFIG_FLASH_SIZE_BYTES 0x00080000 /* 512 kB */
+#define CONFIG_FLASH_BANK_SIZE 0x800 /* 2 kB */
+#define CONFIG_FLASH_ERASE_SIZE 0x800 /* 2 KB */
+#define CONFIG_FLASH_WRITE_SIZE 0x8 /* 64 bits */
 
 /* Ideal write size in page-mode */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100     /* 256 (32 double words) */
+#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100 /* 256 (32 double words) */
 
 /*
  * SRAM1 (48kB) at 0x20000000
  * SRAM2 (16kB) at 0x10000000 (and aliased at 0x2000C000)
  * so they are contiguous.
  */
-#define CONFIG_RAM_BASE         0x20000000
-#define CONFIG_RAM_SIZE         0x00010000      /* 64 kB */
+#define CONFIG_RAM_BASE 0x20000000
+#define CONFIG_RAM_SIZE 0x00010000 /* 64 kB */
 
 /* Number of IRQ vectors on the NVIC */
 #define CONFIG_IRQ_COUNT 109
 
 /* USB packet ram config */
-#define CONFIG_USB_RAM_BASE        0x4000D800
-#define CONFIG_USB_RAM_SIZE        1024
+#define CONFIG_USB_RAM_BASE 0x4000D800
+#define CONFIG_USB_RAM_SIZE 1024
 #define CONFIG_USB_RAM_ACCESS_TYPE uint16_t
 #define CONFIG_USB_RAM_ACCESS_SIZE 2
 
 #undef I2C_PORT_COUNT
-#define I2C_PORT_COUNT	4
+#define I2C_PORT_COUNT 4
 
 /* Number of DMA channels supported (8 channels each for DMA1 and DMA2) */
 #define DMAC_COUNT 16
 
 /* DFU Address */
-#define STM32_DFU_BASE              0x0bf90000
+#define STM32_DFU_BASE 0x0bf90000
diff --git a/chip/stm32/config_chip.h b/chip/stm32/config_chip.h
index 4d630909e1..f85eef5c46 100644
--- a/chip/stm32/config_chip.h
+++ b/chip/stm32/config_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,19 +10,19 @@
 /* CPU core BFD configuration */
 #include "core/cortex-m0/config_core.h"
 /* IRQ priorities */
-#define STM32_IRQ_EXT0_1_PRIORITY	1
-#define STM32_IRQ_EXT2_3_PRIORITY	1
-#define STM32_IRQ_EXTI4_15_PRIORITY	1
+#define STM32_IRQ_EXT0_1_PRIORITY 1
+#define STM32_IRQ_EXT2_3_PRIORITY 1
+#define STM32_IRQ_EXTI4_15_PRIORITY 1
 #else
 /* CPU core BFD configuration */
 #include "core/cortex-m/config_core.h"
-#define STM32_IRQ_EXTI0_PRIORITY	1
-#define STM32_IRQ_EXTI1_PRIORITY	1
-#define STM32_IRQ_EXTI2_PRIORITY	1
-#define STM32_IRQ_EXTI3_PRIORITY	1
-#define STM32_IRQ_EXTI4_PRIORITY	1
-#define STM32_IRQ_EXTI9_5_PRIORITY	1
-#define STM32_IRQ_EXTI15_10_PRIORITY	1
+#define STM32_IRQ_EXTI0_PRIORITY 1
+#define STM32_IRQ_EXTI1_PRIORITY 1
+#define STM32_IRQ_EXTI2_PRIORITY 1
+#define STM32_IRQ_EXTI3_PRIORITY 1
+#define STM32_IRQ_EXTI4_PRIORITY 1
+#define STM32_IRQ_EXTI9_5_PRIORITY 1
+#define STM32_IRQ_EXTI15_10_PRIORITY 1
 #endif
 
 /* Default to UART 1 for EC console */
@@ -87,10 +87,8 @@
 /* Program is run directly from storage */
 #define CONFIG_MAPPED_STORAGE_BASE CONFIG_PROGRAM_MEMORY_BASE
 
-#if !defined(CHIP_FAMILY_STM32F4) && \
-	!defined(CHIP_FAMILY_STM32F7) && \
-	!defined(CHIP_FAMILY_STM32H7) && \
-	!defined(CHIP_VARIANT_STM32F09X) && \
+#if !defined(CHIP_FAMILY_STM32F4) && !defined(CHIP_FAMILY_STM32F7) &&        \
+	!defined(CHIP_FAMILY_STM32H7) && !defined(CHIP_VARIANT_STM32F09X) && \
 	!defined(CHIP_VARIANT_STM32L431X)
 /* Compute the rest of the flash params from these */
 #include "config_std_internal_flash.h"
@@ -132,7 +130,7 @@
 
 /* Interval between HOOK_TICK notifications */
 #define HOOK_TICK_INTERVAL_MS 500
-#define HOOK_TICK_INTERVAL    (HOOK_TICK_INTERVAL_MS * MSEC)
+#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC)
 
 /*
  * Use a timer to print a watchdog warning event before the actual watchdog
@@ -148,7 +146,7 @@
 #define CONFIG_RTC
 
 /* Number of peripheral request signals per DMA channel */
-#define STM32_DMA_PERIPHERALS_PER_CHANNEL	4
+#define STM32_DMA_PERIPHERALS_PER_CHANNEL 4
 
 /*
  * Use DMA for UART transmit for all platforms.  DMA for UART receive is
@@ -165,13 +163,13 @@
 /* Chip needs to do custom pre-init */
 #define CONFIG_CHIP_PRE_INIT
 
-#define GPIO_NAME_BY_PIN(port, index) #port#index
+#define GPIO_NAME_BY_PIN(port, index) #port #index
 #define GPIO_PIN(port, index) GPIO_##port, BIT(index)
 #define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m)
 
 /* Prescaler values for PLL. Currently used only by STM32L476 and STM32L431. */
-#define STM32_PLLM	1
-#define STM32_PLLN	1
-#define STM32_PLLR	1
+#define STM32_PLLM 1
+#define STM32_PLLN 1
+#define STM32_PLLR 1
 
 #endif /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/chip/stm32/crc_hw.h b/chip/stm32/crc_hw.h
index 2a50d5760e..495af2fb98 100644
--- a/chip/stm32/crc_hw.h
+++ b/chip/stm32/crc_hw.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,8 +17,8 @@ static inline void crc32_init(void)
 	/* Delay 1 AHB clock cycle after the clock is enabled */
 	clock_wait_bus_cycles(BUS_AHB, 1);
 	/* reset CRC state */
-	STM32_CRC_CR = STM32_CRC_CR_RESET | STM32_CRC_CR_REV_OUT
-		     | STM32_CRC_CR_REV_IN_WORD;
+	STM32_CRC_CR = STM32_CRC_CR_RESET | STM32_CRC_CR_REV_OUT |
+		       STM32_CRC_CR_REV_IN_WORD;
 	while (STM32_CRC_CR & 1)
 		;
 }
diff --git a/chip/stm32/debug_printf.c b/chip/stm32/debug_printf.c
index c4e151692c..3713d28d26 100644
--- a/chip/stm32/debug_printf.c
+++ b/chip/stm32/debug_printf.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,8 +27,6 @@ static int debug_txchar(void *context, int c)
 	return 0;
 }
 
-
-
 void debug_printf(const char *format, ...)
 {
 	va_list args;
@@ -102,8 +100,8 @@ void uart_init(void)
 	STM32_USART_BRR(UARTN_BASE) =
 		DIV_ROUND_NEAREST(CPU_CLOCK, CONFIG_UART_BAUD_RATE);
 	/* UART enabled, 8 Data bits, oversampling x16, no parity */
-	STM32_USART_CR1(UARTN_BASE) =
-		STM32_USART_CR1_UE | STM32_USART_CR1_TE | STM32_USART_CR1_RE;
+	STM32_USART_CR1(UARTN_BASE) = STM32_USART_CR1_UE | STM32_USART_CR1_TE |
+				      STM32_USART_CR1_RE;
 	/* 1 stop bit, no fancy stuff */
 	STM32_USART_CR2(UARTN_BASE) = 0x0000;
 	/* DMA disabled, special modes disabled, error interrupt disabled */
diff --git a/chip/stm32/debug_printf.h b/chip/stm32/debug_printf.h
index 6091cfc7fc..efd74d40b9 100644
--- a/chip/stm32/debug_printf.h
+++ b/chip/stm32/debug_printf.h
@@ -1,17 +1,17 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 /* Synchronous UART debug printf */
 
-#ifndef __CROS_EC_DEBUG_H
-#define __CROS_EC_DEBUG_H
+#ifndef __CROS_EC_DEBUG_PRINTF_H
+#define __CROS_EC_DEBUG_PRINTF_H
 
 #ifdef CONFIG_DEBUG_PRINTF
-__attribute__((__format__(__printf__, 1, 2)))
-void debug_printf(const char *format, ...);
+__attribute__((__format__(__printf__, 1, 2))) void
+debug_printf(const char *format, ...);
 #else
 #define debug_printf(...)
 #endif
 
-#endif /* __CROS_EC_DEBUG_H */
+#endif /* __CROS_EC_DEBUG_PRINTF_H */
diff --git a/chip/stm32/dfu_bootmanager_main.c b/chip/stm32/dfu_bootmanager_main.c
index 462dd08b60..452a7a6443 100644
--- a/chip/stm32/dfu_bootmanager_main.c
+++ b/chip/stm32/dfu_bootmanager_main.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -93,7 +93,7 @@ static void dfu_bootmanager_init(void)
 {
 	/* enable clock on Power module */
 #ifndef CHIP_FAMILY_STM32H7
-#ifdef	CHIP_FAMILY_STM32L4
+#ifdef CHIP_FAMILY_STM32L4
 	STM32_RCC_APB1ENR1 |= STM32_RCC_PWREN;
 #else
 	STM32_RCC_APB1ENR |= STM32_RCC_PWREN;
@@ -122,8 +122,8 @@ static void jump_to_rw(void)
 {
 	void (*addr)(void);
 
-	addr = (void (*)(void)) (*((uint32_t *) (CONFIG_PROGRAM_MEMORY_BASE +
-		CONFIG_RW_MEM_OFF + 4)));
+	addr = (void (*)(void))(*((uint32_t *)(CONFIG_PROGRAM_MEMORY_BASE +
+					       CONFIG_RW_MEM_OFF + 4)));
 
 	addr();
 }
@@ -132,7 +132,7 @@ static void jump_to_dfu(void)
 {
 	void (*addr)(void);
 
-	addr = (void (*)(void)) (*((uint32_t *) (STM32_DFU_BASE + 4)));
+	addr = (void (*)(void))(*((uint32_t *)(STM32_DFU_BASE + 4)));
 
 	/* Clear the scratchpad. */
 	dfu_bootmanager_backup_write(DFU_BOOTMANAGER_VALUE_CLEAR);
@@ -170,10 +170,18 @@ void exception_panic(void)
  * need to worry about concurrent access.
  */
 
-void task_clear_pending_irq(int irq) {}
-void interrupt_disable(void) {}
-void mutex_lock(mutex_t *mtx) {}
-void mutex_unlock(mutex_t *mtx) {}
+void task_clear_pending_irq(int irq)
+{
+}
+void interrupt_disable(void)
+{
+}
+void mutex_lock(mutex_t *mtx)
+{
+}
+void mutex_unlock(mutex_t *mtx)
+{
+}
 
 bool in_interrupt_context(void)
 {
diff --git a/chip/stm32/dfu_bootmanager_shared.c b/chip/stm32/dfu_bootmanager_shared.c
index 212ee0a9e9..de8edcff5d 100644
--- a/chip/stm32/dfu_bootmanager_shared.c
+++ b/chip/stm32/dfu_bootmanager_shared.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/chip/stm32/dfu_bootmanager_shared.h b/chip/stm32/dfu_bootmanager_shared.h
index 4003583ee2..df920f16a5 100644
--- a/chip/stm32/dfu_bootmanager_shared.h
+++ b/chip/stm32/dfu_bootmanager_shared.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -15,12 +15,12 @@
 #include "common.h"
 
 /* Registers to validate the backup memory region. */
-#define DFU_BOOTMANAGER_VALUE_MASK      0x00FF
-#define DFU_BOOTMANAGER_VALID_MASK      0xFF00
-#define DFU_BOOTMANAGER_VALID_CHECK     0xAA00
+#define DFU_BOOTMANAGER_VALUE_MASK 0x00FF
+#define DFU_BOOTMANAGER_VALID_MASK 0xFF00
+#define DFU_BOOTMANAGER_VALID_CHECK 0xAA00
 
-#define DFU_BOOTMANAGER_VALUE_CLEAR     0
-#define DFU_BOOTMANAGER_VALUE_DFU       UINT8_MAX
+#define DFU_BOOTMANAGER_VALUE_CLEAR 0
+#define DFU_BOOTMANAGER_VALUE_DFU UINT8_MAX
 
 /*
  * Reset and enter the DFU mode.
diff --git a/chip/stm32/dma-stm32f4.c b/chip/stm32/dma-stm32f4.c
index 3374cff7fc..3121089437 100644
--- a/chip/stm32/dma-stm32f4.c
+++ b/chip/stm32/dma-stm32f4.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,15 +14,15 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_DMA, outstr)
-#define CPRINTF(format, args...) cprintf(CC_DMA, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_DMA, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_DMA, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_DMA, format, ##args)
 
 stm32_dma_regs_t *STM32_DMA_REGS[] = { STM32_DMA1_REGS, STM32_DMA2_REGS };
 
 /* Callback data to use when IRQ fires */
 static struct {
-	void (*cb)(void *);	/* Callback function to call */
-	void *cb_data;		/* Callback data for callback function */
+	void (*cb)(void *); /* Callback function to call */
+	void *cb_data; /* Callback data for callback function */
 } dma_irq[STM32_DMAS_TOTAL_COUNT];
 
 /**
@@ -91,7 +91,7 @@ void dma_disable_all(void)
  * @param flags		DMA flags for the control register.
  */
 static void prepare_stream(enum dma_channel stream, unsigned count,
-		void *periph, void *memory, unsigned flags)
+			   void *periph, void *memory, unsigned flags)
 {
 	stm32_dma_stream_t *dma_stream = dma_get_channel(stream);
 	uint32_t ccr = STM32_DMA_CCR_PL_VERY_HIGH;
@@ -128,18 +128,17 @@ void dma_prepare_tx(const struct dma_option *option, unsigned count,
 	 * we're preparing the stream for transmit.
 	 */
 	prepare_stream(option->channel, count, option->periph, (void *)memory,
-			STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR_M2P |
-			option->flags);
+		       STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR_M2P |
+			       option->flags);
 }
 
-void dma_start_rx(const struct dma_option *option, unsigned count,
-		  void *memory)
+void dma_start_rx(const struct dma_option *option, unsigned count, void *memory)
 {
 	stm32_dma_stream_t *stream = dma_get_channel(option->channel);
 
 	prepare_stream(option->channel, count, option->periph, memory,
-			STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR_P2M |
-			option->flags);
+		       STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR_P2M |
+			       option->flags);
 	dma_go(stream);
 }
 
@@ -176,10 +175,8 @@ void dma_dump(enum dma_channel stream)
 	CPRINTF("scr=%x, sndtr=%x, spar=%x, sm0ar=%x, sfcr=%x\n",
 		dma_stream->scr, dma_stream->sndtr, dma_stream->spar,
 		dma_stream->sm0ar, dma_stream->sfcr);
-	CPRINTF("stream %d, isr=%x, ifcr=%x\n",
-		stream,
-		STM32_DMA_GET_ISR(stream),
-		STM32_DMA_GET_IFCR(stream));
+	CPRINTF("stream %d, isr=%x, ifcr=%x\n", stream,
+		STM32_DMA_GET_ISR(stream), STM32_DMA_GET_IFCR(stream));
 }
 
 void dma_check(enum dma_channel stream, char *buf)
@@ -218,7 +215,7 @@ void dma_test(enum dma_channel stream)
 	dma_stream->spar = (uint32_t)periph;
 	dma_stream->sm0ar = (uint32_t)memory;
 	dma_stream->sndtr = count;
-	dma_stream->sfcr  &= ~STM32_DMA_SFCR_DMDIS;
+	dma_stream->sfcr &= ~STM32_DMA_SFCR_DMDIS;
 	ctrl = STM32_DMA_CCR_PL_MEDIUM;
 	dma_stream->scr = ctrl;
 
@@ -300,17 +297,17 @@ void dma_clear_isr(enum dma_channel stream)
 }
 
 #ifdef CONFIG_DMA_DEFAULT_HANDLERS
-#define STM32_DMA_IDX(dma, x)   CONCAT4(STM32_DMA, dma, _STREAM, x)
-#define STM32_DMA_FCT(dma, x)   CONCAT4(dma_, dma, _event_interrupt_stream_, x)
-#define DECLARE_DMA_IRQ(dma, x) \
-	static void STM32_DMA_FCT(dma, x)(void) \
-	{ \
-		dma_clear_isr(STM32_DMA_IDX(dma, x)); \
-		if (dma_irq[STM32_DMA_IDX(dma, x)].cb != NULL) \
-			(*dma_irq[STM32_DMA_IDX(dma, x)].cb) \
-				(dma_irq[STM32_DMA_IDX(dma, x)].cb_data); \
-	} \
-	DECLARE_IRQ(CONCAT4(STM32_IRQ_DMA, dma, _STREAM, x), \
+#define STM32_DMA_IDX(dma, x) CONCAT4(STM32_DMA, dma, _STREAM, x)
+#define STM32_DMA_FCT(dma, x) CONCAT4(dma_, dma, _event_interrupt_stream_, x)
+#define DECLARE_DMA_IRQ(dma, x)                                          \
+	static void STM32_DMA_FCT(dma, x)(void)                          \
+	{                                                                \
+		dma_clear_isr(STM32_DMA_IDX(dma, x));                    \
+		if (dma_irq[STM32_DMA_IDX(dma, x)].cb != NULL)           \
+			(*dma_irq[STM32_DMA_IDX(dma, x)].cb)(            \
+				dma_irq[STM32_DMA_IDX(dma, x)].cb_data); \
+	}                                                                \
+	DECLARE_IRQ(CONCAT4(STM32_IRQ_DMA, dma, _STREAM, x),             \
 		    STM32_DMA_FCT(dma, x), 1);
 
 DECLARE_DMA_IRQ(1, 0);
diff --git a/chip/stm32/dma.c b/chip/stm32/dma.c
index ae5a83789d..fbf0d59627 100644
--- a/chip/stm32/dma.c
+++ b/chip/stm32/dma.c
@@ -1,8 +1,9 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "builtin/assert.h"
 #include "clock.h"
 #include "common.h"
 #include "console.h"
@@ -15,15 +16,14 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_DMA, outstr)
-#define CPRINTF(format, args...) cprintf(CC_DMA, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_DMA, format, ##args)
 
 /* Callback data to use when IRQ fires */
 static struct {
-	void (*cb)(void *);	/* Callback function to call */
-	void *cb_data;		/* Callback data for callback function */
+	void (*cb)(void *); /* Callback function to call */
+	void *cb_data; /* Callback data for callback function */
 } dma_irq[STM32_DMAC_COUNT];
 
-
 /**
  * Return the IRQ for the DMA channel
  *
@@ -36,9 +36,8 @@ static int dma_get_irq(enum dma_channel channel)
 	if (channel == STM32_DMAC_CH1)
 		return STM32_IRQ_DMA_CHANNEL_1;
 
-	return channel > STM32_DMAC_CH3 ?
-		STM32_IRQ_DMA_CHANNEL_4_7 :
-		STM32_IRQ_DMA_CHANNEL_2_3;
+	return channel > STM32_DMAC_CH3 ? STM32_IRQ_DMA_CHANNEL_4_7 :
+					  STM32_IRQ_DMA_CHANNEL_2_3;
 #elif defined(CHIP_FAMILY_STM32L4)
 	if (channel < STM32_DMAC_PER_CTLR)
 		return STM32_IRQ_DMA_CHANNEL_1 + channel;
@@ -55,7 +54,7 @@ static int dma_get_irq(enum dma_channel channel)
 		return STM32_IRQ_DMA_CHANNEL_1 + channel;
 	else
 		return STM32_IRQ_DMA2_CHANNEL1 +
-			(channel - STM32_DMAC_PER_CTLR);
+		       (channel - STM32_DMAC_PER_CTLR);
 #endif
 }
 
@@ -127,7 +126,7 @@ void dma_disable_all(void)
  *				0 for rx
  */
 static void prepare_channel(enum dma_channel channel, unsigned int count,
-		void *periph, void *memory, unsigned int flags)
+			    void *periph, void *memory, unsigned int flags)
 {
 	stm32_dma_chan_t *chan = dma_get_channel(channel);
 	uint32_t ccr = STM32_DMA_CCR_PL_VERY_HIGH;
@@ -161,8 +160,7 @@ void dma_prepare_tx(const struct dma_option *option, unsigned int count,
 	 * we're preparing the channel for transmit.
 	 */
 	prepare_channel(option->channel, count, option->periph, (void *)memory,
-			STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR |
-			option->flags);
+			STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR | option->flags);
 }
 
 void dma_start_rx(const struct dma_option *option, unsigned int count,
@@ -191,10 +189,9 @@ void dma_dump(enum dma_channel channel)
 	stm32_dma_regs_t *dma = STM32_DMA_REGS(channel);
 	stm32_dma_chan_t *chan = dma_get_channel(channel);
 
-	CPRINTF("ccr=%x, cndtr=%x, cpar=%x, cmar=%x\n", chan->ccr,
-		chan->cndtr, chan->cpar, chan->cmar);
-	CPRINTF("chan %d, isr=%x, ifcr=%x\n",
-		channel,
+	CPRINTF("ccr=%x, cndtr=%x, cpar=%x, cmar=%x\n", chan->ccr, chan->cndtr,
+		chan->cpar, chan->cmar);
+	CPRINTF("chan %d, isr=%x, ifcr=%x\n", channel,
 		(dma->isr >> ((channel % STM32_DMAC_PER_CTLR) * 4)) & 0xf,
 		(dma->ifcr >> ((channel % STM32_DMAC_PER_CTLR) * 4)) & 0xf);
 }
@@ -238,11 +235,12 @@ void dma_test(enum dma_channel channel)
 	ctrl = STM32_DMA_CCR_PL_MEDIUM;
 	chan->ccr = ctrl;
 
-	ctrl |= STM32_DMA_CCR_MINC; /* | STM32_DMA_CCR_DIR */;
+	ctrl |= STM32_DMA_CCR_MINC; /* | STM32_DMA_CCR_DIR */
+	;
 	ctrl |= STM32_DMA_CCR_MEM2MEM;
 	ctrl |= STM32_DMA_CCR_PINC;
-/*	ctrl |= STM32_DMA_CCR_MSIZE_32_BIT; */
-/*	ctrl |= STM32_DMA_CCR_PSIZE_32_BIT; */
+	/*	ctrl |= STM32_DMA_CCR_MSIZE_32_BIT; */
+	/*	ctrl |= STM32_DMA_CCR_PSIZE_32_BIT; */
 	chan->ccr = ctrl;
 	chan->ccr = ctrl | STM32_DMA_CCR_EN;
 
@@ -254,11 +252,13 @@ void dma_test(enum dma_channel channel)
 
 void dma_init(void)
 {
-#if defined(CHIP_FAMILY_STM32L4) || defined(CHIP_FAMILY_STM32L5)
-	STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_DMA1EN|STM32_RCC_AHB1ENR_DMA2EN;
-#elif defined(CHIP_FAMILY_STM32G4)
-	STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_DMA1EN|STM32_RCC_AHB1ENR_DMA2EN |
-		STM32_RCC_AHB1ENR_DMAMUXEN;
+#if defined(CHIP_FAMILY_STM32L4)
+	STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_DMA1EN |
+			     STM32_RCC_AHB1ENR_DMA2EN;
+#elif defined(CHIP_FAMILY_STM32G4) || defined(CHIP_FAMILY_STM32L5)
+	STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_DMA1EN |
+			     STM32_RCC_AHB1ENR_DMA2EN |
+			     STM32_RCC_AHB1ENR_DMAMUXEN;
 #else
 	STM32_RCC_AHBENR |= STM32_RCC_HB_DMA1;
 #endif
@@ -337,8 +337,8 @@ static void dma_event_interrupt_channel_1(void)
 	if (STM32_DMA1_REGS->isr & STM32_DMA_ISR_TCIF(STM32_DMAC_CH1)) {
 		dma_clear_isr(STM32_DMAC_CH1);
 		if (dma_irq[STM32_DMAC_CH1].cb != NULL)
-			(*dma_irq[STM32_DMAC_CH1].cb)
-				(dma_irq[STM32_DMAC_CH1].cb_data);
+			(*dma_irq[STM32_DMAC_CH1].cb)(
+				dma_irq[STM32_DMAC_CH1].cb_data);
 	}
 }
 DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_1, dma_event_interrupt_channel_1, 1);
@@ -360,9 +360,7 @@ DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_2_3, dma_event_interrupt_channel_2_3, 1);
 static void dma_event_interrupt_channel_4_7(void)
 {
 	int i;
-	const unsigned int max_chan = MIN(STM32_DMAC_CH7, STM32_DMAC_COUNT);
-
-	for (i = STM32_DMAC_CH4; i <= max_chan; i++) {
+	for (i = STM32_DMAC_CH4; i < STM32_DMAC_COUNT; i++) {
 		if (STM32_DMA1_REGS->isr & STM32_DMA_ISR_TCIF(i)) {
 			dma_clear_isr(i);
 			if (dma_irq[i].cb != NULL)
@@ -374,15 +372,15 @@ DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_4_7, dma_event_interrupt_channel_4_7, 1);
 
 #else /* !CHIP_FAMILY_STM32F0 */
 
-#define DECLARE_DMA_IRQ(x) \
-	static void CONCAT2(dma_event_interrupt_channel_, x)(void) \
-	{ \
-		dma_clear_isr(CONCAT2(STM32_DMAC_CH, x)); \
-		if (dma_irq[CONCAT2(STM32_DMAC_CH, x)].cb != NULL) \
-			(*dma_irq[CONCAT2(STM32_DMAC_CH, x)].cb) \
-				(dma_irq[CONCAT2(STM32_DMAC_CH, x)].cb_data); \
-	} \
-	DECLARE_IRQ(CONCAT2(STM32_IRQ_DMA_CHANNEL_, x), \
+#define DECLARE_DMA_IRQ(x)                                                   \
+	static void CONCAT2(dma_event_interrupt_channel_, x)(void)           \
+	{                                                                    \
+		dma_clear_isr(CONCAT2(STM32_DMAC_CH, x));                    \
+		if (dma_irq[CONCAT2(STM32_DMAC_CH, x)].cb != NULL)           \
+			(*dma_irq[CONCAT2(STM32_DMAC_CH, x)].cb)(            \
+				dma_irq[CONCAT2(STM32_DMAC_CH, x)].cb_data); \
+	}                                                                    \
+	DECLARE_IRQ(CONCAT2(STM32_IRQ_DMA_CHANNEL_, x),                      \
 		    CONCAT2(dma_event_interrupt_channel_, x), 1)
 
 DECLARE_DMA_IRQ(1);
@@ -396,7 +394,7 @@ DECLARE_DMA_IRQ(7);
 DECLARE_DMA_IRQ(9);
 DECLARE_DMA_IRQ(10);
 #endif
-#ifdef CHIP_FAMILY_STM32L4
+#if defined(CHIP_FAMILY_STM32L4) || defined(CHIP_FAMILY_STM32L5)
 DECLARE_DMA_IRQ(9);
 DECLARE_DMA_IRQ(10);
 DECLARE_DMA_IRQ(11);
diff --git a/chip/stm32/flash-f.c b/chip/stm32/flash-f.c
index 9e35a2c689..9bfdb1b6b7 100644
--- a/chip/stm32/flash-f.c
+++ b/chip/stm32/flash-f.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,6 +7,7 @@
 
 #include <stdbool.h>
 #include "battery.h"
+#include "builtin/assert.h"
 #include "console.h"
 #include "clock.h"
 #include "flash.h"
@@ -20,8 +21,8 @@
 #include "util.h"
 #include "watchdog.h"
 
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 /*
  * Approximate number of CPU cycles per iteration of the loop when polling
@@ -49,14 +50,15 @@
 
 /* Forward declarations */
 #if defined(CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE)
-static enum flash_rdp_level flash_physical_get_rdp_level(void);
+	static enum flash_rdp_level
+	flash_physical_get_rdp_level(void);
 static int flash_physical_set_rdp_level(enum flash_rdp_level level);
 #endif /* CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE */
 
 static inline int calculate_flash_timeout(void)
 {
-	return (FLASH_WRITE_TIMEOUT_US *
-		(clock_get_freq() / SECOND) / CYCLE_PER_FLASH_LOOP);
+	return (FLASH_WRITE_TIMEOUT_US * (clock_get_freq() / SECOND) /
+		CYCLE_PER_FLASH_LOOP);
 }
 
 static int wait_busy(void)
@@ -67,7 +69,6 @@ static int wait_busy(void)
 	return (timeout > 0) ? EC_SUCCESS : EC_ERROR_TIMEOUT;
 }
 
-
 void unlock_flash_control_register(void)
 {
 	STM32_FLASH_KEYR = FLASH_KEYR_KEY1;
@@ -134,7 +135,7 @@ bool flash_control_register_locked(void)
  * We at least unlock the control register lock.
  * We may also unlock other locks.
  */
-enum extra_lock_type  {
+enum extra_lock_type {
 	NO_EXTRA_LOCK = 0,
 	OPT_LOCK = 1,
 };
@@ -382,9 +383,7 @@ int crec_flash_physical_write(int offset, int size, const char *data)
 		watchdog_reload();
 
 		/* wait to be ready  */
-		for (i = 0;
-		     (STM32_FLASH_SR & FLASH_SR_BUSY) &&
-		     (i < timeout);
+		for (i = 0; (STM32_FLASH_SR & FLASH_SR_BUSY) && (i < timeout);
 		     i++)
 			;
 
@@ -392,9 +391,7 @@ int crec_flash_physical_write(int offset, int size, const char *data)
 		*address++ = quantum;
 
 		/* Wait for writes to complete */
-		for (i = 0;
-		     (STM32_FLASH_SR & FLASH_SR_BUSY) &&
-		     (i < timeout);
+		for (i = 0; (STM32_FLASH_SR & FLASH_SR_BUSY) && (i < timeout);
 		     i++)
 			;
 
@@ -429,7 +426,7 @@ int crec_flash_physical_erase(int offset, int size)
 	int sector = crec_flash_bank_index(offset);
 	/* we take advantage of sector_size == erase_size */
 	if ((sector < 0) || (crec_flash_bank_index(offset + size) < 0))
-		return EC_ERROR_INVAL;  /* Invalid range */
+		return EC_ERROR_INVAL; /* Invalid range */
 #endif
 
 	if (unlock(NO_EXTRA_LOCK) != EC_SUCCESS)
@@ -459,7 +456,7 @@ int crec_flash_physical_erase(int offset, int size)
 #ifdef CHIP_FAMILY_STM32F4
 		/* select page to erase */
 		STM32_FLASH_CR = (STM32_FLASH_CR & ~STM32_FLASH_CR_SNB_MASK) |
-			(sector << STM32_FLASH_CR_SNB_OFFSET);
+				 (sector << STM32_FLASH_CR_SNB_OFFSET);
 #else
 		/* select page to erase */
 		STM32_FLASH_AR = CONFIG_PROGRAM_MEMORY_BASE + offset;
@@ -472,7 +469,7 @@ int crec_flash_physical_erase(int offset, int size)
 		watchdog_reload();
 		while ((STM32_FLASH_SR & FLASH_SR_BUSY) &&
 		       (get_time().val < deadline.val)) {
-			usleep(timeout_us/100);
+			usleep(timeout_us / 100);
 		}
 		if (STM32_FLASH_SR & FLASH_SR_BUSY) {
 			res = EC_ERROR_TIMEOUT;
@@ -487,7 +484,7 @@ int crec_flash_physical_erase(int offset, int size)
 			res = EC_ERROR_UNKNOWN;
 			goto exit_er;
 		}
-next_sector:
+	next_sector:
 		size -= sector_size;
 		offset += sector_size;
 #ifdef CHIP_FAMILY_STM32F4
@@ -540,8 +537,7 @@ int crec_flash_physical_protect_at_boot(uint32_t new_flags)
 
 	original_val = val = STM32_OPTB_WP & STM32_OPTB_nWRP_ALL;
 
-	for (block = WP_BANK_OFFSET;
-	     block < WP_BANK_OFFSET + PHYSICAL_BANKS;
+	for (block = WP_BANK_OFFSET; block < WP_BANK_OFFSET + PHYSICAL_BANKS;
 	     block++) {
 		int protect = new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT;
 
@@ -573,10 +569,10 @@ static void unprotect_all_blocks(void)
 	write_optb(STM32_FLASH_nWRP_ALL, STM32_FLASH_nWRP_ALL);
 }
 
-#else   /* CHIP_FAMILY_STM32F4 */
+#else /* CHIP_FAMILY_STM32F4 */
 static int flash_physical_get_protect_at_boot(int block)
 {
-	uint8_t val = read_optb(STM32_OPTB_WRP_OFF(block/8));
+	uint8_t val = read_optb(STM32_OPTB_WRP_OFF(block / 8));
 	return (!(val & (1 << (block % 8)))) ? 1 : 0;
 }
 
@@ -589,11 +585,10 @@ int crec_flash_physical_protect_at_boot(uint32_t new_flags)
 	for (i = 0; i < 4; ++i)
 		original_val[i] = val[i] = read_optb(i * 2 + 8);
 
-	for (block = WP_BANK_OFFSET;
-	     block < WP_BANK_OFFSET + PHYSICAL_BANKS;
+	for (block = WP_BANK_OFFSET; block < WP_BANK_OFFSET + PHYSICAL_BANKS;
 	     block++) {
 		int protect = new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT;
-		int byte_off = STM32_OPTB_WRP_OFF(block/8) / 2 - 4;
+		int byte_off = STM32_OPTB_WRP_OFF(block / 8) / 2 - 4;
 
 		if (block >= WP_BANK_OFFSET &&
 		    block < WP_BANK_OFFSET + WP_BANK_COUNT)
@@ -601,7 +596,8 @@ int crec_flash_physical_protect_at_boot(uint32_t new_flags)
 #ifdef CONFIG_ROLLBACK
 		else if (block >= ROLLBACK_BANK_OFFSET &&
 			 block < ROLLBACK_BANK_OFFSET + ROLLBACK_BANK_COUNT)
-			protect |= new_flags & EC_FLASH_PROTECT_ROLLBACK_AT_BOOT;
+			protect |= new_flags &
+				   EC_FLASH_PROTECT_ROLLBACK_AT_BOOT;
 #endif
 #ifdef CONFIG_FLASH_PROTECT_RW
 		else
@@ -729,13 +725,12 @@ int crec_flash_pre_init(void)
 	uint32_t prot_flags = crec_flash_get_protect();
 	int need_reset = 0;
 
-
 #ifdef CHIP_FAMILY_STM32F4
 	unlock(NO_EXTRA_LOCK);
 	/* Set the proper write size */
 	STM32_FLASH_CR = (STM32_FLASH_CR & ~STM32_FLASH_CR_PSIZE_MASK) |
-		 (31 - __builtin_clz(CONFIG_FLASH_WRITE_SIZE)) <<
-		 STM32_FLASH_CR_PSIZE_OFFSET;
+			 (31 - __builtin_clz(CONFIG_FLASH_WRITE_SIZE))
+				 << STM32_FLASH_CR_PSIZE_OFFSET;
 	lock();
 #endif
 	if (crec_flash_physical_restore_state())
@@ -776,8 +771,8 @@ int crec_flash_pre_init(void)
 			 * to the check above.  One of them should be able to
 			 * go away.
 			 */
-			crec_flash_protect_at_boot(
-				prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT);
+			crec_flash_protect_at_boot(prot_flags &
+						   EC_FLASH_PROTECT_RO_AT_BOOT);
 			need_reset = 1;
 		}
 	} else {
@@ -792,7 +787,7 @@ int crec_flash_pre_init(void)
 	}
 
 	if ((crec_flash_physical_get_valid_flags() &
-	    EC_FLASH_PROTECT_ALL_AT_BOOT) &&
+	     EC_FLASH_PROTECT_ALL_AT_BOOT) &&
 	    (!!(prot_flags & EC_FLASH_PROTECT_ALL_AT_BOOT) !=
 	     !!(prot_flags & EC_FLASH_PROTECT_ALL_NOW))) {
 		/*
@@ -808,7 +803,7 @@ int crec_flash_pre_init(void)
 
 #ifdef CONFIG_FLASH_PROTECT_RW
 	if ((crec_flash_physical_get_valid_flags() &
-	    EC_FLASH_PROTECT_RW_AT_BOOT) &&
+	     EC_FLASH_PROTECT_RW_AT_BOOT) &&
 	    (!!(prot_flags & EC_FLASH_PROTECT_RW_AT_BOOT) !=
 	     !!(prot_flags & EC_FLASH_PROTECT_RW_NOW))) {
 		/* RW_AT_BOOT and RW_NOW do not match. */
@@ -818,7 +813,7 @@ int crec_flash_pre_init(void)
 
 #ifdef CONFIG_ROLLBACK
 	if ((crec_flash_physical_get_valid_flags() &
-	    EC_FLASH_PROTECT_ROLLBACK_AT_BOOT) &&
+	     EC_FLASH_PROTECT_ROLLBACK_AT_BOOT) &&
 	    (!!(prot_flags & EC_FLASH_PROTECT_ROLLBACK_AT_BOOT) !=
 	     !!(prot_flags & EC_FLASH_PROTECT_ROLLBACK_NOW))) {
 		/* ROLLBACK_AT_BOOT and ROLLBACK_NOW do not match. */
diff --git a/chip/stm32/flash-f.h b/chip/stm32/flash-f.h
index cbbe6ec86f..507ded32f1 100644
--- a/chip/stm32/flash-f.h
+++ b/chip/stm32/flash-f.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,16 +9,16 @@
 #include <stdbool.h>
 
 enum flash_rdp_level {
-	FLASH_RDP_LEVEL_INVALID = -1,	/**< Error occurred. */
-	FLASH_RDP_LEVEL_0,		/**< No read protection. */
-	FLASH_RDP_LEVEL_1,		/**< Reading flash is disabled while in
-					 *   bootloader mode or JTAG attached.
-					 *   Changing to Level 0 from this level
-					 *   triggers mass erase.
-					 */
-	FLASH_RDP_LEVEL_2,		/**< Same as Level 1, but is permanent
-					 *   and can never be disabled.
-					 */
+	FLASH_RDP_LEVEL_INVALID = -1, /**< Error occurred. */
+	FLASH_RDP_LEVEL_0, /**< No read protection. */
+	FLASH_RDP_LEVEL_1, /**< Reading flash is disabled while in
+			    *   bootloader mode or JTAG attached.
+			    *   Changing to Level 0 from this level
+			    *   triggers mass erase.
+			    */
+	FLASH_RDP_LEVEL_2, /**< Same as Level 1, but is permanent
+			    *   and can never be disabled.
+			    */
 };
 
 bool is_flash_rdp_enabled(void);
diff --git a/chip/stm32/flash-regs.h b/chip/stm32/flash-regs.h
index b0a46667a1..9456c03963 100644
--- a/chip/stm32/flash-regs.h
+++ b/chip/stm32/flash-regs.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/stm32/flash-stm32f0.c b/chip/stm32/flash-stm32f0.c
index f790a657c8..058a8afc46 100644
--- a/chip/stm32/flash-stm32f0.c
+++ b/chip/stm32/flash-stm32f0.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -65,8 +65,7 @@ uint32_t crec_flash_physical_get_protect_flags(void)
 		/* Default: RW. */
 		int region = FLASH_REGION_RW;
 
-		if (i >= WP_BANK_OFFSET &&
-		    i < WP_BANK_OFFSET + WP_BANK_COUNT)
+		if (i >= WP_BANK_OFFSET && i < WP_BANK_OFFSET + WP_BANK_COUNT)
 			region = FLASH_REGION_RO;
 #ifdef CONFIG_ROLLBACK
 		if (i >= ROLLBACK_BANK_OFFSET &&
@@ -95,11 +94,11 @@ uint32_t crec_flash_physical_get_protect_flags(void)
 
 	for (i = 0; i < FLASH_REGION_COUNT; i++) {
 		if (!(wrp01 & wrp_mask[i][0]) &&
-			(wrp01 & wrp_mask[i][0] << 8) == (wrp_mask[i][0] << 8))
+		    (wrp01 & wrp_mask[i][0] << 8) == (wrp_mask[i][0] << 8))
 #if CONFIG_FLASH_SIZE_BYTES > 64 * 1024
 			if (!(wrp23 & wrp_mask[i][1]) &&
-			     (wrp23 & wrp_mask[i][1] << 8) ==
-							 (wrp_mask[i][1] << 8))
+			    (wrp23 & wrp_mask[i][1] << 8) ==
+				    (wrp_mask[i][1] << 8))
 #endif
 				flags |= mask_flags[i];
 	}
@@ -127,18 +126,15 @@ int crec_flash_physical_restore_state(void)
 
 uint32_t crec_flash_physical_get_valid_flags(void)
 {
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-	       EC_FLASH_PROTECT_RO_NOW |
+	return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW |
 #ifdef CONFIG_FLASH_PROTECT_RW
-	       EC_FLASH_PROTECT_RW_AT_BOOT |
-	       EC_FLASH_PROTECT_RW_NOW |
+	       EC_FLASH_PROTECT_RW_AT_BOOT | EC_FLASH_PROTECT_RW_NOW |
 #endif
 #ifdef CONFIG_ROLLBACK
 	       EC_FLASH_PROTECT_ROLLBACK_AT_BOOT |
 	       EC_FLASH_PROTECT_ROLLBACK_NOW |
 #endif
-	       EC_FLASH_PROTECT_ALL_AT_BOOT |
-	       EC_FLASH_PROTECT_ALL_NOW;
+	       EC_FLASH_PROTECT_ALL_AT_BOOT | EC_FLASH_PROTECT_ALL_NOW;
 }
 
 uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
@@ -153,13 +149,13 @@ uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
 	 * ALL/RW at-boot state can be set if WP GPIO is asserted and can always
 	 * be cleared.
 	 */
-	if (cur_flags & (EC_FLASH_PROTECT_ALL_AT_BOOT |
-			 EC_FLASH_PROTECT_GPIO_ASSERTED))
+	if (cur_flags &
+	    (EC_FLASH_PROTECT_ALL_AT_BOOT | EC_FLASH_PROTECT_GPIO_ASSERTED))
 		ret |= EC_FLASH_PROTECT_ALL_AT_BOOT;
 
 #ifdef CONFIG_FLASH_PROTECT_RW
-	if (cur_flags & (EC_FLASH_PROTECT_RW_AT_BOOT |
-			 EC_FLASH_PROTECT_GPIO_ASSERTED))
+	if (cur_flags &
+	    (EC_FLASH_PROTECT_RW_AT_BOOT | EC_FLASH_PROTECT_GPIO_ASSERTED))
 		ret |= EC_FLASH_PROTECT_RW_AT_BOOT;
 #endif
 
diff --git a/chip/stm32/flash-stm32f3.c b/chip/stm32/flash-stm32f3.c
index 138e690fcc..8705e4d657 100644
--- a/chip/stm32/flash-stm32f3.c
+++ b/chip/stm32/flash-stm32f3.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -102,7 +102,7 @@ int crec_flash_physical_get_protect(int block)
 #elif defined(CHIP_FAMILY_STM32F4)
 		!(STM32_OPTB_WP & STM32_OPTB_nWRP(block))
 #endif
-	       );
+	);
 }
 
 uint32_t crec_flash_physical_get_protect_flags(void)
@@ -137,8 +137,7 @@ int crec_flash_physical_protect_now(int all)
 
 uint32_t crec_flash_physical_get_valid_flags(void)
 {
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-	       EC_FLASH_PROTECT_RO_NOW |
+	return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW |
 	       EC_FLASH_PROTECT_ALL_NOW;
 }
 
@@ -173,7 +172,7 @@ int crec_flash_physical_restore_state(void)
 	 */
 	if (reset_flags & EC_RESET_FLAG_SYSJUMP) {
 		prev = (const struct flash_wp_state *)system_get_jump_tag(
-				FLASH_SYSJUMP_TAG, &version, &size);
+			FLASH_SYSJUMP_TAG, &version, &size);
 		if (prev && version == FLASH_HOOK_VERSION &&
 		    size == sizeof(*prev))
 			entire_flash_locked = prev->entire_flash_locked;
diff --git a/chip/stm32/flash-stm32f4.c b/chip/stm32/flash-stm32f4.c
index 6ff8130e17..8705e4d657 120000..100644
--- a/chip/stm32/flash-stm32f4.c
+++ b/chip/stm32/flash-stm32f4.c
@@ -1 +1,197 @@
-flash-stm32f3.c
\ No newline at end of file
+/* Copyright 2017 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Flash memory module for stm32f3 and stm32f4 */
+
+#include <stdbool.h>
+#include "common.h"
+#include "flash.h"
+#include "flash-f.h"
+#include "flash-regs.h"
+#include "hooks.h"
+#include "registers.h"
+#include "system.h"
+#include "panic.h"
+
+/*****************************************************************************/
+/* Physical layer APIs */
+#ifdef CHIP_VARIANT_STM32F76X
+/*
+ * 8 "erase" sectors : 32KB/32KB/32KB/32KB/128KB/256KB/256KB/256KB
+ */
+struct ec_flash_bank const flash_bank_array[] = {
+	{
+		.count = 4,
+		.size_exp = __fls(SIZE_32KB),
+		.write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE),
+		.erase_size_exp = __fls(SIZE_32KB),
+		.protect_size_exp = __fls(SIZE_32KB),
+	},
+	{
+		.count = 1,
+		.size_exp = __fls(SIZE_128KB),
+		.write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE),
+		.erase_size_exp = __fls(SIZE_128KB),
+		.protect_size_exp = __fls(SIZE_128KB),
+	},
+	{
+		.count = (CONFIG_FLASH_SIZE_BYTES - SIZE_256KB) / SIZE_256KB,
+		.write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE),
+		.size_exp = __fls(SIZE_256KB),
+		.erase_size_exp = __fls(SIZE_256KB),
+		.protect_size_exp = __fls(SIZE_256KB),
+	},
+};
+#elif defined(CHIP_FAMILY_STM32F4)
+/*
+ * STM32F412xE has 512 KB flash
+ *   8 "erase" sectors (512 KB) : 16KB/16KB/16KB/16KB/64KB/128KB/128KB/128KB
+ *
+ * STM32F412xG has 1 MB flash
+ *   12 "erase" sectors (1024 KB) :
+ *           16KB/16KB/16KB/16KB/64KB/128KB/128KB/128KB/128KB/128KB/128KB/128KB
+ *
+ * https://www.st.com/resource/en/datasheet/stm32f412cg.pdf
+ */
+struct ec_flash_bank const flash_bank_array[] = {
+	{
+		.count = 4,
+		.size_exp = __fls(SIZE_16KB),
+		.write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE),
+		.erase_size_exp = __fls(SIZE_16KB),
+		.protect_size_exp = __fls(SIZE_16KB),
+	},
+	{
+		.count = 1,
+		.size_exp = __fls(SIZE_64KB),
+		.write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE),
+		.erase_size_exp = __fls(SIZE_64KB),
+		.protect_size_exp = __fls(SIZE_64KB),
+	},
+	{
+		.count = (CONFIG_FLASH_SIZE_BYTES - SIZE_128KB) / SIZE_128KB,
+		.write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE),
+		.size_exp = __fls(SIZE_128KB),
+		.erase_size_exp = __fls(SIZE_128KB),
+		.protect_size_exp = __fls(SIZE_128KB),
+	},
+};
+#endif
+
+/* Flag indicating whether we have locked down entire flash */
+static int entire_flash_locked;
+
+#define FLASH_SYSJUMP_TAG 0x5750 /* "WP" - Write Protect */
+#define FLASH_HOOK_VERSION 1
+
+/* The previous write protect state before sys jump */
+struct flash_wp_state {
+	int entire_flash_locked;
+};
+
+/*****************************************************************************/
+/* Physical layer APIs */
+
+int crec_flash_physical_get_protect(int block)
+{
+	return (entire_flash_locked ||
+#if defined(CHIP_FAMILY_STM32F3)
+		!(STM32_FLASH_WRPR & BIT(block))
+#elif defined(CHIP_FAMILY_STM32F4)
+		!(STM32_OPTB_WP & STM32_OPTB_nWRP(block))
+#endif
+	);
+}
+
+uint32_t crec_flash_physical_get_protect_flags(void)
+{
+	uint32_t flags = 0;
+
+	/* Read all-protected state from our shadow copy */
+	if (entire_flash_locked)
+		flags |= EC_FLASH_PROTECT_ALL_NOW;
+
+#if defined(CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE)
+	if (is_flash_rdp_enabled())
+		flags |= EC_FLASH_PROTECT_RO_AT_BOOT;
+#endif
+
+	return flags;
+}
+
+int crec_flash_physical_protect_now(int all)
+{
+	if (all) {
+		disable_flash_control_register();
+		entire_flash_locked = 1;
+
+		return EC_SUCCESS;
+	}
+
+	disable_flash_option_bytes();
+
+	return EC_SUCCESS;
+}
+
+uint32_t crec_flash_physical_get_valid_flags(void)
+{
+	return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW |
+	       EC_FLASH_PROTECT_ALL_NOW;
+}
+
+uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
+{
+	uint32_t ret = 0;
+
+	/* If RO protection isn't enabled, its at-boot state can be changed. */
+	if (!(cur_flags & EC_FLASH_PROTECT_RO_NOW))
+		ret |= EC_FLASH_PROTECT_RO_AT_BOOT;
+
+	/*
+	 * If entire flash isn't protected at this boot, it can be enabled if
+	 * the WP GPIO is asserted.
+	 */
+	if (!(cur_flags & EC_FLASH_PROTECT_ALL_NOW) &&
+	    (cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED))
+		ret |= EC_FLASH_PROTECT_ALL_NOW;
+
+	return ret;
+}
+
+int crec_flash_physical_restore_state(void)
+{
+	uint32_t reset_flags = system_get_reset_flags();
+	int version, size;
+	const struct flash_wp_state *prev;
+
+	/*
+	 * If we have already jumped between images, an earlier image could
+	 * have applied write protection. Nothing additional needs to be done.
+	 */
+	if (reset_flags & EC_RESET_FLAG_SYSJUMP) {
+		prev = (const struct flash_wp_state *)system_get_jump_tag(
+			FLASH_SYSJUMP_TAG, &version, &size);
+		if (prev && version == FLASH_HOOK_VERSION &&
+		    size == sizeof(*prev))
+			entire_flash_locked = prev->entire_flash_locked;
+		return 1;
+	}
+
+	return 0;
+}
+
+/*****************************************************************************/
+/* Hooks */
+
+static void flash_preserve_state(void)
+{
+	struct flash_wp_state state;
+
+	state.entire_flash_locked = entire_flash_locked;
+
+	system_add_jump_tag(FLASH_SYSJUMP_TAG, FLASH_HOOK_VERSION,
+			    sizeof(state), &state);
+}
+DECLARE_HOOK(HOOK_SYSJUMP, flash_preserve_state, HOOK_PRIO_DEFAULT);
diff --git a/chip/stm32/flash-stm32g4-l4.c b/chip/stm32/flash-stm32g4-l4.c
index f792da6e3c..31dba5c887 100644
--- a/chip/stm32/flash-stm32g4-l4.c
+++ b/chip/stm32/flash-stm32g4-l4.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -37,31 +37,31 @@
 #define FLASH_PAGE_SIZE CONFIG_FLASH_BANK_SIZE
 #define FLASH_PAGE_MAX_COUNT (CONFIG_FLASH_SIZE_BYTES / FLASH_PAGE_SIZE)
 #define FLASH_RO_FIRST_PAGE_IDX WP_BANK_OFFSET
-#define FLASH_RO_LAST_PAGE_IDX ((CONFIG_WP_STORAGE_SIZE / FLASH_PAGE_SIZE) \
-				 + FLASH_RO_FIRST_PAGE_IDX - 1)
+#define FLASH_RO_LAST_PAGE_IDX                        \
+	((CONFIG_WP_STORAGE_SIZE / FLASH_PAGE_SIZE) + \
+	 FLASH_RO_FIRST_PAGE_IDX - 1)
 #define FLASH_RW_FIRST_PAGE_IDX (FLASH_RO_LAST_PAGE_IDX + 1)
 #define FLASH_RW_LAST_PAGE_IDX (FLASH_PAGE_MAX_COUNT - 1)
 
-
 #define FLASH_PAGE_ROLLBACK_COUNT ROLLBACK_BANK_COUNT
 #define FLASH_PAGE_ROLLBACK_FIRST_IDX ROLLBACK_BANK_OFFSET
-#define FLASH_PAGE_ROLLBACK_LAST_IDX (FLASH_PAGE_ROLLBACK_FIRST_IDX +\
-					FLASH_PAGE_ROLLBACK_COUNT -1)
+#define FLASH_PAGE_ROLLBACK_LAST_IDX \
+	(FLASH_PAGE_ROLLBACK_FIRST_IDX + FLASH_PAGE_ROLLBACK_COUNT - 1)
 
 #ifdef STM32_FLASH_DBANK_MODE
-#define FLASH_WRP_MASK              (FLASH_PAGE_MAX_COUNT - 1)
+#define FLASH_WRP_MASK (FLASH_PAGE_MAX_COUNT - 1)
 #else
 #ifdef CHIP_FAMILY_STM32L4
-#define FLASH_WRP_MASK              0xFF
+#define FLASH_WRP_MASK 0xFF
 #else
-#define FLASH_WRP_MASK              ((FLASH_PAGE_MAX_COUNT) / 2 - 1)
+#define FLASH_WRP_MASK ((FLASH_PAGE_MAX_COUNT) / 2 - 1)
 #endif
 #endif /* CONFIG_FLASH_DBANK_MODE */
-#define FLASH_WRP_START(val)        ((val) & FLASH_WRP_MASK)
-#define FLASH_WRP_END(val)          (((val) >> 16) & FLASH_WRP_MASK)
-#define FLASH_WRP_RANGE(start, end) (((start) & FLASH_WRP_MASK) | \
-				       (((end) & FLASH_WRP_MASK) << 16))
-#define FLASH_WRP_RANGE_DISABLED    FLASH_WRP_RANGE(FLASH_WRP_MASK, 0x00)
+#define FLASH_WRP_START(val) ((val)&FLASH_WRP_MASK)
+#define FLASH_WRP_END(val) (((val) >> 16) & FLASH_WRP_MASK)
+#define FLASH_WRP_RANGE(start, end) \
+	(((start)&FLASH_WRP_MASK) | (((end)&FLASH_WRP_MASK) << 16))
+#define FLASH_WRP_RANGE_DISABLED FLASH_WRP_RANGE(FLASH_WRP_MASK, 0x00)
 #define FLASH_WRP1X_MASK FLASH_WRP_RANGE(FLASH_WRP_MASK, FLASH_WRP_MASK)
 
 enum wrp_region {
@@ -77,8 +77,8 @@ struct wrp_info {
 
 static inline int calculate_flash_timeout(void)
 {
-	return (FLASH_TIMEOUT_US *
-		(clock_get_freq() / SECOND) / CYCLE_PER_FLASH_LOOP);
+	return (FLASH_TIMEOUT_US * (clock_get_freq() / SECOND) /
+		CYCLE_PER_FLASH_LOOP);
 }
 
 static int wait_while_busy(void)
@@ -104,8 +104,7 @@ static int unlock(int locks)
 		STM32_FLASH_KEYR = FLASH_KEYR_KEY2;
 	}
 	/* unlock option memory if required */
-	if ((locks & FLASH_CR_OPTLOCK) &&
-	    (STM32_FLASH_CR & FLASH_CR_OPTLOCK)) {
+	if ((locks & FLASH_CR_OPTLOCK) && (STM32_FLASH_CR & FLASH_CR_OPTLOCK)) {
 		STM32_FLASH_OPTKEYR = FLASH_OPTKEYR_KEY1;
 		STM32_FLASH_OPTKEYR = FLASH_OPTKEYR_KEY2;
 	}
@@ -113,8 +112,8 @@ static int unlock(int locks)
 	/* Re-enable bus fault handler */
 	ignore_bus_fault(0);
 
-	return (STM32_FLASH_CR & (locks | FLASH_CR_LOCK)) ? EC_ERROR_UNKNOWN
-							  : EC_SUCCESS;
+	return (STM32_FLASH_CR & (locks | FLASH_CR_LOCK)) ? EC_ERROR_UNKNOWN :
+							    EC_SUCCESS;
 }
 
 static void lock(void)
@@ -299,10 +298,10 @@ static void optb_set_wrp(enum wrp_region region, struct wrp_info *wrp)
 			 * value. Otherwise, can use end passed in directly.
 			 */
 			if (start <= FLASH_WRP_MASK) {
-				rw_end = end > FLASH_WRP_MASK ?
-					FLASH_WRP_MASK : end;
-				STM32_FLASH_WRP1BR = FLASH_WRP_RANGE(start,
-								     rw_end);
+				rw_end = end > FLASH_WRP_MASK ? FLASH_WRP_MASK :
+								end;
+				STM32_FLASH_WRP1BR =
+					FLASH_WRP_RANGE(start, rw_end);
 			}
 			/*
 			 * If the last RW flash page is in the 2nd half of
@@ -366,8 +365,8 @@ int crec_flash_physical_protect_at_boot(uint32_t new_flags)
 	 * write protection in the option bytes. Based on new_flags either RO or
 	 * RW or both regions write protect may be set.
 	 */
-	if (new_flags & (EC_FLASH_PROTECT_ALL_AT_BOOT |
-			 EC_FLASH_PROTECT_RO_AT_BOOT)) {
+	if (new_flags &
+	    (EC_FLASH_PROTECT_ALL_AT_BOOT | EC_FLASH_PROTECT_RO_AT_BOOT)) {
 		wrp_ro.start = FLASH_RO_FIRST_PAGE_IDX;
 		wrp_ro.end = FLASH_RO_LAST_PAGE_IDX;
 		wrp_ro.enable = 1;
@@ -434,9 +433,9 @@ static int registers_need_reset(void)
 	/* The RO region is write-protected by the WRP1AR range. */
 	uint32_t wrp1ar = STM32_OPTB_WRP1AR;
 	uint32_t ro_range = ro_at_boot ?
-		FLASH_WRP_RANGE(FLASH_RO_FIRST_PAGE_IDX,
-				  FLASH_RO_LAST_PAGE_IDX)
-		: FLASH_WRP_RANGE_DISABLED;
+				    FLASH_WRP_RANGE(FLASH_RO_FIRST_PAGE_IDX,
+						    FLASH_RO_LAST_PAGE_IDX) :
+				    FLASH_WRP_RANGE_DISABLED;
 
 	return ro_range != (wrp1ar & FLASH_WRP1X_MASK);
 }
@@ -484,10 +483,10 @@ int crec_flash_physical_write(int offset, int size, const char *data)
 
 		/* write the 2 words */
 		if (unaligned) {
-			*address++ = (uint32_t)data[0] | (data[1] << 8)
-				   | (data[2] << 16) | (data[3] << 24);
-			*address++ = (uint32_t)data[4] | (data[5] << 8)
-				   | (data[6] << 16) | (data[7] << 24);
+			*address++ = (uint32_t)data[0] | (data[1] << 8) |
+				     (data[2] << 16) | (data[3] << 24);
+			*address++ = (uint32_t)data[4] | (data[5] << 8) |
+				     (data[6] << 16) | (data[7] << 24);
 			data += STM32_FLASH_MIN_WRITE_SIZE;
 		} else {
 			*address++ = *data32++;
@@ -540,8 +539,8 @@ int crec_flash_physical_erase(int offset, int size)
 		timestamp_t deadline;
 
 		/* select page to erase and PER bit */
-		STM32_FLASH_CR = (STM32_FLASH_CR & ~FLASH_CR_PNB_MASK)
-				| FLASH_CR_PER | FLASH_CR_PNB(pg);
+		STM32_FLASH_CR = (STM32_FLASH_CR & ~FLASH_CR_PNB_MASK) |
+				 FLASH_CR_PER | FLASH_CR_PNB(pg);
 
 		/* set STRT bit : start erase */
 		STM32_FLASH_CR |= FLASH_CR_STRT;
@@ -591,7 +590,7 @@ int crec_flash_physical_get_protect(int block)
 	optb_get_wrp(WRP_RW, &wrp_rw);
 
 	return ((block >= wrp_ro.start) && (block <= wrp_ro.end)) ||
-		((block >= wrp_rw.start) && (block <= wrp_rw.end));
+	       ((block >= wrp_rw.start) && (block <= wrp_rw.end));
 }
 
 /*
@@ -613,7 +612,6 @@ uint32_t crec_flash_physical_get_protect_flags(void)
 		flags |= EC_FLASH_PROTECT_RO_AT_BOOT;
 
 	if (wrp_rw.enable) {
-
 #ifdef CONFIG_ROLLBACK
 		if (wrp_rw.start <= FLASH_PAGE_ROLLBACK_FIRST_IDX &&
 		    wrp_rw.end >= FLASH_PAGE_ROLLBACK_LAST_IDX)
@@ -639,18 +637,15 @@ int crec_flash_physical_protect_now(int all)
 
 uint32_t crec_flash_physical_get_valid_flags(void)
 {
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-	       EC_FLASH_PROTECT_RO_NOW |
+	return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW |
 #ifdef CONFIG_FLASH_PROTECT_RW
-	       EC_FLASH_PROTECT_RW_AT_BOOT |
-	       EC_FLASH_PROTECT_RW_NOW |
+	       EC_FLASH_PROTECT_RW_AT_BOOT | EC_FLASH_PROTECT_RW_NOW |
 #endif
 #ifdef CONFIG_ROLLBACK
 	       EC_FLASH_PROTECT_ROLLBACK_AT_BOOT |
 	       EC_FLASH_PROTECT_ROLLBACK_NOW |
 #endif
-	       EC_FLASH_PROTECT_ALL_AT_BOOT |
-	       EC_FLASH_PROTECT_ALL_NOW;
+	       EC_FLASH_PROTECT_ALL_AT_BOOT | EC_FLASH_PROTECT_ALL_NOW;
 }
 
 uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
@@ -665,13 +660,13 @@ uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
 	 * ALL/RW at-boot state can be set if WP GPIO is asserted and can always
 	 * be cleared.
 	 */
-	if (cur_flags & (EC_FLASH_PROTECT_ALL_AT_BOOT |
-			 EC_FLASH_PROTECT_GPIO_ASSERTED))
+	if (cur_flags &
+	    (EC_FLASH_PROTECT_ALL_AT_BOOT | EC_FLASH_PROTECT_GPIO_ASSERTED))
 		ret |= EC_FLASH_PROTECT_ALL_AT_BOOT;
 
 #ifdef CONFIG_FLASH_PROTECT_RW
-	if (cur_flags & (EC_FLASH_PROTECT_RW_AT_BOOT |
-			 EC_FLASH_PROTECT_GPIO_ASSERTED))
+	if (cur_flags &
+	    (EC_FLASH_PROTECT_RW_AT_BOOT | EC_FLASH_PROTECT_GPIO_ASSERTED))
 		ret |= EC_FLASH_PROTECT_RW_AT_BOOT;
 #endif
 
@@ -735,8 +730,8 @@ int crec_flash_pre_init(void)
 			 * to the check above.  One of them should be able to
 			 * go away.
 			 */
-			crec_flash_protect_at_boot(
-				prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT);
+			crec_flash_protect_at_boot(prot_flags &
+						   EC_FLASH_PROTECT_RO_AT_BOOT);
 			need_reset = 1;
 		}
 	} else {
@@ -751,7 +746,7 @@ int crec_flash_pre_init(void)
 	}
 
 	if ((crec_flash_physical_get_valid_flags() &
-	    EC_FLASH_PROTECT_ALL_AT_BOOT) &&
+	     EC_FLASH_PROTECT_ALL_AT_BOOT) &&
 	    (!!(prot_flags & EC_FLASH_PROTECT_ALL_AT_BOOT) !=
 	     !!(prot_flags & EC_FLASH_PROTECT_ALL_NOW))) {
 		/*
@@ -767,7 +762,7 @@ int crec_flash_pre_init(void)
 
 #ifdef CONFIG_FLASH_PROTECT_RW
 	if ((crec_flash_physical_get_valid_flags() &
-	    EC_FLASH_PROTECT_RW_AT_BOOT) &&
+	     EC_FLASH_PROTECT_RW_AT_BOOT) &&
 	    (!!(prot_flags & EC_FLASH_PROTECT_RW_AT_BOOT) !=
 	     !!(prot_flags & EC_FLASH_PROTECT_RW_NOW))) {
 		/* RW_AT_BOOT and RW_NOW do not match. */
diff --git a/chip/stm32/flash-stm32h7.c b/chip/stm32/flash-stm32h7.c
index 087ddbf062..445b354e57 100644
--- a/chip/stm32/flash-stm32h7.c
+++ b/chip/stm32/flash-stm32h7.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -45,7 +45,7 @@
  * not what is called 'bank' in the common code (ie Write-Protect sectors)
  * both have the same number of 128KB blocks.
  */
-#define HWBANK_SIZE  (CONFIG_FLASH_SIZE_BYTES / 2)
+#define HWBANK_SIZE (CONFIG_FLASH_SIZE_BYTES / 2)
 #define BLOCKS_PER_HWBANK (HWBANK_SIZE / CONFIG_FLASH_ERASE_SIZE)
 #define BLOCKS_HWBANK_MASK (BIT(BLOCKS_PER_HWBANK) - 1)
 
@@ -74,8 +74,8 @@ struct flash_wp_state {
 
 static inline int calculate_flash_timeout(void)
 {
-	return (FLASH_TIMEOUT_US *
-		(clock_get_freq() / SECOND) / CYCLE_PER_FLASH_LOOP);
+	return (FLASH_TIMEOUT_US * (clock_get_freq() / SECOND) /
+		CYCLE_PER_FLASH_LOOP);
 }
 
 static int unlock(int bank)
@@ -94,8 +94,8 @@ static int unlock(int bank)
 		ignore_bus_fault(0);
 	}
 
-	return (STM32_FLASH_CR(bank) & FLASH_CR_LOCK) ? EC_ERROR_UNKNOWN
-						      : EC_SUCCESS;
+	return (STM32_FLASH_CR(bank) & FLASH_CR_LOCK) ? EC_ERROR_UNKNOWN :
+							EC_SUCCESS;
 }
 
 static void lock(int bank)
@@ -123,15 +123,14 @@ static int unlock_optb(void)
 		ignore_bus_fault(0);
 	}
 
-	return flash_option_bytes_locked() ? EC_ERROR_UNKNOWN
-					   : EC_SUCCESS;
+	return flash_option_bytes_locked() ? EC_ERROR_UNKNOWN : EC_SUCCESS;
 }
 
 static int commit_optb(void)
 {
 	/* might use this before timer_init, cannot use get_time/usleep */
-	int timeout = (FLASH_OPT_PRG_TIMEOUT_US *
-		(clock_get_freq() / SECOND) / CYCLE_PER_FLASH_LOOP);
+	int timeout = (FLASH_OPT_PRG_TIMEOUT_US * (clock_get_freq() / SECOND) /
+		       CYCLE_PER_FLASH_LOOP);
 
 	STM32_FLASH_OPTCR(0) |= FLASH_OPTCR_OPTSTART;
 
@@ -149,12 +148,11 @@ static void protect_blocks(uint32_t blocks)
 	if (unlock_optb())
 		return;
 	STM32_FLASH_WPSN_PRG(0) &= ~(blocks & BLOCKS_HWBANK_MASK);
-	STM32_FLASH_WPSN_PRG(1) &= ~((blocks >> BLOCKS_PER_HWBANK)
-				& BLOCKS_HWBANK_MASK);
+	STM32_FLASH_WPSN_PRG(1) &=
+		~((blocks >> BLOCKS_PER_HWBANK) & BLOCKS_HWBANK_MASK);
 	commit_optb();
 }
 
-
 /*
  * Helper function definitions for consistency with F4 to enable flash
  * physical unitesting
@@ -226,7 +224,7 @@ bool flash_option_bytes_locked(void)
 	 * Always use bank 0 flash controller as there is only one option bytes
 	 * set for both banks. See http://b/181130245
 	 */
-	return  !!(STM32_FLASH_OPTCR(0) & FLASH_OPTCR_OPTLOCK);
+	return !!(STM32_FLASH_OPTCR(0) & FLASH_OPTCR_OPTLOCK);
 }
 
 bool flash_control_register_locked(void)
@@ -252,8 +250,8 @@ bool flash_control_register_locked(void)
 static int is_wp_enabled(void)
 {
 #ifdef CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE
-	return (STM32_FLASH_OPTSR_CUR(0) & FLASH_OPTSR_RDP_MASK)
-		!= FLASH_OPTSR_RDP_LEVEL_0;
+	return (STM32_FLASH_OPTSR_CUR(0) & FLASH_OPTSR_RDP_MASK) !=
+	       FLASH_OPTSR_RDP_LEVEL_0;
 #else
 	return !!(STM32_FLASH_OPTSR_CUR(0) & FLASH_OPTSR_RSS1);
 #endif
@@ -311,8 +309,8 @@ int crec_flash_physical_write(int offset, int size, const char *data)
 	STM32_FLASH_CCR(bank) = FLASH_CCR_ERR_MASK;
 
 	/* select write parallelism */
-	STM32_FLASH_CR(bank) = (STM32_FLASH_CR(bank) & ~FLASH_CR_PSIZE_MASK)
-			| DEFAULT_PSIZE;
+	STM32_FLASH_CR(bank) = (STM32_FLASH_CR(bank) & ~FLASH_CR_PSIZE_MASK) |
+			       DEFAULT_PSIZE;
 
 	/* set PG bit */
 	STM32_FLASH_CR(bank) |= FLASH_CR_PG;
@@ -326,18 +324,21 @@ int crec_flash_physical_write(int offset, int size, const char *data)
 
 		/* write a 256-bit flash word */
 		if (unaligned) {
-			for (i = 0; i < CONFIG_FLASH_WRITE_SIZE / 4; i++,
-								     data += 4)
-				*address++ = (uint32_t)data[0] | (data[1] << 8)
-					   | (data[2] << 16) | (data[3] << 24);
+			for (i = 0; i < CONFIG_FLASH_WRITE_SIZE / 4;
+			     i++, data += 4)
+				*address++ = (uint32_t)data[0] |
+					     (data[1] << 8) | (data[2] << 16) |
+					     (data[3] << 24);
 		} else {
 			for (i = 0; i < CONFIG_FLASH_WRITE_SIZE / 4; i++)
 				*address++ = *data32++;
 		}
 
 		/* Wait for writes to complete */
-		for (i = 0; (STM32_FLASH_SR(bank) &
-		     (FLASH_SR_WBNE | FLASH_SR_QW)) && (i < timeout); i++)
+		for (i = 0;
+		     (STM32_FLASH_SR(bank) & (FLASH_SR_WBNE | FLASH_SR_QW)) &&
+		     (i < timeout);
+		     i++)
 			;
 
 		if (STM32_FLASH_SR(bank) & (FLASH_SR_WBNE | FLASH_SR_QW)) {
@@ -386,16 +387,16 @@ int crec_flash_physical_erase(int offset, int size)
 	STM32_FLASH_CCR(bank) = FLASH_CCR_ERR_MASK;
 
 	/* select erase parallelism */
-	STM32_FLASH_CR(bank) = (STM32_FLASH_CR(bank) & ~FLASH_CR_PSIZE_MASK)
-			| DEFAULT_PSIZE;
+	STM32_FLASH_CR(bank) = (STM32_FLASH_CR(bank) & ~FLASH_CR_PSIZE_MASK) |
+			       DEFAULT_PSIZE;
 
 	for (sect = offset / CONFIG_FLASH_ERASE_SIZE; sect < last; sect++) {
 		timestamp_t deadline;
 
 		/* select page to erase and PER bit */
-		STM32_FLASH_CR(bank) = (STM32_FLASH_CR(bank)
-					& ~FLASH_CR_SNB_MASK)
-				| FLASH_CR_SER | FLASH_CR_SNB(sect);
+		STM32_FLASH_CR(bank) =
+			(STM32_FLASH_CR(bank) & ~FLASH_CR_SNB_MASK) |
+			FLASH_CR_SER | FLASH_CR_SNB(sect);
 
 		/* set STRT bit : start erase */
 		STM32_FLASH_CR(bank) |= FLASH_CR_STRT;
@@ -516,8 +517,7 @@ int crec_flash_physical_protect_at_boot(uint32_t new_flags)
 
 uint32_t crec_flash_physical_get_valid_flags(void)
 {
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-	       EC_FLASH_PROTECT_RO_NOW |
+	return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW |
 	       EC_FLASH_PROTECT_ALL_NOW;
 }
 
@@ -549,11 +549,11 @@ int crec_flash_physical_restore_state(void)
 	/*
 	 * If we have already jumped between images, an earlier image could
 	 * have applied write protection. We simply need to represent these
-         * irreversible flags to other components.
+	 * irreversible flags to other components.
 	 */
 	if (reset_flags & EC_RESET_FLAG_SYSJUMP) {
 		prev = (const struct flash_wp_state *)system_get_jump_tag(
-				FLASH_SYSJUMP_TAG, &version, &size);
+			FLASH_SYSJUMP_TAG, &version, &size);
 		if (prev && version == FLASH_HOOK_VERSION &&
 		    size == sizeof(*prev)) {
 			access_disabled = prev->access_disabled;
@@ -571,7 +571,7 @@ int crec_flash_pre_init(void)
 	uint32_t reset_flags = system_get_reset_flags();
 	uint32_t prot_flags = crec_flash_get_protect();
 	uint32_t unwanted_prot_flags = EC_FLASH_PROTECT_ALL_NOW |
-		EC_FLASH_PROTECT_ERROR_INCONSISTENT;
+				       EC_FLASH_PROTECT_ERROR_INCONSISTENT;
 
 	if (crec_flash_physical_restore_state())
 		return EC_SUCCESS;
diff --git a/chip/stm32/flash-stm32l.c b/chip/stm32/flash-stm32l.c
index f34200219a..b83f8961af 100644
--- a/chip/stm32/flash-stm32l.c
+++ b/chip/stm32/flash-stm32l.c
@@ -1,13 +1,15 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Flash memory module for Chrome EC */
 
+#include "builtin/assert.h"
 #include "clock.h"
 #include "console.h"
 #include "flash.h"
+#include "panic.h"
 #include "registers.h"
 #include "system.h"
 #include "task.h"
@@ -34,7 +36,8 @@ static void lock(void)
 	ignore_bus_fault(1);
 
 	STM32_FLASH_PECR = STM32_FLASH_PECR_PE_LOCK |
-		STM32_FLASH_PECR_PRG_LOCK | STM32_FLASH_PECR_OPT_LOCK;
+			   STM32_FLASH_PECR_PRG_LOCK |
+			   STM32_FLASH_PECR_OPT_LOCK;
 
 	ignore_bus_fault(0);
 }
@@ -105,8 +108,8 @@ static uint16_t read_optb(int offset)
  */
 static void write_optb(int offset, uint16_t value)
 {
-	REG32(STM32_OPTB_BASE + offset) =
-		(uint32_t)value | ((uint32_t)(~value) << 16);
+	REG32(STM32_OPTB_BASE + offset) = (uint32_t)value |
+					  ((uint32_t)(~value) << 16);
 }
 
 /**
@@ -115,7 +118,7 @@ static void write_optb(int offset, uint16_t value)
 static uint32_t read_optb_wrp(void)
 {
 	return read_optb(STM32_OPTB_WRP1L) |
-		((uint32_t)read_optb(STM32_OPTB_WRP1H) << 16);
+	       ((uint32_t)read_optb(STM32_OPTB_WRP1H) << 16);
 }
 
 /**
@@ -133,8 +136,8 @@ static void write_optb_wrp(uint32_t value)
  * This function lives in internal RAM, as we cannot read flash during writing.
  * You must not call other functions from this one or declare it static.
  */
-void  __attribute__((section(".iram.text")))
-	iram_flash_write(uint32_t *addr, uint32_t *data)
+void __attribute__((section(".iram.text")))
+iram_flash_write(uint32_t *addr, uint32_t *data)
 {
 	int i;
 
@@ -189,7 +192,7 @@ int crec_flash_physical_write(int offset, int size, const char *data)
 
 	/* Update flash timeout based on current clock speed */
 	flash_timeout_loop = FLASH_TIMEOUT_MS * (clock_get_freq() / MSEC) /
-		CYCLE_PER_FLASH_LOOP;
+			     CYCLE_PER_FLASH_LOOP;
 
 	while (size > 0) {
 		/*
@@ -204,7 +207,8 @@ int crec_flash_physical_write(int offset, int size, const char *data)
 
 			/* Wait for writes to complete */
 			for (i = 0; ((STM32_FLASH_SR & 9) != 8) &&
-				     (i < flash_timeout_loop); i++)
+				    (i < flash_timeout_loop);
+			     i++)
 				;
 
 			size -= sizeof(uint32_t);
@@ -257,13 +261,13 @@ int crec_flash_physical_erase(int offset, int size)
 
 	for (address = (uint32_t *)(CONFIG_PROGRAM_MEMORY_BASE + offset);
 	     size > 0; size -= CONFIG_FLASH_ERASE_SIZE,
-	     address += CONFIG_FLASH_ERASE_SIZE / sizeof(uint32_t)) {
+	    address += CONFIG_FLASH_ERASE_SIZE / sizeof(uint32_t)) {
 		timestamp_t deadline;
 
 		/* Do nothing if already erased */
 		if (crec_flash_is_erased((uint32_t)address -
-				    CONFIG_PROGRAM_MEMORY_BASE,
-				    CONFIG_FLASH_ERASE_SIZE))
+						 CONFIG_PROGRAM_MEMORY_BASE,
+					 CONFIG_FLASH_ERASE_SIZE))
 			continue;
 
 		/* Start erase */
@@ -336,7 +340,7 @@ int crec_flash_physical_protect_at_boot(uint32_t new_flags)
 		prot &= ~mask;
 
 	if (prot == read_optb_wrp())
-		return EC_SUCCESS;  /* No bits changed */
+		return EC_SUCCESS; /* No bits changed */
 
 	/* Unlock option bytes */
 	rv = unlock(STM32_FLASH_PECR_OPT_LOCK);
@@ -402,8 +406,7 @@ int crec_flash_physical_protect_now(int all)
 
 uint32_t crec_flash_physical_get_valid_flags(void)
 {
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-	       EC_FLASH_PROTECT_RO_NOW |
+	return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW |
 	       EC_FLASH_PROTECT_ALL_NOW;
 }
 
@@ -458,7 +461,7 @@ int crec_flash_pre_init(void)
 			 * Set it back to a good state and reboot.
 			 */
 			crec_flash_protect_at_boot(prot_flags &
-					EC_FLASH_PROTECT_RO_AT_BOOT);
+						   EC_FLASH_PROTECT_RO_AT_BOOT);
 			need_reset = 1;
 		}
 	} else if (prot_flags & (EC_FLASH_PROTECT_RO_NOW |
diff --git a/chip/stm32/fpu.c b/chip/stm32/fpu.c
index b61d0354f7..2bf0a0b803 100644
--- a/chip/stm32/fpu.c
+++ b/chip/stm32/fpu.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -38,5 +38,6 @@ __attribute__((naked)) void IRQ_HANDLER(STM32_IRQ_FPU)(void)
 		     "pop {r0, pc}\n");
 }
 const struct irq_priority __keep IRQ_PRIORITY(STM32_IRQ_FPU)
-	__attribute__((section(".rodata.irqprio")))
-		= {STM32_IRQ_FPU, 0}; /* highest priority */
+	__attribute__((section(".rodata.irqprio"))) = { STM32_IRQ_FPU,
+							0 }; /* highest priority
+							      */
diff --git a/chip/stm32/gpio-f0-l.c b/chip/stm32/gpio-f0-l.c
index 55628cb6d4..87ba4baa9f 100644
--- a/chip/stm32/gpio-f0-l.c
+++ b/chip/stm32/gpio-f0-l.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,6 +9,7 @@
  * These functions are shared by the STM32F0 and STM32L variants.
  */
 
+#include "builtin/assert.h"
 #include "common.h"
 #include "gpio_chip.h"
 #include "registers.h"
@@ -62,7 +63,6 @@ int gpio_get_flags_by_mask(uint32_t port, uint32_t mask)
 			flags |= GPIO_LOW;
 	}
 
-
 	if (STM32_EXTI_RTSR & mask)
 		flags |= GPIO_INT_F_RISING;
 	if (STM32_EXTI_RTSR & mask)
@@ -80,9 +80,9 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
 	/* Set up pullup / pulldown */
 	val = STM32_GPIO_PUPDR(port) & ~mask2;
 	if (flags & GPIO_PULL_UP)
-		val |= 0x55555555 & mask2;	/* Pull Up = 01 */
+		val |= 0x55555555 & mask2; /* Pull Up = 01 */
 	else if (flags & GPIO_PULL_DOWN)
-		val |= 0xaaaaaaaa & mask2;	/* Pull Down = 10 */
+		val |= 0xaaaaaaaa & mask2; /* Pull Down = 10 */
 	STM32_GPIO_PUPDR(port) = val;
 
 	/*
@@ -133,10 +133,10 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
 }
 
 void gpio_set_alternate_function(uint32_t port, uint32_t mask,
-				enum gpio_alternate_func func)
+				 enum gpio_alternate_func func)
 {
 	/* Ensure that the func parameter isn't overflowed */
-	BUILD_ASSERT((int) MODULE_COUNT <= (int) GPIO_ALT_FUNC_MAX);
+	BUILD_ASSERT((int)MODULE_COUNT <= (int)GPIO_ALT_FUNC_MAX);
 
 	int bit;
 	uint32_t half;
diff --git a/chip/stm32/gpio-stm32f0.c b/chip/stm32/gpio-stm32f0.c
index d7e7aa4391..8fbc77a85c 100644
--- a/chip/stm32/gpio-stm32f0.c
+++ b/chip/stm32/gpio-stm32f0.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/stm32/gpio-stm32f3.c b/chip/stm32/gpio-stm32f3.c
index f3a1b0068b..113aadc1e6 100644
--- a/chip/stm32/gpio-stm32f3.c
+++ b/chip/stm32/gpio-stm32f3.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/stm32/gpio-stm32f4.c b/chip/stm32/gpio-stm32f4.c
index 1ccdadd472..8e8658b7f9 100644
--- a/chip/stm32/gpio-stm32f4.c
+++ b/chip/stm32/gpio-stm32f4.c
@@ -1,10 +1,11 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* GPIO module for Chrome EC */
 
+#include "builtin/assert.h"
 #include "clock.h"
 #include "common.h"
 #include "gpio.h"
@@ -17,12 +18,12 @@
 int gpio_required_clocks(void)
 {
 	const int gpio_ports_used = (0
-#		define GPIO(name, pin, flags) pin
-#		define GPIO_INT(name, pin, flags, signal) pin
-#		define ALTERNATE(pinmask, function, module, flagz) pinmask
-#		define PIN(port, index) | STM32_RCC_AHB1ENR_GPIO_PORT ## port
-#		define PIN_MASK(port, mask) PIN(port, 0)
-#		include "gpio.wrap"
+#define GPIO(name, pin, flags) pin
+#define GPIO_INT(name, pin, flags, signal) pin
+#define ALTERNATE(pinmask, function, module, flagz) pinmask
+#define PIN(port, index) | STM32_RCC_AHB1ENR_GPIO_PORT##port
+#define PIN_MASK(port, mask) PIN(port, 0)
+#include "gpio.wrap"
 	);
 
 	/*
diff --git a/chip/stm32/gpio-stm32g4.c b/chip/stm32/gpio-stm32g4.c
index e77adc0ba6..8d1529a7ad 100644
--- a/chip/stm32/gpio-stm32g4.c
+++ b/chip/stm32/gpio-stm32g4.c
@@ -1,10 +1,11 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* GPIO module for Chrome EC */
 
+#include "builtin/assert.h"
 #include "clock.h"
 #include "common.h"
 #include "gpio.h"
@@ -17,12 +18,12 @@
 int gpio_required_clocks(void)
 {
 	const int gpio_ports_used = (0
-#		define GPIO(name, pin, flags) pin
-#		define GPIO_INT(name, pin, flags, signal) pin
-#		define ALTERNATE(pinmask, function, module, flagz) pinmask
-#		define PIN(port, index) | STM32_RCC_AHB2ENR_GPIO_PORT ## port
-#		define PIN_MASK(port, mask) PIN(port, 0)
-#		include "gpio.wrap"
+#define GPIO(name, pin, flags) pin
+#define GPIO_INT(name, pin, flags, signal) pin
+#define ALTERNATE(pinmask, function, module, flagz) pinmask
+#define PIN(port, index) | STM32_RCC_AHB2ENR_GPIO_PORT##port
+#define PIN_MASK(port, mask) PIN(port, 0)
+#include "gpio.wrap"
 	);
 
 	/*
diff --git a/chip/stm32/gpio-stm32h7.c b/chip/stm32/gpio-stm32h7.c
index 2cb723f076..66c696e836 100644
--- a/chip/stm32/gpio-stm32h7.c
+++ b/chip/stm32/gpio-stm32h7.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -33,7 +33,6 @@ static void gpio_init(void)
 	task_enable_irq(STM32_IRQ_EXTI4);
 	task_enable_irq(STM32_IRQ_EXTI9_5);
 	task_enable_irq(STM32_IRQ_EXTI15_10);
-
 }
 DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
 
diff --git a/chip/stm32/gpio-stm32l.c b/chip/stm32/gpio-stm32l.c
index 607a1a391f..920cb382b0 100644
--- a/chip/stm32/gpio-stm32l.c
+++ b/chip/stm32/gpio-stm32l.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/stm32/gpio-stm32l4.c b/chip/stm32/gpio-stm32l4.c
index f4ec6f4412..1ef83a188a 100644
--- a/chip/stm32/gpio-stm32l4.c
+++ b/chip/stm32/gpio-stm32l4.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -38,7 +38,6 @@ static void gpio_init(void)
 	task_enable_irq(STM32_IRQ_EXTI4);
 	task_enable_irq(STM32_IRQ_EXTI9_5);
 	task_enable_irq(STM32_IRQ_EXTI15_10);
-
 }
 DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
 
diff --git a/chip/stm32/gpio-stm32l5.c b/chip/stm32/gpio-stm32l5.c
index 9943edd55b..e714164650 100644
--- a/chip/stm32/gpio-stm32l5.c
+++ b/chip/stm32/gpio-stm32l5.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -45,7 +45,6 @@ static void gpio_init(void)
 	task_enable_irq(STM32_IRQ_EXTI13);
 	task_enable_irq(STM32_IRQ_EXTI14);
 	task_enable_irq(STM32_IRQ_EXTI15);
-
 }
 DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
 
diff --git a/chip/stm32/gpio.c b/chip/stm32/gpio.c
index 20d9223351..2ad9f99d79 100644
--- a/chip/stm32/gpio.c
+++ b/chip/stm32/gpio.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,7 @@
 #include "util.h"
 
 /* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
 /* For each EXTI bit, record which GPIO entry is using it */
 static uint8_t exti_events[16];
 
@@ -83,8 +83,8 @@ test_mockable int gpio_get_level(enum gpio_signal signal)
 
 void gpio_set_level(enum gpio_signal signal, int value)
 {
-	STM32_GPIO_BSRR(gpio_list[signal].port) =
-			gpio_list[signal].mask << (value ? 0 : 16);
+	STM32_GPIO_BSRR(gpio_list[signal].port) = gpio_list[signal].mask
+						  << (value ? 0 : 16);
 }
 
 int gpio_enable_interrupt(enum gpio_signal signal)
@@ -103,8 +103,8 @@ int gpio_enable_interrupt(enum gpio_signal signal)
 	g_old += exti_events[bit];
 
 	if ((exti_events[bit]) && (exti_events[bit] != signal)) {
-		CPRINTS("Overriding %s with %s on EXTI%d",
-			g_old->name, g->name, bit);
+		CPRINTS("Overriding %s with %s on EXTI%d", g_old->name, g->name,
+			bit);
 	}
 	exti_events[bit] = signal;
 
@@ -112,8 +112,9 @@ int gpio_enable_interrupt(enum gpio_signal signal)
 	shift = (bit % 4) * 4;
 	bank = (g->port - STM32_GPIOA_BASE) / 0x400;
 
-	STM32_SYSCFG_EXTICR(group) = (STM32_SYSCFG_EXTICR(group) &
-				      ~(0xF << shift)) | (bank << shift);
+	STM32_SYSCFG_EXTICR(group) =
+		(STM32_SYSCFG_EXTICR(group) & ~(0xF << shift)) |
+		(bank << shift);
 	STM32_EXTI_IMR |= g->mask;
 
 	return EC_SUCCESS;
diff --git a/chip/stm32/gpio_chip.h b/chip/stm32/gpio_chip.h
index b440cf5041..0a52fe9191 100644
--- a/chip/stm32/gpio_chip.h
+++ b/chip/stm32/gpio_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,4 +20,4 @@ void gpio_enable_clocks(void);
 int gpio_required_clocks(void);
 
 void __keep gpio_interrupt(void);
-#endif  /* __CROS_EC_CHIP_STM32_GPIO_CHIP_H */
+#endif /* __CROS_EC_CHIP_STM32_GPIO_CHIP_H */
diff --git a/chip/stm32/host_command_common.c b/chip/stm32/host_command_common.c
index b39a298c64..10653a0711 100644
--- a/chip/stm32/host_command_common.c
+++ b/chip/stm32/host_command_common.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,8 +17,8 @@ static enum fp_transport_type curr_transport_type = FP_TRANSPORT_TYPE_UNKNOWN;
 /*
  * Get protocol information
  */
-static enum ec_status host_command_protocol_info(struct host_cmd_handler_args
-						 *args)
+static enum ec_status
+host_command_protocol_info(struct host_cmd_handler_args *args)
 {
 	enum ec_status ret_status = EC_RES_INVALID_COMMAND;
 
@@ -39,8 +39,7 @@ static enum ec_status host_command_protocol_info(struct host_cmd_handler_args
 
 	return ret_status;
 }
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO,
-		     host_command_protocol_info,
+DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, host_command_protocol_info,
 		     EC_VER_MASK(0));
 
 #endif /* CONFIG_I2C_PERIPHERAL */
diff --git a/chip/stm32/hwtimer.c b/chip/stm32/hwtimer.c
index 8748b7f870..3521347f3f 100644
--- a/chip/stm32/hwtimer.c
+++ b/chip/stm32/hwtimer.c
@@ -1,10 +1,11 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Hardware timers driver */
 
+#include "builtin/assert.h"
 #include "clock.h"
 #include "clock-f.h"
 #include "common.h"
@@ -33,20 +34,20 @@
  *     --------------------
  *     ts =  0  1  2  3
  */
-#define STM32_TIM_TS_SECONDARY_1_PRIMARY_15  0
-#define STM32_TIM_TS_SECONDARY_1_PRIMARY_2   1
-#define STM32_TIM_TS_SECONDARY_1_PRIMARY_3   2
-#define STM32_TIM_TS_SECONDARY_1_PRIMARY_17  3
-#define STM32_TIM_TS_SECONDARY_2_PRIMARY_1   0
-#define STM32_TIM_TS_SECONDARY_2_PRIMARY_15  1
-#define STM32_TIM_TS_SECONDARY_2_PRIMARY_3   2
-#define STM32_TIM_TS_SECONDARY_2_PRIMARY_14  3
-#define STM32_TIM_TS_SECONDARY_3_PRIMARY_1   0
-#define STM32_TIM_TS_SECONDARY_3_PRIMARY_2   1
-#define STM32_TIM_TS_SECONDARY_3_PRIMARY_15  2
-#define STM32_TIM_TS_SECONDARY_3_PRIMARY_14  3
-#define STM32_TIM_TS_SECONDARY_15_PRIMARY_2  0
-#define STM32_TIM_TS_SECONDARY_15_PRIMARY_3  1
+#define STM32_TIM_TS_SECONDARY_1_PRIMARY_15 0
+#define STM32_TIM_TS_SECONDARY_1_PRIMARY_2 1
+#define STM32_TIM_TS_SECONDARY_1_PRIMARY_3 2
+#define STM32_TIM_TS_SECONDARY_1_PRIMARY_17 3
+#define STM32_TIM_TS_SECONDARY_2_PRIMARY_1 0
+#define STM32_TIM_TS_SECONDARY_2_PRIMARY_15 1
+#define STM32_TIM_TS_SECONDARY_2_PRIMARY_3 2
+#define STM32_TIM_TS_SECONDARY_2_PRIMARY_14 3
+#define STM32_TIM_TS_SECONDARY_3_PRIMARY_1 0
+#define STM32_TIM_TS_SECONDARY_3_PRIMARY_2 1
+#define STM32_TIM_TS_SECONDARY_3_PRIMARY_15 2
+#define STM32_TIM_TS_SECONDARY_3_PRIMARY_14 3
+#define STM32_TIM_TS_SECONDARY_15_PRIMARY_2 0
+#define STM32_TIM_TS_SECONDARY_15_PRIMARY_3 1
 #define STM32_TIM_TS_SECONDARY_15_PRIMARY_16 2
 #define STM32_TIM_TS_SECONDARY_15_PRIMARY_17 3
 #elif defined(CHIP_FAMILY_STM32F3)
@@ -61,28 +62,28 @@
  *    ---------------------
  *     ts =  0  1  2  3
  */
-#define STM32_TIM_TS_SECONDARY_2_PRIMARY_19  0
-#define STM32_TIM_TS_SECONDARY_2_PRIMARY_15  1
-#define STM32_TIM_TS_SECONDARY_2_PRIMARY_3   2
-#define STM32_TIM_TS_SECONDARY_2_PRIMARY_14  3
-#define STM32_TIM_TS_SECONDARY_3_PRIMARY_19  0
-#define STM32_TIM_TS_SECONDARY_3_PRIMARY_2   1
-#define STM32_TIM_TS_SECONDARY_3_PRIMARY_5   2
-#define STM32_TIM_TS_SECONDARY_3_PRIMARY_14  3
-#define STM32_TIM_TS_SECONDARY_4_PRIMARY_19  0
-#define STM32_TIM_TS_SECONDARY_4_PRIMARY_2   1
-#define STM32_TIM_TS_SECONDARY_4_PRIMARY_3   2
-#define STM32_TIM_TS_SECONDARY_4_PRIMARY_15  3
-#define STM32_TIM_TS_SECONDARY_5_PRIMARY_2   0
-#define STM32_TIM_TS_SECONDARY_5_PRIMARY_3   1
-#define STM32_TIM_TS_SECONDARY_5_PRIMARY_4   2
-#define STM32_TIM_TS_SECONDARY_5_PRIMARY_15  3
-#define STM32_TIM_TS_SECONDARY_12_PRIMARY_4  0
-#define STM32_TIM_TS_SECONDARY_12_PRIMARY_5  1
+#define STM32_TIM_TS_SECONDARY_2_PRIMARY_19 0
+#define STM32_TIM_TS_SECONDARY_2_PRIMARY_15 1
+#define STM32_TIM_TS_SECONDARY_2_PRIMARY_3 2
+#define STM32_TIM_TS_SECONDARY_2_PRIMARY_14 3
+#define STM32_TIM_TS_SECONDARY_3_PRIMARY_19 0
+#define STM32_TIM_TS_SECONDARY_3_PRIMARY_2 1
+#define STM32_TIM_TS_SECONDARY_3_PRIMARY_5 2
+#define STM32_TIM_TS_SECONDARY_3_PRIMARY_14 3
+#define STM32_TIM_TS_SECONDARY_4_PRIMARY_19 0
+#define STM32_TIM_TS_SECONDARY_4_PRIMARY_2 1
+#define STM32_TIM_TS_SECONDARY_4_PRIMARY_3 2
+#define STM32_TIM_TS_SECONDARY_4_PRIMARY_15 3
+#define STM32_TIM_TS_SECONDARY_5_PRIMARY_2 0
+#define STM32_TIM_TS_SECONDARY_5_PRIMARY_3 1
+#define STM32_TIM_TS_SECONDARY_5_PRIMARY_4 2
+#define STM32_TIM_TS_SECONDARY_5_PRIMARY_15 3
+#define STM32_TIM_TS_SECONDARY_12_PRIMARY_4 0
+#define STM32_TIM_TS_SECONDARY_12_PRIMARY_5 1
 #define STM32_TIM_TS_SECONDARY_12_PRIMARY_13 2
 #define STM32_TIM_TS_SECONDARY_12_PRIMARY_14 3
-#define STM32_TIM_TS_SECONDARY_19_PRIMARY_2  0
-#define STM32_TIM_TS_SECONDARY_19_PRIMARY_3  1
+#define STM32_TIM_TS_SECONDARY_19_PRIMARY_2 0
+#define STM32_TIM_TS_SECONDARY_19_PRIMARY_3 1
 #define STM32_TIM_TS_SECONDARY_19_PRIMARY_15 2
 #define STM32_TIM_TS_SECONDARY_19_PRIMARY_16 3
 #else /* !CHIP_FAMILY_STM32F0 && !CHIP_FAMILY_STM32F3 */
@@ -97,23 +98,23 @@
  *     ts =  0  1  2  3
  */
 #define STM32_TIM_TS_SECONDARY_1_PRIMARY_15 0
-#define STM32_TIM_TS_SECONDARY_1_PRIMARY_2  1
-#define STM32_TIM_TS_SECONDARY_1_PRIMARY_3  2
-#define STM32_TIM_TS_SECONDARY_1_PRIMARY_4  3
-#define STM32_TIM_TS_SECONDARY_2_PRIMARY_9  0
+#define STM32_TIM_TS_SECONDARY_1_PRIMARY_2 1
+#define STM32_TIM_TS_SECONDARY_1_PRIMARY_3 2
+#define STM32_TIM_TS_SECONDARY_1_PRIMARY_4 3
+#define STM32_TIM_TS_SECONDARY_2_PRIMARY_9 0
 #define STM32_TIM_TS_SECONDARY_2_PRIMARY_10 1
-#define STM32_TIM_TS_SECONDARY_2_PRIMARY_3  2
-#define STM32_TIM_TS_SECONDARY_2_PRIMARY_4  3
-#define STM32_TIM_TS_SECONDARY_3_PRIMARY_9  0
-#define STM32_TIM_TS_SECONDARY_3_PRIMARY_2  1
+#define STM32_TIM_TS_SECONDARY_2_PRIMARY_3 2
+#define STM32_TIM_TS_SECONDARY_2_PRIMARY_4 3
+#define STM32_TIM_TS_SECONDARY_3_PRIMARY_9 0
+#define STM32_TIM_TS_SECONDARY_3_PRIMARY_2 1
 #define STM32_TIM_TS_SECONDARY_3_PRIMARY_11 2
-#define STM32_TIM_TS_SECONDARY_3_PRIMARY_4  3
+#define STM32_TIM_TS_SECONDARY_3_PRIMARY_4 3
 #define STM32_TIM_TS_SECONDARY_4_PRIMARY_10 0
-#define STM32_TIM_TS_SECONDARY_4_PRIMARY_2  1
-#define STM32_TIM_TS_SECONDARY_4_PRIMARY_3  2
-#define STM32_TIM_TS_SECONDARY_4_PRIMARY_9  3
-#define STM32_TIM_TS_SECONDARY_9_PRIMARY_2  0
-#define STM32_TIM_TS_SECONDARY_9_PRIMARY_3  1
+#define STM32_TIM_TS_SECONDARY_4_PRIMARY_2 1
+#define STM32_TIM_TS_SECONDARY_4_PRIMARY_3 2
+#define STM32_TIM_TS_SECONDARY_4_PRIMARY_9 3
+#define STM32_TIM_TS_SECONDARY_9_PRIMARY_2 0
+#define STM32_TIM_TS_SECONDARY_9_PRIMARY_3 1
 #define STM32_TIM_TS_SECONDARY_9_PRIMARY_10 2
 #define STM32_TIM_TS_SECONDARY_9_PRIMARY_11 3
 #endif /* !CHIP_FAMILY_STM32F0 */
@@ -126,7 +127,7 @@
  */
 #define IRQ_MSB IRQ_TIM(TIM_CLOCK_MSB)
 #define IRQ_LSB IRQ_TIM(TIM_CLOCK_LSB)
-#define IRQ_WD  IRQ_TIM(TIM_WATCHDOG)
+#define IRQ_WD IRQ_TIM(TIM_WATCHDOG)
 
 /* TIM1 has fancy names for its IRQs; remap count-up IRQ for the macro above */
 #if defined TIM_WATCHDOG && (TIM_WATCHDOG == 1)
@@ -360,8 +361,8 @@ int __hw_clock_source_init(uint32_t start_t)
 	STM32_TIM_CR2(TIM_CLOCK_MSB) = 0x0000;
 	STM32_TIM_CR2(TIM_CLOCK_LSB) = 0x0020;
 
-	STM32_TIM_SMCR(TIM_CLOCK_MSB) = 0x0007 |
-		(TSMAP(TIM_CLOCK_MSB, TIM_CLOCK_LSB) << 4);
+	STM32_TIM_SMCR(TIM_CLOCK_MSB) =
+		0x0007 | (TSMAP(TIM_CLOCK_MSB, TIM_CLOCK_LSB) << 4);
 	STM32_TIM_SMCR(TIM_CLOCK_LSB) = 0x0000;
 
 	/* Auto-reload value : 16-bit free-running counters */
@@ -419,9 +420,12 @@ void IRQ_HANDLER(IRQ_WD)(void)
 		     "pop {r0,pc}\n");
 }
 const struct irq_priority __keep IRQ_PRIORITY(IRQ_WD)
-	__attribute__((section(".rodata.irqprio")))
-		= {IRQ_WD, 0}; /* put the watchdog at the highest
-					    priority */
+	__attribute__((section(".rodata.irqprio"))) = {
+		IRQ_WD, 0
+	}; /* put the watchdog
+	      at the highest
+			priority
+	    */
 
 void hwtimer_setup_watchdog(void)
 {
@@ -474,4 +478,4 @@ void hwtimer_reset_watchdog(void)
 	timer->cnt = timer->arr;
 }
 
-#endif  /* defined(CONFIG_WATCHDOG_HELP) */
+#endif /* defined(CONFIG_WATCHDOG_HELP) */
diff --git a/chip/stm32/hwtimer32.c b/chip/stm32/hwtimer32.c
index f64eab989a..0448d34e4b 100644
--- a/chip/stm32/hwtimer32.c
+++ b/chip/stm32/hwtimer32.c
@@ -1,10 +1,11 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Hardware 32-bit timer driver */
 
+#include "builtin/assert.h"
 #include "clock.h"
 #include "clock-f.h"
 #include "common.h"
@@ -115,7 +116,7 @@ void __hw_timer_enable_clock(int n, int enable)
 #endif
 
 #if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \
-defined(CHIP_FAMILY_STM32H7)
+	defined(CHIP_FAMILY_STM32H7)
 	if (n == 14) {
 		reg = &STM32_RCC_APB1ENR;
 		mask = STM32_RCC_PB1_TIM14;
@@ -157,7 +158,7 @@ defined(CHIP_FAMILY_STM32H7)
 		reg = &STM32_RCC_APB2ENR;
 		mask = (n == 1)	 ? STM32_RCC_APB2ENR_TIM1EN :
 		       (n == 15) ? STM32_RCC_APB2ENR_TIM15EN :
-					 STM32_RCC_APB2ENR_TIM16EN;
+				   STM32_RCC_APB2ENR_TIM16EN;
 	}
 #else
 	if (n >= 2 && n <= 7) {
@@ -213,12 +214,12 @@ static void update_prescaler(void)
 #ifdef CONFIG_WATCHDOG_HELP
 	/* Watchdog timer runs at 1KHz */
 	STM32_TIM_PSC(TIM_WATCHDOG) =
-		(clock_get_timer_freq()  / SECOND * MSEC)- 1;
-#endif  /* CONFIG_WATCHDOG_HELP */
+		(clock_get_timer_freq() / SECOND * MSEC) - 1;
+#endif /* CONFIG_WATCHDOG_HELP */
 }
 DECLARE_HOOK(HOOK_FREQ_CHANGE, update_prescaler, HOOK_PRIO_DEFAULT);
 #endif /* CHIP_FAMILY_STM32L  || CHIP_FAMILY_STM32L4 || */
-	/*  CHIP_FAMILY_STM32F4 || CHIP_FAMILY_STM32H7 */
+/*  CHIP_FAMILY_STM32F4 || CHIP_FAMILY_STM32H7 */
 
 int __hw_clock_source_init(uint32_t start_t)
 {
@@ -285,9 +286,12 @@ void IRQ_HANDLER(IRQ_WD)(void)
 		     "pop {r0,pc}\n");
 }
 const struct irq_priority __keep IRQ_PRIORITY(IRQ_WD)
-	__attribute__((section(".rodata.irqprio")))
-		= {IRQ_WD, 0}; /* put the watchdog at the highest
-					    priority */
+	__attribute__((section(".rodata.irqprio"))) = {
+		IRQ_WD, 0
+	}; /* put the watchdog
+	      at the highest
+			priority
+	    */
 
 void hwtimer_setup_watchdog(void)
 {
@@ -320,8 +324,7 @@ void hwtimer_setup_watchdog(void)
 		STM32_TIM_ARR(TIM_WATCHDOG) = CONFIG_AUX_TIMER_PERIOD_MS;
 
 		/* Update prescaler: watchdog timer runs at 1KHz */
-		STM32_TIM_PSC(TIM_WATCHDOG) =
-			(freq / SECOND * MSEC) - 1;
+		STM32_TIM_PSC(TIM_WATCHDOG) = (freq / SECOND * MSEC) - 1;
 	}
 #ifdef CHIP_FAMILY_STM32L4
 	else {
@@ -351,4 +354,4 @@ void hwtimer_reset_watchdog(void)
 	STM32_TIM_CNT(TIM_WATCHDOG) = 0x0000;
 }
 
-#endif  /* CONFIG_WATCHDOG_HELP */
+#endif /* CONFIG_WATCHDOG_HELP */
diff --git a/chip/stm32/i2c-stm32f0.c b/chip/stm32/i2c-stm32f0.c
index f78a450a4e..acd4d3aca6 100644
--- a/chip/stm32/i2c-stm32f0.c
+++ b/chip/stm32/i2c-stm32f0.c
@@ -1,8 +1,9 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "builtin/assert.h"
 #include "chipset.h"
 #include "clock.h"
 #include "common.h"
@@ -23,10 +24,10 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
 
 /* Transmit timeout in microseconds */
-#define I2C_TX_TIMEOUT_CONTROLLER	(10 * MSEC)
+#define I2C_TX_TIMEOUT_CONTROLLER (10 * MSEC)
 
 #ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
 #if (I2C_PORT_EC == STM32_I2C1_PORT)
@@ -36,11 +37,10 @@
 #endif
 #endif
 
-
 /* I2C port state data */
 struct i2c_port_data {
-	uint32_t timeout_us;    /* Transaction timeout, or 0 to use default */
-	enum i2c_freq freq;	/* Port clock speed */
+	uint32_t timeout_us; /* Transaction timeout, or 0 to use default */
+	enum i2c_freq freq; /* Port clock speed */
 };
 static struct i2c_port_data pdata[I2C_PORT_COUNT];
 
@@ -52,8 +52,8 @@ void i2c_set_timeout(int port, uint32_t timeout)
 /* timingr register values for supported input clks / i2c clk rates */
 static const uint32_t busyloop_us[I2C_FREQ_COUNT] = {
 	[I2C_FREQ_1000KHZ] = 16, /* Enough for 2 bytes */
-	[I2C_FREQ_400KHZ] = 40,  /* Enough for 2 bytes */
-	[I2C_FREQ_100KHZ] = 0,   /* No busy looping at 100kHz (bus is slow) */
+	[I2C_FREQ_400KHZ] = 40, /* Enough for 2 bytes */
+	[I2C_FREQ_100KHZ] = 0, /* No busy looping at 100kHz (bus is slow) */
 };
 
 /**
@@ -72,7 +72,7 @@ static int wait_isr(int port, int mask)
 
 		/* Check for errors */
 		if (isr & (STM32_I2C_ISR_ARLO | STM32_I2C_ISR_BERR |
-			STM32_I2C_ISR_NACK))
+			   STM32_I2C_ISR_NACK))
 			return EC_ERROR_UNKNOWN;
 
 		/* Check for desired mask */
@@ -118,8 +118,7 @@ int chip_i2c_set_freq(int port, enum i2c_freq freq)
 	enum stm32_i2c_clk_src src = I2C_CLK_SRC_48MHZ;
 
 #if defined(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) && \
-	defined(CONFIG_LOW_POWER_IDLE) && \
-	(I2C_PORT_EC == STM32_I2C1_PORT)
+	defined(CONFIG_LOW_POWER_IDLE) && (I2C_PORT_EC == STM32_I2C1_PORT)
 	if (port == STM32_I2C1_PORT) {
 		/*
 		 * Use HSI (8MHz) for i2c clock. This allows smooth wakeup
@@ -165,8 +164,7 @@ static int i2c_init_port(const struct i2c_port_t *p)
 
 	if (port == STM32_I2C1_PORT) {
 #if defined(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) && \
-	defined(CONFIG_LOW_POWER_IDLE) && \
-	(I2C_PORT_EC == STM32_I2C1_PORT)
+	defined(CONFIG_LOW_POWER_IDLE) && (I2C_PORT_EC == STM32_I2C1_PORT)
 		/*
 		 * Use HSI (8MHz) for i2c clock. This allows smooth wakeup
 		 * from STOP mode since HSI is only clock running immediately
@@ -218,7 +216,7 @@ static int i2c_init_port(const struct i2c_port_t *p)
  */
 static uint8_t host_buffer_padded[I2C_MAX_HOST_PACKET_SIZE + 4 +
 				  CONFIG_I2C_EXTRA_PACKET_SIZE] __aligned(4);
-static uint8_t * const host_buffer = host_buffer_padded + 2;
+static uint8_t *const host_buffer = host_buffer_padded + 2;
 static uint8_t params_copy[I2C_MAX_HOST_PACKET_SIZE] __aligned(4);
 static int host_i2c_resp_port;
 static int tx_pending;
@@ -330,7 +328,7 @@ static void i2c_event_handler(int port)
 
 		/* Clear error status bits */
 		STM32_I2C_ICR(port) |= STM32_I2C_ICR_BERRCF |
-				STM32_I2C_ICR_ARLOCF;
+				       STM32_I2C_ICR_ARLOCF;
 	}
 
 	/* Transfer matched our peripheral address */
@@ -439,16 +437,18 @@ static void i2c_event_handler(int port)
 		}
 	}
 }
-static void i2c2_event_interrupt(void) { i2c_event_handler(I2C_PORT_EC); }
+static void i2c2_event_interrupt(void)
+{
+	i2c_event_handler(I2C_PORT_EC);
+}
 DECLARE_IRQ(IRQ_PERIPHERAL, i2c2_event_interrupt, 2);
 #endif
 
 /*****************************************************************************/
 /* Interface */
 
-int chip_i2c_xfer(const int port, const uint16_t addr_flags,
-		  const uint8_t *out, int out_bytes,
-		  uint8_t *in, int in_bytes, int flags)
+int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out,
+		  int out_bytes, uint8_t *in, int in_bytes, int flags)
 {
 	int addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1;
 	int rv = EC_SUCCESS;
@@ -495,13 +495,13 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags,
 		 * if we are not stopping, set RELOAD bit so that we can load
 		 * NBYTES again. if we are starting, then set START bit.
 		 */
-		STM32_I2C_CR2(port) =  ((out_bytes & 0xFF) << 16)
-			| addr_8bit
-			| ((in_bytes == 0 && xfer_stop) ?
-				STM32_I2C_CR2_AUTOEND : 0)
-			| ((in_bytes == 0 && !xfer_stop) ?
-				STM32_I2C_CR2_RELOAD : 0)
-			| (xfer_start ? STM32_I2C_CR2_START : 0);
+		STM32_I2C_CR2(port) =
+			((out_bytes & 0xFF) << 16) | addr_8bit |
+			((in_bytes == 0 && xfer_stop) ? STM32_I2C_CR2_AUTOEND :
+							0) |
+			((in_bytes == 0 && !xfer_stop) ? STM32_I2C_CR2_RELOAD :
+							 0) |
+			(xfer_start ? STM32_I2C_CR2_START : 0);
 
 		for (i = 0; i < out_bytes; i++) {
 			rv = wait_isr(port, STM32_I2C_ISR_TXIS);
@@ -524,11 +524,11 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags,
 		 * NBYTES again. if we were just transmitting, we need to
 		 * set START bit to send (re)start and begin read transaction.
 		 */
-		STM32_I2C_CR2(port) = ((in_bytes & 0xFF) << 16)
-			| STM32_I2C_CR2_RD_WRN | addr_8bit
-			| (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0)
-			| (!xfer_stop ? STM32_I2C_CR2_RELOAD : 0)
-			| (out_bytes || xfer_start ? STM32_I2C_CR2_START : 0);
+		STM32_I2C_CR2(port) =
+			((in_bytes & 0xFF) << 16) | STM32_I2C_CR2_RD_WRN |
+			addr_8bit | (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0) |
+			(!xfer_stop ? STM32_I2C_CR2_RELOAD : 0) |
+			(out_bytes || xfer_start ? STM32_I2C_CR2_START : 0);
 
 		for (i = 0; i < in_bytes; i++) {
 			/* Wait for receive buffer not empty */
@@ -614,7 +614,7 @@ int i2c_raw_get_sda(int port)
 int i2c_get_line_levels(int port)
 {
 	return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) |
-		(i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
+	       (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
 }
 
 void i2c_init(void)
@@ -626,9 +626,10 @@ void i2c_init(void)
 		i2c_init_port(p);
 
 #ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
-	STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_RXIE | STM32_I2C_CR1_ERRIE
-			| STM32_I2C_CR1_ADDRIE | STM32_I2C_CR1_STOPIE
-			| STM32_I2C_CR1_NACKIE;
+	STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_RXIE | STM32_I2C_CR1_ERRIE |
+				      STM32_I2C_CR1_ADDRIE |
+				      STM32_I2C_CR1_STOPIE |
+				      STM32_I2C_CR1_NACKIE;
 #if defined(CONFIG_LOW_POWER_IDLE) && (I2C_PORT_EC == STM32_I2C1_PORT)
 	/*
 	 * If using low power idle and EC port is I2C1, then set I2C1 to wake
@@ -637,15 +638,16 @@ void i2c_init(void)
 	 */
 	STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_WUPEN;
 #endif
-	STM32_I2C_OAR1(I2C_PORT_EC) = 0x8000
-		| (I2C_STRIP_FLAGS(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) << 1);
+	STM32_I2C_OAR1(I2C_PORT_EC) =
+		0x8000 | (I2C_STRIP_FLAGS(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) << 1);
 #ifdef TCPCI_I2C_PERIPHERAL
 	/*
 	 * Configure TCPC address with OA2[1] masked so that we respond
 	 * to CONFIG_TCPC_I2C_BASE_ADDR and CONFIG_TCPC_I2C_BASE_ADDR + 2.
 	 */
-	STM32_I2C_OAR2(I2C_PORT_EC) = 0x8100
-		| (I2C_STRIP_FLAGS(CONFIG_TCPC_I2C_BASE_ADDR_FLAGS) << 1);
+	STM32_I2C_OAR2(I2C_PORT_EC) =
+		0x8100 |
+		(I2C_STRIP_FLAGS(CONFIG_TCPC_I2C_BASE_ADDR_FLAGS) << 1);
 #endif
 	task_enable_irq(IRQ_PERIPHERAL);
 #endif
diff --git a/chip/stm32/i2c-stm32f3.c b/chip/stm32/i2c-stm32f3.c
index ce8523ea90..acd4d3aca6 120000..100644
--- a/chip/stm32/i2c-stm32f3.c
+++ b/chip/stm32/i2c-stm32f3.c
@@ -1 +1,654 @@
-i2c-stm32f0.c
\ No newline at end of file
+/* Copyright 2013 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "builtin/assert.h"
+#include "chipset.h"
+#include "clock.h"
+#include "common.h"
+#include "console.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "hwtimer.h"
+#include "i2c.h"
+#include "i2c_private.h"
+#include "registers.h"
+#include "system.h"
+#include "task.h"
+#include "timer.h"
+#include "usb_pd_tcpc.h"
+#include "usb_pd_tcpm.h"
+#include "util.h"
+
+/* Console output macros */
+#define CPUTS(outstr) cputs(CC_I2C, outstr)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
+
+/* Transmit timeout in microseconds */
+#define I2C_TX_TIMEOUT_CONTROLLER (10 * MSEC)
+
+#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
+#if (I2C_PORT_EC == STM32_I2C1_PORT)
+#define IRQ_PERIPHERAL STM32_IRQ_I2C1
+#else
+#define IRQ_PERIPHERAL STM32_IRQ_I2C2
+#endif
+#endif
+
+/* I2C port state data */
+struct i2c_port_data {
+	uint32_t timeout_us; /* Transaction timeout, or 0 to use default */
+	enum i2c_freq freq; /* Port clock speed */
+};
+static struct i2c_port_data pdata[I2C_PORT_COUNT];
+
+void i2c_set_timeout(int port, uint32_t timeout)
+{
+	pdata[port].timeout_us = timeout ? timeout : I2C_TX_TIMEOUT_CONTROLLER;
+}
+
+/* timingr register values for supported input clks / i2c clk rates */
+static const uint32_t busyloop_us[I2C_FREQ_COUNT] = {
+	[I2C_FREQ_1000KHZ] = 16, /* Enough for 2 bytes */
+	[I2C_FREQ_400KHZ] = 40, /* Enough for 2 bytes */
+	[I2C_FREQ_100KHZ] = 0, /* No busy looping at 100kHz (bus is slow) */
+};
+
+/**
+ * Wait for ISR register to contain the specified mask.
+ *
+ * Returns EC_SUCCESS, EC_ERROR_TIMEOUT if timed out waiting, or
+ * EC_ERROR_UNKNOWN if an error bit appeared in the status register.
+ */
+static int wait_isr(int port, int mask)
+{
+	uint32_t start = __hw_clock_source_read();
+	uint32_t delta = 0;
+
+	do {
+		int isr = STM32_I2C_ISR(port);
+
+		/* Check for errors */
+		if (isr & (STM32_I2C_ISR_ARLO | STM32_I2C_ISR_BERR |
+			   STM32_I2C_ISR_NACK))
+			return EC_ERROR_UNKNOWN;
+
+		/* Check for desired mask */
+		if ((isr & mask) == mask)
+			return EC_SUCCESS;
+
+		delta = __hw_clock_source_read() - start;
+
+		/**
+		 * Depending on the bus speed, busy loop for a while before
+		 * sleeping and letting other things run.
+		 */
+		if (delta >= busyloop_us[pdata[port].freq])
+			usleep(100);
+	} while (delta < pdata[port].timeout_us);
+
+	return EC_ERROR_TIMEOUT;
+}
+
+/* Supported i2c input clocks */
+enum stm32_i2c_clk_src {
+	I2C_CLK_SRC_48MHZ = 0,
+	I2C_CLK_SRC_8MHZ = 1,
+	I2C_CLK_SRC_COUNT,
+};
+
+/* timingr register values for supported input clks / i2c clk rates */
+static const uint32_t timingr_regs[I2C_CLK_SRC_COUNT][I2C_FREQ_COUNT] = {
+	[I2C_CLK_SRC_48MHZ] = {
+		[I2C_FREQ_1000KHZ] = 0x50100103,
+		[I2C_FREQ_400KHZ] = 0x50330609,
+		[I2C_FREQ_100KHZ] = 0xB0421214,
+	},
+	[I2C_CLK_SRC_8MHZ] = {
+		[I2C_FREQ_1000KHZ] = 0x00100306,
+		[I2C_FREQ_400KHZ] = 0x00310309,
+		[I2C_FREQ_100KHZ] = 0x10420f13,
+	},
+};
+
+int chip_i2c_set_freq(int port, enum i2c_freq freq)
+{
+	enum stm32_i2c_clk_src src = I2C_CLK_SRC_48MHZ;
+
+#if defined(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) && \
+	defined(CONFIG_LOW_POWER_IDLE) && (I2C_PORT_EC == STM32_I2C1_PORT)
+	if (port == STM32_I2C1_PORT) {
+		/*
+		 * Use HSI (8MHz) for i2c clock. This allows smooth wakeup
+		 * from STOP mode since HSI is only clock running immediately
+		 * upon exit from STOP mode.
+		 */
+		src = I2C_CLK_SRC_8MHZ;
+	}
+#endif
+
+	/* Disable port */
+	STM32_I2C_CR1(port) = 0;
+	STM32_I2C_CR2(port) = 0;
+	/* Set clock frequency */
+	STM32_I2C_TIMINGR(port) = timingr_regs[src][freq];
+	/* Enable port */
+	STM32_I2C_CR1(port) = STM32_I2C_CR1_PE;
+
+	pdata[port].freq = freq;
+
+	return EC_SUCCESS;
+}
+
+enum i2c_freq chip_i2c_get_freq(int port)
+{
+	return pdata[port].freq;
+}
+
+/**
+ * Initialize on the specified I2C port.
+ *
+ * @param p		the I2c port
+ */
+static int i2c_init_port(const struct i2c_port_t *p)
+{
+	int port = p->port;
+	int ret = EC_SUCCESS;
+	enum i2c_freq freq;
+
+	/* Enable clocks to I2C modules if necessary */
+	if (!(STM32_RCC_APB1ENR & (1 << (21 + port))))
+		STM32_RCC_APB1ENR |= 1 << (21 + port);
+
+	if (port == STM32_I2C1_PORT) {
+#if defined(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) && \
+	defined(CONFIG_LOW_POWER_IDLE) && (I2C_PORT_EC == STM32_I2C1_PORT)
+		/*
+		 * Use HSI (8MHz) for i2c clock. This allows smooth wakeup
+		 * from STOP mode since HSI is only clock running immediately
+		 * upon exit from STOP mode.
+		 */
+		STM32_RCC_CFGR3 &= ~0x10;
+#else
+		/* Use SYSCLK for i2c clock. */
+		STM32_RCC_CFGR3 |= 0x10;
+#endif
+	}
+
+	/* Configure GPIOs */
+	gpio_config_module(MODULE_I2C, 1);
+
+	/* Set clock frequency */
+	switch (p->kbps) {
+	case 1000:
+		freq = I2C_FREQ_1000KHZ;
+		break;
+	case 400:
+		freq = I2C_FREQ_400KHZ;
+		break;
+	case 100:
+		freq = I2C_FREQ_100KHZ;
+		break;
+	default: /* unknown speed, defaults to 100kBps */
+		CPRINTS("I2C bad speed %d kBps", p->kbps);
+		freq = I2C_FREQ_100KHZ;
+		ret = EC_ERROR_INVAL;
+	}
+
+	/* Set up initial bus frequencies */
+	chip_i2c_set_freq(p->port, freq);
+
+	/* Set up default timeout */
+	i2c_set_timeout(port, 0);
+
+	return ret;
+}
+
+/*****************************************************************************/
+#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
+/* Host command peripheral */
+/*
+ * Buffer for received host command packets (including prefix byte on request,
+ * and result/size on response).  After any protocol-specific headers, the
+ * buffers must be 32-bit aligned.
+ */
+static uint8_t host_buffer_padded[I2C_MAX_HOST_PACKET_SIZE + 4 +
+				  CONFIG_I2C_EXTRA_PACKET_SIZE] __aligned(4);
+static uint8_t *const host_buffer = host_buffer_padded + 2;
+static uint8_t params_copy[I2C_MAX_HOST_PACKET_SIZE] __aligned(4);
+static int host_i2c_resp_port;
+static int tx_pending;
+static int tx_index, tx_end;
+static struct host_packet i2c_packet;
+
+static void i2c_send_response_packet(struct host_packet *pkt)
+{
+	int size = pkt->response_size;
+	uint8_t *out = host_buffer;
+
+	/* Ignore host command in-progress */
+	if (pkt->driver_result == EC_RES_IN_PROGRESS)
+		return;
+
+	/* Write result and size to first two bytes. */
+	*out++ = pkt->driver_result;
+	*out++ = size;
+
+	/* host_buffer data range */
+	tx_index = 0;
+	tx_end = size + 2;
+
+	/*
+	 * Set the transmitter to be in 'not full' state to keep sending
+	 * '0xec' in the event loop. Because of this, the controller i2c
+	 * doesn't need to snoop the response stream to abort transaction.
+	 */
+	STM32_I2C_CR1(host_i2c_resp_port) |= STM32_I2C_CR1_TXIE;
+}
+
+/* Process the command in the i2c host buffer */
+static void i2c_process_command(void)
+{
+	char *buff = host_buffer;
+
+	/*
+	 * TODO(crosbug.com/p/29241): Combine this functionality with the
+	 * i2c_process_command function in chip/stm32/i2c-stm32f.c to make one
+	 * host command i2c process function which handles all protocol
+	 * versions.
+	 */
+	i2c_packet.send_response = i2c_send_response_packet;
+
+	i2c_packet.request = (const void *)(&buff[1]);
+	i2c_packet.request_temp = params_copy;
+	i2c_packet.request_max = sizeof(params_copy);
+	/* Don't know the request size so pass in the entire buffer */
+	i2c_packet.request_size = I2C_MAX_HOST_PACKET_SIZE;
+
+	/*
+	 * Stuff response at buff[2] to leave the first two bytes of
+	 * buffer available for the result and size to send over i2c.  Note
+	 * that this 2-byte offset and the 2-byte offset from host_buffer
+	 * add up to make the response buffer 32-bit aligned.
+	 */
+	i2c_packet.response = (void *)(&buff[2]);
+	i2c_packet.response_max = I2C_MAX_HOST_PACKET_SIZE;
+	i2c_packet.response_size = 0;
+
+	if (*buff >= EC_COMMAND_PROTOCOL_3) {
+		i2c_packet.driver_result = EC_RES_SUCCESS;
+	} else {
+		/* Only host command protocol 3 is supported. */
+		i2c_packet.driver_result = EC_RES_INVALID_HEADER;
+	}
+	host_packet_receive(&i2c_packet);
+}
+
+#ifdef TCPCI_I2C_PERIPHERAL
+static void i2c_send_tcpc_response(int len)
+{
+	/* host_buffer data range, beyond this length, will return 0xec */
+	tx_index = 0;
+	tx_end = len;
+
+	/* enable transmit interrupt and use irq to send data back */
+	STM32_I2C_CR1(host_i2c_resp_port) |= STM32_I2C_CR1_TXIE;
+}
+
+static void i2c_process_tcpc_command(int read, int addr, int len)
+{
+	tcpc_i2c_process(read, TCPC_ADDR_TO_PORT(addr), len, &host_buffer[0],
+			 i2c_send_tcpc_response);
+}
+#endif
+
+static void i2c_event_handler(int port)
+{
+	int i2c_isr;
+	static int rx_pending, buf_idx;
+#ifdef TCPCI_I2C_PERIPHERAL
+	int addr;
+#endif
+
+	i2c_isr = STM32_I2C_ISR(port);
+
+	/*
+	 * Check for error conditions. Note, arbitration loss and bus error
+	 * are the only two errors we can get as a peripheral allowing clock
+	 * stretching and in non-SMBus mode.
+	 */
+	if (i2c_isr & (STM32_I2C_ISR_ARLO | STM32_I2C_ISR_BERR)) {
+		rx_pending = 0;
+		tx_pending = 0;
+
+		/* Make sure TXIS interrupt is disabled */
+		STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE;
+
+		/* Clear error status bits */
+		STM32_I2C_ICR(port) |= STM32_I2C_ICR_BERRCF |
+				       STM32_I2C_ICR_ARLOCF;
+	}
+
+	/* Transfer matched our peripheral address */
+	if (i2c_isr & STM32_I2C_ISR_ADDR) {
+		if (i2c_isr & STM32_I2C_ISR_DIR) {
+			/* Transmitter peripheral */
+			/* Clear transmit buffer */
+			STM32_I2C_ISR(port) |= STM32_I2C_ISR_TXE;
+
+			/* Enable txis interrupt to start response */
+			STM32_I2C_CR1(port) |= STM32_I2C_CR1_TXIE;
+		} else {
+			/* Receiver peripheral */
+			buf_idx = 0;
+			rx_pending = 1;
+		}
+
+		/* Clear ADDR bit by writing to ADDRCF bit */
+		STM32_I2C_ICR(port) |= STM32_I2C_ICR_ADDRCF;
+		/* Inhibit sleep mode when addressed until STOPF flag is set */
+		disable_sleep(SLEEP_MASK_I2C_PERIPHERAL);
+	}
+
+	/* Receiver full event */
+	if (i2c_isr & STM32_I2C_ISR_RXNE)
+		host_buffer[buf_idx++] = STM32_I2C_RXDR(port);
+
+	/* Stop condition on bus */
+	if (i2c_isr & STM32_I2C_ISR_STOP) {
+#ifdef TCPCI_I2C_PERIPHERAL
+		/*
+		 * if tcpc is being addressed, and we received a stop
+		 * while rx is pending, then this is a write only to
+		 * the tcpc.
+		 */
+		addr = STM32_I2C_ISR_ADDCODE(STM32_I2C_ISR(port));
+		if (rx_pending && ADDR_IS_TCPC(addr))
+			i2c_process_tcpc_command(0, addr, buf_idx);
+#endif
+		rx_pending = 0;
+		tx_pending = 0;
+
+		/* Make sure TXIS interrupt is disabled */
+		STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE;
+
+		/* Clear STOPF bit by writing to STOPCF bit */
+		STM32_I2C_ICR(port) |= STM32_I2C_ICR_STOPCF;
+
+		/* No longer inhibit deep sleep after stop condition */
+		enable_sleep(SLEEP_MASK_I2C_PERIPHERAL);
+	}
+
+	/* Controller requested STOP or RESTART */
+	if (i2c_isr & STM32_I2C_ISR_NACK) {
+		/* Make sure TXIS interrupt is disabled */
+		STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE;
+		/* Clear NACK */
+		STM32_I2C_ICR(port) |= STM32_I2C_ICR_NACKCF;
+		/* Resend last byte on RESTART */
+		if (port == I2C_PORT_EC && tx_index)
+			tx_index--;
+	}
+
+	/* Transmitter empty event */
+	if (i2c_isr & STM32_I2C_ISR_TXIS) {
+		if (port == I2C_PORT_EC) { /* host is waiting for PD response */
+			if (tx_pending) {
+				if (tx_index < tx_end) {
+					STM32_I2C_TXDR(port) =
+						host_buffer[tx_index++];
+				} else {
+					STM32_I2C_TXDR(port) = 0xec;
+					/*
+					 * Set tx_index = 0 to prevent NACK
+					 * handler resending last buffer byte.
+					 */
+					tx_index = 0;
+					tx_end = 0;
+					/* No pending data */
+					tx_pending = 0;
+				}
+			} else if (rx_pending) {
+				host_i2c_resp_port = port;
+				/*
+				 * Disable TXIS interrupt, transmission will
+				 * be prepared by host command task.
+				 */
+				STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE;
+
+#ifdef TCPCI_I2C_PERIPHERAL
+				addr = STM32_I2C_ISR_ADDCODE(
+					STM32_I2C_ISR(port));
+				if (ADDR_IS_TCPC(addr))
+					i2c_process_tcpc_command(1, addr,
+								 buf_idx);
+				else
+#endif
+					i2c_process_command();
+
+				/* Reset host buffer after end of transfer */
+				rx_pending = 0;
+				tx_pending = 1;
+			} else {
+				STM32_I2C_TXDR(port) = 0xec;
+			}
+		}
+	}
+}
+static void i2c2_event_interrupt(void)
+{
+	i2c_event_handler(I2C_PORT_EC);
+}
+DECLARE_IRQ(IRQ_PERIPHERAL, i2c2_event_interrupt, 2);
+#endif
+
+/*****************************************************************************/
+/* Interface */
+
+int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out,
+		  int out_bytes, uint8_t *in, int in_bytes, int flags)
+{
+	int addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1;
+	int rv = EC_SUCCESS;
+	int i;
+	int xfer_start = flags & I2C_XFER_START;
+	int xfer_stop = flags & I2C_XFER_STOP;
+
+#if defined(CONFIG_I2C_SCL_GATE_ADDR) && defined(CONFIG_I2C_SCL_GATE_PORT)
+	if (port == CONFIG_I2C_SCL_GATE_PORT &&
+	    addr_flags == CONFIG_I2C_SCL_GATE_ADDR_FLAGS)
+		gpio_set_level(CONFIG_I2C_SCL_GATE_GPIO, 1);
+#endif
+
+	ASSERT(out || !out_bytes);
+	ASSERT(in || !in_bytes);
+
+	/* Clear status */
+	if (xfer_start) {
+		uint32_t cr2 = STM32_I2C_CR2(port);
+
+		STM32_I2C_ICR(port) = STM32_I2C_ICR_ALL;
+		STM32_I2C_CR2(port) = 0;
+		if (cr2 & STM32_I2C_CR2_RELOAD) {
+			/*
+			 * If I2C_XFER_START flag is on and we've set RELOAD=1
+			 * in previous chip_i2c_xfer() call. Then we are
+			 * probably in the middle of an i2c transaction.
+			 *
+			 * In this case, we need to clear the RELOAD bit and
+			 * wait for Transfer Complete (TC) flag, to make sure
+			 * the chip is not expecting another NBYTES data, And
+			 * send repeated-start correctly.
+			 */
+			rv = wait_isr(port, STM32_I2C_ISR_TC);
+			if (rv)
+				goto xfer_exit;
+		}
+	}
+
+	if (out_bytes || !in_bytes) {
+		/*
+		 * Configure the write transfer: if we are stopping then set
+		 * AUTOEND bit to automatically set STOP bit after NBYTES.
+		 * if we are not stopping, set RELOAD bit so that we can load
+		 * NBYTES again. if we are starting, then set START bit.
+		 */
+		STM32_I2C_CR2(port) =
+			((out_bytes & 0xFF) << 16) | addr_8bit |
+			((in_bytes == 0 && xfer_stop) ? STM32_I2C_CR2_AUTOEND :
+							0) |
+			((in_bytes == 0 && !xfer_stop) ? STM32_I2C_CR2_RELOAD :
+							 0) |
+			(xfer_start ? STM32_I2C_CR2_START : 0);
+
+		for (i = 0; i < out_bytes; i++) {
+			rv = wait_isr(port, STM32_I2C_ISR_TXIS);
+			if (rv)
+				goto xfer_exit;
+			/* Write next data byte */
+			STM32_I2C_TXDR(port) = out[i];
+		}
+	}
+	if (in_bytes) {
+		if (out_bytes) { /* wait for completion of the write */
+			rv = wait_isr(port, STM32_I2C_ISR_TC);
+			if (rv)
+				goto xfer_exit;
+		}
+		/*
+		 * Configure the read transfer: if we are stopping then set
+		 * AUTOEND bit to automatically set STOP bit after NBYTES.
+		 * if we are not stopping, set RELOAD bit so that we can load
+		 * NBYTES again. if we were just transmitting, we need to
+		 * set START bit to send (re)start and begin read transaction.
+		 */
+		STM32_I2C_CR2(port) =
+			((in_bytes & 0xFF) << 16) | STM32_I2C_CR2_RD_WRN |
+			addr_8bit | (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0) |
+			(!xfer_stop ? STM32_I2C_CR2_RELOAD : 0) |
+			(out_bytes || xfer_start ? STM32_I2C_CR2_START : 0);
+
+		for (i = 0; i < in_bytes; i++) {
+			/* Wait for receive buffer not empty */
+			rv = wait_isr(port, STM32_I2C_ISR_RXNE);
+			if (rv)
+				goto xfer_exit;
+
+			in[i] = STM32_I2C_RXDR(port);
+		}
+	}
+
+	/*
+	 * If we are stopping, then we already set AUTOEND and we should
+	 * wait for the stop bit to be transmitted. Otherwise, we set
+	 * the RELOAD bit and we should wait for transfer complete
+	 * reload (TCR).
+	 */
+	rv = wait_isr(port, xfer_stop ? STM32_I2C_ISR_STOP : STM32_I2C_ISR_TCR);
+	if (rv)
+		goto xfer_exit;
+
+xfer_exit:
+	/* clear status */
+	if (xfer_stop)
+		STM32_I2C_ICR(port) = STM32_I2C_ICR_ALL;
+
+	/* On error, queue a stop condition */
+	if (rv) {
+		/* queue a STOP condition */
+		STM32_I2C_CR2(port) |= STM32_I2C_CR2_STOP;
+		/* wait for it to take effect */
+		/* Wait up to 100 us for bus idle */
+		for (i = 0; i < 10; i++) {
+			if (!(STM32_I2C_ISR(port) & STM32_I2C_ISR_BUSY))
+				break;
+			udelay(10);
+		}
+
+		/*
+		 * Allow bus to idle for at least one 100KHz clock = 10 us.
+		 * This allows peripherals on the bus to detect bus-idle before
+		 * the next start condition.
+		 */
+		udelay(10);
+		/* re-initialize the controller */
+		STM32_I2C_CR2(port) = 0;
+		STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_PE;
+		udelay(10);
+		STM32_I2C_CR1(port) |= STM32_I2C_CR1_PE;
+	}
+
+#ifdef CONFIG_I2C_SCL_GATE_ADDR
+	if (port == CONFIG_I2C_SCL_GATE_PORT &&
+	    addr_flags == CONFIG_I2C_SCL_GATE_ADDR_FLAGS)
+		gpio_set_level(CONFIG_I2C_SCL_GATE_GPIO, 0);
+#endif
+
+	return rv;
+}
+
+int i2c_raw_get_scl(int port)
+{
+	enum gpio_signal g;
+
+	if (get_scl_from_i2c_port(port, &g) == EC_SUCCESS)
+		return gpio_get_level(g);
+
+	/* If no SCL pin defined for this port, then return 1 to appear idle. */
+	return 1;
+}
+
+int i2c_raw_get_sda(int port)
+{
+	enum gpio_signal g;
+
+	if (get_sda_from_i2c_port(port, &g) == EC_SUCCESS)
+		return gpio_get_level(g);
+
+	/* If no SCL pin defined for this port, then return 1 to appear idle. */
+	return 1;
+}
+
+int i2c_get_line_levels(int port)
+{
+	return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) |
+	       (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
+}
+
+void i2c_init(void)
+{
+	const struct i2c_port_t *p = i2c_ports;
+	int i;
+
+	for (i = 0; i < i2c_ports_used; i++, p++)
+		i2c_init_port(p);
+
+#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
+	STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_RXIE | STM32_I2C_CR1_ERRIE |
+				      STM32_I2C_CR1_ADDRIE |
+				      STM32_I2C_CR1_STOPIE |
+				      STM32_I2C_CR1_NACKIE;
+#if defined(CONFIG_LOW_POWER_IDLE) && (I2C_PORT_EC == STM32_I2C1_PORT)
+	/*
+	 * If using low power idle and EC port is I2C1, then set I2C1 to wake
+	 * from STOP mode on address match. Note, this only works on I2C1 and
+	 * only if the clock to I2C1 is HSI 8MHz.
+	 */
+	STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_WUPEN;
+#endif
+	STM32_I2C_OAR1(I2C_PORT_EC) =
+		0x8000 | (I2C_STRIP_FLAGS(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) << 1);
+#ifdef TCPCI_I2C_PERIPHERAL
+	/*
+	 * Configure TCPC address with OA2[1] masked so that we respond
+	 * to CONFIG_TCPC_I2C_BASE_ADDR and CONFIG_TCPC_I2C_BASE_ADDR + 2.
+	 */
+	STM32_I2C_OAR2(I2C_PORT_EC) =
+		0x8100 |
+		(I2C_STRIP_FLAGS(CONFIG_TCPC_I2C_BASE_ADDR_FLAGS) << 1);
+#endif
+	task_enable_irq(IRQ_PERIPHERAL);
+#endif
+}
diff --git a/chip/stm32/i2c-stm32f4.c b/chip/stm32/i2c-stm32f4.c
index bce81b14c9..9f4d799912 100644
--- a/chip/stm32/i2c-stm32f4.c
+++ b/chip/stm32/i2c-stm32f4.c
@@ -1,9 +1,10 @@
 
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "builtin/assert.h"
 #include "chipset.h"
 #include "clock.h"
 #include "common.h"
@@ -20,12 +21,12 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
 
 #define I2C_ERROR_FAILED_START EC_ERROR_INTERNAL_FIRST
 
 /* Transmit timeout in microseconds */
-#define I2C_TX_TIMEOUT_CONTROLLER   (10 * MSEC)
+#define I2C_TX_TIMEOUT_CONTROLLER (10 * MSEC)
 
 #ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
 #if (I2C_PORT_EC == STM32_I2C1_PORT)
@@ -43,36 +44,36 @@
  * two sets of functions to handle this for stm32f4. In stm32f446, we
  * only have one FMP block so we'll hardcode its port number.
  */
-#define STM32F4_FMPI2C_PORT	3
+#define STM32F4_FMPI2C_PORT 3
 
 static const __unused struct dma_option dma_tx_option[I2C_PORT_COUNT] = {
-	{STM32_DMAC_I2C1_TX, (void *)&STM32_I2C_DR(STM32_I2C1_PORT),
-	 STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
-	 STM32_DMA_CCR_CHANNEL(STM32_I2C1_TX_REQ_CH)},
-	{STM32_DMAC_I2C2_TX, (void *)&STM32_I2C_DR(STM32_I2C2_PORT),
-	 STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
-	 STM32_DMA_CCR_CHANNEL(STM32_I2C2_TX_REQ_CH)},
-	{STM32_DMAC_I2C3_TX, (void *)&STM32_I2C_DR(STM32_I2C3_PORT),
-	 STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
-	 STM32_DMA_CCR_CHANNEL(STM32_I2C3_TX_REQ_CH)},
-	{STM32_DMAC_FMPI2C4_TX, (void *)&STM32_FMPI2C_TXDR(STM32_FMPI2C4_PORT),
-	 STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
-	 STM32_DMA_CCR_CHANNEL(STM32_FMPI2C4_TX_REQ_CH)},
+	{ STM32_DMAC_I2C1_TX, (void *)&STM32_I2C_DR(STM32_I2C1_PORT),
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
+		  STM32_DMA_CCR_CHANNEL(STM32_I2C1_TX_REQ_CH) },
+	{ STM32_DMAC_I2C2_TX, (void *)&STM32_I2C_DR(STM32_I2C2_PORT),
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
+		  STM32_DMA_CCR_CHANNEL(STM32_I2C2_TX_REQ_CH) },
+	{ STM32_DMAC_I2C3_TX, (void *)&STM32_I2C_DR(STM32_I2C3_PORT),
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
+		  STM32_DMA_CCR_CHANNEL(STM32_I2C3_TX_REQ_CH) },
+	{ STM32_DMAC_FMPI2C4_TX, (void *)&STM32_FMPI2C_TXDR(STM32_FMPI2C4_PORT),
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
+		  STM32_DMA_CCR_CHANNEL(STM32_FMPI2C4_TX_REQ_CH) },
 };
 
 static const struct dma_option dma_rx_option[I2C_PORT_COUNT] = {
-	{STM32_DMAC_I2C1_RX, (void *)&STM32_I2C_DR(STM32_I2C1_PORT),
-	 STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
-	 STM32_DMA_CCR_CHANNEL(STM32_I2C1_RX_REQ_CH)},
-	{STM32_DMAC_I2C2_RX, (void *)&STM32_I2C_DR(STM32_I2C2_PORT),
-	 STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
-	 STM32_DMA_CCR_CHANNEL(STM32_I2C2_RX_REQ_CH)},
-	{STM32_DMAC_I2C3_RX, (void *)&STM32_I2C_DR(STM32_I2C3_PORT),
-	 STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
-	 STM32_DMA_CCR_CHANNEL(STM32_I2C3_RX_REQ_CH)},
-	{STM32_DMAC_FMPI2C4_RX, (void *)&STM32_FMPI2C_RXDR(STM32_FMPI2C4_PORT),
-	 STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
-	 STM32_DMA_CCR_CHANNEL(STM32_FMPI2C4_RX_REQ_CH)},
+	{ STM32_DMAC_I2C1_RX, (void *)&STM32_I2C_DR(STM32_I2C1_PORT),
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
+		  STM32_DMA_CCR_CHANNEL(STM32_I2C1_RX_REQ_CH) },
+	{ STM32_DMAC_I2C2_RX, (void *)&STM32_I2C_DR(STM32_I2C2_PORT),
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
+		  STM32_DMA_CCR_CHANNEL(STM32_I2C2_RX_REQ_CH) },
+	{ STM32_DMAC_I2C3_RX, (void *)&STM32_I2C_DR(STM32_I2C3_PORT),
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
+		  STM32_DMA_CCR_CHANNEL(STM32_I2C3_RX_REQ_CH) },
+	{ STM32_DMAC_FMPI2C4_RX, (void *)&STM32_FMPI2C_RXDR(STM32_FMPI2C4_PORT),
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
+		  STM32_DMA_CCR_CHANNEL(STM32_FMPI2C4_RX_REQ_CH) },
 };
 
 /* Callback for ISR to wake task on DMA complete. */
@@ -164,7 +165,6 @@ static int wait_sr1(int port, int mask)
 	return wait_sr1_poll(port, mask, SET, 100);
 }
 
-
 /**
  * Send a start condition and peripheral address on the specified port.
  *
@@ -232,8 +232,8 @@ static int wait_fmpi2c_isr_poll(int port, int mask, int val, int poll)
 		int isr = STM32_FMPI2C_ISR(port);
 
 		/* Check for errors */
-		if (isr & (FMPI2C_ISR_ARLO | FMPI2C_ISR_BERR |
-			   FMPI2C_ISR_NACKF)) {
+		if (isr &
+		    (FMPI2C_ISR_ARLO | FMPI2C_ISR_BERR | FMPI2C_ISR_NACKF)) {
 			return EC_ERROR_UNKNOWN;
 		}
 
@@ -265,19 +265,18 @@ static int wait_fmpi2c_isr(int port, int mask)
  *
  * @return Non-zero if error.
  */
-static int send_fmpi2c_start(const int port, const uint16_t addr_8bit,
-			     int size, int is_read)
+static int send_fmpi2c_start(const int port, const uint16_t addr_8bit, int size,
+			     int is_read)
 {
 	uint32_t reg;
 
 	/* Send start bit */
 	reg = STM32_FMPI2C_CR2(port);
 	reg &= ~(FMPI2C_CR2_SADD_MASK | FMPI2C_CR2_SIZE_MASK |
-		FMPI2C_CR2_RELOAD | FMPI2C_CR2_AUTOEND |
-		FMPI2C_CR2_RD_WRN | FMPI2C_CR2_START | FMPI2C_CR2_STOP);
-	reg |= FMPI2C_CR2_START | FMPI2C_CR2_AUTOEND |
-		addr_8bit | FMPI2C_CR2_SIZE(size) |
-		(is_read ? FMPI2C_CR2_RD_WRN : 0);
+		 FMPI2C_CR2_RELOAD | FMPI2C_CR2_AUTOEND | FMPI2C_CR2_RD_WRN |
+		 FMPI2C_CR2_START | FMPI2C_CR2_STOP);
+	reg |= FMPI2C_CR2_START | FMPI2C_CR2_AUTOEND | addr_8bit |
+	       FMPI2C_CR2_SIZE(size) | (is_read ? FMPI2C_CR2_RD_WRN : 0);
 	STM32_FMPI2C_CR2(port) = reg;
 
 	return EC_SUCCESS;
@@ -300,17 +299,17 @@ static void i2c_set_freq_port(const struct i2c_port_t *p)
 
 		/* FMP I2C clock set. */
 		STM32_FMPI2C_CR1(port) &= ~FMPI2C_CR1_PE;
-		prescalar = (freq / (p->kbps * 1000 *
-			     (0x12 + 1 + 0xe + 1 + 1))) - 1;
+		prescalar =
+			(freq / (p->kbps * 1000 * (0x12 + 1 + 0xe + 1 + 1))) -
+			1;
 		actual = freq / ((prescalar + 1) * (0x12 + 1 + 0xe + 1 + 1));
 
-		reg = FMPI2C_TIMINGR_SCLL(0x12) |
-			FMPI2C_TIMINGR_SCLH(0xe) |
-			FMPI2C_TIMINGR_PRESC(prescalar);
+		reg = FMPI2C_TIMINGR_SCLL(0x12) | FMPI2C_TIMINGR_SCLH(0xe) |
+		      FMPI2C_TIMINGR_PRESC(prescalar);
 		STM32_FMPI2C_TIMINGR(port) = reg;
 
-		CPRINTS("port %d target %d, pre %d, act %d, reg 0x%08x",
-			port, p->kbps, prescalar, actual, reg);
+		CPRINTS("port %d target %d, pre %d, act %d, reg 0x%08x", port,
+			p->kbps, prescalar, actual, reg);
 
 		STM32_FMPI2C_CR1(port) |= FMPI2C_CR1_PE;
 		udelay(10);
@@ -323,9 +322,9 @@ static void i2c_set_freq_port(const struct i2c_port_t *p)
 		if (p->kbps > 100) {
 			STM32_I2C_CCR(port) = freq / (2 * MSEC * p->kbps);
 		} else {
-			STM32_I2C_CCR(port) = STM32_I2C_CCR_FM
-				| STM32_I2C_CCR_DUTY
-				| (freq / (16 + 9 * MSEC * p->kbps));
+			STM32_I2C_CCR(port) =
+				STM32_I2C_CCR_FM | STM32_I2C_CCR_DUTY |
+				(freq / (16 + 9 * MSEC * p->kbps));
 		}
 		STM32_I2C_CR2(port) = freq / SECOND;
 		STM32_I2C_TRISE(port) = freq / SECOND + 1;
@@ -384,10 +383,10 @@ static void fmpi2c_clear_regs(int port)
 	STM32_FMPI2C_ICR(port) = 0xffffffff;
 
 	/* Clear start, stop, NACK, etc. bits to get us in a known state */
-	STM32_FMPI2C_CR2(port) &= ~(FMPI2C_CR2_START | FMPI2C_CR2_STOP |
-				FMPI2C_CR2_RD_WRN | FMPI2C_CR2_NACK |
-				FMPI2C_CR2_AUTOEND |
-				FMPI2C_CR2_SADD_MASK | FMPI2C_CR2_SIZE_MASK);
+	STM32_FMPI2C_CR2(port) &=
+		~(FMPI2C_CR2_START | FMPI2C_CR2_STOP | FMPI2C_CR2_RD_WRN |
+		  FMPI2C_CR2_NACK | FMPI2C_CR2_AUTOEND | FMPI2C_CR2_SADD_MASK |
+		  FMPI2C_CR2_SIZE_MASK);
 }
 
 /**
@@ -404,8 +403,8 @@ static void fmpi2c_clear_regs(int port)
  * @return		EC_SUCCESS on success.
  */
 static int chip_fmpi2c_xfer(const int port, const uint16_t addr_8bit,
-			    const uint8_t *out, int out_bytes,
-			    uint8_t *in, int in_bytes, int flags)
+			    const uint8_t *out, int out_bytes, uint8_t *in,
+			    int in_bytes, int flags)
 {
 	int started = (flags & I2C_XFER_START) ? 0 : 1;
 	int rv = EC_SUCCESS;
@@ -424,8 +423,8 @@ static int chip_fmpi2c_xfer(const int port, const uint16_t addr_8bit,
 
 	/* No out bytes and no in bytes means just check for active */
 	if (out_bytes || !in_bytes) {
-		rv = send_fmpi2c_start(
-			port, addr_8bit, out_bytes, FMPI2C_WRITE);
+		rv = send_fmpi2c_start(port, addr_8bit, out_bytes,
+				       FMPI2C_WRITE);
 		if (rv)
 			goto xfer_exit;
 
@@ -450,8 +449,8 @@ static int chip_fmpi2c_xfer(const int port, const uint16_t addr_8bit,
 		dma_start_rx(dma, in_bytes, in);
 		i2c_dma_enable_tc_interrupt(dma->channel, port);
 
-		rv_start = send_fmpi2c_start(
-				port, addr_8bit, in_bytes, FMPI2C_READ);
+		rv_start = send_fmpi2c_start(port, addr_8bit, in_bytes,
+					     FMPI2C_READ);
 		if (rv_start)
 			goto xfer_exit;
 
@@ -460,9 +459,8 @@ static int chip_fmpi2c_xfer(const int port, const uint16_t addr_8bit,
 			goto xfer_exit;
 		STM32_FMPI2C_CR1(port) |= FMPI2C_CR1_RXDMAEN;
 
-		rv = task_wait_event_mask(
-				TASK_EVENT_I2C_COMPLETION(port),
-				DMA_TRANSFER_TIMEOUT_US);
+		rv = task_wait_event_mask(TASK_EVENT_I2C_COMPLETION(port),
+					  DMA_TRANSFER_TIMEOUT_US);
 		if (rv & TASK_EVENT_I2C_COMPLETION(port))
 			rv = EC_SUCCESS;
 		else
@@ -478,7 +476,7 @@ static int chip_fmpi2c_xfer(const int port, const uint16_t addr_8bit,
 		STM32_FMPI2C_CR1(port) &= ~FMPI2C_CR1_RXDMAEN;
 	}
 
- xfer_exit:
+xfer_exit:
 	/* On error, queue a stop condition */
 	if (rv) {
 		flags |= I2C_XFER_STOP;
@@ -492,7 +490,8 @@ static int chip_fmpi2c_xfer(const int port, const uint16_t addr_8bit,
 			const struct i2c_port_t *p;
 
 			CPRINTS("chip_fmpi2c_xfer start error; "
-				"unwedging and resetting i2c %d", port);
+				"unwedging and resetting i2c %d",
+				port);
 
 			p = find_port(port);
 			i2c_unwedge(port);
@@ -522,7 +521,6 @@ static int chip_fmpi2c_xfer(const int port, const uint16_t addr_8bit,
 	return rv;
 }
 
-
 /**
  * Clear status regs on the specified I2C port.
  *
@@ -539,10 +537,8 @@ static void i2c_clear_regs(int port)
 	STM32_I2C_SR1(port) = 0;
 
 	/* Clear start, stop, POS, ACK bits to get us in a known state */
-	STM32_I2C_CR1(port) &= ~(STM32_I2C_CR1_START |
-				 STM32_I2C_CR1_STOP |
-				 STM32_I2C_CR1_POS |
-				 STM32_I2C_CR1_ACK);
+	STM32_I2C_CR1(port) &= ~(STM32_I2C_CR1_START | STM32_I2C_CR1_STOP |
+				 STM32_I2C_CR1_POS | STM32_I2C_CR1_ACK);
 }
 
 /*****************************************************************************
@@ -550,9 +546,8 @@ static void i2c_clear_regs(int port)
  */
 
 /* Perform an i2c transaction. */
-int chip_i2c_xfer(const int port, const uint16_t addr_flags,
-		  const uint8_t *out, int out_bytes,
-		  uint8_t *in, int in_bytes, int flags)
+int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out,
+		  int out_bytes, uint8_t *in, int in_bytes, int flags)
 {
 	int addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1;
 	int started = (flags & I2C_XFER_START) ? 0 : 1;
@@ -565,9 +560,8 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags,
 	ASSERT(!started);
 
 	if (p->port == STM32F4_FMPI2C_PORT) {
-		return chip_fmpi2c_xfer(port, addr_8bit,
-					out, out_bytes,
-					in, in_bytes, flags);
+		return chip_fmpi2c_xfer(port, addr_8bit, out, out_bytes, in,
+					in_bytes, flags);
 	}
 
 	i2c_clear_regs(port);
@@ -644,7 +638,7 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags,
 		STM32_I2C_CR2(port) &= ~STM32_I2C_CR2_DMAEN;
 	}
 
- xfer_exit:
+xfer_exit:
 	/* On error, queue a stop condition */
 	if (rv) {
 		flags |= I2C_XFER_STOP;
@@ -658,7 +652,8 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags,
 			const struct i2c_port_t *p;
 
 			CPRINTS("chip_i2c_xfer start error; "
-				"unwedging and resetting i2c %d", port);
+				"unwedging and resetting i2c %d",
+				port);
 
 			p = find_port(port);
 			i2c_unwedge(port);
@@ -711,7 +706,7 @@ int i2c_raw_get_sda(int port)
 int i2c_get_line_levels(int port)
 {
 	return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) |
-		(i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
+	       (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
 }
 
 /*****************************************************************************/
@@ -766,7 +761,7 @@ DECLARE_HOOK(HOOK_FREQ_CHANGE, i2c_freq_change_hook, HOOK_PRIO_DEFAULT);
  */
 static uint8_t host_buffer_padded[I2C_MAX_HOST_PACKET_SIZE + 4 +
 				  CONFIG_I2C_EXTRA_PACKET_SIZE] __aligned(4);
-static uint8_t * const host_buffer = host_buffer_padded + 2;
+static uint8_t *const host_buffer = host_buffer_padded + 2;
 static uint8_t params_copy[I2C_MAX_HOST_PACKET_SIZE] __aligned(4);
 static int host_i2c_resp_port;
 static int tx_pending;
@@ -879,14 +874,16 @@ static void i2c_event_handler(int port)
 		/* Disable buffer interrupt */
 		STM32_I2C_CR2(port) &= ~STM32_I2C_CR2_ITBUFEN;
 		/* Clear error status bits */
-		STM32_I2C_SR1(port) &= ~(STM32_I2C_SR1_ARLO |
-					 STM32_I2C_SR1_BERR);
+		STM32_I2C_SR1(port) &=
+			~(STM32_I2C_SR1_ARLO | STM32_I2C_SR1_BERR);
 	}
 
 	/* Transfer matched our peripheral address */
 	if (i2c_sr1 & STM32_I2C_SR1_ADDR) {
 		addr_8bit = ((i2c_sr2 & STM32_I2C_SR2_DUALF) ?
-			STM32_I2C_OAR2(port) : STM32_I2C_OAR1(port)) & 0xfe;
+				     STM32_I2C_OAR2(port) :
+				     STM32_I2C_OAR1(port)) &
+			    0xfe;
 		if (i2c_sr2 & STM32_I2C_SR2_TRA) {
 			/* Transmitter peripheral */
 			i2c_sr1 |= STM32_I2C_SR1_TXE;
@@ -957,7 +954,7 @@ static void i2c_event_handler(int port)
 #ifdef CONFIG_BOARD_I2C_ADDR_FLAGS
 		if (rx_pending &&
 		    (addr_8b >> 1) ==
-		    I2C_STRIP_FLAGS(CONFIG_BOARD_I2C_ADDR_FLAGS))
+			    I2C_STRIP_FLAGS(CONFIG_BOARD_I2C_ADDR_FLAGS))
 			i2c_process_board_command(0, addr_8bit, buf_idx);
 #endif
 		rx_pending = 0;
@@ -977,12 +974,14 @@ static void i2c_event_handler(int port)
 	if (!(i2c_cr1 & STM32_I2C_CR1_PE))
 		STM32_I2C_CR1(port) |= STM32_I2C_CR1_PE;
 }
-static void i2c_event_interrupt(void) { i2c_event_handler(I2C_PORT_EC); }
+static void i2c_event_interrupt(void)
+{
+	i2c_event_handler(I2C_PORT_EC);
+}
 DECLARE_IRQ(IRQ_PERIPHERAL_EV, i2c_event_interrupt, 2);
 DECLARE_IRQ(IRQ_PERIPHERAL_ER, i2c_event_interrupt, 2);
 #endif
 
-
 /* Init all available i2c ports */
 void i2c_init(void)
 {
@@ -992,19 +991,20 @@ void i2c_init(void)
 	for (i = 0; i < i2c_ports_used; i++, p++)
 		i2c_init_port(p);
 
-
 #ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
 	/* Enable ACK */
 	STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_ACK;
 	/* Enable interrupts */
-	STM32_I2C_CR2(I2C_PORT_EC) |= STM32_I2C_CR2_ITEVTEN
-			| STM32_I2C_CR2_ITERREN;
+	STM32_I2C_CR2(I2C_PORT_EC) |= STM32_I2C_CR2_ITEVTEN |
+				      STM32_I2C_CR2_ITERREN;
 	/* Setup host command peripheral */
-	STM32_I2C_OAR1(I2C_PORT_EC) = STM32_I2C_OAR1_B14
-		| (I2C_STRIP_ADDR(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) << 1);
+	STM32_I2C_OAR1(I2C_PORT_EC) =
+		STM32_I2C_OAR1_B14 |
+		(I2C_STRIP_ADDR(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) << 1);
 #ifdef CONFIG_BOARD_I2C_ADDR_FLAGS
-	STM32_I2C_OAR2(I2C_PORT_EC) = STM32_I2C_OAR2_ENDUAL
-		| (I2C_STRIP_FLAGS(CONFIG_BOARD_I2C_ADDR_FLAGS) << 1);
+	STM32_I2C_OAR2(I2C_PORT_EC) =
+		STM32_I2C_OAR2_ENDUAL |
+		(I2C_STRIP_FLAGS(CONFIG_BOARD_I2C_ADDR_FLAGS) << 1);
 #endif
 	task_enable_irq(IRQ_PERIPHERAL_EV);
 	task_enable_irq(IRQ_PERIPHERAL_ER);
diff --git a/chip/stm32/i2c-stm32g4.c b/chip/stm32/i2c-stm32g4.c
index fbb13e3453..66ec8173d8 100644
--- a/chip/stm32/i2c-stm32g4.c
+++ b/chip/stm32/i2c-stm32g4.c
@@ -1,8 +1,9 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "builtin/assert.h"
 #include "chipset.h"
 #include "clock.h"
 #include "common.h"
@@ -20,12 +21,12 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
 
 #define I2C_ERROR_FAILED_START EC_ERROR_INTERNAL_FIRST
 
 /* Transmit timeout in microseconds */
-#define I2C_TX_TIMEOUT_MASTER   (10 * MSEC)
+#define I2C_TX_TIMEOUT_MASTER (10 * MSEC)
 
 enum i2c_freq_khz {
 	freq_100 = 100,
@@ -44,8 +45,8 @@ struct i2c_timing {
 /* timing register values for supported input clks / i2c clk rates */
 static const uint32_t busyloop_us[I2C_FREQ_COUNT] = {
 	[I2C_FREQ_1000KHZ] = 16, /* Enough for 2 bytes */
-	[I2C_FREQ_400KHZ] = 40,  /* Enough for 2 bytes */
-	[I2C_FREQ_100KHZ] = 0,   /* No busy looping at 100kHz (bus is slow) */
+	[I2C_FREQ_400KHZ] = 40, /* Enough for 2 bytes */
+	[I2C_FREQ_100KHZ] = 0, /* No busy looping at 100kHz (bus is slow) */
 };
 
 /*
@@ -94,8 +95,8 @@ static const uint32_t i2c_regs_base[] = {
 
 /* I2C port state data */
 struct i2c_port_data {
-	uint32_t timeout_us;    /* Transaction timeout, or 0 to use default */
-	enum i2c_freq freq;	/* Port clock speed */
+	uint32_t timeout_us; /* Transaction timeout, or 0 to use default */
+	enum i2c_freq freq; /* Port clock speed */
 };
 static struct i2c_port_data pdata[I2C_PORT_COUNT];
 
@@ -145,10 +146,10 @@ static void i2c_set_timingr_port(const struct i2c_port_t *p)
 	}
 	/* Assemble write value for timingr register */
 	timingr = (i2c_timingr[index].scll << STM32_I2C_TIMINGR_SCLL_OFF) |
-		(i2c_timingr[index].sclh << STM32_I2C_TIMINGR_SCLH_OFF) |
-		(i2c_timingr[index].sdadel << STM32_I2C_TIMINGR_SDADEL_OFF) |
-		(i2c_timingr[index].scldel << STM32_I2C_TIMINGR_SCLDEL_OFF) |
-		(i2c_timingr[index].presc << STM32_I2C_TIMINGR_PRESC_OFF);
+		  (i2c_timingr[index].sclh << STM32_I2C_TIMINGR_SCLH_OFF) |
+		  (i2c_timingr[index].sdadel << STM32_I2C_TIMINGR_SDADEL_OFF) |
+		  (i2c_timingr[index].scldel << STM32_I2C_TIMINGR_SCLDEL_OFF) |
+		  (i2c_timingr[index].presc << STM32_I2C_TIMINGR_PRESC_OFF);
 
 	/* Write timingr value */
 	STM32_I2C_TIMINGR(base) = timingr;
@@ -189,8 +190,8 @@ static void i2c_init_port(const struct i2c_port_t *p)
 		mask = STM32_RCC_CCIPR_I2CNSEL_MASK << shift;
 		clksel = STM32_RCC_CCIPR;
 		clksel &= ~mask;
-		STM32_RCC_CCIPR = clksel | (STM32_RCC_CCIPR_I2CNSEL_HSI
-					    << shift);
+		STM32_RCC_CCIPR = clksel |
+				  (STM32_RCC_CCIPR_I2CNSEL_HSI << shift);
 	} else if (port == 3) {
 		/* i2c4sel is bits 1:0, no shift required */
 		STM32_RCC_CCIPR2 &= ~STM32_RCC_CCIPR2_I2C4SEL_MASK;
@@ -260,9 +261,8 @@ static int wait_isr(int port, int mask)
  * Exported functions declared in i2c.h
  */
 /* Perform an i2c transaction. */
-int chip_i2c_xfer(const int port, const uint16_t addr_flags,
-		  const uint8_t *out, int out_bytes,
-		  uint8_t *in, int in_bytes, int flags)
+int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out,
+		  int out_bytes, uint8_t *in, int in_bytes, int flags)
 {
 	int addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1;
 	int rv = EC_SUCCESS;
@@ -290,13 +290,13 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags,
 		 * if we are not stopping, set RELOAD bit so that we can load
 		 * NBYTES again. if we are starting, then set START bit.
 		 */
-		STM32_I2C_CR2(base) = ((out_bytes & 0xFF) << 16)
-			| addr_8bit
-			| ((in_bytes == 0 && xfer_stop) ?
-				STM32_I2C_CR2_AUTOEND : 0)
-			| ((in_bytes == 0 && !xfer_stop) ?
-				STM32_I2C_CR2_RELOAD : 0)
-			| (xfer_start ? STM32_I2C_CR2_START : 0);
+		STM32_I2C_CR2(base) =
+			((out_bytes & 0xFF) << 16) | addr_8bit |
+			((in_bytes == 0 && xfer_stop) ? STM32_I2C_CR2_AUTOEND :
+							0) |
+			((in_bytes == 0 && !xfer_stop) ? STM32_I2C_CR2_RELOAD :
+							 0) |
+			(xfer_start ? STM32_I2C_CR2_START : 0);
 
 		for (i = 0; i < out_bytes; i++) {
 			rv = wait_isr(port, STM32_I2C_ISR_TXIS);
@@ -319,11 +319,11 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags,
 		 * NBYTES again. if we were just transmitting, we need to
 		 * set START bit to send (re)start and begin read transaction.
 		 */
-		STM32_I2C_CR2(base) = ((in_bytes & 0xFF) << 16)
-			| STM32_I2C_CR2_RD_WRN | addr_8bit
-			| (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0)
-			| (!xfer_stop ? STM32_I2C_CR2_RELOAD : 0)
-			| (out_bytes || xfer_start ? STM32_I2C_CR2_START : 0);
+		STM32_I2C_CR2(base) =
+			((in_bytes & 0xFF) << 16) | STM32_I2C_CR2_RD_WRN |
+			addr_8bit | (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0) |
+			(!xfer_stop ? STM32_I2C_CR2_RELOAD : 0) |
+			(out_bytes || xfer_start ? STM32_I2C_CR2_START : 0);
 
 		for (i = 0; i < in_bytes; i++) {
 			/* Wait for receive buffer not empty */
@@ -402,7 +402,7 @@ int i2c_raw_get_sda(int port)
 int i2c_get_line_levels(int port)
 {
 	return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) |
-		(i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
+	       (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
 }
 
 /*****************************************************************************/
diff --git a/chip/stm32/i2c-stm32l.c b/chip/stm32/i2c-stm32l.c
index 74ecff192d..f18374281a 100644
--- a/chip/stm32/i2c-stm32l.c
+++ b/chip/stm32/i2c-stm32l.c
@@ -1,8 +1,9 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "builtin/assert.h"
 #include "chipset.h"
 #include "clock.h"
 #include "common.h"
@@ -19,7 +20,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
 
 #define I2C_ERROR_FAILED_START EC_ERROR_INTERNAL_FIRST
 
@@ -35,23 +36,20 @@
  * flips out.  The battery may flip out and hold lines low for up to
  * 25ms.  If we just wait it will eventually let them go.
  */
-#define I2C_TX_TIMEOUT_MASTER	(30 * MSEC)
+#define I2C_TX_TIMEOUT_MASTER (30 * MSEC)
 
 /*
  * Delay 5us in bitbang mode.  That gives us roughly 5us low and 5us high or
  * a frequency of 100kHz.
  */
-#define I2C_BITBANG_HALF_CYCLE_US    5
+#define I2C_BITBANG_HALF_CYCLE_US 5
 
 #ifdef CONFIG_I2C_DEBUG
 static void dump_i2c_reg(int port, const char *what)
 {
 	CPRINTS("i2c CR1=%04x CR2=%04x SR1=%04x SR2=%04x %s",
-		STM32_I2C_CR1(port),
-		STM32_I2C_CR2(port),
-		STM32_I2C_SR1(port),
-		STM32_I2C_SR2(port),
-		what);
+		STM32_I2C_CR1(port), STM32_I2C_CR2(port), STM32_I2C_SR1(port),
+		STM32_I2C_SR2(port), what);
 }
 #else
 static inline void dump_i2c_reg(int port, const char *what)
@@ -164,10 +162,8 @@ static void i2c_init_port(const struct i2c_port_t *p)
 /*****************************************************************************/
 /* Interface */
 
-int chip_i2c_xfer(const int port,
-		  const uint16_t addr_flags,
-		  const uint8_t *out, int out_bytes,
-		  uint8_t *in, int in_bytes, int flags)
+int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out,
+		  int out_bytes, uint8_t *in, int in_bytes, int flags)
 {
 	int addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1;
 	int started = (flags & I2C_XFER_START) ? 0 : 1;
@@ -188,10 +184,8 @@ int chip_i2c_xfer(const int port,
 	STM32_I2C_SR1(port) = 0;
 
 	/* Clear start, stop, POS, ACK bits to get us in a known state */
-	STM32_I2C_CR1(port) &= ~(STM32_I2C_CR1_START |
-				 STM32_I2C_CR1_STOP |
-				 STM32_I2C_CR1_POS |
-				 STM32_I2C_CR1_ACK);
+	STM32_I2C_CR1(port) &= ~(STM32_I2C_CR1_START | STM32_I2C_CR1_STOP |
+				 STM32_I2C_CR1_POS | STM32_I2C_CR1_ACK);
 
 	/* No out bytes and no in bytes means just check for active */
 	if (out_bytes || !in_bytes) {
@@ -291,7 +285,7 @@ int chip_i2c_xfer(const int port,
 		}
 	}
 
- xfer_exit:
+xfer_exit:
 	/* On error, queue a stop condition */
 	if (rv) {
 		flags |= I2C_XFER_STOP;
@@ -305,7 +299,8 @@ int chip_i2c_xfer(const int port,
 		if (rv == I2C_ERROR_FAILED_START) {
 			const struct i2c_port_t *p = i2c_ports;
 			CPRINTS("chip_i2c_xfer start error; "
-				"unwedging and resetting i2c %d", port);
+				"unwedging and resetting i2c %d",
+				port);
 
 			i2c_unwedge(port);
 
@@ -363,7 +358,7 @@ int i2c_raw_get_sda(int port)
 int i2c_get_line_levels(int port)
 {
 	return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) |
-		(i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
+	       (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
 }
 
 /*****************************************************************************/
@@ -414,11 +409,9 @@ void i2c_init(void)
 /*****************************************************************************/
 /* Console commands */
 
-static int command_i2cdump(int argc, char **argv)
+static int command_i2cdump(int argc, const char **argv)
 {
 	dump_i2c_reg(I2C_PORT_MASTER, "dump");
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(i2cdump, command_i2cdump,
-			NULL,
-			"Dump I2C regs");
+DECLARE_CONSOLE_COMMAND(i2cdump, command_i2cdump, NULL, "Dump I2C regs");
diff --git a/chip/stm32/i2c-stm32l4.c b/chip/stm32/i2c-stm32l4.c
index f7d311ba87..eeb87ec4e0 100644
--- a/chip/stm32/i2c-stm32l4.c
+++ b/chip/stm32/i2c-stm32l4.c
@@ -1,8 +1,9 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "builtin/assert.h"
 #include "printf.h"
 #include "chipset.h"
 #include "clock.h"
@@ -21,13 +22,13 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
 
 /* Transmit timeout in microseconds */
-#define I2C_TX_TIMEOUT_MASTER	(10 * MSEC)
+#define I2C_TX_TIMEOUT_MASTER (10 * MSEC)
 
 #ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
-#define I2C_SLAVE_ERROR_CODE	0xec
+#define I2C_SLAVE_ERROR_CODE 0xec
 #if (I2C_PORT_EC == STM32_I2C1_PORT)
 #define IRQ_SLAVE STM32_IRQ_I2C1
 #else
@@ -37,8 +38,8 @@
 
 /* I2C port state data */
 struct i2c_port_data {
-	uint32_t timeout_us;    /* Transaction timeout, or 0 to use default */
-	enum i2c_freq freq;	/* Port clock speed */
+	uint32_t timeout_us; /* Transaction timeout, or 0 to use default */
+	enum i2c_freq freq; /* Port clock speed */
 };
 static struct i2c_port_data pdata[I2C_PORT_COUNT];
 
@@ -50,8 +51,8 @@ void i2c_set_timeout(int port, uint32_t timeout)
 /* timing register values for supported input clks / i2c clk rates */
 static const uint32_t busyloop_us[I2C_FREQ_COUNT] = {
 	[I2C_FREQ_1000KHZ] = 16, /* Enough for 2 bytes */
-	[I2C_FREQ_400KHZ] = 40,  /* Enough for 2 bytes */
-	[I2C_FREQ_100KHZ] = 0,   /* No busy looping at 100kHz (bus is slow) */
+	[I2C_FREQ_400KHZ] = 40, /* Enough for 2 bytes */
+	[I2C_FREQ_100KHZ] = 0, /* No busy looping at 100kHz (bus is slow) */
 };
 
 /**
@@ -70,7 +71,7 @@ static int wait_isr(int port, int mask)
 
 		/* Check for errors */
 		if (isr & (STM32_I2C_ISR_ARLO | STM32_I2C_ISR_BERR |
-			STM32_I2C_ISR_NACK))
+			   STM32_I2C_ISR_NACK))
 			return EC_ERROR_UNKNOWN;
 
 		/* Check for desired mask */
@@ -115,8 +116,7 @@ static const uint32_t timingr_regs[I2C_CLK_SRC_COUNT][I2C_FREQ_COUNT] = {
 };
 
 static void i2c_set_freq_port(const struct i2c_port_t *p,
-			      enum stm32_i2c_clk_src src,
-			      enum i2c_freq freq)
+			      enum stm32_i2c_clk_src src, enum i2c_freq freq)
 {
 	int port = p->port;
 
@@ -209,8 +209,8 @@ static void i2c_event_handler(int port)
 		STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE;
 
 		/* Clear error status bits */
-		STM32_I2C_ICR(port) |= STM32_I2C_ICR_BERRCF
-				| STM32_I2C_ICR_ARLOCF;
+		STM32_I2C_ICR(port) |= STM32_I2C_ICR_BERRCF |
+				       STM32_I2C_ICR_ARLOCF;
 	}
 
 	/* Transfer matched our slave address */
@@ -286,8 +286,8 @@ static void i2c_event_handler(int port)
 					STM32_I2C_TXDR(port) =
 						slave_buffer[tx_idx++];
 				} else {
-					STM32_I2C_TXDR(port)
-						= I2C_SLAVE_ERROR_CODE;
+					STM32_I2C_TXDR(port) =
+						I2C_SLAVE_ERROR_CODE;
 					tx_idx = 0;
 					tx_end = 0;
 					tx_pending = 0;
@@ -309,9 +309,8 @@ DECLARE_IRQ(IRQ_SLAVE, i2c_event_interrupt, 2);
 /*****************************************************************************/
 /* Interface */
 
-int chip_i2c_xfer(const int port, const uint16_t addr_flags,
-		  const uint8_t *out, int out_bytes,
-		  uint8_t *in, int in_bytes, int flags)
+int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out,
+		  int out_bytes, uint8_t *in, int in_bytes, int flags)
 {
 	int addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1;
 	int rv = EC_SUCCESS;
@@ -335,13 +334,13 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags,
 		 * if we are not stopping, set RELOAD bit so that we can load
 		 * NBYTES again. if we are starting, then set START bit.
 		 */
-		STM32_I2C_CR2(port) =  ((out_bytes & 0xFF) << 16)
-			| addr_8bit
-			| ((in_bytes == 0 && xfer_stop) ?
-				STM32_I2C_CR2_AUTOEND : 0)
-			| ((in_bytes == 0 && !xfer_stop) ?
-				STM32_I2C_CR2_RELOAD : 0)
-			| (xfer_start ? STM32_I2C_CR2_START : 0);
+		STM32_I2C_CR2(port) =
+			((out_bytes & 0xFF) << 16) | addr_8bit |
+			((in_bytes == 0 && xfer_stop) ? STM32_I2C_CR2_AUTOEND :
+							0) |
+			((in_bytes == 0 && !xfer_stop) ? STM32_I2C_CR2_RELOAD :
+							 0) |
+			(xfer_start ? STM32_I2C_CR2_START : 0);
 
 		for (i = 0; i < out_bytes; i++) {
 			rv = wait_isr(port, STM32_I2C_ISR_TXIS);
@@ -364,11 +363,11 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags,
 		 * NBYTES again. if we were just transmitting, we need to
 		 * set START bit to send (re)start and begin read transaction.
 		 */
-		STM32_I2C_CR2(port) = ((in_bytes & 0xFF) << 16)
-			| STM32_I2C_CR2_RD_WRN | addr_8bit
-			| (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0)
-			| (!xfer_stop ? STM32_I2C_CR2_RELOAD : 0)
-			| (out_bytes || xfer_start ? STM32_I2C_CR2_START : 0);
+		STM32_I2C_CR2(port) =
+			((in_bytes & 0xFF) << 16) | STM32_I2C_CR2_RD_WRN |
+			addr_8bit | (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0) |
+			(!xfer_stop ? STM32_I2C_CR2_RELOAD : 0) |
+			(out_bytes || xfer_start ? STM32_I2C_CR2_START : 0);
 
 		for (i = 0; i < in_bytes; i++) {
 			/* Wait for receive buffer not empty */
@@ -448,7 +447,7 @@ int i2c_raw_get_sda(int port)
 int i2c_get_line_levels(int port)
 {
 	return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) |
-		(i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
+	       (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
 }
 
 void i2c_init(void)
@@ -460,11 +459,12 @@ void i2c_init(void)
 		i2c_init_port(p);
 
 #ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS
-	STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_RXIE | STM32_I2C_CR1_ERRIE
-			| STM32_I2C_CR1_ADDRIE | STM32_I2C_CR1_STOPIE
-			| STM32_I2C_CR1_NACKIE;
-	STM32_I2C_OAR1(I2C_PORT_EC) = 0x8000
-		| (I2C_STRIP_FLAGS(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) << 1);
+	STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_RXIE | STM32_I2C_CR1_ERRIE |
+				      STM32_I2C_CR1_ADDRIE |
+				      STM32_I2C_CR1_STOPIE |
+				      STM32_I2C_CR1_NACKIE;
+	STM32_I2C_OAR1(I2C_PORT_EC) =
+		0x8000 | (I2C_STRIP_FLAGS(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) << 1);
 	task_enable_irq(IRQ_SLAVE);
 #endif
 }
diff --git a/chip/stm32/i2c-stm32l5.c b/chip/stm32/i2c-stm32l5.c
index 86cc1c6df2..3c7cb170bc 100644
--- a/chip/stm32/i2c-stm32l5.c
+++ b/chip/stm32/i2c-stm32l5.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/stm32/i2c_ite_flash_support.c b/chip/stm32/i2c_ite_flash_support.c
index 916a8c364c..8482065086 100644
--- a/chip/stm32/i2c_ite_flash_support.c
+++ b/chip/stm32/i2c_ite_flash_support.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -33,10 +33,10 @@
  * (1<<9)-6 reads, leaving 6012 bytes of RAM available, down from 7356 bytes of
  * RAM available with the default 60 byte limits.
  */
-#if CONFIG_USB_I2C_MAX_WRITE_COUNT != ((1<<9) - 4)
+#if CONFIG_USB_I2C_MAX_WRITE_COUNT != ((1 << 9) - 4)
 #error Must set CONFIG_USB_I2C_MAX_WRITE_COUNT to ((1<<9) - 4)
 #endif
-#if CONFIG_USB_I2C_MAX_READ_COUNT != ((1<<9) - 6)
+#if CONFIG_USB_I2C_MAX_READ_COUNT != ((1 << 9) - 6)
 #error Must set CONFIG_USB_I2C_MAX_WRITE_COUNT to ((1<<9) - 6)
 #endif
 
@@ -97,16 +97,15 @@ static int ite_i2c_read_register(uint8_t register_offset, uint8_t *output)
 	int ret;
 	/* Tell the ITE EC which register we want to read. */
 	ret = i2c_xfer_unlocked(ite_dfu_config.i2c_port,
-				ITE_DFU_I2C_CMD_ADDR_FLAGS,
-				&register_offset, sizeof(register_offset),
-				NULL, 0, I2C_XFER_SINGLE);
+				ITE_DFU_I2C_CMD_ADDR_FLAGS, &register_offset,
+				sizeof(register_offset), NULL, 0,
+				I2C_XFER_SINGLE);
 	if (ret != EC_SUCCESS)
 		return ret;
 	/* Read in the 1 byte register value. */
 	ret = i2c_xfer_unlocked(ite_dfu_config.i2c_port,
-				ITE_DFU_I2C_DATA_ADDR_FLAGS,
-				NULL, 0,
-				output, sizeof(*output), I2C_XFER_SINGLE);
+				ITE_DFU_I2C_DATA_ADDR_FLAGS, NULL, 0, output,
+				sizeof(*output), I2C_XFER_SINGLE);
 	return ret;
 }
 
@@ -212,7 +211,7 @@ unlock:
 	}
 
 	ccprintf("ITE EC info: CHIPID1=0x%02X CHIPID2=0x%02X CHIPVER=0x%02X ",
-		chipid1[0], chipid2[0], chipver[0]);
+		 chipid1[0], chipid2[0], chipver[0]);
 	ccprintf("version=%d flash_bytes=%d\n", chip_version, flash_kb << 10);
 
 	/*
@@ -226,7 +225,7 @@ unlock:
 }
 
 /* Enable ITE direct firmware update (DFU) mode. */
-static int command_enable_ite_dfu(int argc, char **argv)
+static int command_enable_ite_dfu(int argc, const char **argv)
 {
 	if (argc > 1)
 		return EC_ERROR_PARAM_COUNT;
@@ -236,8 +235,8 @@ static int command_enable_ite_dfu(int argc, char **argv)
 		return EC_ERROR_ACCESS_DENIED;
 
 	/* Enable peripheral clocks. */
-	STM32_RCC_APB2ENR |=
-		STM32_RCC_APB2ENR_TIM16EN | STM32_RCC_APB2ENR_TIM17EN;
+	STM32_RCC_APB2ENR |= STM32_RCC_APB2ENR_TIM16EN |
+			     STM32_RCC_APB2ENR_TIM17EN;
 
 	/* Reset timer registers which are not otherwise set below. */
 	STM32_TIM_CR2(16) = 0x0000;
@@ -265,10 +264,10 @@ static int command_enable_ite_dfu(int argc, char **argv)
 	STM32_TIM_ARR(17) = (MHz / SMDAT_WAVEFORM_PERIOD_HZ) - 1;
 
 	/* Set output compare 1 mode to PWM mode 1 and enable preload. */
-	STM32_TIM_CCMR1(16) =
-		STM32_TIM_CCMR1_OC1M_PWM_MODE_1 | STM32_TIM_CCMR1_OC1PE;
-	STM32_TIM_CCMR1(17) =
-		STM32_TIM_CCMR1_OC1M_PWM_MODE_1 | STM32_TIM_CCMR1_OC1PE;
+	STM32_TIM_CCMR1(16) = STM32_TIM_CCMR1_OC1M_PWM_MODE_1 |
+			      STM32_TIM_CCMR1_OC1PE;
+	STM32_TIM_CCMR1(17) = STM32_TIM_CCMR1_OC1M_PWM_MODE_1 |
+			      STM32_TIM_CCMR1_OC1PE;
 
 	/*
 	 * Enable output compare 1 (or its N counterpart). Note that if only
@@ -335,12 +334,11 @@ static int command_enable_ite_dfu(int argc, char **argv)
 
 	return cprint_ite_chip_id();
 }
-DECLARE_CONSOLE_COMMAND(
-	enable_ite_dfu, command_enable_ite_dfu, "",
-	"Enable ITE Direct Firmware Update (DFU) mode");
+DECLARE_CONSOLE_COMMAND(enable_ite_dfu, command_enable_ite_dfu, "",
+			"Enable ITE Direct Firmware Update (DFU) mode");
 
 /* Read ITE chip ID.  Can be used to verify ITE DFU mode. */
-static int command_get_ite_chipid(int argc, char **argv)
+static int command_get_ite_chipid(int argc, const char **argv)
 {
 	if (argc > 1)
 		return EC_ERROR_PARAM_COUNT;
diff --git a/chip/stm32/keyboard_raw.c b/chip/stm32/keyboard_raw.c
index 219676968a..c3244c19f7 100644
--- a/chip/stm32/keyboard_raw.c
+++ b/chip/stm32/keyboard_raw.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -86,12 +86,12 @@ test_mockable void keyboard_raw_drive_column(int out)
 			}
 		}
 
-	#ifdef CONFIG_KEYBOARD_COL2_INVERTED
+#ifdef CONFIG_KEYBOARD_COL2_INVERTED
 		if (bsrr & (gpio_list[GPIO_KB_OUT02].mask << 16 |
-				 gpio_list[GPIO_KB_OUT02].mask))
+			    gpio_list[GPIO_KB_OUT02].mask))
 			bsrr ^= (gpio_list[GPIO_KB_OUT02].mask << 16 |
 				 gpio_list[GPIO_KB_OUT02].mask);
-	#endif
+#endif
 
 		if (bsrr)
 			STM32_GPIO_BSRR(kb_out_ports[i]) = bsrr;
@@ -131,9 +131,9 @@ void keyboard_raw_enable_interrupt(int enable)
 		 * Clear them before enable interrupt.
 		 */
 		STM32_EXTI_PR |= irq_mask;
-		STM32_EXTI_IMR |= irq_mask;	/* 1: unmask interrupt */
+		STM32_EXTI_IMR |= irq_mask; /* 1: unmask interrupt */
 	} else {
-		STM32_EXTI_IMR &= ~irq_mask;	/* 0: mask interrupts */
+		STM32_EXTI_IMR &= ~irq_mask; /* 0: mask interrupts */
 	}
 }
 
diff --git a/chip/stm32/memory_regions.inc b/chip/stm32/memory_regions.inc
index 2381c511f2..8c8e666f71 100644
--- a/chip/stm32/memory_regions.inc
+++ b/chip/stm32/memory_regions.inc
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/stm32/otp-stm32f4.c b/chip/stm32/otp-stm32f4.c
index 45ce38d159..ff6280ed20 100644
--- a/chip/stm32/otp-stm32f4.c
+++ b/chip/stm32/otp-stm32f4.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,8 +18,7 @@
 #ifdef CONFIG_SERIALNO_LEN
 /* Which block to use */
 #define OTP_SERIAL_BLOCK 0
-#define OTP_SERIAL_ADDR \
-	REG32_ADDR(STM32_OTP_BLOCK_DATA(OTP_SERIAL_BLOCK, 0))
+#define OTP_SERIAL_ADDR REG32_ADDR(STM32_OTP_BLOCK_DATA(OTP_SERIAL_BLOCK, 0))
 
 /* Number of word used in the block */
 #define OTP_SERIAL_BLOCK_SIZE (CONFIG_SERIALNO_LEN / sizeof(uint32_t))
@@ -40,7 +39,7 @@ static int otp_write(uint8_t block, int size, const char *data)
 	if (size >= STM32_OTP_BLOCK_SIZE)
 		return EC_ERROR_PARAM2;
 	return crec_flash_physical_write(STM32_OTP_BLOCK_DATA(block, 0) -
-					 CONFIG_PROGRAM_MEMORY_BASE,
+						 CONFIG_PROGRAM_MEMORY_BASE,
 					 size * sizeof(uint32_t), data);
 }
 
@@ -74,7 +73,7 @@ static int otp_set_protect(uint8_t block)
 	lock = REG32(STM32_OTP_LOCK(block));
 	lock &= ~STM32_OPT_LOCK_MASK(block);
 	rv = crec_flash_physical_write(STM32_OTP_LOCK(block) -
-				       CONFIG_PROGRAM_MEMORY_BASE,
+					       CONFIG_PROGRAM_MEMORY_BASE,
 				       sizeof(uint32_t), (char *)&lock);
 	if (rv)
 		return rv;
diff --git a/chip/stm32/power_led.c b/chip/stm32/power_led.c
index 508745199f..579925fff9 100644
--- a/chip/stm32/power_led.c
+++ b/chip/stm32/power_led.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,6 +15,7 @@
  * results in a breathing effect. It takes about 2sec for a full cycle.
  */
 
+#include "builtin/assert.h"
 #include "clock.h"
 #include "console.h"
 #include "gpio.h"
@@ -28,9 +29,9 @@
 #include "timer.h"
 #include "util.h"
 
-#define LED_STATE_TIMEOUT_MIN	(15 * MSEC)  /* Minimum of 15ms per step */
-#define LED_HOLD_TIME		(330 * MSEC) /* Hold for 330ms at min/max */
-#define LED_STEP_PERCENT	4	/* Incremental value of each step */
+#define LED_STATE_TIMEOUT_MIN (15 * MSEC) /* Minimum of 15ms per step */
+#define LED_HOLD_TIME (330 * MSEC) /* Hold for 330ms at min/max */
+#define LED_STEP_PERCENT 4 /* Incremental value of each step */
 
 static enum powerled_state led_state = POWERLED_STATE_ON;
 static int power_led_percent = 100;
@@ -86,7 +87,8 @@ static int power_led_step(void)
 		 * Decreases timeout as duty cycle percentage approaches
 		 * 0%, increase as it approaches 100%.
 		 */
-		state_timeout = LED_STATE_TIMEOUT_MIN +
+		state_timeout =
+			LED_STATE_TIMEOUT_MIN +
 			LED_STATE_TIMEOUT_MIN * (power_led_percent / 33);
 	}
 
@@ -137,7 +139,7 @@ void power_led_task(void)
 
 #define CONFIG_CMD_POWERLED
 #ifdef CONFIG_CMD_POWERLED
-static int command_powerled(int argc, char **argv)
+static int command_powerled(int argc, const char **argv)
 {
 	enum powerled_state state;
 
@@ -156,7 +158,6 @@ static int command_powerled(int argc, char **argv)
 	powerled_set_state(state);
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(powerled, command_powerled,
-		"[off | on | suspend]",
-		"Change power LED state");
+DECLARE_CONSOLE_COMMAND(powerled, command_powerled, "[off | on | suspend]",
+			"Change power LED state");
 #endif
diff --git a/chip/stm32/pwm.c b/chip/stm32/pwm.c
index aadbde08c2..0f2e50c999 100644
--- a/chip/stm32/pwm.c
+++ b/chip/stm32/pwm.c
@@ -1,10 +1,11 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* PWM control module for STM32 */
 
+#include "builtin/assert.h"
 #include "clock.h"
 #include "clock-f.h"
 #include "gpio.h"
diff --git a/chip/stm32/pwm_chip.h b/chip/stm32/pwm_chip.h
index baa793090a..7269072ac2 100644
--- a/chip/stm32/pwm_chip.h
+++ b/chip/stm32/pwm_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -29,7 +29,10 @@ struct pwm_t {
 extern const struct pwm_t pwm_channels[];
 
 /* Macro to fill in both timer ID and register base */
-#define STM32_TIM(x) {x, STM32_TIM_BASE(x)}
+#define STM32_TIM(x)                 \
+	{                            \
+		x, STM32_TIM_BASE(x) \
+	}
 
 /* Plain ID mapping for readability */
 #define STM32_TIM_CH(x) (x)
diff --git a/chip/stm32/registers-stm32f0.h b/chip/stm32/registers-stm32f0.h
index ee4963777b..645ed5048e 100644
--- a/chip/stm32/registers-stm32f0.h
+++ b/chip/stm32/registers-stm32f0.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,407 +23,402 @@
 #endif
 
 /* --- IRQ numbers --- */
-#define STM32_IRQ_WWDG             0
-#define STM32_IRQ_PVD              1
-#define STM32_IRQ_RTC_WAKEUP       2
-#define STM32_IRQ_RTC_ALARM        2
-#define STM32_IRQ_FLASH            3
-#define STM32_IRQ_RCC              4
-#define STM32_IRQ_EXTI0_1          5
-#define STM32_IRQ_EXTI2_3          6
-#define STM32_IRQ_EXTI4_15         7
-#define STM32_IRQ_TSC              8
-#define STM32_IRQ_DMA_CHANNEL_1    9
+#define STM32_IRQ_WWDG 0
+#define STM32_IRQ_PVD 1
+#define STM32_IRQ_RTC_WAKEUP 2
+#define STM32_IRQ_RTC_ALARM 2
+#define STM32_IRQ_FLASH 3
+#define STM32_IRQ_RCC 4
+#define STM32_IRQ_EXTI0_1 5
+#define STM32_IRQ_EXTI2_3 6
+#define STM32_IRQ_EXTI4_15 7
+#define STM32_IRQ_TSC 8
+#define STM32_IRQ_DMA_CHANNEL_1 9
 #define STM32_IRQ_DMA_CHANNEL_2_3 10
 #define STM32_IRQ_DMA_CHANNEL_4_7 11
-#define STM32_IRQ_ADC_COMP        12
+#define STM32_IRQ_ADC_COMP 12
 #define STM32_IRQ_TIM1_BRK_UP_TRG 13
-#define STM32_IRQ_TIM1_CC         14
-#define STM32_IRQ_TIM2            15
-#define STM32_IRQ_TIM3            16
-#define STM32_IRQ_TIM6_DAC        17
-#define STM32_IRQ_TIM7            18
-#define STM32_IRQ_TIM14           19
-#define STM32_IRQ_TIM15           20
-#define STM32_IRQ_TIM16           21
-#define STM32_IRQ_TIM17           22
-#define STM32_IRQ_I2C1            23
-#define STM32_IRQ_I2C2            24
-#define STM32_IRQ_SPI1            25
-#define STM32_IRQ_SPI2            26
-#define STM32_IRQ_USART1          27
-#define STM32_IRQ_USART2          28
-#define STM32_IRQ_USART3_4        29
-#define STM32_IRQ_CEC_CAN         30
-#define STM32_IRQ_USB             31
+#define STM32_IRQ_TIM1_CC 14
+#define STM32_IRQ_TIM2 15
+#define STM32_IRQ_TIM3 16
+#define STM32_IRQ_TIM6_DAC 17
+#define STM32_IRQ_TIM7 18
+#define STM32_IRQ_TIM14 19
+#define STM32_IRQ_TIM15 20
+#define STM32_IRQ_TIM16 21
+#define STM32_IRQ_TIM17 22
+#define STM32_IRQ_I2C1 23
+#define STM32_IRQ_I2C2 24
+#define STM32_IRQ_SPI1 25
+#define STM32_IRQ_SPI2 26
+#define STM32_IRQ_USART1 27
+#define STM32_IRQ_USART2 28
+#define STM32_IRQ_USART3_4 29
+#define STM32_IRQ_CEC_CAN 30
+#define STM32_IRQ_USB 31
 /* aliases for easier code sharing */
 #define STM32_IRQ_COMP STM32_IRQ_ADC_COMP
 #define STM32_IRQ_USB_LP STM32_IRQ_USB
 
-
-
 /* Peripheral base addresses */
-#define STM32_ADC1_BASE             0x40012400
-#define STM32_ADC_BASE              0x40012700 /* STM32L15X only */
+#define STM32_ADC1_BASE 0x40012400
+#define STM32_ADC_BASE 0x40012700 /* STM32L15X only */
 
-#define STM32_CEC_BASE              0x40007800 /* STM32F373 */
-#define STM32_CRC_BASE              0x40023000
-#define STM32_CRS_BASE              0x40006c00 /* STM32F0XX */
-#define STM32_DAC_BASE              0x40007400
+#define STM32_CEC_BASE 0x40007800 /* STM32F373 */
+#define STM32_CRC_BASE 0x40023000
+#define STM32_CRS_BASE 0x40006c00 /* STM32F0XX */
+#define STM32_DAC_BASE 0x40007400
 
-#define STM32_COMP_BASE             0x40010000
+#define STM32_COMP_BASE 0x40010000
 
-#define STM32_DBGMCU_BASE           0x40015800
+#define STM32_DBGMCU_BASE 0x40015800
 
-#define STM32_DMA1_BASE             0x40020000
-#define STM32_DMA2_BASE             0x40020400
+#define STM32_DMA1_BASE 0x40020000
+#define STM32_DMA2_BASE 0x40020400
 
-#define STM32_EXTI_BASE             0x40010400
+#define STM32_EXTI_BASE 0x40010400
 
-#define STM32_FLASH_REGS_BASE       0x40022000
+#define STM32_FLASH_REGS_BASE 0x40022000
 
-#define STM32_GPIOA_BASE            0x48000000
-#define STM32_GPIOB_BASE            0x48000400
-#define STM32_GPIOC_BASE            0x48000800
-#define STM32_GPIOD_BASE            0x48000C00
-#define STM32_GPIOE_BASE            0x48001000
-#define STM32_GPIOF_BASE            0x48001400
-#define STM32_GPIOG_BASE            0x48001800 /* only for stm32l4x6 */
-#define STM32_GPIOH_BASE            0x48001C00 /* only for stm32l4 */
+#define STM32_GPIOA_BASE 0x48000000
+#define STM32_GPIOB_BASE 0x48000400
+#define STM32_GPIOC_BASE 0x48000800
+#define STM32_GPIOD_BASE 0x48000C00
+#define STM32_GPIOE_BASE 0x48001000
+#define STM32_GPIOF_BASE 0x48001400
+#define STM32_GPIOG_BASE 0x48001800 /* only for stm32l4x6 */
+#define STM32_GPIOH_BASE 0x48001C00 /* only for stm32l4 */
 
-#define STM32_I2C1_BASE             0x40005400
-#define STM32_I2C2_BASE             0x40005800
-#define STM32_I2C3_BASE             0x40005C00
-#define STM32_I2C4_BASE             0x40006000
+#define STM32_I2C1_BASE 0x40005400
+#define STM32_I2C2_BASE 0x40005800
+#define STM32_I2C3_BASE 0x40005C00
+#define STM32_I2C4_BASE 0x40006000
 
-#define STM32_IWDG_BASE             0x40003000
-#define STM32_LCD_BASE              0x40002400
+#define STM32_IWDG_BASE 0x40003000
+#define STM32_LCD_BASE 0x40002400
 
-#define STM32_OPTB_BASE             0x1FFFF800
+#define STM32_OPTB_BASE 0x1FFFF800
 
-#define STM32_PMSE_BASE             0x40013400
-#define STM32_PWR_BASE              0x40007000
+#define STM32_PMSE_BASE 0x40013400
+#define STM32_PWR_BASE 0x40007000
 
-#define STM32_RCC_BASE              0x40021000
+#define STM32_RCC_BASE 0x40021000
 
-#define STM32_RI_BASE               0x40007C00 /* STM32L1xx only */
-#define STM32_RNG_BASE              0x50060800 /* STM32L4 */
-#define STM32_RTC_BASE              0x40002800
+#define STM32_RI_BASE 0x40007C00 /* STM32L1xx only */
+#define STM32_RNG_BASE 0x50060800 /* STM32L4 */
+#define STM32_RTC_BASE 0x40002800
 
-#define STM32_SPI1_BASE             0x40013000
-#define STM32_SPI2_BASE             0x40003800
-#define STM32_SPI3_BASE             0x40003c00 /* STM32F373, STM32L4, STM32F7 */
+#define STM32_SPI1_BASE 0x40013000
+#define STM32_SPI2_BASE 0x40003800
+#define STM32_SPI3_BASE 0x40003c00 /* STM32F373, STM32L4, STM32F7 */
 
-#define STM32_SYSCFG_BASE           0x40010000
+#define STM32_SYSCFG_BASE 0x40010000
 
-#define STM32_TIM1_BASE             0x40012c00 /* STM32F373 */
-#define STM32_TIM2_BASE             0x40000000
-#define STM32_TIM3_BASE             0x40000400
-#define STM32_TIM4_BASE             0x40000800
-#define STM32_TIM5_BASE             0x40000c00 /* STM32F373 */
-#define STM32_TIM6_BASE             0x40001000
-#define STM32_TIM7_BASE             0x40001400
-#define STM32_TIM12_BASE            0x40001800 /* STM32F373 */
-#define STM32_TIM13_BASE            0x40001c00 /* STM32F373 */
-#define STM32_TIM14_BASE            0x40002000 /* STM32F373 */
-#define STM32_TIM15_BASE            0x40014000
-#define STM32_TIM16_BASE            0x40014400
-#define STM32_TIM17_BASE            0x40014800
-#define STM32_TIM18_BASE            0x40009c00 /* STM32F373 only */
-#define STM32_TIM19_BASE            0x40015c00 /* STM32F373 only */
+#define STM32_TIM1_BASE 0x40012c00 /* STM32F373 */
+#define STM32_TIM2_BASE 0x40000000
+#define STM32_TIM3_BASE 0x40000400
+#define STM32_TIM4_BASE 0x40000800
+#define STM32_TIM5_BASE 0x40000c00 /* STM32F373 */
+#define STM32_TIM6_BASE 0x40001000
+#define STM32_TIM7_BASE 0x40001400
+#define STM32_TIM12_BASE 0x40001800 /* STM32F373 */
+#define STM32_TIM13_BASE 0x40001c00 /* STM32F373 */
+#define STM32_TIM14_BASE 0x40002000 /* STM32F373 */
+#define STM32_TIM15_BASE 0x40014000
+#define STM32_TIM16_BASE 0x40014400
+#define STM32_TIM17_BASE 0x40014800
+#define STM32_TIM18_BASE 0x40009c00 /* STM32F373 only */
+#define STM32_TIM19_BASE 0x40015c00 /* STM32F373 only */
 
-#define STM32_UNIQUE_ID_BASE        0x1ffff7ac
+#define STM32_UNIQUE_ID_BASE 0x1ffff7ac
 
-#define STM32_USART1_BASE           0x40013800
-#define STM32_USART2_BASE           0x40004400
-#define STM32_USART3_BASE           0x40004800
-#define STM32_USART4_BASE           0x40004c00
-#define STM32_USART9_BASE           0x40008000 /* LPUART */
+#define STM32_USART1_BASE 0x40013800
+#define STM32_USART2_BASE 0x40004400
+#define STM32_USART3_BASE 0x40004800
+#define STM32_USART4_BASE 0x40004c00
+#define STM32_USART9_BASE 0x40008000 /* LPUART */
 
-#define STM32_USB_CAN_SRAM_BASE     0x40006000
-#define STM32_USB_FS_BASE           0x40005C00
-
-#define STM32_WWDG_BASE             0x40002C00
+#define STM32_USB_CAN_SRAM_BASE 0x40006000
+#define STM32_USB_FS_BASE 0x40005C00
 
+#define STM32_WWDG_BASE 0x40002C00
 
 #ifndef __ASSEMBLER__
 
 /* Register definitions */
 
 /* --- USART --- */
-#define STM32_USART_CR1(base)      STM32_USART_REG(base, 0x00)
-#define STM32_USART_CR1_UE		BIT(0)
-#define STM32_USART_CR1_UESM            BIT(1)
-#define STM32_USART_CR1_RE		BIT(2)
-#define STM32_USART_CR1_TE		BIT(3)
-#define STM32_USART_CR1_RXNEIE		BIT(5)
-#define STM32_USART_CR1_TCIE		BIT(6)
-#define STM32_USART_CR1_TXEIE		BIT(7)
-#define STM32_USART_CR1_PS		BIT(9)
-#define STM32_USART_CR1_PCE		BIT(10)
-#define STM32_USART_CR1_M		BIT(12)
-#define STM32_USART_CR1_OVER8		BIT(15)
-#define STM32_USART_CR2(base)      STM32_USART_REG(base, 0x04)
-#define STM32_USART_CR2_SWAP		BIT(15)
-#define STM32_USART_CR3(base)      STM32_USART_REG(base, 0x08)
-#define STM32_USART_CR3_EIE		BIT(0)
-#define STM32_USART_CR3_DMAR		BIT(6)
-#define STM32_USART_CR3_DMAT		BIT(7)
-#define STM32_USART_CR3_ONEBIT		BIT(11)
-#define STM32_USART_CR3_OVRDIS		BIT(12)
-#define STM32_USART_CR3_WUS_START_BIT	(2 << 20)
-#define STM32_USART_CR3_WUFIE		BIT(22)
-#define STM32_USART_BRR(base)      STM32_USART_REG(base, 0x0C)
-#define STM32_USART_GTPR(base)     STM32_USART_REG(base, 0x10)
-#define STM32_USART_RTOR(base)     STM32_USART_REG(base, 0x14)
-#define STM32_USART_RQR(base)      STM32_USART_REG(base, 0x18)
-#define STM32_USART_ISR(base)      STM32_USART_REG(base, 0x1C)
-#define STM32_USART_ICR(base)      STM32_USART_REG(base, 0x20)
-#define STM32_USART_ICR_ORECF		BIT(3)
-#define STM32_USART_ICR_TCCF		BIT(6)
-#define STM32_USART_RDR(base)      STM32_USART_REG(base, 0x24)
-#define STM32_USART_TDR(base)      STM32_USART_REG(base, 0x28)
-#define STM32_USART_PRESC(base)    STM32_USART_REG(base, 0x2C)
+#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00)
+#define STM32_USART_CR1_UE BIT(0)
+#define STM32_USART_CR1_UESM BIT(1)
+#define STM32_USART_CR1_RE BIT(2)
+#define STM32_USART_CR1_TE BIT(3)
+#define STM32_USART_CR1_RXNEIE BIT(5)
+#define STM32_USART_CR1_TCIE BIT(6)
+#define STM32_USART_CR1_TXEIE BIT(7)
+#define STM32_USART_CR1_PS BIT(9)
+#define STM32_USART_CR1_PCE BIT(10)
+#define STM32_USART_CR1_M BIT(12)
+#define STM32_USART_CR1_OVER8 BIT(15)
+#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04)
+#define STM32_USART_CR2_SWAP BIT(15)
+#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08)
+#define STM32_USART_CR3_EIE BIT(0)
+#define STM32_USART_CR3_DMAR BIT(6)
+#define STM32_USART_CR3_DMAT BIT(7)
+#define STM32_USART_CR3_ONEBIT BIT(11)
+#define STM32_USART_CR3_OVRDIS BIT(12)
+#define STM32_USART_CR3_WUS_START_BIT (2 << 20)
+#define STM32_USART_CR3_WUFIE BIT(22)
+#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C)
+#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10)
+#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14)
+#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18)
+#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C)
+#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20)
+#define STM32_USART_ICR_ORECF BIT(3)
+#define STM32_USART_ICR_TCCF BIT(6)
+#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24)
+#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28)
+#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C)
 /* register alias */
-#define STM32_USART_SR(base)       STM32_USART_ISR(base)
-#define STM32_USART_SR_ORE		BIT(3)
-#define STM32_USART_SR_RXNE		BIT(5)
-#define STM32_USART_SR_TC		BIT(6)
-#define STM32_USART_SR_TXE		BIT(7)
+#define STM32_USART_SR(base) STM32_USART_ISR(base)
+#define STM32_USART_SR_ORE BIT(3)
+#define STM32_USART_SR_RXNE BIT(5)
+#define STM32_USART_SR_TC BIT(6)
+#define STM32_USART_SR_TXE BIT(7)
 
 /* --- GPIO --- */
 
-#define STM32_GPIO_MODER(b)     REG32((b) + 0x00)
-#define STM32_GPIO_OTYPER(b)    REG16((b) + 0x04)
-#define STM32_GPIO_OSPEEDR(b)   REG32((b) + 0x08)
-#define STM32_GPIO_PUPDR(b)     REG32((b) + 0x0C)
-#define STM32_GPIO_IDR(b)       REG16((b) + 0x10)
-#define STM32_GPIO_ODR(b)       REG16((b) + 0x14)
-#define STM32_GPIO_BSRR(b)      REG32((b) + 0x18)
-#define STM32_GPIO_LCKR(b)      REG32((b) + 0x1C)
-#define STM32_GPIO_AFRL(b)      REG32((b) + 0x20)
-#define STM32_GPIO_AFRH(b)      REG32((b) + 0x24)
-#define STM32_GPIO_BRR(b)       REG32((b) + 0x28)
-#define STM32_GPIO_ASCR(b)      REG32((b) + 0x2C) /* only for stm32l4 */
-
-#define GPIO_ALT_F0		0x0
-#define GPIO_ALT_F1		0x1
-#define GPIO_ALT_F2		0x2
-#define GPIO_ALT_F3		0x3
-#define GPIO_ALT_F4		0x4
-#define GPIO_ALT_F5		0x5
-#define GPIO_ALT_F6		0x6
-#define GPIO_ALT_F7		0x7
-#define GPIO_ALT_F8		0x8
-#define GPIO_ALT_F9		0x9
-#define GPIO_ALT_FA		0xA
-#define GPIO_ALT_FB		0xB
-#define GPIO_ALT_FC		0xC
-#define GPIO_ALT_FD		0xD
-#define GPIO_ALT_FE		0xE
-#define GPIO_ALT_FF		0xF
+#define STM32_GPIO_MODER(b) REG32((b) + 0x00)
+#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04)
+#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08)
+#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C)
+#define STM32_GPIO_IDR(b) REG16((b) + 0x10)
+#define STM32_GPIO_ODR(b) REG16((b) + 0x14)
+#define STM32_GPIO_BSRR(b) REG32((b) + 0x18)
+#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C)
+#define STM32_GPIO_AFRL(b) REG32((b) + 0x20)
+#define STM32_GPIO_AFRH(b) REG32((b) + 0x24)
+#define STM32_GPIO_BRR(b) REG32((b) + 0x28)
+#define STM32_GPIO_ASCR(b) REG32((b) + 0x2C) /* only for stm32l4 */
+
+#define GPIO_ALT_F0 0x0
+#define GPIO_ALT_F1 0x1
+#define GPIO_ALT_F2 0x2
+#define GPIO_ALT_F3 0x3
+#define GPIO_ALT_F4 0x4
+#define GPIO_ALT_F5 0x5
+#define GPIO_ALT_F6 0x6
+#define GPIO_ALT_F7 0x7
+#define GPIO_ALT_F8 0x8
+#define GPIO_ALT_F9 0x9
+#define GPIO_ALT_FA 0xA
+#define GPIO_ALT_FB 0xB
+#define GPIO_ALT_FC 0xC
+#define GPIO_ALT_FD 0xD
+#define GPIO_ALT_FE 0xE
+#define GPIO_ALT_FF 0xF
 
 /* --- I2C --- */
-#define STM32_I2C_CR1(n)            REG32(stm32_i2c_reg(n, 0x00))
-#define STM32_I2C_CR1_PE            BIT(0)
-#define STM32_I2C_CR1_TXIE          BIT(1)
-#define STM32_I2C_CR1_RXIE          BIT(2)
-#define STM32_I2C_CR1_ADDRIE        BIT(3)
-#define STM32_I2C_CR1_NACKIE        BIT(4)
-#define STM32_I2C_CR1_STOPIE        BIT(5)
-#define STM32_I2C_CR1_ERRIE         BIT(7)
-#define STM32_I2C_CR1_WUPEN         BIT(18)
-#define STM32_I2C_CR2(n)            REG32(stm32_i2c_reg(n, 0x04))
-#define STM32_I2C_CR2_RD_WRN        BIT(10)
-#define STM32_I2C_CR2_START         BIT(13)
-#define STM32_I2C_CR2_STOP          BIT(14)
-#define STM32_I2C_CR2_NACK          BIT(15)
-#define STM32_I2C_CR2_RELOAD        BIT(24)
-#define STM32_I2C_CR2_AUTOEND       BIT(25)
-#define STM32_I2C_OAR1(n)           REG32(stm32_i2c_reg(n, 0x08))
-#define STM32_I2C_OAR2(n)           REG32(stm32_i2c_reg(n, 0x0C))
-#define STM32_I2C_TIMINGR(n)        REG32(stm32_i2c_reg(n, 0x10))
-#define STM32_I2C_TIMEOUTR(n)       REG32(stm32_i2c_reg(n, 0x14))
-#define STM32_I2C_ISR(n)            REG32(stm32_i2c_reg(n, 0x18))
-#define STM32_I2C_ISR_TXE           BIT(0)
-#define STM32_I2C_ISR_TXIS          BIT(1)
-#define STM32_I2C_ISR_RXNE          BIT(2)
-#define STM32_I2C_ISR_ADDR          BIT(3)
-#define STM32_I2C_ISR_NACK          BIT(4)
-#define STM32_I2C_ISR_STOP          BIT(5)
-#define STM32_I2C_ISR_TC            BIT(6)
-#define STM32_I2C_ISR_TCR           BIT(7)
-#define STM32_I2C_ISR_BERR          BIT(8)
-#define STM32_I2C_ISR_ARLO          BIT(9)
-#define STM32_I2C_ISR_OVR           BIT(10)
-#define STM32_I2C_ISR_PECERR        BIT(11)
-#define STM32_I2C_ISR_TIMEOUT       BIT(12)
-#define STM32_I2C_ISR_ALERT         BIT(13)
-#define STM32_I2C_ISR_BUSY          BIT(15)
-#define STM32_I2C_ISR_DIR           BIT(16)
-#define STM32_I2C_ISR_ADDCODE(isr)  (((isr) >> 16) & 0xfe)
-#define STM32_I2C_ICR(n)            REG32(stm32_i2c_reg(n, 0x1C))
-#define STM32_I2C_ICR_ADDRCF        BIT(3)
-#define STM32_I2C_ICR_NACKCF        BIT(4)
-#define STM32_I2C_ICR_STOPCF        BIT(5)
-#define STM32_I2C_ICR_BERRCF        BIT(8)
-#define STM32_I2C_ICR_ARLOCF        BIT(9)
-#define STM32_I2C_ICR_OVRCF         BIT(10)
-#define STM32_I2C_ICR_TIMEOUTCF     BIT(12)
-#define STM32_I2C_ICR_ALL           0x3F38
-#define STM32_I2C_PECR(n)           REG32(stm32_i2c_reg(n, 0x20))
-#define STM32_I2C_RXDR(n)           REG32(stm32_i2c_reg(n, 0x24))
-#define STM32_I2C_TXDR(n)           REG32(stm32_i2c_reg(n, 0x28))
-
+#define STM32_I2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00))
+#define STM32_I2C_CR1_PE BIT(0)
+#define STM32_I2C_CR1_TXIE BIT(1)
+#define STM32_I2C_CR1_RXIE BIT(2)
+#define STM32_I2C_CR1_ADDRIE BIT(3)
+#define STM32_I2C_CR1_NACKIE BIT(4)
+#define STM32_I2C_CR1_STOPIE BIT(5)
+#define STM32_I2C_CR1_ERRIE BIT(7)
+#define STM32_I2C_CR1_WUPEN BIT(18)
+#define STM32_I2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04))
+#define STM32_I2C_CR2_RD_WRN BIT(10)
+#define STM32_I2C_CR2_START BIT(13)
+#define STM32_I2C_CR2_STOP BIT(14)
+#define STM32_I2C_CR2_NACK BIT(15)
+#define STM32_I2C_CR2_RELOAD BIT(24)
+#define STM32_I2C_CR2_AUTOEND BIT(25)
+#define STM32_I2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08))
+#define STM32_I2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C))
+#define STM32_I2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10))
+#define STM32_I2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14))
+#define STM32_I2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18))
+#define STM32_I2C_ISR_TXE BIT(0)
+#define STM32_I2C_ISR_TXIS BIT(1)
+#define STM32_I2C_ISR_RXNE BIT(2)
+#define STM32_I2C_ISR_ADDR BIT(3)
+#define STM32_I2C_ISR_NACK BIT(4)
+#define STM32_I2C_ISR_STOP BIT(5)
+#define STM32_I2C_ISR_TC BIT(6)
+#define STM32_I2C_ISR_TCR BIT(7)
+#define STM32_I2C_ISR_BERR BIT(8)
+#define STM32_I2C_ISR_ARLO BIT(9)
+#define STM32_I2C_ISR_OVR BIT(10)
+#define STM32_I2C_ISR_PECERR BIT(11)
+#define STM32_I2C_ISR_TIMEOUT BIT(12)
+#define STM32_I2C_ISR_ALERT BIT(13)
+#define STM32_I2C_ISR_BUSY BIT(15)
+#define STM32_I2C_ISR_DIR BIT(16)
+#define STM32_I2C_ISR_ADDCODE(isr) (((isr) >> 16) & 0xfe)
+#define STM32_I2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C))
+#define STM32_I2C_ICR_ADDRCF BIT(3)
+#define STM32_I2C_ICR_NACKCF BIT(4)
+#define STM32_I2C_ICR_STOPCF BIT(5)
+#define STM32_I2C_ICR_BERRCF BIT(8)
+#define STM32_I2C_ICR_ARLOCF BIT(9)
+#define STM32_I2C_ICR_OVRCF BIT(10)
+#define STM32_I2C_ICR_TIMEOUTCF BIT(12)
+#define STM32_I2C_ICR_ALL 0x3F38
+#define STM32_I2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20))
+#define STM32_I2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24))
+#define STM32_I2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28))
 
 /* --- Power / Reset / Clocks --- */
-#define STM32_PWR_CR                REG32(STM32_PWR_BASE + 0x00)
-#define STM32_PWD_PVD_LS_MASK       (0x07 << 5)
-#define STM32_PWD_PVD_LS(n)         ((n & 0x07) << 5)
-#define STM32_PWR_PVDE              BIT(4)
-
-#define STM32_PWR_CSR               REG32(STM32_PWR_BASE + 0x04)
-
-#define STM32_PWR_CSR_EWUP1         BIT(8)
-#define STM32_PWR_CSR_EWUP2         BIT(9)
-#define STM32_PWR_CSR_EWUP3         BIT(10)
-#define STM32_PWR_CSR_EWUP4         BIT(11) /* STM32F0xx only */
-#define STM32_PWR_CSR_EWUP5         BIT(12) /* STM32F0xx only */
-#define STM32_PWR_CSR_EWUP6         BIT(13) /* STM32F0xx only */
-#define STM32_PWR_CSR_EWUP7         BIT(14) /* STM32F0xx only */
-#define STM32_PWR_CSR_EWUP8         BIT(15) /* STM32F0xx only */
-
-#define STM32_CRS_CR                REG32(STM32_CRS_BASE + 0x00) /* STM32F0XX */
-#define STM32_CRS_CR_SYNCOKIE           BIT(0)
-#define STM32_CRS_CR_SYNCWARNIE         BIT(1)
-#define STM32_CRS_CR_ERRIE              BIT(2)
-#define STM32_CRS_CR_ESYNCIE            BIT(3)
-#define STM32_CRS_CR_CEN                BIT(5)
-#define STM32_CRS_CR_AUTOTRIMEN         BIT(6)
-#define STM32_CRS_CR_SWSYNC             BIT(7)
-#define STM32_CRS_CR_TRIM(n)		(((n) & 0x3f) << 8)
-
-#define STM32_CRS_CFGR              REG32(STM32_CRS_BASE + 0x04) /* STM32F0XX */
-#define STM32_CRS_CFGR_RELOAD(n)	(((n) & 0xffff) << 0)
-#define STM32_CRS_CFGR_FELIM(n)		(((n) & 0xff) << 16)
-#define STM32_CRS_CFGR_SYNCDIV(n)	(((n) & 7) << 24)
-#define STM32_CRS_CFGR_SYNCSRC(n)	(((n) & 3) << 28)
-#define STM32_CRS_CFGR_SYNCPOL		BIT(31)
-
-#define STM32_CRS_ISR               REG32(STM32_CRS_BASE + 0x08) /* STM32F0XX */
-#define STM32_CRS_ISR_SYNCOKF		BIT(0)
-#define STM32_CRS_ISR_SYNCWARNF		BIT(1)
-#define STM32_CRS_ISR_ERRF		BIT(2)
-#define STM32_CRS_ISR_ESYNCF		BIT(3)
-#define STM32_CRS_ISR_SYNCERR		BIT(8)
-#define STM32_CRS_ISR_SYNCMISS		BIT(9)
-#define STM32_CRS_ISR_TRIMOVF		BIT(10)
-#define STM32_CRS_ISR_FEDIR		BIT(15)
-#define STM32_CRS_ISR_FECAP		(0xffff << 16)
-
-#define STM32_CRS_ICR               REG32(STM32_CRS_BASE + 0x0c) /* STM32F0XX */
-#define STM32_CRS_ICR_SYNCOKC		BIT(0)
-#define STM32_CRS_ICR_SYNCWARINC	BIT(1)
-#define STM32_CRS_ICR_ERRC		BIT(2)
-#define STM32_CRS_ICR_ESYNCC		BIT(3)
-
-#define STM32_RCC_CR                REG32(STM32_RCC_BASE + 0x00)
-#define STM32_RCC_CFGR              REG32(STM32_RCC_BASE + 0x04)
-#define STM32_RCC_CIR               REG32(STM32_RCC_BASE + 0x08)
-#define STM32_RCC_APB2RSTR          REG32(STM32_RCC_BASE + 0x0c)
-#define STM32_RCC_APB1RSTR          REG32(STM32_RCC_BASE + 0x10)
-#define STM32_RCC_AHBENR            REG32(STM32_RCC_BASE + 0x14)
-#define STM32_RCC_APB2ENR           REG32(STM32_RCC_BASE + 0x18)
-#define STM32_RCC_APB2ENR_ADCEN     BIT(9) /* STM32F3/F0 */
-#define STM32_RCC_APB2ENR_TIM16EN   BIT(17)
-#define STM32_RCC_APB2ENR_TIM17EN   BIT(18)
-#define STM32_RCC_DBGMCUEN          BIT(22)
-#define STM32_RCC_SYSCFGEN          BIT(0)
-
-#define STM32_RCC_APB1ENR           REG32(STM32_RCC_BASE + 0x1c)
-#define STM32_RCC_DACEN                 BIT(29)
-#define STM32_RCC_PWREN                 BIT(28)
-
-#define STM32_RCC_BDCR              REG32(STM32_RCC_BASE + 0x20)
-#define STM32_RCC_CSR               REG32(STM32_RCC_BASE + 0x24)
+#define STM32_PWR_CR REG32(STM32_PWR_BASE + 0x00)
+#define STM32_PWD_PVD_LS_MASK (0x07 << 5)
+#define STM32_PWD_PVD_LS(n) ((n & 0x07) << 5)
+#define STM32_PWR_PVDE BIT(4)
+
+#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04)
+
+#define STM32_PWR_CSR_EWUP1 BIT(8)
+#define STM32_PWR_CSR_EWUP2 BIT(9)
+#define STM32_PWR_CSR_EWUP3 BIT(10)
+#define STM32_PWR_CSR_EWUP4 BIT(11) /* STM32F0xx only */
+#define STM32_PWR_CSR_EWUP5 BIT(12) /* STM32F0xx only */
+#define STM32_PWR_CSR_EWUP6 BIT(13) /* STM32F0xx only */
+#define STM32_PWR_CSR_EWUP7 BIT(14) /* STM32F0xx only */
+#define STM32_PWR_CSR_EWUP8 BIT(15) /* STM32F0xx only */
+
+#define STM32_CRS_CR REG32(STM32_CRS_BASE + 0x00) /* STM32F0XX */
+#define STM32_CRS_CR_SYNCOKIE BIT(0)
+#define STM32_CRS_CR_SYNCWARNIE BIT(1)
+#define STM32_CRS_CR_ERRIE BIT(2)
+#define STM32_CRS_CR_ESYNCIE BIT(3)
+#define STM32_CRS_CR_CEN BIT(5)
+#define STM32_CRS_CR_AUTOTRIMEN BIT(6)
+#define STM32_CRS_CR_SWSYNC BIT(7)
+#define STM32_CRS_CR_TRIM(n) (((n)&0x3f) << 8)
+
+#define STM32_CRS_CFGR REG32(STM32_CRS_BASE + 0x04) /* STM32F0XX */
+#define STM32_CRS_CFGR_RELOAD(n) (((n)&0xffff) << 0)
+#define STM32_CRS_CFGR_FELIM(n) (((n)&0xff) << 16)
+#define STM32_CRS_CFGR_SYNCDIV(n) (((n)&7) << 24)
+#define STM32_CRS_CFGR_SYNCSRC(n) (((n)&3) << 28)
+#define STM32_CRS_CFGR_SYNCPOL BIT(31)
+
+#define STM32_CRS_ISR REG32(STM32_CRS_BASE + 0x08) /* STM32F0XX */
+#define STM32_CRS_ISR_SYNCOKF BIT(0)
+#define STM32_CRS_ISR_SYNCWARNF BIT(1)
+#define STM32_CRS_ISR_ERRF BIT(2)
+#define STM32_CRS_ISR_ESYNCF BIT(3)
+#define STM32_CRS_ISR_SYNCERR BIT(8)
+#define STM32_CRS_ISR_SYNCMISS BIT(9)
+#define STM32_CRS_ISR_TRIMOVF BIT(10)
+#define STM32_CRS_ISR_FEDIR BIT(15)
+#define STM32_CRS_ISR_FECAP (0xffff << 16)
+
+#define STM32_CRS_ICR REG32(STM32_CRS_BASE + 0x0c) /* STM32F0XX */
+#define STM32_CRS_ICR_SYNCOKC BIT(0)
+#define STM32_CRS_ICR_SYNCWARINC BIT(1)
+#define STM32_CRS_ICR_ERRC BIT(2)
+#define STM32_CRS_ICR_ESYNCC BIT(3)
+
+#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00)
+#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x04)
+#define STM32_RCC_CIR REG32(STM32_RCC_BASE + 0x08)
+#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x0c)
+#define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x10)
+#define STM32_RCC_AHBENR REG32(STM32_RCC_BASE + 0x14)
+#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x18)
+#define STM32_RCC_APB2ENR_ADCEN BIT(9) /* STM32F3/F0 */
+#define STM32_RCC_APB2ENR_TIM16EN BIT(17)
+#define STM32_RCC_APB2ENR_TIM17EN BIT(18)
+#define STM32_RCC_DBGMCUEN BIT(22)
+#define STM32_RCC_SYSCFGEN BIT(0)
+
+#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x1c)
+#define STM32_RCC_DACEN BIT(29)
+#define STM32_RCC_PWREN BIT(28)
+
+#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x20)
+#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x24)
 /* STM32F373 */
-#define STM32_RCC_CFGR2             REG32(STM32_RCC_BASE + 0x2c)
+#define STM32_RCC_CFGR2 REG32(STM32_RCC_BASE + 0x2c)
 /* STM32F0XX and STM32F373 */
-#define STM32_RCC_CFGR3             REG32(STM32_RCC_BASE + 0x30)
-#define STM32_RCC_CR2               REG32(STM32_RCC_BASE + 0x34) /* STM32F0XX */
+#define STM32_RCC_CFGR3 REG32(STM32_RCC_BASE + 0x30)
+#define STM32_RCC_CR2 REG32(STM32_RCC_BASE + 0x34) /* STM32F0XX */
 
-#define STM32_RCC_HB_DMA1		BIT(0)
+#define STM32_RCC_HB_DMA1 BIT(0)
 /* STM32F373 */
-#define STM32_RCC_HB_DMA2		BIT(1)
-#define STM32_RCC_PB2_TIM1		BIT(11) /* Except STM32F373 */
-#define STM32_RCC_PB2_TIM15		BIT(16) /* STM32F0XX and STM32F373 */
-#define STM32_RCC_PB2_TIM16		BIT(17) /* STM32F0XX and STM32F373 */
-#define STM32_RCC_PB2_TIM17		BIT(18) /* STM32F0XX and STM32F373 */
-#define STM32_RCC_PB2_TIM19		BIT(19) /* STM32F373 */
-#define STM32_RCC_PB2_PMAD		BIT(11) /* STM32TS */
-#define STM32_RCC_PB2_PMSE		BIT(13) /* STM32TS */
-#define STM32_RCC_PB1_TIM12		BIT(6)  /* STM32F373 */
-#define STM32_RCC_PB1_TIM13		BIT(7)  /* STM32F373 */
-#define STM32_RCC_PB1_TIM14		BIT(8)  /* STM32F0XX and STM32F373 */
-#define STM32_RCC_PB1_TIM18		BIT(9)  /* STM32F373 */
-#define STM32_RCC_PB1_USB		BIT(23)
-#define STM32_RCC_PB1_CRS		BIT(27)
-
-#define STM32_SYSCFG_CFGR1          REG32(STM32_SYSCFG_BASE + 0x00)
-#define STM32_SYSCFG_EXTICR(n)      REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
-#define STM32_SYSCFG_CFGR2          REG32(STM32_SYSCFG_BASE + 0x18)
-
+#define STM32_RCC_HB_DMA2 BIT(1)
+#define STM32_RCC_PB2_TIM1 BIT(11) /* Except STM32F373 */
+#define STM32_RCC_PB2_TIM15 BIT(16) /* STM32F0XX and STM32F373 */
+#define STM32_RCC_PB2_TIM16 BIT(17) /* STM32F0XX and STM32F373 */
+#define STM32_RCC_PB2_TIM17 BIT(18) /* STM32F0XX and STM32F373 */
+#define STM32_RCC_PB2_TIM19 BIT(19) /* STM32F373 */
+#define STM32_RCC_PB2_PMAD BIT(11) /* STM32TS */
+#define STM32_RCC_PB2_PMSE BIT(13) /* STM32TS */
+#define STM32_RCC_PB1_TIM12 BIT(6) /* STM32F373 */
+#define STM32_RCC_PB1_TIM13 BIT(7) /* STM32F373 */
+#define STM32_RCC_PB1_TIM14 BIT(8) /* STM32F0XX and STM32F373 */
+#define STM32_RCC_PB1_TIM18 BIT(9) /* STM32F373 */
+#define STM32_RCC_PB1_USB BIT(23)
+#define STM32_RCC_PB1_CRS BIT(27)
+
+#define STM32_SYSCFG_CFGR1 REG32(STM32_SYSCFG_BASE + 0x00)
+#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
+#define STM32_SYSCFG_CFGR2 REG32(STM32_SYSCFG_BASE + 0x18)
 
 /* Peripheral bits for RCC_APB/AHB and DBGMCU regs */
-#define STM32_RCC_PB2_USART1		BIT(14)
+#define STM32_RCC_PB2_USART1 BIT(14)
 
 /* Reset causes definitions */
 /* Reset causes in RCC CSR register */
 #define STM32_RCC_RESET_CAUSE STM32_RCC_CSR
-#define  RESET_CAUSE_WDG                0x60000000
-#define  RESET_CAUSE_SFT                0x10000000
-#define  RESET_CAUSE_POR                0x08000000
-#define  RESET_CAUSE_PIN                0x04000000
-#define  RESET_CAUSE_OTHER              0xfe000000
-#define  RESET_CAUSE_RMVF               0x01000000
+#define RESET_CAUSE_WDG 0x60000000
+#define RESET_CAUSE_SFT 0x10000000
+#define RESET_CAUSE_POR 0x08000000
+#define RESET_CAUSE_PIN 0x04000000
+#define RESET_CAUSE_OTHER 0xfe000000
+#define RESET_CAUSE_RMVF 0x01000000
 /* Power cause in PWR CSR register */
-#define STM32_PWR_RESET_CAUSE           STM32_PWR_CSR
-#define STM32_PWR_RESET_CAUSE_CLR       STM32_PWR_CR
-#define  RESET_CAUSE_SBF                0x00000002
-#define  RESET_CAUSE_SBF_CLR            0x00000004
+#define STM32_PWR_RESET_CAUSE STM32_PWR_CSR
+#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR
+#define RESET_CAUSE_SBF 0x00000002
+#define RESET_CAUSE_SBF_CLR 0x00000004
 
 /* --- Watchdogs --- */
 
 /* --- Real-Time Clock --- */
-#define STM32_RTC_TR                REG32(STM32_RTC_BASE + 0x00)
-#define STM32_RTC_DR                REG32(STM32_RTC_BASE + 0x04)
-#define STM32_RTC_CR                REG32(STM32_RTC_BASE + 0x08)
-#define STM32_RTC_CR_BYPSHAD        BIT(5)
-#define STM32_RTC_CR_ALRAE          BIT(8)
-#define STM32_RTC_CR_ALRAIE         BIT(12)
-#define STM32_RTC_ISR               REG32(STM32_RTC_BASE + 0x0C)
-#define STM32_RTC_ISR_ALRAWF        BIT(0)
-#define STM32_RTC_ISR_RSF           BIT(5)
-#define STM32_RTC_ISR_INITF         BIT(6)
-#define STM32_RTC_ISR_INIT          BIT(7)
-#define STM32_RTC_ISR_ALRAF         BIT(8)
-#define STM32_RTC_PRER              REG32(STM32_RTC_BASE + 0x10)
-#define STM32_RTC_PRER_A_MASK       (0x7f << 16)
-#define STM32_RTC_PRER_S_MASK       (0x7fff << 0)
-#define STM32_RTC_WUTR              REG32(STM32_RTC_BASE + 0x14)
-#define STM32_RTC_CALIBR            REG32(STM32_RTC_BASE + 0x18)
-#define STM32_RTC_ALRMAR            REG32(STM32_RTC_BASE + 0x1C)
-#define STM32_RTC_ALRMBR            REG32(STM32_RTC_BASE + 0x20)
-#define STM32_RTC_WPR               REG32(STM32_RTC_BASE + 0x24)
-#define STM32_RTC_SSR               REG32(STM32_RTC_BASE + 0x28)
-#define STM32_RTC_TSTR              REG32(STM32_RTC_BASE + 0x30)
-#define STM32_RTC_TSDR              REG32(STM32_RTC_BASE + 0x34)
-#define STM32_RTC_TAFCR             REG32(STM32_RTC_BASE + 0x40)
-#define STM32_RTC_ALRMASSR          REG32(STM32_RTC_BASE + 0x44)
-#define STM32_RTC_BACKUP(n)         REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
-
-#define STM32_BKP_DATA(n)           STM32_RTC_BACKUP(n)
-#define STM32_BKP_BYTES             20
+#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00)
+#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04)
+#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08)
+#define STM32_RTC_CR_BYPSHAD BIT(5)
+#define STM32_RTC_CR_ALRAE BIT(8)
+#define STM32_RTC_CR_ALRAIE BIT(12)
+#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C)
+#define STM32_RTC_ISR_ALRAWF BIT(0)
+#define STM32_RTC_ISR_RSF BIT(5)
+#define STM32_RTC_ISR_INITF BIT(6)
+#define STM32_RTC_ISR_INIT BIT(7)
+#define STM32_RTC_ISR_ALRAF BIT(8)
+#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10)
+#define STM32_RTC_PRER_A_MASK (0x7f << 16)
+#define STM32_RTC_PRER_S_MASK (0x7fff << 0)
+#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14)
+#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18)
+#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C)
+#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20)
+#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24)
+#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28)
+#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30)
+#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34)
+#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40)
+#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44)
+#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
+
+#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n)
+#define STM32_BKP_BYTES 20
 
 /* --- SPI --- */
 
@@ -440,8 +435,8 @@ struct stm32_spi_regs {
 	unsigned crcpr;
 	unsigned rxcrcr;
 	unsigned txcrcr;
-	unsigned i2scfgr;	/* STM32L only */
-	unsigned i2spr;		/* STM32L only */
+	unsigned i2scfgr; /* STM32L only */
+	unsigned i2spr; /* STM32L only */
 };
 /* Must be volatile, or compiler optimizes out repeated accesses */
 typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
@@ -451,155 +446,154 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
 #define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE)
 #define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE)
 
-#define STM32_SPI_CR1_BIDIMODE		BIT(15)
-#define STM32_SPI_CR1_BIDIOE		BIT(14)
-#define STM32_SPI_CR1_CRCEN		BIT(13)
-#define STM32_SPI_CR1_SSM		BIT(9)
-#define STM32_SPI_CR1_SSI		BIT(8)
-#define STM32_SPI_CR1_LSBFIRST		BIT(7)
-#define STM32_SPI_CR1_SPE		BIT(6)
-#define STM32_SPI_CR1_BR_DIV64R		(5 << 3)
-#define STM32_SPI_CR1_BR_DIV4R		BIT(3)
-#define STM32_SPI_CR1_MSTR		BIT(2)
-#define STM32_SPI_CR1_CPOL		BIT(1)
-#define STM32_SPI_CR1_CPHA		BIT(0)
-#define STM32_SPI_CR2_FRXTH		BIT(12)
-#define STM32_SPI_CR2_DATASIZE(n)	(((n) - 1) << 8)
-#define STM32_SPI_CR2_TXEIE		BIT(7)
-#define STM32_SPI_CR2_RXNEIE		BIT(6)
-#define STM32_SPI_CR2_NSSP		BIT(3)
-#define STM32_SPI_CR2_SSOE		BIT(2)
-#define STM32_SPI_CR2_TXDMAEN		BIT(1)
-#define STM32_SPI_CR2_RXDMAEN		BIT(0)
-
-#define STM32_SPI_SR_RXNE		BIT(0)
-#define STM32_SPI_SR_TXE		BIT(1)
-#define STM32_SPI_SR_CRCERR		BIT(4)
-#define STM32_SPI_SR_BSY		BIT(7)
-#define STM32_SPI_SR_FRLVL		(3 << 9)
-#define STM32_SPI_SR_FTLVL		(3 << 11)
+#define STM32_SPI_CR1_BIDIMODE BIT(15)
+#define STM32_SPI_CR1_BIDIOE BIT(14)
+#define STM32_SPI_CR1_CRCEN BIT(13)
+#define STM32_SPI_CR1_SSM BIT(9)
+#define STM32_SPI_CR1_SSI BIT(8)
+#define STM32_SPI_CR1_LSBFIRST BIT(7)
+#define STM32_SPI_CR1_SPE BIT(6)
+#define STM32_SPI_CR1_BR_DIV64R (5 << 3)
+#define STM32_SPI_CR1_BR_DIV4R BIT(3)
+#define STM32_SPI_CR1_MSTR BIT(2)
+#define STM32_SPI_CR1_CPOL BIT(1)
+#define STM32_SPI_CR1_CPHA BIT(0)
+#define STM32_SPI_CR2_FRXTH BIT(12)
+#define STM32_SPI_CR2_DATASIZE(n) (((n)-1) << 8)
+#define STM32_SPI_CR2_TXEIE BIT(7)
+#define STM32_SPI_CR2_RXNEIE BIT(6)
+#define STM32_SPI_CR2_NSSP BIT(3)
+#define STM32_SPI_CR2_SSOE BIT(2)
+#define STM32_SPI_CR2_TXDMAEN BIT(1)
+#define STM32_SPI_CR2_RXDMAEN BIT(0)
+
+#define STM32_SPI_SR_RXNE BIT(0)
+#define STM32_SPI_SR_TXE BIT(1)
+#define STM32_SPI_SR_CRCERR BIT(4)
+#define STM32_SPI_SR_BSY BIT(7)
+#define STM32_SPI_SR_FRLVL (3 << 9)
+#define STM32_SPI_SR_FTLVL (3 << 11)
 /* --- Debug --- */
-#define STM32_DBGMCU_APB1FZ         REG32(STM32_DBGMCU_BASE + 0x08)
-#define STM32_DBGMCU_APB2FZ         REG32(STM32_DBGMCU_BASE + 0x0C)
+#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08)
+#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C)
 
 /* --- Flash --- */
-#define STM32_FLASH_ACR             REG32(STM32_FLASH_REGS_BASE + 0x00)
+#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00)
 #define STM32_FLASH_ACR_LATENCY_SHIFT (0)
-#define STM32_FLASH_ACR_LATENCY_MASK  (7 << STM32_FLASH_ACR_LATENCY_SHIFT)
-#define STM32_FLASH_ACR_LATENCY     BIT(0)
-#define STM32_FLASH_ACR_PRFTEN      BIT(4)
-#define STM32_FLASH_KEYR            REG32(STM32_FLASH_REGS_BASE + 0x04)
-#define  FLASH_KEYR_KEY1                0x45670123
-#define  FLASH_KEYR_KEY2                0xCDEF89AB
-
-#define STM32_FLASH_OPTKEYR         REG32(STM32_FLASH_REGS_BASE + 0x08)
-#define  FLASH_OPTKEYR_KEY1             FLASH_KEYR_KEY1
-#define  FLASH_OPTKEYR_KEY2             FLASH_KEYR_KEY2
-#define STM32_FLASH_SR              REG32(STM32_FLASH_REGS_BASE + 0x0c)
-#define  FLASH_SR_BUSY                  BIT(0)
-#define  FLASH_SR_PGERR                 BIT(2)
-#define  FLASH_SR_WRPRTERR              BIT(4)
-#define  FLASH_SR_ALL_ERR \
-	(FLASH_SR_PGERR | FLASH_SR_WRPRTERR)
-#define  FLASH_SR_EOP                   BIT(5)
-#define STM32_FLASH_CR              REG32(STM32_FLASH_REGS_BASE + 0x10)
-#define  FLASH_CR_PG                    BIT(0)
-#define  FLASH_CR_PER                   BIT(1)
-#define  FLASH_CR_OPTPG                 BIT(4)
-#define  FLASH_CR_OPTER                 BIT(5)
-#define  FLASH_CR_STRT                  BIT(6)
-#define  FLASH_CR_LOCK                  BIT(7)
-#define  FLASH_CR_OPTWRE                BIT(9)
-#define  FLASH_CR_OBL_LAUNCH            BIT(13)
-#define STM32_FLASH_OPT_LOCKED      (!(STM32_FLASH_CR & FLASH_CR_OPTWRE))
-#define STM32_FLASH_AR              REG32(STM32_FLASH_REGS_BASE + 0x14)
-#define STM32_FLASH_OBR             REG32(STM32_FLASH_REGS_BASE + 0x1c)
-#define STM32_FLASH_OBR_RDP_MASK        (3 << 1)
-#define STM32_FLASH_WRPR            REG32(STM32_FLASH_REGS_BASE + 0x20)
-
-#define STM32_OPTB_RDP_OFF              0x00
-#define STM32_OPTB_USER_OFF             0x02
-#define STM32_OPTB_WRP_OFF(n)           (0x08 + (n&3) * 2)
-#define STM32_OPTB_WRP01                0x08
-#define STM32_OPTB_WRP23                0x0c
-
-#define STM32_OPTB_COMPL_SHIFT      8
+#define STM32_FLASH_ACR_LATENCY_MASK (7 << STM32_FLASH_ACR_LATENCY_SHIFT)
+#define STM32_FLASH_ACR_LATENCY BIT(0)
+#define STM32_FLASH_ACR_PRFTEN BIT(4)
+#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x04)
+#define FLASH_KEYR_KEY1 0x45670123
+#define FLASH_KEYR_KEY2 0xCDEF89AB
+
+#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x08)
+#define FLASH_OPTKEYR_KEY1 FLASH_KEYR_KEY1
+#define FLASH_OPTKEYR_KEY2 FLASH_KEYR_KEY2
+#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x0c)
+#define FLASH_SR_BUSY BIT(0)
+#define FLASH_SR_PGERR BIT(2)
+#define FLASH_SR_WRPRTERR BIT(4)
+#define FLASH_SR_ALL_ERR (FLASH_SR_PGERR | FLASH_SR_WRPRTERR)
+#define FLASH_SR_EOP BIT(5)
+#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x10)
+#define FLASH_CR_PG BIT(0)
+#define FLASH_CR_PER BIT(1)
+#define FLASH_CR_OPTPG BIT(4)
+#define FLASH_CR_OPTER BIT(5)
+#define FLASH_CR_STRT BIT(6)
+#define FLASH_CR_LOCK BIT(7)
+#define FLASH_CR_OPTWRE BIT(9)
+#define FLASH_CR_OBL_LAUNCH BIT(13)
+#define STM32_FLASH_OPT_LOCKED (!(STM32_FLASH_CR & FLASH_CR_OPTWRE))
+#define STM32_FLASH_AR REG32(STM32_FLASH_REGS_BASE + 0x14)
+#define STM32_FLASH_OBR REG32(STM32_FLASH_REGS_BASE + 0x1c)
+#define STM32_FLASH_OBR_RDP_MASK (3 << 1)
+#define STM32_FLASH_WRPR REG32(STM32_FLASH_REGS_BASE + 0x20)
+
+#define STM32_OPTB_RDP_OFF 0x00
+#define STM32_OPTB_USER_OFF 0x02
+#define STM32_OPTB_WRP_OFF(n) (0x08 + (n & 3) * 2)
+#define STM32_OPTB_WRP01 0x08
+#define STM32_OPTB_WRP23 0x0c
+
+#define STM32_OPTB_COMPL_SHIFT 8
 
 /* --- External Interrupts --- */
-#define STM32_EXTI_IMR              REG32(STM32_EXTI_BASE + 0x00)
-#define STM32_EXTI_EMR              REG32(STM32_EXTI_BASE + 0x04)
-#define STM32_EXTI_RTSR             REG32(STM32_EXTI_BASE + 0x08)
-#define STM32_EXTI_FTSR             REG32(STM32_EXTI_BASE + 0x0c)
-#define STM32_EXTI_SWIER            REG32(STM32_EXTI_BASE + 0x10)
-#define STM32_EXTI_PR               REG32(STM32_EXTI_BASE + 0x14)
+#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00)
+#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04)
+#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08)
+#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c)
+#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10)
+#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14)
 
-#define EXTI_PVD_EVENT              BIT(16)
-#define EXTI_RTC_ALR_EVENT          BIT(17)
-#define EXTI_COMP2_EVENT            BIT(22)
+#define EXTI_PVD_EVENT BIT(16)
+#define EXTI_RTC_ALR_EVENT BIT(17)
+#define EXTI_COMP2_EVENT BIT(22)
 
 /* --- ADC --- */
-#define STM32_ADC_ISR              REG32(STM32_ADC1_BASE + 0x00)
-#define STM32_ADC_ISR_ADRDY        BIT(0)
-#define STM32_ADC_IER              REG32(STM32_ADC1_BASE + 0x04)
-#define STM32_ADC_IER_AWDIE        BIT(7)
-#define STM32_ADC_IER_OVRIE        BIT(4)
-#define STM32_ADC_IER_EOSEQIE      BIT(3)
-#define STM32_ADC_IER_EOCIE        BIT(2)
-#define STM32_ADC_IER_EOSMPIE      BIT(1)
-#define STM32_ADC_IER_ADRDYIE      BIT(0)
-
-#define STM32_ADC_CR               REG32(STM32_ADC1_BASE + 0x08)
-#define STM32_ADC_CR_ADEN          BIT(0)
-#define STM32_ADC_CR_ADDIS         BIT(1)
-#define STM32_ADC_CR_ADCAL         BIT(31)
-#define STM32_ADC_CFGR1            REG32(STM32_ADC1_BASE + 0x0C)
+#define STM32_ADC_ISR REG32(STM32_ADC1_BASE + 0x00)
+#define STM32_ADC_ISR_ADRDY BIT(0)
+#define STM32_ADC_IER REG32(STM32_ADC1_BASE + 0x04)
+#define STM32_ADC_IER_AWDIE BIT(7)
+#define STM32_ADC_IER_OVRIE BIT(4)
+#define STM32_ADC_IER_EOSEQIE BIT(3)
+#define STM32_ADC_IER_EOCIE BIT(2)
+#define STM32_ADC_IER_EOSMPIE BIT(1)
+#define STM32_ADC_IER_ADRDYIE BIT(0)
+
+#define STM32_ADC_CR REG32(STM32_ADC1_BASE + 0x08)
+#define STM32_ADC_CR_ADEN BIT(0)
+#define STM32_ADC_CR_ADDIS BIT(1)
+#define STM32_ADC_CR_ADCAL BIT(31)
+#define STM32_ADC_CFGR1 REG32(STM32_ADC1_BASE + 0x0C)
 /* Analog watchdog channel selection */
 #define STM32_ADC_CFGR1_AWDCH_MASK (0x1f << 26)
-#define STM32_ADC_CFGR1_AWDEN      BIT(23)
-#define STM32_ADC_CFGR1_AWDSGL     BIT(22)
+#define STM32_ADC_CFGR1_AWDEN BIT(23)
+#define STM32_ADC_CFGR1_AWDSGL BIT(22)
 /* Selects single vs continuous */
-#define STM32_ADC_CFGR1_CONT       BIT(13)
+#define STM32_ADC_CFGR1_CONT BIT(13)
 /* Selects ADC_DR overwrite vs preserve */
-#define STM32_ADC_CFGR1_OVRMOD     BIT(12)
+#define STM32_ADC_CFGR1_OVRMOD BIT(12)
 /* External trigger polarity selection */
-#define STM32_ADC_CFGR1_EXTEN_DIS  (0 << 10)
+#define STM32_ADC_CFGR1_EXTEN_DIS (0 << 10)
 #define STM32_ADC_CFGR1_EXTEN_RISE (1 << 10)
 #define STM32_ADC_CFGR1_EXTEN_FALL (2 << 10)
 #define STM32_ADC_CFGR1_EXTEN_BOTH (3 << 10)
 #define STM32_ADC_CFGR1_EXTEN_MASK (3 << 10)
 /* External trigger selection */
-#define STM32_ADC_CFGR1_TRG0	   (0 << 6)
-#define STM32_ADC_CFGR1_TRG1	   (1 << 6)
-#define STM32_ADC_CFGR1_TRG2	   (2 << 6)
-#define STM32_ADC_CFGR1_TRG3	   (3 << 6)
-#define STM32_ADC_CFGR1_TRG4	   (4 << 6)
-#define STM32_ADC_CFGR1_TRG5	   (5 << 6)
-#define STM32_ADC_CFGR1_TRG6	   (6 << 6)
-#define STM32_ADC_CFGR1_TRG7	   (7 << 6)
-#define STM32_ADC_CFGR1_TRG_MASK   (7 << 6)
+#define STM32_ADC_CFGR1_TRG0 (0 << 6)
+#define STM32_ADC_CFGR1_TRG1 (1 << 6)
+#define STM32_ADC_CFGR1_TRG2 (2 << 6)
+#define STM32_ADC_CFGR1_TRG3 (3 << 6)
+#define STM32_ADC_CFGR1_TRG4 (4 << 6)
+#define STM32_ADC_CFGR1_TRG5 (5 << 6)
+#define STM32_ADC_CFGR1_TRG6 (6 << 6)
+#define STM32_ADC_CFGR1_TRG7 (7 << 6)
+#define STM32_ADC_CFGR1_TRG_MASK (7 << 6)
 /* Selects circular vs one-shot */
-#define STM32_ADC_CFGR1_DMACFG     BIT(1)
-#define STM32_ADC_CFGR1_DMAEN      BIT(0)
-#define STM32_ADC_CFGR2            REG32(STM32_ADC1_BASE + 0x10)
+#define STM32_ADC_CFGR1_DMACFG BIT(1)
+#define STM32_ADC_CFGR1_DMAEN BIT(0)
+#define STM32_ADC_CFGR2 REG32(STM32_ADC1_BASE + 0x10)
 /* Sampling time selection - 1.5 ADC cycles min, 239.5 cycles max */
-#define STM32_ADC_SMPR             REG32(STM32_ADC1_BASE + 0x14)
+#define STM32_ADC_SMPR REG32(STM32_ADC1_BASE + 0x14)
 /* Macro to convert enum stm32_adc_smpr to SMP bits of the ADC_SMPR register */
-#define STM32_ADC_SMPR_SMP(s)      ((s) - 1)
-#define STM32_ADC_TR               REG32(STM32_ADC1_BASE + 0x20)
-#define STM32_ADC_CHSELR           REG32(STM32_ADC1_BASE + 0x28)
-#define STM32_ADC_DR               REG32(STM32_ADC1_BASE + 0x40)
-#define STM32_ADC_CCR              REG32(STM32_ADC1_BASE + 0x308)
+#define STM32_ADC_SMPR_SMP(s) ((s)-1)
+#define STM32_ADC_TR REG32(STM32_ADC1_BASE + 0x20)
+#define STM32_ADC_CHSELR REG32(STM32_ADC1_BASE + 0x28)
+#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x40)
+#define STM32_ADC_CCR REG32(STM32_ADC1_BASE + 0x308)
 
 /* --- Comparators --- */
-#define STM32_COMP_CSR              REG32(STM32_COMP_BASE + 0x1C)
+#define STM32_COMP_CSR REG32(STM32_COMP_BASE + 0x1C)
 
-#define STM32_COMP_CMP2LOCK            BIT(31)
-#define STM32_COMP_CMP2OUT             BIT(30)
-#define STM32_COMP_CMP2HYST_HI         (3 << 28)
-#define STM32_COMP_CMP2HYST_MED        (2 << 28)
-#define STM32_COMP_CMP2HYST_LOW        (1 << 28)
-#define STM32_COMP_CMP2HYST_NO         (0 << 28)
-#define STM32_COMP_CMP2POL             BIT(27)
+#define STM32_COMP_CMP2LOCK BIT(31)
+#define STM32_COMP_CMP2OUT BIT(30)
+#define STM32_COMP_CMP2HYST_HI (3 << 28)
+#define STM32_COMP_CMP2HYST_MED (2 << 28)
+#define STM32_COMP_CMP2HYST_LOW (1 << 28)
+#define STM32_COMP_CMP2HYST_NO (0 << 28)
+#define STM32_COMP_CMP2POL BIT(27)
 
 #define STM32_COMP_CMP2OUTSEL_TIM3_OCR (7 << 24)
 #define STM32_COMP_CMP2OUTSEL_TIM3_IC1 (6 << 24)
@@ -608,32 +602,32 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
 #define STM32_COMP_CMP2OUTSEL_TIM1_OCR (3 << 24)
 #define STM32_COMP_CMP2OUTSEL_TIM1_IC1 (2 << 24)
 #define STM32_COMP_CMP2OUTSEL_TIM1_BRK (1 << 24)
-#define STM32_COMP_CMP2OUTSEL_NONE     (0 << 24)
-#define STM32_COMP_WNDWEN              BIT(23)
-
-#define STM32_COMP_CMP2INSEL_MASK      (7 << 20)
-#define STM32_COMP_CMP2INSEL_INM7      (6 << 20) /* STM32F373 only */
-#define STM32_COMP_CMP2INSEL_INM6      (6 << 20)
-#define STM32_COMP_CMP2INSEL_INM5      (5 << 20)
-#define STM32_COMP_CMP2INSEL_INM4      (4 << 20)
-#define STM32_COMP_CMP2INSEL_VREF      (3 << 20)
-#define STM32_COMP_CMP2INSEL_VREF34    (2 << 20)
-#define STM32_COMP_CMP2INSEL_VREF12    (1 << 20)
-#define STM32_COMP_CMP2INSEL_VREF14    (0 << 20)
-
-#define STM32_COMP_CMP2MODE_VLSPEED    (3 << 18)
-#define STM32_COMP_CMP2MODE_LSPEED     (2 << 18)
-#define STM32_COMP_CMP2MODE_MSPEED     (1 << 18)
-#define STM32_COMP_CMP2MODE_HSPEED     (0 << 18)
-#define STM32_COMP_CMP2EN              BIT(16)
-
-#define STM32_COMP_CMP1LOCK            BIT(15)
-#define STM32_COMP_CMP1OUT             BIT(14)
-#define STM32_COMP_CMP1HYST_HI         (3 << 12)
-#define STM32_COMP_CMP1HYST_MED        (2 << 12)
-#define STM32_COMP_CMP1HYST_LOW        (1 << 12)
-#define STM32_COMP_CMP1HYST_NO         (0 << 12)
-#define STM32_COMP_CMP1POL             BIT(11)
+#define STM32_COMP_CMP2OUTSEL_NONE (0 << 24)
+#define STM32_COMP_WNDWEN BIT(23)
+
+#define STM32_COMP_CMP2INSEL_MASK (7 << 20)
+#define STM32_COMP_CMP2INSEL_INM7 (6 << 20) /* STM32F373 only */
+#define STM32_COMP_CMP2INSEL_INM6 (6 << 20)
+#define STM32_COMP_CMP2INSEL_INM5 (5 << 20)
+#define STM32_COMP_CMP2INSEL_INM4 (4 << 20)
+#define STM32_COMP_CMP2INSEL_VREF (3 << 20)
+#define STM32_COMP_CMP2INSEL_VREF34 (2 << 20)
+#define STM32_COMP_CMP2INSEL_VREF12 (1 << 20)
+#define STM32_COMP_CMP2INSEL_VREF14 (0 << 20)
+
+#define STM32_COMP_CMP2MODE_VLSPEED (3 << 18)
+#define STM32_COMP_CMP2MODE_LSPEED (2 << 18)
+#define STM32_COMP_CMP2MODE_MSPEED (1 << 18)
+#define STM32_COMP_CMP2MODE_HSPEED (0 << 18)
+#define STM32_COMP_CMP2EN BIT(16)
+
+#define STM32_COMP_CMP1LOCK BIT(15)
+#define STM32_COMP_CMP1OUT BIT(14)
+#define STM32_COMP_CMP1HYST_HI (3 << 12)
+#define STM32_COMP_CMP1HYST_MED (2 << 12)
+#define STM32_COMP_CMP1HYST_LOW (1 << 12)
+#define STM32_COMP_CMP1HYST_NO (0 << 12)
+#define STM32_COMP_CMP1POL BIT(11)
 
 #define STM32_COMP_CMP1OUTSEL_TIM3_OCR (7 << 8)
 #define STM32_COMP_CMP1OUTSEL_TIM3_IC1 (6 << 8)
@@ -642,25 +636,24 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
 #define STM32_COMP_CMP1OUTSEL_TIM1_OCR (3 << 8)
 #define STM32_COMP_CMP1OUTSEL_TIM1_IC1 (2 << 8)
 #define STM32_COMP_CMP1OUTSEL_TIM1_BRK (1 << 8)
-#define STM32_COMP_CMP1OUTSEL_NONE     (0 << 8)
-
-#define STM32_COMP_CMP1INSEL_MASK      (7 << 4)
-#define STM32_COMP_CMP1INSEL_INM7      (7 << 4) /* STM32F373 only */
-#define STM32_COMP_CMP1INSEL_INM6      (6 << 4)
-#define STM32_COMP_CMP1INSEL_INM5      (5 << 4)
-#define STM32_COMP_CMP1INSEL_INM4      (4 << 4)
-#define STM32_COMP_CMP1INSEL_VREF      (3 << 4)
-#define STM32_COMP_CMP1INSEL_VREF34    (2 << 4)
-#define STM32_COMP_CMP1INSEL_VREF12    (1 << 4)
-#define STM32_COMP_CMP1INSEL_VREF14    (0 << 4)
-
-#define STM32_COMP_CMP1MODE_VLSPEED    (3 << 2)
-#define STM32_COMP_CMP1MODE_LSPEED     (2 << 2)
-#define STM32_COMP_CMP1MODE_MSPEED     (1 << 2)
-#define STM32_COMP_CMP1MODE_HSPEED     (0 << 2)
-#define STM32_COMP_CMP1SW1             BIT(1)
-#define STM32_COMP_CMP1EN              BIT(0)
-
+#define STM32_COMP_CMP1OUTSEL_NONE (0 << 8)
+
+#define STM32_COMP_CMP1INSEL_MASK (7 << 4)
+#define STM32_COMP_CMP1INSEL_INM7 (7 << 4) /* STM32F373 only */
+#define STM32_COMP_CMP1INSEL_INM6 (6 << 4)
+#define STM32_COMP_CMP1INSEL_INM5 (5 << 4)
+#define STM32_COMP_CMP1INSEL_INM4 (4 << 4)
+#define STM32_COMP_CMP1INSEL_VREF (3 << 4)
+#define STM32_COMP_CMP1INSEL_VREF34 (2 << 4)
+#define STM32_COMP_CMP1INSEL_VREF12 (1 << 4)
+#define STM32_COMP_CMP1INSEL_VREF14 (0 << 4)
+
+#define STM32_COMP_CMP1MODE_VLSPEED (3 << 2)
+#define STM32_COMP_CMP1MODE_LSPEED (2 << 2)
+#define STM32_COMP_CMP1MODE_MSPEED (1 << 2)
+#define STM32_COMP_CMP1MODE_HSPEED (0 << 2)
+#define STM32_COMP_CMP1SW1 BIT(1)
+#define STM32_COMP_CMP1EN BIT(0)
 
 /* --- DMA --- */
 
@@ -682,19 +675,19 @@ enum dma_channel {
 	STM32_DMAC_CH3 = 2,
 	STM32_DMAC_CH4 = 3,
 	STM32_DMAC_CH5 = 4,
+#if defined(CHIP_VARIANT_STM32F07X) || defined(CHIP_VARIANT_STM32F09X)
 	STM32_DMAC_CH6 = 5,
 	STM32_DMAC_CH7 = 6,
-	/*
-	 * Skip CH8, it should belong to DMA engine 1.
-	 * Sharing code with STM32s that have 16 engines will be easier.
-	 */
+#endif
+/* STM32F09 has two DMAs with 7 & 5 channels, respectively */
+#ifdef CHIP_VARIANT_STM32F09X
 	STM32_DMAC_CH9 = 8,
 	STM32_DMAC_CH10 = 9,
 	STM32_DMAC_CH11 = 10,
 	STM32_DMAC_CH12 = 11,
 	STM32_DMAC_CH13 = 12,
 	STM32_DMAC_CH14 = 13,
-
+#endif
 	/* Channel functions */
 	STM32_DMAC_ADC = STM32_DMAC_CH1,
 	STM32_DMAC_SPI1_RX = STM32_DMAC_CH2,
@@ -722,16 +715,19 @@ enum dma_channel {
 	STM32_DMAC_COUNT = 5,
 #endif
 };
-
+/*
+ * TODO(b/233369173): This file was originally shared by many MCUs,
+ *  8 is assumed to be the max number of channels for all chips.
+ */
 #define STM32_DMAC_PER_CTLR 8
 
 /* Registers for a single channel of the DMA controller */
 struct stm32_dma_chan {
-	uint32_t	ccr;		/* Control */
-	uint32_t	cndtr;		/* Number of data to transfer */
-	uint32_t	cpar;		/* Peripheral address */
-	uint32_t	cmar;		/* Memory address */
-	uint32_t	reserved;
+	uint32_t ccr; /* Control */
+	uint32_t cndtr; /* Number of data to transfer */
+	uint32_t cpar; /* Peripheral address */
+	uint32_t cmar; /* Memory address */
+	uint32_t reserved;
 };
 
 /* Always use stm32_dma_chan_t so volatile keyword is included! */
@@ -742,8 +738,8 @@ typedef stm32_dma_chan_t dma_chan_t;
 
 /* Registers for the DMA controller */
 struct stm32_dma_regs {
-	uint32_t	isr;
-	uint32_t	ifcr;
+	uint32_t isr;
+	uint32_t ifcr;
 	stm32_dma_chan_t chan[STM32_DMAC_COUNT];
 };
 
@@ -752,108 +748,106 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
 
 #define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE)
 
-
-#define STM32_DMA_CCR_CHANNEL(channel)		 (0)
+#define STM32_DMA_CCR_CHANNEL(channel) (0)
 
 #ifdef CHIP_VARIANT_STM32F09X
 #define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE)
 #define STM32_DMA_REGS(channel) \
 	((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_REGS : STM32_DMA2_REGS)
-#define STM32_DMA_CSELR(channel) \
-	REG32(((channel) < STM32_DMAC_PER_CTLR ? \
-			STM32_DMA1_BASE : STM32_DMA2_BASE)  + 0xA8)
+#define STM32_DMA_CSELR(channel)                                    \
+	REG32(((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_BASE :  \
+						 STM32_DMA2_BASE) + \
+	      0xA8)
 #else
 #define STM32_DMA_REGS(channel) STM32_DMA1_REGS
 #endif
 
 /* Bits for DMA controller regs (isr and ifcr) */
-#define STM32_DMA_CH_OFFSET(channel)   (4 * ((channel) % STM32_DMAC_PER_CTLR))
+#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR))
 #define STM32_DMA_ISR_MASK(channel, mask) \
 	((mask) << STM32_DMA_CH_OFFSET(channel))
-#define STM32_DMA_ISR_GIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(0))
-#define STM32_DMA_ISR_TCIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(1))
-#define STM32_DMA_ISR_HTIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(2))
-#define STM32_DMA_ISR_TEIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(3))
-#define STM32_DMA_ISR_ALL(channel)	STM32_DMA_ISR_MASK(channel, 0x0f)
-
-#define STM32_DMA_GIF                   BIT(0)
-#define STM32_DMA_TCIF                  BIT(1)
-#define STM32_DMA_HTIF                  BIT(2)
-#define STM32_DMA_TEIF                  BIT(3)
-#define STM32_DMA_ALL                   0xf
-
-#define STM32_DMA_GET_ISR(channel)      \
-	((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_ISR(channel, val) \
-	(STM32_DMA_REGS(channel)->isr = \
-	((STM32_DMA_REGS(channel)->isr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-#define STM32_DMA_GET_IFCR(channel)      \
-	((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_IFCR(channel, val) \
-	(STM32_DMA_REGS(channel)->ifcr = \
-	((STM32_DMA_REGS(channel)->ifcr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-
+#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0))
+#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1))
+#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2))
+#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3))
+#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f)
+
+#define STM32_DMA_GIF BIT(0)
+#define STM32_DMA_TCIF BIT(1)
+#define STM32_DMA_HTIF BIT(2)
+#define STM32_DMA_TEIF BIT(3)
+#define STM32_DMA_ALL 0xf
+
+#define STM32_DMA_GET_ISR(channel)                                        \
+	((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) & \
+	 STM32_DMA_ALL)
+#define STM32_DMA_SET_ISR(channel, val)                                \
+	(STM32_DMA_REGS(channel)->isr =                                \
+		 ((STM32_DMA_REGS(channel)->isr &                      \
+		   ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
+		  (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
+#define STM32_DMA_GET_IFCR(channel)                                        \
+	((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) & \
+	 STM32_DMA_ALL)
+#define STM32_DMA_SET_IFCR(channel, val)                               \
+	(STM32_DMA_REGS(channel)->ifcr =                               \
+		 ((STM32_DMA_REGS(channel)->ifcr &                     \
+		   ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
+		  (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
 
 /* Bits for DMA channel regs */
-#define STM32_DMA_CCR_EN		BIT(0)
-#define STM32_DMA_CCR_TCIE		BIT(1)
-#define STM32_DMA_CCR_HTIE		BIT(2)
-#define STM32_DMA_CCR_TEIE		BIT(3)
-#define STM32_DMA_CCR_DIR		BIT(4)
-#define STM32_DMA_CCR_CIRC		BIT(5)
-#define STM32_DMA_CCR_PINC		BIT(6)
-#define STM32_DMA_CCR_MINC		BIT(7)
-#define STM32_DMA_CCR_PSIZE_8_BIT	(0 << 8)
-#define STM32_DMA_CCR_PSIZE_16_BIT	(1 << 8)
-#define STM32_DMA_CCR_PSIZE_32_BIT	(2 << 8)
-#define STM32_DMA_CCR_MSIZE_8_BIT	(0 << 10)
-#define STM32_DMA_CCR_MSIZE_16_BIT	(1 << 10)
-#define STM32_DMA_CCR_MSIZE_32_BIT	(2 << 10)
-#define STM32_DMA_CCR_PL_LOW		(0 << 12)
-#define STM32_DMA_CCR_PL_MEDIUM		(1 << 12)
-#define STM32_DMA_CCR_PL_HIGH		(2 << 12)
-#define STM32_DMA_CCR_PL_VERY_HIGH	(3 << 12)
-#define STM32_DMA_CCR_MEM2MEM		BIT(14)
-
+#define STM32_DMA_CCR_EN BIT(0)
+#define STM32_DMA_CCR_TCIE BIT(1)
+#define STM32_DMA_CCR_HTIE BIT(2)
+#define STM32_DMA_CCR_TEIE BIT(3)
+#define STM32_DMA_CCR_DIR BIT(4)
+#define STM32_DMA_CCR_CIRC BIT(5)
+#define STM32_DMA_CCR_PINC BIT(6)
+#define STM32_DMA_CCR_MINC BIT(7)
+#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8)
+#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8)
+#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8)
+#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10)
+#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10)
+#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10)
+#define STM32_DMA_CCR_PL_LOW (0 << 12)
+#define STM32_DMA_CCR_PL_MEDIUM (1 << 12)
+#define STM32_DMA_CCR_PL_HIGH (2 << 12)
+#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12)
+#define STM32_DMA_CCR_MEM2MEM BIT(14)
 
 /* --- CRC --- */
-#define STM32_CRC_DR                REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR32              REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR16              REG16(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR8               REG8(STM32_CRC_BASE + 0x0)
-
-#define STM32_CRC_IDR               REG32(STM32_CRC_BASE + 0x4)
-#define STM32_CRC_CR                REG32(STM32_CRC_BASE + 0x8)
-#define STM32_CRC_INIT              REG32(STM32_CRC_BASE + 0x10)
-#define STM32_CRC_POL               REG32(STM32_CRC_BASE + 0x14)
-
-#define STM32_CRC_CR_RESET          BIT(0)
-#define STM32_CRC_CR_POLYSIZE_32    (0 << 3)
-#define STM32_CRC_CR_POLYSIZE_16    (1 << 3)
-#define STM32_CRC_CR_POLYSIZE_8     (2 << 3)
-#define STM32_CRC_CR_POLYSIZE_7     (3 << 3)
-#define STM32_CRC_CR_REV_IN_BYTE    (1 << 5)
-#define STM32_CRC_CR_REV_IN_HWORD   (2 << 5)
-#define STM32_CRC_CR_REV_IN_WORD    (3 << 5)
-#define STM32_CRC_CR_REV_OUT        BIT(7)
-
-#define EP_MASK     0x0F0F
-#define EP_TX_DTOG  0x0040
-#define EP_TX_MASK  0x0030
+#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0)
+
+#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4)
+#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8)
+#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10)
+#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14)
+
+#define STM32_CRC_CR_RESET BIT(0)
+#define STM32_CRC_CR_POLYSIZE_32 (0 << 3)
+#define STM32_CRC_CR_POLYSIZE_16 (1 << 3)
+#define STM32_CRC_CR_POLYSIZE_8 (2 << 3)
+#define STM32_CRC_CR_POLYSIZE_7 (3 << 3)
+#define STM32_CRC_CR_REV_IN_BYTE (1 << 5)
+#define STM32_CRC_CR_REV_IN_HWORD (2 << 5)
+#define STM32_CRC_CR_REV_IN_WORD (3 << 5)
+#define STM32_CRC_CR_REV_OUT BIT(7)
+
+#define EP_MASK 0x0F0F
+#define EP_TX_DTOG 0x0040
+#define EP_TX_MASK 0x0030
 #define EP_TX_VALID 0x0030
-#define EP_TX_NAK   0x0020
+#define EP_TX_NAK 0x0020
 #define EP_TX_STALL 0x0010
 #define EP_TX_DISAB 0x0000
-#define EP_RX_DTOG  0x4000
-#define EP_RX_MASK  0x3000
+#define EP_RX_DTOG 0x4000
+#define EP_RX_MASK 0x3000
 #define EP_RX_VALID 0x3000
-#define EP_RX_NAK   0x2000
+#define EP_RX_NAK 0x2000
 #define EP_RX_STALL 0x1000
 #define EP_RX_DISAB 0x0000
 
@@ -863,28 +857,27 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
 #define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID)
 
 #define STM32_TOGGLE_EP(n, mask, val, flags) \
-	STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \
-			^ (val)) | (flags))
+	STM32_USB_EP(n) =                    \
+		(((STM32_USB_EP(n) & (EP_MASK | (mask))) ^ (val)) | (flags))
 
 /* --- TRNG --- */
-#define STM32_RNG_CR                REG32(STM32_RNG_BASE + 0x0)
-#define STM32_RNG_CR_RNGEN          BIT(2)
-#define STM32_RNG_CR_IE             BIT(3)
-#define STM32_RNG_CR_CED            BIT(5)
-#define STM32_RNG_SR                REG32(STM32_RNG_BASE + 0x4)
-#define STM32_RNG_SR_DRDY           BIT(0)
-#define STM32_RNG_DR                REG32(STM32_RNG_BASE + 0x8)
+#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0)
+#define STM32_RNG_CR_RNGEN BIT(2)
+#define STM32_RNG_CR_IE BIT(3)
+#define STM32_RNG_CR_CED BIT(5)
+#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4)
+#define STM32_RNG_SR_DRDY BIT(0)
+#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8)
 
 /* --- AXI interconnect --- */
 
 /* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */
-#define STM32_AXI_TARG_FN_MOD(x)    REG32(STM32_GPV_BASE + 0x1108 + \
-					  0x1000 * (x))
-#define  WRITE_ISS_OVERRIDE         BIT(1)
-#define  READ_ISS_OVERRIDE          BIT(0)
+#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + 0x1000 * (x))
+#define WRITE_ISS_OVERRIDE BIT(1)
+#define READ_ISS_OVERRIDE BIT(0)
 
 /* --- MISC --- */
-#define STM32_UNIQUE_ID_ADDRESS     REG32_ADDR(STM32_UNIQUE_ID_BASE)
-#define STM32_UNIQUE_ID_LENGTH      (3 * 4)
+#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE)
+#define STM32_UNIQUE_ID_LENGTH (3 * 4)
 
 #endif /* !__ASSEMBLER__ */
diff --git a/chip/stm32/registers-stm32f3.h b/chip/stm32/registers-stm32f3.h
index b7e3cfc8af..e88f5f7d52 100644
--- a/chip/stm32/registers-stm32f3.h
+++ b/chip/stm32/registers-stm32f3.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,473 +19,467 @@
 #endif
 
 /* --- IRQ numbers --- */
-#define STM32_IRQ_WWDG             0
-#define STM32_IRQ_PVD              1
-#define STM32_IRQ_TAMPER_STAMP     2
-#define STM32_IRQ_RTC_WAKEUP       3
-#define STM32_IRQ_FLASH            4
-#define STM32_IRQ_RCC              5
-#define STM32_IRQ_EXTI0            6
-#define STM32_IRQ_EXTI1            7
-#define STM32_IRQ_EXTI2            8
-#define STM32_IRQ_EXTI3            9
-#define STM32_IRQ_EXTI4           10
-#define STM32_IRQ_DMA_CHANNEL_1   11
-#define STM32_IRQ_DMA_CHANNEL_2   12
-#define STM32_IRQ_DMA_CHANNEL_3   13
-#define STM32_IRQ_DMA_CHANNEL_4   14
-#define STM32_IRQ_DMA_CHANNEL_5   15
-#define STM32_IRQ_DMA_CHANNEL_6   16
-#define STM32_IRQ_DMA_CHANNEL_7   17
+#define STM32_IRQ_WWDG 0
+#define STM32_IRQ_PVD 1
+#define STM32_IRQ_TAMPER_STAMP 2
+#define STM32_IRQ_RTC_WAKEUP 3
+#define STM32_IRQ_FLASH 4
+#define STM32_IRQ_RCC 5
+#define STM32_IRQ_EXTI0 6
+#define STM32_IRQ_EXTI1 7
+#define STM32_IRQ_EXTI2 8
+#define STM32_IRQ_EXTI3 9
+#define STM32_IRQ_EXTI4 10
+#define STM32_IRQ_DMA_CHANNEL_1 11
+#define STM32_IRQ_DMA_CHANNEL_2 12
+#define STM32_IRQ_DMA_CHANNEL_3 13
+#define STM32_IRQ_DMA_CHANNEL_4 14
+#define STM32_IRQ_DMA_CHANNEL_5 15
+#define STM32_IRQ_DMA_CHANNEL_6 16
+#define STM32_IRQ_DMA_CHANNEL_7 17
 #ifdef CHIP_VARIANT_STM32F373
-#define STM32_IRQ_USB_HP          74
-#define STM32_IRQ_USB_LP          75
+#define STM32_IRQ_USB_HP 74
+#define STM32_IRQ_USB_LP 75
 #else
-#define STM32_IRQ_USB_HP          19
-#define STM32_IRQ_USB_LP          20
+#define STM32_IRQ_USB_HP 19
+#define STM32_IRQ_USB_LP 20
 #endif
 
-#define STM32_IRQ_ADC1            18 /* STM32L4 only */
-#define STM32_IRQ_CAN_TX          19 /* STM32F373 only */
-#define STM32_IRQ_USB_LP_CAN_RX   20 /* STM32F373 only */
-#define STM32_IRQ_DAC             21
-#define STM32_IRQ_CAN_RX1         21 /* STM32F373 only */
+#define STM32_IRQ_ADC1 18 /* STM32L4 only */
+#define STM32_IRQ_CAN_TX 19 /* STM32F373 only */
+#define STM32_IRQ_USB_LP_CAN_RX 20 /* STM32F373 only */
+#define STM32_IRQ_DAC 21
+#define STM32_IRQ_CAN_RX1 21 /* STM32F373 only */
 
 #ifdef CHIP_VARIANT_STM32F373
-#define STM32_IRQ_COMP            64
+#define STM32_IRQ_COMP 64
 #else
-#define STM32_IRQ_COMP            22
+#define STM32_IRQ_COMP 22
 #endif
 
-#define STM32_IRQ_CAN_SCE         22 /* STM32F373 only */
-#define STM32_IRQ_EXTI9_5         23
-#define STM32_IRQ_LCD             24 /* STM32L15X only */
-#define STM32_IRQ_TIM15           24 /* STM32F373 only */
-#define STM32_IRQ_TIM9            25 /* STM32L15X only */
-#define STM32_IRQ_TIM16           25 /* STM32F373 only */
-#define STM32_IRQ_TIM10           26 /* STM32L15X only */
-#define STM32_IRQ_TIM17           26 /* STM32F373 only */
-#define STM32_IRQ_TIM11           27 /* STM32L15X only */
-#define STM32_IRQ_TIM18_DAC2      27 /* STM32F373 only */
-#define STM32_IRQ_TIM2            28
-#define STM32_IRQ_TIM3            29
-#define STM32_IRQ_TIM4            30
-#define STM32_IRQ_I2C1_EV         31
-#define STM32_IRQ_I2C1_ER         32
-#define STM32_IRQ_I2C2_EV         33
-#define STM32_IRQ_I2C2_ER         34
-#define STM32_IRQ_SPI1            35
-#define STM32_IRQ_SPI2            36
-#define STM32_IRQ_USART1          37
-#define STM32_IRQ_USART2          38
-#define STM32_IRQ_USART3          39
-#define STM32_IRQ_EXTI15_10       40
-#define STM32_IRQ_RTC_ALARM       41
-#define STM32_IRQ_USB_FS_WAKEUP   42 /* STM32L15X */
-#define STM32_IRQ_CEC             42 /* STM32F373 only */
-#define STM32_IRQ_TIM6_BASIC      43 /* STM32L15X only */
-#define STM32_IRQ_TIM12           43 /* STM32F373 only */
-#define STM32_IRQ_TIM7_BASIC      44 /* STM32L15X only */
-#define STM32_IRQ_TIM13           44 /* STM32F373 only */
-#define STM32_IRQ_TIM14           45 /* STM32F373 only */
-#define STM32_IRQ_TIM5            50 /* STM32F373 */
-#define STM32_IRQ_SPI3            51 /* STM32F373 */
-#define STM32_IRQ_USART4          52 /* STM32F446 only */
-#define STM32_IRQ_USART5          53 /* STM32F446 only */
-#define STM32_IRQ_TIM6_DAC        54 /* STM32F373 */
-#define STM32_IRQ_TIM7            55 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL1   56 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL2   57 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL3   58 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL4   59 /* STM32F373 only */
+#define STM32_IRQ_CAN_SCE 22 /* STM32F373 only */
+#define STM32_IRQ_EXTI9_5 23
+#define STM32_IRQ_LCD 24 /* STM32L15X only */
+#define STM32_IRQ_TIM15 24 /* STM32F373 only */
+#define STM32_IRQ_TIM9 25 /* STM32L15X only */
+#define STM32_IRQ_TIM16 25 /* STM32F373 only */
+#define STM32_IRQ_TIM10 26 /* STM32L15X only */
+#define STM32_IRQ_TIM17 26 /* STM32F373 only */
+#define STM32_IRQ_TIM11 27 /* STM32L15X only */
+#define STM32_IRQ_TIM18_DAC2 27 /* STM32F373 only */
+#define STM32_IRQ_TIM2 28
+#define STM32_IRQ_TIM3 29
+#define STM32_IRQ_TIM4 30
+#define STM32_IRQ_I2C1_EV 31
+#define STM32_IRQ_I2C1_ER 32
+#define STM32_IRQ_I2C2_EV 33
+#define STM32_IRQ_I2C2_ER 34
+#define STM32_IRQ_SPI1 35
+#define STM32_IRQ_SPI2 36
+#define STM32_IRQ_USART1 37
+#define STM32_IRQ_USART2 38
+#define STM32_IRQ_USART3 39
+#define STM32_IRQ_EXTI15_10 40
+#define STM32_IRQ_RTC_ALARM 41
+#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X */
+#define STM32_IRQ_CEC 42 /* STM32F373 only */
+#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */
+#define STM32_IRQ_TIM12 43 /* STM32F373 only */
+#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */
+#define STM32_IRQ_TIM13 44 /* STM32F373 only */
+#define STM32_IRQ_TIM14 45 /* STM32F373 only */
+#define STM32_IRQ_TIM5 50 /* STM32F373 */
+#define STM32_IRQ_SPI3 51 /* STM32F373 */
+#define STM32_IRQ_USART4 52 /* STM32F446 only */
+#define STM32_IRQ_USART5 53 /* STM32F446 only */
+#define STM32_IRQ_TIM6_DAC 54 /* STM32F373 */
+#define STM32_IRQ_TIM7 55 /* STM32F373 */
+#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F373 */
+#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F373 */
+#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F373 */
+#define STM32_IRQ_DMA2_CHANNEL4 59 /* STM32F373 only */
 /* if MISC_REMAP bits are set */
-#define STM32_IRQ_DMA2_CHANNEL5   60 /* STM32F373 */
-#define STM32_IRQ_SDADC1          61 /* STM32F373 only */
-#define STM32_IRQ_SDADC2          62 /* STM32F373 only */
-#define STM32_IRQ_SDADC3          63 /* STM32F373 only */
-#define STM32_IRQ_DMA2_CHANNEL6   68 /* STM32L4 only */
-#define STM32_IRQ_DMA2_CHANNEL7   69 /* STM32L4 only */
-#define STM32_IRQ_LPUART          70 /* STM32L4 only */
-#define STM32_IRQ_USART9          70 /* STM32L4 only */
-#define STM32_IRQ_USART6          71 /* STM32F446 only */
-#define STM32_IRQ_I2C3_EV         72 /* STM32F446 only */
-#define STM32_IRQ_I2C3_ER         73 /* STM32F446 only */
-#define STM32_IRQ_USB_WAKEUP      76 /* STM32F373 only */
-#define STM32_IRQ_TIM19           78 /* STM32F373 only */
-#define STM32_IRQ_AES             79 /* STM32L4 only */
-#define STM32_IRQ_RNG             80 /* STM32L4 only */
-#define STM32_IRQ_FPU             81 /* STM32F373 only */
-
+#define STM32_IRQ_DMA2_CHANNEL5 60 /* STM32F373 */
+#define STM32_IRQ_SDADC1 61 /* STM32F373 only */
+#define STM32_IRQ_SDADC2 62 /* STM32F373 only */
+#define STM32_IRQ_SDADC3 63 /* STM32F373 only */
+#define STM32_IRQ_DMA2_CHANNEL6 68 /* STM32L4 only */
+#define STM32_IRQ_DMA2_CHANNEL7 69 /* STM32L4 only */
+#define STM32_IRQ_LPUART 70 /* STM32L4 only */
+#define STM32_IRQ_USART9 70 /* STM32L4 only */
+#define STM32_IRQ_USART6 71 /* STM32F446 only */
+#define STM32_IRQ_I2C3_EV 72 /* STM32F446 only */
+#define STM32_IRQ_I2C3_ER 73 /* STM32F446 only */
+#define STM32_IRQ_USB_WAKEUP 76 /* STM32F373 only */
+#define STM32_IRQ_TIM19 78 /* STM32F373 only */
+#define STM32_IRQ_AES 79 /* STM32L4 only */
+#define STM32_IRQ_RNG 80 /* STM32L4 only */
+#define STM32_IRQ_FPU 81 /* STM32F373 only */
 
 /* To simplify code generation, define DMA channel 9..10 */
-#define STM32_IRQ_DMA_CHANNEL_9    STM32_IRQ_DMA2_CHANNEL1
-#define STM32_IRQ_DMA_CHANNEL_10   STM32_IRQ_DMA2_CHANNEL2
-#define STM32_IRQ_DMA_CHANNEL_13   STM32_IRQ_DMA2_CHANNEL6
-#define STM32_IRQ_DMA_CHANNEL_14   STM32_IRQ_DMA2_CHANNEL7
+#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1
+#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2
+#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6
+#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7
 
 /* aliases for easier code sharing */
 #define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV
 #define STM32_IRQ_I2C2 STM32_IRQ_I2C2_EV
 #define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV
 
-
-
 /* Peripheral base addresses */
-#define STM32_ADC1_BASE             0x40012400
-#define STM32_ADC_BASE              0x40012700 /* STM32L15X only */
+#define STM32_ADC1_BASE 0x40012400
+#define STM32_ADC_BASE 0x40012700 /* STM32L15X only */
 
-#define STM32_CEC_BASE              0x40007800 /* STM32F373 */
-#define STM32_CRC_BASE              0x40023000
-#define STM32_CRS_BASE              0x40006c00 /* STM32F0XX */
-#define STM32_DAC_BASE              0x40007400
+#define STM32_CEC_BASE 0x40007800 /* STM32F373 */
+#define STM32_CRC_BASE 0x40023000
+#define STM32_CRS_BASE 0x40006c00 /* STM32F0XX */
+#define STM32_DAC_BASE 0x40007400
 
-#define STM32_COMP_BASE             0x40010000
+#define STM32_COMP_BASE 0x40010000
 
-#define STM32_DBGMCU_BASE           0xE0042000
+#define STM32_DBGMCU_BASE 0xE0042000
 
-#define STM32_DMA1_BASE             0x40020000
-#define STM32_DMA2_BASE             0x40020400
+#define STM32_DMA1_BASE 0x40020000
+#define STM32_DMA2_BASE 0x40020400
 
-#define STM32_EXTI_BASE             0x40010400
+#define STM32_EXTI_BASE 0x40010400
 
-#define STM32_FLASH_REGS_BASE       0x40022000
+#define STM32_FLASH_REGS_BASE 0x40022000
 
-#define STM32_GPIOA_BASE            0x48000000
-#define STM32_GPIOB_BASE            0x48000400
-#define STM32_GPIOC_BASE            0x48000800
-#define STM32_GPIOD_BASE            0x48000C00
-#define STM32_GPIOE_BASE            0x48001000
-#define STM32_GPIOF_BASE            0x48001400
-#define STM32_GPIOG_BASE            0x48001800 /* only for stm32l4x6 */
-#define STM32_GPIOH_BASE            0x48001C00 /* only for stm32l4 */
+#define STM32_GPIOA_BASE 0x48000000
+#define STM32_GPIOB_BASE 0x48000400
+#define STM32_GPIOC_BASE 0x48000800
+#define STM32_GPIOD_BASE 0x48000C00
+#define STM32_GPIOE_BASE 0x48001000
+#define STM32_GPIOF_BASE 0x48001400
+#define STM32_GPIOG_BASE 0x48001800 /* only for stm32l4x6 */
+#define STM32_GPIOH_BASE 0x48001C00 /* only for stm32l4 */
 
-#define STM32_I2C1_BASE             0x40005400
-#define STM32_I2C2_BASE             0x40005800
-#define STM32_I2C3_BASE             0x40005C00
-#define STM32_I2C4_BASE             0x40006000
+#define STM32_I2C1_BASE 0x40005400
+#define STM32_I2C2_BASE 0x40005800
+#define STM32_I2C3_BASE 0x40005C00
+#define STM32_I2C4_BASE 0x40006000
 
-#define STM32_IWDG_BASE             0x40003000
-#define STM32_LCD_BASE              0x40002400
+#define STM32_IWDG_BASE 0x40003000
+#define STM32_LCD_BASE 0x40002400
 
-#define STM32_OPTB_BASE             0x1FFFF800
+#define STM32_OPTB_BASE 0x1FFFF800
 
-#define STM32_PMSE_BASE             0x40013400
-#define STM32_PWR_BASE              0x40007000
+#define STM32_PMSE_BASE 0x40013400
+#define STM32_PWR_BASE 0x40007000
 
-#define STM32_RCC_BASE              0x40021000
+#define STM32_RCC_BASE 0x40021000
 
-#define STM32_RI_BASE               0x40007C00 /* STM32L1xx only */
-#define STM32_RNG_BASE              0x50060800 /* STM32L4 */
-#define STM32_RTC_BASE              0x40002800
+#define STM32_RI_BASE 0x40007C00 /* STM32L1xx only */
+#define STM32_RNG_BASE 0x50060800 /* STM32L4 */
+#define STM32_RTC_BASE 0x40002800
 
-#define STM32_SPI1_BASE             0x40013000
-#define STM32_SPI2_BASE             0x40003800
-#define STM32_SPI3_BASE             0x40003c00 /* STM32F373, STM32L4, STM32F7 */
+#define STM32_SPI1_BASE 0x40013000
+#define STM32_SPI2_BASE 0x40003800
+#define STM32_SPI3_BASE 0x40003c00 /* STM32F373, STM32L4, STM32F7 */
 
-#define STM32_SYSCFG_BASE           0x40010000
+#define STM32_SYSCFG_BASE 0x40010000
 
-#define STM32_TIM1_BASE             0x40012c00 /* STM32F373 */
-#define STM32_TIM2_BASE             0x40000000
-#define STM32_TIM3_BASE             0x40000400
-#define STM32_TIM4_BASE             0x40000800
-#define STM32_TIM5_BASE             0x40000c00 /* STM32F373 */
-#define STM32_TIM6_BASE             0x40001000
-#define STM32_TIM7_BASE             0x40001400
-#define STM32_TIM12_BASE            0x40001800 /* STM32F373 */
-#define STM32_TIM13_BASE            0x40001c00 /* STM32F373 */
-#define STM32_TIM14_BASE            0x40002000 /* STM32F373 */
-#define STM32_TIM15_BASE            0x40014000
-#define STM32_TIM16_BASE            0x40014400
-#define STM32_TIM17_BASE            0x40014800
-#define STM32_TIM18_BASE            0x40009c00 /* STM32F373 only */
-#define STM32_TIM19_BASE            0x40015c00 /* STM32F373 only */
+#define STM32_TIM1_BASE 0x40012c00 /* STM32F373 */
+#define STM32_TIM2_BASE 0x40000000
+#define STM32_TIM3_BASE 0x40000400
+#define STM32_TIM4_BASE 0x40000800
+#define STM32_TIM5_BASE 0x40000c00 /* STM32F373 */
+#define STM32_TIM6_BASE 0x40001000
+#define STM32_TIM7_BASE 0x40001400
+#define STM32_TIM12_BASE 0x40001800 /* STM32F373 */
+#define STM32_TIM13_BASE 0x40001c00 /* STM32F373 */
+#define STM32_TIM14_BASE 0x40002000 /* STM32F373 */
+#define STM32_TIM15_BASE 0x40014000
+#define STM32_TIM16_BASE 0x40014400
+#define STM32_TIM17_BASE 0x40014800
+#define STM32_TIM18_BASE 0x40009c00 /* STM32F373 only */
+#define STM32_TIM19_BASE 0x40015c00 /* STM32F373 only */
 
-#define STM32_UNIQUE_ID_BASE        0x1ffff7ac
+#define STM32_UNIQUE_ID_BASE 0x1ffff7ac
 
-#define STM32_USART1_BASE           0x40013800
-#define STM32_USART2_BASE           0x40004400
-#define STM32_USART3_BASE           0x40004800
-#define STM32_USART4_BASE           0x40004c00
-#define STM32_USART9_BASE           0x40008000 /* LPUART */
+#define STM32_USART1_BASE 0x40013800
+#define STM32_USART2_BASE 0x40004400
+#define STM32_USART3_BASE 0x40004800
+#define STM32_USART4_BASE 0x40004c00
+#define STM32_USART9_BASE 0x40008000 /* LPUART */
 
-#define STM32_USB_CAN_SRAM_BASE     0x40006000
-#define STM32_USB_FS_BASE           0x40005C00
-
-#define STM32_WWDG_BASE             0x40002C00
+#define STM32_USB_CAN_SRAM_BASE 0x40006000
+#define STM32_USB_FS_BASE 0x40005C00
 
+#define STM32_WWDG_BASE 0x40002C00
 
 #ifndef __ASSEMBLER__
 
 /* Register definitions */
 
 /* --- USART --- */
-#define STM32_USART_CR1(base)      STM32_USART_REG(base, 0x00)
-#define STM32_USART_CR1_UE		BIT(0)
-#define STM32_USART_CR1_UESM            BIT(1)
-#define STM32_USART_CR1_RE		BIT(2)
-#define STM32_USART_CR1_TE		BIT(3)
-#define STM32_USART_CR1_RXNEIE		BIT(5)
-#define STM32_USART_CR1_TCIE		BIT(6)
-#define STM32_USART_CR1_TXEIE		BIT(7)
-#define STM32_USART_CR1_PS		BIT(9)
-#define STM32_USART_CR1_PCE		BIT(10)
-#define STM32_USART_CR1_M		BIT(12)
-#define STM32_USART_CR1_OVER8		BIT(15)
-#define STM32_USART_CR2(base)      STM32_USART_REG(base, 0x04)
-#define STM32_USART_CR2_SWAP		BIT(15)
-#define STM32_USART_CR3(base)      STM32_USART_REG(base, 0x08)
-#define STM32_USART_CR3_EIE		BIT(0)
-#define STM32_USART_CR3_DMAR		BIT(6)
-#define STM32_USART_CR3_DMAT		BIT(7)
-#define STM32_USART_CR3_ONEBIT		BIT(11)
-#define STM32_USART_CR3_OVRDIS		BIT(12)
-#define STM32_USART_CR3_WUS_START_BIT	(2 << 20)
-#define STM32_USART_CR3_WUFIE		BIT(22)
-#define STM32_USART_BRR(base)      STM32_USART_REG(base, 0x0C)
-#define STM32_USART_GTPR(base)     STM32_USART_REG(base, 0x10)
-#define STM32_USART_RTOR(base)     STM32_USART_REG(base, 0x14)
-#define STM32_USART_RQR(base)      STM32_USART_REG(base, 0x18)
-#define STM32_USART_ISR(base)      STM32_USART_REG(base, 0x1C)
-#define STM32_USART_ICR(base)      STM32_USART_REG(base, 0x20)
-#define STM32_USART_ICR_ORECF		BIT(3)
-#define STM32_USART_ICR_TCCF		BIT(6)
-#define STM32_USART_RDR(base)      STM32_USART_REG(base, 0x24)
-#define STM32_USART_TDR(base)      STM32_USART_REG(base, 0x28)
-#define STM32_USART_PRESC(base)    STM32_USART_REG(base, 0x2C)
+#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00)
+#define STM32_USART_CR1_UE BIT(0)
+#define STM32_USART_CR1_UESM BIT(1)
+#define STM32_USART_CR1_RE BIT(2)
+#define STM32_USART_CR1_TE BIT(3)
+#define STM32_USART_CR1_RXNEIE BIT(5)
+#define STM32_USART_CR1_TCIE BIT(6)
+#define STM32_USART_CR1_TXEIE BIT(7)
+#define STM32_USART_CR1_PS BIT(9)
+#define STM32_USART_CR1_PCE BIT(10)
+#define STM32_USART_CR1_M BIT(12)
+#define STM32_USART_CR1_OVER8 BIT(15)
+#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04)
+#define STM32_USART_CR2_SWAP BIT(15)
+#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08)
+#define STM32_USART_CR3_EIE BIT(0)
+#define STM32_USART_CR3_DMAR BIT(6)
+#define STM32_USART_CR3_DMAT BIT(7)
+#define STM32_USART_CR3_ONEBIT BIT(11)
+#define STM32_USART_CR3_OVRDIS BIT(12)
+#define STM32_USART_CR3_WUS_START_BIT (2 << 20)
+#define STM32_USART_CR3_WUFIE BIT(22)
+#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C)
+#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10)
+#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14)
+#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18)
+#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C)
+#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20)
+#define STM32_USART_ICR_ORECF BIT(3)
+#define STM32_USART_ICR_TCCF BIT(6)
+#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24)
+#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28)
+#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C)
 /* register alias */
-#define STM32_USART_SR(base)       STM32_USART_ISR(base)
-#define STM32_USART_SR_ORE		BIT(3)
-#define STM32_USART_SR_RXNE		BIT(5)
-#define STM32_USART_SR_TC		BIT(6)
-#define STM32_USART_SR_TXE		BIT(7)
+#define STM32_USART_SR(base) STM32_USART_ISR(base)
+#define STM32_USART_SR_ORE BIT(3)
+#define STM32_USART_SR_RXNE BIT(5)
+#define STM32_USART_SR_TC BIT(6)
+#define STM32_USART_SR_TXE BIT(7)
 
 /* --- GPIO --- */
 
-#define STM32_GPIO_MODER(b)     REG32((b) + 0x00)
-#define STM32_GPIO_OTYPER(b)    REG16((b) + 0x04)
-#define STM32_GPIO_OSPEEDR(b)   REG32((b) + 0x08)
-#define STM32_GPIO_PUPDR(b)     REG32((b) + 0x0C)
-#define STM32_GPIO_IDR(b)       REG16((b) + 0x10)
-#define STM32_GPIO_ODR(b)       REG16((b) + 0x14)
-#define STM32_GPIO_BSRR(b)      REG32((b) + 0x18)
-#define STM32_GPIO_LCKR(b)      REG32((b) + 0x1C)
-#define STM32_GPIO_AFRL(b)      REG32((b) + 0x20)
-#define STM32_GPIO_AFRH(b)      REG32((b) + 0x24)
-#define STM32_GPIO_BRR(b)       REG32((b) + 0x28)
-#define STM32_GPIO_ASCR(b)      REG32((b) + 0x2C) /* only for stm32l4 */
-
-#define GPIO_ALT_F0		0x0
-#define GPIO_ALT_F1		0x1
-#define GPIO_ALT_F2		0x2
-#define GPIO_ALT_F3		0x3
-#define GPIO_ALT_F4		0x4
-#define GPIO_ALT_F5		0x5
-#define GPIO_ALT_F6		0x6
-#define GPIO_ALT_F7		0x7
-#define GPIO_ALT_F8		0x8
-#define GPIO_ALT_F9		0x9
-#define GPIO_ALT_FA		0xA
-#define GPIO_ALT_FB		0xB
-#define GPIO_ALT_FC		0xC
-#define GPIO_ALT_FD		0xD
-#define GPIO_ALT_FE		0xE
-#define GPIO_ALT_FF		0xF
+#define STM32_GPIO_MODER(b) REG32((b) + 0x00)
+#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04)
+#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08)
+#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C)
+#define STM32_GPIO_IDR(b) REG16((b) + 0x10)
+#define STM32_GPIO_ODR(b) REG16((b) + 0x14)
+#define STM32_GPIO_BSRR(b) REG32((b) + 0x18)
+#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C)
+#define STM32_GPIO_AFRL(b) REG32((b) + 0x20)
+#define STM32_GPIO_AFRH(b) REG32((b) + 0x24)
+#define STM32_GPIO_BRR(b) REG32((b) + 0x28)
+#define STM32_GPIO_ASCR(b) REG32((b) + 0x2C) /* only for stm32l4 */
+
+#define GPIO_ALT_F0 0x0
+#define GPIO_ALT_F1 0x1
+#define GPIO_ALT_F2 0x2
+#define GPIO_ALT_F3 0x3
+#define GPIO_ALT_F4 0x4
+#define GPIO_ALT_F5 0x5
+#define GPIO_ALT_F6 0x6
+#define GPIO_ALT_F7 0x7
+#define GPIO_ALT_F8 0x8
+#define GPIO_ALT_F9 0x9
+#define GPIO_ALT_FA 0xA
+#define GPIO_ALT_FB 0xB
+#define GPIO_ALT_FC 0xC
+#define GPIO_ALT_FD 0xD
+#define GPIO_ALT_FE 0xE
+#define GPIO_ALT_FF 0xF
 
 /* --- I2C --- */
-#define STM32_I2C_CR1(n)            REG32(stm32_i2c_reg(n, 0x00))
-#define STM32_I2C_CR1_PE            BIT(0)
-#define STM32_I2C_CR1_TXIE          BIT(1)
-#define STM32_I2C_CR1_RXIE          BIT(2)
-#define STM32_I2C_CR1_ADDRIE        BIT(3)
-#define STM32_I2C_CR1_NACKIE        BIT(4)
-#define STM32_I2C_CR1_STOPIE        BIT(5)
-#define STM32_I2C_CR1_ERRIE         BIT(7)
-#define STM32_I2C_CR1_WUPEN         BIT(18)
-#define STM32_I2C_CR2(n)            REG32(stm32_i2c_reg(n, 0x04))
-#define STM32_I2C_CR2_RD_WRN        BIT(10)
-#define STM32_I2C_CR2_START         BIT(13)
-#define STM32_I2C_CR2_STOP          BIT(14)
-#define STM32_I2C_CR2_NACK          BIT(15)
-#define STM32_I2C_CR2_RELOAD        BIT(24)
-#define STM32_I2C_CR2_AUTOEND       BIT(25)
-#define STM32_I2C_OAR1(n)           REG32(stm32_i2c_reg(n, 0x08))
-#define STM32_I2C_OAR2(n)           REG32(stm32_i2c_reg(n, 0x0C))
-#define STM32_I2C_TIMINGR(n)        REG32(stm32_i2c_reg(n, 0x10))
-#define STM32_I2C_TIMEOUTR(n)       REG32(stm32_i2c_reg(n, 0x14))
-#define STM32_I2C_ISR(n)            REG32(stm32_i2c_reg(n, 0x18))
-#define STM32_I2C_ISR_TXE           BIT(0)
-#define STM32_I2C_ISR_TXIS          BIT(1)
-#define STM32_I2C_ISR_RXNE          BIT(2)
-#define STM32_I2C_ISR_ADDR          BIT(3)
-#define STM32_I2C_ISR_NACK          BIT(4)
-#define STM32_I2C_ISR_STOP          BIT(5)
-#define STM32_I2C_ISR_TC            BIT(6)
-#define STM32_I2C_ISR_TCR           BIT(7)
-#define STM32_I2C_ISR_BERR          BIT(8)
-#define STM32_I2C_ISR_ARLO          BIT(9)
-#define STM32_I2C_ISR_OVR           BIT(10)
-#define STM32_I2C_ISR_PECERR        BIT(11)
-#define STM32_I2C_ISR_TIMEOUT       BIT(12)
-#define STM32_I2C_ISR_ALERT         BIT(13)
-#define STM32_I2C_ISR_BUSY          BIT(15)
-#define STM32_I2C_ISR_DIR           BIT(16)
-#define STM32_I2C_ISR_ADDCODE(isr)  (((isr) >> 16) & 0xfe)
-#define STM32_I2C_ICR(n)            REG32(stm32_i2c_reg(n, 0x1C))
-#define STM32_I2C_ICR_ADDRCF        BIT(3)
-#define STM32_I2C_ICR_NACKCF        BIT(4)
-#define STM32_I2C_ICR_STOPCF        BIT(5)
-#define STM32_I2C_ICR_BERRCF        BIT(8)
-#define STM32_I2C_ICR_ARLOCF        BIT(9)
-#define STM32_I2C_ICR_OVRCF         BIT(10)
-#define STM32_I2C_ICR_TIMEOUTCF     BIT(12)
-#define STM32_I2C_ICR_ALL           0x3F38
-#define STM32_I2C_PECR(n)           REG32(stm32_i2c_reg(n, 0x20))
-#define STM32_I2C_RXDR(n)           REG32(stm32_i2c_reg(n, 0x24))
-#define STM32_I2C_TXDR(n)           REG32(stm32_i2c_reg(n, 0x28))
-
+#define STM32_I2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00))
+#define STM32_I2C_CR1_PE BIT(0)
+#define STM32_I2C_CR1_TXIE BIT(1)
+#define STM32_I2C_CR1_RXIE BIT(2)
+#define STM32_I2C_CR1_ADDRIE BIT(3)
+#define STM32_I2C_CR1_NACKIE BIT(4)
+#define STM32_I2C_CR1_STOPIE BIT(5)
+#define STM32_I2C_CR1_ERRIE BIT(7)
+#define STM32_I2C_CR1_WUPEN BIT(18)
+#define STM32_I2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04))
+#define STM32_I2C_CR2_RD_WRN BIT(10)
+#define STM32_I2C_CR2_START BIT(13)
+#define STM32_I2C_CR2_STOP BIT(14)
+#define STM32_I2C_CR2_NACK BIT(15)
+#define STM32_I2C_CR2_RELOAD BIT(24)
+#define STM32_I2C_CR2_AUTOEND BIT(25)
+#define STM32_I2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08))
+#define STM32_I2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C))
+#define STM32_I2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10))
+#define STM32_I2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14))
+#define STM32_I2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18))
+#define STM32_I2C_ISR_TXE BIT(0)
+#define STM32_I2C_ISR_TXIS BIT(1)
+#define STM32_I2C_ISR_RXNE BIT(2)
+#define STM32_I2C_ISR_ADDR BIT(3)
+#define STM32_I2C_ISR_NACK BIT(4)
+#define STM32_I2C_ISR_STOP BIT(5)
+#define STM32_I2C_ISR_TC BIT(6)
+#define STM32_I2C_ISR_TCR BIT(7)
+#define STM32_I2C_ISR_BERR BIT(8)
+#define STM32_I2C_ISR_ARLO BIT(9)
+#define STM32_I2C_ISR_OVR BIT(10)
+#define STM32_I2C_ISR_PECERR BIT(11)
+#define STM32_I2C_ISR_TIMEOUT BIT(12)
+#define STM32_I2C_ISR_ALERT BIT(13)
+#define STM32_I2C_ISR_BUSY BIT(15)
+#define STM32_I2C_ISR_DIR BIT(16)
+#define STM32_I2C_ISR_ADDCODE(isr) (((isr) >> 16) & 0xfe)
+#define STM32_I2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C))
+#define STM32_I2C_ICR_ADDRCF BIT(3)
+#define STM32_I2C_ICR_NACKCF BIT(4)
+#define STM32_I2C_ICR_STOPCF BIT(5)
+#define STM32_I2C_ICR_BERRCF BIT(8)
+#define STM32_I2C_ICR_ARLOCF BIT(9)
+#define STM32_I2C_ICR_OVRCF BIT(10)
+#define STM32_I2C_ICR_TIMEOUTCF BIT(12)
+#define STM32_I2C_ICR_ALL 0x3F38
+#define STM32_I2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20))
+#define STM32_I2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24))
+#define STM32_I2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28))
 
 /* --- Power / Reset / Clocks --- */
-#define STM32_PWR_CSR               REG32(STM32_PWR_BASE + 0x04)
-
-#define STM32_PWR_CSR_EWUP1         BIT(8)
-#define STM32_PWR_CSR_EWUP2         BIT(9)
-#define STM32_PWR_CSR_EWUP3         BIT(10)
-#define STM32_PWR_CSR_EWUP4         BIT(11) /* STM32F0xx only */
-#define STM32_PWR_CSR_EWUP5         BIT(12) /* STM32F0xx only */
-#define STM32_PWR_CSR_EWUP6         BIT(13) /* STM32F0xx only */
-#define STM32_PWR_CSR_EWUP7         BIT(14) /* STM32F0xx only */
-#define STM32_PWR_CSR_EWUP8         BIT(15) /* STM32F0xx only */
-
-#define STM32_CRS_CR                REG32(STM32_CRS_BASE + 0x00) /* STM32F0XX */
-#define STM32_CRS_CR_SYNCOKIE           BIT(0)
-#define STM32_CRS_CR_SYNCWARNIE         BIT(1)
-#define STM32_CRS_CR_ERRIE              BIT(2)
-#define STM32_CRS_CR_ESYNCIE            BIT(3)
-#define STM32_CRS_CR_CEN                BIT(5)
-#define STM32_CRS_CR_AUTOTRIMEN         BIT(6)
-#define STM32_CRS_CR_SWSYNC             BIT(7)
-#define STM32_CRS_CR_TRIM(n)		(((n) & 0x3f) << 8)
-
-#define STM32_CRS_CFGR              REG32(STM32_CRS_BASE + 0x04) /* STM32F0XX */
-#define STM32_CRS_CFGR_RELOAD(n)	(((n) & 0xffff) << 0)
-#define STM32_CRS_CFGR_FELIM(n)		(((n) & 0xff) << 16)
-#define STM32_CRS_CFGR_SYNCDIV(n)	(((n) & 7) << 24)
-#define STM32_CRS_CFGR_SYNCSRC(n)	(((n) & 3) << 28)
-#define STM32_CRS_CFGR_SYNCPOL		BIT(31)
-
-#define STM32_CRS_ISR               REG32(STM32_CRS_BASE + 0x08) /* STM32F0XX */
-#define STM32_CRS_ISR_SYNCOKF		BIT(0)
-#define STM32_CRS_ISR_SYNCWARNF		BIT(1)
-#define STM32_CRS_ISR_ERRF		BIT(2)
-#define STM32_CRS_ISR_ESYNCF		BIT(3)
-#define STM32_CRS_ISR_SYNCERR		BIT(8)
-#define STM32_CRS_ISR_SYNCMISS		BIT(9)
-#define STM32_CRS_ISR_TRIMOVF		BIT(10)
-#define STM32_CRS_ISR_FEDIR		BIT(15)
-#define STM32_CRS_ISR_FECAP		(0xffff << 16)
-
-#define STM32_CRS_ICR               REG32(STM32_CRS_BASE + 0x0c) /* STM32F0XX */
-#define STM32_CRS_ICR_SYNCOKC		BIT(0)
-#define STM32_CRS_ICR_SYNCWARINC	BIT(1)
-#define STM32_CRS_ICR_ERRC		BIT(2)
-#define STM32_CRS_ICR_ESYNCC		BIT(3)
-
-#define STM32_RCC_CR                REG32(STM32_RCC_BASE + 0x00)
-#define STM32_RCC_CFGR              REG32(STM32_RCC_BASE + 0x04)
-#define STM32_RCC_CIR               REG32(STM32_RCC_BASE + 0x08)
-#define STM32_RCC_APB2RSTR          REG32(STM32_RCC_BASE + 0x0c)
-#define STM32_RCC_APB1RSTR          REG32(STM32_RCC_BASE + 0x10)
-#define STM32_RCC_AHBENR            REG32(STM32_RCC_BASE + 0x14)
-#define STM32_RCC_APB2ENR           REG32(STM32_RCC_BASE + 0x18)
-#define STM32_RCC_APB2ENR_ADCEN     BIT(9) /* STM32F3/F0 */
-#define STM32_RCC_APB2ENR_TIM16EN   BIT(17)
-#define STM32_RCC_APB2ENR_TIM17EN   BIT(18)
-#define STM32_RCC_DBGMCUEN          BIT(22)
-#define STM32_RCC_SYSCFGEN          BIT(0)
-
-#define STM32_RCC_APB1ENR           REG32(STM32_RCC_BASE + 0x1c)
-#define STM32_RCC_PWREN                 BIT(28)
-
-#define STM32_RCC_BDCR              REG32(STM32_RCC_BASE + 0x20)
-#define STM32_RCC_CSR               REG32(STM32_RCC_BASE + 0x24)
+#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04)
+
+#define STM32_PWR_CSR_EWUP1 BIT(8)
+#define STM32_PWR_CSR_EWUP2 BIT(9)
+#define STM32_PWR_CSR_EWUP3 BIT(10)
+#define STM32_PWR_CSR_EWUP4 BIT(11) /* STM32F0xx only */
+#define STM32_PWR_CSR_EWUP5 BIT(12) /* STM32F0xx only */
+#define STM32_PWR_CSR_EWUP6 BIT(13) /* STM32F0xx only */
+#define STM32_PWR_CSR_EWUP7 BIT(14) /* STM32F0xx only */
+#define STM32_PWR_CSR_EWUP8 BIT(15) /* STM32F0xx only */
+
+#define STM32_CRS_CR REG32(STM32_CRS_BASE + 0x00) /* STM32F0XX */
+#define STM32_CRS_CR_SYNCOKIE BIT(0)
+#define STM32_CRS_CR_SYNCWARNIE BIT(1)
+#define STM32_CRS_CR_ERRIE BIT(2)
+#define STM32_CRS_CR_ESYNCIE BIT(3)
+#define STM32_CRS_CR_CEN BIT(5)
+#define STM32_CRS_CR_AUTOTRIMEN BIT(6)
+#define STM32_CRS_CR_SWSYNC BIT(7)
+#define STM32_CRS_CR_TRIM(n) (((n)&0x3f) << 8)
+
+#define STM32_CRS_CFGR REG32(STM32_CRS_BASE + 0x04) /* STM32F0XX */
+#define STM32_CRS_CFGR_RELOAD(n) (((n)&0xffff) << 0)
+#define STM32_CRS_CFGR_FELIM(n) (((n)&0xff) << 16)
+#define STM32_CRS_CFGR_SYNCDIV(n) (((n)&7) << 24)
+#define STM32_CRS_CFGR_SYNCSRC(n) (((n)&3) << 28)
+#define STM32_CRS_CFGR_SYNCPOL BIT(31)
+
+#define STM32_CRS_ISR REG32(STM32_CRS_BASE + 0x08) /* STM32F0XX */
+#define STM32_CRS_ISR_SYNCOKF BIT(0)
+#define STM32_CRS_ISR_SYNCWARNF BIT(1)
+#define STM32_CRS_ISR_ERRF BIT(2)
+#define STM32_CRS_ISR_ESYNCF BIT(3)
+#define STM32_CRS_ISR_SYNCERR BIT(8)
+#define STM32_CRS_ISR_SYNCMISS BIT(9)
+#define STM32_CRS_ISR_TRIMOVF BIT(10)
+#define STM32_CRS_ISR_FEDIR BIT(15)
+#define STM32_CRS_ISR_FECAP (0xffff << 16)
+
+#define STM32_CRS_ICR REG32(STM32_CRS_BASE + 0x0c) /* STM32F0XX */
+#define STM32_CRS_ICR_SYNCOKC BIT(0)
+#define STM32_CRS_ICR_SYNCWARINC BIT(1)
+#define STM32_CRS_ICR_ERRC BIT(2)
+#define STM32_CRS_ICR_ESYNCC BIT(3)
+
+#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00)
+#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x04)
+#define STM32_RCC_CIR REG32(STM32_RCC_BASE + 0x08)
+#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x0c)
+#define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x10)
+#define STM32_RCC_AHBENR REG32(STM32_RCC_BASE + 0x14)
+#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x18)
+#define STM32_RCC_APB2ENR_ADCEN BIT(9) /* STM32F3/F0 */
+#define STM32_RCC_APB2ENR_TIM16EN BIT(17)
+#define STM32_RCC_APB2ENR_TIM17EN BIT(18)
+#define STM32_RCC_DBGMCUEN BIT(22)
+#define STM32_RCC_SYSCFGEN BIT(0)
+
+#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x1c)
+#define STM32_RCC_PWREN BIT(28)
+
+#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x20)
+#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x24)
 /* STM32F373 */
-#define STM32_RCC_CFGR2             REG32(STM32_RCC_BASE + 0x2c)
+#define STM32_RCC_CFGR2 REG32(STM32_RCC_BASE + 0x2c)
 /* STM32F0XX and STM32F373 */
-#define STM32_RCC_CFGR3             REG32(STM32_RCC_BASE + 0x30)
-#define STM32_RCC_CR2               REG32(STM32_RCC_BASE + 0x34) /* STM32F0XX */
+#define STM32_RCC_CFGR3 REG32(STM32_RCC_BASE + 0x30)
+#define STM32_RCC_CR2 REG32(STM32_RCC_BASE + 0x34) /* STM32F0XX */
 
-#define STM32_RCC_HB_DMA1		BIT(0)
+#define STM32_RCC_HB_DMA1 BIT(0)
 /* STM32F373 */
-#define STM32_RCC_HB_DMA2		BIT(1)
-#define STM32_RCC_PB2_TIM1		BIT(11) /* Except STM32F373 */
-#define STM32_RCC_PB2_TIM15		BIT(16) /* STM32F0XX and STM32F373 */
-#define STM32_RCC_PB2_TIM16		BIT(17) /* STM32F0XX and STM32F373 */
-#define STM32_RCC_PB2_TIM17		BIT(18) /* STM32F0XX and STM32F373 */
-#define STM32_RCC_PB2_TIM19		BIT(19) /* STM32F373 */
-#define STM32_RCC_PB2_PMAD		BIT(11) /* STM32TS */
-#define STM32_RCC_PB2_PMSE		BIT(13) /* STM32TS */
-#define STM32_RCC_PB1_TIM12		BIT(6)  /* STM32F373 */
-#define STM32_RCC_PB1_TIM13		BIT(7)  /* STM32F373 */
-#define STM32_RCC_PB1_TIM14		BIT(8)  /* STM32F0XX and STM32F373 */
-#define STM32_RCC_PB1_TIM18		BIT(9)  /* STM32F373 */
-#define STM32_RCC_PB1_USB		BIT(23)
-#define STM32_RCC_PB1_CRS		BIT(27)
-
-#define STM32_SYSCFG_CFGR1          REG32(STM32_SYSCFG_BASE + 0x00)
-#define STM32_SYSCFG_EXTICR(n)      REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
-#define STM32_SYSCFG_CFGR2          REG32(STM32_SYSCFG_BASE + 0x18)
-
+#define STM32_RCC_HB_DMA2 BIT(1)
+#define STM32_RCC_PB2_TIM1 BIT(11) /* Except STM32F373 */
+#define STM32_RCC_PB2_TIM15 BIT(16) /* STM32F0XX and STM32F373 */
+#define STM32_RCC_PB2_TIM16 BIT(17) /* STM32F0XX and STM32F373 */
+#define STM32_RCC_PB2_TIM17 BIT(18) /* STM32F0XX and STM32F373 */
+#define STM32_RCC_PB2_TIM19 BIT(19) /* STM32F373 */
+#define STM32_RCC_PB2_PMAD BIT(11) /* STM32TS */
+#define STM32_RCC_PB2_PMSE BIT(13) /* STM32TS */
+#define STM32_RCC_PB1_TIM12 BIT(6) /* STM32F373 */
+#define STM32_RCC_PB1_TIM13 BIT(7) /* STM32F373 */
+#define STM32_RCC_PB1_TIM14 BIT(8) /* STM32F0XX and STM32F373 */
+#define STM32_RCC_PB1_TIM18 BIT(9) /* STM32F373 */
+#define STM32_RCC_PB1_USB BIT(23)
+#define STM32_RCC_PB1_CRS BIT(27)
+
+#define STM32_SYSCFG_CFGR1 REG32(STM32_SYSCFG_BASE + 0x00)
+#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
+#define STM32_SYSCFG_CFGR2 REG32(STM32_SYSCFG_BASE + 0x18)
 
 /* Peripheral bits for RCC_APB/AHB and DBGMCU regs */
-#define STM32_RCC_PB2_USART1		BIT(14)
+#define STM32_RCC_PB2_USART1 BIT(14)
 
 /* Reset causes definitions */
 /* Reset causes in RCC CSR register */
 #define STM32_RCC_RESET_CAUSE STM32_RCC_CSR
-#define  RESET_CAUSE_WDG                0x60000000
-#define  RESET_CAUSE_SFT                0x10000000
-#define  RESET_CAUSE_POR                0x08000000
-#define  RESET_CAUSE_PIN                0x04000000
-#define  RESET_CAUSE_OTHER              0xfe000000
-#define  RESET_CAUSE_RMVF               0x01000000
+#define RESET_CAUSE_WDG 0x60000000
+#define RESET_CAUSE_SFT 0x10000000
+#define RESET_CAUSE_POR 0x08000000
+#define RESET_CAUSE_PIN 0x04000000
+#define RESET_CAUSE_OTHER 0xfe000000
+#define RESET_CAUSE_RMVF 0x01000000
 /* Power cause in PWR CSR register */
 #define STM32_PWR_RESET_CAUSE STM32_PWR_CSR
 #define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR
-#define  RESET_CAUSE_SBF                0x00000002
-#define  RESET_CAUSE_SBF_CLR            0x00000004
+#define RESET_CAUSE_SBF 0x00000002
+#define RESET_CAUSE_SBF_CLR 0x00000004
 
 /* --- Watchdogs --- */
 
 /* --- Real-Time Clock --- */
-#define STM32_RTC_TR                REG32(STM32_RTC_BASE + 0x00)
-#define STM32_RTC_DR                REG32(STM32_RTC_BASE + 0x04)
-#define STM32_RTC_CR                REG32(STM32_RTC_BASE + 0x08)
-#define STM32_RTC_CR_BYPSHAD        BIT(5)
-#define STM32_RTC_CR_ALRAE          BIT(8)
-#define STM32_RTC_CR_ALRAIE         BIT(12)
-#define STM32_RTC_ISR               REG32(STM32_RTC_BASE + 0x0C)
-#define STM32_RTC_ISR_ALRAWF        BIT(0)
-#define STM32_RTC_ISR_RSF           BIT(5)
-#define STM32_RTC_ISR_INITF         BIT(6)
-#define STM32_RTC_ISR_INIT          BIT(7)
-#define STM32_RTC_ISR_ALRAF         BIT(8)
-#define STM32_RTC_PRER              REG32(STM32_RTC_BASE + 0x10)
-#define STM32_RTC_PRER_A_MASK       (0x7f << 16)
-#define STM32_RTC_PRER_S_MASK       (0x7fff << 0)
-#define STM32_RTC_WUTR              REG32(STM32_RTC_BASE + 0x14)
-#define STM32_RTC_CALIBR            REG32(STM32_RTC_BASE + 0x18)
-#define STM32_RTC_ALRMAR            REG32(STM32_RTC_BASE + 0x1C)
-#define STM32_RTC_ALRMBR            REG32(STM32_RTC_BASE + 0x20)
-#define STM32_RTC_WPR               REG32(STM32_RTC_BASE + 0x24)
-#define STM32_RTC_SSR               REG32(STM32_RTC_BASE + 0x28)
-#define STM32_RTC_TSTR              REG32(STM32_RTC_BASE + 0x30)
-#define STM32_RTC_TSDR              REG32(STM32_RTC_BASE + 0x34)
-#define STM32_RTC_TAFCR             REG32(STM32_RTC_BASE + 0x40)
-#define STM32_RTC_ALRMASSR          REG32(STM32_RTC_BASE + 0x44)
-#define STM32_RTC_BACKUP(n)         REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
-
-#define STM32_BKP_DATA(n)           STM32_RTC_BACKUP(n)
-#define STM32_BKP_BYTES             64
+#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00)
+#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04)
+#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08)
+#define STM32_RTC_CR_BYPSHAD BIT(5)
+#define STM32_RTC_CR_ALRAE BIT(8)
+#define STM32_RTC_CR_ALRAIE BIT(12)
+#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C)
+#define STM32_RTC_ISR_ALRAWF BIT(0)
+#define STM32_RTC_ISR_RSF BIT(5)
+#define STM32_RTC_ISR_INITF BIT(6)
+#define STM32_RTC_ISR_INIT BIT(7)
+#define STM32_RTC_ISR_ALRAF BIT(8)
+#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10)
+#define STM32_RTC_PRER_A_MASK (0x7f << 16)
+#define STM32_RTC_PRER_S_MASK (0x7fff << 0)
+#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14)
+#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18)
+#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C)
+#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20)
+#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24)
+#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28)
+#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30)
+#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34)
+#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40)
+#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44)
+#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
+
+#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n)
+#define STM32_BKP_BYTES 64
 
 /* --- SPI --- */
 
@@ -502,8 +496,8 @@ struct stm32_spi_regs {
 	unsigned crcpr;
 	unsigned rxcrcr;
 	unsigned txcrcr;
-	unsigned i2scfgr;	/* STM32L only */
-	unsigned i2spr;		/* STM32L only */
+	unsigned i2scfgr; /* STM32L only */
+	unsigned i2spr; /* STM32L only */
 };
 /* Must be volatile, or compiler optimizes out repeated accesses */
 typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
@@ -513,125 +507,124 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
 #define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE)
 #define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE)
 
-#define STM32_SPI_CR1_BIDIMODE		BIT(15)
-#define STM32_SPI_CR1_BIDIOE		BIT(14)
-#define STM32_SPI_CR1_CRCEN		BIT(13)
-#define STM32_SPI_CR1_SSM		BIT(9)
-#define STM32_SPI_CR1_SSI		BIT(8)
-#define STM32_SPI_CR1_LSBFIRST		BIT(7)
-#define STM32_SPI_CR1_SPE		BIT(6)
-#define STM32_SPI_CR1_BR_DIV64R		(5 << 3)
-#define STM32_SPI_CR1_BR_DIV4R		BIT(3)
-#define STM32_SPI_CR1_MSTR		BIT(2)
-#define STM32_SPI_CR1_CPOL		BIT(1)
-#define STM32_SPI_CR1_CPHA		BIT(0)
-#define STM32_SPI_CR2_FRXTH		BIT(12)
-#define STM32_SPI_CR2_DATASIZE(n)	(((n) - 1) << 8)
-#define STM32_SPI_CR2_TXEIE		BIT(7)
-#define STM32_SPI_CR2_RXNEIE		BIT(6)
-#define STM32_SPI_CR2_NSSP		BIT(3)
-#define STM32_SPI_CR2_SSOE		BIT(2)
-#define STM32_SPI_CR2_TXDMAEN		BIT(1)
-#define STM32_SPI_CR2_RXDMAEN		BIT(0)
-
-#define STM32_SPI_SR_RXNE		BIT(0)
-#define STM32_SPI_SR_TXE		BIT(1)
-#define STM32_SPI_SR_CRCERR		BIT(4)
-#define STM32_SPI_SR_BSY		BIT(7)
-#define STM32_SPI_SR_FRLVL		(3 << 9)
-#define STM32_SPI_SR_FTLVL		(3 << 11)
+#define STM32_SPI_CR1_BIDIMODE BIT(15)
+#define STM32_SPI_CR1_BIDIOE BIT(14)
+#define STM32_SPI_CR1_CRCEN BIT(13)
+#define STM32_SPI_CR1_SSM BIT(9)
+#define STM32_SPI_CR1_SSI BIT(8)
+#define STM32_SPI_CR1_LSBFIRST BIT(7)
+#define STM32_SPI_CR1_SPE BIT(6)
+#define STM32_SPI_CR1_BR_DIV64R (5 << 3)
+#define STM32_SPI_CR1_BR_DIV4R BIT(3)
+#define STM32_SPI_CR1_MSTR BIT(2)
+#define STM32_SPI_CR1_CPOL BIT(1)
+#define STM32_SPI_CR1_CPHA BIT(0)
+#define STM32_SPI_CR2_FRXTH BIT(12)
+#define STM32_SPI_CR2_DATASIZE(n) (((n)-1) << 8)
+#define STM32_SPI_CR2_TXEIE BIT(7)
+#define STM32_SPI_CR2_RXNEIE BIT(6)
+#define STM32_SPI_CR2_NSSP BIT(3)
+#define STM32_SPI_CR2_SSOE BIT(2)
+#define STM32_SPI_CR2_TXDMAEN BIT(1)
+#define STM32_SPI_CR2_RXDMAEN BIT(0)
+
+#define STM32_SPI_SR_RXNE BIT(0)
+#define STM32_SPI_SR_TXE BIT(1)
+#define STM32_SPI_SR_CRCERR BIT(4)
+#define STM32_SPI_SR_BSY BIT(7)
+#define STM32_SPI_SR_FRLVL (3 << 9)
+#define STM32_SPI_SR_FTLVL (3 << 11)
 /* --- Debug --- */
-#define STM32_DBGMCU_APB1FZ         REG32(STM32_DBGMCU_BASE + 0x08)
-#define STM32_DBGMCU_APB2FZ         REG32(STM32_DBGMCU_BASE + 0x0C)
+#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08)
+#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C)
 
 /* --- Flash --- */
-#define STM32_FLASH_ACR             REG32(STM32_FLASH_REGS_BASE + 0x00)
+#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00)
 #define STM32_FLASH_ACR_LATENCY_SHIFT (0)
-#define STM32_FLASH_ACR_LATENCY_MASK  (7 << STM32_FLASH_ACR_LATENCY_SHIFT)
-#define STM32_FLASH_ACR_LATENCY     BIT(0)
-#define STM32_FLASH_ACR_PRFTEN      BIT(4)
-#define STM32_FLASH_KEYR            REG32(STM32_FLASH_REGS_BASE + 0x04)
-#define  FLASH_KEYR_KEY1                0x45670123
-#define  FLASH_KEYR_KEY2                0xCDEF89AB
-
-#define STM32_FLASH_OPTKEYR         REG32(STM32_FLASH_REGS_BASE + 0x08)
-#define  FLASH_OPTKEYR_KEY1             FLASH_KEYR_KEY1
-#define  FLASH_OPTKEYR_KEY2             FLASH_KEYR_KEY2
-#define STM32_FLASH_SR              REG32(STM32_FLASH_REGS_BASE + 0x0c)
-#define  FLASH_SR_BUSY                  BIT(0)
-#define  FLASH_SR_PGERR                 BIT(2)
-#define  FLASH_SR_WRPRTERR              BIT(4)
-#define  FLASH_SR_ALL_ERR \
-	(FLASH_SR_PGERR | FLASH_SR_WRPRTERR)
-#define  FLASH_SR_EOP                   BIT(5)
-#define STM32_FLASH_CR              REG32(STM32_FLASH_REGS_BASE + 0x10)
-#define  FLASH_CR_PG                    BIT(0)
-#define  FLASH_CR_PER                   BIT(1)
-#define  FLASH_CR_OPTPG                 BIT(4)
-#define  FLASH_CR_OPTER                 BIT(5)
-#define  FLASH_CR_STRT                  BIT(6)
-#define  FLASH_CR_LOCK                  BIT(7)
-#define  FLASH_CR_OPTWRE                BIT(9)
-#define  FLASH_CR_OBL_LAUNCH            BIT(13)
-#define STM32_FLASH_OPT_LOCKED      (!(STM32_FLASH_CR & FLASH_CR_OPTWRE))
-#define STM32_FLASH_AR              REG32(STM32_FLASH_REGS_BASE + 0x14)
-#define STM32_FLASH_OBR             REG32(STM32_FLASH_REGS_BASE + 0x1c)
-#define STM32_FLASH_OBR_RDP_MASK        (3 << 1)
-#define STM32_FLASH_WRPR            REG32(STM32_FLASH_REGS_BASE + 0x20)
-
-#define STM32_OPTB_RDP_OFF              0x00
-#define STM32_OPTB_USER_OFF             0x02
-#define STM32_OPTB_WRP_OFF(n)           (0x08 + (n&3) * 2)
-#define STM32_OPTB_WRP01                0x08
-#define STM32_OPTB_WRP23                0x0c
-
-#define STM32_OPTB_COMPL_SHIFT      8
+#define STM32_FLASH_ACR_LATENCY_MASK (7 << STM32_FLASH_ACR_LATENCY_SHIFT)
+#define STM32_FLASH_ACR_LATENCY BIT(0)
+#define STM32_FLASH_ACR_PRFTEN BIT(4)
+#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x04)
+#define FLASH_KEYR_KEY1 0x45670123
+#define FLASH_KEYR_KEY2 0xCDEF89AB
+
+#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x08)
+#define FLASH_OPTKEYR_KEY1 FLASH_KEYR_KEY1
+#define FLASH_OPTKEYR_KEY2 FLASH_KEYR_KEY2
+#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x0c)
+#define FLASH_SR_BUSY BIT(0)
+#define FLASH_SR_PGERR BIT(2)
+#define FLASH_SR_WRPRTERR BIT(4)
+#define FLASH_SR_ALL_ERR (FLASH_SR_PGERR | FLASH_SR_WRPRTERR)
+#define FLASH_SR_EOP BIT(5)
+#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x10)
+#define FLASH_CR_PG BIT(0)
+#define FLASH_CR_PER BIT(1)
+#define FLASH_CR_OPTPG BIT(4)
+#define FLASH_CR_OPTER BIT(5)
+#define FLASH_CR_STRT BIT(6)
+#define FLASH_CR_LOCK BIT(7)
+#define FLASH_CR_OPTWRE BIT(9)
+#define FLASH_CR_OBL_LAUNCH BIT(13)
+#define STM32_FLASH_OPT_LOCKED (!(STM32_FLASH_CR & FLASH_CR_OPTWRE))
+#define STM32_FLASH_AR REG32(STM32_FLASH_REGS_BASE + 0x14)
+#define STM32_FLASH_OBR REG32(STM32_FLASH_REGS_BASE + 0x1c)
+#define STM32_FLASH_OBR_RDP_MASK (3 << 1)
+#define STM32_FLASH_WRPR REG32(STM32_FLASH_REGS_BASE + 0x20)
+
+#define STM32_OPTB_RDP_OFF 0x00
+#define STM32_OPTB_USER_OFF 0x02
+#define STM32_OPTB_WRP_OFF(n) (0x08 + (n & 3) * 2)
+#define STM32_OPTB_WRP01 0x08
+#define STM32_OPTB_WRP23 0x0c
+
+#define STM32_OPTB_COMPL_SHIFT 8
 
 /* --- External Interrupts --- */
-#define STM32_EXTI_IMR              REG32(STM32_EXTI_BASE + 0x00)
-#define STM32_EXTI_EMR              REG32(STM32_EXTI_BASE + 0x04)
-#define STM32_EXTI_RTSR             REG32(STM32_EXTI_BASE + 0x08)
-#define STM32_EXTI_FTSR             REG32(STM32_EXTI_BASE + 0x0c)
-#define STM32_EXTI_SWIER            REG32(STM32_EXTI_BASE + 0x10)
-#define STM32_EXTI_PR               REG32(STM32_EXTI_BASE + 0x14)
+#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00)
+#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04)
+#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08)
+#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c)
+#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10)
+#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14)
 
 #define EXTI_RTC_ALR_EVENT BIT(17)
 
 /* --- ADC --- */
 #ifdef CHIP_VARIANT_STM32F373
-#define STM32_ADC_SR               REG32(STM32_ADC1_BASE + 0x00)
-#define STM32_ADC_CR1              REG32(STM32_ADC1_BASE + 0x04)
-#define STM32_ADC_CR2              REG32(STM32_ADC1_BASE + 0x08)
-#define STM32_ADC_CR2_ADON         BIT(0)
-#define STM32_ADC_CR2_CONT         BIT(1)
-#define STM32_ADC_CR2_CAL          BIT(2)
-#define STM32_ADC_CR2_RSTCAL       BIT(3)
-#define STM32_ADC_CR2_ALIGN        BIT(11)
-#define STM32_ADC_CR2_SWSTART      BIT(30)
-#define STM32_ADC_SMPR1            REG32(STM32_ADC1_BASE + 0x0C)
-#define STM32_ADC_SMPR2            REG32(STM32_ADC1_BASE + 0x10)
-#define STM32_ADC_JOFR(n)          REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4)
-#define STM32_ADC_HTR              REG32(STM32_ADC1_BASE + 0x24)
-#define STM32_ADC_LTR              REG32(STM32_ADC1_BASE + 0x28)
-#define STM32_ADC_SQR(n)           REG32(STM32_ADC1_BASE + 0x28 + ((n)&3) * 4)
-#define STM32_ADC_SQR1             REG32(STM32_ADC1_BASE + 0x2C)
-#define STM32_ADC_SQR2             REG32(STM32_ADC1_BASE + 0x30)
-#define STM32_ADC_SQR3             REG32(STM32_ADC1_BASE + 0x34)
-#define STM32_ADC_JSQR             REG32(STM32_ADC1_BASE + 0x38)
-#define STM32_ADC_JDR(n)           REG32(STM32_ADC1_BASE + 0x3C + ((n)&3) * 4)
-#define STM32_ADC_DR               REG32(STM32_ADC1_BASE + 0x4C)
+#define STM32_ADC_SR REG32(STM32_ADC1_BASE + 0x00)
+#define STM32_ADC_CR1 REG32(STM32_ADC1_BASE + 0x04)
+#define STM32_ADC_CR2 REG32(STM32_ADC1_BASE + 0x08)
+#define STM32_ADC_CR2_ADON BIT(0)
+#define STM32_ADC_CR2_CONT BIT(1)
+#define STM32_ADC_CR2_CAL BIT(2)
+#define STM32_ADC_CR2_RSTCAL BIT(3)
+#define STM32_ADC_CR2_ALIGN BIT(11)
+#define STM32_ADC_CR2_SWSTART BIT(30)
+#define STM32_ADC_SMPR1 REG32(STM32_ADC1_BASE + 0x0C)
+#define STM32_ADC_SMPR2 REG32(STM32_ADC1_BASE + 0x10)
+#define STM32_ADC_JOFR(n) REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4)
+#define STM32_ADC_HTR REG32(STM32_ADC1_BASE + 0x24)
+#define STM32_ADC_LTR REG32(STM32_ADC1_BASE + 0x28)
+#define STM32_ADC_SQR(n) REG32(STM32_ADC1_BASE + 0x28 + ((n)&3) * 4)
+#define STM32_ADC_SQR1 REG32(STM32_ADC1_BASE + 0x2C)
+#define STM32_ADC_SQR2 REG32(STM32_ADC1_BASE + 0x30)
+#define STM32_ADC_SQR3 REG32(STM32_ADC1_BASE + 0x34)
+#define STM32_ADC_JSQR REG32(STM32_ADC1_BASE + 0x38)
+#define STM32_ADC_JDR(n) REG32(STM32_ADC1_BASE + 0x3C + ((n)&3) * 4)
+#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x4C)
 #endif
 
 /* --- Comparators --- */
-#define STM32_COMP_CSR              REG32(STM32_COMP_BASE + 0x1C)
+#define STM32_COMP_CSR REG32(STM32_COMP_BASE + 0x1C)
 
-#define STM32_COMP_CMP2LOCK            BIT(31)
-#define STM32_COMP_CMP2OUT             BIT(30)
-#define STM32_COMP_CMP2HYST_HI         (3 << 28)
-#define STM32_COMP_CMP2HYST_MED        (2 << 28)
-#define STM32_COMP_CMP2HYST_LOW        (1 << 28)
-#define STM32_COMP_CMP2HYST_NO         (0 << 28)
-#define STM32_COMP_CMP2POL             BIT(27)
+#define STM32_COMP_CMP2LOCK BIT(31)
+#define STM32_COMP_CMP2OUT BIT(30)
+#define STM32_COMP_CMP2HYST_HI (3 << 28)
+#define STM32_COMP_CMP2HYST_MED (2 << 28)
+#define STM32_COMP_CMP2HYST_LOW (1 << 28)
+#define STM32_COMP_CMP2HYST_NO (0 << 28)
+#define STM32_COMP_CMP2POL BIT(27)
 
 #define STM32_COMP_CMP2OUTSEL_TIM3_OCR (7 << 24)
 #define STM32_COMP_CMP2OUTSEL_TIM3_IC1 (6 << 24)
@@ -646,32 +639,32 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
 #define STM32_COMP_CMP2OUTSEL_TIM1_IC1 (2 << 24)
 #define STM32_COMP_CMP2OUTSEL_TIM1_BRK (1 << 24)
 #endif
-#define STM32_COMP_CMP2OUTSEL_NONE     (0 << 24)
-#define STM32_COMP_WNDWEN              BIT(23)
-
-#define STM32_COMP_CMP2INSEL_MASK      (7 << 20)
-#define STM32_COMP_CMP2INSEL_INM7      (6 << 20) /* STM32F373 only */
-#define STM32_COMP_CMP2INSEL_INM6      (6 << 20)
-#define STM32_COMP_CMP2INSEL_INM5      (5 << 20)
-#define STM32_COMP_CMP2INSEL_INM4      (4 << 20)
-#define STM32_COMP_CMP2INSEL_VREF      (3 << 20)
-#define STM32_COMP_CMP2INSEL_VREF34    (2 << 20)
-#define STM32_COMP_CMP2INSEL_VREF12    (1 << 20)
-#define STM32_COMP_CMP2INSEL_VREF14    (0 << 20)
-
-#define STM32_COMP_CMP2MODE_VLSPEED    (3 << 18)
-#define STM32_COMP_CMP2MODE_LSPEED     (2 << 18)
-#define STM32_COMP_CMP2MODE_MSPEED     (1 << 18)
-#define STM32_COMP_CMP2MODE_HSPEED     (0 << 18)
-#define STM32_COMP_CMP2EN              BIT(16)
-
-#define STM32_COMP_CMP1LOCK            BIT(15)
-#define STM32_COMP_CMP1OUT             BIT(14)
-#define STM32_COMP_CMP1HYST_HI         (3 << 12)
-#define STM32_COMP_CMP1HYST_MED        (2 << 12)
-#define STM32_COMP_CMP1HYST_LOW        (1 << 12)
-#define STM32_COMP_CMP1HYST_NO         (0 << 12)
-#define STM32_COMP_CMP1POL             BIT(11)
+#define STM32_COMP_CMP2OUTSEL_NONE (0 << 24)
+#define STM32_COMP_WNDWEN BIT(23)
+
+#define STM32_COMP_CMP2INSEL_MASK (7 << 20)
+#define STM32_COMP_CMP2INSEL_INM7 (6 << 20) /* STM32F373 only */
+#define STM32_COMP_CMP2INSEL_INM6 (6 << 20)
+#define STM32_COMP_CMP2INSEL_INM5 (5 << 20)
+#define STM32_COMP_CMP2INSEL_INM4 (4 << 20)
+#define STM32_COMP_CMP2INSEL_VREF (3 << 20)
+#define STM32_COMP_CMP2INSEL_VREF34 (2 << 20)
+#define STM32_COMP_CMP2INSEL_VREF12 (1 << 20)
+#define STM32_COMP_CMP2INSEL_VREF14 (0 << 20)
+
+#define STM32_COMP_CMP2MODE_VLSPEED (3 << 18)
+#define STM32_COMP_CMP2MODE_LSPEED (2 << 18)
+#define STM32_COMP_CMP2MODE_MSPEED (1 << 18)
+#define STM32_COMP_CMP2MODE_HSPEED (0 << 18)
+#define STM32_COMP_CMP2EN BIT(16)
+
+#define STM32_COMP_CMP1LOCK BIT(15)
+#define STM32_COMP_CMP1OUT BIT(14)
+#define STM32_COMP_CMP1HYST_HI (3 << 12)
+#define STM32_COMP_CMP1HYST_MED (2 << 12)
+#define STM32_COMP_CMP1HYST_LOW (1 << 12)
+#define STM32_COMP_CMP1HYST_NO (0 << 12)
+#define STM32_COMP_CMP1POL BIT(11)
 
 #ifdef CHIP_VARIANT_STM32F373
 #define STM32_COMP_CMP1OUTSEL_TIM5_OCR (7 << 8)
@@ -690,25 +683,24 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
 #define STM32_COMP_CMP1OUTSEL_TIM1_IC1 (2 << 8)
 #define STM32_COMP_CMP1OUTSEL_TIM1_BRK (1 << 8)
 #endif
-#define STM32_COMP_CMP1OUTSEL_NONE     (0 << 8)
-
-#define STM32_COMP_CMP1INSEL_MASK      (7 << 4)
-#define STM32_COMP_CMP1INSEL_INM7      (7 << 4) /* STM32F373 only */
-#define STM32_COMP_CMP1INSEL_INM6      (6 << 4)
-#define STM32_COMP_CMP1INSEL_INM5      (5 << 4)
-#define STM32_COMP_CMP1INSEL_INM4      (4 << 4)
-#define STM32_COMP_CMP1INSEL_VREF      (3 << 4)
-#define STM32_COMP_CMP1INSEL_VREF34    (2 << 4)
-#define STM32_COMP_CMP1INSEL_VREF12    (1 << 4)
-#define STM32_COMP_CMP1INSEL_VREF14    (0 << 4)
-
-#define STM32_COMP_CMP1MODE_VLSPEED    (3 << 2)
-#define STM32_COMP_CMP1MODE_LSPEED     (2 << 2)
-#define STM32_COMP_CMP1MODE_MSPEED     (1 << 2)
-#define STM32_COMP_CMP1MODE_HSPEED     (0 << 2)
-#define STM32_COMP_CMP1SW1             BIT(1)
-#define STM32_COMP_CMP1EN              BIT(0)
-
+#define STM32_COMP_CMP1OUTSEL_NONE (0 << 8)
+
+#define STM32_COMP_CMP1INSEL_MASK (7 << 4)
+#define STM32_COMP_CMP1INSEL_INM7 (7 << 4) /* STM32F373 only */
+#define STM32_COMP_CMP1INSEL_INM6 (6 << 4)
+#define STM32_COMP_CMP1INSEL_INM5 (5 << 4)
+#define STM32_COMP_CMP1INSEL_INM4 (4 << 4)
+#define STM32_COMP_CMP1INSEL_VREF (3 << 4)
+#define STM32_COMP_CMP1INSEL_VREF34 (2 << 4)
+#define STM32_COMP_CMP1INSEL_VREF12 (1 << 4)
+#define STM32_COMP_CMP1INSEL_VREF14 (0 << 4)
+
+#define STM32_COMP_CMP1MODE_VLSPEED (3 << 2)
+#define STM32_COMP_CMP1MODE_LSPEED (2 << 2)
+#define STM32_COMP_CMP1MODE_MSPEED (1 << 2)
+#define STM32_COMP_CMP1MODE_HSPEED (0 << 2)
+#define STM32_COMP_CMP1SW1 BIT(1)
+#define STM32_COMP_CMP1EN BIT(0)
 
 /* --- DMA --- */
 
@@ -779,11 +771,11 @@ enum dma_channel {
 
 /* Registers for a single channel of the DMA controller */
 struct stm32_dma_chan {
-	uint32_t	ccr;		/* Control */
-	uint32_t	cndtr;		/* Number of data to transfer */
-	uint32_t	cpar;		/* Peripheral address */
-	uint32_t	cmar;		/* Memory address */
-	uint32_t	reserved;
+	uint32_t ccr; /* Control */
+	uint32_t cndtr; /* Number of data to transfer */
+	uint32_t cpar; /* Peripheral address */
+	uint32_t cmar; /* Memory address */
+	uint32_t reserved;
 };
 
 /* Always use stm32_dma_chan_t so volatile keyword is included! */
@@ -794,8 +786,8 @@ typedef stm32_dma_chan_t dma_chan_t;
 
 /* Registers for the DMA controller */
 struct stm32_dma_regs {
-	uint32_t	isr;
-	uint32_t	ifcr;
+	uint32_t isr;
+	uint32_t ifcr;
 	stm32_dma_chan_t chan[STM32_DMAC_COUNT];
 };
 
@@ -804,210 +796,130 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
 
 #define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE)
 
-
-#define STM32_DMA_CCR_CHANNEL(channel)		 (0)
+#define STM32_DMA_CCR_CHANNEL(channel) (0)
 
 #define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE)
 #define STM32_DMA_REGS(channel) \
 	((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_REGS : STM32_DMA2_REGS)
-#define STM32_DMA_CSELR(channel) \
-	REG32(((channel) < STM32_DMAC_PER_CTLR ? \
-			STM32_DMA1_BASE : STM32_DMA2_BASE)  + 0xA8)
+#define STM32_DMA_CSELR(channel)                                    \
+	REG32(((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_BASE :  \
+						 STM32_DMA2_BASE) + \
+	      0xA8)
 
 /* Bits for DMA controller regs (isr and ifcr) */
-#define STM32_DMA_CH_OFFSET(channel)   (4 * ((channel) % STM32_DMAC_PER_CTLR))
+#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR))
 #define STM32_DMA_ISR_MASK(channel, mask) \
 	((mask) << STM32_DMA_CH_OFFSET(channel))
-#define STM32_DMA_ISR_GIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(0))
-#define STM32_DMA_ISR_TCIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(1))
-#define STM32_DMA_ISR_HTIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(2))
-#define STM32_DMA_ISR_TEIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(3))
-#define STM32_DMA_ISR_ALL(channel)	STM32_DMA_ISR_MASK(channel, 0x0f)
-
-#define STM32_DMA_GIF                   BIT(0)
-#define STM32_DMA_TCIF                  BIT(1)
-#define STM32_DMA_HTIF                  BIT(2)
-#define STM32_DMA_TEIF                  BIT(3)
-#define STM32_DMA_ALL                   0xf
-
-#define STM32_DMA_GET_ISR(channel)      \
-	((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_ISR(channel, val) \
-	(STM32_DMA_REGS(channel)->isr = \
-	((STM32_DMA_REGS(channel)->isr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-#define STM32_DMA_GET_IFCR(channel)      \
-	((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_IFCR(channel, val) \
-	(STM32_DMA_REGS(channel)->ifcr = \
-	((STM32_DMA_REGS(channel)->ifcr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-
+#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0))
+#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1))
+#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2))
+#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3))
+#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f)
+
+#define STM32_DMA_GIF BIT(0)
+#define STM32_DMA_TCIF BIT(1)
+#define STM32_DMA_HTIF BIT(2)
+#define STM32_DMA_TEIF BIT(3)
+#define STM32_DMA_ALL 0xf
+
+#define STM32_DMA_GET_ISR(channel)                                        \
+	((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) & \
+	 STM32_DMA_ALL)
+#define STM32_DMA_SET_ISR(channel, val)                                \
+	(STM32_DMA_REGS(channel)->isr =                                \
+		 ((STM32_DMA_REGS(channel)->isr &                      \
+		   ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
+		  (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
+#define STM32_DMA_GET_IFCR(channel)                                        \
+	((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) & \
+	 STM32_DMA_ALL)
+#define STM32_DMA_SET_IFCR(channel, val)                               \
+	(STM32_DMA_REGS(channel)->ifcr =                               \
+		 ((STM32_DMA_REGS(channel)->ifcr &                     \
+		   ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
+		  (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
 
 /* Bits for DMA channel regs */
-#define STM32_DMA_CCR_EN		BIT(0)
-#define STM32_DMA_CCR_TCIE		BIT(1)
-#define STM32_DMA_CCR_HTIE		BIT(2)
-#define STM32_DMA_CCR_TEIE		BIT(3)
-#define STM32_DMA_CCR_DIR		BIT(4)
-#define STM32_DMA_CCR_CIRC		BIT(5)
-#define STM32_DMA_CCR_PINC		BIT(6)
-#define STM32_DMA_CCR_MINC		BIT(7)
-#define STM32_DMA_CCR_PSIZE_8_BIT	(0 << 8)
-#define STM32_DMA_CCR_PSIZE_16_BIT	(1 << 8)
-#define STM32_DMA_CCR_PSIZE_32_BIT	(2 << 8)
-#define STM32_DMA_CCR_MSIZE_8_BIT	(0 << 10)
-#define STM32_DMA_CCR_MSIZE_16_BIT	(1 << 10)
-#define STM32_DMA_CCR_MSIZE_32_BIT	(2 << 10)
-#define STM32_DMA_CCR_PL_LOW		(0 << 12)
-#define STM32_DMA_CCR_PL_MEDIUM		(1 << 12)
-#define STM32_DMA_CCR_PL_HIGH		(2 << 12)
-#define STM32_DMA_CCR_PL_VERY_HIGH	(3 << 12)
-#define STM32_DMA_CCR_MEM2MEM		BIT(14)
-
+#define STM32_DMA_CCR_EN BIT(0)
+#define STM32_DMA_CCR_TCIE BIT(1)
+#define STM32_DMA_CCR_HTIE BIT(2)
+#define STM32_DMA_CCR_TEIE BIT(3)
+#define STM32_DMA_CCR_DIR BIT(4)
+#define STM32_DMA_CCR_CIRC BIT(5)
+#define STM32_DMA_CCR_PINC BIT(6)
+#define STM32_DMA_CCR_MINC BIT(7)
+#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8)
+#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8)
+#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8)
+#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10)
+#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10)
+#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10)
+#define STM32_DMA_CCR_PL_LOW (0 << 12)
+#define STM32_DMA_CCR_PL_MEDIUM (1 << 12)
+#define STM32_DMA_CCR_PL_HIGH (2 << 12)
+#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12)
+#define STM32_DMA_CCR_MEM2MEM BIT(14)
 
 /* --- CRC --- */
-#define STM32_CRC_DR                REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR32              REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR16              REG16(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR8               REG8(STM32_CRC_BASE + 0x0)
-
-#define STM32_CRC_IDR               REG32(STM32_CRC_BASE + 0x4)
-#define STM32_CRC_CR                REG32(STM32_CRC_BASE + 0x8)
-#define STM32_CRC_INIT              REG32(STM32_CRC_BASE + 0x10)
-#define STM32_CRC_POL               REG32(STM32_CRC_BASE + 0x14)
-
-#define STM32_CRC_CR_RESET          BIT(0)
-#define STM32_CRC_CR_POLYSIZE_32    (0 << 3)
-#define STM32_CRC_CR_POLYSIZE_16    (1 << 3)
-#define STM32_CRC_CR_POLYSIZE_8     (2 << 3)
-#define STM32_CRC_CR_POLYSIZE_7     (3 << 3)
-#define STM32_CRC_CR_REV_IN_BYTE    (1 << 5)
-#define STM32_CRC_CR_REV_IN_HWORD   (2 << 5)
-#define STM32_CRC_CR_REV_IN_WORD    (3 << 5)
-#define STM32_CRC_CR_REV_OUT        BIT(7)
+#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0)
+
+#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4)
+#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8)
+#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10)
+#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14)
+
+#define STM32_CRC_CR_RESET BIT(0)
+#define STM32_CRC_CR_POLYSIZE_32 (0 << 3)
+#define STM32_CRC_CR_POLYSIZE_16 (1 << 3)
+#define STM32_CRC_CR_POLYSIZE_8 (2 << 3)
+#define STM32_CRC_CR_POLYSIZE_7 (3 << 3)
+#define STM32_CRC_CR_REV_IN_BYTE (1 << 5)
+#define STM32_CRC_CR_REV_IN_HWORD (2 << 5)
+#define STM32_CRC_CR_REV_IN_WORD (3 << 5)
+#define STM32_CRC_CR_REV_OUT BIT(7)
 
 /* --- PMSE --- */
-#define STM32_PMSE_ARCR             REG32(STM32_PMSE_BASE + 0x0)
-#define STM32_PMSE_ACCR             REG32(STM32_PMSE_BASE + 0x4)
-#define STM32_PMSE_CR               REG32(STM32_PMSE_BASE + 0x8)
-#define STM32_PMSE_CRTDR            REG32(STM32_PMSE_BASE + 0x14)
-#define STM32_PMSE_IER              REG32(STM32_PMSE_BASE + 0x18)
-#define STM32_PMSE_SR               REG32(STM32_PMSE_BASE + 0x1c)
-#define STM32_PMSE_IFCR             REG32(STM32_PMSE_BASE + 0x20)
-#define STM32_PMSE_PxPMR(x)         REG32(STM32_PMSE_BASE + 0x2c + (x) * 4)
-#define STM32_PMSE_PAPMR            REG32(STM32_PMSE_BASE + 0x2c)
-#define STM32_PMSE_PBPMR            REG32(STM32_PMSE_BASE + 0x30)
-#define STM32_PMSE_PCPMR            REG32(STM32_PMSE_BASE + 0x34)
-#define STM32_PMSE_PDPMR            REG32(STM32_PMSE_BASE + 0x38)
-#define STM32_PMSE_PEPMR            REG32(STM32_PMSE_BASE + 0x3c)
-#define STM32_PMSE_PFPMR            REG32(STM32_PMSE_BASE + 0x40)
-#define STM32_PMSE_PGPMR            REG32(STM32_PMSE_BASE + 0x44)
-#define STM32_PMSE_PHPMR            REG32(STM32_PMSE_BASE + 0x48)
-#define STM32_PMSE_PIPMR            REG32(STM32_PMSE_BASE + 0x4c)
-#define STM32_PMSE_MRCR             REG32(STM32_PMSE_BASE + 0x100)
-#define STM32_PMSE_MCCR             REG32(STM32_PMSE_BASE + 0x104)
-
-/* --- USB --- */
-#define STM32_USB_EP(n)            REG16(STM32_USB_FS_BASE + (n) * 4)
-
-#define STM32_USB_CNTR             REG16(STM32_USB_FS_BASE + 0x40)
-
-#define STM32_USB_CNTR_FRES	    BIT(0)
-#define STM32_USB_CNTR_PDWN	    BIT(1)
-#define STM32_USB_CNTR_LP_MODE	    BIT(2)
-#define STM32_USB_CNTR_FSUSP	    BIT(3)
-#define STM32_USB_CNTR_RESUME	    BIT(4)
-#define STM32_USB_CNTR_L1RESUME	    BIT(5)
-#define STM32_USB_CNTR_L1REQM	    BIT(7)
-#define STM32_USB_CNTR_ESOFM	    BIT(8)
-#define STM32_USB_CNTR_SOFM	    BIT(9)
-#define STM32_USB_CNTR_RESETM	    BIT(10)
-#define STM32_USB_CNTR_SUSPM	    BIT(11)
-#define STM32_USB_CNTR_WKUPM	    BIT(12)
-#define STM32_USB_CNTR_ERRM	    BIT(13)
-#define STM32_USB_CNTR_PMAOVRM	    BIT(14)
-#define STM32_USB_CNTR_CTRM	    BIT(15)
-
-#define STM32_USB_ISTR             REG16(STM32_USB_FS_BASE + 0x44)
-
-#define STM32_USB_ISTR_EP_ID_MASK   (0x000f)
-#define STM32_USB_ISTR_DIR	    BIT(4)
-#define STM32_USB_ISTR_L1REQ	    BIT(7)
-#define STM32_USB_ISTR_ESOF	    BIT(8)
-#define STM32_USB_ISTR_SOF	    BIT(9)
-#define STM32_USB_ISTR_RESET	    BIT(10)
-#define STM32_USB_ISTR_SUSP	    BIT(11)
-#define STM32_USB_ISTR_WKUP	    BIT(12)
-#define STM32_USB_ISTR_ERR	    BIT(13)
-#define STM32_USB_ISTR_PMAOVR	    BIT(14)
-#define STM32_USB_ISTR_CTR	    BIT(15)
-
-#define STM32_USB_FNR              REG16(STM32_USB_FS_BASE + 0x48)
-
-#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14)
-#define STM32_USB_FNR_RXDP_RXDM_MASK  (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT)
-
-#define STM32_USB_DADDR            REG16(STM32_USB_FS_BASE + 0x4C)
-#define STM32_USB_BTABLE           REG16(STM32_USB_FS_BASE + 0x50)
-#define STM32_USB_LPMCSR           REG16(STM32_USB_FS_BASE + 0x54)
-#define STM32_USB_BCDR             REG16(STM32_USB_FS_BASE + 0x58)
-
-#define STM32_USB_BCDR_BCDEN	    BIT(0)
-#define STM32_USB_BCDR_DCDEN	    BIT(1)
-#define STM32_USB_BCDR_PDEN	    BIT(2)
-#define STM32_USB_BCDR_SDEN	    BIT(3)
-#define STM32_USB_BCDR_DCDET	    BIT(4)
-#define STM32_USB_BCDR_PDET	    BIT(5)
-#define STM32_USB_BCDR_SDET	    BIT(6)
-#define STM32_USB_BCDR_PS2DET	    BIT(7)
-
-#define EP_MASK     0x0F0F
-#define EP_TX_DTOG  0x0040
-#define EP_TX_MASK  0x0030
-#define EP_TX_VALID 0x0030
-#define EP_TX_NAK   0x0020
-#define EP_TX_STALL 0x0010
-#define EP_TX_DISAB 0x0000
-#define EP_RX_DTOG  0x4000
-#define EP_RX_MASK  0x3000
-#define EP_RX_VALID 0x3000
-#define EP_RX_NAK   0x2000
-#define EP_RX_STALL 0x1000
-#define EP_RX_DISAB 0x0000
-
-#define EP_STATUS_OUT 0x0100
-
-#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK)
-#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID)
-
-#define STM32_TOGGLE_EP(n, mask, val, flags) \
-	STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \
-			^ (val)) | (flags))
+#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0)
+#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4)
+#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8)
+#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14)
+#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18)
+#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c)
+#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20)
+#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x)*4)
+#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c)
+#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30)
+#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34)
+#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38)
+#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c)
+#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40)
+#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44)
+#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48)
+#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c)
+#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100)
+#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104)
 
 /* --- TRNG --- */
-#define STM32_RNG_CR                REG32(STM32_RNG_BASE + 0x0)
-#define STM32_RNG_CR_RNGEN          BIT(2)
-#define STM32_RNG_CR_IE             BIT(3)
-#define STM32_RNG_CR_CED            BIT(5)
-#define STM32_RNG_SR                REG32(STM32_RNG_BASE + 0x4)
-#define STM32_RNG_SR_DRDY           BIT(0)
-#define STM32_RNG_DR                REG32(STM32_RNG_BASE + 0x8)
+#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0)
+#define STM32_RNG_CR_RNGEN BIT(2)
+#define STM32_RNG_CR_IE BIT(3)
+#define STM32_RNG_CR_CED BIT(5)
+#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4)
+#define STM32_RNG_SR_DRDY BIT(0)
+#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8)
 
 /* --- AXI interconnect --- */
 
 /* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */
-#define STM32_AXI_TARG_FN_MOD(x)    REG32(STM32_GPV_BASE + 0x1108 + \
-					  0x1000 * (x))
-#define  WRITE_ISS_OVERRIDE         BIT(1)
-#define  READ_ISS_OVERRIDE          BIT(0)
+#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + 0x1000 * (x))
+#define WRITE_ISS_OVERRIDE BIT(1)
+#define READ_ISS_OVERRIDE BIT(0)
 
 /* --- MISC --- */
-#define STM32_UNIQUE_ID_ADDRESS     REG32_ADDR(STM32_UNIQUE_ID_BASE)
-#define STM32_UNIQUE_ID_LENGTH      (3 * 4)
+#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE)
+#define STM32_UNIQUE_ID_LENGTH (3 * 4)
 
 #endif /* !__ASSEMBLER__ */
diff --git a/chip/stm32/registers-stm32f4.h b/chip/stm32/registers-stm32f4.h
index 12bfe31063..a415b80d5c 100644
--- a/chip/stm32/registers-stm32f4.h
+++ b/chip/stm32/registers-stm32f4.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,104 +22,103 @@
 #endif
 
 /* --- IRQ numbers --- */
-#define STM32_IRQ_WWDG             0
-#define STM32_IRQ_PVD              1
-#define STM32_IRQ_TAMPER_STAMP     2
-#define STM32_IRQ_RTC_WAKEUP       3
-#define STM32_IRQ_FLASH            4
-#define STM32_IRQ_RCC              5
-#define STM32_IRQ_EXTI0            6
-#define STM32_IRQ_EXTI1            7
-#define STM32_IRQ_EXTI2            8
-#define STM32_IRQ_EXTI3            9
-#define STM32_IRQ_EXTI4           10
-#define STM32_IRQ_DMA_CHANNEL_1   11
-#define STM32_IRQ_DMA_CHANNEL_2   12
-#define STM32_IRQ_DMA_CHANNEL_3   13
-#define STM32_IRQ_DMA_CHANNEL_4   14
-#define STM32_IRQ_DMA_CHANNEL_5   15
-#define STM32_IRQ_DMA_CHANNEL_6   16
-#define STM32_IRQ_DMA_CHANNEL_7   17
-#define STM32_IRQ_USB_HP          19
-#define STM32_IRQ_USB_LP          20
-
-#define STM32_IRQ_ADC1            18 /* STM32L4 only */
-#define STM32_IRQ_CAN_TX          19 /* STM32F373 only */
-#define STM32_IRQ_USB_LP_CAN_RX   20 /* STM32F373 only */
-#define STM32_IRQ_DAC             21
-#define STM32_IRQ_CAN_RX1         21 /* STM32F373 only */
-
-#define STM32_IRQ_COMP            22
-
-#define STM32_IRQ_CAN_SCE         22 /* STM32F373 only */
-#define STM32_IRQ_EXTI9_5         23
-#define STM32_IRQ_LCD             24 /* STM32L15X only */
-#define STM32_IRQ_TIM15           24 /* STM32F373 only */
+#define STM32_IRQ_WWDG 0
+#define STM32_IRQ_PVD 1
+#define STM32_IRQ_TAMPER_STAMP 2
+#define STM32_IRQ_RTC_WAKEUP 3
+#define STM32_IRQ_FLASH 4
+#define STM32_IRQ_RCC 5
+#define STM32_IRQ_EXTI0 6
+#define STM32_IRQ_EXTI1 7
+#define STM32_IRQ_EXTI2 8
+#define STM32_IRQ_EXTI3 9
+#define STM32_IRQ_EXTI4 10
+#define STM32_IRQ_DMA_CHANNEL_1 11
+#define STM32_IRQ_DMA_CHANNEL_2 12
+#define STM32_IRQ_DMA_CHANNEL_3 13
+#define STM32_IRQ_DMA_CHANNEL_4 14
+#define STM32_IRQ_DMA_CHANNEL_5 15
+#define STM32_IRQ_DMA_CHANNEL_6 16
+#define STM32_IRQ_DMA_CHANNEL_7 17
+#define STM32_IRQ_USB_HP 19
+#define STM32_IRQ_USB_LP 20
+
+#define STM32_IRQ_ADC1 18 /* STM32L4 only */
+#define STM32_IRQ_CAN_TX 19 /* STM32F373 only */
+#define STM32_IRQ_USB_LP_CAN_RX 20 /* STM32F373 only */
+#define STM32_IRQ_DAC 21
+#define STM32_IRQ_CAN_RX1 21 /* STM32F373 only */
+
+#define STM32_IRQ_COMP 22
+
+#define STM32_IRQ_CAN_SCE 22 /* STM32F373 only */
+#define STM32_IRQ_EXTI9_5 23
+#define STM32_IRQ_LCD 24 /* STM32L15X only */
+#define STM32_IRQ_TIM15 24 /* STM32F373 only */
 #if defined(CHIP_VARIANT_STM32F412)
-#define STM32_IRQ_TIM9            24 /* STM32F412 only */
+#define STM32_IRQ_TIM9 24 /* STM32F412 only */
 #else
-#define STM32_IRQ_TIM9            25 /* STM32L15X only */
+#define STM32_IRQ_TIM9 25 /* STM32L15X only */
 #endif
-#define STM32_IRQ_TIM16           25 /* STM32F373 only */
-#define STM32_IRQ_TIM10           26 /* STM32L15X only */
-#define STM32_IRQ_TIM17           26 /* STM32F373 only */
-#define STM32_IRQ_TIM11           27 /* STM32L15X only */
-#define STM32_IRQ_TIM18_DAC2      27 /* STM32F373 only */
-#define STM32_IRQ_TIM2            28
-#define STM32_IRQ_TIM3            29
-#define STM32_IRQ_TIM4            30
-#define STM32_IRQ_I2C1_EV         31
-#define STM32_IRQ_I2C1_ER         32
-#define STM32_IRQ_I2C2_EV         33
-#define STM32_IRQ_I2C2_ER         34
-#define STM32_IRQ_SPI1            35
-#define STM32_IRQ_SPI2            36
-#define STM32_IRQ_USART1          37
-#define STM32_IRQ_USART2          38
-#define STM32_IRQ_USART3          39
-#define STM32_IRQ_EXTI15_10       40
-#define STM32_IRQ_RTC_ALARM       41
-#define STM32_IRQ_USB_FS_WAKEUP   42 /* STM32L15X */
-#define STM32_IRQ_CEC             42 /* STM32F373 only */
-#define STM32_IRQ_TIM6_BASIC      43 /* STM32L15X only */
-#define STM32_IRQ_TIM12           43 /* STM32F373 only */
-#define STM32_IRQ_TIM7_BASIC      44 /* STM32L15X only */
-#define STM32_IRQ_TIM13           44 /* STM32F373 only */
-#define STM32_IRQ_TIM14           45 /* STM32F373 only */
-#define STM32_IRQ_TIM5            50 /* STM32F373 */
-#define STM32_IRQ_SPI3            51 /* STM32F373 */
-#define STM32_IRQ_USART4          52 /* STM32F446 only */
-#define STM32_IRQ_USART5          53 /* STM32F446 only */
-#define STM32_IRQ_TIM6_DAC        54 /* STM32F373 */
-#define STM32_IRQ_TIM7            55 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL1   56 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL2   57 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL3   58 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL4   59 /* STM32F373 only */
+#define STM32_IRQ_TIM16 25 /* STM32F373 only */
+#define STM32_IRQ_TIM10 26 /* STM32L15X only */
+#define STM32_IRQ_TIM17 26 /* STM32F373 only */
+#define STM32_IRQ_TIM11 27 /* STM32L15X only */
+#define STM32_IRQ_TIM18_DAC2 27 /* STM32F373 only */
+#define STM32_IRQ_TIM2 28
+#define STM32_IRQ_TIM3 29
+#define STM32_IRQ_TIM4 30
+#define STM32_IRQ_I2C1_EV 31
+#define STM32_IRQ_I2C1_ER 32
+#define STM32_IRQ_I2C2_EV 33
+#define STM32_IRQ_I2C2_ER 34
+#define STM32_IRQ_SPI1 35
+#define STM32_IRQ_SPI2 36
+#define STM32_IRQ_USART1 37
+#define STM32_IRQ_USART2 38
+#define STM32_IRQ_USART3 39
+#define STM32_IRQ_EXTI15_10 40
+#define STM32_IRQ_RTC_ALARM 41
+#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X */
+#define STM32_IRQ_CEC 42 /* STM32F373 only */
+#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */
+#define STM32_IRQ_TIM12 43 /* STM32F373 only */
+#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */
+#define STM32_IRQ_TIM13 44 /* STM32F373 only */
+#define STM32_IRQ_TIM14 45 /* STM32F373 only */
+#define STM32_IRQ_TIM5 50 /* STM32F373 */
+#define STM32_IRQ_SPI3 51 /* STM32F373 */
+#define STM32_IRQ_USART4 52 /* STM32F446 only */
+#define STM32_IRQ_USART5 53 /* STM32F446 only */
+#define STM32_IRQ_TIM6_DAC 54 /* STM32F373 */
+#define STM32_IRQ_TIM7 55 /* STM32F373 */
+#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F373 */
+#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F373 */
+#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F373 */
+#define STM32_IRQ_DMA2_CHANNEL4 59 /* STM32F373 only */
 /* if MISC_REMAP bits are set */
-#define STM32_IRQ_DMA2_CHANNEL5   60 /* STM32F373 */
-#define STM32_IRQ_SDADC1          61 /* STM32F373 only */
-#define STM32_IRQ_SDADC2          62 /* STM32F373 only */
-#define STM32_IRQ_SDADC3          63 /* STM32F373 only */
-#define STM32_IRQ_DMA2_CHANNEL6   68 /* STM32L4 only */
-#define STM32_IRQ_DMA2_CHANNEL7   69 /* STM32L4 only */
-#define STM32_IRQ_LPUART          70 /* STM32L4 only */
-#define STM32_IRQ_USART9          70 /* STM32L4 only */
-#define STM32_IRQ_USART6          71 /* STM32F446 only */
-#define STM32_IRQ_I2C3_EV         72 /* STM32F446 only */
-#define STM32_IRQ_I2C3_ER         73 /* STM32F446 only */
-#define STM32_IRQ_USB_WAKEUP      76 /* STM32F373 only */
-#define STM32_IRQ_TIM19           78 /* STM32F373 only */
-#define STM32_IRQ_AES             79 /* STM32L4 only */
-#define STM32_IRQ_RNG             80 /* STM32L4 only */
-#define STM32_IRQ_FPU             81 /* STM32F373 only */
-
+#define STM32_IRQ_DMA2_CHANNEL5 60 /* STM32F373 */
+#define STM32_IRQ_SDADC1 61 /* STM32F373 only */
+#define STM32_IRQ_SDADC2 62 /* STM32F373 only */
+#define STM32_IRQ_SDADC3 63 /* STM32F373 only */
+#define STM32_IRQ_DMA2_CHANNEL6 68 /* STM32L4 only */
+#define STM32_IRQ_DMA2_CHANNEL7 69 /* STM32L4 only */
+#define STM32_IRQ_LPUART 70 /* STM32L4 only */
+#define STM32_IRQ_USART9 70 /* STM32L4 only */
+#define STM32_IRQ_USART6 71 /* STM32F446 only */
+#define STM32_IRQ_I2C3_EV 72 /* STM32F446 only */
+#define STM32_IRQ_I2C3_ER 73 /* STM32F446 only */
+#define STM32_IRQ_USB_WAKEUP 76 /* STM32F373 only */
+#define STM32_IRQ_TIM19 78 /* STM32F373 only */
+#define STM32_IRQ_AES 79 /* STM32L4 only */
+#define STM32_IRQ_RNG 80 /* STM32L4 only */
+#define STM32_IRQ_FPU 81 /* STM32F373 only */
 
 /* To simplify code generation, define DMA channel 9..10 */
-#define STM32_IRQ_DMA_CHANNEL_9    STM32_IRQ_DMA2_CHANNEL1
-#define STM32_IRQ_DMA_CHANNEL_10   STM32_IRQ_DMA2_CHANNEL2
-#define STM32_IRQ_DMA_CHANNEL_13   STM32_IRQ_DMA2_CHANNEL6
-#define STM32_IRQ_DMA_CHANNEL_14   STM32_IRQ_DMA2_CHANNEL7
+#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1
+#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2
+#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6
+#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7
 
 /* aliases for easier code sharing */
 #define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV
@@ -134,279 +133,276 @@
  * STM32F4 introduces a concept of DMA stream to allow
  * fine allocation of a stream to a channel.
  */
-#define STM32_IRQ_DMA1_STREAM0    11
-#define STM32_IRQ_DMA1_STREAM1    12
-#define STM32_IRQ_DMA1_STREAM2    13
-#define STM32_IRQ_DMA1_STREAM3    14
-#define STM32_IRQ_DMA1_STREAM4    15
-#define STM32_IRQ_DMA1_STREAM5    16
-#define STM32_IRQ_DMA1_STREAM6    17
-#define STM32_IRQ_DMA1_STREAM7    47
-#define STM32_IRQ_DMA2_STREAM0    56
-#define STM32_IRQ_DMA2_STREAM1    57
-#define STM32_IRQ_DMA2_STREAM2    58
-#define STM32_IRQ_DMA2_STREAM3    59
-#define STM32_IRQ_DMA2_STREAM4    60
-#define STM32_IRQ_DMA2_STREAM5    68
-#define STM32_IRQ_DMA2_STREAM6    69
-#define STM32_IRQ_DMA2_STREAM7    70
-
-#define STM32_IRQ_OTG_HS_WKUP     76
-#define STM32_IRQ_OTG_HS_EP1_IN   75
-#define STM32_IRQ_OTG_HS_EP1_OUT  74
-#define STM32_IRQ_OTG_HS          77
-#define STM32_IRQ_OTG_FS          67
-#define STM32_IRQ_OTG_FS_WKUP     42
+#define STM32_IRQ_DMA1_STREAM0 11
+#define STM32_IRQ_DMA1_STREAM1 12
+#define STM32_IRQ_DMA1_STREAM2 13
+#define STM32_IRQ_DMA1_STREAM3 14
+#define STM32_IRQ_DMA1_STREAM4 15
+#define STM32_IRQ_DMA1_STREAM5 16
+#define STM32_IRQ_DMA1_STREAM6 17
+#define STM32_IRQ_DMA1_STREAM7 47
+#define STM32_IRQ_DMA2_STREAM0 56
+#define STM32_IRQ_DMA2_STREAM1 57
+#define STM32_IRQ_DMA2_STREAM2 58
+#define STM32_IRQ_DMA2_STREAM3 59
+#define STM32_IRQ_DMA2_STREAM4 60
+#define STM32_IRQ_DMA2_STREAM5 68
+#define STM32_IRQ_DMA2_STREAM6 69
+#define STM32_IRQ_DMA2_STREAM7 70
+
+#define STM32_IRQ_OTG_HS_WKUP 76
+#define STM32_IRQ_OTG_HS_EP1_IN 75
+#define STM32_IRQ_OTG_HS_EP1_OUT 74
+#define STM32_IRQ_OTG_HS 77
+#define STM32_IRQ_OTG_FS 67
+#define STM32_IRQ_OTG_FS_WKUP 42
 
 /* Peripheral base addresses */
-#define STM32_ADC1_BASE             0x40012000
-#define STM32_ADC_BASE              0x40012300
-
-#define STM32_CEC_BASE              0x40007800 /* STM32F373 */
-#define STM32_CRC_BASE              0x40023000
-#define STM32_CRS_BASE              0x40006c00 /* STM32F0XX */
-#define STM32_DAC_BASE              0x40007400
-
-
-#define STM32_DBGMCU_BASE           0xE0042000
-
-#define STM32_DMA1_BASE             0x40026000
-#define STM32_DMA2_BASE             0x40026400
-
-#define STM32_EXTI_BASE             0x40013C00
-
-#define STM32_FLASH_REGS_BASE       0x40023c00
-
-#define STM32_GPIOA_BASE            0x40020000
-#define STM32_GPIOB_BASE            0x40020400
-#define STM32_GPIOC_BASE            0x40020800
-#define STM32_GPIOD_BASE            0x40020C00
-#define STM32_GPIOE_BASE            0x40021000
-#define STM32_GPIOF_BASE            0x40021400 /* see RM0402/0390 table 1 */
-#define STM32_GPIOG_BASE            0x40021800
-#define STM32_GPIOH_BASE            0x40021C00
-
-#define STM32_I2C1_BASE             0x40005400
-#define STM32_I2C2_BASE             0x40005800
-#define STM32_I2C3_BASE             0x40005C00
-#define STM32_I2C4_BASE             0x40006000
-
-#define STM32_IWDG_BASE             0x40003000
-#define STM32_LCD_BASE              0x40002400
-
-#define STM32_OPTB_BASE             0x1FFFC000
-#define STM32_OTP_BASE              0x1FFF7800
-
-#define STM32_PMSE_BASE             0x40013400
-#define STM32_PWR_BASE              0x40007000
-
-#define STM32_RCC_BASE              0x40023800
-
-#define STM32_RI_BASE               0x40007C00 /* STM32L1xx only */
-#define STM32_RNG_BASE              0x50060800 /* STM32L4 */
-#define STM32_RTC_BASE              0x40002800
-
-#define STM32_SPI1_BASE             0x40013000
-#define STM32_SPI2_BASE             0x40003800
-#define STM32_SPI3_BASE             0x40003c00 /* STM32F373, STM32L4, STM32F7 */
-
-#define STM32_SYSCFG_BASE           0x40013800
-
-#define STM32_TIM1_BASE             0x40012c00 /* STM32F373 */
-#define STM32_TIM2_BASE             0x40000000
-#define STM32_TIM3_BASE             0x40000400
-#define STM32_TIM4_BASE             0x40000800
-#define STM32_TIM5_BASE             0x40000c00 /* STM32F373 */
-#define STM32_TIM6_BASE             0x40001000
-#define STM32_TIM7_BASE             0x40001400
-#define STM32_TIM9_BASE             0x40014000 /* STM32F41x only */
-#define STM32_TIM10_BASE            0x40014400 /* STM32F41x only */
-#define STM32_TIM11_BASE            0x40014800 /* STM32F41x only */
-#define STM32_TIM12_BASE            0x40001800 /* STM32F373 */
-#define STM32_TIM13_BASE            0x40001c00 /* STM32F373 */
-#define STM32_TIM14_BASE            0x40002000 /* STM32F373 */
-#define STM32_TIM15_BASE            0x40014000
-#define STM32_TIM16_BASE            0x40014400
-#define STM32_TIM17_BASE            0x40014800
-#define STM32_TIM18_BASE            0x40009c00 /* STM32F373 only */
-#define STM32_TIM19_BASE            0x40015c00 /* STM32F373 only */
-
-#define STM32_UNIQUE_ID_BASE        0x1fff7a10
-
-#define STM32_USART1_BASE           0x40011000
-#define STM32_USART2_BASE           0x40004400
-#define STM32_USART3_BASE           0x40004800
-#define STM32_USART4_BASE           0x40004c00
-#define STM32_USART5_BASE           0x40005000
-#define STM32_USART6_BASE           0x40011400
-
-#define STM32_USB_CAN_SRAM_BASE     0x40006000
-#define STM32_USB_FS_BASE           0x40005C00
-
-#define STM32_WWDG_BASE             0x40002C00
-
+#define STM32_ADC1_BASE 0x40012000
+#define STM32_ADC_BASE 0x40012300
+
+#define STM32_CEC_BASE 0x40007800 /* STM32F373 */
+#define STM32_CRC_BASE 0x40023000
+#define STM32_CRS_BASE 0x40006c00 /* STM32F0XX */
+#define STM32_DAC_BASE 0x40007400
+
+#define STM32_DBGMCU_BASE 0xE0042000
+
+#define STM32_DMA1_BASE 0x40026000
+#define STM32_DMA2_BASE 0x40026400
+
+#define STM32_EXTI_BASE 0x40013C00
+
+#define STM32_FLASH_REGS_BASE 0x40023c00
+
+#define STM32_GPIOA_BASE 0x40020000
+#define STM32_GPIOB_BASE 0x40020400
+#define STM32_GPIOC_BASE 0x40020800
+#define STM32_GPIOD_BASE 0x40020C00
+#define STM32_GPIOE_BASE 0x40021000
+#define STM32_GPIOF_BASE 0x40021400 /* see RM0402/0390 table 1 */
+#define STM32_GPIOG_BASE 0x40021800
+#define STM32_GPIOH_BASE 0x40021C00
+
+#define STM32_I2C1_BASE 0x40005400
+#define STM32_I2C2_BASE 0x40005800
+#define STM32_I2C3_BASE 0x40005C00
+#define STM32_I2C4_BASE 0x40006000
+
+#define STM32_IWDG_BASE 0x40003000
+#define STM32_LCD_BASE 0x40002400
+
+#define STM32_OPTB_BASE 0x1FFFC000
+#define STM32_OTP_BASE 0x1FFF7800
+
+#define STM32_PMSE_BASE 0x40013400
+#define STM32_PWR_BASE 0x40007000
+
+#define STM32_RCC_BASE 0x40023800
+
+#define STM32_RI_BASE 0x40007C00 /* STM32L1xx only */
+#define STM32_RNG_BASE 0x50060800 /* STM32L4 */
+#define STM32_RTC_BASE 0x40002800
+
+#define STM32_SPI1_BASE 0x40013000
+#define STM32_SPI2_BASE 0x40003800
+#define STM32_SPI3_BASE 0x40003c00 /* STM32F373, STM32L4, STM32F7 */
+
+#define STM32_SYSCFG_BASE 0x40013800
+
+#define STM32_TIM1_BASE 0x40012c00 /* STM32F373 */
+#define STM32_TIM2_BASE 0x40000000
+#define STM32_TIM3_BASE 0x40000400
+#define STM32_TIM4_BASE 0x40000800
+#define STM32_TIM5_BASE 0x40000c00 /* STM32F373 */
+#define STM32_TIM6_BASE 0x40001000
+#define STM32_TIM7_BASE 0x40001400
+#define STM32_TIM9_BASE 0x40014000 /* STM32F41x only */
+#define STM32_TIM10_BASE 0x40014400 /* STM32F41x only */
+#define STM32_TIM11_BASE 0x40014800 /* STM32F41x only */
+#define STM32_TIM12_BASE 0x40001800 /* STM32F373 */
+#define STM32_TIM13_BASE 0x40001c00 /* STM32F373 */
+#define STM32_TIM14_BASE 0x40002000 /* STM32F373 */
+#define STM32_TIM15_BASE 0x40014000
+#define STM32_TIM16_BASE 0x40014400
+#define STM32_TIM17_BASE 0x40014800
+#define STM32_TIM18_BASE 0x40009c00 /* STM32F373 only */
+#define STM32_TIM19_BASE 0x40015c00 /* STM32F373 only */
+
+#define STM32_UNIQUE_ID_BASE 0x1fff7a10
+
+#define STM32_USART1_BASE 0x40011000
+#define STM32_USART2_BASE 0x40004400
+#define STM32_USART3_BASE 0x40004800
+#define STM32_USART4_BASE 0x40004c00
+#define STM32_USART5_BASE 0x40005000
+#define STM32_USART6_BASE 0x40011400
+
+#define STM32_USB_CAN_SRAM_BASE 0x40006000
+#define STM32_USB_FS_BASE 0x40005C00
+
+#define STM32_WWDG_BASE 0x40002C00
 
 #ifndef __ASSEMBLER__
 
 /* Register definitions */
 
 /* --- USART --- */
-#define STM32_USART_SR(base)       STM32_USART_REG(base, 0x00)
-#define STM32_USART_SR_ORE		BIT(3)
-#define STM32_USART_SR_RXNE		BIT(5)
-#define STM32_USART_SR_TC		BIT(6)
-#define STM32_USART_SR_TXE		BIT(7)
-#define STM32_USART_DR(base)       STM32_USART_REG(base, 0x04)
-#define STM32_USART_BRR(base)      STM32_USART_REG(base, 0x08)
-#define STM32_USART_CR1(base)      STM32_USART_REG(base, 0x0C)
-#define STM32_USART_CR1_RE		BIT(2)
-#define STM32_USART_CR1_TE		BIT(3)
-#define STM32_USART_CR1_RXNEIE		BIT(5)
-#define STM32_USART_CR1_TCIE		BIT(6)
-#define STM32_USART_CR1_TXEIE		BIT(7)
-#define STM32_USART_CR1_PS		BIT(9)
-#define STM32_USART_CR1_PCE		BIT(10)
-#define STM32_USART_CR1_M		BIT(12)
-#define STM32_USART_CR1_UE		BIT(13)
-#define STM32_USART_CR1_OVER8		BIT(15) /* STM32L only */
-#define STM32_USART_CR2(base)      STM32_USART_REG(base, 0x10)
-#define STM32_USART_CR3(base)      STM32_USART_REG(base, 0x14)
-#define STM32_USART_CR3_EIE		BIT(0)
-#define STM32_USART_CR3_DMAR		BIT(6)
-#define STM32_USART_CR3_DMAT		BIT(7)
-#define STM32_USART_CR3_ONEBIT		BIT(11) /* STM32L only */
-#define STM32_USART_GTPR(base)     STM32_USART_REG(base, 0x18)
+#define STM32_USART_SR(base) STM32_USART_REG(base, 0x00)
+#define STM32_USART_SR_ORE BIT(3)
+#define STM32_USART_SR_RXNE BIT(5)
+#define STM32_USART_SR_TC BIT(6)
+#define STM32_USART_SR_TXE BIT(7)
+#define STM32_USART_DR(base) STM32_USART_REG(base, 0x04)
+#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x08)
+#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x0C)
+#define STM32_USART_CR1_RE BIT(2)
+#define STM32_USART_CR1_TE BIT(3)
+#define STM32_USART_CR1_RXNEIE BIT(5)
+#define STM32_USART_CR1_TCIE BIT(6)
+#define STM32_USART_CR1_TXEIE BIT(7)
+#define STM32_USART_CR1_PS BIT(9)
+#define STM32_USART_CR1_PCE BIT(10)
+#define STM32_USART_CR1_M BIT(12)
+#define STM32_USART_CR1_UE BIT(13)
+#define STM32_USART_CR1_OVER8 BIT(15) /* STM32L only */
+#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x10)
+#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x14)
+#define STM32_USART_CR3_EIE BIT(0)
+#define STM32_USART_CR3_DMAR BIT(6)
+#define STM32_USART_CR3_DMAT BIT(7)
+#define STM32_USART_CR3_ONEBIT BIT(11) /* STM32L only */
+#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x18)
 /* register aliases */
-#define STM32_USART_TDR(base)      STM32_USART_DR(base)
-#define STM32_USART_RDR(base)      STM32_USART_DR(base)
+#define STM32_USART_TDR(base) STM32_USART_DR(base)
+#define STM32_USART_RDR(base) STM32_USART_DR(base)
 
 /* --- GPIO --- */
-#define STM32_GPIO_MODER(b)     REG32((b) + 0x00)
-#define STM32_GPIO_OTYPER(b)    REG16((b) + 0x04)
-#define STM32_GPIO_OSPEEDR(b)   REG32((b) + 0x08)
-#define STM32_GPIO_PUPDR(b)     REG32((b) + 0x0C)
-#define STM32_GPIO_IDR(b)       REG16((b) + 0x10)
-#define STM32_GPIO_ODR(b)       REG16((b) + 0x14)
-#define STM32_GPIO_BSRR(b)      REG32((b) + 0x18)
-#define STM32_GPIO_LCKR(b)      REG32((b) + 0x1C)
-#define STM32_GPIO_AFRL(b)      REG32((b) + 0x20)
-#define STM32_GPIO_AFRH(b)      REG32((b) + 0x24)
-
-#define GPIO_ALT_SYS                 0x0
-#define GPIO_ALT_TIM2                0x1
-#define GPIO_ALT_TIM3_4              0x2
-#define GPIO_ALT_TIM9_11             0x3
-#define GPIO_ALT_I2C                 0x4
-#define GPIO_ALT_SPI                 0x5
-#define GPIO_ALT_SPI3                0x6
-#define GPIO_ALT_USART               0x7
-#define GPIO_ALT_I2C_23              0x9
-#define GPIO_ALT_USB                 0xA
-#define GPIO_ALT_LCD                 0xB
-#define GPIO_ALT_RI                  0xE
-#define GPIO_ALT_EVENTOUT            0xF
+#define STM32_GPIO_MODER(b) REG32((b) + 0x00)
+#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04)
+#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08)
+#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C)
+#define STM32_GPIO_IDR(b) REG16((b) + 0x10)
+#define STM32_GPIO_ODR(b) REG16((b) + 0x14)
+#define STM32_GPIO_BSRR(b) REG32((b) + 0x18)
+#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C)
+#define STM32_GPIO_AFRL(b) REG32((b) + 0x20)
+#define STM32_GPIO_AFRH(b) REG32((b) + 0x24)
+
+#define GPIO_ALT_SYS 0x0
+#define GPIO_ALT_TIM2 0x1
+#define GPIO_ALT_TIM3_4 0x2
+#define GPIO_ALT_TIM9_11 0x3
+#define GPIO_ALT_I2C 0x4
+#define GPIO_ALT_SPI 0x5
+#define GPIO_ALT_SPI3 0x6
+#define GPIO_ALT_USART 0x7
+#define GPIO_ALT_I2C_23 0x9
+#define GPIO_ALT_USB 0xA
+#define GPIO_ALT_LCD 0xB
+#define GPIO_ALT_RI 0xE
+#define GPIO_ALT_EVENTOUT 0xF
 
 /* --- I2C --- */
-#define STM32_I2C_CR1(n)            REG16(stm32_i2c_reg(n, 0x00))
-#define STM32_I2C_CR1_PE	BIT(0)
-#define STM32_I2C_CR1_START	BIT(8)
-#define STM32_I2C_CR1_STOP	BIT(9)
-#define STM32_I2C_CR1_ACK	BIT(10)
-#define STM32_I2C_CR1_POS	BIT(11)
-#define STM32_I2C_CR1_SWRST	BIT(15)
-#define STM32_I2C_CR2(n)            REG16(stm32_i2c_reg(n, 0x04))
-#define STM32_I2C_CR2_ITERREN	BIT(8)
-#define STM32_I2C_CR2_ITEVTEN	BIT(9)
-#define STM32_I2C_CR2_ITBUFEN	BIT(10)
-#define STM32_I2C_CR2_DMAEN	BIT(11)
-#define STM32_I2C_CR2_LAST	BIT(12)
-#define STM32_I2C_OAR1(n)           REG16(stm32_i2c_reg(n, 0x08))
-#define STM32_I2C_OAR1_B14	BIT(14)
-#define STM32_I2C_OAR2(n)           REG16(stm32_i2c_reg(n, 0x0C))
-#define STM32_I2C_OAR2_ENDUAL	BIT(0)
-#define STM32_I2C_DR(n)             REG16(stm32_i2c_reg(n, 0x10))
-#define STM32_I2C_SR1(n)            REG16(stm32_i2c_reg(n, 0x14))
-#define STM32_I2C_SR1_SB	BIT(0)
-#define STM32_I2C_SR1_ADDR	BIT(1)
-#define STM32_I2C_SR1_BTF	BIT(2)
-#define STM32_I2C_SR1_STOPF	BIT(4)
-#define STM32_I2C_SR1_RXNE	BIT(6)
-#define STM32_I2C_SR1_TXE	BIT(7)
-#define STM32_I2C_SR1_BERR	BIT(8)
-#define STM32_I2C_SR1_ARLO	BIT(9)
-#define STM32_I2C_SR1_AF	BIT(10)
-
-#define STM32_I2C_SR2(n)            REG16(stm32_i2c_reg(n, 0x18))
-#define STM32_I2C_SR2_BUSY	BIT(1)
-#define STM32_I2C_SR2_TRA	BIT(2)
-#define STM32_I2C_SR2_DUALF	BIT(7)
-
-#define STM32_I2C_CCR(n)            REG16(stm32_i2c_reg(n, 0x1C))
-#define STM32_I2C_CCR_DUTY	BIT(14)
-#define STM32_I2C_CCR_FM	BIT(15)
-#define STM32_I2C_TRISE(n)          REG16(stm32_i2c_reg(n, 0x20))
-
-#define STM32_FMPI2C_CR1(n)        REG32(stm32_i2c_reg(n, 0x00))
-#define  FMPI2C_CR1_PE             BIT(0)
-#define  FMPI2C_CR1_TXDMAEN        BIT(14)
-#define  FMPI2C_CR1_RXDMAEN        BIT(15)
-#define STM32_FMPI2C_CR2(n)        REG32(stm32_i2c_reg(n, 0x04))
-#define  FMPI2C_CR2_RD_WRN         BIT(10)
-#define  FMPI2C_READ               1
-#define  FMPI2C_WRITE              0
-#define  FMPI2C_CR2_START          BIT(13)
-#define  FMPI2C_CR2_STOP           BIT(14)
-#define  FMPI2C_CR2_NACK           BIT(15)
-#define  FMPI2C_CR2_RELOAD         BIT(24)
-#define  FMPI2C_CR2_AUTOEND        BIT(25)
-#define  FMPI2C_CR2_SADD(addr)     ((addr) & 0x3ff)
-#define  FMPI2C_CR2_SADD_MASK      FMPI2C_CR2_SADD(0x3ff)
-#define  FMPI2C_CR2_SIZE(size)     (((size) & 0xff) << 16)
-#define  FMPI2C_CR2_SIZE_MASK      FMPI2C_CR2_SIZE(0xf)
-#define STM32_FMPI2C_OAR1(n)       REG32(stm32_i2c_reg(n, 0x08))
-#define STM32_FMPI2C_OAR2(n)       REG32(stm32_i2c_reg(n, 0x0C))
-#define STM32_FMPI2C_TIMINGR(n)    REG32(stm32_i2c_reg(n, 0x10))
-#define  TIMINGR_THE_RIGHT_VALUE   0xC0000E12
-#define  FMPI2C_TIMINGR_PRESC(val) (((val) & 0xf) << 28)
-#define  FMPI2C_TIMINGR_SCLDEL(val) (((val) & 0xf) << 20)
-#define  FMPI2C_TIMINGR_SDADEL(val) (((val) & 0xf) << 16)
-#define  FMPI2C_TIMINGR_SCLH(val)  (((val) & 0xff) << 8)
-#define  FMPI2C_TIMINGR_SCLL(val)  (((val) & 0xff) << 0)
-#define STM32_FMPI2C_TIMEOUTR(n)   REG32(stm32_i2c_reg(n, 0x14))
-
-#define STM32_FMPI2C_ISR(n)        REG32(stm32_i2c_reg(n, 0x18))
-#define  FMPI2C_ISR_TXE            BIT(0)
-#define  FMPI2C_ISR_TXIS           BIT(1)
-#define  FMPI2C_ISR_RXNE           BIT(2)
-#define  FMPI2C_ISR_ADDR           BIT(3)
-#define  FMPI2C_ISR_NACKF          BIT(4)
-#define  FMPI2C_ISR_STOPF          BIT(5)
-#define  FMPI2C_ISR_BERR           BIT(8)
-#define  FMPI2C_ISR_ARLO           BIT(9)
-#define  FMPI2C_ISR_BUSY           BIT(15)
-#define STM32_FMPI2C_ICR(n)        REG32(stm32_i2c_reg(n, 0x1C))
-
-#define STM32_FMPI2C_PECR(n)       REG32(stm32_i2c_reg(n, 0x20))
-#define STM32_FMPI2C_RXDR(n)       REG32(stm32_i2c_reg(n, 0x24))
-#define STM32_FMPI2C_TXDR(n)       REG32(stm32_i2c_reg(n, 0x28))
+#define STM32_I2C_CR1(n) REG16(stm32_i2c_reg(n, 0x00))
+#define STM32_I2C_CR1_PE BIT(0)
+#define STM32_I2C_CR1_START BIT(8)
+#define STM32_I2C_CR1_STOP BIT(9)
+#define STM32_I2C_CR1_ACK BIT(10)
+#define STM32_I2C_CR1_POS BIT(11)
+#define STM32_I2C_CR1_SWRST BIT(15)
+#define STM32_I2C_CR2(n) REG16(stm32_i2c_reg(n, 0x04))
+#define STM32_I2C_CR2_ITERREN BIT(8)
+#define STM32_I2C_CR2_ITEVTEN BIT(9)
+#define STM32_I2C_CR2_ITBUFEN BIT(10)
+#define STM32_I2C_CR2_DMAEN BIT(11)
+#define STM32_I2C_CR2_LAST BIT(12)
+#define STM32_I2C_OAR1(n) REG16(stm32_i2c_reg(n, 0x08))
+#define STM32_I2C_OAR1_B14 BIT(14)
+#define STM32_I2C_OAR2(n) REG16(stm32_i2c_reg(n, 0x0C))
+#define STM32_I2C_OAR2_ENDUAL BIT(0)
+#define STM32_I2C_DR(n) REG16(stm32_i2c_reg(n, 0x10))
+#define STM32_I2C_SR1(n) REG16(stm32_i2c_reg(n, 0x14))
+#define STM32_I2C_SR1_SB BIT(0)
+#define STM32_I2C_SR1_ADDR BIT(1)
+#define STM32_I2C_SR1_BTF BIT(2)
+#define STM32_I2C_SR1_STOPF BIT(4)
+#define STM32_I2C_SR1_RXNE BIT(6)
+#define STM32_I2C_SR1_TXE BIT(7)
+#define STM32_I2C_SR1_BERR BIT(8)
+#define STM32_I2C_SR1_ARLO BIT(9)
+#define STM32_I2C_SR1_AF BIT(10)
+
+#define STM32_I2C_SR2(n) REG16(stm32_i2c_reg(n, 0x18))
+#define STM32_I2C_SR2_BUSY BIT(1)
+#define STM32_I2C_SR2_TRA BIT(2)
+#define STM32_I2C_SR2_DUALF BIT(7)
+
+#define STM32_I2C_CCR(n) REG16(stm32_i2c_reg(n, 0x1C))
+#define STM32_I2C_CCR_DUTY BIT(14)
+#define STM32_I2C_CCR_FM BIT(15)
+#define STM32_I2C_TRISE(n) REG16(stm32_i2c_reg(n, 0x20))
+
+#define STM32_FMPI2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00))
+#define FMPI2C_CR1_PE BIT(0)
+#define FMPI2C_CR1_TXDMAEN BIT(14)
+#define FMPI2C_CR1_RXDMAEN BIT(15)
+#define STM32_FMPI2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04))
+#define FMPI2C_CR2_RD_WRN BIT(10)
+#define FMPI2C_READ 1
+#define FMPI2C_WRITE 0
+#define FMPI2C_CR2_START BIT(13)
+#define FMPI2C_CR2_STOP BIT(14)
+#define FMPI2C_CR2_NACK BIT(15)
+#define FMPI2C_CR2_RELOAD BIT(24)
+#define FMPI2C_CR2_AUTOEND BIT(25)
+#define FMPI2C_CR2_SADD(addr) ((addr)&0x3ff)
+#define FMPI2C_CR2_SADD_MASK FMPI2C_CR2_SADD(0x3ff)
+#define FMPI2C_CR2_SIZE(size) (((size)&0xff) << 16)
+#define FMPI2C_CR2_SIZE_MASK FMPI2C_CR2_SIZE(0xf)
+#define STM32_FMPI2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08))
+#define STM32_FMPI2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C))
+#define STM32_FMPI2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10))
+#define TIMINGR_THE_RIGHT_VALUE 0xC0000E12
+#define FMPI2C_TIMINGR_PRESC(val) (((val)&0xf) << 28)
+#define FMPI2C_TIMINGR_SCLDEL(val) (((val)&0xf) << 20)
+#define FMPI2C_TIMINGR_SDADEL(val) (((val)&0xf) << 16)
+#define FMPI2C_TIMINGR_SCLH(val) (((val)&0xff) << 8)
+#define FMPI2C_TIMINGR_SCLL(val) (((val)&0xff) << 0)
+#define STM32_FMPI2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14))
+
+#define STM32_FMPI2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18))
+#define FMPI2C_ISR_TXE BIT(0)
+#define FMPI2C_ISR_TXIS BIT(1)
+#define FMPI2C_ISR_RXNE BIT(2)
+#define FMPI2C_ISR_ADDR BIT(3)
+#define FMPI2C_ISR_NACKF BIT(4)
+#define FMPI2C_ISR_STOPF BIT(5)
+#define FMPI2C_ISR_BERR BIT(8)
+#define FMPI2C_ISR_ARLO BIT(9)
+#define FMPI2C_ISR_BUSY BIT(15)
+#define STM32_FMPI2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C))
+
+#define STM32_FMPI2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20))
+#define STM32_FMPI2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24))
+#define STM32_FMPI2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28))
 
 /* --- Power / Reset / Clocks --- */
-#define STM32_PWR_CSR               REG32(STM32_PWR_BASE + 0x04)
-
+#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04)
 
-#define STM32_RCC_CR                    REG32(STM32_RCC_BASE + 0x00)
-#define STM32_RCC_CR_HSION		BIT(0)
-#define STM32_RCC_CR_HSIRDY		BIT(1)
-#define STM32_RCC_CR_HSEON		BIT(16)
-#define STM32_RCC_CR_HSERDY		BIT(17)
-#define STM32_RCC_CR_PLLON		BIT(24)
-#define STM32_RCC_CR_PLLRDY		BIT(25)
+#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00)
+#define STM32_RCC_CR_HSION BIT(0)
+#define STM32_RCC_CR_HSIRDY BIT(1)
+#define STM32_RCC_CR_HSEON BIT(16)
+#define STM32_RCC_CR_HSERDY BIT(17)
+#define STM32_RCC_CR_PLLON BIT(24)
+#define STM32_RCC_CR_PLLRDY BIT(25)
 
 #if defined(CHIP_VARIANT_STM32F446)
 /* Required or recommended clocks for stm32f446 */
 #define STM32F4_PLL_REQ 2000000
 #define STM32F4_RTC_REQ 1000000
-#define STM32F4_IO_CLOCK  42000000
+#define STM32F4_IO_CLOCK 42000000
 #define STM32F4_USB_REQ 48000000
 #define STM32F4_VCO_CLOCK 336000000
 #define STM32F4_HSI_CLOCK 16000000
@@ -416,15 +412,15 @@
 #define STM32F4_AHB_PRE 0x8
 #define STM32F4_APB1_PRE 0x0
 #define STM32F4_APB2_PRE 0x0
-#define STM32_FLASH_ACR_LATENCY     BIT(0)
+#define STM32_FLASH_ACR_LATENCY BIT(0)
 /* optimized flash latency for < 30Mhz clock (0-WS) e.g. HSI/HSE */
-#define STM32_FLASH_ACR_LATENCY_SLOW      0
+#define STM32_FLASH_ACR_LATENCY_SLOW 0
 
 #elif defined(CHIP_VARIANT_STM32F412)
 /* Required or recommended clocks for stm32f412 */
 #define STM32F4_PLL_REQ 2000000
 #define STM32F4_RTC_REQ 1000000
-#define STM32F4_IO_CLOCK  48000000
+#define STM32F4_IO_CLOCK 48000000
 #define STM32F4_USB_REQ 48000000
 #define STM32F4_VCO_CLOCK 384000000
 #define STM32F4_HSI_CLOCK 16000000
@@ -434,15 +430,15 @@
 #define STM32F4_AHB_PRE 0x0
 #define STM32F4_APB1_PRE 0x4
 #define STM32F4_APB2_PRE 0x4
-#define STM32_FLASH_ACR_LATENCY     (3 << 0)
+#define STM32_FLASH_ACR_LATENCY (3 << 0)
 /* optimized flash latency for < 30Mhz clock (0-WS) e.g. HSI/HSE */
-#define STM32_FLASH_ACR_LATENCY_SLOW      0
+#define STM32_FLASH_ACR_LATENCY_SLOW 0
 
 #elif defined(CHIP_VARIANT_STM32F411)
 /* Required or recommended clocks for stm32f411 */
 #define STM32F4_PLL_REQ 2000000
 #define STM32F4_RTC_REQ 1000000
-#define STM32F4_IO_CLOCK  48000000
+#define STM32F4_IO_CLOCK 48000000
 #define STM32F4_USB_REQ 48000000
 #define STM32F4_VCO_CLOCK 384000000
 #define STM32F4_HSI_CLOCK 16000000
@@ -452,204 +448,205 @@
 #define STM32F4_AHB_PRE 0x8
 #define STM32F4_APB1_PRE 0x0
 #define STM32F4_APB2_PRE 0x0
-#define STM32_FLASH_ACR_LATENCY     BIT(0)
+#define STM32_FLASH_ACR_LATENCY BIT(0)
 /* optimized flash latency for < 30Mhz clock (0-WS) e.g. HSI/HSE */
-#define STM32_FLASH_ACR_LATENCY_SLOW    0
+#define STM32_FLASH_ACR_LATENCY_SLOW 0
 
 #elif defined(CHIP_VARIANT_STM32F76X)
 /* Required or recommended clocks for stm32f767/769 */
 #define STM32F4_PLL_REQ 2000000
 #define STM32F4_RTC_REQ 1000000
 #define STM32F4_IO_CLOCK 45000000
-#define STM32F4_USB_REQ 45000000 /* not compatible with USB, will use PLLSAI */
+#define STM32F4_USB_REQ                                      \
+	45000000 /* not compatible with USB, will use PLLSAI \
+		  */
 #define STM32F4_VCO_CLOCK 360000000
 #define STM32F4_HSI_CLOCK 16000000
 #define STM32F4_LSI_CLOCK 32000
 #define STM32F4_TIMER_CLOCK (STM32F4_IO_CLOCK * 2)
-#define STM32F4_PLLP_DIV 2   /* sys = VCO/2  = 180 Mhz */
-#define STM32F4_AHB_PRE 0x0  /* AHB = sysclk = 180 Mhz */
+#define STM32F4_PLLP_DIV 2 /* sys = VCO/2  = 180 Mhz */
+#define STM32F4_AHB_PRE 0x0 /* AHB = sysclk = 180 Mhz */
 #define STM32F4_APB1_PRE 0x5 /* APB1 = AHB /4 = 45 Mhz */
 #define STM32F4_APB2_PRE 0x5 /* APB2 = AHB /4 = 45 Mhz */
-#define STM32_FLASH_ACR_LATENCY     (5 << 0)
+#define STM32_FLASH_ACR_LATENCY (5 << 0)
 /* optimized flash latency for < 30Mhz clock (0-WS) e.g. HSI/HSE */
-#define STM32_FLASH_ACR_LATENCY_SLOW      0
+#define STM32_FLASH_ACR_LATENCY_SLOW 0
 
 #else
 #error "No valid clocks defined"
 #endif
 
-#define STM32_RCC_PLLCFGR               REG32(STM32_RCC_BASE + 0x04)
+#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x04)
 /* PLL Division factor */
-#define  PLLCFGR_PLLM_OFF		0
-#define  PLLCFGR_PLLM(val)		(((val) & 0x1f) << PLLCFGR_PLLM_OFF)
+#define PLLCFGR_PLLM_OFF 0
+#define PLLCFGR_PLLM(val) (((val)&0x1f) << PLLCFGR_PLLM_OFF)
 /* PLL Multiplication factor */
-#define  PLLCFGR_PLLN_OFF		6
-#define  PLLCFGR_PLLN(val)		(((val) & 0x1ff) << PLLCFGR_PLLN_OFF)
+#define PLLCFGR_PLLN_OFF 6
+#define PLLCFGR_PLLN(val) (((val)&0x1ff) << PLLCFGR_PLLN_OFF)
 /* Main CPU Clock */
-#define  PLLCFGR_PLLP_OFF		16
-#define  PLLCFGR_PLLP(val)		(((val) & 0x3) << PLLCFGR_PLLP_OFF)
+#define PLLCFGR_PLLP_OFF 16
+#define PLLCFGR_PLLP(val) (((val)&0x3) << PLLCFGR_PLLP_OFF)
 
-#define  PLLCFGR_PLLSRC_HSI		(0 << 22)
-#define  PLLCFGR_PLLSRC_HSE		BIT(22)
+#define PLLCFGR_PLLSRC_HSI (0 << 22)
+#define PLLCFGR_PLLSRC_HSE BIT(22)
 /* USB OTG FS: Must equal 48MHz */
-#define  PLLCFGR_PLLQ_OFF		24
-#define  PLLCFGR_PLLQ(val)		(((val) & 0xf) << PLLCFGR_PLLQ_OFF)
+#define PLLCFGR_PLLQ_OFF 24
+#define PLLCFGR_PLLQ(val) (((val)&0xf) << PLLCFGR_PLLQ_OFF)
 /* SYSTEM */
-#define  PLLCFGR_PLLR_OFF		28
-#define  PLLCFGR_PLLR(val)		(((val) & 0x7) << PLLCFGR_PLLR_OFF)
-
-#define STM32_RCC_CFGR                  REG32(STM32_RCC_BASE + 0x08)
-#define STM32_RCC_CFGR_SW_HSI		(0 << 0)
-#define STM32_RCC_CFGR_SW_HSE		(1 << 0)
-#define STM32_RCC_CFGR_SW_PLL		(2 << 0)
-#define STM32_RCC_CFGR_SW_PLL_R		(3 << 0)
-#define STM32_RCC_CFGR_SW_MASK		(3 << 0)
-#define STM32_RCC_CFGR_SWS_HSI		(0 << 2)
-#define STM32_RCC_CFGR_SWS_HSE		(1 << 2)
-#define STM32_RCC_CFGR_SWS_PLL		(2 << 2)
-#define STM32_RCC_CFGR_SWS_PLL_R	(3 << 2)
-#define STM32_RCC_CFGR_SWS_MASK		(3 << 2)
+#define PLLCFGR_PLLR_OFF 28
+#define PLLCFGR_PLLR(val) (((val)&0x7) << PLLCFGR_PLLR_OFF)
+
+#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08)
+#define STM32_RCC_CFGR_SW_HSI (0 << 0)
+#define STM32_RCC_CFGR_SW_HSE (1 << 0)
+#define STM32_RCC_CFGR_SW_PLL (2 << 0)
+#define STM32_RCC_CFGR_SW_PLL_R (3 << 0)
+#define STM32_RCC_CFGR_SW_MASK (3 << 0)
+#define STM32_RCC_CFGR_SWS_HSI (0 << 2)
+#define STM32_RCC_CFGR_SWS_HSE (1 << 2)
+#define STM32_RCC_CFGR_SWS_PLL (2 << 2)
+#define STM32_RCC_CFGR_SWS_PLL_R (3 << 2)
+#define STM32_RCC_CFGR_SWS_MASK (3 << 2)
 /* AHB Prescalar: nonlinear values, look up in RM0390 */
-#define  CFGR_HPRE_OFF			4
-#define  CFGR_HPRE(val)			(((val) & 0xf) << CFGR_HPRE_OFF)
+#define CFGR_HPRE_OFF 4
+#define CFGR_HPRE(val) (((val)&0xf) << CFGR_HPRE_OFF)
 /* APB1 Low Speed Prescalar < 45MHz */
-#define  CFGR_PPRE1_OFF			10
-#define  CFGR_PPRE1(val)		(((val) & 0x7) << CFGR_PPRE1_OFF)
+#define CFGR_PPRE1_OFF 10
+#define CFGR_PPRE1(val) (((val)&0x7) << CFGR_PPRE1_OFF)
 /* APB2 High Speed Prescalar < 90MHz */
-#define  CFGR_PPRE2_OFF			13
-#define  CFGR_PPRE2(val)		(((val) & 0x7) << CFGR_PPRE2_OFF)
+#define CFGR_PPRE2_OFF 13
+#define CFGR_PPRE2(val) (((val)&0x7) << CFGR_PPRE2_OFF)
 /* RTC CLock: Must equal 1MHz */
-#define  CFGR_RTCPRE_OFF		16
-#define  CFGR_RTCPRE(val)		(((val) & 0x1f) << CFGR_RTCPRE_OFF)
-
-#define STM32_RCC_CIR                   REG32(STM32_RCC_BASE + 0x0C)
-#define STM32_RCC_AHB1RSTR              REG32(STM32_RCC_BASE + 0x10)
-#define  RCC_AHB1RSTR_OTGHSRST		BIT(29)
-
-#define STM32_RCC_AHB2RSTR              REG32(STM32_RCC_BASE + 0x14)
-#define STM32_RCC_AHB3RSTR              REG32(STM32_RCC_BASE + 0x18)
-
-#define STM32_RCC_APB1RSTR              REG32(STM32_RCC_BASE + 0x20)
-#define STM32_RCC_APB2RSTR              REG32(STM32_RCC_BASE + 0x24)
-
-#define STM32_RCC_AHB1ENR               REG32(STM32_RCC_BASE + 0x30)
-#define STM32_RCC_AHB1ENR_GPIO_PORTA	BIT(0)
-#define STM32_RCC_AHB1ENR_GPIO_PORTB	BIT(1)
-#define STM32_RCC_AHB1ENR_GPIO_PORTC	BIT(2)
-#define STM32_RCC_AHB1ENR_GPIO_PORTD	BIT(3)
-#define STM32_RCC_AHB1ENR_GPIO_PORTE	BIT(4)
-#define STM32_RCC_AHB1ENR_GPIO_PORTF	BIT(5)
-#define STM32_RCC_AHB1ENR_GPIO_PORTG	BIT(6)
-#define STM32_RCC_AHB1ENR_GPIO_PORTH	BIT(7)
-#define STM32_RCC_AHB1ENR_GPIOMASK	(0xff << 0)
-#define STM32_RCC_AHB1ENR_BKPSRAMEN	BIT(18)
-#define STM32_RCC_AHB1ENR_DMA1EN	BIT(21)
-#define STM32_RCC_AHB1ENR_DMA2EN	BIT(22)
+#define CFGR_RTCPRE_OFF 16
+#define CFGR_RTCPRE(val) (((val)&0x1f) << CFGR_RTCPRE_OFF)
+
+#define STM32_RCC_CIR REG32(STM32_RCC_BASE + 0x0C)
+#define STM32_RCC_AHB1RSTR REG32(STM32_RCC_BASE + 0x10)
+#define RCC_AHB1RSTR_OTGHSRST BIT(29)
+
+#define STM32_RCC_AHB2RSTR REG32(STM32_RCC_BASE + 0x14)
+#define STM32_RCC_AHB3RSTR REG32(STM32_RCC_BASE + 0x18)
+
+#define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x20)
+#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x24)
+
+#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x30)
+#define STM32_RCC_AHB1ENR_GPIO_PORTA BIT(0)
+#define STM32_RCC_AHB1ENR_GPIO_PORTB BIT(1)
+#define STM32_RCC_AHB1ENR_GPIO_PORTC BIT(2)
+#define STM32_RCC_AHB1ENR_GPIO_PORTD BIT(3)
+#define STM32_RCC_AHB1ENR_GPIO_PORTE BIT(4)
+#define STM32_RCC_AHB1ENR_GPIO_PORTF BIT(5)
+#define STM32_RCC_AHB1ENR_GPIO_PORTG BIT(6)
+#define STM32_RCC_AHB1ENR_GPIO_PORTH BIT(7)
+#define STM32_RCC_AHB1ENR_GPIOMASK (0xff << 0)
+#define STM32_RCC_AHB1ENR_BKPSRAMEN BIT(18)
+#define STM32_RCC_AHB1ENR_DMA1EN BIT(21)
+#define STM32_RCC_AHB1ENR_DMA2EN BIT(22)
 
 /* TODO(nsanders): normalize naming.*/
-#define STM32_RCC_HB1_DMA1		BIT(21)
-#define STM32_RCC_HB1_DMA2		BIT(22)
-#define STM32_RCC_AHB1ENR_OTGHSEN	BIT(29)
-#define STM32_RCC_AHB1ENR_OTGHSULPIEN	BIT(30)
-
-#define STM32_RCC_AHB2ENR               REG32(STM32_RCC_BASE + 0x34)
-#define STM32_RCC_AHB2ENR_RNGEN		BIT(6)
-#define STM32_RCC_AHB2ENR_OTGFSEN	BIT(7)
-#define STM32_RCC_AHB3ENR               REG32(STM32_RCC_BASE + 0x38)
-
-#define STM32_RCC_APB1ENR               REG32(STM32_RCC_BASE + 0x40)
-#define STM32_RCC_PWREN                 BIT(28)
-#define STM32_RCC_I2C1EN                BIT(21)
-#define STM32_RCC_I2C2EN                BIT(22)
-#define STM32_RCC_I2C3EN                BIT(23)
-#define STM32_RCC_FMPI2C4EN             BIT(24)
-
-#define STM32_RCC_APB2ENR               REG32(STM32_RCC_BASE + 0x44)
-#define STM32_RCC_APB2ENR_ADC1EN        BIT(8) /* STM32F4 */
-
-#define STM32_RCC_PB2_USART6            BIT(5)
-#define STM32_RCC_SYSCFGEN		BIT(14)
-
-#define STM32_RCC_AHB1LPENR             REG32(STM32_RCC_BASE + 0x50)
-#define STM32_RCC_AHB2LPENR             REG32(STM32_RCC_BASE + 0x54)
-#define STM32_RCC_AHB3LPENR             REG32(STM32_RCC_BASE + 0x58)
-#define STM32_RCC_APB1LPENR             REG32(STM32_RCC_BASE + 0x60)
-#define STM32_RCC_APB2LPENR             REG32(STM32_RCC_BASE + 0x64)
-
-#define STM32_RCC_BDCR                  REG32(STM32_RCC_BASE + 0x70)
-#define STM32_RCC_CSR                   REG32(STM32_RCC_BASE + 0x74)
-#define STM32_RCC_CSR_LSION		BIT(0)
-#define STM32_RCC_CSR_LSIRDY		BIT(1)
-
-#define STM32_RCC_PB2_TIM1		BIT(0)
-#define STM32_RCC_PB2_TIM8		BIT(1)
-#define STM32_RCC_PB2_TIM9		BIT(16)
-#define STM32_RCC_PB2_TIM10		BIT(17)
-#define STM32_RCC_PB2_TIM11		BIT(18)
-
-#define STM32_RCC_DCKCFGR2              REG32(STM32_RCC_BASE + 0x94)
-#define  DCKCFGR2_FMPI2C1SEL(val)       (((val) & 0x3) << 22)
-#define  DCKCFGR2_FMPI2C1SEL_MASK       (0x3 << 22)
-#define  FMPI2C1SEL_APB                 0x0
-
-#define STM32_SYSCFG_MEMRMP             REG32(STM32_SYSCFG_BASE + 0x00)
-#define STM32_SYSCFG_PMC                REG32(STM32_SYSCFG_BASE + 0x04)
-#define STM32_SYSCFG_EXTICR(n)          REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
-#define STM32_SYSCFG_CMPCR              REG32(STM32_SYSCFG_BASE + 0x20)
-#define STM32_SYSCFG_CFGR               REG32(STM32_SYSCFG_BASE + 0x2C)
-
+#define STM32_RCC_HB1_DMA1 BIT(21)
+#define STM32_RCC_HB1_DMA2 BIT(22)
+#define STM32_RCC_AHB1ENR_OTGHSEN BIT(29)
+#define STM32_RCC_AHB1ENR_OTGHSULPIEN BIT(30)
+
+#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x34)
+#define STM32_RCC_AHB2ENR_RNGEN BIT(6)
+#define STM32_RCC_AHB2ENR_OTGFSEN BIT(7)
+#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x38)
+
+#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x40)
+#define STM32_RCC_PWREN BIT(28)
+#define STM32_RCC_I2C1EN BIT(21)
+#define STM32_RCC_I2C2EN BIT(22)
+#define STM32_RCC_I2C3EN BIT(23)
+#define STM32_RCC_FMPI2C4EN BIT(24)
+
+#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x44)
+#define STM32_RCC_APB2ENR_ADC1EN BIT(8) /* STM32F4 */
+
+#define STM32_RCC_PB2_USART6 BIT(5)
+#define STM32_RCC_SYSCFGEN BIT(14)
+
+#define STM32_RCC_AHB1LPENR REG32(STM32_RCC_BASE + 0x50)
+#define STM32_RCC_AHB2LPENR REG32(STM32_RCC_BASE + 0x54)
+#define STM32_RCC_AHB3LPENR REG32(STM32_RCC_BASE + 0x58)
+#define STM32_RCC_APB1LPENR REG32(STM32_RCC_BASE + 0x60)
+#define STM32_RCC_APB2LPENR REG32(STM32_RCC_BASE + 0x64)
+
+#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x70)
+#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x74)
+#define STM32_RCC_CSR_LSION BIT(0)
+#define STM32_RCC_CSR_LSIRDY BIT(1)
+
+#define STM32_RCC_PB2_TIM1 BIT(0)
+#define STM32_RCC_PB2_TIM8 BIT(1)
+#define STM32_RCC_PB2_TIM9 BIT(16)
+#define STM32_RCC_PB2_TIM10 BIT(17)
+#define STM32_RCC_PB2_TIM11 BIT(18)
+
+#define STM32_RCC_DCKCFGR2 REG32(STM32_RCC_BASE + 0x94)
+#define DCKCFGR2_FMPI2C1SEL(val) (((val)&0x3) << 22)
+#define DCKCFGR2_FMPI2C1SEL_MASK (0x3 << 22)
+#define FMPI2C1SEL_APB 0x0
+
+#define STM32_SYSCFG_MEMRMP REG32(STM32_SYSCFG_BASE + 0x00)
+#define STM32_SYSCFG_PMC REG32(STM32_SYSCFG_BASE + 0x04)
+#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
+#define STM32_SYSCFG_CMPCR REG32(STM32_SYSCFG_BASE + 0x20)
+#define STM32_SYSCFG_CFGR REG32(STM32_SYSCFG_BASE + 0x2C)
 
 /* Peripheral bits for RCC_APB/AHB regs */
-#define STM32_RCC_PB2_USART1		BIT(4)
+#define STM32_RCC_PB2_USART1 BIT(4)
 
 /* Reset causes definitions */
 /* Reset causes in RCC CSR register */
 #define STM32_RCC_RESET_CAUSE STM32_RCC_CSR
-#define  RESET_CAUSE_WDG                (BIT(30)|BIT(29))
-#define  RESET_CAUSE_SFT                BIT(28)
-#define  RESET_CAUSE_POR                BIT(27)
-#define  RESET_CAUSE_PIN                BIT(26)
-#define  RESET_CAUSE_OTHER              (BIT(31)|BIT(30)|BIT(29)|BIT(28)| \
-					 BIT(27)|BIT(26)|BIT(25))
-#define  RESET_CAUSE_RMVF                BIT(24)
+#define RESET_CAUSE_WDG (BIT(30) | BIT(29))
+#define RESET_CAUSE_SFT BIT(28)
+#define RESET_CAUSE_POR BIT(27)
+#define RESET_CAUSE_PIN BIT(26)
+#define RESET_CAUSE_OTHER \
+	(BIT(31) | BIT(30) | BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25))
+#define RESET_CAUSE_RMVF BIT(24)
 /* Power cause in PWR CSR register */
 #define STM32_PWR_RESET_CAUSE STM32_PWR_CSR
-#define  RESET_CAUSE_SBF                BIT(1)
+#define RESET_CAUSE_SBF BIT(1)
 #define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR
-#define  RESET_CAUSE_SBF_CLR            BIT(3)
+#define RESET_CAUSE_SBF_CLR BIT(3)
 
 /* --- Watchdogs --- */
 
 /* --- Real-Time Clock --- */
-#define STM32_RTC_TR                REG32(STM32_RTC_BASE + 0x00)
-#define STM32_RTC_DR                REG32(STM32_RTC_BASE + 0x04)
-#define STM32_RTC_CR                REG32(STM32_RTC_BASE + 0x08)
-#define STM32_RTC_CR_BYPSHAD        BIT(5)
-#define STM32_RTC_CR_ALRAE          BIT(8)
-#define STM32_RTC_CR_ALRAIE         BIT(12)
-#define STM32_RTC_ISR               REG32(STM32_RTC_BASE + 0x0C)
-#define STM32_RTC_ISR_ALRAWF        BIT(0)
-#define STM32_RTC_ISR_RSF           BIT(5)
-#define STM32_RTC_ISR_INITF         BIT(6)
-#define STM32_RTC_ISR_INIT          BIT(7)
-#define STM32_RTC_ISR_ALRAF         BIT(8)
-#define STM32_RTC_PRER              REG32(STM32_RTC_BASE + 0x10)
-#define STM32_RTC_PRER_A_MASK       (0x7f << 16)
-#define STM32_RTC_PRER_S_MASK       (0x7fff << 0)
-#define STM32_RTC_WUTR              REG32(STM32_RTC_BASE + 0x14)
-#define STM32_RTC_CALIBR            REG32(STM32_RTC_BASE + 0x18)
-#define STM32_RTC_ALRMAR            REG32(STM32_RTC_BASE + 0x1C)
-#define STM32_RTC_ALRMBR            REG32(STM32_RTC_BASE + 0x20)
-#define STM32_RTC_WPR               REG32(STM32_RTC_BASE + 0x24)
-#define STM32_RTC_SSR               REG32(STM32_RTC_BASE + 0x28)
-#define STM32_RTC_TSTR              REG32(STM32_RTC_BASE + 0x30)
-#define STM32_RTC_TSDR              REG32(STM32_RTC_BASE + 0x34)
-#define STM32_RTC_TAFCR             REG32(STM32_RTC_BASE + 0x40)
-#define STM32_RTC_ALRMASSR          REG32(STM32_RTC_BASE + 0x44)
-#define STM32_RTC_BACKUP(n)         REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
-
-#define STM32_BKP_DATA(n)           STM32_RTC_BACKUP(n)
-#define STM32_BKP_BYTES             80
+#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00)
+#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04)
+#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08)
+#define STM32_RTC_CR_BYPSHAD BIT(5)
+#define STM32_RTC_CR_ALRAE BIT(8)
+#define STM32_RTC_CR_ALRAIE BIT(12)
+#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C)
+#define STM32_RTC_ISR_ALRAWF BIT(0)
+#define STM32_RTC_ISR_RSF BIT(5)
+#define STM32_RTC_ISR_INITF BIT(6)
+#define STM32_RTC_ISR_INIT BIT(7)
+#define STM32_RTC_ISR_ALRAF BIT(8)
+#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10)
+#define STM32_RTC_PRER_A_MASK (0x7f << 16)
+#define STM32_RTC_PRER_S_MASK (0x7fff << 0)
+#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14)
+#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18)
+#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C)
+#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20)
+#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24)
+#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28)
+#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30)
+#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34)
+#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40)
+#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44)
+#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
+
+#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n)
+#define STM32_BKP_BYTES 80
 
 /* --- SPI --- */
 
@@ -666,8 +663,8 @@ struct stm32_spi_regs {
 	unsigned crcpr;
 	unsigned rxcrcr;
 	unsigned txcrcr;
-	unsigned i2scfgr;	/* STM32L only */
-	unsigned i2spr;		/* STM32L only */
+	unsigned i2scfgr; /* STM32L only */
+	unsigned i2spr; /* STM32L only */
 };
 /* Must be volatile, or compiler optimizes out repeated accesses */
 typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
@@ -677,185 +674,181 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
 #define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE)
 #define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE)
 
-#define STM32_SPI_CR1_BIDIMODE		BIT(15)
-#define STM32_SPI_CR1_BIDIOE		BIT(14)
-#define STM32_SPI_CR1_CRCEN		BIT(13)
-#define STM32_SPI_CR1_SSM		BIT(9)
-#define STM32_SPI_CR1_SSI		BIT(8)
-#define STM32_SPI_CR1_LSBFIRST		BIT(7)
-#define STM32_SPI_CR1_SPE		BIT(6)
-#define STM32_SPI_CR1_BR_DIV64R		(5 << 3)
-#define STM32_SPI_CR1_BR_DIV4R		BIT(3)
-#define STM32_SPI_CR1_MSTR		BIT(2)
-#define STM32_SPI_CR1_CPOL		BIT(1)
-#define STM32_SPI_CR1_CPHA		BIT(0)
-#define STM32_SPI_CR2_FRXTH		BIT(12)
-#define STM32_SPI_CR2_DATASIZE(n)	(((n) - 1) << 8)
-#define STM32_SPI_CR2_TXEIE		BIT(7)
-#define STM32_SPI_CR2_RXNEIE		BIT(6)
-#define STM32_SPI_CR2_NSSP		BIT(3)
-#define STM32_SPI_CR2_SSOE		BIT(2)
-#define STM32_SPI_CR2_TXDMAEN		BIT(1)
-#define STM32_SPI_CR2_RXDMAEN		BIT(0)
-
-#define STM32_SPI_SR_RXNE		BIT(0)
-#define STM32_SPI_SR_TXE		BIT(1)
-#define STM32_SPI_SR_CRCERR		BIT(4)
-#define STM32_SPI_SR_BSY		BIT(7)
-#define STM32_SPI_SR_FRLVL		(3 << 9)
-#define STM32_SPI_SR_FTLVL		(3 << 11)
+#define STM32_SPI_CR1_BIDIMODE BIT(15)
+#define STM32_SPI_CR1_BIDIOE BIT(14)
+#define STM32_SPI_CR1_CRCEN BIT(13)
+#define STM32_SPI_CR1_SSM BIT(9)
+#define STM32_SPI_CR1_SSI BIT(8)
+#define STM32_SPI_CR1_LSBFIRST BIT(7)
+#define STM32_SPI_CR1_SPE BIT(6)
+#define STM32_SPI_CR1_BR_DIV64R (5 << 3)
+#define STM32_SPI_CR1_BR_DIV4R BIT(3)
+#define STM32_SPI_CR1_MSTR BIT(2)
+#define STM32_SPI_CR1_CPOL BIT(1)
+#define STM32_SPI_CR1_CPHA BIT(0)
+#define STM32_SPI_CR2_FRXTH BIT(12)
+#define STM32_SPI_CR2_DATASIZE(n) (((n)-1) << 8)
+#define STM32_SPI_CR2_TXEIE BIT(7)
+#define STM32_SPI_CR2_RXNEIE BIT(6)
+#define STM32_SPI_CR2_NSSP BIT(3)
+#define STM32_SPI_CR2_SSOE BIT(2)
+#define STM32_SPI_CR2_TXDMAEN BIT(1)
+#define STM32_SPI_CR2_RXDMAEN BIT(0)
+
+#define STM32_SPI_SR_RXNE BIT(0)
+#define STM32_SPI_SR_TXE BIT(1)
+#define STM32_SPI_SR_CRCERR BIT(4)
+#define STM32_SPI_SR_BSY BIT(7)
+#define STM32_SPI_SR_FRLVL (3 << 9)
+#define STM32_SPI_SR_FTLVL (3 << 11)
 
 /* --- Debug --- */
 
-#define  STM32_DBGMCU_CR_SLEEP                      BIT(0)
-#define  STM32_DBGMCU_CR_STOP                       BIT(1)
-#define  STM32_DBGMCU_CR_STBY                       BIT(2)
-#define  STM32_DBGMCU_CR_TRACE_MASK                 (BIT(5)|BIT(6)|BIT(7))
-#define   STM32_DBGMCU_CR_TRACE_EN                   BIT(5)
-#define   STM32_DBGMCU_CR_TRACE_MODE_ASYNC           0
-#define   STM32_DBGMCU_CR_TRACE_MODE_SYNC1           BIT(6)
-#define   STM32_DBGMCU_CR_TRACE_MODE_SYNC2           BIT(7)
-#define   STM32_DBGMCU_CR_TRACE_MODE_SYNC4           (BIT(6)|BIT(7))
-#define STM32_DBGMCU_APB1FZ         REG32(STM32_DBGMCU_BASE + 0x08)
-#define  STM32_DBGMCU_APB1FZ_TIM2                   BIT(0)
-#define  STM32_DBGMCU_APB1FZ_TIM3                   BIT(1)
-#define  STM32_DBGMCU_APB1FZ_TIM4                   BIT(2)
-#define  STM32_DBGMCU_APB1FZ_TIM5                   BIT(3)
-#define  STM32_DBGMCU_APB1FZ_TIM6                   BIT(4)
-#define  STM32_DBGMCU_APB1FZ_TIM7                   BIT(5)
-#define  STM32_DBGMCU_APB1FZ_TIM12                  BIT(6)
-#define  STM32_DBGMCU_APB1FZ_TIM13                  BIT(7)
-#define  STM32_DBGMCU_APB1FZ_TIM14                  BIT(8)
-#define  STM32_DBGMCU_APB1FZ_RTC                    BIT(10)
-#define  STM32_DBGMCU_APB1FZ_WWDG                   BIT(11)
-#define  STM32_DBGMCU_APB1FZ_IWDG                   BIT(12)
-#define  STM32_DBGMCU_APB1FZ_I2C1_SMBUS_TIMEOUT     BIT(21)
-#define  STM32_DBGMCU_APB1FZ_I2C2_SMBUS_TIMEOUT     BIT(22)
-#define  STM32_DBGMCU_APB1FZ_I2C3_SMBUS_TIMEOUT     BIT(23)
-#define  STM32_DBGMCU_APB1FZ_I2CFMP_SMBUS_TIMEOUT   BIT(24)
-#define  STM32_DBGMCU_APB1FZ_CAN1                   BIT(25)
-#define  STM32_DBGMCU_APB1FZ_CAN2                   BIT(26)
-#define STM32_DBGMCU_APB2FZ         REG32(STM32_DBGMCU_BASE + 0x0C)
-#define  STM32_DBGMCU_APB2FZ_TIM1                   BIT(0)
-#define  STM32_DBGMCU_APB2FZ_TIM8                   BIT(1)
-#define  STM32_DBGMCU_APB2FZ_TIM9                   BIT(16)
-#define  STM32_DBGMCU_APB2FZ_TIM10                  BIT(17)
-#define  STM32_DBGMCU_APB2FZ_TIM11                  BIT(18)
+#define STM32_DBGMCU_CR_SLEEP BIT(0)
+#define STM32_DBGMCU_CR_STOP BIT(1)
+#define STM32_DBGMCU_CR_STBY BIT(2)
+#define STM32_DBGMCU_CR_TRACE_MASK (BIT(5) | BIT(6) | BIT(7))
+#define STM32_DBGMCU_CR_TRACE_EN BIT(5)
+#define STM32_DBGMCU_CR_TRACE_MODE_ASYNC 0
+#define STM32_DBGMCU_CR_TRACE_MODE_SYNC1 BIT(6)
+#define STM32_DBGMCU_CR_TRACE_MODE_SYNC2 BIT(7)
+#define STM32_DBGMCU_CR_TRACE_MODE_SYNC4 (BIT(6) | BIT(7))
+#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08)
+#define STM32_DBGMCU_APB1FZ_TIM2 BIT(0)
+#define STM32_DBGMCU_APB1FZ_TIM3 BIT(1)
+#define STM32_DBGMCU_APB1FZ_TIM4 BIT(2)
+#define STM32_DBGMCU_APB1FZ_TIM5 BIT(3)
+#define STM32_DBGMCU_APB1FZ_TIM6 BIT(4)
+#define STM32_DBGMCU_APB1FZ_TIM7 BIT(5)
+#define STM32_DBGMCU_APB1FZ_TIM12 BIT(6)
+#define STM32_DBGMCU_APB1FZ_TIM13 BIT(7)
+#define STM32_DBGMCU_APB1FZ_TIM14 BIT(8)
+#define STM32_DBGMCU_APB1FZ_RTC BIT(10)
+#define STM32_DBGMCU_APB1FZ_WWDG BIT(11)
+#define STM32_DBGMCU_APB1FZ_IWDG BIT(12)
+#define STM32_DBGMCU_APB1FZ_I2C1_SMBUS_TIMEOUT BIT(21)
+#define STM32_DBGMCU_APB1FZ_I2C2_SMBUS_TIMEOUT BIT(22)
+#define STM32_DBGMCU_APB1FZ_I2C3_SMBUS_TIMEOUT BIT(23)
+#define STM32_DBGMCU_APB1FZ_I2CFMP_SMBUS_TIMEOUT BIT(24)
+#define STM32_DBGMCU_APB1FZ_CAN1 BIT(25)
+#define STM32_DBGMCU_APB1FZ_CAN2 BIT(26)
+#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C)
+#define STM32_DBGMCU_APB2FZ_TIM1 BIT(0)
+#define STM32_DBGMCU_APB2FZ_TIM8 BIT(1)
+#define STM32_DBGMCU_APB2FZ_TIM9 BIT(16)
+#define STM32_DBGMCU_APB2FZ_TIM10 BIT(17)
+#define STM32_DBGMCU_APB2FZ_TIM11 BIT(18)
 
 /* --- Flash --- */
-#define STM32_FLASH_ACR             REG32(STM32_FLASH_REGS_BASE + 0x00)
-#define STM32_FLASH_ACR_SHIFT           0
-#define STM32_FLASH_ACR_LAT_MASK        0xf
-#define STM32_FLASH_ACR_PRFTEN          BIT(8)
-#define STM32_FLASH_ACR_ICEN            BIT(9)
-#define STM32_FLASH_ACR_DCEN            BIT(10)
-#define STM32_FLASH_ACR_ICRST           BIT(11)
-#define STM32_FLASH_ACR_DCRST           BIT(12)
-#define STM32_FLASH_KEYR            REG32(STM32_FLASH_REGS_BASE + 0x04)
-#define  FLASH_KEYR_KEY1                0x45670123
-#define  FLASH_KEYR_KEY2                0xCDEF89AB
-#define STM32_FLASH_OPTKEYR         REG32(STM32_FLASH_REGS_BASE + 0x08)
-#define  FLASH_OPTKEYR_KEY1             0x08192A3B
-#define  FLASH_OPTKEYR_KEY2             0x4C5D6E7F
-#define STM32_FLASH_SR              REG32(STM32_FLASH_REGS_BASE + 0x0c)
-#define  FLASH_SR_EOP                   BIT(0)
-#define  FLASH_SR_OPERR                 BIT(1)
-#define  FLASH_SR_WRPERR                BIT(4)
-#define  FLASH_SR_PGAERR                BIT(5)
-#define  FLASH_SR_PGPERR                BIT(6)
-#define  FLASH_SR_PGSERR                BIT(7)
-#define  FLASH_SR_RDERR                 BIT(8)
-#define  FLASH_SR_ALL_ERR \
+#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00)
+#define STM32_FLASH_ACR_SHIFT 0
+#define STM32_FLASH_ACR_LAT_MASK 0xf
+#define STM32_FLASH_ACR_PRFTEN BIT(8)
+#define STM32_FLASH_ACR_ICEN BIT(9)
+#define STM32_FLASH_ACR_DCEN BIT(10)
+#define STM32_FLASH_ACR_ICRST BIT(11)
+#define STM32_FLASH_ACR_DCRST BIT(12)
+#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x04)
+#define FLASH_KEYR_KEY1 0x45670123
+#define FLASH_KEYR_KEY2 0xCDEF89AB
+#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x08)
+#define FLASH_OPTKEYR_KEY1 0x08192A3B
+#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F
+#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x0c)
+#define FLASH_SR_EOP BIT(0)
+#define FLASH_SR_OPERR BIT(1)
+#define FLASH_SR_WRPERR BIT(4)
+#define FLASH_SR_PGAERR BIT(5)
+#define FLASH_SR_PGPERR BIT(6)
+#define FLASH_SR_PGSERR BIT(7)
+#define FLASH_SR_RDERR BIT(8)
+#define FLASH_SR_ALL_ERR                                      \
 	(FLASH_SR_OPERR | FLASH_SR_WRPERR | FLASH_SR_PGAERR | \
 	 FLASH_SR_PGPERR | FLASH_SR_PGSERR | FLASH_SR_RDERR)
-#define  FLASH_SR_BUSY                   BIT(16)
-#define STM32_FLASH_CR              REG32(STM32_FLASH_REGS_BASE + 0x10)
-#define  FLASH_CR_PG                    BIT(0)
-#define  FLASH_CR_PER                   BIT(1)
-#define  FLASH_CR_MER                   BIT(2)
-#define STM32_FLASH_CR_SNB_OFFSET       (3)
-#define STM32_FLASH_CR_SNB(sec) \
-	(((sec) & 0xf) << STM32_FLASH_CR_SNB_OFFSET)
-#define STM32_FLASH_CR_SNB_MASK         (STM32_FLASH_CR_SNB(0xf))
-#define STM32_FLASH_CR_PSIZE_OFFSET     (8)
-#define STM32_FLASH_CR_PSIZE(size) \
-	(((size) & 0x3) << STM32_FLASH_CR_PSIZE_OFFSET)
-#define STM32_FLASH_CR_PSIZE_MASK       (STM32_FLASH_CR_PSIZE(0x3))
-#define  FLASH_CR_STRT                  BIT(16)
-#define  FLASH_CR_LOCK                  BIT(31)
-#define STM32_FLASH_OPTCR           REG32(STM32_FLASH_REGS_BASE + 0x14)
-#define  FLASH_OPTLOCK                  BIT(0)
-#define  FLASH_OPTSTRT                  BIT(1)
-#define STM32_FLASH_BOR_LEV_OFFSET      (2)
-#define  FLASH_OPTCR_RDP_SHIFT		(8)
-#define  FLASH_OPTCR_RDP_MASK		(0xFF << FLASH_OPTCR_RDP_SHIFT)
-#define  FLASH_OPTCR_RDP_LEVEL_0		(0xAA << FLASH_OPTCR_RDP_SHIFT)
+#define FLASH_SR_BUSY BIT(16)
+#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x10)
+#define FLASH_CR_PG BIT(0)
+#define FLASH_CR_PER BIT(1)
+#define FLASH_CR_MER BIT(2)
+#define STM32_FLASH_CR_SNB_OFFSET (3)
+#define STM32_FLASH_CR_SNB(sec) (((sec)&0xf) << STM32_FLASH_CR_SNB_OFFSET)
+#define STM32_FLASH_CR_SNB_MASK (STM32_FLASH_CR_SNB(0xf))
+#define STM32_FLASH_CR_PSIZE_OFFSET (8)
+#define STM32_FLASH_CR_PSIZE(size) (((size)&0x3) << STM32_FLASH_CR_PSIZE_OFFSET)
+#define STM32_FLASH_CR_PSIZE_MASK (STM32_FLASH_CR_PSIZE(0x3))
+#define FLASH_CR_STRT BIT(16)
+#define FLASH_CR_LOCK BIT(31)
+#define STM32_FLASH_OPTCR REG32(STM32_FLASH_REGS_BASE + 0x14)
+#define FLASH_OPTLOCK BIT(0)
+#define FLASH_OPTSTRT BIT(1)
+#define STM32_FLASH_BOR_LEV_OFFSET (2)
+#define FLASH_OPTCR_RDP_SHIFT (8)
+#define FLASH_OPTCR_RDP_MASK (0xFF << FLASH_OPTCR_RDP_SHIFT)
+#define FLASH_OPTCR_RDP_LEVEL_0 (0xAA << FLASH_OPTCR_RDP_SHIFT)
 /* RDP Level 1: Anything but 0xAA/0xCC */
-#define  FLASH_OPTCR_RDP_LEVEL_1		(0x00 << FLASH_OPTCR_RDP_SHIFT)
-#define  FLASH_OPTCR_RDP_LEVEL_2		(0xCC << FLASH_OPTCR_RDP_SHIFT)
-#define STM32_FLASH_nWRP_OFFSET         (16)
-#define STM32_FLASH_nWRP(_bank)         BIT(_bank + STM32_FLASH_nWRP_OFFSET)
-#define STM32_FLASH_nWRP_ALL            (0xFF << STM32_FLASH_nWRP_OFFSET)
-#define STM32_FLASH_OPT_LOCKED      (STM32_FLASH_OPTCR & FLASH_OPTLOCK)
-
-#define STM32_OPTB_RDP_USER         REG32(STM32_OPTB_BASE + 0x00)
-#define STM32_OPTB_RDP_OFF              0x00
-#define STM32_OPTB_USER_OFF             0x02
-#define STM32_OPTB_WRP_OFF(n)       (0x08 + (n&3) * 2)
-#define STM32_OPTB_WP               REG32(STM32_OPTB_BASE + 0x08)
-#define STM32_OPTB_nWRP(_bank)          BIT(_bank)
-#define STM32_OPTB_nWRP_ALL             (0xFF)
-
-#define STM32_OPTB_COMPL_SHIFT      8
-
-#define STM32_OTP_BLOCK_NB              16
-#define STM32_OTP_BLOCK_SIZE            32
+#define FLASH_OPTCR_RDP_LEVEL_1 (0x00 << FLASH_OPTCR_RDP_SHIFT)
+#define FLASH_OPTCR_RDP_LEVEL_2 (0xCC << FLASH_OPTCR_RDP_SHIFT)
+#define STM32_FLASH_nWRP_OFFSET (16)
+#define STM32_FLASH_nWRP(_bank) BIT(_bank + STM32_FLASH_nWRP_OFFSET)
+#define STM32_FLASH_nWRP_ALL (0xFF << STM32_FLASH_nWRP_OFFSET)
+#define STM32_FLASH_OPT_LOCKED (STM32_FLASH_OPTCR & FLASH_OPTLOCK)
+
+#define STM32_OPTB_RDP_USER REG32(STM32_OPTB_BASE + 0x00)
+#define STM32_OPTB_RDP_OFF 0x00
+#define STM32_OPTB_USER_OFF 0x02
+#define STM32_OPTB_WRP_OFF(n) (0x08 + (n & 3) * 2)
+#define STM32_OPTB_WP REG32(STM32_OPTB_BASE + 0x08)
+#define STM32_OPTB_nWRP(_bank) BIT(_bank)
+#define STM32_OPTB_nWRP_ALL (0xFF)
+
+#define STM32_OPTB_COMPL_SHIFT 8
+
+#define STM32_OTP_BLOCK_NB 16
+#define STM32_OTP_BLOCK_SIZE 32
 #define STM32_OTP_BLOCK_DATA(_block, _offset) \
-	(STM32_OTP_BASE + STM32_OTP_BLOCK_SIZE * (_block) + (_offset) * 4)
-#define STM32_OTP_UNLOCK_BYTE           0x00
-#define STM32_OTP_LOCK_BYTE             0xFF
-#define STM32_OTP_LOCK_BASE         \
+	(STM32_OTP_BASE + STM32_OTP_BLOCK_SIZE * (_block) + (_offset)*4)
+#define STM32_OTP_UNLOCK_BYTE 0x00
+#define STM32_OTP_LOCK_BYTE 0xFF
+#define STM32_OTP_LOCK_BASE \
 	(STM32_OTP_BASE + STM32_OTP_BLOCK_NB * STM32_OTP_BLOCK_SIZE)
-#define STM32_OTP_LOCK(_block) \
-	(STM32_OTP_LOCK_BASE + ((_block) / 4) * 4)
-#define STM32_OPT_LOCK_MASK(_block)    ((0xFF << ((_block) % 4) * 8))
+#define STM32_OTP_LOCK(_block) (STM32_OTP_LOCK_BASE + ((_block) / 4) * 4)
+#define STM32_OPT_LOCK_MASK(_block) ((0xFF << ((_block) % 4) * 8))
 
 /* --- External Interrupts --- */
-#define STM32_EXTI_IMR              REG32(STM32_EXTI_BASE + 0x00)
-#define STM32_EXTI_EMR              REG32(STM32_EXTI_BASE + 0x04)
-#define STM32_EXTI_RTSR             REG32(STM32_EXTI_BASE + 0x08)
-#define STM32_EXTI_FTSR             REG32(STM32_EXTI_BASE + 0x0c)
-#define STM32_EXTI_SWIER            REG32(STM32_EXTI_BASE + 0x10)
-#define STM32_EXTI_PR               REG32(STM32_EXTI_BASE + 0x14)
+#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00)
+#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04)
+#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08)
+#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c)
+#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10)
+#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14)
 
 #define EXTI_RTC_ALR_EVENT BIT(17)
 
 /* --- ADC --- */
-#define STM32_ADC_SR               REG32(STM32_ADC1_BASE + 0x00)
-#define STM32_ADC_CR1              REG32(STM32_ADC1_BASE + 0x04)
-#define STM32_ADC_CR2              REG32(STM32_ADC1_BASE + 0x08)
-#define STM32_ADC_CR2_ADON         BIT(0)
-#define STM32_ADC_CR2_CONT         BIT(1)
-#define STM32_ADC_CR2_CAL          BIT(2)
-#define STM32_ADC_CR2_RSTCAL       BIT(3)
-#define STM32_ADC_CR2_ALIGN        BIT(11)
-#define STM32_ADC_CR2_SWSTART      BIT(30)
-#define STM32_ADC_SMPR1            REG32(STM32_ADC1_BASE + 0x0C)
-#define STM32_ADC_SMPR2            REG32(STM32_ADC1_BASE + 0x10)
-#define STM32_ADC_JOFR(n)          REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4)
-#define STM32_ADC_HTR              REG32(STM32_ADC1_BASE + 0x24)
-#define STM32_ADC_LTR              REG32(STM32_ADC1_BASE + 0x28)
-#define STM32_ADC_SQR(n)           REG32(STM32_ADC1_BASE + 0x28 + ((n)&3) * 4)
-#define STM32_ADC_SQR1             REG32(STM32_ADC1_BASE + 0x2C)
-#define STM32_ADC_SQR2             REG32(STM32_ADC1_BASE + 0x30)
-#define STM32_ADC_SQR3             REG32(STM32_ADC1_BASE + 0x34)
-#define STM32_ADC_JSQR             REG32(STM32_ADC1_BASE + 0x38)
-#define STM32_ADC_JDR(n)           REG32(STM32_ADC1_BASE + 0x3C + ((n)&3) * 4)
-#define STM32_ADC_DR               REG32(STM32_ADC1_BASE + 0x4C)
+#define STM32_ADC_SR REG32(STM32_ADC1_BASE + 0x00)
+#define STM32_ADC_CR1 REG32(STM32_ADC1_BASE + 0x04)
+#define STM32_ADC_CR2 REG32(STM32_ADC1_BASE + 0x08)
+#define STM32_ADC_CR2_ADON BIT(0)
+#define STM32_ADC_CR2_CONT BIT(1)
+#define STM32_ADC_CR2_CAL BIT(2)
+#define STM32_ADC_CR2_RSTCAL BIT(3)
+#define STM32_ADC_CR2_ALIGN BIT(11)
+#define STM32_ADC_CR2_SWSTART BIT(30)
+#define STM32_ADC_SMPR1 REG32(STM32_ADC1_BASE + 0x0C)
+#define STM32_ADC_SMPR2 REG32(STM32_ADC1_BASE + 0x10)
+#define STM32_ADC_JOFR(n) REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4)
+#define STM32_ADC_HTR REG32(STM32_ADC1_BASE + 0x24)
+#define STM32_ADC_LTR REG32(STM32_ADC1_BASE + 0x28)
+#define STM32_ADC_SQR(n) REG32(STM32_ADC1_BASE + 0x28 + ((n)&3) * 4)
+#define STM32_ADC_SQR1 REG32(STM32_ADC1_BASE + 0x2C)
+#define STM32_ADC_SQR2 REG32(STM32_ADC1_BASE + 0x30)
+#define STM32_ADC_SQR3 REG32(STM32_ADC1_BASE + 0x34)
+#define STM32_ADC_JSQR REG32(STM32_ADC1_BASE + 0x38)
+#define STM32_ADC_JDR(n) REG32(STM32_ADC1_BASE + 0x3C + ((n)&3) * 4)
+#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x4C)
 
 /* --- Comparators --- */
 
-
 /* --- DMA --- */
 /*
  * Available DMA streams, numbered from 0.
@@ -963,12 +956,12 @@ enum dma_channel {
 
 /* Registers for a single stream of a DMA controller */
 struct stm32_dma_stream {
-	uint32_t	scr;		/* Control */
-	uint32_t	sndtr;		/* Number of data to transfer */
-	uint32_t	spar;		/* Peripheral address */
-	uint32_t	sm0ar;		/* Memory address 0 */
-	uint32_t	sm1ar;		/*  address 1 for double buffer */
-	uint32_t	sfcr;		/* FIFO control */
+	uint32_t scr; /* Control */
+	uint32_t sndtr; /* Number of data to transfer */
+	uint32_t spar; /* Peripheral address */
+	uint32_t sm0ar; /* Memory address 0 */
+	uint32_t sm1ar; /*  address 1 for double buffer */
+	uint32_t sfcr; /* FIFO control */
 };
 
 /* Always use stm32_dma_stream_t so volatile keyword is included! */
@@ -977,12 +970,11 @@ typedef volatile struct stm32_dma_stream stm32_dma_stream_t;
 /* Common code and header file must use this */
 typedef stm32_dma_stream_t dma_chan_t;
 struct stm32_dma_regs {
-	uint32_t	isr[2];
-	uint32_t	ifcr[2];
+	uint32_t isr[2];
+	uint32_t ifcr[2];
 	stm32_dma_stream_t stream[STM32_DMAS_COUNT];
 };
 
-
 /* Always use stm32_dma_regs_t so volatile keyword is included! */
 typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
 
@@ -993,109 +985,106 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
 #define STM32_DMA_REGS(channel) \
 	((channel) < STM32_DMAS_COUNT ? STM32_DMA1_REGS : STM32_DMA2_REGS)
 
-#define STM32_DMA_CCR_EN                BIT(0)
-#define STM32_DMA_CCR_DMEIE             BIT(1)
-#define STM32_DMA_CCR_TEIE              BIT(2)
-#define STM32_DMA_CCR_HTIE              BIT(3)
-#define STM32_DMA_CCR_TCIE              BIT(4)
-#define STM32_DMA_CCR_PFCTRL            BIT(5)
-#define STM32_DMA_CCR_DIR_P2M		(0 << 6)
-#define STM32_DMA_CCR_DIR_M2P		(1 << 6)
-#define STM32_DMA_CCR_DIR_M2M		(2 << 6)
-#define STM32_DMA_CCR_CIRC              BIT(8)
-#define STM32_DMA_CCR_PINC              BIT(9)
-#define STM32_DMA_CCR_MINC              BIT(10)
-#define STM32_DMA_CCR_PSIZE_8_BIT       (0 << 11)
-#define STM32_DMA_CCR_PSIZE_16_BIT      (1 << 11)
-#define STM32_DMA_CCR_PSIZE_32_BIT      (2 << 11)
-#define STM32_DMA_CCR_MSIZE_8_BIT       (0 << 13)
-#define STM32_DMA_CCR_MSIZE_16_BIT      (1 << 13)
-#define STM32_DMA_CCR_MSIZE_32_BIT      (2 << 13)
-#define STM32_DMA_CCR_PINCOS            BIT(15)
-#define STM32_DMA_CCR_PL_LOW            (0 << 16)
-#define STM32_DMA_CCR_PL_MEDIUM         (1 << 16)
-#define STM32_DMA_CCR_PL_HIGH           (2 << 16)
-#define STM32_DMA_CCR_PL_VERY_HIGH      (3 << 16)
-#define STM32_DMA_CCR_DBM               BIT(18)
-#define STM32_DMA_CCR_CT                BIT(19)
-#define STM32_DMA_CCR_PBURST(b_len)		 ((((b_len) - 4) / 4) << 21)
-#define STM32_DMA_CCR_MBURST(b_len)		 ((((b_len) - 4) / 4) << 21)
-#define STM32_DMA_CCR_CHANNEL_MASK		 (0x7 << 25)
-#define STM32_DMA_CCR_CHANNEL(channel)		 ((channel) << 25)
-#define STM32_DMA_CCR_RSVD_MASK		(0xF0100000)
-
-
-#define STM32_DMA_SFCR_DMDIS		BIT(2)
-#define STM32_DMA_SFCR_FTH(level)	(((level) - 1) << 0)
-
-
-#define STM32_DMA_CH_LOCAL(channel)     ((channel) % STM32_DMAS_COUNT)
-#define STM32_DMA_CH_LH(channel)        \
-	((STM32_DMA_CH_LOCAL(channel) < 4) ? 0 : 1)
-#define STM32_DMA_CH_OFFSET(channel)    \
+#define STM32_DMA_CCR_EN BIT(0)
+#define STM32_DMA_CCR_DMEIE BIT(1)
+#define STM32_DMA_CCR_TEIE BIT(2)
+#define STM32_DMA_CCR_HTIE BIT(3)
+#define STM32_DMA_CCR_TCIE BIT(4)
+#define STM32_DMA_CCR_PFCTRL BIT(5)
+#define STM32_DMA_CCR_DIR_P2M (0 << 6)
+#define STM32_DMA_CCR_DIR_M2P (1 << 6)
+#define STM32_DMA_CCR_DIR_M2M (2 << 6)
+#define STM32_DMA_CCR_CIRC BIT(8)
+#define STM32_DMA_CCR_PINC BIT(9)
+#define STM32_DMA_CCR_MINC BIT(10)
+#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 11)
+#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 11)
+#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 11)
+#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 13)
+#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 13)
+#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 13)
+#define STM32_DMA_CCR_PINCOS BIT(15)
+#define STM32_DMA_CCR_PL_LOW (0 << 16)
+#define STM32_DMA_CCR_PL_MEDIUM (1 << 16)
+#define STM32_DMA_CCR_PL_HIGH (2 << 16)
+#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 16)
+#define STM32_DMA_CCR_DBM BIT(18)
+#define STM32_DMA_CCR_CT BIT(19)
+#define STM32_DMA_CCR_PBURST(b_len) ((((b_len)-4) / 4) << 21)
+#define STM32_DMA_CCR_MBURST(b_len) ((((b_len)-4) / 4) << 21)
+#define STM32_DMA_CCR_CHANNEL_MASK (0x7 << 25)
+#define STM32_DMA_CCR_CHANNEL(channel) ((channel) << 25)
+#define STM32_DMA_CCR_RSVD_MASK (0xF0100000)
+
+#define STM32_DMA_SFCR_DMDIS BIT(2)
+#define STM32_DMA_SFCR_FTH(level) (((level)-1) << 0)
+
+#define STM32_DMA_CH_LOCAL(channel) ((channel) % STM32_DMAS_COUNT)
+#define STM32_DMA_CH_LH(channel) ((STM32_DMA_CH_LOCAL(channel) < 4) ? 0 : 1)
+#define STM32_DMA_CH_OFFSET(channel)               \
 	(((STM32_DMA_CH_LOCAL(channel) % 4) * 6) + \
-	(((STM32_DMA_CH_LOCAL(channel) % 4) >= 2) ? 4 : 0))
+	 (((STM32_DMA_CH_LOCAL(channel) % 4) >= 2) ? 4 : 0))
 #define STM32_DMA_CH_GETBITS(channel, val) \
 	(((val) >> STM32_DMA_CH_OFFSET(channel)) & 0x3f)
-#define STM32_DMA_GET_IFCR(channel)      \
-	(STM32_DMA_CH_GETBITS(channel,   \
-	STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)]))
-#define STM32_DMA_GET_ISR(channel)       \
-	(STM32_DMA_CH_GETBITS(channel,   \
-	STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)]))
-
-#define STM32_DMA_SET_IFCR(channel, val) \
-	(STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] = \
-	(STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] & \
-	~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel)))
-#define STM32_DMA_SET_ISR(channel, val) \
-	(STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] = \
-	(STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] & \
-	~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel)))
-
-#define STM32_DMA_FEIF                  BIT(0)
-#define STM32_DMA_DMEIF                 BIT(2)
-#define STM32_DMA_TEIF                  BIT(3)
-#define STM32_DMA_HTIF                  BIT(4)
-#define STM32_DMA_TCIF                  BIT(5)
-#define STM32_DMA_ALL                   0x3d
-
-
+#define STM32_DMA_GET_IFCR(channel) \
+	(STM32_DMA_CH_GETBITS(      \
+		channel,            \
+		STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)]))
+#define STM32_DMA_GET_ISR(channel) \
+	(STM32_DMA_CH_GETBITS(     \
+		channel,           \
+		STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)]))
+
+#define STM32_DMA_SET_IFCR(channel, val)                                    \
+	(STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] =          \
+		 (STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] & \
+		  ~(0x3f << STM32_DMA_CH_OFFSET(channel))) |                \
+		 (((val)&0x3f) << STM32_DMA_CH_OFFSET(channel)))
+#define STM32_DMA_SET_ISR(channel, val)                                    \
+	(STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] =          \
+		 (STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] & \
+		  ~(0x3f << STM32_DMA_CH_OFFSET(channel))) |               \
+		 (((val)&0x3f) << STM32_DMA_CH_OFFSET(channel)))
+
+#define STM32_DMA_FEIF BIT(0)
+#define STM32_DMA_DMEIF BIT(2)
+#define STM32_DMA_TEIF BIT(3)
+#define STM32_DMA_HTIF BIT(4)
+#define STM32_DMA_TCIF BIT(5)
+#define STM32_DMA_ALL 0x3d
 
 /* --- CRC --- */
-#define STM32_CRC_DR                REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR32              REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR16              REG16(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR8               REG8(STM32_CRC_BASE + 0x0)
-
-#define STM32_CRC_IDR               REG32(STM32_CRC_BASE + 0x4)
-#define STM32_CRC_CR                REG32(STM32_CRC_BASE + 0x8)
-#define STM32_CRC_INIT              REG32(STM32_CRC_BASE + 0x10)
-#define STM32_CRC_POL               REG32(STM32_CRC_BASE + 0x14)
-
-#define STM32_CRC_CR_RESET          BIT(0)
-#define STM32_CRC_CR_POLYSIZE_32    (0 << 3)
-#define STM32_CRC_CR_POLYSIZE_16    (1 << 3)
-#define STM32_CRC_CR_POLYSIZE_8     (2 << 3)
-#define STM32_CRC_CR_POLYSIZE_7     (3 << 3)
-#define STM32_CRC_CR_REV_IN_BYTE    (1 << 5)
-#define STM32_CRC_CR_REV_IN_HWORD   (2 << 5)
-#define STM32_CRC_CR_REV_IN_WORD    (3 << 5)
-#define STM32_CRC_CR_REV_OUT        BIT(7)
-
-#define EP_MASK     0x0F0F
-#define EP_TX_DTOG  0x0040
-#define EP_TX_MASK  0x0030
+#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0)
+
+#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4)
+#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8)
+#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10)
+#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14)
+
+#define STM32_CRC_CR_RESET BIT(0)
+#define STM32_CRC_CR_POLYSIZE_32 (0 << 3)
+#define STM32_CRC_CR_POLYSIZE_16 (1 << 3)
+#define STM32_CRC_CR_POLYSIZE_8 (2 << 3)
+#define STM32_CRC_CR_POLYSIZE_7 (3 << 3)
+#define STM32_CRC_CR_REV_IN_BYTE (1 << 5)
+#define STM32_CRC_CR_REV_IN_HWORD (2 << 5)
+#define STM32_CRC_CR_REV_IN_WORD (3 << 5)
+#define STM32_CRC_CR_REV_OUT BIT(7)
+
+#define EP_MASK 0x0F0F
+#define EP_TX_DTOG 0x0040
+#define EP_TX_MASK 0x0030
 #define EP_TX_VALID 0x0030
-#define EP_TX_NAK   0x0020
+#define EP_TX_NAK 0x0020
 #define EP_TX_STALL 0x0010
 #define EP_TX_DISAB 0x0000
-#define EP_RX_DTOG  0x4000
-#define EP_RX_MASK  0x3000
+#define EP_RX_DTOG 0x4000
+#define EP_RX_MASK 0x3000
 #define EP_RX_VALID 0x3000
-#define EP_RX_NAK   0x2000
+#define EP_RX_NAK 0x2000
 #define EP_RX_STALL 0x1000
 #define EP_RX_DISAB 0x0000
 
@@ -1105,28 +1094,27 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
 #define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID)
 
 #define STM32_TOGGLE_EP(n, mask, val, flags) \
-	STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \
-			^ (val)) | (flags))
+	STM32_USB_EP(n) =                    \
+		(((STM32_USB_EP(n) & (EP_MASK | (mask))) ^ (val)) | (flags))
 
 /* --- TRNG --- */
-#define STM32_RNG_CR                REG32(STM32_RNG_BASE + 0x0)
-#define STM32_RNG_CR_RNGEN          BIT(2)
-#define STM32_RNG_CR_IE             BIT(3)
-#define STM32_RNG_CR_CED            BIT(5)
-#define STM32_RNG_SR                REG32(STM32_RNG_BASE + 0x4)
-#define STM32_RNG_SR_DRDY           BIT(0)
-#define STM32_RNG_DR                REG32(STM32_RNG_BASE + 0x8)
+#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0)
+#define STM32_RNG_CR_RNGEN BIT(2)
+#define STM32_RNG_CR_IE BIT(3)
+#define STM32_RNG_CR_CED BIT(5)
+#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4)
+#define STM32_RNG_SR_DRDY BIT(0)
+#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8)
 
 /* --- AXI interconnect --- */
 
 /* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */
-#define STM32_AXI_TARG_FN_MOD(x)    REG32(STM32_GPV_BASE + 0x1108 + \
-					  0x1000 * (x))
-#define  WRITE_ISS_OVERRIDE         BIT(1)
-#define  READ_ISS_OVERRIDE          BIT(0)
+#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + 0x1000 * (x))
+#define WRITE_ISS_OVERRIDE BIT(1)
+#define READ_ISS_OVERRIDE BIT(0)
 
 /* --- MISC --- */
-#define STM32_UNIQUE_ID_ADDRESS     REG32_ADDR(STM32_UNIQUE_ID_BASE)
-#define STM32_UNIQUE_ID_LENGTH      (3 * 4)
+#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE)
+#define STM32_UNIQUE_ID_LENGTH (3 * 4)
 
 #endif /* !__ASSEMBLER__ */
diff --git a/chip/stm32/registers-stm32f7.h b/chip/stm32/registers-stm32f7.h
index 7c039c9d61..a597cbfe68 100644
--- a/chip/stm32/registers-stm32f7.h
+++ b/chip/stm32/registers-stm32f7.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,100 +19,99 @@
 #endif
 
 /* --- IRQ numbers --- */
-#define STM32_IRQ_WWDG             0
-#define STM32_IRQ_PVD              1
-#define STM32_IRQ_TAMPER_STAMP     2
-#define STM32_IRQ_RTC_WAKEUP       3
-#define STM32_IRQ_FLASH            4
-#define STM32_IRQ_RCC              5
-#define STM32_IRQ_EXTI0            6
-#define STM32_IRQ_EXTI1            7
-#define STM32_IRQ_EXTI2            8
-#define STM32_IRQ_EXTI3            9
-#define STM32_IRQ_EXTI4           10
-#define STM32_IRQ_DMA_CHANNEL_1   11
-#define STM32_IRQ_DMA_CHANNEL_2   12
-#define STM32_IRQ_DMA_CHANNEL_3   13
-#define STM32_IRQ_DMA_CHANNEL_4   14
-#define STM32_IRQ_DMA_CHANNEL_5   15
-#define STM32_IRQ_DMA_CHANNEL_6   16
-#define STM32_IRQ_DMA_CHANNEL_7   17
-#define STM32_IRQ_USB_HP          19
-#define STM32_IRQ_USB_LP          20
-
-#define STM32_IRQ_ADC1            18 /* STM32L4 only */
-#define STM32_IRQ_CAN_TX          19 /* STM32F373 only */
-#define STM32_IRQ_USB_LP_CAN_RX   20 /* STM32F373 only */
-#define STM32_IRQ_DAC             21
-#define STM32_IRQ_CAN_RX1         21 /* STM32F373 only */
-
-#define STM32_IRQ_COMP            22
-
-#define STM32_IRQ_CAN_SCE         22 /* STM32F373 only */
-#define STM32_IRQ_EXTI9_5         23
-#define STM32_IRQ_LCD             24 /* STM32L15X only */
-#define STM32_IRQ_TIM15           24 /* STM32F373 only */
-#define STM32_IRQ_TIM9            25 /* STM32L15X only */
-#define STM32_IRQ_TIM16           25 /* STM32F373 only */
-#define STM32_IRQ_TIM10           26 /* STM32L15X only */
-#define STM32_IRQ_TIM17           26 /* STM32F373 only */
-#define STM32_IRQ_TIM11           27 /* STM32L15X only */
-#define STM32_IRQ_TIM18_DAC2      27 /* STM32F373 only */
-#define STM32_IRQ_TIM2            28
-#define STM32_IRQ_TIM3            29
-#define STM32_IRQ_TIM4            30
-#define STM32_IRQ_I2C1_EV         31
-#define STM32_IRQ_I2C1_ER         32
-#define STM32_IRQ_I2C2_EV         33
-#define STM32_IRQ_I2C2_ER         34
-#define STM32_IRQ_SPI1            35
-#define STM32_IRQ_SPI2            36
-#define STM32_IRQ_USART1          37
-#define STM32_IRQ_USART2          38
-#define STM32_IRQ_USART3          39
-#define STM32_IRQ_EXTI15_10       40
-#define STM32_IRQ_RTC_ALARM       41
-#define STM32_IRQ_USB_FS_WAKEUP   42 /* STM32L15X */
-#define STM32_IRQ_CEC             42 /* STM32F373 only */
-#define STM32_IRQ_TIM6_BASIC      43 /* STM32L15X only */
-#define STM32_IRQ_TIM12           43 /* STM32F373 only */
-#define STM32_IRQ_TIM7_BASIC      44 /* STM32L15X only */
-#define STM32_IRQ_TIM13           44 /* STM32F373 only */
-#define STM32_IRQ_TIM14           45 /* STM32F373 only */
-#define STM32_IRQ_TIM5            50 /* STM32F373 */
-#define STM32_IRQ_SPI3            51 /* STM32F373 */
-#define STM32_IRQ_USART4          52 /* STM32F446 only */
-#define STM32_IRQ_USART5          53 /* STM32F446 only */
-#define STM32_IRQ_TIM6_DAC        54 /* STM32F373 */
-#define STM32_IRQ_TIM7            55 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL1   56 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL2   57 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL3   58 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL4   59 /* STM32F373 only */
+#define STM32_IRQ_WWDG 0
+#define STM32_IRQ_PVD 1
+#define STM32_IRQ_TAMPER_STAMP 2
+#define STM32_IRQ_RTC_WAKEUP 3
+#define STM32_IRQ_FLASH 4
+#define STM32_IRQ_RCC 5
+#define STM32_IRQ_EXTI0 6
+#define STM32_IRQ_EXTI1 7
+#define STM32_IRQ_EXTI2 8
+#define STM32_IRQ_EXTI3 9
+#define STM32_IRQ_EXTI4 10
+#define STM32_IRQ_DMA_CHANNEL_1 11
+#define STM32_IRQ_DMA_CHANNEL_2 12
+#define STM32_IRQ_DMA_CHANNEL_3 13
+#define STM32_IRQ_DMA_CHANNEL_4 14
+#define STM32_IRQ_DMA_CHANNEL_5 15
+#define STM32_IRQ_DMA_CHANNEL_6 16
+#define STM32_IRQ_DMA_CHANNEL_7 17
+#define STM32_IRQ_USB_HP 19
+#define STM32_IRQ_USB_LP 20
+
+#define STM32_IRQ_ADC1 18 /* STM32L4 only */
+#define STM32_IRQ_CAN_TX 19 /* STM32F373 only */
+#define STM32_IRQ_USB_LP_CAN_RX 20 /* STM32F373 only */
+#define STM32_IRQ_DAC 21
+#define STM32_IRQ_CAN_RX1 21 /* STM32F373 only */
+
+#define STM32_IRQ_COMP 22
+
+#define STM32_IRQ_CAN_SCE 22 /* STM32F373 only */
+#define STM32_IRQ_EXTI9_5 23
+#define STM32_IRQ_LCD 24 /* STM32L15X only */
+#define STM32_IRQ_TIM15 24 /* STM32F373 only */
+#define STM32_IRQ_TIM9 25 /* STM32L15X only */
+#define STM32_IRQ_TIM16 25 /* STM32F373 only */
+#define STM32_IRQ_TIM10 26 /* STM32L15X only */
+#define STM32_IRQ_TIM17 26 /* STM32F373 only */
+#define STM32_IRQ_TIM11 27 /* STM32L15X only */
+#define STM32_IRQ_TIM18_DAC2 27 /* STM32F373 only */
+#define STM32_IRQ_TIM2 28
+#define STM32_IRQ_TIM3 29
+#define STM32_IRQ_TIM4 30
+#define STM32_IRQ_I2C1_EV 31
+#define STM32_IRQ_I2C1_ER 32
+#define STM32_IRQ_I2C2_EV 33
+#define STM32_IRQ_I2C2_ER 34
+#define STM32_IRQ_SPI1 35
+#define STM32_IRQ_SPI2 36
+#define STM32_IRQ_USART1 37
+#define STM32_IRQ_USART2 38
+#define STM32_IRQ_USART3 39
+#define STM32_IRQ_EXTI15_10 40
+#define STM32_IRQ_RTC_ALARM 41
+#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X */
+#define STM32_IRQ_CEC 42 /* STM32F373 only */
+#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */
+#define STM32_IRQ_TIM12 43 /* STM32F373 only */
+#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */
+#define STM32_IRQ_TIM13 44 /* STM32F373 only */
+#define STM32_IRQ_TIM14 45 /* STM32F373 only */
+#define STM32_IRQ_TIM5 50 /* STM32F373 */
+#define STM32_IRQ_SPI3 51 /* STM32F373 */
+#define STM32_IRQ_USART4 52 /* STM32F446 only */
+#define STM32_IRQ_USART5 53 /* STM32F446 only */
+#define STM32_IRQ_TIM6_DAC 54 /* STM32F373 */
+#define STM32_IRQ_TIM7 55 /* STM32F373 */
+#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F373 */
+#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F373 */
+#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F373 */
+#define STM32_IRQ_DMA2_CHANNEL4 59 /* STM32F373 only */
 /* if MISC_REMAP bits are set */
-#define STM32_IRQ_DMA2_CHANNEL5   60 /* STM32F373 */
-#define STM32_IRQ_SDADC1          61 /* STM32F373 only */
-#define STM32_IRQ_SDADC2          62 /* STM32F373 only */
-#define STM32_IRQ_SDADC3          63 /* STM32F373 only */
-#define STM32_IRQ_DMA2_CHANNEL6   68 /* STM32L4 only */
-#define STM32_IRQ_DMA2_CHANNEL7   69 /* STM32L4 only */
-#define STM32_IRQ_LPUART          70 /* STM32L4 only */
-#define STM32_IRQ_USART9          70 /* STM32L4 only */
-#define STM32_IRQ_USART6          71 /* STM32F446 only */
-#define STM32_IRQ_I2C3_EV         72 /* STM32F446 only */
-#define STM32_IRQ_I2C3_ER         73 /* STM32F446 only */
-#define STM32_IRQ_USB_WAKEUP      76 /* STM32F373 only */
-#define STM32_IRQ_TIM19           78 /* STM32F373 only */
-#define STM32_IRQ_AES             79 /* STM32L4 only */
-#define STM32_IRQ_RNG             80 /* STM32L4 only */
-#define STM32_IRQ_FPU             81 /* STM32F373 only */
-
+#define STM32_IRQ_DMA2_CHANNEL5 60 /* STM32F373 */
+#define STM32_IRQ_SDADC1 61 /* STM32F373 only */
+#define STM32_IRQ_SDADC2 62 /* STM32F373 only */
+#define STM32_IRQ_SDADC3 63 /* STM32F373 only */
+#define STM32_IRQ_DMA2_CHANNEL6 68 /* STM32L4 only */
+#define STM32_IRQ_DMA2_CHANNEL7 69 /* STM32L4 only */
+#define STM32_IRQ_LPUART 70 /* STM32L4 only */
+#define STM32_IRQ_USART9 70 /* STM32L4 only */
+#define STM32_IRQ_USART6 71 /* STM32F446 only */
+#define STM32_IRQ_I2C3_EV 72 /* STM32F446 only */
+#define STM32_IRQ_I2C3_ER 73 /* STM32F446 only */
+#define STM32_IRQ_USB_WAKEUP 76 /* STM32F373 only */
+#define STM32_IRQ_TIM19 78 /* STM32F373 only */
+#define STM32_IRQ_AES 79 /* STM32L4 only */
+#define STM32_IRQ_RNG 80 /* STM32L4 only */
+#define STM32_IRQ_FPU 81 /* STM32F373 only */
 
 /* To simplify code generation, define DMA channel 9..10 */
-#define STM32_IRQ_DMA_CHANNEL_9    STM32_IRQ_DMA2_CHANNEL1
-#define STM32_IRQ_DMA_CHANNEL_10   STM32_IRQ_DMA2_CHANNEL2
-#define STM32_IRQ_DMA_CHANNEL_13   STM32_IRQ_DMA2_CHANNEL6
-#define STM32_IRQ_DMA_CHANNEL_14   STM32_IRQ_DMA2_CHANNEL7
+#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1
+#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2
+#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6
+#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7
 
 /* aliases for easier code sharing */
 #define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV
@@ -123,464 +122,462 @@
  * STM32F4 introduces a concept of DMA stream to allow
  * fine allocation of a stream to a channel.
  */
-#define STM32_IRQ_DMA1_STREAM0    11
-#define STM32_IRQ_DMA1_STREAM1    12
-#define STM32_IRQ_DMA1_STREAM2    13
-#define STM32_IRQ_DMA1_STREAM3    14
-#define STM32_IRQ_DMA1_STREAM4    15
-#define STM32_IRQ_DMA1_STREAM5    16
-#define STM32_IRQ_DMA1_STREAM6    17
-#define STM32_IRQ_DMA1_STREAM7    47
-#define STM32_IRQ_DMA2_STREAM0    56
-#define STM32_IRQ_DMA2_STREAM1    57
-#define STM32_IRQ_DMA2_STREAM2    58
-#define STM32_IRQ_DMA2_STREAM3    59
-#define STM32_IRQ_DMA2_STREAM4    60
-#define STM32_IRQ_DMA2_STREAM5    68
-#define STM32_IRQ_DMA2_STREAM6    69
-#define STM32_IRQ_DMA2_STREAM7    70
-
-#define STM32_IRQ_OTG_HS_WKUP     76
-#define STM32_IRQ_OTG_HS_EP1_IN   75
-#define STM32_IRQ_OTG_HS_EP1_OUT  74
-#define STM32_IRQ_OTG_HS          77
-#define STM32_IRQ_OTG_FS          67
-#define STM32_IRQ_OTG_FS_WKUP     42
+#define STM32_IRQ_DMA1_STREAM0 11
+#define STM32_IRQ_DMA1_STREAM1 12
+#define STM32_IRQ_DMA1_STREAM2 13
+#define STM32_IRQ_DMA1_STREAM3 14
+#define STM32_IRQ_DMA1_STREAM4 15
+#define STM32_IRQ_DMA1_STREAM5 16
+#define STM32_IRQ_DMA1_STREAM6 17
+#define STM32_IRQ_DMA1_STREAM7 47
+#define STM32_IRQ_DMA2_STREAM0 56
+#define STM32_IRQ_DMA2_STREAM1 57
+#define STM32_IRQ_DMA2_STREAM2 58
+#define STM32_IRQ_DMA2_STREAM3 59
+#define STM32_IRQ_DMA2_STREAM4 60
+#define STM32_IRQ_DMA2_STREAM5 68
+#define STM32_IRQ_DMA2_STREAM6 69
+#define STM32_IRQ_DMA2_STREAM7 70
+
+#define STM32_IRQ_OTG_HS_WKUP 76
+#define STM32_IRQ_OTG_HS_EP1_IN 75
+#define STM32_IRQ_OTG_HS_EP1_OUT 74
+#define STM32_IRQ_OTG_HS 77
+#define STM32_IRQ_OTG_FS 67
+#define STM32_IRQ_OTG_FS_WKUP 42
 
 /* Peripheral base addresses */
-#define STM32_ADC1_BASE             0x40012000
-#define STM32_ADC_BASE              0x40012300
-
-#define STM32_CEC_BASE              0x40007800 /* STM32F373 */
-#define STM32_CRC_BASE              0x40023000
-#define STM32_CRS_BASE              0x40006c00 /* STM32F0XX */
-#define STM32_DAC_BASE              0x40007400
-
-
-#define STM32_DBGMCU_BASE           0xE0042000
-
-#define STM32_DMA1_BASE             0x40026000
-#define STM32_DMA2_BASE             0x40026400
-
-#define STM32_EXTI_BASE             0x40013C00
-
-#define STM32_FLASH_REGS_BASE       0x40023c00
-
-#define STM32_GPIOA_BASE            0x40020000
-#define STM32_GPIOB_BASE            0x40020400
-#define STM32_GPIOC_BASE            0x40020800
-#define STM32_GPIOD_BASE            0x40020C00
-#define STM32_GPIOE_BASE            0x40021000
-#define STM32_GPIOF_BASE            0x40021400 /* see RM0402/0390 table 1 */
-#define STM32_GPIOG_BASE            0x40021800
-#define STM32_GPIOH_BASE            0x40021C00
-
-#define STM32_I2C1_BASE             0x40005400
-#define STM32_I2C2_BASE             0x40005800
-#define STM32_I2C3_BASE             0x40005C00
-#define STM32_I2C4_BASE             0x40006000
-
-#define STM32_IWDG_BASE             0x40003000
-#define STM32_LCD_BASE              0x40002400
-
-#define STM32_OPTB_BASE             0x1FFFC000
-#define STM32_OTP_BASE              0x1FFF7800
-
-#define STM32_PMSE_BASE             0x40013400
-#define STM32_PWR_BASE              0x40007000
-
-#define STM32_RCC_BASE              0x40023800
-
-#define STM32_RI_BASE               0x40007C00 /* STM32L1xx only */
-#define STM32_RNG_BASE              0x50060800 /* STM32L4 */
-#define STM32_RTC_BASE              0x40002800
-
-#define STM32_SPI1_BASE             0x40013000
-#define STM32_SPI2_BASE             0x40003800
-#define STM32_SPI3_BASE             0x40003c00 /* STM32F373, STM32L4, STM32F7 */
-
-#define STM32_SYSCFG_BASE           0x40013800
-
-#define STM32_TIM1_BASE             0x40012c00 /* STM32F373 */
-#define STM32_TIM2_BASE             0x40000000
-#define STM32_TIM3_BASE             0x40000400
-#define STM32_TIM4_BASE             0x40000800
-#define STM32_TIM5_BASE             0x40000c00 /* STM32F373 */
-#define STM32_TIM6_BASE             0x40001000
-#define STM32_TIM7_BASE             0x40001400
-#define STM32_TIM9_BASE             0x40014000 /* STM32F41x only */
-#define STM32_TIM10_BASE            0x40014400 /* STM32F41x only */
-#define STM32_TIM11_BASE            0x40014800 /* STM32F41x only */
-#define STM32_TIM12_BASE            0x40001800 /* STM32F373 */
-#define STM32_TIM13_BASE            0x40001c00 /* STM32F373 */
-#define STM32_TIM14_BASE            0x40002000 /* STM32F373 */
-#define STM32_TIM15_BASE            0x40014000
-#define STM32_TIM16_BASE            0x40014400
-#define STM32_TIM17_BASE            0x40014800
-#define STM32_TIM18_BASE            0x40009c00 /* STM32F373 only */
-#define STM32_TIM19_BASE            0x40015c00 /* STM32F373 only */
-
-#define STM32_UNIQUE_ID_BASE        0x1fff7a10
-
-#define STM32_USART1_BASE           0x40011000
-#define STM32_USART2_BASE           0x40004400
-#define STM32_USART3_BASE           0x40004800
-#define STM32_USART4_BASE           0x40004c00
-#define STM32_USART5_BASE           0x40005000
-#define STM32_USART6_BASE           0x40011400
-
-#define STM32_USB_CAN_SRAM_BASE     0x40006000
-#define STM32_USB_FS_BASE           0x40005C00
-
-#define STM32_WWDG_BASE             0x40002C00
-
+#define STM32_ADC1_BASE 0x40012000
+#define STM32_ADC_BASE 0x40012300
+
+#define STM32_CEC_BASE 0x40007800 /* STM32F373 */
+#define STM32_CRC_BASE 0x40023000
+#define STM32_CRS_BASE 0x40006c00 /* STM32F0XX */
+#define STM32_DAC_BASE 0x40007400
+
+#define STM32_DBGMCU_BASE 0xE0042000
+
+#define STM32_DMA1_BASE 0x40026000
+#define STM32_DMA2_BASE 0x40026400
+
+#define STM32_EXTI_BASE 0x40013C00
+
+#define STM32_FLASH_REGS_BASE 0x40023c00
+
+#define STM32_GPIOA_BASE 0x40020000
+#define STM32_GPIOB_BASE 0x40020400
+#define STM32_GPIOC_BASE 0x40020800
+#define STM32_GPIOD_BASE 0x40020C00
+#define STM32_GPIOE_BASE 0x40021000
+#define STM32_GPIOF_BASE 0x40021400 /* see RM0402/0390 table 1 */
+#define STM32_GPIOG_BASE 0x40021800
+#define STM32_GPIOH_BASE 0x40021C00
+
+#define STM32_I2C1_BASE 0x40005400
+#define STM32_I2C2_BASE 0x40005800
+#define STM32_I2C3_BASE 0x40005C00
+#define STM32_I2C4_BASE 0x40006000
+
+#define STM32_IWDG_BASE 0x40003000
+#define STM32_LCD_BASE 0x40002400
+
+#define STM32_OPTB_BASE 0x1FFFC000
+#define STM32_OTP_BASE 0x1FFF7800
+
+#define STM32_PMSE_BASE 0x40013400
+#define STM32_PWR_BASE 0x40007000
+
+#define STM32_RCC_BASE 0x40023800
+
+#define STM32_RI_BASE 0x40007C00 /* STM32L1xx only */
+#define STM32_RNG_BASE 0x50060800 /* STM32L4 */
+#define STM32_RTC_BASE 0x40002800
+
+#define STM32_SPI1_BASE 0x40013000
+#define STM32_SPI2_BASE 0x40003800
+#define STM32_SPI3_BASE 0x40003c00 /* STM32F373, STM32L4, STM32F7 */
+
+#define STM32_SYSCFG_BASE 0x40013800
+
+#define STM32_TIM1_BASE 0x40012c00 /* STM32F373 */
+#define STM32_TIM2_BASE 0x40000000
+#define STM32_TIM3_BASE 0x40000400
+#define STM32_TIM4_BASE 0x40000800
+#define STM32_TIM5_BASE 0x40000c00 /* STM32F373 */
+#define STM32_TIM6_BASE 0x40001000
+#define STM32_TIM7_BASE 0x40001400
+#define STM32_TIM9_BASE 0x40014000 /* STM32F41x only */
+#define STM32_TIM10_BASE 0x40014400 /* STM32F41x only */
+#define STM32_TIM11_BASE 0x40014800 /* STM32F41x only */
+#define STM32_TIM12_BASE 0x40001800 /* STM32F373 */
+#define STM32_TIM13_BASE 0x40001c00 /* STM32F373 */
+#define STM32_TIM14_BASE 0x40002000 /* STM32F373 */
+#define STM32_TIM15_BASE 0x40014000
+#define STM32_TIM16_BASE 0x40014400
+#define STM32_TIM17_BASE 0x40014800
+#define STM32_TIM18_BASE 0x40009c00 /* STM32F373 only */
+#define STM32_TIM19_BASE 0x40015c00 /* STM32F373 only */
+
+#define STM32_UNIQUE_ID_BASE 0x1fff7a10
+
+#define STM32_USART1_BASE 0x40011000
+#define STM32_USART2_BASE 0x40004400
+#define STM32_USART3_BASE 0x40004800
+#define STM32_USART4_BASE 0x40004c00
+#define STM32_USART5_BASE 0x40005000
+#define STM32_USART6_BASE 0x40011400
+
+#define STM32_USB_CAN_SRAM_BASE 0x40006000
+#define STM32_USB_FS_BASE 0x40005C00
+
+#define STM32_WWDG_BASE 0x40002C00
 
 #ifndef __ASSEMBLER__
 
 /* Register definitions */
 
 /* --- USART --- */
-#define STM32_USART_CR1(base)      STM32_USART_REG(base, 0x00)
-#define STM32_USART_CR1_UE		BIT(0)
-#define STM32_USART_CR1_UESM            BIT(1)
-#define STM32_USART_CR1_RE		BIT(2)
-#define STM32_USART_CR1_TE		BIT(3)
-#define STM32_USART_CR1_RXNEIE		BIT(5)
-#define STM32_USART_CR1_TCIE		BIT(6)
-#define STM32_USART_CR1_TXEIE		BIT(7)
-#define STM32_USART_CR1_PS		BIT(9)
-#define STM32_USART_CR1_PCE		BIT(10)
-#define STM32_USART_CR1_M		BIT(12)
-#define STM32_USART_CR1_OVER8		BIT(15)
-#define STM32_USART_CR2(base)      STM32_USART_REG(base, 0x04)
-#define STM32_USART_CR2_SWAP		BIT(15)
-#define STM32_USART_CR3(base)      STM32_USART_REG(base, 0x08)
-#define STM32_USART_CR3_EIE		BIT(0)
-#define STM32_USART_CR3_DMAR		BIT(6)
-#define STM32_USART_CR3_DMAT		BIT(7)
-#define STM32_USART_CR3_ONEBIT		BIT(11)
-#define STM32_USART_CR3_OVRDIS		BIT(12)
-#define STM32_USART_CR3_WUS_START_BIT	(2 << 20)
-#define STM32_USART_CR3_WUFIE		BIT(22)
-#define STM32_USART_BRR(base)      STM32_USART_REG(base, 0x0C)
-#define STM32_USART_GTPR(base)     STM32_USART_REG(base, 0x10)
-#define STM32_USART_RTOR(base)     STM32_USART_REG(base, 0x14)
-#define STM32_USART_RQR(base)      STM32_USART_REG(base, 0x18)
-#define STM32_USART_ISR(base)      STM32_USART_REG(base, 0x1C)
-#define STM32_USART_ICR(base)      STM32_USART_REG(base, 0x20)
-#define STM32_USART_ICR_ORECF		BIT(3)
-#define STM32_USART_ICR_TCCF		BIT(6)
-#define STM32_USART_RDR(base)      STM32_USART_REG(base, 0x24)
-#define STM32_USART_TDR(base)      STM32_USART_REG(base, 0x28)
-#define STM32_USART_PRESC(base)    STM32_USART_REG(base, 0x2C)
+#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00)
+#define STM32_USART_CR1_UE BIT(0)
+#define STM32_USART_CR1_UESM BIT(1)
+#define STM32_USART_CR1_RE BIT(2)
+#define STM32_USART_CR1_TE BIT(3)
+#define STM32_USART_CR1_RXNEIE BIT(5)
+#define STM32_USART_CR1_TCIE BIT(6)
+#define STM32_USART_CR1_TXEIE BIT(7)
+#define STM32_USART_CR1_PS BIT(9)
+#define STM32_USART_CR1_PCE BIT(10)
+#define STM32_USART_CR1_M BIT(12)
+#define STM32_USART_CR1_OVER8 BIT(15)
+#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04)
+#define STM32_USART_CR2_SWAP BIT(15)
+#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08)
+#define STM32_USART_CR3_EIE BIT(0)
+#define STM32_USART_CR3_DMAR BIT(6)
+#define STM32_USART_CR3_DMAT BIT(7)
+#define STM32_USART_CR3_ONEBIT BIT(11)
+#define STM32_USART_CR3_OVRDIS BIT(12)
+#define STM32_USART_CR3_WUS_START_BIT (2 << 20)
+#define STM32_USART_CR3_WUFIE BIT(22)
+#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C)
+#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10)
+#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14)
+#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18)
+#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C)
+#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20)
+#define STM32_USART_ICR_ORECF BIT(3)
+#define STM32_USART_ICR_TCCF BIT(6)
+#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24)
+#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28)
+#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C)
 /* register alias */
-#define STM32_USART_SR(base)       STM32_USART_ISR(base)
-#define STM32_USART_SR_ORE		BIT(3)
-#define STM32_USART_SR_RXNE		BIT(5)
-#define STM32_USART_SR_TC		BIT(6)
-#define STM32_USART_SR_TXE		BIT(7)
+#define STM32_USART_SR(base) STM32_USART_ISR(base)
+#define STM32_USART_SR_ORE BIT(3)
+#define STM32_USART_SR_RXNE BIT(5)
+#define STM32_USART_SR_TC BIT(6)
+#define STM32_USART_SR_TXE BIT(7)
 
 /* --- GPIO --- */
-#define STM32_GPIO_MODER(b)     REG32((b) + 0x00)
-#define STM32_GPIO_OTYPER(b)    REG16((b) + 0x04)
-#define STM32_GPIO_OSPEEDR(b)   REG32((b) + 0x08)
-#define STM32_GPIO_PUPDR(b)     REG32((b) + 0x0C)
-#define STM32_GPIO_IDR(b)       REG16((b) + 0x10)
-#define STM32_GPIO_ODR(b)       REG16((b) + 0x14)
-#define STM32_GPIO_BSRR(b)      REG32((b) + 0x18)
-#define STM32_GPIO_LCKR(b)      REG32((b) + 0x1C)
-#define STM32_GPIO_AFRL(b)      REG32((b) + 0x20)
-#define STM32_GPIO_AFRH(b)      REG32((b) + 0x24)
-
-#define GPIO_ALT_SYS                 0x0
-#define GPIO_ALT_TIM2                0x1
-#define GPIO_ALT_TIM3_4              0x2
-#define GPIO_ALT_TIM9_11             0x3
-#define GPIO_ALT_I2C                 0x4
-#define GPIO_ALT_SPI                 0x5
-#define GPIO_ALT_SPI3                0x6
-#define GPIO_ALT_USART               0x7
-#define GPIO_ALT_I2C_23              0x9
-#define GPIO_ALT_USB                 0xA
-#define GPIO_ALT_LCD                 0xB
-#define GPIO_ALT_RI                  0xE
-#define GPIO_ALT_EVENTOUT            0xF
+#define STM32_GPIO_MODER(b) REG32((b) + 0x00)
+#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04)
+#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08)
+#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C)
+#define STM32_GPIO_IDR(b) REG16((b) + 0x10)
+#define STM32_GPIO_ODR(b) REG16((b) + 0x14)
+#define STM32_GPIO_BSRR(b) REG32((b) + 0x18)
+#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C)
+#define STM32_GPIO_AFRL(b) REG32((b) + 0x20)
+#define STM32_GPIO_AFRH(b) REG32((b) + 0x24)
+
+#define GPIO_ALT_SYS 0x0
+#define GPIO_ALT_TIM2 0x1
+#define GPIO_ALT_TIM3_4 0x2
+#define GPIO_ALT_TIM9_11 0x3
+#define GPIO_ALT_I2C 0x4
+#define GPIO_ALT_SPI 0x5
+#define GPIO_ALT_SPI3 0x6
+#define GPIO_ALT_USART 0x7
+#define GPIO_ALT_I2C_23 0x9
+#define GPIO_ALT_USB 0xA
+#define GPIO_ALT_LCD 0xB
+#define GPIO_ALT_RI 0xE
+#define GPIO_ALT_EVENTOUT 0xF
 
 /* --- I2C --- */
-#define STM32_I2C_CR1(n)            REG16(stm32_i2c_reg(n, 0x00))
-#define STM32_I2C_CR1_PE	BIT(0)
-#define STM32_I2C_CR1_START	BIT(8)
-#define STM32_I2C_CR1_STOP	BIT(9)
-#define STM32_I2C_CR1_ACK	BIT(10)
-#define STM32_I2C_CR1_POS	BIT(11)
-#define STM32_I2C_CR1_SWRST	BIT(15)
-#define STM32_I2C_CR2(n)            REG16(stm32_i2c_reg(n, 0x04))
-#define STM32_I2C_CR2_ITERREN	BIT(8)
-#define STM32_I2C_CR2_ITEVTEN	BIT(9)
-#define STM32_I2C_CR2_ITBUFEN	BIT(10)
-#define STM32_I2C_CR2_DMAEN	BIT(11)
-#define STM32_I2C_CR2_LAST	BIT(12)
-#define STM32_I2C_OAR1(n)           REG16(stm32_i2c_reg(n, 0x08))
-#define STM32_I2C_OAR1_B14	BIT(14)
-#define STM32_I2C_OAR2(n)           REG16(stm32_i2c_reg(n, 0x0C))
-#define STM32_I2C_OAR2_ENDUAL	BIT(0)
-#define STM32_I2C_DR(n)             REG16(stm32_i2c_reg(n, 0x10))
-#define STM32_I2C_SR1(n)            REG16(stm32_i2c_reg(n, 0x14))
-#define STM32_I2C_SR1_SB	BIT(0)
-#define STM32_I2C_SR1_ADDR	BIT(1)
-#define STM32_I2C_SR1_BTF	BIT(2)
-#define STM32_I2C_SR1_STOPF	BIT(4)
-#define STM32_I2C_SR1_RXNE	BIT(6)
-#define STM32_I2C_SR1_TXE	BIT(7)
-#define STM32_I2C_SR1_BERR	BIT(8)
-#define STM32_I2C_SR1_ARLO	BIT(9)
-#define STM32_I2C_SR1_AF	BIT(10)
-
-#define STM32_I2C_SR2(n)            REG16(stm32_i2c_reg(n, 0x18))
-#define STM32_I2C_SR2_BUSY	BIT(1)
-#define STM32_I2C_SR2_TRA	BIT(2)
-#define STM32_I2C_SR2_DUALF	BIT(7)
-
-#define STM32_I2C_CCR(n)            REG16(stm32_i2c_reg(n, 0x1C))
-#define STM32_I2C_CCR_DUTY	BIT(14)
-#define STM32_I2C_CCR_FM	BIT(15)
-#define STM32_I2C_TRISE(n)          REG16(stm32_i2c_reg(n, 0x20))
-
-#define STM32_FMPI2C_CR1(n)        REG32(stm32_i2c_reg(n, 0x00))
-#define  FMPI2C_CR1_PE             BIT(0)
-#define  FMPI2C_CR1_TXDMAEN        BIT(14)
-#define  FMPI2C_CR1_RXDMAEN        BIT(15)
-#define STM32_FMPI2C_CR2(n)        REG32(stm32_i2c_reg(n, 0x04))
-#define  FMPI2C_CR2_RD_WRN         BIT(10)
-#define  FMPI2C_READ               1
-#define  FMPI2C_WRITE              0
-#define  FMPI2C_CR2_START          BIT(13)
-#define  FMPI2C_CR2_STOP           BIT(14)
-#define  FMPI2C_CR2_NACK           BIT(15)
-#define  FMPI2C_CR2_RELOAD         BIT(24)
-#define  FMPI2C_CR2_AUTOEND        BIT(25)
-#define  FMPI2C_CR2_SADD(addr)     ((addr) & 0x3ff)
-#define  FMPI2C_CR2_SADD_MASK      FMPI2C_CR2_SADD(0x3ff)
-#define  FMPI2C_CR2_SIZE(size)     (((size) & 0xff) << 16)
-#define  FMPI2C_CR2_SIZE_MASK      FMPI2C_CR2_SIZE(0xf)
-#define STM32_FMPI2C_OAR1(n)       REG32(stm32_i2c_reg(n, 0x08))
-#define STM32_FMPI2C_OAR2(n)       REG32(stm32_i2c_reg(n, 0x0C))
-#define STM32_FMPI2C_TIMINGR(n)    REG32(stm32_i2c_reg(n, 0x10))
-#define  TIMINGR_THE_RIGHT_VALUE   0xC0000E12
-#define  FMPI2C_TIMINGR_PRESC(val) (((val) & 0xf) << 28)
-#define  FMPI2C_TIMINGR_SCLDEL(val) (((val) & 0xf) << 20)
-#define  FMPI2C_TIMINGR_SDADEL(val) (((val) & 0xf) << 16)
-#define  FMPI2C_TIMINGR_SCLH(val)  (((val) & 0xff) << 8)
-#define  FMPI2C_TIMINGR_SCLL(val)  (((val) & 0xff) << 0)
-#define STM32_FMPI2C_TIMEOUTR(n)   REG32(stm32_i2c_reg(n, 0x14))
-
-#define STM32_FMPI2C_ISR(n)        REG32(stm32_i2c_reg(n, 0x18))
-#define  FMPI2C_ISR_TXE            BIT(0)
-#define  FMPI2C_ISR_TXIS           BIT(1)
-#define  FMPI2C_ISR_RXNE           BIT(2)
-#define  FMPI2C_ISR_ADDR           BIT(3)
-#define  FMPI2C_ISR_NACKF          BIT(4)
-#define  FMPI2C_ISR_STOPF          BIT(5)
-#define  FMPI2C_ISR_BERR           BIT(8)
-#define  FMPI2C_ISR_ARLO           BIT(9)
-#define  FMPI2C_ISR_BUSY           BIT(15)
-#define STM32_FMPI2C_ICR(n)        REG32(stm32_i2c_reg(n, 0x1C))
-
-#define STM32_FMPI2C_PECR(n)       REG32(stm32_i2c_reg(n, 0x20))
-#define STM32_FMPI2C_RXDR(n)       REG32(stm32_i2c_reg(n, 0x24))
-#define STM32_FMPI2C_TXDR(n)       REG32(stm32_i2c_reg(n, 0x28))
+#define STM32_I2C_CR1(n) REG16(stm32_i2c_reg(n, 0x00))
+#define STM32_I2C_CR1_PE BIT(0)
+#define STM32_I2C_CR1_START BIT(8)
+#define STM32_I2C_CR1_STOP BIT(9)
+#define STM32_I2C_CR1_ACK BIT(10)
+#define STM32_I2C_CR1_POS BIT(11)
+#define STM32_I2C_CR1_SWRST BIT(15)
+#define STM32_I2C_CR2(n) REG16(stm32_i2c_reg(n, 0x04))
+#define STM32_I2C_CR2_ITERREN BIT(8)
+#define STM32_I2C_CR2_ITEVTEN BIT(9)
+#define STM32_I2C_CR2_ITBUFEN BIT(10)
+#define STM32_I2C_CR2_DMAEN BIT(11)
+#define STM32_I2C_CR2_LAST BIT(12)
+#define STM32_I2C_OAR1(n) REG16(stm32_i2c_reg(n, 0x08))
+#define STM32_I2C_OAR1_B14 BIT(14)
+#define STM32_I2C_OAR2(n) REG16(stm32_i2c_reg(n, 0x0C))
+#define STM32_I2C_OAR2_ENDUAL BIT(0)
+#define STM32_I2C_DR(n) REG16(stm32_i2c_reg(n, 0x10))
+#define STM32_I2C_SR1(n) REG16(stm32_i2c_reg(n, 0x14))
+#define STM32_I2C_SR1_SB BIT(0)
+#define STM32_I2C_SR1_ADDR BIT(1)
+#define STM32_I2C_SR1_BTF BIT(2)
+#define STM32_I2C_SR1_STOPF BIT(4)
+#define STM32_I2C_SR1_RXNE BIT(6)
+#define STM32_I2C_SR1_TXE BIT(7)
+#define STM32_I2C_SR1_BERR BIT(8)
+#define STM32_I2C_SR1_ARLO BIT(9)
+#define STM32_I2C_SR1_AF BIT(10)
+
+#define STM32_I2C_SR2(n) REG16(stm32_i2c_reg(n, 0x18))
+#define STM32_I2C_SR2_BUSY BIT(1)
+#define STM32_I2C_SR2_TRA BIT(2)
+#define STM32_I2C_SR2_DUALF BIT(7)
+
+#define STM32_I2C_CCR(n) REG16(stm32_i2c_reg(n, 0x1C))
+#define STM32_I2C_CCR_DUTY BIT(14)
+#define STM32_I2C_CCR_FM BIT(15)
+#define STM32_I2C_TRISE(n) REG16(stm32_i2c_reg(n, 0x20))
+
+#define STM32_FMPI2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00))
+#define FMPI2C_CR1_PE BIT(0)
+#define FMPI2C_CR1_TXDMAEN BIT(14)
+#define FMPI2C_CR1_RXDMAEN BIT(15)
+#define STM32_FMPI2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04))
+#define FMPI2C_CR2_RD_WRN BIT(10)
+#define FMPI2C_READ 1
+#define FMPI2C_WRITE 0
+#define FMPI2C_CR2_START BIT(13)
+#define FMPI2C_CR2_STOP BIT(14)
+#define FMPI2C_CR2_NACK BIT(15)
+#define FMPI2C_CR2_RELOAD BIT(24)
+#define FMPI2C_CR2_AUTOEND BIT(25)
+#define FMPI2C_CR2_SADD(addr) ((addr)&0x3ff)
+#define FMPI2C_CR2_SADD_MASK FMPI2C_CR2_SADD(0x3ff)
+#define FMPI2C_CR2_SIZE(size) (((size)&0xff) << 16)
+#define FMPI2C_CR2_SIZE_MASK FMPI2C_CR2_SIZE(0xf)
+#define STM32_FMPI2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08))
+#define STM32_FMPI2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C))
+#define STM32_FMPI2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10))
+#define TIMINGR_THE_RIGHT_VALUE 0xC0000E12
+#define FMPI2C_TIMINGR_PRESC(val) (((val)&0xf) << 28)
+#define FMPI2C_TIMINGR_SCLDEL(val) (((val)&0xf) << 20)
+#define FMPI2C_TIMINGR_SDADEL(val) (((val)&0xf) << 16)
+#define FMPI2C_TIMINGR_SCLH(val) (((val)&0xff) << 8)
+#define FMPI2C_TIMINGR_SCLL(val) (((val)&0xff) << 0)
+#define STM32_FMPI2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14))
+
+#define STM32_FMPI2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18))
+#define FMPI2C_ISR_TXE BIT(0)
+#define FMPI2C_ISR_TXIS BIT(1)
+#define FMPI2C_ISR_RXNE BIT(2)
+#define FMPI2C_ISR_ADDR BIT(3)
+#define FMPI2C_ISR_NACKF BIT(4)
+#define FMPI2C_ISR_STOPF BIT(5)
+#define FMPI2C_ISR_BERR BIT(8)
+#define FMPI2C_ISR_ARLO BIT(9)
+#define FMPI2C_ISR_BUSY BIT(15)
+#define STM32_FMPI2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C))
+
+#define STM32_FMPI2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20))
+#define STM32_FMPI2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24))
+#define STM32_FMPI2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28))
 
 /* --- Power / Reset / Clocks --- */
-#define STM32_PWR_CSR               REG32(STM32_PWR_BASE + 0x04)
-
+#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04)
 
-#define STM32_RCC_CR                    REG32(STM32_RCC_BASE + 0x00)
-#define STM32_RCC_CR_HSION		BIT(0)
-#define STM32_RCC_CR_HSIRDY		BIT(1)
-#define STM32_RCC_CR_HSEON		BIT(16)
-#define STM32_RCC_CR_HSERDY		BIT(17)
-#define STM32_RCC_CR_PLLON		BIT(24)
-#define STM32_RCC_CR_PLLRDY		BIT(25)
+#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00)
+#define STM32_RCC_CR_HSION BIT(0)
+#define STM32_RCC_CR_HSIRDY BIT(1)
+#define STM32_RCC_CR_HSEON BIT(16)
+#define STM32_RCC_CR_HSERDY BIT(17)
+#define STM32_RCC_CR_PLLON BIT(24)
+#define STM32_RCC_CR_PLLRDY BIT(25)
 
 #ifdef CHIP_VARIANT_STM32F76X
 /* Required or recommended clocks for stm32f767/769 */
 #define STM32F4_PLL_REQ 2000000
 #define STM32F4_RTC_REQ 1000000
 #define STM32F4_IO_CLOCK 45000000
-#define STM32F4_USB_REQ 45000000 /* not compatible with USB, will use PLLSAI */
+#define STM32F4_USB_REQ                                      \
+	45000000 /* not compatible with USB, will use PLLSAI \
+		  */
 #define STM32F4_VCO_CLOCK 360000000
 #define STM32F4_HSI_CLOCK 16000000
 #define STM32F4_LSI_CLOCK 32000
 #define STM32F4_TIMER_CLOCK (STM32F4_IO_CLOCK * 2)
-#define STM32F4_PLLP_DIV 2   /* sys = VCO/2  = 180 Mhz */
-#define STM32F4_AHB_PRE 0x0  /* AHB = sysclk = 180 Mhz */
+#define STM32F4_PLLP_DIV 2 /* sys = VCO/2  = 180 Mhz */
+#define STM32F4_AHB_PRE 0x0 /* AHB = sysclk = 180 Mhz */
 #define STM32F4_APB1_PRE 0x5 /* APB1 = AHB /4 = 45 Mhz */
 #define STM32F4_APB2_PRE 0x5 /* APB2 = AHB /4 = 45 Mhz */
-#define STM32_FLASH_ACR_LATENCY     (5 << 0)
+#define STM32_FLASH_ACR_LATENCY (5 << 0)
 #else
 #error "No valid clocks defined"
 #endif
 
-#define STM32_RCC_PLLCFGR               REG32(STM32_RCC_BASE + 0x04)
+#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x04)
 /* PLL Division factor */
-#define  PLLCFGR_PLLM_OFF		0
-#define  PLLCFGR_PLLM(val)		(((val) & 0x1f) << PLLCFGR_PLLM_OFF)
+#define PLLCFGR_PLLM_OFF 0
+#define PLLCFGR_PLLM(val) (((val)&0x1f) << PLLCFGR_PLLM_OFF)
 /* PLL Multiplication factor */
-#define  PLLCFGR_PLLN_OFF		6
-#define  PLLCFGR_PLLN(val)		(((val) & 0x1ff) << PLLCFGR_PLLN_OFF)
+#define PLLCFGR_PLLN_OFF 6
+#define PLLCFGR_PLLN(val) (((val)&0x1ff) << PLLCFGR_PLLN_OFF)
 /* Main CPU Clock */
-#define  PLLCFGR_PLLP_OFF		16
-#define  PLLCFGR_PLLP(val)		(((val) & 0x3) << PLLCFGR_PLLP_OFF)
+#define PLLCFGR_PLLP_OFF 16
+#define PLLCFGR_PLLP(val) (((val)&0x3) << PLLCFGR_PLLP_OFF)
 
-#define  PLLCFGR_PLLSRC_HSI		(0 << 22)
-#define  PLLCFGR_PLLSRC_HSE		BIT(22)
+#define PLLCFGR_PLLSRC_HSI (0 << 22)
+#define PLLCFGR_PLLSRC_HSE BIT(22)
 /* USB OTG FS: Must equal 48MHz */
-#define  PLLCFGR_PLLQ_OFF		24
-#define  PLLCFGR_PLLQ(val)		(((val) & 0xf) << PLLCFGR_PLLQ_OFF)
+#define PLLCFGR_PLLQ_OFF 24
+#define PLLCFGR_PLLQ(val) (((val)&0xf) << PLLCFGR_PLLQ_OFF)
 /* SYSTEM */
-#define  PLLCFGR_PLLR_OFF		28
-#define  PLLCFGR_PLLR(val)		(((val) & 0x7) << PLLCFGR_PLLR_OFF)
-
-#define STM32_RCC_CFGR                  REG32(STM32_RCC_BASE + 0x08)
-#define STM32_RCC_CFGR_SW_HSI		(0 << 0)
-#define STM32_RCC_CFGR_SW_HSE		(1 << 0)
-#define STM32_RCC_CFGR_SW_PLL		(2 << 0)
-#define STM32_RCC_CFGR_SW_PLL_R		(3 << 0)
-#define STM32_RCC_CFGR_SW_MASK		(3 << 0)
-#define STM32_RCC_CFGR_SWS_HSI		(0 << 2)
-#define STM32_RCC_CFGR_SWS_HSE		(1 << 2)
-#define STM32_RCC_CFGR_SWS_PLL		(2 << 2)
-#define STM32_RCC_CFGR_SWS_PLL_R	(3 << 2)
-#define STM32_RCC_CFGR_SWS_MASK		(3 << 2)
+#define PLLCFGR_PLLR_OFF 28
+#define PLLCFGR_PLLR(val) (((val)&0x7) << PLLCFGR_PLLR_OFF)
+
+#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08)
+#define STM32_RCC_CFGR_SW_HSI (0 << 0)
+#define STM32_RCC_CFGR_SW_HSE (1 << 0)
+#define STM32_RCC_CFGR_SW_PLL (2 << 0)
+#define STM32_RCC_CFGR_SW_PLL_R (3 << 0)
+#define STM32_RCC_CFGR_SW_MASK (3 << 0)
+#define STM32_RCC_CFGR_SWS_HSI (0 << 2)
+#define STM32_RCC_CFGR_SWS_HSE (1 << 2)
+#define STM32_RCC_CFGR_SWS_PLL (2 << 2)
+#define STM32_RCC_CFGR_SWS_PLL_R (3 << 2)
+#define STM32_RCC_CFGR_SWS_MASK (3 << 2)
 /* AHB Prescalar: nonlinear values, look up in RM0390 */
-#define  CFGR_HPRE_OFF			4
-#define  CFGR_HPRE(val)			(((val) & 0xf) << CFGR_HPRE_OFF)
+#define CFGR_HPRE_OFF 4
+#define CFGR_HPRE(val) (((val)&0xf) << CFGR_HPRE_OFF)
 /* APB1 Low Speed Prescalar < 45MHz */
-#define  CFGR_PPRE1_OFF			10
-#define  CFGR_PPRE1(val)		(((val) & 0x7) << CFGR_PPRE1_OFF)
+#define CFGR_PPRE1_OFF 10
+#define CFGR_PPRE1(val) (((val)&0x7) << CFGR_PPRE1_OFF)
 /* APB2 High Speed Prescalar < 90MHz */
-#define  CFGR_PPRE2_OFF			13
-#define  CFGR_PPRE2(val)		(((val) & 0x7) << CFGR_PPRE2_OFF)
+#define CFGR_PPRE2_OFF 13
+#define CFGR_PPRE2(val) (((val)&0x7) << CFGR_PPRE2_OFF)
 /* RTC CLock: Must equal 1MHz */
-#define  CFGR_RTCPRE_OFF		16
-#define  CFGR_RTCPRE(val)		(((val) & 0x1f) << CFGR_RTCPRE_OFF)
+#define CFGR_RTCPRE_OFF 16
+#define CFGR_RTCPRE(val) (((val)&0x1f) << CFGR_RTCPRE_OFF)
 
-#define STM32_RCC_CIR                   REG32(STM32_RCC_BASE + 0x0C)
-#define STM32_RCC_AHB1RSTR              REG32(STM32_RCC_BASE + 0x10)
-#define  RCC_AHB1RSTR_OTGHSRST		BIT(29)
+#define STM32_RCC_CIR REG32(STM32_RCC_BASE + 0x0C)
+#define STM32_RCC_AHB1RSTR REG32(STM32_RCC_BASE + 0x10)
+#define RCC_AHB1RSTR_OTGHSRST BIT(29)
 
-#define STM32_RCC_AHB2RSTR              REG32(STM32_RCC_BASE + 0x14)
-#define STM32_RCC_AHB3RSTR              REG32(STM32_RCC_BASE + 0x18)
+#define STM32_RCC_AHB2RSTR REG32(STM32_RCC_BASE + 0x14)
+#define STM32_RCC_AHB3RSTR REG32(STM32_RCC_BASE + 0x18)
 
-#define STM32_RCC_APB1RSTR              REG32(STM32_RCC_BASE + 0x20)
-#define STM32_RCC_APB2RSTR              REG32(STM32_RCC_BASE + 0x24)
+#define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x20)
+#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x24)
 
-#define STM32_RCC_AHB1ENR               REG32(STM32_RCC_BASE + 0x30)
-#define STM32_RCC_AHB1ENR_GPIOMASK	(0xff << 0)
-#define STM32_RCC_AHB1ENR_BKPSRAMEN	BIT(18)
-#define STM32_RCC_AHB1ENR_DMA1EN	BIT(21)
-#define STM32_RCC_AHB1ENR_DMA2EN	BIT(22)
+#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x30)
+#define STM32_RCC_AHB1ENR_GPIOMASK (0xff << 0)
+#define STM32_RCC_AHB1ENR_BKPSRAMEN BIT(18)
+#define STM32_RCC_AHB1ENR_DMA1EN BIT(21)
+#define STM32_RCC_AHB1ENR_DMA2EN BIT(22)
 /* TODO(nsanders): normalize naming.*/
-#define STM32_RCC_HB1_DMA1		BIT(21)
-#define STM32_RCC_HB1_DMA2		BIT(22)
-#define STM32_RCC_AHB1ENR_OTGHSEN	BIT(29)
-#define STM32_RCC_AHB1ENR_OTGHSULPIEN	BIT(30)
-
-#define STM32_RCC_AHB2ENR               REG32(STM32_RCC_BASE + 0x34)
-#define STM32_RCC_AHB2ENR_RNGEN		BIT(6)
-#define STM32_RCC_AHB2ENR_OTGFSEN	BIT(7)
-#define STM32_RCC_AHB3ENR               REG32(STM32_RCC_BASE + 0x38)
-
-#define STM32_RCC_APB1ENR               REG32(STM32_RCC_BASE + 0x40)
-#define STM32_RCC_PWREN                 BIT(28)
-#define STM32_RCC_I2C1EN                BIT(21)
-#define STM32_RCC_I2C2EN                BIT(22)
-#define STM32_RCC_I2C3EN                BIT(23)
-#define STM32_RCC_FMPI2C4EN             BIT(24)
-
-#define STM32_RCC_APB2ENR               REG32(STM32_RCC_BASE + 0x44)
-#define STM32_RCC_APB2ENR_ADC1EN        BIT(8) /* STM32F4 */
-
-#define STM32_RCC_PB2_USART6            BIT(5)
-#define STM32_RCC_SYSCFGEN		BIT(14)
-
-#define STM32_RCC_AHB1LPENR             REG32(STM32_RCC_BASE + 0x50)
-#define STM32_RCC_AHB2LPENR             REG32(STM32_RCC_BASE + 0x54)
-#define STM32_RCC_AHB3LPENR             REG32(STM32_RCC_BASE + 0x58)
-#define STM32_RCC_APB1LPENR             REG32(STM32_RCC_BASE + 0x60)
-#define STM32_RCC_APB2LPENR             REG32(STM32_RCC_BASE + 0x64)
-
-#define STM32_RCC_BDCR                  REG32(STM32_RCC_BASE + 0x70)
-#define STM32_RCC_CSR                   REG32(STM32_RCC_BASE + 0x74)
-#define STM32_RCC_CSR_LSION		BIT(0)
-#define STM32_RCC_CSR_LSIRDY		BIT(1)
-
-#define STM32_RCC_PB2_TIM9		BIT(16)
-#define STM32_RCC_PB2_TIM10		BIT(17)
-#define STM32_RCC_PB2_TIM11		BIT(18)
-
-#define STM32_RCC_DCKCFGR2              REG32(STM32_RCC_BASE + 0x94)
-#define  DCKCFGR2_FMPI2C1SEL(val)       (((val) & 0x3) << 22)
-#define  DCKCFGR2_FMPI2C1SEL_MASK       (0x3 << 22)
-#define  FMPI2C1SEL_APB                 0x0
-
-#define STM32_SYSCFG_MEMRMP             REG32(STM32_SYSCFG_BASE + 0x00)
-#define STM32_SYSCFG_PMC                REG32(STM32_SYSCFG_BASE + 0x04)
-#define STM32_SYSCFG_EXTICR(n)          REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
-#define STM32_SYSCFG_CMPCR              REG32(STM32_SYSCFG_BASE + 0x20)
-#define STM32_SYSCFG_CFGR               REG32(STM32_SYSCFG_BASE + 0x2C)
-
+#define STM32_RCC_HB1_DMA1 BIT(21)
+#define STM32_RCC_HB1_DMA2 BIT(22)
+#define STM32_RCC_AHB1ENR_OTGHSEN BIT(29)
+#define STM32_RCC_AHB1ENR_OTGHSULPIEN BIT(30)
+
+#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x34)
+#define STM32_RCC_AHB2ENR_RNGEN BIT(6)
+#define STM32_RCC_AHB2ENR_OTGFSEN BIT(7)
+#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x38)
+
+#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x40)
+#define STM32_RCC_PWREN BIT(28)
+#define STM32_RCC_I2C1EN BIT(21)
+#define STM32_RCC_I2C2EN BIT(22)
+#define STM32_RCC_I2C3EN BIT(23)
+#define STM32_RCC_FMPI2C4EN BIT(24)
+
+#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x44)
+#define STM32_RCC_APB2ENR_ADC1EN BIT(8) /* STM32F4 */
+
+#define STM32_RCC_PB2_USART6 BIT(5)
+#define STM32_RCC_SYSCFGEN BIT(14)
+
+#define STM32_RCC_AHB1LPENR REG32(STM32_RCC_BASE + 0x50)
+#define STM32_RCC_AHB2LPENR REG32(STM32_RCC_BASE + 0x54)
+#define STM32_RCC_AHB3LPENR REG32(STM32_RCC_BASE + 0x58)
+#define STM32_RCC_APB1LPENR REG32(STM32_RCC_BASE + 0x60)
+#define STM32_RCC_APB2LPENR REG32(STM32_RCC_BASE + 0x64)
+
+#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x70)
+#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x74)
+#define STM32_RCC_CSR_LSION BIT(0)
+#define STM32_RCC_CSR_LSIRDY BIT(1)
+
+#define STM32_RCC_PB2_TIM9 BIT(16)
+#define STM32_RCC_PB2_TIM10 BIT(17)
+#define STM32_RCC_PB2_TIM11 BIT(18)
+
+#define STM32_RCC_DCKCFGR2 REG32(STM32_RCC_BASE + 0x94)
+#define DCKCFGR2_FMPI2C1SEL(val) (((val)&0x3) << 22)
+#define DCKCFGR2_FMPI2C1SEL_MASK (0x3 << 22)
+#define FMPI2C1SEL_APB 0x0
+
+#define STM32_SYSCFG_MEMRMP REG32(STM32_SYSCFG_BASE + 0x00)
+#define STM32_SYSCFG_PMC REG32(STM32_SYSCFG_BASE + 0x04)
+#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
+#define STM32_SYSCFG_CMPCR REG32(STM32_SYSCFG_BASE + 0x20)
+#define STM32_SYSCFG_CFGR REG32(STM32_SYSCFG_BASE + 0x2C)
 
 /* Peripheral bits for RCC_APB/AHB and DBGMCU regs */
-#define STM32_RCC_PB2_USART1		BIT(4)
+#define STM32_RCC_PB2_USART1 BIT(4)
 
 /* Reset causes definitions */
 /* Reset causes in RCC CSR register */
 #define STM32_RCC_RESET_CAUSE STM32_RCC_CSR
-#define  RESET_CAUSE_WDG                0x60000000
-#define  RESET_CAUSE_SFT                0x10000000
-#define  RESET_CAUSE_POR                0x08000000
-#define  RESET_CAUSE_PIN                0x04000000
-#define  RESET_CAUSE_OTHER              0xfe000000
-#define  RESET_CAUSE_RMVF               0x01000000
+#define RESET_CAUSE_WDG 0x60000000
+#define RESET_CAUSE_SFT 0x10000000
+#define RESET_CAUSE_POR 0x08000000
+#define RESET_CAUSE_PIN 0x04000000
+#define RESET_CAUSE_OTHER 0xfe000000
+#define RESET_CAUSE_RMVF 0x01000000
 /* Power cause in PWR CSR register */
 #define STM32_PWR_RESET_CAUSE STM32_PWR_CSR
 #define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR
-#define  RESET_CAUSE_SBF                0x00000002
-#define  RESET_CAUSE_SBF_CLR            0x00000004
+#define RESET_CAUSE_SBF 0x00000002
+#define RESET_CAUSE_SBF_CLR 0x00000004
 
 /* --- Watchdogs --- */
 
 /* --- Real-Time Clock --- */
-#define STM32_RTC_TR                REG32(STM32_RTC_BASE + 0x00)
-#define STM32_RTC_DR                REG32(STM32_RTC_BASE + 0x04)
-#define STM32_RTC_CR                REG32(STM32_RTC_BASE + 0x08)
-#define STM32_RTC_CR_BYPSHAD        BIT(5)
-#define STM32_RTC_CR_ALRAE          BIT(8)
-#define STM32_RTC_CR_ALRAIE         BIT(12)
-#define STM32_RTC_ISR               REG32(STM32_RTC_BASE + 0x0C)
-#define STM32_RTC_ISR_ALRAWF        BIT(0)
-#define STM32_RTC_ISR_RSF           BIT(5)
-#define STM32_RTC_ISR_INITF         BIT(6)
-#define STM32_RTC_ISR_INIT          BIT(7)
-#define STM32_RTC_ISR_ALRAF         BIT(8)
-#define STM32_RTC_PRER              REG32(STM32_RTC_BASE + 0x10)
-#define STM32_RTC_PRER_A_MASK       (0x7f << 16)
-#define STM32_RTC_PRER_S_MASK       (0x7fff << 0)
-#define STM32_RTC_WUTR              REG32(STM32_RTC_BASE + 0x14)
-#define STM32_RTC_CALIBR            REG32(STM32_RTC_BASE + 0x18)
-#define STM32_RTC_ALRMAR            REG32(STM32_RTC_BASE + 0x1C)
-#define STM32_RTC_ALRMBR            REG32(STM32_RTC_BASE + 0x20)
-#define STM32_RTC_WPR               REG32(STM32_RTC_BASE + 0x24)
-#define STM32_RTC_SSR               REG32(STM32_RTC_BASE + 0x28)
-#define STM32_RTC_TSTR              REG32(STM32_RTC_BASE + 0x30)
-#define STM32_RTC_TSDR              REG32(STM32_RTC_BASE + 0x34)
-#define STM32_RTC_TAFCR             REG32(STM32_RTC_BASE + 0x40)
-#define STM32_RTC_ALRMASSR          REG32(STM32_RTC_BASE + 0x44)
-#define STM32_RTC_BACKUP(n)         REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
-
-#define STM32_BKP_DATA(n)           STM32_RTC_BACKUP(n)
-#define STM32_BKP_BYTES             80
+#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00)
+#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04)
+#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08)
+#define STM32_RTC_CR_BYPSHAD BIT(5)
+#define STM32_RTC_CR_ALRAE BIT(8)
+#define STM32_RTC_CR_ALRAIE BIT(12)
+#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C)
+#define STM32_RTC_ISR_ALRAWF BIT(0)
+#define STM32_RTC_ISR_RSF BIT(5)
+#define STM32_RTC_ISR_INITF BIT(6)
+#define STM32_RTC_ISR_INIT BIT(7)
+#define STM32_RTC_ISR_ALRAF BIT(8)
+#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10)
+#define STM32_RTC_PRER_A_MASK (0x7f << 16)
+#define STM32_RTC_PRER_S_MASK (0x7fff << 0)
+#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14)
+#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18)
+#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C)
+#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20)
+#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24)
+#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28)
+#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30)
+#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34)
+#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40)
+#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44)
+#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
+
+#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n)
+#define STM32_BKP_BYTES 80
 
 /* --- SPI --- */
 
@@ -597,8 +594,8 @@ struct stm32_spi_regs {
 	unsigned crcpr;
 	unsigned rxcrcr;
 	unsigned txcrcr;
-	unsigned i2scfgr;	/* STM32L only */
-	unsigned i2spr;		/* STM32L only */
+	unsigned i2scfgr; /* STM32L only */
+	unsigned i2spr; /* STM32L only */
 };
 /* Must be volatile, or compiler optimizes out repeated accesses */
 typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
@@ -608,146 +605,142 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
 #define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE)
 #define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE)
 
-#define STM32_SPI_CR1_BIDIMODE		BIT(15)
-#define STM32_SPI_CR1_BIDIOE		BIT(14)
-#define STM32_SPI_CR1_CRCEN		BIT(13)
-#define STM32_SPI_CR1_SSM		BIT(9)
-#define STM32_SPI_CR1_SSI		BIT(8)
-#define STM32_SPI_CR1_LSBFIRST		BIT(7)
-#define STM32_SPI_CR1_SPE		BIT(6)
-#define STM32_SPI_CR1_BR_DIV64R		(5 << 3)
-#define STM32_SPI_CR1_BR_DIV4R		BIT(3)
-#define STM32_SPI_CR1_MSTR		BIT(2)
-#define STM32_SPI_CR1_CPOL		BIT(1)
-#define STM32_SPI_CR1_CPHA		BIT(0)
-#define STM32_SPI_CR2_FRXTH		BIT(12)
-#define STM32_SPI_CR2_DATASIZE(n)	(((n) - 1) << 8)
-#define STM32_SPI_CR2_TXEIE		BIT(7)
-#define STM32_SPI_CR2_RXNEIE		BIT(6)
-#define STM32_SPI_CR2_NSSP		BIT(3)
-#define STM32_SPI_CR2_SSOE		BIT(2)
-#define STM32_SPI_CR2_TXDMAEN		BIT(1)
-#define STM32_SPI_CR2_RXDMAEN		BIT(0)
-
-#define STM32_SPI_SR_RXNE		BIT(0)
-#define STM32_SPI_SR_TXE		BIT(1)
-#define STM32_SPI_SR_CRCERR		BIT(4)
-#define STM32_SPI_SR_BSY		BIT(7)
-#define STM32_SPI_SR_FRLVL		(3 << 9)
-#define STM32_SPI_SR_FTLVL		(3 << 11)
+#define STM32_SPI_CR1_BIDIMODE BIT(15)
+#define STM32_SPI_CR1_BIDIOE BIT(14)
+#define STM32_SPI_CR1_CRCEN BIT(13)
+#define STM32_SPI_CR1_SSM BIT(9)
+#define STM32_SPI_CR1_SSI BIT(8)
+#define STM32_SPI_CR1_LSBFIRST BIT(7)
+#define STM32_SPI_CR1_SPE BIT(6)
+#define STM32_SPI_CR1_BR_DIV64R (5 << 3)
+#define STM32_SPI_CR1_BR_DIV4R BIT(3)
+#define STM32_SPI_CR1_MSTR BIT(2)
+#define STM32_SPI_CR1_CPOL BIT(1)
+#define STM32_SPI_CR1_CPHA BIT(0)
+#define STM32_SPI_CR2_FRXTH BIT(12)
+#define STM32_SPI_CR2_DATASIZE(n) (((n)-1) << 8)
+#define STM32_SPI_CR2_TXEIE BIT(7)
+#define STM32_SPI_CR2_RXNEIE BIT(6)
+#define STM32_SPI_CR2_NSSP BIT(3)
+#define STM32_SPI_CR2_SSOE BIT(2)
+#define STM32_SPI_CR2_TXDMAEN BIT(1)
+#define STM32_SPI_CR2_RXDMAEN BIT(0)
+
+#define STM32_SPI_SR_RXNE BIT(0)
+#define STM32_SPI_SR_TXE BIT(1)
+#define STM32_SPI_SR_CRCERR BIT(4)
+#define STM32_SPI_SR_BSY BIT(7)
+#define STM32_SPI_SR_FRLVL (3 << 9)
+#define STM32_SPI_SR_FTLVL (3 << 11)
 /* --- Debug --- */
-#define STM32_DBGMCU_APB1FZ         REG32(STM32_DBGMCU_BASE + 0x08)
-#define STM32_DBGMCU_APB2FZ         REG32(STM32_DBGMCU_BASE + 0x0C)
+#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08)
+#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C)
 
 /* --- Flash --- */
-#define STM32_FLASH_ACR             REG32(STM32_FLASH_REGS_BASE + 0x00)
-#define STM32_FLASH_ACR_SHIFT           0
-#define STM32_FLASH_ACR_LAT_MASK        0xf
-#define STM32_FLASH_ACR_PRFTEN          BIT(8)
-#define STM32_FLASH_ACR_ICEN            BIT(9)
-#define STM32_FLASH_ACR_DCEN            BIT(10)
-#define STM32_FLASH_ACR_ICRST           BIT(11)
-#define STM32_FLASH_ACR_DCRST           BIT(12)
-#define STM32_FLASH_KEYR            REG32(STM32_FLASH_REGS_BASE + 0x04)
-#define  FLASH_KEYR_KEY1                0x45670123
-#define  FLASH_KEYR_KEY2                0xCDEF89AB
-#define STM32_FLASH_OPTKEYR         REG32(STM32_FLASH_REGS_BASE + 0x08)
-#define  FLASH_OPTKEYR_KEY1             0x08192A3B
-#define  FLASH_OPTKEYR_KEY2             0x4C5D6E7F
-#define STM32_FLASH_SR              REG32(STM32_FLASH_REGS_BASE + 0x0c)
-#define  FLASH_SR_EOP                   BIT(0)
-#define  FLASH_SR_OPERR                 BIT(1)
-#define  FLASH_SR_WRPERR                BIT(4)
-#define  FLASH_SR_PGAERR                BIT(5)
-#define  FLASH_SR_PGPERR                BIT(6)
-#define  FLASH_SR_PGSERR                BIT(7)
-#define  FLASH_SR_RDERR                 BIT(8)
-#define  FLASH_SR_ALL_ERR \
+#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00)
+#define STM32_FLASH_ACR_SHIFT 0
+#define STM32_FLASH_ACR_LAT_MASK 0xf
+#define STM32_FLASH_ACR_PRFTEN BIT(8)
+#define STM32_FLASH_ACR_ICEN BIT(9)
+#define STM32_FLASH_ACR_DCEN BIT(10)
+#define STM32_FLASH_ACR_ICRST BIT(11)
+#define STM32_FLASH_ACR_DCRST BIT(12)
+#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x04)
+#define FLASH_KEYR_KEY1 0x45670123
+#define FLASH_KEYR_KEY2 0xCDEF89AB
+#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x08)
+#define FLASH_OPTKEYR_KEY1 0x08192A3B
+#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F
+#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x0c)
+#define FLASH_SR_EOP BIT(0)
+#define FLASH_SR_OPERR BIT(1)
+#define FLASH_SR_WRPERR BIT(4)
+#define FLASH_SR_PGAERR BIT(5)
+#define FLASH_SR_PGPERR BIT(6)
+#define FLASH_SR_PGSERR BIT(7)
+#define FLASH_SR_RDERR BIT(8)
+#define FLASH_SR_ALL_ERR                                      \
 	(FLASH_SR_OPERR | FLASH_SR_WRPERR | FLASH_SR_PGAERR | \
 	 FLASH_SR_PGPERR | FLASH_SR_PGSERR | FLASH_SR_RDERR)
-#define  FLASH_SR_BUSY                   BIT(16)
-#define STM32_FLASH_CR              REG32(STM32_FLASH_REGS_BASE + 0x10)
-#define  FLASH_CR_PG                    BIT(0)
-#define  FLASH_CR_PER                   BIT(1)
-#define  FLASH_CR_MER                   BIT(2)
-#define STM32_FLASH_CR_SNB_OFFSET       (3)
-#define STM32_FLASH_CR_SNB(sec) \
-	(((sec) & 0xf) << STM32_FLASH_CR_SNB_OFFSET)
-#define STM32_FLASH_CR_SNB_MASK         (STM32_FLASH_CR_SNB(0xf))
-#define STM32_FLASH_CR_PSIZE_OFFSET     (8)
-#define STM32_FLASH_CR_PSIZE(size) \
-	(((size) & 0x3) << STM32_FLASH_CR_PSIZE_OFFSET)
-#define STM32_FLASH_CR_PSIZE_MASK       (STM32_FLASH_CR_PSIZE(0x3))
-#define  FLASH_CR_STRT                  BIT(16)
-#define  FLASH_CR_LOCK                  BIT(31)
-#define STM32_FLASH_OPTCR           REG32(STM32_FLASH_REGS_BASE + 0x14)
-#define  FLASH_OPTLOCK                  BIT(0)
-#define  FLASH_OPTSTRT                  BIT(1)
-#define STM32_FLASH_BOR_LEV_OFFSET      (2)
-#define STM32_FLASH_RDP_MASK            (0xFF << 8)
-#define STM32_FLASH_nWRP_OFFSET         (16)
-#define STM32_FLASH_nWRP(_bank)         BIT(_bank + STM32_FLASH_nWRP_OFFSET)
-#define STM32_FLASH_nWRP_ALL            (0xFF << STM32_FLASH_nWRP_OFFSET)
-#define STM32_FLASH_OPT_LOCKED      (STM32_FLASH_OPTCR & FLASH_OPTLOCK)
-
-#define STM32_OPTB_RDP_USER         REG32(STM32_OPTB_BASE + 0x00)
-#define STM32_OPTB_RDP_OFF              0x00
-#define STM32_OPTB_USER_OFF             0x02
-#define STM32_OPTB_WRP_OFF(n)       (0x08 + (n&3) * 2)
-#define STM32_OPTB_WP               REG32(STM32_OPTB_BASE + 0x08)
-#define STM32_OPTB_nWRP(_bank)          BIT(_bank)
-#define STM32_OPTB_nWRP_ALL             (0xFF)
-
-#define STM32_OPTB_COMPL_SHIFT      8
-
-#define STM32_OTP_BLOCK_NB              16
-#define STM32_OTP_BLOCK_SIZE            32
+#define FLASH_SR_BUSY BIT(16)
+#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x10)
+#define FLASH_CR_PG BIT(0)
+#define FLASH_CR_PER BIT(1)
+#define FLASH_CR_MER BIT(2)
+#define STM32_FLASH_CR_SNB_OFFSET (3)
+#define STM32_FLASH_CR_SNB(sec) (((sec)&0xf) << STM32_FLASH_CR_SNB_OFFSET)
+#define STM32_FLASH_CR_SNB_MASK (STM32_FLASH_CR_SNB(0xf))
+#define STM32_FLASH_CR_PSIZE_OFFSET (8)
+#define STM32_FLASH_CR_PSIZE(size) (((size)&0x3) << STM32_FLASH_CR_PSIZE_OFFSET)
+#define STM32_FLASH_CR_PSIZE_MASK (STM32_FLASH_CR_PSIZE(0x3))
+#define FLASH_CR_STRT BIT(16)
+#define FLASH_CR_LOCK BIT(31)
+#define STM32_FLASH_OPTCR REG32(STM32_FLASH_REGS_BASE + 0x14)
+#define FLASH_OPTLOCK BIT(0)
+#define FLASH_OPTSTRT BIT(1)
+#define STM32_FLASH_BOR_LEV_OFFSET (2)
+#define STM32_FLASH_RDP_MASK (0xFF << 8)
+#define STM32_FLASH_nWRP_OFFSET (16)
+#define STM32_FLASH_nWRP(_bank) BIT(_bank + STM32_FLASH_nWRP_OFFSET)
+#define STM32_FLASH_nWRP_ALL (0xFF << STM32_FLASH_nWRP_OFFSET)
+#define STM32_FLASH_OPT_LOCKED (STM32_FLASH_OPTCR & FLASH_OPTLOCK)
+
+#define STM32_OPTB_RDP_USER REG32(STM32_OPTB_BASE + 0x00)
+#define STM32_OPTB_RDP_OFF 0x00
+#define STM32_OPTB_USER_OFF 0x02
+#define STM32_OPTB_WRP_OFF(n) (0x08 + (n & 3) * 2)
+#define STM32_OPTB_WP REG32(STM32_OPTB_BASE + 0x08)
+#define STM32_OPTB_nWRP(_bank) BIT(_bank)
+#define STM32_OPTB_nWRP_ALL (0xFF)
+
+#define STM32_OPTB_COMPL_SHIFT 8
+
+#define STM32_OTP_BLOCK_NB 16
+#define STM32_OTP_BLOCK_SIZE 32
 #define STM32_OTP_BLOCK_DATA(_block, _offset) \
-	(STM32_OTP_BASE + STM32_OTP_BLOCK_SIZE * (_block) + (_offset) * 4)
-#define STM32_OTP_UNLOCK_BYTE           0x00
-#define STM32_OTP_LOCK_BYTE             0xFF
-#define STM32_OTP_LOCK_BASE         \
+	(STM32_OTP_BASE + STM32_OTP_BLOCK_SIZE * (_block) + (_offset)*4)
+#define STM32_OTP_UNLOCK_BYTE 0x00
+#define STM32_OTP_LOCK_BYTE 0xFF
+#define STM32_OTP_LOCK_BASE \
 	(STM32_OTP_BASE + STM32_OTP_BLOCK_NB * STM32_OTP_BLOCK_SIZE)
-#define STM32_OTP_LOCK(_block) \
-	(STM32_OTP_LOCK_BASE + ((_block) / 4) * 4)
-#define STM32_OPT_LOCK_MASK(_block)    ((0xFF << ((_block) % 4) * 8))
+#define STM32_OTP_LOCK(_block) (STM32_OTP_LOCK_BASE + ((_block) / 4) * 4)
+#define STM32_OPT_LOCK_MASK(_block) ((0xFF << ((_block) % 4) * 8))
 
 /* --- External Interrupts --- */
-#define STM32_EXTI_IMR              REG32(STM32_EXTI_BASE + 0x00)
-#define STM32_EXTI_EMR              REG32(STM32_EXTI_BASE + 0x04)
-#define STM32_EXTI_RTSR             REG32(STM32_EXTI_BASE + 0x08)
-#define STM32_EXTI_FTSR             REG32(STM32_EXTI_BASE + 0x0c)
-#define STM32_EXTI_SWIER            REG32(STM32_EXTI_BASE + 0x10)
-#define STM32_EXTI_PR               REG32(STM32_EXTI_BASE + 0x14)
+#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00)
+#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04)
+#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08)
+#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c)
+#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10)
+#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14)
 
 #define EXTI_RTC_ALR_EVENT BIT(17)
 
 /* --- ADC --- */
-#define STM32_ADC_SR               REG32(STM32_ADC1_BASE + 0x00)
-#define STM32_ADC_CR1              REG32(STM32_ADC1_BASE + 0x04)
-#define STM32_ADC_CR2              REG32(STM32_ADC1_BASE + 0x08)
-#define STM32_ADC_CR2_ADON         BIT(0)
-#define STM32_ADC_CR2_CONT         BIT(1)
-#define STM32_ADC_CR2_CAL          BIT(2)
-#define STM32_ADC_CR2_RSTCAL       BIT(3)
-#define STM32_ADC_CR2_ALIGN        BIT(11)
-#define STM32_ADC_CR2_SWSTART      BIT(30)
-#define STM32_ADC_SMPR1            REG32(STM32_ADC1_BASE + 0x0C)
-#define STM32_ADC_SMPR2            REG32(STM32_ADC1_BASE + 0x10)
-#define STM32_ADC_JOFR(n)          REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4)
-#define STM32_ADC_HTR              REG32(STM32_ADC1_BASE + 0x24)
-#define STM32_ADC_LTR              REG32(STM32_ADC1_BASE + 0x28)
-#define STM32_ADC_SQR(n)           REG32(STM32_ADC1_BASE + 0x28 + ((n)&3) * 4)
-#define STM32_ADC_SQR1             REG32(STM32_ADC1_BASE + 0x2C)
-#define STM32_ADC_SQR2             REG32(STM32_ADC1_BASE + 0x30)
-#define STM32_ADC_SQR3             REG32(STM32_ADC1_BASE + 0x34)
-#define STM32_ADC_JSQR             REG32(STM32_ADC1_BASE + 0x38)
-#define STM32_ADC_JDR(n)           REG32(STM32_ADC1_BASE + 0x3C + ((n)&3) * 4)
-#define STM32_ADC_DR               REG32(STM32_ADC1_BASE + 0x4C)
+#define STM32_ADC_SR REG32(STM32_ADC1_BASE + 0x00)
+#define STM32_ADC_CR1 REG32(STM32_ADC1_BASE + 0x04)
+#define STM32_ADC_CR2 REG32(STM32_ADC1_BASE + 0x08)
+#define STM32_ADC_CR2_ADON BIT(0)
+#define STM32_ADC_CR2_CONT BIT(1)
+#define STM32_ADC_CR2_CAL BIT(2)
+#define STM32_ADC_CR2_RSTCAL BIT(3)
+#define STM32_ADC_CR2_ALIGN BIT(11)
+#define STM32_ADC_CR2_SWSTART BIT(30)
+#define STM32_ADC_SMPR1 REG32(STM32_ADC1_BASE + 0x0C)
+#define STM32_ADC_SMPR2 REG32(STM32_ADC1_BASE + 0x10)
+#define STM32_ADC_JOFR(n) REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4)
+#define STM32_ADC_HTR REG32(STM32_ADC1_BASE + 0x24)
+#define STM32_ADC_LTR REG32(STM32_ADC1_BASE + 0x28)
+#define STM32_ADC_SQR(n) REG32(STM32_ADC1_BASE + 0x28 + ((n)&3) * 4)
+#define STM32_ADC_SQR1 REG32(STM32_ADC1_BASE + 0x2C)
+#define STM32_ADC_SQR2 REG32(STM32_ADC1_BASE + 0x30)
+#define STM32_ADC_SQR3 REG32(STM32_ADC1_BASE + 0x34)
+#define STM32_ADC_JSQR REG32(STM32_ADC1_BASE + 0x38)
+#define STM32_ADC_JDR(n) REG32(STM32_ADC1_BASE + 0x3C + ((n)&3) * 4)
+#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x4C)
 
 /* --- Comparators --- */
 
-
 /* --- DMA --- */
 /*
  * Available DMA streams, numbered from 0.
@@ -838,12 +831,12 @@ enum dma_channel {
 
 /* Registers for a single stream of a DMA controller */
 struct stm32_dma_stream {
-	uint32_t	scr;		/* Control */
-	uint32_t	sndtr;		/* Number of data to transfer */
-	uint32_t	spar;		/* Peripheral address */
-	uint32_t	sm0ar;		/* Memory address 0 */
-	uint32_t	sm1ar;		/*  address 1 for double buffer */
-	uint32_t	sfcr;		/* FIFO control */
+	uint32_t scr; /* Control */
+	uint32_t sndtr; /* Number of data to transfer */
+	uint32_t spar; /* Peripheral address */
+	uint32_t sm0ar; /* Memory address 0 */
+	uint32_t sm1ar; /*  address 1 for double buffer */
+	uint32_t sfcr; /* FIFO control */
 };
 
 /* Always use stm32_dma_stream_t so volatile keyword is included! */
@@ -852,12 +845,11 @@ typedef volatile struct stm32_dma_stream stm32_dma_stream_t;
 /* Common code and header file must use this */
 typedef stm32_dma_stream_t dma_chan_t;
 struct stm32_dma_regs {
-	uint32_t	isr[2];
-	uint32_t	ifcr[2];
+	uint32_t isr[2];
+	uint32_t ifcr[2];
 	stm32_dma_stream_t stream[STM32_DMAS_COUNT];
 };
 
-
 /* Always use stm32_dma_regs_t so volatile keyword is included! */
 typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
 
@@ -868,215 +860,134 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
 #define STM32_DMA_REGS(channel) \
 	((channel) < STM32_DMAS_COUNT ? STM32_DMA1_REGS : STM32_DMA2_REGS)
 
-#define STM32_DMA_CCR_EN                BIT(0)
-#define STM32_DMA_CCR_DMEIE             BIT(1)
-#define STM32_DMA_CCR_TEIE              BIT(2)
-#define STM32_DMA_CCR_HTIE              BIT(3)
-#define STM32_DMA_CCR_TCIE              BIT(4)
-#define STM32_DMA_CCR_PFCTRL            BIT(5)
-#define STM32_DMA_CCR_DIR_P2M		(0 << 6)
-#define STM32_DMA_CCR_DIR_M2P		(1 << 6)
-#define STM32_DMA_CCR_DIR_M2M		(2 << 6)
-#define STM32_DMA_CCR_CIRC              BIT(8)
-#define STM32_DMA_CCR_PINC              BIT(9)
-#define STM32_DMA_CCR_MINC              BIT(10)
-#define STM32_DMA_CCR_PSIZE_8_BIT       (0 << 11)
-#define STM32_DMA_CCR_PSIZE_16_BIT      (1 << 11)
-#define STM32_DMA_CCR_PSIZE_32_BIT      (2 << 11)
-#define STM32_DMA_CCR_MSIZE_8_BIT       (0 << 13)
-#define STM32_DMA_CCR_MSIZE_16_BIT      (1 << 13)
-#define STM32_DMA_CCR_MSIZE_32_BIT      (2 << 13)
-#define STM32_DMA_CCR_PINCOS            BIT(15)
-#define STM32_DMA_CCR_PL_LOW            (0 << 16)
-#define STM32_DMA_CCR_PL_MEDIUM         (1 << 16)
-#define STM32_DMA_CCR_PL_HIGH           (2 << 16)
-#define STM32_DMA_CCR_PL_VERY_HIGH      (3 << 16)
-#define STM32_DMA_CCR_DBM               BIT(18)
-#define STM32_DMA_CCR_CT                BIT(19)
-#define STM32_DMA_CCR_PBURST(b_len)		 ((((b_len) - 4) / 4) << 21)
-#define STM32_DMA_CCR_MBURST(b_len)		 ((((b_len) - 4) / 4) << 21)
-#define STM32_DMA_CCR_CHANNEL_MASK		 (0x7 << 25)
-#define STM32_DMA_CCR_CHANNEL(channel)		 ((channel) << 25)
-#define STM32_DMA_CCR_RSVD_MASK		(0xF0100000)
-
-
-#define STM32_DMA_SFCR_DMDIS		BIT(2)
-#define STM32_DMA_SFCR_FTH(level)	(((level) - 1) << 0)
-
-
-#define STM32_DMA_CH_LOCAL(channel)     ((channel) % STM32_DMAS_COUNT)
-#define STM32_DMA_CH_LH(channel)        \
-	((STM32_DMA_CH_LOCAL(channel) < 4) ? 0 : 1)
-#define STM32_DMA_CH_OFFSET(channel)    \
+#define STM32_DMA_CCR_EN BIT(0)
+#define STM32_DMA_CCR_DMEIE BIT(1)
+#define STM32_DMA_CCR_TEIE BIT(2)
+#define STM32_DMA_CCR_HTIE BIT(3)
+#define STM32_DMA_CCR_TCIE BIT(4)
+#define STM32_DMA_CCR_PFCTRL BIT(5)
+#define STM32_DMA_CCR_DIR_P2M (0 << 6)
+#define STM32_DMA_CCR_DIR_M2P (1 << 6)
+#define STM32_DMA_CCR_DIR_M2M (2 << 6)
+#define STM32_DMA_CCR_CIRC BIT(8)
+#define STM32_DMA_CCR_PINC BIT(9)
+#define STM32_DMA_CCR_MINC BIT(10)
+#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 11)
+#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 11)
+#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 11)
+#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 13)
+#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 13)
+#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 13)
+#define STM32_DMA_CCR_PINCOS BIT(15)
+#define STM32_DMA_CCR_PL_LOW (0 << 16)
+#define STM32_DMA_CCR_PL_MEDIUM (1 << 16)
+#define STM32_DMA_CCR_PL_HIGH (2 << 16)
+#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 16)
+#define STM32_DMA_CCR_DBM BIT(18)
+#define STM32_DMA_CCR_CT BIT(19)
+#define STM32_DMA_CCR_PBURST(b_len) ((((b_len)-4) / 4) << 21)
+#define STM32_DMA_CCR_MBURST(b_len) ((((b_len)-4) / 4) << 21)
+#define STM32_DMA_CCR_CHANNEL_MASK (0x7 << 25)
+#define STM32_DMA_CCR_CHANNEL(channel) ((channel) << 25)
+#define STM32_DMA_CCR_RSVD_MASK (0xF0100000)
+
+#define STM32_DMA_SFCR_DMDIS BIT(2)
+#define STM32_DMA_SFCR_FTH(level) (((level)-1) << 0)
+
+#define STM32_DMA_CH_LOCAL(channel) ((channel) % STM32_DMAS_COUNT)
+#define STM32_DMA_CH_LH(channel) ((STM32_DMA_CH_LOCAL(channel) < 4) ? 0 : 1)
+#define STM32_DMA_CH_OFFSET(channel)               \
 	(((STM32_DMA_CH_LOCAL(channel) % 4) * 6) + \
-	(((STM32_DMA_CH_LOCAL(channel) % 4) >= 2) ? 4 : 0))
+	 (((STM32_DMA_CH_LOCAL(channel) % 4) >= 2) ? 4 : 0))
 #define STM32_DMA_CH_GETBITS(channel, val) \
 	(((val) >> STM32_DMA_CH_OFFSET(channel)) & 0x3f)
-#define STM32_DMA_GET_IFCR(channel)      \
-	(STM32_DMA_CH_GETBITS(channel,   \
-	STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)]))
-#define STM32_DMA_GET_ISR(channel)       \
-	(STM32_DMA_CH_GETBITS(channel,   \
-	STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)]))
-
-#define STM32_DMA_SET_IFCR(channel, val) \
-	(STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] = \
-	(STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] & \
-	~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel)))
-#define STM32_DMA_SET_ISR(channel, val) \
-	(STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] = \
-	(STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] & \
-	~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel)))
-
-#define STM32_DMA_FEIF                  BIT(0)
-#define STM32_DMA_DMEIF                 BIT(2)
-#define STM32_DMA_TEIF                  BIT(3)
-#define STM32_DMA_HTIF                  BIT(4)
-#define STM32_DMA_TCIF                  BIT(5)
-#define STM32_DMA_ALL                   0x3d
-
-
+#define STM32_DMA_GET_IFCR(channel) \
+	(STM32_DMA_CH_GETBITS(      \
+		channel,            \
+		STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)]))
+#define STM32_DMA_GET_ISR(channel) \
+	(STM32_DMA_CH_GETBITS(     \
+		channel,           \
+		STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)]))
+
+#define STM32_DMA_SET_IFCR(channel, val)                                    \
+	(STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] =          \
+		 (STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] & \
+		  ~(0x3f << STM32_DMA_CH_OFFSET(channel))) |                \
+		 (((val)&0x3f) << STM32_DMA_CH_OFFSET(channel)))
+#define STM32_DMA_SET_ISR(channel, val)                                    \
+	(STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] =          \
+		 (STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] & \
+		  ~(0x3f << STM32_DMA_CH_OFFSET(channel))) |               \
+		 (((val)&0x3f) << STM32_DMA_CH_OFFSET(channel)))
+
+#define STM32_DMA_FEIF BIT(0)
+#define STM32_DMA_DMEIF BIT(2)
+#define STM32_DMA_TEIF BIT(3)
+#define STM32_DMA_HTIF BIT(4)
+#define STM32_DMA_TCIF BIT(5)
+#define STM32_DMA_ALL 0x3d
 
 /* --- CRC --- */
-#define STM32_CRC_DR                REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR32              REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR16              REG16(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR8               REG8(STM32_CRC_BASE + 0x0)
-
-#define STM32_CRC_IDR               REG32(STM32_CRC_BASE + 0x4)
-#define STM32_CRC_CR                REG32(STM32_CRC_BASE + 0x8)
-#define STM32_CRC_INIT              REG32(STM32_CRC_BASE + 0x10)
-#define STM32_CRC_POL               REG32(STM32_CRC_BASE + 0x14)
-
-#define STM32_CRC_CR_RESET          BIT(0)
-#define STM32_CRC_CR_POLYSIZE_32    (0 << 3)
-#define STM32_CRC_CR_POLYSIZE_16    (1 << 3)
-#define STM32_CRC_CR_POLYSIZE_8     (2 << 3)
-#define STM32_CRC_CR_POLYSIZE_7     (3 << 3)
-#define STM32_CRC_CR_REV_IN_BYTE    (1 << 5)
-#define STM32_CRC_CR_REV_IN_HWORD   (2 << 5)
-#define STM32_CRC_CR_REV_IN_WORD    (3 << 5)
-#define STM32_CRC_CR_REV_OUT        BIT(7)
+#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0)
+
+#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4)
+#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8)
+#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10)
+#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14)
+
+#define STM32_CRC_CR_RESET BIT(0)
+#define STM32_CRC_CR_POLYSIZE_32 (0 << 3)
+#define STM32_CRC_CR_POLYSIZE_16 (1 << 3)
+#define STM32_CRC_CR_POLYSIZE_8 (2 << 3)
+#define STM32_CRC_CR_POLYSIZE_7 (3 << 3)
+#define STM32_CRC_CR_REV_IN_BYTE (1 << 5)
+#define STM32_CRC_CR_REV_IN_HWORD (2 << 5)
+#define STM32_CRC_CR_REV_IN_WORD (3 << 5)
+#define STM32_CRC_CR_REV_OUT BIT(7)
 
 /* --- PMSE --- */
-#define STM32_PMSE_ARCR             REG32(STM32_PMSE_BASE + 0x0)
-#define STM32_PMSE_ACCR             REG32(STM32_PMSE_BASE + 0x4)
-#define STM32_PMSE_CR               REG32(STM32_PMSE_BASE + 0x8)
-#define STM32_PMSE_CRTDR            REG32(STM32_PMSE_BASE + 0x14)
-#define STM32_PMSE_IER              REG32(STM32_PMSE_BASE + 0x18)
-#define STM32_PMSE_SR               REG32(STM32_PMSE_BASE + 0x1c)
-#define STM32_PMSE_IFCR             REG32(STM32_PMSE_BASE + 0x20)
-#define STM32_PMSE_PxPMR(x)         REG32(STM32_PMSE_BASE + 0x2c + (x) * 4)
-#define STM32_PMSE_PAPMR            REG32(STM32_PMSE_BASE + 0x2c)
-#define STM32_PMSE_PBPMR            REG32(STM32_PMSE_BASE + 0x30)
-#define STM32_PMSE_PCPMR            REG32(STM32_PMSE_BASE + 0x34)
-#define STM32_PMSE_PDPMR            REG32(STM32_PMSE_BASE + 0x38)
-#define STM32_PMSE_PEPMR            REG32(STM32_PMSE_BASE + 0x3c)
-#define STM32_PMSE_PFPMR            REG32(STM32_PMSE_BASE + 0x40)
-#define STM32_PMSE_PGPMR            REG32(STM32_PMSE_BASE + 0x44)
-#define STM32_PMSE_PHPMR            REG32(STM32_PMSE_BASE + 0x48)
-#define STM32_PMSE_PIPMR            REG32(STM32_PMSE_BASE + 0x4c)
-#define STM32_PMSE_MRCR             REG32(STM32_PMSE_BASE + 0x100)
-#define STM32_PMSE_MCCR             REG32(STM32_PMSE_BASE + 0x104)
-
-/* --- USB --- */
-#define STM32_USB_EP(n)            REG16(STM32_USB_FS_BASE + (n) * 4)
-
-#define STM32_USB_CNTR             REG16(STM32_USB_FS_BASE + 0x40)
-
-#define STM32_USB_CNTR_FRES	    BIT(0)
-#define STM32_USB_CNTR_PDWN	    BIT(1)
-#define STM32_USB_CNTR_LP_MODE	    BIT(2)
-#define STM32_USB_CNTR_FSUSP	    BIT(3)
-#define STM32_USB_CNTR_RESUME	    BIT(4)
-#define STM32_USB_CNTR_L1RESUME	    BIT(5)
-#define STM32_USB_CNTR_L1REQM	    BIT(7)
-#define STM32_USB_CNTR_ESOFM	    BIT(8)
-#define STM32_USB_CNTR_SOFM	    BIT(9)
-#define STM32_USB_CNTR_RESETM	    BIT(10)
-#define STM32_USB_CNTR_SUSPM	    BIT(11)
-#define STM32_USB_CNTR_WKUPM	    BIT(12)
-#define STM32_USB_CNTR_ERRM	    BIT(13)
-#define STM32_USB_CNTR_PMAOVRM	    BIT(14)
-#define STM32_USB_CNTR_CTRM	    BIT(15)
-
-#define STM32_USB_ISTR             REG16(STM32_USB_FS_BASE + 0x44)
-
-#define STM32_USB_ISTR_EP_ID_MASK   (0x000f)
-#define STM32_USB_ISTR_DIR	    BIT(4)
-#define STM32_USB_ISTR_L1REQ	    BIT(7)
-#define STM32_USB_ISTR_ESOF	    BIT(8)
-#define STM32_USB_ISTR_SOF	    BIT(9)
-#define STM32_USB_ISTR_RESET	    BIT(10)
-#define STM32_USB_ISTR_SUSP	    BIT(11)
-#define STM32_USB_ISTR_WKUP	    BIT(12)
-#define STM32_USB_ISTR_ERR	    BIT(13)
-#define STM32_USB_ISTR_PMAOVR	    BIT(14)
-#define STM32_USB_ISTR_CTR	    BIT(15)
-
-#define STM32_USB_FNR              REG16(STM32_USB_FS_BASE + 0x48)
-
-#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14)
-#define STM32_USB_FNR_RXDP_RXDM_MASK  (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT)
-
-#define STM32_USB_DADDR            REG16(STM32_USB_FS_BASE + 0x4C)
-#define STM32_USB_BTABLE           REG16(STM32_USB_FS_BASE + 0x50)
-#define STM32_USB_LPMCSR           REG16(STM32_USB_FS_BASE + 0x54)
-#define STM32_USB_BCDR             REG16(STM32_USB_FS_BASE + 0x58)
-
-#define STM32_USB_BCDR_BCDEN	    BIT(0)
-#define STM32_USB_BCDR_DCDEN	    BIT(1)
-#define STM32_USB_BCDR_PDEN	    BIT(2)
-#define STM32_USB_BCDR_SDEN	    BIT(3)
-#define STM32_USB_BCDR_DCDET	    BIT(4)
-#define STM32_USB_BCDR_PDET	    BIT(5)
-#define STM32_USB_BCDR_SDET	    BIT(6)
-#define STM32_USB_BCDR_PS2DET	    BIT(7)
-
-#define EP_MASK     0x0F0F
-#define EP_TX_DTOG  0x0040
-#define EP_TX_MASK  0x0030
-#define EP_TX_VALID 0x0030
-#define EP_TX_NAK   0x0020
-#define EP_TX_STALL 0x0010
-#define EP_TX_DISAB 0x0000
-#define EP_RX_DTOG  0x4000
-#define EP_RX_MASK  0x3000
-#define EP_RX_VALID 0x3000
-#define EP_RX_NAK   0x2000
-#define EP_RX_STALL 0x1000
-#define EP_RX_DISAB 0x0000
-
-#define EP_STATUS_OUT 0x0100
-
-#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK)
-#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID)
-
-#define STM32_TOGGLE_EP(n, mask, val, flags) \
-	STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \
-			^ (val)) | (flags))
+#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0)
+#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4)
+#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8)
+#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14)
+#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18)
+#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c)
+#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20)
+#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x)*4)
+#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c)
+#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30)
+#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34)
+#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38)
+#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c)
+#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40)
+#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44)
+#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48)
+#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c)
+#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100)
+#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104)
 
 /* --- TRNG --- */
-#define STM32_RNG_CR                REG32(STM32_RNG_BASE + 0x0)
-#define STM32_RNG_CR_RNGEN          BIT(2)
-#define STM32_RNG_CR_IE             BIT(3)
-#define STM32_RNG_CR_CED            BIT(5)
-#define STM32_RNG_SR                REG32(STM32_RNG_BASE + 0x4)
-#define STM32_RNG_SR_DRDY           BIT(0)
-#define STM32_RNG_DR                REG32(STM32_RNG_BASE + 0x8)
+#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0)
+#define STM32_RNG_CR_RNGEN BIT(2)
+#define STM32_RNG_CR_IE BIT(3)
+#define STM32_RNG_CR_CED BIT(5)
+#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4)
+#define STM32_RNG_SR_DRDY BIT(0)
+#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8)
 
 /* --- AXI interconnect --- */
 
 /* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */
-#define STM32_AXI_TARG_FN_MOD(x)    REG32(STM32_GPV_BASE + 0x1108 + \
-					  0x1000 * (x))
-#define  WRITE_ISS_OVERRIDE         BIT(1)
-#define  READ_ISS_OVERRIDE          BIT(0)
+#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + 0x1000 * (x))
+#define WRITE_ISS_OVERRIDE BIT(1)
+#define READ_ISS_OVERRIDE BIT(0)
 
 /* --- MISC --- */
-#define STM32_UNIQUE_ID_ADDRESS     REG32_ADDR(STM32_UNIQUE_ID_BASE)
-#define STM32_UNIQUE_ID_LENGTH      (3 * 4)
+#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE)
+#define STM32_UNIQUE_ID_LENGTH (3 * 4)
 
 #endif /* !__ASSEMBLER__ */
diff --git a/chip/stm32/registers-stm32g4.h b/chip/stm32/registers-stm32g4.h
index 5ad6194795..4610bb1e98 100644
--- a/chip/stm32/registers-stm32g4.h
+++ b/chip/stm32/registers-stm32g4.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,87 +19,87 @@
 #endif
 
 /* --- IRQ numbers --- */
-#define STM32_IRQ_WWDG             0
-#define STM32_IRQ_PVD              1
-#define STM32_IRQ_TAMPER_STAMP     2
-#define STM32_IRQ_RTC_WAKEUP       3
-#define STM32_IRQ_FLASH            4
-#define STM32_IRQ_RCC              5
-#define STM32_IRQ_EXTI0            6
-#define STM32_IRQ_EXTI1            7
-#define STM32_IRQ_EXTI2            8
-#define STM32_IRQ_EXTI3            9
-#define STM32_IRQ_EXTI4           10
-#define STM32_IRQ_DMA_CHANNEL_1   11
-#define STM32_IRQ_DMA_CHANNEL_2   12
-#define STM32_IRQ_DMA_CHANNEL_3   13
-#define STM32_IRQ_DMA_CHANNEL_4   14
-#define STM32_IRQ_DMA_CHANNEL_5   15
-#define STM32_IRQ_DMA_CHANNEL_6   16
-#define STM32_IRQ_DMA_CHANNEL_7   17
-#define STM32_IRQ_ADC1            18
-#define STM32_IRQ_USB_HP          19
-#define STM32_IRQ_USB_LP          20
-#define STM32_IRQ_FDCAN_IT0       21
-#define STM32_IRQ_FDCAN_IT1       22
-#define STM32_IRQ_EXTI9_5         23
-#define STM32_IRQ_TIM15           24
-#define STM32_IRQ_TIM16           25
-#define STM32_IRQ_TIM17           26
-#define STM32_IRQ_TIM1_CC         27
-#define STM32_IRQ_TIM2            28
-#define STM32_IRQ_TIM3            29
-#define STM32_IRQ_TIM4            30
-#define STM32_IRQ_I2C1_EV         31
-#define STM32_IRQ_I2C1_ER         32
-#define STM32_IRQ_I2C2_EV         33
-#define STM32_IRQ_I2C2_ER         34
-#define STM32_IRQ_SPI1            35
-#define STM32_IRQ_SPI2            36
-#define STM32_IRQ_USART1          37
-#define STM32_IRQ_USART2          38
-#define STM32_IRQ_USART3          39
-#define STM32_IRQ_EXTI15_10       40
-#define STM32_IRQ_RTC_ALARM       41
-#define STM32_IRQ_USB_FS_WAKEUP   42
-#define STM32_IRQ_TIM8_BREAK      43
-#define STM32_IRQ_TIM8_UP         44
-#define STM32_IRQ_TIM8_TRG_COM    45
-#define STM32_IRQ_TIM8_CC         46
-#define STM32_IRQ_LPTIM1          49
-#define STM32_IRQ_SPI3            51
-#define STM32_IRQ_USART4          52
-#define STM32_IRQ_TIM6_DAC        54
-#define STM32_IRQ_TIM7            55
-#define STM32_IRQ_DMA2_CHANNEL1   56
-#define STM32_IRQ_DMA2_CHANNEL2   57
-#define STM32_IRQ_DMA2_CHANNEL3   58
-#define STM32_IRQ_DMA2_CHANNEL4   59
-#define STM32_IRQ_DMA2_CHANNEL5   60
-#define STM32_IRQ_UCPD1           63
-#define STM32_IRQ_COMP_1_2_3      64
-#define STM32_IRQ_COMP_4          65
-#define STM32_IRQ_CRS             75
-#define STM32_IRQ_SAI1            76
-#define STM32_IRQ_FPU             81
-#define STM32_IRQ_RNG             90
-#define STM32_IRQ_LPUART          91
-#define STM32_IRQ_I2C3_EV         92
-#define STM32_IRQ_I2C3_ER         93
-#define STM32_IRQ_DMAMUX_OVR      94
-#define STM32_IRQ_DMA1_CHANNEL8   96
-#define STM32_IRQ_DMA2_CHANNEL6   97
-#define STM32_IRQ_DMA2_CHANNEL7   98
-#define STM32_IRQ_DMA2_CHANNEL8   99
-#define STM32_IRQ_CORDIC          100
-#define STM32_IRQ_FMAC            101
+#define STM32_IRQ_WWDG 0
+#define STM32_IRQ_PVD 1
+#define STM32_IRQ_TAMPER_STAMP 2
+#define STM32_IRQ_RTC_WAKEUP 3
+#define STM32_IRQ_FLASH 4
+#define STM32_IRQ_RCC 5
+#define STM32_IRQ_EXTI0 6
+#define STM32_IRQ_EXTI1 7
+#define STM32_IRQ_EXTI2 8
+#define STM32_IRQ_EXTI3 9
+#define STM32_IRQ_EXTI4 10
+#define STM32_IRQ_DMA_CHANNEL_1 11
+#define STM32_IRQ_DMA_CHANNEL_2 12
+#define STM32_IRQ_DMA_CHANNEL_3 13
+#define STM32_IRQ_DMA_CHANNEL_4 14
+#define STM32_IRQ_DMA_CHANNEL_5 15
+#define STM32_IRQ_DMA_CHANNEL_6 16
+#define STM32_IRQ_DMA_CHANNEL_7 17
+#define STM32_IRQ_ADC1 18
+#define STM32_IRQ_USB_HP 19
+#define STM32_IRQ_USB_LP 20
+#define STM32_IRQ_FDCAN_IT0 21
+#define STM32_IRQ_FDCAN_IT1 22
+#define STM32_IRQ_EXTI9_5 23
+#define STM32_IRQ_TIM15 24
+#define STM32_IRQ_TIM16 25
+#define STM32_IRQ_TIM17 26
+#define STM32_IRQ_TIM1_CC 27
+#define STM32_IRQ_TIM2 28
+#define STM32_IRQ_TIM3 29
+#define STM32_IRQ_TIM4 30
+#define STM32_IRQ_I2C1_EV 31
+#define STM32_IRQ_I2C1_ER 32
+#define STM32_IRQ_I2C2_EV 33
+#define STM32_IRQ_I2C2_ER 34
+#define STM32_IRQ_SPI1 35
+#define STM32_IRQ_SPI2 36
+#define STM32_IRQ_USART1 37
+#define STM32_IRQ_USART2 38
+#define STM32_IRQ_USART3 39
+#define STM32_IRQ_EXTI15_10 40
+#define STM32_IRQ_RTC_ALARM 41
+#define STM32_IRQ_USB_FS_WAKEUP 42
+#define STM32_IRQ_TIM8_BREAK 43
+#define STM32_IRQ_TIM8_UP 44
+#define STM32_IRQ_TIM8_TRG_COM 45
+#define STM32_IRQ_TIM8_CC 46
+#define STM32_IRQ_LPTIM1 49
+#define STM32_IRQ_SPI3 51
+#define STM32_IRQ_USART4 52
+#define STM32_IRQ_TIM6_DAC 54
+#define STM32_IRQ_TIM7 55
+#define STM32_IRQ_DMA2_CHANNEL1 56
+#define STM32_IRQ_DMA2_CHANNEL2 57
+#define STM32_IRQ_DMA2_CHANNEL3 58
+#define STM32_IRQ_DMA2_CHANNEL4 59
+#define STM32_IRQ_DMA2_CHANNEL5 60
+#define STM32_IRQ_UCPD1 63
+#define STM32_IRQ_COMP_1_2_3 64
+#define STM32_IRQ_COMP_4 65
+#define STM32_IRQ_CRS 75
+#define STM32_IRQ_SAI1 76
+#define STM32_IRQ_FPU 81
+#define STM32_IRQ_RNG 90
+#define STM32_IRQ_LPUART 91
+#define STM32_IRQ_I2C3_EV 92
+#define STM32_IRQ_I2C3_ER 93
+#define STM32_IRQ_DMAMUX_OVR 94
+#define STM32_IRQ_DMA1_CHANNEL8 96
+#define STM32_IRQ_DMA2_CHANNEL6 97
+#define STM32_IRQ_DMA2_CHANNEL7 98
+#define STM32_IRQ_DMA2_CHANNEL8 99
+#define STM32_IRQ_CORDIC 100
+#define STM32_IRQ_FMAC 101
 
 /* LPUART gets accessed as UART9 in STM32 uart driver */
 #define STM32_IRQ_USART9 STM32_IRQ_LPUART
 
 /* To simplify code generation, define DMA channel 13 - 14 */
-#define STM32_IRQ_DMA_CHANNEL_13   STM32_IRQ_DMA2_CHANNEL6
-#define STM32_IRQ_DMA_CHANNEL_14   STM32_IRQ_DMA2_CHANNEL7
+#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6
+#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7
 
 /* aliases for easier code sharing */
 #define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV
@@ -111,144 +111,144 @@
 #endif
 
 /* Embedded flash option bytes base address */
-#define STM32_OPTB_BANK1_BASE       0x1FFF7800UL
-#define STM32_OPTB_BANK2_BASE       0x1FFF8000UL
+#define STM32_OPTB_BANK1_BASE 0x1FFF7800UL
+#define STM32_OPTB_BANK2_BASE 0x1FFF8000UL
 
 /* Peripheral base addresses */
-#define STM32_PERIPH_BASE           (0x40000000UL)
+#define STM32_PERIPH_BASE (0x40000000UL)
 /* Peripheral memory map */
-#define STM32_APB1PERIPH_BASE       (STM32_PERIPH_BASE + 0x00000000UL)
-#define STM32_APB2PERIPH_BASE       (STM32_PERIPH_BASE + 0x00010000UL)
-#define STM32_AHB1PERIPH_BASE       (STM32_PERIPH_BASE + 0x00020000UL)
-#define STM32_AHB2PERIPH_BASE       (STM32_PERIPH_BASE + 0x08000000UL)
+#define STM32_APB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00000000UL)
+#define STM32_APB2PERIPH_BASE (STM32_PERIPH_BASE + 0x00010000UL)
+#define STM32_AHB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00020000UL)
+#define STM32_AHB2PERIPH_BASE (STM32_PERIPH_BASE + 0x08000000UL)
 
 /* APB1 peripherals */
-#define STM32_APB1PERIPH(offset)    (STM32_APB1PERIPH_BASE + offset)
-#define STM32_TIM2_BASE             STM32_APB1PERIPH(0x0000UL)
-#define STM32_TIM3_BASE             STM32_APB1PERIPH(0x0400UL)
-#define STM32_TIM4_BASE             STM32_APB1PERIPH(0x0800UL)
-#define STM32_TIM6_BASE             STM32_APB1PERIPH(0x1000UL)
-#define STM32_TIM7_BASE             STM32_APB1PERIPH(0x1400UL)
-#define STM32_CRS_BASE              STM32_APB1PERIPH(0x2000UL)
-#define STM32_TAMP_BASE             STM32_APB1PERIPH(0x2400UL)
-#define STM32_RTC_BASE              STM32_APB1PERIPH(0x2800UL)
-#define STM32_WWDG_BASE             STM32_APB1PERIPH(0x2C00UL)
-#define STM32_IWDG_BASE             STM32_APB1PERIPH(0x3000UL)
-#define STM32_SPI2_BASE             STM32_APB1PERIPH(0x3800UL)
-#define STM32_SPI3_BASE             STM32_APB1PERIPH(0x3C00UL)
-#define STM32_USART2_BASE           STM32_APB1PERIPH(0x4400UL)
-#define STM32_USART3_BASE           STM32_APB1PERIPH(0x4800UL)
-#define STM32_UART4_BASE            STM32_APB1PERIPH(0x4C00UL)
-#define STM32_I2C1_BASE             STM32_APB1PERIPH(0x5400UL)
-#define STM32_I2C2_BASE             STM32_APB1PERIPH(0x5800UL)
+#define STM32_APB1PERIPH(offset) (STM32_APB1PERIPH_BASE + offset)
+#define STM32_TIM2_BASE STM32_APB1PERIPH(0x0000UL)
+#define STM32_TIM3_BASE STM32_APB1PERIPH(0x0400UL)
+#define STM32_TIM4_BASE STM32_APB1PERIPH(0x0800UL)
+#define STM32_TIM6_BASE STM32_APB1PERIPH(0x1000UL)
+#define STM32_TIM7_BASE STM32_APB1PERIPH(0x1400UL)
+#define STM32_CRS_BASE STM32_APB1PERIPH(0x2000UL)
+#define STM32_TAMP_BASE STM32_APB1PERIPH(0x2400UL)
+#define STM32_RTC_BASE STM32_APB1PERIPH(0x2800UL)
+#define STM32_WWDG_BASE STM32_APB1PERIPH(0x2C00UL)
+#define STM32_IWDG_BASE STM32_APB1PERIPH(0x3000UL)
+#define STM32_SPI2_BASE STM32_APB1PERIPH(0x3800UL)
+#define STM32_SPI3_BASE STM32_APB1PERIPH(0x3C00UL)
+#define STM32_USART2_BASE STM32_APB1PERIPH(0x4400UL)
+#define STM32_USART3_BASE STM32_APB1PERIPH(0x4800UL)
+#define STM32_UART4_BASE STM32_APB1PERIPH(0x4C00UL)
+#define STM32_I2C1_BASE STM32_APB1PERIPH(0x5400UL)
+#define STM32_I2C2_BASE STM32_APB1PERIPH(0x5800UL)
 /* USB_IP Peripheral Registers base address */
-#define STM32_USB_FS_BASE           STM32_APB1PERIPH(0x5C00UL)
+#define STM32_USB_FS_BASE STM32_APB1PERIPH(0x5C00UL)
 /* USB_IP Packet Memory Area base address */
-#define STM32_USB_PMAADDR           STM32_APB1PERIPH(0x6000UL)
-#define STM32_FDCAN1_BASE           STM32_APB1PERIPH(0x6400UL)
+#define STM32_USB_PMAADDR STM32_APB1PERIPH(0x6000UL)
+#define STM32_FDCAN1_BASE STM32_APB1PERIPH(0x6400UL)
 /* FDCAN configuration registers base address */
-#define STM32_FDCAN_CONFIG_BASE     STM32_APB1PERIPH(0x6500UL)
-#define STM32_PWR_BASE              STM32_APB1PERIPH(0x7000UL)
-#define STM32_I2C3_BASE             STM32_APB1PERIPH(0x7800UL)
-#define STM32_LPTIM1_BASE           STM32_APB1PERIPH(0x7C00UL)
-#define STM32_LPUART1_BASE          STM32_APB1PERIPH(0x8000UL)
-#define STM32_I2C4_BASE             STM32_APB1PERIPH(0x8400UL)
+#define STM32_FDCAN_CONFIG_BASE STM32_APB1PERIPH(0x6500UL)
+#define STM32_PWR_BASE STM32_APB1PERIPH(0x7000UL)
+#define STM32_I2C3_BASE STM32_APB1PERIPH(0x7800UL)
+#define STM32_LPTIM1_BASE STM32_APB1PERIPH(0x7C00UL)
+#define STM32_LPUART1_BASE STM32_APB1PERIPH(0x8000UL)
+#define STM32_I2C4_BASE STM32_APB1PERIPH(0x8400UL)
 /* UART9 is used as link to LPUART in STM32 uart.c implementation */
-#define STM32_USART9_BASE           STM32_APB1PERIPH(0x8000UL)
-#define STM32_I2C4_BASE             STM32_APB1PERIPH(0x8400UL)
-#define STM32_UCPD1_BASE            STM32_APB1PERIPH(0xA000UL)
-#define STM32_SRAMCAN_BASE          STM32_APB1PERIPH(0xA400UL)
+#define STM32_USART9_BASE STM32_APB1PERIPH(0x8000UL)
+#define STM32_I2C4_BASE STM32_APB1PERIPH(0x8400UL)
+#define STM32_UCPD1_BASE STM32_APB1PERIPH(0xA000UL)
+#define STM32_SRAMCAN_BASE STM32_APB1PERIPH(0xA400UL)
 
 /* APB2 peripherals */
-#define STM32_APB2PERIPH(offset)    (STM32_APB2PERIPH_BASE + offset)
-#define STM32_SYSCFG_BASE           STM32_APB2PERIPH(0x0000UL)
-#define STM32_VREFBUF_BASE          STM32_APB2PERIPH(0x0030UL)
-#define STM32_COMP1_BASE            STM32_APB2PERIPH(0x0200UL)
-#define STM32_COMP2_BASE            STM32_APB2PERIPH(0x0204UL)
-#define STM32_COMP3_BASE            STM32_APB2PERIPH(0x0208UL)
-#define STM32_COMP4_BASE            STM32_APB2PERIPH(0x020CUL)
-#define STM32_OPAMP_BASE            STM32_APB2PERIPH(0x0300UL)
-#define STM32_OPAMP1_BASE           STM32_APB2PERIPH(0x0300UL)
-#define STM32_OPAMP2_BASE           STM32_APB2PERIPH(0x0304UL)
-#define STM32_OPAMP3_BASE           STM32_APB2PERIPH(0x0308UL)
-#define STM32_EXTI_BASE             STM32_APB2PERIPH(0x0400UL)
-#define STM32_TIM1_BASE             STM32_APB2PERIPH(0x2C00UL)
-#define STM32_SPI1_BASE             STM32_APB2PERIPH(0x3000UL)
-#define STM32_TIM8_BASE             STM32_APB2PERIPH(0x3400UL)
-#define STM32_USART1_BASE           STM32_APB2PERIPH(0x3800UL)
-#define STM32_TIM15_BASE            STM32_APB2PERIPH(0x4000UL)
-#define STM32_TIM16_BASE            STM32_APB2PERIPH(0x4400UL)
-#define STM32_TIM17_BASE            STM32_APB2PERIPH(0x4800UL)
-#define STM32_SAI1_BASE             STM32_APB2PERIPH(0x5400UL)
-#define STM32_SAI1_Block_A_BASE     (SAI1_BASE + 0x0004UL)
-#define STM32_SAI1_Block_B_BASE     (SAI1_BASE + 0x0024UL)
+#define STM32_APB2PERIPH(offset) (STM32_APB2PERIPH_BASE + offset)
+#define STM32_SYSCFG_BASE STM32_APB2PERIPH(0x0000UL)
+#define STM32_VREFBUF_BASE STM32_APB2PERIPH(0x0030UL)
+#define STM32_COMP1_BASE STM32_APB2PERIPH(0x0200UL)
+#define STM32_COMP2_BASE STM32_APB2PERIPH(0x0204UL)
+#define STM32_COMP3_BASE STM32_APB2PERIPH(0x0208UL)
+#define STM32_COMP4_BASE STM32_APB2PERIPH(0x020CUL)
+#define STM32_OPAMP_BASE STM32_APB2PERIPH(0x0300UL)
+#define STM32_OPAMP1_BASE STM32_APB2PERIPH(0x0300UL)
+#define STM32_OPAMP2_BASE STM32_APB2PERIPH(0x0304UL)
+#define STM32_OPAMP3_BASE STM32_APB2PERIPH(0x0308UL)
+#define STM32_EXTI_BASE STM32_APB2PERIPH(0x0400UL)
+#define STM32_TIM1_BASE STM32_APB2PERIPH(0x2C00UL)
+#define STM32_SPI1_BASE STM32_APB2PERIPH(0x3000UL)
+#define STM32_TIM8_BASE STM32_APB2PERIPH(0x3400UL)
+#define STM32_USART1_BASE STM32_APB2PERIPH(0x3800UL)
+#define STM32_TIM15_BASE STM32_APB2PERIPH(0x4000UL)
+#define STM32_TIM16_BASE STM32_APB2PERIPH(0x4400UL)
+#define STM32_TIM17_BASE STM32_APB2PERIPH(0x4800UL)
+#define STM32_SAI1_BASE STM32_APB2PERIPH(0x5400UL)
+#define STM32_SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL)
+#define STM32_SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL)
 
 /* AHB1 peripherals */
-#define STM32_AHB1PERIPH(offset)    (STM32_AHB1PERIPH_BASE + offset)
-#define STM32_DMA1_BASE             STM32_AHB1PERIPH(0x0000UL)
-#define STM32_DMA2_BASE             STM32_AHB1PERIPH(0x0400UL)
-#define STM32_DMAMUX_BASE           STM32_AHB1PERIPH(0x0800UL)
-#define STM32_CORDIC_BASE           STM32_AHB1PERIPH(0x0C00UL)
-#define STM32_RCC_BASE              STM32_AHB1PERIPH(0x1000UL)
-#define STM32_FMAC_BASE             STM32_AHB1PERIPH(0x1400UL)
-#define STM32_FLASH_REGS_BASE       STM32_AHB1PERIPH(0x2000UL)
-#define STM32_CRC_BASE              STM32_AHB1PERIPH(0x3000UL)
-
-#define STM32_DMA1_CHAN(offset)     (STM32_DMA1_BASE + offset)
-#define STM32_DMA1_Channel1_BASE    STM32_DMA1_CHAN(0x0008UL)
-#define STM32_DMA1_Channel2_BASE    STM32_DMA1_CHAN(0x001CUL)
-#define STM32_DMA1_Channel3_BASE    STM32_DMA1_CHAN(0x0030UL)
-#define STM32_DMA1_Channel4_BASE    STM32_DMA1_CHAN(0x0044UL)
-#define STM32_DMA1_Channel5_BASE    STM32_DMA1_CHAN(0x0058UL)
-#define STM32_DMA1_Channel6_BASE    STM32_DMA1_CHAN(0x006CUL)
-
-#define STM32_DMA2_CHAN(offset)     (STM32_DMA2_BASE + offset)
-#define STM32_DMA2_Channel1_BASE    STM32_DMA2_CHAN(0x0008UL)
-#define STM32_DMA2_Channel2_BASE    STM32_DMA2_CHAN(0x001CUL)
-#define STM32_DMA2_Channel3_BASE    STM32_DMA2_CHAN(0x0030UL)
-#define STM32_DMA2_Channel4_BASE    STM32_DMA2_CHAN(0x0044UL)
-#define STM32_DMA2_Channel5_BASE    STM32_DMA2_CHAN(0x0058UL)
-#define STM32_DMA2_Channel6_BASE    STM32_DMA2_CHAN(0x006CUL)
-
-#define STM32_DMAMUX(offset)          (STM32_DMAMUX_BASE + offset)
-#define STM32_DMAMUX_Channel0_BASE    STM32_DMAMUX(0x0000UL)
-#define STM32_DMAMUX_Channel1_BASE    STM32_DMAMUX(0x0004UL)
-#define STM32_DMAMUX_Channel2_BASE    STM32_DMAMUX(0x0008UL)
-#define STM32_DMAMUX_Channel3_BASE    STM32_DMAMUX(0x000CUL)
-#define STM32_DMAMUX_Channel4_BASE    STM32_DMAMUX(0x0010UL)
-#define STM32_DMAMUX_Channel5_BASE    STM32_DMAMUX(0x0014UL)
-#define STM32_DMAMUX_Channel6_BASE    STM32_DMAMUX(0x0020UL)
-#define STM32_DMAMUX_Channel7_BASE    STM32_DMAMUX(0x0024UL)
-#define STM32_DMAMUX_Channel8_BASE    STM32_DMAMUX(0x0028UL)
-#define STM32_DMAMUX_Channel9_BASE    STM32_DMAMUX(0x002CUL)
-#define STM32_DMAMUX_Channel10_BASE   STM32_DMAMUX(0x0030UL)
-#define STM32_DMAMUX_Channel11_BASE   STM32_DMAMUX(0x0034UL)
-#define STM32_DMAMUX_RequestGenerator0_BASE  STM32_DMAMUX(0x0100UL)
-#define STM32_DMAMUX_RequestGenerator1_BASE  STM32_DMAMUX(0x0104UL)
-#define STM32_DMAMUX_RequestGenerator2_BASE  STM32_DMAMUX(0x0108UL)
-#define STM32_DMAMUX_RequestGenerator3_BASE  STM32_DMAMUX(0x010CUL)
-#define STM32_DMAMUX_ChannelStatus_BASE      STM32_DMAMUX(0x0080UL)
-#define STM32_DMAMUX_RequestGenStatus_BASE   STM32_DMAMUX(0x0140UL)
+#define STM32_AHB1PERIPH(offset) (STM32_AHB1PERIPH_BASE + offset)
+#define STM32_DMA1_BASE STM32_AHB1PERIPH(0x0000UL)
+#define STM32_DMA2_BASE STM32_AHB1PERIPH(0x0400UL)
+#define STM32_DMAMUX_BASE STM32_AHB1PERIPH(0x0800UL)
+#define STM32_CORDIC_BASE STM32_AHB1PERIPH(0x0C00UL)
+#define STM32_RCC_BASE STM32_AHB1PERIPH(0x1000UL)
+#define STM32_FMAC_BASE STM32_AHB1PERIPH(0x1400UL)
+#define STM32_FLASH_REGS_BASE STM32_AHB1PERIPH(0x2000UL)
+#define STM32_CRC_BASE STM32_AHB1PERIPH(0x3000UL)
+
+#define STM32_DMA1_CHAN(offset) (STM32_DMA1_BASE + offset)
+#define STM32_DMA1_Channel1_BASE STM32_DMA1_CHAN(0x0008UL)
+#define STM32_DMA1_Channel2_BASE STM32_DMA1_CHAN(0x001CUL)
+#define STM32_DMA1_Channel3_BASE STM32_DMA1_CHAN(0x0030UL)
+#define STM32_DMA1_Channel4_BASE STM32_DMA1_CHAN(0x0044UL)
+#define STM32_DMA1_Channel5_BASE STM32_DMA1_CHAN(0x0058UL)
+#define STM32_DMA1_Channel6_BASE STM32_DMA1_CHAN(0x006CUL)
+
+#define STM32_DMA2_CHAN(offset) (STM32_DMA2_BASE + offset)
+#define STM32_DMA2_Channel1_BASE STM32_DMA2_CHAN(0x0008UL)
+#define STM32_DMA2_Channel2_BASE STM32_DMA2_CHAN(0x001CUL)
+#define STM32_DMA2_Channel3_BASE STM32_DMA2_CHAN(0x0030UL)
+#define STM32_DMA2_Channel4_BASE STM32_DMA2_CHAN(0x0044UL)
+#define STM32_DMA2_Channel5_BASE STM32_DMA2_CHAN(0x0058UL)
+#define STM32_DMA2_Channel6_BASE STM32_DMA2_CHAN(0x006CUL)
+
+#define STM32_DMAMUX(offset) (STM32_DMAMUX_BASE + offset)
+#define STM32_DMAMUX_Channel0_BASE STM32_DMAMUX(0x0000UL)
+#define STM32_DMAMUX_Channel1_BASE STM32_DMAMUX(0x0004UL)
+#define STM32_DMAMUX_Channel2_BASE STM32_DMAMUX(0x0008UL)
+#define STM32_DMAMUX_Channel3_BASE STM32_DMAMUX(0x000CUL)
+#define STM32_DMAMUX_Channel4_BASE STM32_DMAMUX(0x0010UL)
+#define STM32_DMAMUX_Channel5_BASE STM32_DMAMUX(0x0014UL)
+#define STM32_DMAMUX_Channel6_BASE STM32_DMAMUX(0x0020UL)
+#define STM32_DMAMUX_Channel7_BASE STM32_DMAMUX(0x0024UL)
+#define STM32_DMAMUX_Channel8_BASE STM32_DMAMUX(0x0028UL)
+#define STM32_DMAMUX_Channel9_BASE STM32_DMAMUX(0x002CUL)
+#define STM32_DMAMUX_Channel10_BASE STM32_DMAMUX(0x0030UL)
+#define STM32_DMAMUX_Channel11_BASE STM32_DMAMUX(0x0034UL)
+#define STM32_DMAMUX_RequestGenerator0_BASE STM32_DMAMUX(0x0100UL)
+#define STM32_DMAMUX_RequestGenerator1_BASE STM32_DMAMUX(0x0104UL)
+#define STM32_DMAMUX_RequestGenerator2_BASE STM32_DMAMUX(0x0108UL)
+#define STM32_DMAMUX_RequestGenerator3_BASE STM32_DMAMUX(0x010CUL)
+#define STM32_DMAMUX_ChannelStatus_BASE STM32_DMAMUX(0x0080UL)
+#define STM32_DMAMUX_RequestGenStatus_BASE STM32_DMAMUX(0x0140UL)
 
 /* AHB2 peripherals */
-#define STM32_AHB2PERIPH(offset)    (STM32_AHB2PERIPH_BASE + offset)
-#define STM32_GPIOA_BASE            STM32_AHB2PERIPH(0x0000UL)
-#define STM32_GPIOB_BASE            STM32_AHB2PERIPH(0x0400UL)
-#define STM32_GPIOC_BASE            STM32_AHB2PERIPH(0x0800UL)
-#define STM32_GPIOD_BASE            STM32_AHB2PERIPH(0x0C00UL)
-#define STM32_GPIOE_BASE            STM32_AHB2PERIPH(0x1000UL)
-#define STM32_GPIOF_BASE            STM32_AHB2PERIPH(0x1400UL)
-#define STM32_GPIOG_BASE            STM32_AHB2PERIPH(0x1800UL)
-#define STM32_ADC1_BASE             STM32_AHB2PERIPH(0x08000000UL)
-#define STM32_ADC2_BASE             STM32_AHB2PERIPH(0x08000100UL)
-#define STM32_ADC12_COMMON_BASE     STM32_AHB2PERIPH(0x08000300UL)
-#define STM32_DAC_BASE              STM32_AHB2PERIPH(0x08000800UL)
-#define STM32_DAC1_BASE             STM32_AHB2PERIPH(0x08000800UL)
-#define STM32_DAC3_BASE             STM32_AHB2PERIPH(0x08001000UL)
-#define STM32_RNG_BASE              STM32_AHB2PERIPH(0x08060800UL)
-
-#define STM32_UNIQUE_ID_BASE        0x1FFF7590
-#define STM32_DBGMCU_BASE           0xE0042000
+#define STM32_AHB2PERIPH(offset) (STM32_AHB2PERIPH_BASE + offset)
+#define STM32_GPIOA_BASE STM32_AHB2PERIPH(0x0000UL)
+#define STM32_GPIOB_BASE STM32_AHB2PERIPH(0x0400UL)
+#define STM32_GPIOC_BASE STM32_AHB2PERIPH(0x0800UL)
+#define STM32_GPIOD_BASE STM32_AHB2PERIPH(0x0C00UL)
+#define STM32_GPIOE_BASE STM32_AHB2PERIPH(0x1000UL)
+#define STM32_GPIOF_BASE STM32_AHB2PERIPH(0x1400UL)
+#define STM32_GPIOG_BASE STM32_AHB2PERIPH(0x1800UL)
+#define STM32_ADC1_BASE STM32_AHB2PERIPH(0x08000000UL)
+#define STM32_ADC2_BASE STM32_AHB2PERIPH(0x08000100UL)
+#define STM32_ADC12_COMMON_BASE STM32_AHB2PERIPH(0x08000300UL)
+#define STM32_DAC_BASE STM32_AHB2PERIPH(0x08000800UL)
+#define STM32_DAC1_BASE STM32_AHB2PERIPH(0x08000800UL)
+#define STM32_DAC3_BASE STM32_AHB2PERIPH(0x08001000UL)
+#define STM32_RNG_BASE STM32_AHB2PERIPH(0x08060800UL)
+
+#define STM32_UNIQUE_ID_BASE 0x1FFF7590
+#define STM32_DBGMCU_BASE 0xE0042000
 
 #ifndef __ASSEMBLER__
 
@@ -256,319 +256,299 @@
 
 /* --- UCPD --- */
 #define STM32_UCPD_REG(port, offset) \
-	REG32(((STM32_UCPD1_BASE + ((port) * 0x400)) + (offset)))
-
-#define STM32_UCPD_CFGR1(port)              STM32_UCPD_REG(port, 0x00)
-#define STM32_UCPD_CFGR2(port)              STM32_UCPD_REG(port, 0x04)
-#define STM32_UCPD_CR(port)                 STM32_UCPD_REG(port, 0x0c)
-#define STM32_UCPD_IMR(port)                STM32_UCPD_REG(port, 0x10)
-#define STM32_UCPD_SR(port)                 STM32_UCPD_REG(port, 0x14)
-#define STM32_UCPD_ICR(port)                STM32_UCPD_REG(port, 0x18)
-#define STM32_UCPD_TX_ORDSETR(port)         STM32_UCPD_REG(port, 0x1c)
-#define STM32_UCPD_TX_PAYSZR(port)          STM32_UCPD_REG(port, 0x20)
-#define STM32_UCPD_TXDR(port)               STM32_UCPD_REG(port, 0x24)
-#define STM32_UCPD_RX_ORDSETR(port)         STM32_UCPD_REG(port, 0x28)
-#define STM32_UCPD_RX_PAYSZR(port)          STM32_UCPD_REG(port, 0x2c)
-#define STM32_UCPD_RXDR(port)               STM32_UCPD_REG(port, 0x30)
-#define STM32_UCPD_RX_ORDEXTR1(port)        STM32_UCPD_REG(port, 0x34)
-#define STM32_UCPD_RX_ORDEXTR2(port)        STM32_UCPD_REG(port, 0x38)
+	REG32(((STM32_UCPD1_BASE + ((port)*0x400)) + (offset)))
+
+#define STM32_UCPD_CFGR1(port) STM32_UCPD_REG(port, 0x00)
+#define STM32_UCPD_CFGR2(port) STM32_UCPD_REG(port, 0x04)
+#define STM32_UCPD_CR(port) STM32_UCPD_REG(port, 0x0c)
+#define STM32_UCPD_IMR(port) STM32_UCPD_REG(port, 0x10)
+#define STM32_UCPD_SR(port) STM32_UCPD_REG(port, 0x14)
+#define STM32_UCPD_ICR(port) STM32_UCPD_REG(port, 0x18)
+#define STM32_UCPD_TX_ORDSETR(port) STM32_UCPD_REG(port, 0x1c)
+#define STM32_UCPD_TX_PAYSZR(port) STM32_UCPD_REG(port, 0x20)
+#define STM32_UCPD_TXDR(port) STM32_UCPD_REG(port, 0x24)
+#define STM32_UCPD_RX_ORDSETR(port) STM32_UCPD_REG(port, 0x28)
+#define STM32_UCPD_RX_PAYSZR(port) STM32_UCPD_REG(port, 0x2c)
+#define STM32_UCPD_RXDR(port) STM32_UCPD_REG(port, 0x30)
+#define STM32_UCPD_RX_ORDEXTR1(port) STM32_UCPD_REG(port, 0x34)
+#define STM32_UCPD_RX_ORDEXTR2(port) STM32_UCPD_REG(port, 0x38)
 
 /* --- UCPD CFGR1 Bit Definitions --- */
-#define STM32_UCPD_CFGR1_HBITCLKD_SHIFT     0
-#define STM32_UCPD_CFGR1_HBITCLKD_MASK      ((0x3f) << \
-					     (STM32_UCPD_CFGR1_HBITCLKD_SHIFT))
-#define STM32_UCPD_CFGR1_HBITCLKD_VAL(x)    ((x) << \
-					     STM32_UCPD_CFGR1_HBITCLKD_SHIFT)
-#define STM32_UCPD_CFGR1_IFRGAP_SHIFT       6
-#define STM32_UCPD_CFGR1_IFRGAP_MASK        ((0x1f) << \
-					     (STM32_UCPD_CFGR1_IFRGAP_SHIFT))
-#define STM32_UCPD_CFGR1_IFRGAP_VAL(x)      ((x) << \
-					     STM32_UCPD_CFGR1_IFRGAP_SHIFT)
-#define STM32_UCPD_CFGR1_TRANSWIN_SHIFT     11
-#define STM32_UCPD_CFGR1_TRANSWIN_MASK      ((0x1f) << \
-					     (STM32_UCPD_CFGR1_TRANSWIN_SHIFT))
-#define STM32_UCPD_CFGR1_TRANSWIN_VAL(x)    ((x) << \
-					     STM32_UCPD_CFGR1_TRANSWIN_SHIFT)
-#define STM32_UCPD_CFGR1_PSC_CLK_SHIFT      17
-#define STM32_UCPD_CFGR1_PSC_CLK_MASK       ((0x7) << \
-					     STM32_UCPD_CFGR1_PSC_CLK_SHIFT)
-#define STM32_UCPD_CFGR1_PSC_CLK_VAL(x)     ((x) << \
-					     STM32_UCPD_CFGR1_PSC_CLK_SHIFT)
-#define STM32_UCPD_CFGR1_RXORDSETEN_SHIFT   20
-#define STM32_UCPD_CFGR1_RXORDSETEN_MASK    ((0x1ff) << \
-					     STM32_UCPD_CFGR1_RXORDSETEN_SHIFT)
-#define STM32_UCPD_CFGR1_RXORDSETEN_VAL(x)  ((x) << \
-					     STM32_UCPD_CFGR1_RXORDSETEN_SHIFT)
-#define STM32_UCPD_CFGR1_TXDMAEN            BIT(29)
-#define STM32_UCPD_CFGR1_RXDMAEN            BIT(30)
-#define STM32_UCPD_CFGR1_UCPDEN             BIT(31)
+#define STM32_UCPD_CFGR1_HBITCLKD_SHIFT 0
+#define STM32_UCPD_CFGR1_HBITCLKD_MASK \
+	((0x3f) << (STM32_UCPD_CFGR1_HBITCLKD_SHIFT))
+#define STM32_UCPD_CFGR1_HBITCLKD_VAL(x) \
+	((x) << STM32_UCPD_CFGR1_HBITCLKD_SHIFT)
+#define STM32_UCPD_CFGR1_IFRGAP_SHIFT 6
+#define STM32_UCPD_CFGR1_IFRGAP_MASK ((0x1f) << (STM32_UCPD_CFGR1_IFRGAP_SHIFT))
+#define STM32_UCPD_CFGR1_IFRGAP_VAL(x) ((x) << STM32_UCPD_CFGR1_IFRGAP_SHIFT)
+#define STM32_UCPD_CFGR1_TRANSWIN_SHIFT 11
+#define STM32_UCPD_CFGR1_TRANSWIN_MASK \
+	((0x1f) << (STM32_UCPD_CFGR1_TRANSWIN_SHIFT))
+#define STM32_UCPD_CFGR1_TRANSWIN_VAL(x) \
+	((x) << STM32_UCPD_CFGR1_TRANSWIN_SHIFT)
+#define STM32_UCPD_CFGR1_PSC_CLK_SHIFT 17
+#define STM32_UCPD_CFGR1_PSC_CLK_MASK ((0x7) << STM32_UCPD_CFGR1_PSC_CLK_SHIFT)
+#define STM32_UCPD_CFGR1_PSC_CLK_VAL(x) ((x) << STM32_UCPD_CFGR1_PSC_CLK_SHIFT)
+#define STM32_UCPD_CFGR1_RXORDSETEN_SHIFT 20
+#define STM32_UCPD_CFGR1_RXORDSETEN_MASK \
+	((0x1ff) << STM32_UCPD_CFGR1_RXORDSETEN_SHIFT)
+#define STM32_UCPD_CFGR1_RXORDSETEN_VAL(x) \
+	((x) << STM32_UCPD_CFGR1_RXORDSETEN_SHIFT)
+#define STM32_UCPD_CFGR1_TXDMAEN BIT(29)
+#define STM32_UCPD_CFGR1_RXDMAEN BIT(30)
+#define STM32_UCPD_CFGR1_UCPDEN BIT(31)
 
 /* --- UCPD CFGR2 Bit Definitions --- */
-#define STM32_UCPD_CFGR2_RXFILTDIS          BIT(0)
-#define STM32_UCPD_CFGR2_RXFILT2N3          BIT(1)
-#define STM32_UCPD_CFGR2_FORCECLK           BIT(2)
-#define STM32_UCPD_CFGR2_WUPEN              BIT(3)
+#define STM32_UCPD_CFGR2_RXFILTDIS BIT(0)
+#define STM32_UCPD_CFGR2_RXFILT2N3 BIT(1)
+#define STM32_UCPD_CFGR2_FORCECLK BIT(2)
+#define STM32_UCPD_CFGR2_WUPEN BIT(3)
 
 /* --- UCPD CR Bit Definitions --- */
-#define STM32_UCPD_CR_TXMODE_SHIFT          0
-#define STM32_UCPD_CR_TXMODE_MASK           ((0x3) << \
-					     (STM32_UCPD_CR_TXMODE_SHIFT))
-#define STM32_UCPD_CR_TXMODE_VAL(x)         ((x) << STM32_UCPD_CR_TXMODE_SHIFT)
-#define STM32_UCPD_CR_TXSEND                BIT(2)
-#define STM32_UCPD_CR_TXHRST                BIT(3)
-#define STM32_UCPD_CR_RXMODE                BIT(4)
-#define STM32_UCPD_CR_PHYRXEN               BIT(5)
-#define STM32_UCPD_CR_PHYCCSEL              BIT(6)
-#define STM32_UCPD_CR_ANASUBMODE_SHIFT      7
-#define STM32_UCPD_CR_ANASUBMODE_MASK       ((0x3) << \
-					     (STM32_UCPD_CR_ANASUBMODE_SHIFT))
-#define STM32_UCPD_CR_ANASUBMODE_VAL(x)     ((x) << \
-					     STM32_UCPD_CR_ANASUBMODE_SHIFT)
-#define STM32_UCPD_CR_ANAMODE               BIT(9)
-#define STM32_UCPD_CR_CCENABLE_SHIFT        10
-#define STM32_UCPD_CR_CCENABLE_MASK         ((0x3) << \
-					     (STM32_UCPD_CR_CCENABLE_SHIFT))
-#define STM32_UCPD_CR_CCENABLE_VAL(x)       ((x) << \
-					     STM32_UCPD_CR_CCENABLE_SHIFT)
-#define STM32_UCPD_CR_FRSRXEN               BIT(16)
-#define STM32_UCPD_CR_FRSTX                 BIT(17)
-#define STM32_UCPD_CR_RDCH                  BIT(18)
-#define STM32_UCPD_CR_CC1TCDIS              BIT(20)
-#define STM32_UCPD_CR_CC2TCDIS              BIT(21)
+#define STM32_UCPD_CR_TXMODE_SHIFT 0
+#define STM32_UCPD_CR_TXMODE_MASK ((0x3) << (STM32_UCPD_CR_TXMODE_SHIFT))
+#define STM32_UCPD_CR_TXMODE_VAL(x) ((x) << STM32_UCPD_CR_TXMODE_SHIFT)
+#define STM32_UCPD_CR_TXSEND BIT(2)
+#define STM32_UCPD_CR_TXHRST BIT(3)
+#define STM32_UCPD_CR_RXMODE BIT(4)
+#define STM32_UCPD_CR_PHYRXEN BIT(5)
+#define STM32_UCPD_CR_PHYCCSEL BIT(6)
+#define STM32_UCPD_CR_ANASUBMODE_SHIFT 7
+#define STM32_UCPD_CR_ANASUBMODE_MASK \
+	((0x3) << (STM32_UCPD_CR_ANASUBMODE_SHIFT))
+#define STM32_UCPD_CR_ANASUBMODE_VAL(x) ((x) << STM32_UCPD_CR_ANASUBMODE_SHIFT)
+#define STM32_UCPD_CR_ANAMODE BIT(9)
+#define STM32_UCPD_CR_CCENABLE_SHIFT 10
+#define STM32_UCPD_CR_CCENABLE_MASK ((0x3) << (STM32_UCPD_CR_CCENABLE_SHIFT))
+#define STM32_UCPD_CR_CCENABLE_VAL(x) ((x) << STM32_UCPD_CR_CCENABLE_SHIFT)
+#define STM32_UCPD_CR_FRSRXEN BIT(16)
+#define STM32_UCPD_CR_FRSTX BIT(17)
+#define STM32_UCPD_CR_RDCH BIT(18)
+#define STM32_UCPD_CR_CC1TCDIS BIT(20)
+#define STM32_UCPD_CR_CC2TCDIS BIT(21)
 
 /* TX mode message types */
-#define STM32_UCPD_CR_TXMODE_DEF            0
-#define STM32_UCPD_CR_TXMODE_CBL_RST        1
-#define STM32_UCPD_CR_TXMODE_BIST           2
+#define STM32_UCPD_CR_TXMODE_DEF 0
+#define STM32_UCPD_CR_TXMODE_CBL_RST 1
+#define STM32_UCPD_CR_TXMODE_BIST 2
 
 /* --- UCPD IMR Bit Definitions --- */
-#define STM32_UCPD_IMR_TXISIE               BIT(0)
-#define STM32_UCPD_IMR_TXMSGDISCIE          BIT(1)
-#define STM32_UCPD_IMR_TXMSGSENTIE          BIT(2)
-#define STM32_UCPD_IMR_TXMSGABTIE           BIT(3)
-#define STM32_UCPD_IMR_HRSTDISCIE           BIT(4)
-#define STM32_UCPD_IMR_HRSTSENTIE           BIT(5)
-#define STM32_UCPD_IMR_TXUNDIE              BIT(6)
-#define STM32_UCPD_IMR_RXNEIE               BIT(8)
-#define STM32_UCPD_IMR_RXORDDETIE           BIT(9)
-#define STM32_UCPD_IMR_RXHRSTDETIE          BIT(10)
-#define STM32_UCPD_IMR_RXOVRIE              BIT(11)
-#define STM32_UCPD_IMR_RXMSGENDIE           BIT(12)
-#define STM32_UCPD_IMR_TYPECEVT1IE          BIT(14)
-#define STM32_UCPD_IMR_TYPECEVT2IE          BIT(15)
-#define STM32_UCPD_IMR_FRSEVTIE             BIT(20)
+#define STM32_UCPD_IMR_TXISIE BIT(0)
+#define STM32_UCPD_IMR_TXMSGDISCIE BIT(1)
+#define STM32_UCPD_IMR_TXMSGSENTIE BIT(2)
+#define STM32_UCPD_IMR_TXMSGABTIE BIT(3)
+#define STM32_UCPD_IMR_HRSTDISCIE BIT(4)
+#define STM32_UCPD_IMR_HRSTSENTIE BIT(5)
+#define STM32_UCPD_IMR_TXUNDIE BIT(6)
+#define STM32_UCPD_IMR_RXNEIE BIT(8)
+#define STM32_UCPD_IMR_RXORDDETIE BIT(9)
+#define STM32_UCPD_IMR_RXHRSTDETIE BIT(10)
+#define STM32_UCPD_IMR_RXOVRIE BIT(11)
+#define STM32_UCPD_IMR_RXMSGENDIE BIT(12)
+#define STM32_UCPD_IMR_TYPECEVT1IE BIT(14)
+#define STM32_UCPD_IMR_TYPECEVT2IE BIT(15)
+#define STM32_UCPD_IMR_FRSEVTIE BIT(20)
 
 /* --- UCPD SR Bit Definitions --- */
-#define STM32_UCPD_SR_TXIS                  BIT(0)
-#define STM32_UCPD_SR_TXMSGDISC             BIT(1)
-#define STM32_UCPD_SR_TXMSGSENT             BIT(2)
-#define STM32_UCPD_SR_TXMSGABT              BIT(3)
-#define STM32_UCPD_SR_HRSTDISC              BIT(4)
-#define STM32_UCPD_SR_HRSTSENT              BIT(5)
-#define STM32_UCPD_SR_TXUND                 BIT(6)
-#define STM32_UCPD_SR_RXNE                  BIT(8)
-#define STM32_UCPD_SR_RXORDDET              BIT(9)
-#define STM32_UCPD_SR_RXHRSTDET             BIT(10)
-#define STM32_UCPD_SR_RXOVR                 BIT(11)
-#define STM32_UCPD_SR_RXMSGEND              BIT(12)
-#define STM32_UCPD_SR_RXERR                 BIT(13)
-#define STM32_UCPD_SR_TYPECEVT1             BIT(14)
-#define STM32_UCPD_SR_TYPECEVT2             BIT(15)
-#define STM32_UCPD_SR_VSTATE_CC1_SHIFT      16
-#define STM32_UCPD_SR_VSTATE_CC1_MASK       ((0x3) << \
-					       (STM32_UCPD_SR_VSTATE_CC1_SHIFT))
-#define STM32_UCPD_SR_VSTATE_CC1_VAL(x)     ((x) << \
-					     STM32_UCPD_SR_VSTATE_CC1_SHIFT)
-#define STM32_UCPD_SR_VSTATE_CC2_SHIFT      18
-#define STM32_UCPD_SR_VSTATE_CC2_MASK       ((0x3) << \
-					     (STM32_UCPD_SR_VSTATE_CC2_SHIFT))
-#define STM32_UCPD_SR_VSTATE_CC2_VAL(x)     ((x) << \
-					     STM32_UCPD_SR_VSTATE_CC2_SHIFT)
-#define STM32_UCPD_SR_FRSEVT                BIT(20)
-
-#define STM32_UCPD_SR_VSTATE_OPEN           3
-#define STM32_UCPD_SR_VSTATE_RA             0
+#define STM32_UCPD_SR_TXIS BIT(0)
+#define STM32_UCPD_SR_TXMSGDISC BIT(1)
+#define STM32_UCPD_SR_TXMSGSENT BIT(2)
+#define STM32_UCPD_SR_TXMSGABT BIT(3)
+#define STM32_UCPD_SR_HRSTDISC BIT(4)
+#define STM32_UCPD_SR_HRSTSENT BIT(5)
+#define STM32_UCPD_SR_TXUND BIT(6)
+#define STM32_UCPD_SR_RXNE BIT(8)
+#define STM32_UCPD_SR_RXORDDET BIT(9)
+#define STM32_UCPD_SR_RXHRSTDET BIT(10)
+#define STM32_UCPD_SR_RXOVR BIT(11)
+#define STM32_UCPD_SR_RXMSGEND BIT(12)
+#define STM32_UCPD_SR_RXERR BIT(13)
+#define STM32_UCPD_SR_TYPECEVT1 BIT(14)
+#define STM32_UCPD_SR_TYPECEVT2 BIT(15)
+#define STM32_UCPD_SR_VSTATE_CC1_SHIFT 16
+#define STM32_UCPD_SR_VSTATE_CC1_MASK \
+	((0x3) << (STM32_UCPD_SR_VSTATE_CC1_SHIFT))
+#define STM32_UCPD_SR_VSTATE_CC1_VAL(x) ((x) << STM32_UCPD_SR_VSTATE_CC1_SHIFT)
+#define STM32_UCPD_SR_VSTATE_CC2_SHIFT 18
+#define STM32_UCPD_SR_VSTATE_CC2_MASK \
+	((0x3) << (STM32_UCPD_SR_VSTATE_CC2_SHIFT))
+#define STM32_UCPD_SR_VSTATE_CC2_VAL(x) ((x) << STM32_UCPD_SR_VSTATE_CC2_SHIFT)
+#define STM32_UCPD_SR_FRSEVT BIT(20)
+
+#define STM32_UCPD_SR_VSTATE_OPEN 3
+#define STM32_UCPD_SR_VSTATE_RA 0
 
 /* --- UCPD ICR Bit Definitions --- */
-#define STM32_UCPD_ICR_TXMSGDISCCF          BIT(1)
-#define STM32_UCPD_ICR_TXMSGSENTCF          BIT(2)
-#define STM32_UCPD_ICR_TXMSGABTCF           BIT(3)
-#define STM32_UCPD_ICR_HRSTDISCCF           BIT(4)
-#define STM32_UCPD_ICR_HRSTSENTCF           BIT(5)
-#define STM32_UCPD_ICR_TXUNDCF              BIT(6)
-#define STM32_UCPD_ICR_RXORDDETCF           BIT(9)
-#define STM32_UCPD_ICR_RXHRSTDETCF          BIT(10)
-#define STM32_UCPD_ICR_RXOVRCF              BIT(11)
-#define STM32_UCPD_ICR_RXMSGENDCF           BIT(12)
-#define STM32_UCPD_ICR_TYPECEVT1CF          BIT(14)
-#define STM32_UCPD_ICR_TYPECEVT2CF          BIT(15)
-#define STM32_UCPD_ICR_FRSEVTCF             BIT(20)
-
+#define STM32_UCPD_ICR_TXMSGDISCCF BIT(1)
+#define STM32_UCPD_ICR_TXMSGSENTCF BIT(2)
+#define STM32_UCPD_ICR_TXMSGABTCF BIT(3)
+#define STM32_UCPD_ICR_HRSTDISCCF BIT(4)
+#define STM32_UCPD_ICR_HRSTSENTCF BIT(5)
+#define STM32_UCPD_ICR_TXUNDCF BIT(6)
+#define STM32_UCPD_ICR_RXORDDETCF BIT(9)
+#define STM32_UCPD_ICR_RXHRSTDETCF BIT(10)
+#define STM32_UCPD_ICR_RXOVRCF BIT(11)
+#define STM32_UCPD_ICR_RXMSGENDCF BIT(12)
+#define STM32_UCPD_ICR_TYPECEVT1CF BIT(14)
+#define STM32_UCPD_ICR_TYPECEVT2CF BIT(15)
+#define STM32_UCPD_ICR_FRSEVTCF BIT(20)
 
 /* --- UCPD TX_ORDSETR Bit Definitions --- */
-#define STM32_UCPD_TX_ORDSETR_SHIFT        0
-#define STM32_UCPD_TX_ORDSETR_MASK         ((0xfffff) << \
-					    (STM32_UCPD_TX_ORDSETR_SHIFT))
-#define STM32_UCPD_TX_ORDSETR_VAL(x)       ((x) << STM32_UCPD_TX_ORDSETR_SHIFT)
+#define STM32_UCPD_TX_ORDSETR_SHIFT 0
+#define STM32_UCPD_TX_ORDSETR_MASK ((0xfffff) << (STM32_UCPD_TX_ORDSETR_SHIFT))
+#define STM32_UCPD_TX_ORDSETR_VAL(x) ((x) << STM32_UCPD_TX_ORDSETR_SHIFT)
 
 /* --- UCPD TX_PAYSZR Bit Definitions --- */
-#define STM32_UCPD_TX_PAYSZR_SHIFT        0
-#define STM32_UCPD_TX_PAYSZR_MASK         ((0x3ff) << \
-					   (STM32_UCPD_TX_PAYSZR_SHIFT))
-#define STM32_UCPD_TX_PAYSZR_VAL(x)       ((x) << STM32_UCPD_TX_PAYSZR_SHIFT)
+#define STM32_UCPD_TX_PAYSZR_SHIFT 0
+#define STM32_UCPD_TX_PAYSZR_MASK ((0x3ff) << (STM32_UCPD_TX_PAYSZR_SHIFT))
+#define STM32_UCPD_TX_PAYSZR_VAL(x) ((x) << STM32_UCPD_TX_PAYSZR_SHIFT)
 
 /* --- UCPD TXDR Bit Definitions --- */
-#define STM32_UCPD_TXDR_SHIFT             0
-#define STM32_UCPD_TXDR_MASK              ((0xff) << \
-					   (STM32_UCPD_TXDR_SHIFT))
-#define STM32_UCPD_TXDR_VAL(x)            ((x) << STM32_UCPD_TXDR_SHIFT)
+#define STM32_UCPD_TXDR_SHIFT 0
+#define STM32_UCPD_TXDR_MASK ((0xff) << (STM32_UCPD_TXDR_SHIFT))
+#define STM32_UCPD_TXDR_VAL(x) ((x) << STM32_UCPD_TXDR_SHIFT)
 
 /* --- UCPD RX_ORDSETR Bit Definitions --- */
-#define STM32_UCPD_RXORDSETR_SHIFT        0
-#define STM32_UCPD_RXORDSETR_MASK         ((0x7) << \
-					   (STM32_UCPD_RXORDSETR_SHIFT))
-#define STM32_UCPD_RXORDSETR_VAL(x)       ((x) << STM32_UCPD_RXORDSETR_SHIFT)
-#define STM32_UCPD_RXSOP3OF4              BIT(3)
-#define STM32_UCPD_RXSOPKINVALID_SHIFT    4
-#define STM32_UCPD_RXSOPKINVALID_MASK     ((0x7) << \
-					   (STM32_UCPD_RXSOPKINVALID_SHIFT))
-#define STM32_UCPD_RXSOPKINVALID_VAL(x)   ((x) << \
-					   STM32_UCPD_RXSOPKINVALID_SHIFT)
+#define STM32_UCPD_RXORDSETR_SHIFT 0
+#define STM32_UCPD_RXORDSETR_MASK ((0x7) << (STM32_UCPD_RXORDSETR_SHIFT))
+#define STM32_UCPD_RXORDSETR_VAL(x) ((x) << STM32_UCPD_RXORDSETR_SHIFT)
+#define STM32_UCPD_RXSOP3OF4 BIT(3)
+#define STM32_UCPD_RXSOPKINVALID_SHIFT 4
+#define STM32_UCPD_RXSOPKINVALID_MASK \
+	((0x7) << (STM32_UCPD_RXSOPKINVALID_SHIFT))
+#define STM32_UCPD_RXSOPKINVALID_VAL(x) ((x) << STM32_UCPD_RXSOPKINVALID_SHIFT)
 
 /* --- UCPD RX_PAYSZR Bit Definitions --- */
-#define STM32_UCPD_RX_PAYSZR_SHIFT        0
-#define STM32_UCPD_RX_PAYSZR_MASK         ((0x3ff) << \
-					   (STM32_UCPD_RX_PAYSZR_SHIFT))
-#define STM32_UCPD_RX_PAYSZR_VAL(x)       ((x) << STM32_UCPD_RX_PAYSZR_SHIFT)
+#define STM32_UCPD_RX_PAYSZR_SHIFT 0
+#define STM32_UCPD_RX_PAYSZR_MASK ((0x3ff) << (STM32_UCPD_RX_PAYSZR_SHIFT))
+#define STM32_UCPD_RX_PAYSZR_VAL(x) ((x) << STM32_UCPD_RX_PAYSZR_SHIFT)
 
 /* --- UCPD TXDR Bit Definitions --- */
-#define STM32_UCPD_RXDR_SHIFT             0
-#define STM32_UCPD_RXDR_MASK              ((0xff) << \
-					   (STM32_UCPD_RXDR_SHIFT))
-#define STM32_UCPD_RXDR_VAL(x)            ((x) << STM32_UCPD_RXDR_SHIFT)
-
+#define STM32_UCPD_RXDR_SHIFT 0
+#define STM32_UCPD_RXDR_MASK ((0xff) << (STM32_UCPD_RXDR_SHIFT))
+#define STM32_UCPD_RXDR_VAL(x) ((x) << STM32_UCPD_RXDR_SHIFT)
 
 /* --- USART --- */
-#define STM32_USART_CR1(base)      STM32_USART_REG(base, 0x00)
-#define STM32_USART_CR2(base)      STM32_USART_REG(base, 0x04)
-#define STM32_USART_CR3(base)      STM32_USART_REG(base, 0x08)
-#define STM32_USART_BRR(base)      STM32_USART_REG(base, 0x0C)
-#define STM32_USART_GTPR(base)     STM32_USART_REG(base, 0x10)
-#define STM32_USART_SR(base)       STM32_USART_REG(base, 0x1C)
-#define STM32_USART_RDR(base)      STM32_USART_REG(base, 0x24)
-#define STM32_USART_TDR(base)      STM32_USART_REG(base, 0x28)
+#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00)
+#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04)
+#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08)
+#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C)
+#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10)
+#define STM32_USART_SR(base) STM32_USART_REG(base, 0x1C)
+#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24)
+#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28)
 
 /* --- USART bit definitions -- */
-#define STM32_USART_SR_ORE		BIT(3)
-#define STM32_USART_SR_RXNE		BIT(5)
-#define STM32_USART_SR_TC		BIT(6)
-#define STM32_USART_SR_TXE		BIT(7)
-
-#define STM32_USART_CR1_UE		BIT(0)
-#define STM32_USART_CR1_RE		BIT(2)
-#define STM32_USART_CR1_TE		BIT(3)
-#define STM32_USART_CR1_RXNEIE		BIT(5)
-#define STM32_USART_CR1_TCIE		BIT(6)
-#define STM32_USART_CR1_TXEIE		BIT(7)
-#define STM32_USART_CR1_PS		BIT(9)
-#define STM32_USART_CR1_PCE		BIT(10)
-#define STM32_USART_CR1_M		BIT(12)
-#define STM32_USART_CR1_OVER8		BIT(15)
-
-#define STM32_USART_CR3_EIE		BIT(0)
-#define STM32_USART_CR3_DMAR		BIT(6)
-#define STM32_USART_CR3_DMAT		BIT(7)
-#define STM32_USART_CR3_ONEBIT		BIT(11)
-
+#define STM32_USART_SR_ORE BIT(3)
+#define STM32_USART_SR_RXNE BIT(5)
+#define STM32_USART_SR_TC BIT(6)
+#define STM32_USART_SR_TXE BIT(7)
+
+#define STM32_USART_CR1_UE BIT(0)
+#define STM32_USART_CR1_RE BIT(2)
+#define STM32_USART_CR1_TE BIT(3)
+#define STM32_USART_CR1_RXNEIE BIT(5)
+#define STM32_USART_CR1_TCIE BIT(6)
+#define STM32_USART_CR1_TXEIE BIT(7)
+#define STM32_USART_CR1_PS BIT(9)
+#define STM32_USART_CR1_PCE BIT(10)
+#define STM32_USART_CR1_M BIT(12)
+#define STM32_USART_CR1_OVER8 BIT(15)
+
+#define STM32_USART_CR3_EIE BIT(0)
+#define STM32_USART_CR3_DMAR BIT(6)
+#define STM32_USART_CR3_DMAT BIT(7)
+#define STM32_USART_CR3_ONEBIT BIT(11)
 
 /* --- GPIO --- */
-#define STM32_GPIO_MODER(b)     REG32((b) + 0x00)
-#define STM32_GPIO_OTYPER(b)    REG16((b) + 0x04)
-#define STM32_GPIO_OSPEEDR(b)   REG32((b) + 0x08)
-#define STM32_GPIO_PUPDR(b)     REG32((b) + 0x0C)
-#define STM32_GPIO_IDR(b)       REG16((b) + 0x10)
-#define STM32_GPIO_ODR(b)       REG16((b) + 0x14)
-#define STM32_GPIO_BSRR(b)      REG32((b) + 0x18)
-#define STM32_GPIO_LCKR(b)      REG32((b) + 0x1C)
-#define STM32_GPIO_AFRL(b)      REG32((b) + 0x20)
-#define STM32_GPIO_AFRH(b)      REG32((b) + 0x24)
-
-#define GPIO_ALT_SYS                 0x0
-#define GPIO_ALT_TIM2                0x1
-#define GPIO_ALT_I2C3                0x2
-#define GPIO_ALT_TIM9_11             0x3
-#define GPIO_ALT_I2C                 0x4
-#define GPIO_ALT_SPI                 0x5
-#define GPIO_ALT_SPI3                0x6
-#define GPIO_ALT_USART               0x7
-#define GPIO_ALT_I2C_23              0x9
-#define GPIO_ALT_USB                 0xA
-#define GPIO_ALT_LCD                 0xB
-#define GPIO_ALT_LPUART              0xC
-#define GPIO_ALT_SAI1                0xD
-#define GPIO_ALT_RI                  0xE
-#define GPIO_ALT_EVENTOUT            0xF
+#define STM32_GPIO_MODER(b) REG32((b) + 0x00)
+#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04)
+#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08)
+#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C)
+#define STM32_GPIO_IDR(b) REG16((b) + 0x10)
+#define STM32_GPIO_ODR(b) REG16((b) + 0x14)
+#define STM32_GPIO_BSRR(b) REG32((b) + 0x18)
+#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C)
+#define STM32_GPIO_AFRL(b) REG32((b) + 0x20)
+#define STM32_GPIO_AFRH(b) REG32((b) + 0x24)
+
+#define GPIO_ALT_SYS 0x0
+#define GPIO_ALT_TIM2 0x1
+#define GPIO_ALT_I2C3 0x2
+#define GPIO_ALT_TIM9_11 0x3
+#define GPIO_ALT_I2C 0x4
+#define GPIO_ALT_SPI 0x5
+#define GPIO_ALT_SPI3 0x6
+#define GPIO_ALT_USART 0x7
+#define GPIO_ALT_I2C_23 0x9
+#define GPIO_ALT_USB 0xA
+#define GPIO_ALT_LCD 0xB
+#define GPIO_ALT_LPUART 0xC
+#define GPIO_ALT_SAI1 0xD
+#define GPIO_ALT_RI 0xE
+#define GPIO_ALT_EVENTOUT 0xF
 
 /* --- I2C --- */
 #define stm32g4_i2c_reg(base, offset) ((uint16_t *)((base) + (offset)))
 
-#define STM32_I2C_CR1(base)            REG32(stm32g4_i2c_reg(base, 0x00))
-#define STM32_I2C_CR2(base)            REG32(stm32g4_i2c_reg(base, 0x04))
-#define STM32_I2C_OAR1(base)           REG16(stm32g4_i2c_reg(base, 0x08))
-#define STM32_I2C_OAR2(base)           REG16(stm32g4_i2c_reg(base, 0x0C))
-#define STM32_I2C_TIMINGR(base)        REG32(stm32g4_i2c_reg(base, 0x10))
-#define STM32_I2C_TIMEOUTR(base)       REG32(stm32g4_i2c_reg(base, 0x14))
-#define STM32_I2C_ISR(base)            REG32(stm32g4_i2c_reg(base, 0x18))
-#define STM32_I2C_ICR(base)            REG32(stm32g4_i2c_reg(base, 0x1C))
-#define STM32_I2C_PECR(base)           REG32(stm32g4_i2c_reg(base, 0x20))
-#define STM32_I2C_RXDR(base)           REG32(stm32g4_i2c_reg(base, 0x24))
-#define STM32_I2C_TXDR(base)           REG32(stm32g4_i2c_reg(base, 0x28))
+#define STM32_I2C_CR1(base) REG32(stm32g4_i2c_reg(base, 0x00))
+#define STM32_I2C_CR2(base) REG32(stm32g4_i2c_reg(base, 0x04))
+#define STM32_I2C_OAR1(base) REG16(stm32g4_i2c_reg(base, 0x08))
+#define STM32_I2C_OAR2(base) REG16(stm32g4_i2c_reg(base, 0x0C))
+#define STM32_I2C_TIMINGR(base) REG32(stm32g4_i2c_reg(base, 0x10))
+#define STM32_I2C_TIMEOUTR(base) REG32(stm32g4_i2c_reg(base, 0x14))
+#define STM32_I2C_ISR(base) REG32(stm32g4_i2c_reg(base, 0x18))
+#define STM32_I2C_ICR(base) REG32(stm32g4_i2c_reg(base, 0x1C))
+#define STM32_I2C_PECR(base) REG32(stm32g4_i2c_reg(base, 0x20))
+#define STM32_I2C_RXDR(base) REG32(stm32g4_i2c_reg(base, 0x24))
+#define STM32_I2C_TXDR(base) REG32(stm32g4_i2c_reg(base, 0x28))
 
 /* --- I2C CR1 Bit Definitions --- */
-#define STM32_I2C_CR1_PE            BIT(0)
-#define STM32_I2C_CR1_TXIE          BIT(1)
-#define STM32_I2C_CR1_RXIE          BIT(2)
-#define STM32_I2C_CR1_ADDRIE        BIT(3)
-#define STM32_I2C_CR1_NACKIE        BIT(4)
-#define STM32_I2C_CR1_STOPIE        BIT(5)
-#define STM32_I2C_CR1_ERRIE         BIT(7)
-#define STM32_I2C_CR1_WUPEN         BIT(18)
+#define STM32_I2C_CR1_PE BIT(0)
+#define STM32_I2C_CR1_TXIE BIT(1)
+#define STM32_I2C_CR1_RXIE BIT(2)
+#define STM32_I2C_CR1_ADDRIE BIT(3)
+#define STM32_I2C_CR1_NACKIE BIT(4)
+#define STM32_I2C_CR1_STOPIE BIT(5)
+#define STM32_I2C_CR1_ERRIE BIT(7)
+#define STM32_I2C_CR1_WUPEN BIT(18)
 
 /* --- I2C CR2 Bit Definitions --- */
-#define STM32_I2C_CR2_RD_WRN        BIT(10)
-#define STM32_I2C_CR2_START         BIT(13)
-#define STM32_I2C_CR2_STOP          BIT(14)
-#define STM32_I2C_CR2_NACK          BIT(15)
-#define STM32_I2C_CR2_RELOAD        BIT(24)
-#define STM32_I2C_CR2_AUTOEND       BIT(25)
+#define STM32_I2C_CR2_RD_WRN BIT(10)
+#define STM32_I2C_CR2_START BIT(13)
+#define STM32_I2C_CR2_STOP BIT(14)
+#define STM32_I2C_CR2_NACK BIT(15)
+#define STM32_I2C_CR2_RELOAD BIT(24)
+#define STM32_I2C_CR2_AUTOEND BIT(25)
 
 /* --- I2C ISR Bit Definitions --- */
-#define STM32_I2C_ISR_TXE           BIT(0)
-#define STM32_I2C_ISR_TXIS          BIT(1)
-#define STM32_I2C_ISR_RXNE          BIT(2)
-#define STM32_I2C_ISR_ADDR          BIT(3)
-#define STM32_I2C_ISR_NACK          BIT(4)
-#define STM32_I2C_ISR_STOP          BIT(5)
-#define STM32_I2C_ISR_TC            BIT(6)
-#define STM32_I2C_ISR_TCR           BIT(7)
-#define STM32_I2C_ISR_BERR          BIT(8)
-#define STM32_I2C_ISR_ARLO          BIT(9)
-#define STM32_I2C_ISR_OVR           BIT(10)
-#define STM32_I2C_ISR_PECERR        BIT(11)
-#define STM32_I2C_ISR_TIMEOUT       BIT(12)
-#define STM32_I2C_ISR_ALERT         BIT(13)
-#define STM32_I2C_ISR_BUSY          BIT(15)
-#define STM32_I2C_ISR_DIR           BIT(16)
+#define STM32_I2C_ISR_TXE BIT(0)
+#define STM32_I2C_ISR_TXIS BIT(1)
+#define STM32_I2C_ISR_RXNE BIT(2)
+#define STM32_I2C_ISR_ADDR BIT(3)
+#define STM32_I2C_ISR_NACK BIT(4)
+#define STM32_I2C_ISR_STOP BIT(5)
+#define STM32_I2C_ISR_TC BIT(6)
+#define STM32_I2C_ISR_TCR BIT(7)
+#define STM32_I2C_ISR_BERR BIT(8)
+#define STM32_I2C_ISR_ARLO BIT(9)
+#define STM32_I2C_ISR_OVR BIT(10)
+#define STM32_I2C_ISR_PECERR BIT(11)
+#define STM32_I2C_ISR_TIMEOUT BIT(12)
+#define STM32_I2C_ISR_ALERT BIT(13)
+#define STM32_I2C_ISR_BUSY BIT(15)
+#define STM32_I2C_ISR_DIR BIT(16)
 
 /* --- I2C ICR Bit Definitions --- */
-#define STM32_I2C_ICR_ADDRCF        BIT(3)
-#define STM32_I2C_ICR_NACKCF        BIT(4)
-#define STM32_I2C_ICR_STOPCF        BIT(5)
-#define STM32_I2C_ICR_BERRCF        BIT(8)
-#define STM32_I2C_ICR_ARLOCF        BIT(9)
-#define STM32_I2C_ICR_OVRCF         BIT(10)
-#define STM32_I2C_ICR_TIMEOUTCF     BIT(12)
-#define STM32_I2C_ICR_ALL           0x3F38
+#define STM32_I2C_ICR_ADDRCF BIT(3)
+#define STM32_I2C_ICR_NACKCF BIT(4)
+#define STM32_I2C_ICR_STOPCF BIT(5)
+#define STM32_I2C_ICR_BERRCF BIT(8)
+#define STM32_I2C_ICR_ARLOCF BIT(9)
+#define STM32_I2C_ICR_OVRCF BIT(10)
+#define STM32_I2C_ICR_TIMEOUTCF BIT(12)
+#define STM32_I2C_ICR_ALL 0x3F38
 
 /* --- I2C TIMINGR bit Definitions --- */
 #define STM32_I2C_TIMINGR_SCLL_OFF 0
@@ -579,277 +559,271 @@
 
 /* --- Power / Reset / Clocks --- */
 
-#define STM32_RCC_CR                    REG32(STM32_RCC_BASE + 0x00)
-#define STM32_RCC_ICSCR                 REG32(STM32_RCC_BASE + 0x04)
-#define STM32_RCC_CFGR                  REG32(STM32_RCC_BASE + 0x08)
-#define STM32_RCC_PLLCFGR               REG32(STM32_RCC_BASE + 0x0C)
-#define STM32_RCC_CIER                  REG32(STM32_RCC_BASE + 0x18)
-#define STM32_RCC_CIFR                  REG32(STM32_RCC_BASE + 0x1C)
-#define STM32_RCC_CICR                  REG32(STM32_RCC_BASE + 0x20)
-#define STM32_RCC_AHB1RSTR              REG32(STM32_RCC_BASE + 0x28)
-#define STM32_RCC_AHB2RSTR              REG32(STM32_RCC_BASE + 0x2C)
-#define STM32_RCC_AHB3RSTR              REG32(STM32_RCC_BASE + 0x30)
-#define STM32_RCC_APB1RSTR1             REG32(STM32_RCC_BASE + 0x38)
-#define STM32_RCC_APB1RSTR2             REG32(STM32_RCC_BASE + 0x3C)
-#define STM32_RCC_APB2RSTR              REG32(STM32_RCC_BASE + 0x40)
-#define STM32_RCC_AHB1ENR               REG32(STM32_RCC_BASE + 0x48)
-#define STM32_RCC_AHB2ENR               REG32(STM32_RCC_BASE + 0x4C)
-#define STM32_RCC_AHB3ENR               REG32(STM32_RCC_BASE + 0x50)
-#define STM32_RCC_APB1ENR1              REG32(STM32_RCC_BASE + 0x58)
-#define STM32_RCC_APB1ENR2              REG32(STM32_RCC_BASE + 0x5C)
-#define STM32_RCC_APB2ENR               REG32(STM32_RCC_BASE + 0x60)
-#define STM32_RCC_AHB1SMENR             REG32(STM32_RCC_BASE + 0x68)
-#define STM32_RCC_AHB2SMENR             REG32(STM32_RCC_BASE + 0x6C)
-#define STM32_RCC_AHB3SMENR             REG32(STM32_RCC_BASE + 0x70)
-#define STM32_RCC_APB1SMENR1            REG32(STM32_RCC_BASE + 0x78)
-#define STM32_RCC_APB1SMENR2            REG32(STM32_RCC_BASE + 0x7C)
-#define STM32_RCC_APB2SMENR             REG32(STM32_RCC_BASE + 0x80)
-#define STM32_RCC_CCIPR                 REG32(STM32_RCC_BASE + 0x88)
-#define STM32_RCC_BDCR                  REG32(STM32_RCC_BASE + 0x90)
-#define STM32_RCC_CSR                   REG32(STM32_RCC_BASE + 0x94)
-#define STM32_RCC_CRRCR                 REG32(STM32_RCC_BASE + 0x98)
-#define STM32_RCC_CCIPR2                REG32(STM32_RCC_BASE + 0x9C)
+#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00)
+#define STM32_RCC_ICSCR REG32(STM32_RCC_BASE + 0x04)
+#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08)
+#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x0C)
+#define STM32_RCC_CIER REG32(STM32_RCC_BASE + 0x18)
+#define STM32_RCC_CIFR REG32(STM32_RCC_BASE + 0x1C)
+#define STM32_RCC_CICR REG32(STM32_RCC_BASE + 0x20)
+#define STM32_RCC_AHB1RSTR REG32(STM32_RCC_BASE + 0x28)
+#define STM32_RCC_AHB2RSTR REG32(STM32_RCC_BASE + 0x2C)
+#define STM32_RCC_AHB3RSTR REG32(STM32_RCC_BASE + 0x30)
+#define STM32_RCC_APB1RSTR1 REG32(STM32_RCC_BASE + 0x38)
+#define STM32_RCC_APB1RSTR2 REG32(STM32_RCC_BASE + 0x3C)
+#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x40)
+#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x48)
+#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x4C)
+#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x50)
+#define STM32_RCC_APB1ENR1 REG32(STM32_RCC_BASE + 0x58)
+#define STM32_RCC_APB1ENR2 REG32(STM32_RCC_BASE + 0x5C)
+#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x60)
+#define STM32_RCC_AHB1SMENR REG32(STM32_RCC_BASE + 0x68)
+#define STM32_RCC_AHB2SMENR REG32(STM32_RCC_BASE + 0x6C)
+#define STM32_RCC_AHB3SMENR REG32(STM32_RCC_BASE + 0x70)
+#define STM32_RCC_APB1SMENR1 REG32(STM32_RCC_BASE + 0x78)
+#define STM32_RCC_APB1SMENR2 REG32(STM32_RCC_BASE + 0x7C)
+#define STM32_RCC_APB2SMENR REG32(STM32_RCC_BASE + 0x80)
+#define STM32_RCC_CCIPR REG32(STM32_RCC_BASE + 0x88)
+#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x90)
+#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x94)
+#define STM32_RCC_CRRCR REG32(STM32_RCC_BASE + 0x98)
+#define STM32_RCC_CCIPR2 REG32(STM32_RCC_BASE + 0x9C)
 
 #define STM32_RCC_APB1ENR STM32_RCC_APB1ENR1
 #define STM32_RCC_AHBENR STM32_RCC_APB1ENR
 
 /* --- RCC CR Bit Definitions --- */
-#define STM32_RCC_CR_HSION		BIT(8)
-#define STM32_RCC_CR_HSIRDY		BIT(10)
-#define STM32_RCC_CR_HSEON		BIT(16)
-#define STM32_RCC_CR_HSERDY		BIT(17)
-#define STM32_RCC_CR_PLLON		BIT(24)
-#define STM32_RCC_CR_PLLRDY		BIT(25)
+#define STM32_RCC_CR_HSION BIT(8)
+#define STM32_RCC_CR_HSIRDY BIT(10)
+#define STM32_RCC_CR_HSEON BIT(16)
+#define STM32_RCC_CR_HSERDY BIT(17)
+#define STM32_RCC_CR_PLLON BIT(24)
+#define STM32_RCC_CR_PLLRDY BIT(25)
 
 /* --- RCC PLLCFGR Bit Definitions --- */
-#define  PLLCFGR_PLLSRC_OFF		0
-#define  PLLCFGR_PLLSRC(val)		(((val) & 0x3) << PLLCFGR_PLLSRC_OFF)
-#define  PLLCFGR_PLLSRC_HSI		2
-#define  PLLCFGR_PLLSRC_HSE		3
+#define PLLCFGR_PLLSRC_OFF 0
+#define PLLCFGR_PLLSRC(val) (((val)&0x3) << PLLCFGR_PLLSRC_OFF)
+#define PLLCFGR_PLLSRC_HSI 2
+#define PLLCFGR_PLLSRC_HSE 3
 /* PLL Division factor */
-#define  PLLCFGR_PLLM_OFF		4
-#define  PLLCFGR_PLLM(val)		(((val) & 0x1f) << PLLCFGR_PLLM_OFF)
+#define PLLCFGR_PLLM_OFF 4
+#define PLLCFGR_PLLM(val) (((val)&0x1f) << PLLCFGR_PLLM_OFF)
 /* PLL Multiplication factor */
-#define  PLLCFGR_PLLN_OFF		8
-#define  PLLCFGR_PLLN(val)		(((val) & 0x7f) << PLLCFGR_PLLN_OFF)
-#define  PLLCFGR_PLLQ_EN		BIT(20)
-#define  PLLCFGR_PLLQ_OFF		21
-#define  PLLCFGR_PLLQ(val)		(((val) & 0x3) << PLLCFGR_PLLQ_OFF)
+#define PLLCFGR_PLLN_OFF 8
+#define PLLCFGR_PLLN(val) (((val)&0x7f) << PLLCFGR_PLLN_OFF)
+#define PLLCFGR_PLLQ_EN BIT(20)
+#define PLLCFGR_PLLQ_OFF 21
+#define PLLCFGR_PLLQ(val) (((val)&0x3) << PLLCFGR_PLLQ_OFF)
 /* System and main CPU clock */
-#define  PLLCFGR_PLLR_EN		BIT(24)
-#define  PLLCFGR_PLLR_OFF		25
-#define  PLLCFGR_PLLR(val)		(((val) & 0x3) << PLLCFGR_PLLR_OFF)
-#define  PLLCFGR_PLLP_OFF		27
-#define  PLLCFGR_PLLP(val)		(((val) & 0x1f) << PLLCFGR_PLLP_OFF)
+#define PLLCFGR_PLLR_EN BIT(24)
+#define PLLCFGR_PLLR_OFF 25
+#define PLLCFGR_PLLR(val) (((val)&0x3) << PLLCFGR_PLLR_OFF)
+#define PLLCFGR_PLLP_OFF 27
+#define PLLCFGR_PLLP(val) (((val)&0x1f) << PLLCFGR_PLLP_OFF)
 
 /* --- RCC CFGR Bit Definitions --- */
-#define STM32_RCC_CFGR_SW_HSI		(1 << 0)
-#define STM32_RCC_CFGR_SW_HSE		(2 << 0)
-#define STM32_RCC_CFGR_SW_PLL		(3 << 0)
-#define STM32_RCC_CFGR_SW_MASK		(3 << 0)
-#define STM32_RCC_CFGR_SWS_HSI		(1 << 2)
-#define STM32_RCC_CFGR_SWS_HSE		(2 << 2)
-#define STM32_RCC_CFGR_SWS_PLL		(3 << 2)
-#define STM32_RCC_CFGR_SWS_MASK		(3 << 2)
+#define STM32_RCC_CFGR_SW_HSI (1 << 0)
+#define STM32_RCC_CFGR_SW_HSE (2 << 0)
+#define STM32_RCC_CFGR_SW_PLL (3 << 0)
+#define STM32_RCC_CFGR_SW_MASK (3 << 0)
+#define STM32_RCC_CFGR_SWS_HSI (1 << 2)
+#define STM32_RCC_CFGR_SWS_HSE (2 << 2)
+#define STM32_RCC_CFGR_SWS_PLL (3 << 2)
+#define STM32_RCC_CFGR_SWS_MASK (3 << 2)
 /* AHB Prescalar: */
-#define  CFGR_HPRE_OFF			4
-#define  CFGR_HPRE(val)			(((val) & 0xf) << CFGR_HPRE_OFF)
+#define CFGR_HPRE_OFF 4
+#define CFGR_HPRE(val) (((val)&0xf) << CFGR_HPRE_OFF)
 /* APB1 Low Speed Prescalar < 45MHz */
-#define  CFGR_PPRE1_OFF			8
-#define  CFGR_PPRE1(val)		(((val) & 0x7) << CFGR_PPRE1_OFF)
+#define CFGR_PPRE1_OFF 8
+#define CFGR_PPRE1(val) (((val)&0x7) << CFGR_PPRE1_OFF)
 /* APB2 High Speed Prescalar < 90MHz */
-#define  CFGR_PPRE2_OFF			11
-#define  CFGR_PPRE2(val)		(((val) & 0x7) << CFGR_PPRE2_OFF)
+#define CFGR_PPRE2_OFF 11
+#define CFGR_PPRE2(val) (((val)&0x7) << CFGR_PPRE2_OFF)
 /* RTC CLock: Must equal 1MHz */
-#define  CFGR_RTCPRE_OFF		16
-#define  CFGR_RTCPRE(val)		(((val) & 0x1f) << CFGR_RTCPRE_OFF)
+#define CFGR_RTCPRE_OFF 16
+#define CFGR_RTCPRE(val) (((val)&0x1f) << CFGR_RTCPRE_OFF)
 
 /* --- RCC AHB1ENR Bit Definitions --- */
-#define STM32_RCC_AHB1ENR_DMA1EN	BIT(0)
-#define STM32_RCC_AHB1ENR_DMA2EN	BIT(1)
-#define STM32_RCC_AHB1ENR_DMAMUXEN	BIT(2)
+#define STM32_RCC_AHB1ENR_DMA1EN BIT(0)
+#define STM32_RCC_AHB1ENR_DMA2EN BIT(1)
+#define STM32_RCC_AHB1ENR_DMAMUXEN BIT(2)
 
 /* --- RCC AHB2ENR Bit Definitions --- */
-#define STM32_RCC_AHB2ENR_GPIO_PORTA	BIT(0)
-#define STM32_RCC_AHB2ENR_GPIO_PORTB	BIT(1)
-#define STM32_RCC_AHB2ENR_GPIO_PORTC	BIT(2)
-#define STM32_RCC_AHB2ENR_GPIO_PORTD	BIT(3)
-#define STM32_RCC_AHB2ENR_GPIO_PORTE	BIT(4)
-#define STM32_RCC_AHB2ENR_GPIO_PORTF	BIT(5)
-#define STM32_RCC_AHB2ENR_GPIO_PORTG	BIT(6)
-#define STM32_RCC_AHB2ENR_GPIOMASK	(0x7f << 0)
-#define STM32_RCC_AHB2ENR_ADC12EN	BIT(13)
-#define STM32_RCC_APB2ENR_ADC345EN	BIT(14)
-#define STM32_RCC_AHB2ENR_RNGEN		BIT(26)
+#define STM32_RCC_AHB2ENR_GPIO_PORTA BIT(0)
+#define STM32_RCC_AHB2ENR_GPIO_PORTB BIT(1)
+#define STM32_RCC_AHB2ENR_GPIO_PORTC BIT(2)
+#define STM32_RCC_AHB2ENR_GPIO_PORTD BIT(3)
+#define STM32_RCC_AHB2ENR_GPIO_PORTE BIT(4)
+#define STM32_RCC_AHB2ENR_GPIO_PORTF BIT(5)
+#define STM32_RCC_AHB2ENR_GPIO_PORTG BIT(6)
+#define STM32_RCC_AHB2ENR_GPIOMASK (0x7f << 0)
+#define STM32_RCC_AHB2ENR_ADC12EN BIT(13)
+#define STM32_RCC_APB2ENR_ADC345EN BIT(14)
+#define STM32_RCC_AHB2ENR_RNGEN BIT(26)
 
 /* --- RCC APB1ENR1 Bit Definitions --- */
-#define STM32_RCC_APB1ENR1_TIM2EN                BIT(0)
-#define STM32_RCC_APB1ENR1_TIM3EN                BIT(1)
-#define STM32_RCC_APB1ENR1_TIM4EN                BIT(2)
-#define STM32_RCC_APB1ENR1_TIM5EN                BIT(3)
-#define STM32_RCC_APB1ENR1_TIM6EN                BIT(4)
-#define STM32_RCC_APB1ENR1_TIM7EN                BIT(5)
-#define STM32_RCC_APB1ENR1_WWDGEN                BIT(11)
-#define STM32_RCC_APB1ENR1_USART2                BIT(17)
-#define STM32_RCC_APB1ENR1_USART3                BIT(18)
-#define STM32_RCC_APB1ENR1_UART4                 BIT(19)
-#define STM32_RCC_APB1ENR1_UART5                 BIT(20)
-#define STM32_RCC_APB1ENR1_I2C1EN                BIT(21)
-#define STM32_RCC_APB1ENR1_I2C2EN                BIT(22)
-#define STM32_RCC_APB1ENR1_USBEN                 BIT(23)
-#define STM32_RCC_APB1ENR1_PWREN                 BIT(28)
-#define STM32_RCC_APB1ENR1_I2C3EN                BIT(30)
+#define STM32_RCC_APB1ENR1_TIM2EN BIT(0)
+#define STM32_RCC_APB1ENR1_TIM3EN BIT(1)
+#define STM32_RCC_APB1ENR1_TIM4EN BIT(2)
+#define STM32_RCC_APB1ENR1_TIM5EN BIT(3)
+#define STM32_RCC_APB1ENR1_TIM6EN BIT(4)
+#define STM32_RCC_APB1ENR1_TIM7EN BIT(5)
+#define STM32_RCC_APB1ENR1_WWDGEN BIT(11)
+#define STM32_RCC_APB1ENR1_USART2 BIT(17)
+#define STM32_RCC_APB1ENR1_USART3 BIT(18)
+#define STM32_RCC_APB1ENR1_UART4 BIT(19)
+#define STM32_RCC_APB1ENR1_UART5 BIT(20)
+#define STM32_RCC_APB1ENR1_I2C1EN BIT(21)
+#define STM32_RCC_APB1ENR1_I2C2EN BIT(22)
+#define STM32_RCC_APB1ENR1_USBEN BIT(23)
+#define STM32_RCC_APB1ENR1_PWREN BIT(28)
+#define STM32_RCC_APB1ENR1_I2C3EN BIT(30)
 
 #define STM32_RCC_PWREN STM32_RCC_APB1ENR1_PWREN
 
 /* --- RCC APB1ENR2 Bit Definitions --- */
-#define STM32_RCC_APB1ENR2_LPUART1EN             BIT(0)
-#define STM32_RCC_APB1ENR2_I2C4EN                BIT(1)
-#define STM32_RCC_APB1ENR2_UPCD1EN               BIT(8)
+#define STM32_RCC_APB1ENR2_LPUART1EN BIT(0)
+#define STM32_RCC_APB1ENR2_I2C4EN BIT(1)
+#define STM32_RCC_APB1ENR2_UPCD1EN BIT(8)
 
 /* --- RCC APB2ENR Bit Definitions --- */
-#define STM32_RCC_APB2ENR_SYSCFGEN	BIT(0)
-#define STM32_RCC_APB2ENR_TIM1		BIT(11)
-#define STM32_RCC_APB2ENR_SPI1EN	BIT(12)
-#define STM32_RCC_APB2ENR_TIM8		BIT(13)
-#define STM32_RCC_APB2ENR_USART1        BIT(14)
-#define STM32_RCC_APB2ENR_SPI4EN	BIT(15)
-#define STM32_RCC_APB2ENR_TIM15	BIT(16)
-#define STM32_RCC_APB2ENR_TIM16	BIT(17)
-#define STM32_RCC_APB2ENR_TIM17	BIT(18)
-#define STM32_RCC_APB2ENR_TIM20	BIT(20)
-
-#define STM32_RCC_PB2_USART1		STM32_RCC_APB2ENR_USART1
+#define STM32_RCC_APB2ENR_SYSCFGEN BIT(0)
+#define STM32_RCC_APB2ENR_TIM1 BIT(11)
+#define STM32_RCC_APB2ENR_SPI1EN BIT(12)
+#define STM32_RCC_APB2ENR_TIM8 BIT(13)
+#define STM32_RCC_APB2ENR_USART1 BIT(14)
+#define STM32_RCC_APB2ENR_SPI4EN BIT(15)
+#define STM32_RCC_APB2ENR_TIM15 BIT(16)
+#define STM32_RCC_APB2ENR_TIM16 BIT(17)
+#define STM32_RCC_APB2ENR_TIM17 BIT(18)
+#define STM32_RCC_APB2ENR_TIM20 BIT(20)
+
+#define STM32_RCC_PB2_USART1 STM32_RCC_APB2ENR_USART1
 
 /* gpio.c needs STM32_RCC_SYSCFGEN */
 #define STM32_RCC_SYSCFGEN STM32_RCC_APB2ENR_SYSCFGEN
 
 /* --- RCC APB1RSTR1 Bit Definitions --- */
-#define STM32_RCC_APB1RSTR1_USB_RST     BIT(23)
-#define STM32_RCC_APB1RSTR              STM32_RCC_APB1RSTR1
-#define STM32_RCC_PB1_USB               STM32_RCC_APB1RSTR1_USB_RST
+#define STM32_RCC_APB1RSTR1_USB_RST BIT(23)
+#define STM32_RCC_APB1RSTR STM32_RCC_APB1RSTR1
+#define STM32_RCC_PB1_USB STM32_RCC_APB1RSTR1_USB_RST
 
 /* --- RCC CSR Bit Definitions --- */
-#define STM32_RCC_CSR_LSION		BIT(0)
-#define STM32_RCC_CSR_LSIRDY		BIT(1)
+#define STM32_RCC_CSR_LSION BIT(0)
+#define STM32_RCC_CSR_LSIRDY BIT(1)
 
 /* --- RCC CCIPR Bit Definitions --- */
-#define STM32_RCC_CCIPR_UART_SYSCLK      0x1
-#define STM32_RCC_CCIPR_USART1SEL_MASK   0x3
-#define STM32_RCC_CCIPR_USART1SEL_SHIFT  0
-#define STM32_RCC_CCIPR_LPUART1SEL_MASK  0x3
+#define STM32_RCC_CCIPR_UART_SYSCLK 0x1
+#define STM32_RCC_CCIPR_USART1SEL_MASK 0x3
+#define STM32_RCC_CCIPR_USART1SEL_SHIFT 0
+#define STM32_RCC_CCIPR_LPUART1SEL_MASK 0x3
 #define STM32_RCC_CCIPR_LPUART1SEL_SHIFT 10
-#define STM32_RCC_CCIPR_I2C1SEL_MASK     0x3
-#define STM32_RCC_CCIPR_I2C1SEL_SHIFT    12
-#define STM32_RCC_CCIPR_I2C2SEL_MASK     0x3
-#define STM32_RCC_CCIPR_I2C2SEL_SHIFT    14
-#define STM32_RCC_CCIPR_I2C3SEL_MASK     0x3
-#define STM32_RCC_CCIPR_I2C3SEL_SHIFT    16
+#define STM32_RCC_CCIPR_I2C1SEL_MASK 0x3
+#define STM32_RCC_CCIPR_I2C1SEL_SHIFT 12
+#define STM32_RCC_CCIPR_I2C2SEL_MASK 0x3
+#define STM32_RCC_CCIPR_I2C2SEL_SHIFT 14
+#define STM32_RCC_CCIPR_I2C3SEL_MASK 0x3
+#define STM32_RCC_CCIPR_I2C3SEL_SHIFT 16
 
-#define STM32_RCC_CCIPR2_I2C4SEL_MASK    0x3
+#define STM32_RCC_CCIPR2_I2C4SEL_MASK 0x3
 
-#define STM32_RCC_CCIPR_I2CNSEL_MASK     0x3
+#define STM32_RCC_CCIPR_I2CNSEL_MASK 0x3
 #define STM32_RCC_CCIPR_I2CNSEL_SHIFT(n) (STM32_RCC_CCIPR_I2C1SEL_SHIFT + n * 2)
-#define STM32_RCC_CCIPR_I2CNSEL_HSI      0x2
+#define STM32_RCC_CCIPR_I2CNSEL_HSI 0x2
 /* --- RCC CRRCR Bit Definitions */
-#define RCC_CRRCR_HSI48O               BIT(0)
-#define RCC_CRRCR_HSIRDY               BIT(1)
+#define RCC_CRRCR_HSI48O BIT(0)
+#define RCC_CRRCR_HSIRDY BIT(1)
 
 /* Reset causes definitions */
 /*
  * Reset causes in RCC CSR register. The generic names are required
  */
 #define STM32_RCC_RESET_CAUSE STM32_RCC_CSR
-#define STM32_RCC_CSR_RMVF              BIT(24)
-#define STM32_RCC_CSR_BORRS             BIT(25)
-#define STM32_RCC_CSR_PIN               BIT(26)
-#define STM32_RCC_CSR_POR               BIT(27)
-#define STM32_RCC_CSR_SFT               BIT(28)
-#define STM32_RCC_CSR_IWDG              BIT(29)
-#define STM32_RCC_CSR_WWDG              BIT(30)
-#define STM32_RCC_CSR_LPWR              BIT(31)
-
-
-#define  RESET_CAUSE_WDG                (STM32_RCC_CSR_WWDG | \
-					 STM32_RCC_CSR_IWDG)
-#define  RESET_CAUSE_SFT                STM32_RCC_CSR_SFT
-#define  RESET_CAUSE_POR                STM32_RCC_CSR_POR
-#define  RESET_CAUSE_PIN                STM32_RCC_CSR_PIN
-#define  RESET_CAUSE_RMVF               STM32_RCC_CSR_RMVF
-#define  RESET_CAUSE_OTHER              (STM32_RCC_CSR_LPWR | \
-					 STM32_RCC_CSR_BORRS)
+#define STM32_RCC_CSR_RMVF BIT(24)
+#define STM32_RCC_CSR_BORRS BIT(25)
+#define STM32_RCC_CSR_PIN BIT(26)
+#define STM32_RCC_CSR_POR BIT(27)
+#define STM32_RCC_CSR_SFT BIT(28)
+#define STM32_RCC_CSR_IWDG BIT(29)
+#define STM32_RCC_CSR_WWDG BIT(30)
+#define STM32_RCC_CSR_LPWR BIT(31)
+
+#define RESET_CAUSE_WDG (STM32_RCC_CSR_WWDG | STM32_RCC_CSR_IWDG)
+#define RESET_CAUSE_SFT STM32_RCC_CSR_SFT
+#define RESET_CAUSE_POR STM32_RCC_CSR_POR
+#define RESET_CAUSE_PIN STM32_RCC_CSR_PIN
+#define RESET_CAUSE_RMVF STM32_RCC_CSR_RMVF
+#define RESET_CAUSE_OTHER (STM32_RCC_CSR_LPWR | STM32_RCC_CSR_BORRS)
 /* Power cause in PWR CSR register */
-#define STM32_PWR_CR1                   REG32(STM32_PWR_BASE + 0x00)
-#define STM32_PWR_CR2                   REG32(STM32_PWR_BASE + 0x04)
-#define STM32_PWR_CR3                   REG32(STM32_PWR_BASE + 0x08)
-#define STM32_PWR_CR4                   REG32(STM32_PWR_BASE + 0x0C)
-#define STM32_PWR_SR1                   REG32(STM32_PWR_BASE + 0x10)
-#define STM32_PWR_SR2                   REG32(STM32_PWR_BASE + 0x14)
-#define STM32_PWR_SCR                   REG32(STM32_PWR_BASE + 0x18)
-#define STM32_PWR_SCR_CSBF              BIT(8)
-#define STM32_PWR_SR1_SBF               BIT(8)
+#define STM32_PWR_CR1 REG32(STM32_PWR_BASE + 0x00)
+#define STM32_PWR_CR2 REG32(STM32_PWR_BASE + 0x04)
+#define STM32_PWR_CR3 REG32(STM32_PWR_BASE + 0x08)
+#define STM32_PWR_CR4 REG32(STM32_PWR_BASE + 0x0C)
+#define STM32_PWR_SR1 REG32(STM32_PWR_BASE + 0x10)
+#define STM32_PWR_SR2 REG32(STM32_PWR_BASE + 0x14)
+#define STM32_PWR_SCR REG32(STM32_PWR_BASE + 0x18)
+#define STM32_PWR_SCR_CSBF BIT(8)
+#define STM32_PWR_SR1_SBF BIT(8)
 
 #define STM32_PWR_RESET_CAUSE STM32_PWR_SR1
-#define  RESET_CAUSE_SBF                STM32_PWR_SR1_SBF
+#define RESET_CAUSE_SBF STM32_PWR_SR1_SBF
 #define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_SCR
-#define  RESET_CAUSE_SBF_CLR            STM32_PWR_SCR_CSBF
+#define RESET_CAUSE_SBF_CLR STM32_PWR_SCR_CSBF
 
-#define STM32_PWR_CR1_DBP               BIT(8)
+#define STM32_PWR_CR1_DBP BIT(8)
 
-#define STM32_PWR_CR3_UCPD1_STDBY       BIT(13)
-#define STM32_PWR_CR3_UCPD1_DBDIS       BIT(14)
+#define STM32_PWR_CR3_UCPD1_STDBY BIT(13)
+#define STM32_PWR_CR3_UCPD1_DBDIS BIT(14)
 
 /* --- System Config Registers --- */
-#define STM32_SYSCFG_MEMRMP             REG32(STM32_SYSCFG_BASE + 0x00)
-#define STM32_SYSCFG_PMC                REG32(STM32_SYSCFG_BASE + 0x04)
-#define STM32_SYSCFG_EXTICR(n)          REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
-#define STM32_SYSCFG_CMPCR              REG32(STM32_SYSCFG_BASE + 0x20)
-#define STM32_SYSCFG_CFGR               REG32(STM32_SYSCFG_BASE + 0x2C)
+#define STM32_SYSCFG_MEMRMP REG32(STM32_SYSCFG_BASE + 0x00)
+#define STM32_SYSCFG_PMC REG32(STM32_SYSCFG_BASE + 0x04)
+#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
+#define STM32_SYSCFG_CMPCR REG32(STM32_SYSCFG_BASE + 0x20)
+#define STM32_SYSCFG_CFGR REG32(STM32_SYSCFG_BASE + 0x2C)
 
 /* --- Watchdogs --- */
 
 /* --- Real-Time Clock --- */
-#define STM32_RTC_TR                REG32(STM32_RTC_BASE + 0x00)
-#define STM32_RTC_DR                REG32(STM32_RTC_BASE + 0x04)
-#define STM32_RTC_SSR               REG32(STM32_RTC_BASE + 0x08)
-#define STM32_RTC_ISR               REG32(STM32_RTC_BASE + 0x0C)
-#define STM32_RTC_PRER              REG32(STM32_RTC_BASE + 0x10)
-#define STM32_RTC_WUTR              REG32(STM32_RTC_BASE + 0x14)
-#define STM32_RTC_CR                REG32(STM32_RTC_BASE + 0x18)
-
-
-#define STM32_RTC_WPR               REG32(STM32_RTC_BASE + 0x24)
-#define STM32_RTC_CALR              REG32(STM32_RTC_BASE + 0x28)
-#define STM32_RTC_SHIFTR            REG32(STM32_RTC_BASE + 0x2C)
-#define STM32_RTC_TSTR              REG32(STM32_RTC_BASE + 0x30)
-#define STM32_RTC_TSDR              REG32(STM32_RTC_BASE + 0x34)
-#define STM32_RTC_TSSSR             REG32(STM32_RTC_BASE + 0x38)
-
-#define STM32_RTC_ALRMAR            REG32(STM32_RTC_BASE + 0x40)
-#define STM32_RTC_ALRMASSR          REG32(STM32_RTC_BASE + 0x44)
-#define STM32_RTC_ALRMBR            REG32(STM32_RTC_BASE + 0x48)
-#define STM32_RTC_ALRMBSSR          REG32(STM32_RTC_BASE + 0x44)
+#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00)
+#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04)
+#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x08)
+#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C)
+#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10)
+#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14)
+#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x18)
+
+#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24)
+#define STM32_RTC_CALR REG32(STM32_RTC_BASE + 0x28)
+#define STM32_RTC_SHIFTR REG32(STM32_RTC_BASE + 0x2C)
+#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30)
+#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34)
+#define STM32_RTC_TSSSR REG32(STM32_RTC_BASE + 0x38)
+
+#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x40)
+#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44)
+#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x48)
+#define STM32_RTC_ALRMBSSR REG32(STM32_RTC_BASE + 0x44)
 
 /* --- RTC CR Bit Definitions --- */
-#define STM32_RTC_CR_BYPSHAD        BIT(5)
-#define STM32_RTC_CR_ALRAE          BIT(8)
-#define STM32_RTC_CR_ALRAIE         BIT(12)
+#define STM32_RTC_CR_BYPSHAD BIT(5)
+#define STM32_RTC_CR_ALRAE BIT(8)
+#define STM32_RTC_CR_ALRAIE BIT(12)
 /* --- RTC ICSR Bit Definitions --- */
-#define STM32_RTC_ISR_ALRAWF        BIT(0)
-#define STM32_RTC_ISR_RSF           BIT(5)
-#define STM32_RTC_ISR_INITF         BIT(6)
-#define STM32_RTC_ISR_INIT          BIT(7)
-#define STM32_RTC_ISR_ALRAF         BIT(8)
+#define STM32_RTC_ISR_ALRAWF BIT(0)
+#define STM32_RTC_ISR_RSF BIT(5)
+#define STM32_RTC_ISR_INITF BIT(6)
+#define STM32_RTC_ISR_INIT BIT(7)
+#define STM32_RTC_ISR_ALRAF BIT(8)
 /* --- RTC PRER Bit Definitions --- */
-#define STM32_RTC_PRER_A_MASK       (0x7f << 16)
-#define STM32_RTC_PRER_S_MASK       (0x7fff << 0)
-
+#define STM32_RTC_PRER_A_MASK (0x7f << 16)
+#define STM32_RTC_PRER_S_MASK (0x7fff << 0)
 
 /* --- Tamper and Backup --- */
-#define STM32_TAMP_BKPxR(n)         REG32(STM32_TAMP_BASE + 0x100 + 4 * (n))
-#define STM32_BKP_DATA(n)           STM32_TAMP_BKPxR(n)
-#define STM32_BKP_BYTES             64
-
+#define STM32_TAMP_BKPxR(n) REG32(STM32_TAMP_BASE + 0x100 + 4 * (n))
+#define STM32_BKP_DATA(n) STM32_TAMP_BKPxR(n)
+#define STM32_BKP_BYTES 64
 
 /* --- SPI --- */
 
@@ -877,223 +851,222 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
 #define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE)
 #define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE)
 
-#define STM32_SPI_CR1_BIDIMODE		BIT(15)
-#define STM32_SPI_CR1_BIDIOE		BIT(14)
-#define STM32_SPI_CR1_CRCEN		BIT(13)
-#define STM32_SPI_CR1_SSM		BIT(9)
-#define STM32_SPI_CR1_SSI		BIT(8)
-#define STM32_SPI_CR1_LSBFIRST		BIT(7)
-#define STM32_SPI_CR1_SPE		BIT(6)
-#define STM32_SPI_CR1_BR_DIV64R		(5 << 3)
-#define STM32_SPI_CR1_BR_DIV4R		BIT(3)
-#define STM32_SPI_CR1_MSTR		BIT(2)
-#define STM32_SPI_CR1_CPOL		BIT(1)
-#define STM32_SPI_CR1_CPHA		BIT(0)
-#define STM32_SPI_CR2_FRXTH		BIT(12)
-#define STM32_SPI_CR2_DATASIZE(n)	(((n) - 1) << 8)
-#define STM32_SPI_CR2_TXEIE		BIT(7)
-#define STM32_SPI_CR2_RXNEIE		BIT(6)
-#define STM32_SPI_CR2_NSSP		BIT(3)
-#define STM32_SPI_CR2_SSOE		BIT(2)
-#define STM32_SPI_CR2_TXDMAEN		BIT(1)
-#define STM32_SPI_CR2_RXDMAEN		BIT(0)
-
-#define STM32_SPI_SR_RXNE		BIT(0)
-#define STM32_SPI_SR_TXE		BIT(1)
-#define STM32_SPI_SR_CRCERR		BIT(4)
-#define STM32_SPI_SR_BSY		BIT(7)
-#define STM32_SPI_SR_FRLVL		(3 << 9)
-#define STM32_SPI_SR_FTLVL		(3 << 11)
+#define STM32_SPI_CR1_BIDIMODE BIT(15)
+#define STM32_SPI_CR1_BIDIOE BIT(14)
+#define STM32_SPI_CR1_CRCEN BIT(13)
+#define STM32_SPI_CR1_SSM BIT(9)
+#define STM32_SPI_CR1_SSI BIT(8)
+#define STM32_SPI_CR1_LSBFIRST BIT(7)
+#define STM32_SPI_CR1_SPE BIT(6)
+#define STM32_SPI_CR1_BR_DIV64R (5 << 3)
+#define STM32_SPI_CR1_BR_DIV4R BIT(3)
+#define STM32_SPI_CR1_MSTR BIT(2)
+#define STM32_SPI_CR1_CPOL BIT(1)
+#define STM32_SPI_CR1_CPHA BIT(0)
+#define STM32_SPI_CR2_FRXTH BIT(12)
+#define STM32_SPI_CR2_DATASIZE(n) (((n)-1) << 8)
+#define STM32_SPI_CR2_TXEIE BIT(7)
+#define STM32_SPI_CR2_RXNEIE BIT(6)
+#define STM32_SPI_CR2_NSSP BIT(3)
+#define STM32_SPI_CR2_SSOE BIT(2)
+#define STM32_SPI_CR2_TXDMAEN BIT(1)
+#define STM32_SPI_CR2_RXDMAEN BIT(0)
+
+#define STM32_SPI_SR_RXNE BIT(0)
+#define STM32_SPI_SR_TXE BIT(1)
+#define STM32_SPI_SR_CRCERR BIT(4)
+#define STM32_SPI_SR_BSY BIT(7)
+#define STM32_SPI_SR_FRLVL (3 << 9)
+#define STM32_SPI_SR_FTLVL (3 << 11)
 
 /* --- Debug --- */
-#define STM32_DBGMCU_IDCODE         REG32(STM32_DBGMCU_BASE + 0x00)
-#define STM32_DBGMCU_CR             REG32(STM32_DBGMCU_BASE + 0x04)
-#define STM32_DBGMCU_APB1FZ         REG32(STM32_DBGMCU_BASE + 0x08)
-#define STM32_DBGMCU_APB2FZ         REG32(STM32_DBGMCU_BASE + 0x0C)
+#define STM32_DBGMCU_IDCODE REG32(STM32_DBGMCU_BASE + 0x00)
+#define STM32_DBGMCU_CR REG32(STM32_DBGMCU_BASE + 0x04)
+#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08)
+#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C)
 
 /* --- DBGMCU CR Bit Definitions --- */
-#define  STM32_DBGMCU_CR_SLEEP                      BIT(0)
-#define  STM32_DBGMCU_CR_STOP                       BIT(1)
-#define  STM32_DBGMCU_CR_STBY                       BIT(2)
-#define  STM32_DBGMCU_CR_TRACE_MASK                 (BIT(5)|BIT(6)|BIT(7))
-#define   STM32_DBGMCU_CR_TRACE_EN                   BIT(5)
-#define   STM32_DBGMCU_CR_TRACE_MODE_ASYNC           0
-#define   STM32_DBGMCU_CR_TRACE_MODE_SYNC1           BIT(6)
-#define   STM32_DBGMCU_CR_TRACE_MODE_SYNC2           BIT(7)
-#define   STM32_DBGMCU_CR_TRACE_MODE_SYNC4           (BIT(6)|BIT(7))
+#define STM32_DBGMCU_CR_SLEEP BIT(0)
+#define STM32_DBGMCU_CR_STOP BIT(1)
+#define STM32_DBGMCU_CR_STBY BIT(2)
+#define STM32_DBGMCU_CR_TRACE_MASK (BIT(5) | BIT(6) | BIT(7))
+#define STM32_DBGMCU_CR_TRACE_EN BIT(5)
+#define STM32_DBGMCU_CR_TRACE_MODE_ASYNC 0
+#define STM32_DBGMCU_CR_TRACE_MODE_SYNC1 BIT(6)
+#define STM32_DBGMCU_CR_TRACE_MODE_SYNC2 BIT(7)
+#define STM32_DBGMCU_CR_TRACE_MODE_SYNC4 (BIT(6) | BIT(7))
 /* --- DBGMCU APB1FZ Bit Definitions --- */
-#define  STM32_DBGMCU_APB1FZ_TIM2                   BIT(0)
-#define  STM32_DBGMCU_APB1FZ_TIM3                   BIT(1)
-#define  STM32_DBGMCU_APB1FZ_TIM4                   BIT(2)
-#define  STM32_DBGMCU_APB1FZ_TIM5                   BIT(3)
-#define  STM32_DBGMCU_APB1FZ_TIM6                   BIT(4)
-#define  STM32_DBGMCU_APB1FZ_TIM7                   BIT(5)
-#define  STM32_DBGMCU_APB1FZ_RTC                    BIT(10)
-#define  STM32_DBGMCU_APB1FZ_WWDG                   BIT(11)
-#define  STM32_DBGMCU_APB1FZ_IWDG                   BIT(12)
-#define  STM32_DBGMCU_APB1FZ_I2C1_SMBUS_TIMEOUT     BIT(21)
-#define  STM32_DBGMCU_APB1FZ_I2C2_SMBUS_TIMEOUT     BIT(22)
-#define  STM32_DBGMCU_APB1FZ_I2C3_SMBUS_TIMEOUT     BIT(30)
+#define STM32_DBGMCU_APB1FZ_TIM2 BIT(0)
+#define STM32_DBGMCU_APB1FZ_TIM3 BIT(1)
+#define STM32_DBGMCU_APB1FZ_TIM4 BIT(2)
+#define STM32_DBGMCU_APB1FZ_TIM5 BIT(3)
+#define STM32_DBGMCU_APB1FZ_TIM6 BIT(4)
+#define STM32_DBGMCU_APB1FZ_TIM7 BIT(5)
+#define STM32_DBGMCU_APB1FZ_RTC BIT(10)
+#define STM32_DBGMCU_APB1FZ_WWDG BIT(11)
+#define STM32_DBGMCU_APB1FZ_IWDG BIT(12)
+#define STM32_DBGMCU_APB1FZ_I2C1_SMBUS_TIMEOUT BIT(21)
+#define STM32_DBGMCU_APB1FZ_I2C2_SMBUS_TIMEOUT BIT(22)
+#define STM32_DBGMCU_APB1FZ_I2C3_SMBUS_TIMEOUT BIT(30)
 /* --- DBGMCU  APB2FZ Bit Definitions --- */
-#define  STM32_DBGMCU_APB2FZ_TIM1                   BIT(11)
-#define  STM32_DBGMCU_APB2FZ_TIM8                   BIT(13)
-#define  STM32_DBGMCU_APB2FZ_TIM15                  BIT(16)
-#define  STM32_DBGMCU_APB2FZ_TIM16                  BIT(17)
-#define  STM32_DBGMCU_APB2FZ_TIM17                  BIT(18)
-#define  STM32_DBGMCU_APB2FZ_TIM20                  BIT(20)
+#define STM32_DBGMCU_APB2FZ_TIM1 BIT(11)
+#define STM32_DBGMCU_APB2FZ_TIM8 BIT(13)
+#define STM32_DBGMCU_APB2FZ_TIM15 BIT(16)
+#define STM32_DBGMCU_APB2FZ_TIM16 BIT(17)
+#define STM32_DBGMCU_APB2FZ_TIM17 BIT(18)
+#define STM32_DBGMCU_APB2FZ_TIM20 BIT(20)
 
 /* --- Flash --- */
-#define STM32_FLASH_REG(off)        REG32(STM32_FLASH_REGS_BASE + (off))
-#define STM32_FLASH_ACR             STM32_FLASH_REG(0x00)
-#define STM32_FLASH_PDKEYR          STM32_FLASH_REG(0x04)
-#define STM32_FLASH_KEYR            STM32_FLASH_REG(0x08)
-#define STM32_FLASH_OPTKEYR         STM32_FLASH_REG(0x0c)
-#define STM32_FLASH_SR              STM32_FLASH_REG(0x10)
-#define STM32_FLASH_CR              STM32_FLASH_REG(0x14)
-#define STM32_FLASH_ECCR            STM32_FLASH_REG(0x18)
+#define STM32_FLASH_REG(off) REG32(STM32_FLASH_REGS_BASE + (off))
+#define STM32_FLASH_ACR STM32_FLASH_REG(0x00)
+#define STM32_FLASH_PDKEYR STM32_FLASH_REG(0x04)
+#define STM32_FLASH_KEYR STM32_FLASH_REG(0x08)
+#define STM32_FLASH_OPTKEYR STM32_FLASH_REG(0x0c)
+#define STM32_FLASH_SR STM32_FLASH_REG(0x10)
+#define STM32_FLASH_CR STM32_FLASH_REG(0x14)
+#define STM32_FLASH_ECCR STM32_FLASH_REG(0x18)
 /*
  * Bank 1 Option Byte Copy Registers. These registers are loaded from the option
  * bytes location in flash at reset, assuming that option byte loading has not
  * been disabled.
  */
-#define STM32_FLASH_OPTR            STM32_FLASH_REG(0x20)
-#define STM32_FLASH_PCROP1SR        STM32_FLASH_REG(0x24)
-#define STM32_FLASH_PCROP1ER        STM32_FLASH_REG(0x28)
-#define STM32_FLASH_WRP1AR          STM32_FLASH_REG(0x2C)
-#define STM32_FLASH_WRP1BR          STM32_FLASH_REG(0x30)
+#define STM32_FLASH_OPTR STM32_FLASH_REG(0x20)
+#define STM32_FLASH_PCROP1SR STM32_FLASH_REG(0x24)
+#define STM32_FLASH_PCROP1ER STM32_FLASH_REG(0x28)
+#define STM32_FLASH_WRP1AR STM32_FLASH_REG(0x2C)
+#define STM32_FLASH_WRP1BR STM32_FLASH_REG(0x30)
 /*
  * Bank 2 Option Byte Copy Registers. These will only exist for category 3
  * devices.
  */
-#define STM32_FLASH_PCROP2SR        STM32_FLASH_REG(0x44)
-#define STM32_FLASH_PCROP2ER        STM32_FLASH_REG(0x48)
-#define STM32_FLASH_WRP2AR          STM32_FLASH_REG(0x4C)
-#define STM32_FLASH_WRP2BR          STM32_FLASH_REG(0x50)
+#define STM32_FLASH_PCROP2SR STM32_FLASH_REG(0x44)
+#define STM32_FLASH_PCROP2ER STM32_FLASH_REG(0x48)
+#define STM32_FLASH_WRP2AR STM32_FLASH_REG(0x4C)
+#define STM32_FLASH_WRP2BR STM32_FLASH_REG(0x50)
 
-#define STM32_FLASH_SEC_SIZE1       STM32_FLASH_REG(0x70)
-#define STM32_FLASH_SEC_SIZE2       STM32_FLASH_REG(0x74)
+#define STM32_FLASH_SEC_SIZE1 STM32_FLASH_REG(0x70)
+#define STM32_FLASH_SEC_SIZE2 STM32_FLASH_REG(0x74)
 
 /* --- FLASH CR Bit Definitions --- */
 #define STM32_FLASH_ACR_LATENCY_SHIFT (0)
-#define STM32_FLASH_ACR_LATENCY_MASK  (0xf << STM32_FLASH_ACR_LATENCY_SHIFT)
-#define STM32_FLASH_ACR_PRFTEN      BIT(8)
-#define STM32_FLASH_ACR_ICEN        BIT(9)
-#define STM32_FLASH_ACR_DCEN        BIT(10)
-#define STM32_FLASH_ACR_ICRST       BIT(11)
-#define STM32_FLASH_ACR_DCRST       BIT(12)
+#define STM32_FLASH_ACR_LATENCY_MASK (0xf << STM32_FLASH_ACR_LATENCY_SHIFT)
+#define STM32_FLASH_ACR_PRFTEN BIT(8)
+#define STM32_FLASH_ACR_ICEN BIT(9)
+#define STM32_FLASH_ACR_DCEN BIT(10)
+#define STM32_FLASH_ACR_ICRST BIT(11)
+#define STM32_FLASH_ACR_DCRST BIT(12)
 
 /* --- FLASH KEYR Bit Definitions --- */
-#define  FLASH_KEYR_KEY1            0x45670123
-#define  FLASH_KEYR_KEY2            0xCDEF89AB
+#define FLASH_KEYR_KEY1 0x45670123
+#define FLASH_KEYR_KEY2 0xCDEF89AB
 
 /* --- FLASH OPTKEYR Bit Definitions --- */
-#define  FLASH_OPTKEYR_KEY1         0x08192A3B
-#define  FLASH_OPTKEYR_KEY2         0x4C5D6E7F
+#define FLASH_OPTKEYR_KEY1 0x08192A3B
+#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F
 
 /* --- FLASH SR Bit Definitions --- */
-#define  FLASH_SR_BUSY              BIT(16)
-#define  FLASH_SR_OPTVERR           BIT(15)
-#define  FLASH_SR_RDERR             BIT(14)
-#define  FLASH_SR_FASTERR           BIT(9)
-#define  FLASH_SR_MISERR            BIT(8)
-#define  FLASH_SR_PGSERR            BIT(7)
-#define  FLASH_SR_SIZERR            BIT(6)
-#define  FLASH_SR_PGAERR            BIT(5)
-#define  FLASH_SR_WRPERR            BIT(4)
-#define  FLASH_SR_PROGERR           BIT(3)
-#define  FLASH_SR_OPERR             BIT(1)
-#define  FLASH_SR_ERR_MASK          (FLASH_SR_OPTVERR | FLASH_SR_RDERR | \
-				     FLASH_SR_FASTERR | FLASH_SR_PGSERR | \
-				     FLASH_SR_SIZERR | FLASH_SR_PGAERR |  \
-				     FLASH_SR_WRPERR |  FLASH_SR_PROGERR | \
-				     FLASH_SR_OPERR)
+#define FLASH_SR_BUSY BIT(16)
+#define FLASH_SR_OPTVERR BIT(15)
+#define FLASH_SR_RDERR BIT(14)
+#define FLASH_SR_FASTERR BIT(9)
+#define FLASH_SR_MISERR BIT(8)
+#define FLASH_SR_PGSERR BIT(7)
+#define FLASH_SR_SIZERR BIT(6)
+#define FLASH_SR_PGAERR BIT(5)
+#define FLASH_SR_WRPERR BIT(4)
+#define FLASH_SR_PROGERR BIT(3)
+#define FLASH_SR_OPERR BIT(1)
+#define FLASH_SR_ERR_MASK                                       \
+	(FLASH_SR_OPTVERR | FLASH_SR_RDERR | FLASH_SR_FASTERR | \
+	 FLASH_SR_PGSERR | FLASH_SR_SIZERR | FLASH_SR_PGAERR |  \
+	 FLASH_SR_WRPERR | FLASH_SR_PROGERR | FLASH_SR_OPERR)
 
 /* --- FLASH CR Bit Definitions --- */
-#define  FLASH_CR_PG                BIT(0)
-#define  FLASH_CR_PER               BIT(1)
-#define  FLASH_CR_STRT              BIT(16)
-#define  FLASH_CR_OPTSTRT           BIT(17)
-#define  FLASH_CR_OBL_LAUNCH        BIT(27)
-#define  FLASH_CR_OPTLOCK           BIT(30)
-#define  FLASH_CR_LOCK              BIT(31)
-#define  FLASH_CR_PNB(sec)          (((sec) & 0x7f) << 3)
-#define  FLASH_CR_PNB_MASK          FLASH_CR_PNB(0x7f)
-
-#define STM32_FLASH_MIN_WRITE_SIZE  (CONFIG_FLASH_WRITE_SIZE * 2)
+#define FLASH_CR_PG BIT(0)
+#define FLASH_CR_PER BIT(1)
+#define FLASH_CR_STRT BIT(16)
+#define FLASH_CR_OPTSTRT BIT(17)
+#define FLASH_CR_OBL_LAUNCH BIT(27)
+#define FLASH_CR_OPTLOCK BIT(30)
+#define FLASH_CR_LOCK BIT(31)
+#define FLASH_CR_PNB(sec) (((sec)&0x7f) << 3)
+#define FLASH_CR_PNB_MASK FLASH_CR_PNB(0x7f)
+
+#define STM32_FLASH_MIN_WRITE_SIZE (CONFIG_FLASH_WRITE_SIZE * 2)
 
 /* --- FLASH Option bytes --- */
-#define STM32_OPTB_USER_RDP         REG32(STM32_OPTB_BANK1_BASE + 0x00)
-#define STM32_OPTB_PCROP1_START     REG32(STM32_OPTB_BANK1_BASE + 0x08)
-#define STM32_OPTB_PCROP1_END       REG32(STM32_OPTB_BANK1_BASE + 0x10)
-#define STM32_OPTB_WRP1AR           REG32(STM32_OPTB_BANK1_BASE + 0x18)
-#define STM32_OPTB_WRP1BR           REG32(STM32_OPTB_BANK1_BASE + 0x20)
-#define STM32_OPTB_SECURE1_MEM      REG32(STM32_OPTB_BANK1_BASE + 0x28)
-
-#define STM32_OPTB_UNUSED           REG32(STM32_OPTB_BANK2_BASE + 0x00)
-#define STM32_OPTB_PCROP2_START     REG32(STM32_OPTB_BANK2_BASE + 0x08)
-#define STM32_OPTB_PCROP2_END       REG32(STM32_OPTB_BANK2_BASE + 0x10)
-#define STM32_OPTB_WRP2AR           REG32(STM32_OPTB_BANK2_BASE + 0x18)
-#define STM32_OPTB_WRP2BR           REG32(STM32_OPTB_BANK2_BASE + 0x20)
-#define STM32_OPTB_SECURE2_MEM      REG32(STM32_OPTB_BANK2_BASE + 0x28)
+#define STM32_OPTB_USER_RDP REG32(STM32_OPTB_BANK1_BASE + 0x00)
+#define STM32_OPTB_PCROP1_START REG32(STM32_OPTB_BANK1_BASE + 0x08)
+#define STM32_OPTB_PCROP1_END REG32(STM32_OPTB_BANK1_BASE + 0x10)
+#define STM32_OPTB_WRP1AR REG32(STM32_OPTB_BANK1_BASE + 0x18)
+#define STM32_OPTB_WRP1BR REG32(STM32_OPTB_BANK1_BASE + 0x20)
+#define STM32_OPTB_SECURE1_MEM REG32(STM32_OPTB_BANK1_BASE + 0x28)
+
+#define STM32_OPTB_UNUSED REG32(STM32_OPTB_BANK2_BASE + 0x00)
+#define STM32_OPTB_PCROP2_START REG32(STM32_OPTB_BANK2_BASE + 0x08)
+#define STM32_OPTB_PCROP2_END REG32(STM32_OPTB_BANK2_BASE + 0x10)
+#define STM32_OPTB_WRP2AR REG32(STM32_OPTB_BANK2_BASE + 0x18)
+#define STM32_OPTB_WRP2BR REG32(STM32_OPTB_BANK2_BASE + 0x20)
+#define STM32_OPTB_SECURE2_MEM REG32(STM32_OPTB_BANK2_BASE + 0x28)
 
 /* Read option bytes from flash memory for Bank 1 */
-#define STM32_OPTB_BANK1_READ(n)      REG32(STM32_OPTB_BANK1_BASE + ((n) * 8))
-#define STM32_OPTB_BANK1_COMP_READ(n) REG32(STM32_OPTB_BANK1_BASE + ((n) * 8) + 0x4)
-#define STM32_OPTB_BANK2_READ(n)      REG32(STM32_OPTB_BANK2_BASE + ((n) * 8))
-#define STM32_OPTB_BANK2_COMP_READ(n) REG32(STM32_OPTB_BANK2_BASE + ((n) * 8) + 0x4)
-
-#define STM32_OPTB_USER_DBANK       BIT(22)
-#define STM32_OPTB_USER_nBOOT1      BIT(23)
-#define STM32_OPTB_USER_nSWBOOT0    BIT(26)
-#define STM32_OPTB_USER_nBOOT0      BIT(27)
+#define STM32_OPTB_BANK1_READ(n) REG32(STM32_OPTB_BANK1_BASE + ((n)*8))
+#define STM32_OPTB_BANK1_COMP_READ(n) \
+	REG32(STM32_OPTB_BANK1_BASE + ((n)*8) + 0x4)
+#define STM32_OPTB_BANK2_READ(n) REG32(STM32_OPTB_BANK2_BASE + ((n)*8))
+#define STM32_OPTB_BANK2_COMP_READ(n) \
+	REG32(STM32_OPTB_BANK2_BASE + ((n)*8) + 0x4)
+
+#define STM32_OPTB_USER_DBANK BIT(22)
+#define STM32_OPTB_USER_nBOOT1 BIT(23)
+#define STM32_OPTB_USER_nSWBOOT0 BIT(26)
+#define STM32_OPTB_USER_nBOOT0 BIT(27)
 #define STM32_OPTB_ENTRY_NUM 6
 
 /* --- External Interrupts --- */
-#define STM32_EXTI_IMR              REG32(STM32_EXTI_BASE + 0x00)
-#define STM32_EXTI_EMR              REG32(STM32_EXTI_BASE + 0x04)
-#define STM32_EXTI_RTSR             REG32(STM32_EXTI_BASE + 0x08)
-#define STM32_EXTI_FTSR             REG32(STM32_EXTI_BASE + 0x0c)
-#define STM32_EXTI_SWIER            REG32(STM32_EXTI_BASE + 0x10)
-#define STM32_EXTI_PR               REG32(STM32_EXTI_BASE + 0x14)
+#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00)
+#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04)
+#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08)
+#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c)
+#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10)
+#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14)
 
 #define EXTI_RTC_ALR_EVENT BIT(17)
 
 /* --- ADC --- */
-#define STM32_ADC_ISR              REG32(STM32_ADC1_BASE + 0x00)
-#define STM32_ADC_IER              REG32(STM32_ADC1_BASE + 0x04)
-#define STM32_ADC_CR               REG32(STM32_ADC1_BASE + 0x08)
-#define STM32_ADC_CFGR             REG32(STM32_ADC1_BASE + 0x0C)
-#define STM32_ADC_CFGR2            REG32(STM32_ADC1_BASE + 0x10)
-#define STM32_ADC_SMPR1            REG32(STM32_ADC1_BASE + 0x14)
-#define STM32_ADC_SMPR2            REG32(STM32_ADC1_BASE + 0x18)
-#define STM32_ADC_TR1              REG32(STM32_ADC1_BASE + 0x20)
-#define STM32_ADC_TR2              REG32(STM32_ADC1_BASE + 0x24)
-#define STM32_ADC_TR3              REG32(STM32_ADC1_BASE + 0x28)
-#define STM32_ADC_JOFR(n)          REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4)
-#define STM32_ADC_HTR              REG32(STM32_ADC1_BASE + 0x24)
-#define STM32_ADC_LTR              REG32(STM32_ADC1_BASE + 0x28)
-#define STM32_ADC_SQR(n)           REG32(STM32_ADC1_BASE + 0x30 + ((n)&3) * 4)
-#define STM32_ADC_SQR1             REG32(STM32_ADC1_BASE + 0x30)
-#define STM32_ADC_SQR2             REG32(STM32_ADC1_BASE + 0x34)
-#define STM32_ADC_SQR3             REG32(STM32_ADC1_BASE + 0x38)
-#define STM32_ADC_SQR4             REG32(STM32_ADC1_BASE + 0x3C)
-#define STM32_ADC_DR               REG32(STM32_ADC1_BASE + 0x40)
-#define STM32_ADC_JSQR             REG32(STM32_ADC1_BASE + 0x4C)
-#define STM32_ADC_JDR(n)           REG32(STM32_ADC1_BASE + 0x80 + ((n)&3) * 4)
-
+#define STM32_ADC_ISR REG32(STM32_ADC1_BASE + 0x00)
+#define STM32_ADC_IER REG32(STM32_ADC1_BASE + 0x04)
+#define STM32_ADC_CR REG32(STM32_ADC1_BASE + 0x08)
+#define STM32_ADC_CFGR REG32(STM32_ADC1_BASE + 0x0C)
+#define STM32_ADC_CFGR2 REG32(STM32_ADC1_BASE + 0x10)
+#define STM32_ADC_SMPR1 REG32(STM32_ADC1_BASE + 0x14)
+#define STM32_ADC_SMPR2 REG32(STM32_ADC1_BASE + 0x18)
+#define STM32_ADC_TR1 REG32(STM32_ADC1_BASE + 0x20)
+#define STM32_ADC_TR2 REG32(STM32_ADC1_BASE + 0x24)
+#define STM32_ADC_TR3 REG32(STM32_ADC1_BASE + 0x28)
+#define STM32_ADC_JOFR(n) REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4)
+#define STM32_ADC_HTR REG32(STM32_ADC1_BASE + 0x24)
+#define STM32_ADC_LTR REG32(STM32_ADC1_BASE + 0x28)
+#define STM32_ADC_SQR(n) REG32(STM32_ADC1_BASE + 0x30 + ((n)&3) * 4)
+#define STM32_ADC_SQR1 REG32(STM32_ADC1_BASE + 0x30)
+#define STM32_ADC_SQR2 REG32(STM32_ADC1_BASE + 0x34)
+#define STM32_ADC_SQR3 REG32(STM32_ADC1_BASE + 0x38)
+#define STM32_ADC_SQR4 REG32(STM32_ADC1_BASE + 0x3C)
+#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x40)
+#define STM32_ADC_JSQR REG32(STM32_ADC1_BASE + 0x4C)
+#define STM32_ADC_JDR(n) REG32(STM32_ADC1_BASE + 0x80 + ((n)&3) * 4)
 
 /* --- ADC CR Bit Definitions --- */
-#define STM32_ADC_CR_ADEN          BIT(0)
-#define STM32_ADC_CR_ADSTART       BIT(2)
-#define STM32_ADC_CR_ADVREGEN      BIT(28)
-#define STM32_ADC_CR_CAL           BIT(31)
+#define STM32_ADC_CR_ADEN BIT(0)
+#define STM32_ADC_CR_ADSTART BIT(2)
+#define STM32_ADC_CR_ADVREGEN BIT(28)
+#define STM32_ADC_CR_CAL BIT(31)
 
-#define STM32_ADC_CFGR_CONT        BIT(13)
-#define STM32_ADC_CR2_ALIGN        BIT(15)
+#define STM32_ADC_CFGR_CONT BIT(13)
+#define STM32_ADC_CR2_ALIGN BIT(15)
 
 /* --- Comparators --- */
 
-
 /* --- DMA --- */
 /*
  * Available DMA streams, numbered from 0.
@@ -1175,11 +1148,11 @@ enum dma_channel {
 
 /* Registers for a single channel of the DMA controller */
 struct stm32_dma_chan {
-	uint32_t	ccr;		/* Control */
-	uint32_t	cndtr;		/* Number of data to transfer */
-	uint32_t	cpar;		/* Peripheral address */
-	uint32_t	cmar;		/* Memory address */
-	uint32_t	reserved;
+	uint32_t ccr; /* Control */
+	uint32_t cndtr; /* Number of data to transfer */
+	uint32_t cpar; /* Peripheral address */
+	uint32_t cmar; /* Memory address */
+	uint32_t reserved;
 };
 
 /* Always use stm32_dma_chan_t so volatile keyword is included! */
@@ -1190,8 +1163,8 @@ typedef stm32_dma_chan_t dma_chan_t;
 
 /* Registers for the DMA controller */
 struct stm32_dma_regs {
-	uint32_t	isr;
-	uint32_t	ifcr;
+	uint32_t isr;
+	uint32_t ifcr;
 	stm32_dma_chan_t chan[STM32_DMAC_COUNT];
 };
 
@@ -1200,78 +1173,77 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
 
 #define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE)
 
-
-#define STM32_DMA_CCR_CHANNEL(channel)		 (0)
+#define STM32_DMA_CCR_CHANNEL(channel) (0)
 #define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE)
 #define STM32_DMA_REGS(channel) \
 	((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_REGS : STM32_DMA2_REGS)
-#define STM32_DMA_CSELR(channel) \
-	REG32(((channel) < STM32_DMAC_PER_CTLR ? \
-			STM32_DMA1_BASE : STM32_DMA2_BASE)  + 0xA8)
+#define STM32_DMA_CSELR(channel)                                    \
+	REG32(((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_BASE :  \
+						 STM32_DMA2_BASE) + \
+	      0xA8)
 
 /* Bits for DMA controller regs (isr and ifcr) */
-#define STM32_DMA_CH_OFFSET(channel)   (4 * ((channel) % STM32_DMAC_PER_CTLR))
+#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR))
 #define STM32_DMA_ISR_MASK(channel, mask) \
 	((mask) << STM32_DMA_CH_OFFSET(channel))
-#define STM32_DMA_ISR_GIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(0))
-#define STM32_DMA_ISR_TCIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(1))
-#define STM32_DMA_ISR_HTIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(2))
-#define STM32_DMA_ISR_TEIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(3))
-#define STM32_DMA_ISR_ALL(channel)	STM32_DMA_ISR_MASK(channel, 0x0f)
-
-#define STM32_DMA_GIF                   BIT(0)
-#define STM32_DMA_TCIF                  BIT(1)
-#define STM32_DMA_HTIF                  BIT(2)
-#define STM32_DMA_TEIF                  BIT(3)
-#define STM32_DMA_ALL                   0xf
-
-#define STM32_DMA_GET_ISR(channel)      \
-	((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_ISR(channel, val) \
-	(STM32_DMA_REGS(channel)->isr = \
-	((STM32_DMA_REGS(channel)->isr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-#define STM32_DMA_GET_IFCR(channel)      \
-	((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_IFCR(channel, val) \
-	(STM32_DMA_REGS(channel)->ifcr = \
-	((STM32_DMA_REGS(channel)->ifcr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-
+#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0))
+#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1))
+#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2))
+#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3))
+#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f)
+
+#define STM32_DMA_GIF BIT(0)
+#define STM32_DMA_TCIF BIT(1)
+#define STM32_DMA_HTIF BIT(2)
+#define STM32_DMA_TEIF BIT(3)
+#define STM32_DMA_ALL 0xf
+
+#define STM32_DMA_GET_ISR(channel)                                        \
+	((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) & \
+	 STM32_DMA_ALL)
+#define STM32_DMA_SET_ISR(channel, val)                                \
+	(STM32_DMA_REGS(channel)->isr =                                \
+		 ((STM32_DMA_REGS(channel)->isr &                      \
+		   ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
+		  (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
+#define STM32_DMA_GET_IFCR(channel)                                        \
+	((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) & \
+	 STM32_DMA_ALL)
+#define STM32_DMA_SET_IFCR(channel, val)                               \
+	(STM32_DMA_REGS(channel)->ifcr =                               \
+		 ((STM32_DMA_REGS(channel)->ifcr &                     \
+		   ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
+		  (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
 
 /* Bits for DMA channel regs */
-#define STM32_DMA_CCR_EN		BIT(0)
-#define STM32_DMA_CCR_TCIE		BIT(1)
-#define STM32_DMA_CCR_HTIE		BIT(2)
-#define STM32_DMA_CCR_TEIE		BIT(3)
-#define STM32_DMA_CCR_DIR		BIT(4)
-#define STM32_DMA_CCR_CIRC		BIT(5)
-#define STM32_DMA_CCR_PINC		BIT(6)
-#define STM32_DMA_CCR_MINC		BIT(7)
-#define STM32_DMA_CCR_PSIZE_8_BIT	(0 << 8)
-#define STM32_DMA_CCR_PSIZE_16_BIT	(1 << 8)
-#define STM32_DMA_CCR_PSIZE_32_BIT	(2 << 8)
-#define STM32_DMA_CCR_MSIZE_8_BIT	(0 << 10)
-#define STM32_DMA_CCR_MSIZE_16_BIT	(1 << 10)
-#define STM32_DMA_CCR_MSIZE_32_BIT	(2 << 10)
-#define STM32_DMA_CCR_PL_LOW		(0 << 12)
-#define STM32_DMA_CCR_PL_MEDIUM		(1 << 12)
-#define STM32_DMA_CCR_PL_HIGH		(2 << 12)
-#define STM32_DMA_CCR_PL_VERY_HIGH	(3 << 12)
-#define STM32_DMA_CCR_MEM2MEM		BIT(14)
+#define STM32_DMA_CCR_EN BIT(0)
+#define STM32_DMA_CCR_TCIE BIT(1)
+#define STM32_DMA_CCR_HTIE BIT(2)
+#define STM32_DMA_CCR_TEIE BIT(3)
+#define STM32_DMA_CCR_DIR BIT(4)
+#define STM32_DMA_CCR_CIRC BIT(5)
+#define STM32_DMA_CCR_PINC BIT(6)
+#define STM32_DMA_CCR_MINC BIT(7)
+#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8)
+#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8)
+#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8)
+#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10)
+#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10)
+#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10)
+#define STM32_DMA_CCR_PL_LOW (0 << 12)
+#define STM32_DMA_CCR_PL_MEDIUM (1 << 12)
+#define STM32_DMA_CCR_PL_HIGH (2 << 12)
+#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12)
+#define STM32_DMA_CCR_MEM2MEM BIT(14)
 
 /* The requests for the DMA1/DMA2 controllers are routed through DMAMUX. */
 /* DMAMUX registers */
-#define STM32_DMAMUX_CxCR(x)      REG32(STM32_DMAMUX_BASE + 4 * (x))
-#define STM32_DMAMUX_CSR          REG32(STM32_DMAMUX_BASE + 0x80)
-#define STM32_DMAMUX_CFR          REG32(STM32_DMAMUX_BASE + 0x84)
-#define STM32_DMAMUX_RGxCR(x)     REG32(STM32_DMAMUX_BASE + 0x100 + 4 * (x))
-#define STM32_DMAMUX_RGSR         REG32(STM32_DMAMUX_BASE + 0x140)
-#define STM32_DMAMUX_RGCFR        REG32(STM32_DMAMUX_BASE + 0x144)
+#define STM32_DMAMUX_CxCR(x) REG32(STM32_DMAMUX_BASE + 4 * (x))
+#define STM32_DMAMUX_CSR REG32(STM32_DMAMUX_BASE + 0x80)
+#define STM32_DMAMUX_CFR REG32(STM32_DMAMUX_BASE + 0x84)
+#define STM32_DMAMUX_RGxCR(x) REG32(STM32_DMAMUX_BASE + 0x100 + 4 * (x))
+#define STM32_DMAMUX_RGSR REG32(STM32_DMAMUX_BASE + 0x140)
+#define STM32_DMAMUX_RGCFR REG32(STM32_DMAMUX_BASE + 0x144)
 
 enum dmamux1_request {
 	DMAMUX_REQ_ADC1 = 5,
@@ -1378,94 +1350,41 @@ enum dmamux1_request {
 #define DMAMUX_REQ_UART9_TX DMAMUX_REQ_LPUART1_TX
 
 /* --- CRC --- */
-#define STM32_CRC_DR                REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR32              REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR16              REG16(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR8               REG8(STM32_CRC_BASE + 0x0)
-
-#define STM32_CRC_IDR               REG32(STM32_CRC_BASE + 0x4)
-#define STM32_CRC_CR                REG32(STM32_CRC_BASE + 0x8)
-#define STM32_CRC_INIT              REG32(STM32_CRC_BASE + 0x10)
-#define STM32_CRC_POL               REG32(STM32_CRC_BASE + 0x14)
-
-#define STM32_CRC_CR_RESET          BIT(0)
-#define STM32_CRC_CR_POLYSIZE_32    (0 << 3)
-#define STM32_CRC_CR_POLYSIZE_16    (1 << 3)
-#define STM32_CRC_CR_POLYSIZE_8     (2 << 3)
-#define STM32_CRC_CR_POLYSIZE_7     (3 << 3)
-#define STM32_CRC_CR_REV_IN_BYTE    (1 << 5)
-#define STM32_CRC_CR_REV_IN_HWORD   (2 << 5)
-#define STM32_CRC_CR_REV_IN_WORD    (3 << 5)
-#define STM32_CRC_CR_REV_OUT        BIT(7)
-
+#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0)
+
+#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4)
+#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8)
+#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10)
+#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14)
+
+#define STM32_CRC_CR_RESET BIT(0)
+#define STM32_CRC_CR_POLYSIZE_32 (0 << 3)
+#define STM32_CRC_CR_POLYSIZE_16 (1 << 3)
+#define STM32_CRC_CR_POLYSIZE_8 (2 << 3)
+#define STM32_CRC_CR_POLYSIZE_7 (3 << 3)
+#define STM32_CRC_CR_REV_IN_BYTE (1 << 5)
+#define STM32_CRC_CR_REV_IN_HWORD (2 << 5)
+#define STM32_CRC_CR_REV_IN_WORD (3 << 5)
+#define STM32_CRC_CR_REV_OUT BIT(7)
 
 /* --- USB --- */
-#define STM32_USB_EP(n)            REG16(STM32_USB_FS_BASE + (n) * 4)
-
-#define STM32_USB_CNTR             REG16(STM32_USB_FS_BASE + 0x40)
-
-#define STM32_USB_CNTR_FRES	    BIT(0)
-#define STM32_USB_CNTR_PDWN	    BIT(1)
-#define STM32_USB_CNTR_LP_MODE	    BIT(2)
-#define STM32_USB_CNTR_FSUSP	    BIT(3)
-#define STM32_USB_CNTR_RESUME	    BIT(4)
-#define STM32_USB_CNTR_L1RESUME	    BIT(5)
-#define STM32_USB_CNTR_L1REQM	    BIT(7)
-#define STM32_USB_CNTR_ESOFM	    BIT(8)
-#define STM32_USB_CNTR_SOFM	    BIT(9)
-#define STM32_USB_CNTR_RESETM	    BIT(10)
-#define STM32_USB_CNTR_SUSPM	    BIT(11)
-#define STM32_USB_CNTR_WKUPM	    BIT(12)
-#define STM32_USB_CNTR_ERRM	    BIT(13)
-#define STM32_USB_CNTR_PMAOVRM	    BIT(14)
-#define STM32_USB_CNTR_CTRM	    BIT(15)
-
-#define STM32_USB_ISTR             REG16(STM32_USB_FS_BASE + 0x44)
-
-#define STM32_USB_ISTR_EP_ID_MASK   (0x000f)
-#define STM32_USB_ISTR_DIR	    BIT(4)
-#define STM32_USB_ISTR_L1REQ	    BIT(7)
-#define STM32_USB_ISTR_ESOF	    BIT(8)
-#define STM32_USB_ISTR_SOF	    BIT(9)
-#define STM32_USB_ISTR_RESET	    BIT(10)
-#define STM32_USB_ISTR_SUSP	    BIT(11)
-#define STM32_USB_ISTR_WKUP	    BIT(12)
-#define STM32_USB_ISTR_ERR	    BIT(13)
-#define STM32_USB_ISTR_PMAOVR	    BIT(14)
-#define STM32_USB_ISTR_CTR	    BIT(15)
-
-#define STM32_USB_FNR              REG16(STM32_USB_FS_BASE + 0x48)
-
-#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14)
-#define STM32_USB_FNR_RXDP_RXDM_MASK  (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT)
-
-#define STM32_USB_DADDR            REG16(STM32_USB_FS_BASE + 0x4C)
-#define STM32_USB_BTABLE           REG16(STM32_USB_FS_BASE + 0x50)
-#define STM32_USB_LPMCSR           REG16(STM32_USB_FS_BASE + 0x54)
-#define STM32_USB_BCDR             REG16(STM32_USB_FS_BASE + 0x58)
-
-#define STM32_USB_BCDR_BCDEN	    BIT(0)
-#define STM32_USB_BCDR_DCDEN	    BIT(1)
-#define STM32_USB_BCDR_PDEN	    BIT(2)
-#define STM32_USB_BCDR_SDEN	    BIT(3)
-#define STM32_USB_BCDR_DCDET	    BIT(4)
-#define STM32_USB_BCDR_PDET	    BIT(5)
-#define STM32_USB_BCDR_SDET	    BIT(6)
-#define STM32_USB_BCDR_PS2DET	    BIT(7)
-#define STM32_USB_BCDR_DPPU	    BIT(15)
+#define STM32_USB_BCDR_DPPU BIT(15)
 
 /* --- USB Endpoint bit definitions  --- */
-#define EP_MASK     0x0F0F
-#define EP_TX_DTOG  0x0040
-#define EP_TX_MASK  0x0030
+#define EP_MASK 0x0F0F
+#define EP_TX_DTOG 0x0040
+#define EP_TX_MASK 0x0030
 #define EP_TX_VALID 0x0030
-#define EP_TX_NAK   0x0020
+#define EP_TX_NAK 0x0020
 #define EP_TX_STALL 0x0010
 #define EP_TX_DISAB 0x0000
-#define EP_RX_DTOG  0x4000
-#define EP_RX_MASK  0x3000
+#define EP_RX_DTOG 0x4000
+#define EP_RX_MASK 0x3000
 #define EP_RX_VALID 0x3000
-#define EP_RX_NAK   0x2000
+#define EP_RX_NAK 0x2000
 #define EP_RX_STALL 0x1000
 #define EP_RX_DISAB 0x0000
 
@@ -1475,31 +1394,30 @@ enum dmamux1_request {
 #define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID)
 
 #define STM32_TOGGLE_EP(n, mask, val, flags) \
-	STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \
-			^ (val)) | (flags))
+	STM32_USB_EP(n) =                    \
+		(((STM32_USB_EP(n) & (EP_MASK | (mask))) ^ (val)) | (flags))
 
 /* --- TRNG --- */
-#define STM32_RNG_CR                REG32(STM32_RNG_BASE + 0x0)
-#define STM32_RNG_SR                REG32(STM32_RNG_BASE + 0x4)
-#define STM32_RNG_DR                REG32(STM32_RNG_BASE + 0x8)
+#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0)
+#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4)
+#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8)
 
 /* --- RNG CR Bit Definitions --- */
-#define STM32_RNG_CR_RNGEN          BIT(2)
-#define STM32_RNG_CR_IE             BIT(3)
-#define STM32_RNG_CR_CED            BIT(5)
+#define STM32_RNG_CR_RNGEN BIT(2)
+#define STM32_RNG_CR_IE BIT(3)
+#define STM32_RNG_CR_CED BIT(5)
 /* --- RNG SR_DRDY Bit Definitions --- */
-#define STM32_RNG_SR_DRDY           BIT(0)
+#define STM32_RNG_SR_DRDY BIT(0)
 
 /* --- AXI interconnect --- */
 
 /* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */
-#define STM32_AXI_TARG_FN_MOD(x)    REG32(STM32_GPV_BASE + 0x1108 + \
-					  0x1000 * (x))
-#define  WRITE_ISS_OVERRIDE         BIT(1)
-#define  READ_ISS_OVERRIDE          BIT(0)
+#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + 0x1000 * (x))
+#define WRITE_ISS_OVERRIDE BIT(1)
+#define READ_ISS_OVERRIDE BIT(0)
 
 /* --- MISC --- */
-#define STM32_UNIQUE_ID_ADDRESS     REG32_ADDR(STM32_UNIQUE_ID_BASE)
-#define STM32_UNIQUE_ID_LENGTH      (3 * 4)
+#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE)
+#define STM32_UNIQUE_ID_LENGTH (3 * 4)
 
 #endif /* !__ASSEMBLER__ */
diff --git a/chip/stm32/registers-stm32h7.h b/chip/stm32/registers-stm32h7.h
index 1ae8e3bdaa..f4178d17f0 100644
--- a/chip/stm32/registers-stm32h7.h
+++ b/chip/stm32/registers-stm32h7.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,591 +19,586 @@
 #endif
 
 /* --- IRQ numbers --- */
-#define STM32_IRQ_WWDG             0
-#define STM32_IRQ_PVD              1
-#define STM32_IRQ_TAMPER_STAMP     2
-#define STM32_IRQ_RTC_WAKEUP       3
-#define STM32_IRQ_FLASH            4
-#define STM32_IRQ_RCC              5
-#define STM32_IRQ_EXTI0            6
-#define STM32_IRQ_EXTI1            7
-#define STM32_IRQ_EXTI2            8
-#define STM32_IRQ_EXTI3            9
-#define STM32_IRQ_EXTI4           10
-#define STM32_IRQ_DMA_CHANNEL_1   11
-#define STM32_IRQ_DMA_CHANNEL_2   12
-#define STM32_IRQ_DMA_CHANNEL_3   13
-#define STM32_IRQ_DMA_CHANNEL_4   14
-#define STM32_IRQ_DMA_CHANNEL_5   15
-#define STM32_IRQ_DMA_CHANNEL_6   16
-#define STM32_IRQ_DMA_CHANNEL_7   17
-#define STM32_IRQ_USB_HP          19
-#define STM32_IRQ_USB_LP          20
-
-#define STM32_IRQ_ADC1            18 /* STM32L4 only */
-#define STM32_IRQ_CAN_TX          19 /* STM32F373 only */
-#define STM32_IRQ_USB_LP_CAN_RX   20 /* STM32F373 only */
-#define STM32_IRQ_DAC             21
-#define STM32_IRQ_CAN_RX1         21 /* STM32F373 only */
-
-#define STM32_IRQ_COMP            22
-
-#define STM32_IRQ_CAN_SCE         22 /* STM32F373 only */
-#define STM32_IRQ_EXTI9_5         23
-#define STM32_IRQ_TIM2            28
-#define STM32_IRQ_TIM3            29
-#define STM32_IRQ_TIM4            30
-#define STM32_IRQ_I2C1_EV         31
-#define STM32_IRQ_I2C1_ER         32
-#define STM32_IRQ_I2C2_EV         33
-#define STM32_IRQ_I2C2_ER         34
-#define STM32_IRQ_SPI1            35
-#define STM32_IRQ_SPI2            36
-#define STM32_IRQ_USART1          37
-#define STM32_IRQ_USART2          38
-#define STM32_IRQ_USART3          39
-#define STM32_IRQ_EXTI15_10       40
-#define STM32_IRQ_RTC_ALARM       41
-#define STM32_IRQ_USB_FS_WAKEUP   42 /* STM32L15X */
-#define STM32_IRQ_CEC             42 /* STM32F373 only */
-#define STM32_IRQ_TIM6_BASIC      43 /* STM32L15X only */
-#define STM32_IRQ_TIM12           43 /* STM32F373 only */
-#define STM32_IRQ_TIM7_BASIC      44 /* STM32L15X only */
-#define STM32_IRQ_TIM13           44 /* STM32F373 only */
-#define STM32_IRQ_TIM14           45 /* STM32F373 only */
-#define STM32_IRQ_TIM5            50 /* STM32F373 */
-#define STM32_IRQ_SPI3            51 /* STM32F373 */
-#define STM32_IRQ_USART4          52 /* STM32F446 only */
-#define STM32_IRQ_USART5          53 /* STM32F446 only */
-#define STM32_IRQ_TIM6_DAC        54 /* STM32F373 */
-#define STM32_IRQ_TIM7            55 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL1   56 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL2   57 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL3   58 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL4   59 /* STM32F373 only */
+#define STM32_IRQ_WWDG 0
+#define STM32_IRQ_PVD 1
+#define STM32_IRQ_TAMPER_STAMP 2
+#define STM32_IRQ_RTC_WAKEUP 3
+#define STM32_IRQ_FLASH 4
+#define STM32_IRQ_RCC 5
+#define STM32_IRQ_EXTI0 6
+#define STM32_IRQ_EXTI1 7
+#define STM32_IRQ_EXTI2 8
+#define STM32_IRQ_EXTI3 9
+#define STM32_IRQ_EXTI4 10
+#define STM32_IRQ_DMA_CHANNEL_1 11
+#define STM32_IRQ_DMA_CHANNEL_2 12
+#define STM32_IRQ_DMA_CHANNEL_3 13
+#define STM32_IRQ_DMA_CHANNEL_4 14
+#define STM32_IRQ_DMA_CHANNEL_5 15
+#define STM32_IRQ_DMA_CHANNEL_6 16
+#define STM32_IRQ_DMA_CHANNEL_7 17
+#define STM32_IRQ_USB_HP 19
+#define STM32_IRQ_USB_LP 20
+
+#define STM32_IRQ_ADC1 18 /* STM32L4 only */
+#define STM32_IRQ_CAN_TX 19 /* STM32F373 only */
+#define STM32_IRQ_USB_LP_CAN_RX 20 /* STM32F373 only */
+#define STM32_IRQ_DAC 21
+#define STM32_IRQ_CAN_RX1 21 /* STM32F373 only */
+
+#define STM32_IRQ_COMP 22
+
+#define STM32_IRQ_CAN_SCE 22 /* STM32F373 only */
+#define STM32_IRQ_EXTI9_5 23
+#define STM32_IRQ_TIM2 28
+#define STM32_IRQ_TIM3 29
+#define STM32_IRQ_TIM4 30
+#define STM32_IRQ_I2C1_EV 31
+#define STM32_IRQ_I2C1_ER 32
+#define STM32_IRQ_I2C2_EV 33
+#define STM32_IRQ_I2C2_ER 34
+#define STM32_IRQ_SPI1 35
+#define STM32_IRQ_SPI2 36
+#define STM32_IRQ_USART1 37
+#define STM32_IRQ_USART2 38
+#define STM32_IRQ_USART3 39
+#define STM32_IRQ_EXTI15_10 40
+#define STM32_IRQ_RTC_ALARM 41
+#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X */
+#define STM32_IRQ_CEC 42 /* STM32F373 only */
+#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */
+#define STM32_IRQ_TIM12 43 /* STM32F373 only */
+#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */
+#define STM32_IRQ_TIM13 44 /* STM32F373 only */
+#define STM32_IRQ_TIM14 45 /* STM32F373 only */
+#define STM32_IRQ_TIM5 50 /* STM32F373 */
+#define STM32_IRQ_SPI3 51 /* STM32F373 */
+#define STM32_IRQ_USART4 52 /* STM32F446 only */
+#define STM32_IRQ_USART5 53 /* STM32F446 only */
+#define STM32_IRQ_TIM6_DAC 54 /* STM32F373 */
+#define STM32_IRQ_TIM7 55 /* STM32F373 */
+#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F373 */
+#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F373 */
+#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F373 */
+#define STM32_IRQ_DMA2_CHANNEL4 59 /* STM32F373 only */
 /* if MISC_REMAP bits are set */
-#define STM32_IRQ_DMA2_CHANNEL5   60 /* STM32F373 */
-#define STM32_IRQ_SDADC1          61 /* STM32F373 only */
-#define STM32_IRQ_SDADC2          62 /* STM32F373 only */
-#define STM32_IRQ_SDADC3          63 /* STM32F373 only */
-#define STM32_IRQ_DMA2_CHANNEL6   68 /* STM32L4 only */
-#define STM32_IRQ_DMA2_CHANNEL7   69 /* STM32L4 only */
-#define STM32_IRQ_LPUART          70 /* STM32L4 only */
-#define STM32_IRQ_USART9          70 /* STM32L4 only */
-#define STM32_IRQ_USART6          71 /* STM32F446 only */
-#define STM32_IRQ_I2C3_EV         72 /* STM32F446 only */
-#define STM32_IRQ_I2C3_ER         73 /* STM32F446 only */
-#define STM32_IRQ_USB_WAKEUP      76 /* STM32F373 only */
-#define STM32_IRQ_TIM19           78 /* STM32F373 only */
-#define STM32_IRQ_AES             79 /* STM32L4 only */
-#define STM32_IRQ_RNG             80 /* STM32L4 only */
-#define STM32_IRQ_FPU             81 /* STM32F373 only */
-
-#define STM32_IRQ_LPTIM1         93
-#define STM32_IRQ_TIM15         116
-#define STM32_IRQ_TIM16         117
-#define STM32_IRQ_TIM17         118
-#define STM32_IRQ_LPTIM2        138
-#define STM32_IRQ_LPTIM3        139
-#define STM32_IRQ_LPTIM4        140
-#define STM32_IRQ_LPTIM5        141
+#define STM32_IRQ_DMA2_CHANNEL5 60 /* STM32F373 */
+#define STM32_IRQ_SDADC1 61 /* STM32F373 only */
+#define STM32_IRQ_SDADC2 62 /* STM32F373 only */
+#define STM32_IRQ_SDADC3 63 /* STM32F373 only */
+#define STM32_IRQ_DMA2_CHANNEL6 68 /* STM32L4 only */
+#define STM32_IRQ_DMA2_CHANNEL7 69 /* STM32L4 only */
+#define STM32_IRQ_LPUART 70 /* STM32L4 only */
+#define STM32_IRQ_USART9 70 /* STM32L4 only */
+#define STM32_IRQ_USART6 71 /* STM32F446 only */
+#define STM32_IRQ_I2C3_EV 72 /* STM32F446 only */
+#define STM32_IRQ_I2C3_ER 73 /* STM32F446 only */
+#define STM32_IRQ_USB_WAKEUP 76 /* STM32F373 only */
+#define STM32_IRQ_TIM19 78 /* STM32F373 only */
+#define STM32_IRQ_AES 79 /* STM32L4 only */
+#define STM32_IRQ_RNG 80 /* STM32L4 only */
+#define STM32_IRQ_FPU 81 /* STM32F373 only */
+
+#define STM32_IRQ_LPTIM1 93
+#define STM32_IRQ_TIM15 116
+#define STM32_IRQ_TIM16 117
+#define STM32_IRQ_TIM17 118
+#define STM32_IRQ_LPTIM2 138
+#define STM32_IRQ_LPTIM3 139
+#define STM32_IRQ_LPTIM4 140
+#define STM32_IRQ_LPTIM5 141
 
 /* To simplify code generation, define DMA channel 9..10 */
-#define STM32_IRQ_DMA_CHANNEL_9    STM32_IRQ_DMA2_CHANNEL1
-#define STM32_IRQ_DMA_CHANNEL_10   STM32_IRQ_DMA2_CHANNEL2
-#define STM32_IRQ_DMA_CHANNEL_13   STM32_IRQ_DMA2_CHANNEL6
-#define STM32_IRQ_DMA_CHANNEL_14   STM32_IRQ_DMA2_CHANNEL7
+#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1
+#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2
+#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6
+#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7
 
 /* aliases for easier code sharing */
 #define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV
 #define STM32_IRQ_I2C2 STM32_IRQ_I2C2_EV
 #define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV
 
-
 /*
  * STM32F4 introduces a concept of DMA stream to allow
  * fine allocation of a stream to a channel.
  */
-#define STM32_IRQ_DMA1_STREAM0    11
-#define STM32_IRQ_DMA1_STREAM1    12
-#define STM32_IRQ_DMA1_STREAM2    13
-#define STM32_IRQ_DMA1_STREAM3    14
-#define STM32_IRQ_DMA1_STREAM4    15
-#define STM32_IRQ_DMA1_STREAM5    16
-#define STM32_IRQ_DMA1_STREAM6    17
-#define STM32_IRQ_DMA1_STREAM7    47
-#define STM32_IRQ_DMA2_STREAM0    56
-#define STM32_IRQ_DMA2_STREAM1    57
-#define STM32_IRQ_DMA2_STREAM2    58
-#define STM32_IRQ_DMA2_STREAM3    59
-#define STM32_IRQ_DMA2_STREAM4    60
-#define STM32_IRQ_DMA2_STREAM5    68
-#define STM32_IRQ_DMA2_STREAM6    69
-#define STM32_IRQ_DMA2_STREAM7    70
-
-#define STM32_IRQ_OTG_HS_WKUP     76
-#define STM32_IRQ_OTG_HS_EP1_IN   75
-#define STM32_IRQ_OTG_HS_EP1_OUT  74
-#define STM32_IRQ_OTG_HS          77
-#define STM32_IRQ_OTG_FS          67
-#define STM32_IRQ_OTG_FS_WKUP     42
+#define STM32_IRQ_DMA1_STREAM0 11
+#define STM32_IRQ_DMA1_STREAM1 12
+#define STM32_IRQ_DMA1_STREAM2 13
+#define STM32_IRQ_DMA1_STREAM3 14
+#define STM32_IRQ_DMA1_STREAM4 15
+#define STM32_IRQ_DMA1_STREAM5 16
+#define STM32_IRQ_DMA1_STREAM6 17
+#define STM32_IRQ_DMA1_STREAM7 47
+#define STM32_IRQ_DMA2_STREAM0 56
+#define STM32_IRQ_DMA2_STREAM1 57
+#define STM32_IRQ_DMA2_STREAM2 58
+#define STM32_IRQ_DMA2_STREAM3 59
+#define STM32_IRQ_DMA2_STREAM4 60
+#define STM32_IRQ_DMA2_STREAM5 68
+#define STM32_IRQ_DMA2_STREAM6 69
+#define STM32_IRQ_DMA2_STREAM7 70
+
+#define STM32_IRQ_OTG_HS_WKUP 76
+#define STM32_IRQ_OTG_HS_EP1_IN 75
+#define STM32_IRQ_OTG_HS_EP1_OUT 74
+#define STM32_IRQ_OTG_HS 77
+#define STM32_IRQ_OTG_FS 67
+#define STM32_IRQ_OTG_FS_WKUP 42
 
 /* Peripheral base addresses */
 
-#define STM32_GPV_BASE              0x51000000
-
-#define STM32_DBGMCU_BASE           0x5C001000
-
-#define STM32_BDMA_BASE             0x58025400
-#define STM32_DMA1_BASE             0x40020000
-#define STM32_DMA2_BASE             0x40020400
-#define STM32_DMA2D_BASE            0x52001000
-#define STM32_DMAMUX1_BASE          0x40020800
-#define STM32_DMAMUX2_BASE          0x58025800
-#define STM32_MDMA_BASE             0x52000000
-
-#define STM32_EXTI_BASE             0x58000000
-
-#define STM32_FLASH_REGS_BASE       0x52002000
-
-#define STM32_GPIOA_BASE            0x58020000
-#define STM32_GPIOB_BASE            0x58020400
-#define STM32_GPIOC_BASE            0x58020800
-#define STM32_GPIOD_BASE            0x58020C00
-#define STM32_GPIOE_BASE            0x58021000
-#define STM32_GPIOF_BASE            0x58021400
-#define STM32_GPIOG_BASE            0x58021800
-#define STM32_GPIOH_BASE            0x58021C00
-#define STM32_GPIOI_BASE            0x58022000
-#define STM32_GPIOJ_BASE            0x58022400
-#define STM32_GPIOK_BASE            0x58022800
-
-#define STM32_IWDG_BASE             0x58004800
-
-#define STM32_LPTIM1_BASE           0x40002400
-#define STM32_LPTIM2_BASE           0x58002400
-#define STM32_LPTIM3_BASE           0x58002800
-#define STM32_LPTIM4_BASE           0x58002C00
-#define STM32_LPTIM5_BASE           0x58003000
-
-#define STM32_PWR_BASE              0x58024800
-#define STM32_RCC_BASE              0x58024400
-#define STM32_RNG_BASE              0x48021800
-#define STM32_RTC_BASE              0x58004000
-
-#define STM32_SYSCFG_BASE           0x58000400
-
-#define STM32_SPI1_BASE             0x40013000
-#define STM32_SPI2_BASE             0x40003800
-#define STM32_SPI3_BASE             0x40003c00
-#define STM32_SPI4_BASE             0x40013400
-#define STM32_SPI5_BASE             0x40015000
-
-#define STM32_TIM1_BASE             0x40010000
-#define STM32_TIM2_BASE             0x40000000
-#define STM32_TIM3_BASE             0x40000400
-#define STM32_TIM4_BASE             0x40000800
-#define STM32_TIM5_BASE             0x40000c00
-#define STM32_TIM6_BASE             0x40001000
-#define STM32_TIM7_BASE             0x40001400
-#define STM32_TIM8_BASE             0x40010400
-#define STM32_TIM12_BASE            0x40001800
-#define STM32_TIM13_BASE            0x40001c00
-#define STM32_TIM14_BASE            0x40002000
-#define STM32_TIM15_BASE            0x40014000
-#define STM32_TIM16_BASE            0x40014400
-#define STM32_TIM17_BASE            0x40014800
-
-#define STM32_UNIQUE_ID_BASE        0x1ff1e800
-
-#define STM32_USART1_BASE           0x40011000
-#define STM32_USART2_BASE           0x40004400
-#define STM32_USART3_BASE           0x40004800
-#define STM32_USART4_BASE           0x40004c00
-#define STM32_USART5_BASE           0x40005000
-#define STM32_USART6_BASE           0x40011400
-#define STM32_USART7_BASE           0x40007800
-#define STM32_USART8_BASE           0x40007C00
+#define STM32_GPV_BASE 0x51000000
+
+#define STM32_DBGMCU_BASE 0x5C001000
+
+#define STM32_BDMA_BASE 0x58025400
+#define STM32_DMA1_BASE 0x40020000
+#define STM32_DMA2_BASE 0x40020400
+#define STM32_DMA2D_BASE 0x52001000
+#define STM32_DMAMUX1_BASE 0x40020800
+#define STM32_DMAMUX2_BASE 0x58025800
+#define STM32_MDMA_BASE 0x52000000
+
+#define STM32_EXTI_BASE 0x58000000
+
+#define STM32_FLASH_REGS_BASE 0x52002000
+
+#define STM32_GPIOA_BASE 0x58020000
+#define STM32_GPIOB_BASE 0x58020400
+#define STM32_GPIOC_BASE 0x58020800
+#define STM32_GPIOD_BASE 0x58020C00
+#define STM32_GPIOE_BASE 0x58021000
+#define STM32_GPIOF_BASE 0x58021400
+#define STM32_GPIOG_BASE 0x58021800
+#define STM32_GPIOH_BASE 0x58021C00
+#define STM32_GPIOI_BASE 0x58022000
+#define STM32_GPIOJ_BASE 0x58022400
+#define STM32_GPIOK_BASE 0x58022800
+
+#define STM32_IWDG_BASE 0x58004800
+
+#define STM32_LPTIM1_BASE 0x40002400
+#define STM32_LPTIM2_BASE 0x58002400
+#define STM32_LPTIM3_BASE 0x58002800
+#define STM32_LPTIM4_BASE 0x58002C00
+#define STM32_LPTIM5_BASE 0x58003000
+
+#define STM32_PWR_BASE 0x58024800
+#define STM32_RCC_BASE 0x58024400
+#define STM32_RNG_BASE 0x48021800
+#define STM32_RTC_BASE 0x58004000
+
+#define STM32_SYSCFG_BASE 0x58000400
+
+#define STM32_SPI1_BASE 0x40013000
+#define STM32_SPI2_BASE 0x40003800
+#define STM32_SPI3_BASE 0x40003c00
+#define STM32_SPI4_BASE 0x40013400
+#define STM32_SPI5_BASE 0x40015000
+
+#define STM32_TIM1_BASE 0x40010000
+#define STM32_TIM2_BASE 0x40000000
+#define STM32_TIM3_BASE 0x40000400
+#define STM32_TIM4_BASE 0x40000800
+#define STM32_TIM5_BASE 0x40000c00
+#define STM32_TIM6_BASE 0x40001000
+#define STM32_TIM7_BASE 0x40001400
+#define STM32_TIM8_BASE 0x40010400
+#define STM32_TIM12_BASE 0x40001800
+#define STM32_TIM13_BASE 0x40001c00
+#define STM32_TIM14_BASE 0x40002000
+#define STM32_TIM15_BASE 0x40014000
+#define STM32_TIM16_BASE 0x40014400
+#define STM32_TIM17_BASE 0x40014800
+
+#define STM32_UNIQUE_ID_BASE 0x1ff1e800
+
+#define STM32_USART1_BASE 0x40011000
+#define STM32_USART2_BASE 0x40004400
+#define STM32_USART3_BASE 0x40004800
+#define STM32_USART4_BASE 0x40004c00
+#define STM32_USART5_BASE 0x40005000
+#define STM32_USART6_BASE 0x40011400
+#define STM32_USART7_BASE 0x40007800
+#define STM32_USART8_BASE 0x40007C00
 
 #ifndef __ASSEMBLER__
 
 /* Register definitions */
 
 /* --- USART --- */
-#define STM32_USART_CR1(base)         STM32_USART_REG(base, 0x00)
-#define  STM32_USART_CR1_UE            BIT(0)
-#define  STM32_USART_CR1_UESM          BIT(1)
-#define  STM32_USART_CR1_RE            BIT(2)
-#define  STM32_USART_CR1_TE            BIT(3)
-#define  STM32_USART_CR1_RXNEIE        BIT(5)
-#define  STM32_USART_CR1_TCIE          BIT(6)
-#define  STM32_USART_CR1_TXEIE         BIT(7)
-#define  STM32_USART_CR1_PS            BIT(9)
-#define  STM32_USART_CR1_PCE           BIT(10)
-#define  STM32_USART_CR1_M             BIT(12)
-#define  STM32_USART_CR1_OVER8         BIT(15)
-#define STM32_USART_CR2(base)         STM32_USART_REG(base, 0x04)
-#define  STM32_USART_CR2_SWAP          BIT(15)
-#define STM32_USART_CR3(base)         STM32_USART_REG(base, 0x08)
-#define  STM32_USART_CR3_EIE           BIT(0)
-#define  STM32_USART_CR3_DMAR          BIT(6)
-#define  STM32_USART_CR3_DMAT          BIT(7)
-#define  STM32_USART_CR3_ONEBIT        BIT(11)
-#define  STM32_USART_CR3_OVRDIS        BIT(12)
-#define  STM32_USART_CR3_WUS_START_BIT (2 << 20)
-#define  STM32_USART_CR3_WUFIE         BIT(22)
-#define STM32_USART_BRR(base)         STM32_USART_REG(base, 0x0C)
-#define STM32_USART_GTPR(base)        STM32_USART_REG(base, 0x10)
-#define STM32_USART_RTOR(base)        STM32_USART_REG(base, 0x14)
-#define STM32_USART_RQR(base)         STM32_USART_REG(base, 0x18)
-#define STM32_USART_ISR(base)         STM32_USART_REG(base, 0x1C)
-#define STM32_USART_ICR(base)         STM32_USART_REG(base, 0x20)
-#define  STM32_USART_ICR_ORECF         BIT(3)
-#define  STM32_USART_ICR_TCCF          BIT(6)
-#define STM32_USART_RDR(base)         STM32_USART_REG(base, 0x24)
-#define STM32_USART_TDR(base)         STM32_USART_REG(base, 0x28)
-#define STM32_USART_PRESC(base)       STM32_USART_REG(base, 0x2C)
+#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00)
+#define STM32_USART_CR1_UE BIT(0)
+#define STM32_USART_CR1_UESM BIT(1)
+#define STM32_USART_CR1_RE BIT(2)
+#define STM32_USART_CR1_TE BIT(3)
+#define STM32_USART_CR1_RXNEIE BIT(5)
+#define STM32_USART_CR1_TCIE BIT(6)
+#define STM32_USART_CR1_TXEIE BIT(7)
+#define STM32_USART_CR1_PS BIT(9)
+#define STM32_USART_CR1_PCE BIT(10)
+#define STM32_USART_CR1_M BIT(12)
+#define STM32_USART_CR1_OVER8 BIT(15)
+#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04)
+#define STM32_USART_CR2_SWAP BIT(15)
+#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08)
+#define STM32_USART_CR3_EIE BIT(0)
+#define STM32_USART_CR3_DMAR BIT(6)
+#define STM32_USART_CR3_DMAT BIT(7)
+#define STM32_USART_CR3_ONEBIT BIT(11)
+#define STM32_USART_CR3_OVRDIS BIT(12)
+#define STM32_USART_CR3_WUS_START_BIT (2 << 20)
+#define STM32_USART_CR3_WUFIE BIT(22)
+#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C)
+#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10)
+#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14)
+#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18)
+#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C)
+#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20)
+#define STM32_USART_ICR_ORECF BIT(3)
+#define STM32_USART_ICR_TCCF BIT(6)
+#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24)
+#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28)
+#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C)
 /* register alias */
-#define STM32_USART_SR(base)          STM32_USART_ISR(base)
-#define  STM32_USART_SR_ORE            BIT(3)
-#define  STM32_USART_SR_RXNE           BIT(5)
-#define  STM32_USART_SR_TC             BIT(6)
-#define  STM32_USART_SR_TXE            BIT(7)
+#define STM32_USART_SR(base) STM32_USART_ISR(base)
+#define STM32_USART_SR_ORE BIT(3)
+#define STM32_USART_SR_RXNE BIT(5)
+#define STM32_USART_SR_TC BIT(6)
+#define STM32_USART_SR_TXE BIT(7)
 
 /* --- GPIO --- */
 
-
-#define STM32_GPIO_MODER(b)           REG32((b) + 0x00)
-#define STM32_GPIO_OTYPER(b)          REG16((b) + 0x04)
-#define STM32_GPIO_OSPEEDR(b)         REG32((b) + 0x08)
-#define STM32_GPIO_PUPDR(b)           REG32((b) + 0x0C)
-#define STM32_GPIO_IDR(b)             REG16((b) + 0x10)
-#define STM32_GPIO_ODR(b)             REG16((b) + 0x14)
-#define STM32_GPIO_BSRR(b)            REG32((b) + 0x18)
-#define STM32_GPIO_LCKR(b)            REG32((b) + 0x1C)
-#define STM32_GPIO_AFRL(b)            REG32((b) + 0x20)
-#define STM32_GPIO_AFRH(b)            REG32((b) + 0x24)
-
-#define GPIO_ALT_SYS                 0x0
-#define GPIO_ALT_TIM2                0x1
-#define GPIO_ALT_TIM3_4              0x2
-#define GPIO_ALT_TIM9_11             0x3
-#define GPIO_ALT_I2C                 0x4
-#define GPIO_ALT_SPI                 0x5
-#define GPIO_ALT_SPI3                0x6
-#define GPIO_ALT_USART               0x7
-#define GPIO_ALT_I2C_23              0x9
-#define GPIO_ALT_USB                 0xA
-#define GPIO_ALT_LCD                 0xB
-#define GPIO_ALT_RI                  0xE
-#define GPIO_ALT_EVENTOUT            0xF
+#define STM32_GPIO_MODER(b) REG32((b) + 0x00)
+#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04)
+#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08)
+#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C)
+#define STM32_GPIO_IDR(b) REG16((b) + 0x10)
+#define STM32_GPIO_ODR(b) REG16((b) + 0x14)
+#define STM32_GPIO_BSRR(b) REG32((b) + 0x18)
+#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C)
+#define STM32_GPIO_AFRL(b) REG32((b) + 0x20)
+#define STM32_GPIO_AFRH(b) REG32((b) + 0x24)
+
+#define GPIO_ALT_SYS 0x0
+#define GPIO_ALT_TIM2 0x1
+#define GPIO_ALT_TIM3_4 0x2
+#define GPIO_ALT_TIM9_11 0x3
+#define GPIO_ALT_I2C 0x4
+#define GPIO_ALT_SPI 0x5
+#define GPIO_ALT_SPI3 0x6
+#define GPIO_ALT_USART 0x7
+#define GPIO_ALT_I2C_23 0x9
+#define GPIO_ALT_USB 0xA
+#define GPIO_ALT_LCD 0xB
+#define GPIO_ALT_RI 0xE
+#define GPIO_ALT_EVENTOUT 0xF
 
 /* --- I2C --- */
-#define STM32_I2C_CR1(n)              REG16(stm32_i2c_reg(n, 0x00))
-#define  STM32_I2C_CR1_PE              BIT(0)
-#define  STM32_I2C_CR1_START           BIT(8)
-#define  STM32_I2C_CR1_STOP            BIT(9)
-#define  STM32_I2C_CR1_ACK             BIT(10)
-#define  STM32_I2C_CR1_POS             BIT(11)
-#define  STM32_I2C_CR1_SWRST           BIT(15)
-#define STM32_I2C_CR2(n)              REG16(stm32_i2c_reg(n, 0x04))
-#define  STM32_I2C_CR2_ITERREN         BIT(8)
-#define  STM32_I2C_CR2_ITEVTEN         BIT(9)
-#define  STM32_I2C_CR2_ITBUFEN         BIT(10)
-#define  STM32_I2C_CR2_DMAEN           BIT(11)
-#define  STM32_I2C_CR2_LAST            BIT(12)
-#define STM32_I2C_OAR1(n)             REG16(stm32_i2c_reg(n, 0x08))
-#define  STM32_I2C_OAR1_B14            BIT(14)
-#define STM32_I2C_OAR2(n)             REG16(stm32_i2c_reg(n, 0x0C))
-#define  STM32_I2C_OAR2_ENDUAL         BIT(0)
-#define STM32_I2C_DR(n)               REG16(stm32_i2c_reg(n, 0x10))
-#define STM32_I2C_SR1(n)              REG16(stm32_i2c_reg(n, 0x14))
-#define  STM32_I2C_SR1_SB              BIT(0)
-#define  STM32_I2C_SR1_ADDR            BIT(1)
-#define  STM32_I2C_SR1_BTF             BIT(2)
-#define  STM32_I2C_SR1_STOPF           BIT(4)
-#define  STM32_I2C_SR1_RXNE            BIT(6)
-#define  STM32_I2C_SR1_TXE             BIT(7)
-#define  STM32_I2C_SR1_BERR            BIT(8)
-#define  STM32_I2C_SR1_ARLO            BIT(9)
-#define  STM32_I2C_SR1_AF              BIT(10)
-
-#define STM32_I2C_SR2(n)              REG16(stm32_i2c_reg(n, 0x18))
-#define  STM32_I2C_SR2_BUSY            BIT(1)
-#define  STM32_I2C_SR2_TRA             BIT(2)
-#define  STM32_I2C_SR2_DUALF           BIT(7)
-
-#define STM32_I2C_CCR(n)              REG16(stm32_i2c_reg(n, 0x1C))
-#define  STM32_I2C_CCR_DUTY            BIT(14)
-#define  STM32_I2C_CCR_FM              BIT(15)
-#define STM32_I2C_TRISE(n)            REG16(stm32_i2c_reg(n, 0x20))
-
+#define STM32_I2C_CR1(n) REG16(stm32_i2c_reg(n, 0x00))
+#define STM32_I2C_CR1_PE BIT(0)
+#define STM32_I2C_CR1_START BIT(8)
+#define STM32_I2C_CR1_STOP BIT(9)
+#define STM32_I2C_CR1_ACK BIT(10)
+#define STM32_I2C_CR1_POS BIT(11)
+#define STM32_I2C_CR1_SWRST BIT(15)
+#define STM32_I2C_CR2(n) REG16(stm32_i2c_reg(n, 0x04))
+#define STM32_I2C_CR2_ITERREN BIT(8)
+#define STM32_I2C_CR2_ITEVTEN BIT(9)
+#define STM32_I2C_CR2_ITBUFEN BIT(10)
+#define STM32_I2C_CR2_DMAEN BIT(11)
+#define STM32_I2C_CR2_LAST BIT(12)
+#define STM32_I2C_OAR1(n) REG16(stm32_i2c_reg(n, 0x08))
+#define STM32_I2C_OAR1_B14 BIT(14)
+#define STM32_I2C_OAR2(n) REG16(stm32_i2c_reg(n, 0x0C))
+#define STM32_I2C_OAR2_ENDUAL BIT(0)
+#define STM32_I2C_DR(n) REG16(stm32_i2c_reg(n, 0x10))
+#define STM32_I2C_SR1(n) REG16(stm32_i2c_reg(n, 0x14))
+#define STM32_I2C_SR1_SB BIT(0)
+#define STM32_I2C_SR1_ADDR BIT(1)
+#define STM32_I2C_SR1_BTF BIT(2)
+#define STM32_I2C_SR1_STOPF BIT(4)
+#define STM32_I2C_SR1_RXNE BIT(6)
+#define STM32_I2C_SR1_TXE BIT(7)
+#define STM32_I2C_SR1_BERR BIT(8)
+#define STM32_I2C_SR1_ARLO BIT(9)
+#define STM32_I2C_SR1_AF BIT(10)
+
+#define STM32_I2C_SR2(n) REG16(stm32_i2c_reg(n, 0x18))
+#define STM32_I2C_SR2_BUSY BIT(1)
+#define STM32_I2C_SR2_TRA BIT(2)
+#define STM32_I2C_SR2_DUALF BIT(7)
+
+#define STM32_I2C_CCR(n) REG16(stm32_i2c_reg(n, 0x1C))
+#define STM32_I2C_CCR_DUTY BIT(14)
+#define STM32_I2C_CCR_FM BIT(15)
+#define STM32_I2C_TRISE(n) REG16(stm32_i2c_reg(n, 0x20))
 
 /* --- Power / Reset / Clocks --- */
-#define STM32_PWR_CSR               REG32(STM32_PWR_BASE + 0x04)
-#define STM32_PWR_CR2               REG32(STM32_PWR_BASE + 0x08)
-#define STM32_PWR_CR3               REG32(STM32_PWR_BASE + 0x0C)
-#define  STM32_PWR_CR3_BYPASS        BIT(0)
-#define  STM32_PWR_CR3_LDOEN         BIT(1)
-#define  STM32_PWR_CR3_SCUEN         BIT(2)
-#define  STM32_PWR_CR3_VBE           BIT(8)
-#define  STM32_PWR_CR3_VBRS          BIT(9)
-#define  STM32_PWR_CR3_USB33DEN      BIT(24)
-#define  STM32_PWR_CR3_USBREGEN      BIT(25)
-#define  STM32_PWR_CR3_USB33RDY      BIT(26)
-#define STM32_PWR_CPUCR             REG32(STM32_PWR_BASE + 0x10)
-#define  STM32_PWR_CPUCR_PDDS_D1     BIT(0)
-#define  STM32_PWR_CPUCR_PDDS_D2     BIT(1)
-#define  STM32_PWR_CPUCR_PDDS_D3     BIT(2)
-#define  STM32_PWR_CPUCR_STOPF       BIT(5)
-#define  STM32_PWR_CPUCR_SBF         BIT(6)
-#define  STM32_PWR_CPUCR_SBF_D1      BIT(7)
-#define  STM32_PWR_CPUCR_SBF_D2      BIT(8)
-#define  STM32_PWR_CPUCR_CSSF        BIT(9)
-#define  STM32_PWR_CPUCR_RUN_D3      BIT(11)
-#define STM32_PWR_D3CR              REG32(STM32_PWR_BASE + 0x18)
-#define  STM32_PWR_D3CR_VOS1         (3 << 14)
-#define  STM32_PWR_D3CR_VOS2         (2 << 14)
-#define  STM32_PWR_D3CR_VOS3         (1 << 14)
-#define  STM32_PWR_D3CR_VOSMASK      (3 << 14)
-#define  STM32_PWR_D3CR_VOSRDY       (1 << 13)
-#define STM32_PWR_WKUPCR            REG32(STM32_PWR_BASE + 0x20)
-#define STM32_PWR_WKUPFR            REG32(STM32_PWR_BASE + 0x24)
-#define STM32_PWR_WKUPEPR           REG32(STM32_PWR_BASE + 0x28)
-
-
-#define STM32_RCC_CR                REG32(STM32_RCC_BASE + 0x000)
-#define STM32_RCC_ICSCR             REG32(STM32_RCC_BASE + 0x004)
-#define STM32_RCC_CRRCR             REG32(STM32_RCC_BASE + 0x008)
-#define STM32_RCC_CFGR              REG32(STM32_RCC_BASE + 0x010)
-#define STM32_RCC_D1CFGR            REG32(STM32_RCC_BASE + 0x018)
-#define STM32_RCC_D2CFGR            REG32(STM32_RCC_BASE + 0x01C)
-#define STM32_RCC_D3CFGR            REG32(STM32_RCC_BASE + 0x020)
-#define STM32_RCC_PLLCKSELR         REG32(STM32_RCC_BASE + 0x028)
-#define STM32_RCC_PLLCFGR           REG32(STM32_RCC_BASE + 0x02C)
-#define STM32_RCC_PLL1DIVR          REG32(STM32_RCC_BASE + 0x030)
-#define STM32_RCC_PLL1FRACR         REG32(STM32_RCC_BASE + 0x034)
-#define STM32_RCC_PLL2DIVR          REG32(STM32_RCC_BASE + 0x038)
-#define STM32_RCC_PLL2FRACR         REG32(STM32_RCC_BASE + 0x03C)
-#define STM32_RCC_PLL3DIVR          REG32(STM32_RCC_BASE + 0x040)
-#define STM32_RCC_PLL3FRACR         REG32(STM32_RCC_BASE + 0x044)
-#define STM32_RCC_D1CCIPR           REG32(STM32_RCC_BASE + 0x04C)
-#define STM32_RCC_D2CCIP1R          REG32(STM32_RCC_BASE + 0x050)
-#define STM32_RCC_D2CCIP2R          REG32(STM32_RCC_BASE + 0x054)
-#define STM32_RCC_D3CCIPR           REG32(STM32_RCC_BASE + 0x058)
-#define STM32_RCC_CIER              REG32(STM32_RCC_BASE + 0x060)
-#define STM32_RCC_CIFR              REG32(STM32_RCC_BASE + 0x064)
-#define STM32_RCC_CICR              REG32(STM32_RCC_BASE + 0x068)
-#define STM32_RCC_BDCR              REG32(STM32_RCC_BASE + 0x070)
-#define STM32_RCC_CSR               REG32(STM32_RCC_BASE + 0x074)
-
-#define STM32_RCC_APB2RSTR          REG32(STM32_RCC_BASE + 0x098)
-
-#define STM32_RCC_RSR               REG32(STM32_RCC_BASE + 0x0D0)
-#define STM32_RCC_AHB3ENR           REG32(STM32_RCC_BASE + 0x0D4)
-#define STM32_RCC_AHB1ENR           REG32(STM32_RCC_BASE + 0x0D8)
-#define STM32_RCC_AHB2ENR           REG32(STM32_RCC_BASE + 0x0DC)
-#define STM32_RCC_AHB2ENR_RNGEN     BIT(6)
-#define STM32_RCC_AHB2ENR_HASHEN    BIT(5)
-#define STM32_RCC_AHB2ENR_CRYPTEN   BIT(4)
-#define STM32_RCC_AHB4ENR           REG32(STM32_RCC_BASE + 0x0E0)
-#define STM32_RCC_AHB4ENR_GPIOMASK  0x3ff
-#define STM32_RCC_APB3ENR           REG32(STM32_RCC_BASE + 0x0E4)
-#define STM32_RCC_APB1LENR          REG32(STM32_RCC_BASE + 0x0E8)
-#define STM32_RCC_APB1HENR          REG32(STM32_RCC_BASE + 0x0EC)
-#define STM32_RCC_APB2ENR           REG32(STM32_RCC_BASE + 0x0F0)
-#define STM32_RCC_APB4ENR           REG32(STM32_RCC_BASE + 0x0F4)
-#define STM32_RCC_SYSCFGEN          BIT(1)
-#define STM32_RCC_AHB3LPENR         REG32(STM32_RCC_BASE + 0x0FC)
-#define STM32_RCC_AHB1LPENR         REG32(STM32_RCC_BASE + 0x100)
-#define STM32_RCC_AHB2LPENR         REG32(STM32_RCC_BASE + 0x104)
-#define STM32_RCC_AHB4LPENR         REG32(STM32_RCC_BASE + 0x108)
-#define STM32_RCC_APB3LPENR         REG32(STM32_RCC_BASE + 0x10C)
-#define STM32_RCC_APB1LLPENR        REG32(STM32_RCC_BASE + 0x110)
-#define STM32_RCC_APB1HLPENR        REG32(STM32_RCC_BASE + 0x114)
-#define STM32_RCC_APB2LPENR         REG32(STM32_RCC_BASE + 0x118)
-#define STM32_RCC_APB4LPENR         REG32(STM32_RCC_BASE + 0x11C)
+#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04)
+#define STM32_PWR_CR2 REG32(STM32_PWR_BASE + 0x08)
+#define STM32_PWR_CR3 REG32(STM32_PWR_BASE + 0x0C)
+#define STM32_PWR_CR3_BYPASS BIT(0)
+#define STM32_PWR_CR3_LDOEN BIT(1)
+#define STM32_PWR_CR3_SCUEN BIT(2)
+#define STM32_PWR_CR3_VBE BIT(8)
+#define STM32_PWR_CR3_VBRS BIT(9)
+#define STM32_PWR_CR3_USB33DEN BIT(24)
+#define STM32_PWR_CR3_USBREGEN BIT(25)
+#define STM32_PWR_CR3_USB33RDY BIT(26)
+#define STM32_PWR_CPUCR REG32(STM32_PWR_BASE + 0x10)
+#define STM32_PWR_CPUCR_PDDS_D1 BIT(0)
+#define STM32_PWR_CPUCR_PDDS_D2 BIT(1)
+#define STM32_PWR_CPUCR_PDDS_D3 BIT(2)
+#define STM32_PWR_CPUCR_STOPF BIT(5)
+#define STM32_PWR_CPUCR_SBF BIT(6)
+#define STM32_PWR_CPUCR_SBF_D1 BIT(7)
+#define STM32_PWR_CPUCR_SBF_D2 BIT(8)
+#define STM32_PWR_CPUCR_CSSF BIT(9)
+#define STM32_PWR_CPUCR_RUN_D3 BIT(11)
+#define STM32_PWR_D3CR REG32(STM32_PWR_BASE + 0x18)
+#define STM32_PWR_D3CR_VOS1 (3 << 14)
+#define STM32_PWR_D3CR_VOS2 (2 << 14)
+#define STM32_PWR_D3CR_VOS3 (1 << 14)
+#define STM32_PWR_D3CR_VOSMASK (3 << 14)
+#define STM32_PWR_D3CR_VOSRDY (1 << 13)
+#define STM32_PWR_WKUPCR REG32(STM32_PWR_BASE + 0x20)
+#define STM32_PWR_WKUPFR REG32(STM32_PWR_BASE + 0x24)
+#define STM32_PWR_WKUPEPR REG32(STM32_PWR_BASE + 0x28)
+
+#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x000)
+#define STM32_RCC_ICSCR REG32(STM32_RCC_BASE + 0x004)
+#define STM32_RCC_CRRCR REG32(STM32_RCC_BASE + 0x008)
+#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x010)
+#define STM32_RCC_D1CFGR REG32(STM32_RCC_BASE + 0x018)
+#define STM32_RCC_D2CFGR REG32(STM32_RCC_BASE + 0x01C)
+#define STM32_RCC_D3CFGR REG32(STM32_RCC_BASE + 0x020)
+#define STM32_RCC_PLLCKSELR REG32(STM32_RCC_BASE + 0x028)
+#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x02C)
+#define STM32_RCC_PLL1DIVR REG32(STM32_RCC_BASE + 0x030)
+#define STM32_RCC_PLL1FRACR REG32(STM32_RCC_BASE + 0x034)
+#define STM32_RCC_PLL2DIVR REG32(STM32_RCC_BASE + 0x038)
+#define STM32_RCC_PLL2FRACR REG32(STM32_RCC_BASE + 0x03C)
+#define STM32_RCC_PLL3DIVR REG32(STM32_RCC_BASE + 0x040)
+#define STM32_RCC_PLL3FRACR REG32(STM32_RCC_BASE + 0x044)
+#define STM32_RCC_D1CCIPR REG32(STM32_RCC_BASE + 0x04C)
+#define STM32_RCC_D2CCIP1R REG32(STM32_RCC_BASE + 0x050)
+#define STM32_RCC_D2CCIP2R REG32(STM32_RCC_BASE + 0x054)
+#define STM32_RCC_D3CCIPR REG32(STM32_RCC_BASE + 0x058)
+#define STM32_RCC_CIER REG32(STM32_RCC_BASE + 0x060)
+#define STM32_RCC_CIFR REG32(STM32_RCC_BASE + 0x064)
+#define STM32_RCC_CICR REG32(STM32_RCC_BASE + 0x068)
+#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x070)
+#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x074)
+
+#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x098)
+
+#define STM32_RCC_RSR REG32(STM32_RCC_BASE + 0x0D0)
+#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x0D4)
+#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x0D8)
+#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x0DC)
+#define STM32_RCC_AHB2ENR_RNGEN BIT(6)
+#define STM32_RCC_AHB2ENR_HASHEN BIT(5)
+#define STM32_RCC_AHB2ENR_CRYPTEN BIT(4)
+#define STM32_RCC_AHB4ENR REG32(STM32_RCC_BASE + 0x0E0)
+#define STM32_RCC_AHB4ENR_GPIOMASK 0x3ff
+#define STM32_RCC_APB3ENR REG32(STM32_RCC_BASE + 0x0E4)
+#define STM32_RCC_APB1LENR REG32(STM32_RCC_BASE + 0x0E8)
+#define STM32_RCC_APB1HENR REG32(STM32_RCC_BASE + 0x0EC)
+#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x0F0)
+#define STM32_RCC_APB4ENR REG32(STM32_RCC_BASE + 0x0F4)
+#define STM32_RCC_SYSCFGEN BIT(1)
+#define STM32_RCC_AHB3LPENR REG32(STM32_RCC_BASE + 0x0FC)
+#define STM32_RCC_AHB1LPENR REG32(STM32_RCC_BASE + 0x100)
+#define STM32_RCC_AHB2LPENR REG32(STM32_RCC_BASE + 0x104)
+#define STM32_RCC_AHB4LPENR REG32(STM32_RCC_BASE + 0x108)
+#define STM32_RCC_APB3LPENR REG32(STM32_RCC_BASE + 0x10C)
+#define STM32_RCC_APB1LLPENR REG32(STM32_RCC_BASE + 0x110)
+#define STM32_RCC_APB1HLPENR REG32(STM32_RCC_BASE + 0x114)
+#define STM32_RCC_APB2LPENR REG32(STM32_RCC_BASE + 0x118)
+#define STM32_RCC_APB4LPENR REG32(STM32_RCC_BASE + 0x11C)
 /* Aliases */
-#define STM32_RCC_APB1ENR           STM32_RCC_APB1LENR
-
-#define STM32_RCC_CR_HSION                     BIT(0)
-#define STM32_RCC_CR_HSIRDY                    BIT(2)
-#define STM32_RCC_CR_CSION                     BIT(7)
-#define STM32_RCC_CR_CSIRDY                    BIT(8)
-#define STM32_RCC_CR_HSI48ON                   BIT(12)
-#define STM32_RCC_CR_HSI48RDY                  BIT(13)
-#define STM32_RCC_CR_PLL1ON                    BIT(24)
-#define STM32_RCC_CR_PLL1RDY                   BIT(25)
-#define STM32_RCC_CR_PLL2ON                    BIT(26)
-#define STM32_RCC_CR_PLL2RDY                   BIT(27)
-#define STM32_RCC_CR_PLL3ON                    BIT(28)
-#define STM32_RCC_CR_PLL3RDY                   BIT(29)
-#define STM32_RCC_CFGR_SW_HSI                  (0 << 0)
-#define STM32_RCC_CFGR_SW_CSI                  (1 << 0)
-#define STM32_RCC_CFGR_SW_HSE                  (2 << 0)
-#define STM32_RCC_CFGR_SW_PLL1                 (3 << 0)
-#define STM32_RCC_CFGR_SW_MASK                 (3 << 0)
-#define STM32_RCC_CFGR_SWS_HSI                 (0 << 3)
-#define STM32_RCC_CFGR_SWS_CSI                 (1 << 3)
-#define STM32_RCC_CFGR_SWS_HSE                 (2 << 3)
-#define STM32_RCC_CFGR_SWS_PLL1                (3 << 3)
-#define STM32_RCC_CFGR_SWS_MASK                (3 << 3)
-#define STM32_RCC_D1CFGR_HPRE_DIV1             (0 << 0)
-#define STM32_RCC_D1CFGR_HPRE_DIV2             (8 << 0)
-#define STM32_RCC_D1CFGR_HPRE_DIV4             (9 << 0)
-#define STM32_RCC_D1CFGR_HPRE_DIV8            (10 << 0)
-#define STM32_RCC_D1CFGR_HPRE_DIV16           (11 << 0)
-#define STM32_RCC_D1CFGR_D1PPRE_DIV1           (0 << 4)
-#define STM32_RCC_D1CFGR_D1PPRE_DIV2           (4 << 4)
-#define STM32_RCC_D1CFGR_D1PPRE_DIV4           (5 << 4)
-#define STM32_RCC_D1CFGR_D1PPRE_DIV8           (6 << 4)
-#define STM32_RCC_D1CFGR_D1PPRE_DIV16          (7 << 4)
-#define STM32_RCC_D1CFGR_D1CPRE_DIV1           (0 << 8)
-#define STM32_RCC_D1CFGR_D1CPRE_DIV2           (8 << 8)
-#define STM32_RCC_D1CFGR_D1CPRE_DIV4           (9 << 8)
-#define STM32_RCC_D1CFGR_D1CPRE_DIV8          (10 << 8)
-#define STM32_RCC_D1CFGR_D1CPRE_DIV16         (1BIT(8))
-#define STM32_RCC_PLLCKSEL_PLLSRC_HSI          (0 << 0)
-#define STM32_RCC_PLLCKSEL_PLLSRC_CSI          (1 << 0)
-#define STM32_RCC_PLLCKSEL_PLLSRC_HSE          (2 << 0)
-#define STM32_RCC_PLLCKSEL_PLLSRC_NONE         (3 << 0)
-#define STM32_RCC_PLLCKSEL_PLLSRC_MASK         (3 << 0)
-#define STM32_RCC_PLLCKSEL_DIVM1(m)            ((m) << 4)
-#define STM32_RCC_PLLCKSEL_DIVM2(m)            ((m) << 12)
-#define STM32_RCC_PLLCKSEL_DIVM3(m)            ((m) << 20)
-#define STM32_RCC_PLLCFG_PLL1VCOSEL_FRACEN     BIT(0)
-#define STM32_RCC_PLLCFG_PLL1VCOSEL_WIDE       (0 << 1)
-#define STM32_RCC_PLLCFG_PLL1VCOSEL_MEDIUM     BIT(1)
-#define STM32_RCC_PLLCFG_PLL1RGE_1M_2M         (0 << 2)
-#define STM32_RCC_PLLCFG_PLL1RGE_2M_4M         (1 << 2)
-#define STM32_RCC_PLLCFG_PLL1RGE_4M_8M         (2 << 2)
-#define STM32_RCC_PLLCFG_PLL1RGE_8M_16M        (3 << 2)
-#define STM32_RCC_PLLCFG_DIVP1EN               BIT(16)
-#define STM32_RCC_PLLCFG_DIVQ1EN               BIT(17)
-#define STM32_RCC_PLLCFG_DIVR1EN               BIT(18)
-#define STM32_RCC_PLLDIV_DIVN(n)               (((n) - 1) << 0)
-#define STM32_RCC_PLLDIV_DIVP(p)               (((p) - 1) << 9)
-#define STM32_RCC_PLLDIV_DIVQ(q)               (((q) - 1) << 16)
-#define STM32_RCC_PLLDIV_DIVR(r)               (((r) - 1) << 24)
-#define STM32_RCC_PLLFRAC(n)                   ((n) << 3)
-#define STM32_RCC_D2CCIP1R_SPI123SEL_PLL1Q     (0 << 12)
-#define STM32_RCC_D2CCIP1R_SPI123SEL_PLL2P     (1 << 12)
-#define STM32_RCC_D2CCIP1R_SPI123SEL_PLL3P     (2 << 12)
-#define STM32_RCC_D2CCIP1R_SPI123SEL_I2SCKIN   (3 << 12)
-#define STM32_RCC_D2CCIP1R_SPI123SEL_PERCK     (4 << 12)
-#define STM32_RCC_D2CCIP1R_SPI123SEL_MASK      (7 << 12)
-#define STM32_RCC_D2CCIP1R_SPI45SEL_APB        (0 << 16)
-#define STM32_RCC_D2CCIP1R_SPI45SEL_PLL2Q      (1 << 16)
-#define STM32_RCC_D2CCIP1R_SPI45SEL_PLL3Q      (2 << 16)
-#define STM32_RCC_D2CCIP1R_SPI45SEL_HSI        (3 << 16)
-#define STM32_RCC_D2CCIP1R_SPI45SEL_CSI        (4 << 16)
-#define STM32_RCC_D2CCIP1R_SPI45SEL_HSE        (5 << 16)
-#define STM32_RCC_D2CCIP1R_SPI45SEL_MASK       (7 << 16)
-#define STM32_RCC_D2CCIP2_USART234578SEL_PCLK  (0 << 0)
+#define STM32_RCC_APB1ENR STM32_RCC_APB1LENR
+
+#define STM32_RCC_CR_HSION BIT(0)
+#define STM32_RCC_CR_HSIRDY BIT(2)
+#define STM32_RCC_CR_CSION BIT(7)
+#define STM32_RCC_CR_CSIRDY BIT(8)
+#define STM32_RCC_CR_HSI48ON BIT(12)
+#define STM32_RCC_CR_HSI48RDY BIT(13)
+#define STM32_RCC_CR_PLL1ON BIT(24)
+#define STM32_RCC_CR_PLL1RDY BIT(25)
+#define STM32_RCC_CR_PLL2ON BIT(26)
+#define STM32_RCC_CR_PLL2RDY BIT(27)
+#define STM32_RCC_CR_PLL3ON BIT(28)
+#define STM32_RCC_CR_PLL3RDY BIT(29)
+#define STM32_RCC_CFGR_SW_HSI (0 << 0)
+#define STM32_RCC_CFGR_SW_CSI (1 << 0)
+#define STM32_RCC_CFGR_SW_HSE (2 << 0)
+#define STM32_RCC_CFGR_SW_PLL1 (3 << 0)
+#define STM32_RCC_CFGR_SW_MASK (3 << 0)
+#define STM32_RCC_CFGR_SWS_HSI (0 << 3)
+#define STM32_RCC_CFGR_SWS_CSI (1 << 3)
+#define STM32_RCC_CFGR_SWS_HSE (2 << 3)
+#define STM32_RCC_CFGR_SWS_PLL1 (3 << 3)
+#define STM32_RCC_CFGR_SWS_MASK (3 << 3)
+#define STM32_RCC_D1CFGR_HPRE_DIV1 (0 << 0)
+#define STM32_RCC_D1CFGR_HPRE_DIV2 (8 << 0)
+#define STM32_RCC_D1CFGR_HPRE_DIV4 (9 << 0)
+#define STM32_RCC_D1CFGR_HPRE_DIV8 (10 << 0)
+#define STM32_RCC_D1CFGR_HPRE_DIV16 (11 << 0)
+#define STM32_RCC_D1CFGR_D1PPRE_DIV1 (0 << 4)
+#define STM32_RCC_D1CFGR_D1PPRE_DIV2 (4 << 4)
+#define STM32_RCC_D1CFGR_D1PPRE_DIV4 (5 << 4)
+#define STM32_RCC_D1CFGR_D1PPRE_DIV8 (6 << 4)
+#define STM32_RCC_D1CFGR_D1PPRE_DIV16 (7 << 4)
+#define STM32_RCC_D1CFGR_D1CPRE_DIV1 (0 << 8)
+#define STM32_RCC_D1CFGR_D1CPRE_DIV2 (8 << 8)
+#define STM32_RCC_D1CFGR_D1CPRE_DIV4 (9 << 8)
+#define STM32_RCC_D1CFGR_D1CPRE_DIV8 (10 << 8)
+#define STM32_RCC_D1CFGR_D1CPRE_DIV16 (1BIT(8))
+#define STM32_RCC_PLLCKSEL_PLLSRC_HSI (0 << 0)
+#define STM32_RCC_PLLCKSEL_PLLSRC_CSI (1 << 0)
+#define STM32_RCC_PLLCKSEL_PLLSRC_HSE (2 << 0)
+#define STM32_RCC_PLLCKSEL_PLLSRC_NONE (3 << 0)
+#define STM32_RCC_PLLCKSEL_PLLSRC_MASK (3 << 0)
+#define STM32_RCC_PLLCKSEL_DIVM1(m) ((m) << 4)
+#define STM32_RCC_PLLCKSEL_DIVM2(m) ((m) << 12)
+#define STM32_RCC_PLLCKSEL_DIVM3(m) ((m) << 20)
+#define STM32_RCC_PLLCFG_PLL1VCOSEL_FRACEN BIT(0)
+#define STM32_RCC_PLLCFG_PLL1VCOSEL_WIDE (0 << 1)
+#define STM32_RCC_PLLCFG_PLL1VCOSEL_MEDIUM BIT(1)
+#define STM32_RCC_PLLCFG_PLL1RGE_1M_2M (0 << 2)
+#define STM32_RCC_PLLCFG_PLL1RGE_2M_4M (1 << 2)
+#define STM32_RCC_PLLCFG_PLL1RGE_4M_8M (2 << 2)
+#define STM32_RCC_PLLCFG_PLL1RGE_8M_16M (3 << 2)
+#define STM32_RCC_PLLCFG_DIVP1EN BIT(16)
+#define STM32_RCC_PLLCFG_DIVQ1EN BIT(17)
+#define STM32_RCC_PLLCFG_DIVR1EN BIT(18)
+#define STM32_RCC_PLLDIV_DIVN(n) (((n)-1) << 0)
+#define STM32_RCC_PLLDIV_DIVP(p) (((p)-1) << 9)
+#define STM32_RCC_PLLDIV_DIVQ(q) (((q)-1) << 16)
+#define STM32_RCC_PLLDIV_DIVR(r) (((r)-1) << 24)
+#define STM32_RCC_PLLFRAC(n) ((n) << 3)
+#define STM32_RCC_D2CCIP1R_SPI123SEL_PLL1Q (0 << 12)
+#define STM32_RCC_D2CCIP1R_SPI123SEL_PLL2P (1 << 12)
+#define STM32_RCC_D2CCIP1R_SPI123SEL_PLL3P (2 << 12)
+#define STM32_RCC_D2CCIP1R_SPI123SEL_I2SCKIN (3 << 12)
+#define STM32_RCC_D2CCIP1R_SPI123SEL_PERCK (4 << 12)
+#define STM32_RCC_D2CCIP1R_SPI123SEL_MASK (7 << 12)
+#define STM32_RCC_D2CCIP1R_SPI45SEL_APB (0 << 16)
+#define STM32_RCC_D2CCIP1R_SPI45SEL_PLL2Q (1 << 16)
+#define STM32_RCC_D2CCIP1R_SPI45SEL_PLL3Q (2 << 16)
+#define STM32_RCC_D2CCIP1R_SPI45SEL_HSI (3 << 16)
+#define STM32_RCC_D2CCIP1R_SPI45SEL_CSI (4 << 16)
+#define STM32_RCC_D2CCIP1R_SPI45SEL_HSE (5 << 16)
+#define STM32_RCC_D2CCIP1R_SPI45SEL_MASK (7 << 16)
+#define STM32_RCC_D2CCIP2_USART234578SEL_PCLK (0 << 0)
 #define STM32_RCC_D2CCIP2_USART234578SEL_PLL2Q (1 << 0)
 #define STM32_RCC_D2CCIP2_USART234578SEL_PLL3Q (2 << 0)
-#define STM32_RCC_D2CCIP2_USART234578SEL_HSI   (3 << 0)
-#define STM32_RCC_D2CCIP2_USART234578SEL_CSI   (4 << 0)
-#define STM32_RCC_D2CCIP2_USART234578SEL_LSE   (5 << 0)
-#define STM32_RCC_D2CCIP2_USART234578SEL_MASK  (7 << 0)
-#define STM32_RCC_D2CCIP2_USART16SEL_PCLK      (0 << 3)
-#define STM32_RCC_D2CCIP2_USART16SEL_PLL2Q     (1 << 3)
-#define STM32_RCC_D2CCIP2_USART16SEL_PLL3Q     (2 << 3)
-#define STM32_RCC_D2CCIP2_USART16SEL_HSI       (3 << 3)
-#define STM32_RCC_D2CCIP2_USART16SEL_CSI       (4 << 3)
-#define STM32_RCC_D2CCIP2_USART16SEL_LSE       (5 << 3)
-#define STM32_RCC_D2CCIP2_USART16SEL_MASK      (7 << 3)
-#define STM32_RCC_D2CCIP2_RNGSEL_HSI48         (0 << 8)
-#define STM32_RCC_D2CCIP2_RNGSEL_PLL1Q         (1 << 8)
-#define STM32_RCC_D2CCIP2_RNGSEL_LSE           (2 << 8)
-#define STM32_RCC_D2CCIP2_RNGSEL_LSI           (3 << 8)
-#define STM32_RCC_D2CCIP2_RNGSEL_MASK          (3 << 8)
-#define STM32_RCC_D2CCIP2_LPTIM1SEL_PCLK       (0 << 28)
-#define STM32_RCC_D2CCIP2_LPTIM1SEL_PLL2       (1 << 28)
-#define STM32_RCC_D2CCIP2_LPTIM1SEL_PLL3       (2 << 28)
-#define STM32_RCC_D2CCIP2_LPTIM1SEL_LSE        (3 << 28)
-#define STM32_RCC_D2CCIP2_LPTIM1SEL_LSI        (4 << 28)
-#define STM32_RCC_D2CCIP2_LPTIM1SEL_PER        (5 << 28)
-#define STM32_RCC_D2CCIP2_LPTIM1SEL_MASK       (7 << 28)
-#define STM32_RCC_CSR_LSION                    BIT(0)
-#define STM32_RCC_CSR_LSIRDY                   BIT(1)
-
-#define STM32_SYSCFG_PMCR           REG32(STM32_SYSCFG_BASE + 0x04)
-#define STM32_SYSCFG_EXTICR(n)      REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
+#define STM32_RCC_D2CCIP2_USART234578SEL_HSI (3 << 0)
+#define STM32_RCC_D2CCIP2_USART234578SEL_CSI (4 << 0)
+#define STM32_RCC_D2CCIP2_USART234578SEL_LSE (5 << 0)
+#define STM32_RCC_D2CCIP2_USART234578SEL_MASK (7 << 0)
+#define STM32_RCC_D2CCIP2_USART16SEL_PCLK (0 << 3)
+#define STM32_RCC_D2CCIP2_USART16SEL_PLL2Q (1 << 3)
+#define STM32_RCC_D2CCIP2_USART16SEL_PLL3Q (2 << 3)
+#define STM32_RCC_D2CCIP2_USART16SEL_HSI (3 << 3)
+#define STM32_RCC_D2CCIP2_USART16SEL_CSI (4 << 3)
+#define STM32_RCC_D2CCIP2_USART16SEL_LSE (5 << 3)
+#define STM32_RCC_D2CCIP2_USART16SEL_MASK (7 << 3)
+#define STM32_RCC_D2CCIP2_RNGSEL_HSI48 (0 << 8)
+#define STM32_RCC_D2CCIP2_RNGSEL_PLL1Q (1 << 8)
+#define STM32_RCC_D2CCIP2_RNGSEL_LSE (2 << 8)
+#define STM32_RCC_D2CCIP2_RNGSEL_LSI (3 << 8)
+#define STM32_RCC_D2CCIP2_RNGSEL_MASK (3 << 8)
+#define STM32_RCC_D2CCIP2_LPTIM1SEL_PCLK (0 << 28)
+#define STM32_RCC_D2CCIP2_LPTIM1SEL_PLL2 (1 << 28)
+#define STM32_RCC_D2CCIP2_LPTIM1SEL_PLL3 (2 << 28)
+#define STM32_RCC_D2CCIP2_LPTIM1SEL_LSE (3 << 28)
+#define STM32_RCC_D2CCIP2_LPTIM1SEL_LSI (4 << 28)
+#define STM32_RCC_D2CCIP2_LPTIM1SEL_PER (5 << 28)
+#define STM32_RCC_D2CCIP2_LPTIM1SEL_MASK (7 << 28)
+#define STM32_RCC_CSR_LSION BIT(0)
+#define STM32_RCC_CSR_LSIRDY BIT(1)
+
+#define STM32_SYSCFG_PMCR REG32(STM32_SYSCFG_BASE + 0x04)
+#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
 
 /* Peripheral bits for APB1ENR regs */
-#define STM32_RCC_PB1_LPTIM1            BIT(9)
+#define STM32_RCC_PB1_LPTIM1 BIT(9)
 
 /* Peripheral bits for APB2ENR regs */
-#define STM32_RCC_PB2_TIM1              BIT(0)
-#define STM32_RCC_PB2_TIM2              BIT(1)
-#define STM32_RCC_PB2_USART1            BIT(4)
-#define STM32_RCC_PB2_SPI1              BIT(12)
-#define STM32_RCC_PB2_SPI4              BIT(13)
-#define STM32_RCC_PB2_TIM15             BIT(16)
-#define STM32_RCC_PB2_TIM16             BIT(17)
-#define STM32_RCC_PB2_TIM17             BIT(18)
+#define STM32_RCC_PB2_TIM1 BIT(0)
+#define STM32_RCC_PB2_TIM2 BIT(1)
+#define STM32_RCC_PB2_USART1 BIT(4)
+#define STM32_RCC_PB2_SPI1 BIT(12)
+#define STM32_RCC_PB2_SPI4 BIT(13)
+#define STM32_RCC_PB2_TIM15 BIT(16)
+#define STM32_RCC_PB2_TIM16 BIT(17)
+#define STM32_RCC_PB2_TIM17 BIT(18)
 
 /* Peripheral bits for AHB1/2/3/4ENR regs */
-#define STM32_RCC_HB1_DMA1              BIT(0)
-#define STM32_RCC_HB1_DMA2              BIT(1)
-#define STM32_RCC_HB3_MDMA              BIT(0)
-#define STM32_RCC_HB4_BDMA              BIT(21)
-
+#define STM32_RCC_HB1_DMA1 BIT(0)
+#define STM32_RCC_HB1_DMA2 BIT(1)
+#define STM32_RCC_HB3_MDMA BIT(0)
+#define STM32_RCC_HB4_BDMA BIT(21)
 
 /* Peripheral bits for RCC_APB/AHB and DBGMCU regs */
-#define STM32_RCC_PB2_USART1           BIT(4)
+#define STM32_RCC_PB2_USART1 BIT(4)
 
 /* Reset causes definitions */
 #define STM32_RCC_RESET_CAUSE STM32_RCC_RSR
-#define  RESET_CAUSE_WDG                (BIT(28)|BIT(26))
-#define  RESET_CAUSE_SFT                BIT(24)
-#define  RESET_CAUSE_POR                BIT(23)
-#define  RESET_CAUSE_PIN                BIT(22)
-#define  RESET_CAUSE_OTHER              (BIT(31)|BIT(30)|BIT(29)|BIT(28)| \
-					 BIT(27)|BIT(26)|BIT(25)|BIT(24)| \
-					 BIT(23)|BIT(22)|BIT(21)|BIT(20)| \
-					 BIT(19)|BIT(18)|BIT(17))
-#define  RESET_CAUSE_RMVF               BIT(16)
+#define RESET_CAUSE_WDG (BIT(28) | BIT(26))
+#define RESET_CAUSE_SFT BIT(24)
+#define RESET_CAUSE_POR BIT(23)
+#define RESET_CAUSE_PIN BIT(22)
+#define RESET_CAUSE_OTHER                                                      \
+	(BIT(31) | BIT(30) | BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25) | \
+	 BIT(24) | BIT(23) | BIT(22) | BIT(21) | BIT(20) | BIT(19) | BIT(18) | \
+	 BIT(17))
+#define RESET_CAUSE_RMVF BIT(16)
 
 /* Power cause in PWR CPUCR register (Standby&Stop modes) */
 #define STM32_PWR_RESET_CAUSE STM32_PWR_CPUCR
 #define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CPUCR
-#define  RESET_CAUSE_SBF                BIT(6)
-#define  RESET_CAUSE_SBF_CLR            BIT(9)
+#define RESET_CAUSE_SBF BIT(6)
+#define RESET_CAUSE_SBF_CLR BIT(9)
 
 /* --- Watchdogs --- */
 
 /* --- Real-Time Clock --- */
-#define STM32_RTC_TR                REG32(STM32_RTC_BASE + 0x00)
-#define STM32_RTC_DR                REG32(STM32_RTC_BASE + 0x04)
-#define STM32_RTC_CR                REG32(STM32_RTC_BASE + 0x08)
-#define  STM32_RTC_CR_BYPSHAD        BIT(5)
-#define  STM32_RTC_CR_ALRAE          BIT(8)
-#define  STM32_RTC_CR_ALRAIE         BIT(12)
-#define STM32_RTC_ISR               REG32(STM32_RTC_BASE + 0x0C)
-#define  STM32_RTC_ISR_ALRAWF        BIT(0)
-#define  STM32_RTC_ISR_RSF           BIT(5)
-#define  STM32_RTC_ISR_INITF         BIT(6)
-#define  STM32_RTC_ISR_INIT          BIT(7)
-#define  STM32_RTC_ISR_ALRAF         BIT(8)
-#define STM32_RTC_PRER              REG32(STM32_RTC_BASE + 0x10)
-#define  STM32_RTC_PRER_A_MASK       (0x7f << 16)
-#define  STM32_RTC_PRER_S_MASK       (0x7fff << 0)
-#define STM32_RTC_WUTR              REG32(STM32_RTC_BASE + 0x14)
-#define STM32_RTC_CALIBR            REG32(STM32_RTC_BASE + 0x18)
-#define STM32_RTC_ALRMAR            REG32(STM32_RTC_BASE + 0x1C)
-#define STM32_RTC_ALRMBR            REG32(STM32_RTC_BASE + 0x20)
-#define STM32_RTC_WPR               REG32(STM32_RTC_BASE + 0x24)
-#define STM32_RTC_SSR               REG32(STM32_RTC_BASE + 0x28)
-#define STM32_RTC_TSTR              REG32(STM32_RTC_BASE + 0x30)
-#define STM32_RTC_TSDR              REG32(STM32_RTC_BASE + 0x34)
-#define STM32_RTC_TAFCR             REG32(STM32_RTC_BASE + 0x40)
-#define STM32_RTC_ALRMASSR          REG32(STM32_RTC_BASE + 0x44)
-#define STM32_RTC_BACKUP(n)         REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
-
-#define STM32_BKP_DATA(n)           STM32_RTC_BACKUP(n)
-#define STM32_BKP_BYTES             128
+#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00)
+#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04)
+#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08)
+#define STM32_RTC_CR_BYPSHAD BIT(5)
+#define STM32_RTC_CR_ALRAE BIT(8)
+#define STM32_RTC_CR_ALRAIE BIT(12)
+#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C)
+#define STM32_RTC_ISR_ALRAWF BIT(0)
+#define STM32_RTC_ISR_RSF BIT(5)
+#define STM32_RTC_ISR_INITF BIT(6)
+#define STM32_RTC_ISR_INIT BIT(7)
+#define STM32_RTC_ISR_ALRAF BIT(8)
+#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10)
+#define STM32_RTC_PRER_A_MASK (0x7f << 16)
+#define STM32_RTC_PRER_S_MASK (0x7fff << 0)
+#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14)
+#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18)
+#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C)
+#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20)
+#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24)
+#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28)
+#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30)
+#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34)
+#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40)
+#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44)
+#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
+
+#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n)
+#define STM32_BKP_BYTES 128
 
 /* --- SPI --- */
 
@@ -634,163 +629,160 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
 #define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE)
 #define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE)
 
-#define STM32_SPI_CR1_SPE                      BIT(0)
-#define STM32_SPI_CR1_CSTART                   BIT(9)
-#define STM32_SPI_CR1_SSI                      BIT(12)
-#define STM32_SPI_CR1_DIV(div)                 ((div) << 28)
-#define STM32_SPI_CFG1_DATASIZE(n)             (((n) - 1) << 0)
-#define STM32_SPI_CFG1_FTHLV(n)                (((n) - 1) << 5)
-#define STM32_SPI_CFG1_UDRCFG_CONST            (0 << 9)
-#define STM32_SPI_CFG1_UDRCFG_LAST_RX          (1 << 9)
-#define STM32_SPI_CFG1_UDRCFG_LAST_TX          (2 << 9)
-#define STM32_SPI_CFG1_UDRDET_BEGIN_FRM        (0 << 11)
-#define STM32_SPI_CFG1_UDRDET_END_FRM          (1 << 11)
-#define STM32_SPI_CFG1_UDRDET_BEGIN_SS         (2 << 11)
-#define STM32_SPI_CFG1_RXDMAEN                 BIT(14)
-#define STM32_SPI_CFG1_TXDMAEN                 BIT(15)
-#define STM32_SPI_CFG1_CRCSIZE(n)              (((n) - 1) << 16)
-#define  STM32_SPI_CFG2_MSTR                   BIT(22)
-#define  STM32_SPI_CFG2_SSM                    BIT(26)
-#define  STM32_SPI_CFG2_AFCNTR                 BIT(31)
-
-#define STM32_SPI_SR_RXNE                      BIT(0)
-#define STM32_SPI_SR_UDR                       BIT(5)
-#define STM32_SPI_SR_FRLVL                     (3 << 13)
-#define STM32_SPI_SR_TXC                       BIT(12)
+#define STM32_SPI_CR1_SPE BIT(0)
+#define STM32_SPI_CR1_CSTART BIT(9)
+#define STM32_SPI_CR1_SSI BIT(12)
+#define STM32_SPI_CR1_DIV(div) ((div) << 28)
+#define STM32_SPI_CFG1_DATASIZE(n) (((n)-1) << 0)
+#define STM32_SPI_CFG1_FTHLV(n) (((n)-1) << 5)
+#define STM32_SPI_CFG1_UDRCFG_CONST (0 << 9)
+#define STM32_SPI_CFG1_UDRCFG_LAST_RX (1 << 9)
+#define STM32_SPI_CFG1_UDRCFG_LAST_TX (2 << 9)
+#define STM32_SPI_CFG1_UDRDET_BEGIN_FRM (0 << 11)
+#define STM32_SPI_CFG1_UDRDET_END_FRM (1 << 11)
+#define STM32_SPI_CFG1_UDRDET_BEGIN_SS (2 << 11)
+#define STM32_SPI_CFG1_RXDMAEN BIT(14)
+#define STM32_SPI_CFG1_TXDMAEN BIT(15)
+#define STM32_SPI_CFG1_CRCSIZE(n) (((n)-1) << 16)
+#define STM32_SPI_CFG2_MSTR BIT(22)
+#define STM32_SPI_CFG2_SSM BIT(26)
+#define STM32_SPI_CFG2_AFCNTR BIT(31)
+
+#define STM32_SPI_SR_RXNE BIT(0)
+#define STM32_SPI_SR_UDR BIT(5)
+#define STM32_SPI_SR_FRLVL (3 << 13)
+#define STM32_SPI_SR_TXC BIT(12)
 
 /* --- Debug --- */
-#define STM32_DBGMCU_APB3FZ         REG32(STM32_DBGMCU_BASE + 0x34)
-#define STM32_DBGMCU_APB1LFZ        REG32(STM32_DBGMCU_BASE + 0x3C)
-#define STM32_DBGMCU_APB1HFZ        REG32(STM32_DBGMCU_BASE + 0x44)
-#define STM32_DBGMCU_APB2FZ         REG32(STM32_DBGMCU_BASE + 0x4C)
-#define STM32_DBGMCU_APB4FZ         REG32(STM32_DBGMCU_BASE + 0x54)
+#define STM32_DBGMCU_APB3FZ REG32(STM32_DBGMCU_BASE + 0x34)
+#define STM32_DBGMCU_APB1LFZ REG32(STM32_DBGMCU_BASE + 0x3C)
+#define STM32_DBGMCU_APB1HFZ REG32(STM32_DBGMCU_BASE + 0x44)
+#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x4C)
+#define STM32_DBGMCU_APB4FZ REG32(STM32_DBGMCU_BASE + 0x54)
 /* Alias */
-#define STM32_DBGMCU_APB1FZ         STM32_DBGMCU_APB1LFZ
+#define STM32_DBGMCU_APB1FZ STM32_DBGMCU_APB1LFZ
 
 /* --- Flash --- */
-#define STM32_FLASH_REG(bank, offset)     REG32(((bank) ? 0x100 : 0) + \
-					  STM32_FLASH_REGS_BASE + (offset))
+#define STM32_FLASH_REG(bank, offset) \
+	REG32(((bank) ? 0x100 : 0) + STM32_FLASH_REGS_BASE + (offset))
 
-#define STM32_FLASH_ACR(bank)             STM32_FLASH_REG(bank, 0x00)
+#define STM32_FLASH_ACR(bank) STM32_FLASH_REG(bank, 0x00)
 #define STM32_FLASH_ACR_LATENCY_SHIFT (0)
-#define STM32_FLASH_ACR_LATENCY_MASK  (7 << STM32_FLASH_ACR_LATENCY_SHIFT)
-#define STM32_FLASH_ACR_WRHIGHFREQ_85MHZ  (0 << 4)
+#define STM32_FLASH_ACR_LATENCY_MASK (7 << STM32_FLASH_ACR_LATENCY_SHIFT)
+#define STM32_FLASH_ACR_WRHIGHFREQ_85MHZ (0 << 4)
 #define STM32_FLASH_ACR_WRHIGHFREQ_185MHZ (1 << 4)
 #define STM32_FLASH_ACR_WRHIGHFREQ_285MHZ (2 << 4)
 #define STM32_FLASH_ACR_WRHIGHFREQ_385MHZ (3 << 4)
 
-#define STM32_FLASH_KEYR(bank)            STM32_FLASH_REG(bank, 0x04)
-#define  FLASH_KEYR_KEY1                   0x45670123
-#define  FLASH_KEYR_KEY2                   0xCDEF89AB
-#define STM32_FLASH_OPTKEYR(bank)         STM32_FLASH_REG(bank, 0x08)
-#define  FLASH_OPTKEYR_KEY1                0x08192A3B
-#define  FLASH_OPTKEYR_KEY2                0x4C5D6E7F
-#define STM32_FLASH_CR(bank)              STM32_FLASH_REG(bank, 0x0C)
-#define  FLASH_CR_LOCK                     BIT(0)
-#define  FLASH_CR_PG                       BIT(1)
-#define  FLASH_CR_SER                      BIT(2)
-#define  FLASH_CR_BER                      BIT(3)
-#define  FLASH_CR_PSIZE_BYTE               (0 << 4)
-#define  FLASH_CR_PSIZE_HWORD              (1 << 4)
-#define  FLASH_CR_PSIZE_WORD               (2 << 4)
-#define  FLASH_CR_PSIZE_DWORD              (3 << 4)
-#define  FLASH_CR_PSIZE_MASK               (3 << 4)
-#define  FLASH_CR_FW                       BIT(6)
-#define  FLASH_CR_STRT                     BIT(7)
-#define  FLASH_CR_SNB(sec)                 (((sec) & 0x7) << 8)
-#define  FLASH_CR_SNB_MASK                FLASH_CR_SNB(0x7)
-#define STM32_FLASH_SR(bank)              STM32_FLASH_REG(bank, 0x10)
-#define  FLASH_SR_BUSY                     BIT(0)
-#define  FLASH_SR_WBNE                     BIT(1)
-#define  FLASH_SR_QW                       BIT(2)
-#define  FLASH_SR_CRC_BUSY                 BIT(3)
-#define  FLASH_SR_EOP                      BIT(16)
-#define  FLASH_SR_WRPERR                   BIT(17)
-#define  FLASH_SR_PGSERR                   BIT(18)
-#define  FLASH_SR_STRBERR                  BIT(19)
-#define  FLASH_SR_INCERR                   BIT(21)
-#define  FLASH_SR_OPERR                    BIT(22)
-#define  FLASH_SR_RDPERR                   BIT(23)
-#define  FLASH_SR_RDSERR                   BIT(24)
-#define  FLASH_SR_SNECCERR                 BIT(25)
-#define  FLASH_SR_DBECCERR                 BIT(26)
-#define  FLASH_SR_CRCEND                   BIT(27)
-#define STM32_FLASH_CCR(bank)             STM32_FLASH_REG(bank, 0x14)
-#define  FLASH_CCR_ERR_MASK              (FLASH_SR_WRPERR | FLASH_SR_PGSERR \
-					| FLASH_SR_STRBERR | FLASH_SR_INCERR \
-					| FLASH_SR_OPERR | FLASH_SR_RDPERR \
-					| FLASH_SR_RDSERR | FLASH_SR_SNECCERR \
-					| FLASH_SR_DBECCERR)
-#define STM32_FLASH_OPTCR(bank)           STM32_FLASH_REG(bank, 0x18)
-#define  FLASH_OPTCR_OPTLOCK              BIT(0)
-#define  FLASH_OPTCR_OPTSTART             BIT(1)
-#define STM32_FLASH_OPTSR_CUR(bank)       STM32_FLASH_REG(bank, 0x1C)
-#define STM32_FLASH_OPTSR_PRG(bank)       STM32_FLASH_REG(bank, 0x20)
-#define  FLASH_OPTSR_BUSY                 BIT(0)   /* only in OPTSR_CUR */
-#define  FLASH_OPTSR_RDP_MASK             (0xFF << 8)
-#define  FLASH_OPTSR_RDP_LEVEL_0          (0xAA << 8)
+#define STM32_FLASH_KEYR(bank) STM32_FLASH_REG(bank, 0x04)
+#define FLASH_KEYR_KEY1 0x45670123
+#define FLASH_KEYR_KEY2 0xCDEF89AB
+#define STM32_FLASH_OPTKEYR(bank) STM32_FLASH_REG(bank, 0x08)
+#define FLASH_OPTKEYR_KEY1 0x08192A3B
+#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F
+#define STM32_FLASH_CR(bank) STM32_FLASH_REG(bank, 0x0C)
+#define FLASH_CR_LOCK BIT(0)
+#define FLASH_CR_PG BIT(1)
+#define FLASH_CR_SER BIT(2)
+#define FLASH_CR_BER BIT(3)
+#define FLASH_CR_PSIZE_BYTE (0 << 4)
+#define FLASH_CR_PSIZE_HWORD (1 << 4)
+#define FLASH_CR_PSIZE_WORD (2 << 4)
+#define FLASH_CR_PSIZE_DWORD (3 << 4)
+#define FLASH_CR_PSIZE_MASK (3 << 4)
+#define FLASH_CR_FW BIT(6)
+#define FLASH_CR_STRT BIT(7)
+#define FLASH_CR_SNB(sec) (((sec)&0x7) << 8)
+#define FLASH_CR_SNB_MASK FLASH_CR_SNB(0x7)
+#define STM32_FLASH_SR(bank) STM32_FLASH_REG(bank, 0x10)
+#define FLASH_SR_BUSY BIT(0)
+#define FLASH_SR_WBNE BIT(1)
+#define FLASH_SR_QW BIT(2)
+#define FLASH_SR_CRC_BUSY BIT(3)
+#define FLASH_SR_EOP BIT(16)
+#define FLASH_SR_WRPERR BIT(17)
+#define FLASH_SR_PGSERR BIT(18)
+#define FLASH_SR_STRBERR BIT(19)
+#define FLASH_SR_INCERR BIT(21)
+#define FLASH_SR_OPERR BIT(22)
+#define FLASH_SR_RDPERR BIT(23)
+#define FLASH_SR_RDSERR BIT(24)
+#define FLASH_SR_SNECCERR BIT(25)
+#define FLASH_SR_DBECCERR BIT(26)
+#define FLASH_SR_CRCEND BIT(27)
+#define STM32_FLASH_CCR(bank) STM32_FLASH_REG(bank, 0x14)
+#define FLASH_CCR_ERR_MASK                                      \
+	(FLASH_SR_WRPERR | FLASH_SR_PGSERR | FLASH_SR_STRBERR | \
+	 FLASH_SR_INCERR | FLASH_SR_OPERR | FLASH_SR_RDPERR |   \
+	 FLASH_SR_RDSERR | FLASH_SR_SNECCERR | FLASH_SR_DBECCERR)
+#define STM32_FLASH_OPTCR(bank) STM32_FLASH_REG(bank, 0x18)
+#define FLASH_OPTCR_OPTLOCK BIT(0)
+#define FLASH_OPTCR_OPTSTART BIT(1)
+#define STM32_FLASH_OPTSR_CUR(bank) STM32_FLASH_REG(bank, 0x1C)
+#define STM32_FLASH_OPTSR_PRG(bank) STM32_FLASH_REG(bank, 0x20)
+#define FLASH_OPTSR_BUSY BIT(0) /* only in OPTSR_CUR */
+#define FLASH_OPTSR_RDP_MASK (0xFF << 8)
+#define FLASH_OPTSR_RDP_LEVEL_0 (0xAA << 8)
 /* RDP Level 1: Anything but 0xAA/0xCC */
-#define  FLASH_OPTSR_RDP_LEVEL_1          (0x00 << 8)
-#define  FLASH_OPTSR_RDP_LEVEL_2          (0xCC << 8)
-#define  FLASH_OPTSR_RSS1                 BIT(26)
-#define  FLASH_OPTSR_RSS2                 BIT(27)
-#define STM32_FLASH_OPTCCR(bank)          STM32_FLASH_REG(bank, 0x24)
-#define STM32_FLASH_PRAR_CUR(bank)        STM32_FLASH_REG(bank, 0x28)
-#define STM32_FLASH_PRAR_PRG(bank)        STM32_FLASH_REG(bank, 0x2C)
-#define STM32_FLASH_SCAR_CUR(bank)        STM32_FLASH_REG(bank, 0x30)
-#define STM32_FLASH_SCAR_PRG(bank)        STM32_FLASH_REG(bank, 0x34)
-#define STM32_FLASH_WPSN_CUR(bank)        STM32_FLASH_REG(bank, 0x38)
-#define STM32_FLASH_WPSN_PRG(bank)        STM32_FLASH_REG(bank, 0x3C)
-#define STM32_FLASH_BOOT_CUR(bank)        STM32_FLASH_REG(bank, 0x40)
-#define STM32_FLASH_BOOT_PRG(bank)        STM32_FLASH_REG(bank, 0x44)
-#define STM32_FLASH_CRC_CR(bank)          STM32_FLASH_REG(bank, 0x50)
-#define STM32_FLASH_CRC_SADDR(bank)       STM32_FLASH_REG(bank, 0x54)
-#define STM32_FLASH_CRC_EADDR(bank)       STM32_FLASH_REG(bank, 0x58)
-#define STM32_FLASH_CRC_DATA(bank)        STM32_FLASH_REG(bank, 0x5C)
-#define STM32_FLASH_ECC_FA(bank)          STM32_FLASH_REG(bank, 0x60)
+#define FLASH_OPTSR_RDP_LEVEL_1 (0x00 << 8)
+#define FLASH_OPTSR_RDP_LEVEL_2 (0xCC << 8)
+#define FLASH_OPTSR_RSS1 BIT(26)
+#define FLASH_OPTSR_RSS2 BIT(27)
+#define STM32_FLASH_OPTCCR(bank) STM32_FLASH_REG(bank, 0x24)
+#define STM32_FLASH_PRAR_CUR(bank) STM32_FLASH_REG(bank, 0x28)
+#define STM32_FLASH_PRAR_PRG(bank) STM32_FLASH_REG(bank, 0x2C)
+#define STM32_FLASH_SCAR_CUR(bank) STM32_FLASH_REG(bank, 0x30)
+#define STM32_FLASH_SCAR_PRG(bank) STM32_FLASH_REG(bank, 0x34)
+#define STM32_FLASH_WPSN_CUR(bank) STM32_FLASH_REG(bank, 0x38)
+#define STM32_FLASH_WPSN_PRG(bank) STM32_FLASH_REG(bank, 0x3C)
+#define STM32_FLASH_BOOT_CUR(bank) STM32_FLASH_REG(bank, 0x40)
+#define STM32_FLASH_BOOT_PRG(bank) STM32_FLASH_REG(bank, 0x44)
+#define STM32_FLASH_CRC_CR(bank) STM32_FLASH_REG(bank, 0x50)
+#define STM32_FLASH_CRC_SADDR(bank) STM32_FLASH_REG(bank, 0x54)
+#define STM32_FLASH_CRC_EADDR(bank) STM32_FLASH_REG(bank, 0x58)
+#define STM32_FLASH_CRC_DATA(bank) STM32_FLASH_REG(bank, 0x5C)
+#define STM32_FLASH_ECC_FA(bank) STM32_FLASH_REG(bank, 0x60)
 
 /* --- External Interrupts --- */
-#define STM32_EXTI_RTSR1            REG32(STM32_EXTI_BASE + 0x00)
-#define STM32_EXTI_FTSR1            REG32(STM32_EXTI_BASE + 0x04)
-#define STM32_EXTI_SWIER1           REG32(STM32_EXTI_BASE + 0x08)
-#define STM32_EXTI_D3PMR1           REG32(STM32_EXTI_BASE + 0x0C)
-#define STM32_EXTI_D3PCR1L          REG32(STM32_EXTI_BASE + 0x10)
-#define STM32_EXTI_D3PCR1H          REG32(STM32_EXTI_BASE + 0x14)
-#define STM32_EXTI_RTSR2            REG32(STM32_EXTI_BASE + 0x20)
-#define STM32_EXTI_FTSR2            REG32(STM32_EXTI_BASE + 0x24)
-#define STM32_EXTI_SWIER2           REG32(STM32_EXTI_BASE + 0x28)
-#define STM32_EXTI_D3PMR2           REG32(STM32_EXTI_BASE + 0x2C)
-#define STM32_EXTI_D3PCR2L          REG32(STM32_EXTI_BASE + 0x30)
-#define STM32_EXTI_D3PCR2H          REG32(STM32_EXTI_BASE + 0x34)
-#define STM32_EXTI_RTSR3            REG32(STM32_EXTI_BASE + 0x40)
-#define STM32_EXTI_FTSR3            REG32(STM32_EXTI_BASE + 0x44)
-#define STM32_EXTI_SWIER3           REG32(STM32_EXTI_BASE + 0x48)
-#define STM32_EXTI_D3PMR3           REG32(STM32_EXTI_BASE + 0x4C)
-#define STM32_EXTI_D3PCR3L          REG32(STM32_EXTI_BASE + 0x50)
-#define STM32_EXTI_D3PCR3H          REG32(STM32_EXTI_BASE + 0x54)
-#define STM32_EXTI_CPUIMR1          REG32(STM32_EXTI_BASE + 0x80)
-#define STM32_EXTI_CPUIER1          REG32(STM32_EXTI_BASE + 0x84)
-#define STM32_EXTI_CPUPR1           REG32(STM32_EXTI_BASE + 0x88)
-#define STM32_EXTI_CPUIMR2          REG32(STM32_EXTI_BASE + 0x90)
-#define STM32_EXTI_CPUIER2          REG32(STM32_EXTI_BASE + 0x94)
-#define STM32_EXTI_CPUPR2           REG32(STM32_EXTI_BASE + 0x98)
-#define STM32_EXTI_CPUIMR3          REG32(STM32_EXTI_BASE + 0xA0)
-#define STM32_EXTI_CPUIER3          REG32(STM32_EXTI_BASE + 0xA4)
-#define STM32_EXTI_CPUPR3           REG32(STM32_EXTI_BASE + 0xA8)
+#define STM32_EXTI_RTSR1 REG32(STM32_EXTI_BASE + 0x00)
+#define STM32_EXTI_FTSR1 REG32(STM32_EXTI_BASE + 0x04)
+#define STM32_EXTI_SWIER1 REG32(STM32_EXTI_BASE + 0x08)
+#define STM32_EXTI_D3PMR1 REG32(STM32_EXTI_BASE + 0x0C)
+#define STM32_EXTI_D3PCR1L REG32(STM32_EXTI_BASE + 0x10)
+#define STM32_EXTI_D3PCR1H REG32(STM32_EXTI_BASE + 0x14)
+#define STM32_EXTI_RTSR2 REG32(STM32_EXTI_BASE + 0x20)
+#define STM32_EXTI_FTSR2 REG32(STM32_EXTI_BASE + 0x24)
+#define STM32_EXTI_SWIER2 REG32(STM32_EXTI_BASE + 0x28)
+#define STM32_EXTI_D3PMR2 REG32(STM32_EXTI_BASE + 0x2C)
+#define STM32_EXTI_D3PCR2L REG32(STM32_EXTI_BASE + 0x30)
+#define STM32_EXTI_D3PCR2H REG32(STM32_EXTI_BASE + 0x34)
+#define STM32_EXTI_RTSR3 REG32(STM32_EXTI_BASE + 0x40)
+#define STM32_EXTI_FTSR3 REG32(STM32_EXTI_BASE + 0x44)
+#define STM32_EXTI_SWIER3 REG32(STM32_EXTI_BASE + 0x48)
+#define STM32_EXTI_D3PMR3 REG32(STM32_EXTI_BASE + 0x4C)
+#define STM32_EXTI_D3PCR3L REG32(STM32_EXTI_BASE + 0x50)
+#define STM32_EXTI_D3PCR3H REG32(STM32_EXTI_BASE + 0x54)
+#define STM32_EXTI_CPUIMR1 REG32(STM32_EXTI_BASE + 0x80)
+#define STM32_EXTI_CPUIER1 REG32(STM32_EXTI_BASE + 0x84)
+#define STM32_EXTI_CPUPR1 REG32(STM32_EXTI_BASE + 0x88)
+#define STM32_EXTI_CPUIMR2 REG32(STM32_EXTI_BASE + 0x90)
+#define STM32_EXTI_CPUIER2 REG32(STM32_EXTI_BASE + 0x94)
+#define STM32_EXTI_CPUPR2 REG32(STM32_EXTI_BASE + 0x98)
+#define STM32_EXTI_CPUIMR3 REG32(STM32_EXTI_BASE + 0xA0)
+#define STM32_EXTI_CPUIER3 REG32(STM32_EXTI_BASE + 0xA4)
+#define STM32_EXTI_CPUPR3 REG32(STM32_EXTI_BASE + 0xA8)
 /* Aliases */
-#define STM32_EXTI_IMR              STM32_EXTI_CPUIMR1
-#define STM32_EXTI_EMR              STM32_EXTI_CPUIMR1
-#define STM32_EXTI_RTSR             STM32_EXTI_RTSR1
-#define STM32_EXTI_FTSR             STM32_EXTI_FTSR1
-#define STM32_EXTI_SWIER            STM32_EXTI_SWIER1
-#define STM32_EXTI_PR               STM32_EXTI_CPUPR1
-
+#define STM32_EXTI_IMR STM32_EXTI_CPUIMR1
+#define STM32_EXTI_EMR STM32_EXTI_CPUIMR1
+#define STM32_EXTI_RTSR STM32_EXTI_RTSR1
+#define STM32_EXTI_FTSR STM32_EXTI_FTSR1
+#define STM32_EXTI_SWIER STM32_EXTI_SWIER1
+#define STM32_EXTI_PR STM32_EXTI_CPUPR1
 
 /* --- ADC --- */
 
 /* --- Comparators --- */
 
-
 /* --- DMA --- */
 /*
  * Available DMA streams, numbered from 0.
@@ -879,12 +871,12 @@ enum dma_channel {
 
 /* Registers for a single stream of a DMA controller */
 struct stm32_dma_stream {
-	uint32_t	scr;		/* Control */
-	uint32_t	sndtr;		/* Number of data to transfer */
-	uint32_t	spar;		/* Peripheral address */
-	uint32_t	sm0ar;		/* Memory address 0 */
-	uint32_t	sm1ar;		/*  address 1 for double buffer */
-	uint32_t	sfcr;		/* FIFO control */
+	uint32_t scr; /* Control */
+	uint32_t sndtr; /* Number of data to transfer */
+	uint32_t spar; /* Peripheral address */
+	uint32_t sm0ar; /* Memory address 0 */
+	uint32_t sm1ar; /*  address 1 for double buffer */
+	uint32_t sfcr; /* FIFO control */
 };
 
 /* Always use stm32_dma_stream_t so volatile keyword is included! */
@@ -893,12 +885,11 @@ typedef volatile struct stm32_dma_stream stm32_dma_stream_t;
 /* Common code and header file must use this */
 typedef stm32_dma_stream_t dma_chan_t;
 struct stm32_dma_regs {
-	uint32_t	isr[2];
-	uint32_t	ifcr[2];
+	uint32_t isr[2];
+	uint32_t ifcr[2];
 	stm32_dma_stream_t stream[STM32_DMAS_COUNT];
 };
 
-
 /* Always use stm32_dma_regs_t so volatile keyword is included! */
 typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
 
@@ -909,87 +900,85 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
 #define STM32_DMA_REGS(channel) \
 	((channel) < STM32_DMAS_COUNT ? STM32_DMA1_REGS : STM32_DMA2_REGS)
 
-#define STM32_DMA_CCR_EN                BIT(0)
-#define STM32_DMA_CCR_DMEIE             BIT(1)
-#define STM32_DMA_CCR_TEIE              BIT(2)
-#define STM32_DMA_CCR_HTIE              BIT(3)
-#define STM32_DMA_CCR_TCIE              BIT(4)
-#define STM32_DMA_CCR_PFCTRL            BIT(5)
-#define STM32_DMA_CCR_DIR_P2M           (0 << 6)
-#define STM32_DMA_CCR_DIR_M2P           (1 << 6)
-#define STM32_DMA_CCR_DIR_M2M           (2 << 6)
-#define STM32_DMA_CCR_CIRC              BIT(8)
-#define STM32_DMA_CCR_PINC              BIT(9)
-#define STM32_DMA_CCR_MINC              BIT(10)
-#define STM32_DMA_CCR_PSIZE_8_BIT       (0 << 11)
-#define STM32_DMA_CCR_PSIZE_16_BIT      (1 << 11)
-#define STM32_DMA_CCR_PSIZE_32_BIT      (2 << 11)
-#define STM32_DMA_CCR_MSIZE_8_BIT       (0 << 13)
-#define STM32_DMA_CCR_MSIZE_16_BIT      (1 << 13)
-#define STM32_DMA_CCR_MSIZE_32_BIT      (2 << 13)
-#define STM32_DMA_CCR_PINCOS            BIT(15)
-#define STM32_DMA_CCR_PL_LOW            (0 << 16)
-#define STM32_DMA_CCR_PL_MEDIUM         (1 << 16)
-#define STM32_DMA_CCR_PL_HIGH           (2 << 16)
-#define STM32_DMA_CCR_PL_VERY_HIGH      (3 << 16)
-#define STM32_DMA_CCR_DBM               BIT(18)
-#define STM32_DMA_CCR_CT                BIT(19)
-#define STM32_DMA_CCR_PBURST(b_len)     ((((b_len) - 4) / 4) << 21)
-#define STM32_DMA_CCR_MBURST(b_len)     ((((b_len) - 4) / 4) << 21)
-#define STM32_DMA_CCR_CHANNEL_MASK      (0 << 25)
-#define STM32_DMA_CCR_CHANNEL(channel)  (0)
-#define STM32_DMA_CCR_RSVD_MASK         (0xF0100000)
-#define STM32_DMA_SFCR_DMDIS            BIT(2)
-#define STM32_DMA_SFCR_FTH(level)       (((level) - 1) << 0)
-
-
-#define STM32_DMA_CH_LOCAL(channel)     ((channel) % STM32_DMAS_COUNT)
-#define STM32_DMA_CH_LH(channel)        \
-	((STM32_DMA_CH_LOCAL(channel) < 4) ? 0 : 1)
-#define STM32_DMA_CH_OFFSET(channel)    \
+#define STM32_DMA_CCR_EN BIT(0)
+#define STM32_DMA_CCR_DMEIE BIT(1)
+#define STM32_DMA_CCR_TEIE BIT(2)
+#define STM32_DMA_CCR_HTIE BIT(3)
+#define STM32_DMA_CCR_TCIE BIT(4)
+#define STM32_DMA_CCR_PFCTRL BIT(5)
+#define STM32_DMA_CCR_DIR_P2M (0 << 6)
+#define STM32_DMA_CCR_DIR_M2P (1 << 6)
+#define STM32_DMA_CCR_DIR_M2M (2 << 6)
+#define STM32_DMA_CCR_CIRC BIT(8)
+#define STM32_DMA_CCR_PINC BIT(9)
+#define STM32_DMA_CCR_MINC BIT(10)
+#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 11)
+#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 11)
+#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 11)
+#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 13)
+#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 13)
+#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 13)
+#define STM32_DMA_CCR_PINCOS BIT(15)
+#define STM32_DMA_CCR_PL_LOW (0 << 16)
+#define STM32_DMA_CCR_PL_MEDIUM (1 << 16)
+#define STM32_DMA_CCR_PL_HIGH (2 << 16)
+#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 16)
+#define STM32_DMA_CCR_DBM BIT(18)
+#define STM32_DMA_CCR_CT BIT(19)
+#define STM32_DMA_CCR_PBURST(b_len) ((((b_len)-4) / 4) << 21)
+#define STM32_DMA_CCR_MBURST(b_len) ((((b_len)-4) / 4) << 21)
+#define STM32_DMA_CCR_CHANNEL_MASK (0 << 25)
+#define STM32_DMA_CCR_CHANNEL(channel) (0)
+#define STM32_DMA_CCR_RSVD_MASK (0xF0100000)
+#define STM32_DMA_SFCR_DMDIS BIT(2)
+#define STM32_DMA_SFCR_FTH(level) (((level)-1) << 0)
+
+#define STM32_DMA_CH_LOCAL(channel) ((channel) % STM32_DMAS_COUNT)
+#define STM32_DMA_CH_LH(channel) ((STM32_DMA_CH_LOCAL(channel) < 4) ? 0 : 1)
+#define STM32_DMA_CH_OFFSET(channel)               \
 	(((STM32_DMA_CH_LOCAL(channel) % 4) * 6) + \
-	(((STM32_DMA_CH_LOCAL(channel) % 4) >= 2) ? 4 : 0))
+	 (((STM32_DMA_CH_LOCAL(channel) % 4) >= 2) ? 4 : 0))
 #define STM32_DMA_CH_GETBITS(channel, val) \
 	(((val) >> STM32_DMA_CH_OFFSET(channel)) & 0x3f)
-#define STM32_DMA_GET_IFCR(channel)      \
-	(STM32_DMA_CH_GETBITS(channel,   \
-	STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)]))
-#define STM32_DMA_GET_ISR(channel)       \
-	(STM32_DMA_CH_GETBITS(channel,   \
-	STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)]))
-
-#define STM32_DMA_SET_IFCR(channel, val) \
-	(STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] = \
-	(STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] & \
-	~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel)))
-#define STM32_DMA_SET_ISR(channel, val) \
-	(STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] = \
-	(STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] & \
-	~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel)))
-
-#define STM32_DMA_FEIF                  BIT(0)
-#define STM32_DMA_DMEIF                 BIT(2)
-#define STM32_DMA_TEIF                  BIT(3)
-#define STM32_DMA_HTIF                  BIT(4)
-#define STM32_DMA_TCIF                  BIT(5)
-#define STM32_DMA_ALL                   0x3d
-
+#define STM32_DMA_GET_IFCR(channel) \
+	(STM32_DMA_CH_GETBITS(      \
+		channel,            \
+		STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)]))
+#define STM32_DMA_GET_ISR(channel) \
+	(STM32_DMA_CH_GETBITS(     \
+		channel,           \
+		STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)]))
+
+#define STM32_DMA_SET_IFCR(channel, val)                                    \
+	(STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] =          \
+		 (STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] & \
+		  ~(0x3f << STM32_DMA_CH_OFFSET(channel))) |                \
+		 (((val)&0x3f) << STM32_DMA_CH_OFFSET(channel)))
+#define STM32_DMA_SET_ISR(channel, val)                                    \
+	(STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] =          \
+		 (STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] & \
+		  ~(0x3f << STM32_DMA_CH_OFFSET(channel))) |               \
+		 (((val)&0x3f) << STM32_DMA_CH_OFFSET(channel)))
+
+#define STM32_DMA_FEIF BIT(0)
+#define STM32_DMA_DMEIF BIT(2)
+#define STM32_DMA_TEIF BIT(3)
+#define STM32_DMA_HTIF BIT(4)
+#define STM32_DMA_TCIF BIT(5)
+#define STM32_DMA_ALL 0x3d
 
 /* The requests for the DMA1/DMA2 controllers are routed through DMAMUX1. */
 /* DMAMUX1/2 registers */
 #define DMAMUX1 0
 #define DMAMUX2 1
-#define STM32_DMAMUX_BASE(n)        ((n) ? STM32_DMAMUX2_BASE \
-					 : STM32_DMAMUX1_BASE)
-#define STM32_DMAMUX_REG32(n, off)  REG32(STM32_DMAMUX_BASE(n) + (off))
-#define STM2_DMAMUX_CxCR(n, x)      STM32_DMAMUX_REG32(n, 4 * (x))
-#define STM2_DMAMUX_CSR(n)          STM32_DMAMUX_REG32(n, 0x80)
-#define STM2_DMAMUX_CFR(n)          STM32_DMAMUX_REG32(n, 0x84)
-#define STM2_DMAMUX_RGxCR(n, x)     STM32_DMAMUX_REG32(n, 0x100 + 4 * (x))
-#define STM2_DMAMUX_RGSR(n)         STM32_DMAMUX_REG32(n, 0x140)
-#define STM2_DMAMUX_RGCFR(n)        STM32_DMAMUX_REG32(n, 0x144)
+#define STM32_DMAMUX_BASE(n) ((n) ? STM32_DMAMUX2_BASE : STM32_DMAMUX1_BASE)
+#define STM32_DMAMUX_REG32(n, off) REG32(STM32_DMAMUX_BASE(n) + (off))
+#define STM2_DMAMUX_CxCR(n, x) STM32_DMAMUX_REG32(n, 4 * (x))
+#define STM2_DMAMUX_CSR(n) STM32_DMAMUX_REG32(n, 0x80)
+#define STM2_DMAMUX_CFR(n) STM32_DMAMUX_REG32(n, 0x84)
+#define STM2_DMAMUX_RGxCR(n, x) STM32_DMAMUX_REG32(n, 0x100 + 4 * (x))
+#define STM2_DMAMUX_RGSR(n) STM32_DMAMUX_REG32(n, 0x140)
+#define STM2_DMAMUX_RGCFR(n) STM32_DMAMUX_REG32(n, 0x144)
 
 enum dmamux1_request {
 	DMAMUX1_REQ_ADC1 = 9,
@@ -1091,138 +1080,63 @@ enum dmamux1_request {
 };
 
 /* --- CRC --- */
-#define STM32_CRC_DR                REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR32              REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR16              REG16(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR8               REG8(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_IDR               REG32(STM32_CRC_BASE + 0x4)
-#define STM32_CRC_CR                REG32(STM32_CRC_BASE + 0x8)
-#define  STM32_CRC_CR_RESET          BIT(0)
-#define  STM32_CRC_CR_POLYSIZE_32    (0 << 3)
-#define  STM32_CRC_CR_POLYSIZE_16    (1 << 3)
-#define  STM32_CRC_CR_POLYSIZE_8     (2 << 3)
-#define  STM32_CRC_CR_POLYSIZE_7     (3 << 3)
-#define  STM32_CRC_CR_REV_IN_BYTE    (1 << 5)
-#define  STM32_CRC_CR_REV_IN_HWORD   (2 << 5)
-#define  STM32_CRC_CR_REV_IN_WORD    (3 << 5)
-#define  STM32_CRC_CR_REV_OUT        BIT(7)
-#define STM32_CRC_INIT              REG32(STM32_CRC_BASE + 0x10)
-#define STM32_CRC_POL               REG32(STM32_CRC_BASE + 0x14)
+#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4)
+#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8)
+#define STM32_CRC_CR_RESET BIT(0)
+#define STM32_CRC_CR_POLYSIZE_32 (0 << 3)
+#define STM32_CRC_CR_POLYSIZE_16 (1 << 3)
+#define STM32_CRC_CR_POLYSIZE_8 (2 << 3)
+#define STM32_CRC_CR_POLYSIZE_7 (3 << 3)
+#define STM32_CRC_CR_REV_IN_BYTE (1 << 5)
+#define STM32_CRC_CR_REV_IN_HWORD (2 << 5)
+#define STM32_CRC_CR_REV_IN_WORD (3 << 5)
+#define STM32_CRC_CR_REV_OUT BIT(7)
+#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10)
+#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14)
 
 /* --- PMSE --- */
-#define STM32_PMSE_ARCR             REG32(STM32_PMSE_BASE + 0x0)
-#define STM32_PMSE_ACCR             REG32(STM32_PMSE_BASE + 0x4)
-#define STM32_PMSE_CR               REG32(STM32_PMSE_BASE + 0x8)
-#define STM32_PMSE_CRTDR            REG32(STM32_PMSE_BASE + 0x14)
-#define STM32_PMSE_IER              REG32(STM32_PMSE_BASE + 0x18)
-#define STM32_PMSE_SR               REG32(STM32_PMSE_BASE + 0x1c)
-#define STM32_PMSE_IFCR             REG32(STM32_PMSE_BASE + 0x20)
-#define STM32_PMSE_PxPMR(x)         REG32(STM32_PMSE_BASE + 0x2c + (x) * 4)
-#define STM32_PMSE_PAPMR            REG32(STM32_PMSE_BASE + 0x2c)
-#define STM32_PMSE_PBPMR            REG32(STM32_PMSE_BASE + 0x30)
-#define STM32_PMSE_PCPMR            REG32(STM32_PMSE_BASE + 0x34)
-#define STM32_PMSE_PDPMR            REG32(STM32_PMSE_BASE + 0x38)
-#define STM32_PMSE_PEPMR            REG32(STM32_PMSE_BASE + 0x3c)
-#define STM32_PMSE_PFPMR            REG32(STM32_PMSE_BASE + 0x40)
-#define STM32_PMSE_PGPMR            REG32(STM32_PMSE_BASE + 0x44)
-#define STM32_PMSE_PHPMR            REG32(STM32_PMSE_BASE + 0x48)
-#define STM32_PMSE_PIPMR            REG32(STM32_PMSE_BASE + 0x4c)
-#define STM32_PMSE_MRCR             REG32(STM32_PMSE_BASE + 0x100)
-#define STM32_PMSE_MCCR             REG32(STM32_PMSE_BASE + 0x104)
-
-/* --- USB --- */
-#define STM32_USB_EP(n)            REG16(STM32_USB_FS_BASE + (n) * 4)
-
-#define STM32_USB_CNTR             REG16(STM32_USB_FS_BASE + 0x40)
-#define  STM32_USB_CNTR_FRES        BIT(0)
-#define  STM32_USB_CNTR_PDWN        BIT(1)
-#define  STM32_USB_CNTR_LP_MODE     BIT(2)
-#define  STM32_USB_CNTR_FSUSP       BIT(3)
-#define  STM32_USB_CNTR_RESUME      BIT(4)
-#define  STM32_USB_CNTR_L1RESUME    BIT(5)
-#define  STM32_USB_CNTR_L1REQM      BIT(7)
-#define  STM32_USB_CNTR_ESOFM       BIT(8)
-#define  STM32_USB_CNTR_SOFM        BIT(9)
-#define  STM32_USB_CNTR_RESETM      BIT(10)
-#define  STM32_USB_CNTR_SUSPM       BIT(11)
-#define  STM32_USB_CNTR_WKUPM       BIT(12)
-#define  STM32_USB_CNTR_ERRM        BIT(13)
-#define  STM32_USB_CNTR_PMAOVRM     BIT(14)
-#define  STM32_USB_CNTR_CTRM        BIT(15)
-
-#define STM32_USB_ISTR             REG16(STM32_USB_FS_BASE + 0x44)
-#define  STM32_USB_ISTR_EP_ID_MASK  (0x000f)
-#define  STM32_USB_ISTR_DIR         BIT(4)
-#define  STM32_USB_ISTR_L1REQ       BIT(7)
-#define  STM32_USB_ISTR_ESOF        BIT(8)
-#define  STM32_USB_ISTR_SOF         BIT(9)
-#define  STM32_USB_ISTR_RESET       BIT(10)
-#define  STM32_USB_ISTR_SUSP        BIT(11)
-#define  STM32_USB_ISTR_WKUP        BIT(12)
-#define  STM32_USB_ISTR_ERR         BIT(13)
-#define  STM32_USB_ISTR_PMAOVR      BIT(14)
-#define  STM32_USB_ISTR_CTR         BIT(15)
-
-#define STM32_USB_FNR              REG16(STM32_USB_FS_BASE + 0x48)
-
-#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14)
-#define STM32_USB_FNR_RXDP_RXDM_MASK  (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT)
-
-#define STM32_USB_DADDR            REG16(STM32_USB_FS_BASE + 0x4C)
-#define STM32_USB_BTABLE           REG16(STM32_USB_FS_BASE + 0x50)
-#define STM32_USB_LPMCSR           REG16(STM32_USB_FS_BASE + 0x54)
-#define STM32_USB_BCDR             REG16(STM32_USB_FS_BASE + 0x58)
-#define  STM32_USB_BCDR_BCDEN       BIT(0)
-#define  STM32_USB_BCDR_DCDEN       BIT(1)
-#define  STM32_USB_BCDR_PDEN        BIT(2)
-#define  STM32_USB_BCDR_SDEN        BIT(3)
-#define  STM32_USB_BCDR_DCDET       BIT(4)
-#define  STM32_USB_BCDR_PDET        BIT(5)
-#define  STM32_USB_BCDR_SDET        BIT(6)
-#define  STM32_USB_BCDR_PS2DET      BIT(7)
-
-#define EP_MASK     0x0F0F
-#define EP_TX_DTOG  0x0040
-#define EP_TX_MASK  0x0030
-#define EP_TX_VALID 0x0030
-#define EP_TX_NAK   0x0020
-#define EP_TX_STALL 0x0010
-#define EP_TX_DISAB 0x0000
-#define EP_RX_DTOG  0x4000
-#define EP_RX_MASK  0x3000
-#define EP_RX_VALID 0x3000
-#define EP_RX_NAK   0x2000
-#define EP_RX_STALL 0x1000
-#define EP_RX_DISAB 0x0000
-
-#define EP_STATUS_OUT 0x0100
-
-#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK)
-#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID)
-
-#define STM32_TOGGLE_EP(n, mask, val, flags) \
-	STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \
-			^ (val)) | (flags))
+#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0)
+#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4)
+#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8)
+#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14)
+#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18)
+#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c)
+#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20)
+#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x)*4)
+#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c)
+#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30)
+#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34)
+#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38)
+#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c)
+#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40)
+#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44)
+#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48)
+#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c)
+#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100)
+#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104)
 
 /* --- TRNG --- */
-#define STM32_RNG_CR                REG32(STM32_RNG_BASE + 0x0)
-#define  STM32_RNG_CR_RNGEN          BIT(2)
-#define  STM32_RNG_CR_IE             BIT(3)
-#define  STM32_RNG_CR_CED            BIT(5)
-#define STM32_RNG_SR                REG32(STM32_RNG_BASE + 0x4)
-#define  STM32_RNG_SR_DRDY           BIT(0)
-#define STM32_RNG_DR                REG32(STM32_RNG_BASE + 0x8)
+#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0)
+#define STM32_RNG_CR_RNGEN BIT(2)
+#define STM32_RNG_CR_IE BIT(3)
+#define STM32_RNG_CR_CED BIT(5)
+#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4)
+#define STM32_RNG_SR_DRDY BIT(0)
+#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8)
 
 /* --- AXI interconnect --- */
 
 /* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */
-#define STM32_AXI_TARG_FN_MOD(x)    REG32(STM32_GPV_BASE + 0x1108 + \
-					  0x1000 * (x))
-#define  WRITE_ISS_OVERRIDE          BIT(1)
-#define  READ_ISS_OVERRIDE           BIT(0)
+#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + 0x1000 * (x))
+#define WRITE_ISS_OVERRIDE BIT(1)
+#define READ_ISS_OVERRIDE BIT(0)
 
 /* --- MISC --- */
-#define STM32_UNIQUE_ID_ADDRESS     REG32_ADDR(STM32_UNIQUE_ID_BASE)
-#define STM32_UNIQUE_ID_LENGTH      (3 * 4)
+#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE)
+#define STM32_UNIQUE_ID_LENGTH (3 * 4)
 
 #endif /* !__ASSEMBLER__ */
diff --git a/chip/stm32/registers-stm32l.h b/chip/stm32/registers-stm32l.h
index 37b31ac302..07ead4411a 100644
--- a/chip/stm32/registers-stm32l.h
+++ b/chip/stm32/registers-stm32l.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,401 +20,393 @@
 #endif
 
 /* --- IRQ numbers --- */
-#define STM32_IRQ_WWDG             0
-#define STM32_IRQ_PVD              1
-#define STM32_IRQ_TAMPER_STAMP     2
-#define STM32_IRQ_RTC_WAKEUP       3
-#define STM32_IRQ_FLASH            4
-#define STM32_IRQ_RCC              5
-#define STM32_IRQ_EXTI0            6
-#define STM32_IRQ_EXTI1            7
-#define STM32_IRQ_EXTI2            8
-#define STM32_IRQ_EXTI3            9
-#define STM32_IRQ_EXTI4           10
-#define STM32_IRQ_DMA_CHANNEL_1   11
-#define STM32_IRQ_DMA_CHANNEL_2   12
-#define STM32_IRQ_DMA_CHANNEL_3   13
-#define STM32_IRQ_DMA_CHANNEL_4   14
-#define STM32_IRQ_DMA_CHANNEL_5   15
-#define STM32_IRQ_DMA_CHANNEL_6   16
-#define STM32_IRQ_DMA_CHANNEL_7   17
-#define STM32_IRQ_USB_HP          19
-#define STM32_IRQ_USB_LP          20
-
-#define STM32_IRQ_ADC1            18 /* STM32L4 only */
-#define STM32_IRQ_CAN_TX          19 /* STM32F373 only */
-#define STM32_IRQ_USB_LP_CAN_RX   20 /* STM32F373 only */
-#define STM32_IRQ_DAC             21
-#define STM32_IRQ_CAN_RX1         21 /* STM32F373 only */
-
-#define STM32_IRQ_COMP            22
-
-#define STM32_IRQ_CAN_SCE         22 /* STM32F373 only */
-#define STM32_IRQ_EXTI9_5         23
-#define STM32_IRQ_LCD             24 /* STM32L15X only */
-#define STM32_IRQ_TIM15           24 /* STM32F373 only */
-#define STM32_IRQ_TIM9            25 /* STM32L15X only */
-#define STM32_IRQ_TIM16           25 /* STM32F373 only */
-#define STM32_IRQ_TIM10           26 /* STM32L15X only */
-#define STM32_IRQ_TIM17           26 /* STM32F373 only */
-#define STM32_IRQ_TIM11           27 /* STM32L15X only */
-#define STM32_IRQ_TIM18_DAC2      27 /* STM32F373 only */
-#define STM32_IRQ_TIM2            28
-#define STM32_IRQ_TIM3            29
-#define STM32_IRQ_TIM4            30
-#define STM32_IRQ_I2C1_EV         31
-#define STM32_IRQ_I2C1_ER         32
-#define STM32_IRQ_I2C2_EV         33
-#define STM32_IRQ_I2C2_ER         34
-#define STM32_IRQ_SPI1            35
-#define STM32_IRQ_SPI2            36
-#define STM32_IRQ_USART1          37
-#define STM32_IRQ_USART2          38
-#define STM32_IRQ_USART3          39
-#define STM32_IRQ_EXTI15_10       40
-#define STM32_IRQ_RTC_ALARM       41
-#define STM32_IRQ_USB_FS_WAKEUP   42 /* STM32L15X */
-#define STM32_IRQ_CEC             42 /* STM32F373 only */
-#define STM32_IRQ_TIM6_BASIC      43 /* STM32L15X only */
-#define STM32_IRQ_TIM12           43 /* STM32F373 only */
-#define STM32_IRQ_TIM7_BASIC      44 /* STM32L15X only */
-#define STM32_IRQ_TIM13           44 /* STM32F373 only */
-#define STM32_IRQ_TIM14           45 /* STM32F373 only */
-#define STM32_IRQ_TIM5            50 /* STM32F373 */
-#define STM32_IRQ_SPI3            51 /* STM32F373 */
-#define STM32_IRQ_USART4          52 /* STM32F446 only */
-#define STM32_IRQ_USART5          53 /* STM32F446 only */
-#define STM32_IRQ_TIM6_DAC        54 /* STM32F373 */
-#define STM32_IRQ_TIM7            55 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL1   56 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL2   57 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL3   58 /* STM32F373 */
-#define STM32_IRQ_DMA2_CHANNEL4   59 /* STM32F373 only */
+#define STM32_IRQ_WWDG 0
+#define STM32_IRQ_PVD 1
+#define STM32_IRQ_TAMPER_STAMP 2
+#define STM32_IRQ_RTC_WAKEUP 3
+#define STM32_IRQ_FLASH 4
+#define STM32_IRQ_RCC 5
+#define STM32_IRQ_EXTI0 6
+#define STM32_IRQ_EXTI1 7
+#define STM32_IRQ_EXTI2 8
+#define STM32_IRQ_EXTI3 9
+#define STM32_IRQ_EXTI4 10
+#define STM32_IRQ_DMA_CHANNEL_1 11
+#define STM32_IRQ_DMA_CHANNEL_2 12
+#define STM32_IRQ_DMA_CHANNEL_3 13
+#define STM32_IRQ_DMA_CHANNEL_4 14
+#define STM32_IRQ_DMA_CHANNEL_5 15
+#define STM32_IRQ_DMA_CHANNEL_6 16
+#define STM32_IRQ_DMA_CHANNEL_7 17
+#define STM32_IRQ_USB_HP 19
+#define STM32_IRQ_USB_LP 20
+
+#define STM32_IRQ_ADC1 18 /* STM32L4 only */
+#define STM32_IRQ_CAN_TX 19 /* STM32F373 only */
+#define STM32_IRQ_USB_LP_CAN_RX 20 /* STM32F373 only */
+#define STM32_IRQ_DAC 21
+#define STM32_IRQ_CAN_RX1 21 /* STM32F373 only */
+
+#define STM32_IRQ_COMP 22
+
+#define STM32_IRQ_CAN_SCE 22 /* STM32F373 only */
+#define STM32_IRQ_EXTI9_5 23
+#define STM32_IRQ_LCD 24 /* STM32L15X only */
+#define STM32_IRQ_TIM15 24 /* STM32F373 only */
+#define STM32_IRQ_TIM9 25 /* STM32L15X only */
+#define STM32_IRQ_TIM16 25 /* STM32F373 only */
+#define STM32_IRQ_TIM10 26 /* STM32L15X only */
+#define STM32_IRQ_TIM17 26 /* STM32F373 only */
+#define STM32_IRQ_TIM11 27 /* STM32L15X only */
+#define STM32_IRQ_TIM18_DAC2 27 /* STM32F373 only */
+#define STM32_IRQ_TIM2 28
+#define STM32_IRQ_TIM3 29
+#define STM32_IRQ_TIM4 30
+#define STM32_IRQ_I2C1_EV 31
+#define STM32_IRQ_I2C1_ER 32
+#define STM32_IRQ_I2C2_EV 33
+#define STM32_IRQ_I2C2_ER 34
+#define STM32_IRQ_SPI1 35
+#define STM32_IRQ_SPI2 36
+#define STM32_IRQ_USART1 37
+#define STM32_IRQ_USART2 38
+#define STM32_IRQ_USART3 39
+#define STM32_IRQ_EXTI15_10 40
+#define STM32_IRQ_RTC_ALARM 41
+#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X */
+#define STM32_IRQ_CEC 42 /* STM32F373 only */
+#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */
+#define STM32_IRQ_TIM12 43 /* STM32F373 only */
+#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */
+#define STM32_IRQ_TIM13 44 /* STM32F373 only */
+#define STM32_IRQ_TIM14 45 /* STM32F373 only */
+#define STM32_IRQ_TIM5 50 /* STM32F373 */
+#define STM32_IRQ_SPI3 51 /* STM32F373 */
+#define STM32_IRQ_USART4 52 /* STM32F446 only */
+#define STM32_IRQ_USART5 53 /* STM32F446 only */
+#define STM32_IRQ_TIM6_DAC 54 /* STM32F373 */
+#define STM32_IRQ_TIM7 55 /* STM32F373 */
+#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F373 */
+#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F373 */
+#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F373 */
+#define STM32_IRQ_DMA2_CHANNEL4 59 /* STM32F373 only */
 /* if MISC_REMAP bits are set */
-#define STM32_IRQ_DMA2_CHANNEL5   60 /* STM32F373 */
-#define STM32_IRQ_SDADC1          61 /* STM32F373 only */
-#define STM32_IRQ_SDADC2          62 /* STM32F373 only */
-#define STM32_IRQ_SDADC3          63 /* STM32F373 only */
-#define STM32_IRQ_DMA2_CHANNEL6   68 /* STM32L4 only */
-#define STM32_IRQ_DMA2_CHANNEL7   69 /* STM32L4 only */
-#define STM32_IRQ_LPUART          70 /* STM32L4 only */
-#define STM32_IRQ_USART9          70 /* STM32L4 only */
-#define STM32_IRQ_USART6          71 /* STM32F446 only */
-#define STM32_IRQ_I2C3_EV         72 /* STM32F446 only */
-#define STM32_IRQ_I2C3_ER         73 /* STM32F446 only */
-#define STM32_IRQ_USB_WAKEUP      76 /* STM32F373 only */
-#define STM32_IRQ_TIM19           78 /* STM32F373 only */
-#define STM32_IRQ_AES             79 /* STM32L4 only */
-#define STM32_IRQ_RNG             80 /* STM32L4 only */
-#define STM32_IRQ_FPU             81 /* STM32F373 only */
-
+#define STM32_IRQ_DMA2_CHANNEL5 60 /* STM32F373 */
+#define STM32_IRQ_SDADC1 61 /* STM32F373 only */
+#define STM32_IRQ_SDADC2 62 /* STM32F373 only */
+#define STM32_IRQ_SDADC3 63 /* STM32F373 only */
+#define STM32_IRQ_DMA2_CHANNEL6 68 /* STM32L4 only */
+#define STM32_IRQ_DMA2_CHANNEL7 69 /* STM32L4 only */
+#define STM32_IRQ_LPUART 70 /* STM32L4 only */
+#define STM32_IRQ_USART9 70 /* STM32L4 only */
+#define STM32_IRQ_USART6 71 /* STM32F446 only */
+#define STM32_IRQ_I2C3_EV 72 /* STM32F446 only */
+#define STM32_IRQ_I2C3_ER 73 /* STM32F446 only */
+#define STM32_IRQ_USB_WAKEUP 76 /* STM32F373 only */
+#define STM32_IRQ_TIM19 78 /* STM32F373 only */
+#define STM32_IRQ_AES 79 /* STM32L4 only */
+#define STM32_IRQ_RNG 80 /* STM32L4 only */
+#define STM32_IRQ_FPU 81 /* STM32F373 only */
 
 /* To simplify code generation, define DMA channel 9..10 */
-#define STM32_IRQ_DMA_CHANNEL_9    STM32_IRQ_DMA2_CHANNEL1
-#define STM32_IRQ_DMA_CHANNEL_10   STM32_IRQ_DMA2_CHANNEL2
-#define STM32_IRQ_DMA_CHANNEL_13   STM32_IRQ_DMA2_CHANNEL6
-#define STM32_IRQ_DMA_CHANNEL_14   STM32_IRQ_DMA2_CHANNEL7
+#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1
+#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2
+#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6
+#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7
 
 /* aliases for easier code sharing */
 #define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV
 #define STM32_IRQ_I2C2 STM32_IRQ_I2C2_EV
 #define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV
 
-
-
 /* Peripheral base addresses */
-#define STM32_ADC1_BASE             0x40012400
-#define STM32_ADC_BASE              0x40012700 /* STM32L15X only */
-
-#define STM32_CEC_BASE              0x40007800 /* STM32F373 */
-#define STM32_CRC_BASE              0x40023000
-#define STM32_CRS_BASE              0x40006c00 /* STM32F0XX */
-#define STM32_DAC_BASE              0x40007400
+#define STM32_ADC1_BASE 0x40012400
+#define STM32_ADC_BASE 0x40012700 /* STM32L15X only */
 
-#define STM32_COMP_BASE             0x40007C00
+#define STM32_CEC_BASE 0x40007800 /* STM32F373 */
+#define STM32_CRC_BASE 0x40023000
+#define STM32_CRS_BASE 0x40006c00 /* STM32F0XX */
+#define STM32_DAC_BASE 0x40007400
 
-#define STM32_DBGMCU_BASE           0xE0042000
+#define STM32_COMP_BASE 0x40007C00
 
-#define STM32_DMA1_BASE             0x40026000
+#define STM32_DBGMCU_BASE 0xE0042000
 
-#define STM32_EXTI_BASE             0x40010400
+#define STM32_DMA1_BASE 0x40026000
 
-#define STM32_FLASH_REGS_BASE       0x40023c00
+#define STM32_EXTI_BASE 0x40010400
 
-#define STM32_GPIOA_BASE            0x40020000
-#define STM32_GPIOB_BASE            0x40020400
-#define STM32_GPIOC_BASE            0x40020800
-#define STM32_GPIOD_BASE            0x40020C00
-#define STM32_GPIOE_BASE            0x40021000
-#define STM32_GPIOF_BASE            0x40021800 /* see RM0038 table 5 */
-#define STM32_GPIOG_BASE            0x40021C00
-#define STM32_GPIOH_BASE            0x40021400
+#define STM32_FLASH_REGS_BASE 0x40023c00
 
-#define STM32_I2C1_BASE             0x40005400
-#define STM32_I2C2_BASE             0x40005800
-#define STM32_I2C3_BASE             0x40005C00
-#define STM32_I2C4_BASE             0x40006000
+#define STM32_GPIOA_BASE 0x40020000
+#define STM32_GPIOB_BASE 0x40020400
+#define STM32_GPIOC_BASE 0x40020800
+#define STM32_GPIOD_BASE 0x40020C00
+#define STM32_GPIOE_BASE 0x40021000
+#define STM32_GPIOF_BASE 0x40021800 /* see RM0038 table 5 */
+#define STM32_GPIOG_BASE 0x40021C00
+#define STM32_GPIOH_BASE 0x40021400
 
-#define STM32_IWDG_BASE             0x40003000
-#define STM32_LCD_BASE              0x40002400
+#define STM32_I2C1_BASE 0x40005400
+#define STM32_I2C2_BASE 0x40005800
+#define STM32_I2C3_BASE 0x40005C00
+#define STM32_I2C4_BASE 0x40006000
 
-#define STM32_OPTB_BASE             0x1ff80000
+#define STM32_IWDG_BASE 0x40003000
+#define STM32_LCD_BASE 0x40002400
 
-#define STM32_PMSE_BASE             0x40013400
-#define STM32_PWR_BASE              0x40007000
+#define STM32_OPTB_BASE 0x1ff80000
 
-#define STM32_RCC_BASE              0x40023800
+#define STM32_PMSE_BASE 0x40013400
+#define STM32_PWR_BASE 0x40007000
 
-#define STM32_RI_BASE               0x40007C00 /* STM32L1xx only */
-#define STM32_RNG_BASE              0x50060800 /* STM32L4 */
-#define STM32_RTC_BASE              0x40002800
+#define STM32_RCC_BASE 0x40023800
 
-#define STM32_SPI1_BASE             0x40013000
-#define STM32_SPI2_BASE             0x40003800
-#define STM32_SPI3_BASE             0x40003c00 /* STM32F373, STM32L4, STM32F7 */
+#define STM32_RI_BASE 0x40007C00 /* STM32L1xx only */
+#define STM32_RNG_BASE 0x50060800 /* STM32L4 */
+#define STM32_RTC_BASE 0x40002800
 
-#define STM32_SYSCFG_BASE           0x40010000
+#define STM32_SPI1_BASE 0x40013000
+#define STM32_SPI2_BASE 0x40003800
+#define STM32_SPI3_BASE 0x40003c00 /* STM32F373, STM32L4, STM32F7 */
 
-#define STM32_TIM1_BASE             0x40012c00 /* STM32F373 */
-#define STM32_TIM2_BASE             0x40000000
-#define STM32_TIM3_BASE             0x40000400
-#define STM32_TIM4_BASE             0x40000800
-#define STM32_TIM5_BASE             0x40000c00 /* STM32F373 */
-#define STM32_TIM6_BASE             0x40001000
-#define STM32_TIM7_BASE             0x40001400
-#define STM32_TIM9_BASE             0x40010800 /* STM32L15X only */
-#define STM32_TIM10_BASE            0x40010C00 /* STM32L15X only */
-#define STM32_TIM11_BASE            0x40011000 /* STM32L15X only */
-#define STM32_TIM12_BASE            0x40001800 /* STM32F373 */
-#define STM32_TIM13_BASE            0x40001c00 /* STM32F373 */
-#define STM32_TIM14_BASE            0x40002000 /* STM32F373 */
-#define STM32_TIM15_BASE            0x40014000
-#define STM32_TIM16_BASE            0x40014400
-#define STM32_TIM17_BASE            0x40014800
-#define STM32_TIM18_BASE            0x40009c00 /* STM32F373 only */
-#define STM32_TIM19_BASE            0x40015c00 /* STM32F373 only */
+#define STM32_SYSCFG_BASE 0x40010000
 
-#define STM32_UNIQUE_ID_BASE        0x1ffff7ac
+#define STM32_TIM1_BASE 0x40012c00 /* STM32F373 */
+#define STM32_TIM2_BASE 0x40000000
+#define STM32_TIM3_BASE 0x40000400
+#define STM32_TIM4_BASE 0x40000800
+#define STM32_TIM5_BASE 0x40000c00 /* STM32F373 */
+#define STM32_TIM6_BASE 0x40001000
+#define STM32_TIM7_BASE 0x40001400
+#define STM32_TIM9_BASE 0x40010800 /* STM32L15X only */
+#define STM32_TIM10_BASE 0x40010C00 /* STM32L15X only */
+#define STM32_TIM11_BASE 0x40011000 /* STM32L15X only */
+#define STM32_TIM12_BASE 0x40001800 /* STM32F373 */
+#define STM32_TIM13_BASE 0x40001c00 /* STM32F373 */
+#define STM32_TIM14_BASE 0x40002000 /* STM32F373 */
+#define STM32_TIM15_BASE 0x40014000
+#define STM32_TIM16_BASE 0x40014400
+#define STM32_TIM17_BASE 0x40014800
+#define STM32_TIM18_BASE 0x40009c00 /* STM32F373 only */
+#define STM32_TIM19_BASE 0x40015c00 /* STM32F373 only */
 
-#define STM32_USART1_BASE           0x40013800
-#define STM32_USART2_BASE           0x40004400
-#define STM32_USART3_BASE           0x40004800
-#define STM32_USART4_BASE           0x40004c00
-#define STM32_USART9_BASE           0x40008000 /* LPUART */
+#define STM32_UNIQUE_ID_BASE 0x1ffff7ac
 
-#define STM32_USB_CAN_SRAM_BASE     0x40006000
-#define STM32_USB_FS_BASE           0x40005C00
+#define STM32_USART1_BASE 0x40013800
+#define STM32_USART2_BASE 0x40004400
+#define STM32_USART3_BASE 0x40004800
+#define STM32_USART4_BASE 0x40004c00
+#define STM32_USART9_BASE 0x40008000 /* LPUART */
 
-#define STM32_WWDG_BASE             0x40002C00
+#define STM32_USB_CAN_SRAM_BASE 0x40006000
+#define STM32_USB_FS_BASE 0x40005C00
 
+#define STM32_WWDG_BASE 0x40002C00
 
 #ifndef __ASSEMBLER__
 
 /* Register definitions */
 
 /* --- USART --- */
-#define STM32_USART_SR(base)       STM32_USART_REG(base, 0x00)
-#define STM32_USART_SR_ORE		BIT(3)
-#define STM32_USART_SR_RXNE		BIT(5)
-#define STM32_USART_SR_TC		BIT(6)
-#define STM32_USART_SR_TXE		BIT(7)
-#define STM32_USART_DR(base)       STM32_USART_REG(base, 0x04)
-#define STM32_USART_BRR(base)      STM32_USART_REG(base, 0x08)
-#define STM32_USART_CR1(base)      STM32_USART_REG(base, 0x0C)
-#define STM32_USART_CR1_RE		BIT(2)
-#define STM32_USART_CR1_TE		BIT(3)
-#define STM32_USART_CR1_RXNEIE		BIT(5)
-#define STM32_USART_CR1_TCIE		BIT(6)
-#define STM32_USART_CR1_TXEIE		BIT(7)
-#define STM32_USART_CR1_PS		BIT(9)
-#define STM32_USART_CR1_PCE		BIT(10)
-#define STM32_USART_CR1_M		BIT(12)
-#define STM32_USART_CR1_UE		BIT(13)
-#define STM32_USART_CR1_OVER8		BIT(15) /* STM32L only */
-#define STM32_USART_CR2(base)      STM32_USART_REG(base, 0x10)
-#define STM32_USART_CR3(base)      STM32_USART_REG(base, 0x14)
-#define STM32_USART_CR3_EIE		BIT(0)
-#define STM32_USART_CR3_DMAR		BIT(6)
-#define STM32_USART_CR3_DMAT		BIT(7)
-#define STM32_USART_CR3_ONEBIT		BIT(11) /* STM32L only */
-#define STM32_USART_GTPR(base)     STM32_USART_REG(base, 0x18)
+#define STM32_USART_SR(base) STM32_USART_REG(base, 0x00)
+#define STM32_USART_SR_ORE BIT(3)
+#define STM32_USART_SR_RXNE BIT(5)
+#define STM32_USART_SR_TC BIT(6)
+#define STM32_USART_SR_TXE BIT(7)
+#define STM32_USART_DR(base) STM32_USART_REG(base, 0x04)
+#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x08)
+#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x0C)
+#define STM32_USART_CR1_RE BIT(2)
+#define STM32_USART_CR1_TE BIT(3)
+#define STM32_USART_CR1_RXNEIE BIT(5)
+#define STM32_USART_CR1_TCIE BIT(6)
+#define STM32_USART_CR1_TXEIE BIT(7)
+#define STM32_USART_CR1_PS BIT(9)
+#define STM32_USART_CR1_PCE BIT(10)
+#define STM32_USART_CR1_M BIT(12)
+#define STM32_USART_CR1_UE BIT(13)
+#define STM32_USART_CR1_OVER8 BIT(15) /* STM32L only */
+#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x10)
+#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x14)
+#define STM32_USART_CR3_EIE BIT(0)
+#define STM32_USART_CR3_DMAR BIT(6)
+#define STM32_USART_CR3_DMAT BIT(7)
+#define STM32_USART_CR3_ONEBIT BIT(11) /* STM32L only */
+#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x18)
 /* register aliases */
-#define STM32_USART_TDR(base)      STM32_USART_DR(base)
-#define STM32_USART_RDR(base)      STM32_USART_DR(base)
+#define STM32_USART_TDR(base) STM32_USART_DR(base)
+#define STM32_USART_RDR(base) STM32_USART_DR(base)
 
 /* --- GPIO --- */
 
-
-#define STM32_GPIO_MODER(b)     REG32((b) + 0x00)
-#define STM32_GPIO_OTYPER(b)    REG16((b) + 0x04)
-#define STM32_GPIO_OSPEEDR(b)   REG32((b) + 0x08)
-#define STM32_GPIO_PUPDR(b)     REG32((b) + 0x0C)
-#define STM32_GPIO_IDR(b)       REG16((b) + 0x10)
-#define STM32_GPIO_ODR(b)       REG16((b) + 0x14)
-#define STM32_GPIO_BSRR(b)      REG32((b) + 0x18)
-#define STM32_GPIO_LCKR(b)      REG32((b) + 0x1C)
-#define STM32_GPIO_AFRL(b)      REG32((b) + 0x20)
-#define STM32_GPIO_AFRH(b)      REG32((b) + 0x24)
-
-#define GPIO_ALT_SYS                 0x0
-#define GPIO_ALT_TIM2                0x1
-#define GPIO_ALT_TIM3_4              0x2
-#define GPIO_ALT_TIM9_11             0x3
-#define GPIO_ALT_I2C                 0x4
-#define GPIO_ALT_SPI                 0x5
-#define GPIO_ALT_SPI3                0x6
-#define GPIO_ALT_USART               0x7
-#define GPIO_ALT_I2C_23              0x9
-#define GPIO_ALT_USB                 0xA
-#define GPIO_ALT_LCD                 0xB
-#define GPIO_ALT_RI                  0xE
-#define GPIO_ALT_EVENTOUT            0xF
+#define STM32_GPIO_MODER(b) REG32((b) + 0x00)
+#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04)
+#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08)
+#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C)
+#define STM32_GPIO_IDR(b) REG16((b) + 0x10)
+#define STM32_GPIO_ODR(b) REG16((b) + 0x14)
+#define STM32_GPIO_BSRR(b) REG32((b) + 0x18)
+#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C)
+#define STM32_GPIO_AFRL(b) REG32((b) + 0x20)
+#define STM32_GPIO_AFRH(b) REG32((b) + 0x24)
+
+#define GPIO_ALT_SYS 0x0
+#define GPIO_ALT_TIM2 0x1
+#define GPIO_ALT_TIM3_4 0x2
+#define GPIO_ALT_TIM9_11 0x3
+#define GPIO_ALT_I2C 0x4
+#define GPIO_ALT_SPI 0x5
+#define GPIO_ALT_SPI3 0x6
+#define GPIO_ALT_USART 0x7
+#define GPIO_ALT_I2C_23 0x9
+#define GPIO_ALT_USB 0xA
+#define GPIO_ALT_LCD 0xB
+#define GPIO_ALT_RI 0xE
+#define GPIO_ALT_EVENTOUT 0xF
 
 /* --- I2C --- */
-#define STM32_I2C_CR1(n)            REG16(stm32_i2c_reg(n, 0x00))
-#define STM32_I2C_CR1_PE	BIT(0)
-#define STM32_I2C_CR1_START	BIT(8)
-#define STM32_I2C_CR1_STOP	BIT(9)
-#define STM32_I2C_CR1_ACK	BIT(10)
-#define STM32_I2C_CR1_POS	BIT(11)
-#define STM32_I2C_CR1_SWRST	BIT(15)
-#define STM32_I2C_CR2(n)            REG16(stm32_i2c_reg(n, 0x04))
-#define STM32_I2C_CR2_ITERREN	BIT(8)
-#define STM32_I2C_CR2_ITEVTEN	BIT(9)
-#define STM32_I2C_CR2_ITBUFEN	BIT(10)
-#define STM32_I2C_CR2_DMAEN	BIT(11)
-#define STM32_I2C_CR2_LAST	BIT(12)
-#define STM32_I2C_OAR1(n)           REG16(stm32_i2c_reg(n, 0x08))
-#define STM32_I2C_OAR1_B14	BIT(14)
-#define STM32_I2C_OAR2(n)           REG16(stm32_i2c_reg(n, 0x0C))
-#define STM32_I2C_OAR2_ENDUAL	BIT(0)
-#define STM32_I2C_DR(n)             REG16(stm32_i2c_reg(n, 0x10))
-#define STM32_I2C_SR1(n)            REG16(stm32_i2c_reg(n, 0x14))
-#define STM32_I2C_SR1_SB	BIT(0)
-#define STM32_I2C_SR1_ADDR	BIT(1)
-#define STM32_I2C_SR1_BTF	BIT(2)
-#define STM32_I2C_SR1_STOPF	BIT(4)
-#define STM32_I2C_SR1_RXNE	BIT(6)
-#define STM32_I2C_SR1_TXE	BIT(7)
-#define STM32_I2C_SR1_BERR	BIT(8)
-#define STM32_I2C_SR1_ARLO	BIT(9)
-#define STM32_I2C_SR1_AF	BIT(10)
-
-#define STM32_I2C_SR2(n)            REG16(stm32_i2c_reg(n, 0x18))
-#define STM32_I2C_SR2_BUSY	BIT(1)
-#define STM32_I2C_SR2_TRA	BIT(2)
-#define STM32_I2C_SR2_DUALF	BIT(7)
-
-#define STM32_I2C_CCR(n)            REG16(stm32_i2c_reg(n, 0x1C))
-#define STM32_I2C_CCR_DUTY	BIT(14)
-#define STM32_I2C_CCR_FM	BIT(15)
-#define STM32_I2C_TRISE(n)          REG16(stm32_i2c_reg(n, 0x20))
-
+#define STM32_I2C_CR1(n) REG16(stm32_i2c_reg(n, 0x00))
+#define STM32_I2C_CR1_PE BIT(0)
+#define STM32_I2C_CR1_START BIT(8)
+#define STM32_I2C_CR1_STOP BIT(9)
+#define STM32_I2C_CR1_ACK BIT(10)
+#define STM32_I2C_CR1_POS BIT(11)
+#define STM32_I2C_CR1_SWRST BIT(15)
+#define STM32_I2C_CR2(n) REG16(stm32_i2c_reg(n, 0x04))
+#define STM32_I2C_CR2_ITERREN BIT(8)
+#define STM32_I2C_CR2_ITEVTEN BIT(9)
+#define STM32_I2C_CR2_ITBUFEN BIT(10)
+#define STM32_I2C_CR2_DMAEN BIT(11)
+#define STM32_I2C_CR2_LAST BIT(12)
+#define STM32_I2C_OAR1(n) REG16(stm32_i2c_reg(n, 0x08))
+#define STM32_I2C_OAR1_B14 BIT(14)
+#define STM32_I2C_OAR2(n) REG16(stm32_i2c_reg(n, 0x0C))
+#define STM32_I2C_OAR2_ENDUAL BIT(0)
+#define STM32_I2C_DR(n) REG16(stm32_i2c_reg(n, 0x10))
+#define STM32_I2C_SR1(n) REG16(stm32_i2c_reg(n, 0x14))
+#define STM32_I2C_SR1_SB BIT(0)
+#define STM32_I2C_SR1_ADDR BIT(1)
+#define STM32_I2C_SR1_BTF BIT(2)
+#define STM32_I2C_SR1_STOPF BIT(4)
+#define STM32_I2C_SR1_RXNE BIT(6)
+#define STM32_I2C_SR1_TXE BIT(7)
+#define STM32_I2C_SR1_BERR BIT(8)
+#define STM32_I2C_SR1_ARLO BIT(9)
+#define STM32_I2C_SR1_AF BIT(10)
+
+#define STM32_I2C_SR2(n) REG16(stm32_i2c_reg(n, 0x18))
+#define STM32_I2C_SR2_BUSY BIT(1)
+#define STM32_I2C_SR2_TRA BIT(2)
+#define STM32_I2C_SR2_DUALF BIT(7)
+
+#define STM32_I2C_CCR(n) REG16(stm32_i2c_reg(n, 0x1C))
+#define STM32_I2C_CCR_DUTY BIT(14)
+#define STM32_I2C_CCR_FM BIT(15)
+#define STM32_I2C_TRISE(n) REG16(stm32_i2c_reg(n, 0x20))
 
 /* --- Power / Reset / Clocks --- */
-#define STM32_PWR_CSR               REG32(STM32_PWR_BASE + 0x04)
-
-
-#define STM32_RCC_CR                REG32(STM32_RCC_BASE + 0x00)
-#define STM32_RCC_CR_HSION		BIT(0)
-#define STM32_RCC_CR_HSIRDY		BIT(1)
-#define STM32_RCC_CR_MSION		BIT(8)
-#define STM32_RCC_CR_MSIRDY		BIT(9)
-#define STM32_RCC_CR_PLLON		BIT(24)
-#define STM32_RCC_CR_PLLRDY		BIT(25)
-#define STM32_RCC_ICSCR             REG32(STM32_RCC_BASE + 0x04)
-#define STM32_RCC_ICSCR_MSIRANGE(n)	((n) << 13)
-#define STM32_RCC_ICSCR_MSIRANGE_1MHZ	STM32_RCC_ICSCR_MSIRANGE(4)
-#define STM32_RCC_ICSCR_MSIRANGE_2MHZ	STM32_RCC_ICSCR_MSIRANGE(5)
-#define STM32_RCC_ICSCR_MSIRANGE_MASK	STM32_RCC_ICSCR_MSIRANGE(7)
-#define STM32_RCC_CFGR              REG32(STM32_RCC_BASE + 0x08)
-#define STM32_RCC_CFGR_SW_MSI		(0 << 0)
-#define STM32_RCC_CFGR_SW_HSI		(1 << 0)
-#define STM32_RCC_CFGR_SW_HSE		(2 << 0)
-#define STM32_RCC_CFGR_SW_PLL		(3 << 0)
-#define STM32_RCC_CFGR_SW_MASK		(3 << 0)
-#define STM32_RCC_CFGR_SWS_MSI		(0 << 2)
-#define STM32_RCC_CFGR_SWS_HSI		(1 << 2)
-#define STM32_RCC_CFGR_SWS_HSE		(2 << 2)
-#define STM32_RCC_CFGR_SWS_PLL		(3 << 2)
-#define STM32_RCC_CFGR_SWS_MASK		(3 << 2)
-#define STM32_RCC_CIR               REG32(STM32_RCC_BASE + 0x0C)
-#define STM32_RCC_AHBRSTR           REG32(STM32_RCC_BASE + 0x10)
-#define STM32_RCC_APB2RSTR          REG32(STM32_RCC_BASE + 0x14)
-#define STM32_RCC_APB1RSTR          REG32(STM32_RCC_BASE + 0x18)
-#define STM32_RCC_AHBENR            REG32(STM32_RCC_BASE + 0x1C)
-#define STM32_RCC_APB2ENR           REG32(STM32_RCC_BASE + 0x20)
-#define STM32_RCC_SYSCFGEN		BIT(0)
-
-#define STM32_RCC_APB1ENR           REG32(STM32_RCC_BASE + 0x24)
-#define STM32_RCC_PWREN                 BIT(28)
-
-#define STM32_RCC_AHBLPENR          REG32(STM32_RCC_BASE + 0x28)
-#define STM32_RCC_APB2LPENR         REG32(STM32_RCC_BASE + 0x2C)
-#define STM32_RCC_APB1LPENR         REG32(STM32_RCC_BASE + 0x30)
-#define STM32_RCC_CSR               REG32(STM32_RCC_BASE + 0x34)
-
-#define STM32_RCC_HB_DMA1		BIT(24)
-#define STM32_RCC_PB2_TIM9		BIT(2)
-#define STM32_RCC_PB2_TIM10		BIT(3)
-#define STM32_RCC_PB2_TIM11		BIT(4)
-#define STM32_RCC_PB1_USB		BIT(23)
-
-#define STM32_SYSCFG_MEMRMP         REG32(STM32_SYSCFG_BASE + 0x00)
-#define STM32_SYSCFG_PMC            REG32(STM32_SYSCFG_BASE + 0x04)
-#define STM32_SYSCFG_EXTICR(n)      REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
-
+#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04)
+
+#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00)
+#define STM32_RCC_CR_HSION BIT(0)
+#define STM32_RCC_CR_HSIRDY BIT(1)
+#define STM32_RCC_CR_MSION BIT(8)
+#define STM32_RCC_CR_MSIRDY BIT(9)
+#define STM32_RCC_CR_PLLON BIT(24)
+#define STM32_RCC_CR_PLLRDY BIT(25)
+#define STM32_RCC_ICSCR REG32(STM32_RCC_BASE + 0x04)
+#define STM32_RCC_ICSCR_MSIRANGE(n) ((n) << 13)
+#define STM32_RCC_ICSCR_MSIRANGE_1MHZ STM32_RCC_ICSCR_MSIRANGE(4)
+#define STM32_RCC_ICSCR_MSIRANGE_2MHZ STM32_RCC_ICSCR_MSIRANGE(5)
+#define STM32_RCC_ICSCR_MSIRANGE_MASK STM32_RCC_ICSCR_MSIRANGE(7)
+#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08)
+#define STM32_RCC_CFGR_SW_MSI (0 << 0)
+#define STM32_RCC_CFGR_SW_HSI (1 << 0)
+#define STM32_RCC_CFGR_SW_HSE (2 << 0)
+#define STM32_RCC_CFGR_SW_PLL (3 << 0)
+#define STM32_RCC_CFGR_SW_MASK (3 << 0)
+#define STM32_RCC_CFGR_SWS_MSI (0 << 2)
+#define STM32_RCC_CFGR_SWS_HSI (1 << 2)
+#define STM32_RCC_CFGR_SWS_HSE (2 << 2)
+#define STM32_RCC_CFGR_SWS_PLL (3 << 2)
+#define STM32_RCC_CFGR_SWS_MASK (3 << 2)
+#define STM32_RCC_CIR REG32(STM32_RCC_BASE + 0x0C)
+#define STM32_RCC_AHBRSTR REG32(STM32_RCC_BASE + 0x10)
+#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x14)
+#define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x18)
+#define STM32_RCC_AHBENR REG32(STM32_RCC_BASE + 0x1C)
+#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x20)
+#define STM32_RCC_SYSCFGEN BIT(0)
+
+#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x24)
+#define STM32_RCC_PWREN BIT(28)
+
+#define STM32_RCC_AHBLPENR REG32(STM32_RCC_BASE + 0x28)
+#define STM32_RCC_APB2LPENR REG32(STM32_RCC_BASE + 0x2C)
+#define STM32_RCC_APB1LPENR REG32(STM32_RCC_BASE + 0x30)
+#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x34)
+
+#define STM32_RCC_HB_DMA1 BIT(24)
+#define STM32_RCC_PB2_TIM9 BIT(2)
+#define STM32_RCC_PB2_TIM10 BIT(3)
+#define STM32_RCC_PB2_TIM11 BIT(4)
+#define STM32_RCC_PB1_USB BIT(23)
+
+#define STM32_SYSCFG_MEMRMP REG32(STM32_SYSCFG_BASE + 0x00)
+#define STM32_SYSCFG_PMC REG32(STM32_SYSCFG_BASE + 0x04)
+#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
 
 /* Peripheral bits for RCC_APB/AHB and DBGMCU regs */
-#define STM32_RCC_PB2_USART1		BIT(14)
+#define STM32_RCC_PB2_USART1 BIT(14)
 
 /* Reset causes definitions */
 /* Reset causes in RCC CSR register */
 #define STM32_RCC_RESET_CAUSE STM32_RCC_CSR
-#define  RESET_CAUSE_WDG                0x60000000
-#define  RESET_CAUSE_SFT                0x10000000
-#define  RESET_CAUSE_POR                0x08000000
-#define  RESET_CAUSE_PIN                0x04000000
-#define  RESET_CAUSE_OTHER              0xfe000000
-#define  RESET_CAUSE_RMVF               0x01000000
+#define RESET_CAUSE_WDG 0x60000000
+#define RESET_CAUSE_SFT 0x10000000
+#define RESET_CAUSE_POR 0x08000000
+#define RESET_CAUSE_PIN 0x04000000
+#define RESET_CAUSE_OTHER 0xfe000000
+#define RESET_CAUSE_RMVF 0x01000000
 /* Power cause in PWR CSR register */
 #define STM32_PWR_RESET_CAUSE STM32_PWR_CSR
 #define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR
-#define  RESET_CAUSE_SBF                0x00000002
-#define  RESET_CAUSE_SBF_CLR            0x00000004
+#define RESET_CAUSE_SBF 0x00000002
+#define RESET_CAUSE_SBF_CLR 0x00000004
 
 /* --- Watchdogs --- */
 
 /* --- Real-Time Clock --- */
-#define STM32_RTC_TR                REG32(STM32_RTC_BASE + 0x00)
-#define STM32_RTC_DR                REG32(STM32_RTC_BASE + 0x04)
-#define STM32_RTC_CR                REG32(STM32_RTC_BASE + 0x08)
-#define STM32_RTC_CR_BYPSHAD        BIT(5)
-#define STM32_RTC_CR_ALRAE          BIT(8)
-#define STM32_RTC_CR_ALRAIE         BIT(12)
-#define STM32_RTC_ISR               REG32(STM32_RTC_BASE + 0x0C)
-#define STM32_RTC_ISR_ALRAWF        BIT(0)
-#define STM32_RTC_ISR_RSF           BIT(5)
-#define STM32_RTC_ISR_INITF         BIT(6)
-#define STM32_RTC_ISR_INIT          BIT(7)
-#define STM32_RTC_ISR_ALRAF         BIT(8)
-#define STM32_RTC_PRER              REG32(STM32_RTC_BASE + 0x10)
-#define STM32_RTC_PRER_A_MASK       (0x7f << 16)
-#define STM32_RTC_PRER_S_MASK       (0x7fff << 0)
-#define STM32_RTC_WUTR              REG32(STM32_RTC_BASE + 0x14)
-#define STM32_RTC_CALIBR            REG32(STM32_RTC_BASE + 0x18)
-#define STM32_RTC_ALRMAR            REG32(STM32_RTC_BASE + 0x1C)
-#define STM32_RTC_ALRMBR            REG32(STM32_RTC_BASE + 0x20)
-#define STM32_RTC_WPR               REG32(STM32_RTC_BASE + 0x24)
-#define STM32_RTC_SSR               REG32(STM32_RTC_BASE + 0x28)
-#define STM32_RTC_TSTR              REG32(STM32_RTC_BASE + 0x30)
-#define STM32_RTC_TSDR              REG32(STM32_RTC_BASE + 0x34)
-#define STM32_RTC_TAFCR             REG32(STM32_RTC_BASE + 0x40)
-#define STM32_RTC_ALRMASSR          REG32(STM32_RTC_BASE + 0x44)
-#define STM32_RTC_BACKUP(n)         REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
-
-#define STM32_BKP_DATA(n)           STM32_RTC_BACKUP(n)
-#define STM32_BKP_BYTES             80
+#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00)
+#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04)
+#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08)
+#define STM32_RTC_CR_BYPSHAD BIT(5)
+#define STM32_RTC_CR_ALRAE BIT(8)
+#define STM32_RTC_CR_ALRAIE BIT(12)
+#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C)
+#define STM32_RTC_ISR_ALRAWF BIT(0)
+#define STM32_RTC_ISR_RSF BIT(5)
+#define STM32_RTC_ISR_INITF BIT(6)
+#define STM32_RTC_ISR_INIT BIT(7)
+#define STM32_RTC_ISR_ALRAF BIT(8)
+#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10)
+#define STM32_RTC_PRER_A_MASK (0x7f << 16)
+#define STM32_RTC_PRER_S_MASK (0x7fff << 0)
+#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14)
+#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18)
+#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C)
+#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20)
+#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24)
+#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28)
+#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30)
+#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34)
+#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40)
+#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44)
+#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
+
+#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n)
+#define STM32_BKP_BYTES 80
 
 /* --- SPI --- */
 
@@ -431,8 +423,8 @@ struct stm32_spi_regs {
 	unsigned crcpr;
 	unsigned rxcrcr;
 	unsigned txcrcr;
-	unsigned i2scfgr;	/* STM32L only */
-	unsigned i2spr;		/* STM32L only */
+	unsigned i2scfgr; /* STM32L only */
+	unsigned i2spr; /* STM32L only */
 };
 /* Must be volatile, or compiler optimizes out repeated accesses */
 typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
@@ -442,146 +434,144 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
 #define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE)
 #define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE)
 
-#define STM32_SPI_CR1_BIDIMODE		BIT(15)
-#define STM32_SPI_CR1_BIDIOE		BIT(14)
-#define STM32_SPI_CR1_CRCEN		BIT(13)
-#define STM32_SPI_CR1_SSM		BIT(9)
-#define STM32_SPI_CR1_SSI		BIT(8)
-#define STM32_SPI_CR1_LSBFIRST		BIT(7)
-#define STM32_SPI_CR1_SPE		BIT(6)
-#define STM32_SPI_CR1_BR_DIV64R		(5 << 3)
-#define STM32_SPI_CR1_BR_DIV4R		BIT(3)
-#define STM32_SPI_CR1_MSTR		BIT(2)
-#define STM32_SPI_CR1_CPOL		BIT(1)
-#define STM32_SPI_CR1_CPHA		BIT(0)
-#define STM32_SPI_CR2_FRXTH		BIT(12)
-#define STM32_SPI_CR2_DATASIZE(n)	(((n) - 1) << 8)
-#define STM32_SPI_CR2_TXEIE		BIT(7)
-#define STM32_SPI_CR2_RXNEIE		BIT(6)
-#define STM32_SPI_CR2_NSSP		BIT(3)
-#define STM32_SPI_CR2_SSOE		BIT(2)
-#define STM32_SPI_CR2_TXDMAEN		BIT(1)
-#define STM32_SPI_CR2_RXDMAEN		BIT(0)
-
-#define STM32_SPI_SR_RXNE		BIT(0)
-#define STM32_SPI_SR_TXE		BIT(1)
-#define STM32_SPI_SR_CRCERR		BIT(4)
-#define STM32_SPI_SR_BSY		BIT(7)
-#define STM32_SPI_SR_FRLVL		(3 << 9)
-#define STM32_SPI_SR_FTLVL		(3 << 11)
+#define STM32_SPI_CR1_BIDIMODE BIT(15)
+#define STM32_SPI_CR1_BIDIOE BIT(14)
+#define STM32_SPI_CR1_CRCEN BIT(13)
+#define STM32_SPI_CR1_SSM BIT(9)
+#define STM32_SPI_CR1_SSI BIT(8)
+#define STM32_SPI_CR1_LSBFIRST BIT(7)
+#define STM32_SPI_CR1_SPE BIT(6)
+#define STM32_SPI_CR1_BR_DIV64R (5 << 3)
+#define STM32_SPI_CR1_BR_DIV4R BIT(3)
+#define STM32_SPI_CR1_MSTR BIT(2)
+#define STM32_SPI_CR1_CPOL BIT(1)
+#define STM32_SPI_CR1_CPHA BIT(0)
+#define STM32_SPI_CR2_FRXTH BIT(12)
+#define STM32_SPI_CR2_DATASIZE(n) (((n)-1) << 8)
+#define STM32_SPI_CR2_TXEIE BIT(7)
+#define STM32_SPI_CR2_RXNEIE BIT(6)
+#define STM32_SPI_CR2_NSSP BIT(3)
+#define STM32_SPI_CR2_SSOE BIT(2)
+#define STM32_SPI_CR2_TXDMAEN BIT(1)
+#define STM32_SPI_CR2_RXDMAEN BIT(0)
+
+#define STM32_SPI_SR_RXNE BIT(0)
+#define STM32_SPI_SR_TXE BIT(1)
+#define STM32_SPI_SR_CRCERR BIT(4)
+#define STM32_SPI_SR_BSY BIT(7)
+#define STM32_SPI_SR_FRLVL (3 << 9)
+#define STM32_SPI_SR_FTLVL (3 << 11)
 /* --- Debug --- */
-#define STM32_DBGMCU_APB1FZ         REG32(STM32_DBGMCU_BASE + 0x08)
-#define STM32_DBGMCU_APB2FZ         REG32(STM32_DBGMCU_BASE + 0x0C)
+#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08)
+#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C)
 
 /* --- Flash --- */
-#define STM32_FLASH_ACR             REG32(STM32_FLASH_REGS_BASE + 0x00)
-#define STM32_FLASH_ACR_LATENCY		BIT(0)
-#define STM32_FLASH_ACR_PRFTEN		BIT(1)
-#define STM32_FLASH_ACR_ACC64		BIT(2)
-#define STM32_FLASH_PECR            REG32(STM32_FLASH_REGS_BASE + 0x04)
-#define STM32_FLASH_PECR_PE_LOCK	BIT(0)
-#define STM32_FLASH_PECR_PRG_LOCK	BIT(1)
-#define STM32_FLASH_PECR_OPT_LOCK	BIT(2)
-#define STM32_FLASH_PECR_PROG		BIT(3)
-#define STM32_FLASH_PECR_ERASE		BIT(9)
-#define STM32_FLASH_PECR_FPRG		BIT(10)
-#define STM32_FLASH_PECR_OBL_LAUNCH	BIT(18)
-#define STM32_FLASH_PDKEYR          REG32(STM32_FLASH_REGS_BASE + 0x08)
-#define STM32_FLASH_PEKEYR          REG32(STM32_FLASH_REGS_BASE + 0x0c)
-#define STM32_FLASH_PEKEYR_KEY1		0x89ABCDEF
-#define STM32_FLASH_PEKEYR_KEY2		0x02030405
-#define STM32_FLASH_PRGKEYR         REG32(STM32_FLASH_REGS_BASE + 0x10)
-#define STM32_FLASH_PRGKEYR_KEY1	0x8C9DAEBF
-#define STM32_FLASH_PRGKEYR_KEY2	0x13141516
-#define STM32_FLASH_OPTKEYR         REG32(STM32_FLASH_REGS_BASE + 0x14)
-#define STM32_FLASH_OPTKEYR_KEY1	0xFBEAD9C8
-#define STM32_FLASH_OPTKEYR_KEY2	0x24252627
-#define STM32_FLASH_SR              REG32(STM32_FLASH_REGS_BASE + 0x18)
-#define STM32_FLASH_OBR             REG32(STM32_FLASH_REGS_BASE + 0x1c)
-#define STM32_FLASH_WRPR            REG32(STM32_FLASH_REGS_BASE + 0x20)
-
-#define STM32_OPTB_RDP                  0x00
-#define STM32_OPTB_USER                 0x04
-#define STM32_OPTB_WRP1L                0x08
-#define STM32_OPTB_WRP1H                0x0c
-#define STM32_OPTB_WRP2L                0x10
-#define STM32_OPTB_WRP2H                0x14
-#define STM32_OPTB_WRP3L                0x18
-#define STM32_OPTB_WRP3H                0x1c
+#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00)
+#define STM32_FLASH_ACR_LATENCY BIT(0)
+#define STM32_FLASH_ACR_PRFTEN BIT(1)
+#define STM32_FLASH_ACR_ACC64 BIT(2)
+#define STM32_FLASH_PECR REG32(STM32_FLASH_REGS_BASE + 0x04)
+#define STM32_FLASH_PECR_PE_LOCK BIT(0)
+#define STM32_FLASH_PECR_PRG_LOCK BIT(1)
+#define STM32_FLASH_PECR_OPT_LOCK BIT(2)
+#define STM32_FLASH_PECR_PROG BIT(3)
+#define STM32_FLASH_PECR_ERASE BIT(9)
+#define STM32_FLASH_PECR_FPRG BIT(10)
+#define STM32_FLASH_PECR_OBL_LAUNCH BIT(18)
+#define STM32_FLASH_PDKEYR REG32(STM32_FLASH_REGS_BASE + 0x08)
+#define STM32_FLASH_PEKEYR REG32(STM32_FLASH_REGS_BASE + 0x0c)
+#define STM32_FLASH_PEKEYR_KEY1 0x89ABCDEF
+#define STM32_FLASH_PEKEYR_KEY2 0x02030405
+#define STM32_FLASH_PRGKEYR REG32(STM32_FLASH_REGS_BASE + 0x10)
+#define STM32_FLASH_PRGKEYR_KEY1 0x8C9DAEBF
+#define STM32_FLASH_PRGKEYR_KEY2 0x13141516
+#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x14)
+#define STM32_FLASH_OPTKEYR_KEY1 0xFBEAD9C8
+#define STM32_FLASH_OPTKEYR_KEY2 0x24252627
+#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x18)
+#define STM32_FLASH_OBR REG32(STM32_FLASH_REGS_BASE + 0x1c)
+#define STM32_FLASH_WRPR REG32(STM32_FLASH_REGS_BASE + 0x20)
+
+#define STM32_OPTB_RDP 0x00
+#define STM32_OPTB_USER 0x04
+#define STM32_OPTB_WRP1L 0x08
+#define STM32_OPTB_WRP1H 0x0c
+#define STM32_OPTB_WRP2L 0x10
+#define STM32_OPTB_WRP2H 0x14
+#define STM32_OPTB_WRP3L 0x18
+#define STM32_OPTB_WRP3H 0x1c
 
 /* --- External Interrupts --- */
-#define STM32_EXTI_IMR              REG32(STM32_EXTI_BASE + 0x00)
-#define STM32_EXTI_EMR              REG32(STM32_EXTI_BASE + 0x04)
-#define STM32_EXTI_RTSR             REG32(STM32_EXTI_BASE + 0x08)
-#define STM32_EXTI_FTSR             REG32(STM32_EXTI_BASE + 0x0c)
-#define STM32_EXTI_SWIER            REG32(STM32_EXTI_BASE + 0x10)
-#define STM32_EXTI_PR               REG32(STM32_EXTI_BASE + 0x14)
-
+#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00)
+#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04)
+#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08)
+#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c)
+#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10)
+#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14)
 
 /* --- ADC --- */
-#define STM32_ADC_SR               REG32(STM32_ADC1_BASE + 0x00)
-#define STM32_ADC_CR1              REG32(STM32_ADC1_BASE + 0x04)
-#define STM32_ADC_CR2              REG32(STM32_ADC1_BASE + 0x08)
-#define STM32_ADC_SMPR1            REG32(STM32_ADC1_BASE + 0x0C)
-#define STM32_ADC_SMPR2            REG32(STM32_ADC1_BASE + 0x10)
-#define STM32_ADC_SMPR3            REG32(STM32_ADC1_BASE + 0x14)
-#define STM32_ADC_JOFR1            REG32(STM32_ADC1_BASE + 0x18)
-#define STM32_ADC_JOFR2            REG32(STM32_ADC1_BASE + 0x1C)
-#define STM32_ADC_JOFR3            REG32(STM32_ADC1_BASE + 0x20)
-#define STM32_ADC_JOFR4            REG32(STM32_ADC1_BASE + 0x24)
-#define STM32_ADC_HTR              REG32(STM32_ADC1_BASE + 0x28)
-#define STM32_ADC_LTR              REG32(STM32_ADC1_BASE + 0x2C)
-#define STM32_ADC_SQR(n)           REG32(STM32_ADC1_BASE + 0x2C + (n) * 4)
-#define STM32_ADC_SQR1             REG32(STM32_ADC1_BASE + 0x30)
-#define STM32_ADC_SQR2             REG32(STM32_ADC1_BASE + 0x34)
-#define STM32_ADC_SQR3             REG32(STM32_ADC1_BASE + 0x38)
-#define STM32_ADC_SQR4             REG32(STM32_ADC1_BASE + 0x3C)
-#define STM32_ADC_SQR5             REG32(STM32_ADC1_BASE + 0x40)
-#define STM32_ADC_JSQR             REG32(STM32_ADC1_BASE + 0x44)
-#define STM32_ADC_JDR1             REG32(STM32_ADC1_BASE + 0x48)
-#define STM32_ADC_JDR2             REG32(STM32_ADC1_BASE + 0x4C)
-#define STM32_ADC_JDR3             REG32(STM32_ADC1_BASE + 0x50)
-#define STM32_ADC_JDR3             REG32(STM32_ADC1_BASE + 0x50)
-#define STM32_ADC_JDR4             REG32(STM32_ADC1_BASE + 0x54)
-#define STM32_ADC_DR               REG32(STM32_ADC1_BASE + 0x58)
-#define STM32_ADC_SMPR0            REG32(STM32_ADC1_BASE + 0x5C)
-
-#define STM32_ADC_CCR              REG32(STM32_ADC_BASE + 0x04)
+#define STM32_ADC_SR REG32(STM32_ADC1_BASE + 0x00)
+#define STM32_ADC_CR1 REG32(STM32_ADC1_BASE + 0x04)
+#define STM32_ADC_CR2 REG32(STM32_ADC1_BASE + 0x08)
+#define STM32_ADC_SMPR1 REG32(STM32_ADC1_BASE + 0x0C)
+#define STM32_ADC_SMPR2 REG32(STM32_ADC1_BASE + 0x10)
+#define STM32_ADC_SMPR3 REG32(STM32_ADC1_BASE + 0x14)
+#define STM32_ADC_JOFR1 REG32(STM32_ADC1_BASE + 0x18)
+#define STM32_ADC_JOFR2 REG32(STM32_ADC1_BASE + 0x1C)
+#define STM32_ADC_JOFR3 REG32(STM32_ADC1_BASE + 0x20)
+#define STM32_ADC_JOFR4 REG32(STM32_ADC1_BASE + 0x24)
+#define STM32_ADC_HTR REG32(STM32_ADC1_BASE + 0x28)
+#define STM32_ADC_LTR REG32(STM32_ADC1_BASE + 0x2C)
+#define STM32_ADC_SQR(n) REG32(STM32_ADC1_BASE + 0x2C + (n)*4)
+#define STM32_ADC_SQR1 REG32(STM32_ADC1_BASE + 0x30)
+#define STM32_ADC_SQR2 REG32(STM32_ADC1_BASE + 0x34)
+#define STM32_ADC_SQR3 REG32(STM32_ADC1_BASE + 0x38)
+#define STM32_ADC_SQR4 REG32(STM32_ADC1_BASE + 0x3C)
+#define STM32_ADC_SQR5 REG32(STM32_ADC1_BASE + 0x40)
+#define STM32_ADC_JSQR REG32(STM32_ADC1_BASE + 0x44)
+#define STM32_ADC_JDR1 REG32(STM32_ADC1_BASE + 0x48)
+#define STM32_ADC_JDR2 REG32(STM32_ADC1_BASE + 0x4C)
+#define STM32_ADC_JDR3 REG32(STM32_ADC1_BASE + 0x50)
+#define STM32_ADC_JDR3 REG32(STM32_ADC1_BASE + 0x50)
+#define STM32_ADC_JDR4 REG32(STM32_ADC1_BASE + 0x54)
+#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x58)
+#define STM32_ADC_SMPR0 REG32(STM32_ADC1_BASE + 0x5C)
+
+#define STM32_ADC_CCR REG32(STM32_ADC_BASE + 0x04)
 
 /* --- Comparators --- */
-#define STM32_COMP_CSR              REG32(STM32_COMP_BASE + 0x00)
-
-#define STM32_COMP_OUTSEL_TIM2_IC4  (0 << 21)
-#define STM32_COMP_OUTSEL_TIM2_OCR  (1 << 21)
-#define STM32_COMP_OUTSEL_TIM3_IC4  (2 << 21)
-#define STM32_COMP_OUTSEL_TIM3_OCR  (3 << 21)
-#define STM32_COMP_OUTSEL_TIM4_IC4  (4 << 21)
-#define STM32_COMP_OUTSEL_TIM4_OCR  (5 << 21)
+#define STM32_COMP_CSR REG32(STM32_COMP_BASE + 0x00)
+
+#define STM32_COMP_OUTSEL_TIM2_IC4 (0 << 21)
+#define STM32_COMP_OUTSEL_TIM2_OCR (1 << 21)
+#define STM32_COMP_OUTSEL_TIM3_IC4 (2 << 21)
+#define STM32_COMP_OUTSEL_TIM3_OCR (3 << 21)
+#define STM32_COMP_OUTSEL_TIM4_IC4 (4 << 21)
+#define STM32_COMP_OUTSEL_TIM4_OCR (5 << 21)
 #define STM32_COMP_OUTSEL_TIM10_IC1 (6 << 21)
-#define STM32_COMP_OUTSEL_NONE      (7 << 21)
-
-#define STM32_COMP_INSEL_NONE       (0 << 18)
-#define STM32_COMP_INSEL_PB3        (1 << 18)
-#define STM32_COMP_INSEL_VREF       (2 << 18)
-#define STM32_COMP_INSEL_VREF34     (3 << 18)
-#define STM32_COMP_INSEL_VREF12     (4 << 18)
-#define STM32_COMP_INSEL_VREF14     (5 << 18)
-#define STM32_COMP_INSEL_DAC_OUT1   (6 << 18)
-#define STM32_COMP_INSEL_DAC_OUT2   (7 << 18)
-
-#define STM32_COMP_WNDWE            BIT(17)
-#define STM32_COMP_VREFOUTEN        BIT(16)
-#define STM32_COMP_CMP2OUT          BIT(13)
-#define STM32_COMP_SPEED_FAST       BIT(12)
-
-#define STM32_COMP_CMP1OUT          BIT(7)
-#define STM32_COMP_CMP1EN           BIT(4)
-
-#define STM32_COMP_400KPD           BIT(3)
-#define STM32_COMP_10KPD            BIT(2)
-#define STM32_COMP_400KPU           BIT(1)
-#define STM32_COMP_10KPU            BIT(0)
-
+#define STM32_COMP_OUTSEL_NONE (7 << 21)
+
+#define STM32_COMP_INSEL_NONE (0 << 18)
+#define STM32_COMP_INSEL_PB3 (1 << 18)
+#define STM32_COMP_INSEL_VREF (2 << 18)
+#define STM32_COMP_INSEL_VREF34 (3 << 18)
+#define STM32_COMP_INSEL_VREF12 (4 << 18)
+#define STM32_COMP_INSEL_VREF14 (5 << 18)
+#define STM32_COMP_INSEL_DAC_OUT1 (6 << 18)
+#define STM32_COMP_INSEL_DAC_OUT2 (7 << 18)
+
+#define STM32_COMP_WNDWE BIT(17)
+#define STM32_COMP_VREFOUTEN BIT(16)
+#define STM32_COMP_CMP2OUT BIT(13)
+#define STM32_COMP_SPEED_FAST BIT(12)
+
+#define STM32_COMP_CMP1OUT BIT(7)
+#define STM32_COMP_CMP1EN BIT(4)
+
+#define STM32_COMP_400KPD BIT(3)
+#define STM32_COMP_10KPD BIT(2)
+#define STM32_COMP_400KPU BIT(1)
+#define STM32_COMP_10KPU BIT(0)
 
 /* --- DMA --- */
 
@@ -642,11 +632,11 @@ enum dma_channel {
 
 /* Registers for a single channel of the DMA controller */
 struct stm32_dma_chan {
-	uint32_t	ccr;		/* Control */
-	uint32_t	cndtr;		/* Number of data to transfer */
-	uint32_t	cpar;		/* Peripheral address */
-	uint32_t	cmar;		/* Memory address */
-	uint32_t	reserved;
+	uint32_t ccr; /* Control */
+	uint32_t cndtr; /* Number of data to transfer */
+	uint32_t cpar; /* Peripheral address */
+	uint32_t cmar; /* Memory address */
+	uint32_t reserved;
 };
 
 /* Always use stm32_dma_chan_t so volatile keyword is included! */
@@ -657,8 +647,8 @@ typedef stm32_dma_chan_t dma_chan_t;
 
 /* Registers for the DMA controller */
 struct stm32_dma_regs {
-	uint32_t	isr;
-	uint32_t	ifcr;
+	uint32_t isr;
+	uint32_t ifcr;
 	stm32_dma_chan_t chan[STM32_DMAC_COUNT];
 };
 
@@ -667,205 +657,124 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
 
 #define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE)
 
-
-#define STM32_DMA_CCR_CHANNEL(channel)		 (0)
+#define STM32_DMA_CCR_CHANNEL(channel) (0)
 
 #define STM32_DMA_REGS(channel) STM32_DMA1_REGS
 
 /* Bits for DMA controller regs (isr and ifcr) */
-#define STM32_DMA_CH_OFFSET(channel)   (4 * ((channel) % STM32_DMAC_PER_CTLR))
+#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR))
 #define STM32_DMA_ISR_MASK(channel, mask) \
 	((mask) << STM32_DMA_CH_OFFSET(channel))
-#define STM32_DMA_ISR_GIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(0))
-#define STM32_DMA_ISR_TCIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(1))
-#define STM32_DMA_ISR_HTIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(2))
-#define STM32_DMA_ISR_TEIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(3))
-#define STM32_DMA_ISR_ALL(channel)	STM32_DMA_ISR_MASK(channel, 0x0f)
-
-#define STM32_DMA_GIF                   BIT(0)
-#define STM32_DMA_TCIF                  BIT(1)
-#define STM32_DMA_HTIF                  BIT(2)
-#define STM32_DMA_TEIF                  BIT(3)
-#define STM32_DMA_ALL                   0xf
-
-#define STM32_DMA_GET_ISR(channel)      \
-	((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_ISR(channel, val) \
-	(STM32_DMA_REGS(channel)->isr = \
-	((STM32_DMA_REGS(channel)->isr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-#define STM32_DMA_GET_IFCR(channel)      \
-	((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_IFCR(channel, val) \
-	(STM32_DMA_REGS(channel)->ifcr = \
-	((STM32_DMA_REGS(channel)->ifcr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-
+#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0))
+#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1))
+#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2))
+#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3))
+#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f)
+
+#define STM32_DMA_GIF BIT(0)
+#define STM32_DMA_TCIF BIT(1)
+#define STM32_DMA_HTIF BIT(2)
+#define STM32_DMA_TEIF BIT(3)
+#define STM32_DMA_ALL 0xf
+
+#define STM32_DMA_GET_ISR(channel)                                        \
+	((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) & \
+	 STM32_DMA_ALL)
+#define STM32_DMA_SET_ISR(channel, val)                                \
+	(STM32_DMA_REGS(channel)->isr =                                \
+		 ((STM32_DMA_REGS(channel)->isr &                      \
+		   ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
+		  (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
+#define STM32_DMA_GET_IFCR(channel)                                        \
+	((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) & \
+	 STM32_DMA_ALL)
+#define STM32_DMA_SET_IFCR(channel, val)                               \
+	(STM32_DMA_REGS(channel)->ifcr =                               \
+		 ((STM32_DMA_REGS(channel)->ifcr &                     \
+		   ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
+		  (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
 
 /* Bits for DMA channel regs */
-#define STM32_DMA_CCR_EN		BIT(0)
-#define STM32_DMA_CCR_TCIE		BIT(1)
-#define STM32_DMA_CCR_HTIE		BIT(2)
-#define STM32_DMA_CCR_TEIE		BIT(3)
-#define STM32_DMA_CCR_DIR		BIT(4)
-#define STM32_DMA_CCR_CIRC		BIT(5)
-#define STM32_DMA_CCR_PINC		BIT(6)
-#define STM32_DMA_CCR_MINC		BIT(7)
-#define STM32_DMA_CCR_PSIZE_8_BIT	(0 << 8)
-#define STM32_DMA_CCR_PSIZE_16_BIT	(1 << 8)
-#define STM32_DMA_CCR_PSIZE_32_BIT	(2 << 8)
-#define STM32_DMA_CCR_MSIZE_8_BIT	(0 << 10)
-#define STM32_DMA_CCR_MSIZE_16_BIT	(1 << 10)
-#define STM32_DMA_CCR_MSIZE_32_BIT	(2 << 10)
-#define STM32_DMA_CCR_PL_LOW		(0 << 12)
-#define STM32_DMA_CCR_PL_MEDIUM		(1 << 12)
-#define STM32_DMA_CCR_PL_HIGH		(2 << 12)
-#define STM32_DMA_CCR_PL_VERY_HIGH	(3 << 12)
-#define STM32_DMA_CCR_MEM2MEM		BIT(14)
-
+#define STM32_DMA_CCR_EN BIT(0)
+#define STM32_DMA_CCR_TCIE BIT(1)
+#define STM32_DMA_CCR_HTIE BIT(2)
+#define STM32_DMA_CCR_TEIE BIT(3)
+#define STM32_DMA_CCR_DIR BIT(4)
+#define STM32_DMA_CCR_CIRC BIT(5)
+#define STM32_DMA_CCR_PINC BIT(6)
+#define STM32_DMA_CCR_MINC BIT(7)
+#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8)
+#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8)
+#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8)
+#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10)
+#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10)
+#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10)
+#define STM32_DMA_CCR_PL_LOW (0 << 12)
+#define STM32_DMA_CCR_PL_MEDIUM (1 << 12)
+#define STM32_DMA_CCR_PL_HIGH (2 << 12)
+#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12)
+#define STM32_DMA_CCR_MEM2MEM BIT(14)
 
 /* --- CRC --- */
-#define STM32_CRC_DR                REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR32              REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR16              REG16(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR8               REG8(STM32_CRC_BASE + 0x0)
-
-#define STM32_CRC_IDR               REG32(STM32_CRC_BASE + 0x4)
-#define STM32_CRC_CR                REG32(STM32_CRC_BASE + 0x8)
-#define STM32_CRC_INIT              REG32(STM32_CRC_BASE + 0x10)
-#define STM32_CRC_POL               REG32(STM32_CRC_BASE + 0x14)
-
-#define STM32_CRC_CR_RESET          BIT(0)
-#define STM32_CRC_CR_POLYSIZE_32    (0 << 3)
-#define STM32_CRC_CR_POLYSIZE_16    (1 << 3)
-#define STM32_CRC_CR_POLYSIZE_8     (2 << 3)
-#define STM32_CRC_CR_POLYSIZE_7     (3 << 3)
-#define STM32_CRC_CR_REV_IN_BYTE    (1 << 5)
-#define STM32_CRC_CR_REV_IN_HWORD   (2 << 5)
-#define STM32_CRC_CR_REV_IN_WORD    (3 << 5)
-#define STM32_CRC_CR_REV_OUT        BIT(7)
+#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0)
+
+#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4)
+#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8)
+#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10)
+#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14)
+
+#define STM32_CRC_CR_RESET BIT(0)
+#define STM32_CRC_CR_POLYSIZE_32 (0 << 3)
+#define STM32_CRC_CR_POLYSIZE_16 (1 << 3)
+#define STM32_CRC_CR_POLYSIZE_8 (2 << 3)
+#define STM32_CRC_CR_POLYSIZE_7 (3 << 3)
+#define STM32_CRC_CR_REV_IN_BYTE (1 << 5)
+#define STM32_CRC_CR_REV_IN_HWORD (2 << 5)
+#define STM32_CRC_CR_REV_IN_WORD (3 << 5)
+#define STM32_CRC_CR_REV_OUT BIT(7)
 
 /* --- PMSE --- */
-#define STM32_PMSE_ARCR             REG32(STM32_PMSE_BASE + 0x0)
-#define STM32_PMSE_ACCR             REG32(STM32_PMSE_BASE + 0x4)
-#define STM32_PMSE_CR               REG32(STM32_PMSE_BASE + 0x8)
-#define STM32_PMSE_CRTDR            REG32(STM32_PMSE_BASE + 0x14)
-#define STM32_PMSE_IER              REG32(STM32_PMSE_BASE + 0x18)
-#define STM32_PMSE_SR               REG32(STM32_PMSE_BASE + 0x1c)
-#define STM32_PMSE_IFCR             REG32(STM32_PMSE_BASE + 0x20)
-#define STM32_PMSE_PxPMR(x)         REG32(STM32_PMSE_BASE + 0x2c + (x) * 4)
-#define STM32_PMSE_PAPMR            REG32(STM32_PMSE_BASE + 0x2c)
-#define STM32_PMSE_PBPMR            REG32(STM32_PMSE_BASE + 0x30)
-#define STM32_PMSE_PCPMR            REG32(STM32_PMSE_BASE + 0x34)
-#define STM32_PMSE_PDPMR            REG32(STM32_PMSE_BASE + 0x38)
-#define STM32_PMSE_PEPMR            REG32(STM32_PMSE_BASE + 0x3c)
-#define STM32_PMSE_PFPMR            REG32(STM32_PMSE_BASE + 0x40)
-#define STM32_PMSE_PGPMR            REG32(STM32_PMSE_BASE + 0x44)
-#define STM32_PMSE_PHPMR            REG32(STM32_PMSE_BASE + 0x48)
-#define STM32_PMSE_PIPMR            REG32(STM32_PMSE_BASE + 0x4c)
-#define STM32_PMSE_MRCR             REG32(STM32_PMSE_BASE + 0x100)
-#define STM32_PMSE_MCCR             REG32(STM32_PMSE_BASE + 0x104)
-
-/* --- USB --- */
-#define STM32_USB_EP(n)            REG16(STM32_USB_FS_BASE + (n) * 4)
-
-#define STM32_USB_CNTR             REG16(STM32_USB_FS_BASE + 0x40)
-
-#define STM32_USB_CNTR_FRES	    BIT(0)
-#define STM32_USB_CNTR_PDWN	    BIT(1)
-#define STM32_USB_CNTR_LP_MODE	    BIT(2)
-#define STM32_USB_CNTR_FSUSP	    BIT(3)
-#define STM32_USB_CNTR_RESUME	    BIT(4)
-#define STM32_USB_CNTR_L1RESUME	    BIT(5)
-#define STM32_USB_CNTR_L1REQM	    BIT(7)
-#define STM32_USB_CNTR_ESOFM	    BIT(8)
-#define STM32_USB_CNTR_SOFM	    BIT(9)
-#define STM32_USB_CNTR_RESETM	    BIT(10)
-#define STM32_USB_CNTR_SUSPM	    BIT(11)
-#define STM32_USB_CNTR_WKUPM	    BIT(12)
-#define STM32_USB_CNTR_ERRM	    BIT(13)
-#define STM32_USB_CNTR_PMAOVRM	    BIT(14)
-#define STM32_USB_CNTR_CTRM	    BIT(15)
-
-#define STM32_USB_ISTR             REG16(STM32_USB_FS_BASE + 0x44)
-
-#define STM32_USB_ISTR_EP_ID_MASK   (0x000f)
-#define STM32_USB_ISTR_DIR	    BIT(4)
-#define STM32_USB_ISTR_L1REQ	    BIT(7)
-#define STM32_USB_ISTR_ESOF	    BIT(8)
-#define STM32_USB_ISTR_SOF	    BIT(9)
-#define STM32_USB_ISTR_RESET	    BIT(10)
-#define STM32_USB_ISTR_SUSP	    BIT(11)
-#define STM32_USB_ISTR_WKUP	    BIT(12)
-#define STM32_USB_ISTR_ERR	    BIT(13)
-#define STM32_USB_ISTR_PMAOVR	    BIT(14)
-#define STM32_USB_ISTR_CTR	    BIT(15)
-
-#define STM32_USB_FNR              REG16(STM32_USB_FS_BASE + 0x48)
-
-#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14)
-#define STM32_USB_FNR_RXDP_RXDM_MASK  (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT)
-
-#define STM32_USB_DADDR            REG16(STM32_USB_FS_BASE + 0x4C)
-#define STM32_USB_BTABLE           REG16(STM32_USB_FS_BASE + 0x50)
-#define STM32_USB_LPMCSR           REG16(STM32_USB_FS_BASE + 0x54)
-#define STM32_USB_BCDR             REG16(STM32_USB_FS_BASE + 0x58)
-
-#define STM32_USB_BCDR_BCDEN	    BIT(0)
-#define STM32_USB_BCDR_DCDEN	    BIT(1)
-#define STM32_USB_BCDR_PDEN	    BIT(2)
-#define STM32_USB_BCDR_SDEN	    BIT(3)
-#define STM32_USB_BCDR_DCDET	    BIT(4)
-#define STM32_USB_BCDR_PDET	    BIT(5)
-#define STM32_USB_BCDR_SDET	    BIT(6)
-#define STM32_USB_BCDR_PS2DET	    BIT(7)
-
-#define EP_MASK     0x0F0F
-#define EP_TX_DTOG  0x0040
-#define EP_TX_MASK  0x0030
-#define EP_TX_VALID 0x0030
-#define EP_TX_NAK   0x0020
-#define EP_TX_STALL 0x0010
-#define EP_TX_DISAB 0x0000
-#define EP_RX_DTOG  0x4000
-#define EP_RX_MASK  0x3000
-#define EP_RX_VALID 0x3000
-#define EP_RX_NAK   0x2000
-#define EP_RX_STALL 0x1000
-#define EP_RX_DISAB 0x0000
-
-#define EP_STATUS_OUT 0x0100
-
-#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK)
-#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID)
-
-#define STM32_TOGGLE_EP(n, mask, val, flags) \
-	STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \
-			^ (val)) | (flags))
+#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0)
+#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4)
+#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8)
+#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14)
+#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18)
+#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c)
+#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20)
+#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x)*4)
+#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c)
+#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30)
+#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34)
+#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38)
+#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c)
+#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40)
+#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44)
+#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48)
+#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c)
+#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100)
+#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104)
 
 /* --- TRNG --- */
-#define STM32_RNG_CR                REG32(STM32_RNG_BASE + 0x0)
-#define STM32_RNG_CR_RNGEN          BIT(2)
-#define STM32_RNG_CR_IE             BIT(3)
-#define STM32_RNG_CR_CED            BIT(5)
-#define STM32_RNG_SR                REG32(STM32_RNG_BASE + 0x4)
-#define STM32_RNG_SR_DRDY           BIT(0)
-#define STM32_RNG_DR                REG32(STM32_RNG_BASE + 0x8)
+#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0)
+#define STM32_RNG_CR_RNGEN BIT(2)
+#define STM32_RNG_CR_IE BIT(3)
+#define STM32_RNG_CR_CED BIT(5)
+#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4)
+#define STM32_RNG_SR_DRDY BIT(0)
+#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8)
 
 /* --- AXI interconnect --- */
 
 /* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */
-#define STM32_AXI_TARG_FN_MOD(x)    REG32(STM32_GPV_BASE + 0x1108 + \
-					  0x1000 * (x))
-#define  WRITE_ISS_OVERRIDE         BIT(1)
-#define  READ_ISS_OVERRIDE          BIT(0)
+#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + 0x1000 * (x))
+#define WRITE_ISS_OVERRIDE BIT(1)
+#define READ_ISS_OVERRIDE BIT(0)
 
 /* --- MISC --- */
-#define STM32_UNIQUE_ID_ADDRESS     REG32_ADDR(STM32_UNIQUE_ID_BASE)
-#define STM32_UNIQUE_ID_LENGTH      (3 * 4)
+#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE)
+#define STM32_UNIQUE_ID_LENGTH (3 * 4)
 
 #endif /* !__ASSEMBLER__ */
diff --git a/chip/stm32/registers-stm32l4.h b/chip/stm32/registers-stm32l4.h
index 156994cc10..b55204be5e 100644
--- a/chip/stm32/registers-stm32l4.h
+++ b/chip/stm32/registers-stm32l4.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,364 +20,364 @@
 #endif
 
 /******  STM32 specific Interrupt Numbers ********/
-#define   STM32_IRQ_WWDG                    0
-#define   STM32_IRQ_PVD_PVM                 1
-#define   STM32_IRQ_TAMP_STAMP              2
-#define   STM32_IRQ_RTC_WKUP                3
-#define   STM32_IRQ_FLASH                   4
-#define   STM32_IRQ_RCC                     5
-#define   STM32_IRQ_EXTI0                   6
-#define   STM32_IRQ_EXTI1                   7
-#define   STM32_IRQ_EXTI2                   8
-#define   STM32_IRQ_EXTI3                   9
-#define   STM32_IRQ_EXTI4                   10
-#define   STM32_IRQ_DMA_CHANNEL_1           11
-#define   STM32_IRQ_DMA_CHANNEL_2           12
-#define   STM32_IRQ_DMA_CHANNEL_3           13
-#define   STM32_IRQ_DMA_CHANNEL_4           14
-#define   STM32_IRQ_DMA_CHANNEL_5           15
-#define   STM32_IRQ_DMA_CHANNEL_6           16
-#define   STM32_IRQ_DMA_CHANNEL_7           17
-#define   STM32_IRQ_ADC1                    18
-#define   STM32_IRQ_CAN1_TX                 19
-#define   STM32_IRQ_CAN1_RX0                20
-#define   STM32_IRQ_CAN1_RX1                21
-#define   STM32_IRQ_CAN1_SCE                22
-#define   STM32_IRQ_EXTI9_5                 23
-#define   STM32_IRQ_TIM1_BRK_TIM15          24
-#define   STM32_IRQ_TIM1_UP_TIM16           25
-#define   STM32_IRQ_TIM1_TRG_COM            26
-#define   STM32_IRQ_TIM1_CC                 27
-#define   STM32_IRQ_TIM2                    28
-#define   STM32_IRQ_I2C1_EV                 31
-#define   STM32_IRQ_I2C1_ER                 32
-#define   STM32_IRQ_I2C2_EV                 33
-#define   STM32_IRQ_I2C2_ER                 34
-#define   STM32_IRQ_SPI1                    35
-#define   STM32_IRQ_SPI2                    36
-#define   STM32_IRQ_USART1                  37
-#define   STM32_IRQ_USART2                  38
-#define   STM32_IRQ_USART3                  39
-#define   STM32_IRQ_EXTI15_10               40
-#define   STM32_IRQ_RTC_ALARM               41
-#define   STM32_IRQ_SDMMC1                  49
-#define   STM32_IRQ_TIM5                    50
-#define   STM32_IRQ_SPI3                    51
-#define   STM32_IRQ_TIM6_DAC                54
-#define   STM32_IRQ_TIM7                    55
-#define   STM32_IRQ_DMA2_CHANNEL1           56
-#define   STM32_IRQ_DMA2_CHANNEL2           57
-#define   STM32_IRQ_DMA2_CHANNEL3           58
-#define   STM32_IRQ_DMA2_CHANNEL4           59
-#define   STM32_IRQ_DMA2_CHANNEL5           60
-#define   STM32_IRQ_COMP                    64
-#define   LSTM32_IRQ_PTIM1                  65
-#define   STM32_IRQ_LPTIM2                  66
-#define   STM32_IRQ_DMA2_CHANNEL6           68
-#define   STM32_IRQ_DMA2_CHANNEL7           69
-#define   STM32_IRQ_LPUART1                 70
-#define   STM32_IRQ_QUADSPI                 71
-#define   STM32_IRQ_I2C3_EV                 72
-#define   STM32_IRQ_I2C3_ER                 73
-#define   STM32_IRQ_SAI1                    74
-#define   STM32_IRQ_SWPMI1                  76
-#define   STM32_IRQ_TSC                     77
-#define   STM32_IRQ_RNG                     80
-#define   STM32_IRQ_FPU                     81
-#define   STM32_IRQ_CRS                     82
+#define STM32_IRQ_WWDG 0
+#define STM32_IRQ_PVD_PVM 1
+#define STM32_IRQ_TAMP_STAMP 2
+#define STM32_IRQ_RTC_WKUP 3
+#define STM32_IRQ_FLASH 4
+#define STM32_IRQ_RCC 5
+#define STM32_IRQ_EXTI0 6
+#define STM32_IRQ_EXTI1 7
+#define STM32_IRQ_EXTI2 8
+#define STM32_IRQ_EXTI3 9
+#define STM32_IRQ_EXTI4 10
+#define STM32_IRQ_DMA_CHANNEL_1 11
+#define STM32_IRQ_DMA_CHANNEL_2 12
+#define STM32_IRQ_DMA_CHANNEL_3 13
+#define STM32_IRQ_DMA_CHANNEL_4 14
+#define STM32_IRQ_DMA_CHANNEL_5 15
+#define STM32_IRQ_DMA_CHANNEL_6 16
+#define STM32_IRQ_DMA_CHANNEL_7 17
+#define STM32_IRQ_ADC1 18
+#define STM32_IRQ_CAN1_TX 19
+#define STM32_IRQ_CAN1_RX0 20
+#define STM32_IRQ_CAN1_RX1 21
+#define STM32_IRQ_CAN1_SCE 22
+#define STM32_IRQ_EXTI9_5 23
+#define STM32_IRQ_TIM1_BRK_TIM15 24
+#define STM32_IRQ_TIM1_UP_TIM16 25
+#define STM32_IRQ_TIM1_TRG_COM 26
+#define STM32_IRQ_TIM1_CC 27
+#define STM32_IRQ_TIM2 28
+#define STM32_IRQ_I2C1_EV 31
+#define STM32_IRQ_I2C1_ER 32
+#define STM32_IRQ_I2C2_EV 33
+#define STM32_IRQ_I2C2_ER 34
+#define STM32_IRQ_SPI1 35
+#define STM32_IRQ_SPI2 36
+#define STM32_IRQ_USART1 37
+#define STM32_IRQ_USART2 38
+#define STM32_IRQ_USART3 39
+#define STM32_IRQ_EXTI15_10 40
+#define STM32_IRQ_RTC_ALARM 41
+#define STM32_IRQ_SDMMC1 49
+#define STM32_IRQ_TIM5 50
+#define STM32_IRQ_SPI3 51
+#define STM32_IRQ_TIM6_DAC 54
+#define STM32_IRQ_TIM7 55
+#define STM32_IRQ_DMA2_CHANNEL1 56
+#define STM32_IRQ_DMA2_CHANNEL2 57
+#define STM32_IRQ_DMA2_CHANNEL3 58
+#define STM32_IRQ_DMA2_CHANNEL4 59
+#define STM32_IRQ_DMA2_CHANNEL5 60
+#define STM32_IRQ_COMP 64
+#define LSTM32_IRQ_PTIM1 65
+#define STM32_IRQ_LPTIM2 66
+#define STM32_IRQ_DMA2_CHANNEL6 68
+#define STM32_IRQ_DMA2_CHANNEL7 69
+#define STM32_IRQ_LPUART1 70
+#define STM32_IRQ_QUADSPI 71
+#define STM32_IRQ_I2C3_EV 72
+#define STM32_IRQ_I2C3_ER 73
+#define STM32_IRQ_SAI1 74
+#define STM32_IRQ_SWPMI1 76
+#define STM32_IRQ_TSC 77
+#define STM32_IRQ_RNG 80
+#define STM32_IRQ_FPU 81
+#define STM32_IRQ_CRS 82
 
 /* To simplify code generation, define DMA channel 9..10 */
-#define STM32_IRQ_DMA_CHANNEL_9    STM32_IRQ_DMA2_CHANNEL1
-#define STM32_IRQ_DMA_CHANNEL_10   STM32_IRQ_DMA2_CHANNEL2
-#define STM32_IRQ_DMA_CHANNEL_11   STM32_IRQ_DMA2_CHANNEL3
-#define STM32_IRQ_DMA_CHANNEL_12   STM32_IRQ_DMA2_CHANNEL4
-#define STM32_IRQ_DMA_CHANNEL_13   STM32_IRQ_DMA2_CHANNEL5
-#define STM32_IRQ_DMA_CHANNEL_14   STM32_IRQ_DMA2_CHANNEL6
-#define STM32_IRQ_DMA_CHANNEL_15   STM32_IRQ_DMA2_CHANNEL7
-#define STM32_IRQ_USART9           STM32_IRQ_LPUART1
-
+#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1
+#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2
+#define STM32_IRQ_DMA_CHANNEL_11 STM32_IRQ_DMA2_CHANNEL3
+#define STM32_IRQ_DMA_CHANNEL_12 STM32_IRQ_DMA2_CHANNEL4
+#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL5
+#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL6
+#define STM32_IRQ_DMA_CHANNEL_15 STM32_IRQ_DMA2_CHANNEL7
+#define STM32_IRQ_USART9 STM32_IRQ_LPUART1
 
 /* Peripheral base addresses */
-#define FLASH_BASE            0x08000000UL
-#define FLASH_END             0x0803FFFFUL
-#define FLASH_BANK1_END       0x0803FFFFUL
-#define SRAM1_BASE            0x20000000UL
-#define SRAM2_BASE            0x10000000UL
-#define PERIPH_BASE           0x40000000UL
-#define QSPI_BASE             0x90000000UL
-#define QSPI_R_BASE           0xA0001000UL
-#define SRAM1_BB_BASE         0x22000000UL
-#define PERIPH_BB_BASE        0x42000000UL
+#define FLASH_BASE 0x08000000UL
+#define FLASH_END 0x0803FFFFUL
+#define FLASH_BANK1_END 0x0803FFFFUL
+#define SRAM1_BASE 0x20000000UL
+#define SRAM2_BASE 0x10000000UL
+#define PERIPH_BASE 0x40000000UL
+#define QSPI_BASE 0x90000000UL
+#define QSPI_R_BASE 0xA0001000UL
+#define SRAM1_BB_BASE 0x22000000UL
+#define PERIPH_BB_BASE 0x42000000UL
 
 /* Legacy defines */
-#define SRAM_BASE             SRAM1_BASE
-#define SRAM_BB_BASE          SRAM1_BB_BASE
-#define SRAM1_SIZE_MAX        0x0000C000UL
-#define SRAM2_SIZE            0x00004000UL
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+#define SRAM1_SIZE_MAX 0x0000C000UL
+#define SRAM2_SIZE 0x00004000UL
 #define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0)
-#define FLASH_SIZE               (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) \
-			& (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x100U << 10U) : \
-			(((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & \
-			(0x0000FFFFU)) << 10U))
+#define FLASH_SIZE                                                            \
+	(((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) ==     \
+	   0x0000FFFFU)) ?                                                    \
+		 (0x100U << 10U) :                                            \
+		 (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) \
+		  << 10U))
 
 /*!< Peripheral memory map */
-#define APB1PERIPH_BASE        PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000UL)
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)
 
 /*!< APB1 peripherals */
-#define STM32_TIM2_BASE             (APB1PERIPH_BASE + 0x0000UL)
-#define STM32_TIM5_BASE             (APB1PERIPH_BASE + 0x0C00UL)
-#define STM32_TIM6_BASE             (APB1PERIPH_BASE + 0x1000UL)
-#define STM32_TIM7_BASE             (APB1PERIPH_BASE + 0x1400UL)
-#define STM32_RTC_BASE              (APB1PERIPH_BASE + 0x2800UL)
-#define STM32_WWDG_BASE             (APB1PERIPH_BASE + 0x2C00UL)
-#define STM32_IWDG_BASE             (APB1PERIPH_BASE + 0x3000UL)
-#define STM32_SPI2_BASE             (APB1PERIPH_BASE + 0x3800UL)
-#define STM32_SPI3_BASE             (APB1PERIPH_BASE + 0x3C00UL)
-#define STM32_USART2_BASE           (APB1PERIPH_BASE + 0x4400UL)
-#define STM32_USART3_BASE           (APB1PERIPH_BASE + 0x4800UL)
-#define STM32_I2C1_BASE             (APB1PERIPH_BASE + 0x5400UL)
-#define STM32_I2C2_BASE             (APB1PERIPH_BASE + 0x5800UL)
-#define STM32_I2C3_BASE             (APB1PERIPH_BASE + 0x5C00UL)
-#define STM32_CRS_BASE              (APB1PERIPH_BASE + 0x6000UL)
-#define STM32_CAN1_BASE             (APB1PERIPH_BASE + 0x6400UL)
-#define STM32_PWR_BASE              (APB1PERIPH_BASE + 0x7000UL)
-#define STM32_DAC_BASE              (APB1PERIPH_BASE + 0x7400UL)
-#define STM32_DAC1_BASE             (APB1PERIPH_BASE + 0x7400UL)
-#define STM32_OPAMP_BASE            (APB1PERIPH_BASE + 0x7800UL)
-#define STM32_OPAMP1_BASE           (APB1PERIPH_BASE + 0x7800UL)
-#define STM32_LPTIM1_BASE           (APB1PERIPH_BASE + 0x7C00UL)
-#define STM32_LPUART1_BASE          (APB1PERIPH_BASE + 0x8000UL)
-#define STM32_SWPMI1_BASE           (APB1PERIPH_BASE + 0x8800UL)
-#define STM32_LPTIM2_BASE           (APB1PERIPH_BASE + 0x9400UL)
-
-#define STM32_USART9_BASE           STM32_LPUART1_BASE
+#define STM32_TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
+#define STM32_TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
+#define STM32_TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
+#define STM32_TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
+#define STM32_RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
+#define STM32_WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
+#define STM32_IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
+#define STM32_SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
+#define STM32_SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
+#define STM32_USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
+#define STM32_USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
+#define STM32_I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
+#define STM32_I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
+#define STM32_I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)
+#define STM32_CRS_BASE (APB1PERIPH_BASE + 0x6000UL)
+#define STM32_CAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
+#define STM32_PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
+#define STM32_DAC_BASE (APB1PERIPH_BASE + 0x7400UL)
+#define STM32_DAC1_BASE (APB1PERIPH_BASE + 0x7400UL)
+#define STM32_OPAMP_BASE (APB1PERIPH_BASE + 0x7800UL)
+#define STM32_OPAMP1_BASE (APB1PERIPH_BASE + 0x7800UL)
+#define STM32_LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL)
+#define STM32_LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL)
+#define STM32_SWPMI1_BASE (APB1PERIPH_BASE + 0x8800UL)
+#define STM32_LPTIM2_BASE (APB1PERIPH_BASE + 0x9400UL)
+
+#define STM32_USART9_BASE STM32_LPUART1_BASE
 
 /*!< APB2 peripherals */
-#define STM32_SYSCFG_BASE           (APB2PERIPH_BASE + 0x0000UL)
-#define STM32_VREFBUF_BASE          (APB2PERIPH_BASE + 0x0030UL)
-#define STM32_OMP1_BASE             (APB2PERIPH_BASE + 0x0200UL)
-#define STM32_COMP2_BASE            (APB2PERIPH_BASE + 0x0204UL)
-#define STM32_EXTI_BASE             (APB2PERIPH_BASE + 0x0400UL)
-#define STM32_FIREWALL_BASE         (APB2PERIPH_BASE + 0x1C00UL)
-#define STM32_SDMMC1_BASE           (APB2PERIPH_BASE + 0x2800UL)
-#define STM32_TIM1_BASE             (APB2PERIPH_BASE + 0x2C00UL)
-#define STM32_SPI1_BASE             (APB2PERIPH_BASE + 0x3000UL)
-#define STM32_USART1_BASE           (APB2PERIPH_BASE + 0x3800UL)
-#define STM32_TIM15_BASE            (APB2PERIPH_BASE + 0x4000UL)
-#define STM32_TIM16_BASE            (APB2PERIPH_BASE + 0x4400UL)
-#define STM32_SAI1_BASE             (APB2PERIPH_BASE + 0x5400UL)
-#define STM32_SAI1_Block_A_BASE     (SAI1_BASE + 0x0004UL)
-#define STM32_SAI1_Block_B_BASE     (SAI1_BASE + 0x0024UL)
+#define STM32_SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL)
+#define STM32_VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL)
+#define STM32_OMP1_BASE (APB2PERIPH_BASE + 0x0200UL)
+#define STM32_COMP2_BASE (APB2PERIPH_BASE + 0x0204UL)
+#define STM32_EXTI_BASE (APB2PERIPH_BASE + 0x0400UL)
+#define STM32_FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00UL)
+#define STM32_SDMMC1_BASE (APB2PERIPH_BASE + 0x2800UL)
+#define STM32_TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL)
+#define STM32_SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
+#define STM32_USART1_BASE (APB2PERIPH_BASE + 0x3800UL)
+#define STM32_TIM15_BASE (APB2PERIPH_BASE + 0x4000UL)
+#define STM32_TIM16_BASE (APB2PERIPH_BASE + 0x4400UL)
+#define STM32_SAI1_BASE (APB2PERIPH_BASE + 0x5400UL)
+#define STM32_SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL)
+#define STM32_SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL)
 
 /*!< AHB1 peripherals */
-#define STM32_DMA1_BASE             (AHB1PERIPH_BASE)
-#define STM32_DMA2_BASE             (AHB1PERIPH_BASE + 0x0400UL)
-#define STM32_RCC_BASE              (AHB1PERIPH_BASE + 0x1000UL)
-#define STM32_FLASH_R_BASE          (AHB1PERIPH_BASE + 0x2000UL)
-#define STM32_CRC_BASE              (AHB1PERIPH_BASE + 0x3000UL)
-#define STM32_TSC_BASE              (AHB1PERIPH_BASE + 0x4000UL)
-#define STM32_DMA1_Channel1_BASE    (DMA1_BASE + 0x0008UL)
-#define STM32_DMA1_Channel2_BASE    (DMA1_BASE + 0x001CUL)
-#define STM32_DMA1_Channel3_BASE    (DMA1_BASE + 0x0030UL)
-#define STM32_DMA1_Channel4_BASE    (DMA1_BASE + 0x0044UL)
-#define STM32_DMA1_Channel5_BASE    (DMA1_BASE + 0x0058UL)
-#define STM32_DMA1_Channel6_BASE    (DMA1_BASE + 0x006CUL)
-#define STM32_DMA1_Channel7_BASE    (DMA1_BASE + 0x0080UL)
-#define STM32_DMA1_CSELR_BASE       (DMA1_BASE + 0x00A8UL)
-#define STM32_DMA2_Channel1_BASE    (DMA2_BASE + 0x0008UL)
-#define STM32_DMA2_Channel2_BASE    (DMA2_BASE + 0x001CUL)
-#define STM32_DMA2_Channel3_BASE    (DMA2_BASE + 0x0030UL)
-#define STM32_DMA2_Channel4_BASE    (DMA2_BASE + 0x0044UL)
-#define STM32_DMA2_Channel5_BASE    (DMA2_BASE + 0x0058UL)
-#define STM32_DMA2_Channel6_BASE    (DMA2_BASE + 0x006CUL)
-#define STM32_DMA2_Channel7_BASE    (DMA2_BASE + 0x0080UL)
-#define STM32_DMA2_CSELR_BASE       (DMA2_BASE + 0x00A8UL)
+#define STM32_DMA1_BASE (AHB1PERIPH_BASE)
+#define STM32_DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL)
+#define STM32_RCC_BASE (AHB1PERIPH_BASE + 0x1000UL)
+#define STM32_FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL)
+#define STM32_CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
+#define STM32_TSC_BASE (AHB1PERIPH_BASE + 0x4000UL)
+#define STM32_DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL)
+#define STM32_DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL)
+#define STM32_DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL)
+#define STM32_DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL)
+#define STM32_DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL)
+#define STM32_DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL)
+#define STM32_DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL)
+#define STM32_DMA1_CSELR_BASE (DMA1_BASE + 0x00A8UL)
+#define STM32_DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL)
+#define STM32_DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL)
+#define STM32_DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL)
+#define STM32_DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL)
+#define STM32_DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL)
+#define STM32_DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL)
+#define STM32_DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL)
+#define STM32_DMA2_CSELR_BASE (DMA2_BASE + 0x00A8UL)
 
 /*!< AHB2 peripherals */
-#define STM32_GPIOA_BASE            (AHB2PERIPH_BASE + 0x0000UL)
-#define STM32_GPIOB_BASE            (AHB2PERIPH_BASE + 0x0400UL)
-#define STM32_GPIOC_BASE            (AHB2PERIPH_BASE + 0x0800UL)
-#define STM32_GPIOD_BASE            (AHB2PERIPH_BASE + 0x0C00UL)
-#define STM32_GPIOE_BASE            (AHB2PERIPH_BASE + 0x1000UL)
-#define STM32_GPIOF_BASE            (AHB2PERIPH_BASE + 0x1400UL)
-#define STM32_GPIOG_BASE            (AHB2PERIPH_BASE + 0x1800UL) /* stm32l4x6 */
-#define STM32_GPIOH_BASE            (AHB2PERIPH_BASE + 0x1C00UL)
-#define STM32_ADC1_BASE             (AHB2PERIPH_BASE + 0x08040000UL)
-#define STM32_ADC1_COMMON_BASE      (AHB2PERIPH_BASE + 0x08040300UL)
-#define STM32_RNG_BASE              (AHB2PERIPH_BASE + 0x08060800UL)
+#define STM32_GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL)
+#define STM32_GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL)
+#define STM32_GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL)
+#define STM32_GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL)
+#define STM32_GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL)
+#define STM32_GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL)
+#define STM32_GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL) /* stm32l4x6 */
+#define STM32_GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00UL)
+#define STM32_ADC1_BASE (AHB2PERIPH_BASE + 0x08040000UL)
+#define STM32_ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300UL)
+#define STM32_RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL)
 
 /* Debug MCU registers base address */
-#define STM32_DBGMCU_BASE           0xE0042000UL
-#define STM32_PACKAGE_BASE          0x1FFF7500UL
-#define STM32_UID_BASE              0x1FFF7590UL
-#define STM32_FLASHSIZE_BASE        0x1FFF75E0UL
+#define STM32_DBGMCU_BASE 0xE0042000UL
+#define STM32_PACKAGE_BASE 0x1FFF7500UL
+#define STM32_UID_BASE 0x1FFF7590UL
+#define STM32_FLASHSIZE_BASE 0x1FFF75E0UL
 
-#define STM32_FLASH_REGS_BASE       STM32_FLASH_R_BASE
-#define STM32_UNIQUE_ID_BASE        STM32_UID_BASE
-#define STM32_OPTB_BASE             0x1FFF7800
+#define STM32_FLASH_REGS_BASE STM32_FLASH_R_BASE
+#define STM32_UNIQUE_ID_BASE STM32_UID_BASE
+#define STM32_OPTB_BASE 0x1FFF7800
 
 #ifndef __ASSEMBLER__
 
 /* Register definitions */
 
 /* --- USART --- */
-#define STM32_USART_CR1(base)       STM32_USART_REG(base, 0x00)
-#define STM32_USART_CR1_UE          BIT(0)
-#define STM32_USART_CR1_UESM        BIT(1)
-#define STM32_USART_CR1_RE          BIT(2)
-#define STM32_USART_CR1_TE          BIT(3)
-#define STM32_USART_CR1_RXNEIE      BIT(5)
-#define STM32_USART_CR1_TCIE        BIT(6)
-#define STM32_USART_CR1_TXEIE       BIT(7)
-#define STM32_USART_CR1_PS          BIT(9)
-#define STM32_USART_CR1_PCE         BIT(10)
-#define STM32_USART_CR1_M           BIT(12)
-#define STM32_USART_CR1_OVER8       BIT(15)
-
-#define STM32_USART_CR2(base)       STM32_USART_REG(base, 0x04)
-#define STM32_USART_CR2_SWAP        BIT(15)
-
-#define STM32_USART_CR3(base)       STM32_USART_REG(base, 0x08)
-#define STM32_USART_CR3_EIE         BIT(0)
-#define STM32_USART_CR3_DMAR        BIT(6)
-#define STM32_USART_CR3_DMAT        BIT(7)
-#define STM32_USART_CR3_ONEBIT      BIT(11)
-#define STM32_USART_CR3_OVRDIS      BIT(12)
+#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00)
+#define STM32_USART_CR1_UE BIT(0)
+#define STM32_USART_CR1_UESM BIT(1)
+#define STM32_USART_CR1_RE BIT(2)
+#define STM32_USART_CR1_TE BIT(3)
+#define STM32_USART_CR1_RXNEIE BIT(5)
+#define STM32_USART_CR1_TCIE BIT(6)
+#define STM32_USART_CR1_TXEIE BIT(7)
+#define STM32_USART_CR1_PS BIT(9)
+#define STM32_USART_CR1_PCE BIT(10)
+#define STM32_USART_CR1_M BIT(12)
+#define STM32_USART_CR1_OVER8 BIT(15)
+
+#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04)
+#define STM32_USART_CR2_SWAP BIT(15)
+
+#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08)
+#define STM32_USART_CR3_EIE BIT(0)
+#define STM32_USART_CR3_DMAR BIT(6)
+#define STM32_USART_CR3_DMAT BIT(7)
+#define STM32_USART_CR3_ONEBIT BIT(11)
+#define STM32_USART_CR3_OVRDIS BIT(12)
 #define STM32_USART_CR3_WUS_START_BIT (2 << 20)
-#define STM32_USART_CR3_WUFIE       BIT(22)
-
-#define STM32_USART_BRR(base)       STM32_USART_REG(base, 0x0C)
-#define STM32_USART_GTPR(base)      STM32_USART_REG(base, 0x10)
-#define STM32_USART_RTOR(base)      STM32_USART_REG(base, 0x14)
-#define STM32_USART_RQR(base)       STM32_USART_REG(base, 0x18)
-#define STM32_USART_ISR(base)       STM32_USART_REG(base, 0x1C)
-#define STM32_USART_ICR(base)       STM32_USART_REG(base, 0x20)
-#define STM32_USART_ICR_ORECF       BIT(3)
-#define STM32_USART_ICR_TCCF        BIT(6)
-#define STM32_USART_RDR(base)       STM32_USART_REG(base, 0x24)
-#define STM32_USART_TDR(base)       STM32_USART_REG(base, 0x28)
-#define STM32_USART_PRESC(base)     STM32_USART_REG(base, 0x2C)
+#define STM32_USART_CR3_WUFIE BIT(22)
+
+#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C)
+#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10)
+#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14)
+#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18)
+#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C)
+#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20)
+#define STM32_USART_ICR_ORECF BIT(3)
+#define STM32_USART_ICR_TCCF BIT(6)
+#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24)
+#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28)
+#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C)
 /* register alias */
-#define STM32_USART_SR(base)        STM32_USART_ISR(base)
-#define STM32_USART_SR_ORE          BIT(3)
-#define STM32_USART_SR_RXNE         BIT(5)
-#define STM32_USART_SR_TC           BIT(6)
-#define STM32_USART_SR_TXE          BIT(7)
+#define STM32_USART_SR(base) STM32_USART_ISR(base)
+#define STM32_USART_SR_ORE BIT(3)
+#define STM32_USART_SR_RXNE BIT(5)
+#define STM32_USART_SR_TC BIT(6)
+#define STM32_USART_SR_TXE BIT(7)
 
 /* --- GPIO --- */
-#define STM32_GPIO_MODER(b)     REG32((b) + 0x00)
-#define STM32_GPIO_OTYPER(b)    REG16((b) + 0x04)
-#define STM32_GPIO_OSPEEDR(b)   REG32((b) + 0x08)
-#define STM32_GPIO_PUPDR(b)     REG32((b) + 0x0C)
-#define STM32_GPIO_IDR(b)       REG16((b) + 0x10)
-#define STM32_GPIO_ODR(b)       REG16((b) + 0x14)
-#define STM32_GPIO_BSRR(b)      REG32((b) + 0x18)
-#define STM32_GPIO_LCKR(b)      REG32((b) + 0x1C)
-#define STM32_GPIO_AFRL(b)      REG32((b) + 0x20)
-#define STM32_GPIO_AFRH(b)      REG32((b) + 0x24)
-#define STM32_GPIO_BRR(b)       REG32((b) + 0x28)
-#define STM32_GPIO_ASCR(b)      REG32((b) + 0x2C) /* only for stm32l4x6 */
-
-#define GPIO_ALT_F0		0x0
-#define GPIO_ALT_F1		0x1
-#define GPIO_ALT_F2		0x2
-#define GPIO_ALT_F3		0x3
-#define GPIO_ALT_F4		0x4
-#define GPIO_ALT_F5		0x5
-#define GPIO_ALT_F6		0x6
-#define GPIO_ALT_F7		0x7
-#define GPIO_ALT_F8		0x8
-#define GPIO_ALT_F9		0x9
-#define GPIO_ALT_FA		0xA
-#define GPIO_ALT_FB		0xB
-#define GPIO_ALT_FC		0xC
-#define GPIO_ALT_FD		0xD
-#define GPIO_ALT_FE		0xE
-#define GPIO_ALT_FF		0xF
+#define STM32_GPIO_MODER(b) REG32((b) + 0x00)
+#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04)
+#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08)
+#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C)
+#define STM32_GPIO_IDR(b) REG16((b) + 0x10)
+#define STM32_GPIO_ODR(b) REG16((b) + 0x14)
+#define STM32_GPIO_BSRR(b) REG32((b) + 0x18)
+#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C)
+#define STM32_GPIO_AFRL(b) REG32((b) + 0x20)
+#define STM32_GPIO_AFRH(b) REG32((b) + 0x24)
+#define STM32_GPIO_BRR(b) REG32((b) + 0x28)
+#define STM32_GPIO_ASCR(b) REG32((b) + 0x2C) /* only for stm32l4x6 */
+
+#define GPIO_ALT_F0 0x0
+#define GPIO_ALT_F1 0x1
+#define GPIO_ALT_F2 0x2
+#define GPIO_ALT_F3 0x3
+#define GPIO_ALT_F4 0x4
+#define GPIO_ALT_F5 0x5
+#define GPIO_ALT_F6 0x6
+#define GPIO_ALT_F7 0x7
+#define GPIO_ALT_F8 0x8
+#define GPIO_ALT_F9 0x9
+#define GPIO_ALT_FA 0xA
+#define GPIO_ALT_FB 0xB
+#define GPIO_ALT_FC 0xC
+#define GPIO_ALT_FD 0xD
+#define GPIO_ALT_FE 0xE
+#define GPIO_ALT_FF 0xF
 
 /* --- I2C --- */
-#define STM32_I2C_CR1(n)            REG32(stm32_i2c_reg(n, 0x00))
-#define STM32_I2C_CR1_PE            BIT(0)
-#define STM32_I2C_CR1_TXIE          BIT(1)
-#define STM32_I2C_CR1_RXIE          BIT(2)
-#define STM32_I2C_CR1_ADDRIE        BIT(3)
-#define STM32_I2C_CR1_NACKIE        BIT(4)
-#define STM32_I2C_CR1_STOPIE        BIT(5)
-#define STM32_I2C_CR1_ERRIE         BIT(7)
-#define STM32_I2C_CR1_WUPEN         BIT(18)
-#define STM32_I2C_CR2(n)            REG32(stm32_i2c_reg(n, 0x04))
-#define STM32_I2C_CR2_RD_WRN        BIT(10)
-#define STM32_I2C_CR2_START         BIT(13)
-#define STM32_I2C_CR2_STOP          BIT(14)
-#define STM32_I2C_CR2_NACK          BIT(15)
-#define STM32_I2C_CR2_RELOAD        BIT(24)
-#define STM32_I2C_CR2_AUTOEND       BIT(25)
-#define STM32_I2C_OAR1(n)           REG32(stm32_i2c_reg(n, 0x08))
-#define STM32_I2C_OAR2(n)           REG32(stm32_i2c_reg(n, 0x0C))
-#define STM32_I2C_TIMINGR(n)        REG32(stm32_i2c_reg(n, 0x10))
-#define STM32_I2C_TIMEOUTR(n)       REG32(stm32_i2c_reg(n, 0x14))
-#define STM32_I2C_ISR(n)            REG32(stm32_i2c_reg(n, 0x18))
-#define STM32_I2C_ISR_TXE           BIT(0)
-#define STM32_I2C_ISR_TXIS          BIT(1)
-#define STM32_I2C_ISR_RXNE          BIT(2)
-#define STM32_I2C_ISR_ADDR          BIT(3)
-#define STM32_I2C_ISR_NACK          BIT(4)
-#define STM32_I2C_ISR_STOP          BIT(5)
-#define STM32_I2C_ISR_TC            BIT(6)
-#define STM32_I2C_ISR_TCR           BIT(7)
-#define STM32_I2C_ISR_BERR          BIT(8)
-#define STM32_I2C_ISR_ARLO          BIT(9)
-#define STM32_I2C_ISR_OVR           BIT(10)
-#define STM32_I2C_ISR_PECERR        BIT(11)
-#define STM32_I2C_ISR_TIMEOUT       BIT(12)
-#define STM32_I2C_ISR_ALERT         BIT(13)
-#define STM32_I2C_ISR_BUSY          BIT(15)
-#define STM32_I2C_ISR_DIR           BIT(16)
-#define STM32_I2C_ISR_ADDCODE(isr)  (((isr) >> 16) & 0xfe)
-#define STM32_I2C_ICR(n)            REG32(stm32_i2c_reg(n, 0x1C))
-#define STM32_I2C_ICR_ADDRCF        BIT(3)
-#define STM32_I2C_ICR_NACKCF        BIT(4)
-#define STM32_I2C_ICR_STOPCF        BIT(5)
-#define STM32_I2C_ICR_BERRCF        BIT(8)
-#define STM32_I2C_ICR_ARLOCF        BIT(9)
-#define STM32_I2C_ICR_OVRCF         BIT(10)
-#define STM32_I2C_ICR_TIMEOUTCF     BIT(12)
-#define STM32_I2C_ICR_ALL           0x3F38
-#define STM32_I2C_PECR(n)           REG32(stm32_i2c_reg(n, 0x20))
-#define STM32_I2C_RXDR(n)           REG32(stm32_i2c_reg(n, 0x24))
-#define STM32_I2C_TXDR(n)           REG32(stm32_i2c_reg(n, 0x28))
+#define STM32_I2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00))
+#define STM32_I2C_CR1_PE BIT(0)
+#define STM32_I2C_CR1_TXIE BIT(1)
+#define STM32_I2C_CR1_RXIE BIT(2)
+#define STM32_I2C_CR1_ADDRIE BIT(3)
+#define STM32_I2C_CR1_NACKIE BIT(4)
+#define STM32_I2C_CR1_STOPIE BIT(5)
+#define STM32_I2C_CR1_ERRIE BIT(7)
+#define STM32_I2C_CR1_WUPEN BIT(18)
+#define STM32_I2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04))
+#define STM32_I2C_CR2_RD_WRN BIT(10)
+#define STM32_I2C_CR2_START BIT(13)
+#define STM32_I2C_CR2_STOP BIT(14)
+#define STM32_I2C_CR2_NACK BIT(15)
+#define STM32_I2C_CR2_RELOAD BIT(24)
+#define STM32_I2C_CR2_AUTOEND BIT(25)
+#define STM32_I2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08))
+#define STM32_I2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C))
+#define STM32_I2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10))
+#define STM32_I2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14))
+#define STM32_I2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18))
+#define STM32_I2C_ISR_TXE BIT(0)
+#define STM32_I2C_ISR_TXIS BIT(1)
+#define STM32_I2C_ISR_RXNE BIT(2)
+#define STM32_I2C_ISR_ADDR BIT(3)
+#define STM32_I2C_ISR_NACK BIT(4)
+#define STM32_I2C_ISR_STOP BIT(5)
+#define STM32_I2C_ISR_TC BIT(6)
+#define STM32_I2C_ISR_TCR BIT(7)
+#define STM32_I2C_ISR_BERR BIT(8)
+#define STM32_I2C_ISR_ARLO BIT(9)
+#define STM32_I2C_ISR_OVR BIT(10)
+#define STM32_I2C_ISR_PECERR BIT(11)
+#define STM32_I2C_ISR_TIMEOUT BIT(12)
+#define STM32_I2C_ISR_ALERT BIT(13)
+#define STM32_I2C_ISR_BUSY BIT(15)
+#define STM32_I2C_ISR_DIR BIT(16)
+#define STM32_I2C_ISR_ADDCODE(isr) (((isr) >> 16) & 0xfe)
+#define STM32_I2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C))
+#define STM32_I2C_ICR_ADDRCF BIT(3)
+#define STM32_I2C_ICR_NACKCF BIT(4)
+#define STM32_I2C_ICR_STOPCF BIT(5)
+#define STM32_I2C_ICR_BERRCF BIT(8)
+#define STM32_I2C_ICR_ARLOCF BIT(9)
+#define STM32_I2C_ICR_OVRCF BIT(10)
+#define STM32_I2C_ICR_TIMEOUTCF BIT(12)
+#define STM32_I2C_ICR_ALL 0x3F38
+#define STM32_I2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20))
+#define STM32_I2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24))
+#define STM32_I2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28))
 
 /* --- Power / Reset / Clocks --- */
-#define STM32_PWR_CR1               REG32(STM32_PWR_BASE + 0x00)
-#define STM32_PWR_CR2               REG32(STM32_PWR_BASE + 0x04)
-#define STM32_PWR_CSR               REG32(STM32_PWR_BASE + 0x10)
-#define STM32_PWR_SCR               REG32(STM32_PWR_BASE + 0x18)
-
-#define PWR_CR1_LPMS_POS             0U
-#define PWR_CR1_LPMS_MSK             (0x7UL << PWR_CR1_LPMS_POS)
-#define PWR_CR1_LPMS                 PWR_CR1_LPMS_MSK
-#define PWR_CR1_LPMS_STOP0           (0x00000000UL)
-#define PWR_CR1_LPMS_STOP1_POS       0U
-#define PWR_CR1_LPMS_STOP1_MSK       (0x1UL << PWR_CR1_LPMS_STOP1_POS)
-#define PWR_CR1_LPMS_STOP1           PWR_CR1_LPMS_STOP1_MSK
-#define PWR_CR1_LPMS_STOP2_POS       1U
-#define PWR_CR1_LPMS_STOP2_MSK       (0x1UL << PWR_CR1_LPMS_STOP2_POS)
-#define PWR_CR1_LPMS_STOP2           PWR_CR1_LPMS_STOP2_MSK
-#define PWR_CR1_LPMS_STANDBY_POS     0U
-#define PWR_CR1_LPMS_STANDBY_MSK     (0x3UL << PWR_CR1_LPMS_STANDBY_POS)
-#define PWR_CR1_LPMS_STANDBY         PWR_CR1_LPMS_STANDBY_MSK
-#define PWR_CR1_LPMS_SHUTDOWN_POS    2U
-#define PWR_CR1_LPMS_SHUTDOWN_MSK    (0x1UL << PWR_CR1_LPMS_SHUTDOWN_POS)
-#define PWR_CR1_LPMS_SHUTDOWN        PWR_CR1_LPMS_SHUTDOWN_MSK
-#define PWR_CR1_VOS_POS              9U
-#define PWR_CR1_VOS_MSK              (0x3UL << PWR_CR1_VOS_POS)
-#define PWR_CR1_VOS                  PWR_CR1_VOS_MSK
-#define PWR_CR1_VOS_0                (0x1UL << PWR_CR1_VOS_POS)
-#define PWR_CR1_VOS_1                (0x2UL << PWR_CR1_VOS_POS)
-
+#define STM32_PWR_CR1 REG32(STM32_PWR_BASE + 0x00)
+#define STM32_PWR_CR2 REG32(STM32_PWR_BASE + 0x04)
+#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x10)
+#define STM32_PWR_SCR REG32(STM32_PWR_BASE + 0x18)
+
+#define PWR_CR1_LPMS_POS 0U
+#define PWR_CR1_LPMS_MSK (0x7UL << PWR_CR1_LPMS_POS)
+#define PWR_CR1_LPMS PWR_CR1_LPMS_MSK
+#define PWR_CR1_LPMS_STOP0 (0x00000000UL)
+#define PWR_CR1_LPMS_STOP1_POS 0U
+#define PWR_CR1_LPMS_STOP1_MSK (0x1UL << PWR_CR1_LPMS_STOP1_POS)
+#define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_MSK
+#define PWR_CR1_LPMS_STOP2_POS 1U
+#define PWR_CR1_LPMS_STOP2_MSK (0x1UL << PWR_CR1_LPMS_STOP2_POS)
+#define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_MSK
+#define PWR_CR1_LPMS_STANDBY_POS 0U
+#define PWR_CR1_LPMS_STANDBY_MSK (0x3UL << PWR_CR1_LPMS_STANDBY_POS)
+#define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_MSK
+#define PWR_CR1_LPMS_SHUTDOWN_POS 2U
+#define PWR_CR1_LPMS_SHUTDOWN_MSK (0x1UL << PWR_CR1_LPMS_SHUTDOWN_POS)
+#define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_MSK
+#define PWR_CR1_VOS_POS 9U
+#define PWR_CR1_VOS_MSK (0x3UL << PWR_CR1_VOS_POS)
+#define PWR_CR1_VOS PWR_CR1_VOS_MSK
+#define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_POS)
+#define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_POS)
 
 /* --- Macro usage in ec code --- */
 #define STM32_RCC_AHB2ENR_GPIOMASK                               \
@@ -388,133 +388,131 @@
 #define STM32_RCC_ICSCR_MSIRANGE_1MHZ STM32_RCC_ICSCR_MSIRANGE(4)
 #define STM32_RCC_ICSCR_MSIRANGE_2MHZ STM32_RCC_ICSCR_MSIRANGE(5)
 #define STM32_RCC_ICSCR_MSIRANGE_MASK STM32_RCC_CR_MSIRANGE_MSK
-#define STM32_RCC_SYSCFGEN            STM32_RCC_APB2ENR_SYSCFGEN
+#define STM32_RCC_SYSCFGEN STM32_RCC_APB2ENR_SYSCFGEN
 
-#define STM32_RCC_PB2_TIM1            STM32_RCC_APB2ENR_TIM1EN
-#define STM32_RCC_PB2_TIM15           STM32_RCC_APB2ENR_TIM15EN
-#define STM32_RCC_PB2_TIM16           STM32_RCC_APB2ENR_TIM16EN
+#define STM32_RCC_PB2_TIM1 STM32_RCC_APB2ENR_TIM1EN
+#define STM32_RCC_PB2_TIM15 STM32_RCC_APB2ENR_TIM15EN
+#define STM32_RCC_PB2_TIM16 STM32_RCC_APB2ENR_TIM16EN
 #ifndef CHIP_VARIANT_STM32L431X
-#define STM32_RCC_PB2_TIM8            BIT(13)
+#define STM32_RCC_PB2_TIM8 BIT(13)
 #endif
 #define STM32_RCC_PWREN STM32_RCC_APB1ENR1_PWREN
 
-#define STM32_RCC_AHB2ENR_GPIO_PORTA	BIT(0)
-#define STM32_RCC_AHB2ENR_GPIO_PORTB	BIT(1)
-#define STM32_RCC_AHB2ENR_GPIO_PORTC	BIT(2)
-#define STM32_RCC_AHB2ENR_GPIO_PORTD	BIT(3)
-#define STM32_RCC_AHB2ENR_GPIO_PORTE	BIT(4)
-#define STM32_RCC_AHB2ENR_GPIO_PORTH	BIT(7)
+#define STM32_RCC_AHB2ENR_GPIO_PORTA BIT(0)
+#define STM32_RCC_AHB2ENR_GPIO_PORTB BIT(1)
+#define STM32_RCC_AHB2ENR_GPIO_PORTC BIT(2)
+#define STM32_RCC_AHB2ENR_GPIO_PORTD BIT(3)
+#define STM32_RCC_AHB2ENR_GPIO_PORTE BIT(4)
+#define STM32_RCC_AHB2ENR_GPIO_PORTH BIT(7)
 #define STM32_RCC_CCIPR_USART1SEL_SHIFT (0)
-#define STM32_RCC_CCIPR_USART1SEL_MASK  (3 << STM32_RCC_CCIPR_USART1SEL_SHIFT)
+#define STM32_RCC_CCIPR_USART1SEL_MASK (3 << STM32_RCC_CCIPR_USART1SEL_SHIFT)
 #define STM32_RCC_CCIPR_USART2SEL_SHIFT (2)
-#define STM32_RCC_CCIPR_USART2SEL_MASK  (3 << STM32_RCC_CCIPR_USART2SEL_SHIFT)
+#define STM32_RCC_CCIPR_USART2SEL_MASK (3 << STM32_RCC_CCIPR_USART2SEL_SHIFT)
 #define STM32_RCC_CCIPR_USART3SEL_SHIFT (4)
-#define STM32_RCC_CCIPR_USART3SEL_MASK  (3 << STM32_RCC_CCIPR_USART3SEL_SHIFT)
+#define STM32_RCC_CCIPR_USART3SEL_MASK (3 << STM32_RCC_CCIPR_USART3SEL_SHIFT)
 #define STM32_RCC_CCIPR_UART4SEL_SHIFT (6)
-#define STM32_RCC_CCIPR_UART4SEL_MASK  (3 << STM32_RCC_CCIPR_UART4SEL_SHIFT)
+#define STM32_RCC_CCIPR_UART4SEL_MASK (3 << STM32_RCC_CCIPR_UART4SEL_SHIFT)
 #define STM32_RCC_CCIPR_UART5SEL_SHIFT (8)
-#define STM32_RCC_CCIPR_UART5SEL_MASK  (3 << STM32_RCC_CCIPR_UART5SEL_SHIFT)
+#define STM32_RCC_CCIPR_UART5SEL_MASK (3 << STM32_RCC_CCIPR_UART5SEL_SHIFT)
 #define STM32_RCC_CCIPR_LPUART1SEL_SHIFT (10)
-#define STM32_RCC_CCIPR_LPUART1SEL_MASK  (3 << STM32_RCC_CCIPR_LPUART1SEL_SHIFT)
+#define STM32_RCC_CCIPR_LPUART1SEL_MASK (3 << STM32_RCC_CCIPR_LPUART1SEL_SHIFT)
 #define STM32_RCC_CCIPR_I2C1SEL_SHIFT (12)
-#define STM32_RCC_CCIPR_I2C1SEL_MASK  (3 << STM32_RCC_CCIPR_I2C1SEL_SHIFT)
+#define STM32_RCC_CCIPR_I2C1SEL_MASK (3 << STM32_RCC_CCIPR_I2C1SEL_SHIFT)
 #define STM32_RCC_CCIPR_I2C2SEL_SHIFT (14)
-#define STM32_RCC_CCIPR_I2C2SEL_MASK  (3 << STM32_RCC_CCIPR_I2C2SEL_SHIFT)
+#define STM32_RCC_CCIPR_I2C2SEL_MASK (3 << STM32_RCC_CCIPR_I2C2SEL_SHIFT)
 #define STM32_RCC_CCIPR_I2C3SEL_SHIFT (16)
-#define STM32_RCC_CCIPR_I2C3SEL_MASK  (3 << STM32_RCC_CCIPR_I2C3SEL_SHIFT)
+#define STM32_RCC_CCIPR_I2C3SEL_MASK (3 << STM32_RCC_CCIPR_I2C3SEL_SHIFT)
 #define STM32_RCC_CCIPR_LPTIM1SEL_SHIFT (18)
-#define STM32_RCC_CCIPR_LPTIM1SEL_MASK  (3 << STM32_RCC_CCIPR_LPTIM1SEL_SHIFT)
+#define STM32_RCC_CCIPR_LPTIM1SEL_MASK (3 << STM32_RCC_CCIPR_LPTIM1SEL_SHIFT)
 #define STM32_RCC_CCIPR_LPTIM2SEL_SHIFT (20)
-#define STM32_RCC_CCIPR_LPTIM2SEL_MASK  (3 << STM32_RCC_CCIPR_LPTIM2SEL_SHIFT)
+#define STM32_RCC_CCIPR_LPTIM2SEL_MASK (3 << STM32_RCC_CCIPR_LPTIM2SEL_SHIFT)
 #define STM32_RCC_CCIPR_SAI1SEL_SHIFT (22)
-#define STM32_RCC_CCIPR_SAI1SEL_MASK  (3 << STM32_RCC_CCIPR_SAI1SEL_SHIFT)
+#define STM32_RCC_CCIPR_SAI1SEL_MASK (3 << STM32_RCC_CCIPR_SAI1SEL_SHIFT)
 #define STM32_RCC_CCIPR_SAI2SEL_SHIFT (24)
-#define STM32_RCC_CCIPR_SAI2SEL_MASK  (3 << STM32_RCC_CCIPR_SAI2SEL_SHIFT)
+#define STM32_RCC_CCIPR_SAI2SEL_MASK (3 << STM32_RCC_CCIPR_SAI2SEL_SHIFT)
 #define STM32_RCC_CCIPR_CLK48SEL_SHIFT (26)
-#define STM32_RCC_CCIPR_CLK48SEL_MASK  (3 << STM32_RCC_CCIPR_CLK48SEL_SHIFT)
+#define STM32_RCC_CCIPR_CLK48SEL_MASK (3 << STM32_RCC_CCIPR_CLK48SEL_SHIFT)
 #define STM32_RCC_CCIPR_ADCSEL_SHIFT (28)
-#define STM32_RCC_CCIPR_ADCSEL_MASK  (3 << STM32_RCC_CCIPR_ADCSEL_SHIFT)
+#define STM32_RCC_CCIPR_ADCSEL_MASK (3 << STM32_RCC_CCIPR_ADCSEL_SHIFT)
 #define STM32_RCC_CCIPR_SWPMI1SEL_SHIFT (30)
-#define STM32_RCC_CCIPR_SWPMI1SEL_MASK  BIT(STM32_RCC_CCIPR_SWPMI1SEL_SHIFT)
+#define STM32_RCC_CCIPR_SWPMI1SEL_MASK BIT(STM32_RCC_CCIPR_SWPMI1SEL_SHIFT)
 #define STM32_RCC_CCIPR_DFSDM1SEL_SHIFT (31)
-#define STM32_RCC_CCIPR_DFSDM1SEL_MASK  BIT(STM32_RCC_CCIPR_DFSDM1SEL_SHIFT)
+#define STM32_RCC_CCIPR_DFSDM1SEL_MASK BIT(STM32_RCC_CCIPR_DFSDM1SEL_SHIFT)
 /* Possible clock sources for each peripheral */
-#define STM32_RCC_CCIPR_UART_PCLK	0
-#define STM32_RCC_CCIPR_UART_SYSCLK	1
-#define STM32_RCC_CCIPR_UART_HSI16	2
-#define STM32_RCC_CCIPR_UART_LSE	3
-
-#define STM32_RCC_CCIPR_I2C_PCLK	0
-#define STM32_RCC_CCIPR_I2C_SYSCLK	1
-#define STM32_RCC_CCIPR_I2C_HSI16	2
-
-#define STM32_RCC_CCIPR_LPTIM_PCLK	0
-#define STM32_RCC_CCIPR_LPTIM_LSI	1
-#define STM32_RCC_CCIPR_LPTIM_HSI16	2
-#define STM32_RCC_CCIPR_LPTIM_LSE	3
-
-#define STM32_RCC_CCIPR_SAI_PLLSAI1CLK	0
-#define STM32_RCC_CCIPR_SAI_PLLSAI2CLK	1
-#define STM32_RCC_CCIPR_SAI_PLLSAI3CLK	2
-#define STM32_RCC_CCIPR_SAI_EXTCLK		3
-
-#define STM32_RCC_CCIPR_CLK48_NONE			0
-#define STM32_RCC_CCIPR_CLK48_PLL48M2CLK	1
-#define STM32_RCC_CCIPR_CLK48_PLL48M1CLK	2
-#define STM32_RCC_CCIPR_CLK48_MSI			3
-
-#define STM32_RCC_CCIPR_ADC_NONE		0
-#define STM32_RCC_CCIPR_ADC_PLLADC1CLK	1
-#define STM32_RCC_CCIPR_ADC_PLLADC2CLK	2
-#define STM32_RCC_CCIPR_ADC_SYSCLK	3
-
-#define STM32_RCC_CCIPR_SWPMI_PCLK	0
-#define STM32_RCC_CCIPR_SWPMI_HSI16	1
-
-#define STM32_RCC_CCIPR_DFSDM_PCLK		0
-#define STM32_RCC_CCIPR_DFSDM_SYSCLK	1
-
-
-
-#define STM32_RCC_CR          REG32(STM32_RCC_BASE + 0x00)
-#define STM32_RCC_ICSCR       REG32(STM32_RCC_BASE + 0x04)
-#define STM32_RCC_CFGR        REG32(STM32_RCC_BASE + 0x08)
-#define STM32_RCC_PLLCFGR     REG32(STM32_RCC_BASE + 0x0C)
+#define STM32_RCC_CCIPR_UART_PCLK 0
+#define STM32_RCC_CCIPR_UART_SYSCLK 1
+#define STM32_RCC_CCIPR_UART_HSI16 2
+#define STM32_RCC_CCIPR_UART_LSE 3
+
+#define STM32_RCC_CCIPR_I2C_PCLK 0
+#define STM32_RCC_CCIPR_I2C_SYSCLK 1
+#define STM32_RCC_CCIPR_I2C_HSI16 2
+
+#define STM32_RCC_CCIPR_LPTIM_PCLK 0
+#define STM32_RCC_CCIPR_LPTIM_LSI 1
+#define STM32_RCC_CCIPR_LPTIM_HSI16 2
+#define STM32_RCC_CCIPR_LPTIM_LSE 3
+
+#define STM32_RCC_CCIPR_SAI_PLLSAI1CLK 0
+#define STM32_RCC_CCIPR_SAI_PLLSAI2CLK 1
+#define STM32_RCC_CCIPR_SAI_PLLSAI3CLK 2
+#define STM32_RCC_CCIPR_SAI_EXTCLK 3
+
+#define STM32_RCC_CCIPR_CLK48_NONE 0
+#define STM32_RCC_CCIPR_CLK48_PLL48M2CLK 1
+#define STM32_RCC_CCIPR_CLK48_PLL48M1CLK 2
+#define STM32_RCC_CCIPR_CLK48_MSI 3
+
+#define STM32_RCC_CCIPR_ADC_NONE 0
+#define STM32_RCC_CCIPR_ADC_PLLADC1CLK 1
+#define STM32_RCC_CCIPR_ADC_PLLADC2CLK 2
+#define STM32_RCC_CCIPR_ADC_SYSCLK 3
+
+#define STM32_RCC_CCIPR_SWPMI_PCLK 0
+#define STM32_RCC_CCIPR_SWPMI_HSI16 1
+
+#define STM32_RCC_CCIPR_DFSDM_PCLK 0
+#define STM32_RCC_CCIPR_DFSDM_SYSCLK 1
+
+#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00)
+#define STM32_RCC_ICSCR REG32(STM32_RCC_BASE + 0x04)
+#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08)
+#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x0C)
 #define STM32_RCC_PLLSAI1CFGR REG32(STM32_RCC_BASE + 0x10)
-#define STM32_RCC_RESERVED    REG32(STM32_RCC_BASE + 0x14)
-#define STM32_RCC_CIER        REG32(STM32_RCC_BASE + 0x18)
-#define STM32_RCC_CIFR        REG32(STM32_RCC_BASE + 0x1C)
-#define STM32_RCC_CICR        REG32(STM32_RCC_BASE + 0x20)
-#define STM32_RCC_RESERVED0   REG32(STM32_RCC_BASE + 0x24)
-#define STM32_RCC_AHB1RSTR    REG32(STM32_RCC_BASE + 0x28)
-#define STM32_RCC_AHB2RSTR    REG32(STM32_RCC_BASE + 0x2C)
-#define STM32_RCC_AHB3RSTR    REG32(STM32_RCC_BASE + 0x30)
-#define STM32_RCC_RESERVED1   REG32(STM32_RCC_BASE + 0x34)
-#define STM32_RCC_APB1RSTR1   REG32(STM32_RCC_BASE + 0x38)
-#define STM32_RCC_APB1RSTR2   REG32(STM32_RCC_BASE + 0x3C)
-#define STM32_RCC_APB2RSTR    REG32(STM32_RCC_BASE + 0x40)
-#define STM32_RCC_RESERVED2   REG32(STM32_RCC_BASE + 0x44)
-#define STM32_RCC_AHB1ENR     REG32(STM32_RCC_BASE + 0x48)
-#define STM32_RCC_AHB2ENR     REG32(STM32_RCC_BASE + 0x4C)
-#define STM32_RCC_AHB3ENR     REG32(STM32_RCC_BASE + 0x50)
-#define STM32_RCC_RESERVED3   REG32(STM32_RCC_BASE + 0x54)
-#define STM32_RCC_APB1ENR1    REG32(STM32_RCC_BASE + 0x58)
-#define STM32_RCC_APB1ENR2    REG32(STM32_RCC_BASE + 0x5C)
-#define STM32_RCC_APB2ENR     REG32(STM32_RCC_BASE + 0x60)
-#define STM32_RCC_RESERVED4   REG32(STM32_RCC_BASE + 0x64)
-#define STM32_RCC_AHB1SMENR   REG32(STM32_RCC_BASE + 0x68)
-#define STM32_RCC_AHB2SMENR   REG32(STM32_RCC_BASE + 0x6C)
-#define STM32_RCC_AHB3SMENR   REG32(STM32_RCC_BASE + 0x70)
-#define STM32_RCC_RESERVED5   REG32(STM32_RCC_BASE + 0x74)
-#define STM32_RCC_APB1SMENR1  REG32(STM32_RCC_BASE + 0x78)
-#define STM32_RCC_APB1SMENR2  REG32(STM32_RCC_BASE + 0x7C)
-#define STM32_RCC_APB2SMENR   REG32(STM32_RCC_BASE + 0x80)
-#define STM32_RCC_RESERVED6   REG32(STM32_RCC_BASE + 0x84)
-#define STM32_RCC_CCIPR       REG32(STM32_RCC_BASE + 0x88)
-#define STM32_RCC_RESERVED7   REG32(STM32_RCC_BASE + 0x8C)
-#define STM32_RCC_BDCR        REG32(STM32_RCC_BASE + 0x90)
-#define STM32_RCC_CSR         REG32(STM32_RCC_BASE + 0x94)
-#define STM32_RCC_CRRCR       REG32(STM32_RCC_BASE + 0x98)
+#define STM32_RCC_RESERVED REG32(STM32_RCC_BASE + 0x14)
+#define STM32_RCC_CIER REG32(STM32_RCC_BASE + 0x18)
+#define STM32_RCC_CIFR REG32(STM32_RCC_BASE + 0x1C)
+#define STM32_RCC_CICR REG32(STM32_RCC_BASE + 0x20)
+#define STM32_RCC_RESERVED0 REG32(STM32_RCC_BASE + 0x24)
+#define STM32_RCC_AHB1RSTR REG32(STM32_RCC_BASE + 0x28)
+#define STM32_RCC_AHB2RSTR REG32(STM32_RCC_BASE + 0x2C)
+#define STM32_RCC_AHB3RSTR REG32(STM32_RCC_BASE + 0x30)
+#define STM32_RCC_RESERVED1 REG32(STM32_RCC_BASE + 0x34)
+#define STM32_RCC_APB1RSTR1 REG32(STM32_RCC_BASE + 0x38)
+#define STM32_RCC_APB1RSTR2 REG32(STM32_RCC_BASE + 0x3C)
+#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x40)
+#define STM32_RCC_RESERVED2 REG32(STM32_RCC_BASE + 0x44)
+#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x48)
+#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x4C)
+#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x50)
+#define STM32_RCC_RESERVED3 REG32(STM32_RCC_BASE + 0x54)
+#define STM32_RCC_APB1ENR1 REG32(STM32_RCC_BASE + 0x58)
+#define STM32_RCC_APB1ENR2 REG32(STM32_RCC_BASE + 0x5C)
+#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x60)
+#define STM32_RCC_RESERVED4 REG32(STM32_RCC_BASE + 0x64)
+#define STM32_RCC_AHB1SMENR REG32(STM32_RCC_BASE + 0x68)
+#define STM32_RCC_AHB2SMENR REG32(STM32_RCC_BASE + 0x6C)
+#define STM32_RCC_AHB3SMENR REG32(STM32_RCC_BASE + 0x70)
+#define STM32_RCC_RESERVED5 REG32(STM32_RCC_BASE + 0x74)
+#define STM32_RCC_APB1SMENR1 REG32(STM32_RCC_BASE + 0x78)
+#define STM32_RCC_APB1SMENR2 REG32(STM32_RCC_BASE + 0x7C)
+#define STM32_RCC_APB2SMENR REG32(STM32_RCC_BASE + 0x80)
+#define STM32_RCC_RESERVED6 REG32(STM32_RCC_BASE + 0x84)
+#define STM32_RCC_CCIPR REG32(STM32_RCC_BASE + 0x88)
+#define STM32_RCC_RESERVED7 REG32(STM32_RCC_BASE + 0x8C)
+#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x90)
+#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x94)
+#define STM32_RCC_CRRCR REG32(STM32_RCC_BASE + 0x98)
 
 #define STM32_RCC_PLLSAI1_SUPPORT
 #define STM32_RCC_PLLP_SUPPORT
@@ -522,236 +520,236 @@
 #define STM32_RCC_PLLP_DIV_2_31_SUPPORT
 #define STM32_RCC_PLLSAI1P_DIV_2_31_SUPPORT
 
-#define STM32_RCC_APB1ENR                STM32_RCC_APB1ENR1
+#define STM32_RCC_APB1ENR STM32_RCC_APB1ENR1
 
 /********************  BIT DEFINITION FOR STM32_RCC_CR REGISTER  **************/
-#define STM32_RCC_CR_MSION_POS           0U
-#define STM32_RCC_CR_MSION_MSK           (0x1UL << STM32_RCC_CR_MSION_POS)
-#define STM32_RCC_CR_MSION               STM32_RCC_CR_MSION_MSK
-#define STM32_RCC_CR_MSIRDY_POS          1U
-#define STM32_RCC_CR_MSIRDY_MSK          (0x1UL << STM32_RCC_CR_MSIRDY_POS)
-#define STM32_RCC_CR_MSIRDY              STM32_RCC_CR_MSIRDY_MSK
-#define STM32_RCC_CR_MSIPLLEN_POS        2U
-#define STM32_RCC_CR_MSIPLLEN_MSK        (0x1UL << STM32_RCC_CR_MSIPLLEN_POS)
-#define STM32_RCC_CR_MSIPLLEN            STM32_RCC_CR_MSIPLLEN_MSK
-#define STM32_RCC_CR_MSIRGSEL_POS        3U
-#define STM32_RCC_CR_MSIRGSEL_MSK        (0x1UL << STM32_RCC_CR_MSIRGSEL_POS)
-#define STM32_RCC_CR_MSIRGSEL            STM32_RCC_CR_MSIRGSEL_MSK
+#define STM32_RCC_CR_MSION_POS 0U
+#define STM32_RCC_CR_MSION_MSK (0x1UL << STM32_RCC_CR_MSION_POS)
+#define STM32_RCC_CR_MSION STM32_RCC_CR_MSION_MSK
+#define STM32_RCC_CR_MSIRDY_POS 1U
+#define STM32_RCC_CR_MSIRDY_MSK (0x1UL << STM32_RCC_CR_MSIRDY_POS)
+#define STM32_RCC_CR_MSIRDY STM32_RCC_CR_MSIRDY_MSK
+#define STM32_RCC_CR_MSIPLLEN_POS 2U
+#define STM32_RCC_CR_MSIPLLEN_MSK (0x1UL << STM32_RCC_CR_MSIPLLEN_POS)
+#define STM32_RCC_CR_MSIPLLEN STM32_RCC_CR_MSIPLLEN_MSK
+#define STM32_RCC_CR_MSIRGSEL_POS 3U
+#define STM32_RCC_CR_MSIRGSEL_MSK (0x1UL << STM32_RCC_CR_MSIRGSEL_POS)
+#define STM32_RCC_CR_MSIRGSEL STM32_RCC_CR_MSIRGSEL_MSK
 
 /*!< MSIRANGE CONFIGURATION : 12 FREQUENCY RANGES AVAILABLE */
-#define STM32_RCC_CR_MSIRANGE_POS        4U
-#define STM32_RCC_CR_MSIRANGE_MSK        (0xFUL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE            STM32_RCC_CR_MSIRANGE_MSK
-#define STM32_RCC_CR_MSIRANGE_0          (0x0UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_1          (0x1UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_2          (0x2UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_3          (0x3UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_4          (0x4UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_5          (0x5UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_6          (0x6UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_7          (0x7UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_8          (0x8UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_9          (0x9UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_10         (0xAUL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_11         (0xBUL << STM32_RCC_CR_MSIRANGE_POS)
-
-#define STM32_RCC_CR_HSION_POS           8U
-#define STM32_RCC_CR_HSION_MSK           (0x1UL << STM32_RCC_CR_HSION_POS)
-#define STM32_RCC_CR_HSION               STM32_RCC_CR_HSION_MSK
-#define STM32_RCC_CR_HSIKERON_POS        9U
-#define STM32_RCC_CR_HSIKERON_MSK        (0x1UL << STM32_RCC_CR_HSIKERON_POS)
-#define STM32_RCC_CR_HSIKERON            STM32_RCC_CR_HSIKERON_MSK
-#define STM32_RCC_CR_HSIRDY_POS          10U
-#define STM32_RCC_CR_HSIRDY_MSK          (0x1UL << STM32_RCC_CR_HSIRDY_POS)
-#define STM32_RCC_CR_HSIRDY              STM32_RCC_CR_HSIRDY_MSK
-#define STM32_RCC_CR_HSIASFS_POS         11U
-#define STM32_RCC_CR_HSIASFS_MSK         (0x1UL << STM32_RCC_CR_HSIASFS_POS)
-#define STM32_RCC_CR_HSIASFS             STM32_RCC_CR_HSIASFS_MSK
-
-#define STM32_RCC_CR_HSEON_POS           16U
-#define STM32_RCC_CR_HSEON_MSK           (0x1UL << STM32_RCC_CR_HSEON_POS)
-#define STM32_RCC_CR_HSEON               STM32_RCC_CR_HSEON_MSK
-#define STM32_RCC_CR_HSERDY_POS          17U
-#define STM32_RCC_CR_HSERDY_MSK          (0x1UL << STM32_RCC_CR_HSERDY_POS)
-#define STM32_RCC_CR_HSERDY              STM32_RCC_CR_HSERDY_MSK
-#define STM32_RCC_CR_HSEBYP_POS          18U
-#define STM32_RCC_CR_HSEBYP_MSK          (0x1UL << STM32_RCC_CR_HSEBYP_POS)
-#define STM32_RCC_CR_HSEBYP              STM32_RCC_CR_HSEBYP_MSK
-#define STM32_RCC_CR_CSSON_POS           19U
-#define STM32_RCC_CR_CSSON_MSK           (0x1UL << STM32_RCC_CR_CSSON_POS)
-#define STM32_RCC_CR_CSSON               STM32_RCC_CR_CSSON_MSK
-
-#define STM32_RCC_CR_PLLON_POS           24U
-#define STM32_RCC_CR_PLLON_MSK           (0x1UL << STM32_RCC_CR_PLLON_POS)
-#define STM32_RCC_CR_PLLON               STM32_RCC_CR_PLLON_MSK
-#define STM32_RCC_CR_PLLRDY_POS          25U
-#define STM32_RCC_CR_PLLRDY_MSK          (0x1UL << STM32_RCC_CR_PLLRDY_POS)
-#define STM32_RCC_CR_PLLRDY              STM32_RCC_CR_PLLRDY_MSK
-#define STM32_RCC_CR_PLLSAI1ON_POS       26U
-#define STM32_RCC_CR_PLLSAI1ON_MSK       (0x1UL << STM32_RCC_CR_PLLSAI1ON_POS)
-#define STM32_RCC_CR_PLLSAI1ON           STM32_RCC_CR_PLLSAI1ON_MSK
-#define STM32_RCC_CR_PLLSAI1RDY_POS      27U
-#define STM32_RCC_CR_PLLSAI1RDY_MSK      (0x1UL << STM32_RCC_CR_PLLSAI1RDY_POS)
-#define STM32_RCC_CR_PLLSAI1RDY          STM32_RCC_CR_PLLSAI1RDY_MSK
+#define STM32_RCC_CR_MSIRANGE_POS 4U
+#define STM32_RCC_CR_MSIRANGE_MSK (0xFUL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE STM32_RCC_CR_MSIRANGE_MSK
+#define STM32_RCC_CR_MSIRANGE_0 (0x0UL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_1 (0x1UL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_2 (0x2UL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_3 (0x3UL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_4 (0x4UL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_5 (0x5UL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_6 (0x6UL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_7 (0x7UL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_8 (0x8UL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_9 (0x9UL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_10 (0xAUL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_11 (0xBUL << STM32_RCC_CR_MSIRANGE_POS)
+
+#define STM32_RCC_CR_HSION_POS 8U
+#define STM32_RCC_CR_HSION_MSK (0x1UL << STM32_RCC_CR_HSION_POS)
+#define STM32_RCC_CR_HSION STM32_RCC_CR_HSION_MSK
+#define STM32_RCC_CR_HSIKERON_POS 9U
+#define STM32_RCC_CR_HSIKERON_MSK (0x1UL << STM32_RCC_CR_HSIKERON_POS)
+#define STM32_RCC_CR_HSIKERON STM32_RCC_CR_HSIKERON_MSK
+#define STM32_RCC_CR_HSIRDY_POS 10U
+#define STM32_RCC_CR_HSIRDY_MSK (0x1UL << STM32_RCC_CR_HSIRDY_POS)
+#define STM32_RCC_CR_HSIRDY STM32_RCC_CR_HSIRDY_MSK
+#define STM32_RCC_CR_HSIASFS_POS 11U
+#define STM32_RCC_CR_HSIASFS_MSK (0x1UL << STM32_RCC_CR_HSIASFS_POS)
+#define STM32_RCC_CR_HSIASFS STM32_RCC_CR_HSIASFS_MSK
+
+#define STM32_RCC_CR_HSEON_POS 16U
+#define STM32_RCC_CR_HSEON_MSK (0x1UL << STM32_RCC_CR_HSEON_POS)
+#define STM32_RCC_CR_HSEON STM32_RCC_CR_HSEON_MSK
+#define STM32_RCC_CR_HSERDY_POS 17U
+#define STM32_RCC_CR_HSERDY_MSK (0x1UL << STM32_RCC_CR_HSERDY_POS)
+#define STM32_RCC_CR_HSERDY STM32_RCC_CR_HSERDY_MSK
+#define STM32_RCC_CR_HSEBYP_POS 18U
+#define STM32_RCC_CR_HSEBYP_MSK (0x1UL << STM32_RCC_CR_HSEBYP_POS)
+#define STM32_RCC_CR_HSEBYP STM32_RCC_CR_HSEBYP_MSK
+#define STM32_RCC_CR_CSSON_POS 19U
+#define STM32_RCC_CR_CSSON_MSK (0x1UL << STM32_RCC_CR_CSSON_POS)
+#define STM32_RCC_CR_CSSON STM32_RCC_CR_CSSON_MSK
+
+#define STM32_RCC_CR_PLLON_POS 24U
+#define STM32_RCC_CR_PLLON_MSK (0x1UL << STM32_RCC_CR_PLLON_POS)
+#define STM32_RCC_CR_PLLON STM32_RCC_CR_PLLON_MSK
+#define STM32_RCC_CR_PLLRDY_POS 25U
+#define STM32_RCC_CR_PLLRDY_MSK (0x1UL << STM32_RCC_CR_PLLRDY_POS)
+#define STM32_RCC_CR_PLLRDY STM32_RCC_CR_PLLRDY_MSK
+#define STM32_RCC_CR_PLLSAI1ON_POS 26U
+#define STM32_RCC_CR_PLLSAI1ON_MSK (0x1UL << STM32_RCC_CR_PLLSAI1ON_POS)
+#define STM32_RCC_CR_PLLSAI1ON STM32_RCC_CR_PLLSAI1ON_MSK
+#define STM32_RCC_CR_PLLSAI1RDY_POS 27U
+#define STM32_RCC_CR_PLLSAI1RDY_MSK (0x1UL << STM32_RCC_CR_PLLSAI1RDY_POS)
+#define STM32_RCC_CR_PLLSAI1RDY STM32_RCC_CR_PLLSAI1RDY_MSK
 
 /********************  BIT DEFINITION FOR STM32_RCC_ICSCR REGISTER  ***********/
 /*!< MSICAL CONFIGURATION */
-#define STM32_RCC_ICSCR_MSICAL_POS       0U
-#define STM32_RCC_ICSCR_MSICAL_MSK       (0xFFUL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL           STM32_RCC_ICSCR_MSICAL_MSK
-#define STM32_RCC_ICSCR_MSICAL_0         (0x01UL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL_1         (0x02UL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL_2         (0x04UL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL_3         (0x08UL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL_4         (0x10UL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL_5         (0x20UL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL_6         (0x40UL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL_7         (0x80UL << STM32_RCC_ICSCR_MSICAL_POS)
+#define STM32_RCC_ICSCR_MSICAL_POS 0U
+#define STM32_RCC_ICSCR_MSICAL_MSK (0xFFUL << STM32_RCC_ICSCR_MSICAL_POS)
+#define STM32_RCC_ICSCR_MSICAL STM32_RCC_ICSCR_MSICAL_MSK
+#define STM32_RCC_ICSCR_MSICAL_0 (0x01UL << STM32_RCC_ICSCR_MSICAL_POS)
+#define STM32_RCC_ICSCR_MSICAL_1 (0x02UL << STM32_RCC_ICSCR_MSICAL_POS)
+#define STM32_RCC_ICSCR_MSICAL_2 (0x04UL << STM32_RCC_ICSCR_MSICAL_POS)
+#define STM32_RCC_ICSCR_MSICAL_3 (0x08UL << STM32_RCC_ICSCR_MSICAL_POS)
+#define STM32_RCC_ICSCR_MSICAL_4 (0x10UL << STM32_RCC_ICSCR_MSICAL_POS)
+#define STM32_RCC_ICSCR_MSICAL_5 (0x20UL << STM32_RCC_ICSCR_MSICAL_POS)
+#define STM32_RCC_ICSCR_MSICAL_6 (0x40UL << STM32_RCC_ICSCR_MSICAL_POS)
+#define STM32_RCC_ICSCR_MSICAL_7 (0x80UL << STM32_RCC_ICSCR_MSICAL_POS)
 
 /*!< MSITRIM CONFIGURATION */
-#define STM32_RCC_ICSCR_MSITRIM_POS      8U
-#define STM32_RCC_ICSCR_MSITRIM_MSK      (0xFFUL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM          STM32_RCC_ICSCR_MSITRIM_MSK
-#define STM32_RCC_ICSCR_MSITRIM_0        (0x01UL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM_1        (0x02UL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM_2        (0x04UL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM_3        (0x08UL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM_4        (0x10UL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM_5        (0x20UL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM_6        (0x40UL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM_7        (0x80UL << STM32_RCC_ICSCR_MSITRIM_POS)
+#define STM32_RCC_ICSCR_MSITRIM_POS 8U
+#define STM32_RCC_ICSCR_MSITRIM_MSK (0xFFUL << STM32_RCC_ICSCR_MSITRIM_POS)
+#define STM32_RCC_ICSCR_MSITRIM STM32_RCC_ICSCR_MSITRIM_MSK
+#define STM32_RCC_ICSCR_MSITRIM_0 (0x01UL << STM32_RCC_ICSCR_MSITRIM_POS)
+#define STM32_RCC_ICSCR_MSITRIM_1 (0x02UL << STM32_RCC_ICSCR_MSITRIM_POS)
+#define STM32_RCC_ICSCR_MSITRIM_2 (0x04UL << STM32_RCC_ICSCR_MSITRIM_POS)
+#define STM32_RCC_ICSCR_MSITRIM_3 (0x08UL << STM32_RCC_ICSCR_MSITRIM_POS)
+#define STM32_RCC_ICSCR_MSITRIM_4 (0x10UL << STM32_RCC_ICSCR_MSITRIM_POS)
+#define STM32_RCC_ICSCR_MSITRIM_5 (0x20UL << STM32_RCC_ICSCR_MSITRIM_POS)
+#define STM32_RCC_ICSCR_MSITRIM_6 (0x40UL << STM32_RCC_ICSCR_MSITRIM_POS)
+#define STM32_RCC_ICSCR_MSITRIM_7 (0x80UL << STM32_RCC_ICSCR_MSITRIM_POS)
 
 /*!< HSICAL CONFIGURATION */
-#define STM32_RCC_ICSCR_HSICAL_POS       16U
-#define STM32_RCC_ICSCR_HSICAL_MSK       (0xFFUL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL           STM32_RCC_ICSCR_HSICAL_MSK
-#define STM32_RCC_ICSCR_HSICAL_0         (0x01UL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL_1         (0x02UL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL_2         (0x04UL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL_3         (0x08UL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL_4         (0x10UL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL_5         (0x20UL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL_6         (0x40UL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL_7         (0x80UL << STM32_RCC_ICSCR_HSICAL_POS)
+#define STM32_RCC_ICSCR_HSICAL_POS 16U
+#define STM32_RCC_ICSCR_HSICAL_MSK (0xFFUL << STM32_RCC_ICSCR_HSICAL_POS)
+#define STM32_RCC_ICSCR_HSICAL STM32_RCC_ICSCR_HSICAL_MSK
+#define STM32_RCC_ICSCR_HSICAL_0 (0x01UL << STM32_RCC_ICSCR_HSICAL_POS)
+#define STM32_RCC_ICSCR_HSICAL_1 (0x02UL << STM32_RCC_ICSCR_HSICAL_POS)
+#define STM32_RCC_ICSCR_HSICAL_2 (0x04UL << STM32_RCC_ICSCR_HSICAL_POS)
+#define STM32_RCC_ICSCR_HSICAL_3 (0x08UL << STM32_RCC_ICSCR_HSICAL_POS)
+#define STM32_RCC_ICSCR_HSICAL_4 (0x10UL << STM32_RCC_ICSCR_HSICAL_POS)
+#define STM32_RCC_ICSCR_HSICAL_5 (0x20UL << STM32_RCC_ICSCR_HSICAL_POS)
+#define STM32_RCC_ICSCR_HSICAL_6 (0x40UL << STM32_RCC_ICSCR_HSICAL_POS)
+#define STM32_RCC_ICSCR_HSICAL_7 (0x80UL << STM32_RCC_ICSCR_HSICAL_POS)
 
 /*!< HSITRIM CONFIGURATION */
-#define STM32_RCC_ICSCR_HSITRIM_POS      24U
-#define STM32_RCC_ICSCR_HSITRIM_MSK      (0x1FUL << STM32_RCC_ICSCR_HSITRIM_POS)
-#define STM32_RCC_ICSCR_HSITRIM          STM32_RCC_ICSCR_HSITRIM_MSK
-#define STM32_RCC_ICSCR_HSITRIM_0        (0x01UL << STM32_RCC_ICSCR_HSITRIM_POS)
-#define STM32_RCC_ICSCR_HSITRIM_1        (0x02UL << STM32_RCC_ICSCR_HSITRIM_POS)
-#define STM32_RCC_ICSCR_HSITRIM_2        (0x04UL << STM32_RCC_ICSCR_HSITRIM_POS)
-#define STM32_RCC_ICSCR_HSITRIM_3        (0x08UL << STM32_RCC_ICSCR_HSITRIM_POS)
-#define STM32_RCC_ICSCR_HSITRIM_4        (0x10UL << STM32_RCC_ICSCR_HSITRIM_POS)
+#define STM32_RCC_ICSCR_HSITRIM_POS 24U
+#define STM32_RCC_ICSCR_HSITRIM_MSK (0x1FUL << STM32_RCC_ICSCR_HSITRIM_POS)
+#define STM32_RCC_ICSCR_HSITRIM STM32_RCC_ICSCR_HSITRIM_MSK
+#define STM32_RCC_ICSCR_HSITRIM_0 (0x01UL << STM32_RCC_ICSCR_HSITRIM_POS)
+#define STM32_RCC_ICSCR_HSITRIM_1 (0x02UL << STM32_RCC_ICSCR_HSITRIM_POS)
+#define STM32_RCC_ICSCR_HSITRIM_2 (0x04UL << STM32_RCC_ICSCR_HSITRIM_POS)
+#define STM32_RCC_ICSCR_HSITRIM_3 (0x08UL << STM32_RCC_ICSCR_HSITRIM_POS)
+#define STM32_RCC_ICSCR_HSITRIM_4 (0x10UL << STM32_RCC_ICSCR_HSITRIM_POS)
 
 /****************  BIT DEFINITION FOR STM32_RCC_CFGR REGISTER  **************/
 /*!< SW CONFIGURATION */
-#define STM32_RCC_CFGR_SW_POS            0U
-#define STM32_RCC_CFGR_SW_MSK            (0x3UL << STM32_RCC_CFGR_SW_POS)
-#define STM32_RCC_CFGR_SW                STM32_RCC_CFGR_SW_MSK
-#define STM32_RCC_CFGR_SW_0              (0x1UL << STM32_RCC_CFGR_SW_POS)
-#define STM32_RCC_CFGR_SW_1              (0x2UL << STM32_RCC_CFGR_SW_POS)
+#define STM32_RCC_CFGR_SW_POS 0U
+#define STM32_RCC_CFGR_SW_MSK (0x3UL << STM32_RCC_CFGR_SW_POS)
+#define STM32_RCC_CFGR_SW STM32_RCC_CFGR_SW_MSK
+#define STM32_RCC_CFGR_SW_0 (0x1UL << STM32_RCC_CFGR_SW_POS)
+#define STM32_RCC_CFGR_SW_1 (0x2UL << STM32_RCC_CFGR_SW_POS)
 
-#define STM32_RCC_CFGR_SW_MSI            (0x00000000UL)
-#define STM32_RCC_CFGR_SW_HSI            (0x00000001UL)
-#define STM32_RCC_CFGR_SW_HSE            (0x00000002UL)
-#define STM32_RCC_CFGR_SW_PLL            (0x00000003UL)
+#define STM32_RCC_CFGR_SW_MSI (0x00000000UL)
+#define STM32_RCC_CFGR_SW_HSI (0x00000001UL)
+#define STM32_RCC_CFGR_SW_HSE (0x00000002UL)
+#define STM32_RCC_CFGR_SW_PLL (0x00000003UL)
 
 /*!< SWS CONFIGURATION */
-#define STM32_RCC_CFGR_SWS_POS           2U
-#define STM32_RCC_CFGR_SWS_MSK           (0x3UL << STM32_RCC_CFGR_SWS_POS)
-#define STM32_RCC_CFGR_SWS               STM32_RCC_CFGR_SWS_MSK
-#define STM32_RCC_CFGR_SWS_0             (0x1UL << STM32_RCC_CFGR_SWS_POS)
-#define STM32_RCC_CFGR_SWS_1             (0x2UL << STM32_RCC_CFGR_SWS_POS)
+#define STM32_RCC_CFGR_SWS_POS 2U
+#define STM32_RCC_CFGR_SWS_MSK (0x3UL << STM32_RCC_CFGR_SWS_POS)
+#define STM32_RCC_CFGR_SWS STM32_RCC_CFGR_SWS_MSK
+#define STM32_RCC_CFGR_SWS_0 (0x1UL << STM32_RCC_CFGR_SWS_POS)
+#define STM32_RCC_CFGR_SWS_1 (0x2UL << STM32_RCC_CFGR_SWS_POS)
 
-#define STM32_RCC_CFGR_SWS_MSI           (0x00000000UL)
-#define STM32_RCC_CFGR_SWS_HSI           (0x00000004UL)
-#define STM32_RCC_CFGR_SWS_HSE           (0x00000008UL)
-#define STM32_RCC_CFGR_SWS_PLL           (0x0000000CUL)
+#define STM32_RCC_CFGR_SWS_MSI (0x00000000UL)
+#define STM32_RCC_CFGR_SWS_HSI (0x00000004UL)
+#define STM32_RCC_CFGR_SWS_HSE (0x00000008UL)
+#define STM32_RCC_CFGR_SWS_PLL (0x0000000CUL)
 
 /*!< HPRE CONFIGURATION */
-#define STM32_RCC_CFGR_HPRE_POS          4U
-#define STM32_RCC_CFGR_HPRE_MSK          (0xFUL << STM32_RCC_CFGR_HPRE_POS)
-#define STM32_RCC_CFGR_HPRE              STM32_RCC_CFGR_HPRE_MSK
-#define STM32_RCC_CFGR_HPRE_0            (0x1UL << STM32_RCC_CFGR_HPRE_POS)
-#define STM32_RCC_CFGR_HPRE_1            (0x2UL << STM32_RCC_CFGR_HPRE_POS)
-#define STM32_RCC_CFGR_HPRE_2            (0x4UL << STM32_RCC_CFGR_HPRE_POS)
-#define STM32_RCC_CFGR_HPRE_3            (0x8UL << STM32_RCC_CFGR_HPRE_POS)
-
-#define STM32_RCC_CFGR_HPRE_DIV1         (0x00000000UL)
-#define STM32_RCC_CFGR_HPRE_DIV2         (0x00000080UL)
-#define STM32_RCC_CFGR_HPRE_DIV4         (0x00000090UL)
-#define STM32_RCC_CFGR_HPRE_DIV8         (0x000000A0UL)
-#define STM32_RCC_CFGR_HPRE_DIV16        (0x000000B0UL)
-#define STM32_RCC_CFGR_HPRE_DIV64        (0x000000C0UL)
-#define STM32_RCC_CFGR_HPRE_DIV128       (0x000000D0UL)
-#define STM32_RCC_CFGR_HPRE_DIV256       (0x000000E0UL)
-#define STM32_RCC_CFGR_HPRE_DIV512       (0x000000F0UL)
+#define STM32_RCC_CFGR_HPRE_POS 4U
+#define STM32_RCC_CFGR_HPRE_MSK (0xFUL << STM32_RCC_CFGR_HPRE_POS)
+#define STM32_RCC_CFGR_HPRE STM32_RCC_CFGR_HPRE_MSK
+#define STM32_RCC_CFGR_HPRE_0 (0x1UL << STM32_RCC_CFGR_HPRE_POS)
+#define STM32_RCC_CFGR_HPRE_1 (0x2UL << STM32_RCC_CFGR_HPRE_POS)
+#define STM32_RCC_CFGR_HPRE_2 (0x4UL << STM32_RCC_CFGR_HPRE_POS)
+#define STM32_RCC_CFGR_HPRE_3 (0x8UL << STM32_RCC_CFGR_HPRE_POS)
+
+#define STM32_RCC_CFGR_HPRE_DIV1 (0x00000000UL)
+#define STM32_RCC_CFGR_HPRE_DIV2 (0x00000080UL)
+#define STM32_RCC_CFGR_HPRE_DIV4 (0x00000090UL)
+#define STM32_RCC_CFGR_HPRE_DIV8 (0x000000A0UL)
+#define STM32_RCC_CFGR_HPRE_DIV16 (0x000000B0UL)
+#define STM32_RCC_CFGR_HPRE_DIV64 (0x000000C0UL)
+#define STM32_RCC_CFGR_HPRE_DIV128 (0x000000D0UL)
+#define STM32_RCC_CFGR_HPRE_DIV256 (0x000000E0UL)
+#define STM32_RCC_CFGR_HPRE_DIV512 (0x000000F0UL)
 
 /*!< PPRE1 CONFIGURATION */
-#define STM32_RCC_CFGR_PPRE1_POS         8U
-#define STM32_RCC_CFGR_PPRE1_MSK         (0x7UL << STM32_RCC_CFGR_PPRE1_POS)
-#define STM32_RCC_CFGR_PPRE1             STM32_RCC_CFGR_PPRE1_MSK
-#define STM32_RCC_CFGR_PPRE1_0           (0x1UL << STM32_RCC_CFGR_PPRE1_POS)
-#define STM32_RCC_CFGR_PPRE1_1           (0x2UL << STM32_RCC_CFGR_PPRE1_POS)
-#define STM32_RCC_CFGR_PPRE1_2           (0x4UL << STM32_RCC_CFGR_PPRE1_POS)
-
-#define STM32_RCC_CFGR_PPRE1_DIV1        (0x00000000UL)
-#define STM32_RCC_CFGR_PPRE1_DIV2        (0x00000400UL)
-#define STM32_RCC_CFGR_PPRE1_DIV4        (0x00000500UL)
-#define STM32_RCC_CFGR_PPRE1_DIV8        (0x00000600UL)
-#define STM32_RCC_CFGR_PPRE1_DIV16       (0x00000700UL)
+#define STM32_RCC_CFGR_PPRE1_POS 8U
+#define STM32_RCC_CFGR_PPRE1_MSK (0x7UL << STM32_RCC_CFGR_PPRE1_POS)
+#define STM32_RCC_CFGR_PPRE1 STM32_RCC_CFGR_PPRE1_MSK
+#define STM32_RCC_CFGR_PPRE1_0 (0x1UL << STM32_RCC_CFGR_PPRE1_POS)
+#define STM32_RCC_CFGR_PPRE1_1 (0x2UL << STM32_RCC_CFGR_PPRE1_POS)
+#define STM32_RCC_CFGR_PPRE1_2 (0x4UL << STM32_RCC_CFGR_PPRE1_POS)
+
+#define STM32_RCC_CFGR_PPRE1_DIV1 (0x00000000UL)
+#define STM32_RCC_CFGR_PPRE1_DIV2 (0x00000400UL)
+#define STM32_RCC_CFGR_PPRE1_DIV4 (0x00000500UL)
+#define STM32_RCC_CFGR_PPRE1_DIV8 (0x00000600UL)
+#define STM32_RCC_CFGR_PPRE1_DIV16 (0x00000700UL)
 
 /*!< PPRE2 CONFIGURATION */
-#define STM32_RCC_CFGR_PPRE2_POS         11U
-#define STM32_RCC_CFGR_PPRE2_MSK         (0x7UL << STM32_RCC_CFGR_PPRE2_POS)
-#define STM32_RCC_CFGR_PPRE2             STM32_RCC_CFGR_PPRE2_MSK
-#define STM32_RCC_CFGR_PPRE2_0           (0x1UL << STM32_RCC_CFGR_PPRE2_POS)
-#define STM32_RCC_CFGR_PPRE2_1           (0x2UL << STM32_RCC_CFGR_PPRE2_POS)
-#define STM32_RCC_CFGR_PPRE2_2           (0x4UL << STM32_RCC_CFGR_PPRE2_POS)
-
-#define STM32_RCC_CFGR_PPRE2_DIV1        (0x00000000UL)
-#define STM32_RCC_CFGR_PPRE2_DIV2        (0x00002000UL)
-#define STM32_RCC_CFGR_PPRE2_DIV4        (0x00002800UL)
-#define STM32_RCC_CFGR_PPRE2_DIV8        (0x00003000UL)
-#define STM32_RCC_CFGR_PPRE2_DIV16       (0x00003800UL)
-
-#define STM32_RCC_CFGR_STOPWUCK_POS      15U
-#define STM32_RCC_CFGR_STOPWUCK_MSK      (0x1UL << STM32_RCC_CFGR_STOPWUCK_POS)
-#define STM32_RCC_CFGR_STOPWUCK          STM32_RCC_CFGR_STOPWUCK_MSK
+#define STM32_RCC_CFGR_PPRE2_POS 11U
+#define STM32_RCC_CFGR_PPRE2_MSK (0x7UL << STM32_RCC_CFGR_PPRE2_POS)
+#define STM32_RCC_CFGR_PPRE2 STM32_RCC_CFGR_PPRE2_MSK
+#define STM32_RCC_CFGR_PPRE2_0 (0x1UL << STM32_RCC_CFGR_PPRE2_POS)
+#define STM32_RCC_CFGR_PPRE2_1 (0x2UL << STM32_RCC_CFGR_PPRE2_POS)
+#define STM32_RCC_CFGR_PPRE2_2 (0x4UL << STM32_RCC_CFGR_PPRE2_POS)
+
+#define STM32_RCC_CFGR_PPRE2_DIV1 (0x00000000UL)
+#define STM32_RCC_CFGR_PPRE2_DIV2 (0x00002000UL)
+#define STM32_RCC_CFGR_PPRE2_DIV4 (0x00002800UL)
+#define STM32_RCC_CFGR_PPRE2_DIV8 (0x00003000UL)
+#define STM32_RCC_CFGR_PPRE2_DIV16 (0x00003800UL)
+
+#define STM32_RCC_CFGR_STOPWUCK_POS 15U
+#define STM32_RCC_CFGR_STOPWUCK_MSK (0x1UL << STM32_RCC_CFGR_STOPWUCK_POS)
+#define STM32_RCC_CFGR_STOPWUCK STM32_RCC_CFGR_STOPWUCK_MSK
 
 /*!< MCOSEL CONFIGURATION */
-#define STM32_RCC_CFGR_MCOSEL_POS        24U
-#define STM32_RCC_CFGR_MCOSEL_MSK        (0xFUL << STM32_RCC_CFGR_MCOSEL_POS)
-#define STM32_RCC_CFGR_MCOSEL            STM32_RCC_CFGR_MCOSEL_MSK
-#define STM32_RCC_CFGR_MCOSEL_0          (0x1UL << STM32_RCC_CFGR_MCOSEL_POS)
-#define STM32_RCC_CFGR_MCOSEL_1          (0x2UL << STM32_RCC_CFGR_MCOSEL_POS)
-#define STM32_RCC_CFGR_MCOSEL_2          (0x4UL << STM32_RCC_CFGR_MCOSEL_POS)
-#define STM32_RCC_CFGR_MCOSEL_3          (0x8UL << STM32_RCC_CFGR_MCOSEL_POS)
-
-#define STM32_RCC_CFGR_MCOPRE_POS        28U
-#define STM32_RCC_CFGR_MCOPRE_MSK        (0x7UL << STM32_RCC_CFGR_MCOPRE_POS)
-#define STM32_RCC_CFGR_MCOPRE            STM32_RCC_CFGR_MCOPRE_MSK
-#define STM32_RCC_CFGR_MCOPRE_0          (0x1UL << STM32_RCC_CFGR_MCOPRE_POS)
-#define STM32_RCC_CFGR_MCOPRE_1          (0x2UL << STM32_RCC_CFGR_MCOPRE_POS)
-#define STM32_RCC_CFGR_MCOPRE_2          (0x4UL << STM32_RCC_CFGR_MCOPRE_POS)
-
-#define STM32_RCC_CFGR_MCOPRE_DIV1       (0x00000000UL)
-#define STM32_RCC_CFGR_MCOPRE_DIV2       (0x10000000UL)
-#define STM32_RCC_CFGR_MCOPRE_DIV4       (0x20000000UL)
-#define STM32_RCC_CFGR_MCOPRE_DIV8       (0x30000000UL)
-#define STM32_RCC_CFGR_MCOPRE_DIV16      (0x40000000UL)
+#define STM32_RCC_CFGR_MCOSEL_POS 24U
+#define STM32_RCC_CFGR_MCOSEL_MSK (0xFUL << STM32_RCC_CFGR_MCOSEL_POS)
+#define STM32_RCC_CFGR_MCOSEL STM32_RCC_CFGR_MCOSEL_MSK
+#define STM32_RCC_CFGR_MCOSEL_0 (0x1UL << STM32_RCC_CFGR_MCOSEL_POS)
+#define STM32_RCC_CFGR_MCOSEL_1 (0x2UL << STM32_RCC_CFGR_MCOSEL_POS)
+#define STM32_RCC_CFGR_MCOSEL_2 (0x4UL << STM32_RCC_CFGR_MCOSEL_POS)
+#define STM32_RCC_CFGR_MCOSEL_3 (0x8UL << STM32_RCC_CFGR_MCOSEL_POS)
+
+#define STM32_RCC_CFGR_MCOPRE_POS 28U
+#define STM32_RCC_CFGR_MCOPRE_MSK (0x7UL << STM32_RCC_CFGR_MCOPRE_POS)
+#define STM32_RCC_CFGR_MCOPRE STM32_RCC_CFGR_MCOPRE_MSK
+#define STM32_RCC_CFGR_MCOPRE_0 (0x1UL << STM32_RCC_CFGR_MCOPRE_POS)
+#define STM32_RCC_CFGR_MCOPRE_1 (0x2UL << STM32_RCC_CFGR_MCOPRE_POS)
+#define STM32_RCC_CFGR_MCOPRE_2 (0x4UL << STM32_RCC_CFGR_MCOPRE_POS)
+
+#define STM32_RCC_CFGR_MCOPRE_DIV1 (0x00000000UL)
+#define STM32_RCC_CFGR_MCOPRE_DIV2 (0x10000000UL)
+#define STM32_RCC_CFGR_MCOPRE_DIV4 (0x20000000UL)
+#define STM32_RCC_CFGR_MCOPRE_DIV8 (0x30000000UL)
+#define STM32_RCC_CFGR_MCOPRE_DIV16 (0x40000000UL)
 
 /* LEGACY ALIASES */
-#define STM32_RCC_CFGR_MCO_PRE           STM32_RCC_CFGR_MCOPRE
-#define STM32_RCC_CFGR_MCO_PRE_1         STM32_RCC_CFGR_MCOPRE_DIV1
-#define STM32_RCC_CFGR_MCO_PRE_2         STM32_RCC_CFGR_MCOPRE_DIV2
-#define STM32_RCC_CFGR_MCO_PRE_4         STM32_RCC_CFGR_MCOPRE_DIV4
-#define STM32_RCC_CFGR_MCO_PRE_8         STM32_RCC_CFGR_MCOPRE_DIV8
-#define STM32_RCC_CFGR_MCO_PRE_16        STM32_RCC_CFGR_MCOPRE_DIV16
+#define STM32_RCC_CFGR_MCO_PRE STM32_RCC_CFGR_MCOPRE
+#define STM32_RCC_CFGR_MCO_PRE_1 STM32_RCC_CFGR_MCOPRE_DIV1
+#define STM32_RCC_CFGR_MCO_PRE_2 STM32_RCC_CFGR_MCOPRE_DIV2
+#define STM32_RCC_CFGR_MCO_PRE_4 STM32_RCC_CFGR_MCOPRE_DIV4
+#define STM32_RCC_CFGR_MCO_PRE_8 STM32_RCC_CFGR_MCOPRE_DIV8
+#define STM32_RCC_CFGR_MCO_PRE_16 STM32_RCC_CFGR_MCOPRE_DIV16
 
 /****************  BIT DEFINITION FOR STM32_RCC_PLLCFGR REGISTER  ***********/
-#define STM32_RCC_PLLCFGR_PLLSRC_POS     0U
+#define STM32_RCC_PLLCFGR_PLLSRC_POS 0U
 #define STM32_RCC_PLLCFGR_PLLSRC_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLSRC_POS)
 #define STM32_RCC_PLLCFGR_PLLSRC STM32_RCC_PLLCFGR_PLLSRC_MSK
 
@@ -766,59 +764,59 @@
 #define STM32_RCC_PLLCFGR_PLLSRC_HSE_POS 0U
 #define STM32_RCC_PLLCFGR_PLLSRC_HSE_MSK \
 	(0x3UL << STM32_RCC_PLLCFGR_PLLSRC_HSE_POS)
-#define STM32_RCC_PLLCFGR_PLLSRC_HSE     STM32_RCC_PLLCFGR_PLLSRC_HSE_MSK
-
-#define STM32_RCC_PLLCFGR_PLLM_POS       4U
-#define STM32_RCC_PLLCFGR_PLLM_MSK       (0x7UL << STM32_RCC_PLLCFGR_PLLM_POS)
-#define STM32_RCC_PLLCFGR_PLLM           STM32_RCC_PLLCFGR_PLLM_MSK
-#define STM32_RCC_PLLCFGR_PLLM_0         (0x1UL << STM32_RCC_PLLCFGR_PLLM_POS)
-#define STM32_RCC_PLLCFGR_PLLM_1         (0x2UL << STM32_RCC_PLLCFGR_PLLM_POS)
-#define STM32_RCC_PLLCFGR_PLLM_2         (0x4UL << STM32_RCC_PLLCFGR_PLLM_POS)
-
-#define STM32_RCC_PLLCFGR_PLLN_POS       8U
-#define STM32_RCC_PLLCFGR_PLLN_MSK       (0x7FUL << STM32_RCC_PLLCFGR_PLLN_POS)
-#define STM32_RCC_PLLCFGR_PLLN           STM32_RCC_PLLCFGR_PLLN_MSK
-#define STM32_RCC_PLLCFGR_PLLN_0         (0x01UL << STM32_RCC_PLLCFGR_PLLN_POS)
-#define STM32_RCC_PLLCFGR_PLLN_1         (0x02UL << STM32_RCC_PLLCFGR_PLLN_POS)
-#define STM32_RCC_PLLCFGR_PLLN_2         (0x04UL << STM32_RCC_PLLCFGR_PLLN_POS)
-#define STM32_RCC_PLLCFGR_PLLN_3         (0x08UL << STM32_RCC_PLLCFGR_PLLN_POS)
-#define STM32_RCC_PLLCFGR_PLLN_4         (0x10UL << STM32_RCC_PLLCFGR_PLLN_POS)
-#define STM32_RCC_PLLCFGR_PLLN_5         (0x20UL << STM32_RCC_PLLCFGR_PLLN_POS)
-#define STM32_RCC_PLLCFGR_PLLN_6         (0x40UL << STM32_RCC_PLLCFGR_PLLN_POS)
-
-#define STM32_RCC_PLLCFGR_PLLPEN_POS     16U
-#define STM32_RCC_PLLCFGR_PLLPEN_MSK     (0x1UL << STM32_RCC_PLLCFGR_PLLPEN_POS)
-#define STM32_RCC_PLLCFGR_PLLPEN         STM32_RCC_PLLCFGR_PLLPEN_MSK
-#define STM32_RCC_PLLCFGR_PLLP_POS       17U
-#define STM32_RCC_PLLCFGR_PLLP_MSK       (0x1UL << STM32_RCC_PLLCFGR_PLLP_POS)
-#define STM32_RCC_PLLCFGR_PLLP           STM32_RCC_PLLCFGR_PLLP_MSK
-#define STM32_RCC_PLLCFGR_PLLQEN_POS     20U
-#define STM32_RCC_PLLCFGR_PLLQEN_MSK     (0x1UL << STM32_RCC_PLLCFGR_PLLQEN_POS)
-#define STM32_RCC_PLLCFGR_PLLQEN         STM32_RCC_PLLCFGR_PLLQEN_MSK
-
-#define STM32_RCC_PLLCFGR_PLLQ_POS       21U
-#define STM32_RCC_PLLCFGR_PLLQ_MSK       (0x3UL << STM32_RCC_PLLCFGR_PLLQ_POS)
-#define STM32_RCC_PLLCFGR_PLLQ           STM32_RCC_PLLCFGR_PLLQ_MSK
-#define STM32_RCC_PLLCFGR_PLLQ_0         (0x1UL << STM32_RCC_PLLCFGR_PLLQ_POS)
-#define STM32_RCC_PLLCFGR_PLLQ_1         (0x2UL << STM32_RCC_PLLCFGR_PLLQ_POS)
-
-#define STM32_RCC_PLLCFGR_PLLREN_POS     24U
-#define STM32_RCC_PLLCFGR_PLLREN_MSK     (0x1UL << STM32_RCC_PLLCFGR_PLLREN_POS)
-#define STM32_RCC_PLLCFGR_PLLREN         STM32_RCC_PLLCFGR_PLLREN_MSK
-#define STM32_RCC_PLLCFGR_PLLR_POS       25U
-#define STM32_RCC_PLLCFGR_PLLR_MSK       (0x3UL << STM32_RCC_PLLCFGR_PLLR_POS)
-#define STM32_RCC_PLLCFGR_PLLR           STM32_RCC_PLLCFGR_PLLR_MSK
-#define STM32_RCC_PLLCFGR_PLLR_0         (0x1UL << STM32_RCC_PLLCFGR_PLLR_POS)
-#define STM32_RCC_PLLCFGR_PLLR_1         (0x2UL << STM32_RCC_PLLCFGR_PLLR_POS)
-
-#define STM32_RCC_PLLCFGR_PLLPDIV_POS  27U
-#define STM32_RCC_PLLCFGR_PLLPDIV_MSK  (0x1FUL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
-#define STM32_RCC_PLLCFGR_PLLPDIV      STM32_RCC_PLLCFGR_PLLPDIV_MSK
-#define STM32_RCC_PLLCFGR_PLLPDIV_0    (0x01UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
-#define STM32_RCC_PLLCFGR_PLLPDIV_1    (0x02UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
-#define STM32_RCC_PLLCFGR_PLLPDIV_2    (0x04UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
-#define STM32_RCC_PLLCFGR_PLLPDIV_3    (0x08UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
-#define STM32_RCC_PLLCFGR_PLLPDIV_4    (0x10UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
+#define STM32_RCC_PLLCFGR_PLLSRC_HSE STM32_RCC_PLLCFGR_PLLSRC_HSE_MSK
+
+#define STM32_RCC_PLLCFGR_PLLM_POS 4U
+#define STM32_RCC_PLLCFGR_PLLM_MSK (0x7UL << STM32_RCC_PLLCFGR_PLLM_POS)
+#define STM32_RCC_PLLCFGR_PLLM STM32_RCC_PLLCFGR_PLLM_MSK
+#define STM32_RCC_PLLCFGR_PLLM_0 (0x1UL << STM32_RCC_PLLCFGR_PLLM_POS)
+#define STM32_RCC_PLLCFGR_PLLM_1 (0x2UL << STM32_RCC_PLLCFGR_PLLM_POS)
+#define STM32_RCC_PLLCFGR_PLLM_2 (0x4UL << STM32_RCC_PLLCFGR_PLLM_POS)
+
+#define STM32_RCC_PLLCFGR_PLLN_POS 8U
+#define STM32_RCC_PLLCFGR_PLLN_MSK (0x7FUL << STM32_RCC_PLLCFGR_PLLN_POS)
+#define STM32_RCC_PLLCFGR_PLLN STM32_RCC_PLLCFGR_PLLN_MSK
+#define STM32_RCC_PLLCFGR_PLLN_0 (0x01UL << STM32_RCC_PLLCFGR_PLLN_POS)
+#define STM32_RCC_PLLCFGR_PLLN_1 (0x02UL << STM32_RCC_PLLCFGR_PLLN_POS)
+#define STM32_RCC_PLLCFGR_PLLN_2 (0x04UL << STM32_RCC_PLLCFGR_PLLN_POS)
+#define STM32_RCC_PLLCFGR_PLLN_3 (0x08UL << STM32_RCC_PLLCFGR_PLLN_POS)
+#define STM32_RCC_PLLCFGR_PLLN_4 (0x10UL << STM32_RCC_PLLCFGR_PLLN_POS)
+#define STM32_RCC_PLLCFGR_PLLN_5 (0x20UL << STM32_RCC_PLLCFGR_PLLN_POS)
+#define STM32_RCC_PLLCFGR_PLLN_6 (0x40UL << STM32_RCC_PLLCFGR_PLLN_POS)
+
+#define STM32_RCC_PLLCFGR_PLLPEN_POS 16U
+#define STM32_RCC_PLLCFGR_PLLPEN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLPEN_POS)
+#define STM32_RCC_PLLCFGR_PLLPEN STM32_RCC_PLLCFGR_PLLPEN_MSK
+#define STM32_RCC_PLLCFGR_PLLP_POS 17U
+#define STM32_RCC_PLLCFGR_PLLP_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLP_POS)
+#define STM32_RCC_PLLCFGR_PLLP STM32_RCC_PLLCFGR_PLLP_MSK
+#define STM32_RCC_PLLCFGR_PLLQEN_POS 20U
+#define STM32_RCC_PLLCFGR_PLLQEN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLQEN_POS)
+#define STM32_RCC_PLLCFGR_PLLQEN STM32_RCC_PLLCFGR_PLLQEN_MSK
+
+#define STM32_RCC_PLLCFGR_PLLQ_POS 21U
+#define STM32_RCC_PLLCFGR_PLLQ_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLQ_POS)
+#define STM32_RCC_PLLCFGR_PLLQ STM32_RCC_PLLCFGR_PLLQ_MSK
+#define STM32_RCC_PLLCFGR_PLLQ_0 (0x1UL << STM32_RCC_PLLCFGR_PLLQ_POS)
+#define STM32_RCC_PLLCFGR_PLLQ_1 (0x2UL << STM32_RCC_PLLCFGR_PLLQ_POS)
+
+#define STM32_RCC_PLLCFGR_PLLREN_POS 24U
+#define STM32_RCC_PLLCFGR_PLLREN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLREN_POS)
+#define STM32_RCC_PLLCFGR_PLLREN STM32_RCC_PLLCFGR_PLLREN_MSK
+#define STM32_RCC_PLLCFGR_PLLR_POS 25U
+#define STM32_RCC_PLLCFGR_PLLR_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLR_POS)
+#define STM32_RCC_PLLCFGR_PLLR STM32_RCC_PLLCFGR_PLLR_MSK
+#define STM32_RCC_PLLCFGR_PLLR_0 (0x1UL << STM32_RCC_PLLCFGR_PLLR_POS)
+#define STM32_RCC_PLLCFGR_PLLR_1 (0x2UL << STM32_RCC_PLLCFGR_PLLR_POS)
+
+#define STM32_RCC_PLLCFGR_PLLPDIV_POS 27U
+#define STM32_RCC_PLLCFGR_PLLPDIV_MSK (0x1FUL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
+#define STM32_RCC_PLLCFGR_PLLPDIV STM32_RCC_PLLCFGR_PLLPDIV_MSK
+#define STM32_RCC_PLLCFGR_PLLPDIV_0 (0x01UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
+#define STM32_RCC_PLLCFGR_PLLPDIV_1 (0x02UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
+#define STM32_RCC_PLLCFGR_PLLPDIV_2 (0x04UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
+#define STM32_RCC_PLLCFGR_PLLPDIV_3 (0x08UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
+#define STM32_RCC_PLLCFGR_PLLPDIV_4 (0x10UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
 
 /****************  BIT DEFINITION FOR STM32_RCC_PLLSAI1CFGR REGISTER  ********/
 #define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS 8U
@@ -840,7 +838,7 @@
 #define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_6 \
 	(0x40UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
 
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_POS  16U
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_POS 16U
 #define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_MSK \
 	(0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_POS)
 #define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_MSK
@@ -1701,102 +1699,100 @@
 #define STM32_SYSCFG_I2CFMP(n) BIT(n + 21)
 
 /* Peripheral bits for STM32_RCC_APB/AHB and DBGMCU regs */
-#define STM32_RCC_PB1_PWREN			BIT(28)
+#define STM32_RCC_PB1_PWREN BIT(28)
 
-#define STM32_RCC_PB2_SYSCFGEN		BIT(0)
-#define STM32_RCC_PB2_USART1		BIT(14)
+#define STM32_RCC_PB2_SYSCFGEN BIT(0)
+#define STM32_RCC_PB2_USART1 BIT(14)
 
-#define STM32_RCC_HB1_DMA1		BIT(0)
-#define STM32_RCC_HB1_DMA2		BIT(1)
+#define STM32_RCC_HB1_DMA1 BIT(0)
+#define STM32_RCC_HB1_DMA2 BIT(1)
 
-#define STM32_RCC_HB2_GPIOA		BIT(0)
-#define STM32_RCC_HB2_GPIOB		BIT(1)
-#define STM32_RCC_HB2_GPIOC		BIT(2)
-#define STM32_RCC_HB2_GPIOD		BIT(3)
-#define STM32_RCC_HB2_GPIOE		BIT(4)
-#define STM32_RCC_HB2_GPIOH		BIT(7)
-#define STM32_RCC_HB2_ADC1		BIT(13)
+#define STM32_RCC_HB2_GPIOA BIT(0)
+#define STM32_RCC_HB2_GPIOB BIT(1)
+#define STM32_RCC_HB2_GPIOC BIT(2)
+#define STM32_RCC_HB2_GPIOD BIT(3)
+#define STM32_RCC_HB2_GPIOE BIT(4)
+#define STM32_RCC_HB2_GPIOH BIT(7)
+#define STM32_RCC_HB2_ADC1 BIT(13)
 
 /* Reset causes definitions */
 /* Reset causes in RCC CSR register */
-#define  STM32_RCC_RESET_CAUSE	STM32_RCC_CSR
-#define  RESET_CAUSE_WDG                0x60000000
-#define  RESET_CAUSE_SFT                0x10000000
-#define  RESET_CAUSE_POR                0x08000000
-#define  RESET_CAUSE_PIN                0x04000000
-#define  RESET_CAUSE_OTHER              0xff000000
-#define  RESET_CAUSE_RMVF               BIT(23)
+#define STM32_RCC_RESET_CAUSE STM32_RCC_CSR
+#define RESET_CAUSE_WDG 0x60000000
+#define RESET_CAUSE_SFT 0x10000000
+#define RESET_CAUSE_POR 0x08000000
+#define RESET_CAUSE_PIN 0x04000000
+#define RESET_CAUSE_OTHER 0xff000000
+#define RESET_CAUSE_RMVF BIT(23)
 /* Power cause in PWR CSR register */
-#define STM32_PWR_RESET_CAUSE			STM32_PWR_CSR
-#define STM32_PWR_RESET_CAUSE_CLR		STM32_PWR_SCR
-#define  RESET_CAUSE_SBF                BIT(8)
-#define  RESET_CAUSE_SBF_CLR            BIT(8)
+#define STM32_PWR_RESET_CAUSE STM32_PWR_CSR
+#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_SCR
+#define RESET_CAUSE_SBF BIT(8)
+#define RESET_CAUSE_SBF_CLR BIT(8)
 
 /* --- Watchdogs --- */
 
 /* --- Real-Time Clock --- */
-#define STM32_RTC_TR                REG32(STM32_RTC_BASE + 0x00)
-#define STM32_RTC_DR                REG32(STM32_RTC_BASE + 0x04)
-#define STM32_RTC_CR                REG32(STM32_RTC_BASE + 0x08)
-#define STM32_RTC_CR_BYPSHAD        BIT(5)
-#define STM32_RTC_CR_ALRAE          BIT(8)
-#define STM32_RTC_CR_WUTE           BIT(10)
-#define STM32_RTC_CR_ALRAIE         BIT(12)
-#define STM32_RTC_CR_WUTIE          BIT(14)
-#define STM32_RTC_ISR               REG32(STM32_RTC_BASE + 0x0C)
-#define STM32_RTC_ISR_ALRAWF        BIT(0)
-#define STM32_RTC_ISR_WUTWF         BIT(2)
-#define STM32_RTC_ISR_INITS         BIT(4)
-#define STM32_RTC_ISR_RSF           BIT(5)
-#define STM32_RTC_ISR_INITF         BIT(6)
-#define STM32_RTC_ISR_INIT          BIT(7)
-#define STM32_RTC_ISR_ALRAF         BIT(8)
-#define STM32_RTC_ISR_WUTF          BIT(9)
-#define STM32_RTC_PRER              REG32(STM32_RTC_BASE + 0x10)
-#define STM32_RTC_PRER_A_MASK       (0x7f << 16)
-#define STM32_RTC_PRER_S_MASK       (0x7fff << 0)
-#define STM32_RTC_WUTR              REG32(STM32_RTC_BASE + 0x14)
-#define STM32_RTC_CALIBR            REG32(STM32_RTC_BASE + 0x18)
-#define STM32_RTC_ALRMAR            REG32(STM32_RTC_BASE + 0x1C)
-#define STM32_RTC_ALRMBR            REG32(STM32_RTC_BASE + 0x20)
-#define STM32_RTC_WPR               REG32(STM32_RTC_BASE + 0x24)
-#define STM32_RTC_SSR               REG32(STM32_RTC_BASE + 0x28)
-#define STM32_RTC_TSTR              REG32(STM32_RTC_BASE + 0x30)
-#define STM32_RTC_TSDR              REG32(STM32_RTC_BASE + 0x34)
-#define STM32_RTC_TAFCR             REG32(STM32_RTC_BASE + 0x40)
-#define STM32_RTC_ALRMASSR          REG32(STM32_RTC_BASE + 0x44)
-#define STM32_RTC_BACKUP(n)         REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
+#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00)
+#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04)
+#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08)
+#define STM32_RTC_CR_BYPSHAD BIT(5)
+#define STM32_RTC_CR_ALRAE BIT(8)
+#define STM32_RTC_CR_WUTE BIT(10)
+#define STM32_RTC_CR_ALRAIE BIT(12)
+#define STM32_RTC_CR_WUTIE BIT(14)
+#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C)
+#define STM32_RTC_ISR_ALRAWF BIT(0)
+#define STM32_RTC_ISR_WUTWF BIT(2)
+#define STM32_RTC_ISR_INITS BIT(4)
+#define STM32_RTC_ISR_RSF BIT(5)
+#define STM32_RTC_ISR_INITF BIT(6)
+#define STM32_RTC_ISR_INIT BIT(7)
+#define STM32_RTC_ISR_ALRAF BIT(8)
+#define STM32_RTC_ISR_WUTF BIT(9)
+#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10)
+#define STM32_RTC_PRER_A_MASK (0x7f << 16)
+#define STM32_RTC_PRER_S_MASK (0x7fff << 0)
+#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14)
+#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18)
+#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C)
+#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20)
+#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24)
+#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28)
+#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30)
+#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34)
+#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40)
+#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44)
+#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
 
 #define STM32_RTC_CLEAR_FLAG(x)                         \
-			(STM32_RTC_ISR = (~((x) | STM32_RTC_ISR_INIT) | \
-					(STM32_RTC_ISR & STM32_RTC_ISR_INIT)))
-
-#define STM32_BKP_DATA(n)           STM32_RTC_BACKUP(n)
-#define STM32_BKP_BYTES             128
-
-#define RTC_TR_PM_POS                  22U
-#define RTC_TR_PM_MSK                  (0x1UL << RTC_TR_PM_POS)
-#define RTC_TR_PM                      RTC_TR_PM_MSK
-#define RTC_TR_HT_POS                  20U
-#define RTC_TR_HT_MSK                  (0x3UL << RTC_TR_HT_POS)
-#define RTC_TR_HT                      RTC_TR_HT_MSK
-#define RTC_TR_HU_POS                  16U
-#define RTC_TR_HU_MSK                  (0xFUL << RTC_TR_HU_POS)
-#define RTC_TR_HU                      RTC_TR_HU_MSK
-#define RTC_TR_MNT_POS                 12U
-#define RTC_TR_MNT_MSK                 (0x7UL << RTC_TR_MNT_POS)
-#define RTC_TR_MNT                     RTC_TR_MNT_MSK
-#define RTC_TR_MNU_POS                 8U
-#define RTC_TR_MNU_MSK                 (0xFUL << RTC_TR_MNU_POS)
-#define RTC_TR_MNU                     RTC_TR_MNU_MSK
-#define RTC_TR_ST_POS                  4U
-#define RTC_TR_ST_MSK                  (0x7UL << RTC_TR_ST_POS)
-#define RTC_TR_ST                      RTC_TR_ST_MSK
-#define RTC_TR_SU_POS                  0U
-#define RTC_TR_SU_MSK                  (0xFUL << RTC_TR_SU_POS)
-#define RTC_TR_SU                      RTC_TR_SU_MSK
-
-
+	(STM32_RTC_ISR = (~((x) | STM32_RTC_ISR_INIT) | \
+			  (STM32_RTC_ISR & STM32_RTC_ISR_INIT)))
+
+#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n)
+#define STM32_BKP_BYTES 128
+
+#define RTC_TR_PM_POS 22U
+#define RTC_TR_PM_MSK (0x1UL << RTC_TR_PM_POS)
+#define RTC_TR_PM RTC_TR_PM_MSK
+#define RTC_TR_HT_POS 20U
+#define RTC_TR_HT_MSK (0x3UL << RTC_TR_HT_POS)
+#define RTC_TR_HT RTC_TR_HT_MSK
+#define RTC_TR_HU_POS 16U
+#define RTC_TR_HU_MSK (0xFUL << RTC_TR_HU_POS)
+#define RTC_TR_HU RTC_TR_HU_MSK
+#define RTC_TR_MNT_POS 12U
+#define RTC_TR_MNT_MSK (0x7UL << RTC_TR_MNT_POS)
+#define RTC_TR_MNT RTC_TR_MNT_MSK
+#define RTC_TR_MNU_POS 8U
+#define RTC_TR_MNU_MSK (0xFUL << RTC_TR_MNU_POS)
+#define RTC_TR_MNU RTC_TR_MNU_MSK
+#define RTC_TR_ST_POS 4U
+#define RTC_TR_ST_MSK (0x7UL << RTC_TR_ST_POS)
+#define RTC_TR_ST RTC_TR_ST_MSK
+#define RTC_TR_SU_POS 0U
+#define RTC_TR_SU_MSK (0xFUL << RTC_TR_SU_POS)
+#define RTC_TR_SU RTC_TR_SU_MSK
 
 /* --- SPI --- */
 
@@ -1813,8 +1809,8 @@ struct stm32_spi_regs {
 	unsigned int crcpr;
 	unsigned int rxcrcr;
 	unsigned int txcrcr;
-	unsigned int i2scfgr;	/* STM32L only */
-	unsigned int i2spr;	/* STM32L only */
+	unsigned int i2scfgr; /* STM32L only */
+	unsigned int i2spr; /* STM32L only */
 };
 /* Must be volatile, or compiler optimizes out repeated accesses */
 typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
@@ -1824,152 +1820,152 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
 #define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE)
 #define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE)
 
-#define STM32_SPI_CR1_BIDIMODE		BIT(15)
-#define STM32_SPI_CR1_BIDIOE		BIT(14)
-#define STM32_SPI_CR1_CRCEN		BIT(13)
-#define STM32_SPI_CR1_SSM		BIT(9)
-#define STM32_SPI_CR1_SSI		BIT(8)
-#define STM32_SPI_CR1_LSBFIRST		BIT(7)
-#define STM32_SPI_CR1_SPE		BIT(6)
-#define STM32_SPI_CR1_BR_DIV64R		(5 << 3)
-#define STM32_SPI_CR1_BR_DIV4R		BIT(3)
-#define STM32_SPI_CR1_MSTR		BIT(2)
-#define STM32_SPI_CR1_CPOL		BIT(1)
-#define STM32_SPI_CR1_CPHA		BIT(0)
-#define STM32_SPI_CR2_FRXTH		BIT(12)
-#define STM32_SPI_CR2_DATASIZE(n)	(((n) - 1) << 8)
-#define STM32_SPI_CR2_TXEIE		BIT(7)
-#define STM32_SPI_CR2_RXNEIE		BIT(6)
-#define STM32_SPI_CR2_NSSP		BIT(3)
-#define STM32_SPI_CR2_SSOE		BIT(2)
-#define STM32_SPI_CR2_TXDMAEN		BIT(1)
-#define STM32_SPI_CR2_RXDMAEN		BIT(0)
-
-#define STM32_SPI_SR_RXNE		BIT(0)
-#define STM32_SPI_SR_TXE		BIT(1)
-#define STM32_SPI_SR_CRCERR		BIT(4)
-#define STM32_SPI_SR_BSY		BIT(7)
-#define STM32_SPI_SR_FRLVL		(3 << 9)
-#define STM32_SPI_SR_FTLVL		(3 << 11)
+#define STM32_SPI_CR1_BIDIMODE BIT(15)
+#define STM32_SPI_CR1_BIDIOE BIT(14)
+#define STM32_SPI_CR1_CRCEN BIT(13)
+#define STM32_SPI_CR1_SSM BIT(9)
+#define STM32_SPI_CR1_SSI BIT(8)
+#define STM32_SPI_CR1_LSBFIRST BIT(7)
+#define STM32_SPI_CR1_SPE BIT(6)
+#define STM32_SPI_CR1_BR_DIV64R (5 << 3)
+#define STM32_SPI_CR1_BR_DIV4R BIT(3)
+#define STM32_SPI_CR1_MSTR BIT(2)
+#define STM32_SPI_CR1_CPOL BIT(1)
+#define STM32_SPI_CR1_CPHA BIT(0)
+#define STM32_SPI_CR2_FRXTH BIT(12)
+#define STM32_SPI_CR2_DATASIZE(n) (((n)-1) << 8)
+#define STM32_SPI_CR2_TXEIE BIT(7)
+#define STM32_SPI_CR2_RXNEIE BIT(6)
+#define STM32_SPI_CR2_NSSP BIT(3)
+#define STM32_SPI_CR2_SSOE BIT(2)
+#define STM32_SPI_CR2_TXDMAEN BIT(1)
+#define STM32_SPI_CR2_RXDMAEN BIT(0)
+
+#define STM32_SPI_SR_RXNE BIT(0)
+#define STM32_SPI_SR_TXE BIT(1)
+#define STM32_SPI_SR_CRCERR BIT(4)
+#define STM32_SPI_SR_BSY BIT(7)
+#define STM32_SPI_SR_FRLVL (3 << 9)
+#define STM32_SPI_SR_FTLVL (3 << 11)
 /* --- Debug --- */
-#define STM32_DBGMCU_APB1FZ         REG32(STM32_DBGMCU_BASE + 0x08)
-#define STM32_DBGMCU_APB2FZ         REG32(STM32_DBGMCU_BASE + 0x0C)
+#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08)
+#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C)
 
 /* --- Flash --- */
-#define STM32_FLASH_ACR             REG32(STM32_FLASH_REGS_BASE + 0x00)
+#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00)
 #define STM32_FLASH_ACR_LATENCY_SHIFT (0)
-#define STM32_FLASH_ACR_LATENCY_MASK  (7 << STM32_FLASH_ACR_LATENCY_SHIFT)
-#define STM32_FLASH_ACR_PRFTEN      BIT(8)
-#define STM32_FLASH_ACR_ICEN        BIT(9)
-#define STM32_FLASH_ACR_DCEN        BIT(10)
-#define STM32_FLASH_ACR_ICRST       BIT(11)
-#define STM32_FLASH_ACR_DCRST       BIT(12)
-#define STM32_FLASH_PDKEYR          REG32(STM32_FLASH_REGS_BASE + 0x04)
-#define STM32_FLASH_KEYR            REG32(STM32_FLASH_REGS_BASE + 0x08)
-#define  FLASH_KEYR_KEY1            0x45670123
-#define  FLASH_KEYR_KEY2            0xCDEF89AB
-#define STM32_FLASH_OPTKEYR         REG32(STM32_FLASH_REGS_BASE + 0x0c)
-#define  FLASH_OPTKEYR_KEY1         0x08192A3B
-#define  FLASH_OPTKEYR_KEY2         0x4C5D6E7F
-#define STM32_FLASH_SR              REG32(STM32_FLASH_REGS_BASE + 0x10)
-#define  FLASH_SR_BUSY              BIT(16)
-#define  FLASH_SR_ERR_MASK          (0xc3fa)
-#define STM32_FLASH_CR              REG32(STM32_FLASH_REGS_BASE + 0x14)
-#define  FLASH_CR_PG                BIT(0)
-#define  FLASH_CR_PER               BIT(1)
-#define  FLASH_CR_STRT              BIT(16)
-#define  FLASH_CR_OPTSTRT           BIT(17)
-#define  FLASH_CR_OBL_LAUNCH        BIT(27)
-#define  FLASH_CR_OPTLOCK           BIT(30)
-#define  FLASH_CR_LOCK              BIT(31)
-#define  FLASH_CR_PNB(sec)          (((sec) & 0xff) << 3)
-#define  FLASH_CR_PNB_MASK          FLASH_CR_PNB(0xff)
-#define STM32_FLASH_ECCR            REG32(STM32_FLASH_REGS_BASE + 0x18)
-#define STM32_FLASH_OPTR            REG32(STM32_FLASH_REGS_BASE + 0x20)
-#define STM32_FLASH_PCROP1SR        REG32(STM32_FLASH_REGS_BASE + 0x24)
-#define STM32_FLASH_PCROP1ER        REG32(STM32_FLASH_REGS_BASE + 0x28)
-#define STM32_FLASH_WRP1AR          REG32(STM32_FLASH_REGS_BASE + 0x2C)
-#define STM32_FLASH_WRP1BR          REG32(STM32_FLASH_REGS_BASE + 0x30)
+#define STM32_FLASH_ACR_LATENCY_MASK (7 << STM32_FLASH_ACR_LATENCY_SHIFT)
+#define STM32_FLASH_ACR_PRFTEN BIT(8)
+#define STM32_FLASH_ACR_ICEN BIT(9)
+#define STM32_FLASH_ACR_DCEN BIT(10)
+#define STM32_FLASH_ACR_ICRST BIT(11)
+#define STM32_FLASH_ACR_DCRST BIT(12)
+#define STM32_FLASH_PDKEYR REG32(STM32_FLASH_REGS_BASE + 0x04)
+#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x08)
+#define FLASH_KEYR_KEY1 0x45670123
+#define FLASH_KEYR_KEY2 0xCDEF89AB
+#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x0c)
+#define FLASH_OPTKEYR_KEY1 0x08192A3B
+#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F
+#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x10)
+#define FLASH_SR_BUSY BIT(16)
+#define FLASH_SR_ERR_MASK (0xc3fa)
+#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x14)
+#define FLASH_CR_PG BIT(0)
+#define FLASH_CR_PER BIT(1)
+#define FLASH_CR_STRT BIT(16)
+#define FLASH_CR_OPTSTRT BIT(17)
+#define FLASH_CR_OBL_LAUNCH BIT(27)
+#define FLASH_CR_OPTLOCK BIT(30)
+#define FLASH_CR_LOCK BIT(31)
+#define FLASH_CR_PNB(sec) (((sec)&0xff) << 3)
+#define FLASH_CR_PNB_MASK FLASH_CR_PNB(0xff)
+#define STM32_FLASH_ECCR REG32(STM32_FLASH_REGS_BASE + 0x18)
+#define STM32_FLASH_OPTR REG32(STM32_FLASH_REGS_BASE + 0x20)
+#define STM32_FLASH_PCROP1SR REG32(STM32_FLASH_REGS_BASE + 0x24)
+#define STM32_FLASH_PCROP1ER REG32(STM32_FLASH_REGS_BASE + 0x28)
+#define STM32_FLASH_WRP1AR REG32(STM32_FLASH_REGS_BASE + 0x2C)
+#define STM32_FLASH_WRP1BR REG32(STM32_FLASH_REGS_BASE + 0x30)
 /* Minimum number of bytes that can be written to flash */
-#define STM32_FLASH_MIN_WRITE_SIZE  CONFIG_FLASH_WRITE_SIZE
+#define STM32_FLASH_MIN_WRITE_SIZE CONFIG_FLASH_WRITE_SIZE
 
-#define STM32_OPTB_USER_RDP         REG32(STM32_OPTB_BASE + 0x00)
-#define STM32_OPTB_WRP1AR           REG32(STM32_OPTB_BASE + 0x18)
-#define STM32_OPTB_WRP1BR           REG32(STM32_OPTB_BASE + 0x20)
+#define STM32_OPTB_USER_RDP REG32(STM32_OPTB_BASE + 0x00)
+#define STM32_OPTB_WRP1AR REG32(STM32_OPTB_BASE + 0x18)
+#define STM32_OPTB_WRP1BR REG32(STM32_OPTB_BASE + 0x20)
 
 /* --- External Interrupts --- */
-#define STM32_EXTI_IMR              REG32(STM32_EXTI_BASE + 0x00)
-#define STM32_EXTI_EMR              REG32(STM32_EXTI_BASE + 0x04)
-#define STM32_EXTI_RTSR             REG32(STM32_EXTI_BASE + 0x08)
-#define STM32_EXTI_FTSR             REG32(STM32_EXTI_BASE + 0x0c)
-#define STM32_EXTI_SWIER            REG32(STM32_EXTI_BASE + 0x10)
-#define STM32_EXTI_PR               REG32(STM32_EXTI_BASE + 0x14)
+#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00)
+#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04)
+#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08)
+#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c)
+#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10)
+#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14)
 
-#define EXTI_RTC_ALR_EVENT          BIT(18)
+#define EXTI_RTC_ALR_EVENT BIT(18)
 
 /* --- ADC --- */
-#define STM32_ADC1_ISR              REG32(STM32_ADC1_BASE + 0x00)
-#define STM32_ADC1_ISR_ADRDY        BIT(0)
-#define STM32_ADC1_IER              REG32(STM32_ADC1_BASE + 0x04)
-#define STM32_ADC1_IER_AWDIE        BIT(7)
-#define STM32_ADC1_IER_OVRIE        BIT(4)
-#define STM32_ADC1_IER_EOSEQIE      BIT(3)
-#define STM32_ADC1_IER_EOCIE        BIT(2)
-#define STM32_ADC1_IER_EOSMPIE      BIT(1)
-#define STM32_ADC1_IER_ADRDYIE      BIT(0)
-
-#define STM32_ADC1_CR               REG32(STM32_ADC1_BASE + 0x08)
-#define STM32_ADC1_CR_ADEN          BIT(0)
-#define STM32_ADC1_CR_ADDIS         BIT(1)
-#define STM32_ADC1_CR_ADSTP         BIT(4)
-#define STM32_ADC1_CR_ADVREGEN      BIT(28)
-#define STM32_ADC1_CR_DEEPPWD	    BIT(29)
-#define STM32_ADC1_CR_ADCAL         BIT(31)
-#define STM32_ADC1_CFGR             REG32(STM32_ADC1_BASE + 0x0C)
+#define STM32_ADC1_ISR REG32(STM32_ADC1_BASE + 0x00)
+#define STM32_ADC1_ISR_ADRDY BIT(0)
+#define STM32_ADC1_IER REG32(STM32_ADC1_BASE + 0x04)
+#define STM32_ADC1_IER_AWDIE BIT(7)
+#define STM32_ADC1_IER_OVRIE BIT(4)
+#define STM32_ADC1_IER_EOSEQIE BIT(3)
+#define STM32_ADC1_IER_EOCIE BIT(2)
+#define STM32_ADC1_IER_EOSMPIE BIT(1)
+#define STM32_ADC1_IER_ADRDYIE BIT(0)
+
+#define STM32_ADC1_CR REG32(STM32_ADC1_BASE + 0x08)
+#define STM32_ADC1_CR_ADEN BIT(0)
+#define STM32_ADC1_CR_ADDIS BIT(1)
+#define STM32_ADC1_CR_ADSTP BIT(4)
+#define STM32_ADC1_CR_ADVREGEN BIT(28)
+#define STM32_ADC1_CR_DEEPPWD BIT(29)
+#define STM32_ADC1_CR_ADCAL BIT(31)
+#define STM32_ADC1_CFGR REG32(STM32_ADC1_BASE + 0x0C)
 /* Analog watchdog channel selection */
-#define STM32_ADC1_CFGR_AWDCH_MASK  (0x1f << 26)
-#define STM32_ADC1_CFGR_AWDEN       BIT(23)
-#define STM32_ADC1_CFGR_AWDSGL      BIT(22)
-#define STM32_ADC1_CFGR_AUTDLY	    BIT(14)
+#define STM32_ADC1_CFGR_AWDCH_MASK (0x1f << 26)
+#define STM32_ADC1_CFGR_AWDEN BIT(23)
+#define STM32_ADC1_CFGR_AWDSGL BIT(22)
+#define STM32_ADC1_CFGR_AUTDLY BIT(14)
 /* Selects single vs continuous */
-#define STM32_ADC1_CFGR_CONT        BIT(13)
+#define STM32_ADC1_CFGR_CONT BIT(13)
 /* Selects ADC_DR overwrite vs preserve */
-#define STM32_ADC1_CFGR_OVRMOD      BIT(12)
+#define STM32_ADC1_CFGR_OVRMOD BIT(12)
 /* External trigger polarity selection */
-#define STM32_ADC1_CFGR_EXTEN_DIS   (0 << 10)
-#define STM32_ADC1_CFGR_EXTEN_RISE  (1 << 10)
-#define STM32_ADC1_CFGR_EXTEN_FALL  (2 << 10)
-#define STM32_ADC1_CFGR_EXTEN_BOTH  (3 << 10)
-#define STM32_ADC1_CFGR_EXTEN_MASK  (3 << 10)
-#define STM32_ADC1_CFGR_ALIGN	    BIT(5)
+#define STM32_ADC1_CFGR_EXTEN_DIS (0 << 10)
+#define STM32_ADC1_CFGR_EXTEN_RISE (1 << 10)
+#define STM32_ADC1_CFGR_EXTEN_FALL (2 << 10)
+#define STM32_ADC1_CFGR_EXTEN_BOTH (3 << 10)
+#define STM32_ADC1_CFGR_EXTEN_MASK (3 << 10)
+#define STM32_ADC1_CFGR_ALIGN BIT(5)
 /* External trigger selection */
-#define STM32_ADC1_CFGR_TRG0        (0 << 6)
-#define STM32_ADC1_CFGR_TRG1        (1 << 6)
-#define STM32_ADC1_CFGR_TRG2        (2 << 6)
-#define STM32_ADC1_CFGR_TRG3        (3 << 6)
-#define STM32_ADC1_CFGR_TRG4        (4 << 6)
-#define STM32_ADC1_CFGR_TRG5        (5 << 6)
-#define STM32_ADC1_CFGR_TRG6        (6 << 6)
-#define STM32_ADC1_CFGR_TRG7        (7 << 6)
-#define STM32_ADC1_CFGR_TRG_MASK    (7 << 6)
+#define STM32_ADC1_CFGR_TRG0 (0 << 6)
+#define STM32_ADC1_CFGR_TRG1 (1 << 6)
+#define STM32_ADC1_CFGR_TRG2 (2 << 6)
+#define STM32_ADC1_CFGR_TRG3 (3 << 6)
+#define STM32_ADC1_CFGR_TRG4 (4 << 6)
+#define STM32_ADC1_CFGR_TRG5 (5 << 6)
+#define STM32_ADC1_CFGR_TRG6 (6 << 6)
+#define STM32_ADC1_CFGR_TRG7 (7 << 6)
+#define STM32_ADC1_CFGR_TRG_MASK (7 << 6)
 /* Selects circular vs one-shot */
-#define STM32_ADC1_CFGR_DMACFG      BIT(1)
-#define STM32_ADC1_CFGR_DMAEN       BIT(0)
-#define STM32_ADC1_CFGR2            REG32(STM32_ADC1_BASE + 0x10)
+#define STM32_ADC1_CFGR_DMACFG BIT(1)
+#define STM32_ADC1_CFGR_DMAEN BIT(0)
+#define STM32_ADC1_CFGR2 REG32(STM32_ADC1_BASE + 0x10)
 /* Sampling time selection - 1.5 ADC cycles min, 239.5 cycles max */
-#define STM32_ADC1_SMPR1            REG32(STM32_ADC1_BASE + 0x14)
-#define STM32_ADC1_SMPR2            REG32(STM32_ADC1_BASE + 0x18)
+#define STM32_ADC1_SMPR1 REG32(STM32_ADC1_BASE + 0x14)
+#define STM32_ADC1_SMPR2 REG32(STM32_ADC1_BASE + 0x18)
 /* Macro to convert enum stm32_adc_smpr to SMP bits of the ADC_SMPR register */
-#define STM32_ADC1_SMPR_SMP(s)      ((s) - 1)
-#define STM32_ADC1_TR               REG32(STM32_ADC1_BASE + 0x20)
-#define STM32_ADC1_CHSELR           REG32(STM32_ADC1_BASE + 0x28)
-#define STM32_ADC1_DR               REG32(STM32_ADC1_BASE + 0x40)
-#define STM32_ADC1_JSQR             REG32(STM32_ADC1_BASE + 0x4C)
-#define STM32_ADC1_JDR1             REG32(STM32_ADC1_BASE + 0x80)
-#define STM32_ADC1_JDR2             REG32(STM32_ADC1_BASE + 0x84)
-#define STM32_ADC1_JDR3             REG32(STM32_ADC1_BASE + 0x88)
-#define STM32_ADC1_JDR4             REG32(STM32_ADC1_BASE + 0x8C)
-#define STM32_ADC1_CCR              REG32(STM32_ADC1_BASE + 0x308)
+#define STM32_ADC1_SMPR_SMP(s) ((s)-1)
+#define STM32_ADC1_TR REG32(STM32_ADC1_BASE + 0x20)
+#define STM32_ADC1_CHSELR REG32(STM32_ADC1_BASE + 0x28)
+#define STM32_ADC1_DR REG32(STM32_ADC1_BASE + 0x40)
+#define STM32_ADC1_JSQR REG32(STM32_ADC1_BASE + 0x4C)
+#define STM32_ADC1_JDR1 REG32(STM32_ADC1_BASE + 0x80)
+#define STM32_ADC1_JDR2 REG32(STM32_ADC1_BASE + 0x84)
+#define STM32_ADC1_JDR3 REG32(STM32_ADC1_BASE + 0x88)
+#define STM32_ADC1_JDR4 REG32(STM32_ADC1_BASE + 0x8C)
+#define STM32_ADC1_CCR REG32(STM32_ADC1_BASE + 0x308)
 
 /* --- DMA --- */
 
@@ -2021,11 +2017,11 @@ enum dma_channel {
 
 /* Registers for a single channel of the DMA controller */
 struct stm32_dma_chan {
-	uint32_t	ccr;		/* Control */
-	uint32_t	cndtr;		/* Number of data to transfer */
-	uint32_t	cpar;		/* Peripheral address */
-	uint32_t	cmar;		/* Memory address */
-	uint32_t	reserved;
+	uint32_t ccr; /* Control */
+	uint32_t cndtr; /* Number of data to transfer */
+	uint32_t cpar; /* Peripheral address */
+	uint32_t cmar; /* Memory address */
+	uint32_t reserved;
 };
 
 /* Always use stm32_dma_chan_t so volatile keyword is included! */
@@ -2036,8 +2032,8 @@ typedef stm32_dma_chan_t dma_chan_t;
 
 /* Registers for the DMA controller */
 struct stm32_dma_regs {
-	uint32_t	isr;
-	uint32_t	ifcr;
+	uint32_t isr;
+	uint32_t ifcr;
 	stm32_dma_chan_t chan[STM32_DMAC_COUNT];
 };
 
@@ -2046,68 +2042,67 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
 
 #define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE)
 
-
-#define STM32_DMA_CCR_CHANNEL(channel)		 (0)
+#define STM32_DMA_CCR_CHANNEL(channel) (0)
 #define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE)
 #define STM32_DMA_REGS(channel) \
 	((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_REGS : STM32_DMA2_REGS)
-#define STM32_DMA_CSELR(channel) \
-	REG32(((channel) < STM32_DMAC_PER_CTLR ? \
-			STM32_DMA1_BASE : STM32_DMA2_BASE)  + 0xA8)
+#define STM32_DMA_CSELR(channel)                                    \
+	REG32(((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_BASE :  \
+						 STM32_DMA2_BASE) + \
+	      0xA8)
 
 /* Bits for DMA controller regs (isr and ifcr) */
-#define STM32_DMA_CH_OFFSET(channel)   (4 * ((channel) % STM32_DMAC_PER_CTLR))
+#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR))
 #define STM32_DMA_ISR_MASK(channel, mask) \
 	((mask) << STM32_DMA_CH_OFFSET(channel))
-#define STM32_DMA_ISR_GIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(0))
-#define STM32_DMA_ISR_TCIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(1))
-#define STM32_DMA_ISR_HTIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(2))
-#define STM32_DMA_ISR_TEIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(3))
-#define STM32_DMA_ISR_ALL(channel)	STM32_DMA_ISR_MASK(channel, 0x0f)
-
-#define STM32_DMA_GIF                   BIT(0)
-#define STM32_DMA_TCIF                  BIT(1)
-#define STM32_DMA_HTIF                  BIT(2)
-#define STM32_DMA_TEIF                  BIT(3)
-#define STM32_DMA_ALL                   0xf
-
-#define STM32_DMA_GET_ISR(channel)      \
-	((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_ISR(channel, val) \
-	(STM32_DMA_REGS(channel)->isr = \
-	((STM32_DMA_REGS(channel)->isr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-#define STM32_DMA_GET_IFCR(channel)      \
-	((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_IFCR(channel, val) \
-	(STM32_DMA_REGS(channel)->ifcr = \
-	((STM32_DMA_REGS(channel)->ifcr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-
+#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0))
+#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1))
+#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2))
+#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3))
+#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f)
+
+#define STM32_DMA_GIF BIT(0)
+#define STM32_DMA_TCIF BIT(1)
+#define STM32_DMA_HTIF BIT(2)
+#define STM32_DMA_TEIF BIT(3)
+#define STM32_DMA_ALL 0xf
+
+#define STM32_DMA_GET_ISR(channel)                                        \
+	((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) & \
+	 STM32_DMA_ALL)
+#define STM32_DMA_SET_ISR(channel, val)                                \
+	(STM32_DMA_REGS(channel)->isr =                                \
+		 ((STM32_DMA_REGS(channel)->isr &                      \
+		   ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
+		  (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
+#define STM32_DMA_GET_IFCR(channel)                                        \
+	((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) & \
+	 STM32_DMA_ALL)
+#define STM32_DMA_SET_IFCR(channel, val)                               \
+	(STM32_DMA_REGS(channel)->ifcr =                               \
+		 ((STM32_DMA_REGS(channel)->ifcr &                     \
+		   ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
+		  (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
 
 /* Bits for DMA channel regs */
-#define STM32_DMA_CCR_EN		BIT(0)
-#define STM32_DMA_CCR_TCIE		BIT(1)
-#define STM32_DMA_CCR_HTIE		BIT(2)
-#define STM32_DMA_CCR_TEIE		BIT(3)
-#define STM32_DMA_CCR_DIR		BIT(4)
-#define STM32_DMA_CCR_CIRC		BIT(5)
-#define STM32_DMA_CCR_PINC		BIT(6)
-#define STM32_DMA_CCR_MINC		BIT(7)
-#define STM32_DMA_CCR_PSIZE_8_BIT	(0 << 8)
-#define STM32_DMA_CCR_PSIZE_16_BIT	(1 << 8)
-#define STM32_DMA_CCR_PSIZE_32_BIT	(2 << 8)
-#define STM32_DMA_CCR_MSIZE_8_BIT	(0 << 10)
-#define STM32_DMA_CCR_MSIZE_16_BIT	(1 << 10)
-#define STM32_DMA_CCR_MSIZE_32_BIT	(2 << 10)
-#define STM32_DMA_CCR_PL_LOW		(0 << 12)
-#define STM32_DMA_CCR_PL_MEDIUM		(1 << 12)
-#define STM32_DMA_CCR_PL_HIGH		(2 << 12)
-#define STM32_DMA_CCR_PL_VERY_HIGH	(3 << 12)
-#define STM32_DMA_CCR_MEM2MEM		BIT(14)
+#define STM32_DMA_CCR_EN BIT(0)
+#define STM32_DMA_CCR_TCIE BIT(1)
+#define STM32_DMA_CCR_HTIE BIT(2)
+#define STM32_DMA_CCR_TEIE BIT(3)
+#define STM32_DMA_CCR_DIR BIT(4)
+#define STM32_DMA_CCR_CIRC BIT(5)
+#define STM32_DMA_CCR_PINC BIT(6)
+#define STM32_DMA_CCR_MINC BIT(7)
+#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8)
+#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8)
+#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8)
+#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10)
+#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10)
+#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10)
+#define STM32_DMA_CCR_PL_LOW (0 << 12)
+#define STM32_DMA_CCR_PL_MEDIUM (1 << 12)
+#define STM32_DMA_CCR_PL_HIGH (2 << 12)
+#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12)
+#define STM32_DMA_CCR_MEM2MEM BIT(14)
 
 #endif /* !__ASSEMBLER__ */
diff --git a/chip/stm32/registers-stm32l5.h b/chip/stm32/registers-stm32l5.h
index 5055bc9e19..47f766e035 100644
--- a/chip/stm32/registers-stm32l5.h
+++ b/chip/stm32/registers-stm32l5.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,93 +19,93 @@
 #endif
 
 /******  STM32 specific Interrupt Numbers ********/
-#define STM32_IRQ_WWDG             0
-#define STM32_IRQ_PVD              1
-#define STM32_IRQ_RTC_ALARM        2
-#define STM32_IRQ_FLASH            6
-#define STM32_IRQ_FLASH_S          7
-#define STM32_IRQ_RCC              9
-#define STM32_IRQ_RCC_S           10
-#define STM32_IRQ_EXTI0           11
-#define STM32_IRQ_EXTI1           12
-#define STM32_IRQ_EXTI2           13
-#define STM32_IRQ_EXTI3           14
-#define STM32_IRQ_EXTI4           15
-#define STM32_IRQ_EXTI5           16
-#define STM32_IRQ_EXTI6           17
-#define STM32_IRQ_EXTI7           18
-#define STM32_IRQ_EXTI8           19
-#define STM32_IRQ_EXTI9           20
-#define STM32_IRQ_EXTI10          21
-#define STM32_IRQ_EXTI11          22
-#define STM32_IRQ_EXTI12          23
-#define STM32_IRQ_EXTI13          24
-#define STM32_IRQ_EXTI14          25
-#define STM32_IRQ_EXTI15          26
-#define STM32_IRQ_DMAMUX_OVR      27
-#define STM32_IRQ_DMAMUX_OVR_S    28
-#define STM32_IRQ_DMA_CHANNEL_1   29
-#define STM32_IRQ_DMA_CHANNEL_2   30
-#define STM32_IRQ_DMA_CHANNEL_3   31
-#define STM32_IRQ_DMA_CHANNEL_4   32
-#define STM32_IRQ_DMA_CHANNEL_5   33
-#define STM32_IRQ_DMA_CHANNEL_6   34
-#define STM32_IRQ_DMA_CHANNEL_7   35
-#define STM32_IRQ_DMA_CHANNEL_8   36
-#define STM32_IRQ_ADC1            37
-#define STM32_IRQ_TIM1_BRK        41
-#define STM32_IRQ_TIM1_UP         42
-#define STM32_IRQ_TIM1_TRG_COM    43
-#define STM32_IRQ_TIM1_CC         44
-#define STM32_IRQ_TIM2            45
-#define STM32_IRQ_TIM3            46
-#define STM32_IRQ_TIM4            47
-#define STM32_IRQ_TIM5            48
-#define STM32_IRQ_TIM6            49
-#define STM32_IRQ_TIM7            50
-#define STM32_IRQ_TIM8_BRK        51
-#define STM32_IRQ_TIM8_UP         52
-#define STM32_IRQ_TIM8_TRG_COM    53
-#define STM32_IRQ_TIM8_CC         54
-#define STM32_IRQ_I2C1_EV         55
-#define STM32_IRQ_I2C1_ER         56
-#define STM32_IRQ_I2C2_EV         57
-#define STM32_IRQ_I2C2_ER         58
-#define STM32_IRQ_SPI1            59
-#define STM32_IRQ_SPI2            60
-#define STM32_IRQ_USART1          61
-#define STM32_IRQ_USART2          62
-#define STM32_IRQ_USART3          63
-#define STM32_IRQ_USART4          64
-#define STM32_IRQ_USART5          65
-#define STM32_IRQ_LPUART1         66
-#define STM32_IRQ_LPTIM1          67
-#define STM32_IRQ_LPTIM2          68
-#define STM32_IRQ_TIM15           69
-#define STM32_IRQ_TIM16           70
-#define STM32_IRQ_TIM17           71
-#define STM32_IRQ_COMP            72
-#define STM32_IRQ_USB_FS          73
-#define STM32_IRQ_CRS             74
-#define STM32_IRQ_FMC             75
-#define STM32_IRQ_DMA2_CHANNEL1   80
-#define STM32_IRQ_DMA2_CHANNEL2   81
-#define STM32_IRQ_DMA2_CHANNEL3   82
-#define STM32_IRQ_DMA2_CHANNEL4   83
-#define STM32_IRQ_DMA2_CHANNEL5   84
-#define STM32_IRQ_DMA2_CHANNEL6   85
-#define STM32_IRQ_DMA2_CHANNEL7   86
-#define STM32_IRQ_DMA2_CHANNEL8   87
+#define STM32_IRQ_WWDG 0
+#define STM32_IRQ_PVD 1
+#define STM32_IRQ_RTC_ALARM 2
+#define STM32_IRQ_FLASH 6
+#define STM32_IRQ_FLASH_S 7
+#define STM32_IRQ_RCC 9
+#define STM32_IRQ_RCC_S 10
+#define STM32_IRQ_EXTI0 11
+#define STM32_IRQ_EXTI1 12
+#define STM32_IRQ_EXTI2 13
+#define STM32_IRQ_EXTI3 14
+#define STM32_IRQ_EXTI4 15
+#define STM32_IRQ_EXTI5 16
+#define STM32_IRQ_EXTI6 17
+#define STM32_IRQ_EXTI7 18
+#define STM32_IRQ_EXTI8 19
+#define STM32_IRQ_EXTI9 20
+#define STM32_IRQ_EXTI10 21
+#define STM32_IRQ_EXTI11 22
+#define STM32_IRQ_EXTI12 23
+#define STM32_IRQ_EXTI13 24
+#define STM32_IRQ_EXTI14 25
+#define STM32_IRQ_EXTI15 26
+#define STM32_IRQ_DMAMUX_OVR 27
+#define STM32_IRQ_DMAMUX_OVR_S 28
+#define STM32_IRQ_DMA_CHANNEL_1 29
+#define STM32_IRQ_DMA_CHANNEL_2 30
+#define STM32_IRQ_DMA_CHANNEL_3 31
+#define STM32_IRQ_DMA_CHANNEL_4 32
+#define STM32_IRQ_DMA_CHANNEL_5 33
+#define STM32_IRQ_DMA_CHANNEL_6 34
+#define STM32_IRQ_DMA_CHANNEL_7 35
+#define STM32_IRQ_DMA_CHANNEL_8 36
+#define STM32_IRQ_ADC1 37
+#define STM32_IRQ_TIM1_BRK 41
+#define STM32_IRQ_TIM1_UP 42
+#define STM32_IRQ_TIM1_TRG_COM 43
+#define STM32_IRQ_TIM1_CC 44
+#define STM32_IRQ_TIM2 45
+#define STM32_IRQ_TIM3 46
+#define STM32_IRQ_TIM4 47
+#define STM32_IRQ_TIM5 48
+#define STM32_IRQ_TIM6 49
+#define STM32_IRQ_TIM7 50
+#define STM32_IRQ_TIM8_BRK 51
+#define STM32_IRQ_TIM8_UP 52
+#define STM32_IRQ_TIM8_TRG_COM 53
+#define STM32_IRQ_TIM8_CC 54
+#define STM32_IRQ_I2C1_EV 55
+#define STM32_IRQ_I2C1_ER 56
+#define STM32_IRQ_I2C2_EV 57
+#define STM32_IRQ_I2C2_ER 58
+#define STM32_IRQ_SPI1 59
+#define STM32_IRQ_SPI2 60
+#define STM32_IRQ_USART1 61
+#define STM32_IRQ_USART2 62
+#define STM32_IRQ_USART3 63
+#define STM32_IRQ_USART4 64
+#define STM32_IRQ_USART5 65
+#define STM32_IRQ_LPUART1 66
+#define STM32_IRQ_LPTIM1 67
+#define STM32_IRQ_LPTIM2 68
+#define STM32_IRQ_TIM15 69
+#define STM32_IRQ_TIM16 70
+#define STM32_IRQ_TIM17 71
+#define STM32_IRQ_COMP 72
+#define STM32_IRQ_USB_FS 73
+#define STM32_IRQ_CRS 74
+#define STM32_IRQ_FMC 75
+#define STM32_IRQ_DMA2_CHANNEL1 80
+#define STM32_IRQ_DMA2_CHANNEL2 81
+#define STM32_IRQ_DMA2_CHANNEL3 82
+#define STM32_IRQ_DMA2_CHANNEL4 83
+#define STM32_IRQ_DMA2_CHANNEL5 84
+#define STM32_IRQ_DMA2_CHANNEL6 85
+#define STM32_IRQ_DMA2_CHANNEL7 86
+#define STM32_IRQ_DMA2_CHANNEL8 87
 
 /* To simplify code generation, define DMA channel 9..16 */
-#define STM32_IRQ_DMA_CHANNEL_9    STM32_IRQ_DMA2_CHANNEL1
-#define STM32_IRQ_DMA_CHANNEL_10   STM32_IRQ_DMA2_CHANNEL2
-#define STM32_IRQ_DMA_CHANNEL_11   STM32_IRQ_DMA2_CHANNEL3
-#define STM32_IRQ_DMA_CHANNEL_12   STM32_IRQ_DMA2_CHANNEL4
-#define STM32_IRQ_DMA_CHANNEL_13   STM32_IRQ_DMA2_CHANNEL5
-#define STM32_IRQ_DMA_CHANNEL_14   STM32_IRQ_DMA2_CHANNEL6
-#define STM32_IRQ_DMA_CHANNEL_15   STM32_IRQ_DMA2_CHANNEL7
-#define STM32_IRQ_DMA_CHANNEL_16   STM32_IRQ_DMA2_CHANNEL8
+#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1
+#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2
+#define STM32_IRQ_DMA_CHANNEL_11 STM32_IRQ_DMA2_CHANNEL3
+#define STM32_IRQ_DMA_CHANNEL_12 STM32_IRQ_DMA2_CHANNEL4
+#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL5
+#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL6
+#define STM32_IRQ_DMA_CHANNEL_15 STM32_IRQ_DMA2_CHANNEL7
+#define STM32_IRQ_DMA_CHANNEL_16 STM32_IRQ_DMA2_CHANNEL8
 
 /* aliases for easier code sharing */
 #define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV
@@ -113,269 +113,268 @@
 #define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV
 #define STM32_IRQ_USB_LP STM32_IRQ_USB_FS
 
-
-#define PERIPH_BASE           0x40000000UL
+#define PERIPH_BASE 0x40000000UL
 
 /*!< Peripheral memory map */
-#define APB1PERIPH_BASE        PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x02000000UL)
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x02000000UL)
 
 /*!< APB1 peripherals */
-#define STM32_TIM2_BASE             (APB1PERIPH_BASE + 0x0000UL)
-#define STM32_TIM3_BASE             (APB1PERIPH_BASE + 0x0400UL)
-#define STM32_TIM4_BASE             (APB1PERIPH_BASE + 0x0800UL)
-#define STM32_TIM5_BASE             (APB1PERIPH_BASE + 0x0C00UL)
-#define STM32_TIM6_BASE             (APB1PERIPH_BASE + 0x1000UL)
-#define STM32_TIM7_BASE             (APB1PERIPH_BASE + 0x1400UL)
-#define STM32_RTC_BASE              (APB1PERIPH_BASE + 0x2800UL)
-#define STM32_WWDG_BASE             (APB1PERIPH_BASE + 0x2C00UL)
-#define STM32_IWDG_BASE             (APB1PERIPH_BASE + 0x3000UL)
-#define STM32_SPI2_BASE             (APB1PERIPH_BASE + 0x3800UL)
-#define STM32_SPI3_BASE             (APB1PERIPH_BASE + 0x3C00UL)
-#define STM32_USART2_BASE           (APB1PERIPH_BASE + 0x4400UL)
-#define STM32_USART3_BASE           (APB1PERIPH_BASE + 0x4800UL)
-#define STM32_USART4_BASE           (APB1PERIPH_BASE + 0x4c00UL)
-#define STM32_USART5_BASE           (APB1PERIPH_BASE + 0x5000UL)
-#define STM32_I2C1_BASE             (APB1PERIPH_BASE + 0x5400UL)
-#define STM32_I2C2_BASE             (APB1PERIPH_BASE + 0x5800UL)
-#define STM32_I2C3_BASE             (APB1PERIPH_BASE + 0x5C00UL)
-#define STM32_CRS_BASE              (APB1PERIPH_BASE + 0x6000UL)
-#define STM32_PWR_BASE              (APB1PERIPH_BASE + 0x7000UL)
-#define STM32_DAC_BASE              (APB1PERIPH_BASE + 0x7400UL)
-#define STM32_DAC1_BASE             (APB1PERIPH_BASE + 0x7400UL)
-#define STM32_OPAMP_BASE            (APB1PERIPH_BASE + 0x7800UL)
-#define STM32_LPTIM1_BASE           (APB1PERIPH_BASE + 0x7C00UL)
-#define STM32_LPUART1_BASE          (APB1PERIPH_BASE + 0x8000UL)
-#define STM32_I2C4_BASE             (APB1PERIPH_BASE + 0x8400UL)
-#define STM32_LPTIM2_BASE           (APB1PERIPH_BASE + 0x9400UL)
-#define STM32_LPTIM3_BASE           (APB1PERIPH_BASE + 0x9800UL)
-#define STM32_FDCAN_RAM_BASE        (APB1PERIPH_BASE + 0xA400UL)
-#define STM32_CAN_RAM_BASE          (APB1PERIPH_BASE + 0xAC00UL)
-#define STM32_USB_FS_BASE           (APB1PERIPH_BASE + 0xD400UL)
-#define STM32_USB_CAN_SRAM_BASE     (APB1PERIPH_BASE + 0xD800UL)
-#define STM32_UCPD1_BASE            (APB1PERIPH_BASE + 0xDC00UL)
+#define STM32_TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
+#define STM32_TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
+#define STM32_TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
+#define STM32_TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
+#define STM32_TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
+#define STM32_TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
+#define STM32_RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
+#define STM32_WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
+#define STM32_IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
+#define STM32_SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
+#define STM32_SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
+#define STM32_USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
+#define STM32_USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
+#define STM32_USART4_BASE (APB1PERIPH_BASE + 0x4c00UL)
+#define STM32_USART5_BASE (APB1PERIPH_BASE + 0x5000UL)
+#define STM32_I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
+#define STM32_I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
+#define STM32_I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)
+#define STM32_CRS_BASE (APB1PERIPH_BASE + 0x6000UL)
+#define STM32_PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
+#define STM32_DAC_BASE (APB1PERIPH_BASE + 0x7400UL)
+#define STM32_DAC1_BASE (APB1PERIPH_BASE + 0x7400UL)
+#define STM32_OPAMP_BASE (APB1PERIPH_BASE + 0x7800UL)
+#define STM32_LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL)
+#define STM32_LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL)
+#define STM32_I2C4_BASE (APB1PERIPH_BASE + 0x8400UL)
+#define STM32_LPTIM2_BASE (APB1PERIPH_BASE + 0x9400UL)
+#define STM32_LPTIM3_BASE (APB1PERIPH_BASE + 0x9800UL)
+#define STM32_FDCAN_RAM_BASE (APB1PERIPH_BASE + 0xA400UL)
+#define STM32_CAN_RAM_BASE (APB1PERIPH_BASE + 0xAC00UL)
+#define STM32_USB_FS_BASE (APB1PERIPH_BASE + 0xD400UL)
+#define STM32_USB_CAN_SRAM_BASE (APB1PERIPH_BASE + 0xD800UL)
+#define STM32_UCPD1_BASE (APB1PERIPH_BASE + 0xDC00UL)
 
 /*!< APB2 peripherals */
-#define STM32_SYSCFG_BASE           (APB2PERIPH_BASE + 0x0000UL)
-#define STM32_EXTI_BASE             (AHB1PERIPH_BASE + 0xf400UL)
-#define STM32_TIM1_BASE             (APB2PERIPH_BASE + 0x2C00UL)
-#define STM32_SPI1_BASE             (APB2PERIPH_BASE + 0x3000UL)
-#define STM32_TIM8_BASE             (APB2PERIPH_BASE + 0x3400UL)
-#define STM32_USART1_BASE           (APB2PERIPH_BASE + 0x3800UL)
-#define STM32_TIM15_BASE            (APB2PERIPH_BASE + 0x4000UL)
-#define STM32_TIM16_BASE            (APB2PERIPH_BASE + 0x4400UL)
-#define STM32_TIM17_BASE            (APB2PERIPH_BASE + 0x4800UL)
+#define STM32_SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL)
+#define STM32_EXTI_BASE (AHB1PERIPH_BASE + 0xf400UL)
+#define STM32_TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL)
+#define STM32_SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
+#define STM32_TIM8_BASE (APB2PERIPH_BASE + 0x3400UL)
+#define STM32_USART1_BASE (APB2PERIPH_BASE + 0x3800UL)
+#define STM32_TIM15_BASE (APB2PERIPH_BASE + 0x4000UL)
+#define STM32_TIM16_BASE (APB2PERIPH_BASE + 0x4400UL)
+#define STM32_TIM17_BASE (APB2PERIPH_BASE + 0x4800UL)
 
 /*!< AHB1 peripherals */
-#define STM32_DMA1_BASE             (AHB1PERIPH_BASE + 0x0000UL)
-#define STM32_DMA2_BASE             (AHB1PERIPH_BASE + 0x0400UL)
-#define STM32_RCC_BASE              (AHB1PERIPH_BASE + 0x1000UL)
-#define STM32_FLASH_R_BASE          (AHB1PERIPH_BASE + 0x2000UL)
-#define STM32_CRC_BASE              (AHB1PERIPH_BASE + 0x3000UL)
-#define STM32_DMA1_Channel1_BASE    (DMA1_BASE + 0x0008UL)
-#define STM32_DMA1_Channel2_BASE    (DMA1_BASE + 0x001CUL)
-#define STM32_DMA1_Channel3_BASE    (DMA1_BASE + 0x0030UL)
-#define STM32_DMA1_Channel4_BASE    (DMA1_BASE + 0x0044UL)
-#define STM32_DMA1_Channel5_BASE    (DMA1_BASE + 0x0058UL)
-#define STM32_DMA1_Channel6_BASE    (DMA1_BASE + 0x006CUL)
-#define STM32_DMA1_Channel7_BASE    (DMA1_BASE + 0x0080UL)
-#define STM32_DMA1_CSELR_BASE       (DMA1_BASE + 0x00A8UL)
-#define STM32_DMA2_Channel1_BASE    (DMA2_BASE + 0x0008UL)
-#define STM32_DMA2_Channel2_BASE    (DMA2_BASE + 0x001CUL)
-#define STM32_DMA2_Channel3_BASE    (DMA2_BASE + 0x0030UL)
-#define STM32_DMA2_Channel4_BASE    (DMA2_BASE + 0x0044UL)
-#define STM32_DMA2_Channel5_BASE    (DMA2_BASE + 0x0058UL)
-#define STM32_DMA2_Channel6_BASE    (DMA2_BASE + 0x006CUL)
-#define STM32_DMA2_Channel7_BASE    (DMA2_BASE + 0x0080UL)
-#define STM32_DMA2_CSELR_BASE       (DMA2_BASE + 0x00A8UL)
+#define STM32_DMA1_BASE (AHB1PERIPH_BASE + 0x0000UL)
+#define STM32_DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL)
+#define STM32_DMAMUX_BASE (AHB1PERIPH_BASE + 0x0800UL)
+#define STM32_RCC_BASE (AHB1PERIPH_BASE + 0x1000UL)
+#define STM32_FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL)
+#define STM32_CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
+#define STM32_DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL)
+#define STM32_DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL)
+#define STM32_DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL)
+#define STM32_DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL)
+#define STM32_DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL)
+#define STM32_DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL)
+#define STM32_DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL)
+#define STM32_DMA1_CSELR_BASE (DMA1_BASE + 0x00A8UL)
+#define STM32_DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL)
+#define STM32_DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL)
+#define STM32_DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL)
+#define STM32_DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL)
+#define STM32_DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL)
+#define STM32_DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL)
+#define STM32_DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL)
+#define STM32_DMA2_CSELR_BASE (DMA2_BASE + 0x00A8UL)
 
 /*!< AHB2 peripherals */
-#define STM32_GPIOA_BASE            (AHB2PERIPH_BASE + 0x20000UL)
-#define STM32_GPIOB_BASE            (AHB2PERIPH_BASE + 0x20400UL)
-#define STM32_GPIOC_BASE            (AHB2PERIPH_BASE + 0x20800UL)
-#define STM32_GPIOD_BASE            (AHB2PERIPH_BASE + 0x20C00UL)
-#define STM32_GPIOE_BASE            (AHB2PERIPH_BASE + 0x21000UL)
-#define STM32_GPIOF_BASE            (AHB2PERIPH_BASE + 0x21400UL)
-#define STM32_GPIOG_BASE            (AHB2PERIPH_BASE + 0x21800UL)
-#define STM32_GPIOH_BASE            (AHB2PERIPH_BASE + 0x21C00UL)
-#define STM32_RNG_BASE              (AHB2PERIPH_BASE + 0xC4000UL)
+#define STM32_GPIOA_BASE (AHB2PERIPH_BASE + 0x20000UL)
+#define STM32_GPIOB_BASE (AHB2PERIPH_BASE + 0x20400UL)
+#define STM32_GPIOC_BASE (AHB2PERIPH_BASE + 0x20800UL)
+#define STM32_GPIOD_BASE (AHB2PERIPH_BASE + 0x20C00UL)
+#define STM32_GPIOE_BASE (AHB2PERIPH_BASE + 0x21000UL)
+#define STM32_GPIOF_BASE (AHB2PERIPH_BASE + 0x21400UL)
+#define STM32_GPIOG_BASE (AHB2PERIPH_BASE + 0x21800UL)
+#define STM32_GPIOH_BASE (AHB2PERIPH_BASE + 0x21C00UL)
+#define STM32_RNG_BASE (AHB2PERIPH_BASE + 0xC4000UL)
 
 /* Debug MCU registers base address */
-#define STM32_PACKAGE_BASE          0x0BFA0500UL
-#define STM32_UID_BASE              0x0BFA0590UL
-#define STM32_FLASHSIZE_BASE        0x0BFA05E0UL
+#define STM32_PACKAGE_BASE 0x0BFA0500UL
+#define STM32_UID_BASE 0x0BFA0590UL
+#define STM32_FLASHSIZE_BASE 0x0BFA05E0UL
 
-#define STM32_FLASH_REGS_BASE       STM32_FLASH_R_BASE
-#define STM32_UNIQUE_ID_BASE        STM32_UID_BASE
+#define STM32_FLASH_REGS_BASE STM32_FLASH_R_BASE
+#define STM32_UNIQUE_ID_BASE STM32_UID_BASE
 
 #ifndef __ASSEMBLER__
 
 /* Register definitions */
 
 /* --- USART --- */
-#define STM32_USART_CR1(base)       STM32_USART_REG(base, 0x00)
-#define STM32_USART_CR1_UE          BIT(0)
-#define STM32_USART_CR1_UESM        BIT(1)
-#define STM32_USART_CR1_RE          BIT(2)
-#define STM32_USART_CR1_TE          BIT(3)
-#define STM32_USART_CR1_RXNEIE      BIT(5)
-#define STM32_USART_CR1_TCIE        BIT(6)
-#define STM32_USART_CR1_TXEIE       BIT(7)
-#define STM32_USART_CR1_PS          BIT(9)
-#define STM32_USART_CR1_PCE         BIT(10)
-#define STM32_USART_CR1_M           BIT(12)
-#define STM32_USART_CR1_OVER8       BIT(15)
-
-#define STM32_USART_CR2(base)       STM32_USART_REG(base, 0x04)
-#define STM32_USART_CR2_SWAP        BIT(15)
-
-#define STM32_USART_CR3(base)       STM32_USART_REG(base, 0x08)
-#define STM32_USART_CR3_EIE         BIT(0)
-#define STM32_USART_CR3_DMAR        BIT(6)
-#define STM32_USART_CR3_DMAT        BIT(7)
-#define STM32_USART_CR3_ONEBIT      BIT(11)
-#define STM32_USART_CR3_OVRDIS      BIT(12)
+#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00)
+#define STM32_USART_CR1_UE BIT(0)
+#define STM32_USART_CR1_UESM BIT(1)
+#define STM32_USART_CR1_RE BIT(2)
+#define STM32_USART_CR1_TE BIT(3)
+#define STM32_USART_CR1_RXNEIE BIT(5)
+#define STM32_USART_CR1_TCIE BIT(6)
+#define STM32_USART_CR1_TXEIE BIT(7)
+#define STM32_USART_CR1_PS BIT(9)
+#define STM32_USART_CR1_PCE BIT(10)
+#define STM32_USART_CR1_M BIT(12)
+#define STM32_USART_CR1_OVER8 BIT(15)
+
+#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04)
+#define STM32_USART_CR2_SWAP BIT(15)
+
+#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08)
+#define STM32_USART_CR3_EIE BIT(0)
+#define STM32_USART_CR3_DMAR BIT(6)
+#define STM32_USART_CR3_DMAT BIT(7)
+#define STM32_USART_CR3_ONEBIT BIT(11)
+#define STM32_USART_CR3_OVRDIS BIT(12)
 #define STM32_USART_CR3_WUS_START_BIT (2 << 20)
-#define STM32_USART_CR3_WUFIE       BIT(22)
-
-#define STM32_USART_BRR(base)       STM32_USART_REG(base, 0x0C)
-#define STM32_USART_GTPR(base)      STM32_USART_REG(base, 0x10)
-#define STM32_USART_RTOR(base)      STM32_USART_REG(base, 0x14)
-#define STM32_USART_RQR(base)       STM32_USART_REG(base, 0x18)
-#define STM32_USART_ISR(base)       STM32_USART_REG(base, 0x1C)
-#define STM32_USART_ICR(base)       STM32_USART_REG(base, 0x20)
-#define STM32_USART_ICR_ORECF       BIT(3)
-#define STM32_USART_ICR_TCCF        BIT(6)
-#define STM32_USART_RDR(base)       STM32_USART_REG(base, 0x24)
-#define STM32_USART_TDR(base)       STM32_USART_REG(base, 0x28)
-#define STM32_USART_PRESC(base)     STM32_USART_REG(base, 0x2C)
+#define STM32_USART_CR3_WUFIE BIT(22)
+
+#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C)
+#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10)
+#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14)
+#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18)
+#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C)
+#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20)
+#define STM32_USART_ICR_ORECF BIT(3)
+#define STM32_USART_ICR_TCCF BIT(6)
+#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24)
+#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28)
+#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C)
 /* register alias */
-#define STM32_USART_SR(base)        STM32_USART_ISR(base)
-#define STM32_USART_SR_ORE          BIT(3)
-#define STM32_USART_SR_RXNE         BIT(5)
-#define STM32_USART_SR_TC           BIT(6)
-#define STM32_USART_SR_TXE          BIT(7)
+#define STM32_USART_SR(base) STM32_USART_ISR(base)
+#define STM32_USART_SR_ORE BIT(3)
+#define STM32_USART_SR_RXNE BIT(5)
+#define STM32_USART_SR_TC BIT(6)
+#define STM32_USART_SR_TXE BIT(7)
 
 /* --- GPIO --- */
-#define STM32_GPIO_MODER(b)     REG32((b) + 0x00)
-#define STM32_GPIO_OTYPER(b)    REG16((b) + 0x04)
-#define STM32_GPIO_OSPEEDR(b)   REG32((b) + 0x08)
-#define STM32_GPIO_PUPDR(b)     REG32((b) + 0x0C)
-#define STM32_GPIO_IDR(b)       REG16((b) + 0x10)
-#define STM32_GPIO_ODR(b)       REG16((b) + 0x14)
-#define STM32_GPIO_BSRR(b)      REG32((b) + 0x18)
-#define STM32_GPIO_LCKR(b)      REG32((b) + 0x1C)
-#define STM32_GPIO_AFRL(b)      REG32((b) + 0x20)
-#define STM32_GPIO_AFRH(b)      REG32((b) + 0x24)
-#define STM32_GPIO_BRR(b)       REG32((b) + 0x28)
-#define STM32_GPIO_ASCR(b)      REG32((b) + 0x2C) /* only for stm32l4x6 */
-
-#define GPIO_ALT_F0		0x0
-#define GPIO_ALT_F1		0x1
-#define GPIO_ALT_F2		0x2
-#define GPIO_ALT_F3		0x3
-#define GPIO_ALT_F4		0x4
-#define GPIO_ALT_F5		0x5
-#define GPIO_ALT_F6		0x6
-#define GPIO_ALT_F7		0x7
-#define GPIO_ALT_F8		0x8
-#define GPIO_ALT_F9		0x9
-#define GPIO_ALT_FA		0xA
-#define GPIO_ALT_FB		0xB
-#define GPIO_ALT_FC		0xC
-#define GPIO_ALT_FD		0xD
-#define GPIO_ALT_FE		0xE
-#define GPIO_ALT_FF		0xF
+#define STM32_GPIO_MODER(b) REG32((b) + 0x00)
+#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04)
+#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08)
+#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C)
+#define STM32_GPIO_IDR(b) REG16((b) + 0x10)
+#define STM32_GPIO_ODR(b) REG16((b) + 0x14)
+#define STM32_GPIO_BSRR(b) REG32((b) + 0x18)
+#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C)
+#define STM32_GPIO_AFRL(b) REG32((b) + 0x20)
+#define STM32_GPIO_AFRH(b) REG32((b) + 0x24)
+#define STM32_GPIO_BRR(b) REG32((b) + 0x28)
+#define STM32_GPIO_ASCR(b) REG32((b) + 0x2C) /* only for stm32l4x6 */
+
+#define GPIO_ALT_F0 0x0
+#define GPIO_ALT_F1 0x1
+#define GPIO_ALT_F2 0x2
+#define GPIO_ALT_F3 0x3
+#define GPIO_ALT_F4 0x4
+#define GPIO_ALT_F5 0x5
+#define GPIO_ALT_F6 0x6
+#define GPIO_ALT_F7 0x7
+#define GPIO_ALT_F8 0x8
+#define GPIO_ALT_F9 0x9
+#define GPIO_ALT_FA 0xA
+#define GPIO_ALT_FB 0xB
+#define GPIO_ALT_FC 0xC
+#define GPIO_ALT_FD 0xD
+#define GPIO_ALT_FE 0xE
+#define GPIO_ALT_FF 0xF
 
 /* --- I2C --- */
-#define STM32_I2C_CR1(n)            REG32(stm32_i2c_reg(n, 0x00))
-#define STM32_I2C_CR1_PE            BIT(0)
-#define STM32_I2C_CR1_TXIE          BIT(1)
-#define STM32_I2C_CR1_RXIE          BIT(2)
-#define STM32_I2C_CR1_ADDRIE        BIT(3)
-#define STM32_I2C_CR1_NACKIE        BIT(4)
-#define STM32_I2C_CR1_STOPIE        BIT(5)
-#define STM32_I2C_CR1_ERRIE         BIT(7)
-#define STM32_I2C_CR1_WUPEN         BIT(18)
-#define STM32_I2C_CR2(n)            REG32(stm32_i2c_reg(n, 0x04))
-#define STM32_I2C_CR2_RD_WRN        BIT(10)
-#define STM32_I2C_CR2_START         BIT(13)
-#define STM32_I2C_CR2_STOP          BIT(14)
-#define STM32_I2C_CR2_NACK          BIT(15)
-#define STM32_I2C_CR2_RELOAD        BIT(24)
-#define STM32_I2C_CR2_AUTOEND       BIT(25)
-#define STM32_I2C_OAR1(n)           REG32(stm32_i2c_reg(n, 0x08))
-#define STM32_I2C_OAR2(n)           REG32(stm32_i2c_reg(n, 0x0C))
-#define STM32_I2C_TIMINGR(n)        REG32(stm32_i2c_reg(n, 0x10))
-#define STM32_I2C_TIMEOUTR(n)       REG32(stm32_i2c_reg(n, 0x14))
-#define STM32_I2C_ISR(n)            REG32(stm32_i2c_reg(n, 0x18))
-#define STM32_I2C_ISR_TXE           BIT(0)
-#define STM32_I2C_ISR_TXIS          BIT(1)
-#define STM32_I2C_ISR_RXNE          BIT(2)
-#define STM32_I2C_ISR_ADDR          BIT(3)
-#define STM32_I2C_ISR_NACK          BIT(4)
-#define STM32_I2C_ISR_STOP          BIT(5)
-#define STM32_I2C_ISR_TC            BIT(6)
-#define STM32_I2C_ISR_TCR           BIT(7)
-#define STM32_I2C_ISR_BERR          BIT(8)
-#define STM32_I2C_ISR_ARLO          BIT(9)
-#define STM32_I2C_ISR_OVR           BIT(10)
-#define STM32_I2C_ISR_PECERR        BIT(11)
-#define STM32_I2C_ISR_TIMEOUT       BIT(12)
-#define STM32_I2C_ISR_ALERT         BIT(13)
-#define STM32_I2C_ISR_BUSY          BIT(15)
-#define STM32_I2C_ISR_DIR           BIT(16)
-#define STM32_I2C_ISR_ADDCODE(isr)  (((isr) >> 16) & 0xfe)
-#define STM32_I2C_ICR(n)            REG32(stm32_i2c_reg(n, 0x1C))
-#define STM32_I2C_ICR_ADDRCF        BIT(3)
-#define STM32_I2C_ICR_NACKCF        BIT(4)
-#define STM32_I2C_ICR_STOPCF        BIT(5)
-#define STM32_I2C_ICR_BERRCF        BIT(8)
-#define STM32_I2C_ICR_ARLOCF        BIT(9)
-#define STM32_I2C_ICR_OVRCF         BIT(10)
-#define STM32_I2C_ICR_TIMEOUTCF     BIT(12)
-#define STM32_I2C_ICR_ALL           0x3F38
-#define STM32_I2C_PECR(n)           REG32(stm32_i2c_reg(n, 0x20))
-#define STM32_I2C_RXDR(n)           REG32(stm32_i2c_reg(n, 0x24))
-#define STM32_I2C_TXDR(n)           REG32(stm32_i2c_reg(n, 0x28))
+#define STM32_I2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00))
+#define STM32_I2C_CR1_PE BIT(0)
+#define STM32_I2C_CR1_TXIE BIT(1)
+#define STM32_I2C_CR1_RXIE BIT(2)
+#define STM32_I2C_CR1_ADDRIE BIT(3)
+#define STM32_I2C_CR1_NACKIE BIT(4)
+#define STM32_I2C_CR1_STOPIE BIT(5)
+#define STM32_I2C_CR1_ERRIE BIT(7)
+#define STM32_I2C_CR1_WUPEN BIT(18)
+#define STM32_I2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04))
+#define STM32_I2C_CR2_RD_WRN BIT(10)
+#define STM32_I2C_CR2_START BIT(13)
+#define STM32_I2C_CR2_STOP BIT(14)
+#define STM32_I2C_CR2_NACK BIT(15)
+#define STM32_I2C_CR2_RELOAD BIT(24)
+#define STM32_I2C_CR2_AUTOEND BIT(25)
+#define STM32_I2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08))
+#define STM32_I2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C))
+#define STM32_I2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10))
+#define STM32_I2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14))
+#define STM32_I2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18))
+#define STM32_I2C_ISR_TXE BIT(0)
+#define STM32_I2C_ISR_TXIS BIT(1)
+#define STM32_I2C_ISR_RXNE BIT(2)
+#define STM32_I2C_ISR_ADDR BIT(3)
+#define STM32_I2C_ISR_NACK BIT(4)
+#define STM32_I2C_ISR_STOP BIT(5)
+#define STM32_I2C_ISR_TC BIT(6)
+#define STM32_I2C_ISR_TCR BIT(7)
+#define STM32_I2C_ISR_BERR BIT(8)
+#define STM32_I2C_ISR_ARLO BIT(9)
+#define STM32_I2C_ISR_OVR BIT(10)
+#define STM32_I2C_ISR_PECERR BIT(11)
+#define STM32_I2C_ISR_TIMEOUT BIT(12)
+#define STM32_I2C_ISR_ALERT BIT(13)
+#define STM32_I2C_ISR_BUSY BIT(15)
+#define STM32_I2C_ISR_DIR BIT(16)
+#define STM32_I2C_ISR_ADDCODE(isr) (((isr) >> 16) & 0xfe)
+#define STM32_I2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C))
+#define STM32_I2C_ICR_ADDRCF BIT(3)
+#define STM32_I2C_ICR_NACKCF BIT(4)
+#define STM32_I2C_ICR_STOPCF BIT(5)
+#define STM32_I2C_ICR_BERRCF BIT(8)
+#define STM32_I2C_ICR_ARLOCF BIT(9)
+#define STM32_I2C_ICR_OVRCF BIT(10)
+#define STM32_I2C_ICR_TIMEOUTCF BIT(12)
+#define STM32_I2C_ICR_ALL 0x3F38
+#define STM32_I2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20))
+#define STM32_I2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24))
+#define STM32_I2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28))
 
 /* --- Power / Reset / Clocks --- */
-#define STM32_PWR_CR1               REG32(STM32_PWR_BASE + 0x00)
-#define STM32_PWR_CR2               REG32(STM32_PWR_BASE + 0x04)
-#define STM32_PWR_CSR               REG32(STM32_PWR_BASE + 0x10)
-#define STM32_PWR_SCR               REG32(STM32_PWR_BASE + 0x18)
-
-#define PWR_CR1_LPMS_POS             0U
-#define PWR_CR1_LPMS_MSK             (0x7UL << PWR_CR1_LPMS_POS)
-#define PWR_CR1_LPMS                 PWR_CR1_LPMS_MSK
-#define PWR_CR1_LPMS_STOP0           (0x00000000UL)
-#define PWR_CR1_LPMS_STOP1_POS       0U
-#define PWR_CR1_LPMS_STOP1_MSK       (0x1UL << PWR_CR1_LPMS_STOP1_POS)
-#define PWR_CR1_LPMS_STOP1           PWR_CR1_LPMS_STOP1_MSK
-#define PWR_CR1_LPMS_STOP2_POS       1U
-#define PWR_CR1_LPMS_STOP2_MSK       (0x1UL << PWR_CR1_LPMS_STOP2_POS)
-#define PWR_CR1_LPMS_STOP2           PWR_CR1_LPMS_STOP2_MSK
-#define PWR_CR1_LPMS_STANDBY_POS     0U
-#define PWR_CR1_LPMS_STANDBY_MSK     (0x3UL << PWR_CR1_LPMS_STANDBY_POS)
-#define PWR_CR1_LPMS_STANDBY         PWR_CR1_LPMS_STANDBY_MSK
-#define PWR_CR1_LPMS_SHUTDOWN_POS    2U
-#define PWR_CR1_LPMS_SHUTDOWN_MSK    (0x1UL << PWR_CR1_LPMS_SHUTDOWN_POS)
-#define PWR_CR1_LPMS_SHUTDOWN        PWR_CR1_LPMS_SHUTDOWN_MSK
-#define PWR_CR1_VOS_POS              9U
-#define PWR_CR1_VOS_MSK              (0x3UL << PWR_CR1_VOS_POS)
-#define PWR_CR1_VOS                  PWR_CR1_VOS_MSK
-#define PWR_CR1_VOS_0                (0x1UL << PWR_CR1_VOS_POS)
-#define PWR_CR1_VOS_1                (0x2UL << PWR_CR1_VOS_POS)
-
-#define STM32_PWR_CR2_IOSV_POS       9U
-#define STM32_PWR_CR2_IOSV_MASK      BIT(STM32_PWR_CR2_IOSV_POS)
-#define STM32_PWR_CR2_IOSV           STM32_PWR_CR2_IOSV_MASK
-#define STM32_PWR_CR2_USV_POS        10U
-#define STM32_PWR_CR2_USV_MASK       BIT(STM32_PWR_CR2_USV_POS)
-#define STM32_PWR_CR2_USV            STM32_PWR_CR2_USV_MASK
-
+#define STM32_PWR_CR1 REG32(STM32_PWR_BASE + 0x00)
+#define STM32_PWR_CR2 REG32(STM32_PWR_BASE + 0x04)
+#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x10)
+#define STM32_PWR_SCR REG32(STM32_PWR_BASE + 0x18)
+
+#define PWR_CR1_LPMS_POS 0U
+#define PWR_CR1_LPMS_MSK (0x7UL << PWR_CR1_LPMS_POS)
+#define PWR_CR1_LPMS PWR_CR1_LPMS_MSK
+#define PWR_CR1_LPMS_STOP0 (0x00000000UL)
+#define PWR_CR1_LPMS_STOP1_POS 0U
+#define PWR_CR1_LPMS_STOP1_MSK (0x1UL << PWR_CR1_LPMS_STOP1_POS)
+#define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_MSK
+#define PWR_CR1_LPMS_STOP2_POS 1U
+#define PWR_CR1_LPMS_STOP2_MSK (0x1UL << PWR_CR1_LPMS_STOP2_POS)
+#define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_MSK
+#define PWR_CR1_LPMS_STANDBY_POS 0U
+#define PWR_CR1_LPMS_STANDBY_MSK (0x3UL << PWR_CR1_LPMS_STANDBY_POS)
+#define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_MSK
+#define PWR_CR1_LPMS_SHUTDOWN_POS 2U
+#define PWR_CR1_LPMS_SHUTDOWN_MSK (0x1UL << PWR_CR1_LPMS_SHUTDOWN_POS)
+#define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_MSK
+#define PWR_CR1_VOS_POS 9U
+#define PWR_CR1_VOS_MSK (0x3UL << PWR_CR1_VOS_POS)
+#define PWR_CR1_VOS PWR_CR1_VOS_MSK
+#define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_POS)
+#define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_POS)
+
+#define STM32_PWR_CR2_IOSV_POS 9U
+#define STM32_PWR_CR2_IOSV_MASK BIT(STM32_PWR_CR2_IOSV_POS)
+#define STM32_PWR_CR2_IOSV STM32_PWR_CR2_IOSV_MASK
+#define STM32_PWR_CR2_USV_POS 10U
+#define STM32_PWR_CR2_USV_MASK BIT(STM32_PWR_CR2_USV_POS)
+#define STM32_PWR_CR2_USV STM32_PWR_CR2_USV_MASK
 
 /* --- Macro usage in ec code --- */
 #define STM32_RCC_AHB2ENR_GPIOMASK                               \
@@ -387,139 +386,137 @@
 #define STM32_RCC_ICSCR_MSIRANGE_1MHZ STM32_RCC_ICSCR_MSIRANGE(4)
 #define STM32_RCC_ICSCR_MSIRANGE_2MHZ STM32_RCC_ICSCR_MSIRANGE(5)
 #define STM32_RCC_ICSCR_MSIRANGE_MASK STM32_RCC_CR_MSIRANGE_MSK
-#define STM32_RCC_SYSCFGEN            STM32_RCC_APB2ENR_SYSCFGEN
+#define STM32_RCC_SYSCFGEN STM32_RCC_APB2ENR_SYSCFGEN
 
-#define STM32_RCC_PB2_TIM1            STM32_RCC_APB2ENR_TIM1EN
-#define STM32_RCC_PB2_TIM15           STM32_RCC_APB2ENR_TIM15EN
-#define STM32_RCC_PB2_TIM16           STM32_RCC_APB2ENR_TIM16EN
+#define STM32_RCC_PB2_TIM1 STM32_RCC_APB2ENR_TIM1EN
+#define STM32_RCC_PB2_TIM15 STM32_RCC_APB2ENR_TIM15EN
+#define STM32_RCC_PB2_TIM16 STM32_RCC_APB2ENR_TIM16EN
 #ifndef CHIP_VARIANT_STM32L431X
-#define STM32_RCC_PB2_TIM8            BIT(13)
+#define STM32_RCC_PB2_TIM8 BIT(13)
 #endif
 #define STM32_RCC_PWREN STM32_RCC_APB1ENR1_PWREN
 
-#define STM32_RCC_AHB2ENR_GPIO_PORTA	BIT(0)
-#define STM32_RCC_AHB2ENR_GPIO_PORTB	BIT(1)
-#define STM32_RCC_AHB2ENR_GPIO_PORTC	BIT(2)
-#define STM32_RCC_AHB2ENR_GPIO_PORTD	BIT(3)
-#define STM32_RCC_AHB2ENR_GPIO_PORTE	BIT(4)
-#define STM32_RCC_AHB2ENR_GPIO_PORTH	BIT(7)
+#define STM32_RCC_AHB2ENR_GPIO_PORTA BIT(0)
+#define STM32_RCC_AHB2ENR_GPIO_PORTB BIT(1)
+#define STM32_RCC_AHB2ENR_GPIO_PORTC BIT(2)
+#define STM32_RCC_AHB2ENR_GPIO_PORTD BIT(3)
+#define STM32_RCC_AHB2ENR_GPIO_PORTE BIT(4)
+#define STM32_RCC_AHB2ENR_GPIO_PORTH BIT(7)
 #define STM32_RCC_CCIPR_USART1SEL_SHIFT (0)
-#define STM32_RCC_CCIPR_USART1SEL_MASK  (3 << STM32_RCC_CCIPR_USART1SEL_SHIFT)
+#define STM32_RCC_CCIPR_USART1SEL_MASK (3 << STM32_RCC_CCIPR_USART1SEL_SHIFT)
 #define STM32_RCC_CCIPR_USART2SEL_SHIFT (2)
-#define STM32_RCC_CCIPR_USART2SEL_MASK  (3 << STM32_RCC_CCIPR_USART2SEL_SHIFT)
+#define STM32_RCC_CCIPR_USART2SEL_MASK (3 << STM32_RCC_CCIPR_USART2SEL_SHIFT)
 #define STM32_RCC_CCIPR_USART3SEL_SHIFT (4)
-#define STM32_RCC_CCIPR_USART3SEL_MASK  (3 << STM32_RCC_CCIPR_USART3SEL_SHIFT)
+#define STM32_RCC_CCIPR_USART3SEL_MASK (3 << STM32_RCC_CCIPR_USART3SEL_SHIFT)
 #define STM32_RCC_CCIPR_UART4SEL_SHIFT (6)
-#define STM32_RCC_CCIPR_UART4SEL_MASK  (3 << STM32_RCC_CCIPR_UART4SEL_SHIFT)
+#define STM32_RCC_CCIPR_UART4SEL_MASK (3 << STM32_RCC_CCIPR_UART4SEL_SHIFT)
 #define STM32_RCC_CCIPR_UART5SEL_SHIFT (8)
-#define STM32_RCC_CCIPR_UART5SEL_MASK  (3 << STM32_RCC_CCIPR_UART5SEL_SHIFT)
+#define STM32_RCC_CCIPR_UART5SEL_MASK (3 << STM32_RCC_CCIPR_UART5SEL_SHIFT)
 #define STM32_RCC_CCIPR_LPUART1SEL_SHIFT (10)
-#define STM32_RCC_CCIPR_LPUART1SEL_MASK  (3 << STM32_RCC_CCIPR_LPUART1SEL_SHIFT)
+#define STM32_RCC_CCIPR_LPUART1SEL_MASK (3 << STM32_RCC_CCIPR_LPUART1SEL_SHIFT)
 #define STM32_RCC_CCIPR_I2C1SEL_SHIFT (12)
-#define STM32_RCC_CCIPR_I2C1SEL_MASK  (3 << STM32_RCC_CCIPR_I2C1SEL_SHIFT)
+#define STM32_RCC_CCIPR_I2C1SEL_MASK (3 << STM32_RCC_CCIPR_I2C1SEL_SHIFT)
 #define STM32_RCC_CCIPR_I2C2SEL_SHIFT (14)
-#define STM32_RCC_CCIPR_I2C2SEL_MASK  (3 << STM32_RCC_CCIPR_I2C2SEL_SHIFT)
+#define STM32_RCC_CCIPR_I2C2SEL_MASK (3 << STM32_RCC_CCIPR_I2C2SEL_SHIFT)
 #define STM32_RCC_CCIPR_I2C3SEL_SHIFT (16)
-#define STM32_RCC_CCIPR_I2C3SEL_MASK  (3 << STM32_RCC_CCIPR_I2C3SEL_SHIFT)
+#define STM32_RCC_CCIPR_I2C3SEL_MASK (3 << STM32_RCC_CCIPR_I2C3SEL_SHIFT)
 #define STM32_RCC_CCIPR_LPTIM1SEL_SHIFT (18)
-#define STM32_RCC_CCIPR_LPTIM1SEL_MASK  (3 << STM32_RCC_CCIPR_LPTIM1SEL_SHIFT)
+#define STM32_RCC_CCIPR_LPTIM1SEL_MASK (3 << STM32_RCC_CCIPR_LPTIM1SEL_SHIFT)
 #define STM32_RCC_CCIPR_LPTIM2SEL_SHIFT (20)
-#define STM32_RCC_CCIPR_LPTIM2SEL_MASK  (3 << STM32_RCC_CCIPR_LPTIM2SEL_SHIFT)
+#define STM32_RCC_CCIPR_LPTIM2SEL_MASK (3 << STM32_RCC_CCIPR_LPTIM2SEL_SHIFT)
 #define STM32_RCC_CCIPR_SAI1SEL_SHIFT (22)
-#define STM32_RCC_CCIPR_SAI1SEL_MASK  (3 << STM32_RCC_CCIPR_SAI1SEL_SHIFT)
+#define STM32_RCC_CCIPR_SAI1SEL_MASK (3 << STM32_RCC_CCIPR_SAI1SEL_SHIFT)
 #define STM32_RCC_CCIPR_SAI2SEL_SHIFT (24)
-#define STM32_RCC_CCIPR_SAI2SEL_MASK  (3 << STM32_RCC_CCIPR_SAI2SEL_SHIFT)
+#define STM32_RCC_CCIPR_SAI2SEL_MASK (3 << STM32_RCC_CCIPR_SAI2SEL_SHIFT)
 #define STM32_RCC_CCIPR_CLK48SEL_SHIFT (26)
-#define STM32_RCC_CCIPR_CLK48SEL_MASK  (3 << STM32_RCC_CCIPR_CLK48SEL_SHIFT)
+#define STM32_RCC_CCIPR_CLK48SEL_MASK (3 << STM32_RCC_CCIPR_CLK48SEL_SHIFT)
 #define STM32_RCC_CCIPR_ADCSEL_SHIFT (28)
-#define STM32_RCC_CCIPR_ADCSEL_MASK  (3 << STM32_RCC_CCIPR_ADCSEL_SHIFT)
+#define STM32_RCC_CCIPR_ADCSEL_MASK (3 << STM32_RCC_CCIPR_ADCSEL_SHIFT)
 #define STM32_RCC_CCIPR_SWPMI1SEL_SHIFT (30)
-#define STM32_RCC_CCIPR_SWPMI1SEL_MASK  BIT(STM32_RCC_CCIPR_SWPMI1SEL_SHIFT)
+#define STM32_RCC_CCIPR_SWPMI1SEL_MASK BIT(STM32_RCC_CCIPR_SWPMI1SEL_SHIFT)
 #define STM32_RCC_CCIPR_DFSDM1SEL_SHIFT (31)
-#define STM32_RCC_CCIPR_DFSDM1SEL_MASK  BIT(STM32_RCC_CCIPR_DFSDM1SEL_SHIFT)
+#define STM32_RCC_CCIPR_DFSDM1SEL_MASK BIT(STM32_RCC_CCIPR_DFSDM1SEL_SHIFT)
 /* Possible clock sources for each peripheral */
-#define STM32_RCC_CCIPR_UART_PCLK	0
-#define STM32_RCC_CCIPR_UART_SYSCLK	1
-#define STM32_RCC_CCIPR_UART_HSI16	2
-#define STM32_RCC_CCIPR_UART_LSE	3
-
-#define STM32_RCC_CCIPR_I2C_PCLK	0
-#define STM32_RCC_CCIPR_I2C_SYSCLK	1
-#define STM32_RCC_CCIPR_I2C_HSI16	2
-
-#define STM32_RCC_CCIPR_LPTIM_PCLK	0
-#define STM32_RCC_CCIPR_LPTIM_LSI	1
-#define STM32_RCC_CCIPR_LPTIM_HSI16	2
-#define STM32_RCC_CCIPR_LPTIM_LSE	3
-
-#define STM32_RCC_CCIPR_SAI_PLLSAI1CLK	0
-#define STM32_RCC_CCIPR_SAI_PLLSAI2CLK	1
-#define STM32_RCC_CCIPR_SAI_PLLSAI3CLK	2
-#define STM32_RCC_CCIPR_SAI_EXTCLK		3
-
-#define STM32_RCC_CCIPR_CLK48_NONE			0
-#define STM32_RCC_CCIPR_CLK48_PLL48M2CLK	1
-#define STM32_RCC_CCIPR_CLK48_PLL48M1CLK	2
-#define STM32_RCC_CCIPR_CLK48_MSI			3
-
-#define STM32_RCC_CCIPR_ADC_NONE		0
-#define STM32_RCC_CCIPR_ADC_PLLADC1CLK	1
-#define STM32_RCC_CCIPR_ADC_PLLADC2CLK	2
-#define STM32_RCC_CCIPR_ADC_SYSCLK	3
-
-#define STM32_RCC_CCIPR_SWPMI_PCLK	0
-#define STM32_RCC_CCIPR_SWPMI_HSI16	1
-
-#define STM32_RCC_CCIPR_DFSDM_PCLK		0
-#define STM32_RCC_CCIPR_DFSDM_SYSCLK	1
-
-
-
-#define STM32_RCC_CR          REG32(STM32_RCC_BASE + 0x00)
-#define STM32_RCC_ICSCR       REG32(STM32_RCC_BASE + 0x04)
-#define STM32_RCC_CFGR        REG32(STM32_RCC_BASE + 0x08)
-#define STM32_RCC_PLLCFGR     REG32(STM32_RCC_BASE + 0x0C)
+#define STM32_RCC_CCIPR_UART_PCLK 0
+#define STM32_RCC_CCIPR_UART_SYSCLK 1
+#define STM32_RCC_CCIPR_UART_HSI16 2
+#define STM32_RCC_CCIPR_UART_LSE 3
+
+#define STM32_RCC_CCIPR_I2C_PCLK 0
+#define STM32_RCC_CCIPR_I2C_SYSCLK 1
+#define STM32_RCC_CCIPR_I2C_HSI16 2
+
+#define STM32_RCC_CCIPR_LPTIM_PCLK 0
+#define STM32_RCC_CCIPR_LPTIM_LSI 1
+#define STM32_RCC_CCIPR_LPTIM_HSI16 2
+#define STM32_RCC_CCIPR_LPTIM_LSE 3
+
+#define STM32_RCC_CCIPR_SAI_PLLSAI1CLK 0
+#define STM32_RCC_CCIPR_SAI_PLLSAI2CLK 1
+#define STM32_RCC_CCIPR_SAI_PLLSAI3CLK 2
+#define STM32_RCC_CCIPR_SAI_EXTCLK 3
+
+#define STM32_RCC_CCIPR_CLK48_NONE 0
+#define STM32_RCC_CCIPR_CLK48_PLL48M2CLK 1
+#define STM32_RCC_CCIPR_CLK48_PLL48M1CLK 2
+#define STM32_RCC_CCIPR_CLK48_MSI 3
+
+#define STM32_RCC_CCIPR_ADC_NONE 0
+#define STM32_RCC_CCIPR_ADC_PLLADC1CLK 1
+#define STM32_RCC_CCIPR_ADC_PLLADC2CLK 2
+#define STM32_RCC_CCIPR_ADC_SYSCLK 3
+
+#define STM32_RCC_CCIPR_SWPMI_PCLK 0
+#define STM32_RCC_CCIPR_SWPMI_HSI16 1
+
+#define STM32_RCC_CCIPR_DFSDM_PCLK 0
+#define STM32_RCC_CCIPR_DFSDM_SYSCLK 1
+
+#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00)
+#define STM32_RCC_ICSCR REG32(STM32_RCC_BASE + 0x04)
+#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08)
+#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x0C)
 #define STM32_RCC_PLLSAI1CFGR REG32(STM32_RCC_BASE + 0x10)
-#define STM32_RCC_RESERVED    REG32(STM32_RCC_BASE + 0x14)
-#define STM32_RCC_CIER        REG32(STM32_RCC_BASE + 0x18)
-#define STM32_RCC_CIFR        REG32(STM32_RCC_BASE + 0x1C)
-#define STM32_RCC_CICR        REG32(STM32_RCC_BASE + 0x20)
-#define STM32_RCC_RESERVED0   REG32(STM32_RCC_BASE + 0x24)
-#define STM32_RCC_AHB1RSTR    REG32(STM32_RCC_BASE + 0x28)
-#define STM32_RCC_AHB2RSTR    REG32(STM32_RCC_BASE + 0x2C)
-#define STM32_RCC_AHB3RSTR    REG32(STM32_RCC_BASE + 0x30)
-#define STM32_RCC_RESERVED1   REG32(STM32_RCC_BASE + 0x34)
-#define STM32_RCC_APB1RSTR1   REG32(STM32_RCC_BASE + 0x38)
-#define STM32_RCC_APB1RSTR2   REG32(STM32_RCC_BASE + 0x3C)
-#define STM32_RCC_APB2RSTR    REG32(STM32_RCC_BASE + 0x40)
-#define STM32_RCC_RESERVED2   REG32(STM32_RCC_BASE + 0x44)
-#define STM32_RCC_AHB1ENR     REG32(STM32_RCC_BASE + 0x48)
-#define STM32_RCC_AHB2ENR     REG32(STM32_RCC_BASE + 0x4C)
-#define STM32_RCC_AHB3ENR     REG32(STM32_RCC_BASE + 0x50)
-#define STM32_RCC_RESERVED3   REG32(STM32_RCC_BASE + 0x54)
-#define STM32_RCC_APB1ENR1    REG32(STM32_RCC_BASE + 0x58)
-#define STM32_RCC_APB1ENR2    REG32(STM32_RCC_BASE + 0x5C)
-#define STM32_RCC_APB2ENR     REG32(STM32_RCC_BASE + 0x60)
-#define STM32_RCC_RESERVED4   REG32(STM32_RCC_BASE + 0x64)
-#define STM32_RCC_AHB1SMENR   REG32(STM32_RCC_BASE + 0x68)
-#define STM32_RCC_AHB2SMENR   REG32(STM32_RCC_BASE + 0x6C)
-#define STM32_RCC_AHB3SMENR   REG32(STM32_RCC_BASE + 0x70)
-#define STM32_RCC_RESERVED5   REG32(STM32_RCC_BASE + 0x74)
-#define STM32_RCC_APB1SMENR1  REG32(STM32_RCC_BASE + 0x78)
-#define STM32_RCC_APB1SMENR2  REG32(STM32_RCC_BASE + 0x7C)
-#define STM32_RCC_APB2SMENR   REG32(STM32_RCC_BASE + 0x80)
-#define STM32_RCC_RESERVED6   REG32(STM32_RCC_BASE + 0x84)
-#define STM32_RCC_CCIPR1      REG32(STM32_RCC_BASE + 0x88)
-#define STM32_RCC_CCIPR       STM32_RCC_CCIPR1
-#define STM32_RCC_RESERVED7   REG32(STM32_RCC_BASE + 0x8C)
-#define STM32_RCC_BDCR        REG32(STM32_RCC_BASE + 0x90)
-#define STM32_RCC_CSR         REG32(STM32_RCC_BASE + 0x94)
-#define STM32_RCC_CRRCR       REG32(STM32_RCC_BASE + 0x98)
-#define STM32_RCC_CCIPR2      REG32(STM32_RCC_BASE + 0x9C)
-#define STM32_CRS_CR          REG32(STM32_CRS_BASE + 0x00)
-#define STM32_CRS_CFGR        REG32(STM32_CRS_BASE + 0x04)
-#define STM32_CRS_ISR         REG32(STM32_CRS_BASE + 0x08)
-#define STM32_CRS_ICR         REG32(STM32_CRS_BASE + 0x0C)
+#define STM32_RCC_RESERVED REG32(STM32_RCC_BASE + 0x14)
+#define STM32_RCC_CIER REG32(STM32_RCC_BASE + 0x18)
+#define STM32_RCC_CIFR REG32(STM32_RCC_BASE + 0x1C)
+#define STM32_RCC_CICR REG32(STM32_RCC_BASE + 0x20)
+#define STM32_RCC_RESERVED0 REG32(STM32_RCC_BASE + 0x24)
+#define STM32_RCC_AHB1RSTR REG32(STM32_RCC_BASE + 0x28)
+#define STM32_RCC_AHB2RSTR REG32(STM32_RCC_BASE + 0x2C)
+#define STM32_RCC_AHB3RSTR REG32(STM32_RCC_BASE + 0x30)
+#define STM32_RCC_RESERVED1 REG32(STM32_RCC_BASE + 0x34)
+#define STM32_RCC_APB1RSTR1 REG32(STM32_RCC_BASE + 0x38)
+#define STM32_RCC_APB1RSTR2 REG32(STM32_RCC_BASE + 0x3C)
+#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x40)
+#define STM32_RCC_RESERVED2 REG32(STM32_RCC_BASE + 0x44)
+#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x48)
+#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x4C)
+#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x50)
+#define STM32_RCC_RESERVED3 REG32(STM32_RCC_BASE + 0x54)
+#define STM32_RCC_APB1ENR1 REG32(STM32_RCC_BASE + 0x58)
+#define STM32_RCC_APB1ENR2 REG32(STM32_RCC_BASE + 0x5C)
+#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x60)
+#define STM32_RCC_RESERVED4 REG32(STM32_RCC_BASE + 0x64)
+#define STM32_RCC_AHB1SMENR REG32(STM32_RCC_BASE + 0x68)
+#define STM32_RCC_AHB2SMENR REG32(STM32_RCC_BASE + 0x6C)
+#define STM32_RCC_AHB3SMENR REG32(STM32_RCC_BASE + 0x70)
+#define STM32_RCC_RESERVED5 REG32(STM32_RCC_BASE + 0x74)
+#define STM32_RCC_APB1SMENR1 REG32(STM32_RCC_BASE + 0x78)
+#define STM32_RCC_APB1SMENR2 REG32(STM32_RCC_BASE + 0x7C)
+#define STM32_RCC_APB2SMENR REG32(STM32_RCC_BASE + 0x80)
+#define STM32_RCC_RESERVED6 REG32(STM32_RCC_BASE + 0x84)
+#define STM32_RCC_CCIPR1 REG32(STM32_RCC_BASE + 0x88)
+#define STM32_RCC_CCIPR STM32_RCC_CCIPR1
+#define STM32_RCC_RESERVED7 REG32(STM32_RCC_BASE + 0x8C)
+#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x90)
+#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x94)
+#define STM32_RCC_CRRCR REG32(STM32_RCC_BASE + 0x98)
+#define STM32_RCC_CCIPR2 REG32(STM32_RCC_BASE + 0x9C)
+#define STM32_CRS_CR REG32(STM32_CRS_BASE + 0x00)
+#define STM32_CRS_CFGR REG32(STM32_CRS_BASE + 0x04)
+#define STM32_CRS_ISR REG32(STM32_CRS_BASE + 0x08)
+#define STM32_CRS_ICR REG32(STM32_CRS_BASE + 0x0C)
 
 #define STM32_RCC_PLLSAI1_SUPPORT
 #define STM32_RCC_PLLP_SUPPORT
@@ -527,236 +524,236 @@
 #define STM32_RCC_PLLP_DIV_2_31_SUPPORT
 #define STM32_RCC_PLLSAI1P_DIV_2_31_SUPPORT
 
-#define STM32_RCC_APB1ENR                STM32_RCC_APB1ENR1
+#define STM32_RCC_APB1ENR STM32_RCC_APB1ENR1
 
 /********************  BIT DEFINITION FOR STM32_RCC_CR REGISTER  **************/
-#define STM32_RCC_CR_MSION_POS           0U
-#define STM32_RCC_CR_MSION_MSK           (0x1UL << STM32_RCC_CR_MSION_POS)
-#define STM32_RCC_CR_MSION               STM32_RCC_CR_MSION_MSK
-#define STM32_RCC_CR_MSIRDY_POS          1U
-#define STM32_RCC_CR_MSIRDY_MSK          (0x1UL << STM32_RCC_CR_MSIRDY_POS)
-#define STM32_RCC_CR_MSIRDY              STM32_RCC_CR_MSIRDY_MSK
-#define STM32_RCC_CR_MSIPLLEN_POS        2U
-#define STM32_RCC_CR_MSIPLLEN_MSK        (0x1UL << STM32_RCC_CR_MSIPLLEN_POS)
-#define STM32_RCC_CR_MSIPLLEN            STM32_RCC_CR_MSIPLLEN_MSK
-#define STM32_RCC_CR_MSIRGSEL_POS        3U
-#define STM32_RCC_CR_MSIRGSEL_MSK        (0x1UL << STM32_RCC_CR_MSIRGSEL_POS)
-#define STM32_RCC_CR_MSIRGSEL            STM32_RCC_CR_MSIRGSEL_MSK
+#define STM32_RCC_CR_MSION_POS 0U
+#define STM32_RCC_CR_MSION_MSK (0x1UL << STM32_RCC_CR_MSION_POS)
+#define STM32_RCC_CR_MSION STM32_RCC_CR_MSION_MSK
+#define STM32_RCC_CR_MSIRDY_POS 1U
+#define STM32_RCC_CR_MSIRDY_MSK (0x1UL << STM32_RCC_CR_MSIRDY_POS)
+#define STM32_RCC_CR_MSIRDY STM32_RCC_CR_MSIRDY_MSK
+#define STM32_RCC_CR_MSIPLLEN_POS 2U
+#define STM32_RCC_CR_MSIPLLEN_MSK (0x1UL << STM32_RCC_CR_MSIPLLEN_POS)
+#define STM32_RCC_CR_MSIPLLEN STM32_RCC_CR_MSIPLLEN_MSK
+#define STM32_RCC_CR_MSIRGSEL_POS 3U
+#define STM32_RCC_CR_MSIRGSEL_MSK (0x1UL << STM32_RCC_CR_MSIRGSEL_POS)
+#define STM32_RCC_CR_MSIRGSEL STM32_RCC_CR_MSIRGSEL_MSK
 
 /*!< MSIRANGE CONFIGURATION : 12 FREQUENCY RANGES AVAILABLE */
-#define STM32_RCC_CR_MSIRANGE_POS        4U
-#define STM32_RCC_CR_MSIRANGE_MSK        (0xFUL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE            STM32_RCC_CR_MSIRANGE_MSK
-#define STM32_RCC_CR_MSIRANGE_0          (0x0UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_1          (0x1UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_2          (0x2UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_3          (0x3UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_4          (0x4UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_5          (0x5UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_6          (0x6UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_7          (0x7UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_8          (0x8UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_9          (0x9UL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_10         (0xAUL << STM32_RCC_CR_MSIRANGE_POS)
-#define STM32_RCC_CR_MSIRANGE_11         (0xBUL << STM32_RCC_CR_MSIRANGE_POS)
-
-#define STM32_RCC_CR_HSION_POS           8U
-#define STM32_RCC_CR_HSION_MSK           (0x1UL << STM32_RCC_CR_HSION_POS)
-#define STM32_RCC_CR_HSION               STM32_RCC_CR_HSION_MSK
-#define STM32_RCC_CR_HSIKERON_POS        9U
-#define STM32_RCC_CR_HSIKERON_MSK        (0x1UL << STM32_RCC_CR_HSIKERON_POS)
-#define STM32_RCC_CR_HSIKERON            STM32_RCC_CR_HSIKERON_MSK
-#define STM32_RCC_CR_HSIRDY_POS          10U
-#define STM32_RCC_CR_HSIRDY_MSK          (0x1UL << STM32_RCC_CR_HSIRDY_POS)
-#define STM32_RCC_CR_HSIRDY              STM32_RCC_CR_HSIRDY_MSK
-#define STM32_RCC_CR_HSIASFS_POS         11U
-#define STM32_RCC_CR_HSIASFS_MSK         (0x1UL << STM32_RCC_CR_HSIASFS_POS)
-#define STM32_RCC_CR_HSIASFS             STM32_RCC_CR_HSIASFS_MSK
-
-#define STM32_RCC_CR_HSEON_POS           16U
-#define STM32_RCC_CR_HSEON_MSK           (0x1UL << STM32_RCC_CR_HSEON_POS)
-#define STM32_RCC_CR_HSEON               STM32_RCC_CR_HSEON_MSK
-#define STM32_RCC_CR_HSERDY_POS          17U
-#define STM32_RCC_CR_HSERDY_MSK          (0x1UL << STM32_RCC_CR_HSERDY_POS)
-#define STM32_RCC_CR_HSERDY              STM32_RCC_CR_HSERDY_MSK
-#define STM32_RCC_CR_HSEBYP_POS          18U
-#define STM32_RCC_CR_HSEBYP_MSK          (0x1UL << STM32_RCC_CR_HSEBYP_POS)
-#define STM32_RCC_CR_HSEBYP              STM32_RCC_CR_HSEBYP_MSK
-#define STM32_RCC_CR_CSSON_POS           19U
-#define STM32_RCC_CR_CSSON_MSK           (0x1UL << STM32_RCC_CR_CSSON_POS)
-#define STM32_RCC_CR_CSSON               STM32_RCC_CR_CSSON_MSK
-
-#define STM32_RCC_CR_PLLON_POS           24U
-#define STM32_RCC_CR_PLLON_MSK           (0x1UL << STM32_RCC_CR_PLLON_POS)
-#define STM32_RCC_CR_PLLON               STM32_RCC_CR_PLLON_MSK
-#define STM32_RCC_CR_PLLRDY_POS          25U
-#define STM32_RCC_CR_PLLRDY_MSK          (0x1UL << STM32_RCC_CR_PLLRDY_POS)
-#define STM32_RCC_CR_PLLRDY              STM32_RCC_CR_PLLRDY_MSK
-#define STM32_RCC_CR_PLLSAI1ON_POS       26U
-#define STM32_RCC_CR_PLLSAI1ON_MSK       (0x1UL << STM32_RCC_CR_PLLSAI1ON_POS)
-#define STM32_RCC_CR_PLLSAI1ON           STM32_RCC_CR_PLLSAI1ON_MSK
-#define STM32_RCC_CR_PLLSAI1RDY_POS      27U
-#define STM32_RCC_CR_PLLSAI1RDY_MSK      (0x1UL << STM32_RCC_CR_PLLSAI1RDY_POS)
-#define STM32_RCC_CR_PLLSAI1RDY          STM32_RCC_CR_PLLSAI1RDY_MSK
+#define STM32_RCC_CR_MSIRANGE_POS 4U
+#define STM32_RCC_CR_MSIRANGE_MSK (0xFUL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE STM32_RCC_CR_MSIRANGE_MSK
+#define STM32_RCC_CR_MSIRANGE_0 (0x0UL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_1 (0x1UL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_2 (0x2UL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_3 (0x3UL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_4 (0x4UL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_5 (0x5UL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_6 (0x6UL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_7 (0x7UL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_8 (0x8UL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_9 (0x9UL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_10 (0xAUL << STM32_RCC_CR_MSIRANGE_POS)
+#define STM32_RCC_CR_MSIRANGE_11 (0xBUL << STM32_RCC_CR_MSIRANGE_POS)
+
+#define STM32_RCC_CR_HSION_POS 8U
+#define STM32_RCC_CR_HSION_MSK (0x1UL << STM32_RCC_CR_HSION_POS)
+#define STM32_RCC_CR_HSION STM32_RCC_CR_HSION_MSK
+#define STM32_RCC_CR_HSIKERON_POS 9U
+#define STM32_RCC_CR_HSIKERON_MSK (0x1UL << STM32_RCC_CR_HSIKERON_POS)
+#define STM32_RCC_CR_HSIKERON STM32_RCC_CR_HSIKERON_MSK
+#define STM32_RCC_CR_HSIRDY_POS 10U
+#define STM32_RCC_CR_HSIRDY_MSK (0x1UL << STM32_RCC_CR_HSIRDY_POS)
+#define STM32_RCC_CR_HSIRDY STM32_RCC_CR_HSIRDY_MSK
+#define STM32_RCC_CR_HSIASFS_POS 11U
+#define STM32_RCC_CR_HSIASFS_MSK (0x1UL << STM32_RCC_CR_HSIASFS_POS)
+#define STM32_RCC_CR_HSIASFS STM32_RCC_CR_HSIASFS_MSK
+
+#define STM32_RCC_CR_HSEON_POS 16U
+#define STM32_RCC_CR_HSEON_MSK (0x1UL << STM32_RCC_CR_HSEON_POS)
+#define STM32_RCC_CR_HSEON STM32_RCC_CR_HSEON_MSK
+#define STM32_RCC_CR_HSERDY_POS 17U
+#define STM32_RCC_CR_HSERDY_MSK (0x1UL << STM32_RCC_CR_HSERDY_POS)
+#define STM32_RCC_CR_HSERDY STM32_RCC_CR_HSERDY_MSK
+#define STM32_RCC_CR_HSEBYP_POS 18U
+#define STM32_RCC_CR_HSEBYP_MSK (0x1UL << STM32_RCC_CR_HSEBYP_POS)
+#define STM32_RCC_CR_HSEBYP STM32_RCC_CR_HSEBYP_MSK
+#define STM32_RCC_CR_CSSON_POS 19U
+#define STM32_RCC_CR_CSSON_MSK (0x1UL << STM32_RCC_CR_CSSON_POS)
+#define STM32_RCC_CR_CSSON STM32_RCC_CR_CSSON_MSK
+
+#define STM32_RCC_CR_PLLON_POS 24U
+#define STM32_RCC_CR_PLLON_MSK (0x1UL << STM32_RCC_CR_PLLON_POS)
+#define STM32_RCC_CR_PLLON STM32_RCC_CR_PLLON_MSK
+#define STM32_RCC_CR_PLLRDY_POS 25U
+#define STM32_RCC_CR_PLLRDY_MSK (0x1UL << STM32_RCC_CR_PLLRDY_POS)
+#define STM32_RCC_CR_PLLRDY STM32_RCC_CR_PLLRDY_MSK
+#define STM32_RCC_CR_PLLSAI1ON_POS 26U
+#define STM32_RCC_CR_PLLSAI1ON_MSK (0x1UL << STM32_RCC_CR_PLLSAI1ON_POS)
+#define STM32_RCC_CR_PLLSAI1ON STM32_RCC_CR_PLLSAI1ON_MSK
+#define STM32_RCC_CR_PLLSAI1RDY_POS 27U
+#define STM32_RCC_CR_PLLSAI1RDY_MSK (0x1UL << STM32_RCC_CR_PLLSAI1RDY_POS)
+#define STM32_RCC_CR_PLLSAI1RDY STM32_RCC_CR_PLLSAI1RDY_MSK
 
 /********************  BIT DEFINITION FOR STM32_RCC_ICSCR REGISTER  ***********/
 /*!< MSICAL CONFIGURATION */
-#define STM32_RCC_ICSCR_MSICAL_POS       0U
-#define STM32_RCC_ICSCR_MSICAL_MSK       (0xFFUL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL           STM32_RCC_ICSCR_MSICAL_MSK
-#define STM32_RCC_ICSCR_MSICAL_0         (0x01UL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL_1         (0x02UL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL_2         (0x04UL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL_3         (0x08UL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL_4         (0x10UL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL_5         (0x20UL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL_6         (0x40UL << STM32_RCC_ICSCR_MSICAL_POS)
-#define STM32_RCC_ICSCR_MSICAL_7         (0x80UL << STM32_RCC_ICSCR_MSICAL_POS)
+#define STM32_RCC_ICSCR_MSICAL_POS 0U
+#define STM32_RCC_ICSCR_MSICAL_MSK (0xFFUL << STM32_RCC_ICSCR_MSICAL_POS)
+#define STM32_RCC_ICSCR_MSICAL STM32_RCC_ICSCR_MSICAL_MSK
+#define STM32_RCC_ICSCR_MSICAL_0 (0x01UL << STM32_RCC_ICSCR_MSICAL_POS)
+#define STM32_RCC_ICSCR_MSICAL_1 (0x02UL << STM32_RCC_ICSCR_MSICAL_POS)
+#define STM32_RCC_ICSCR_MSICAL_2 (0x04UL << STM32_RCC_ICSCR_MSICAL_POS)
+#define STM32_RCC_ICSCR_MSICAL_3 (0x08UL << STM32_RCC_ICSCR_MSICAL_POS)
+#define STM32_RCC_ICSCR_MSICAL_4 (0x10UL << STM32_RCC_ICSCR_MSICAL_POS)
+#define STM32_RCC_ICSCR_MSICAL_5 (0x20UL << STM32_RCC_ICSCR_MSICAL_POS)
+#define STM32_RCC_ICSCR_MSICAL_6 (0x40UL << STM32_RCC_ICSCR_MSICAL_POS)
+#define STM32_RCC_ICSCR_MSICAL_7 (0x80UL << STM32_RCC_ICSCR_MSICAL_POS)
 
 /*!< MSITRIM CONFIGURATION */
-#define STM32_RCC_ICSCR_MSITRIM_POS      8U
-#define STM32_RCC_ICSCR_MSITRIM_MSK      (0xFFUL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM          STM32_RCC_ICSCR_MSITRIM_MSK
-#define STM32_RCC_ICSCR_MSITRIM_0        (0x01UL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM_1        (0x02UL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM_2        (0x04UL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM_3        (0x08UL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM_4        (0x10UL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM_5        (0x20UL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM_6        (0x40UL << STM32_RCC_ICSCR_MSITRIM_POS)
-#define STM32_RCC_ICSCR_MSITRIM_7        (0x80UL << STM32_RCC_ICSCR_MSITRIM_POS)
+#define STM32_RCC_ICSCR_MSITRIM_POS 8U
+#define STM32_RCC_ICSCR_MSITRIM_MSK (0xFFUL << STM32_RCC_ICSCR_MSITRIM_POS)
+#define STM32_RCC_ICSCR_MSITRIM STM32_RCC_ICSCR_MSITRIM_MSK
+#define STM32_RCC_ICSCR_MSITRIM_0 (0x01UL << STM32_RCC_ICSCR_MSITRIM_POS)
+#define STM32_RCC_ICSCR_MSITRIM_1 (0x02UL << STM32_RCC_ICSCR_MSITRIM_POS)
+#define STM32_RCC_ICSCR_MSITRIM_2 (0x04UL << STM32_RCC_ICSCR_MSITRIM_POS)
+#define STM32_RCC_ICSCR_MSITRIM_3 (0x08UL << STM32_RCC_ICSCR_MSITRIM_POS)
+#define STM32_RCC_ICSCR_MSITRIM_4 (0x10UL << STM32_RCC_ICSCR_MSITRIM_POS)
+#define STM32_RCC_ICSCR_MSITRIM_5 (0x20UL << STM32_RCC_ICSCR_MSITRIM_POS)
+#define STM32_RCC_ICSCR_MSITRIM_6 (0x40UL << STM32_RCC_ICSCR_MSITRIM_POS)
+#define STM32_RCC_ICSCR_MSITRIM_7 (0x80UL << STM32_RCC_ICSCR_MSITRIM_POS)
 
 /*!< HSICAL CONFIGURATION */
-#define STM32_RCC_ICSCR_HSICAL_POS       16U
-#define STM32_RCC_ICSCR_HSICAL_MSK       (0xFFUL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL           STM32_RCC_ICSCR_HSICAL_MSK
-#define STM32_RCC_ICSCR_HSICAL_0         (0x01UL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL_1         (0x02UL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL_2         (0x04UL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL_3         (0x08UL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL_4         (0x10UL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL_5         (0x20UL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL_6         (0x40UL << STM32_RCC_ICSCR_HSICAL_POS)
-#define STM32_RCC_ICSCR_HSICAL_7         (0x80UL << STM32_RCC_ICSCR_HSICAL_POS)
+#define STM32_RCC_ICSCR_HSICAL_POS 16U
+#define STM32_RCC_ICSCR_HSICAL_MSK (0xFFUL << STM32_RCC_ICSCR_HSICAL_POS)
+#define STM32_RCC_ICSCR_HSICAL STM32_RCC_ICSCR_HSICAL_MSK
+#define STM32_RCC_ICSCR_HSICAL_0 (0x01UL << STM32_RCC_ICSCR_HSICAL_POS)
+#define STM32_RCC_ICSCR_HSICAL_1 (0x02UL << STM32_RCC_ICSCR_HSICAL_POS)
+#define STM32_RCC_ICSCR_HSICAL_2 (0x04UL << STM32_RCC_ICSCR_HSICAL_POS)
+#define STM32_RCC_ICSCR_HSICAL_3 (0x08UL << STM32_RCC_ICSCR_HSICAL_POS)
+#define STM32_RCC_ICSCR_HSICAL_4 (0x10UL << STM32_RCC_ICSCR_HSICAL_POS)
+#define STM32_RCC_ICSCR_HSICAL_5 (0x20UL << STM32_RCC_ICSCR_HSICAL_POS)
+#define STM32_RCC_ICSCR_HSICAL_6 (0x40UL << STM32_RCC_ICSCR_HSICAL_POS)
+#define STM32_RCC_ICSCR_HSICAL_7 (0x80UL << STM32_RCC_ICSCR_HSICAL_POS)
 
 /*!< HSITRIM CONFIGURATION */
-#define STM32_RCC_ICSCR_HSITRIM_POS      24U
-#define STM32_RCC_ICSCR_HSITRIM_MSK      (0x1FUL << STM32_RCC_ICSCR_HSITRIM_POS)
-#define STM32_RCC_ICSCR_HSITRIM          STM32_RCC_ICSCR_HSITRIM_MSK
-#define STM32_RCC_ICSCR_HSITRIM_0        (0x01UL << STM32_RCC_ICSCR_HSITRIM_POS)
-#define STM32_RCC_ICSCR_HSITRIM_1        (0x02UL << STM32_RCC_ICSCR_HSITRIM_POS)
-#define STM32_RCC_ICSCR_HSITRIM_2        (0x04UL << STM32_RCC_ICSCR_HSITRIM_POS)
-#define STM32_RCC_ICSCR_HSITRIM_3        (0x08UL << STM32_RCC_ICSCR_HSITRIM_POS)
-#define STM32_RCC_ICSCR_HSITRIM_4        (0x10UL << STM32_RCC_ICSCR_HSITRIM_POS)
+#define STM32_RCC_ICSCR_HSITRIM_POS 24U
+#define STM32_RCC_ICSCR_HSITRIM_MSK (0x1FUL << STM32_RCC_ICSCR_HSITRIM_POS)
+#define STM32_RCC_ICSCR_HSITRIM STM32_RCC_ICSCR_HSITRIM_MSK
+#define STM32_RCC_ICSCR_HSITRIM_0 (0x01UL << STM32_RCC_ICSCR_HSITRIM_POS)
+#define STM32_RCC_ICSCR_HSITRIM_1 (0x02UL << STM32_RCC_ICSCR_HSITRIM_POS)
+#define STM32_RCC_ICSCR_HSITRIM_2 (0x04UL << STM32_RCC_ICSCR_HSITRIM_POS)
+#define STM32_RCC_ICSCR_HSITRIM_3 (0x08UL << STM32_RCC_ICSCR_HSITRIM_POS)
+#define STM32_RCC_ICSCR_HSITRIM_4 (0x10UL << STM32_RCC_ICSCR_HSITRIM_POS)
 
 /****************  BIT DEFINITION FOR STM32_RCC_CFGR REGISTER  **************/
 /*!< SW CONFIGURATION */
-#define STM32_RCC_CFGR_SW_POS            0U
-#define STM32_RCC_CFGR_SW_MSK            (0x3UL << STM32_RCC_CFGR_SW_POS)
-#define STM32_RCC_CFGR_SW                STM32_RCC_CFGR_SW_MSK
-#define STM32_RCC_CFGR_SW_0              (0x1UL << STM32_RCC_CFGR_SW_POS)
-#define STM32_RCC_CFGR_SW_1              (0x2UL << STM32_RCC_CFGR_SW_POS)
+#define STM32_RCC_CFGR_SW_POS 0U
+#define STM32_RCC_CFGR_SW_MSK (0x3UL << STM32_RCC_CFGR_SW_POS)
+#define STM32_RCC_CFGR_SW STM32_RCC_CFGR_SW_MSK
+#define STM32_RCC_CFGR_SW_0 (0x1UL << STM32_RCC_CFGR_SW_POS)
+#define STM32_RCC_CFGR_SW_1 (0x2UL << STM32_RCC_CFGR_SW_POS)
 
-#define STM32_RCC_CFGR_SW_MSI            (0x00000000UL)
-#define STM32_RCC_CFGR_SW_HSI            (0x00000001UL)
-#define STM32_RCC_CFGR_SW_HSE            (0x00000002UL)
-#define STM32_RCC_CFGR_SW_PLL            (0x00000003UL)
+#define STM32_RCC_CFGR_SW_MSI (0x00000000UL)
+#define STM32_RCC_CFGR_SW_HSI (0x00000001UL)
+#define STM32_RCC_CFGR_SW_HSE (0x00000002UL)
+#define STM32_RCC_CFGR_SW_PLL (0x00000003UL)
 
 /*!< SWS CONFIGURATION */
-#define STM32_RCC_CFGR_SWS_POS           2U
-#define STM32_RCC_CFGR_SWS_MSK           (0x3UL << STM32_RCC_CFGR_SWS_POS)
-#define STM32_RCC_CFGR_SWS               STM32_RCC_CFGR_SWS_MSK
-#define STM32_RCC_CFGR_SWS_0             (0x1UL << STM32_RCC_CFGR_SWS_POS)
-#define STM32_RCC_CFGR_SWS_1             (0x2UL << STM32_RCC_CFGR_SWS_POS)
+#define STM32_RCC_CFGR_SWS_POS 2U
+#define STM32_RCC_CFGR_SWS_MSK (0x3UL << STM32_RCC_CFGR_SWS_POS)
+#define STM32_RCC_CFGR_SWS STM32_RCC_CFGR_SWS_MSK
+#define STM32_RCC_CFGR_SWS_0 (0x1UL << STM32_RCC_CFGR_SWS_POS)
+#define STM32_RCC_CFGR_SWS_1 (0x2UL << STM32_RCC_CFGR_SWS_POS)
 
-#define STM32_RCC_CFGR_SWS_MSI           (0x00000000UL)
-#define STM32_RCC_CFGR_SWS_HSI           (0x00000004UL)
-#define STM32_RCC_CFGR_SWS_HSE           (0x00000008UL)
-#define STM32_RCC_CFGR_SWS_PLL           (0x0000000CUL)
+#define STM32_RCC_CFGR_SWS_MSI (0x00000000UL)
+#define STM32_RCC_CFGR_SWS_HSI (0x00000004UL)
+#define STM32_RCC_CFGR_SWS_HSE (0x00000008UL)
+#define STM32_RCC_CFGR_SWS_PLL (0x0000000CUL)
 
 /*!< HPRE CONFIGURATION */
-#define STM32_RCC_CFGR_HPRE_POS          4U
-#define STM32_RCC_CFGR_HPRE_MSK          (0xFUL << STM32_RCC_CFGR_HPRE_POS)
-#define STM32_RCC_CFGR_HPRE              STM32_RCC_CFGR_HPRE_MSK
-#define STM32_RCC_CFGR_HPRE_0            (0x1UL << STM32_RCC_CFGR_HPRE_POS)
-#define STM32_RCC_CFGR_HPRE_1            (0x2UL << STM32_RCC_CFGR_HPRE_POS)
-#define STM32_RCC_CFGR_HPRE_2            (0x4UL << STM32_RCC_CFGR_HPRE_POS)
-#define STM32_RCC_CFGR_HPRE_3            (0x8UL << STM32_RCC_CFGR_HPRE_POS)
-
-#define STM32_RCC_CFGR_HPRE_DIV1         (0x00000000UL)
-#define STM32_RCC_CFGR_HPRE_DIV2         (0x00000080UL)
-#define STM32_RCC_CFGR_HPRE_DIV4         (0x00000090UL)
-#define STM32_RCC_CFGR_HPRE_DIV8         (0x000000A0UL)
-#define STM32_RCC_CFGR_HPRE_DIV16        (0x000000B0UL)
-#define STM32_RCC_CFGR_HPRE_DIV64        (0x000000C0UL)
-#define STM32_RCC_CFGR_HPRE_DIV128       (0x000000D0UL)
-#define STM32_RCC_CFGR_HPRE_DIV256       (0x000000E0UL)
-#define STM32_RCC_CFGR_HPRE_DIV512       (0x000000F0UL)
+#define STM32_RCC_CFGR_HPRE_POS 4U
+#define STM32_RCC_CFGR_HPRE_MSK (0xFUL << STM32_RCC_CFGR_HPRE_POS)
+#define STM32_RCC_CFGR_HPRE STM32_RCC_CFGR_HPRE_MSK
+#define STM32_RCC_CFGR_HPRE_0 (0x1UL << STM32_RCC_CFGR_HPRE_POS)
+#define STM32_RCC_CFGR_HPRE_1 (0x2UL << STM32_RCC_CFGR_HPRE_POS)
+#define STM32_RCC_CFGR_HPRE_2 (0x4UL << STM32_RCC_CFGR_HPRE_POS)
+#define STM32_RCC_CFGR_HPRE_3 (0x8UL << STM32_RCC_CFGR_HPRE_POS)
+
+#define STM32_RCC_CFGR_HPRE_DIV1 (0x00000000UL)
+#define STM32_RCC_CFGR_HPRE_DIV2 (0x00000080UL)
+#define STM32_RCC_CFGR_HPRE_DIV4 (0x00000090UL)
+#define STM32_RCC_CFGR_HPRE_DIV8 (0x000000A0UL)
+#define STM32_RCC_CFGR_HPRE_DIV16 (0x000000B0UL)
+#define STM32_RCC_CFGR_HPRE_DIV64 (0x000000C0UL)
+#define STM32_RCC_CFGR_HPRE_DIV128 (0x000000D0UL)
+#define STM32_RCC_CFGR_HPRE_DIV256 (0x000000E0UL)
+#define STM32_RCC_CFGR_HPRE_DIV512 (0x000000F0UL)
 
 /*!< PPRE1 CONFIGURATION */
-#define STM32_RCC_CFGR_PPRE1_POS         8U
-#define STM32_RCC_CFGR_PPRE1_MSK         (0x7UL << STM32_RCC_CFGR_PPRE1_POS)
-#define STM32_RCC_CFGR_PPRE1             STM32_RCC_CFGR_PPRE1_MSK
-#define STM32_RCC_CFGR_PPRE1_0           (0x1UL << STM32_RCC_CFGR_PPRE1_POS)
-#define STM32_RCC_CFGR_PPRE1_1           (0x2UL << STM32_RCC_CFGR_PPRE1_POS)
-#define STM32_RCC_CFGR_PPRE1_2           (0x4UL << STM32_RCC_CFGR_PPRE1_POS)
-
-#define STM32_RCC_CFGR_PPRE1_DIV1        (0x00000000UL)
-#define STM32_RCC_CFGR_PPRE1_DIV2        (0x00000400UL)
-#define STM32_RCC_CFGR_PPRE1_DIV4        (0x00000500UL)
-#define STM32_RCC_CFGR_PPRE1_DIV8        (0x00000600UL)
-#define STM32_RCC_CFGR_PPRE1_DIV16       (0x00000700UL)
+#define STM32_RCC_CFGR_PPRE1_POS 8U
+#define STM32_RCC_CFGR_PPRE1_MSK (0x7UL << STM32_RCC_CFGR_PPRE1_POS)
+#define STM32_RCC_CFGR_PPRE1 STM32_RCC_CFGR_PPRE1_MSK
+#define STM32_RCC_CFGR_PPRE1_0 (0x1UL << STM32_RCC_CFGR_PPRE1_POS)
+#define STM32_RCC_CFGR_PPRE1_1 (0x2UL << STM32_RCC_CFGR_PPRE1_POS)
+#define STM32_RCC_CFGR_PPRE1_2 (0x4UL << STM32_RCC_CFGR_PPRE1_POS)
+
+#define STM32_RCC_CFGR_PPRE1_DIV1 (0x00000000UL)
+#define STM32_RCC_CFGR_PPRE1_DIV2 (0x00000400UL)
+#define STM32_RCC_CFGR_PPRE1_DIV4 (0x00000500UL)
+#define STM32_RCC_CFGR_PPRE1_DIV8 (0x00000600UL)
+#define STM32_RCC_CFGR_PPRE1_DIV16 (0x00000700UL)
 
 /*!< PPRE2 CONFIGURATION */
-#define STM32_RCC_CFGR_PPRE2_POS         11U
-#define STM32_RCC_CFGR_PPRE2_MSK         (0x7UL << STM32_RCC_CFGR_PPRE2_POS)
-#define STM32_RCC_CFGR_PPRE2             STM32_RCC_CFGR_PPRE2_MSK
-#define STM32_RCC_CFGR_PPRE2_0           (0x1UL << STM32_RCC_CFGR_PPRE2_POS)
-#define STM32_RCC_CFGR_PPRE2_1           (0x2UL << STM32_RCC_CFGR_PPRE2_POS)
-#define STM32_RCC_CFGR_PPRE2_2           (0x4UL << STM32_RCC_CFGR_PPRE2_POS)
-
-#define STM32_RCC_CFGR_PPRE2_DIV1        (0x00000000UL)
-#define STM32_RCC_CFGR_PPRE2_DIV2        (0x00002000UL)
-#define STM32_RCC_CFGR_PPRE2_DIV4        (0x00002800UL)
-#define STM32_RCC_CFGR_PPRE2_DIV8        (0x00003000UL)
-#define STM32_RCC_CFGR_PPRE2_DIV16       (0x00003800UL)
-
-#define STM32_RCC_CFGR_STOPWUCK_POS      15U
-#define STM32_RCC_CFGR_STOPWUCK_MSK      (0x1UL << STM32_RCC_CFGR_STOPWUCK_POS)
-#define STM32_RCC_CFGR_STOPWUCK          STM32_RCC_CFGR_STOPWUCK_MSK
+#define STM32_RCC_CFGR_PPRE2_POS 11U
+#define STM32_RCC_CFGR_PPRE2_MSK (0x7UL << STM32_RCC_CFGR_PPRE2_POS)
+#define STM32_RCC_CFGR_PPRE2 STM32_RCC_CFGR_PPRE2_MSK
+#define STM32_RCC_CFGR_PPRE2_0 (0x1UL << STM32_RCC_CFGR_PPRE2_POS)
+#define STM32_RCC_CFGR_PPRE2_1 (0x2UL << STM32_RCC_CFGR_PPRE2_POS)
+#define STM32_RCC_CFGR_PPRE2_2 (0x4UL << STM32_RCC_CFGR_PPRE2_POS)
+
+#define STM32_RCC_CFGR_PPRE2_DIV1 (0x00000000UL)
+#define STM32_RCC_CFGR_PPRE2_DIV2 (0x00002000UL)
+#define STM32_RCC_CFGR_PPRE2_DIV4 (0x00002800UL)
+#define STM32_RCC_CFGR_PPRE2_DIV8 (0x00003000UL)
+#define STM32_RCC_CFGR_PPRE2_DIV16 (0x00003800UL)
+
+#define STM32_RCC_CFGR_STOPWUCK_POS 15U
+#define STM32_RCC_CFGR_STOPWUCK_MSK (0x1UL << STM32_RCC_CFGR_STOPWUCK_POS)
+#define STM32_RCC_CFGR_STOPWUCK STM32_RCC_CFGR_STOPWUCK_MSK
 
 /*!< MCOSEL CONFIGURATION */
-#define STM32_RCC_CFGR_MCOSEL_POS        24U
-#define STM32_RCC_CFGR_MCOSEL_MSK        (0xFUL << STM32_RCC_CFGR_MCOSEL_POS)
-#define STM32_RCC_CFGR_MCOSEL            STM32_RCC_CFGR_MCOSEL_MSK
-#define STM32_RCC_CFGR_MCOSEL_0          (0x1UL << STM32_RCC_CFGR_MCOSEL_POS)
-#define STM32_RCC_CFGR_MCOSEL_1          (0x2UL << STM32_RCC_CFGR_MCOSEL_POS)
-#define STM32_RCC_CFGR_MCOSEL_2          (0x4UL << STM32_RCC_CFGR_MCOSEL_POS)
-#define STM32_RCC_CFGR_MCOSEL_3          (0x8UL << STM32_RCC_CFGR_MCOSEL_POS)
-
-#define STM32_RCC_CFGR_MCOPRE_POS        28U
-#define STM32_RCC_CFGR_MCOPRE_MSK        (0x7UL << STM32_RCC_CFGR_MCOPRE_POS)
-#define STM32_RCC_CFGR_MCOPRE            STM32_RCC_CFGR_MCOPRE_MSK
-#define STM32_RCC_CFGR_MCOPRE_0          (0x1UL << STM32_RCC_CFGR_MCOPRE_POS)
-#define STM32_RCC_CFGR_MCOPRE_1          (0x2UL << STM32_RCC_CFGR_MCOPRE_POS)
-#define STM32_RCC_CFGR_MCOPRE_2          (0x4UL << STM32_RCC_CFGR_MCOPRE_POS)
-
-#define STM32_RCC_CFGR_MCOPRE_DIV1       (0x00000000UL)
-#define STM32_RCC_CFGR_MCOPRE_DIV2       (0x10000000UL)
-#define STM32_RCC_CFGR_MCOPRE_DIV4       (0x20000000UL)
-#define STM32_RCC_CFGR_MCOPRE_DIV8       (0x30000000UL)
-#define STM32_RCC_CFGR_MCOPRE_DIV16      (0x40000000UL)
+#define STM32_RCC_CFGR_MCOSEL_POS 24U
+#define STM32_RCC_CFGR_MCOSEL_MSK (0xFUL << STM32_RCC_CFGR_MCOSEL_POS)
+#define STM32_RCC_CFGR_MCOSEL STM32_RCC_CFGR_MCOSEL_MSK
+#define STM32_RCC_CFGR_MCOSEL_0 (0x1UL << STM32_RCC_CFGR_MCOSEL_POS)
+#define STM32_RCC_CFGR_MCOSEL_1 (0x2UL << STM32_RCC_CFGR_MCOSEL_POS)
+#define STM32_RCC_CFGR_MCOSEL_2 (0x4UL << STM32_RCC_CFGR_MCOSEL_POS)
+#define STM32_RCC_CFGR_MCOSEL_3 (0x8UL << STM32_RCC_CFGR_MCOSEL_POS)
+
+#define STM32_RCC_CFGR_MCOPRE_POS 28U
+#define STM32_RCC_CFGR_MCOPRE_MSK (0x7UL << STM32_RCC_CFGR_MCOPRE_POS)
+#define STM32_RCC_CFGR_MCOPRE STM32_RCC_CFGR_MCOPRE_MSK
+#define STM32_RCC_CFGR_MCOPRE_0 (0x1UL << STM32_RCC_CFGR_MCOPRE_POS)
+#define STM32_RCC_CFGR_MCOPRE_1 (0x2UL << STM32_RCC_CFGR_MCOPRE_POS)
+#define STM32_RCC_CFGR_MCOPRE_2 (0x4UL << STM32_RCC_CFGR_MCOPRE_POS)
+
+#define STM32_RCC_CFGR_MCOPRE_DIV1 (0x00000000UL)
+#define STM32_RCC_CFGR_MCOPRE_DIV2 (0x10000000UL)
+#define STM32_RCC_CFGR_MCOPRE_DIV4 (0x20000000UL)
+#define STM32_RCC_CFGR_MCOPRE_DIV8 (0x30000000UL)
+#define STM32_RCC_CFGR_MCOPRE_DIV16 (0x40000000UL)
 
 /* LEGACY ALIASES */
-#define STM32_RCC_CFGR_MCO_PRE           STM32_RCC_CFGR_MCOPRE
-#define STM32_RCC_CFGR_MCO_PRE_1         STM32_RCC_CFGR_MCOPRE_DIV1
-#define STM32_RCC_CFGR_MCO_PRE_2         STM32_RCC_CFGR_MCOPRE_DIV2
-#define STM32_RCC_CFGR_MCO_PRE_4         STM32_RCC_CFGR_MCOPRE_DIV4
-#define STM32_RCC_CFGR_MCO_PRE_8         STM32_RCC_CFGR_MCOPRE_DIV8
-#define STM32_RCC_CFGR_MCO_PRE_16        STM32_RCC_CFGR_MCOPRE_DIV16
+#define STM32_RCC_CFGR_MCO_PRE STM32_RCC_CFGR_MCOPRE
+#define STM32_RCC_CFGR_MCO_PRE_1 STM32_RCC_CFGR_MCOPRE_DIV1
+#define STM32_RCC_CFGR_MCO_PRE_2 STM32_RCC_CFGR_MCOPRE_DIV2
+#define STM32_RCC_CFGR_MCO_PRE_4 STM32_RCC_CFGR_MCOPRE_DIV4
+#define STM32_RCC_CFGR_MCO_PRE_8 STM32_RCC_CFGR_MCOPRE_DIV8
+#define STM32_RCC_CFGR_MCO_PRE_16 STM32_RCC_CFGR_MCOPRE_DIV16
 
 /****************  BIT DEFINITION FOR STM32_RCC_PLLCFGR REGISTER  ***********/
-#define STM32_RCC_PLLCFGR_PLLSRC_POS     0U
+#define STM32_RCC_PLLCFGR_PLLSRC_POS 0U
 #define STM32_RCC_PLLCFGR_PLLSRC_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLSRC_POS)
 #define STM32_RCC_PLLCFGR_PLLSRC STM32_RCC_PLLCFGR_PLLSRC_MSK
 
@@ -771,59 +768,59 @@
 #define STM32_RCC_PLLCFGR_PLLSRC_HSE_POS 0U
 #define STM32_RCC_PLLCFGR_PLLSRC_HSE_MSK \
 	(0x3UL << STM32_RCC_PLLCFGR_PLLSRC_HSE_POS)
-#define STM32_RCC_PLLCFGR_PLLSRC_HSE     STM32_RCC_PLLCFGR_PLLSRC_HSE_MSK
-
-#define STM32_RCC_PLLCFGR_PLLM_POS       4U
-#define STM32_RCC_PLLCFGR_PLLM_MSK       (0x7UL << STM32_RCC_PLLCFGR_PLLM_POS)
-#define STM32_RCC_PLLCFGR_PLLM           STM32_RCC_PLLCFGR_PLLM_MSK
-#define STM32_RCC_PLLCFGR_PLLM_0         (0x1UL << STM32_RCC_PLLCFGR_PLLM_POS)
-#define STM32_RCC_PLLCFGR_PLLM_1         (0x2UL << STM32_RCC_PLLCFGR_PLLM_POS)
-#define STM32_RCC_PLLCFGR_PLLM_2         (0x4UL << STM32_RCC_PLLCFGR_PLLM_POS)
-
-#define STM32_RCC_PLLCFGR_PLLN_POS       8U
-#define STM32_RCC_PLLCFGR_PLLN_MSK       (0x7FUL << STM32_RCC_PLLCFGR_PLLN_POS)
-#define STM32_RCC_PLLCFGR_PLLN           STM32_RCC_PLLCFGR_PLLN_MSK
-#define STM32_RCC_PLLCFGR_PLLN_0         (0x01UL << STM32_RCC_PLLCFGR_PLLN_POS)
-#define STM32_RCC_PLLCFGR_PLLN_1         (0x02UL << STM32_RCC_PLLCFGR_PLLN_POS)
-#define STM32_RCC_PLLCFGR_PLLN_2         (0x04UL << STM32_RCC_PLLCFGR_PLLN_POS)
-#define STM32_RCC_PLLCFGR_PLLN_3         (0x08UL << STM32_RCC_PLLCFGR_PLLN_POS)
-#define STM32_RCC_PLLCFGR_PLLN_4         (0x10UL << STM32_RCC_PLLCFGR_PLLN_POS)
-#define STM32_RCC_PLLCFGR_PLLN_5         (0x20UL << STM32_RCC_PLLCFGR_PLLN_POS)
-#define STM32_RCC_PLLCFGR_PLLN_6         (0x40UL << STM32_RCC_PLLCFGR_PLLN_POS)
-
-#define STM32_RCC_PLLCFGR_PLLPEN_POS     16U
-#define STM32_RCC_PLLCFGR_PLLPEN_MSK     (0x1UL << STM32_RCC_PLLCFGR_PLLPEN_POS)
-#define STM32_RCC_PLLCFGR_PLLPEN         STM32_RCC_PLLCFGR_PLLPEN_MSK
-#define STM32_RCC_PLLCFGR_PLLP_POS       17U
-#define STM32_RCC_PLLCFGR_PLLP_MSK       (0x1UL << STM32_RCC_PLLCFGR_PLLP_POS)
-#define STM32_RCC_PLLCFGR_PLLP           STM32_RCC_PLLCFGR_PLLP_MSK
-#define STM32_RCC_PLLCFGR_PLLQEN_POS     20U
-#define STM32_RCC_PLLCFGR_PLLQEN_MSK     (0x1UL << STM32_RCC_PLLCFGR_PLLQEN_POS)
-#define STM32_RCC_PLLCFGR_PLLQEN         STM32_RCC_PLLCFGR_PLLQEN_MSK
-
-#define STM32_RCC_PLLCFGR_PLLQ_POS       21U
-#define STM32_RCC_PLLCFGR_PLLQ_MSK       (0x3UL << STM32_RCC_PLLCFGR_PLLQ_POS)
-#define STM32_RCC_PLLCFGR_PLLQ           STM32_RCC_PLLCFGR_PLLQ_MSK
-#define STM32_RCC_PLLCFGR_PLLQ_0         (0x1UL << STM32_RCC_PLLCFGR_PLLQ_POS)
-#define STM32_RCC_PLLCFGR_PLLQ_1         (0x2UL << STM32_RCC_PLLCFGR_PLLQ_POS)
-
-#define STM32_RCC_PLLCFGR_PLLREN_POS     24U
-#define STM32_RCC_PLLCFGR_PLLREN_MSK     (0x1UL << STM32_RCC_PLLCFGR_PLLREN_POS)
-#define STM32_RCC_PLLCFGR_PLLREN         STM32_RCC_PLLCFGR_PLLREN_MSK
-#define STM32_RCC_PLLCFGR_PLLR_POS       25U
-#define STM32_RCC_PLLCFGR_PLLR_MSK       (0x3UL << STM32_RCC_PLLCFGR_PLLR_POS)
-#define STM32_RCC_PLLCFGR_PLLR           STM32_RCC_PLLCFGR_PLLR_MSK
-#define STM32_RCC_PLLCFGR_PLLR_0         (0x1UL << STM32_RCC_PLLCFGR_PLLR_POS)
-#define STM32_RCC_PLLCFGR_PLLR_1         (0x2UL << STM32_RCC_PLLCFGR_PLLR_POS)
-
-#define STM32_RCC_PLLCFGR_PLLPDIV_POS  27U
-#define STM32_RCC_PLLCFGR_PLLPDIV_MSK  (0x1FUL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
-#define STM32_RCC_PLLCFGR_PLLPDIV      STM32_RCC_PLLCFGR_PLLPDIV_MSK
-#define STM32_RCC_PLLCFGR_PLLPDIV_0    (0x01UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
-#define STM32_RCC_PLLCFGR_PLLPDIV_1    (0x02UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
-#define STM32_RCC_PLLCFGR_PLLPDIV_2    (0x04UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
-#define STM32_RCC_PLLCFGR_PLLPDIV_3    (0x08UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
-#define STM32_RCC_PLLCFGR_PLLPDIV_4    (0x10UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
+#define STM32_RCC_PLLCFGR_PLLSRC_HSE STM32_RCC_PLLCFGR_PLLSRC_HSE_MSK
+
+#define STM32_RCC_PLLCFGR_PLLM_POS 4U
+#define STM32_RCC_PLLCFGR_PLLM_MSK (0x7UL << STM32_RCC_PLLCFGR_PLLM_POS)
+#define STM32_RCC_PLLCFGR_PLLM STM32_RCC_PLLCFGR_PLLM_MSK
+#define STM32_RCC_PLLCFGR_PLLM_0 (0x1UL << STM32_RCC_PLLCFGR_PLLM_POS)
+#define STM32_RCC_PLLCFGR_PLLM_1 (0x2UL << STM32_RCC_PLLCFGR_PLLM_POS)
+#define STM32_RCC_PLLCFGR_PLLM_2 (0x4UL << STM32_RCC_PLLCFGR_PLLM_POS)
+
+#define STM32_RCC_PLLCFGR_PLLN_POS 8U
+#define STM32_RCC_PLLCFGR_PLLN_MSK (0x7FUL << STM32_RCC_PLLCFGR_PLLN_POS)
+#define STM32_RCC_PLLCFGR_PLLN STM32_RCC_PLLCFGR_PLLN_MSK
+#define STM32_RCC_PLLCFGR_PLLN_0 (0x01UL << STM32_RCC_PLLCFGR_PLLN_POS)
+#define STM32_RCC_PLLCFGR_PLLN_1 (0x02UL << STM32_RCC_PLLCFGR_PLLN_POS)
+#define STM32_RCC_PLLCFGR_PLLN_2 (0x04UL << STM32_RCC_PLLCFGR_PLLN_POS)
+#define STM32_RCC_PLLCFGR_PLLN_3 (0x08UL << STM32_RCC_PLLCFGR_PLLN_POS)
+#define STM32_RCC_PLLCFGR_PLLN_4 (0x10UL << STM32_RCC_PLLCFGR_PLLN_POS)
+#define STM32_RCC_PLLCFGR_PLLN_5 (0x20UL << STM32_RCC_PLLCFGR_PLLN_POS)
+#define STM32_RCC_PLLCFGR_PLLN_6 (0x40UL << STM32_RCC_PLLCFGR_PLLN_POS)
+
+#define STM32_RCC_PLLCFGR_PLLPEN_POS 16U
+#define STM32_RCC_PLLCFGR_PLLPEN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLPEN_POS)
+#define STM32_RCC_PLLCFGR_PLLPEN STM32_RCC_PLLCFGR_PLLPEN_MSK
+#define STM32_RCC_PLLCFGR_PLLP_POS 17U
+#define STM32_RCC_PLLCFGR_PLLP_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLP_POS)
+#define STM32_RCC_PLLCFGR_PLLP STM32_RCC_PLLCFGR_PLLP_MSK
+#define STM32_RCC_PLLCFGR_PLLQEN_POS 20U
+#define STM32_RCC_PLLCFGR_PLLQEN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLQEN_POS)
+#define STM32_RCC_PLLCFGR_PLLQEN STM32_RCC_PLLCFGR_PLLQEN_MSK
+
+#define STM32_RCC_PLLCFGR_PLLQ_POS 21U
+#define STM32_RCC_PLLCFGR_PLLQ_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLQ_POS)
+#define STM32_RCC_PLLCFGR_PLLQ STM32_RCC_PLLCFGR_PLLQ_MSK
+#define STM32_RCC_PLLCFGR_PLLQ_0 (0x1UL << STM32_RCC_PLLCFGR_PLLQ_POS)
+#define STM32_RCC_PLLCFGR_PLLQ_1 (0x2UL << STM32_RCC_PLLCFGR_PLLQ_POS)
+
+#define STM32_RCC_PLLCFGR_PLLREN_POS 24U
+#define STM32_RCC_PLLCFGR_PLLREN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLREN_POS)
+#define STM32_RCC_PLLCFGR_PLLREN STM32_RCC_PLLCFGR_PLLREN_MSK
+#define STM32_RCC_PLLCFGR_PLLR_POS 25U
+#define STM32_RCC_PLLCFGR_PLLR_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLR_POS)
+#define STM32_RCC_PLLCFGR_PLLR STM32_RCC_PLLCFGR_PLLR_MSK
+#define STM32_RCC_PLLCFGR_PLLR_0 (0x1UL << STM32_RCC_PLLCFGR_PLLR_POS)
+#define STM32_RCC_PLLCFGR_PLLR_1 (0x2UL << STM32_RCC_PLLCFGR_PLLR_POS)
+
+#define STM32_RCC_PLLCFGR_PLLPDIV_POS 27U
+#define STM32_RCC_PLLCFGR_PLLPDIV_MSK (0x1FUL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
+#define STM32_RCC_PLLCFGR_PLLPDIV STM32_RCC_PLLCFGR_PLLPDIV_MSK
+#define STM32_RCC_PLLCFGR_PLLPDIV_0 (0x01UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
+#define STM32_RCC_PLLCFGR_PLLPDIV_1 (0x02UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
+#define STM32_RCC_PLLCFGR_PLLPDIV_2 (0x04UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
+#define STM32_RCC_PLLCFGR_PLLPDIV_3 (0x08UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
+#define STM32_RCC_PLLCFGR_PLLPDIV_4 (0x10UL << STM32_RCC_PLLCFGR_PLLPDIV_POS)
 
 /****************  BIT DEFINITION FOR STM32_RCC_PLLSAI1CFGR REGISTER  ********/
 #define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS 8U
@@ -845,7 +842,7 @@
 #define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_6 \
 	(0x40UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS)
 
-#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_POS  16U
+#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_POS 16U
 #define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_MSK \
 	(0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_POS)
 #define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_MSK
@@ -1225,8 +1222,10 @@
 #define STM32_RCC_AHB1ENR_DMA2EN_MSK (0x1UL << STM32_RCC_AHB1ENR_DMA2EN_POS)
 #define STM32_RCC_AHB1ENR_DMA2EN STM32_RCC_AHB1ENR_DMA2EN_MSK
 #define STM32_RCC_AHB1ENR_DMAMUX1EN_POS 2U
-#define STM32_RCC_AHB1ENR_DMAMUX1EN_MSK (0x1UL << STM32_RCC_AHB1ENR_DMAMUX1EN_POS)
+#define STM32_RCC_AHB1ENR_DMAMUX1EN_MSK \
+	(0x1UL << STM32_RCC_AHB1ENR_DMAMUX1EN_POS)
 #define STM32_RCC_AHB1ENR_DMAMUX1EN STM32_RCC_AHB1ENR_DMAMUX1EN_MSK
+#define STM32_RCC_AHB1ENR_DMAMUXEN STM32_RCC_AHB1ENR_DMAMUX1EN_MSK
 #define STM32_RCC_AHB1ENR_FLASHEN_POS 8U
 #define STM32_RCC_AHB1ENR_FLASHEN_MSK (0x1UL << STM32_RCC_AHB1ENR_FLASHEN_POS)
 #define STM32_RCC_AHB1ENR_FLASHEN STM32_RCC_AHB1ENR_FLASHEN_MSK
@@ -1337,12 +1336,10 @@
 	(0x1UL << STM32_RCC_APB1ENR1_USART3EN_POS)
 #define STM32_RCC_APB1ENR1_USART3EN STM32_RCC_APB1ENR1_USART3EN_MSK
 #define STM32_RCC_APB1ENR1_UART4EN_POS 19U
-#define STM32_RCC_APB1ENR1_UART4EN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR1_UART4EN_POS)
+#define STM32_RCC_APB1ENR1_UART4EN_MSK (0x1UL << STM32_RCC_APB1ENR1_UART4EN_POS)
 #define STM32_RCC_APB1ENR1_UART4EN STM32_RCC_APB1ENR1_UART4EN_MSK
 #define STM32_RCC_APB1ENR1_UART5EN_POS 20U
-#define STM32_RCC_APB1ENR1_UART5EN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR1_UART5EN_POS)
+#define STM32_RCC_APB1ENR1_UART5EN_MSK (0x1UL << STM32_RCC_APB1ENR1_UART5EN_POS)
 #define STM32_RCC_APB1ENR1_UART5EN STM32_RCC_APB1ENR1_UART5EN_MSK
 #define STM32_RCC_APB1ENR1_I2C1EN_POS 21U
 #define STM32_RCC_APB1ENR1_I2C1EN_MSK (0x1UL << STM32_RCC_APB1ENR1_I2C1EN_POS)
@@ -1376,8 +1373,7 @@
 	(0x1UL << STM32_RCC_APB1ENR2_LPUART1EN_POS)
 #define STM32_RCC_APB1ENR2_LPUART1EN STM32_RCC_APB1ENR2_LPUART1EN_MSK
 #define STM32_RCC_APB1ENR2_I2C4EN_POS 1U
-#define STM32_RCC_APB1ENR2_I2C4EN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR2_I2C4EN_POS)
+#define STM32_RCC_APB1ENR2_I2C4EN_MSK (0x1UL << STM32_RCC_APB1ENR2_I2C4EN_POS)
 #define STM32_RCC_APB1ENR2_I2C4EN STM32_RCC_APB1ENR2_I2C4EN_MSK
 #define STM32_RCC_APB1ENR2_LPTIM2EN_POS 5U
 #define STM32_RCC_APB1ENR2_LPTIM2EN_MSK \
@@ -1392,12 +1388,10 @@
 	(0x1UL << STM32_RCC_APB1ENR2_FDCAN1EN_POS)
 #define STM32_RCC_APB1ENR2_FDCAN1EN STM32_RCC_APB1ENR2_FDCAN1EN_MSK
 #define STM32_RCC_APB1ENR2_USBFSEN_POS 21U
-#define STM32_RCC_APB1ENR2_USBFSEN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR2_USBFSEN_POS)
+#define STM32_RCC_APB1ENR2_USBFSEN_MSK (0x1UL << STM32_RCC_APB1ENR2_USBFSEN_POS)
 #define STM32_RCC_APB1ENR2_USBFSEN STM32_RCC_APB1ENR2_USBFSEN_MSK
 #define STM32_RCC_APB1ENR2_UCPD1EN_POS 23U
-#define STM32_RCC_APB1ENR2_UCPD1EN_MSK \
-	(0x1UL << STM32_RCC_APB1ENR2_UCPD1EN_POS)
+#define STM32_RCC_APB1ENR2_UCPD1EN_MSK (0x1UL << STM32_RCC_APB1ENR2_UCPD1EN_POS)
 #define STM32_RCC_APB1ENR2_UCPD1EN STM32_RCC_APB1ENR2_UCPD1EN_MSK
 
 /**************  BIT DEFINITION FOR STM32_RCC_APB2ENR REGISTER  ***************/
@@ -1928,8 +1922,6 @@
 #define STM32_CRS_CR_SWSYNC_MSK (0x1UL << STM32_CRS_CR_SWSYNC_POS)
 #define STM32_CRS_CR_SWSYNC STM32_CRS_CR_SWSYNC_MSK
 
-
-
 /*!< HSI48CAL configuration */
 #define STM32_RCC_CRRCR_HSI48CAL_POS 7U
 #define STM32_RCC_CRRCR_HSI48CAL_MSK (0x1FFUL << STM32_RCC_CRRCR_HSI48CAL_POS)
@@ -1949,102 +1941,100 @@
 #define STM32_SYSCFG_I2CFMP(n) BIT(n + 21)
 
 /* Peripheral bits for STM32_RCC_APB/AHB and DBGMCU regs */
-#define STM32_RCC_PB1_PWREN			BIT(28)
+#define STM32_RCC_PB1_PWREN BIT(28)
 
-#define STM32_RCC_PB2_SYSCFGEN		BIT(0)
-#define STM32_RCC_PB2_USART1		BIT(14)
+#define STM32_RCC_PB2_SYSCFGEN BIT(0)
+#define STM32_RCC_PB2_USART1 BIT(14)
 
-#define STM32_RCC_HB1_DMA1		BIT(0)
-#define STM32_RCC_HB1_DMA2		BIT(1)
+#define STM32_RCC_HB1_DMA1 BIT(0)
+#define STM32_RCC_HB1_DMA2 BIT(1)
 
-#define STM32_RCC_HB2_GPIOA		BIT(0)
-#define STM32_RCC_HB2_GPIOB		BIT(1)
-#define STM32_RCC_HB2_GPIOC		BIT(2)
-#define STM32_RCC_HB2_GPIOD		BIT(3)
-#define STM32_RCC_HB2_GPIOE		BIT(4)
-#define STM32_RCC_HB2_GPIOH		BIT(7)
-#define STM32_RCC_HB2_ADC1		BIT(13)
+#define STM32_RCC_HB2_GPIOA BIT(0)
+#define STM32_RCC_HB2_GPIOB BIT(1)
+#define STM32_RCC_HB2_GPIOC BIT(2)
+#define STM32_RCC_HB2_GPIOD BIT(3)
+#define STM32_RCC_HB2_GPIOE BIT(4)
+#define STM32_RCC_HB2_GPIOH BIT(7)
+#define STM32_RCC_HB2_ADC1 BIT(13)
 
 /* Reset causes definitions */
 /* Reset causes in RCC CSR register */
-#define  STM32_RCC_RESET_CAUSE	STM32_RCC_CSR
-#define  RESET_CAUSE_WDG                0x60000000
-#define  RESET_CAUSE_SFT                0x10000000
-#define  RESET_CAUSE_POR                0x08000000
-#define  RESET_CAUSE_PIN                0x04000000
-#define  RESET_CAUSE_OTHER              0xff000000
-#define  RESET_CAUSE_RMVF               BIT(23)
+#define STM32_RCC_RESET_CAUSE STM32_RCC_CSR
+#define RESET_CAUSE_WDG 0x60000000
+#define RESET_CAUSE_SFT 0x10000000
+#define RESET_CAUSE_POR 0x08000000
+#define RESET_CAUSE_PIN 0x04000000
+#define RESET_CAUSE_OTHER 0xff000000
+#define RESET_CAUSE_RMVF BIT(23)
 /* Power cause in PWR CSR register */
-#define STM32_PWR_RESET_CAUSE			STM32_PWR_CSR
-#define STM32_PWR_RESET_CAUSE_CLR		STM32_PWR_SCR
-#define  RESET_CAUSE_SBF                BIT(8)
-#define  RESET_CAUSE_SBF_CLR            BIT(8)
+#define STM32_PWR_RESET_CAUSE STM32_PWR_CSR
+#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_SCR
+#define RESET_CAUSE_SBF BIT(8)
+#define RESET_CAUSE_SBF_CLR BIT(8)
 
 /* --- Watchdogs --- */
 
 /* --- Real-Time Clock --- */
-#define STM32_RTC_TR                REG32(STM32_RTC_BASE + 0x00)
-#define STM32_RTC_DR                REG32(STM32_RTC_BASE + 0x04)
-#define STM32_RTC_CR                REG32(STM32_RTC_BASE + 0x08)
-#define STM32_RTC_CR_BYPSHAD        BIT(5)
-#define STM32_RTC_CR_ALRAE          BIT(8)
-#define STM32_RTC_CR_WUTE           BIT(10)
-#define STM32_RTC_CR_ALRAIE         BIT(12)
-#define STM32_RTC_CR_WUTIE          BIT(14)
-#define STM32_RTC_ISR               REG32(STM32_RTC_BASE + 0x0C)
-#define STM32_RTC_ISR_ALRAWF        BIT(0)
-#define STM32_RTC_ISR_WUTWF         BIT(2)
-#define STM32_RTC_ISR_INITS         BIT(4)
-#define STM32_RTC_ISR_RSF           BIT(5)
-#define STM32_RTC_ISR_INITF         BIT(6)
-#define STM32_RTC_ISR_INIT          BIT(7)
-#define STM32_RTC_ISR_ALRAF         BIT(8)
-#define STM32_RTC_ISR_WUTF          BIT(9)
-#define STM32_RTC_PRER              REG32(STM32_RTC_BASE + 0x10)
-#define STM32_RTC_PRER_A_MASK       (0x7f << 16)
-#define STM32_RTC_PRER_S_MASK       (0x7fff << 0)
-#define STM32_RTC_WUTR              REG32(STM32_RTC_BASE + 0x14)
-#define STM32_RTC_CALIBR            REG32(STM32_RTC_BASE + 0x18)
-#define STM32_RTC_ALRMAR            REG32(STM32_RTC_BASE + 0x1C)
-#define STM32_RTC_ALRMBR            REG32(STM32_RTC_BASE + 0x20)
-#define STM32_RTC_WPR               REG32(STM32_RTC_BASE + 0x24)
-#define STM32_RTC_SSR               REG32(STM32_RTC_BASE + 0x28)
-#define STM32_RTC_TSTR              REG32(STM32_RTC_BASE + 0x30)
-#define STM32_RTC_TSDR              REG32(STM32_RTC_BASE + 0x34)
-#define STM32_RTC_TAFCR             REG32(STM32_RTC_BASE + 0x40)
-#define STM32_RTC_ALRMASSR          REG32(STM32_RTC_BASE + 0x44)
-#define STM32_RTC_BACKUP(n)         REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
+#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00)
+#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04)
+#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08)
+#define STM32_RTC_CR_BYPSHAD BIT(5)
+#define STM32_RTC_CR_ALRAE BIT(8)
+#define STM32_RTC_CR_WUTE BIT(10)
+#define STM32_RTC_CR_ALRAIE BIT(12)
+#define STM32_RTC_CR_WUTIE BIT(14)
+#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C)
+#define STM32_RTC_ISR_ALRAWF BIT(0)
+#define STM32_RTC_ISR_WUTWF BIT(2)
+#define STM32_RTC_ISR_INITS BIT(4)
+#define STM32_RTC_ISR_RSF BIT(5)
+#define STM32_RTC_ISR_INITF BIT(6)
+#define STM32_RTC_ISR_INIT BIT(7)
+#define STM32_RTC_ISR_ALRAF BIT(8)
+#define STM32_RTC_ISR_WUTF BIT(9)
+#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10)
+#define STM32_RTC_PRER_A_MASK (0x7f << 16)
+#define STM32_RTC_PRER_S_MASK (0x7fff << 0)
+#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14)
+#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18)
+#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C)
+#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20)
+#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24)
+#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28)
+#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30)
+#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34)
+#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40)
+#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44)
+#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
 
 #define STM32_RTC_CLEAR_FLAG(x)                         \
-			(STM32_RTC_ISR = (~((x) | STM32_RTC_ISR_INIT) | \
-					(STM32_RTC_ISR & STM32_RTC_ISR_INIT)))
-
-#define STM32_BKP_DATA(n)           STM32_RTC_BACKUP(n)
-#define STM32_BKP_BYTES             128
-
-#define RTC_TR_PM_POS                  22U
-#define RTC_TR_PM_MSK                  (0x1UL << RTC_TR_PM_POS)
-#define RTC_TR_PM                      RTC_TR_PM_MSK
-#define RTC_TR_HT_POS                  20U
-#define RTC_TR_HT_MSK                  (0x3UL << RTC_TR_HT_POS)
-#define RTC_TR_HT                      RTC_TR_HT_MSK
-#define RTC_TR_HU_POS                  16U
-#define RTC_TR_HU_MSK                  (0xFUL << RTC_TR_HU_POS)
-#define RTC_TR_HU                      RTC_TR_HU_MSK
-#define RTC_TR_MNT_POS                 12U
-#define RTC_TR_MNT_MSK                 (0x7UL << RTC_TR_MNT_POS)
-#define RTC_TR_MNT                     RTC_TR_MNT_MSK
-#define RTC_TR_MNU_POS                 8U
-#define RTC_TR_MNU_MSK                 (0xFUL << RTC_TR_MNU_POS)
-#define RTC_TR_MNU                     RTC_TR_MNU_MSK
-#define RTC_TR_ST_POS                  4U
-#define RTC_TR_ST_MSK                  (0x7UL << RTC_TR_ST_POS)
-#define RTC_TR_ST                      RTC_TR_ST_MSK
-#define RTC_TR_SU_POS                  0U
-#define RTC_TR_SU_MSK                  (0xFUL << RTC_TR_SU_POS)
-#define RTC_TR_SU                      RTC_TR_SU_MSK
-
-
+	(STM32_RTC_ISR = (~((x) | STM32_RTC_ISR_INIT) | \
+			  (STM32_RTC_ISR & STM32_RTC_ISR_INIT)))
+
+#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n)
+#define STM32_BKP_BYTES 128
+
+#define RTC_TR_PM_POS 22U
+#define RTC_TR_PM_MSK (0x1UL << RTC_TR_PM_POS)
+#define RTC_TR_PM RTC_TR_PM_MSK
+#define RTC_TR_HT_POS 20U
+#define RTC_TR_HT_MSK (0x3UL << RTC_TR_HT_POS)
+#define RTC_TR_HT RTC_TR_HT_MSK
+#define RTC_TR_HU_POS 16U
+#define RTC_TR_HU_MSK (0xFUL << RTC_TR_HU_POS)
+#define RTC_TR_HU RTC_TR_HU_MSK
+#define RTC_TR_MNT_POS 12U
+#define RTC_TR_MNT_MSK (0x7UL << RTC_TR_MNT_POS)
+#define RTC_TR_MNT RTC_TR_MNT_MSK
+#define RTC_TR_MNU_POS 8U
+#define RTC_TR_MNU_MSK (0xFUL << RTC_TR_MNU_POS)
+#define RTC_TR_MNU RTC_TR_MNU_MSK
+#define RTC_TR_ST_POS 4U
+#define RTC_TR_ST_MSK (0x7UL << RTC_TR_ST_POS)
+#define RTC_TR_ST RTC_TR_ST_MSK
+#define RTC_TR_SU_POS 0U
+#define RTC_TR_SU_MSK (0xFUL << RTC_TR_SU_POS)
+#define RTC_TR_SU RTC_TR_SU_MSK
 
 /* --- SPI --- */
 
@@ -2061,8 +2051,8 @@ struct stm32_spi_regs {
 	unsigned int crcpr;
 	unsigned int rxcrcr;
 	unsigned int txcrcr;
-	unsigned int i2scfgr;	/* STM32L only */
-	unsigned int i2spr;	/* STM32L only */
+	unsigned int i2scfgr; /* STM32L only */
+	unsigned int i2spr; /* STM32L only */
 };
 /* Must be volatile, or compiler optimizes out repeated accesses */
 typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
@@ -2072,227 +2062,152 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
 #define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE)
 #define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE)
 
-#define STM32_SPI_CR1_BIDIMODE		BIT(15)
-#define STM32_SPI_CR1_BIDIOE		BIT(14)
-#define STM32_SPI_CR1_CRCEN		BIT(13)
-#define STM32_SPI_CR1_SSM		BIT(9)
-#define STM32_SPI_CR1_SSI		BIT(8)
-#define STM32_SPI_CR1_LSBFIRST		BIT(7)
-#define STM32_SPI_CR1_SPE		BIT(6)
-#define STM32_SPI_CR1_BR_DIV64R		(5 << 3)
-#define STM32_SPI_CR1_BR_DIV4R		BIT(3)
-#define STM32_SPI_CR1_MSTR		BIT(2)
-#define STM32_SPI_CR1_CPOL		BIT(1)
-#define STM32_SPI_CR1_CPHA		BIT(0)
-#define STM32_SPI_CR2_FRXTH		BIT(12)
-#define STM32_SPI_CR2_DATASIZE(n)	(((n) - 1) << 8)
-#define STM32_SPI_CR2_TXEIE		BIT(7)
-#define STM32_SPI_CR2_RXNEIE		BIT(6)
-#define STM32_SPI_CR2_NSSP		BIT(3)
-#define STM32_SPI_CR2_SSOE		BIT(2)
-#define STM32_SPI_CR2_TXDMAEN		BIT(1)
-#define STM32_SPI_CR2_RXDMAEN		BIT(0)
-
-#define STM32_SPI_SR_RXNE		BIT(0)
-#define STM32_SPI_SR_TXE		BIT(1)
-#define STM32_SPI_SR_CRCERR		BIT(4)
-#define STM32_SPI_SR_BSY		BIT(7)
-#define STM32_SPI_SR_FRLVL		(3 << 9)
-#define STM32_SPI_SR_FTLVL		(3 << 11)
+#define STM32_SPI_CR1_BIDIMODE BIT(15)
+#define STM32_SPI_CR1_BIDIOE BIT(14)
+#define STM32_SPI_CR1_CRCEN BIT(13)
+#define STM32_SPI_CR1_SSM BIT(9)
+#define STM32_SPI_CR1_SSI BIT(8)
+#define STM32_SPI_CR1_LSBFIRST BIT(7)
+#define STM32_SPI_CR1_SPE BIT(6)
+#define STM32_SPI_CR1_BR_DIV64R (5 << 3)
+#define STM32_SPI_CR1_BR_DIV4R BIT(3)
+#define STM32_SPI_CR1_MSTR BIT(2)
+#define STM32_SPI_CR1_CPOL BIT(1)
+#define STM32_SPI_CR1_CPHA BIT(0)
+#define STM32_SPI_CR2_FRXTH BIT(12)
+#define STM32_SPI_CR2_DATASIZE(n) (((n)-1) << 8)
+#define STM32_SPI_CR2_TXEIE BIT(7)
+#define STM32_SPI_CR2_RXNEIE BIT(6)
+#define STM32_SPI_CR2_NSSP BIT(3)
+#define STM32_SPI_CR2_SSOE BIT(2)
+#define STM32_SPI_CR2_TXDMAEN BIT(1)
+#define STM32_SPI_CR2_RXDMAEN BIT(0)
+
+#define STM32_SPI_SR_RXNE BIT(0)
+#define STM32_SPI_SR_TXE BIT(1)
+#define STM32_SPI_SR_CRCERR BIT(4)
+#define STM32_SPI_SR_BSY BIT(7)
+#define STM32_SPI_SR_FRLVL (3 << 9)
+#define STM32_SPI_SR_FTLVL (3 << 11)
 /* --- Debug --- */
-#define STM32_DBGMCU_APB1FZ         REG32(STM32_DBGMCU_BASE + 0x08)
-#define STM32_DBGMCU_APB2FZ         REG32(STM32_DBGMCU_BASE + 0x0C)
+#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08)
+#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C)
 
 /* --- Flash --- */
-#define STM32_FLASH_ACR             REG32(STM32_FLASH_REGS_BASE + 0x00)
+#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00)
 #define STM32_FLASH_ACR_LATENCY_SHIFT (0)
-#define STM32_FLASH_ACR_LATENCY_MASK  (7 << STM32_FLASH_ACR_LATENCY_SHIFT)
-#define STM32_FLASH_ACR_PRFTEN      BIT(8)
-#define STM32_FLASH_ACR_ICEN        BIT(9)
-#define STM32_FLASH_ACR_DCEN        BIT(10)
-#define STM32_FLASH_ACR_ICRST       BIT(11)
-#define STM32_FLASH_ACR_DCRST       BIT(12)
-#define STM32_FLASH_PDKEYR          REG32(STM32_FLASH_REGS_BASE + 0x04)
-#define STM32_FLASH_KEYR            REG32(STM32_FLASH_REGS_BASE + 0x08)
-#define  FLASH_KEYR_KEY1            0x45670123
-#define  FLASH_KEYR_KEY2            0xCDEF89AB
-#define STM32_FLASH_OPTKEYR         REG32(STM32_FLASH_REGS_BASE + 0x10)
-#define  FLASH_OPTKEYR_KEY1         0x08192A3B
-#define  FLASH_OPTKEYR_KEY2         0x4C5D6E7F
-#define STM32_FLASH_SR              REG32(STM32_FLASH_REGS_BASE + 0x20)
-#define  FLASH_SR_BUSY              BIT(16)
-#define  FLASH_SR_ERR_MASK          (0xc3fa)
-#define STM32_FLASH_CR              REG32(STM32_FLASH_REGS_BASE + 0x28)
-#define  FLASH_CR_PG                BIT(0)
-#define  FLASH_CR_PER               BIT(1)
-#define  FLASH_CR_STRT              BIT(16)
-#define  FLASH_CR_OPTSTRT           BIT(17)
-#define  FLASH_CR_OBL_LAUNCH        BIT(27)
-#define  FLASH_CR_OPTLOCK           BIT(30)
-#define  FLASH_CR_LOCK              BIT(31)
-#define  FLASH_CR_PNB(sec)          (((sec) & 0xff) << 3)
-#define  FLASH_CR_PNB_MASK          FLASH_CR_PNB(0xff)
-#define STM32_FLASH_ECCR            REG32(STM32_FLASH_REGS_BASE + 0x30)
-#define STM32_FLASH_OPTR            REG32(STM32_FLASH_REGS_BASE + 0x40)
-#define STM32_FLASH_WRP1AR          REG32(STM32_FLASH_REGS_BASE + 0x58)
-#define STM32_FLASH_WRP1BR          REG32(STM32_FLASH_REGS_BASE + 0x5C)
+#define STM32_FLASH_ACR_LATENCY_MASK (7 << STM32_FLASH_ACR_LATENCY_SHIFT)
+#define STM32_FLASH_ACR_PRFTEN BIT(8)
+#define STM32_FLASH_ACR_ICEN BIT(9)
+#define STM32_FLASH_ACR_DCEN BIT(10)
+#define STM32_FLASH_ACR_ICRST BIT(11)
+#define STM32_FLASH_ACR_DCRST BIT(12)
+#define STM32_FLASH_PDKEYR REG32(STM32_FLASH_REGS_BASE + 0x04)
+#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x08)
+#define FLASH_KEYR_KEY1 0x45670123
+#define FLASH_KEYR_KEY2 0xCDEF89AB
+#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x10)
+#define FLASH_OPTKEYR_KEY1 0x08192A3B
+#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F
+#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x20)
+#define FLASH_SR_BUSY BIT(16)
+#define FLASH_SR_ERR_MASK (0xc3fa)
+#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x28)
+#define FLASH_CR_PG BIT(0)
+#define FLASH_CR_PER BIT(1)
+#define FLASH_CR_STRT BIT(16)
+#define FLASH_CR_OPTSTRT BIT(17)
+#define FLASH_CR_OBL_LAUNCH BIT(27)
+#define FLASH_CR_OPTLOCK BIT(30)
+#define FLASH_CR_LOCK BIT(31)
+#define FLASH_CR_PNB(sec) (((sec)&0xff) << 3)
+#define FLASH_CR_PNB_MASK FLASH_CR_PNB(0xff)
+#define STM32_FLASH_ECCR REG32(STM32_FLASH_REGS_BASE + 0x30)
+#define STM32_FLASH_OPTR REG32(STM32_FLASH_REGS_BASE + 0x40)
+#define STM32_FLASH_WRP1AR REG32(STM32_FLASH_REGS_BASE + 0x58)
+#define STM32_FLASH_WRP1BR REG32(STM32_FLASH_REGS_BASE + 0x5C)
 /* Minimum number of bytes that can be written to flash */
-#define STM32_FLASH_MIN_WRITE_SIZE  CONFIG_FLASH_WRITE_SIZE
+#define STM32_FLASH_MIN_WRITE_SIZE CONFIG_FLASH_WRITE_SIZE
 
-#define STM32_OPTB_WRP1AR           STM32_FLASH_WRP1AR
-#define STM32_OPTB_WRP1BR           STM32_FLASH_WRP1BR
+#define STM32_OPTB_WRP1AR STM32_FLASH_WRP1AR
+#define STM32_OPTB_WRP1BR STM32_FLASH_WRP1BR
 
 /* --- External Interrupts --- */
-#define STM32_EXTI_IMR              REG32(STM32_EXTI_BASE + 0x00)
-#define STM32_EXTI_EMR              REG32(STM32_EXTI_BASE + 0x04)
-#define STM32_EXTI_RTSR             REG32(STM32_EXTI_BASE + 0x08)
-#define STM32_EXTI_FTSR             REG32(STM32_EXTI_BASE + 0x0c)
-#define STM32_EXTI_SWIER            REG32(STM32_EXTI_BASE + 0x10)
-#define STM32_EXTI_PR               REG32(STM32_EXTI_BASE + 0x14)
+#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00)
+#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04)
+#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08)
+#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c)
+#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10)
+#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14)
 
-#define EXTI_RTC_ALR_EVENT          BIT(18)
+#define EXTI_RTC_ALR_EVENT BIT(18)
 
 /* --- ADC --- */
-#define STM32_ADC1_ISR              REG32(STM32_ADC1_BASE + 0x00)
-#define STM32_ADC1_ISR_ADRDY        BIT(0)
-#define STM32_ADC1_IER              REG32(STM32_ADC1_BASE + 0x04)
-#define STM32_ADC1_IER_AWDIE        BIT(7)
-#define STM32_ADC1_IER_OVRIE        BIT(4)
-#define STM32_ADC1_IER_EOSEQIE      BIT(3)
-#define STM32_ADC1_IER_EOCIE        BIT(2)
-#define STM32_ADC1_IER_EOSMPIE      BIT(1)
-#define STM32_ADC1_IER_ADRDYIE      BIT(0)
-
-#define STM32_ADC1_CR               REG32(STM32_ADC1_BASE + 0x08)
-#define STM32_ADC1_CR_ADEN          BIT(0)
-#define STM32_ADC1_CR_ADDIS         BIT(1)
-#define STM32_ADC1_CR_ADSTP         BIT(4)
-#define STM32_ADC1_CR_ADVREGEN      BIT(28)
-#define STM32_ADC1_CR_DEEPPWD	    BIT(29)
-#define STM32_ADC1_CR_ADCAL         BIT(31)
-#define STM32_ADC1_CFGR             REG32(STM32_ADC1_BASE + 0x0C)
+#define STM32_ADC1_ISR REG32(STM32_ADC1_BASE + 0x00)
+#define STM32_ADC1_ISR_ADRDY BIT(0)
+#define STM32_ADC1_IER REG32(STM32_ADC1_BASE + 0x04)
+#define STM32_ADC1_IER_AWDIE BIT(7)
+#define STM32_ADC1_IER_OVRIE BIT(4)
+#define STM32_ADC1_IER_EOSEQIE BIT(3)
+#define STM32_ADC1_IER_EOCIE BIT(2)
+#define STM32_ADC1_IER_EOSMPIE BIT(1)
+#define STM32_ADC1_IER_ADRDYIE BIT(0)
+
+#define STM32_ADC1_CR REG32(STM32_ADC1_BASE + 0x08)
+#define STM32_ADC1_CR_ADEN BIT(0)
+#define STM32_ADC1_CR_ADDIS BIT(1)
+#define STM32_ADC1_CR_ADSTP BIT(4)
+#define STM32_ADC1_CR_ADVREGEN BIT(28)
+#define STM32_ADC1_CR_DEEPPWD BIT(29)
+#define STM32_ADC1_CR_ADCAL BIT(31)
+#define STM32_ADC1_CFGR REG32(STM32_ADC1_BASE + 0x0C)
 /* Analog watchdog channel selection */
-#define STM32_ADC1_CFGR_AWDCH_MASK  (0x1f << 26)
-#define STM32_ADC1_CFGR_AWDEN       BIT(23)
-#define STM32_ADC1_CFGR_AWDSGL      BIT(22)
-#define STM32_ADC1_CFGR_AUTDLY	    BIT(14)
+#define STM32_ADC1_CFGR_AWDCH_MASK (0x1f << 26)
+#define STM32_ADC1_CFGR_AWDEN BIT(23)
+#define STM32_ADC1_CFGR_AWDSGL BIT(22)
+#define STM32_ADC1_CFGR_AUTDLY BIT(14)
 /* Selects single vs continuous */
-#define STM32_ADC1_CFGR_CONT        BIT(13)
+#define STM32_ADC1_CFGR_CONT BIT(13)
 /* Selects ADC_DR overwrite vs preserve */
-#define STM32_ADC1_CFGR_OVRMOD      BIT(12)
+#define STM32_ADC1_CFGR_OVRMOD BIT(12)
 /* External trigger polarity selection */
-#define STM32_ADC1_CFGR_EXTEN_DIS   (0 << 10)
-#define STM32_ADC1_CFGR_EXTEN_RISE  (1 << 10)
-#define STM32_ADC1_CFGR_EXTEN_FALL  (2 << 10)
-#define STM32_ADC1_CFGR_EXTEN_BOTH  (3 << 10)
-#define STM32_ADC1_CFGR_EXTEN_MASK  (3 << 10)
-#define STM32_ADC1_CFGR_ALIGN	    BIT(5)
+#define STM32_ADC1_CFGR_EXTEN_DIS (0 << 10)
+#define STM32_ADC1_CFGR_EXTEN_RISE (1 << 10)
+#define STM32_ADC1_CFGR_EXTEN_FALL (2 << 10)
+#define STM32_ADC1_CFGR_EXTEN_BOTH (3 << 10)
+#define STM32_ADC1_CFGR_EXTEN_MASK (3 << 10)
+#define STM32_ADC1_CFGR_ALIGN BIT(5)
 /* External trigger selection */
-#define STM32_ADC1_CFGR_TRG0        (0 << 6)
-#define STM32_ADC1_CFGR_TRG1        (1 << 6)
-#define STM32_ADC1_CFGR_TRG2        (2 << 6)
-#define STM32_ADC1_CFGR_TRG3        (3 << 6)
-#define STM32_ADC1_CFGR_TRG4        (4 << 6)
-#define STM32_ADC1_CFGR_TRG5        (5 << 6)
-#define STM32_ADC1_CFGR_TRG6        (6 << 6)
-#define STM32_ADC1_CFGR_TRG7        (7 << 6)
-#define STM32_ADC1_CFGR_TRG_MASK    (7 << 6)
+#define STM32_ADC1_CFGR_TRG0 (0 << 6)
+#define STM32_ADC1_CFGR_TRG1 (1 << 6)
+#define STM32_ADC1_CFGR_TRG2 (2 << 6)
+#define STM32_ADC1_CFGR_TRG3 (3 << 6)
+#define STM32_ADC1_CFGR_TRG4 (4 << 6)
+#define STM32_ADC1_CFGR_TRG5 (5 << 6)
+#define STM32_ADC1_CFGR_TRG6 (6 << 6)
+#define STM32_ADC1_CFGR_TRG7 (7 << 6)
+#define STM32_ADC1_CFGR_TRG_MASK (7 << 6)
 /* Selects circular vs one-shot */
-#define STM32_ADC1_CFGR_DMACFG      BIT(1)
-#define STM32_ADC1_CFGR_DMAEN       BIT(0)
-#define STM32_ADC1_CFGR2            REG32(STM32_ADC1_BASE + 0x10)
+#define STM32_ADC1_CFGR_DMACFG BIT(1)
+#define STM32_ADC1_CFGR_DMAEN BIT(0)
+#define STM32_ADC1_CFGR2 REG32(STM32_ADC1_BASE + 0x10)
 /* Sampling time selection - 1.5 ADC cycles min, 239.5 cycles max */
-#define STM32_ADC1_SMPR1            REG32(STM32_ADC1_BASE + 0x14)
-#define STM32_ADC1_SMPR2            REG32(STM32_ADC1_BASE + 0x18)
+#define STM32_ADC1_SMPR1 REG32(STM32_ADC1_BASE + 0x14)
+#define STM32_ADC1_SMPR2 REG32(STM32_ADC1_BASE + 0x18)
 /* Macro to convert enum stm32_adc_smpr to SMP bits of the ADC_SMPR register */
-#define STM32_ADC1_SMPR_SMP(s)      ((s) - 1)
-#define STM32_ADC1_TR               REG32(STM32_ADC1_BASE + 0x20)
-#define STM32_ADC1_CHSELR           REG32(STM32_ADC1_BASE + 0x28)
-#define STM32_ADC1_DR               REG32(STM32_ADC1_BASE + 0x40)
-#define STM32_ADC1_JSQR             REG32(STM32_ADC1_BASE + 0x4C)
-#define STM32_ADC1_JDR1             REG32(STM32_ADC1_BASE + 0x80)
-#define STM32_ADC1_JDR2             REG32(STM32_ADC1_BASE + 0x84)
-#define STM32_ADC1_JDR3             REG32(STM32_ADC1_BASE + 0x88)
-#define STM32_ADC1_JDR4             REG32(STM32_ADC1_BASE + 0x8C)
-#define STM32_ADC1_CCR              REG32(STM32_ADC1_BASE + 0x308)
+#define STM32_ADC1_SMPR_SMP(s) ((s)-1)
+#define STM32_ADC1_TR REG32(STM32_ADC1_BASE + 0x20)
+#define STM32_ADC1_CHSELR REG32(STM32_ADC1_BASE + 0x28)
+#define STM32_ADC1_DR REG32(STM32_ADC1_BASE + 0x40)
+#define STM32_ADC1_JSQR REG32(STM32_ADC1_BASE + 0x4C)
+#define STM32_ADC1_JDR1 REG32(STM32_ADC1_BASE + 0x80)
+#define STM32_ADC1_JDR2 REG32(STM32_ADC1_BASE + 0x84)
+#define STM32_ADC1_JDR3 REG32(STM32_ADC1_BASE + 0x88)
+#define STM32_ADC1_JDR4 REG32(STM32_ADC1_BASE + 0x8C)
+#define STM32_ADC1_CCR REG32(STM32_ADC1_BASE + 0x308)
 
 /* --- USB --- */
-#define STM32_USB_EP(n)            REG16(STM32_USB_FS_BASE + (n) * 4)
-
-#define STM32_USB_CNTR             REG16(STM32_USB_FS_BASE + 0x40)
-
-#define STM32_USB_CNTR_FRES	    BIT(0)
-#define STM32_USB_CNTR_PDWN	    BIT(1)
-#define STM32_USB_CNTR_LP_MODE	    BIT(2)
-#define STM32_USB_CNTR_FSUSP	    BIT(3)
-#define STM32_USB_CNTR_RESUME	    BIT(4)
-#define STM32_USB_CNTR_L1RESUME	    BIT(5)
-#define STM32_USB_CNTR_L1REQM	    BIT(7)
-#define STM32_USB_CNTR_ESOFM	    BIT(8)
-#define STM32_USB_CNTR_SOFM	    BIT(9)
-#define STM32_USB_CNTR_RESETM	    BIT(10)
-#define STM32_USB_CNTR_SUSPM	    BIT(11)
-#define STM32_USB_CNTR_WKUPM	    BIT(12)
-#define STM32_USB_CNTR_ERRM	    BIT(13)
-#define STM32_USB_CNTR_PMAOVRM	    BIT(14)
-#define STM32_USB_CNTR_CTRM	    BIT(15)
-
-#define STM32_USB_ISTR             REG16(STM32_USB_FS_BASE + 0x44)
-
-#define STM32_USB_ISTR_EP_ID_MASK   (0x000f)
-#define STM32_USB_ISTR_DIR	    BIT(4)
-#define STM32_USB_ISTR_L1REQ	    BIT(7)
-#define STM32_USB_ISTR_ESOF	    BIT(8)
-#define STM32_USB_ISTR_SOF	    BIT(9)
-#define STM32_USB_ISTR_RESET	    BIT(10)
-#define STM32_USB_ISTR_SUSP	    BIT(11)
-#define STM32_USB_ISTR_WKUP	    BIT(12)
-#define STM32_USB_ISTR_ERR	    BIT(13)
-#define STM32_USB_ISTR_PMAOVR	    BIT(14)
-#define STM32_USB_ISTR_CTR	    BIT(15)
-
-#define STM32_USB_FNR              REG16(STM32_USB_FS_BASE + 0x48)
-
-#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14)
-#define STM32_USB_FNR_RXDP_RXDM_MASK  (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT)
-
-#define STM32_USB_DADDR            REG16(STM32_USB_FS_BASE + 0x4C)
-#define STM32_USB_BTABLE           REG16(STM32_USB_FS_BASE + 0x50)
-#define STM32_USB_LPMCSR           REG16(STM32_USB_FS_BASE + 0x54)
-#define STM32_USB_BCDR             REG16(STM32_USB_FS_BASE + 0x58)
-
-#define STM32_USB_BCDR_BCDEN	    BIT(0)
-#define STM32_USB_BCDR_DCDEN	    BIT(1)
-#define STM32_USB_BCDR_PDEN	    BIT(2)
-#define STM32_USB_BCDR_SDEN	    BIT(3)
-#define STM32_USB_BCDR_DCDET	    BIT(4)
-#define STM32_USB_BCDR_PDET	    BIT(5)
-#define STM32_USB_BCDR_SDET	    BIT(6)
-#define STM32_USB_BCDR_PS2DET	    BIT(7)
-#define STM32_USB_BCDR_DPPU	    BIT(15)
-
-#define EP_MASK     0x0F0F
-#define EP_TX_DTOG  0x0040
-#define EP_TX_MASK  0x0030
-#define EP_TX_VALID 0x0030
-#define EP_TX_NAK   0x0020
-#define EP_TX_STALL 0x0010
-#define EP_TX_DISAB 0x0000
-#define EP_RX_DTOG  0x4000
-#define EP_RX_MASK  0x3000
-#define EP_RX_VALID 0x3000
-#define EP_RX_NAK   0x2000
-#define EP_RX_STALL 0x1000
-#define EP_RX_DISAB 0x0000
-
-#define EP_STATUS_OUT 0x0100
-
-#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK)
-#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID)
-
-#define STM32_TOGGLE_EP(n, mask, val, flags) \
-	STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \
-			^ (val)) | (flags))
+#define STM32_USB_BCDR_DPPU BIT(15)
 
 /* --- DMA --- */
 
@@ -2344,11 +2259,11 @@ enum dma_channel {
 
 /* Registers for a single channel of the DMA controller */
 struct stm32_dma_chan {
-	uint32_t	ccr;		/* Control */
-	uint32_t	cndtr;		/* Number of data to transfer */
-	uint32_t	cpar;		/* Peripheral address */
-	uint32_t	cmar;		/* Memory address */
-	uint32_t	reserved;
+	uint32_t ccr; /* Control */
+	uint32_t cndtr; /* Number of data to transfer */
+	uint32_t cpar; /* Peripheral address */
+	uint32_t cmar; /* Memory address */
+	uint32_t reserved;
 };
 
 /* Always use stm32_dma_chan_t so volatile keyword is included! */
@@ -2359,8 +2274,8 @@ typedef stm32_dma_chan_t dma_chan_t;
 
 /* Registers for the DMA controller */
 struct stm32_dma_regs {
-	uint32_t	isr;
-	uint32_t	ifcr;
+	uint32_t isr;
+	uint32_t ifcr;
 	stm32_dma_chan_t chan[STM32_DMAC_COUNT];
 };
 
@@ -2369,74 +2284,175 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
 
 #define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE)
 
-
-#define STM32_DMA_CCR_CHANNEL(channel)		 (0)
+#define STM32_DMA_CCR_CHANNEL(channel) (0)
 #define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE)
 #define STM32_DMA_REGS(channel) \
 	((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_REGS : STM32_DMA2_REGS)
-#define STM32_DMA_CSELR(channel) \
-	REG32(((channel) < STM32_DMAC_PER_CTLR ? \
-			STM32_DMA1_BASE : STM32_DMA2_BASE)  + 0xA8)
+#define STM32_DMA_CSELR(channel)                                    \
+	REG32(((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_BASE :  \
+						 STM32_DMA2_BASE) + \
+	      0xA8)
 
 /* Bits for DMA controller regs (isr and ifcr) */
-#define STM32_DMA_CH_OFFSET(channel)   (4 * ((channel) % STM32_DMAC_PER_CTLR))
+#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR))
 #define STM32_DMA_ISR_MASK(channel, mask) \
 	((mask) << STM32_DMA_CH_OFFSET(channel))
-#define STM32_DMA_ISR_GIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(0))
-#define STM32_DMA_ISR_TCIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(1))
-#define STM32_DMA_ISR_HTIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(2))
-#define STM32_DMA_ISR_TEIF(channel)	STM32_DMA_ISR_MASK(channel, BIT(3))
-#define STM32_DMA_ISR_ALL(channel)	STM32_DMA_ISR_MASK(channel, 0x0f)
-
-#define STM32_DMA_GIF                   BIT(0)
-#define STM32_DMA_TCIF                  BIT(1)
-#define STM32_DMA_HTIF                  BIT(2)
-#define STM32_DMA_TEIF                  BIT(3)
-#define STM32_DMA_ALL                   0xf
-
-#define STM32_DMA_GET_ISR(channel)      \
-	((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_ISR(channel, val) \
-	(STM32_DMA_REGS(channel)->isr = \
-	((STM32_DMA_REGS(channel)->isr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-#define STM32_DMA_GET_IFCR(channel)      \
-	((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \
-	& STM32_DMA_ALL)
-#define STM32_DMA_SET_IFCR(channel, val) \
-	(STM32_DMA_REGS(channel)->ifcr = \
-	((STM32_DMA_REGS(channel)->ifcr & \
-	~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
-	(((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
-
+#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0))
+#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1))
+#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2))
+#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3))
+#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f)
+
+#define STM32_DMA_GIF BIT(0)
+#define STM32_DMA_TCIF BIT(1)
+#define STM32_DMA_HTIF BIT(2)
+#define STM32_DMA_TEIF BIT(3)
+#define STM32_DMA_ALL 0xf
+
+#define STM32_DMA_GET_ISR(channel)                                        \
+	((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) & \
+	 STM32_DMA_ALL)
+#define STM32_DMA_SET_ISR(channel, val)                                \
+	(STM32_DMA_REGS(channel)->isr =                                \
+		 ((STM32_DMA_REGS(channel)->isr &                      \
+		   ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
+		  (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
+#define STM32_DMA_GET_IFCR(channel)                                        \
+	((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) & \
+	 STM32_DMA_ALL)
+#define STM32_DMA_SET_IFCR(channel, val)                               \
+	(STM32_DMA_REGS(channel)->ifcr =                               \
+		 ((STM32_DMA_REGS(channel)->ifcr &                     \
+		   ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \
+		  (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel))))
 
 /* Bits for DMA channel regs */
-#define STM32_DMA_CCR_EN		BIT(0)
-#define STM32_DMA_CCR_TCIE		BIT(1)
-#define STM32_DMA_CCR_HTIE		BIT(2)
-#define STM32_DMA_CCR_TEIE		BIT(3)
-#define STM32_DMA_CCR_DIR		BIT(4)
-#define STM32_DMA_CCR_CIRC		BIT(5)
-#define STM32_DMA_CCR_PINC		BIT(6)
-#define STM32_DMA_CCR_MINC		BIT(7)
-#define STM32_DMA_CCR_PSIZE_8_BIT	(0 << 8)
-#define STM32_DMA_CCR_PSIZE_16_BIT	(1 << 8)
-#define STM32_DMA_CCR_PSIZE_32_BIT	(2 << 8)
-#define STM32_DMA_CCR_MSIZE_8_BIT	(0 << 10)
-#define STM32_DMA_CCR_MSIZE_16_BIT	(1 << 10)
-#define STM32_DMA_CCR_MSIZE_32_BIT	(2 << 10)
-#define STM32_DMA_CCR_PL_LOW		(0 << 12)
-#define STM32_DMA_CCR_PL_MEDIUM		(1 << 12)
-#define STM32_DMA_CCR_PL_HIGH		(2 << 12)
-#define STM32_DMA_CCR_PL_VERY_HIGH	(3 << 12)
-#define STM32_DMA_CCR_MEM2MEM		BIT(14)
+#define STM32_DMA_CCR_EN BIT(0)
+#define STM32_DMA_CCR_TCIE BIT(1)
+#define STM32_DMA_CCR_HTIE BIT(2)
+#define STM32_DMA_CCR_TEIE BIT(3)
+#define STM32_DMA_CCR_DIR BIT(4)
+#define STM32_DMA_CCR_CIRC BIT(5)
+#define STM32_DMA_CCR_PINC BIT(6)
+#define STM32_DMA_CCR_MINC BIT(7)
+#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8)
+#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8)
+#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8)
+#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10)
+#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10)
+#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10)
+#define STM32_DMA_CCR_PL_LOW (0 << 12)
+#define STM32_DMA_CCR_PL_MEDIUM (1 << 12)
+#define STM32_DMA_CCR_PL_HIGH (2 << 12)
+#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12)
+#define STM32_DMA_CCR_MEM2MEM BIT(14)
+
+/* The requests for the DMA1/DMA2 controllers are routed through DMAMUX. */
+/* DMAMUX registers */
+#define STM32_DMAMUX_CxCR(x) REG32(STM32_DMAMUX_BASE + 4 * (x))
+#define STM32_DMAMUX_CSR REG32(STM32_DMAMUX_BASE + 0x80)
+#define STM32_DMAMUX_CFR REG32(STM32_DMAMUX_BASE + 0x84)
+#define STM32_DMAMUX_RGxCR(x) REG32(STM32_DMAMUX_BASE + 0x100 + 4 * (x))
+#define STM32_DMAMUX_RGSR REG32(STM32_DMAMUX_BASE + 0x140)
+#define STM32_DMAMUX_RGCFR REG32(STM32_DMAMUX_BASE + 0x144)
+
+enum dmamux1_request {
+	DMAMUX_REQ_ADC1 = 5,
+	DMAMUX_REQ_ADC2 = 6,
+	DMAMUX_REQ_DAC1 = 7,
+	DMAMUX_REQ_DAC2 = 8,
+	DMAMUX_REQ_TIM6_UP = 9,
+	DMAMUX_REQ_TIM7_UP = 10,
+	DMAMUX_REQ_SPI1_RX = 11,
+	DMAMUX_REQ_SPI1_TX = 12,
+	DMAMUX_REQ_SPI2_RX = 13,
+	DMAMUX_REQ_SPI2_TX = 14,
+	DMAMUX_REQ_SPI3_RX = 15,
+	DMAMUX_REQ_SPI3_TX = 16,
+	DMAMUX_REQ_I2C1_RX = 17,
+	DMAMUX_REQ_I2C1_TX = 18,
+	DMAMUX_REQ_I2C2_RX = 19,
+	DMAMUX_REQ_I2C2_TX = 20,
+	DMAMUX_REQ_I2C3_RX = 21,
+	DMAMUX_REQ_I2C3_TX = 22,
+	DMAMUX_REQ_I2C4_RX = 23,
+	DMAMUX_REQ_I2C4_TX = 24,
+	DMAMUX_REQ_USART1_RX = 25,
+	DMAMUX_REQ_USART1_TX = 26,
+	DMAMUX_REQ_USART2_RX = 27,
+	DMAMUX_REQ_USART2_TX = 28,
+	DMAMUX_REQ_USART3_RX = 29,
+	DMAMUX_REQ_USART3_TX = 30,
+	DMAMUX_REQ_UART4_RX = 31,
+	DMAMUX_REQ_UART4_TX = 32,
+	DMAMUX_REQ_UART5_RX = 33,
+	DMAMUX_REQ_UART5_TX = 34,
+	DMAMUX_REQ_LPUART1_RX = 35,
+	DMAMUX_REQ_LPUART1_TX = 36,
+	DMAMUX_REQ_SAI1_A = 37,
+	DMAMUX_REQ_SAI1_B = 38,
+	DMAMUX_REQ_SAI2_A = 39,
+	DMAMUX_REQ_SAI2_B = 40,
+	DMAMUX_REQ_OCTOSPI1 = 41,
+	DMAMUX_REQ_TIM1_CH1 = 42,
+	DMAMUX_REQ_TIM1_CH2 = 43,
+	DMAMUX_REQ_TIM1_CH3 = 44,
+	DMAMUX_REQ_TIM1_CH4 = 45,
+	DMAMUX_REQ_TIM1_UP = 46,
+	DMAMUX_REQ_TIM1_TRIG = 47,
+	DMAMUX_REQ_TIM1_COM = 48,
+	DMAMUX_REQ_TIM8_CH1 = 49,
+	DMAMUX_REQ_TIM8_CH2 = 50,
+	DMAMUX_REQ_TIM8_CH3 = 51,
+	DMAMUX_REQ_TIM8_CH4 = 52,
+	DMAMUX_REQ_TIM8_UP = 53,
+	DMAMUX_REQ_TIM8_TRIG = 54,
+	DMAMUX_REQ_TIM8_COM = 55,
+	DMAMUX_REQ_TIM2_CH1 = 56,
+	DMAMUX_REQ_TIM2_CH2 = 57,
+	DMAMUX_REQ_TIM2_CH3 = 58,
+	DMAMUX_REQ_TIM2_CH4 = 59,
+	DMAMUX_REQ_TIM2_UP = 60,
+	DMAMUX_REQ_TIM3_CH1 = 61,
+	DMAMUX_REQ_TIM3_CH2 = 62,
+	DMAMUX_REQ_TIM3_CH3 = 63,
+	DMAMUX_REQ_TIM3_CH4 = 64,
+	DMAMUX_REQ_TIM3_UP = 65,
+	DMAMUX_REQ_TIM3_TRIG = 66,
+	DMAMUX_REQ_TIM4_CH1 = 67,
+	DMAMUX_REQ_TIM4_CH2 = 68,
+	DMAMUX_REQ_TIM4_CH3 = 69,
+	DMAMUX_REQ_TIM4_CH4 = 70,
+	DMAMUX_REQ_TIM4_UP = 71,
+	DMAMUX_REQ_TIM5_CH1 = 72,
+	DMAMUX_REQ_TIM5_CH2 = 73,
+	DMAMUX_REQ_TIM5_CH3 = 74,
+	DMAMUX_REQ_TIM5_CH4 = 75,
+	DMAMUX_REQ_TIM5_UP = 76,
+	DMAMUX_REQ_TIM5_TRIG = 77,
+	DMAMUX_REQ_TIM15_CH1 = 78,
+	DMAMUX_REQ_TIM15_UP = 79,
+	DMAMUX_REQ_TIM15_TRIG = 80,
+	DMAMUX_REQ_TIM15_COM = 81,
+	DMAMUX_REQ_TIM16_CH1 = 82,
+	DMAMUX_REQ_TIM16_UP = 83,
+	DMAMUX_REQ_TIM17_CH1 = 84,
+	DMAMUX_REQ_TIM17_UP = 85,
+	DMAMUX_REQ_DFSDM1_FLT0 = 86,
+	DMAMUX_REQ_DFSDM1_FLT1 = 87,
+	DMAMUX_REQ_DFSDM1_FLT2 = 88,
+	DMAMUX_REQ_DFSDM1_FLT3 = 89,
+	DMAMUX_REQ_AES_IN = 90,
+	DMAMUX_REQ_AES_OUT = 91,
+	DMAMUX_REQ_HASH_IN = 92,
+	DMAMUX_REQ_USBPD_TX = 93,
+	DMAMUX_REQ_USBPD_RX = 94,
+};
 
 /* LPUART gets accessed as UART9 in STM32 uart module */
-#define STM32_USART9_BASE		STM32_LPUART1_BASE
-#define STM32_IRQ_USART9		STM32_IRQ_LPUART1
-#define DMAMUX_REQ_UART9_RX		DMAMUX_REQ_LPUART1_RX
-#define DMAMUX_REQ_UART9_TX		DMAMUX_REQ_LPUART1_TX
+#define STM32_USART9_BASE STM32_LPUART1_BASE
+#define STM32_IRQ_USART9 STM32_IRQ_LPUART1
+#define DMAMUX_REQ_UART9_RX DMAMUX_REQ_LPUART1_RX
+#define DMAMUX_REQ_UART9_TX DMAMUX_REQ_LPUART1_TX
 
 #endif /* !__ASSEMBLER__ */
diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h
index 320a3852f1..2ec0ff28fc 100644
--- a/chip/stm32/registers.h
+++ b/chip/stm32/registers.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -46,74 +46,71 @@
 #include "common.h"
 #include "compile_time_macros.h"
 
-
 #ifndef __ASSEMBLER__
 
 /* Register definitions */
 
 /* --- USART --- */
-#define STM32_USART_BASE(n)           CONCAT3(STM32_USART, n, _BASE)
+#define STM32_USART_BASE(n) CONCAT3(STM32_USART, n, _BASE)
 #define STM32_USART_REG(base, offset) REG32((base) + (offset))
 
-#define STM32_IRQ_USART(n)         CONCAT2(STM32_IRQ_USART, n)
+#define STM32_IRQ_USART(n) CONCAT2(STM32_IRQ_USART, n)
 
 /* --- TIMERS --- */
-#define STM32_TIM_BASE(n)          CONCAT3(STM32_TIM, n, _BASE)
-
-#define STM32_TIM_REG(n, offset) \
-		REG16(STM32_TIM_BASE(n) + (offset))
-#define STM32_TIM_REG32(n, offset) \
-		REG32(STM32_TIM_BASE(n) + (offset))
-
-#define STM32_TIM_CR1(n)           STM32_TIM_REG(n, 0x00)
-#define STM32_TIM_CR1_CEN		BIT(0)
-#define STM32_TIM_CR2(n)           STM32_TIM_REG(n, 0x04)
-#define STM32_TIM_SMCR(n)          STM32_TIM_REG(n, 0x08)
-#define STM32_TIM_DIER(n)          STM32_TIM_REG(n, 0x0C)
-#define STM32_TIM_SR(n)            STM32_TIM_REG(n, 0x10)
-#define STM32_TIM_EGR(n)           STM32_TIM_REG(n, 0x14)
-#define STM32_TIM_EGR_UG		BIT(0)
-#define STM32_TIM_CCMR1(n)         STM32_TIM_REG(n, 0x18)
-#define STM32_TIM_CCMR1_OC1PE		BIT(2)
+#define STM32_TIM_BASE(n) CONCAT3(STM32_TIM, n, _BASE)
+
+#define STM32_TIM_REG(n, offset) REG16(STM32_TIM_BASE(n) + (offset))
+#define STM32_TIM_REG32(n, offset) REG32(STM32_TIM_BASE(n) + (offset))
+
+#define STM32_TIM_CR1(n) STM32_TIM_REG(n, 0x00)
+#define STM32_TIM_CR1_CEN BIT(0)
+#define STM32_TIM_CR2(n) STM32_TIM_REG(n, 0x04)
+#define STM32_TIM_SMCR(n) STM32_TIM_REG(n, 0x08)
+#define STM32_TIM_DIER(n) STM32_TIM_REG(n, 0x0C)
+#define STM32_TIM_SR(n) STM32_TIM_REG(n, 0x10)
+#define STM32_TIM_EGR(n) STM32_TIM_REG(n, 0x14)
+#define STM32_TIM_EGR_UG BIT(0)
+#define STM32_TIM_CCMR1(n) STM32_TIM_REG(n, 0x18)
+#define STM32_TIM_CCMR1_OC1PE BIT(2)
 /* Use in place of TIM_CCMR1_OC1M_0 through 2 from STM documentation. */
-#define STM32_TIM_CCMR1_OC1M(n)    (((n) & 0x7) << 4)
-#define STM32_TIM_CCMR1_OC1M_MASK              STM32_TIM_CCMR1_OC1M(~0)
-#define STM32_TIM_CCMR1_OC1M_FROZEN            STM32_TIM_CCMR1_OC1M(0x0)
-#define STM32_TIM_CCMR1_OC1M_ACTIVE_ON_MATCH   STM32_TIM_CCMR1_OC1M(0x1)
+#define STM32_TIM_CCMR1_OC1M(n) (((n)&0x7) << 4)
+#define STM32_TIM_CCMR1_OC1M_MASK STM32_TIM_CCMR1_OC1M(~0)
+#define STM32_TIM_CCMR1_OC1M_FROZEN STM32_TIM_CCMR1_OC1M(0x0)
+#define STM32_TIM_CCMR1_OC1M_ACTIVE_ON_MATCH STM32_TIM_CCMR1_OC1M(0x1)
 #define STM32_TIM_CCMR1_OC1M_INACTIVE_ON_MATCH STM32_TIM_CCMR1_OC1M(0x2)
-#define STM32_TIM_CCMR1_OC1M_TOGGLE            STM32_TIM_CCMR1_OC1M(0x3)
-#define STM32_TIM_CCMR1_OC1M_FORCE_INACTIVE    STM32_TIM_CCMR1_OC1M(0x4)
-#define STM32_TIM_CCMR1_OC1M_FORCE_ACTIVE      STM32_TIM_CCMR1_OC1M(0x5)
-#define STM32_TIM_CCMR1_OC1M_PWM_MODE_1        STM32_TIM_CCMR1_OC1M(0x6)
-#define STM32_TIM_CCMR1_OC1M_PWM_MODE_2        STM32_TIM_CCMR1_OC1M(0x7)
-#define STM32_TIM_CCMR2(n)         STM32_TIM_REG(n, 0x1C)
-#define STM32_TIM_CCER(n)          STM32_TIM_REG(n, 0x20)
-#define STM32_TIM_CCER_CC1E		BIT(0)
-#define STM32_TIM_CCER_CC1P		BIT(1)
-#define STM32_TIM_CCER_CC1NE		BIT(2)
-#define STM32_TIM_CCER_CC1NP		BIT(3)
-#define STM32_TIM_CNT(n)           STM32_TIM_REG(n, 0x24)
-#define STM32_TIM_PSC(n)           STM32_TIM_REG(n, 0x28)
-#define STM32_TIM_ARR(n)           STM32_TIM_REG(n, 0x2C)
-#define STM32_TIM_RCR(n)           STM32_TIM_REG(n, 0x30)
-#define STM32_TIM_CCR1(n)          STM32_TIM_REG(n, 0x34)
-#define STM32_TIM_CCR2(n)          STM32_TIM_REG(n, 0x38)
-#define STM32_TIM_CCR3(n)          STM32_TIM_REG(n, 0x3C)
-#define STM32_TIM_CCR4(n)          STM32_TIM_REG(n, 0x40)
-#define STM32_TIM_BDTR(n)          STM32_TIM_REG(n, 0x44)
-#define STM32_TIM_BDTR_MOE		BIT(15)
-#define STM32_TIM_DCR(n)           STM32_TIM_REG(n, 0x48)
-#define STM32_TIM_DMAR(n)          STM32_TIM_REG(n, 0x4C)
-#define STM32_TIM_OR(n)            STM32_TIM_REG(n, 0x50)
-
-#define STM32_TIM_CCRx(n, x)       STM32_TIM_REG(n, 0x34 + ((x) - 1) * 4)
-
-#define STM32_TIM32_CNT(n)         STM32_TIM_REG32(n, 0x24)
-#define STM32_TIM32_ARR(n)         STM32_TIM_REG32(n, 0x2C)
-#define STM32_TIM32_CCR1(n)        STM32_TIM_REG32(n, 0x34)
-#define STM32_TIM32_CCR2(n)        STM32_TIM_REG32(n, 0x38)
-#define STM32_TIM32_CCR3(n)        STM32_TIM_REG32(n, 0x3C)
-#define STM32_TIM32_CCR4(n)        STM32_TIM_REG32(n, 0x40)
+#define STM32_TIM_CCMR1_OC1M_TOGGLE STM32_TIM_CCMR1_OC1M(0x3)
+#define STM32_TIM_CCMR1_OC1M_FORCE_INACTIVE STM32_TIM_CCMR1_OC1M(0x4)
+#define STM32_TIM_CCMR1_OC1M_FORCE_ACTIVE STM32_TIM_CCMR1_OC1M(0x5)
+#define STM32_TIM_CCMR1_OC1M_PWM_MODE_1 STM32_TIM_CCMR1_OC1M(0x6)
+#define STM32_TIM_CCMR1_OC1M_PWM_MODE_2 STM32_TIM_CCMR1_OC1M(0x7)
+#define STM32_TIM_CCMR2(n) STM32_TIM_REG(n, 0x1C)
+#define STM32_TIM_CCER(n) STM32_TIM_REG(n, 0x20)
+#define STM32_TIM_CCER_CC1E BIT(0)
+#define STM32_TIM_CCER_CC1P BIT(1)
+#define STM32_TIM_CCER_CC1NE BIT(2)
+#define STM32_TIM_CCER_CC1NP BIT(3)
+#define STM32_TIM_CNT(n) STM32_TIM_REG(n, 0x24)
+#define STM32_TIM_PSC(n) STM32_TIM_REG(n, 0x28)
+#define STM32_TIM_ARR(n) STM32_TIM_REG(n, 0x2C)
+#define STM32_TIM_RCR(n) STM32_TIM_REG(n, 0x30)
+#define STM32_TIM_CCR1(n) STM32_TIM_REG(n, 0x34)
+#define STM32_TIM_CCR2(n) STM32_TIM_REG(n, 0x38)
+#define STM32_TIM_CCR3(n) STM32_TIM_REG(n, 0x3C)
+#define STM32_TIM_CCR4(n) STM32_TIM_REG(n, 0x40)
+#define STM32_TIM_BDTR(n) STM32_TIM_REG(n, 0x44)
+#define STM32_TIM_BDTR_MOE BIT(15)
+#define STM32_TIM_DCR(n) STM32_TIM_REG(n, 0x48)
+#define STM32_TIM_DMAR(n) STM32_TIM_REG(n, 0x4C)
+#define STM32_TIM_OR(n) STM32_TIM_REG(n, 0x50)
+
+#define STM32_TIM_CCRx(n, x) STM32_TIM_REG(n, 0x34 + ((x)-1) * 4)
+
+#define STM32_TIM32_CNT(n) STM32_TIM_REG32(n, 0x24)
+#define STM32_TIM32_ARR(n) STM32_TIM_REG32(n, 0x2C)
+#define STM32_TIM32_CCR1(n) STM32_TIM_REG32(n, 0x34)
+#define STM32_TIM32_CCR2(n) STM32_TIM_REG32(n, 0x38)
+#define STM32_TIM32_CCR3(n) STM32_TIM_REG32(n, 0x3C)
+#define STM32_TIM32_CCR4(n) STM32_TIM_REG32(n, 0x40)
 /* Timer registers as struct */
 struct timer_ctlr {
 	unsigned cr1;
@@ -145,327 +142,325 @@ typedef volatile struct timer_ctlr timer_ctlr_t;
 #define IRQ_TIM(n) CONCAT2(STM32_IRQ_TIM, n)
 
 /* --- Low power timers --- */
-#define STM32_LPTIM_BASE(n)          CONCAT3(STM32_LPTIM, n, _BASE)
-
-#define STM32_LPTIM_REG(n, offset)   REG32(STM32_LPTIM_BASE(n) + (offset))
-
-#define STM32_LPTIM_ISR(n)           STM32_LPTIM_REG(n, 0x00)
-#define STM32_LPTIM_ICR(n)           STM32_LPTIM_REG(n, 0x04)
-#define STM32_LPTIM_IER(n)           STM32_LPTIM_REG(n, 0x08)
-#define STM32_LPTIM_INT_DOWN		BIT(6)
-#define STM32_LPTIM_INT_UP		BIT(5)
-#define STM32_LPTIM_INT_ARROK		BIT(4)
-#define STM32_LPTIM_INT_CMPOK		BIT(3)
-#define STM32_LPTIM_INT_EXTTRIG		BIT(2)
-#define STM32_LPTIM_INT_ARRM		BIT(1)
-#define STM32_LPTIM_INT_CMPM		BIT(0)
-#define STM32_LPTIM_CFGR(n)          STM32_LPTIM_REG(n, 0x0C)
-#define STM32_LPTIM_CR(n)            STM32_LPTIM_REG(n, 0x10)
-#define STM32_LPTIM_CR_RSTARE		BIT(4)
-#define STM32_LPTIM_CR_COUNTRST		BIT(3)
-#define STM32_LPTIM_CR_CNTSTRT		BIT(2)
-#define STM32_LPTIM_CR_SNGSTRT		BIT(1)
-#define STM32_LPTIM_CR_ENABLE		BIT(0)
-#define STM32_LPTIM_CMP(n)           STM32_LPTIM_REG(n, 0x14)
-#define STM32_LPTIM_ARR(n)           STM32_LPTIM_REG(n, 0x18)
-#define STM32_LPTIM_CNT(n)           STM32_LPTIM_REG(n, 0x1C)
-#define STM32_LPTIM_CFGR2(n)         STM32_LPTIM_REG(n, 0x24)
+#define STM32_LPTIM_BASE(n) CONCAT3(STM32_LPTIM, n, _BASE)
+
+#define STM32_LPTIM_REG(n, offset) REG32(STM32_LPTIM_BASE(n) + (offset))
+
+#define STM32_LPTIM_ISR(n) STM32_LPTIM_REG(n, 0x00)
+#define STM32_LPTIM_ICR(n) STM32_LPTIM_REG(n, 0x04)
+#define STM32_LPTIM_IER(n) STM32_LPTIM_REG(n, 0x08)
+#define STM32_LPTIM_INT_DOWN BIT(6)
+#define STM32_LPTIM_INT_UP BIT(5)
+#define STM32_LPTIM_INT_ARROK BIT(4)
+#define STM32_LPTIM_INT_CMPOK BIT(3)
+#define STM32_LPTIM_INT_EXTTRIG BIT(2)
+#define STM32_LPTIM_INT_ARRM BIT(1)
+#define STM32_LPTIM_INT_CMPM BIT(0)
+#define STM32_LPTIM_CFGR(n) STM32_LPTIM_REG(n, 0x0C)
+#define STM32_LPTIM_CR(n) STM32_LPTIM_REG(n, 0x10)
+#define STM32_LPTIM_CR_RSTARE BIT(4)
+#define STM32_LPTIM_CR_COUNTRST BIT(3)
+#define STM32_LPTIM_CR_CNTSTRT BIT(2)
+#define STM32_LPTIM_CR_SNGSTRT BIT(1)
+#define STM32_LPTIM_CR_ENABLE BIT(0)
+#define STM32_LPTIM_CMP(n) STM32_LPTIM_REG(n, 0x14)
+#define STM32_LPTIM_ARR(n) STM32_LPTIM_REG(n, 0x18)
+#define STM32_LPTIM_CNT(n) STM32_LPTIM_REG(n, 0x1C)
+#define STM32_LPTIM_CFGR2(n) STM32_LPTIM_REG(n, 0x24)
 
 /* --- GPIO --- */
 
-#define GPIO_A                       STM32_GPIOA_BASE
-#define GPIO_B                       STM32_GPIOB_BASE
-#define GPIO_C                       STM32_GPIOC_BASE
-#define GPIO_D                       STM32_GPIOD_BASE
-#define GPIO_E                       STM32_GPIOE_BASE
-#define GPIO_F                       STM32_GPIOF_BASE
-#define GPIO_G                       STM32_GPIOG_BASE
-#define GPIO_H                       STM32_GPIOH_BASE
-#define GPIO_I                       STM32_GPIOI_BASE
-#define GPIO_J                       STM32_GPIOJ_BASE
-#define GPIO_K                       STM32_GPIOK_BASE
+#define GPIO_A STM32_GPIOA_BASE
+#define GPIO_B STM32_GPIOB_BASE
+#define GPIO_C STM32_GPIOC_BASE
+#define GPIO_D STM32_GPIOD_BASE
+#define GPIO_E STM32_GPIOE_BASE
+#define GPIO_F STM32_GPIOF_BASE
+#define GPIO_G STM32_GPIOG_BASE
+#define GPIO_H STM32_GPIOH_BASE
+#define GPIO_I STM32_GPIOI_BASE
+#define GPIO_J STM32_GPIOJ_BASE
+#define GPIO_K STM32_GPIOK_BASE
 
 #define UNIMPLEMENTED_GPIO_BANK GPIO_A
 
-
 /* --- I2C --- */
-#define STM32_I2C1_PORT             0
-#define STM32_I2C2_PORT             1
-#define STM32_I2C3_PORT             2
-#define STM32_FMPI2C4_PORT          3
+#define STM32_I2C1_PORT 0
+#define STM32_I2C2_PORT 1
+#define STM32_I2C3_PORT 2
+#define STM32_FMPI2C4_PORT 3
 
 #define stm32_i2c_reg(port, offset) \
-	((uint16_t *)((STM32_I2C1_BASE + ((port) * 0x400)) + (offset)))
+	((uint16_t *)((STM32_I2C1_BASE + ((port)*0x400)) + (offset)))
 /* --- Power / Reset / Clocks --- */
-#define STM32_PWR_CR                REG32(STM32_PWR_BASE + 0x00)
-#define STM32_PWR_CR_LPSDSR		(1 << 0)
-#define STM32_PWR_CR_FLPS		(1 << 9)
-#define STM32_PWR_CR_SVOS5		(1 << 14)
-#define STM32_PWR_CR_SVOS4		(2 << 14)
-#define STM32_PWR_CR_SVOS3		(3 << 14)
-#define STM32_PWR_CR_SVOS_MASK		(3 << 14)
+#define STM32_PWR_CR REG32(STM32_PWR_BASE + 0x00)
+#define STM32_PWR_CR_LPSDSR (1 << 0)
+#define STM32_PWR_CR_FLPS (1 << 9)
+#define STM32_PWR_CR_SVOS5 (1 << 14)
+#define STM32_PWR_CR_SVOS4 (2 << 14)
+#define STM32_PWR_CR_SVOS3 (3 << 14)
+#define STM32_PWR_CR_SVOS_MASK (3 << 14)
 
 /* RTC domain control register */
-#define STM32_RCC_BDCR_BDRST		BIT(16)
-#define STM32_RCC_BDCR_RTCEN		BIT(15)
-#define STM32_RCC_BDCR_LSERDY		BIT(1)
-#define STM32_RCC_BDCR_LSEON		BIT(0)
-#define  BDCR_RTCSEL_MASK		((0x3) << 8)
-#define  BDCR_RTCSEL(source)		(((source) << 8) & BDCR_RTCSEL_MASK)
-#define  BDCR_SRC_LSE			0x1
-#define  BDCR_SRC_LSI			0x2
-#define  BDCR_SRC_HSE			0x3
+#define STM32_RCC_BDCR_BDRST BIT(16)
+#define STM32_RCC_BDCR_RTCEN BIT(15)
+#define STM32_RCC_BDCR_LSERDY BIT(1)
+#define STM32_RCC_BDCR_LSEON BIT(0)
+#define BDCR_RTCSEL_MASK ((0x3) << 8)
+#define BDCR_RTCSEL(source) (((source) << 8) & BDCR_RTCSEL_MASK)
+#define BDCR_SRC_LSE 0x1
+#define BDCR_SRC_LSI 0x2
+#define BDCR_SRC_HSE 0x3
 /* Peripheral bits for RCC_APB/AHB and DBGMCU regs */
-#define STM32_RCC_PB1_TIM2		BIT(0)
-#define STM32_RCC_PB1_TIM3		BIT(1)
-#define STM32_RCC_PB1_TIM4		BIT(2)
-#define STM32_RCC_PB1_TIM5		BIT(3)
-#define STM32_RCC_PB1_TIM6		BIT(4)
-#define STM32_RCC_PB1_TIM7		BIT(5)
-#define STM32_RCC_PB1_TIM12             BIT(6) /* STM32H7 */
-#define STM32_RCC_PB1_TIM13             BIT(7) /* STM32H7 */
-#define STM32_RCC_PB1_TIM14             BIT(8) /* STM32H7 */
-#define STM32_RCC_PB1_RTC		BIT(10) /* DBGMCU only */
-#define STM32_RCC_PB1_WWDG		BIT(11)
-#define STM32_RCC_PB1_IWDG		BIT(12) /* DBGMCU only */
-#define STM32_RCC_PB1_SPI2		BIT(14)
-#define STM32_RCC_PB1_SPI3		BIT(15)
-#define STM32_RCC_PB1_USART2		BIT(17)
-#define STM32_RCC_PB1_USART3		BIT(18)
-#define STM32_RCC_PB1_USART4		BIT(19)
-#define STM32_RCC_PB1_USART5		BIT(20)
-#define STM32_RCC_PB1_PWREN		BIT(28)
-#define STM32_RCC_PB2_SPI1		BIT(12)
+#define STM32_RCC_PB1_TIM2 BIT(0)
+#define STM32_RCC_PB1_TIM3 BIT(1)
+#define STM32_RCC_PB1_TIM4 BIT(2)
+#define STM32_RCC_PB1_TIM5 BIT(3)
+#define STM32_RCC_PB1_TIM6 BIT(4)
+#define STM32_RCC_PB1_TIM7 BIT(5)
+#define STM32_RCC_PB1_TIM12 BIT(6) /* STM32H7 */
+#define STM32_RCC_PB1_TIM13 BIT(7) /* STM32H7 */
+#define STM32_RCC_PB1_TIM14 BIT(8) /* STM32H7 */
+#define STM32_RCC_PB1_RTC BIT(10) /* DBGMCU only */
+#define STM32_RCC_PB1_WWDG BIT(11)
+#define STM32_RCC_PB1_IWDG BIT(12) /* DBGMCU only */
+#define STM32_RCC_PB1_SPI2 BIT(14)
+#define STM32_RCC_PB1_SPI3 BIT(15)
+#define STM32_RCC_PB1_USART2 BIT(17)
+#define STM32_RCC_PB1_USART3 BIT(18)
+#define STM32_RCC_PB1_USART4 BIT(19)
+#define STM32_RCC_PB1_USART5 BIT(20)
+#define STM32_RCC_PB1_PWREN BIT(28)
+#define STM32_RCC_PB2_SPI1 BIT(12)
 /* Reset causes definitions */
 
 /* --- Watchdogs --- */
 
-#define STM32_WWDG_CR               REG32(STM32_WWDG_BASE + 0x00)
-#define STM32_WWDG_CFR              REG32(STM32_WWDG_BASE + 0x04)
-#define STM32_WWDG_SR               REG32(STM32_WWDG_BASE + 0x08)
-
-#define STM32_WWDG_TB_8             (3 << 7)
-#define STM32_WWDG_EWI              BIT(9)
-
-#define STM32_IWDG_KR               REG32(STM32_IWDG_BASE + 0x00)
-#define STM32_IWDG_KR_UNLOCK		0x5555
-#define STM32_IWDG_KR_RELOAD		0xaaaa
-#define STM32_IWDG_KR_START		0xcccc
-#define STM32_IWDG_PR               REG32(STM32_IWDG_BASE + 0x04)
-#define STM32_IWDG_RLR              REG32(STM32_IWDG_BASE + 0x08)
-#define STM32_IWDG_RLR_MAX		0x0fff
-#define STM32_IWDG_SR               REG32(STM32_IWDG_BASE + 0x0C)
-#define STM32_IWDG_SR_WVU		BIT(2)
-#define STM32_IWDG_SR_RVU		BIT(1)
-#define STM32_IWDG_SR_PVU		BIT(0)
-#define STM32_IWDG_WINR             REG32(STM32_IWDG_BASE + 0x10)
+#define STM32_WWDG_CR REG32(STM32_WWDG_BASE + 0x00)
+#define STM32_WWDG_CFR REG32(STM32_WWDG_BASE + 0x04)
+#define STM32_WWDG_SR REG32(STM32_WWDG_BASE + 0x08)
+
+#define STM32_WWDG_TB_8 (3 << 7)
+#define STM32_WWDG_EWI BIT(9)
+
+#define STM32_IWDG_KR REG32(STM32_IWDG_BASE + 0x00)
+#define STM32_IWDG_KR_UNLOCK 0x5555
+#define STM32_IWDG_KR_RELOAD 0xaaaa
+#define STM32_IWDG_KR_START 0xcccc
+#define STM32_IWDG_PR REG32(STM32_IWDG_BASE + 0x04)
+#define STM32_IWDG_RLR REG32(STM32_IWDG_BASE + 0x08)
+#define STM32_IWDG_RLR_MAX 0x0fff
+#define STM32_IWDG_SR REG32(STM32_IWDG_BASE + 0x0C)
+#define STM32_IWDG_SR_WVU BIT(2)
+#define STM32_IWDG_SR_RVU BIT(1)
+#define STM32_IWDG_SR_PVU BIT(0)
+#define STM32_IWDG_WINR REG32(STM32_IWDG_BASE + 0x10)
 
 /* --- Real-Time Clock --- */
 /* --- Debug --- */
-#define STM32_DBGMCU_IDCODE         REG32(STM32_DBGMCU_BASE + 0x00)
-#define STM32_DBGMCU_CR             REG32(STM32_DBGMCU_BASE + 0x04)
+#define STM32_DBGMCU_IDCODE REG32(STM32_DBGMCU_BASE + 0x00)
+#define STM32_DBGMCU_CR REG32(STM32_DBGMCU_BASE + 0x04)
 /* --- Routing interface --- */
 /* STM32L1xx only */
-#define STM32_RI_ICR                REG32(STM32_COMP_BASE + 0x04)
-#define STM32_RI_ASCR1              REG32(STM32_COMP_BASE + 0x08)
-#define STM32_RI_ASCR2              REG32(STM32_COMP_BASE + 0x0C)
-#define STM32_RI_HYSCR1             REG32(STM32_COMP_BASE + 0x10)
-#define STM32_RI_HYSCR2             REG32(STM32_COMP_BASE + 0x14)
-#define STM32_RI_HYSCR3             REG32(STM32_COMP_BASE + 0x18)
-#define STM32_RI_AMSR1              REG32(STM32_COMP_BASE + 0x1C)
-#define STM32_RI_CMR1               REG32(STM32_COMP_BASE + 0x20)
-#define STM32_RI_CICR1              REG32(STM32_COMP_BASE + 0x24)
-#define STM32_RI_AMSR2              REG32(STM32_COMP_BASE + 0x28)
-#define STM32_RI_CMR2               REG32(STM32_COMP_BASE + 0x30)
-#define STM32_RI_CICR2              REG32(STM32_COMP_BASE + 0x34)
-#define STM32_RI_AMSR3              REG32(STM32_COMP_BASE + 0x38)
-#define STM32_RI_CMR3               REG32(STM32_COMP_BASE + 0x3C)
-#define STM32_RI_CICR3              REG32(STM32_COMP_BASE + 0x40)
-#define STM32_RI_AMSR4              REG32(STM32_COMP_BASE + 0x44)
-#define STM32_RI_CMR4               REG32(STM32_COMP_BASE + 0x48)
-#define STM32_RI_CICR4              REG32(STM32_COMP_BASE + 0x4C)
-#define STM32_RI_AMSR5              REG32(STM32_COMP_BASE + 0x50)
-#define STM32_RI_CMR5               REG32(STM32_COMP_BASE + 0x54)
-#define STM32_RI_CICR5              REG32(STM32_COMP_BASE + 0x58)
+#define STM32_RI_ICR REG32(STM32_COMP_BASE + 0x04)
+#define STM32_RI_ASCR1 REG32(STM32_COMP_BASE + 0x08)
+#define STM32_RI_ASCR2 REG32(STM32_COMP_BASE + 0x0C)
+#define STM32_RI_HYSCR1 REG32(STM32_COMP_BASE + 0x10)
+#define STM32_RI_HYSCR2 REG32(STM32_COMP_BASE + 0x14)
+#define STM32_RI_HYSCR3 REG32(STM32_COMP_BASE + 0x18)
+#define STM32_RI_AMSR1 REG32(STM32_COMP_BASE + 0x1C)
+#define STM32_RI_CMR1 REG32(STM32_COMP_BASE + 0x20)
+#define STM32_RI_CICR1 REG32(STM32_COMP_BASE + 0x24)
+#define STM32_RI_AMSR2 REG32(STM32_COMP_BASE + 0x28)
+#define STM32_RI_CMR2 REG32(STM32_COMP_BASE + 0x30)
+#define STM32_RI_CICR2 REG32(STM32_COMP_BASE + 0x34)
+#define STM32_RI_AMSR3 REG32(STM32_COMP_BASE + 0x38)
+#define STM32_RI_CMR3 REG32(STM32_COMP_BASE + 0x3C)
+#define STM32_RI_CICR3 REG32(STM32_COMP_BASE + 0x40)
+#define STM32_RI_AMSR4 REG32(STM32_COMP_BASE + 0x44)
+#define STM32_RI_CMR4 REG32(STM32_COMP_BASE + 0x48)
+#define STM32_RI_CICR4 REG32(STM32_COMP_BASE + 0x4C)
+#define STM32_RI_AMSR5 REG32(STM32_COMP_BASE + 0x50)
+#define STM32_RI_CMR5 REG32(STM32_COMP_BASE + 0x54)
+#define STM32_RI_CICR5 REG32(STM32_COMP_BASE + 0x58)
 
 /* --- DAC --- */
-#define STM32_DAC_CR               REG32(STM32_DAC_BASE + 0x00)
-#define STM32_DAC_SWTRIGR          REG32(STM32_DAC_BASE + 0x04)
-#define STM32_DAC_DHR12R1          REG32(STM32_DAC_BASE + 0x08)
-#define STM32_DAC_DHR12L1          REG32(STM32_DAC_BASE + 0x0C)
-#define STM32_DAC_DHR8R1           REG32(STM32_DAC_BASE + 0x10)
-#define STM32_DAC_DHR12R2          REG32(STM32_DAC_BASE + 0x14)
-#define STM32_DAC_DHR12L2          REG32(STM32_DAC_BASE + 0x18)
-#define STM32_DAC_DHR8R2           REG32(STM32_DAC_BASE + 0x1C)
-#define STM32_DAC_DHR12RD          REG32(STM32_DAC_BASE + 0x20)
-#define STM32_DAC_DHR12LD          REG32(STM32_DAC_BASE + 0x24)
-#define STM32_DAC_DHR8RD           REG32(STM32_DAC_BASE + 0x28)
-#define STM32_DAC_DOR1             REG32(STM32_DAC_BASE + 0x2C)
-#define STM32_DAC_DOR2             REG32(STM32_DAC_BASE + 0x30)
-#define STM32_DAC_SR               REG32(STM32_DAC_BASE + 0x34)
-
-#define STM32_DAC_CR_DMAEN2        BIT(28)
-#define STM32_DAC_CR_TSEL2_SWTRG   (7 << 19)
-#define STM32_DAC_CR_TSEL2_TMR4    (5 << 19)
-#define STM32_DAC_CR_TSEL2_TMR2    (4 << 19)
-#define STM32_DAC_CR_TSEL2_TMR9    (3 << 19)
-#define STM32_DAC_CR_TSEL2_TMR7    (2 << 19)
-#define STM32_DAC_CR_TSEL2_TMR6    (0 << 19)
-#define STM32_DAC_CR_TSEL2_MASK    (7 << 19)
-#define STM32_DAC_CR_TEN2          BIT(18)
-#define STM32_DAC_CR_BOFF2         BIT(17)
-#define STM32_DAC_CR_EN2           BIT(16)
-#define STM32_DAC_CR_DMAEN1        BIT(12)
-#define STM32_DAC_CR_TSEL1_SWTRG   (7 << 3)
-#define STM32_DAC_CR_TSEL1_TMR4    (5 << 3)
-#define STM32_DAC_CR_TSEL1_TMR2    (4 << 3)
-#define STM32_DAC_CR_TSEL1_TMR9    (3 << 3)
-#define STM32_DAC_CR_TSEL1_TMR7    (2 << 3)
-#define STM32_DAC_CR_TSEL1_TMR6    (0 << 3)
-#define STM32_DAC_CR_TSEL1_MASK    (7 << 3)
-#define STM32_DAC_CR_TEN1          BIT(2)
-#define STM32_DAC_CR_BOFF1         BIT(1)
-#define STM32_DAC_CR_EN1           BIT(0)
+#define STM32_DAC_CR REG32(STM32_DAC_BASE + 0x00)
+#define STM32_DAC_SWTRIGR REG32(STM32_DAC_BASE + 0x04)
+#define STM32_DAC_DHR12R1 REG32(STM32_DAC_BASE + 0x08)
+#define STM32_DAC_DHR12L1 REG32(STM32_DAC_BASE + 0x0C)
+#define STM32_DAC_DHR8R1 REG32(STM32_DAC_BASE + 0x10)
+#define STM32_DAC_DHR12R2 REG32(STM32_DAC_BASE + 0x14)
+#define STM32_DAC_DHR12L2 REG32(STM32_DAC_BASE + 0x18)
+#define STM32_DAC_DHR8R2 REG32(STM32_DAC_BASE + 0x1C)
+#define STM32_DAC_DHR12RD REG32(STM32_DAC_BASE + 0x20)
+#define STM32_DAC_DHR12LD REG32(STM32_DAC_BASE + 0x24)
+#define STM32_DAC_DHR8RD REG32(STM32_DAC_BASE + 0x28)
+#define STM32_DAC_DOR1 REG32(STM32_DAC_BASE + 0x2C)
+#define STM32_DAC_DOR2 REG32(STM32_DAC_BASE + 0x30)
+#define STM32_DAC_SR REG32(STM32_DAC_BASE + 0x34)
+
+#define STM32_DAC_CR_DMAEN2 BIT(28)
+#define STM32_DAC_CR_TSEL2_SWTRG (7 << 19)
+#define STM32_DAC_CR_TSEL2_TMR4 (5 << 19)
+#define STM32_DAC_CR_TSEL2_TMR2 (4 << 19)
+#define STM32_DAC_CR_TSEL2_TMR9 (3 << 19)
+#define STM32_DAC_CR_TSEL2_TMR7 (2 << 19)
+#define STM32_DAC_CR_TSEL2_TMR6 (0 << 19)
+#define STM32_DAC_CR_TSEL2_MASK (7 << 19)
+#define STM32_DAC_CR_TEN2 BIT(18)
+#define STM32_DAC_CR_BOFF2 BIT(17)
+#define STM32_DAC_CR_EN2 BIT(16)
+#define STM32_DAC_CR_DMAEN1 BIT(12)
+#define STM32_DAC_CR_TSEL1_SWTRG (7 << 3)
+#define STM32_DAC_CR_TSEL1_TMR4 (5 << 3)
+#define STM32_DAC_CR_TSEL1_TMR2 (4 << 3)
+#define STM32_DAC_CR_TSEL1_TMR9 (3 << 3)
+#define STM32_DAC_CR_TSEL1_TMR7 (2 << 3)
+#define STM32_DAC_CR_TSEL1_TMR6 (0 << 3)
+#define STM32_DAC_CR_TSEL1_MASK (7 << 3)
+#define STM32_DAC_CR_TEN1 BIT(2)
+#define STM32_DAC_CR_BOFF1 BIT(1)
+#define STM32_DAC_CR_EN1 BIT(0)
 /* --- CRC --- */
-#define STM32_CRC_DR                REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR32              REG32(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR16              REG16(STM32_CRC_BASE + 0x0)
-#define STM32_CRC_DR8               REG8(STM32_CRC_BASE + 0x0)
-
-#define STM32_CRC_IDR               REG32(STM32_CRC_BASE + 0x4)
-#define STM32_CRC_CR                REG32(STM32_CRC_BASE + 0x8)
-#define STM32_CRC_INIT              REG32(STM32_CRC_BASE + 0x10)
-#define STM32_CRC_POL               REG32(STM32_CRC_BASE + 0x14)
-
-#define STM32_CRC_CR_RESET          BIT(0)
-#define STM32_CRC_CR_POLYSIZE_32    (0 << 3)
-#define STM32_CRC_CR_POLYSIZE_16    (1 << 3)
-#define STM32_CRC_CR_POLYSIZE_8     (2 << 3)
-#define STM32_CRC_CR_POLYSIZE_7     (3 << 3)
-#define STM32_CRC_CR_REV_IN_BYTE    (1 << 5)
-#define STM32_CRC_CR_REV_IN_HWORD   (2 << 5)
-#define STM32_CRC_CR_REV_IN_WORD    (3 << 5)
-#define STM32_CRC_CR_REV_OUT        BIT(7)
+#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0)
+#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0)
+
+#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4)
+#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8)
+#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10)
+#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14)
+
+#define STM32_CRC_CR_RESET BIT(0)
+#define STM32_CRC_CR_POLYSIZE_32 (0 << 3)
+#define STM32_CRC_CR_POLYSIZE_16 (1 << 3)
+#define STM32_CRC_CR_POLYSIZE_8 (2 << 3)
+#define STM32_CRC_CR_POLYSIZE_7 (3 << 3)
+#define STM32_CRC_CR_REV_IN_BYTE (1 << 5)
+#define STM32_CRC_CR_REV_IN_HWORD (2 << 5)
+#define STM32_CRC_CR_REV_IN_WORD (3 << 5)
+#define STM32_CRC_CR_REV_OUT BIT(7)
 
 /* --- PMSE --- */
-#define STM32_PMSE_ARCR             REG32(STM32_PMSE_BASE + 0x0)
-#define STM32_PMSE_ACCR             REG32(STM32_PMSE_BASE + 0x4)
-#define STM32_PMSE_CR               REG32(STM32_PMSE_BASE + 0x8)
-#define STM32_PMSE_CRTDR            REG32(STM32_PMSE_BASE + 0x14)
-#define STM32_PMSE_IER              REG32(STM32_PMSE_BASE + 0x18)
-#define STM32_PMSE_SR               REG32(STM32_PMSE_BASE + 0x1c)
-#define STM32_PMSE_IFCR             REG32(STM32_PMSE_BASE + 0x20)
-#define STM32_PMSE_PxPMR(x)         REG32(STM32_PMSE_BASE + 0x2c + (x) * 4)
-#define STM32_PMSE_PAPMR            REG32(STM32_PMSE_BASE + 0x2c)
-#define STM32_PMSE_PBPMR            REG32(STM32_PMSE_BASE + 0x30)
-#define STM32_PMSE_PCPMR            REG32(STM32_PMSE_BASE + 0x34)
-#define STM32_PMSE_PDPMR            REG32(STM32_PMSE_BASE + 0x38)
-#define STM32_PMSE_PEPMR            REG32(STM32_PMSE_BASE + 0x3c)
-#define STM32_PMSE_PFPMR            REG32(STM32_PMSE_BASE + 0x40)
-#define STM32_PMSE_PGPMR            REG32(STM32_PMSE_BASE + 0x44)
-#define STM32_PMSE_PHPMR            REG32(STM32_PMSE_BASE + 0x48)
-#define STM32_PMSE_PIPMR            REG32(STM32_PMSE_BASE + 0x4c)
-#define STM32_PMSE_MRCR             REG32(STM32_PMSE_BASE + 0x100)
-#define STM32_PMSE_MCCR             REG32(STM32_PMSE_BASE + 0x104)
+#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0)
+#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4)
+#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8)
+#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14)
+#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18)
+#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c)
+#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20)
+#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x)*4)
+#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c)
+#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30)
+#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34)
+#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38)
+#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c)
+#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40)
+#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44)
+#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48)
+#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c)
+#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100)
+#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104)
 
 /* --- USB --- */
-#define STM32_USB_EP(n)            REG16(STM32_USB_FS_BASE + (n) * 4)
-
-#define STM32_USB_CNTR             REG16(STM32_USB_FS_BASE + 0x40)
-
-#define STM32_USB_CNTR_FRES	    BIT(0)
-#define STM32_USB_CNTR_PDWN	    BIT(1)
-#define STM32_USB_CNTR_LP_MODE	    BIT(2)
-#define STM32_USB_CNTR_FSUSP	    BIT(3)
-#define STM32_USB_CNTR_RESUME	    BIT(4)
-#define STM32_USB_CNTR_L1RESUME	    BIT(5)
-#define STM32_USB_CNTR_L1REQM	    BIT(7)
-#define STM32_USB_CNTR_ESOFM	    BIT(8)
-#define STM32_USB_CNTR_SOFM	    BIT(9)
-#define STM32_USB_CNTR_RESETM	    BIT(10)
-#define STM32_USB_CNTR_SUSPM	    BIT(11)
-#define STM32_USB_CNTR_WKUPM	    BIT(12)
-#define STM32_USB_CNTR_ERRM	    BIT(13)
-#define STM32_USB_CNTR_PMAOVRM	    BIT(14)
-#define STM32_USB_CNTR_CTRM	    BIT(15)
-
-#define STM32_USB_ISTR             REG16(STM32_USB_FS_BASE + 0x44)
-
-#define STM32_USB_ISTR_EP_ID_MASK   (0x000f)
-#define STM32_USB_ISTR_DIR	    BIT(4)
-#define STM32_USB_ISTR_L1REQ	    BIT(7)
-#define STM32_USB_ISTR_ESOF	    BIT(8)
-#define STM32_USB_ISTR_SOF	    BIT(9)
-#define STM32_USB_ISTR_RESET	    BIT(10)
-#define STM32_USB_ISTR_SUSP	    BIT(11)
-#define STM32_USB_ISTR_WKUP	    BIT(12)
-#define STM32_USB_ISTR_ERR	    BIT(13)
-#define STM32_USB_ISTR_PMAOVR	    BIT(14)
-#define STM32_USB_ISTR_CTR	    BIT(15)
-
-#define STM32_USB_FNR              REG16(STM32_USB_FS_BASE + 0x48)
+#define STM32_USB_EP(n) REG16(STM32_USB_FS_BASE + (n)*4)
+
+#define STM32_USB_CNTR REG16(STM32_USB_FS_BASE + 0x40)
+
+#define STM32_USB_CNTR_FRES BIT(0)
+#define STM32_USB_CNTR_PDWN BIT(1)
+#define STM32_USB_CNTR_LP_MODE BIT(2)
+#define STM32_USB_CNTR_FSUSP BIT(3)
+#define STM32_USB_CNTR_RESUME BIT(4)
+#define STM32_USB_CNTR_L1RESUME BIT(5)
+#define STM32_USB_CNTR_L1REQM BIT(7)
+#define STM32_USB_CNTR_ESOFM BIT(8)
+#define STM32_USB_CNTR_SOFM BIT(9)
+#define STM32_USB_CNTR_RESETM BIT(10)
+#define STM32_USB_CNTR_SUSPM BIT(11)
+#define STM32_USB_CNTR_WKUPM BIT(12)
+#define STM32_USB_CNTR_ERRM BIT(13)
+#define STM32_USB_CNTR_PMAOVRM BIT(14)
+#define STM32_USB_CNTR_CTRM BIT(15)
+
+#define STM32_USB_ISTR REG16(STM32_USB_FS_BASE + 0x44)
+
+#define STM32_USB_ISTR_EP_ID_MASK (0x000f)
+#define STM32_USB_ISTR_DIR BIT(4)
+#define STM32_USB_ISTR_L1REQ BIT(7)
+#define STM32_USB_ISTR_ESOF BIT(8)
+#define STM32_USB_ISTR_SOF BIT(9)
+#define STM32_USB_ISTR_RESET BIT(10)
+#define STM32_USB_ISTR_SUSP BIT(11)
+#define STM32_USB_ISTR_WKUP BIT(12)
+#define STM32_USB_ISTR_ERR BIT(13)
+#define STM32_USB_ISTR_PMAOVR BIT(14)
+#define STM32_USB_ISTR_CTR BIT(15)
+
+#define STM32_USB_FNR REG16(STM32_USB_FS_BASE + 0x48)
 
 #define STM32_USB_FNR_RXDP_RXDM_SHIFT (14)
-#define STM32_USB_FNR_RXDP_RXDM_MASK  (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT)
-
-#define STM32_USB_DADDR            REG16(STM32_USB_FS_BASE + 0x4C)
-#define STM32_USB_BTABLE           REG16(STM32_USB_FS_BASE + 0x50)
-#define STM32_USB_LPMCSR           REG16(STM32_USB_FS_BASE + 0x54)
-#define STM32_USB_BCDR             REG16(STM32_USB_FS_BASE + 0x58)
-
-#define STM32_USB_BCDR_BCDEN	    BIT(0)
-#define STM32_USB_BCDR_DCDEN	    BIT(1)
-#define STM32_USB_BCDR_PDEN	    BIT(2)
-#define STM32_USB_BCDR_SDEN	    BIT(3)
-#define STM32_USB_BCDR_DCDET	    BIT(4)
-#define STM32_USB_BCDR_PDET	    BIT(5)
-#define STM32_USB_BCDR_SDET	    BIT(6)
-#define STM32_USB_BCDR_PS2DET	    BIT(7)
-
-#define EP_MASK     0x0F0F
-#define EP_TX_DTOG  0x0040
-#define EP_TX_MASK  0x0030
+#define STM32_USB_FNR_RXDP_RXDM_MASK (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT)
+
+#define STM32_USB_DADDR REG16(STM32_USB_FS_BASE + 0x4C)
+#define STM32_USB_BTABLE REG16(STM32_USB_FS_BASE + 0x50)
+#define STM32_USB_LPMCSR REG16(STM32_USB_FS_BASE + 0x54)
+#define STM32_USB_BCDR REG16(STM32_USB_FS_BASE + 0x58)
+
+#define STM32_USB_BCDR_BCDEN BIT(0)
+#define STM32_USB_BCDR_DCDEN BIT(1)
+#define STM32_USB_BCDR_PDEN BIT(2)
+#define STM32_USB_BCDR_SDEN BIT(3)
+#define STM32_USB_BCDR_DCDET BIT(4)
+#define STM32_USB_BCDR_PDET BIT(5)
+#define STM32_USB_BCDR_SDET BIT(6)
+#define STM32_USB_BCDR_PS2DET BIT(7)
+
+#define EP_MASK 0x0F0F
+#define EP_TX_DTOG 0x0040
+#define EP_TX_MASK 0x0030
 #define EP_TX_VALID 0x0030
-#define EP_TX_NAK   0x0020
+#define EP_TX_NAK 0x0020
 #define EP_TX_STALL 0x0010
 #define EP_TX_DISAB 0x0000
-#define EP_RX_DTOG  0x4000
-#define EP_RX_MASK  0x3000
+#define EP_RX_DTOG 0x4000
+#define EP_RX_MASK 0x3000
 #define EP_RX_VALID 0x3000
-#define EP_RX_NAK   0x2000
+#define EP_RX_NAK 0x2000
 #define EP_RX_STALL 0x1000
 #define EP_RX_DISAB 0x0000
 
 #define EP_STATUS_OUT 0x0100
 
-#define EP_TX_RX_MASK  (EP_TX_MASK | EP_RX_MASK)
+#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK)
 #define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID)
-#define EP_TX_RX_NAK   (EP_TX_NAK | EP_RX_NAK)
+#define EP_TX_RX_NAK (EP_TX_NAK | EP_RX_NAK)
 
 #define STM32_TOGGLE_EP(n, mask, val, flags) \
-	STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \
-			^ (val)) | (flags))
+	STM32_USB_EP(n) =                    \
+		(((STM32_USB_EP(n) & (EP_MASK | (mask))) ^ (val)) | (flags))
 
 /* --- TRNG --- */
-#define STM32_RNG_CR                REG32(STM32_RNG_BASE + 0x0)
-#define STM32_RNG_CR_RNGEN		BIT(2)
-#define STM32_RNG_CR_IE			BIT(3)
-#define STM32_RNG_CR_CED		BIT(5)
-#define STM32_RNG_SR                REG32(STM32_RNG_BASE + 0x4)
-#define STM32_RNG_SR_DRDY		BIT(0)
-#define STM32_RNG_DR                REG32(STM32_RNG_BASE + 0x8)
+#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0)
+#define STM32_RNG_CR_RNGEN BIT(2)
+#define STM32_RNG_CR_IE BIT(3)
+#define STM32_RNG_CR_CED BIT(5)
+#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4)
+#define STM32_RNG_SR_DRDY BIT(0)
+#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8)
 
 /* --- AXI interconnect --- */
 
 /* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */
-#define STM32_AXI_TARG_FN_MOD(x)    REG32(STM32_GPV_BASE + 0x1108 + \
-					  0x1000 * (x))
-#define  WRITE_ISS_OVERRIDE         BIT(1)
-#define  READ_ISS_OVERRIDE          BIT(0)
+#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + 0x1000 * (x))
+#define WRITE_ISS_OVERRIDE BIT(1)
+#define READ_ISS_OVERRIDE BIT(0)
 
 /* --- MISC --- */
-#define STM32_UNIQUE_ID_ADDRESS     REG32_ADDR(STM32_UNIQUE_ID_BASE)
-#define STM32_UNIQUE_ID_LENGTH      (3 * 4)
+#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE)
+#define STM32_UNIQUE_ID_LENGTH (3 * 4)
 
 #endif /* !__ASSEMBLER__ */
 
diff --git a/chip/stm32/spi.c b/chip/stm32/spi.c
index 268b7880e6..e6be946113 100644
--- a/chip/stm32/spi.c
+++ b/chip/stm32/spi.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2013 The Chromium OS Authors. All rights reserved.
+ * Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,6 +8,7 @@
  * This uses DMA to handle transmission and reception.
  */
 
+#include "builtin/assert.h"
 #include "chipset.h"
 #include "clock.h"
 #include "console.h"
@@ -24,8 +25,8 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_SPI, outstr)
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SPI, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SPI, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SPI, format, ##args)
 
 /* SPI FIFO registers */
 #ifdef CHIP_FAMILY_STM32H7
@@ -41,7 +42,7 @@ static const struct dma_option dma_tx_option = {
 	STM32_DMAC_SPI1_TX, (void *)&SPI_TXDR,
 	STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
 #ifdef CHIP_FAMILY_STM32F4
-	| STM32_DMA_CCR_CHANNEL(STM32_SPI1_TX_REQ_CH)
+		| STM32_DMA_CCR_CHANNEL(STM32_SPI1_TX_REQ_CH)
 #endif
 };
 
@@ -49,7 +50,7 @@ static const struct dma_option dma_rx_option = {
 	STM32_DMAC_SPI1_RX, (void *)&SPI_RXDR,
 	STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
 #ifdef CHIP_FAMILY_STM32F4
-	| STM32_DMA_CCR_CHANNEL(STM32_SPI1_RX_REQ_CH)
+		| STM32_DMA_CCR_CHANNEL(STM32_SPI1_RX_REQ_CH)
 #endif
 };
 
@@ -71,8 +72,8 @@ static const struct dma_option dma_rx_option = {
  * the AP will have a known and identifiable value.
  */
 #define SPI_PROTO2_OFFSET (EC_PROTO2_RESPONSE_HEADER_BYTES + 2)
-#define SPI_PROTO2_OVERHEAD (SPI_PROTO2_OFFSET +		\
-			     EC_PROTO2_RESPONSE_TRAILER_BYTES + 1)
+#define SPI_PROTO2_OVERHEAD \
+	(SPI_PROTO2_OFFSET + EC_PROTO2_RESPONSE_TRAILER_BYTES + 1)
 #endif /* defined(CONFIG_SPI_PROTOCOL_V2) */
 /*
  * Max data size for a version 3 request/response packet.  This is big enough
@@ -92,10 +93,8 @@ static const struct dma_option dma_rx_option = {
  * 32-bit aligned.
  */
 static const uint8_t out_preamble[4] = {
-	EC_SPI_PROCESSING,
-	EC_SPI_PROCESSING,
-	EC_SPI_PROCESSING,
-	EC_SPI_FRAME_START,  /* This is the byte which matters */
+	EC_SPI_PROCESSING, EC_SPI_PROCESSING, EC_SPI_PROCESSING,
+	EC_SPI_FRAME_START, /* This is the byte which matters */
 };
 
 /*
@@ -117,7 +116,7 @@ static const uint8_t out_preamble[4] = {
  * message, including protocol overhead, and must be 32-bit aligned.
  */
 static uint8_t out_msg[SPI_MAX_RESPONSE_SIZE + sizeof(out_preamble) +
-	EC_SPI_PAST_END_LENGTH] __aligned(4) __uncached;
+		       EC_SPI_PAST_END_LENGTH] __aligned(4) __uncached;
 static uint8_t in_msg[SPI_MAX_REQUEST_SIZE] __aligned(4) __uncached;
 static uint8_t enabled;
 #ifdef CONFIG_SPI_PROTOCOL_V2
@@ -172,8 +171,7 @@ enum spi_state {
  * @param nss		GPIO signal for NSS control line
  * @return 0 if bytes received, -1 if we hit a timeout or NSS went high
  */
-static int wait_for_bytes(dma_chan_t *rxdma, int needed,
-			  enum gpio_signal nss)
+static int wait_for_bytes(dma_chan_t *rxdma, int needed, enum gpio_signal nss)
 {
 	timestamp_t deadline;
 
@@ -230,8 +228,8 @@ static int wait_for_bytes(dma_chan_t *rxdma, int needed,
  *			SPI_PROTO2_OFFSET bytes into out_msg
  * @param msg_len	Number of message bytes to send
  */
-static void reply(dma_chan_t *txdma,
-		  enum ec_status status, char *msg_ptr, int msg_len)
+static void reply(dma_chan_t *txdma, enum ec_status status, char *msg_ptr,
+		  int msg_len)
 {
 	char *msg = out_msg;
 	int need_copy = msg_ptr != msg + SPI_PROTO2_OFFSET;
@@ -438,8 +436,10 @@ static void spi_send_response_packet(struct host_packet *pkt)
 
 	/* Transmit the reply */
 	txdma = dma_get_channel(STM32_DMAC_SPI1_TX);
-	dma_prepare_tx(&dma_tx_option, sizeof(out_preamble) + pkt->response_size
-		+ EC_SPI_PAST_END_LENGTH, out_msg);
+	dma_prepare_tx(&dma_tx_option,
+		       sizeof(out_preamble) + pkt->response_size +
+			       EC_SPI_PAST_END_LENGTH,
+		       out_msg);
 	dma_go(txdma);
 #ifdef CHIP_FAMILY_STM32H7
 	/* clear any previous underrun */
@@ -544,8 +544,9 @@ void spi_event(enum gpio_signal signal)
 		memcpy(out_msg, out_preamble, sizeof(out_preamble));
 		spi_packet.response = out_msg + sizeof(out_preamble);
 		/* Reserve space for the preamble and trailing past-end byte */
-		spi_packet.response_max = sizeof(out_msg)
-			- sizeof(out_preamble) - EC_SPI_PAST_END_LENGTH;
+		spi_packet.response_max = sizeof(out_msg) -
+					  sizeof(out_preamble) -
+					  EC_SPI_PAST_END_LENGTH;
 		spi_packet.response_size = 0;
 
 		spi_packet.driver_result = EC_RES_SUCCESS;
@@ -608,7 +609,7 @@ void spi_event(enum gpio_signal signal)
 #endif /* defined(CONFIG_SPI_PROTOCOL_V2) */
 	}
 
- spi_event_error:
+spi_event_error:
 	/* Error, timeout, or protocol we can't handle.  Ignore data. */
 	tx_status(EC_SPI_RX_BAD_DATA);
 	state = SPI_STATE_RX_BAD;
@@ -701,14 +702,13 @@ static void spi_init(void)
 #ifdef CHIP_FAMILY_STM32H7
 	spi->cfg2 = 0;
 	spi->cfg1 = STM32_SPI_CFG1_DATASIZE(8) | STM32_SPI_CFG1_FTHLV(4) |
-			STM32_SPI_CFG1_CRCSIZE(8) |
-			STM32_SPI_CFG1_TXDMAEN | STM32_SPI_CFG1_RXDMAEN |
-			STM32_SPI_CFG1_UDRCFG_CONST |
-			STM32_SPI_CFG1_UDRDET_BEGIN_FRM;
+		    STM32_SPI_CFG1_CRCSIZE(8) | STM32_SPI_CFG1_TXDMAEN |
+		    STM32_SPI_CFG1_RXDMAEN | STM32_SPI_CFG1_UDRCFG_CONST |
+		    STM32_SPI_CFG1_UDRDET_BEGIN_FRM;
 	spi->cr1 = 0;
 #else /* !CHIP_FAMILY_STM32H7 */
 	spi->cr2 = STM32_SPI_CR2_RXDMAEN | STM32_SPI_CR2_TXDMAEN |
-		STM32_SPI_CR2_FRXTH | STM32_SPI_CR2_DATASIZE(8);
+		   STM32_SPI_CR2_FRXTH | STM32_SPI_CR2_DATASIZE(8);
 
 	/* Enable the SPI peripheral */
 	spi->cr1 |= STM32_SPI_CR1_SPE;
diff --git a/chip/stm32/spi_controller-stm32h7.c b/chip/stm32/spi_controller-stm32h7.c
index 7792204a85..705bf4e607 100644
--- a/chip/stm32/spi_controller-stm32h7.c
+++ b/chip/stm32/spi_controller-stm32h7.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -50,44 +50,28 @@ static struct mutex spi_mutex[ARRAY_SIZE(SPI_REGS)];
 
 static const struct dma_option dma_tx_option[] = {
 #ifdef CONFIG_STM32_SPI1_CONTROLLER
-	{
-		STM32_DMAC_SPI1_TX, (void *)&STM32_SPI1_REGS->txdr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-	},
+	{ STM32_DMAC_SPI1_TX, (void *)&STM32_SPI1_REGS->txdr,
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT },
 #endif
-	{
-		STM32_DMAC_SPI2_TX, (void *)&STM32_SPI2_REGS->txdr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-	},
-	{
-		STM32_DMAC_SPI3_TX, (void *)&STM32_SPI3_REGS->txdr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-	},
-	{
-		STM32_DMAC_SPI4_TX, (void *)&STM32_SPI4_REGS->txdr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-	},
+	{ STM32_DMAC_SPI2_TX, (void *)&STM32_SPI2_REGS->txdr,
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT },
+	{ STM32_DMAC_SPI3_TX, (void *)&STM32_SPI3_REGS->txdr,
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT },
+	{ STM32_DMAC_SPI4_TX, (void *)&STM32_SPI4_REGS->txdr,
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT },
 };
 
 static const struct dma_option dma_rx_option[] = {
 #ifdef CONFIG_STM32_SPI1_CONTROLLER
-	{
-		STM32_DMAC_SPI1_RX, (void *)&STM32_SPI1_REGS->rxdr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-	},
+	{ STM32_DMAC_SPI1_RX, (void *)&STM32_SPI1_REGS->rxdr,
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT },
 #endif
-	{
-		STM32_DMAC_SPI2_RX, (void *)&STM32_SPI2_REGS->rxdr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-	},
-	{
-		STM32_DMAC_SPI3_RX, (void *)&STM32_SPI3_REGS->rxdr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-	},
-	{
-		STM32_DMAC_SPI4_RX, (void *)&STM32_SPI4_REGS->rxdr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-	},
+	{ STM32_DMAC_SPI2_RX, (void *)&STM32_SPI2_REGS->rxdr,
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT },
+	{ STM32_DMAC_SPI3_RX, (void *)&STM32_SPI3_REGS->rxdr,
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT },
+	{ STM32_DMAC_SPI4_RX, (void *)&STM32_SPI4_REGS->rxdr,
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT },
 };
 
 static uint8_t spi_enabled[ARRAY_SIZE(SPI_REGS)];
@@ -252,8 +236,8 @@ static int spi_dma_wait(int port)
 }
 
 int spi_transaction_async(const struct spi_device_t *spi_device,
-			  const uint8_t *txdata, int txlen,
-			  uint8_t *rxdata, int rxlen)
+			  const uint8_t *txdata, int txlen, uint8_t *rxdata,
+			  int rxlen)
 {
 	int rv = EC_SUCCESS;
 	int port = spi_device->port;
@@ -314,8 +298,8 @@ int spi_transaction_wait(const struct spi_device_t *spi_device)
 }
 
 int spi_transaction(const struct spi_device_t *spi_device,
-		    const uint8_t *txdata, int txlen,
-		    uint8_t *rxdata, int rxlen)
+		    const uint8_t *txdata, int txlen, uint8_t *rxdata,
+		    int rxlen)
 {
 	int rv;
 	int port = spi_device->port;
diff --git a/chip/stm32/spi_controller.c b/chip/stm32/spi_controller.c
index e34afde7e1..70e0eb3cd7 100644
--- a/chip/stm32/spi_controller.c
+++ b/chip/stm32/spi_controller.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
+ * Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -17,12 +17,11 @@
 #include "timer.h"
 #include "util.h"
 
-#if defined(CHIP_VARIANT_STM32F373)  || \
-	defined(CHIP_FAMILY_STM32L4) || \
-	defined(CHIP_VARIANT_STM32F76X)
+#if defined(CHIP_VARIANT_STM32F373) || defined(CHIP_FAMILY_STM32L4) || \
+	defined(CHIP_FAMILY_STM32L5) || defined(CHIP_VARIANT_STM32F76X)
 #define HAS_SPI3
 #else
-#undef  HAS_SPI3
+#undef HAS_SPI3
 #endif
 
 /* The second (and third if available) SPI port are used as controller */
@@ -36,14 +35,26 @@ static stm32_spi_regs_t *SPI_REGS[] = {
 #endif
 };
 
-#ifdef CHIP_FAMILY_STM32L4
 /* DMA request mapping on channels */
-static uint8_t dma_req[ARRAY_SIZE(SPI_REGS)] = {
+struct dma_req_t {
+	uint8_t tx_req;
+	uint8_t rx_req;
+};
+#ifdef CHIP_FAMILY_STM32L4
+static struct dma_req_t dma_req[ARRAY_SIZE(SPI_REGS)] = {
 #ifdef CONFIG_STM32_SPI1_CONTROLLER
-	/* SPI1 */ 1,
+	/* SPI1 */ { 1, 1 },
 #endif
-	/* SPI2 */ 1,
-	/* SPI3 */ 3,
+	/* SPI2 */ { 1, 1 },
+	/* SPI3 */ { 3, 3 },
+};
+#elif defined(CHIP_FAMILY_STM32L5)
+static struct dma_req_t dma_req[ARRAY_SIZE(SPI_REGS)] = {
+#ifdef CONFIG_STM32_SPI1_CONTROLLER
+	/* SPI1 */ { DMAMUX_REQ_SPI1_TX, DMAMUX_REQ_SPI1_RX },
+#endif
+	/* SPI2 */ { DMAMUX_REQ_SPI2_TX, DMAMUX_REQ_SPI2_RX },
+	/* SPI3 */ { DMAMUX_REQ_SPI3_TX, DMAMUX_REQ_SPI3_RX },
 };
 #endif
 
@@ -53,52 +64,40 @@ static struct mutex spi_mutex[ARRAY_SIZE(SPI_REGS)];
 
 /* Default DMA channel options */
 #ifdef CHIP_FAMILY_STM32F4
-#define F4_CHANNEL(ch)	STM32_DMA_CCR_CHANNEL(ch)
+#define F4_CHANNEL(ch) STM32_DMA_CCR_CHANNEL(ch)
 #else
-#define F4_CHANNEL(ch)	0
+#define F4_CHANNEL(ch) 0
 #endif
 
 static const struct dma_option dma_tx_option[] = {
 #ifdef CONFIG_STM32_SPI1_CONTROLLER
-	{
-		STM32_DMAC_SPI1_TX, (void *)&STM32_SPI1_REGS->dr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-		| F4_CHANNEL(STM32_SPI1_TX_REQ_CH)
-	},
+	{ STM32_DMAC_SPI1_TX, (void *)&STM32_SPI1_REGS->dr,
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
+		  F4_CHANNEL(STM32_SPI1_TX_REQ_CH) },
 #endif
-	{
-		STM32_DMAC_SPI2_TX, (void *)&STM32_SPI2_REGS->dr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-		| F4_CHANNEL(STM32_SPI2_TX_REQ_CH)
-	},
+	{ STM32_DMAC_SPI2_TX, (void *)&STM32_SPI2_REGS->dr,
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
+		  F4_CHANNEL(STM32_SPI2_TX_REQ_CH) },
 #ifdef HAS_SPI3
-	{
-		STM32_DMAC_SPI3_TX, (void *)&STM32_SPI3_REGS->dr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-		| F4_CHANNEL(STM32_SPI3_TX_REQ_CH)
-	},
+	{ STM32_DMAC_SPI3_TX, (void *)&STM32_SPI3_REGS->dr,
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
+		  F4_CHANNEL(STM32_SPI3_TX_REQ_CH) },
 #endif
 };
 
 static const struct dma_option dma_rx_option[] = {
 #ifdef CONFIG_STM32_SPI1_CONTROLLER
-	{
-		STM32_DMAC_SPI1_RX, (void *)&STM32_SPI1_REGS->dr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-		| F4_CHANNEL(STM32_SPI1_RX_REQ_CH)
-	},
+	{ STM32_DMAC_SPI1_RX, (void *)&STM32_SPI1_REGS->dr,
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
+		  F4_CHANNEL(STM32_SPI1_RX_REQ_CH) },
 #endif
-	{
-		STM32_DMAC_SPI2_RX, (void *)&STM32_SPI2_REGS->dr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-		| F4_CHANNEL(STM32_SPI2_RX_REQ_CH)
-	},
+	{ STM32_DMAC_SPI2_RX, (void *)&STM32_SPI2_REGS->dr,
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
+		  F4_CHANNEL(STM32_SPI2_RX_REQ_CH) },
 #ifdef HAS_SPI3
-	{
-		STM32_DMAC_SPI3_RX, (void *)&STM32_SPI3_REGS->dr,
-		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
-		| F4_CHANNEL(STM32_SPI3_RX_REQ_CH)
-	},
+	{ STM32_DMAC_SPI3_RX, (void *)&STM32_SPI3_REGS->dr,
+	  STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
+		  F4_CHANNEL(STM32_SPI3_RX_REQ_CH) },
 #endif
 };
 
@@ -121,7 +120,7 @@ static int spi_clear_rx_fifo(stm32_spi_regs_t *spi)
 	uint32_t start = __hw_clock_source_read(), delta;
 
 	while (!spi_rx_done(spi)) {
-		unused = spi->dr;  /* Read one byte from FIFO */
+		unused = spi->dr; /* Read one byte from FIFO */
 		delta = __hw_clock_source_read() - start;
 		if (delta >= SPI_TRANSACTION_TIMEOUT_USEC)
 			return EC_ERROR_TIMEOUT;
@@ -203,9 +202,9 @@ static int spi_controller_initialize(const struct spi_device_t *spi_device)
 	spi->cr1 = STM32_SPI_CR1_MSTR | STM32_SPI_CR1_SSM | STM32_SPI_CR1_SSI |
 		   (spi_device->div << 3);
 
-#ifdef CHIP_FAMILY_STM32L4
-	dma_select_channel(dma_tx_option[port].channel, dma_req[port]);
-	dma_select_channel(dma_rx_option[port].channel, dma_req[port]);
+#if defined(CHIP_FAMILY_STM32L4) || defined(CHIP_FAMILY_STM32L5)
+	dma_select_channel(dma_tx_option[port].channel, dma_req[port].tx_req);
+	dma_select_channel(dma_rx_option[port].channel, dma_req[port].rx_req);
 #endif
 	/*
 	 * Configure 8-bit datasize, set FRXTH, enable DMA,
@@ -219,7 +218,7 @@ static int spi_controller_initialize(const struct spi_device_t *spi_device)
 	 * https://www.st.com/resource/en/reference_manual/dm00031936.pdf#page=803
 	 */
 	spi->cr2 = STM32_SPI_CR2_TXDMAEN | STM32_SPI_CR2_RXDMAEN |
-			STM32_SPI_CR2_FRXTH | STM32_SPI_CR2_DATASIZE(8);
+		   STM32_SPI_CR2_FRXTH | STM32_SPI_CR2_DATASIZE(8);
 
 #ifdef CONFIG_SPI_HALFDUPLEX
 	spi->cr1 |= STM32_SPI_CR1_BIDIMODE | STM32_SPI_CR1_BIDIOE;
@@ -274,8 +273,8 @@ int spi_enable(const struct spi_device_t *spi_device, int enable)
 		return spi_controller_shutdown(spi_device);
 }
 
-static int spi_dma_start(int port, const uint8_t *txdata,
-			 uint8_t *rxdata, int len)
+static int spi_dma_start(int port, const uint8_t *txdata, uint8_t *rxdata,
+			 int len)
 {
 	dma_chan_t *txdma;
 
@@ -337,8 +336,8 @@ static int spi_dma_wait(int port)
 static uint8_t spi_chip_select_already_asserted[ARRAY_SIZE(SPI_REGS)];
 
 int spi_transaction_async(const struct spi_device_t *spi_device,
-			  const uint8_t *txdata, int txlen,
-			  uint8_t *rxdata, int rxlen)
+			  const uint8_t *txdata, int txlen, uint8_t *rxdata,
+			  int rxlen)
 {
 	int rv = EC_SUCCESS;
 	int port = spi_device->port;
@@ -372,13 +371,14 @@ int spi_transaction_async(const struct spi_device_t *spi_device,
 
 	spi_clear_rx_fifo(spi);
 
-	rv = spi_dma_start(port, txdata, buf, txlen);
-	if (rv != EC_SUCCESS)
-		goto err_free;
-
+	if (txlen) {
+		rv = spi_dma_start(port, txdata, buf, txlen);
+		if (rv != EC_SUCCESS)
+			goto err_free;
 #ifdef CONFIG_SPI_HALFDUPLEX
-	spi->cr1 |= STM32_SPI_CR1_BIDIOE;
+		spi->cr1 |= STM32_SPI_CR1_BIDIOE;
 #endif
+	}
 
 	if (full_readback)
 		return EC_SUCCESS;
@@ -410,8 +410,8 @@ int spi_transaction_flush(const struct spi_device_t *spi_device)
 {
 	int rv = spi_dma_wait(spi_device->port);
 
-	if (!IS_ENABLED(CONFIG_USB_SPI)
-	    || !spi_chip_select_already_asserted[spi_device->port]) {
+	if (!IS_ENABLED(CONFIG_USB_SPI) ||
+	    !spi_chip_select_already_asserted[spi_device->port]) {
 		/* Drive SS high */
 		gpio_set_level(spi_device->gpio_cs, 1);
 	}
@@ -425,8 +425,8 @@ int spi_transaction_wait(const struct spi_device_t *spi_device)
 }
 
 int spi_transaction(const struct spi_device_t *spi_device,
-		    const uint8_t *txdata, int txlen,
-		    uint8_t *rxdata, int rxlen)
+		    const uint8_t *txdata, int txlen, uint8_t *rxdata,
+		    int rxlen)
 {
 	int rv;
 	int port = spi_device->port;
diff --git a/chip/stm32/stm32-dma.h b/chip/stm32/stm32-dma.h
index 06233b9c93..3bda9ec41d 100644
--- a/chip/stm32/stm32-dma.h
+++ b/chip/stm32/stm32-dma.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/stm32/system.c b/chip/stm32/system.c
index d7388055a9..dc53022c8b 100644
--- a/chip/stm32/system.c
+++ b/chip/stm32/system.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -28,10 +28,10 @@
 #define BDCR_SRC BDCR_SRC_LSI
 #define BDCR_RDY 0
 #endif
-#define BDCR_ENABLE_VALUE (STM32_RCC_BDCR_RTCEN | BDCR_RTCSEL(BDCR_SRC) | \
-			BDCR_RDY)
-#define BDCR_ENABLE_MASK (BDCR_ENABLE_VALUE | BDCR_RTCSEL_MASK | \
-			STM32_RCC_BDCR_BDRST)
+#define BDCR_ENABLE_VALUE \
+	(STM32_RCC_BDCR_RTCEN | BDCR_RTCSEL(BDCR_SRC) | BDCR_RDY)
+#define BDCR_ENABLE_MASK \
+	(BDCR_ENABLE_VALUE | BDCR_RTCSEL_MASK | STM32_RCC_BDCR_BDRST)
 
 #ifdef CONFIG_USB_PD_DUAL_ROLE
 BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT <= 3);
@@ -149,62 +149,61 @@ void chip_pre_init(void)
 	uint32_t apb2fz_reg = 0;
 
 #if defined(CHIP_FAMILY_STM32F0)
-	apb1fz_reg =
-		STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM6 |
-		STM32_RCC_PB1_TIM7 | STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG;
+	apb1fz_reg = STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 |
+		     STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_TIM7 |
+		     STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG;
 	apb2fz_reg = STM32_RCC_PB2_TIM15 | STM32_RCC_PB2_TIM16 |
-		STM32_RCC_PB2_TIM17 | STM32_RCC_PB2_TIM1;
+		     STM32_RCC_PB2_TIM17 | STM32_RCC_PB2_TIM1;
 
 	/* enable clock to debug module before writing */
 	STM32_RCC_APB2ENR |= STM32_RCC_DBGMCUEN;
 #elif defined(CHIP_FAMILY_STM32F3)
-	apb1fz_reg =
-		STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM4 |
-		STM32_RCC_PB1_TIM5 | STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_TIM7 |
-		STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG;
-	apb2fz_reg =
-		STM32_RCC_PB2_TIM15 | STM32_RCC_PB2_TIM16 | STM32_RCC_PB2_TIM17;
+	apb1fz_reg = STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 |
+		     STM32_RCC_PB1_TIM4 | STM32_RCC_PB1_TIM5 |
+		     STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_TIM7 |
+		     STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG;
+	apb2fz_reg = STM32_RCC_PB2_TIM15 | STM32_RCC_PB2_TIM16 |
+		     STM32_RCC_PB2_TIM17;
 #elif defined(CHIP_FAMILY_STM32F4)
-	apb1fz_reg =
-		STM32_RCC_PB1_TIM2  | STM32_RCC_PB1_TIM3  | STM32_RCC_PB1_TIM4 |
-		STM32_RCC_PB1_TIM5  | STM32_RCC_PB1_TIM6  | STM32_RCC_PB1_TIM7 |
-		STM32_RCC_PB1_TIM12 | STM32_RCC_PB1_TIM13 | STM32_RCC_PB1_TIM14|
-		STM32_RCC_PB1_RTC   | STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG;
-	apb2fz_reg =
-		STM32_RCC_PB2_TIM1  | STM32_RCC_PB2_TIM8  | STM32_RCC_PB2_TIM9 |
-		STM32_RCC_PB2_TIM10 | STM32_RCC_PB2_TIM11;
+	apb1fz_reg = STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 |
+		     STM32_RCC_PB1_TIM4 | STM32_RCC_PB1_TIM5 |
+		     STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_TIM7 |
+		     STM32_RCC_PB1_TIM12 | STM32_RCC_PB1_TIM13 |
+		     STM32_RCC_PB1_TIM14 | STM32_RCC_PB1_RTC |
+		     STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG;
+	apb2fz_reg = STM32_RCC_PB2_TIM1 | STM32_RCC_PB2_TIM8 |
+		     STM32_RCC_PB2_TIM9 | STM32_RCC_PB2_TIM10 |
+		     STM32_RCC_PB2_TIM11;
 #elif defined(CHIP_FAMILY_STM32L4)
 
-#ifdef	CHIP_VARIANT_STM32L431X
-	apb1fz_reg =
-		STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM7 | STM32_RCC_PB1_TIM6 |
-		STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG;
-	apb2fz_reg =
-		STM32_RCC_PB2_TIM1 | STM32_RCC_PB2_TIM15 | STM32_RCC_PB2_TIM16;
+#ifdef CHIP_VARIANT_STM32L431X
+	apb1fz_reg = STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM7 |
+		     STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_WWDG |
+		     STM32_RCC_PB1_IWDG;
+	apb2fz_reg = STM32_RCC_PB2_TIM1 | STM32_RCC_PB2_TIM15 |
+		     STM32_RCC_PB2_TIM16;
 #else
-	apb1fz_reg =
-		STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM4 |
-		STM32_RCC_PB1_TIM5 | STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_TIM7 |
-		STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG;
+	apb1fz_reg = STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 |
+		     STM32_RCC_PB1_TIM4 | STM32_RCC_PB1_TIM5 |
+		     STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_TIM7 |
+		     STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG;
 	apb2fz_reg = STM32_RCC_PB2_TIM1 | STM32_RCC_PB2_TIM8;
 #endif
 #elif defined(CHIP_FAMILY_STM32L)
-	apb1fz_reg =
-		STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM4 |
-		STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG;
+	apb1fz_reg = STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 |
+		     STM32_RCC_PB1_TIM4 | STM32_RCC_PB1_WWDG |
+		     STM32_RCC_PB1_IWDG;
 	apb2fz_reg = STM32_RCC_PB2_TIM9 | STM32_RCC_PB2_TIM10 |
-		STM32_RCC_PB2_TIM11;
+		     STM32_RCC_PB2_TIM11;
 #elif defined(CHIP_FAMILY_STM32G4)
-	apb1fz_reg =
-		STM32_DBGMCU_APB1FZ_TIM2 | STM32_DBGMCU_APB1FZ_TIM3 |
-		STM32_DBGMCU_APB1FZ_TIM4 | STM32_DBGMCU_APB1FZ_TIM5 |
-		STM32_DBGMCU_APB1FZ_TIM6 | STM32_DBGMCU_APB1FZ_TIM7 |
-		STM32_DBGMCU_APB1FZ_RTC  | STM32_DBGMCU_APB1FZ_WWDG |
-		STM32_DBGMCU_APB1FZ_IWDG;
-	apb2fz_reg =
-		STM32_DBGMCU_APB2FZ_TIM1 | STM32_DBGMCU_APB2FZ_TIM8 |
-		STM32_DBGMCU_APB2FZ_TIM15 | STM32_DBGMCU_APB2FZ_TIM16 |
-		STM32_DBGMCU_APB2FZ_TIM17 | STM32_DBGMCU_APB2FZ_TIM20;
+	apb1fz_reg = STM32_DBGMCU_APB1FZ_TIM2 | STM32_DBGMCU_APB1FZ_TIM3 |
+		     STM32_DBGMCU_APB1FZ_TIM4 | STM32_DBGMCU_APB1FZ_TIM5 |
+		     STM32_DBGMCU_APB1FZ_TIM6 | STM32_DBGMCU_APB1FZ_TIM7 |
+		     STM32_DBGMCU_APB1FZ_RTC | STM32_DBGMCU_APB1FZ_WWDG |
+		     STM32_DBGMCU_APB1FZ_IWDG;
+	apb2fz_reg = STM32_DBGMCU_APB2FZ_TIM1 | STM32_DBGMCU_APB2FZ_TIM8 |
+		     STM32_DBGMCU_APB2FZ_TIM15 | STM32_DBGMCU_APB2FZ_TIM16 |
+		     STM32_DBGMCU_APB2FZ_TIM17 | STM32_DBGMCU_APB2FZ_TIM20;
 #elif defined(CHIP_FAMILY_STM32H7)
 	/* TODO(b/67081508) */
 #endif
@@ -274,7 +273,7 @@ void system_pre_init(void)
 
 	/* enable clock on Power module */
 #ifndef CHIP_FAMILY_STM32H7
-#ifdef	CHIP_FAMILY_STM32L4
+#ifdef CHIP_FAMILY_STM32L4
 	STM32_RCC_APB1ENR1 |= STM32_RCC_PWREN;
 #else
 	STM32_RCC_APB1ENR |= STM32_RCC_PWREN;
@@ -322,10 +321,10 @@ void system_pre_init(void)
 		/* Enable RTC and use LSI as clock source */
 		STM32_RCC_CSR = (STM32_RCC_CSR & ~0x00C30000) | 0x00420000;
 	}
-#elif defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \
-	defined(CHIP_FAMILY_STM32L4) || \
-	defined(CHIP_FAMILY_STM32L5) || defined(CHIP_FAMILY_STM32F4) ||	\
-	defined(CHIP_FAMILY_STM32H7) || defined(CHIP_FAMILY_STM32G4)
+#elif defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) ||   \
+	defined(CHIP_FAMILY_STM32L4) || defined(CHIP_FAMILY_STM32L5) || \
+	defined(CHIP_FAMILY_STM32F4) || defined(CHIP_FAMILY_STM32H7) || \
+	defined(CHIP_FAMILY_STM32G4)
 	if ((STM32_RCC_BDCR & BDCR_ENABLE_MASK) != BDCR_ENABLE_VALUE) {
 		/* The RTC settings are bad, we need to reset it */
 		STM32_RCC_BDCR |= STM32_RCC_BDCR_BDRST;
@@ -438,9 +437,9 @@ void system_reset(int flags)
 			bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_REASON, reason);
 			bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_INFO, info);
 			bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_EXCEPTION,
-			    exception);
+				      exception);
 			bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_FLAGS,
-			    panic_flags);
+				      panic_flags);
 		}
 #endif
 
@@ -633,19 +632,19 @@ int system_is_reboot_warm(void)
 #elif defined(CHIP_FAMILY_STM32L)
 	return ((STM32_RCC_AHBENR & 0x3f) == 0x3f);
 #elif defined(CHIP_FAMILY_STM32L4)
-	return ((STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_GPIOMASK)
-			== STM32_RCC_AHB2ENR_GPIOMASK);
+	return ((STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_GPIOMASK) ==
+		STM32_RCC_AHB2ENR_GPIOMASK);
 #elif defined(CHIP_FAMILY_STM32L5)
-	return ((STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_GPIOMASK)
-			== STM32_RCC_AHB2ENR_GPIOMASK);
+	return ((STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_GPIOMASK) ==
+		STM32_RCC_AHB2ENR_GPIOMASK);
 #elif defined(CHIP_FAMILY_STM32F4)
-	return ((STM32_RCC_AHB1ENR & STM32_RCC_AHB1ENR_GPIOMASK)
-			== gpio_required_clocks());
+	return ((STM32_RCC_AHB1ENR & STM32_RCC_AHB1ENR_GPIOMASK) ==
+		gpio_required_clocks());
 #elif defined(CHIP_FAMILY_STM32G4)
-	return ((STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_GPIOMASK)
-			== gpio_required_clocks());
+	return ((STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_GPIOMASK) ==
+		gpio_required_clocks());
 #elif defined(CHIP_FAMILY_STM32H7)
-	return ((STM32_RCC_AHB4ENR & STM32_RCC_AHB4ENR_GPIOMASK)
-			== STM32_RCC_AHB4ENR_GPIOMASK);
+	return ((STM32_RCC_AHB4ENR & STM32_RCC_AHB4ENR_GPIOMASK) ==
+		STM32_RCC_AHB4ENR_GPIOMASK);
 #endif
 }
diff --git a/chip/stm32/trng.c b/chip/stm32/trng.c
index 48d5335c53..aafc0e89c1 100644
--- a/chip/stm32/trng.c
+++ b/chip/stm32/trng.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,13 +9,14 @@
 #include "console.h"
 #include "host_command.h"
 #include "panic.h"
+#include "printf.h"
 #include "registers.h"
 #include "system.h"
 #include "task.h"
 #include "trng.h"
 #include "util.h"
 
-uint32_t rand(void)
+uint32_t trng_rand(void)
 {
 	int tries = 300;
 	/* Wait for a valid random number */
@@ -28,10 +29,10 @@ uint32_t rand(void)
 	return STM32_RNG_DR;
 }
 
-test_mockable void rand_bytes(void *buffer, size_t len)
+test_mockable void trng_rand_bytes(void *buffer, size_t len)
 {
 	while (len) {
-		uint32_t number = rand();
+		uint32_t number = trng_rand();
 		size_t cnt = 4;
 		/* deal with the lack of alignment guarantee in the API */
 		uintptr_t align = (uintptr_t)buffer & 3;
@@ -47,7 +48,7 @@ test_mockable void rand_bytes(void *buffer, size_t len)
 	}
 }
 
-test_mockable void init_trng(void)
+test_mockable void trng_init(void)
 {
 #ifdef CHIP_FAMILY_STM32L4
 	/* Enable the 48Mhz internal RC oscillator */
@@ -57,8 +58,8 @@ test_mockable void init_trng(void)
 		;
 
 	/* Clock the TRNG using the HSI48 */
-	STM32_RCC_CCIPR = (STM32_RCC_CCIPR & ~STM32_RCC_CCIPR_CLK48SEL_MASK)
-			| (0 << STM32_RCC_CCIPR_CLK48SEL_SHIFT);
+	STM32_RCC_CCIPR = (STM32_RCC_CCIPR & ~STM32_RCC_CCIPR_CLK48SEL_MASK) |
+			  (0 << STM32_RCC_CCIPR_CLK48SEL_SHIFT);
 #elif defined(CHIP_FAMILY_STM32H7)
 	/* Enable the 48Mhz internal RC oscillator */
 	STM32_RCC_CR |= STM32_RCC_CR_HSI48ON;
@@ -68,8 +69,8 @@ test_mockable void init_trng(void)
 
 	/* Clock the TRNG using the HSI48 */
 	STM32_RCC_D2CCIP2R =
-		(STM32_RCC_D2CCIP2R & ~STM32_RCC_D2CCIP2_RNGSEL_MASK)
-			| STM32_RCC_D2CCIP2_RNGSEL_HSI48;
+		(STM32_RCC_D2CCIP2R & ~STM32_RCC_D2CCIP2_RNGSEL_MASK) |
+		STM32_RCC_D2CCIP2_RNGSEL_HSI48;
 #elif defined(CHIP_FAMILY_STM32F4)
 	/*
 	 * The RNG clock is the same as the SDIO/USB OTG clock, already set at
@@ -84,7 +85,7 @@ test_mockable void init_trng(void)
 	STM32_RNG_CR |= STM32_RNG_CR_RNGEN;
 }
 
-test_mockable void exit_trng(void)
+test_mockable void trng_exit(void)
 {
 	STM32_RNG_CR &= ~STM32_RNG_CR_RNGEN;
 	STM32_RCC_AHB2ENR &= ~STM32_RCC_AHB2ENR_RNGEN;
@@ -103,20 +104,23 @@ test_mockable void exit_trng(void)
  * update RO once in production.
  */
 #if defined(SECTION_IS_RW)
-static int command_rand(int argc, char **argv)
+static int command_rand(int argc, const char **argv)
 {
 	uint8_t data[32];
+	char str_buf[hex_str_buf_size(sizeof(data))];
 
-	init_trng();
-	rand_bytes(data, sizeof(data));
-	exit_trng();
+	trng_init();
+	trng_rand_bytes(data, sizeof(data));
+	trng_exit();
 
-	ccprintf("rand %ph\n", HEX_BUF(data, sizeof(data)));
+	snprintf_hex_buffer(str_buf, sizeof(str_buf),
+			    HEX_BUF(data, sizeof(data)));
+	ccprintf("rand %s\n", str_buf);
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(rand, command_rand,
-			NULL, "Output random bytes to console.");
+DECLARE_CONSOLE_COMMAND(rand, command_rand, NULL,
+			"Output random bytes to console.");
 
 static enum ec_status host_command_rand(struct host_cmd_handler_args *args)
 {
@@ -130,9 +134,9 @@ static enum ec_status host_command_rand(struct host_cmd_handler_args *args)
 	if (num_rand_bytes > args->response_max)
 		return EC_RES_OVERFLOW;
 
-	init_trng();
-	rand_bytes(r->rand, num_rand_bytes);
-	exit_trng();
+	trng_init();
+	trng_rand_bytes(r->rand, num_rand_bytes);
+	trng_exit();
 
 	args->response_size = num_rand_bytes;
 
diff --git a/chip/stm32/uart.c b/chip/stm32/uart.c
index 6be0790c63..1bb961a935 100644
--- a/chip/stm32/uart.c
+++ b/chip/stm32/uart.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,7 +18,7 @@
 #include "stm32-dma.h"
 
 /* Console USART index */
-#define UARTN      CONFIG_UART_CONSOLE
+#define UARTN CONFIG_UART_CONSOLE
 #define UARTN_BASE STM32_USART_BASE(CONFIG_UART_CONSOLE)
 
 #ifdef CONFIG_UART_TX_DMA
@@ -33,7 +33,7 @@ static const struct dma_option dma_tx_option = {
 	CONFIG_UART_TX_DMA_CH, (void *)&STM32_USART_TDR(UARTN_BASE),
 	STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
 #ifdef CHIP_FAMILY_STM32F4
-	| STM32_DMA_CCR_CHANNEL(CONFIG_UART_TX_REQ_CH)
+		| STM32_DMA_CCR_CHANNEL(CONFIG_UART_TX_REQ_CH)
 #endif
 };
 
@@ -51,16 +51,16 @@ static const struct dma_option dma_rx_option = {
 	CONFIG_UART_RX_DMA_CH, (void *)&STM32_USART_RDR(UARTN_BASE),
 	STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT |
 #ifdef CHIP_FAMILY_STM32F4
-	STM32_DMA_CCR_CHANNEL(CONFIG_UART_RX_REQ_CH) |
+		STM32_DMA_CCR_CHANNEL(CONFIG_UART_RX_REQ_CH) |
 #endif
-	STM32_DMA_CCR_CIRC
+		STM32_DMA_CCR_CIRC
 };
 
-static int dma_rx_len;   /* Size of receive DMA circular buffer */
+static int dma_rx_len; /* Size of receive DMA circular buffer */
 #endif
 
-static int init_done;    /* Initialization done? */
-static int should_stop;  /* Last TX control action */
+static int init_done; /* Initialization done? */
+static int should_stop; /* Last TX control action */
 
 int uart_init_done(void)
 {
@@ -249,13 +249,13 @@ static void uart_freq_change(void)
 	freq = clock_get_freq();
 #endif
 
-#if (UARTN == 9)	/* LPUART */
+#if (UARTN == 9) /* LPUART */
 	div = DIV_ROUND_NEAREST(freq, CONFIG_UART_BAUD_RATE) * 256;
 #else
 	div = DIV_ROUND_NEAREST(freq, CONFIG_UART_BAUD_RATE);
 #endif
 
-#if defined(CHIP_FAMILY_STM32L) || defined(CHIP_FAMILY_STM32F0) || \
+#if defined(CHIP_FAMILY_STM32L) || defined(CHIP_FAMILY_STM32F0) ||      \
 	defined(CHIP_FAMILY_STM32F3) || defined(CHIP_FAMILY_STM32L4) || \
 	defined(CHIP_FAMILY_STM32F4) || defined(CHIP_FAMILY_STM32G4)
 	if (div / 16 > 0) {
@@ -277,7 +277,6 @@ static void uart_freq_change(void)
 	/* STM32F only supports x16 oversampling */
 	STM32_USART_BRR(UARTN_BASE) = div;
 #endif
-
 }
 DECLARE_HOOK(HOOK_FREQ_CHANGE, uart_freq_change, HOOK_PRIO_DEFAULT);
 
@@ -286,7 +285,7 @@ void uart_init(void)
 	/* Select clock source */
 #if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3)
 #if (UARTN == 1)
-	STM32_RCC_CFGR3 |= 0x0003;   /* USART1 clock source from HSI(8MHz) */
+	STM32_RCC_CFGR3 |= 0x0003; /* USART1 clock source from HSI(8MHz) */
 #elif (UARTN == 2)
 	STM32_RCC_CFGR3 |= 0x030000; /* USART2 clock source from HSI(8MHz) */
 #endif /* UARTN */
@@ -339,8 +338,8 @@ void uart_init(void)
 	/* Configure GPIOs */
 	gpio_config_module(MODULE_UART, 1);
 
-#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) \
-|| defined(CHIP_FAMILY_STM32H7) || defined(CHIP_FAMILY_STM32L4)
+#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \
+	defined(CHIP_FAMILY_STM32H7) || defined(CHIP_FAMILY_STM32L4)
 	/*
 	 * Wake up on start bit detection. WUS can only be written when UE=0,
 	 * so clear UE first.
@@ -352,7 +351,7 @@ void uart_init(void)
 	 * and we don't want to clear an extra flag in the interrupt
 	 */
 	STM32_USART_CR3(UARTN_BASE) |= STM32_USART_CR3_WUS_START_BIT |
-	                               STM32_USART_CR3_OVRDIS;
+				       STM32_USART_CR3_OVRDIS;
 #endif
 
 	/*
@@ -360,11 +359,10 @@ void uart_init(void)
 	 * TX and RX enabled.
 	 */
 #ifdef CHIP_FAMILY_STM32L4
-	STM32_USART_CR1(UARTN_BASE) =
-		STM32_USART_CR1_TE | STM32_USART_CR1_RE;
+	STM32_USART_CR1(UARTN_BASE) = STM32_USART_CR1_TE | STM32_USART_CR1_RE;
 #else
-	STM32_USART_CR1(UARTN_BASE) =
-		STM32_USART_CR1_UE | STM32_USART_CR1_TE | STM32_USART_CR1_RE;
+	STM32_USART_CR1(UARTN_BASE) = STM32_USART_CR1_UE | STM32_USART_CR1_TE |
+				      STM32_USART_CR1_RE;
 #endif
 
 	/* 1 stop bit, no fancy stuff */
diff --git a/chip/stm32/ucpd-stm32gx.c b/chip/stm32/ucpd-stm32gx.c
index d8c41c8f28..3fec860200 100644
--- a/chip/stm32/ucpd-stm32gx.c
+++ b/chip/stm32/ucpd-stm32gx.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,8 +20,8 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 #define USB_VID_STM32 0x0483
 
@@ -33,22 +33,19 @@
  */
 #define UCPD_BUF_LEN 30
 
-#define UCPD_IMR_RX_INT_MASK (STM32_UCPD_IMR_RXNEIE| \
-			      STM32_UCPD_IMR_RXORDDETIE | \
-			      STM32_UCPD_IMR_RXHRSTDETIE |	\
-			      STM32_UCPD_IMR_RXOVRIE |		\
-			      STM32_UCPD_IMR_RXMSGENDIE)
+#define UCPD_IMR_RX_INT_MASK                                   \
+	(STM32_UCPD_IMR_RXNEIE | STM32_UCPD_IMR_RXORDDETIE |   \
+	 STM32_UCPD_IMR_RXHRSTDETIE | STM32_UCPD_IMR_RXOVRIE | \
+	 STM32_UCPD_IMR_RXMSGENDIE)
 
-#define UCPD_IMR_TX_INT_MASK (STM32_UCPD_IMR_TXISIE | \
-			      STM32_UCPD_IMR_TXMSGDISCIE |     \
-			      STM32_UCPD_IMR_TXMSGSENTIE |     \
-			      STM32_UCPD_IMR_TXMSGABTIE |      \
-			      STM32_UCPD_IMR_TXUNDIE)
+#define UCPD_IMR_TX_INT_MASK                                      \
+	(STM32_UCPD_IMR_TXISIE | STM32_UCPD_IMR_TXMSGDISCIE |     \
+	 STM32_UCPD_IMR_TXMSGSENTIE | STM32_UCPD_IMR_TXMSGABTIE | \
+	 STM32_UCPD_IMR_TXUNDIE)
 
-#define UCPD_ICR_TX_INT_MASK (STM32_UCPD_ICR_TXMSGDISCCF | \
-			      STM32_UCPD_ICR_TXMSGSENTCF |     \
-			      STM32_UCPD_ICR_TXMSGABTCF |     \
-			      STM32_UCPD_ICR_TXUNDCF)
+#define UCPD_ICR_TX_INT_MASK                                       \
+	(STM32_UCPD_ICR_TXMSGDISCCF | STM32_UCPD_ICR_TXMSGSENTCF | \
+	 STM32_UCPD_ICR_TXMSGABTCF | STM32_UCPD_ICR_TXUNDCF)
 
 #define UCPD_ANASUB_TO_RP(r) ((r - 1) & 0x3)
 #define UCPD_RP_TO_ANASUB(r) ((r + 1) & 0x3)
@@ -69,16 +66,16 @@ enum ucpd_state {
 };
 
 /* Events for pd_interrupt_handler_task */
-#define UCPD_EVT_GOOD_CRC_REQ   BIT(0)
-#define UCPD_EVT_TCPM_MSG_REQ   BIT(1)
-#define UCPD_EVT_HR_REQ         BIT(2)
-#define UCPD_EVT_TX_MSG_FAIL    BIT(3)
-#define UCPD_EVT_TX_MSG_DISC    BIT(4)
+#define UCPD_EVT_GOOD_CRC_REQ BIT(0)
+#define UCPD_EVT_TCPM_MSG_REQ BIT(1)
+#define UCPD_EVT_HR_REQ BIT(2)
+#define UCPD_EVT_TX_MSG_FAIL BIT(3)
+#define UCPD_EVT_TX_MSG_DISC BIT(4)
 #define UCPD_EVT_TX_MSG_SUCCESS BIT(5)
-#define UCPD_EVT_HR_DONE        BIT(6)
-#define UCPD_EVT_HR_FAIL        BIT(7)
-#define UCPD_EVT_RX_GOOD_CRC    BIT(8)
-#define UCPD_EVT_RX_MSG         BIT(9)
+#define UCPD_EVT_HR_DONE BIT(6)
+#define UCPD_EVT_HR_FAIL BIT(7)
+#define UCPD_EVT_RX_GOOD_CRC BIT(8)
+#define UCPD_EVT_RX_MSG BIT(9)
 
 #define UCPD_T_RECEIVE_US (1 * MSEC)
 
@@ -161,11 +158,7 @@ int ucpd_tx_state_log_idx;
 int ucpd_tx_state_log_freeze;
 
 static char ucpd_names[][12] = {
-	"TX_IDLE",
-	"ACT_TCPM",
-	"ACT_CRC",
-	"HARD_RST",
-	"WAIT_CRC",
+	"TX_IDLE", "ACT_TCPM", "ACT_CRC", "HARD_RST", "WAIT_CRC",
 };
 /* Defines and macros used for ucpd pd message logging */
 #define MSG_LOG_LEN 64
@@ -218,8 +211,8 @@ static void ucpd_log_add_msg(uint16_t header, int dir)
 	 * crc -> GoodCrc received following tx message
 	 */
 	if (msg_log_cnt++ < MSG_LOG_LEN) {
-		int msg_bytes = MIN((PD_HEADER_CNT(header) << 2) + 2,
-				    MSG_BUF_LEN);
+		int msg_bytes =
+			MIN((PD_HEADER_CNT(header) << 2) + 2, MSG_BUF_LEN);
 
 		msg_log[idx].header = header;
 		msg_log[idx].ts = ts;
@@ -278,10 +271,10 @@ static void ucpd_cc_status(int port)
 	 * values of CC voltage detector, polarity, and PD enable status are
 	 * displayed.
 	 */
-	rv = stm32gx_ucpd_get_cc(port,&v_cc1, &v_cc2);
+	rv = stm32gx_ucpd_get_cc(port, &v_cc1, &v_cc2);
 	rp_name = rp_string[(rc >> 4) % 0x3];
-	ccprintf("\tcc1\t = %s\n\tcc2\t = %s\n\tRp\t = %s\n",
-		 ccx[cc1_pull], ccx[cc2_pull], rp_name);
+	ccprintf("\tcc1\t = %s\n\tcc2\t = %s\n\tRp\t = %s\n", ccx[cc1_pull],
+		 ccx[cc2_pull], rp_name);
 	if (!rv)
 		ccprintf("\tcc1_v\t = %d\n\tcc2_v\t = %d\n", v_cc1, v_cc2);
 }
@@ -329,8 +322,8 @@ static void ucpd_cc_change_notify(void)
 		ccprintf("vstate: cc1 = %x, cc2 = %x, Rp = %d\n",
 			 (sr >> STM32_UCPD_SR_VSTATE_CC1_SHIFT) & 0x3,
 			 (sr >> STM32_UCPD_SR_VSTATE_CC2_SHIFT) & 0x3,
-			 (ucpd_cc_set_save >> STM32_UCPD_CR_ANASUBMODE_SHIFT)
-			 & 0x3);
+			 (ucpd_cc_set_save >> STM32_UCPD_CR_ANASUBMODE_SHIFT) &
+				 0x3);
 		/* Display CC status on EC console */
 		ucpd_cc_status(0);
 	}
@@ -345,7 +338,9 @@ static int ucpd_msg_is_good_crc(uint16_t header)
 	 * type in the header.
 	 */
 	return ((PD_HEADER_CNT(header) == 0) && (PD_HEADER_EXT(header) == 0) &&
-		(PD_HEADER_TYPE(header) == PD_CTRL_GOOD_CRC)) ? 1 : 0;
+		(PD_HEADER_TYPE(header) == PD_CTRL_GOOD_CRC)) ?
+		       1 :
+		       0;
 }
 
 static void ucpd_hard_reset_rx_log(void)
@@ -365,7 +360,7 @@ static void ucpd_port_enable(int port, int enable)
 static int ucpd_is_cc_pull_active(int port, enum usbpd_cc_pin cc_line)
 {
 	int cc_enable = (STM32_UCPD_CR(port) & STM32_UCPD_CR_CCENABLE_MASK) >>
-					       STM32_UCPD_CR_CCENABLE_SHIFT;
+			STM32_UCPD_CR_CCENABLE_SHIFT;
 
 	return ((cc_enable >> cc_line) & 0x1);
 }
@@ -425,10 +420,10 @@ int stm32gx_ucpd_init(int port)
 	task_disable_irq(STM32_IRQ_UCPD1);
 
 	/*
-	* After exiting reset, stm32gx will have dead battery mode enabled by
-	* default which connects Rd to CC1/CC2. This should be disabled when EC
-	* is powered up.
-	*/
+	 * After exiting reset, stm32gx will have dead battery mode enabled by
+	 * default which connects Rd to CC1/CC2. This should be disabled when EC
+	 * is powered up.
+	 */
 	STM32_PWR_CR3 |= STM32_PWR_CR3_UCPD1_DBDIS;
 
 	/* Ensure that clock to UCPD is enabled */
@@ -446,9 +441,9 @@ int stm32gx_ucpd_init(int port)
 	ucpd_port_enable(port, 0);
 
 	cfgr1_reg = STM32_UCPD_CFGR1_PSC_CLK_VAL(UCPD_PSC_DIV - 1) |
-		STM32_UCPD_CFGR1_TRANSWIN_VAL(UCPD_TRANSWIN_CNT - 1) |
-		STM32_UCPD_CFGR1_IFRGAP_VAL(UCPD_IFRGAP_CNT - 1) |
-		STM32_UCPD_CFGR1_HBITCLKD_VAL(UCPD_HBIT_DIV - 1);
+		    STM32_UCPD_CFGR1_TRANSWIN_VAL(UCPD_TRANSWIN_CNT - 1) |
+		    STM32_UCPD_CFGR1_IFRGAP_VAL(UCPD_IFRGAP_CNT - 1) |
+		    STM32_UCPD_CFGR1_HBITCLKD_VAL(UCPD_HBIT_DIV - 1);
 	STM32_UCPD_CFGR1(port) = cfgr1_reg;
 
 	/*
@@ -463,9 +458,9 @@ int stm32gx_ucpd_init(int port)
 
 	/* Configure CC change interrupts */
 	STM32_UCPD_IMR(port) = STM32_UCPD_IMR_TYPECEVT1IE |
-		STM32_UCPD_IMR_TYPECEVT2IE;
+			       STM32_UCPD_IMR_TYPECEVT2IE;
 	STM32_UCPD_ICR(port) = STM32_UCPD_ICR_TYPECEVT1CF |
-		STM32_UCPD_ICR_TYPECEVT2CF;
+			       STM32_UCPD_ICR_TYPECEVT2CF;
 
 	/* SOP'/SOP'' must be enabled via TCPCI call */
 	ucpd_rx_sop_prime_enabled = false;
@@ -486,7 +481,7 @@ int stm32gx_ucpd_release(int port)
 }
 
 int stm32gx_ucpd_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2)
+			enum tcpc_cc_voltage_status *cc2)
 {
 	int vstate_cc1;
 	int vstate_cc2;
@@ -500,7 +495,7 @@ int stm32gx_ucpd_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
 	 *
 	 * vstate_cc maps directly to cc_state from tcpci spec when ANAMODE = 1,
 	 * but needs to be modified slightly for case ANAMODE = 0.
-         *
+	 *
 	 * If presenting Rp (source), then need to to a circular shift of
 	 * vstate_ccx value:
 	 *     vstate_cc | cc_state
@@ -515,9 +510,9 @@ int stm32gx_ucpd_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
 	/* Get Rp or Rd active */
 	anamode = !!(STM32_UCPD_CR(port) & STM32_UCPD_CR_ANAMODE);
 	vstate_cc1 = (sr & STM32_UCPD_SR_VSTATE_CC1_MASK) >>
-		STM32_UCPD_SR_VSTATE_CC1_SHIFT;
+		     STM32_UCPD_SR_VSTATE_CC1_SHIFT;
 	vstate_cc2 = (sr & STM32_UCPD_SR_VSTATE_CC2_MASK) >>
-		STM32_UCPD_SR_VSTATE_CC2_SHIFT;
+		     STM32_UCPD_SR_VSTATE_CC2_SHIFT;
 
 	/* Do circular shift if port == source */
 	if (anamode) {
@@ -544,8 +539,9 @@ int stm32gx_ucpd_get_role_control(int port)
 	int cc1;
 	int cc2;
 	int anamode = !!(STM32_UCPD_CR(port) & STM32_UCPD_CR_ANAMODE);
-	int anasubmode = (STM32_UCPD_CR(port) & STM32_UCPD_CR_ANASUBMODE_MASK)
-		>> STM32_UCPD_CR_ANASUBMODE_SHIFT;
+	int anasubmode =
+		(STM32_UCPD_CR(port) & STM32_UCPD_CR_ANASUBMODE_MASK) >>
+		STM32_UCPD_CR_ANASUBMODE_SHIFT;
 
 	/*
 	 * Role control register is defined as:
@@ -575,9 +571,9 @@ int stm32gx_ucpd_get_role_control(int port)
 	 *   Rp  = (ANASUBMODE - 1) & 0x3
 	 */
 	cc1 = ucpd_is_cc_pull_active(port, USBPD_CC_PIN_1) ? anamode + 1 :
-		TYPEC_CC_OPEN;
+							     TYPEC_CC_OPEN;
 	cc2 = ucpd_is_cc_pull_active(port, USBPD_CC_PIN_2) ? anamode + 1 :
-		TYPEC_CC_OPEN;
+							     TYPEC_CC_OPEN;
 	role_control = cc1 | (cc2 << 2);
 	/* Circular shift anasubmode to convert to Rp range */
 	role_control |= (UCPD_ANASUB_TO_RP(anasubmode) << 4);
@@ -633,7 +629,7 @@ int stm32gx_ucpd_set_cc(int port, int cc_pull, int rp)
 	/* Set ANAMODE if cc_pull is Rd */
 	if (cc_pull == TYPEC_CC_RD) {
 		cr |= STM32_UCPD_CR_ANAMODE | STM32_UCPD_CR_CCENABLE_MASK;
-	/* Clear ANAMODE if cc_pull is Rp */
+		/* Clear ANAMODE if cc_pull is Rp */
 	} else if (cc_pull == TYPEC_CC_RP) {
 		cr &= ~(STM32_UCPD_CR_ANAMODE);
 		cr |= ucpd_get_cc_enable_mask(port);
@@ -650,7 +646,8 @@ int stm32gx_ucpd_set_cc(int port, int cc_pull, int rp)
 	return EC_SUCCESS;
 }
 
-int stm32gx_ucpd_set_polarity(int port, enum tcpc_cc_polarity polarity) {
+int stm32gx_ucpd_set_polarity(int port, enum tcpc_cc_polarity polarity)
+{
 	/*
 	 * Polarity impacts the PHYCCSEL, CCENABLE, and CCxTCDIS fields. This
 	 * function is called when polarity is updated at TCPM layer. STM32Gx
@@ -707,7 +704,7 @@ int stm32gx_ucpd_sop_prime_enable(int port, bool enable)
 }
 
 int stm32gx_ucpd_get_chip_info(int port, int live,
-			struct ec_response_pd_chip_info_v1 *chip_info)
+			       struct ec_response_pd_chip_info_v1 *chip_info)
 {
 	chip_info->vendor_id = USB_VID_STM32;
 	chip_info->product_id = 0;
@@ -726,7 +723,7 @@ static int stm32gx_ucpd_start_transmit(int port, enum ucpd_tx_msg msg_type)
 	type = ucpd_tx_active_buffer->type;
 
 	if (type == TCPCI_MSG_TX_HARD_RESET) {
-				/*
+		/*
 		 * From RM0440 45.4.4:
 		 * In order to facilitate generation of a Hard Reset, a special
 		 * code of TXMODE field is used. No other fields need to be
@@ -745,9 +742,9 @@ static int stm32gx_ucpd_start_transmit(int port, enum ucpd_tx_msg msg_type)
 		 */
 		/* Enable interrupt for Hard Reset sent/discarded */
 		STM32_UCPD_ICR(port) = STM32_UCPD_ICR_HRSTDISCCF |
-			STM32_UCPD_ICR_HRSTSENTCF;
+				       STM32_UCPD_ICR_HRSTSENTCF;
 		STM32_UCPD_IMR(port) |= STM32_UCPD_IMR_HRSTDISCIE |
-			STM32_UCPD_IMR_HRSTSENTIE;
+					STM32_UCPD_IMR_HRSTSENTIE;
 		/* Initiate Hard Reset */
 		STM32_UCPD_CR(port) |= STM32_UCPD_CR_TXHRST;
 	} else if (type != TCPCI_MSG_INVALID) {
@@ -794,7 +791,7 @@ static int stm32gx_ucpd_start_transmit(int port, enum ucpd_tx_msg msg_type)
 			STM32_UCPD_TX_ORDSETR(port) = ucpd_txorderset[type];
 
 		/* Reset msg byte index */
-		ucpd_tx_active_buffer-> msg_index = 0;
+		ucpd_tx_active_buffer->msg_index = 0;
 
 		/* Enable interrupts */
 		ucpd_tx_interrupts_enable(port, 1);
@@ -860,13 +857,11 @@ static void ucpd_task_log_dump(void)
 
 	ccprintf("\n\t UCDP Task Log\n");
 	for (n = 0; n < TX_STATE_LOG_LEN; n++) {
-		ccprintf("[%d]:\t\%8s\t%8s\t%02x\t%08x\t%09d\t%d\n",
-			 n,
+		ccprintf("[%d]:\t\%8s\t%8s\t%02x\t%08x\t%09d\t%d\n", n,
 			 ucpd_names[ucpd_tx_statelog[idx].enter_state],
 			 ucpd_names[ucpd_tx_statelog[idx].exit_state],
 			 ucpd_tx_statelog[idx].tx_request,
-			 ucpd_tx_statelog[idx].evt,
-			 ucpd_tx_statelog[idx].ts,
+			 ucpd_tx_statelog[idx].evt, ucpd_tx_statelog[idx].ts,
 			 ucpd_tx_statelog[idx].timeout_us);
 
 		idx = (idx + 1) & TX_STATE_LOG_MASK;
@@ -915,8 +910,8 @@ static void ucpd_manage_tx(int port, int evt)
 				 * not been sent yet, it needs to be discarded
 				 * based on the received message event.
 				 */
-				pd_transmit_complete(port,
-						     TCPC_TX_COMPLETE_DISCARDED);
+				pd_transmit_complete(
+					port, TCPC_TX_COMPLETE_DISCARDED);
 				ucpd_tx_request &= ~MSG_TCPM_MASK;
 			} else if (!ucpd_rx_msg_active) {
 				ucpd_set_tx_state(STATE_ACTIVE_TCPM);
@@ -924,9 +919,10 @@ static void ucpd_manage_tx(int port, int evt)
 				/* Save msgID required for GoodCRC check */
 				hdr = ucpd_tx_buffers[TX_MSG_TCPM].data.header;
 				msg_id_match = PD_HEADER_ID(hdr);
-				tx_retry_max = PD_HEADER_REV(hdr) == PD_REV30 ?
-					UCPD_N_RETRY_COUNT_REV30 :
-					UCPD_N_RETRY_COUNT_REV20;
+				tx_retry_max =
+					PD_HEADER_REV(hdr) == PD_REV30 ?
+						UCPD_N_RETRY_COUNT_REV30 :
+						UCPD_N_RETRY_COUNT_REV20;
 			}
 		}
 
@@ -962,8 +958,9 @@ static void ucpd_manage_tx(int port, int evt)
 					 * was just received.
 					 */
 					ucpd_set_tx_state(STATE_IDLE);
-					pd_transmit_complete(port,
-							     TCPC_TX_COMPLETE_DISCARDED);
+					pd_transmit_complete(
+						port,
+						TCPC_TX_COMPLETE_DISCARDED);
 					ucpd_set_tx_state(STATE_IDLE);
 				} else {
 					/*
@@ -977,8 +974,8 @@ static void ucpd_manage_tx(int port, int evt)
 				enum tcpc_transmit_complete status;
 
 				status = (evt & UCPD_EVT_TX_MSG_FAIL) ?
-					TCPC_TX_COMPLETE_FAILED :
-					TCPC_TX_COMPLETE_DISCARDED;
+						 TCPC_TX_COMPLETE_FAILED :
+						 TCPC_TX_COMPLETE_DISCARDED;
 				ucpd_set_tx_state(STATE_IDLE);
 				pd_transmit_complete(port, status);
 			}
@@ -997,11 +994,9 @@ static void ucpd_manage_tx(int port, int evt)
 		break;
 
 	case STATE_WAIT_CRC_ACK:
-		if (evt & UCPD_EVT_RX_GOOD_CRC &&
-		    ucpd_crc_id == msg_id_match) {
+		if (evt & UCPD_EVT_RX_GOOD_CRC && ucpd_crc_id == msg_id_match) {
 			/* GoodCRC with matching ID was received */
-			pd_transmit_complete(port,
-					     TCPC_TX_COMPLETE_SUCCESS);
+			pd_transmit_complete(port, TCPC_TX_COMPLETE_SUCCESS);
 			ucpd_set_tx_state(STATE_IDLE);
 #ifdef CONFIG_STM32G4_UCPD_DEBUG
 			ucpd_log_mark_crc();
@@ -1026,8 +1021,7 @@ static void ucpd_manage_tx(int port, int evt)
 			 * in this state, then treat it as a discard from an
 			 * incoming message.
 			 */
-			pd_transmit_complete(port,
-					     TCPC_TX_COMPLETE_DISCARDED);
+			pd_transmit_complete(port, TCPC_TX_COMPLETE_DISCARDED);
 			ucpd_set_tx_state(STATE_IDLE);
 		}
 		break;
@@ -1064,7 +1058,7 @@ static void ucpd_manage_tx(int port, int evt)
  */
 void ucpd_task(void *p)
 {
-	const int port = (int) ((intptr_t) p);
+	const int port = (int)((intptr_t)p);
 
 	/* Init variables used to manage tx process */
 	stm32gx_ucpd_state_init(port);
@@ -1117,8 +1111,8 @@ void ucpd_task(void *p)
 			ucpd_manage_tx(port, evt);
 			/* Look at task events only once. */
 			evt = 0;
-		} while (ucpd_tx_request && ucpd_tx_state == STATE_IDLE
-			 && !ucpd_rx_msg_active);
+		} while (ucpd_tx_request && ucpd_tx_state == STATE_IDLE &&
+			 !ucpd_rx_msg_active);
 	}
 }
 
@@ -1176,9 +1170,7 @@ static void ucpd_send_good_crc(int port, uint16_t rx_header)
 	task_set_event(TASK_ID_UCPD, UCPD_EVT_GOOD_CRC_REQ);
 }
 
-int stm32gx_ucpd_transmit(int port,
-			  enum tcpci_msg_type type,
-			  uint16_t header,
+int stm32gx_ucpd_transmit(int port, enum tcpci_msg_type type, uint16_t header,
 			  const uint32_t *data)
 {
 	/* Length in bytes = (4 * object len) + 2 header byes */
@@ -1220,11 +1212,11 @@ int stm32gx_ucpd_get_message_raw(int port, uint32_t *payload, int *head)
 	*head = *rx_header;
 
 #ifdef CONFIG_USB_PD_DECODE_SOP
-/*
- * The message header is a 16-bit value that's stored in a 32-bit data type.
- * SOP* is encoded in bits 31 to 28 of the 32-bit data type.
- * NOTE: The 4 byte header is not part of the PD spec.
- */
+	/*
+	 * The message header is a 16-bit value that's stored in a 32-bit data
+	 * type. SOP* is encoded in bits 31 to 28 of the 32-bit data type. NOTE:
+	 * The 4 byte header is not part of the PD spec.
+	 */
 	/* Get SOP value */
 	sop = STM32_UCPD_RX_ORDSETR(port) & STM32_UCPD_RXORDSETR_MASK;
 	/* Put SOP in bits 31:28 of 32 bit header */
@@ -1253,9 +1245,10 @@ static void stm32gx_ucpd1_irq(void)
 	/* STM32_IRQ_UCPD indicates this is from UCPD1, so port = 0 */
 	int port = 0;
 	uint32_t sr = STM32_UCPD_SR(port);
-	uint32_t tx_done_mask = STM32_UCPD_SR_TXMSGSENT | STM32_UCPD_SR_TXMSGABT
-		| STM32_UCPD_SR_TXMSGDISC | STM32_UCPD_SR_HRSTSENT |
-		STM32_UCPD_SR_HRSTDISC;
+	uint32_t tx_done_mask = STM32_UCPD_SR_TXMSGSENT |
+				STM32_UCPD_SR_TXMSGABT |
+				STM32_UCPD_SR_TXMSGDISC |
+				STM32_UCPD_SR_HRSTSENT | STM32_UCPD_SR_HRSTDISC;
 
 	/* Check for CC events, set event to wake PD task */
 	if (sr & (STM32_UCPD_SR_TYPECEVT1 | STM32_UCPD_SR_TYPECEVT2)) {
@@ -1279,8 +1272,8 @@ static void stm32gx_ucpd1_irq(void)
 #ifdef CONFIG_STM32G4_UCPD_DEBUG
 			ucpd_log_mark_tx_comp();
 #endif
-		} else if (sr & (STM32_UCPD_SR_TXMSGABT |
-				 STM32_UCPD_SR_TXUND)) {
+		} else if (sr &
+			   (STM32_UCPD_SR_TXMSGABT | STM32_UCPD_SR_TXUND)) {
 			task_set_event(TASK_ID_UCPD, UCPD_EVT_TX_MSG_FAIL);
 		} else if (sr & STM32_UCPD_SR_TXMSGDISC) {
 			task_set_event(TASK_ID_UCPD, UCPD_EVT_TX_MSG_DISC);
@@ -1320,7 +1313,7 @@ static void stm32gx_ucpd1_irq(void)
 			int good_crc = 0;
 
 			type = STM32_UCPD_RX_ORDSETR(port) &
-				STM32_UCPD_RXORDSETR_MASK;
+			       STM32_UCPD_RXORDSETR_MASK;
 
 			good_crc = ucpd_msg_is_good_crc(*rx_header);
 
@@ -1337,26 +1330,25 @@ static void stm32gx_ucpd1_irq(void)
 			 */
 			if (!good_crc && (ucpd_rx_sop_prime_enabled ||
 					  type == TCPCI_MSG_SOP)) {
-
 				/*
 				 * If BIST test mode is active, then still need
 				 * to send GoodCRC reply, but there is no need
 				 * to send the message up to the tcpm layer.
 				 */
-				if(!ucpd_rx_bist_mode) {
+				if (!ucpd_rx_bist_mode) {
 					if (tcpm_enqueue_message(port))
-						hook_call_deferred(&ucpd_rx_enque_error_data,
-							   0);
+						hook_call_deferred(
+							&ucpd_rx_enque_error_data,
+							0);
 				}
 
-				task_set_event(TASK_ID_UCPD,
-						       UCPD_EVT_RX_MSG);
+				task_set_event(TASK_ID_UCPD, UCPD_EVT_RX_MSG);
 
 				/* Send GoodCRC message (if required) */
 				ucpd_send_good_crc(port, *rx_header);
 			} else if (good_crc) {
 				task_set_event(TASK_ID_UCPD,
-						       UCPD_EVT_RX_GOOD_CRC);
+					       UCPD_EVT_RX_GOOD_CRC);
 				ucpd_crc_id = PD_HEADER_ID(*rx_header);
 			}
 		} else {
@@ -1379,44 +1371,16 @@ DECLARE_IRQ(STM32_IRQ_UCPD1, stm32gx_ucpd1_irq, 1);
 
 #ifdef CONFIG_STM32G4_UCPD_DEBUG
 static char ctrl_names[][12] = {
-	"rsvd",
-	"GoodCRC",
-	"Goto Min",
-	"Accept",
-	"Reject",
-	"Ping",
-	"PS_Rdy",
-	"Get_SRC",
-	"Get_SNK",
-	"DR_Swap",
-	"PR_Swap",
-	"VCONN_Swp",
-	"Wait",
-	"Soft_Rst",
-	"RSVD",
-	"RSVD",
-	"Not_Sup",
-	"Get_SRC_Ext",
-	"Get_Status",
+	"rsvd",	   "GoodCRC",	"Goto Min",    "Accept",     "Reject",
+	"Ping",	   "PS_Rdy",	"Get_SRC",     "Get_SNK",    "DR_Swap",
+	"PR_Swap", "VCONN_Swp", "Wait",	       "Soft_Rst",   "RSVD",
+	"RSVD",	   "Not_Sup",	"Get_SRC_Ext", "Get_Status",
 };
 
 static char data_names[][10] = {
-	"RSVD",
-	"SRC_CAP",
-	"REQUEST",
-	"BIST",
-	"SINK_CAP",
-	"BATTERY",
-        "ALERT",
-	"GET_INFO",
-	"ENTER_USB",
-	"RSVD",
-	"RSVD",
-	"RSVD",
-	"RSVD",
-	"RSVD",
-	"RSVD",
-	"VDM",
+	"RSVD",	 "SRC_CAP",  "REQUEST",	  "BIST", "SINK_CAP", "BATTERY",
+	"ALERT", "GET_INFO", "ENTER_USB", "RSVD", "RSVD",     "RSVD",
+	"RSVD",	 "RSVD",     "RSVD",	  "VDM",
 };
 
 static void ucpd_dump_msg_log(void)
@@ -1428,7 +1392,6 @@ static void ucpd_dump_msg_log(void)
 	uint16_t header;
 	char *name;
 
-
 	ccprintf("ucpd: msg_total = %d\n", msg_log_cnt);
 	ccprintf("Idx\t  Delta(us)\tDir\t   Type\t\tLen\t s1  s2   PR\t DR\n");
 	ccprintf("-----------------------------------------------------------"
@@ -1446,18 +1409,13 @@ static void ucpd_dump_msg_log(void)
 			name = len ? data_names[type] : ctrl_names[type];
 			dir = msg_log[i].dir;
 			if (i) {
-				delta_ts = msg_log[i].ts - msg_log[i-1].ts;
+				delta_ts = msg_log[i].ts - msg_log[i - 1].ts;
 			}
 
 			ccprintf("msg[%02d]: %08d\t %s\t %8s\t %02d\t %d  %d\t"
 				 "%s\t %s",
-				 i,
-				 delta_ts,
-				 dir ? "Rx" : "Tx",
-				 name,
-				 len,
-				 msg_log[i].comp,
-				 msg_log[i].crc,
+				 i, delta_ts, dir ? "Rx" : "Tx", name, len,
+				 msg_log[i].comp, msg_log[i].crc,
 				 PD_HEADER_PROLE(header) ? "SRC" : "SNK",
 				 PD_HEADER_DROLE(header) ? "DFP" : "UFP");
 			len = MIN((len * 4) + 2, MSG_BUF_LEN);
@@ -1465,10 +1423,10 @@ static void ucpd_dump_msg_log(void)
 				ccprintf(" %02x", msg_log[i].buf[j]);
 		} else {
 			if (i) {
-				delta_ts = msg_log[i].ts - msg_log[i-1].ts;
+				delta_ts = msg_log[i].ts - msg_log[i - 1].ts;
 			}
-			ccprintf("msg[%02d]: %08d\t CC Voltage Change!",
-				 i, delta_ts);
+			ccprintf("msg[%02d]: %08d\t CC Voltage Change!", i,
+				 delta_ts);
 		}
 		ccprintf("\n");
 		msleep(5);
@@ -1496,7 +1454,7 @@ static void stm32gx_ucpd_set_cc_debug(int port, int cc_mask, int pull, int rp)
 	 */
 	/* Get existing cc enable value */
 	cc_enable = (cr & STM32_UCPD_CR_CCENABLE_MASK) >>
-		STM32_UCPD_CR_CCENABLE_SHIFT;
+		    STM32_UCPD_CR_CCENABLE_SHIFT;
 	/* Apply cc_mask (enable CC line specified) */
 	cc_enable |= cc_mask;
 
@@ -1527,12 +1485,12 @@ void ucpd_info(int port)
 
 	/* Dump ucpd task state info */
 	ccprintf("ucpd: tx_state = %s, tx_req = %02x, timeout_us = %d\n",
-		ucpd_names[ucpd_tx_state], ucpd_tx_request, ucpd_timeout_us);
+		 ucpd_names[ucpd_tx_state], ucpd_tx_request, ucpd_timeout_us);
 
 	ucpd_task_log_dump();
 }
 
-static int command_ucpd(int argc, char **argv)
+static int command_ucpd(int argc, const char **argv)
 {
 	uint32_t tx_data = 0;
 	char *e;
diff --git a/chip/stm32/ucpd-stm32gx.h b/chip/stm32/ucpd-stm32gx.h
index d3af41e5bc..d41503f9ef 100644
--- a/chip/stm32/ucpd-stm32gx.h
+++ b/chip/stm32/ucpd-stm32gx.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -37,7 +37,6 @@
 #define UCPD_TRANSWIN_CNT 8
 #define UCPD_IFRGAP_CNT 17
 
-
 /*
  * K-codes and ordered set defines. These codes and sets are used to encode
  * which type of USB-PD message is being sent. This information can be found in
@@ -47,48 +46,36 @@
 #define UCPD_SYNC1 0x18u
 #define UCPD_SYNC2 0x11u
 #define UCPD_SYNC3 0x06u
-#define UCPD_RST1  0x07u
-#define UCPD_RST2  0x19u
-#define UCPD_EOP   0x0Du
+#define UCPD_RST1 0x07u
+#define UCPD_RST2 0x19u
+#define UCPD_EOP 0x0Du
 
 /* This order of this enum matches tcpm_sop_type */
 enum ucpd_tx_ordset {
-	TX_ORDERSET_SOP =	(UCPD_SYNC1 |
-				(UCPD_SYNC1<<5u) |
-				(UCPD_SYNC1<<10u) |
-				(UCPD_SYNC2<<15u)),
-
-	TX_ORDERSET_SOP_PRIME =	(UCPD_SYNC1 |
-				(UCPD_SYNC1<<5u) |
-				(UCPD_SYNC3<<10u) |
-				(UCPD_SYNC3<<15u)),
-
-	TX_ORDERSET_SOP_PRIME_PRIME =	(UCPD_SYNC1 |
-				(UCPD_SYNC3<<5u) |
-				(UCPD_SYNC1<<10u) |
-				(UCPD_SYNC3<<15u)),
-
-	TX_ORDERSET_SOP_PRIME_DEBUG =	(UCPD_SYNC1 |
-					(UCPD_RST2<<5u) |
-					(UCPD_RST2<<10u) |
-					(UCPD_SYNC3<<15u)),
-
-	TX_ORDERSET_SOP_PRIME_PRIME_DEBUG =	(UCPD_SYNC1 |
-					(UCPD_RST2<<5u) |
-					(UCPD_SYNC3<<10u) |
-					(UCPD_SYNC2<<15u)),
-
-	TX_ORDERSET_HARD_RESET =	(UCPD_RST1  |
-					(UCPD_RST1<<5u) |
-					(UCPD_RST1<<10u)  |
-					(UCPD_RST2<<15u)),
-
-	TX_ORDERSET_CABLE_RESET =	(UCPD_RST1 |
-					(UCPD_SYNC1<<5u) |
-					(UCPD_RST1<<10u)  |
-					(UCPD_SYNC3<<15u)),
-};
+	TX_ORDERSET_SOP = (UCPD_SYNC1 | (UCPD_SYNC1 << 5u) |
+			   (UCPD_SYNC1 << 10u) | (UCPD_SYNC2 << 15u)),
+
+	TX_ORDERSET_SOP_PRIME = (UCPD_SYNC1 | (UCPD_SYNC1 << 5u) |
+				 (UCPD_SYNC3 << 10u) | (UCPD_SYNC3 << 15u)),
+
+	TX_ORDERSET_SOP_PRIME_PRIME =
+		(UCPD_SYNC1 | (UCPD_SYNC3 << 5u) | (UCPD_SYNC1 << 10u) |
+		 (UCPD_SYNC3 << 15u)),
 
+	TX_ORDERSET_SOP_PRIME_DEBUG =
+		(UCPD_SYNC1 | (UCPD_RST2 << 5u) | (UCPD_RST2 << 10u) |
+		 (UCPD_SYNC3 << 15u)),
+
+	TX_ORDERSET_SOP_PRIME_PRIME_DEBUG =
+		(UCPD_SYNC1 | (UCPD_RST2 << 5u) | (UCPD_SYNC3 << 10u) |
+		 (UCPD_SYNC2 << 15u)),
+
+	TX_ORDERSET_HARD_RESET = (UCPD_RST1 | (UCPD_RST1 << 5u) |
+				  (UCPD_RST1 << 10u) | (UCPD_RST2 << 15u)),
+
+	TX_ORDERSET_CABLE_RESET = (UCPD_RST1 | (UCPD_SYNC1 << 5u) |
+				   (UCPD_RST1 << 10u) | (UCPD_SYNC3 << 15u)),
+};
 
 /**
  * STM32Gx UCPD implementation of tcpci .init method
@@ -172,9 +159,7 @@ int stm32gx_ucpd_set_msg_header(int port, int power_role, int data_role);
  * @param *data -> pointer to message contents
  * @return EC_SUCCESS
  */
-int stm32gx_ucpd_transmit(int port,
-			enum tcpci_msg_type type,
-			uint16_t header,
+int stm32gx_ucpd_transmit(int port, enum tcpci_msg_type type, uint16_t header,
 			  const uint32_t *data);
 
 /**
diff --git a/chip/stm32/usart-stm32f0.c b/chip/stm32/usart-stm32f0.c
index 740d3929bc..56325cdc74 100644
--- a/chip/stm32/usart-stm32f0.c
+++ b/chip/stm32/usart-stm32f0.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,7 +23,7 @@ static struct usart_config const *configs[STM32_USARTS_MAX];
 
 struct usart_configs usart_get_configs(void)
 {
-	return (struct usart_configs) {configs, ARRAY_SIZE(configs)};
+	return (struct usart_configs){ configs, ARRAY_SIZE(configs) };
 }
 
 static void usart_variant_enable(struct usart_config const *config)
@@ -54,8 +54,7 @@ static void usart_variant_disable(struct usart_config const *config)
 	 * Only disable the shared interrupt for USART3/4 if both USARTs are
 	 * now disabled.
 	 */
-	if ((index == 0) ||
-	    (index == 1) ||
+	if ((index == 0) || (index == 1) ||
 	    (index == 2 && configs[3] == NULL) ||
 	    (index == 3 && configs[2] == NULL))
 		task_disable_irq(config->hw->irq);
@@ -64,18 +63,18 @@ static void usart_variant_disable(struct usart_config const *config)
 }
 
 static struct usart_hw_ops const usart_variant_hw_ops = {
-	.enable  = usart_variant_enable,
+	.enable = usart_variant_enable,
 	.disable = usart_variant_disable,
 };
 
 static void freq_change(void)
 {
-	size_t	i;
+	size_t i;
 
 	for (i = 0; i < ARRAY_SIZE(configs); ++i)
 		if (configs[i])
 			usart_set_baud_f0_l(configs[i], configs[i]->baud,
-					clock_get_freq());
+					    clock_get_freq());
 }
 
 DECLARE_HOOK(HOOK_FREQ_CHANGE, freq_change, HOOK_PRIO_DEFAULT);
@@ -98,12 +97,12 @@ void usart_clear_tc(struct usart_config const *config)
  */
 #if defined(CONFIG_STREAM_USART1)
 struct usart_hw_config const usart1_hw = {
-	.index          = 0,
-	.base           = STM32_USART1_BASE,
-	.irq            = STM32_IRQ_USART1,
+	.index = 0,
+	.base = STM32_USART1_BASE,
+	.irq = STM32_IRQ_USART1,
 	.clock_register = &STM32_RCC_APB2ENR,
-	.clock_enable   = STM32_RCC_PB2_USART1,
-	.ops            = &usart_variant_hw_ops,
+	.clock_enable = STM32_RCC_PB2_USART1,
+	.ops = &usart_variant_hw_ops,
 };
 
 static void usart1_interrupt(void)
@@ -116,12 +115,12 @@ DECLARE_IRQ(STM32_IRQ_USART1, usart1_interrupt, 2);
 
 #if defined(CONFIG_STREAM_USART2)
 struct usart_hw_config const usart2_hw = {
-	.index          = 1,
-	.base           = STM32_USART2_BASE,
-	.irq            = STM32_IRQ_USART2,
+	.index = 1,
+	.base = STM32_USART2_BASE,
+	.irq = STM32_IRQ_USART2,
 	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART2,
-	.ops            = &usart_variant_hw_ops,
+	.clock_enable = STM32_RCC_PB1_USART2,
+	.ops = &usart_variant_hw_ops,
 };
 
 static void usart2_interrupt(void)
@@ -134,23 +133,23 @@ DECLARE_IRQ(STM32_IRQ_USART2, usart2_interrupt, 2);
 
 #if defined(CONFIG_STREAM_USART3)
 struct usart_hw_config const usart3_hw = {
-	.index          = 2,
-	.base           = STM32_USART3_BASE,
-	.irq            = STM32_IRQ_USART3_4,
+	.index = 2,
+	.base = STM32_USART3_BASE,
+	.irq = STM32_IRQ_USART3_4,
 	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART3,
-	.ops            = &usart_variant_hw_ops,
+	.clock_enable = STM32_RCC_PB1_USART3,
+	.ops = &usart_variant_hw_ops,
 };
 #endif
 
 #if defined(CONFIG_STREAM_USART4)
 struct usart_hw_config const usart4_hw = {
-	.index          = 3,
-	.base           = STM32_USART4_BASE,
-	.irq            = STM32_IRQ_USART3_4,
+	.index = 3,
+	.base = STM32_USART4_BASE,
+	.irq = STM32_IRQ_USART3_4,
 	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART4,
-	.ops            = &usart_variant_hw_ops,
+	.clock_enable = STM32_RCC_PB1_USART4,
+	.ops = &usart_variant_hw_ops,
 };
 #endif
 
diff --git a/chip/stm32/usart-stm32f0.h b/chip/stm32/usart-stm32f0.h
index 1b7eee95a7..72c88fba9c 100644
--- a/chip/stm32/usart-stm32f0.h
+++ b/chip/stm32/usart-stm32f0.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/stm32/usart-stm32f3.c b/chip/stm32/usart-stm32f3.c
index 887d79d21f..f5a138643c 100644
--- a/chip/stm32/usart-stm32f3.c
+++ b/chip/stm32/usart-stm32f3.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,7 +22,7 @@ static struct usart_config const *configs[STM32_USARTS_MAX];
 
 struct usart_configs usart_get_configs(void)
 {
-	return (struct usart_configs) {configs, ARRAY_SIZE(configs)};
+	return (struct usart_configs){ configs, ARRAY_SIZE(configs) };
 }
 
 static void usart_variant_enable(struct usart_config const *config)
@@ -50,7 +50,7 @@ static void usart_variant_disable(struct usart_config const *config)
 }
 
 static struct usart_hw_ops const usart_variant_hw_ops = {
-	.enable  = usart_variant_enable,
+	.enable = usart_variant_enable,
 	.disable = usart_variant_disable,
 };
 
@@ -72,12 +72,12 @@ void usart_clear_tc(struct usart_config const *config)
  */
 #if defined(CONFIG_STREAM_USART1)
 struct usart_hw_config const usart1_hw = {
-	.index          = 0,
-	.base           = STM32_USART1_BASE,
-	.irq            = STM32_IRQ_USART1,
+	.index = 0,
+	.base = STM32_USART1_BASE,
+	.irq = STM32_IRQ_USART1,
 	.clock_register = &STM32_RCC_APB2ENR,
-	.clock_enable   = STM32_RCC_PB2_USART1,
-	.ops            = &usart_variant_hw_ops,
+	.clock_enable = STM32_RCC_PB2_USART1,
+	.ops = &usart_variant_hw_ops,
 };
 
 static void usart1_interrupt(void)
@@ -90,12 +90,12 @@ DECLARE_IRQ(STM32_IRQ_USART1, usart1_interrupt, 2);
 
 #if defined(CONFIG_STREAM_USART2)
 struct usart_hw_config const usart2_hw = {
-	.index          = 1,
-	.base           = STM32_USART2_BASE,
-	.irq            = STM32_IRQ_USART2,
+	.index = 1,
+	.base = STM32_USART2_BASE,
+	.irq = STM32_IRQ_USART2,
 	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART2,
-	.ops            = &usart_variant_hw_ops,
+	.clock_enable = STM32_RCC_PB1_USART2,
+	.ops = &usart_variant_hw_ops,
 };
 
 static void usart2_interrupt(void)
@@ -108,12 +108,12 @@ DECLARE_IRQ(STM32_IRQ_USART2, usart2_interrupt, 2);
 
 #if defined(CONFIG_STREAM_USART3)
 struct usart_hw_config const usart3_hw = {
-	.index          = 2,
-	.base           = STM32_USART3_BASE,
-	.irq            = STM32_IRQ_USART3,
+	.index = 2,
+	.base = STM32_USART3_BASE,
+	.irq = STM32_IRQ_USART3,
 	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART3,
-	.ops            = &usart_variant_hw_ops,
+	.clock_enable = STM32_RCC_PB1_USART3,
+	.ops = &usart_variant_hw_ops,
 };
 #endif
 
diff --git a/chip/stm32/usart-stm32f3.h b/chip/stm32/usart-stm32f3.h
index 09f1ba608c..e1c391183d 100644
--- a/chip/stm32/usart-stm32f3.h
+++ b/chip/stm32/usart-stm32f3.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/stm32/usart-stm32f4.c b/chip/stm32/usart-stm32f4.c
index 2c9e4b1f4a..a710760e3a 100644
--- a/chip/stm32/usart-stm32f4.c
+++ b/chip/stm32/usart-stm32f4.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,14 +24,13 @@ static struct usart_config const *configs[STM32_USARTS_MAX];
 
 struct usart_configs usart_get_configs(void)
 {
-	return (struct usart_configs) {configs, ARRAY_SIZE(configs)};
+	return (struct usart_configs){ configs, ARRAY_SIZE(configs) };
 }
 
 static void usart_variant_enable(struct usart_config const *config)
 {
 	configs[config->hw->index] = config;
 
-
 	/* Use single-bit sampling */
 	STM32_USART_CR3(config->hw->base) |= STM32_USART_CR3_ONEBIT;
 
@@ -48,7 +47,7 @@ static void usart_variant_disable(struct usart_config const *config)
 }
 
 static struct usart_hw_ops const usart_variant_hw_ops = {
-	.enable  = usart_variant_enable,
+	.enable = usart_variant_enable,
 	.disable = usart_variant_disable,
 };
 
@@ -58,12 +57,12 @@ static struct usart_hw_ops const usart_variant_hw_ops = {
  */
 #if defined(CONFIG_STREAM_USART1)
 struct usart_hw_config const usart1_hw = {
-	.index          = 0,
-	.base           = STM32_USART1_BASE,
-	.irq            = STM32_IRQ_USART1,
+	.index = 0,
+	.base = STM32_USART1_BASE,
+	.irq = STM32_IRQ_USART1,
 	.clock_register = &STM32_RCC_APB2ENR,
-	.clock_enable   = STM32_RCC_PB2_USART1,
-	.ops            = &usart_variant_hw_ops,
+	.clock_enable = STM32_RCC_PB2_USART1,
+	.ops = &usart_variant_hw_ops,
 };
 
 static void usart1_interrupt(void)
@@ -76,12 +75,12 @@ DECLARE_IRQ(STM32_IRQ_USART1, usart1_interrupt, 2);
 
 #if defined(CONFIG_STREAM_USART2)
 struct usart_hw_config const usart2_hw = {
-	.index          = 1,
-	.base           = STM32_USART2_BASE,
-	.irq            = STM32_IRQ_USART2,
+	.index = 1,
+	.base = STM32_USART2_BASE,
+	.irq = STM32_IRQ_USART2,
 	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART2,
-	.ops            = &usart_variant_hw_ops,
+	.clock_enable = STM32_RCC_PB1_USART2,
+	.ops = &usart_variant_hw_ops,
 };
 
 static void usart2_interrupt(void)
@@ -94,12 +93,12 @@ DECLARE_IRQ(STM32_IRQ_USART2, usart2_interrupt, 2);
 
 #if defined(CONFIG_STREAM_USART3)
 struct usart_hw_config const usart3_hw = {
-	.index          = 2,
-	.base           = STM32_USART3_BASE,
-	.irq            = STM32_IRQ_USART3,
+	.index = 2,
+	.base = STM32_USART3_BASE,
+	.irq = STM32_IRQ_USART3,
 	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART3,
-	.ops            = &usart_variant_hw_ops,
+	.clock_enable = STM32_RCC_PB1_USART3,
+	.ops = &usart_variant_hw_ops,
 };
 #endif
 
diff --git a/chip/stm32/usart-stm32f4.h b/chip/stm32/usart-stm32f4.h
index 49af2af405..5ecb4d62e1 100644
--- a/chip/stm32/usart-stm32f4.h
+++ b/chip/stm32/usart-stm32f4.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/stm32/usart-stm32l.c b/chip/stm32/usart-stm32l.c
index 8d23524bb0..dc300d598a 100644
--- a/chip/stm32/usart-stm32l.c
+++ b/chip/stm32/usart-stm32l.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,7 +23,7 @@ static struct usart_config const *configs[STM32_USARTS_MAX];
 
 struct usart_configs usart_get_configs(void)
 {
-	return (struct usart_configs) {configs, ARRAY_SIZE(configs)};
+	return (struct usart_configs){ configs, ARRAY_SIZE(configs) };
 }
 
 static void usart_variant_enable(struct usart_config const *config)
@@ -52,18 +52,18 @@ static void usart_variant_disable(struct usart_config const *config)
 }
 
 static struct usart_hw_ops const usart_variant_hw_ops = {
-	.enable  = usart_variant_enable,
+	.enable = usart_variant_enable,
 	.disable = usart_variant_disable,
 };
 
 static void freq_change(void)
 {
-	size_t	i;
+	size_t i;
 
 	for (i = 0; i < ARRAY_SIZE(configs); ++i)
 		if (configs[i])
 			usart_set_baud_f0_l(configs[i], configs[i]->baud,
-					clock_get_freq());
+					    clock_get_freq());
 }
 
 DECLARE_HOOK(HOOK_FREQ_CHANGE, freq_change, HOOK_PRIO_DEFAULT);
@@ -79,12 +79,12 @@ void usart_clear_tc(struct usart_config const *config)
  */
 #if defined(CONFIG_STREAM_USART1)
 struct usart_hw_config const usart1_hw = {
-	.index          = 0,
-	.base           = STM32_USART1_BASE,
-	.irq            = STM32_IRQ_USART1,
+	.index = 0,
+	.base = STM32_USART1_BASE,
+	.irq = STM32_IRQ_USART1,
 	.clock_register = &STM32_RCC_APB2ENR,
-	.clock_enable   = STM32_RCC_PB2_USART1,
-	.ops            = &usart_variant_hw_ops,
+	.clock_enable = STM32_RCC_PB2_USART1,
+	.ops = &usart_variant_hw_ops,
 };
 
 static void usart1_interrupt(void)
@@ -97,12 +97,12 @@ DECLARE_IRQ(STM32_IRQ_USART1, usart1_interrupt, 2);
 
 #if defined(CONFIG_STREAM_USART2)
 struct usart_hw_config const usart2_hw = {
-	.index          = 1,
-	.base           = STM32_USART2_BASE,
-	.irq            = STM32_IRQ_USART2,
+	.index = 1,
+	.base = STM32_USART2_BASE,
+	.irq = STM32_IRQ_USART2,
 	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART2,
-	.ops            = &usart_variant_hw_ops,
+	.clock_enable = STM32_RCC_PB1_USART2,
+	.ops = &usart_variant_hw_ops,
 };
 
 static void usart2_interrupt(void)
@@ -115,12 +115,12 @@ DECLARE_IRQ(STM32_IRQ_USART2, usart2_interrupt, 2);
 
 #if defined(CONFIG_STREAM_USART3)
 struct usart_hw_config const usart3_hw = {
-	.index          = 2,
-	.base           = STM32_USART3_BASE,
-	.irq            = STM32_IRQ_USART3,
+	.index = 2,
+	.base = STM32_USART3_BASE,
+	.irq = STM32_IRQ_USART3,
 	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART3,
-	.ops            = &usart_variant_hw_ops,
+	.clock_enable = STM32_RCC_PB1_USART3,
+	.ops = &usart_variant_hw_ops,
 };
 
 static void usart3_interrupt(void)
diff --git a/chip/stm32/usart-stm32l.h b/chip/stm32/usart-stm32l.h
index eb1ae9db1d..2bb92fe1c7 100644
--- a/chip/stm32/usart-stm32l.h
+++ b/chip/stm32/usart-stm32l.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/stm32/usart-stm32l5.c b/chip/stm32/usart-stm32l5.c
index 2306f54606..30e0f009ff 100644
--- a/chip/stm32/usart-stm32l5.c
+++ b/chip/stm32/usart-stm32l5.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,13 +17,13 @@
  * each USART, an entry will be NULL if no USART driver is initialized for the
  * corresponding hardware instance.
  */
-#define STM32_USARTS_MAX 5
+#define STM32_USARTS_MAX 6
 
 static struct usart_config const *configs[STM32_USARTS_MAX];
 
 struct usart_configs usart_get_configs(void)
 {
-	return (struct usart_configs) {configs, ARRAY_SIZE(configs)};
+	return (struct usart_configs){ configs, ARRAY_SIZE(configs) };
 }
 
 static void usart_variant_enable(struct usart_config const *config)
@@ -52,18 +52,18 @@ static void usart_variant_disable(struct usart_config const *config)
 }
 
 static struct usart_hw_ops const usart_variant_hw_ops = {
-	.enable  = usart_variant_enable,
+	.enable = usart_variant_enable,
 	.disable = usart_variant_disable,
 };
 
 static void freq_change(void)
 {
-	size_t	i;
+	size_t i;
 
 	for (i = 0; i < ARRAY_SIZE(configs); ++i)
 		if (configs[i])
 			usart_set_baud_f0_l(configs[i], configs[i]->baud,
-					clock_get_freq());
+					    clock_get_freq());
 }
 
 DECLARE_HOOK(HOOK_FREQ_CHANGE, freq_change, HOOK_PRIO_DEFAULT);
@@ -79,12 +79,12 @@ void usart_clear_tc(struct usart_config const *config)
  */
 #if defined(CONFIG_STREAM_USART1)
 struct usart_hw_config const usart1_hw = {
-	.index          = 0,
-	.base           = STM32_USART1_BASE,
-	.irq            = STM32_IRQ_USART1,
+	.index = 0,
+	.base = STM32_USART1_BASE,
+	.irq = STM32_IRQ_USART1,
 	.clock_register = &STM32_RCC_APB2ENR,
-	.clock_enable   = STM32_RCC_PB2_USART1,
-	.ops            = &usart_variant_hw_ops,
+	.clock_enable = STM32_RCC_PB2_USART1,
+	.ops = &usart_variant_hw_ops,
 };
 
 static void usart1_interrupt(void)
@@ -97,12 +97,12 @@ DECLARE_IRQ(STM32_IRQ_USART1, usart1_interrupt, 2);
 
 #if defined(CONFIG_STREAM_USART2)
 struct usart_hw_config const usart2_hw = {
-	.index          = 1,
-	.base           = STM32_USART2_BASE,
-	.irq            = STM32_IRQ_USART2,
+	.index = 1,
+	.base = STM32_USART2_BASE,
+	.irq = STM32_IRQ_USART2,
 	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART2,
-	.ops            = &usart_variant_hw_ops,
+	.clock_enable = STM32_RCC_PB1_USART2,
+	.ops = &usart_variant_hw_ops,
 };
 
 static void usart2_interrupt(void)
@@ -115,12 +115,12 @@ DECLARE_IRQ(STM32_IRQ_USART2, usart2_interrupt, 2);
 
 #if defined(CONFIG_STREAM_USART3)
 struct usart_hw_config const usart3_hw = {
-	.index          = 2,
-	.base           = STM32_USART3_BASE,
-	.irq            = STM32_IRQ_USART3,
+	.index = 2,
+	.base = STM32_USART3_BASE,
+	.irq = STM32_IRQ_USART3,
 	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART3,
-	.ops            = &usart_variant_hw_ops,
+	.clock_enable = STM32_RCC_PB1_USART3,
+	.ops = &usart_variant_hw_ops,
 };
 
 static void usart3_interrupt(void)
@@ -133,12 +133,12 @@ DECLARE_IRQ(STM32_IRQ_USART3, usart3_interrupt, 2);
 
 #if defined(CONFIG_STREAM_USART4)
 struct usart_hw_config const usart4_hw = {
-	.index          = 3,
-	.base           = STM32_USART4_BASE,
-	.irq            = STM32_IRQ_USART4,
+	.index = 3,
+	.base = STM32_USART4_BASE,
+	.irq = STM32_IRQ_USART4,
 	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART4,
-	.ops            = &usart_variant_hw_ops,
+	.clock_enable = STM32_RCC_PB1_USART4,
+	.ops = &usart_variant_hw_ops,
 };
 
 static void usart4_interrupt(void)
@@ -151,12 +151,12 @@ DECLARE_IRQ(STM32_IRQ_USART4, usart4_interrupt, 2);
 
 #if defined(CONFIG_STREAM_USART5)
 struct usart_hw_config const usart5_hw = {
-	.index          = 4,
-	.base           = STM32_USART5_BASE,
-	.irq            = STM32_IRQ_USART5,
+	.index = 4,
+	.base = STM32_USART5_BASE,
+	.irq = STM32_IRQ_USART5,
 	.clock_register = &STM32_RCC_APB1ENR,
-	.clock_enable   = STM32_RCC_PB1_USART5,
-	.ops            = &usart_variant_hw_ops,
+	.clock_enable = STM32_RCC_PB1_USART5,
+	.ops = &usart_variant_hw_ops,
 };
 
 static void usart5_interrupt(void)
@@ -166,3 +166,21 @@ static void usart5_interrupt(void)
 
 DECLARE_IRQ(STM32_IRQ_USART5, usart5_interrupt, 2);
 #endif
+
+#if defined(CONFIG_STREAM_USART9)
+struct usart_hw_config const usart9_hw = {
+	.index = 5,
+	.base = STM32_USART9_BASE,
+	.irq = STM32_IRQ_USART9,
+	.clock_register = &STM32_RCC_APB1ENR2,
+	.clock_enable = STM32_RCC_APB1ENR2_LPUART1EN,
+	.ops = &usart_variant_hw_ops,
+};
+
+static void usart9_interrupt(void)
+{
+	usart_interrupt(configs[5]);
+}
+
+DECLARE_IRQ(STM32_IRQ_USART9, usart9_interrupt, 2);
+#endif
diff --git a/chip/stm32/usart-stm32l5.h b/chip/stm32/usart-stm32l5.h
index cf4f8cdd1f..ccc0985bda 100644
--- a/chip/stm32/usart-stm32l5.h
+++ b/chip/stm32/usart-stm32l5.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,5 +16,6 @@ extern struct usart_hw_config const usart2_hw;
 extern struct usart_hw_config const usart3_hw;
 extern struct usart_hw_config const usart4_hw;
 extern struct usart_hw_config const usart5_hw;
+extern struct usart_hw_config const usart9_hw; /* LPUART1 */
 
 #endif /* __CROS_EC_USART_STM32L5_H */
diff --git a/chip/stm32/usart.c b/chip/stm32/usart.c
index 7f8c55aaa6..be9d0a4571 100644
--- a/chip/stm32/usart.c
+++ b/chip/stm32/usart.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -45,7 +45,7 @@ void usart_init(struct usart_config const *config)
 	cr2 = 0x0000;
 	cr3 = 0x0000;
 #if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \
-    defined(CHIP_FAMILY_STM32L4)
+	defined(CHIP_FAMILY_STM32L4)
 	if (config->flags & USART_CONFIG_FLAG_RX_INV)
 		cr2 |= BIT(16);
 	if (config->flags & USART_CONFIG_FLAG_TX_INV)
@@ -87,11 +87,16 @@ void usart_shutdown(struct usart_config const *config)
 }
 
 void usart_set_baud_f0_l(struct usart_config const *config, int baud,
-			int frequency_hz)
+			 int frequency_hz)
 {
-	int      div  = DIV_ROUND_NEAREST(frequency_hz, baud);
+	int div = DIV_ROUND_NEAREST(frequency_hz, baud);
 	intptr_t base = config->hw->base;
 
+#ifdef STM32_USART9_BASE
+	if (config->hw->base == STM32_USART9_BASE) /* LPUART */
+		div *= 256;
+#endif
+
 	if (div / 16 > 0) {
 		/*
 		 * CPU clock is high enough to support x16 oversampling.
@@ -110,10 +115,15 @@ void usart_set_baud_f0_l(struct usart_config const *config, int baud,
 }
 
 void usart_set_baud_f(struct usart_config const *config, int baud,
-		int frequency_hz)
+		      int frequency_hz)
 {
 	int div = DIV_ROUND_NEAREST(frequency_hz, baud);
 
+#ifdef STM32_USART9_BASE
+	if (config->hw->base == STM32_USART9_BASE) /* LPUART */
+		div *= 256;
+#endif
+
 	/* STM32F only supports x16 oversampling */
 	STM32_USART_BRR(config->hw->base) = div;
 }
diff --git a/chip/stm32/usart.h b/chip/stm32/usart.h
index 491bd66a04..9067fd4b6a 100644
--- a/chip/stm32/usart.h
+++ b/chip/stm32/usart.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -97,12 +97,12 @@ extern struct usart_tx const usart_tx_interrupt;
  * structure are provided by each variants driver, one per physical USART.
  */
 struct usart_hw_config {
-	int      index;
+	int index;
 	intptr_t base;
-	int      irq;
+	int irq;
 
 	uint32_t volatile *clock_register;
-	uint32_t           clock_enable;
+	uint32_t clock_enable;
 
 	struct usart_hw_ops const *ops;
 };
@@ -160,7 +160,7 @@ struct usart_config {
  * BUILD_ASSERT(RX_QUEUE.unit_bytes == 1);
  * BUILD_ASSERT(TX_QUEUE.unit_bytes == 1);
  */
-#define USART_CONFIG(HW, RX, TX, BAUD, FLAGS, RX_QUEUE, TX_QUEUE)	\
+#define USART_CONFIG(HW, RX, TX, BAUD, FLAGS, RX_QUEUE, TX_QUEUE) \
 	((struct usart_config const) {					\
 		.hw       = &HW,					\
 		.rx       = &RX,					\
@@ -208,9 +208,9 @@ void usart_tx_start(struct usart_config const *config);
  * change.  The baud rate divisor input frequency is passed in Hertz.
  */
 void usart_set_baud_f0_l(struct usart_config const *config, int baud,
-			int frequency_hz);
+			 int frequency_hz);
 void usart_set_baud_f(struct usart_config const *config, int baud,
-		int frequency_hz);
+		      int frequency_hz);
 
 /*
  * Allow specification of parity for this usart.
@@ -249,7 +249,7 @@ struct usart_configs {
 	 *
 	 * configs[i]->hw->index == i;
 	 */
-	struct usart_config const * const *configs;
+	struct usart_config const *const *configs;
 
 	/*
 	 * The total possible number of configs that this family supports.
diff --git a/chip/stm32/usart_host_command.c b/chip/stm32/usart_host_command.c
index f4d6a65fc4..437975e609 100644
--- a/chip/stm32/usart_host_command.c
+++ b/chip/stm32/usart_host_command.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,8 +19,8 @@
 #include "util.h"
 
 /* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_HOSTCMD, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_HOSTCMD, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_HOSTCMD, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_HOSTCMD, format, ##args)
 
 /*
  * Timeout to wait for complete request packet
@@ -51,7 +51,7 @@
 
 /*
  * Max data size for a version 3 request/response packet.  This is big enough
- * to handle a request/response header, flash write offset/size and 512 bytes 
+ * to handle a request/response header, flash write offset/size and 512 bytes
  * of request payload or 224 bytes of response payload.
  */
 #define USART_MAX_REQUEST_SIZE 0x220
@@ -271,12 +271,12 @@ static struct usart_rx_dma const usart_host_command_rx_dma = {
  * Configure USART structure with hardware, interrupt handlers, baudrate.
  */
 static struct usart_config const tl_usart = {
-	.hw	= &CONFIG_UART_HOST_COMMAND_HW,
-	.rx	= &usart_host_command_rx_dma.usart_rx,
-	.tx	= &usart_host_command_tx_interrupt,
-	.state	= &((struct usart_state){}),
-	.baud	= CONFIG_UART_HOST_COMMAND_BAUD_RATE,
-	.flags	= 0,
+	.hw = &CONFIG_UART_HOST_COMMAND_HW,
+	.rx = &usart_host_command_rx_dma.usart_rx,
+	.tx = &usart_host_command_tx_interrupt,
+	.state = &((struct usart_state){}),
+	.baud = CONFIG_UART_HOST_COMMAND_BAUD_RATE,
+	.flags = 0,
 };
 
 /*
@@ -327,7 +327,7 @@ static void usart_host_command_process_request(void)
 {
 	/* Handle usart_in_buffer as ec_host_request */
 	struct ec_host_request *ec_request =
-			(struct ec_host_request *)usart_in_buffer;
+		(struct ec_host_request *)usart_in_buffer;
 
 	/* Prepare host_packet for host command task */
 	static struct host_packet uart_packet;
@@ -362,16 +362,13 @@ static void usart_host_command_process_request(void)
 	 * Cancel deferred call to timeout handler as request
 	 * received was good.
 	 */
-	hook_call_deferred(
-		&usart_host_command_request_timeout_data,
-		-1);
+	hook_call_deferred(&usart_host_command_request_timeout_data, -1);
 
 	uart_packet.send_response = usart_host_command_process_response;
 	uart_packet.request = usart_in_buffer;
 	uart_packet.request_temp = NULL;
 	uart_packet.request_max = sizeof(usart_in_buffer);
-	uart_packet.request_size =
-			host_request_expected_size(ec_request);
+	uart_packet.request_size = host_request_expected_size(ec_request);
 	uart_packet.response = usart_out_buffer;
 	uart_packet.response_max = sizeof(usart_out_buffer);
 	uart_packet.response_size = 0;
@@ -427,14 +424,10 @@ static void usart_host_command_process_response(struct host_packet *pkt)
 static void usart_host_command_reset(void)
 {
 	/* Cancel deferred call to process_request. */
-	hook_call_deferred(
-		&usart_host_command_process_request_data,
-		-1);
+	hook_call_deferred(&usart_host_command_process_request_data, -1);
 
 	/* Cancel deferred call to timeout handler. */
-	hook_call_deferred(
-		&usart_host_command_request_timeout_data,
-		-1);
+	hook_call_deferred(&usart_host_command_request_timeout_data, -1);
 
 	/*
 	 * Disable interrupts before entering critical region
@@ -491,7 +484,7 @@ size_t usart_host_command_rx_append_data(struct usart_config const *config,
 {
 	/* Define ec_host_request pointer to process in bytes later*/
 	struct ec_host_request *ec_request =
-			(struct ec_host_request *) usart_in_buffer;
+		(struct ec_host_request *)usart_in_buffer;
 
 	/* Once the header is received, store the datalen */
 	static int usart_in_datalen;
@@ -504,8 +497,7 @@ size_t usart_host_command_rx_append_data(struct usart_config const *config,
 	    current_state == USART_HOST_CMD_RECEIVING ||
 	    (usart_in_head + count) < USART_MAX_REQUEST_SIZE) {
 		/* Copy all the bytes from DMA FIFO */
-		memcpy(usart_in_buffer + usart_in_head,
-			src, count);
+		memcpy(usart_in_buffer + usart_in_head, src, count);
 	}
 
 	/*
@@ -519,7 +511,7 @@ size_t usart_host_command_rx_append_data(struct usart_config const *config,
 	if (current_state == USART_HOST_CMD_READY_TO_RX) {
 		/* Kick deferred call to request timeout handler */
 		hook_call_deferred(&usart_host_command_request_timeout_data,
-			USART_REQ_RX_TIMEOUT);
+				   USART_REQ_RX_TIMEOUT);
 
 		/* Move current state to receiving */
 		current_state = USART_HOST_CMD_RECEIVING;
@@ -551,8 +543,7 @@ size_t usart_host_command_rx_append_data(struct usart_config const *config,
 		} else if (usart_in_head > usart_in_datalen) {
 			/* Cancel deferred call to process_request */
 			hook_call_deferred(
-				&usart_host_command_process_request_data,
-				-1);
+				&usart_host_command_process_request_data, -1);
 
 			/* Move state to overrun*/
 			current_state = USART_HOST_CMD_RX_OVERRUN;
@@ -579,13 +570,12 @@ size_t usart_host_command_tx_remove_data(struct usart_config const *config,
 {
 	size_t bytes_remaining = 0;
 
-	if (current_state == USART_HOST_CMD_SENDING &&
-	    usart_out_datalen != 0) {
+	if (current_state == USART_HOST_CMD_SENDING && usart_out_datalen != 0) {
 		/* Calculate byte_remaining in out_buffer */
 		bytes_remaining = usart_out_datalen - usart_out_head;
 
 		/* Get char on the head */
-		*((uint8_t *) dest) = usart_out_buffer[usart_out_head++];
+		*((uint8_t *)dest) = usart_out_buffer[usart_out_head++];
 
 		/* If no bytes remaining, reset layer to accept next
 		 * request.
diff --git a/chip/stm32/usart_host_command.h b/chip/stm32/usart_host_command.h
index ee41d8a59b..ee4bdd88dc 100644
--- a/chip/stm32/usart_host_command.h
+++ b/chip/stm32/usart_host_command.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,7 @@
 #ifndef __CROS_EC_USART_HOST_COMMAND_H
 #define __CROS_EC_USART_HOST_COMMAND_H
 
-#include <stdarg.h>  /* For va_list */
+#include <stdarg.h> /* For va_list */
 #include "common.h"
 #include "gpio.h"
 #include "host_command.h"
diff --git a/chip/stm32/usart_info_command.c b/chip/stm32/usart_info_command.c
index 7b7dc1362a..ca73b51210 100644
--- a/chip/stm32/usart_info_command.c
+++ b/chip/stm32/usart_info_command.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -9,7 +9,7 @@
 #include "console.h"
 #include "usart.h"
 
-static int command_usart_info(int argc, char **argv)
+static int command_usart_info(int argc, const char **argv)
 {
 	struct usart_configs configs = usart_get_configs();
 	size_t i;
@@ -39,7 +39,5 @@ static int command_usart_info(int argc, char **argv)
 	return EC_SUCCESS;
 }
 
-DECLARE_CONSOLE_COMMAND(usart_info,
-			command_usart_info,
-			NULL,
+DECLARE_CONSOLE_COMMAND(usart_info, command_usart_info, NULL,
 			"Display USART info");
diff --git a/chip/stm32/usart_rx_dma.c b/chip/stm32/usart_rx_dma.c
index c75ebdde41..21c8313c73 100644
--- a/chip/stm32/usart_rx_dma.c
+++ b/chip/stm32/usart_rx_dma.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,7 +14,7 @@
 #include "util.h"
 
 typedef size_t (*add_data_t)(struct usart_config const *config,
-	const uint8_t *src, size_t count);
+			     const uint8_t *src, size_t count);
 
 void usart_rx_dma_init(struct usart_config const *config)
 {
@@ -25,10 +25,9 @@ void usart_rx_dma_init(struct usart_config const *config)
 
 	struct dma_option options = {
 		.channel = dma_config->channel,
-		.periph  = (void *)&STM32_USART_RDR(base),
-		.flags   = (STM32_DMA_CCR_MSIZE_8_BIT |
-			    STM32_DMA_CCR_PSIZE_8_BIT |
-			    STM32_DMA_CCR_CIRC),
+		.periph = (void *)&STM32_USART_RDR(base),
+		.flags = (STM32_DMA_CCR_MSIZE_8_BIT |
+			  STM32_DMA_CCR_PSIZE_8_BIT | STM32_DMA_CCR_CIRC),
 	};
 
 	if (IS_ENABLED(CHIP_FAMILY_STM32F4))
@@ -38,31 +37,29 @@ void usart_rx_dma_init(struct usart_config const *config)
 	STM32_USART_CR1(base) |= STM32_USART_CR1_RE;
 	STM32_USART_CR3(base) |= STM32_USART_CR3_DMAR;
 
-	dma_config->state->index     = 0;
+	dma_config->state->index = 0;
 	dma_config->state->max_bytes = 0;
 
 	dma_start_rx(&options, dma_config->fifo_size, dma_config->fifo_buffer);
 }
 
-static void usart_rx_dma_interrupt_common(
-		struct usart_config const *config,
-		add_data_t add_data)
+static void usart_rx_dma_interrupt_common(struct usart_config const *config,
+					  add_data_t add_data)
 {
 	struct usart_rx_dma const *dma_config =
 		DOWNCAST(config->rx, struct usart_rx_dma const, usart_rx);
 
-	dma_chan_t *channel  = dma_get_channel(dma_config->channel);
-	size_t     new_index = dma_bytes_done(channel, dma_config->fifo_size);
-	size_t     old_index = dma_config->state->index;
-	size_t     new_bytes = 0;
-	size_t     added     = 0;
+	dma_chan_t *channel = dma_get_channel(dma_config->channel);
+	size_t new_index = dma_bytes_done(channel, dma_config->fifo_size);
+	size_t old_index = dma_config->state->index;
+	size_t new_bytes = 0;
+	size_t added = 0;
 
 	if (new_index > old_index) {
 		new_bytes = new_index - old_index;
 
-		added = add_data(config,
-				dma_config->fifo_buffer + old_index,
-				new_bytes);
+		added = add_data(config, dma_config->fifo_buffer + old_index,
+				 new_bytes);
 	} else if (new_index < old_index) {
 		/*
 		 * Handle the case where the received bytes are not contiguous
@@ -71,12 +68,9 @@ static void usart_rx_dma_interrupt_common(
 		 */
 		new_bytes = dma_config->fifo_size - (old_index - new_index);
 
-		added = add_data(config,
-				dma_config->fifo_buffer + old_index,
-				dma_config->fifo_size - old_index) +
-			add_data(config,
-				dma_config->fifo_buffer,
-				new_index);
+		added = add_data(config, dma_config->fifo_buffer + old_index,
+				 dma_config->fifo_size - old_index) +
+			add_data(config, dma_config->fifo_buffer, new_index);
 	} else {
 		/* (new_index == old_index): nothing to add to the queue. */
 	}
@@ -89,8 +83,8 @@ static void usart_rx_dma_interrupt_common(
 	dma_config->state->index = new_index;
 }
 
-static size_t queue_add(struct usart_config const *config,
-			const uint8_t *src, size_t count)
+static size_t queue_add(struct usart_config const *config, const uint8_t *src,
+			size_t count)
 {
 	return queue_add_units(config->producer.queue, (void *)src, count);
 }
@@ -100,7 +94,6 @@ void usart_rx_dma_interrupt(struct usart_config const *config)
 	usart_rx_dma_interrupt_common(config, &queue_add);
 }
 
-
 #if defined(CONFIG_USART_HOST_COMMAND)
 void usart_host_command_rx_dma_interrupt(struct usart_config const *config)
 {
diff --git a/chip/stm32/usart_rx_dma.h b/chip/stm32/usart_rx_dma.h
index 064ab8046c..6d273d18b9 100644
--- a/chip/stm32/usart_rx_dma.h
+++ b/chip/stm32/usart_rx_dma.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -44,7 +44,7 @@
  * reasonable stress test the "DMA RX max_bytes" value will be a reasonable
  * size for the FIFO (perhaps +10% for safety).
  */
-#define USART_RX_DMA(CHANNEL, FIFO_SIZE)				\
+#define USART_RX_DMA(CHANNEL, FIFO_SIZE) \
 	((struct usart_rx_dma const) {					\
 		.usart_rx = {						\
 			.producer_ops = {				\
@@ -88,7 +88,7 @@ struct usart_rx_dma {
 	struct usart_rx_dma_state volatile *state;
 
 	uint8_t *fifo_buffer;
-	size_t  fifo_size;
+	size_t fifo_size;
 
 	enum dma_channel channel;
 };
diff --git a/chip/stm32/usart_rx_interrupt-stm32f0.c b/chip/stm32/usart_rx_interrupt-stm32f0.c
index a756455f9b..dfbe6ec3ff 120000..100644
--- a/chip/stm32/usart_rx_interrupt-stm32f0.c
+++ b/chip/stm32/usart_rx_interrupt-stm32f0.c
@@ -1 +1,49 @@
-usart_rx_interrupt.c
\ No newline at end of file
+/* Copyright 2014 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Interrupt based USART RX driver for STM32F0 and STM32F3 */
+
+#include "usart.h"
+
+#include "atomic.h"
+#include "common.h"
+#include "queue.h"
+#include "registers.h"
+
+static void usart_rx_init(struct usart_config const *config)
+{
+	intptr_t base = config->hw->base;
+
+	STM32_USART_CR1(base) |= STM32_USART_CR1_RXNEIE;
+	STM32_USART_CR1(base) |= STM32_USART_CR1_RE;
+	STM32_USART_CR3(base) |= STM32_USART_CR3_OVRDIS;
+}
+
+static void usart_rx_interrupt_handler(struct usart_config const *config)
+{
+	intptr_t base = config->hw->base;
+	int32_t status = STM32_USART_SR(base);
+
+	if (status & STM32_USART_SR_RXNE) {
+		uint8_t byte = STM32_USART_RDR(base);
+
+		if (!queue_add_unit(config->producer.queue, &byte))
+			atomic_add((atomic_t *)&(config->state->rx_dropped), 1);
+	}
+}
+
+struct usart_rx const usart_rx_interrupt = {
+	.producer_ops = {
+		/*
+		 * Nothing to do here, we either had enough space in the queue
+		 * when a character came in or we dropped it already.
+		 */
+		.read = NULL,
+	},
+
+	.init      = usart_rx_init,
+	.interrupt = usart_rx_interrupt_handler,
+	.info      = NULL,
+};
diff --git a/chip/stm32/usart_rx_interrupt-stm32f3.c b/chip/stm32/usart_rx_interrupt-stm32f3.c
index a756455f9b..dfbe6ec3ff 120000..100644
--- a/chip/stm32/usart_rx_interrupt-stm32f3.c
+++ b/chip/stm32/usart_rx_interrupt-stm32f3.c
@@ -1 +1,49 @@
-usart_rx_interrupt.c
\ No newline at end of file
+/* Copyright 2014 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Interrupt based USART RX driver for STM32F0 and STM32F3 */
+
+#include "usart.h"
+
+#include "atomic.h"
+#include "common.h"
+#include "queue.h"
+#include "registers.h"
+
+static void usart_rx_init(struct usart_config const *config)
+{
+	intptr_t base = config->hw->base;
+
+	STM32_USART_CR1(base) |= STM32_USART_CR1_RXNEIE;
+	STM32_USART_CR1(base) |= STM32_USART_CR1_RE;
+	STM32_USART_CR3(base) |= STM32_USART_CR3_OVRDIS;
+}
+
+static void usart_rx_interrupt_handler(struct usart_config const *config)
+{
+	intptr_t base = config->hw->base;
+	int32_t status = STM32_USART_SR(base);
+
+	if (status & STM32_USART_SR_RXNE) {
+		uint8_t byte = STM32_USART_RDR(base);
+
+		if (!queue_add_unit(config->producer.queue, &byte))
+			atomic_add((atomic_t *)&(config->state->rx_dropped), 1);
+	}
+}
+
+struct usart_rx const usart_rx_interrupt = {
+	.producer_ops = {
+		/*
+		 * Nothing to do here, we either had enough space in the queue
+		 * when a character came in or we dropped it already.
+		 */
+		.read = NULL,
+	},
+
+	.init      = usart_rx_init,
+	.interrupt = usart_rx_interrupt_handler,
+	.info      = NULL,
+};
diff --git a/chip/stm32/usart_rx_interrupt-stm32f4.c b/chip/stm32/usart_rx_interrupt-stm32f4.c
index b796ae1175..1d86c7d5b6 100644
--- a/chip/stm32/usart_rx_interrupt-stm32f4.c
+++ b/chip/stm32/usart_rx_interrupt-stm32f4.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,8 +26,8 @@ static void usart_rx_init(struct usart_config const *config)
 
 static void usart_rx_interrupt_handler(struct usart_config const *config)
 {
-	intptr_t base   = config->hw->base;
-	int32_t  status = STM32_USART_SR(base);
+	intptr_t base = config->hw->base;
+	int32_t status = STM32_USART_SR(base);
 
 	if (status & STM32_USART_SR_RXNE) {
 		uint8_t byte = STM32_USART_RDR(base);
diff --git a/chip/stm32/usart_rx_interrupt-stm32l.c b/chip/stm32/usart_rx_interrupt-stm32l.c
index a89d474d05..750809307b 100644
--- a/chip/stm32/usart_rx_interrupt-stm32l.c
+++ b/chip/stm32/usart_rx_interrupt-stm32l.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,8 +22,8 @@ static void usart_rx_init(struct usart_config const *config)
 
 static void usart_rx_interrupt_handler(struct usart_config const *config)
 {
-	intptr_t base   = config->hw->base;
-	int32_t  status = STM32_USART_SR(base);
+	intptr_t base = config->hw->base;
+	int32_t status = STM32_USART_SR(base);
 
 	/*
 	 * We have to check and clear the overrun error flag on STM32L because
diff --git a/chip/stm32/usart_rx_interrupt-stm32l5.c b/chip/stm32/usart_rx_interrupt-stm32l5.c
index fa644b6baf..45c2ecca9f 100644
--- a/chip/stm32/usart_rx_interrupt-stm32l5.c
+++ b/chip/stm32/usart_rx_interrupt-stm32l5.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/stm32/usart_rx_interrupt.c b/chip/stm32/usart_rx_interrupt.c
index 49d4e83894..dfbe6ec3ff 100644
--- a/chip/stm32/usart_rx_interrupt.c
+++ b/chip/stm32/usart_rx_interrupt.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,8 +23,8 @@ static void usart_rx_init(struct usart_config const *config)
 
 static void usart_rx_interrupt_handler(struct usart_config const *config)
 {
-	intptr_t base   = config->hw->base;
-	int32_t  status = STM32_USART_SR(base);
+	intptr_t base = config->hw->base;
+	int32_t status = STM32_USART_SR(base);
 
 	if (status & STM32_USART_SR_RXNE) {
 		uint8_t byte = STM32_USART_RDR(base);
diff --git a/chip/stm32/usart_tx_dma.c b/chip/stm32/usart_tx_dma.c
index 0c8e2c73d6..8128231ff7 100644
--- a/chip/stm32/usart_tx_dma.c
+++ b/chip/stm32/usart_tx_dma.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -36,13 +36,13 @@ static void usart_tx_dma_start(struct usart_config const *config,
 			       struct usart_tx_dma const *dma_config)
 {
 	struct usart_tx_dma_state volatile *state = dma_config->state;
-	intptr_t                           base   = config->hw->base;
+	intptr_t base = config->hw->base;
 
 	struct dma_option options = {
 		.channel = dma_config->channel,
-		.periph  = (void *)&STM32_USART_TDR(base),
-		.flags   = (STM32_DMA_CCR_MSIZE_8_BIT |
-			    STM32_DMA_CCR_PSIZE_8_BIT),
+		.periph = (void *)&STM32_USART_TDR(base),
+		.flags =
+			(STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT),
 	};
 
 	/*
diff --git a/chip/stm32/usart_tx_dma.h b/chip/stm32/usart_tx_dma.h
index c17164e04a..f1028e3a9e 100644
--- a/chip/stm32/usart_tx_dma.h
+++ b/chip/stm32/usart_tx_dma.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -29,7 +29,7 @@
  * required because the queue isn't notified that it has been read from until
  * after the DMA transfer completes.
  */
-#define USART_TX_DMA(CHANNEL, MAX_BYTES)			\
+#define USART_TX_DMA(CHANNEL, MAX_BYTES) \
 	((struct usart_tx_dma const) {				\
 		.usart_tx = {					\
 			.consumer_ops = {			\
diff --git a/chip/stm32/usart_tx_interrupt.c b/chip/stm32/usart_tx_interrupt.c
index d8d441ba1b..80d1d4df0f 100644
--- a/chip/stm32/usart_tx_interrupt.c
+++ b/chip/stm32/usart_tx_interrupt.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -37,12 +37,11 @@ static void usart_written(struct consumer const *consumer, size_t count)
 		STM32_USART_CR1(config->hw->base) |= STM32_USART_CR1_TXEIE;
 }
 
-static void usart_tx_interrupt_handler_common(
-		struct usart_config const *config,
-		remove_data_t remove_data)
+static void usart_tx_interrupt_handler_common(struct usart_config const *config,
+					      remove_data_t remove_data)
 {
 	intptr_t base = config->hw->base;
-	uint8_t  byte;
+	uint8_t byte;
 
 	if (!(STM32_USART_SR(base) & STM32_USART_SR_TXE))
 		return;
@@ -73,7 +72,7 @@ static void usart_tx_interrupt_handler_common(
 
 static size_t queue_remove(struct usart_config const *config, uint8_t *dest)
 {
-	return queue_remove_unit(config->consumer.queue, (void *) dest);
+	return queue_remove_unit(config->consumer.queue, (void *)dest);
 }
 
 static void usart_tx_interrupt_handler(struct usart_config const *config)
@@ -107,11 +106,11 @@ struct usart_tx const usart_tx_interrupt = {
 
 #if defined(CONFIG_USART_HOST_COMMAND)
 
-static void usart_host_command_tx_interrupt_handler(
-		struct usart_config const *config)
+static void
+usart_host_command_tx_interrupt_handler(struct usart_config const *config)
 {
 	usart_tx_interrupt_handler_common(config,
-		&usart_host_command_tx_remove_data);
+					  &usart_host_command_tx_remove_data);
 }
 
 struct usart_tx const usart_host_command_tx_interrupt = {
diff --git a/chip/stm32/usb-stm32f0.c b/chip/stm32/usb-stm32f0.c
index 08c0a17455..227842f549 100644
--- a/chip/stm32/usb-stm32f0.c
+++ b/chip/stm32/usb-stm32f0.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/chip/stm32/usb-stm32f3.c b/chip/stm32/usb-stm32f3.c
index 2376d00b41..eb48129e09 100644
--- a/chip/stm32/usb-stm32f3.c
+++ b/chip/stm32/usb-stm32f3.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/chip/stm32/usb-stm32f3.h b/chip/stm32/usb-stm32f3.h
index 196c43a53a..62921fe491 100644
--- a/chip/stm32/usb-stm32f3.h
+++ b/chip/stm32/usb-stm32f3.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/chip/stm32/usb-stm32g4.c b/chip/stm32/usb-stm32g4.c
index b4402f670d..acd758584b 100644
--- a/chip/stm32/usb-stm32g4.c
+++ b/chip/stm32/usb-stm32g4.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/chip/stm32/usb-stm32l.c b/chip/stm32/usb-stm32l.c
index bb9838531b..3780dfed10 100644
--- a/chip/stm32/usb-stm32l.c
+++ b/chip/stm32/usb-stm32l.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/chip/stm32/usb-stm32l5.c b/chip/stm32/usb-stm32l5.c
index 9eaa622815..a286ab488e 100644
--- a/chip/stm32/usb-stm32l5.c
+++ b/chip/stm32/usb-stm32l5.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/stm32/usb-stream.c b/chip/stm32/usb-stream.c
index 7429832f10..76f7fbd340 100644
--- a/chip/stm32/usb-stream.c
+++ b/chip/stm32/usb-stream.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -28,19 +28,16 @@ static size_t rx_read(struct usb_stream_config const *config)
 	if (count > queue_space(config->producer.queue))
 		return 0;
 
-	return queue_add_memcpy(config->producer.queue,
-				(void *) address,
-				count,
+	return queue_add_memcpy(config->producer.queue, (void *)address, count,
 				memcpy_from_usbram);
 }
 
 static size_t tx_write(struct usb_stream_config const *config)
 {
 	uintptr_t address = btable_ep[config->endpoint].tx_addr;
-	size_t    count   = queue_remove_memcpy(config->consumer.queue,
-						(void *) address,
-						config->tx_size,
-						memcpy_to_usbram);
+	size_t count = queue_remove_memcpy(config->consumer.queue,
+					   (void *)address, config->tx_size,
+					   memcpy_to_usbram);
 
 	btable_ep[config->endpoint].tx_count = count;
 
@@ -127,36 +124,33 @@ void usb_stream_event(struct usb_stream_config const *config,
 
 	i = config->endpoint;
 
-	btable_ep[i].tx_addr  = usb_sram_addr(config->tx_ram);
+	btable_ep[i].tx_addr = usb_sram_addr(config->tx_ram);
 	btable_ep[i].tx_count = 0;
 
-	btable_ep[i].rx_addr  = usb_sram_addr(config->rx_ram);
+	btable_ep[i].rx_addr = usb_sram_addr(config->rx_ram);
 	btable_ep[i].rx_count = usb_ep_rx_size(config->rx_size);
 
 	config->state->rx_waiting = 0;
 
-	STM32_USB_EP(i) = ((i <<  0) | /* Endpoint Addr*/
-			   (2 <<  4) | /* TX NAK */
-			   (0 <<  9) | /* Bulk EP */
+	STM32_USB_EP(i) = ((i << 0) | /* Endpoint Addr*/
+			   (2 << 4) | /* TX NAK */
+			   (0 << 9) | /* Bulk EP */
 			   (rx_disabled(config) ? EP_RX_NAK : EP_RX_VALID));
 }
 
 int usb_usart_interface(struct usb_stream_config const *config,
-			struct usart_config const *usart,
-			int interface,
+			struct usart_config const *usart, int interface,
 			usb_uint *rx_buf, usb_uint *tx_buf)
 {
 	struct usb_setup_packet req;
 
 	usb_read_setup_packet(rx_buf, &req);
 
-	if (req.bmRequestType != (USB_DIR_OUT |
-				  USB_TYPE_VENDOR |
-				  USB_RECIP_INTERFACE))
+	if (req.bmRequestType !=
+	    (USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_INTERFACE))
 		return -1;
 
-	if (req.wIndex  != interface ||
-	    req.wLength != 0)
+	if (req.wIndex != interface || req.wLength != 0)
 		return -1;
 
 	switch (req.bRequest) {
diff --git a/chip/stm32/usb-stream.h b/chip/stm32/usb-stream.h
index 915d8905cd..b22ee56620 100644
--- a/chip/stm32/usb-stream.h
+++ b/chip/stm32/usb-stream.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -118,32 +118,25 @@ extern struct producer_ops const usb_stream_producer_ops;
  * BUILD_ASSERT(RX_QUEUE.unit_bytes == 1);
  * BUILD_ASSERT(TX_QUEUE.unit_bytes == 1);
  */
-#define USB_STREAM_CONFIG_FULL(NAME,					\
-			       INTERFACE,				\
-			       INTERFACE_CLASS,				\
-			       INTERFACE_SUBCLASS,			\
-			       INTERFACE_PROTOCOL,			\
-			       INTERFACE_NAME,				\
-			       ENDPOINT,				\
-			       RX_SIZE,					\
-			       TX_SIZE,					\
-			       RX_QUEUE,				\
-			       TX_QUEUE)				\
-									\
-	BUILD_ASSERT(RX_SIZE <= USB_MAX_PACKET_SIZE);			\
-	BUILD_ASSERT(TX_SIZE <= USB_MAX_PACKET_SIZE);			\
-	BUILD_ASSERT(RX_SIZE > 0);					\
-	BUILD_ASSERT(TX_SIZE > 0);					\
-	BUILD_ASSERT((RX_SIZE <   64 && (RX_SIZE & 0x01) == 0) ||	\
-		     (RX_SIZE < 1024 && (RX_SIZE & 0x1f) == 0));	\
-	BUILD_ASSERT((TX_SIZE <   64 && (TX_SIZE & 0x01) == 0) ||	\
-		     (TX_SIZE < 1024 && (TX_SIZE & 0x1f) == 0));	\
-									\
-	static usb_uint CONCAT2(NAME, _ep_rx_buffer)[RX_SIZE / 2] __usb_ram; \
-	static usb_uint CONCAT2(NAME, _ep_tx_buffer)[TX_SIZE / 2] __usb_ram; \
-	static struct usb_stream_state CONCAT2(NAME, _state);		\
-	static void CONCAT2(NAME, _deferred_)(void);			\
-	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_));			\
+#define USB_STREAM_CONFIG_FULL(NAME, INTERFACE, INTERFACE_CLASS,               \
+			       INTERFACE_SUBCLASS, INTERFACE_PROTOCOL,         \
+			       INTERFACE_NAME, ENDPOINT, RX_SIZE, TX_SIZE,     \
+			       RX_QUEUE, TX_QUEUE)                             \
+                                                                               \
+	BUILD_ASSERT(RX_SIZE <= USB_MAX_PACKET_SIZE);                          \
+	BUILD_ASSERT(TX_SIZE <= USB_MAX_PACKET_SIZE);                          \
+	BUILD_ASSERT(RX_SIZE > 0);                                             \
+	BUILD_ASSERT(TX_SIZE > 0);                                             \
+	BUILD_ASSERT((RX_SIZE < 64 && (RX_SIZE & 0x01) == 0) ||                \
+		     (RX_SIZE < 1024 && (RX_SIZE & 0x1f) == 0));               \
+	BUILD_ASSERT((TX_SIZE < 64 && (TX_SIZE & 0x01) == 0) ||                \
+		     (TX_SIZE < 1024 && (TX_SIZE & 0x1f) == 0));               \
+                                                                               \
+	static usb_uint CONCAT2(NAME, _ep_rx_buffer)[RX_SIZE / 2] __usb_ram;   \
+	static usb_uint CONCAT2(NAME, _ep_tx_buffer)[TX_SIZE / 2] __usb_ram;   \
+	static struct usb_stream_state CONCAT2(NAME, _state);                  \
+	static void CONCAT2(NAME, _deferred_)(void);                           \
+	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_));                           \
 	struct usb_stream_config const NAME = {				\
 		.state     = &CONCAT2(NAME, _state),			\
 		.endpoint  = ENDPOINT,					\
@@ -160,107 +153,80 @@ extern struct producer_ops const usb_stream_producer_ops;
 			.queue = &RX_QUEUE,				\
 			.ops   = &usb_stream_producer_ops,		\
 		},							\
-	};								\
-	const struct usb_interface_descriptor				\
-	USB_IFACE_DESC(INTERFACE) = {					\
-		.bLength            = USB_DT_INTERFACE_SIZE,		\
-		.bDescriptorType    = USB_DT_INTERFACE,			\
-		.bInterfaceNumber   = INTERFACE,			\
-		.bAlternateSetting  = 0,				\
-		.bNumEndpoints      = 2,				\
-		.bInterfaceClass    = INTERFACE_CLASS,			\
-		.bInterfaceSubClass = INTERFACE_SUBCLASS,		\
-		.bInterfaceProtocol = INTERFACE_PROTOCOL,		\
-		.iInterface         = INTERFACE_NAME,			\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 0) = {					\
-		.bLength          = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = 0x80 | ENDPOINT,			\
-		.bmAttributes     = 0x02 /* Bulk IN */,			\
-		.wMaxPacketSize   = TX_SIZE,				\
-		.bInterval        = 10,					\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 1) = {					\
-		.bLength          = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = ENDPOINT,				\
-		.bmAttributes     = 0x02 /* Bulk OUT */,		\
-		.wMaxPacketSize   = RX_SIZE,				\
-		.bInterval        = 0,					\
-	};								\
-	static void CONCAT2(NAME, _ep_tx)(void)				\
-	{								\
-		usb_stream_tx(&NAME);					\
-	}								\
-	static void CONCAT2(NAME, _ep_rx)(void)				\
-	{								\
-		usb_stream_rx(&NAME);					\
-	}								\
-	static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt)	\
-	{								\
-		usb_stream_event(&NAME, evt);				\
-	}								\
-	USB_DECLARE_EP(ENDPOINT,					\
-		       CONCAT2(NAME, _ep_tx),				\
-		       CONCAT2(NAME, _ep_rx),				\
-		       CONCAT2(NAME, _ep_event));			\
-	static void CONCAT2(NAME, _deferred_)(void)			\
-	{ usb_stream_deferred(&NAME); }
+	};                           \
+	const struct usb_interface_descriptor USB_IFACE_DESC(INTERFACE) = {    \
+		.bLength = USB_DT_INTERFACE_SIZE,                              \
+		.bDescriptorType = USB_DT_INTERFACE,                           \
+		.bInterfaceNumber = INTERFACE,                                 \
+		.bAlternateSetting = 0,                                        \
+		.bNumEndpoints = 2,                                            \
+		.bInterfaceClass = INTERFACE_CLASS,                            \
+		.bInterfaceSubClass = INTERFACE_SUBCLASS,                      \
+		.bInterfaceProtocol = INTERFACE_PROTOCOL,                      \
+		.iInterface = INTERFACE_NAME,                                  \
+	};                                                                     \
+	const struct usb_endpoint_descriptor USB_EP_DESC(INTERFACE, 0) = {     \
+		.bLength = USB_DT_ENDPOINT_SIZE,                               \
+		.bDescriptorType = USB_DT_ENDPOINT,                            \
+		.bEndpointAddress = 0x80 | ENDPOINT,                           \
+		.bmAttributes = 0x02 /* Bulk IN */,                            \
+		.wMaxPacketSize = TX_SIZE,                                     \
+		.bInterval = 10,                                               \
+	};                                                                     \
+	const struct usb_endpoint_descriptor USB_EP_DESC(INTERFACE, 1) = {     \
+		.bLength = USB_DT_ENDPOINT_SIZE,                               \
+		.bDescriptorType = USB_DT_ENDPOINT,                            \
+		.bEndpointAddress = ENDPOINT,                                  \
+		.bmAttributes = 0x02 /* Bulk OUT */,                           \
+		.wMaxPacketSize = RX_SIZE,                                     \
+		.bInterval = 0,                                                \
+	};                                                                     \
+	static void CONCAT2(NAME, _ep_tx)(void)                                \
+	{                                                                      \
+		usb_stream_tx(&NAME);                                          \
+	}                                                                      \
+	static void CONCAT2(NAME, _ep_rx)(void)                                \
+	{                                                                      \
+		usb_stream_rx(&NAME);                                          \
+	}                                                                      \
+	static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt)            \
+	{                                                                      \
+		usb_stream_event(&NAME, evt);                                  \
+	}                                                                      \
+	USB_DECLARE_EP(ENDPOINT, CONCAT2(NAME, _ep_tx), CONCAT2(NAME, _ep_rx), \
+		       CONCAT2(NAME, _ep_event));                              \
+	static void CONCAT2(NAME, _deferred_)(void)                            \
+	{                                                                      \
+		usb_stream_deferred(&NAME);                                    \
+	}
 
 /* This is a short version for declaring Google serial endpoints */
-#define USB_STREAM_CONFIG(NAME,						\
-			  INTERFACE,					\
-			  INTERFACE_NAME,				\
-			  ENDPOINT,					\
-			  RX_SIZE,					\
-			  TX_SIZE,					\
-			  RX_QUEUE,					\
-			  TX_QUEUE)					\
-	USB_STREAM_CONFIG_FULL(NAME,					\
-			       INTERFACE,				\
-			       USB_CLASS_VENDOR_SPEC,			\
-			       USB_SUBCLASS_GOOGLE_SERIAL,		\
-			       USB_PROTOCOL_GOOGLE_SERIAL,		\
-			       INTERFACE_NAME,				\
-			       ENDPOINT,				\
-			       RX_SIZE,					\
-			       TX_SIZE,					\
-			       RX_QUEUE,				\
-			       TX_QUEUE)
+#define USB_STREAM_CONFIG(NAME, INTERFACE, INTERFACE_NAME, ENDPOINT, RX_SIZE, \
+			  TX_SIZE, RX_QUEUE, TX_QUEUE)                        \
+	USB_STREAM_CONFIG_FULL(NAME, INTERFACE, USB_CLASS_VENDOR_SPEC,        \
+			       USB_SUBCLASS_GOOGLE_SERIAL,                    \
+			       USB_PROTOCOL_GOOGLE_SERIAL, INTERFACE_NAME,    \
+			       ENDPOINT, RX_SIZE, TX_SIZE, RX_QUEUE, TX_QUEUE)
 
 /* Declare a utility interface for setting parity/baud. */
-#define USB_USART_IFACE(NAME, INTERFACE, USART_CFG)			\
-	static int CONCAT2(NAME,  _interface_)(usb_uint *rx_buf,	\
-					      usb_uint *tx_buf)		\
-	{ return usb_usart_interface(&NAME, &USART_CFG, INTERFACE,	\
-					rx_buf, tx_buf); }		\
-	USB_DECLARE_IFACE(INTERFACE,					\
-			  CONCAT2(NAME, _interface_))
+#define USB_USART_IFACE(NAME, INTERFACE, USART_CFG)                      \
+	static int CONCAT2(NAME, _interface_)(usb_uint * rx_buf,         \
+					      usb_uint * tx_buf)         \
+	{                                                                \
+		return usb_usart_interface(&NAME, &USART_CFG, INTERFACE, \
+					   rx_buf, tx_buf);              \
+	}                                                                \
+	USB_DECLARE_IFACE(INTERFACE, CONCAT2(NAME, _interface_))
 
 /* This is a medium version for declaring Google serial endpoints */
-#define USB_STREAM_CONFIG_USART_IFACE(NAME,				\
-				      INTERFACE,			\
-				      INTERFACE_NAME,			\
-				      ENDPOINT,				\
-				      RX_SIZE,				\
-				      TX_SIZE,				\
-				      RX_QUEUE,				\
-				      TX_QUEUE,				\
-				      USART_CFG)			\
-	USB_STREAM_CONFIG_FULL(NAME,					\
-			       INTERFACE,				\
-			       USB_CLASS_VENDOR_SPEC,			\
-			       USB_SUBCLASS_GOOGLE_SERIAL,		\
-			       USB_PROTOCOL_GOOGLE_SERIAL,		\
-			       INTERFACE_NAME,				\
-			       ENDPOINT,				\
-			       RX_SIZE,					\
-			       TX_SIZE,					\
-			       RX_QUEUE,				\
-			       TX_QUEUE);				\
+#define USB_STREAM_CONFIG_USART_IFACE(NAME, INTERFACE, INTERFACE_NAME,      \
+				      ENDPOINT, RX_SIZE, TX_SIZE, RX_QUEUE, \
+				      TX_QUEUE, USART_CFG)                  \
+	USB_STREAM_CONFIG_FULL(NAME, INTERFACE, USB_CLASS_VENDOR_SPEC,      \
+			       USB_SUBCLASS_GOOGLE_SERIAL,                  \
+			       USB_PROTOCOL_GOOGLE_SERIAL, INTERFACE_NAME,  \
+			       ENDPOINT, RX_SIZE, TX_SIZE, RX_QUEUE,        \
+			       TX_QUEUE);                                   \
 	USB_USART_IFACE(NAME, INTERFACE, USART_CFG)
 
 /*
@@ -285,8 +251,8 @@ enum usb_usart {
 #define USB_USART_BAUD_MULTIPLIER 100
 
 int usb_usart_interface(struct usb_stream_config const *config,
-		    struct usart_config const *usart,
-		    int interface, usb_uint *rx_buf, usb_uint *tx_buf);
+			struct usart_config const *usart, int interface,
+			usb_uint *rx_buf, usb_uint *tx_buf);
 
 /*
  * These functions are used by the trampoline functions defined above to
diff --git a/chip/stm32/usb.c b/chip/stm32/usb.c
index a1f60e8906..1c621a32b3 100644
--- a/chip/stm32/usb.c
+++ b/chip/stm32/usb.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,7 +21,7 @@
 #include "usb_hw.h"
 
 /* Console output macro */
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args)
 
 #ifdef CONFIG_USB_BOS
 /* v2.10 (vs 2.00) BOS Descriptor provided */
@@ -73,11 +73,11 @@ const struct usb_config_descriptor USB_CONF_DESC(conf) = {
 	.bConfigurationValue = 1,
 	.iConfiguration = USB_STR_VERSION,
 	.bmAttributes = 0x80 /* Reserved bit */
-#ifdef CONFIG_USB_SELF_POWERED  /* bus or self powered */
-		      | 0x40
+#ifdef CONFIG_USB_SELF_POWERED /* bus or self powered */
+			| 0x40
 #endif
 #ifdef CONFIG_USB_REMOTE_WAKEUP
-		      | 0x20
+			| 0x20
 #endif
 	,
 	.bMaxPower = (CONFIG_USB_MAXPOWER_MA / 2),
@@ -85,8 +85,7 @@ const struct usb_config_descriptor USB_CONF_DESC(conf) = {
 
 const uint8_t usb_string_desc[] = {
 	4, /* Descriptor size */
-	USB_DT_STRING,
-	0x09, 0x04 /* LangID = 0x0409: U.S. English */
+	USB_DT_STRING, 0x09, 0x04 /* LangID = 0x0409: U.S. English */
 };
 
 #ifdef CONFIG_USB_MS_EXTENDED_COMPAT_ID_DESCRIPTOR
@@ -95,7 +94,8 @@ const uint8_t usb_string_desc[] = {
  * descriptor is used by Windows OS to know to request a Windows Compatible ID
  * OS Descriptor so that Windows will load the proper WINUSB driver.
  */
-const void *const usb_ms_os_string_descriptor = {USB_MS_STRING_DESC("MSFT100")};
+const void *const usb_ms_os_string_descriptor = { USB_MS_STRING_DESC(
+	"MSFT100") };
 
 /*
  * Extended Compat ID OS Feature descriptor. This descriptor is used by Windows
@@ -125,7 +125,7 @@ struct stm32_endpoint btable_ep[USB_EP_COUNT] __aligned(8) __usb_btable;
 static usb_uint ep0_buf_tx[USB_MAX_PACKET_SIZE / 2] __usb_ram;
 static usb_uint ep0_buf_rx[USB_MAX_PACKET_SIZE / 2] __usb_ram;
 
-#define EP0_BUF_TX_SRAM_ADDR ((void *) usb_sram_addr(ep0_buf_tx))
+#define EP0_BUF_TX_SRAM_ADDR ((void *)usb_sram_addr(ep0_buf_tx))
 
 static int set_addr;
 /* remaining size of descriptor data to transfer */
@@ -142,10 +142,10 @@ static int remote_wakeup_enabled;
 void usb_read_setup_packet(usb_uint *buffer, struct usb_setup_packet *packet)
 {
 	packet->bmRequestType = buffer[0] & 0xff;
-	packet->bRequest      = buffer[0] >> 8;
-	packet->wValue        = buffer[1];
-	packet->wIndex        = buffer[2];
-	packet->wLength       = buffer[3];
+	packet->bRequest = buffer[0] >> 8;
+	packet->wValue = buffer[1];
+	packet->wIndex = buffer[2];
+	packet->wLength = buffer[3];
 }
 
 struct usb_descriptor_patch {
@@ -155,8 +155,8 @@ struct usb_descriptor_patch {
 
 static struct usb_descriptor_patch desc_patches[USB_DESC_PATCH_COUNT];
 
-void set_descriptor_patch(enum usb_desc_patch_type type,
-			  const void *address, uint16_t data)
+void set_descriptor_patch(enum usb_desc_patch_type type, const void *address,
+			  uint16_t data)
 {
 	desc_patches[type].address = address;
 	desc_patches[type].data = data;
@@ -176,7 +176,8 @@ void *memcpy_to_usbram_ep0_patch(const void *src, size_t n)
 			continue;
 
 		memcpy_to_usbram((void *)(usb_sram_addr(ep0_buf_tx) + offset),
-			&desc_patches[i].data, sizeof(desc_patches[i].data));
+				 &desc_patches[i].data,
+				 sizeof(desc_patches[i].data));
 	}
 
 	return ret;
@@ -246,7 +247,7 @@ static void ep0_rx(void)
 
 #ifdef CONFIG_USB_MS_EXTENDED_COMPAT_ID_DESCRIPTOR
 		if (b_req == USB_MS_STRING_DESC_VENDOR_CODE &&
-			w_index == USB_MS_EXT_COMPATIBLE_ID_INDEX) {
+		    w_index == USB_MS_EXT_COMPATIBLE_ID_INDEX) {
 			ep0_send_descriptor((uint8_t *)&winusb_desc,
 					    winusb_desc.dwLength, 0);
 			return;
@@ -310,8 +311,9 @@ static void ep0_rx(void)
 		default: /* unhandled descriptor */
 			goto unknown_req;
 		}
-		ep0_send_descriptor(desc, len, type == USB_DT_CONFIGURATION ?
-						USB_DESC_SIZE : 0);
+		ep0_send_descriptor(
+			desc, len,
+			type == USB_DT_CONFIGURATION ? USB_DESC_SIZE : 0);
 	} else if (req == (USB_DIR_IN | (USB_REQ_GET_STATUS << 8))) {
 		uint16_t data = 0;
 		/* Get status */
@@ -325,14 +327,14 @@ static void ep0_rx(void)
 		memcpy_to_usbram(EP0_BUF_TX_SRAM_ADDR, (void *)&data, 2);
 		btable_ep[0].tx_count = 2;
 		STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID,
-			  EP_STATUS_OUT /*null OUT transaction */);
+				EP_STATUS_OUT /*null OUT transaction */);
 	} else if ((req & 0xff) == USB_DIR_OUT) {
 		switch (req >> 8) {
 		case USB_REQ_SET_FEATURE:
 		case USB_REQ_CLEAR_FEATURE:
 #ifdef CONFIG_USB_REMOTE_WAKEUP
 			if (ep0_buf_rx[1] ==
-					USB_REQ_FEATURE_DEVICE_REMOTE_WAKEUP) {
+			    USB_REQ_FEATURE_DEVICE_REMOTE_WAKEUP) {
 				remote_wakeup_enabled =
 					((req >> 8) == USB_REQ_SET_FEATURE);
 				btable_ep[0].tx_count = 0;
@@ -407,13 +409,12 @@ static void ep0_event(enum usb_ep_event evt)
 	if (evt != USB_EVENT_RESET)
 		return;
 
-	STM32_USB_EP(0) = BIT(9) /* control EP */ |
-			  (2 << 4) /* TX NAK */ |
+	STM32_USB_EP(0) = BIT(9) /* control EP */ | (2 << 4) /* TX NAK */ |
 			  (3 << 12) /* RX VALID */;
 
 	btable_ep[0].tx_addr = usb_sram_addr(ep0_buf_tx);
 	btable_ep[0].rx_addr = usb_sram_addr(ep0_buf_rx);
-	btable_ep[0].rx_count = 0x8000 | ((USB_MAX_PACKET_SIZE/32-1) << 10);
+	btable_ep[0].rx_count = 0x8000 | ((USB_MAX_PACKET_SIZE / 32 - 1) << 10);
 	btable_ep[0].tx_count = 0;
 }
 USB_DECLARE_EP(0, ep0_tx, ep0_rx, ep0_event);
@@ -473,8 +474,8 @@ static volatile int sof_received;
 
 static void usb_resume_deferred(void)
 {
-	uint32_t state = (STM32_USB_FNR & STM32_USB_FNR_RXDP_RXDM_MASK)
-		>> STM32_USB_FNR_RXDP_RXDM_SHIFT;
+	uint32_t state = (STM32_USB_FNR & STM32_USB_FNR_RXDP_RXDM_MASK) >>
+			 STM32_USB_FNR_RXDP_RXDM_SHIFT;
 
 	CPRINTF("RSMd %d %04x %d\n", state, STM32_USB_CNTR, sof_received);
 	if (sof_received == 0 && (state == 2 || state == 3))
@@ -496,8 +497,8 @@ static void usb_resume(void)
 	/* USB is in use again */
 	disable_sleep(SLEEP_MASK_USB_DEVICE);
 
-	state = (STM32_USB_FNR & STM32_USB_FNR_RXDP_RXDM_MASK)
-		>> STM32_USB_FNR_RXDP_RXDM_SHIFT;
+	state = (STM32_USB_FNR & STM32_USB_FNR_RXDP_RXDM_MASK) >>
+		STM32_USB_FNR_RXDP_RXDM_SHIFT;
 
 	CPRINTF("RSM %d %04x\n", state, STM32_USB_CNTR);
 
@@ -534,8 +535,7 @@ static volatile int usb_wake_done = 1;
  */
 static volatile int esof_count;
 
-__attribute__((weak))
-void board_usb_wake(void)
+__attribute__((weak)) void board_usb_wake(void)
 {
 	/* Side-band USB wake, do nothing by default. */
 }
@@ -598,8 +598,8 @@ void usb_wake(void)
 
 	/* STM32_USB_CNTR can also be updated from interrupt context. */
 	interrupt_disable();
-	STM32_USB_CNTR |= STM32_USB_CNTR_RESUME |
-		STM32_USB_CNTR_ESOFM | STM32_USB_CNTR_SOFM;
+	STM32_USB_CNTR |= STM32_USB_CNTR_RESUME | STM32_USB_CNTR_ESOFM |
+			  STM32_USB_CNTR_SOFM;
 	interrupt_enable();
 
 	/* Try side-band wake as well. */
@@ -654,8 +654,8 @@ static void usb_interrupt_handle_wake(uint16_t status)
 		STM32_USB_CNTR &= ~STM32_USB_CNTR_RESUME;
 
 	/* Then count down until state is resumed. */
-	state = (STM32_USB_FNR & STM32_USB_FNR_RXDP_RXDM_MASK)
-				>> STM32_USB_FNR_RXDP_RXDM_SHIFT;
+	state = (STM32_USB_FNR & STM32_USB_FNR_RXDP_RXDM_MASK) >>
+		STM32_USB_FNR_RXDP_RXDM_SHIFT;
 
 	/*
 	 * state 2, or receiving an SOF, means resume
@@ -670,13 +670,13 @@ static void usb_interrupt_handle_wake(uint16_t status)
 		STM32_USB_CNTR &= ~STM32_USB_CNTR_ESOFM;
 		usb_wake_done = 1;
 		if (!good) {
-			CPRINTF("wake error: cnt=%d state=%d\n",
-				esof_count, state);
+			CPRINTF("wake error: cnt=%d state=%d\n", esof_count,
+				state);
 			usb_suspend();
 			return;
 		}
 
-		CPRINTF("RSMOK%d %d\n",	-esof_count, state);
+		CPRINTF("RSMOK%d %d\n", -esof_count, state);
 
 		for (ep = 1; ep < USB_EP_COUNT; ep++)
 			usb_ep_event[ep](USB_EVENT_DEVICE_RESUME);
@@ -703,7 +703,7 @@ static void usb_interrupt(void)
 
 #ifdef CONFIG_USB_REMOTE_WAKEUP
 	if (status & (STM32_USB_ISTR_ESOF | STM32_USB_ISTR_SOF) &&
-			!usb_wake_done)
+	    !usb_wake_done)
 		usb_interrupt_handle_wake(status);
 #endif
 
@@ -759,12 +759,10 @@ void usb_init(void)
 	/* Enable interrupt handlers */
 	task_enable_irq(STM32_IRQ_USB_LP);
 	/* set interrupts mask : reset/correct transfer/errors */
-	STM32_USB_CNTR = STM32_USB_CNTR_CTRM |
-			 STM32_USB_CNTR_PMAOVRM |
+	STM32_USB_CNTR = STM32_USB_CNTR_CTRM | STM32_USB_CNTR_PMAOVRM |
 			 STM32_USB_CNTR_ERRM |
 #ifdef CONFIG_USB_SUSPEND
-			 STM32_USB_CNTR_WKUPM |
-			 STM32_USB_CNTR_SUSPM |
+			 STM32_USB_CNTR_WKUPM | STM32_USB_CNTR_SUSPM |
 #endif
 			 STM32_USB_CNTR_RESETM;
 
@@ -809,10 +807,10 @@ int usb_is_enabled(void)
 
 void *memcpy_to_usbram(void *dest, const void *src, size_t n)
 {
-	int       unaligned =                 (((uintptr_t) dest) & 1);
-	usb_uint *d         = &__usb_ram_start[((uintptr_t) dest) / 2];
-	uint8_t  *s         = (uint8_t *) src;
-	int       i;
+	int unaligned = (((uintptr_t)dest) & 1);
+	usb_uint *d = &__usb_ram_start[((uintptr_t)dest) / 2];
+	uint8_t *s = (uint8_t *)src;
+	int i;
 
 	/*
 	 * Handle unaligned leading byte via read/modify/write.
@@ -839,10 +837,10 @@ void *memcpy_to_usbram(void *dest, const void *src, size_t n)
 
 void *memcpy_from_usbram(void *dest, const void *src, size_t n)
 {
-	int             unaligned =                 (((uintptr_t) src) & 1);
-	usb_uint const *s         = &__usb_ram_start[((uintptr_t) src) / 2];
-	uint8_t        *d         = (uint8_t *) dest;
-	int             i;
+	int unaligned = (((uintptr_t)src) & 1);
+	usb_uint const *s = &__usb_ram_start[((uintptr_t)src) / 2];
+	uint8_t *d = (uint8_t *)dest;
+	int i;
 
 	if (unaligned && n) {
 		*d = *s >> 8;
@@ -923,7 +921,7 @@ static int usb_save_serial(const char *serialno)
 	return rv;
 }
 
-static int command_serialno(int argc, char **argv)
+static int command_serialno(int argc, const char **argv)
 {
 	struct usb_string_desc *sd = usb_serialno_desc;
 	char buf[CONFIG_SERIALNO_LEN];
@@ -931,12 +929,10 @@ static int command_serialno(int argc, char **argv)
 	int i;
 
 	if (argc != 1) {
-		if ((strcasecmp(argv[1], "set") == 0) &&
-		    (argc == 3)) {
+		if ((strcasecmp(argv[1], "set") == 0) && (argc == 3)) {
 			ccprintf("Saving serial number\n");
 			rv = usb_save_serial(argv[2]);
-		} else if ((strcasecmp(argv[1], "load") == 0) &&
-			   (argc == 2)) {
+		} else if ((strcasecmp(argv[1], "load") == 0) && (argc == 2)) {
 			ccprintf("Loading serial number\n");
 			rv = usb_load_serial();
 		} else
@@ -949,11 +945,10 @@ static int command_serialno(int argc, char **argv)
 	return rv;
 }
 
-DECLARE_CONSOLE_COMMAND(serialno, command_serialno,
-	"load/set [value]",
-	"Read and write USB serial number");
+DECLARE_CONSOLE_COMMAND(serialno, command_serialno, "load/set [value]",
+			"Read and write USB serial number");
 
-#endif  /* CONFIG_USB_SERIALNO */
+#endif /* CONFIG_USB_SERIALNO */
 
 #ifdef CONFIG_MAC_ADDR
 
@@ -980,18 +975,16 @@ static int usb_save_mac_addr(const char *mac_addr)
 	}
 }
 
-static int command_macaddr(int argc, char **argv)
+static int command_macaddr(int argc, const char **argv)
 {
-	const char* buf;
+	const char *buf;
 	int rv = EC_SUCCESS;
 
 	if (argc != 1) {
-		if ((strcasecmp(argv[1], "set") == 0) &&
-		    (argc == 3)) {
+		if ((strcasecmp(argv[1], "set") == 0) && (argc == 3)) {
 			ccprintf("Saving MAC address\n");
 			rv = usb_save_mac_addr(argv[2]);
-		} else if ((strcasecmp(argv[1], "load") == 0) &&
-			   (argc == 2)) {
+		} else if ((strcasecmp(argv[1], "load") == 0) && (argc == 2)) {
 			ccprintf("Loading MAC address\n");
 		} else {
 			return EC_ERROR_INVAL;
@@ -1006,8 +999,7 @@ static int command_macaddr(int argc, char **argv)
 	return rv;
 }
 
-DECLARE_CONSOLE_COMMAND(macaddr, command_macaddr,
-	"load/set [value]",
-	"Read and write MAC address");
+DECLARE_CONSOLE_COMMAND(macaddr, command_macaddr, "load/set [value]",
+			"Read and write MAC address");
 
-#endif  /* CONFIG_MAC_ADDR */
+#endif /* CONFIG_MAC_ADDR */
diff --git a/chip/stm32/usb_console.c b/chip/stm32/usb_console.c
index b5666c8fbf..fdadc243c1 100644
--- a/chip/stm32/usb_console.c
+++ b/chip/stm32/usb_console.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,11 +18,11 @@
 #include "usb_hw.h"
 
 /* Console output macro */
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args)
 #define USB_CONSOLE_TIMEOUT_US (30 * MSEC)
 
-static struct queue const tx_q = QUEUE_NULL(CONFIG_USB_CONSOLE_TX_BUF_SIZE,
-					    uint8_t);
+static struct queue const tx_q =
+	QUEUE_NULL(CONFIG_USB_CONSOLE_TX_BUF_SIZE, uint8_t);
 static struct queue const rx_q = QUEUE_NULL(USB_MAX_PACKET_SIZE, uint8_t);
 
 static int last_tx_ok = 1;
@@ -33,31 +33,31 @@ static int is_readonly;
 
 /* USB-Serial descriptors */
 const struct usb_interface_descriptor USB_IFACE_DESC(USB_IFACE_CONSOLE) = {
-	.bLength            = USB_DT_INTERFACE_SIZE,
-	.bDescriptorType    = USB_DT_INTERFACE,
-	.bInterfaceNumber   = USB_IFACE_CONSOLE,
-	.bAlternateSetting  = 0,
-	.bNumEndpoints      = 2,
-	.bInterfaceClass    = USB_CLASS_VENDOR_SPEC,
+	.bLength = USB_DT_INTERFACE_SIZE,
+	.bDescriptorType = USB_DT_INTERFACE,
+	.bInterfaceNumber = USB_IFACE_CONSOLE,
+	.bAlternateSetting = 0,
+	.bNumEndpoints = 2,
+	.bInterfaceClass = USB_CLASS_VENDOR_SPEC,
 	.bInterfaceSubClass = USB_SUBCLASS_GOOGLE_SERIAL,
 	.bInterfaceProtocol = USB_PROTOCOL_GOOGLE_SERIAL,
-	.iInterface         = USB_STR_CONSOLE_NAME,
+	.iInterface = USB_STR_CONSOLE_NAME,
 };
 const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_CONSOLE, 0) = {
-	.bLength            = USB_DT_ENDPOINT_SIZE,
-	.bDescriptorType    = USB_DT_ENDPOINT,
-	.bEndpointAddress   = 0x80 | USB_EP_CONSOLE,
-	.bmAttributes       = 0x02 /* Bulk IN */,
-	.wMaxPacketSize     = USB_MAX_PACKET_SIZE,
-	.bInterval          = 10
+	.bLength = USB_DT_ENDPOINT_SIZE,
+	.bDescriptorType = USB_DT_ENDPOINT,
+	.bEndpointAddress = 0x80 | USB_EP_CONSOLE,
+	.bmAttributes = 0x02 /* Bulk IN */,
+	.wMaxPacketSize = USB_MAX_PACKET_SIZE,
+	.bInterval = 10
 };
 const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_CONSOLE, 1) = {
-	.bLength            = USB_DT_ENDPOINT_SIZE,
-	.bDescriptorType    = USB_DT_ENDPOINT,
-	.bEndpointAddress   = USB_EP_CONSOLE,
-	.bmAttributes       = 0x02 /* Bulk OUT */,
-	.wMaxPacketSize     = USB_MAX_PACKET_SIZE,
-	.bInterval          = 0
+	.bLength = USB_DT_ENDPOINT_SIZE,
+	.bDescriptorType = USB_DT_ENDPOINT,
+	.bEndpointAddress = USB_EP_CONSOLE,
+	.bmAttributes = 0x02 /* Bulk OUT */,
+	.wMaxPacketSize = USB_MAX_PACKET_SIZE,
+	.bInterval = 0
 };
 
 static usb_uint ep_buf_tx[USB_MAX_PACKET_SIZE / 2] __usb_ram;
@@ -81,9 +81,8 @@ static void con_ep_rx(void)
 
 	for (i = 0; i < (btable_ep[USB_EP_CONSOLE].rx_count & RX_COUNT_MASK);
 	     i++) {
-		int val = ((i & 1) ?
-			   (ep_buf_rx[i >> 1] >> 8) :
-			   (ep_buf_rx[i >> 1] & 0xff));
+		int val = ((i & 1) ? (ep_buf_rx[i >> 1] >> 8) :
+				     (ep_buf_rx[i >> 1] & 0xff));
 
 		QUEUE_ADD_UNITS(&rx_q, &val, 1);
 	}
@@ -100,18 +99,18 @@ static void ep_event(enum usb_ep_event evt)
 	if (evt != USB_EVENT_RESET)
 		return;
 
-	btable_ep[USB_EP_CONSOLE].tx_addr  = usb_sram_addr(ep_buf_tx);
+	btable_ep[USB_EP_CONSOLE].tx_addr = usb_sram_addr(ep_buf_tx);
 	btable_ep[USB_EP_CONSOLE].tx_count = 0;
 
-	btable_ep[USB_EP_CONSOLE].rx_addr  = usb_sram_addr(ep_buf_rx);
+	btable_ep[USB_EP_CONSOLE].rx_addr = usb_sram_addr(ep_buf_rx);
 	btable_ep[USB_EP_CONSOLE].rx_count =
 		0x8000 | ((USB_MAX_PACKET_SIZE / 32 - 1) << 10);
 
-	STM32_USB_EP(USB_EP_CONSOLE) = (USB_EP_CONSOLE | /* Endpoint Addr */
-					(2 << 4)       | /* TX NAK        */
-					(0 << 9)       | /* Bulk EP       */
-					(is_readonly ? EP_RX_NAK
-						     : EP_RX_VALID));
+	STM32_USB_EP(USB_EP_CONSOLE) =
+		(USB_EP_CONSOLE | /* Endpoint Addr */
+		 (2 << 4) | /* TX NAK        */
+		 (0 << 9) | /* Bulk EP       */
+		 (is_readonly ? EP_RX_NAK : EP_RX_VALID));
 
 	is_reset = 1;
 }
@@ -201,9 +200,9 @@ static void tx_fifo_handler(void)
 			break;
 
 		if (!(count & 1))
-			buf[count/2] = val;
+			buf[count / 2] = val;
 		else
-			buf[count/2] |= val << 8;
+			buf[count / 2] |= val << 8;
 		count++;
 	}
 
diff --git a/chip/stm32/usb_dfu_runtime.c b/chip/stm32/usb_dfu_runtime.c
index 7626faec8e..92e152078b 100644
--- a/chip/stm32/usb_dfu_runtime.c
+++ b/chip/stm32/usb_dfu_runtime.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,15 +23,15 @@ const struct usb_interface_descriptor USB_IFACE_DESC(USB_IFACE_DFU) = {
 };
 
 /* DFU Functional Descriptor. */
-const struct usb_runtime_dfu_functional_desc USB_CUSTOM_DESC_VAR(USB_IFACE_DFU,
-						dfu, dfu_func_desc) = {
-	.bLength = USB_DFU_RUNTIME_DESC_SIZE,
-	.bDescriptorType = USB_DFU_RUNTIME_DESC_FUNCTIONAL,
-	.bmAttributes = USB_DFU_RUNTIME_DESC_ATTRS,
-	.wDetachTimeOut = USB_DFU_RUNTIME_DESC_DETACH_TIMEOUT,
-	.wTransferSize = USB_DFU_RUNTIME_DESC_TRANSFER_SIZE,
-	.bcdDFUVersion = USB_DFU_RUNTIME_DESC_DFU_VERSION,
-};
+const struct usb_runtime_dfu_functional_desc
+	USB_CUSTOM_DESC_VAR(USB_IFACE_DFU, dfu, dfu_func_desc) = {
+		.bLength = USB_DFU_RUNTIME_DESC_SIZE,
+		.bDescriptorType = USB_DFU_RUNTIME_DESC_FUNCTIONAL,
+		.bmAttributes = USB_DFU_RUNTIME_DESC_ATTRS,
+		.wDetachTimeOut = USB_DFU_RUNTIME_DESC_DETACH_TIMEOUT,
+		.wTransferSize = USB_DFU_RUNTIME_DESC_TRANSFER_SIZE,
+		.bcdDFUVersion = USB_DFU_RUNTIME_DESC_DFU_VERSION,
+	};
 
 static int dfu_runtime_request(usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx)
 {
@@ -40,21 +40,21 @@ static int dfu_runtime_request(usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx)
 	usb_read_setup_packet(ep0_buf_rx, &packet);
 	btable_ep[0].tx_count = 0;
 	if ((packet.bmRequestType ==
-		(USB_DIR_OUT | USB_TYPE_STANDARD |  USB_RECIP_INTERFACE)) &&
-		(packet.bRequest == USB_REQ_SET_INTERFACE)) {
+	     (USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE)) &&
+	    (packet.bRequest == USB_REQ_SET_INTERFACE)) {
 		/* ACK the change alternative mode request. */
 
 		STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0);
 		return 0;
 	} else if ((packet.bmRequestType ==
-			(USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_INTERFACE)) &&
-			(packet.bRequest == USB_DFU_RUNTIME_REQ_DETACH)) {
+		    (USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_INTERFACE)) &&
+		   (packet.bRequest == USB_DFU_RUNTIME_REQ_DETACH)) {
 		/* Host is requesting a jump from application to DFU mode. */
 
 		STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0);
 		return dfu_bootmanager_enter_dfu();
 	} else if (packet.bmRequestType ==
-			(USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_INTERFACE)) {
+		   (USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_INTERFACE)) {
 		if (packet.bRequest == USB_DFU_RUNTIME_REQ_GET_STATUS) {
 			/* Return the Get Status response. */
 
@@ -63,8 +63,8 @@ static int dfu_runtime_request(usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx)
 				.bState = USB_DFU_RUNTIME_STATE_APP_IDLE,
 			};
 
-			memcpy_to_usbram((void *) usb_sram_addr(ep0_buf_tx),
-				&response, sizeof(response));
+			memcpy_to_usbram((void *)usb_sram_addr(ep0_buf_tx),
+					 &response, sizeof(response));
 			btable_ep[0].tx_count = sizeof(response);
 			STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0);
 			return 0;
@@ -76,8 +76,8 @@ static int dfu_runtime_request(usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx)
 				.bState = USB_DFU_RUNTIME_STATE_APP_IDLE,
 			};
 
-			memcpy_to_usbram((void *) usb_sram_addr(ep0_buf_tx),
-				&response, sizeof(response));
+			memcpy_to_usbram((void *)usb_sram_addr(ep0_buf_tx),
+					 &response, sizeof(response));
 			btable_ep[0].tx_count = sizeof(response);
 			STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0);
 			return 0;
diff --git a/chip/stm32/usb_dfu_runtime.h b/chip/stm32/usb_dfu_runtime.h
index 08781d77b0..8b0bbbe219 100644
--- a/chip/stm32/usb_dfu_runtime.h
+++ b/chip/stm32/usb_dfu_runtime.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,47 +12,46 @@
  * https://www.usb.org/sites/default/files/DFU_1.1.pdf
  */
 
-#define USB_DFU_RUNTIME_SUBCLASS    0x01
-#define USB_DFU_RUNTIME_PROTOCOL    0x01
+#define USB_DFU_RUNTIME_SUBCLASS 0x01
+#define USB_DFU_RUNTIME_PROTOCOL 0x01
 
-#define USB_DFU_RUNTIME_DESC_ATTR_CAN_DOWNLOAD       BIT(0)
-#define USB_DFU_RUNTIME_DESC_ATTR_CAN_UPLOAD         BIT(1)
-#define USB_DFU_RUNTIME_DESC_ATTR_MANIFEST_TOLERANT  BIT(2)
-#define USB_DFU_RUNTIME_DESC_ATTR_WILL_DETACH        BIT(3)
+#define USB_DFU_RUNTIME_DESC_ATTR_CAN_DOWNLOAD BIT(0)
+#define USB_DFU_RUNTIME_DESC_ATTR_CAN_UPLOAD BIT(1)
+#define USB_DFU_RUNTIME_DESC_ATTR_MANIFEST_TOLERANT BIT(2)
+#define USB_DFU_RUNTIME_DESC_ATTR_WILL_DETACH BIT(3)
 
-#define USB_DFU_RUNTIME_DESC_ATTRS \
+#define USB_DFU_RUNTIME_DESC_ATTRS                \
 	(USB_DFU_RUNTIME_DESC_ATTR_CAN_DOWNLOAD | \
-	USB_DFU_RUNTIME_DESC_ATTR_CAN_UPLOAD | \
-	USB_DFU_RUNTIME_DESC_ATTR_WILL_DETACH)
+	 USB_DFU_RUNTIME_DESC_ATTR_CAN_UPLOAD |   \
+	 USB_DFU_RUNTIME_DESC_ATTR_WILL_DETACH)
 
-#define USB_DFU_RUNTIME_DESC_SIZE            9
-#define USB_DFU_RUNTIME_DESC_FUNCTIONAL      0x21
-#define USB_DFU_RUNTIME_DESC_DETACH_TIMEOUT  0xffff
-#define USB_DFU_RUNTIME_DESC_TRANSFER_SIZE   64
-#define USB_DFU_RUNTIME_DESC_DFU_VERSION     0x0022
+#define USB_DFU_RUNTIME_DESC_SIZE 9
+#define USB_DFU_RUNTIME_DESC_FUNCTIONAL 0x21
+#define USB_DFU_RUNTIME_DESC_DETACH_TIMEOUT 0xffff
+#define USB_DFU_RUNTIME_DESC_TRANSFER_SIZE 64
+#define USB_DFU_RUNTIME_DESC_DFU_VERSION 0x0022
 
 /* DFU states */
-#define USB_DFU_RUNTIME_STATE_APP_IDLE      0
-#define USB_DFU_RUNTIME_STATE_APP_DETACH    1
+#define USB_DFU_RUNTIME_STATE_APP_IDLE 0
+#define USB_DFU_RUNTIME_STATE_APP_DETACH 1
 
 /* DFU status */
-#define USB_DFU_RUNTIME_STATUS_OK           0
+#define USB_DFU_RUNTIME_STATUS_OK 0
 
 /* DFU Request types */
-#define USB_DFU_RUNTIME_REQ_DETACH          0
-#define USB_DFU_RUNTIME_REQ_DNLOAD          1
-#define USB_DFU_RUNTIME_REQ_UPLOAD          2
-#define USB_DFU_RUNTIME_REQ_GET_STATUS      3
-#define USB_DFU_RUNTIME_REQ_CLR_STATUS      4
-#define USB_DFU_RUNTIME_REQ_GET_STATE       5
-#define USB_DFU_RUNTIME_REQ_ABORT           6
-
+#define USB_DFU_RUNTIME_REQ_DETACH 0
+#define USB_DFU_RUNTIME_REQ_DNLOAD 1
+#define USB_DFU_RUNTIME_REQ_UPLOAD 2
+#define USB_DFU_RUNTIME_REQ_GET_STATUS 3
+#define USB_DFU_RUNTIME_REQ_CLR_STATUS 4
+#define USB_DFU_RUNTIME_REQ_GET_STATE 5
+#define USB_DFU_RUNTIME_REQ_ABORT 6
 
 /* DFU Functional Descriptor  */
 struct usb_runtime_dfu_functional_desc {
-	uint8_t  bLength;
-	uint8_t  bDescriptorType;
-	uint8_t  bmAttributes;
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	uint8_t bmAttributes;
 	uint16_t wDetachTimeOut;
 	uint16_t wTransferSize;
 	uint16_t bcdDFUVersion;
diff --git a/chip/stm32/usb_dwc.c b/chip/stm32/usb_dwc.c
index 0028806432..67f89a5222 100644
--- a/chip/stm32/usb_dwc.c
+++ b/chip/stm32/usb_dwc.c
@@ -1,8 +1,9 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "builtin/assert.h"
 #include "clock.h"
 #include "common.h"
 #include "config.h"
@@ -20,19 +21,17 @@
 #include "usb_descriptor.h"
 #include "watchdog.h"
 
-
 /****************************************************************************/
 /* Debug output */
 
 /* Console output macro */
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USB, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args)
 
 /* TODO: Something unexpected happened. Figure out how to report & fix it. */
-#define report_error(val)						\
-	CPRINTS("Unhandled USB event at %s line %d: 0x%x",		\
-		__FILE__, __LINE__, val)
-
+#define report_error(val)                                                      \
+	CPRINTS("Unhandled USB event at %s line %d: 0x%x", __FILE__, __LINE__, \
+		val)
 
 /****************************************************************************/
 /* Standard USB stuff */
@@ -49,7 +48,7 @@
 #endif
 
 #ifndef CONFIG_USB_BCD_DEV
-#define CONFIG_USB_BCD_DEV 0x0100		/* 1.00 */
+#define CONFIG_USB_BCD_DEV 0x0100 /* 1.00 */
 #endif
 
 #ifndef CONFIG_USB_SERIALNO
@@ -58,7 +57,6 @@
 static int usb_load_serial(void);
 #endif
 
-
 /* USB Standard Device Descriptor */
 static const struct usb_device_descriptor dev_desc = {
 	.bLength = USB_DT_DEVICE_SIZE,
@@ -81,25 +79,24 @@ static const struct usb_device_descriptor dev_desc = {
 const struct usb_config_descriptor USB_CONF_DESC(conf) = {
 	.bLength = USB_DT_CONFIG_SIZE,
 	.bDescriptorType = USB_DT_CONFIGURATION,
-	.wTotalLength = 0x0BAD,	 /* number of returned bytes, set at runtime */
+	.wTotalLength = 0x0BAD, /* number of returned bytes, set at runtime */
 	.bNumInterfaces = USB_IFACE_COUNT,
-	.bConfigurationValue = 1,		/* Caution: hard-coded value */
+	.bConfigurationValue = 1, /* Caution: hard-coded value */
 	.iConfiguration = USB_STR_VERSION,
 	.bmAttributes = 0x80 /* Reserved bit */
-#ifdef CONFIG_USB_SELF_POWERED  /* bus or self powered */
-		      | 0x40
+#ifdef CONFIG_USB_SELF_POWERED /* bus or self powered */
+			| 0x40
 #endif
 #ifdef CONFIG_USB_REMOTE_WAKEUP
-		      | 0x20
+			| 0x20
 #endif
 	,
 	.bMaxPower = (CONFIG_USB_MAXPOWER_MA / 2),
 };
 
 const uint8_t usb_string_desc[] = {
-	4,					/* Descriptor size */
-	USB_DT_STRING,
-	0x09, 0x04			    /* LangID = 0x0409: U.S. English */
+	4, /* Descriptor size */
+	USB_DT_STRING, 0x09, 0x04 /* LangID = 0x0409: U.S. English */
 };
 
 /****************************************************************************/
@@ -113,7 +110,7 @@ static enum {
 } what_am_i_doing;
 
 #ifdef DEBUG_ME
-static const char * const wat[3] = {
+static const char *const wat[3] = {
 	[WAITING_FOR_SETUP_PACKET] = "wait_for_setup",
 	[DATA_STAGE_IN] = "data_in",
 	[NO_DATA_STAGE] = "no_data",
@@ -182,7 +179,6 @@ static enum {
 } device_state;
 static uint8_t configuration_value;
 
-
 /* True if the HW Rx/OUT FIFO is currently listening. */
 int rx_ep_is_active(uint32_t ep_num)
 {
@@ -326,10 +322,9 @@ void usb_epN_rx(uint32_t ep_num)
 	/* Bytes received decrement DOEPTSIZ XFERSIZE */
 	if (GR_USB_DOEPINT(ep_num) & DOEPINT_XFERCOMPL) {
 		if (ep->out_expected > 0) {
-			ep->out_pending =
-				ep->out_expected -
-				(GR_USB_DOEPTSIZ(ep_num) &
-				 GC_USB_DOEPTSIZ1_XFERSIZE_MASK);
+			ep->out_pending = ep->out_expected -
+					  (GR_USB_DOEPTSIZ(ep_num) &
+					   GC_USB_DOEPTSIZ1_XFERSIZE_MASK);
 		} else {
 			CPRINTF("usb_ep%d_rx: unexpected RX DOEPTSIZ %08x\n",
 				ep_num, GR_USB_DOEPTSIZ(ep_num));
@@ -350,25 +345,22 @@ void usb_epN_rx(uint32_t ep_num)
 void epN_reset(uint32_t ep_num)
 {
 	GR_USB_DOEPCTL(ep_num) = DXEPCTL_MPS(USB_MAX_PACKET_SIZE) |
-		DXEPCTL_USBACTEP | DXEPCTL_EPTYPE_BULK;
+				 DXEPCTL_USBACTEP | DXEPCTL_EPTYPE_BULK;
 	GR_USB_DIEPCTL(ep_num) = DXEPCTL_MPS(USB_MAX_PACKET_SIZE) |
-		DXEPCTL_USBACTEP | DXEPCTL_EPTYPE_BULK |
-		DXEPCTL_TXFNUM(ep_num);
-	GR_USB_DAINTMSK |= DAINT_INEP(ep_num) |
-			   DAINT_OUTEP(ep_num);
+				 DXEPCTL_USBACTEP | DXEPCTL_EPTYPE_BULK |
+				 DXEPCTL_TXFNUM(ep_num);
+	GR_USB_DAINTMSK |= DAINT_INEP(ep_num) | DAINT_OUTEP(ep_num);
 }
 
-
 /******************************************************************************
  * Internal and EP0 functions.
  */
 
-
 static void flush_all_fifos(void)
 {
 	/* Flush all FIFOs according to Section 2.1.1.2 */
-	GR_USB_GRSTCTL = GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH
-		| GRSTCTL_RXFFLSH;
+	GR_USB_GRSTCTL = GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
+			 GRSTCTL_RXFFLSH;
 	while (GR_USB_GRSTCTL & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH))
 		;
 }
@@ -390,7 +382,6 @@ int send_in_packet(uint32_t ep_num)
 	GR_USB_DIEPTSIZ(0) |= DXEPTSIZ_XFERSIZE(len);
 	GR_USB_DIEPDMA(0) = (uint32_t)ep->in_data;
 
-
 	/* We're sending this much. */
 	ep->in_pending -= len;
 	ep->in_packets -= 1;
@@ -400,7 +391,6 @@ int send_in_packet(uint32_t ep_num)
 	return len;
 }
 
-
 /* Load the EP0 IN FIFO buffer with some data (zero-length works too). Returns
  * len, or negative on error.
  */
@@ -418,7 +408,7 @@ int initialize_in_transfer(const void *source, uint32_t len)
 #else
 	/* HS OTG port requires an external phy to support HS */
 	ASSERT(!((usb->phy_type == USB_PHY_INTERNAL) &&
-		(usb->speed == USB_SPEED_HS)));
+		 (usb->speed == USB_SPEED_HS)));
 	ASSERT(usb->irq == STM32_IRQ_OTG_HS);
 #endif
 
@@ -435,7 +425,7 @@ int initialize_in_transfer(const void *source, uint32_t len)
 	/* We will send as many packets as necessary, including a final
 	 * packet of < USB_MAX_PACKET_SIZE (maybe zero length)
 	 */
-	ep->in_packets = (len + USB_MAX_PACKET_SIZE)/USB_MAX_PACKET_SIZE;
+	ep->in_packets = (len + USB_MAX_PACKET_SIZE) / USB_MAX_PACKET_SIZE;
 	ep->in_pending = len;
 
 	send_in_packet(0);
@@ -495,8 +485,8 @@ static void expect_data_phase_in(enum table_case tc)
 
 	/* Send the reply (data phase in) */
 	if (tc == TABLE_CASE_SETUP)
-		GR_USB_DIEPCTL(0) |= DXEPCTL_USBACTEP |
-					DXEPCTL_CNAK | DXEPCTL_EPENA;
+		GR_USB_DIEPCTL(0) |= DXEPCTL_USBACTEP | DXEPCTL_CNAK |
+				     DXEPCTL_EPENA;
 	else
 		GR_USB_DIEPCTL(0) |= DXEPCTL_EPENA;
 
@@ -508,7 +498,6 @@ static void expect_data_phase_in(enum table_case tc)
 
 	/* Get an interrupt when either IN or OUT arrives */
 	GR_USB_DAINTMSK |= (DAINT_OUTEP(0) | DAINT_INEP(0));
-
 }
 
 static void expect_data_phase_out(enum table_case tc)
@@ -524,12 +513,12 @@ static void expect_status_phase_in(enum table_case tc)
 	what_am_i_doing = NO_DATA_STAGE;
 
 	/* Expect a zero-length IN for the Status phase */
-	(void) initialize_in_transfer(0, 0);
+	(void)initialize_in_transfer(0, 0);
 
 	/* Blindly following instructions here, too. */
 	if (tc == TABLE_CASE_SETUP)
-		GR_USB_DIEPCTL(0) |= DXEPCTL_USBACTEP
-			| DXEPCTL_CNAK | DXEPCTL_EPENA;
+		GR_USB_DIEPCTL(0) |= DXEPCTL_USBACTEP | DXEPCTL_CNAK |
+				     DXEPCTL_EPENA;
 	else
 		GR_USB_DIEPCTL(0) |= DXEPCTL_EPENA;
 
@@ -549,7 +538,7 @@ static int handle_setup_with_in_stage(enum table_case tc,
 	const void *data = 0;
 	uint32_t len = 0;
 	int ugly_hack = 0;
-	static const uint16_t zero;		/* == 0 */
+	static const uint16_t zero; /* == 0 */
 
 	switch (req->bRequest) {
 	case USB_REQ_GET_DESCRIPTOR: {
@@ -564,7 +553,7 @@ static int handle_setup_with_in_stage(enum table_case tc,
 		case USB_DT_CONFIGURATION:
 			data = __usb_desc;
 			len = USB_DESC_SIZE;
-			ugly_hack = 1;		/* see below */
+			ugly_hack = 1; /* see below */
 			break;
 #ifdef CONFIG_USB_BOS
 		case USB_DT_BOS:
@@ -657,7 +646,7 @@ static int handle_setup_with_in_stage(enum table_case tc,
 
 /* Handle a Setup that comes with additional data for us. */
 static int handle_setup_with_out_stage(enum table_case tc,
-					struct usb_setup_packet *req)
+				       struct usb_setup_packet *req)
 {
 	/* TODO: We don't support any of these. We should. */
 	report_error(-1);
@@ -720,7 +709,7 @@ static int handle_setup_with_no_data_stage(enum table_case tc,
 			configuration_value = req->wValue;
 			device_state = DS_ADDRESS;
 			break;
-		case 1:	    /* Caution: Only one config descriptor TODAY */
+		case 1: /* Caution: Only one config descriptor TODAY */
 			/* TODO: All endpoints set to DATA0 toggle state */
 			configuration_value = req->wValue;
 			device_state = DS_CONFIGURED;
@@ -756,7 +745,7 @@ static void handle_setup(enum table_case tc)
 		(struct usb_setup_packet *)ep->out_databuffer;
 	int data_phase_in = req->bmRequestType & USB_DIR_IN;
 	int data_phase_out = !data_phase_in && req->wLength;
-	int bytes = -1;				/* default is to stall */
+	int bytes = -1; /* default is to stall */
 
 	if (0 == (req->bmRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))) {
 		/* Standard Device requests */
@@ -900,20 +889,20 @@ static void ep0_interrupt(uint32_t intr_on_out, uint32_t intr_on_in)
  * We support up to 3 control EPs, no periodic IN EPs, up to 16 TX EPs. Max
  * data packet size is 64 bytes. Total SPRAM available is 1024 slots.
  */
-#define MAX_CONTROL_EPS   3
-#define MAX_NORMAL_EPS    16
-#define FIFO_RAM_DEPTH    1024
+#define MAX_CONTROL_EPS 3
+#define MAX_NORMAL_EPS 16
+#define FIFO_RAM_DEPTH 1024
 /*
  * Device RX FIFO size is thus:
  *   (4 * 3 + 6) + 2 * ((64 / 4) + 1) + (2 * 16) + 1 == 85
  */
-#define RXFIFO_SIZE  ((4 * MAX_CONTROL_EPS + 6) + \
-		      2 * ((USB_MAX_PACKET_SIZE / 4) + 1) + \
-		      (2 * MAX_NORMAL_EPS) + 1)
+#define RXFIFO_SIZE                                                        \
+	((4 * MAX_CONTROL_EPS + 6) + 2 * ((USB_MAX_PACKET_SIZE / 4) + 1) + \
+	 (2 * MAX_NORMAL_EPS) + 1)
 /*
  * Device TX FIFO size is 2 * (64 / 4) == 32 for each IN EP (Page 46).
  */
-#define TXFIFO_SIZE  (2 * (USB_MAX_PACKET_SIZE / 4))
+#define TXFIFO_SIZE (2 * (USB_MAX_PACKET_SIZE / 4))
 /*
  * We need 4 slots per endpoint direction for endpoint status stuff (Table 2-1,
  * unconfigurable).
@@ -925,20 +914,19 @@ static void ep0_interrupt(uint32_t intr_on_out, uint32_t intr_on_in)
 BUILD_ASSERT(RXFIFO_SIZE + TXFIFO_SIZE * MAX_NORMAL_EPS + EP_STATUS_SIZE <
 	     FIFO_RAM_DEPTH);
 
-
 /* Now put those constants into the correct registers */
 static void setup_data_fifos(void)
 {
 	int i;
 
 	/* Programmer's Guide, p31 */
-	GR_USB_GRXFSIZ = RXFIFO_SIZE;			      /* RXFIFO */
+	GR_USB_GRXFSIZ = RXFIFO_SIZE; /* RXFIFO */
 	GR_USB_GNPTXFSIZ = (TXFIFO_SIZE << 16) | RXFIFO_SIZE; /* TXFIFO 0 */
 
 	/* TXFIFO 1..15 */
 	for (i = 1; i < MAX_NORMAL_EPS; i++)
-		GR_USB_DIEPTXF(i) = ((TXFIFO_SIZE << 16) |
-				     (RXFIFO_SIZE + i * TXFIFO_SIZE));
+		GR_USB_DIEPTXF(i) =
+			((TXFIFO_SIZE << 16) | (RXFIFO_SIZE + i * TXFIFO_SIZE));
 
 	/*
 	 * TODO: The Programmer's Guide is confusing about when or whether to
@@ -953,10 +941,10 @@ static void setup_data_fifos(void)
 	 */
 
 	/* Flush all FIFOs according to Section 2.1.1.2 */
-	GR_USB_GRSTCTL = GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH
-		| GRSTCTL_RXFFLSH;
+	GR_USB_GRSTCTL = GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
+			 GRSTCTL_RXFFLSH;
 	while (GR_USB_GRSTCTL & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH))
-		;				/* TODO: timeout 100ms */
+		; /* TODO: timeout 100ms */
 }
 
 static void usb_init_endpoints(void)
@@ -998,7 +986,6 @@ static void usb_enumdone(void)
 	GR_USB_DCTL |= DCTL_CGOUTNAK;
 }
 
-
 static void usb_interrupt(void)
 {
 	uint32_t status = GR_USB_GINTSTS & GR_USB_GINTMSK;
@@ -1027,10 +1014,10 @@ static void usb_interrupt(void)
 		 * let it know which direction(s) had an interrupt.
 		 */
 		if (daint & (DAINT_OUTEP(0) | DAINT_INEP(0))) {
-			uint32_t intr_on_out = (oepint &&
-						(daint & DAINT_OUTEP(0)));
-			uint32_t intr_on_in = (iepint &&
-						(daint & DAINT_INEP(0)));
+			uint32_t intr_on_out =
+				(oepint && (daint & DAINT_OUTEP(0)));
+			uint32_t intr_on_in =
+				(iepint && (daint & DAINT_INEP(0)));
 			ep0_interrupt(intr_on_out, intr_on_in);
 		}
 
@@ -1103,8 +1090,8 @@ void usb_reset_init_phy(void)
 
 	if (usb->phy_type == USB_PHY_ULPI) {
 		GR_USB_GCCFG &= ~GCCFG_PWRDWN;
-		GR_USB_GUSBCFG &= ~(GUSBCFG_TSDPS |
-			GUSBCFG_ULPIFSLS | GUSBCFG_PHYSEL);
+		GR_USB_GUSBCFG &=
+			~(GUSBCFG_TSDPS | GUSBCFG_ULPIFSLS | GUSBCFG_PHYSEL);
 		GR_USB_GUSBCFG &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI);
 		/* No suspend */
 		GR_USB_GUSBCFG |= GUSBCFG_ULPICSM | GUSBCFG_ULPIAR;
@@ -1168,11 +1155,11 @@ void usb_init(void)
 		 * GR_USB_DCFG = (GR_USB_DCFG & ~GC_USB_DCFG_DEVSPD_MASK)
 		 * | DCFG_DEVSPD_HSULPI;
 		 */
-		GR_USB_DCFG = (GR_USB_DCFG & ~GC_USB_DCFG_DEVSPD_MASK)
-			| DCFG_DEVSPD_FSULPI;
+		GR_USB_DCFG = (GR_USB_DCFG & ~GC_USB_DCFG_DEVSPD_MASK) |
+			      DCFG_DEVSPD_FSULPI;
 	} else {
-		GR_USB_DCFG = (GR_USB_DCFG & ~GC_USB_DCFG_DEVSPD_MASK)
-			| DCFG_DEVSPD_FS48;
+		GR_USB_DCFG = (GR_USB_DCFG & ~GC_USB_DCFG_DEVSPD_MASK) |
+			      DCFG_DEVSPD_FS48;
 	}
 
 	GR_USB_DCFG |= DCFG_NZLSOHSK;
@@ -1190,10 +1177,11 @@ void usb_init(void)
 	GR_USB_GAHBCFG |= GAHBCFG_TXFELVL | GAHBCFG_PTXFELVL;
 
 	/* Device only, no SRP */
-	GR_USB_GUSBCFG |= GUSBCFG_FDMOD
-		| GUSBCFG_TOUTCAL(7)
-		/* FIXME: Magic number! 14 is for 15MHz! Use 9 for 30MHz */
-		| GUSBCFG_USBTRDTIM(14);
+	GR_USB_GUSBCFG |= GUSBCFG_FDMOD |
+			  GUSBCFG_TOUTCAL(7)
+			  /* FIXME: Magic number! 14 is for 15MHz! Use 9 for
+			     30MHz */
+			  | GUSBCFG_USBTRDTIM(14);
 
 	/* Be in disconnected state until we are ready */
 	usb_disconnect();
@@ -1225,15 +1213,15 @@ void usb_init(void)
 
 	if (usb->dma_en) {
 		GR_USB_DTHRCTL = DTHRCTL_TXTHRLEN_6 | DTHRCTL_RXTHRLEN_6;
-		GR_USB_DTHRCTL |= DTHRCTL_RXTHREN | DTHRCTL_ISOTHREN
-			| DTHRCTL_NONISOTHREN;
+		GR_USB_DTHRCTL |= DTHRCTL_RXTHREN | DTHRCTL_ISOTHREN |
+				  DTHRCTL_NONISOTHREN;
 		i = GR_USB_DTHRCTL;
 	}
 
 	GR_USB_GINTSTS = 0xFFFFFFFF;
 
-	GR_USB_GAHBCFG |= GAHBCFG_GLB_INTR_EN | GAHBCFG_TXFELVL
-		| GAHBCFG_PTXFELVL;
+	GR_USB_GAHBCFG |= GAHBCFG_GLB_INTR_EN | GAHBCFG_TXFELVL |
+			  GAHBCFG_PTXFELVL;
 
 	if (!(usb->dma_en))
 		GR_USB_GINTMSK |= GINTMSK(RXFLVL);
@@ -1241,7 +1229,7 @@ void usb_init(void)
 	/* Unmask some endpoint interrupt causes */
 	GR_USB_DIEPMSK = DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK;
 	GR_USB_DOEPMSK = DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK |
-		DOEPMSK_SETUPMSK;
+			 DOEPMSK_SETUPMSK;
 
 	/* Enable interrupt handlers */
 	task_enable_irq(usb->irq);
@@ -1253,7 +1241,7 @@ void usb_init(void)
 		/* Initialization events */
 		GINTMSK(USBRST) | GINTMSK(ENUMDONE) |
 		/* Reset detected while suspended. Need to wake up. */
-		GINTMSK(RESETDET) |		/* TODO: Do we need this? */
+		GINTMSK(RESETDET) | /* TODO: Do we need this? */
 		/* Idle, Suspend detected. Should go to sleep. */
 		GINTMSK(ERLYSUSP) | GINTMSK(USBSUSP);
 
@@ -1314,7 +1302,7 @@ static void usb_info(void)
 	}
 }
 
-static int command_usb(int argc, char **argv)
+static int command_usb(int argc, const char **argv)
 {
 	if (argc > 1) {
 		if (!strcasecmp("on", argv[1]))
@@ -1328,8 +1316,7 @@ static int command_usb(int argc, char **argv)
 
 	return EC_ERROR_PARAM1;
 }
-DECLARE_CONSOLE_COMMAND(usb, command_usb,
-			"[on|off|info]",
+DECLARE_CONSOLE_COMMAND(usb, command_usb, "[on|off|info]",
 			"Get/set the USB connection state and PHY selection");
 
 #ifdef CONFIG_USB_SERIALNO
@@ -1391,7 +1378,7 @@ static int usb_save_serial(const char *serialno)
 	return rv;
 }
 
-static int command_serialno(int argc, char **argv)
+static int command_serialno(int argc, const char **argv)
 {
 	struct usb_string_desc *sd = usb_serialno_desc;
 	char buf[CONFIG_SERIALNO_LEN];
@@ -1399,12 +1386,10 @@ static int command_serialno(int argc, char **argv)
 	int i;
 
 	if (argc != 1) {
-		if ((strcasecmp(argv[1], "set") == 0) &&
-		    (argc == 3)) {
+		if ((strcasecmp(argv[1], "set") == 0) && (argc == 3)) {
 			ccprintf("Saving serial number\n");
 			rv = usb_save_serial(argv[2]);
-		} else if ((strcasecmp(argv[1], "load") == 0) &&
-			   (argc == 2)) {
+		} else if ((strcasecmp(argv[1], "load") == 0) && (argc == 2)) {
 			ccprintf("Loading serial number\n");
 			rv = usb_load_serial();
 		} else
@@ -1417,7 +1402,6 @@ static int command_serialno(int argc, char **argv)
 	return rv;
 }
 
-DECLARE_CONSOLE_COMMAND(serialno, command_serialno,
-	"load/set [value]",
-	"Read and write USB serial number");
-#endif  /* CONFIG_USB_SERIALNO */
+DECLARE_CONSOLE_COMMAND(serialno, command_serialno, "load/set [value]",
+			"Read and write USB serial number");
+#endif /* CONFIG_USB_SERIALNO */
diff --git a/chip/stm32/usb_dwc_console.c b/chip/stm32/usb_dwc_console.c
index 0d1340fb83..fd66db7380 100644
--- a/chip/stm32/usb_dwc_console.c
+++ b/chip/stm32/usb_dwc_console.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,7 +17,7 @@
 #include "usb_hw.h"
 
 /* Console output macro */
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args)
 #define USB_CONSOLE_TIMEOUT_US (30 * MSEC)
 
 static int last_tx_ok = 1;
@@ -28,31 +28,31 @@ static int is_readonly;
 
 /* USB-Serial descriptors */
 const struct usb_interface_descriptor USB_IFACE_DESC(USB_IFACE_CONSOLE) = {
-	.bLength		= USB_DT_INTERFACE_SIZE,
-	.bDescriptorType	= USB_DT_INTERFACE,
-	.bInterfaceNumber	= USB_IFACE_CONSOLE,
-	.bAlternateSetting	= 0,
-	.bNumEndpoints		= 2,
-	.bInterfaceClass	= USB_CLASS_VENDOR_SPEC,
-	.bInterfaceSubClass	= USB_SUBCLASS_GOOGLE_SERIAL,
-	.bInterfaceProtocol	= USB_PROTOCOL_GOOGLE_SERIAL,
-	.iInterface		= USB_STR_CONSOLE_NAME,
+	.bLength = USB_DT_INTERFACE_SIZE,
+	.bDescriptorType = USB_DT_INTERFACE,
+	.bInterfaceNumber = USB_IFACE_CONSOLE,
+	.bAlternateSetting = 0,
+	.bNumEndpoints = 2,
+	.bInterfaceClass = USB_CLASS_VENDOR_SPEC,
+	.bInterfaceSubClass = USB_SUBCLASS_GOOGLE_SERIAL,
+	.bInterfaceProtocol = USB_PROTOCOL_GOOGLE_SERIAL,
+	.iInterface = USB_STR_CONSOLE_NAME,
 };
 const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_CONSOLE, 0) = {
-	.bLength		= USB_DT_ENDPOINT_SIZE,
-	.bDescriptorType	= USB_DT_ENDPOINT,
-	.bEndpointAddress	= 0x80 | USB_EP_CONSOLE,
-	.bmAttributes		= 0x02 /* Bulk IN */,
-	.wMaxPacketSize		= USB_MAX_PACKET_SIZE,
-	.bInterval		 = 10,
+	.bLength = USB_DT_ENDPOINT_SIZE,
+	.bDescriptorType = USB_DT_ENDPOINT,
+	.bEndpointAddress = 0x80 | USB_EP_CONSOLE,
+	.bmAttributes = 0x02 /* Bulk IN */,
+	.wMaxPacketSize = USB_MAX_PACKET_SIZE,
+	.bInterval = 10,
 };
 const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_CONSOLE, 1) = {
-	.bLength	    = USB_DT_ENDPOINT_SIZE,
-	.bDescriptorType    = USB_DT_ENDPOINT,
-	.bEndpointAddress   = USB_EP_CONSOLE,
-	.bmAttributes       = 0x02 /* Bulk OUT */,
-	.wMaxPacketSize     = USB_MAX_PACKET_SIZE,
-	.bInterval	  = 0
+	.bLength = USB_DT_ENDPOINT_SIZE,
+	.bDescriptorType = USB_DT_ENDPOINT,
+	.bEndpointAddress = USB_EP_CONSOLE,
+	.bmAttributes = 0x02 /* Bulk OUT */,
+	.wMaxPacketSize = USB_MAX_PACKET_SIZE,
+	.bInterval = 0
 };
 
 static uint8_t ep_buf_tx[USB_MAX_PACKET_SIZE];
@@ -61,7 +61,6 @@ static uint8_t ep_buf_rx[USB_MAX_PACKET_SIZE];
 static struct queue const tx_q = QUEUE_NULL(256, uint8_t);
 static struct queue const rx_q = QUEUE_NULL(USB_MAX_PACKET_SIZE, uint8_t);
 
-
 struct dwc_usb_ep ep_console_ctl = {
 	.max_packet = USB_MAX_PACKET_SIZE,
 	.tx_fifo = USB_EP_CONSOLE,
@@ -76,8 +75,6 @@ struct dwc_usb_ep ep_console_ctl = {
 	.in_databuffer_max = sizeof(ep_buf_rx),
 };
 
-
-
 /* Let the USB HW IN-to-host FIFO transmit some bytes */
 static void usb_enable_tx(int len)
 {
@@ -162,9 +159,8 @@ static void con_ep_rx(void)
 	/* Bytes received decrement DOEPTSIZ XFERSIZE */
 	if (GR_USB_DOEPINT(USB_EP_CONSOLE) & DOEPINT_XFERCOMPL) {
 		ep->out_pending =
-			ep->max_packet -
-			(GR_USB_DOEPTSIZ(USB_EP_CONSOLE) &
-			 GC_USB_DOEPTSIZ1_XFERSIZE_MASK);
+			ep->max_packet - (GR_USB_DOEPTSIZ(USB_EP_CONSOLE) &
+					  GC_USB_DOEPTSIZ1_XFERSIZE_MASK);
 	}
 
 	/* Wake up the Rx FIFO handler */
@@ -193,8 +189,8 @@ static void tx_fifo_handler(void)
 	if (!tx_fifo_is_ready())
 		return;
 
-	count = QUEUE_REMOVE_UNITS(&tx_q,
-		ep->in_databuffer, USB_MAX_PACKET_SIZE);
+	count = QUEUE_REMOVE_UNITS(&tx_q, ep->in_databuffer,
+				   USB_MAX_PACKET_SIZE);
 	if (count)
 		usb_enable_tx(count);
 }
@@ -232,7 +228,6 @@ static void ep_event(enum usb_ep_event evt)
 	usb_enable_rx(USB_MAX_PACKET_SIZE);
 }
 
-
 USB_DECLARE_EP(USB_EP_CONSOLE, con_ep_tx, con_ep_rx, ep_event);
 
 static int usb_wait_console(void)
@@ -274,8 +269,7 @@ static int usb_wait_console(void)
 }
 static int __tx_char(void *context, int c)
 {
-	struct queue *state =
-			(struct queue *) context;
+	struct queue *state = (struct queue *)context;
 
 	if (c == '\n' && __tx_char(state, '\r'))
 		return 1;
@@ -308,7 +302,7 @@ int usb_puts(const char *outstr)
 	if (is_readonly)
 		return EC_SUCCESS;
 
-	ret  = usb_wait_console();
+	ret = usb_wait_console();
 	if (ret)
 		return ret;
 
diff --git a/chip/stm32/usb_dwc_console.h b/chip/stm32/usb_dwc_console.h
index ab2206d359..f0a0732c7d 100644
--- a/chip/stm32/usb_dwc_console.h
+++ b/chip/stm32/usb_dwc_console.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,4 +10,4 @@
 
 extern struct dwc_usb_ep ep_console_ctl;
 
-#endif  /* __CHIP_STM32_USB_DWC_CONSOLE_H */
+#endif /* __CHIP_STM32_USB_DWC_CONSOLE_H */
diff --git a/chip/stm32/usb_dwc_hw.h b/chip/stm32/usb_dwc_hw.h
index d1fe07cb87..ea87869257 100644
--- a/chip/stm32/usb_dwc_hw.h
+++ b/chip/stm32/usb_dwc_hw.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,29 +18,27 @@
 #define _EP_RX_HANDLER_TYPECHECK(num) _EP_HANDLER2(num, _rx_typecheck)
 #define _EP_EVENT_HANDLER_TYPECHECK(num) _EP_HANDLER2(num, _evt_typecheck)
 
-#define USB_DECLARE_EP(num, tx_handler, rx_handler, evt_handler)  \
-	void _EP_TX_HANDLER(num)(void)				  \
-		__attribute__ ((alias(STRINGIFY(tx_handler))));	  \
-	void _EP_RX_HANDLER(num)(void)                            \
-		__attribute__ ((alias(STRINGIFY(rx_handler))));	  \
-	void _EP_EVENT_HANDLER(num)(enum usb_ep_event evt)	  \
-		__attribute__ ((alias(STRINGIFY(evt_handler))));  \
-	static __unused void					  \
-	(*_EP_TX_HANDLER_TYPECHECK(num))(void) = tx_handler;	  \
-	static __unused void					  \
-	(*_EP_RX_HANDLER_TYPECHECK(num))(void) = rx_handler;	  \
-	static __unused void					  \
-	(*_EP_EVENT_HANDLER_TYPECHECK(num))(enum usb_ep_event evt)\
-			= evt_handler
+#define USB_DECLARE_EP(num, tx_handler, rx_handler, evt_handler)      \
+	void _EP_TX_HANDLER(num)(void)                                \
+		__attribute__((alias(STRINGIFY(tx_handler))));        \
+	void _EP_RX_HANDLER(num)(void)                                \
+		__attribute__((alias(STRINGIFY(rx_handler))));        \
+	void _EP_EVENT_HANDLER(num)(enum usb_ep_event evt)            \
+		__attribute__((alias(STRINGIFY(evt_handler))));       \
+	static __unused void (*_EP_TX_HANDLER_TYPECHECK(num))(void) = \
+		tx_handler;                                           \
+	static __unused void (*_EP_RX_HANDLER_TYPECHECK(num))(void) = \
+		rx_handler;                                           \
+	static __unused void (*_EP_EVENT_HANDLER_TYPECHECK(num))(     \
+		enum usb_ep_event evt) = evt_handler
 
 /* Endpoint callbacks */
-extern void (*usb_ep_tx[]) (void);
-extern void (*usb_ep_rx[]) (void);
-extern void (*usb_ep_event[]) (enum usb_ep_event evt);
+extern void (*usb_ep_tx[])(void);
+extern void (*usb_ep_rx[])(void);
+extern void (*usb_ep_event[])(enum usb_ep_event evt);
 struct usb_setup_packet;
 /* EP0 Interface handler callbacks */
-extern int (*usb_iface_request[]) (struct usb_setup_packet *req);
-
+extern int (*usb_iface_request[])(struct usb_setup_packet *req);
 
 /* True if the HW Rx/OUT FIFO is currently listening. */
 int rx_ep_is_active(uint32_t ep_num);
@@ -99,8 +97,8 @@ void epN_reset(uint32_t ep_num);
  * (and thus indicate error to the host).
  */
 #define _IFACE_HANDLER(num) CONCAT3(iface_, num, _request)
-#define USB_DECLARE_IFACE(num, handler)				\
-	int _IFACE_HANDLER(num)(struct usb_setup_packet *req)	\
-		__attribute__ ((alias(STRINGIFY(handler))))
+#define USB_DECLARE_IFACE(num, handler)                        \
+	int _IFACE_HANDLER(num)(struct usb_setup_packet * req) \
+		__attribute__((alias(STRINGIFY(handler))))
 
-#endif	/* __CROS_EC_USB_DWC_HW_H */
+#endif /* __CROS_EC_USB_DWC_HW_H */
diff --git a/chip/stm32/usb_dwc_i2c.h b/chip/stm32/usb_dwc_i2c.h
index e44002268a..6e6c72e22c 100644
--- a/chip/stm32/usb_dwc_i2c.h
+++ b/chip/stm32/usb_dwc_i2c.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/stm32/usb_dwc_registers.h b/chip/stm32/usb_dwc_registers.h
index faac9ca775..b5ada2ce65 100644
--- a/chip/stm32/usb_dwc_registers.h
+++ b/chip/stm32/usb_dwc_registers.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -55,7479 +55,7467 @@ extern struct dwc_usb usb_ctl;
  * Added Alias Module Family Base Address to 0-instance Module Base Address
  * Simplify GBASE(mname) macro
  */
-#define GC_MODULE_OFFSET         0x10000
+#define GC_MODULE_OFFSET 0x10000
 
-#define GBASE(mname)      \
-	GC_ ## mname ## _BASE_ADDR
-#define GOFFSET(mname, rname)  \
-	GC_ ## mname ## _ ## rname ## _OFFSET
+#define GBASE(mname) GC_##mname##_BASE_ADDR
+#define GOFFSET(mname, rname) GC_##mname##_##rname##_OFFSET
 
-#define GREG8(mname, rname) \
-	REG8(GBASE(mname) + GOFFSET(mname, rname))
-#define GREG32(mname, rname) \
-	REG32(GBASE(mname) + GOFFSET(mname, rname))
+#define GREG8(mname, rname) REG8(GBASE(mname) + GOFFSET(mname, rname))
+#define GREG32(mname, rname) REG32(GBASE(mname) + GOFFSET(mname, rname))
 #define GREG32_ADDR(mname, rname) \
 	REG32_ADDR(GBASE(mname) + GOFFSET(mname, rname))
 #define GWRITE(mname, rname, value) (GREG32(mname, rname) = (value))
-#define GREAD(mname, rname)	    GREG32(mname, rname)
+#define GREAD(mname, rname) GREG32(mname, rname)
 
-#define GFIELD_MASK(mname, rname, fname) \
-	GC_ ## mname ## _ ## rname ## _ ## fname ## _MASK
+#define GFIELD_MASK(mname, rname, fname) GC_##mname##_##rname##_##fname##_MASK
 
-#define GFIELD_LSB(mname, rname, fname)  \
-	GC_ ## mname ## _ ## rname ## _ ## fname ## _LSB
+#define GFIELD_LSB(mname, rname, fname) GC_##mname##_##rname##_##fname##_LSB
 
-#define GREAD_FIELD(mname, rname, fname) \
-	((GREG32(mname, rname) & GFIELD_MASK(mname, rname, fname)) \
-		>> GFIELD_LSB(mname, rname, fname))
+#define GREAD_FIELD(mname, rname, fname)                              \
+	((GREG32(mname, rname) & GFIELD_MASK(mname, rname, fname)) >> \
+	 GFIELD_LSB(mname, rname, fname))
 
-#define GWRITE_FIELD(mname, rname, fname, fval) \
-	(GREG32(mname, rname) = \
-	((GREG32(mname, rname) & (~GFIELD_MASK(mname, rname, fname))) | \
-	(((fval) << GFIELD_LSB(mname, rname, fname)) & \
-		GFIELD_MASK(mname, rname, fname))))
+#define GWRITE_FIELD(mname, rname, fname, fval)                  \
+	(GREG32(mname, rname) =                                  \
+		 ((GREG32(mname, rname) &                        \
+		   (~GFIELD_MASK(mname, rname, fname))) |        \
+		  (((fval) << GFIELD_LSB(mname, rname, fname)) & \
+		   GFIELD_MASK(mname, rname, fname))))
 
-
-#define GBASE_I(mname, i)     (GBASE(mname) + i*GC_MODULE_OFFSET)
+#define GBASE_I(mname, i) (GBASE(mname) + i * GC_MODULE_OFFSET)
 
 #define GREG32_I(mname, i, rname) \
-		REG32(GBASE_I(mname, i) + GOFFSET(mname, rname))
+	REG32(GBASE_I(mname, i) + GOFFSET(mname, rname))
 
 #define GREG32_ADDR_I(mname, i, rname) \
-		REG32_ADDR(GBASE_I(mname, i) + GOFFSET(mname, rname))
+	REG32_ADDR(GBASE_I(mname, i) + GOFFSET(mname, rname))
 
 #define GWRITE_I(mname, i, rname, value) (GREG32_I(mname, i, rname) = (value))
-#define GREAD_I(mname, i, rname)	        GREG32_I(mname, i, rname)
+#define GREAD_I(mname, i, rname) GREG32_I(mname, i, rname)
 
-#define GREAD_FIELD_I(mname, i, rname, fname) \
-	((GREG32_I(mname, i, rname) & GFIELD_MASK(mname, rname, fname)) \
-		>> GFIELD_LSB(mname, rname, fname))
+#define GREAD_FIELD_I(mname, i, rname, fname)                              \
+	((GREG32_I(mname, i, rname) & GFIELD_MASK(mname, rname, fname)) >> \
+	 GFIELD_LSB(mname, rname, fname))
 
-#define GWRITE_FIELD_I(mname, i, rname, fname, fval) \
-	(GREG32_I(mname, i, rname) = \
-	((GREG32_I(mname, i, rname) & (~GFIELD_MASK(mname, rname, fname))) | \
-	(((fval) << GFIELD_LSB(mname, rname, fname)) & \
-		GFIELD_MASK(mname, rname, fname))))
+#define GWRITE_FIELD_I(mname, i, rname, fname, fval)             \
+	(GREG32_I(mname, i, rname) =                             \
+		 ((GREG32_I(mname, i, rname) &                   \
+		   (~GFIELD_MASK(mname, rname, fname))) |        \
+		  (((fval) << GFIELD_LSB(mname, rname, fname)) & \
+		   GFIELD_MASK(mname, rname, fname))))
 
 /* Replace masked bits with val << lsb */
 #define REG_WRITE_MLV(reg, mask, lsb, val) \
-		(reg = ((reg & ~mask) | ((val << lsb) & mask)))
-
+	(reg = ((reg & ~mask) | ((val << lsb) & mask)))
 
 /* USB device controller */
-#define GR_USB_REG(off)               REG32(GC_USB_BASE_ADDR + (off))
-#define GR_USB_GOTGCTL                GR_USB_REG(GC_USB_GOTGCTL_OFFSET)
-#define GR_USB_GOTGINT                GR_USB_REG(GC_USB_GOTGINT_OFFSET)
-#define GR_USB_GAHBCFG                GR_USB_REG(GC_USB_GAHBCFG_OFFSET)
-#define GR_USB_GUSBCFG                GR_USB_REG(GC_USB_GUSBCFG_OFFSET)
-#define GR_USB_GRSTCTL                GR_USB_REG(GC_USB_GRSTCTL_OFFSET)
-#define GR_USB_GINTSTS                GR_USB_REG(GC_USB_GINTSTS_OFFSET)
-#define   GINTSTS(bit)                (1 << GC_USB_GINTSTS_ ## bit ## _LSB)
-#define GR_USB_GINTMSK                GR_USB_REG(GC_USB_GINTMSK_OFFSET)
-#define   GINTMSK(bit)                (1 << GC_USB_GINTMSK_ ## bit ## MSK_LSB)
-#define GR_USB_GRXSTSR                GR_USB_REG(GC_USB_GRXSTSR_OFFSET)
-#define GR_USB_GRXSTSP                GR_USB_REG(GC_USB_GRXSTSP_OFFSET)
-#define GR_USB_GRXFSIZ                GR_USB_REG(GC_USB_GRXFSIZ_OFFSET)
-#define GR_USB_GNPTXFSIZ              GR_USB_REG(GC_USB_GNPTXFSIZ_OFFSET)
+#define GR_USB_REG(off) REG32(GC_USB_BASE_ADDR + (off))
+#define GR_USB_GOTGCTL GR_USB_REG(GC_USB_GOTGCTL_OFFSET)
+#define GR_USB_GOTGINT GR_USB_REG(GC_USB_GOTGINT_OFFSET)
+#define GR_USB_GAHBCFG GR_USB_REG(GC_USB_GAHBCFG_OFFSET)
+#define GR_USB_GUSBCFG GR_USB_REG(GC_USB_GUSBCFG_OFFSET)
+#define GR_USB_GRSTCTL GR_USB_REG(GC_USB_GRSTCTL_OFFSET)
+#define GR_USB_GINTSTS GR_USB_REG(GC_USB_GINTSTS_OFFSET)
+#define GINTSTS(bit) (1 << GC_USB_GINTSTS_##bit##_LSB)
+#define GR_USB_GINTMSK GR_USB_REG(GC_USB_GINTMSK_OFFSET)
+#define GINTMSK(bit) (1 << GC_USB_GINTMSK_##bit##MSK_LSB)
+#define GR_USB_GRXSTSR GR_USB_REG(GC_USB_GRXSTSR_OFFSET)
+#define GR_USB_GRXSTSP GR_USB_REG(GC_USB_GRXSTSP_OFFSET)
+#define GR_USB_GRXFSIZ GR_USB_REG(GC_USB_GRXFSIZ_OFFSET)
+#define GR_USB_GNPTXFSIZ GR_USB_REG(GC_USB_GNPTXFSIZ_OFFSET)
 /*#define GR_USB_GGPIO                  GR_USB_REG(GC_USB_GGPIO_OFFSET)*/
-#define GR_USB_GCCFG                  GR_USB_REG(GC_USB_GCCFG_OFFSET)
-#define  GCCFG_VBDEN            BIT(21)
-#define  GCCFG_PWRDWN           BIT(16)
-#define GR_USB_PCGCCTL                GR_USB_REG(GC_USB_PCGCCTL_OFFSET)
+#define GR_USB_GCCFG GR_USB_REG(GC_USB_GCCFG_OFFSET)
+#define GCCFG_VBDEN BIT(21)
+#define GCCFG_PWRDWN BIT(16)
+#define GR_USB_PCGCCTL GR_USB_REG(GC_USB_PCGCCTL_OFFSET)
 
-#define GR_USB_GSNPSID                GR_USB_REG(GC_USB_GSNPSID_OFFSET)
-#define GR_USB_GHWCFG1                GR_USB_REG(GC_USB_GHWCFG1_OFFSET)
-#define GR_USB_GHWCFG2                GR_USB_REG(GC_USB_GHWCFG2_OFFSET)
-#define GR_USB_GHWCFG3                GR_USB_REG(GC_USB_GHWCFG3_OFFSET)
-#define GR_USB_GHWCFG4                GR_USB_REG(GC_USB_GHWCFG4_OFFSET)
-#define GR_USB_GDFIFOCFG              GR_USB_REG(GC_USB_GDFIFOCFG_OFFSET)
-#define GR_USB_DIEPTXF(n)	\
-	GR_USB_REG(GC_USB_DIEPTXF1_OFFSET - 4 + (n)*4)
-#define GR_USB_DCFG                   GR_USB_REG(GC_USB_DCFG_OFFSET)
-#define GR_USB_DCTL                   GR_USB_REG(GC_USB_DCTL_OFFSET)
-#define GR_USB_DSTS                   GR_USB_REG(GC_USB_DSTS_OFFSET)
-#define GR_USB_DIEPMSK                GR_USB_REG(GC_USB_DIEPMSK_OFFSET)
-#define GR_USB_DOEPMSK                GR_USB_REG(GC_USB_DOEPMSK_OFFSET)
-#define GR_USB_DAINT                  GR_USB_REG(GC_USB_DAINT_OFFSET)
-#define GR_USB_DAINTMSK               GR_USB_REG(GC_USB_DAINTMSK_OFFSET)
-#define  DAINT_INEP(ep)               (1 << (ep + GC_USB_DAINTMSK_INEPMSK0_LSB))
-#define  DAINT_OUTEP(ep)	\
-	(1 << (ep + GC_USB_DAINTMSK_OUTEPMSK0_LSB))
-#define GR_USB_DTHRCTL                GR_USB_REG(GC_USB_DTHRCTL_OFFSET)
-#define  DTHRCTL_TXTHRLEN_6           (0x40 << 2)
-#define  DTHRCTL_RXTHRLEN_6           (0x40 << 17)
-#define  DTHRCTL_RXTHREN              BIT(16)
-#define  DTHRCTL_ISOTHREN             BIT(1)
-#define  DTHRCTL_NONISOTHREN          BIT(0)
-#define GR_USB_DIEPEMPMSK             GR_USB_REG(GC_USB_DIEPEMPMSK_OFFSET)
+#define GR_USB_GSNPSID GR_USB_REG(GC_USB_GSNPSID_OFFSET)
+#define GR_USB_GHWCFG1 GR_USB_REG(GC_USB_GHWCFG1_OFFSET)
+#define GR_USB_GHWCFG2 GR_USB_REG(GC_USB_GHWCFG2_OFFSET)
+#define GR_USB_GHWCFG3 GR_USB_REG(GC_USB_GHWCFG3_OFFSET)
+#define GR_USB_GHWCFG4 GR_USB_REG(GC_USB_GHWCFG4_OFFSET)
+#define GR_USB_GDFIFOCFG GR_USB_REG(GC_USB_GDFIFOCFG_OFFSET)
+#define GR_USB_DIEPTXF(n) GR_USB_REG(GC_USB_DIEPTXF1_OFFSET - 4 + (n)*4)
+#define GR_USB_DCFG GR_USB_REG(GC_USB_DCFG_OFFSET)
+#define GR_USB_DCTL GR_USB_REG(GC_USB_DCTL_OFFSET)
+#define GR_USB_DSTS GR_USB_REG(GC_USB_DSTS_OFFSET)
+#define GR_USB_DIEPMSK GR_USB_REG(GC_USB_DIEPMSK_OFFSET)
+#define GR_USB_DOEPMSK GR_USB_REG(GC_USB_DOEPMSK_OFFSET)
+#define GR_USB_DAINT GR_USB_REG(GC_USB_DAINT_OFFSET)
+#define GR_USB_DAINTMSK GR_USB_REG(GC_USB_DAINTMSK_OFFSET)
+#define DAINT_INEP(ep) (1 << (ep + GC_USB_DAINTMSK_INEPMSK0_LSB))
+#define DAINT_OUTEP(ep) (1 << (ep + GC_USB_DAINTMSK_OUTEPMSK0_LSB))
+#define GR_USB_DTHRCTL GR_USB_REG(GC_USB_DTHRCTL_OFFSET)
+#define DTHRCTL_TXTHRLEN_6 (0x40 << 2)
+#define DTHRCTL_RXTHRLEN_6 (0x40 << 17)
+#define DTHRCTL_RXTHREN BIT(16)
+#define DTHRCTL_ISOTHREN BIT(1)
+#define DTHRCTL_NONISOTHREN BIT(0)
+#define GR_USB_DIEPEMPMSK GR_USB_REG(GC_USB_DIEPEMPMSK_OFFSET)
 
-#define GR_USB_EPIREG(off, n)         GR_USB_REG(0x900 + (n) * 0x20 + (off))
-#define GR_USB_EPOREG(off, n)         GR_USB_REG(0xb00 + (n) * 0x20 + (off))
-#define GR_USB_DIEPCTL(n)             GR_USB_EPIREG(0x00, n)
-#define GR_USB_DIEPINT(n)             GR_USB_EPIREG(0x08, n)
-#define GR_USB_DIEPTSIZ(n)            GR_USB_EPIREG(0x10, n)
-#define GR_USB_DIEPDMA(n)             GR_USB_EPIREG(0x14, n)
-#define GR_USB_DTXFSTS(n)             GR_USB_EPIREG(0x18, n)
-#define GR_USB_DIEPDMAB(n)            GR_USB_EPIREG(0x1c, n)
-#define GR_USB_DOEPCTL(n)             GR_USB_EPOREG(0x00, n)
-#define GR_USB_DOEPINT(n)             GR_USB_EPOREG(0x08, n)
-#define GR_USB_DOEPTSIZ(n)            GR_USB_EPOREG(0x10, n)
-#define GR_USB_DOEPDMA(n)             GR_USB_EPOREG(0x14, n)
-#define GR_USB_DOEPDMAB(n)            GR_USB_EPOREG(0x1c, n)
+#define GR_USB_EPIREG(off, n) GR_USB_REG(0x900 + (n)*0x20 + (off))
+#define GR_USB_EPOREG(off, n) GR_USB_REG(0xb00 + (n)*0x20 + (off))
+#define GR_USB_DIEPCTL(n) GR_USB_EPIREG(0x00, n)
+#define GR_USB_DIEPINT(n) GR_USB_EPIREG(0x08, n)
+#define GR_USB_DIEPTSIZ(n) GR_USB_EPIREG(0x10, n)
+#define GR_USB_DIEPDMA(n) GR_USB_EPIREG(0x14, n)
+#define GR_USB_DTXFSTS(n) GR_USB_EPIREG(0x18, n)
+#define GR_USB_DIEPDMAB(n) GR_USB_EPIREG(0x1c, n)
+#define GR_USB_DOEPCTL(n) GR_USB_EPOREG(0x00, n)
+#define GR_USB_DOEPINT(n) GR_USB_EPOREG(0x08, n)
+#define GR_USB_DOEPTSIZ(n) GR_USB_EPOREG(0x10, n)
+#define GR_USB_DOEPDMA(n) GR_USB_EPOREG(0x14, n)
+#define GR_USB_DOEPDMAB(n) GR_USB_EPOREG(0x1c, n)
 
-#define GOTGCTL_BVALOEN               BIT(GC_USB_GOTGCTL_BVALIDOVEN_LSB)
-#define GOTGCTL_BVALOVAL              BIT(7)
+#define GOTGCTL_BVALOEN BIT(GC_USB_GOTGCTL_BVALIDOVEN_LSB)
+#define GOTGCTL_BVALOVAL BIT(7)
 
 /* Bit 5 */
-#define GAHBCFG_DMA_EN                BIT(GC_USB_GAHBCFG_DMAEN_LSB)
+#define GAHBCFG_DMA_EN BIT(GC_USB_GAHBCFG_DMAEN_LSB)
 /* Bit 1 */
-#define GAHBCFG_GLB_INTR_EN           BIT(GC_USB_GAHBCFG_GLBLINTRMSK_LSB)
+#define GAHBCFG_GLB_INTR_EN BIT(GC_USB_GAHBCFG_GLBLINTRMSK_LSB)
 /* HS Burst Len */
-#define GAHBCFG_HBSTLEN_INCR4         (3 << GC_USB_GAHBCFG_HBSTLEN_LSB)
+#define GAHBCFG_HBSTLEN_INCR4 (3 << GC_USB_GAHBCFG_HBSTLEN_LSB)
 /* Bit 7 */
-#define GAHBCFG_NP_TXF_EMP_LVL        (1 <<  GC_USB_GAHBCFG_NPTXFEMPLVL_LSB)
-#define GAHBCFG_TXFELVL               GAHBCFG_NP_TXF_EMP_LVL
-#define GAHBCFG_PTXFELVL              BIT(8)
+#define GAHBCFG_NP_TXF_EMP_LVL (1 << GC_USB_GAHBCFG_NPTXFEMPLVL_LSB)
+#define GAHBCFG_TXFELVL GAHBCFG_NP_TXF_EMP_LVL
+#define GAHBCFG_PTXFELVL BIT(8)
 
-#define GUSBCFG_TOUTCAL(n)            (((n) << GC_USB_GUSBCFG_TOUTCAL_LSB) \
-				       & GC_USB_GUSBCFG_TOUTCAL_MASK)
-#define GUSBCFG_USBTRDTIM(n)          (((n) << GC_USB_GUSBCFG_USBTRDTIM_LSB) \
-				       & GC_USB_GUSBCFG_USBTRDTIM_MASK)
+#define GUSBCFG_TOUTCAL(n) \
+	(((n) << GC_USB_GUSBCFG_TOUTCAL_LSB) & GC_USB_GUSBCFG_TOUTCAL_MASK)
+#define GUSBCFG_USBTRDTIM(n) \
+	(((n) << GC_USB_GUSBCFG_USBTRDTIM_LSB) & GC_USB_GUSBCFG_USBTRDTIM_MASK)
 /* Force device mode */
-#define GUSBCFG_FDMOD                 BIT(GC_USB_GUSBCFG_FDMOD_LSB)
-#define GUSBCFG_PHYSEL                BIT(6)
-#define GUSBCFG_SRPCAP                BIT(8)
-#define GUSBCFG_HNPCAP                BIT(9)
-#define GUSBCFG_ULPIFSLS              BIT(17)
-#define GUSBCFG_ULPIAR                BIT(18)
-#define GUSBCFG_ULPICSM               BIT(19)
-#define GUSBCFG_ULPIEVBUSD            BIT(20)
-#define GUSBCFG_ULPIEVBUSI            BIT(21)
-#define GUSBCFG_TSDPS                 BIT(22)
-#define GUSBCFG_PCCI                  BIT(23)
-#define GUSBCFG_PTCI                  BIT(24)
-#define GUSBCFG_ULPIIPD               BIT(25)
-#define GUSBCFG_TSDPS                 BIT(22)
-
+#define GUSBCFG_FDMOD BIT(GC_USB_GUSBCFG_FDMOD_LSB)
+#define GUSBCFG_PHYSEL BIT(6)
+#define GUSBCFG_SRPCAP BIT(8)
+#define GUSBCFG_HNPCAP BIT(9)
+#define GUSBCFG_ULPIFSLS BIT(17)
+#define GUSBCFG_ULPIAR BIT(18)
+#define GUSBCFG_ULPICSM BIT(19)
+#define GUSBCFG_ULPIEVBUSD BIT(20)
+#define GUSBCFG_ULPIEVBUSI BIT(21)
+#define GUSBCFG_TSDPS BIT(22)
+#define GUSBCFG_PCCI BIT(23)
+#define GUSBCFG_PTCI BIT(24)
+#define GUSBCFG_ULPIIPD BIT(25)
+#define GUSBCFG_TSDPS BIT(22)
 
-#define GRSTCTL_CSFTRST               BIT(GC_USB_GRSTCTL_CSFTRST_LSB)
-#define GRSTCTL_AHBIDLE               BIT(GC_USB_GRSTCTL_AHBIDLE_LSB)
-#define GRSTCTL_TXFFLSH               BIT(GC_USB_GRSTCTL_TXFFLSH_LSB)
-#define GRSTCTL_RXFFLSH               BIT(GC_USB_GRSTCTL_RXFFLSH_LSB)
-#define GRSTCTL_TXFNUM(n)	\
+#define GRSTCTL_CSFTRST BIT(GC_USB_GRSTCTL_CSFTRST_LSB)
+#define GRSTCTL_AHBIDLE BIT(GC_USB_GRSTCTL_AHBIDLE_LSB)
+#define GRSTCTL_TXFFLSH BIT(GC_USB_GRSTCTL_TXFFLSH_LSB)
+#define GRSTCTL_RXFFLSH BIT(GC_USB_GRSTCTL_RXFFLSH_LSB)
+#define GRSTCTL_TXFNUM(n) \
 	(((n) << GC_USB_GRSTCTL_TXFNUM_LSB) & GC_USB_GRSTCTL_TXFNUM_MASK)
 
-#define DCFG_DEVSPD_HSULPI            (0 << GC_USB_DCFG_DEVSPD_LSB)
-#define DCFG_DEVSPD_FSULPI            BIT(GC_USB_DCFG_DEVSPD_LSB)
-#define DCFG_DEVSPD_FS48              (3 << GC_USB_DCFG_DEVSPD_LSB)
-#define DCFG_DEVADDR(a)	\
+#define DCFG_DEVSPD_HSULPI (0 << GC_USB_DCFG_DEVSPD_LSB)
+#define DCFG_DEVSPD_FSULPI BIT(GC_USB_DCFG_DEVSPD_LSB)
+#define DCFG_DEVSPD_FS48 (3 << GC_USB_DCFG_DEVSPD_LSB)
+#define DCFG_DEVADDR(a) \
 	(((a) << GC_USB_DCFG_DEVADDR_LSB) & GC_USB_DCFG_DEVADDR_MASK)
-#define DCFG_NZLSOHSK                 BIT(GC_USB_DCFG_NZSTSOUTHSHK_LSB)
+#define DCFG_NZLSOHSK BIT(GC_USB_DCFG_NZSTSOUTHSHK_LSB)
 
-#define DCTL_SFTDISCON                BIT(GC_USB_DCTL_SFTDISCON_LSB)
-#define DCTL_CGOUTNAK                 BIT(GC_USB_DCTL_CGOUTNAK_LSB)
-#define DCTL_CGNPINNAK                BIT(GC_USB_DCTL_CGNPINNAK_LSB)
-#define DCTL_PWRONPRGDONE             BIT(GC_USB_DCTL_PWRONPRGDONE_LSB)
+#define DCTL_SFTDISCON BIT(GC_USB_DCTL_SFTDISCON_LSB)
+#define DCTL_CGOUTNAK BIT(GC_USB_DCTL_CGOUTNAK_LSB)
+#define DCTL_CGNPINNAK BIT(GC_USB_DCTL_CGNPINNAK_LSB)
+#define DCTL_PWRONPRGDONE BIT(GC_USB_DCTL_PWRONPRGDONE_LSB)
 
 /* Device Endpoint Common IN Interrupt Mask bits */
-#define DIEPMSK_AHBERRMSK             BIT(GC_USB_DIEPMSK_AHBERRMSK_LSB)
-#define DIEPMSK_BNAININTRMSK          BIT(GC_USB_DIEPMSK_BNAININTRMSK_LSB)
-#define DIEPMSK_EPDISBLDMSK           BIT(GC_USB_DIEPMSK_EPDISBLDMSK_LSB)
-#define DIEPMSK_INEPNAKEFFMSK         BIT(GC_USB_DIEPMSK_INEPNAKEFFMSK_LSB)
-#define DIEPMSK_INTKNEPMISMSK         BIT(GC_USB_DIEPMSK_INTKNEPMISMSK_LSB)
-#define DIEPMSK_INTKNTXFEMPMSK        BIT(GC_USB_DIEPMSK_INTKNTXFEMPMSK_LSB)
-#define DIEPMSK_NAKMSK                BIT(GC_USB_DIEPMSK_NAKMSK_LSB)
-#define DIEPMSK_TIMEOUTMSK            BIT(GC_USB_DIEPMSK_TIMEOUTMSK_LSB)
-#define DIEPMSK_TXFIFOUNDRNMSK        BIT(GC_USB_DIEPMSK_TXFIFOUNDRNMSK_LSB)
-#define DIEPMSK_XFERCOMPLMSK          BIT(GC_USB_DIEPMSK_XFERCOMPLMSK_LSB)
+#define DIEPMSK_AHBERRMSK BIT(GC_USB_DIEPMSK_AHBERRMSK_LSB)
+#define DIEPMSK_BNAININTRMSK BIT(GC_USB_DIEPMSK_BNAININTRMSK_LSB)
+#define DIEPMSK_EPDISBLDMSK BIT(GC_USB_DIEPMSK_EPDISBLDMSK_LSB)
+#define DIEPMSK_INEPNAKEFFMSK BIT(GC_USB_DIEPMSK_INEPNAKEFFMSK_LSB)
+#define DIEPMSK_INTKNEPMISMSK BIT(GC_USB_DIEPMSK_INTKNEPMISMSK_LSB)
+#define DIEPMSK_INTKNTXFEMPMSK BIT(GC_USB_DIEPMSK_INTKNTXFEMPMSK_LSB)
+#define DIEPMSK_NAKMSK BIT(GC_USB_DIEPMSK_NAKMSK_LSB)
+#define DIEPMSK_TIMEOUTMSK BIT(GC_USB_DIEPMSK_TIMEOUTMSK_LSB)
+#define DIEPMSK_TXFIFOUNDRNMSK BIT(GC_USB_DIEPMSK_TXFIFOUNDRNMSK_LSB)
+#define DIEPMSK_XFERCOMPLMSK BIT(GC_USB_DIEPMSK_XFERCOMPLMSK_LSB)
 
 /* Device Endpoint Common OUT Interrupt Mask bits */
-#define DOEPMSK_AHBERRMSK             BIT(GC_USB_DOEPMSK_AHBERRMSK_LSB)
-#define DOEPMSK_BBLEERRMSK            BIT(GC_USB_DOEPMSK_BBLEERRMSK_LSB)
-#define DOEPMSK_BNAOUTINTRMSK         BIT(GC_USB_DOEPMSK_BNAOUTINTRMSK_LSB)
-#define DOEPMSK_EPDISBLDMSK           BIT(GC_USB_DOEPMSK_EPDISBLDMSK_LSB)
-#define DOEPMSK_NAKMSK                BIT(GC_USB_DOEPMSK_NAKMSK_LSB)
-#define DOEPMSK_NYETMSK               BIT(GC_USB_DOEPMSK_NYETMSK_LSB)
-#define DOEPMSK_OUTPKTERRMSK          BIT(GC_USB_DOEPMSK_OUTPKTERRMSK_LSB)
-#define DOEPMSK_OUTTKNEPDISMSK        BIT(GC_USB_DOEPMSK_OUTTKNEPDISMSK_LSB)
-#define DOEPMSK_SETUPMSK              BIT(GC_USB_DOEPMSK_SETUPMSK_LSB)
-#define DOEPMSK_STSPHSERCVDMSK        BIT(GC_USB_DOEPMSK_STSPHSERCVDMSK_LSB)
-#define DOEPMSK_XFERCOMPLMSK          BIT(GC_USB_DOEPMSK_XFERCOMPLMSK_LSB)
+#define DOEPMSK_AHBERRMSK BIT(GC_USB_DOEPMSK_AHBERRMSK_LSB)
+#define DOEPMSK_BBLEERRMSK BIT(GC_USB_DOEPMSK_BBLEERRMSK_LSB)
+#define DOEPMSK_BNAOUTINTRMSK BIT(GC_USB_DOEPMSK_BNAOUTINTRMSK_LSB)
+#define DOEPMSK_EPDISBLDMSK BIT(GC_USB_DOEPMSK_EPDISBLDMSK_LSB)
+#define DOEPMSK_NAKMSK BIT(GC_USB_DOEPMSK_NAKMSK_LSB)
+#define DOEPMSK_NYETMSK BIT(GC_USB_DOEPMSK_NYETMSK_LSB)
+#define DOEPMSK_OUTPKTERRMSK BIT(GC_USB_DOEPMSK_OUTPKTERRMSK_LSB)
+#define DOEPMSK_OUTTKNEPDISMSK BIT(GC_USB_DOEPMSK_OUTTKNEPDISMSK_LSB)
+#define DOEPMSK_SETUPMSK BIT(GC_USB_DOEPMSK_SETUPMSK_LSB)
+#define DOEPMSK_STSPHSERCVDMSK BIT(GC_USB_DOEPMSK_STSPHSERCVDMSK_LSB)
+#define DOEPMSK_XFERCOMPLMSK BIT(GC_USB_DOEPMSK_XFERCOMPLMSK_LSB)
 
 /* Device Endpoint-n IN Interrupt Register bits */
-#define DIEPINT_AHBERR             BIT(GC_USB_DIEPINT0_AHBERR_LSB)
-#define DIEPINT_BBLEERR            BIT(GC_USB_DIEPINT0_BBLEERR_LSB)
-#define DIEPINT_BNAINTR            BIT(GC_USB_DIEPINT0_BNAINTR_LSB)
-#define DIEPINT_EPDISBLD           BIT(GC_USB_DIEPINT0_EPDISBLD_LSB)
-#define DIEPINT_INEPNAKEFF         BIT(GC_USB_DIEPINT0_INEPNAKEFF_LSB)
-#define DIEPINT_INTKNEPMIS         BIT(GC_USB_DIEPINT0_INTKNEPMIS_LSB)
-#define DIEPINT_INTKNTXFEMP        BIT(GC_USB_DIEPINT0_INTKNTXFEMP_LSB)
-#define DIEPINT_NAKINTRPT          BIT(GC_USB_DIEPINT0_NAKINTRPT_LSB)
-#define DIEPINT_NYETINTRPT         BIT(GC_USB_DIEPINT0_NYETINTRPT_LSB)
-#define DIEPINT_PKTDRPSTS          BIT(GC_USB_DIEPINT0_PKTDRPSTS_LSB)
-#define DIEPINT_TIMEOUT            BIT(GC_USB_DIEPINT0_TIMEOUT_LSB)
-#define DIEPINT_TXFEMP             BIT(GC_USB_DIEPINT0_TXFEMP_LSB)
-#define DIEPINT_TXFIFOUNDRN        BIT(GC_USB_DIEPINT0_TXFIFOUNDRN_LSB)
-#define DIEPINT_XFERCOMPL          BIT(GC_USB_DIEPINT0_XFERCOMPL_LSB)
+#define DIEPINT_AHBERR BIT(GC_USB_DIEPINT0_AHBERR_LSB)
+#define DIEPINT_BBLEERR BIT(GC_USB_DIEPINT0_BBLEERR_LSB)
+#define DIEPINT_BNAINTR BIT(GC_USB_DIEPINT0_BNAINTR_LSB)
+#define DIEPINT_EPDISBLD BIT(GC_USB_DIEPINT0_EPDISBLD_LSB)
+#define DIEPINT_INEPNAKEFF BIT(GC_USB_DIEPINT0_INEPNAKEFF_LSB)
+#define DIEPINT_INTKNEPMIS BIT(GC_USB_DIEPINT0_INTKNEPMIS_LSB)
+#define DIEPINT_INTKNTXFEMP BIT(GC_USB_DIEPINT0_INTKNTXFEMP_LSB)
+#define DIEPINT_NAKINTRPT BIT(GC_USB_DIEPINT0_NAKINTRPT_LSB)
+#define DIEPINT_NYETINTRPT BIT(GC_USB_DIEPINT0_NYETINTRPT_LSB)
+#define DIEPINT_PKTDRPSTS BIT(GC_USB_DIEPINT0_PKTDRPSTS_LSB)
+#define DIEPINT_TIMEOUT BIT(GC_USB_DIEPINT0_TIMEOUT_LSB)
+#define DIEPINT_TXFEMP BIT(GC_USB_DIEPINT0_TXFEMP_LSB)
+#define DIEPINT_TXFIFOUNDRN BIT(GC_USB_DIEPINT0_TXFIFOUNDRN_LSB)
+#define DIEPINT_XFERCOMPL BIT(GC_USB_DIEPINT0_XFERCOMPL_LSB)
 
 /* Device Endpoint-n OUT Interrupt Register bits */
-#define DOEPINT_AHBERR             BIT(GC_USB_DOEPINT0_AHBERR_LSB)
-#define DOEPINT_BACK2BACKSETUP     BIT(GC_USB_DOEPINT0_BACK2BACKSETUP_LSB)
-#define DOEPINT_BBLEERR            BIT(GC_USB_DOEPINT0_BBLEERR_LSB)
-#define DOEPINT_BNAINTR            BIT(GC_USB_DOEPINT0_BNAINTR_LSB)
-#define DOEPINT_EPDISBLD           BIT(GC_USB_DOEPINT0_EPDISBLD_LSB)
-#define DOEPINT_NAKINTRPT          BIT(GC_USB_DOEPINT0_NAKINTRPT_LSB)
-#define DOEPINT_NYETINTRPT         BIT(GC_USB_DOEPINT0_NYETINTRPT_LSB)
-#define DOEPINT_OUTPKTERR          BIT(GC_USB_DOEPINT0_OUTPKTERR_LSB)
-#define DOEPINT_OUTTKNEPDIS        BIT(GC_USB_DOEPINT0_OUTTKNEPDIS_LSB)
-#define DOEPINT_PKTDRPSTS          BIT(GC_USB_DOEPINT0_PKTDRPSTS_LSB)
-#define DOEPINT_SETUP              BIT(GC_USB_DOEPINT0_SETUP_LSB)
-#define DOEPINT_STSPHSERCVD        BIT(GC_USB_DOEPINT0_STSPHSERCVD_LSB)
-#define DOEPINT_STUPPKTRCVD        BIT(GC_USB_DOEPINT0_STUPPKTRCVD_LSB)
-#define DOEPINT_XFERCOMPL          BIT(GC_USB_DOEPINT0_XFERCOMPL_LSB)
+#define DOEPINT_AHBERR BIT(GC_USB_DOEPINT0_AHBERR_LSB)
+#define DOEPINT_BACK2BACKSETUP BIT(GC_USB_DOEPINT0_BACK2BACKSETUP_LSB)
+#define DOEPINT_BBLEERR BIT(GC_USB_DOEPINT0_BBLEERR_LSB)
+#define DOEPINT_BNAINTR BIT(GC_USB_DOEPINT0_BNAINTR_LSB)
+#define DOEPINT_EPDISBLD BIT(GC_USB_DOEPINT0_EPDISBLD_LSB)
+#define DOEPINT_NAKINTRPT BIT(GC_USB_DOEPINT0_NAKINTRPT_LSB)
+#define DOEPINT_NYETINTRPT BIT(GC_USB_DOEPINT0_NYETINTRPT_LSB)
+#define DOEPINT_OUTPKTERR BIT(GC_USB_DOEPINT0_OUTPKTERR_LSB)
+#define DOEPINT_OUTTKNEPDIS BIT(GC_USB_DOEPINT0_OUTTKNEPDIS_LSB)
+#define DOEPINT_PKTDRPSTS BIT(GC_USB_DOEPINT0_PKTDRPSTS_LSB)
+#define DOEPINT_SETUP BIT(GC_USB_DOEPINT0_SETUP_LSB)
+#define DOEPINT_STSPHSERCVD BIT(GC_USB_DOEPINT0_STSPHSERCVD_LSB)
+#define DOEPINT_STUPPKTRCVD BIT(GC_USB_DOEPINT0_STUPPKTRCVD_LSB)
+#define DOEPINT_XFERCOMPL BIT(GC_USB_DOEPINT0_XFERCOMPL_LSB)
 
-#define DXEPCTL_EPTYPE_CTRL           (0 << GC_USB_DIEPCTL0_EPTYPE_LSB)
-#define DXEPCTL_EPTYPE_ISO            (1 << GC_USB_DIEPCTL0_EPTYPE_LSB)
-#define DXEPCTL_EPTYPE_BULK           (2 << GC_USB_DIEPCTL0_EPTYPE_LSB)
-#define DXEPCTL_EPTYPE_INT            (3 << GC_USB_DIEPCTL0_EPTYPE_LSB)
-#define DXEPCTL_EPTYPE_MASK           GC_USB_DIEPCTL0_EPTYPE_MASK
-#define DXEPCTL_TXFNUM(n)             ((n) << GC_USB_DIEPCTL1_TXFNUM_LSB)
-#define DXEPCTL_STALL                 BIT(GC_USB_DIEPCTL0_STALL_LSB)
-#define DXEPCTL_CNAK                  BIT(GC_USB_DIEPCTL0_CNAK_LSB)
-#define DXEPCTL_DPID                  BIT(GC_USB_DIEPCTL0_DPID_LSB)
-#define DXEPCTL_SNAK                  BIT(GC_USB_DIEPCTL0_SNAK_LSB)
-#define DXEPCTL_NAKSTS                BIT(GC_USB_DIEPCTL0_NAKSTS_LSB)
-#define DXEPCTL_EPENA                 BIT(GC_USB_DIEPCTL0_EPENA_LSB)
-#define DXEPCTL_EPDIS                 BIT(GC_USB_DIEPCTL0_EPDIS_LSB)
-#define DXEPCTL_USBACTEP              BIT(GC_USB_DIEPCTL0_USBACTEP_LSB)
-#define DXEPCTL_MPS64                 (0 << GC_USB_DIEPCTL0_MPS_LSB)
-#define DXEPCTL_MPS(cnt)              ((cnt) << GC_USB_DIEPCTL1_MPS_LSB)
+#define DXEPCTL_EPTYPE_CTRL (0 << GC_USB_DIEPCTL0_EPTYPE_LSB)
+#define DXEPCTL_EPTYPE_ISO (1 << GC_USB_DIEPCTL0_EPTYPE_LSB)
+#define DXEPCTL_EPTYPE_BULK (2 << GC_USB_DIEPCTL0_EPTYPE_LSB)
+#define DXEPCTL_EPTYPE_INT (3 << GC_USB_DIEPCTL0_EPTYPE_LSB)
+#define DXEPCTL_EPTYPE_MASK GC_USB_DIEPCTL0_EPTYPE_MASK
+#define DXEPCTL_TXFNUM(n) ((n) << GC_USB_DIEPCTL1_TXFNUM_LSB)
+#define DXEPCTL_STALL BIT(GC_USB_DIEPCTL0_STALL_LSB)
+#define DXEPCTL_CNAK BIT(GC_USB_DIEPCTL0_CNAK_LSB)
+#define DXEPCTL_DPID BIT(GC_USB_DIEPCTL0_DPID_LSB)
+#define DXEPCTL_SNAK BIT(GC_USB_DIEPCTL0_SNAK_LSB)
+#define DXEPCTL_NAKSTS BIT(GC_USB_DIEPCTL0_NAKSTS_LSB)
+#define DXEPCTL_EPENA BIT(GC_USB_DIEPCTL0_EPENA_LSB)
+#define DXEPCTL_EPDIS BIT(GC_USB_DIEPCTL0_EPDIS_LSB)
+#define DXEPCTL_USBACTEP BIT(GC_USB_DIEPCTL0_USBACTEP_LSB)
+#define DXEPCTL_MPS64 (0 << GC_USB_DIEPCTL0_MPS_LSB)
+#define DXEPCTL_MPS(cnt) ((cnt) << GC_USB_DIEPCTL1_MPS_LSB)
 
-#define DXEPTSIZ_SUPCNT(n)            ((n) << GC_USB_DOEPTSIZ0_SUPCNT_LSB)
-#define DXEPTSIZ_PKTCNT(n)            ((n) << GC_USB_DIEPTSIZ0_PKTCNT_LSB)
-#define DXEPTSIZ_XFERSIZE(n)          ((n) << GC_USB_DIEPTSIZ0_XFERSIZE_LSB)
-
-#define DOEPDMA_BS_HOST_RDY           (0 << 30)
-#define DOEPDMA_BS_DMA_BSY            (1 << 30)
-#define DOEPDMA_BS_DMA_DONE           (2 << 30)
-#define DOEPDMA_BS_HOST_BSY           (3 << 30)
-#define DOEPDMA_BS_MASK               (3 << 30)
-#define DOEPDMA_RXSTS_MASK            (3 << 28)
-#define DOEPDMA_LAST                  BIT(27)
-#define DOEPDMA_SP                    BIT(26)
-#define DOEPDMA_IOC                   BIT(25)
-#define DOEPDMA_SR                    BIT(24)
-#define DOEPDMA_MTRF                  BIT(23)
-#define DOEPDMA_NAK                   BIT(16)
-#define DOEPDMA_RXBYTES(n)            (((n) & 0xFFFF) << 0)
-#define DOEPDMA_RXBYTES_MASK          (0xFFFF << 0)
-
-#define DIEPDMA_BS_HOST_RDY           (0 << 30)
-#define DIEPDMA_BS_DMA_BSY            (1 << 30)
-#define DIEPDMA_BS_DMA_DONE           (2 << 30)
-#define DIEPDMA_BS_HOST_BSY           (3 << 30)
-#define DIEPDMA_BS_MASK               (3 << 30)
-#define DIEPDMA_TXSTS_MASK            (3 << 28)
-#define DIEPDMA_LAST                  BIT(27)
-#define DIEPDMA_SP                    BIT(26)
-#define DIEPDMA_IOC                   BIT(25)
-#define DIEPDMA_TXBYTES(n)            (((n) & 0xFFFF) << 0)
-#define DIEPDMA_TXBYTES_MASK          (0xFFFF << 0)
+#define DXEPTSIZ_SUPCNT(n) ((n) << GC_USB_DOEPTSIZ0_SUPCNT_LSB)
+#define DXEPTSIZ_PKTCNT(n) ((n) << GC_USB_DIEPTSIZ0_PKTCNT_LSB)
+#define DXEPTSIZ_XFERSIZE(n) ((n) << GC_USB_DIEPTSIZ0_XFERSIZE_LSB)
 
+#define DOEPDMA_BS_HOST_RDY (0 << 30)
+#define DOEPDMA_BS_DMA_BSY (1 << 30)
+#define DOEPDMA_BS_DMA_DONE (2 << 30)
+#define DOEPDMA_BS_HOST_BSY (3 << 30)
+#define DOEPDMA_BS_MASK (3 << 30)
+#define DOEPDMA_RXSTS_MASK (3 << 28)
+#define DOEPDMA_LAST BIT(27)
+#define DOEPDMA_SP BIT(26)
+#define DOEPDMA_IOC BIT(25)
+#define DOEPDMA_SR BIT(24)
+#define DOEPDMA_MTRF BIT(23)
+#define DOEPDMA_NAK BIT(16)
+#define DOEPDMA_RXBYTES(n) (((n)&0xFFFF) << 0)
+#define DOEPDMA_RXBYTES_MASK (0xFFFF << 0)
 
+#define DIEPDMA_BS_HOST_RDY (0 << 30)
+#define DIEPDMA_BS_DMA_BSY (1 << 30)
+#define DIEPDMA_BS_DMA_DONE (2 << 30)
+#define DIEPDMA_BS_HOST_BSY (3 << 30)
+#define DIEPDMA_BS_MASK (3 << 30)
+#define DIEPDMA_TXSTS_MASK (3 << 28)
+#define DIEPDMA_LAST BIT(27)
+#define DIEPDMA_SP BIT(26)
+#define DIEPDMA_IOC BIT(25)
+#define DIEPDMA_TXBYTES(n) (((n)&0xFFFF) << 0)
+#define DIEPDMA_TXBYTES_MASK (0xFFFF << 0)
 
 /* Register defs referenced from DWC block in CR50. This is not a native
  * ST block, so we'll use this modified regdefs list.
  */
 
-#define GC_USB_FS_BASE_ADDR                        0x50000000
-#define GC_USB_HS_BASE_ADDR                        0x40040000
+#define GC_USB_FS_BASE_ADDR 0x50000000
+#define GC_USB_HS_BASE_ADDR 0x40040000
 #ifdef CONFIG_USB_DWC_FS
-#define GC_USB_BASE_ADDR                         GC_USB_FS_BASE_ADDR
+#define GC_USB_BASE_ADDR GC_USB_FS_BASE_ADDR
 #else
-#define GC_USB_BASE_ADDR                         GC_USB_HS_BASE_ADDR
+#define GC_USB_BASE_ADDR GC_USB_HS_BASE_ADDR
 #endif
 
-#define GC_USB_GOTGCTL_OFFSET                    0x0
-#define GC_USB_GOTGCTL_DEFAULT                   0x0
-#define GC_USB_GOTGINT_OFFSET                    0x4
-#define GC_USB_GOTGINT_DEFAULT                   0x0
-#define GC_USB_GAHBCFG_OFFSET                    0x8
-#define GC_USB_GAHBCFG_DEFAULT                   0x0
-#define GC_USB_GUSBCFG_OFFSET                    0xc
-#define GC_USB_GUSBCFG_DEFAULT                   0x0
-#define GC_USB_GRSTCTL_OFFSET                    0x10
-#define GC_USB_GRSTCTL_DEFAULT                   0x0
-#define GC_USB_GINTSTS_OFFSET                    0x14
-#define GC_USB_GINTSTS_DEFAULT                   0x0
-#define GC_USB_GINTMSK_OFFSET                    0x18
-#define GC_USB_GINTMSK_DEFAULT                   0x0
-#define GC_USB_GRXSTSR_OFFSET                    0x1c
-#define GC_USB_GRXSTSR_DEFAULT                   0x0
-#define GC_USB_GRXSTSP_OFFSET                    0x20
-#define GC_USB_GRXSTSP_DEFAULT                   0x0
-#define GC_USB_GRXFSIZ_OFFSET                    0x24
-#define GC_USB_GRXFSIZ_DEFAULT                   0x0
-#define GC_USB_GNPTXFSIZ_OFFSET                  0x28
-#define GC_USB_GNPTXFSIZ_DEFAULT                 0x0
+#define GC_USB_GOTGCTL_OFFSET 0x0
+#define GC_USB_GOTGCTL_DEFAULT 0x0
+#define GC_USB_GOTGINT_OFFSET 0x4
+#define GC_USB_GOTGINT_DEFAULT 0x0
+#define GC_USB_GAHBCFG_OFFSET 0x8
+#define GC_USB_GAHBCFG_DEFAULT 0x0
+#define GC_USB_GUSBCFG_OFFSET 0xc
+#define GC_USB_GUSBCFG_DEFAULT 0x0
+#define GC_USB_GRSTCTL_OFFSET 0x10
+#define GC_USB_GRSTCTL_DEFAULT 0x0
+#define GC_USB_GINTSTS_OFFSET 0x14
+#define GC_USB_GINTSTS_DEFAULT 0x0
+#define GC_USB_GINTMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_DEFAULT 0x0
+#define GC_USB_GRXSTSR_OFFSET 0x1c
+#define GC_USB_GRXSTSR_DEFAULT 0x0
+#define GC_USB_GRXSTSP_OFFSET 0x20
+#define GC_USB_GRXSTSP_DEFAULT 0x0
+#define GC_USB_GRXFSIZ_OFFSET 0x24
+#define GC_USB_GRXFSIZ_DEFAULT 0x0
+#define GC_USB_GNPTXFSIZ_OFFSET 0x28
+#define GC_USB_GNPTXFSIZ_DEFAULT 0x0
 
-#define GC_USB_GCCFG_OFFSET                      0x38
-#define GC_USB_GCCFG_DEFAULT                     0x0
-#define GC_USB_GUID_OFFSET                       0x3c
-#define GC_USB_GUID_DEFAULT                      0x0
-#define GC_USB_GSNPSID_OFFSET                    0x40
-#define GC_USB_GSNPSID_DEFAULT                   0x0
-#define GC_USB_GHWCFG1_OFFSET                    0x44
-#define GC_USB_GHWCFG1_DEFAULT                   0x0
-#define GC_USB_GHWCFG2_OFFSET                    0x48
-#define GC_USB_GHWCFG2_DEFAULT                   0x0
-#define GC_USB_GHWCFG3_OFFSET                    0x4c
-#define GC_USB_GHWCFG3_DEFAULT                   0x0
-#define GC_USB_GHWCFG4_OFFSET                    0x50
-#define GC_USB_GHWCFG4_DEFAULT                   0x0
-#define GC_USB_GDFIFOCFG_OFFSET                  0x5c
-#define GC_USB_GDFIFOCFG_DEFAULT                 0x0
-#define GC_USB_DIEPTXF1_OFFSET                   0x104
-#define GC_USB_DIEPTXF1_DEFAULT                  0x1000
-#define GC_USB_DIEPTXF2_OFFSET                   0x108
-#define GC_USB_DIEPTXF2_DEFAULT                  0x0
-#define GC_USB_DIEPTXF3_OFFSET                   0x10c
-#define GC_USB_DIEPTXF3_DEFAULT                  0x0
-#define GC_USB_DIEPTXF4_OFFSET                   0x110
-#define GC_USB_DIEPTXF4_DEFAULT                  0x0
-#define GC_USB_DIEPTXF5_OFFSET                   0x114
-#define GC_USB_DIEPTXF5_DEFAULT                  0x0
-#define GC_USB_DIEPTXF6_OFFSET                   0x118
-#define GC_USB_DIEPTXF6_DEFAULT                  0x0
-#define GC_USB_DIEPTXF7_OFFSET                   0x11c
-#define GC_USB_DIEPTXF7_DEFAULT                  0x0
-#define GC_USB_DIEPTXF8_OFFSET                   0x120
-#define GC_USB_DIEPTXF8_DEFAULT                  0x0
-#define GC_USB_DIEPTXF9_OFFSET                   0x124
-#define GC_USB_DIEPTXF9_DEFAULT                  0x0
-#define GC_USB_DIEPTXF10_OFFSET                  0x128
-#define GC_USB_DIEPTXF10_DEFAULT                 0x0
-#define GC_USB_DIEPTXF11_OFFSET                  0x12c
-#define GC_USB_DIEPTXF11_DEFAULT                 0x0
-#define GC_USB_DIEPTXF12_OFFSET                  0x130
-#define GC_USB_DIEPTXF12_DEFAULT                 0x0
-#define GC_USB_DIEPTXF13_OFFSET                  0x134
-#define GC_USB_DIEPTXF13_DEFAULT                 0x0
-#define GC_USB_DIEPTXF14_OFFSET                  0x138
-#define GC_USB_DIEPTXF14_DEFAULT                 0x0
-#define GC_USB_DIEPTXF15_OFFSET                  0x13c
-#define GC_USB_DIEPTXF15_DEFAULT                 0x0
-#define GC_USB_DCFG_OFFSET                       0x800
-#define GC_USB_DCFG_DEFAULT                      0x8000000
-#define GC_USB_DCTL_OFFSET                       0x804
-#define GC_USB_DCTL_DEFAULT                      0x0
-#define GC_USB_DSTS_OFFSET                       0x808
-#define GC_USB_DSTS_DEFAULT                      0x0
-#define GC_USB_DIEPMSK_OFFSET                    0x810
-#define GC_USB_DIEPMSK_DEFAULT                   0x80
-#define GC_USB_DOEPMSK_OFFSET                    0x814
-#define GC_USB_DOEPMSK_DEFAULT                   0x0
-#define GC_USB_DAINT_OFFSET                      0x818
-#define GC_USB_DAINT_DEFAULT                     0x0
-#define GC_USB_DAINTMSK_OFFSET                   0x81c
-#define GC_USB_DAINTMSK_DEFAULT                  0x0
-#define GC_USB_DVBUSDIS_OFFSET                   0x828
-#define GC_USB_DVBUSDIS_DEFAULT                  0x0
-#define GC_USB_DVBUSPULSE_OFFSET                 0x82c
-#define GC_USB_DVBUSPULSE_DEFAULT                0x0
-#define GC_USB_DTHRCTL_OFFSET                    0x830
-#define GC_USB_DTHRCTL_DEFAULT                   0x0
-#define GC_USB_DIEPEMPMSK_OFFSET                 0x834
-#define GC_USB_DIEPEMPMSK_DEFAULT                0x0
-#define GC_USB_DIEPCTL0_OFFSET                   0x900
-#define GC_USB_DIEPCTL0_DEFAULT                  0x0
-#define GC_USB_DIEPINT0_OFFSET                   0x908
-#define GC_USB_DIEPINT0_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ0_OFFSET                  0x910
-#define GC_USB_DIEPTSIZ0_DEFAULT                 0x0
-#define GC_USB_DIEPDMA0_OFFSET                   0x914
-#define GC_USB_DIEPDMA0_DEFAULT                  0x0
-#define GC_USB_DTXFSTS0_OFFSET                   0x918
-#define GC_USB_DTXFSTS0_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB0_OFFSET                  0x91c
-#define GC_USB_DIEPDMAB0_DEFAULT                 0x0
-#define GC_USB_DIEPCTL1_OFFSET                   0x920
-#define GC_USB_DIEPCTL1_DEFAULT                  0x0
-#define GC_USB_DIEPINT1_OFFSET                   0x928
-#define GC_USB_DIEPINT1_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ1_OFFSET                  0x930
-#define GC_USB_DIEPTSIZ1_DEFAULT                 0x0
-#define GC_USB_DIEPDMA1_OFFSET                   0x934
-#define GC_USB_DIEPDMA1_DEFAULT                  0x0
-#define GC_USB_DTXFSTS1_OFFSET                   0x938
-#define GC_USB_DTXFSTS1_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB1_OFFSET                  0x93c
-#define GC_USB_DIEPDMAB1_DEFAULT                 0x0
-#define GC_USB_DIEPCTL2_OFFSET                   0x940
-#define GC_USB_DIEPCTL2_DEFAULT                  0x0
-#define GC_USB_DIEPINT2_OFFSET                   0x948
-#define GC_USB_DIEPINT2_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ2_OFFSET                  0x950
-#define GC_USB_DIEPTSIZ2_DEFAULT                 0x0
-#define GC_USB_DIEPDMA2_OFFSET                   0x954
-#define GC_USB_DIEPDMA2_DEFAULT                  0x0
-#define GC_USB_DTXFSTS2_OFFSET                   0x958
-#define GC_USB_DTXFSTS2_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB2_OFFSET                  0x95c
-#define GC_USB_DIEPDMAB2_DEFAULT                 0x0
-#define GC_USB_DIEPCTL3_OFFSET                   0x960
-#define GC_USB_DIEPCTL3_DEFAULT                  0x0
-#define GC_USB_DIEPINT3_OFFSET                   0x968
-#define GC_USB_DIEPINT3_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ3_OFFSET                  0x970
-#define GC_USB_DIEPTSIZ3_DEFAULT                 0x0
-#define GC_USB_DIEPDMA3_OFFSET                   0x974
-#define GC_USB_DIEPDMA3_DEFAULT                  0x0
-#define GC_USB_DTXFSTS3_OFFSET                   0x978
-#define GC_USB_DTXFSTS3_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB3_OFFSET                  0x97c
-#define GC_USB_DIEPDMAB3_DEFAULT                 0x0
-#define GC_USB_DIEPCTL4_OFFSET                   0x980
-#define GC_USB_DIEPCTL4_DEFAULT                  0x0
-#define GC_USB_DIEPINT4_OFFSET                   0x988
-#define GC_USB_DIEPINT4_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ4_OFFSET                  0x990
-#define GC_USB_DIEPTSIZ4_DEFAULT                 0x0
-#define GC_USB_DIEPDMA4_OFFSET                   0x994
-#define GC_USB_DIEPDMA4_DEFAULT                  0x0
-#define GC_USB_DTXFSTS4_OFFSET                   0x998
-#define GC_USB_DTXFSTS4_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB4_OFFSET                  0x99c
-#define GC_USB_DIEPDMAB4_DEFAULT                 0x0
-#define GC_USB_DIEPCTL5_OFFSET                   0x9a0
-#define GC_USB_DIEPCTL5_DEFAULT                  0x0
-#define GC_USB_DIEPINT5_OFFSET                   0x9a8
-#define GC_USB_DIEPINT5_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ5_OFFSET                  0x9b0
-#define GC_USB_DIEPTSIZ5_DEFAULT                 0x0
-#define GC_USB_DIEPDMA5_OFFSET                   0x9b4
-#define GC_USB_DIEPDMA5_DEFAULT                  0x0
-#define GC_USB_DTXFSTS5_OFFSET                   0x9b8
-#define GC_USB_DTXFSTS5_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB5_OFFSET                  0x9bc
-#define GC_USB_DIEPDMAB5_DEFAULT                 0x0
-#define GC_USB_DIEPCTL6_OFFSET                   0x9c0
-#define GC_USB_DIEPCTL6_DEFAULT                  0x0
-#define GC_USB_DIEPINT6_OFFSET                   0x9c8
-#define GC_USB_DIEPINT6_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ6_OFFSET                  0x9d0
-#define GC_USB_DIEPTSIZ6_DEFAULT                 0x0
-#define GC_USB_DIEPDMA6_OFFSET                   0x9d4
-#define GC_USB_DIEPDMA6_DEFAULT                  0x0
-#define GC_USB_DTXFSTS6_OFFSET                   0x9d8
-#define GC_USB_DTXFSTS6_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB6_OFFSET                  0x9dc
-#define GC_USB_DIEPDMAB6_DEFAULT                 0x0
-#define GC_USB_DIEPCTL7_OFFSET                   0x9e0
-#define GC_USB_DIEPCTL7_DEFAULT                  0x0
-#define GC_USB_DIEPINT7_OFFSET                   0x9e8
-#define GC_USB_DIEPINT7_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ7_OFFSET                  0x9f0
-#define GC_USB_DIEPTSIZ7_DEFAULT                 0x0
-#define GC_USB_DIEPDMA7_OFFSET                   0x9f4
-#define GC_USB_DIEPDMA7_DEFAULT                  0x0
-#define GC_USB_DTXFSTS7_OFFSET                   0x9f8
-#define GC_USB_DTXFSTS7_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB7_OFFSET                  0x9fc
-#define GC_USB_DIEPDMAB7_DEFAULT                 0x0
-#define GC_USB_DIEPCTL8_OFFSET                   0xa00
-#define GC_USB_DIEPCTL8_DEFAULT                  0x0
-#define GC_USB_DIEPINT8_OFFSET                   0xa08
-#define GC_USB_DIEPINT8_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ8_OFFSET                  0xa10
-#define GC_USB_DIEPTSIZ8_DEFAULT                 0x0
-#define GC_USB_DIEPDMA8_OFFSET                   0xa14
-#define GC_USB_DIEPDMA8_DEFAULT                  0x0
-#define GC_USB_DTXFSTS8_OFFSET                   0xa18
-#define GC_USB_DTXFSTS8_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB8_OFFSET                  0xa1c
-#define GC_USB_DIEPDMAB8_DEFAULT                 0x0
-#define GC_USB_DIEPCTL9_OFFSET                   0xa20
-#define GC_USB_DIEPCTL9_DEFAULT                  0x0
-#define GC_USB_DIEPINT9_OFFSET                   0xa28
-#define GC_USB_DIEPINT9_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ9_OFFSET                  0xa30
-#define GC_USB_DIEPTSIZ9_DEFAULT                 0x0
-#define GC_USB_DIEPDMA9_OFFSET                   0xa34
-#define GC_USB_DIEPDMA9_DEFAULT                  0x0
-#define GC_USB_DTXFSTS9_OFFSET                   0xa38
-#define GC_USB_DTXFSTS9_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB9_OFFSET                  0xa3c
-#define GC_USB_DIEPDMAB9_DEFAULT                 0x0
-#define GC_USB_DIEPCTL10_OFFSET                  0xa40
-#define GC_USB_DIEPCTL10_DEFAULT                 0x0
-#define GC_USB_DIEPINT10_OFFSET                  0xa48
-#define GC_USB_DIEPINT10_DEFAULT                 0x0
-#define GC_USB_DIEPTSIZ10_OFFSET                 0xa50
-#define GC_USB_DIEPTSIZ10_DEFAULT                0x0
-#define GC_USB_DIEPDMA10_OFFSET                  0xa54
-#define GC_USB_DIEPDMA10_DEFAULT                 0x0
-#define GC_USB_DTXFSTS10_OFFSET                  0xa58
-#define GC_USB_DTXFSTS10_DEFAULT                 0x0
-#define GC_USB_DIEPDMAB10_OFFSET                 0xa5c
-#define GC_USB_DIEPDMAB10_DEFAULT                0x0
-#define GC_USB_DIEPCTL11_OFFSET                  0xa60
-#define GC_USB_DIEPCTL11_DEFAULT                 0x0
-#define GC_USB_DIEPINT11_OFFSET                  0xa68
-#define GC_USB_DIEPINT11_DEFAULT                 0x0
-#define GC_USB_DIEPTSIZ11_OFFSET                 0xa70
-#define GC_USB_DIEPTSIZ11_DEFAULT                0x0
-#define GC_USB_DIEPDMA11_OFFSET                  0xa74
-#define GC_USB_DIEPDMA11_DEFAULT                 0x0
-#define GC_USB_DTXFSTS11_OFFSET                  0xa78
-#define GC_USB_DTXFSTS11_DEFAULT                 0x0
-#define GC_USB_DIEPDMAB11_OFFSET                 0xa7c
-#define GC_USB_DIEPDMAB11_DEFAULT                0x0
-#define GC_USB_DIEPCTL12_OFFSET                  0xa80
-#define GC_USB_DIEPCTL12_DEFAULT                 0x0
-#define GC_USB_DIEPINT12_OFFSET                  0xa88
-#define GC_USB_DIEPINT12_DEFAULT                 0x0
-#define GC_USB_DIEPTSIZ12_OFFSET                 0xa90
-#define GC_USB_DIEPTSIZ12_DEFAULT                0x0
-#define GC_USB_DIEPDMA12_OFFSET                  0xa94
-#define GC_USB_DIEPDMA12_DEFAULT                 0x0
-#define GC_USB_DTXFSTS12_OFFSET                  0xa98
-#define GC_USB_DTXFSTS12_DEFAULT                 0x0
-#define GC_USB_DIEPDMAB12_OFFSET                 0xa9c
-#define GC_USB_DIEPDMAB12_DEFAULT                0x0
-#define GC_USB_DIEPCTL13_OFFSET                  0xaa0
-#define GC_USB_DIEPCTL13_DEFAULT                 0x0
-#define GC_USB_DIEPINT13_OFFSET                  0xaa8
-#define GC_USB_DIEPINT13_DEFAULT                 0x0
-#define GC_USB_DIEPTSIZ13_OFFSET                 0xab0
-#define GC_USB_DIEPTSIZ13_DEFAULT                0x0
-#define GC_USB_DIEPDMA13_OFFSET                  0xab4
-#define GC_USB_DIEPDMA13_DEFAULT                 0x0
-#define GC_USB_DTXFSTS13_OFFSET                  0xab8
-#define GC_USB_DTXFSTS13_DEFAULT                 0x0
-#define GC_USB_DIEPDMAB13_OFFSET                 0xabc
-#define GC_USB_DIEPDMAB13_DEFAULT                0x0
-#define GC_USB_DIEPCTL14_OFFSET                  0xac0
-#define GC_USB_DIEPCTL14_DEFAULT                 0x0
-#define GC_USB_DIEPINT14_OFFSET                  0xac8
-#define GC_USB_DIEPINT14_DEFAULT                 0x0
-#define GC_USB_DIEPTSIZ14_OFFSET                 0xad0
-#define GC_USB_DIEPTSIZ14_DEFAULT                0x0
-#define GC_USB_DIEPDMA14_OFFSET                  0xad4
-#define GC_USB_DIEPDMA14_DEFAULT                 0x0
-#define GC_USB_DTXFSTS14_OFFSET                  0xad8
-#define GC_USB_DTXFSTS14_DEFAULT                 0x0
-#define GC_USB_DIEPDMAB14_OFFSET                 0xadc
-#define GC_USB_DIEPDMAB14_DEFAULT                0x0
-#define GC_USB_DIEPCTL15_OFFSET                  0xae0
-#define GC_USB_DIEPCTL15_DEFAULT                 0x0
-#define GC_USB_DIEPINT15_OFFSET                  0xae8
-#define GC_USB_DIEPINT15_DEFAULT                 0x0
-#define GC_USB_DIEPTSIZ15_OFFSET                 0xaf0
-#define GC_USB_DIEPTSIZ15_DEFAULT                0x0
-#define GC_USB_DIEPDMA15_OFFSET                  0xaf4
-#define GC_USB_DIEPDMA15_DEFAULT                 0x0
-#define GC_USB_DTXFSTS15_OFFSET                  0xaf8
-#define GC_USB_DTXFSTS15_DEFAULT                 0x0
-#define GC_USB_DIEPDMAB15_OFFSET                 0xafc
-#define GC_USB_DIEPDMAB15_DEFAULT                0x0
-#define GC_USB_DOEPCTL0_OFFSET                   0xb00
-#define GC_USB_DOEPCTL0_DEFAULT                  0x0
-#define GC_USB_DOEPINT0_OFFSET                   0xb08
-#define GC_USB_DOEPINT0_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ0_OFFSET                  0xb10
-#define GC_USB_DOEPTSIZ0_DEFAULT                 0x0
-#define GC_USB_DOEPDMA0_OFFSET                   0xb14
-#define GC_USB_DOEPDMA0_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB0_OFFSET                  0xb1c
-#define GC_USB_DOEPDMAB0_DEFAULT                 0x0
-#define GC_USB_DOEPCTL1_OFFSET                   0xb20
-#define GC_USB_DOEPCTL1_DEFAULT                  0x0
-#define GC_USB_DOEPINT1_OFFSET                   0xb28
-#define GC_USB_DOEPINT1_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ1_OFFSET                  0xb30
-#define GC_USB_DOEPTSIZ1_DEFAULT                 0x0
-#define GC_USB_DOEPDMA1_OFFSET                   0xb34
-#define GC_USB_DOEPDMA1_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB1_OFFSET                  0xb3c
-#define GC_USB_DOEPDMAB1_DEFAULT                 0x0
-#define GC_USB_DOEPCTL2_OFFSET                   0xb40
-#define GC_USB_DOEPCTL2_DEFAULT                  0x0
-#define GC_USB_DOEPINT2_OFFSET                   0xb48
-#define GC_USB_DOEPINT2_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ2_OFFSET                  0xb50
-#define GC_USB_DOEPTSIZ2_DEFAULT                 0x0
-#define GC_USB_DOEPDMA2_OFFSET                   0xb54
-#define GC_USB_DOEPDMA2_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB2_OFFSET                  0xb5c
-#define GC_USB_DOEPDMAB2_DEFAULT                 0x0
-#define GC_USB_DOEPCTL3_OFFSET                   0xb60
-#define GC_USB_DOEPCTL3_DEFAULT                  0x0
-#define GC_USB_DOEPINT3_OFFSET                   0xb68
-#define GC_USB_DOEPINT3_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ3_OFFSET                  0xb70
-#define GC_USB_DOEPTSIZ3_DEFAULT                 0x0
-#define GC_USB_DOEPDMA3_OFFSET                   0xb74
-#define GC_USB_DOEPDMA3_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB3_OFFSET                  0xb7c
-#define GC_USB_DOEPDMAB3_DEFAULT                 0x0
-#define GC_USB_DOEPCTL4_OFFSET                   0xb80
-#define GC_USB_DOEPCTL4_DEFAULT                  0x0
-#define GC_USB_DOEPINT4_OFFSET                   0xb88
-#define GC_USB_DOEPINT4_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ4_OFFSET                  0xb90
-#define GC_USB_DOEPTSIZ4_DEFAULT                 0x0
-#define GC_USB_DOEPDMA4_OFFSET                   0xb94
-#define GC_USB_DOEPDMA4_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB4_OFFSET                  0xb9c
-#define GC_USB_DOEPDMAB4_DEFAULT                 0x0
-#define GC_USB_DOEPCTL5_OFFSET                   0xba0
-#define GC_USB_DOEPCTL5_DEFAULT                  0x0
-#define GC_USB_DOEPINT5_OFFSET                   0xba8
-#define GC_USB_DOEPINT5_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ5_OFFSET                  0xbb0
-#define GC_USB_DOEPTSIZ5_DEFAULT                 0x0
-#define GC_USB_DOEPDMA5_OFFSET                   0xbb4
-#define GC_USB_DOEPDMA5_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB5_OFFSET                  0xbbc
-#define GC_USB_DOEPDMAB5_DEFAULT                 0x0
-#define GC_USB_DOEPCTL6_OFFSET                   0xbc0
-#define GC_USB_DOEPCTL6_DEFAULT                  0x0
-#define GC_USB_DOEPINT6_OFFSET                   0xbc8
-#define GC_USB_DOEPINT6_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ6_OFFSET                  0xbd0
-#define GC_USB_DOEPTSIZ6_DEFAULT                 0x0
-#define GC_USB_DOEPDMA6_OFFSET                   0xbd4
-#define GC_USB_DOEPDMA6_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB6_OFFSET                  0xbdc
-#define GC_USB_DOEPDMAB6_DEFAULT                 0x0
-#define GC_USB_DOEPCTL7_OFFSET                   0xbe0
-#define GC_USB_DOEPCTL7_DEFAULT                  0x0
-#define GC_USB_DOEPINT7_OFFSET                   0xbe8
-#define GC_USB_DOEPINT7_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ7_OFFSET                  0xbf0
-#define GC_USB_DOEPTSIZ7_DEFAULT                 0x0
-#define GC_USB_DOEPDMA7_OFFSET                   0xbf4
-#define GC_USB_DOEPDMA7_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB7_OFFSET                  0xbfc
-#define GC_USB_DOEPDMAB7_DEFAULT                 0x0
-#define GC_USB_DOEPCTL8_OFFSET                   0xc00
-#define GC_USB_DOEPCTL8_DEFAULT                  0x0
-#define GC_USB_DOEPINT8_OFFSET                   0xc08
-#define GC_USB_DOEPINT8_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ8_OFFSET                  0xc10
-#define GC_USB_DOEPTSIZ8_DEFAULT                 0x0
-#define GC_USB_DOEPDMA8_OFFSET                   0xc14
-#define GC_USB_DOEPDMA8_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB8_OFFSET                  0xc1c
-#define GC_USB_DOEPDMAB8_DEFAULT                 0x0
-#define GC_USB_DOEPCTL9_OFFSET                   0xc20
-#define GC_USB_DOEPCTL9_DEFAULT                  0x0
-#define GC_USB_DOEPINT9_OFFSET                   0xc28
-#define GC_USB_DOEPINT9_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ9_OFFSET                  0xc30
-#define GC_USB_DOEPTSIZ9_DEFAULT                 0x0
-#define GC_USB_DOEPDMA9_OFFSET                   0xc34
-#define GC_USB_DOEPDMA9_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB9_OFFSET                  0xc3c
-#define GC_USB_DOEPDMAB9_DEFAULT                 0x0
-#define GC_USB_DOEPCTL10_OFFSET                  0xc40
-#define GC_USB_DOEPCTL10_DEFAULT                 0x0
-#define GC_USB_DOEPINT10_OFFSET                  0xc48
-#define GC_USB_DOEPINT10_DEFAULT                 0x0
-#define GC_USB_DOEPTSIZ10_OFFSET                 0xc50
-#define GC_USB_DOEPTSIZ10_DEFAULT                0x0
-#define GC_USB_DOEPDMA10_OFFSET                  0xc54
-#define GC_USB_DOEPDMA10_DEFAULT                 0x0
-#define GC_USB_DOEPDMAB10_OFFSET                 0xc5c
-#define GC_USB_DOEPDMAB10_DEFAULT                0x0
-#define GC_USB_DOEPCTL11_OFFSET                  0xc60
-#define GC_USB_DOEPCTL11_DEFAULT                 0x0
-#define GC_USB_DOEPINT11_OFFSET                  0xc68
-#define GC_USB_DOEPINT11_DEFAULT                 0x0
-#define GC_USB_DOEPTSIZ11_OFFSET                 0xc70
-#define GC_USB_DOEPTSIZ11_DEFAULT                0x0
-#define GC_USB_DOEPDMA11_OFFSET                  0xc74
-#define GC_USB_DOEPDMA11_DEFAULT                 0x0
-#define GC_USB_DOEPDMAB11_OFFSET                 0xc7c
-#define GC_USB_DOEPDMAB11_DEFAULT                0x0
-#define GC_USB_DOEPCTL12_OFFSET                  0xc80
-#define GC_USB_DOEPCTL12_DEFAULT                 0x0
-#define GC_USB_DOEPINT12_OFFSET                  0xc88
-#define GC_USB_DOEPINT12_DEFAULT                 0x0
-#define GC_USB_DOEPTSIZ12_OFFSET                 0xc90
-#define GC_USB_DOEPTSIZ12_DEFAULT                0x0
-#define GC_USB_DOEPDMA12_OFFSET                  0xc94
-#define GC_USB_DOEPDMA12_DEFAULT                 0x0
-#define GC_USB_DOEPDMAB12_OFFSET                 0xc9c
-#define GC_USB_DOEPDMAB12_DEFAULT                0x0
-#define GC_USB_DOEPCTL13_OFFSET                  0xca0
-#define GC_USB_DOEPCTL13_DEFAULT                 0x0
-#define GC_USB_DOEPINT13_OFFSET                  0xca8
-#define GC_USB_DOEPINT13_DEFAULT                 0x0
-#define GC_USB_DOEPTSIZ13_OFFSET                 0xcb0
-#define GC_USB_DOEPTSIZ13_DEFAULT                0x0
-#define GC_USB_DOEPDMA13_OFFSET                  0xcb4
-#define GC_USB_DOEPDMA13_DEFAULT                 0x0
-#define GC_USB_DOEPDMAB13_OFFSET                 0xcbc
-#define GC_USB_DOEPDMAB13_DEFAULT                0x0
-#define GC_USB_DOEPCTL14_OFFSET                  0xcc0
-#define GC_USB_DOEPCTL14_DEFAULT                 0x0
-#define GC_USB_DOEPINT14_OFFSET                  0xcc8
-#define GC_USB_DOEPINT14_DEFAULT                 0x0
-#define GC_USB_DOEPTSIZ14_OFFSET                 0xcd0
-#define GC_USB_DOEPTSIZ14_DEFAULT                0x0
-#define GC_USB_DOEPDMA14_OFFSET                  0xcd4
-#define GC_USB_DOEPDMA14_DEFAULT                 0x0
-#define GC_USB_DOEPDMAB14_OFFSET                 0xcdc
-#define GC_USB_DOEPDMAB14_DEFAULT                0x0
-#define GC_USB_DOEPCTL15_OFFSET                  0xce0
-#define GC_USB_DOEPCTL15_DEFAULT                 0x0
-#define GC_USB_DOEPINT15_OFFSET                  0xce8
-#define GC_USB_DOEPINT15_DEFAULT                 0x0
-#define GC_USB_DOEPTSIZ15_OFFSET                 0xcf0
-#define GC_USB_DOEPTSIZ15_DEFAULT                0x0
-#define GC_USB_DOEPDMA15_OFFSET                  0xcf4
-#define GC_USB_DOEPDMA15_DEFAULT                 0x0
-#define GC_USB_DOEPDMAB15_OFFSET                 0xcfc
-#define GC_USB_DOEPDMAB15_DEFAULT                0x0
-#define GC_USB_PCGCCTL_OFFSET                    0xe00
-#define GC_USB_PCGCCTL_DEFAULT                   0x0
-#define GC_USB_DFIFO_OFFSET                      0x20000
-#define GC_USB_GOTGCTL_BVALIDOVEN_LSB            0x6
-#define GC_USB_GOTGCTL_BVALIDOVEN_MASK           0x40
-#define GC_USB_GOTGCTL_BVALIDOVEN_SIZE           0x1
-#define GC_USB_GOTGCTL_BVALIDOVEN_DEFAULT        0x0
-#define GC_USB_GOTGCTL_BVALIDOVEN_OFFSET         0x0
-#define GC_USB_GOTGCTL_BVALIDOVVAL_LSB           0x7
-#define GC_USB_GOTGCTL_BVALIDOVVAL_MASK          0x80
-#define GC_USB_GOTGCTL_BVALIDOVVAL_SIZE          0x1
-#define GC_USB_GOTGCTL_BVALIDOVVAL_DEFAULT       0x0
-#define GC_USB_GOTGCTL_BVALIDOVVAL_OFFSET        0x0
-#define GC_USB_GOTGCTL_CONIDSTS_LSB              0x10
-#define GC_USB_GOTGCTL_CONIDSTS_MASK             0x10000
-#define GC_USB_GOTGCTL_CONIDSTS_SIZE             0x1
-#define GC_USB_GOTGCTL_CONIDSTS_DEFAULT          0x0
-#define GC_USB_GOTGCTL_CONIDSTS_OFFSET           0x0
-#define GC_USB_GOTGCTL_BSESVLD_LSB               0x13
-#define GC_USB_GOTGCTL_BSESVLD_MASK              0x80000
-#define GC_USB_GOTGCTL_BSESVLD_SIZE              0x1
-#define GC_USB_GOTGCTL_BSESVLD_DEFAULT           0x0
-#define GC_USB_GOTGCTL_BSESVLD_OFFSET            0x0
-#define GC_USB_GOTGCTL_OTGVER_LSB                0x14
-#define GC_USB_GOTGCTL_OTGVER_MASK               0x100000
-#define GC_USB_GOTGCTL_OTGVER_SIZE               0x1
-#define GC_USB_GOTGCTL_OTGVER_DEFAULT            0x0
-#define GC_USB_GOTGCTL_OTGVER_OFFSET             0x0
-#define GC_USB_GOTGCTL_CURMOD_LSB                0x15
-#define GC_USB_GOTGCTL_CURMOD_MASK               0x200000
-#define GC_USB_GOTGCTL_CURMOD_SIZE               0x1
-#define GC_USB_GOTGCTL_CURMOD_DEFAULT            0x0
-#define GC_USB_GOTGCTL_CURMOD_OFFSET             0x0
-#define GC_USB_GOTGINT_SESENDDET_LSB             0x2
-#define GC_USB_GOTGINT_SESENDDET_MASK            0x4
-#define GC_USB_GOTGINT_SESENDDET_SIZE            0x1
-#define GC_USB_GOTGINT_SESENDDET_DEFAULT         0x0
-#define GC_USB_GOTGINT_SESENDDET_OFFSET          0x4
-#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_LSB      0x8
-#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_MASK     0x100
-#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_SIZE     0x1
-#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_DEFAULT  0x0
-#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_OFFSET   0x4
-#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_LSB      0x9
-#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_MASK     0x200
-#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_SIZE     0x1
-#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_DEFAULT  0x0
-#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_OFFSET   0x4
-#define GC_USB_GOTGINT_HSTNEGDET_LSB             0x11
-#define GC_USB_GOTGINT_HSTNEGDET_MASK            0x20000
-#define GC_USB_GOTGINT_HSTNEGDET_SIZE            0x1
-#define GC_USB_GOTGINT_HSTNEGDET_DEFAULT         0x0
-#define GC_USB_GOTGINT_HSTNEGDET_OFFSET          0x4
-#define GC_USB_GOTGINT_ADEVTOUTCHG_LSB           0x12
-#define GC_USB_GOTGINT_ADEVTOUTCHG_MASK          0x40000
-#define GC_USB_GOTGINT_ADEVTOUTCHG_SIZE          0x1
-#define GC_USB_GOTGINT_ADEVTOUTCHG_DEFAULT       0x0
-#define GC_USB_GOTGINT_ADEVTOUTCHG_OFFSET        0x4
-#define GC_USB_GAHBCFG_GLBLINTRMSK_LSB           0x0
-#define GC_USB_GAHBCFG_GLBLINTRMSK_MASK          0x1
-#define GC_USB_GAHBCFG_GLBLINTRMSK_SIZE          0x1
-#define GC_USB_GAHBCFG_GLBLINTRMSK_DEFAULT       0x0
-#define GC_USB_GAHBCFG_GLBLINTRMSK_OFFSET        0x8
-#define GC_USB_GAHBCFG_HBSTLEN_LSB               0x1
-#define GC_USB_GAHBCFG_HBSTLEN_MASK              0x1e
-#define GC_USB_GAHBCFG_HBSTLEN_SIZE              0x4
-#define GC_USB_GAHBCFG_HBSTLEN_DEFAULT           0x0
-#define GC_USB_GAHBCFG_HBSTLEN_OFFSET            0x8
-#define GC_USB_GAHBCFG_DMAEN_LSB                 0x5
-#define GC_USB_GAHBCFG_DMAEN_MASK                0x20
-#define GC_USB_GAHBCFG_DMAEN_SIZE                0x1
-#define GC_USB_GAHBCFG_DMAEN_DEFAULT             0x0
-#define GC_USB_GAHBCFG_DMAEN_OFFSET              0x8
+#define GC_USB_GCCFG_OFFSET 0x38
+#define GC_USB_GCCFG_DEFAULT 0x0
+#define GC_USB_GUID_OFFSET 0x3c
+#define GC_USB_GUID_DEFAULT 0x0
+#define GC_USB_GSNPSID_OFFSET 0x40
+#define GC_USB_GSNPSID_DEFAULT 0x0
+#define GC_USB_GHWCFG1_OFFSET 0x44
+#define GC_USB_GHWCFG1_DEFAULT 0x0
+#define GC_USB_GHWCFG2_OFFSET 0x48
+#define GC_USB_GHWCFG2_DEFAULT 0x0
+#define GC_USB_GHWCFG3_OFFSET 0x4c
+#define GC_USB_GHWCFG3_DEFAULT 0x0
+#define GC_USB_GHWCFG4_OFFSET 0x50
+#define GC_USB_GHWCFG4_DEFAULT 0x0
+#define GC_USB_GDFIFOCFG_OFFSET 0x5c
+#define GC_USB_GDFIFOCFG_DEFAULT 0x0
+#define GC_USB_DIEPTXF1_OFFSET 0x104
+#define GC_USB_DIEPTXF1_DEFAULT 0x1000
+#define GC_USB_DIEPTXF2_OFFSET 0x108
+#define GC_USB_DIEPTXF2_DEFAULT 0x0
+#define GC_USB_DIEPTXF3_OFFSET 0x10c
+#define GC_USB_DIEPTXF3_DEFAULT 0x0
+#define GC_USB_DIEPTXF4_OFFSET 0x110
+#define GC_USB_DIEPTXF4_DEFAULT 0x0
+#define GC_USB_DIEPTXF5_OFFSET 0x114
+#define GC_USB_DIEPTXF5_DEFAULT 0x0
+#define GC_USB_DIEPTXF6_OFFSET 0x118
+#define GC_USB_DIEPTXF6_DEFAULT 0x0
+#define GC_USB_DIEPTXF7_OFFSET 0x11c
+#define GC_USB_DIEPTXF7_DEFAULT 0x0
+#define GC_USB_DIEPTXF8_OFFSET 0x120
+#define GC_USB_DIEPTXF8_DEFAULT 0x0
+#define GC_USB_DIEPTXF9_OFFSET 0x124
+#define GC_USB_DIEPTXF9_DEFAULT 0x0
+#define GC_USB_DIEPTXF10_OFFSET 0x128
+#define GC_USB_DIEPTXF10_DEFAULT 0x0
+#define GC_USB_DIEPTXF11_OFFSET 0x12c
+#define GC_USB_DIEPTXF11_DEFAULT 0x0
+#define GC_USB_DIEPTXF12_OFFSET 0x130
+#define GC_USB_DIEPTXF12_DEFAULT 0x0
+#define GC_USB_DIEPTXF13_OFFSET 0x134
+#define GC_USB_DIEPTXF13_DEFAULT 0x0
+#define GC_USB_DIEPTXF14_OFFSET 0x138
+#define GC_USB_DIEPTXF14_DEFAULT 0x0
+#define GC_USB_DIEPTXF15_OFFSET 0x13c
+#define GC_USB_DIEPTXF15_DEFAULT 0x0
+#define GC_USB_DCFG_OFFSET 0x800
+#define GC_USB_DCFG_DEFAULT 0x8000000
+#define GC_USB_DCTL_OFFSET 0x804
+#define GC_USB_DCTL_DEFAULT 0x0
+#define GC_USB_DSTS_OFFSET 0x808
+#define GC_USB_DSTS_DEFAULT 0x0
+#define GC_USB_DIEPMSK_OFFSET 0x810
+#define GC_USB_DIEPMSK_DEFAULT 0x80
+#define GC_USB_DOEPMSK_OFFSET 0x814
+#define GC_USB_DOEPMSK_DEFAULT 0x0
+#define GC_USB_DAINT_OFFSET 0x818
+#define GC_USB_DAINT_DEFAULT 0x0
+#define GC_USB_DAINTMSK_OFFSET 0x81c
+#define GC_USB_DAINTMSK_DEFAULT 0x0
+#define GC_USB_DVBUSDIS_OFFSET 0x828
+#define GC_USB_DVBUSDIS_DEFAULT 0x0
+#define GC_USB_DVBUSPULSE_OFFSET 0x82c
+#define GC_USB_DVBUSPULSE_DEFAULT 0x0
+#define GC_USB_DTHRCTL_OFFSET 0x830
+#define GC_USB_DTHRCTL_DEFAULT 0x0
+#define GC_USB_DIEPEMPMSK_OFFSET 0x834
+#define GC_USB_DIEPEMPMSK_DEFAULT 0x0
+#define GC_USB_DIEPCTL0_OFFSET 0x900
+#define GC_USB_DIEPCTL0_DEFAULT 0x0
+#define GC_USB_DIEPINT0_OFFSET 0x908
+#define GC_USB_DIEPINT0_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ0_OFFSET 0x910
+#define GC_USB_DIEPTSIZ0_DEFAULT 0x0
+#define GC_USB_DIEPDMA0_OFFSET 0x914
+#define GC_USB_DIEPDMA0_DEFAULT 0x0
+#define GC_USB_DTXFSTS0_OFFSET 0x918
+#define GC_USB_DTXFSTS0_DEFAULT 0x0
+#define GC_USB_DIEPDMAB0_OFFSET 0x91c
+#define GC_USB_DIEPDMAB0_DEFAULT 0x0
+#define GC_USB_DIEPCTL1_OFFSET 0x920
+#define GC_USB_DIEPCTL1_DEFAULT 0x0
+#define GC_USB_DIEPINT1_OFFSET 0x928
+#define GC_USB_DIEPINT1_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ1_OFFSET 0x930
+#define GC_USB_DIEPTSIZ1_DEFAULT 0x0
+#define GC_USB_DIEPDMA1_OFFSET 0x934
+#define GC_USB_DIEPDMA1_DEFAULT 0x0
+#define GC_USB_DTXFSTS1_OFFSET 0x938
+#define GC_USB_DTXFSTS1_DEFAULT 0x0
+#define GC_USB_DIEPDMAB1_OFFSET 0x93c
+#define GC_USB_DIEPDMAB1_DEFAULT 0x0
+#define GC_USB_DIEPCTL2_OFFSET 0x940
+#define GC_USB_DIEPCTL2_DEFAULT 0x0
+#define GC_USB_DIEPINT2_OFFSET 0x948
+#define GC_USB_DIEPINT2_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ2_OFFSET 0x950
+#define GC_USB_DIEPTSIZ2_DEFAULT 0x0
+#define GC_USB_DIEPDMA2_OFFSET 0x954
+#define GC_USB_DIEPDMA2_DEFAULT 0x0
+#define GC_USB_DTXFSTS2_OFFSET 0x958
+#define GC_USB_DTXFSTS2_DEFAULT 0x0
+#define GC_USB_DIEPDMAB2_OFFSET 0x95c
+#define GC_USB_DIEPDMAB2_DEFAULT 0x0
+#define GC_USB_DIEPCTL3_OFFSET 0x960
+#define GC_USB_DIEPCTL3_DEFAULT 0x0
+#define GC_USB_DIEPINT3_OFFSET 0x968
+#define GC_USB_DIEPINT3_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ3_OFFSET 0x970
+#define GC_USB_DIEPTSIZ3_DEFAULT 0x0
+#define GC_USB_DIEPDMA3_OFFSET 0x974
+#define GC_USB_DIEPDMA3_DEFAULT 0x0
+#define GC_USB_DTXFSTS3_OFFSET 0x978
+#define GC_USB_DTXFSTS3_DEFAULT 0x0
+#define GC_USB_DIEPDMAB3_OFFSET 0x97c
+#define GC_USB_DIEPDMAB3_DEFAULT 0x0
+#define GC_USB_DIEPCTL4_OFFSET 0x980
+#define GC_USB_DIEPCTL4_DEFAULT 0x0
+#define GC_USB_DIEPINT4_OFFSET 0x988
+#define GC_USB_DIEPINT4_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ4_OFFSET 0x990
+#define GC_USB_DIEPTSIZ4_DEFAULT 0x0
+#define GC_USB_DIEPDMA4_OFFSET 0x994
+#define GC_USB_DIEPDMA4_DEFAULT 0x0
+#define GC_USB_DTXFSTS4_OFFSET 0x998
+#define GC_USB_DTXFSTS4_DEFAULT 0x0
+#define GC_USB_DIEPDMAB4_OFFSET 0x99c
+#define GC_USB_DIEPDMAB4_DEFAULT 0x0
+#define GC_USB_DIEPCTL5_OFFSET 0x9a0
+#define GC_USB_DIEPCTL5_DEFAULT 0x0
+#define GC_USB_DIEPINT5_OFFSET 0x9a8
+#define GC_USB_DIEPINT5_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ5_OFFSET 0x9b0
+#define GC_USB_DIEPTSIZ5_DEFAULT 0x0
+#define GC_USB_DIEPDMA5_OFFSET 0x9b4
+#define GC_USB_DIEPDMA5_DEFAULT 0x0
+#define GC_USB_DTXFSTS5_OFFSET 0x9b8
+#define GC_USB_DTXFSTS5_DEFAULT 0x0
+#define GC_USB_DIEPDMAB5_OFFSET 0x9bc
+#define GC_USB_DIEPDMAB5_DEFAULT 0x0
+#define GC_USB_DIEPCTL6_OFFSET 0x9c0
+#define GC_USB_DIEPCTL6_DEFAULT 0x0
+#define GC_USB_DIEPINT6_OFFSET 0x9c8
+#define GC_USB_DIEPINT6_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ6_OFFSET 0x9d0
+#define GC_USB_DIEPTSIZ6_DEFAULT 0x0
+#define GC_USB_DIEPDMA6_OFFSET 0x9d4
+#define GC_USB_DIEPDMA6_DEFAULT 0x0
+#define GC_USB_DTXFSTS6_OFFSET 0x9d8
+#define GC_USB_DTXFSTS6_DEFAULT 0x0
+#define GC_USB_DIEPDMAB6_OFFSET 0x9dc
+#define GC_USB_DIEPDMAB6_DEFAULT 0x0
+#define GC_USB_DIEPCTL7_OFFSET 0x9e0
+#define GC_USB_DIEPCTL7_DEFAULT 0x0
+#define GC_USB_DIEPINT7_OFFSET 0x9e8
+#define GC_USB_DIEPINT7_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ7_OFFSET 0x9f0
+#define GC_USB_DIEPTSIZ7_DEFAULT 0x0
+#define GC_USB_DIEPDMA7_OFFSET 0x9f4
+#define GC_USB_DIEPDMA7_DEFAULT 0x0
+#define GC_USB_DTXFSTS7_OFFSET 0x9f8
+#define GC_USB_DTXFSTS7_DEFAULT 0x0
+#define GC_USB_DIEPDMAB7_OFFSET 0x9fc
+#define GC_USB_DIEPDMAB7_DEFAULT 0x0
+#define GC_USB_DIEPCTL8_OFFSET 0xa00
+#define GC_USB_DIEPCTL8_DEFAULT 0x0
+#define GC_USB_DIEPINT8_OFFSET 0xa08
+#define GC_USB_DIEPINT8_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ8_OFFSET 0xa10
+#define GC_USB_DIEPTSIZ8_DEFAULT 0x0
+#define GC_USB_DIEPDMA8_OFFSET 0xa14
+#define GC_USB_DIEPDMA8_DEFAULT 0x0
+#define GC_USB_DTXFSTS8_OFFSET 0xa18
+#define GC_USB_DTXFSTS8_DEFAULT 0x0
+#define GC_USB_DIEPDMAB8_OFFSET 0xa1c
+#define GC_USB_DIEPDMAB8_DEFAULT 0x0
+#define GC_USB_DIEPCTL9_OFFSET 0xa20
+#define GC_USB_DIEPCTL9_DEFAULT 0x0
+#define GC_USB_DIEPINT9_OFFSET 0xa28
+#define GC_USB_DIEPINT9_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ9_OFFSET 0xa30
+#define GC_USB_DIEPTSIZ9_DEFAULT 0x0
+#define GC_USB_DIEPDMA9_OFFSET 0xa34
+#define GC_USB_DIEPDMA9_DEFAULT 0x0
+#define GC_USB_DTXFSTS9_OFFSET 0xa38
+#define GC_USB_DTXFSTS9_DEFAULT 0x0
+#define GC_USB_DIEPDMAB9_OFFSET 0xa3c
+#define GC_USB_DIEPDMAB9_DEFAULT 0x0
+#define GC_USB_DIEPCTL10_OFFSET 0xa40
+#define GC_USB_DIEPCTL10_DEFAULT 0x0
+#define GC_USB_DIEPINT10_OFFSET 0xa48
+#define GC_USB_DIEPINT10_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ10_OFFSET 0xa50
+#define GC_USB_DIEPTSIZ10_DEFAULT 0x0
+#define GC_USB_DIEPDMA10_OFFSET 0xa54
+#define GC_USB_DIEPDMA10_DEFAULT 0x0
+#define GC_USB_DTXFSTS10_OFFSET 0xa58
+#define GC_USB_DTXFSTS10_DEFAULT 0x0
+#define GC_USB_DIEPDMAB10_OFFSET 0xa5c
+#define GC_USB_DIEPDMAB10_DEFAULT 0x0
+#define GC_USB_DIEPCTL11_OFFSET 0xa60
+#define GC_USB_DIEPCTL11_DEFAULT 0x0
+#define GC_USB_DIEPINT11_OFFSET 0xa68
+#define GC_USB_DIEPINT11_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ11_OFFSET 0xa70
+#define GC_USB_DIEPTSIZ11_DEFAULT 0x0
+#define GC_USB_DIEPDMA11_OFFSET 0xa74
+#define GC_USB_DIEPDMA11_DEFAULT 0x0
+#define GC_USB_DTXFSTS11_OFFSET 0xa78
+#define GC_USB_DTXFSTS11_DEFAULT 0x0
+#define GC_USB_DIEPDMAB11_OFFSET 0xa7c
+#define GC_USB_DIEPDMAB11_DEFAULT 0x0
+#define GC_USB_DIEPCTL12_OFFSET 0xa80
+#define GC_USB_DIEPCTL12_DEFAULT 0x0
+#define GC_USB_DIEPINT12_OFFSET 0xa88
+#define GC_USB_DIEPINT12_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ12_OFFSET 0xa90
+#define GC_USB_DIEPTSIZ12_DEFAULT 0x0
+#define GC_USB_DIEPDMA12_OFFSET 0xa94
+#define GC_USB_DIEPDMA12_DEFAULT 0x0
+#define GC_USB_DTXFSTS12_OFFSET 0xa98
+#define GC_USB_DTXFSTS12_DEFAULT 0x0
+#define GC_USB_DIEPDMAB12_OFFSET 0xa9c
+#define GC_USB_DIEPDMAB12_DEFAULT 0x0
+#define GC_USB_DIEPCTL13_OFFSET 0xaa0
+#define GC_USB_DIEPCTL13_DEFAULT 0x0
+#define GC_USB_DIEPINT13_OFFSET 0xaa8
+#define GC_USB_DIEPINT13_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ13_OFFSET 0xab0
+#define GC_USB_DIEPTSIZ13_DEFAULT 0x0
+#define GC_USB_DIEPDMA13_OFFSET 0xab4
+#define GC_USB_DIEPDMA13_DEFAULT 0x0
+#define GC_USB_DTXFSTS13_OFFSET 0xab8
+#define GC_USB_DTXFSTS13_DEFAULT 0x0
+#define GC_USB_DIEPDMAB13_OFFSET 0xabc
+#define GC_USB_DIEPDMAB13_DEFAULT 0x0
+#define GC_USB_DIEPCTL14_OFFSET 0xac0
+#define GC_USB_DIEPCTL14_DEFAULT 0x0
+#define GC_USB_DIEPINT14_OFFSET 0xac8
+#define GC_USB_DIEPINT14_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ14_OFFSET 0xad0
+#define GC_USB_DIEPTSIZ14_DEFAULT 0x0
+#define GC_USB_DIEPDMA14_OFFSET 0xad4
+#define GC_USB_DIEPDMA14_DEFAULT 0x0
+#define GC_USB_DTXFSTS14_OFFSET 0xad8
+#define GC_USB_DTXFSTS14_DEFAULT 0x0
+#define GC_USB_DIEPDMAB14_OFFSET 0xadc
+#define GC_USB_DIEPDMAB14_DEFAULT 0x0
+#define GC_USB_DIEPCTL15_OFFSET 0xae0
+#define GC_USB_DIEPCTL15_DEFAULT 0x0
+#define GC_USB_DIEPINT15_OFFSET 0xae8
+#define GC_USB_DIEPINT15_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ15_OFFSET 0xaf0
+#define GC_USB_DIEPTSIZ15_DEFAULT 0x0
+#define GC_USB_DIEPDMA15_OFFSET 0xaf4
+#define GC_USB_DIEPDMA15_DEFAULT 0x0
+#define GC_USB_DTXFSTS15_OFFSET 0xaf8
+#define GC_USB_DTXFSTS15_DEFAULT 0x0
+#define GC_USB_DIEPDMAB15_OFFSET 0xafc
+#define GC_USB_DIEPDMAB15_DEFAULT 0x0
+#define GC_USB_DOEPCTL0_OFFSET 0xb00
+#define GC_USB_DOEPCTL0_DEFAULT 0x0
+#define GC_USB_DOEPINT0_OFFSET 0xb08
+#define GC_USB_DOEPINT0_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ0_OFFSET 0xb10
+#define GC_USB_DOEPTSIZ0_DEFAULT 0x0
+#define GC_USB_DOEPDMA0_OFFSET 0xb14
+#define GC_USB_DOEPDMA0_DEFAULT 0x0
+#define GC_USB_DOEPDMAB0_OFFSET 0xb1c
+#define GC_USB_DOEPDMAB0_DEFAULT 0x0
+#define GC_USB_DOEPCTL1_OFFSET 0xb20
+#define GC_USB_DOEPCTL1_DEFAULT 0x0
+#define GC_USB_DOEPINT1_OFFSET 0xb28
+#define GC_USB_DOEPINT1_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ1_OFFSET 0xb30
+#define GC_USB_DOEPTSIZ1_DEFAULT 0x0
+#define GC_USB_DOEPDMA1_OFFSET 0xb34
+#define GC_USB_DOEPDMA1_DEFAULT 0x0
+#define GC_USB_DOEPDMAB1_OFFSET 0xb3c
+#define GC_USB_DOEPDMAB1_DEFAULT 0x0
+#define GC_USB_DOEPCTL2_OFFSET 0xb40
+#define GC_USB_DOEPCTL2_DEFAULT 0x0
+#define GC_USB_DOEPINT2_OFFSET 0xb48
+#define GC_USB_DOEPINT2_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ2_OFFSET 0xb50
+#define GC_USB_DOEPTSIZ2_DEFAULT 0x0
+#define GC_USB_DOEPDMA2_OFFSET 0xb54
+#define GC_USB_DOEPDMA2_DEFAULT 0x0
+#define GC_USB_DOEPDMAB2_OFFSET 0xb5c
+#define GC_USB_DOEPDMAB2_DEFAULT 0x0
+#define GC_USB_DOEPCTL3_OFFSET 0xb60
+#define GC_USB_DOEPCTL3_DEFAULT 0x0
+#define GC_USB_DOEPINT3_OFFSET 0xb68
+#define GC_USB_DOEPINT3_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ3_OFFSET 0xb70
+#define GC_USB_DOEPTSIZ3_DEFAULT 0x0
+#define GC_USB_DOEPDMA3_OFFSET 0xb74
+#define GC_USB_DOEPDMA3_DEFAULT 0x0
+#define GC_USB_DOEPDMAB3_OFFSET 0xb7c
+#define GC_USB_DOEPDMAB3_DEFAULT 0x0
+#define GC_USB_DOEPCTL4_OFFSET 0xb80
+#define GC_USB_DOEPCTL4_DEFAULT 0x0
+#define GC_USB_DOEPINT4_OFFSET 0xb88
+#define GC_USB_DOEPINT4_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ4_OFFSET 0xb90
+#define GC_USB_DOEPTSIZ4_DEFAULT 0x0
+#define GC_USB_DOEPDMA4_OFFSET 0xb94
+#define GC_USB_DOEPDMA4_DEFAULT 0x0
+#define GC_USB_DOEPDMAB4_OFFSET 0xb9c
+#define GC_USB_DOEPDMAB4_DEFAULT 0x0
+#define GC_USB_DOEPCTL5_OFFSET 0xba0
+#define GC_USB_DOEPCTL5_DEFAULT 0x0
+#define GC_USB_DOEPINT5_OFFSET 0xba8
+#define GC_USB_DOEPINT5_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ5_OFFSET 0xbb0
+#define GC_USB_DOEPTSIZ5_DEFAULT 0x0
+#define GC_USB_DOEPDMA5_OFFSET 0xbb4
+#define GC_USB_DOEPDMA5_DEFAULT 0x0
+#define GC_USB_DOEPDMAB5_OFFSET 0xbbc
+#define GC_USB_DOEPDMAB5_DEFAULT 0x0
+#define GC_USB_DOEPCTL6_OFFSET 0xbc0
+#define GC_USB_DOEPCTL6_DEFAULT 0x0
+#define GC_USB_DOEPINT6_OFFSET 0xbc8
+#define GC_USB_DOEPINT6_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ6_OFFSET 0xbd0
+#define GC_USB_DOEPTSIZ6_DEFAULT 0x0
+#define GC_USB_DOEPDMA6_OFFSET 0xbd4
+#define GC_USB_DOEPDMA6_DEFAULT 0x0
+#define GC_USB_DOEPDMAB6_OFFSET 0xbdc
+#define GC_USB_DOEPDMAB6_DEFAULT 0x0
+#define GC_USB_DOEPCTL7_OFFSET 0xbe0
+#define GC_USB_DOEPCTL7_DEFAULT 0x0
+#define GC_USB_DOEPINT7_OFFSET 0xbe8
+#define GC_USB_DOEPINT7_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ7_OFFSET 0xbf0
+#define GC_USB_DOEPTSIZ7_DEFAULT 0x0
+#define GC_USB_DOEPDMA7_OFFSET 0xbf4
+#define GC_USB_DOEPDMA7_DEFAULT 0x0
+#define GC_USB_DOEPDMAB7_OFFSET 0xbfc
+#define GC_USB_DOEPDMAB7_DEFAULT 0x0
+#define GC_USB_DOEPCTL8_OFFSET 0xc00
+#define GC_USB_DOEPCTL8_DEFAULT 0x0
+#define GC_USB_DOEPINT8_OFFSET 0xc08
+#define GC_USB_DOEPINT8_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ8_OFFSET 0xc10
+#define GC_USB_DOEPTSIZ8_DEFAULT 0x0
+#define GC_USB_DOEPDMA8_OFFSET 0xc14
+#define GC_USB_DOEPDMA8_DEFAULT 0x0
+#define GC_USB_DOEPDMAB8_OFFSET 0xc1c
+#define GC_USB_DOEPDMAB8_DEFAULT 0x0
+#define GC_USB_DOEPCTL9_OFFSET 0xc20
+#define GC_USB_DOEPCTL9_DEFAULT 0x0
+#define GC_USB_DOEPINT9_OFFSET 0xc28
+#define GC_USB_DOEPINT9_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ9_OFFSET 0xc30
+#define GC_USB_DOEPTSIZ9_DEFAULT 0x0
+#define GC_USB_DOEPDMA9_OFFSET 0xc34
+#define GC_USB_DOEPDMA9_DEFAULT 0x0
+#define GC_USB_DOEPDMAB9_OFFSET 0xc3c
+#define GC_USB_DOEPDMAB9_DEFAULT 0x0
+#define GC_USB_DOEPCTL10_OFFSET 0xc40
+#define GC_USB_DOEPCTL10_DEFAULT 0x0
+#define GC_USB_DOEPINT10_OFFSET 0xc48
+#define GC_USB_DOEPINT10_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ10_OFFSET 0xc50
+#define GC_USB_DOEPTSIZ10_DEFAULT 0x0
+#define GC_USB_DOEPDMA10_OFFSET 0xc54
+#define GC_USB_DOEPDMA10_DEFAULT 0x0
+#define GC_USB_DOEPDMAB10_OFFSET 0xc5c
+#define GC_USB_DOEPDMAB10_DEFAULT 0x0
+#define GC_USB_DOEPCTL11_OFFSET 0xc60
+#define GC_USB_DOEPCTL11_DEFAULT 0x0
+#define GC_USB_DOEPINT11_OFFSET 0xc68
+#define GC_USB_DOEPINT11_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ11_OFFSET 0xc70
+#define GC_USB_DOEPTSIZ11_DEFAULT 0x0
+#define GC_USB_DOEPDMA11_OFFSET 0xc74
+#define GC_USB_DOEPDMA11_DEFAULT 0x0
+#define GC_USB_DOEPDMAB11_OFFSET 0xc7c
+#define GC_USB_DOEPDMAB11_DEFAULT 0x0
+#define GC_USB_DOEPCTL12_OFFSET 0xc80
+#define GC_USB_DOEPCTL12_DEFAULT 0x0
+#define GC_USB_DOEPINT12_OFFSET 0xc88
+#define GC_USB_DOEPINT12_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ12_OFFSET 0xc90
+#define GC_USB_DOEPTSIZ12_DEFAULT 0x0
+#define GC_USB_DOEPDMA12_OFFSET 0xc94
+#define GC_USB_DOEPDMA12_DEFAULT 0x0
+#define GC_USB_DOEPDMAB12_OFFSET 0xc9c
+#define GC_USB_DOEPDMAB12_DEFAULT 0x0
+#define GC_USB_DOEPCTL13_OFFSET 0xca0
+#define GC_USB_DOEPCTL13_DEFAULT 0x0
+#define GC_USB_DOEPINT13_OFFSET 0xca8
+#define GC_USB_DOEPINT13_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ13_OFFSET 0xcb0
+#define GC_USB_DOEPTSIZ13_DEFAULT 0x0
+#define GC_USB_DOEPDMA13_OFFSET 0xcb4
+#define GC_USB_DOEPDMA13_DEFAULT 0x0
+#define GC_USB_DOEPDMAB13_OFFSET 0xcbc
+#define GC_USB_DOEPDMAB13_DEFAULT 0x0
+#define GC_USB_DOEPCTL14_OFFSET 0xcc0
+#define GC_USB_DOEPCTL14_DEFAULT 0x0
+#define GC_USB_DOEPINT14_OFFSET 0xcc8
+#define GC_USB_DOEPINT14_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ14_OFFSET 0xcd0
+#define GC_USB_DOEPTSIZ14_DEFAULT 0x0
+#define GC_USB_DOEPDMA14_OFFSET 0xcd4
+#define GC_USB_DOEPDMA14_DEFAULT 0x0
+#define GC_USB_DOEPDMAB14_OFFSET 0xcdc
+#define GC_USB_DOEPDMAB14_DEFAULT 0x0
+#define GC_USB_DOEPCTL15_OFFSET 0xce0
+#define GC_USB_DOEPCTL15_DEFAULT 0x0
+#define GC_USB_DOEPINT15_OFFSET 0xce8
+#define GC_USB_DOEPINT15_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ15_OFFSET 0xcf0
+#define GC_USB_DOEPTSIZ15_DEFAULT 0x0
+#define GC_USB_DOEPDMA15_OFFSET 0xcf4
+#define GC_USB_DOEPDMA15_DEFAULT 0x0
+#define GC_USB_DOEPDMAB15_OFFSET 0xcfc
+#define GC_USB_DOEPDMAB15_DEFAULT 0x0
+#define GC_USB_PCGCCTL_OFFSET 0xe00
+#define GC_USB_PCGCCTL_DEFAULT 0x0
+#define GC_USB_DFIFO_OFFSET 0x20000
+#define GC_USB_GOTGCTL_BVALIDOVEN_LSB 0x6
+#define GC_USB_GOTGCTL_BVALIDOVEN_MASK 0x40
+#define GC_USB_GOTGCTL_BVALIDOVEN_SIZE 0x1
+#define GC_USB_GOTGCTL_BVALIDOVEN_DEFAULT 0x0
+#define GC_USB_GOTGCTL_BVALIDOVEN_OFFSET 0x0
+#define GC_USB_GOTGCTL_BVALIDOVVAL_LSB 0x7
+#define GC_USB_GOTGCTL_BVALIDOVVAL_MASK 0x80
+#define GC_USB_GOTGCTL_BVALIDOVVAL_SIZE 0x1
+#define GC_USB_GOTGCTL_BVALIDOVVAL_DEFAULT 0x0
+#define GC_USB_GOTGCTL_BVALIDOVVAL_OFFSET 0x0
+#define GC_USB_GOTGCTL_CONIDSTS_LSB 0x10
+#define GC_USB_GOTGCTL_CONIDSTS_MASK 0x10000
+#define GC_USB_GOTGCTL_CONIDSTS_SIZE 0x1
+#define GC_USB_GOTGCTL_CONIDSTS_DEFAULT 0x0
+#define GC_USB_GOTGCTL_CONIDSTS_OFFSET 0x0
+#define GC_USB_GOTGCTL_BSESVLD_LSB 0x13
+#define GC_USB_GOTGCTL_BSESVLD_MASK 0x80000
+#define GC_USB_GOTGCTL_BSESVLD_SIZE 0x1
+#define GC_USB_GOTGCTL_BSESVLD_DEFAULT 0x0
+#define GC_USB_GOTGCTL_BSESVLD_OFFSET 0x0
+#define GC_USB_GOTGCTL_OTGVER_LSB 0x14
+#define GC_USB_GOTGCTL_OTGVER_MASK 0x100000
+#define GC_USB_GOTGCTL_OTGVER_SIZE 0x1
+#define GC_USB_GOTGCTL_OTGVER_DEFAULT 0x0
+#define GC_USB_GOTGCTL_OTGVER_OFFSET 0x0
+#define GC_USB_GOTGCTL_CURMOD_LSB 0x15
+#define GC_USB_GOTGCTL_CURMOD_MASK 0x200000
+#define GC_USB_GOTGCTL_CURMOD_SIZE 0x1
+#define GC_USB_GOTGCTL_CURMOD_DEFAULT 0x0
+#define GC_USB_GOTGCTL_CURMOD_OFFSET 0x0
+#define GC_USB_GOTGINT_SESENDDET_LSB 0x2
+#define GC_USB_GOTGINT_SESENDDET_MASK 0x4
+#define GC_USB_GOTGINT_SESENDDET_SIZE 0x1
+#define GC_USB_GOTGINT_SESENDDET_DEFAULT 0x0
+#define GC_USB_GOTGINT_SESENDDET_OFFSET 0x4
+#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_LSB 0x8
+#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_MASK 0x100
+#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_SIZE 0x1
+#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_DEFAULT 0x0
+#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_OFFSET 0x4
+#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_LSB 0x9
+#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_MASK 0x200
+#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_SIZE 0x1
+#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_DEFAULT 0x0
+#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_OFFSET 0x4
+#define GC_USB_GOTGINT_HSTNEGDET_LSB 0x11
+#define GC_USB_GOTGINT_HSTNEGDET_MASK 0x20000
+#define GC_USB_GOTGINT_HSTNEGDET_SIZE 0x1
+#define GC_USB_GOTGINT_HSTNEGDET_DEFAULT 0x0
+#define GC_USB_GOTGINT_HSTNEGDET_OFFSET 0x4
+#define GC_USB_GOTGINT_ADEVTOUTCHG_LSB 0x12
+#define GC_USB_GOTGINT_ADEVTOUTCHG_MASK 0x40000
+#define GC_USB_GOTGINT_ADEVTOUTCHG_SIZE 0x1
+#define GC_USB_GOTGINT_ADEVTOUTCHG_DEFAULT 0x0
+#define GC_USB_GOTGINT_ADEVTOUTCHG_OFFSET 0x4
+#define GC_USB_GAHBCFG_GLBLINTRMSK_LSB 0x0
+#define GC_USB_GAHBCFG_GLBLINTRMSK_MASK 0x1
+#define GC_USB_GAHBCFG_GLBLINTRMSK_SIZE 0x1
+#define GC_USB_GAHBCFG_GLBLINTRMSK_DEFAULT 0x0
+#define GC_USB_GAHBCFG_GLBLINTRMSK_OFFSET 0x8
+#define GC_USB_GAHBCFG_HBSTLEN_LSB 0x1
+#define GC_USB_GAHBCFG_HBSTLEN_MASK 0x1e
+#define GC_USB_GAHBCFG_HBSTLEN_SIZE 0x4
+#define GC_USB_GAHBCFG_HBSTLEN_DEFAULT 0x0
+#define GC_USB_GAHBCFG_HBSTLEN_OFFSET 0x8
+#define GC_USB_GAHBCFG_DMAEN_LSB 0x5
+#define GC_USB_GAHBCFG_DMAEN_MASK 0x20
+#define GC_USB_GAHBCFG_DMAEN_SIZE 0x1
+#define GC_USB_GAHBCFG_DMAEN_DEFAULT 0x0
+#define GC_USB_GAHBCFG_DMAEN_OFFSET 0x8
 
-#define GC_USB_GAHBCFG_NPTXFEMPLVL_LSB           0x7
-#define GC_USB_GAHBCFG_NPTXFEMPLVL_MASK          0x80
-#define GC_USB_GAHBCFG_NPTXFEMPLVL_SIZE          0x1
-#define GC_USB_GAHBCFG_NPTXFEMPLVL_DEFAULT       0x0
-#define GC_USB_GAHBCFG_NPTXFEMPLVL_OFFSET        0x8
+#define GC_USB_GAHBCFG_NPTXFEMPLVL_LSB 0x7
+#define GC_USB_GAHBCFG_NPTXFEMPLVL_MASK 0x80
+#define GC_USB_GAHBCFG_NPTXFEMPLVL_SIZE 0x1
+#define GC_USB_GAHBCFG_NPTXFEMPLVL_DEFAULT 0x0
+#define GC_USB_GAHBCFG_NPTXFEMPLVL_OFFSET 0x8
 
-#define GC_USB_GAHBCFG_REMMEMSUPP_LSB            0x15
-#define GC_USB_GAHBCFG_REMMEMSUPP_MASK           0x200000
-#define GC_USB_GAHBCFG_REMMEMSUPP_SIZE           0x1
-#define GC_USB_GAHBCFG_REMMEMSUPP_DEFAULT        0x0
-#define GC_USB_GAHBCFG_REMMEMSUPP_OFFSET         0x8
-#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_LSB        0x16
-#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_MASK       0x400000
-#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_SIZE       0x1
-#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_DEFAULT    0x0
-#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_OFFSET     0x8
-#define GC_USB_GAHBCFG_AHBSINGLE_LSB             0x17
-#define GC_USB_GAHBCFG_AHBSINGLE_MASK            0x800000
-#define GC_USB_GAHBCFG_AHBSINGLE_SIZE            0x1
-#define GC_USB_GAHBCFG_AHBSINGLE_DEFAULT         0x0
-#define GC_USB_GAHBCFG_AHBSINGLE_OFFSET          0x8
-#define GC_USB_GAHBCFG_INVDESCENDIANESS_LSB      0x18
-#define GC_USB_GAHBCFG_INVDESCENDIANESS_MASK     0x1000000
-#define GC_USB_GAHBCFG_INVDESCENDIANESS_SIZE     0x1
-#define GC_USB_GAHBCFG_INVDESCENDIANESS_DEFAULT  0x0
-#define GC_USB_GAHBCFG_INVDESCENDIANESS_OFFSET   0x8
-#define GC_USB_GUSBCFG_TOUTCAL_LSB               0x0
-#define GC_USB_GUSBCFG_TOUTCAL_MASK              0x7
-#define GC_USB_GUSBCFG_TOUTCAL_SIZE              0x3
-#define GC_USB_GUSBCFG_TOUTCAL_DEFAULT           0x0
-#define GC_USB_GUSBCFG_TOUTCAL_OFFSET            0xc
+#define GC_USB_GAHBCFG_REMMEMSUPP_LSB 0x15
+#define GC_USB_GAHBCFG_REMMEMSUPP_MASK 0x200000
+#define GC_USB_GAHBCFG_REMMEMSUPP_SIZE 0x1
+#define GC_USB_GAHBCFG_REMMEMSUPP_DEFAULT 0x0
+#define GC_USB_GAHBCFG_REMMEMSUPP_OFFSET 0x8
+#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_LSB 0x16
+#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_MASK 0x400000
+#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_SIZE 0x1
+#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_DEFAULT 0x0
+#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_OFFSET 0x8
+#define GC_USB_GAHBCFG_AHBSINGLE_LSB 0x17
+#define GC_USB_GAHBCFG_AHBSINGLE_MASK 0x800000
+#define GC_USB_GAHBCFG_AHBSINGLE_SIZE 0x1
+#define GC_USB_GAHBCFG_AHBSINGLE_DEFAULT 0x0
+#define GC_USB_GAHBCFG_AHBSINGLE_OFFSET 0x8
+#define GC_USB_GAHBCFG_INVDESCENDIANESS_LSB 0x18
+#define GC_USB_GAHBCFG_INVDESCENDIANESS_MASK 0x1000000
+#define GC_USB_GAHBCFG_INVDESCENDIANESS_SIZE 0x1
+#define GC_USB_GAHBCFG_INVDESCENDIANESS_DEFAULT 0x0
+#define GC_USB_GAHBCFG_INVDESCENDIANESS_OFFSET 0x8
+#define GC_USB_GUSBCFG_TOUTCAL_LSB 0x0
+#define GC_USB_GUSBCFG_TOUTCAL_MASK 0x7
+#define GC_USB_GUSBCFG_TOUTCAL_SIZE 0x3
+#define GC_USB_GUSBCFG_TOUTCAL_DEFAULT 0x0
+#define GC_USB_GUSBCFG_TOUTCAL_OFFSET 0xc
 
-#define GC_USB_GUSBCFG_USBTRDTIM_LSB             0xa
-#define GC_USB_GUSBCFG_USBTRDTIM_MASK            0x3c00
-#define GC_USB_GUSBCFG_USBTRDTIM_SIZE            0x4
-#define GC_USB_GUSBCFG_USBTRDTIM_DEFAULT         0x0
-#define GC_USB_GUSBCFG_USBTRDTIM_OFFSET          0xc
-#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_LSB         15
-#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_MASK        0x8000
-#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_SIZE        0x1
-#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_DEFAULT     0x0
-#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_OFFSET      0xc
-#define GC_USB_GUSBCFG_ULPIFSLS_LSB              17
-#define GC_USB_GUSBCFG_ULPIFSLS_MASK             0x20000
-#define GC_USB_GUSBCFG_ULPIFSLS_SIZE             0x1
-#define GC_USB_GUSBCFG_ULPIFSLS_DEFAULT          0x0
-#define GC_USB_GUSBCFG_ULPIFSLS_OFFSET           0xc
-#define GC_USB_GUSBCFG_ULPIAUTORES_LSB           18
-#define GC_USB_GUSBCFG_ULPIAUTORES_MASK          0x40000
-#define GC_USB_GUSBCFG_ULPIAUTORES_SIZE          0x1
-#define GC_USB_GUSBCFG_ULPIAUTORES_DEFAULT       0x0
-#define GC_USB_GUSBCFG_ULPIAUTORES_OFFSET        0xc
-#define GC_USB_GUSBCFG_ULPICLKSUSM_LSB           19
-#define GC_USB_GUSBCFG_ULPICLKSUSM_MASK          0x80000
-#define GC_USB_GUSBCFG_ULPICLKSUSM_SIZE          0x1
-#define GC_USB_GUSBCFG_ULPICLKSUSM_DEFAULT       0x0
-#define GC_USB_GUSBCFG_ULPICLKSUSM_OFFSET        0xc
+#define GC_USB_GUSBCFG_USBTRDTIM_LSB 0xa
+#define GC_USB_GUSBCFG_USBTRDTIM_MASK 0x3c00
+#define GC_USB_GUSBCFG_USBTRDTIM_SIZE 0x4
+#define GC_USB_GUSBCFG_USBTRDTIM_DEFAULT 0x0
+#define GC_USB_GUSBCFG_USBTRDTIM_OFFSET 0xc
+#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_LSB 15
+#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_MASK 0x8000
+#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_SIZE 0x1
+#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_DEFAULT 0x0
+#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_OFFSET 0xc
+#define GC_USB_GUSBCFG_ULPIFSLS_LSB 17
+#define GC_USB_GUSBCFG_ULPIFSLS_MASK 0x20000
+#define GC_USB_GUSBCFG_ULPIFSLS_SIZE 0x1
+#define GC_USB_GUSBCFG_ULPIFSLS_DEFAULT 0x0
+#define GC_USB_GUSBCFG_ULPIFSLS_OFFSET 0xc
+#define GC_USB_GUSBCFG_ULPIAUTORES_LSB 18
+#define GC_USB_GUSBCFG_ULPIAUTORES_MASK 0x40000
+#define GC_USB_GUSBCFG_ULPIAUTORES_SIZE 0x1
+#define GC_USB_GUSBCFG_ULPIAUTORES_DEFAULT 0x0
+#define GC_USB_GUSBCFG_ULPIAUTORES_OFFSET 0xc
+#define GC_USB_GUSBCFG_ULPICLKSUSM_LSB 19
+#define GC_USB_GUSBCFG_ULPICLKSUSM_MASK 0x80000
+#define GC_USB_GUSBCFG_ULPICLKSUSM_SIZE 0x1
+#define GC_USB_GUSBCFG_ULPICLKSUSM_DEFAULT 0x0
+#define GC_USB_GUSBCFG_ULPICLKSUSM_OFFSET 0xc
 
-#define GC_USB_GUSBCFG_ULPIEVBUSD_LSB            20
-#define GC_USB_GUSBCFG_ULPIEVBUSD_MASK           0x100000
-#define GC_USB_GUSBCFG_ULPIEVBUSD_SIZE           0x1
-#define GC_USB_GUSBCFG_ULPIEVBUSD_DEFAULT        0x0
-#define GC_USB_GUSBCFG_ULPIEVBUSD_OFFSET         0xc
+#define GC_USB_GUSBCFG_ULPIEVBUSD_LSB 20
+#define GC_USB_GUSBCFG_ULPIEVBUSD_MASK 0x100000
+#define GC_USB_GUSBCFG_ULPIEVBUSD_SIZE 0x1
+#define GC_USB_GUSBCFG_ULPIEVBUSD_DEFAULT 0x0
+#define GC_USB_GUSBCFG_ULPIEVBUSD_OFFSET 0xc
 
-#define GC_USB_GUSBCFG_ULPIEVBUSI_LSB            21
-#define GC_USB_GUSBCFG_ULPIEVBUSI_MASK           0x200000
-#define GC_USB_GUSBCFG_ULPIEVBUSI_SIZE           0x1
-#define GC_USB_GUSBCFG_ULPIEVBUSI_DEFAULT        0x0
-#define GC_USB_GUSBCFG_ULPIEVBUSI_OFFSET         0xc
+#define GC_USB_GUSBCFG_ULPIEVBUSI_LSB 21
+#define GC_USB_GUSBCFG_ULPIEVBUSI_MASK 0x200000
+#define GC_USB_GUSBCFG_ULPIEVBUSI_SIZE 0x1
+#define GC_USB_GUSBCFG_ULPIEVBUSI_DEFAULT 0x0
+#define GC_USB_GUSBCFG_ULPIEVBUSI_OFFSET 0xc
 
-#define GC_USB_GUSBCFG_TERMSELDLPULSE_LSB        22
-#define GC_USB_GUSBCFG_TERMSELDLPULSE_MASK       0x400000
-#define GC_USB_GUSBCFG_TERMSELDLPULSE_SIZE       0x1
-#define GC_USB_GUSBCFG_TERMSELDLPULSE_DEFAULT    0x0
-#define GC_USB_GUSBCFG_TERMSELDLPULSE_OFFSET     0xc
+#define GC_USB_GUSBCFG_TERMSELDLPULSE_LSB 22
+#define GC_USB_GUSBCFG_TERMSELDLPULSE_MASK 0x400000
+#define GC_USB_GUSBCFG_TERMSELDLPULSE_SIZE 0x1
+#define GC_USB_GUSBCFG_TERMSELDLPULSE_DEFAULT 0x0
+#define GC_USB_GUSBCFG_TERMSELDLPULSE_OFFSET 0xc
 
-#define GC_USB_GUSBCFG_PCCI_LSB                  23
-#define GC_USB_GUSBCFG_PCCI_MASK                 BIT(23)
-#define GC_USB_GUSBCFG_PCCI_SIZE                 0x1
-#define GC_USB_GUSBCFG_PCCI_DEFAULT              0x0
-#define GC_USB_GUSBCFG_PCCI_OFFSET               0xc
+#define GC_USB_GUSBCFG_PCCI_LSB 23
+#define GC_USB_GUSBCFG_PCCI_MASK BIT(23)
+#define GC_USB_GUSBCFG_PCCI_SIZE 0x1
+#define GC_USB_GUSBCFG_PCCI_DEFAULT 0x0
+#define GC_USB_GUSBCFG_PCCI_OFFSET 0xc
 
-#define GC_USB_GUSBCFG_PTCI_LSB                  24
-#define GC_USB_GUSBCFG_PTCI_MASK                 BIT(24)
-#define GC_USB_GUSBCFG_PTCI_SIZE                 0x1
-#define GC_USB_GUSBCFG_PTCI_DEFAULT              0x0
-#define GC_USB_GUSBCFG_PTCI_OFFSET               0xc
+#define GC_USB_GUSBCFG_PTCI_LSB 24
+#define GC_USB_GUSBCFG_PTCI_MASK BIT(24)
+#define GC_USB_GUSBCFG_PTCI_SIZE 0x1
+#define GC_USB_GUSBCFG_PTCI_DEFAULT 0x0
+#define GC_USB_GUSBCFG_PTCI_OFFSET 0xc
 
-#define GC_USB_GUSBCFG_ULPIIPD_LSB               25
-#define GC_USB_GUSBCFG_ULPIIPD_MASK              BIT(25)
-#define GC_USB_GUSBCFG_ULPIIPD_SIZE              0x1
-#define GC_USB_GUSBCFG_ULPIIPD_DEFAULT           0x0
-#define GC_USB_GUSBCFG_ULPIIPD_OFFSET            0xc
+#define GC_USB_GUSBCFG_ULPIIPD_LSB 25
+#define GC_USB_GUSBCFG_ULPIIPD_MASK BIT(25)
+#define GC_USB_GUSBCFG_ULPIIPD_SIZE 0x1
+#define GC_USB_GUSBCFG_ULPIIPD_DEFAULT 0x0
+#define GC_USB_GUSBCFG_ULPIIPD_OFFSET 0xc
 
-#define GC_USB_GUSBCFG_FHMOD_LSB                 29
-#define GC_USB_GUSBCFG_FHMOD_MASK                BIT(29)
-#define GC_USB_GUSBCFG_FHMOD_SIZE                0x1
-#define GC_USB_GUSBCFG_FHMOD_DEFAULT             0x0
-#define GC_USB_GUSBCFG_FHMOD_OFFSET              0xc
+#define GC_USB_GUSBCFG_FHMOD_LSB 29
+#define GC_USB_GUSBCFG_FHMOD_MASK BIT(29)
+#define GC_USB_GUSBCFG_FHMOD_SIZE 0x1
+#define GC_USB_GUSBCFG_FHMOD_DEFAULT 0x0
+#define GC_USB_GUSBCFG_FHMOD_OFFSET 0xc
 
-#define GC_USB_GUSBCFG_FDMOD_LSB                 30
-#define GC_USB_GUSBCFG_FDMOD_MASK                BIT(30)
-#define GC_USB_GUSBCFG_FDMOD_SIZE                0x1
-#define GC_USB_GUSBCFG_FDMOD_DEFAULT             0x0
-#define GC_USB_GUSBCFG_FDMOD_OFFSET              0xc
+#define GC_USB_GUSBCFG_FDMOD_LSB 30
+#define GC_USB_GUSBCFG_FDMOD_MASK BIT(30)
+#define GC_USB_GUSBCFG_FDMOD_SIZE 0x1
+#define GC_USB_GUSBCFG_FDMOD_DEFAULT 0x0
+#define GC_USB_GUSBCFG_FDMOD_OFFSET 0xc
 
-#define GC_USB_GRSTCTL_CSFTRST_LSB               0x0
-#define GC_USB_GRSTCTL_CSFTRST_MASK              0x1
-#define GC_USB_GRSTCTL_CSFTRST_SIZE              0x1
-#define GC_USB_GRSTCTL_CSFTRST_DEFAULT           0x0
-#define GC_USB_GRSTCTL_CSFTRST_OFFSET            0x10
-#define GC_USB_GRSTCTL_PIUFSSFTRST_LSB           0x1
-#define GC_USB_GRSTCTL_PIUFSSFTRST_MASK          0x2
-#define GC_USB_GRSTCTL_PIUFSSFTRST_SIZE          0x1
-#define GC_USB_GRSTCTL_PIUFSSFTRST_DEFAULT       0x0
-#define GC_USB_GRSTCTL_PIUFSSFTRST_OFFSET        0x10
-#define GC_USB_GRSTCTL_RXFFLSH_LSB               0x4
-#define GC_USB_GRSTCTL_RXFFLSH_MASK              0x10
-#define GC_USB_GRSTCTL_RXFFLSH_SIZE              0x1
-#define GC_USB_GRSTCTL_RXFFLSH_DEFAULT           0x0
-#define GC_USB_GRSTCTL_RXFFLSH_OFFSET            0x10
-#define GC_USB_GRSTCTL_TXFFLSH_LSB               0x5
-#define GC_USB_GRSTCTL_TXFFLSH_MASK              0x20
-#define GC_USB_GRSTCTL_TXFFLSH_SIZE              0x1
-#define GC_USB_GRSTCTL_TXFFLSH_DEFAULT           0x0
-#define GC_USB_GRSTCTL_TXFFLSH_OFFSET            0x10
-#define GC_USB_GRSTCTL_TXFNUM_LSB                0x6
-#define GC_USB_GRSTCTL_TXFNUM_MASK               0x7c0
-#define GC_USB_GRSTCTL_TXFNUM_SIZE               0x5
-#define GC_USB_GRSTCTL_TXFNUM_DEFAULT            0x0
-#define GC_USB_GRSTCTL_TXFNUM_OFFSET             0x10
-#define GC_USB_GRSTCTL_DMAREQ_LSB                0x1e
-#define GC_USB_GRSTCTL_DMAREQ_MASK               0x40000000
-#define GC_USB_GRSTCTL_DMAREQ_SIZE               0x1
-#define GC_USB_GRSTCTL_DMAREQ_DEFAULT            0x0
-#define GC_USB_GRSTCTL_DMAREQ_OFFSET             0x10
-#define GC_USB_GRSTCTL_AHBIDLE_LSB               0x1f
-#define GC_USB_GRSTCTL_AHBIDLE_MASK              0x80000000
-#define GC_USB_GRSTCTL_AHBIDLE_SIZE              0x1
-#define GC_USB_GRSTCTL_AHBIDLE_DEFAULT           0x0
-#define GC_USB_GRSTCTL_AHBIDLE_OFFSET            0x10
-#define GC_USB_GINTSTS_CURMOD_LSB                0x0
-#define GC_USB_GINTSTS_CURMOD_MASK               0x1
-#define GC_USB_GINTSTS_CURMOD_SIZE               0x1
-#define GC_USB_GINTSTS_CURMOD_DEFAULT            0x0
-#define GC_USB_GINTSTS_CURMOD_OFFSET             0x14
-#define GC_USB_GINTSTS_MODEMIS_LSB               0x1
-#define GC_USB_GINTSTS_MODEMIS_MASK              0x2
-#define GC_USB_GINTSTS_MODEMIS_SIZE              0x1
-#define GC_USB_GINTSTS_MODEMIS_DEFAULT           0x0
-#define GC_USB_GINTSTS_MODEMIS_OFFSET            0x14
-#define GC_USB_GINTSTS_OTGINT_LSB                0x2
-#define GC_USB_GINTSTS_OTGINT_MASK               0x4
-#define GC_USB_GINTSTS_OTGINT_SIZE               0x1
-#define GC_USB_GINTSTS_OTGINT_DEFAULT            0x0
-#define GC_USB_GINTSTS_OTGINT_OFFSET             0x14
-#define GC_USB_GINTSTS_SOF_LSB                   0x3
-#define GC_USB_GINTSTS_SOF_MASK                  0x8
-#define GC_USB_GINTSTS_SOF_SIZE                  0x1
-#define GC_USB_GINTSTS_SOF_DEFAULT               0x0
-#define GC_USB_GINTSTS_SOF_OFFSET                0x14
-#define GC_USB_GINTSTS_RXFLVL_LSB                0x4
-#define GC_USB_GINTSTS_RXFLVL_MASK               0x10
-#define GC_USB_GINTSTS_RXFLVL_SIZE               0x1
-#define GC_USB_GINTSTS_RXFLVL_DEFAULT            0x0
-#define GC_USB_GINTSTS_RXFLVL_OFFSET             0x14
-#define GC_USB_GINTSTS_GINNAKEFF_LSB             0x6
-#define GC_USB_GINTSTS_GINNAKEFF_MASK            0x40
-#define GC_USB_GINTSTS_GINNAKEFF_SIZE            0x1
-#define GC_USB_GINTSTS_GINNAKEFF_DEFAULT         0x0
-#define GC_USB_GINTSTS_GINNAKEFF_OFFSET          0x14
-#define GC_USB_GINTSTS_GOUTNAKEFF_LSB            0x7
-#define GC_USB_GINTSTS_GOUTNAKEFF_MASK           0x80
-#define GC_USB_GINTSTS_GOUTNAKEFF_SIZE           0x1
-#define GC_USB_GINTSTS_GOUTNAKEFF_DEFAULT        0x0
-#define GC_USB_GINTSTS_GOUTNAKEFF_OFFSET         0x14
-#define GC_USB_GINTSTS_ERLYSUSP_LSB              0xa
-#define GC_USB_GINTSTS_ERLYSUSP_MASK             0x400
-#define GC_USB_GINTSTS_ERLYSUSP_SIZE             0x1
-#define GC_USB_GINTSTS_ERLYSUSP_DEFAULT          0x0
-#define GC_USB_GINTSTS_ERLYSUSP_OFFSET           0x14
-#define GC_USB_GINTSTS_USBSUSP_LSB               0xb
-#define GC_USB_GINTSTS_USBSUSP_MASK              0x800
-#define GC_USB_GINTSTS_USBSUSP_SIZE              0x1
-#define GC_USB_GINTSTS_USBSUSP_DEFAULT           0x0
-#define GC_USB_GINTSTS_USBSUSP_OFFSET            0x14
-#define GC_USB_GINTSTS_USBRST_LSB                0xc
-#define GC_USB_GINTSTS_USBRST_MASK               0x1000
-#define GC_USB_GINTSTS_USBRST_SIZE               0x1
-#define GC_USB_GINTSTS_USBRST_DEFAULT            0x0
-#define GC_USB_GINTSTS_USBRST_OFFSET             0x14
-#define GC_USB_GINTSTS_ENUMDONE_LSB              0xd
-#define GC_USB_GINTSTS_ENUMDONE_MASK             0x2000
-#define GC_USB_GINTSTS_ENUMDONE_SIZE             0x1
-#define GC_USB_GINTSTS_ENUMDONE_DEFAULT          0x0
-#define GC_USB_GINTSTS_ENUMDONE_OFFSET           0x14
-#define GC_USB_GINTSTS_ISOOUTDROP_LSB            0xe
-#define GC_USB_GINTSTS_ISOOUTDROP_MASK           0x4000
-#define GC_USB_GINTSTS_ISOOUTDROP_SIZE           0x1
-#define GC_USB_GINTSTS_ISOOUTDROP_DEFAULT        0x0
-#define GC_USB_GINTSTS_ISOOUTDROP_OFFSET         0x14
-#define GC_USB_GINTSTS_EOPF_LSB                  0xf
-#define GC_USB_GINTSTS_EOPF_MASK                 0x8000
-#define GC_USB_GINTSTS_EOPF_SIZE                 0x1
-#define GC_USB_GINTSTS_EOPF_DEFAULT              0x0
-#define GC_USB_GINTSTS_EOPF_OFFSET               0x14
-#define GC_USB_GINTSTS_EPMIS_LSB                 0x11
-#define GC_USB_GINTSTS_EPMIS_MASK                0x20000
-#define GC_USB_GINTSTS_EPMIS_SIZE                0x1
-#define GC_USB_GINTSTS_EPMIS_DEFAULT             0x0
-#define GC_USB_GINTSTS_EPMIS_OFFSET              0x14
-#define GC_USB_GINTSTS_IEPINT_LSB                0x12
-#define GC_USB_GINTSTS_IEPINT_MASK               0x40000
-#define GC_USB_GINTSTS_IEPINT_SIZE               0x1
-#define GC_USB_GINTSTS_IEPINT_DEFAULT            0x0
-#define GC_USB_GINTSTS_IEPINT_OFFSET             0x14
-#define GC_USB_GINTSTS_OEPINT_LSB                0x13
-#define GC_USB_GINTSTS_OEPINT_MASK               0x80000
-#define GC_USB_GINTSTS_OEPINT_SIZE               0x1
-#define GC_USB_GINTSTS_OEPINT_DEFAULT            0x0
-#define GC_USB_GINTSTS_OEPINT_OFFSET             0x14
-#define GC_USB_GINTSTS_INCOMPISOIN_LSB           0x14
-#define GC_USB_GINTSTS_INCOMPISOIN_MASK          0x100000
-#define GC_USB_GINTSTS_INCOMPISOIN_SIZE          0x1
-#define GC_USB_GINTSTS_INCOMPISOIN_DEFAULT       0x0
-#define GC_USB_GINTSTS_INCOMPISOIN_OFFSET        0x14
-#define GC_USB_GINTSTS_INCOMPLP_LSB              0x15
-#define GC_USB_GINTSTS_INCOMPLP_MASK             0x200000
-#define GC_USB_GINTSTS_INCOMPLP_SIZE             0x1
-#define GC_USB_GINTSTS_INCOMPLP_DEFAULT          0x0
-#define GC_USB_GINTSTS_INCOMPLP_OFFSET           0x14
-#define GC_USB_GINTSTS_FETSUSP_LSB               0x16
-#define GC_USB_GINTSTS_FETSUSP_MASK              0x400000
-#define GC_USB_GINTSTS_FETSUSP_SIZE              0x1
-#define GC_USB_GINTSTS_FETSUSP_DEFAULT           0x0
-#define GC_USB_GINTSTS_FETSUSP_OFFSET            0x14
-#define GC_USB_GINTSTS_RESETDET_LSB              0x17
-#define GC_USB_GINTSTS_RESETDET_MASK             0x800000
-#define GC_USB_GINTSTS_RESETDET_SIZE             0x1
-#define GC_USB_GINTSTS_RESETDET_DEFAULT          0x0
-#define GC_USB_GINTSTS_RESETDET_OFFSET           0x14
-#define GC_USB_GINTSTS_CONIDSTSCHNG_LSB          0x1c
-#define GC_USB_GINTSTS_CONIDSTSCHNG_MASK         0x10000000
-#define GC_USB_GINTSTS_CONIDSTSCHNG_SIZE         0x1
-#define GC_USB_GINTSTS_CONIDSTSCHNG_DEFAULT      0x0
-#define GC_USB_GINTSTS_CONIDSTSCHNG_OFFSET       0x14
-#define GC_USB_GINTSTS_SESSREQINT_LSB            0x1e
-#define GC_USB_GINTSTS_SESSREQINT_MASK           0x40000000
-#define GC_USB_GINTSTS_SESSREQINT_SIZE           0x1
-#define GC_USB_GINTSTS_SESSREQINT_DEFAULT        0x0
-#define GC_USB_GINTSTS_SESSREQINT_OFFSET         0x14
-#define GC_USB_GINTSTS_WKUPINT_LSB               0x1f
-#define GC_USB_GINTSTS_WKUPINT_MASK              0x80000000
-#define GC_USB_GINTSTS_WKUPINT_SIZE              0x1
-#define GC_USB_GINTSTS_WKUPINT_DEFAULT           0x0
-#define GC_USB_GINTSTS_WKUPINT_OFFSET            0x14
-#define GC_USB_GINTMSK_MODEMISMSK_LSB            0x1
-#define GC_USB_GINTMSK_MODEMISMSK_MASK           0x2
-#define GC_USB_GINTMSK_MODEMISMSK_SIZE           0x1
-#define GC_USB_GINTMSK_MODEMISMSK_DEFAULT        0x0
-#define GC_USB_GINTMSK_MODEMISMSK_OFFSET         0x18
-#define GC_USB_GINTMSK_OTGINTMSK_LSB             0x2
-#define GC_USB_GINTMSK_OTGINTMSK_MASK            0x4
-#define GC_USB_GINTMSK_OTGINTMSK_SIZE            0x1
-#define GC_USB_GINTMSK_OTGINTMSK_DEFAULT         0x0
-#define GC_USB_GINTMSK_OTGINTMSK_OFFSET          0x18
-#define GC_USB_GINTMSK_SOFMSK_LSB                0x3
-#define GC_USB_GINTMSK_SOFMSK_MASK               0x8
-#define GC_USB_GINTMSK_SOFMSK_SIZE               0x1
-#define GC_USB_GINTMSK_SOFMSK_DEFAULT            0x0
-#define GC_USB_GINTMSK_SOFMSK_OFFSET             0x18
-#define GC_USB_GINTMSK_RXFLVLMSK_LSB             0x4
-#define GC_USB_GINTMSK_RXFLVLMSK_MASK            0x10
-#define GC_USB_GINTMSK_RXFLVLMSK_SIZE            0x1
-#define GC_USB_GINTMSK_RXFLVLMSK_DEFAULT         0x0
-#define GC_USB_GINTMSK_RXFLVLMSK_OFFSET          0x18
-#define GC_USB_GINTMSK_UNKNOWN5_LSB              0x5
-#define GC_USB_GINTMSK_UNKNOWN5_MASK             0x20
-#define GC_USB_GINTMSK_UNKNOWN5_SIZE             0x1
-#define GC_USB_GINTMSK_UNKNOWN5_DEFAULT          0x0
-#define GC_USB_GINTMSK_UNKNOWN5_OFFSET           0x18
-#define GC_USB_GINTMSK_GINNAKEFFMSK_LSB          0x6
-#define GC_USB_GINTMSK_GINNAKEFFMSK_MASK         0x40
-#define GC_USB_GINTMSK_GINNAKEFFMSK_SIZE         0x1
-#define GC_USB_GINTMSK_GINNAKEFFMSK_DEFAULT      0x0
-#define GC_USB_GINTMSK_GINNAKEFFMSK_OFFSET       0x18
-#define GC_USB_GINTMSK_GOUTNAKEFFMSK_LSB         0x7
-#define GC_USB_GINTMSK_GOUTNAKEFFMSK_MASK        0x80
-#define GC_USB_GINTMSK_GOUTNAKEFFMSK_SIZE        0x1
-#define GC_USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT     0x0
-#define GC_USB_GINTMSK_GOUTNAKEFFMSK_OFFSET      0x18
-#define GC_USB_GINTMSK_ERLYSUSPMSK_LSB           0xa
-#define GC_USB_GINTMSK_ERLYSUSPMSK_MASK          0x400
-#define GC_USB_GINTMSK_ERLYSUSPMSK_SIZE          0x1
-#define GC_USB_GINTMSK_ERLYSUSPMSK_DEFAULT       0x0
-#define GC_USB_GINTMSK_ERLYSUSPMSK_OFFSET        0x18
-#define GC_USB_GINTMSK_USBSUSPMSK_LSB            0xb
-#define GC_USB_GINTMSK_USBSUSPMSK_MASK           0x800
-#define GC_USB_GINTMSK_USBSUSPMSK_SIZE           0x1
-#define GC_USB_GINTMSK_USBSUSPMSK_DEFAULT        0x0
-#define GC_USB_GINTMSK_USBSUSPMSK_OFFSET         0x18
-#define GC_USB_GINTMSK_USBRSTMSK_LSB             0xc
-#define GC_USB_GINTMSK_USBRSTMSK_MASK            0x1000
-#define GC_USB_GINTMSK_USBRSTMSK_SIZE            0x1
-#define GC_USB_GINTMSK_USBRSTMSK_DEFAULT         0x0
-#define GC_USB_GINTMSK_USBRSTMSK_OFFSET          0x18
-#define GC_USB_GINTMSK_ENUMDONEMSK_LSB           0xd
-#define GC_USB_GINTMSK_ENUMDONEMSK_MASK          0x2000
-#define GC_USB_GINTMSK_ENUMDONEMSK_SIZE          0x1
-#define GC_USB_GINTMSK_ENUMDONEMSK_DEFAULT       0x0
-#define GC_USB_GINTMSK_ENUMDONEMSK_OFFSET        0x18
-#define GC_USB_GINTMSK_ISOOUTDROPMSK_LSB         0xe
-#define GC_USB_GINTMSK_ISOOUTDROPMSK_MASK        0x4000
-#define GC_USB_GINTMSK_ISOOUTDROPMSK_SIZE        0x1
-#define GC_USB_GINTMSK_ISOOUTDROPMSK_DEFAULT     0x0
-#define GC_USB_GINTMSK_ISOOUTDROPMSK_OFFSET      0x18
-#define GC_USB_GINTMSK_EOPFMSK_LSB               0xf
-#define GC_USB_GINTMSK_EOPFMSK_MASK              0x8000
-#define GC_USB_GINTMSK_EOPFMSK_SIZE              0x1
-#define GC_USB_GINTMSK_EOPFMSK_DEFAULT           0x0
-#define GC_USB_GINTMSK_EOPFMSK_OFFSET            0x18
-#define GC_USB_GINTMSK_UNKNOWN16_LSB             0x10
-#define GC_USB_GINTMSK_UNKNOWN16_MASK            0x10000
-#define GC_USB_GINTMSK_UNKNOWN16_SIZE            0x1
-#define GC_USB_GINTMSK_UNKNOWN16_DEFAULT         0x0
-#define GC_USB_GINTMSK_UNKNOWN16_OFFSET          0x18
-#define GC_USB_GINTMSK_EPMISMSK_LSB              0x11
-#define GC_USB_GINTMSK_EPMISMSK_MASK             0x20000
-#define GC_USB_GINTMSK_EPMISMSK_SIZE             0x1
-#define GC_USB_GINTMSK_EPMISMSK_DEFAULT          0x0
-#define GC_USB_GINTMSK_EPMISMSK_OFFSET           0x18
-#define GC_USB_GINTMSK_IEPINTMSK_LSB             0x12
-#define GC_USB_GINTMSK_IEPINTMSK_MASK            0x40000
-#define GC_USB_GINTMSK_IEPINTMSK_SIZE            0x1
-#define GC_USB_GINTMSK_IEPINTMSK_DEFAULT         0x0
-#define GC_USB_GINTMSK_IEPINTMSK_OFFSET          0x18
-#define GC_USB_GINTMSK_OEPINTMSK_LSB             0x13
-#define GC_USB_GINTMSK_OEPINTMSK_MASK            0x80000
-#define GC_USB_GINTMSK_OEPINTMSK_SIZE            0x1
-#define GC_USB_GINTMSK_OEPINTMSK_DEFAULT         0x0
-#define GC_USB_GINTMSK_OEPINTMSK_OFFSET          0x18
-#define GC_USB_GINTMSK_INCOMPISOINMSK_LSB        0x14
-#define GC_USB_GINTMSK_INCOMPISOINMSK_MASK       0x100000
-#define GC_USB_GINTMSK_INCOMPISOINMSK_SIZE       0x1
-#define GC_USB_GINTMSK_INCOMPISOINMSK_DEFAULT    0x0
-#define GC_USB_GINTMSK_INCOMPISOINMSK_OFFSET     0x18
-#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_LSB      0x15
-#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_MASK     0x200000
-#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_SIZE     0x1
-#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_DEFAULT  0x0
-#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_OFFSET   0x18
-#define GC_USB_GINTMSK_FETSUSPMSK_LSB            0x16
-#define GC_USB_GINTMSK_FETSUSPMSK_MASK           0x400000
-#define GC_USB_GINTMSK_FETSUSPMSK_SIZE           0x1
-#define GC_USB_GINTMSK_FETSUSPMSK_DEFAULT        0x0
-#define GC_USB_GINTMSK_FETSUSPMSK_OFFSET         0x18
-#define GC_USB_GINTMSK_RESETDETMSK_LSB           0x17
-#define GC_USB_GINTMSK_RESETDETMSK_MASK          0x800000
-#define GC_USB_GINTMSK_RESETDETMSK_SIZE          0x1
-#define GC_USB_GINTMSK_RESETDETMSK_DEFAULT       0x0
-#define GC_USB_GINTMSK_RESETDETMSK_OFFSET        0x18
-#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_LSB       0x1c
-#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_MASK      0x10000000
-#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_SIZE      0x1
-#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_DEFAULT   0x0
-#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_OFFSET    0x18
-#define GC_USB_GINTMSK_DISCONNINTMSK_LSB         0x1d
-#define GC_USB_GINTMSK_DISCONNINTMSK_MASK        0x20000000
-#define GC_USB_GINTMSK_DISCONNINTMSK_SIZE        0x1
-#define GC_USB_GINTMSK_DISCONNINTMSK_DEFAULT     0x0
-#define GC_USB_GINTMSK_DISCONNINTMSK_OFFSET      0x18
-#define GC_USB_GINTMSK_SESSREQINTMSK_LSB         0x1e
-#define GC_USB_GINTMSK_SESSREQINTMSK_MASK        0x40000000
-#define GC_USB_GINTMSK_SESSREQINTMSK_SIZE        0x1
-#define GC_USB_GINTMSK_SESSREQINTMSK_DEFAULT     0x0
-#define GC_USB_GINTMSK_SESSREQINTMSK_OFFSET      0x18
-#define GC_USB_GINTMSK_WKUPINTMSK_LSB            0x1f
-#define GC_USB_GINTMSK_WKUPINTMSK_MASK           0x80000000
-#define GC_USB_GINTMSK_WKUPINTMSK_SIZE           0x1
-#define GC_USB_GINTMSK_WKUPINTMSK_DEFAULT        0x0
-#define GC_USB_GINTMSK_WKUPINTMSK_OFFSET         0x18
-#define GC_USB_GRXSTSR_CHNUM_LSB                 0x0
-#define GC_USB_GRXSTSR_CHNUM_MASK                0xf
-#define GC_USB_GRXSTSR_CHNUM_SIZE                0x4
-#define GC_USB_GRXSTSR_CHNUM_DEFAULT             0x0
-#define GC_USB_GRXSTSR_CHNUM_OFFSET              0x1c
-#define GC_USB_GRXSTSR_BCNT_LSB                  0x4
-#define GC_USB_GRXSTSR_BCNT_MASK                 0x7ff0
-#define GC_USB_GRXSTSR_BCNT_SIZE                 0xb
-#define GC_USB_GRXSTSR_BCNT_DEFAULT              0x0
-#define GC_USB_GRXSTSR_BCNT_OFFSET               0x1c
-#define GC_USB_GRXSTSR_DPID_LSB                  0xf
-#define GC_USB_GRXSTSR_DPID_MASK                 0x18000
-#define GC_USB_GRXSTSR_DPID_SIZE                 0x2
-#define GC_USB_GRXSTSR_DPID_DEFAULT              0x0
-#define GC_USB_GRXSTSR_DPID_OFFSET               0x1c
-#define GC_USB_GRXSTSR_PKTSTS_LSB                0x11
-#define GC_USB_GRXSTSR_PKTSTS_MASK               0x1e0000
-#define GC_USB_GRXSTSR_PKTSTS_SIZE               0x4
-#define GC_USB_GRXSTSR_PKTSTS_DEFAULT            0x0
-#define GC_USB_GRXSTSR_PKTSTS_OFFSET             0x1c
-#define GC_USB_GRXSTSR_FN_LSB                    0x15
-#define GC_USB_GRXSTSR_FN_MASK                   0x1e00000
-#define GC_USB_GRXSTSR_FN_SIZE                   0x4
-#define GC_USB_GRXSTSR_FN_DEFAULT                0x0
-#define GC_USB_GRXSTSR_FN_OFFSET                 0x1c
-#define GC_USB_GRXSTSP_CHNUM_LSB                 0x0
-#define GC_USB_GRXSTSP_CHNUM_MASK                0xf
-#define GC_USB_GRXSTSP_CHNUM_SIZE                0x4
-#define GC_USB_GRXSTSP_CHNUM_DEFAULT             0x0
-#define GC_USB_GRXSTSP_CHNUM_OFFSET              0x20
-#define GC_USB_GRXSTSP_BCNT_LSB                  0x4
-#define GC_USB_GRXSTSP_BCNT_MASK                 0x7ff0
-#define GC_USB_GRXSTSP_BCNT_SIZE                 0xb
-#define GC_USB_GRXSTSP_BCNT_DEFAULT              0x0
-#define GC_USB_GRXSTSP_BCNT_OFFSET               0x20
-#define GC_USB_GRXSTSP_DPID_LSB                  0xf
-#define GC_USB_GRXSTSP_DPID_MASK                 0x18000
-#define GC_USB_GRXSTSP_DPID_SIZE                 0x2
-#define GC_USB_GRXSTSP_DPID_DEFAULT              0x0
-#define GC_USB_GRXSTSP_DPID_OFFSET               0x20
-#define GC_USB_GRXSTSP_PKTSTS_LSB                0x11
-#define GC_USB_GRXSTSP_PKTSTS_MASK               0x1e0000
-#define GC_USB_GRXSTSP_PKTSTS_SIZE               0x4
-#define GC_USB_GRXSTSP_PKTSTS_DEFAULT            0x0
-#define GC_USB_GRXSTSP_PKTSTS_OFFSET             0x20
-#define GC_USB_GRXSTSP_FN_LSB                    0x15
-#define GC_USB_GRXSTSP_FN_MASK                   0x1e00000
-#define GC_USB_GRXSTSP_FN_SIZE                   0x4
-#define GC_USB_GRXSTSP_FN_DEFAULT                0x0
-#define GC_USB_GRXSTSP_FN_OFFSET                 0x20
-#define GC_USB_GRXFSIZ_RXFDEP_LSB                0x0
-#define GC_USB_GRXFSIZ_RXFDEP_MASK               0x7ff
-#define GC_USB_GRXFSIZ_RXFDEP_SIZE               0xb
-#define GC_USB_GRXFSIZ_RXFDEP_DEFAULT            0x0
-#define GC_USB_GRXFSIZ_RXFDEP_OFFSET             0x24
-#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_LSB      0x0
-#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_MASK     0xffff
-#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_SIZE     0x10
-#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_DEFAULT  0x0
-#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_OFFSET   0x28
-#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_LSB         0x10
-#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_MASK        0xffff0000
-#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_SIZE        0x10
-#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_DEFAULT     0x0
-#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_OFFSET      0x28
+#define GC_USB_GRSTCTL_CSFTRST_LSB 0x0
+#define GC_USB_GRSTCTL_CSFTRST_MASK 0x1
+#define GC_USB_GRSTCTL_CSFTRST_SIZE 0x1
+#define GC_USB_GRSTCTL_CSFTRST_DEFAULT 0x0
+#define GC_USB_GRSTCTL_CSFTRST_OFFSET 0x10
+#define GC_USB_GRSTCTL_PIUFSSFTRST_LSB 0x1
+#define GC_USB_GRSTCTL_PIUFSSFTRST_MASK 0x2
+#define GC_USB_GRSTCTL_PIUFSSFTRST_SIZE 0x1
+#define GC_USB_GRSTCTL_PIUFSSFTRST_DEFAULT 0x0
+#define GC_USB_GRSTCTL_PIUFSSFTRST_OFFSET 0x10
+#define GC_USB_GRSTCTL_RXFFLSH_LSB 0x4
+#define GC_USB_GRSTCTL_RXFFLSH_MASK 0x10
+#define GC_USB_GRSTCTL_RXFFLSH_SIZE 0x1
+#define GC_USB_GRSTCTL_RXFFLSH_DEFAULT 0x0
+#define GC_USB_GRSTCTL_RXFFLSH_OFFSET 0x10
+#define GC_USB_GRSTCTL_TXFFLSH_LSB 0x5
+#define GC_USB_GRSTCTL_TXFFLSH_MASK 0x20
+#define GC_USB_GRSTCTL_TXFFLSH_SIZE 0x1
+#define GC_USB_GRSTCTL_TXFFLSH_DEFAULT 0x0
+#define GC_USB_GRSTCTL_TXFFLSH_OFFSET 0x10
+#define GC_USB_GRSTCTL_TXFNUM_LSB 0x6
+#define GC_USB_GRSTCTL_TXFNUM_MASK 0x7c0
+#define GC_USB_GRSTCTL_TXFNUM_SIZE 0x5
+#define GC_USB_GRSTCTL_TXFNUM_DEFAULT 0x0
+#define GC_USB_GRSTCTL_TXFNUM_OFFSET 0x10
+#define GC_USB_GRSTCTL_DMAREQ_LSB 0x1e
+#define GC_USB_GRSTCTL_DMAREQ_MASK 0x40000000
+#define GC_USB_GRSTCTL_DMAREQ_SIZE 0x1
+#define GC_USB_GRSTCTL_DMAREQ_DEFAULT 0x0
+#define GC_USB_GRSTCTL_DMAREQ_OFFSET 0x10
+#define GC_USB_GRSTCTL_AHBIDLE_LSB 0x1f
+#define GC_USB_GRSTCTL_AHBIDLE_MASK 0x80000000
+#define GC_USB_GRSTCTL_AHBIDLE_SIZE 0x1
+#define GC_USB_GRSTCTL_AHBIDLE_DEFAULT 0x0
+#define GC_USB_GRSTCTL_AHBIDLE_OFFSET 0x10
+#define GC_USB_GINTSTS_CURMOD_LSB 0x0
+#define GC_USB_GINTSTS_CURMOD_MASK 0x1
+#define GC_USB_GINTSTS_CURMOD_SIZE 0x1
+#define GC_USB_GINTSTS_CURMOD_DEFAULT 0x0
+#define GC_USB_GINTSTS_CURMOD_OFFSET 0x14
+#define GC_USB_GINTSTS_MODEMIS_LSB 0x1
+#define GC_USB_GINTSTS_MODEMIS_MASK 0x2
+#define GC_USB_GINTSTS_MODEMIS_SIZE 0x1
+#define GC_USB_GINTSTS_MODEMIS_DEFAULT 0x0
+#define GC_USB_GINTSTS_MODEMIS_OFFSET 0x14
+#define GC_USB_GINTSTS_OTGINT_LSB 0x2
+#define GC_USB_GINTSTS_OTGINT_MASK 0x4
+#define GC_USB_GINTSTS_OTGINT_SIZE 0x1
+#define GC_USB_GINTSTS_OTGINT_DEFAULT 0x0
+#define GC_USB_GINTSTS_OTGINT_OFFSET 0x14
+#define GC_USB_GINTSTS_SOF_LSB 0x3
+#define GC_USB_GINTSTS_SOF_MASK 0x8
+#define GC_USB_GINTSTS_SOF_SIZE 0x1
+#define GC_USB_GINTSTS_SOF_DEFAULT 0x0
+#define GC_USB_GINTSTS_SOF_OFFSET 0x14
+#define GC_USB_GINTSTS_RXFLVL_LSB 0x4
+#define GC_USB_GINTSTS_RXFLVL_MASK 0x10
+#define GC_USB_GINTSTS_RXFLVL_SIZE 0x1
+#define GC_USB_GINTSTS_RXFLVL_DEFAULT 0x0
+#define GC_USB_GINTSTS_RXFLVL_OFFSET 0x14
+#define GC_USB_GINTSTS_GINNAKEFF_LSB 0x6
+#define GC_USB_GINTSTS_GINNAKEFF_MASK 0x40
+#define GC_USB_GINTSTS_GINNAKEFF_SIZE 0x1
+#define GC_USB_GINTSTS_GINNAKEFF_DEFAULT 0x0
+#define GC_USB_GINTSTS_GINNAKEFF_OFFSET 0x14
+#define GC_USB_GINTSTS_GOUTNAKEFF_LSB 0x7
+#define GC_USB_GINTSTS_GOUTNAKEFF_MASK 0x80
+#define GC_USB_GINTSTS_GOUTNAKEFF_SIZE 0x1
+#define GC_USB_GINTSTS_GOUTNAKEFF_DEFAULT 0x0
+#define GC_USB_GINTSTS_GOUTNAKEFF_OFFSET 0x14
+#define GC_USB_GINTSTS_ERLYSUSP_LSB 0xa
+#define GC_USB_GINTSTS_ERLYSUSP_MASK 0x400
+#define GC_USB_GINTSTS_ERLYSUSP_SIZE 0x1
+#define GC_USB_GINTSTS_ERLYSUSP_DEFAULT 0x0
+#define GC_USB_GINTSTS_ERLYSUSP_OFFSET 0x14
+#define GC_USB_GINTSTS_USBSUSP_LSB 0xb
+#define GC_USB_GINTSTS_USBSUSP_MASK 0x800
+#define GC_USB_GINTSTS_USBSUSP_SIZE 0x1
+#define GC_USB_GINTSTS_USBSUSP_DEFAULT 0x0
+#define GC_USB_GINTSTS_USBSUSP_OFFSET 0x14
+#define GC_USB_GINTSTS_USBRST_LSB 0xc
+#define GC_USB_GINTSTS_USBRST_MASK 0x1000
+#define GC_USB_GINTSTS_USBRST_SIZE 0x1
+#define GC_USB_GINTSTS_USBRST_DEFAULT 0x0
+#define GC_USB_GINTSTS_USBRST_OFFSET 0x14
+#define GC_USB_GINTSTS_ENUMDONE_LSB 0xd
+#define GC_USB_GINTSTS_ENUMDONE_MASK 0x2000
+#define GC_USB_GINTSTS_ENUMDONE_SIZE 0x1
+#define GC_USB_GINTSTS_ENUMDONE_DEFAULT 0x0
+#define GC_USB_GINTSTS_ENUMDONE_OFFSET 0x14
+#define GC_USB_GINTSTS_ISOOUTDROP_LSB 0xe
+#define GC_USB_GINTSTS_ISOOUTDROP_MASK 0x4000
+#define GC_USB_GINTSTS_ISOOUTDROP_SIZE 0x1
+#define GC_USB_GINTSTS_ISOOUTDROP_DEFAULT 0x0
+#define GC_USB_GINTSTS_ISOOUTDROP_OFFSET 0x14
+#define GC_USB_GINTSTS_EOPF_LSB 0xf
+#define GC_USB_GINTSTS_EOPF_MASK 0x8000
+#define GC_USB_GINTSTS_EOPF_SIZE 0x1
+#define GC_USB_GINTSTS_EOPF_DEFAULT 0x0
+#define GC_USB_GINTSTS_EOPF_OFFSET 0x14
+#define GC_USB_GINTSTS_EPMIS_LSB 0x11
+#define GC_USB_GINTSTS_EPMIS_MASK 0x20000
+#define GC_USB_GINTSTS_EPMIS_SIZE 0x1
+#define GC_USB_GINTSTS_EPMIS_DEFAULT 0x0
+#define GC_USB_GINTSTS_EPMIS_OFFSET 0x14
+#define GC_USB_GINTSTS_IEPINT_LSB 0x12
+#define GC_USB_GINTSTS_IEPINT_MASK 0x40000
+#define GC_USB_GINTSTS_IEPINT_SIZE 0x1
+#define GC_USB_GINTSTS_IEPINT_DEFAULT 0x0
+#define GC_USB_GINTSTS_IEPINT_OFFSET 0x14
+#define GC_USB_GINTSTS_OEPINT_LSB 0x13
+#define GC_USB_GINTSTS_OEPINT_MASK 0x80000
+#define GC_USB_GINTSTS_OEPINT_SIZE 0x1
+#define GC_USB_GINTSTS_OEPINT_DEFAULT 0x0
+#define GC_USB_GINTSTS_OEPINT_OFFSET 0x14
+#define GC_USB_GINTSTS_INCOMPISOIN_LSB 0x14
+#define GC_USB_GINTSTS_INCOMPISOIN_MASK 0x100000
+#define GC_USB_GINTSTS_INCOMPISOIN_SIZE 0x1
+#define GC_USB_GINTSTS_INCOMPISOIN_DEFAULT 0x0
+#define GC_USB_GINTSTS_INCOMPISOIN_OFFSET 0x14
+#define GC_USB_GINTSTS_INCOMPLP_LSB 0x15
+#define GC_USB_GINTSTS_INCOMPLP_MASK 0x200000
+#define GC_USB_GINTSTS_INCOMPLP_SIZE 0x1
+#define GC_USB_GINTSTS_INCOMPLP_DEFAULT 0x0
+#define GC_USB_GINTSTS_INCOMPLP_OFFSET 0x14
+#define GC_USB_GINTSTS_FETSUSP_LSB 0x16
+#define GC_USB_GINTSTS_FETSUSP_MASK 0x400000
+#define GC_USB_GINTSTS_FETSUSP_SIZE 0x1
+#define GC_USB_GINTSTS_FETSUSP_DEFAULT 0x0
+#define GC_USB_GINTSTS_FETSUSP_OFFSET 0x14
+#define GC_USB_GINTSTS_RESETDET_LSB 0x17
+#define GC_USB_GINTSTS_RESETDET_MASK 0x800000
+#define GC_USB_GINTSTS_RESETDET_SIZE 0x1
+#define GC_USB_GINTSTS_RESETDET_DEFAULT 0x0
+#define GC_USB_GINTSTS_RESETDET_OFFSET 0x14
+#define GC_USB_GINTSTS_CONIDSTSCHNG_LSB 0x1c
+#define GC_USB_GINTSTS_CONIDSTSCHNG_MASK 0x10000000
+#define GC_USB_GINTSTS_CONIDSTSCHNG_SIZE 0x1
+#define GC_USB_GINTSTS_CONIDSTSCHNG_DEFAULT 0x0
+#define GC_USB_GINTSTS_CONIDSTSCHNG_OFFSET 0x14
+#define GC_USB_GINTSTS_SESSREQINT_LSB 0x1e
+#define GC_USB_GINTSTS_SESSREQINT_MASK 0x40000000
+#define GC_USB_GINTSTS_SESSREQINT_SIZE 0x1
+#define GC_USB_GINTSTS_SESSREQINT_DEFAULT 0x0
+#define GC_USB_GINTSTS_SESSREQINT_OFFSET 0x14
+#define GC_USB_GINTSTS_WKUPINT_LSB 0x1f
+#define GC_USB_GINTSTS_WKUPINT_MASK 0x80000000
+#define GC_USB_GINTSTS_WKUPINT_SIZE 0x1
+#define GC_USB_GINTSTS_WKUPINT_DEFAULT 0x0
+#define GC_USB_GINTSTS_WKUPINT_OFFSET 0x14
+#define GC_USB_GINTMSK_MODEMISMSK_LSB 0x1
+#define GC_USB_GINTMSK_MODEMISMSK_MASK 0x2
+#define GC_USB_GINTMSK_MODEMISMSK_SIZE 0x1
+#define GC_USB_GINTMSK_MODEMISMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_MODEMISMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_OTGINTMSK_LSB 0x2
+#define GC_USB_GINTMSK_OTGINTMSK_MASK 0x4
+#define GC_USB_GINTMSK_OTGINTMSK_SIZE 0x1
+#define GC_USB_GINTMSK_OTGINTMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_OTGINTMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_SOFMSK_LSB 0x3
+#define GC_USB_GINTMSK_SOFMSK_MASK 0x8
+#define GC_USB_GINTMSK_SOFMSK_SIZE 0x1
+#define GC_USB_GINTMSK_SOFMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_SOFMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_RXFLVLMSK_LSB 0x4
+#define GC_USB_GINTMSK_RXFLVLMSK_MASK 0x10
+#define GC_USB_GINTMSK_RXFLVLMSK_SIZE 0x1
+#define GC_USB_GINTMSK_RXFLVLMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_RXFLVLMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_UNKNOWN5_LSB 0x5
+#define GC_USB_GINTMSK_UNKNOWN5_MASK 0x20
+#define GC_USB_GINTMSK_UNKNOWN5_SIZE 0x1
+#define GC_USB_GINTMSK_UNKNOWN5_DEFAULT 0x0
+#define GC_USB_GINTMSK_UNKNOWN5_OFFSET 0x18
+#define GC_USB_GINTMSK_GINNAKEFFMSK_LSB 0x6
+#define GC_USB_GINTMSK_GINNAKEFFMSK_MASK 0x40
+#define GC_USB_GINTMSK_GINNAKEFFMSK_SIZE 0x1
+#define GC_USB_GINTMSK_GINNAKEFFMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_GINNAKEFFMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_GOUTNAKEFFMSK_LSB 0x7
+#define GC_USB_GINTMSK_GOUTNAKEFFMSK_MASK 0x80
+#define GC_USB_GINTMSK_GOUTNAKEFFMSK_SIZE 0x1
+#define GC_USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_GOUTNAKEFFMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_ERLYSUSPMSK_LSB 0xa
+#define GC_USB_GINTMSK_ERLYSUSPMSK_MASK 0x400
+#define GC_USB_GINTMSK_ERLYSUSPMSK_SIZE 0x1
+#define GC_USB_GINTMSK_ERLYSUSPMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_ERLYSUSPMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_USBSUSPMSK_LSB 0xb
+#define GC_USB_GINTMSK_USBSUSPMSK_MASK 0x800
+#define GC_USB_GINTMSK_USBSUSPMSK_SIZE 0x1
+#define GC_USB_GINTMSK_USBSUSPMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_USBSUSPMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_USBRSTMSK_LSB 0xc
+#define GC_USB_GINTMSK_USBRSTMSK_MASK 0x1000
+#define GC_USB_GINTMSK_USBRSTMSK_SIZE 0x1
+#define GC_USB_GINTMSK_USBRSTMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_USBRSTMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_ENUMDONEMSK_LSB 0xd
+#define GC_USB_GINTMSK_ENUMDONEMSK_MASK 0x2000
+#define GC_USB_GINTMSK_ENUMDONEMSK_SIZE 0x1
+#define GC_USB_GINTMSK_ENUMDONEMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_ENUMDONEMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_ISOOUTDROPMSK_LSB 0xe
+#define GC_USB_GINTMSK_ISOOUTDROPMSK_MASK 0x4000
+#define GC_USB_GINTMSK_ISOOUTDROPMSK_SIZE 0x1
+#define GC_USB_GINTMSK_ISOOUTDROPMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_ISOOUTDROPMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_EOPFMSK_LSB 0xf
+#define GC_USB_GINTMSK_EOPFMSK_MASK 0x8000
+#define GC_USB_GINTMSK_EOPFMSK_SIZE 0x1
+#define GC_USB_GINTMSK_EOPFMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_EOPFMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_UNKNOWN16_LSB 0x10
+#define GC_USB_GINTMSK_UNKNOWN16_MASK 0x10000
+#define GC_USB_GINTMSK_UNKNOWN16_SIZE 0x1
+#define GC_USB_GINTMSK_UNKNOWN16_DEFAULT 0x0
+#define GC_USB_GINTMSK_UNKNOWN16_OFFSET 0x18
+#define GC_USB_GINTMSK_EPMISMSK_LSB 0x11
+#define GC_USB_GINTMSK_EPMISMSK_MASK 0x20000
+#define GC_USB_GINTMSK_EPMISMSK_SIZE 0x1
+#define GC_USB_GINTMSK_EPMISMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_EPMISMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_IEPINTMSK_LSB 0x12
+#define GC_USB_GINTMSK_IEPINTMSK_MASK 0x40000
+#define GC_USB_GINTMSK_IEPINTMSK_SIZE 0x1
+#define GC_USB_GINTMSK_IEPINTMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_IEPINTMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_OEPINTMSK_LSB 0x13
+#define GC_USB_GINTMSK_OEPINTMSK_MASK 0x80000
+#define GC_USB_GINTMSK_OEPINTMSK_SIZE 0x1
+#define GC_USB_GINTMSK_OEPINTMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_OEPINTMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_INCOMPISOINMSK_LSB 0x14
+#define GC_USB_GINTMSK_INCOMPISOINMSK_MASK 0x100000
+#define GC_USB_GINTMSK_INCOMPISOINMSK_SIZE 0x1
+#define GC_USB_GINTMSK_INCOMPISOINMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_INCOMPISOINMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_LSB 0x15
+#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_MASK 0x200000
+#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_SIZE 0x1
+#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_FETSUSPMSK_LSB 0x16
+#define GC_USB_GINTMSK_FETSUSPMSK_MASK 0x400000
+#define GC_USB_GINTMSK_FETSUSPMSK_SIZE 0x1
+#define GC_USB_GINTMSK_FETSUSPMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_FETSUSPMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_RESETDETMSK_LSB 0x17
+#define GC_USB_GINTMSK_RESETDETMSK_MASK 0x800000
+#define GC_USB_GINTMSK_RESETDETMSK_SIZE 0x1
+#define GC_USB_GINTMSK_RESETDETMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_RESETDETMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_LSB 0x1c
+#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_MASK 0x10000000
+#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_SIZE 0x1
+#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_DISCONNINTMSK_LSB 0x1d
+#define GC_USB_GINTMSK_DISCONNINTMSK_MASK 0x20000000
+#define GC_USB_GINTMSK_DISCONNINTMSK_SIZE 0x1
+#define GC_USB_GINTMSK_DISCONNINTMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_DISCONNINTMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_SESSREQINTMSK_LSB 0x1e
+#define GC_USB_GINTMSK_SESSREQINTMSK_MASK 0x40000000
+#define GC_USB_GINTMSK_SESSREQINTMSK_SIZE 0x1
+#define GC_USB_GINTMSK_SESSREQINTMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_SESSREQINTMSK_OFFSET 0x18
+#define GC_USB_GINTMSK_WKUPINTMSK_LSB 0x1f
+#define GC_USB_GINTMSK_WKUPINTMSK_MASK 0x80000000
+#define GC_USB_GINTMSK_WKUPINTMSK_SIZE 0x1
+#define GC_USB_GINTMSK_WKUPINTMSK_DEFAULT 0x0
+#define GC_USB_GINTMSK_WKUPINTMSK_OFFSET 0x18
+#define GC_USB_GRXSTSR_CHNUM_LSB 0x0
+#define GC_USB_GRXSTSR_CHNUM_MASK 0xf
+#define GC_USB_GRXSTSR_CHNUM_SIZE 0x4
+#define GC_USB_GRXSTSR_CHNUM_DEFAULT 0x0
+#define GC_USB_GRXSTSR_CHNUM_OFFSET 0x1c
+#define GC_USB_GRXSTSR_BCNT_LSB 0x4
+#define GC_USB_GRXSTSR_BCNT_MASK 0x7ff0
+#define GC_USB_GRXSTSR_BCNT_SIZE 0xb
+#define GC_USB_GRXSTSR_BCNT_DEFAULT 0x0
+#define GC_USB_GRXSTSR_BCNT_OFFSET 0x1c
+#define GC_USB_GRXSTSR_DPID_LSB 0xf
+#define GC_USB_GRXSTSR_DPID_MASK 0x18000
+#define GC_USB_GRXSTSR_DPID_SIZE 0x2
+#define GC_USB_GRXSTSR_DPID_DEFAULT 0x0
+#define GC_USB_GRXSTSR_DPID_OFFSET 0x1c
+#define GC_USB_GRXSTSR_PKTSTS_LSB 0x11
+#define GC_USB_GRXSTSR_PKTSTS_MASK 0x1e0000
+#define GC_USB_GRXSTSR_PKTSTS_SIZE 0x4
+#define GC_USB_GRXSTSR_PKTSTS_DEFAULT 0x0
+#define GC_USB_GRXSTSR_PKTSTS_OFFSET 0x1c
+#define GC_USB_GRXSTSR_FN_LSB 0x15
+#define GC_USB_GRXSTSR_FN_MASK 0x1e00000
+#define GC_USB_GRXSTSR_FN_SIZE 0x4
+#define GC_USB_GRXSTSR_FN_DEFAULT 0x0
+#define GC_USB_GRXSTSR_FN_OFFSET 0x1c
+#define GC_USB_GRXSTSP_CHNUM_LSB 0x0
+#define GC_USB_GRXSTSP_CHNUM_MASK 0xf
+#define GC_USB_GRXSTSP_CHNUM_SIZE 0x4
+#define GC_USB_GRXSTSP_CHNUM_DEFAULT 0x0
+#define GC_USB_GRXSTSP_CHNUM_OFFSET 0x20
+#define GC_USB_GRXSTSP_BCNT_LSB 0x4
+#define GC_USB_GRXSTSP_BCNT_MASK 0x7ff0
+#define GC_USB_GRXSTSP_BCNT_SIZE 0xb
+#define GC_USB_GRXSTSP_BCNT_DEFAULT 0x0
+#define GC_USB_GRXSTSP_BCNT_OFFSET 0x20
+#define GC_USB_GRXSTSP_DPID_LSB 0xf
+#define GC_USB_GRXSTSP_DPID_MASK 0x18000
+#define GC_USB_GRXSTSP_DPID_SIZE 0x2
+#define GC_USB_GRXSTSP_DPID_DEFAULT 0x0
+#define GC_USB_GRXSTSP_DPID_OFFSET 0x20
+#define GC_USB_GRXSTSP_PKTSTS_LSB 0x11
+#define GC_USB_GRXSTSP_PKTSTS_MASK 0x1e0000
+#define GC_USB_GRXSTSP_PKTSTS_SIZE 0x4
+#define GC_USB_GRXSTSP_PKTSTS_DEFAULT 0x0
+#define GC_USB_GRXSTSP_PKTSTS_OFFSET 0x20
+#define GC_USB_GRXSTSP_FN_LSB 0x15
+#define GC_USB_GRXSTSP_FN_MASK 0x1e00000
+#define GC_USB_GRXSTSP_FN_SIZE 0x4
+#define GC_USB_GRXSTSP_FN_DEFAULT 0x0
+#define GC_USB_GRXSTSP_FN_OFFSET 0x20
+#define GC_USB_GRXFSIZ_RXFDEP_LSB 0x0
+#define GC_USB_GRXFSIZ_RXFDEP_MASK 0x7ff
+#define GC_USB_GRXFSIZ_RXFDEP_SIZE 0xb
+#define GC_USB_GRXFSIZ_RXFDEP_DEFAULT 0x0
+#define GC_USB_GRXFSIZ_RXFDEP_OFFSET 0x24
+#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_LSB 0x0
+#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_MASK 0xffff
+#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_SIZE 0x10
+#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_DEFAULT 0x0
+#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_OFFSET 0x28
+#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_LSB 0x10
+#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_MASK 0xffff0000
+#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_SIZE 0x10
+#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_DEFAULT 0x0
+#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_OFFSET 0x28
 
-#define GC_USB_GUID_GUID_LSB                     0x0
-#define GC_USB_GUID_GUID_MASK                    0xffffffff
-#define GC_USB_GUID_GUID_SIZE                    0x20
-#define GC_USB_GUID_GUID_DEFAULT                 0x0
-#define GC_USB_GUID_GUID_OFFSET                  0x3c
-#define GC_USB_GSNPSID_SYNOPSYSID_LSB            0x0
-#define GC_USB_GSNPSID_SYNOPSYSID_MASK           0xffffffff
-#define GC_USB_GSNPSID_SYNOPSYSID_SIZE           0x20
-#define GC_USB_GSNPSID_SYNOPSYSID_DEFAULT        0x0
-#define GC_USB_GSNPSID_SYNOPSYSID_OFFSET         0x40
-#define GC_USB_GHWCFG1_EPDIR_LSB                 0x0
-#define GC_USB_GHWCFG1_EPDIR_MASK                0xffffffff
-#define GC_USB_GHWCFG1_EPDIR_SIZE                0x20
-#define GC_USB_GHWCFG1_EPDIR_DEFAULT             0x0
-#define GC_USB_GHWCFG1_EPDIR_OFFSET              0x44
-#define GC_USB_GHWCFG2_OTGMODE_LSB               0x0
-#define GC_USB_GHWCFG2_OTGMODE_MASK              0x7
-#define GC_USB_GHWCFG2_OTGMODE_SIZE              0x3
-#define GC_USB_GHWCFG2_OTGMODE_DEFAULT           0x0
-#define GC_USB_GHWCFG2_OTGMODE_OFFSET            0x48
-#define GC_USB_GHWCFG2_OTGARCH_LSB               0x3
-#define GC_USB_GHWCFG2_OTGARCH_MASK              0x18
-#define GC_USB_GHWCFG2_OTGARCH_SIZE              0x2
-#define GC_USB_GHWCFG2_OTGARCH_DEFAULT           0x0
-#define GC_USB_GHWCFG2_OTGARCH_OFFSET            0x48
-#define GC_USB_GHWCFG2_SINGPNT_LSB               0x5
-#define GC_USB_GHWCFG2_SINGPNT_MASK              0x20
-#define GC_USB_GHWCFG2_SINGPNT_SIZE              0x1
-#define GC_USB_GHWCFG2_SINGPNT_DEFAULT           0x0
-#define GC_USB_GHWCFG2_SINGPNT_OFFSET            0x48
-#define GC_USB_GHWCFG2_HSPHYTYPE_LSB             0x6
-#define GC_USB_GHWCFG2_HSPHYTYPE_MASK            0xc0
-#define GC_USB_GHWCFG2_HSPHYTYPE_SIZE            0x2
-#define GC_USB_GHWCFG2_HSPHYTYPE_DEFAULT         0x0
-#define GC_USB_GHWCFG2_HSPHYTYPE_OFFSET          0x48
-#define GC_USB_GHWCFG2_FSPHYTYPE_LSB             0x8
-#define GC_USB_GHWCFG2_FSPHYTYPE_MASK            0x300
-#define GC_USB_GHWCFG2_FSPHYTYPE_SIZE            0x2
-#define GC_USB_GHWCFG2_FSPHYTYPE_DEFAULT         0x0
-#define GC_USB_GHWCFG2_FSPHYTYPE_OFFSET          0x48
-#define GC_USB_GHWCFG2_NUMDEVEPS_LSB             0xa
-#define GC_USB_GHWCFG2_NUMDEVEPS_MASK            0x3c00
-#define GC_USB_GHWCFG2_NUMDEVEPS_SIZE            0x4
-#define GC_USB_GHWCFG2_NUMDEVEPS_DEFAULT         0x0
-#define GC_USB_GHWCFG2_NUMDEVEPS_OFFSET          0x48
-#define GC_USB_GHWCFG2_NUMHSTCHNL_LSB            0xe
-#define GC_USB_GHWCFG2_NUMHSTCHNL_MASK           0x3c000
-#define GC_USB_GHWCFG2_NUMHSTCHNL_SIZE           0x4
-#define GC_USB_GHWCFG2_NUMHSTCHNL_DEFAULT        0x0
-#define GC_USB_GHWCFG2_NUMHSTCHNL_OFFSET         0x48
-#define GC_USB_GHWCFG2_PERIOSUPPORT_LSB          0x12
-#define GC_USB_GHWCFG2_PERIOSUPPORT_MASK         0x40000
-#define GC_USB_GHWCFG2_PERIOSUPPORT_SIZE         0x1
-#define GC_USB_GHWCFG2_PERIOSUPPORT_DEFAULT      0x0
-#define GC_USB_GHWCFG2_PERIOSUPPORT_OFFSET       0x48
-#define GC_USB_GHWCFG2_DYNFIFOSIZING_LSB         0x13
-#define GC_USB_GHWCFG2_DYNFIFOSIZING_MASK        0x80000
-#define GC_USB_GHWCFG2_DYNFIFOSIZING_SIZE        0x1
-#define GC_USB_GHWCFG2_DYNFIFOSIZING_DEFAULT     0x0
-#define GC_USB_GHWCFG2_DYNFIFOSIZING_OFFSET      0x48
-#define GC_USB_GHWCFG2_MULTIPROCINTRPT_LSB       0x14
-#define GC_USB_GHWCFG2_MULTIPROCINTRPT_MASK      0x100000
-#define GC_USB_GHWCFG2_MULTIPROCINTRPT_SIZE      0x1
-#define GC_USB_GHWCFG2_MULTIPROCINTRPT_DEFAULT   0x0
-#define GC_USB_GHWCFG2_MULTIPROCINTRPT_OFFSET    0x48
-#define GC_USB_GHWCFG2_NPTXQDEPTH_LSB            0x16
-#define GC_USB_GHWCFG2_NPTXQDEPTH_MASK           0xc00000
-#define GC_USB_GHWCFG2_NPTXQDEPTH_SIZE           0x2
-#define GC_USB_GHWCFG2_NPTXQDEPTH_DEFAULT        0x0
-#define GC_USB_GHWCFG2_NPTXQDEPTH_OFFSET         0x48
-#define GC_USB_GHWCFG2_PTXQDEPTH_LSB             0x18
-#define GC_USB_GHWCFG2_PTXQDEPTH_MASK            0x3000000
-#define GC_USB_GHWCFG2_PTXQDEPTH_SIZE            0x2
-#define GC_USB_GHWCFG2_PTXQDEPTH_DEFAULT         0x0
-#define GC_USB_GHWCFG2_PTXQDEPTH_OFFSET          0x48
-#define GC_USB_GHWCFG2_TKNQDEPTH_LSB             0x1a
-#define GC_USB_GHWCFG2_TKNQDEPTH_MASK            0x7c000000
-#define GC_USB_GHWCFG2_TKNQDEPTH_SIZE            0x5
-#define GC_USB_GHWCFG2_TKNQDEPTH_DEFAULT         0x0
-#define GC_USB_GHWCFG2_TKNQDEPTH_OFFSET          0x48
-#define GC_USB_GHWCFG3_XFERSIZEWIDTH_LSB         0x0
-#define GC_USB_GHWCFG3_XFERSIZEWIDTH_MASK        0xf
-#define GC_USB_GHWCFG3_XFERSIZEWIDTH_SIZE        0x4
-#define GC_USB_GHWCFG3_XFERSIZEWIDTH_DEFAULT     0x0
-#define GC_USB_GHWCFG3_XFERSIZEWIDTH_OFFSET      0x4c
-#define GC_USB_GHWCFG3_PKTSIZEWIDTH_LSB          0x4
-#define GC_USB_GHWCFG3_PKTSIZEWIDTH_MASK         0x70
-#define GC_USB_GHWCFG3_PKTSIZEWIDTH_SIZE         0x3
-#define GC_USB_GHWCFG3_PKTSIZEWIDTH_DEFAULT      0x0
-#define GC_USB_GHWCFG3_PKTSIZEWIDTH_OFFSET       0x4c
-#define GC_USB_GHWCFG3_OTGEN_LSB                 0x7
-#define GC_USB_GHWCFG3_OTGEN_MASK                0x80
-#define GC_USB_GHWCFG3_OTGEN_SIZE                0x1
-#define GC_USB_GHWCFG3_OTGEN_DEFAULT             0x0
-#define GC_USB_GHWCFG3_OTGEN_OFFSET              0x4c
-#define GC_USB_GHWCFG3_I2CINTSEL_LSB             0x8
-#define GC_USB_GHWCFG3_I2CINTSEL_MASK            0x100
-#define GC_USB_GHWCFG3_I2CINTSEL_SIZE            0x1
-#define GC_USB_GHWCFG3_I2CINTSEL_DEFAULT         0x0
-#define GC_USB_GHWCFG3_I2CINTSEL_OFFSET          0x4c
-#define GC_USB_GHWCFG3_VNDCTLSUPT_LSB            0x9
-#define GC_USB_GHWCFG3_VNDCTLSUPT_MASK           0x200
-#define GC_USB_GHWCFG3_VNDCTLSUPT_SIZE           0x1
-#define GC_USB_GHWCFG3_VNDCTLSUPT_DEFAULT        0x0
-#define GC_USB_GHWCFG3_VNDCTLSUPT_OFFSET         0x4c
-#define GC_USB_GHWCFG3_OPTFEATURE_LSB            0xa
-#define GC_USB_GHWCFG3_OPTFEATURE_MASK           0x400
-#define GC_USB_GHWCFG3_OPTFEATURE_SIZE           0x1
-#define GC_USB_GHWCFG3_OPTFEATURE_DEFAULT        0x0
-#define GC_USB_GHWCFG3_OPTFEATURE_OFFSET         0x4c
-#define GC_USB_GHWCFG3_RSTTYPE_LSB               0xb
-#define GC_USB_GHWCFG3_RSTTYPE_MASK              0x800
-#define GC_USB_GHWCFG3_RSTTYPE_SIZE              0x1
-#define GC_USB_GHWCFG3_RSTTYPE_DEFAULT           0x0
-#define GC_USB_GHWCFG3_RSTTYPE_OFFSET            0x4c
-#define GC_USB_GHWCFG3_ADPSUPPORT_LSB            0xc
-#define GC_USB_GHWCFG3_ADPSUPPORT_MASK           0x1000
-#define GC_USB_GHWCFG3_ADPSUPPORT_SIZE           0x1
-#define GC_USB_GHWCFG3_ADPSUPPORT_DEFAULT        0x0
-#define GC_USB_GHWCFG3_ADPSUPPORT_OFFSET         0x4c
-#define GC_USB_GHWCFG3_HSICMODE_LSB              0xd
-#define GC_USB_GHWCFG3_HSICMODE_MASK             0x2000
-#define GC_USB_GHWCFG3_HSICMODE_SIZE             0x1
-#define GC_USB_GHWCFG3_HSICMODE_DEFAULT          0x0
-#define GC_USB_GHWCFG3_HSICMODE_OFFSET           0x4c
-#define GC_USB_GHWCFG3_BCSUPPORT_LSB             0xe
-#define GC_USB_GHWCFG3_BCSUPPORT_MASK            0x4000
-#define GC_USB_GHWCFG3_BCSUPPORT_SIZE            0x1
-#define GC_USB_GHWCFG3_BCSUPPORT_DEFAULT         0x0
-#define GC_USB_GHWCFG3_BCSUPPORT_OFFSET          0x4c
-#define GC_USB_GHWCFG3_LPMMODE_LSB               0xf
-#define GC_USB_GHWCFG3_LPMMODE_MASK              0x8000
-#define GC_USB_GHWCFG3_LPMMODE_SIZE              0x1
-#define GC_USB_GHWCFG3_LPMMODE_DEFAULT           0x0
-#define GC_USB_GHWCFG3_LPMMODE_OFFSET            0x4c
-#define GC_USB_GHWCFG3_DFIFODEPTH_LSB            0x10
-#define GC_USB_GHWCFG3_DFIFODEPTH_MASK           0xffff0000
-#define GC_USB_GHWCFG3_DFIFODEPTH_SIZE           0x10
-#define GC_USB_GHWCFG3_DFIFODEPTH_DEFAULT        0x0
-#define GC_USB_GHWCFG3_DFIFODEPTH_OFFSET         0x4c
-#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_LSB        0x0
-#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_MASK       0xf
-#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_SIZE       0x4
-#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_DEFAULT    0x0
-#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_OFFSET     0x50
-#define GC_USB_GHWCFG4_PARTIALPWRDN_LSB          0x4
-#define GC_USB_GHWCFG4_PARTIALPWRDN_MASK         0x10
-#define GC_USB_GHWCFG4_PARTIALPWRDN_SIZE         0x1
-#define GC_USB_GHWCFG4_PARTIALPWRDN_DEFAULT      0x0
-#define GC_USB_GHWCFG4_PARTIALPWRDN_OFFSET       0x50
-#define GC_USB_GHWCFG4_AHBFREQ_LSB               0x5
-#define GC_USB_GHWCFG4_AHBFREQ_MASK              0x20
-#define GC_USB_GHWCFG4_AHBFREQ_SIZE              0x1
-#define GC_USB_GHWCFG4_AHBFREQ_DEFAULT           0x0
-#define GC_USB_GHWCFG4_AHBFREQ_OFFSET            0x50
-#define GC_USB_GHWCFG4_HIBERNATION_LSB           0x6
-#define GC_USB_GHWCFG4_HIBERNATION_MASK          0x40
-#define GC_USB_GHWCFG4_HIBERNATION_SIZE          0x1
-#define GC_USB_GHWCFG4_HIBERNATION_DEFAULT       0x0
-#define GC_USB_GHWCFG4_HIBERNATION_OFFSET        0x50
-#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_LSB   0x7
-#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_MASK  0x80
-#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_SIZE  0x1
+#define GC_USB_GUID_GUID_LSB 0x0
+#define GC_USB_GUID_GUID_MASK 0xffffffff
+#define GC_USB_GUID_GUID_SIZE 0x20
+#define GC_USB_GUID_GUID_DEFAULT 0x0
+#define GC_USB_GUID_GUID_OFFSET 0x3c
+#define GC_USB_GSNPSID_SYNOPSYSID_LSB 0x0
+#define GC_USB_GSNPSID_SYNOPSYSID_MASK 0xffffffff
+#define GC_USB_GSNPSID_SYNOPSYSID_SIZE 0x20
+#define GC_USB_GSNPSID_SYNOPSYSID_DEFAULT 0x0
+#define GC_USB_GSNPSID_SYNOPSYSID_OFFSET 0x40
+#define GC_USB_GHWCFG1_EPDIR_LSB 0x0
+#define GC_USB_GHWCFG1_EPDIR_MASK 0xffffffff
+#define GC_USB_GHWCFG1_EPDIR_SIZE 0x20
+#define GC_USB_GHWCFG1_EPDIR_DEFAULT 0x0
+#define GC_USB_GHWCFG1_EPDIR_OFFSET 0x44
+#define GC_USB_GHWCFG2_OTGMODE_LSB 0x0
+#define GC_USB_GHWCFG2_OTGMODE_MASK 0x7
+#define GC_USB_GHWCFG2_OTGMODE_SIZE 0x3
+#define GC_USB_GHWCFG2_OTGMODE_DEFAULT 0x0
+#define GC_USB_GHWCFG2_OTGMODE_OFFSET 0x48
+#define GC_USB_GHWCFG2_OTGARCH_LSB 0x3
+#define GC_USB_GHWCFG2_OTGARCH_MASK 0x18
+#define GC_USB_GHWCFG2_OTGARCH_SIZE 0x2
+#define GC_USB_GHWCFG2_OTGARCH_DEFAULT 0x0
+#define GC_USB_GHWCFG2_OTGARCH_OFFSET 0x48
+#define GC_USB_GHWCFG2_SINGPNT_LSB 0x5
+#define GC_USB_GHWCFG2_SINGPNT_MASK 0x20
+#define GC_USB_GHWCFG2_SINGPNT_SIZE 0x1
+#define GC_USB_GHWCFG2_SINGPNT_DEFAULT 0x0
+#define GC_USB_GHWCFG2_SINGPNT_OFFSET 0x48
+#define GC_USB_GHWCFG2_HSPHYTYPE_LSB 0x6
+#define GC_USB_GHWCFG2_HSPHYTYPE_MASK 0xc0
+#define GC_USB_GHWCFG2_HSPHYTYPE_SIZE 0x2
+#define GC_USB_GHWCFG2_HSPHYTYPE_DEFAULT 0x0
+#define GC_USB_GHWCFG2_HSPHYTYPE_OFFSET 0x48
+#define GC_USB_GHWCFG2_FSPHYTYPE_LSB 0x8
+#define GC_USB_GHWCFG2_FSPHYTYPE_MASK 0x300
+#define GC_USB_GHWCFG2_FSPHYTYPE_SIZE 0x2
+#define GC_USB_GHWCFG2_FSPHYTYPE_DEFAULT 0x0
+#define GC_USB_GHWCFG2_FSPHYTYPE_OFFSET 0x48
+#define GC_USB_GHWCFG2_NUMDEVEPS_LSB 0xa
+#define GC_USB_GHWCFG2_NUMDEVEPS_MASK 0x3c00
+#define GC_USB_GHWCFG2_NUMDEVEPS_SIZE 0x4
+#define GC_USB_GHWCFG2_NUMDEVEPS_DEFAULT 0x0
+#define GC_USB_GHWCFG2_NUMDEVEPS_OFFSET 0x48
+#define GC_USB_GHWCFG2_NUMHSTCHNL_LSB 0xe
+#define GC_USB_GHWCFG2_NUMHSTCHNL_MASK 0x3c000
+#define GC_USB_GHWCFG2_NUMHSTCHNL_SIZE 0x4
+#define GC_USB_GHWCFG2_NUMHSTCHNL_DEFAULT 0x0
+#define GC_USB_GHWCFG2_NUMHSTCHNL_OFFSET 0x48
+#define GC_USB_GHWCFG2_PERIOSUPPORT_LSB 0x12
+#define GC_USB_GHWCFG2_PERIOSUPPORT_MASK 0x40000
+#define GC_USB_GHWCFG2_PERIOSUPPORT_SIZE 0x1
+#define GC_USB_GHWCFG2_PERIOSUPPORT_DEFAULT 0x0
+#define GC_USB_GHWCFG2_PERIOSUPPORT_OFFSET 0x48
+#define GC_USB_GHWCFG2_DYNFIFOSIZING_LSB 0x13
+#define GC_USB_GHWCFG2_DYNFIFOSIZING_MASK 0x80000
+#define GC_USB_GHWCFG2_DYNFIFOSIZING_SIZE 0x1
+#define GC_USB_GHWCFG2_DYNFIFOSIZING_DEFAULT 0x0
+#define GC_USB_GHWCFG2_DYNFIFOSIZING_OFFSET 0x48
+#define GC_USB_GHWCFG2_MULTIPROCINTRPT_LSB 0x14
+#define GC_USB_GHWCFG2_MULTIPROCINTRPT_MASK 0x100000
+#define GC_USB_GHWCFG2_MULTIPROCINTRPT_SIZE 0x1
+#define GC_USB_GHWCFG2_MULTIPROCINTRPT_DEFAULT 0x0
+#define GC_USB_GHWCFG2_MULTIPROCINTRPT_OFFSET 0x48
+#define GC_USB_GHWCFG2_NPTXQDEPTH_LSB 0x16
+#define GC_USB_GHWCFG2_NPTXQDEPTH_MASK 0xc00000
+#define GC_USB_GHWCFG2_NPTXQDEPTH_SIZE 0x2
+#define GC_USB_GHWCFG2_NPTXQDEPTH_DEFAULT 0x0
+#define GC_USB_GHWCFG2_NPTXQDEPTH_OFFSET 0x48
+#define GC_USB_GHWCFG2_PTXQDEPTH_LSB 0x18
+#define GC_USB_GHWCFG2_PTXQDEPTH_MASK 0x3000000
+#define GC_USB_GHWCFG2_PTXQDEPTH_SIZE 0x2
+#define GC_USB_GHWCFG2_PTXQDEPTH_DEFAULT 0x0
+#define GC_USB_GHWCFG2_PTXQDEPTH_OFFSET 0x48
+#define GC_USB_GHWCFG2_TKNQDEPTH_LSB 0x1a
+#define GC_USB_GHWCFG2_TKNQDEPTH_MASK 0x7c000000
+#define GC_USB_GHWCFG2_TKNQDEPTH_SIZE 0x5
+#define GC_USB_GHWCFG2_TKNQDEPTH_DEFAULT 0x0
+#define GC_USB_GHWCFG2_TKNQDEPTH_OFFSET 0x48
+#define GC_USB_GHWCFG3_XFERSIZEWIDTH_LSB 0x0
+#define GC_USB_GHWCFG3_XFERSIZEWIDTH_MASK 0xf
+#define GC_USB_GHWCFG3_XFERSIZEWIDTH_SIZE 0x4
+#define GC_USB_GHWCFG3_XFERSIZEWIDTH_DEFAULT 0x0
+#define GC_USB_GHWCFG3_XFERSIZEWIDTH_OFFSET 0x4c
+#define GC_USB_GHWCFG3_PKTSIZEWIDTH_LSB 0x4
+#define GC_USB_GHWCFG3_PKTSIZEWIDTH_MASK 0x70
+#define GC_USB_GHWCFG3_PKTSIZEWIDTH_SIZE 0x3
+#define GC_USB_GHWCFG3_PKTSIZEWIDTH_DEFAULT 0x0
+#define GC_USB_GHWCFG3_PKTSIZEWIDTH_OFFSET 0x4c
+#define GC_USB_GHWCFG3_OTGEN_LSB 0x7
+#define GC_USB_GHWCFG3_OTGEN_MASK 0x80
+#define GC_USB_GHWCFG3_OTGEN_SIZE 0x1
+#define GC_USB_GHWCFG3_OTGEN_DEFAULT 0x0
+#define GC_USB_GHWCFG3_OTGEN_OFFSET 0x4c
+#define GC_USB_GHWCFG3_I2CINTSEL_LSB 0x8
+#define GC_USB_GHWCFG3_I2CINTSEL_MASK 0x100
+#define GC_USB_GHWCFG3_I2CINTSEL_SIZE 0x1
+#define GC_USB_GHWCFG3_I2CINTSEL_DEFAULT 0x0
+#define GC_USB_GHWCFG3_I2CINTSEL_OFFSET 0x4c
+#define GC_USB_GHWCFG3_VNDCTLSUPT_LSB 0x9
+#define GC_USB_GHWCFG3_VNDCTLSUPT_MASK 0x200
+#define GC_USB_GHWCFG3_VNDCTLSUPT_SIZE 0x1
+#define GC_USB_GHWCFG3_VNDCTLSUPT_DEFAULT 0x0
+#define GC_USB_GHWCFG3_VNDCTLSUPT_OFFSET 0x4c
+#define GC_USB_GHWCFG3_OPTFEATURE_LSB 0xa
+#define GC_USB_GHWCFG3_OPTFEATURE_MASK 0x400
+#define GC_USB_GHWCFG3_OPTFEATURE_SIZE 0x1
+#define GC_USB_GHWCFG3_OPTFEATURE_DEFAULT 0x0
+#define GC_USB_GHWCFG3_OPTFEATURE_OFFSET 0x4c
+#define GC_USB_GHWCFG3_RSTTYPE_LSB 0xb
+#define GC_USB_GHWCFG3_RSTTYPE_MASK 0x800
+#define GC_USB_GHWCFG3_RSTTYPE_SIZE 0x1
+#define GC_USB_GHWCFG3_RSTTYPE_DEFAULT 0x0
+#define GC_USB_GHWCFG3_RSTTYPE_OFFSET 0x4c
+#define GC_USB_GHWCFG3_ADPSUPPORT_LSB 0xc
+#define GC_USB_GHWCFG3_ADPSUPPORT_MASK 0x1000
+#define GC_USB_GHWCFG3_ADPSUPPORT_SIZE 0x1
+#define GC_USB_GHWCFG3_ADPSUPPORT_DEFAULT 0x0
+#define GC_USB_GHWCFG3_ADPSUPPORT_OFFSET 0x4c
+#define GC_USB_GHWCFG3_HSICMODE_LSB 0xd
+#define GC_USB_GHWCFG3_HSICMODE_MASK 0x2000
+#define GC_USB_GHWCFG3_HSICMODE_SIZE 0x1
+#define GC_USB_GHWCFG3_HSICMODE_DEFAULT 0x0
+#define GC_USB_GHWCFG3_HSICMODE_OFFSET 0x4c
+#define GC_USB_GHWCFG3_BCSUPPORT_LSB 0xe
+#define GC_USB_GHWCFG3_BCSUPPORT_MASK 0x4000
+#define GC_USB_GHWCFG3_BCSUPPORT_SIZE 0x1
+#define GC_USB_GHWCFG3_BCSUPPORT_DEFAULT 0x0
+#define GC_USB_GHWCFG3_BCSUPPORT_OFFSET 0x4c
+#define GC_USB_GHWCFG3_LPMMODE_LSB 0xf
+#define GC_USB_GHWCFG3_LPMMODE_MASK 0x8000
+#define GC_USB_GHWCFG3_LPMMODE_SIZE 0x1
+#define GC_USB_GHWCFG3_LPMMODE_DEFAULT 0x0
+#define GC_USB_GHWCFG3_LPMMODE_OFFSET 0x4c
+#define GC_USB_GHWCFG3_DFIFODEPTH_LSB 0x10
+#define GC_USB_GHWCFG3_DFIFODEPTH_MASK 0xffff0000
+#define GC_USB_GHWCFG3_DFIFODEPTH_SIZE 0x10
+#define GC_USB_GHWCFG3_DFIFODEPTH_DEFAULT 0x0
+#define GC_USB_GHWCFG3_DFIFODEPTH_OFFSET 0x4c
+#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_LSB 0x0
+#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_MASK 0xf
+#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_SIZE 0x4
+#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_DEFAULT 0x0
+#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_OFFSET 0x50
+#define GC_USB_GHWCFG4_PARTIALPWRDN_LSB 0x4
+#define GC_USB_GHWCFG4_PARTIALPWRDN_MASK 0x10
+#define GC_USB_GHWCFG4_PARTIALPWRDN_SIZE 0x1
+#define GC_USB_GHWCFG4_PARTIALPWRDN_DEFAULT 0x0
+#define GC_USB_GHWCFG4_PARTIALPWRDN_OFFSET 0x50
+#define GC_USB_GHWCFG4_AHBFREQ_LSB 0x5
+#define GC_USB_GHWCFG4_AHBFREQ_MASK 0x20
+#define GC_USB_GHWCFG4_AHBFREQ_SIZE 0x1
+#define GC_USB_GHWCFG4_AHBFREQ_DEFAULT 0x0
+#define GC_USB_GHWCFG4_AHBFREQ_OFFSET 0x50
+#define GC_USB_GHWCFG4_HIBERNATION_LSB 0x6
+#define GC_USB_GHWCFG4_HIBERNATION_MASK 0x40
+#define GC_USB_GHWCFG4_HIBERNATION_SIZE 0x1
+#define GC_USB_GHWCFG4_HIBERNATION_DEFAULT 0x0
+#define GC_USB_GHWCFG4_HIBERNATION_OFFSET 0x50
+#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_LSB 0x7
+#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_MASK 0x80
+#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_SIZE 0x1
 #define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_DEFAULT 0x0
 #define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_OFFSET 0x50
-#define GC_USB_GHWCFG4_PHYDATAWIDTH_LSB          0xe
-#define GC_USB_GHWCFG4_PHYDATAWIDTH_MASK         0xc000
-#define GC_USB_GHWCFG4_PHYDATAWIDTH_SIZE         0x2
-#define GC_USB_GHWCFG4_PHYDATAWIDTH_DEFAULT      0x0
-#define GC_USB_GHWCFG4_PHYDATAWIDTH_OFFSET       0x50
-#define GC_USB_GHWCFG4_NUMCTLEPS_LSB             0x10
-#define GC_USB_GHWCFG4_NUMCTLEPS_MASK            0xf0000
-#define GC_USB_GHWCFG4_NUMCTLEPS_SIZE            0x4
-#define GC_USB_GHWCFG4_NUMCTLEPS_DEFAULT         0x0
-#define GC_USB_GHWCFG4_NUMCTLEPS_OFFSET          0x50
-#define GC_USB_GHWCFG4_IDDGFLTR_LSB              0x14
-#define GC_USB_GHWCFG4_IDDGFLTR_MASK             0x100000
-#define GC_USB_GHWCFG4_IDDGFLTR_SIZE             0x1
-#define GC_USB_GHWCFG4_IDDGFLTR_DEFAULT          0x0
-#define GC_USB_GHWCFG4_IDDGFLTR_OFFSET           0x50
-#define GC_USB_GHWCFG4_VBUSVALIDFLTR_LSB         0x15
-#define GC_USB_GHWCFG4_VBUSVALIDFLTR_MASK        0x200000
-#define GC_USB_GHWCFG4_VBUSVALIDFLTR_SIZE        0x1
-#define GC_USB_GHWCFG4_VBUSVALIDFLTR_DEFAULT     0x0
-#define GC_USB_GHWCFG4_VBUSVALIDFLTR_OFFSET      0x50
-#define GC_USB_GHWCFG4_AVALIDFLTR_LSB            0x16
-#define GC_USB_GHWCFG4_AVALIDFLTR_MASK           0x400000
-#define GC_USB_GHWCFG4_AVALIDFLTR_SIZE           0x1
-#define GC_USB_GHWCFG4_AVALIDFLTR_DEFAULT        0x0
-#define GC_USB_GHWCFG4_AVALIDFLTR_OFFSET         0x50
-#define GC_USB_GHWCFG4_BVALIDFLTR_LSB            0x17
-#define GC_USB_GHWCFG4_BVALIDFLTR_MASK           0x800000
-#define GC_USB_GHWCFG4_BVALIDFLTR_SIZE           0x1
-#define GC_USB_GHWCFG4_BVALIDFLTR_DEFAULT        0x0
-#define GC_USB_GHWCFG4_BVALIDFLTR_OFFSET         0x50
-#define GC_USB_GHWCFG4_SESSENDFLTR_LSB           0x18
-#define GC_USB_GHWCFG4_SESSENDFLTR_MASK          0x1000000
-#define GC_USB_GHWCFG4_SESSENDFLTR_SIZE          0x1
-#define GC_USB_GHWCFG4_SESSENDFLTR_DEFAULT       0x0
-#define GC_USB_GHWCFG4_SESSENDFLTR_OFFSET        0x50
-#define GC_USB_GHWCFG4_DEDFIFOMODE_LSB           0x19
-#define GC_USB_GHWCFG4_DEDFIFOMODE_MASK          0x2000000
-#define GC_USB_GHWCFG4_DEDFIFOMODE_SIZE          0x1
-#define GC_USB_GHWCFG4_DEDFIFOMODE_DEFAULT       0x0
-#define GC_USB_GHWCFG4_DEDFIFOMODE_OFFSET        0x50
-#define GC_USB_GHWCFG4_INEPS_LSB                 0x1a
-#define GC_USB_GHWCFG4_INEPS_MASK                0x3c000000
-#define GC_USB_GHWCFG4_INEPS_SIZE                0x4
-#define GC_USB_GHWCFG4_INEPS_DEFAULT             0x0
-#define GC_USB_GHWCFG4_INEPS_OFFSET              0x50
-#define GC_USB_GHWCFG4_DESCDMAENABLED_LSB        0x1e
-#define GC_USB_GHWCFG4_DESCDMAENABLED_MASK       0x40000000
-#define GC_USB_GHWCFG4_DESCDMAENABLED_SIZE       0x1
-#define GC_USB_GHWCFG4_DESCDMAENABLED_DEFAULT    0x0
-#define GC_USB_GHWCFG4_DESCDMAENABLED_OFFSET     0x50
-#define GC_USB_GHWCFG4_DESCDMA_LSB               0x1f
-#define GC_USB_GHWCFG4_DESCDMA_MASK              0x80000000
-#define GC_USB_GHWCFG4_DESCDMA_SIZE              0x1
-#define GC_USB_GHWCFG4_DESCDMA_DEFAULT           0x0
-#define GC_USB_GHWCFG4_DESCDMA_OFFSET            0x50
-#define GC_USB_GDFIFOCFG_GDFIFOCFG_LSB           0x0
-#define GC_USB_GDFIFOCFG_GDFIFOCFG_MASK          0xffff
-#define GC_USB_GDFIFOCFG_GDFIFOCFG_SIZE          0x10
-#define GC_USB_GDFIFOCFG_GDFIFOCFG_DEFAULT       0x0
-#define GC_USB_GDFIFOCFG_GDFIFOCFG_OFFSET        0x5c
-#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_LSB      0x10
-#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_MASK     0xffff0000
-#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_SIZE     0x10
-#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_DEFAULT  0x0
-#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_OFFSET   0x5c
-#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_OFFSET    0x104
-#define GC_USB_DIEPTXF1_RESERVED11_LSB           0xc
-#define GC_USB_DIEPTXF1_RESERVED11_MASK          0x1000
-#define GC_USB_DIEPTXF1_RESERVED11_SIZE          0x1
-#define GC_USB_DIEPTXF1_RESERVED11_DEFAULT       0x1
-#define GC_USB_DIEPTXF1_RESERVED11_OFFSET        0x104
-#define GC_USB_DIEPTXF1_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF1_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF1_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF1_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF1_INEPNTXFDEP_OFFSET       0x104
-#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_OFFSET    0x108
-#define GC_USB_DIEPTXF2_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF2_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF2_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF2_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF2_INEPNTXFDEP_OFFSET       0x108
-#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_OFFSET    0x10c
-#define GC_USB_DIEPTXF3_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF3_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF3_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF3_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF3_INEPNTXFDEP_OFFSET       0x10c
-#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_OFFSET    0x110
-#define GC_USB_DIEPTXF4_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF4_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF4_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF4_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF4_INEPNTXFDEP_OFFSET       0x110
-#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_OFFSET    0x114
-#define GC_USB_DIEPTXF5_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF5_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF5_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF5_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF5_INEPNTXFDEP_OFFSET       0x114
-#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_OFFSET    0x118
-#define GC_USB_DIEPTXF6_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF6_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF6_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF6_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF6_INEPNTXFDEP_OFFSET       0x118
-#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_OFFSET    0x11c
-#define GC_USB_DIEPTXF7_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF7_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF7_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF7_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF7_INEPNTXFDEP_OFFSET       0x11c
-#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_OFFSET    0x120
-#define GC_USB_DIEPTXF8_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF8_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF8_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF8_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF8_INEPNTXFDEP_OFFSET       0x120
-#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_OFFSET    0x124
-#define GC_USB_DIEPTXF9_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF9_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF9_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF9_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF9_INEPNTXFDEP_OFFSET       0x124
-#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_LSB      0x0
-#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_MASK     0x7ff
-#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_SIZE     0xb
-#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_DEFAULT  0x0
-#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_OFFSET   0x128
-#define GC_USB_DIEPTXF10_INEPNTXFDEP_LSB         0x10
-#define GC_USB_DIEPTXF10_INEPNTXFDEP_MASK        0x3f0000
-#define GC_USB_DIEPTXF10_INEPNTXFDEP_SIZE        0x6
-#define GC_USB_DIEPTXF10_INEPNTXFDEP_DEFAULT     0x0
-#define GC_USB_DIEPTXF10_INEPNTXFDEP_OFFSET      0x128
-#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_LSB      0x0
-#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_MASK     0x7ff
-#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_SIZE     0xb
-#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_DEFAULT  0x0
-#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_OFFSET   0x12c
-#define GC_USB_DIEPTXF11_INEPNTXFDEP_LSB         0x10
-#define GC_USB_DIEPTXF11_INEPNTXFDEP_MASK        0x3f0000
-#define GC_USB_DIEPTXF11_INEPNTXFDEP_SIZE        0x6
-#define GC_USB_DIEPTXF11_INEPNTXFDEP_DEFAULT     0x0
-#define GC_USB_DIEPTXF11_INEPNTXFDEP_OFFSET      0x12c
-#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_LSB      0x0
-#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_MASK     0x7ff
-#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_SIZE     0xb
-#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_DEFAULT  0x0
-#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_OFFSET   0x130
-#define GC_USB_DIEPTXF12_INEPNTXFDEP_LSB         0x10
-#define GC_USB_DIEPTXF12_INEPNTXFDEP_MASK        0x3f0000
-#define GC_USB_DIEPTXF12_INEPNTXFDEP_SIZE        0x6
-#define GC_USB_DIEPTXF12_INEPNTXFDEP_DEFAULT     0x0
-#define GC_USB_DIEPTXF12_INEPNTXFDEP_OFFSET      0x130
-#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_LSB      0x0
-#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_MASK     0x7ff
-#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_SIZE     0xb
-#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_DEFAULT  0x0
-#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_OFFSET   0x134
-#define GC_USB_DIEPTXF13_INEPNTXFDEP_LSB         0x10
-#define GC_USB_DIEPTXF13_INEPNTXFDEP_MASK        0x3f0000
-#define GC_USB_DIEPTXF13_INEPNTXFDEP_SIZE        0x6
-#define GC_USB_DIEPTXF13_INEPNTXFDEP_DEFAULT     0x0
-#define GC_USB_DIEPTXF13_INEPNTXFDEP_OFFSET      0x134
-#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_LSB      0x0
-#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_MASK     0x7ff
-#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_SIZE     0xb
-#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_DEFAULT  0x0
-#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_OFFSET   0x138
-#define GC_USB_DIEPTXF14_INEPNTXFDEP_LSB         0x10
-#define GC_USB_DIEPTXF14_INEPNTXFDEP_MASK        0x3f0000
-#define GC_USB_DIEPTXF14_INEPNTXFDEP_SIZE        0x6
-#define GC_USB_DIEPTXF14_INEPNTXFDEP_DEFAULT     0x0
-#define GC_USB_DIEPTXF14_INEPNTXFDEP_OFFSET      0x138
-#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_LSB      0x0
-#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_MASK     0x7ff
-#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_SIZE     0xb
-#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_DEFAULT  0x0
-#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_OFFSET   0x13c
-#define GC_USB_DIEPTXF15_INEPNTXFDEP_LSB         0x10
-#define GC_USB_DIEPTXF15_INEPNTXFDEP_MASK        0x3f0000
-#define GC_USB_DIEPTXF15_INEPNTXFDEP_SIZE        0x6
-#define GC_USB_DIEPTXF15_INEPNTXFDEP_DEFAULT     0x0
-#define GC_USB_DIEPTXF15_INEPNTXFDEP_OFFSET      0x13c
-#define GC_USB_DCFG_DEVSPD_LSB                   0x0
-#define GC_USB_DCFG_DEVSPD_MASK                  0x3
-#define GC_USB_DCFG_DEVSPD_SIZE                  0x2
-#define GC_USB_DCFG_DEVSPD_DEFAULT               0x0
-#define GC_USB_DCFG_DEVSPD_OFFSET                0x800
-#define GC_USB_DCFG_NZSTSOUTHSHK_LSB             0x2
-#define GC_USB_DCFG_NZSTSOUTHSHK_MASK            0x4
-#define GC_USB_DCFG_NZSTSOUTHSHK_SIZE            0x1
-#define GC_USB_DCFG_NZSTSOUTHSHK_DEFAULT         0x0
-#define GC_USB_DCFG_NZSTSOUTHSHK_OFFSET          0x800
-#define GC_USB_DCFG_ENA32KHZSUSP_LSB             0x3
-#define GC_USB_DCFG_ENA32KHZSUSP_MASK            0x8
-#define GC_USB_DCFG_ENA32KHZSUSP_SIZE            0x1
-#define GC_USB_DCFG_ENA32KHZSUSP_DEFAULT         0x0
-#define GC_USB_DCFG_ENA32KHZSUSP_OFFSET          0x800
-#define GC_USB_DCFG_DEVADDR_LSB                  0x4
-#define GC_USB_DCFG_DEVADDR_MASK                 0x7f0
-#define GC_USB_DCFG_DEVADDR_SIZE                 0x7
-#define GC_USB_DCFG_DEVADDR_DEFAULT              0x0
-#define GC_USB_DCFG_DEVADDR_OFFSET               0x800
-#define GC_USB_DCFG_PERFRINT_LSB                 0xb
-#define GC_USB_DCFG_PERFRINT_MASK                0x1800
-#define GC_USB_DCFG_PERFRINT_SIZE                0x2
-#define GC_USB_DCFG_PERFRINT_DEFAULT             0x0
-#define GC_USB_DCFG_PERFRINT_OFFSET              0x800
-#define GC_USB_DCFG_ENDEVOUTNAK_LSB              0xd
-#define GC_USB_DCFG_ENDEVOUTNAK_MASK             0x2000
-#define GC_USB_DCFG_ENDEVOUTNAK_SIZE             0x1
-#define GC_USB_DCFG_ENDEVOUTNAK_DEFAULT          0x0
-#define GC_USB_DCFG_ENDEVOUTNAK_OFFSET           0x800
-#define GC_USB_DCFG_XCVRDLY_LSB                  0xe
-#define GC_USB_DCFG_XCVRDLY_MASK                 0x4000
-#define GC_USB_DCFG_XCVRDLY_SIZE                 0x1
-#define GC_USB_DCFG_XCVRDLY_DEFAULT              0x0
-#define GC_USB_DCFG_XCVRDLY_OFFSET               0x800
-#define GC_USB_DCFG_ERRATICINTMSK_LSB            0xf
-#define GC_USB_DCFG_ERRATICINTMSK_MASK           0x8000
-#define GC_USB_DCFG_ERRATICINTMSK_SIZE           0x1
-#define GC_USB_DCFG_ERRATICINTMSK_DEFAULT        0x0
-#define GC_USB_DCFG_ERRATICINTMSK_OFFSET         0x800
-#define GC_USB_DCFG_DESCDMA_LSB                  0x17
-#define GC_USB_DCFG_DESCDMA_MASK                 0x800000
-#define GC_USB_DCFG_DESCDMA_SIZE                 0x1
-#define GC_USB_DCFG_DESCDMA_DEFAULT              0x0
-#define GC_USB_DCFG_DESCDMA_OFFSET               0x800
-#define GC_USB_DCFG_PERSCHINTVL_LSB              0x18
-#define GC_USB_DCFG_PERSCHINTVL_MASK             0x3000000
-#define GC_USB_DCFG_PERSCHINTVL_SIZE             0x2
-#define GC_USB_DCFG_PERSCHINTVL_DEFAULT          0x0
-#define GC_USB_DCFG_PERSCHINTVL_OFFSET           0x800
-#define GC_USB_DCFG_RESVALID_LSB                 0x1a
-#define GC_USB_DCFG_RESVALID_MASK                0xfc000000
-#define GC_USB_DCFG_RESVALID_SIZE                0x6
-#define GC_USB_DCFG_RESVALID_DEFAULT             0x2
-#define GC_USB_DCFG_RESVALID_OFFSET              0x800
-#define GC_USB_DCTL_RMTWKUPSIG_LSB               0x0
-#define GC_USB_DCTL_RMTWKUPSIG_MASK              0x1
-#define GC_USB_DCTL_RMTWKUPSIG_SIZE              0x1
-#define GC_USB_DCTL_RMTWKUPSIG_DEFAULT           0x0
-#define GC_USB_DCTL_RMTWKUPSIG_OFFSET            0x804
-#define GC_USB_DCTL_SFTDISCON_LSB                0x1
-#define GC_USB_DCTL_SFTDISCON_MASK               0x2
-#define GC_USB_DCTL_SFTDISCON_SIZE               0x1
-#define GC_USB_DCTL_SFTDISCON_DEFAULT            0x0
-#define GC_USB_DCTL_SFTDISCON_OFFSET             0x804
-#define GC_USB_DCTL_GNPINNAKSTS_LSB              0x2
-#define GC_USB_DCTL_GNPINNAKSTS_MASK             0x4
-#define GC_USB_DCTL_GNPINNAKSTS_SIZE             0x1
-#define GC_USB_DCTL_GNPINNAKSTS_DEFAULT          0x0
-#define GC_USB_DCTL_GNPINNAKSTS_OFFSET           0x804
-#define GC_USB_DCTL_GOUTNAKSTS_LSB               0x3
-#define GC_USB_DCTL_GOUTNAKSTS_MASK              0x8
-#define GC_USB_DCTL_GOUTNAKSTS_SIZE              0x1
-#define GC_USB_DCTL_GOUTNAKSTS_DEFAULT           0x0
-#define GC_USB_DCTL_GOUTNAKSTS_OFFSET            0x804
-#define GC_USB_DCTL_TSTCTL_LSB                   0x4
-#define GC_USB_DCTL_TSTCTL_MASK                  0x70
-#define GC_USB_DCTL_TSTCTL_SIZE                  0x3
-#define GC_USB_DCTL_TSTCTL_DEFAULT               0x0
-#define GC_USB_DCTL_TSTCTL_OFFSET                0x804
-#define GC_USB_DCTL_SGNPINNAK_LSB                0x7
-#define GC_USB_DCTL_SGNPINNAK_MASK               0x80
-#define GC_USB_DCTL_SGNPINNAK_SIZE               0x1
-#define GC_USB_DCTL_SGNPINNAK_DEFAULT            0x0
-#define GC_USB_DCTL_SGNPINNAK_OFFSET             0x804
-#define GC_USB_DCTL_CGNPINNAK_LSB                0x8
-#define GC_USB_DCTL_CGNPINNAK_MASK               0x100
-#define GC_USB_DCTL_CGNPINNAK_SIZE               0x1
-#define GC_USB_DCTL_CGNPINNAK_DEFAULT            0x0
-#define GC_USB_DCTL_CGNPINNAK_OFFSET             0x804
-#define GC_USB_DCTL_SGOUTNAK_LSB                 0x9
-#define GC_USB_DCTL_SGOUTNAK_MASK                0x200
-#define GC_USB_DCTL_SGOUTNAK_SIZE                0x1
-#define GC_USB_DCTL_SGOUTNAK_DEFAULT             0x0
-#define GC_USB_DCTL_SGOUTNAK_OFFSET              0x804
-#define GC_USB_DCTL_CGOUTNAK_LSB                 0xa
-#define GC_USB_DCTL_CGOUTNAK_MASK                0x400
-#define GC_USB_DCTL_CGOUTNAK_SIZE                0x1
-#define GC_USB_DCTL_CGOUTNAK_DEFAULT             0x0
-#define GC_USB_DCTL_CGOUTNAK_OFFSET              0x804
-#define GC_USB_DCTL_PWRONPRGDONE_LSB             0xb
-#define GC_USB_DCTL_PWRONPRGDONE_MASK            0x800
-#define GC_USB_DCTL_PWRONPRGDONE_SIZE            0x1
-#define GC_USB_DCTL_PWRONPRGDONE_DEFAULT         0x0
-#define GC_USB_DCTL_PWRONPRGDONE_OFFSET          0x804
-#define GC_USB_DCTL_GMC_LSB                      0xd
-#define GC_USB_DCTL_GMC_MASK                     0x6000
-#define GC_USB_DCTL_GMC_SIZE                     0x2
-#define GC_USB_DCTL_GMC_DEFAULT                  0x0
-#define GC_USB_DCTL_GMC_OFFSET                   0x804
-#define GC_USB_DCTL_IGNRFRMNUM_LSB               0xf
-#define GC_USB_DCTL_IGNRFRMNUM_MASK              0x8000
-#define GC_USB_DCTL_IGNRFRMNUM_SIZE              0x1
-#define GC_USB_DCTL_IGNRFRMNUM_DEFAULT           0x0
-#define GC_USB_DCTL_IGNRFRMNUM_OFFSET            0x804
-#define GC_USB_DCTL_NAKONBBLE_LSB                0x10
-#define GC_USB_DCTL_NAKONBBLE_MASK               0x10000
-#define GC_USB_DCTL_NAKONBBLE_SIZE               0x1
-#define GC_USB_DCTL_NAKONBBLE_DEFAULT            0x0
-#define GC_USB_DCTL_NAKONBBLE_OFFSET             0x804
-#define GC_USB_DCTL_ENCONTONBNA_LSB              0x11
-#define GC_USB_DCTL_ENCONTONBNA_MASK             0x20000
-#define GC_USB_DCTL_ENCONTONBNA_SIZE             0x1
-#define GC_USB_DCTL_ENCONTONBNA_DEFAULT          0x0
-#define GC_USB_DCTL_ENCONTONBNA_OFFSET           0x804
-#define GC_USB_DSTS_SUSPSTS_LSB                  0x0
-#define GC_USB_DSTS_SUSPSTS_MASK                 0x1
-#define GC_USB_DSTS_SUSPSTS_SIZE                 0x1
-#define GC_USB_DSTS_SUSPSTS_DEFAULT              0x0
-#define GC_USB_DSTS_SUSPSTS_OFFSET               0x808
-#define GC_USB_DSTS_ENUMSPD_LSB                  0x1
-#define GC_USB_DSTS_ENUMSPD_MASK                 0x6
-#define GC_USB_DSTS_ENUMSPD_SIZE                 0x2
-#define GC_USB_DSTS_ENUMSPD_DEFAULT              0x0
-#define GC_USB_DSTS_ENUMSPD_OFFSET               0x808
-#define GC_USB_DSTS_ERRTICERR_LSB                0x3
-#define GC_USB_DSTS_ERRTICERR_MASK               0x8
-#define GC_USB_DSTS_ERRTICERR_SIZE               0x1
-#define GC_USB_DSTS_ERRTICERR_DEFAULT            0x0
-#define GC_USB_DSTS_ERRTICERR_OFFSET             0x808
-#define GC_USB_DSTS_SOFFN_LSB                    0x8
-#define GC_USB_DSTS_SOFFN_MASK                   0x3fff00
-#define GC_USB_DSTS_SOFFN_SIZE                   0xe
-#define GC_USB_DSTS_SOFFN_DEFAULT                0x0
-#define GC_USB_DSTS_SOFFN_OFFSET                 0x808
-#define GC_USB_DSTS_DEVLNSTS_LSB                 0x16
-#define GC_USB_DSTS_DEVLNSTS_MASK                0xc00000
-#define GC_USB_DSTS_DEVLNSTS_SIZE                0x2
-#define GC_USB_DSTS_DEVLNSTS_DEFAULT             0x0
-#define GC_USB_DSTS_DEVLNSTS_OFFSET              0x808
-#define GC_USB_DIEPMSK_XFERCOMPLMSK_LSB          0x0
-#define GC_USB_DIEPMSK_XFERCOMPLMSK_MASK         0x1
-#define GC_USB_DIEPMSK_XFERCOMPLMSK_SIZE         0x1
-#define GC_USB_DIEPMSK_XFERCOMPLMSK_DEFAULT      0x0
-#define GC_USB_DIEPMSK_XFERCOMPLMSK_OFFSET       0x810
-#define GC_USB_DIEPMSK_EPDISBLDMSK_LSB           0x1
-#define GC_USB_DIEPMSK_EPDISBLDMSK_MASK          0x2
-#define GC_USB_DIEPMSK_EPDISBLDMSK_SIZE          0x1
-#define GC_USB_DIEPMSK_EPDISBLDMSK_DEFAULT       0x0
-#define GC_USB_DIEPMSK_EPDISBLDMSK_OFFSET        0x810
-#define GC_USB_DIEPMSK_AHBERRMSK_LSB             0x2
-#define GC_USB_DIEPMSK_AHBERRMSK_MASK            0x4
-#define GC_USB_DIEPMSK_AHBERRMSK_SIZE            0x1
-#define GC_USB_DIEPMSK_AHBERRMSK_DEFAULT         0x0
-#define GC_USB_DIEPMSK_AHBERRMSK_OFFSET          0x810
-#define GC_USB_DIEPMSK_TIMEOUTMSK_LSB            0x3
-#define GC_USB_DIEPMSK_TIMEOUTMSK_MASK           0x8
-#define GC_USB_DIEPMSK_TIMEOUTMSK_SIZE           0x1
-#define GC_USB_DIEPMSK_TIMEOUTMSK_DEFAULT        0x0
-#define GC_USB_DIEPMSK_TIMEOUTMSK_OFFSET         0x810
-#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_LSB        0x4
-#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_MASK       0x10
-#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_SIZE       0x1
-#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_DEFAULT    0x0
-#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_OFFSET     0x810
-#define GC_USB_DIEPMSK_INTKNEPMISMSK_LSB         0x5
-#define GC_USB_DIEPMSK_INTKNEPMISMSK_MASK        0x20
-#define GC_USB_DIEPMSK_INTKNEPMISMSK_SIZE        0x1
-#define GC_USB_DIEPMSK_INTKNEPMISMSK_DEFAULT     0x0
-#define GC_USB_DIEPMSK_INTKNEPMISMSK_OFFSET      0x810
-#define GC_USB_DIEPMSK_INEPNAKEFFMSK_LSB         0x6
-#define GC_USB_DIEPMSK_INEPNAKEFFMSK_MASK        0x40
-#define GC_USB_DIEPMSK_INEPNAKEFFMSK_SIZE        0x1
-#define GC_USB_DIEPMSK_INEPNAKEFFMSK_DEFAULT     0x0
-#define GC_USB_DIEPMSK_INEPNAKEFFMSK_OFFSET      0x810
-#define GC_USB_DIEPMSK_RESERVED7_LSB             0x7
-#define GC_USB_DIEPMSK_RESERVED7_MASK            0x80
-#define GC_USB_DIEPMSK_RESERVED7_SIZE            0x1
-#define GC_USB_DIEPMSK_RESERVED7_DEFAULT         0x1
-#define GC_USB_DIEPMSK_RESERVED7_OFFSET          0x810
-#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_LSB        0x8
-#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_MASK       0x100
-#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_SIZE       0x1
-#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_DEFAULT    0x0
-#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_OFFSET     0x810
-#define GC_USB_DIEPMSK_BNAININTRMSK_LSB          0x9
-#define GC_USB_DIEPMSK_BNAININTRMSK_MASK         0x200
-#define GC_USB_DIEPMSK_BNAININTRMSK_SIZE         0x1
-#define GC_USB_DIEPMSK_BNAININTRMSK_DEFAULT      0x0
-#define GC_USB_DIEPMSK_BNAININTRMSK_OFFSET       0x810
-#define GC_USB_DIEPMSK_NAKMSK_LSB                0xd
-#define GC_USB_DIEPMSK_NAKMSK_MASK               0x2000
-#define GC_USB_DIEPMSK_NAKMSK_SIZE               0x1
-#define GC_USB_DIEPMSK_NAKMSK_DEFAULT            0x0
-#define GC_USB_DIEPMSK_NAKMSK_OFFSET             0x810
-#define GC_USB_DOEPMSK_XFERCOMPLMSK_LSB          0x0
-#define GC_USB_DOEPMSK_XFERCOMPLMSK_MASK         0x1
-#define GC_USB_DOEPMSK_XFERCOMPLMSK_SIZE         0x1
-#define GC_USB_DOEPMSK_XFERCOMPLMSK_DEFAULT      0x0
-#define GC_USB_DOEPMSK_XFERCOMPLMSK_OFFSET       0x814
-#define GC_USB_DOEPMSK_EPDISBLDMSK_LSB           0x1
-#define GC_USB_DOEPMSK_EPDISBLDMSK_MASK          0x2
-#define GC_USB_DOEPMSK_EPDISBLDMSK_SIZE          0x1
-#define GC_USB_DOEPMSK_EPDISBLDMSK_DEFAULT       0x0
-#define GC_USB_DOEPMSK_EPDISBLDMSK_OFFSET        0x814
-#define GC_USB_DOEPMSK_AHBERRMSK_LSB             0x2
-#define GC_USB_DOEPMSK_AHBERRMSK_MASK            0x4
-#define GC_USB_DOEPMSK_AHBERRMSK_SIZE            0x1
-#define GC_USB_DOEPMSK_AHBERRMSK_DEFAULT         0x0
-#define GC_USB_DOEPMSK_AHBERRMSK_OFFSET          0x814
-#define GC_USB_DOEPMSK_SETUPMSK_LSB              0x3
-#define GC_USB_DOEPMSK_SETUPMSK_MASK             0x8
-#define GC_USB_DOEPMSK_SETUPMSK_SIZE             0x1
-#define GC_USB_DOEPMSK_SETUPMSK_DEFAULT          0x0
-#define GC_USB_DOEPMSK_SETUPMSK_OFFSET           0x814
-#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_LSB        0x4
-#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_MASK       0x10
-#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_SIZE       0x1
-#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_DEFAULT    0x0
-#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_OFFSET     0x814
-#define GC_USB_DOEPMSK_STSPHSERCVDMSK_LSB        0x5
-#define GC_USB_DOEPMSK_STSPHSERCVDMSK_MASK       0x20
-#define GC_USB_DOEPMSK_STSPHSERCVDMSK_SIZE       0x1
-#define GC_USB_DOEPMSK_STSPHSERCVDMSK_DEFAULT    0x0
-#define GC_USB_DOEPMSK_STSPHSERCVDMSK_OFFSET     0x814
-#define GC_USB_DOEPMSK_BACK2BACKSETUP_LSB        0x6
-#define GC_USB_DOEPMSK_BACK2BACKSETUP_MASK       0x40
-#define GC_USB_DOEPMSK_BACK2BACKSETUP_SIZE       0x1
-#define GC_USB_DOEPMSK_BACK2BACKSETUP_DEFAULT    0x0
-#define GC_USB_DOEPMSK_BACK2BACKSETUP_OFFSET     0x814
-#define GC_USB_DOEPMSK_OUTPKTERRMSK_LSB          0x8
-#define GC_USB_DOEPMSK_OUTPKTERRMSK_MASK         0x100
-#define GC_USB_DOEPMSK_OUTPKTERRMSK_SIZE         0x1
-#define GC_USB_DOEPMSK_OUTPKTERRMSK_DEFAULT      0x0
-#define GC_USB_DOEPMSK_OUTPKTERRMSK_OFFSET       0x814
-#define GC_USB_DOEPMSK_BNAOUTINTRMSK_LSB         0x9
-#define GC_USB_DOEPMSK_BNAOUTINTRMSK_MASK        0x200
-#define GC_USB_DOEPMSK_BNAOUTINTRMSK_SIZE        0x1
-#define GC_USB_DOEPMSK_BNAOUTINTRMSK_DEFAULT     0x0
-#define GC_USB_DOEPMSK_BNAOUTINTRMSK_OFFSET      0x814
-#define GC_USB_DOEPMSK_BBLEERRMSK_LSB            0xc
-#define GC_USB_DOEPMSK_BBLEERRMSK_MASK           0x1000
-#define GC_USB_DOEPMSK_BBLEERRMSK_SIZE           0x1
-#define GC_USB_DOEPMSK_BBLEERRMSK_DEFAULT        0x0
-#define GC_USB_DOEPMSK_BBLEERRMSK_OFFSET         0x814
-#define GC_USB_DOEPMSK_NAKMSK_LSB                0xd
-#define GC_USB_DOEPMSK_NAKMSK_MASK               0x2000
-#define GC_USB_DOEPMSK_NAKMSK_SIZE               0x1
-#define GC_USB_DOEPMSK_NAKMSK_DEFAULT            0x0
-#define GC_USB_DOEPMSK_NAKMSK_OFFSET             0x814
-#define GC_USB_DOEPMSK_NYETMSK_LSB               0xe
-#define GC_USB_DOEPMSK_NYETMSK_MASK              0x4000
-#define GC_USB_DOEPMSK_NYETMSK_SIZE              0x1
-#define GC_USB_DOEPMSK_NYETMSK_DEFAULT           0x0
-#define GC_USB_DOEPMSK_NYETMSK_OFFSET            0x814
-#define GC_USB_DAINT_INEPINT0_LSB                0x0
-#define GC_USB_DAINT_INEPINT0_MASK               0x1
-#define GC_USB_DAINT_INEPINT0_SIZE               0x1
-#define GC_USB_DAINT_INEPINT0_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT0_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT1_LSB                0x1
-#define GC_USB_DAINT_INEPINT1_MASK               0x2
-#define GC_USB_DAINT_INEPINT1_SIZE               0x1
-#define GC_USB_DAINT_INEPINT1_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT1_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT2_LSB                0x2
-#define GC_USB_DAINT_INEPINT2_MASK               0x4
-#define GC_USB_DAINT_INEPINT2_SIZE               0x1
-#define GC_USB_DAINT_INEPINT2_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT2_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT3_LSB                0x3
-#define GC_USB_DAINT_INEPINT3_MASK               0x8
-#define GC_USB_DAINT_INEPINT3_SIZE               0x1
-#define GC_USB_DAINT_INEPINT3_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT3_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT4_LSB                0x4
-#define GC_USB_DAINT_INEPINT4_MASK               0x10
-#define GC_USB_DAINT_INEPINT4_SIZE               0x1
-#define GC_USB_DAINT_INEPINT4_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT4_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT5_LSB                0x5
-#define GC_USB_DAINT_INEPINT5_MASK               0x20
-#define GC_USB_DAINT_INEPINT5_SIZE               0x1
-#define GC_USB_DAINT_INEPINT5_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT5_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT6_LSB                0x6
-#define GC_USB_DAINT_INEPINT6_MASK               0x40
-#define GC_USB_DAINT_INEPINT6_SIZE               0x1
-#define GC_USB_DAINT_INEPINT6_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT6_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT7_LSB                0x7
-#define GC_USB_DAINT_INEPINT7_MASK               0x80
-#define GC_USB_DAINT_INEPINT7_SIZE               0x1
-#define GC_USB_DAINT_INEPINT7_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT7_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT8_LSB                0x8
-#define GC_USB_DAINT_INEPINT8_MASK               0x100
-#define GC_USB_DAINT_INEPINT8_SIZE               0x1
-#define GC_USB_DAINT_INEPINT8_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT8_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT9_LSB                0x9
-#define GC_USB_DAINT_INEPINT9_MASK               0x200
-#define GC_USB_DAINT_INEPINT9_SIZE               0x1
-#define GC_USB_DAINT_INEPINT9_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT9_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT10_LSB               0xa
-#define GC_USB_DAINT_INEPINT10_MASK              0x400
-#define GC_USB_DAINT_INEPINT10_SIZE              0x1
-#define GC_USB_DAINT_INEPINT10_DEFAULT           0x0
-#define GC_USB_DAINT_INEPINT10_OFFSET            0x818
-#define GC_USB_DAINT_INEPINT11_LSB               0xb
-#define GC_USB_DAINT_INEPINT11_MASK              0x800
-#define GC_USB_DAINT_INEPINT11_SIZE              0x1
-#define GC_USB_DAINT_INEPINT11_DEFAULT           0x0
-#define GC_USB_DAINT_INEPINT11_OFFSET            0x818
-#define GC_USB_DAINT_INEPINT12_LSB               0xc
-#define GC_USB_DAINT_INEPINT12_MASK              0x1000
-#define GC_USB_DAINT_INEPINT12_SIZE              0x1
-#define GC_USB_DAINT_INEPINT12_DEFAULT           0x0
-#define GC_USB_DAINT_INEPINT12_OFFSET            0x818
-#define GC_USB_DAINT_INEPINT13_LSB               0xd
-#define GC_USB_DAINT_INEPINT13_MASK              0x2000
-#define GC_USB_DAINT_INEPINT13_SIZE              0x1
-#define GC_USB_DAINT_INEPINT13_DEFAULT           0x0
-#define GC_USB_DAINT_INEPINT13_OFFSET            0x818
-#define GC_USB_DAINT_INEPINT14_LSB               0xe
-#define GC_USB_DAINT_INEPINT14_MASK              0x4000
-#define GC_USB_DAINT_INEPINT14_SIZE              0x1
-#define GC_USB_DAINT_INEPINT14_DEFAULT           0x0
-#define GC_USB_DAINT_INEPINT14_OFFSET            0x818
-#define GC_USB_DAINT_INEPINT15_LSB               0xf
-#define GC_USB_DAINT_INEPINT15_MASK              0x8000
-#define GC_USB_DAINT_INEPINT15_SIZE              0x1
-#define GC_USB_DAINT_INEPINT15_DEFAULT           0x0
-#define GC_USB_DAINT_INEPINT15_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT0_LSB               0x10
-#define GC_USB_DAINT_OUTEPINT0_MASK              0x10000
-#define GC_USB_DAINT_OUTEPINT0_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT0_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT0_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT1_LSB               0x11
-#define GC_USB_DAINT_OUTEPINT1_MASK              0x20000
-#define GC_USB_DAINT_OUTEPINT1_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT1_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT1_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT2_LSB               0x12
-#define GC_USB_DAINT_OUTEPINT2_MASK              0x40000
-#define GC_USB_DAINT_OUTEPINT2_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT2_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT2_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT3_LSB               0x13
-#define GC_USB_DAINT_OUTEPINT3_MASK              0x80000
-#define GC_USB_DAINT_OUTEPINT3_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT3_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT3_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT4_LSB               0x14
-#define GC_USB_DAINT_OUTEPINT4_MASK              0x100000
-#define GC_USB_DAINT_OUTEPINT4_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT4_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT4_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT5_LSB               0x15
-#define GC_USB_DAINT_OUTEPINT5_MASK              0x200000
-#define GC_USB_DAINT_OUTEPINT5_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT5_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT5_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT6_LSB               0x16
-#define GC_USB_DAINT_OUTEPINT6_MASK              0x400000
-#define GC_USB_DAINT_OUTEPINT6_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT6_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT6_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT7_LSB               0x17
-#define GC_USB_DAINT_OUTEPINT7_MASK              0x800000
-#define GC_USB_DAINT_OUTEPINT7_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT7_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT7_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT8_LSB               0x18
-#define GC_USB_DAINT_OUTEPINT8_MASK              0x1000000
-#define GC_USB_DAINT_OUTEPINT8_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT8_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT8_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT9_LSB               0x19
-#define GC_USB_DAINT_OUTEPINT9_MASK              0x2000000
-#define GC_USB_DAINT_OUTEPINT9_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT9_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT9_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT10_LSB              0x1a
-#define GC_USB_DAINT_OUTEPINT10_MASK             0x4000000
-#define GC_USB_DAINT_OUTEPINT10_SIZE             0x1
-#define GC_USB_DAINT_OUTEPINT10_DEFAULT          0x0
-#define GC_USB_DAINT_OUTEPINT10_OFFSET           0x818
-#define GC_USB_DAINT_OUTEPINT11_LSB              0x1b
-#define GC_USB_DAINT_OUTEPINT11_MASK             0x8000000
-#define GC_USB_DAINT_OUTEPINT11_SIZE             0x1
-#define GC_USB_DAINT_OUTEPINT11_DEFAULT          0x0
-#define GC_USB_DAINT_OUTEPINT11_OFFSET           0x818
-#define GC_USB_DAINT_OUTEPINT12_LSB              0x1c
-#define GC_USB_DAINT_OUTEPINT12_MASK             0x10000000
-#define GC_USB_DAINT_OUTEPINT12_SIZE             0x1
-#define GC_USB_DAINT_OUTEPINT12_DEFAULT          0x0
-#define GC_USB_DAINT_OUTEPINT12_OFFSET           0x818
-#define GC_USB_DAINT_OUTEPINT13_LSB              0x1d
-#define GC_USB_DAINT_OUTEPINT13_MASK             0x20000000
-#define GC_USB_DAINT_OUTEPINT13_SIZE             0x1
-#define GC_USB_DAINT_OUTEPINT13_DEFAULT          0x0
-#define GC_USB_DAINT_OUTEPINT13_OFFSET           0x818
-#define GC_USB_DAINT_OUTEPINT14_LSB              0x1e
-#define GC_USB_DAINT_OUTEPINT14_MASK             0x40000000
-#define GC_USB_DAINT_OUTEPINT14_SIZE             0x1
-#define GC_USB_DAINT_OUTEPINT14_DEFAULT          0x0
-#define GC_USB_DAINT_OUTEPINT14_OFFSET           0x818
-#define GC_USB_DAINT_OUTEPINT15_LSB              0x1f
-#define GC_USB_DAINT_OUTEPINT15_MASK             0x80000000
-#define GC_USB_DAINT_OUTEPINT15_SIZE             0x1
-#define GC_USB_DAINT_OUTEPINT15_DEFAULT          0x0
-#define GC_USB_DAINT_OUTEPINT15_OFFSET           0x818
-#define GC_USB_DAINTMSK_INEPMSK0_LSB             0x0
-#define GC_USB_DAINTMSK_INEPMSK0_MASK            0x1
-#define GC_USB_DAINTMSK_INEPMSK0_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK0_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK0_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK1_LSB             0x1
-#define GC_USB_DAINTMSK_INEPMSK1_MASK            0x2
-#define GC_USB_DAINTMSK_INEPMSK1_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK1_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK1_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK2_LSB             0x2
-#define GC_USB_DAINTMSK_INEPMSK2_MASK            0x4
-#define GC_USB_DAINTMSK_INEPMSK2_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK2_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK2_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK3_LSB             0x3
-#define GC_USB_DAINTMSK_INEPMSK3_MASK            0x8
-#define GC_USB_DAINTMSK_INEPMSK3_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK3_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK3_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK4_LSB             0x4
-#define GC_USB_DAINTMSK_INEPMSK4_MASK            0x10
-#define GC_USB_DAINTMSK_INEPMSK4_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK4_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK4_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK5_LSB             0x5
-#define GC_USB_DAINTMSK_INEPMSK5_MASK            0x20
-#define GC_USB_DAINTMSK_INEPMSK5_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK5_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK5_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK6_LSB             0x6
-#define GC_USB_DAINTMSK_INEPMSK6_MASK            0x40
-#define GC_USB_DAINTMSK_INEPMSK6_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK6_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK6_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK7_LSB             0x7
-#define GC_USB_DAINTMSK_INEPMSK7_MASK            0x80
-#define GC_USB_DAINTMSK_INEPMSK7_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK7_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK7_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK8_LSB             0x8
-#define GC_USB_DAINTMSK_INEPMSK8_MASK            0x100
-#define GC_USB_DAINTMSK_INEPMSK8_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK8_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK8_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK9_LSB             0x9
-#define GC_USB_DAINTMSK_INEPMSK9_MASK            0x200
-#define GC_USB_DAINTMSK_INEPMSK9_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK9_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK9_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK10_LSB            0xa
-#define GC_USB_DAINTMSK_INEPMSK10_MASK           0x400
-#define GC_USB_DAINTMSK_INEPMSK10_SIZE           0x1
-#define GC_USB_DAINTMSK_INEPMSK10_DEFAULT        0x0
-#define GC_USB_DAINTMSK_INEPMSK10_OFFSET         0x81c
-#define GC_USB_DAINTMSK_INEPMSK11_LSB            0xb
-#define GC_USB_DAINTMSK_INEPMSK11_MASK           0x800
-#define GC_USB_DAINTMSK_INEPMSK11_SIZE           0x1
-#define GC_USB_DAINTMSK_INEPMSK11_DEFAULT        0x0
-#define GC_USB_DAINTMSK_INEPMSK11_OFFSET         0x81c
-#define GC_USB_DAINTMSK_INEPMSK12_LSB            0xc
-#define GC_USB_DAINTMSK_INEPMSK12_MASK           0x1000
-#define GC_USB_DAINTMSK_INEPMSK12_SIZE           0x1
-#define GC_USB_DAINTMSK_INEPMSK12_DEFAULT        0x0
-#define GC_USB_DAINTMSK_INEPMSK12_OFFSET         0x81c
-#define GC_USB_DAINTMSK_INEPMSK13_LSB            0xd
-#define GC_USB_DAINTMSK_INEPMSK13_MASK           0x2000
-#define GC_USB_DAINTMSK_INEPMSK13_SIZE           0x1
-#define GC_USB_DAINTMSK_INEPMSK13_DEFAULT        0x0
-#define GC_USB_DAINTMSK_INEPMSK13_OFFSET         0x81c
-#define GC_USB_DAINTMSK_INEPMSK14_LSB            0xe
-#define GC_USB_DAINTMSK_INEPMSK14_MASK           0x4000
-#define GC_USB_DAINTMSK_INEPMSK14_SIZE           0x1
-#define GC_USB_DAINTMSK_INEPMSK14_DEFAULT        0x0
-#define GC_USB_DAINTMSK_INEPMSK14_OFFSET         0x81c
-#define GC_USB_DAINTMSK_INEPMSK15_LSB            0xf
-#define GC_USB_DAINTMSK_INEPMSK15_MASK           0x8000
-#define GC_USB_DAINTMSK_INEPMSK15_SIZE           0x1
-#define GC_USB_DAINTMSK_INEPMSK15_DEFAULT        0x0
-#define GC_USB_DAINTMSK_INEPMSK15_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK0_LSB            0x10
-#define GC_USB_DAINTMSK_OUTEPMSK0_MASK           0x10000
-#define GC_USB_DAINTMSK_OUTEPMSK0_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK0_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK0_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK1_LSB            0x11
-#define GC_USB_DAINTMSK_OUTEPMSK1_MASK           0x20000
-#define GC_USB_DAINTMSK_OUTEPMSK1_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK1_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK1_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK2_LSB            0x12
-#define GC_USB_DAINTMSK_OUTEPMSK2_MASK           0x40000
-#define GC_USB_DAINTMSK_OUTEPMSK2_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK2_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK2_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK3_LSB            0x13
-#define GC_USB_DAINTMSK_OUTEPMSK3_MASK           0x80000
-#define GC_USB_DAINTMSK_OUTEPMSK3_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK3_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK3_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK4_LSB            0x14
-#define GC_USB_DAINTMSK_OUTEPMSK4_MASK           0x100000
-#define GC_USB_DAINTMSK_OUTEPMSK4_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK4_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK4_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK5_LSB            0x15
-#define GC_USB_DAINTMSK_OUTEPMSK5_MASK           0x200000
-#define GC_USB_DAINTMSK_OUTEPMSK5_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK5_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK5_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK6_LSB            0x16
-#define GC_USB_DAINTMSK_OUTEPMSK6_MASK           0x400000
-#define GC_USB_DAINTMSK_OUTEPMSK6_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK6_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK6_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK7_LSB            0x17
-#define GC_USB_DAINTMSK_OUTEPMSK7_MASK           0x800000
-#define GC_USB_DAINTMSK_OUTEPMSK7_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK7_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK7_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK8_LSB            0x18
-#define GC_USB_DAINTMSK_OUTEPMSK8_MASK           0x1000000
-#define GC_USB_DAINTMSK_OUTEPMSK8_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK8_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK8_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK9_LSB            0x19
-#define GC_USB_DAINTMSK_OUTEPMSK9_MASK           0x2000000
-#define GC_USB_DAINTMSK_OUTEPMSK9_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK9_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK9_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK10_LSB           0x1a
-#define GC_USB_DAINTMSK_OUTEPMSK10_MASK          0x4000000
-#define GC_USB_DAINTMSK_OUTEPMSK10_SIZE          0x1
-#define GC_USB_DAINTMSK_OUTEPMSK10_DEFAULT       0x0
-#define GC_USB_DAINTMSK_OUTEPMSK10_OFFSET        0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK11_LSB           0x1b
-#define GC_USB_DAINTMSK_OUTEPMSK11_MASK          0x8000000
-#define GC_USB_DAINTMSK_OUTEPMSK11_SIZE          0x1
-#define GC_USB_DAINTMSK_OUTEPMSK11_DEFAULT       0x0
-#define GC_USB_DAINTMSK_OUTEPMSK11_OFFSET        0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK12_LSB           0x1c
-#define GC_USB_DAINTMSK_OUTEPMSK12_MASK          0x10000000
-#define GC_USB_DAINTMSK_OUTEPMSK12_SIZE          0x1
-#define GC_USB_DAINTMSK_OUTEPMSK12_DEFAULT       0x0
-#define GC_USB_DAINTMSK_OUTEPMSK12_OFFSET        0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK13_LSB           0x1d
-#define GC_USB_DAINTMSK_OUTEPMSK13_MASK          0x20000000
-#define GC_USB_DAINTMSK_OUTEPMSK13_SIZE          0x1
-#define GC_USB_DAINTMSK_OUTEPMSK13_DEFAULT       0x0
-#define GC_USB_DAINTMSK_OUTEPMSK13_OFFSET        0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK14_LSB           0x1e
-#define GC_USB_DAINTMSK_OUTEPMSK14_MASK          0x40000000
-#define GC_USB_DAINTMSK_OUTEPMSK14_SIZE          0x1
-#define GC_USB_DAINTMSK_OUTEPMSK14_DEFAULT       0x0
-#define GC_USB_DAINTMSK_OUTEPMSK14_OFFSET        0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK15_LSB           0x1f
-#define GC_USB_DAINTMSK_OUTEPMSK15_MASK          0x80000000
-#define GC_USB_DAINTMSK_OUTEPMSK15_SIZE          0x1
-#define GC_USB_DAINTMSK_OUTEPMSK15_DEFAULT       0x0
-#define GC_USB_DAINTMSK_OUTEPMSK15_OFFSET        0x81c
-#define GC_USB_DVBUSDIS_DVBUSDIS_LSB             0x0
-#define GC_USB_DVBUSDIS_DVBUSDIS_MASK            0xffff
-#define GC_USB_DVBUSDIS_DVBUSDIS_SIZE            0x10
-#define GC_USB_DVBUSDIS_DVBUSDIS_DEFAULT         0x0
-#define GC_USB_DVBUSDIS_DVBUSDIS_OFFSET          0x828
-#define GC_USB_DVBUSPULSE_DVBUSPULSE_LSB         0x0
-#define GC_USB_DVBUSPULSE_DVBUSPULSE_MASK        0xfff
-#define GC_USB_DVBUSPULSE_DVBUSPULSE_SIZE        0xc
-#define GC_USB_DVBUSPULSE_DVBUSPULSE_DEFAULT     0x0
-#define GC_USB_DVBUSPULSE_DVBUSPULSE_OFFSET      0x82c
-#define GC_USB_DTHRCTL_NONISOTHREN_LSB           0x0
-#define GC_USB_DTHRCTL_NONISOTHREN_MASK          0x1
-#define GC_USB_DTHRCTL_NONISOTHREN_SIZE          0x1
-#define GC_USB_DTHRCTL_NONISOTHREN_DEFAULT       0x0
-#define GC_USB_DTHRCTL_NONISOTHREN_OFFSET        0x830
-#define GC_USB_DTHRCTL_ISOTHREN_LSB              0x1
-#define GC_USB_DTHRCTL_ISOTHREN_MASK             0x2
-#define GC_USB_DTHRCTL_ISOTHREN_SIZE             0x1
-#define GC_USB_DTHRCTL_ISOTHREN_DEFAULT          0x0
-#define GC_USB_DTHRCTL_ISOTHREN_OFFSET           0x830
-#define GC_USB_DTHRCTL_TXTHRLEN_LSB              0x2
-#define GC_USB_DTHRCTL_TXTHRLEN_MASK             0x7fc
-#define GC_USB_DTHRCTL_TXTHRLEN_SIZE             0x9
-#define GC_USB_DTHRCTL_TXTHRLEN_DEFAULT          0x0
-#define GC_USB_DTHRCTL_TXTHRLEN_OFFSET           0x830
-#define GC_USB_DTHRCTL_AHBTHRRATIO_LSB           0xb
-#define GC_USB_DTHRCTL_AHBTHRRATIO_MASK          0x1800
-#define GC_USB_DTHRCTL_AHBTHRRATIO_SIZE          0x2
-#define GC_USB_DTHRCTL_AHBTHRRATIO_DEFAULT       0x0
-#define GC_USB_DTHRCTL_AHBTHRRATIO_OFFSET        0x830
-#define GC_USB_DTHRCTL_RXTHREN_LSB               0x10
-#define GC_USB_DTHRCTL_RXTHREN_MASK              0x10000
-#define GC_USB_DTHRCTL_RXTHREN_SIZE              0x1
-#define GC_USB_DTHRCTL_RXTHREN_DEFAULT           0x0
-#define GC_USB_DTHRCTL_RXTHREN_OFFSET            0x830
-#define GC_USB_DTHRCTL_RXTHRLEN_LSB              0x11
-#define GC_USB_DTHRCTL_RXTHRLEN_MASK             0x3fe0000
-#define GC_USB_DTHRCTL_RXTHRLEN_SIZE             0x9
-#define GC_USB_DTHRCTL_RXTHRLEN_DEFAULT          0x0
-#define GC_USB_DTHRCTL_RXTHRLEN_OFFSET           0x830
-#define GC_USB_DTHRCTL_ARBPRKEN_LSB              0x1b
-#define GC_USB_DTHRCTL_ARBPRKEN_MASK             0x8000000
-#define GC_USB_DTHRCTL_ARBPRKEN_SIZE             0x1
-#define GC_USB_DTHRCTL_ARBPRKEN_DEFAULT          0x0
-#define GC_USB_DTHRCTL_ARBPRKEN_OFFSET           0x830
-#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_LSB      0x0
-#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_MASK     0xffff
-#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_SIZE     0x10
-#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_DEFAULT  0x0
-#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_OFFSET   0x834
-#define GC_USB_DIEPCTL0_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL0_MPS_MASK                 0x3
-#define GC_USB_DIEPCTL0_MPS_SIZE                 0x2
-#define GC_USB_DIEPCTL0_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL0_MPS_OFFSET               0x900
-#define GC_USB_DIEPCTL0_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL0_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL0_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL0_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL0_USBACTEP_OFFSET          0x900
-#define GC_USB_DIEPCTL0_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL0_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL0_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL0_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL0_NAKSTS_OFFSET            0x900
-#define GC_USB_DIEPCTL0_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL0_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL0_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL0_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL0_EPTYPE_OFFSET            0x900
-#define GC_USB_DIEPCTL0_STALL_LSB                0x15
-#define GC_USB_DIEPCTL0_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL0_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL0_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL0_STALL_OFFSET             0x900
-#define GC_USB_DIEPCTL0_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL0_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL0_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL0_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL0_TXFNUM_OFFSET            0x900
-#define GC_USB_DIEPCTL0_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL0_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL0_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL0_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL0_CNAK_OFFSET              0x900
-#define GC_USB_DIEPCTL0_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL0_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL0_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL0_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL0_SNAK_OFFSET              0x900
-#define GC_USB_DIEPCTL0_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL0_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL0_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL0_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL0_EPDIS_OFFSET             0x900
-#define GC_USB_DIEPCTL0_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL0_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL0_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL0_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL0_EPENA_OFFSET             0x900
-#define GC_USB_DIEPINT0_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT0_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT0_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT0_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT0_XFERCOMPL_OFFSET         0x908
-#define GC_USB_DIEPINT0_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT0_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT0_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT0_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT0_EPDISBLD_OFFSET          0x908
-#define GC_USB_DIEPINT0_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT0_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT0_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT0_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT0_AHBERR_OFFSET            0x908
-#define GC_USB_DIEPINT0_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT0_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT0_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT0_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT0_TIMEOUT_OFFSET           0x908
-#define GC_USB_DIEPINT0_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT0_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT0_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT0_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT0_INTKNTXFEMP_OFFSET       0x908
-#define GC_USB_DIEPINT0_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT0_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT0_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT0_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT0_INTKNEPMIS_OFFSET        0x908
-#define GC_USB_DIEPINT0_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT0_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT0_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT0_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT0_INEPNAKEFF_OFFSET        0x908
-#define GC_USB_DIEPINT0_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT0_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT0_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT0_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT0_TXFEMP_OFFSET            0x908
-#define GC_USB_DIEPINT0_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT0_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT0_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT0_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT0_TXFIFOUNDRN_OFFSET       0x908
-#define GC_USB_DIEPINT0_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT0_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT0_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT0_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT0_BNAINTR_OFFSET           0x908
-#define GC_USB_DIEPINT0_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT0_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT0_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT0_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT0_PKTDRPSTS_OFFSET         0x908
-#define GC_USB_DIEPINT0_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT0_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT0_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT0_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT0_BBLEERR_OFFSET           0x908
-#define GC_USB_DIEPINT0_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT0_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT0_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT0_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT0_NAKINTRPT_OFFSET         0x908
-#define GC_USB_DIEPINT0_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT0_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT0_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT0_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT0_NYETINTRPT_OFFSET        0x908
-#define GC_USB_DIEPTSIZ0_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ0_XFERSIZE_MASK           0x7f
-#define GC_USB_DIEPTSIZ0_XFERSIZE_SIZE           0x7
-#define GC_USB_DIEPTSIZ0_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ0_XFERSIZE_OFFSET         0x910
-#define GC_USB_DIEPTSIZ0_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ0_PKTCNT_MASK             0x180000
-#define GC_USB_DIEPTSIZ0_PKTCNT_SIZE             0x2
-#define GC_USB_DIEPTSIZ0_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ0_PKTCNT_OFFSET           0x910
-#define GC_USB_DIEPDMA0_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA0_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA0_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA0_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA0_DMAADDR_OFFSET           0x914
-#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_OFFSET   0x918
-#define GC_USB_DIEPDMAB0_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB0_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB0_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB0_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB0_DMABUFFERADDR_OFFSET    0x91c
-#define GC_USB_DIEPCTL1_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL1_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL1_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL1_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL1_MPS_OFFSET               0x920
-#define GC_USB_DIEPCTL1_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL1_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL1_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL1_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL1_USBACTEP_OFFSET          0x920
-#define GC_USB_DIEPCTL1_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL1_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL1_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL1_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL1_DPID_OFFSET              0x920
-#define GC_USB_DIEPCTL1_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL1_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL1_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL1_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL1_NAKSTS_OFFSET            0x920
-#define GC_USB_DIEPCTL1_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL1_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL1_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL1_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL1_EPTYPE_OFFSET            0x920
-#define GC_USB_DIEPCTL1_STALL_LSB                0x15
-#define GC_USB_DIEPCTL1_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL1_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL1_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL1_STALL_OFFSET             0x920
-#define GC_USB_DIEPCTL1_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL1_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL1_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL1_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL1_TXFNUM_OFFSET            0x920
-#define GC_USB_DIEPCTL1_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL1_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL1_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL1_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL1_CNAK_OFFSET              0x920
-#define GC_USB_DIEPCTL1_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL1_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL1_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL1_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL1_SNAK_OFFSET              0x920
-#define GC_USB_DIEPCTL1_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL1_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL1_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL1_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL1_SETD0PID_OFFSET          0x920
-#define GC_USB_DIEPCTL1_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL1_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL1_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL1_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL1_SETD1PID_OFFSET          0x920
-#define GC_USB_DIEPCTL1_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL1_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL1_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL1_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL1_EPDIS_OFFSET             0x920
-#define GC_USB_DIEPCTL1_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL1_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL1_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL1_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL1_EPENA_OFFSET             0x920
-#define GC_USB_DIEPINT1_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT1_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT1_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT1_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT1_XFERCOMPL_OFFSET         0x928
-#define GC_USB_DIEPINT1_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT1_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT1_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT1_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT1_EPDISBLD_OFFSET          0x928
-#define GC_USB_DIEPINT1_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT1_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT1_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT1_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT1_AHBERR_OFFSET            0x928
-#define GC_USB_DIEPINT1_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT1_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT1_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT1_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT1_TIMEOUT_OFFSET           0x928
-#define GC_USB_DIEPINT1_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT1_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT1_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT1_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT1_INTKNTXFEMP_OFFSET       0x928
-#define GC_USB_DIEPINT1_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT1_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT1_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT1_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT1_INTKNEPMIS_OFFSET        0x928
-#define GC_USB_DIEPINT1_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT1_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT1_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT1_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT1_INEPNAKEFF_OFFSET        0x928
-#define GC_USB_DIEPINT1_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT1_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT1_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT1_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT1_TXFEMP_OFFSET            0x928
-#define GC_USB_DIEPINT1_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT1_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT1_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT1_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT1_TXFIFOUNDRN_OFFSET       0x928
-#define GC_USB_DIEPINT1_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT1_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT1_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT1_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT1_BNAINTR_OFFSET           0x928
-#define GC_USB_DIEPINT1_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT1_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT1_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT1_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT1_PKTDRPSTS_OFFSET         0x928
-#define GC_USB_DIEPINT1_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT1_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT1_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT1_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT1_BBLEERR_OFFSET           0x928
-#define GC_USB_DIEPINT1_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT1_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT1_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT1_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT1_NAKINTRPT_OFFSET         0x928
-#define GC_USB_DIEPINT1_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT1_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT1_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT1_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT1_NYETINTRPT_OFFSET        0x928
-#define GC_USB_DIEPTSIZ1_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ1_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ1_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ1_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ1_XFERSIZE_OFFSET         0x930
-#define GC_USB_DIEPTSIZ1_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ1_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ1_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ1_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ1_PKTCNT_OFFSET           0x930
-#define GC_USB_DIEPTSIZ1_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ1_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ1_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ1_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ1_MC_OFFSET               0x930
-#define GC_USB_DIEPDMA1_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA1_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA1_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA1_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA1_DMAADDR_OFFSET           0x934
-#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_OFFSET   0x938
-#define GC_USB_DIEPDMAB1_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB1_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB1_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB1_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB1_DMABUFFERADDR_OFFSET    0x93c
-#define GC_USB_DIEPCTL2_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL2_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL2_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL2_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL2_MPS_OFFSET               0x940
-#define GC_USB_DIEPCTL2_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL2_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL2_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL2_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL2_USBACTEP_OFFSET          0x940
-#define GC_USB_DIEPCTL2_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL2_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL2_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL2_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL2_DPID_OFFSET              0x940
-#define GC_USB_DIEPCTL2_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL2_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL2_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL2_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL2_NAKSTS_OFFSET            0x940
-#define GC_USB_DIEPCTL2_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL2_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL2_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL2_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL2_EPTYPE_OFFSET            0x940
-#define GC_USB_DIEPCTL2_STALL_LSB                0x15
-#define GC_USB_DIEPCTL2_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL2_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL2_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL2_STALL_OFFSET             0x940
-#define GC_USB_DIEPCTL2_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL2_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL2_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL2_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL2_TXFNUM_OFFSET            0x940
-#define GC_USB_DIEPCTL2_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL2_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL2_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL2_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL2_CNAK_OFFSET              0x940
-#define GC_USB_DIEPCTL2_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL2_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL2_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL2_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL2_SNAK_OFFSET              0x940
-#define GC_USB_DIEPCTL2_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL2_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL2_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL2_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL2_SETD0PID_OFFSET          0x940
-#define GC_USB_DIEPCTL2_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL2_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL2_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL2_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL2_SETD1PID_OFFSET          0x940
-#define GC_USB_DIEPCTL2_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL2_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL2_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL2_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL2_EPDIS_OFFSET             0x940
-#define GC_USB_DIEPCTL2_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL2_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL2_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL2_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL2_EPENA_OFFSET             0x940
-#define GC_USB_DIEPINT2_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT2_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT2_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT2_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT2_XFERCOMPL_OFFSET         0x948
-#define GC_USB_DIEPINT2_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT2_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT2_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT2_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT2_EPDISBLD_OFFSET          0x948
-#define GC_USB_DIEPINT2_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT2_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT2_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT2_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT2_AHBERR_OFFSET            0x948
-#define GC_USB_DIEPINT2_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT2_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT2_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT2_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT2_TIMEOUT_OFFSET           0x948
-#define GC_USB_DIEPINT2_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT2_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT2_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT2_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT2_INTKNTXFEMP_OFFSET       0x948
-#define GC_USB_DIEPINT2_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT2_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT2_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT2_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT2_INTKNEPMIS_OFFSET        0x948
-#define GC_USB_DIEPINT2_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT2_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT2_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT2_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT2_INEPNAKEFF_OFFSET        0x948
-#define GC_USB_DIEPINT2_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT2_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT2_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT2_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT2_TXFEMP_OFFSET            0x948
-#define GC_USB_DIEPINT2_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT2_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT2_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT2_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT2_TXFIFOUNDRN_OFFSET       0x948
-#define GC_USB_DIEPINT2_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT2_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT2_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT2_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT2_BNAINTR_OFFSET           0x948
-#define GC_USB_DIEPINT2_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT2_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT2_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT2_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT2_PKTDRPSTS_OFFSET         0x948
-#define GC_USB_DIEPINT2_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT2_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT2_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT2_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT2_BBLEERR_OFFSET           0x948
-#define GC_USB_DIEPINT2_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT2_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT2_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT2_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT2_NAKINTRPT_OFFSET         0x948
-#define GC_USB_DIEPINT2_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT2_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT2_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT2_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT2_NYETINTRPT_OFFSET        0x948
-#define GC_USB_DIEPTSIZ2_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ2_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ2_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ2_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ2_XFERSIZE_OFFSET         0x950
-#define GC_USB_DIEPTSIZ2_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ2_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ2_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ2_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ2_PKTCNT_OFFSET           0x950
-#define GC_USB_DIEPTSIZ2_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ2_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ2_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ2_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ2_MC_OFFSET               0x950
-#define GC_USB_DIEPDMA2_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA2_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA2_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA2_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA2_DMAADDR_OFFSET           0x954
-#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_OFFSET   0x958
-#define GC_USB_DIEPDMAB2_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB2_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB2_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB2_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB2_DMABUFFERADDR_OFFSET    0x95c
-#define GC_USB_DIEPCTL3_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL3_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL3_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL3_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL3_MPS_OFFSET               0x960
-#define GC_USB_DIEPCTL3_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL3_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL3_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL3_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL3_USBACTEP_OFFSET          0x960
-#define GC_USB_DIEPCTL3_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL3_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL3_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL3_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL3_DPID_OFFSET              0x960
-#define GC_USB_DIEPCTL3_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL3_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL3_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL3_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL3_NAKSTS_OFFSET            0x960
-#define GC_USB_DIEPCTL3_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL3_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL3_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL3_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL3_EPTYPE_OFFSET            0x960
-#define GC_USB_DIEPCTL3_STALL_LSB                0x15
-#define GC_USB_DIEPCTL3_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL3_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL3_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL3_STALL_OFFSET             0x960
-#define GC_USB_DIEPCTL3_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL3_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL3_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL3_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL3_TXFNUM_OFFSET            0x960
-#define GC_USB_DIEPCTL3_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL3_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL3_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL3_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL3_CNAK_OFFSET              0x960
-#define GC_USB_DIEPCTL3_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL3_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL3_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL3_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL3_SNAK_OFFSET              0x960
-#define GC_USB_DIEPCTL3_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL3_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL3_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL3_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL3_SETD0PID_OFFSET          0x960
-#define GC_USB_DIEPCTL3_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL3_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL3_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL3_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL3_SETD1PID_OFFSET          0x960
-#define GC_USB_DIEPCTL3_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL3_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL3_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL3_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL3_EPDIS_OFFSET             0x960
-#define GC_USB_DIEPCTL3_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL3_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL3_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL3_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL3_EPENA_OFFSET             0x960
-#define GC_USB_DIEPINT3_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT3_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT3_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT3_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT3_XFERCOMPL_OFFSET         0x968
-#define GC_USB_DIEPINT3_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT3_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT3_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT3_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT3_EPDISBLD_OFFSET          0x968
-#define GC_USB_DIEPINT3_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT3_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT3_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT3_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT3_AHBERR_OFFSET            0x968
-#define GC_USB_DIEPINT3_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT3_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT3_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT3_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT3_TIMEOUT_OFFSET           0x968
-#define GC_USB_DIEPINT3_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT3_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT3_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT3_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT3_INTKNTXFEMP_OFFSET       0x968
-#define GC_USB_DIEPINT3_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT3_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT3_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT3_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT3_INTKNEPMIS_OFFSET        0x968
-#define GC_USB_DIEPINT3_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT3_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT3_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT3_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT3_INEPNAKEFF_OFFSET        0x968
-#define GC_USB_DIEPINT3_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT3_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT3_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT3_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT3_TXFEMP_OFFSET            0x968
-#define GC_USB_DIEPINT3_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT3_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT3_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT3_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT3_TXFIFOUNDRN_OFFSET       0x968
-#define GC_USB_DIEPINT3_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT3_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT3_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT3_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT3_BNAINTR_OFFSET           0x968
-#define GC_USB_DIEPINT3_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT3_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT3_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT3_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT3_PKTDRPSTS_OFFSET         0x968
-#define GC_USB_DIEPINT3_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT3_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT3_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT3_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT3_BBLEERR_OFFSET           0x968
-#define GC_USB_DIEPINT3_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT3_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT3_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT3_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT3_NAKINTRPT_OFFSET         0x968
-#define GC_USB_DIEPINT3_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT3_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT3_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT3_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT3_NYETINTRPT_OFFSET        0x968
-#define GC_USB_DIEPTSIZ3_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ3_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ3_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ3_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ3_XFERSIZE_OFFSET         0x970
-#define GC_USB_DIEPTSIZ3_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ3_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ3_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ3_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ3_PKTCNT_OFFSET           0x970
-#define GC_USB_DIEPTSIZ3_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ3_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ3_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ3_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ3_MC_OFFSET               0x970
-#define GC_USB_DIEPDMA3_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA3_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA3_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA3_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA3_DMAADDR_OFFSET           0x974
-#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_OFFSET   0x978
-#define GC_USB_DIEPDMAB3_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB3_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB3_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB3_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB3_DMABUFFERADDR_OFFSET    0x97c
-#define GC_USB_DIEPCTL4_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL4_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL4_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL4_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL4_MPS_OFFSET               0x980
-#define GC_USB_DIEPCTL4_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL4_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL4_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL4_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL4_USBACTEP_OFFSET          0x980
-#define GC_USB_DIEPCTL4_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL4_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL4_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL4_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL4_DPID_OFFSET              0x980
-#define GC_USB_DIEPCTL4_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL4_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL4_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL4_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL4_NAKSTS_OFFSET            0x980
-#define GC_USB_DIEPCTL4_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL4_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL4_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL4_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL4_EPTYPE_OFFSET            0x980
-#define GC_USB_DIEPCTL4_STALL_LSB                0x15
-#define GC_USB_DIEPCTL4_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL4_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL4_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL4_STALL_OFFSET             0x980
-#define GC_USB_DIEPCTL4_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL4_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL4_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL4_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL4_TXFNUM_OFFSET            0x980
-#define GC_USB_DIEPCTL4_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL4_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL4_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL4_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL4_CNAK_OFFSET              0x980
-#define GC_USB_DIEPCTL4_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL4_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL4_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL4_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL4_SNAK_OFFSET              0x980
-#define GC_USB_DIEPCTL4_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL4_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL4_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL4_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL4_SETD0PID_OFFSET          0x980
-#define GC_USB_DIEPCTL4_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL4_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL4_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL4_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL4_SETD1PID_OFFSET          0x980
-#define GC_USB_DIEPCTL4_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL4_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL4_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL4_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL4_EPDIS_OFFSET             0x980
-#define GC_USB_DIEPCTL4_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL4_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL4_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL4_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL4_EPENA_OFFSET             0x980
-#define GC_USB_DIEPINT4_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT4_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT4_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT4_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT4_XFERCOMPL_OFFSET         0x988
-#define GC_USB_DIEPINT4_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT4_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT4_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT4_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT4_EPDISBLD_OFFSET          0x988
-#define GC_USB_DIEPINT4_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT4_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT4_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT4_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT4_AHBERR_OFFSET            0x988
-#define GC_USB_DIEPINT4_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT4_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT4_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT4_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT4_TIMEOUT_OFFSET           0x988
-#define GC_USB_DIEPINT4_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT4_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT4_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT4_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT4_INTKNTXFEMP_OFFSET       0x988
-#define GC_USB_DIEPINT4_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT4_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT4_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT4_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT4_INTKNEPMIS_OFFSET        0x988
-#define GC_USB_DIEPINT4_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT4_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT4_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT4_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT4_INEPNAKEFF_OFFSET        0x988
-#define GC_USB_DIEPINT4_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT4_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT4_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT4_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT4_TXFEMP_OFFSET            0x988
-#define GC_USB_DIEPINT4_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT4_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT4_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT4_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT4_TXFIFOUNDRN_OFFSET       0x988
-#define GC_USB_DIEPINT4_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT4_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT4_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT4_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT4_BNAINTR_OFFSET           0x988
-#define GC_USB_DIEPINT4_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT4_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT4_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT4_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT4_PKTDRPSTS_OFFSET         0x988
-#define GC_USB_DIEPINT4_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT4_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT4_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT4_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT4_BBLEERR_OFFSET           0x988
-#define GC_USB_DIEPINT4_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT4_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT4_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT4_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT4_NAKINTRPT_OFFSET         0x988
-#define GC_USB_DIEPINT4_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT4_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT4_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT4_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT4_NYETINTRPT_OFFSET        0x988
-#define GC_USB_DIEPTSIZ4_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ4_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ4_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ4_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ4_XFERSIZE_OFFSET         0x990
-#define GC_USB_DIEPTSIZ4_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ4_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ4_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ4_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ4_PKTCNT_OFFSET           0x990
-#define GC_USB_DIEPTSIZ4_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ4_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ4_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ4_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ4_MC_OFFSET               0x990
-#define GC_USB_DIEPDMA4_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA4_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA4_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA4_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA4_DMAADDR_OFFSET           0x994
-#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_OFFSET   0x998
-#define GC_USB_DIEPDMAB4_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB4_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB4_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB4_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB4_DMABUFFERADDR_OFFSET    0x99c
-#define GC_USB_DIEPCTL5_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL5_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL5_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL5_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL5_MPS_OFFSET               0x9a0
-#define GC_USB_DIEPCTL5_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL5_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL5_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL5_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL5_USBACTEP_OFFSET          0x9a0
-#define GC_USB_DIEPCTL5_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL5_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL5_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL5_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL5_DPID_OFFSET              0x9a0
-#define GC_USB_DIEPCTL5_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL5_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL5_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL5_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL5_NAKSTS_OFFSET            0x9a0
-#define GC_USB_DIEPCTL5_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL5_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL5_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL5_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL5_EPTYPE_OFFSET            0x9a0
-#define GC_USB_DIEPCTL5_STALL_LSB                0x15
-#define GC_USB_DIEPCTL5_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL5_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL5_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL5_STALL_OFFSET             0x9a0
-#define GC_USB_DIEPCTL5_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL5_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL5_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL5_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL5_TXFNUM_OFFSET            0x9a0
-#define GC_USB_DIEPCTL5_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL5_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL5_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL5_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL5_CNAK_OFFSET              0x9a0
-#define GC_USB_DIEPCTL5_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL5_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL5_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL5_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL5_SNAK_OFFSET              0x9a0
-#define GC_USB_DIEPCTL5_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL5_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL5_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL5_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL5_SETD0PID_OFFSET          0x9a0
-#define GC_USB_DIEPCTL5_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL5_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL5_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL5_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL5_SETD1PID_OFFSET          0x9a0
-#define GC_USB_DIEPCTL5_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL5_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL5_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL5_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL5_EPDIS_OFFSET             0x9a0
-#define GC_USB_DIEPCTL5_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL5_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL5_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL5_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL5_EPENA_OFFSET             0x9a0
-#define GC_USB_DIEPINT5_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT5_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT5_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT5_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT5_XFERCOMPL_OFFSET         0x9a8
-#define GC_USB_DIEPINT5_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT5_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT5_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT5_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT5_EPDISBLD_OFFSET          0x9a8
-#define GC_USB_DIEPINT5_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT5_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT5_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT5_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT5_AHBERR_OFFSET            0x9a8
-#define GC_USB_DIEPINT5_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT5_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT5_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT5_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT5_TIMEOUT_OFFSET           0x9a8
-#define GC_USB_DIEPINT5_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT5_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT5_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT5_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT5_INTKNTXFEMP_OFFSET       0x9a8
-#define GC_USB_DIEPINT5_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT5_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT5_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT5_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT5_INTKNEPMIS_OFFSET        0x9a8
-#define GC_USB_DIEPINT5_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT5_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT5_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT5_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT5_INEPNAKEFF_OFFSET        0x9a8
-#define GC_USB_DIEPINT5_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT5_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT5_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT5_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT5_TXFEMP_OFFSET            0x9a8
-#define GC_USB_DIEPINT5_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT5_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT5_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT5_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT5_TXFIFOUNDRN_OFFSET       0x9a8
-#define GC_USB_DIEPINT5_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT5_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT5_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT5_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT5_BNAINTR_OFFSET           0x9a8
-#define GC_USB_DIEPINT5_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT5_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT5_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT5_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT5_PKTDRPSTS_OFFSET         0x9a8
-#define GC_USB_DIEPINT5_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT5_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT5_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT5_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT5_BBLEERR_OFFSET           0x9a8
-#define GC_USB_DIEPINT5_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT5_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT5_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT5_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT5_NAKINTRPT_OFFSET         0x9a8
-#define GC_USB_DIEPINT5_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT5_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT5_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT5_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT5_NYETINTRPT_OFFSET        0x9a8
-#define GC_USB_DIEPTSIZ5_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ5_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ5_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ5_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ5_XFERSIZE_OFFSET         0x9b0
-#define GC_USB_DIEPTSIZ5_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ5_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ5_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ5_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ5_PKTCNT_OFFSET           0x9b0
-#define GC_USB_DIEPTSIZ5_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ5_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ5_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ5_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ5_MC_OFFSET               0x9b0
-#define GC_USB_DIEPDMA5_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA5_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA5_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA5_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA5_DMAADDR_OFFSET           0x9b4
-#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_OFFSET   0x9b8
-#define GC_USB_DIEPDMAB5_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB5_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB5_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB5_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB5_DMABUFFERADDR_OFFSET    0x9bc
-#define GC_USB_DIEPCTL6_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL6_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL6_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL6_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL6_MPS_OFFSET               0x9c0
-#define GC_USB_DIEPCTL6_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL6_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL6_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL6_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL6_USBACTEP_OFFSET          0x9c0
-#define GC_USB_DIEPCTL6_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL6_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL6_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL6_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL6_DPID_OFFSET              0x9c0
-#define GC_USB_DIEPCTL6_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL6_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL6_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL6_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL6_NAKSTS_OFFSET            0x9c0
-#define GC_USB_DIEPCTL6_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL6_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL6_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL6_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL6_EPTYPE_OFFSET            0x9c0
-#define GC_USB_DIEPCTL6_STALL_LSB                0x15
-#define GC_USB_DIEPCTL6_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL6_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL6_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL6_STALL_OFFSET             0x9c0
-#define GC_USB_DIEPCTL6_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL6_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL6_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL6_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL6_TXFNUM_OFFSET            0x9c0
-#define GC_USB_DIEPCTL6_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL6_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL6_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL6_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL6_CNAK_OFFSET              0x9c0
-#define GC_USB_DIEPCTL6_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL6_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL6_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL6_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL6_SNAK_OFFSET              0x9c0
-#define GC_USB_DIEPCTL6_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL6_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL6_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL6_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL6_SETD0PID_OFFSET          0x9c0
-#define GC_USB_DIEPCTL6_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL6_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL6_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL6_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL6_SETD1PID_OFFSET          0x9c0
-#define GC_USB_DIEPCTL6_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL6_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL6_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL6_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL6_EPDIS_OFFSET             0x9c0
-#define GC_USB_DIEPCTL6_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL6_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL6_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL6_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL6_EPENA_OFFSET             0x9c0
-#define GC_USB_DIEPINT6_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT6_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT6_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT6_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT6_XFERCOMPL_OFFSET         0x9c8
-#define GC_USB_DIEPINT6_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT6_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT6_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT6_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT6_EPDISBLD_OFFSET          0x9c8
-#define GC_USB_DIEPINT6_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT6_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT6_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT6_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT6_AHBERR_OFFSET            0x9c8
-#define GC_USB_DIEPINT6_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT6_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT6_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT6_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT6_TIMEOUT_OFFSET           0x9c8
-#define GC_USB_DIEPINT6_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT6_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT6_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT6_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT6_INTKNTXFEMP_OFFSET       0x9c8
-#define GC_USB_DIEPINT6_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT6_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT6_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT6_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT6_INTKNEPMIS_OFFSET        0x9c8
-#define GC_USB_DIEPINT6_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT6_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT6_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT6_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT6_INEPNAKEFF_OFFSET        0x9c8
-#define GC_USB_DIEPINT6_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT6_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT6_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT6_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT6_TXFEMP_OFFSET            0x9c8
-#define GC_USB_DIEPINT6_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT6_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT6_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT6_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT6_TXFIFOUNDRN_OFFSET       0x9c8
-#define GC_USB_DIEPINT6_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT6_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT6_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT6_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT6_BNAINTR_OFFSET           0x9c8
-#define GC_USB_DIEPINT6_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT6_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT6_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT6_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT6_PKTDRPSTS_OFFSET         0x9c8
-#define GC_USB_DIEPINT6_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT6_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT6_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT6_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT6_BBLEERR_OFFSET           0x9c8
-#define GC_USB_DIEPINT6_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT6_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT6_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT6_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT6_NAKINTRPT_OFFSET         0x9c8
-#define GC_USB_DIEPINT6_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT6_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT6_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT6_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT6_NYETINTRPT_OFFSET        0x9c8
-#define GC_USB_DIEPTSIZ6_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ6_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ6_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ6_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ6_XFERSIZE_OFFSET         0x9d0
-#define GC_USB_DIEPTSIZ6_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ6_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ6_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ6_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ6_PKTCNT_OFFSET           0x9d0
-#define GC_USB_DIEPTSIZ6_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ6_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ6_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ6_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ6_MC_OFFSET               0x9d0
-#define GC_USB_DIEPDMA6_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA6_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA6_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA6_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA6_DMAADDR_OFFSET           0x9d4
-#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_OFFSET   0x9d8
-#define GC_USB_DIEPDMAB6_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB6_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB6_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB6_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB6_DMABUFFERADDR_OFFSET    0x9dc
-#define GC_USB_DIEPCTL7_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL7_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL7_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL7_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL7_MPS_OFFSET               0x9e0
-#define GC_USB_DIEPCTL7_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL7_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL7_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL7_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL7_USBACTEP_OFFSET          0x9e0
-#define GC_USB_DIEPCTL7_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL7_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL7_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL7_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL7_DPID_OFFSET              0x9e0
-#define GC_USB_DIEPCTL7_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL7_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL7_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL7_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL7_NAKSTS_OFFSET            0x9e0
-#define GC_USB_DIEPCTL7_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL7_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL7_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL7_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL7_EPTYPE_OFFSET            0x9e0
-#define GC_USB_DIEPCTL7_STALL_LSB                0x15
-#define GC_USB_DIEPCTL7_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL7_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL7_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL7_STALL_OFFSET             0x9e0
-#define GC_USB_DIEPCTL7_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL7_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL7_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL7_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL7_TXFNUM_OFFSET            0x9e0
-#define GC_USB_DIEPCTL7_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL7_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL7_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL7_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL7_CNAK_OFFSET              0x9e0
-#define GC_USB_DIEPCTL7_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL7_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL7_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL7_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL7_SNAK_OFFSET              0x9e0
-#define GC_USB_DIEPCTL7_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL7_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL7_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL7_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL7_SETD0PID_OFFSET          0x9e0
-#define GC_USB_DIEPCTL7_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL7_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL7_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL7_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL7_SETD1PID_OFFSET          0x9e0
-#define GC_USB_DIEPCTL7_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL7_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL7_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL7_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL7_EPDIS_OFFSET             0x9e0
-#define GC_USB_DIEPCTL7_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL7_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL7_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL7_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL7_EPENA_OFFSET             0x9e0
-#define GC_USB_DIEPINT7_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT7_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT7_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT7_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT7_XFERCOMPL_OFFSET         0x9e8
-#define GC_USB_DIEPINT7_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT7_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT7_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT7_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT7_EPDISBLD_OFFSET          0x9e8
-#define GC_USB_DIEPINT7_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT7_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT7_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT7_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT7_AHBERR_OFFSET            0x9e8
-#define GC_USB_DIEPINT7_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT7_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT7_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT7_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT7_TIMEOUT_OFFSET           0x9e8
-#define GC_USB_DIEPINT7_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT7_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT7_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT7_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT7_INTKNTXFEMP_OFFSET       0x9e8
-#define GC_USB_DIEPINT7_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT7_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT7_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT7_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT7_INTKNEPMIS_OFFSET        0x9e8
-#define GC_USB_DIEPINT7_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT7_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT7_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT7_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT7_INEPNAKEFF_OFFSET        0x9e8
-#define GC_USB_DIEPINT7_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT7_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT7_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT7_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT7_TXFEMP_OFFSET            0x9e8
-#define GC_USB_DIEPINT7_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT7_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT7_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT7_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT7_TXFIFOUNDRN_OFFSET       0x9e8
-#define GC_USB_DIEPINT7_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT7_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT7_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT7_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT7_BNAINTR_OFFSET           0x9e8
-#define GC_USB_DIEPINT7_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT7_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT7_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT7_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT7_PKTDRPSTS_OFFSET         0x9e8
-#define GC_USB_DIEPINT7_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT7_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT7_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT7_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT7_BBLEERR_OFFSET           0x9e8
-#define GC_USB_DIEPINT7_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT7_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT7_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT7_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT7_NAKINTRPT_OFFSET         0x9e8
-#define GC_USB_DIEPINT7_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT7_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT7_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT7_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT7_NYETINTRPT_OFFSET        0x9e8
-#define GC_USB_DIEPTSIZ7_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ7_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ7_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ7_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ7_XFERSIZE_OFFSET         0x9f0
-#define GC_USB_DIEPTSIZ7_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ7_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ7_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ7_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ7_PKTCNT_OFFSET           0x9f0
-#define GC_USB_DIEPTSIZ7_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ7_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ7_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ7_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ7_MC_OFFSET               0x9f0
-#define GC_USB_DIEPDMA7_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA7_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA7_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA7_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA7_DMAADDR_OFFSET           0x9f4
-#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_OFFSET   0x9f8
-#define GC_USB_DIEPDMAB7_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB7_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB7_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB7_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB7_DMABUFFERADDR_OFFSET    0x9fc
-#define GC_USB_DIEPCTL8_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL8_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL8_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL8_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL8_MPS_OFFSET               0xa00
-#define GC_USB_DIEPCTL8_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL8_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL8_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL8_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL8_USBACTEP_OFFSET          0xa00
-#define GC_USB_DIEPCTL8_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL8_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL8_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL8_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL8_DPID_OFFSET              0xa00
-#define GC_USB_DIEPCTL8_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL8_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL8_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL8_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL8_NAKSTS_OFFSET            0xa00
-#define GC_USB_DIEPCTL8_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL8_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL8_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL8_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL8_EPTYPE_OFFSET            0xa00
-#define GC_USB_DIEPCTL8_STALL_LSB                0x15
-#define GC_USB_DIEPCTL8_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL8_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL8_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL8_STALL_OFFSET             0xa00
-#define GC_USB_DIEPCTL8_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL8_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL8_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL8_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL8_TXFNUM_OFFSET            0xa00
-#define GC_USB_DIEPCTL8_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL8_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL8_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL8_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL8_CNAK_OFFSET              0xa00
-#define GC_USB_DIEPCTL8_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL8_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL8_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL8_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL8_SNAK_OFFSET              0xa00
-#define GC_USB_DIEPCTL8_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL8_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL8_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL8_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL8_SETD0PID_OFFSET          0xa00
-#define GC_USB_DIEPCTL8_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL8_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL8_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL8_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL8_SETD1PID_OFFSET          0xa00
-#define GC_USB_DIEPCTL8_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL8_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL8_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL8_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL8_EPDIS_OFFSET             0xa00
-#define GC_USB_DIEPCTL8_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL8_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL8_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL8_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL8_EPENA_OFFSET             0xa00
-#define GC_USB_DIEPINT8_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT8_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT8_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT8_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT8_XFERCOMPL_OFFSET         0xa08
-#define GC_USB_DIEPINT8_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT8_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT8_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT8_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT8_EPDISBLD_OFFSET          0xa08
-#define GC_USB_DIEPINT8_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT8_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT8_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT8_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT8_AHBERR_OFFSET            0xa08
-#define GC_USB_DIEPINT8_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT8_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT8_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT8_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT8_TIMEOUT_OFFSET           0xa08
-#define GC_USB_DIEPINT8_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT8_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT8_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT8_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT8_INTKNTXFEMP_OFFSET       0xa08
-#define GC_USB_DIEPINT8_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT8_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT8_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT8_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT8_INTKNEPMIS_OFFSET        0xa08
-#define GC_USB_DIEPINT8_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT8_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT8_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT8_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT8_INEPNAKEFF_OFFSET        0xa08
-#define GC_USB_DIEPINT8_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT8_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT8_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT8_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT8_TXFEMP_OFFSET            0xa08
-#define GC_USB_DIEPINT8_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT8_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT8_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT8_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT8_TXFIFOUNDRN_OFFSET       0xa08
-#define GC_USB_DIEPINT8_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT8_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT8_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT8_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT8_BNAINTR_OFFSET           0xa08
-#define GC_USB_DIEPINT8_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT8_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT8_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT8_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT8_PKTDRPSTS_OFFSET         0xa08
-#define GC_USB_DIEPINT8_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT8_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT8_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT8_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT8_BBLEERR_OFFSET           0xa08
-#define GC_USB_DIEPINT8_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT8_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT8_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT8_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT8_NAKINTRPT_OFFSET         0xa08
-#define GC_USB_DIEPINT8_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT8_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT8_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT8_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT8_NYETINTRPT_OFFSET        0xa08
-#define GC_USB_DIEPTSIZ8_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ8_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ8_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ8_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ8_XFERSIZE_OFFSET         0xa10
-#define GC_USB_DIEPTSIZ8_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ8_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ8_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ8_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ8_PKTCNT_OFFSET           0xa10
-#define GC_USB_DIEPTSIZ8_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ8_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ8_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ8_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ8_MC_OFFSET               0xa10
-#define GC_USB_DIEPDMA8_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA8_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA8_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA8_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA8_DMAADDR_OFFSET           0xa14
-#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_OFFSET   0xa18
-#define GC_USB_DIEPDMAB8_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB8_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB8_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB8_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB8_DMABUFFERADDR_OFFSET    0xa1c
-#define GC_USB_DIEPCTL9_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL9_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL9_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL9_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL9_MPS_OFFSET               0xa20
-#define GC_USB_DIEPCTL9_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL9_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL9_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL9_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL9_USBACTEP_OFFSET          0xa20
-#define GC_USB_DIEPCTL9_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL9_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL9_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL9_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL9_DPID_OFFSET              0xa20
-#define GC_USB_DIEPCTL9_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL9_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL9_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL9_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL9_NAKSTS_OFFSET            0xa20
-#define GC_USB_DIEPCTL9_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL9_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL9_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL9_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL9_EPTYPE_OFFSET            0xa20
-#define GC_USB_DIEPCTL9_STALL_LSB                0x15
-#define GC_USB_DIEPCTL9_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL9_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL9_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL9_STALL_OFFSET             0xa20
-#define GC_USB_DIEPCTL9_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL9_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL9_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL9_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL9_TXFNUM_OFFSET            0xa20
-#define GC_USB_DIEPCTL9_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL9_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL9_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL9_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL9_CNAK_OFFSET              0xa20
-#define GC_USB_DIEPCTL9_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL9_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL9_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL9_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL9_SNAK_OFFSET              0xa20
-#define GC_USB_DIEPCTL9_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL9_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL9_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL9_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL9_SETD0PID_OFFSET          0xa20
-#define GC_USB_DIEPCTL9_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL9_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL9_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL9_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL9_SETD1PID_OFFSET          0xa20
-#define GC_USB_DIEPCTL9_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL9_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL9_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL9_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL9_EPDIS_OFFSET             0xa20
-#define GC_USB_DIEPCTL9_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL9_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL9_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL9_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL9_EPENA_OFFSET             0xa20
-#define GC_USB_DIEPINT9_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT9_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT9_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT9_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT9_XFERCOMPL_OFFSET         0xa28
-#define GC_USB_DIEPINT9_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT9_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT9_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT9_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT9_EPDISBLD_OFFSET          0xa28
-#define GC_USB_DIEPINT9_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT9_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT9_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT9_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT9_AHBERR_OFFSET            0xa28
-#define GC_USB_DIEPINT9_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT9_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT9_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT9_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT9_TIMEOUT_OFFSET           0xa28
-#define GC_USB_DIEPINT9_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT9_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT9_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT9_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT9_INTKNTXFEMP_OFFSET       0xa28
-#define GC_USB_DIEPINT9_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT9_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT9_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT9_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT9_INTKNEPMIS_OFFSET        0xa28
-#define GC_USB_DIEPINT9_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT9_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT9_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT9_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT9_INEPNAKEFF_OFFSET        0xa28
-#define GC_USB_DIEPINT9_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT9_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT9_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT9_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT9_TXFEMP_OFFSET            0xa28
-#define GC_USB_DIEPINT9_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT9_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT9_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT9_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT9_TXFIFOUNDRN_OFFSET       0xa28
-#define GC_USB_DIEPINT9_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT9_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT9_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT9_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT9_BNAINTR_OFFSET           0xa28
-#define GC_USB_DIEPINT9_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT9_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT9_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT9_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT9_PKTDRPSTS_OFFSET         0xa28
-#define GC_USB_DIEPINT9_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT9_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT9_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT9_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT9_BBLEERR_OFFSET           0xa28
-#define GC_USB_DIEPINT9_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT9_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT9_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT9_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT9_NAKINTRPT_OFFSET         0xa28
-#define GC_USB_DIEPINT9_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT9_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT9_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT9_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT9_NYETINTRPT_OFFSET        0xa28
-#define GC_USB_DIEPTSIZ9_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ9_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ9_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ9_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ9_XFERSIZE_OFFSET         0xa30
-#define GC_USB_DIEPTSIZ9_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ9_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ9_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ9_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ9_PKTCNT_OFFSET           0xa30
-#define GC_USB_DIEPTSIZ9_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ9_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ9_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ9_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ9_MC_OFFSET               0xa30
-#define GC_USB_DIEPDMA9_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA9_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA9_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA9_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA9_DMAADDR_OFFSET           0xa34
-#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_OFFSET   0xa38
-#define GC_USB_DIEPDMAB9_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB9_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB9_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB9_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB9_DMABUFFERADDR_OFFSET    0xa3c
-#define GC_USB_DIEPCTL10_MPS_LSB                 0x0
-#define GC_USB_DIEPCTL10_MPS_MASK                0x7ff
-#define GC_USB_DIEPCTL10_MPS_SIZE                0xb
-#define GC_USB_DIEPCTL10_MPS_DEFAULT             0x0
-#define GC_USB_DIEPCTL10_MPS_OFFSET              0xa40
-#define GC_USB_DIEPCTL10_USBACTEP_LSB            0xf
-#define GC_USB_DIEPCTL10_USBACTEP_MASK           0x8000
-#define GC_USB_DIEPCTL10_USBACTEP_SIZE           0x1
-#define GC_USB_DIEPCTL10_USBACTEP_DEFAULT        0x0
-#define GC_USB_DIEPCTL10_USBACTEP_OFFSET         0xa40
-#define GC_USB_DIEPCTL10_DPID_LSB                0x10
-#define GC_USB_DIEPCTL10_DPID_MASK               0x10000
-#define GC_USB_DIEPCTL10_DPID_SIZE               0x1
-#define GC_USB_DIEPCTL10_DPID_DEFAULT            0x0
-#define GC_USB_DIEPCTL10_DPID_OFFSET             0xa40
-#define GC_USB_DIEPCTL10_NAKSTS_LSB              0x11
-#define GC_USB_DIEPCTL10_NAKSTS_MASK             0x20000
-#define GC_USB_DIEPCTL10_NAKSTS_SIZE             0x1
-#define GC_USB_DIEPCTL10_NAKSTS_DEFAULT          0x0
-#define GC_USB_DIEPCTL10_NAKSTS_OFFSET           0xa40
-#define GC_USB_DIEPCTL10_EPTYPE_LSB              0x12
-#define GC_USB_DIEPCTL10_EPTYPE_MASK             0xc0000
-#define GC_USB_DIEPCTL10_EPTYPE_SIZE             0x2
-#define GC_USB_DIEPCTL10_EPTYPE_DEFAULT          0x0
-#define GC_USB_DIEPCTL10_EPTYPE_OFFSET           0xa40
-#define GC_USB_DIEPCTL10_STALL_LSB               0x15
-#define GC_USB_DIEPCTL10_STALL_MASK              0x200000
-#define GC_USB_DIEPCTL10_STALL_SIZE              0x1
-#define GC_USB_DIEPCTL10_STALL_DEFAULT           0x0
-#define GC_USB_DIEPCTL10_STALL_OFFSET            0xa40
-#define GC_USB_DIEPCTL10_TXFNUM_LSB              0x16
-#define GC_USB_DIEPCTL10_TXFNUM_MASK             0x3c00000
-#define GC_USB_DIEPCTL10_TXFNUM_SIZE             0x4
-#define GC_USB_DIEPCTL10_TXFNUM_DEFAULT          0x0
-#define GC_USB_DIEPCTL10_TXFNUM_OFFSET           0xa40
-#define GC_USB_DIEPCTL10_CNAK_LSB                0x1a
-#define GC_USB_DIEPCTL10_CNAK_MASK               0x4000000
-#define GC_USB_DIEPCTL10_CNAK_SIZE               0x1
-#define GC_USB_DIEPCTL10_CNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL10_CNAK_OFFSET             0xa40
-#define GC_USB_DIEPCTL10_SNAK_LSB                0x1b
-#define GC_USB_DIEPCTL10_SNAK_MASK               0x8000000
-#define GC_USB_DIEPCTL10_SNAK_SIZE               0x1
-#define GC_USB_DIEPCTL10_SNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL10_SNAK_OFFSET             0xa40
-#define GC_USB_DIEPCTL10_SETD0PID_LSB            0x1c
-#define GC_USB_DIEPCTL10_SETD0PID_MASK           0x10000000
-#define GC_USB_DIEPCTL10_SETD0PID_SIZE           0x1
-#define GC_USB_DIEPCTL10_SETD0PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL10_SETD0PID_OFFSET         0xa40
-#define GC_USB_DIEPCTL10_SETD1PID_LSB            0x1d
-#define GC_USB_DIEPCTL10_SETD1PID_MASK           0x20000000
-#define GC_USB_DIEPCTL10_SETD1PID_SIZE           0x1
-#define GC_USB_DIEPCTL10_SETD1PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL10_SETD1PID_OFFSET         0xa40
-#define GC_USB_DIEPCTL10_EPDIS_LSB               0x1e
-#define GC_USB_DIEPCTL10_EPDIS_MASK              0x40000000
-#define GC_USB_DIEPCTL10_EPDIS_SIZE              0x1
-#define GC_USB_DIEPCTL10_EPDIS_DEFAULT           0x0
-#define GC_USB_DIEPCTL10_EPDIS_OFFSET            0xa40
-#define GC_USB_DIEPCTL10_EPENA_LSB               0x1f
-#define GC_USB_DIEPCTL10_EPENA_MASK              0x80000000
-#define GC_USB_DIEPCTL10_EPENA_SIZE              0x1
-#define GC_USB_DIEPCTL10_EPENA_DEFAULT           0x0
-#define GC_USB_DIEPCTL10_EPENA_OFFSET            0xa40
-#define GC_USB_DIEPINT10_XFERCOMPL_LSB           0x0
-#define GC_USB_DIEPINT10_XFERCOMPL_MASK          0x1
-#define GC_USB_DIEPINT10_XFERCOMPL_SIZE          0x1
-#define GC_USB_DIEPINT10_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DIEPINT10_XFERCOMPL_OFFSET        0xa48
-#define GC_USB_DIEPINT10_EPDISBLD_LSB            0x1
-#define GC_USB_DIEPINT10_EPDISBLD_MASK           0x2
-#define GC_USB_DIEPINT10_EPDISBLD_SIZE           0x1
-#define GC_USB_DIEPINT10_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DIEPINT10_EPDISBLD_OFFSET         0xa48
-#define GC_USB_DIEPINT10_AHBERR_LSB              0x2
-#define GC_USB_DIEPINT10_AHBERR_MASK             0x4
-#define GC_USB_DIEPINT10_AHBERR_SIZE             0x1
-#define GC_USB_DIEPINT10_AHBERR_DEFAULT          0x0
-#define GC_USB_DIEPINT10_AHBERR_OFFSET           0xa48
-#define GC_USB_DIEPINT10_TIMEOUT_LSB             0x3
-#define GC_USB_DIEPINT10_TIMEOUT_MASK            0x8
-#define GC_USB_DIEPINT10_TIMEOUT_SIZE            0x1
-#define GC_USB_DIEPINT10_TIMEOUT_DEFAULT         0x0
-#define GC_USB_DIEPINT10_TIMEOUT_OFFSET          0xa48
-#define GC_USB_DIEPINT10_INTKNTXFEMP_LSB         0x4
-#define GC_USB_DIEPINT10_INTKNTXFEMP_MASK        0x10
-#define GC_USB_DIEPINT10_INTKNTXFEMP_SIZE        0x1
-#define GC_USB_DIEPINT10_INTKNTXFEMP_DEFAULT     0x0
-#define GC_USB_DIEPINT10_INTKNTXFEMP_OFFSET      0xa48
-#define GC_USB_DIEPINT10_INTKNEPMIS_LSB          0x5
-#define GC_USB_DIEPINT10_INTKNEPMIS_MASK         0x20
-#define GC_USB_DIEPINT10_INTKNEPMIS_SIZE         0x1
-#define GC_USB_DIEPINT10_INTKNEPMIS_DEFAULT      0x0
-#define GC_USB_DIEPINT10_INTKNEPMIS_OFFSET       0xa48
-#define GC_USB_DIEPINT10_INEPNAKEFF_LSB          0x6
-#define GC_USB_DIEPINT10_INEPNAKEFF_MASK         0x40
-#define GC_USB_DIEPINT10_INEPNAKEFF_SIZE         0x1
-#define GC_USB_DIEPINT10_INEPNAKEFF_DEFAULT      0x0
-#define GC_USB_DIEPINT10_INEPNAKEFF_OFFSET       0xa48
-#define GC_USB_DIEPINT10_TXFEMP_LSB              0x7
-#define GC_USB_DIEPINT10_TXFEMP_MASK             0x80
-#define GC_USB_DIEPINT10_TXFEMP_SIZE             0x1
-#define GC_USB_DIEPINT10_TXFEMP_DEFAULT          0x0
-#define GC_USB_DIEPINT10_TXFEMP_OFFSET           0xa48
-#define GC_USB_DIEPINT10_TXFIFOUNDRN_LSB         0x8
-#define GC_USB_DIEPINT10_TXFIFOUNDRN_MASK        0x100
-#define GC_USB_DIEPINT10_TXFIFOUNDRN_SIZE        0x1
-#define GC_USB_DIEPINT10_TXFIFOUNDRN_DEFAULT     0x0
-#define GC_USB_DIEPINT10_TXFIFOUNDRN_OFFSET      0xa48
-#define GC_USB_DIEPINT10_BNAINTR_LSB             0x9
-#define GC_USB_DIEPINT10_BNAINTR_MASK            0x200
-#define GC_USB_DIEPINT10_BNAINTR_SIZE            0x1
-#define GC_USB_DIEPINT10_BNAINTR_DEFAULT         0x0
-#define GC_USB_DIEPINT10_BNAINTR_OFFSET          0xa48
-#define GC_USB_DIEPINT10_PKTDRPSTS_LSB           0xb
-#define GC_USB_DIEPINT10_PKTDRPSTS_MASK          0x800
-#define GC_USB_DIEPINT10_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DIEPINT10_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DIEPINT10_PKTDRPSTS_OFFSET        0xa48
-#define GC_USB_DIEPINT10_BBLEERR_LSB             0xc
-#define GC_USB_DIEPINT10_BBLEERR_MASK            0x1000
-#define GC_USB_DIEPINT10_BBLEERR_SIZE            0x1
-#define GC_USB_DIEPINT10_BBLEERR_DEFAULT         0x0
-#define GC_USB_DIEPINT10_BBLEERR_OFFSET          0xa48
-#define GC_USB_DIEPINT10_NAKINTRPT_LSB           0xd
-#define GC_USB_DIEPINT10_NAKINTRPT_MASK          0x2000
-#define GC_USB_DIEPINT10_NAKINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT10_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT10_NAKINTRPT_OFFSET        0xa48
-#define GC_USB_DIEPINT10_NYETINTRPT_LSB          0xe
-#define GC_USB_DIEPINT10_NYETINTRPT_MASK         0x4000
-#define GC_USB_DIEPINT10_NYETINTRPT_SIZE         0x1
-#define GC_USB_DIEPINT10_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DIEPINT10_NYETINTRPT_OFFSET       0xa48
-#define GC_USB_DIEPTSIZ10_XFERSIZE_LSB           0x0
-#define GC_USB_DIEPTSIZ10_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DIEPTSIZ10_XFERSIZE_SIZE          0x13
-#define GC_USB_DIEPTSIZ10_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DIEPTSIZ10_XFERSIZE_OFFSET        0xa50
-#define GC_USB_DIEPTSIZ10_PKTCNT_LSB             0x13
-#define GC_USB_DIEPTSIZ10_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DIEPTSIZ10_PKTCNT_SIZE            0xa
-#define GC_USB_DIEPTSIZ10_PKTCNT_DEFAULT         0x0
-#define GC_USB_DIEPTSIZ10_PKTCNT_OFFSET          0xa50
-#define GC_USB_DIEPTSIZ10_MC_LSB                 0x1d
-#define GC_USB_DIEPTSIZ10_MC_MASK                0x60000000
-#define GC_USB_DIEPTSIZ10_MC_SIZE                0x2
-#define GC_USB_DIEPTSIZ10_MC_DEFAULT             0x0
-#define GC_USB_DIEPTSIZ10_MC_OFFSET              0xa50
-#define GC_USB_DIEPDMA10_DMAADDR_LSB             0x0
-#define GC_USB_DIEPDMA10_DMAADDR_MASK            0xffffffff
-#define GC_USB_DIEPDMA10_DMAADDR_SIZE            0x20
-#define GC_USB_DIEPDMA10_DMAADDR_DEFAULT         0x0
-#define GC_USB_DIEPDMA10_DMAADDR_OFFSET          0xa54
-#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_LSB     0x0
-#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_MASK    0xffff
-#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_SIZE    0x10
+#define GC_USB_GHWCFG4_PHYDATAWIDTH_LSB 0xe
+#define GC_USB_GHWCFG4_PHYDATAWIDTH_MASK 0xc000
+#define GC_USB_GHWCFG4_PHYDATAWIDTH_SIZE 0x2
+#define GC_USB_GHWCFG4_PHYDATAWIDTH_DEFAULT 0x0
+#define GC_USB_GHWCFG4_PHYDATAWIDTH_OFFSET 0x50
+#define GC_USB_GHWCFG4_NUMCTLEPS_LSB 0x10
+#define GC_USB_GHWCFG4_NUMCTLEPS_MASK 0xf0000
+#define GC_USB_GHWCFG4_NUMCTLEPS_SIZE 0x4
+#define GC_USB_GHWCFG4_NUMCTLEPS_DEFAULT 0x0
+#define GC_USB_GHWCFG4_NUMCTLEPS_OFFSET 0x50
+#define GC_USB_GHWCFG4_IDDGFLTR_LSB 0x14
+#define GC_USB_GHWCFG4_IDDGFLTR_MASK 0x100000
+#define GC_USB_GHWCFG4_IDDGFLTR_SIZE 0x1
+#define GC_USB_GHWCFG4_IDDGFLTR_DEFAULT 0x0
+#define GC_USB_GHWCFG4_IDDGFLTR_OFFSET 0x50
+#define GC_USB_GHWCFG4_VBUSVALIDFLTR_LSB 0x15
+#define GC_USB_GHWCFG4_VBUSVALIDFLTR_MASK 0x200000
+#define GC_USB_GHWCFG4_VBUSVALIDFLTR_SIZE 0x1
+#define GC_USB_GHWCFG4_VBUSVALIDFLTR_DEFAULT 0x0
+#define GC_USB_GHWCFG4_VBUSVALIDFLTR_OFFSET 0x50
+#define GC_USB_GHWCFG4_AVALIDFLTR_LSB 0x16
+#define GC_USB_GHWCFG4_AVALIDFLTR_MASK 0x400000
+#define GC_USB_GHWCFG4_AVALIDFLTR_SIZE 0x1
+#define GC_USB_GHWCFG4_AVALIDFLTR_DEFAULT 0x0
+#define GC_USB_GHWCFG4_AVALIDFLTR_OFFSET 0x50
+#define GC_USB_GHWCFG4_BVALIDFLTR_LSB 0x17
+#define GC_USB_GHWCFG4_BVALIDFLTR_MASK 0x800000
+#define GC_USB_GHWCFG4_BVALIDFLTR_SIZE 0x1
+#define GC_USB_GHWCFG4_BVALIDFLTR_DEFAULT 0x0
+#define GC_USB_GHWCFG4_BVALIDFLTR_OFFSET 0x50
+#define GC_USB_GHWCFG4_SESSENDFLTR_LSB 0x18
+#define GC_USB_GHWCFG4_SESSENDFLTR_MASK 0x1000000
+#define GC_USB_GHWCFG4_SESSENDFLTR_SIZE 0x1
+#define GC_USB_GHWCFG4_SESSENDFLTR_DEFAULT 0x0
+#define GC_USB_GHWCFG4_SESSENDFLTR_OFFSET 0x50
+#define GC_USB_GHWCFG4_DEDFIFOMODE_LSB 0x19
+#define GC_USB_GHWCFG4_DEDFIFOMODE_MASK 0x2000000
+#define GC_USB_GHWCFG4_DEDFIFOMODE_SIZE 0x1
+#define GC_USB_GHWCFG4_DEDFIFOMODE_DEFAULT 0x0
+#define GC_USB_GHWCFG4_DEDFIFOMODE_OFFSET 0x50
+#define GC_USB_GHWCFG4_INEPS_LSB 0x1a
+#define GC_USB_GHWCFG4_INEPS_MASK 0x3c000000
+#define GC_USB_GHWCFG4_INEPS_SIZE 0x4
+#define GC_USB_GHWCFG4_INEPS_DEFAULT 0x0
+#define GC_USB_GHWCFG4_INEPS_OFFSET 0x50
+#define GC_USB_GHWCFG4_DESCDMAENABLED_LSB 0x1e
+#define GC_USB_GHWCFG4_DESCDMAENABLED_MASK 0x40000000
+#define GC_USB_GHWCFG4_DESCDMAENABLED_SIZE 0x1
+#define GC_USB_GHWCFG4_DESCDMAENABLED_DEFAULT 0x0
+#define GC_USB_GHWCFG4_DESCDMAENABLED_OFFSET 0x50
+#define GC_USB_GHWCFG4_DESCDMA_LSB 0x1f
+#define GC_USB_GHWCFG4_DESCDMA_MASK 0x80000000
+#define GC_USB_GHWCFG4_DESCDMA_SIZE 0x1
+#define GC_USB_GHWCFG4_DESCDMA_DEFAULT 0x0
+#define GC_USB_GHWCFG4_DESCDMA_OFFSET 0x50
+#define GC_USB_GDFIFOCFG_GDFIFOCFG_LSB 0x0
+#define GC_USB_GDFIFOCFG_GDFIFOCFG_MASK 0xffff
+#define GC_USB_GDFIFOCFG_GDFIFOCFG_SIZE 0x10
+#define GC_USB_GDFIFOCFG_GDFIFOCFG_DEFAULT 0x0
+#define GC_USB_GDFIFOCFG_GDFIFOCFG_OFFSET 0x5c
+#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_LSB 0x10
+#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_MASK 0xffff0000
+#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_SIZE 0x10
+#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_DEFAULT 0x0
+#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_OFFSET 0x5c
+#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_LSB 0x0
+#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_MASK 0x7ff
+#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_SIZE 0xb
+#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_DEFAULT 0x0
+#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_OFFSET 0x104
+#define GC_USB_DIEPTXF1_RESERVED11_LSB 0xc
+#define GC_USB_DIEPTXF1_RESERVED11_MASK 0x1000
+#define GC_USB_DIEPTXF1_RESERVED11_SIZE 0x1
+#define GC_USB_DIEPTXF1_RESERVED11_DEFAULT 0x1
+#define GC_USB_DIEPTXF1_RESERVED11_OFFSET 0x104
+#define GC_USB_DIEPTXF1_INEPNTXFDEP_LSB 0x10
+#define GC_USB_DIEPTXF1_INEPNTXFDEP_MASK 0x3f0000
+#define GC_USB_DIEPTXF1_INEPNTXFDEP_SIZE 0x6
+#define GC_USB_DIEPTXF1_INEPNTXFDEP_DEFAULT 0x0
+#define GC_USB_DIEPTXF1_INEPNTXFDEP_OFFSET 0x104
+#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_LSB 0x0
+#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_MASK 0x7ff
+#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_SIZE 0xb
+#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_DEFAULT 0x0
+#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_OFFSET 0x108
+#define GC_USB_DIEPTXF2_INEPNTXFDEP_LSB 0x10
+#define GC_USB_DIEPTXF2_INEPNTXFDEP_MASK 0x3f0000
+#define GC_USB_DIEPTXF2_INEPNTXFDEP_SIZE 0x6
+#define GC_USB_DIEPTXF2_INEPNTXFDEP_DEFAULT 0x0
+#define GC_USB_DIEPTXF2_INEPNTXFDEP_OFFSET 0x108
+#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_LSB 0x0
+#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_MASK 0x7ff
+#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_SIZE 0xb
+#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_DEFAULT 0x0
+#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_OFFSET 0x10c
+#define GC_USB_DIEPTXF3_INEPNTXFDEP_LSB 0x10
+#define GC_USB_DIEPTXF3_INEPNTXFDEP_MASK 0x3f0000
+#define GC_USB_DIEPTXF3_INEPNTXFDEP_SIZE 0x6
+#define GC_USB_DIEPTXF3_INEPNTXFDEP_DEFAULT 0x0
+#define GC_USB_DIEPTXF3_INEPNTXFDEP_OFFSET 0x10c
+#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_LSB 0x0
+#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_MASK 0x7ff
+#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_SIZE 0xb
+#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_DEFAULT 0x0
+#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_OFFSET 0x110
+#define GC_USB_DIEPTXF4_INEPNTXFDEP_LSB 0x10
+#define GC_USB_DIEPTXF4_INEPNTXFDEP_MASK 0x3f0000
+#define GC_USB_DIEPTXF4_INEPNTXFDEP_SIZE 0x6
+#define GC_USB_DIEPTXF4_INEPNTXFDEP_DEFAULT 0x0
+#define GC_USB_DIEPTXF4_INEPNTXFDEP_OFFSET 0x110
+#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_LSB 0x0
+#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_MASK 0x7ff
+#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_SIZE 0xb
+#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_DEFAULT 0x0
+#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_OFFSET 0x114
+#define GC_USB_DIEPTXF5_INEPNTXFDEP_LSB 0x10
+#define GC_USB_DIEPTXF5_INEPNTXFDEP_MASK 0x3f0000
+#define GC_USB_DIEPTXF5_INEPNTXFDEP_SIZE 0x6
+#define GC_USB_DIEPTXF5_INEPNTXFDEP_DEFAULT 0x0
+#define GC_USB_DIEPTXF5_INEPNTXFDEP_OFFSET 0x114
+#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_LSB 0x0
+#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_MASK 0x7ff
+#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_SIZE 0xb
+#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_DEFAULT 0x0
+#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_OFFSET 0x118
+#define GC_USB_DIEPTXF6_INEPNTXFDEP_LSB 0x10
+#define GC_USB_DIEPTXF6_INEPNTXFDEP_MASK 0x3f0000
+#define GC_USB_DIEPTXF6_INEPNTXFDEP_SIZE 0x6
+#define GC_USB_DIEPTXF6_INEPNTXFDEP_DEFAULT 0x0
+#define GC_USB_DIEPTXF6_INEPNTXFDEP_OFFSET 0x118
+#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_LSB 0x0
+#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_MASK 0x7ff
+#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_SIZE 0xb
+#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_DEFAULT 0x0
+#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_OFFSET 0x11c
+#define GC_USB_DIEPTXF7_INEPNTXFDEP_LSB 0x10
+#define GC_USB_DIEPTXF7_INEPNTXFDEP_MASK 0x3f0000
+#define GC_USB_DIEPTXF7_INEPNTXFDEP_SIZE 0x6
+#define GC_USB_DIEPTXF7_INEPNTXFDEP_DEFAULT 0x0
+#define GC_USB_DIEPTXF7_INEPNTXFDEP_OFFSET 0x11c
+#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_LSB 0x0
+#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_MASK 0x7ff
+#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_SIZE 0xb
+#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_DEFAULT 0x0
+#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_OFFSET 0x120
+#define GC_USB_DIEPTXF8_INEPNTXFDEP_LSB 0x10
+#define GC_USB_DIEPTXF8_INEPNTXFDEP_MASK 0x3f0000
+#define GC_USB_DIEPTXF8_INEPNTXFDEP_SIZE 0x6
+#define GC_USB_DIEPTXF8_INEPNTXFDEP_DEFAULT 0x0
+#define GC_USB_DIEPTXF8_INEPNTXFDEP_OFFSET 0x120
+#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_LSB 0x0
+#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_MASK 0x7ff
+#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_SIZE 0xb
+#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_DEFAULT 0x0
+#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_OFFSET 0x124
+#define GC_USB_DIEPTXF9_INEPNTXFDEP_LSB 0x10
+#define GC_USB_DIEPTXF9_INEPNTXFDEP_MASK 0x3f0000
+#define GC_USB_DIEPTXF9_INEPNTXFDEP_SIZE 0x6
+#define GC_USB_DIEPTXF9_INEPNTXFDEP_DEFAULT 0x0
+#define GC_USB_DIEPTXF9_INEPNTXFDEP_OFFSET 0x124
+#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_LSB 0x0
+#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_MASK 0x7ff
+#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_SIZE 0xb
+#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_DEFAULT 0x0
+#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_OFFSET 0x128
+#define GC_USB_DIEPTXF10_INEPNTXFDEP_LSB 0x10
+#define GC_USB_DIEPTXF10_INEPNTXFDEP_MASK 0x3f0000
+#define GC_USB_DIEPTXF10_INEPNTXFDEP_SIZE 0x6
+#define GC_USB_DIEPTXF10_INEPNTXFDEP_DEFAULT 0x0
+#define GC_USB_DIEPTXF10_INEPNTXFDEP_OFFSET 0x128
+#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_LSB 0x0
+#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_MASK 0x7ff
+#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_SIZE 0xb
+#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_DEFAULT 0x0
+#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_OFFSET 0x12c
+#define GC_USB_DIEPTXF11_INEPNTXFDEP_LSB 0x10
+#define GC_USB_DIEPTXF11_INEPNTXFDEP_MASK 0x3f0000
+#define GC_USB_DIEPTXF11_INEPNTXFDEP_SIZE 0x6
+#define GC_USB_DIEPTXF11_INEPNTXFDEP_DEFAULT 0x0
+#define GC_USB_DIEPTXF11_INEPNTXFDEP_OFFSET 0x12c
+#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_LSB 0x0
+#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_MASK 0x7ff
+#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_SIZE 0xb
+#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_DEFAULT 0x0
+#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_OFFSET 0x130
+#define GC_USB_DIEPTXF12_INEPNTXFDEP_LSB 0x10
+#define GC_USB_DIEPTXF12_INEPNTXFDEP_MASK 0x3f0000
+#define GC_USB_DIEPTXF12_INEPNTXFDEP_SIZE 0x6
+#define GC_USB_DIEPTXF12_INEPNTXFDEP_DEFAULT 0x0
+#define GC_USB_DIEPTXF12_INEPNTXFDEP_OFFSET 0x130
+#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_LSB 0x0
+#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_MASK 0x7ff
+#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_SIZE 0xb
+#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_DEFAULT 0x0
+#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_OFFSET 0x134
+#define GC_USB_DIEPTXF13_INEPNTXFDEP_LSB 0x10
+#define GC_USB_DIEPTXF13_INEPNTXFDEP_MASK 0x3f0000
+#define GC_USB_DIEPTXF13_INEPNTXFDEP_SIZE 0x6
+#define GC_USB_DIEPTXF13_INEPNTXFDEP_DEFAULT 0x0
+#define GC_USB_DIEPTXF13_INEPNTXFDEP_OFFSET 0x134
+#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_LSB 0x0
+#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_MASK 0x7ff
+#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_SIZE 0xb
+#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_DEFAULT 0x0
+#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_OFFSET 0x138
+#define GC_USB_DIEPTXF14_INEPNTXFDEP_LSB 0x10
+#define GC_USB_DIEPTXF14_INEPNTXFDEP_MASK 0x3f0000
+#define GC_USB_DIEPTXF14_INEPNTXFDEP_SIZE 0x6
+#define GC_USB_DIEPTXF14_INEPNTXFDEP_DEFAULT 0x0
+#define GC_USB_DIEPTXF14_INEPNTXFDEP_OFFSET 0x138
+#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_LSB 0x0
+#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_MASK 0x7ff
+#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_SIZE 0xb
+#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_DEFAULT 0x0
+#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_OFFSET 0x13c
+#define GC_USB_DIEPTXF15_INEPNTXFDEP_LSB 0x10
+#define GC_USB_DIEPTXF15_INEPNTXFDEP_MASK 0x3f0000
+#define GC_USB_DIEPTXF15_INEPNTXFDEP_SIZE 0x6
+#define GC_USB_DIEPTXF15_INEPNTXFDEP_DEFAULT 0x0
+#define GC_USB_DIEPTXF15_INEPNTXFDEP_OFFSET 0x13c
+#define GC_USB_DCFG_DEVSPD_LSB 0x0
+#define GC_USB_DCFG_DEVSPD_MASK 0x3
+#define GC_USB_DCFG_DEVSPD_SIZE 0x2
+#define GC_USB_DCFG_DEVSPD_DEFAULT 0x0
+#define GC_USB_DCFG_DEVSPD_OFFSET 0x800
+#define GC_USB_DCFG_NZSTSOUTHSHK_LSB 0x2
+#define GC_USB_DCFG_NZSTSOUTHSHK_MASK 0x4
+#define GC_USB_DCFG_NZSTSOUTHSHK_SIZE 0x1
+#define GC_USB_DCFG_NZSTSOUTHSHK_DEFAULT 0x0
+#define GC_USB_DCFG_NZSTSOUTHSHK_OFFSET 0x800
+#define GC_USB_DCFG_ENA32KHZSUSP_LSB 0x3
+#define GC_USB_DCFG_ENA32KHZSUSP_MASK 0x8
+#define GC_USB_DCFG_ENA32KHZSUSP_SIZE 0x1
+#define GC_USB_DCFG_ENA32KHZSUSP_DEFAULT 0x0
+#define GC_USB_DCFG_ENA32KHZSUSP_OFFSET 0x800
+#define GC_USB_DCFG_DEVADDR_LSB 0x4
+#define GC_USB_DCFG_DEVADDR_MASK 0x7f0
+#define GC_USB_DCFG_DEVADDR_SIZE 0x7
+#define GC_USB_DCFG_DEVADDR_DEFAULT 0x0
+#define GC_USB_DCFG_DEVADDR_OFFSET 0x800
+#define GC_USB_DCFG_PERFRINT_LSB 0xb
+#define GC_USB_DCFG_PERFRINT_MASK 0x1800
+#define GC_USB_DCFG_PERFRINT_SIZE 0x2
+#define GC_USB_DCFG_PERFRINT_DEFAULT 0x0
+#define GC_USB_DCFG_PERFRINT_OFFSET 0x800
+#define GC_USB_DCFG_ENDEVOUTNAK_LSB 0xd
+#define GC_USB_DCFG_ENDEVOUTNAK_MASK 0x2000
+#define GC_USB_DCFG_ENDEVOUTNAK_SIZE 0x1
+#define GC_USB_DCFG_ENDEVOUTNAK_DEFAULT 0x0
+#define GC_USB_DCFG_ENDEVOUTNAK_OFFSET 0x800
+#define GC_USB_DCFG_XCVRDLY_LSB 0xe
+#define GC_USB_DCFG_XCVRDLY_MASK 0x4000
+#define GC_USB_DCFG_XCVRDLY_SIZE 0x1
+#define GC_USB_DCFG_XCVRDLY_DEFAULT 0x0
+#define GC_USB_DCFG_XCVRDLY_OFFSET 0x800
+#define GC_USB_DCFG_ERRATICINTMSK_LSB 0xf
+#define GC_USB_DCFG_ERRATICINTMSK_MASK 0x8000
+#define GC_USB_DCFG_ERRATICINTMSK_SIZE 0x1
+#define GC_USB_DCFG_ERRATICINTMSK_DEFAULT 0x0
+#define GC_USB_DCFG_ERRATICINTMSK_OFFSET 0x800
+#define GC_USB_DCFG_DESCDMA_LSB 0x17
+#define GC_USB_DCFG_DESCDMA_MASK 0x800000
+#define GC_USB_DCFG_DESCDMA_SIZE 0x1
+#define GC_USB_DCFG_DESCDMA_DEFAULT 0x0
+#define GC_USB_DCFG_DESCDMA_OFFSET 0x800
+#define GC_USB_DCFG_PERSCHINTVL_LSB 0x18
+#define GC_USB_DCFG_PERSCHINTVL_MASK 0x3000000
+#define GC_USB_DCFG_PERSCHINTVL_SIZE 0x2
+#define GC_USB_DCFG_PERSCHINTVL_DEFAULT 0x0
+#define GC_USB_DCFG_PERSCHINTVL_OFFSET 0x800
+#define GC_USB_DCFG_RESVALID_LSB 0x1a
+#define GC_USB_DCFG_RESVALID_MASK 0xfc000000
+#define GC_USB_DCFG_RESVALID_SIZE 0x6
+#define GC_USB_DCFG_RESVALID_DEFAULT 0x2
+#define GC_USB_DCFG_RESVALID_OFFSET 0x800
+#define GC_USB_DCTL_RMTWKUPSIG_LSB 0x0
+#define GC_USB_DCTL_RMTWKUPSIG_MASK 0x1
+#define GC_USB_DCTL_RMTWKUPSIG_SIZE 0x1
+#define GC_USB_DCTL_RMTWKUPSIG_DEFAULT 0x0
+#define GC_USB_DCTL_RMTWKUPSIG_OFFSET 0x804
+#define GC_USB_DCTL_SFTDISCON_LSB 0x1
+#define GC_USB_DCTL_SFTDISCON_MASK 0x2
+#define GC_USB_DCTL_SFTDISCON_SIZE 0x1
+#define GC_USB_DCTL_SFTDISCON_DEFAULT 0x0
+#define GC_USB_DCTL_SFTDISCON_OFFSET 0x804
+#define GC_USB_DCTL_GNPINNAKSTS_LSB 0x2
+#define GC_USB_DCTL_GNPINNAKSTS_MASK 0x4
+#define GC_USB_DCTL_GNPINNAKSTS_SIZE 0x1
+#define GC_USB_DCTL_GNPINNAKSTS_DEFAULT 0x0
+#define GC_USB_DCTL_GNPINNAKSTS_OFFSET 0x804
+#define GC_USB_DCTL_GOUTNAKSTS_LSB 0x3
+#define GC_USB_DCTL_GOUTNAKSTS_MASK 0x8
+#define GC_USB_DCTL_GOUTNAKSTS_SIZE 0x1
+#define GC_USB_DCTL_GOUTNAKSTS_DEFAULT 0x0
+#define GC_USB_DCTL_GOUTNAKSTS_OFFSET 0x804
+#define GC_USB_DCTL_TSTCTL_LSB 0x4
+#define GC_USB_DCTL_TSTCTL_MASK 0x70
+#define GC_USB_DCTL_TSTCTL_SIZE 0x3
+#define GC_USB_DCTL_TSTCTL_DEFAULT 0x0
+#define GC_USB_DCTL_TSTCTL_OFFSET 0x804
+#define GC_USB_DCTL_SGNPINNAK_LSB 0x7
+#define GC_USB_DCTL_SGNPINNAK_MASK 0x80
+#define GC_USB_DCTL_SGNPINNAK_SIZE 0x1
+#define GC_USB_DCTL_SGNPINNAK_DEFAULT 0x0
+#define GC_USB_DCTL_SGNPINNAK_OFFSET 0x804
+#define GC_USB_DCTL_CGNPINNAK_LSB 0x8
+#define GC_USB_DCTL_CGNPINNAK_MASK 0x100
+#define GC_USB_DCTL_CGNPINNAK_SIZE 0x1
+#define GC_USB_DCTL_CGNPINNAK_DEFAULT 0x0
+#define GC_USB_DCTL_CGNPINNAK_OFFSET 0x804
+#define GC_USB_DCTL_SGOUTNAK_LSB 0x9
+#define GC_USB_DCTL_SGOUTNAK_MASK 0x200
+#define GC_USB_DCTL_SGOUTNAK_SIZE 0x1
+#define GC_USB_DCTL_SGOUTNAK_DEFAULT 0x0
+#define GC_USB_DCTL_SGOUTNAK_OFFSET 0x804
+#define GC_USB_DCTL_CGOUTNAK_LSB 0xa
+#define GC_USB_DCTL_CGOUTNAK_MASK 0x400
+#define GC_USB_DCTL_CGOUTNAK_SIZE 0x1
+#define GC_USB_DCTL_CGOUTNAK_DEFAULT 0x0
+#define GC_USB_DCTL_CGOUTNAK_OFFSET 0x804
+#define GC_USB_DCTL_PWRONPRGDONE_LSB 0xb
+#define GC_USB_DCTL_PWRONPRGDONE_MASK 0x800
+#define GC_USB_DCTL_PWRONPRGDONE_SIZE 0x1
+#define GC_USB_DCTL_PWRONPRGDONE_DEFAULT 0x0
+#define GC_USB_DCTL_PWRONPRGDONE_OFFSET 0x804
+#define GC_USB_DCTL_GMC_LSB 0xd
+#define GC_USB_DCTL_GMC_MASK 0x6000
+#define GC_USB_DCTL_GMC_SIZE 0x2
+#define GC_USB_DCTL_GMC_DEFAULT 0x0
+#define GC_USB_DCTL_GMC_OFFSET 0x804
+#define GC_USB_DCTL_IGNRFRMNUM_LSB 0xf
+#define GC_USB_DCTL_IGNRFRMNUM_MASK 0x8000
+#define GC_USB_DCTL_IGNRFRMNUM_SIZE 0x1
+#define GC_USB_DCTL_IGNRFRMNUM_DEFAULT 0x0
+#define GC_USB_DCTL_IGNRFRMNUM_OFFSET 0x804
+#define GC_USB_DCTL_NAKONBBLE_LSB 0x10
+#define GC_USB_DCTL_NAKONBBLE_MASK 0x10000
+#define GC_USB_DCTL_NAKONBBLE_SIZE 0x1
+#define GC_USB_DCTL_NAKONBBLE_DEFAULT 0x0
+#define GC_USB_DCTL_NAKONBBLE_OFFSET 0x804
+#define GC_USB_DCTL_ENCONTONBNA_LSB 0x11
+#define GC_USB_DCTL_ENCONTONBNA_MASK 0x20000
+#define GC_USB_DCTL_ENCONTONBNA_SIZE 0x1
+#define GC_USB_DCTL_ENCONTONBNA_DEFAULT 0x0
+#define GC_USB_DCTL_ENCONTONBNA_OFFSET 0x804
+#define GC_USB_DSTS_SUSPSTS_LSB 0x0
+#define GC_USB_DSTS_SUSPSTS_MASK 0x1
+#define GC_USB_DSTS_SUSPSTS_SIZE 0x1
+#define GC_USB_DSTS_SUSPSTS_DEFAULT 0x0
+#define GC_USB_DSTS_SUSPSTS_OFFSET 0x808
+#define GC_USB_DSTS_ENUMSPD_LSB 0x1
+#define GC_USB_DSTS_ENUMSPD_MASK 0x6
+#define GC_USB_DSTS_ENUMSPD_SIZE 0x2
+#define GC_USB_DSTS_ENUMSPD_DEFAULT 0x0
+#define GC_USB_DSTS_ENUMSPD_OFFSET 0x808
+#define GC_USB_DSTS_ERRTICERR_LSB 0x3
+#define GC_USB_DSTS_ERRTICERR_MASK 0x8
+#define GC_USB_DSTS_ERRTICERR_SIZE 0x1
+#define GC_USB_DSTS_ERRTICERR_DEFAULT 0x0
+#define GC_USB_DSTS_ERRTICERR_OFFSET 0x808
+#define GC_USB_DSTS_SOFFN_LSB 0x8
+#define GC_USB_DSTS_SOFFN_MASK 0x3fff00
+#define GC_USB_DSTS_SOFFN_SIZE 0xe
+#define GC_USB_DSTS_SOFFN_DEFAULT 0x0
+#define GC_USB_DSTS_SOFFN_OFFSET 0x808
+#define GC_USB_DSTS_DEVLNSTS_LSB 0x16
+#define GC_USB_DSTS_DEVLNSTS_MASK 0xc00000
+#define GC_USB_DSTS_DEVLNSTS_SIZE 0x2
+#define GC_USB_DSTS_DEVLNSTS_DEFAULT 0x0
+#define GC_USB_DSTS_DEVLNSTS_OFFSET 0x808
+#define GC_USB_DIEPMSK_XFERCOMPLMSK_LSB 0x0
+#define GC_USB_DIEPMSK_XFERCOMPLMSK_MASK 0x1
+#define GC_USB_DIEPMSK_XFERCOMPLMSK_SIZE 0x1
+#define GC_USB_DIEPMSK_XFERCOMPLMSK_DEFAULT 0x0
+#define GC_USB_DIEPMSK_XFERCOMPLMSK_OFFSET 0x810
+#define GC_USB_DIEPMSK_EPDISBLDMSK_LSB 0x1
+#define GC_USB_DIEPMSK_EPDISBLDMSK_MASK 0x2
+#define GC_USB_DIEPMSK_EPDISBLDMSK_SIZE 0x1
+#define GC_USB_DIEPMSK_EPDISBLDMSK_DEFAULT 0x0
+#define GC_USB_DIEPMSK_EPDISBLDMSK_OFFSET 0x810
+#define GC_USB_DIEPMSK_AHBERRMSK_LSB 0x2
+#define GC_USB_DIEPMSK_AHBERRMSK_MASK 0x4
+#define GC_USB_DIEPMSK_AHBERRMSK_SIZE 0x1
+#define GC_USB_DIEPMSK_AHBERRMSK_DEFAULT 0x0
+#define GC_USB_DIEPMSK_AHBERRMSK_OFFSET 0x810
+#define GC_USB_DIEPMSK_TIMEOUTMSK_LSB 0x3
+#define GC_USB_DIEPMSK_TIMEOUTMSK_MASK 0x8
+#define GC_USB_DIEPMSK_TIMEOUTMSK_SIZE 0x1
+#define GC_USB_DIEPMSK_TIMEOUTMSK_DEFAULT 0x0
+#define GC_USB_DIEPMSK_TIMEOUTMSK_OFFSET 0x810
+#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_LSB 0x4
+#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_MASK 0x10
+#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_SIZE 0x1
+#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_DEFAULT 0x0
+#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_OFFSET 0x810
+#define GC_USB_DIEPMSK_INTKNEPMISMSK_LSB 0x5
+#define GC_USB_DIEPMSK_INTKNEPMISMSK_MASK 0x20
+#define GC_USB_DIEPMSK_INTKNEPMISMSK_SIZE 0x1
+#define GC_USB_DIEPMSK_INTKNEPMISMSK_DEFAULT 0x0
+#define GC_USB_DIEPMSK_INTKNEPMISMSK_OFFSET 0x810
+#define GC_USB_DIEPMSK_INEPNAKEFFMSK_LSB 0x6
+#define GC_USB_DIEPMSK_INEPNAKEFFMSK_MASK 0x40
+#define GC_USB_DIEPMSK_INEPNAKEFFMSK_SIZE 0x1
+#define GC_USB_DIEPMSK_INEPNAKEFFMSK_DEFAULT 0x0
+#define GC_USB_DIEPMSK_INEPNAKEFFMSK_OFFSET 0x810
+#define GC_USB_DIEPMSK_RESERVED7_LSB 0x7
+#define GC_USB_DIEPMSK_RESERVED7_MASK 0x80
+#define GC_USB_DIEPMSK_RESERVED7_SIZE 0x1
+#define GC_USB_DIEPMSK_RESERVED7_DEFAULT 0x1
+#define GC_USB_DIEPMSK_RESERVED7_OFFSET 0x810
+#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_LSB 0x8
+#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_MASK 0x100
+#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_SIZE 0x1
+#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_DEFAULT 0x0
+#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_OFFSET 0x810
+#define GC_USB_DIEPMSK_BNAININTRMSK_LSB 0x9
+#define GC_USB_DIEPMSK_BNAININTRMSK_MASK 0x200
+#define GC_USB_DIEPMSK_BNAININTRMSK_SIZE 0x1
+#define GC_USB_DIEPMSK_BNAININTRMSK_DEFAULT 0x0
+#define GC_USB_DIEPMSK_BNAININTRMSK_OFFSET 0x810
+#define GC_USB_DIEPMSK_NAKMSK_LSB 0xd
+#define GC_USB_DIEPMSK_NAKMSK_MASK 0x2000
+#define GC_USB_DIEPMSK_NAKMSK_SIZE 0x1
+#define GC_USB_DIEPMSK_NAKMSK_DEFAULT 0x0
+#define GC_USB_DIEPMSK_NAKMSK_OFFSET 0x810
+#define GC_USB_DOEPMSK_XFERCOMPLMSK_LSB 0x0
+#define GC_USB_DOEPMSK_XFERCOMPLMSK_MASK 0x1
+#define GC_USB_DOEPMSK_XFERCOMPLMSK_SIZE 0x1
+#define GC_USB_DOEPMSK_XFERCOMPLMSK_DEFAULT 0x0
+#define GC_USB_DOEPMSK_XFERCOMPLMSK_OFFSET 0x814
+#define GC_USB_DOEPMSK_EPDISBLDMSK_LSB 0x1
+#define GC_USB_DOEPMSK_EPDISBLDMSK_MASK 0x2
+#define GC_USB_DOEPMSK_EPDISBLDMSK_SIZE 0x1
+#define GC_USB_DOEPMSK_EPDISBLDMSK_DEFAULT 0x0
+#define GC_USB_DOEPMSK_EPDISBLDMSK_OFFSET 0x814
+#define GC_USB_DOEPMSK_AHBERRMSK_LSB 0x2
+#define GC_USB_DOEPMSK_AHBERRMSK_MASK 0x4
+#define GC_USB_DOEPMSK_AHBERRMSK_SIZE 0x1
+#define GC_USB_DOEPMSK_AHBERRMSK_DEFAULT 0x0
+#define GC_USB_DOEPMSK_AHBERRMSK_OFFSET 0x814
+#define GC_USB_DOEPMSK_SETUPMSK_LSB 0x3
+#define GC_USB_DOEPMSK_SETUPMSK_MASK 0x8
+#define GC_USB_DOEPMSK_SETUPMSK_SIZE 0x1
+#define GC_USB_DOEPMSK_SETUPMSK_DEFAULT 0x0
+#define GC_USB_DOEPMSK_SETUPMSK_OFFSET 0x814
+#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_LSB 0x4
+#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_MASK 0x10
+#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_SIZE 0x1
+#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_DEFAULT 0x0
+#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_OFFSET 0x814
+#define GC_USB_DOEPMSK_STSPHSERCVDMSK_LSB 0x5
+#define GC_USB_DOEPMSK_STSPHSERCVDMSK_MASK 0x20
+#define GC_USB_DOEPMSK_STSPHSERCVDMSK_SIZE 0x1
+#define GC_USB_DOEPMSK_STSPHSERCVDMSK_DEFAULT 0x0
+#define GC_USB_DOEPMSK_STSPHSERCVDMSK_OFFSET 0x814
+#define GC_USB_DOEPMSK_BACK2BACKSETUP_LSB 0x6
+#define GC_USB_DOEPMSK_BACK2BACKSETUP_MASK 0x40
+#define GC_USB_DOEPMSK_BACK2BACKSETUP_SIZE 0x1
+#define GC_USB_DOEPMSK_BACK2BACKSETUP_DEFAULT 0x0
+#define GC_USB_DOEPMSK_BACK2BACKSETUP_OFFSET 0x814
+#define GC_USB_DOEPMSK_OUTPKTERRMSK_LSB 0x8
+#define GC_USB_DOEPMSK_OUTPKTERRMSK_MASK 0x100
+#define GC_USB_DOEPMSK_OUTPKTERRMSK_SIZE 0x1
+#define GC_USB_DOEPMSK_OUTPKTERRMSK_DEFAULT 0x0
+#define GC_USB_DOEPMSK_OUTPKTERRMSK_OFFSET 0x814
+#define GC_USB_DOEPMSK_BNAOUTINTRMSK_LSB 0x9
+#define GC_USB_DOEPMSK_BNAOUTINTRMSK_MASK 0x200
+#define GC_USB_DOEPMSK_BNAOUTINTRMSK_SIZE 0x1
+#define GC_USB_DOEPMSK_BNAOUTINTRMSK_DEFAULT 0x0
+#define GC_USB_DOEPMSK_BNAOUTINTRMSK_OFFSET 0x814
+#define GC_USB_DOEPMSK_BBLEERRMSK_LSB 0xc
+#define GC_USB_DOEPMSK_BBLEERRMSK_MASK 0x1000
+#define GC_USB_DOEPMSK_BBLEERRMSK_SIZE 0x1
+#define GC_USB_DOEPMSK_BBLEERRMSK_DEFAULT 0x0
+#define GC_USB_DOEPMSK_BBLEERRMSK_OFFSET 0x814
+#define GC_USB_DOEPMSK_NAKMSK_LSB 0xd
+#define GC_USB_DOEPMSK_NAKMSK_MASK 0x2000
+#define GC_USB_DOEPMSK_NAKMSK_SIZE 0x1
+#define GC_USB_DOEPMSK_NAKMSK_DEFAULT 0x0
+#define GC_USB_DOEPMSK_NAKMSK_OFFSET 0x814
+#define GC_USB_DOEPMSK_NYETMSK_LSB 0xe
+#define GC_USB_DOEPMSK_NYETMSK_MASK 0x4000
+#define GC_USB_DOEPMSK_NYETMSK_SIZE 0x1
+#define GC_USB_DOEPMSK_NYETMSK_DEFAULT 0x0
+#define GC_USB_DOEPMSK_NYETMSK_OFFSET 0x814
+#define GC_USB_DAINT_INEPINT0_LSB 0x0
+#define GC_USB_DAINT_INEPINT0_MASK 0x1
+#define GC_USB_DAINT_INEPINT0_SIZE 0x1
+#define GC_USB_DAINT_INEPINT0_DEFAULT 0x0
+#define GC_USB_DAINT_INEPINT0_OFFSET 0x818
+#define GC_USB_DAINT_INEPINT1_LSB 0x1
+#define GC_USB_DAINT_INEPINT1_MASK 0x2
+#define GC_USB_DAINT_INEPINT1_SIZE 0x1
+#define GC_USB_DAINT_INEPINT1_DEFAULT 0x0
+#define GC_USB_DAINT_INEPINT1_OFFSET 0x818
+#define GC_USB_DAINT_INEPINT2_LSB 0x2
+#define GC_USB_DAINT_INEPINT2_MASK 0x4
+#define GC_USB_DAINT_INEPINT2_SIZE 0x1
+#define GC_USB_DAINT_INEPINT2_DEFAULT 0x0
+#define GC_USB_DAINT_INEPINT2_OFFSET 0x818
+#define GC_USB_DAINT_INEPINT3_LSB 0x3
+#define GC_USB_DAINT_INEPINT3_MASK 0x8
+#define GC_USB_DAINT_INEPINT3_SIZE 0x1
+#define GC_USB_DAINT_INEPINT3_DEFAULT 0x0
+#define GC_USB_DAINT_INEPINT3_OFFSET 0x818
+#define GC_USB_DAINT_INEPINT4_LSB 0x4
+#define GC_USB_DAINT_INEPINT4_MASK 0x10
+#define GC_USB_DAINT_INEPINT4_SIZE 0x1
+#define GC_USB_DAINT_INEPINT4_DEFAULT 0x0
+#define GC_USB_DAINT_INEPINT4_OFFSET 0x818
+#define GC_USB_DAINT_INEPINT5_LSB 0x5
+#define GC_USB_DAINT_INEPINT5_MASK 0x20
+#define GC_USB_DAINT_INEPINT5_SIZE 0x1
+#define GC_USB_DAINT_INEPINT5_DEFAULT 0x0
+#define GC_USB_DAINT_INEPINT5_OFFSET 0x818
+#define GC_USB_DAINT_INEPINT6_LSB 0x6
+#define GC_USB_DAINT_INEPINT6_MASK 0x40
+#define GC_USB_DAINT_INEPINT6_SIZE 0x1
+#define GC_USB_DAINT_INEPINT6_DEFAULT 0x0
+#define GC_USB_DAINT_INEPINT6_OFFSET 0x818
+#define GC_USB_DAINT_INEPINT7_LSB 0x7
+#define GC_USB_DAINT_INEPINT7_MASK 0x80
+#define GC_USB_DAINT_INEPINT7_SIZE 0x1
+#define GC_USB_DAINT_INEPINT7_DEFAULT 0x0
+#define GC_USB_DAINT_INEPINT7_OFFSET 0x818
+#define GC_USB_DAINT_INEPINT8_LSB 0x8
+#define GC_USB_DAINT_INEPINT8_MASK 0x100
+#define GC_USB_DAINT_INEPINT8_SIZE 0x1
+#define GC_USB_DAINT_INEPINT8_DEFAULT 0x0
+#define GC_USB_DAINT_INEPINT8_OFFSET 0x818
+#define GC_USB_DAINT_INEPINT9_LSB 0x9
+#define GC_USB_DAINT_INEPINT9_MASK 0x200
+#define GC_USB_DAINT_INEPINT9_SIZE 0x1
+#define GC_USB_DAINT_INEPINT9_DEFAULT 0x0
+#define GC_USB_DAINT_INEPINT9_OFFSET 0x818
+#define GC_USB_DAINT_INEPINT10_LSB 0xa
+#define GC_USB_DAINT_INEPINT10_MASK 0x400
+#define GC_USB_DAINT_INEPINT10_SIZE 0x1
+#define GC_USB_DAINT_INEPINT10_DEFAULT 0x0
+#define GC_USB_DAINT_INEPINT10_OFFSET 0x818
+#define GC_USB_DAINT_INEPINT11_LSB 0xb
+#define GC_USB_DAINT_INEPINT11_MASK 0x800
+#define GC_USB_DAINT_INEPINT11_SIZE 0x1
+#define GC_USB_DAINT_INEPINT11_DEFAULT 0x0
+#define GC_USB_DAINT_INEPINT11_OFFSET 0x818
+#define GC_USB_DAINT_INEPINT12_LSB 0xc
+#define GC_USB_DAINT_INEPINT12_MASK 0x1000
+#define GC_USB_DAINT_INEPINT12_SIZE 0x1
+#define GC_USB_DAINT_INEPINT12_DEFAULT 0x0
+#define GC_USB_DAINT_INEPINT12_OFFSET 0x818
+#define GC_USB_DAINT_INEPINT13_LSB 0xd
+#define GC_USB_DAINT_INEPINT13_MASK 0x2000
+#define GC_USB_DAINT_INEPINT13_SIZE 0x1
+#define GC_USB_DAINT_INEPINT13_DEFAULT 0x0
+#define GC_USB_DAINT_INEPINT13_OFFSET 0x818
+#define GC_USB_DAINT_INEPINT14_LSB 0xe
+#define GC_USB_DAINT_INEPINT14_MASK 0x4000
+#define GC_USB_DAINT_INEPINT14_SIZE 0x1
+#define GC_USB_DAINT_INEPINT14_DEFAULT 0x0
+#define GC_USB_DAINT_INEPINT14_OFFSET 0x818
+#define GC_USB_DAINT_INEPINT15_LSB 0xf
+#define GC_USB_DAINT_INEPINT15_MASK 0x8000
+#define GC_USB_DAINT_INEPINT15_SIZE 0x1
+#define GC_USB_DAINT_INEPINT15_DEFAULT 0x0
+#define GC_USB_DAINT_INEPINT15_OFFSET 0x818
+#define GC_USB_DAINT_OUTEPINT0_LSB 0x10
+#define GC_USB_DAINT_OUTEPINT0_MASK 0x10000
+#define GC_USB_DAINT_OUTEPINT0_SIZE 0x1
+#define GC_USB_DAINT_OUTEPINT0_DEFAULT 0x0
+#define GC_USB_DAINT_OUTEPINT0_OFFSET 0x818
+#define GC_USB_DAINT_OUTEPINT1_LSB 0x11
+#define GC_USB_DAINT_OUTEPINT1_MASK 0x20000
+#define GC_USB_DAINT_OUTEPINT1_SIZE 0x1
+#define GC_USB_DAINT_OUTEPINT1_DEFAULT 0x0
+#define GC_USB_DAINT_OUTEPINT1_OFFSET 0x818
+#define GC_USB_DAINT_OUTEPINT2_LSB 0x12
+#define GC_USB_DAINT_OUTEPINT2_MASK 0x40000
+#define GC_USB_DAINT_OUTEPINT2_SIZE 0x1
+#define GC_USB_DAINT_OUTEPINT2_DEFAULT 0x0
+#define GC_USB_DAINT_OUTEPINT2_OFFSET 0x818
+#define GC_USB_DAINT_OUTEPINT3_LSB 0x13
+#define GC_USB_DAINT_OUTEPINT3_MASK 0x80000
+#define GC_USB_DAINT_OUTEPINT3_SIZE 0x1
+#define GC_USB_DAINT_OUTEPINT3_DEFAULT 0x0
+#define GC_USB_DAINT_OUTEPINT3_OFFSET 0x818
+#define GC_USB_DAINT_OUTEPINT4_LSB 0x14
+#define GC_USB_DAINT_OUTEPINT4_MASK 0x100000
+#define GC_USB_DAINT_OUTEPINT4_SIZE 0x1
+#define GC_USB_DAINT_OUTEPINT4_DEFAULT 0x0
+#define GC_USB_DAINT_OUTEPINT4_OFFSET 0x818
+#define GC_USB_DAINT_OUTEPINT5_LSB 0x15
+#define GC_USB_DAINT_OUTEPINT5_MASK 0x200000
+#define GC_USB_DAINT_OUTEPINT5_SIZE 0x1
+#define GC_USB_DAINT_OUTEPINT5_DEFAULT 0x0
+#define GC_USB_DAINT_OUTEPINT5_OFFSET 0x818
+#define GC_USB_DAINT_OUTEPINT6_LSB 0x16
+#define GC_USB_DAINT_OUTEPINT6_MASK 0x400000
+#define GC_USB_DAINT_OUTEPINT6_SIZE 0x1
+#define GC_USB_DAINT_OUTEPINT6_DEFAULT 0x0
+#define GC_USB_DAINT_OUTEPINT6_OFFSET 0x818
+#define GC_USB_DAINT_OUTEPINT7_LSB 0x17
+#define GC_USB_DAINT_OUTEPINT7_MASK 0x800000
+#define GC_USB_DAINT_OUTEPINT7_SIZE 0x1
+#define GC_USB_DAINT_OUTEPINT7_DEFAULT 0x0
+#define GC_USB_DAINT_OUTEPINT7_OFFSET 0x818
+#define GC_USB_DAINT_OUTEPINT8_LSB 0x18
+#define GC_USB_DAINT_OUTEPINT8_MASK 0x1000000
+#define GC_USB_DAINT_OUTEPINT8_SIZE 0x1
+#define GC_USB_DAINT_OUTEPINT8_DEFAULT 0x0
+#define GC_USB_DAINT_OUTEPINT8_OFFSET 0x818
+#define GC_USB_DAINT_OUTEPINT9_LSB 0x19
+#define GC_USB_DAINT_OUTEPINT9_MASK 0x2000000
+#define GC_USB_DAINT_OUTEPINT9_SIZE 0x1
+#define GC_USB_DAINT_OUTEPINT9_DEFAULT 0x0
+#define GC_USB_DAINT_OUTEPINT9_OFFSET 0x818
+#define GC_USB_DAINT_OUTEPINT10_LSB 0x1a
+#define GC_USB_DAINT_OUTEPINT10_MASK 0x4000000
+#define GC_USB_DAINT_OUTEPINT10_SIZE 0x1
+#define GC_USB_DAINT_OUTEPINT10_DEFAULT 0x0
+#define GC_USB_DAINT_OUTEPINT10_OFFSET 0x818
+#define GC_USB_DAINT_OUTEPINT11_LSB 0x1b
+#define GC_USB_DAINT_OUTEPINT11_MASK 0x8000000
+#define GC_USB_DAINT_OUTEPINT11_SIZE 0x1
+#define GC_USB_DAINT_OUTEPINT11_DEFAULT 0x0
+#define GC_USB_DAINT_OUTEPINT11_OFFSET 0x818
+#define GC_USB_DAINT_OUTEPINT12_LSB 0x1c
+#define GC_USB_DAINT_OUTEPINT12_MASK 0x10000000
+#define GC_USB_DAINT_OUTEPINT12_SIZE 0x1
+#define GC_USB_DAINT_OUTEPINT12_DEFAULT 0x0
+#define GC_USB_DAINT_OUTEPINT12_OFFSET 0x818
+#define GC_USB_DAINT_OUTEPINT13_LSB 0x1d
+#define GC_USB_DAINT_OUTEPINT13_MASK 0x20000000
+#define GC_USB_DAINT_OUTEPINT13_SIZE 0x1
+#define GC_USB_DAINT_OUTEPINT13_DEFAULT 0x0
+#define GC_USB_DAINT_OUTEPINT13_OFFSET 0x818
+#define GC_USB_DAINT_OUTEPINT14_LSB 0x1e
+#define GC_USB_DAINT_OUTEPINT14_MASK 0x40000000
+#define GC_USB_DAINT_OUTEPINT14_SIZE 0x1
+#define GC_USB_DAINT_OUTEPINT14_DEFAULT 0x0
+#define GC_USB_DAINT_OUTEPINT14_OFFSET 0x818
+#define GC_USB_DAINT_OUTEPINT15_LSB 0x1f
+#define GC_USB_DAINT_OUTEPINT15_MASK 0x80000000
+#define GC_USB_DAINT_OUTEPINT15_SIZE 0x1
+#define GC_USB_DAINT_OUTEPINT15_DEFAULT 0x0
+#define GC_USB_DAINT_OUTEPINT15_OFFSET 0x818
+#define GC_USB_DAINTMSK_INEPMSK0_LSB 0x0
+#define GC_USB_DAINTMSK_INEPMSK0_MASK 0x1
+#define GC_USB_DAINTMSK_INEPMSK0_SIZE 0x1
+#define GC_USB_DAINTMSK_INEPMSK0_DEFAULT 0x0
+#define GC_USB_DAINTMSK_INEPMSK0_OFFSET 0x81c
+#define GC_USB_DAINTMSK_INEPMSK1_LSB 0x1
+#define GC_USB_DAINTMSK_INEPMSK1_MASK 0x2
+#define GC_USB_DAINTMSK_INEPMSK1_SIZE 0x1
+#define GC_USB_DAINTMSK_INEPMSK1_DEFAULT 0x0
+#define GC_USB_DAINTMSK_INEPMSK1_OFFSET 0x81c
+#define GC_USB_DAINTMSK_INEPMSK2_LSB 0x2
+#define GC_USB_DAINTMSK_INEPMSK2_MASK 0x4
+#define GC_USB_DAINTMSK_INEPMSK2_SIZE 0x1
+#define GC_USB_DAINTMSK_INEPMSK2_DEFAULT 0x0
+#define GC_USB_DAINTMSK_INEPMSK2_OFFSET 0x81c
+#define GC_USB_DAINTMSK_INEPMSK3_LSB 0x3
+#define GC_USB_DAINTMSK_INEPMSK3_MASK 0x8
+#define GC_USB_DAINTMSK_INEPMSK3_SIZE 0x1
+#define GC_USB_DAINTMSK_INEPMSK3_DEFAULT 0x0
+#define GC_USB_DAINTMSK_INEPMSK3_OFFSET 0x81c
+#define GC_USB_DAINTMSK_INEPMSK4_LSB 0x4
+#define GC_USB_DAINTMSK_INEPMSK4_MASK 0x10
+#define GC_USB_DAINTMSK_INEPMSK4_SIZE 0x1
+#define GC_USB_DAINTMSK_INEPMSK4_DEFAULT 0x0
+#define GC_USB_DAINTMSK_INEPMSK4_OFFSET 0x81c
+#define GC_USB_DAINTMSK_INEPMSK5_LSB 0x5
+#define GC_USB_DAINTMSK_INEPMSK5_MASK 0x20
+#define GC_USB_DAINTMSK_INEPMSK5_SIZE 0x1
+#define GC_USB_DAINTMSK_INEPMSK5_DEFAULT 0x0
+#define GC_USB_DAINTMSK_INEPMSK5_OFFSET 0x81c
+#define GC_USB_DAINTMSK_INEPMSK6_LSB 0x6
+#define GC_USB_DAINTMSK_INEPMSK6_MASK 0x40
+#define GC_USB_DAINTMSK_INEPMSK6_SIZE 0x1
+#define GC_USB_DAINTMSK_INEPMSK6_DEFAULT 0x0
+#define GC_USB_DAINTMSK_INEPMSK6_OFFSET 0x81c
+#define GC_USB_DAINTMSK_INEPMSK7_LSB 0x7
+#define GC_USB_DAINTMSK_INEPMSK7_MASK 0x80
+#define GC_USB_DAINTMSK_INEPMSK7_SIZE 0x1
+#define GC_USB_DAINTMSK_INEPMSK7_DEFAULT 0x0
+#define GC_USB_DAINTMSK_INEPMSK7_OFFSET 0x81c
+#define GC_USB_DAINTMSK_INEPMSK8_LSB 0x8
+#define GC_USB_DAINTMSK_INEPMSK8_MASK 0x100
+#define GC_USB_DAINTMSK_INEPMSK8_SIZE 0x1
+#define GC_USB_DAINTMSK_INEPMSK8_DEFAULT 0x0
+#define GC_USB_DAINTMSK_INEPMSK8_OFFSET 0x81c
+#define GC_USB_DAINTMSK_INEPMSK9_LSB 0x9
+#define GC_USB_DAINTMSK_INEPMSK9_MASK 0x200
+#define GC_USB_DAINTMSK_INEPMSK9_SIZE 0x1
+#define GC_USB_DAINTMSK_INEPMSK9_DEFAULT 0x0
+#define GC_USB_DAINTMSK_INEPMSK9_OFFSET 0x81c
+#define GC_USB_DAINTMSK_INEPMSK10_LSB 0xa
+#define GC_USB_DAINTMSK_INEPMSK10_MASK 0x400
+#define GC_USB_DAINTMSK_INEPMSK10_SIZE 0x1
+#define GC_USB_DAINTMSK_INEPMSK10_DEFAULT 0x0
+#define GC_USB_DAINTMSK_INEPMSK10_OFFSET 0x81c
+#define GC_USB_DAINTMSK_INEPMSK11_LSB 0xb
+#define GC_USB_DAINTMSK_INEPMSK11_MASK 0x800
+#define GC_USB_DAINTMSK_INEPMSK11_SIZE 0x1
+#define GC_USB_DAINTMSK_INEPMSK11_DEFAULT 0x0
+#define GC_USB_DAINTMSK_INEPMSK11_OFFSET 0x81c
+#define GC_USB_DAINTMSK_INEPMSK12_LSB 0xc
+#define GC_USB_DAINTMSK_INEPMSK12_MASK 0x1000
+#define GC_USB_DAINTMSK_INEPMSK12_SIZE 0x1
+#define GC_USB_DAINTMSK_INEPMSK12_DEFAULT 0x0
+#define GC_USB_DAINTMSK_INEPMSK12_OFFSET 0x81c
+#define GC_USB_DAINTMSK_INEPMSK13_LSB 0xd
+#define GC_USB_DAINTMSK_INEPMSK13_MASK 0x2000
+#define GC_USB_DAINTMSK_INEPMSK13_SIZE 0x1
+#define GC_USB_DAINTMSK_INEPMSK13_DEFAULT 0x0
+#define GC_USB_DAINTMSK_INEPMSK13_OFFSET 0x81c
+#define GC_USB_DAINTMSK_INEPMSK14_LSB 0xe
+#define GC_USB_DAINTMSK_INEPMSK14_MASK 0x4000
+#define GC_USB_DAINTMSK_INEPMSK14_SIZE 0x1
+#define GC_USB_DAINTMSK_INEPMSK14_DEFAULT 0x0
+#define GC_USB_DAINTMSK_INEPMSK14_OFFSET 0x81c
+#define GC_USB_DAINTMSK_INEPMSK15_LSB 0xf
+#define GC_USB_DAINTMSK_INEPMSK15_MASK 0x8000
+#define GC_USB_DAINTMSK_INEPMSK15_SIZE 0x1
+#define GC_USB_DAINTMSK_INEPMSK15_DEFAULT 0x0
+#define GC_USB_DAINTMSK_INEPMSK15_OFFSET 0x81c
+#define GC_USB_DAINTMSK_OUTEPMSK0_LSB 0x10
+#define GC_USB_DAINTMSK_OUTEPMSK0_MASK 0x10000
+#define GC_USB_DAINTMSK_OUTEPMSK0_SIZE 0x1
+#define GC_USB_DAINTMSK_OUTEPMSK0_DEFAULT 0x0
+#define GC_USB_DAINTMSK_OUTEPMSK0_OFFSET 0x81c
+#define GC_USB_DAINTMSK_OUTEPMSK1_LSB 0x11
+#define GC_USB_DAINTMSK_OUTEPMSK1_MASK 0x20000
+#define GC_USB_DAINTMSK_OUTEPMSK1_SIZE 0x1
+#define GC_USB_DAINTMSK_OUTEPMSK1_DEFAULT 0x0
+#define GC_USB_DAINTMSK_OUTEPMSK1_OFFSET 0x81c
+#define GC_USB_DAINTMSK_OUTEPMSK2_LSB 0x12
+#define GC_USB_DAINTMSK_OUTEPMSK2_MASK 0x40000
+#define GC_USB_DAINTMSK_OUTEPMSK2_SIZE 0x1
+#define GC_USB_DAINTMSK_OUTEPMSK2_DEFAULT 0x0
+#define GC_USB_DAINTMSK_OUTEPMSK2_OFFSET 0x81c
+#define GC_USB_DAINTMSK_OUTEPMSK3_LSB 0x13
+#define GC_USB_DAINTMSK_OUTEPMSK3_MASK 0x80000
+#define GC_USB_DAINTMSK_OUTEPMSK3_SIZE 0x1
+#define GC_USB_DAINTMSK_OUTEPMSK3_DEFAULT 0x0
+#define GC_USB_DAINTMSK_OUTEPMSK3_OFFSET 0x81c
+#define GC_USB_DAINTMSK_OUTEPMSK4_LSB 0x14
+#define GC_USB_DAINTMSK_OUTEPMSK4_MASK 0x100000
+#define GC_USB_DAINTMSK_OUTEPMSK4_SIZE 0x1
+#define GC_USB_DAINTMSK_OUTEPMSK4_DEFAULT 0x0
+#define GC_USB_DAINTMSK_OUTEPMSK4_OFFSET 0x81c
+#define GC_USB_DAINTMSK_OUTEPMSK5_LSB 0x15
+#define GC_USB_DAINTMSK_OUTEPMSK5_MASK 0x200000
+#define GC_USB_DAINTMSK_OUTEPMSK5_SIZE 0x1
+#define GC_USB_DAINTMSK_OUTEPMSK5_DEFAULT 0x0
+#define GC_USB_DAINTMSK_OUTEPMSK5_OFFSET 0x81c
+#define GC_USB_DAINTMSK_OUTEPMSK6_LSB 0x16
+#define GC_USB_DAINTMSK_OUTEPMSK6_MASK 0x400000
+#define GC_USB_DAINTMSK_OUTEPMSK6_SIZE 0x1
+#define GC_USB_DAINTMSK_OUTEPMSK6_DEFAULT 0x0
+#define GC_USB_DAINTMSK_OUTEPMSK6_OFFSET 0x81c
+#define GC_USB_DAINTMSK_OUTEPMSK7_LSB 0x17
+#define GC_USB_DAINTMSK_OUTEPMSK7_MASK 0x800000
+#define GC_USB_DAINTMSK_OUTEPMSK7_SIZE 0x1
+#define GC_USB_DAINTMSK_OUTEPMSK7_DEFAULT 0x0
+#define GC_USB_DAINTMSK_OUTEPMSK7_OFFSET 0x81c
+#define GC_USB_DAINTMSK_OUTEPMSK8_LSB 0x18
+#define GC_USB_DAINTMSK_OUTEPMSK8_MASK 0x1000000
+#define GC_USB_DAINTMSK_OUTEPMSK8_SIZE 0x1
+#define GC_USB_DAINTMSK_OUTEPMSK8_DEFAULT 0x0
+#define GC_USB_DAINTMSK_OUTEPMSK8_OFFSET 0x81c
+#define GC_USB_DAINTMSK_OUTEPMSK9_LSB 0x19
+#define GC_USB_DAINTMSK_OUTEPMSK9_MASK 0x2000000
+#define GC_USB_DAINTMSK_OUTEPMSK9_SIZE 0x1
+#define GC_USB_DAINTMSK_OUTEPMSK9_DEFAULT 0x0
+#define GC_USB_DAINTMSK_OUTEPMSK9_OFFSET 0x81c
+#define GC_USB_DAINTMSK_OUTEPMSK10_LSB 0x1a
+#define GC_USB_DAINTMSK_OUTEPMSK10_MASK 0x4000000
+#define GC_USB_DAINTMSK_OUTEPMSK10_SIZE 0x1
+#define GC_USB_DAINTMSK_OUTEPMSK10_DEFAULT 0x0
+#define GC_USB_DAINTMSK_OUTEPMSK10_OFFSET 0x81c
+#define GC_USB_DAINTMSK_OUTEPMSK11_LSB 0x1b
+#define GC_USB_DAINTMSK_OUTEPMSK11_MASK 0x8000000
+#define GC_USB_DAINTMSK_OUTEPMSK11_SIZE 0x1
+#define GC_USB_DAINTMSK_OUTEPMSK11_DEFAULT 0x0
+#define GC_USB_DAINTMSK_OUTEPMSK11_OFFSET 0x81c
+#define GC_USB_DAINTMSK_OUTEPMSK12_LSB 0x1c
+#define GC_USB_DAINTMSK_OUTEPMSK12_MASK 0x10000000
+#define GC_USB_DAINTMSK_OUTEPMSK12_SIZE 0x1
+#define GC_USB_DAINTMSK_OUTEPMSK12_DEFAULT 0x0
+#define GC_USB_DAINTMSK_OUTEPMSK12_OFFSET 0x81c
+#define GC_USB_DAINTMSK_OUTEPMSK13_LSB 0x1d
+#define GC_USB_DAINTMSK_OUTEPMSK13_MASK 0x20000000
+#define GC_USB_DAINTMSK_OUTEPMSK13_SIZE 0x1
+#define GC_USB_DAINTMSK_OUTEPMSK13_DEFAULT 0x0
+#define GC_USB_DAINTMSK_OUTEPMSK13_OFFSET 0x81c
+#define GC_USB_DAINTMSK_OUTEPMSK14_LSB 0x1e
+#define GC_USB_DAINTMSK_OUTEPMSK14_MASK 0x40000000
+#define GC_USB_DAINTMSK_OUTEPMSK14_SIZE 0x1
+#define GC_USB_DAINTMSK_OUTEPMSK14_DEFAULT 0x0
+#define GC_USB_DAINTMSK_OUTEPMSK14_OFFSET 0x81c
+#define GC_USB_DAINTMSK_OUTEPMSK15_LSB 0x1f
+#define GC_USB_DAINTMSK_OUTEPMSK15_MASK 0x80000000
+#define GC_USB_DAINTMSK_OUTEPMSK15_SIZE 0x1
+#define GC_USB_DAINTMSK_OUTEPMSK15_DEFAULT 0x0
+#define GC_USB_DAINTMSK_OUTEPMSK15_OFFSET 0x81c
+#define GC_USB_DVBUSDIS_DVBUSDIS_LSB 0x0
+#define GC_USB_DVBUSDIS_DVBUSDIS_MASK 0xffff
+#define GC_USB_DVBUSDIS_DVBUSDIS_SIZE 0x10
+#define GC_USB_DVBUSDIS_DVBUSDIS_DEFAULT 0x0
+#define GC_USB_DVBUSDIS_DVBUSDIS_OFFSET 0x828
+#define GC_USB_DVBUSPULSE_DVBUSPULSE_LSB 0x0
+#define GC_USB_DVBUSPULSE_DVBUSPULSE_MASK 0xfff
+#define GC_USB_DVBUSPULSE_DVBUSPULSE_SIZE 0xc
+#define GC_USB_DVBUSPULSE_DVBUSPULSE_DEFAULT 0x0
+#define GC_USB_DVBUSPULSE_DVBUSPULSE_OFFSET 0x82c
+#define GC_USB_DTHRCTL_NONISOTHREN_LSB 0x0
+#define GC_USB_DTHRCTL_NONISOTHREN_MASK 0x1
+#define GC_USB_DTHRCTL_NONISOTHREN_SIZE 0x1
+#define GC_USB_DTHRCTL_NONISOTHREN_DEFAULT 0x0
+#define GC_USB_DTHRCTL_NONISOTHREN_OFFSET 0x830
+#define GC_USB_DTHRCTL_ISOTHREN_LSB 0x1
+#define GC_USB_DTHRCTL_ISOTHREN_MASK 0x2
+#define GC_USB_DTHRCTL_ISOTHREN_SIZE 0x1
+#define GC_USB_DTHRCTL_ISOTHREN_DEFAULT 0x0
+#define GC_USB_DTHRCTL_ISOTHREN_OFFSET 0x830
+#define GC_USB_DTHRCTL_TXTHRLEN_LSB 0x2
+#define GC_USB_DTHRCTL_TXTHRLEN_MASK 0x7fc
+#define GC_USB_DTHRCTL_TXTHRLEN_SIZE 0x9
+#define GC_USB_DTHRCTL_TXTHRLEN_DEFAULT 0x0
+#define GC_USB_DTHRCTL_TXTHRLEN_OFFSET 0x830
+#define GC_USB_DTHRCTL_AHBTHRRATIO_LSB 0xb
+#define GC_USB_DTHRCTL_AHBTHRRATIO_MASK 0x1800
+#define GC_USB_DTHRCTL_AHBTHRRATIO_SIZE 0x2
+#define GC_USB_DTHRCTL_AHBTHRRATIO_DEFAULT 0x0
+#define GC_USB_DTHRCTL_AHBTHRRATIO_OFFSET 0x830
+#define GC_USB_DTHRCTL_RXTHREN_LSB 0x10
+#define GC_USB_DTHRCTL_RXTHREN_MASK 0x10000
+#define GC_USB_DTHRCTL_RXTHREN_SIZE 0x1
+#define GC_USB_DTHRCTL_RXTHREN_DEFAULT 0x0
+#define GC_USB_DTHRCTL_RXTHREN_OFFSET 0x830
+#define GC_USB_DTHRCTL_RXTHRLEN_LSB 0x11
+#define GC_USB_DTHRCTL_RXTHRLEN_MASK 0x3fe0000
+#define GC_USB_DTHRCTL_RXTHRLEN_SIZE 0x9
+#define GC_USB_DTHRCTL_RXTHRLEN_DEFAULT 0x0
+#define GC_USB_DTHRCTL_RXTHRLEN_OFFSET 0x830
+#define GC_USB_DTHRCTL_ARBPRKEN_LSB 0x1b
+#define GC_USB_DTHRCTL_ARBPRKEN_MASK 0x8000000
+#define GC_USB_DTHRCTL_ARBPRKEN_SIZE 0x1
+#define GC_USB_DTHRCTL_ARBPRKEN_DEFAULT 0x0
+#define GC_USB_DTHRCTL_ARBPRKEN_OFFSET 0x830
+#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_LSB 0x0
+#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_MASK 0xffff
+#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_SIZE 0x10
+#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_DEFAULT 0x0
+#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_OFFSET 0x834
+#define GC_USB_DIEPCTL0_MPS_LSB 0x0
+#define GC_USB_DIEPCTL0_MPS_MASK 0x3
+#define GC_USB_DIEPCTL0_MPS_SIZE 0x2
+#define GC_USB_DIEPCTL0_MPS_DEFAULT 0x0
+#define GC_USB_DIEPCTL0_MPS_OFFSET 0x900
+#define GC_USB_DIEPCTL0_USBACTEP_LSB 0xf
+#define GC_USB_DIEPCTL0_USBACTEP_MASK 0x8000
+#define GC_USB_DIEPCTL0_USBACTEP_SIZE 0x1
+#define GC_USB_DIEPCTL0_USBACTEP_DEFAULT 0x0
+#define GC_USB_DIEPCTL0_USBACTEP_OFFSET 0x900
+#define GC_USB_DIEPCTL0_NAKSTS_LSB 0x11
+#define GC_USB_DIEPCTL0_NAKSTS_MASK 0x20000
+#define GC_USB_DIEPCTL0_NAKSTS_SIZE 0x1
+#define GC_USB_DIEPCTL0_NAKSTS_DEFAULT 0x0
+#define GC_USB_DIEPCTL0_NAKSTS_OFFSET 0x900
+#define GC_USB_DIEPCTL0_EPTYPE_LSB 0x12
+#define GC_USB_DIEPCTL0_EPTYPE_MASK 0xc0000
+#define GC_USB_DIEPCTL0_EPTYPE_SIZE 0x2
+#define GC_USB_DIEPCTL0_EPTYPE_DEFAULT 0x0
+#define GC_USB_DIEPCTL0_EPTYPE_OFFSET 0x900
+#define GC_USB_DIEPCTL0_STALL_LSB 0x15
+#define GC_USB_DIEPCTL0_STALL_MASK 0x200000
+#define GC_USB_DIEPCTL0_STALL_SIZE 0x1
+#define GC_USB_DIEPCTL0_STALL_DEFAULT 0x0
+#define GC_USB_DIEPCTL0_STALL_OFFSET 0x900
+#define GC_USB_DIEPCTL0_TXFNUM_LSB 0x16
+#define GC_USB_DIEPCTL0_TXFNUM_MASK 0x3c00000
+#define GC_USB_DIEPCTL0_TXFNUM_SIZE 0x4
+#define GC_USB_DIEPCTL0_TXFNUM_DEFAULT 0x0
+#define GC_USB_DIEPCTL0_TXFNUM_OFFSET 0x900
+#define GC_USB_DIEPCTL0_CNAK_LSB 0x1a
+#define GC_USB_DIEPCTL0_CNAK_MASK 0x4000000
+#define GC_USB_DIEPCTL0_CNAK_SIZE 0x1
+#define GC_USB_DIEPCTL0_CNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL0_CNAK_OFFSET 0x900
+#define GC_USB_DIEPCTL0_SNAK_LSB 0x1b
+#define GC_USB_DIEPCTL0_SNAK_MASK 0x8000000
+#define GC_USB_DIEPCTL0_SNAK_SIZE 0x1
+#define GC_USB_DIEPCTL0_SNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL0_SNAK_OFFSET 0x900
+#define GC_USB_DIEPCTL0_EPDIS_LSB 0x1e
+#define GC_USB_DIEPCTL0_EPDIS_MASK 0x40000000
+#define GC_USB_DIEPCTL0_EPDIS_SIZE 0x1
+#define GC_USB_DIEPCTL0_EPDIS_DEFAULT 0x0
+#define GC_USB_DIEPCTL0_EPDIS_OFFSET 0x900
+#define GC_USB_DIEPCTL0_EPENA_LSB 0x1f
+#define GC_USB_DIEPCTL0_EPENA_MASK 0x80000000
+#define GC_USB_DIEPCTL0_EPENA_SIZE 0x1
+#define GC_USB_DIEPCTL0_EPENA_DEFAULT 0x0
+#define GC_USB_DIEPCTL0_EPENA_OFFSET 0x900
+#define GC_USB_DIEPINT0_XFERCOMPL_LSB 0x0
+#define GC_USB_DIEPINT0_XFERCOMPL_MASK 0x1
+#define GC_USB_DIEPINT0_XFERCOMPL_SIZE 0x1
+#define GC_USB_DIEPINT0_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DIEPINT0_XFERCOMPL_OFFSET 0x908
+#define GC_USB_DIEPINT0_EPDISBLD_LSB 0x1
+#define GC_USB_DIEPINT0_EPDISBLD_MASK 0x2
+#define GC_USB_DIEPINT0_EPDISBLD_SIZE 0x1
+#define GC_USB_DIEPINT0_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DIEPINT0_EPDISBLD_OFFSET 0x908
+#define GC_USB_DIEPINT0_AHBERR_LSB 0x2
+#define GC_USB_DIEPINT0_AHBERR_MASK 0x4
+#define GC_USB_DIEPINT0_AHBERR_SIZE 0x1
+#define GC_USB_DIEPINT0_AHBERR_DEFAULT 0x0
+#define GC_USB_DIEPINT0_AHBERR_OFFSET 0x908
+#define GC_USB_DIEPINT0_TIMEOUT_LSB 0x3
+#define GC_USB_DIEPINT0_TIMEOUT_MASK 0x8
+#define GC_USB_DIEPINT0_TIMEOUT_SIZE 0x1
+#define GC_USB_DIEPINT0_TIMEOUT_DEFAULT 0x0
+#define GC_USB_DIEPINT0_TIMEOUT_OFFSET 0x908
+#define GC_USB_DIEPINT0_INTKNTXFEMP_LSB 0x4
+#define GC_USB_DIEPINT0_INTKNTXFEMP_MASK 0x10
+#define GC_USB_DIEPINT0_INTKNTXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT0_INTKNTXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT0_INTKNTXFEMP_OFFSET 0x908
+#define GC_USB_DIEPINT0_INTKNEPMIS_LSB 0x5
+#define GC_USB_DIEPINT0_INTKNEPMIS_MASK 0x20
+#define GC_USB_DIEPINT0_INTKNEPMIS_SIZE 0x1
+#define GC_USB_DIEPINT0_INTKNEPMIS_DEFAULT 0x0
+#define GC_USB_DIEPINT0_INTKNEPMIS_OFFSET 0x908
+#define GC_USB_DIEPINT0_INEPNAKEFF_LSB 0x6
+#define GC_USB_DIEPINT0_INEPNAKEFF_MASK 0x40
+#define GC_USB_DIEPINT0_INEPNAKEFF_SIZE 0x1
+#define GC_USB_DIEPINT0_INEPNAKEFF_DEFAULT 0x0
+#define GC_USB_DIEPINT0_INEPNAKEFF_OFFSET 0x908
+#define GC_USB_DIEPINT0_TXFEMP_LSB 0x7
+#define GC_USB_DIEPINT0_TXFEMP_MASK 0x80
+#define GC_USB_DIEPINT0_TXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT0_TXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT0_TXFEMP_OFFSET 0x908
+#define GC_USB_DIEPINT0_TXFIFOUNDRN_LSB 0x8
+#define GC_USB_DIEPINT0_TXFIFOUNDRN_MASK 0x100
+#define GC_USB_DIEPINT0_TXFIFOUNDRN_SIZE 0x1
+#define GC_USB_DIEPINT0_TXFIFOUNDRN_DEFAULT 0x0
+#define GC_USB_DIEPINT0_TXFIFOUNDRN_OFFSET 0x908
+#define GC_USB_DIEPINT0_BNAINTR_LSB 0x9
+#define GC_USB_DIEPINT0_BNAINTR_MASK 0x200
+#define GC_USB_DIEPINT0_BNAINTR_SIZE 0x1
+#define GC_USB_DIEPINT0_BNAINTR_DEFAULT 0x0
+#define GC_USB_DIEPINT0_BNAINTR_OFFSET 0x908
+#define GC_USB_DIEPINT0_PKTDRPSTS_LSB 0xb
+#define GC_USB_DIEPINT0_PKTDRPSTS_MASK 0x800
+#define GC_USB_DIEPINT0_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DIEPINT0_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DIEPINT0_PKTDRPSTS_OFFSET 0x908
+#define GC_USB_DIEPINT0_BBLEERR_LSB 0xc
+#define GC_USB_DIEPINT0_BBLEERR_MASK 0x1000
+#define GC_USB_DIEPINT0_BBLEERR_SIZE 0x1
+#define GC_USB_DIEPINT0_BBLEERR_DEFAULT 0x0
+#define GC_USB_DIEPINT0_BBLEERR_OFFSET 0x908
+#define GC_USB_DIEPINT0_NAKINTRPT_LSB 0xd
+#define GC_USB_DIEPINT0_NAKINTRPT_MASK 0x2000
+#define GC_USB_DIEPINT0_NAKINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT0_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT0_NAKINTRPT_OFFSET 0x908
+#define GC_USB_DIEPINT0_NYETINTRPT_LSB 0xe
+#define GC_USB_DIEPINT0_NYETINTRPT_MASK 0x4000
+#define GC_USB_DIEPINT0_NYETINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT0_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT0_NYETINTRPT_OFFSET 0x908
+#define GC_USB_DIEPTSIZ0_XFERSIZE_LSB 0x0
+#define GC_USB_DIEPTSIZ0_XFERSIZE_MASK 0x7f
+#define GC_USB_DIEPTSIZ0_XFERSIZE_SIZE 0x7
+#define GC_USB_DIEPTSIZ0_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ0_XFERSIZE_OFFSET 0x910
+#define GC_USB_DIEPTSIZ0_PKTCNT_LSB 0x13
+#define GC_USB_DIEPTSIZ0_PKTCNT_MASK 0x180000
+#define GC_USB_DIEPTSIZ0_PKTCNT_SIZE 0x2
+#define GC_USB_DIEPTSIZ0_PKTCNT_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ0_PKTCNT_OFFSET 0x910
+#define GC_USB_DIEPDMA0_DMAADDR_LSB 0x0
+#define GC_USB_DIEPDMA0_DMAADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMA0_DMAADDR_SIZE 0x20
+#define GC_USB_DIEPDMA0_DMAADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMA0_DMAADDR_OFFSET 0x914
+#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_LSB 0x0
+#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_MASK 0xffff
+#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_SIZE 0x10
+#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_DEFAULT 0x0
+#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_OFFSET 0x918
+#define GC_USB_DIEPDMAB0_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DIEPDMAB0_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMAB0_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DIEPDMAB0_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMAB0_DMABUFFERADDR_OFFSET 0x91c
+#define GC_USB_DIEPCTL1_MPS_LSB 0x0
+#define GC_USB_DIEPCTL1_MPS_MASK 0x7ff
+#define GC_USB_DIEPCTL1_MPS_SIZE 0xb
+#define GC_USB_DIEPCTL1_MPS_DEFAULT 0x0
+#define GC_USB_DIEPCTL1_MPS_OFFSET 0x920
+#define GC_USB_DIEPCTL1_USBACTEP_LSB 0xf
+#define GC_USB_DIEPCTL1_USBACTEP_MASK 0x8000
+#define GC_USB_DIEPCTL1_USBACTEP_SIZE 0x1
+#define GC_USB_DIEPCTL1_USBACTEP_DEFAULT 0x0
+#define GC_USB_DIEPCTL1_USBACTEP_OFFSET 0x920
+#define GC_USB_DIEPCTL1_DPID_LSB 0x10
+#define GC_USB_DIEPCTL1_DPID_MASK 0x10000
+#define GC_USB_DIEPCTL1_DPID_SIZE 0x1
+#define GC_USB_DIEPCTL1_DPID_DEFAULT 0x0
+#define GC_USB_DIEPCTL1_DPID_OFFSET 0x920
+#define GC_USB_DIEPCTL1_NAKSTS_LSB 0x11
+#define GC_USB_DIEPCTL1_NAKSTS_MASK 0x20000
+#define GC_USB_DIEPCTL1_NAKSTS_SIZE 0x1
+#define GC_USB_DIEPCTL1_NAKSTS_DEFAULT 0x0
+#define GC_USB_DIEPCTL1_NAKSTS_OFFSET 0x920
+#define GC_USB_DIEPCTL1_EPTYPE_LSB 0x12
+#define GC_USB_DIEPCTL1_EPTYPE_MASK 0xc0000
+#define GC_USB_DIEPCTL1_EPTYPE_SIZE 0x2
+#define GC_USB_DIEPCTL1_EPTYPE_DEFAULT 0x0
+#define GC_USB_DIEPCTL1_EPTYPE_OFFSET 0x920
+#define GC_USB_DIEPCTL1_STALL_LSB 0x15
+#define GC_USB_DIEPCTL1_STALL_MASK 0x200000
+#define GC_USB_DIEPCTL1_STALL_SIZE 0x1
+#define GC_USB_DIEPCTL1_STALL_DEFAULT 0x0
+#define GC_USB_DIEPCTL1_STALL_OFFSET 0x920
+#define GC_USB_DIEPCTL1_TXFNUM_LSB 0x16
+#define GC_USB_DIEPCTL1_TXFNUM_MASK 0x3c00000
+#define GC_USB_DIEPCTL1_TXFNUM_SIZE 0x4
+#define GC_USB_DIEPCTL1_TXFNUM_DEFAULT 0x0
+#define GC_USB_DIEPCTL1_TXFNUM_OFFSET 0x920
+#define GC_USB_DIEPCTL1_CNAK_LSB 0x1a
+#define GC_USB_DIEPCTL1_CNAK_MASK 0x4000000
+#define GC_USB_DIEPCTL1_CNAK_SIZE 0x1
+#define GC_USB_DIEPCTL1_CNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL1_CNAK_OFFSET 0x920
+#define GC_USB_DIEPCTL1_SNAK_LSB 0x1b
+#define GC_USB_DIEPCTL1_SNAK_MASK 0x8000000
+#define GC_USB_DIEPCTL1_SNAK_SIZE 0x1
+#define GC_USB_DIEPCTL1_SNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL1_SNAK_OFFSET 0x920
+#define GC_USB_DIEPCTL1_SETD0PID_LSB 0x1c
+#define GC_USB_DIEPCTL1_SETD0PID_MASK 0x10000000
+#define GC_USB_DIEPCTL1_SETD0PID_SIZE 0x1
+#define GC_USB_DIEPCTL1_SETD0PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL1_SETD0PID_OFFSET 0x920
+#define GC_USB_DIEPCTL1_SETD1PID_LSB 0x1d
+#define GC_USB_DIEPCTL1_SETD1PID_MASK 0x20000000
+#define GC_USB_DIEPCTL1_SETD1PID_SIZE 0x1
+#define GC_USB_DIEPCTL1_SETD1PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL1_SETD1PID_OFFSET 0x920
+#define GC_USB_DIEPCTL1_EPDIS_LSB 0x1e
+#define GC_USB_DIEPCTL1_EPDIS_MASK 0x40000000
+#define GC_USB_DIEPCTL1_EPDIS_SIZE 0x1
+#define GC_USB_DIEPCTL1_EPDIS_DEFAULT 0x0
+#define GC_USB_DIEPCTL1_EPDIS_OFFSET 0x920
+#define GC_USB_DIEPCTL1_EPENA_LSB 0x1f
+#define GC_USB_DIEPCTL1_EPENA_MASK 0x80000000
+#define GC_USB_DIEPCTL1_EPENA_SIZE 0x1
+#define GC_USB_DIEPCTL1_EPENA_DEFAULT 0x0
+#define GC_USB_DIEPCTL1_EPENA_OFFSET 0x920
+#define GC_USB_DIEPINT1_XFERCOMPL_LSB 0x0
+#define GC_USB_DIEPINT1_XFERCOMPL_MASK 0x1
+#define GC_USB_DIEPINT1_XFERCOMPL_SIZE 0x1
+#define GC_USB_DIEPINT1_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DIEPINT1_XFERCOMPL_OFFSET 0x928
+#define GC_USB_DIEPINT1_EPDISBLD_LSB 0x1
+#define GC_USB_DIEPINT1_EPDISBLD_MASK 0x2
+#define GC_USB_DIEPINT1_EPDISBLD_SIZE 0x1
+#define GC_USB_DIEPINT1_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DIEPINT1_EPDISBLD_OFFSET 0x928
+#define GC_USB_DIEPINT1_AHBERR_LSB 0x2
+#define GC_USB_DIEPINT1_AHBERR_MASK 0x4
+#define GC_USB_DIEPINT1_AHBERR_SIZE 0x1
+#define GC_USB_DIEPINT1_AHBERR_DEFAULT 0x0
+#define GC_USB_DIEPINT1_AHBERR_OFFSET 0x928
+#define GC_USB_DIEPINT1_TIMEOUT_LSB 0x3
+#define GC_USB_DIEPINT1_TIMEOUT_MASK 0x8
+#define GC_USB_DIEPINT1_TIMEOUT_SIZE 0x1
+#define GC_USB_DIEPINT1_TIMEOUT_DEFAULT 0x0
+#define GC_USB_DIEPINT1_TIMEOUT_OFFSET 0x928
+#define GC_USB_DIEPINT1_INTKNTXFEMP_LSB 0x4
+#define GC_USB_DIEPINT1_INTKNTXFEMP_MASK 0x10
+#define GC_USB_DIEPINT1_INTKNTXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT1_INTKNTXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT1_INTKNTXFEMP_OFFSET 0x928
+#define GC_USB_DIEPINT1_INTKNEPMIS_LSB 0x5
+#define GC_USB_DIEPINT1_INTKNEPMIS_MASK 0x20
+#define GC_USB_DIEPINT1_INTKNEPMIS_SIZE 0x1
+#define GC_USB_DIEPINT1_INTKNEPMIS_DEFAULT 0x0
+#define GC_USB_DIEPINT1_INTKNEPMIS_OFFSET 0x928
+#define GC_USB_DIEPINT1_INEPNAKEFF_LSB 0x6
+#define GC_USB_DIEPINT1_INEPNAKEFF_MASK 0x40
+#define GC_USB_DIEPINT1_INEPNAKEFF_SIZE 0x1
+#define GC_USB_DIEPINT1_INEPNAKEFF_DEFAULT 0x0
+#define GC_USB_DIEPINT1_INEPNAKEFF_OFFSET 0x928
+#define GC_USB_DIEPINT1_TXFEMP_LSB 0x7
+#define GC_USB_DIEPINT1_TXFEMP_MASK 0x80
+#define GC_USB_DIEPINT1_TXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT1_TXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT1_TXFEMP_OFFSET 0x928
+#define GC_USB_DIEPINT1_TXFIFOUNDRN_LSB 0x8
+#define GC_USB_DIEPINT1_TXFIFOUNDRN_MASK 0x100
+#define GC_USB_DIEPINT1_TXFIFOUNDRN_SIZE 0x1
+#define GC_USB_DIEPINT1_TXFIFOUNDRN_DEFAULT 0x0
+#define GC_USB_DIEPINT1_TXFIFOUNDRN_OFFSET 0x928
+#define GC_USB_DIEPINT1_BNAINTR_LSB 0x9
+#define GC_USB_DIEPINT1_BNAINTR_MASK 0x200
+#define GC_USB_DIEPINT1_BNAINTR_SIZE 0x1
+#define GC_USB_DIEPINT1_BNAINTR_DEFAULT 0x0
+#define GC_USB_DIEPINT1_BNAINTR_OFFSET 0x928
+#define GC_USB_DIEPINT1_PKTDRPSTS_LSB 0xb
+#define GC_USB_DIEPINT1_PKTDRPSTS_MASK 0x800
+#define GC_USB_DIEPINT1_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DIEPINT1_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DIEPINT1_PKTDRPSTS_OFFSET 0x928
+#define GC_USB_DIEPINT1_BBLEERR_LSB 0xc
+#define GC_USB_DIEPINT1_BBLEERR_MASK 0x1000
+#define GC_USB_DIEPINT1_BBLEERR_SIZE 0x1
+#define GC_USB_DIEPINT1_BBLEERR_DEFAULT 0x0
+#define GC_USB_DIEPINT1_BBLEERR_OFFSET 0x928
+#define GC_USB_DIEPINT1_NAKINTRPT_LSB 0xd
+#define GC_USB_DIEPINT1_NAKINTRPT_MASK 0x2000
+#define GC_USB_DIEPINT1_NAKINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT1_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT1_NAKINTRPT_OFFSET 0x928
+#define GC_USB_DIEPINT1_NYETINTRPT_LSB 0xe
+#define GC_USB_DIEPINT1_NYETINTRPT_MASK 0x4000
+#define GC_USB_DIEPINT1_NYETINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT1_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT1_NYETINTRPT_OFFSET 0x928
+#define GC_USB_DIEPTSIZ1_XFERSIZE_LSB 0x0
+#define GC_USB_DIEPTSIZ1_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DIEPTSIZ1_XFERSIZE_SIZE 0x13
+#define GC_USB_DIEPTSIZ1_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ1_XFERSIZE_OFFSET 0x930
+#define GC_USB_DIEPTSIZ1_PKTCNT_LSB 0x13
+#define GC_USB_DIEPTSIZ1_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DIEPTSIZ1_PKTCNT_SIZE 0xa
+#define GC_USB_DIEPTSIZ1_PKTCNT_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ1_PKTCNT_OFFSET 0x930
+#define GC_USB_DIEPTSIZ1_MC_LSB 0x1d
+#define GC_USB_DIEPTSIZ1_MC_MASK 0x60000000
+#define GC_USB_DIEPTSIZ1_MC_SIZE 0x2
+#define GC_USB_DIEPTSIZ1_MC_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ1_MC_OFFSET 0x930
+#define GC_USB_DIEPDMA1_DMAADDR_LSB 0x0
+#define GC_USB_DIEPDMA1_DMAADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMA1_DMAADDR_SIZE 0x20
+#define GC_USB_DIEPDMA1_DMAADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMA1_DMAADDR_OFFSET 0x934
+#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_LSB 0x0
+#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_MASK 0xffff
+#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_SIZE 0x10
+#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_DEFAULT 0x0
+#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_OFFSET 0x938
+#define GC_USB_DIEPDMAB1_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DIEPDMAB1_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMAB1_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DIEPDMAB1_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMAB1_DMABUFFERADDR_OFFSET 0x93c
+#define GC_USB_DIEPCTL2_MPS_LSB 0x0
+#define GC_USB_DIEPCTL2_MPS_MASK 0x7ff
+#define GC_USB_DIEPCTL2_MPS_SIZE 0xb
+#define GC_USB_DIEPCTL2_MPS_DEFAULT 0x0
+#define GC_USB_DIEPCTL2_MPS_OFFSET 0x940
+#define GC_USB_DIEPCTL2_USBACTEP_LSB 0xf
+#define GC_USB_DIEPCTL2_USBACTEP_MASK 0x8000
+#define GC_USB_DIEPCTL2_USBACTEP_SIZE 0x1
+#define GC_USB_DIEPCTL2_USBACTEP_DEFAULT 0x0
+#define GC_USB_DIEPCTL2_USBACTEP_OFFSET 0x940
+#define GC_USB_DIEPCTL2_DPID_LSB 0x10
+#define GC_USB_DIEPCTL2_DPID_MASK 0x10000
+#define GC_USB_DIEPCTL2_DPID_SIZE 0x1
+#define GC_USB_DIEPCTL2_DPID_DEFAULT 0x0
+#define GC_USB_DIEPCTL2_DPID_OFFSET 0x940
+#define GC_USB_DIEPCTL2_NAKSTS_LSB 0x11
+#define GC_USB_DIEPCTL2_NAKSTS_MASK 0x20000
+#define GC_USB_DIEPCTL2_NAKSTS_SIZE 0x1
+#define GC_USB_DIEPCTL2_NAKSTS_DEFAULT 0x0
+#define GC_USB_DIEPCTL2_NAKSTS_OFFSET 0x940
+#define GC_USB_DIEPCTL2_EPTYPE_LSB 0x12
+#define GC_USB_DIEPCTL2_EPTYPE_MASK 0xc0000
+#define GC_USB_DIEPCTL2_EPTYPE_SIZE 0x2
+#define GC_USB_DIEPCTL2_EPTYPE_DEFAULT 0x0
+#define GC_USB_DIEPCTL2_EPTYPE_OFFSET 0x940
+#define GC_USB_DIEPCTL2_STALL_LSB 0x15
+#define GC_USB_DIEPCTL2_STALL_MASK 0x200000
+#define GC_USB_DIEPCTL2_STALL_SIZE 0x1
+#define GC_USB_DIEPCTL2_STALL_DEFAULT 0x0
+#define GC_USB_DIEPCTL2_STALL_OFFSET 0x940
+#define GC_USB_DIEPCTL2_TXFNUM_LSB 0x16
+#define GC_USB_DIEPCTL2_TXFNUM_MASK 0x3c00000
+#define GC_USB_DIEPCTL2_TXFNUM_SIZE 0x4
+#define GC_USB_DIEPCTL2_TXFNUM_DEFAULT 0x0
+#define GC_USB_DIEPCTL2_TXFNUM_OFFSET 0x940
+#define GC_USB_DIEPCTL2_CNAK_LSB 0x1a
+#define GC_USB_DIEPCTL2_CNAK_MASK 0x4000000
+#define GC_USB_DIEPCTL2_CNAK_SIZE 0x1
+#define GC_USB_DIEPCTL2_CNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL2_CNAK_OFFSET 0x940
+#define GC_USB_DIEPCTL2_SNAK_LSB 0x1b
+#define GC_USB_DIEPCTL2_SNAK_MASK 0x8000000
+#define GC_USB_DIEPCTL2_SNAK_SIZE 0x1
+#define GC_USB_DIEPCTL2_SNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL2_SNAK_OFFSET 0x940
+#define GC_USB_DIEPCTL2_SETD0PID_LSB 0x1c
+#define GC_USB_DIEPCTL2_SETD0PID_MASK 0x10000000
+#define GC_USB_DIEPCTL2_SETD0PID_SIZE 0x1
+#define GC_USB_DIEPCTL2_SETD0PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL2_SETD0PID_OFFSET 0x940
+#define GC_USB_DIEPCTL2_SETD1PID_LSB 0x1d
+#define GC_USB_DIEPCTL2_SETD1PID_MASK 0x20000000
+#define GC_USB_DIEPCTL2_SETD1PID_SIZE 0x1
+#define GC_USB_DIEPCTL2_SETD1PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL2_SETD1PID_OFFSET 0x940
+#define GC_USB_DIEPCTL2_EPDIS_LSB 0x1e
+#define GC_USB_DIEPCTL2_EPDIS_MASK 0x40000000
+#define GC_USB_DIEPCTL2_EPDIS_SIZE 0x1
+#define GC_USB_DIEPCTL2_EPDIS_DEFAULT 0x0
+#define GC_USB_DIEPCTL2_EPDIS_OFFSET 0x940
+#define GC_USB_DIEPCTL2_EPENA_LSB 0x1f
+#define GC_USB_DIEPCTL2_EPENA_MASK 0x80000000
+#define GC_USB_DIEPCTL2_EPENA_SIZE 0x1
+#define GC_USB_DIEPCTL2_EPENA_DEFAULT 0x0
+#define GC_USB_DIEPCTL2_EPENA_OFFSET 0x940
+#define GC_USB_DIEPINT2_XFERCOMPL_LSB 0x0
+#define GC_USB_DIEPINT2_XFERCOMPL_MASK 0x1
+#define GC_USB_DIEPINT2_XFERCOMPL_SIZE 0x1
+#define GC_USB_DIEPINT2_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DIEPINT2_XFERCOMPL_OFFSET 0x948
+#define GC_USB_DIEPINT2_EPDISBLD_LSB 0x1
+#define GC_USB_DIEPINT2_EPDISBLD_MASK 0x2
+#define GC_USB_DIEPINT2_EPDISBLD_SIZE 0x1
+#define GC_USB_DIEPINT2_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DIEPINT2_EPDISBLD_OFFSET 0x948
+#define GC_USB_DIEPINT2_AHBERR_LSB 0x2
+#define GC_USB_DIEPINT2_AHBERR_MASK 0x4
+#define GC_USB_DIEPINT2_AHBERR_SIZE 0x1
+#define GC_USB_DIEPINT2_AHBERR_DEFAULT 0x0
+#define GC_USB_DIEPINT2_AHBERR_OFFSET 0x948
+#define GC_USB_DIEPINT2_TIMEOUT_LSB 0x3
+#define GC_USB_DIEPINT2_TIMEOUT_MASK 0x8
+#define GC_USB_DIEPINT2_TIMEOUT_SIZE 0x1
+#define GC_USB_DIEPINT2_TIMEOUT_DEFAULT 0x0
+#define GC_USB_DIEPINT2_TIMEOUT_OFFSET 0x948
+#define GC_USB_DIEPINT2_INTKNTXFEMP_LSB 0x4
+#define GC_USB_DIEPINT2_INTKNTXFEMP_MASK 0x10
+#define GC_USB_DIEPINT2_INTKNTXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT2_INTKNTXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT2_INTKNTXFEMP_OFFSET 0x948
+#define GC_USB_DIEPINT2_INTKNEPMIS_LSB 0x5
+#define GC_USB_DIEPINT2_INTKNEPMIS_MASK 0x20
+#define GC_USB_DIEPINT2_INTKNEPMIS_SIZE 0x1
+#define GC_USB_DIEPINT2_INTKNEPMIS_DEFAULT 0x0
+#define GC_USB_DIEPINT2_INTKNEPMIS_OFFSET 0x948
+#define GC_USB_DIEPINT2_INEPNAKEFF_LSB 0x6
+#define GC_USB_DIEPINT2_INEPNAKEFF_MASK 0x40
+#define GC_USB_DIEPINT2_INEPNAKEFF_SIZE 0x1
+#define GC_USB_DIEPINT2_INEPNAKEFF_DEFAULT 0x0
+#define GC_USB_DIEPINT2_INEPNAKEFF_OFFSET 0x948
+#define GC_USB_DIEPINT2_TXFEMP_LSB 0x7
+#define GC_USB_DIEPINT2_TXFEMP_MASK 0x80
+#define GC_USB_DIEPINT2_TXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT2_TXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT2_TXFEMP_OFFSET 0x948
+#define GC_USB_DIEPINT2_TXFIFOUNDRN_LSB 0x8
+#define GC_USB_DIEPINT2_TXFIFOUNDRN_MASK 0x100
+#define GC_USB_DIEPINT2_TXFIFOUNDRN_SIZE 0x1
+#define GC_USB_DIEPINT2_TXFIFOUNDRN_DEFAULT 0x0
+#define GC_USB_DIEPINT2_TXFIFOUNDRN_OFFSET 0x948
+#define GC_USB_DIEPINT2_BNAINTR_LSB 0x9
+#define GC_USB_DIEPINT2_BNAINTR_MASK 0x200
+#define GC_USB_DIEPINT2_BNAINTR_SIZE 0x1
+#define GC_USB_DIEPINT2_BNAINTR_DEFAULT 0x0
+#define GC_USB_DIEPINT2_BNAINTR_OFFSET 0x948
+#define GC_USB_DIEPINT2_PKTDRPSTS_LSB 0xb
+#define GC_USB_DIEPINT2_PKTDRPSTS_MASK 0x800
+#define GC_USB_DIEPINT2_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DIEPINT2_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DIEPINT2_PKTDRPSTS_OFFSET 0x948
+#define GC_USB_DIEPINT2_BBLEERR_LSB 0xc
+#define GC_USB_DIEPINT2_BBLEERR_MASK 0x1000
+#define GC_USB_DIEPINT2_BBLEERR_SIZE 0x1
+#define GC_USB_DIEPINT2_BBLEERR_DEFAULT 0x0
+#define GC_USB_DIEPINT2_BBLEERR_OFFSET 0x948
+#define GC_USB_DIEPINT2_NAKINTRPT_LSB 0xd
+#define GC_USB_DIEPINT2_NAKINTRPT_MASK 0x2000
+#define GC_USB_DIEPINT2_NAKINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT2_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT2_NAKINTRPT_OFFSET 0x948
+#define GC_USB_DIEPINT2_NYETINTRPT_LSB 0xe
+#define GC_USB_DIEPINT2_NYETINTRPT_MASK 0x4000
+#define GC_USB_DIEPINT2_NYETINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT2_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT2_NYETINTRPT_OFFSET 0x948
+#define GC_USB_DIEPTSIZ2_XFERSIZE_LSB 0x0
+#define GC_USB_DIEPTSIZ2_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DIEPTSIZ2_XFERSIZE_SIZE 0x13
+#define GC_USB_DIEPTSIZ2_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ2_XFERSIZE_OFFSET 0x950
+#define GC_USB_DIEPTSIZ2_PKTCNT_LSB 0x13
+#define GC_USB_DIEPTSIZ2_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DIEPTSIZ2_PKTCNT_SIZE 0xa
+#define GC_USB_DIEPTSIZ2_PKTCNT_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ2_PKTCNT_OFFSET 0x950
+#define GC_USB_DIEPTSIZ2_MC_LSB 0x1d
+#define GC_USB_DIEPTSIZ2_MC_MASK 0x60000000
+#define GC_USB_DIEPTSIZ2_MC_SIZE 0x2
+#define GC_USB_DIEPTSIZ2_MC_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ2_MC_OFFSET 0x950
+#define GC_USB_DIEPDMA2_DMAADDR_LSB 0x0
+#define GC_USB_DIEPDMA2_DMAADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMA2_DMAADDR_SIZE 0x20
+#define GC_USB_DIEPDMA2_DMAADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMA2_DMAADDR_OFFSET 0x954
+#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_LSB 0x0
+#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_MASK 0xffff
+#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_SIZE 0x10
+#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_DEFAULT 0x0
+#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_OFFSET 0x958
+#define GC_USB_DIEPDMAB2_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DIEPDMAB2_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMAB2_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DIEPDMAB2_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMAB2_DMABUFFERADDR_OFFSET 0x95c
+#define GC_USB_DIEPCTL3_MPS_LSB 0x0
+#define GC_USB_DIEPCTL3_MPS_MASK 0x7ff
+#define GC_USB_DIEPCTL3_MPS_SIZE 0xb
+#define GC_USB_DIEPCTL3_MPS_DEFAULT 0x0
+#define GC_USB_DIEPCTL3_MPS_OFFSET 0x960
+#define GC_USB_DIEPCTL3_USBACTEP_LSB 0xf
+#define GC_USB_DIEPCTL3_USBACTEP_MASK 0x8000
+#define GC_USB_DIEPCTL3_USBACTEP_SIZE 0x1
+#define GC_USB_DIEPCTL3_USBACTEP_DEFAULT 0x0
+#define GC_USB_DIEPCTL3_USBACTEP_OFFSET 0x960
+#define GC_USB_DIEPCTL3_DPID_LSB 0x10
+#define GC_USB_DIEPCTL3_DPID_MASK 0x10000
+#define GC_USB_DIEPCTL3_DPID_SIZE 0x1
+#define GC_USB_DIEPCTL3_DPID_DEFAULT 0x0
+#define GC_USB_DIEPCTL3_DPID_OFFSET 0x960
+#define GC_USB_DIEPCTL3_NAKSTS_LSB 0x11
+#define GC_USB_DIEPCTL3_NAKSTS_MASK 0x20000
+#define GC_USB_DIEPCTL3_NAKSTS_SIZE 0x1
+#define GC_USB_DIEPCTL3_NAKSTS_DEFAULT 0x0
+#define GC_USB_DIEPCTL3_NAKSTS_OFFSET 0x960
+#define GC_USB_DIEPCTL3_EPTYPE_LSB 0x12
+#define GC_USB_DIEPCTL3_EPTYPE_MASK 0xc0000
+#define GC_USB_DIEPCTL3_EPTYPE_SIZE 0x2
+#define GC_USB_DIEPCTL3_EPTYPE_DEFAULT 0x0
+#define GC_USB_DIEPCTL3_EPTYPE_OFFSET 0x960
+#define GC_USB_DIEPCTL3_STALL_LSB 0x15
+#define GC_USB_DIEPCTL3_STALL_MASK 0x200000
+#define GC_USB_DIEPCTL3_STALL_SIZE 0x1
+#define GC_USB_DIEPCTL3_STALL_DEFAULT 0x0
+#define GC_USB_DIEPCTL3_STALL_OFFSET 0x960
+#define GC_USB_DIEPCTL3_TXFNUM_LSB 0x16
+#define GC_USB_DIEPCTL3_TXFNUM_MASK 0x3c00000
+#define GC_USB_DIEPCTL3_TXFNUM_SIZE 0x4
+#define GC_USB_DIEPCTL3_TXFNUM_DEFAULT 0x0
+#define GC_USB_DIEPCTL3_TXFNUM_OFFSET 0x960
+#define GC_USB_DIEPCTL3_CNAK_LSB 0x1a
+#define GC_USB_DIEPCTL3_CNAK_MASK 0x4000000
+#define GC_USB_DIEPCTL3_CNAK_SIZE 0x1
+#define GC_USB_DIEPCTL3_CNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL3_CNAK_OFFSET 0x960
+#define GC_USB_DIEPCTL3_SNAK_LSB 0x1b
+#define GC_USB_DIEPCTL3_SNAK_MASK 0x8000000
+#define GC_USB_DIEPCTL3_SNAK_SIZE 0x1
+#define GC_USB_DIEPCTL3_SNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL3_SNAK_OFFSET 0x960
+#define GC_USB_DIEPCTL3_SETD0PID_LSB 0x1c
+#define GC_USB_DIEPCTL3_SETD0PID_MASK 0x10000000
+#define GC_USB_DIEPCTL3_SETD0PID_SIZE 0x1
+#define GC_USB_DIEPCTL3_SETD0PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL3_SETD0PID_OFFSET 0x960
+#define GC_USB_DIEPCTL3_SETD1PID_LSB 0x1d
+#define GC_USB_DIEPCTL3_SETD1PID_MASK 0x20000000
+#define GC_USB_DIEPCTL3_SETD1PID_SIZE 0x1
+#define GC_USB_DIEPCTL3_SETD1PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL3_SETD1PID_OFFSET 0x960
+#define GC_USB_DIEPCTL3_EPDIS_LSB 0x1e
+#define GC_USB_DIEPCTL3_EPDIS_MASK 0x40000000
+#define GC_USB_DIEPCTL3_EPDIS_SIZE 0x1
+#define GC_USB_DIEPCTL3_EPDIS_DEFAULT 0x0
+#define GC_USB_DIEPCTL3_EPDIS_OFFSET 0x960
+#define GC_USB_DIEPCTL3_EPENA_LSB 0x1f
+#define GC_USB_DIEPCTL3_EPENA_MASK 0x80000000
+#define GC_USB_DIEPCTL3_EPENA_SIZE 0x1
+#define GC_USB_DIEPCTL3_EPENA_DEFAULT 0x0
+#define GC_USB_DIEPCTL3_EPENA_OFFSET 0x960
+#define GC_USB_DIEPINT3_XFERCOMPL_LSB 0x0
+#define GC_USB_DIEPINT3_XFERCOMPL_MASK 0x1
+#define GC_USB_DIEPINT3_XFERCOMPL_SIZE 0x1
+#define GC_USB_DIEPINT3_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DIEPINT3_XFERCOMPL_OFFSET 0x968
+#define GC_USB_DIEPINT3_EPDISBLD_LSB 0x1
+#define GC_USB_DIEPINT3_EPDISBLD_MASK 0x2
+#define GC_USB_DIEPINT3_EPDISBLD_SIZE 0x1
+#define GC_USB_DIEPINT3_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DIEPINT3_EPDISBLD_OFFSET 0x968
+#define GC_USB_DIEPINT3_AHBERR_LSB 0x2
+#define GC_USB_DIEPINT3_AHBERR_MASK 0x4
+#define GC_USB_DIEPINT3_AHBERR_SIZE 0x1
+#define GC_USB_DIEPINT3_AHBERR_DEFAULT 0x0
+#define GC_USB_DIEPINT3_AHBERR_OFFSET 0x968
+#define GC_USB_DIEPINT3_TIMEOUT_LSB 0x3
+#define GC_USB_DIEPINT3_TIMEOUT_MASK 0x8
+#define GC_USB_DIEPINT3_TIMEOUT_SIZE 0x1
+#define GC_USB_DIEPINT3_TIMEOUT_DEFAULT 0x0
+#define GC_USB_DIEPINT3_TIMEOUT_OFFSET 0x968
+#define GC_USB_DIEPINT3_INTKNTXFEMP_LSB 0x4
+#define GC_USB_DIEPINT3_INTKNTXFEMP_MASK 0x10
+#define GC_USB_DIEPINT3_INTKNTXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT3_INTKNTXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT3_INTKNTXFEMP_OFFSET 0x968
+#define GC_USB_DIEPINT3_INTKNEPMIS_LSB 0x5
+#define GC_USB_DIEPINT3_INTKNEPMIS_MASK 0x20
+#define GC_USB_DIEPINT3_INTKNEPMIS_SIZE 0x1
+#define GC_USB_DIEPINT3_INTKNEPMIS_DEFAULT 0x0
+#define GC_USB_DIEPINT3_INTKNEPMIS_OFFSET 0x968
+#define GC_USB_DIEPINT3_INEPNAKEFF_LSB 0x6
+#define GC_USB_DIEPINT3_INEPNAKEFF_MASK 0x40
+#define GC_USB_DIEPINT3_INEPNAKEFF_SIZE 0x1
+#define GC_USB_DIEPINT3_INEPNAKEFF_DEFAULT 0x0
+#define GC_USB_DIEPINT3_INEPNAKEFF_OFFSET 0x968
+#define GC_USB_DIEPINT3_TXFEMP_LSB 0x7
+#define GC_USB_DIEPINT3_TXFEMP_MASK 0x80
+#define GC_USB_DIEPINT3_TXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT3_TXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT3_TXFEMP_OFFSET 0x968
+#define GC_USB_DIEPINT3_TXFIFOUNDRN_LSB 0x8
+#define GC_USB_DIEPINT3_TXFIFOUNDRN_MASK 0x100
+#define GC_USB_DIEPINT3_TXFIFOUNDRN_SIZE 0x1
+#define GC_USB_DIEPINT3_TXFIFOUNDRN_DEFAULT 0x0
+#define GC_USB_DIEPINT3_TXFIFOUNDRN_OFFSET 0x968
+#define GC_USB_DIEPINT3_BNAINTR_LSB 0x9
+#define GC_USB_DIEPINT3_BNAINTR_MASK 0x200
+#define GC_USB_DIEPINT3_BNAINTR_SIZE 0x1
+#define GC_USB_DIEPINT3_BNAINTR_DEFAULT 0x0
+#define GC_USB_DIEPINT3_BNAINTR_OFFSET 0x968
+#define GC_USB_DIEPINT3_PKTDRPSTS_LSB 0xb
+#define GC_USB_DIEPINT3_PKTDRPSTS_MASK 0x800
+#define GC_USB_DIEPINT3_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DIEPINT3_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DIEPINT3_PKTDRPSTS_OFFSET 0x968
+#define GC_USB_DIEPINT3_BBLEERR_LSB 0xc
+#define GC_USB_DIEPINT3_BBLEERR_MASK 0x1000
+#define GC_USB_DIEPINT3_BBLEERR_SIZE 0x1
+#define GC_USB_DIEPINT3_BBLEERR_DEFAULT 0x0
+#define GC_USB_DIEPINT3_BBLEERR_OFFSET 0x968
+#define GC_USB_DIEPINT3_NAKINTRPT_LSB 0xd
+#define GC_USB_DIEPINT3_NAKINTRPT_MASK 0x2000
+#define GC_USB_DIEPINT3_NAKINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT3_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT3_NAKINTRPT_OFFSET 0x968
+#define GC_USB_DIEPINT3_NYETINTRPT_LSB 0xe
+#define GC_USB_DIEPINT3_NYETINTRPT_MASK 0x4000
+#define GC_USB_DIEPINT3_NYETINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT3_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT3_NYETINTRPT_OFFSET 0x968
+#define GC_USB_DIEPTSIZ3_XFERSIZE_LSB 0x0
+#define GC_USB_DIEPTSIZ3_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DIEPTSIZ3_XFERSIZE_SIZE 0x13
+#define GC_USB_DIEPTSIZ3_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ3_XFERSIZE_OFFSET 0x970
+#define GC_USB_DIEPTSIZ3_PKTCNT_LSB 0x13
+#define GC_USB_DIEPTSIZ3_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DIEPTSIZ3_PKTCNT_SIZE 0xa
+#define GC_USB_DIEPTSIZ3_PKTCNT_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ3_PKTCNT_OFFSET 0x970
+#define GC_USB_DIEPTSIZ3_MC_LSB 0x1d
+#define GC_USB_DIEPTSIZ3_MC_MASK 0x60000000
+#define GC_USB_DIEPTSIZ3_MC_SIZE 0x2
+#define GC_USB_DIEPTSIZ3_MC_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ3_MC_OFFSET 0x970
+#define GC_USB_DIEPDMA3_DMAADDR_LSB 0x0
+#define GC_USB_DIEPDMA3_DMAADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMA3_DMAADDR_SIZE 0x20
+#define GC_USB_DIEPDMA3_DMAADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMA3_DMAADDR_OFFSET 0x974
+#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_LSB 0x0
+#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_MASK 0xffff
+#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_SIZE 0x10
+#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_DEFAULT 0x0
+#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_OFFSET 0x978
+#define GC_USB_DIEPDMAB3_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DIEPDMAB3_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMAB3_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DIEPDMAB3_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMAB3_DMABUFFERADDR_OFFSET 0x97c
+#define GC_USB_DIEPCTL4_MPS_LSB 0x0
+#define GC_USB_DIEPCTL4_MPS_MASK 0x7ff
+#define GC_USB_DIEPCTL4_MPS_SIZE 0xb
+#define GC_USB_DIEPCTL4_MPS_DEFAULT 0x0
+#define GC_USB_DIEPCTL4_MPS_OFFSET 0x980
+#define GC_USB_DIEPCTL4_USBACTEP_LSB 0xf
+#define GC_USB_DIEPCTL4_USBACTEP_MASK 0x8000
+#define GC_USB_DIEPCTL4_USBACTEP_SIZE 0x1
+#define GC_USB_DIEPCTL4_USBACTEP_DEFAULT 0x0
+#define GC_USB_DIEPCTL4_USBACTEP_OFFSET 0x980
+#define GC_USB_DIEPCTL4_DPID_LSB 0x10
+#define GC_USB_DIEPCTL4_DPID_MASK 0x10000
+#define GC_USB_DIEPCTL4_DPID_SIZE 0x1
+#define GC_USB_DIEPCTL4_DPID_DEFAULT 0x0
+#define GC_USB_DIEPCTL4_DPID_OFFSET 0x980
+#define GC_USB_DIEPCTL4_NAKSTS_LSB 0x11
+#define GC_USB_DIEPCTL4_NAKSTS_MASK 0x20000
+#define GC_USB_DIEPCTL4_NAKSTS_SIZE 0x1
+#define GC_USB_DIEPCTL4_NAKSTS_DEFAULT 0x0
+#define GC_USB_DIEPCTL4_NAKSTS_OFFSET 0x980
+#define GC_USB_DIEPCTL4_EPTYPE_LSB 0x12
+#define GC_USB_DIEPCTL4_EPTYPE_MASK 0xc0000
+#define GC_USB_DIEPCTL4_EPTYPE_SIZE 0x2
+#define GC_USB_DIEPCTL4_EPTYPE_DEFAULT 0x0
+#define GC_USB_DIEPCTL4_EPTYPE_OFFSET 0x980
+#define GC_USB_DIEPCTL4_STALL_LSB 0x15
+#define GC_USB_DIEPCTL4_STALL_MASK 0x200000
+#define GC_USB_DIEPCTL4_STALL_SIZE 0x1
+#define GC_USB_DIEPCTL4_STALL_DEFAULT 0x0
+#define GC_USB_DIEPCTL4_STALL_OFFSET 0x980
+#define GC_USB_DIEPCTL4_TXFNUM_LSB 0x16
+#define GC_USB_DIEPCTL4_TXFNUM_MASK 0x3c00000
+#define GC_USB_DIEPCTL4_TXFNUM_SIZE 0x4
+#define GC_USB_DIEPCTL4_TXFNUM_DEFAULT 0x0
+#define GC_USB_DIEPCTL4_TXFNUM_OFFSET 0x980
+#define GC_USB_DIEPCTL4_CNAK_LSB 0x1a
+#define GC_USB_DIEPCTL4_CNAK_MASK 0x4000000
+#define GC_USB_DIEPCTL4_CNAK_SIZE 0x1
+#define GC_USB_DIEPCTL4_CNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL4_CNAK_OFFSET 0x980
+#define GC_USB_DIEPCTL4_SNAK_LSB 0x1b
+#define GC_USB_DIEPCTL4_SNAK_MASK 0x8000000
+#define GC_USB_DIEPCTL4_SNAK_SIZE 0x1
+#define GC_USB_DIEPCTL4_SNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL4_SNAK_OFFSET 0x980
+#define GC_USB_DIEPCTL4_SETD0PID_LSB 0x1c
+#define GC_USB_DIEPCTL4_SETD0PID_MASK 0x10000000
+#define GC_USB_DIEPCTL4_SETD0PID_SIZE 0x1
+#define GC_USB_DIEPCTL4_SETD0PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL4_SETD0PID_OFFSET 0x980
+#define GC_USB_DIEPCTL4_SETD1PID_LSB 0x1d
+#define GC_USB_DIEPCTL4_SETD1PID_MASK 0x20000000
+#define GC_USB_DIEPCTL4_SETD1PID_SIZE 0x1
+#define GC_USB_DIEPCTL4_SETD1PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL4_SETD1PID_OFFSET 0x980
+#define GC_USB_DIEPCTL4_EPDIS_LSB 0x1e
+#define GC_USB_DIEPCTL4_EPDIS_MASK 0x40000000
+#define GC_USB_DIEPCTL4_EPDIS_SIZE 0x1
+#define GC_USB_DIEPCTL4_EPDIS_DEFAULT 0x0
+#define GC_USB_DIEPCTL4_EPDIS_OFFSET 0x980
+#define GC_USB_DIEPCTL4_EPENA_LSB 0x1f
+#define GC_USB_DIEPCTL4_EPENA_MASK 0x80000000
+#define GC_USB_DIEPCTL4_EPENA_SIZE 0x1
+#define GC_USB_DIEPCTL4_EPENA_DEFAULT 0x0
+#define GC_USB_DIEPCTL4_EPENA_OFFSET 0x980
+#define GC_USB_DIEPINT4_XFERCOMPL_LSB 0x0
+#define GC_USB_DIEPINT4_XFERCOMPL_MASK 0x1
+#define GC_USB_DIEPINT4_XFERCOMPL_SIZE 0x1
+#define GC_USB_DIEPINT4_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DIEPINT4_XFERCOMPL_OFFSET 0x988
+#define GC_USB_DIEPINT4_EPDISBLD_LSB 0x1
+#define GC_USB_DIEPINT4_EPDISBLD_MASK 0x2
+#define GC_USB_DIEPINT4_EPDISBLD_SIZE 0x1
+#define GC_USB_DIEPINT4_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DIEPINT4_EPDISBLD_OFFSET 0x988
+#define GC_USB_DIEPINT4_AHBERR_LSB 0x2
+#define GC_USB_DIEPINT4_AHBERR_MASK 0x4
+#define GC_USB_DIEPINT4_AHBERR_SIZE 0x1
+#define GC_USB_DIEPINT4_AHBERR_DEFAULT 0x0
+#define GC_USB_DIEPINT4_AHBERR_OFFSET 0x988
+#define GC_USB_DIEPINT4_TIMEOUT_LSB 0x3
+#define GC_USB_DIEPINT4_TIMEOUT_MASK 0x8
+#define GC_USB_DIEPINT4_TIMEOUT_SIZE 0x1
+#define GC_USB_DIEPINT4_TIMEOUT_DEFAULT 0x0
+#define GC_USB_DIEPINT4_TIMEOUT_OFFSET 0x988
+#define GC_USB_DIEPINT4_INTKNTXFEMP_LSB 0x4
+#define GC_USB_DIEPINT4_INTKNTXFEMP_MASK 0x10
+#define GC_USB_DIEPINT4_INTKNTXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT4_INTKNTXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT4_INTKNTXFEMP_OFFSET 0x988
+#define GC_USB_DIEPINT4_INTKNEPMIS_LSB 0x5
+#define GC_USB_DIEPINT4_INTKNEPMIS_MASK 0x20
+#define GC_USB_DIEPINT4_INTKNEPMIS_SIZE 0x1
+#define GC_USB_DIEPINT4_INTKNEPMIS_DEFAULT 0x0
+#define GC_USB_DIEPINT4_INTKNEPMIS_OFFSET 0x988
+#define GC_USB_DIEPINT4_INEPNAKEFF_LSB 0x6
+#define GC_USB_DIEPINT4_INEPNAKEFF_MASK 0x40
+#define GC_USB_DIEPINT4_INEPNAKEFF_SIZE 0x1
+#define GC_USB_DIEPINT4_INEPNAKEFF_DEFAULT 0x0
+#define GC_USB_DIEPINT4_INEPNAKEFF_OFFSET 0x988
+#define GC_USB_DIEPINT4_TXFEMP_LSB 0x7
+#define GC_USB_DIEPINT4_TXFEMP_MASK 0x80
+#define GC_USB_DIEPINT4_TXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT4_TXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT4_TXFEMP_OFFSET 0x988
+#define GC_USB_DIEPINT4_TXFIFOUNDRN_LSB 0x8
+#define GC_USB_DIEPINT4_TXFIFOUNDRN_MASK 0x100
+#define GC_USB_DIEPINT4_TXFIFOUNDRN_SIZE 0x1
+#define GC_USB_DIEPINT4_TXFIFOUNDRN_DEFAULT 0x0
+#define GC_USB_DIEPINT4_TXFIFOUNDRN_OFFSET 0x988
+#define GC_USB_DIEPINT4_BNAINTR_LSB 0x9
+#define GC_USB_DIEPINT4_BNAINTR_MASK 0x200
+#define GC_USB_DIEPINT4_BNAINTR_SIZE 0x1
+#define GC_USB_DIEPINT4_BNAINTR_DEFAULT 0x0
+#define GC_USB_DIEPINT4_BNAINTR_OFFSET 0x988
+#define GC_USB_DIEPINT4_PKTDRPSTS_LSB 0xb
+#define GC_USB_DIEPINT4_PKTDRPSTS_MASK 0x800
+#define GC_USB_DIEPINT4_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DIEPINT4_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DIEPINT4_PKTDRPSTS_OFFSET 0x988
+#define GC_USB_DIEPINT4_BBLEERR_LSB 0xc
+#define GC_USB_DIEPINT4_BBLEERR_MASK 0x1000
+#define GC_USB_DIEPINT4_BBLEERR_SIZE 0x1
+#define GC_USB_DIEPINT4_BBLEERR_DEFAULT 0x0
+#define GC_USB_DIEPINT4_BBLEERR_OFFSET 0x988
+#define GC_USB_DIEPINT4_NAKINTRPT_LSB 0xd
+#define GC_USB_DIEPINT4_NAKINTRPT_MASK 0x2000
+#define GC_USB_DIEPINT4_NAKINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT4_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT4_NAKINTRPT_OFFSET 0x988
+#define GC_USB_DIEPINT4_NYETINTRPT_LSB 0xe
+#define GC_USB_DIEPINT4_NYETINTRPT_MASK 0x4000
+#define GC_USB_DIEPINT4_NYETINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT4_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT4_NYETINTRPT_OFFSET 0x988
+#define GC_USB_DIEPTSIZ4_XFERSIZE_LSB 0x0
+#define GC_USB_DIEPTSIZ4_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DIEPTSIZ4_XFERSIZE_SIZE 0x13
+#define GC_USB_DIEPTSIZ4_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ4_XFERSIZE_OFFSET 0x990
+#define GC_USB_DIEPTSIZ4_PKTCNT_LSB 0x13
+#define GC_USB_DIEPTSIZ4_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DIEPTSIZ4_PKTCNT_SIZE 0xa
+#define GC_USB_DIEPTSIZ4_PKTCNT_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ4_PKTCNT_OFFSET 0x990
+#define GC_USB_DIEPTSIZ4_MC_LSB 0x1d
+#define GC_USB_DIEPTSIZ4_MC_MASK 0x60000000
+#define GC_USB_DIEPTSIZ4_MC_SIZE 0x2
+#define GC_USB_DIEPTSIZ4_MC_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ4_MC_OFFSET 0x990
+#define GC_USB_DIEPDMA4_DMAADDR_LSB 0x0
+#define GC_USB_DIEPDMA4_DMAADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMA4_DMAADDR_SIZE 0x20
+#define GC_USB_DIEPDMA4_DMAADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMA4_DMAADDR_OFFSET 0x994
+#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_LSB 0x0
+#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_MASK 0xffff
+#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_SIZE 0x10
+#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_DEFAULT 0x0
+#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_OFFSET 0x998
+#define GC_USB_DIEPDMAB4_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DIEPDMAB4_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMAB4_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DIEPDMAB4_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMAB4_DMABUFFERADDR_OFFSET 0x99c
+#define GC_USB_DIEPCTL5_MPS_LSB 0x0
+#define GC_USB_DIEPCTL5_MPS_MASK 0x7ff
+#define GC_USB_DIEPCTL5_MPS_SIZE 0xb
+#define GC_USB_DIEPCTL5_MPS_DEFAULT 0x0
+#define GC_USB_DIEPCTL5_MPS_OFFSET 0x9a0
+#define GC_USB_DIEPCTL5_USBACTEP_LSB 0xf
+#define GC_USB_DIEPCTL5_USBACTEP_MASK 0x8000
+#define GC_USB_DIEPCTL5_USBACTEP_SIZE 0x1
+#define GC_USB_DIEPCTL5_USBACTEP_DEFAULT 0x0
+#define GC_USB_DIEPCTL5_USBACTEP_OFFSET 0x9a0
+#define GC_USB_DIEPCTL5_DPID_LSB 0x10
+#define GC_USB_DIEPCTL5_DPID_MASK 0x10000
+#define GC_USB_DIEPCTL5_DPID_SIZE 0x1
+#define GC_USB_DIEPCTL5_DPID_DEFAULT 0x0
+#define GC_USB_DIEPCTL5_DPID_OFFSET 0x9a0
+#define GC_USB_DIEPCTL5_NAKSTS_LSB 0x11
+#define GC_USB_DIEPCTL5_NAKSTS_MASK 0x20000
+#define GC_USB_DIEPCTL5_NAKSTS_SIZE 0x1
+#define GC_USB_DIEPCTL5_NAKSTS_DEFAULT 0x0
+#define GC_USB_DIEPCTL5_NAKSTS_OFFSET 0x9a0
+#define GC_USB_DIEPCTL5_EPTYPE_LSB 0x12
+#define GC_USB_DIEPCTL5_EPTYPE_MASK 0xc0000
+#define GC_USB_DIEPCTL5_EPTYPE_SIZE 0x2
+#define GC_USB_DIEPCTL5_EPTYPE_DEFAULT 0x0
+#define GC_USB_DIEPCTL5_EPTYPE_OFFSET 0x9a0
+#define GC_USB_DIEPCTL5_STALL_LSB 0x15
+#define GC_USB_DIEPCTL5_STALL_MASK 0x200000
+#define GC_USB_DIEPCTL5_STALL_SIZE 0x1
+#define GC_USB_DIEPCTL5_STALL_DEFAULT 0x0
+#define GC_USB_DIEPCTL5_STALL_OFFSET 0x9a0
+#define GC_USB_DIEPCTL5_TXFNUM_LSB 0x16
+#define GC_USB_DIEPCTL5_TXFNUM_MASK 0x3c00000
+#define GC_USB_DIEPCTL5_TXFNUM_SIZE 0x4
+#define GC_USB_DIEPCTL5_TXFNUM_DEFAULT 0x0
+#define GC_USB_DIEPCTL5_TXFNUM_OFFSET 0x9a0
+#define GC_USB_DIEPCTL5_CNAK_LSB 0x1a
+#define GC_USB_DIEPCTL5_CNAK_MASK 0x4000000
+#define GC_USB_DIEPCTL5_CNAK_SIZE 0x1
+#define GC_USB_DIEPCTL5_CNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL5_CNAK_OFFSET 0x9a0
+#define GC_USB_DIEPCTL5_SNAK_LSB 0x1b
+#define GC_USB_DIEPCTL5_SNAK_MASK 0x8000000
+#define GC_USB_DIEPCTL5_SNAK_SIZE 0x1
+#define GC_USB_DIEPCTL5_SNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL5_SNAK_OFFSET 0x9a0
+#define GC_USB_DIEPCTL5_SETD0PID_LSB 0x1c
+#define GC_USB_DIEPCTL5_SETD0PID_MASK 0x10000000
+#define GC_USB_DIEPCTL5_SETD0PID_SIZE 0x1
+#define GC_USB_DIEPCTL5_SETD0PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL5_SETD0PID_OFFSET 0x9a0
+#define GC_USB_DIEPCTL5_SETD1PID_LSB 0x1d
+#define GC_USB_DIEPCTL5_SETD1PID_MASK 0x20000000
+#define GC_USB_DIEPCTL5_SETD1PID_SIZE 0x1
+#define GC_USB_DIEPCTL5_SETD1PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL5_SETD1PID_OFFSET 0x9a0
+#define GC_USB_DIEPCTL5_EPDIS_LSB 0x1e
+#define GC_USB_DIEPCTL5_EPDIS_MASK 0x40000000
+#define GC_USB_DIEPCTL5_EPDIS_SIZE 0x1
+#define GC_USB_DIEPCTL5_EPDIS_DEFAULT 0x0
+#define GC_USB_DIEPCTL5_EPDIS_OFFSET 0x9a0
+#define GC_USB_DIEPCTL5_EPENA_LSB 0x1f
+#define GC_USB_DIEPCTL5_EPENA_MASK 0x80000000
+#define GC_USB_DIEPCTL5_EPENA_SIZE 0x1
+#define GC_USB_DIEPCTL5_EPENA_DEFAULT 0x0
+#define GC_USB_DIEPCTL5_EPENA_OFFSET 0x9a0
+#define GC_USB_DIEPINT5_XFERCOMPL_LSB 0x0
+#define GC_USB_DIEPINT5_XFERCOMPL_MASK 0x1
+#define GC_USB_DIEPINT5_XFERCOMPL_SIZE 0x1
+#define GC_USB_DIEPINT5_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DIEPINT5_XFERCOMPL_OFFSET 0x9a8
+#define GC_USB_DIEPINT5_EPDISBLD_LSB 0x1
+#define GC_USB_DIEPINT5_EPDISBLD_MASK 0x2
+#define GC_USB_DIEPINT5_EPDISBLD_SIZE 0x1
+#define GC_USB_DIEPINT5_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DIEPINT5_EPDISBLD_OFFSET 0x9a8
+#define GC_USB_DIEPINT5_AHBERR_LSB 0x2
+#define GC_USB_DIEPINT5_AHBERR_MASK 0x4
+#define GC_USB_DIEPINT5_AHBERR_SIZE 0x1
+#define GC_USB_DIEPINT5_AHBERR_DEFAULT 0x0
+#define GC_USB_DIEPINT5_AHBERR_OFFSET 0x9a8
+#define GC_USB_DIEPINT5_TIMEOUT_LSB 0x3
+#define GC_USB_DIEPINT5_TIMEOUT_MASK 0x8
+#define GC_USB_DIEPINT5_TIMEOUT_SIZE 0x1
+#define GC_USB_DIEPINT5_TIMEOUT_DEFAULT 0x0
+#define GC_USB_DIEPINT5_TIMEOUT_OFFSET 0x9a8
+#define GC_USB_DIEPINT5_INTKNTXFEMP_LSB 0x4
+#define GC_USB_DIEPINT5_INTKNTXFEMP_MASK 0x10
+#define GC_USB_DIEPINT5_INTKNTXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT5_INTKNTXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT5_INTKNTXFEMP_OFFSET 0x9a8
+#define GC_USB_DIEPINT5_INTKNEPMIS_LSB 0x5
+#define GC_USB_DIEPINT5_INTKNEPMIS_MASK 0x20
+#define GC_USB_DIEPINT5_INTKNEPMIS_SIZE 0x1
+#define GC_USB_DIEPINT5_INTKNEPMIS_DEFAULT 0x0
+#define GC_USB_DIEPINT5_INTKNEPMIS_OFFSET 0x9a8
+#define GC_USB_DIEPINT5_INEPNAKEFF_LSB 0x6
+#define GC_USB_DIEPINT5_INEPNAKEFF_MASK 0x40
+#define GC_USB_DIEPINT5_INEPNAKEFF_SIZE 0x1
+#define GC_USB_DIEPINT5_INEPNAKEFF_DEFAULT 0x0
+#define GC_USB_DIEPINT5_INEPNAKEFF_OFFSET 0x9a8
+#define GC_USB_DIEPINT5_TXFEMP_LSB 0x7
+#define GC_USB_DIEPINT5_TXFEMP_MASK 0x80
+#define GC_USB_DIEPINT5_TXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT5_TXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT5_TXFEMP_OFFSET 0x9a8
+#define GC_USB_DIEPINT5_TXFIFOUNDRN_LSB 0x8
+#define GC_USB_DIEPINT5_TXFIFOUNDRN_MASK 0x100
+#define GC_USB_DIEPINT5_TXFIFOUNDRN_SIZE 0x1
+#define GC_USB_DIEPINT5_TXFIFOUNDRN_DEFAULT 0x0
+#define GC_USB_DIEPINT5_TXFIFOUNDRN_OFFSET 0x9a8
+#define GC_USB_DIEPINT5_BNAINTR_LSB 0x9
+#define GC_USB_DIEPINT5_BNAINTR_MASK 0x200
+#define GC_USB_DIEPINT5_BNAINTR_SIZE 0x1
+#define GC_USB_DIEPINT5_BNAINTR_DEFAULT 0x0
+#define GC_USB_DIEPINT5_BNAINTR_OFFSET 0x9a8
+#define GC_USB_DIEPINT5_PKTDRPSTS_LSB 0xb
+#define GC_USB_DIEPINT5_PKTDRPSTS_MASK 0x800
+#define GC_USB_DIEPINT5_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DIEPINT5_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DIEPINT5_PKTDRPSTS_OFFSET 0x9a8
+#define GC_USB_DIEPINT5_BBLEERR_LSB 0xc
+#define GC_USB_DIEPINT5_BBLEERR_MASK 0x1000
+#define GC_USB_DIEPINT5_BBLEERR_SIZE 0x1
+#define GC_USB_DIEPINT5_BBLEERR_DEFAULT 0x0
+#define GC_USB_DIEPINT5_BBLEERR_OFFSET 0x9a8
+#define GC_USB_DIEPINT5_NAKINTRPT_LSB 0xd
+#define GC_USB_DIEPINT5_NAKINTRPT_MASK 0x2000
+#define GC_USB_DIEPINT5_NAKINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT5_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT5_NAKINTRPT_OFFSET 0x9a8
+#define GC_USB_DIEPINT5_NYETINTRPT_LSB 0xe
+#define GC_USB_DIEPINT5_NYETINTRPT_MASK 0x4000
+#define GC_USB_DIEPINT5_NYETINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT5_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT5_NYETINTRPT_OFFSET 0x9a8
+#define GC_USB_DIEPTSIZ5_XFERSIZE_LSB 0x0
+#define GC_USB_DIEPTSIZ5_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DIEPTSIZ5_XFERSIZE_SIZE 0x13
+#define GC_USB_DIEPTSIZ5_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ5_XFERSIZE_OFFSET 0x9b0
+#define GC_USB_DIEPTSIZ5_PKTCNT_LSB 0x13
+#define GC_USB_DIEPTSIZ5_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DIEPTSIZ5_PKTCNT_SIZE 0xa
+#define GC_USB_DIEPTSIZ5_PKTCNT_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ5_PKTCNT_OFFSET 0x9b0
+#define GC_USB_DIEPTSIZ5_MC_LSB 0x1d
+#define GC_USB_DIEPTSIZ5_MC_MASK 0x60000000
+#define GC_USB_DIEPTSIZ5_MC_SIZE 0x2
+#define GC_USB_DIEPTSIZ5_MC_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ5_MC_OFFSET 0x9b0
+#define GC_USB_DIEPDMA5_DMAADDR_LSB 0x0
+#define GC_USB_DIEPDMA5_DMAADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMA5_DMAADDR_SIZE 0x20
+#define GC_USB_DIEPDMA5_DMAADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMA5_DMAADDR_OFFSET 0x9b4
+#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_LSB 0x0
+#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_MASK 0xffff
+#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_SIZE 0x10
+#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_DEFAULT 0x0
+#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_OFFSET 0x9b8
+#define GC_USB_DIEPDMAB5_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DIEPDMAB5_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMAB5_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DIEPDMAB5_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMAB5_DMABUFFERADDR_OFFSET 0x9bc
+#define GC_USB_DIEPCTL6_MPS_LSB 0x0
+#define GC_USB_DIEPCTL6_MPS_MASK 0x7ff
+#define GC_USB_DIEPCTL6_MPS_SIZE 0xb
+#define GC_USB_DIEPCTL6_MPS_DEFAULT 0x0
+#define GC_USB_DIEPCTL6_MPS_OFFSET 0x9c0
+#define GC_USB_DIEPCTL6_USBACTEP_LSB 0xf
+#define GC_USB_DIEPCTL6_USBACTEP_MASK 0x8000
+#define GC_USB_DIEPCTL6_USBACTEP_SIZE 0x1
+#define GC_USB_DIEPCTL6_USBACTEP_DEFAULT 0x0
+#define GC_USB_DIEPCTL6_USBACTEP_OFFSET 0x9c0
+#define GC_USB_DIEPCTL6_DPID_LSB 0x10
+#define GC_USB_DIEPCTL6_DPID_MASK 0x10000
+#define GC_USB_DIEPCTL6_DPID_SIZE 0x1
+#define GC_USB_DIEPCTL6_DPID_DEFAULT 0x0
+#define GC_USB_DIEPCTL6_DPID_OFFSET 0x9c0
+#define GC_USB_DIEPCTL6_NAKSTS_LSB 0x11
+#define GC_USB_DIEPCTL6_NAKSTS_MASK 0x20000
+#define GC_USB_DIEPCTL6_NAKSTS_SIZE 0x1
+#define GC_USB_DIEPCTL6_NAKSTS_DEFAULT 0x0
+#define GC_USB_DIEPCTL6_NAKSTS_OFFSET 0x9c0
+#define GC_USB_DIEPCTL6_EPTYPE_LSB 0x12
+#define GC_USB_DIEPCTL6_EPTYPE_MASK 0xc0000
+#define GC_USB_DIEPCTL6_EPTYPE_SIZE 0x2
+#define GC_USB_DIEPCTL6_EPTYPE_DEFAULT 0x0
+#define GC_USB_DIEPCTL6_EPTYPE_OFFSET 0x9c0
+#define GC_USB_DIEPCTL6_STALL_LSB 0x15
+#define GC_USB_DIEPCTL6_STALL_MASK 0x200000
+#define GC_USB_DIEPCTL6_STALL_SIZE 0x1
+#define GC_USB_DIEPCTL6_STALL_DEFAULT 0x0
+#define GC_USB_DIEPCTL6_STALL_OFFSET 0x9c0
+#define GC_USB_DIEPCTL6_TXFNUM_LSB 0x16
+#define GC_USB_DIEPCTL6_TXFNUM_MASK 0x3c00000
+#define GC_USB_DIEPCTL6_TXFNUM_SIZE 0x4
+#define GC_USB_DIEPCTL6_TXFNUM_DEFAULT 0x0
+#define GC_USB_DIEPCTL6_TXFNUM_OFFSET 0x9c0
+#define GC_USB_DIEPCTL6_CNAK_LSB 0x1a
+#define GC_USB_DIEPCTL6_CNAK_MASK 0x4000000
+#define GC_USB_DIEPCTL6_CNAK_SIZE 0x1
+#define GC_USB_DIEPCTL6_CNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL6_CNAK_OFFSET 0x9c0
+#define GC_USB_DIEPCTL6_SNAK_LSB 0x1b
+#define GC_USB_DIEPCTL6_SNAK_MASK 0x8000000
+#define GC_USB_DIEPCTL6_SNAK_SIZE 0x1
+#define GC_USB_DIEPCTL6_SNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL6_SNAK_OFFSET 0x9c0
+#define GC_USB_DIEPCTL6_SETD0PID_LSB 0x1c
+#define GC_USB_DIEPCTL6_SETD0PID_MASK 0x10000000
+#define GC_USB_DIEPCTL6_SETD0PID_SIZE 0x1
+#define GC_USB_DIEPCTL6_SETD0PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL6_SETD0PID_OFFSET 0x9c0
+#define GC_USB_DIEPCTL6_SETD1PID_LSB 0x1d
+#define GC_USB_DIEPCTL6_SETD1PID_MASK 0x20000000
+#define GC_USB_DIEPCTL6_SETD1PID_SIZE 0x1
+#define GC_USB_DIEPCTL6_SETD1PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL6_SETD1PID_OFFSET 0x9c0
+#define GC_USB_DIEPCTL6_EPDIS_LSB 0x1e
+#define GC_USB_DIEPCTL6_EPDIS_MASK 0x40000000
+#define GC_USB_DIEPCTL6_EPDIS_SIZE 0x1
+#define GC_USB_DIEPCTL6_EPDIS_DEFAULT 0x0
+#define GC_USB_DIEPCTL6_EPDIS_OFFSET 0x9c0
+#define GC_USB_DIEPCTL6_EPENA_LSB 0x1f
+#define GC_USB_DIEPCTL6_EPENA_MASK 0x80000000
+#define GC_USB_DIEPCTL6_EPENA_SIZE 0x1
+#define GC_USB_DIEPCTL6_EPENA_DEFAULT 0x0
+#define GC_USB_DIEPCTL6_EPENA_OFFSET 0x9c0
+#define GC_USB_DIEPINT6_XFERCOMPL_LSB 0x0
+#define GC_USB_DIEPINT6_XFERCOMPL_MASK 0x1
+#define GC_USB_DIEPINT6_XFERCOMPL_SIZE 0x1
+#define GC_USB_DIEPINT6_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DIEPINT6_XFERCOMPL_OFFSET 0x9c8
+#define GC_USB_DIEPINT6_EPDISBLD_LSB 0x1
+#define GC_USB_DIEPINT6_EPDISBLD_MASK 0x2
+#define GC_USB_DIEPINT6_EPDISBLD_SIZE 0x1
+#define GC_USB_DIEPINT6_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DIEPINT6_EPDISBLD_OFFSET 0x9c8
+#define GC_USB_DIEPINT6_AHBERR_LSB 0x2
+#define GC_USB_DIEPINT6_AHBERR_MASK 0x4
+#define GC_USB_DIEPINT6_AHBERR_SIZE 0x1
+#define GC_USB_DIEPINT6_AHBERR_DEFAULT 0x0
+#define GC_USB_DIEPINT6_AHBERR_OFFSET 0x9c8
+#define GC_USB_DIEPINT6_TIMEOUT_LSB 0x3
+#define GC_USB_DIEPINT6_TIMEOUT_MASK 0x8
+#define GC_USB_DIEPINT6_TIMEOUT_SIZE 0x1
+#define GC_USB_DIEPINT6_TIMEOUT_DEFAULT 0x0
+#define GC_USB_DIEPINT6_TIMEOUT_OFFSET 0x9c8
+#define GC_USB_DIEPINT6_INTKNTXFEMP_LSB 0x4
+#define GC_USB_DIEPINT6_INTKNTXFEMP_MASK 0x10
+#define GC_USB_DIEPINT6_INTKNTXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT6_INTKNTXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT6_INTKNTXFEMP_OFFSET 0x9c8
+#define GC_USB_DIEPINT6_INTKNEPMIS_LSB 0x5
+#define GC_USB_DIEPINT6_INTKNEPMIS_MASK 0x20
+#define GC_USB_DIEPINT6_INTKNEPMIS_SIZE 0x1
+#define GC_USB_DIEPINT6_INTKNEPMIS_DEFAULT 0x0
+#define GC_USB_DIEPINT6_INTKNEPMIS_OFFSET 0x9c8
+#define GC_USB_DIEPINT6_INEPNAKEFF_LSB 0x6
+#define GC_USB_DIEPINT6_INEPNAKEFF_MASK 0x40
+#define GC_USB_DIEPINT6_INEPNAKEFF_SIZE 0x1
+#define GC_USB_DIEPINT6_INEPNAKEFF_DEFAULT 0x0
+#define GC_USB_DIEPINT6_INEPNAKEFF_OFFSET 0x9c8
+#define GC_USB_DIEPINT6_TXFEMP_LSB 0x7
+#define GC_USB_DIEPINT6_TXFEMP_MASK 0x80
+#define GC_USB_DIEPINT6_TXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT6_TXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT6_TXFEMP_OFFSET 0x9c8
+#define GC_USB_DIEPINT6_TXFIFOUNDRN_LSB 0x8
+#define GC_USB_DIEPINT6_TXFIFOUNDRN_MASK 0x100
+#define GC_USB_DIEPINT6_TXFIFOUNDRN_SIZE 0x1
+#define GC_USB_DIEPINT6_TXFIFOUNDRN_DEFAULT 0x0
+#define GC_USB_DIEPINT6_TXFIFOUNDRN_OFFSET 0x9c8
+#define GC_USB_DIEPINT6_BNAINTR_LSB 0x9
+#define GC_USB_DIEPINT6_BNAINTR_MASK 0x200
+#define GC_USB_DIEPINT6_BNAINTR_SIZE 0x1
+#define GC_USB_DIEPINT6_BNAINTR_DEFAULT 0x0
+#define GC_USB_DIEPINT6_BNAINTR_OFFSET 0x9c8
+#define GC_USB_DIEPINT6_PKTDRPSTS_LSB 0xb
+#define GC_USB_DIEPINT6_PKTDRPSTS_MASK 0x800
+#define GC_USB_DIEPINT6_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DIEPINT6_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DIEPINT6_PKTDRPSTS_OFFSET 0x9c8
+#define GC_USB_DIEPINT6_BBLEERR_LSB 0xc
+#define GC_USB_DIEPINT6_BBLEERR_MASK 0x1000
+#define GC_USB_DIEPINT6_BBLEERR_SIZE 0x1
+#define GC_USB_DIEPINT6_BBLEERR_DEFAULT 0x0
+#define GC_USB_DIEPINT6_BBLEERR_OFFSET 0x9c8
+#define GC_USB_DIEPINT6_NAKINTRPT_LSB 0xd
+#define GC_USB_DIEPINT6_NAKINTRPT_MASK 0x2000
+#define GC_USB_DIEPINT6_NAKINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT6_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT6_NAKINTRPT_OFFSET 0x9c8
+#define GC_USB_DIEPINT6_NYETINTRPT_LSB 0xe
+#define GC_USB_DIEPINT6_NYETINTRPT_MASK 0x4000
+#define GC_USB_DIEPINT6_NYETINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT6_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT6_NYETINTRPT_OFFSET 0x9c8
+#define GC_USB_DIEPTSIZ6_XFERSIZE_LSB 0x0
+#define GC_USB_DIEPTSIZ6_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DIEPTSIZ6_XFERSIZE_SIZE 0x13
+#define GC_USB_DIEPTSIZ6_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ6_XFERSIZE_OFFSET 0x9d0
+#define GC_USB_DIEPTSIZ6_PKTCNT_LSB 0x13
+#define GC_USB_DIEPTSIZ6_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DIEPTSIZ6_PKTCNT_SIZE 0xa
+#define GC_USB_DIEPTSIZ6_PKTCNT_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ6_PKTCNT_OFFSET 0x9d0
+#define GC_USB_DIEPTSIZ6_MC_LSB 0x1d
+#define GC_USB_DIEPTSIZ6_MC_MASK 0x60000000
+#define GC_USB_DIEPTSIZ6_MC_SIZE 0x2
+#define GC_USB_DIEPTSIZ6_MC_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ6_MC_OFFSET 0x9d0
+#define GC_USB_DIEPDMA6_DMAADDR_LSB 0x0
+#define GC_USB_DIEPDMA6_DMAADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMA6_DMAADDR_SIZE 0x20
+#define GC_USB_DIEPDMA6_DMAADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMA6_DMAADDR_OFFSET 0x9d4
+#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_LSB 0x0
+#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_MASK 0xffff
+#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_SIZE 0x10
+#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_DEFAULT 0x0
+#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_OFFSET 0x9d8
+#define GC_USB_DIEPDMAB6_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DIEPDMAB6_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMAB6_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DIEPDMAB6_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMAB6_DMABUFFERADDR_OFFSET 0x9dc
+#define GC_USB_DIEPCTL7_MPS_LSB 0x0
+#define GC_USB_DIEPCTL7_MPS_MASK 0x7ff
+#define GC_USB_DIEPCTL7_MPS_SIZE 0xb
+#define GC_USB_DIEPCTL7_MPS_DEFAULT 0x0
+#define GC_USB_DIEPCTL7_MPS_OFFSET 0x9e0
+#define GC_USB_DIEPCTL7_USBACTEP_LSB 0xf
+#define GC_USB_DIEPCTL7_USBACTEP_MASK 0x8000
+#define GC_USB_DIEPCTL7_USBACTEP_SIZE 0x1
+#define GC_USB_DIEPCTL7_USBACTEP_DEFAULT 0x0
+#define GC_USB_DIEPCTL7_USBACTEP_OFFSET 0x9e0
+#define GC_USB_DIEPCTL7_DPID_LSB 0x10
+#define GC_USB_DIEPCTL7_DPID_MASK 0x10000
+#define GC_USB_DIEPCTL7_DPID_SIZE 0x1
+#define GC_USB_DIEPCTL7_DPID_DEFAULT 0x0
+#define GC_USB_DIEPCTL7_DPID_OFFSET 0x9e0
+#define GC_USB_DIEPCTL7_NAKSTS_LSB 0x11
+#define GC_USB_DIEPCTL7_NAKSTS_MASK 0x20000
+#define GC_USB_DIEPCTL7_NAKSTS_SIZE 0x1
+#define GC_USB_DIEPCTL7_NAKSTS_DEFAULT 0x0
+#define GC_USB_DIEPCTL7_NAKSTS_OFFSET 0x9e0
+#define GC_USB_DIEPCTL7_EPTYPE_LSB 0x12
+#define GC_USB_DIEPCTL7_EPTYPE_MASK 0xc0000
+#define GC_USB_DIEPCTL7_EPTYPE_SIZE 0x2
+#define GC_USB_DIEPCTL7_EPTYPE_DEFAULT 0x0
+#define GC_USB_DIEPCTL7_EPTYPE_OFFSET 0x9e0
+#define GC_USB_DIEPCTL7_STALL_LSB 0x15
+#define GC_USB_DIEPCTL7_STALL_MASK 0x200000
+#define GC_USB_DIEPCTL7_STALL_SIZE 0x1
+#define GC_USB_DIEPCTL7_STALL_DEFAULT 0x0
+#define GC_USB_DIEPCTL7_STALL_OFFSET 0x9e0
+#define GC_USB_DIEPCTL7_TXFNUM_LSB 0x16
+#define GC_USB_DIEPCTL7_TXFNUM_MASK 0x3c00000
+#define GC_USB_DIEPCTL7_TXFNUM_SIZE 0x4
+#define GC_USB_DIEPCTL7_TXFNUM_DEFAULT 0x0
+#define GC_USB_DIEPCTL7_TXFNUM_OFFSET 0x9e0
+#define GC_USB_DIEPCTL7_CNAK_LSB 0x1a
+#define GC_USB_DIEPCTL7_CNAK_MASK 0x4000000
+#define GC_USB_DIEPCTL7_CNAK_SIZE 0x1
+#define GC_USB_DIEPCTL7_CNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL7_CNAK_OFFSET 0x9e0
+#define GC_USB_DIEPCTL7_SNAK_LSB 0x1b
+#define GC_USB_DIEPCTL7_SNAK_MASK 0x8000000
+#define GC_USB_DIEPCTL7_SNAK_SIZE 0x1
+#define GC_USB_DIEPCTL7_SNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL7_SNAK_OFFSET 0x9e0
+#define GC_USB_DIEPCTL7_SETD0PID_LSB 0x1c
+#define GC_USB_DIEPCTL7_SETD0PID_MASK 0x10000000
+#define GC_USB_DIEPCTL7_SETD0PID_SIZE 0x1
+#define GC_USB_DIEPCTL7_SETD0PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL7_SETD0PID_OFFSET 0x9e0
+#define GC_USB_DIEPCTL7_SETD1PID_LSB 0x1d
+#define GC_USB_DIEPCTL7_SETD1PID_MASK 0x20000000
+#define GC_USB_DIEPCTL7_SETD1PID_SIZE 0x1
+#define GC_USB_DIEPCTL7_SETD1PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL7_SETD1PID_OFFSET 0x9e0
+#define GC_USB_DIEPCTL7_EPDIS_LSB 0x1e
+#define GC_USB_DIEPCTL7_EPDIS_MASK 0x40000000
+#define GC_USB_DIEPCTL7_EPDIS_SIZE 0x1
+#define GC_USB_DIEPCTL7_EPDIS_DEFAULT 0x0
+#define GC_USB_DIEPCTL7_EPDIS_OFFSET 0x9e0
+#define GC_USB_DIEPCTL7_EPENA_LSB 0x1f
+#define GC_USB_DIEPCTL7_EPENA_MASK 0x80000000
+#define GC_USB_DIEPCTL7_EPENA_SIZE 0x1
+#define GC_USB_DIEPCTL7_EPENA_DEFAULT 0x0
+#define GC_USB_DIEPCTL7_EPENA_OFFSET 0x9e0
+#define GC_USB_DIEPINT7_XFERCOMPL_LSB 0x0
+#define GC_USB_DIEPINT7_XFERCOMPL_MASK 0x1
+#define GC_USB_DIEPINT7_XFERCOMPL_SIZE 0x1
+#define GC_USB_DIEPINT7_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DIEPINT7_XFERCOMPL_OFFSET 0x9e8
+#define GC_USB_DIEPINT7_EPDISBLD_LSB 0x1
+#define GC_USB_DIEPINT7_EPDISBLD_MASK 0x2
+#define GC_USB_DIEPINT7_EPDISBLD_SIZE 0x1
+#define GC_USB_DIEPINT7_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DIEPINT7_EPDISBLD_OFFSET 0x9e8
+#define GC_USB_DIEPINT7_AHBERR_LSB 0x2
+#define GC_USB_DIEPINT7_AHBERR_MASK 0x4
+#define GC_USB_DIEPINT7_AHBERR_SIZE 0x1
+#define GC_USB_DIEPINT7_AHBERR_DEFAULT 0x0
+#define GC_USB_DIEPINT7_AHBERR_OFFSET 0x9e8
+#define GC_USB_DIEPINT7_TIMEOUT_LSB 0x3
+#define GC_USB_DIEPINT7_TIMEOUT_MASK 0x8
+#define GC_USB_DIEPINT7_TIMEOUT_SIZE 0x1
+#define GC_USB_DIEPINT7_TIMEOUT_DEFAULT 0x0
+#define GC_USB_DIEPINT7_TIMEOUT_OFFSET 0x9e8
+#define GC_USB_DIEPINT7_INTKNTXFEMP_LSB 0x4
+#define GC_USB_DIEPINT7_INTKNTXFEMP_MASK 0x10
+#define GC_USB_DIEPINT7_INTKNTXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT7_INTKNTXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT7_INTKNTXFEMP_OFFSET 0x9e8
+#define GC_USB_DIEPINT7_INTKNEPMIS_LSB 0x5
+#define GC_USB_DIEPINT7_INTKNEPMIS_MASK 0x20
+#define GC_USB_DIEPINT7_INTKNEPMIS_SIZE 0x1
+#define GC_USB_DIEPINT7_INTKNEPMIS_DEFAULT 0x0
+#define GC_USB_DIEPINT7_INTKNEPMIS_OFFSET 0x9e8
+#define GC_USB_DIEPINT7_INEPNAKEFF_LSB 0x6
+#define GC_USB_DIEPINT7_INEPNAKEFF_MASK 0x40
+#define GC_USB_DIEPINT7_INEPNAKEFF_SIZE 0x1
+#define GC_USB_DIEPINT7_INEPNAKEFF_DEFAULT 0x0
+#define GC_USB_DIEPINT7_INEPNAKEFF_OFFSET 0x9e8
+#define GC_USB_DIEPINT7_TXFEMP_LSB 0x7
+#define GC_USB_DIEPINT7_TXFEMP_MASK 0x80
+#define GC_USB_DIEPINT7_TXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT7_TXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT7_TXFEMP_OFFSET 0x9e8
+#define GC_USB_DIEPINT7_TXFIFOUNDRN_LSB 0x8
+#define GC_USB_DIEPINT7_TXFIFOUNDRN_MASK 0x100
+#define GC_USB_DIEPINT7_TXFIFOUNDRN_SIZE 0x1
+#define GC_USB_DIEPINT7_TXFIFOUNDRN_DEFAULT 0x0
+#define GC_USB_DIEPINT7_TXFIFOUNDRN_OFFSET 0x9e8
+#define GC_USB_DIEPINT7_BNAINTR_LSB 0x9
+#define GC_USB_DIEPINT7_BNAINTR_MASK 0x200
+#define GC_USB_DIEPINT7_BNAINTR_SIZE 0x1
+#define GC_USB_DIEPINT7_BNAINTR_DEFAULT 0x0
+#define GC_USB_DIEPINT7_BNAINTR_OFFSET 0x9e8
+#define GC_USB_DIEPINT7_PKTDRPSTS_LSB 0xb
+#define GC_USB_DIEPINT7_PKTDRPSTS_MASK 0x800
+#define GC_USB_DIEPINT7_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DIEPINT7_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DIEPINT7_PKTDRPSTS_OFFSET 0x9e8
+#define GC_USB_DIEPINT7_BBLEERR_LSB 0xc
+#define GC_USB_DIEPINT7_BBLEERR_MASK 0x1000
+#define GC_USB_DIEPINT7_BBLEERR_SIZE 0x1
+#define GC_USB_DIEPINT7_BBLEERR_DEFAULT 0x0
+#define GC_USB_DIEPINT7_BBLEERR_OFFSET 0x9e8
+#define GC_USB_DIEPINT7_NAKINTRPT_LSB 0xd
+#define GC_USB_DIEPINT7_NAKINTRPT_MASK 0x2000
+#define GC_USB_DIEPINT7_NAKINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT7_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT7_NAKINTRPT_OFFSET 0x9e8
+#define GC_USB_DIEPINT7_NYETINTRPT_LSB 0xe
+#define GC_USB_DIEPINT7_NYETINTRPT_MASK 0x4000
+#define GC_USB_DIEPINT7_NYETINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT7_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT7_NYETINTRPT_OFFSET 0x9e8
+#define GC_USB_DIEPTSIZ7_XFERSIZE_LSB 0x0
+#define GC_USB_DIEPTSIZ7_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DIEPTSIZ7_XFERSIZE_SIZE 0x13
+#define GC_USB_DIEPTSIZ7_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ7_XFERSIZE_OFFSET 0x9f0
+#define GC_USB_DIEPTSIZ7_PKTCNT_LSB 0x13
+#define GC_USB_DIEPTSIZ7_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DIEPTSIZ7_PKTCNT_SIZE 0xa
+#define GC_USB_DIEPTSIZ7_PKTCNT_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ7_PKTCNT_OFFSET 0x9f0
+#define GC_USB_DIEPTSIZ7_MC_LSB 0x1d
+#define GC_USB_DIEPTSIZ7_MC_MASK 0x60000000
+#define GC_USB_DIEPTSIZ7_MC_SIZE 0x2
+#define GC_USB_DIEPTSIZ7_MC_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ7_MC_OFFSET 0x9f0
+#define GC_USB_DIEPDMA7_DMAADDR_LSB 0x0
+#define GC_USB_DIEPDMA7_DMAADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMA7_DMAADDR_SIZE 0x20
+#define GC_USB_DIEPDMA7_DMAADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMA7_DMAADDR_OFFSET 0x9f4
+#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_LSB 0x0
+#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_MASK 0xffff
+#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_SIZE 0x10
+#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_DEFAULT 0x0
+#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_OFFSET 0x9f8
+#define GC_USB_DIEPDMAB7_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DIEPDMAB7_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMAB7_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DIEPDMAB7_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMAB7_DMABUFFERADDR_OFFSET 0x9fc
+#define GC_USB_DIEPCTL8_MPS_LSB 0x0
+#define GC_USB_DIEPCTL8_MPS_MASK 0x7ff
+#define GC_USB_DIEPCTL8_MPS_SIZE 0xb
+#define GC_USB_DIEPCTL8_MPS_DEFAULT 0x0
+#define GC_USB_DIEPCTL8_MPS_OFFSET 0xa00
+#define GC_USB_DIEPCTL8_USBACTEP_LSB 0xf
+#define GC_USB_DIEPCTL8_USBACTEP_MASK 0x8000
+#define GC_USB_DIEPCTL8_USBACTEP_SIZE 0x1
+#define GC_USB_DIEPCTL8_USBACTEP_DEFAULT 0x0
+#define GC_USB_DIEPCTL8_USBACTEP_OFFSET 0xa00
+#define GC_USB_DIEPCTL8_DPID_LSB 0x10
+#define GC_USB_DIEPCTL8_DPID_MASK 0x10000
+#define GC_USB_DIEPCTL8_DPID_SIZE 0x1
+#define GC_USB_DIEPCTL8_DPID_DEFAULT 0x0
+#define GC_USB_DIEPCTL8_DPID_OFFSET 0xa00
+#define GC_USB_DIEPCTL8_NAKSTS_LSB 0x11
+#define GC_USB_DIEPCTL8_NAKSTS_MASK 0x20000
+#define GC_USB_DIEPCTL8_NAKSTS_SIZE 0x1
+#define GC_USB_DIEPCTL8_NAKSTS_DEFAULT 0x0
+#define GC_USB_DIEPCTL8_NAKSTS_OFFSET 0xa00
+#define GC_USB_DIEPCTL8_EPTYPE_LSB 0x12
+#define GC_USB_DIEPCTL8_EPTYPE_MASK 0xc0000
+#define GC_USB_DIEPCTL8_EPTYPE_SIZE 0x2
+#define GC_USB_DIEPCTL8_EPTYPE_DEFAULT 0x0
+#define GC_USB_DIEPCTL8_EPTYPE_OFFSET 0xa00
+#define GC_USB_DIEPCTL8_STALL_LSB 0x15
+#define GC_USB_DIEPCTL8_STALL_MASK 0x200000
+#define GC_USB_DIEPCTL8_STALL_SIZE 0x1
+#define GC_USB_DIEPCTL8_STALL_DEFAULT 0x0
+#define GC_USB_DIEPCTL8_STALL_OFFSET 0xa00
+#define GC_USB_DIEPCTL8_TXFNUM_LSB 0x16
+#define GC_USB_DIEPCTL8_TXFNUM_MASK 0x3c00000
+#define GC_USB_DIEPCTL8_TXFNUM_SIZE 0x4
+#define GC_USB_DIEPCTL8_TXFNUM_DEFAULT 0x0
+#define GC_USB_DIEPCTL8_TXFNUM_OFFSET 0xa00
+#define GC_USB_DIEPCTL8_CNAK_LSB 0x1a
+#define GC_USB_DIEPCTL8_CNAK_MASK 0x4000000
+#define GC_USB_DIEPCTL8_CNAK_SIZE 0x1
+#define GC_USB_DIEPCTL8_CNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL8_CNAK_OFFSET 0xa00
+#define GC_USB_DIEPCTL8_SNAK_LSB 0x1b
+#define GC_USB_DIEPCTL8_SNAK_MASK 0x8000000
+#define GC_USB_DIEPCTL8_SNAK_SIZE 0x1
+#define GC_USB_DIEPCTL8_SNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL8_SNAK_OFFSET 0xa00
+#define GC_USB_DIEPCTL8_SETD0PID_LSB 0x1c
+#define GC_USB_DIEPCTL8_SETD0PID_MASK 0x10000000
+#define GC_USB_DIEPCTL8_SETD0PID_SIZE 0x1
+#define GC_USB_DIEPCTL8_SETD0PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL8_SETD0PID_OFFSET 0xa00
+#define GC_USB_DIEPCTL8_SETD1PID_LSB 0x1d
+#define GC_USB_DIEPCTL8_SETD1PID_MASK 0x20000000
+#define GC_USB_DIEPCTL8_SETD1PID_SIZE 0x1
+#define GC_USB_DIEPCTL8_SETD1PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL8_SETD1PID_OFFSET 0xa00
+#define GC_USB_DIEPCTL8_EPDIS_LSB 0x1e
+#define GC_USB_DIEPCTL8_EPDIS_MASK 0x40000000
+#define GC_USB_DIEPCTL8_EPDIS_SIZE 0x1
+#define GC_USB_DIEPCTL8_EPDIS_DEFAULT 0x0
+#define GC_USB_DIEPCTL8_EPDIS_OFFSET 0xa00
+#define GC_USB_DIEPCTL8_EPENA_LSB 0x1f
+#define GC_USB_DIEPCTL8_EPENA_MASK 0x80000000
+#define GC_USB_DIEPCTL8_EPENA_SIZE 0x1
+#define GC_USB_DIEPCTL8_EPENA_DEFAULT 0x0
+#define GC_USB_DIEPCTL8_EPENA_OFFSET 0xa00
+#define GC_USB_DIEPINT8_XFERCOMPL_LSB 0x0
+#define GC_USB_DIEPINT8_XFERCOMPL_MASK 0x1
+#define GC_USB_DIEPINT8_XFERCOMPL_SIZE 0x1
+#define GC_USB_DIEPINT8_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DIEPINT8_XFERCOMPL_OFFSET 0xa08
+#define GC_USB_DIEPINT8_EPDISBLD_LSB 0x1
+#define GC_USB_DIEPINT8_EPDISBLD_MASK 0x2
+#define GC_USB_DIEPINT8_EPDISBLD_SIZE 0x1
+#define GC_USB_DIEPINT8_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DIEPINT8_EPDISBLD_OFFSET 0xa08
+#define GC_USB_DIEPINT8_AHBERR_LSB 0x2
+#define GC_USB_DIEPINT8_AHBERR_MASK 0x4
+#define GC_USB_DIEPINT8_AHBERR_SIZE 0x1
+#define GC_USB_DIEPINT8_AHBERR_DEFAULT 0x0
+#define GC_USB_DIEPINT8_AHBERR_OFFSET 0xa08
+#define GC_USB_DIEPINT8_TIMEOUT_LSB 0x3
+#define GC_USB_DIEPINT8_TIMEOUT_MASK 0x8
+#define GC_USB_DIEPINT8_TIMEOUT_SIZE 0x1
+#define GC_USB_DIEPINT8_TIMEOUT_DEFAULT 0x0
+#define GC_USB_DIEPINT8_TIMEOUT_OFFSET 0xa08
+#define GC_USB_DIEPINT8_INTKNTXFEMP_LSB 0x4
+#define GC_USB_DIEPINT8_INTKNTXFEMP_MASK 0x10
+#define GC_USB_DIEPINT8_INTKNTXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT8_INTKNTXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT8_INTKNTXFEMP_OFFSET 0xa08
+#define GC_USB_DIEPINT8_INTKNEPMIS_LSB 0x5
+#define GC_USB_DIEPINT8_INTKNEPMIS_MASK 0x20
+#define GC_USB_DIEPINT8_INTKNEPMIS_SIZE 0x1
+#define GC_USB_DIEPINT8_INTKNEPMIS_DEFAULT 0x0
+#define GC_USB_DIEPINT8_INTKNEPMIS_OFFSET 0xa08
+#define GC_USB_DIEPINT8_INEPNAKEFF_LSB 0x6
+#define GC_USB_DIEPINT8_INEPNAKEFF_MASK 0x40
+#define GC_USB_DIEPINT8_INEPNAKEFF_SIZE 0x1
+#define GC_USB_DIEPINT8_INEPNAKEFF_DEFAULT 0x0
+#define GC_USB_DIEPINT8_INEPNAKEFF_OFFSET 0xa08
+#define GC_USB_DIEPINT8_TXFEMP_LSB 0x7
+#define GC_USB_DIEPINT8_TXFEMP_MASK 0x80
+#define GC_USB_DIEPINT8_TXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT8_TXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT8_TXFEMP_OFFSET 0xa08
+#define GC_USB_DIEPINT8_TXFIFOUNDRN_LSB 0x8
+#define GC_USB_DIEPINT8_TXFIFOUNDRN_MASK 0x100
+#define GC_USB_DIEPINT8_TXFIFOUNDRN_SIZE 0x1
+#define GC_USB_DIEPINT8_TXFIFOUNDRN_DEFAULT 0x0
+#define GC_USB_DIEPINT8_TXFIFOUNDRN_OFFSET 0xa08
+#define GC_USB_DIEPINT8_BNAINTR_LSB 0x9
+#define GC_USB_DIEPINT8_BNAINTR_MASK 0x200
+#define GC_USB_DIEPINT8_BNAINTR_SIZE 0x1
+#define GC_USB_DIEPINT8_BNAINTR_DEFAULT 0x0
+#define GC_USB_DIEPINT8_BNAINTR_OFFSET 0xa08
+#define GC_USB_DIEPINT8_PKTDRPSTS_LSB 0xb
+#define GC_USB_DIEPINT8_PKTDRPSTS_MASK 0x800
+#define GC_USB_DIEPINT8_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DIEPINT8_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DIEPINT8_PKTDRPSTS_OFFSET 0xa08
+#define GC_USB_DIEPINT8_BBLEERR_LSB 0xc
+#define GC_USB_DIEPINT8_BBLEERR_MASK 0x1000
+#define GC_USB_DIEPINT8_BBLEERR_SIZE 0x1
+#define GC_USB_DIEPINT8_BBLEERR_DEFAULT 0x0
+#define GC_USB_DIEPINT8_BBLEERR_OFFSET 0xa08
+#define GC_USB_DIEPINT8_NAKINTRPT_LSB 0xd
+#define GC_USB_DIEPINT8_NAKINTRPT_MASK 0x2000
+#define GC_USB_DIEPINT8_NAKINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT8_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT8_NAKINTRPT_OFFSET 0xa08
+#define GC_USB_DIEPINT8_NYETINTRPT_LSB 0xe
+#define GC_USB_DIEPINT8_NYETINTRPT_MASK 0x4000
+#define GC_USB_DIEPINT8_NYETINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT8_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT8_NYETINTRPT_OFFSET 0xa08
+#define GC_USB_DIEPTSIZ8_XFERSIZE_LSB 0x0
+#define GC_USB_DIEPTSIZ8_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DIEPTSIZ8_XFERSIZE_SIZE 0x13
+#define GC_USB_DIEPTSIZ8_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ8_XFERSIZE_OFFSET 0xa10
+#define GC_USB_DIEPTSIZ8_PKTCNT_LSB 0x13
+#define GC_USB_DIEPTSIZ8_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DIEPTSIZ8_PKTCNT_SIZE 0xa
+#define GC_USB_DIEPTSIZ8_PKTCNT_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ8_PKTCNT_OFFSET 0xa10
+#define GC_USB_DIEPTSIZ8_MC_LSB 0x1d
+#define GC_USB_DIEPTSIZ8_MC_MASK 0x60000000
+#define GC_USB_DIEPTSIZ8_MC_SIZE 0x2
+#define GC_USB_DIEPTSIZ8_MC_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ8_MC_OFFSET 0xa10
+#define GC_USB_DIEPDMA8_DMAADDR_LSB 0x0
+#define GC_USB_DIEPDMA8_DMAADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMA8_DMAADDR_SIZE 0x20
+#define GC_USB_DIEPDMA8_DMAADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMA8_DMAADDR_OFFSET 0xa14
+#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_LSB 0x0
+#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_MASK 0xffff
+#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_SIZE 0x10
+#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_DEFAULT 0x0
+#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_OFFSET 0xa18
+#define GC_USB_DIEPDMAB8_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DIEPDMAB8_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMAB8_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DIEPDMAB8_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMAB8_DMABUFFERADDR_OFFSET 0xa1c
+#define GC_USB_DIEPCTL9_MPS_LSB 0x0
+#define GC_USB_DIEPCTL9_MPS_MASK 0x7ff
+#define GC_USB_DIEPCTL9_MPS_SIZE 0xb
+#define GC_USB_DIEPCTL9_MPS_DEFAULT 0x0
+#define GC_USB_DIEPCTL9_MPS_OFFSET 0xa20
+#define GC_USB_DIEPCTL9_USBACTEP_LSB 0xf
+#define GC_USB_DIEPCTL9_USBACTEP_MASK 0x8000
+#define GC_USB_DIEPCTL9_USBACTEP_SIZE 0x1
+#define GC_USB_DIEPCTL9_USBACTEP_DEFAULT 0x0
+#define GC_USB_DIEPCTL9_USBACTEP_OFFSET 0xa20
+#define GC_USB_DIEPCTL9_DPID_LSB 0x10
+#define GC_USB_DIEPCTL9_DPID_MASK 0x10000
+#define GC_USB_DIEPCTL9_DPID_SIZE 0x1
+#define GC_USB_DIEPCTL9_DPID_DEFAULT 0x0
+#define GC_USB_DIEPCTL9_DPID_OFFSET 0xa20
+#define GC_USB_DIEPCTL9_NAKSTS_LSB 0x11
+#define GC_USB_DIEPCTL9_NAKSTS_MASK 0x20000
+#define GC_USB_DIEPCTL9_NAKSTS_SIZE 0x1
+#define GC_USB_DIEPCTL9_NAKSTS_DEFAULT 0x0
+#define GC_USB_DIEPCTL9_NAKSTS_OFFSET 0xa20
+#define GC_USB_DIEPCTL9_EPTYPE_LSB 0x12
+#define GC_USB_DIEPCTL9_EPTYPE_MASK 0xc0000
+#define GC_USB_DIEPCTL9_EPTYPE_SIZE 0x2
+#define GC_USB_DIEPCTL9_EPTYPE_DEFAULT 0x0
+#define GC_USB_DIEPCTL9_EPTYPE_OFFSET 0xa20
+#define GC_USB_DIEPCTL9_STALL_LSB 0x15
+#define GC_USB_DIEPCTL9_STALL_MASK 0x200000
+#define GC_USB_DIEPCTL9_STALL_SIZE 0x1
+#define GC_USB_DIEPCTL9_STALL_DEFAULT 0x0
+#define GC_USB_DIEPCTL9_STALL_OFFSET 0xa20
+#define GC_USB_DIEPCTL9_TXFNUM_LSB 0x16
+#define GC_USB_DIEPCTL9_TXFNUM_MASK 0x3c00000
+#define GC_USB_DIEPCTL9_TXFNUM_SIZE 0x4
+#define GC_USB_DIEPCTL9_TXFNUM_DEFAULT 0x0
+#define GC_USB_DIEPCTL9_TXFNUM_OFFSET 0xa20
+#define GC_USB_DIEPCTL9_CNAK_LSB 0x1a
+#define GC_USB_DIEPCTL9_CNAK_MASK 0x4000000
+#define GC_USB_DIEPCTL9_CNAK_SIZE 0x1
+#define GC_USB_DIEPCTL9_CNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL9_CNAK_OFFSET 0xa20
+#define GC_USB_DIEPCTL9_SNAK_LSB 0x1b
+#define GC_USB_DIEPCTL9_SNAK_MASK 0x8000000
+#define GC_USB_DIEPCTL9_SNAK_SIZE 0x1
+#define GC_USB_DIEPCTL9_SNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL9_SNAK_OFFSET 0xa20
+#define GC_USB_DIEPCTL9_SETD0PID_LSB 0x1c
+#define GC_USB_DIEPCTL9_SETD0PID_MASK 0x10000000
+#define GC_USB_DIEPCTL9_SETD0PID_SIZE 0x1
+#define GC_USB_DIEPCTL9_SETD0PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL9_SETD0PID_OFFSET 0xa20
+#define GC_USB_DIEPCTL9_SETD1PID_LSB 0x1d
+#define GC_USB_DIEPCTL9_SETD1PID_MASK 0x20000000
+#define GC_USB_DIEPCTL9_SETD1PID_SIZE 0x1
+#define GC_USB_DIEPCTL9_SETD1PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL9_SETD1PID_OFFSET 0xa20
+#define GC_USB_DIEPCTL9_EPDIS_LSB 0x1e
+#define GC_USB_DIEPCTL9_EPDIS_MASK 0x40000000
+#define GC_USB_DIEPCTL9_EPDIS_SIZE 0x1
+#define GC_USB_DIEPCTL9_EPDIS_DEFAULT 0x0
+#define GC_USB_DIEPCTL9_EPDIS_OFFSET 0xa20
+#define GC_USB_DIEPCTL9_EPENA_LSB 0x1f
+#define GC_USB_DIEPCTL9_EPENA_MASK 0x80000000
+#define GC_USB_DIEPCTL9_EPENA_SIZE 0x1
+#define GC_USB_DIEPCTL9_EPENA_DEFAULT 0x0
+#define GC_USB_DIEPCTL9_EPENA_OFFSET 0xa20
+#define GC_USB_DIEPINT9_XFERCOMPL_LSB 0x0
+#define GC_USB_DIEPINT9_XFERCOMPL_MASK 0x1
+#define GC_USB_DIEPINT9_XFERCOMPL_SIZE 0x1
+#define GC_USB_DIEPINT9_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DIEPINT9_XFERCOMPL_OFFSET 0xa28
+#define GC_USB_DIEPINT9_EPDISBLD_LSB 0x1
+#define GC_USB_DIEPINT9_EPDISBLD_MASK 0x2
+#define GC_USB_DIEPINT9_EPDISBLD_SIZE 0x1
+#define GC_USB_DIEPINT9_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DIEPINT9_EPDISBLD_OFFSET 0xa28
+#define GC_USB_DIEPINT9_AHBERR_LSB 0x2
+#define GC_USB_DIEPINT9_AHBERR_MASK 0x4
+#define GC_USB_DIEPINT9_AHBERR_SIZE 0x1
+#define GC_USB_DIEPINT9_AHBERR_DEFAULT 0x0
+#define GC_USB_DIEPINT9_AHBERR_OFFSET 0xa28
+#define GC_USB_DIEPINT9_TIMEOUT_LSB 0x3
+#define GC_USB_DIEPINT9_TIMEOUT_MASK 0x8
+#define GC_USB_DIEPINT9_TIMEOUT_SIZE 0x1
+#define GC_USB_DIEPINT9_TIMEOUT_DEFAULT 0x0
+#define GC_USB_DIEPINT9_TIMEOUT_OFFSET 0xa28
+#define GC_USB_DIEPINT9_INTKNTXFEMP_LSB 0x4
+#define GC_USB_DIEPINT9_INTKNTXFEMP_MASK 0x10
+#define GC_USB_DIEPINT9_INTKNTXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT9_INTKNTXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT9_INTKNTXFEMP_OFFSET 0xa28
+#define GC_USB_DIEPINT9_INTKNEPMIS_LSB 0x5
+#define GC_USB_DIEPINT9_INTKNEPMIS_MASK 0x20
+#define GC_USB_DIEPINT9_INTKNEPMIS_SIZE 0x1
+#define GC_USB_DIEPINT9_INTKNEPMIS_DEFAULT 0x0
+#define GC_USB_DIEPINT9_INTKNEPMIS_OFFSET 0xa28
+#define GC_USB_DIEPINT9_INEPNAKEFF_LSB 0x6
+#define GC_USB_DIEPINT9_INEPNAKEFF_MASK 0x40
+#define GC_USB_DIEPINT9_INEPNAKEFF_SIZE 0x1
+#define GC_USB_DIEPINT9_INEPNAKEFF_DEFAULT 0x0
+#define GC_USB_DIEPINT9_INEPNAKEFF_OFFSET 0xa28
+#define GC_USB_DIEPINT9_TXFEMP_LSB 0x7
+#define GC_USB_DIEPINT9_TXFEMP_MASK 0x80
+#define GC_USB_DIEPINT9_TXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT9_TXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT9_TXFEMP_OFFSET 0xa28
+#define GC_USB_DIEPINT9_TXFIFOUNDRN_LSB 0x8
+#define GC_USB_DIEPINT9_TXFIFOUNDRN_MASK 0x100
+#define GC_USB_DIEPINT9_TXFIFOUNDRN_SIZE 0x1
+#define GC_USB_DIEPINT9_TXFIFOUNDRN_DEFAULT 0x0
+#define GC_USB_DIEPINT9_TXFIFOUNDRN_OFFSET 0xa28
+#define GC_USB_DIEPINT9_BNAINTR_LSB 0x9
+#define GC_USB_DIEPINT9_BNAINTR_MASK 0x200
+#define GC_USB_DIEPINT9_BNAINTR_SIZE 0x1
+#define GC_USB_DIEPINT9_BNAINTR_DEFAULT 0x0
+#define GC_USB_DIEPINT9_BNAINTR_OFFSET 0xa28
+#define GC_USB_DIEPINT9_PKTDRPSTS_LSB 0xb
+#define GC_USB_DIEPINT9_PKTDRPSTS_MASK 0x800
+#define GC_USB_DIEPINT9_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DIEPINT9_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DIEPINT9_PKTDRPSTS_OFFSET 0xa28
+#define GC_USB_DIEPINT9_BBLEERR_LSB 0xc
+#define GC_USB_DIEPINT9_BBLEERR_MASK 0x1000
+#define GC_USB_DIEPINT9_BBLEERR_SIZE 0x1
+#define GC_USB_DIEPINT9_BBLEERR_DEFAULT 0x0
+#define GC_USB_DIEPINT9_BBLEERR_OFFSET 0xa28
+#define GC_USB_DIEPINT9_NAKINTRPT_LSB 0xd
+#define GC_USB_DIEPINT9_NAKINTRPT_MASK 0x2000
+#define GC_USB_DIEPINT9_NAKINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT9_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT9_NAKINTRPT_OFFSET 0xa28
+#define GC_USB_DIEPINT9_NYETINTRPT_LSB 0xe
+#define GC_USB_DIEPINT9_NYETINTRPT_MASK 0x4000
+#define GC_USB_DIEPINT9_NYETINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT9_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT9_NYETINTRPT_OFFSET 0xa28
+#define GC_USB_DIEPTSIZ9_XFERSIZE_LSB 0x0
+#define GC_USB_DIEPTSIZ9_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DIEPTSIZ9_XFERSIZE_SIZE 0x13
+#define GC_USB_DIEPTSIZ9_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ9_XFERSIZE_OFFSET 0xa30
+#define GC_USB_DIEPTSIZ9_PKTCNT_LSB 0x13
+#define GC_USB_DIEPTSIZ9_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DIEPTSIZ9_PKTCNT_SIZE 0xa
+#define GC_USB_DIEPTSIZ9_PKTCNT_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ9_PKTCNT_OFFSET 0xa30
+#define GC_USB_DIEPTSIZ9_MC_LSB 0x1d
+#define GC_USB_DIEPTSIZ9_MC_MASK 0x60000000
+#define GC_USB_DIEPTSIZ9_MC_SIZE 0x2
+#define GC_USB_DIEPTSIZ9_MC_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ9_MC_OFFSET 0xa30
+#define GC_USB_DIEPDMA9_DMAADDR_LSB 0x0
+#define GC_USB_DIEPDMA9_DMAADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMA9_DMAADDR_SIZE 0x20
+#define GC_USB_DIEPDMA9_DMAADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMA9_DMAADDR_OFFSET 0xa34
+#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_LSB 0x0
+#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_MASK 0xffff
+#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_SIZE 0x10
+#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_DEFAULT 0x0
+#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_OFFSET 0xa38
+#define GC_USB_DIEPDMAB9_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DIEPDMAB9_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMAB9_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DIEPDMAB9_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMAB9_DMABUFFERADDR_OFFSET 0xa3c
+#define GC_USB_DIEPCTL10_MPS_LSB 0x0
+#define GC_USB_DIEPCTL10_MPS_MASK 0x7ff
+#define GC_USB_DIEPCTL10_MPS_SIZE 0xb
+#define GC_USB_DIEPCTL10_MPS_DEFAULT 0x0
+#define GC_USB_DIEPCTL10_MPS_OFFSET 0xa40
+#define GC_USB_DIEPCTL10_USBACTEP_LSB 0xf
+#define GC_USB_DIEPCTL10_USBACTEP_MASK 0x8000
+#define GC_USB_DIEPCTL10_USBACTEP_SIZE 0x1
+#define GC_USB_DIEPCTL10_USBACTEP_DEFAULT 0x0
+#define GC_USB_DIEPCTL10_USBACTEP_OFFSET 0xa40
+#define GC_USB_DIEPCTL10_DPID_LSB 0x10
+#define GC_USB_DIEPCTL10_DPID_MASK 0x10000
+#define GC_USB_DIEPCTL10_DPID_SIZE 0x1
+#define GC_USB_DIEPCTL10_DPID_DEFAULT 0x0
+#define GC_USB_DIEPCTL10_DPID_OFFSET 0xa40
+#define GC_USB_DIEPCTL10_NAKSTS_LSB 0x11
+#define GC_USB_DIEPCTL10_NAKSTS_MASK 0x20000
+#define GC_USB_DIEPCTL10_NAKSTS_SIZE 0x1
+#define GC_USB_DIEPCTL10_NAKSTS_DEFAULT 0x0
+#define GC_USB_DIEPCTL10_NAKSTS_OFFSET 0xa40
+#define GC_USB_DIEPCTL10_EPTYPE_LSB 0x12
+#define GC_USB_DIEPCTL10_EPTYPE_MASK 0xc0000
+#define GC_USB_DIEPCTL10_EPTYPE_SIZE 0x2
+#define GC_USB_DIEPCTL10_EPTYPE_DEFAULT 0x0
+#define GC_USB_DIEPCTL10_EPTYPE_OFFSET 0xa40
+#define GC_USB_DIEPCTL10_STALL_LSB 0x15
+#define GC_USB_DIEPCTL10_STALL_MASK 0x200000
+#define GC_USB_DIEPCTL10_STALL_SIZE 0x1
+#define GC_USB_DIEPCTL10_STALL_DEFAULT 0x0
+#define GC_USB_DIEPCTL10_STALL_OFFSET 0xa40
+#define GC_USB_DIEPCTL10_TXFNUM_LSB 0x16
+#define GC_USB_DIEPCTL10_TXFNUM_MASK 0x3c00000
+#define GC_USB_DIEPCTL10_TXFNUM_SIZE 0x4
+#define GC_USB_DIEPCTL10_TXFNUM_DEFAULT 0x0
+#define GC_USB_DIEPCTL10_TXFNUM_OFFSET 0xa40
+#define GC_USB_DIEPCTL10_CNAK_LSB 0x1a
+#define GC_USB_DIEPCTL10_CNAK_MASK 0x4000000
+#define GC_USB_DIEPCTL10_CNAK_SIZE 0x1
+#define GC_USB_DIEPCTL10_CNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL10_CNAK_OFFSET 0xa40
+#define GC_USB_DIEPCTL10_SNAK_LSB 0x1b
+#define GC_USB_DIEPCTL10_SNAK_MASK 0x8000000
+#define GC_USB_DIEPCTL10_SNAK_SIZE 0x1
+#define GC_USB_DIEPCTL10_SNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL10_SNAK_OFFSET 0xa40
+#define GC_USB_DIEPCTL10_SETD0PID_LSB 0x1c
+#define GC_USB_DIEPCTL10_SETD0PID_MASK 0x10000000
+#define GC_USB_DIEPCTL10_SETD0PID_SIZE 0x1
+#define GC_USB_DIEPCTL10_SETD0PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL10_SETD0PID_OFFSET 0xa40
+#define GC_USB_DIEPCTL10_SETD1PID_LSB 0x1d
+#define GC_USB_DIEPCTL10_SETD1PID_MASK 0x20000000
+#define GC_USB_DIEPCTL10_SETD1PID_SIZE 0x1
+#define GC_USB_DIEPCTL10_SETD1PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL10_SETD1PID_OFFSET 0xa40
+#define GC_USB_DIEPCTL10_EPDIS_LSB 0x1e
+#define GC_USB_DIEPCTL10_EPDIS_MASK 0x40000000
+#define GC_USB_DIEPCTL10_EPDIS_SIZE 0x1
+#define GC_USB_DIEPCTL10_EPDIS_DEFAULT 0x0
+#define GC_USB_DIEPCTL10_EPDIS_OFFSET 0xa40
+#define GC_USB_DIEPCTL10_EPENA_LSB 0x1f
+#define GC_USB_DIEPCTL10_EPENA_MASK 0x80000000
+#define GC_USB_DIEPCTL10_EPENA_SIZE 0x1
+#define GC_USB_DIEPCTL10_EPENA_DEFAULT 0x0
+#define GC_USB_DIEPCTL10_EPENA_OFFSET 0xa40
+#define GC_USB_DIEPINT10_XFERCOMPL_LSB 0x0
+#define GC_USB_DIEPINT10_XFERCOMPL_MASK 0x1
+#define GC_USB_DIEPINT10_XFERCOMPL_SIZE 0x1
+#define GC_USB_DIEPINT10_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DIEPINT10_XFERCOMPL_OFFSET 0xa48
+#define GC_USB_DIEPINT10_EPDISBLD_LSB 0x1
+#define GC_USB_DIEPINT10_EPDISBLD_MASK 0x2
+#define GC_USB_DIEPINT10_EPDISBLD_SIZE 0x1
+#define GC_USB_DIEPINT10_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DIEPINT10_EPDISBLD_OFFSET 0xa48
+#define GC_USB_DIEPINT10_AHBERR_LSB 0x2
+#define GC_USB_DIEPINT10_AHBERR_MASK 0x4
+#define GC_USB_DIEPINT10_AHBERR_SIZE 0x1
+#define GC_USB_DIEPINT10_AHBERR_DEFAULT 0x0
+#define GC_USB_DIEPINT10_AHBERR_OFFSET 0xa48
+#define GC_USB_DIEPINT10_TIMEOUT_LSB 0x3
+#define GC_USB_DIEPINT10_TIMEOUT_MASK 0x8
+#define GC_USB_DIEPINT10_TIMEOUT_SIZE 0x1
+#define GC_USB_DIEPINT10_TIMEOUT_DEFAULT 0x0
+#define GC_USB_DIEPINT10_TIMEOUT_OFFSET 0xa48
+#define GC_USB_DIEPINT10_INTKNTXFEMP_LSB 0x4
+#define GC_USB_DIEPINT10_INTKNTXFEMP_MASK 0x10
+#define GC_USB_DIEPINT10_INTKNTXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT10_INTKNTXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT10_INTKNTXFEMP_OFFSET 0xa48
+#define GC_USB_DIEPINT10_INTKNEPMIS_LSB 0x5
+#define GC_USB_DIEPINT10_INTKNEPMIS_MASK 0x20
+#define GC_USB_DIEPINT10_INTKNEPMIS_SIZE 0x1
+#define GC_USB_DIEPINT10_INTKNEPMIS_DEFAULT 0x0
+#define GC_USB_DIEPINT10_INTKNEPMIS_OFFSET 0xa48
+#define GC_USB_DIEPINT10_INEPNAKEFF_LSB 0x6
+#define GC_USB_DIEPINT10_INEPNAKEFF_MASK 0x40
+#define GC_USB_DIEPINT10_INEPNAKEFF_SIZE 0x1
+#define GC_USB_DIEPINT10_INEPNAKEFF_DEFAULT 0x0
+#define GC_USB_DIEPINT10_INEPNAKEFF_OFFSET 0xa48
+#define GC_USB_DIEPINT10_TXFEMP_LSB 0x7
+#define GC_USB_DIEPINT10_TXFEMP_MASK 0x80
+#define GC_USB_DIEPINT10_TXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT10_TXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT10_TXFEMP_OFFSET 0xa48
+#define GC_USB_DIEPINT10_TXFIFOUNDRN_LSB 0x8
+#define GC_USB_DIEPINT10_TXFIFOUNDRN_MASK 0x100
+#define GC_USB_DIEPINT10_TXFIFOUNDRN_SIZE 0x1
+#define GC_USB_DIEPINT10_TXFIFOUNDRN_DEFAULT 0x0
+#define GC_USB_DIEPINT10_TXFIFOUNDRN_OFFSET 0xa48
+#define GC_USB_DIEPINT10_BNAINTR_LSB 0x9
+#define GC_USB_DIEPINT10_BNAINTR_MASK 0x200
+#define GC_USB_DIEPINT10_BNAINTR_SIZE 0x1
+#define GC_USB_DIEPINT10_BNAINTR_DEFAULT 0x0
+#define GC_USB_DIEPINT10_BNAINTR_OFFSET 0xa48
+#define GC_USB_DIEPINT10_PKTDRPSTS_LSB 0xb
+#define GC_USB_DIEPINT10_PKTDRPSTS_MASK 0x800
+#define GC_USB_DIEPINT10_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DIEPINT10_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DIEPINT10_PKTDRPSTS_OFFSET 0xa48
+#define GC_USB_DIEPINT10_BBLEERR_LSB 0xc
+#define GC_USB_DIEPINT10_BBLEERR_MASK 0x1000
+#define GC_USB_DIEPINT10_BBLEERR_SIZE 0x1
+#define GC_USB_DIEPINT10_BBLEERR_DEFAULT 0x0
+#define GC_USB_DIEPINT10_BBLEERR_OFFSET 0xa48
+#define GC_USB_DIEPINT10_NAKINTRPT_LSB 0xd
+#define GC_USB_DIEPINT10_NAKINTRPT_MASK 0x2000
+#define GC_USB_DIEPINT10_NAKINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT10_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT10_NAKINTRPT_OFFSET 0xa48
+#define GC_USB_DIEPINT10_NYETINTRPT_LSB 0xe
+#define GC_USB_DIEPINT10_NYETINTRPT_MASK 0x4000
+#define GC_USB_DIEPINT10_NYETINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT10_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT10_NYETINTRPT_OFFSET 0xa48
+#define GC_USB_DIEPTSIZ10_XFERSIZE_LSB 0x0
+#define GC_USB_DIEPTSIZ10_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DIEPTSIZ10_XFERSIZE_SIZE 0x13
+#define GC_USB_DIEPTSIZ10_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ10_XFERSIZE_OFFSET 0xa50
+#define GC_USB_DIEPTSIZ10_PKTCNT_LSB 0x13
+#define GC_USB_DIEPTSIZ10_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DIEPTSIZ10_PKTCNT_SIZE 0xa
+#define GC_USB_DIEPTSIZ10_PKTCNT_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ10_PKTCNT_OFFSET 0xa50
+#define GC_USB_DIEPTSIZ10_MC_LSB 0x1d
+#define GC_USB_DIEPTSIZ10_MC_MASK 0x60000000
+#define GC_USB_DIEPTSIZ10_MC_SIZE 0x2
+#define GC_USB_DIEPTSIZ10_MC_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ10_MC_OFFSET 0xa50
+#define GC_USB_DIEPDMA10_DMAADDR_LSB 0x0
+#define GC_USB_DIEPDMA10_DMAADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMA10_DMAADDR_SIZE 0x20
+#define GC_USB_DIEPDMA10_DMAADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMA10_DMAADDR_OFFSET 0xa54
+#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_LSB 0x0
+#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_MASK 0xffff
+#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_SIZE 0x10
 #define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_DEFAULT 0x0
-#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_OFFSET  0xa58
-#define GC_USB_DIEPDMAB10_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DIEPDMAB10_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DIEPDMAB10_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DIEPDMAB10_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DIEPDMAB10_DMABUFFERADDR_OFFSET   0xa5c
-#define GC_USB_DIEPCTL11_MPS_LSB                 0x0
-#define GC_USB_DIEPCTL11_MPS_MASK                0x7ff
-#define GC_USB_DIEPCTL11_MPS_SIZE                0xb
-#define GC_USB_DIEPCTL11_MPS_DEFAULT             0x0
-#define GC_USB_DIEPCTL11_MPS_OFFSET              0xa60
-#define GC_USB_DIEPCTL11_USBACTEP_LSB            0xf
-#define GC_USB_DIEPCTL11_USBACTEP_MASK           0x8000
-#define GC_USB_DIEPCTL11_USBACTEP_SIZE           0x1
-#define GC_USB_DIEPCTL11_USBACTEP_DEFAULT        0x0
-#define GC_USB_DIEPCTL11_USBACTEP_OFFSET         0xa60
-#define GC_USB_DIEPCTL11_DPID_LSB                0x10
-#define GC_USB_DIEPCTL11_DPID_MASK               0x10000
-#define GC_USB_DIEPCTL11_DPID_SIZE               0x1
-#define GC_USB_DIEPCTL11_DPID_DEFAULT            0x0
-#define GC_USB_DIEPCTL11_DPID_OFFSET             0xa60
-#define GC_USB_DIEPCTL11_NAKSTS_LSB              0x11
-#define GC_USB_DIEPCTL11_NAKSTS_MASK             0x20000
-#define GC_USB_DIEPCTL11_NAKSTS_SIZE             0x1
-#define GC_USB_DIEPCTL11_NAKSTS_DEFAULT          0x0
-#define GC_USB_DIEPCTL11_NAKSTS_OFFSET           0xa60
-#define GC_USB_DIEPCTL11_EPTYPE_LSB              0x12
-#define GC_USB_DIEPCTL11_EPTYPE_MASK             0xc0000
-#define GC_USB_DIEPCTL11_EPTYPE_SIZE             0x2
-#define GC_USB_DIEPCTL11_EPTYPE_DEFAULT          0x0
-#define GC_USB_DIEPCTL11_EPTYPE_OFFSET           0xa60
-#define GC_USB_DIEPCTL11_STALL_LSB               0x15
-#define GC_USB_DIEPCTL11_STALL_MASK              0x200000
-#define GC_USB_DIEPCTL11_STALL_SIZE              0x1
-#define GC_USB_DIEPCTL11_STALL_DEFAULT           0x0
-#define GC_USB_DIEPCTL11_STALL_OFFSET            0xa60
-#define GC_USB_DIEPCTL11_TXFNUM_LSB              0x16
-#define GC_USB_DIEPCTL11_TXFNUM_MASK             0x3c00000
-#define GC_USB_DIEPCTL11_TXFNUM_SIZE             0x4
-#define GC_USB_DIEPCTL11_TXFNUM_DEFAULT          0x0
-#define GC_USB_DIEPCTL11_TXFNUM_OFFSET           0xa60
-#define GC_USB_DIEPCTL11_CNAK_LSB                0x1a
-#define GC_USB_DIEPCTL11_CNAK_MASK               0x4000000
-#define GC_USB_DIEPCTL11_CNAK_SIZE               0x1
-#define GC_USB_DIEPCTL11_CNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL11_CNAK_OFFSET             0xa60
-#define GC_USB_DIEPCTL11_SNAK_LSB                0x1b
-#define GC_USB_DIEPCTL11_SNAK_MASK               0x8000000
-#define GC_USB_DIEPCTL11_SNAK_SIZE               0x1
-#define GC_USB_DIEPCTL11_SNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL11_SNAK_OFFSET             0xa60
-#define GC_USB_DIEPCTL11_SETD0PID_LSB            0x1c
-#define GC_USB_DIEPCTL11_SETD0PID_MASK           0x10000000
-#define GC_USB_DIEPCTL11_SETD0PID_SIZE           0x1
-#define GC_USB_DIEPCTL11_SETD0PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL11_SETD0PID_OFFSET         0xa60
-#define GC_USB_DIEPCTL11_SETD1PID_LSB            0x1d
-#define GC_USB_DIEPCTL11_SETD1PID_MASK           0x20000000
-#define GC_USB_DIEPCTL11_SETD1PID_SIZE           0x1
-#define GC_USB_DIEPCTL11_SETD1PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL11_SETD1PID_OFFSET         0xa60
-#define GC_USB_DIEPCTL11_EPDIS_LSB               0x1e
-#define GC_USB_DIEPCTL11_EPDIS_MASK              0x40000000
-#define GC_USB_DIEPCTL11_EPDIS_SIZE              0x1
-#define GC_USB_DIEPCTL11_EPDIS_DEFAULT           0x0
-#define GC_USB_DIEPCTL11_EPDIS_OFFSET            0xa60
-#define GC_USB_DIEPCTL11_EPENA_LSB               0x1f
-#define GC_USB_DIEPCTL11_EPENA_MASK              0x80000000
-#define GC_USB_DIEPCTL11_EPENA_SIZE              0x1
-#define GC_USB_DIEPCTL11_EPENA_DEFAULT           0x0
-#define GC_USB_DIEPCTL11_EPENA_OFFSET            0xa60
-#define GC_USB_DIEPINT11_XFERCOMPL_LSB           0x0
-#define GC_USB_DIEPINT11_XFERCOMPL_MASK          0x1
-#define GC_USB_DIEPINT11_XFERCOMPL_SIZE          0x1
-#define GC_USB_DIEPINT11_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DIEPINT11_XFERCOMPL_OFFSET        0xa68
-#define GC_USB_DIEPINT11_EPDISBLD_LSB            0x1
-#define GC_USB_DIEPINT11_EPDISBLD_MASK           0x2
-#define GC_USB_DIEPINT11_EPDISBLD_SIZE           0x1
-#define GC_USB_DIEPINT11_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DIEPINT11_EPDISBLD_OFFSET         0xa68
-#define GC_USB_DIEPINT11_AHBERR_LSB              0x2
-#define GC_USB_DIEPINT11_AHBERR_MASK             0x4
-#define GC_USB_DIEPINT11_AHBERR_SIZE             0x1
-#define GC_USB_DIEPINT11_AHBERR_DEFAULT          0x0
-#define GC_USB_DIEPINT11_AHBERR_OFFSET           0xa68
-#define GC_USB_DIEPINT11_TIMEOUT_LSB             0x3
-#define GC_USB_DIEPINT11_TIMEOUT_MASK            0x8
-#define GC_USB_DIEPINT11_TIMEOUT_SIZE            0x1
-#define GC_USB_DIEPINT11_TIMEOUT_DEFAULT         0x0
-#define GC_USB_DIEPINT11_TIMEOUT_OFFSET          0xa68
-#define GC_USB_DIEPINT11_INTKNTXFEMP_LSB         0x4
-#define GC_USB_DIEPINT11_INTKNTXFEMP_MASK        0x10
-#define GC_USB_DIEPINT11_INTKNTXFEMP_SIZE        0x1
-#define GC_USB_DIEPINT11_INTKNTXFEMP_DEFAULT     0x0
-#define GC_USB_DIEPINT11_INTKNTXFEMP_OFFSET      0xa68
-#define GC_USB_DIEPINT11_INTKNEPMIS_LSB          0x5
-#define GC_USB_DIEPINT11_INTKNEPMIS_MASK         0x20
-#define GC_USB_DIEPINT11_INTKNEPMIS_SIZE         0x1
-#define GC_USB_DIEPINT11_INTKNEPMIS_DEFAULT      0x0
-#define GC_USB_DIEPINT11_INTKNEPMIS_OFFSET       0xa68
-#define GC_USB_DIEPINT11_INEPNAKEFF_LSB          0x6
-#define GC_USB_DIEPINT11_INEPNAKEFF_MASK         0x40
-#define GC_USB_DIEPINT11_INEPNAKEFF_SIZE         0x1
-#define GC_USB_DIEPINT11_INEPNAKEFF_DEFAULT      0x0
-#define GC_USB_DIEPINT11_INEPNAKEFF_OFFSET       0xa68
-#define GC_USB_DIEPINT11_TXFEMP_LSB              0x7
-#define GC_USB_DIEPINT11_TXFEMP_MASK             0x80
-#define GC_USB_DIEPINT11_TXFEMP_SIZE             0x1
-#define GC_USB_DIEPINT11_TXFEMP_DEFAULT          0x0
-#define GC_USB_DIEPINT11_TXFEMP_OFFSET           0xa68
-#define GC_USB_DIEPINT11_TXFIFOUNDRN_LSB         0x8
-#define GC_USB_DIEPINT11_TXFIFOUNDRN_MASK        0x100
-#define GC_USB_DIEPINT11_TXFIFOUNDRN_SIZE        0x1
-#define GC_USB_DIEPINT11_TXFIFOUNDRN_DEFAULT     0x0
-#define GC_USB_DIEPINT11_TXFIFOUNDRN_OFFSET      0xa68
-#define GC_USB_DIEPINT11_BNAINTR_LSB             0x9
-#define GC_USB_DIEPINT11_BNAINTR_MASK            0x200
-#define GC_USB_DIEPINT11_BNAINTR_SIZE            0x1
-#define GC_USB_DIEPINT11_BNAINTR_DEFAULT         0x0
-#define GC_USB_DIEPINT11_BNAINTR_OFFSET          0xa68
-#define GC_USB_DIEPINT11_PKTDRPSTS_LSB           0xb
-#define GC_USB_DIEPINT11_PKTDRPSTS_MASK          0x800
-#define GC_USB_DIEPINT11_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DIEPINT11_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DIEPINT11_PKTDRPSTS_OFFSET        0xa68
-#define GC_USB_DIEPINT11_BBLEERR_LSB             0xc
-#define GC_USB_DIEPINT11_BBLEERR_MASK            0x1000
-#define GC_USB_DIEPINT11_BBLEERR_SIZE            0x1
-#define GC_USB_DIEPINT11_BBLEERR_DEFAULT         0x0
-#define GC_USB_DIEPINT11_BBLEERR_OFFSET          0xa68
-#define GC_USB_DIEPINT11_NAKINTRPT_LSB           0xd
-#define GC_USB_DIEPINT11_NAKINTRPT_MASK          0x2000
-#define GC_USB_DIEPINT11_NAKINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT11_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT11_NAKINTRPT_OFFSET        0xa68
-#define GC_USB_DIEPINT11_NYETINTRPT_LSB          0xe
-#define GC_USB_DIEPINT11_NYETINTRPT_MASK         0x4000
-#define GC_USB_DIEPINT11_NYETINTRPT_SIZE         0x1
-#define GC_USB_DIEPINT11_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DIEPINT11_NYETINTRPT_OFFSET       0xa68
-#define GC_USB_DIEPTSIZ11_XFERSIZE_LSB           0x0
-#define GC_USB_DIEPTSIZ11_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DIEPTSIZ11_XFERSIZE_SIZE          0x13
-#define GC_USB_DIEPTSIZ11_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DIEPTSIZ11_XFERSIZE_OFFSET        0xa70
-#define GC_USB_DIEPTSIZ11_PKTCNT_LSB             0x13
-#define GC_USB_DIEPTSIZ11_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DIEPTSIZ11_PKTCNT_SIZE            0xa
-#define GC_USB_DIEPTSIZ11_PKTCNT_DEFAULT         0x0
-#define GC_USB_DIEPTSIZ11_PKTCNT_OFFSET          0xa70
-#define GC_USB_DIEPTSIZ11_MC_LSB                 0x1d
-#define GC_USB_DIEPTSIZ11_MC_MASK                0x60000000
-#define GC_USB_DIEPTSIZ11_MC_SIZE                0x2
-#define GC_USB_DIEPTSIZ11_MC_DEFAULT             0x0
-#define GC_USB_DIEPTSIZ11_MC_OFFSET              0xa70
-#define GC_USB_DIEPDMA11_DMAADDR_LSB             0x0
-#define GC_USB_DIEPDMA11_DMAADDR_MASK            0xffffffff
-#define GC_USB_DIEPDMA11_DMAADDR_SIZE            0x20
-#define GC_USB_DIEPDMA11_DMAADDR_DEFAULT         0x0
-#define GC_USB_DIEPDMA11_DMAADDR_OFFSET          0xa74
-#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_LSB     0x0
-#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_MASK    0xffff
-#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_SIZE    0x10
+#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_OFFSET 0xa58
+#define GC_USB_DIEPDMAB10_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DIEPDMAB10_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMAB10_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DIEPDMAB10_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMAB10_DMABUFFERADDR_OFFSET 0xa5c
+#define GC_USB_DIEPCTL11_MPS_LSB 0x0
+#define GC_USB_DIEPCTL11_MPS_MASK 0x7ff
+#define GC_USB_DIEPCTL11_MPS_SIZE 0xb
+#define GC_USB_DIEPCTL11_MPS_DEFAULT 0x0
+#define GC_USB_DIEPCTL11_MPS_OFFSET 0xa60
+#define GC_USB_DIEPCTL11_USBACTEP_LSB 0xf
+#define GC_USB_DIEPCTL11_USBACTEP_MASK 0x8000
+#define GC_USB_DIEPCTL11_USBACTEP_SIZE 0x1
+#define GC_USB_DIEPCTL11_USBACTEP_DEFAULT 0x0
+#define GC_USB_DIEPCTL11_USBACTEP_OFFSET 0xa60
+#define GC_USB_DIEPCTL11_DPID_LSB 0x10
+#define GC_USB_DIEPCTL11_DPID_MASK 0x10000
+#define GC_USB_DIEPCTL11_DPID_SIZE 0x1
+#define GC_USB_DIEPCTL11_DPID_DEFAULT 0x0
+#define GC_USB_DIEPCTL11_DPID_OFFSET 0xa60
+#define GC_USB_DIEPCTL11_NAKSTS_LSB 0x11
+#define GC_USB_DIEPCTL11_NAKSTS_MASK 0x20000
+#define GC_USB_DIEPCTL11_NAKSTS_SIZE 0x1
+#define GC_USB_DIEPCTL11_NAKSTS_DEFAULT 0x0
+#define GC_USB_DIEPCTL11_NAKSTS_OFFSET 0xa60
+#define GC_USB_DIEPCTL11_EPTYPE_LSB 0x12
+#define GC_USB_DIEPCTL11_EPTYPE_MASK 0xc0000
+#define GC_USB_DIEPCTL11_EPTYPE_SIZE 0x2
+#define GC_USB_DIEPCTL11_EPTYPE_DEFAULT 0x0
+#define GC_USB_DIEPCTL11_EPTYPE_OFFSET 0xa60
+#define GC_USB_DIEPCTL11_STALL_LSB 0x15
+#define GC_USB_DIEPCTL11_STALL_MASK 0x200000
+#define GC_USB_DIEPCTL11_STALL_SIZE 0x1
+#define GC_USB_DIEPCTL11_STALL_DEFAULT 0x0
+#define GC_USB_DIEPCTL11_STALL_OFFSET 0xa60
+#define GC_USB_DIEPCTL11_TXFNUM_LSB 0x16
+#define GC_USB_DIEPCTL11_TXFNUM_MASK 0x3c00000
+#define GC_USB_DIEPCTL11_TXFNUM_SIZE 0x4
+#define GC_USB_DIEPCTL11_TXFNUM_DEFAULT 0x0
+#define GC_USB_DIEPCTL11_TXFNUM_OFFSET 0xa60
+#define GC_USB_DIEPCTL11_CNAK_LSB 0x1a
+#define GC_USB_DIEPCTL11_CNAK_MASK 0x4000000
+#define GC_USB_DIEPCTL11_CNAK_SIZE 0x1
+#define GC_USB_DIEPCTL11_CNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL11_CNAK_OFFSET 0xa60
+#define GC_USB_DIEPCTL11_SNAK_LSB 0x1b
+#define GC_USB_DIEPCTL11_SNAK_MASK 0x8000000
+#define GC_USB_DIEPCTL11_SNAK_SIZE 0x1
+#define GC_USB_DIEPCTL11_SNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL11_SNAK_OFFSET 0xa60
+#define GC_USB_DIEPCTL11_SETD0PID_LSB 0x1c
+#define GC_USB_DIEPCTL11_SETD0PID_MASK 0x10000000
+#define GC_USB_DIEPCTL11_SETD0PID_SIZE 0x1
+#define GC_USB_DIEPCTL11_SETD0PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL11_SETD0PID_OFFSET 0xa60
+#define GC_USB_DIEPCTL11_SETD1PID_LSB 0x1d
+#define GC_USB_DIEPCTL11_SETD1PID_MASK 0x20000000
+#define GC_USB_DIEPCTL11_SETD1PID_SIZE 0x1
+#define GC_USB_DIEPCTL11_SETD1PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL11_SETD1PID_OFFSET 0xa60
+#define GC_USB_DIEPCTL11_EPDIS_LSB 0x1e
+#define GC_USB_DIEPCTL11_EPDIS_MASK 0x40000000
+#define GC_USB_DIEPCTL11_EPDIS_SIZE 0x1
+#define GC_USB_DIEPCTL11_EPDIS_DEFAULT 0x0
+#define GC_USB_DIEPCTL11_EPDIS_OFFSET 0xa60
+#define GC_USB_DIEPCTL11_EPENA_LSB 0x1f
+#define GC_USB_DIEPCTL11_EPENA_MASK 0x80000000
+#define GC_USB_DIEPCTL11_EPENA_SIZE 0x1
+#define GC_USB_DIEPCTL11_EPENA_DEFAULT 0x0
+#define GC_USB_DIEPCTL11_EPENA_OFFSET 0xa60
+#define GC_USB_DIEPINT11_XFERCOMPL_LSB 0x0
+#define GC_USB_DIEPINT11_XFERCOMPL_MASK 0x1
+#define GC_USB_DIEPINT11_XFERCOMPL_SIZE 0x1
+#define GC_USB_DIEPINT11_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DIEPINT11_XFERCOMPL_OFFSET 0xa68
+#define GC_USB_DIEPINT11_EPDISBLD_LSB 0x1
+#define GC_USB_DIEPINT11_EPDISBLD_MASK 0x2
+#define GC_USB_DIEPINT11_EPDISBLD_SIZE 0x1
+#define GC_USB_DIEPINT11_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DIEPINT11_EPDISBLD_OFFSET 0xa68
+#define GC_USB_DIEPINT11_AHBERR_LSB 0x2
+#define GC_USB_DIEPINT11_AHBERR_MASK 0x4
+#define GC_USB_DIEPINT11_AHBERR_SIZE 0x1
+#define GC_USB_DIEPINT11_AHBERR_DEFAULT 0x0
+#define GC_USB_DIEPINT11_AHBERR_OFFSET 0xa68
+#define GC_USB_DIEPINT11_TIMEOUT_LSB 0x3
+#define GC_USB_DIEPINT11_TIMEOUT_MASK 0x8
+#define GC_USB_DIEPINT11_TIMEOUT_SIZE 0x1
+#define GC_USB_DIEPINT11_TIMEOUT_DEFAULT 0x0
+#define GC_USB_DIEPINT11_TIMEOUT_OFFSET 0xa68
+#define GC_USB_DIEPINT11_INTKNTXFEMP_LSB 0x4
+#define GC_USB_DIEPINT11_INTKNTXFEMP_MASK 0x10
+#define GC_USB_DIEPINT11_INTKNTXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT11_INTKNTXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT11_INTKNTXFEMP_OFFSET 0xa68
+#define GC_USB_DIEPINT11_INTKNEPMIS_LSB 0x5
+#define GC_USB_DIEPINT11_INTKNEPMIS_MASK 0x20
+#define GC_USB_DIEPINT11_INTKNEPMIS_SIZE 0x1
+#define GC_USB_DIEPINT11_INTKNEPMIS_DEFAULT 0x0
+#define GC_USB_DIEPINT11_INTKNEPMIS_OFFSET 0xa68
+#define GC_USB_DIEPINT11_INEPNAKEFF_LSB 0x6
+#define GC_USB_DIEPINT11_INEPNAKEFF_MASK 0x40
+#define GC_USB_DIEPINT11_INEPNAKEFF_SIZE 0x1
+#define GC_USB_DIEPINT11_INEPNAKEFF_DEFAULT 0x0
+#define GC_USB_DIEPINT11_INEPNAKEFF_OFFSET 0xa68
+#define GC_USB_DIEPINT11_TXFEMP_LSB 0x7
+#define GC_USB_DIEPINT11_TXFEMP_MASK 0x80
+#define GC_USB_DIEPINT11_TXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT11_TXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT11_TXFEMP_OFFSET 0xa68
+#define GC_USB_DIEPINT11_TXFIFOUNDRN_LSB 0x8
+#define GC_USB_DIEPINT11_TXFIFOUNDRN_MASK 0x100
+#define GC_USB_DIEPINT11_TXFIFOUNDRN_SIZE 0x1
+#define GC_USB_DIEPINT11_TXFIFOUNDRN_DEFAULT 0x0
+#define GC_USB_DIEPINT11_TXFIFOUNDRN_OFFSET 0xa68
+#define GC_USB_DIEPINT11_BNAINTR_LSB 0x9
+#define GC_USB_DIEPINT11_BNAINTR_MASK 0x200
+#define GC_USB_DIEPINT11_BNAINTR_SIZE 0x1
+#define GC_USB_DIEPINT11_BNAINTR_DEFAULT 0x0
+#define GC_USB_DIEPINT11_BNAINTR_OFFSET 0xa68
+#define GC_USB_DIEPINT11_PKTDRPSTS_LSB 0xb
+#define GC_USB_DIEPINT11_PKTDRPSTS_MASK 0x800
+#define GC_USB_DIEPINT11_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DIEPINT11_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DIEPINT11_PKTDRPSTS_OFFSET 0xa68
+#define GC_USB_DIEPINT11_BBLEERR_LSB 0xc
+#define GC_USB_DIEPINT11_BBLEERR_MASK 0x1000
+#define GC_USB_DIEPINT11_BBLEERR_SIZE 0x1
+#define GC_USB_DIEPINT11_BBLEERR_DEFAULT 0x0
+#define GC_USB_DIEPINT11_BBLEERR_OFFSET 0xa68
+#define GC_USB_DIEPINT11_NAKINTRPT_LSB 0xd
+#define GC_USB_DIEPINT11_NAKINTRPT_MASK 0x2000
+#define GC_USB_DIEPINT11_NAKINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT11_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT11_NAKINTRPT_OFFSET 0xa68
+#define GC_USB_DIEPINT11_NYETINTRPT_LSB 0xe
+#define GC_USB_DIEPINT11_NYETINTRPT_MASK 0x4000
+#define GC_USB_DIEPINT11_NYETINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT11_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT11_NYETINTRPT_OFFSET 0xa68
+#define GC_USB_DIEPTSIZ11_XFERSIZE_LSB 0x0
+#define GC_USB_DIEPTSIZ11_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DIEPTSIZ11_XFERSIZE_SIZE 0x13
+#define GC_USB_DIEPTSIZ11_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ11_XFERSIZE_OFFSET 0xa70
+#define GC_USB_DIEPTSIZ11_PKTCNT_LSB 0x13
+#define GC_USB_DIEPTSIZ11_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DIEPTSIZ11_PKTCNT_SIZE 0xa
+#define GC_USB_DIEPTSIZ11_PKTCNT_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ11_PKTCNT_OFFSET 0xa70
+#define GC_USB_DIEPTSIZ11_MC_LSB 0x1d
+#define GC_USB_DIEPTSIZ11_MC_MASK 0x60000000
+#define GC_USB_DIEPTSIZ11_MC_SIZE 0x2
+#define GC_USB_DIEPTSIZ11_MC_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ11_MC_OFFSET 0xa70
+#define GC_USB_DIEPDMA11_DMAADDR_LSB 0x0
+#define GC_USB_DIEPDMA11_DMAADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMA11_DMAADDR_SIZE 0x20
+#define GC_USB_DIEPDMA11_DMAADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMA11_DMAADDR_OFFSET 0xa74
+#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_LSB 0x0
+#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_MASK 0xffff
+#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_SIZE 0x10
 #define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_DEFAULT 0x0
-#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_OFFSET  0xa78
-#define GC_USB_DIEPDMAB11_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DIEPDMAB11_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DIEPDMAB11_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DIEPDMAB11_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DIEPDMAB11_DMABUFFERADDR_OFFSET   0xa7c
-#define GC_USB_DIEPCTL12_MPS_LSB                 0x0
-#define GC_USB_DIEPCTL12_MPS_MASK                0x7ff
-#define GC_USB_DIEPCTL12_MPS_SIZE                0xb
-#define GC_USB_DIEPCTL12_MPS_DEFAULT             0x0
-#define GC_USB_DIEPCTL12_MPS_OFFSET              0xa80
-#define GC_USB_DIEPCTL12_USBACTEP_LSB            0xf
-#define GC_USB_DIEPCTL12_USBACTEP_MASK           0x8000
-#define GC_USB_DIEPCTL12_USBACTEP_SIZE           0x1
-#define GC_USB_DIEPCTL12_USBACTEP_DEFAULT        0x0
-#define GC_USB_DIEPCTL12_USBACTEP_OFFSET         0xa80
-#define GC_USB_DIEPCTL12_DPID_LSB                0x10
-#define GC_USB_DIEPCTL12_DPID_MASK               0x10000
-#define GC_USB_DIEPCTL12_DPID_SIZE               0x1
-#define GC_USB_DIEPCTL12_DPID_DEFAULT            0x0
-#define GC_USB_DIEPCTL12_DPID_OFFSET             0xa80
-#define GC_USB_DIEPCTL12_NAKSTS_LSB              0x11
-#define GC_USB_DIEPCTL12_NAKSTS_MASK             0x20000
-#define GC_USB_DIEPCTL12_NAKSTS_SIZE             0x1
-#define GC_USB_DIEPCTL12_NAKSTS_DEFAULT          0x0
-#define GC_USB_DIEPCTL12_NAKSTS_OFFSET           0xa80
-#define GC_USB_DIEPCTL12_EPTYPE_LSB              0x12
-#define GC_USB_DIEPCTL12_EPTYPE_MASK             0xc0000
-#define GC_USB_DIEPCTL12_EPTYPE_SIZE             0x2
-#define GC_USB_DIEPCTL12_EPTYPE_DEFAULT          0x0
-#define GC_USB_DIEPCTL12_EPTYPE_OFFSET           0xa80
-#define GC_USB_DIEPCTL12_STALL_LSB               0x15
-#define GC_USB_DIEPCTL12_STALL_MASK              0x200000
-#define GC_USB_DIEPCTL12_STALL_SIZE              0x1
-#define GC_USB_DIEPCTL12_STALL_DEFAULT           0x0
-#define GC_USB_DIEPCTL12_STALL_OFFSET            0xa80
-#define GC_USB_DIEPCTL12_TXFNUM_LSB              0x16
-#define GC_USB_DIEPCTL12_TXFNUM_MASK             0x3c00000
-#define GC_USB_DIEPCTL12_TXFNUM_SIZE             0x4
-#define GC_USB_DIEPCTL12_TXFNUM_DEFAULT          0x0
-#define GC_USB_DIEPCTL12_TXFNUM_OFFSET           0xa80
-#define GC_USB_DIEPCTL12_CNAK_LSB                0x1a
-#define GC_USB_DIEPCTL12_CNAK_MASK               0x4000000
-#define GC_USB_DIEPCTL12_CNAK_SIZE               0x1
-#define GC_USB_DIEPCTL12_CNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL12_CNAK_OFFSET             0xa80
-#define GC_USB_DIEPCTL12_SNAK_LSB                0x1b
-#define GC_USB_DIEPCTL12_SNAK_MASK               0x8000000
-#define GC_USB_DIEPCTL12_SNAK_SIZE               0x1
-#define GC_USB_DIEPCTL12_SNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL12_SNAK_OFFSET             0xa80
-#define GC_USB_DIEPCTL12_SETD0PID_LSB            0x1c
-#define GC_USB_DIEPCTL12_SETD0PID_MASK           0x10000000
-#define GC_USB_DIEPCTL12_SETD0PID_SIZE           0x1
-#define GC_USB_DIEPCTL12_SETD0PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL12_SETD0PID_OFFSET         0xa80
-#define GC_USB_DIEPCTL12_SETD1PID_LSB            0x1d
-#define GC_USB_DIEPCTL12_SETD1PID_MASK           0x20000000
-#define GC_USB_DIEPCTL12_SETD1PID_SIZE           0x1
-#define GC_USB_DIEPCTL12_SETD1PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL12_SETD1PID_OFFSET         0xa80
-#define GC_USB_DIEPCTL12_EPDIS_LSB               0x1e
-#define GC_USB_DIEPCTL12_EPDIS_MASK              0x40000000
-#define GC_USB_DIEPCTL12_EPDIS_SIZE              0x1
-#define GC_USB_DIEPCTL12_EPDIS_DEFAULT           0x0
-#define GC_USB_DIEPCTL12_EPDIS_OFFSET            0xa80
-#define GC_USB_DIEPCTL12_EPENA_LSB               0x1f
-#define GC_USB_DIEPCTL12_EPENA_MASK              0x80000000
-#define GC_USB_DIEPCTL12_EPENA_SIZE              0x1
-#define GC_USB_DIEPCTL12_EPENA_DEFAULT           0x0
-#define GC_USB_DIEPCTL12_EPENA_OFFSET            0xa80
-#define GC_USB_DIEPINT12_XFERCOMPL_LSB           0x0
-#define GC_USB_DIEPINT12_XFERCOMPL_MASK          0x1
-#define GC_USB_DIEPINT12_XFERCOMPL_SIZE          0x1
-#define GC_USB_DIEPINT12_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DIEPINT12_XFERCOMPL_OFFSET        0xa88
-#define GC_USB_DIEPINT12_EPDISBLD_LSB            0x1
-#define GC_USB_DIEPINT12_EPDISBLD_MASK           0x2
-#define GC_USB_DIEPINT12_EPDISBLD_SIZE           0x1
-#define GC_USB_DIEPINT12_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DIEPINT12_EPDISBLD_OFFSET         0xa88
-#define GC_USB_DIEPINT12_AHBERR_LSB              0x2
-#define GC_USB_DIEPINT12_AHBERR_MASK             0x4
-#define GC_USB_DIEPINT12_AHBERR_SIZE             0x1
-#define GC_USB_DIEPINT12_AHBERR_DEFAULT          0x0
-#define GC_USB_DIEPINT12_AHBERR_OFFSET           0xa88
-#define GC_USB_DIEPINT12_TIMEOUT_LSB             0x3
-#define GC_USB_DIEPINT12_TIMEOUT_MASK            0x8
-#define GC_USB_DIEPINT12_TIMEOUT_SIZE            0x1
-#define GC_USB_DIEPINT12_TIMEOUT_DEFAULT         0x0
-#define GC_USB_DIEPINT12_TIMEOUT_OFFSET          0xa88
-#define GC_USB_DIEPINT12_INTKNTXFEMP_LSB         0x4
-#define GC_USB_DIEPINT12_INTKNTXFEMP_MASK        0x10
-#define GC_USB_DIEPINT12_INTKNTXFEMP_SIZE        0x1
-#define GC_USB_DIEPINT12_INTKNTXFEMP_DEFAULT     0x0
-#define GC_USB_DIEPINT12_INTKNTXFEMP_OFFSET      0xa88
-#define GC_USB_DIEPINT12_INTKNEPMIS_LSB          0x5
-#define GC_USB_DIEPINT12_INTKNEPMIS_MASK         0x20
-#define GC_USB_DIEPINT12_INTKNEPMIS_SIZE         0x1
-#define GC_USB_DIEPINT12_INTKNEPMIS_DEFAULT      0x0
-#define GC_USB_DIEPINT12_INTKNEPMIS_OFFSET       0xa88
-#define GC_USB_DIEPINT12_INEPNAKEFF_LSB          0x6
-#define GC_USB_DIEPINT12_INEPNAKEFF_MASK         0x40
-#define GC_USB_DIEPINT12_INEPNAKEFF_SIZE         0x1
-#define GC_USB_DIEPINT12_INEPNAKEFF_DEFAULT      0x0
-#define GC_USB_DIEPINT12_INEPNAKEFF_OFFSET       0xa88
-#define GC_USB_DIEPINT12_TXFEMP_LSB              0x7
-#define GC_USB_DIEPINT12_TXFEMP_MASK             0x80
-#define GC_USB_DIEPINT12_TXFEMP_SIZE             0x1
-#define GC_USB_DIEPINT12_TXFEMP_DEFAULT          0x0
-#define GC_USB_DIEPINT12_TXFEMP_OFFSET           0xa88
-#define GC_USB_DIEPINT12_TXFIFOUNDRN_LSB         0x8
-#define GC_USB_DIEPINT12_TXFIFOUNDRN_MASK        0x100
-#define GC_USB_DIEPINT12_TXFIFOUNDRN_SIZE        0x1
-#define GC_USB_DIEPINT12_TXFIFOUNDRN_DEFAULT     0x0
-#define GC_USB_DIEPINT12_TXFIFOUNDRN_OFFSET      0xa88
-#define GC_USB_DIEPINT12_BNAINTR_LSB             0x9
-#define GC_USB_DIEPINT12_BNAINTR_MASK            0x200
-#define GC_USB_DIEPINT12_BNAINTR_SIZE            0x1
-#define GC_USB_DIEPINT12_BNAINTR_DEFAULT         0x0
-#define GC_USB_DIEPINT12_BNAINTR_OFFSET          0xa88
-#define GC_USB_DIEPINT12_PKTDRPSTS_LSB           0xb
-#define GC_USB_DIEPINT12_PKTDRPSTS_MASK          0x800
-#define GC_USB_DIEPINT12_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DIEPINT12_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DIEPINT12_PKTDRPSTS_OFFSET        0xa88
-#define GC_USB_DIEPINT12_BBLEERR_LSB             0xc
-#define GC_USB_DIEPINT12_BBLEERR_MASK            0x1000
-#define GC_USB_DIEPINT12_BBLEERR_SIZE            0x1
-#define GC_USB_DIEPINT12_BBLEERR_DEFAULT         0x0
-#define GC_USB_DIEPINT12_BBLEERR_OFFSET          0xa88
-#define GC_USB_DIEPINT12_NAKINTRPT_LSB           0xd
-#define GC_USB_DIEPINT12_NAKINTRPT_MASK          0x2000
-#define GC_USB_DIEPINT12_NAKINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT12_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT12_NAKINTRPT_OFFSET        0xa88
-#define GC_USB_DIEPINT12_NYETINTRPT_LSB          0xe
-#define GC_USB_DIEPINT12_NYETINTRPT_MASK         0x4000
-#define GC_USB_DIEPINT12_NYETINTRPT_SIZE         0x1
-#define GC_USB_DIEPINT12_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DIEPINT12_NYETINTRPT_OFFSET       0xa88
-#define GC_USB_DIEPTSIZ12_XFERSIZE_LSB           0x0
-#define GC_USB_DIEPTSIZ12_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DIEPTSIZ12_XFERSIZE_SIZE          0x13
-#define GC_USB_DIEPTSIZ12_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DIEPTSIZ12_XFERSIZE_OFFSET        0xa90
-#define GC_USB_DIEPTSIZ12_PKTCNT_LSB             0x13
-#define GC_USB_DIEPTSIZ12_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DIEPTSIZ12_PKTCNT_SIZE            0xa
-#define GC_USB_DIEPTSIZ12_PKTCNT_DEFAULT         0x0
-#define GC_USB_DIEPTSIZ12_PKTCNT_OFFSET          0xa90
-#define GC_USB_DIEPTSIZ12_MC_LSB                 0x1d
-#define GC_USB_DIEPTSIZ12_MC_MASK                0x60000000
-#define GC_USB_DIEPTSIZ12_MC_SIZE                0x2
-#define GC_USB_DIEPTSIZ12_MC_DEFAULT             0x0
-#define GC_USB_DIEPTSIZ12_MC_OFFSET              0xa90
-#define GC_USB_DIEPDMA12_DMAADDR_LSB             0x0
-#define GC_USB_DIEPDMA12_DMAADDR_MASK            0xffffffff
-#define GC_USB_DIEPDMA12_DMAADDR_SIZE            0x20
-#define GC_USB_DIEPDMA12_DMAADDR_DEFAULT         0x0
-#define GC_USB_DIEPDMA12_DMAADDR_OFFSET          0xa94
-#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_LSB     0x0
-#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_MASK    0xffff
-#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_SIZE    0x10
+#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_OFFSET 0xa78
+#define GC_USB_DIEPDMAB11_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DIEPDMAB11_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMAB11_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DIEPDMAB11_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMAB11_DMABUFFERADDR_OFFSET 0xa7c
+#define GC_USB_DIEPCTL12_MPS_LSB 0x0
+#define GC_USB_DIEPCTL12_MPS_MASK 0x7ff
+#define GC_USB_DIEPCTL12_MPS_SIZE 0xb
+#define GC_USB_DIEPCTL12_MPS_DEFAULT 0x0
+#define GC_USB_DIEPCTL12_MPS_OFFSET 0xa80
+#define GC_USB_DIEPCTL12_USBACTEP_LSB 0xf
+#define GC_USB_DIEPCTL12_USBACTEP_MASK 0x8000
+#define GC_USB_DIEPCTL12_USBACTEP_SIZE 0x1
+#define GC_USB_DIEPCTL12_USBACTEP_DEFAULT 0x0
+#define GC_USB_DIEPCTL12_USBACTEP_OFFSET 0xa80
+#define GC_USB_DIEPCTL12_DPID_LSB 0x10
+#define GC_USB_DIEPCTL12_DPID_MASK 0x10000
+#define GC_USB_DIEPCTL12_DPID_SIZE 0x1
+#define GC_USB_DIEPCTL12_DPID_DEFAULT 0x0
+#define GC_USB_DIEPCTL12_DPID_OFFSET 0xa80
+#define GC_USB_DIEPCTL12_NAKSTS_LSB 0x11
+#define GC_USB_DIEPCTL12_NAKSTS_MASK 0x20000
+#define GC_USB_DIEPCTL12_NAKSTS_SIZE 0x1
+#define GC_USB_DIEPCTL12_NAKSTS_DEFAULT 0x0
+#define GC_USB_DIEPCTL12_NAKSTS_OFFSET 0xa80
+#define GC_USB_DIEPCTL12_EPTYPE_LSB 0x12
+#define GC_USB_DIEPCTL12_EPTYPE_MASK 0xc0000
+#define GC_USB_DIEPCTL12_EPTYPE_SIZE 0x2
+#define GC_USB_DIEPCTL12_EPTYPE_DEFAULT 0x0
+#define GC_USB_DIEPCTL12_EPTYPE_OFFSET 0xa80
+#define GC_USB_DIEPCTL12_STALL_LSB 0x15
+#define GC_USB_DIEPCTL12_STALL_MASK 0x200000
+#define GC_USB_DIEPCTL12_STALL_SIZE 0x1
+#define GC_USB_DIEPCTL12_STALL_DEFAULT 0x0
+#define GC_USB_DIEPCTL12_STALL_OFFSET 0xa80
+#define GC_USB_DIEPCTL12_TXFNUM_LSB 0x16
+#define GC_USB_DIEPCTL12_TXFNUM_MASK 0x3c00000
+#define GC_USB_DIEPCTL12_TXFNUM_SIZE 0x4
+#define GC_USB_DIEPCTL12_TXFNUM_DEFAULT 0x0
+#define GC_USB_DIEPCTL12_TXFNUM_OFFSET 0xa80
+#define GC_USB_DIEPCTL12_CNAK_LSB 0x1a
+#define GC_USB_DIEPCTL12_CNAK_MASK 0x4000000
+#define GC_USB_DIEPCTL12_CNAK_SIZE 0x1
+#define GC_USB_DIEPCTL12_CNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL12_CNAK_OFFSET 0xa80
+#define GC_USB_DIEPCTL12_SNAK_LSB 0x1b
+#define GC_USB_DIEPCTL12_SNAK_MASK 0x8000000
+#define GC_USB_DIEPCTL12_SNAK_SIZE 0x1
+#define GC_USB_DIEPCTL12_SNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL12_SNAK_OFFSET 0xa80
+#define GC_USB_DIEPCTL12_SETD0PID_LSB 0x1c
+#define GC_USB_DIEPCTL12_SETD0PID_MASK 0x10000000
+#define GC_USB_DIEPCTL12_SETD0PID_SIZE 0x1
+#define GC_USB_DIEPCTL12_SETD0PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL12_SETD0PID_OFFSET 0xa80
+#define GC_USB_DIEPCTL12_SETD1PID_LSB 0x1d
+#define GC_USB_DIEPCTL12_SETD1PID_MASK 0x20000000
+#define GC_USB_DIEPCTL12_SETD1PID_SIZE 0x1
+#define GC_USB_DIEPCTL12_SETD1PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL12_SETD1PID_OFFSET 0xa80
+#define GC_USB_DIEPCTL12_EPDIS_LSB 0x1e
+#define GC_USB_DIEPCTL12_EPDIS_MASK 0x40000000
+#define GC_USB_DIEPCTL12_EPDIS_SIZE 0x1
+#define GC_USB_DIEPCTL12_EPDIS_DEFAULT 0x0
+#define GC_USB_DIEPCTL12_EPDIS_OFFSET 0xa80
+#define GC_USB_DIEPCTL12_EPENA_LSB 0x1f
+#define GC_USB_DIEPCTL12_EPENA_MASK 0x80000000
+#define GC_USB_DIEPCTL12_EPENA_SIZE 0x1
+#define GC_USB_DIEPCTL12_EPENA_DEFAULT 0x0
+#define GC_USB_DIEPCTL12_EPENA_OFFSET 0xa80
+#define GC_USB_DIEPINT12_XFERCOMPL_LSB 0x0
+#define GC_USB_DIEPINT12_XFERCOMPL_MASK 0x1
+#define GC_USB_DIEPINT12_XFERCOMPL_SIZE 0x1
+#define GC_USB_DIEPINT12_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DIEPINT12_XFERCOMPL_OFFSET 0xa88
+#define GC_USB_DIEPINT12_EPDISBLD_LSB 0x1
+#define GC_USB_DIEPINT12_EPDISBLD_MASK 0x2
+#define GC_USB_DIEPINT12_EPDISBLD_SIZE 0x1
+#define GC_USB_DIEPINT12_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DIEPINT12_EPDISBLD_OFFSET 0xa88
+#define GC_USB_DIEPINT12_AHBERR_LSB 0x2
+#define GC_USB_DIEPINT12_AHBERR_MASK 0x4
+#define GC_USB_DIEPINT12_AHBERR_SIZE 0x1
+#define GC_USB_DIEPINT12_AHBERR_DEFAULT 0x0
+#define GC_USB_DIEPINT12_AHBERR_OFFSET 0xa88
+#define GC_USB_DIEPINT12_TIMEOUT_LSB 0x3
+#define GC_USB_DIEPINT12_TIMEOUT_MASK 0x8
+#define GC_USB_DIEPINT12_TIMEOUT_SIZE 0x1
+#define GC_USB_DIEPINT12_TIMEOUT_DEFAULT 0x0
+#define GC_USB_DIEPINT12_TIMEOUT_OFFSET 0xa88
+#define GC_USB_DIEPINT12_INTKNTXFEMP_LSB 0x4
+#define GC_USB_DIEPINT12_INTKNTXFEMP_MASK 0x10
+#define GC_USB_DIEPINT12_INTKNTXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT12_INTKNTXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT12_INTKNTXFEMP_OFFSET 0xa88
+#define GC_USB_DIEPINT12_INTKNEPMIS_LSB 0x5
+#define GC_USB_DIEPINT12_INTKNEPMIS_MASK 0x20
+#define GC_USB_DIEPINT12_INTKNEPMIS_SIZE 0x1
+#define GC_USB_DIEPINT12_INTKNEPMIS_DEFAULT 0x0
+#define GC_USB_DIEPINT12_INTKNEPMIS_OFFSET 0xa88
+#define GC_USB_DIEPINT12_INEPNAKEFF_LSB 0x6
+#define GC_USB_DIEPINT12_INEPNAKEFF_MASK 0x40
+#define GC_USB_DIEPINT12_INEPNAKEFF_SIZE 0x1
+#define GC_USB_DIEPINT12_INEPNAKEFF_DEFAULT 0x0
+#define GC_USB_DIEPINT12_INEPNAKEFF_OFFSET 0xa88
+#define GC_USB_DIEPINT12_TXFEMP_LSB 0x7
+#define GC_USB_DIEPINT12_TXFEMP_MASK 0x80
+#define GC_USB_DIEPINT12_TXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT12_TXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT12_TXFEMP_OFFSET 0xa88
+#define GC_USB_DIEPINT12_TXFIFOUNDRN_LSB 0x8
+#define GC_USB_DIEPINT12_TXFIFOUNDRN_MASK 0x100
+#define GC_USB_DIEPINT12_TXFIFOUNDRN_SIZE 0x1
+#define GC_USB_DIEPINT12_TXFIFOUNDRN_DEFAULT 0x0
+#define GC_USB_DIEPINT12_TXFIFOUNDRN_OFFSET 0xa88
+#define GC_USB_DIEPINT12_BNAINTR_LSB 0x9
+#define GC_USB_DIEPINT12_BNAINTR_MASK 0x200
+#define GC_USB_DIEPINT12_BNAINTR_SIZE 0x1
+#define GC_USB_DIEPINT12_BNAINTR_DEFAULT 0x0
+#define GC_USB_DIEPINT12_BNAINTR_OFFSET 0xa88
+#define GC_USB_DIEPINT12_PKTDRPSTS_LSB 0xb
+#define GC_USB_DIEPINT12_PKTDRPSTS_MASK 0x800
+#define GC_USB_DIEPINT12_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DIEPINT12_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DIEPINT12_PKTDRPSTS_OFFSET 0xa88
+#define GC_USB_DIEPINT12_BBLEERR_LSB 0xc
+#define GC_USB_DIEPINT12_BBLEERR_MASK 0x1000
+#define GC_USB_DIEPINT12_BBLEERR_SIZE 0x1
+#define GC_USB_DIEPINT12_BBLEERR_DEFAULT 0x0
+#define GC_USB_DIEPINT12_BBLEERR_OFFSET 0xa88
+#define GC_USB_DIEPINT12_NAKINTRPT_LSB 0xd
+#define GC_USB_DIEPINT12_NAKINTRPT_MASK 0x2000
+#define GC_USB_DIEPINT12_NAKINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT12_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT12_NAKINTRPT_OFFSET 0xa88
+#define GC_USB_DIEPINT12_NYETINTRPT_LSB 0xe
+#define GC_USB_DIEPINT12_NYETINTRPT_MASK 0x4000
+#define GC_USB_DIEPINT12_NYETINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT12_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT12_NYETINTRPT_OFFSET 0xa88
+#define GC_USB_DIEPTSIZ12_XFERSIZE_LSB 0x0
+#define GC_USB_DIEPTSIZ12_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DIEPTSIZ12_XFERSIZE_SIZE 0x13
+#define GC_USB_DIEPTSIZ12_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ12_XFERSIZE_OFFSET 0xa90
+#define GC_USB_DIEPTSIZ12_PKTCNT_LSB 0x13
+#define GC_USB_DIEPTSIZ12_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DIEPTSIZ12_PKTCNT_SIZE 0xa
+#define GC_USB_DIEPTSIZ12_PKTCNT_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ12_PKTCNT_OFFSET 0xa90
+#define GC_USB_DIEPTSIZ12_MC_LSB 0x1d
+#define GC_USB_DIEPTSIZ12_MC_MASK 0x60000000
+#define GC_USB_DIEPTSIZ12_MC_SIZE 0x2
+#define GC_USB_DIEPTSIZ12_MC_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ12_MC_OFFSET 0xa90
+#define GC_USB_DIEPDMA12_DMAADDR_LSB 0x0
+#define GC_USB_DIEPDMA12_DMAADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMA12_DMAADDR_SIZE 0x20
+#define GC_USB_DIEPDMA12_DMAADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMA12_DMAADDR_OFFSET 0xa94
+#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_LSB 0x0
+#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_MASK 0xffff
+#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_SIZE 0x10
 #define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_DEFAULT 0x0
-#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_OFFSET  0xa98
-#define GC_USB_DIEPDMAB12_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DIEPDMAB12_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DIEPDMAB12_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DIEPDMAB12_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DIEPDMAB12_DMABUFFERADDR_OFFSET   0xa9c
-#define GC_USB_DIEPCTL13_MPS_LSB                 0x0
-#define GC_USB_DIEPCTL13_MPS_MASK                0x7ff
-#define GC_USB_DIEPCTL13_MPS_SIZE                0xb
-#define GC_USB_DIEPCTL13_MPS_DEFAULT             0x0
-#define GC_USB_DIEPCTL13_MPS_OFFSET              0xaa0
-#define GC_USB_DIEPCTL13_USBACTEP_LSB            0xf
-#define GC_USB_DIEPCTL13_USBACTEP_MASK           0x8000
-#define GC_USB_DIEPCTL13_USBACTEP_SIZE           0x1
-#define GC_USB_DIEPCTL13_USBACTEP_DEFAULT        0x0
-#define GC_USB_DIEPCTL13_USBACTEP_OFFSET         0xaa0
-#define GC_USB_DIEPCTL13_DPID_LSB                0x10
-#define GC_USB_DIEPCTL13_DPID_MASK               0x10000
-#define GC_USB_DIEPCTL13_DPID_SIZE               0x1
-#define GC_USB_DIEPCTL13_DPID_DEFAULT            0x0
-#define GC_USB_DIEPCTL13_DPID_OFFSET             0xaa0
-#define GC_USB_DIEPCTL13_NAKSTS_LSB              0x11
-#define GC_USB_DIEPCTL13_NAKSTS_MASK             0x20000
-#define GC_USB_DIEPCTL13_NAKSTS_SIZE             0x1
-#define GC_USB_DIEPCTL13_NAKSTS_DEFAULT          0x0
-#define GC_USB_DIEPCTL13_NAKSTS_OFFSET           0xaa0
-#define GC_USB_DIEPCTL13_EPTYPE_LSB              0x12
-#define GC_USB_DIEPCTL13_EPTYPE_MASK             0xc0000
-#define GC_USB_DIEPCTL13_EPTYPE_SIZE             0x2
-#define GC_USB_DIEPCTL13_EPTYPE_DEFAULT          0x0
-#define GC_USB_DIEPCTL13_EPTYPE_OFFSET           0xaa0
-#define GC_USB_DIEPCTL13_STALL_LSB               0x15
-#define GC_USB_DIEPCTL13_STALL_MASK              0x200000
-#define GC_USB_DIEPCTL13_STALL_SIZE              0x1
-#define GC_USB_DIEPCTL13_STALL_DEFAULT           0x0
-#define GC_USB_DIEPCTL13_STALL_OFFSET            0xaa0
-#define GC_USB_DIEPCTL13_TXFNUM_LSB              0x16
-#define GC_USB_DIEPCTL13_TXFNUM_MASK             0x3c00000
-#define GC_USB_DIEPCTL13_TXFNUM_SIZE             0x4
-#define GC_USB_DIEPCTL13_TXFNUM_DEFAULT          0x0
-#define GC_USB_DIEPCTL13_TXFNUM_OFFSET           0xaa0
-#define GC_USB_DIEPCTL13_CNAK_LSB                0x1a
-#define GC_USB_DIEPCTL13_CNAK_MASK               0x4000000
-#define GC_USB_DIEPCTL13_CNAK_SIZE               0x1
-#define GC_USB_DIEPCTL13_CNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL13_CNAK_OFFSET             0xaa0
-#define GC_USB_DIEPCTL13_SNAK_LSB                0x1b
-#define GC_USB_DIEPCTL13_SNAK_MASK               0x8000000
-#define GC_USB_DIEPCTL13_SNAK_SIZE               0x1
-#define GC_USB_DIEPCTL13_SNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL13_SNAK_OFFSET             0xaa0
-#define GC_USB_DIEPCTL13_SETD0PID_LSB            0x1c
-#define GC_USB_DIEPCTL13_SETD0PID_MASK           0x10000000
-#define GC_USB_DIEPCTL13_SETD0PID_SIZE           0x1
-#define GC_USB_DIEPCTL13_SETD0PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL13_SETD0PID_OFFSET         0xaa0
-#define GC_USB_DIEPCTL13_SETD1PID_LSB            0x1d
-#define GC_USB_DIEPCTL13_SETD1PID_MASK           0x20000000
-#define GC_USB_DIEPCTL13_SETD1PID_SIZE           0x1
-#define GC_USB_DIEPCTL13_SETD1PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL13_SETD1PID_OFFSET         0xaa0
-#define GC_USB_DIEPCTL13_EPDIS_LSB               0x1e
-#define GC_USB_DIEPCTL13_EPDIS_MASK              0x40000000
-#define GC_USB_DIEPCTL13_EPDIS_SIZE              0x1
-#define GC_USB_DIEPCTL13_EPDIS_DEFAULT           0x0
-#define GC_USB_DIEPCTL13_EPDIS_OFFSET            0xaa0
-#define GC_USB_DIEPCTL13_EPENA_LSB               0x1f
-#define GC_USB_DIEPCTL13_EPENA_MASK              0x80000000
-#define GC_USB_DIEPCTL13_EPENA_SIZE              0x1
-#define GC_USB_DIEPCTL13_EPENA_DEFAULT           0x0
-#define GC_USB_DIEPCTL13_EPENA_OFFSET            0xaa0
-#define GC_USB_DIEPINT13_XFERCOMPL_LSB           0x0
-#define GC_USB_DIEPINT13_XFERCOMPL_MASK          0x1
-#define GC_USB_DIEPINT13_XFERCOMPL_SIZE          0x1
-#define GC_USB_DIEPINT13_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DIEPINT13_XFERCOMPL_OFFSET        0xaa8
-#define GC_USB_DIEPINT13_EPDISBLD_LSB            0x1
-#define GC_USB_DIEPINT13_EPDISBLD_MASK           0x2
-#define GC_USB_DIEPINT13_EPDISBLD_SIZE           0x1
-#define GC_USB_DIEPINT13_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DIEPINT13_EPDISBLD_OFFSET         0xaa8
-#define GC_USB_DIEPINT13_AHBERR_LSB              0x2
-#define GC_USB_DIEPINT13_AHBERR_MASK             0x4
-#define GC_USB_DIEPINT13_AHBERR_SIZE             0x1
-#define GC_USB_DIEPINT13_AHBERR_DEFAULT          0x0
-#define GC_USB_DIEPINT13_AHBERR_OFFSET           0xaa8
-#define GC_USB_DIEPINT13_TIMEOUT_LSB             0x3
-#define GC_USB_DIEPINT13_TIMEOUT_MASK            0x8
-#define GC_USB_DIEPINT13_TIMEOUT_SIZE            0x1
-#define GC_USB_DIEPINT13_TIMEOUT_DEFAULT         0x0
-#define GC_USB_DIEPINT13_TIMEOUT_OFFSET          0xaa8
-#define GC_USB_DIEPINT13_INTKNTXFEMP_LSB         0x4
-#define GC_USB_DIEPINT13_INTKNTXFEMP_MASK        0x10
-#define GC_USB_DIEPINT13_INTKNTXFEMP_SIZE        0x1
-#define GC_USB_DIEPINT13_INTKNTXFEMP_DEFAULT     0x0
-#define GC_USB_DIEPINT13_INTKNTXFEMP_OFFSET      0xaa8
-#define GC_USB_DIEPINT13_INTKNEPMIS_LSB          0x5
-#define GC_USB_DIEPINT13_INTKNEPMIS_MASK         0x20
-#define GC_USB_DIEPINT13_INTKNEPMIS_SIZE         0x1
-#define GC_USB_DIEPINT13_INTKNEPMIS_DEFAULT      0x0
-#define GC_USB_DIEPINT13_INTKNEPMIS_OFFSET       0xaa8
-#define GC_USB_DIEPINT13_INEPNAKEFF_LSB          0x6
-#define GC_USB_DIEPINT13_INEPNAKEFF_MASK         0x40
-#define GC_USB_DIEPINT13_INEPNAKEFF_SIZE         0x1
-#define GC_USB_DIEPINT13_INEPNAKEFF_DEFAULT      0x0
-#define GC_USB_DIEPINT13_INEPNAKEFF_OFFSET       0xaa8
-#define GC_USB_DIEPINT13_TXFEMP_LSB              0x7
-#define GC_USB_DIEPINT13_TXFEMP_MASK             0x80
-#define GC_USB_DIEPINT13_TXFEMP_SIZE             0x1
-#define GC_USB_DIEPINT13_TXFEMP_DEFAULT          0x0
-#define GC_USB_DIEPINT13_TXFEMP_OFFSET           0xaa8
-#define GC_USB_DIEPINT13_TXFIFOUNDRN_LSB         0x8
-#define GC_USB_DIEPINT13_TXFIFOUNDRN_MASK        0x100
-#define GC_USB_DIEPINT13_TXFIFOUNDRN_SIZE        0x1
-#define GC_USB_DIEPINT13_TXFIFOUNDRN_DEFAULT     0x0
-#define GC_USB_DIEPINT13_TXFIFOUNDRN_OFFSET      0xaa8
-#define GC_USB_DIEPINT13_BNAINTR_LSB             0x9
-#define GC_USB_DIEPINT13_BNAINTR_MASK            0x200
-#define GC_USB_DIEPINT13_BNAINTR_SIZE            0x1
-#define GC_USB_DIEPINT13_BNAINTR_DEFAULT         0x0
-#define GC_USB_DIEPINT13_BNAINTR_OFFSET          0xaa8
-#define GC_USB_DIEPINT13_PKTDRPSTS_LSB           0xb
-#define GC_USB_DIEPINT13_PKTDRPSTS_MASK          0x800
-#define GC_USB_DIEPINT13_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DIEPINT13_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DIEPINT13_PKTDRPSTS_OFFSET        0xaa8
-#define GC_USB_DIEPINT13_BBLEERR_LSB             0xc
-#define GC_USB_DIEPINT13_BBLEERR_MASK            0x1000
-#define GC_USB_DIEPINT13_BBLEERR_SIZE            0x1
-#define GC_USB_DIEPINT13_BBLEERR_DEFAULT         0x0
-#define GC_USB_DIEPINT13_BBLEERR_OFFSET          0xaa8
-#define GC_USB_DIEPINT13_NAKINTRPT_LSB           0xd
-#define GC_USB_DIEPINT13_NAKINTRPT_MASK          0x2000
-#define GC_USB_DIEPINT13_NAKINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT13_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT13_NAKINTRPT_OFFSET        0xaa8
-#define GC_USB_DIEPINT13_NYETINTRPT_LSB          0xe
-#define GC_USB_DIEPINT13_NYETINTRPT_MASK         0x4000
-#define GC_USB_DIEPINT13_NYETINTRPT_SIZE         0x1
-#define GC_USB_DIEPINT13_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DIEPINT13_NYETINTRPT_OFFSET       0xaa8
-#define GC_USB_DIEPTSIZ13_XFERSIZE_LSB           0x0
-#define GC_USB_DIEPTSIZ13_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DIEPTSIZ13_XFERSIZE_SIZE          0x13
-#define GC_USB_DIEPTSIZ13_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DIEPTSIZ13_XFERSIZE_OFFSET        0xab0
-#define GC_USB_DIEPTSIZ13_PKTCNT_LSB             0x13
-#define GC_USB_DIEPTSIZ13_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DIEPTSIZ13_PKTCNT_SIZE            0xa
-#define GC_USB_DIEPTSIZ13_PKTCNT_DEFAULT         0x0
-#define GC_USB_DIEPTSIZ13_PKTCNT_OFFSET          0xab0
-#define GC_USB_DIEPTSIZ13_MC_LSB                 0x1d
-#define GC_USB_DIEPTSIZ13_MC_MASK                0x60000000
-#define GC_USB_DIEPTSIZ13_MC_SIZE                0x2
-#define GC_USB_DIEPTSIZ13_MC_DEFAULT             0x0
-#define GC_USB_DIEPTSIZ13_MC_OFFSET              0xab0
-#define GC_USB_DIEPDMA13_DMAADDR_LSB             0x0
-#define GC_USB_DIEPDMA13_DMAADDR_MASK            0xffffffff
-#define GC_USB_DIEPDMA13_DMAADDR_SIZE            0x20
-#define GC_USB_DIEPDMA13_DMAADDR_DEFAULT         0x0
-#define GC_USB_DIEPDMA13_DMAADDR_OFFSET          0xab4
-#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_LSB     0x0
-#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_MASK    0xffff
-#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_SIZE    0x10
+#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_OFFSET 0xa98
+#define GC_USB_DIEPDMAB12_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DIEPDMAB12_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMAB12_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DIEPDMAB12_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMAB12_DMABUFFERADDR_OFFSET 0xa9c
+#define GC_USB_DIEPCTL13_MPS_LSB 0x0
+#define GC_USB_DIEPCTL13_MPS_MASK 0x7ff
+#define GC_USB_DIEPCTL13_MPS_SIZE 0xb
+#define GC_USB_DIEPCTL13_MPS_DEFAULT 0x0
+#define GC_USB_DIEPCTL13_MPS_OFFSET 0xaa0
+#define GC_USB_DIEPCTL13_USBACTEP_LSB 0xf
+#define GC_USB_DIEPCTL13_USBACTEP_MASK 0x8000
+#define GC_USB_DIEPCTL13_USBACTEP_SIZE 0x1
+#define GC_USB_DIEPCTL13_USBACTEP_DEFAULT 0x0
+#define GC_USB_DIEPCTL13_USBACTEP_OFFSET 0xaa0
+#define GC_USB_DIEPCTL13_DPID_LSB 0x10
+#define GC_USB_DIEPCTL13_DPID_MASK 0x10000
+#define GC_USB_DIEPCTL13_DPID_SIZE 0x1
+#define GC_USB_DIEPCTL13_DPID_DEFAULT 0x0
+#define GC_USB_DIEPCTL13_DPID_OFFSET 0xaa0
+#define GC_USB_DIEPCTL13_NAKSTS_LSB 0x11
+#define GC_USB_DIEPCTL13_NAKSTS_MASK 0x20000
+#define GC_USB_DIEPCTL13_NAKSTS_SIZE 0x1
+#define GC_USB_DIEPCTL13_NAKSTS_DEFAULT 0x0
+#define GC_USB_DIEPCTL13_NAKSTS_OFFSET 0xaa0
+#define GC_USB_DIEPCTL13_EPTYPE_LSB 0x12
+#define GC_USB_DIEPCTL13_EPTYPE_MASK 0xc0000
+#define GC_USB_DIEPCTL13_EPTYPE_SIZE 0x2
+#define GC_USB_DIEPCTL13_EPTYPE_DEFAULT 0x0
+#define GC_USB_DIEPCTL13_EPTYPE_OFFSET 0xaa0
+#define GC_USB_DIEPCTL13_STALL_LSB 0x15
+#define GC_USB_DIEPCTL13_STALL_MASK 0x200000
+#define GC_USB_DIEPCTL13_STALL_SIZE 0x1
+#define GC_USB_DIEPCTL13_STALL_DEFAULT 0x0
+#define GC_USB_DIEPCTL13_STALL_OFFSET 0xaa0
+#define GC_USB_DIEPCTL13_TXFNUM_LSB 0x16
+#define GC_USB_DIEPCTL13_TXFNUM_MASK 0x3c00000
+#define GC_USB_DIEPCTL13_TXFNUM_SIZE 0x4
+#define GC_USB_DIEPCTL13_TXFNUM_DEFAULT 0x0
+#define GC_USB_DIEPCTL13_TXFNUM_OFFSET 0xaa0
+#define GC_USB_DIEPCTL13_CNAK_LSB 0x1a
+#define GC_USB_DIEPCTL13_CNAK_MASK 0x4000000
+#define GC_USB_DIEPCTL13_CNAK_SIZE 0x1
+#define GC_USB_DIEPCTL13_CNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL13_CNAK_OFFSET 0xaa0
+#define GC_USB_DIEPCTL13_SNAK_LSB 0x1b
+#define GC_USB_DIEPCTL13_SNAK_MASK 0x8000000
+#define GC_USB_DIEPCTL13_SNAK_SIZE 0x1
+#define GC_USB_DIEPCTL13_SNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL13_SNAK_OFFSET 0xaa0
+#define GC_USB_DIEPCTL13_SETD0PID_LSB 0x1c
+#define GC_USB_DIEPCTL13_SETD0PID_MASK 0x10000000
+#define GC_USB_DIEPCTL13_SETD0PID_SIZE 0x1
+#define GC_USB_DIEPCTL13_SETD0PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL13_SETD0PID_OFFSET 0xaa0
+#define GC_USB_DIEPCTL13_SETD1PID_LSB 0x1d
+#define GC_USB_DIEPCTL13_SETD1PID_MASK 0x20000000
+#define GC_USB_DIEPCTL13_SETD1PID_SIZE 0x1
+#define GC_USB_DIEPCTL13_SETD1PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL13_SETD1PID_OFFSET 0xaa0
+#define GC_USB_DIEPCTL13_EPDIS_LSB 0x1e
+#define GC_USB_DIEPCTL13_EPDIS_MASK 0x40000000
+#define GC_USB_DIEPCTL13_EPDIS_SIZE 0x1
+#define GC_USB_DIEPCTL13_EPDIS_DEFAULT 0x0
+#define GC_USB_DIEPCTL13_EPDIS_OFFSET 0xaa0
+#define GC_USB_DIEPCTL13_EPENA_LSB 0x1f
+#define GC_USB_DIEPCTL13_EPENA_MASK 0x80000000
+#define GC_USB_DIEPCTL13_EPENA_SIZE 0x1
+#define GC_USB_DIEPCTL13_EPENA_DEFAULT 0x0
+#define GC_USB_DIEPCTL13_EPENA_OFFSET 0xaa0
+#define GC_USB_DIEPINT13_XFERCOMPL_LSB 0x0
+#define GC_USB_DIEPINT13_XFERCOMPL_MASK 0x1
+#define GC_USB_DIEPINT13_XFERCOMPL_SIZE 0x1
+#define GC_USB_DIEPINT13_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DIEPINT13_XFERCOMPL_OFFSET 0xaa8
+#define GC_USB_DIEPINT13_EPDISBLD_LSB 0x1
+#define GC_USB_DIEPINT13_EPDISBLD_MASK 0x2
+#define GC_USB_DIEPINT13_EPDISBLD_SIZE 0x1
+#define GC_USB_DIEPINT13_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DIEPINT13_EPDISBLD_OFFSET 0xaa8
+#define GC_USB_DIEPINT13_AHBERR_LSB 0x2
+#define GC_USB_DIEPINT13_AHBERR_MASK 0x4
+#define GC_USB_DIEPINT13_AHBERR_SIZE 0x1
+#define GC_USB_DIEPINT13_AHBERR_DEFAULT 0x0
+#define GC_USB_DIEPINT13_AHBERR_OFFSET 0xaa8
+#define GC_USB_DIEPINT13_TIMEOUT_LSB 0x3
+#define GC_USB_DIEPINT13_TIMEOUT_MASK 0x8
+#define GC_USB_DIEPINT13_TIMEOUT_SIZE 0x1
+#define GC_USB_DIEPINT13_TIMEOUT_DEFAULT 0x0
+#define GC_USB_DIEPINT13_TIMEOUT_OFFSET 0xaa8
+#define GC_USB_DIEPINT13_INTKNTXFEMP_LSB 0x4
+#define GC_USB_DIEPINT13_INTKNTXFEMP_MASK 0x10
+#define GC_USB_DIEPINT13_INTKNTXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT13_INTKNTXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT13_INTKNTXFEMP_OFFSET 0xaa8
+#define GC_USB_DIEPINT13_INTKNEPMIS_LSB 0x5
+#define GC_USB_DIEPINT13_INTKNEPMIS_MASK 0x20
+#define GC_USB_DIEPINT13_INTKNEPMIS_SIZE 0x1
+#define GC_USB_DIEPINT13_INTKNEPMIS_DEFAULT 0x0
+#define GC_USB_DIEPINT13_INTKNEPMIS_OFFSET 0xaa8
+#define GC_USB_DIEPINT13_INEPNAKEFF_LSB 0x6
+#define GC_USB_DIEPINT13_INEPNAKEFF_MASK 0x40
+#define GC_USB_DIEPINT13_INEPNAKEFF_SIZE 0x1
+#define GC_USB_DIEPINT13_INEPNAKEFF_DEFAULT 0x0
+#define GC_USB_DIEPINT13_INEPNAKEFF_OFFSET 0xaa8
+#define GC_USB_DIEPINT13_TXFEMP_LSB 0x7
+#define GC_USB_DIEPINT13_TXFEMP_MASK 0x80
+#define GC_USB_DIEPINT13_TXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT13_TXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT13_TXFEMP_OFFSET 0xaa8
+#define GC_USB_DIEPINT13_TXFIFOUNDRN_LSB 0x8
+#define GC_USB_DIEPINT13_TXFIFOUNDRN_MASK 0x100
+#define GC_USB_DIEPINT13_TXFIFOUNDRN_SIZE 0x1
+#define GC_USB_DIEPINT13_TXFIFOUNDRN_DEFAULT 0x0
+#define GC_USB_DIEPINT13_TXFIFOUNDRN_OFFSET 0xaa8
+#define GC_USB_DIEPINT13_BNAINTR_LSB 0x9
+#define GC_USB_DIEPINT13_BNAINTR_MASK 0x200
+#define GC_USB_DIEPINT13_BNAINTR_SIZE 0x1
+#define GC_USB_DIEPINT13_BNAINTR_DEFAULT 0x0
+#define GC_USB_DIEPINT13_BNAINTR_OFFSET 0xaa8
+#define GC_USB_DIEPINT13_PKTDRPSTS_LSB 0xb
+#define GC_USB_DIEPINT13_PKTDRPSTS_MASK 0x800
+#define GC_USB_DIEPINT13_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DIEPINT13_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DIEPINT13_PKTDRPSTS_OFFSET 0xaa8
+#define GC_USB_DIEPINT13_BBLEERR_LSB 0xc
+#define GC_USB_DIEPINT13_BBLEERR_MASK 0x1000
+#define GC_USB_DIEPINT13_BBLEERR_SIZE 0x1
+#define GC_USB_DIEPINT13_BBLEERR_DEFAULT 0x0
+#define GC_USB_DIEPINT13_BBLEERR_OFFSET 0xaa8
+#define GC_USB_DIEPINT13_NAKINTRPT_LSB 0xd
+#define GC_USB_DIEPINT13_NAKINTRPT_MASK 0x2000
+#define GC_USB_DIEPINT13_NAKINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT13_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT13_NAKINTRPT_OFFSET 0xaa8
+#define GC_USB_DIEPINT13_NYETINTRPT_LSB 0xe
+#define GC_USB_DIEPINT13_NYETINTRPT_MASK 0x4000
+#define GC_USB_DIEPINT13_NYETINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT13_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT13_NYETINTRPT_OFFSET 0xaa8
+#define GC_USB_DIEPTSIZ13_XFERSIZE_LSB 0x0
+#define GC_USB_DIEPTSIZ13_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DIEPTSIZ13_XFERSIZE_SIZE 0x13
+#define GC_USB_DIEPTSIZ13_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ13_XFERSIZE_OFFSET 0xab0
+#define GC_USB_DIEPTSIZ13_PKTCNT_LSB 0x13
+#define GC_USB_DIEPTSIZ13_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DIEPTSIZ13_PKTCNT_SIZE 0xa
+#define GC_USB_DIEPTSIZ13_PKTCNT_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ13_PKTCNT_OFFSET 0xab0
+#define GC_USB_DIEPTSIZ13_MC_LSB 0x1d
+#define GC_USB_DIEPTSIZ13_MC_MASK 0x60000000
+#define GC_USB_DIEPTSIZ13_MC_SIZE 0x2
+#define GC_USB_DIEPTSIZ13_MC_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ13_MC_OFFSET 0xab0
+#define GC_USB_DIEPDMA13_DMAADDR_LSB 0x0
+#define GC_USB_DIEPDMA13_DMAADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMA13_DMAADDR_SIZE 0x20
+#define GC_USB_DIEPDMA13_DMAADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMA13_DMAADDR_OFFSET 0xab4
+#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_LSB 0x0
+#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_MASK 0xffff
+#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_SIZE 0x10
 #define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_DEFAULT 0x0
-#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_OFFSET  0xab8
-#define GC_USB_DIEPDMAB13_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DIEPDMAB13_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DIEPDMAB13_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DIEPDMAB13_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DIEPDMAB13_DMABUFFERADDR_OFFSET   0xabc
-#define GC_USB_DIEPCTL14_MPS_LSB                 0x0
-#define GC_USB_DIEPCTL14_MPS_MASK                0x7ff
-#define GC_USB_DIEPCTL14_MPS_SIZE                0xb
-#define GC_USB_DIEPCTL14_MPS_DEFAULT             0x0
-#define GC_USB_DIEPCTL14_MPS_OFFSET              0xac0
-#define GC_USB_DIEPCTL14_USBACTEP_LSB            0xf
-#define GC_USB_DIEPCTL14_USBACTEP_MASK           0x8000
-#define GC_USB_DIEPCTL14_USBACTEP_SIZE           0x1
-#define GC_USB_DIEPCTL14_USBACTEP_DEFAULT        0x0
-#define GC_USB_DIEPCTL14_USBACTEP_OFFSET         0xac0
-#define GC_USB_DIEPCTL14_DPID_LSB                0x10
-#define GC_USB_DIEPCTL14_DPID_MASK               0x10000
-#define GC_USB_DIEPCTL14_DPID_SIZE               0x1
-#define GC_USB_DIEPCTL14_DPID_DEFAULT            0x0
-#define GC_USB_DIEPCTL14_DPID_OFFSET             0xac0
-#define GC_USB_DIEPCTL14_NAKSTS_LSB              0x11
-#define GC_USB_DIEPCTL14_NAKSTS_MASK             0x20000
-#define GC_USB_DIEPCTL14_NAKSTS_SIZE             0x1
-#define GC_USB_DIEPCTL14_NAKSTS_DEFAULT          0x0
-#define GC_USB_DIEPCTL14_NAKSTS_OFFSET           0xac0
-#define GC_USB_DIEPCTL14_EPTYPE_LSB              0x12
-#define GC_USB_DIEPCTL14_EPTYPE_MASK             0xc0000
-#define GC_USB_DIEPCTL14_EPTYPE_SIZE             0x2
-#define GC_USB_DIEPCTL14_EPTYPE_DEFAULT          0x0
-#define GC_USB_DIEPCTL14_EPTYPE_OFFSET           0xac0
-#define GC_USB_DIEPCTL14_STALL_LSB               0x15
-#define GC_USB_DIEPCTL14_STALL_MASK              0x200000
-#define GC_USB_DIEPCTL14_STALL_SIZE              0x1
-#define GC_USB_DIEPCTL14_STALL_DEFAULT           0x0
-#define GC_USB_DIEPCTL14_STALL_OFFSET            0xac0
-#define GC_USB_DIEPCTL14_TXFNUM_LSB              0x16
-#define GC_USB_DIEPCTL14_TXFNUM_MASK             0x3c00000
-#define GC_USB_DIEPCTL14_TXFNUM_SIZE             0x4
-#define GC_USB_DIEPCTL14_TXFNUM_DEFAULT          0x0
-#define GC_USB_DIEPCTL14_TXFNUM_OFFSET           0xac0
-#define GC_USB_DIEPCTL14_CNAK_LSB                0x1a
-#define GC_USB_DIEPCTL14_CNAK_MASK               0x4000000
-#define GC_USB_DIEPCTL14_CNAK_SIZE               0x1
-#define GC_USB_DIEPCTL14_CNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL14_CNAK_OFFSET             0xac0
-#define GC_USB_DIEPCTL14_SNAK_LSB                0x1b
-#define GC_USB_DIEPCTL14_SNAK_MASK               0x8000000
-#define GC_USB_DIEPCTL14_SNAK_SIZE               0x1
-#define GC_USB_DIEPCTL14_SNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL14_SNAK_OFFSET             0xac0
-#define GC_USB_DIEPCTL14_SETD0PID_LSB            0x1c
-#define GC_USB_DIEPCTL14_SETD0PID_MASK           0x10000000
-#define GC_USB_DIEPCTL14_SETD0PID_SIZE           0x1
-#define GC_USB_DIEPCTL14_SETD0PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL14_SETD0PID_OFFSET         0xac0
-#define GC_USB_DIEPCTL14_SETD1PID_LSB            0x1d
-#define GC_USB_DIEPCTL14_SETD1PID_MASK           0x20000000
-#define GC_USB_DIEPCTL14_SETD1PID_SIZE           0x1
-#define GC_USB_DIEPCTL14_SETD1PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL14_SETD1PID_OFFSET         0xac0
-#define GC_USB_DIEPCTL14_EPDIS_LSB               0x1e
-#define GC_USB_DIEPCTL14_EPDIS_MASK              0x40000000
-#define GC_USB_DIEPCTL14_EPDIS_SIZE              0x1
-#define GC_USB_DIEPCTL14_EPDIS_DEFAULT           0x0
-#define GC_USB_DIEPCTL14_EPDIS_OFFSET            0xac0
-#define GC_USB_DIEPCTL14_EPENA_LSB               0x1f
-#define GC_USB_DIEPCTL14_EPENA_MASK              0x80000000
-#define GC_USB_DIEPCTL14_EPENA_SIZE              0x1
-#define GC_USB_DIEPCTL14_EPENA_DEFAULT           0x0
-#define GC_USB_DIEPCTL14_EPENA_OFFSET            0xac0
-#define GC_USB_DIEPINT14_XFERCOMPL_LSB           0x0
-#define GC_USB_DIEPINT14_XFERCOMPL_MASK          0x1
-#define GC_USB_DIEPINT14_XFERCOMPL_SIZE          0x1
-#define GC_USB_DIEPINT14_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DIEPINT14_XFERCOMPL_OFFSET        0xac8
-#define GC_USB_DIEPINT14_EPDISBLD_LSB            0x1
-#define GC_USB_DIEPINT14_EPDISBLD_MASK           0x2
-#define GC_USB_DIEPINT14_EPDISBLD_SIZE           0x1
-#define GC_USB_DIEPINT14_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DIEPINT14_EPDISBLD_OFFSET         0xac8
-#define GC_USB_DIEPINT14_AHBERR_LSB              0x2
-#define GC_USB_DIEPINT14_AHBERR_MASK             0x4
-#define GC_USB_DIEPINT14_AHBERR_SIZE             0x1
-#define GC_USB_DIEPINT14_AHBERR_DEFAULT          0x0
-#define GC_USB_DIEPINT14_AHBERR_OFFSET           0xac8
-#define GC_USB_DIEPINT14_TIMEOUT_LSB             0x3
-#define GC_USB_DIEPINT14_TIMEOUT_MASK            0x8
-#define GC_USB_DIEPINT14_TIMEOUT_SIZE            0x1
-#define GC_USB_DIEPINT14_TIMEOUT_DEFAULT         0x0
-#define GC_USB_DIEPINT14_TIMEOUT_OFFSET          0xac8
-#define GC_USB_DIEPINT14_INTKNTXFEMP_LSB         0x4
-#define GC_USB_DIEPINT14_INTKNTXFEMP_MASK        0x10
-#define GC_USB_DIEPINT14_INTKNTXFEMP_SIZE        0x1
-#define GC_USB_DIEPINT14_INTKNTXFEMP_DEFAULT     0x0
-#define GC_USB_DIEPINT14_INTKNTXFEMP_OFFSET      0xac8
-#define GC_USB_DIEPINT14_INTKNEPMIS_LSB          0x5
-#define GC_USB_DIEPINT14_INTKNEPMIS_MASK         0x20
-#define GC_USB_DIEPINT14_INTKNEPMIS_SIZE         0x1
-#define GC_USB_DIEPINT14_INTKNEPMIS_DEFAULT      0x0
-#define GC_USB_DIEPINT14_INTKNEPMIS_OFFSET       0xac8
-#define GC_USB_DIEPINT14_INEPNAKEFF_LSB          0x6
-#define GC_USB_DIEPINT14_INEPNAKEFF_MASK         0x40
-#define GC_USB_DIEPINT14_INEPNAKEFF_SIZE         0x1
-#define GC_USB_DIEPINT14_INEPNAKEFF_DEFAULT      0x0
-#define GC_USB_DIEPINT14_INEPNAKEFF_OFFSET       0xac8
-#define GC_USB_DIEPINT14_TXFEMP_LSB              0x7
-#define GC_USB_DIEPINT14_TXFEMP_MASK             0x80
-#define GC_USB_DIEPINT14_TXFEMP_SIZE             0x1
-#define GC_USB_DIEPINT14_TXFEMP_DEFAULT          0x0
-#define GC_USB_DIEPINT14_TXFEMP_OFFSET           0xac8
-#define GC_USB_DIEPINT14_TXFIFOUNDRN_LSB         0x8
-#define GC_USB_DIEPINT14_TXFIFOUNDRN_MASK        0x100
-#define GC_USB_DIEPINT14_TXFIFOUNDRN_SIZE        0x1
-#define GC_USB_DIEPINT14_TXFIFOUNDRN_DEFAULT     0x0
-#define GC_USB_DIEPINT14_TXFIFOUNDRN_OFFSET      0xac8
-#define GC_USB_DIEPINT14_BNAINTR_LSB             0x9
-#define GC_USB_DIEPINT14_BNAINTR_MASK            0x200
-#define GC_USB_DIEPINT14_BNAINTR_SIZE            0x1
-#define GC_USB_DIEPINT14_BNAINTR_DEFAULT         0x0
-#define GC_USB_DIEPINT14_BNAINTR_OFFSET          0xac8
-#define GC_USB_DIEPINT14_PKTDRPSTS_LSB           0xb
-#define GC_USB_DIEPINT14_PKTDRPSTS_MASK          0x800
-#define GC_USB_DIEPINT14_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DIEPINT14_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DIEPINT14_PKTDRPSTS_OFFSET        0xac8
-#define GC_USB_DIEPINT14_BBLEERR_LSB             0xc
-#define GC_USB_DIEPINT14_BBLEERR_MASK            0x1000
-#define GC_USB_DIEPINT14_BBLEERR_SIZE            0x1
-#define GC_USB_DIEPINT14_BBLEERR_DEFAULT         0x0
-#define GC_USB_DIEPINT14_BBLEERR_OFFSET          0xac8
-#define GC_USB_DIEPINT14_NAKINTRPT_LSB           0xd
-#define GC_USB_DIEPINT14_NAKINTRPT_MASK          0x2000
-#define GC_USB_DIEPINT14_NAKINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT14_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT14_NAKINTRPT_OFFSET        0xac8
-#define GC_USB_DIEPINT14_NYETINTRPT_LSB          0xe
-#define GC_USB_DIEPINT14_NYETINTRPT_MASK         0x4000
-#define GC_USB_DIEPINT14_NYETINTRPT_SIZE         0x1
-#define GC_USB_DIEPINT14_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DIEPINT14_NYETINTRPT_OFFSET       0xac8
-#define GC_USB_DIEPTSIZ14_XFERSIZE_LSB           0x0
-#define GC_USB_DIEPTSIZ14_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DIEPTSIZ14_XFERSIZE_SIZE          0x13
-#define GC_USB_DIEPTSIZ14_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DIEPTSIZ14_XFERSIZE_OFFSET        0xad0
-#define GC_USB_DIEPTSIZ14_PKTCNT_LSB             0x13
-#define GC_USB_DIEPTSIZ14_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DIEPTSIZ14_PKTCNT_SIZE            0xa
-#define GC_USB_DIEPTSIZ14_PKTCNT_DEFAULT         0x0
-#define GC_USB_DIEPTSIZ14_PKTCNT_OFFSET          0xad0
-#define GC_USB_DIEPTSIZ14_MC_LSB                 0x1d
-#define GC_USB_DIEPTSIZ14_MC_MASK                0x60000000
-#define GC_USB_DIEPTSIZ14_MC_SIZE                0x2
-#define GC_USB_DIEPTSIZ14_MC_DEFAULT             0x0
-#define GC_USB_DIEPTSIZ14_MC_OFFSET              0xad0
-#define GC_USB_DIEPDMA14_DMAADDR_LSB             0x0
-#define GC_USB_DIEPDMA14_DMAADDR_MASK            0xffffffff
-#define GC_USB_DIEPDMA14_DMAADDR_SIZE            0x20
-#define GC_USB_DIEPDMA14_DMAADDR_DEFAULT         0x0
-#define GC_USB_DIEPDMA14_DMAADDR_OFFSET          0xad4
-#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_LSB     0x0
-#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_MASK    0xffff
-#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_SIZE    0x10
+#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_OFFSET 0xab8
+#define GC_USB_DIEPDMAB13_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DIEPDMAB13_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMAB13_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DIEPDMAB13_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMAB13_DMABUFFERADDR_OFFSET 0xabc
+#define GC_USB_DIEPCTL14_MPS_LSB 0x0
+#define GC_USB_DIEPCTL14_MPS_MASK 0x7ff
+#define GC_USB_DIEPCTL14_MPS_SIZE 0xb
+#define GC_USB_DIEPCTL14_MPS_DEFAULT 0x0
+#define GC_USB_DIEPCTL14_MPS_OFFSET 0xac0
+#define GC_USB_DIEPCTL14_USBACTEP_LSB 0xf
+#define GC_USB_DIEPCTL14_USBACTEP_MASK 0x8000
+#define GC_USB_DIEPCTL14_USBACTEP_SIZE 0x1
+#define GC_USB_DIEPCTL14_USBACTEP_DEFAULT 0x0
+#define GC_USB_DIEPCTL14_USBACTEP_OFFSET 0xac0
+#define GC_USB_DIEPCTL14_DPID_LSB 0x10
+#define GC_USB_DIEPCTL14_DPID_MASK 0x10000
+#define GC_USB_DIEPCTL14_DPID_SIZE 0x1
+#define GC_USB_DIEPCTL14_DPID_DEFAULT 0x0
+#define GC_USB_DIEPCTL14_DPID_OFFSET 0xac0
+#define GC_USB_DIEPCTL14_NAKSTS_LSB 0x11
+#define GC_USB_DIEPCTL14_NAKSTS_MASK 0x20000
+#define GC_USB_DIEPCTL14_NAKSTS_SIZE 0x1
+#define GC_USB_DIEPCTL14_NAKSTS_DEFAULT 0x0
+#define GC_USB_DIEPCTL14_NAKSTS_OFFSET 0xac0
+#define GC_USB_DIEPCTL14_EPTYPE_LSB 0x12
+#define GC_USB_DIEPCTL14_EPTYPE_MASK 0xc0000
+#define GC_USB_DIEPCTL14_EPTYPE_SIZE 0x2
+#define GC_USB_DIEPCTL14_EPTYPE_DEFAULT 0x0
+#define GC_USB_DIEPCTL14_EPTYPE_OFFSET 0xac0
+#define GC_USB_DIEPCTL14_STALL_LSB 0x15
+#define GC_USB_DIEPCTL14_STALL_MASK 0x200000
+#define GC_USB_DIEPCTL14_STALL_SIZE 0x1
+#define GC_USB_DIEPCTL14_STALL_DEFAULT 0x0
+#define GC_USB_DIEPCTL14_STALL_OFFSET 0xac0
+#define GC_USB_DIEPCTL14_TXFNUM_LSB 0x16
+#define GC_USB_DIEPCTL14_TXFNUM_MASK 0x3c00000
+#define GC_USB_DIEPCTL14_TXFNUM_SIZE 0x4
+#define GC_USB_DIEPCTL14_TXFNUM_DEFAULT 0x0
+#define GC_USB_DIEPCTL14_TXFNUM_OFFSET 0xac0
+#define GC_USB_DIEPCTL14_CNAK_LSB 0x1a
+#define GC_USB_DIEPCTL14_CNAK_MASK 0x4000000
+#define GC_USB_DIEPCTL14_CNAK_SIZE 0x1
+#define GC_USB_DIEPCTL14_CNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL14_CNAK_OFFSET 0xac0
+#define GC_USB_DIEPCTL14_SNAK_LSB 0x1b
+#define GC_USB_DIEPCTL14_SNAK_MASK 0x8000000
+#define GC_USB_DIEPCTL14_SNAK_SIZE 0x1
+#define GC_USB_DIEPCTL14_SNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL14_SNAK_OFFSET 0xac0
+#define GC_USB_DIEPCTL14_SETD0PID_LSB 0x1c
+#define GC_USB_DIEPCTL14_SETD0PID_MASK 0x10000000
+#define GC_USB_DIEPCTL14_SETD0PID_SIZE 0x1
+#define GC_USB_DIEPCTL14_SETD0PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL14_SETD0PID_OFFSET 0xac0
+#define GC_USB_DIEPCTL14_SETD1PID_LSB 0x1d
+#define GC_USB_DIEPCTL14_SETD1PID_MASK 0x20000000
+#define GC_USB_DIEPCTL14_SETD1PID_SIZE 0x1
+#define GC_USB_DIEPCTL14_SETD1PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL14_SETD1PID_OFFSET 0xac0
+#define GC_USB_DIEPCTL14_EPDIS_LSB 0x1e
+#define GC_USB_DIEPCTL14_EPDIS_MASK 0x40000000
+#define GC_USB_DIEPCTL14_EPDIS_SIZE 0x1
+#define GC_USB_DIEPCTL14_EPDIS_DEFAULT 0x0
+#define GC_USB_DIEPCTL14_EPDIS_OFFSET 0xac0
+#define GC_USB_DIEPCTL14_EPENA_LSB 0x1f
+#define GC_USB_DIEPCTL14_EPENA_MASK 0x80000000
+#define GC_USB_DIEPCTL14_EPENA_SIZE 0x1
+#define GC_USB_DIEPCTL14_EPENA_DEFAULT 0x0
+#define GC_USB_DIEPCTL14_EPENA_OFFSET 0xac0
+#define GC_USB_DIEPINT14_XFERCOMPL_LSB 0x0
+#define GC_USB_DIEPINT14_XFERCOMPL_MASK 0x1
+#define GC_USB_DIEPINT14_XFERCOMPL_SIZE 0x1
+#define GC_USB_DIEPINT14_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DIEPINT14_XFERCOMPL_OFFSET 0xac8
+#define GC_USB_DIEPINT14_EPDISBLD_LSB 0x1
+#define GC_USB_DIEPINT14_EPDISBLD_MASK 0x2
+#define GC_USB_DIEPINT14_EPDISBLD_SIZE 0x1
+#define GC_USB_DIEPINT14_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DIEPINT14_EPDISBLD_OFFSET 0xac8
+#define GC_USB_DIEPINT14_AHBERR_LSB 0x2
+#define GC_USB_DIEPINT14_AHBERR_MASK 0x4
+#define GC_USB_DIEPINT14_AHBERR_SIZE 0x1
+#define GC_USB_DIEPINT14_AHBERR_DEFAULT 0x0
+#define GC_USB_DIEPINT14_AHBERR_OFFSET 0xac8
+#define GC_USB_DIEPINT14_TIMEOUT_LSB 0x3
+#define GC_USB_DIEPINT14_TIMEOUT_MASK 0x8
+#define GC_USB_DIEPINT14_TIMEOUT_SIZE 0x1
+#define GC_USB_DIEPINT14_TIMEOUT_DEFAULT 0x0
+#define GC_USB_DIEPINT14_TIMEOUT_OFFSET 0xac8
+#define GC_USB_DIEPINT14_INTKNTXFEMP_LSB 0x4
+#define GC_USB_DIEPINT14_INTKNTXFEMP_MASK 0x10
+#define GC_USB_DIEPINT14_INTKNTXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT14_INTKNTXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT14_INTKNTXFEMP_OFFSET 0xac8
+#define GC_USB_DIEPINT14_INTKNEPMIS_LSB 0x5
+#define GC_USB_DIEPINT14_INTKNEPMIS_MASK 0x20
+#define GC_USB_DIEPINT14_INTKNEPMIS_SIZE 0x1
+#define GC_USB_DIEPINT14_INTKNEPMIS_DEFAULT 0x0
+#define GC_USB_DIEPINT14_INTKNEPMIS_OFFSET 0xac8
+#define GC_USB_DIEPINT14_INEPNAKEFF_LSB 0x6
+#define GC_USB_DIEPINT14_INEPNAKEFF_MASK 0x40
+#define GC_USB_DIEPINT14_INEPNAKEFF_SIZE 0x1
+#define GC_USB_DIEPINT14_INEPNAKEFF_DEFAULT 0x0
+#define GC_USB_DIEPINT14_INEPNAKEFF_OFFSET 0xac8
+#define GC_USB_DIEPINT14_TXFEMP_LSB 0x7
+#define GC_USB_DIEPINT14_TXFEMP_MASK 0x80
+#define GC_USB_DIEPINT14_TXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT14_TXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT14_TXFEMP_OFFSET 0xac8
+#define GC_USB_DIEPINT14_TXFIFOUNDRN_LSB 0x8
+#define GC_USB_DIEPINT14_TXFIFOUNDRN_MASK 0x100
+#define GC_USB_DIEPINT14_TXFIFOUNDRN_SIZE 0x1
+#define GC_USB_DIEPINT14_TXFIFOUNDRN_DEFAULT 0x0
+#define GC_USB_DIEPINT14_TXFIFOUNDRN_OFFSET 0xac8
+#define GC_USB_DIEPINT14_BNAINTR_LSB 0x9
+#define GC_USB_DIEPINT14_BNAINTR_MASK 0x200
+#define GC_USB_DIEPINT14_BNAINTR_SIZE 0x1
+#define GC_USB_DIEPINT14_BNAINTR_DEFAULT 0x0
+#define GC_USB_DIEPINT14_BNAINTR_OFFSET 0xac8
+#define GC_USB_DIEPINT14_PKTDRPSTS_LSB 0xb
+#define GC_USB_DIEPINT14_PKTDRPSTS_MASK 0x800
+#define GC_USB_DIEPINT14_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DIEPINT14_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DIEPINT14_PKTDRPSTS_OFFSET 0xac8
+#define GC_USB_DIEPINT14_BBLEERR_LSB 0xc
+#define GC_USB_DIEPINT14_BBLEERR_MASK 0x1000
+#define GC_USB_DIEPINT14_BBLEERR_SIZE 0x1
+#define GC_USB_DIEPINT14_BBLEERR_DEFAULT 0x0
+#define GC_USB_DIEPINT14_BBLEERR_OFFSET 0xac8
+#define GC_USB_DIEPINT14_NAKINTRPT_LSB 0xd
+#define GC_USB_DIEPINT14_NAKINTRPT_MASK 0x2000
+#define GC_USB_DIEPINT14_NAKINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT14_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT14_NAKINTRPT_OFFSET 0xac8
+#define GC_USB_DIEPINT14_NYETINTRPT_LSB 0xe
+#define GC_USB_DIEPINT14_NYETINTRPT_MASK 0x4000
+#define GC_USB_DIEPINT14_NYETINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT14_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT14_NYETINTRPT_OFFSET 0xac8
+#define GC_USB_DIEPTSIZ14_XFERSIZE_LSB 0x0
+#define GC_USB_DIEPTSIZ14_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DIEPTSIZ14_XFERSIZE_SIZE 0x13
+#define GC_USB_DIEPTSIZ14_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ14_XFERSIZE_OFFSET 0xad0
+#define GC_USB_DIEPTSIZ14_PKTCNT_LSB 0x13
+#define GC_USB_DIEPTSIZ14_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DIEPTSIZ14_PKTCNT_SIZE 0xa
+#define GC_USB_DIEPTSIZ14_PKTCNT_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ14_PKTCNT_OFFSET 0xad0
+#define GC_USB_DIEPTSIZ14_MC_LSB 0x1d
+#define GC_USB_DIEPTSIZ14_MC_MASK 0x60000000
+#define GC_USB_DIEPTSIZ14_MC_SIZE 0x2
+#define GC_USB_DIEPTSIZ14_MC_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ14_MC_OFFSET 0xad0
+#define GC_USB_DIEPDMA14_DMAADDR_LSB 0x0
+#define GC_USB_DIEPDMA14_DMAADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMA14_DMAADDR_SIZE 0x20
+#define GC_USB_DIEPDMA14_DMAADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMA14_DMAADDR_OFFSET 0xad4
+#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_LSB 0x0
+#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_MASK 0xffff
+#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_SIZE 0x10
 #define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_DEFAULT 0x0
-#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_OFFSET  0xad8
-#define GC_USB_DIEPDMAB14_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DIEPDMAB14_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DIEPDMAB14_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DIEPDMAB14_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DIEPDMAB14_DMABUFFERADDR_OFFSET   0xadc
-#define GC_USB_DIEPCTL15_MPS_LSB                 0x0
-#define GC_USB_DIEPCTL15_MPS_MASK                0x7ff
-#define GC_USB_DIEPCTL15_MPS_SIZE                0xb
-#define GC_USB_DIEPCTL15_MPS_DEFAULT             0x0
-#define GC_USB_DIEPCTL15_MPS_OFFSET              0xae0
-#define GC_USB_DIEPCTL15_USBACTEP_LSB            0xf
-#define GC_USB_DIEPCTL15_USBACTEP_MASK           0x8000
-#define GC_USB_DIEPCTL15_USBACTEP_SIZE           0x1
-#define GC_USB_DIEPCTL15_USBACTEP_DEFAULT        0x0
-#define GC_USB_DIEPCTL15_USBACTEP_OFFSET         0xae0
-#define GC_USB_DIEPCTL15_DPID_LSB                0x10
-#define GC_USB_DIEPCTL15_DPID_MASK               0x10000
-#define GC_USB_DIEPCTL15_DPID_SIZE               0x1
-#define GC_USB_DIEPCTL15_DPID_DEFAULT            0x0
-#define GC_USB_DIEPCTL15_DPID_OFFSET             0xae0
-#define GC_USB_DIEPCTL15_NAKSTS_LSB              0x11
-#define GC_USB_DIEPCTL15_NAKSTS_MASK             0x20000
-#define GC_USB_DIEPCTL15_NAKSTS_SIZE             0x1
-#define GC_USB_DIEPCTL15_NAKSTS_DEFAULT          0x0
-#define GC_USB_DIEPCTL15_NAKSTS_OFFSET           0xae0
-#define GC_USB_DIEPCTL15_EPTYPE_LSB              0x12
-#define GC_USB_DIEPCTL15_EPTYPE_MASK             0xc0000
-#define GC_USB_DIEPCTL15_EPTYPE_SIZE             0x2
-#define GC_USB_DIEPCTL15_EPTYPE_DEFAULT          0x0
-#define GC_USB_DIEPCTL15_EPTYPE_OFFSET           0xae0
-#define GC_USB_DIEPCTL15_STALL_LSB               0x15
-#define GC_USB_DIEPCTL15_STALL_MASK              0x200000
-#define GC_USB_DIEPCTL15_STALL_SIZE              0x1
-#define GC_USB_DIEPCTL15_STALL_DEFAULT           0x0
-#define GC_USB_DIEPCTL15_STALL_OFFSET            0xae0
-#define GC_USB_DIEPCTL15_TXFNUM_LSB              0x16
-#define GC_USB_DIEPCTL15_TXFNUM_MASK             0x3c00000
-#define GC_USB_DIEPCTL15_TXFNUM_SIZE             0x4
-#define GC_USB_DIEPCTL15_TXFNUM_DEFAULT          0x0
-#define GC_USB_DIEPCTL15_TXFNUM_OFFSET           0xae0
-#define GC_USB_DIEPCTL15_CNAK_LSB                0x1a
-#define GC_USB_DIEPCTL15_CNAK_MASK               0x4000000
-#define GC_USB_DIEPCTL15_CNAK_SIZE               0x1
-#define GC_USB_DIEPCTL15_CNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL15_CNAK_OFFSET             0xae0
-#define GC_USB_DIEPCTL15_SNAK_LSB                0x1b
-#define GC_USB_DIEPCTL15_SNAK_MASK               0x8000000
-#define GC_USB_DIEPCTL15_SNAK_SIZE               0x1
-#define GC_USB_DIEPCTL15_SNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL15_SNAK_OFFSET             0xae0
-#define GC_USB_DIEPCTL15_SETD0PID_LSB            0x1c
-#define GC_USB_DIEPCTL15_SETD0PID_MASK           0x10000000
-#define GC_USB_DIEPCTL15_SETD0PID_SIZE           0x1
-#define GC_USB_DIEPCTL15_SETD0PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL15_SETD0PID_OFFSET         0xae0
-#define GC_USB_DIEPCTL15_SETD1PID_LSB            0x1d
-#define GC_USB_DIEPCTL15_SETD1PID_MASK           0x20000000
-#define GC_USB_DIEPCTL15_SETD1PID_SIZE           0x1
-#define GC_USB_DIEPCTL15_SETD1PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL15_SETD1PID_OFFSET         0xae0
-#define GC_USB_DIEPCTL15_EPDIS_LSB               0x1e
-#define GC_USB_DIEPCTL15_EPDIS_MASK              0x40000000
-#define GC_USB_DIEPCTL15_EPDIS_SIZE              0x1
-#define GC_USB_DIEPCTL15_EPDIS_DEFAULT           0x0
-#define GC_USB_DIEPCTL15_EPDIS_OFFSET            0xae0
-#define GC_USB_DIEPCTL15_EPENA_LSB               0x1f
-#define GC_USB_DIEPCTL15_EPENA_MASK              0x80000000
-#define GC_USB_DIEPCTL15_EPENA_SIZE              0x1
-#define GC_USB_DIEPCTL15_EPENA_DEFAULT           0x0
-#define GC_USB_DIEPCTL15_EPENA_OFFSET            0xae0
-#define GC_USB_DIEPINT15_XFERCOMPL_LSB           0x0
-#define GC_USB_DIEPINT15_XFERCOMPL_MASK          0x1
-#define GC_USB_DIEPINT15_XFERCOMPL_SIZE          0x1
-#define GC_USB_DIEPINT15_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DIEPINT15_XFERCOMPL_OFFSET        0xae8
-#define GC_USB_DIEPINT15_EPDISBLD_LSB            0x1
-#define GC_USB_DIEPINT15_EPDISBLD_MASK           0x2
-#define GC_USB_DIEPINT15_EPDISBLD_SIZE           0x1
-#define GC_USB_DIEPINT15_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DIEPINT15_EPDISBLD_OFFSET         0xae8
-#define GC_USB_DIEPINT15_AHBERR_LSB              0x2
-#define GC_USB_DIEPINT15_AHBERR_MASK             0x4
-#define GC_USB_DIEPINT15_AHBERR_SIZE             0x1
-#define GC_USB_DIEPINT15_AHBERR_DEFAULT          0x0
-#define GC_USB_DIEPINT15_AHBERR_OFFSET           0xae8
-#define GC_USB_DIEPINT15_TIMEOUT_LSB             0x3
-#define GC_USB_DIEPINT15_TIMEOUT_MASK            0x8
-#define GC_USB_DIEPINT15_TIMEOUT_SIZE            0x1
-#define GC_USB_DIEPINT15_TIMEOUT_DEFAULT         0x0
-#define GC_USB_DIEPINT15_TIMEOUT_OFFSET          0xae8
-#define GC_USB_DIEPINT15_INTKNTXFEMP_LSB         0x4
-#define GC_USB_DIEPINT15_INTKNTXFEMP_MASK        0x10
-#define GC_USB_DIEPINT15_INTKNTXFEMP_SIZE        0x1
-#define GC_USB_DIEPINT15_INTKNTXFEMP_DEFAULT     0x0
-#define GC_USB_DIEPINT15_INTKNTXFEMP_OFFSET      0xae8
-#define GC_USB_DIEPINT15_INTKNEPMIS_LSB          0x5
-#define GC_USB_DIEPINT15_INTKNEPMIS_MASK         0x20
-#define GC_USB_DIEPINT15_INTKNEPMIS_SIZE         0x1
-#define GC_USB_DIEPINT15_INTKNEPMIS_DEFAULT      0x0
-#define GC_USB_DIEPINT15_INTKNEPMIS_OFFSET       0xae8
-#define GC_USB_DIEPINT15_INEPNAKEFF_LSB          0x6
-#define GC_USB_DIEPINT15_INEPNAKEFF_MASK         0x40
-#define GC_USB_DIEPINT15_INEPNAKEFF_SIZE         0x1
-#define GC_USB_DIEPINT15_INEPNAKEFF_DEFAULT      0x0
-#define GC_USB_DIEPINT15_INEPNAKEFF_OFFSET       0xae8
-#define GC_USB_DIEPINT15_TXFEMP_LSB              0x7
-#define GC_USB_DIEPINT15_TXFEMP_MASK             0x80
-#define GC_USB_DIEPINT15_TXFEMP_SIZE             0x1
-#define GC_USB_DIEPINT15_TXFEMP_DEFAULT          0x0
-#define GC_USB_DIEPINT15_TXFEMP_OFFSET           0xae8
-#define GC_USB_DIEPINT15_TXFIFOUNDRN_LSB         0x8
-#define GC_USB_DIEPINT15_TXFIFOUNDRN_MASK        0x100
-#define GC_USB_DIEPINT15_TXFIFOUNDRN_SIZE        0x1
-#define GC_USB_DIEPINT15_TXFIFOUNDRN_DEFAULT     0x0
-#define GC_USB_DIEPINT15_TXFIFOUNDRN_OFFSET      0xae8
-#define GC_USB_DIEPINT15_BNAINTR_LSB             0x9
-#define GC_USB_DIEPINT15_BNAINTR_MASK            0x200
-#define GC_USB_DIEPINT15_BNAINTR_SIZE            0x1
-#define GC_USB_DIEPINT15_BNAINTR_DEFAULT         0x0
-#define GC_USB_DIEPINT15_BNAINTR_OFFSET          0xae8
-#define GC_USB_DIEPINT15_PKTDRPSTS_LSB           0xb
-#define GC_USB_DIEPINT15_PKTDRPSTS_MASK          0x800
-#define GC_USB_DIEPINT15_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DIEPINT15_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DIEPINT15_PKTDRPSTS_OFFSET        0xae8
-#define GC_USB_DIEPINT15_BBLEERR_LSB             0xc
-#define GC_USB_DIEPINT15_BBLEERR_MASK            0x1000
-#define GC_USB_DIEPINT15_BBLEERR_SIZE            0x1
-#define GC_USB_DIEPINT15_BBLEERR_DEFAULT         0x0
-#define GC_USB_DIEPINT15_BBLEERR_OFFSET          0xae8
-#define GC_USB_DIEPINT15_NAKINTRPT_LSB           0xd
-#define GC_USB_DIEPINT15_NAKINTRPT_MASK          0x2000
-#define GC_USB_DIEPINT15_NAKINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT15_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT15_NAKINTRPT_OFFSET        0xae8
-#define GC_USB_DIEPINT15_NYETINTRPT_LSB          0xe
-#define GC_USB_DIEPINT15_NYETINTRPT_MASK         0x4000
-#define GC_USB_DIEPINT15_NYETINTRPT_SIZE         0x1
-#define GC_USB_DIEPINT15_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DIEPINT15_NYETINTRPT_OFFSET       0xae8
-#define GC_USB_DIEPTSIZ15_XFERSIZE_LSB           0x0
-#define GC_USB_DIEPTSIZ15_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DIEPTSIZ15_XFERSIZE_SIZE          0x13
-#define GC_USB_DIEPTSIZ15_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DIEPTSIZ15_XFERSIZE_OFFSET        0xaf0
-#define GC_USB_DIEPTSIZ15_PKTCNT_LSB             0x13
-#define GC_USB_DIEPTSIZ15_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DIEPTSIZ15_PKTCNT_SIZE            0xa
-#define GC_USB_DIEPTSIZ15_PKTCNT_DEFAULT         0x0
-#define GC_USB_DIEPTSIZ15_PKTCNT_OFFSET          0xaf0
-#define GC_USB_DIEPTSIZ15_MC_LSB                 0x1d
-#define GC_USB_DIEPTSIZ15_MC_MASK                0x60000000
-#define GC_USB_DIEPTSIZ15_MC_SIZE                0x2
-#define GC_USB_DIEPTSIZ15_MC_DEFAULT             0x0
-#define GC_USB_DIEPTSIZ15_MC_OFFSET              0xaf0
-#define GC_USB_DIEPDMA15_DMAADDR_LSB             0x0
-#define GC_USB_DIEPDMA15_DMAADDR_MASK            0xffffffff
-#define GC_USB_DIEPDMA15_DMAADDR_SIZE            0x20
-#define GC_USB_DIEPDMA15_DMAADDR_DEFAULT         0x0
-#define GC_USB_DIEPDMA15_DMAADDR_OFFSET          0xaf4
-#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_LSB     0x0
-#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_MASK    0xffff
-#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_SIZE    0x10
+#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_OFFSET 0xad8
+#define GC_USB_DIEPDMAB14_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DIEPDMAB14_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMAB14_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DIEPDMAB14_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMAB14_DMABUFFERADDR_OFFSET 0xadc
+#define GC_USB_DIEPCTL15_MPS_LSB 0x0
+#define GC_USB_DIEPCTL15_MPS_MASK 0x7ff
+#define GC_USB_DIEPCTL15_MPS_SIZE 0xb
+#define GC_USB_DIEPCTL15_MPS_DEFAULT 0x0
+#define GC_USB_DIEPCTL15_MPS_OFFSET 0xae0
+#define GC_USB_DIEPCTL15_USBACTEP_LSB 0xf
+#define GC_USB_DIEPCTL15_USBACTEP_MASK 0x8000
+#define GC_USB_DIEPCTL15_USBACTEP_SIZE 0x1
+#define GC_USB_DIEPCTL15_USBACTEP_DEFAULT 0x0
+#define GC_USB_DIEPCTL15_USBACTEP_OFFSET 0xae0
+#define GC_USB_DIEPCTL15_DPID_LSB 0x10
+#define GC_USB_DIEPCTL15_DPID_MASK 0x10000
+#define GC_USB_DIEPCTL15_DPID_SIZE 0x1
+#define GC_USB_DIEPCTL15_DPID_DEFAULT 0x0
+#define GC_USB_DIEPCTL15_DPID_OFFSET 0xae0
+#define GC_USB_DIEPCTL15_NAKSTS_LSB 0x11
+#define GC_USB_DIEPCTL15_NAKSTS_MASK 0x20000
+#define GC_USB_DIEPCTL15_NAKSTS_SIZE 0x1
+#define GC_USB_DIEPCTL15_NAKSTS_DEFAULT 0x0
+#define GC_USB_DIEPCTL15_NAKSTS_OFFSET 0xae0
+#define GC_USB_DIEPCTL15_EPTYPE_LSB 0x12
+#define GC_USB_DIEPCTL15_EPTYPE_MASK 0xc0000
+#define GC_USB_DIEPCTL15_EPTYPE_SIZE 0x2
+#define GC_USB_DIEPCTL15_EPTYPE_DEFAULT 0x0
+#define GC_USB_DIEPCTL15_EPTYPE_OFFSET 0xae0
+#define GC_USB_DIEPCTL15_STALL_LSB 0x15
+#define GC_USB_DIEPCTL15_STALL_MASK 0x200000
+#define GC_USB_DIEPCTL15_STALL_SIZE 0x1
+#define GC_USB_DIEPCTL15_STALL_DEFAULT 0x0
+#define GC_USB_DIEPCTL15_STALL_OFFSET 0xae0
+#define GC_USB_DIEPCTL15_TXFNUM_LSB 0x16
+#define GC_USB_DIEPCTL15_TXFNUM_MASK 0x3c00000
+#define GC_USB_DIEPCTL15_TXFNUM_SIZE 0x4
+#define GC_USB_DIEPCTL15_TXFNUM_DEFAULT 0x0
+#define GC_USB_DIEPCTL15_TXFNUM_OFFSET 0xae0
+#define GC_USB_DIEPCTL15_CNAK_LSB 0x1a
+#define GC_USB_DIEPCTL15_CNAK_MASK 0x4000000
+#define GC_USB_DIEPCTL15_CNAK_SIZE 0x1
+#define GC_USB_DIEPCTL15_CNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL15_CNAK_OFFSET 0xae0
+#define GC_USB_DIEPCTL15_SNAK_LSB 0x1b
+#define GC_USB_DIEPCTL15_SNAK_MASK 0x8000000
+#define GC_USB_DIEPCTL15_SNAK_SIZE 0x1
+#define GC_USB_DIEPCTL15_SNAK_DEFAULT 0x0
+#define GC_USB_DIEPCTL15_SNAK_OFFSET 0xae0
+#define GC_USB_DIEPCTL15_SETD0PID_LSB 0x1c
+#define GC_USB_DIEPCTL15_SETD0PID_MASK 0x10000000
+#define GC_USB_DIEPCTL15_SETD0PID_SIZE 0x1
+#define GC_USB_DIEPCTL15_SETD0PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL15_SETD0PID_OFFSET 0xae0
+#define GC_USB_DIEPCTL15_SETD1PID_LSB 0x1d
+#define GC_USB_DIEPCTL15_SETD1PID_MASK 0x20000000
+#define GC_USB_DIEPCTL15_SETD1PID_SIZE 0x1
+#define GC_USB_DIEPCTL15_SETD1PID_DEFAULT 0x0
+#define GC_USB_DIEPCTL15_SETD1PID_OFFSET 0xae0
+#define GC_USB_DIEPCTL15_EPDIS_LSB 0x1e
+#define GC_USB_DIEPCTL15_EPDIS_MASK 0x40000000
+#define GC_USB_DIEPCTL15_EPDIS_SIZE 0x1
+#define GC_USB_DIEPCTL15_EPDIS_DEFAULT 0x0
+#define GC_USB_DIEPCTL15_EPDIS_OFFSET 0xae0
+#define GC_USB_DIEPCTL15_EPENA_LSB 0x1f
+#define GC_USB_DIEPCTL15_EPENA_MASK 0x80000000
+#define GC_USB_DIEPCTL15_EPENA_SIZE 0x1
+#define GC_USB_DIEPCTL15_EPENA_DEFAULT 0x0
+#define GC_USB_DIEPCTL15_EPENA_OFFSET 0xae0
+#define GC_USB_DIEPINT15_XFERCOMPL_LSB 0x0
+#define GC_USB_DIEPINT15_XFERCOMPL_MASK 0x1
+#define GC_USB_DIEPINT15_XFERCOMPL_SIZE 0x1
+#define GC_USB_DIEPINT15_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DIEPINT15_XFERCOMPL_OFFSET 0xae8
+#define GC_USB_DIEPINT15_EPDISBLD_LSB 0x1
+#define GC_USB_DIEPINT15_EPDISBLD_MASK 0x2
+#define GC_USB_DIEPINT15_EPDISBLD_SIZE 0x1
+#define GC_USB_DIEPINT15_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DIEPINT15_EPDISBLD_OFFSET 0xae8
+#define GC_USB_DIEPINT15_AHBERR_LSB 0x2
+#define GC_USB_DIEPINT15_AHBERR_MASK 0x4
+#define GC_USB_DIEPINT15_AHBERR_SIZE 0x1
+#define GC_USB_DIEPINT15_AHBERR_DEFAULT 0x0
+#define GC_USB_DIEPINT15_AHBERR_OFFSET 0xae8
+#define GC_USB_DIEPINT15_TIMEOUT_LSB 0x3
+#define GC_USB_DIEPINT15_TIMEOUT_MASK 0x8
+#define GC_USB_DIEPINT15_TIMEOUT_SIZE 0x1
+#define GC_USB_DIEPINT15_TIMEOUT_DEFAULT 0x0
+#define GC_USB_DIEPINT15_TIMEOUT_OFFSET 0xae8
+#define GC_USB_DIEPINT15_INTKNTXFEMP_LSB 0x4
+#define GC_USB_DIEPINT15_INTKNTXFEMP_MASK 0x10
+#define GC_USB_DIEPINT15_INTKNTXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT15_INTKNTXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT15_INTKNTXFEMP_OFFSET 0xae8
+#define GC_USB_DIEPINT15_INTKNEPMIS_LSB 0x5
+#define GC_USB_DIEPINT15_INTKNEPMIS_MASK 0x20
+#define GC_USB_DIEPINT15_INTKNEPMIS_SIZE 0x1
+#define GC_USB_DIEPINT15_INTKNEPMIS_DEFAULT 0x0
+#define GC_USB_DIEPINT15_INTKNEPMIS_OFFSET 0xae8
+#define GC_USB_DIEPINT15_INEPNAKEFF_LSB 0x6
+#define GC_USB_DIEPINT15_INEPNAKEFF_MASK 0x40
+#define GC_USB_DIEPINT15_INEPNAKEFF_SIZE 0x1
+#define GC_USB_DIEPINT15_INEPNAKEFF_DEFAULT 0x0
+#define GC_USB_DIEPINT15_INEPNAKEFF_OFFSET 0xae8
+#define GC_USB_DIEPINT15_TXFEMP_LSB 0x7
+#define GC_USB_DIEPINT15_TXFEMP_MASK 0x80
+#define GC_USB_DIEPINT15_TXFEMP_SIZE 0x1
+#define GC_USB_DIEPINT15_TXFEMP_DEFAULT 0x0
+#define GC_USB_DIEPINT15_TXFEMP_OFFSET 0xae8
+#define GC_USB_DIEPINT15_TXFIFOUNDRN_LSB 0x8
+#define GC_USB_DIEPINT15_TXFIFOUNDRN_MASK 0x100
+#define GC_USB_DIEPINT15_TXFIFOUNDRN_SIZE 0x1
+#define GC_USB_DIEPINT15_TXFIFOUNDRN_DEFAULT 0x0
+#define GC_USB_DIEPINT15_TXFIFOUNDRN_OFFSET 0xae8
+#define GC_USB_DIEPINT15_BNAINTR_LSB 0x9
+#define GC_USB_DIEPINT15_BNAINTR_MASK 0x200
+#define GC_USB_DIEPINT15_BNAINTR_SIZE 0x1
+#define GC_USB_DIEPINT15_BNAINTR_DEFAULT 0x0
+#define GC_USB_DIEPINT15_BNAINTR_OFFSET 0xae8
+#define GC_USB_DIEPINT15_PKTDRPSTS_LSB 0xb
+#define GC_USB_DIEPINT15_PKTDRPSTS_MASK 0x800
+#define GC_USB_DIEPINT15_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DIEPINT15_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DIEPINT15_PKTDRPSTS_OFFSET 0xae8
+#define GC_USB_DIEPINT15_BBLEERR_LSB 0xc
+#define GC_USB_DIEPINT15_BBLEERR_MASK 0x1000
+#define GC_USB_DIEPINT15_BBLEERR_SIZE 0x1
+#define GC_USB_DIEPINT15_BBLEERR_DEFAULT 0x0
+#define GC_USB_DIEPINT15_BBLEERR_OFFSET 0xae8
+#define GC_USB_DIEPINT15_NAKINTRPT_LSB 0xd
+#define GC_USB_DIEPINT15_NAKINTRPT_MASK 0x2000
+#define GC_USB_DIEPINT15_NAKINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT15_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT15_NAKINTRPT_OFFSET 0xae8
+#define GC_USB_DIEPINT15_NYETINTRPT_LSB 0xe
+#define GC_USB_DIEPINT15_NYETINTRPT_MASK 0x4000
+#define GC_USB_DIEPINT15_NYETINTRPT_SIZE 0x1
+#define GC_USB_DIEPINT15_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DIEPINT15_NYETINTRPT_OFFSET 0xae8
+#define GC_USB_DIEPTSIZ15_XFERSIZE_LSB 0x0
+#define GC_USB_DIEPTSIZ15_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DIEPTSIZ15_XFERSIZE_SIZE 0x13
+#define GC_USB_DIEPTSIZ15_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ15_XFERSIZE_OFFSET 0xaf0
+#define GC_USB_DIEPTSIZ15_PKTCNT_LSB 0x13
+#define GC_USB_DIEPTSIZ15_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DIEPTSIZ15_PKTCNT_SIZE 0xa
+#define GC_USB_DIEPTSIZ15_PKTCNT_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ15_PKTCNT_OFFSET 0xaf0
+#define GC_USB_DIEPTSIZ15_MC_LSB 0x1d
+#define GC_USB_DIEPTSIZ15_MC_MASK 0x60000000
+#define GC_USB_DIEPTSIZ15_MC_SIZE 0x2
+#define GC_USB_DIEPTSIZ15_MC_DEFAULT 0x0
+#define GC_USB_DIEPTSIZ15_MC_OFFSET 0xaf0
+#define GC_USB_DIEPDMA15_DMAADDR_LSB 0x0
+#define GC_USB_DIEPDMA15_DMAADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMA15_DMAADDR_SIZE 0x20
+#define GC_USB_DIEPDMA15_DMAADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMA15_DMAADDR_OFFSET 0xaf4
+#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_LSB 0x0
+#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_MASK 0xffff
+#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_SIZE 0x10
 #define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_DEFAULT 0x0
-#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_OFFSET  0xaf8
-#define GC_USB_DIEPDMAB15_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DIEPDMAB15_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DIEPDMAB15_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DIEPDMAB15_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DIEPDMAB15_DMABUFFERADDR_OFFSET   0xafc
-#define GC_USB_DOEPCTL0_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL0_MPS_MASK                 0x3
-#define GC_USB_DOEPCTL0_MPS_SIZE                 0x2
-#define GC_USB_DOEPCTL0_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL0_MPS_OFFSET               0xb00
-#define GC_USB_DOEPCTL0_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL0_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL0_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL0_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL0_USBACTEP_OFFSET          0xb00
-#define GC_USB_DOEPCTL0_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL0_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL0_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL0_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL0_NAKSTS_OFFSET            0xb00
-#define GC_USB_DOEPCTL0_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL0_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL0_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL0_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL0_EPTYPE_OFFSET            0xb00
-#define GC_USB_DOEPCTL0_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL0_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL0_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL0_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL0_SNP_OFFSET               0xb00
-#define GC_USB_DOEPCTL0_STALL_LSB                0x15
-#define GC_USB_DOEPCTL0_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL0_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL0_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL0_STALL_OFFSET             0xb00
-#define GC_USB_DOEPCTL0_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL0_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL0_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL0_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL0_CNAK_OFFSET              0xb00
-#define GC_USB_DOEPCTL0_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL0_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL0_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL0_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL0_SNAK_OFFSET              0xb00
-#define GC_USB_DOEPCTL0_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL0_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL0_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL0_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL0_EPDIS_OFFSET             0xb00
-#define GC_USB_DOEPCTL0_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL0_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL0_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL0_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL0_EPENA_OFFSET             0xb00
-#define GC_USB_DOEPINT0_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT0_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT0_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT0_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT0_XFERCOMPL_OFFSET         0xb08
-#define GC_USB_DOEPINT0_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT0_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT0_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT0_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT0_EPDISBLD_OFFSET          0xb08
-#define GC_USB_DOEPINT0_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT0_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT0_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT0_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT0_AHBERR_OFFSET            0xb08
-#define GC_USB_DOEPINT0_SETUP_LSB                0x3
-#define GC_USB_DOEPINT0_SETUP_MASK               0x8
-#define GC_USB_DOEPINT0_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT0_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT0_SETUP_OFFSET             0xb08
-#define GC_USB_DOEPINT0_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT0_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT0_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT0_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT0_OUTTKNEPDIS_OFFSET       0xb08
-#define GC_USB_DOEPINT0_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT0_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT0_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT0_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT0_STSPHSERCVD_OFFSET       0xb08
-#define GC_USB_DOEPINT0_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT0_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT0_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT0_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT0_BACK2BACKSETUP_OFFSET    0xb08
-#define GC_USB_DOEPINT0_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT0_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT0_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT0_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT0_OUTPKTERR_OFFSET         0xb08
-#define GC_USB_DOEPINT0_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT0_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT0_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT0_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT0_BNAINTR_OFFSET           0xb08
-#define GC_USB_DOEPINT0_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT0_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT0_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT0_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT0_PKTDRPSTS_OFFSET         0xb08
-#define GC_USB_DOEPINT0_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT0_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT0_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT0_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT0_BBLEERR_OFFSET           0xb08
-#define GC_USB_DOEPINT0_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT0_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT0_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT0_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT0_NAKINTRPT_OFFSET         0xb08
-#define GC_USB_DOEPINT0_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT0_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT0_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT0_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT0_NYETINTRPT_OFFSET        0xb08
-#define GC_USB_DOEPINT0_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT0_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT0_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT0_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT0_STUPPKTRCVD_OFFSET       0xb08
-#define GC_USB_DOEPTSIZ0_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ0_XFERSIZE_MASK           0x7f
-#define GC_USB_DOEPTSIZ0_XFERSIZE_SIZE           0x7
-#define GC_USB_DOEPTSIZ0_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ0_XFERSIZE_OFFSET         0xb10
-#define GC_USB_DOEPTSIZ0_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ0_PKTCNT_MASK             0x80000
-#define GC_USB_DOEPTSIZ0_PKTCNT_SIZE             0x1
-#define GC_USB_DOEPTSIZ0_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ0_PKTCNT_OFFSET           0xb10
-#define GC_USB_DOEPTSIZ0_SUPCNT_LSB              0x1d
-#define GC_USB_DOEPTSIZ0_SUPCNT_MASK             0x60000000
-#define GC_USB_DOEPTSIZ0_SUPCNT_SIZE             0x2
-#define GC_USB_DOEPTSIZ0_SUPCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ0_SUPCNT_OFFSET           0xb10
-#define GC_USB_DOEPDMA0_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA0_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA0_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA0_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA0_DMAADDR_OFFSET           0xb14
-#define GC_USB_DOEPDMAB0_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB0_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB0_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB0_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB0_DMABUFFERADDR_OFFSET    0xb1c
-#define GC_USB_DOEPCTL1_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL1_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL1_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL1_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL1_MPS_OFFSET               0xb20
-#define GC_USB_DOEPCTL1_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL1_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL1_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL1_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL1_USBACTEP_OFFSET          0xb20
-#define GC_USB_DOEPCTL1_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL1_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL1_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL1_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL1_DPID_OFFSET              0xb20
-#define GC_USB_DOEPCTL1_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL1_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL1_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL1_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL1_NAKSTS_OFFSET            0xb20
-#define GC_USB_DOEPCTL1_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL1_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL1_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL1_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL1_EPTYPE_OFFSET            0xb20
-#define GC_USB_DOEPCTL1_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL1_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL1_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL1_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL1_SNP_OFFSET               0xb20
-#define GC_USB_DOEPCTL1_STALL_LSB                0x15
-#define GC_USB_DOEPCTL1_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL1_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL1_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL1_STALL_OFFSET             0xb20
-#define GC_USB_DOEPCTL1_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL1_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL1_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL1_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL1_CNAK_OFFSET              0xb20
-#define GC_USB_DOEPCTL1_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL1_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL1_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL1_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL1_SNAK_OFFSET              0xb20
-#define GC_USB_DOEPCTL1_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL1_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL1_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL1_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL1_SETD0PID_OFFSET          0xb20
-#define GC_USB_DOEPCTL1_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL1_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL1_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL1_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL1_SETD1PID_OFFSET          0xb20
-#define GC_USB_DOEPCTL1_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL1_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL1_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL1_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL1_EPDIS_OFFSET             0xb20
-#define GC_USB_DOEPCTL1_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL1_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL1_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL1_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL1_EPENA_OFFSET             0xb20
-#define GC_USB_DOEPINT1_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT1_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT1_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT1_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT1_XFERCOMPL_OFFSET         0xb28
-#define GC_USB_DOEPINT1_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT1_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT1_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT1_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT1_EPDISBLD_OFFSET          0xb28
-#define GC_USB_DOEPINT1_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT1_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT1_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT1_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT1_AHBERR_OFFSET            0xb28
-#define GC_USB_DOEPINT1_SETUP_LSB                0x3
-#define GC_USB_DOEPINT1_SETUP_MASK               0x8
-#define GC_USB_DOEPINT1_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT1_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT1_SETUP_OFFSET             0xb28
-#define GC_USB_DOEPINT1_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT1_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT1_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT1_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT1_OUTTKNEPDIS_OFFSET       0xb28
-#define GC_USB_DOEPINT1_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT1_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT1_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT1_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT1_STSPHSERCVD_OFFSET       0xb28
-#define GC_USB_DOEPINT1_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT1_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT1_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT1_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT1_BACK2BACKSETUP_OFFSET    0xb28
-#define GC_USB_DOEPINT1_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT1_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT1_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT1_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT1_OUTPKTERR_OFFSET         0xb28
-#define GC_USB_DOEPINT1_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT1_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT1_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT1_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT1_BNAINTR_OFFSET           0xb28
-#define GC_USB_DOEPINT1_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT1_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT1_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT1_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT1_PKTDRPSTS_OFFSET         0xb28
-#define GC_USB_DOEPINT1_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT1_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT1_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT1_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT1_BBLEERR_OFFSET           0xb28
-#define GC_USB_DOEPINT1_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT1_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT1_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT1_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT1_NAKINTRPT_OFFSET         0xb28
-#define GC_USB_DOEPINT1_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT1_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT1_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT1_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT1_NYETINTRPT_OFFSET        0xb28
-#define GC_USB_DOEPINT1_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT1_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT1_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT1_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT1_STUPPKTRCVD_OFFSET       0xb28
-#define GC_USB_DOEPTSIZ1_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ1_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ1_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ1_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ1_XFERSIZE_OFFSET         0xb30
-#define GC_USB_DOEPTSIZ1_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ1_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ1_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ1_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ1_PKTCNT_OFFSET           0xb30
-#define GC_USB_DOEPTSIZ1_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ1_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ1_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ1_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ1_RXDPID_OFFSET           0xb30
-#define GC_USB_DOEPDMA1_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA1_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA1_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA1_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA1_DMAADDR_OFFSET           0xb34
-#define GC_USB_DOEPDMAB1_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB1_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB1_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB1_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB1_DMABUFFERADDR_OFFSET    0xb3c
-#define GC_USB_DOEPCTL2_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL2_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL2_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL2_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL2_MPS_OFFSET               0xb40
-#define GC_USB_DOEPCTL2_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL2_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL2_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL2_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL2_USBACTEP_OFFSET          0xb40
-#define GC_USB_DOEPCTL2_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL2_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL2_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL2_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL2_DPID_OFFSET              0xb40
-#define GC_USB_DOEPCTL2_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL2_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL2_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL2_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL2_NAKSTS_OFFSET            0xb40
-#define GC_USB_DOEPCTL2_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL2_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL2_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL2_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL2_EPTYPE_OFFSET            0xb40
-#define GC_USB_DOEPCTL2_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL2_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL2_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL2_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL2_SNP_OFFSET               0xb40
-#define GC_USB_DOEPCTL2_STALL_LSB                0x15
-#define GC_USB_DOEPCTL2_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL2_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL2_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL2_STALL_OFFSET             0xb40
-#define GC_USB_DOEPCTL2_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL2_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL2_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL2_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL2_CNAK_OFFSET              0xb40
-#define GC_USB_DOEPCTL2_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL2_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL2_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL2_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL2_SNAK_OFFSET              0xb40
-#define GC_USB_DOEPCTL2_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL2_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL2_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL2_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL2_SETD0PID_OFFSET          0xb40
-#define GC_USB_DOEPCTL2_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL2_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL2_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL2_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL2_SETD1PID_OFFSET          0xb40
-#define GC_USB_DOEPCTL2_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL2_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL2_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL2_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL2_EPDIS_OFFSET             0xb40
-#define GC_USB_DOEPCTL2_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL2_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL2_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL2_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL2_EPENA_OFFSET             0xb40
-#define GC_USB_DOEPINT2_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT2_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT2_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT2_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT2_XFERCOMPL_OFFSET         0xb48
-#define GC_USB_DOEPINT2_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT2_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT2_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT2_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT2_EPDISBLD_OFFSET          0xb48
-#define GC_USB_DOEPINT2_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT2_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT2_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT2_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT2_AHBERR_OFFSET            0xb48
-#define GC_USB_DOEPINT2_SETUP_LSB                0x3
-#define GC_USB_DOEPINT2_SETUP_MASK               0x8
-#define GC_USB_DOEPINT2_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT2_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT2_SETUP_OFFSET             0xb48
-#define GC_USB_DOEPINT2_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT2_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT2_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT2_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT2_OUTTKNEPDIS_OFFSET       0xb48
-#define GC_USB_DOEPINT2_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT2_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT2_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT2_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT2_STSPHSERCVD_OFFSET       0xb48
-#define GC_USB_DOEPINT2_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT2_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT2_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT2_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT2_BACK2BACKSETUP_OFFSET    0xb48
-#define GC_USB_DOEPINT2_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT2_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT2_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT2_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT2_OUTPKTERR_OFFSET         0xb48
-#define GC_USB_DOEPINT2_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT2_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT2_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT2_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT2_BNAINTR_OFFSET           0xb48
-#define GC_USB_DOEPINT2_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT2_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT2_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT2_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT2_PKTDRPSTS_OFFSET         0xb48
-#define GC_USB_DOEPINT2_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT2_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT2_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT2_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT2_BBLEERR_OFFSET           0xb48
-#define GC_USB_DOEPINT2_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT2_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT2_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT2_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT2_NAKINTRPT_OFFSET         0xb48
-#define GC_USB_DOEPINT2_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT2_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT2_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT2_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT2_NYETINTRPT_OFFSET        0xb48
-#define GC_USB_DOEPINT2_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT2_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT2_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT2_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT2_STUPPKTRCVD_OFFSET       0xb48
-#define GC_USB_DOEPTSIZ2_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ2_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ2_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ2_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ2_XFERSIZE_OFFSET         0xb50
-#define GC_USB_DOEPTSIZ2_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ2_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ2_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ2_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ2_PKTCNT_OFFSET           0xb50
-#define GC_USB_DOEPTSIZ2_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ2_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ2_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ2_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ2_RXDPID_OFFSET           0xb50
-#define GC_USB_DOEPDMA2_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA2_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA2_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA2_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA2_DMAADDR_OFFSET           0xb54
-#define GC_USB_DOEPDMAB2_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB2_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB2_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB2_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB2_DMABUFFERADDR_OFFSET    0xb5c
-#define GC_USB_DOEPCTL3_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL3_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL3_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL3_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL3_MPS_OFFSET               0xb60
-#define GC_USB_DOEPCTL3_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL3_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL3_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL3_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL3_USBACTEP_OFFSET          0xb60
-#define GC_USB_DOEPCTL3_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL3_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL3_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL3_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL3_DPID_OFFSET              0xb60
-#define GC_USB_DOEPCTL3_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL3_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL3_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL3_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL3_NAKSTS_OFFSET            0xb60
-#define GC_USB_DOEPCTL3_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL3_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL3_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL3_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL3_EPTYPE_OFFSET            0xb60
-#define GC_USB_DOEPCTL3_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL3_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL3_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL3_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL3_SNP_OFFSET               0xb60
-#define GC_USB_DOEPCTL3_STALL_LSB                0x15
-#define GC_USB_DOEPCTL3_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL3_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL3_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL3_STALL_OFFSET             0xb60
-#define GC_USB_DOEPCTL3_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL3_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL3_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL3_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL3_CNAK_OFFSET              0xb60
-#define GC_USB_DOEPCTL3_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL3_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL3_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL3_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL3_SNAK_OFFSET              0xb60
-#define GC_USB_DOEPCTL3_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL3_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL3_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL3_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL3_SETD0PID_OFFSET          0xb60
-#define GC_USB_DOEPCTL3_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL3_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL3_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL3_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL3_SETD1PID_OFFSET          0xb60
-#define GC_USB_DOEPCTL3_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL3_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL3_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL3_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL3_EPDIS_OFFSET             0xb60
-#define GC_USB_DOEPCTL3_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL3_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL3_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL3_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL3_EPENA_OFFSET             0xb60
-#define GC_USB_DOEPINT3_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT3_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT3_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT3_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT3_XFERCOMPL_OFFSET         0xb68
-#define GC_USB_DOEPINT3_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT3_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT3_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT3_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT3_EPDISBLD_OFFSET          0xb68
-#define GC_USB_DOEPINT3_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT3_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT3_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT3_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT3_AHBERR_OFFSET            0xb68
-#define GC_USB_DOEPINT3_SETUP_LSB                0x3
-#define GC_USB_DOEPINT3_SETUP_MASK               0x8
-#define GC_USB_DOEPINT3_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT3_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT3_SETUP_OFFSET             0xb68
-#define GC_USB_DOEPINT3_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT3_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT3_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT3_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT3_OUTTKNEPDIS_OFFSET       0xb68
-#define GC_USB_DOEPINT3_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT3_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT3_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT3_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT3_STSPHSERCVD_OFFSET       0xb68
-#define GC_USB_DOEPINT3_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT3_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT3_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT3_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT3_BACK2BACKSETUP_OFFSET    0xb68
-#define GC_USB_DOEPINT3_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT3_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT3_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT3_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT3_OUTPKTERR_OFFSET         0xb68
-#define GC_USB_DOEPINT3_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT3_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT3_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT3_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT3_BNAINTR_OFFSET           0xb68
-#define GC_USB_DOEPINT3_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT3_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT3_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT3_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT3_PKTDRPSTS_OFFSET         0xb68
-#define GC_USB_DOEPINT3_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT3_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT3_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT3_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT3_BBLEERR_OFFSET           0xb68
-#define GC_USB_DOEPINT3_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT3_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT3_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT3_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT3_NAKINTRPT_OFFSET         0xb68
-#define GC_USB_DOEPINT3_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT3_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT3_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT3_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT3_NYETINTRPT_OFFSET        0xb68
-#define GC_USB_DOEPINT3_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT3_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT3_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT3_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT3_STUPPKTRCVD_OFFSET       0xb68
-#define GC_USB_DOEPTSIZ3_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ3_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ3_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ3_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ3_XFERSIZE_OFFSET         0xb70
-#define GC_USB_DOEPTSIZ3_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ3_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ3_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ3_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ3_PKTCNT_OFFSET           0xb70
-#define GC_USB_DOEPTSIZ3_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ3_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ3_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ3_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ3_RXDPID_OFFSET           0xb70
-#define GC_USB_DOEPDMA3_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA3_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA3_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA3_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA3_DMAADDR_OFFSET           0xb74
-#define GC_USB_DOEPDMAB3_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB3_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB3_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB3_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB3_DMABUFFERADDR_OFFSET    0xb7c
-#define GC_USB_DOEPCTL4_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL4_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL4_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL4_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL4_MPS_OFFSET               0xb80
-#define GC_USB_DOEPCTL4_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL4_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL4_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL4_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL4_USBACTEP_OFFSET          0xb80
-#define GC_USB_DOEPCTL4_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL4_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL4_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL4_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL4_DPID_OFFSET              0xb80
-#define GC_USB_DOEPCTL4_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL4_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL4_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL4_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL4_NAKSTS_OFFSET            0xb80
-#define GC_USB_DOEPCTL4_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL4_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL4_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL4_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL4_EPTYPE_OFFSET            0xb80
-#define GC_USB_DOEPCTL4_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL4_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL4_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL4_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL4_SNP_OFFSET               0xb80
-#define GC_USB_DOEPCTL4_STALL_LSB                0x15
-#define GC_USB_DOEPCTL4_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL4_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL4_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL4_STALL_OFFSET             0xb80
-#define GC_USB_DOEPCTL4_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL4_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL4_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL4_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL4_CNAK_OFFSET              0xb80
-#define GC_USB_DOEPCTL4_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL4_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL4_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL4_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL4_SNAK_OFFSET              0xb80
-#define GC_USB_DOEPCTL4_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL4_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL4_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL4_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL4_SETD0PID_OFFSET          0xb80
-#define GC_USB_DOEPCTL4_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL4_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL4_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL4_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL4_SETD1PID_OFFSET          0xb80
-#define GC_USB_DOEPCTL4_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL4_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL4_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL4_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL4_EPDIS_OFFSET             0xb80
-#define GC_USB_DOEPCTL4_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL4_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL4_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL4_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL4_EPENA_OFFSET             0xb80
-#define GC_USB_DOEPINT4_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT4_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT4_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT4_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT4_XFERCOMPL_OFFSET         0xb88
-#define GC_USB_DOEPINT4_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT4_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT4_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT4_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT4_EPDISBLD_OFFSET          0xb88
-#define GC_USB_DOEPINT4_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT4_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT4_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT4_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT4_AHBERR_OFFSET            0xb88
-#define GC_USB_DOEPINT4_SETUP_LSB                0x3
-#define GC_USB_DOEPINT4_SETUP_MASK               0x8
-#define GC_USB_DOEPINT4_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT4_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT4_SETUP_OFFSET             0xb88
-#define GC_USB_DOEPINT4_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT4_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT4_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT4_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT4_OUTTKNEPDIS_OFFSET       0xb88
-#define GC_USB_DOEPINT4_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT4_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT4_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT4_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT4_STSPHSERCVD_OFFSET       0xb88
-#define GC_USB_DOEPINT4_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT4_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT4_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT4_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT4_BACK2BACKSETUP_OFFSET    0xb88
-#define GC_USB_DOEPINT4_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT4_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT4_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT4_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT4_OUTPKTERR_OFFSET         0xb88
-#define GC_USB_DOEPINT4_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT4_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT4_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT4_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT4_BNAINTR_OFFSET           0xb88
-#define GC_USB_DOEPINT4_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT4_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT4_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT4_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT4_PKTDRPSTS_OFFSET         0xb88
-#define GC_USB_DOEPINT4_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT4_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT4_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT4_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT4_BBLEERR_OFFSET           0xb88
-#define GC_USB_DOEPINT4_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT4_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT4_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT4_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT4_NAKINTRPT_OFFSET         0xb88
-#define GC_USB_DOEPINT4_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT4_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT4_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT4_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT4_NYETINTRPT_OFFSET        0xb88
-#define GC_USB_DOEPINT4_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT4_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT4_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT4_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT4_STUPPKTRCVD_OFFSET       0xb88
-#define GC_USB_DOEPTSIZ4_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ4_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ4_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ4_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ4_XFERSIZE_OFFSET         0xb90
-#define GC_USB_DOEPTSIZ4_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ4_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ4_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ4_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ4_PKTCNT_OFFSET           0xb90
-#define GC_USB_DOEPTSIZ4_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ4_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ4_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ4_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ4_RXDPID_OFFSET           0xb90
-#define GC_USB_DOEPDMA4_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA4_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA4_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA4_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA4_DMAADDR_OFFSET           0xb94
-#define GC_USB_DOEPDMAB4_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB4_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB4_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB4_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB4_DMABUFFERADDR_OFFSET    0xb9c
-#define GC_USB_DOEPCTL5_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL5_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL5_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL5_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL5_MPS_OFFSET               0xba0
-#define GC_USB_DOEPCTL5_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL5_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL5_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL5_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL5_USBACTEP_OFFSET          0xba0
-#define GC_USB_DOEPCTL5_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL5_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL5_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL5_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL5_DPID_OFFSET              0xba0
-#define GC_USB_DOEPCTL5_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL5_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL5_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL5_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL5_NAKSTS_OFFSET            0xba0
-#define GC_USB_DOEPCTL5_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL5_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL5_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL5_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL5_EPTYPE_OFFSET            0xba0
-#define GC_USB_DOEPCTL5_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL5_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL5_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL5_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL5_SNP_OFFSET               0xba0
-#define GC_USB_DOEPCTL5_STALL_LSB                0x15
-#define GC_USB_DOEPCTL5_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL5_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL5_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL5_STALL_OFFSET             0xba0
-#define GC_USB_DOEPCTL5_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL5_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL5_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL5_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL5_CNAK_OFFSET              0xba0
-#define GC_USB_DOEPCTL5_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL5_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL5_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL5_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL5_SNAK_OFFSET              0xba0
-#define GC_USB_DOEPCTL5_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL5_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL5_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL5_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL5_SETD0PID_OFFSET          0xba0
-#define GC_USB_DOEPCTL5_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL5_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL5_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL5_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL5_SETD1PID_OFFSET          0xba0
-#define GC_USB_DOEPCTL5_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL5_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL5_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL5_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL5_EPDIS_OFFSET             0xba0
-#define GC_USB_DOEPCTL5_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL5_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL5_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL5_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL5_EPENA_OFFSET             0xba0
-#define GC_USB_DOEPINT5_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT5_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT5_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT5_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT5_XFERCOMPL_OFFSET         0xba8
-#define GC_USB_DOEPINT5_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT5_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT5_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT5_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT5_EPDISBLD_OFFSET          0xba8
-#define GC_USB_DOEPINT5_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT5_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT5_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT5_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT5_AHBERR_OFFSET            0xba8
-#define GC_USB_DOEPINT5_SETUP_LSB                0x3
-#define GC_USB_DOEPINT5_SETUP_MASK               0x8
-#define GC_USB_DOEPINT5_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT5_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT5_SETUP_OFFSET             0xba8
-#define GC_USB_DOEPINT5_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT5_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT5_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT5_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT5_OUTTKNEPDIS_OFFSET       0xba8
-#define GC_USB_DOEPINT5_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT5_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT5_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT5_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT5_STSPHSERCVD_OFFSET       0xba8
-#define GC_USB_DOEPINT5_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT5_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT5_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT5_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT5_BACK2BACKSETUP_OFFSET    0xba8
-#define GC_USB_DOEPINT5_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT5_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT5_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT5_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT5_OUTPKTERR_OFFSET         0xba8
-#define GC_USB_DOEPINT5_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT5_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT5_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT5_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT5_BNAINTR_OFFSET           0xba8
-#define GC_USB_DOEPINT5_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT5_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT5_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT5_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT5_PKTDRPSTS_OFFSET         0xba8
-#define GC_USB_DOEPINT5_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT5_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT5_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT5_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT5_BBLEERR_OFFSET           0xba8
-#define GC_USB_DOEPINT5_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT5_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT5_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT5_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT5_NAKINTRPT_OFFSET         0xba8
-#define GC_USB_DOEPINT5_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT5_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT5_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT5_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT5_NYETINTRPT_OFFSET        0xba8
-#define GC_USB_DOEPINT5_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT5_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT5_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT5_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT5_STUPPKTRCVD_OFFSET       0xba8
-#define GC_USB_DOEPTSIZ5_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ5_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ5_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ5_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ5_XFERSIZE_OFFSET         0xbb0
-#define GC_USB_DOEPTSIZ5_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ5_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ5_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ5_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ5_PKTCNT_OFFSET           0xbb0
-#define GC_USB_DOEPTSIZ5_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ5_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ5_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ5_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ5_RXDPID_OFFSET           0xbb0
-#define GC_USB_DOEPDMA5_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA5_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA5_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA5_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA5_DMAADDR_OFFSET           0xbb4
-#define GC_USB_DOEPDMAB5_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB5_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB5_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB5_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB5_DMABUFFERADDR_OFFSET    0xbbc
-#define GC_USB_DOEPCTL6_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL6_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL6_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL6_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL6_MPS_OFFSET               0xbc0
-#define GC_USB_DOEPCTL6_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL6_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL6_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL6_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL6_USBACTEP_OFFSET          0xbc0
-#define GC_USB_DOEPCTL6_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL6_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL6_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL6_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL6_DPID_OFFSET              0xbc0
-#define GC_USB_DOEPCTL6_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL6_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL6_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL6_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL6_NAKSTS_OFFSET            0xbc0
-#define GC_USB_DOEPCTL6_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL6_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL6_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL6_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL6_EPTYPE_OFFSET            0xbc0
-#define GC_USB_DOEPCTL6_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL6_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL6_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL6_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL6_SNP_OFFSET               0xbc0
-#define GC_USB_DOEPCTL6_STALL_LSB                0x15
-#define GC_USB_DOEPCTL6_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL6_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL6_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL6_STALL_OFFSET             0xbc0
-#define GC_USB_DOEPCTL6_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL6_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL6_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL6_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL6_CNAK_OFFSET              0xbc0
-#define GC_USB_DOEPCTL6_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL6_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL6_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL6_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL6_SNAK_OFFSET              0xbc0
-#define GC_USB_DOEPCTL6_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL6_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL6_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL6_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL6_SETD0PID_OFFSET          0xbc0
-#define GC_USB_DOEPCTL6_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL6_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL6_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL6_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL6_SETD1PID_OFFSET          0xbc0
-#define GC_USB_DOEPCTL6_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL6_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL6_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL6_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL6_EPDIS_OFFSET             0xbc0
-#define GC_USB_DOEPCTL6_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL6_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL6_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL6_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL6_EPENA_OFFSET             0xbc0
-#define GC_USB_DOEPINT6_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT6_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT6_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT6_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT6_XFERCOMPL_OFFSET         0xbc8
-#define GC_USB_DOEPINT6_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT6_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT6_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT6_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT6_EPDISBLD_OFFSET          0xbc8
-#define GC_USB_DOEPINT6_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT6_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT6_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT6_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT6_AHBERR_OFFSET            0xbc8
-#define GC_USB_DOEPINT6_SETUP_LSB                0x3
-#define GC_USB_DOEPINT6_SETUP_MASK               0x8
-#define GC_USB_DOEPINT6_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT6_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT6_SETUP_OFFSET             0xbc8
-#define GC_USB_DOEPINT6_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT6_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT6_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT6_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT6_OUTTKNEPDIS_OFFSET       0xbc8
-#define GC_USB_DOEPINT6_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT6_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT6_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT6_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT6_STSPHSERCVD_OFFSET       0xbc8
-#define GC_USB_DOEPINT6_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT6_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT6_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT6_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT6_BACK2BACKSETUP_OFFSET    0xbc8
-#define GC_USB_DOEPINT6_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT6_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT6_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT6_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT6_OUTPKTERR_OFFSET         0xbc8
-#define GC_USB_DOEPINT6_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT6_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT6_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT6_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT6_BNAINTR_OFFSET           0xbc8
-#define GC_USB_DOEPINT6_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT6_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT6_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT6_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT6_PKTDRPSTS_OFFSET         0xbc8
-#define GC_USB_DOEPINT6_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT6_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT6_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT6_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT6_BBLEERR_OFFSET           0xbc8
-#define GC_USB_DOEPINT6_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT6_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT6_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT6_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT6_NAKINTRPT_OFFSET         0xbc8
-#define GC_USB_DOEPINT6_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT6_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT6_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT6_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT6_NYETINTRPT_OFFSET        0xbc8
-#define GC_USB_DOEPINT6_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT6_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT6_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT6_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT6_STUPPKTRCVD_OFFSET       0xbc8
-#define GC_USB_DOEPTSIZ6_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ6_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ6_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ6_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ6_XFERSIZE_OFFSET         0xbd0
-#define GC_USB_DOEPTSIZ6_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ6_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ6_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ6_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ6_PKTCNT_OFFSET           0xbd0
-#define GC_USB_DOEPTSIZ6_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ6_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ6_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ6_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ6_RXDPID_OFFSET           0xbd0
-#define GC_USB_DOEPDMA6_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA6_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA6_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA6_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA6_DMAADDR_OFFSET           0xbd4
-#define GC_USB_DOEPDMAB6_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB6_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB6_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB6_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB6_DMABUFFERADDR_OFFSET    0xbdc
-#define GC_USB_DOEPCTL7_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL7_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL7_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL7_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL7_MPS_OFFSET               0xbe0
-#define GC_USB_DOEPCTL7_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL7_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL7_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL7_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL7_USBACTEP_OFFSET          0xbe0
-#define GC_USB_DOEPCTL7_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL7_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL7_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL7_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL7_DPID_OFFSET              0xbe0
-#define GC_USB_DOEPCTL7_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL7_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL7_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL7_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL7_NAKSTS_OFFSET            0xbe0
-#define GC_USB_DOEPCTL7_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL7_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL7_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL7_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL7_EPTYPE_OFFSET            0xbe0
-#define GC_USB_DOEPCTL7_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL7_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL7_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL7_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL7_SNP_OFFSET               0xbe0
-#define GC_USB_DOEPCTL7_STALL_LSB                0x15
-#define GC_USB_DOEPCTL7_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL7_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL7_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL7_STALL_OFFSET             0xbe0
-#define GC_USB_DOEPCTL7_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL7_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL7_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL7_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL7_CNAK_OFFSET              0xbe0
-#define GC_USB_DOEPCTL7_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL7_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL7_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL7_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL7_SNAK_OFFSET              0xbe0
-#define GC_USB_DOEPCTL7_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL7_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL7_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL7_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL7_SETD0PID_OFFSET          0xbe0
-#define GC_USB_DOEPCTL7_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL7_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL7_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL7_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL7_SETD1PID_OFFSET          0xbe0
-#define GC_USB_DOEPCTL7_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL7_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL7_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL7_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL7_EPDIS_OFFSET             0xbe0
-#define GC_USB_DOEPCTL7_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL7_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL7_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL7_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL7_EPENA_OFFSET             0xbe0
-#define GC_USB_DOEPINT7_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT7_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT7_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT7_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT7_XFERCOMPL_OFFSET         0xbe8
-#define GC_USB_DOEPINT7_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT7_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT7_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT7_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT7_EPDISBLD_OFFSET          0xbe8
-#define GC_USB_DOEPINT7_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT7_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT7_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT7_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT7_AHBERR_OFFSET            0xbe8
-#define GC_USB_DOEPINT7_SETUP_LSB                0x3
-#define GC_USB_DOEPINT7_SETUP_MASK               0x8
-#define GC_USB_DOEPINT7_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT7_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT7_SETUP_OFFSET             0xbe8
-#define GC_USB_DOEPINT7_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT7_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT7_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT7_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT7_OUTTKNEPDIS_OFFSET       0xbe8
-#define GC_USB_DOEPINT7_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT7_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT7_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT7_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT7_STSPHSERCVD_OFFSET       0xbe8
-#define GC_USB_DOEPINT7_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT7_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT7_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT7_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT7_BACK2BACKSETUP_OFFSET    0xbe8
-#define GC_USB_DOEPINT7_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT7_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT7_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT7_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT7_OUTPKTERR_OFFSET         0xbe8
-#define GC_USB_DOEPINT7_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT7_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT7_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT7_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT7_BNAINTR_OFFSET           0xbe8
-#define GC_USB_DOEPINT7_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT7_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT7_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT7_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT7_PKTDRPSTS_OFFSET         0xbe8
-#define GC_USB_DOEPINT7_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT7_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT7_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT7_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT7_BBLEERR_OFFSET           0xbe8
-#define GC_USB_DOEPINT7_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT7_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT7_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT7_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT7_NAKINTRPT_OFFSET         0xbe8
-#define GC_USB_DOEPINT7_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT7_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT7_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT7_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT7_NYETINTRPT_OFFSET        0xbe8
-#define GC_USB_DOEPINT7_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT7_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT7_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT7_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT7_STUPPKTRCVD_OFFSET       0xbe8
-#define GC_USB_DOEPTSIZ7_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ7_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ7_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ7_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ7_XFERSIZE_OFFSET         0xbf0
-#define GC_USB_DOEPTSIZ7_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ7_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ7_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ7_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ7_PKTCNT_OFFSET           0xbf0
-#define GC_USB_DOEPTSIZ7_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ7_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ7_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ7_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ7_RXDPID_OFFSET           0xbf0
-#define GC_USB_DOEPDMA7_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA7_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA7_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA7_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA7_DMAADDR_OFFSET           0xbf4
-#define GC_USB_DOEPDMAB7_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB7_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB7_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB7_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB7_DMABUFFERADDR_OFFSET    0xbfc
-#define GC_USB_DOEPCTL8_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL8_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL8_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL8_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL8_MPS_OFFSET               0xc00
-#define GC_USB_DOEPCTL8_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL8_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL8_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL8_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL8_USBACTEP_OFFSET          0xc00
-#define GC_USB_DOEPCTL8_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL8_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL8_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL8_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL8_DPID_OFFSET              0xc00
-#define GC_USB_DOEPCTL8_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL8_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL8_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL8_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL8_NAKSTS_OFFSET            0xc00
-#define GC_USB_DOEPCTL8_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL8_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL8_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL8_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL8_EPTYPE_OFFSET            0xc00
-#define GC_USB_DOEPCTL8_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL8_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL8_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL8_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL8_SNP_OFFSET               0xc00
-#define GC_USB_DOEPCTL8_STALL_LSB                0x15
-#define GC_USB_DOEPCTL8_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL8_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL8_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL8_STALL_OFFSET             0xc00
-#define GC_USB_DOEPCTL8_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL8_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL8_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL8_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL8_CNAK_OFFSET              0xc00
-#define GC_USB_DOEPCTL8_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL8_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL8_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL8_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL8_SNAK_OFFSET              0xc00
-#define GC_USB_DOEPCTL8_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL8_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL8_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL8_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL8_SETD0PID_OFFSET          0xc00
-#define GC_USB_DOEPCTL8_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL8_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL8_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL8_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL8_SETD1PID_OFFSET          0xc00
-#define GC_USB_DOEPCTL8_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL8_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL8_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL8_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL8_EPDIS_OFFSET             0xc00
-#define GC_USB_DOEPCTL8_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL8_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL8_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL8_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL8_EPENA_OFFSET             0xc00
-#define GC_USB_DOEPINT8_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT8_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT8_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT8_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT8_XFERCOMPL_OFFSET         0xc08
-#define GC_USB_DOEPINT8_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT8_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT8_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT8_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT8_EPDISBLD_OFFSET          0xc08
-#define GC_USB_DOEPINT8_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT8_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT8_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT8_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT8_AHBERR_OFFSET            0xc08
-#define GC_USB_DOEPINT8_SETUP_LSB                0x3
-#define GC_USB_DOEPINT8_SETUP_MASK               0x8
-#define GC_USB_DOEPINT8_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT8_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT8_SETUP_OFFSET             0xc08
-#define GC_USB_DOEPINT8_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT8_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT8_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT8_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT8_OUTTKNEPDIS_OFFSET       0xc08
-#define GC_USB_DOEPINT8_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT8_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT8_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT8_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT8_STSPHSERCVD_OFFSET       0xc08
-#define GC_USB_DOEPINT8_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT8_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT8_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT8_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT8_BACK2BACKSETUP_OFFSET    0xc08
-#define GC_USB_DOEPINT8_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT8_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT8_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT8_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT8_OUTPKTERR_OFFSET         0xc08
-#define GC_USB_DOEPINT8_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT8_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT8_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT8_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT8_BNAINTR_OFFSET           0xc08
-#define GC_USB_DOEPINT8_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT8_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT8_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT8_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT8_PKTDRPSTS_OFFSET         0xc08
-#define GC_USB_DOEPINT8_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT8_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT8_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT8_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT8_BBLEERR_OFFSET           0xc08
-#define GC_USB_DOEPINT8_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT8_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT8_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT8_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT8_NAKINTRPT_OFFSET         0xc08
-#define GC_USB_DOEPINT8_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT8_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT8_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT8_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT8_NYETINTRPT_OFFSET        0xc08
-#define GC_USB_DOEPINT8_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT8_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT8_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT8_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT8_STUPPKTRCVD_OFFSET       0xc08
-#define GC_USB_DOEPTSIZ8_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ8_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ8_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ8_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ8_XFERSIZE_OFFSET         0xc10
-#define GC_USB_DOEPTSIZ8_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ8_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ8_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ8_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ8_PKTCNT_OFFSET           0xc10
-#define GC_USB_DOEPTSIZ8_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ8_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ8_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ8_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ8_RXDPID_OFFSET           0xc10
-#define GC_USB_DOEPDMA8_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA8_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA8_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA8_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA8_DMAADDR_OFFSET           0xc14
-#define GC_USB_DOEPDMAB8_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB8_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB8_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB8_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB8_DMABUFFERADDR_OFFSET    0xc1c
-#define GC_USB_DOEPCTL9_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL9_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL9_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL9_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL9_MPS_OFFSET               0xc20
-#define GC_USB_DOEPCTL9_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL9_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL9_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL9_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL9_USBACTEP_OFFSET          0xc20
-#define GC_USB_DOEPCTL9_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL9_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL9_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL9_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL9_DPID_OFFSET              0xc20
-#define GC_USB_DOEPCTL9_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL9_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL9_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL9_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL9_NAKSTS_OFFSET            0xc20
-#define GC_USB_DOEPCTL9_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL9_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL9_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL9_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL9_EPTYPE_OFFSET            0xc20
-#define GC_USB_DOEPCTL9_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL9_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL9_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL9_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL9_SNP_OFFSET               0xc20
-#define GC_USB_DOEPCTL9_STALL_LSB                0x15
-#define GC_USB_DOEPCTL9_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL9_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL9_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL9_STALL_OFFSET             0xc20
-#define GC_USB_DOEPCTL9_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL9_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL9_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL9_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL9_CNAK_OFFSET              0xc20
-#define GC_USB_DOEPCTL9_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL9_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL9_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL9_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL9_SNAK_OFFSET              0xc20
-#define GC_USB_DOEPCTL9_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL9_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL9_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL9_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL9_SETD0PID_OFFSET          0xc20
-#define GC_USB_DOEPCTL9_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL9_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL9_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL9_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL9_SETD1PID_OFFSET          0xc20
-#define GC_USB_DOEPCTL9_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL9_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL9_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL9_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL9_EPDIS_OFFSET             0xc20
-#define GC_USB_DOEPCTL9_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL9_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL9_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL9_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL9_EPENA_OFFSET             0xc20
-#define GC_USB_DOEPINT9_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT9_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT9_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT9_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT9_XFERCOMPL_OFFSET         0xc28
-#define GC_USB_DOEPINT9_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT9_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT9_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT9_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT9_EPDISBLD_OFFSET          0xc28
-#define GC_USB_DOEPINT9_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT9_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT9_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT9_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT9_AHBERR_OFFSET            0xc28
-#define GC_USB_DOEPINT9_SETUP_LSB                0x3
-#define GC_USB_DOEPINT9_SETUP_MASK               0x8
-#define GC_USB_DOEPINT9_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT9_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT9_SETUP_OFFSET             0xc28
-#define GC_USB_DOEPINT9_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT9_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT9_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT9_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT9_OUTTKNEPDIS_OFFSET       0xc28
-#define GC_USB_DOEPINT9_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT9_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT9_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT9_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT9_STSPHSERCVD_OFFSET       0xc28
-#define GC_USB_DOEPINT9_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT9_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT9_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT9_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT9_BACK2BACKSETUP_OFFSET    0xc28
-#define GC_USB_DOEPINT9_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT9_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT9_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT9_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT9_OUTPKTERR_OFFSET         0xc28
-#define GC_USB_DOEPINT9_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT9_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT9_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT9_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT9_BNAINTR_OFFSET           0xc28
-#define GC_USB_DOEPINT9_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT9_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT9_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT9_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT9_PKTDRPSTS_OFFSET         0xc28
-#define GC_USB_DOEPINT9_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT9_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT9_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT9_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT9_BBLEERR_OFFSET           0xc28
-#define GC_USB_DOEPINT9_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT9_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT9_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT9_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT9_NAKINTRPT_OFFSET         0xc28
-#define GC_USB_DOEPINT9_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT9_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT9_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT9_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT9_NYETINTRPT_OFFSET        0xc28
-#define GC_USB_DOEPINT9_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT9_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT9_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT9_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT9_STUPPKTRCVD_OFFSET       0xc28
-#define GC_USB_DOEPTSIZ9_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ9_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ9_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ9_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ9_XFERSIZE_OFFSET         0xc30
-#define GC_USB_DOEPTSIZ9_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ9_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ9_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ9_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ9_PKTCNT_OFFSET           0xc30
-#define GC_USB_DOEPTSIZ9_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ9_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ9_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ9_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ9_RXDPID_OFFSET           0xc30
-#define GC_USB_DOEPDMA9_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA9_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA9_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA9_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA9_DMAADDR_OFFSET           0xc34
-#define GC_USB_DOEPDMAB9_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB9_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB9_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB9_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB9_DMABUFFERADDR_OFFSET    0xc3c
-#define GC_USB_DOEPCTL10_MPS_LSB                 0x0
-#define GC_USB_DOEPCTL10_MPS_MASK                0x7ff
-#define GC_USB_DOEPCTL10_MPS_SIZE                0xb
-#define GC_USB_DOEPCTL10_MPS_DEFAULT             0x0
-#define GC_USB_DOEPCTL10_MPS_OFFSET              0xc40
-#define GC_USB_DOEPCTL10_USBACTEP_LSB            0xf
-#define GC_USB_DOEPCTL10_USBACTEP_MASK           0x8000
-#define GC_USB_DOEPCTL10_USBACTEP_SIZE           0x1
-#define GC_USB_DOEPCTL10_USBACTEP_DEFAULT        0x0
-#define GC_USB_DOEPCTL10_USBACTEP_OFFSET         0xc40
-#define GC_USB_DOEPCTL10_DPID_LSB                0x10
-#define GC_USB_DOEPCTL10_DPID_MASK               0x10000
-#define GC_USB_DOEPCTL10_DPID_SIZE               0x1
-#define GC_USB_DOEPCTL10_DPID_DEFAULT            0x0
-#define GC_USB_DOEPCTL10_DPID_OFFSET             0xc40
-#define GC_USB_DOEPCTL10_NAKSTS_LSB              0x11
-#define GC_USB_DOEPCTL10_NAKSTS_MASK             0x20000
-#define GC_USB_DOEPCTL10_NAKSTS_SIZE             0x1
-#define GC_USB_DOEPCTL10_NAKSTS_DEFAULT          0x0
-#define GC_USB_DOEPCTL10_NAKSTS_OFFSET           0xc40
-#define GC_USB_DOEPCTL10_EPTYPE_LSB              0x12
-#define GC_USB_DOEPCTL10_EPTYPE_MASK             0xc0000
-#define GC_USB_DOEPCTL10_EPTYPE_SIZE             0x2
-#define GC_USB_DOEPCTL10_EPTYPE_DEFAULT          0x0
-#define GC_USB_DOEPCTL10_EPTYPE_OFFSET           0xc40
-#define GC_USB_DOEPCTL10_SNP_LSB                 0x14
-#define GC_USB_DOEPCTL10_SNP_MASK                0x100000
-#define GC_USB_DOEPCTL10_SNP_SIZE                0x1
-#define GC_USB_DOEPCTL10_SNP_DEFAULT             0x0
-#define GC_USB_DOEPCTL10_SNP_OFFSET              0xc40
-#define GC_USB_DOEPCTL10_STALL_LSB               0x15
-#define GC_USB_DOEPCTL10_STALL_MASK              0x200000
-#define GC_USB_DOEPCTL10_STALL_SIZE              0x1
-#define GC_USB_DOEPCTL10_STALL_DEFAULT           0x0
-#define GC_USB_DOEPCTL10_STALL_OFFSET            0xc40
-#define GC_USB_DOEPCTL10_CNAK_LSB                0x1a
-#define GC_USB_DOEPCTL10_CNAK_MASK               0x4000000
-#define GC_USB_DOEPCTL10_CNAK_SIZE               0x1
-#define GC_USB_DOEPCTL10_CNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL10_CNAK_OFFSET             0xc40
-#define GC_USB_DOEPCTL10_SNAK_LSB                0x1b
-#define GC_USB_DOEPCTL10_SNAK_MASK               0x8000000
-#define GC_USB_DOEPCTL10_SNAK_SIZE               0x1
-#define GC_USB_DOEPCTL10_SNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL10_SNAK_OFFSET             0xc40
-#define GC_USB_DOEPCTL10_SETD0PID_LSB            0x1c
-#define GC_USB_DOEPCTL10_SETD0PID_MASK           0x10000000
-#define GC_USB_DOEPCTL10_SETD0PID_SIZE           0x1
-#define GC_USB_DOEPCTL10_SETD0PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL10_SETD0PID_OFFSET         0xc40
-#define GC_USB_DOEPCTL10_SETD1PID_LSB            0x1d
-#define GC_USB_DOEPCTL10_SETD1PID_MASK           0x20000000
-#define GC_USB_DOEPCTL10_SETD1PID_SIZE           0x1
-#define GC_USB_DOEPCTL10_SETD1PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL10_SETD1PID_OFFSET         0xc40
-#define GC_USB_DOEPCTL10_EPDIS_LSB               0x1e
-#define GC_USB_DOEPCTL10_EPDIS_MASK              0x40000000
-#define GC_USB_DOEPCTL10_EPDIS_SIZE              0x1
-#define GC_USB_DOEPCTL10_EPDIS_DEFAULT           0x0
-#define GC_USB_DOEPCTL10_EPDIS_OFFSET            0xc40
-#define GC_USB_DOEPCTL10_EPENA_LSB               0x1f
-#define GC_USB_DOEPCTL10_EPENA_MASK              0x80000000
-#define GC_USB_DOEPCTL10_EPENA_SIZE              0x1
-#define GC_USB_DOEPCTL10_EPENA_DEFAULT           0x0
-#define GC_USB_DOEPCTL10_EPENA_OFFSET            0xc40
-#define GC_USB_DOEPINT10_XFERCOMPL_LSB           0x0
-#define GC_USB_DOEPINT10_XFERCOMPL_MASK          0x1
-#define GC_USB_DOEPINT10_XFERCOMPL_SIZE          0x1
-#define GC_USB_DOEPINT10_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DOEPINT10_XFERCOMPL_OFFSET        0xc48
-#define GC_USB_DOEPINT10_EPDISBLD_LSB            0x1
-#define GC_USB_DOEPINT10_EPDISBLD_MASK           0x2
-#define GC_USB_DOEPINT10_EPDISBLD_SIZE           0x1
-#define GC_USB_DOEPINT10_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DOEPINT10_EPDISBLD_OFFSET         0xc48
-#define GC_USB_DOEPINT10_AHBERR_LSB              0x2
-#define GC_USB_DOEPINT10_AHBERR_MASK             0x4
-#define GC_USB_DOEPINT10_AHBERR_SIZE             0x1
-#define GC_USB_DOEPINT10_AHBERR_DEFAULT          0x0
-#define GC_USB_DOEPINT10_AHBERR_OFFSET           0xc48
-#define GC_USB_DOEPINT10_SETUP_LSB               0x3
-#define GC_USB_DOEPINT10_SETUP_MASK              0x8
-#define GC_USB_DOEPINT10_SETUP_SIZE              0x1
-#define GC_USB_DOEPINT10_SETUP_DEFAULT           0x0
-#define GC_USB_DOEPINT10_SETUP_OFFSET            0xc48
-#define GC_USB_DOEPINT10_OUTTKNEPDIS_LSB         0x4
-#define GC_USB_DOEPINT10_OUTTKNEPDIS_MASK        0x10
-#define GC_USB_DOEPINT10_OUTTKNEPDIS_SIZE        0x1
-#define GC_USB_DOEPINT10_OUTTKNEPDIS_DEFAULT     0x0
-#define GC_USB_DOEPINT10_OUTTKNEPDIS_OFFSET      0xc48
-#define GC_USB_DOEPINT10_STSPHSERCVD_LSB         0x5
-#define GC_USB_DOEPINT10_STSPHSERCVD_MASK        0x20
-#define GC_USB_DOEPINT10_STSPHSERCVD_SIZE        0x1
-#define GC_USB_DOEPINT10_STSPHSERCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT10_STSPHSERCVD_OFFSET      0xc48
-#define GC_USB_DOEPINT10_BACK2BACKSETUP_LSB      0x6
-#define GC_USB_DOEPINT10_BACK2BACKSETUP_MASK     0x40
-#define GC_USB_DOEPINT10_BACK2BACKSETUP_SIZE     0x1
-#define GC_USB_DOEPINT10_BACK2BACKSETUP_DEFAULT  0x0
-#define GC_USB_DOEPINT10_BACK2BACKSETUP_OFFSET   0xc48
-#define GC_USB_DOEPINT10_OUTPKTERR_LSB           0x8
-#define GC_USB_DOEPINT10_OUTPKTERR_MASK          0x100
-#define GC_USB_DOEPINT10_OUTPKTERR_SIZE          0x1
-#define GC_USB_DOEPINT10_OUTPKTERR_DEFAULT       0x0
-#define GC_USB_DOEPINT10_OUTPKTERR_OFFSET        0xc48
-#define GC_USB_DOEPINT10_BNAINTR_LSB             0x9
-#define GC_USB_DOEPINT10_BNAINTR_MASK            0x200
-#define GC_USB_DOEPINT10_BNAINTR_SIZE            0x1
-#define GC_USB_DOEPINT10_BNAINTR_DEFAULT         0x0
-#define GC_USB_DOEPINT10_BNAINTR_OFFSET          0xc48
-#define GC_USB_DOEPINT10_PKTDRPSTS_LSB           0xb
-#define GC_USB_DOEPINT10_PKTDRPSTS_MASK          0x800
-#define GC_USB_DOEPINT10_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DOEPINT10_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DOEPINT10_PKTDRPSTS_OFFSET        0xc48
-#define GC_USB_DOEPINT10_BBLEERR_LSB             0xc
-#define GC_USB_DOEPINT10_BBLEERR_MASK            0x1000
-#define GC_USB_DOEPINT10_BBLEERR_SIZE            0x1
-#define GC_USB_DOEPINT10_BBLEERR_DEFAULT         0x0
-#define GC_USB_DOEPINT10_BBLEERR_OFFSET          0xc48
-#define GC_USB_DOEPINT10_NAKINTRPT_LSB           0xd
-#define GC_USB_DOEPINT10_NAKINTRPT_MASK          0x2000
-#define GC_USB_DOEPINT10_NAKINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT10_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT10_NAKINTRPT_OFFSET        0xc48
-#define GC_USB_DOEPINT10_NYETINTRPT_LSB          0xe
-#define GC_USB_DOEPINT10_NYETINTRPT_MASK         0x4000
-#define GC_USB_DOEPINT10_NYETINTRPT_SIZE         0x1
-#define GC_USB_DOEPINT10_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DOEPINT10_NYETINTRPT_OFFSET       0xc48
-#define GC_USB_DOEPINT10_STUPPKTRCVD_LSB         0xf
-#define GC_USB_DOEPINT10_STUPPKTRCVD_MASK        0x8000
-#define GC_USB_DOEPINT10_STUPPKTRCVD_SIZE        0x1
-#define GC_USB_DOEPINT10_STUPPKTRCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT10_STUPPKTRCVD_OFFSET      0xc48
-#define GC_USB_DOEPTSIZ10_XFERSIZE_LSB           0x0
-#define GC_USB_DOEPTSIZ10_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DOEPTSIZ10_XFERSIZE_SIZE          0x13
-#define GC_USB_DOEPTSIZ10_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DOEPTSIZ10_XFERSIZE_OFFSET        0xc50
-#define GC_USB_DOEPTSIZ10_PKTCNT_LSB             0x13
-#define GC_USB_DOEPTSIZ10_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DOEPTSIZ10_PKTCNT_SIZE            0xa
-#define GC_USB_DOEPTSIZ10_PKTCNT_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ10_PKTCNT_OFFSET          0xc50
-#define GC_USB_DOEPTSIZ10_RXDPID_LSB             0x1d
-#define GC_USB_DOEPTSIZ10_RXDPID_MASK            0x60000000
-#define GC_USB_DOEPTSIZ10_RXDPID_SIZE            0x2
-#define GC_USB_DOEPTSIZ10_RXDPID_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ10_RXDPID_OFFSET          0xc50
-#define GC_USB_DOEPDMA10_DMAADDR_LSB             0x0
-#define GC_USB_DOEPDMA10_DMAADDR_MASK            0xffffffff
-#define GC_USB_DOEPDMA10_DMAADDR_SIZE            0x20
-#define GC_USB_DOEPDMA10_DMAADDR_DEFAULT         0x0
-#define GC_USB_DOEPDMA10_DMAADDR_OFFSET          0xc54
-#define GC_USB_DOEPDMAB10_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DOEPDMAB10_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DOEPDMAB10_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DOEPDMAB10_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DOEPDMAB10_DMABUFFERADDR_OFFSET   0xc5c
-#define GC_USB_DOEPCTL11_MPS_LSB                 0x0
-#define GC_USB_DOEPCTL11_MPS_MASK                0x7ff
-#define GC_USB_DOEPCTL11_MPS_SIZE                0xb
-#define GC_USB_DOEPCTL11_MPS_DEFAULT             0x0
-#define GC_USB_DOEPCTL11_MPS_OFFSET              0xc60
-#define GC_USB_DOEPCTL11_USBACTEP_LSB            0xf
-#define GC_USB_DOEPCTL11_USBACTEP_MASK           0x8000
-#define GC_USB_DOEPCTL11_USBACTEP_SIZE           0x1
-#define GC_USB_DOEPCTL11_USBACTEP_DEFAULT        0x0
-#define GC_USB_DOEPCTL11_USBACTEP_OFFSET         0xc60
-#define GC_USB_DOEPCTL11_DPID_LSB                0x10
-#define GC_USB_DOEPCTL11_DPID_MASK               0x10000
-#define GC_USB_DOEPCTL11_DPID_SIZE               0x1
-#define GC_USB_DOEPCTL11_DPID_DEFAULT            0x0
-#define GC_USB_DOEPCTL11_DPID_OFFSET             0xc60
-#define GC_USB_DOEPCTL11_NAKSTS_LSB              0x11
-#define GC_USB_DOEPCTL11_NAKSTS_MASK             0x20000
-#define GC_USB_DOEPCTL11_NAKSTS_SIZE             0x1
-#define GC_USB_DOEPCTL11_NAKSTS_DEFAULT          0x0
-#define GC_USB_DOEPCTL11_NAKSTS_OFFSET           0xc60
-#define GC_USB_DOEPCTL11_EPTYPE_LSB              0x12
-#define GC_USB_DOEPCTL11_EPTYPE_MASK             0xc0000
-#define GC_USB_DOEPCTL11_EPTYPE_SIZE             0x2
-#define GC_USB_DOEPCTL11_EPTYPE_DEFAULT          0x0
-#define GC_USB_DOEPCTL11_EPTYPE_OFFSET           0xc60
-#define GC_USB_DOEPCTL11_SNP_LSB                 0x14
-#define GC_USB_DOEPCTL11_SNP_MASK                0x100000
-#define GC_USB_DOEPCTL11_SNP_SIZE                0x1
-#define GC_USB_DOEPCTL11_SNP_DEFAULT             0x0
-#define GC_USB_DOEPCTL11_SNP_OFFSET              0xc60
-#define GC_USB_DOEPCTL11_STALL_LSB               0x15
-#define GC_USB_DOEPCTL11_STALL_MASK              0x200000
-#define GC_USB_DOEPCTL11_STALL_SIZE              0x1
-#define GC_USB_DOEPCTL11_STALL_DEFAULT           0x0
-#define GC_USB_DOEPCTL11_STALL_OFFSET            0xc60
-#define GC_USB_DOEPCTL11_CNAK_LSB                0x1a
-#define GC_USB_DOEPCTL11_CNAK_MASK               0x4000000
-#define GC_USB_DOEPCTL11_CNAK_SIZE               0x1
-#define GC_USB_DOEPCTL11_CNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL11_CNAK_OFFSET             0xc60
-#define GC_USB_DOEPCTL11_SNAK_LSB                0x1b
-#define GC_USB_DOEPCTL11_SNAK_MASK               0x8000000
-#define GC_USB_DOEPCTL11_SNAK_SIZE               0x1
-#define GC_USB_DOEPCTL11_SNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL11_SNAK_OFFSET             0xc60
-#define GC_USB_DOEPCTL11_SETD0PID_LSB            0x1c
-#define GC_USB_DOEPCTL11_SETD0PID_MASK           0x10000000
-#define GC_USB_DOEPCTL11_SETD0PID_SIZE           0x1
-#define GC_USB_DOEPCTL11_SETD0PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL11_SETD0PID_OFFSET         0xc60
-#define GC_USB_DOEPCTL11_SETD1PID_LSB            0x1d
-#define GC_USB_DOEPCTL11_SETD1PID_MASK           0x20000000
-#define GC_USB_DOEPCTL11_SETD1PID_SIZE           0x1
-#define GC_USB_DOEPCTL11_SETD1PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL11_SETD1PID_OFFSET         0xc60
-#define GC_USB_DOEPCTL11_EPDIS_LSB               0x1e
-#define GC_USB_DOEPCTL11_EPDIS_MASK              0x40000000
-#define GC_USB_DOEPCTL11_EPDIS_SIZE              0x1
-#define GC_USB_DOEPCTL11_EPDIS_DEFAULT           0x0
-#define GC_USB_DOEPCTL11_EPDIS_OFFSET            0xc60
-#define GC_USB_DOEPCTL11_EPENA_LSB               0x1f
-#define GC_USB_DOEPCTL11_EPENA_MASK              0x80000000
-#define GC_USB_DOEPCTL11_EPENA_SIZE              0x1
-#define GC_USB_DOEPCTL11_EPENA_DEFAULT           0x0
-#define GC_USB_DOEPCTL11_EPENA_OFFSET            0xc60
-#define GC_USB_DOEPINT11_XFERCOMPL_LSB           0x0
-#define GC_USB_DOEPINT11_XFERCOMPL_MASK          0x1
-#define GC_USB_DOEPINT11_XFERCOMPL_SIZE          0x1
-#define GC_USB_DOEPINT11_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DOEPINT11_XFERCOMPL_OFFSET        0xc68
-#define GC_USB_DOEPINT11_EPDISBLD_LSB            0x1
-#define GC_USB_DOEPINT11_EPDISBLD_MASK           0x2
-#define GC_USB_DOEPINT11_EPDISBLD_SIZE           0x1
-#define GC_USB_DOEPINT11_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DOEPINT11_EPDISBLD_OFFSET         0xc68
-#define GC_USB_DOEPINT11_AHBERR_LSB              0x2
-#define GC_USB_DOEPINT11_AHBERR_MASK             0x4
-#define GC_USB_DOEPINT11_AHBERR_SIZE             0x1
-#define GC_USB_DOEPINT11_AHBERR_DEFAULT          0x0
-#define GC_USB_DOEPINT11_AHBERR_OFFSET           0xc68
-#define GC_USB_DOEPINT11_SETUP_LSB               0x3
-#define GC_USB_DOEPINT11_SETUP_MASK              0x8
-#define GC_USB_DOEPINT11_SETUP_SIZE              0x1
-#define GC_USB_DOEPINT11_SETUP_DEFAULT           0x0
-#define GC_USB_DOEPINT11_SETUP_OFFSET            0xc68
-#define GC_USB_DOEPINT11_OUTTKNEPDIS_LSB         0x4
-#define GC_USB_DOEPINT11_OUTTKNEPDIS_MASK        0x10
-#define GC_USB_DOEPINT11_OUTTKNEPDIS_SIZE        0x1
-#define GC_USB_DOEPINT11_OUTTKNEPDIS_DEFAULT     0x0
-#define GC_USB_DOEPINT11_OUTTKNEPDIS_OFFSET      0xc68
-#define GC_USB_DOEPINT11_STSPHSERCVD_LSB         0x5
-#define GC_USB_DOEPINT11_STSPHSERCVD_MASK        0x20
-#define GC_USB_DOEPINT11_STSPHSERCVD_SIZE        0x1
-#define GC_USB_DOEPINT11_STSPHSERCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT11_STSPHSERCVD_OFFSET      0xc68
-#define GC_USB_DOEPINT11_BACK2BACKSETUP_LSB      0x6
-#define GC_USB_DOEPINT11_BACK2BACKSETUP_MASK     0x40
-#define GC_USB_DOEPINT11_BACK2BACKSETUP_SIZE     0x1
-#define GC_USB_DOEPINT11_BACK2BACKSETUP_DEFAULT  0x0
-#define GC_USB_DOEPINT11_BACK2BACKSETUP_OFFSET   0xc68
-#define GC_USB_DOEPINT11_OUTPKTERR_LSB           0x8
-#define GC_USB_DOEPINT11_OUTPKTERR_MASK          0x100
-#define GC_USB_DOEPINT11_OUTPKTERR_SIZE          0x1
-#define GC_USB_DOEPINT11_OUTPKTERR_DEFAULT       0x0
-#define GC_USB_DOEPINT11_OUTPKTERR_OFFSET        0xc68
-#define GC_USB_DOEPINT11_BNAINTR_LSB             0x9
-#define GC_USB_DOEPINT11_BNAINTR_MASK            0x200
-#define GC_USB_DOEPINT11_BNAINTR_SIZE            0x1
-#define GC_USB_DOEPINT11_BNAINTR_DEFAULT         0x0
-#define GC_USB_DOEPINT11_BNAINTR_OFFSET          0xc68
-#define GC_USB_DOEPINT11_PKTDRPSTS_LSB           0xb
-#define GC_USB_DOEPINT11_PKTDRPSTS_MASK          0x800
-#define GC_USB_DOEPINT11_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DOEPINT11_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DOEPINT11_PKTDRPSTS_OFFSET        0xc68
-#define GC_USB_DOEPINT11_BBLEERR_LSB             0xc
-#define GC_USB_DOEPINT11_BBLEERR_MASK            0x1000
-#define GC_USB_DOEPINT11_BBLEERR_SIZE            0x1
-#define GC_USB_DOEPINT11_BBLEERR_DEFAULT         0x0
-#define GC_USB_DOEPINT11_BBLEERR_OFFSET          0xc68
-#define GC_USB_DOEPINT11_NAKINTRPT_LSB           0xd
-#define GC_USB_DOEPINT11_NAKINTRPT_MASK          0x2000
-#define GC_USB_DOEPINT11_NAKINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT11_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT11_NAKINTRPT_OFFSET        0xc68
-#define GC_USB_DOEPINT11_NYETINTRPT_LSB          0xe
-#define GC_USB_DOEPINT11_NYETINTRPT_MASK         0x4000
-#define GC_USB_DOEPINT11_NYETINTRPT_SIZE         0x1
-#define GC_USB_DOEPINT11_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DOEPINT11_NYETINTRPT_OFFSET       0xc68
-#define GC_USB_DOEPINT11_STUPPKTRCVD_LSB         0xf
-#define GC_USB_DOEPINT11_STUPPKTRCVD_MASK        0x8000
-#define GC_USB_DOEPINT11_STUPPKTRCVD_SIZE        0x1
-#define GC_USB_DOEPINT11_STUPPKTRCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT11_STUPPKTRCVD_OFFSET      0xc68
-#define GC_USB_DOEPTSIZ11_XFERSIZE_LSB           0x0
-#define GC_USB_DOEPTSIZ11_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DOEPTSIZ11_XFERSIZE_SIZE          0x13
-#define GC_USB_DOEPTSIZ11_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DOEPTSIZ11_XFERSIZE_OFFSET        0xc70
-#define GC_USB_DOEPTSIZ11_PKTCNT_LSB             0x13
-#define GC_USB_DOEPTSIZ11_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DOEPTSIZ11_PKTCNT_SIZE            0xa
-#define GC_USB_DOEPTSIZ11_PKTCNT_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ11_PKTCNT_OFFSET          0xc70
-#define GC_USB_DOEPTSIZ11_RXDPID_LSB             0x1d
-#define GC_USB_DOEPTSIZ11_RXDPID_MASK            0x60000000
-#define GC_USB_DOEPTSIZ11_RXDPID_SIZE            0x2
-#define GC_USB_DOEPTSIZ11_RXDPID_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ11_RXDPID_OFFSET          0xc70
-#define GC_USB_DOEPDMA11_DMAADDR_LSB             0x0
-#define GC_USB_DOEPDMA11_DMAADDR_MASK            0xffffffff
-#define GC_USB_DOEPDMA11_DMAADDR_SIZE            0x20
-#define GC_USB_DOEPDMA11_DMAADDR_DEFAULT         0x0
-#define GC_USB_DOEPDMA11_DMAADDR_OFFSET          0xc74
-#define GC_USB_DOEPDMAB11_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DOEPDMAB11_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DOEPDMAB11_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DOEPDMAB11_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DOEPDMAB11_DMABUFFERADDR_OFFSET   0xc7c
-#define GC_USB_DOEPCTL12_MPS_LSB                 0x0
-#define GC_USB_DOEPCTL12_MPS_MASK                0x7ff
-#define GC_USB_DOEPCTL12_MPS_SIZE                0xb
-#define GC_USB_DOEPCTL12_MPS_DEFAULT             0x0
-#define GC_USB_DOEPCTL12_MPS_OFFSET              0xc80
-#define GC_USB_DOEPCTL12_USBACTEP_LSB            0xf
-#define GC_USB_DOEPCTL12_USBACTEP_MASK           0x8000
-#define GC_USB_DOEPCTL12_USBACTEP_SIZE           0x1
-#define GC_USB_DOEPCTL12_USBACTEP_DEFAULT        0x0
-#define GC_USB_DOEPCTL12_USBACTEP_OFFSET         0xc80
-#define GC_USB_DOEPCTL12_DPID_LSB                0x10
-#define GC_USB_DOEPCTL12_DPID_MASK               0x10000
-#define GC_USB_DOEPCTL12_DPID_SIZE               0x1
-#define GC_USB_DOEPCTL12_DPID_DEFAULT            0x0
-#define GC_USB_DOEPCTL12_DPID_OFFSET             0xc80
-#define GC_USB_DOEPCTL12_NAKSTS_LSB              0x11
-#define GC_USB_DOEPCTL12_NAKSTS_MASK             0x20000
-#define GC_USB_DOEPCTL12_NAKSTS_SIZE             0x1
-#define GC_USB_DOEPCTL12_NAKSTS_DEFAULT          0x0
-#define GC_USB_DOEPCTL12_NAKSTS_OFFSET           0xc80
-#define GC_USB_DOEPCTL12_EPTYPE_LSB              0x12
-#define GC_USB_DOEPCTL12_EPTYPE_MASK             0xc0000
-#define GC_USB_DOEPCTL12_EPTYPE_SIZE             0x2
-#define GC_USB_DOEPCTL12_EPTYPE_DEFAULT          0x0
-#define GC_USB_DOEPCTL12_EPTYPE_OFFSET           0xc80
-#define GC_USB_DOEPCTL12_SNP_LSB                 0x14
-#define GC_USB_DOEPCTL12_SNP_MASK                0x100000
-#define GC_USB_DOEPCTL12_SNP_SIZE                0x1
-#define GC_USB_DOEPCTL12_SNP_DEFAULT             0x0
-#define GC_USB_DOEPCTL12_SNP_OFFSET              0xc80
-#define GC_USB_DOEPCTL12_STALL_LSB               0x15
-#define GC_USB_DOEPCTL12_STALL_MASK              0x200000
-#define GC_USB_DOEPCTL12_STALL_SIZE              0x1
-#define GC_USB_DOEPCTL12_STALL_DEFAULT           0x0
-#define GC_USB_DOEPCTL12_STALL_OFFSET            0xc80
-#define GC_USB_DOEPCTL12_CNAK_LSB                0x1a
-#define GC_USB_DOEPCTL12_CNAK_MASK               0x4000000
-#define GC_USB_DOEPCTL12_CNAK_SIZE               0x1
-#define GC_USB_DOEPCTL12_CNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL12_CNAK_OFFSET             0xc80
-#define GC_USB_DOEPCTL12_SNAK_LSB                0x1b
-#define GC_USB_DOEPCTL12_SNAK_MASK               0x8000000
-#define GC_USB_DOEPCTL12_SNAK_SIZE               0x1
-#define GC_USB_DOEPCTL12_SNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL12_SNAK_OFFSET             0xc80
-#define GC_USB_DOEPCTL12_SETD0PID_LSB            0x1c
-#define GC_USB_DOEPCTL12_SETD0PID_MASK           0x10000000
-#define GC_USB_DOEPCTL12_SETD0PID_SIZE           0x1
-#define GC_USB_DOEPCTL12_SETD0PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL12_SETD0PID_OFFSET         0xc80
-#define GC_USB_DOEPCTL12_SETD1PID_LSB            0x1d
-#define GC_USB_DOEPCTL12_SETD1PID_MASK           0x20000000
-#define GC_USB_DOEPCTL12_SETD1PID_SIZE           0x1
-#define GC_USB_DOEPCTL12_SETD1PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL12_SETD1PID_OFFSET         0xc80
-#define GC_USB_DOEPCTL12_EPDIS_LSB               0x1e
-#define GC_USB_DOEPCTL12_EPDIS_MASK              0x40000000
-#define GC_USB_DOEPCTL12_EPDIS_SIZE              0x1
-#define GC_USB_DOEPCTL12_EPDIS_DEFAULT           0x0
-#define GC_USB_DOEPCTL12_EPDIS_OFFSET            0xc80
-#define GC_USB_DOEPCTL12_EPENA_LSB               0x1f
-#define GC_USB_DOEPCTL12_EPENA_MASK              0x80000000
-#define GC_USB_DOEPCTL12_EPENA_SIZE              0x1
-#define GC_USB_DOEPCTL12_EPENA_DEFAULT           0x0
-#define GC_USB_DOEPCTL12_EPENA_OFFSET            0xc80
-#define GC_USB_DOEPINT12_XFERCOMPL_LSB           0x0
-#define GC_USB_DOEPINT12_XFERCOMPL_MASK          0x1
-#define GC_USB_DOEPINT12_XFERCOMPL_SIZE          0x1
-#define GC_USB_DOEPINT12_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DOEPINT12_XFERCOMPL_OFFSET        0xc88
-#define GC_USB_DOEPINT12_EPDISBLD_LSB            0x1
-#define GC_USB_DOEPINT12_EPDISBLD_MASK           0x2
-#define GC_USB_DOEPINT12_EPDISBLD_SIZE           0x1
-#define GC_USB_DOEPINT12_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DOEPINT12_EPDISBLD_OFFSET         0xc88
-#define GC_USB_DOEPINT12_AHBERR_LSB              0x2
-#define GC_USB_DOEPINT12_AHBERR_MASK             0x4
-#define GC_USB_DOEPINT12_AHBERR_SIZE             0x1
-#define GC_USB_DOEPINT12_AHBERR_DEFAULT          0x0
-#define GC_USB_DOEPINT12_AHBERR_OFFSET           0xc88
-#define GC_USB_DOEPINT12_SETUP_LSB               0x3
-#define GC_USB_DOEPINT12_SETUP_MASK              0x8
-#define GC_USB_DOEPINT12_SETUP_SIZE              0x1
-#define GC_USB_DOEPINT12_SETUP_DEFAULT           0x0
-#define GC_USB_DOEPINT12_SETUP_OFFSET            0xc88
-#define GC_USB_DOEPINT12_OUTTKNEPDIS_LSB         0x4
-#define GC_USB_DOEPINT12_OUTTKNEPDIS_MASK        0x10
-#define GC_USB_DOEPINT12_OUTTKNEPDIS_SIZE        0x1
-#define GC_USB_DOEPINT12_OUTTKNEPDIS_DEFAULT     0x0
-#define GC_USB_DOEPINT12_OUTTKNEPDIS_OFFSET      0xc88
-#define GC_USB_DOEPINT12_STSPHSERCVD_LSB         0x5
-#define GC_USB_DOEPINT12_STSPHSERCVD_MASK        0x20
-#define GC_USB_DOEPINT12_STSPHSERCVD_SIZE        0x1
-#define GC_USB_DOEPINT12_STSPHSERCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT12_STSPHSERCVD_OFFSET      0xc88
-#define GC_USB_DOEPINT12_BACK2BACKSETUP_LSB      0x6
-#define GC_USB_DOEPINT12_BACK2BACKSETUP_MASK     0x40
-#define GC_USB_DOEPINT12_BACK2BACKSETUP_SIZE     0x1
-#define GC_USB_DOEPINT12_BACK2BACKSETUP_DEFAULT  0x0
-#define GC_USB_DOEPINT12_BACK2BACKSETUP_OFFSET   0xc88
-#define GC_USB_DOEPINT12_OUTPKTERR_LSB           0x8
-#define GC_USB_DOEPINT12_OUTPKTERR_MASK          0x100
-#define GC_USB_DOEPINT12_OUTPKTERR_SIZE          0x1
-#define GC_USB_DOEPINT12_OUTPKTERR_DEFAULT       0x0
-#define GC_USB_DOEPINT12_OUTPKTERR_OFFSET        0xc88
-#define GC_USB_DOEPINT12_BNAINTR_LSB             0x9
-#define GC_USB_DOEPINT12_BNAINTR_MASK            0x200
-#define GC_USB_DOEPINT12_BNAINTR_SIZE            0x1
-#define GC_USB_DOEPINT12_BNAINTR_DEFAULT         0x0
-#define GC_USB_DOEPINT12_BNAINTR_OFFSET          0xc88
-#define GC_USB_DOEPINT12_PKTDRPSTS_LSB           0xb
-#define GC_USB_DOEPINT12_PKTDRPSTS_MASK          0x800
-#define GC_USB_DOEPINT12_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DOEPINT12_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DOEPINT12_PKTDRPSTS_OFFSET        0xc88
-#define GC_USB_DOEPINT12_BBLEERR_LSB             0xc
-#define GC_USB_DOEPINT12_BBLEERR_MASK            0x1000
-#define GC_USB_DOEPINT12_BBLEERR_SIZE            0x1
-#define GC_USB_DOEPINT12_BBLEERR_DEFAULT         0x0
-#define GC_USB_DOEPINT12_BBLEERR_OFFSET          0xc88
-#define GC_USB_DOEPINT12_NAKINTRPT_LSB           0xd
-#define GC_USB_DOEPINT12_NAKINTRPT_MASK          0x2000
-#define GC_USB_DOEPINT12_NAKINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT12_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT12_NAKINTRPT_OFFSET        0xc88
-#define GC_USB_DOEPINT12_NYETINTRPT_LSB          0xe
-#define GC_USB_DOEPINT12_NYETINTRPT_MASK         0x4000
-#define GC_USB_DOEPINT12_NYETINTRPT_SIZE         0x1
-#define GC_USB_DOEPINT12_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DOEPINT12_NYETINTRPT_OFFSET       0xc88
-#define GC_USB_DOEPINT12_STUPPKTRCVD_LSB         0xf
-#define GC_USB_DOEPINT12_STUPPKTRCVD_MASK        0x8000
-#define GC_USB_DOEPINT12_STUPPKTRCVD_SIZE        0x1
-#define GC_USB_DOEPINT12_STUPPKTRCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT12_STUPPKTRCVD_OFFSET      0xc88
-#define GC_USB_DOEPTSIZ12_XFERSIZE_LSB           0x0
-#define GC_USB_DOEPTSIZ12_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DOEPTSIZ12_XFERSIZE_SIZE          0x13
-#define GC_USB_DOEPTSIZ12_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DOEPTSIZ12_XFERSIZE_OFFSET        0xc90
-#define GC_USB_DOEPTSIZ12_PKTCNT_LSB             0x13
-#define GC_USB_DOEPTSIZ12_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DOEPTSIZ12_PKTCNT_SIZE            0xa
-#define GC_USB_DOEPTSIZ12_PKTCNT_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ12_PKTCNT_OFFSET          0xc90
-#define GC_USB_DOEPTSIZ12_RXDPID_LSB             0x1d
-#define GC_USB_DOEPTSIZ12_RXDPID_MASK            0x60000000
-#define GC_USB_DOEPTSIZ12_RXDPID_SIZE            0x2
-#define GC_USB_DOEPTSIZ12_RXDPID_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ12_RXDPID_OFFSET          0xc90
-#define GC_USB_DOEPDMA12_DMAADDR_LSB             0x0
-#define GC_USB_DOEPDMA12_DMAADDR_MASK            0xffffffff
-#define GC_USB_DOEPDMA12_DMAADDR_SIZE            0x20
-#define GC_USB_DOEPDMA12_DMAADDR_DEFAULT         0x0
-#define GC_USB_DOEPDMA12_DMAADDR_OFFSET          0xc94
-#define GC_USB_DOEPDMAB12_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DOEPDMAB12_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DOEPDMAB12_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DOEPDMAB12_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DOEPDMAB12_DMABUFFERADDR_OFFSET   0xc9c
-#define GC_USB_DOEPCTL13_MPS_LSB                 0x0
-#define GC_USB_DOEPCTL13_MPS_MASK                0x7ff
-#define GC_USB_DOEPCTL13_MPS_SIZE                0xb
-#define GC_USB_DOEPCTL13_MPS_DEFAULT             0x0
-#define GC_USB_DOEPCTL13_MPS_OFFSET              0xca0
-#define GC_USB_DOEPCTL13_USBACTEP_LSB            0xf
-#define GC_USB_DOEPCTL13_USBACTEP_MASK           0x8000
-#define GC_USB_DOEPCTL13_USBACTEP_SIZE           0x1
-#define GC_USB_DOEPCTL13_USBACTEP_DEFAULT        0x0
-#define GC_USB_DOEPCTL13_USBACTEP_OFFSET         0xca0
-#define GC_USB_DOEPCTL13_DPID_LSB                0x10
-#define GC_USB_DOEPCTL13_DPID_MASK               0x10000
-#define GC_USB_DOEPCTL13_DPID_SIZE               0x1
-#define GC_USB_DOEPCTL13_DPID_DEFAULT            0x0
-#define GC_USB_DOEPCTL13_DPID_OFFSET             0xca0
-#define GC_USB_DOEPCTL13_NAKSTS_LSB              0x11
-#define GC_USB_DOEPCTL13_NAKSTS_MASK             0x20000
-#define GC_USB_DOEPCTL13_NAKSTS_SIZE             0x1
-#define GC_USB_DOEPCTL13_NAKSTS_DEFAULT          0x0
-#define GC_USB_DOEPCTL13_NAKSTS_OFFSET           0xca0
-#define GC_USB_DOEPCTL13_EPTYPE_LSB              0x12
-#define GC_USB_DOEPCTL13_EPTYPE_MASK             0xc0000
-#define GC_USB_DOEPCTL13_EPTYPE_SIZE             0x2
-#define GC_USB_DOEPCTL13_EPTYPE_DEFAULT          0x0
-#define GC_USB_DOEPCTL13_EPTYPE_OFFSET           0xca0
-#define GC_USB_DOEPCTL13_SNP_LSB                 0x14
-#define GC_USB_DOEPCTL13_SNP_MASK                0x100000
-#define GC_USB_DOEPCTL13_SNP_SIZE                0x1
-#define GC_USB_DOEPCTL13_SNP_DEFAULT             0x0
-#define GC_USB_DOEPCTL13_SNP_OFFSET              0xca0
-#define GC_USB_DOEPCTL13_STALL_LSB               0x15
-#define GC_USB_DOEPCTL13_STALL_MASK              0x200000
-#define GC_USB_DOEPCTL13_STALL_SIZE              0x1
-#define GC_USB_DOEPCTL13_STALL_DEFAULT           0x0
-#define GC_USB_DOEPCTL13_STALL_OFFSET            0xca0
-#define GC_USB_DOEPCTL13_CNAK_LSB                0x1a
-#define GC_USB_DOEPCTL13_CNAK_MASK               0x4000000
-#define GC_USB_DOEPCTL13_CNAK_SIZE               0x1
-#define GC_USB_DOEPCTL13_CNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL13_CNAK_OFFSET             0xca0
-#define GC_USB_DOEPCTL13_SNAK_LSB                0x1b
-#define GC_USB_DOEPCTL13_SNAK_MASK               0x8000000
-#define GC_USB_DOEPCTL13_SNAK_SIZE               0x1
-#define GC_USB_DOEPCTL13_SNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL13_SNAK_OFFSET             0xca0
-#define GC_USB_DOEPCTL13_SETD0PID_LSB            0x1c
-#define GC_USB_DOEPCTL13_SETD0PID_MASK           0x10000000
-#define GC_USB_DOEPCTL13_SETD0PID_SIZE           0x1
-#define GC_USB_DOEPCTL13_SETD0PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL13_SETD0PID_OFFSET         0xca0
-#define GC_USB_DOEPCTL13_SETD1PID_LSB            0x1d
-#define GC_USB_DOEPCTL13_SETD1PID_MASK           0x20000000
-#define GC_USB_DOEPCTL13_SETD1PID_SIZE           0x1
-#define GC_USB_DOEPCTL13_SETD1PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL13_SETD1PID_OFFSET         0xca0
-#define GC_USB_DOEPCTL13_EPDIS_LSB               0x1e
-#define GC_USB_DOEPCTL13_EPDIS_MASK              0x40000000
-#define GC_USB_DOEPCTL13_EPDIS_SIZE              0x1
-#define GC_USB_DOEPCTL13_EPDIS_DEFAULT           0x0
-#define GC_USB_DOEPCTL13_EPDIS_OFFSET            0xca0
-#define GC_USB_DOEPCTL13_EPENA_LSB               0x1f
-#define GC_USB_DOEPCTL13_EPENA_MASK              0x80000000
-#define GC_USB_DOEPCTL13_EPENA_SIZE              0x1
-#define GC_USB_DOEPCTL13_EPENA_DEFAULT           0x0
-#define GC_USB_DOEPCTL13_EPENA_OFFSET            0xca0
-#define GC_USB_DOEPINT13_XFERCOMPL_LSB           0x0
-#define GC_USB_DOEPINT13_XFERCOMPL_MASK          0x1
-#define GC_USB_DOEPINT13_XFERCOMPL_SIZE          0x1
-#define GC_USB_DOEPINT13_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DOEPINT13_XFERCOMPL_OFFSET        0xca8
-#define GC_USB_DOEPINT13_EPDISBLD_LSB            0x1
-#define GC_USB_DOEPINT13_EPDISBLD_MASK           0x2
-#define GC_USB_DOEPINT13_EPDISBLD_SIZE           0x1
-#define GC_USB_DOEPINT13_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DOEPINT13_EPDISBLD_OFFSET         0xca8
-#define GC_USB_DOEPINT13_AHBERR_LSB              0x2
-#define GC_USB_DOEPINT13_AHBERR_MASK             0x4
-#define GC_USB_DOEPINT13_AHBERR_SIZE             0x1
-#define GC_USB_DOEPINT13_AHBERR_DEFAULT          0x0
-#define GC_USB_DOEPINT13_AHBERR_OFFSET           0xca8
-#define GC_USB_DOEPINT13_SETUP_LSB               0x3
-#define GC_USB_DOEPINT13_SETUP_MASK              0x8
-#define GC_USB_DOEPINT13_SETUP_SIZE              0x1
-#define GC_USB_DOEPINT13_SETUP_DEFAULT           0x0
-#define GC_USB_DOEPINT13_SETUP_OFFSET            0xca8
-#define GC_USB_DOEPINT13_OUTTKNEPDIS_LSB         0x4
-#define GC_USB_DOEPINT13_OUTTKNEPDIS_MASK        0x10
-#define GC_USB_DOEPINT13_OUTTKNEPDIS_SIZE        0x1
-#define GC_USB_DOEPINT13_OUTTKNEPDIS_DEFAULT     0x0
-#define GC_USB_DOEPINT13_OUTTKNEPDIS_OFFSET      0xca8
-#define GC_USB_DOEPINT13_STSPHSERCVD_LSB         0x5
-#define GC_USB_DOEPINT13_STSPHSERCVD_MASK        0x20
-#define GC_USB_DOEPINT13_STSPHSERCVD_SIZE        0x1
-#define GC_USB_DOEPINT13_STSPHSERCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT13_STSPHSERCVD_OFFSET      0xca8
-#define GC_USB_DOEPINT13_BACK2BACKSETUP_LSB      0x6
-#define GC_USB_DOEPINT13_BACK2BACKSETUP_MASK     0x40
-#define GC_USB_DOEPINT13_BACK2BACKSETUP_SIZE     0x1
-#define GC_USB_DOEPINT13_BACK2BACKSETUP_DEFAULT  0x0
-#define GC_USB_DOEPINT13_BACK2BACKSETUP_OFFSET   0xca8
-#define GC_USB_DOEPINT13_OUTPKTERR_LSB           0x8
-#define GC_USB_DOEPINT13_OUTPKTERR_MASK          0x100
-#define GC_USB_DOEPINT13_OUTPKTERR_SIZE          0x1
-#define GC_USB_DOEPINT13_OUTPKTERR_DEFAULT       0x0
-#define GC_USB_DOEPINT13_OUTPKTERR_OFFSET        0xca8
-#define GC_USB_DOEPINT13_BNAINTR_LSB             0x9
-#define GC_USB_DOEPINT13_BNAINTR_MASK            0x200
-#define GC_USB_DOEPINT13_BNAINTR_SIZE            0x1
-#define GC_USB_DOEPINT13_BNAINTR_DEFAULT         0x0
-#define GC_USB_DOEPINT13_BNAINTR_OFFSET          0xca8
-#define GC_USB_DOEPINT13_PKTDRPSTS_LSB           0xb
-#define GC_USB_DOEPINT13_PKTDRPSTS_MASK          0x800
-#define GC_USB_DOEPINT13_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DOEPINT13_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DOEPINT13_PKTDRPSTS_OFFSET        0xca8
-#define GC_USB_DOEPINT13_BBLEERR_LSB             0xc
-#define GC_USB_DOEPINT13_BBLEERR_MASK            0x1000
-#define GC_USB_DOEPINT13_BBLEERR_SIZE            0x1
-#define GC_USB_DOEPINT13_BBLEERR_DEFAULT         0x0
-#define GC_USB_DOEPINT13_BBLEERR_OFFSET          0xca8
-#define GC_USB_DOEPINT13_NAKINTRPT_LSB           0xd
-#define GC_USB_DOEPINT13_NAKINTRPT_MASK          0x2000
-#define GC_USB_DOEPINT13_NAKINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT13_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT13_NAKINTRPT_OFFSET        0xca8
-#define GC_USB_DOEPINT13_NYETINTRPT_LSB          0xe
-#define GC_USB_DOEPINT13_NYETINTRPT_MASK         0x4000
-#define GC_USB_DOEPINT13_NYETINTRPT_SIZE         0x1
-#define GC_USB_DOEPINT13_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DOEPINT13_NYETINTRPT_OFFSET       0xca8
-#define GC_USB_DOEPINT13_STUPPKTRCVD_LSB         0xf
-#define GC_USB_DOEPINT13_STUPPKTRCVD_MASK        0x8000
-#define GC_USB_DOEPINT13_STUPPKTRCVD_SIZE        0x1
-#define GC_USB_DOEPINT13_STUPPKTRCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT13_STUPPKTRCVD_OFFSET      0xca8
-#define GC_USB_DOEPTSIZ13_XFERSIZE_LSB           0x0
-#define GC_USB_DOEPTSIZ13_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DOEPTSIZ13_XFERSIZE_SIZE          0x13
-#define GC_USB_DOEPTSIZ13_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DOEPTSIZ13_XFERSIZE_OFFSET        0xcb0
-#define GC_USB_DOEPTSIZ13_PKTCNT_LSB             0x13
-#define GC_USB_DOEPTSIZ13_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DOEPTSIZ13_PKTCNT_SIZE            0xa
-#define GC_USB_DOEPTSIZ13_PKTCNT_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ13_PKTCNT_OFFSET          0xcb0
-#define GC_USB_DOEPTSIZ13_RXDPID_LSB             0x1d
-#define GC_USB_DOEPTSIZ13_RXDPID_MASK            0x60000000
-#define GC_USB_DOEPTSIZ13_RXDPID_SIZE            0x2
-#define GC_USB_DOEPTSIZ13_RXDPID_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ13_RXDPID_OFFSET          0xcb0
-#define GC_USB_DOEPDMA13_DMAADDR_LSB             0x0
-#define GC_USB_DOEPDMA13_DMAADDR_MASK            0xffffffff
-#define GC_USB_DOEPDMA13_DMAADDR_SIZE            0x20
-#define GC_USB_DOEPDMA13_DMAADDR_DEFAULT         0x0
-#define GC_USB_DOEPDMA13_DMAADDR_OFFSET          0xcb4
-#define GC_USB_DOEPDMAB13_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DOEPDMAB13_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DOEPDMAB13_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DOEPDMAB13_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DOEPDMAB13_DMABUFFERADDR_OFFSET   0xcbc
-#define GC_USB_DOEPCTL14_MPS_LSB                 0x0
-#define GC_USB_DOEPCTL14_MPS_MASK                0x7ff
-#define GC_USB_DOEPCTL14_MPS_SIZE                0xb
-#define GC_USB_DOEPCTL14_MPS_DEFAULT             0x0
-#define GC_USB_DOEPCTL14_MPS_OFFSET              0xcc0
-#define GC_USB_DOEPCTL14_USBACTEP_LSB            0xf
-#define GC_USB_DOEPCTL14_USBACTEP_MASK           0x8000
-#define GC_USB_DOEPCTL14_USBACTEP_SIZE           0x1
-#define GC_USB_DOEPCTL14_USBACTEP_DEFAULT        0x0
-#define GC_USB_DOEPCTL14_USBACTEP_OFFSET         0xcc0
-#define GC_USB_DOEPCTL14_DPID_LSB                0x10
-#define GC_USB_DOEPCTL14_DPID_MASK               0x10000
-#define GC_USB_DOEPCTL14_DPID_SIZE               0x1
-#define GC_USB_DOEPCTL14_DPID_DEFAULT            0x0
-#define GC_USB_DOEPCTL14_DPID_OFFSET             0xcc0
-#define GC_USB_DOEPCTL14_NAKSTS_LSB              0x11
-#define GC_USB_DOEPCTL14_NAKSTS_MASK             0x20000
-#define GC_USB_DOEPCTL14_NAKSTS_SIZE             0x1
-#define GC_USB_DOEPCTL14_NAKSTS_DEFAULT          0x0
-#define GC_USB_DOEPCTL14_NAKSTS_OFFSET           0xcc0
-#define GC_USB_DOEPCTL14_EPTYPE_LSB              0x12
-#define GC_USB_DOEPCTL14_EPTYPE_MASK             0xc0000
-#define GC_USB_DOEPCTL14_EPTYPE_SIZE             0x2
-#define GC_USB_DOEPCTL14_EPTYPE_DEFAULT          0x0
-#define GC_USB_DOEPCTL14_EPTYPE_OFFSET           0xcc0
-#define GC_USB_DOEPCTL14_SNP_LSB                 0x14
-#define GC_USB_DOEPCTL14_SNP_MASK                0x100000
-#define GC_USB_DOEPCTL14_SNP_SIZE                0x1
-#define GC_USB_DOEPCTL14_SNP_DEFAULT             0x0
-#define GC_USB_DOEPCTL14_SNP_OFFSET              0xcc0
-#define GC_USB_DOEPCTL14_STALL_LSB               0x15
-#define GC_USB_DOEPCTL14_STALL_MASK              0x200000
-#define GC_USB_DOEPCTL14_STALL_SIZE              0x1
-#define GC_USB_DOEPCTL14_STALL_DEFAULT           0x0
-#define GC_USB_DOEPCTL14_STALL_OFFSET            0xcc0
-#define GC_USB_DOEPCTL14_CNAK_LSB                0x1a
-#define GC_USB_DOEPCTL14_CNAK_MASK               0x4000000
-#define GC_USB_DOEPCTL14_CNAK_SIZE               0x1
-#define GC_USB_DOEPCTL14_CNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL14_CNAK_OFFSET             0xcc0
-#define GC_USB_DOEPCTL14_SNAK_LSB                0x1b
-#define GC_USB_DOEPCTL14_SNAK_MASK               0x8000000
-#define GC_USB_DOEPCTL14_SNAK_SIZE               0x1
-#define GC_USB_DOEPCTL14_SNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL14_SNAK_OFFSET             0xcc0
-#define GC_USB_DOEPCTL14_SETD0PID_LSB            0x1c
-#define GC_USB_DOEPCTL14_SETD0PID_MASK           0x10000000
-#define GC_USB_DOEPCTL14_SETD0PID_SIZE           0x1
-#define GC_USB_DOEPCTL14_SETD0PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL14_SETD0PID_OFFSET         0xcc0
-#define GC_USB_DOEPCTL14_SETD1PID_LSB            0x1d
-#define GC_USB_DOEPCTL14_SETD1PID_MASK           0x20000000
-#define GC_USB_DOEPCTL14_SETD1PID_SIZE           0x1
-#define GC_USB_DOEPCTL14_SETD1PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL14_SETD1PID_OFFSET         0xcc0
-#define GC_USB_DOEPCTL14_EPDIS_LSB               0x1e
-#define GC_USB_DOEPCTL14_EPDIS_MASK              0x40000000
-#define GC_USB_DOEPCTL14_EPDIS_SIZE              0x1
-#define GC_USB_DOEPCTL14_EPDIS_DEFAULT           0x0
-#define GC_USB_DOEPCTL14_EPDIS_OFFSET            0xcc0
-#define GC_USB_DOEPCTL14_EPENA_LSB               0x1f
-#define GC_USB_DOEPCTL14_EPENA_MASK              0x80000000
-#define GC_USB_DOEPCTL14_EPENA_SIZE              0x1
-#define GC_USB_DOEPCTL14_EPENA_DEFAULT           0x0
-#define GC_USB_DOEPCTL14_EPENA_OFFSET            0xcc0
-#define GC_USB_DOEPINT14_XFERCOMPL_LSB           0x0
-#define GC_USB_DOEPINT14_XFERCOMPL_MASK          0x1
-#define GC_USB_DOEPINT14_XFERCOMPL_SIZE          0x1
-#define GC_USB_DOEPINT14_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DOEPINT14_XFERCOMPL_OFFSET        0xcc8
-#define GC_USB_DOEPINT14_EPDISBLD_LSB            0x1
-#define GC_USB_DOEPINT14_EPDISBLD_MASK           0x2
-#define GC_USB_DOEPINT14_EPDISBLD_SIZE           0x1
-#define GC_USB_DOEPINT14_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DOEPINT14_EPDISBLD_OFFSET         0xcc8
-#define GC_USB_DOEPINT14_AHBERR_LSB              0x2
-#define GC_USB_DOEPINT14_AHBERR_MASK             0x4
-#define GC_USB_DOEPINT14_AHBERR_SIZE             0x1
-#define GC_USB_DOEPINT14_AHBERR_DEFAULT          0x0
-#define GC_USB_DOEPINT14_AHBERR_OFFSET           0xcc8
-#define GC_USB_DOEPINT14_SETUP_LSB               0x3
-#define GC_USB_DOEPINT14_SETUP_MASK              0x8
-#define GC_USB_DOEPINT14_SETUP_SIZE              0x1
-#define GC_USB_DOEPINT14_SETUP_DEFAULT           0x0
-#define GC_USB_DOEPINT14_SETUP_OFFSET            0xcc8
-#define GC_USB_DOEPINT14_OUTTKNEPDIS_LSB         0x4
-#define GC_USB_DOEPINT14_OUTTKNEPDIS_MASK        0x10
-#define GC_USB_DOEPINT14_OUTTKNEPDIS_SIZE        0x1
-#define GC_USB_DOEPINT14_OUTTKNEPDIS_DEFAULT     0x0
-#define GC_USB_DOEPINT14_OUTTKNEPDIS_OFFSET      0xcc8
-#define GC_USB_DOEPINT14_STSPHSERCVD_LSB         0x5
-#define GC_USB_DOEPINT14_STSPHSERCVD_MASK        0x20
-#define GC_USB_DOEPINT14_STSPHSERCVD_SIZE        0x1
-#define GC_USB_DOEPINT14_STSPHSERCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT14_STSPHSERCVD_OFFSET      0xcc8
-#define GC_USB_DOEPINT14_BACK2BACKSETUP_LSB      0x6
-#define GC_USB_DOEPINT14_BACK2BACKSETUP_MASK     0x40
-#define GC_USB_DOEPINT14_BACK2BACKSETUP_SIZE     0x1
-#define GC_USB_DOEPINT14_BACK2BACKSETUP_DEFAULT  0x0
-#define GC_USB_DOEPINT14_BACK2BACKSETUP_OFFSET   0xcc8
-#define GC_USB_DOEPINT14_OUTPKTERR_LSB           0x8
-#define GC_USB_DOEPINT14_OUTPKTERR_MASK          0x100
-#define GC_USB_DOEPINT14_OUTPKTERR_SIZE          0x1
-#define GC_USB_DOEPINT14_OUTPKTERR_DEFAULT       0x0
-#define GC_USB_DOEPINT14_OUTPKTERR_OFFSET        0xcc8
-#define GC_USB_DOEPINT14_BNAINTR_LSB             0x9
-#define GC_USB_DOEPINT14_BNAINTR_MASK            0x200
-#define GC_USB_DOEPINT14_BNAINTR_SIZE            0x1
-#define GC_USB_DOEPINT14_BNAINTR_DEFAULT         0x0
-#define GC_USB_DOEPINT14_BNAINTR_OFFSET          0xcc8
-#define GC_USB_DOEPINT14_PKTDRPSTS_LSB           0xb
-#define GC_USB_DOEPINT14_PKTDRPSTS_MASK          0x800
-#define GC_USB_DOEPINT14_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DOEPINT14_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DOEPINT14_PKTDRPSTS_OFFSET        0xcc8
-#define GC_USB_DOEPINT14_BBLEERR_LSB             0xc
-#define GC_USB_DOEPINT14_BBLEERR_MASK            0x1000
-#define GC_USB_DOEPINT14_BBLEERR_SIZE            0x1
-#define GC_USB_DOEPINT14_BBLEERR_DEFAULT         0x0
-#define GC_USB_DOEPINT14_BBLEERR_OFFSET          0xcc8
-#define GC_USB_DOEPINT14_NAKINTRPT_LSB           0xd
-#define GC_USB_DOEPINT14_NAKINTRPT_MASK          0x2000
-#define GC_USB_DOEPINT14_NAKINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT14_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT14_NAKINTRPT_OFFSET        0xcc8
-#define GC_USB_DOEPINT14_NYETINTRPT_LSB          0xe
-#define GC_USB_DOEPINT14_NYETINTRPT_MASK         0x4000
-#define GC_USB_DOEPINT14_NYETINTRPT_SIZE         0x1
-#define GC_USB_DOEPINT14_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DOEPINT14_NYETINTRPT_OFFSET       0xcc8
-#define GC_USB_DOEPINT14_STUPPKTRCVD_LSB         0xf
-#define GC_USB_DOEPINT14_STUPPKTRCVD_MASK        0x8000
-#define GC_USB_DOEPINT14_STUPPKTRCVD_SIZE        0x1
-#define GC_USB_DOEPINT14_STUPPKTRCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT14_STUPPKTRCVD_OFFSET      0xcc8
-#define GC_USB_DOEPTSIZ14_XFERSIZE_LSB           0x0
-#define GC_USB_DOEPTSIZ14_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DOEPTSIZ14_XFERSIZE_SIZE          0x13
-#define GC_USB_DOEPTSIZ14_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DOEPTSIZ14_XFERSIZE_OFFSET        0xcd0
-#define GC_USB_DOEPTSIZ14_PKTCNT_LSB             0x13
-#define GC_USB_DOEPTSIZ14_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DOEPTSIZ14_PKTCNT_SIZE            0xa
-#define GC_USB_DOEPTSIZ14_PKTCNT_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ14_PKTCNT_OFFSET          0xcd0
-#define GC_USB_DOEPTSIZ14_RXDPID_LSB             0x1d
-#define GC_USB_DOEPTSIZ14_RXDPID_MASK            0x60000000
-#define GC_USB_DOEPTSIZ14_RXDPID_SIZE            0x2
-#define GC_USB_DOEPTSIZ14_RXDPID_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ14_RXDPID_OFFSET          0xcd0
-#define GC_USB_DOEPDMA14_DMAADDR_LSB             0x0
-#define GC_USB_DOEPDMA14_DMAADDR_MASK            0xffffffff
-#define GC_USB_DOEPDMA14_DMAADDR_SIZE            0x20
-#define GC_USB_DOEPDMA14_DMAADDR_DEFAULT         0x0
-#define GC_USB_DOEPDMA14_DMAADDR_OFFSET          0xcd4
-#define GC_USB_DOEPDMAB14_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DOEPDMAB14_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DOEPDMAB14_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DOEPDMAB14_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DOEPDMAB14_DMABUFFERADDR_OFFSET   0xcdc
-#define GC_USB_DOEPCTL15_MPS_LSB                 0x0
-#define GC_USB_DOEPCTL15_MPS_MASK                0x7ff
-#define GC_USB_DOEPCTL15_MPS_SIZE                0xb
-#define GC_USB_DOEPCTL15_MPS_DEFAULT             0x0
-#define GC_USB_DOEPCTL15_MPS_OFFSET              0xce0
-#define GC_USB_DOEPCTL15_USBACTEP_LSB            0xf
-#define GC_USB_DOEPCTL15_USBACTEP_MASK           0x8000
-#define GC_USB_DOEPCTL15_USBACTEP_SIZE           0x1
-#define GC_USB_DOEPCTL15_USBACTEP_DEFAULT        0x0
-#define GC_USB_DOEPCTL15_USBACTEP_OFFSET         0xce0
-#define GC_USB_DOEPCTL15_DPID_LSB                0x10
-#define GC_USB_DOEPCTL15_DPID_MASK               0x10000
-#define GC_USB_DOEPCTL15_DPID_SIZE               0x1
-#define GC_USB_DOEPCTL15_DPID_DEFAULT            0x0
-#define GC_USB_DOEPCTL15_DPID_OFFSET             0xce0
-#define GC_USB_DOEPCTL15_NAKSTS_LSB              0x11
-#define GC_USB_DOEPCTL15_NAKSTS_MASK             0x20000
-#define GC_USB_DOEPCTL15_NAKSTS_SIZE             0x1
-#define GC_USB_DOEPCTL15_NAKSTS_DEFAULT          0x0
-#define GC_USB_DOEPCTL15_NAKSTS_OFFSET           0xce0
-#define GC_USB_DOEPCTL15_EPTYPE_LSB              0x12
-#define GC_USB_DOEPCTL15_EPTYPE_MASK             0xc0000
-#define GC_USB_DOEPCTL15_EPTYPE_SIZE             0x2
-#define GC_USB_DOEPCTL15_EPTYPE_DEFAULT          0x0
-#define GC_USB_DOEPCTL15_EPTYPE_OFFSET           0xce0
-#define GC_USB_DOEPCTL15_SNP_LSB                 0x14
-#define GC_USB_DOEPCTL15_SNP_MASK                0x100000
-#define GC_USB_DOEPCTL15_SNP_SIZE                0x1
-#define GC_USB_DOEPCTL15_SNP_DEFAULT             0x0
-#define GC_USB_DOEPCTL15_SNP_OFFSET              0xce0
-#define GC_USB_DOEPCTL15_STALL_LSB               0x15
-#define GC_USB_DOEPCTL15_STALL_MASK              0x200000
-#define GC_USB_DOEPCTL15_STALL_SIZE              0x1
-#define GC_USB_DOEPCTL15_STALL_DEFAULT           0x0
-#define GC_USB_DOEPCTL15_STALL_OFFSET            0xce0
-#define GC_USB_DOEPCTL15_CNAK_LSB                0x1a
-#define GC_USB_DOEPCTL15_CNAK_MASK               0x4000000
-#define GC_USB_DOEPCTL15_CNAK_SIZE               0x1
-#define GC_USB_DOEPCTL15_CNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL15_CNAK_OFFSET             0xce0
-#define GC_USB_DOEPCTL15_SNAK_LSB                0x1b
-#define GC_USB_DOEPCTL15_SNAK_MASK               0x8000000
-#define GC_USB_DOEPCTL15_SNAK_SIZE               0x1
-#define GC_USB_DOEPCTL15_SNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL15_SNAK_OFFSET             0xce0
-#define GC_USB_DOEPCTL15_SETD0PID_LSB            0x1c
-#define GC_USB_DOEPCTL15_SETD0PID_MASK           0x10000000
-#define GC_USB_DOEPCTL15_SETD0PID_SIZE           0x1
-#define GC_USB_DOEPCTL15_SETD0PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL15_SETD0PID_OFFSET         0xce0
-#define GC_USB_DOEPCTL15_SETD1PID_LSB            0x1d
-#define GC_USB_DOEPCTL15_SETD1PID_MASK           0x20000000
-#define GC_USB_DOEPCTL15_SETD1PID_SIZE           0x1
-#define GC_USB_DOEPCTL15_SETD1PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL15_SETD1PID_OFFSET         0xce0
-#define GC_USB_DOEPCTL15_EPDIS_LSB               0x1e
-#define GC_USB_DOEPCTL15_EPDIS_MASK              0x40000000
-#define GC_USB_DOEPCTL15_EPDIS_SIZE              0x1
-#define GC_USB_DOEPCTL15_EPDIS_DEFAULT           0x0
-#define GC_USB_DOEPCTL15_EPDIS_OFFSET            0xce0
-#define GC_USB_DOEPCTL15_EPENA_LSB               0x1f
-#define GC_USB_DOEPCTL15_EPENA_MASK              0x80000000
-#define GC_USB_DOEPCTL15_EPENA_SIZE              0x1
-#define GC_USB_DOEPCTL15_EPENA_DEFAULT           0x0
-#define GC_USB_DOEPCTL15_EPENA_OFFSET            0xce0
-#define GC_USB_DOEPINT15_XFERCOMPL_LSB           0x0
-#define GC_USB_DOEPINT15_XFERCOMPL_MASK          0x1
-#define GC_USB_DOEPINT15_XFERCOMPL_SIZE          0x1
-#define GC_USB_DOEPINT15_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DOEPINT15_XFERCOMPL_OFFSET        0xce8
-#define GC_USB_DOEPINT15_EPDISBLD_LSB            0x1
-#define GC_USB_DOEPINT15_EPDISBLD_MASK           0x2
-#define GC_USB_DOEPINT15_EPDISBLD_SIZE           0x1
-#define GC_USB_DOEPINT15_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DOEPINT15_EPDISBLD_OFFSET         0xce8
-#define GC_USB_DOEPINT15_AHBERR_LSB              0x2
-#define GC_USB_DOEPINT15_AHBERR_MASK             0x4
-#define GC_USB_DOEPINT15_AHBERR_SIZE             0x1
-#define GC_USB_DOEPINT15_AHBERR_DEFAULT          0x0
-#define GC_USB_DOEPINT15_AHBERR_OFFSET           0xce8
-#define GC_USB_DOEPINT15_SETUP_LSB               0x3
-#define GC_USB_DOEPINT15_SETUP_MASK              0x8
-#define GC_USB_DOEPINT15_SETUP_SIZE              0x1
-#define GC_USB_DOEPINT15_SETUP_DEFAULT           0x0
-#define GC_USB_DOEPINT15_SETUP_OFFSET            0xce8
-#define GC_USB_DOEPINT15_OUTTKNEPDIS_LSB         0x4
-#define GC_USB_DOEPINT15_OUTTKNEPDIS_MASK        0x10
-#define GC_USB_DOEPINT15_OUTTKNEPDIS_SIZE        0x1
-#define GC_USB_DOEPINT15_OUTTKNEPDIS_DEFAULT     0x0
-#define GC_USB_DOEPINT15_OUTTKNEPDIS_OFFSET      0xce8
-#define GC_USB_DOEPINT15_STSPHSERCVD_LSB         0x5
-#define GC_USB_DOEPINT15_STSPHSERCVD_MASK        0x20
-#define GC_USB_DOEPINT15_STSPHSERCVD_SIZE        0x1
-#define GC_USB_DOEPINT15_STSPHSERCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT15_STSPHSERCVD_OFFSET      0xce8
-#define GC_USB_DOEPINT15_BACK2BACKSETUP_LSB      0x6
-#define GC_USB_DOEPINT15_BACK2BACKSETUP_MASK     0x40
-#define GC_USB_DOEPINT15_BACK2BACKSETUP_SIZE     0x1
-#define GC_USB_DOEPINT15_BACK2BACKSETUP_DEFAULT  0x0
-#define GC_USB_DOEPINT15_BACK2BACKSETUP_OFFSET   0xce8
-#define GC_USB_DOEPINT15_OUTPKTERR_LSB           0x8
-#define GC_USB_DOEPINT15_OUTPKTERR_MASK          0x100
-#define GC_USB_DOEPINT15_OUTPKTERR_SIZE          0x1
-#define GC_USB_DOEPINT15_OUTPKTERR_DEFAULT       0x0
-#define GC_USB_DOEPINT15_OUTPKTERR_OFFSET        0xce8
-#define GC_USB_DOEPINT15_BNAINTR_LSB             0x9
-#define GC_USB_DOEPINT15_BNAINTR_MASK            0x200
-#define GC_USB_DOEPINT15_BNAINTR_SIZE            0x1
-#define GC_USB_DOEPINT15_BNAINTR_DEFAULT         0x0
-#define GC_USB_DOEPINT15_BNAINTR_OFFSET          0xce8
-#define GC_USB_DOEPINT15_PKTDRPSTS_LSB           0xb
-#define GC_USB_DOEPINT15_PKTDRPSTS_MASK          0x800
-#define GC_USB_DOEPINT15_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DOEPINT15_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DOEPINT15_PKTDRPSTS_OFFSET        0xce8
-#define GC_USB_DOEPINT15_BBLEERR_LSB             0xc
-#define GC_USB_DOEPINT15_BBLEERR_MASK            0x1000
-#define GC_USB_DOEPINT15_BBLEERR_SIZE            0x1
-#define GC_USB_DOEPINT15_BBLEERR_DEFAULT         0x0
-#define GC_USB_DOEPINT15_BBLEERR_OFFSET          0xce8
-#define GC_USB_DOEPINT15_NAKINTRPT_LSB           0xd
-#define GC_USB_DOEPINT15_NAKINTRPT_MASK          0x2000
-#define GC_USB_DOEPINT15_NAKINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT15_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT15_NAKINTRPT_OFFSET        0xce8
-#define GC_USB_DOEPINT15_NYETINTRPT_LSB          0xe
-#define GC_USB_DOEPINT15_NYETINTRPT_MASK         0x4000
-#define GC_USB_DOEPINT15_NYETINTRPT_SIZE         0x1
-#define GC_USB_DOEPINT15_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DOEPINT15_NYETINTRPT_OFFSET       0xce8
-#define GC_USB_DOEPINT15_STUPPKTRCVD_LSB         0xf
-#define GC_USB_DOEPINT15_STUPPKTRCVD_MASK        0x8000
-#define GC_USB_DOEPINT15_STUPPKTRCVD_SIZE        0x1
-#define GC_USB_DOEPINT15_STUPPKTRCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT15_STUPPKTRCVD_OFFSET      0xce8
-#define GC_USB_DOEPTSIZ15_XFERSIZE_LSB           0x0
-#define GC_USB_DOEPTSIZ15_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DOEPTSIZ15_XFERSIZE_SIZE          0x13
-#define GC_USB_DOEPTSIZ15_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DOEPTSIZ15_XFERSIZE_OFFSET        0xcf0
-#define GC_USB_DOEPTSIZ15_PKTCNT_LSB             0x13
-#define GC_USB_DOEPTSIZ15_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DOEPTSIZ15_PKTCNT_SIZE            0xa
-#define GC_USB_DOEPTSIZ15_PKTCNT_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ15_PKTCNT_OFFSET          0xcf0
-#define GC_USB_DOEPTSIZ15_RXDPID_LSB             0x1d
-#define GC_USB_DOEPTSIZ15_RXDPID_MASK            0x60000000
-#define GC_USB_DOEPTSIZ15_RXDPID_SIZE            0x2
-#define GC_USB_DOEPTSIZ15_RXDPID_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ15_RXDPID_OFFSET          0xcf0
-#define GC_USB_DOEPDMA15_DMAADDR_LSB             0x0
-#define GC_USB_DOEPDMA15_DMAADDR_MASK            0xffffffff
-#define GC_USB_DOEPDMA15_DMAADDR_SIZE            0x20
-#define GC_USB_DOEPDMA15_DMAADDR_DEFAULT         0x0
-#define GC_USB_DOEPDMA15_DMAADDR_OFFSET          0xcf4
-#define GC_USB_DOEPDMAB15_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DOEPDMAB15_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DOEPDMAB15_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DOEPDMAB15_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DOEPDMAB15_DMABUFFERADDR_OFFSET   0xcfc
-#define GC_USB_PCGCCTL_STOPPCLK_LSB              0x0
-#define GC_USB_PCGCCTL_STOPPCLK_MASK             0x1
-#define GC_USB_PCGCCTL_STOPPCLK_SIZE             0x1
-#define GC_USB_PCGCCTL_STOPPCLK_DEFAULT          0x0
-#define GC_USB_PCGCCTL_STOPPCLK_OFFSET           0xe00
-#define GC_USB_PCGCCTL_GATEHCLK_LSB              0x1
-#define GC_USB_PCGCCTL_GATEHCLK_MASK             0x2
-#define GC_USB_PCGCCTL_GATEHCLK_SIZE             0x1
-#define GC_USB_PCGCCTL_GATEHCLK_DEFAULT          0x0
-#define GC_USB_PCGCCTL_GATEHCLK_OFFSET           0xe00
-#define GC_USB_PCGCCTL_PWRCLMP_LSB               0x2
-#define GC_USB_PCGCCTL_PWRCLMP_MASK              0x4
-#define GC_USB_PCGCCTL_PWRCLMP_SIZE              0x1
-#define GC_USB_PCGCCTL_PWRCLMP_DEFAULT           0x0
-#define GC_USB_PCGCCTL_PWRCLMP_OFFSET            0xe00
-#define GC_USB_PCGCCTL_RSTPDWNMODULE_LSB         0x3
-#define GC_USB_PCGCCTL_RSTPDWNMODULE_MASK        0x8
-#define GC_USB_PCGCCTL_RSTPDWNMODULE_SIZE        0x1
-#define GC_USB_PCGCCTL_RSTPDWNMODULE_DEFAULT     0x0
-#define GC_USB_PCGCCTL_RSTPDWNMODULE_OFFSET      0xe00
-#define GC_USB_PCGCCTL_PHYSLEEP_LSB              0x6
-#define GC_USB_PCGCCTL_PHYSLEEP_MASK             0x40
-#define GC_USB_PCGCCTL_PHYSLEEP_SIZE             0x1
-#define GC_USB_PCGCCTL_PHYSLEEP_DEFAULT          0x0
-#define GC_USB_PCGCCTL_PHYSLEEP_OFFSET           0xe00
-#define GC_USB_PCGCCTL_L1SUSPENDED_LSB           0x7
-#define GC_USB_PCGCCTL_L1SUSPENDED_MASK          0x80
-#define GC_USB_PCGCCTL_L1SUSPENDED_SIZE          0x1
-#define GC_USB_PCGCCTL_L1SUSPENDED_DEFAULT       0x0
-#define GC_USB_PCGCCTL_L1SUSPENDED_OFFSET        0xe00
-#define GC_USB_DFIFO_SIZE                        0x1000
-
+#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_OFFSET 0xaf8
+#define GC_USB_DIEPDMAB15_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DIEPDMAB15_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DIEPDMAB15_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DIEPDMAB15_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DIEPDMAB15_DMABUFFERADDR_OFFSET 0xafc
+#define GC_USB_DOEPCTL0_MPS_LSB 0x0
+#define GC_USB_DOEPCTL0_MPS_MASK 0x3
+#define GC_USB_DOEPCTL0_MPS_SIZE 0x2
+#define GC_USB_DOEPCTL0_MPS_DEFAULT 0x0
+#define GC_USB_DOEPCTL0_MPS_OFFSET 0xb00
+#define GC_USB_DOEPCTL0_USBACTEP_LSB 0xf
+#define GC_USB_DOEPCTL0_USBACTEP_MASK 0x8000
+#define GC_USB_DOEPCTL0_USBACTEP_SIZE 0x1
+#define GC_USB_DOEPCTL0_USBACTEP_DEFAULT 0x0
+#define GC_USB_DOEPCTL0_USBACTEP_OFFSET 0xb00
+#define GC_USB_DOEPCTL0_NAKSTS_LSB 0x11
+#define GC_USB_DOEPCTL0_NAKSTS_MASK 0x20000
+#define GC_USB_DOEPCTL0_NAKSTS_SIZE 0x1
+#define GC_USB_DOEPCTL0_NAKSTS_DEFAULT 0x0
+#define GC_USB_DOEPCTL0_NAKSTS_OFFSET 0xb00
+#define GC_USB_DOEPCTL0_EPTYPE_LSB 0x12
+#define GC_USB_DOEPCTL0_EPTYPE_MASK 0xc0000
+#define GC_USB_DOEPCTL0_EPTYPE_SIZE 0x2
+#define GC_USB_DOEPCTL0_EPTYPE_DEFAULT 0x0
+#define GC_USB_DOEPCTL0_EPTYPE_OFFSET 0xb00
+#define GC_USB_DOEPCTL0_SNP_LSB 0x14
+#define GC_USB_DOEPCTL0_SNP_MASK 0x100000
+#define GC_USB_DOEPCTL0_SNP_SIZE 0x1
+#define GC_USB_DOEPCTL0_SNP_DEFAULT 0x0
+#define GC_USB_DOEPCTL0_SNP_OFFSET 0xb00
+#define GC_USB_DOEPCTL0_STALL_LSB 0x15
+#define GC_USB_DOEPCTL0_STALL_MASK 0x200000
+#define GC_USB_DOEPCTL0_STALL_SIZE 0x1
+#define GC_USB_DOEPCTL0_STALL_DEFAULT 0x0
+#define GC_USB_DOEPCTL0_STALL_OFFSET 0xb00
+#define GC_USB_DOEPCTL0_CNAK_LSB 0x1a
+#define GC_USB_DOEPCTL0_CNAK_MASK 0x4000000
+#define GC_USB_DOEPCTL0_CNAK_SIZE 0x1
+#define GC_USB_DOEPCTL0_CNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL0_CNAK_OFFSET 0xb00
+#define GC_USB_DOEPCTL0_SNAK_LSB 0x1b
+#define GC_USB_DOEPCTL0_SNAK_MASK 0x8000000
+#define GC_USB_DOEPCTL0_SNAK_SIZE 0x1
+#define GC_USB_DOEPCTL0_SNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL0_SNAK_OFFSET 0xb00
+#define GC_USB_DOEPCTL0_EPDIS_LSB 0x1e
+#define GC_USB_DOEPCTL0_EPDIS_MASK 0x40000000
+#define GC_USB_DOEPCTL0_EPDIS_SIZE 0x1
+#define GC_USB_DOEPCTL0_EPDIS_DEFAULT 0x0
+#define GC_USB_DOEPCTL0_EPDIS_OFFSET 0xb00
+#define GC_USB_DOEPCTL0_EPENA_LSB 0x1f
+#define GC_USB_DOEPCTL0_EPENA_MASK 0x80000000
+#define GC_USB_DOEPCTL0_EPENA_SIZE 0x1
+#define GC_USB_DOEPCTL0_EPENA_DEFAULT 0x0
+#define GC_USB_DOEPCTL0_EPENA_OFFSET 0xb00
+#define GC_USB_DOEPINT0_XFERCOMPL_LSB 0x0
+#define GC_USB_DOEPINT0_XFERCOMPL_MASK 0x1
+#define GC_USB_DOEPINT0_XFERCOMPL_SIZE 0x1
+#define GC_USB_DOEPINT0_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DOEPINT0_XFERCOMPL_OFFSET 0xb08
+#define GC_USB_DOEPINT0_EPDISBLD_LSB 0x1
+#define GC_USB_DOEPINT0_EPDISBLD_MASK 0x2
+#define GC_USB_DOEPINT0_EPDISBLD_SIZE 0x1
+#define GC_USB_DOEPINT0_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DOEPINT0_EPDISBLD_OFFSET 0xb08
+#define GC_USB_DOEPINT0_AHBERR_LSB 0x2
+#define GC_USB_DOEPINT0_AHBERR_MASK 0x4
+#define GC_USB_DOEPINT0_AHBERR_SIZE 0x1
+#define GC_USB_DOEPINT0_AHBERR_DEFAULT 0x0
+#define GC_USB_DOEPINT0_AHBERR_OFFSET 0xb08
+#define GC_USB_DOEPINT0_SETUP_LSB 0x3
+#define GC_USB_DOEPINT0_SETUP_MASK 0x8
+#define GC_USB_DOEPINT0_SETUP_SIZE 0x1
+#define GC_USB_DOEPINT0_SETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT0_SETUP_OFFSET 0xb08
+#define GC_USB_DOEPINT0_OUTTKNEPDIS_LSB 0x4
+#define GC_USB_DOEPINT0_OUTTKNEPDIS_MASK 0x10
+#define GC_USB_DOEPINT0_OUTTKNEPDIS_SIZE 0x1
+#define GC_USB_DOEPINT0_OUTTKNEPDIS_DEFAULT 0x0
+#define GC_USB_DOEPINT0_OUTTKNEPDIS_OFFSET 0xb08
+#define GC_USB_DOEPINT0_STSPHSERCVD_LSB 0x5
+#define GC_USB_DOEPINT0_STSPHSERCVD_MASK 0x20
+#define GC_USB_DOEPINT0_STSPHSERCVD_SIZE 0x1
+#define GC_USB_DOEPINT0_STSPHSERCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT0_STSPHSERCVD_OFFSET 0xb08
+#define GC_USB_DOEPINT0_BACK2BACKSETUP_LSB 0x6
+#define GC_USB_DOEPINT0_BACK2BACKSETUP_MASK 0x40
+#define GC_USB_DOEPINT0_BACK2BACKSETUP_SIZE 0x1
+#define GC_USB_DOEPINT0_BACK2BACKSETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT0_BACK2BACKSETUP_OFFSET 0xb08
+#define GC_USB_DOEPINT0_OUTPKTERR_LSB 0x8
+#define GC_USB_DOEPINT0_OUTPKTERR_MASK 0x100
+#define GC_USB_DOEPINT0_OUTPKTERR_SIZE 0x1
+#define GC_USB_DOEPINT0_OUTPKTERR_DEFAULT 0x0
+#define GC_USB_DOEPINT0_OUTPKTERR_OFFSET 0xb08
+#define GC_USB_DOEPINT0_BNAINTR_LSB 0x9
+#define GC_USB_DOEPINT0_BNAINTR_MASK 0x200
+#define GC_USB_DOEPINT0_BNAINTR_SIZE 0x1
+#define GC_USB_DOEPINT0_BNAINTR_DEFAULT 0x0
+#define GC_USB_DOEPINT0_BNAINTR_OFFSET 0xb08
+#define GC_USB_DOEPINT0_PKTDRPSTS_LSB 0xb
+#define GC_USB_DOEPINT0_PKTDRPSTS_MASK 0x800
+#define GC_USB_DOEPINT0_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DOEPINT0_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DOEPINT0_PKTDRPSTS_OFFSET 0xb08
+#define GC_USB_DOEPINT0_BBLEERR_LSB 0xc
+#define GC_USB_DOEPINT0_BBLEERR_MASK 0x1000
+#define GC_USB_DOEPINT0_BBLEERR_SIZE 0x1
+#define GC_USB_DOEPINT0_BBLEERR_DEFAULT 0x0
+#define GC_USB_DOEPINT0_BBLEERR_OFFSET 0xb08
+#define GC_USB_DOEPINT0_NAKINTRPT_LSB 0xd
+#define GC_USB_DOEPINT0_NAKINTRPT_MASK 0x2000
+#define GC_USB_DOEPINT0_NAKINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT0_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT0_NAKINTRPT_OFFSET 0xb08
+#define GC_USB_DOEPINT0_NYETINTRPT_LSB 0xe
+#define GC_USB_DOEPINT0_NYETINTRPT_MASK 0x4000
+#define GC_USB_DOEPINT0_NYETINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT0_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT0_NYETINTRPT_OFFSET 0xb08
+#define GC_USB_DOEPINT0_STUPPKTRCVD_LSB 0xf
+#define GC_USB_DOEPINT0_STUPPKTRCVD_MASK 0x8000
+#define GC_USB_DOEPINT0_STUPPKTRCVD_SIZE 0x1
+#define GC_USB_DOEPINT0_STUPPKTRCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT0_STUPPKTRCVD_OFFSET 0xb08
+#define GC_USB_DOEPTSIZ0_XFERSIZE_LSB 0x0
+#define GC_USB_DOEPTSIZ0_XFERSIZE_MASK 0x7f
+#define GC_USB_DOEPTSIZ0_XFERSIZE_SIZE 0x7
+#define GC_USB_DOEPTSIZ0_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ0_XFERSIZE_OFFSET 0xb10
+#define GC_USB_DOEPTSIZ0_PKTCNT_LSB 0x13
+#define GC_USB_DOEPTSIZ0_PKTCNT_MASK 0x80000
+#define GC_USB_DOEPTSIZ0_PKTCNT_SIZE 0x1
+#define GC_USB_DOEPTSIZ0_PKTCNT_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ0_PKTCNT_OFFSET 0xb10
+#define GC_USB_DOEPTSIZ0_SUPCNT_LSB 0x1d
+#define GC_USB_DOEPTSIZ0_SUPCNT_MASK 0x60000000
+#define GC_USB_DOEPTSIZ0_SUPCNT_SIZE 0x2
+#define GC_USB_DOEPTSIZ0_SUPCNT_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ0_SUPCNT_OFFSET 0xb10
+#define GC_USB_DOEPDMA0_DMAADDR_LSB 0x0
+#define GC_USB_DOEPDMA0_DMAADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMA0_DMAADDR_SIZE 0x20
+#define GC_USB_DOEPDMA0_DMAADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMA0_DMAADDR_OFFSET 0xb14
+#define GC_USB_DOEPDMAB0_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DOEPDMAB0_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMAB0_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DOEPDMAB0_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMAB0_DMABUFFERADDR_OFFSET 0xb1c
+#define GC_USB_DOEPCTL1_MPS_LSB 0x0
+#define GC_USB_DOEPCTL1_MPS_MASK 0x7ff
+#define GC_USB_DOEPCTL1_MPS_SIZE 0xb
+#define GC_USB_DOEPCTL1_MPS_DEFAULT 0x0
+#define GC_USB_DOEPCTL1_MPS_OFFSET 0xb20
+#define GC_USB_DOEPCTL1_USBACTEP_LSB 0xf
+#define GC_USB_DOEPCTL1_USBACTEP_MASK 0x8000
+#define GC_USB_DOEPCTL1_USBACTEP_SIZE 0x1
+#define GC_USB_DOEPCTL1_USBACTEP_DEFAULT 0x0
+#define GC_USB_DOEPCTL1_USBACTEP_OFFSET 0xb20
+#define GC_USB_DOEPCTL1_DPID_LSB 0x10
+#define GC_USB_DOEPCTL1_DPID_MASK 0x10000
+#define GC_USB_DOEPCTL1_DPID_SIZE 0x1
+#define GC_USB_DOEPCTL1_DPID_DEFAULT 0x0
+#define GC_USB_DOEPCTL1_DPID_OFFSET 0xb20
+#define GC_USB_DOEPCTL1_NAKSTS_LSB 0x11
+#define GC_USB_DOEPCTL1_NAKSTS_MASK 0x20000
+#define GC_USB_DOEPCTL1_NAKSTS_SIZE 0x1
+#define GC_USB_DOEPCTL1_NAKSTS_DEFAULT 0x0
+#define GC_USB_DOEPCTL1_NAKSTS_OFFSET 0xb20
+#define GC_USB_DOEPCTL1_EPTYPE_LSB 0x12
+#define GC_USB_DOEPCTL1_EPTYPE_MASK 0xc0000
+#define GC_USB_DOEPCTL1_EPTYPE_SIZE 0x2
+#define GC_USB_DOEPCTL1_EPTYPE_DEFAULT 0x0
+#define GC_USB_DOEPCTL1_EPTYPE_OFFSET 0xb20
+#define GC_USB_DOEPCTL1_SNP_LSB 0x14
+#define GC_USB_DOEPCTL1_SNP_MASK 0x100000
+#define GC_USB_DOEPCTL1_SNP_SIZE 0x1
+#define GC_USB_DOEPCTL1_SNP_DEFAULT 0x0
+#define GC_USB_DOEPCTL1_SNP_OFFSET 0xb20
+#define GC_USB_DOEPCTL1_STALL_LSB 0x15
+#define GC_USB_DOEPCTL1_STALL_MASK 0x200000
+#define GC_USB_DOEPCTL1_STALL_SIZE 0x1
+#define GC_USB_DOEPCTL1_STALL_DEFAULT 0x0
+#define GC_USB_DOEPCTL1_STALL_OFFSET 0xb20
+#define GC_USB_DOEPCTL1_CNAK_LSB 0x1a
+#define GC_USB_DOEPCTL1_CNAK_MASK 0x4000000
+#define GC_USB_DOEPCTL1_CNAK_SIZE 0x1
+#define GC_USB_DOEPCTL1_CNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL1_CNAK_OFFSET 0xb20
+#define GC_USB_DOEPCTL1_SNAK_LSB 0x1b
+#define GC_USB_DOEPCTL1_SNAK_MASK 0x8000000
+#define GC_USB_DOEPCTL1_SNAK_SIZE 0x1
+#define GC_USB_DOEPCTL1_SNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL1_SNAK_OFFSET 0xb20
+#define GC_USB_DOEPCTL1_SETD0PID_LSB 0x1c
+#define GC_USB_DOEPCTL1_SETD0PID_MASK 0x10000000
+#define GC_USB_DOEPCTL1_SETD0PID_SIZE 0x1
+#define GC_USB_DOEPCTL1_SETD0PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL1_SETD0PID_OFFSET 0xb20
+#define GC_USB_DOEPCTL1_SETD1PID_LSB 0x1d
+#define GC_USB_DOEPCTL1_SETD1PID_MASK 0x20000000
+#define GC_USB_DOEPCTL1_SETD1PID_SIZE 0x1
+#define GC_USB_DOEPCTL1_SETD1PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL1_SETD1PID_OFFSET 0xb20
+#define GC_USB_DOEPCTL1_EPDIS_LSB 0x1e
+#define GC_USB_DOEPCTL1_EPDIS_MASK 0x40000000
+#define GC_USB_DOEPCTL1_EPDIS_SIZE 0x1
+#define GC_USB_DOEPCTL1_EPDIS_DEFAULT 0x0
+#define GC_USB_DOEPCTL1_EPDIS_OFFSET 0xb20
+#define GC_USB_DOEPCTL1_EPENA_LSB 0x1f
+#define GC_USB_DOEPCTL1_EPENA_MASK 0x80000000
+#define GC_USB_DOEPCTL1_EPENA_SIZE 0x1
+#define GC_USB_DOEPCTL1_EPENA_DEFAULT 0x0
+#define GC_USB_DOEPCTL1_EPENA_OFFSET 0xb20
+#define GC_USB_DOEPINT1_XFERCOMPL_LSB 0x0
+#define GC_USB_DOEPINT1_XFERCOMPL_MASK 0x1
+#define GC_USB_DOEPINT1_XFERCOMPL_SIZE 0x1
+#define GC_USB_DOEPINT1_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DOEPINT1_XFERCOMPL_OFFSET 0xb28
+#define GC_USB_DOEPINT1_EPDISBLD_LSB 0x1
+#define GC_USB_DOEPINT1_EPDISBLD_MASK 0x2
+#define GC_USB_DOEPINT1_EPDISBLD_SIZE 0x1
+#define GC_USB_DOEPINT1_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DOEPINT1_EPDISBLD_OFFSET 0xb28
+#define GC_USB_DOEPINT1_AHBERR_LSB 0x2
+#define GC_USB_DOEPINT1_AHBERR_MASK 0x4
+#define GC_USB_DOEPINT1_AHBERR_SIZE 0x1
+#define GC_USB_DOEPINT1_AHBERR_DEFAULT 0x0
+#define GC_USB_DOEPINT1_AHBERR_OFFSET 0xb28
+#define GC_USB_DOEPINT1_SETUP_LSB 0x3
+#define GC_USB_DOEPINT1_SETUP_MASK 0x8
+#define GC_USB_DOEPINT1_SETUP_SIZE 0x1
+#define GC_USB_DOEPINT1_SETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT1_SETUP_OFFSET 0xb28
+#define GC_USB_DOEPINT1_OUTTKNEPDIS_LSB 0x4
+#define GC_USB_DOEPINT1_OUTTKNEPDIS_MASK 0x10
+#define GC_USB_DOEPINT1_OUTTKNEPDIS_SIZE 0x1
+#define GC_USB_DOEPINT1_OUTTKNEPDIS_DEFAULT 0x0
+#define GC_USB_DOEPINT1_OUTTKNEPDIS_OFFSET 0xb28
+#define GC_USB_DOEPINT1_STSPHSERCVD_LSB 0x5
+#define GC_USB_DOEPINT1_STSPHSERCVD_MASK 0x20
+#define GC_USB_DOEPINT1_STSPHSERCVD_SIZE 0x1
+#define GC_USB_DOEPINT1_STSPHSERCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT1_STSPHSERCVD_OFFSET 0xb28
+#define GC_USB_DOEPINT1_BACK2BACKSETUP_LSB 0x6
+#define GC_USB_DOEPINT1_BACK2BACKSETUP_MASK 0x40
+#define GC_USB_DOEPINT1_BACK2BACKSETUP_SIZE 0x1
+#define GC_USB_DOEPINT1_BACK2BACKSETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT1_BACK2BACKSETUP_OFFSET 0xb28
+#define GC_USB_DOEPINT1_OUTPKTERR_LSB 0x8
+#define GC_USB_DOEPINT1_OUTPKTERR_MASK 0x100
+#define GC_USB_DOEPINT1_OUTPKTERR_SIZE 0x1
+#define GC_USB_DOEPINT1_OUTPKTERR_DEFAULT 0x0
+#define GC_USB_DOEPINT1_OUTPKTERR_OFFSET 0xb28
+#define GC_USB_DOEPINT1_BNAINTR_LSB 0x9
+#define GC_USB_DOEPINT1_BNAINTR_MASK 0x200
+#define GC_USB_DOEPINT1_BNAINTR_SIZE 0x1
+#define GC_USB_DOEPINT1_BNAINTR_DEFAULT 0x0
+#define GC_USB_DOEPINT1_BNAINTR_OFFSET 0xb28
+#define GC_USB_DOEPINT1_PKTDRPSTS_LSB 0xb
+#define GC_USB_DOEPINT1_PKTDRPSTS_MASK 0x800
+#define GC_USB_DOEPINT1_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DOEPINT1_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DOEPINT1_PKTDRPSTS_OFFSET 0xb28
+#define GC_USB_DOEPINT1_BBLEERR_LSB 0xc
+#define GC_USB_DOEPINT1_BBLEERR_MASK 0x1000
+#define GC_USB_DOEPINT1_BBLEERR_SIZE 0x1
+#define GC_USB_DOEPINT1_BBLEERR_DEFAULT 0x0
+#define GC_USB_DOEPINT1_BBLEERR_OFFSET 0xb28
+#define GC_USB_DOEPINT1_NAKINTRPT_LSB 0xd
+#define GC_USB_DOEPINT1_NAKINTRPT_MASK 0x2000
+#define GC_USB_DOEPINT1_NAKINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT1_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT1_NAKINTRPT_OFFSET 0xb28
+#define GC_USB_DOEPINT1_NYETINTRPT_LSB 0xe
+#define GC_USB_DOEPINT1_NYETINTRPT_MASK 0x4000
+#define GC_USB_DOEPINT1_NYETINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT1_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT1_NYETINTRPT_OFFSET 0xb28
+#define GC_USB_DOEPINT1_STUPPKTRCVD_LSB 0xf
+#define GC_USB_DOEPINT1_STUPPKTRCVD_MASK 0x8000
+#define GC_USB_DOEPINT1_STUPPKTRCVD_SIZE 0x1
+#define GC_USB_DOEPINT1_STUPPKTRCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT1_STUPPKTRCVD_OFFSET 0xb28
+#define GC_USB_DOEPTSIZ1_XFERSIZE_LSB 0x0
+#define GC_USB_DOEPTSIZ1_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DOEPTSIZ1_XFERSIZE_SIZE 0x13
+#define GC_USB_DOEPTSIZ1_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ1_XFERSIZE_OFFSET 0xb30
+#define GC_USB_DOEPTSIZ1_PKTCNT_LSB 0x13
+#define GC_USB_DOEPTSIZ1_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DOEPTSIZ1_PKTCNT_SIZE 0xa
+#define GC_USB_DOEPTSIZ1_PKTCNT_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ1_PKTCNT_OFFSET 0xb30
+#define GC_USB_DOEPTSIZ1_RXDPID_LSB 0x1d
+#define GC_USB_DOEPTSIZ1_RXDPID_MASK 0x60000000
+#define GC_USB_DOEPTSIZ1_RXDPID_SIZE 0x2
+#define GC_USB_DOEPTSIZ1_RXDPID_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ1_RXDPID_OFFSET 0xb30
+#define GC_USB_DOEPDMA1_DMAADDR_LSB 0x0
+#define GC_USB_DOEPDMA1_DMAADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMA1_DMAADDR_SIZE 0x20
+#define GC_USB_DOEPDMA1_DMAADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMA1_DMAADDR_OFFSET 0xb34
+#define GC_USB_DOEPDMAB1_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DOEPDMAB1_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMAB1_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DOEPDMAB1_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMAB1_DMABUFFERADDR_OFFSET 0xb3c
+#define GC_USB_DOEPCTL2_MPS_LSB 0x0
+#define GC_USB_DOEPCTL2_MPS_MASK 0x7ff
+#define GC_USB_DOEPCTL2_MPS_SIZE 0xb
+#define GC_USB_DOEPCTL2_MPS_DEFAULT 0x0
+#define GC_USB_DOEPCTL2_MPS_OFFSET 0xb40
+#define GC_USB_DOEPCTL2_USBACTEP_LSB 0xf
+#define GC_USB_DOEPCTL2_USBACTEP_MASK 0x8000
+#define GC_USB_DOEPCTL2_USBACTEP_SIZE 0x1
+#define GC_USB_DOEPCTL2_USBACTEP_DEFAULT 0x0
+#define GC_USB_DOEPCTL2_USBACTEP_OFFSET 0xb40
+#define GC_USB_DOEPCTL2_DPID_LSB 0x10
+#define GC_USB_DOEPCTL2_DPID_MASK 0x10000
+#define GC_USB_DOEPCTL2_DPID_SIZE 0x1
+#define GC_USB_DOEPCTL2_DPID_DEFAULT 0x0
+#define GC_USB_DOEPCTL2_DPID_OFFSET 0xb40
+#define GC_USB_DOEPCTL2_NAKSTS_LSB 0x11
+#define GC_USB_DOEPCTL2_NAKSTS_MASK 0x20000
+#define GC_USB_DOEPCTL2_NAKSTS_SIZE 0x1
+#define GC_USB_DOEPCTL2_NAKSTS_DEFAULT 0x0
+#define GC_USB_DOEPCTL2_NAKSTS_OFFSET 0xb40
+#define GC_USB_DOEPCTL2_EPTYPE_LSB 0x12
+#define GC_USB_DOEPCTL2_EPTYPE_MASK 0xc0000
+#define GC_USB_DOEPCTL2_EPTYPE_SIZE 0x2
+#define GC_USB_DOEPCTL2_EPTYPE_DEFAULT 0x0
+#define GC_USB_DOEPCTL2_EPTYPE_OFFSET 0xb40
+#define GC_USB_DOEPCTL2_SNP_LSB 0x14
+#define GC_USB_DOEPCTL2_SNP_MASK 0x100000
+#define GC_USB_DOEPCTL2_SNP_SIZE 0x1
+#define GC_USB_DOEPCTL2_SNP_DEFAULT 0x0
+#define GC_USB_DOEPCTL2_SNP_OFFSET 0xb40
+#define GC_USB_DOEPCTL2_STALL_LSB 0x15
+#define GC_USB_DOEPCTL2_STALL_MASK 0x200000
+#define GC_USB_DOEPCTL2_STALL_SIZE 0x1
+#define GC_USB_DOEPCTL2_STALL_DEFAULT 0x0
+#define GC_USB_DOEPCTL2_STALL_OFFSET 0xb40
+#define GC_USB_DOEPCTL2_CNAK_LSB 0x1a
+#define GC_USB_DOEPCTL2_CNAK_MASK 0x4000000
+#define GC_USB_DOEPCTL2_CNAK_SIZE 0x1
+#define GC_USB_DOEPCTL2_CNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL2_CNAK_OFFSET 0xb40
+#define GC_USB_DOEPCTL2_SNAK_LSB 0x1b
+#define GC_USB_DOEPCTL2_SNAK_MASK 0x8000000
+#define GC_USB_DOEPCTL2_SNAK_SIZE 0x1
+#define GC_USB_DOEPCTL2_SNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL2_SNAK_OFFSET 0xb40
+#define GC_USB_DOEPCTL2_SETD0PID_LSB 0x1c
+#define GC_USB_DOEPCTL2_SETD0PID_MASK 0x10000000
+#define GC_USB_DOEPCTL2_SETD0PID_SIZE 0x1
+#define GC_USB_DOEPCTL2_SETD0PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL2_SETD0PID_OFFSET 0xb40
+#define GC_USB_DOEPCTL2_SETD1PID_LSB 0x1d
+#define GC_USB_DOEPCTL2_SETD1PID_MASK 0x20000000
+#define GC_USB_DOEPCTL2_SETD1PID_SIZE 0x1
+#define GC_USB_DOEPCTL2_SETD1PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL2_SETD1PID_OFFSET 0xb40
+#define GC_USB_DOEPCTL2_EPDIS_LSB 0x1e
+#define GC_USB_DOEPCTL2_EPDIS_MASK 0x40000000
+#define GC_USB_DOEPCTL2_EPDIS_SIZE 0x1
+#define GC_USB_DOEPCTL2_EPDIS_DEFAULT 0x0
+#define GC_USB_DOEPCTL2_EPDIS_OFFSET 0xb40
+#define GC_USB_DOEPCTL2_EPENA_LSB 0x1f
+#define GC_USB_DOEPCTL2_EPENA_MASK 0x80000000
+#define GC_USB_DOEPCTL2_EPENA_SIZE 0x1
+#define GC_USB_DOEPCTL2_EPENA_DEFAULT 0x0
+#define GC_USB_DOEPCTL2_EPENA_OFFSET 0xb40
+#define GC_USB_DOEPINT2_XFERCOMPL_LSB 0x0
+#define GC_USB_DOEPINT2_XFERCOMPL_MASK 0x1
+#define GC_USB_DOEPINT2_XFERCOMPL_SIZE 0x1
+#define GC_USB_DOEPINT2_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DOEPINT2_XFERCOMPL_OFFSET 0xb48
+#define GC_USB_DOEPINT2_EPDISBLD_LSB 0x1
+#define GC_USB_DOEPINT2_EPDISBLD_MASK 0x2
+#define GC_USB_DOEPINT2_EPDISBLD_SIZE 0x1
+#define GC_USB_DOEPINT2_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DOEPINT2_EPDISBLD_OFFSET 0xb48
+#define GC_USB_DOEPINT2_AHBERR_LSB 0x2
+#define GC_USB_DOEPINT2_AHBERR_MASK 0x4
+#define GC_USB_DOEPINT2_AHBERR_SIZE 0x1
+#define GC_USB_DOEPINT2_AHBERR_DEFAULT 0x0
+#define GC_USB_DOEPINT2_AHBERR_OFFSET 0xb48
+#define GC_USB_DOEPINT2_SETUP_LSB 0x3
+#define GC_USB_DOEPINT2_SETUP_MASK 0x8
+#define GC_USB_DOEPINT2_SETUP_SIZE 0x1
+#define GC_USB_DOEPINT2_SETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT2_SETUP_OFFSET 0xb48
+#define GC_USB_DOEPINT2_OUTTKNEPDIS_LSB 0x4
+#define GC_USB_DOEPINT2_OUTTKNEPDIS_MASK 0x10
+#define GC_USB_DOEPINT2_OUTTKNEPDIS_SIZE 0x1
+#define GC_USB_DOEPINT2_OUTTKNEPDIS_DEFAULT 0x0
+#define GC_USB_DOEPINT2_OUTTKNEPDIS_OFFSET 0xb48
+#define GC_USB_DOEPINT2_STSPHSERCVD_LSB 0x5
+#define GC_USB_DOEPINT2_STSPHSERCVD_MASK 0x20
+#define GC_USB_DOEPINT2_STSPHSERCVD_SIZE 0x1
+#define GC_USB_DOEPINT2_STSPHSERCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT2_STSPHSERCVD_OFFSET 0xb48
+#define GC_USB_DOEPINT2_BACK2BACKSETUP_LSB 0x6
+#define GC_USB_DOEPINT2_BACK2BACKSETUP_MASK 0x40
+#define GC_USB_DOEPINT2_BACK2BACKSETUP_SIZE 0x1
+#define GC_USB_DOEPINT2_BACK2BACKSETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT2_BACK2BACKSETUP_OFFSET 0xb48
+#define GC_USB_DOEPINT2_OUTPKTERR_LSB 0x8
+#define GC_USB_DOEPINT2_OUTPKTERR_MASK 0x100
+#define GC_USB_DOEPINT2_OUTPKTERR_SIZE 0x1
+#define GC_USB_DOEPINT2_OUTPKTERR_DEFAULT 0x0
+#define GC_USB_DOEPINT2_OUTPKTERR_OFFSET 0xb48
+#define GC_USB_DOEPINT2_BNAINTR_LSB 0x9
+#define GC_USB_DOEPINT2_BNAINTR_MASK 0x200
+#define GC_USB_DOEPINT2_BNAINTR_SIZE 0x1
+#define GC_USB_DOEPINT2_BNAINTR_DEFAULT 0x0
+#define GC_USB_DOEPINT2_BNAINTR_OFFSET 0xb48
+#define GC_USB_DOEPINT2_PKTDRPSTS_LSB 0xb
+#define GC_USB_DOEPINT2_PKTDRPSTS_MASK 0x800
+#define GC_USB_DOEPINT2_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DOEPINT2_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DOEPINT2_PKTDRPSTS_OFFSET 0xb48
+#define GC_USB_DOEPINT2_BBLEERR_LSB 0xc
+#define GC_USB_DOEPINT2_BBLEERR_MASK 0x1000
+#define GC_USB_DOEPINT2_BBLEERR_SIZE 0x1
+#define GC_USB_DOEPINT2_BBLEERR_DEFAULT 0x0
+#define GC_USB_DOEPINT2_BBLEERR_OFFSET 0xb48
+#define GC_USB_DOEPINT2_NAKINTRPT_LSB 0xd
+#define GC_USB_DOEPINT2_NAKINTRPT_MASK 0x2000
+#define GC_USB_DOEPINT2_NAKINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT2_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT2_NAKINTRPT_OFFSET 0xb48
+#define GC_USB_DOEPINT2_NYETINTRPT_LSB 0xe
+#define GC_USB_DOEPINT2_NYETINTRPT_MASK 0x4000
+#define GC_USB_DOEPINT2_NYETINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT2_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT2_NYETINTRPT_OFFSET 0xb48
+#define GC_USB_DOEPINT2_STUPPKTRCVD_LSB 0xf
+#define GC_USB_DOEPINT2_STUPPKTRCVD_MASK 0x8000
+#define GC_USB_DOEPINT2_STUPPKTRCVD_SIZE 0x1
+#define GC_USB_DOEPINT2_STUPPKTRCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT2_STUPPKTRCVD_OFFSET 0xb48
+#define GC_USB_DOEPTSIZ2_XFERSIZE_LSB 0x0
+#define GC_USB_DOEPTSIZ2_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DOEPTSIZ2_XFERSIZE_SIZE 0x13
+#define GC_USB_DOEPTSIZ2_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ2_XFERSIZE_OFFSET 0xb50
+#define GC_USB_DOEPTSIZ2_PKTCNT_LSB 0x13
+#define GC_USB_DOEPTSIZ2_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DOEPTSIZ2_PKTCNT_SIZE 0xa
+#define GC_USB_DOEPTSIZ2_PKTCNT_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ2_PKTCNT_OFFSET 0xb50
+#define GC_USB_DOEPTSIZ2_RXDPID_LSB 0x1d
+#define GC_USB_DOEPTSIZ2_RXDPID_MASK 0x60000000
+#define GC_USB_DOEPTSIZ2_RXDPID_SIZE 0x2
+#define GC_USB_DOEPTSIZ2_RXDPID_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ2_RXDPID_OFFSET 0xb50
+#define GC_USB_DOEPDMA2_DMAADDR_LSB 0x0
+#define GC_USB_DOEPDMA2_DMAADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMA2_DMAADDR_SIZE 0x20
+#define GC_USB_DOEPDMA2_DMAADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMA2_DMAADDR_OFFSET 0xb54
+#define GC_USB_DOEPDMAB2_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DOEPDMAB2_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMAB2_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DOEPDMAB2_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMAB2_DMABUFFERADDR_OFFSET 0xb5c
+#define GC_USB_DOEPCTL3_MPS_LSB 0x0
+#define GC_USB_DOEPCTL3_MPS_MASK 0x7ff
+#define GC_USB_DOEPCTL3_MPS_SIZE 0xb
+#define GC_USB_DOEPCTL3_MPS_DEFAULT 0x0
+#define GC_USB_DOEPCTL3_MPS_OFFSET 0xb60
+#define GC_USB_DOEPCTL3_USBACTEP_LSB 0xf
+#define GC_USB_DOEPCTL3_USBACTEP_MASK 0x8000
+#define GC_USB_DOEPCTL3_USBACTEP_SIZE 0x1
+#define GC_USB_DOEPCTL3_USBACTEP_DEFAULT 0x0
+#define GC_USB_DOEPCTL3_USBACTEP_OFFSET 0xb60
+#define GC_USB_DOEPCTL3_DPID_LSB 0x10
+#define GC_USB_DOEPCTL3_DPID_MASK 0x10000
+#define GC_USB_DOEPCTL3_DPID_SIZE 0x1
+#define GC_USB_DOEPCTL3_DPID_DEFAULT 0x0
+#define GC_USB_DOEPCTL3_DPID_OFFSET 0xb60
+#define GC_USB_DOEPCTL3_NAKSTS_LSB 0x11
+#define GC_USB_DOEPCTL3_NAKSTS_MASK 0x20000
+#define GC_USB_DOEPCTL3_NAKSTS_SIZE 0x1
+#define GC_USB_DOEPCTL3_NAKSTS_DEFAULT 0x0
+#define GC_USB_DOEPCTL3_NAKSTS_OFFSET 0xb60
+#define GC_USB_DOEPCTL3_EPTYPE_LSB 0x12
+#define GC_USB_DOEPCTL3_EPTYPE_MASK 0xc0000
+#define GC_USB_DOEPCTL3_EPTYPE_SIZE 0x2
+#define GC_USB_DOEPCTL3_EPTYPE_DEFAULT 0x0
+#define GC_USB_DOEPCTL3_EPTYPE_OFFSET 0xb60
+#define GC_USB_DOEPCTL3_SNP_LSB 0x14
+#define GC_USB_DOEPCTL3_SNP_MASK 0x100000
+#define GC_USB_DOEPCTL3_SNP_SIZE 0x1
+#define GC_USB_DOEPCTL3_SNP_DEFAULT 0x0
+#define GC_USB_DOEPCTL3_SNP_OFFSET 0xb60
+#define GC_USB_DOEPCTL3_STALL_LSB 0x15
+#define GC_USB_DOEPCTL3_STALL_MASK 0x200000
+#define GC_USB_DOEPCTL3_STALL_SIZE 0x1
+#define GC_USB_DOEPCTL3_STALL_DEFAULT 0x0
+#define GC_USB_DOEPCTL3_STALL_OFFSET 0xb60
+#define GC_USB_DOEPCTL3_CNAK_LSB 0x1a
+#define GC_USB_DOEPCTL3_CNAK_MASK 0x4000000
+#define GC_USB_DOEPCTL3_CNAK_SIZE 0x1
+#define GC_USB_DOEPCTL3_CNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL3_CNAK_OFFSET 0xb60
+#define GC_USB_DOEPCTL3_SNAK_LSB 0x1b
+#define GC_USB_DOEPCTL3_SNAK_MASK 0x8000000
+#define GC_USB_DOEPCTL3_SNAK_SIZE 0x1
+#define GC_USB_DOEPCTL3_SNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL3_SNAK_OFFSET 0xb60
+#define GC_USB_DOEPCTL3_SETD0PID_LSB 0x1c
+#define GC_USB_DOEPCTL3_SETD0PID_MASK 0x10000000
+#define GC_USB_DOEPCTL3_SETD0PID_SIZE 0x1
+#define GC_USB_DOEPCTL3_SETD0PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL3_SETD0PID_OFFSET 0xb60
+#define GC_USB_DOEPCTL3_SETD1PID_LSB 0x1d
+#define GC_USB_DOEPCTL3_SETD1PID_MASK 0x20000000
+#define GC_USB_DOEPCTL3_SETD1PID_SIZE 0x1
+#define GC_USB_DOEPCTL3_SETD1PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL3_SETD1PID_OFFSET 0xb60
+#define GC_USB_DOEPCTL3_EPDIS_LSB 0x1e
+#define GC_USB_DOEPCTL3_EPDIS_MASK 0x40000000
+#define GC_USB_DOEPCTL3_EPDIS_SIZE 0x1
+#define GC_USB_DOEPCTL3_EPDIS_DEFAULT 0x0
+#define GC_USB_DOEPCTL3_EPDIS_OFFSET 0xb60
+#define GC_USB_DOEPCTL3_EPENA_LSB 0x1f
+#define GC_USB_DOEPCTL3_EPENA_MASK 0x80000000
+#define GC_USB_DOEPCTL3_EPENA_SIZE 0x1
+#define GC_USB_DOEPCTL3_EPENA_DEFAULT 0x0
+#define GC_USB_DOEPCTL3_EPENA_OFFSET 0xb60
+#define GC_USB_DOEPINT3_XFERCOMPL_LSB 0x0
+#define GC_USB_DOEPINT3_XFERCOMPL_MASK 0x1
+#define GC_USB_DOEPINT3_XFERCOMPL_SIZE 0x1
+#define GC_USB_DOEPINT3_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DOEPINT3_XFERCOMPL_OFFSET 0xb68
+#define GC_USB_DOEPINT3_EPDISBLD_LSB 0x1
+#define GC_USB_DOEPINT3_EPDISBLD_MASK 0x2
+#define GC_USB_DOEPINT3_EPDISBLD_SIZE 0x1
+#define GC_USB_DOEPINT3_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DOEPINT3_EPDISBLD_OFFSET 0xb68
+#define GC_USB_DOEPINT3_AHBERR_LSB 0x2
+#define GC_USB_DOEPINT3_AHBERR_MASK 0x4
+#define GC_USB_DOEPINT3_AHBERR_SIZE 0x1
+#define GC_USB_DOEPINT3_AHBERR_DEFAULT 0x0
+#define GC_USB_DOEPINT3_AHBERR_OFFSET 0xb68
+#define GC_USB_DOEPINT3_SETUP_LSB 0x3
+#define GC_USB_DOEPINT3_SETUP_MASK 0x8
+#define GC_USB_DOEPINT3_SETUP_SIZE 0x1
+#define GC_USB_DOEPINT3_SETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT3_SETUP_OFFSET 0xb68
+#define GC_USB_DOEPINT3_OUTTKNEPDIS_LSB 0x4
+#define GC_USB_DOEPINT3_OUTTKNEPDIS_MASK 0x10
+#define GC_USB_DOEPINT3_OUTTKNEPDIS_SIZE 0x1
+#define GC_USB_DOEPINT3_OUTTKNEPDIS_DEFAULT 0x0
+#define GC_USB_DOEPINT3_OUTTKNEPDIS_OFFSET 0xb68
+#define GC_USB_DOEPINT3_STSPHSERCVD_LSB 0x5
+#define GC_USB_DOEPINT3_STSPHSERCVD_MASK 0x20
+#define GC_USB_DOEPINT3_STSPHSERCVD_SIZE 0x1
+#define GC_USB_DOEPINT3_STSPHSERCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT3_STSPHSERCVD_OFFSET 0xb68
+#define GC_USB_DOEPINT3_BACK2BACKSETUP_LSB 0x6
+#define GC_USB_DOEPINT3_BACK2BACKSETUP_MASK 0x40
+#define GC_USB_DOEPINT3_BACK2BACKSETUP_SIZE 0x1
+#define GC_USB_DOEPINT3_BACK2BACKSETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT3_BACK2BACKSETUP_OFFSET 0xb68
+#define GC_USB_DOEPINT3_OUTPKTERR_LSB 0x8
+#define GC_USB_DOEPINT3_OUTPKTERR_MASK 0x100
+#define GC_USB_DOEPINT3_OUTPKTERR_SIZE 0x1
+#define GC_USB_DOEPINT3_OUTPKTERR_DEFAULT 0x0
+#define GC_USB_DOEPINT3_OUTPKTERR_OFFSET 0xb68
+#define GC_USB_DOEPINT3_BNAINTR_LSB 0x9
+#define GC_USB_DOEPINT3_BNAINTR_MASK 0x200
+#define GC_USB_DOEPINT3_BNAINTR_SIZE 0x1
+#define GC_USB_DOEPINT3_BNAINTR_DEFAULT 0x0
+#define GC_USB_DOEPINT3_BNAINTR_OFFSET 0xb68
+#define GC_USB_DOEPINT3_PKTDRPSTS_LSB 0xb
+#define GC_USB_DOEPINT3_PKTDRPSTS_MASK 0x800
+#define GC_USB_DOEPINT3_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DOEPINT3_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DOEPINT3_PKTDRPSTS_OFFSET 0xb68
+#define GC_USB_DOEPINT3_BBLEERR_LSB 0xc
+#define GC_USB_DOEPINT3_BBLEERR_MASK 0x1000
+#define GC_USB_DOEPINT3_BBLEERR_SIZE 0x1
+#define GC_USB_DOEPINT3_BBLEERR_DEFAULT 0x0
+#define GC_USB_DOEPINT3_BBLEERR_OFFSET 0xb68
+#define GC_USB_DOEPINT3_NAKINTRPT_LSB 0xd
+#define GC_USB_DOEPINT3_NAKINTRPT_MASK 0x2000
+#define GC_USB_DOEPINT3_NAKINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT3_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT3_NAKINTRPT_OFFSET 0xb68
+#define GC_USB_DOEPINT3_NYETINTRPT_LSB 0xe
+#define GC_USB_DOEPINT3_NYETINTRPT_MASK 0x4000
+#define GC_USB_DOEPINT3_NYETINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT3_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT3_NYETINTRPT_OFFSET 0xb68
+#define GC_USB_DOEPINT3_STUPPKTRCVD_LSB 0xf
+#define GC_USB_DOEPINT3_STUPPKTRCVD_MASK 0x8000
+#define GC_USB_DOEPINT3_STUPPKTRCVD_SIZE 0x1
+#define GC_USB_DOEPINT3_STUPPKTRCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT3_STUPPKTRCVD_OFFSET 0xb68
+#define GC_USB_DOEPTSIZ3_XFERSIZE_LSB 0x0
+#define GC_USB_DOEPTSIZ3_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DOEPTSIZ3_XFERSIZE_SIZE 0x13
+#define GC_USB_DOEPTSIZ3_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ3_XFERSIZE_OFFSET 0xb70
+#define GC_USB_DOEPTSIZ3_PKTCNT_LSB 0x13
+#define GC_USB_DOEPTSIZ3_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DOEPTSIZ3_PKTCNT_SIZE 0xa
+#define GC_USB_DOEPTSIZ3_PKTCNT_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ3_PKTCNT_OFFSET 0xb70
+#define GC_USB_DOEPTSIZ3_RXDPID_LSB 0x1d
+#define GC_USB_DOEPTSIZ3_RXDPID_MASK 0x60000000
+#define GC_USB_DOEPTSIZ3_RXDPID_SIZE 0x2
+#define GC_USB_DOEPTSIZ3_RXDPID_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ3_RXDPID_OFFSET 0xb70
+#define GC_USB_DOEPDMA3_DMAADDR_LSB 0x0
+#define GC_USB_DOEPDMA3_DMAADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMA3_DMAADDR_SIZE 0x20
+#define GC_USB_DOEPDMA3_DMAADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMA3_DMAADDR_OFFSET 0xb74
+#define GC_USB_DOEPDMAB3_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DOEPDMAB3_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMAB3_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DOEPDMAB3_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMAB3_DMABUFFERADDR_OFFSET 0xb7c
+#define GC_USB_DOEPCTL4_MPS_LSB 0x0
+#define GC_USB_DOEPCTL4_MPS_MASK 0x7ff
+#define GC_USB_DOEPCTL4_MPS_SIZE 0xb
+#define GC_USB_DOEPCTL4_MPS_DEFAULT 0x0
+#define GC_USB_DOEPCTL4_MPS_OFFSET 0xb80
+#define GC_USB_DOEPCTL4_USBACTEP_LSB 0xf
+#define GC_USB_DOEPCTL4_USBACTEP_MASK 0x8000
+#define GC_USB_DOEPCTL4_USBACTEP_SIZE 0x1
+#define GC_USB_DOEPCTL4_USBACTEP_DEFAULT 0x0
+#define GC_USB_DOEPCTL4_USBACTEP_OFFSET 0xb80
+#define GC_USB_DOEPCTL4_DPID_LSB 0x10
+#define GC_USB_DOEPCTL4_DPID_MASK 0x10000
+#define GC_USB_DOEPCTL4_DPID_SIZE 0x1
+#define GC_USB_DOEPCTL4_DPID_DEFAULT 0x0
+#define GC_USB_DOEPCTL4_DPID_OFFSET 0xb80
+#define GC_USB_DOEPCTL4_NAKSTS_LSB 0x11
+#define GC_USB_DOEPCTL4_NAKSTS_MASK 0x20000
+#define GC_USB_DOEPCTL4_NAKSTS_SIZE 0x1
+#define GC_USB_DOEPCTL4_NAKSTS_DEFAULT 0x0
+#define GC_USB_DOEPCTL4_NAKSTS_OFFSET 0xb80
+#define GC_USB_DOEPCTL4_EPTYPE_LSB 0x12
+#define GC_USB_DOEPCTL4_EPTYPE_MASK 0xc0000
+#define GC_USB_DOEPCTL4_EPTYPE_SIZE 0x2
+#define GC_USB_DOEPCTL4_EPTYPE_DEFAULT 0x0
+#define GC_USB_DOEPCTL4_EPTYPE_OFFSET 0xb80
+#define GC_USB_DOEPCTL4_SNP_LSB 0x14
+#define GC_USB_DOEPCTL4_SNP_MASK 0x100000
+#define GC_USB_DOEPCTL4_SNP_SIZE 0x1
+#define GC_USB_DOEPCTL4_SNP_DEFAULT 0x0
+#define GC_USB_DOEPCTL4_SNP_OFFSET 0xb80
+#define GC_USB_DOEPCTL4_STALL_LSB 0x15
+#define GC_USB_DOEPCTL4_STALL_MASK 0x200000
+#define GC_USB_DOEPCTL4_STALL_SIZE 0x1
+#define GC_USB_DOEPCTL4_STALL_DEFAULT 0x0
+#define GC_USB_DOEPCTL4_STALL_OFFSET 0xb80
+#define GC_USB_DOEPCTL4_CNAK_LSB 0x1a
+#define GC_USB_DOEPCTL4_CNAK_MASK 0x4000000
+#define GC_USB_DOEPCTL4_CNAK_SIZE 0x1
+#define GC_USB_DOEPCTL4_CNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL4_CNAK_OFFSET 0xb80
+#define GC_USB_DOEPCTL4_SNAK_LSB 0x1b
+#define GC_USB_DOEPCTL4_SNAK_MASK 0x8000000
+#define GC_USB_DOEPCTL4_SNAK_SIZE 0x1
+#define GC_USB_DOEPCTL4_SNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL4_SNAK_OFFSET 0xb80
+#define GC_USB_DOEPCTL4_SETD0PID_LSB 0x1c
+#define GC_USB_DOEPCTL4_SETD0PID_MASK 0x10000000
+#define GC_USB_DOEPCTL4_SETD0PID_SIZE 0x1
+#define GC_USB_DOEPCTL4_SETD0PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL4_SETD0PID_OFFSET 0xb80
+#define GC_USB_DOEPCTL4_SETD1PID_LSB 0x1d
+#define GC_USB_DOEPCTL4_SETD1PID_MASK 0x20000000
+#define GC_USB_DOEPCTL4_SETD1PID_SIZE 0x1
+#define GC_USB_DOEPCTL4_SETD1PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL4_SETD1PID_OFFSET 0xb80
+#define GC_USB_DOEPCTL4_EPDIS_LSB 0x1e
+#define GC_USB_DOEPCTL4_EPDIS_MASK 0x40000000
+#define GC_USB_DOEPCTL4_EPDIS_SIZE 0x1
+#define GC_USB_DOEPCTL4_EPDIS_DEFAULT 0x0
+#define GC_USB_DOEPCTL4_EPDIS_OFFSET 0xb80
+#define GC_USB_DOEPCTL4_EPENA_LSB 0x1f
+#define GC_USB_DOEPCTL4_EPENA_MASK 0x80000000
+#define GC_USB_DOEPCTL4_EPENA_SIZE 0x1
+#define GC_USB_DOEPCTL4_EPENA_DEFAULT 0x0
+#define GC_USB_DOEPCTL4_EPENA_OFFSET 0xb80
+#define GC_USB_DOEPINT4_XFERCOMPL_LSB 0x0
+#define GC_USB_DOEPINT4_XFERCOMPL_MASK 0x1
+#define GC_USB_DOEPINT4_XFERCOMPL_SIZE 0x1
+#define GC_USB_DOEPINT4_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DOEPINT4_XFERCOMPL_OFFSET 0xb88
+#define GC_USB_DOEPINT4_EPDISBLD_LSB 0x1
+#define GC_USB_DOEPINT4_EPDISBLD_MASK 0x2
+#define GC_USB_DOEPINT4_EPDISBLD_SIZE 0x1
+#define GC_USB_DOEPINT4_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DOEPINT4_EPDISBLD_OFFSET 0xb88
+#define GC_USB_DOEPINT4_AHBERR_LSB 0x2
+#define GC_USB_DOEPINT4_AHBERR_MASK 0x4
+#define GC_USB_DOEPINT4_AHBERR_SIZE 0x1
+#define GC_USB_DOEPINT4_AHBERR_DEFAULT 0x0
+#define GC_USB_DOEPINT4_AHBERR_OFFSET 0xb88
+#define GC_USB_DOEPINT4_SETUP_LSB 0x3
+#define GC_USB_DOEPINT4_SETUP_MASK 0x8
+#define GC_USB_DOEPINT4_SETUP_SIZE 0x1
+#define GC_USB_DOEPINT4_SETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT4_SETUP_OFFSET 0xb88
+#define GC_USB_DOEPINT4_OUTTKNEPDIS_LSB 0x4
+#define GC_USB_DOEPINT4_OUTTKNEPDIS_MASK 0x10
+#define GC_USB_DOEPINT4_OUTTKNEPDIS_SIZE 0x1
+#define GC_USB_DOEPINT4_OUTTKNEPDIS_DEFAULT 0x0
+#define GC_USB_DOEPINT4_OUTTKNEPDIS_OFFSET 0xb88
+#define GC_USB_DOEPINT4_STSPHSERCVD_LSB 0x5
+#define GC_USB_DOEPINT4_STSPHSERCVD_MASK 0x20
+#define GC_USB_DOEPINT4_STSPHSERCVD_SIZE 0x1
+#define GC_USB_DOEPINT4_STSPHSERCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT4_STSPHSERCVD_OFFSET 0xb88
+#define GC_USB_DOEPINT4_BACK2BACKSETUP_LSB 0x6
+#define GC_USB_DOEPINT4_BACK2BACKSETUP_MASK 0x40
+#define GC_USB_DOEPINT4_BACK2BACKSETUP_SIZE 0x1
+#define GC_USB_DOEPINT4_BACK2BACKSETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT4_BACK2BACKSETUP_OFFSET 0xb88
+#define GC_USB_DOEPINT4_OUTPKTERR_LSB 0x8
+#define GC_USB_DOEPINT4_OUTPKTERR_MASK 0x100
+#define GC_USB_DOEPINT4_OUTPKTERR_SIZE 0x1
+#define GC_USB_DOEPINT4_OUTPKTERR_DEFAULT 0x0
+#define GC_USB_DOEPINT4_OUTPKTERR_OFFSET 0xb88
+#define GC_USB_DOEPINT4_BNAINTR_LSB 0x9
+#define GC_USB_DOEPINT4_BNAINTR_MASK 0x200
+#define GC_USB_DOEPINT4_BNAINTR_SIZE 0x1
+#define GC_USB_DOEPINT4_BNAINTR_DEFAULT 0x0
+#define GC_USB_DOEPINT4_BNAINTR_OFFSET 0xb88
+#define GC_USB_DOEPINT4_PKTDRPSTS_LSB 0xb
+#define GC_USB_DOEPINT4_PKTDRPSTS_MASK 0x800
+#define GC_USB_DOEPINT4_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DOEPINT4_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DOEPINT4_PKTDRPSTS_OFFSET 0xb88
+#define GC_USB_DOEPINT4_BBLEERR_LSB 0xc
+#define GC_USB_DOEPINT4_BBLEERR_MASK 0x1000
+#define GC_USB_DOEPINT4_BBLEERR_SIZE 0x1
+#define GC_USB_DOEPINT4_BBLEERR_DEFAULT 0x0
+#define GC_USB_DOEPINT4_BBLEERR_OFFSET 0xb88
+#define GC_USB_DOEPINT4_NAKINTRPT_LSB 0xd
+#define GC_USB_DOEPINT4_NAKINTRPT_MASK 0x2000
+#define GC_USB_DOEPINT4_NAKINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT4_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT4_NAKINTRPT_OFFSET 0xb88
+#define GC_USB_DOEPINT4_NYETINTRPT_LSB 0xe
+#define GC_USB_DOEPINT4_NYETINTRPT_MASK 0x4000
+#define GC_USB_DOEPINT4_NYETINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT4_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT4_NYETINTRPT_OFFSET 0xb88
+#define GC_USB_DOEPINT4_STUPPKTRCVD_LSB 0xf
+#define GC_USB_DOEPINT4_STUPPKTRCVD_MASK 0x8000
+#define GC_USB_DOEPINT4_STUPPKTRCVD_SIZE 0x1
+#define GC_USB_DOEPINT4_STUPPKTRCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT4_STUPPKTRCVD_OFFSET 0xb88
+#define GC_USB_DOEPTSIZ4_XFERSIZE_LSB 0x0
+#define GC_USB_DOEPTSIZ4_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DOEPTSIZ4_XFERSIZE_SIZE 0x13
+#define GC_USB_DOEPTSIZ4_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ4_XFERSIZE_OFFSET 0xb90
+#define GC_USB_DOEPTSIZ4_PKTCNT_LSB 0x13
+#define GC_USB_DOEPTSIZ4_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DOEPTSIZ4_PKTCNT_SIZE 0xa
+#define GC_USB_DOEPTSIZ4_PKTCNT_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ4_PKTCNT_OFFSET 0xb90
+#define GC_USB_DOEPTSIZ4_RXDPID_LSB 0x1d
+#define GC_USB_DOEPTSIZ4_RXDPID_MASK 0x60000000
+#define GC_USB_DOEPTSIZ4_RXDPID_SIZE 0x2
+#define GC_USB_DOEPTSIZ4_RXDPID_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ4_RXDPID_OFFSET 0xb90
+#define GC_USB_DOEPDMA4_DMAADDR_LSB 0x0
+#define GC_USB_DOEPDMA4_DMAADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMA4_DMAADDR_SIZE 0x20
+#define GC_USB_DOEPDMA4_DMAADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMA4_DMAADDR_OFFSET 0xb94
+#define GC_USB_DOEPDMAB4_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DOEPDMAB4_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMAB4_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DOEPDMAB4_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMAB4_DMABUFFERADDR_OFFSET 0xb9c
+#define GC_USB_DOEPCTL5_MPS_LSB 0x0
+#define GC_USB_DOEPCTL5_MPS_MASK 0x7ff
+#define GC_USB_DOEPCTL5_MPS_SIZE 0xb
+#define GC_USB_DOEPCTL5_MPS_DEFAULT 0x0
+#define GC_USB_DOEPCTL5_MPS_OFFSET 0xba0
+#define GC_USB_DOEPCTL5_USBACTEP_LSB 0xf
+#define GC_USB_DOEPCTL5_USBACTEP_MASK 0x8000
+#define GC_USB_DOEPCTL5_USBACTEP_SIZE 0x1
+#define GC_USB_DOEPCTL5_USBACTEP_DEFAULT 0x0
+#define GC_USB_DOEPCTL5_USBACTEP_OFFSET 0xba0
+#define GC_USB_DOEPCTL5_DPID_LSB 0x10
+#define GC_USB_DOEPCTL5_DPID_MASK 0x10000
+#define GC_USB_DOEPCTL5_DPID_SIZE 0x1
+#define GC_USB_DOEPCTL5_DPID_DEFAULT 0x0
+#define GC_USB_DOEPCTL5_DPID_OFFSET 0xba0
+#define GC_USB_DOEPCTL5_NAKSTS_LSB 0x11
+#define GC_USB_DOEPCTL5_NAKSTS_MASK 0x20000
+#define GC_USB_DOEPCTL5_NAKSTS_SIZE 0x1
+#define GC_USB_DOEPCTL5_NAKSTS_DEFAULT 0x0
+#define GC_USB_DOEPCTL5_NAKSTS_OFFSET 0xba0
+#define GC_USB_DOEPCTL5_EPTYPE_LSB 0x12
+#define GC_USB_DOEPCTL5_EPTYPE_MASK 0xc0000
+#define GC_USB_DOEPCTL5_EPTYPE_SIZE 0x2
+#define GC_USB_DOEPCTL5_EPTYPE_DEFAULT 0x0
+#define GC_USB_DOEPCTL5_EPTYPE_OFFSET 0xba0
+#define GC_USB_DOEPCTL5_SNP_LSB 0x14
+#define GC_USB_DOEPCTL5_SNP_MASK 0x100000
+#define GC_USB_DOEPCTL5_SNP_SIZE 0x1
+#define GC_USB_DOEPCTL5_SNP_DEFAULT 0x0
+#define GC_USB_DOEPCTL5_SNP_OFFSET 0xba0
+#define GC_USB_DOEPCTL5_STALL_LSB 0x15
+#define GC_USB_DOEPCTL5_STALL_MASK 0x200000
+#define GC_USB_DOEPCTL5_STALL_SIZE 0x1
+#define GC_USB_DOEPCTL5_STALL_DEFAULT 0x0
+#define GC_USB_DOEPCTL5_STALL_OFFSET 0xba0
+#define GC_USB_DOEPCTL5_CNAK_LSB 0x1a
+#define GC_USB_DOEPCTL5_CNAK_MASK 0x4000000
+#define GC_USB_DOEPCTL5_CNAK_SIZE 0x1
+#define GC_USB_DOEPCTL5_CNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL5_CNAK_OFFSET 0xba0
+#define GC_USB_DOEPCTL5_SNAK_LSB 0x1b
+#define GC_USB_DOEPCTL5_SNAK_MASK 0x8000000
+#define GC_USB_DOEPCTL5_SNAK_SIZE 0x1
+#define GC_USB_DOEPCTL5_SNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL5_SNAK_OFFSET 0xba0
+#define GC_USB_DOEPCTL5_SETD0PID_LSB 0x1c
+#define GC_USB_DOEPCTL5_SETD0PID_MASK 0x10000000
+#define GC_USB_DOEPCTL5_SETD0PID_SIZE 0x1
+#define GC_USB_DOEPCTL5_SETD0PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL5_SETD0PID_OFFSET 0xba0
+#define GC_USB_DOEPCTL5_SETD1PID_LSB 0x1d
+#define GC_USB_DOEPCTL5_SETD1PID_MASK 0x20000000
+#define GC_USB_DOEPCTL5_SETD1PID_SIZE 0x1
+#define GC_USB_DOEPCTL5_SETD1PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL5_SETD1PID_OFFSET 0xba0
+#define GC_USB_DOEPCTL5_EPDIS_LSB 0x1e
+#define GC_USB_DOEPCTL5_EPDIS_MASK 0x40000000
+#define GC_USB_DOEPCTL5_EPDIS_SIZE 0x1
+#define GC_USB_DOEPCTL5_EPDIS_DEFAULT 0x0
+#define GC_USB_DOEPCTL5_EPDIS_OFFSET 0xba0
+#define GC_USB_DOEPCTL5_EPENA_LSB 0x1f
+#define GC_USB_DOEPCTL5_EPENA_MASK 0x80000000
+#define GC_USB_DOEPCTL5_EPENA_SIZE 0x1
+#define GC_USB_DOEPCTL5_EPENA_DEFAULT 0x0
+#define GC_USB_DOEPCTL5_EPENA_OFFSET 0xba0
+#define GC_USB_DOEPINT5_XFERCOMPL_LSB 0x0
+#define GC_USB_DOEPINT5_XFERCOMPL_MASK 0x1
+#define GC_USB_DOEPINT5_XFERCOMPL_SIZE 0x1
+#define GC_USB_DOEPINT5_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DOEPINT5_XFERCOMPL_OFFSET 0xba8
+#define GC_USB_DOEPINT5_EPDISBLD_LSB 0x1
+#define GC_USB_DOEPINT5_EPDISBLD_MASK 0x2
+#define GC_USB_DOEPINT5_EPDISBLD_SIZE 0x1
+#define GC_USB_DOEPINT5_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DOEPINT5_EPDISBLD_OFFSET 0xba8
+#define GC_USB_DOEPINT5_AHBERR_LSB 0x2
+#define GC_USB_DOEPINT5_AHBERR_MASK 0x4
+#define GC_USB_DOEPINT5_AHBERR_SIZE 0x1
+#define GC_USB_DOEPINT5_AHBERR_DEFAULT 0x0
+#define GC_USB_DOEPINT5_AHBERR_OFFSET 0xba8
+#define GC_USB_DOEPINT5_SETUP_LSB 0x3
+#define GC_USB_DOEPINT5_SETUP_MASK 0x8
+#define GC_USB_DOEPINT5_SETUP_SIZE 0x1
+#define GC_USB_DOEPINT5_SETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT5_SETUP_OFFSET 0xba8
+#define GC_USB_DOEPINT5_OUTTKNEPDIS_LSB 0x4
+#define GC_USB_DOEPINT5_OUTTKNEPDIS_MASK 0x10
+#define GC_USB_DOEPINT5_OUTTKNEPDIS_SIZE 0x1
+#define GC_USB_DOEPINT5_OUTTKNEPDIS_DEFAULT 0x0
+#define GC_USB_DOEPINT5_OUTTKNEPDIS_OFFSET 0xba8
+#define GC_USB_DOEPINT5_STSPHSERCVD_LSB 0x5
+#define GC_USB_DOEPINT5_STSPHSERCVD_MASK 0x20
+#define GC_USB_DOEPINT5_STSPHSERCVD_SIZE 0x1
+#define GC_USB_DOEPINT5_STSPHSERCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT5_STSPHSERCVD_OFFSET 0xba8
+#define GC_USB_DOEPINT5_BACK2BACKSETUP_LSB 0x6
+#define GC_USB_DOEPINT5_BACK2BACKSETUP_MASK 0x40
+#define GC_USB_DOEPINT5_BACK2BACKSETUP_SIZE 0x1
+#define GC_USB_DOEPINT5_BACK2BACKSETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT5_BACK2BACKSETUP_OFFSET 0xba8
+#define GC_USB_DOEPINT5_OUTPKTERR_LSB 0x8
+#define GC_USB_DOEPINT5_OUTPKTERR_MASK 0x100
+#define GC_USB_DOEPINT5_OUTPKTERR_SIZE 0x1
+#define GC_USB_DOEPINT5_OUTPKTERR_DEFAULT 0x0
+#define GC_USB_DOEPINT5_OUTPKTERR_OFFSET 0xba8
+#define GC_USB_DOEPINT5_BNAINTR_LSB 0x9
+#define GC_USB_DOEPINT5_BNAINTR_MASK 0x200
+#define GC_USB_DOEPINT5_BNAINTR_SIZE 0x1
+#define GC_USB_DOEPINT5_BNAINTR_DEFAULT 0x0
+#define GC_USB_DOEPINT5_BNAINTR_OFFSET 0xba8
+#define GC_USB_DOEPINT5_PKTDRPSTS_LSB 0xb
+#define GC_USB_DOEPINT5_PKTDRPSTS_MASK 0x800
+#define GC_USB_DOEPINT5_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DOEPINT5_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DOEPINT5_PKTDRPSTS_OFFSET 0xba8
+#define GC_USB_DOEPINT5_BBLEERR_LSB 0xc
+#define GC_USB_DOEPINT5_BBLEERR_MASK 0x1000
+#define GC_USB_DOEPINT5_BBLEERR_SIZE 0x1
+#define GC_USB_DOEPINT5_BBLEERR_DEFAULT 0x0
+#define GC_USB_DOEPINT5_BBLEERR_OFFSET 0xba8
+#define GC_USB_DOEPINT5_NAKINTRPT_LSB 0xd
+#define GC_USB_DOEPINT5_NAKINTRPT_MASK 0x2000
+#define GC_USB_DOEPINT5_NAKINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT5_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT5_NAKINTRPT_OFFSET 0xba8
+#define GC_USB_DOEPINT5_NYETINTRPT_LSB 0xe
+#define GC_USB_DOEPINT5_NYETINTRPT_MASK 0x4000
+#define GC_USB_DOEPINT5_NYETINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT5_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT5_NYETINTRPT_OFFSET 0xba8
+#define GC_USB_DOEPINT5_STUPPKTRCVD_LSB 0xf
+#define GC_USB_DOEPINT5_STUPPKTRCVD_MASK 0x8000
+#define GC_USB_DOEPINT5_STUPPKTRCVD_SIZE 0x1
+#define GC_USB_DOEPINT5_STUPPKTRCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT5_STUPPKTRCVD_OFFSET 0xba8
+#define GC_USB_DOEPTSIZ5_XFERSIZE_LSB 0x0
+#define GC_USB_DOEPTSIZ5_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DOEPTSIZ5_XFERSIZE_SIZE 0x13
+#define GC_USB_DOEPTSIZ5_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ5_XFERSIZE_OFFSET 0xbb0
+#define GC_USB_DOEPTSIZ5_PKTCNT_LSB 0x13
+#define GC_USB_DOEPTSIZ5_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DOEPTSIZ5_PKTCNT_SIZE 0xa
+#define GC_USB_DOEPTSIZ5_PKTCNT_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ5_PKTCNT_OFFSET 0xbb0
+#define GC_USB_DOEPTSIZ5_RXDPID_LSB 0x1d
+#define GC_USB_DOEPTSIZ5_RXDPID_MASK 0x60000000
+#define GC_USB_DOEPTSIZ5_RXDPID_SIZE 0x2
+#define GC_USB_DOEPTSIZ5_RXDPID_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ5_RXDPID_OFFSET 0xbb0
+#define GC_USB_DOEPDMA5_DMAADDR_LSB 0x0
+#define GC_USB_DOEPDMA5_DMAADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMA5_DMAADDR_SIZE 0x20
+#define GC_USB_DOEPDMA5_DMAADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMA5_DMAADDR_OFFSET 0xbb4
+#define GC_USB_DOEPDMAB5_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DOEPDMAB5_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMAB5_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DOEPDMAB5_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMAB5_DMABUFFERADDR_OFFSET 0xbbc
+#define GC_USB_DOEPCTL6_MPS_LSB 0x0
+#define GC_USB_DOEPCTL6_MPS_MASK 0x7ff
+#define GC_USB_DOEPCTL6_MPS_SIZE 0xb
+#define GC_USB_DOEPCTL6_MPS_DEFAULT 0x0
+#define GC_USB_DOEPCTL6_MPS_OFFSET 0xbc0
+#define GC_USB_DOEPCTL6_USBACTEP_LSB 0xf
+#define GC_USB_DOEPCTL6_USBACTEP_MASK 0x8000
+#define GC_USB_DOEPCTL6_USBACTEP_SIZE 0x1
+#define GC_USB_DOEPCTL6_USBACTEP_DEFAULT 0x0
+#define GC_USB_DOEPCTL6_USBACTEP_OFFSET 0xbc0
+#define GC_USB_DOEPCTL6_DPID_LSB 0x10
+#define GC_USB_DOEPCTL6_DPID_MASK 0x10000
+#define GC_USB_DOEPCTL6_DPID_SIZE 0x1
+#define GC_USB_DOEPCTL6_DPID_DEFAULT 0x0
+#define GC_USB_DOEPCTL6_DPID_OFFSET 0xbc0
+#define GC_USB_DOEPCTL6_NAKSTS_LSB 0x11
+#define GC_USB_DOEPCTL6_NAKSTS_MASK 0x20000
+#define GC_USB_DOEPCTL6_NAKSTS_SIZE 0x1
+#define GC_USB_DOEPCTL6_NAKSTS_DEFAULT 0x0
+#define GC_USB_DOEPCTL6_NAKSTS_OFFSET 0xbc0
+#define GC_USB_DOEPCTL6_EPTYPE_LSB 0x12
+#define GC_USB_DOEPCTL6_EPTYPE_MASK 0xc0000
+#define GC_USB_DOEPCTL6_EPTYPE_SIZE 0x2
+#define GC_USB_DOEPCTL6_EPTYPE_DEFAULT 0x0
+#define GC_USB_DOEPCTL6_EPTYPE_OFFSET 0xbc0
+#define GC_USB_DOEPCTL6_SNP_LSB 0x14
+#define GC_USB_DOEPCTL6_SNP_MASK 0x100000
+#define GC_USB_DOEPCTL6_SNP_SIZE 0x1
+#define GC_USB_DOEPCTL6_SNP_DEFAULT 0x0
+#define GC_USB_DOEPCTL6_SNP_OFFSET 0xbc0
+#define GC_USB_DOEPCTL6_STALL_LSB 0x15
+#define GC_USB_DOEPCTL6_STALL_MASK 0x200000
+#define GC_USB_DOEPCTL6_STALL_SIZE 0x1
+#define GC_USB_DOEPCTL6_STALL_DEFAULT 0x0
+#define GC_USB_DOEPCTL6_STALL_OFFSET 0xbc0
+#define GC_USB_DOEPCTL6_CNAK_LSB 0x1a
+#define GC_USB_DOEPCTL6_CNAK_MASK 0x4000000
+#define GC_USB_DOEPCTL6_CNAK_SIZE 0x1
+#define GC_USB_DOEPCTL6_CNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL6_CNAK_OFFSET 0xbc0
+#define GC_USB_DOEPCTL6_SNAK_LSB 0x1b
+#define GC_USB_DOEPCTL6_SNAK_MASK 0x8000000
+#define GC_USB_DOEPCTL6_SNAK_SIZE 0x1
+#define GC_USB_DOEPCTL6_SNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL6_SNAK_OFFSET 0xbc0
+#define GC_USB_DOEPCTL6_SETD0PID_LSB 0x1c
+#define GC_USB_DOEPCTL6_SETD0PID_MASK 0x10000000
+#define GC_USB_DOEPCTL6_SETD0PID_SIZE 0x1
+#define GC_USB_DOEPCTL6_SETD0PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL6_SETD0PID_OFFSET 0xbc0
+#define GC_USB_DOEPCTL6_SETD1PID_LSB 0x1d
+#define GC_USB_DOEPCTL6_SETD1PID_MASK 0x20000000
+#define GC_USB_DOEPCTL6_SETD1PID_SIZE 0x1
+#define GC_USB_DOEPCTL6_SETD1PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL6_SETD1PID_OFFSET 0xbc0
+#define GC_USB_DOEPCTL6_EPDIS_LSB 0x1e
+#define GC_USB_DOEPCTL6_EPDIS_MASK 0x40000000
+#define GC_USB_DOEPCTL6_EPDIS_SIZE 0x1
+#define GC_USB_DOEPCTL6_EPDIS_DEFAULT 0x0
+#define GC_USB_DOEPCTL6_EPDIS_OFFSET 0xbc0
+#define GC_USB_DOEPCTL6_EPENA_LSB 0x1f
+#define GC_USB_DOEPCTL6_EPENA_MASK 0x80000000
+#define GC_USB_DOEPCTL6_EPENA_SIZE 0x1
+#define GC_USB_DOEPCTL6_EPENA_DEFAULT 0x0
+#define GC_USB_DOEPCTL6_EPENA_OFFSET 0xbc0
+#define GC_USB_DOEPINT6_XFERCOMPL_LSB 0x0
+#define GC_USB_DOEPINT6_XFERCOMPL_MASK 0x1
+#define GC_USB_DOEPINT6_XFERCOMPL_SIZE 0x1
+#define GC_USB_DOEPINT6_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DOEPINT6_XFERCOMPL_OFFSET 0xbc8
+#define GC_USB_DOEPINT6_EPDISBLD_LSB 0x1
+#define GC_USB_DOEPINT6_EPDISBLD_MASK 0x2
+#define GC_USB_DOEPINT6_EPDISBLD_SIZE 0x1
+#define GC_USB_DOEPINT6_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DOEPINT6_EPDISBLD_OFFSET 0xbc8
+#define GC_USB_DOEPINT6_AHBERR_LSB 0x2
+#define GC_USB_DOEPINT6_AHBERR_MASK 0x4
+#define GC_USB_DOEPINT6_AHBERR_SIZE 0x1
+#define GC_USB_DOEPINT6_AHBERR_DEFAULT 0x0
+#define GC_USB_DOEPINT6_AHBERR_OFFSET 0xbc8
+#define GC_USB_DOEPINT6_SETUP_LSB 0x3
+#define GC_USB_DOEPINT6_SETUP_MASK 0x8
+#define GC_USB_DOEPINT6_SETUP_SIZE 0x1
+#define GC_USB_DOEPINT6_SETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT6_SETUP_OFFSET 0xbc8
+#define GC_USB_DOEPINT6_OUTTKNEPDIS_LSB 0x4
+#define GC_USB_DOEPINT6_OUTTKNEPDIS_MASK 0x10
+#define GC_USB_DOEPINT6_OUTTKNEPDIS_SIZE 0x1
+#define GC_USB_DOEPINT6_OUTTKNEPDIS_DEFAULT 0x0
+#define GC_USB_DOEPINT6_OUTTKNEPDIS_OFFSET 0xbc8
+#define GC_USB_DOEPINT6_STSPHSERCVD_LSB 0x5
+#define GC_USB_DOEPINT6_STSPHSERCVD_MASK 0x20
+#define GC_USB_DOEPINT6_STSPHSERCVD_SIZE 0x1
+#define GC_USB_DOEPINT6_STSPHSERCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT6_STSPHSERCVD_OFFSET 0xbc8
+#define GC_USB_DOEPINT6_BACK2BACKSETUP_LSB 0x6
+#define GC_USB_DOEPINT6_BACK2BACKSETUP_MASK 0x40
+#define GC_USB_DOEPINT6_BACK2BACKSETUP_SIZE 0x1
+#define GC_USB_DOEPINT6_BACK2BACKSETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT6_BACK2BACKSETUP_OFFSET 0xbc8
+#define GC_USB_DOEPINT6_OUTPKTERR_LSB 0x8
+#define GC_USB_DOEPINT6_OUTPKTERR_MASK 0x100
+#define GC_USB_DOEPINT6_OUTPKTERR_SIZE 0x1
+#define GC_USB_DOEPINT6_OUTPKTERR_DEFAULT 0x0
+#define GC_USB_DOEPINT6_OUTPKTERR_OFFSET 0xbc8
+#define GC_USB_DOEPINT6_BNAINTR_LSB 0x9
+#define GC_USB_DOEPINT6_BNAINTR_MASK 0x200
+#define GC_USB_DOEPINT6_BNAINTR_SIZE 0x1
+#define GC_USB_DOEPINT6_BNAINTR_DEFAULT 0x0
+#define GC_USB_DOEPINT6_BNAINTR_OFFSET 0xbc8
+#define GC_USB_DOEPINT6_PKTDRPSTS_LSB 0xb
+#define GC_USB_DOEPINT6_PKTDRPSTS_MASK 0x800
+#define GC_USB_DOEPINT6_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DOEPINT6_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DOEPINT6_PKTDRPSTS_OFFSET 0xbc8
+#define GC_USB_DOEPINT6_BBLEERR_LSB 0xc
+#define GC_USB_DOEPINT6_BBLEERR_MASK 0x1000
+#define GC_USB_DOEPINT6_BBLEERR_SIZE 0x1
+#define GC_USB_DOEPINT6_BBLEERR_DEFAULT 0x0
+#define GC_USB_DOEPINT6_BBLEERR_OFFSET 0xbc8
+#define GC_USB_DOEPINT6_NAKINTRPT_LSB 0xd
+#define GC_USB_DOEPINT6_NAKINTRPT_MASK 0x2000
+#define GC_USB_DOEPINT6_NAKINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT6_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT6_NAKINTRPT_OFFSET 0xbc8
+#define GC_USB_DOEPINT6_NYETINTRPT_LSB 0xe
+#define GC_USB_DOEPINT6_NYETINTRPT_MASK 0x4000
+#define GC_USB_DOEPINT6_NYETINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT6_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT6_NYETINTRPT_OFFSET 0xbc8
+#define GC_USB_DOEPINT6_STUPPKTRCVD_LSB 0xf
+#define GC_USB_DOEPINT6_STUPPKTRCVD_MASK 0x8000
+#define GC_USB_DOEPINT6_STUPPKTRCVD_SIZE 0x1
+#define GC_USB_DOEPINT6_STUPPKTRCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT6_STUPPKTRCVD_OFFSET 0xbc8
+#define GC_USB_DOEPTSIZ6_XFERSIZE_LSB 0x0
+#define GC_USB_DOEPTSIZ6_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DOEPTSIZ6_XFERSIZE_SIZE 0x13
+#define GC_USB_DOEPTSIZ6_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ6_XFERSIZE_OFFSET 0xbd0
+#define GC_USB_DOEPTSIZ6_PKTCNT_LSB 0x13
+#define GC_USB_DOEPTSIZ6_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DOEPTSIZ6_PKTCNT_SIZE 0xa
+#define GC_USB_DOEPTSIZ6_PKTCNT_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ6_PKTCNT_OFFSET 0xbd0
+#define GC_USB_DOEPTSIZ6_RXDPID_LSB 0x1d
+#define GC_USB_DOEPTSIZ6_RXDPID_MASK 0x60000000
+#define GC_USB_DOEPTSIZ6_RXDPID_SIZE 0x2
+#define GC_USB_DOEPTSIZ6_RXDPID_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ6_RXDPID_OFFSET 0xbd0
+#define GC_USB_DOEPDMA6_DMAADDR_LSB 0x0
+#define GC_USB_DOEPDMA6_DMAADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMA6_DMAADDR_SIZE 0x20
+#define GC_USB_DOEPDMA6_DMAADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMA6_DMAADDR_OFFSET 0xbd4
+#define GC_USB_DOEPDMAB6_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DOEPDMAB6_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMAB6_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DOEPDMAB6_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMAB6_DMABUFFERADDR_OFFSET 0xbdc
+#define GC_USB_DOEPCTL7_MPS_LSB 0x0
+#define GC_USB_DOEPCTL7_MPS_MASK 0x7ff
+#define GC_USB_DOEPCTL7_MPS_SIZE 0xb
+#define GC_USB_DOEPCTL7_MPS_DEFAULT 0x0
+#define GC_USB_DOEPCTL7_MPS_OFFSET 0xbe0
+#define GC_USB_DOEPCTL7_USBACTEP_LSB 0xf
+#define GC_USB_DOEPCTL7_USBACTEP_MASK 0x8000
+#define GC_USB_DOEPCTL7_USBACTEP_SIZE 0x1
+#define GC_USB_DOEPCTL7_USBACTEP_DEFAULT 0x0
+#define GC_USB_DOEPCTL7_USBACTEP_OFFSET 0xbe0
+#define GC_USB_DOEPCTL7_DPID_LSB 0x10
+#define GC_USB_DOEPCTL7_DPID_MASK 0x10000
+#define GC_USB_DOEPCTL7_DPID_SIZE 0x1
+#define GC_USB_DOEPCTL7_DPID_DEFAULT 0x0
+#define GC_USB_DOEPCTL7_DPID_OFFSET 0xbe0
+#define GC_USB_DOEPCTL7_NAKSTS_LSB 0x11
+#define GC_USB_DOEPCTL7_NAKSTS_MASK 0x20000
+#define GC_USB_DOEPCTL7_NAKSTS_SIZE 0x1
+#define GC_USB_DOEPCTL7_NAKSTS_DEFAULT 0x0
+#define GC_USB_DOEPCTL7_NAKSTS_OFFSET 0xbe0
+#define GC_USB_DOEPCTL7_EPTYPE_LSB 0x12
+#define GC_USB_DOEPCTL7_EPTYPE_MASK 0xc0000
+#define GC_USB_DOEPCTL7_EPTYPE_SIZE 0x2
+#define GC_USB_DOEPCTL7_EPTYPE_DEFAULT 0x0
+#define GC_USB_DOEPCTL7_EPTYPE_OFFSET 0xbe0
+#define GC_USB_DOEPCTL7_SNP_LSB 0x14
+#define GC_USB_DOEPCTL7_SNP_MASK 0x100000
+#define GC_USB_DOEPCTL7_SNP_SIZE 0x1
+#define GC_USB_DOEPCTL7_SNP_DEFAULT 0x0
+#define GC_USB_DOEPCTL7_SNP_OFFSET 0xbe0
+#define GC_USB_DOEPCTL7_STALL_LSB 0x15
+#define GC_USB_DOEPCTL7_STALL_MASK 0x200000
+#define GC_USB_DOEPCTL7_STALL_SIZE 0x1
+#define GC_USB_DOEPCTL7_STALL_DEFAULT 0x0
+#define GC_USB_DOEPCTL7_STALL_OFFSET 0xbe0
+#define GC_USB_DOEPCTL7_CNAK_LSB 0x1a
+#define GC_USB_DOEPCTL7_CNAK_MASK 0x4000000
+#define GC_USB_DOEPCTL7_CNAK_SIZE 0x1
+#define GC_USB_DOEPCTL7_CNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL7_CNAK_OFFSET 0xbe0
+#define GC_USB_DOEPCTL7_SNAK_LSB 0x1b
+#define GC_USB_DOEPCTL7_SNAK_MASK 0x8000000
+#define GC_USB_DOEPCTL7_SNAK_SIZE 0x1
+#define GC_USB_DOEPCTL7_SNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL7_SNAK_OFFSET 0xbe0
+#define GC_USB_DOEPCTL7_SETD0PID_LSB 0x1c
+#define GC_USB_DOEPCTL7_SETD0PID_MASK 0x10000000
+#define GC_USB_DOEPCTL7_SETD0PID_SIZE 0x1
+#define GC_USB_DOEPCTL7_SETD0PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL7_SETD0PID_OFFSET 0xbe0
+#define GC_USB_DOEPCTL7_SETD1PID_LSB 0x1d
+#define GC_USB_DOEPCTL7_SETD1PID_MASK 0x20000000
+#define GC_USB_DOEPCTL7_SETD1PID_SIZE 0x1
+#define GC_USB_DOEPCTL7_SETD1PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL7_SETD1PID_OFFSET 0xbe0
+#define GC_USB_DOEPCTL7_EPDIS_LSB 0x1e
+#define GC_USB_DOEPCTL7_EPDIS_MASK 0x40000000
+#define GC_USB_DOEPCTL7_EPDIS_SIZE 0x1
+#define GC_USB_DOEPCTL7_EPDIS_DEFAULT 0x0
+#define GC_USB_DOEPCTL7_EPDIS_OFFSET 0xbe0
+#define GC_USB_DOEPCTL7_EPENA_LSB 0x1f
+#define GC_USB_DOEPCTL7_EPENA_MASK 0x80000000
+#define GC_USB_DOEPCTL7_EPENA_SIZE 0x1
+#define GC_USB_DOEPCTL7_EPENA_DEFAULT 0x0
+#define GC_USB_DOEPCTL7_EPENA_OFFSET 0xbe0
+#define GC_USB_DOEPINT7_XFERCOMPL_LSB 0x0
+#define GC_USB_DOEPINT7_XFERCOMPL_MASK 0x1
+#define GC_USB_DOEPINT7_XFERCOMPL_SIZE 0x1
+#define GC_USB_DOEPINT7_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DOEPINT7_XFERCOMPL_OFFSET 0xbe8
+#define GC_USB_DOEPINT7_EPDISBLD_LSB 0x1
+#define GC_USB_DOEPINT7_EPDISBLD_MASK 0x2
+#define GC_USB_DOEPINT7_EPDISBLD_SIZE 0x1
+#define GC_USB_DOEPINT7_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DOEPINT7_EPDISBLD_OFFSET 0xbe8
+#define GC_USB_DOEPINT7_AHBERR_LSB 0x2
+#define GC_USB_DOEPINT7_AHBERR_MASK 0x4
+#define GC_USB_DOEPINT7_AHBERR_SIZE 0x1
+#define GC_USB_DOEPINT7_AHBERR_DEFAULT 0x0
+#define GC_USB_DOEPINT7_AHBERR_OFFSET 0xbe8
+#define GC_USB_DOEPINT7_SETUP_LSB 0x3
+#define GC_USB_DOEPINT7_SETUP_MASK 0x8
+#define GC_USB_DOEPINT7_SETUP_SIZE 0x1
+#define GC_USB_DOEPINT7_SETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT7_SETUP_OFFSET 0xbe8
+#define GC_USB_DOEPINT7_OUTTKNEPDIS_LSB 0x4
+#define GC_USB_DOEPINT7_OUTTKNEPDIS_MASK 0x10
+#define GC_USB_DOEPINT7_OUTTKNEPDIS_SIZE 0x1
+#define GC_USB_DOEPINT7_OUTTKNEPDIS_DEFAULT 0x0
+#define GC_USB_DOEPINT7_OUTTKNEPDIS_OFFSET 0xbe8
+#define GC_USB_DOEPINT7_STSPHSERCVD_LSB 0x5
+#define GC_USB_DOEPINT7_STSPHSERCVD_MASK 0x20
+#define GC_USB_DOEPINT7_STSPHSERCVD_SIZE 0x1
+#define GC_USB_DOEPINT7_STSPHSERCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT7_STSPHSERCVD_OFFSET 0xbe8
+#define GC_USB_DOEPINT7_BACK2BACKSETUP_LSB 0x6
+#define GC_USB_DOEPINT7_BACK2BACKSETUP_MASK 0x40
+#define GC_USB_DOEPINT7_BACK2BACKSETUP_SIZE 0x1
+#define GC_USB_DOEPINT7_BACK2BACKSETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT7_BACK2BACKSETUP_OFFSET 0xbe8
+#define GC_USB_DOEPINT7_OUTPKTERR_LSB 0x8
+#define GC_USB_DOEPINT7_OUTPKTERR_MASK 0x100
+#define GC_USB_DOEPINT7_OUTPKTERR_SIZE 0x1
+#define GC_USB_DOEPINT7_OUTPKTERR_DEFAULT 0x0
+#define GC_USB_DOEPINT7_OUTPKTERR_OFFSET 0xbe8
+#define GC_USB_DOEPINT7_BNAINTR_LSB 0x9
+#define GC_USB_DOEPINT7_BNAINTR_MASK 0x200
+#define GC_USB_DOEPINT7_BNAINTR_SIZE 0x1
+#define GC_USB_DOEPINT7_BNAINTR_DEFAULT 0x0
+#define GC_USB_DOEPINT7_BNAINTR_OFFSET 0xbe8
+#define GC_USB_DOEPINT7_PKTDRPSTS_LSB 0xb
+#define GC_USB_DOEPINT7_PKTDRPSTS_MASK 0x800
+#define GC_USB_DOEPINT7_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DOEPINT7_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DOEPINT7_PKTDRPSTS_OFFSET 0xbe8
+#define GC_USB_DOEPINT7_BBLEERR_LSB 0xc
+#define GC_USB_DOEPINT7_BBLEERR_MASK 0x1000
+#define GC_USB_DOEPINT7_BBLEERR_SIZE 0x1
+#define GC_USB_DOEPINT7_BBLEERR_DEFAULT 0x0
+#define GC_USB_DOEPINT7_BBLEERR_OFFSET 0xbe8
+#define GC_USB_DOEPINT7_NAKINTRPT_LSB 0xd
+#define GC_USB_DOEPINT7_NAKINTRPT_MASK 0x2000
+#define GC_USB_DOEPINT7_NAKINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT7_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT7_NAKINTRPT_OFFSET 0xbe8
+#define GC_USB_DOEPINT7_NYETINTRPT_LSB 0xe
+#define GC_USB_DOEPINT7_NYETINTRPT_MASK 0x4000
+#define GC_USB_DOEPINT7_NYETINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT7_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT7_NYETINTRPT_OFFSET 0xbe8
+#define GC_USB_DOEPINT7_STUPPKTRCVD_LSB 0xf
+#define GC_USB_DOEPINT7_STUPPKTRCVD_MASK 0x8000
+#define GC_USB_DOEPINT7_STUPPKTRCVD_SIZE 0x1
+#define GC_USB_DOEPINT7_STUPPKTRCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT7_STUPPKTRCVD_OFFSET 0xbe8
+#define GC_USB_DOEPTSIZ7_XFERSIZE_LSB 0x0
+#define GC_USB_DOEPTSIZ7_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DOEPTSIZ7_XFERSIZE_SIZE 0x13
+#define GC_USB_DOEPTSIZ7_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ7_XFERSIZE_OFFSET 0xbf0
+#define GC_USB_DOEPTSIZ7_PKTCNT_LSB 0x13
+#define GC_USB_DOEPTSIZ7_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DOEPTSIZ7_PKTCNT_SIZE 0xa
+#define GC_USB_DOEPTSIZ7_PKTCNT_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ7_PKTCNT_OFFSET 0xbf0
+#define GC_USB_DOEPTSIZ7_RXDPID_LSB 0x1d
+#define GC_USB_DOEPTSIZ7_RXDPID_MASK 0x60000000
+#define GC_USB_DOEPTSIZ7_RXDPID_SIZE 0x2
+#define GC_USB_DOEPTSIZ7_RXDPID_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ7_RXDPID_OFFSET 0xbf0
+#define GC_USB_DOEPDMA7_DMAADDR_LSB 0x0
+#define GC_USB_DOEPDMA7_DMAADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMA7_DMAADDR_SIZE 0x20
+#define GC_USB_DOEPDMA7_DMAADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMA7_DMAADDR_OFFSET 0xbf4
+#define GC_USB_DOEPDMAB7_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DOEPDMAB7_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMAB7_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DOEPDMAB7_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMAB7_DMABUFFERADDR_OFFSET 0xbfc
+#define GC_USB_DOEPCTL8_MPS_LSB 0x0
+#define GC_USB_DOEPCTL8_MPS_MASK 0x7ff
+#define GC_USB_DOEPCTL8_MPS_SIZE 0xb
+#define GC_USB_DOEPCTL8_MPS_DEFAULT 0x0
+#define GC_USB_DOEPCTL8_MPS_OFFSET 0xc00
+#define GC_USB_DOEPCTL8_USBACTEP_LSB 0xf
+#define GC_USB_DOEPCTL8_USBACTEP_MASK 0x8000
+#define GC_USB_DOEPCTL8_USBACTEP_SIZE 0x1
+#define GC_USB_DOEPCTL8_USBACTEP_DEFAULT 0x0
+#define GC_USB_DOEPCTL8_USBACTEP_OFFSET 0xc00
+#define GC_USB_DOEPCTL8_DPID_LSB 0x10
+#define GC_USB_DOEPCTL8_DPID_MASK 0x10000
+#define GC_USB_DOEPCTL8_DPID_SIZE 0x1
+#define GC_USB_DOEPCTL8_DPID_DEFAULT 0x0
+#define GC_USB_DOEPCTL8_DPID_OFFSET 0xc00
+#define GC_USB_DOEPCTL8_NAKSTS_LSB 0x11
+#define GC_USB_DOEPCTL8_NAKSTS_MASK 0x20000
+#define GC_USB_DOEPCTL8_NAKSTS_SIZE 0x1
+#define GC_USB_DOEPCTL8_NAKSTS_DEFAULT 0x0
+#define GC_USB_DOEPCTL8_NAKSTS_OFFSET 0xc00
+#define GC_USB_DOEPCTL8_EPTYPE_LSB 0x12
+#define GC_USB_DOEPCTL8_EPTYPE_MASK 0xc0000
+#define GC_USB_DOEPCTL8_EPTYPE_SIZE 0x2
+#define GC_USB_DOEPCTL8_EPTYPE_DEFAULT 0x0
+#define GC_USB_DOEPCTL8_EPTYPE_OFFSET 0xc00
+#define GC_USB_DOEPCTL8_SNP_LSB 0x14
+#define GC_USB_DOEPCTL8_SNP_MASK 0x100000
+#define GC_USB_DOEPCTL8_SNP_SIZE 0x1
+#define GC_USB_DOEPCTL8_SNP_DEFAULT 0x0
+#define GC_USB_DOEPCTL8_SNP_OFFSET 0xc00
+#define GC_USB_DOEPCTL8_STALL_LSB 0x15
+#define GC_USB_DOEPCTL8_STALL_MASK 0x200000
+#define GC_USB_DOEPCTL8_STALL_SIZE 0x1
+#define GC_USB_DOEPCTL8_STALL_DEFAULT 0x0
+#define GC_USB_DOEPCTL8_STALL_OFFSET 0xc00
+#define GC_USB_DOEPCTL8_CNAK_LSB 0x1a
+#define GC_USB_DOEPCTL8_CNAK_MASK 0x4000000
+#define GC_USB_DOEPCTL8_CNAK_SIZE 0x1
+#define GC_USB_DOEPCTL8_CNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL8_CNAK_OFFSET 0xc00
+#define GC_USB_DOEPCTL8_SNAK_LSB 0x1b
+#define GC_USB_DOEPCTL8_SNAK_MASK 0x8000000
+#define GC_USB_DOEPCTL8_SNAK_SIZE 0x1
+#define GC_USB_DOEPCTL8_SNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL8_SNAK_OFFSET 0xc00
+#define GC_USB_DOEPCTL8_SETD0PID_LSB 0x1c
+#define GC_USB_DOEPCTL8_SETD0PID_MASK 0x10000000
+#define GC_USB_DOEPCTL8_SETD0PID_SIZE 0x1
+#define GC_USB_DOEPCTL8_SETD0PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL8_SETD0PID_OFFSET 0xc00
+#define GC_USB_DOEPCTL8_SETD1PID_LSB 0x1d
+#define GC_USB_DOEPCTL8_SETD1PID_MASK 0x20000000
+#define GC_USB_DOEPCTL8_SETD1PID_SIZE 0x1
+#define GC_USB_DOEPCTL8_SETD1PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL8_SETD1PID_OFFSET 0xc00
+#define GC_USB_DOEPCTL8_EPDIS_LSB 0x1e
+#define GC_USB_DOEPCTL8_EPDIS_MASK 0x40000000
+#define GC_USB_DOEPCTL8_EPDIS_SIZE 0x1
+#define GC_USB_DOEPCTL8_EPDIS_DEFAULT 0x0
+#define GC_USB_DOEPCTL8_EPDIS_OFFSET 0xc00
+#define GC_USB_DOEPCTL8_EPENA_LSB 0x1f
+#define GC_USB_DOEPCTL8_EPENA_MASK 0x80000000
+#define GC_USB_DOEPCTL8_EPENA_SIZE 0x1
+#define GC_USB_DOEPCTL8_EPENA_DEFAULT 0x0
+#define GC_USB_DOEPCTL8_EPENA_OFFSET 0xc00
+#define GC_USB_DOEPINT8_XFERCOMPL_LSB 0x0
+#define GC_USB_DOEPINT8_XFERCOMPL_MASK 0x1
+#define GC_USB_DOEPINT8_XFERCOMPL_SIZE 0x1
+#define GC_USB_DOEPINT8_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DOEPINT8_XFERCOMPL_OFFSET 0xc08
+#define GC_USB_DOEPINT8_EPDISBLD_LSB 0x1
+#define GC_USB_DOEPINT8_EPDISBLD_MASK 0x2
+#define GC_USB_DOEPINT8_EPDISBLD_SIZE 0x1
+#define GC_USB_DOEPINT8_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DOEPINT8_EPDISBLD_OFFSET 0xc08
+#define GC_USB_DOEPINT8_AHBERR_LSB 0x2
+#define GC_USB_DOEPINT8_AHBERR_MASK 0x4
+#define GC_USB_DOEPINT8_AHBERR_SIZE 0x1
+#define GC_USB_DOEPINT8_AHBERR_DEFAULT 0x0
+#define GC_USB_DOEPINT8_AHBERR_OFFSET 0xc08
+#define GC_USB_DOEPINT8_SETUP_LSB 0x3
+#define GC_USB_DOEPINT8_SETUP_MASK 0x8
+#define GC_USB_DOEPINT8_SETUP_SIZE 0x1
+#define GC_USB_DOEPINT8_SETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT8_SETUP_OFFSET 0xc08
+#define GC_USB_DOEPINT8_OUTTKNEPDIS_LSB 0x4
+#define GC_USB_DOEPINT8_OUTTKNEPDIS_MASK 0x10
+#define GC_USB_DOEPINT8_OUTTKNEPDIS_SIZE 0x1
+#define GC_USB_DOEPINT8_OUTTKNEPDIS_DEFAULT 0x0
+#define GC_USB_DOEPINT8_OUTTKNEPDIS_OFFSET 0xc08
+#define GC_USB_DOEPINT8_STSPHSERCVD_LSB 0x5
+#define GC_USB_DOEPINT8_STSPHSERCVD_MASK 0x20
+#define GC_USB_DOEPINT8_STSPHSERCVD_SIZE 0x1
+#define GC_USB_DOEPINT8_STSPHSERCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT8_STSPHSERCVD_OFFSET 0xc08
+#define GC_USB_DOEPINT8_BACK2BACKSETUP_LSB 0x6
+#define GC_USB_DOEPINT8_BACK2BACKSETUP_MASK 0x40
+#define GC_USB_DOEPINT8_BACK2BACKSETUP_SIZE 0x1
+#define GC_USB_DOEPINT8_BACK2BACKSETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT8_BACK2BACKSETUP_OFFSET 0xc08
+#define GC_USB_DOEPINT8_OUTPKTERR_LSB 0x8
+#define GC_USB_DOEPINT8_OUTPKTERR_MASK 0x100
+#define GC_USB_DOEPINT8_OUTPKTERR_SIZE 0x1
+#define GC_USB_DOEPINT8_OUTPKTERR_DEFAULT 0x0
+#define GC_USB_DOEPINT8_OUTPKTERR_OFFSET 0xc08
+#define GC_USB_DOEPINT8_BNAINTR_LSB 0x9
+#define GC_USB_DOEPINT8_BNAINTR_MASK 0x200
+#define GC_USB_DOEPINT8_BNAINTR_SIZE 0x1
+#define GC_USB_DOEPINT8_BNAINTR_DEFAULT 0x0
+#define GC_USB_DOEPINT8_BNAINTR_OFFSET 0xc08
+#define GC_USB_DOEPINT8_PKTDRPSTS_LSB 0xb
+#define GC_USB_DOEPINT8_PKTDRPSTS_MASK 0x800
+#define GC_USB_DOEPINT8_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DOEPINT8_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DOEPINT8_PKTDRPSTS_OFFSET 0xc08
+#define GC_USB_DOEPINT8_BBLEERR_LSB 0xc
+#define GC_USB_DOEPINT8_BBLEERR_MASK 0x1000
+#define GC_USB_DOEPINT8_BBLEERR_SIZE 0x1
+#define GC_USB_DOEPINT8_BBLEERR_DEFAULT 0x0
+#define GC_USB_DOEPINT8_BBLEERR_OFFSET 0xc08
+#define GC_USB_DOEPINT8_NAKINTRPT_LSB 0xd
+#define GC_USB_DOEPINT8_NAKINTRPT_MASK 0x2000
+#define GC_USB_DOEPINT8_NAKINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT8_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT8_NAKINTRPT_OFFSET 0xc08
+#define GC_USB_DOEPINT8_NYETINTRPT_LSB 0xe
+#define GC_USB_DOEPINT8_NYETINTRPT_MASK 0x4000
+#define GC_USB_DOEPINT8_NYETINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT8_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT8_NYETINTRPT_OFFSET 0xc08
+#define GC_USB_DOEPINT8_STUPPKTRCVD_LSB 0xf
+#define GC_USB_DOEPINT8_STUPPKTRCVD_MASK 0x8000
+#define GC_USB_DOEPINT8_STUPPKTRCVD_SIZE 0x1
+#define GC_USB_DOEPINT8_STUPPKTRCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT8_STUPPKTRCVD_OFFSET 0xc08
+#define GC_USB_DOEPTSIZ8_XFERSIZE_LSB 0x0
+#define GC_USB_DOEPTSIZ8_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DOEPTSIZ8_XFERSIZE_SIZE 0x13
+#define GC_USB_DOEPTSIZ8_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ8_XFERSIZE_OFFSET 0xc10
+#define GC_USB_DOEPTSIZ8_PKTCNT_LSB 0x13
+#define GC_USB_DOEPTSIZ8_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DOEPTSIZ8_PKTCNT_SIZE 0xa
+#define GC_USB_DOEPTSIZ8_PKTCNT_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ8_PKTCNT_OFFSET 0xc10
+#define GC_USB_DOEPTSIZ8_RXDPID_LSB 0x1d
+#define GC_USB_DOEPTSIZ8_RXDPID_MASK 0x60000000
+#define GC_USB_DOEPTSIZ8_RXDPID_SIZE 0x2
+#define GC_USB_DOEPTSIZ8_RXDPID_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ8_RXDPID_OFFSET 0xc10
+#define GC_USB_DOEPDMA8_DMAADDR_LSB 0x0
+#define GC_USB_DOEPDMA8_DMAADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMA8_DMAADDR_SIZE 0x20
+#define GC_USB_DOEPDMA8_DMAADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMA8_DMAADDR_OFFSET 0xc14
+#define GC_USB_DOEPDMAB8_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DOEPDMAB8_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMAB8_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DOEPDMAB8_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMAB8_DMABUFFERADDR_OFFSET 0xc1c
+#define GC_USB_DOEPCTL9_MPS_LSB 0x0
+#define GC_USB_DOEPCTL9_MPS_MASK 0x7ff
+#define GC_USB_DOEPCTL9_MPS_SIZE 0xb
+#define GC_USB_DOEPCTL9_MPS_DEFAULT 0x0
+#define GC_USB_DOEPCTL9_MPS_OFFSET 0xc20
+#define GC_USB_DOEPCTL9_USBACTEP_LSB 0xf
+#define GC_USB_DOEPCTL9_USBACTEP_MASK 0x8000
+#define GC_USB_DOEPCTL9_USBACTEP_SIZE 0x1
+#define GC_USB_DOEPCTL9_USBACTEP_DEFAULT 0x0
+#define GC_USB_DOEPCTL9_USBACTEP_OFFSET 0xc20
+#define GC_USB_DOEPCTL9_DPID_LSB 0x10
+#define GC_USB_DOEPCTL9_DPID_MASK 0x10000
+#define GC_USB_DOEPCTL9_DPID_SIZE 0x1
+#define GC_USB_DOEPCTL9_DPID_DEFAULT 0x0
+#define GC_USB_DOEPCTL9_DPID_OFFSET 0xc20
+#define GC_USB_DOEPCTL9_NAKSTS_LSB 0x11
+#define GC_USB_DOEPCTL9_NAKSTS_MASK 0x20000
+#define GC_USB_DOEPCTL9_NAKSTS_SIZE 0x1
+#define GC_USB_DOEPCTL9_NAKSTS_DEFAULT 0x0
+#define GC_USB_DOEPCTL9_NAKSTS_OFFSET 0xc20
+#define GC_USB_DOEPCTL9_EPTYPE_LSB 0x12
+#define GC_USB_DOEPCTL9_EPTYPE_MASK 0xc0000
+#define GC_USB_DOEPCTL9_EPTYPE_SIZE 0x2
+#define GC_USB_DOEPCTL9_EPTYPE_DEFAULT 0x0
+#define GC_USB_DOEPCTL9_EPTYPE_OFFSET 0xc20
+#define GC_USB_DOEPCTL9_SNP_LSB 0x14
+#define GC_USB_DOEPCTL9_SNP_MASK 0x100000
+#define GC_USB_DOEPCTL9_SNP_SIZE 0x1
+#define GC_USB_DOEPCTL9_SNP_DEFAULT 0x0
+#define GC_USB_DOEPCTL9_SNP_OFFSET 0xc20
+#define GC_USB_DOEPCTL9_STALL_LSB 0x15
+#define GC_USB_DOEPCTL9_STALL_MASK 0x200000
+#define GC_USB_DOEPCTL9_STALL_SIZE 0x1
+#define GC_USB_DOEPCTL9_STALL_DEFAULT 0x0
+#define GC_USB_DOEPCTL9_STALL_OFFSET 0xc20
+#define GC_USB_DOEPCTL9_CNAK_LSB 0x1a
+#define GC_USB_DOEPCTL9_CNAK_MASK 0x4000000
+#define GC_USB_DOEPCTL9_CNAK_SIZE 0x1
+#define GC_USB_DOEPCTL9_CNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL9_CNAK_OFFSET 0xc20
+#define GC_USB_DOEPCTL9_SNAK_LSB 0x1b
+#define GC_USB_DOEPCTL9_SNAK_MASK 0x8000000
+#define GC_USB_DOEPCTL9_SNAK_SIZE 0x1
+#define GC_USB_DOEPCTL9_SNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL9_SNAK_OFFSET 0xc20
+#define GC_USB_DOEPCTL9_SETD0PID_LSB 0x1c
+#define GC_USB_DOEPCTL9_SETD0PID_MASK 0x10000000
+#define GC_USB_DOEPCTL9_SETD0PID_SIZE 0x1
+#define GC_USB_DOEPCTL9_SETD0PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL9_SETD0PID_OFFSET 0xc20
+#define GC_USB_DOEPCTL9_SETD1PID_LSB 0x1d
+#define GC_USB_DOEPCTL9_SETD1PID_MASK 0x20000000
+#define GC_USB_DOEPCTL9_SETD1PID_SIZE 0x1
+#define GC_USB_DOEPCTL9_SETD1PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL9_SETD1PID_OFFSET 0xc20
+#define GC_USB_DOEPCTL9_EPDIS_LSB 0x1e
+#define GC_USB_DOEPCTL9_EPDIS_MASK 0x40000000
+#define GC_USB_DOEPCTL9_EPDIS_SIZE 0x1
+#define GC_USB_DOEPCTL9_EPDIS_DEFAULT 0x0
+#define GC_USB_DOEPCTL9_EPDIS_OFFSET 0xc20
+#define GC_USB_DOEPCTL9_EPENA_LSB 0x1f
+#define GC_USB_DOEPCTL9_EPENA_MASK 0x80000000
+#define GC_USB_DOEPCTL9_EPENA_SIZE 0x1
+#define GC_USB_DOEPCTL9_EPENA_DEFAULT 0x0
+#define GC_USB_DOEPCTL9_EPENA_OFFSET 0xc20
+#define GC_USB_DOEPINT9_XFERCOMPL_LSB 0x0
+#define GC_USB_DOEPINT9_XFERCOMPL_MASK 0x1
+#define GC_USB_DOEPINT9_XFERCOMPL_SIZE 0x1
+#define GC_USB_DOEPINT9_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DOEPINT9_XFERCOMPL_OFFSET 0xc28
+#define GC_USB_DOEPINT9_EPDISBLD_LSB 0x1
+#define GC_USB_DOEPINT9_EPDISBLD_MASK 0x2
+#define GC_USB_DOEPINT9_EPDISBLD_SIZE 0x1
+#define GC_USB_DOEPINT9_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DOEPINT9_EPDISBLD_OFFSET 0xc28
+#define GC_USB_DOEPINT9_AHBERR_LSB 0x2
+#define GC_USB_DOEPINT9_AHBERR_MASK 0x4
+#define GC_USB_DOEPINT9_AHBERR_SIZE 0x1
+#define GC_USB_DOEPINT9_AHBERR_DEFAULT 0x0
+#define GC_USB_DOEPINT9_AHBERR_OFFSET 0xc28
+#define GC_USB_DOEPINT9_SETUP_LSB 0x3
+#define GC_USB_DOEPINT9_SETUP_MASK 0x8
+#define GC_USB_DOEPINT9_SETUP_SIZE 0x1
+#define GC_USB_DOEPINT9_SETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT9_SETUP_OFFSET 0xc28
+#define GC_USB_DOEPINT9_OUTTKNEPDIS_LSB 0x4
+#define GC_USB_DOEPINT9_OUTTKNEPDIS_MASK 0x10
+#define GC_USB_DOEPINT9_OUTTKNEPDIS_SIZE 0x1
+#define GC_USB_DOEPINT9_OUTTKNEPDIS_DEFAULT 0x0
+#define GC_USB_DOEPINT9_OUTTKNEPDIS_OFFSET 0xc28
+#define GC_USB_DOEPINT9_STSPHSERCVD_LSB 0x5
+#define GC_USB_DOEPINT9_STSPHSERCVD_MASK 0x20
+#define GC_USB_DOEPINT9_STSPHSERCVD_SIZE 0x1
+#define GC_USB_DOEPINT9_STSPHSERCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT9_STSPHSERCVD_OFFSET 0xc28
+#define GC_USB_DOEPINT9_BACK2BACKSETUP_LSB 0x6
+#define GC_USB_DOEPINT9_BACK2BACKSETUP_MASK 0x40
+#define GC_USB_DOEPINT9_BACK2BACKSETUP_SIZE 0x1
+#define GC_USB_DOEPINT9_BACK2BACKSETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT9_BACK2BACKSETUP_OFFSET 0xc28
+#define GC_USB_DOEPINT9_OUTPKTERR_LSB 0x8
+#define GC_USB_DOEPINT9_OUTPKTERR_MASK 0x100
+#define GC_USB_DOEPINT9_OUTPKTERR_SIZE 0x1
+#define GC_USB_DOEPINT9_OUTPKTERR_DEFAULT 0x0
+#define GC_USB_DOEPINT9_OUTPKTERR_OFFSET 0xc28
+#define GC_USB_DOEPINT9_BNAINTR_LSB 0x9
+#define GC_USB_DOEPINT9_BNAINTR_MASK 0x200
+#define GC_USB_DOEPINT9_BNAINTR_SIZE 0x1
+#define GC_USB_DOEPINT9_BNAINTR_DEFAULT 0x0
+#define GC_USB_DOEPINT9_BNAINTR_OFFSET 0xc28
+#define GC_USB_DOEPINT9_PKTDRPSTS_LSB 0xb
+#define GC_USB_DOEPINT9_PKTDRPSTS_MASK 0x800
+#define GC_USB_DOEPINT9_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DOEPINT9_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DOEPINT9_PKTDRPSTS_OFFSET 0xc28
+#define GC_USB_DOEPINT9_BBLEERR_LSB 0xc
+#define GC_USB_DOEPINT9_BBLEERR_MASK 0x1000
+#define GC_USB_DOEPINT9_BBLEERR_SIZE 0x1
+#define GC_USB_DOEPINT9_BBLEERR_DEFAULT 0x0
+#define GC_USB_DOEPINT9_BBLEERR_OFFSET 0xc28
+#define GC_USB_DOEPINT9_NAKINTRPT_LSB 0xd
+#define GC_USB_DOEPINT9_NAKINTRPT_MASK 0x2000
+#define GC_USB_DOEPINT9_NAKINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT9_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT9_NAKINTRPT_OFFSET 0xc28
+#define GC_USB_DOEPINT9_NYETINTRPT_LSB 0xe
+#define GC_USB_DOEPINT9_NYETINTRPT_MASK 0x4000
+#define GC_USB_DOEPINT9_NYETINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT9_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT9_NYETINTRPT_OFFSET 0xc28
+#define GC_USB_DOEPINT9_STUPPKTRCVD_LSB 0xf
+#define GC_USB_DOEPINT9_STUPPKTRCVD_MASK 0x8000
+#define GC_USB_DOEPINT9_STUPPKTRCVD_SIZE 0x1
+#define GC_USB_DOEPINT9_STUPPKTRCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT9_STUPPKTRCVD_OFFSET 0xc28
+#define GC_USB_DOEPTSIZ9_XFERSIZE_LSB 0x0
+#define GC_USB_DOEPTSIZ9_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DOEPTSIZ9_XFERSIZE_SIZE 0x13
+#define GC_USB_DOEPTSIZ9_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ9_XFERSIZE_OFFSET 0xc30
+#define GC_USB_DOEPTSIZ9_PKTCNT_LSB 0x13
+#define GC_USB_DOEPTSIZ9_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DOEPTSIZ9_PKTCNT_SIZE 0xa
+#define GC_USB_DOEPTSIZ9_PKTCNT_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ9_PKTCNT_OFFSET 0xc30
+#define GC_USB_DOEPTSIZ9_RXDPID_LSB 0x1d
+#define GC_USB_DOEPTSIZ9_RXDPID_MASK 0x60000000
+#define GC_USB_DOEPTSIZ9_RXDPID_SIZE 0x2
+#define GC_USB_DOEPTSIZ9_RXDPID_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ9_RXDPID_OFFSET 0xc30
+#define GC_USB_DOEPDMA9_DMAADDR_LSB 0x0
+#define GC_USB_DOEPDMA9_DMAADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMA9_DMAADDR_SIZE 0x20
+#define GC_USB_DOEPDMA9_DMAADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMA9_DMAADDR_OFFSET 0xc34
+#define GC_USB_DOEPDMAB9_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DOEPDMAB9_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMAB9_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DOEPDMAB9_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMAB9_DMABUFFERADDR_OFFSET 0xc3c
+#define GC_USB_DOEPCTL10_MPS_LSB 0x0
+#define GC_USB_DOEPCTL10_MPS_MASK 0x7ff
+#define GC_USB_DOEPCTL10_MPS_SIZE 0xb
+#define GC_USB_DOEPCTL10_MPS_DEFAULT 0x0
+#define GC_USB_DOEPCTL10_MPS_OFFSET 0xc40
+#define GC_USB_DOEPCTL10_USBACTEP_LSB 0xf
+#define GC_USB_DOEPCTL10_USBACTEP_MASK 0x8000
+#define GC_USB_DOEPCTL10_USBACTEP_SIZE 0x1
+#define GC_USB_DOEPCTL10_USBACTEP_DEFAULT 0x0
+#define GC_USB_DOEPCTL10_USBACTEP_OFFSET 0xc40
+#define GC_USB_DOEPCTL10_DPID_LSB 0x10
+#define GC_USB_DOEPCTL10_DPID_MASK 0x10000
+#define GC_USB_DOEPCTL10_DPID_SIZE 0x1
+#define GC_USB_DOEPCTL10_DPID_DEFAULT 0x0
+#define GC_USB_DOEPCTL10_DPID_OFFSET 0xc40
+#define GC_USB_DOEPCTL10_NAKSTS_LSB 0x11
+#define GC_USB_DOEPCTL10_NAKSTS_MASK 0x20000
+#define GC_USB_DOEPCTL10_NAKSTS_SIZE 0x1
+#define GC_USB_DOEPCTL10_NAKSTS_DEFAULT 0x0
+#define GC_USB_DOEPCTL10_NAKSTS_OFFSET 0xc40
+#define GC_USB_DOEPCTL10_EPTYPE_LSB 0x12
+#define GC_USB_DOEPCTL10_EPTYPE_MASK 0xc0000
+#define GC_USB_DOEPCTL10_EPTYPE_SIZE 0x2
+#define GC_USB_DOEPCTL10_EPTYPE_DEFAULT 0x0
+#define GC_USB_DOEPCTL10_EPTYPE_OFFSET 0xc40
+#define GC_USB_DOEPCTL10_SNP_LSB 0x14
+#define GC_USB_DOEPCTL10_SNP_MASK 0x100000
+#define GC_USB_DOEPCTL10_SNP_SIZE 0x1
+#define GC_USB_DOEPCTL10_SNP_DEFAULT 0x0
+#define GC_USB_DOEPCTL10_SNP_OFFSET 0xc40
+#define GC_USB_DOEPCTL10_STALL_LSB 0x15
+#define GC_USB_DOEPCTL10_STALL_MASK 0x200000
+#define GC_USB_DOEPCTL10_STALL_SIZE 0x1
+#define GC_USB_DOEPCTL10_STALL_DEFAULT 0x0
+#define GC_USB_DOEPCTL10_STALL_OFFSET 0xc40
+#define GC_USB_DOEPCTL10_CNAK_LSB 0x1a
+#define GC_USB_DOEPCTL10_CNAK_MASK 0x4000000
+#define GC_USB_DOEPCTL10_CNAK_SIZE 0x1
+#define GC_USB_DOEPCTL10_CNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL10_CNAK_OFFSET 0xc40
+#define GC_USB_DOEPCTL10_SNAK_LSB 0x1b
+#define GC_USB_DOEPCTL10_SNAK_MASK 0x8000000
+#define GC_USB_DOEPCTL10_SNAK_SIZE 0x1
+#define GC_USB_DOEPCTL10_SNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL10_SNAK_OFFSET 0xc40
+#define GC_USB_DOEPCTL10_SETD0PID_LSB 0x1c
+#define GC_USB_DOEPCTL10_SETD0PID_MASK 0x10000000
+#define GC_USB_DOEPCTL10_SETD0PID_SIZE 0x1
+#define GC_USB_DOEPCTL10_SETD0PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL10_SETD0PID_OFFSET 0xc40
+#define GC_USB_DOEPCTL10_SETD1PID_LSB 0x1d
+#define GC_USB_DOEPCTL10_SETD1PID_MASK 0x20000000
+#define GC_USB_DOEPCTL10_SETD1PID_SIZE 0x1
+#define GC_USB_DOEPCTL10_SETD1PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL10_SETD1PID_OFFSET 0xc40
+#define GC_USB_DOEPCTL10_EPDIS_LSB 0x1e
+#define GC_USB_DOEPCTL10_EPDIS_MASK 0x40000000
+#define GC_USB_DOEPCTL10_EPDIS_SIZE 0x1
+#define GC_USB_DOEPCTL10_EPDIS_DEFAULT 0x0
+#define GC_USB_DOEPCTL10_EPDIS_OFFSET 0xc40
+#define GC_USB_DOEPCTL10_EPENA_LSB 0x1f
+#define GC_USB_DOEPCTL10_EPENA_MASK 0x80000000
+#define GC_USB_DOEPCTL10_EPENA_SIZE 0x1
+#define GC_USB_DOEPCTL10_EPENA_DEFAULT 0x0
+#define GC_USB_DOEPCTL10_EPENA_OFFSET 0xc40
+#define GC_USB_DOEPINT10_XFERCOMPL_LSB 0x0
+#define GC_USB_DOEPINT10_XFERCOMPL_MASK 0x1
+#define GC_USB_DOEPINT10_XFERCOMPL_SIZE 0x1
+#define GC_USB_DOEPINT10_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DOEPINT10_XFERCOMPL_OFFSET 0xc48
+#define GC_USB_DOEPINT10_EPDISBLD_LSB 0x1
+#define GC_USB_DOEPINT10_EPDISBLD_MASK 0x2
+#define GC_USB_DOEPINT10_EPDISBLD_SIZE 0x1
+#define GC_USB_DOEPINT10_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DOEPINT10_EPDISBLD_OFFSET 0xc48
+#define GC_USB_DOEPINT10_AHBERR_LSB 0x2
+#define GC_USB_DOEPINT10_AHBERR_MASK 0x4
+#define GC_USB_DOEPINT10_AHBERR_SIZE 0x1
+#define GC_USB_DOEPINT10_AHBERR_DEFAULT 0x0
+#define GC_USB_DOEPINT10_AHBERR_OFFSET 0xc48
+#define GC_USB_DOEPINT10_SETUP_LSB 0x3
+#define GC_USB_DOEPINT10_SETUP_MASK 0x8
+#define GC_USB_DOEPINT10_SETUP_SIZE 0x1
+#define GC_USB_DOEPINT10_SETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT10_SETUP_OFFSET 0xc48
+#define GC_USB_DOEPINT10_OUTTKNEPDIS_LSB 0x4
+#define GC_USB_DOEPINT10_OUTTKNEPDIS_MASK 0x10
+#define GC_USB_DOEPINT10_OUTTKNEPDIS_SIZE 0x1
+#define GC_USB_DOEPINT10_OUTTKNEPDIS_DEFAULT 0x0
+#define GC_USB_DOEPINT10_OUTTKNEPDIS_OFFSET 0xc48
+#define GC_USB_DOEPINT10_STSPHSERCVD_LSB 0x5
+#define GC_USB_DOEPINT10_STSPHSERCVD_MASK 0x20
+#define GC_USB_DOEPINT10_STSPHSERCVD_SIZE 0x1
+#define GC_USB_DOEPINT10_STSPHSERCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT10_STSPHSERCVD_OFFSET 0xc48
+#define GC_USB_DOEPINT10_BACK2BACKSETUP_LSB 0x6
+#define GC_USB_DOEPINT10_BACK2BACKSETUP_MASK 0x40
+#define GC_USB_DOEPINT10_BACK2BACKSETUP_SIZE 0x1
+#define GC_USB_DOEPINT10_BACK2BACKSETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT10_BACK2BACKSETUP_OFFSET 0xc48
+#define GC_USB_DOEPINT10_OUTPKTERR_LSB 0x8
+#define GC_USB_DOEPINT10_OUTPKTERR_MASK 0x100
+#define GC_USB_DOEPINT10_OUTPKTERR_SIZE 0x1
+#define GC_USB_DOEPINT10_OUTPKTERR_DEFAULT 0x0
+#define GC_USB_DOEPINT10_OUTPKTERR_OFFSET 0xc48
+#define GC_USB_DOEPINT10_BNAINTR_LSB 0x9
+#define GC_USB_DOEPINT10_BNAINTR_MASK 0x200
+#define GC_USB_DOEPINT10_BNAINTR_SIZE 0x1
+#define GC_USB_DOEPINT10_BNAINTR_DEFAULT 0x0
+#define GC_USB_DOEPINT10_BNAINTR_OFFSET 0xc48
+#define GC_USB_DOEPINT10_PKTDRPSTS_LSB 0xb
+#define GC_USB_DOEPINT10_PKTDRPSTS_MASK 0x800
+#define GC_USB_DOEPINT10_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DOEPINT10_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DOEPINT10_PKTDRPSTS_OFFSET 0xc48
+#define GC_USB_DOEPINT10_BBLEERR_LSB 0xc
+#define GC_USB_DOEPINT10_BBLEERR_MASK 0x1000
+#define GC_USB_DOEPINT10_BBLEERR_SIZE 0x1
+#define GC_USB_DOEPINT10_BBLEERR_DEFAULT 0x0
+#define GC_USB_DOEPINT10_BBLEERR_OFFSET 0xc48
+#define GC_USB_DOEPINT10_NAKINTRPT_LSB 0xd
+#define GC_USB_DOEPINT10_NAKINTRPT_MASK 0x2000
+#define GC_USB_DOEPINT10_NAKINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT10_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT10_NAKINTRPT_OFFSET 0xc48
+#define GC_USB_DOEPINT10_NYETINTRPT_LSB 0xe
+#define GC_USB_DOEPINT10_NYETINTRPT_MASK 0x4000
+#define GC_USB_DOEPINT10_NYETINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT10_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT10_NYETINTRPT_OFFSET 0xc48
+#define GC_USB_DOEPINT10_STUPPKTRCVD_LSB 0xf
+#define GC_USB_DOEPINT10_STUPPKTRCVD_MASK 0x8000
+#define GC_USB_DOEPINT10_STUPPKTRCVD_SIZE 0x1
+#define GC_USB_DOEPINT10_STUPPKTRCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT10_STUPPKTRCVD_OFFSET 0xc48
+#define GC_USB_DOEPTSIZ10_XFERSIZE_LSB 0x0
+#define GC_USB_DOEPTSIZ10_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DOEPTSIZ10_XFERSIZE_SIZE 0x13
+#define GC_USB_DOEPTSIZ10_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ10_XFERSIZE_OFFSET 0xc50
+#define GC_USB_DOEPTSIZ10_PKTCNT_LSB 0x13
+#define GC_USB_DOEPTSIZ10_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DOEPTSIZ10_PKTCNT_SIZE 0xa
+#define GC_USB_DOEPTSIZ10_PKTCNT_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ10_PKTCNT_OFFSET 0xc50
+#define GC_USB_DOEPTSIZ10_RXDPID_LSB 0x1d
+#define GC_USB_DOEPTSIZ10_RXDPID_MASK 0x60000000
+#define GC_USB_DOEPTSIZ10_RXDPID_SIZE 0x2
+#define GC_USB_DOEPTSIZ10_RXDPID_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ10_RXDPID_OFFSET 0xc50
+#define GC_USB_DOEPDMA10_DMAADDR_LSB 0x0
+#define GC_USB_DOEPDMA10_DMAADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMA10_DMAADDR_SIZE 0x20
+#define GC_USB_DOEPDMA10_DMAADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMA10_DMAADDR_OFFSET 0xc54
+#define GC_USB_DOEPDMAB10_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DOEPDMAB10_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMAB10_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DOEPDMAB10_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMAB10_DMABUFFERADDR_OFFSET 0xc5c
+#define GC_USB_DOEPCTL11_MPS_LSB 0x0
+#define GC_USB_DOEPCTL11_MPS_MASK 0x7ff
+#define GC_USB_DOEPCTL11_MPS_SIZE 0xb
+#define GC_USB_DOEPCTL11_MPS_DEFAULT 0x0
+#define GC_USB_DOEPCTL11_MPS_OFFSET 0xc60
+#define GC_USB_DOEPCTL11_USBACTEP_LSB 0xf
+#define GC_USB_DOEPCTL11_USBACTEP_MASK 0x8000
+#define GC_USB_DOEPCTL11_USBACTEP_SIZE 0x1
+#define GC_USB_DOEPCTL11_USBACTEP_DEFAULT 0x0
+#define GC_USB_DOEPCTL11_USBACTEP_OFFSET 0xc60
+#define GC_USB_DOEPCTL11_DPID_LSB 0x10
+#define GC_USB_DOEPCTL11_DPID_MASK 0x10000
+#define GC_USB_DOEPCTL11_DPID_SIZE 0x1
+#define GC_USB_DOEPCTL11_DPID_DEFAULT 0x0
+#define GC_USB_DOEPCTL11_DPID_OFFSET 0xc60
+#define GC_USB_DOEPCTL11_NAKSTS_LSB 0x11
+#define GC_USB_DOEPCTL11_NAKSTS_MASK 0x20000
+#define GC_USB_DOEPCTL11_NAKSTS_SIZE 0x1
+#define GC_USB_DOEPCTL11_NAKSTS_DEFAULT 0x0
+#define GC_USB_DOEPCTL11_NAKSTS_OFFSET 0xc60
+#define GC_USB_DOEPCTL11_EPTYPE_LSB 0x12
+#define GC_USB_DOEPCTL11_EPTYPE_MASK 0xc0000
+#define GC_USB_DOEPCTL11_EPTYPE_SIZE 0x2
+#define GC_USB_DOEPCTL11_EPTYPE_DEFAULT 0x0
+#define GC_USB_DOEPCTL11_EPTYPE_OFFSET 0xc60
+#define GC_USB_DOEPCTL11_SNP_LSB 0x14
+#define GC_USB_DOEPCTL11_SNP_MASK 0x100000
+#define GC_USB_DOEPCTL11_SNP_SIZE 0x1
+#define GC_USB_DOEPCTL11_SNP_DEFAULT 0x0
+#define GC_USB_DOEPCTL11_SNP_OFFSET 0xc60
+#define GC_USB_DOEPCTL11_STALL_LSB 0x15
+#define GC_USB_DOEPCTL11_STALL_MASK 0x200000
+#define GC_USB_DOEPCTL11_STALL_SIZE 0x1
+#define GC_USB_DOEPCTL11_STALL_DEFAULT 0x0
+#define GC_USB_DOEPCTL11_STALL_OFFSET 0xc60
+#define GC_USB_DOEPCTL11_CNAK_LSB 0x1a
+#define GC_USB_DOEPCTL11_CNAK_MASK 0x4000000
+#define GC_USB_DOEPCTL11_CNAK_SIZE 0x1
+#define GC_USB_DOEPCTL11_CNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL11_CNAK_OFFSET 0xc60
+#define GC_USB_DOEPCTL11_SNAK_LSB 0x1b
+#define GC_USB_DOEPCTL11_SNAK_MASK 0x8000000
+#define GC_USB_DOEPCTL11_SNAK_SIZE 0x1
+#define GC_USB_DOEPCTL11_SNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL11_SNAK_OFFSET 0xc60
+#define GC_USB_DOEPCTL11_SETD0PID_LSB 0x1c
+#define GC_USB_DOEPCTL11_SETD0PID_MASK 0x10000000
+#define GC_USB_DOEPCTL11_SETD0PID_SIZE 0x1
+#define GC_USB_DOEPCTL11_SETD0PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL11_SETD0PID_OFFSET 0xc60
+#define GC_USB_DOEPCTL11_SETD1PID_LSB 0x1d
+#define GC_USB_DOEPCTL11_SETD1PID_MASK 0x20000000
+#define GC_USB_DOEPCTL11_SETD1PID_SIZE 0x1
+#define GC_USB_DOEPCTL11_SETD1PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL11_SETD1PID_OFFSET 0xc60
+#define GC_USB_DOEPCTL11_EPDIS_LSB 0x1e
+#define GC_USB_DOEPCTL11_EPDIS_MASK 0x40000000
+#define GC_USB_DOEPCTL11_EPDIS_SIZE 0x1
+#define GC_USB_DOEPCTL11_EPDIS_DEFAULT 0x0
+#define GC_USB_DOEPCTL11_EPDIS_OFFSET 0xc60
+#define GC_USB_DOEPCTL11_EPENA_LSB 0x1f
+#define GC_USB_DOEPCTL11_EPENA_MASK 0x80000000
+#define GC_USB_DOEPCTL11_EPENA_SIZE 0x1
+#define GC_USB_DOEPCTL11_EPENA_DEFAULT 0x0
+#define GC_USB_DOEPCTL11_EPENA_OFFSET 0xc60
+#define GC_USB_DOEPINT11_XFERCOMPL_LSB 0x0
+#define GC_USB_DOEPINT11_XFERCOMPL_MASK 0x1
+#define GC_USB_DOEPINT11_XFERCOMPL_SIZE 0x1
+#define GC_USB_DOEPINT11_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DOEPINT11_XFERCOMPL_OFFSET 0xc68
+#define GC_USB_DOEPINT11_EPDISBLD_LSB 0x1
+#define GC_USB_DOEPINT11_EPDISBLD_MASK 0x2
+#define GC_USB_DOEPINT11_EPDISBLD_SIZE 0x1
+#define GC_USB_DOEPINT11_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DOEPINT11_EPDISBLD_OFFSET 0xc68
+#define GC_USB_DOEPINT11_AHBERR_LSB 0x2
+#define GC_USB_DOEPINT11_AHBERR_MASK 0x4
+#define GC_USB_DOEPINT11_AHBERR_SIZE 0x1
+#define GC_USB_DOEPINT11_AHBERR_DEFAULT 0x0
+#define GC_USB_DOEPINT11_AHBERR_OFFSET 0xc68
+#define GC_USB_DOEPINT11_SETUP_LSB 0x3
+#define GC_USB_DOEPINT11_SETUP_MASK 0x8
+#define GC_USB_DOEPINT11_SETUP_SIZE 0x1
+#define GC_USB_DOEPINT11_SETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT11_SETUP_OFFSET 0xc68
+#define GC_USB_DOEPINT11_OUTTKNEPDIS_LSB 0x4
+#define GC_USB_DOEPINT11_OUTTKNEPDIS_MASK 0x10
+#define GC_USB_DOEPINT11_OUTTKNEPDIS_SIZE 0x1
+#define GC_USB_DOEPINT11_OUTTKNEPDIS_DEFAULT 0x0
+#define GC_USB_DOEPINT11_OUTTKNEPDIS_OFFSET 0xc68
+#define GC_USB_DOEPINT11_STSPHSERCVD_LSB 0x5
+#define GC_USB_DOEPINT11_STSPHSERCVD_MASK 0x20
+#define GC_USB_DOEPINT11_STSPHSERCVD_SIZE 0x1
+#define GC_USB_DOEPINT11_STSPHSERCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT11_STSPHSERCVD_OFFSET 0xc68
+#define GC_USB_DOEPINT11_BACK2BACKSETUP_LSB 0x6
+#define GC_USB_DOEPINT11_BACK2BACKSETUP_MASK 0x40
+#define GC_USB_DOEPINT11_BACK2BACKSETUP_SIZE 0x1
+#define GC_USB_DOEPINT11_BACK2BACKSETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT11_BACK2BACKSETUP_OFFSET 0xc68
+#define GC_USB_DOEPINT11_OUTPKTERR_LSB 0x8
+#define GC_USB_DOEPINT11_OUTPKTERR_MASK 0x100
+#define GC_USB_DOEPINT11_OUTPKTERR_SIZE 0x1
+#define GC_USB_DOEPINT11_OUTPKTERR_DEFAULT 0x0
+#define GC_USB_DOEPINT11_OUTPKTERR_OFFSET 0xc68
+#define GC_USB_DOEPINT11_BNAINTR_LSB 0x9
+#define GC_USB_DOEPINT11_BNAINTR_MASK 0x200
+#define GC_USB_DOEPINT11_BNAINTR_SIZE 0x1
+#define GC_USB_DOEPINT11_BNAINTR_DEFAULT 0x0
+#define GC_USB_DOEPINT11_BNAINTR_OFFSET 0xc68
+#define GC_USB_DOEPINT11_PKTDRPSTS_LSB 0xb
+#define GC_USB_DOEPINT11_PKTDRPSTS_MASK 0x800
+#define GC_USB_DOEPINT11_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DOEPINT11_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DOEPINT11_PKTDRPSTS_OFFSET 0xc68
+#define GC_USB_DOEPINT11_BBLEERR_LSB 0xc
+#define GC_USB_DOEPINT11_BBLEERR_MASK 0x1000
+#define GC_USB_DOEPINT11_BBLEERR_SIZE 0x1
+#define GC_USB_DOEPINT11_BBLEERR_DEFAULT 0x0
+#define GC_USB_DOEPINT11_BBLEERR_OFFSET 0xc68
+#define GC_USB_DOEPINT11_NAKINTRPT_LSB 0xd
+#define GC_USB_DOEPINT11_NAKINTRPT_MASK 0x2000
+#define GC_USB_DOEPINT11_NAKINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT11_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT11_NAKINTRPT_OFFSET 0xc68
+#define GC_USB_DOEPINT11_NYETINTRPT_LSB 0xe
+#define GC_USB_DOEPINT11_NYETINTRPT_MASK 0x4000
+#define GC_USB_DOEPINT11_NYETINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT11_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT11_NYETINTRPT_OFFSET 0xc68
+#define GC_USB_DOEPINT11_STUPPKTRCVD_LSB 0xf
+#define GC_USB_DOEPINT11_STUPPKTRCVD_MASK 0x8000
+#define GC_USB_DOEPINT11_STUPPKTRCVD_SIZE 0x1
+#define GC_USB_DOEPINT11_STUPPKTRCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT11_STUPPKTRCVD_OFFSET 0xc68
+#define GC_USB_DOEPTSIZ11_XFERSIZE_LSB 0x0
+#define GC_USB_DOEPTSIZ11_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DOEPTSIZ11_XFERSIZE_SIZE 0x13
+#define GC_USB_DOEPTSIZ11_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ11_XFERSIZE_OFFSET 0xc70
+#define GC_USB_DOEPTSIZ11_PKTCNT_LSB 0x13
+#define GC_USB_DOEPTSIZ11_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DOEPTSIZ11_PKTCNT_SIZE 0xa
+#define GC_USB_DOEPTSIZ11_PKTCNT_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ11_PKTCNT_OFFSET 0xc70
+#define GC_USB_DOEPTSIZ11_RXDPID_LSB 0x1d
+#define GC_USB_DOEPTSIZ11_RXDPID_MASK 0x60000000
+#define GC_USB_DOEPTSIZ11_RXDPID_SIZE 0x2
+#define GC_USB_DOEPTSIZ11_RXDPID_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ11_RXDPID_OFFSET 0xc70
+#define GC_USB_DOEPDMA11_DMAADDR_LSB 0x0
+#define GC_USB_DOEPDMA11_DMAADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMA11_DMAADDR_SIZE 0x20
+#define GC_USB_DOEPDMA11_DMAADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMA11_DMAADDR_OFFSET 0xc74
+#define GC_USB_DOEPDMAB11_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DOEPDMAB11_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMAB11_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DOEPDMAB11_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMAB11_DMABUFFERADDR_OFFSET 0xc7c
+#define GC_USB_DOEPCTL12_MPS_LSB 0x0
+#define GC_USB_DOEPCTL12_MPS_MASK 0x7ff
+#define GC_USB_DOEPCTL12_MPS_SIZE 0xb
+#define GC_USB_DOEPCTL12_MPS_DEFAULT 0x0
+#define GC_USB_DOEPCTL12_MPS_OFFSET 0xc80
+#define GC_USB_DOEPCTL12_USBACTEP_LSB 0xf
+#define GC_USB_DOEPCTL12_USBACTEP_MASK 0x8000
+#define GC_USB_DOEPCTL12_USBACTEP_SIZE 0x1
+#define GC_USB_DOEPCTL12_USBACTEP_DEFAULT 0x0
+#define GC_USB_DOEPCTL12_USBACTEP_OFFSET 0xc80
+#define GC_USB_DOEPCTL12_DPID_LSB 0x10
+#define GC_USB_DOEPCTL12_DPID_MASK 0x10000
+#define GC_USB_DOEPCTL12_DPID_SIZE 0x1
+#define GC_USB_DOEPCTL12_DPID_DEFAULT 0x0
+#define GC_USB_DOEPCTL12_DPID_OFFSET 0xc80
+#define GC_USB_DOEPCTL12_NAKSTS_LSB 0x11
+#define GC_USB_DOEPCTL12_NAKSTS_MASK 0x20000
+#define GC_USB_DOEPCTL12_NAKSTS_SIZE 0x1
+#define GC_USB_DOEPCTL12_NAKSTS_DEFAULT 0x0
+#define GC_USB_DOEPCTL12_NAKSTS_OFFSET 0xc80
+#define GC_USB_DOEPCTL12_EPTYPE_LSB 0x12
+#define GC_USB_DOEPCTL12_EPTYPE_MASK 0xc0000
+#define GC_USB_DOEPCTL12_EPTYPE_SIZE 0x2
+#define GC_USB_DOEPCTL12_EPTYPE_DEFAULT 0x0
+#define GC_USB_DOEPCTL12_EPTYPE_OFFSET 0xc80
+#define GC_USB_DOEPCTL12_SNP_LSB 0x14
+#define GC_USB_DOEPCTL12_SNP_MASK 0x100000
+#define GC_USB_DOEPCTL12_SNP_SIZE 0x1
+#define GC_USB_DOEPCTL12_SNP_DEFAULT 0x0
+#define GC_USB_DOEPCTL12_SNP_OFFSET 0xc80
+#define GC_USB_DOEPCTL12_STALL_LSB 0x15
+#define GC_USB_DOEPCTL12_STALL_MASK 0x200000
+#define GC_USB_DOEPCTL12_STALL_SIZE 0x1
+#define GC_USB_DOEPCTL12_STALL_DEFAULT 0x0
+#define GC_USB_DOEPCTL12_STALL_OFFSET 0xc80
+#define GC_USB_DOEPCTL12_CNAK_LSB 0x1a
+#define GC_USB_DOEPCTL12_CNAK_MASK 0x4000000
+#define GC_USB_DOEPCTL12_CNAK_SIZE 0x1
+#define GC_USB_DOEPCTL12_CNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL12_CNAK_OFFSET 0xc80
+#define GC_USB_DOEPCTL12_SNAK_LSB 0x1b
+#define GC_USB_DOEPCTL12_SNAK_MASK 0x8000000
+#define GC_USB_DOEPCTL12_SNAK_SIZE 0x1
+#define GC_USB_DOEPCTL12_SNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL12_SNAK_OFFSET 0xc80
+#define GC_USB_DOEPCTL12_SETD0PID_LSB 0x1c
+#define GC_USB_DOEPCTL12_SETD0PID_MASK 0x10000000
+#define GC_USB_DOEPCTL12_SETD0PID_SIZE 0x1
+#define GC_USB_DOEPCTL12_SETD0PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL12_SETD0PID_OFFSET 0xc80
+#define GC_USB_DOEPCTL12_SETD1PID_LSB 0x1d
+#define GC_USB_DOEPCTL12_SETD1PID_MASK 0x20000000
+#define GC_USB_DOEPCTL12_SETD1PID_SIZE 0x1
+#define GC_USB_DOEPCTL12_SETD1PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL12_SETD1PID_OFFSET 0xc80
+#define GC_USB_DOEPCTL12_EPDIS_LSB 0x1e
+#define GC_USB_DOEPCTL12_EPDIS_MASK 0x40000000
+#define GC_USB_DOEPCTL12_EPDIS_SIZE 0x1
+#define GC_USB_DOEPCTL12_EPDIS_DEFAULT 0x0
+#define GC_USB_DOEPCTL12_EPDIS_OFFSET 0xc80
+#define GC_USB_DOEPCTL12_EPENA_LSB 0x1f
+#define GC_USB_DOEPCTL12_EPENA_MASK 0x80000000
+#define GC_USB_DOEPCTL12_EPENA_SIZE 0x1
+#define GC_USB_DOEPCTL12_EPENA_DEFAULT 0x0
+#define GC_USB_DOEPCTL12_EPENA_OFFSET 0xc80
+#define GC_USB_DOEPINT12_XFERCOMPL_LSB 0x0
+#define GC_USB_DOEPINT12_XFERCOMPL_MASK 0x1
+#define GC_USB_DOEPINT12_XFERCOMPL_SIZE 0x1
+#define GC_USB_DOEPINT12_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DOEPINT12_XFERCOMPL_OFFSET 0xc88
+#define GC_USB_DOEPINT12_EPDISBLD_LSB 0x1
+#define GC_USB_DOEPINT12_EPDISBLD_MASK 0x2
+#define GC_USB_DOEPINT12_EPDISBLD_SIZE 0x1
+#define GC_USB_DOEPINT12_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DOEPINT12_EPDISBLD_OFFSET 0xc88
+#define GC_USB_DOEPINT12_AHBERR_LSB 0x2
+#define GC_USB_DOEPINT12_AHBERR_MASK 0x4
+#define GC_USB_DOEPINT12_AHBERR_SIZE 0x1
+#define GC_USB_DOEPINT12_AHBERR_DEFAULT 0x0
+#define GC_USB_DOEPINT12_AHBERR_OFFSET 0xc88
+#define GC_USB_DOEPINT12_SETUP_LSB 0x3
+#define GC_USB_DOEPINT12_SETUP_MASK 0x8
+#define GC_USB_DOEPINT12_SETUP_SIZE 0x1
+#define GC_USB_DOEPINT12_SETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT12_SETUP_OFFSET 0xc88
+#define GC_USB_DOEPINT12_OUTTKNEPDIS_LSB 0x4
+#define GC_USB_DOEPINT12_OUTTKNEPDIS_MASK 0x10
+#define GC_USB_DOEPINT12_OUTTKNEPDIS_SIZE 0x1
+#define GC_USB_DOEPINT12_OUTTKNEPDIS_DEFAULT 0x0
+#define GC_USB_DOEPINT12_OUTTKNEPDIS_OFFSET 0xc88
+#define GC_USB_DOEPINT12_STSPHSERCVD_LSB 0x5
+#define GC_USB_DOEPINT12_STSPHSERCVD_MASK 0x20
+#define GC_USB_DOEPINT12_STSPHSERCVD_SIZE 0x1
+#define GC_USB_DOEPINT12_STSPHSERCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT12_STSPHSERCVD_OFFSET 0xc88
+#define GC_USB_DOEPINT12_BACK2BACKSETUP_LSB 0x6
+#define GC_USB_DOEPINT12_BACK2BACKSETUP_MASK 0x40
+#define GC_USB_DOEPINT12_BACK2BACKSETUP_SIZE 0x1
+#define GC_USB_DOEPINT12_BACK2BACKSETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT12_BACK2BACKSETUP_OFFSET 0xc88
+#define GC_USB_DOEPINT12_OUTPKTERR_LSB 0x8
+#define GC_USB_DOEPINT12_OUTPKTERR_MASK 0x100
+#define GC_USB_DOEPINT12_OUTPKTERR_SIZE 0x1
+#define GC_USB_DOEPINT12_OUTPKTERR_DEFAULT 0x0
+#define GC_USB_DOEPINT12_OUTPKTERR_OFFSET 0xc88
+#define GC_USB_DOEPINT12_BNAINTR_LSB 0x9
+#define GC_USB_DOEPINT12_BNAINTR_MASK 0x200
+#define GC_USB_DOEPINT12_BNAINTR_SIZE 0x1
+#define GC_USB_DOEPINT12_BNAINTR_DEFAULT 0x0
+#define GC_USB_DOEPINT12_BNAINTR_OFFSET 0xc88
+#define GC_USB_DOEPINT12_PKTDRPSTS_LSB 0xb
+#define GC_USB_DOEPINT12_PKTDRPSTS_MASK 0x800
+#define GC_USB_DOEPINT12_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DOEPINT12_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DOEPINT12_PKTDRPSTS_OFFSET 0xc88
+#define GC_USB_DOEPINT12_BBLEERR_LSB 0xc
+#define GC_USB_DOEPINT12_BBLEERR_MASK 0x1000
+#define GC_USB_DOEPINT12_BBLEERR_SIZE 0x1
+#define GC_USB_DOEPINT12_BBLEERR_DEFAULT 0x0
+#define GC_USB_DOEPINT12_BBLEERR_OFFSET 0xc88
+#define GC_USB_DOEPINT12_NAKINTRPT_LSB 0xd
+#define GC_USB_DOEPINT12_NAKINTRPT_MASK 0x2000
+#define GC_USB_DOEPINT12_NAKINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT12_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT12_NAKINTRPT_OFFSET 0xc88
+#define GC_USB_DOEPINT12_NYETINTRPT_LSB 0xe
+#define GC_USB_DOEPINT12_NYETINTRPT_MASK 0x4000
+#define GC_USB_DOEPINT12_NYETINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT12_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT12_NYETINTRPT_OFFSET 0xc88
+#define GC_USB_DOEPINT12_STUPPKTRCVD_LSB 0xf
+#define GC_USB_DOEPINT12_STUPPKTRCVD_MASK 0x8000
+#define GC_USB_DOEPINT12_STUPPKTRCVD_SIZE 0x1
+#define GC_USB_DOEPINT12_STUPPKTRCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT12_STUPPKTRCVD_OFFSET 0xc88
+#define GC_USB_DOEPTSIZ12_XFERSIZE_LSB 0x0
+#define GC_USB_DOEPTSIZ12_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DOEPTSIZ12_XFERSIZE_SIZE 0x13
+#define GC_USB_DOEPTSIZ12_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ12_XFERSIZE_OFFSET 0xc90
+#define GC_USB_DOEPTSIZ12_PKTCNT_LSB 0x13
+#define GC_USB_DOEPTSIZ12_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DOEPTSIZ12_PKTCNT_SIZE 0xa
+#define GC_USB_DOEPTSIZ12_PKTCNT_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ12_PKTCNT_OFFSET 0xc90
+#define GC_USB_DOEPTSIZ12_RXDPID_LSB 0x1d
+#define GC_USB_DOEPTSIZ12_RXDPID_MASK 0x60000000
+#define GC_USB_DOEPTSIZ12_RXDPID_SIZE 0x2
+#define GC_USB_DOEPTSIZ12_RXDPID_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ12_RXDPID_OFFSET 0xc90
+#define GC_USB_DOEPDMA12_DMAADDR_LSB 0x0
+#define GC_USB_DOEPDMA12_DMAADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMA12_DMAADDR_SIZE 0x20
+#define GC_USB_DOEPDMA12_DMAADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMA12_DMAADDR_OFFSET 0xc94
+#define GC_USB_DOEPDMAB12_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DOEPDMAB12_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMAB12_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DOEPDMAB12_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMAB12_DMABUFFERADDR_OFFSET 0xc9c
+#define GC_USB_DOEPCTL13_MPS_LSB 0x0
+#define GC_USB_DOEPCTL13_MPS_MASK 0x7ff
+#define GC_USB_DOEPCTL13_MPS_SIZE 0xb
+#define GC_USB_DOEPCTL13_MPS_DEFAULT 0x0
+#define GC_USB_DOEPCTL13_MPS_OFFSET 0xca0
+#define GC_USB_DOEPCTL13_USBACTEP_LSB 0xf
+#define GC_USB_DOEPCTL13_USBACTEP_MASK 0x8000
+#define GC_USB_DOEPCTL13_USBACTEP_SIZE 0x1
+#define GC_USB_DOEPCTL13_USBACTEP_DEFAULT 0x0
+#define GC_USB_DOEPCTL13_USBACTEP_OFFSET 0xca0
+#define GC_USB_DOEPCTL13_DPID_LSB 0x10
+#define GC_USB_DOEPCTL13_DPID_MASK 0x10000
+#define GC_USB_DOEPCTL13_DPID_SIZE 0x1
+#define GC_USB_DOEPCTL13_DPID_DEFAULT 0x0
+#define GC_USB_DOEPCTL13_DPID_OFFSET 0xca0
+#define GC_USB_DOEPCTL13_NAKSTS_LSB 0x11
+#define GC_USB_DOEPCTL13_NAKSTS_MASK 0x20000
+#define GC_USB_DOEPCTL13_NAKSTS_SIZE 0x1
+#define GC_USB_DOEPCTL13_NAKSTS_DEFAULT 0x0
+#define GC_USB_DOEPCTL13_NAKSTS_OFFSET 0xca0
+#define GC_USB_DOEPCTL13_EPTYPE_LSB 0x12
+#define GC_USB_DOEPCTL13_EPTYPE_MASK 0xc0000
+#define GC_USB_DOEPCTL13_EPTYPE_SIZE 0x2
+#define GC_USB_DOEPCTL13_EPTYPE_DEFAULT 0x0
+#define GC_USB_DOEPCTL13_EPTYPE_OFFSET 0xca0
+#define GC_USB_DOEPCTL13_SNP_LSB 0x14
+#define GC_USB_DOEPCTL13_SNP_MASK 0x100000
+#define GC_USB_DOEPCTL13_SNP_SIZE 0x1
+#define GC_USB_DOEPCTL13_SNP_DEFAULT 0x0
+#define GC_USB_DOEPCTL13_SNP_OFFSET 0xca0
+#define GC_USB_DOEPCTL13_STALL_LSB 0x15
+#define GC_USB_DOEPCTL13_STALL_MASK 0x200000
+#define GC_USB_DOEPCTL13_STALL_SIZE 0x1
+#define GC_USB_DOEPCTL13_STALL_DEFAULT 0x0
+#define GC_USB_DOEPCTL13_STALL_OFFSET 0xca0
+#define GC_USB_DOEPCTL13_CNAK_LSB 0x1a
+#define GC_USB_DOEPCTL13_CNAK_MASK 0x4000000
+#define GC_USB_DOEPCTL13_CNAK_SIZE 0x1
+#define GC_USB_DOEPCTL13_CNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL13_CNAK_OFFSET 0xca0
+#define GC_USB_DOEPCTL13_SNAK_LSB 0x1b
+#define GC_USB_DOEPCTL13_SNAK_MASK 0x8000000
+#define GC_USB_DOEPCTL13_SNAK_SIZE 0x1
+#define GC_USB_DOEPCTL13_SNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL13_SNAK_OFFSET 0xca0
+#define GC_USB_DOEPCTL13_SETD0PID_LSB 0x1c
+#define GC_USB_DOEPCTL13_SETD0PID_MASK 0x10000000
+#define GC_USB_DOEPCTL13_SETD0PID_SIZE 0x1
+#define GC_USB_DOEPCTL13_SETD0PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL13_SETD0PID_OFFSET 0xca0
+#define GC_USB_DOEPCTL13_SETD1PID_LSB 0x1d
+#define GC_USB_DOEPCTL13_SETD1PID_MASK 0x20000000
+#define GC_USB_DOEPCTL13_SETD1PID_SIZE 0x1
+#define GC_USB_DOEPCTL13_SETD1PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL13_SETD1PID_OFFSET 0xca0
+#define GC_USB_DOEPCTL13_EPDIS_LSB 0x1e
+#define GC_USB_DOEPCTL13_EPDIS_MASK 0x40000000
+#define GC_USB_DOEPCTL13_EPDIS_SIZE 0x1
+#define GC_USB_DOEPCTL13_EPDIS_DEFAULT 0x0
+#define GC_USB_DOEPCTL13_EPDIS_OFFSET 0xca0
+#define GC_USB_DOEPCTL13_EPENA_LSB 0x1f
+#define GC_USB_DOEPCTL13_EPENA_MASK 0x80000000
+#define GC_USB_DOEPCTL13_EPENA_SIZE 0x1
+#define GC_USB_DOEPCTL13_EPENA_DEFAULT 0x0
+#define GC_USB_DOEPCTL13_EPENA_OFFSET 0xca0
+#define GC_USB_DOEPINT13_XFERCOMPL_LSB 0x0
+#define GC_USB_DOEPINT13_XFERCOMPL_MASK 0x1
+#define GC_USB_DOEPINT13_XFERCOMPL_SIZE 0x1
+#define GC_USB_DOEPINT13_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DOEPINT13_XFERCOMPL_OFFSET 0xca8
+#define GC_USB_DOEPINT13_EPDISBLD_LSB 0x1
+#define GC_USB_DOEPINT13_EPDISBLD_MASK 0x2
+#define GC_USB_DOEPINT13_EPDISBLD_SIZE 0x1
+#define GC_USB_DOEPINT13_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DOEPINT13_EPDISBLD_OFFSET 0xca8
+#define GC_USB_DOEPINT13_AHBERR_LSB 0x2
+#define GC_USB_DOEPINT13_AHBERR_MASK 0x4
+#define GC_USB_DOEPINT13_AHBERR_SIZE 0x1
+#define GC_USB_DOEPINT13_AHBERR_DEFAULT 0x0
+#define GC_USB_DOEPINT13_AHBERR_OFFSET 0xca8
+#define GC_USB_DOEPINT13_SETUP_LSB 0x3
+#define GC_USB_DOEPINT13_SETUP_MASK 0x8
+#define GC_USB_DOEPINT13_SETUP_SIZE 0x1
+#define GC_USB_DOEPINT13_SETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT13_SETUP_OFFSET 0xca8
+#define GC_USB_DOEPINT13_OUTTKNEPDIS_LSB 0x4
+#define GC_USB_DOEPINT13_OUTTKNEPDIS_MASK 0x10
+#define GC_USB_DOEPINT13_OUTTKNEPDIS_SIZE 0x1
+#define GC_USB_DOEPINT13_OUTTKNEPDIS_DEFAULT 0x0
+#define GC_USB_DOEPINT13_OUTTKNEPDIS_OFFSET 0xca8
+#define GC_USB_DOEPINT13_STSPHSERCVD_LSB 0x5
+#define GC_USB_DOEPINT13_STSPHSERCVD_MASK 0x20
+#define GC_USB_DOEPINT13_STSPHSERCVD_SIZE 0x1
+#define GC_USB_DOEPINT13_STSPHSERCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT13_STSPHSERCVD_OFFSET 0xca8
+#define GC_USB_DOEPINT13_BACK2BACKSETUP_LSB 0x6
+#define GC_USB_DOEPINT13_BACK2BACKSETUP_MASK 0x40
+#define GC_USB_DOEPINT13_BACK2BACKSETUP_SIZE 0x1
+#define GC_USB_DOEPINT13_BACK2BACKSETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT13_BACK2BACKSETUP_OFFSET 0xca8
+#define GC_USB_DOEPINT13_OUTPKTERR_LSB 0x8
+#define GC_USB_DOEPINT13_OUTPKTERR_MASK 0x100
+#define GC_USB_DOEPINT13_OUTPKTERR_SIZE 0x1
+#define GC_USB_DOEPINT13_OUTPKTERR_DEFAULT 0x0
+#define GC_USB_DOEPINT13_OUTPKTERR_OFFSET 0xca8
+#define GC_USB_DOEPINT13_BNAINTR_LSB 0x9
+#define GC_USB_DOEPINT13_BNAINTR_MASK 0x200
+#define GC_USB_DOEPINT13_BNAINTR_SIZE 0x1
+#define GC_USB_DOEPINT13_BNAINTR_DEFAULT 0x0
+#define GC_USB_DOEPINT13_BNAINTR_OFFSET 0xca8
+#define GC_USB_DOEPINT13_PKTDRPSTS_LSB 0xb
+#define GC_USB_DOEPINT13_PKTDRPSTS_MASK 0x800
+#define GC_USB_DOEPINT13_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DOEPINT13_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DOEPINT13_PKTDRPSTS_OFFSET 0xca8
+#define GC_USB_DOEPINT13_BBLEERR_LSB 0xc
+#define GC_USB_DOEPINT13_BBLEERR_MASK 0x1000
+#define GC_USB_DOEPINT13_BBLEERR_SIZE 0x1
+#define GC_USB_DOEPINT13_BBLEERR_DEFAULT 0x0
+#define GC_USB_DOEPINT13_BBLEERR_OFFSET 0xca8
+#define GC_USB_DOEPINT13_NAKINTRPT_LSB 0xd
+#define GC_USB_DOEPINT13_NAKINTRPT_MASK 0x2000
+#define GC_USB_DOEPINT13_NAKINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT13_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT13_NAKINTRPT_OFFSET 0xca8
+#define GC_USB_DOEPINT13_NYETINTRPT_LSB 0xe
+#define GC_USB_DOEPINT13_NYETINTRPT_MASK 0x4000
+#define GC_USB_DOEPINT13_NYETINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT13_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT13_NYETINTRPT_OFFSET 0xca8
+#define GC_USB_DOEPINT13_STUPPKTRCVD_LSB 0xf
+#define GC_USB_DOEPINT13_STUPPKTRCVD_MASK 0x8000
+#define GC_USB_DOEPINT13_STUPPKTRCVD_SIZE 0x1
+#define GC_USB_DOEPINT13_STUPPKTRCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT13_STUPPKTRCVD_OFFSET 0xca8
+#define GC_USB_DOEPTSIZ13_XFERSIZE_LSB 0x0
+#define GC_USB_DOEPTSIZ13_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DOEPTSIZ13_XFERSIZE_SIZE 0x13
+#define GC_USB_DOEPTSIZ13_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ13_XFERSIZE_OFFSET 0xcb0
+#define GC_USB_DOEPTSIZ13_PKTCNT_LSB 0x13
+#define GC_USB_DOEPTSIZ13_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DOEPTSIZ13_PKTCNT_SIZE 0xa
+#define GC_USB_DOEPTSIZ13_PKTCNT_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ13_PKTCNT_OFFSET 0xcb0
+#define GC_USB_DOEPTSIZ13_RXDPID_LSB 0x1d
+#define GC_USB_DOEPTSIZ13_RXDPID_MASK 0x60000000
+#define GC_USB_DOEPTSIZ13_RXDPID_SIZE 0x2
+#define GC_USB_DOEPTSIZ13_RXDPID_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ13_RXDPID_OFFSET 0xcb0
+#define GC_USB_DOEPDMA13_DMAADDR_LSB 0x0
+#define GC_USB_DOEPDMA13_DMAADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMA13_DMAADDR_SIZE 0x20
+#define GC_USB_DOEPDMA13_DMAADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMA13_DMAADDR_OFFSET 0xcb4
+#define GC_USB_DOEPDMAB13_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DOEPDMAB13_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMAB13_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DOEPDMAB13_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMAB13_DMABUFFERADDR_OFFSET 0xcbc
+#define GC_USB_DOEPCTL14_MPS_LSB 0x0
+#define GC_USB_DOEPCTL14_MPS_MASK 0x7ff
+#define GC_USB_DOEPCTL14_MPS_SIZE 0xb
+#define GC_USB_DOEPCTL14_MPS_DEFAULT 0x0
+#define GC_USB_DOEPCTL14_MPS_OFFSET 0xcc0
+#define GC_USB_DOEPCTL14_USBACTEP_LSB 0xf
+#define GC_USB_DOEPCTL14_USBACTEP_MASK 0x8000
+#define GC_USB_DOEPCTL14_USBACTEP_SIZE 0x1
+#define GC_USB_DOEPCTL14_USBACTEP_DEFAULT 0x0
+#define GC_USB_DOEPCTL14_USBACTEP_OFFSET 0xcc0
+#define GC_USB_DOEPCTL14_DPID_LSB 0x10
+#define GC_USB_DOEPCTL14_DPID_MASK 0x10000
+#define GC_USB_DOEPCTL14_DPID_SIZE 0x1
+#define GC_USB_DOEPCTL14_DPID_DEFAULT 0x0
+#define GC_USB_DOEPCTL14_DPID_OFFSET 0xcc0
+#define GC_USB_DOEPCTL14_NAKSTS_LSB 0x11
+#define GC_USB_DOEPCTL14_NAKSTS_MASK 0x20000
+#define GC_USB_DOEPCTL14_NAKSTS_SIZE 0x1
+#define GC_USB_DOEPCTL14_NAKSTS_DEFAULT 0x0
+#define GC_USB_DOEPCTL14_NAKSTS_OFFSET 0xcc0
+#define GC_USB_DOEPCTL14_EPTYPE_LSB 0x12
+#define GC_USB_DOEPCTL14_EPTYPE_MASK 0xc0000
+#define GC_USB_DOEPCTL14_EPTYPE_SIZE 0x2
+#define GC_USB_DOEPCTL14_EPTYPE_DEFAULT 0x0
+#define GC_USB_DOEPCTL14_EPTYPE_OFFSET 0xcc0
+#define GC_USB_DOEPCTL14_SNP_LSB 0x14
+#define GC_USB_DOEPCTL14_SNP_MASK 0x100000
+#define GC_USB_DOEPCTL14_SNP_SIZE 0x1
+#define GC_USB_DOEPCTL14_SNP_DEFAULT 0x0
+#define GC_USB_DOEPCTL14_SNP_OFFSET 0xcc0
+#define GC_USB_DOEPCTL14_STALL_LSB 0x15
+#define GC_USB_DOEPCTL14_STALL_MASK 0x200000
+#define GC_USB_DOEPCTL14_STALL_SIZE 0x1
+#define GC_USB_DOEPCTL14_STALL_DEFAULT 0x0
+#define GC_USB_DOEPCTL14_STALL_OFFSET 0xcc0
+#define GC_USB_DOEPCTL14_CNAK_LSB 0x1a
+#define GC_USB_DOEPCTL14_CNAK_MASK 0x4000000
+#define GC_USB_DOEPCTL14_CNAK_SIZE 0x1
+#define GC_USB_DOEPCTL14_CNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL14_CNAK_OFFSET 0xcc0
+#define GC_USB_DOEPCTL14_SNAK_LSB 0x1b
+#define GC_USB_DOEPCTL14_SNAK_MASK 0x8000000
+#define GC_USB_DOEPCTL14_SNAK_SIZE 0x1
+#define GC_USB_DOEPCTL14_SNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL14_SNAK_OFFSET 0xcc0
+#define GC_USB_DOEPCTL14_SETD0PID_LSB 0x1c
+#define GC_USB_DOEPCTL14_SETD0PID_MASK 0x10000000
+#define GC_USB_DOEPCTL14_SETD0PID_SIZE 0x1
+#define GC_USB_DOEPCTL14_SETD0PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL14_SETD0PID_OFFSET 0xcc0
+#define GC_USB_DOEPCTL14_SETD1PID_LSB 0x1d
+#define GC_USB_DOEPCTL14_SETD1PID_MASK 0x20000000
+#define GC_USB_DOEPCTL14_SETD1PID_SIZE 0x1
+#define GC_USB_DOEPCTL14_SETD1PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL14_SETD1PID_OFFSET 0xcc0
+#define GC_USB_DOEPCTL14_EPDIS_LSB 0x1e
+#define GC_USB_DOEPCTL14_EPDIS_MASK 0x40000000
+#define GC_USB_DOEPCTL14_EPDIS_SIZE 0x1
+#define GC_USB_DOEPCTL14_EPDIS_DEFAULT 0x0
+#define GC_USB_DOEPCTL14_EPDIS_OFFSET 0xcc0
+#define GC_USB_DOEPCTL14_EPENA_LSB 0x1f
+#define GC_USB_DOEPCTL14_EPENA_MASK 0x80000000
+#define GC_USB_DOEPCTL14_EPENA_SIZE 0x1
+#define GC_USB_DOEPCTL14_EPENA_DEFAULT 0x0
+#define GC_USB_DOEPCTL14_EPENA_OFFSET 0xcc0
+#define GC_USB_DOEPINT14_XFERCOMPL_LSB 0x0
+#define GC_USB_DOEPINT14_XFERCOMPL_MASK 0x1
+#define GC_USB_DOEPINT14_XFERCOMPL_SIZE 0x1
+#define GC_USB_DOEPINT14_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DOEPINT14_XFERCOMPL_OFFSET 0xcc8
+#define GC_USB_DOEPINT14_EPDISBLD_LSB 0x1
+#define GC_USB_DOEPINT14_EPDISBLD_MASK 0x2
+#define GC_USB_DOEPINT14_EPDISBLD_SIZE 0x1
+#define GC_USB_DOEPINT14_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DOEPINT14_EPDISBLD_OFFSET 0xcc8
+#define GC_USB_DOEPINT14_AHBERR_LSB 0x2
+#define GC_USB_DOEPINT14_AHBERR_MASK 0x4
+#define GC_USB_DOEPINT14_AHBERR_SIZE 0x1
+#define GC_USB_DOEPINT14_AHBERR_DEFAULT 0x0
+#define GC_USB_DOEPINT14_AHBERR_OFFSET 0xcc8
+#define GC_USB_DOEPINT14_SETUP_LSB 0x3
+#define GC_USB_DOEPINT14_SETUP_MASK 0x8
+#define GC_USB_DOEPINT14_SETUP_SIZE 0x1
+#define GC_USB_DOEPINT14_SETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT14_SETUP_OFFSET 0xcc8
+#define GC_USB_DOEPINT14_OUTTKNEPDIS_LSB 0x4
+#define GC_USB_DOEPINT14_OUTTKNEPDIS_MASK 0x10
+#define GC_USB_DOEPINT14_OUTTKNEPDIS_SIZE 0x1
+#define GC_USB_DOEPINT14_OUTTKNEPDIS_DEFAULT 0x0
+#define GC_USB_DOEPINT14_OUTTKNEPDIS_OFFSET 0xcc8
+#define GC_USB_DOEPINT14_STSPHSERCVD_LSB 0x5
+#define GC_USB_DOEPINT14_STSPHSERCVD_MASK 0x20
+#define GC_USB_DOEPINT14_STSPHSERCVD_SIZE 0x1
+#define GC_USB_DOEPINT14_STSPHSERCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT14_STSPHSERCVD_OFFSET 0xcc8
+#define GC_USB_DOEPINT14_BACK2BACKSETUP_LSB 0x6
+#define GC_USB_DOEPINT14_BACK2BACKSETUP_MASK 0x40
+#define GC_USB_DOEPINT14_BACK2BACKSETUP_SIZE 0x1
+#define GC_USB_DOEPINT14_BACK2BACKSETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT14_BACK2BACKSETUP_OFFSET 0xcc8
+#define GC_USB_DOEPINT14_OUTPKTERR_LSB 0x8
+#define GC_USB_DOEPINT14_OUTPKTERR_MASK 0x100
+#define GC_USB_DOEPINT14_OUTPKTERR_SIZE 0x1
+#define GC_USB_DOEPINT14_OUTPKTERR_DEFAULT 0x0
+#define GC_USB_DOEPINT14_OUTPKTERR_OFFSET 0xcc8
+#define GC_USB_DOEPINT14_BNAINTR_LSB 0x9
+#define GC_USB_DOEPINT14_BNAINTR_MASK 0x200
+#define GC_USB_DOEPINT14_BNAINTR_SIZE 0x1
+#define GC_USB_DOEPINT14_BNAINTR_DEFAULT 0x0
+#define GC_USB_DOEPINT14_BNAINTR_OFFSET 0xcc8
+#define GC_USB_DOEPINT14_PKTDRPSTS_LSB 0xb
+#define GC_USB_DOEPINT14_PKTDRPSTS_MASK 0x800
+#define GC_USB_DOEPINT14_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DOEPINT14_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DOEPINT14_PKTDRPSTS_OFFSET 0xcc8
+#define GC_USB_DOEPINT14_BBLEERR_LSB 0xc
+#define GC_USB_DOEPINT14_BBLEERR_MASK 0x1000
+#define GC_USB_DOEPINT14_BBLEERR_SIZE 0x1
+#define GC_USB_DOEPINT14_BBLEERR_DEFAULT 0x0
+#define GC_USB_DOEPINT14_BBLEERR_OFFSET 0xcc8
+#define GC_USB_DOEPINT14_NAKINTRPT_LSB 0xd
+#define GC_USB_DOEPINT14_NAKINTRPT_MASK 0x2000
+#define GC_USB_DOEPINT14_NAKINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT14_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT14_NAKINTRPT_OFFSET 0xcc8
+#define GC_USB_DOEPINT14_NYETINTRPT_LSB 0xe
+#define GC_USB_DOEPINT14_NYETINTRPT_MASK 0x4000
+#define GC_USB_DOEPINT14_NYETINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT14_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT14_NYETINTRPT_OFFSET 0xcc8
+#define GC_USB_DOEPINT14_STUPPKTRCVD_LSB 0xf
+#define GC_USB_DOEPINT14_STUPPKTRCVD_MASK 0x8000
+#define GC_USB_DOEPINT14_STUPPKTRCVD_SIZE 0x1
+#define GC_USB_DOEPINT14_STUPPKTRCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT14_STUPPKTRCVD_OFFSET 0xcc8
+#define GC_USB_DOEPTSIZ14_XFERSIZE_LSB 0x0
+#define GC_USB_DOEPTSIZ14_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DOEPTSIZ14_XFERSIZE_SIZE 0x13
+#define GC_USB_DOEPTSIZ14_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ14_XFERSIZE_OFFSET 0xcd0
+#define GC_USB_DOEPTSIZ14_PKTCNT_LSB 0x13
+#define GC_USB_DOEPTSIZ14_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DOEPTSIZ14_PKTCNT_SIZE 0xa
+#define GC_USB_DOEPTSIZ14_PKTCNT_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ14_PKTCNT_OFFSET 0xcd0
+#define GC_USB_DOEPTSIZ14_RXDPID_LSB 0x1d
+#define GC_USB_DOEPTSIZ14_RXDPID_MASK 0x60000000
+#define GC_USB_DOEPTSIZ14_RXDPID_SIZE 0x2
+#define GC_USB_DOEPTSIZ14_RXDPID_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ14_RXDPID_OFFSET 0xcd0
+#define GC_USB_DOEPDMA14_DMAADDR_LSB 0x0
+#define GC_USB_DOEPDMA14_DMAADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMA14_DMAADDR_SIZE 0x20
+#define GC_USB_DOEPDMA14_DMAADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMA14_DMAADDR_OFFSET 0xcd4
+#define GC_USB_DOEPDMAB14_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DOEPDMAB14_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMAB14_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DOEPDMAB14_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMAB14_DMABUFFERADDR_OFFSET 0xcdc
+#define GC_USB_DOEPCTL15_MPS_LSB 0x0
+#define GC_USB_DOEPCTL15_MPS_MASK 0x7ff
+#define GC_USB_DOEPCTL15_MPS_SIZE 0xb
+#define GC_USB_DOEPCTL15_MPS_DEFAULT 0x0
+#define GC_USB_DOEPCTL15_MPS_OFFSET 0xce0
+#define GC_USB_DOEPCTL15_USBACTEP_LSB 0xf
+#define GC_USB_DOEPCTL15_USBACTEP_MASK 0x8000
+#define GC_USB_DOEPCTL15_USBACTEP_SIZE 0x1
+#define GC_USB_DOEPCTL15_USBACTEP_DEFAULT 0x0
+#define GC_USB_DOEPCTL15_USBACTEP_OFFSET 0xce0
+#define GC_USB_DOEPCTL15_DPID_LSB 0x10
+#define GC_USB_DOEPCTL15_DPID_MASK 0x10000
+#define GC_USB_DOEPCTL15_DPID_SIZE 0x1
+#define GC_USB_DOEPCTL15_DPID_DEFAULT 0x0
+#define GC_USB_DOEPCTL15_DPID_OFFSET 0xce0
+#define GC_USB_DOEPCTL15_NAKSTS_LSB 0x11
+#define GC_USB_DOEPCTL15_NAKSTS_MASK 0x20000
+#define GC_USB_DOEPCTL15_NAKSTS_SIZE 0x1
+#define GC_USB_DOEPCTL15_NAKSTS_DEFAULT 0x0
+#define GC_USB_DOEPCTL15_NAKSTS_OFFSET 0xce0
+#define GC_USB_DOEPCTL15_EPTYPE_LSB 0x12
+#define GC_USB_DOEPCTL15_EPTYPE_MASK 0xc0000
+#define GC_USB_DOEPCTL15_EPTYPE_SIZE 0x2
+#define GC_USB_DOEPCTL15_EPTYPE_DEFAULT 0x0
+#define GC_USB_DOEPCTL15_EPTYPE_OFFSET 0xce0
+#define GC_USB_DOEPCTL15_SNP_LSB 0x14
+#define GC_USB_DOEPCTL15_SNP_MASK 0x100000
+#define GC_USB_DOEPCTL15_SNP_SIZE 0x1
+#define GC_USB_DOEPCTL15_SNP_DEFAULT 0x0
+#define GC_USB_DOEPCTL15_SNP_OFFSET 0xce0
+#define GC_USB_DOEPCTL15_STALL_LSB 0x15
+#define GC_USB_DOEPCTL15_STALL_MASK 0x200000
+#define GC_USB_DOEPCTL15_STALL_SIZE 0x1
+#define GC_USB_DOEPCTL15_STALL_DEFAULT 0x0
+#define GC_USB_DOEPCTL15_STALL_OFFSET 0xce0
+#define GC_USB_DOEPCTL15_CNAK_LSB 0x1a
+#define GC_USB_DOEPCTL15_CNAK_MASK 0x4000000
+#define GC_USB_DOEPCTL15_CNAK_SIZE 0x1
+#define GC_USB_DOEPCTL15_CNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL15_CNAK_OFFSET 0xce0
+#define GC_USB_DOEPCTL15_SNAK_LSB 0x1b
+#define GC_USB_DOEPCTL15_SNAK_MASK 0x8000000
+#define GC_USB_DOEPCTL15_SNAK_SIZE 0x1
+#define GC_USB_DOEPCTL15_SNAK_DEFAULT 0x0
+#define GC_USB_DOEPCTL15_SNAK_OFFSET 0xce0
+#define GC_USB_DOEPCTL15_SETD0PID_LSB 0x1c
+#define GC_USB_DOEPCTL15_SETD0PID_MASK 0x10000000
+#define GC_USB_DOEPCTL15_SETD0PID_SIZE 0x1
+#define GC_USB_DOEPCTL15_SETD0PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL15_SETD0PID_OFFSET 0xce0
+#define GC_USB_DOEPCTL15_SETD1PID_LSB 0x1d
+#define GC_USB_DOEPCTL15_SETD1PID_MASK 0x20000000
+#define GC_USB_DOEPCTL15_SETD1PID_SIZE 0x1
+#define GC_USB_DOEPCTL15_SETD1PID_DEFAULT 0x0
+#define GC_USB_DOEPCTL15_SETD1PID_OFFSET 0xce0
+#define GC_USB_DOEPCTL15_EPDIS_LSB 0x1e
+#define GC_USB_DOEPCTL15_EPDIS_MASK 0x40000000
+#define GC_USB_DOEPCTL15_EPDIS_SIZE 0x1
+#define GC_USB_DOEPCTL15_EPDIS_DEFAULT 0x0
+#define GC_USB_DOEPCTL15_EPDIS_OFFSET 0xce0
+#define GC_USB_DOEPCTL15_EPENA_LSB 0x1f
+#define GC_USB_DOEPCTL15_EPENA_MASK 0x80000000
+#define GC_USB_DOEPCTL15_EPENA_SIZE 0x1
+#define GC_USB_DOEPCTL15_EPENA_DEFAULT 0x0
+#define GC_USB_DOEPCTL15_EPENA_OFFSET 0xce0
+#define GC_USB_DOEPINT15_XFERCOMPL_LSB 0x0
+#define GC_USB_DOEPINT15_XFERCOMPL_MASK 0x1
+#define GC_USB_DOEPINT15_XFERCOMPL_SIZE 0x1
+#define GC_USB_DOEPINT15_XFERCOMPL_DEFAULT 0x0
+#define GC_USB_DOEPINT15_XFERCOMPL_OFFSET 0xce8
+#define GC_USB_DOEPINT15_EPDISBLD_LSB 0x1
+#define GC_USB_DOEPINT15_EPDISBLD_MASK 0x2
+#define GC_USB_DOEPINT15_EPDISBLD_SIZE 0x1
+#define GC_USB_DOEPINT15_EPDISBLD_DEFAULT 0x0
+#define GC_USB_DOEPINT15_EPDISBLD_OFFSET 0xce8
+#define GC_USB_DOEPINT15_AHBERR_LSB 0x2
+#define GC_USB_DOEPINT15_AHBERR_MASK 0x4
+#define GC_USB_DOEPINT15_AHBERR_SIZE 0x1
+#define GC_USB_DOEPINT15_AHBERR_DEFAULT 0x0
+#define GC_USB_DOEPINT15_AHBERR_OFFSET 0xce8
+#define GC_USB_DOEPINT15_SETUP_LSB 0x3
+#define GC_USB_DOEPINT15_SETUP_MASK 0x8
+#define GC_USB_DOEPINT15_SETUP_SIZE 0x1
+#define GC_USB_DOEPINT15_SETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT15_SETUP_OFFSET 0xce8
+#define GC_USB_DOEPINT15_OUTTKNEPDIS_LSB 0x4
+#define GC_USB_DOEPINT15_OUTTKNEPDIS_MASK 0x10
+#define GC_USB_DOEPINT15_OUTTKNEPDIS_SIZE 0x1
+#define GC_USB_DOEPINT15_OUTTKNEPDIS_DEFAULT 0x0
+#define GC_USB_DOEPINT15_OUTTKNEPDIS_OFFSET 0xce8
+#define GC_USB_DOEPINT15_STSPHSERCVD_LSB 0x5
+#define GC_USB_DOEPINT15_STSPHSERCVD_MASK 0x20
+#define GC_USB_DOEPINT15_STSPHSERCVD_SIZE 0x1
+#define GC_USB_DOEPINT15_STSPHSERCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT15_STSPHSERCVD_OFFSET 0xce8
+#define GC_USB_DOEPINT15_BACK2BACKSETUP_LSB 0x6
+#define GC_USB_DOEPINT15_BACK2BACKSETUP_MASK 0x40
+#define GC_USB_DOEPINT15_BACK2BACKSETUP_SIZE 0x1
+#define GC_USB_DOEPINT15_BACK2BACKSETUP_DEFAULT 0x0
+#define GC_USB_DOEPINT15_BACK2BACKSETUP_OFFSET 0xce8
+#define GC_USB_DOEPINT15_OUTPKTERR_LSB 0x8
+#define GC_USB_DOEPINT15_OUTPKTERR_MASK 0x100
+#define GC_USB_DOEPINT15_OUTPKTERR_SIZE 0x1
+#define GC_USB_DOEPINT15_OUTPKTERR_DEFAULT 0x0
+#define GC_USB_DOEPINT15_OUTPKTERR_OFFSET 0xce8
+#define GC_USB_DOEPINT15_BNAINTR_LSB 0x9
+#define GC_USB_DOEPINT15_BNAINTR_MASK 0x200
+#define GC_USB_DOEPINT15_BNAINTR_SIZE 0x1
+#define GC_USB_DOEPINT15_BNAINTR_DEFAULT 0x0
+#define GC_USB_DOEPINT15_BNAINTR_OFFSET 0xce8
+#define GC_USB_DOEPINT15_PKTDRPSTS_LSB 0xb
+#define GC_USB_DOEPINT15_PKTDRPSTS_MASK 0x800
+#define GC_USB_DOEPINT15_PKTDRPSTS_SIZE 0x1
+#define GC_USB_DOEPINT15_PKTDRPSTS_DEFAULT 0x0
+#define GC_USB_DOEPINT15_PKTDRPSTS_OFFSET 0xce8
+#define GC_USB_DOEPINT15_BBLEERR_LSB 0xc
+#define GC_USB_DOEPINT15_BBLEERR_MASK 0x1000
+#define GC_USB_DOEPINT15_BBLEERR_SIZE 0x1
+#define GC_USB_DOEPINT15_BBLEERR_DEFAULT 0x0
+#define GC_USB_DOEPINT15_BBLEERR_OFFSET 0xce8
+#define GC_USB_DOEPINT15_NAKINTRPT_LSB 0xd
+#define GC_USB_DOEPINT15_NAKINTRPT_MASK 0x2000
+#define GC_USB_DOEPINT15_NAKINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT15_NAKINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT15_NAKINTRPT_OFFSET 0xce8
+#define GC_USB_DOEPINT15_NYETINTRPT_LSB 0xe
+#define GC_USB_DOEPINT15_NYETINTRPT_MASK 0x4000
+#define GC_USB_DOEPINT15_NYETINTRPT_SIZE 0x1
+#define GC_USB_DOEPINT15_NYETINTRPT_DEFAULT 0x0
+#define GC_USB_DOEPINT15_NYETINTRPT_OFFSET 0xce8
+#define GC_USB_DOEPINT15_STUPPKTRCVD_LSB 0xf
+#define GC_USB_DOEPINT15_STUPPKTRCVD_MASK 0x8000
+#define GC_USB_DOEPINT15_STUPPKTRCVD_SIZE 0x1
+#define GC_USB_DOEPINT15_STUPPKTRCVD_DEFAULT 0x0
+#define GC_USB_DOEPINT15_STUPPKTRCVD_OFFSET 0xce8
+#define GC_USB_DOEPTSIZ15_XFERSIZE_LSB 0x0
+#define GC_USB_DOEPTSIZ15_XFERSIZE_MASK 0x7ffff
+#define GC_USB_DOEPTSIZ15_XFERSIZE_SIZE 0x13
+#define GC_USB_DOEPTSIZ15_XFERSIZE_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ15_XFERSIZE_OFFSET 0xcf0
+#define GC_USB_DOEPTSIZ15_PKTCNT_LSB 0x13
+#define GC_USB_DOEPTSIZ15_PKTCNT_MASK 0x1ff80000
+#define GC_USB_DOEPTSIZ15_PKTCNT_SIZE 0xa
+#define GC_USB_DOEPTSIZ15_PKTCNT_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ15_PKTCNT_OFFSET 0xcf0
+#define GC_USB_DOEPTSIZ15_RXDPID_LSB 0x1d
+#define GC_USB_DOEPTSIZ15_RXDPID_MASK 0x60000000
+#define GC_USB_DOEPTSIZ15_RXDPID_SIZE 0x2
+#define GC_USB_DOEPTSIZ15_RXDPID_DEFAULT 0x0
+#define GC_USB_DOEPTSIZ15_RXDPID_OFFSET 0xcf0
+#define GC_USB_DOEPDMA15_DMAADDR_LSB 0x0
+#define GC_USB_DOEPDMA15_DMAADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMA15_DMAADDR_SIZE 0x20
+#define GC_USB_DOEPDMA15_DMAADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMA15_DMAADDR_OFFSET 0xcf4
+#define GC_USB_DOEPDMAB15_DMABUFFERADDR_LSB 0x0
+#define GC_USB_DOEPDMAB15_DMABUFFERADDR_MASK 0xffffffff
+#define GC_USB_DOEPDMAB15_DMABUFFERADDR_SIZE 0x20
+#define GC_USB_DOEPDMAB15_DMABUFFERADDR_DEFAULT 0x0
+#define GC_USB_DOEPDMAB15_DMABUFFERADDR_OFFSET 0xcfc
+#define GC_USB_PCGCCTL_STOPPCLK_LSB 0x0
+#define GC_USB_PCGCCTL_STOPPCLK_MASK 0x1
+#define GC_USB_PCGCCTL_STOPPCLK_SIZE 0x1
+#define GC_USB_PCGCCTL_STOPPCLK_DEFAULT 0x0
+#define GC_USB_PCGCCTL_STOPPCLK_OFFSET 0xe00
+#define GC_USB_PCGCCTL_GATEHCLK_LSB 0x1
+#define GC_USB_PCGCCTL_GATEHCLK_MASK 0x2
+#define GC_USB_PCGCCTL_GATEHCLK_SIZE 0x1
+#define GC_USB_PCGCCTL_GATEHCLK_DEFAULT 0x0
+#define GC_USB_PCGCCTL_GATEHCLK_OFFSET 0xe00
+#define GC_USB_PCGCCTL_PWRCLMP_LSB 0x2
+#define GC_USB_PCGCCTL_PWRCLMP_MASK 0x4
+#define GC_USB_PCGCCTL_PWRCLMP_SIZE 0x1
+#define GC_USB_PCGCCTL_PWRCLMP_DEFAULT 0x0
+#define GC_USB_PCGCCTL_PWRCLMP_OFFSET 0xe00
+#define GC_USB_PCGCCTL_RSTPDWNMODULE_LSB 0x3
+#define GC_USB_PCGCCTL_RSTPDWNMODULE_MASK 0x8
+#define GC_USB_PCGCCTL_RSTPDWNMODULE_SIZE 0x1
+#define GC_USB_PCGCCTL_RSTPDWNMODULE_DEFAULT 0x0
+#define GC_USB_PCGCCTL_RSTPDWNMODULE_OFFSET 0xe00
+#define GC_USB_PCGCCTL_PHYSLEEP_LSB 0x6
+#define GC_USB_PCGCCTL_PHYSLEEP_MASK 0x40
+#define GC_USB_PCGCCTL_PHYSLEEP_SIZE 0x1
+#define GC_USB_PCGCCTL_PHYSLEEP_DEFAULT 0x0
+#define GC_USB_PCGCCTL_PHYSLEEP_OFFSET 0xe00
+#define GC_USB_PCGCCTL_L1SUSPENDED_LSB 0x7
+#define GC_USB_PCGCCTL_L1SUSPENDED_MASK 0x80
+#define GC_USB_PCGCCTL_L1SUSPENDED_SIZE 0x1
+#define GC_USB_PCGCCTL_L1SUSPENDED_DEFAULT 0x0
+#define GC_USB_PCGCCTL_L1SUSPENDED_OFFSET 0xe00
+#define GC_USB_DFIFO_SIZE 0x1000
 
 #endif /* __CHIP_STM32_USB_DWC_REGISTERS_H */
diff --git a/chip/stm32/usb_dwc_stream.c b/chip/stm32/usb_dwc_stream.c
index 2f20d88dda..670c93b437 100644
--- a/chip/stm32/usb_dwc_stream.c
+++ b/chip/stm32/usb_dwc_stream.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,7 +9,7 @@
 #include "util.h"
 
 #include "console.h"
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args)
 
 /*
  * This function tries to shove new bytes from the USB host into the queue for
@@ -24,9 +24,8 @@ int rx_stream_handler(struct usb_stream_config const *config)
 
 	/* If we have some, try to shove them into the queue */
 	if (rx_count) {
-		size_t added = QUEUE_ADD_UNITS(
-			config->producer.queue, config->rx_ram,
-			rx_count);
+		size_t added = QUEUE_ADD_UNITS(config->producer.queue,
+					       config->rx_ram, rx_count);
 		if (added != rx_count) {
 			CPRINTF("rx_stream_handler: failed ep%d "
 				"queue %d bytes, accepted %d\n",
@@ -60,7 +59,7 @@ int tx_stream_handler(struct usb_stream_config const *config)
 
 /* Reset stream */
 void usb_stream_event(struct usb_stream_config const *config,
-		enum usb_ep_event evt)
+		      enum usb_ep_event evt)
 {
 	if (evt != USB_EVENT_RESET)
 		return;
diff --git a/chip/stm32/usb_dwc_stream.h b/chip/stm32/usb_dwc_stream.h
index e46e7a929c..7e5e938053 100644
--- a/chip/stm32/usb_dwc_stream.h
+++ b/chip/stm32/usb_dwc_stream.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -54,7 +54,6 @@ struct usb_stream_config {
 extern struct consumer_ops const usb_stream_consumer_ops;
 extern struct producer_ops const usb_stream_producer_ops;
 
-
 /*
  * Convenience macro for defining USB streams and their associated state and
  * buffers.
@@ -92,26 +91,19 @@ extern struct producer_ops const usb_stream_producer_ops;
  * BUILD_ASSERT(RX_QUEUE.unit_bytes == 1);
  * BUILD_ASSERT(TX_QUEUE.unit_bytes == 1);
  */
-#define USB_STREAM_CONFIG_FULL(NAME,					\
-			       INTERFACE,				\
-			       INTERFACE_CLASS,				\
-			       INTERFACE_SUBCLASS,			\
-			       INTERFACE_PROTOCOL,			\
-			       INTERFACE_NAME,				\
-			       ENDPOINT,				\
-			       RX_SIZE,					\
-			       TX_SIZE,					\
-			       RX_QUEUE,				\
-			       TX_QUEUE)				\
-									\
-	static uint8_t CONCAT2(NAME, _buf_rx_)[RX_SIZE];		\
-	static uint8_t CONCAT2(NAME, _buf_tx_)[TX_SIZE];		\
-	static int CONCAT2(NAME, _is_reset_);				\
-	static int CONCAT2(NAME, _overflow_);				\
-	static void CONCAT2(NAME, _deferred_tx_)(void);			\
-	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_tx_));			\
-	static void CONCAT2(NAME, _deferred_rx_)(void);			\
-	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_rx_));			\
+#define USB_STREAM_CONFIG_FULL(NAME, INTERFACE, INTERFACE_CLASS,               \
+			       INTERFACE_SUBCLASS, INTERFACE_PROTOCOL,         \
+			       INTERFACE_NAME, ENDPOINT, RX_SIZE, TX_SIZE,     \
+			       RX_QUEUE, TX_QUEUE)                             \
+                                                                               \
+	static uint8_t CONCAT2(NAME, _buf_rx_)[RX_SIZE];                       \
+	static uint8_t CONCAT2(NAME, _buf_tx_)[TX_SIZE];                       \
+	static int CONCAT2(NAME, _is_reset_);                                  \
+	static int CONCAT2(NAME, _overflow_);                                  \
+	static void CONCAT2(NAME, _deferred_tx_)(void);                        \
+	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_tx_));                        \
+	static void CONCAT2(NAME, _deferred_rx_)(void);                        \
+	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_rx_));                        \
 	struct usb_stream_config const NAME = {				\
 		.endpoint     = ENDPOINT,				\
 		.is_reset     = &CONCAT2(NAME, _is_reset_),		\
@@ -130,94 +122,80 @@ extern struct producer_ops const usb_stream_producer_ops;
 			.queue = &RX_QUEUE,				\
 			.ops   = &usb_stream_producer_ops,		\
 		},							\
-	};								\
-	const struct usb_interface_descriptor				\
-	USB_IFACE_DESC(INTERFACE) = {					\
-		.bLength            = USB_DT_INTERFACE_SIZE,		\
-		.bDescriptorType    = USB_DT_INTERFACE,			\
-		.bInterfaceNumber   = INTERFACE,			\
-		.bAlternateSetting  = 0,				\
-		.bNumEndpoints      = 2,				\
-		.bInterfaceClass    = INTERFACE_CLASS,			\
-		.bInterfaceSubClass = INTERFACE_SUBCLASS,		\
-		.bInterfaceProtocol = INTERFACE_PROTOCOL,		\
-		.iInterface         = INTERFACE_NAME,			\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 0) = {					\
-		.bLength          = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = 0x80 | ENDPOINT,			\
-		.bmAttributes     = 0x02 /* Bulk IN */,			\
-		.wMaxPacketSize   = TX_SIZE,				\
-		.bInterval        = 10,					\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 1) = {					\
-		.bLength          = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = ENDPOINT,				\
-		.bmAttributes     = 0x02 /* Bulk OUT */,		\
-		.wMaxPacketSize   = RX_SIZE,				\
-		.bInterval        = 0,					\
-	};								\
-	static void CONCAT2(NAME, _deferred_tx_)(void)			\
-	{ tx_stream_handler(&NAME); }					\
-	static void CONCAT2(NAME, _deferred_rx_)(void)			\
-	{ rx_stream_handler(&NAME); }					\
-	static void CONCAT2(NAME, _ep_tx)(void)				\
-	{								\
-		usb_epN_tx(ENDPOINT);					\
-	}								\
-	static void CONCAT2(NAME, _ep_rx)(void)				\
-	{								\
-		usb_epN_rx(ENDPOINT);					\
-	}								\
-	static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt)	\
-	{								\
-		usb_stream_event(&NAME, evt);				\
-	}								\
-	struct dwc_usb_ep CONCAT2(NAME, _ep_ctl) = {			\
-		.max_packet = USB_MAX_PACKET_SIZE,			\
-		.tx_fifo = ENDPOINT,					\
-		.out_pending = 0,					\
-		.out_expected = 0,					\
-		.out_data = 0,						\
-		.out_databuffer = CONCAT2(NAME, _buf_rx_),		\
-		.out_databuffer_max = RX_SIZE,				\
-		.rx_deferred = &CONCAT2(NAME, _deferred_rx__data),	\
-		.in_packets = 0,					\
-		.in_pending = 0,					\
-		.in_data = 0,						\
-		.in_databuffer = CONCAT2(NAME, _buf_tx_),		\
-		.in_databuffer_max = TX_SIZE,				\
-		.tx_deferred = &CONCAT2(NAME, _deferred_tx__data),	\
-	};								\
-	USB_DECLARE_EP(ENDPOINT,					\
-		       CONCAT2(NAME, _ep_tx),				\
-		       CONCAT2(NAME, _ep_rx),				\
+	};                           \
+	const struct usb_interface_descriptor USB_IFACE_DESC(INTERFACE) = {    \
+		.bLength = USB_DT_INTERFACE_SIZE,                              \
+		.bDescriptorType = USB_DT_INTERFACE,                           \
+		.bInterfaceNumber = INTERFACE,                                 \
+		.bAlternateSetting = 0,                                        \
+		.bNumEndpoints = 2,                                            \
+		.bInterfaceClass = INTERFACE_CLASS,                            \
+		.bInterfaceSubClass = INTERFACE_SUBCLASS,                      \
+		.bInterfaceProtocol = INTERFACE_PROTOCOL,                      \
+		.iInterface = INTERFACE_NAME,                                  \
+	};                                                                     \
+	const struct usb_endpoint_descriptor USB_EP_DESC(INTERFACE, 0) = {     \
+		.bLength = USB_DT_ENDPOINT_SIZE,                               \
+		.bDescriptorType = USB_DT_ENDPOINT,                            \
+		.bEndpointAddress = 0x80 | ENDPOINT,                           \
+		.bmAttributes = 0x02 /* Bulk IN */,                            \
+		.wMaxPacketSize = TX_SIZE,                                     \
+		.bInterval = 10,                                               \
+	};                                                                     \
+	const struct usb_endpoint_descriptor USB_EP_DESC(INTERFACE, 1) = {     \
+		.bLength = USB_DT_ENDPOINT_SIZE,                               \
+		.bDescriptorType = USB_DT_ENDPOINT,                            \
+		.bEndpointAddress = ENDPOINT,                                  \
+		.bmAttributes = 0x02 /* Bulk OUT */,                           \
+		.wMaxPacketSize = RX_SIZE,                                     \
+		.bInterval = 0,                                                \
+	};                                                                     \
+	static void CONCAT2(NAME, _deferred_tx_)(void)                         \
+	{                                                                      \
+		tx_stream_handler(&NAME);                                      \
+	}                                                                      \
+	static void CONCAT2(NAME, _deferred_rx_)(void)                         \
+	{                                                                      \
+		rx_stream_handler(&NAME);                                      \
+	}                                                                      \
+	static void CONCAT2(NAME, _ep_tx)(void)                                \
+	{                                                                      \
+		usb_epN_tx(ENDPOINT);                                          \
+	}                                                                      \
+	static void CONCAT2(NAME, _ep_rx)(void)                                \
+	{                                                                      \
+		usb_epN_rx(ENDPOINT);                                          \
+	}                                                                      \
+	static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt)            \
+	{                                                                      \
+		usb_stream_event(&NAME, evt);                                  \
+	}                                                                      \
+	struct dwc_usb_ep CONCAT2(NAME, _ep_ctl) = {                           \
+		.max_packet = USB_MAX_PACKET_SIZE,                             \
+		.tx_fifo = ENDPOINT,                                           \
+		.out_pending = 0,                                              \
+		.out_expected = 0,                                             \
+		.out_data = 0,                                                 \
+		.out_databuffer = CONCAT2(NAME, _buf_rx_),                     \
+		.out_databuffer_max = RX_SIZE,                                 \
+		.rx_deferred = &CONCAT2(NAME, _deferred_rx__data),             \
+		.in_packets = 0,                                               \
+		.in_pending = 0,                                               \
+		.in_data = 0,                                                  \
+		.in_databuffer = CONCAT2(NAME, _buf_tx_),                      \
+		.in_databuffer_max = TX_SIZE,                                  \
+		.tx_deferred = &CONCAT2(NAME, _deferred_tx__data),             \
+	};                                                                     \
+	USB_DECLARE_EP(ENDPOINT, CONCAT2(NAME, _ep_tx), CONCAT2(NAME, _ep_rx), \
 		       CONCAT2(NAME, _ep_event));
 
 /* This is a short version for declaring Google serial endpoints */
-#define USB_STREAM_CONFIG(NAME,						\
-			  INTERFACE,					\
-			  INTERFACE_NAME,				\
-			  ENDPOINT,					\
-			  RX_SIZE,					\
-			  TX_SIZE,					\
-			  RX_QUEUE,					\
-			  TX_QUEUE)					\
-	USB_STREAM_CONFIG_FULL(NAME,					\
-			       INTERFACE,				\
-			       USB_CLASS_VENDOR_SPEC,			\
-			       USB_SUBCLASS_GOOGLE_SERIAL,		\
-			       USB_PROTOCOL_GOOGLE_SERIAL,		\
-			       INTERFACE_NAME,				\
-			       ENDPOINT,				\
-			       RX_SIZE,					\
-			       TX_SIZE,					\
-			       RX_QUEUE,				\
-			       TX_QUEUE)
+#define USB_STREAM_CONFIG(NAME, INTERFACE, INTERFACE_NAME, ENDPOINT, RX_SIZE, \
+			  TX_SIZE, RX_QUEUE, TX_QUEUE)                        \
+	USB_STREAM_CONFIG_FULL(NAME, INTERFACE, USB_CLASS_VENDOR_SPEC,        \
+			       USB_SUBCLASS_GOOGLE_SERIAL,                    \
+			       USB_PROTOCOL_GOOGLE_SERIAL, INTERFACE_NAME,    \
+			       ENDPOINT, RX_SIZE, TX_SIZE, RX_QUEUE, TX_QUEUE)
 
 /*
  * Handle USB and Queue request in a deferred callback.
@@ -232,6 +210,6 @@ int tx_stream_handler(struct usb_stream_config const *config);
 void usb_stream_tx(struct usb_stream_config const *config);
 void usb_stream_rx(struct usb_stream_config const *config);
 void usb_stream_event(struct usb_stream_config const *config,
-		enum usb_ep_event evt);
+		      enum usb_ep_event evt);
 
 #endif /* __CROS_EC_USB_STREAM_H */
diff --git a/chip/stm32/usb_dwc_update.h b/chip/stm32/usb_dwc_update.h
index 6d79f3aca9..1d5027a01f 100644
--- a/chip/stm32/usb_dwc_update.h
+++ b/chip/stm32/usb_dwc_update.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/chip/stm32/usb_endpoints.c b/chip/stm32/usb_endpoints.c
index 7cdff25a6a..b435a88846 100644
--- a/chip/stm32/usb_endpoints.c
+++ b/chip/stm32/usb_endpoints.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -12,7 +12,7 @@
 #include "usb_hw.h"
 
 typedef void (*xfer_func)(void);
-typedef void (*evt_func) (enum usb_ep_event evt);
+typedef void (*evt_func)(enum usb_ep_event evt);
 
 #if defined(CHIP_FAMILY_STM32F4)
 #define iface_arguments struct usb_setup_packet *req
@@ -44,18 +44,18 @@ int iface_undefined(iface_arguments)
 
 #define table(type, name, x) x
 
-#define endpoint_tx(number) \
+#define endpoint_tx(number)                                            \
 	extern void __attribute__((used, weak, alias("ep_undefined"))) \
-		ep_ ## number ## _tx(void);
-#define endpoint_rx(number) \
+	ep_##number##_tx(void);
+#define endpoint_rx(number)                                            \
 	extern void __attribute__((used, weak, alias("ep_undefined"))) \
-		ep_ ## number ## _rx(void);
-#define endpoint_evt(number) \
+	ep_##number##_rx(void);
+#define endpoint_evt(number)                                               \
 	extern void __attribute__((used, weak, alias("ep_evt_undefined"))) \
-		ep_ ## number ## _evt(enum usb_ep_event evt);
-#define interface(number) \
+	ep_##number##_evt(enum usb_ep_event evt);
+#define interface(number)                                                \
 	extern int __attribute__((used, weak, alias("iface_undefined"))) \
-		iface_ ## number ## _request(iface_arguments);
+	iface_##number##_request(iface_arguments);
 
 #define null
 
@@ -79,20 +79,23 @@ int iface_undefined(iface_arguments)
 #endif /* __clang__ */
 
 /* align function pointers on a 32-bit boundary */
-#define table(type, name, x) type name[] __attribute__((aligned(4), section(".rodata.usb_ep." #name ",\"a\" @"))) = { x };
-#define null (void*)0
+#define table(type, name, x)                                                   \
+	type name[] __attribute__((aligned(4), section(".rodata.usb_ep." #name \
+						       ",\"a\" @"))) = { x };
+#define null (void *)0
 
 #define ep_(num, suf) CONCAT3(ep_, num, suf)
 #define ep(num, suf) ep_(num, suf)
 
 #define endpoint_tx(number) \
-	[number < USB_EP_COUNT ? number : USB_EP_COUNT - 1] = ep_ ## number ## _tx,
+	[number < USB_EP_COUNT ? number : USB_EP_COUNT - 1] = ep_##number##_tx,
 #define endpoint_rx(number) \
-	[number < USB_EP_COUNT ? number : USB_EP_COUNT - 1] = ep_ ## number ## _rx,
+	[number < USB_EP_COUNT ? number : USB_EP_COUNT - 1] = ep_##number##_rx,
 #define endpoint_evt(number) \
-	[number < USB_EP_COUNT ? number : USB_EP_COUNT - 1] = ep_ ## number ## _evt,
-#define interface(number) \
-	[number < USB_IFACE_COUNT ? number : USB_IFACE_COUNT - 1] = iface_ ## number ## _request,
+	[number < USB_EP_COUNT ? number : USB_EP_COUNT - 1] = ep_##number##_evt,
+#define interface(number)                                           \
+	[number < USB_IFACE_COUNT ? number : USB_IFACE_COUNT - 1] = \
+		iface_##number##_request,
 #endif /* PASS 2 */
 
 /*
@@ -102,73 +105,36 @@ int iface_undefined(iface_arguments)
  * It all sorts out nicely
  */
 table(xfer_func, usb_ep_tx,
-	endpoint_tx(15)
-	endpoint_tx(14)
-	endpoint_tx(13)
-	endpoint_tx(12)
-	endpoint_tx(11)
-	endpoint_tx(10)
-	endpoint_tx(9)
-	endpoint_tx(8)
-	endpoint_tx(7)
-	endpoint_tx(6)
-	endpoint_tx(5)
-	endpoint_tx(4)
-	endpoint_tx(3)
-	endpoint_tx(2)
-	endpoint_tx(1)
-	endpoint_tx(0)
-)
-
-table(xfer_func, usb_ep_rx,
-	endpoint_rx(15)
-	endpoint_rx(14)
-	endpoint_rx(13)
-	endpoint_rx(12)
-	endpoint_rx(11)
-	endpoint_rx(10)
-	endpoint_rx(9)
-	endpoint_rx(8)
-	endpoint_rx(7)
-	endpoint_rx(6)
-	endpoint_rx(5)
-	endpoint_rx(4)
-	endpoint_rx(3)
-	endpoint_rx(2)
-	endpoint_rx(1)
-	endpoint_rx(0)
-)
-
-table(evt_func, usb_ep_event,
-	endpoint_evt(15)
-	endpoint_evt(14)
-	endpoint_evt(13)
-	endpoint_evt(12)
-	endpoint_evt(11)
-	endpoint_evt(10)
-	endpoint_evt(9)
-	endpoint_evt(8)
-	endpoint_evt(7)
-	endpoint_evt(6)
-	endpoint_evt(5)
-	endpoint_evt(4)
-	endpoint_evt(3)
-	endpoint_evt(2)
-	endpoint_evt(1)
-	endpoint_evt(0)
-)
+      endpoint_tx(15) endpoint_tx(14) endpoint_tx(13) endpoint_tx(12)
+	      endpoint_tx(11) endpoint_tx(10) endpoint_tx(9) endpoint_tx(8)
+		      endpoint_tx(7) endpoint_tx(6) endpoint_tx(5)
+			      endpoint_tx(4) endpoint_tx(3) endpoint_tx(2)
+				      endpoint_tx(1) endpoint_tx(0))
+
+	table(xfer_func, usb_ep_rx,
+	      endpoint_rx(15) endpoint_rx(14) endpoint_rx(13) endpoint_rx(12)
+		      endpoint_rx(11) endpoint_rx(10) endpoint_rx(9)
+			      endpoint_rx(8) endpoint_rx(7) endpoint_rx(6)
+				      endpoint_rx(5) endpoint_rx(4)
+					      endpoint_rx(3) endpoint_rx(2)
+						      endpoint_rx(1)
+							      endpoint_rx(0))
+
+		table(evt_func, usb_ep_event,
+		      endpoint_evt(15) endpoint_evt(14) endpoint_evt(
+			      13) endpoint_evt(12) endpoint_evt(11)
+			      endpoint_evt(10) endpoint_evt(9) endpoint_evt(
+				      8) endpoint_evt(7) endpoint_evt(6)
+				      endpoint_evt(5) endpoint_evt(4)
+					      endpoint_evt(3) endpoint_evt(2)
+						      endpoint_evt(1)
+							      endpoint_evt(0))
 
 #if USB_IFACE_COUNT > 0
-table(iface_func, usb_iface_request,
-	interface(7)
-	interface(6)
-	interface(5)
-	interface(4)
-	interface(3)
-	interface(2)
-	interface(1)
-	interface(0)
-)
+			table(iface_func, usb_iface_request,
+			      interface(7) interface(6) interface(5)
+				      interface(4) interface(3) interface(2)
+					      interface(1) interface(0))
 #endif
 
 #if PASS == 2
diff --git a/chip/stm32/usb_gpio.c b/chip/stm32/usb_gpio.c
index 64d46875b5..a0655fd045 100644
--- a/chip/stm32/usb_gpio.c
+++ b/chip/stm32/usb_gpio.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,8 @@
 
 void usb_gpio_tx(struct usb_gpio_config const *config)
 {
-	size_t   i;
-	uint32_t mask  = 1;
+	size_t i;
+	uint32_t mask = 1;
 	uint32_t value = 0;
 
 	for (i = 0; i < config->num_gpios; ++i, mask <<= 1)
@@ -31,12 +31,12 @@ void usb_gpio_tx(struct usb_gpio_config const *config)
 
 void usb_gpio_rx(struct usb_gpio_config const *config)
 {
-	size_t   i;
-	uint32_t mask        = 1;
-	uint32_t set_mask    = ((uint32_t)(config->rx_ram[0]) |
-			        (uint32_t)(config->rx_ram[1]) << 16);
-	uint32_t clear_mask  = ((uint32_t)(config->rx_ram[2]) |
-			        (uint32_t)(config->rx_ram[3]) << 16);
+	size_t i;
+	uint32_t mask = 1;
+	uint32_t set_mask = ((uint32_t)(config->rx_ram[0]) |
+			     (uint32_t)(config->rx_ram[1]) << 16);
+	uint32_t clear_mask = ((uint32_t)(config->rx_ram[2]) |
+			       (uint32_t)(config->rx_ram[3]) << 16);
 	uint32_t ignore_mask = set_mask & clear_mask;
 
 	config->state->set_mask = set_mask;
@@ -69,10 +69,10 @@ void usb_gpio_event(struct usb_gpio_config const *config, enum usb_ep_event evt)
 
 	i = config->endpoint;
 
-	btable_ep[i].tx_addr  = usb_sram_addr(config->tx_ram);
+	btable_ep[i].tx_addr = usb_sram_addr(config->tx_ram);
 	btable_ep[i].tx_count = USB_GPIO_TX_PACKET_SIZE;
 
-	btable_ep[i].rx_addr  = usb_sram_addr(config->rx_ram);
+	btable_ep[i].rx_addr = usb_sram_addr(config->rx_ram);
 	btable_ep[i].rx_count = ((USB_GPIO_RX_PACKET_SIZE / 2) << 10);
 
 	/*
@@ -82,8 +82,8 @@ void usb_gpio_event(struct usb_gpio_config const *config, enum usb_ep_event evt)
 	config->tx_ram[0] = 0;
 	config->tx_ram[1] = 0;
 
-	STM32_USB_EP(i) = ((i <<  0) | /* Endpoint Addr*/
-			   (3 <<  4) | /* TX Valid */
-			   (0 <<  9) | /* Bulk EP */
+	STM32_USB_EP(i) = ((i << 0) | /* Endpoint Addr*/
+			   (3 << 4) | /* TX Valid */
+			   (0 << 9) | /* Bulk EP */
 			   (3 << 12)); /* RX Valid */
 }
diff --git a/chip/stm32/usb_gpio.h b/chip/stm32/usb_gpio.h
index b27c7f9485..a54801048b 100644
--- a/chip/stm32/usb_gpio.h
+++ b/chip/stm32/usb_gpio.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -55,69 +55,62 @@ struct usb_gpio_config {
  * ENDPOINT is the index of the USB bulk endpoint used for receiving and
  * transmitting bytes.
  */
-#define USB_GPIO_CONFIG(NAME,						\
-			GPIO_LIST,					\
-			INTERFACE,					\
-			ENDPOINT)					\
-	BUILD_ASSERT(ARRAY_SIZE(GPIO_LIST) <= 32);			\
-	static usb_uint CONCAT2(NAME, _ep_rx_buffer)[USB_GPIO_RX_PACKET_SIZE / 2] __usb_ram;	\
-	static usb_uint CONCAT2(NAME, _ep_tx_buffer)[USB_GPIO_TX_PACKET_SIZE / 2] __usb_ram;	\
-	struct usb_gpio_config const NAME = {				\
-		.state     = &((struct usb_gpio_state){}),		\
-		.endpoint  = ENDPOINT,					\
-		.rx_ram    = CONCAT2(NAME, _ep_rx_buffer),		\
-		.tx_ram    = CONCAT2(NAME, _ep_tx_buffer),		\
-		.gpios     = GPIO_LIST,					\
-		.num_gpios = ARRAY_SIZE(GPIO_LIST),			\
-	};								\
-	const struct usb_interface_descriptor				\
-	USB_IFACE_DESC(INTERFACE) = {					\
-		.bLength            = USB_DT_INTERFACE_SIZE,		\
-		.bDescriptorType    = USB_DT_INTERFACE,			\
-		.bInterfaceNumber   = INTERFACE,			\
-		.bAlternateSetting  = 0,				\
-		.bNumEndpoints      = 2,				\
-		.bInterfaceClass    = USB_CLASS_VENDOR_SPEC,		\
-		.bInterfaceSubClass = 0,				\
-		.bInterfaceProtocol = 0,				\
-		.iInterface         = 0,				\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 0) = {					\
-		.bLength          = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = 0x80 | ENDPOINT,			\
-		.bmAttributes     = 0x02 /* Bulk IN */,			\
-		.wMaxPacketSize   = USB_GPIO_TX_PACKET_SIZE,		\
-		.bInterval        = 10,					\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 1) = {					\
-		.bLength          = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = ENDPOINT,				\
-		.bmAttributes     = 0x02 /* Bulk OUT */,		\
-		.wMaxPacketSize   = USB_GPIO_RX_PACKET_SIZE,		\
-		.bInterval        = 0,					\
-	};								\
-	static void CONCAT2(NAME, _ep_tx)(void)				\
-	{								\
-		usb_gpio_tx(&NAME);					\
-	}								\
-	static void CONCAT2(NAME, _ep_rx)(void)				\
-	{								\
-		usb_gpio_rx(&NAME);					\
-	}								\
-	static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt)	\
-	{								\
-		usb_gpio_event(&NAME, evt);				\
-	}								\
-	USB_DECLARE_EP(ENDPOINT,					\
-		       CONCAT2(NAME, _ep_tx),				\
-		       CONCAT2(NAME, _ep_rx),				\
+#define USB_GPIO_CONFIG(NAME, GPIO_LIST, INTERFACE, ENDPOINT)                  \
+	BUILD_ASSERT(ARRAY_SIZE(GPIO_LIST) <= 32);                             \
+	static usb_uint CONCAT2(                                               \
+		NAME, _ep_rx_buffer)[USB_GPIO_RX_PACKET_SIZE / 2] __usb_ram;   \
+	static usb_uint CONCAT2(                                               \
+		NAME, _ep_tx_buffer)[USB_GPIO_TX_PACKET_SIZE / 2] __usb_ram;   \
+	struct usb_gpio_config const NAME = {                                  \
+		.state = &((struct usb_gpio_state){}),                         \
+		.endpoint = ENDPOINT,                                          \
+		.rx_ram = CONCAT2(NAME, _ep_rx_buffer),                        \
+		.tx_ram = CONCAT2(NAME, _ep_tx_buffer),                        \
+		.gpios = GPIO_LIST,                                            \
+		.num_gpios = ARRAY_SIZE(GPIO_LIST),                            \
+	};                                                                     \
+	const struct usb_interface_descriptor USB_IFACE_DESC(INTERFACE) = {    \
+		.bLength = USB_DT_INTERFACE_SIZE,                              \
+		.bDescriptorType = USB_DT_INTERFACE,                           \
+		.bInterfaceNumber = INTERFACE,                                 \
+		.bAlternateSetting = 0,                                        \
+		.bNumEndpoints = 2,                                            \
+		.bInterfaceClass = USB_CLASS_VENDOR_SPEC,                      \
+		.bInterfaceSubClass = 0,                                       \
+		.bInterfaceProtocol = 0,                                       \
+		.iInterface = 0,                                               \
+	};                                                                     \
+	const struct usb_endpoint_descriptor USB_EP_DESC(INTERFACE, 0) = {     \
+		.bLength = USB_DT_ENDPOINT_SIZE,                               \
+		.bDescriptorType = USB_DT_ENDPOINT,                            \
+		.bEndpointAddress = 0x80 | ENDPOINT,                           \
+		.bmAttributes = 0x02 /* Bulk IN */,                            \
+		.wMaxPacketSize = USB_GPIO_TX_PACKET_SIZE,                     \
+		.bInterval = 10,                                               \
+	};                                                                     \
+	const struct usb_endpoint_descriptor USB_EP_DESC(INTERFACE, 1) = {     \
+		.bLength = USB_DT_ENDPOINT_SIZE,                               \
+		.bDescriptorType = USB_DT_ENDPOINT,                            \
+		.bEndpointAddress = ENDPOINT,                                  \
+		.bmAttributes = 0x02 /* Bulk OUT */,                           \
+		.wMaxPacketSize = USB_GPIO_RX_PACKET_SIZE,                     \
+		.bInterval = 0,                                                \
+	};                                                                     \
+	static void CONCAT2(NAME, _ep_tx)(void)                                \
+	{                                                                      \
+		usb_gpio_tx(&NAME);                                            \
+	}                                                                      \
+	static void CONCAT2(NAME, _ep_rx)(void)                                \
+	{                                                                      \
+		usb_gpio_rx(&NAME);                                            \
+	}                                                                      \
+	static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt)            \
+	{                                                                      \
+		usb_gpio_event(&NAME, evt);                                    \
+	}                                                                      \
+	USB_DECLARE_EP(ENDPOINT, CONCAT2(NAME, _ep_tx), CONCAT2(NAME, _ep_rx), \
 		       CONCAT2(NAME, _ep_event))
 
-
 /*
  * These functions are used by the trampoline functions defined above to
  * connect USB endpoint events with the generic USB GPIO driver.
diff --git a/chip/stm32/usb_hid.c b/chip/stm32/usb_hid.c
index b8336fa0a0..e9426b690d 100644
--- a/chip/stm32/usb_hid.c
+++ b/chip/stm32/usb_hid.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,7 +20,7 @@
 #include "usb_hid_hw.h"
 
 /* Console output macro */
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args)
 
 void hid_tx(int ep)
 {
@@ -41,17 +41,15 @@ void hid_reset(int ep, usb_uint *hid_ep_tx_buf, int tx_len,
 	for (i = 0; i < DIV_ROUND_UP(tx_len, 2); i++)
 		hid_ep_tx_buf[i] = 0;
 
-	ep_reg = (ep << 0) /* Endpoint Address */ |
-		EP_TX_VALID |
-		(3 << 9) /* interrupt EP */ |
-		EP_RX_DISAB;
+	ep_reg = (ep << 0) /* Endpoint Address */ | EP_TX_VALID |
+		 (3 << 9) /* interrupt EP */ | EP_RX_DISAB;
 
 	/* Enable RX for output reports */
 	if (hid_ep_rx_buf && rx_len > 0) {
 		btable_ep[ep].rx_addr = usb_sram_addr(hid_ep_rx_buf);
 		btable_ep[ep].rx_count = ((rx_len + 1) / 2) << 10;
 
-		ep_reg |= EP_RX_VALID;  /* RX Valid */
+		ep_reg |= EP_RX_VALID; /* RX Valid */
 	}
 
 	STM32_USB_EP(ep) = ep_reg;
@@ -73,14 +71,13 @@ static const uint8_t *report_ptr;
  *
  * @return 0 if entire report is sent, 1 if there are remaining data.
  */
-static int send_report(usb_uint *ep0_buf_tx,
-		       const uint8_t *report,
+static int send_report(usb_uint *ep0_buf_tx, const uint8_t *report,
 		       int report_size)
 {
 	int packet_size = MIN(report_size, USB_MAX_PACKET_SIZE);
 
-	memcpy_to_usbram((void *) usb_sram_addr(ep0_buf_tx),
-			 report, packet_size);
+	memcpy_to_usbram((void *)usb_sram_addr(ep0_buf_tx), report,
+			 packet_size);
 	btable_ep[0].tx_count = packet_size;
 	/* report_left != 0 if report doesn't fit in 1 packet. */
 	report_left = report_size - packet_size;
@@ -108,8 +105,8 @@ int hid_iface_request(usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx,
 		if (report_left == 0)
 			return -1;
 		report_size = MIN(USB_MAX_PACKET_SIZE, report_left);
-		memcpy_to_usbram((void *) usb_sram_addr(ep0_buf_tx),
-				 report_ptr, report_size);
+		memcpy_to_usbram((void *)usb_sram_addr(ep0_buf_tx), report_ptr,
+				 report_size);
 		btable_ep[0].tx_count = report_size;
 		report_left -= report_size;
 		report_ptr += report_size;
@@ -117,7 +114,7 @@ int hid_iface_request(usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx,
 				report_left ? 0 : EP_STATUS_OUT);
 		return report_left ? 1 : 0;
 	} else if (ep0_buf_rx[0] == (USB_DIR_IN | USB_RECIP_INTERFACE |
-					(USB_REQ_GET_DESCRIPTOR << 8))) {
+				     (USB_REQ_GET_DESCRIPTOR << 8))) {
 		if (ep0_buf_rx[1] == (USB_HID_DT_REPORT << 8)) {
 			/* Setup : HID specific : Get Report descriptor */
 			return send_report(ep0_buf_tx, report_desc,
@@ -130,10 +127,9 @@ int hid_iface_request(usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx,
 					EP_STATUS_OUT);
 			return 0;
 		}
-	} else if (ep0_buf_rx[0] == (USB_DIR_IN |
-				     USB_RECIP_INTERFACE |
-				     USB_TYPE_CLASS |
-				     (USB_HID_REQ_GET_REPORT << 8))) {
+	} else if (ep0_buf_rx[0] ==
+		   (USB_DIR_IN | USB_RECIP_INTERFACE | USB_TYPE_CLASS |
+		    (USB_HID_REQ_GET_REPORT << 8))) {
 		const uint8_t report_type = (ep0_buf_rx[1] >> 8) & 0xFF;
 		const uint8_t report_id = ep0_buf_rx[1] & 0xFF;
 		int retval;
@@ -142,9 +138,7 @@ int hid_iface_request(usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx,
 		if (!config->get_report) /* not supported */
 			return -1;
 
-		retval = config->get_report(report_id,
-					    report_type,
-					    &report_ptr,
+		retval = config->get_report(report_id, report_type, &report_ptr,
 					    &report_left);
 		if (retval)
 			return retval;
diff --git a/chip/stm32/usb_hid_hw.h b/chip/stm32/usb_hid_hw.h
index a36a66567e..54bfca0808 100644
--- a/chip/stm32/usb_hid_hw.h
+++ b/chip/stm32/usb_hid_hw.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -25,10 +25,8 @@ struct usb_hid_config_t {
 	 * @param buffer_size: handler should set it to the size of returned
 	 *     buffer.
 	 */
-	int (*get_report)(uint8_t report_id,
-			  uint8_t report_type,
-			  const uint8_t **buffer_ptr,
-			  int *buffer_size);
+	int (*get_report)(uint8_t report_id, uint8_t report_type,
+			  const uint8_t **buffer_ptr, int *buffer_size);
 };
 
 /* internal callbacks for HID class drivers */
diff --git a/chip/stm32/usb_hid_keyboard.c b/chip/stm32/usb_hid_keyboard.c
index 99775fd7fb..7f3caac960 100644
--- a/chip/stm32/usb_hid_keyboard.c
+++ b/chip/stm32/usb_hid_keyboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -28,7 +28,7 @@
 #include "usb_hid_hw.h"
 
 /* Console output macro */
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args)
 
 static const int keyboard_debug;
 
@@ -51,7 +51,7 @@ enum hid_protocol {
 static enum hid_protocol protocol = HID_REPORT_PROTOCOL;
 
 #if defined(CONFIG_KEYBOARD_ASSISTANT_KEY) || \
-    defined(CONFIG_KEYBOARD_TABLET_MODE_SWITCH)
+	defined(CONFIG_KEYBOARD_TABLET_MODE_SWITCH)
 #define HID_KEYBOARD_EXTRA_FIELD
 #endif
 
@@ -126,19 +126,20 @@ struct usb_hid_keyboard_output_report {
  * Assistant key is mapped as 0xf0, but this key code is never actually send.
  */
 const uint8_t keycodes[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = {
-	{0x00, 0x00, 0xe0, 0xe3, 0xe4, HID_KEYBOARD_ASSISTANT_KEY, 0x00, 0x00},
-	{0xe3, 0x29, 0x2b, 0x35, 0x04, 0x1d, 0x1e, 0x14},
-	{0x3a, 0x3d, 0x3c, 0x3b, 0x07, 0x06, 0x20, 0x08},
-	{0x05, 0x0a, 0x17, 0x22, 0x09, 0x19, 0x21, 0x15},
-	{0x43, 0x40, 0x3f, 0x3e, 0x16, 0x1b, 0x1f, 0x1a},
-	{0x87, 0x00, 0x30, 0x00, 0x0e, 0x36, 0x25, 0x0c},
-	{0x11, 0x0b, 0x1c, 0x23, 0x0d, 0x10, 0x24, 0x18},
-	{0x00, 0x00, 0x64, 0x00, 0x00, 0xe1, 0x00, 0xe5},
-	{0x2e, 0x34, 0x2F, 0x2d, 0x33, 0x38, 0x27, 0x13},
-	{0x00, 0x42, 0x41, 0x68, 0x0f, 0x37, 0x26, 0x12},
-	{0xe6, 0x00, 0x89, 0x00, 0x31, 0x00, 0xe2, 0x00},
-	{0x00, 0x2a, 0x00, 0x31, 0x28, 0x2c, 0x51, 0x52},
-	{0x00, 0x8a, 0x00, 0x8b, 0x00, 0x00, 0x4f, 0x50},
+	{ 0x00, 0x00, 0xe0, 0xe3, 0xe4, HID_KEYBOARD_ASSISTANT_KEY, 0x00,
+	  0x00 },
+	{ 0xe3, 0x29, 0x2b, 0x35, 0x04, 0x1d, 0x1e, 0x14 },
+	{ 0x3a, 0x3d, 0x3c, 0x3b, 0x07, 0x06, 0x20, 0x08 },
+	{ 0x05, 0x0a, 0x17, 0x22, 0x09, 0x19, 0x21, 0x15 },
+	{ 0x43, 0x40, 0x3f, 0x3e, 0x16, 0x1b, 0x1f, 0x1a },
+	{ 0x87, 0x00, 0x30, 0x00, 0x0e, 0x36, 0x25, 0x0c },
+	{ 0x11, 0x0b, 0x1c, 0x23, 0x0d, 0x10, 0x24, 0x18 },
+	{ 0x00, 0x00, 0x64, 0x00, 0x00, 0xe1, 0x00, 0xe5 },
+	{ 0x2e, 0x34, 0x2F, 0x2d, 0x33, 0x38, 0x27, 0x13 },
+	{ 0x00, 0x42, 0x41, 0x68, 0x0f, 0x37, 0x26, 0x12 },
+	{ 0xe6, 0x00, 0x89, 0x00, 0x31, 0x00, 0xe2, 0x00 },
+	{ 0x00, 0x2a, 0x00, 0x31, 0x28, 0x2c, 0x51, 0x52 },
+	{ 0x00, 0x8a, 0x00, 0x8b, 0x00, 0x00, 0x4f, 0x50 },
 };
 
 /* HID descriptors */
@@ -177,80 +178,84 @@ const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_HID_KEYBOARD, 02) = {
 };
 #endif
 
-#define KEYBOARD_BASE_DESC						\
-	0x05, 0x01, /* Usage Page (Generic Desktop) */			\
-	0x09, 0x06, /* Usage (Keyboard) */				\
-	0xA1, 0x01, /* Collection (Application) */			\
-									\
-	/* Modifiers */							\
-	0x05, 0x07, /* Usage Page (Key Codes) */			\
-	0x19, HID_KEYBOARD_MODIFIER_LOW, /* Usage Minimum */		\
-	0x29, HID_KEYBOARD_MODIFIER_HIGH, /* Usage Maximum */		\
-	0x15, 0x00, /* Logical Minimum (0) */				\
-	0x25, 0x01, /* Logical Maximum (1) */				\
-	0x75, 0x01, /* Report Size (1) */				\
-	0x95, 0x08, /* Report Count (8) */				\
-	0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier byte */ \
-									\
-	0x95, 0x01, /* Report Count (1) */				\
-	0x75, 0x08, /* Report Size (8) */				\
-	0x81, 0x01, /* Input (Constant), ;Reserved byte */		\
-									\
-	/* Normal keys */						\
-	0x95, 0x06, /* Report Count (6) */				\
-	0x75, 0x08, /* Report Size (8) */				\
-	0x15, 0x00, /* Logical Minimum (0) */				\
-	0x25, 0xa4, /* Logical Maximum (164) */				\
-	0x05, 0x07, /* Usage Page (Key Codes) */			\
-	0x19, 0x00, /* Usage Minimum (0) */				\
-	0x29, 0xa4, /* Usage Maximum (164) */				\
-	0x81, 0x00, /* Input (Data, Array), ;Key arrays (6 bytes) */
-
-#define KEYBOARD_TOP_ROW_DESC						\
-	/* Modifiers */							\
-	0x05, 0x0C, /* Consumer Page */					\
-	0x0A, 0x24, 0x02, /* AC Back (0x224) */				\
-	0x0A, 0x25, 0x02, /* AC Forward (0x225) */			\
-	0x0A, 0x27, 0x02, /* AC Refresh (0x227) */			\
-	0x0A, 0x32, 0x02, /* AC View Toggle (0x232) */			\
-	0x0A, 0x9F, 0x02, /* AC Desktop Show All windows (0x29F) */	\
-	0x09, 0x70,       /* Display Brightness Decrement (0x70) */	\
-	0x09, 0x6F,       /* Display Brightness Increment (0x6F) */	\
-	0x09, 0xE2,       /* Mute (0xE2) */				\
-	0x09, 0xEA,       /* Volume Decrement (0xEA) */			\
-	0x09, 0xE9,       /* Volume Increment (0xE9) */			\
-	0x0B, 0x46, 0x00, 0x07, 0x00, /* PrintScreen (Page 0x7, Usage 0x46) */ \
-	0x0A, 0xD0, 0x02, /* Privacy Screen Toggle (0x2D0) */		\
-	0x09, 0x7A,       /* Keyboard Brightness Decrement (0x7A) */	\
-	0x09, 0x79,       /* Keyboard Brightness Increment (0x79)*/	\
-	0x09, 0xCD,       /* Play / Pause (0xCD) */			\
-	0x09, 0xB5,       /* Scan Next Track (0xB5) */			\
-	0x09, 0xB6,       /* Scan Previous Track (0xB6) */		\
-	0x09, 0x7C,       /* Keyboard Backlight OOC (0x7C) */ \
-	0x0B, 0x2F, 0x00, 0x0B, 0x00, /* Phone Mute (Page 0xB, Usage 0x2F) */ \
-	0x09, 0x32,       /* Sleep (0x32) */				\
-	0x15, 0x00, /* Logical Minimum (0) */				\
-	0x25, 0x01, /* Logical Maximum (1) */				\
-	0x75, 0x01, /* Report Size (1) */				\
-	0x95, 0x14, /* Report Count (20) */				\
-	0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier byte */ \
-									\
-	/* 12-bit padding */						\
-	0x95, 0x0C, /* Report Count (12) */				\
-	0x75, 0x01, /* Report Size (1) */				\
-	0x81, 0x01, /* Input (Constant), ;1-bit padding */
-
-#define KEYBOARD_TOP_ROW_FEATURE_DESC					\
-	0x06, 0xd1, 0xff, /* Usage Page (Google) */			\
-	0x09, 0x01,       /* Usage (Top Row List) */			\
-	0xa1, 0x02,       /* Collection (Logical) */			\
-	0x05, 0x0a,       /*   Usage Page (Ordinal) */			\
-	0x19, 0x01,       /*   Usage Minimum (1) */			\
-	0x29, CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS, /* Usage Maximum */	\
-	0x95, CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS, /* Report Count */	\
-	0x75, 0x20,       /*   Report Size (32) */			\
-	0xb1, 0x03,       /*   Feature (Cnst,Var,Abs) */		\
-	0xc0,             /* End Collection */
+#define KEYBOARD_BASE_DESC                                                 \
+	0x05, 0x01, /* Usage Page (Generic Desktop) */                     \
+		0x09, 0x06, /* Usage (Keyboard) */                         \
+		0xA1, 0x01, /* Collection (Application) */                 \
+                                                                           \
+		/* Modifiers */                                            \
+		0x05, 0x07, /* Usage Page (Key Codes) */                   \
+		0x19, HID_KEYBOARD_MODIFIER_LOW, /* Usage Minimum */       \
+		0x29, HID_KEYBOARD_MODIFIER_HIGH, /* Usage Maximum */      \
+		0x15, 0x00, /* Logical Minimum (0) */                      \
+		0x25, 0x01, /* Logical Maximum (1) */                      \
+		0x75, 0x01, /* Report Size (1) */                          \
+		0x95, 0x08, /* Report Count (8) */                         \
+		0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier \
+			       byte */                                     \
+                                                                           \
+		0x95, 0x01, /* Report Count (1) */                         \
+		0x75, 0x08, /* Report Size (8) */                          \
+		0x81, 0x01, /* Input (Constant), ;Reserved byte */         \
+                                                                           \
+		/* Normal keys */                                          \
+		0x95, 0x06, /* Report Count (6) */                         \
+		0x75, 0x08, /* Report Size (8) */                          \
+		0x15, 0x00, /* Logical Minimum (0) */                      \
+		0x25, 0xa4, /* Logical Maximum (164) */                    \
+		0x05, 0x07, /* Usage Page (Key Codes) */                   \
+		0x19, 0x00, /* Usage Minimum (0) */                        \
+		0x29, 0xa4, /* Usage Maximum (164) */                      \
+		0x81, 0x00, /* Input (Data, Array), ;Key arrays (6 bytes) */
+
+#define KEYBOARD_TOP_ROW_DESC                                                 \
+	/* Modifiers */                                                       \
+	0x05, 0x0C, /* Consumer Page */                                       \
+		0x0A, 0x24, 0x02, /* AC Back (0x224) */                       \
+		0x0A, 0x25, 0x02, /* AC Forward (0x225) */                    \
+		0x0A, 0x27, 0x02, /* AC Refresh (0x227) */                    \
+		0x0A, 0x32, 0x02, /* AC View Toggle (0x232) */                \
+		0x0A, 0x9F, 0x02, /* AC Desktop Show All windows (0x29F) */   \
+		0x09, 0x70, /* Display Brightness Decrement (0x70) */         \
+		0x09, 0x6F, /* Display Brightness Increment (0x6F) */         \
+		0x09, 0xE2, /* Mute (0xE2) */                                 \
+		0x09, 0xEA, /* Volume Decrement (0xEA) */                     \
+		0x09, 0xE9, /* Volume Increment (0xE9) */                     \
+		0x0B, 0x46, 0x00, 0x07, 0x00, /* PrintScreen (Page 0x7, Usage \
+						 0x46) */                     \
+		0x0A, 0xD0, 0x02, /* Privacy Screen Toggle (0x2D0) */         \
+		0x09, 0x7A, /* Keyboard Brightness Decrement (0x7A) */        \
+		0x09, 0x79, /* Keyboard Brightness Increment (0x79)*/         \
+		0x09, 0xCD, /* Play / Pause (0xCD) */                         \
+		0x09, 0xB5, /* Scan Next Track (0xB5) */                      \
+		0x09, 0xB6, /* Scan Previous Track (0xB6) */                  \
+		0x09, 0x7C, /* Keyboard Backlight OOC (0x7C) */               \
+		0x0B, 0x2F, 0x00, 0x0B, 0x00, /* Phone Mute (Page 0xB, Usage  \
+						 0x2F) */                     \
+		0x09, 0x32, /* Sleep (0x32) */                                \
+		0x15, 0x00, /* Logical Minimum (0) */                         \
+		0x25, 0x01, /* Logical Maximum (1) */                         \
+		0x75, 0x01, /* Report Size (1) */                             \
+		0x95, 0x14, /* Report Count (20) */                           \
+		0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier    \
+			       byte */                                        \
+                                                                              \
+		/* 12-bit padding */                                          \
+		0x95, 0x0C, /* Report Count (12) */                           \
+		0x75, 0x01, /* Report Size (1) */                             \
+		0x81, 0x01, /* Input (Constant), ;1-bit padding */
+
+#define KEYBOARD_TOP_ROW_FEATURE_DESC                                         \
+	0x06, 0xd1, 0xff, /* Usage Page (Google) */                           \
+		0x09, 0x01, /* Usage (Top Row List) */                        \
+		0xa1, 0x02, /* Collection (Logical) */                        \
+		0x05, 0x0a, /*   Usage Page (Ordinal) */                      \
+		0x19, 0x01, /*   Usage Minimum (1) */                         \
+		0x29, CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS, /* Usage Maximum */ \
+		0x95, CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS, /* Report Count */  \
+		0x75, 0x20, /*   Report Size (32) */                          \
+		0xb1, 0x03, /*   Feature (Cnst,Var,Abs) */                    \
+		0xc0, /* End Collection */
 
 /*
  * Vendor-defined Usage Page 0xffd1:
@@ -259,60 +264,62 @@ const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_HID_KEYBOARD, 02) = {
  */
 #ifdef HID_KEYBOARD_EXTRA_FIELD
 #ifdef CONFIG_KEYBOARD_ASSISTANT_KEY
-#define KEYBOARD_ASSISTANT_KEY_DESC					\
-	0x19, 0x18, /* Usage Minimum */					\
-	0x29, 0x18, /* Usage Maximum */					\
-	0x15, 0x00, /* Logical Minimum (0) */				\
-	0x25, 0x01, /* Logical Maximum (1) */				\
-	0x75, 0x01, /* Report Size (1) */				\
-	0x95, 0x01, /* Report Count (1) */				\
-	0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier byte */
+#define KEYBOARD_ASSISTANT_KEY_DESC                                        \
+	0x19, 0x18, /* Usage Minimum */                                    \
+		0x29, 0x18, /* Usage Maximum */                            \
+		0x15, 0x00, /* Logical Minimum (0) */                      \
+		0x25, 0x01, /* Logical Maximum (1) */                      \
+		0x75, 0x01, /* Report Size (1) */                          \
+		0x95, 0x01, /* Report Count (1) */                         \
+		0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier \
+			       byte */
 #else
 /* No assistant key: just pad 1 bit. */
-#define KEYBOARD_ASSISTANT_KEY_DESC					\
-	0x95, 0x01, /* Report Count (1) */				\
-	0x75, 0x01, /* Report Size (1) */				\
-	0x81, 0x01, /* Input (Constant), ;1-bit padding */
+#define KEYBOARD_ASSISTANT_KEY_DESC               \
+	0x95, 0x01, /* Report Count (1) */        \
+		0x75, 0x01, /* Report Size (1) */ \
+		0x81, 0x01, /* Input (Constant), ;1-bit padding */
 #endif /* !CONFIG_KEYBOARD_ASSISTANT_KEY */
 
 #ifdef CONFIG_KEYBOARD_TABLET_MODE_SWITCH
-#define KEYBOARD_TABLET_MODE_SWITCH_DESC				\
-	0x19, 0x19, /* Usage Minimum */					\
-	0x29, 0x19, /* Usage Maximum */					\
-	0x15, 0x00, /* Logical Minimum (0) */				\
-	0x25, 0x01, /* Logical Maximum (1) */				\
-	0x75, 0x01, /* Report Size (1) */				\
-	0x95, 0x01, /* Report Count (1) */				\
-	0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier byte */
+#define KEYBOARD_TABLET_MODE_SWITCH_DESC                                   \
+	0x19, 0x19, /* Usage Minimum */                                    \
+		0x29, 0x19, /* Usage Maximum */                            \
+		0x15, 0x00, /* Logical Minimum (0) */                      \
+		0x25, 0x01, /* Logical Maximum (1) */                      \
+		0x75, 0x01, /* Report Size (1) */                          \
+		0x95, 0x01, /* Report Count (1) */                         \
+		0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier \
+			       byte */
 #else
 /* No tablet mode swtch: just pad 1 bit. */
-#define KEYBOARD_TABLET_MODE_SWITCH_DESC				\
-	0x95, 0x01, /* Report Count (1) */				\
-	0x75, 0x01, /* Report Size (1) */				\
-	0x81, 0x01, /* Input (Constant), ;1-bit padding */
+#define KEYBOARD_TABLET_MODE_SWITCH_DESC          \
+	0x95, 0x01, /* Report Count (1) */        \
+		0x75, 0x01, /* Report Size (1) */ \
+		0x81, 0x01, /* Input (Constant), ;1-bit padding */
 #endif /* CONFIG_KEYBOARD_TABLET_MODE_SWITCH */
 
-#define KEYBOARD_VENDOR_DESC						\
-	0x06, 0xd1, 0xff, /* Usage Page (Vendor-defined 0xffd1) */	\
-									\
-	KEYBOARD_ASSISTANT_KEY_DESC					\
-	KEYBOARD_TABLET_MODE_SWITCH_DESC				\
-									\
-	0x95, 0x01, /* Report Count (1) */				\
-	0x75, 0x06, /* Report Size (6) */				\
-	0x81, 0x01, /* Input (Constant), ;6-bit padding */
+#define KEYBOARD_VENDOR_DESC                                                 \
+	0x06, 0xd1, 0xff, /* Usage Page (Vendor-defined 0xffd1) */           \
+                                                                             \
+		KEYBOARD_ASSISTANT_KEY_DESC KEYBOARD_TABLET_MODE_SWITCH_DESC \
+                                                                             \
+		0x95,                                                        \
+		0x01, /* Report Count (1) */                                 \
+		0x75, 0x06, /* Report Size (6) */                            \
+		0x81, 0x01, /* Input (Constant), ;6-bit padding */
 #endif /* HID_KEYBOARD_EXTRA_FIELD */
 
-#define KEYBOARD_BACKLIGHT_DESC \
-	0xA1, 0x02, /* Collection (Logical) */				\
-	0x05, 0x14, /*   Usage Page (Alphanumeric Display) */		\
-	0x09, 0x46, /*   Usage (Display Brightness) */			\
-	0x95, 0x01, /*   Report Count (1) */				\
-	0x75, 0x08, /*   Report Size (8) */				\
-	0x15, 0x00, /*   Logical Minimum (0) */				\
-	0x25, 0x64, /*   Logical Maximum (100) */			\
-	0x91, 0x02, /*   Output (Data, Variable, Absolute) */		\
-	0xC0,       /* End Collection */
+#define KEYBOARD_BACKLIGHT_DESC                                       \
+	0xA1, 0x02, /* Collection (Logical) */                        \
+		0x05, 0x14, /*   Usage Page (Alphanumeric Display) */ \
+		0x09, 0x46, /*   Usage (Display Brightness) */        \
+		0x95, 0x01, /*   Report Count (1) */                  \
+		0x75, 0x08, /*   Report Size (8) */                   \
+		0x15, 0x00, /*   Logical Minimum (0) */               \
+		0x25, 0x64, /*   Logical Maximum (100) */             \
+		0x91, 0x02, /*   Output (Data, Variable, Absolute) */ \
+		0xC0, /* End Collection */
 
 /*
  * To allow dynamic detection of keyboard backlights, we define two descriptors.
@@ -325,17 +332,15 @@ static const uint8_t report_desc[] = {
 	KEYBOARD_BASE_DESC
 
 #ifdef KEYBOARD_VENDOR_DESC
-	KEYBOARD_VENDOR_DESC
+		KEYBOARD_VENDOR_DESC
 #endif
 
 #ifdef CONFIG_USB_HID_KEYBOARD_VIVALDI
-	KEYBOARD_TOP_ROW_DESC
-	KEYBOARD_TOP_ROW_FEATURE_DESC
+			KEYBOARD_TOP_ROW_DESC KEYBOARD_TOP_ROW_FEATURE_DESC
 #endif
-	0xC0        /* End Collection */
+	0xC0 /* End Collection */
 };
 
-
 #ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT
 
 /* HID : Report Descriptor with keyboard backlight */
@@ -344,32 +349,29 @@ static const uint8_t report_desc_with_backlight[] = {
 	KEYBOARD_BASE_DESC
 
 #ifdef KEYBOARD_VENDOR_DESC
-	KEYBOARD_VENDOR_DESC
+		KEYBOARD_VENDOR_DESC
 #endif
 
 #ifdef CONFIG_USB_HID_KEYBOARD_VIVALDI
-	KEYBOARD_TOP_ROW_DESC
-	KEYBOARD_TOP_ROW_FEATURE_DESC
+			KEYBOARD_TOP_ROW_DESC KEYBOARD_TOP_ROW_FEATURE_DESC
 #endif
-	KEYBOARD_BACKLIGHT_DESC
+				KEYBOARD_BACKLIGHT_DESC
 
-	0xC0        /* End Collection */
+	0xC0 /* End Collection */
 };
 
 #endif
 
 /* HID: HID Descriptor */
-const struct usb_hid_descriptor USB_CUSTOM_DESC_VAR(USB_IFACE_HID_KEYBOARD,
-						hid, hid_desc_kb) = {
+const struct usb_hid_descriptor USB_CUSTOM_DESC_VAR(USB_IFACE_HID_KEYBOARD, hid,
+						    hid_desc_kb) = {
 	.bLength = 9,
 	.bDescriptorType = USB_HID_DT_HID,
 	.bcdHID = 0x0100,
 	.bCountryCode = 0x00, /* Hardware target country */
 	.bNumDescriptors = 1,
-	.desc = {{
-		.bDescriptorType = USB_HID_DT_REPORT,
-		.wDescriptorLength = sizeof(report_desc)
-	}}
+	.desc = { { .bDescriptorType = USB_HID_DT_REPORT,
+		    .wDescriptorLength = sizeof(report_desc) } }
 };
 
 #define EP_TX_BUF_SIZE DIV_ROUND_UP(HID_KEYBOARD_REPORT_SIZE, 2)
@@ -403,10 +405,10 @@ static void write_keyboard_report(void)
 		 * send the buffer: enable TX.
 		 */
 
-		memcpy_to_usbram((void *) usb_sram_addr(hid_ep_tx_buf),
-				&report, sizeof(report));
-		STM32_TOGGLE_EP(USB_EP_HID_KEYBOARD, EP_TX_MASK,
-				EP_TX_VALID, 0);
+		memcpy_to_usbram((void *)usb_sram_addr(hid_ep_tx_buf), &report,
+				 sizeof(report));
+		STM32_TOGGLE_EP(USB_EP_HID_KEYBOARD, EP_TX_MASK, EP_TX_VALID,
+				0);
 	}
 
 	/*
@@ -422,7 +424,7 @@ static void write_keyboard_report(void)
 static void hid_keyboard_rx(void)
 {
 	struct usb_hid_keyboard_output_report report;
-	memcpy_from_usbram(&report, (void *) usb_sram_addr(hid_ep_rx_buf),
+	memcpy_from_usbram(&report, (void *)usb_sram_addr(hid_ep_rx_buf),
 			   HID_KEYBOARD_OUTPUT_REPORT_SIZE);
 
 	CPRINTF("Keyboard backlight set to %d%%\n", report.brightness);
@@ -439,10 +441,10 @@ static void hid_keyboard_tx(void)
 {
 	hid_tx(USB_EP_HID_KEYBOARD);
 	if (hid_ep_data_ready) {
-		memcpy_to_usbram((void *) usb_sram_addr(hid_ep_tx_buf),
-				&report, sizeof(report));
-		STM32_TOGGLE_EP(USB_EP_HID_KEYBOARD, EP_TX_MASK,
-				EP_TX_VALID, 0);
+		memcpy_to_usbram((void *)usb_sram_addr(hid_ep_tx_buf), &report,
+				 sizeof(report));
+		STM32_TOGGLE_EP(USB_EP_HID_KEYBOARD, EP_TX_MASK, EP_TX_VALID,
+				0);
 		hid_ep_data_ready = 0;
 	}
 
@@ -455,16 +457,14 @@ static void hid_keyboard_event(enum usb_ep_event evt)
 	if (evt == USB_EVENT_RESET) {
 		protocol = HID_REPORT_PROTOCOL;
 
-		hid_reset(USB_EP_HID_KEYBOARD,
-			  hid_ep_tx_buf,
+		hid_reset(USB_EP_HID_KEYBOARD, hid_ep_tx_buf,
 			  HID_KEYBOARD_REPORT_SIZE,
 #ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT
-			  hid_ep_rx_buf,
-			  HID_KEYBOARD_OUTPUT_REPORT_SIZE
+			  hid_ep_rx_buf, HID_KEYBOARD_OUTPUT_REPORT_SIZE
 #else
 			  NULL, 0
 #endif
-			  );
+		);
 
 		/*
 		 * Reload endpoint on reset, to make sure we report accurate
@@ -547,8 +547,8 @@ static int hid_keyboard_get_report(uint8_t report_id, uint8_t report_type,
 #ifdef CONFIG_USB_HID_KEYBOARD_VIVALDI
 	if (report_type == REPORT_TYPE_FEATURE) {
 		*buffer_ptr = (uint8_t *)feature_report;
-		*buffer_size = (sizeof(uint32_t) *
-				CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS);
+		*buffer_size =
+			(sizeof(uint32_t) * CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS);
 		return 0;
 	}
 #endif
@@ -572,8 +572,9 @@ static int hid_keyboard_iface_request(usb_uint *ep0_buf_rx,
 	if (ret >= 0)
 		return ret;
 
-	if (ep0_buf_rx[0] == (USB_DIR_OUT | USB_TYPE_CLASS |
-		       USB_RECIP_INTERFACE | (USB_HID_REQ_SET_PROTOCOL << 8))) {
+	if (ep0_buf_rx[0] ==
+	    (USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_INTERFACE |
+	     (USB_HID_REQ_SET_PROTOCOL << 8))) {
 		uint16_t value = ep0_buf_rx[1];
 
 		if (value >= HID_PROTOCOL_COUNT)
@@ -584,19 +585,21 @@ static int hid_keyboard_iface_request(usb_uint *ep0_buf_rx,
 		/* Reload endpoint with appropriate tx_count. */
 		btable_ep[USB_EP_HID_KEYBOARD].tx_count =
 			(protocol == HID_BOOT_PROTOCOL) ?
-			HID_KEYBOARD_BOOT_SIZE : HID_KEYBOARD_REPORT_SIZE;
-		STM32_TOGGLE_EP(USB_EP_HID_KEYBOARD, EP_TX_MASK,
-				EP_TX_VALID, 0);
+				HID_KEYBOARD_BOOT_SIZE :
+				HID_KEYBOARD_REPORT_SIZE;
+		STM32_TOGGLE_EP(USB_EP_HID_KEYBOARD, EP_TX_MASK, EP_TX_VALID,
+				0);
 
 		btable_ep[0].tx_count = 0;
 		STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0);
 		return 0;
-	} else if (ep0_buf_rx[0] == (USB_DIR_IN | USB_TYPE_CLASS |
-		       USB_RECIP_INTERFACE | (USB_HID_REQ_GET_PROTOCOL << 8))) {
+	} else if (ep0_buf_rx[0] ==
+		   (USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_INTERFACE |
+		    (USB_HID_REQ_GET_PROTOCOL << 8))) {
 		uint8_t value = protocol;
 
-		memcpy_to_usbram((void *) usb_sram_addr(ep0_buf_tx),
-				 &value, sizeof(value));
+		memcpy_to_usbram((void *)usb_sram_addr(ep0_buf_tx), &value,
+				 sizeof(value));
 		btable_ep[0].tx_count = 1;
 		STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0);
 		return 0;
@@ -615,7 +618,7 @@ void keyboard_clear_buffer(void)
 	memset(&report, 0, sizeof(report));
 #ifdef CONFIG_KEYBOARD_TABLET_MODE_SWITCH
 	if (tablet_get_mode())
-		report.extra |= 0x01 <<	(HID_KEYBOARD_TABLET_MODE_SWITCH -
+		report.extra |= 0x01 << (HID_KEYBOARD_TABLET_MODE_SWITCH -
 					 HID_KEYBOARD_EXTRA_LOW);
 #endif
 	write_keyboard_report();
@@ -648,7 +651,7 @@ static uint32_t maybe_convert_function_key(int keycode)
 		return SLEEP_KEY_MASK;
 
 	if (index >= config->num_top_row_keys ||
-			config->action_keys[index] == TK_ABSENT)
+	    config->action_keys[index] == TK_ABSENT)
 		return 0; /* not mapped */
 	return action_key[config->action_keys[index]].mask;
 }
@@ -666,8 +669,8 @@ static void keyboard_process_queue(void)
 	if (keyboard_debug)
 		CPRINTF("Q%d (s%d ep%d hw%d)\n", queue_count(&key_queue),
 			usb_is_suspended(), hid_ep_data_ready,
-			(STM32_USB_EP(USB_EP_HID_KEYBOARD) & EP_TX_MASK)
-			== EP_TX_VALID);
+			(STM32_USB_EP(USB_EP_HID_KEYBOARD) & EP_TX_MASK) ==
+				EP_TX_VALID);
 	mutex_lock(&key_queue_mutex);
 
 	if (queue_count(&key_queue) == 0) {
@@ -728,7 +731,7 @@ static void keyboard_process_queue(void)
 			valid = 1;
 #endif
 		} else if (ev.keycode >= HID_KEYBOARD_EXTRA_LOW &&
-		    ev.keycode <= HID_KEYBOARD_EXTRA_HIGH) {
+			   ev.keycode <= HID_KEYBOARD_EXTRA_HIGH) {
 #ifdef HID_KEYBOARD_EXTRA_FIELD
 			mask = 0x01 << (ev.keycode - HID_KEYBOARD_EXTRA_LOW);
 			if (ev.pressed)
@@ -738,7 +741,7 @@ static void keyboard_process_queue(void)
 			valid = 1;
 #endif
 		} else if (ev.keycode >= HID_KEYBOARD_MODIFIER_LOW &&
-		    ev.keycode <= HID_KEYBOARD_MODIFIER_HIGH) {
+			   ev.keycode <= HID_KEYBOARD_MODIFIER_HIGH) {
 			mask = 0x01 << (ev.keycode - HID_KEYBOARD_MODIFIER_LOW);
 			if (ev.pressed)
 				report.modifiers |= mask;
@@ -805,7 +808,7 @@ static void tablet_mode_change(void)
 }
 DECLARE_HOOK(HOOK_TABLET_MODE_CHANGE, tablet_mode_change, HOOK_PRIO_DEFAULT);
 /* Run after tablet_mode_init. */
-DECLARE_HOOK(HOOK_INIT, tablet_mode_change, HOOK_PRIO_DEFAULT+1);
+DECLARE_HOOK(HOOK_INIT, tablet_mode_change, HOOK_PRIO_DEFAULT + 1);
 #endif
 
 void keyboard_state_changed(int row, int col, int is_pressed)
@@ -821,7 +824,8 @@ void keyboard_state_changed(int row, int col, int is_pressed)
 }
 
 void clear_typematic_key(void)
-{ }
+{
+}
 
 #ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT
 void usb_hid_keyboard_init(void)
@@ -831,8 +835,8 @@ void usb_hid_keyboard_init(void)
 		hid_config_kb.report_size = sizeof(report_desc_with_backlight);
 
 		set_descriptor_patch(USB_DESC_KEYBOARD_BACKLIGHT,
-			&hid_desc_kb.desc[0].wDescriptorLength,
-			sizeof(report_desc_with_backlight));
+				     &hid_desc_kb.desc[0].wDescriptorLength,
+				     sizeof(report_desc_with_backlight));
 	}
 }
 /* This needs to happen before usb_init (HOOK_PRIO_DEFAULT) */
diff --git a/chip/stm32/usb_hid_touchpad.c b/chip/stm32/usb_hid_touchpad.c
index 0ead660432..15dd38756f 100644
--- a/chip/stm32/usb_hid_touchpad.c
+++ b/chip/stm32/usb_hid_touchpad.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,16 +24,16 @@
 #include "usb_hid_touchpad.h"
 
 /* Console output macro */
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USB, format, ##args)
 
 static const int touchpad_debug;
 
-static struct queue const report_queue = QUEUE_NULL(8,
-						struct usb_hid_touchpad_report);
+static struct queue const report_queue =
+	QUEUE_NULL(8, struct usb_hid_touchpad_report);
 static struct mutex report_queue_mutex;
 
-#define HID_TOUCHPAD_REPORT_SIZE  sizeof(struct usb_hid_touchpad_report)
+#define HID_TOUCHPAD_REPORT_SIZE sizeof(struct usb_hid_touchpad_report)
 
 /*
  * Touchpad EP interval: Make sure this value is smaller than the typical
@@ -65,58 +65,63 @@ const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_HID_TOUCHPAD, 81) = {
 	.bInterval = HID_TOUCHPAD_EP_INTERVAL_MS /* polling interval */
 };
 
-#define FINGER_USAGE \
-	0x05, 0x0D,        /*   Usage Page (Digitizer) */ \
-	0x09, 0x22,        /*   Usage (Finger) */ \
-	0xA1, 0x02,        /*   Collection (Logical) */ \
-	0x09, 0x47,        /*     Usage (Confidence) */ \
-	0x09, 0x42,        /*     Usage (Tip Switch) */ \
-	0x09, 0x32,        /*     Usage (In Range) */ \
-	0x15, 0x00,        /*     Logical Minimum (0) */ \
-	0x25, 0x01,        /*     Logical Maximum (1) */ \
-	0x75, 0x01,        /*     Report Size (1) */ \
-	0x95, 0x03,        /*     Report Count (3) */ \
-	0x81, 0x02,        /*     Input (Data,Var,Abs) */ \
-	0x09, 0x51,        /*     Usage (0x51) Contact identifier */ \
-	0x75, 0x04,        /*     Report Size (4) */ \
-	0x95, 0x01,        /*     Report Count (1) */ \
-	0x25, 0x0F,        /*     Logical Maximum (15) */ \
-	0x81, 0x02,        /*     Input (Data,Var,Abs) */ \
-	0x05, 0x0D,        /*     Usage Page (Digitizer) */ \
-			   /*     Logical Maximum of Pressure */ \
-	0x26, (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE & 0xFF), \
-	      (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE >> 8), \
-	0x75, 0x09,        /*     Report Size (9) */ \
-	0x09, 0x30,        /*     Usage (Tip pressure) */ \
-	0x81, 0x02,        /*     Input (Data,Var,Abs) */ \
-	0x26, 0xFF, 0x0F,  /*     Logical Maximum (4095) */ \
-	0x75, 0x0C,        /*     Report Size (12) */ \
-	0x09, 0x48,        /*     Usage (WIDTH) */ \
-	0x81, 0x02,        /*     Input (Data,Var,Abs) */ \
-	0x09, 0x49,        /*     Usage (HEIGHT) */ \
-	0x81, 0x02,        /*     Input (Data,Var,Abs) */ \
-	0x05, 0x01,        /*     Usage Page (Generic Desktop Ctrls) */ \
-	0x75, 0x0C,        /*     Report Size (12) */ \
-	0x55, 0x0E,        /*     Unit Exponent (-2) */ \
-	0x65, 0x11,        /*     Unit (System: SI Linear, Length: cm) */ \
-	0x09, 0x30,        /*     Usage (X) */ \
-	0x35, 0x00,        /*     Physical Minimum (0) */ \
-	0x26, (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X & 0xff), \
-	      (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X >> 8), \
-	                   /*     Logical Maximum */ \
-	0x46, (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X & 0xff), \
-	      (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X >> 8), \
-	                   /*     Physical Maximum (tenth of mm) */ \
-	0x81, 0x02,        /*     Input (Data,Var,Abs) */ \
-	0x26, (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y & 0xff), \
-	      (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y >> 8), \
-	                   /*     Logical Maximum */ \
-	0x46, (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y & 0xff), \
-	      (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y >> 8), \
-	                   /*     Physical Maximum (tenth of mm) */ \
-	0x09, 0x31,        /*     Usage (Y) */ \
-	0x81, 0x02,        /*     Input (Data,Var,Abs) */ \
-	0xC0               /*   End Collection */
+#define FINGER_USAGE                                                           \
+	0x05, 0x0D, /*   Usage Page (Digitizer) */                             \
+		0x09, 0x22, /*   Usage (Finger) */                             \
+		0xA1, 0x02, /*   Collection (Logical) */                       \
+		0x09, 0x47, /*     Usage (Confidence) */                       \
+		0x09, 0x42, /*     Usage (Tip Switch) */                       \
+		0x09, 0x32, /*     Usage (In Range) */                         \
+		0x15, 0x00, /*     Logical Minimum (0) */                      \
+		0x25, 0x01, /*     Logical Maximum (1) */                      \
+		0x75, 0x01, /*     Report Size (1) */                          \
+		0x95, 0x03, /*     Report Count (3) */                         \
+		0x81, 0x02, /*     Input (Data,Var,Abs) */                     \
+		0x09, 0x51, /*     Usage (0x51) Contact identifier */          \
+		0x75, 0x04, /*     Report Size (4) */                          \
+		0x95, 0x01, /*     Report Count (1) */                         \
+		0x25, 0x0F, /*     Logical Maximum (15) */                     \
+		0x81, 0x02, /*     Input (Data,Var,Abs) */                     \
+		0x05, 0x0D, /*     Usage Page (Digitizer) */ /*     Logical    \
+								Maximum of     \
+								Pressure */    \
+		0x26, (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE & 0xFF),   \
+		(CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE >> 8), 0x75,     \
+		0x09, /*     Report Size (9) */                                \
+		0x09, 0x30, /*     Usage (Tip pressure) */                     \
+		0x81, 0x02, /*     Input (Data,Var,Abs) */                     \
+		0x26, 0xFF, 0x0F, /*     Logical Maximum (4095) */             \
+		0x75, 0x0C, /*     Report Size (12) */                         \
+		0x09, 0x48, /*     Usage (WIDTH) */                            \
+		0x81, 0x02, /*     Input (Data,Var,Abs) */                     \
+		0x09, 0x49, /*     Usage (HEIGHT) */                           \
+		0x81, 0x02, /*     Input (Data,Var,Abs) */                     \
+		0x05, 0x01, /*     Usage Page (Generic Desktop Ctrls) */       \
+		0x75, 0x0C, /*     Report Size (12) */                         \
+		0x55, 0x0E, /*     Unit Exponent (-2) */                       \
+		0x65, 0x11, /*     Unit (System: SI Linear, Length: cm) */     \
+		0x09, 0x30, /*     Usage (X) */                                \
+		0x35, 0x00, /*     Physical Minimum (0) */                     \
+		0x26, (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X & 0xff),          \
+		(CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X >> 8), /*     Logical   \
+								 Maximum */    \
+		0x46, (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X & 0xff),         \
+		(CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X >> 8), /*     Physical \
+								  Maximum      \
+								  (tenth of    \
+								  mm) */       \
+		0x81, 0x02, /*     Input (Data,Var,Abs) */                     \
+		0x26, (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y & 0xff),          \
+		(CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y >> 8), /*     Logical   \
+								 Maximum */    \
+		0x46, (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y & 0xff),         \
+		(CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y >> 8), /*     Physical \
+								  Maximum      \
+								  (tenth of    \
+								  mm) */       \
+		0x09, 0x31, /*     Usage (Y) */                                \
+		0x81, 0x02, /*     Input (Data,Var,Abs) */                     \
+		0xC0 /*   End Collection */
 
 /*
  * HID: Report Descriptor
@@ -125,10 +130,10 @@ const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_HID_TOUCHPAD, 81) = {
  */
 static const uint8_t report_desc[] = {
 	/* Touchpad Collection */
-	0x05, 0x0D,                    /* Usage Page (Digitizer) */
-	0x09, 0x05,                    /* Usage (Touch Pad) */
-	0xA1, 0x01,                    /* Collection (Application) */
-	0x85, REPORT_ID_TOUCHPAD,      /*   Report ID (1, Touch) */
+	0x05, 0x0D, /* Usage Page (Digitizer) */
+	0x09, 0x05, /* Usage (Touch Pad) */
+	0xA1, 0x01, /* Collection (Application) */
+	0x85, REPORT_ID_TOUCHPAD, /*   Report ID (1, Touch) */
 	/* Finger 0 */
 	FINGER_USAGE,
 	/* Finger 1 */
@@ -140,52 +145,52 @@ static const uint8_t report_desc[] = {
 	/* Finger 4 */
 	FINGER_USAGE,
 	/* Contact count */
-	0x05, 0x0D,                    /*   Usage Page (Digitizer) */
-	0x09, 0x54,                    /*   Usage (Contact count) */
-	0x25, MAX_FINGERS,             /*   Logical Maximum (MAX_FINGERS) */
-	0x75, 0x07,                    /*   Report Size (7) */
-	0x95, 0x01,                    /*   Report Count (1) */
-	0x81, 0x02,                    /*   Input (Data,Var,Abs) */
+	0x05, 0x0D, /*   Usage Page (Digitizer) */
+	0x09, 0x54, /*   Usage (Contact count) */
+	0x25, MAX_FINGERS, /*   Logical Maximum (MAX_FINGERS) */
+	0x75, 0x07, /*   Report Size (7) */
+	0x95, 0x01, /*   Report Count (1) */
+	0x81, 0x02, /*   Input (Data,Var,Abs) */
 	/* Button */
-	0x05, 0x01,                    /*   Usage Page(Generic Desktop Ctrls) */
-	0x05, 0x09,                    /*   Usage (Button) */
-	0x19, 0x01,                    /*   Usage Minimum (0x01) */
-	0x29, 0x01,                    /*   Usage Maximum (0x01) */
-	0x15, 0x00,                    /*   Logical Minimum (0) */
-	0x25, 0x01,                    /*   Logical Maximum (1) */
-	0x75, 0x01,                    /*   Report Size (1) */
-	0x95, 0x01,                    /*   Report Count (1) */
-	0x81, 0x02,                    /*   Input (Data,Var,Abs) */
+	0x05, 0x01, /*   Usage Page(Generic Desktop Ctrls) */
+	0x05, 0x09, /*   Usage (Button) */
+	0x19, 0x01, /*   Usage Minimum (0x01) */
+	0x29, 0x01, /*   Usage Maximum (0x01) */
+	0x15, 0x00, /*   Logical Minimum (0) */
+	0x25, 0x01, /*   Logical Maximum (1) */
+	0x75, 0x01, /*   Report Size (1) */
+	0x95, 0x01, /*   Report Count (1) */
+	0x81, 0x02, /*   Input (Data,Var,Abs) */
 	/* Timestamp */
-	0x05, 0x0D,                    /*   Usage Page (Digitizer) */
-	0x55, 0x0C,                    /*   Unit Exponent (-4) */
-	0x66, 0x01, 0x10,              /*   Unit (Seconds) */
-	0x47, 0xFF, 0xFF, 0x00, 0x00,  /*   Physical Maximum (65535) */
-	0x27, 0xFF, 0xFF, 0x00, 0x00,  /*   Logical Maximum (65535) */
-	0x75, 0x10,                    /*   Report Size (16) */
-	0x95, 0x01,                    /*   Report Count (1) */
-	0x09, 0x56,                    /*   Usage (0x56, Relative Scan Time) */
-	0x81, 0x02,                    /*   Input (Data,Var,Abs) */
-
-	0x85, REPORT_ID_DEVICE_CAPS,   /*   Report ID (Device Capabilities) */
-	0x09, 0x55,                    /*   Usage (Contact Count Maximum) */
-	0x09, 0x59,                    /*   Usage (Pad Type) */
-	0x25, 0x0F,                    /*   Logical Maximum (15) */
-	0x75, 0x08,                    /*   Report Size (8) */
-	0x95, 0x02,                    /*   Report Count (2) */
-	0xB1, 0x02,                    /*   Feature (Data,Var,Abs) */
+	0x05, 0x0D, /*   Usage Page (Digitizer) */
+	0x55, 0x0C, /*   Unit Exponent (-4) */
+	0x66, 0x01, 0x10, /*   Unit (Seconds) */
+	0x47, 0xFF, 0xFF, 0x00, 0x00, /*   Physical Maximum (65535) */
+	0x27, 0xFF, 0xFF, 0x00, 0x00, /*   Logical Maximum (65535) */
+	0x75, 0x10, /*   Report Size (16) */
+	0x95, 0x01, /*   Report Count (1) */
+	0x09, 0x56, /*   Usage (0x56, Relative Scan Time) */
+	0x81, 0x02, /*   Input (Data,Var,Abs) */
+
+	0x85, REPORT_ID_DEVICE_CAPS, /*   Report ID (Device Capabilities) */
+	0x09, 0x55, /*   Usage (Contact Count Maximum) */
+	0x09, 0x59, /*   Usage (Pad Type) */
+	0x25, 0x0F, /*   Logical Maximum (15) */
+	0x75, 0x08, /*   Report Size (8) */
+	0x95, 0x02, /*   Report Count (2) */
+	0xB1, 0x02, /*   Feature (Data,Var,Abs) */
 
 	/* Page 0xFF, usage 0xC5 is device certificate. */
-	0x06, 0x00, 0xFF,              /*   Usage Page (Vendor Defined) */
-	0x85, REPORT_ID_DEVICE_CERT,   /*   Report ID (Device Certification) */
-	0x09, 0xC5,                    /*   Usage (Vendor Usage 0xC5) */
-	0x15, 0x00,                    /*   Logical Minimum (0) */
-	0x26, 0xFF, 0x00,              /*   Logical Maximum (255) */
-	0x75, 0x08,                    /*   Report Size (8) */
-	0x96, 0x00, 0x01,              /*   Report Count (256) */
-	0xB1, 0x02,                    /*   Feature (Data,Var,Abs) */
-
-	0xC0,                          /* End Collection */
+	0x06, 0x00, 0xFF, /*   Usage Page (Vendor Defined) */
+	0x85, REPORT_ID_DEVICE_CERT, /*   Report ID (Device Certification) */
+	0x09, 0xC5, /*   Usage (Vendor Usage 0xC5) */
+	0x15, 0x00, /*   Logical Minimum (0) */
+	0x26, 0xFF, 0x00, /*   Logical Maximum (255) */
+	0x75, 0x08, /*   Report Size (8) */
+	0x96, 0x00, 0x01, /*   Report Count (256) */
+	0xB1, 0x02, /*   Feature (Data,Var,Abs) */
+
+	0xC0, /* End Collection */
 };
 
 /* A 256-byte default blob for the 'device certification status' feature report.
@@ -195,59 +200,281 @@ static const uint8_t report_desc[] = {
 static const uint8_t device_cert_response[] = {
 	REPORT_ID_DEVICE_CERT,
 
-	0xFC, 0x28, 0xFE, 0x84, 0x40, 0xCB, 0x9A, 0x87,
-	0x0D, 0xBE, 0x57, 0x3C, 0xB6, 0x70, 0x09, 0x88,
-	0x07, 0x97, 0x2D, 0x2B, 0xE3, 0x38, 0x34, 0xB6,
-	0x6C, 0xED, 0xB0, 0xF7, 0xE5, 0x9C, 0xF6, 0xC2,
-	0x2E, 0x84, 0x1B, 0xE8, 0xB4, 0x51, 0x78, 0x43,
-	0x1F, 0x28, 0x4B, 0x7C, 0x2D, 0x53, 0xAF, 0xFC,
-	0x47, 0x70, 0x1B, 0x59, 0x6F, 0x74, 0x43, 0xC4,
-	0xF3, 0x47, 0x18, 0x53, 0x1A, 0xA2, 0xA1, 0x71,
-	0xC7, 0x95, 0x0E, 0x31, 0x55, 0x21, 0xD3, 0xB5,
-	0x1E, 0xE9, 0x0C, 0xBA, 0xEC, 0xB8, 0x89, 0x19,
-	0x3E, 0xB3, 0xAF, 0x75, 0x81, 0x9D, 0x53, 0xB9,
-	0x41, 0x57, 0xF4, 0x6D, 0x39, 0x25, 0x29, 0x7C,
-	0x87, 0xD9, 0xB4, 0x98, 0x45, 0x7D, 0xA7, 0x26,
-	0x9C, 0x65, 0x3B, 0x85, 0x68, 0x89, 0xD7, 0x3B,
-	0xBD, 0xFF, 0x14, 0x67, 0xF2, 0x2B, 0xF0, 0x2A,
-	0x41, 0x54, 0xF0, 0xFD, 0x2C, 0x66, 0x7C, 0xF8,
-	0xC0, 0x8F, 0x33, 0x13, 0x03, 0xF1, 0xD3, 0xC1,
-	0x0B, 0x89, 0xD9, 0x1B, 0x62, 0xCD, 0x51, 0xB7,
-	0x80, 0xB8, 0xAF, 0x3A, 0x10, 0xC1, 0x8A, 0x5B,
-	0xE8, 0x8A, 0x56, 0xF0, 0x8C, 0xAA, 0xFA, 0x35,
-	0xE9, 0x42, 0xC4, 0xD8, 0x55, 0xC3, 0x38, 0xCC,
-	0x2B, 0x53, 0x5C, 0x69, 0x52, 0xD5, 0xC8, 0x73,
-	0x02, 0x38, 0x7C, 0x73, 0xB6, 0x41, 0xE7, 0xFF,
-	0x05, 0xD8, 0x2B, 0x79, 0x9A, 0xE2, 0x34, 0x60,
-	0x8F, 0xA3, 0x32, 0x1F, 0x09, 0x78, 0x62, 0xBC,
-	0x80, 0xE3, 0x0F, 0xBD, 0x65, 0x20, 0x08, 0x13,
-	0xC1, 0xE2, 0xEE, 0x53, 0x2D, 0x86, 0x7E, 0xA7,
-	0x5A, 0xC5, 0xD3, 0x7D, 0x98, 0xBE, 0x31, 0x48,
-	0x1F, 0xFB, 0xDA, 0xAF, 0xA2, 0xA8, 0x6A, 0x89,
-	0xD6, 0xBF, 0xF2, 0xD3, 0x32, 0x2A, 0x9A, 0xE4,
-	0xCF, 0x17, 0xB7, 0xB8, 0xF4, 0xE1, 0x33, 0x08,
-	0x24, 0x8B, 0xC4, 0x43, 0xA5, 0xE5, 0x24, 0xC2,
+	0xFC,
+	0x28,
+	0xFE,
+	0x84,
+	0x40,
+	0xCB,
+	0x9A,
+	0x87,
+	0x0D,
+	0xBE,
+	0x57,
+	0x3C,
+	0xB6,
+	0x70,
+	0x09,
+	0x88,
+	0x07,
+	0x97,
+	0x2D,
+	0x2B,
+	0xE3,
+	0x38,
+	0x34,
+	0xB6,
+	0x6C,
+	0xED,
+	0xB0,
+	0xF7,
+	0xE5,
+	0x9C,
+	0xF6,
+	0xC2,
+	0x2E,
+	0x84,
+	0x1B,
+	0xE8,
+	0xB4,
+	0x51,
+	0x78,
+	0x43,
+	0x1F,
+	0x28,
+	0x4B,
+	0x7C,
+	0x2D,
+	0x53,
+	0xAF,
+	0xFC,
+	0x47,
+	0x70,
+	0x1B,
+	0x59,
+	0x6F,
+	0x74,
+	0x43,
+	0xC4,
+	0xF3,
+	0x47,
+	0x18,
+	0x53,
+	0x1A,
+	0xA2,
+	0xA1,
+	0x71,
+	0xC7,
+	0x95,
+	0x0E,
+	0x31,
+	0x55,
+	0x21,
+	0xD3,
+	0xB5,
+	0x1E,
+	0xE9,
+	0x0C,
+	0xBA,
+	0xEC,
+	0xB8,
+	0x89,
+	0x19,
+	0x3E,
+	0xB3,
+	0xAF,
+	0x75,
+	0x81,
+	0x9D,
+	0x53,
+	0xB9,
+	0x41,
+	0x57,
+	0xF4,
+	0x6D,
+	0x39,
+	0x25,
+	0x29,
+	0x7C,
+	0x87,
+	0xD9,
+	0xB4,
+	0x98,
+	0x45,
+	0x7D,
+	0xA7,
+	0x26,
+	0x9C,
+	0x65,
+	0x3B,
+	0x85,
+	0x68,
+	0x89,
+	0xD7,
+	0x3B,
+	0xBD,
+	0xFF,
+	0x14,
+	0x67,
+	0xF2,
+	0x2B,
+	0xF0,
+	0x2A,
+	0x41,
+	0x54,
+	0xF0,
+	0xFD,
+	0x2C,
+	0x66,
+	0x7C,
+	0xF8,
+	0xC0,
+	0x8F,
+	0x33,
+	0x13,
+	0x03,
+	0xF1,
+	0xD3,
+	0xC1,
+	0x0B,
+	0x89,
+	0xD9,
+	0x1B,
+	0x62,
+	0xCD,
+	0x51,
+	0xB7,
+	0x80,
+	0xB8,
+	0xAF,
+	0x3A,
+	0x10,
+	0xC1,
+	0x8A,
+	0x5B,
+	0xE8,
+	0x8A,
+	0x56,
+	0xF0,
+	0x8C,
+	0xAA,
+	0xFA,
+	0x35,
+	0xE9,
+	0x42,
+	0xC4,
+	0xD8,
+	0x55,
+	0xC3,
+	0x38,
+	0xCC,
+	0x2B,
+	0x53,
+	0x5C,
+	0x69,
+	0x52,
+	0xD5,
+	0xC8,
+	0x73,
+	0x02,
+	0x38,
+	0x7C,
+	0x73,
+	0xB6,
+	0x41,
+	0xE7,
+	0xFF,
+	0x05,
+	0xD8,
+	0x2B,
+	0x79,
+	0x9A,
+	0xE2,
+	0x34,
+	0x60,
+	0x8F,
+	0xA3,
+	0x32,
+	0x1F,
+	0x09,
+	0x78,
+	0x62,
+	0xBC,
+	0x80,
+	0xE3,
+	0x0F,
+	0xBD,
+	0x65,
+	0x20,
+	0x08,
+	0x13,
+	0xC1,
+	0xE2,
+	0xEE,
+	0x53,
+	0x2D,
+	0x86,
+	0x7E,
+	0xA7,
+	0x5A,
+	0xC5,
+	0xD3,
+	0x7D,
+	0x98,
+	0xBE,
+	0x31,
+	0x48,
+	0x1F,
+	0xFB,
+	0xDA,
+	0xAF,
+	0xA2,
+	0xA8,
+	0x6A,
+	0x89,
+	0xD6,
+	0xBF,
+	0xF2,
+	0xD3,
+	0x32,
+	0x2A,
+	0x9A,
+	0xE4,
+	0xCF,
+	0x17,
+	0xB7,
+	0xB8,
+	0xF4,
+	0xE1,
+	0x33,
+	0x08,
+	0x24,
+	0x8B,
+	0xC4,
+	0x43,
+	0xA5,
+	0xE5,
+	0x24,
+	0xC2,
 };
 
 /* Device capabilities feature report. */
 static const uint8_t device_caps_response[] = {
 	REPORT_ID_DEVICE_CAPS,
 
-	MAX_FINGERS,            /* Contact Count Maximum */
-	0x00,                   /* Pad Type: Depressible click-pad */
+	MAX_FINGERS, /* Contact Count Maximum */
+	0x00, /* Pad Type: Depressible click-pad */
 };
 
-const struct usb_hid_descriptor USB_CUSTOM_DESC_VAR(USB_IFACE_HID_TOUCHPAD,
-						hid, hid_desc_tp) = {
+const struct usb_hid_descriptor USB_CUSTOM_DESC_VAR(USB_IFACE_HID_TOUCHPAD, hid,
+						    hid_desc_tp) = {
 	.bLength = 9,
 	.bDescriptorType = USB_HID_DT_HID,
 	.bcdHID = 0x0100,
 	.bCountryCode = 0x00, /* Hardware target country */
 	.bNumDescriptors = 1,
-	.desc = {{
-		.bDescriptorType = USB_HID_DT_REPORT,
-		.wDescriptorLength = sizeof(report_desc)
-	}}
+	.desc = { { .bDescriptorType = USB_HID_DT_REPORT,
+		    .wDescriptorLength = sizeof(report_desc) } }
 };
 
 static usb_uint hid_ep_buf[DIV_ROUND_UP(HID_TOUCHPAD_REPORT_SIZE, 2)] __usb_ram;
@@ -258,8 +485,8 @@ static usb_uint hid_ep_buf[DIV_ROUND_UP(HID_TOUCHPAD_REPORT_SIZE, 2)] __usb_ram;
  */
 static void write_touchpad_report(struct usb_hid_touchpad_report *report)
 {
-	memcpy_to_usbram((void *) usb_sram_addr(hid_ep_buf),
-			 report, sizeof(*report));
+	memcpy_to_usbram((void *)usb_sram_addr(hid_ep_buf), report,
+			 sizeof(*report));
 	/* enable TX */
 	STM32_TOGGLE_EP(USB_EP_HID_TOUCHPAD, EP_TX_MASK, EP_TX_VALID, 0);
 
@@ -289,8 +516,7 @@ static void hid_touchpad_process_queue(void)
 	now = __hw_clock_source_read() / USB_HID_TOUCHPAD_TIMESTAMP_UNIT;
 
 	if (usb_is_suspended() ||
-			(STM32_USB_EP(USB_EP_HID_TOUCHPAD) & EP_TX_MASK)
-				== EP_TX_VALID) {
+	    (STM32_USB_EP(USB_EP_HID_TOUCHPAD) & EP_TX_MASK) == EP_TX_VALID) {
 		usb_wake();
 
 		/* Let's trim old events from the queue, if any. */
@@ -307,8 +533,8 @@ static void hid_touchpad_process_queue(void)
 
 		queue_peek_units(&report_queue, &report, 0, 1);
 
-		delta = (int)((uint16_t)(now - report.timestamp))
-				* USB_HID_TOUCHPAD_TIMESTAMP_UNIT;
+		delta = (int)((uint16_t)(now - report.timestamp)) *
+			USB_HID_TOUCHPAD_TIMESTAMP_UNIT;
 
 		if (touchpad_debug)
 			CPRINTS("evt t=%d d=%d", report.timestamp, delta);
@@ -345,8 +571,8 @@ void set_touchpad_report(struct usb_hid_touchpad_report *report)
 
 	/* USB/EP ready and nothing in queue, just write the report. */
 	if (!usb_is_suspended() &&
-	    (STM32_USB_EP(USB_EP_HID_TOUCHPAD) & EP_TX_MASK) != EP_TX_VALID
-	    && queue_count(&report_queue) == 0) {
+	    (STM32_USB_EP(USB_EP_HID_TOUCHPAD) & EP_TX_MASK) != EP_TX_VALID &&
+	    queue_count(&report_queue) == 0) {
 		write_touchpad_report(report);
 		mutex_unlock(&report_queue_mutex);
 		return;
@@ -385,7 +611,7 @@ static void hid_touchpad_event(enum usb_ep_event evt)
 		hid_reset(USB_EP_HID_TOUCHPAD, hid_ep_buf,
 			  HID_TOUCHPAD_REPORT_SIZE, NULL, 0);
 	else if (evt == USB_EVENT_DEVICE_RESUME &&
-			queue_count(&report_queue) > 0)
+		 queue_count(&report_queue) > 0)
 		hook_call_deferred(&hid_touchpad_process_queue_data, 0);
 }
 
@@ -393,8 +619,7 @@ USB_DECLARE_EP(USB_EP_HID_TOUCHPAD, hid_touchpad_tx, hid_touchpad_tx,
 	       hid_touchpad_event);
 
 static int get_report(uint8_t report_id, uint8_t report_type,
-		      const uint8_t **buffer_ptr,
-		      int *buffer_size)
+		      const uint8_t **buffer_ptr, int *buffer_size)
 {
 	switch (report_id) {
 	case REPORT_ID_DEVICE_CAPS:
diff --git a/chip/stm32/usb_hw.h b/chip/stm32/usb_hw.h
index fc186ff7de..511cd9c75a 100644
--- a/chip/stm32/usb_hw.h
+++ b/chip/stm32/usb_hw.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,12 +19,11 @@ enum usb_ep_event {
 #include "usb_dwc_hw.h"
 #else
 
-
 /*
  * The STM32 has dedicated USB RAM visible on the APB1 bus (so all reads &
  * writes are 16-bits wide). The endpoint tables and the data buffers live in
  * this RAM.
-*/
+ */
 
 /* Primitive to access the words in USB RAM */
 typedef CONFIG_USB_RAM_ACCESS_TYPE usb_uint;
@@ -87,8 +86,8 @@ enum usb_desc_patch_type {
  * The patches need to be setup before _before_ usb_init is executed (or, at
  * least, before the first call to memcpy_to_usbram_ep0_patch).
  */
-void set_descriptor_patch(enum usb_desc_patch_type type,
-			  const void *address, uint16_t data);
+void set_descriptor_patch(enum usb_desc_patch_type type, const void *address,
+			  uint16_t data);
 
 /* Copy to USB ram, applying patches to src as required. */
 void *memcpy_to_usbram_ep0_patch(const void *src, size_t n);
@@ -106,44 +105,42 @@ void *memcpy_to_usbram_ep0_patch(const void *src, size_t n);
 #define _EP_RX_HANDLER_TYPECHECK(num) _EP_HANDLER2(num, _rx_typecheck)
 #define _EP_EVENT_HANDLER_TYPECHECK(num) _EP_HANDLER2(num, _evt_typecheck)
 
-#define USB_DECLARE_EP(num, tx_handler, rx_handler, evt_handler)  \
-	void _EP_TX_HANDLER(num)(void)				  \
-		__attribute__ ((alias(STRINGIFY(tx_handler))));	  \
-	void _EP_RX_HANDLER(num)(void)                            \
-		__attribute__ ((alias(STRINGIFY(rx_handler))));	  \
-	void _EP_EVENT_HANDLER(num)(enum usb_ep_event evt)        \
-		__attribute__ ((alias(STRINGIFY(evt_handler))));  \
-	static __unused void					  \
-	(*_EP_TX_HANDLER_TYPECHECK(num))(void) = tx_handler;	  \
-	static __unused void					  \
-	(*_EP_RX_HANDLER_TYPECHECK(num))(void) = rx_handler;	  \
-	static __unused void					  \
-	(*_EP_EVENT_HANDLER_TYPECHECK(num))(enum usb_ep_event evt)\
-			= evt_handler
+#define USB_DECLARE_EP(num, tx_handler, rx_handler, evt_handler)      \
+	void _EP_TX_HANDLER(num)(void)                                \
+		__attribute__((alias(STRINGIFY(tx_handler))));        \
+	void _EP_RX_HANDLER(num)(void)                                \
+		__attribute__((alias(STRINGIFY(rx_handler))));        \
+	void _EP_EVENT_HANDLER(num)(enum usb_ep_event evt)            \
+		__attribute__((alias(STRINGIFY(evt_handler))));       \
+	static __unused void (*_EP_TX_HANDLER_TYPECHECK(num))(void) = \
+		tx_handler;                                           \
+	static __unused void (*_EP_RX_HANDLER_TYPECHECK(num))(void) = \
+		rx_handler;                                           \
+	static __unused void (*_EP_EVENT_HANDLER_TYPECHECK(num))(     \
+		enum usb_ep_event evt) = evt_handler
 
 /* arrays with all endpoint callbacks */
-extern void (*usb_ep_tx[]) (void);
-extern void (*usb_ep_rx[]) (void);
-extern void (*usb_ep_event[]) (enum usb_ep_event evt);
+extern void (*usb_ep_tx[])(void);
+extern void (*usb_ep_rx[])(void);
+extern void (*usb_ep_event[])(enum usb_ep_event evt);
 /* array with interface-specific control request callbacks */
-extern int (*usb_iface_request[]) (usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx);
+extern int (*usb_iface_request[])(usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx);
 
 /*
  * Interface handler returns -1 on error, 0 if it wrote the last chunk of data,
  * or 1 if more data needs to be transferred on the next control request.
  */
 #define _IFACE_HANDLER(num) CONCAT3(iface_, num, _request)
-#define USB_DECLARE_IFACE(num, handler)					\
-	int _IFACE_HANDLER(num)(usb_uint *ep0_buf_rx,			\
-			       usb_uint *epo_buf_tx)			\
-	__attribute__ ((alias(STRINGIFY(handler))));
+#define USB_DECLARE_IFACE(num, handler)                                       \
+	int _IFACE_HANDLER(num)(usb_uint * ep0_buf_rx, usb_uint * epo_buf_tx) \
+		__attribute__((alias(STRINGIFY(handler))));
 
 #endif
 
 /*
  * In and out buffer sizes for host command over USB.
  */
-#define USBHC_MAX_REQUEST_SIZE	0x200
+#define USBHC_MAX_REQUEST_SIZE 0x200
 #define USBHC_MAX_RESPONSE_SIZE 0x100
 
-#endif	/* __CROS_EC_USB_HW_H */
+#endif /* __CROS_EC_USB_HW_H */
diff --git a/chip/stm32/usb_isochronous.c b/chip/stm32/usb_isochronous.c
index 792507aa75..ad20b6d1ca 100644
--- a/chip/stm32/usb_isochronous.c
+++ b/chip/stm32/usb_isochronous.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,10 +13,9 @@
 #include "usb_hw.h"
 #include "usb_isochronous.h"
 
-
 /* Console output macro */
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USB, format, ##args)
 
 /*
  * Currently, we only support TX direction for USB isochronous transfer.
@@ -65,8 +64,7 @@ static usb_uint *get_app_addr(struct usb_isochronous_config const *config,
  * Sets number of bytes written to application buffer.
  */
 static void set_app_count(struct usb_isochronous_config const *config,
-			  int dtog_value,
-			  usb_uint count)
+			  int dtog_value, usb_uint count)
 {
 	if (dtog_value)
 		btable_ep[config->endpoint].tx_count = count;
@@ -74,13 +72,9 @@ static void set_app_count(struct usb_isochronous_config const *config,
 		btable_ep[config->endpoint].rx_count = count;
 }
 
-int usb_isochronous_write_buffer(
-		struct usb_isochronous_config const *config,
-		const uint8_t *src,
-		size_t n,
-		size_t dst_offset,
-		int *buffer_id,
-		int commit)
+int usb_isochronous_write_buffer(struct usb_isochronous_config const *config,
+				 const uint8_t *src, size_t n,
+				 size_t dst_offset, int *buffer_id, int commit)
 {
 	int dtog_value = get_tx_dtog(config);
 	usb_uint *buffer = get_app_addr(config, dtog_value);
@@ -142,15 +136,13 @@ void usb_isochronous_tx(struct usb_isochronous_config const *config)
 }
 
 int usb_isochronous_iface_handler(struct usb_isochronous_config const *config,
-				  usb_uint *ep0_buf_rx,
-				  usb_uint *ep0_buf_tx)
+				  usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx)
 {
 	int ret = -1;
 
-	if (ep0_buf_rx[0] == (USB_DIR_OUT |
-			      USB_TYPE_STANDARD |
-			      USB_RECIP_INTERFACE |
-			      USB_REQ_SET_INTERFACE << 8)) {
+	if (ep0_buf_rx[0] ==
+	    (USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE |
+	     USB_REQ_SET_INTERFACE << 8)) {
 		ret = config->set_interface(ep0_buf_rx[1], ep0_buf_rx[2]);
 
 		if (ret == 0) {
diff --git a/chip/stm32/usb_isochronous.h b/chip/stm32/usb_isochronous.h
index efa4d94ab4..a96b6db876 100644
--- a/chip/stm32/usb_isochronous.h
+++ b/chip/stm32/usb_isochronous.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -75,13 +75,9 @@ struct usb_isochronous_config;
  *
  * @return  -EC_ERROR_CODE on failure, or number of bytes written on success.
  */
-int usb_isochronous_write_buffer(
-		struct usb_isochronous_config const *config,
-		const uint8_t *src,
-		size_t n,
-		size_t dst_offset,
-		int *buffer_id,
-		int commit);
+int usb_isochronous_write_buffer(struct usb_isochronous_config const *config,
+				 const uint8_t *src, size_t n,
+				 size_t dst_offset, int *buffer_id, int commit);
 
 struct usb_isochronous_config {
 	int endpoint;
@@ -110,21 +106,15 @@ struct usb_isochronous_config {
 };
 
 /* Define an USB isochronous interface */
-#define USB_ISOCHRONOUS_CONFIG_FULL(NAME,				\
-				    INTERFACE,				\
-				    INTERFACE_CLASS,			\
-				    INTERFACE_SUBCLASS,			\
-				    INTERFACE_PROTOCOL,			\
-				    INTERFACE_NAME,			\
-				    ENDPOINT,				\
-				    TX_SIZE,				\
-				    TX_CALLBACK,			\
-				    SET_INTERFACE,			\
-				    NUM_EXTRA_ENDPOINTS)		\
-	BUILD_ASSERT(TX_SIZE > 0);					\
-	BUILD_ASSERT((TX_SIZE <   64 && (TX_SIZE & 0x01) == 0) ||	\
-		     (TX_SIZE < 1024 && (TX_SIZE & 0x1f) == 0));	\
-	/* Declare buffer */						\
+#define USB_ISOCHRONOUS_CONFIG_FULL(NAME, INTERFACE, INTERFACE_CLASS,          \
+				    INTERFACE_SUBCLASS, INTERFACE_PROTOCOL,    \
+				    INTERFACE_NAME, ENDPOINT, TX_SIZE,         \
+				    TX_CALLBACK, SET_INTERFACE,                \
+				    NUM_EXTRA_ENDPOINTS)                       \
+	BUILD_ASSERT(TX_SIZE > 0);                                             \
+	BUILD_ASSERT((TX_SIZE < 64 && (TX_SIZE & 0x01) == 0) ||                \
+		     (TX_SIZE < 1024 && (TX_SIZE & 0x1f) == 0));               \
+	/* Declare buffer */                                                   \
 	static usb_uint CONCAT2(NAME, _ep_tx_buffer_0)[TX_SIZE / 2] __usb_ram; \
 	static usb_uint CONCAT2(NAME, _ep_tx_buffer_1)[TX_SIZE / 2] __usb_ram; \
 	struct usb_isochronous_config const NAME = {			\
@@ -136,62 +126,57 @@ struct usb_isochronous_config {
 			CONCAT2(NAME, _ep_tx_buffer_0),			\
 			CONCAT2(NAME, _ep_tx_buffer_1),			\
 		},							\
-	};								\
-	const struct usb_interface_descriptor				\
-	USB_IFACE_DESC(INTERFACE) = {					\
-		.bLength            = USB_DT_INTERFACE_SIZE,		\
-		.bDescriptorType    = USB_DT_INTERFACE,			\
-		.bInterfaceNumber   = INTERFACE,			\
-		.bAlternateSetting  = 0,				\
-		.bNumEndpoints      = 0,				\
-		.bInterfaceClass    = INTERFACE_CLASS,			\
-		.bInterfaceSubClass = INTERFACE_SUBCLASS,		\
-		.bInterfaceProtocol = INTERFACE_PROTOCOL,		\
-		.iInterface         = INTERFACE_NAME,			\
-	};								\
-	const struct usb_interface_descriptor				\
-	USB_CONF_DESC(CONCAT3(iface, INTERFACE, _1iface)) = {		\
-		.bLength            = USB_DT_INTERFACE_SIZE,		\
-		.bDescriptorType    = USB_DT_INTERFACE,			\
-		.bInterfaceNumber   = INTERFACE,			\
-		.bAlternateSetting  = 1,				\
-		.bNumEndpoints      = 1 + NUM_EXTRA_ENDPOINTS,		\
-		.bInterfaceClass    = INTERFACE_CLASS,			\
-		.bInterfaceSubClass = INTERFACE_SUBCLASS,		\
-		.bInterfaceProtocol = INTERFACE_PROTOCOL,		\
-		.iInterface         = INTERFACE_NAME,			\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 0) = {					\
-		.bLength          = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = 0x80 | ENDPOINT,			\
-		.bmAttributes     = 0x01 /* Isochronous IN */,		\
-		.wMaxPacketSize   = TX_SIZE,				\
-		.bInterval        = 1,					\
-	};								\
-	static void CONCAT2(NAME, _ep_tx)(void)				\
-	{								\
-		usb_isochronous_tx(&NAME);				\
-	}								\
-	static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt)	\
-	{								\
-		usb_isochronous_event(&NAME, evt);			\
-	}								\
-	static int CONCAT2(NAME, _handler)(usb_uint *rx, usb_uint *tx)	\
-	{								\
-		return usb_isochronous_iface_handler(&NAME, rx, tx);	\
-	}								\
-	USB_DECLARE_IFACE(INTERFACE, CONCAT2(NAME, _handler));		\
-	USB_DECLARE_EP(ENDPOINT,					\
-		       CONCAT2(NAME, _ep_tx),				\
-		       CONCAT2(NAME, _ep_tx),				\
-		       CONCAT2(NAME, _ep_event));			\
+	};                       \
+	const struct usb_interface_descriptor USB_IFACE_DESC(INTERFACE) = {    \
+		.bLength = USB_DT_INTERFACE_SIZE,                              \
+		.bDescriptorType = USB_DT_INTERFACE,                           \
+		.bInterfaceNumber = INTERFACE,                                 \
+		.bAlternateSetting = 0,                                        \
+		.bNumEndpoints = 0,                                            \
+		.bInterfaceClass = INTERFACE_CLASS,                            \
+		.bInterfaceSubClass = INTERFACE_SUBCLASS,                      \
+		.bInterfaceProtocol = INTERFACE_PROTOCOL,                      \
+		.iInterface = INTERFACE_NAME,                                  \
+	};                                                                     \
+	const struct usb_interface_descriptor USB_CONF_DESC(                   \
+		CONCAT3(iface, INTERFACE, _1iface)) = {                        \
+		.bLength = USB_DT_INTERFACE_SIZE,                              \
+		.bDescriptorType = USB_DT_INTERFACE,                           \
+		.bInterfaceNumber = INTERFACE,                                 \
+		.bAlternateSetting = 1,                                        \
+		.bNumEndpoints = 1 + NUM_EXTRA_ENDPOINTS,                      \
+		.bInterfaceClass = INTERFACE_CLASS,                            \
+		.bInterfaceSubClass = INTERFACE_SUBCLASS,                      \
+		.bInterfaceProtocol = INTERFACE_PROTOCOL,                      \
+		.iInterface = INTERFACE_NAME,                                  \
+	};                                                                     \
+	const struct usb_endpoint_descriptor USB_EP_DESC(INTERFACE, 0) = {     \
+		.bLength = USB_DT_ENDPOINT_SIZE,                               \
+		.bDescriptorType = USB_DT_ENDPOINT,                            \
+		.bEndpointAddress = 0x80 | ENDPOINT,                           \
+		.bmAttributes = 0x01 /* Isochronous IN */,                     \
+		.wMaxPacketSize = TX_SIZE,                                     \
+		.bInterval = 1,                                                \
+	};                                                                     \
+	static void CONCAT2(NAME, _ep_tx)(void)                                \
+	{                                                                      \
+		usb_isochronous_tx(&NAME);                                     \
+	}                                                                      \
+	static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt)            \
+	{                                                                      \
+		usb_isochronous_event(&NAME, evt);                             \
+	}                                                                      \
+	static int CONCAT2(NAME, _handler)(usb_uint * rx, usb_uint * tx)       \
+	{                                                                      \
+		return usb_isochronous_iface_handler(&NAME, rx, tx);           \
+	}                                                                      \
+	USB_DECLARE_IFACE(INTERFACE, CONCAT2(NAME, _handler));                 \
+	USB_DECLARE_EP(ENDPOINT, CONCAT2(NAME, _ep_tx), CONCAT2(NAME, _ep_tx), \
+		       CONCAT2(NAME, _ep_event));
 
 void usb_isochronous_tx(struct usb_isochronous_config const *config);
 void usb_isochronous_event(struct usb_isochronous_config const *config,
 			   enum usb_ep_event event);
 int usb_isochronous_iface_handler(struct usb_isochronous_config const *config,
-				  usb_uint *ep0_buf_rx,
-				  usb_uint *ep0_buf_tx);
+				  usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx);
 #endif /* __CROS_EC_USB_ISOCHRONOUS_H */
diff --git a/chip/stm32/usb_pd_phy.c b/chip/stm32/usb_pd_phy.c
index 21484b1a88..9536301863 100644
--- a/chip/stm32/usb_pd_phy.c
+++ b/chip/stm32/usb_pd_phy.c
@@ -1,9 +1,10 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "adc.h"
+#include "builtin/assert.h"
 #include "clock.h"
 #include "common.h"
 #include "console.h"
@@ -21,8 +22,8 @@
 #include "usb_pd_config.h"
 
 #ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 #else
 #define CPRINTF(format, args...)
 #define CPRINTS(format, args...)
@@ -38,7 +39,7 @@
  */
 #define PD_BIT_LEN 429
 
-#define PD_MAX_RAW_SIZE (PD_BIT_LEN*2)
+#define PD_MAX_RAW_SIZE (PD_BIT_LEN * 2)
 
 /* maximum number of consecutive similar bits with Biphase Mark Coding */
 #define MAX_BITS 2
@@ -46,12 +47,12 @@
 /* alternating bit sequence used for packet preamble : 00 10 11 01 00 ..  */
 #define PD_PREAMBLE 0xB4B4B4B4 /* starts with 0, ends with 1 */
 
-#define TX_CLOCK_DIV ((clock_get_freq() / (2*PD_DATARATE)))
+#define TX_CLOCK_DIV ((clock_get_freq() / (2 * PD_DATARATE)))
 
 /* threshold for 1 300-khz period */
 #define PERIOD 4
-#define NB_PERIOD(from, to) ((((to) - (from) + (PERIOD/2)) & 0xFF) / PERIOD)
-#define PERIOD_THRESHOLD ((PERIOD + 2*PERIOD) / 2)
+#define NB_PERIOD(from, to) ((((to) - (from) + (PERIOD / 2)) & 0xFF) / PERIOD)
+#define PERIOD_THRESHOLD ((PERIOD + 2 * PERIOD) / 2)
 
 static struct pd_physical {
 	/* samples for the PD messages */
@@ -73,8 +74,8 @@ static struct pd_physical {
 } pd_phy[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 /* keep track of RX edge timing in order to trigger receive */
-static timestamp_t
-	rx_edge_ts[CONFIG_USB_PD_PORT_MAX_COUNT][PD_RX_TRANSITION_COUNT];
+static timestamp_t rx_edge_ts[CONFIG_USB_PD_PORT_MAX_COUNT]
+			     [PD_RX_TRANSITION_COUNT];
 static int rx_edge_ts_idx[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 /* keep track of transmit polarity for DMA interrupt */
@@ -95,8 +96,8 @@ static int wait_bits(int port, int nb)
 
 	avail = dma_bytes_done(rx, PD_MAX_RAW_SIZE);
 	if (avail < nb) { /* no received yet ... */
-		while ((dma_bytes_done(rx, PD_MAX_RAW_SIZE) < nb)
-			&& !(pd_phy[port].tim_rx->sr & 4))
+		while ((dma_bytes_done(rx, PD_MAX_RAW_SIZE) < nb) &&
+		       !(pd_phy[port].tim_rx->sr & 4))
 			; /* optimized for latency, not CPU usage ... */
 		if (dma_bytes_done(rx, PD_MAX_RAW_SIZE) < nb) {
 			CPRINTS("PD TMOUT RX %d/%d",
@@ -117,8 +118,8 @@ int pd_dequeue_bits(int port, int off, int len, uint32_t *val)
 		w = wait_bits(port, off + 2);
 		if (w < 0)
 			goto stream_err;
-		cnt = samples[off] - samples[off-1];
-		if (!cnt || (cnt > 3*PERIOD))
+		cnt = samples[off] - samples[off - 1];
+		if (!cnt || (cnt > 3 * PERIOD))
 			goto stream_err;
 		off++;
 		if (cnt <= PERIOD_THRESHOLD) {
@@ -127,20 +128,22 @@ int pd_dequeue_bits(int port, int off, int len, uint32_t *val)
 			if (w < 0)
 				goto stream_err;
 			*/
-			cnt = samples[off] - samples[off-1];
-			if (cnt >  PERIOD_THRESHOLD)
+			cnt = samples[off] - samples[off - 1];
+			if (cnt > PERIOD_THRESHOLD)
 				goto stream_err;
 			off++;
 		}
 
 		/* enqueue the bit of the last period */
-		pd_phy[port].d_last = (pd_phy[port].d_last >> 1)
-		       | (cnt <= PERIOD_THRESHOLD ? 0x80000000 : 0);
+		pd_phy[port].d_last =
+			(pd_phy[port].d_last >> 1) |
+			(cnt <= PERIOD_THRESHOLD ? 0x80000000 : 0);
 		pd_phy[port].d_lastlen++;
 	}
 	if (off < PD_MAX_RAW_SIZE) {
-		*val = (pd_phy[port].d_last << (pd_phy[port].d_lastlen - len))
-				>> (32 - len);
+		*val = (pd_phy[port].d_last
+			<< (pd_phy[port].d_lastlen - len)) >>
+		       (32 - len);
 		pd_phy[port].d_lastlen -= len;
 		return off;
 	} else {
@@ -168,7 +171,7 @@ int pd_find_preamble(int port)
 		/* wait if the bit is not received yet ... */
 		if (PD_MAX_RAW_SIZE - rx->cndtr < bit + 1) {
 			while ((PD_MAX_RAW_SIZE - rx->cndtr < bit + 1) &&
-				!(pd_phy[port].tim_rx->sr & 4))
+			       !(pd_phy[port].tim_rx->sr & 4))
 				;
 			if (pd_phy[port].tim_rx->sr & 4) {
 				CPRINTS("PD TMOUT RX %d/%d",
@@ -176,7 +179,7 @@ int pd_find_preamble(int port)
 				return -1;
 			}
 		}
-		cnt = vals[bit] - vals[bit-1];
+		cnt = vals[bit] - vals[bit - 1];
 		all = (all >> 1) | (cnt <= PERIOD_THRESHOLD ? BIT(31) : 0);
 		if (all == 0x36db6db6)
 			return bit - 1; /* should be SYNC-1 */
@@ -198,7 +201,7 @@ int pd_write_preamble(int port)
 	msg[2] = PD_PREAMBLE;
 	msg[3] = PD_PREAMBLE;
 	pd_phy[port].b_toggle = 0x3FF; /* preamble ends with 1 */
-	return 2*64;
+	return 2 * 64;
 }
 
 int pd_write_sym(int port, int bit_off, uint32_t val10)
@@ -214,10 +217,10 @@ int pd_write_sym(int port, int bit_off, uint32_t val10)
 		msg[word_idx] |= val << bit_idx;
 	} else {
 		msg[word_idx] |= val << bit_idx;
-		msg[word_idx+1] = val >> (32 - bit_idx);
+		msg[word_idx + 1] = val >> (32 - bit_idx);
 		/* side effect: clear the new word when starting it */
 	}
-	return bit_off + 5*2;
+	return bit_off + 5 * 2;
 }
 
 int pd_write_last_edge(int port, int bit_off)
@@ -239,7 +242,7 @@ int pd_write_last_edge(int port, int bit_off)
 		}
 	}
 	/* ensure that the trailer is 0 */
-	msg[word_idx+1] = 0;
+	msg[word_idx + 1] = 0;
 
 	return bit_off + 3;
 }
@@ -252,15 +255,15 @@ void pd_dump_packet(int port, const char *msg)
 
 	CPRINTF("ERR %s:\n000:- ", msg);
 	/* Packet debug output */
-	for (bit = 1; bit <  PD_MAX_RAW_SIZE; bit++) {
-		int cnt = NB_PERIOD(vals[bit-1], vals[bit]);
+	for (bit = 1; bit < PD_MAX_RAW_SIZE; bit++) {
+		int cnt = NB_PERIOD(vals[bit - 1], vals[bit]);
 		if ((bit & 31) == 0)
 			CPRINTF("\n%03d:", bit);
 		CPRINTF("%1d ", cnt);
 	}
 	CPRINTF("><\n");
 	cflush();
-	for (bit = 0; bit <  PD_MAX_RAW_SIZE; bit++) {
+	for (bit = 0; bit < PD_MAX_RAW_SIZE; bit++) {
 		if ((bit & 31) == 0)
 			CPRINTF("\n%03d:", bit);
 		CPRINTF("%02x ", vals[bit]);
@@ -280,9 +283,9 @@ void pd_tx_spi_init(int port)
 	spi->cr2 = STM32_SPI_CR2_TXDMAEN | STM32_SPI_CR2_DATASIZE(8);
 
 	/* Enable the slave SPI: LSB first, force NSS, TX only, CPHA */
-	spi->cr1 = STM32_SPI_CR1_SPE | STM32_SPI_CR1_LSBFIRST
-		 | STM32_SPI_CR1_SSM | STM32_SPI_CR1_BIDIMODE
-		 | STM32_SPI_CR1_BIDIOE | STM32_SPI_CR1_CPHA;
+	spi->cr1 = STM32_SPI_CR1_SPE | STM32_SPI_CR1_LSBFIRST |
+		   STM32_SPI_CR1_SSM | STM32_SPI_CR1_BIDIMODE |
+		   STM32_SPI_CR1_BIDIOE | STM32_SPI_CR1_CPHA;
 }
 
 static void tx_dma_done(void *data)
@@ -330,9 +333,8 @@ int pd_start_tx(int port, int polarity, int bit_len)
 	pd_phy[port].tim_tx->cnt = TX_CLOCK_DIV - 1;
 
 	/* update DMA configuration */
-	dma_prepare_tx(&(pd_phy[port].dma_tx_option),
-			DIV_ROUND_UP(bit_len, 8),
-			pd_phy[port].raw_samples);
+	dma_prepare_tx(&(pd_phy[port].dma_tx_option), DIV_ROUND_UP(bit_len, 8),
+		       pd_phy[port].raw_samples);
 	/* Flush data in write buffer so that DMA can get the latest data */
 	asm volatile("dmb;");
 
@@ -343,8 +345,7 @@ int pd_start_tx(int port, int polarity, int bit_len)
 	if (!(pd_phy[port].dma_tx_option.flags & STM32_DMA_CCR_CIRC)) {
 		/* Only enable interrupt if not in circular mode */
 		dma_enable_tc_interrupt_callback(DMAC_SPI_TX(port),
-						 &tx_dma_done,
-						 (void *)port);
+						 &tx_dma_done, (void *)port);
 	}
 #endif
 	dma_go(tx);
@@ -401,9 +402,10 @@ void pd_rx_start(int port)
 {
 	/* start sampling the edges on the CC line using the RX timer */
 	dma_start_rx(&(pd_phy[port].dma_tim_option), PD_MAX_RAW_SIZE,
-			pd_phy[port].raw_samples);
+		     pd_phy[port].raw_samples);
 	/* enable TIM2 DMA requests */
-	pd_phy[port].tim_rx->egr = 0x0001; /* reset counter / reload PSC */;
+	pd_phy[port].tim_rx->egr = 0x0001; /* reset counter / reload PSC */
+	;
 	pd_phy[port].tim_rx->sr = 0; /* clear overflows */
 	pd_phy[port].tim_rx->cr1 |= 1;
 }
@@ -441,8 +443,8 @@ void pd_rx_disable_monitoring(int port)
 uint64_t get_time_since_last_edge(int port)
 {
 	int prev_idx = (rx_edge_ts_idx[port] == 0) ?
-			PD_RX_TRANSITION_COUNT - 1 :
-			rx_edge_ts_idx[port] - 1;
+			       PD_RX_TRANSITION_COUNT - 1 :
+			       rx_edge_ts_idx[port] - 1;
 	return get_time().val - rx_edge_ts[port][prev_idx].val;
 }
 
@@ -467,11 +469,12 @@ void pd_rx_handler(void)
 		if (pending & EXTI_COMP_MASK(i)) {
 			rx_edge_ts[i][rx_edge_ts_idx[i]].val = get_time().val;
 			next_idx = (rx_edge_ts_idx[i] ==
-					PD_RX_TRANSITION_COUNT - 1) ?
-						0 : rx_edge_ts_idx[i] + 1;
+				    PD_RX_TRANSITION_COUNT - 1) ?
+					   0 :
+					   rx_edge_ts_idx[i] + 1;
 
-#if defined(CONFIG_LOW_POWER_IDLE) &&                        \
-defined(CONFIG_USB_PD_LOW_POWER_IDLE_WHEN_CONNECTED)
+#if defined(CONFIG_LOW_POWER_IDLE) && \
+	defined(CONFIG_USB_PD_LOW_POWER_IDLE_WHEN_CONNECTED)
 			/*
 			 * Do not deep sleep while waiting for more edges. For
 			 * most boards, sleep is already disabled due to being
@@ -487,8 +490,8 @@ defined(CONFIG_USB_PD_LOW_POWER_IDLE_WHEN_CONNECTED)
 			 * time, then trigger RX start.
 			 */
 			if ((rx_edge_ts[i][rx_edge_ts_idx[i]].val -
-			     rx_edge_ts[i][next_idx].val)
-			     < PD_RX_TRANSITION_WINDOW) {
+			     rx_edge_ts[i][next_idx].val) <
+			    PD_RX_TRANSITION_WINDOW) {
 				/* start sampling */
 				pd_rx_start(i);
 				/*
@@ -535,7 +538,7 @@ void pd_hw_init_rx(int port)
 	phy->dma_tim_option.channel = DMAC_TIM_RX(port);
 	phy->dma_tim_option.periph = (void *)(TIM_RX_CCR_REG(port));
 	phy->dma_tim_option.flags = STM32_DMA_CCR_MSIZE_8_BIT |
-				     STM32_DMA_CCR_PSIZE_16_BIT;
+				    STM32_DMA_CCR_PSIZE_16_BIT;
 
 	/* --- set counter for RX timing : 2.4Mhz rate, free-running --- */
 	__hw_timer_enable_clock(TIM_CLOCK_PD_RX(port), 1);
@@ -561,7 +564,8 @@ void pd_hw_init_rx(int port)
 
 	phy->tim_rx->ccer = 0xB << ((TIM_RX_CCR_IDX(port) - 1) * 4);
 	/* configure DMA request on CCRx update */
-	phy->tim_rx->dier |= 1 << (8 + TIM_RX_CCR_IDX(port)); /* CCxDE */;
+	phy->tim_rx->dier |= 1 << (8 + TIM_RX_CCR_IDX(port)); /* CCxDE */
+	;
 	/* set prescaler to /26 (F=1.2Mhz, T=0.8us) */
 	phy->tim_rx->psc = (clock_get_freq() / 2400000) - 1;
 	/* Reload the pre-scaler and reset the counter (clear CCRx) */
@@ -590,18 +594,15 @@ void pd_hw_init_rx(int port)
 	clock_wait_bus_cycles(BUS_APB, 1);
 	/* currently in hi-speed mode : TODO revisit later, INM = PA0(INM6) */
 	STM32_COMP_CSR = STM32_COMP_CMP1MODE_LSPEED |
-			 STM32_COMP_CMP1INSEL_INM6 |
-			 CMP1OUTSEL |
-			 STM32_COMP_CMP1HYST_HI |
-			 STM32_COMP_CMP2MODE_LSPEED |
-			 STM32_COMP_CMP2INSEL_INM6 |
-			 CMP2OUTSEL |
+			 STM32_COMP_CMP1INSEL_INM6 | CMP1OUTSEL |
+			 STM32_COMP_CMP1HYST_HI | STM32_COMP_CMP2MODE_LSPEED |
+			 STM32_COMP_CMP2INSEL_INM6 | CMP2OUTSEL |
 			 STM32_COMP_CMP2HYST_HI;
 #elif defined(CHIP_FAMILY_STM32L)
 	STM32_RCC_APB1ENR |= BIT(31); /* turn on COMP */
 
-	STM32_COMP_CSR = STM32_COMP_OUTSEL_TIM2_IC4 | STM32_COMP_INSEL_DAC_OUT1
-			| STM32_COMP_SPEED_FAST;
+	STM32_COMP_CSR = STM32_COMP_OUTSEL_TIM2_IC4 |
+			 STM32_COMP_INSEL_DAC_OUT1 | STM32_COMP_SPEED_FAST;
 	/* route PB4 to COMP input2 through GR6_1 bit 4 (or PB5->GR6_2 bit 5) */
 	STM32_RI_ASCR2 |= BIT(4);
 #else
@@ -638,9 +639,9 @@ void pd_hw_init(int port, enum pd_power_role role)
 	phy->dma_tx_option.channel = DMAC_SPI_TX(port);
 	phy->dma_tx_option.periph = (void *)&SPI_REGS(port)->dr;
 	phy->dma_tx_option.flags = STM32_DMA_CCR_MSIZE_8_BIT |
-				    STM32_DMA_CCR_PSIZE_8_BIT;
+				   STM32_DMA_CCR_PSIZE_8_BIT;
 	dma_prepare_tx(&(phy->dma_tx_option), PD_MAX_RAW_SIZE,
-			phy->raw_samples);
+		       phy->raw_samples);
 
 	/* configure registers used for timers */
 	phy->tim_tx = (void *)TIM_REG_TX(port);
@@ -680,5 +681,5 @@ void pd_hw_init(int port, enum pd_power_role role)
 
 void pd_set_clock(int port, int freq)
 {
-	pd_phy[port].tim_tx->arr = clock_get_freq() / (2*freq);
+	pd_phy[port].tim_tx->arr = clock_get_freq() / (2 * freq);
 }
diff --git a/chip/stm32/usb_power.c b/chip/stm32/usb_power.c
index 3e159d646f..589767f15c 100644
--- a/chip/stm32/usb_power.c
+++ b/chip/stm32/usb_power.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,7 +14,7 @@
 #include "usb_power.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
 
 static int usb_power_init_inas(struct usb_power_config const *config);
 static int usb_power_read(struct usb_power_config const *config);
@@ -42,16 +42,15 @@ void usb_power_deferred_tx(struct usb_power_config const *config)
 		state->reports_xmit_active = state->reports_tail;
 
 		/* Wait for the next command */
-		usb_read_ep(config->endpoint,
-			config->ep->out_databuffer_max,
-			config->ep->out_databuffer);
+		usb_read_ep(config->endpoint, config->ep->out_databuffer_max,
+			    config->ep->out_databuffer);
 		return;
 	}
 }
 
 /* Reset stream */
 void usb_power_event(struct usb_power_config const *config,
-		enum usb_ep_event evt)
+		     enum usb_ep_event evt)
 {
 	if (evt != USB_EVENT_RESET)
 		return;
@@ -68,15 +67,15 @@ void usb_power_event(struct usb_power_config const *config,
 	hook_call_deferred(config->ep->tx_deferred, 0);
 }
 
-
 /* Write one or more power records to USB */
 static int usb_power_write_line(struct usb_power_config const *config)
 {
 	struct usb_power_state *state = config->state;
-	struct usb_power_report *r = (struct usb_power_report *)(
-		state->reports_data_area +
-		(USB_POWER_RECORD_SIZE(state->ina_count)
-		* state->reports_tail));
+	struct usb_power_report *r =
+		(struct usb_power_report *)(state->reports_data_area +
+					    (USB_POWER_RECORD_SIZE(
+						     state->ina_count) *
+					     state->reports_tail));
 	/* status + size + timestamps + power list */
 	size_t bytes = USB_POWER_RECORD_SIZE(state->ina_count);
 
@@ -89,12 +88,12 @@ static int usb_power_write_line(struct usb_power_config const *config)
 			recordcount = config->state->reports_head -
 				      config->state->reports_tail;
 		else
-			recordcount = state->max_cached -
-				      config->state->reports_tail;
+			recordcount =
+				state->max_cached - config->state->reports_tail;
 
 		state->reports_xmit_active = state->reports_tail;
-		state->reports_tail = (state->reports_tail + recordcount) %
-			state->max_cached;
+		state->reports_tail =
+			(state->reports_tail + recordcount) % state->max_cached;
 
 		usb_write_ep(config->endpoint, bytes * recordcount, r);
 		return bytes;
@@ -103,7 +102,6 @@ static int usb_power_write_line(struct usb_power_config const *config)
 	return 0;
 }
 
-
 static int usb_power_state_reset(struct usb_power_config const *config)
 {
 	struct usb_power_state *state = config->state;
@@ -117,7 +115,6 @@ static int usb_power_state_reset(struct usb_power_config const *config)
 	return USB_POWER_SUCCESS;
 }
 
-
 static int usb_power_state_stop(struct usb_power_config const *config)
 {
 	struct usb_power_state *state = config->state;
@@ -137,8 +134,6 @@ static int usb_power_state_stop(struct usb_power_config const *config)
 	return USB_POWER_SUCCESS;
 }
 
-
-
 static int usb_power_state_start(struct usb_power_config const *config,
 				 union usb_power_command_data *cmd, int count)
 {
@@ -182,13 +177,12 @@ static int usb_power_state_start(struct usb_power_config const *config,
 	return USB_POWER_SUCCESS;
 }
 
-
 static int usb_power_state_settime(struct usb_power_config const *config,
-				 union usb_power_command_data *cmd, int count)
+				   union usb_power_command_data *cmd, int count)
 {
 	if (count != sizeof(struct usb_power_command_settime)) {
-		CPRINTS("[SETTIME] Error: count %d is not %d",
-			(int)count, sizeof(struct usb_power_command_settime));
+		CPRINTS("[SETTIME] Error: count %d is not %d", (int)count,
+			sizeof(struct usb_power_command_settime));
 		return USB_POWER_ERROR_READ_SIZE;
 	}
 
@@ -201,9 +195,8 @@ static int usb_power_state_settime(struct usb_power_config const *config,
 	return USB_POWER_SUCCESS;
 }
 
-
 static int usb_power_state_addina(struct usb_power_config const *config,
-				 union usb_power_command_data *cmd, int count)
+				  union usb_power_command_data *cmd, int count)
 {
 	struct usb_power_state *state = config->state;
 	struct usb_power_ina_cfg *ina;
@@ -217,8 +210,8 @@ static int usb_power_state_addina(struct usb_power_config const *config,
 	}
 
 	if (count != sizeof(struct usb_power_command_addina)) {
-		CPRINTS("[ADDINA] Error count %d is not %d",
-			(int)count, sizeof(struct usb_power_command_addina));
+		CPRINTS("[ADDINA] Error count %d is not %d", (int)count,
+			sizeof(struct usb_power_command_addina));
 		return USB_POWER_ERROR_READ_SIZE;
 	}
 
@@ -286,8 +279,8 @@ static int usb_power_read(struct usb_power_config const *config)
 	 * If there is a USB packet waiting we process it and generate a
 	 * response.
 	 */
-	uint8_t count		= rx_ep_pending(config->endpoint);
-	uint8_t result		= USB_POWER_SUCCESS;
+	uint8_t count = rx_ep_pending(config->endpoint);
+	uint8_t result = USB_POWER_SUCCESS;
 	union usb_power_command_data *cmd =
 		(union usb_power_command_data *)config->ep->out_databuffer;
 
@@ -314,14 +307,14 @@ static int usb_power_read(struct usb_power_config const *config)
 		result = usb_power_state_start(config, cmd, count);
 		if (result == USB_POWER_SUCCESS) {
 			/* Send back actual integration time. */
-			ep->in_databuffer[1] =
-				(state->integration_us >> 0) & 0xff;
-			ep->in_databuffer[2] =
-				(state->integration_us >> 8) & 0xff;
-			ep->in_databuffer[3] =
-				(state->integration_us >> 16) & 0xff;
-			ep->in_databuffer[4] =
-				(state->integration_us >> 24) & 0xff;
+			ep->in_databuffer[1] = (state->integration_us >> 0) &
+					       0xff;
+			ep->in_databuffer[2] = (state->integration_us >> 8) &
+					       0xff;
+			ep->in_databuffer[3] = (state->integration_us >> 16) &
+					       0xff;
+			ep->in_databuffer[4] = (state->integration_us >> 24) &
+					       0xff;
 			in_msgsize += 4;
 		}
 		break;
@@ -363,8 +356,6 @@ static int usb_power_read(struct usb_power_config const *config)
 	return EC_SUCCESS;
 }
 
-
-
 /******************************************************************************
  * INA231 interface.
  * List the registers and fields here.
@@ -374,20 +365,19 @@ static int usb_power_read(struct usb_power_config const *config)
 #define INA231_REG_CONF 0
 #define INA231_REG_RSHV 1
 #define INA231_REG_BUSV 2
-#define INA231_REG_PWR  3
+#define INA231_REG_PWR 3
 #define INA231_REG_CURR 4
-#define INA231_REG_CAL  5
-#define INA231_REG_EN   6
-
-
-#define INA231_CONF_AVG(val)		(((int)(val & 0x7)) << 9)
-#define INA231_CONF_BUS_TIME(val)	(((int)(val & 0x7)) << 6)
-#define INA231_CONF_SHUNT_TIME(val)	(((int)(val & 0x7)) << 3)
-#define INA231_CONF_MODE(val)		(((int)(val & 0x7)) << 0)
-#define INA231_MODE_OFF			0x0
-#define INA231_MODE_SHUNT		0x5
-#define INA231_MODE_BUS			0x6
-#define INA231_MODE_BOTH		0x7
+#define INA231_REG_CAL 5
+#define INA231_REG_EN 6
+
+#define INA231_CONF_AVG(val) (((int)(val & 0x7)) << 9)
+#define INA231_CONF_BUS_TIME(val) (((int)(val & 0x7)) << 6)
+#define INA231_CONF_SHUNT_TIME(val) (((int)(val & 0x7)) << 3)
+#define INA231_CONF_MODE(val) (((int)(val & 0x7)) << 0)
+#define INA231_MODE_OFF 0x0
+#define INA231_MODE_SHUNT 0x5
+#define INA231_MODE_BUS 0x6
+#define INA231_MODE_BOTH 0x7
 
 int reg_type_mapping(enum usb_power_ina_type ina_type)
 {
@@ -411,36 +401,32 @@ uint16_t ina2xx_readagain(uint8_t port, uint16_t addr_flags)
 	int res;
 	uint16_t val;
 
-	res = i2c_xfer(port, addr_flags,
-		       NULL, 0, (uint8_t *)&val, sizeof(uint16_t));
+	res = i2c_xfer(port, addr_flags, NULL, 0, (uint8_t *)&val,
+		       sizeof(uint16_t));
 
 	if (res) {
-		CPRINTS("INA2XX I2C readagain failed p:%d a:%02x",
-			(int)port, (int)I2C_STRIP_FLAGS(addr_flags));
+		CPRINTS("INA2XX I2C readagain failed p:%d a:%02x", (int)port,
+			(int)I2C_STRIP_FLAGS(addr_flags));
 		return 0x0bad;
 	}
 	return (val >> 8) | ((val & 0xff) << 8);
 }
 
-
-uint16_t ina2xx_read(uint8_t port, uint16_t addr_flags,
-		     uint8_t reg)
+uint16_t ina2xx_read(uint8_t port, uint16_t addr_flags, uint8_t reg)
 {
 	int res;
 	int val;
 
 	res = i2c_read16(port, addr_flags, reg, &val);
 	if (res) {
-		CPRINTS("INA2XX I2C read failed p:%d a:%02x, r:%02x",
-			(int)port, (int)I2C_STRIP_FLAGS(addr_flags),
-			(int)reg);
+		CPRINTS("INA2XX I2C read failed p:%d a:%02x, r:%02x", (int)port,
+			(int)I2C_STRIP_FLAGS(addr_flags), (int)reg);
 		return 0x0bad;
 	}
 	return (val >> 8) | ((val & 0xff) << 8);
 }
 
-int ina2xx_write(uint8_t port, uint16_t addr_flags,
-		 uint8_t reg, uint16_t val)
+int ina2xx_write(uint8_t port, uint16_t addr_flags, uint8_t reg, uint16_t val)
 {
 	int res;
 	uint16_t be_val = (val >> 8) | ((val & 0xff) << 8);
@@ -451,8 +437,6 @@ int ina2xx_write(uint8_t port, uint16_t addr_flags,
 	return res;
 }
 
-
-
 /******************************************************************************
  * Background tasks
  *
@@ -462,11 +446,10 @@ int ina2xx_write(uint8_t port, uint16_t addr_flags,
  */
 
 /* INA231 integration and averaging time presets, indexed by register value */
-#define NELEMS(x)  (sizeof(x) / sizeof((x)[0]))
-static const int average_settings[] = {
-	1, 4, 16, 64, 128, 256, 512, 1024};
-static const int conversion_time_us[] =	{
-	140, 204, 332, 588, 1100, 2116, 4156, 8244};
+#define NELEMS(x) (sizeof(x) / sizeof((x)[0]))
+static const int average_settings[] = { 1, 4, 16, 64, 128, 256, 512, 1024 };
+static const int conversion_time_us[] = { 140,	204,  332,  588,
+					  1100, 2116, 4156, 8244 };
 
 static int usb_power_init_inas(struct usb_power_config const *config)
 {
@@ -491,8 +474,7 @@ static int usb_power_init_inas(struct usb_power_config const *config)
 	/* Find an averaging setting from the INA presets that fits. */
 	while (avg < (NELEMS(average_settings) - 1)) {
 		if ((conversion_time_us[shunt_time] *
-		     average_settings[avg + 1])
-		    > target_us)
+		     average_settings[avg + 1]) > target_us)
 			break;
 		avg++;
 	}
@@ -507,15 +489,15 @@ static int usb_power_init_inas(struct usb_power_config const *config)
 
 #ifdef USB_POWER_VERBOSE
 		{
-		int conf, cal;
-
-		conf = ina2xx_read(ina->port, ina->addr_flags,
-				   INA231_REG_CONF);
-		cal = ina2xx_read(ina->port, ina->addr_flags,
-				  INA231_REG_CAL);
-		CPRINTS("[CAP] %d (%d,0x%02x): conf:%x, cal:%x",
-			i, ina->port, I2C_STRIP_FLAGS(ina->addr_flags),
-			conf, cal);
+			int conf, cal;
+
+			conf = ina2xx_read(ina->port, ina->addr_flags,
+					   INA231_REG_CONF);
+			cal = ina2xx_read(ina->port, ina->addr_flags,
+					  INA231_REG_CAL);
+			CPRINTS("[CAP] %d (%d,0x%02x): conf:%x, cal:%x", i,
+				ina->port, I2C_STRIP_FLAGS(ina->addr_flags),
+				conf, cal);
 		}
 #endif
 		/*
@@ -536,54 +518,53 @@ static int usb_power_init_inas(struct usb_power_config const *config)
 		if (ina->scale == 0)
 			return -1;
 		value = (5120000 * 100) / (ina->scale * ina->rs);
-		ret = ina2xx_write(ina->port, ina->addr_flags,
-				   INA231_REG_CAL, value);
+		ret = ina2xx_write(ina->port, ina->addr_flags, INA231_REG_CAL,
+				   value);
 		if (ret != EC_SUCCESS) {
 			CPRINTS("[CAP] usb_power_init_inas CAL FAIL: %d", ret);
 			return ret;
 		}
 #ifdef USB_POWER_VERBOSE
 		{
-		int actual;
+			int actual;
 
-		actual = ina2xx_read(ina->port, ina->addr_flags,
-				     INA231_REG_CAL);
-		CPRINTS("[CAP] scale: %d uA/div, %d uW/div, cal:%x act:%x",
-			ina->scale / 100, ina->scale*25/100, value, actual);
+			actual = ina2xx_read(ina->port, ina->addr_flags,
+					     INA231_REG_CAL);
+			CPRINTS("[CAP] scale: %d uA/div, %d uW/div, cal:%x act:%x",
+				ina->scale / 100, ina->scale * 25 / 100, value,
+				actual);
 		}
 #endif
 		/* Conversion time, shunt + bus, set average. */
 		value = INA231_CONF_MODE(INA231_MODE_BOTH) |
 			INA231_CONF_SHUNT_TIME(shunt_time) |
-			INA231_CONF_BUS_TIME(shunt_time) |
-			INA231_CONF_AVG(avg);
-		ret = ina2xx_write(ina->port, ina->addr_flags,
-				   INA231_REG_CONF, value);
+			INA231_CONF_BUS_TIME(shunt_time) | INA231_CONF_AVG(avg);
+		ret = ina2xx_write(ina->port, ina->addr_flags, INA231_REG_CONF,
+				   value);
 		if (ret != EC_SUCCESS) {
 			CPRINTS("[CAP] usb_power_init_inas CONF FAIL: %d", ret);
 			return ret;
 		}
 #ifdef USB_POWER_VERBOSE
 		{
-		int actual;
+			int actual;
 
-		actual = ina2xx_read(ina->port, ina->addr_flags,
-				     INA231_REG_CONF);
-		CPRINTS("[CAP] %d (%d,0x%02x): conf:%x, act:%x",
-			i, ina->port, I2C_STRIP_FLAGS(ina->addr_flags),
-			value, actual);
+			actual = ina2xx_read(ina->port, ina->addr_flags,
+					     INA231_REG_CONF);
+			CPRINTS("[CAP] %d (%d,0x%02x): conf:%x, act:%x", i,
+				ina->port, I2C_STRIP_FLAGS(ina->addr_flags),
+				value, actual);
 		}
 #endif
 #ifdef USB_POWER_VERBOSE
 		{
-		int busv_mv =
-			(ina2xx_read(ina->port, ina->addr_flags,
-				     INA231_REG_BUSV)
-			 * 125) / 100;
-
-		CPRINTS("[CAP] %d (%d,0x%02x): busv:%dmv",
-			i, ina->port, I2C_STRIP_FLAGS(ina->addr_flags),
-			busv_mv);
+			int busv_mv = (ina2xx_read(ina->port, ina->addr_flags,
+						   INA231_REG_BUSV) *
+				       125) /
+				      100;
+
+			CPRINTS("[CAP] %d (%d,0x%02x): busv:%dmv", i, ina->port,
+				I2C_STRIP_FLAGS(ina->addr_flags), busv_mv);
 		}
 #endif
 		/* Initialize read from power register. This register address
@@ -600,7 +581,6 @@ static int usb_power_init_inas(struct usb_power_config const *config)
 	return EC_SUCCESS;
 }
 
-
 /*
  * Read each INA's power integration measurement.
  *
@@ -614,19 +594,20 @@ static int usb_power_get_samples(struct usb_power_config const *config)
 {
 	uint64_t time = get_time().val;
 	struct usb_power_state *state = config->state;
-	struct usb_power_report *r = (struct usb_power_report *)(
-		state->reports_data_area +
-		(USB_POWER_RECORD_SIZE(state->ina_count)
-		* state->reports_head));
+	struct usb_power_report *r =
+		(struct usb_power_report *)(state->reports_data_area +
+					    (USB_POWER_RECORD_SIZE(
+						     state->ina_count) *
+					     state->reports_head));
 	struct usb_power_ina_cfg *inas = state->ina_cfg;
 	int i;
 
 	/* TODO(nsanders): Would we prefer to evict oldest? */
-	if (((state->reports_head + 1) % USB_POWER_MAX_CACHED(state->ina_count))
-	    == state->reports_xmit_active) {
-		CPRINTS("Overflow! h:%d a:%d t:%d (%d)",
-			state->reports_head, state->reports_xmit_active,
-			state->reports_tail,
+	if (((state->reports_head + 1) %
+	     USB_POWER_MAX_CACHED(state->ina_count)) ==
+	    state->reports_xmit_active) {
+		CPRINTS("Overflow! h:%d a:%d t:%d (%d)", state->reports_head,
+			state->reports_xmit_active, state->reports_tail,
 			USB_POWER_MAX_CACHED(state->ina_count));
 		return USB_POWER_ERROR_OVERFLOW;
 	}
@@ -650,47 +631,48 @@ static int usb_power_get_samples(struct usb_power_config const *config)
 		 */
 		if (ina->shared)
 			regval = ina2xx_read(ina->port, ina->addr_flags,
-					reg_type_mapping(ina->type));
+					     reg_type_mapping(ina->type));
 		else
-			regval = ina2xx_readagain(ina->port,
-						  ina->addr_flags);
+			regval = ina2xx_readagain(ina->port, ina->addr_flags);
 		r->power[i] = regval;
 #ifdef USB_POWER_VERBOSE
 		{
-		int current;
-		int power;
-		int voltage;
-		int bvoltage;
-
-		voltage = ina2xx_read(ina->port, ina->addr_flags,
-				      INA231_REG_RSHV);
-		bvoltage = ina2xx_read(ina->port, ina->addr_flags,
-				       INA231_REG_BUSV);
-		current = ina2xx_read(ina->port, ina->addr_flags,
-				      INA231_REG_CURR);
-		power = ina2xx_read(ina->port, ina->addr_flags,
-				    INA231_REG_PWR);
-		{
-		int uV = ((int)voltage * 25) / 10;
-		int mV = ((int)bvoltage * 125) / 100;
-		int uA = (uV * 1000) / ina->rs;
-		int CuA = (((int)current * ina->scale) / 100);
-		int uW = (((int)power * ina->scale*25)/100);
-
-		CPRINTS("[CAP] %d (%d,0x%02x): %dmV / %dmO = %dmA",
-			i, ina->port, I2C_STRIP_FLAGS(ina->addr_flags),
-			uV/1000, ina->rs, uA/1000);
-		CPRINTS("[CAP] %duV %dmV %duA %dCuA "
-			"%duW v:%04x, b:%04x, p:%04x",
-			uV, mV, uA, CuA, uW, voltage, bvoltage, power);
-		}
+			int current;
+			int power;
+			int voltage;
+			int bvoltage;
+
+			voltage = ina2xx_read(ina->port, ina->addr_flags,
+					      INA231_REG_RSHV);
+			bvoltage = ina2xx_read(ina->port, ina->addr_flags,
+					       INA231_REG_BUSV);
+			current = ina2xx_read(ina->port, ina->addr_flags,
+					      INA231_REG_CURR);
+			power = ina2xx_read(ina->port, ina->addr_flags,
+					    INA231_REG_PWR);
+			{
+				int uV = ((int)voltage * 25) / 10;
+				int mV = ((int)bvoltage * 125) / 100;
+				int uA = (uV * 1000) / ina->rs;
+				int CuA = (((int)current * ina->scale) / 100);
+				int uW = (((int)power * ina->scale * 25) / 100);
+
+				CPRINTS("[CAP] %d (%d,0x%02x): %dmV / %dmO = %dmA",
+					i, ina->port,
+					I2C_STRIP_FLAGS(ina->addr_flags),
+					uV / 1000, ina->rs, uA / 1000);
+				CPRINTS("[CAP] %duV %dmV %duA %dCuA "
+					"%duW v:%04x, b:%04x, p:%04x",
+					uV, mV, uA, CuA, uW, voltage, bvoltage,
+					power);
+			}
 		}
 #endif
 	}
 
 	/* Mark this slot as used. */
 	state->reports_head = (state->reports_head + 1) %
-		USB_POWER_MAX_CACHED(state->ina_count);
+			      USB_POWER_MAX_CACHED(state->ina_count);
 
 	return EC_SUCCESS;
 }
diff --git a/chip/stm32/usb_power.h b/chip/stm32/usb_power.h
index 51220691b6..1445fcea0f 100644
--- a/chip/stm32/usb_power.h
+++ b/chip/stm32/usb_power.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -38,7 +38,8 @@
  *
  *     addina:	0x0002
  *     +--------+--------------------------+-------------+--------------+-----------+--------+
- *     | 0x0002 | 1B: 4b: extender 4b: bus | 1B:INA type | 1B: INA addr | 1B: extra | 4B: Rs |
+ *     | 0x0002 | 1B: 4b: extender 4b: bus | 1B:INA type | 1B: INA addr | 1B:
+ *extra | 4B: Rs |
  *     +--------+--------------------------+-------------+--------------+-----------+--------+
  *
  *     start:	0x0003
@@ -90,40 +91,40 @@
 
 /* 8b status field. */
 enum usb_power_error {
-	USB_POWER_SUCCESS		= 0x00,
-	USB_POWER_ERROR_I2C		= 0x01,
-	USB_POWER_ERROR_OVERFLOW	= 0x02,
-	USB_POWER_ERROR_NOT_SETUP	= 0x03,
-	USB_POWER_ERROR_NOT_CAPTURING	= 0x04,
-	USB_POWER_ERROR_TIMEOUT		= 0x05,
-	USB_POWER_ERROR_BUSY		= 0x06,
-	USB_POWER_ERROR_READ_SIZE	= 0x07,
-	USB_POWER_ERROR_FULL		= 0x08,
-	USB_POWER_ERROR_INVAL		= 0x09,
-	USB_POWER_ERROR_UNKNOWN		= 0x80,
+	USB_POWER_SUCCESS = 0x00,
+	USB_POWER_ERROR_I2C = 0x01,
+	USB_POWER_ERROR_OVERFLOW = 0x02,
+	USB_POWER_ERROR_NOT_SETUP = 0x03,
+	USB_POWER_ERROR_NOT_CAPTURING = 0x04,
+	USB_POWER_ERROR_TIMEOUT = 0x05,
+	USB_POWER_ERROR_BUSY = 0x06,
+	USB_POWER_ERROR_READ_SIZE = 0x07,
+	USB_POWER_ERROR_FULL = 0x08,
+	USB_POWER_ERROR_INVAL = 0x09,
+	USB_POWER_ERROR_UNKNOWN = 0x80,
 };
 
 /* 16b command field. */
 enum usb_power_command {
-	USB_POWER_CMD_RESET	= 0x0000,
-	USB_POWER_CMD_STOP	= 0x0001,
-	USB_POWER_CMD_ADDINA	= 0x0002,
-	USB_POWER_CMD_START	= 0x0003,
-	USB_POWER_CMD_NEXT	= 0x0004,
-	USB_POWER_CMD_SETTIME	= 0x0005,
+	USB_POWER_CMD_RESET = 0x0000,
+	USB_POWER_CMD_STOP = 0x0001,
+	USB_POWER_CMD_ADDINA = 0x0002,
+	USB_POWER_CMD_START = 0x0003,
+	USB_POWER_CMD_NEXT = 0x0004,
+	USB_POWER_CMD_SETTIME = 0x0005,
 };
 
 /* Addina "INA Type" field. */
 enum usb_power_ina_type {
-	USBP_INA231_POWER	= 0x01,
-	USBP_INA231_BUSV	= 0x02,
-	USBP_INA231_CURRENT	= 0x03,
-	USBP_INA231_SHUNTV	= 0x04,
+	USBP_INA231_POWER = 0x01,
+	USBP_INA231_BUSV = 0x02,
+	USBP_INA231_CURRENT = 0x03,
+	USBP_INA231_SHUNTV = 0x04,
 };
 
 /* Internal state machine values */
 enum usb_power_states {
-	USB_POWER_STATE_OFF	= 0,
+	USB_POWER_STATE_OFF = 0,
 	USB_POWER_STATE_SETUP,
 	USB_POWER_STATE_CAPTURING,
 };
@@ -154,8 +155,7 @@ struct usb_power_ina_cfg {
 	int shared;
 };
 
-
-struct __attribute__ ((__packed__)) usb_power_report {
+struct __attribute__((__packed__)) usb_power_report {
 	uint8_t status;
 	uint8_t size;
 	uint64_t timestamp;
@@ -163,17 +163,19 @@ struct __attribute__ ((__packed__)) usb_power_report {
 };
 
 /* Must be 4 byte aligned */
-#define USB_POWER_RECORD_SIZE(ina_count)				\
-	((((sizeof(struct usb_power_report)				\
-	- (sizeof(uint16_t) * USB_POWER_MAX_READ_COUNT)			\
-	+ (sizeof(uint16_t) * (ina_count))) + 3) / 4) * 4)
-
-#define USB_POWER_DATA_SIZE						\
+#define USB_POWER_RECORD_SIZE(ina_count)                    \
+	((((sizeof(struct usb_power_report) -               \
+	    (sizeof(uint16_t) * USB_POWER_MAX_READ_COUNT) + \
+	    (sizeof(uint16_t) * (ina_count))) +             \
+	   3) /                                             \
+	  4) *                                              \
+	 4)
+
+#define USB_POWER_DATA_SIZE \
 	(sizeof(struct usb_power_report) * (USB_POWER_MIN_CACHED + 1))
-#define USB_POWER_MAX_CACHED(ina_count)					\
+#define USB_POWER_MAX_CACHED(ina_count) \
 	(USB_POWER_DATA_SIZE / USB_POWER_RECORD_SIZE(ina_count))
 
-
 struct usb_power_state {
 	/*
 	 * The power data acquisition must be setup, then started, in order to
@@ -212,7 +214,6 @@ struct usb_power_state {
 	uint8_t tx_buf[USB_MAX_PACKET_SIZE * 4];
 };
 
-
 /*
  * Compile time Per-USB gpio configuration stored in flash.  Instances of this
  * structure are provided by the user of the USB gpio.  This structure binds
@@ -234,12 +235,12 @@ struct usb_power_config {
 	const struct deferred_data *deferred_cap;
 };
 
-struct __attribute__ ((__packed__)) usb_power_command_start {
+struct __attribute__((__packed__)) usb_power_command_start {
 	uint16_t command;
 	uint32_t integration_us;
 };
 
-struct __attribute__ ((__packed__)) usb_power_command_addina {
+struct __attribute__((__packed__)) usb_power_command_addina {
 	uint16_t command;
 	uint8_t port;
 	uint8_t type;
@@ -248,7 +249,7 @@ struct __attribute__ ((__packed__)) usb_power_command_addina {
 	uint32_t rs;
 };
 
-struct __attribute__ ((__packed__)) usb_power_command_settime {
+struct __attribute__((__packed__)) usb_power_command_settime {
 	uint16_t command;
 	uint64_t time;
 };
@@ -260,7 +261,6 @@ union usb_power_command_data {
 	struct usb_power_command_settime settime;
 };
 
-
 /*
  * Convenience macro for defining a USB INA Power driver.
  *
@@ -273,92 +273,96 @@ union usb_power_command_data {
  * ENDPOINT is the index of the USB bulk endpoint used for receiving and
  * transmitting bytes.
  */
-#define USB_POWER_CONFIG(NAME,						\
-		       INTERFACE,					\
-		       ENDPOINT)					\
-	static void CONCAT2(NAME, _deferred_tx_)(void);			\
-	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_tx_));			\
-	static void CONCAT2(NAME, _deferred_rx_)(void);			\
-	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_rx_));			\
-	static void CONCAT2(NAME, _deferred_cap_)(void);		\
-	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_cap_));		\
-	struct usb_power_state CONCAT2(NAME, _state_) = {		\
-		.state = USB_POWER_STATE_OFF,				\
-		.ina_count = 0,						\
-		.integration_us = 0,					\
-		.reports_head = 0,					\
-		.reports_tail = 0,					\
-		.wall_offset = 0,					\
-	};								\
-	static struct dwc_usb_ep CONCAT2(NAME, _ep_ctl) = {		\
-		.max_packet = USB_MAX_PACKET_SIZE,			\
-		.tx_fifo = ENDPOINT,					\
-		.out_pending = 0,					\
-		.out_data = 0,						\
-		.out_databuffer = 0,					\
-		.out_databuffer_max = 0,				\
-		.rx_deferred = &CONCAT2(NAME, _deferred_rx__data),	\
-		.in_packets = 0,					\
-		.in_pending = 0,					\
-		.in_data = 0,						\
-		.in_databuffer = 0,					\
-		.in_databuffer_max = 0,					\
-		.tx_deferred = &CONCAT2(NAME, _deferred_tx__data),	\
-	};								\
-	struct usb_power_config const NAME = {				\
-		.state     = &CONCAT2(NAME, _state_),			\
-		.ep	= &CONCAT2(NAME, _ep_ctl),			\
-		.interface = INTERFACE,					\
-		.endpoint  = ENDPOINT,					\
-		.deferred_cap  = &CONCAT2(NAME, _deferred_cap__data),	\
-	};								\
-	const struct usb_interface_descriptor				\
-	USB_IFACE_DESC(INTERFACE) = {					\
-		.bLength	    = USB_DT_INTERFACE_SIZE,		\
-		.bDescriptorType    = USB_DT_INTERFACE,			\
-		.bInterfaceNumber   = INTERFACE,			\
-		.bAlternateSetting  = 0,				\
-		.bNumEndpoints      = 2,				\
-		.bInterfaceClass    = USB_CLASS_VENDOR_SPEC,		\
-		.bInterfaceSubClass = USB_SUBCLASS_GOOGLE_POWER,	\
-		.bInterfaceProtocol = USB_PROTOCOL_GOOGLE_POWER,	\
-		.iInterface	 = 0,				\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 0) = {					\
-		.bLength	  = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = 0x80 | ENDPOINT,			\
-		.bmAttributes     = 0x02 /* Bulk IN */,			\
-		.wMaxPacketSize   = USB_MAX_PACKET_SIZE,		\
-		.bInterval	= 1,					\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 1) = {					\
-		.bLength	  = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = ENDPOINT,				\
-		.bmAttributes     = 0x02 /* Bulk OUT */,		\
-		.wMaxPacketSize   = USB_MAX_PACKET_SIZE,		\
-		.bInterval	= 0,					\
-	};								\
-	static void CONCAT2(NAME, _ep_tx_)   (void) { usb_epN_tx(ENDPOINT); } \
-	static void CONCAT2(NAME, _ep_rx_)   (void) { usb_epN_rx(ENDPOINT); } \
-	static void CONCAT2(NAME, _ep_event_)(enum usb_ep_event evt)	\
-	{								\
-			usb_power_event(&NAME, evt);			\
-	}								\
-	USB_DECLARE_EP(ENDPOINT,					\
-		       CONCAT2(NAME, _ep_tx_),				\
-		       CONCAT2(NAME, _ep_rx_),				\
-		       CONCAT2(NAME, _ep_event_));			\
-	static void CONCAT2(NAME, _deferred_tx_)(void)			\
-	{ usb_power_deferred_tx(&NAME); }				\
-	static void CONCAT2(NAME, _deferred_rx_)(void)			\
-	{ usb_power_deferred_rx(&NAME); }				\
-	static void CONCAT2(NAME, _deferred_cap_)(void)			\
-	{ usb_power_deferred_cap(&NAME); }
-
+#define USB_POWER_CONFIG(NAME, INTERFACE, ENDPOINT)                         \
+	static void CONCAT2(NAME, _deferred_tx_)(void);                     \
+	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_tx_));                     \
+	static void CONCAT2(NAME, _deferred_rx_)(void);                     \
+	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_rx_));                     \
+	static void CONCAT2(NAME, _deferred_cap_)(void);                    \
+	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_cap_));                    \
+	struct usb_power_state CONCAT2(NAME, _state_) = {                   \
+		.state = USB_POWER_STATE_OFF,                               \
+		.ina_count = 0,                                             \
+		.integration_us = 0,                                        \
+		.reports_head = 0,                                          \
+		.reports_tail = 0,                                          \
+		.wall_offset = 0,                                           \
+	};                                                                  \
+	static struct dwc_usb_ep CONCAT2(NAME, _ep_ctl) = {                 \
+		.max_packet = USB_MAX_PACKET_SIZE,                          \
+		.tx_fifo = ENDPOINT,                                        \
+		.out_pending = 0,                                           \
+		.out_data = 0,                                              \
+		.out_databuffer = 0,                                        \
+		.out_databuffer_max = 0,                                    \
+		.rx_deferred = &CONCAT2(NAME, _deferred_rx__data),          \
+		.in_packets = 0,                                            \
+		.in_pending = 0,                                            \
+		.in_data = 0,                                               \
+		.in_databuffer = 0,                                         \
+		.in_databuffer_max = 0,                                     \
+		.tx_deferred = &CONCAT2(NAME, _deferred_tx__data),          \
+	};                                                                  \
+	struct usb_power_config const NAME = {                              \
+		.state = &CONCAT2(NAME, _state_),                           \
+		.ep = &CONCAT2(NAME, _ep_ctl),                              \
+		.interface = INTERFACE,                                     \
+		.endpoint = ENDPOINT,                                       \
+		.deferred_cap = &CONCAT2(NAME, _deferred_cap__data),        \
+	};                                                                  \
+	const struct usb_interface_descriptor USB_IFACE_DESC(INTERFACE) = { \
+		.bLength = USB_DT_INTERFACE_SIZE,                           \
+		.bDescriptorType = USB_DT_INTERFACE,                        \
+		.bInterfaceNumber = INTERFACE,                              \
+		.bAlternateSetting = 0,                                     \
+		.bNumEndpoints = 2,                                         \
+		.bInterfaceClass = USB_CLASS_VENDOR_SPEC,                   \
+		.bInterfaceSubClass = USB_SUBCLASS_GOOGLE_POWER,            \
+		.bInterfaceProtocol = USB_PROTOCOL_GOOGLE_POWER,            \
+		.iInterface = 0,                                            \
+	};                                                                  \
+	const struct usb_endpoint_descriptor USB_EP_DESC(INTERFACE, 0) = {  \
+		.bLength = USB_DT_ENDPOINT_SIZE,                            \
+		.bDescriptorType = USB_DT_ENDPOINT,                         \
+		.bEndpointAddress = 0x80 | ENDPOINT,                        \
+		.bmAttributes = 0x02 /* Bulk IN */,                         \
+		.wMaxPacketSize = USB_MAX_PACKET_SIZE,                      \
+		.bInterval = 1,                                             \
+	};                                                                  \
+	const struct usb_endpoint_descriptor USB_EP_DESC(INTERFACE, 1) = {  \
+		.bLength = USB_DT_ENDPOINT_SIZE,                            \
+		.bDescriptorType = USB_DT_ENDPOINT,                         \
+		.bEndpointAddress = ENDPOINT,                               \
+		.bmAttributes = 0x02 /* Bulk OUT */,                        \
+		.wMaxPacketSize = USB_MAX_PACKET_SIZE,                      \
+		.bInterval = 0,                                             \
+	};                                                                  \
+	static void CONCAT2(NAME, _ep_tx_)(void)                            \
+	{                                                                   \
+		usb_epN_tx(ENDPOINT);                                       \
+	}                                                                   \
+	static void CONCAT2(NAME, _ep_rx_)(void)                            \
+	{                                                                   \
+		usb_epN_rx(ENDPOINT);                                       \
+	}                                                                   \
+	static void CONCAT2(NAME, _ep_event_)(enum usb_ep_event evt)        \
+	{                                                                   \
+		usb_power_event(&NAME, evt);                                \
+	}                                                                   \
+	USB_DECLARE_EP(ENDPOINT, CONCAT2(NAME, _ep_tx_),                    \
+		       CONCAT2(NAME, _ep_rx_), CONCAT2(NAME, _ep_event_));  \
+	static void CONCAT2(NAME, _deferred_tx_)(void)                      \
+	{                                                                   \
+		usb_power_deferred_tx(&NAME);                               \
+	}                                                                   \
+	static void CONCAT2(NAME, _deferred_rx_)(void)                      \
+	{                                                                   \
+		usb_power_deferred_rx(&NAME);                               \
+	}                                                                   \
+	static void CONCAT2(NAME, _deferred_cap_)(void)                     \
+	{                                                                   \
+		usb_power_deferred_cap(&NAME);                              \
+	}
 
 /*
  * Handle power request in a deferred callback.
@@ -374,9 +378,6 @@ void usb_power_deferred_cap(struct usb_power_config const *config);
 void usb_power_tx(struct usb_power_config const *config);
 void usb_power_rx(struct usb_power_config const *config);
 void usb_power_event(struct usb_power_config const *config,
-		enum usb_ep_event evt);
-
-
-
+		     enum usb_ep_event evt);
 
 #endif /* __CROS_EC_USB_DWC_POWER_H */
diff --git a/chip/stm32/usb_spi.c b/chip/stm32/usb_spi.c
index e80d15b6cd..5ea813a86c 100644
--- a/chip/stm32/usb_spi.c
+++ b/chip/stm32/usb_spi.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,9 +17,9 @@
 static bool usb_spi_received_packet(struct usb_spi_config const *config);
 static bool usb_spi_transmitted_packet(struct usb_spi_config const *config);
 static void usb_spi_read_packet(struct usb_spi_config const *config,
-			struct usb_spi_packet_ctx *packet);
+				struct usb_spi_packet_ctx *packet);
 static void usb_spi_write_packet(struct usb_spi_config const *config,
-			struct usb_spi_packet_ctx *packet);
+				 struct usb_spi_packet_ctx *packet);
 
 /*
  * Map EC error codes to USB_SPI error codes.
@@ -31,10 +31,14 @@ static void usb_spi_write_packet(struct usb_spi_config const *config,
 static int16_t usb_spi_map_error(int error)
 {
 	switch (error) {
-	case EC_SUCCESS:       return USB_SPI_SUCCESS;
-	case EC_ERROR_TIMEOUT: return USB_SPI_TIMEOUT;
-	case EC_ERROR_BUSY:    return USB_SPI_BUSY;
-	default:               return USB_SPI_UNKNOWN_ERROR | (error & 0x7fff);
+	case EC_SUCCESS:
+		return USB_SPI_SUCCESS;
+	case EC_ERROR_TIMEOUT:
+		return USB_SPI_TIMEOUT;
+	case EC_ERROR_BUSY:
+		return USB_SPI_BUSY;
+	default:
+		return USB_SPI_UNKNOWN_ERROR | (error & 0x7fff);
 	}
 }
 
@@ -47,7 +51,7 @@ static int16_t usb_spi_map_error(int error)
  * @returns         USB_SPI_RX_DATA_OVERFLOW if the source packet is too large
  */
 static int usb_spi_read_usb_packet(struct usb_spi_transfer_ctx *dst,
-				const struct usb_spi_packet_ctx *src)
+				   const struct usb_spi_packet_ctx *src)
 {
 	size_t max_read_length = dst->transfer_size - dst->transfer_index;
 	size_t bytes_in_buffer = src->packet_size - src->header_size;
@@ -61,7 +65,7 @@ static int usb_spi_read_usb_packet(struct usb_spi_transfer_ctx *dst,
 		return USB_SPI_RX_DATA_OVERFLOW;
 	}
 	memcpy(dst->buffer + dst->transfer_index, packet_buffer,
-		bytes_in_buffer);
+	       bytes_in_buffer);
 
 	dst->transfer_index += bytes_in_buffer;
 	return USB_SPI_SUCCESS;
@@ -74,7 +78,7 @@ static int usb_spi_read_usb_packet(struct usb_spi_transfer_ctx *dst,
  * @param src       Source transmit context we are reading data from.
  */
 static void usb_spi_fill_usb_packet(struct usb_spi_packet_ctx *dst,
-				struct usb_spi_transfer_ctx *src)
+				    struct usb_spi_transfer_ctx *src)
 {
 	size_t transfer_size = src->transfer_size - src->transfer_index;
 	size_t max_buffer_size = USB_MAX_PACKET_SIZE - dst->header_size;
@@ -97,7 +101,7 @@ static void usb_spi_fill_usb_packet(struct usb_spi_packet_ctx *dst,
  * @param read_count    Number of bytes to read in the SPI transfer
  */
 static void usb_spi_setup_transfer(struct usb_spi_config const *config,
-				size_t write_count, size_t read_count)
+				   size_t write_count, size_t read_count)
 {
 	/* Reset any status code. */
 	config->state->status_code = USB_SPI_SUCCESS;
@@ -145,7 +149,7 @@ static bool usb_spi_response_in_progress(struct usb_spi_config const *config)
  * @param status_code	status code to set for the response.
  */
 static void setup_transfer_response(struct usb_spi_config const *config,
-				uint16_t status_code)
+				    uint16_t status_code)
 {
 	config->state->status_code = status_code;
 	config->state->spi_read_ctx.transfer_index = 0;
@@ -163,7 +167,7 @@ static void setup_transfer_response(struct usb_spi_config const *config,
  * @param packet        Packet buffer we will be transmitting.
  */
 static void create_spi_config_response(struct usb_spi_config const *config,
-				struct usb_spi_packet_ctx *packet)
+				       struct usb_spi_packet_ctx *packet)
 {
 	/* Construct the response packet. */
 	packet->rsp_config.packet_id = USB_SPI_PKT_ID_RSP_USB_SPI_CONFIG;
@@ -175,8 +179,7 @@ static void create_spi_config_response(struct usb_spi_config const *config,
 	packet->rsp_config.feature_bitmap |=
 		USB_SPI_FEATURE_FULL_DUPLEX_SUPPORTED;
 #endif
-	packet->packet_size =
-		sizeof(struct usb_spi_response_configuration_v2);
+	packet->packet_size = sizeof(struct usb_spi_response_configuration_v2);
 }
 
 static void create_spi_chip_select_response(struct usb_spi_config const *config,
@@ -196,16 +199,14 @@ static void create_spi_chip_select_response(struct usb_spi_config const *config,
  * @param config        USB SPI config
  * @param packet        Packet buffer we will be transmitting.
  */
-static void usb_spi_create_spi_transfer_response(
-				struct usb_spi_config const *config,
-				struct usb_spi_packet_ctx *transmit_packet)
+static void
+usb_spi_create_spi_transfer_response(struct usb_spi_config const *config,
+				     struct usb_spi_packet_ctx *transmit_packet)
 {
-
 	if (!usb_spi_response_in_progress(config))
 		return;
 
 	if (config->state->spi_read_ctx.transfer_index == 0) {
-
 		/* Transmit the first packet with the status code. */
 		transmit_packet->header_size =
 			offsetof(struct usb_spi_response_v2, data);
@@ -215,10 +216,9 @@ static void usb_spi_create_spi_transfer_response(
 			config->state->status_code;
 
 		usb_spi_fill_usb_packet(transmit_packet,
-			&config->state->spi_read_ctx);
+					&config->state->spi_read_ctx);
 	} else if (config->state->spi_read_ctx.transfer_index <
-		config->state->spi_read_ctx.transfer_size) {
-
+		   config->state->spi_read_ctx.transfer_size) {
 		/* Transmit the continue packets. */
 		transmit_packet->header_size =
 			offsetof(struct usb_spi_continue_v2, data);
@@ -228,10 +228,10 @@ static void usb_spi_create_spi_transfer_response(
 			config->state->spi_read_ctx.transfer_index;
 
 		usb_spi_fill_usb_packet(transmit_packet,
-			&config->state->spi_read_ctx);
+					&config->state->spi_read_ctx);
 	}
 	if (config->state->spi_read_ctx.transfer_index <
-		config->state->spi_read_ctx.transfer_size) {
+	    config->state->spi_read_ctx.transfer_size) {
 		config->state->mode = USB_SPI_MODE_CONTINUE_RESPONSE;
 	} else {
 		config->state->mode = USB_SPI_MODE_IDLE;
@@ -245,7 +245,7 @@ static void usb_spi_create_spi_transfer_response(
  * @param packet        Received packet to process.
  */
 static void usb_spi_process_rx_packet(struct usb_spi_config const *config,
-				struct usb_spi_packet_ctx *packet)
+				      struct usb_spi_packet_ctx *packet)
 {
 	if (packet->packet_size < USB_SPI_MIN_PACKET_SIZE) {
 		/* No valid packet exists smaller than the packet id. */
@@ -256,14 +256,12 @@ static void usb_spi_process_rx_packet(struct usb_spi_config const *config,
 	config->state->mode = USB_SPI_MODE_IDLE;
 
 	switch (packet->packet_id) {
-	case USB_SPI_PKT_ID_CMD_GET_USB_SPI_CONFIG:
-	{
+	case USB_SPI_PKT_ID_CMD_GET_USB_SPI_CONFIG: {
 		/* The host requires the SPI configuration. */
 		config->state->mode = USB_SPI_MODE_SEND_CONFIGURATION;
 		break;
 	}
-	case USB_SPI_PKT_ID_CMD_RESTART_RESPONSE:
-	{
+	case USB_SPI_PKT_ID_CMD_RESTART_RESPONSE: {
 		/*
 		 * The host has requested the device restart the last response.
 		 * This is used to recover from lost USB packets without
@@ -272,8 +270,7 @@ static void usb_spi_process_rx_packet(struct usb_spi_config const *config,
 		setup_transfer_response(config, config->state->status_code);
 		break;
 	}
-	case USB_SPI_PKT_ID_CMD_TRANSFER_START:
-	{
+	case USB_SPI_PKT_ID_CMD_TRANSFER_START: {
 		/* The host started a new USB SPI transfer */
 		size_t write_count = packet->cmd_start.write_count;
 		size_t read_count = packet->cmd_start.read_count;
@@ -282,42 +279,41 @@ static void usb_spi_process_rx_packet(struct usb_spi_config const *config,
 			setup_transfer_response(config, USB_SPI_DISABLED);
 		} else if (write_count > USB_SPI_MAX_WRITE_COUNT) {
 			setup_transfer_response(config,
-				USB_SPI_WRITE_COUNT_INVALID);
+						USB_SPI_WRITE_COUNT_INVALID);
 #ifdef CONFIG_SPI_HALFDUPLEX
 		} else if (read_count == USB_SPI_FULL_DUPLEX_ENABLED) {
 			/* Full duplex mode is not supported on this device. */
-			setup_transfer_response(config,
-				USB_SPI_UNSUPPORTED_FULL_DUPLEX);
+			setup_transfer_response(
+				config, USB_SPI_UNSUPPORTED_FULL_DUPLEX);
 #endif
 		} else if (read_count > USB_SPI_MAX_READ_COUNT &&
-				read_count != USB_SPI_FULL_DUPLEX_ENABLED) {
+			   read_count != USB_SPI_FULL_DUPLEX_ENABLED) {
 			setup_transfer_response(config,
-				USB_SPI_READ_COUNT_INVALID);
+						USB_SPI_READ_COUNT_INVALID);
 		} else {
-		        usb_spi_setup_transfer(config, write_count, read_count);
-		        packet->header_size =
-		        	offsetof(struct usb_spi_command_v2, data);
-		        config->state->status_code = usb_spi_read_usb_packet(
-		        	&config->state->spi_write_ctx, packet);
+			usb_spi_setup_transfer(config, write_count, read_count);
+			packet->header_size =
+				offsetof(struct usb_spi_command_v2, data);
+			config->state->status_code = usb_spi_read_usb_packet(
+				&config->state->spi_write_ctx, packet);
 		}
 
 		/* Send responses if we encountered an error. */
 		if (config->state->status_code != USB_SPI_SUCCESS) {
 			setup_transfer_response(config,
-				config->state->status_code);
+						config->state->status_code);
 			break;
 		}
 
 		/* Start the SPI transfer when we've read all data. */
 		if (config->state->spi_write_ctx.transfer_index ==
-				config->state->spi_write_ctx.transfer_size) {
+		    config->state->spi_write_ctx.transfer_size) {
 			config->state->mode = USB_SPI_MODE_START_SPI;
 		}
 
 		break;
 	}
-	case USB_SPI_PKT_ID_CMD_TRANSFER_CONTINUE:
-	{
+	case USB_SPI_PKT_ID_CMD_TRANSFER_CONTINUE: {
 		/*
 		 * The host has sent a continue packet for the SPI transfer
 		 * which contains additional data payload.
@@ -326,26 +322,25 @@ static void usb_spi_process_rx_packet(struct usb_spi_config const *config,
 			offsetof(struct usb_spi_continue_v2, data);
 		if (config->state->status_code == USB_SPI_SUCCESS) {
 			config->state->status_code = usb_spi_read_usb_packet(
-					&config->state->spi_write_ctx, packet);
+				&config->state->spi_write_ctx, packet);
 		}
 
 		/* Send responses if we encountered an error. */
 		if (config->state->status_code != USB_SPI_SUCCESS) {
 			setup_transfer_response(config,
-				config->state->status_code);
+						config->state->status_code);
 			break;
 		}
 
 		/* Start the SPI transfer when we've read all data. */
 		if (config->state->spi_write_ctx.transfer_index ==
-				config->state->spi_write_ctx.transfer_size) {
+		    config->state->spi_write_ctx.transfer_size) {
 			config->state->mode = USB_SPI_MODE_START_SPI;
 		}
 
 		break;
 	}
-	case USB_SPI_PKT_ID_CMD_CHIP_SELECT:
-	{
+	case USB_SPI_PKT_ID_CMD_CHIP_SELECT: {
 		/*
 		 * The host is requesting the chip select line be
 		 * asserted or deasserted.
@@ -362,8 +357,7 @@ static void usb_spi_process_rx_packet(struct usb_spi_config const *config,
 		config->state->mode = USB_SPI_MODE_SEND_CHIP_SELECT_RESPONSE;
 		break;
 	}
-	default:
-	{
+	default: {
 		/* An unknown USB packet was delivered. */
 		setup_transfer_response(config, USB_SPI_RX_UNEXPECTED_PACKET);
 		break;
@@ -396,8 +390,10 @@ void usb_spi_deferred(struct usb_spi_config const *config)
 	 * enable or disable routines and save our new state.
 	 */
 	if (enabled != config->state->enabled) {
-		if (enabled) usb_spi_board_enable(config);
-		else         usb_spi_board_disable(config);
+		if (enabled)
+			usb_spi_board_enable(config);
+		else
+			usb_spi_board_disable(config);
 
 		config->state->enabled = enabled;
 	}
@@ -439,11 +435,10 @@ void usb_spi_deferred(struct usb_spi_config const *config)
 			read_count = SPI_READBACK_ALL;
 		}
 #endif
-		status_code = spi_transaction(SPI_FLASH_DEVICE,
-			config->state->spi_write_ctx.buffer,
+		status_code = spi_transaction(
+			SPI_FLASH_DEVICE, config->state->spi_write_ctx.buffer,
 			config->state->spi_write_ctx.transfer_size,
-			config->state->spi_read_ctx.buffer,
-			read_count);
+			config->state->spi_read_ctx.buffer, read_count);
 
 		/* Cast the EC status code to USB SPI and start the response. */
 		status_code = usb_spi_map_error(status_code);
@@ -451,7 +446,7 @@ void usb_spi_deferred(struct usb_spi_config const *config)
 	}
 
 	if (usb_spi_response_in_progress(config) &&
-			usb_spi_transmitted_packet(config)) {
+	    usb_spi_transmitted_packet(config)) {
 		usb_spi_create_spi_transfer_response(config, transmit_packet);
 		usb_spi_write_packet(config, transmit_packet);
 	}
@@ -491,7 +486,8 @@ static void usb_spi_read_packet(struct usb_spi_config const *config,
 	/* Copy bytes from endpoint memory. */
 	packet_size = btable_ep[config->endpoint].rx_count & RX_COUNT_MASK;
 	memcpy_from_usbram(packet->bytes,
-		(void *)usb_sram_addr(config->ep_rx_ram), packet_size);
+			   (void *)usb_sram_addr(config->ep_rx_ram),
+			   packet_size);
 	packet->packet_size = packet_size;
 	/* Set endpoint as valid for accepting new packet. */
 	STM32_TOGGLE_EP(config->endpoint, EP_RX_MASK, EP_RX_VALID, 0);
@@ -505,14 +501,14 @@ static void usb_spi_read_packet(struct usb_spi_config const *config,
  * @param packet        Source packet we will write to the endpoint data.
  */
 static void usb_spi_write_packet(struct usb_spi_config const *config,
-				struct usb_spi_packet_ctx *packet)
+				 struct usb_spi_packet_ctx *packet)
 {
 	if (packet->packet_size == 0)
 		return;
 
 	/* Copy bytes to endpoint memory. */
 	memcpy_to_usbram((void *)usb_sram_addr(config->ep_tx_ram),
-		packet->bytes, packet->packet_size);
+			 packet->bytes, packet->packet_size);
 	btable_ep[config->endpoint].tx_count = packet->packet_size;
 
 	/* Mark the packet as having no data. */
@@ -597,17 +593,17 @@ void usb_spi_event(struct usb_spi_config const *config, enum usb_ep_event evt)
 
 	usb_spi_reset_interface(config);
 
-	btable_ep[endpoint].tx_addr  = usb_sram_addr(config->ep_tx_ram);
+	btable_ep[endpoint].tx_addr = usb_sram_addr(config->ep_tx_ram);
 	btable_ep[endpoint].tx_count = 0;
 
-	btable_ep[endpoint].rx_addr  = usb_sram_addr(config->ep_rx_ram);
-	btable_ep[endpoint].rx_count =
-		0x8000 | ((USB_MAX_PACKET_SIZE / 32 - 1) << 10);
+	btable_ep[endpoint].rx_addr = usb_sram_addr(config->ep_rx_ram);
+	btable_ep[endpoint].rx_count = 0x8000 |
+				       ((USB_MAX_PACKET_SIZE / 32 - 1) << 10);
 
-	STM32_USB_EP(endpoint) = ((endpoint <<  0) | /* Endpoint Addr*/
-				  (2        <<  4) | /* TX NAK */
-				  (0        <<  9) | /* Bulk EP */
-				  (3        << 12)); /* RX Valid */
+	STM32_USB_EP(endpoint) = ((endpoint << 0) | /* Endpoint Addr*/
+				  (2 << 4) | /* TX NAK */
+				  (0 << 9) | /* Bulk EP */
+				  (3 << 12)); /* RX Valid */
 }
 
 /*
@@ -617,21 +613,18 @@ void usb_spi_event(struct usb_spi_config const *config, enum usb_ep_event evt)
  * @param rx_buf        Contains setup packet
  * @param tx_buf        unused
  */
-int usb_spi_interface(struct usb_spi_config const *config,
-		      usb_uint *rx_buf,
+int usb_spi_interface(struct usb_spi_config const *config, usb_uint *rx_buf,
 		      usb_uint *tx_buf)
 {
 	struct usb_setup_packet setup;
 
 	usb_read_setup_packet(rx_buf, &setup);
 
-	if (setup.bmRequestType != (USB_DIR_OUT |
-				    USB_TYPE_VENDOR |
-				    USB_RECIP_INTERFACE))
+	if (setup.bmRequestType !=
+	    (USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_INTERFACE))
 		return 1;
 
-	if (setup.wValue  != 0 ||
-	    setup.wIndex  != config->interface ||
+	if (setup.wValue != 0 || setup.wIndex != config->interface ||
 	    setup.wLength != 0)
 		return 1;
 
@@ -644,7 +637,8 @@ int usb_spi_interface(struct usb_spi_config const *config,
 		config->state->enabled_host = 0;
 		break;
 
-	default: return 1;
+	default:
+		return 1;
 	}
 
 	/*
diff --git a/chip/stm32/usb_spi.h b/chip/stm32/usb_spi.h
index fa86ba3651..3ff582dd14 100644
--- a/chip/stm32/usb_spi.h
+++ b/chip/stm32/usb_spi.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -268,48 +268,48 @@
  *                      http://libusb.sourceforge.net/api-1.0/group__misc.html
  */
 
-#define USB_SPI_FULL_DUPLEX_ENABLED         (UINT16_MAX)
+#define USB_SPI_FULL_DUPLEX_ENABLED (UINT16_MAX)
 
-#define USB_SPI_PAYLOAD_SIZE_V2_START       (58)
+#define USB_SPI_PAYLOAD_SIZE_V2_START (58)
 
-#define USB_SPI_PAYLOAD_SIZE_V2_RESPONSE    (60)
+#define USB_SPI_PAYLOAD_SIZE_V2_RESPONSE (60)
 
-#define USB_SPI_PAYLOAD_SIZE_V2_CONTINUE    (60)
+#define USB_SPI_PAYLOAD_SIZE_V2_CONTINUE (60)
 
-#define USB_SPI_PAYLOAD_SIZE_V2_ERROR       (60)
+#define USB_SPI_PAYLOAD_SIZE_V2_ERROR (60)
 
-#define USB_SPI_MIN_PACKET_SIZE             (2)
+#define USB_SPI_MIN_PACKET_SIZE (2)
 
 enum packet_id_type {
 	/* Request USB SPI configuration data from device. */
 	USB_SPI_PKT_ID_CMD_GET_USB_SPI_CONFIG = 0,
 	/* USB SPI configuration data from device. */
-	USB_SPI_PKT_ID_RSP_USB_SPI_CONFIG     = 1,
+	USB_SPI_PKT_ID_RSP_USB_SPI_CONFIG = 1,
 	/*
 	 * Start a USB SPI transfer specifying number of bytes to write,
 	 * read and deliver first packet of data to write.
 	 */
-	USB_SPI_PKT_ID_CMD_TRANSFER_START     = 2,
+	USB_SPI_PKT_ID_CMD_TRANSFER_START = 2,
 	/* Additional packets containing write payload. */
-	USB_SPI_PKT_ID_CMD_TRANSFER_CONTINUE  = 3,
+	USB_SPI_PKT_ID_CMD_TRANSFER_CONTINUE = 3,
 	/*
 	 * Request the device restart the response enabling us to recover
 	 * from packet loss without another SPI transfer.
 	 */
-	USB_SPI_PKT_ID_CMD_RESTART_RESPONSE   = 4,
+	USB_SPI_PKT_ID_CMD_RESTART_RESPONSE = 4,
 	/*
 	 * First packet of USB SPI response with the status code
 	 * and read payload if it was successful.
 	 */
-	USB_SPI_PKT_ID_RSP_TRANSFER_START     = 5,
+	USB_SPI_PKT_ID_RSP_TRANSFER_START = 5,
 	/* Additional packets containing read payload. */
-	USB_SPI_PKT_ID_RSP_TRANSFER_CONTINUE  = 6,
+	USB_SPI_PKT_ID_RSP_TRANSFER_CONTINUE = 6,
 	/*
 	 * Request assertion or deassertion of chip select
 	 */
-	USB_SPI_PKT_ID_CMD_CHIP_SELECT        = 7,
+	USB_SPI_PKT_ID_CMD_CHIP_SELECT = 7,
 	/* Response to above request. */
-	USB_SPI_PKT_ID_RSP_CHIP_SELECT        = 8,
+	USB_SPI_PKT_ID_RSP_CHIP_SELECT = 8,
 };
 
 enum feature_bitmap {
@@ -383,25 +383,25 @@ struct usb_spi_packet_ctx {
 };
 
 enum usb_spi_error {
-	USB_SPI_SUCCESS                 = 0x0000,
-	USB_SPI_TIMEOUT                 = 0x0001,
-	USB_SPI_BUSY                    = 0x0002,
-	USB_SPI_WRITE_COUNT_INVALID     = 0x0003,
-	USB_SPI_READ_COUNT_INVALID      = 0x0004,
-	USB_SPI_DISABLED                = 0x0005,
+	USB_SPI_SUCCESS = 0x0000,
+	USB_SPI_TIMEOUT = 0x0001,
+	USB_SPI_BUSY = 0x0002,
+	USB_SPI_WRITE_COUNT_INVALID = 0x0003,
+	USB_SPI_READ_COUNT_INVALID = 0x0004,
+	USB_SPI_DISABLED = 0x0005,
 	/* The RX continue packet's data index is invalid. */
-	USB_SPI_RX_BAD_DATA_INDEX       = 0x0006,
+	USB_SPI_RX_BAD_DATA_INDEX = 0x0006,
 	/* The RX endpoint has received more data than write count. */
-	USB_SPI_RX_DATA_OVERFLOW        = 0x0007,
+	USB_SPI_RX_DATA_OVERFLOW = 0x0007,
 	/* An unexpected packet arrived on the device. */
-	USB_SPI_RX_UNEXPECTED_PACKET    = 0x0008,
+	USB_SPI_RX_UNEXPECTED_PACKET = 0x0008,
 	/* The device does not support full duplex mode. */
 	USB_SPI_UNSUPPORTED_FULL_DUPLEX = 0x0009,
-	USB_SPI_UNKNOWN_ERROR           = 0x8000,
+	USB_SPI_UNKNOWN_ERROR = 0x8000,
 };
 
 enum usb_spi_request {
-	USB_SPI_REQ_ENABLE  = 0x0000,
+	USB_SPI_REQ_ENABLE = 0x0000,
 	USB_SPI_REQ_DISABLE = 0x0001,
 };
 
@@ -416,11 +416,11 @@ enum usb_spi_request {
 #ifdef CONFIG_USB_SPI_BUFFER_SIZE
 #define USB_SPI_BUFFER_SIZE CONFIG_USB_SPI_BUFFER_SIZE
 #else
-#define USB_SPI_BUFFER_SIZE	(USB_SPI_PAYLOAD_SIZE_V2_START + \
-				(4 * USB_SPI_PAYLOAD_SIZE_V2_CONTINUE))
+#define USB_SPI_BUFFER_SIZE \
+	(USB_SPI_PAYLOAD_SIZE_V2_START + (4 * USB_SPI_PAYLOAD_SIZE_V2_CONTINUE))
 #endif
-#define USB_SPI_MAX_WRITE_COUNT	USB_SPI_BUFFER_SIZE
-#define USB_SPI_MAX_READ_COUNT	USB_SPI_BUFFER_SIZE
+#define USB_SPI_MAX_WRITE_COUNT USB_SPI_BUFFER_SIZE
+#define USB_SPI_MAX_READ_COUNT USB_SPI_BUFFER_SIZE
 
 /* Protocol uses two-byte length fields.  Larger buffer makes no sense. */
 BUILD_ASSERT(USB_SPI_BUFFER_SIZE <= 65536);
@@ -541,78 +541,82 @@ struct usb_spi_config {
  * FLAGS encodes different run-time control parameters. See
  * USB_SPI_CONFIG_FLAGS_* for definitions.
  */
-#define USB_SPI_CONFIG(NAME,						\
-		       INTERFACE,					\
-		       ENDPOINT,					\
-		       FLAGS)						\
-	static uint16_t CONCAT2(NAME, _buffer_)[(USB_SPI_BUFFER_SIZE + 1) / 2];\
-	static usb_uint CONCAT2(NAME, _ep_rx_buffer_)[USB_MAX_PACKET_SIZE / 2] __usb_ram; \
-	static usb_uint CONCAT2(NAME, _ep_tx_buffer_)[USB_MAX_PACKET_SIZE / 2] __usb_ram; \
-	static void CONCAT2(NAME, _deferred_)(void);			\
-	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_));			\
-	struct usb_spi_state CONCAT2(NAME, _state_) = {			\
-		.enabled_host   = 0,					\
-		.enabled_device = 0,					\
-		.enabled        = 0,					\
+#define USB_SPI_CONFIG(NAME, INTERFACE, ENDPOINT, FLAGS)                    \
+	static uint16_t CONCAT2(NAME,                                       \
+				_buffer_)[(USB_SPI_BUFFER_SIZE + 1) / 2];   \
+	static usb_uint CONCAT2(                                            \
+		NAME, _ep_rx_buffer_)[USB_MAX_PACKET_SIZE / 2] __usb_ram;   \
+	static usb_uint CONCAT2(                                            \
+		NAME, _ep_tx_buffer_)[USB_MAX_PACKET_SIZE / 2] __usb_ram;   \
+	static void CONCAT2(NAME, _deferred_)(void);                        \
+	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_));                        \
+	struct usb_spi_state CONCAT2(NAME, _state_) = {                     \
+		.enabled_host = 0,                                          \
+		.enabled_device = 0,                                        \
+		.enabled = 0,                                               \
 		.spi_write_ctx.buffer = (uint8_t *)CONCAT2(NAME, _buffer_), \
-		.spi_read_ctx.buffer = (uint8_t *)CONCAT2(NAME, _buffer_), \
-	};								\
-	struct usb_spi_config const NAME = {				\
-		.state     = &CONCAT2(NAME, _state_),			\
-		.interface = INTERFACE,					\
-		.endpoint  = ENDPOINT,					\
-		.deferred  = &CONCAT2(NAME, _deferred__data),		\
-		.ep_rx_ram = CONCAT2(NAME, _ep_rx_buffer_),		\
-		.ep_tx_ram = CONCAT2(NAME, _ep_tx_buffer_),		\
-		.flags     = FLAGS,		\
-	};								\
-	const struct usb_interface_descriptor				\
-	USB_IFACE_DESC(INTERFACE) = {					\
-		.bLength            = USB_DT_INTERFACE_SIZE,		\
-		.bDescriptorType    = USB_DT_INTERFACE,			\
-		.bInterfaceNumber   = INTERFACE,			\
-		.bAlternateSetting  = 0,				\
-		.bNumEndpoints      = 2,				\
-		.bInterfaceClass    = USB_CLASS_VENDOR_SPEC,		\
-		.bInterfaceSubClass = USB_SUBCLASS_GOOGLE_SPI,		\
-		.bInterfaceProtocol = USB_PROTOCOL_GOOGLE_SPI,		\
-		.iInterface         = USB_STR_SPI_NAME,			\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 0) = {					\
-		.bLength          = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = 0x80 | ENDPOINT,			\
-		.bmAttributes     = 0x02 /* Bulk IN */,			\
-		.wMaxPacketSize   = USB_MAX_PACKET_SIZE,		\
-		.bInterval        = 10,					\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 1) = {					\
-		.bLength          = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = ENDPOINT,				\
-		.bmAttributes     = 0x02 /* Bulk OUT */,		\
-		.wMaxPacketSize   = USB_MAX_PACKET_SIZE,		\
-		.bInterval        = 0,					\
-	};								\
-	static void CONCAT2(NAME, _ep_tx_)   (void) { usb_spi_tx   (&NAME); } \
-	static void CONCAT2(NAME, _ep_rx_)   (void) { usb_spi_rx   (&NAME); } \
-	static void CONCAT2(NAME, _ep_event_)(enum usb_ep_event evt)	\
-	{								\
-		usb_spi_event(&NAME, evt);				\
-	}								\
-	USB_DECLARE_EP(ENDPOINT,					\
-		       CONCAT2(NAME, _ep_tx_),				\
-		       CONCAT2(NAME, _ep_rx_),				\
-		       CONCAT2(NAME, _ep_event_));			\
-	static int CONCAT2(NAME, _interface_)(usb_uint *rx_buf,		\
-					      usb_uint *tx_buf)		\
-	{ return usb_spi_interface(&NAME, rx_buf, tx_buf); }		\
-	USB_DECLARE_IFACE(INTERFACE,					\
-			  CONCAT2(NAME, _interface_));			\
-	static void CONCAT2(NAME, _deferred_)(void)			\
-	{ usb_spi_deferred(&NAME); }
+		.spi_read_ctx.buffer = (uint8_t *)CONCAT2(NAME, _buffer_),  \
+	};                                                                  \
+	struct usb_spi_config const NAME = {                                \
+		.state = &CONCAT2(NAME, _state_),                           \
+		.interface = INTERFACE,                                     \
+		.endpoint = ENDPOINT,                                       \
+		.deferred = &CONCAT2(NAME, _deferred__data),                \
+		.ep_rx_ram = CONCAT2(NAME, _ep_rx_buffer_),                 \
+		.ep_tx_ram = CONCAT2(NAME, _ep_tx_buffer_),                 \
+		.flags = FLAGS,                                             \
+	};                                                                  \
+	const struct usb_interface_descriptor USB_IFACE_DESC(INTERFACE) = { \
+		.bLength = USB_DT_INTERFACE_SIZE,                           \
+		.bDescriptorType = USB_DT_INTERFACE,                        \
+		.bInterfaceNumber = INTERFACE,                              \
+		.bAlternateSetting = 0,                                     \
+		.bNumEndpoints = 2,                                         \
+		.bInterfaceClass = USB_CLASS_VENDOR_SPEC,                   \
+		.bInterfaceSubClass = USB_SUBCLASS_GOOGLE_SPI,              \
+		.bInterfaceProtocol = USB_PROTOCOL_GOOGLE_SPI,              \
+		.iInterface = USB_STR_SPI_NAME,                             \
+	};                                                                  \
+	const struct usb_endpoint_descriptor USB_EP_DESC(INTERFACE, 0) = {  \
+		.bLength = USB_DT_ENDPOINT_SIZE,                            \
+		.bDescriptorType = USB_DT_ENDPOINT,                         \
+		.bEndpointAddress = 0x80 | ENDPOINT,                        \
+		.bmAttributes = 0x02 /* Bulk IN */,                         \
+		.wMaxPacketSize = USB_MAX_PACKET_SIZE,                      \
+		.bInterval = 10,                                            \
+	};                                                                  \
+	const struct usb_endpoint_descriptor USB_EP_DESC(INTERFACE, 1) = {  \
+		.bLength = USB_DT_ENDPOINT_SIZE,                            \
+		.bDescriptorType = USB_DT_ENDPOINT,                         \
+		.bEndpointAddress = ENDPOINT,                               \
+		.bmAttributes = 0x02 /* Bulk OUT */,                        \
+		.wMaxPacketSize = USB_MAX_PACKET_SIZE,                      \
+		.bInterval = 0,                                             \
+	};                                                                  \
+	static void CONCAT2(NAME, _ep_tx_)(void)                            \
+	{                                                                   \
+		usb_spi_tx(&NAME);                                          \
+	}                                                                   \
+	static void CONCAT2(NAME, _ep_rx_)(void)                            \
+	{                                                                   \
+		usb_spi_rx(&NAME);                                          \
+	}                                                                   \
+	static void CONCAT2(NAME, _ep_event_)(enum usb_ep_event evt)        \
+	{                                                                   \
+		usb_spi_event(&NAME, evt);                                  \
+	}                                                                   \
+	USB_DECLARE_EP(ENDPOINT, CONCAT2(NAME, _ep_tx_),                    \
+		       CONCAT2(NAME, _ep_rx_), CONCAT2(NAME, _ep_event_));  \
+	static int CONCAT2(NAME, _interface_)(usb_uint * rx_buf,            \
+					      usb_uint * tx_buf)            \
+	{                                                                   \
+		return usb_spi_interface(&NAME, rx_buf, tx_buf);            \
+	}                                                                   \
+	USB_DECLARE_IFACE(INTERFACE, CONCAT2(NAME, _interface_));           \
+	static void CONCAT2(NAME, _deferred_)(void)                         \
+	{                                                                   \
+		usb_spi_deferred(&NAME);                                    \
+	}
 
 /*
  * Handle SPI request in a deferred callback.
@@ -636,9 +640,8 @@ void usb_spi_enable(struct usb_spi_config const *config, int enabled);
 void usb_spi_tx(struct usb_spi_config const *config);
 void usb_spi_rx(struct usb_spi_config const *config);
 void usb_spi_event(struct usb_spi_config const *config, enum usb_ep_event evt);
-int  usb_spi_interface(struct usb_spi_config const *config,
-		       usb_uint *rx_buf,
-		       usb_uint *tx_buf);
+int usb_spi_interface(struct usb_spi_config const *config, usb_uint *rx_buf,
+		      usb_uint *tx_buf);
 
 /*
  * These functions should be implemented by the board to provide any board
diff --git a/chip/stm32/watchdog.c b/chip/stm32/watchdog.c
index 40dfc72059..1a54d6f52d 100644
--- a/chip/stm32/watchdog.c
+++ b/chip/stm32/watchdog.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -67,8 +67,9 @@ int watchdog_init(void)
 	STM32_IWDG_PR = IWDG_PRESCALER & 7;
 
 	/* Set the reload value of the watchdog counter */
-	STM32_IWDG_RLR = MIN(STM32_IWDG_RLR_MAX, CONFIG_WATCHDOG_PERIOD_MS *
-			     (LSI_CLOCK / IWDG_PRESCALER_DIV) / 1000);
+	STM32_IWDG_RLR = MIN(STM32_IWDG_RLR_MAX,
+			     CONFIG_WATCHDOG_PERIOD_MS *
+				     (LSI_CLOCK / IWDG_PRESCALER_DIV) / 1000);
 #ifdef CHIP_FAMILY_STM32L4
 	tickstart = get_time();
 	/* Wait for SR */
diff --git a/common/accel_cal.c b/common/accel_cal.c
index 533a14fbc4..0fe9fe7656 100644
--- a/common/accel_cal.c
+++ b/common/accel_cal.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,17 +23,17 @@ void accel_cal_reset(struct accel_cal *cal)
 
 static inline int compute_temp_gate(const struct accel_cal *cal, fp_t temp)
 {
-	int gate = (int) fp_div(fp_mul(temp - CONFIG_ACCEL_CAL_MIN_TEMP,
-				       INT_TO_FP(cal->num_temp_windows)),
-				TEMP_RANGE);
+	int gate = (int)fp_div(fp_mul(temp - CONFIG_ACCEL_CAL_MIN_TEMP,
+				      INT_TO_FP(cal->num_temp_windows)),
+			       TEMP_RANGE);
 
-	return gate < cal->num_temp_windows
-		? gate : (cal->num_temp_windows - 1);
+	return gate < cal->num_temp_windows ? gate :
+					      (cal->num_temp_windows - 1);
 }
 
-test_mockable bool accel_cal_accumulate(
-	struct accel_cal *cal, uint32_t timestamp, fp_t x, fp_t y, fp_t z,
-	fp_t temp)
+test_mockable bool accel_cal_accumulate(struct accel_cal *cal,
+					uint32_t timestamp, fp_t x, fp_t y,
+					fp_t z, fp_t temp)
 {
 	struct accel_cal_algo *algo;
 
diff --git a/common/acpi.c b/common/acpi.c
index c234347019..86217ab1ba 100644
--- a/common/acpi.c
+++ b/common/acpi.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,6 +15,7 @@
 #include "host_command.h"
 #include "keyboard_backlight.h"
 #include "lpc.h"
+#include "printf.h"
 #include "pwm.h"
 #include "timer.h"
 #include "tablet_mode.h"
@@ -24,8 +25,8 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_LPC, outstr)
-#define CPRINTF(format, args...) cprintf(CC_LPC, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_LPC, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args)
 
 /* Last received ACPI command */
 static uint8_t acpi_cmd;
@@ -37,8 +38,8 @@ static int acpi_data_count;
 static uint8_t acpi_mem_test;
 
 #ifdef CONFIG_DPTF
-static int dptf_temp_sensor_id;	/* last sensor ID written */
-static int dptf_temp_threshold;	/* last threshold written */
+static int dptf_temp_sensor_id; /* last sensor ID written */
+static int dptf_temp_threshold; /* last threshold written */
 
 /*
  * Current DPTF profile number.
@@ -62,9 +63,9 @@ static int current_dptf_profile = DPTF_PROFILE_DEFAULT;
 #define ACPI_READ_CACHE_FLUSHED (EC_ACPI_MEM_MAPPED_BEGIN - 1)
 
 /* Calculate size of valid cache based upon end of memmap data. */
-#define ACPI_VALID_CACHE_SIZE(addr) (MIN( \
-	EC_ACPI_MEM_MAPPED_SIZE + EC_ACPI_MEM_MAPPED_BEGIN - (addr), \
-	ACPI_READ_CACHE_SIZE))
+#define ACPI_VALID_CACHE_SIZE(addr)                                       \
+	(MIN(EC_ACPI_MEM_MAPPED_SIZE + EC_ACPI_MEM_MAPPED_BEGIN - (addr), \
+	     ACPI_READ_CACHE_SIZE))
 
 /*
  * In burst mode, read the requested memmap data and the data immediately
@@ -140,24 +141,20 @@ static int acpi_read(uint8_t addr)
 	/* Check for out-of-range read. */
 	if (addr < EC_ACPI_MEM_MAPPED_BEGIN ||
 	    addr >= EC_ACPI_MEM_MAPPED_BEGIN + EC_ACPI_MEM_MAPPED_SIZE) {
-		CPRINTS("ACPI read 0x%02x (ignored)",
-			acpi_addr);
+		CPRINTS("ACPI read 0x%02x (ignored)", acpi_addr);
 		return 0xff;
 	}
 #ifdef __clang__
 #pragma clang diagnostic pop
 #endif /* __clang__ */
 
-
 	/* Read from cache if enabled (burst mode). */
 	if (acpi_read_cache.enabled) {
 		/* Fetch to cache on miss. */
 		if (acpi_read_cache.start_addr == ACPI_READ_CACHE_FLUSHED ||
 		    acpi_read_cache.start_addr > addr ||
-		    addr - acpi_read_cache.start_addr >=
-		    ACPI_READ_CACHE_SIZE) {
-			memcpy(acpi_read_cache.data,
-			       memmap_addr,
+		    addr - acpi_read_cache.start_addr >= ACPI_READ_CACHE_SIZE) {
+			memcpy(acpi_read_cache.data, memmap_addr,
 			       ACPI_VALID_CACHE_SIZE(addr));
 			acpi_read_cache.start_addr = addr;
 		}
@@ -177,7 +174,7 @@ int acpi_ap_to_ec(int is_cmd, uint8_t value, uint8_t *resultptr)
 {
 	int data = 0;
 	int retval = 0;
-	int result = 0xff;			/* value for bogus read */
+	int result = 0xff; /* value for bogus read */
 
 	/* Read command/data; this clears the FRMH status bit. */
 	if (is_cmd) {
@@ -241,7 +238,7 @@ int acpi_ap_to_ec(int is_cmd, uint8_t value, uint8_t *resultptr)
 #ifdef CONFIG_DPTF
 			result |= (acpi_dptf_get_profile_num() &
 				   EC_ACPI_MEM_DDPN_MASK)
-				<< EC_ACPI_MEM_DDPN_SHIFT;
+				  << EC_ACPI_MEM_DDPN_SHIFT;
 #endif
 			break;
 
@@ -260,7 +257,7 @@ int acpi_ap_to_ec(int is_cmd, uint8_t value, uint8_t *resultptr)
 
 			result = val >> (8 * off);
 			break;
-			}
+		}
 		case EC_ACPI_MEM_DEVICE_FEATURES4:
 		case EC_ACPI_MEM_DEVICE_FEATURES5:
 		case EC_ACPI_MEM_DEVICE_FEATURES6:
@@ -270,7 +267,7 @@ int acpi_ap_to_ec(int is_cmd, uint8_t value, uint8_t *resultptr)
 
 			result = val >> (8 * off);
 			break;
-			}
+		}
 
 #ifdef CONFIG_USB_PORT_POWER_DUMB
 		case EC_ACPI_MEM_USB_PORT_POWER: {
@@ -289,7 +286,7 @@ int acpi_ap_to_ec(int is_cmd, uint8_t value, uint8_t *resultptr)
 					result |= 1 << i;
 			}
 			break;
-			}
+		}
 #endif
 #ifdef CONFIG_USBC_RETIMER_FW_UPDATE
 		case EC_ACPI_MEM_USB_RETIMER_FW_UPDATE:
@@ -318,17 +315,19 @@ int acpi_ap_to_ec(int is_cmd, uint8_t value, uint8_t *resultptr)
 			break;
 #endif
 #ifdef CONFIG_KEYBOARD_BACKLIGHT
-		case EC_ACPI_MEM_KEYBOARD_BACKLIGHT:
+		case EC_ACPI_MEM_KEYBOARD_BACKLIGHT: {
+			char ts_str[PRINTF_TIMESTAMP_BUF_SIZE];
 			/*
 			 * Debug output with CR not newline, because the host
 			 * does a lot of keyboard backlights and it scrolls the
 			 * debug console.
 			 */
-			CPRINTF("\r[%pT ACPI kblight %d]",
-				PRINTF_TIMESTAMP_NOW, data);
+			snprintf_timestamp_now(ts_str, sizeof(ts_str));
+			CPRINTF("\r[%s ACPI kblight %d]", ts_str, data);
 			kblight_set(data);
 			kblight_enable(data > 0);
 			break;
+		}
 #endif
 #ifdef CONFIG_FANS
 		case EC_ACPI_MEM_FAN_DUTY:
@@ -342,13 +341,12 @@ int acpi_ap_to_ec(int is_cmd, uint8_t value, uint8_t *resultptr)
 		case EC_ACPI_MEM_TEMP_THRESHOLD:
 			dptf_temp_threshold = data + EC_TEMP_SENSOR_OFFSET;
 			break;
-		case EC_ACPI_MEM_TEMP_COMMIT:
-		{
+		case EC_ACPI_MEM_TEMP_COMMIT: {
 			int idx = data & EC_ACPI_MEM_TEMP_COMMIT_SELECT_MASK;
 			int enable = data & EC_ACPI_MEM_TEMP_COMMIT_ENABLE_MASK;
 			dptf_set_temp_threshold(dptf_temp_sensor_id,
-						dptf_temp_threshold,
-						idx, enable);
+						dptf_temp_threshold, idx,
+						enable);
 			break;
 		}
 #endif
@@ -380,8 +378,9 @@ int acpi_ap_to_ec(int is_cmd, uint8_t value, uint8_t *resultptr)
 				if (mode_field & 1)
 					mode = USB_CHARGE_MODE_ENABLED;
 
-				if (usb_charge_set_mode(i, mode,
-				    USB_ALLOW_SUSPEND_CHARGE)) {
+				if (usb_charge_set_mode(
+					    i, mode,
+					    USB_ALLOW_SUSPEND_CHARGE)) {
 					CPRINTS("ERROR: could not set charge "
 						"mode of USB port p%d to %d",
 						i, mode);
@@ -389,7 +388,7 @@ int acpi_ap_to_ec(int is_cmd, uint8_t value, uint8_t *resultptr)
 				mode_field >>= 1;
 			}
 			break;
-			}
+		}
 #endif
 #ifdef CONFIG_USBC_RETIMER_FW_UPDATE
 		case EC_ACPI_MEM_USB_RETIMER_FW_UPDATE:
@@ -427,7 +426,8 @@ int acpi_ap_to_ec(int is_cmd, uint8_t value, uint8_t *resultptr)
 		 * Disable from deferred function in case burst mode is enabled
 		 * for an extremely long time  (ex. kernel bug / crash).
 		 */
-		hook_call_deferred(&acpi_disable_burst_deferred_data, 1*SECOND);
+		hook_call_deferred(&acpi_disable_burst_deferred_data,
+				   1 * SECOND);
 
 		/* ACPI 5.0-12.3.3: Burst ACK */
 		*resultptr = 0x90;
diff --git a/common/adc.c b/common/adc.c
index c9e3a36e57..89e0b1f645 100644
--- a/common/adc.c
+++ b/common/adc.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -41,7 +41,7 @@ static int print_one_adc(int channel)
 	return EC_SUCCESS;
 }
 
-static int command_adc(int argc, char **argv)
+static int command_adc(int argc, const char **argv)
 {
 	int i, ret;
 
@@ -61,9 +61,7 @@ static int command_adc(int argc, char **argv)
 		return EC_SUCCESS;
 	}
 }
-DECLARE_CONSOLE_COMMAND(adc, command_adc,
-			"[name]",
-			"Print ADC channel(s)");
+DECLARE_CONSOLE_COMMAND(adc, command_adc, "[name]", "Print ADC channel(s)");
 
 static enum ec_status hc_adc_read(struct host_cmd_handler_args *args)
 {
diff --git a/common/als.c b/common/als.c
index 2e9c7ba96c..832ed382f3 100644
--- a/common/als.c
+++ b/common/als.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,9 +19,8 @@
 #include "util.h"
 
 #define CPUTS(outstr) cputs(CC_ALS, outstr)
-#define CPRINTS(format, args...) cprints(CC_ALS, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_ALS, format, ## args)
-
+#define CPRINTS(format, args...) cprints(CC_ALS, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_ALS, format, ##args)
 
 #define ALS_POLL_PERIOD SECOND
 
@@ -90,8 +89,7 @@ static void als_task_init(void)
 	 * Enable ALS task in S0 only and may need to re-enable
 	 * when sysjumped.
 	 */
-	if (system_jumped_late() &&
-		chipset_in_state(CHIPSET_STATE_ON))
+	if (system_jumped_late() && chipset_in_state(CHIPSET_STATE_ON))
 		als_task_enable();
 }
 
@@ -103,7 +101,7 @@ DECLARE_HOOK(HOOK_INIT, als_task_init, HOOK_PRIO_ALS_INIT);
 /* Console commands */
 
 #ifdef CONFIG_CMD_ALS
-static int command_als(int argc, char **argv)
+static int command_als(int argc, const char **argv)
 {
 	int i, rv, val;
 
@@ -121,7 +119,5 @@ static int command_als(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(als, command_als,
-			NULL,
-			"Print ALS values");
+DECLARE_CONSOLE_COMMAND(als, command_als, NULL, "Print ALS values");
 #endif
diff --git a/common/ap_hang_detect.c b/common/ap_hang_detect.c
index 0c9e7a186d..6e3d7177a7 100644
--- a/common/ap_hang_detect.c
+++ b/common/ap_hang_detect.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,12 +18,12 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 static struct ec_params_hang_detect hdparams;
 
-static int active;  /* Is hang detect timer active / counting? */
-static int timeout_will_reboot;  /* Will the deferred call reboot the AP? */
+static int active; /* Is hang detect timer active / counting? */
+static int timeout_will_reboot; /* Will the deferred call reboot the AP? */
 
 /**
  * Handle the hang detect timer expiring.
@@ -56,7 +56,8 @@ static void hang_detect_deferred(void)
 		timeout_will_reboot = 1;
 		hook_call_deferred(&hang_detect_deferred_data,
 				   (hdparams.warm_reboot_timeout_msec -
-				    hdparams.host_event_timeout_msec) * MSEC);
+				    hdparams.host_event_timeout_msec) *
+					   MSEC);
 	} else {
 		/* Not rebooting, so go back to idle */
 		active = 0;
@@ -196,19 +197,18 @@ hang_detect_host_command(struct host_cmd_handler_args *args)
 	 */
 	if (hdparams.warm_reboot_timeout_msec &&
 	    hdparams.warm_reboot_timeout_msec <=
-	    hdparams.host_event_timeout_msec)
+		    hdparams.host_event_timeout_msec)
 		hdparams.host_event_timeout_msec = 0;
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_HANG_DETECT,
-		     hang_detect_host_command,
+DECLARE_HOST_COMMAND(EC_CMD_HANG_DETECT, hang_detect_host_command,
 		     EC_VER_MASK(0));
 
 /*****************************************************************************/
 /* Console command */
 
-static int command_hang_detect(int argc, char **argv)
+static int command_hang_detect(int argc, const char **argv)
 {
 	ccprintf("flags:  0x%x\n", hdparams.flags);
 
@@ -233,6 +233,5 @@ static int command_hang_detect(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(hangdet, command_hang_detect,
-			NULL,
+DECLARE_CONSOLE_COMMAND(hangdet, command_hang_detect, NULL,
 			"Print hang detect state");
diff --git a/common/audio_codec.c b/common/audio_codec.c
index 3f7203ad15..aba1453ce3 100644
--- a/common/audio_codec.c
+++ b/common/audio_codec.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,15 +9,14 @@
 #include "host_command.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ##args)
 
-static const uint32_t capabilities =
-	0
+static const uint32_t capabilities = 0
 #ifdef CONFIG_AUDIO_CODEC_CAP_WOV_AUDIO_SHM
-	| BIT(EC_CODEC_CAP_WOV_AUDIO_SHM)
+				     | BIT(EC_CODEC_CAP_WOV_AUDIO_SHM)
 #endif
 #ifdef CONFIG_AUDIO_CODEC_CAP_WOV_LANG_SHM
-	| BIT(EC_CODEC_CAP_WOV_LANG_SHM)
+				     | BIT(EC_CODEC_CAP_WOV_LANG_SHM)
 #endif
 	;
 
@@ -122,8 +121,8 @@ int audio_codec_capable(uint8_t cap)
 	return capabilities & BIT(cap);
 }
 
-int audio_codec_register_shm(uint8_t shm_id, uint8_t cap,
-		uintptr_t *addr, uint32_t len, uint8_t type)
+int audio_codec_register_shm(uint8_t shm_id, uint8_t cap, uintptr_t *addr,
+			     uint32_t len, uint8_t type)
 {
 	if (shm_id >= EC_CODEC_SHM_ID_LAST)
 		return EC_ERROR_INVAL;
@@ -140,8 +139,8 @@ int audio_codec_register_shm(uint8_t shm_id, uint8_t cap,
 	return EC_SUCCESS;
 }
 
-__attribute__((weak))
-int audio_codec_memmap_ap_to_ec(uintptr_t ap_addr, uintptr_t *ec_addr)
+__attribute__((weak)) int audio_codec_memmap_ap_to_ec(uintptr_t ap_addr,
+						      uintptr_t *ec_addr)
 {
 	return EC_ERROR_UNIMPLEMENTED;
 }
diff --git a/common/audio_codec_dmic.c b/common/audio_codec_dmic.c
index c4f0b07a46..d85245791d 100644
--- a/common/audio_codec_dmic.c
+++ b/common/audio_codec_dmic.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,7 +8,7 @@
 #include "console.h"
 #include "host_command.h"
 
-#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ##args)
 
 static enum ec_status dmic_get_max_gain(struct host_cmd_handler_args *args)
 {
@@ -25,9 +25,9 @@ static enum ec_status dmic_set_gain_idx(struct host_cmd_handler_args *args)
 {
 	const struct ec_param_ec_codec_dmic *p = args->params;
 
-	if (audio_codec_dmic_set_gain_idx(
-			p->set_gain_idx_param.channel,
-			p->set_gain_idx_param.gain) != EC_SUCCESS)
+	if (audio_codec_dmic_set_gain_idx(p->set_gain_idx_param.channel,
+					  p->set_gain_idx_param.gain) !=
+	    EC_SUCCESS)
 		return EC_RES_ERROR;
 
 	return EC_RES_SUCCESS;
@@ -38,8 +38,8 @@ static enum ec_status dmic_get_gain_idx(struct host_cmd_handler_args *args)
 	const struct ec_param_ec_codec_dmic *p = args->params;
 	struct ec_response_ec_codec_dmic_get_gain_idx *r = args->response;
 
-	if (audio_codec_dmic_get_gain_idx(
-			p->get_gain_idx_param.channel, &r->gain) != EC_SUCCESS)
+	if (audio_codec_dmic_get_gain_idx(p->get_gain_idx_param.channel,
+					  &r->gain) != EC_SUCCESS)
 		return EC_RES_ERROR;
 
 	args->response_size = sizeof(*r);
diff --git a/common/audio_codec_i2s_rx.c b/common/audio_codec_i2s_rx.c
index aeae19bdca..ac6aa8ecce 100644
--- a/common/audio_codec_i2s_rx.c
+++ b/common/audio_codec_i2s_rx.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,7 +8,7 @@
 #include "console.h"
 #include "host_command.h"
 
-#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ##args)
 
 static uint8_t i2s_rx_enabled;
 
@@ -128,5 +128,5 @@ static enum ec_status i2s_rx_host_command(struct host_cmd_handler_args *args)
 
 	return EC_RES_INVALID_PARAM;
 }
-DECLARE_HOST_COMMAND(EC_CMD_EC_CODEC_I2S_RX,
-	i2s_rx_host_command, EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_EC_CODEC_I2S_RX, i2s_rx_host_command,
+		     EC_VER_MASK(0));
diff --git a/common/audio_codec_wov.c b/common/audio_codec_wov.c
index f84e45f342..7c7b43acae 100644
--- a/common/audio_codec_wov.c
+++ b/common/audio_codec_wov.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,7 +13,7 @@
 #include "task.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ##args)
 
 /*
  * To shorten the variable names, or the following code is likely to greater
@@ -99,7 +99,7 @@ static enum ec_status wov_set_lang_shm(struct host_cmd_handler_args *args)
 {
 	const struct ec_param_ec_codec_wov *p = args->params;
 	const struct ec_param_ec_codec_wov_set_lang_shm *pp =
-			&p->set_lang_shm_param;
+		&p->set_lang_shm_param;
 
 	if (pp->total_len > LANG_BUF_LEN)
 		return EC_RES_INVALID_PARAM;
@@ -135,11 +135,11 @@ static enum ec_status wov_set_lang(struct host_cmd_handler_args *args)
 		return EC_RES_BUSY;
 
 	if (!pp->offset)
-		memset((uint8_t *)audio_codec_wov_lang_buf_addr,
-		       0, LANG_BUF_LEN);
+		memset((uint8_t *)audio_codec_wov_lang_buf_addr, 0,
+		       LANG_BUF_LEN);
 
-	memcpy((uint8_t *)audio_codec_wov_lang_buf_addr + pp->offset,
-		pp->buf, pp->len);
+	memcpy((uint8_t *)audio_codec_wov_lang_buf_addr + pp->offset, pp->buf,
+	       pp->len);
 
 	if (pp->offset + pp->len == pp->total_len) {
 		if (check_lang_buf((uint8_t *)audio_codec_wov_lang_buf_addr,
@@ -176,7 +176,7 @@ static enum ec_status wov_enable(struct host_cmd_handler_args *args)
 
 	if (!speech_lib_loaded) {
 		if (!GoogleHotwordDspInit(
-				(void *)audio_codec_wov_lang_buf_addr))
+			    (void *)audio_codec_wov_lang_buf_addr))
 			return EC_RES_ERROR;
 		speech_lib_loaded = 1;
 	} else {
@@ -359,7 +359,6 @@ void audio_codec_wov_task(void *arg)
 			continue;
 		}
 
-
 		/* Clear the buffer if full. */
 		if (is_buf_full()) {
 			audio_buf_wp = audio_buf_rp;
@@ -415,7 +414,7 @@ void audio_codec_wov_task(void *arg)
 		 * case, sample is S16_LE.  Thus, n / 2.
 		 */
 		if (!hotword_detected &&
-				GoogleHotwordDspProcess(p, n / 2, &r)) {
+		    GoogleHotwordDspProcess(p, n / 2, &r)) {
 			CPRINTS("hotword detected");
 
 			mutex_lock(&lock);
diff --git a/common/backlight_lid.c b/common/backlight_lid.c
index f0dd3b2e24..f8fd8d637f 100644
--- a/common/backlight_lid.c
+++ b/common/backlight_lid.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,7 +11,6 @@
 #include "host_command.h"
 #include "lid_switch.h"
 
-
 /**
  * Activate/Deactivate the backlight GPIO pin considering active high or low.
  */
@@ -32,7 +31,7 @@ static void update_backlight(void)
 #ifdef CONFIG_BACKLIGHT_REQ_GPIO
 	/* Enable the backlight if lid is open AND requested by AP */
 	enable_backlight(lid_is_open() &&
-		gpio_get_level(CONFIG_BACKLIGHT_REQ_GPIO));
+			 gpio_get_level(CONFIG_BACKLIGHT_REQ_GPIO));
 #else
 	/*
 	 * Enable backlight if lid is open; this is AND'd with the request from
@@ -79,5 +78,4 @@ switch_command_enable_backlight(struct host_cmd_handler_args *args)
 	return EC_RES_SUCCESS;
 }
 DECLARE_HOST_COMMAND(EC_CMD_SWITCH_ENABLE_BKLIGHT,
-		     switch_command_enable_backlight,
-		     EC_VER_MASK(0));
+		     switch_command_enable_backlight, EC_VER_MASK(0));
diff --git a/common/base32.c b/common/base32.c
index a6be8409b1..fc3fe3c8ae 100644
--- a/common/base32.c
+++ b/common/base32.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,15 +9,13 @@
 #include "base32.h"
 #include "util.h"
 
-static const unsigned char crc5_table1[] = {
-	0x00, 0x0E, 0x1C, 0x12, 0x11, 0x1F, 0x0D, 0x03,
-	0x0B, 0x05, 0x17, 0x19, 0x1A, 0x14, 0x06, 0x08
-};
+static const unsigned char crc5_table1[] = { 0x00, 0x0E, 0x1C, 0x12, 0x11, 0x1F,
+					     0x0D, 0x03, 0x0B, 0x05, 0x17, 0x19,
+					     0x1A, 0x14, 0x06, 0x08 };
 
-static const unsigned char crc5_table0[] = {
-	0x00, 0x16, 0x05, 0x13, 0x0A, 0x1C, 0x0F, 0x19,
-	0x14, 0x02, 0x11, 0x07, 0x1E, 0x08, 0x1B, 0x0D
-};
+static const unsigned char crc5_table0[] = { 0x00, 0x16, 0x05, 0x13, 0x0A, 0x1C,
+					     0x0F, 0x19, 0x14, 0x02, 0x11, 0x07,
+					     0x1E, 0x08, 0x1B, 0x0D };
 
 uint8_t crc5_sym(uint8_t sym, uint8_t previous_crc)
 {
@@ -46,9 +44,8 @@ static int decode_sym(int sym)
 	return -1;
 }
 
-int base32_encode(char *dest, int destlen_chars,
-		  const void *srcbits, int srclen_bits,
-		  int add_crc_every)
+int base32_encode(char *dest, int destlen_chars, const void *srcbits,
+		  int srclen_bits, int add_crc_every)
 {
 	const uint8_t *src = srcbits;
 	int destlen_needed;
@@ -59,14 +56,14 @@ int base32_encode(char *dest, int destlen_chars,
 	*dest = 0;
 
 	/* Make sure destination is big enough */
-	destlen_needed = (srclen_bits + 4) / 5;  /* Symbols before adding CRC */
+	destlen_needed = (srclen_bits + 4) / 5; /* Symbols before adding CRC */
 	if (add_crc_every) {
 		/* Must be an exact number of groups to add CRC */
 		if (destlen_needed % add_crc_every)
 			return EC_ERROR_INVAL;
 		destlen_needed += destlen_needed / add_crc_every;
 	}
-	destlen_needed++;  /* For terminating null */
+	destlen_needed++; /* For terminating null */
 	if (destlen_chars < destlen_needed)
 		return EC_ERROR_INVAL;
 
@@ -124,7 +121,7 @@ int base32_decode(uint8_t *dest, int destlen_bits, const char *src,
 
 		sym = decode_sym(*src);
 		if (sym < 0)
-			return -1;  /* Bad input symbol */
+			return -1; /* Bad input symbol */
 
 		/* Check CRC if needed */
 		if (crc_after_every) {
@@ -155,7 +152,7 @@ int base32_decode(uint8_t *dest, int destlen_bits, const char *src,
 		dbits = 8 - (out_bits & 7);
 		b = MIN(dbits, sbits);
 		if (dbits == 8)
-			dest[out_bits / 8] = 0;  /* Starting a new byte */
+			dest[out_bits / 8] = 0; /* Starting a new byte */
 		dest[out_bits / 8] |= (sym << (dbits - b)) >> (sbits - b);
 		out_bits += b;
 		sbits -= b;
diff --git a/common/base_state.c b/common/base_state.c
index 543329fe29..f90a5e7ce5 100644
--- a/common/base_state.c
+++ b/common/base_state.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,7 +8,7 @@
 #include "host_command.h"
 #include "hooks.h"
 
-#define CPRINTS(format, args...) cprints(CC_MOTION_LID, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_MOTION_LID, format, ##args)
 
 #ifdef CONFIG_BASE_ATTACHED_SWITCH
 /* 1: base attached, 0: otherwise */
@@ -33,7 +33,7 @@ void base_set_state(int state)
 }
 #endif
 
-static int command_setbasestate(int argc, char **argv)
+static int command_setbasestate(int argc, const char **argv)
 {
 	if (argc != 2)
 		return EC_ERROR_PARAM_COUNT;
@@ -47,10 +47,9 @@ static int command_setbasestate(int argc, char **argv)
 		return EC_ERROR_PARAM1;
 
 	return EC_SUCCESS;
-
 }
-DECLARE_CONSOLE_COMMAND(basestate, command_setbasestate,
-	"[attach | detach | reset]",
+DECLARE_CONSOLE_COMMAND(
+	basestate, command_setbasestate, "[attach | detach | reset]",
 	"Manually force base state to attached, detached or reset.");
 
 static enum ec_status hostcmd_setbasestate(struct host_cmd_handler_args *args)
diff --git a/common/battery.c b/common/battery.c
index 01478d5b52..00c9540a1f 100644
--- a/common/battery.c
+++ b/common/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -6,6 +6,7 @@
  */
 
 #include "battery.h"
+#include "battery_fuel_gauge.h"
 #include "charge_manager.h"
 #include "charge_state.h"
 #include "common.h"
@@ -21,8 +22,8 @@
 #include "util.h"
 #include "watchdog.h"
 
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 #define CUTOFFPRINTS(info) CPRINTS("%s %s", "Battery cut off", info)
 
 /* See config.h for details */
@@ -77,9 +78,14 @@ static int check_print_error(int rv)
 
 static void print_battery_status(void)
 {
-	static const char * const st[] = {"EMPTY", "FULL", "DCHG", "INIT",};
-	static const char * const al[] = {"RT", "RC", "--", "TD",
-					  "OT", "--", "TC", "OC"};
+	static const char *const st[] = {
+		"EMPTY",
+		"FULL",
+		"DCHG",
+		"INIT",
+	};
+	static const char *const al[] = { "RT", "RC", "--", "TD",
+					  "OT", "--", "TC", "OC" };
 
 	int value, i;
 
@@ -92,12 +98,12 @@ static void print_battery_status(void)
 
 		/* bits 4-7 are status */
 		for (i = 0; i < 4; i++)
-			if (value & (1 << (i+4)))
+			if (value & (1 << (i + 4)))
 				ccprintf(" %s", st[i]);
 
 		/* bits 15-8 are alarms */
 		for (i = 0; i < 8; i++)
-			if (value & (1 << (i+8)))
+			if (value & (1 << (i + 8)))
 				ccprintf(" %s", al[i]);
 
 		ccprintf("\n");
@@ -138,10 +144,8 @@ static void print_battery_params(void)
 	ccprintf("%08x\n", batt->flags);
 
 	print_item_name("Temp:");
-	ccprintf("0x%04x = %.1d K (%.1d C)\n",
-		 batt->temperature,
-		 batt->temperature,
-		 batt->temperature - 2731);
+	ccprintf("0x%04x = %.1d K (%.1d C)\n", batt->temperature,
+		 batt->temperature, batt->temperature - 2731);
 
 	print_item_name("V:");
 	ccprintf("0x%04x = %d mV\n", batt->voltage, batt->voltage);
@@ -167,7 +171,7 @@ static void print_battery_params(void)
 		 batt->flags & BATT_FLAG_WANT_CHARGE ? "" : "Not ");
 
 	print_item_name("Charge:");
-		ccprintf("%d %%\n", batt->state_of_charge);
+	ccprintf("%d %%\n", batt->state_of_charge);
 
 	if (IS_ENABLED(CONFIG_CHARGER)) {
 		int value;
@@ -214,10 +218,10 @@ static void print_battery_info(void)
 	print_item_name("Time-full:");
 	if (check_print_error(battery_time_to_full(&value))) {
 		if (value == 65535) {
-			hour   = 0;
+			hour = 0;
 			minute = 0;
 		} else {
-			hour   = value / 60;
+			hour = value / 60;
 			minute = value % 60;
 		}
 		ccprintf("%dh:%d\n", hour, minute);
@@ -226,10 +230,10 @@ static void print_battery_info(void)
 	print_item_name("  Empty:");
 	if (check_print_error(battery_time_to_empty(&value))) {
 		if (value == 65535) {
-			hour   = 0;
+			hour = 0;
 			minute = 0;
 		} else {
-			hour   = value / 60;
+			hour = value / 60;
 			minute = value % 60;
 		}
 		ccprintf("%dh:%d\n", hour, minute);
@@ -240,6 +244,15 @@ static void print_battery_info(void)
 
 	print_item_name("shutdown_soc:");
 	ccprintf("%d %%\n", batt_host_shutdown_pct);
+
+#ifdef CONFIG_BATTERY_FUEL_GAUGE
+	value = battery_is_charge_fet_disabled();
+	/* reverse the flag if no error */
+	if (value != -1)
+		value = !value;
+	print_item_name("C-FET:");
+	ccprintf("%d\n", value);
+#endif
 }
 
 void print_battery_debug(void)
@@ -250,7 +263,7 @@ void print_battery_debug(void)
 	print_battery_info();
 }
 
-static int command_battery(int argc, char **argv)
+static int command_battery(int argc, const char **argv)
 {
 	int repeat = 1;
 	int loop;
@@ -289,8 +302,7 @@ static int command_battery(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(battery, command_battery,
-			"<repeat_count> <sleep_ms>",
+DECLARE_CONSOLE_COMMAND(battery, command_battery, "<repeat_count> <sleep_ms>",
 			"Print battery info");
 
 #ifdef CONFIG_BATTERY_CUT_OFF
@@ -349,7 +361,7 @@ static enum ec_status battery_command_cutoff(struct host_cmd_handler_args *args)
 	return rv;
 }
 DECLARE_HOST_COMMAND(EC_CMD_BATTERY_CUT_OFF, battery_command_cutoff,
-		EC_VER_MASK(0) | EC_VER_MASK(1));
+		     EC_VER_MASK(0) | EC_VER_MASK(1));
 
 static void check_pending_cutoff(void)
 {
@@ -362,7 +374,7 @@ static void check_pending_cutoff(void)
 }
 DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, check_pending_cutoff, HOOK_PRIO_LAST);
 
-static int command_cutoff(int argc, char **argv)
+static int command_cutoff(int argc, const char **argv)
 {
 	int rv;
 
@@ -384,15 +396,14 @@ static int command_cutoff(int argc, char **argv)
 
 	return EC_ERROR_UNKNOWN;
 }
-DECLARE_CONSOLE_COMMAND(cutoff, command_cutoff,
-		"[at-shutdown]",
-		"Cut off the battery output");
+DECLARE_CONSOLE_COMMAND(cutoff, command_cutoff, "[at-shutdown]",
+			"Cut off the battery output");
 #else
 int battery_is_cut_off(void)
 {
-	return 0;  /* Always return NOT cut off */
+	return 0; /* Always return NOT cut off */
 }
-#endif  /* CONFIG_BATTERY_CUT_OFF */
+#endif /* CONFIG_BATTERY_CUT_OFF */
 
 #ifdef CONFIG_BATTERY_VENDOR_PARAM
 __overridable int battery_get_vendor_param(uint32_t param, uint32_t *value)
@@ -427,7 +438,7 @@ __overridable int battery_set_vendor_param(uint32_t param, uint32_t value)
 	return EC_ERROR_UNIMPLEMENTED;
 }
 
-static int console_command_battery_vendor_param(int argc, char **argv)
+static int console_command_battery_vendor_param(int argc, const char **argv)
 {
 	uint32_t param;
 	uint32_t value;
@@ -488,11 +499,9 @@ host_command_battery_vendor_param(struct host_cmd_handler_args *args)
 	return rv;
 }
 DECLARE_HOST_COMMAND(EC_CMD_BATTERY_VENDOR_PARAM,
-		     host_command_battery_vendor_param,
-		     EC_VER_MASK(0));
+		     host_command_battery_vendor_param, EC_VER_MASK(0));
 #endif /* CONFIG_BATTERY_VENDOR_PARAM */
 
-
 void battery_compensate_params(struct batt_params *batt)
 {
 	int numer, denom;
@@ -500,7 +509,7 @@ void battery_compensate_params(struct batt_params *batt)
 	int full = batt->full_capacity;
 
 	if ((batt->flags & BATT_FLAG_BAD_FULL_CAPACITY) ||
-			(batt->flags & BATT_FLAG_BAD_REMAINING_CAPACITY))
+	    (batt->flags & BATT_FLAG_BAD_REMAINING_CAPACITY))
 		return;
 
 	if (*remain <= 0 || full <= 0)
@@ -589,20 +598,21 @@ __overridable enum battery_disconnect_state battery_get_disconnect_state(void)
 #ifdef CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV
 
 #if CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV < 5000 || \
-    CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV >= PD_MAX_VOLTAGE_MV
-	#error "Voltage limit must be between 5000 and PD_MAX_VOLTAGE_MV"
+	CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV >= PD_MAX_VOLTAGE_MV
+#error "Voltage limit must be between 5000 and PD_MAX_VOLTAGE_MV"
 #endif
 
 #if !((defined(CONFIG_USB_PD_TCPMV1) && defined(CONFIG_USB_PD_DUAL_ROLE)) || \
-    (defined(CONFIG_USB_PD_TCPMV2) && defined(CONFIG_USB_PE_SM)))
-	#error "Voltage reducing requires TCPM with Policy Engine"
+      (defined(CONFIG_USB_PD_TCPMV2) && defined(CONFIG_USB_PE_SM)))
+#error "Voltage reducing requires TCPM with Policy Engine"
 #endif
 
 /*
  * Returns true if input voltage should be reduced (chipset is in S5/G3) and
  * battery is full, otherwise returns false
  */
-static bool board_wants_reduced_input_voltage(void) {
+static bool board_wants_reduced_input_voltage(void)
+{
 	struct batt_params batt;
 
 	/* Chipset not in S5/G3, so we don't want to reduce voltage */
@@ -638,7 +648,7 @@ static void reduce_input_voltage_when_full(void)
 		    CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV) {
 			saved_input_voltage = max_pd_voltage_mv;
 			max_pd_voltage_mv =
-			    CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV;
+				CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV;
 		}
 	} else if (saved_input_voltage != -1) {
 		/*
@@ -656,8 +666,7 @@ static void reduce_input_voltage_when_full(void)
 	if (pd_get_max_voltage() != max_pd_voltage_mv)
 		pd_set_external_voltage_limit(port, max_pd_voltage_mv);
 }
-DECLARE_HOOK(HOOK_AC_CHANGE, reduce_input_voltage_when_full,
-	     HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_AC_CHANGE, reduce_input_voltage_when_full, HOOK_PRIO_DEFAULT);
 DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, reduce_input_voltage_when_full,
 	     HOOK_PRIO_DEFAULT);
 DECLARE_HOOK(HOOK_CHIPSET_STARTUP, reduce_input_voltage_when_full,
@@ -677,7 +686,7 @@ void battery_validate_params(struct batt_params *batt)
 	 */
 	if (batt->temperature > CELSIUS_TO_DECI_KELVIN(5660)) {
 		CPRINTS("ignoring ridiculous batt.temp of %dC",
-			 DECI_KELVIN_TO_CELSIUS(batt->temperature));
+			DECI_KELVIN_TO_CELSIUS(batt->temperature));
 		batt->flags |= BATT_FLAG_BAD_TEMPERATURE;
 	}
 
diff --git a/common/battery_fuel_gauge.c b/common/battery_fuel_gauge.c
index 900798a9fd..0382abca26 100644
--- a/common/battery_fuel_gauge.c
+++ b/common/battery_fuel_gauge.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -12,7 +12,7 @@
 #include "i2c.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 /*
  * Authenticate the battery connected.
@@ -26,8 +26,8 @@ static bool authenticate_battery_type(int index, char *manuf_name)
 {
 	char device_name[32];
 
-	const struct fuel_gauge_info * const fuel_gauge =
-			&board_battery_info[index].fuel_gauge;
+	const struct fuel_gauge_info *const fuel_gauge =
+		&board_battery_info[index].fuel_gauge;
 	int len = 0;
 
 	/* check for valid index */
@@ -40,17 +40,14 @@ static bool authenticate_battery_type(int index, char *manuf_name)
 
 	/* device name is specified in table */
 	if (fuel_gauge->device_name != NULL) {
-
 		/* Get the device name */
-		if (battery_device_name(device_name,
-				sizeof(device_name)))
+		if (battery_device_name(device_name, sizeof(device_name)))
 			return false;
 
 		len = strlen(fuel_gauge->device_name);
 
 		/* device name mismatch */
-		if (strncasecmp(device_name, fuel_gauge->device_name,
-					len))
+		if (strncasecmp(device_name, fuel_gauge->device_name, len))
 			return false;
 	}
 
@@ -70,7 +67,7 @@ static int battery_get_fixed_battery_type(void)
 {
 	if (fixed_battery_type == BATTERY_TYPE_UNINITIALIZED) {
 		CPRINTS("Warning: Battery type is not Initialized! "
-				"Setting to default battery type.\n");
+			"Setting to default battery type.\n");
 		fixed_battery_type = DEFAULT_BATTERY_TYPE;
 	}
 
@@ -144,7 +141,8 @@ static inline const struct board_batt_params *get_batt_params(void)
 	int type = get_battery_type();
 
 	return &board_battery_info[type == BATTERY_TYPE_COUNT ?
-		board_get_default_battery_type() : type];
+					   board_get_default_battery_type() :
+					   type];
 }
 
 const struct battery_info *battery_get_info(void)
@@ -202,10 +200,10 @@ int board_cut_off_battery(void)
 
 	if (board_battery_info[type].fuel_gauge.ship_mode.wb_support)
 		rv = cut_off_battery_block_write(
-			  &board_battery_info[type].fuel_gauge.ship_mode);
+			&board_battery_info[type].fuel_gauge.ship_mode);
 	else
 		rv = cut_off_battery_sb_write(
-			  &board_battery_info[type].fuel_gauge.ship_mode);
+			&board_battery_info[type].fuel_gauge.ship_mode);
 
 	return rv ? EC_RES_ERROR : EC_RES_SUCCESS;
 }
@@ -308,8 +306,7 @@ enum battery_disconnect_state battery_get_disconnect_state(void)
 	if ((reg & board_battery_info[type].fuel_gauge.fet.reg_mask) ==
 	    board_battery_info[type].fuel_gauge.fet.disconnect_val) {
 		CPRINTS("Batt disconnected: reg 0x%04x mask 0x%04x disc 0x%04x",
-			reg,
-			board_battery_info[type].fuel_gauge.fet.reg_mask,
+			reg, board_battery_info[type].fuel_gauge.fet.reg_mask,
 			board_battery_info[type].fuel_gauge.fet.disconnect_val);
 		return BATTERY_DISCONNECTED;
 	}
@@ -326,8 +323,9 @@ int battery_imbalance_mv(void)
 	 * If battery type is unknown, we cannot safely access non-standard
 	 * registers.
 	 */
-	return (type == BATTERY_TYPE_COUNT) ? 0 :
-		board_battery_info[type].fuel_gauge.imbalance_mv();
+	return (type == BATTERY_TYPE_COUNT) ?
+		       0 :
+		       board_battery_info[type].fuel_gauge.imbalance_mv();
 }
 
 int battery_default_imbalance_mv(void)
diff --git a/common/battery_v1.c b/common/battery_v1.c
index d6fc42affb..2c81d6b446 100644
--- a/common/battery_v1.c
+++ b/common/battery_v1.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -15,8 +15,8 @@
 #include "printf.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 /* Returns zero if every item was updated. */
 int update_static_battery_info(void)
@@ -34,8 +34,11 @@ int update_static_battery_info(void)
 	batt_str = (char *)host_get_memmap(EC_MEMMAP_BATT_SERIAL);
 	memset(batt_str, 0, EC_MEMMAP_TEXT_MAX);
 	rv = battery_serial_number(&batt_serial);
-	if (!rv)
-		snprintf(batt_str, EC_MEMMAP_TEXT_MAX, "%04X", batt_serial);
+	if (!rv) {
+		if (snprintf(batt_str, EC_MEMMAP_TEXT_MAX, "%04X",
+			     batt_serial) <= 0)
+			rv |= EC_ERROR_UNKNOWN;
+	}
 
 	/* Design Capacity of Full */
 	rv |= battery_design_capacity(
@@ -136,7 +139,8 @@ void update_dynamic_battery_info(void)
 		 * Don't report zero charge, as that has special meaning
 		 * to Chrome OS powerd.
 		 */
-		if (curr->batt.remaining_capacity == 0 && !curr->batt_is_charging)
+		if (curr->batt.remaining_capacity == 0 &&
+		    !curr->batt_is_charging)
 			*memmap_cap = 1;
 		else
 			*memmap_cap = curr->batt.remaining_capacity;
@@ -151,12 +155,11 @@ void update_dynamic_battery_info(void)
 	}
 
 	if (curr->batt.is_present == BP_YES &&
-	    !(curr->batt.flags & BATT_FLAG_BAD_STATE_OF_CHARGE) &&
-	    curr->batt.state_of_charge <= BATTERY_LEVEL_CRITICAL)
+	    battery_is_below_threshold(BATT_THRESHOLD_TYPE_SHUTDOWN, false))
 		tmp |= EC_BATT_FLAG_LEVEL_CRITICAL;
 
 	tmp |= curr->batt_is_charging ? EC_BATT_FLAG_CHARGING :
-				       EC_BATT_FLAG_DISCHARGING;
+					EC_BATT_FLAG_DISCHARGING;
 
 	/* Tell the AP to re-read battery status if charge state changes */
 	if (*memmap_flags != tmp)
diff --git a/common/battery_v2.c b/common/battery_v2.c
index 27ae0285ac..57ae07196b 100644
--- a/common/battery_v2.c
+++ b/common/battery_v2.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -15,8 +15,8 @@
 #include "printf.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 /*
  * Store battery information in these 2 structures. Main (lid) battery is always
@@ -135,8 +135,7 @@ host_command_battery_get_static(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_BATTERY_GET_STATIC,
-		     host_command_battery_get_static,
+DECLARE_HOST_COMMAND(EC_CMD_BATTERY_GET_STATIC, host_command_battery_get_static,
 		     EC_VER_MASK(0) | EC_VER_MASK(1));
 
 static enum ec_status
@@ -154,8 +153,7 @@ host_command_battery_get_dynamic(struct host_cmd_handler_args *args)
 	return EC_RES_SUCCESS;
 }
 DECLARE_HOST_COMMAND(EC_CMD_BATTERY_GET_DYNAMIC,
-		     host_command_battery_get_dynamic,
-		     EC_VER_MASK(0));
+		     host_command_battery_get_dynamic, EC_VER_MASK(0));
 #endif /* CONFIG_HOSTCMD_BATTERY_V2 */
 
 void battery_memmap_refresh(enum battery_index index)
@@ -222,8 +220,9 @@ int update_static_battery_info(void)
 	/* Smart battery serial number is 16 bits */
 	rv = battery_serial_number(&batt_serial);
 	if (!rv)
-		snprintf(bs->serial_ext, sizeof(bs->serial_ext),
-			 "%04X", batt_serial);
+		if (snprintf(bs->serial_ext, sizeof(bs->serial_ext), "%04X",
+			     batt_serial) <= 0)
+			rv |= EC_ERROR_UNKNOWN;
 
 	/* Design Capacity of Full */
 	ret = battery_design_capacity(&val);
@@ -344,29 +343,31 @@ void update_dynamic_battery_info(void)
 		 * to Chrome OS powerd.
 		 */
 		if (curr->batt.remaining_capacity == 0 &&
-				!curr->batt_is_charging)
+		    !curr->batt_is_charging)
 			bd->remaining_capacity = 1;
 		else
 			bd->remaining_capacity = curr->batt.remaining_capacity;
 	}
 
 	if (!(curr->batt.flags & BATT_FLAG_BAD_FULL_CAPACITY) &&
-		(curr->batt.full_capacity <=
-			(bd->full_capacity - LFCC_EVENT_THRESH) ||
-		 curr->batt.full_capacity >=
-			(bd->full_capacity + LFCC_EVENT_THRESH))) {
+	    (curr->batt.full_capacity <=
+		     (bd->full_capacity - LFCC_EVENT_THRESH) ||
+	     curr->batt.full_capacity >=
+		     (bd->full_capacity + LFCC_EVENT_THRESH))) {
 		bd->full_capacity = curr->batt.full_capacity;
 		/* Poke the AP if the full_capacity changes. */
 		send_batt_info_event++;
 	}
 
 	if (curr->batt.is_present == BP_YES &&
-	    !(curr->batt.flags & BATT_FLAG_BAD_STATE_OF_CHARGE) &&
-	    curr->batt.state_of_charge <= BATTERY_LEVEL_CRITICAL)
+	    battery_is_below_threshold(BATT_THRESHOLD_TYPE_SHUTDOWN, false))
 		tmp |= EC_BATT_FLAG_LEVEL_CRITICAL;
 
 	tmp |= curr->batt_is_charging ? EC_BATT_FLAG_CHARGING :
-				       EC_BATT_FLAG_DISCHARGING;
+					EC_BATT_FLAG_DISCHARGING;
+
+	if (battery_is_cut_off())
+		tmp |= EC_BATT_FLAG_CUT_OFF;
 
 	/* Tell the AP to re-read battery status if charge state changes */
 	if (bd->flags != tmp)
diff --git a/common/blink.c b/common/blink.c
index ed16146f5a..dcd6f0bdaa 100644
--- a/common/blink.c
+++ b/common/blink.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,12 +10,12 @@
 #include "hooks.h"
 
 #ifndef CONFIG_BLINK_LEDS
-	#error The macro CONFIG_BLINK_LEDS must be specified to use BLINK.
+#error The macro CONFIG_BLINK_LEDS must be specified to use BLINK.
 #endif
 
 static const enum gpio_signal leds[] = { CONFIG_BLINK_LEDS };
 
-BUILD_ASSERT(ARRAY_SIZE(leds) <= sizeof(int)*8, "Too many LEDs to drive.");
+BUILD_ASSERT(ARRAY_SIZE(leds) <= sizeof(int) * 8, "Too many LEDs to drive.");
 BUILD_ASSERT(ARRAY_SIZE(leds) > 0, "Must have at least one LED to blink.");
 
 static void blink(void)
diff --git a/common/bluetooth_le.c b/common/bluetooth_le.c
index c148ef8285..3108553a8b 100644
--- a/common/bluetooth_le.c
+++ b/common/bluetooth_le.c
@@ -1,13 +1,14 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "builtin/assert.h"
 #include "bluetooth_le.h"
 #include "util.h"
 #include "console.h"
 
-#define CPRINTF(format, args...) cprintf(CC_BLUETOOTH_LE, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_BLUETOOTH_LE, format, ##args)
 
 /*
  * Convert from BLE Channel to frequency
@@ -15,11 +16,11 @@
  * Bluetooth 4.1 Vol 6 pg 36 4.1 Table 1.1
  */
 
-#define CHAN_0_MHZ      2404
-#define CHAN_11_MHZ     2428
-#define CHAN_37_MHZ     2402
-#define CHAN_38_MHZ     2426
-#define CHAN_39_MHZ     2480
+#define CHAN_0_MHZ 2404
+#define CHAN_11_MHZ 2428
+#define CHAN_37_MHZ 2402
+#define CHAN_38_MHZ 2426
+#define CHAN_39_MHZ 2480
 
 int chan2freq(int channel)
 {
@@ -72,11 +73,11 @@ uint8_t get_next_data_channel(struct remapping_table *rt)
 
 	/* Check if the channel is mapped */
 	if (rt->map[rt->last_unmapped_channel / 8] &
-			(1 << (rt->last_unmapped_channel % 8)))
+	    (1 << (rt->last_unmapped_channel % 8)))
 		return rt->last_unmapped_channel;
 	else
-		return rt->remapping_index
-			[rt->last_unmapped_channel % rt->num_used_channels];
+		return rt->remapping_index[rt->last_unmapped_channel %
+					   rt->num_used_channels];
 }
 
 /* BLE 4.1 Vol 3 Part C 11 */
@@ -85,27 +86,27 @@ uint8_t get_next_data_channel(struct remapping_table *rt)
 uint8_t *pack_adv(uint8_t *dest, int length, int type, const uint8_t *data)
 {
 	/* Add the structure length */
-	dest[0] = (uint8_t)length+1;
+	dest[0] = (uint8_t)length + 1;
 	/* Add the structure type */
 	dest[1] = (uint8_t)type;
 	/* Add the data */
 	memcpy(&dest[2], data, length);
 
 	/* Return a pointer to the next structure */
-	return &dest[2+length];
+	return &dest[2 + length];
 }
 
 uint8_t *pack_adv_int(uint8_t *dest, int length, int type, int data)
 {
 	/* Add the structure length */
-	dest[0] = (uint8_t)length+1;
+	dest[0] = (uint8_t)length + 1;
 	/* Add the structure type */
 	dest[1] = (uint8_t)type;
 	/* Add the data */
 	memcpy(&dest[2], &data, length);
 
 	/* Return a pointer to the next structure */
-	return &dest[2+length];
+	return &dest[2 + length];
 }
 
 uint8_t *pack_adv_addr(uint8_t *dest, uint64_t addr)
@@ -139,7 +140,7 @@ static void mem_dump(uint8_t *mem, int len)
 	for (i = 0; i < len; i++) {
 		value = mem[i];
 		if (i % 8 == 0)
-			CPRINTF("\n%pP: %02x", &mem[i], value);
+			CPRINTF("\n%p: %02x", &mem[i], value);
 		else
 			CPRINTF(" %02x", value);
 	}
@@ -160,19 +161,19 @@ void dump_ble_packet(struct ble_pdu *ble_p)
 	int curr_offs;
 
 	if (ble_p->header_type_adv) {
-		CPRINTF("BLE packet @ %pP: type %d, len %d, %s %s\n",
-			ble_p, ble_p->header.adv.type, ble_p->header.adv.length,
+		CPRINTF("BLE packet @ %p: type %d, len %d, %s %s\n", ble_p,
+			ble_p->header.adv.type, ble_p->header.adv.length,
 			(ble_p->header.adv.txaddr ? " TXADDR" : ""),
 			(ble_p->header.adv.rxaddr ? " RXADDR" : ""));
 
 		curr_offs = 0;
 
 		if (ble_p->header.adv.type ==
-			BLE_ADV_HEADER_PDU_TYPE_SCAN_REQ) {
+		    BLE_ADV_HEADER_PDU_TYPE_SCAN_REQ) {
 			dump_ble_addr(ble_p->payload, "ScanA");
 			curr_offs += BLUETOOTH_ADDR_OCTETS;
 		} else if (ble_p->header.adv.type ==
-			BLE_ADV_HEADER_PDU_TYPE_CONNECT_REQ) {
+			   BLE_ADV_HEADER_PDU_TYPE_CONNECT_REQ) {
 			dump_ble_addr(ble_p->payload, "InitA");
 			curr_offs += BLUETOOTH_ADDR_OCTETS;
 		}
@@ -187,7 +188,7 @@ void dump_ble_packet(struct ble_pdu *ble_p)
 			mem_dump(ble_p->payload + curr_offs,
 				 ble_p->header.adv.length - curr_offs);
 	} else { /* Data PDUs */
-		CPRINTF("BLE data packet @%pP: LLID %d,"
+		CPRINTF("BLE data packet @%p: LLID %d,"
 			" nesn %d, sn %d, md %d, length %d\n",
 			ble_p, ble_p->header.data.llid, ble_p->header.data.nesn,
 			ble_p->header.data.sn, ble_p->header.data.md,
diff --git a/common/body_detection.c b/common/body_detection.c
index 4fbc88e852..848c4f08c1 100644
--- a/common/body_detection.c
+++ b/common/body_detection.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,8 +14,8 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
 
 static struct motion_sensor_t *body_sensor =
 	&motion_sensors[CONFIG_BODY_DETECTION_SENSOR];
@@ -31,10 +31,9 @@ static bool history_initialized;
 static bool body_detect_enable;
 STATIC_IF(CONFIG_ACCEL_SPOOF_MODE) bool spoof_enable;
 
-static struct body_detect_motion_data
-{
+static struct body_detect_motion_data {
 	int history[CONFIG_BODY_DETECTION_MAX_WINDOW_SIZE]; /* acceleration */
-	int sum;              /* sum(history) */
+	int sum; /* sum(history) */
 	uint64_t n2_variance; /* n^2 * var(history) */
 } data[2]; /* motion data for X-axis and Y-axis */
 
@@ -59,8 +58,8 @@ static void update_motion_data(struct body_detect_motion_data *x, int x_n)
 	const int sum_diff = x_n - x_0;
 	const int new_sum = x->sum + sum_diff;
 
-	x->n2_variance += sum_diff *
-			  ((int64_t)n * (x_n + x_0) - new_sum - x->sum);
+	x->n2_variance +=
+		sum_diff * ((int64_t)n * (x_n + x_0) - new_sum - x->sum);
 	x->sum = new_sum;
 	x->history[history_idx] = x_n;
 }
@@ -76,8 +75,8 @@ static void update_motion_variance(void)
 /* return Var(X) + Var(Y) */
 static uint64_t get_motion_variance(void)
 {
-	return (data[X].n2_variance + data[Y].n2_variance)
-		/ window_size / window_size;
+	return (data[X].n2_variance + data[Y].n2_variance) / window_size /
+	       window_size;
 }
 
 static int calculate_motion_confidence(uint64_t var)
@@ -87,7 +86,7 @@ static int calculate_motion_confidence(uint64_t var)
 	if (var > var_threshold_scaled + confidence_delta_scaled)
 		return 100;
 	return 100 * (var - var_threshold_scaled + confidence_delta_scaled) /
-		(2 * confidence_delta_scaled);
+	       (2 * confidence_delta_scaled);
 }
 
 /* Change the motion state and commit the change to AP. */
@@ -105,7 +104,7 @@ void body_detect_change_state(enum body_detect_states state, bool spoof)
 			.sensor_num = MOTION_SENSE_ACTIVITY_SENSOR_ID,
 		};
 		motion_sense_fifo_stage_data(&vector, NULL, 0,
-				__hw_clock_source_read());
+					     __hw_clock_source_read());
 		motion_sense_fifo_commit_data();
 	}
 	/* change the motion state */
@@ -160,15 +159,15 @@ static void determine_threshold_scale(int range, int resolution, int rms_noise)
 	 * CONFIG_BODY_DETECTION_VAR_NOISE_FACTOR / 100.
 	 */
 	const int var_noise = POW2((uint64_t)rms_noise) *
-			      CONFIG_BODY_DETECTION_VAR_NOISE_FACTOR * POW2(98)
-			      / 100 / POW2(10000);
+			      CONFIG_BODY_DETECTION_VAR_NOISE_FACTOR *
+			      POW2(98) / 100 / POW2(10000);
 
-	var_threshold_scaled = (uint64_t)
-		(CONFIG_BODY_DETECTION_VAR_THRESHOLD + var_noise) *
-		multiplier / divisor;
-	confidence_delta_scaled = (uint64_t)
-		CONFIG_BODY_DETECTION_CONFIDENCE_DELTA *
+	var_threshold_scaled =
+		(uint64_t)(CONFIG_BODY_DETECTION_VAR_THRESHOLD + var_noise) *
 		multiplier / divisor;
+	confidence_delta_scaled =
+		(uint64_t)CONFIG_BODY_DETECTION_CONFIDENCE_DELTA * multiplier /
+		divisor;
 }
 
 void body_detect_reset(void)
@@ -185,8 +184,8 @@ void body_detect_reset(void)
 	if (odr == 0)
 		return;
 	determine_window_size(odr);
-	determine_threshold_scale(body_sensor->current_range,
-				  resolution, rms_noise);
+	determine_threshold_scale(body_sensor->current_range, resolution,
+				  rms_noise);
 	/* initialize motion data and state */
 	memset(data, 0, sizeof(data));
 	history_idx = 0;
diff --git a/common/btle_hci_controller.c b/common/btle_hci_controller.c
index cc5b872b19..a4dcadaccf 100644
--- a/common/btle_hci_controller.c
+++ b/common/btle_hci_controller.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,8 @@
 #ifdef CONFIG_BLUETOOTH_HCI_DEBUG
 
 #define CPUTS(outstr) cputs(CC_BLUETOOTH_HCI, outstr)
-#define CPRINTS(format, args...) cprints(CC_BLUETOOTH_HCI, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_BLUETOOTH_HCI, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_BLUETOOTH_HCI, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_BLUETOOTH_HCI, format, ##args)
 
 #else /* CONFIG_BLUETOOTH_HCI_DEBUG */
 
@@ -27,7 +27,7 @@ static uint64_t hci_le_event_mask;
 
 #define MAX_MESSAGE 24
 
-#define STATUS  (return_params[0])
+#define STATUS (return_params[0])
 #define RPARAMS (&(return_params[1]))
 
 void hci_cmd(uint8_t *hciCmdbuf)
@@ -56,215 +56,184 @@ void hci_cmd(uint8_t *hciCmdbuf)
 	}
 
 	switch (hdr->opcode) {
-	case CMD_MAKE_OPCODE(HCI_OGF_Controller_and_Baseband,
-				HCI_CMD_Reset):
+	case CMD_MAKE_OPCODE(HCI_OGF_Controller_and_Baseband, HCI_CMD_Reset):
 		STATUS = ll_reset();
-	break;
+		break;
 	case CMD_MAKE_OPCODE(HCI_OGF_Controller_and_Baseband,
-				HCI_CMD_Set_Event_Mask):
+			     HCI_CMD_Set_Event_Mask):
 		if (hdr->paramLen != sizeof(hci_event_mask))
 			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
 		else
 			STATUS = HCI_SUCCESS;
 		memcpy(&hci_event_mask, params, sizeof(hci_event_mask));
-	break;
+		break;
 	case CMD_MAKE_OPCODE(HCI_OGF_Controller_and_Baseband,
-				HCI_CMD_Read_Transmit_Power_Level):
-	case CMD_MAKE_OPCODE(HCI_OGF_Informational,
-				HCI_CMD_Read_Local_Supported_Features):
+			     HCI_CMD_Read_Transmit_Power_Level):
 	case CMD_MAKE_OPCODE(HCI_OGF_Informational,
-				HCI_CMD_Read_Local_Supported_Commands):
+			     HCI_CMD_Read_Local_Supported_Features):
 	case CMD_MAKE_OPCODE(HCI_OGF_Informational,
-				HCI_CMD_Read_Local_Version_Information):
+			     HCI_CMD_Read_Local_Supported_Commands):
 	case CMD_MAKE_OPCODE(HCI_OGF_Informational,
-				HCI_CMD_Read_BD_ADDR):
+			     HCI_CMD_Read_Local_Version_Information):
+	case CMD_MAKE_OPCODE(HCI_OGF_Informational, HCI_CMD_Read_BD_ADDR):
 	case CMD_MAKE_OPCODE(HCI_OGF_Link_Control,
-				HCI_CMD_Read_Remote_Version_Information):
-	case CMD_MAKE_OPCODE(HCI_OGF_Status,
-				HCI_CMD_Read_RSSI):
+			     HCI_CMD_Read_Remote_Version_Information):
+	case CMD_MAKE_OPCODE(HCI_OGF_Status, HCI_CMD_Read_RSSI):
 		event = 0;
-	break;
+		break;
 
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Set_Event_Mask):
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Set_Event_Mask):
 		if (hdr->paramLen != sizeof(hci_le_event_mask))
 			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
 		else
 			STATUS = HCI_SUCCESS;
 		memcpy(&hci_le_event_mask, params, sizeof(hci_le_event_mask));
-	break;
+		break;
 
 	/* LE Information */
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Read_Buffer_Size):
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Read_Buffer_Size):
 		if (hdr->paramLen != 0)
 			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
 		else
 			STATUS = ll_read_buffer_size(RPARAMS);
 		rparam_count = sizeof(struct hciCmplLeReadBufferSize);
-	break;
+		break;
 	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Read_Local_Supported_Features):
+			     HCI_CMD_LE_Read_Local_Supported_Features):
 		if (hdr->paramLen != 0)
 			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
 		else
 			STATUS = ll_read_local_supported_features(RPARAMS);
 		rparam_count =
 			sizeof(struct hciCmplLeReadLocalSupportedFeatures);
-	break;
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Read_Supported_States):
+		break;
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Read_Supported_States):
 		if (hdr->paramLen != 0)
 			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
 		else
 			STATUS = ll_read_supported_states(RPARAMS);
 		rparam_count = sizeof(struct hciCmplLeReadSupportedStates);
-	break;
+		break;
 	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Set_Host_Channel_Classification):
+			     HCI_CMD_LE_Set_Host_Channel_Classification):
 		if (hdr->paramLen !=
 		    sizeof(struct hciLeSetHostChannelClassification))
 			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
 		else
 			STATUS = ll_set_host_channel_classification(params);
-	break;
+		break;
 
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Set_Random_Address):
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Set_Random_Address):
 		if (hdr->paramLen != sizeof(struct hciLeSetRandomAddress))
 			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
 		else
 			STATUS = ll_set_random_address(params);
-	break;
+		break;
 
 	/* Advertising */
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Set_Advertise_Enable):
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Set_Advertise_Enable):
 		STATUS = ll_set_advertising_enable(params);
-	break;
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Set_Advertising_Data):
+		break;
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Set_Advertising_Data):
 		STATUS = ll_set_adv_data(params);
-	break;
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Set_Adv_Params):
+		break;
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Set_Adv_Params):
 		if (hdr->paramLen != sizeof(struct hciLeSetAdvParams))
 			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
 		else
 			STATUS = ll_set_advertising_params(params);
-	break;
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Read_Adv_Channel_TX_Power):
+		break;
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Read_Adv_Channel_TX_Power):
 		STATUS = ll_read_tx_power();
 		rparam_count = sizeof(struct hciCmplLeReadAdvChannelTxPower);
-	break;
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Set_Scan_Response_Data):
+		break;
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Set_Scan_Response_Data):
 		STATUS = ll_set_scan_response_data(params);
-	break;
+		break;
 
 	/* Connections */
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Read_Remote_Used_Features):
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Read_Remote_Used_Features):
 		if (hdr->paramLen != sizeof(struct hciLeReadRemoteUsedFeatures))
 			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
 		else
 			STATUS = ll_read_remote_used_features(params);
 		event = HCI_EVT_Command_Status;
-	break;
-	case CMD_MAKE_OPCODE(HCI_OGF_Link_Control,
-				HCI_CMD_Disconnect):
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Connection_Update):
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Create_Connection):
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Create_Connection_Cancel):
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Read_Channel_Map):
+		break;
+	case CMD_MAKE_OPCODE(HCI_OGF_Link_Control, HCI_CMD_Disconnect):
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Connection_Update):
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Create_Connection):
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Create_Connection_Cancel):
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Read_Channel_Map):
 		event = 0;
-	break;
+		break;
 
 	/* Encryption */
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Encrypt):
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_LTK_Request_Reply):
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_LTK_Request_Negative_Reply):
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Rand):
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Start_Encryption):
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Encrypt):
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_LTK_Request_Reply):
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_LTK_Request_Negative_Reply):
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Rand):
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Start_Encryption):
 		event = 0;
-	break;
+		break;
 
 	/* Scanning */
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Set_Scan_Enable):
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Set_Scan_Enable):
 		if (hdr->paramLen != sizeof(struct hciLeSetScanEnable))
 			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
 		else
 			STATUS = ll_set_scan_enable(params);
-	break;
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Set_Scan_Parameters):
+		break;
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Set_Scan_Parameters):
 		if (hdr->paramLen != sizeof(struct hciLeSetScanParams))
 			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
 		else
 			STATUS = ll_set_scan_params(params);
-	break;
+		break;
 
 	/* Allow List */
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Clear_Allow_List):
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Clear_Allow_List):
 		if (hdr->paramLen != 0)
 			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
 		else
 			STATUS = ll_clear_allow_list();
-	break;
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Read_Allow_List_Size):
+		break;
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Read_Allow_List_Size):
 		if (hdr->paramLen != 0)
 			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
 		else
 			STATUS = ll_read_allow_list_size(RPARAMS);
 		rparam_count = sizeof(struct hciCmplLeReadAllowListSize);
-	break;
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Add_Device_To_Allow_List):
+		break;
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Add_Device_To_Allow_List):
 		if (hdr->paramLen != sizeof(struct hciLeAddDeviceToAllowList))
 			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
 		else
 			STATUS = ll_add_device_to_allow_list(params);
-	break;
+		break;
 	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Remove_Device_From_Allow_List):
+			     HCI_CMD_LE_Remove_Device_From_Allow_List):
 		if (hdr->paramLen !=
-				sizeof(struct hciLeRemoveDeviceFromAllowList))
+		    sizeof(struct hciLeRemoveDeviceFromAllowList))
 			STATUS = HCI_ERR_Invalid_HCI_Command_Parameters;
 		else
 			STATUS = ll_remove_device_from_allow_list(params);
-	break;
+		break;
 
 	/* RFPHY Testing Support */
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Receiver_Test):
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Receiver_Test):
 		STATUS = ll_receiver_test(params);
-	break;
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Transmitter_Test):
+		break;
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Transmitter_Test):
 		STATUS = ll_transmitter_test(params);
-	break;
-	case CMD_MAKE_OPCODE(HCI_OGF_LE,
-				HCI_CMD_LE_Test_End):
+		break;
+	case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Test_End):
 		STATUS = ll_test_end(RPARAMS);
 		rparam_count = sizeof(struct hciCmplLeTestEnd);
-	break;
+		break;
 
 	default:
 		STATUS = HCI_ERR_Unknown_HCI_Command;
-	break;
+		break;
 	}
 
 	hci_event(event, rparam_count, return_params);
@@ -275,12 +244,11 @@ void hci_acl_to_host(uint8_t *data, uint16_t hdr, uint16_t len)
 	int i;
 
 	/* Enqueue hdr, len, len bytes of data */
-	CPRINTF("Sending %d bytes of data from handle %d with PB=%x.\n",
-		len, hdr & ACL_HDR_MASK_CONN_ID,
-		hdr & ACL_HDR_MASK_PB);
-		for (i = 0; i < len; i++)
-			CPRINTF("0x%x, ", data[i]);
-		CPRINTF("\n");
+	CPRINTF("Sending %d bytes of data from handle %d with PB=%x.\n", len,
+		hdr & ACL_HDR_MASK_CONN_ID, hdr & ACL_HDR_MASK_PB);
+	for (i = 0; i < len; i++)
+		CPRINTF("0x%x, ", data[i]);
+	CPRINTF("\n");
 }
 
 void hci_acl_from_host(uint8_t *hciAclbuf)
@@ -290,12 +258,11 @@ void hci_acl_from_host(uint8_t *hciAclbuf)
 	int i;
 
 	/* Send the data to the link layer */
-	CPRINTF("Sending %d bytes of data to handle %d with PB=%x.\n",
-		hdr->len, hdr->hdr & ACL_HDR_MASK_CONN_ID,
-		hdr->hdr & ACL_HDR_MASK_PB);
-		for (i = 0; i < hdr->len; i++)
-			CPRINTF("0x%x, ", data[i]);
-		CPRINTF("\n");
+	CPRINTF("Sending %d bytes of data to handle %d with PB=%x.\n", hdr->len,
+		hdr->hdr & ACL_HDR_MASK_CONN_ID, hdr->hdr & ACL_HDR_MASK_PB);
+	for (i = 0; i < hdr->len; i++)
+		CPRINTF("0x%x, ", data[i]);
+	CPRINTF("\n");
 }
 
 /*
@@ -335,52 +302,50 @@ void hci_event(uint8_t event_code, uint8_t len, uint8_t *params)
  * hcitool lcmd 0x2008 18 0x42410906 0x03454443 0x203c119 0x3030501 0x1812
  * hcitool cmd 8 8 6 9 41 42 43 44 45 3 19 c1 3 2 1 5 3 3 12 18
  */
-uint8_t adv0[19] = {0x07, 0x09, 'A', 'B', 'C', 'D', 'E', 'F', /* Name */
-		    0x03, 0x19, 0xc1, 0x03,                   /* Keyboard */
-		    0x02, 0x01, 0x05,                         /* Flags */
-		    0x03, 0x03, 0x12, 0x18};                  /* UUID */
+uint8_t adv0[19] = { 0x07, 0x09, 'A',  'B',  'C', 'D', 'E', 'F', /* Name */
+		     0x03, 0x19, 0xc1, 0x03, /* Keyboard */
+		     0x02, 0x01, 0x05, /* Flags */
+		     0x03, 0x03, 0x12, 0x18 }; /* UUID */
 
-uint8_t adv1[18] = {0x06, 0x09, 'A', 'B', 'C', 'D', 'E',      /* Name */
-		    0x02, 0x01, 0x05,                         /* Flags */
-		    0x03, 0x19, 0xc1, 0x03,                   /* Keyboard */
-		    0x03, 0x03, 0x12, 0x18};                  /* UUID */
+uint8_t adv1[18] = { 0x06, 0x09, 'A',  'B',  'C', 'D', 'E', /* Name */
+		     0x02, 0x01, 0x05, /* Flags */
+		     0x03, 0x19, 0xc1, 0x03, /* Keyboard */
+		     0x03, 0x03, 0x12, 0x18 }; /* UUID */
 
-uint8_t *adverts[] = {adv0, adv1};
-uint8_t adv_lengths[] = {sizeof(adv0), sizeof(adv1)};
+uint8_t *adverts[] = { adv0, adv1 };
+uint8_t adv_lengths[] = { sizeof(adv0), sizeof(adv1) };
 
-uint8_t scan0[4] = {0x03, 0x08, 'A', 'B'}; /* Short Name */
+uint8_t scan0[4] = { 0x03, 0x08, 'A', 'B' }; /* Short Name */
 
-uint8_t scan1[] = {};                         /* Empty */
+uint8_t scan1[] = {}; /* Empty */
 
-uint8_t *scans[] = {scan0, scan1};
-uint8_t scan_lengths[] = {sizeof(scan0), sizeof(scan1)};
+uint8_t *scans[] = { scan0, scan1 };
+uint8_t scan_lengths[] = { sizeof(scan0), sizeof(scan1) };
 
 /*
  * LE_Set_Adv_Params
  * hcitool lcmd 0x2006 15 0x010000f0 0xb0010100 0xb4b3b2b1 0x0007c5
  * hcitool cmd 8 6 f0 0 0 1 0 1 1 b0 b1 b2 b3 b4 c5 7 0
  */
-uint8_t adv_param0[15] = {
-		0xf0, 0x00,                               /* IntervalMin */
-		0x00, 0x01,                               /* IntervalMax */
-		0x00,                                     /* Adv Type */
-		0x01,                                     /* Use Random Addr */
-		0x01,                                     /* Direct Random */
-		0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xc5,       /* Direct Addr */
-		0x07,                                     /* Channel Map */
-		0x00};                                    /* Filter Policy */
-
-uint8_t adv_param1[15] = {
-		0xf0, 0x00,                               /* IntervalMin */
-		0x00, 0x01,                               /* IntervalMax */
-		0x02,                                     /* Adv Type */
-		0x01,                                     /* Use Random Addr */
-		0x01,                                     /* Direct Random */
-		0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xc5,       /* Direct Addr */
-		0x07,                                     /* Channel Map */
-		0x00};                                    /* Filter Policy */
-
-uint8_t *adv_params[] = {adv_param0, adv_param1};
+uint8_t adv_param0[15] = { 0xf0, 0x00, /* IntervalMin */
+			   0x00, 0x01, /* IntervalMax */
+			   0x00, /* Adv Type */
+			   0x01, /* Use Random Addr */
+			   0x01, /* Direct Random */
+			   0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xc5, /* Direct Addr */
+			   0x07, /* Channel Map */
+			   0x00 }; /* Filter Policy */
+
+uint8_t adv_param1[15] = { 0xf0, 0x00, /* IntervalMin */
+			   0x00, 0x01, /* IntervalMax */
+			   0x02, /* Adv Type */
+			   0x01, /* Use Random Addr */
+			   0x01, /* Direct Random */
+			   0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xc5, /* Direct Addr */
+			   0x07, /* Channel Map */
+			   0x00 }; /* Filter Policy */
+
+uint8_t *adv_params[] = { adv_param0, adv_param1 };
 
 /*
  * LE Information
@@ -466,7 +431,7 @@ static uint8_t hci_buf[200];
 #define MAX_BLE_HCI_PARAMS 8
 static uint32_t param[MAX_BLE_HCI_PARAMS];
 
-static int command_ble_hci_cmd(int argc, char **argv)
+static int command_ble_hci_cmd(int argc, const char **argv)
 {
 	static struct hciCmdHdr header;
 	int length, opcode, i;
@@ -489,7 +454,7 @@ static int command_ble_hci_cmd(int argc, char **argv)
 	}
 
 	for (i = 3; i < argc; i++) {
-		param[i-3] = strtoi(argv[i], &e, 0);
+		param[i - 3] = strtoi(argv[i], &e, 0);
 		if (*e)
 			return EC_ERROR_PARAM3 + i;
 	}
@@ -498,12 +463,11 @@ static int command_ble_hci_cmd(int argc, char **argv)
 	header.paramLen = length;
 
 	memcpy(hci_buf, &header, sizeof(struct hciCmdHdr));
-	memcpy(hci_buf + sizeof(struct hciCmdHdr),
-			param, length);
+	memcpy(hci_buf + sizeof(struct hciCmdHdr), param, length);
 
 	hci_cmd(hci_buf);
 
-	CPRINTS("hci cmd @%pP", hci_buf);
+	CPRINTS("hci cmd @%p", hci_buf);
 
 	return EC_SUCCESS;
 }
@@ -511,7 +475,7 @@ DECLARE_CONSOLE_COMMAND(ble_hci_cmd, command_ble_hci_cmd,
 			"opcode len uint32 uint32 uint32... (little endian)",
 			"Send an hci command of length len");
 
-static int command_hcitool(int argc, char **argv)
+static int command_hcitool(int argc, const char **argv)
 {
 	static struct hciCmdHdr header;
 	int i, ogf, ocf;
@@ -521,7 +485,7 @@ static int command_hcitool(int argc, char **argv)
 		return EC_ERROR_PARAM_COUNT;
 
 	if (argv[1][0] == 'l') /* strcmp lcmd */
-		return command_ble_hci_cmd(argc-1, &argv[1]);
+		return command_ble_hci_cmd(argc - 1, &argv[1]);
 
 	ogf = strtoi(argv[2], &e, 16);
 	if (*e)
@@ -532,7 +496,7 @@ static int command_hcitool(int argc, char **argv)
 		return EC_ERROR_PARAM3;
 
 	header.opcode = CMD_MAKE_OPCODE(ogf, ocf);
-	header.paramLen = argc-4;
+	header.paramLen = argc - 4;
 	memcpy(hci_buf, &header, sizeof(struct hciCmdHdr));
 
 	for (i = 4; i < argc; i++) {
@@ -543,15 +507,16 @@ static int command_hcitool(int argc, char **argv)
 
 	hci_cmd(hci_buf);
 
-	CPRINTS("hci cmd @%pP", hci_buf);
+	CPRINTS("hci cmd @%p", hci_buf);
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(hcitool, command_hcitool,
-			"cmd ogf ocf b0 b1 b2 b3... or lcmd opcode len uint32.. (little endian)",
-			"Send an hci command of length len");
+DECLARE_CONSOLE_COMMAND(
+	hcitool, command_hcitool,
+	"cmd ogf ocf b0 b1 b2 b3... or lcmd opcode len uint32.. (little endian)",
+	"Send an hci command of length len");
 
-static int command_ble_hci_acl(int argc, char **argv)
+static int command_ble_hci_acl(int argc, const char **argv)
 {
 	static struct hciAclHdr header;
 	int length, hdr, i;
@@ -574,7 +539,7 @@ static int command_ble_hci_acl(int argc, char **argv)
 	}
 
 	for (i = 3; i < argc; i++) {
-		param[i-3] = strtoi(argv[i], &e, 0);
+		param[i - 3] = strtoi(argv[i], &e, 0);
 		if (*e)
 			return EC_ERROR_PARAM3 + i;
 	}
@@ -583,12 +548,11 @@ static int command_ble_hci_acl(int argc, char **argv)
 	header.len = length;
 
 	memcpy(hci_buf, &header, sizeof(struct hciCmdHdr));
-	memcpy(hci_buf + sizeof(struct hciCmdHdr),
-			param, length);
+	memcpy(hci_buf + sizeof(struct hciCmdHdr), param, length);
 
 	hci_cmd(hci_buf);
 
-	CPRINTS("hci acl @%pP", hci_buf);
+	CPRINTS("hci acl @%p", hci_buf);
 
 	return EC_SUCCESS;
 }
@@ -596,7 +560,7 @@ DECLARE_CONSOLE_COMMAND(ble_hci_acl, command_ble_hci_acl,
 			"hdr len uint32 uint32 uint32... (little endian)",
 			"Send hci acl data of length len");
 
-static int command_ble_hci_adv(int argc, char **argv)
+static int command_ble_hci_adv(int argc, const char **argv)
 {
 	static struct hciCmdHdr header;
 	int adv, p = 0, scan_rsp = 0;
@@ -625,33 +589,33 @@ static int command_ble_hci_adv(int argc, char **argv)
 	header.paramLen = sizeof(struct hciLeSetAdvParams);
 
 	memcpy(hci_buf, &header, sizeof(struct hciCmdHdr));
-	memcpy(hci_buf + sizeof(struct hciCmdHdr),
-			adv_params[p], header.paramLen);
+	memcpy(hci_buf + sizeof(struct hciCmdHdr), adv_params[p],
+	       header.paramLen);
 
 	hci_cmd(hci_buf);
 
-	header.opcode = CMD_MAKE_OPCODE(HCI_OGF_LE,
-					HCI_CMD_LE_Set_Advertising_Data);
+	header.opcode =
+		CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Set_Advertising_Data);
 	header.paramLen = adv_lengths[adv];
 
 	memcpy(hci_buf, &header, sizeof(struct hciCmdHdr));
-	memcpy(hci_buf + sizeof(struct hciCmdHdr),
-			adverts[adv], header.paramLen);
+	memcpy(hci_buf + sizeof(struct hciCmdHdr), adverts[adv],
+	       header.paramLen);
 
 	hci_cmd(hci_buf);
 
-	header.opcode = CMD_MAKE_OPCODE(HCI_OGF_LE,
-					HCI_CMD_LE_Set_Scan_Response_Data);
+	header.opcode =
+		CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Set_Scan_Response_Data);
 	header.paramLen = scan_lengths[scan_rsp];
 
 	memcpy(hci_buf, &header, sizeof(struct hciCmdHdr));
-	memcpy(hci_buf + sizeof(struct hciCmdHdr),
-			scans[scan_rsp], header.paramLen);
+	memcpy(hci_buf + sizeof(struct hciCmdHdr), scans[scan_rsp],
+	       header.paramLen);
 
 	hci_cmd(hci_buf);
 
-	header.opcode = CMD_MAKE_OPCODE(HCI_OGF_LE,
-					HCI_CMD_LE_Set_Advertise_Enable);
+	header.opcode =
+		CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Set_Advertise_Enable);
 	header.paramLen = sizeof(struct hciLeSetAdvEnable);
 
 	memcpy(hci_buf, &header, sizeof(struct hciCmdHdr));
diff --git a/common/btle_ll.c b/common/btle_ll.c
index d57eb3bfd3..71ca108565 100644
--- a/common/btle_ll.c
+++ b/common/btle_ll.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,8 +16,8 @@
 #ifdef CONFIG_BLUETOOTH_LL_DEBUG
 
 #define CPUTS(outstr) cputs(CC_BLUETOOTH_LL, outstr)
-#define CPRINTS(format, args...) cprints(CC_BLUETOOTH_LL, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_BLUETOOTH_LL, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_BLUETOOTH_LL, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_BLUETOOTH_LL, format, ##args)
 
 #else /* CONFIG_BLUETOOTH_LL_DEBUG */
 
@@ -57,7 +57,7 @@ uint8_t is_first_data_packet;
 
 static uint64_t ll_random_address = 0xC5BADBADBAD1; /* Uninitialized */
 static uint64_t ll_public_address = 0xC5BADBADBADF; /* Uninitialized */
-static uint8_t ll_channel_map[5] = {0xff, 0xff, 0xff, 0xff, 0x1f};
+static uint8_t ll_channel_map[5] = { 0xff, 0xff, 0xff, 0xff, 0x1f };
 
 static uint8_t ll_filter_duplicates;
 
@@ -161,8 +161,8 @@ static uint8_t ll_state_change_request(enum ll_state_t next_state)
 {
 	/* Initialize the radio if it hasn't been initialized */
 	if (ll_state == UNINITIALIZED) {
-		if (ble_radio_init(BLE_ADV_ACCESS_ADDRESS, BLE_ADV_CRCINIT)
-				!= EC_SUCCESS)
+		if (ble_radio_init(BLE_ADV_ACCESS_ADDRESS, BLE_ADV_CRCINIT) !=
+		    EC_SUCCESS)
 			return HCI_ERR_Hardware_Failure;
 		ll_state = STANDBY;
 	}
@@ -236,50 +236,50 @@ uint8_t initialize_connection(void)
 	num_consecutive_failures = 0;
 
 	/* Copy data into the appropriate portions of memory */
-	memcpy((uint8_t *)&(conn_params.init_a),
-			payload_start, CONNECT_REQ_INITA_LEN);
+	memcpy((uint8_t *)&(conn_params.init_a), payload_start,
+	       CONNECT_REQ_INITA_LEN);
 	cur_offset += CONNECT_REQ_INITA_LEN;
 
-	memcpy((uint8_t *)&(conn_params.adv_a),
-			payload_start+cur_offset, CONNECT_REQ_ADVA_LEN);
+	memcpy((uint8_t *)&(conn_params.adv_a), payload_start + cur_offset,
+	       CONNECT_REQ_ADVA_LEN);
 	cur_offset += CONNECT_REQ_ADVA_LEN;
 
-	memcpy(&(conn_params.access_addr),
-			payload_start+cur_offset, CONNECT_REQ_ACCESS_ADDR_LEN);
+	memcpy(&(conn_params.access_addr), payload_start + cur_offset,
+	       CONNECT_REQ_ACCESS_ADDR_LEN);
 	cur_offset += CONNECT_REQ_ACCESS_ADDR_LEN;
 
 	conn_params.crc_init_val = 0;
-	memcpy(&(conn_params.crc_init_val),
-			payload_start+cur_offset, CONNECT_REQ_CRC_INIT_VAL_LEN);
+	memcpy(&(conn_params.crc_init_val), payload_start + cur_offset,
+	       CONNECT_REQ_CRC_INIT_VAL_LEN);
 	cur_offset += CONNECT_REQ_CRC_INIT_VAL_LEN;
 
-	memcpy(&(conn_params.win_size),
-			payload_start+cur_offset, CONNECT_REQ_WIN_SIZE_LEN);
+	memcpy(&(conn_params.win_size), payload_start + cur_offset,
+	       CONNECT_REQ_WIN_SIZE_LEN);
 	cur_offset += CONNECT_REQ_WIN_SIZE_LEN;
 
-	memcpy(&(conn_params.win_offset),
-			payload_start+cur_offset, CONNECT_REQ_WIN_OFFSET_LEN);
+	memcpy(&(conn_params.win_offset), payload_start + cur_offset,
+	       CONNECT_REQ_WIN_OFFSET_LEN);
 	cur_offset += CONNECT_REQ_WIN_OFFSET_LEN;
 
-	memcpy(&(conn_params.interval),
-			payload_start+cur_offset, CONNECT_REQ_INTERVAL_LEN);
+	memcpy(&(conn_params.interval), payload_start + cur_offset,
+	       CONNECT_REQ_INTERVAL_LEN);
 	cur_offset += CONNECT_REQ_INTERVAL_LEN;
 
-	memcpy(&(conn_params.latency),
-			payload_start+cur_offset, CONNECT_REQ_LATENCY_LEN);
+	memcpy(&(conn_params.latency), payload_start + cur_offset,
+	       CONNECT_REQ_LATENCY_LEN);
 	cur_offset += CONNECT_REQ_LATENCY_LEN;
 
-	memcpy(&(conn_params.timeout),
-			payload_start+cur_offset, CONNECT_REQ_TIMEOUT_LEN);
+	memcpy(&(conn_params.timeout), payload_start + cur_offset,
+	       CONNECT_REQ_TIMEOUT_LEN);
 	cur_offset += CONNECT_REQ_TIMEOUT_LEN;
 
 	conn_params.channel_map = 0;
-	memcpy(&(conn_params.channel_map),
-			payload_start+cur_offset, CONNECT_REQ_CHANNEL_MAP_LEN);
+	memcpy(&(conn_params.channel_map), payload_start + cur_offset,
+	       CONNECT_REQ_CHANNEL_MAP_LEN);
 	cur_offset += CONNECT_REQ_CHANNEL_MAP_LEN;
 
-	memcpy(&final_octet, payload_start+cur_offset,
-			CONNECT_REQ_HOP_INCREMENT_AND_SCA_LEN);
+	memcpy(&final_octet, payload_start + cur_offset,
+	       CONNECT_REQ_HOP_INCREMENT_AND_SCA_LEN);
 
 	/* last  5 bits of final_octet: */
 	conn_params.hop_increment = final_octet & 0x1f;
@@ -288,9 +288,9 @@ uint8_t initialize_connection(void)
 
 	/* Set up channel mapping table */
 	for (i = 0; i < 5; ++i)
-		remap_arr[i] = *(((uint8_t *)&(conn_params.channel_map))+i);
+		remap_arr[i] = *(((uint8_t *)&(conn_params.channel_map)) + i);
 	fill_remapping_table(&remap_table, remap_arr,
-		conn_params.hop_increment);
+			     conn_params.hop_increment);
 
 	/* Calculate transmission window parameters */
 	conn_params.transmitWindowSize = conn_params.win_size * 1250;
@@ -332,7 +332,7 @@ uint8_t ll_read_allow_list_size(uint8_t *return_params)
 uint8_t ll_add_device_to_allow_list(uint8_t *params)
 {
 	if (ble_radio_add_device_to_allow_list(&params[1], params[0]) ==
-			EC_SUCCESS)
+	    EC_SUCCESS)
 		return HCI_SUCCESS;
 	else
 		return HCI_ERR_Host_Rejected_Due_To_Limited_Resources;
@@ -341,7 +341,7 @@ uint8_t ll_add_device_to_allow_list(uint8_t *params)
 uint8_t ll_remove_device_from_allow_list(uint8_t *params)
 {
 	if (ble_radio_remove_device_from_allow_list(&params[1], params[0]) ==
-			EC_SUCCESS)
+	    EC_SUCCESS)
 		return HCI_SUCCESS;
 	else
 		return HCI_ERR_Hardware_Failure;
@@ -449,27 +449,28 @@ uint8_t ll_set_advertising_params(uint8_t *params)
 	case BLE_ADV_HEADER_PDU_TYPE_ADV_NONCONN_IND:
 	case BLE_ADV_HEADER_PDU_TYPE_ADV_SCAN_IND:
 		if (ll_adv_params.advIntervalMin <
-		    (100000 / LL_ADV_INTERVAL_UNIT_US))    /* 100ms */
+		    (100000 / LL_ADV_INTERVAL_UNIT_US)) /* 100ms */
 			return HCI_ERR_Invalid_HCI_Command_Parameters;
 	/* Fall through */
 	case BLE_ADV_HEADER_PDU_TYPE_ADV_IND:
 		if (ll_adv_params.advIntervalMin > ll_adv_params.advIntervalMax)
 			return HCI_ERR_Invalid_HCI_Command_Parameters;
 		if (ll_adv_params.advIntervalMin <
-		    (20000 / LL_ADV_INTERVAL_UNIT_US) ||   /* 20ms */
+			    (20000 / LL_ADV_INTERVAL_UNIT_US) || /* 20ms */
 		    ll_adv_params.advIntervalMax >
-		    (10240000 / LL_ADV_INTERVAL_UNIT_US))  /* 10.24s */
+			    (10240000 / LL_ADV_INTERVAL_UNIT_US)) /* 10.24s */
 			return HCI_ERR_Invalid_HCI_Command_Parameters;
 		ll_adv_interval_us = (((ll_adv_params.advIntervalMin +
-					ll_adv_params.advIntervalMax) / 2) *
-					LL_ADV_INTERVAL_UNIT_US);
+					ll_adv_params.advIntervalMax) /
+				       2) *
+				      LL_ADV_INTERVAL_UNIT_US);
 		/* Don't time out */
 		ll_adv_timeout_us = -1;
-	break;
+		break;
 	case BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND:
 		ll_adv_interval_us = LL_ADV_DIRECT_INTERVAL_US;
 		ll_adv_timeout_us = LL_ADV_DIRECT_TIMEOUT_US;
-	break;
+		break;
 	default:
 		return HCI_ERR_Invalid_HCI_Command_Parameters;
 	}
@@ -563,25 +564,25 @@ int ble_ll_adv(int chan)
 	case BLE_ADV_HEADER_PDU_TYPE_SCAN_REQ:
 		/* Scan requests are only allowed for ADV_IND and SCAN_IND */
 		if ((ll_adv_pdu.header.adv.type !=
-		     BLE_ADV_HEADER_PDU_TYPE_ADV_IND &&
+			     BLE_ADV_HEADER_PDU_TYPE_ADV_IND &&
 		     ll_adv_pdu.header.adv.type !=
-		     BLE_ADV_HEADER_PDU_TYPE_ADV_SCAN_IND) ||
-			/* The advertising address needs to match */
+			     BLE_ADV_HEADER_PDU_TYPE_ADV_SCAN_IND) ||
+		    /* The advertising address needs to match */
 		    (memcmp(&ll_rcv_packet.payload[BLUETOOTH_ADDR_OCTETS],
 			    &ll_adv_pdu.payload[0], BLUETOOTH_ADDR_OCTETS))) {
 			/* Don't send the scan response */
 			radio_disable();
 			return rv;
 		}
-	break;
+		break;
 	case BLE_ADV_HEADER_PDU_TYPE_CONNECT_REQ:
 		/* Don't send a scan response */
 		radio_disable();
 		/* Connecting is only allowed for ADV_IND and ADV_DIRECT_IND */
 		if (ll_adv_pdu.header.adv.type !=
-			BLE_ADV_HEADER_PDU_TYPE_ADV_IND &&
+			    BLE_ADV_HEADER_PDU_TYPE_ADV_IND &&
 		    ll_adv_pdu.header.adv.type !=
-			BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND)
+			    BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND)
 			return rv;
 		/* The advertising address needs to match */
 		if (memcmp(&ll_rcv_packet.payload[BLUETOOTH_ADDR_OCTETS],
@@ -589,9 +590,9 @@ int ble_ll_adv(int chan)
 			return rv;
 		/* The InitAddr address needs to match for ADV_DIRECT_IND */
 		if (ll_adv_pdu.header.adv.type ==
-			BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND &&
-			memcmp(&ll_adv_pdu.payload[BLUETOOTH_ADDR_OCTETS],
-			&ll_rcv_packet.payload[0], BLUETOOTH_ADDR_OCTETS))
+			    BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND &&
+		    memcmp(&ll_adv_pdu.payload[BLUETOOTH_ADDR_OCTETS],
+			   &ll_rcv_packet.payload[0], BLUETOOTH_ADDR_OCTETS))
 			return rv;
 
 		/* Mark time that connect was received */
@@ -604,11 +605,11 @@ int ble_ll_adv(int chan)
 		ll_state = CONNECTION;
 
 		return rv;
-	break;
+		break;
 	default: /* Unhandled response packet */
 		radio_disable();
 		return rv;
-	break;
+		break;
 	}
 
 	CPRINTF("ADV %u Response %u %u\n", tx_end, rsp_end, tx_rsp_end);
@@ -632,7 +633,6 @@ int ble_ll_adv_event(void)
 	return rv;
 }
 
-
 void print_connection_state(void)
 {
 	CPRINTF("vvvvvvvvvvvvvvvvvvvCONNECTION STATEvvvvvvvvvvvvvvvvvvv\n");
@@ -663,12 +663,12 @@ int connected_communicate(void)
 
 	if (num_consecutive_failures > 0) {
 		ble_radio_init(conn_params.access_addr,
-			conn_params.crc_init_val);
+			       conn_params.crc_init_val);
 		NRF51_RADIO_FREQUENCY =
 			NRF51_RADIO_FREQUENCY_VAL(chan2freq(comm_channel));
 		NRF51_RADIO_DATAWHITEIV = comm_channel;
-		listen_time = last_receive_time + conn_params.connInterval
-			- get_time().val + conn_params.transmitWindowSize;
+		listen_time = last_receive_time + conn_params.connInterval -
+			      get_time().val + conn_params.transmitWindowSize;
 
 		/*
 		 * This listens for 1.25 times the expected amount
@@ -680,12 +680,12 @@ int connected_communicate(void)
 		 * slightly longer than expected in the case that
 		 * there was a timing disagreement.
 		 */
-		rv = ble_rx(&ll_rcv_packet,
-			listen_time + (listen_time >> 2), 0);
+		rv = ble_rx(&ll_rcv_packet, listen_time + (listen_time >> 2),
+			    0);
 	} else {
 		if (!is_first_data_packet) {
-			sleep_time = receive_time +
-				conn_params.connInterval - get_time().val;
+			sleep_time = receive_time + conn_params.connInterval -
+				     get_time().val;
 			/*
 			 * The time slept is 31/32 (96.875%) of the calculated
 			 * required sleep time because the code to receive
@@ -695,8 +695,8 @@ int connected_communicate(void)
 		} else {
 			last_receive_time = time_of_connect_req;
 			sleep_time = TRANSMIT_WINDOW_OFFSET_CONSTANT +
-					conn_params.transmitWindowOffset +
-					time_of_connect_req - get_time().val;
+				     conn_params.transmitWindowOffset +
+				     time_of_connect_req - get_time().val;
 			if (sleep_time >= 0) {
 				/*
 				 * Radio is on for longer than needed for first
@@ -709,7 +709,7 @@ int connected_communicate(void)
 		}
 
 		ble_radio_init(conn_params.access_addr,
-			conn_params.crc_init_val);
+			       conn_params.crc_init_val);
 		NRF51_RADIO_FREQUENCY =
 			NRF51_RADIO_FREQUENCY_VAL(chan2freq(comm_channel));
 		NRF51_RADIO_DATAWHITEIV = comm_channel;
@@ -722,14 +722,13 @@ int connected_communicate(void)
 		 * how early the window opens in microseconds.
 		 */
 		if (!is_first_data_packet)
-			offset = last_receive_time + conn_params.connInterval
-				- get_time().val;
+			offset = last_receive_time + conn_params.connInterval -
+				 get_time().val;
 		else
 			offset = 0;
 
 		rv = ble_rx(&ll_rcv_packet,
-			    offset + conn_params.transmitWindowSize,
-			    0);
+			    offset + conn_params.transmitWindowSize, 0);
 	}
 
 	/*
@@ -766,9 +765,9 @@ void bluetooth_ll_task(void)
 		case ADVERTISING:
 
 			if (deadline.val == 0) {
-				CPRINTS("ADV @%pP", &ll_adv_pdu);
+				CPRINTS("ADV @%p", &ll_adv_pdu);
 				deadline.val = get_time().val +
-					(uint32_t)ll_adv_timeout_us;
+					       (uint32_t)ll_adv_timeout_us;
 				ll_adv_events = 0;
 			}
 
@@ -786,7 +785,7 @@ void bluetooth_ll_task(void)
 				ll_state = STANDBY;
 				break;
 			}
-		break;
+			break;
 		case STANDBY:
 			deadline.val = 0;
 			CPRINTS("Standby %d events", ll_adv_events);
@@ -795,20 +794,20 @@ void bluetooth_ll_task(void)
 			task_wait_event(-1);
 			connection_initialized = 0;
 			errors_recovered = 0;
-		break;
+			break;
 		case TEST_RX:
 			if (ble_test_rx() == HCI_SUCCESS)
 				ll_test_packets++;
 			/* Packets come every 625us, sleep to save power */
 			usleep(300);
-		break;
+			break;
 		case TEST_TX:
 			start = get_time().le.lo;
 			ble_test_tx();
 			ll_test_packets++;
 			end = get_time().le.lo;
-			usleep(625 - 82 - (end-start)); /* 625us */
-		break;
+			usleep(625 - 82 - (end - start)); /* 625us */
+			break;
 		case UNINITIALIZED:
 			ble_radio_init(BLE_ADV_ACCESS_ADDRESS, BLE_ADV_CRCINIT);
 			ll_adv_events = 0;
@@ -816,7 +815,7 @@ void bluetooth_ll_task(void)
 			connection_initialized = 0;
 			packet_tb_sent = &tx_packet_1;
 			set_empty_data_packet(&tx_packet_1);
-		break;
+			break;
 		case CONNECTION:
 			if (!connection_initialized) {
 				if (initialize_connection() != HCI_SUCCESS) {
@@ -835,8 +834,7 @@ void bluetooth_ll_task(void)
 			} else {
 				num_consecutive_failures++;
 				if ((get_time().val - last_rx_time) >
-					conn_params.connSupervisionTimeout) {
-
+				    conn_params.connSupervisionTimeout) {
 					ll_state = STANDBY;
 					CPRINTF("EXITING CONNECTION STATE "
 						"DUE TO TIMEOUT.\n");
@@ -847,10 +845,11 @@ void bluetooth_ll_task(void)
 			if (ll_state == STANDBY) {
 				CPRINTF("Exiting connection state/Entering "
 					"Standby state after %d connections "
-					"events\n", ll_conn_events);
+					"events\n",
+					ll_conn_events);
 				print_connection_state();
 			}
-		break;
+			break;
 		default:
 			CPRINTS("Unhandled State ll_state = %d", ll_state);
 			ll_state = UNINITIALIZED;
diff --git a/common/build.mk b/common/build.mk
index 6473d53291..f784d57732 100644
--- a/common/build.mk
+++ b/common/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
+# Copyright 2014 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -9,7 +9,7 @@
 # Note that this variable includes the trailing "/"
 _common_dir:=$(dir $(lastword $(MAKEFILE_LIST)))
 
-common-y=util.o util_stdlib.o
+common-y=util.o
 common-y+=version.o printf.o queue.o queue_policies.o irq_locking.o
 
 common-$(CONFIG_ACCELGYRO_BMI160)+=math_util.o
@@ -66,7 +66,10 @@ common-$(CONFIG_CHARGE_RAMP_SW)+=charge_ramp.o charge_ramp_sw.o
 common-$(CONFIG_CHARGESPLASH)+=chargesplash.o
 common-$(CONFIG_CHIP_INIT_ROM_REGION)+=init_rom.o
 common-$(CONFIG_CMD_CHARGEN) += chargen.o
-common-$(CONFIG_CHARGER)+=charger.o charge_state_v2.o
+common-$(CONFIG_CHARGER)+=charger.o
+ifneq ($(CONFIG_CHARGER),)
+common-$(CONFIG_BATTERY)+=charge_state_v2.o
+endif
 common-$(CONFIG_CHARGER_PROFILE_OVERRIDE_COMMON)+=charger_profile_override.o
 common-$(CONFIG_CMD_I2CWEDGE)+=i2c_wedge.o
 common-$(CONFIG_COMMON_GPIO)+=gpio.o gpio_commands.o
diff --git a/common/button.c b/common/button.c
index 145cd9db74..53745adaef 100644
--- a/common/button.c
+++ b/common/button.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,7 +24,7 @@
 #include "watchdog.h"
 
 /* Console output macro */
-#define CPRINTS(format, args...) cprints(CC_SWITCH, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SWITCH, format, ##args)
 
 struct button_state_t {
 	uint64_t debounce_time;
@@ -75,12 +75,12 @@ static int raw_button_pressed(const struct button_config *button)
 	int simulated_value = 0;
 	if (!(button->flags & BUTTON_FLAG_DISABLED)) {
 		if (IS_ENABLED(CONFIG_ADC_BUTTONS) &&
-			button_is_adc_detected(button->gpio)) {
-			physical_value =
-				adc_to_physical_value(button->gpio);
+		    button_is_adc_detected(button->gpio)) {
+			physical_value = adc_to_physical_value(button->gpio);
 		} else {
-			physical_value = (!!gpio_get_level(button->gpio) ==
-				!!(button->flags & BUTTON_FLAG_ACTIVE_HIGH));
+			physical_value =
+				(!!gpio_get_level(button->gpio) ==
+				 !!(button->flags & BUTTON_FLAG_ACTIVE_HIGH));
 		}
 #ifdef CONFIG_SIMULATED_BUTTON
 		simulated_value = simulated_button_pressed(button);
@@ -193,7 +193,7 @@ static int is_recovery_boot(void)
 	if (system_jumped_to_this_image())
 		return 0;
 	if (!(system_get_reset_flags() &
-	    (EC_RESET_FLAG_RESET_PIN | EC_RESET_FLAG_POWER_ON)))
+	      (EC_RESET_FLAG_RESET_PIN | EC_RESET_FLAG_POWER_ON)))
 		return 0;
 	if (!is_recovery_button_pressed())
 		return 0;
@@ -202,7 +202,7 @@ static int is_recovery_boot(void)
 #endif /* CONFIG_BUTTON_TRIGGERED_RECOVERY */
 
 static void button_reset(enum button button_type,
-	const struct button_config *button)
+			 const struct button_config *button)
 {
 	state[button_type].debounced_pressed = raw_button_pressed(button);
 	state[button_type].debounce_time = 0;
@@ -260,7 +260,6 @@ int button_disable_gpio(enum button button_type)
 }
 #endif
 
-
 /*
  * Handle debounced button changing state.
  */
@@ -308,15 +307,14 @@ static void button_change_deferred(void)
 					hook_call_deferred(
 						&debug_mode_handle_data, 0);
 #endif
-				CPRINTS("Button '%s' was %s",
-					buttons[i].name, new_pressed ?
-					"pressed" : "released");
+				CPRINTS("Button '%s' was %s", buttons[i].name,
+					new_pressed ? "pressed" : "released");
 				if (IS_ENABLED(CONFIG_MKBP_INPUT_DEVICES)) {
 					mkbp_button_update(buttons[i].type,
-								new_pressed);
+							   new_pressed);
 				} else if (IS_ENABLED(HAS_TASK_KEYPROTO)) {
 					keyboard_update_button(buttons[i].type,
-								new_pressed);
+							       new_pressed);
 				}
 			}
 
@@ -327,10 +325,11 @@ static void button_change_deferred(void)
 			 * Make sure the next deferred call happens on or before
 			 * each button needs it.
 			 */
-			soonest_debounce_time = (soonest_debounce_time == 0) ?
-				state[i].debounce_time :
-				MIN(soonest_debounce_time,
-				    state[i].debounce_time);
+			soonest_debounce_time =
+				(soonest_debounce_time == 0) ?
+					state[i].debounce_time :
+					MIN(soonest_debounce_time,
+					    state[i].debounce_time);
 		}
 	}
 
@@ -418,12 +417,12 @@ static void simulate_button(uint32_t button_mask, int press_ms)
 
 	/* Defer the button release for specified duration */
 	hook_call_deferred(&simulate_button_release_deferred_data,
-				press_ms * MSEC);
+			   press_ms * MSEC);
 }
 #endif /* #ifdef CONFIG_SIMULATED_BUTTON */
 
 #ifdef CONFIG_CMD_BUTTON
-static int console_command_button(int argc, char **argv)
+static int console_command_button(int argc, const char **argv)
 {
 	int press_ms = 50;
 	char *e;
@@ -465,8 +464,7 @@ static int console_command_button(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(button, console_command_button,
-			"vup|vdown|rec msec",
+DECLARE_CONSOLE_COMMAND(button, console_command_button, "vup|vdown|rec msec",
 			"Simulate button press");
 #endif /* CONFIG_CMD_BUTTON */
 
@@ -494,7 +492,6 @@ DECLARE_HOST_COMMAND(EC_CMD_BUTTON, host_command_button, EC_VER_MASK(0));
 
 #endif /* CONFIG_HOSTCMD_BUTTON */
 
-
 #ifdef CONFIG_EMULATED_SYSRQ
 
 #ifdef CONFIG_DEDICATED_RECOVERY_BUTTON
@@ -546,10 +543,10 @@ enum debug_state {
 	STATE_WARM_RESET_EXEC,
 };
 
-#define DEBUG_BTN_POWER         BIT(0)
-#define DEBUG_BTN_VOL_UP        BIT(1)
-#define DEBUG_BTN_VOL_DN        BIT(2)
-#define DEBUG_TIMEOUT           (10 * SECOND)
+#define DEBUG_BTN_POWER BIT(0)
+#define DEBUG_BTN_VOL_UP BIT(1)
+#define DEBUG_BTN_VOL_DN BIT(2)
+#define DEBUG_TIMEOUT (10 * SECOND)
 
 static enum debug_state curr_debug_state = STATE_DEBUG_NONE;
 static enum debug_state next_debug_state = STATE_DEBUG_NONE;
@@ -721,8 +718,9 @@ static void debug_mode_handle(void)
 			 * Schedule a deferred call in case timeout hasn't
 			 * occurred yet.
 			 */
-			hook_call_deferred(&debug_mode_handle_data,
-					(debug_state_deadline.val - now.val));
+			hook_call_deferred(
+				&debug_mode_handle_data,
+				(debug_state_deadline.val - now.val));
 		}
 
 		break;
diff --git a/common/capsense.c b/common/capsense.c
index b2413ac61f..2c2bbd6db5 100644
--- a/common/capsense.c
+++ b/common/capsense.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,11 +9,12 @@
 #include "hooks.h"
 #include "i2c.h"
 #include "keyboard_protocol.h"
+#include "printf.h"
 #include "timer.h"
 
 /* Console output macro */
-#define CPRINTF(format, args...) cprintf(CC_KEYBOARD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_KEYBOARD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ##args)
 
 #define CAPSENSE_I2C_ADDR 0x08
 #define CAPSENSE_MASK_BITS 8
@@ -24,8 +25,7 @@ static int capsense_read_bitmask(void)
 	int rv;
 	uint8_t val = 0;
 
-	rv = i2c_xfer(I2C_PORT_CAPSENSE, CAPSENSE_I2C_ADDR,
-		      0, 0, &val, 1);
+	rv = i2c_xfer(I2C_PORT_CAPSENSE, CAPSENSE_I2C_ADDR, 0, 0, &val, 1);
 
 	if (rv)
 		CPRINTS("%s failed: error %d", __func__, rv);
@@ -49,11 +49,12 @@ static void capsense_change_deferred(void)
 	static uint8_t cur_val;
 	uint8_t new_val;
 	int i, n, c;
+	char ts_str[PRINTF_TIMESTAMP_BUF_SIZE];
 
 	new_val = capsense_read_bitmask();
 	if (new_val != cur_val) {
-		CPRINTF("[%pT capsense 0x%02x: ",
-			PRINTF_TIMESTAMP_NOW, new_val);
+		snprintf_timestamp_now(ts_str, sizeof(ts_str));
+		CPRINTF("[%s capsense 0x%02x: ", ts_str, new_val);
 		for (i = 0; i < CAPSENSE_MASK_BITS; i++) {
 			/* See what changed */
 			n = (new_val >> i) & 0x01;
diff --git a/common/cbi.c b/common/cbi.c
index e18f15e5a9..26125c902e 100644
--- a/common/cbi.c
+++ b/common/cbi.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -31,8 +31,8 @@ uint8_t cbi_crc8(const struct cbi_header *h)
 			 h->total_size - sizeof(h->magic) - sizeof(h->crc));
 }
 
-uint8_t *cbi_set_data(uint8_t *p, enum cbi_data_tag tag,
-		      const void *buf, int size)
+uint8_t *cbi_set_data(uint8_t *p, enum cbi_data_tag tag, const void *buf,
+		      int size)
 {
 	struct cbi_data *d = (struct cbi_data *)p;
 
@@ -77,11 +77,11 @@ struct cbi_data *cbi_find_tag(const void *buf, enum cbi_data_tag tag)
  */
 #ifndef HOST_TOOLS_BUILD
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, "CBI " format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, "CBI " format, ##args)
 
 static int cache_status = CBI_CACHE_STATUS_INVALID;
 static uint8_t cbi[CBI_IMAGE_SIZE];
-static struct cbi_header * const head = (struct cbi_header *)cbi;
+static struct cbi_header *const head = (struct cbi_header *)cbi;
 
 int cbi_create(void)
 {
@@ -133,21 +133,21 @@ static int do_cbi_read(void)
 	 * buffer has practical limitation.
 	 */
 	if (head->total_size < sizeof(*head) ||
-			head->total_size > CBI_IMAGE_SIZE) {
+	    head->total_size > CBI_IMAGE_SIZE) {
 		CPRINTS("Bad size: %d", head->total_size);
 		return EC_ERROR_OVERFLOW;
 	}
 
 	/* Read the data */
 	if (cbi_config.drv->load(sizeof(*head), head->data,
-			head->total_size - sizeof(*head))) {
+				 head->total_size - sizeof(*head))) {
 		CPRINTS("Failed to read body");
 		return EC_ERROR_INVAL;
 	}
 
 	/* Check CRC. This supports new fields unknown to this parser. */
 	if (cbi_config.storage_type != CBI_STORAGE_TYPE_GPIO &&
-			cbi_crc8(head) != head->crc) {
+	    cbi_crc8(head) != head->crc) {
 		CPRINTS("Bad CRC");
 		return EC_ERROR_INVAL;
 	}
@@ -175,8 +175,8 @@ static int cbi_read(void)
 	return rv;
 }
 
-__attribute__((weak))
-int cbi_board_override(enum cbi_data_tag tag, uint8_t *buf, uint8_t *size)
+__attribute__((weak)) int cbi_board_override(enum cbi_data_tag tag,
+					     uint8_t *buf, uint8_t *size)
 {
 	return EC_SUCCESS;
 }
@@ -294,8 +294,7 @@ int cbi_get_ssfc(uint32_t *ssfc)
 {
 	uint8_t size = sizeof(*ssfc);
 
-	return cbi_get_board_info(CBI_TAG_SSFC, (uint8_t *)ssfc,
-				  &size);
+	return cbi_get_board_info(CBI_TAG_SSFC, (uint8_t *)ssfc, &size);
 }
 
 int cbi_get_pcb_supplier(uint32_t *pcb_supplier)
@@ -303,7 +302,7 @@ int cbi_get_pcb_supplier(uint32_t *pcb_supplier)
 	uint8_t size = sizeof(*pcb_supplier);
 
 	return cbi_get_board_info(CBI_TAG_PCB_SUPPLIER, (uint8_t *)pcb_supplier,
-			&size);
+				  &size);
 }
 
 int cbi_get_rework_id(uint64_t *id)
@@ -312,6 +311,14 @@ int cbi_get_rework_id(uint64_t *id)
 	return cbi_get_board_info(CBI_TAG_REWORK_ID, (uint8_t *)id, &size);
 }
 
+int cbi_get_factory_calibration_data(uint32_t *calibration_data)
+{
+	uint8_t size = sizeof(*calibration_data);
+
+	return cbi_get_board_info(CBI_TAG_FACTORY_CALIBRATION_DATA,
+				  (uint8_t *)calibration_data, &size);
+}
+
 static enum ec_status hc_cbi_get(struct host_cmd_handler_args *args)
 {
 	const struct __ec_align4 ec_params_get_cbi *p = args->params;
@@ -326,19 +333,16 @@ static enum ec_status hc_cbi_get(struct host_cmd_handler_args *args)
 	args->response_size = size;
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_GET_CROS_BOARD_INFO,
-		     hc_cbi_get,
-		     EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_GET_CROS_BOARD_INFO, hc_cbi_get, EC_VER_MASK(0));
 
-static enum ec_status common_cbi_set(const struct __ec_align4
-							ec_params_set_cbi * p)
+static enum ec_status
+common_cbi_set(const struct __ec_align4 ec_params_set_cbi *p)
 {
 	/*
 	 * If we ultimately cannot write to the flash, then fail early unless
 	 * we are explicitly trying to write to the in-memory CBI only
 	 */
-	if (cbi_config.drv->is_protected() &&
-	    !(p->flag & CBI_SET_NO_SYNC)) {
+	if (cbi_config.drv->is_protected() && !(p->flag & CBI_SET_NO_SYNC)) {
 		CPRINTS("Failed to write due to WP");
 		return EC_RES_ACCESS_DENIED;
 	}
@@ -386,7 +390,7 @@ static enum ec_status common_cbi_set(const struct __ec_align4
 
 static enum ec_status hc_cbi_set(struct host_cmd_handler_args *args)
 {
-	const struct __ec_align4 ec_params_set_cbi * p = args->params;
+	const struct __ec_align4 ec_params_set_cbi *p = args->params;
 
 	/* Given data size exceeds the packet size. */
 	if (args->params_size < sizeof(*p) + p->size)
@@ -394,12 +398,10 @@ static enum ec_status hc_cbi_set(struct host_cmd_handler_args *args)
 
 	return common_cbi_set(p);
 }
-DECLARE_HOST_COMMAND(EC_CMD_SET_CROS_BOARD_INFO,
-		     hc_cbi_set,
-		     EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_SET_CROS_BOARD_INFO, hc_cbi_set, EC_VER_MASK(0));
 
 #ifdef CONFIG_CMD_CBI
-static void print_tag(const char * const tag, int rv, const uint32_t *val)
+static void print_tag(const char *const tag, int rv, const uint32_t *val)
 {
 	ccprintf("%s", tag);
 	if (rv == EC_SUCCESS && val)
@@ -408,7 +410,7 @@ static void print_tag(const char * const tag, int rv, const uint32_t *val)
 		ccprintf(": (Error %d)\n", rv);
 }
 
-static void print_uint64_tag(const char * const tag, int rv,
+static void print_uint64_tag(const char *const tag, int rv,
 			     const uint64_t *lval)
 {
 	ccprintf("%s", tag);
@@ -429,7 +431,8 @@ static void dump_cbi(void)
 	cbi_read();
 
 	if (cbi_get_cache_status() != CBI_CACHE_STATUS_SYNCED) {
-		ccprintf("Cannot Read CBI (Error %d)\n", cbi_get_cache_status());
+		ccprintf("Cannot Read CBI (Error %d)\n",
+			 cbi_get_cache_status());
 		return;
 	}
 
@@ -450,12 +453,12 @@ static void dump_cbi(void)
  * Space for the set command (does not include data space) plus maximum
  * possible console input
  */
-static uint8_t buf[sizeof(struct ec_params_set_cbi) + \
-		       CONFIG_CONSOLE_INPUT_LINE_SIZE];
+static uint8_t
+	buf[sizeof(struct ec_params_set_cbi) + CONFIG_CONSOLE_INPUT_LINE_SIZE];
 
-static int cc_cbi(int argc, char **argv)
+static int cc_cbi(int argc, const char **argv)
 {
-	struct __ec_align4 ec_params_set_cbi * setter =
+	struct __ec_align4 ec_params_set_cbi *setter =
 		(struct __ec_align4 ec_params_set_cbi *)buf;
 	int last_arg;
 	char *e;
@@ -494,8 +497,9 @@ static int cc_cbi(int argc, char **argv)
 			if (setter->size < 1) {
 				ccprintf("Set size too small\n");
 				return EC_ERROR_PARAM4;
-			} else if ((setter->size > 8) || (setter->size > 4 &&
-				   setter->tag != CBI_TAG_REWORK_ID)) {
+			} else if ((setter->size > 8) ||
+				   (setter->size > 4 &&
+				    setter->tag != CBI_TAG_REWORK_ID)) {
 				ccprintf("Set size too large\n");
 				return EC_ERROR_PARAM4;
 			}
@@ -542,7 +546,8 @@ static int cc_cbi(int argc, char **argv)
 
 	return EC_ERROR_UNKNOWN;
 }
-DECLARE_CONSOLE_COMMAND(cbi, cc_cbi, "[set <tag> <value> <size> | "
+DECLARE_CONSOLE_COMMAND(cbi, cc_cbi,
+			"[set <tag> <value> <size> | "
 			"remove <tag>] [init | skip_write]",
 			"Print or change Cros Board Info from flash");
 #endif /* CONFIG_CMD_CBI */
diff --git a/common/cbi_eeprom.c b/common/cbi_eeprom.c
index ef20fdc7e2..da7d85f21b 100644
--- a/common/cbi_eeprom.c
+++ b/common/cbi_eeprom.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,20 +14,20 @@
 #include "util.h"
 #include "write_protect.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, "CBI " format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, "CBI " format, ##args)
 
 /*
  * We allow EEPROMs with page size of 8 or 16. Use 8 to be the most compatible.
  * This causes a little more overhead for writes, but we are not writing to the
  * EEPROM outside of the factory process.
  */
-#define EEPROM_PAGE_WRITE_SIZE	8
-#define EEPROM_PAGE_WRITE_MS	5
+#define EEPROM_PAGE_WRITE_SIZE 8
+#define EEPROM_PAGE_WRITE_MS 5
 
 static int eeprom_read(uint8_t offset, uint8_t *data, int len)
 {
-	return i2c_read_block(I2C_PORT_EEPROM, I2C_ADDR_EEPROM_FLAGS,
-			      offset, data, len);
+	return i2c_read_block(I2C_PORT_EEPROM, I2C_ADDR_EEPROM_FLAGS, offset,
+			      data, len);
 }
 
 static int eeprom_is_write_protected(void)
diff --git a/common/cbi_gpio.c b/common/cbi_gpio.c
index 7b9fb25ebb..09e1dd3a18 100644
--- a/common/cbi_gpio.c
+++ b/common/cbi_gpio.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,7 +11,7 @@
 #include "system.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, "CBI " format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, "CBI " format, ##args)
 
 static int cbi_gpio_read(uint8_t offset, uint8_t *data, int len)
 {
@@ -39,8 +39,8 @@ static int cbi_gpio_read(uint8_t offset, uint8_t *data, int len)
 	}
 
 	sku_id = system_get_sku_id();
-	rv = cbi_set_board_info(CBI_TAG_SKU_ID,
-				(uint8_t *)&sku_id, sizeof(int));
+	rv = cbi_set_board_info(CBI_TAG_SKU_ID, (uint8_t *)&sku_id,
+				sizeof(int));
 	if (rv) {
 		CPRINTS("Failed (%d) to set SKU_ID tag", rv);
 		err++;
diff --git a/common/cec.c b/common/cec.c
index 1bc3273c1d..4b15fc1799 100644
--- a/common/cec.c
+++ b/common/cec.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,8 +7,8 @@
 #include "console.h"
 #include "task.h"
 
-#define CPRINTF(format, args...) cprintf(CC_CEC, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CEC, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CEC, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CEC, format, ##args)
 
 /*
  * Mutex for the read-offset of the rx queue. Needed since the
@@ -75,7 +75,7 @@ int cec_rx_queue_push(struct cec_rx_queue *queue, const uint8_t *msg,
 	queue->buf[offset] = 0;
 	offset = (offset + 1) % CEC_RX_BUFFER_SIZE;
 
-	for (i = 0 ; i < msg_len; i++) {
+	for (i = 0; i < msg_len; i++) {
 		if (offset == queue->read_offset) {
 			/* Buffer full */
 			return EC_ERROR_OVERFLOW;
@@ -101,8 +101,7 @@ int cec_rx_queue_push(struct cec_rx_queue *queue, const uint8_t *msg,
 	return EC_SUCCESS;
 }
 
-int cec_rx_queue_pop(struct cec_rx_queue *queue, uint8_t *msg,
-		     uint8_t *msg_len)
+int cec_rx_queue_pop(struct cec_rx_queue *queue, uint8_t *msg, uint8_t *msg_len)
 {
 	int i;
 
@@ -126,9 +125,8 @@ int cec_rx_queue_pop(struct cec_rx_queue *queue, uint8_t *msg,
 	queue->read_offset = (queue->read_offset + 1) % CEC_RX_BUFFER_SIZE;
 	for (i = 0; i < *msg_len; i++) {
 		msg[i] = queue->buf[queue->read_offset];
-		queue->read_offset = (queue->read_offset + 1) %
-							CEC_RX_BUFFER_SIZE;
-
+		queue->read_offset =
+			(queue->read_offset + 1) % CEC_RX_BUFFER_SIZE;
 	}
 
 	mutex_unlock(&rx_queue_readoffset_mutex);
diff --git a/common/charge_manager.c b/common/charge_manager.c
index f8a08b7fa8..3e8b937e53 100644
--- a/common/charge_manager.c
+++ b/common/charge_manager.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,6 +6,7 @@
 #include "adc.h"
 #include "atomic.h"
 #include "battery.h"
+#include "builtin/assert.h"
 #include "charge_manager.h"
 #include "charge_ramp.h"
 #include "charge_state_v2.h"
@@ -30,13 +31,13 @@
 #error Mock defined HAS_MOCK_CHARGE_MANAGER
 #endif
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
 
 #define POWER(charge_port) ((charge_port.current) * (charge_port.voltage))
 
 /* Timeout for delayed override power swap, allow for 500ms extra */
-#define POWER_SWAP_TIMEOUT (PD_T_SRC_RECOVER_MAX + PD_T_SRC_TURN_ON + \
-			    PD_T_SAFE_0V + 500 * MSEC)
+#define POWER_SWAP_TIMEOUT \
+	(PD_T_SRC_RECOVER_MAX + PD_T_SRC_TURN_ON + PD_T_SAFE_0V + 500 * MSEC)
 
 /*
  * Default charge supplier priority
@@ -70,15 +71,13 @@ __overridable const int supplier_priority[] = {
 	[CHARGE_SUPPLIER_OTHER] = 4,
 	[CHARGE_SUPPLIER_VBUS] = 4,
 #endif
-#ifdef CONFIG_WIRELESS_CHARGER_P9221_R7
-	[CHARGE_SUPPLIER_WPC_BPP] = 5,
-	[CHARGE_SUPPLIER_WPC_EPP] = 5,
-	[CHARGE_SUPPLIER_WPC_GPP] = 5,
-#endif
 
 };
 BUILD_ASSERT(ARRAY_SIZE(supplier_priority) == CHARGE_SUPPLIER_COUNT);
 
+const char *charge_supplier_name[] = { CHARGE_SUPPLIER_NAME };
+BUILD_ASSERT(ARRAY_SIZE(charge_supplier_name) == CHARGE_SUPPLIER_COUNT);
+
 /* Keep track of available charge for each charge port. */
 static struct charge_port_info available_charge[CHARGE_SUPPLIER_COUNT]
 					       [CHARGE_PORT_COUNT];
@@ -150,7 +149,7 @@ enum charge_manager_change_type {
 	CHANGE_DUALROLE,
 };
 
-static int is_pd_port(int port)
+int is_pd_port(int port)
 {
 	return port >= 0 && port < board_get_usb_pd_port_count();
 }
@@ -204,9 +203,8 @@ static int is_connected(int port)
  */
 static int charge_manager_spoof_dualrole_capability(void)
 {
-	return (system_get_image_copy() == EC_IMAGE_RO &&
-		system_is_locked()) || !left_safe_mode;
-
+	return (system_get_image_copy() == EC_IMAGE_RO && system_is_locked()) ||
+	       !left_safe_mode;
 }
 #endif /* !CONFIG_CHARGE_MANAGER_DRP_CHARGING */
 
@@ -257,9 +255,9 @@ static int charge_manager_is_seeded(void)
 			if (!is_valid_port(j))
 				continue;
 			if (available_charge[i][j].current ==
-			    CHARGE_CURRENT_UNINITIALIZED ||
+				    CHARGE_CURRENT_UNINITIALIZED ||
 			    available_charge[i][j].voltage ==
-			    CHARGE_VOLTAGE_UNINITIALIZED)
+				    CHARGE_VOLTAGE_UNINITIALIZED)
 				return 0;
 		}
 	}
@@ -340,8 +338,8 @@ static enum charge_supplier get_current_supplier(int port)
 
 	return supplier;
 }
-static enum usb_power_roles get_current_power_role(int port,
-		enum charge_supplier supplier)
+static enum usb_power_roles
+get_current_power_role(int port, enum charge_supplier supplier)
 {
 	enum usb_power_roles role;
 	if (charge_port == port)
@@ -397,30 +395,38 @@ static int get_vbus_voltage(int port, enum usb_power_roles current_role)
 
 int charge_manager_get_vbus_voltage(int port)
 {
-	return get_vbus_voltage(port, get_current_power_role(port,
-				get_current_supplier(port)));
+	return get_vbus_voltage(
+		port, get_current_power_role(port, get_current_supplier(port)));
 }
 
 #ifdef CONFIG_CMD_VBUS
-static int command_vbus(int argc, char **argv)
+static int command_vbus(int argc, const char **argv)
 {
 	/* port = -1 to print all the ports */
 	int port = -1;
+	int vbus, vsys;
 
 	if (argc == 2)
 		port = atoi(argv[1]);
 
-	for (int i = 0; i < board_get_usb_pd_port_count(); i++) {
-		if (port < 0 || i == port)
-			ccprintf("VBUS C%d = %d mV\n", i,
-				 charge_manager_get_vbus_voltage(i));
+	ccprintf("       VBUS     VSYS\n");
+	for (int i = 0; i < CHARGE_PORT_COUNT; i++) {
+		if (port < 0 || i == port) {
+			vbus = charge_manager_get_vbus_voltage(i);
+			if (charger_get_vsys_voltage(i, &vsys))
+				vsys = -1;
+			ccprintf("  P%d %6dmV ", i, vbus);
+			if (vsys >= 0)
+				ccprintf("%6dmV\n", vsys);
+			else
+				ccprintf("(unknown)\n");
+		}
 	}
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(vbus, command_vbus,
-			"[port]",
-			"VBUS of the given port");
+DECLARE_CONSOLE_COMMAND(vbus, command_vbus, "[port]",
+			"Print VBUS & VSYS of the given port");
 #endif
 
 /**
@@ -429,8 +435,9 @@ DECLARE_CONSOLE_COMMAND(vbus, command_vbus,
  * @param port	Charge port.
  * @param r	USB PD power info to be updated.
  */
-static void charge_manager_fill_power_info(int port,
-	struct ec_response_usb_pd_power_info *r)
+static void
+charge_manager_fill_power_info(int port,
+			       struct ec_response_usb_pd_power_info *r)
 {
 	enum charge_supplier sup = get_current_supplier(port);
 
@@ -461,6 +468,8 @@ static void charge_manager_fill_power_info(int port,
 		}
 	} else {
 		int use_ramp_current;
+		uint32_t max_mv, max_ma, pdo, unused;
+
 		switch (sup) {
 		case CHARGE_SUPPLIER_PD:
 			r->type = USB_CHG_TYPE_PD;
@@ -486,30 +495,32 @@ static void charge_manager_fill_power_info(int port,
 			r->type = USB_CHG_TYPE_VBUS;
 			break;
 #endif
-#ifdef CONFIG_WIRELESS_CHARGER_P9221_R7
-		/*
-		 * Todo:need kernel add wpc device node in power_supply
-		 * before that use USB_CHG_TYPE_PROPRIETARY to present WPC.
-		 */
-		case CHARGE_SUPPLIER_WPC_BPP:
-		case CHARGE_SUPPLIER_WPC_EPP:
-		case CHARGE_SUPPLIER_WPC_GPP:
-			r->type = USB_CHG_TYPE_PROPRIETARY;
-			break;
-#endif
 #if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
 		case CHARGE_SUPPLIER_DEDICATED:
 			r->type = USB_CHG_TYPE_DEDICATED;
 			break;
 #endif
 		default:
-#ifdef CONFIG_WIRELESS_CHARGER_P9221_R7
-			r->type = USB_CHG_TYPE_VBUS;
-#else
 			r->type = USB_CHG_TYPE_OTHER;
-#endif
 		}
-		r->meas.voltage_max = available_charge[sup][port].voltage;
+
+		if (IS_ENABLED(CONFIG_USB_PD_DPS) && dps_is_enabled() &&
+		    sup == CHARGE_SUPPLIER_PD) {
+			/*
+			 * Returns the maximum power the system can request when
+			 * DPS enabled. This is to prevent the system think it's
+			 * using a low power charger.
+			 */
+			pd_find_pdo_index(pd_get_src_cap_cnt(port),
+					  pd_get_src_caps(port),
+					  pd_get_max_voltage(), &pdo);
+			pd_extract_pdo_power(pdo, &max_ma, &max_mv, &unused);
+		} else {
+			max_mv = available_charge[sup][port].voltage;
+			max_ma = available_charge[sup][port].current;
+		}
+
+		r->meas.voltage_max = max_mv;
 
 		/*
 		 * Report unknown charger CHARGE_DETECT_DELAY after supplier
@@ -523,15 +534,15 @@ static void charge_manager_fill_power_info(int port,
 		 * lose power again).
 		 */
 #ifdef CONFIG_BATTERY
-		if (get_time().val < registration_time[port].val +
-				     CHARGE_DETECT_DELAY)
+		if (get_time().val <
+		    registration_time[port].val + CHARGE_DETECT_DELAY)
 			r->type = USB_CHG_TYPE_UNKNOWN;
 #endif
 
 #if defined(HAS_TASK_CHG_RAMP) || defined(CONFIG_CHARGE_RAMP_HW)
 		/* Read ramped current if active charging port */
-		use_ramp_current =
-			(charge_port == port) && chg_ramp_allowed(port, sup);
+		use_ramp_current = (charge_port == port) &&
+				   chg_ramp_allowed(port, sup);
 #else
 		use_ramp_current = 0;
 #endif
@@ -548,17 +559,15 @@ static void charge_manager_fill_power_info(int port,
 			 * If ramp is not allowed, max current is just the
 			 * available charge current.
 			 */
-			r->meas.current_max = chg_ramp_is_stable() ?
-				r->meas.current_lim : chg_ramp_max(port, sup,
-					available_charge[sup][port].current);
+			r->meas.current_max =
+				chg_ramp_is_stable() ?
+					r->meas.current_lim :
+					chg_ramp_max(port, sup, max_ma);
 
-			r->max_power =
-				r->meas.current_max * r->meas.voltage_max;
 		} else {
-			r->meas.current_max = r->meas.current_lim =
-				available_charge[sup][port].current;
-			r->max_power = POWER(available_charge[sup][port]);
+			r->meas.current_max = r->meas.current_lim = max_ma;
 		}
+		r->max_power = r->meas.current_max * r->meas.voltage_max;
 
 		r->meas.voltage_now = get_vbus_voltage(port, r->role);
 	}
@@ -588,8 +597,8 @@ void charge_manager_save_log(int port)
 		 (pinfo.dualrole ? CHARGE_FLAGS_DUAL_ROLE : 0);
 
 	pd_log_event(PD_EVENT_MCU_CHARGE,
-		     PD_LOG_PORT_SIZE(port, sizeof(pinfo.meas)),
-		     flags, &pinfo.meas);
+		     PD_LOG_PORT_SIZE(port, sizeof(pinfo.meas)), flags,
+		     &pinfo.meas);
 }
 #endif /* CONFIG_USB_PD_LOGGING */
 
@@ -650,7 +659,6 @@ static void charge_manager_get_best_charge_port(int *new_port,
 
 	/* Skip port selection on OVERRIDE_DONT_CHARGE. */
 	if (override_port != OVERRIDE_DONT_CHARGE) {
-
 		/*
 		 * Charge supplier selection logic:
 		 * 1. Prefer DPS charge port.
@@ -680,8 +688,7 @@ static void charge_manager_get_best_charge_port(int *new_port,
 				 * charge on another override port.
 				 */
 				if (override_port != OVERRIDE_OFF &&
-				    override_port == port &&
-				    override_port != j)
+				    override_port == port && override_port != j)
 					continue;
 
 #ifndef CONFIG_CHARGE_MANAGER_DRP_CHARGING
@@ -706,31 +713,36 @@ static void charge_manager_get_best_charge_port(int *new_port,
 					supplier = i;
 					port = j;
 					break;
-				/* Select if no supplier chosen yet. */
+					/* Select if no supplier chosen yet. */
 				} else if (supplier == CHARGE_SUPPLIER_NONE ||
-				/* ..or if supplier priority is higher. */
-				    supplier_priority[i] <
-				    supplier_priority[supplier] ||
-				/* ..or if this is our override port. */
-				   (j == override_port &&
-				    port != override_port) ||
-				/* ..or if priority is tied and.. */
-				   (supplier_priority[i] ==
-				    supplier_priority[supplier] &&
-				/* candidate port can supply more power or.. */
-				   (candidate_port_power > best_port_power ||
-				/*
-				 * candidate port is the active port and can
-				 * supply the same amount of power.
-				 */
-				   (candidate_port_power == best_port_power &&
-				    charge_port == j)))) {
+					   /* ..or if supplier priority is
+					      higher. */
+					   supplier_priority[i] <
+						   supplier_priority[supplier] ||
+					   /* ..or if this is our override port.
+					    */
+					   (j == override_port &&
+					    port != override_port) ||
+					   /* ..or if priority is tied and.. */
+					   (supplier_priority[i] ==
+						    supplier_priority[supplier] &&
+					    /* candidate port can supply more
+					       power or.. */
+					    (candidate_port_power >
+						     best_port_power ||
+					     /*
+					      * candidate port is the active
+					      * port and can supply the same
+					      * amount of power.
+					      */
+					     (candidate_port_power ==
+						      best_port_power &&
+					      charge_port == j)))) {
 					supplier = i;
 					port = j;
 					best_port_power = candidate_port_power;
 				}
 			}
-
 	}
 
 #ifdef CONFIG_BATTERY
@@ -738,8 +750,7 @@ static void charge_manager_get_best_charge_port(int *new_port,
 	 * if no battery present then retain same charge port
 	 * and charge supplier to avoid the port switching
 	 */
-	if (charge_port != CHARGE_SUPPLIER_NONE &&
-	    charge_port != port &&
+	if (charge_port != CHARGE_SUPPLIER_NONE && charge_port != port &&
 	    (battery_is_present() == BP_NO ||
 	     (battery_is_present() == BP_YES &&
 	      battery_is_cut_off() != BATTERY_CUTOFF_STATE_NORMAL))) {
@@ -782,9 +793,8 @@ static void charge_manager_refresh(void)
 		 * the port, for example, if the port has become a charge
 		 * source.
 		 */
-		if (active_charge_port_initialized &&
-		     new_port == charge_port &&
-		     new_supplier == charge_supplier)
+		if (active_charge_port_initialized && new_port == charge_port &&
+		    new_supplier == charge_supplier)
 			break;
 
 		/*
@@ -844,8 +854,8 @@ static void charge_manager_refresh(void)
 		/* Enforce port charge ceiling. */
 		ceil = charge_manager_get_ceil(new_port);
 		if (left_safe_mode && ceil != CHARGE_CEIL_NONE)
-			new_charge_current = MIN(ceil,
-						 new_charge_current_uncapped);
+			new_charge_current =
+				MIN(ceil, new_charge_current_uncapped);
 		else
 			new_charge_current = new_charge_current_uncapped;
 
@@ -866,19 +876,19 @@ static void charge_manager_refresh(void)
 	if (new_port != charge_port || new_charge_current != charge_current ||
 	    new_supplier != charge_supplier) {
 #ifdef HAS_TASK_CHG_RAMP
-		chg_ramp_charge_supplier_change(
-				new_port, new_supplier, new_charge_current,
-				registration_time[new_port],
-				new_charge_voltage);
+		chg_ramp_charge_supplier_change(new_port, new_supplier,
+						new_charge_current,
+						registration_time[new_port],
+						new_charge_voltage);
 #else
 #ifdef CONFIG_CHARGE_RAMP_HW
 		/* Enable or disable charge ramp */
 		charger_set_hw_ramp(chg_ramp_allowed(new_port, new_supplier));
 #endif
 		board_set_charge_limit(new_port, new_supplier,
-					new_charge_current,
-					new_charge_current_uncapped,
-					new_charge_voltage);
+				       new_charge_current,
+				       new_charge_current_uncapped,
+				       new_charge_voltage);
 #endif /* HAS_TASK_CHG_RAMP */
 
 		power_changed = 1;
@@ -946,9 +956,9 @@ static void charge_manager_refresh(void)
 	if (is_pd_port(updated_new_port)) {
 		/* Check if we can get requested voltage/current */
 		if ((IS_ENABLED(CONFIG_USB_PD_TCPMV1) &&
-		    IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE)) ||
+		     IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE)) ||
 		    (IS_ENABLED(CONFIG_USB_PD_TCPMV2) &&
-		    IS_ENABLED(CONFIG_USB_PE_SM))) {
+		     IS_ENABLED(CONFIG_USB_PE_SM))) {
 			uint32_t pdo;
 			uint32_t max_voltage;
 			uint32_t max_current;
@@ -959,9 +969,9 @@ static void charge_manager_refresh(void)
 			 * than requested. If yes, send new power request
 			 */
 			if (pd_get_requested_voltage(updated_new_port) !=
-			    charge_voltage ||
+				    charge_voltage ||
 			    pd_get_requested_current(updated_new_port) !=
-			    charge_current_uncapped)
+				    charge_current_uncapped)
 				new_req = true;
 
 			if (IS_ENABLED(CONFIG_USB_PD_DPS) && dps_is_enabled()) {
@@ -996,9 +1006,11 @@ static void charge_manager_refresh(void)
 	if (is_pd_port(updated_old_port))
 		pd_set_new_power_request(updated_old_port);
 
-	if (power_changed)
+	if (power_changed) {
+		hook_notify(HOOK_POWER_SUPPLY_CHANGE);
 		/* notify host of power info change */
 		pd_send_host_event(PD_EVENT_POWER_CHANGE);
+	}
 }
 DECLARE_DEFERRED(charge_manager_refresh);
 
@@ -1031,8 +1043,7 @@ DECLARE_DEFERRED(charger_detect_debounced);
  * @param charge		Charge port current / voltage.
  */
 static void charge_manager_make_change(enum charge_manager_change_type change,
-				       int supplier,
-				       int port,
+				       int supplier, int port,
 				       const struct charge_port_info *charge)
 {
 	int i;
@@ -1048,9 +1059,8 @@ static void charge_manager_make_change(enum charge_manager_change_type change,
 	case CHANGE_CHARGE:
 		/* Ignore changes where charge is identical */
 		if (available_charge[supplier][port].current ==
-		    charge->current &&
-		    available_charge[supplier][port].voltage ==
-		    charge->voltage)
+			    charge->current &&
+		    available_charge[supplier][port].voltage == charge->voltage)
 			return;
 		if (charge->current > 0 &&
 		    available_charge[supplier][port].current == 0)
@@ -1084,12 +1094,13 @@ static void charge_manager_make_change(enum charge_manager_change_type change,
 	}
 
 	/* Remove override when a charger is plugged */
-	if (clear_override && override_port != port
+	if (clear_override &&
+	    override_port != port
 #ifndef CONFIG_CHARGE_MANAGER_DRP_CHARGING
 	    /* only remove override when it's a dedicated charger */
 	    && dualrole_capability[port] == CAP_DEDICATED
 #endif
-	    ) {
+	) {
 		override_port = OVERRIDE_OFF;
 		if (delayed_override_port != OVERRIDE_OFF) {
 			delayed_override_port = OVERRIDE_OFF;
@@ -1117,7 +1128,7 @@ static void charge_manager_make_change(enum charge_manager_change_type change,
 		/*
 		 * If we have a charge on our delayed override port within
 		 * the deadline, make it our override port.
-		*/
+		 */
 		if (port == delayed_override_port && charge->current > 0 &&
 		    is_sink(delayed_override_port) &&
 		    get_time().val < delayed_override_deadline.val) {
@@ -1202,11 +1213,10 @@ void typec_set_input_current_limit(int port, typec_current_t max_ma,
 						     NULL);
 }
 
-void charge_manager_update_charge(int supplier,
-				  int port,
+void charge_manager_update_charge(int supplier, int port,
 				  const struct charge_port_info *charge)
 {
-	struct charge_port_info zero = {0};
+	struct charge_port_info zero = { 0 };
 	if (!charge)
 		charge = &zero;
 	charge_manager_make_change(CHANGE_CHARGE, supplier, port, charge);
@@ -1230,6 +1240,21 @@ void charge_manager_leave_safe_mode(void)
 	if (left_safe_mode)
 		return;
 
+	/*
+	 * Sometimes the fuel gauge will report that it has
+	 * sufficient state of charge and remaining capacity,
+	 * but in actuality it doesn't.  When the EC sees that
+	 * information, it trusts it and leaves charge manager
+	 * safe mode.  Doing so will allow CHARGE_PORT_NONE to
+	 * be selected, thereby cutting off the input FETs.
+	 * When the battery cannot provide the charge it claims,
+	 * the system loses power, shuts down, and the battery
+	 * is not charged even though the charger is plugged in.
+	 * By waiting 500ms, we can avoid the selection of
+	 * CHARGE_PORT_NONE around init time and not cut off the
+	 * input FETs.
+	 */
+	msleep(500);
 	CPRINTS("%s()", __func__);
 	cflush();
 	left_safe_mode = 1;
@@ -1288,8 +1313,8 @@ int charge_manager_set_override(int port)
 		if (override_port != port) {
 			override_port = port;
 			if (charge_manager_is_seeded())
-				hook_call_deferred(
-					&charge_manager_refresh_data, 0);
+				hook_call_deferred(&charge_manager_refresh_data,
+						   0);
 		}
 	}
 	/*
@@ -1297,13 +1322,13 @@ int charge_manager_set_override(int port)
 	 * power swap and set the delayed override for swap completion.
 	 */
 	else if (!is_sink(port) && dualrole_capability[port] == CAP_DUALROLE) {
-		delayed_override_deadline.val = get_time().val +
-						POWER_SWAP_TIMEOUT;
+		delayed_override_deadline.val =
+			get_time().val + POWER_SWAP_TIMEOUT;
 		delayed_override_port = port;
 		hook_call_deferred(&charge_override_timeout_data,
 				   POWER_SWAP_TIMEOUT);
 		pd_request_power_swap(port);
-	/* Can't charge from requested port -- return error. */
+		/* Can't charge from requested port -- return error. */
 	} else
 		retval = EC_ERROR_INVAL;
 
@@ -1361,7 +1386,7 @@ int charge_manager_get_power_limit_uw(void)
 
 /* Bitmap of ports used as power source */
 static volatile uint32_t source_port_bitmap;
-BUILD_ASSERT(sizeof(source_port_bitmap)*8 >= CONFIG_USB_PD_PORT_MAX_COUNT);
+BUILD_ASSERT(sizeof(source_port_bitmap) * 8 >= CONFIG_USB_PD_PORT_MAX_COUNT);
 
 static inline int has_other_active_source(int port)
 {
@@ -1392,7 +1417,7 @@ static int can_supply_max_current(int port)
 		if (p == port)
 			continue;
 		if (source_port_rp[p] ==
-				CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT)
+		    CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT)
 			return 0;
 	}
 	return 1;
@@ -1418,8 +1443,8 @@ void charge_manager_source_port(int port, int enable)
 	/* Set port limit according to policy */
 	for (p = 0; p < board_get_usb_pd_port_count(); p++) {
 		rp = can_supply_max_current(p) ?
-				CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT :
-				CONFIG_USB_PD_PULLUP;
+			     CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT :
+			     CONFIG_USB_PD_PULLUP;
 		source_port_rp[p] = rp;
 
 #ifdef CONFIG_USB_PD_LOGGING
@@ -1471,8 +1496,7 @@ static enum ec_status hc_pd_power_info(struct host_cmd_handler_args *args)
 	args->response_size = sizeof(*r);
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_USB_PD_POWER_INFO,
-		     hc_pd_power_info,
+DECLARE_HOST_COMMAND(EC_CMD_USB_PD_POWER_INFO, hc_pd_power_info,
 		     EC_VER_MASK(0));
 
 static enum ec_status hc_charge_port_count(struct host_cmd_handler_args *args)
@@ -1484,8 +1508,7 @@ static enum ec_status hc_charge_port_count(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_CHARGE_PORT_COUNT,
-		     hc_charge_port_count,
+DECLARE_HOST_COMMAND(EC_CMD_CHARGE_PORT_COUNT, hc_charge_port_count,
 		     EC_VER_MASK(0));
 
 static enum ec_status
@@ -1499,15 +1522,15 @@ hc_charge_port_override(struct host_cmd_handler_args *args)
 		return EC_RES_INVALID_PARAM;
 
 	return charge_manager_set_override(override_port) == EC_SUCCESS ?
-		EC_RES_SUCCESS : EC_RES_ERROR;
+		       EC_RES_SUCCESS :
+		       EC_RES_ERROR;
 }
-DECLARE_HOST_COMMAND(EC_CMD_PD_CHARGE_PORT_OVERRIDE,
-		     hc_charge_port_override,
+DECLARE_HOST_COMMAND(EC_CMD_PD_CHARGE_PORT_OVERRIDE, hc_charge_port_override,
 		     EC_VER_MASK(0));
 
 #if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
-static enum ec_status hc_override_dedicated_charger_limit(
-		struct host_cmd_handler_args *args)
+static enum ec_status
+hc_override_dedicated_charger_limit(struct host_cmd_handler_args *args)
 {
 	const struct ec_params_dedicated_charger_limit *p = args->params;
 	struct charge_port_info ci = {
@@ -1528,11 +1551,10 @@ static enum ec_status hc_override_dedicated_charger_limit(
 	return EC_RES_SUCCESS;
 }
 DECLARE_HOST_COMMAND(EC_CMD_OVERRIDE_DEDICATED_CHARGER_LIMIT,
-		     hc_override_dedicated_charger_limit,
-		     EC_VER_MASK(0));
+		     hc_override_dedicated_charger_limit, EC_VER_MASK(0));
 #endif
 
-static int command_charge_port_override(int argc, char **argv)
+static int command_charge_port_override(int argc, const char **argv)
 {
 	int port = OVERRIDE_OFF;
 	int ret = EC_SUCCESS;
@@ -1546,12 +1568,12 @@ static int command_charge_port_override(int argc, char **argv)
 		ret = charge_manager_set_override(port);
 	}
 
-	ccprintf("Override: %d\n", (argc >= 2 && ret == EC_SUCCESS) ?
-					port : override_port);
+	ccprintf("Override: %d\n",
+		 (argc >= 2 && ret == EC_SUCCESS) ? port : override_port);
 	return ret;
 }
-DECLARE_CONSOLE_COMMAND(chgoverride, command_charge_port_override,
-	"[port | -1 | -2]",
+DECLARE_CONSOLE_COMMAND(
+	chgoverride, command_charge_port_override, "[port | -1 | -2]",
 	"Force charging from a given port (-1 = off, -2 = disable charging)");
 
 #ifdef CONFIG_CHARGE_MANAGER_EXTERNAL_POWER_LIMIT
@@ -1588,16 +1610,14 @@ hc_external_power_limit(struct host_cmd_handler_args *args)
 {
 	const struct ec_params_external_power_limit_v1 *p = args->params;
 
-	charge_manager_set_external_power_limit(p->current_lim,
-						p->voltage_lim);
+	charge_manager_set_external_power_limit(p->current_lim, p->voltage_lim);
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_EXTERNAL_POWER_LIMIT,
-		     hc_external_power_limit,
+DECLARE_HOST_COMMAND(EC_CMD_EXTERNAL_POWER_LIMIT, hc_external_power_limit,
 		     EC_VER_MASK(1));
 
-static int command_external_power_limit(int argc, char **argv)
+static int command_external_power_limit(int argc, const char **argv)
 {
 	int max_current;
 	int max_voltage;
@@ -1623,41 +1643,63 @@ static int command_external_power_limit(int argc, char **argv)
 	return EC_SUCCESS;
 }
 DECLARE_CONSOLE_COMMAND(chglim, command_external_power_limit,
-	"[max_current (mA)] [max_voltage (mV)]",
-	"Set max charger current / voltage");
+			"[max_current (mA)] [max_voltage (mV)]",
+			"Set max charger current / voltage");
 #endif /* CONFIG_CHARGE_MANAGER_EXTERNAL_POWER_LIMIT */
 
 #ifdef CONFIG_CMD_CHARGE_SUPPLIER_INFO
-static int charge_supplier_info(int argc, char **argv)
+static int charge_supplier_info(int argc, const char **argv)
 {
-	ccprintf("port=%d, type=%d, cur=%dmA, vtg=%dmV, lsm=%d\n",
-			charge_manager_get_active_charge_port(),
-			charge_supplier,
-			charge_current,
-			charge_voltage,
-			left_safe_mode);
-
+	int p, s;
+	int port_printed;
+
+	ccprintf("\n");
+	ccprintf("Port --Supplier-- Prio -Available Power-\n");
+	for (p = 0; p < CHARGE_PORT_COUNT; p++) {
+		port_printed = 0;
+		for (s = 0; s < CHARGE_SUPPLIER_COUNT; s++) {
+			if (available_charge[s][p].current == 0 &&
+			    available_charge[s][p].voltage == 0)
+				continue;
+			if (charge_manager_get_active_charge_port() == p &&
+			    charge_manager_get_supplier() == s)
+				ccprintf("*");
+			else
+				ccprintf(" ");
+			if (!port_printed) {
+				ccprintf("P%d  ", p);
+				port_printed = 1;
+			} else {
+				ccprintf("    ");
+			}
+			ccprintf("%-10s  %4d  %5dmA %5dmV\n",
+				 charge_supplier_name[s], supplier_priority[s],
+				 available_charge[s][p].current,
+				 available_charge[s][p].voltage);
+		}
+	}
+	ccprintf("\n");
+	ccprintf("  %s safe mode\n", left_safe_mode ? "Left" : "In");
+	ccprintf("  Override port = P%d\n", charge_manager_get_override());
+	ccprintf("\n");
 	return 0;
 }
-DECLARE_CONSOLE_COMMAND(chgsup, charge_supplier_info,
-			NULL, "print chg supplier info");
+DECLARE_CONSOLE_COMMAND(chgsup, charge_supplier_info, NULL,
+			"print chg supplier info");
 #endif
 
-__overridable
-int board_charge_port_is_sink(int port)
+__overridable int board_charge_port_is_sink(int port)
 {
 	return 1;
 }
 
-__overridable
-int board_charge_port_is_connected(int port)
+__overridable int board_charge_port_is_connected(int port)
 {
 	return 1;
 }
 
-__overridable
-void board_fill_source_power_info(int port,
-				  struct ec_response_usb_pd_power_info *r)
+__overridable void
+board_fill_source_power_info(int port, struct ec_response_usb_pd_power_info *r)
 {
 	r->meas.voltage_now = 0;
 	r->meas.voltage_max = 0;
diff --git a/common/charge_ramp.c b/common/charge_ramp.c
index 32e0d21ddb..2c84087e21 100644
--- a/common/charge_ramp.c
+++ b/common/charge_ramp.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -41,7 +41,7 @@ test_mockable int chg_ramp_allowed(int port, int supplier)
 	case CHARGE_SUPPLIER_PD:
 	case CHARGE_SUPPLIER_TYPEC:
 		return 0;
-	/* default: fall through */
+		/* default: fall through */
 	}
 
 	/* Otherwise ask the BC1.2 detect module */
@@ -59,7 +59,7 @@ test_mockable int chg_ramp_max(int port, int supplier, int sup_curr)
 		 * we may brownout the systems they are connected to.
 		 */
 		return sup_curr;
-	/* default: fall through */
+		/* default: fall through */
 	}
 
 	/* Otherwise ask the BC1.2 detect module */
diff --git a/common/charge_ramp_sw.c b/common/charge_ramp_sw.c
index bfd6db057b..4c09a94a8d 100644
--- a/common/charge_ramp_sw.c
+++ b/common/charge_ramp_sw.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,30 +16,30 @@
 #include "usb_pd.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
 
 /* Number of times to ramp current searching for limit before stable charging */
-#define RAMP_COUNT          3
+#define RAMP_COUNT 3
 
 /* Maximum allowable time charger can be unplugged to be considered an OCP */
 #define OC_RECOVER_MAX_TIME (SECOND)
 
 /* Delay for running state machine when board is not consuming full current */
-#define CURRENT_DRAW_DELAY  (5*SECOND)
+#define CURRENT_DRAW_DELAY (5 * SECOND)
 
 /* Current ramp increment */
-#define RAMP_CURR_INCR_MA   64
-#define RAMP_CURR_DELAY     (500*MSEC)
-#define RAMP_CURR_START_MA  500
+#define RAMP_CURR_INCR_MA 64
+#define RAMP_CURR_DELAY (500 * MSEC)
+#define RAMP_CURR_START_MA 500
 
 /* How much to backoff the input current limit when limit has been found */
-#define RAMP_ICL_BACKOFF    (2*RAMP_CURR_INCR_MA)
+#define RAMP_ICL_BACKOFF (2 * RAMP_CURR_INCR_MA)
 
 /* Interval at which VBUS voltage is monitored in stable state */
 #define STABLE_VBUS_MONITOR_INTERVAL (SECOND)
 
 /* Time to delay for stablizing the charging current */
-#define STABLIZE_DELAY (5*SECOND)
+#define STABLIZE_DELAY (5 * SECOND)
 
 enum chg_ramp_state {
 	CHG_RAMP_DISCONNECTED,
@@ -78,14 +78,13 @@ static int max_icl;
 static int min_icl;
 
 void chg_ramp_charge_supplier_change(int port, int supplier, int current,
-				timestamp_t registration_time, int voltage)
+				     timestamp_t registration_time, int voltage)
 {
 	/*
 	 * If the last active port was a valid port and the port
 	 * has changed, then this may have been an over-current.
 	 */
-	if (active_port != CHARGE_PORT_NONE &&
-	    port != active_port) {
+	if (active_port != CHARGE_PORT_NONE && port != active_port) {
 		if (oc_info_idx[active_port] == RAMP_COUNT - 1)
 			oc_info_idx[active_port] = 0;
 		else
@@ -111,7 +110,8 @@ void chg_ramp_charge_supplier_change(int port, int supplier, int current,
 	reg_time = registration_time;
 	if (ramp_st != CHG_RAMP_STABILIZE) {
 		ramp_st = (active_port == CHARGE_PORT_NONE) ?
-			  CHG_RAMP_DISCONNECTED : CHG_RAMP_CHARGE_DETECT_DELAY;
+				  CHG_RAMP_DISCONNECTED :
+				  CHG_RAMP_CHARGE_DETECT_DELAY;
 		CPRINTS("Ramp reset: st%d", ramp_st);
 		task_wake(TASK_ID_CHG_RAMP);
 	}
@@ -153,7 +153,7 @@ void chg_ramp_task(void *u)
 	int last_active_port = CHARGE_PORT_NONE;
 
 	enum chg_ramp_state ramp_st_prev = CHG_RAMP_DISCONNECTED,
-				   ramp_st_new = CHG_RAMP_DISCONNECTED;
+			    ramp_st_new = CHG_RAMP_DISCONNECTED;
 	int active_icl_new;
 
 	/* Clear last OCP supplier to guarantee we ramp on first connect */
@@ -190,15 +190,15 @@ void chg_ramp_task(void *u)
 				last_active_port = active_port;
 				if (reg_time.val <
 				    ACTIVE_OC_INFO.ts.val +
-				    OC_RECOVER_MAX_TIME) {
+					    OC_RECOVER_MAX_TIME) {
 					ACTIVE_OC_INFO.oc_detected = 1;
 				} else {
 					for (i = 0; i < RAMP_COUNT; ++i)
-						oc_info[active_port][i].
-							oc_detected = 0;
+						oc_info[active_port][i]
+							.oc_detected = 0;
 				}
-				detect_end_time_us = get_time().val +
-						     CHARGE_DETECT_DELAY;
+				detect_end_time_us =
+					get_time().val + CHARGE_DETECT_DELAY;
 				task_wait_time = CHARGE_DETECT_DELAY;
 				break;
 			}
@@ -246,8 +246,8 @@ void chg_ramp_task(void *u)
 
 			if (i == RAMP_COUNT) {
 				/* Found OC threshold! */
-				active_icl_new = ACTIVE_OC_INFO.icl -
-						 RAMP_ICL_BACKOFF;
+				active_icl_new =
+					ACTIVE_OC_INFO.icl - RAMP_ICL_BACKOFF;
 				ramp_st_new = CHG_RAMP_STABLE;
 			} else {
 				/*
@@ -272,8 +272,8 @@ void chg_ramp_task(void *u)
 			if (board_is_vbus_too_low(active_port,
 						  CHG_RAMP_VBUS_RAMPING)) {
 				CPRINTS("VBUS low");
-				active_icl_new = MAX(min_icl, active_icl -
-							      RAMP_ICL_BACKOFF);
+				active_icl_new = MAX(
+					min_icl, active_icl - RAMP_ICL_BACKOFF);
 				ramp_st_new = CHG_RAMP_STABILIZE;
 				task_wait_time = STABLIZE_DELAY;
 				stablize_port = active_port;
@@ -300,8 +300,8 @@ void chg_ramp_task(void *u)
 			}
 
 			ramp_st_new = active_port == CHARGE_PORT_NONE ?
-				      CHG_RAMP_DISCONNECTED :
-				      CHG_RAMP_CHARGE_DETECT_DELAY;
+					      CHG_RAMP_DISCONNECTED :
+					      CHG_RAMP_CHARGE_DETECT_DELAY;
 			break;
 		case CHG_RAMP_STABLE:
 			/* Maintain input current limit */
@@ -320,7 +320,7 @@ void chg_ramp_task(void *u)
 						  CHG_RAMP_VBUS_STABLE)) {
 				CPRINTS("VBUS low; Re-ramp");
 				max_icl = MAX(min_icl,
-						max_icl - RAMP_ICL_BACKOFF);
+					      max_icl - RAMP_ICL_BACKOFF);
 				active_icl_new = min_icl;
 				ramp_st_new = CHG_RAMP_RAMP;
 			}
@@ -334,9 +334,9 @@ void chg_ramp_task(void *u)
 
 		/* Skip setting limit if status is stable twice in a row */
 		if (ramp_st_prev != CHG_RAMP_STABLE ||
-				ramp_st != CHG_RAMP_STABLE) {
-			CPRINTS("Ramp p%d st%d %dmA %dmA",
-				active_port, ramp_st, min_icl, active_icl);
+		    ramp_st != CHG_RAMP_STABLE) {
+			CPRINTS("Ramp p%d st%d %dmA %dmA", active_port, ramp_st,
+				min_icl, active_icl);
 			/* Set the input current limit */
 			lim = chg_ramp_get_current_limit();
 			board_set_charge_limit(active_port, active_sup, lim,
@@ -356,13 +356,13 @@ void chg_ramp_task(void *u)
 }
 
 #ifdef CONFIG_CMD_CHGRAMP
-static int command_chgramp(int argc, char **argv)
+static int command_chgramp(int argc, const char **argv)
 {
 	int i;
 	int port;
 
-	ccprintf("Chg Ramp:\nState: %d\nMin ICL: %d\nActive ICL: %d\n",
-		 ramp_st, min_icl, active_icl);
+	ccprintf("Chg Ramp:\nState: %d\nMin ICL: %d\nActive ICL: %d\n", ramp_st,
+		 min_icl, active_icl);
 
 	for (port = 0; port < board_get_usb_pd_port_count(); port++) {
 		ccprintf("Port %d:\n", port);
@@ -377,7 +377,6 @@ static int command_chgramp(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(chgramp, command_chgramp,
-	"",
-	"Dump charge ramp state info");
+DECLARE_CONSOLE_COMMAND(chgramp, command_chgramp, "",
+			"Dump charge ramp state info");
 #endif
diff --git a/common/charge_state_v2.c b/common/charge_state_v2.c
index f3dc811eef..728606ef8a 100644
--- a/common/charge_state_v2.c
+++ b/common/charge_state_v2.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -7,6 +7,7 @@
 
 #include "battery.h"
 #include "battery_smart.h"
+#include "builtin/assert.h"
 #include "charge_manager.h"
 #include "charger_profile_override.h"
 #include "charge_state.h"
@@ -35,8 +36,8 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CHARGER, outstr)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
 
 /* Extra debugging prints when allocating power between lid and base. */
 #undef CHARGE_ALLOCATE_EXTRA_DEBUG
@@ -87,8 +88,8 @@ static int prev_ac, prev_charge, prev_full, prev_disp_charge;
 static enum battery_present prev_bp;
 static int is_full; /* battery not accepting current */
 static enum ec_charge_control_mode chg_ctl_mode;
-static int manual_voltage;  /* Manual voltage override (-1 = no override) */
-static int manual_current;  /* Manual current override (-1 = no override) */
+static int manual_voltage; /* Manual voltage override (-1 = no override) */
+static int manual_current; /* Manual current override (-1 = no override) */
 static unsigned int user_current_limit = -1U;
 test_export_static timestamp_t shutdown_target_time;
 static bool is_charging_progress_displayed;
@@ -155,18 +156,10 @@ static int battery_was_removed;
 static int problems_exist;
 static int debugging;
 
-
-static const char * const prob_text[] = {
-	"static update",
-	"set voltage",
-	"set current",
-	"set mode",
-	"set input current",
-	"post init",
-	"chg params",
-	"batt params",
-	"custom profile",
-	"cfg secondary chg"
+static const char *const prob_text[] = {
+	"static update",     "set voltage",	 "set current", "set mode",
+	"set input current", "post init",	 "chg params",	"batt params",
+	"custom profile",    "cfg secondary chg"
 };
 BUILD_ASSERT(ARRAY_SIZE(prob_text) == NUM_PROBLEM_TYPES);
 
@@ -184,7 +177,7 @@ void charge_problem(enum problem_type p, int v)
 		t_now = get_time();
 		t_diff.val = t_now.val - last_prob_time[p].val;
 		CPRINTS("charge problem: %s, 0x%x -> 0x%x after %.6" PRId64 "s",
-			 prob_text[p], last_prob_val[p], v, t_diff.val);
+			prob_text[p], last_prob_val[p], v, t_diff.val);
 		last_prob_val[p] = v;
 		last_prob_time[p] = t_now;
 	}
@@ -304,11 +297,12 @@ static const struct dual_battery_policy db_policy = {
 };
 
 /* Add at most "value" to power_var, subtracting from total_power budget. */
-#define CHG_ALLOCATE(power_var, total_power, value) do {	\
-	int val_capped = MIN(value, total_power);		\
-	(power_var) += val_capped;				\
-	(total_power) -= val_capped;				\
-} while (0)
+#define CHG_ALLOCATE(power_var, total_power, value)       \
+	do {                                              \
+		int val_capped = MIN(value, total_power); \
+		(power_var) += val_capped;                \
+		(total_power) -= val_capped;              \
+	} while (0)
 
 /* Update base battery information */
 static void update_base_battery_info(void)
@@ -346,9 +340,9 @@ static void update_base_battery_info(void)
 
 		/* Newly connected battery, or change in capacity. */
 		if (old_flags & EC_BATT_FLAG_INVALID_DATA ||
-				((old_flags & EC_BATT_FLAG_BATT_PRESENT) !=
-				 (bd->flags & EC_BATT_FLAG_BATT_PRESENT)) ||
-				old_full_capacity != bd->full_capacity)
+		    ((old_flags & EC_BATT_FLAG_BATT_PRESENT) !=
+		     (bd->flags & EC_BATT_FLAG_BATT_PRESENT)) ||
+		    old_full_capacity != bd->full_capacity)
 			host_set_single_event(EC_HOST_EVENT_BATTERY);
 
 		if (flags_changed)
@@ -359,8 +353,8 @@ static void update_base_battery_info(void)
 				 BATT_FLAG_BAD_REMAINING_CAPACITY))
 			charge_base = -1;
 		else if (bd->full_capacity > 0)
-			charge_base = 100 * bd->remaining_capacity
-						/ bd->full_capacity;
+			charge_base = 100 * bd->remaining_capacity /
+				      bd->full_capacity;
 		else
 			charge_base = 0;
 	}
@@ -380,8 +374,8 @@ static int set_base_current(int current_base, int allow_charge_base)
 	const int otg_voltage = db_policy.otg_voltage;
 	int ret;
 
-	ret = ec_ec_client_base_charge_control(current_base,
-					otg_voltage, allow_charge_base);
+	ret = ec_ec_client_base_charge_control(current_base, otg_voltage,
+					       allow_charge_base);
 	if (ret) {
 		/* Ignore errors until the base is responsive. */
 		if (base_responsive)
@@ -418,9 +412,9 @@ static void set_base_lid_current(int current_base, int allow_charge_base,
 	if (prev_current_base != current_base ||
 	    prev_allow_charge_base != allow_charge_base ||
 	    prev_current_lid != current_lid) {
-		CPRINTS("Base/Lid: %d%s/%d%s mA",
-			current_base, allow_charge_base ? "+" : "",
-			current_lid, allow_charge_lid ? "+" : "");
+		CPRINTS("Base/Lid: %d%s/%d%s mA", current_base,
+			allow_charge_base ? "+" : "", current_lid,
+			allow_charge_lid ? "+" : "");
 	}
 
 	/*
@@ -452,12 +446,12 @@ static void set_base_lid_current(int current_base, int allow_charge_base,
 			return;
 		if (allow_charge_lid)
 			ret = charge_request(curr.requested_voltage,
-				curr.requested_current);
+					     curr.requested_current);
 		else
 			ret = charge_request(0, 0);
 	} else {
-		ret = charge_set_output_current_limit(CHARGER_SOLO,
-						-current_lid, otg_voltage);
+		ret = charge_set_output_current_limit(
+			CHARGER_SOLO, -current_lid, otg_voltage);
 	}
 
 	if (ret)
@@ -536,7 +530,6 @@ static void charge_allocate_input_current_limit(void)
 	const struct ec_response_battery_dynamic_info *const base_bd =
 		&battery_dynamic[BATT_IDX_BASE];
 
-
 	if (!base_connected) {
 		set_base_lid_current(0, 0, curr.desired_input_current, 1);
 		prev_base_battery_power = -1;
@@ -553,7 +546,8 @@ static void charge_allocate_input_current_limit(void)
 	 * but the value is currently wrong, especially during transitions.
 	 */
 	if (total_power <= 0) {
-		int base_critical = charge_base >= 0 &&
+		int base_critical =
+			charge_base >= 0 &&
 			charge_base < db_policy.max_charge_base_batt_to_batt;
 
 		/* Discharging */
@@ -567,14 +561,14 @@ static void charge_allocate_input_current_limit(void)
 
 			if (manual_noac_current_base > 0) {
 				base_current = -manual_noac_current_base;
-				lid_current =
-					add_margin(manual_noac_current_base,
-						db_policy.margin_otg_current);
+				lid_current = add_margin(
+					manual_noac_current_base,
+					db_policy.margin_otg_current);
 			} else {
 				lid_current = manual_noac_current_base;
-				base_current =
-					add_margin(-manual_noac_current_base,
-						db_policy.margin_otg_current);
+				base_current = add_margin(
+					-manual_noac_current_base,
+					db_policy.margin_otg_current);
 			}
 
 			set_base_lid_current(base_current, 0, lid_current, 0);
@@ -605,18 +599,20 @@ static void charge_allocate_input_current_limit(void)
 		 * touchpad events.
 		 */
 		if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
-					!base_critical) {
+		    !base_critical) {
 			set_base_lid_current(0, 0, 0, 0);
 			return;
 		}
 
 		if (charge_base > db_policy.min_charge_base_otg) {
 			int lid_current = db_policy.max_base_to_lid_current;
-			int base_current = add_margin(lid_current,
-						db_policy.margin_otg_current);
+			int base_current = add_margin(
+				lid_current, db_policy.margin_otg_current);
 			/* Draw current from base to lid */
-			set_base_lid_current(-base_current, 0, lid_current,
-			    charge_lid < db_policy.max_charge_lid_batt_to_batt);
+			set_base_lid_current(
+				-base_current, 0, lid_current,
+				charge_lid <
+					db_policy.max_charge_lid_batt_to_batt);
 		} else {
 			/*
 			 * Base battery is too low, apply power to it, and allow
@@ -635,8 +631,8 @@ static void charge_allocate_input_current_limit(void)
 			int base_current =
 				(db_policy.min_base_system_power * 1000) /
 				db_policy.otg_voltage;
-			int lid_current = add_margin(base_current,
-						db_policy.margin_otg_current);
+			int lid_current = add_margin(
+				base_current, db_policy.margin_otg_current);
 
 			set_base_lid_current(base_current, base_critical,
 					     -lid_current, 0);
@@ -664,8 +660,8 @@ static void charge_allocate_input_current_limit(void)
 	lid_system_power = charger_get_system_power() / 1000;
 
 	/* Smooth system power, as it is very spiky */
-	lid_system_power = smooth_value(prev_lid_system_power,
-			lid_system_power, db_policy.lid_system_power_smooth);
+	lid_system_power = smooth_value(prev_lid_system_power, lid_system_power,
+					db_policy.lid_system_power_smooth);
 	prev_lid_system_power = lid_system_power;
 
 	/*
@@ -677,15 +673,15 @@ static void charge_allocate_input_current_limit(void)
 	 */
 	/* Estimate lid battery power. */
 	if (!(curr.batt.flags &
-			(BATT_FLAG_BAD_VOLTAGE | BATT_FLAG_BAD_CURRENT)))
-		lid_battery_power = curr.batt.current *
-				    curr.batt.voltage / 1000;
+	      (BATT_FLAG_BAD_VOLTAGE | BATT_FLAG_BAD_CURRENT)))
+		lid_battery_power =
+			curr.batt.current * curr.batt.voltage / 1000;
 	if (lid_battery_power < prev_lid_battery_power)
-		lid_battery_power = smooth_value(prev_lid_battery_power,
-			     lid_battery_power, db_policy.battery_power_smooth);
+		lid_battery_power =
+			smooth_value(prev_lid_battery_power, lid_battery_power,
+				     db_policy.battery_power_smooth);
 	if (!(curr.batt.flags &
-			(BATT_FLAG_BAD_DESIRED_VOLTAGE |
-				BATT_FLAG_BAD_DESIRED_CURRENT)))
+	      (BATT_FLAG_BAD_DESIRED_VOLTAGE | BATT_FLAG_BAD_DESIRED_CURRENT)))
 		lid_battery_power_max = curr.batt.desired_current *
 					curr.batt.desired_voltage / 1000;
 
@@ -699,19 +695,20 @@ static void charge_allocate_input_current_limit(void)
 					 base_bd->desired_voltage / 1000;
 	}
 	if (base_battery_power < prev_base_battery_power)
-		base_battery_power = smooth_value(prev_base_battery_power,
-			    base_battery_power, db_policy.battery_power_smooth);
+		base_battery_power = smooth_value(
+			prev_base_battery_power, base_battery_power,
+			db_policy.battery_power_smooth);
 	base_battery_power = MIN(base_battery_power, base_battery_power_max);
 
 	if (debugging) {
 		CPRINTF("%s:\n", __func__);
 		CPRINTF("total power: %d\n", total_power);
-		CPRINTF("base battery power: %d (%d)\n",
-			base_battery_power, base_battery_power_max);
+		CPRINTF("base battery power: %d (%d)\n", base_battery_power,
+			base_battery_power_max);
 		CPRINTF("lid system power: %d\n", lid_system_power);
 		CPRINTF("lid battery power: %d\n", lid_battery_power);
-		CPRINTF("percent base/lid: %d%% %d%%\n",
-			charge_base, charge_lid);
+		CPRINTF("percent base/lid: %d%% %d%%\n", charge_base,
+			charge_lid);
 	}
 
 	prev_lid_battery_power = lid_battery_power;
@@ -720,30 +717,31 @@ static void charge_allocate_input_current_limit(void)
 	if (total_power > 0) { /* Charging */
 		/* Allocate system power */
 		CHG_ALLOCATE(power_base, total_power,
-			db_policy.min_base_system_power);
+			     db_policy.min_base_system_power);
 		CHG_ALLOCATE(power_lid, total_power, lid_system_power);
 
 		/* Allocate lid, then base battery power */
-		lid_battery_power = add_margin(lid_battery_power,
-					db_policy.margin_lid_battery_power);
+		lid_battery_power = add_margin(
+			lid_battery_power, db_policy.margin_lid_battery_power);
 		CHG_ALLOCATE(power_lid, total_power, lid_battery_power);
 
-		base_battery_power = add_margin(base_battery_power,
-					db_policy.margin_base_battery_power);
+		base_battery_power =
+			add_margin(base_battery_power,
+				   db_policy.margin_base_battery_power);
 		CHG_ALLOCATE(power_base, total_power, base_battery_power);
 
 		/* Give everything else to the lid. */
 		CHG_ALLOCATE(power_lid, total_power, total_power);
 		if (debugging)
-			CPRINTF("power: base %d mW / lid %d mW\n",
-				power_base, power_lid);
+			CPRINTF("power: base %d mW / lid %d mW\n", power_base,
+				power_lid);
 
 		current_base = 1000 * power_base / curr.input_voltage;
 		current_lid = 1000 * power_lid / curr.input_voltage;
 
 		if (current_base > db_policy.max_lid_to_base_current) {
-			current_lid += (current_base
-					- db_policy.max_lid_to_base_current);
+			current_lid += (current_base -
+					db_policy.max_lid_to_base_current);
 			current_base = db_policy.max_lid_to_base_current;
 		}
 
@@ -760,12 +758,13 @@ static void charge_allocate_input_current_limit(void)
 }
 #endif /* CONFIG_EC_EC_COMM_BATTERY_CLIENT */
 
-static const char * const state_list[] = {
-	"idle", "discharge", "charge", "precharge"
-};
+static const char *const state_list[] = { "idle", "discharge", "charge",
+					  "precharge" };
 BUILD_ASSERT(ARRAY_SIZE(state_list) == NUM_STATES_V2);
-static const char * const batt_pres[] = {
-	"NO", "YES", "NOT_SURE",
+static const char *const batt_pres[] = {
+	"NO",
+	"YES",
+	"NOT_SURE",
 };
 
 const char *mode_text[] = EC_CHARGE_MODE_TEXT;
@@ -774,9 +773,9 @@ BUILD_ASSERT(ARRAY_SIZE(mode_text) == CHARGE_CONTROL_COUNT);
 static void dump_charge_state(void)
 {
 #define DUMP(FLD, FMT) ccprintf(#FLD " = " FMT "\n", curr.FLD)
-#define DUMP_CHG(FLD, FMT) ccprintf("\t" #FLD " = " FMT "\n", curr.chg. FLD)
-#define DUMP_BATT(FLD, FMT) ccprintf("\t" #FLD " = " FMT "\n", curr.batt. FLD)
-#define DUMP_OCPC(FLD, FMT) ccprintf("\t" #FLD " = " FMT "\n", curr.ocpc. FLD)
+#define DUMP_CHG(FLD, FMT) ccprintf("\t" #FLD " = " FMT "\n", curr.chg.FLD)
+#define DUMP_BATT(FLD, FMT) ccprintf("\t" #FLD " = " FMT "\n", curr.batt.FLD)
+#define DUMP_OCPC(FLD, FMT) ccprintf("\t" #FLD " = " FMT "\n", curr.ocpc.FLD)
 
 	enum ec_charge_control_mode cmode = get_chg_ctrl_mode();
 
@@ -846,8 +845,8 @@ static void dump_charge_state(void)
 	ccprintf("battery_was_removed = %d\n", battery_was_removed);
 	ccprintf("debug output = %s\n", debugging ? "on" : "off");
 	ccprintf("Battery sustainer = %s (%d%% ~ %d%%)\n",
-		 battery_sustainer_enabled() ? "on" : "off",
-		 sustain_soc.lower, sustain_soc.upper);
+		 battery_sustainer_enabled() ? "on" : "off", sustain_soc.lower,
+		 sustain_soc.upper);
 #undef DUMP
 }
 
@@ -901,14 +900,13 @@ static void show_charging_progress(void)
 	dsoc = charge_get_display_charge();
 	if (rv)
 		CPRINTS("Battery %d%% (Display %d.%d %%) / ??h:?? %s%s",
-			curr.batt.state_of_charge,
-			dsoc / 10, dsoc % 10,
+			curr.batt.state_of_charge, dsoc / 10, dsoc % 10,
 			to_full ? "to full" : "to empty",
 			is_full ? ", not accepting current" : "");
 	else
 		CPRINTS("Battery %d%% (Display %d.%d %%) / %dh:%d %s%s",
-			curr.batt.state_of_charge,
-			dsoc / 10, dsoc % 10, minutes / 60, minutes % 60,
+			curr.batt.state_of_charge, dsoc / 10, dsoc % 10,
+			minutes / 60, minutes % 60,
 			to_full ? "to full" : "to empty",
 			is_full ? ", not accepting current" : "");
 
@@ -948,6 +946,11 @@ test_mockable int calc_is_full(void)
 	return ret;
 }
 
+__overridable int board_should_charger_bypass(void)
+{
+	return false;
+}
+
 /*
  * Ask the charger for some voltage and current. If either value is 0,
  * charging is disabled; otherwise it's enabled. Negative values are ignored.
@@ -956,6 +959,7 @@ static int charge_request(int voltage, int current)
 {
 	int r1 = EC_SUCCESS, r2 = EC_SUCCESS, r3 = EC_SUCCESS, r4 = EC_SUCCESS;
 	static int prev_volt, prev_curr;
+	bool should_bypass;
 
 	if (!voltage || !current) {
 #ifdef CONFIG_CHARGER_NARROW_VDC
@@ -983,6 +987,17 @@ static int charge_request(int voltage, int current)
 	}
 
 	/*
+	 * Enable bypass mode if applicable. Transition from Bypass to Bypass +
+	 * CHRG or backward is done after this call (by set_current & set_mode)
+	 * thus not done here. Similarly, when bypass is disabled, transitioning
+	 * from nvdc + chrg will be done separately.
+	 */
+	should_bypass = board_should_charger_bypass();
+	if ((should_bypass && !(curr.chg.status & CHARGER_BYPASS_MODE)) ||
+	    (!should_bypass && (curr.chg.status & CHARGER_BYPASS_MODE)))
+		charger_enable_bypass_mode(0, should_bypass);
+
+	/*
 	 * Set current before voltage so that if we are just starting
 	 * to charge, we allow some time (i2c delay) for charging circuit to
 	 * start at a voltage just above battery voltage before jumping
@@ -1019,9 +1034,9 @@ static int charge_request(int voltage, int current)
 	 */
 	if (curr.ocpc.active_chg_chip == CHARGER_SECONDARY) {
 		if ((current >= 0) || (voltage >= 0))
-			r3 = ocpc_config_secondary_charger(&curr.desired_input_current,
-							   &curr.ocpc,
-							   voltage, current);
+			r3 = ocpc_config_secondary_charger(
+				&curr.desired_input_current, &curr.ocpc,
+				voltage, current);
 		if (r3 != EC_SUCCESS)
 			charge_problem(PR_CFG_SEC_CHG, r3);
 	}
@@ -1140,9 +1155,8 @@ static inline int battery_too_low(void)
 		 curr.batt.voltage <= batt_info->voltage_min));
 }
 
-__attribute__((weak))
-enum critical_shutdown board_critical_shutdown_check(
-		struct charge_state_data *curr)
+__attribute__((weak)) enum critical_shutdown
+board_critical_shutdown_check(struct charge_state_data *curr)
 {
 #ifdef CONFIG_BATTERY_CRITICAL_SHUTDOWN_CUT_OFF
 	return CRITICAL_SHUTDOWN_CUTOFF;
@@ -1173,21 +1187,21 @@ static int is_battery_critical(void)
 	}
 
 	if (battery_too_low() && !curr.batt_is_charging) {
-		CPRINTS("Low battery: %d%%, %dmV",
-			curr.batt.state_of_charge, curr.batt.voltage);
+		CPRINTS("Low battery: %d%%, %dmV", curr.batt.state_of_charge,
+			curr.batt.voltage);
 		return 1;
 	}
 
 	return 0;
 }
 
- /*
-  * If the battery is at extremely low charge (and discharging) or extremely
-  * high temperature, the EC will notify the AP and start a timer. If the
-  * critical condition is not corrected before the timeout expires, the EC
-  * will shut down the AP (if the AP is not already off) and then optionally
-  * hibernate or cut off battery.
-  */
+/*
+ * If the battery is at extremely low charge (and discharging) or extremely
+ * high temperature, the EC will notify the AP and start a timer. If the
+ * critical condition is not corrected before the timeout expires, the EC
+ * will shut down the AP (if the AP is not already off) and then optionally
+ * hibernate or cut off battery.
+ */
 static int shutdown_on_critical_battery(void)
 {
 	if (!is_battery_critical()) {
@@ -1199,8 +1213,8 @@ static int shutdown_on_critical_battery(void)
 	if (!shutdown_target_time.val) {
 		/* Start count down timer */
 		CPRINTS("Start shutdown due to critical battery");
-		shutdown_target_time.val = get_time().val
-				+ CRITICAL_BATTERY_SHUTDOWN_TIMEOUT_US;
+		shutdown_target_time.val =
+			get_time().val + CRITICAL_BATTERY_SHUTDOWN_TIMEOUT_US;
 #ifdef CONFIG_HOSTCMD_EVENTS
 		if (!chipset_in_state(CHIPSET_STATE_ANY_OFF))
 			host_set_single_event(EC_HOST_EVENT_BATTERY_SHUTDOWN);
@@ -1245,14 +1259,36 @@ static int shutdown_on_critical_battery(void)
 		}
 	} else {
 		/* Timeout waiting for AP to shut down, so kill it */
-		CPRINTS(
-		  "charge force shutdown due to critical battery");
+		CPRINTS("charge force shutdown due to critical battery");
 		chipset_force_shutdown(CHIPSET_SHUTDOWN_BATTERY_CRIT);
 	}
 
 	return 1;
 }
 
+int battery_is_below_threshold(enum batt_threshold_type type, bool transitioned)
+{
+	int threshold;
+
+	/* We can't tell what the current charge is. Assume it's okay. */
+	if (curr.batt.flags & BATT_FLAG_BAD_STATE_OF_CHARGE)
+		return 0;
+
+	switch (type) {
+	case BATT_THRESHOLD_TYPE_LOW:
+		threshold = BATTERY_LEVEL_LOW;
+		break;
+	case BATT_THRESHOLD_TYPE_SHUTDOWN:
+		threshold = CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE;
+		break;
+	default:
+		return 0;
+	}
+
+	return curr.batt.state_of_charge <= threshold &&
+	       (!transitioned || prev_charge > threshold);
+}
+
 /*
  * Send host events as the battery charge drops below certain thresholds.
  * We handle forced shutdown and other actions elsewhere; this is just for the
@@ -1261,17 +1297,11 @@ static int shutdown_on_critical_battery(void)
  */
 static void notify_host_of_low_battery_charge(void)
 {
-	/* We can't tell what the current charge is. Assume it's okay. */
-	if (curr.batt.flags & BATT_FLAG_BAD_STATE_OF_CHARGE)
-		return;
-
 #ifdef CONFIG_HOSTCMD_EVENTS
-	if (curr.batt.state_of_charge <= BATTERY_LEVEL_LOW &&
-	    prev_charge > BATTERY_LEVEL_LOW)
+	if (battery_is_below_threshold(BATT_THRESHOLD_TYPE_LOW, true))
 		host_set_single_event(EC_HOST_EVENT_BATTERY_LOW);
 
-	if (curr.batt.state_of_charge <= BATTERY_LEVEL_CRITICAL &&
-	    prev_charge > BATTERY_LEVEL_CRITICAL)
+	if (battery_is_below_threshold(BATT_THRESHOLD_TYPE_SHUTDOWN, true))
 		host_set_single_event(EC_HOST_EVENT_BATTERY_CRITICAL);
 #endif
 }
@@ -1295,16 +1325,16 @@ static void notify_host_of_low_battery_voltage(void)
 			    THROTTLE_SRC_BAT_VOLTAGE);
 		uvp_throttle_start_time = get_time();
 	} else if (uvp_throttle_start_time.val &&
-		   (curr.batt.voltage < BAT_LOW_VOLTAGE_THRESH +
-		    BAT_UVP_HYSTERESIS)) {
+		   (curr.batt.voltage <
+		    BAT_LOW_VOLTAGE_THRESH + BAT_UVP_HYSTERESIS)) {
 		/*
 		 * Reset the timer when we are not sure if VBAT can stay
 		 * above BAT_LOW_VOLTAGE_THRESH after we stop throttling.
 		 */
 		uvp_throttle_start_time = get_time();
 	} else if (uvp_throttle_start_time.val &&
-		   (get_time().val > uvp_throttle_start_time.val +
-		     BAT_UVP_TIMEOUT_US)) {
+		   (get_time().val >
+		    uvp_throttle_start_time.val + BAT_UVP_TIMEOUT_US)) {
 		throttle_ap(THROTTLE_OFF, THROTTLE_SOFT,
 			    THROTTLE_SRC_BAT_VOLTAGE);
 		uvp_throttle_start_time.val = 0;
@@ -1328,8 +1358,8 @@ static void notify_host_of_over_current(struct batt_params *batt)
 		throttle_ap(THROTTLE_ON, THROTTLE_SOFT,
 			    THROTTLE_SRC_BAT_DISCHG_CURRENT);
 	} else if (ocp_throttle_start_time.val &&
-		   (get_time().val > ocp_throttle_start_time.val +
-		    BAT_OCP_TIMEOUT_US)) {
+		   (get_time().val >
+		    ocp_throttle_start_time.val + BAT_OCP_TIMEOUT_US)) {
 		/*
 		 * Clear the timer and notify AP to stop throttling if
 		 * we haven't seen over current for BAT_OCP_TIMEOUT_US.
@@ -1361,8 +1391,8 @@ static int battery_outside_charging_temperature(void)
 	if (curr.batt.flags & BATT_FLAG_BAD_TEMPERATURE)
 		return 0;
 
-	if((curr.batt.desired_voltage == 0) &&
-		(curr.batt.desired_current == 0)){
+	if ((curr.batt.desired_voltage == 0) &&
+	    (curr.batt.desired_current == 0)) {
 		max_c = batt_info->start_charging_max_c;
 		min_c = batt_info->start_charging_min_c;
 	} else {
@@ -1370,9 +1400,7 @@ static int battery_outside_charging_temperature(void)
 		min_c = batt_info->charging_min_c;
 	}
 
-
-	if ((batt_temp_c >= max_c) ||
-		 (batt_temp_c <= min_c)) {
+	if ((batt_temp_c >= max_c) || (batt_temp_c <= min_c)) {
 		return 1;
 	}
 	return 0;
@@ -1385,8 +1413,8 @@ static void sustain_battery_soc(void)
 	int rv;
 
 	/* If either AC or battery is not present, nothing to do. */
-	if (!curr.ac || curr.batt.is_present != BP_YES
-			|| !battery_sustainer_enabled())
+	if (!curr.ac || curr.batt.is_present != BP_YES ||
+	    !battery_sustainer_enabled())
 		return;
 
 	soc = charge_get_display_charge() / 10;
@@ -1402,7 +1430,8 @@ static void sustain_battery_soc(void)
 		/* Going up */
 		if (sustain_soc.upper < soc)
 			mode = sustain_soc.upper == sustain_soc.lower ?
-				CHARGE_CONTROL_IDLE : CHARGE_CONTROL_DISCHARGE;
+				       CHARGE_CONTROL_IDLE :
+				       CHARGE_CONTROL_DISCHARGE;
 		break;
 	case CHARGE_CONTROL_IDLE:
 		/* Discharging naturally */
@@ -1422,8 +1451,8 @@ static void sustain_battery_soc(void)
 		return;
 
 	rv = set_chg_ctrl_mode(mode);
-	CPRINTS("%s: %s control mode to %s",
-		__func__, rv == EC_SUCCESS ? "Switched" : "Failed to switch",
+	CPRINTS("%s: %s control mode to %s", __func__,
+		rv == EC_SUCCESS ? "Switched" : "Failed to switch",
 		mode_text[mode]);
 }
 
@@ -1454,6 +1483,7 @@ static void charge_wakeup(void)
 }
 DECLARE_HOOK(HOOK_CHIPSET_RESUME, charge_wakeup, HOOK_PRIO_DEFAULT);
 DECLARE_HOOK(HOOK_AC_CHANGE, charge_wakeup, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_POWER_SUPPLY_CHANGE, charge_wakeup, HOOK_PRIO_DEFAULT);
 
 #ifdef CONFIG_EC_EC_COMM_BATTERY_CLIENT
 /* Reset the base on S5->S0 transition. */
@@ -1465,20 +1495,19 @@ static void bat_low_voltage_throttle_reset(void)
 {
 	uvp_throttle_start_time.val = 0;
 }
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN,
-	     bat_low_voltage_throttle_reset,
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, bat_low_voltage_throttle_reset,
 	     HOOK_PRIO_DEFAULT);
 #endif
 
 static int get_desired_input_current(enum battery_present batt_present,
-				     const struct charger_info * const info)
+				     const struct charger_info *const info)
 {
 	if (batt_present == BP_YES || system_is_locked() || base_connected) {
 #ifdef CONFIG_CHARGE_MANAGER
 		int ilim = charge_manager_get_charger_current();
 		return ilim == CHARGE_CURRENT_UNINITIALIZED ?
-			CHARGE_CURRENT_UNINITIALIZED :
-			MAX(CONFIG_CHARGER_INPUT_CURRENT, ilim);
+			       CHARGE_CURRENT_UNINITIALIZED :
+			       MAX(CONFIG_CHARGER_INPUT_CURRENT, ilim);
 #else
 		return CONFIG_CHARGER_INPUT_CURRENT;
 #endif
@@ -1498,9 +1527,9 @@ static void wakeup_battery(int *need_static)
 		set_charge_state(ST_IDLE);
 		curr.requested_voltage = 0;
 		curr.requested_current = 0;
-	} else if (curr.state == ST_PRECHARGE
-			&& (get_time().val > precharge_start_time.val +
-			PRECHARGE_TIMEOUT_US)) {
+	} else if (curr.state == ST_PRECHARGE &&
+		   (get_time().val >
+		    precharge_start_time.val + PRECHARGE_TIMEOUT_US)) {
 		/* We've tried long enough, give up */
 		CPRINTS("battery seems to be dead");
 		battery_seems_dead = 1;
@@ -1531,9 +1560,10 @@ static void deep_charge_battery(int *need_static)
 		/* Deep charge time out , do nothing */
 		curr.requested_voltage = 0;
 		curr.requested_current = 0;
-	} else if (curr.state == ST_PRECHARGE
-			&& (get_time().val > precharge_start_time.val +
-			CONFIG_BATTERY_LOW_VOLTAGE_TIMEOUT)) {
+	} else if (curr.state == ST_PRECHARGE &&
+		   (get_time().val >
+		    precharge_start_time.val +
+			    CONFIG_BATTERY_LOW_VOLTAGE_TIMEOUT)) {
 		/* We've tried long enough, give up */
 		CPRINTS("Precharge for low voltage timed out");
 		set_charge_state(ST_IDLE);
@@ -1552,13 +1582,11 @@ static void deep_charge_battery(int *need_static)
 	}
 }
 
-
 static void revive_battery(int *need_static)
 {
-	if (IS_ENABLED(CONFIG_BATTERY_REQUESTS_NIL_WHEN_DEAD)
-			&& curr.requested_voltage == 0
-			&& curr.requested_current == 0
-			&& curr.batt.state_of_charge == 0) {
+	if (IS_ENABLED(CONFIG_BATTERY_REQUESTS_NIL_WHEN_DEAD) &&
+	    curr.requested_voltage == 0 && curr.requested_current == 0 &&
+	    curr.batt.state_of_charge == 0) {
 		/*
 		 * Battery is dead, give precharge current
 		 * TODO (crosbug.com/p/29467): remove this workaround
@@ -1566,10 +1594,9 @@ static void revive_battery(int *need_static)
 		 */
 		curr.requested_voltage = batt_info->voltage_max;
 		curr.requested_current = batt_info->precharge_current;
-	} else if (IS_ENABLED(CONFIG_BATTERY_REVIVE_DISCONNECT)
-			&& curr.requested_voltage == 0
-			&& curr.requested_current == 0
-			&& battery_seems_disconnected) {
+	} else if (IS_ENABLED(CONFIG_BATTERY_REVIVE_DISCONNECT) &&
+		   curr.requested_voltage == 0 && curr.requested_current == 0 &&
+		   battery_seems_disconnected) {
 		/*
 		 * Battery is in disconnect state. Apply a
 		 * current to kick it out of this state.
@@ -1577,8 +1604,8 @@ static void revive_battery(int *need_static)
 		CPRINTS("found battery in disconnect state");
 		curr.requested_voltage = batt_info->voltage_max;
 		curr.requested_current = batt_info->precharge_current;
-	} else if (curr.state == ST_PRECHARGE
-			|| battery_seems_dead || battery_was_removed) {
+	} else if (curr.state == ST_PRECHARGE || battery_seems_dead ||
+		   battery_was_removed) {
 		CPRINTS("battery woke up");
 		/* Update the battery-specific values */
 		batt_info = battery_get_info();
@@ -1594,7 +1621,7 @@ void charger_task(void *u)
 	int sleep_usec;
 	int battery_critical;
 	int need_static = 1;
-	const struct charger_info * const info = charger_get_info();
+	const struct charger_info *const info = charger_get_info();
 	int prev_plt_and_desired_mw;
 	int chgnum = 0;
 
@@ -1622,8 +1649,8 @@ void charger_task(void *u)
 	 * as needed.
 	 */
 	prev_bp = BP_NOT_INIT;
-	curr.desired_input_current = get_desired_input_current(
-			curr.batt.is_present, info);
+	curr.desired_input_current =
+		get_desired_input_current(curr.batt.is_present, info);
 
 	if (IS_ENABLED(CONFIG_USB_PD_PREFER_MV)) {
 		/* init battery desired power */
@@ -1640,7 +1667,6 @@ void charger_task(void *u)
 	battery_level_shutdown = board_set_battery_level_shutdown();
 
 	while (1) {
-
 		/* Let's see what's going on... */
 		curr.ts = get_time();
 		sleep_usec = 0;
@@ -1657,8 +1683,8 @@ void charger_task(void *u)
 			curr.ac = 0;
 
 		/* System is off: if AC gets connected, reset the base. */
-		if (chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
-				!prev_ac && curr.ac)
+		if (chipset_in_state(CHIPSET_STATE_ANY_OFF) && !prev_ac &&
+		    curr.ac)
 			board_base_reset();
 #endif
 		if (curr.ac != prev_ac) {
@@ -1679,7 +1705,7 @@ void charger_task(void *u)
 				if (rv != EC_SUCCESS) {
 					charge_problem(PR_POST_INIT, rv);
 				} else if (curr.desired_input_current !=
-					    CHARGE_CURRENT_UNINITIALIZED) {
+					   CHARGE_CURRENT_UNINITIALIZED) {
 					rv = charger_set_input_current_limit(
 						chgnum,
 						curr.desired_input_current);
@@ -1727,8 +1753,8 @@ void charger_task(void *u)
 				get_desired_input_current(prev_bp, info);
 			if (curr.desired_input_current !=
 			    CHARGE_CURRENT_UNINITIALIZED)
-				charger_set_input_current_limit(chgnum,
-					curr.desired_input_current);
+				charger_set_input_current_limit(
+					chgnum, curr.desired_input_current);
 			hook_notify(HOOK_BATTERY_SOC_CHANGE);
 		}
 
@@ -1749,7 +1775,7 @@ void charger_task(void *u)
 		 * applying power to a battery we can't talk to.
 		 */
 		if (curr.batt.flags & (BATT_FLAG_BAD_DESIRED_VOLTAGE |
-					BATT_FLAG_BAD_DESIRED_CURRENT)) {
+				       BATT_FLAG_BAD_DESIRED_CURRENT)) {
 			curr.requested_voltage = 0;
 			curr.requested_current = 0;
 		} else {
@@ -1805,9 +1831,9 @@ void charger_task(void *u)
 			goto wait_for_it;
 		}
 
-		if (IS_ENABLED(CONFIG_BATTERY_LOW_VOLTAGE_PROTECTION)
-			&& !(curr.batt.flags & BATT_FLAG_BAD_VOLTAGE)
-			&& (curr.batt.voltage <= batt_info->voltage_min)) {
+		if (IS_ENABLED(CONFIG_BATTERY_LOW_VOLTAGE_PROTECTION) &&
+		    !(curr.batt.flags & BATT_FLAG_BAD_VOLTAGE) &&
+		    (curr.batt.voltage <= batt_info->voltage_min)) {
 			deep_charge_battery(&need_static);
 			goto wait_for_it;
 		}
@@ -1819,23 +1845,23 @@ void charger_task(void *u)
 		 * the battery disconnect state is one of the items used
 		 * to decide whether or not to leave safe mode.
 		 */
-		battery_seems_disconnected =
-			battery_get_disconnect_state() == BATTERY_DISCONNECTED;
+		battery_seems_disconnected = battery_get_disconnect_state() ==
+					     BATTERY_DISCONNECTED;
 
 		revive_battery(&need_static);
 
 		set_charge_state(ST_CHARGE);
 
-wait_for_it:
-		if (IS_ENABLED(CONFIG_CHARGER_PROFILE_OVERRIDE)
-			&& get_chg_ctrl_mode() == CHARGE_CONTROL_NORMAL) {
+	wait_for_it:
+		if (IS_ENABLED(CONFIG_CHARGER_PROFILE_OVERRIDE) &&
+		    get_chg_ctrl_mode() == CHARGE_CONTROL_NORMAL) {
 			sleep_usec = charger_profile_override(&curr);
 			if (sleep_usec < 0)
 				charge_problem(PR_CUSTOM, sleep_usec);
 		}
 
-		if (IS_ENABLED(CONFIG_BATTERY_CHECK_CHARGE_TEMP_LIMITS)
-				&& battery_outside_charging_temperature()) {
+		if (IS_ENABLED(CONFIG_BATTERY_CHECK_CHARGE_TEMP_LIMITS) &&
+		    battery_outside_charging_temperature()) {
 			curr.requested_current = 0;
 			curr.requested_voltage = 0;
 			curr.batt.flags &= ~BATT_FLAG_WANT_CHARGE;
@@ -1845,23 +1871,8 @@ wait_for_it:
 
 #ifdef CONFIG_CHARGE_MANAGER
 		if (curr.batt.state_of_charge >=
-		    CONFIG_CHARGE_MANAGER_BAT_PCT_SAFE_MODE_EXIT &&
+			    CONFIG_CHARGE_MANAGER_BAT_PCT_SAFE_MODE_EXIT &&
 		    !battery_seems_disconnected) {
-			/*
-			 * Sometimes the fuel gauge will report that it has
-			 * sufficient state of charge and remaining capacity,
-			 * but in actuality it doesn't.  When the EC sees that
-			 * information, it trusts it and leaves charge manager
-			 * safe mode.  Doing so will allow CHARGE_PORT_NONE to
-			 * be selected, thereby cutting off the input FETs.
-			 * When the battery cannot provide the charge it claims,
-			 * the system loses power, shuts down, and the battery
-			 * is not charged even though the charger is plugged in.
-			 * By waiting 500ms, we can avoid the selection of
-			 * CHARGE_PORT_NONE around init time and not cut off the
-			 * input FETs.
-			 */
-			msleep(500);
 			charge_manager_leave_safe_mode();
 		}
 #endif
@@ -1882,12 +1893,11 @@ wait_for_it:
 		sustain_battery_soc();
 
 		if ((!(curr.batt.flags & BATT_FLAG_BAD_STATE_OF_CHARGE) &&
-		    curr.batt.state_of_charge != prev_charge) ||
+		     curr.batt.state_of_charge != prev_charge) ||
 #ifdef CONFIG_EC_EC_COMM_BATTERY_CLIENT
 		    (charge_base != prev_charge_base) ||
 #endif
-		    (is_full != prev_full) ||
-		    (curr.state != prev_state) ||
+		    (is_full != prev_full) || (curr.state != prev_state) ||
 		    (charge_get_display_charge() != prev_disp_charge)) {
 			show_charging_progress();
 			prev_charge = curr.batt.state_of_charge;
@@ -1968,9 +1978,8 @@ wait_for_it:
 			sleep_usec = CHARGE_POLL_PERIOD_SHORT;
 		else if (sleep_usec <= 0) {
 			/* default values depend on the state */
-			if (!curr.ac &&
-			    (curr.state == ST_IDLE ||
-			    curr.state == ST_DISCHARGE)) {
+			if (!curr.ac && (curr.state == ST_IDLE ||
+					 curr.state == ST_DISCHARGE)) {
 #ifdef CONFIG_CHARGER_OTG
 				int output_current = curr.output_current;
 #else
@@ -1980,9 +1989,10 @@ wait_for_it:
 				 * If AP is off and we do not provide power, we
 				 * can sleep a long time.
 				 */
-				if (chipset_in_state(CHIPSET_STATE_ANY_OFF |
-						     CHIPSET_STATE_ANY_SUSPEND)
-						&& output_current == 0)
+				if (chipset_in_state(
+					    CHIPSET_STATE_ANY_OFF |
+					    CHIPSET_STATE_ANY_SUSPEND) &&
+				    output_current == 0)
 					sleep_usec =
 						CHARGE_POLL_PERIOD_VERY_LONG;
 				else
@@ -2062,15 +2072,14 @@ wait_for_it:
 	}
 }
 
-
 /*****************************************************************************/
 /* Exported functions */
 
 int charge_want_shutdown(void)
 {
 	return (curr.state == ST_DISCHARGE) &&
-		!(curr.batt.flags & BATT_FLAG_BAD_STATE_OF_CHARGE) &&
-		(curr.batt.state_of_charge < battery_level_shutdown);
+	       !(curr.batt.flags & BATT_FLAG_BAD_STATE_OF_CHARGE) &&
+	       (curr.batt.state_of_charge < battery_level_shutdown);
 }
 
 int charge_prevent_power_on(int power_button_pressed)
@@ -2103,14 +2112,14 @@ int charge_prevent_power_on(int power_button_pressed)
 	if (current_batt_params->is_present != BP_YES ||
 #ifdef CONFIG_BATTERY_MEASURE_IMBALANCE
 	    (current_batt_params->flags & BATT_FLAG_IMBALANCED_CELL &&
-		current_batt_params->state_of_charge <
-		CONFIG_CHARGER_MIN_BAT_PCT_IMBALANCED_POWER_ON) ||
+	     current_batt_params->state_of_charge <
+		     CONFIG_CHARGER_MIN_BAT_PCT_IMBALANCED_POWER_ON) ||
 #endif
 #ifdef CONFIG_BATTERY_REVIVE_DISCONNECT
 	    battery_get_disconnect_state() != BATTERY_NOT_DISCONNECTED ||
 #endif
 	    current_batt_params->state_of_charge <
-		CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON)
+		    CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON)
 		prevent_power_on = 1;
 
 #if defined(CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON) && \
@@ -2123,13 +2132,14 @@ int charge_prevent_power_on(int power_button_pressed)
 #if defined(CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT) && \
 	defined(CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC)
 		else if (charge_manager_get_power_limit_uw() >=
-		    CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT * 1000
+				 CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT *
+					 1000
 #ifdef CONFIG_BATTERY_REVIVE_DISCONNECT
-		    && battery_get_disconnect_state() ==
-							BATTERY_NOT_DISCONNECTED
+			 && battery_get_disconnect_state() ==
+				    BATTERY_NOT_DISCONNECTED
 #endif
-		    && (current_batt_params->state_of_charge >=
-			CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC))
+			 && (current_batt_params->state_of_charge >=
+			     CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC))
 			prevent_power_on = 0;
 #endif
 	}
@@ -2140,18 +2150,18 @@ int charge_prevent_power_on(int power_button_pressed)
 	 * except when auto-power-on at EC startup and the battery
 	 * is physically present.
 	 */
-	prevent_power_on &= (system_is_locked() || (automatic_power_on
+	prevent_power_on &=
+		(system_is_locked() || (automatic_power_on
 #ifdef CONFIG_BATTERY_HW_PRESENT_CUSTOM
-				    && battery_hw_present() == BP_YES
+					&& battery_hw_present() == BP_YES
 #endif
-				     ));
+					));
 #endif /* CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON */
 
 #ifdef CONFIG_CHARGE_MANAGER
 	/* Always prevent power on until charge current is initialized */
-	if (extpower_is_present() &&
-	    (charge_manager_get_charger_current() ==
-	     CHARGE_CURRENT_UNINITIALIZED))
+	if (extpower_is_present() && (charge_manager_get_charger_current() ==
+				      CHARGE_CURRENT_UNINITIALIZED))
 		prevent_power_on = 1;
 #ifdef CONFIG_BATTERY_HW_PRESENT_CUSTOM
 	/*
@@ -2161,19 +2171,19 @@ int charge_prevent_power_on(int power_button_pressed)
 	if (extpower_is_present() && battery_hw_present() == BP_NO
 #ifdef CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
 	    && charge_manager_get_power_limit_uw() <
-		CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON * 1000
+		       CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON * 1000
 #endif /* CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON */
-	    )
+	)
 		prevent_power_on = 1;
 #endif /* CONFIG_BATTERY_HW_PRESENT_CUSTOM */
 #endif /* CONFIG_CHARGE_MANAGER */
 
-	/*
-	 * Prevent power on if there is no battery nor ac power. This
-	 * happens when the servo is powering the EC to flash it. Only include
-	 * this logic for boards in initial bring up phase since this won't
-	 * happen for released boards.
-	 */
+		/*
+		 * Prevent power on if there is no battery nor ac power. This
+		 * happens when the servo is powering the EC to flash it. Only
+		 * include this logic for boards in initial bring up phase since
+		 * this won't happen for released boards.
+		 */
 #ifdef CONFIG_SYSTEM_UNLOCKED
 	if (!current_batt_params->is_present && !curr.ac)
 		prevent_power_on = 1;
@@ -2197,11 +2207,19 @@ static int battery_near_full(void)
 
 enum charge_state charge_get_state(void)
 {
+	uint32_t chflags;
+
 	switch (curr.state) {
 	case ST_IDLE:
+		chflags = charge_get_flags();
+
 		if (battery_seems_dead || curr.batt.is_present == BP_NO)
 			return PWR_STATE_ERROR;
-		return PWR_STATE_IDLE;
+
+		if (chflags & CHARGE_FLAG_FORCE_IDLE)
+			return PWR_STATE_FORCED_IDLE;
+		else
+			return PWR_STATE_IDLE;
 	case ST_DISCHARGE:
 #ifdef CONFIG_PWR_STATE_DISCHARGE_FULL
 		if (battery_near_full())
@@ -2219,8 +2237,13 @@ enum charge_state charge_get_state(void)
 		else
 			return PWR_STATE_CHARGE;
 	case ST_PRECHARGE:
+		chflags = charge_get_flags();
+
 		/* we're in battery discovery mode */
-		return PWR_STATE_IDLE;
+		if (chflags & CHARGE_FLAG_FORCE_IDLE)
+			return PWR_STATE_FORCED_IDLE;
+		else
+			return PWR_STATE_IDLE;
 	default:
 		/* Anything else can be considered an error for LED purposes */
 		return PWR_STATE_ERROR;
@@ -2317,8 +2340,7 @@ int charge_set_input_current_limit(int ma, int mv)
 	 * browning out due to insufficient input current.
 	 */
 	if (curr.batt.is_present != BP_YES && !system_is_locked() &&
-		!base_connected) {
-
+	    !base_connected) {
 		int prev_input = 0;
 
 		charger_get_input_current_limit(chgnum, &prev_input);
@@ -2333,8 +2355,8 @@ int charge_set_input_current_limit(int ma, int mv)
 		 * input system power.
 		 */
 
-		if (mv > 0 && mv * curr.desired_input_current >
-			PD_MAX_POWER_MW * 1000)
+		if (mv > 0 &&
+		    mv * curr.desired_input_current > PD_MAX_POWER_MW * 1000)
 			ma = (PD_MAX_POWER_MW * 1000) / mv;
 		/*
 		 * If the active charger has already been initialized to at
@@ -2346,11 +2368,11 @@ int charge_set_input_current_limit(int ma, int mv)
 		if (prev_input >= ma)
 			return EC_SUCCESS;
 #endif
-		/*
-		 * If the current needs lowered due to PD max power
-		 * considerations, or needs raised for the selected active
-		 * charger chip, fall through to set.
-		 */
+			/*
+			 * If the current needs lowered due to PD max power
+			 * considerations, or needs raised for the selected
+			 * active charger chip, fall through to set.
+			 */
 #endif /* CONFIG_USB_POWER_DELIVERY */
 	}
 
@@ -2468,8 +2490,8 @@ charge_command_charge_control(struct host_cmd_handler_args *args)
 		if (p->cmd == EC_CHARGE_CONTROL_CMD_SET) {
 			if (p->mode == CHARGE_CONTROL_NORMAL) {
 				rv = battery_sustainer_set(
-						p->sustain_soc.lower,
-						p->sustain_soc.upper);
+					p->sustain_soc.lower,
+					p->sustain_soc.upper);
 				if (rv == EC_RES_UNAVAILABLE)
 					return EC_RES_UNAVAILABLE;
 				if (rv)
@@ -2565,7 +2587,6 @@ charge_command_charge_state(struct host_cmd_handler_args *args)
 		chgnum = in->chgnum;
 
 	switch (in->cmd) {
-
 	case CHARGE_STATE_CMD_GET_STATE:
 		out->get_state.ac = curr.ac;
 		out->get_state.chg_voltage = curr.chg.voltage;
@@ -2577,18 +2598,18 @@ charge_command_charge_state(struct host_cmd_handler_args *args)
 
 	case CHARGE_STATE_CMD_GET_PARAM:
 		val = 0;
-		if (IS_ENABLED(CONFIG_CHARGER_PROFILE_OVERRIDE)
-			&& in->get_param.param >= CS_PARAM_CUSTOM_PROFILE_MIN
-			&& in->get_param.param <= CS_PARAM_CUSTOM_PROFILE_MAX) {
+		if (IS_ENABLED(CONFIG_CHARGER_PROFILE_OVERRIDE) &&
+		    in->get_param.param >= CS_PARAM_CUSTOM_PROFILE_MIN &&
+		    in->get_param.param <= CS_PARAM_CUSTOM_PROFILE_MAX) {
 			/* custom profile params */
-			rv  = charger_profile_override_get_param(
+			rv = charger_profile_override_get_param(
 				in->get_param.param, &val);
-		} else if (IS_ENABLED(CONFIG_CHARGE_STATE_DEBUG)
-			&& in->get_param.param >= CS_PARAM_DEBUG_MIN
-			&& in->get_param.param <= CS_PARAM_DEBUG_MAX) {
+		} else if (IS_ENABLED(CONFIG_CHARGE_STATE_DEBUG) &&
+			   in->get_param.param >= CS_PARAM_DEBUG_MIN &&
+			   in->get_param.param <= CS_PARAM_DEBUG_MAX) {
 			/* debug params */
-			rv = charge_get_charge_state_debug(
-				in->get_param.param, &val);
+			rv = charge_get_charge_state_debug(in->get_param.param,
+							   &val);
 		} else {
 			/* standard params */
 			switch (in->get_param.param) {
@@ -2615,10 +2636,11 @@ charge_command_charge_state(struct host_cmd_handler_args *args)
 				 */
 				if ((curr.batt.is_present != BP_YES ||
 				     curr.batt.state_of_charge <
-				     CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT)
-				     && charge_manager_get_power_limit_uw() <
-				     CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW
-				     * 1000 && system_is_locked())
+					     CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT) &&
+				    charge_manager_get_power_limit_uw() <
+					    CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW *
+						    1000 &&
+				    system_is_locked())
 					val = 1;
 				else
 #endif
@@ -2639,11 +2661,11 @@ charge_command_charge_state(struct host_cmd_handler_args *args)
 			return EC_RES_ACCESS_DENIED;
 
 		val = in->set_param.value;
-		if (IS_ENABLED(CONFIG_CHARGER_PROFILE_OVERRIDE)
-			&& in->set_param.param >= CS_PARAM_CUSTOM_PROFILE_MIN
-			&& in->set_param.param <= CS_PARAM_CUSTOM_PROFILE_MAX) {
+		if (IS_ENABLED(CONFIG_CHARGER_PROFILE_OVERRIDE) &&
+		    in->set_param.param >= CS_PARAM_CUSTOM_PROFILE_MIN &&
+		    in->set_param.param <= CS_PARAM_CUSTOM_PROFILE_MAX) {
 			/* custom profile params */
-			rv  = charger_profile_override_set_param(
+			rv = charger_profile_override_set_param(
 				in->set_param.param, val);
 		} else {
 			switch (in->set_param.param) {
@@ -2669,7 +2691,6 @@ charge_command_charge_state(struct host_cmd_handler_args *args)
 				break;
 			default:
 				rv = EC_RES_INVALID_PARAM;
-
 			}
 		}
 		break;
@@ -2690,7 +2711,7 @@ DECLARE_HOST_COMMAND(EC_CMD_CHARGE_STATE, charge_command_charge_state,
 
 #ifdef CONFIG_CMD_PWR_AVG
 
-static int command_pwr_avg(int argc, char **argv)
+static int command_pwr_avg(int argc, const char **argv)
 {
 	int avg_mv;
 	int avg_ma;
@@ -2705,18 +2726,16 @@ static int command_pwr_avg(int argc, char **argv)
 	avg_ma = battery_get_avg_current();
 	avg_mw = avg_mv * avg_ma / 1000;
 
-	ccprintf("mv = %d\nma = %d\nmw = %d\n",
-		avg_mv, avg_ma, avg_mw);
+	ccprintf("mv = %d\nma = %d\nmw = %d\n", avg_mv, avg_ma, avg_mw);
 	return EC_SUCCESS;
 }
 
-DECLARE_CONSOLE_COMMAND(pwr_avg, command_pwr_avg,
-			NULL,
+DECLARE_CONSOLE_COMMAND(pwr_avg, command_pwr_avg, NULL,
 			"Get 1 min power average");
 
 #endif /* CONFIG_CMD_PWR_AVG */
 
-static int command_chgstate(int argc, char **argv)
+static int command_chgstate(int argc, const char **argv)
 {
 	int rv;
 	int val;
@@ -2729,7 +2748,7 @@ static int command_chgstate(int argc, char **argv)
 			if (!parse_bool(argv[2], &val))
 				return EC_ERROR_PARAM2;
 			rv = set_chg_ctrl_mode(val ? CHARGE_CONTROL_IDLE :
-						CHARGE_CONTROL_NORMAL);
+						     CHARGE_CONTROL_NORMAL);
 			if (rv)
 				return rv;
 		} else if (!strcasecmp(argv[1], "discharge")) {
@@ -2738,7 +2757,7 @@ static int command_chgstate(int argc, char **argv)
 			if (!parse_bool(argv[2], &val))
 				return EC_ERROR_PARAM2;
 			rv = set_chg_ctrl_mode(val ? CHARGE_CONTROL_DISCHARGE :
-						CHARGE_CONTROL_NORMAL);
+						     CHARGE_CONTROL_NORMAL);
 			if (rv)
 				return rv;
 		} else if (!strcasecmp(argv[1], "debug")) {
@@ -2774,7 +2793,7 @@ DECLARE_CONSOLE_COMMAND(chgstate, command_chgstate,
 			"Get/set charge state machine status");
 
 #ifdef CONFIG_EC_EC_COMM_BATTERY_CLIENT
-static int command_chgdualdebug(int argc, char **argv)
+static int command_chgdualdebug(int argc, const char **argv)
 {
 	int val;
 	char *e;
@@ -2812,9 +2831,8 @@ static int command_chgdualdebug(int argc, char **argv)
 			return EC_ERROR_PARAM1;
 		}
 	} else {
-		ccprintf("Base/Lid: %d%s/%d mA\n",
-			 prev_current_base, prev_allow_charge_base ? "+" : "",
-			 prev_current_lid);
+		ccprintf("Base/Lid: %d%s/%d mA\n", prev_current_base,
+			 prev_allow_charge_base ? "+" : "", prev_current_lid);
 	}
 
 	return EC_SUCCESS;
diff --git a/common/chargen.c b/common/chargen.c
index 1a57e7f539..cfbf8bb2ca 100644
--- a/common/chargen.c
+++ b/common/chargen.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,8 +17,8 @@
  * Microseconds time to drain entire UART_TX console buffer at 115200 b/s, 10
  * bits per character.
  */
-#define BUFFER_DRAIN_TIME_US (1000000UL * 10 * CONFIG_UART_TX_BUF_SIZE         \
-				/ CONFIG_UART_BAUD_RATE)
+#define BUFFER_DRAIN_TIME_US \
+	(1000000UL * 10 * CONFIG_UART_TX_BUF_SIZE / CONFIG_UART_BAUD_RATE)
 
 /*
  * Generate a stream of characters on the UART (and USB) console.
@@ -37,7 +37,7 @@
  *
  * Hitting 'x' on the keyboard stops the generator.
  */
-static int command_chargen(int argc, char **argv)
+static int command_chargen(int argc, const char **argv)
 {
 	int wrap_value = 0;
 	int wrap_counter = 0;
@@ -80,7 +80,7 @@ static int command_chargen(int argc, char **argv)
 			 * Let's let other tasks run for a bit while buffer is
 			 * being drained a little.
 			 */
-			usleep(BUFFER_DRAIN_TIME_US/10);
+			usleep(BUFFER_DRAIN_TIME_US / 10);
 
 			current_time = get_time();
 
@@ -110,7 +110,7 @@ static int command_chargen(int argc, char **argv)
 			c = '0';
 		else if (c == ('Z' + 1))
 			c = 'a';
-		else if (c  == ('9' + 1))
+		else if (c == ('9' + 1))
 			c = 'A';
 	}
 
@@ -128,6 +128,5 @@ DECLARE_SAFE_CONSOLE_COMMAND(chargen, command_chargen,
 #endif
 			     "Generate a constant stream of characters on the "
 			     "UART console,\nrepeating every 'seq_length' "
-			     "characters, up to 'num_chars' total."
-	);
-#endif  /* !SECTION_IS_RO */
+			     "characters, up to 'num_chars' total.");
+#endif /* !SECTION_IS_RO */
diff --git a/common/charger.c b/common/charger.c
index 8dae2e71e8..c19dd85832 100644
--- a/common/charger.c
+++ b/common/charger.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -18,7 +18,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CHARGER, outstr)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 /* DPTF current limit, -1 = none */
 static int dptf_limit_ma = -1;
@@ -71,7 +71,7 @@ int charger_closest_voltage(int voltage)
 
 int charger_closest_current(int current)
 {
-	const struct charger_info * const info = charger_get_info();
+	const struct charger_info *const info = charger_get_info();
 
 	/* Apply DPTF limit if necessary */
 	if (dptf_limit_ma >= 0 && current > dptf_limit_ma)
@@ -146,7 +146,7 @@ void print_charger_debug(int chgnum)
 	/* option */
 	print_item_name("Option:");
 	if (check_print_error(charger_get_option(&d)))
-		ccprintf("%pb (0x%04x)\n", BINARY_VALUE(d, 16), d);
+		ccprintf("(0x%04x)\n", d);
 
 	/* manufacturer id */
 	print_item_name("Man id:");
@@ -184,7 +184,7 @@ void print_charger_debug(int chgnum)
 		ccputs("disabled\n");
 }
 
-static int command_charger(int argc, char **argv)
+static int command_charger(int argc, const char **argv)
 {
 	int d;
 	char *e;
@@ -210,41 +210,43 @@ static int command_charger(int argc, char **argv)
 		return EC_SUCCESS;
 	}
 
-	if (strcasecmp(argv[1+idx_provided], "input") == 0) {
-		d = strtoi(argv[2+idx_provided], &e, 0);
+	if (strcasecmp(argv[1 + idx_provided], "input") == 0) {
+		d = strtoi(argv[2 + idx_provided], &e, 0);
 		if (*e)
-			return EC_ERROR_PARAM2+idx_provided;
+			return EC_ERROR_PARAM2 + idx_provided;
 		return charger_set_input_current_limit(chgnum, d);
-	} else if (strcasecmp(argv[1+idx_provided], "current") == 0) {
-		d = strtoi(argv[2+idx_provided], &e, 0);
+	} else if (IS_ENABLED(CONFIG_BATTERY) &&
+		   strcasecmp(argv[1 + idx_provided], "current") == 0) {
+		d = strtoi(argv[2 + idx_provided], &e, 0);
 		if (*e)
-			return EC_ERROR_PARAM2+idx_provided;
+			return EC_ERROR_PARAM2 + idx_provided;
 		chgstate_set_manual_current(d);
 		return charger_set_current(chgnum, d);
-	} else if (strcasecmp(argv[1+idx_provided], "voltage") == 0) {
-		d = strtoi(argv[2+idx_provided], &e, 0);
+	} else if (IS_ENABLED(CONFIG_BATTERY) &&
+		   strcasecmp(argv[1 + idx_provided], "voltage") == 0) {
+		d = strtoi(argv[2 + idx_provided], &e, 0);
 		if (*e)
-			return EC_ERROR_PARAM2+idx_provided;
+			return EC_ERROR_PARAM2 + idx_provided;
 		chgstate_set_manual_voltage(d);
 		return charger_set_voltage(chgnum, d);
-	} else if (strcasecmp(argv[1+idx_provided], "dptf") == 0) {
-		d = strtoi(argv[2+idx_provided], &e, 0);
+	} else if (strcasecmp(argv[1 + idx_provided], "dptf") == 0) {
+		d = strtoi(argv[2 + idx_provided], &e, 0);
 		if (*e)
-			return EC_ERROR_PARAM2+idx_provided;
+			return EC_ERROR_PARAM2 + idx_provided;
 		dptf_limit_ma = d;
 		return EC_SUCCESS;
-	} else if (strcasecmp(argv[1+idx_provided], "dump") == 0) {
+	} else if (strcasecmp(argv[1 + idx_provided], "dump") == 0) {
 		if (!IS_ENABLED(CONFIG_CMD_CHARGER_DUMP) ||
-				!chg_chips[chgnum].drv->dump_registers) {
+		    !chg_chips[chgnum].drv->dump_registers) {
 			ccprintf("dump not supported\n");
-			return EC_ERROR_PARAM1+idx_provided;
+			return EC_ERROR_PARAM1 + idx_provided;
 		}
 		ccprintf("Dump %s registers\n",
-				chg_chips[chgnum].drv->get_info(chgnum)->name);
+			 chg_chips[chgnum].drv->get_info(chgnum)->name);
 		chg_chips[chgnum].drv->dump_registers(chgnum);
 		return EC_SUCCESS;
 	} else {
-		return EC_ERROR_PARAM1+idx_provided;
+		return EC_ERROR_PARAM1 + idx_provided;
 	}
 }
 
@@ -500,7 +502,7 @@ enum ec_error_list charger_enable_bypass_mode(int chgnum, int enable)
 	return chg_chips[chgnum].drv->enable_bypass_mode(chgnum, enable);
 }
 
-enum ec_error_list charger_get_vbus_voltage(int port, int *voltage)
+static int charger_get_valid_chgnum(int port)
 {
 	int chgnum = 0;
 
@@ -510,15 +512,38 @@ enum ec_error_list charger_get_vbus_voltage(int port, int *voltage)
 
 	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
 		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
-		return 0;
+		return -1;
 	}
 
+	return chgnum;
+}
+
+enum ec_error_list charger_get_vbus_voltage(int port, int *voltage)
+{
+	int chgnum = charger_get_valid_chgnum(port);
+
+	if (chgnum < 0)
+		return EC_ERROR_INVAL;
+
 	if (!chg_chips[chgnum].drv->get_vbus_voltage)
 		return EC_ERROR_UNIMPLEMENTED;
 
 	return chg_chips[chgnum].drv->get_vbus_voltage(chgnum, port, voltage);
 }
 
+enum ec_error_list charger_get_vsys_voltage(int port, int *voltage)
+{
+	int chgnum = charger_get_valid_chgnum(port);
+
+	if (chgnum < 0)
+		return EC_ERROR_INVAL;
+
+	if (!chg_chips[chgnum].drv->get_vsys_voltage)
+		return EC_ERROR_UNIMPLEMENTED;
+
+	return chg_chips[chgnum].drv->get_vsys_voltage(chgnum, port, voltage);
+}
+
 enum ec_error_list charger_set_input_current_limit(int chgnum,
 						   int input_current)
 {
@@ -644,12 +669,16 @@ enum ec_error_list charger_set_hw_ramp(int enable)
 			if (enable) {
 				/* Check if this is the active chg chip. */
 				if (chgnum == charge_get_active_chg_chip())
-					rv = chg_chips[chgnum].drv->set_hw_ramp(chgnum, 1);
-				/* This is not the active chg chip, disable hw_ramp. */
+					rv = chg_chips[chgnum].drv->set_hw_ramp(
+						chgnum, 1);
+				/* This is not the active chg chip, disable
+				 * hw_ramp. */
 				else
-					rv = chg_chips[chgnum].drv->set_hw_ramp(chgnum, 0);
+					rv = chg_chips[chgnum].drv->set_hw_ramp(
+						chgnum, 0);
 			} else
-				rv = chg_chips[chgnum].drv->set_hw_ramp(chgnum, 0);
+				rv = chg_chips[chgnum].drv->set_hw_ramp(chgnum,
+									0);
 		}
 	}
 
@@ -705,8 +734,7 @@ int chg_ramp_get_current_limit(void)
 
 enum ec_error_list charger_set_vsys_compensation(int chgnum,
 						 struct ocpc_data *ocpc,
-						 int current_ma,
-						 int voltage_mv)
+						 int current_ma, int voltage_mv)
 {
 	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
 		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
@@ -726,7 +754,7 @@ enum ec_error_list charger_set_vsys_compensation(int chgnum,
 
 enum ec_error_list charger_is_icl_reached(int chgnum, bool *reached)
 {
-		if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
+	if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) {
 		CPRINTS("%s(%d) Invalid charger!", __func__, chgnum);
 		return EC_ERROR_INVAL;
 	}
@@ -750,3 +778,10 @@ enum ec_error_list charger_enable_linear_charge(int chgnum, bool enable)
 
 	return EC_ERROR_UNIMPLEMENTED;
 }
+
+#ifdef CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON
+inline int charger_get_min_bat_pct_for_power_on(void)
+{
+	return CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON;
+}
+#endif
diff --git a/common/charger_profile_override.c b/common/charger_profile_override.c
index 2b691b9a5a..00aaa2b5bd 100644
--- a/common/charger_profile_override.c
+++ b/common/charger_profile_override.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -20,17 +20,17 @@ static int test_vtg_mV = -1;
 
 static int fast_charging_allowed = 1;
 
-int charger_profile_override_common(struct charge_state_data *curr,
-			const struct fast_charge_params *fast_chg_params,
-			const struct fast_charge_profile **prev_chg_prof_info,
-			int batt_vtg_max)
+int charger_profile_override_common(
+	struct charge_state_data *curr,
+	const struct fast_charge_params *fast_chg_params,
+	const struct fast_charge_profile **prev_chg_prof_info, int batt_vtg_max)
 {
 	int i, voltage_range;
 	/* temp in 0.1 deg C */
 	int temp_c = curr->batt.temperature - 2731;
 	int temp_ranges = fast_chg_params->total_temp_ranges;
 	const struct fast_charge_profile *chg_profile_info =
-				fast_chg_params->chg_profile_info;
+		fast_chg_params->chg_profile_info;
 
 #ifdef CONFIG_CMD_CHARGER_PROFILE_OVERRIDE_TEST
 	if (fast_charge_test_on && test_vtg_mV != -1) {
@@ -78,9 +78,9 @@ int charger_profile_override_common(struct charge_state_data *curr,
 
 	if (!(curr->batt.flags & BATT_FLAG_BAD_VOLTAGE)) {
 		for (i = 0; i < CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES - 1;
-			i++) {
+		     i++) {
 			if (curr->batt.voltage <
-					fast_chg_params->voltage_mV[i]) {
+			    fast_chg_params->voltage_mV[i]) {
 				voltage_range = i;
 				break;
 			}
@@ -98,13 +98,13 @@ int charger_profile_override_common(struct charge_state_data *curr,
 	 * Okay, impose our custom will:
 	 */
 	curr->requested_current =
-			(*prev_chg_prof_info)->current_mA[voltage_range];
+		(*prev_chg_prof_info)->current_mA[voltage_range];
 	curr->requested_voltage = curr->requested_current ? batt_vtg_max : 0;
 
 #ifdef CONFIG_CMD_CHARGER_PROFILE_OVERRIDE_TEST
 	if (fast_charge_test_on)
 		ccprintf("Fast charge profile i=%dmA, v=%dmV\n",
-			curr->requested_current, curr->requested_voltage);
+			 curr->requested_current, curr->requested_voltage);
 #endif
 
 	return 0;
@@ -134,7 +134,7 @@ enum ec_status charger_profile_override_set_param(uint32_t param,
 }
 
 #ifdef CONFIG_CMD_CHARGER_PROFILE_OVERRIDE
-static int command_fastcharge(int argc, char **argv)
+static int command_fastcharge(int argc, const char **argv)
 {
 	if (argc > 1 && !parse_bool(argv[1], &fast_charging_allowed))
 		return EC_ERROR_PARAM1;
@@ -143,8 +143,7 @@ static int command_fastcharge(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(fastcharge, command_fastcharge,
-			"[on|off]",
+DECLARE_CONSOLE_COMMAND(fastcharge, command_fastcharge, "[on|off]",
 			"Get or set fast charging profile");
 #endif
 
@@ -153,7 +152,7 @@ DECLARE_CONSOLE_COMMAND(fastcharge, command_fastcharge,
  * fast charging profile is selected.
  */
 #ifdef CONFIG_CMD_CHARGER_PROFILE_OVERRIDE_TEST
-static int command_fastcharge_test(int argc, char **argv)
+static int command_fastcharge_test(int argc, const char **argv)
 {
 	char *e;
 	int test_on;
diff --git a/common/chargesplash.c b/common/chargesplash.c
index 88bc6a63f1..17da9a5c8c 100644
--- a/common/chargesplash.c
+++ b/common/chargesplash.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -171,7 +171,7 @@ static void handle_chipset_shutdown(void)
 }
 DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, handle_chipset_shutdown, HOOK_PRIO_DEFAULT);
 
-static int command_chargesplash(int argc, char **argv)
+static int command_chargesplash(int argc, const char **argv)
 {
 	if (argc != 2) {
 		return EC_ERROR_PARAM_COUNT;
diff --git a/common/chipset.c b/common/chipset.c
index 61478f184a..55964e4ba9 100644
--- a/common/chipset.c
+++ b/common/chipset.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,30 +18,27 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 /*****************************************************************************/
 /* Console commands */
 
 #ifdef CONFIG_CMD_POWER_AP
-static int command_apreset(int argc, char **argv)
+static int command_apreset(int argc, const char **argv)
 {
 	/* Force the chipset to reset */
 	ccprintf("Issuing AP reset...\n");
 	chipset_reset(CHIPSET_RESET_CONSOLE_CMD);
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(apreset, command_apreset,
-			NULL,
-			"Issue AP reset");
+DECLARE_CONSOLE_COMMAND(apreset, command_apreset, NULL, "Issue AP reset");
 
-static int command_apshutdown(int argc, char **argv)
+static int command_apshutdown(int argc, const char **argv)
 {
 	chipset_force_shutdown(CHIPSET_SHUTDOWN_CONSOLE_CMD);
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(apshutdown, command_apshutdown,
-			NULL,
+DECLARE_CONSOLE_COMMAND(apshutdown, command_apshutdown, NULL,
 			"Force AP shutdown");
 
 #endif
@@ -53,9 +50,7 @@ static enum ec_status host_command_apreset(struct host_cmd_handler_args *args)
 	chipset_reset(CHIPSET_RESET_HOST_CMD);
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_AP_RESET,
-		     host_command_apreset,
-		     EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_AP_RESET, host_command_apreset, EC_VER_MASK(0));
 
 #endif
 
@@ -64,8 +59,7 @@ K_MUTEX_DEFINE(reset_log_mutex);
 static int next_reset_log __preserved_logs(next_reset_log);
 static uint32_t ap_resets_since_ec_boot;
 /* keep reset_logs size a power of 2 */
-static struct ap_reset_log_entry
-		reset_logs[4] __preserved_logs(reset_logs);
+static struct ap_reset_log_entry reset_logs[4] __preserved_logs(reset_logs);
 static int reset_log_checksum __preserved_logs(reset_log_checksum);
 
 /* Calculate reset log checksum */
@@ -113,11 +107,10 @@ get_ap_reset_stats(struct ap_reset_log_entry *reset_log_entries,
 
 	mutex_lock(&reset_log_mutex);
 	*resets_since_ec_boot = ap_resets_since_ec_boot;
-	for (i = 0;
-	     i != ARRAY_SIZE(reset_logs) && i != num_reset_log_entries;
+	for (i = 0; i != ARRAY_SIZE(reset_logs) && i != num_reset_log_entries;
 	     ++i) {
 		log_address = (next_reset_log + i) &
-			(ARRAY_SIZE(reset_logs) - 1);
+			      (ARRAY_SIZE(reset_logs) - 1);
 		reset_log_entries[i] = reset_logs[log_address];
 	}
 	mutex_unlock(&reset_log_mutex);
@@ -125,4 +118,19 @@ get_ap_reset_stats(struct ap_reset_log_entry *reset_log_entries,
 	return EC_SUCCESS;
 }
 
-#endif  /* !CONFIG_AP_RESET_LOG */
+enum chipset_shutdown_reason chipset_get_shutdown_reason(void)
+{
+	enum chipset_shutdown_reason reason = CHIPSET_RESET_UNKNOWN;
+
+	mutex_lock(&reset_log_mutex);
+	if (ap_resets_since_ec_boot != 0) {
+		int i = (next_reset_log == 0) ? ARRAY_SIZE(reset_logs) - 1 :
+						next_reset_log - 1;
+		reason = reset_logs[i].reset_cause;
+	}
+	mutex_unlock(&reset_log_mutex);
+
+	return reason;
+}
+
+#endif /* !CONFIG_AP_RESET_LOG */
diff --git a/common/clz.c b/common/clz.c
index b0b58e76a0..178c44d345 100644
--- a/common/clz.c
+++ b/common/clz.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/common/console.c b/common/console.c
index dc0d2655c0..9e7d6ad036 100644
--- a/common/console.c
+++ b/common/console.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -52,14 +52,14 @@ static int last_rx_was_cr;
 #ifndef CONFIG_EXPERIMENTAL_CONSOLE
 /* State of input escape code */
 static enum {
-	ESC_OUTSIDE,   /* Not in escape code */
-	ESC_START,     /* Got ESC */
-	ESC_BAD,       /* Bad escape sequence */
-	ESC_BRACKET,   /* Got ESC [ */
+	ESC_OUTSIDE, /* Not in escape code */
+	ESC_START, /* Got ESC */
+	ESC_BAD, /* Bad escape sequence */
+	ESC_BRACKET, /* Got ESC [ */
 	ESC_BRACKET_1, /* Got ESC [ 1 */
 	ESC_BRACKET_3, /* Got ESC [ 3 */
 	ESC_BRACKET_4, /* Got ESC [ 4 */
-	ESC_O,         /* Got ESC O */
+	ESC_O, /* Got ESC O */
 } esc_state;
 #endif /* !defined(CONFIG_EXPERIMENTAL_CONSOLE) */
 
@@ -85,7 +85,7 @@ enum extended_key_code {
  * @return EC_SUCCESS.  If more than MAX_ARGS_PER_COMMAND words are found,
  *	discards the excess and returns EC_ERROR_OVERFLOW.
  */
-static int split_words(char *input, int *argc, char **argv)
+static int split_words(char *input, int *argc, const char **argv)
 {
 	char *c;
 	int in_word = 0;
@@ -129,7 +129,7 @@ static int split_words(char *input, int *argc, char **argv)
  *
  * @return A pointer to the command structure, or NULL if no match found.
  */
-static const struct console_command *find_command(char *name)
+static const struct console_command *find_command(const char *name)
 {
 	const struct console_command *cmd, *match = NULL;
 	int match_length = strlen(name);
@@ -151,18 +151,10 @@ static const struct console_command *find_command(char *name)
 	return match;
 }
 
-
 static const char *const errmsgs[] = {
-	"OK",
-	"Unknown error",
-	"Unimplemented",
-	"Overflow",
-	"Timeout",
-	"Invalid argument",
-	"Busy",
-	"Access Denied",
-	"Not Powered",
-	"Not Calibrated",
+	"OK",	       "Unknown error",	   "Unimplemented", "Overflow",
+	"Timeout",     "Invalid argument", "Busy",	    "Access Denied",
+	"Not Powered", "Not Calibrated",
 };
 
 /**
@@ -175,7 +167,7 @@ static const char *const errmsgs[] = {
 static int handle_command(char *input)
 {
 	const struct console_command *cmd;
-	char *argv[MAX_ARGS_PER_COMMAND];
+	const char *argv[MAX_ARGS_PER_COMMAND];
 	int argc = 0;
 	int rv;
 #ifdef CONFIG_EXPERIMENTAL_CONSOLE
@@ -205,10 +197,10 @@ static int handle_command(char *input)
 	i = input[1] == '&' ? 2 : 1;
 
 	/* Next, there should be 4 hex digits: XXYY + '&' */
-	if (i+5 > input_len)
+	if (i + 5 > input_len)
 		goto command_has_error;
 	/* Replace the '&' with null so we can call strtoi(). */
-	input[i+4] = 0;
+	input[i + 4] = 0;
 	j = strtoi(input + i, &e, 16);
 	if (*e)
 		goto command_has_error;
@@ -218,10 +210,10 @@ static int handle_command(char *input)
 	i += 5;
 
 	/* Lastly, verify the CRC8 of the command. */
-	if (i+command_len > input_len)
+	if (i + command_len > input_len)
 		goto command_has_error;
 	if (packed_crc8 != cros_crc8(&input[i], command_len)) {
-command_has_error:
+	command_has_error:
 		/* Send back the error string. */
 		ccprintf("&&EE\n");
 		return EC_ERROR_UNKNOWN;
@@ -248,7 +240,7 @@ command_has_error:
 		rv = EC_ERROR_ACCESS_DENIED;
 	else
 #endif
-	rv = cmd->handler(argc, argv);
+		rv = cmd->handler(argc, argv);
 	if (rv == EC_SUCCESS)
 		return rv;
 
@@ -372,7 +364,7 @@ static void save_history(void)
 static void handle_backspace(void)
 {
 	if (!input_pos)
-		return;  /* Already at beginning of line */
+		return; /* Already at beginning of line */
 
 	/* Move cursor back */
 	console_putc('\b');
@@ -380,8 +372,7 @@ static void handle_backspace(void)
 	/* Print and move anything following the cursor position */
 	if (input_pos != input_len) {
 		ccputs(input_buf + input_pos);
-		memmove(input_buf + input_pos - 1,
-			input_buf + input_pos,
+		memmove(input_buf + input_pos - 1, input_buf + input_pos,
 			input_len - input_pos + 1);
 	} else {
 		input_buf[input_len - 1] = '\0';
@@ -511,7 +502,7 @@ static void console_handle_char(int c)
 #ifndef CONFIG_EXPERIMENTAL_CONSOLE
 	case KEY_DEL:
 		if (input_pos == input_len)
-			break;  /* Already at end */
+			break; /* Already at end */
 
 		move_cursor_right();
 
@@ -544,8 +535,8 @@ static void console_handle_char(int c)
 		/* Save command in history buffer */
 		if (input_len) {
 			save_history();
-			history_next = (history_next + 1) %
-				CONFIG_CONSOLE_HISTORY;
+			history_next =
+				(history_next + 1) % CONFIG_CONSOLE_HISTORY;
 			history_pos = history_next;
 		}
 #endif
@@ -692,7 +683,7 @@ void console_task(void *u)
 			console_handle_char(c);
 		}
 
-		task_wait_event(-1);  /* Wait for more input */
+		task_wait_event(-1); /* Wait for more input */
 	}
 }
 
@@ -700,10 +691,10 @@ void console_task(void *u)
 /* Console commands */
 
 /* Command handler - prints help. */
-static int command_help(int argc, char **argv)
+static int command_help(int argc, const char **argv)
 {
 	const int ncmds = __cmds_end - __cmds;
-	const int cols = 5;			/* printing in five columns */
+	const int cols = 5; /* printing in five columns */
 	const int rows = (ncmds + cols - 1) / cols;
 	int i, j;
 
@@ -715,16 +706,15 @@ static int command_help(int argc, char **argv)
 #ifdef CONFIG_CONSOLE_COMMAND_FLAGS
 			ccputs("Command     Flags   Description\n");
 			for (i = 0; i < ncmds; i++) {
-				ccprintf(" %-14s %x %s\n",
-					 __cmds[i].name, __cmds[i].flags,
-					 __cmds[i].help);
+				ccprintf(" %-14s %x %s\n", __cmds[i].name,
+					 __cmds[i].flags, __cmds[i].help);
 				cflush();
 			}
 #else
 			ccputs("Known commands:\n");
 			for (i = 0; i < ncmds; i++) {
-				ccprintf("  %-15s%s\n",
-					 __cmds[i].name, __cmds[i].help);
+				ccprintf("  %-15s%s\n", __cmds[i].name,
+					 __cmds[i].help);
 				cflush();
 			}
 #endif
@@ -771,12 +761,11 @@ static int command_help(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_SAFE_CONSOLE_COMMAND(help, command_help,
-			     "[ list | <name> ]",
+DECLARE_SAFE_CONSOLE_COMMAND(help, command_help, "[ list | <name> ]",
 			     "Print command help");
 
 #ifdef CONFIG_CONSOLE_HISTORY
-static int command_history(int argc, char **argv)
+static int command_history(int argc, const char **argv)
 {
 	int i;
 
@@ -788,7 +777,6 @@ static int command_history(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_SAFE_CONSOLE_COMMAND(history, command_history,
-			     NULL,
+DECLARE_SAFE_CONSOLE_COMMAND(history, command_history, NULL,
 			     "Print console history");
 #endif
diff --git a/common/console_output.c b/common/console_output.c
index 33b1466181..24bdb5aa3a 100644
--- a/common/console_output.c
+++ b/common/console_output.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,6 +6,7 @@
 /* Console output module for Chrome EC */
 
 #include "console.h"
+#include "printf.h"
 #include "uart.h"
 #include "usb_console.h"
 #include "util.h"
@@ -27,14 +28,14 @@ static uint32_t channel_mask_saved = CC_DEFAULT;
  * might also become more important if we have >32 channels - for example, if
  * we decide to replace enum console_channel with enum module_id.
  */
-static const char * const channel_names[] = {
-	#define CONSOLE_CHANNEL(enumeration, string) string,
-	#include "console_channel.inc"
-	#undef CONSOLE_CHANNEL
+static const char *const channel_names[] = {
+#define CONSOLE_CHANNEL(enumeration, string) string,
+#include "console_channel.inc"
+#undef CONSOLE_CHANNEL
 };
 BUILD_ASSERT(ARRAY_SIZE(channel_names) == CC_CHANNEL_COUNT);
 /* ensure that we are not silently masking additional channels */
-BUILD_ASSERT(CC_CHANNEL_COUNT <= 8*sizeof(uint32_t));
+BUILD_ASSERT(CC_CHANNEL_COUNT <= 8 * sizeof(uint32_t));
 
 static int console_channel_name_to_index(const char *name)
 {
@@ -114,12 +115,14 @@ int cprints(enum console_channel channel, const char *format, ...)
 {
 	int r, rv;
 	va_list args;
+	char ts_str[PRINTF_TIMESTAMP_BUF_SIZE];
 
 	/* Filter out inactive channels */
 	if (console_channel_is_disabled(channel))
 		return EC_SUCCESS;
 
-	rv = cprintf(channel, "[%pT ", PRINTF_TIMESTAMP_NOW);
+	snprintf_timestamp_now(ts_str, sizeof(ts_str));
+	rv = cprintf(channel, "[%s ", ts_str);
 
 	va_start(args, format);
 	r = uart_vprintf(format, args);
@@ -148,7 +151,7 @@ void cflush(void)
 
 #ifdef CONFIG_CONSOLE_CHANNEL
 /* Set active channels */
-static int command_ch(int argc, char **argv)
+static int command_ch(int argc, const char **argv)
 {
 	int i;
 	char *e;
@@ -178,15 +181,13 @@ static int command_ch(int argc, char **argv)
 	/* Print the list of channels */
 	ccputs(" # Mask     E Channel\n");
 	for (i = 0; i < CC_CHANNEL_COUNT; i++) {
-		ccprintf("%2d %08x %c %s\n",
-			 i, CC_MASK(i),
+		ccprintf("%2d %08x %c %s\n", i, CC_MASK(i),
 			 (channel_mask & CC_MASK(i)) ? '*' : ' ',
 			 channel_names[i]);
 		cflush();
 	}
 	return EC_SUCCESS;
 };
-DECLARE_SAFE_CONSOLE_COMMAND(chan, command_ch,
-			     "[ save | restore | <mask> ]",
+DECLARE_SAFE_CONSOLE_COMMAND(chan, command_ch, "[ save | restore | <mask> ]",
 			     "Save, restore, get or set console channel mask");
 #endif /* CONFIG_CONSOLE_CHANNEL */
diff --git a/common/crc.c b/common/crc.c
index 8b45150b67..a53cf91d47 100644
--- a/common/crc.c
+++ b/common/crc.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/common/crc8.c b/common/crc8.c
index 8098fa74eb..0aba3e80a3 100644
--- a/common/crc8.c
+++ b/common/crc8.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/common/ctz.c b/common/ctz.c
index bb6f69624e..ad144225f0 100644
--- a/common/ctz.c
+++ b/common/ctz.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -20,8 +20,8 @@
 int __keep __ctzsi2(int x)
 {
 	static const uint8_t MulDeBruijnBitPos[32] = {
-		0, 1, 28, 2, 29, 14, 24, 3, 30, 22, 20, 15, 25, 17, 4, 8,
-		31, 27, 13, 23, 21, 19, 16, 7, 26, 12, 18, 6, 11, 5, 10, 9
+		0,  1,	28, 2,	29, 14, 24, 3, 30, 22, 20, 15, 25, 17, 4,  8,
+		31, 27, 13, 23, 21, 19, 16, 7, 26, 12, 18, 6,  11, 5,  10, 9
 	};
 	return MulDeBruijnBitPos[((uint32_t)((x & -x) * 0x077CB531U)) >> 27];
 }
diff --git a/common/device_event.c b/common/device_event.c
index 748a98ae8f..b9e1bafc69 100644
--- a/common/device_event.c
+++ b/common/device_event.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,7 +15,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_EVENTS, outstr)
-#define CPRINTS(format, args...) cprints(CC_EVENTS, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_EVENTS, format, ##args)
 
 static atomic_t device_current_events;
 static atomic_t device_enabled_events;
@@ -87,7 +87,7 @@ void device_enable_event(enum ec_device_event event)
 /* Console commands */
 
 #ifdef CONFIG_CMD_DEVICE_EVENT
-static int command_device_event(int argc, char **argv)
+static int command_device_event(int argc, const char **argv)
 {
 	/* Handle sub-commands */
 	if (argc == 3) {
diff --git a/common/device_state.c b/common/device_state.c
index 0ba94d6115..1739a9beb2 100644
--- a/common/device_state.c
+++ b/common/device_state.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,7 +7,7 @@
 #include "device_state.h"
 #include "hooks.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 /**
  * Return text description for a state
@@ -17,8 +17,9 @@
  */
 static const char *state_desc(enum device_state state)
 {
-	return state == DEVICE_STATE_ON ? "on" :
-			state == DEVICE_STATE_OFF ? "off" : "unknown";
+	return state == DEVICE_STATE_ON	 ? "on" :
+	       state == DEVICE_STATE_OFF ? "off" :
+					   "unknown";
 }
 
 enum device_state device_get_state(enum device_type device)
@@ -65,7 +66,7 @@ static void check_device_state(void)
 }
 DECLARE_HOOK(HOOK_SECOND, check_device_state, HOOK_PRIO_DEFAULT);
 
-static int command_devices(int argc, char **argv)
+static int command_devices(int argc, const char **argv)
 {
 	const struct device_config *dc = device_states;
 	int i;
@@ -78,6 +79,5 @@ static int command_devices(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_SAFE_CONSOLE_COMMAND(devices, command_devices,
-			     "",
+DECLARE_SAFE_CONSOLE_COMMAND(devices, command_devices, "",
 			     "Get the device states");
diff --git a/common/dps.c b/common/dps.c
index 3af25e6280..13f551a95d 100644
--- a/common/dps.c
+++ b/common/dps.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -7,15 +7,14 @@
 
 #include <stdint.h>
 
-#include "adc.h"
 #include "dps.h"
 #include "atomic.h"
 #include "battery.h"
+#include "common.h"
 #include "console.h"
 #include "charger.h"
 #include "charge_manager.h"
 #include "charge_state.h"
-#include "charge_state_v2.h"
 #include "ec_commands.h"
 #include "math_util.h"
 #include "task.h"
@@ -23,8 +22,6 @@
 #include "usb_common.h"
 #include "usb_pd.h"
 #include "util.h"
-#include "usb_pe_sm.h"
-
 
 #define K_MORE_PWR 96
 #define K_LESS_PWR 93
@@ -33,17 +30,16 @@
 #define T_REQUEST_STABLE_TIME (10 * SECOND)
 #define T_NEXT_CHECK_TIME (5 * SECOND)
 
-#define DPS_FLAG_DISABLED		BIT(0)
-#define DPS_FLAG_NO_SRCCAP		BIT(1)
-#define DPS_FLAG_WAITING		BIT(2)
-#define DPS_FLAG_SAMPLED		BIT(3)
-#define DPS_FLAG_NEED_MORE_PWR		BIT(4)
+#define DPS_FLAG_DISABLED BIT(0)
+#define DPS_FLAG_NO_SRCCAP BIT(1)
+#define DPS_FLAG_WAITING BIT(2)
+#define DPS_FLAG_SAMPLED BIT(3)
+#define DPS_FLAG_NEED_MORE_PWR BIT(4)
 
-#define DPS_FLAG_STOP_EVENTS		(DPS_FLAG_DISABLED | \
-					 DPS_FLAG_NO_SRCCAP)
-#define DPS_FLAG_ALL			GENMASK(31, 0)
+#define DPS_FLAG_STOP_EVENTS (DPS_FLAG_DISABLED | DPS_FLAG_NO_SRCCAP)
+#define DPS_FLAG_ALL GENMASK(31, 0)
 
-#define MAX_MOVING_AVG_WINDOW		5
+#define MAX_MOVING_AVG_WINDOW 5
 
 BUILD_ASSERT(K_MORE_PWR > K_LESS_PWR && 100 >= K_MORE_PWR && 100 >= K_LESS_PWR);
 
@@ -71,6 +67,11 @@ __overridable struct dps_config_t dps_config = {
 	.is_more_efficient = NULL,
 };
 
+__test_only struct dps_config_t *dps_get_config(void)
+{
+	return &dps_config;
+}
+
 int dps_get_dynamic_voltage(void)
 {
 	return dynamic_mv;
@@ -86,14 +87,15 @@ bool dps_is_enabled(void)
 	return is_enabled;
 }
 
-static void dps_enable(bool en)
+test_export_static void dps_enable(bool en)
 {
 	bool prev_en = is_enabled;
 
 	is_enabled = en;
 
-	if (is_enabled && !prev_en)
+	if (is_enabled && !prev_en) {
 		task_wake(TASK_ID_DPS);
+	}
 
 	if (!is_enabled) {
 		/* issue a new PD request for a default voltage */
@@ -126,22 +128,24 @@ static void dps_reset(void)
 /*
  * DPS initialization.
  */
-static void dps_init(void)
+test_export_static int dps_init(void)
 {
+	int rc = EC_SUCCESS;
+
 	dps_reset();
 
 	if (dps_config.k_window > MAX_MOVING_AVG_WINDOW) {
-		dps_config.k_window = MAX_MOVING_AVG_WINDOW;
 		CPRINTS("ERR:WIN");
+		rc = EC_ERROR_INVALID_CONFIG;
 	}
 
-	if (dps_config.k_less_pwr > 100 ||
-	    dps_config.k_more_pwr > 100 ||
+	if (dps_config.k_less_pwr > 100 || dps_config.k_more_pwr > 100 ||
 	    dps_config.k_more_pwr <= dps_config.k_less_pwr) {
-		dps_config.k_less_pwr = K_LESS_PWR;
-		dps_config.k_more_pwr = K_MORE_PWR;
 		CPRINTS("ERR:COEF");
+		rc = EC_ERROR_INVALID_CONFIG;
 	}
+
+	return rc;
 }
 
 static bool is_near_limit(int val, int limit)
@@ -197,6 +201,26 @@ static int get_desired_input_power(int *vbus, int *input_current)
 	return (*vbus) * (*input_current) / 1000;
 }
 
+static int get_battery_target_voltage(int *target_mv)
+{
+	int charger_id = charge_get_active_chg_chip();
+	int error = charger_get_voltage(charger_id, target_mv);
+
+	if (!error) {
+		return EC_SUCCESS;
+	}
+	if (error != EC_ERROR_UNIMPLEMENTED) {
+		CPRINTS("Failed to get voltage for charge port %d: %d",
+			charger_id, error);
+		return error;
+	}
+	/*
+	 * Fall back to battery design voltage if charger output voltage
+	 * is not available.
+	 */
+	return battery_design_voltage(target_mv);
+}
+
 /*
  * Get the most efficient PDO voltage for the battery of the charging port
  *
@@ -224,7 +248,7 @@ int get_efficient_voltage(void)
 	if (!input_pwr)
 		return 0;
 
-	if (battery_design_voltage(&batt_mv))
+	if (get_battery_target_voltage(&batt_mv))
 		return 0;
 
 	batt_pwr = batt->current * batt->voltage / 1000;
@@ -258,16 +282,16 @@ struct pdo_candidate {
 };
 
 #define UPDATE_CANDIDATE(new_port, new_mv, new_mw) \
-	do { \
-		cand->port = new_port; \
-		cand->mv = new_mv; \
-		cand->mw = new_mw; \
+	do {                                       \
+		cand->port = new_port;             \
+		cand->mv = new_mv;                 \
+		cand->mw = new_mw;                 \
 	} while (0)
 
-#define CLEAR_AND_RETURN() \
-	do { \
+#define CLEAR_AND_RETURN()            \
+	do {                          \
 		moving_avg_count = 0; \
-		return false; \
+		return false;         \
 	} while (0)
 
 /*
@@ -276,7 +300,7 @@ struct pdo_candidate {
  * @param struct pdo_candidate: The candidate PDO. (Return value)
  * @return true if a new power request, or false otherwise.
  */
-static bool has_new_power_request(struct pdo_candidate *cand)
+__maybe_unused static bool has_new_power_request(struct pdo_candidate *cand)
 {
 	int vbus, input_curr, input_pwr;
 	int input_pwr_avg = 0, input_curr_avg = 0;
@@ -305,7 +329,7 @@ static bool has_new_power_request(struct pdo_candidate *cand)
 	if (!req_mv)
 		CLEAR_AND_RETURN();
 
-	if (battery_design_voltage(&batt_mv))
+	if (get_battery_target_voltage(&batt_mv))
 		CLEAR_AND_RETURN();
 
 	/* if last sample is not the same as the current one, reset counting. */
@@ -360,7 +384,7 @@ static bool has_new_power_request(struct pdo_candidate *cand)
 			input_curr, input_pwr_avg, input_curr_avg);
 
 	for (int i = 0; i < board_get_usb_pd_port_count(); ++i) {
-		const uint32_t * const src_caps = pd_get_src_caps(i);
+		const uint32_t *const src_caps = pd_get_src_caps(i);
 
 		/* If the port is not SNK, skip evaluating this port. */
 		if (pd_get_power_role(i) != PD_ROLE_SINK)
@@ -380,7 +404,7 @@ static bool has_new_power_request(struct pdo_candidate *cand)
 			if (mv > max_mv)
 				continue;
 
-			mw = ma * mv / 1000;
+			mw = MIN(ma, PD_MAX_CURRENT_MA) * mv / 1000;
 			efficient = is_more_efficient(mv, cand->mv, batt_mv,
 						      batt_pwr, input_pwr_avg);
 
@@ -419,7 +443,6 @@ static bool has_new_power_request(struct pdo_candidate *cand)
 				}
 			}
 
-
 			/*
 			 * if the candidate is the same as the current one, pick
 			 * the one at active charge port.
@@ -436,7 +459,7 @@ static bool has_new_power_request(struct pdo_candidate *cand)
 	return (cand->mv != req_mv);
 }
 
-static bool has_srccap(void)
+__maybe_unused static bool has_srccap(void)
 {
 	for (int i = 0; i < board_get_usb_pd_port_count(); ++i) {
 		if (pd_is_connected(i) &&
@@ -454,14 +477,20 @@ void dps_update_stabilized_time(int port)
 
 void dps_task(void *u)
 {
-	struct pdo_candidate last_cand = {CHARGE_PORT_NONE, 0, 0};
+	struct pdo_candidate last_cand = { CHARGE_PORT_NONE, 0, 0 };
 	int sample_count = 0;
+	int rv;
+
+	rv = dps_init();
+	if (rv) {
+		CPRINTS("ERR:INIT%d", rv);
+		return;
+	}
 
-	dps_init();
 	update_timeout(dps_config.t_check);
 
 	while (1) {
-		struct pdo_candidate curr_cand = {CHARGE_PORT_NONE, 0, 0};
+		struct pdo_candidate curr_cand = { CHARGE_PORT_NONE, 0, 0 };
 		timestamp_t now;
 
 		now = get_time();
@@ -505,8 +534,7 @@ void dps_task(void *u)
 		if (sample_count == dps_config.k_sample) {
 			dynamic_mv = curr_cand.mv;
 			dps_port = curr_cand.port;
-			pd_dpm_request(dps_port,
-				       DPM_REQUEST_NEW_POWER_LEVEL);
+			pd_dpm_request(dps_port, DPM_REQUEST_NEW_POWER_LEVEL);
 			sample_count = 0;
 			flag &= ~(DPS_FLAG_SAMPLED | DPS_FLAG_NEED_MORE_PWR);
 		}
@@ -519,7 +547,7 @@ void dps_task(void *u)
 	}
 }
 
-static int command_dps(int argc, char **argv)
+static int command_dps(int argc, const char **argv)
 {
 	int port = charge_manager_get_active_charge_port();
 	int input_pwr, vbus, input_curr;
@@ -545,7 +573,7 @@ static int command_dps(int argc, char **argv)
 			return EC_SUCCESS;
 		}
 
-		battery_design_voltage(&batt_mv);
+		get_battery_target_voltage(&batt_mv);
 		input_pwr = get_desired_input_power(&vbus, &input_curr);
 		if (!(flag & DPS_FLAG_NO_SRCCAP)) {
 			last_mv = pd_get_requested_voltage(port);
@@ -557,10 +585,8 @@ static int command_dps(int argc, char **argv)
 			 "Efficient: %dmV\n"
 			 "Batt:      %dmv\n"
 			 "PDMaxMV:   %dmV\n",
-			 port, last_mv, last_ma,
-			 vbus, input_curr, input_pwr,
-			 get_efficient_voltage(),
-			 batt_mv,
+			 port, last_mv, last_ma, vbus, input_curr, input_pwr,
+			 get_efficient_voltage(), batt_mv,
 			 pd_get_max_voltage());
 		return EC_SUCCESS;
 	}
@@ -657,6 +683,24 @@ static enum ec_status hc_usb_pd_dps_control(struct host_cmd_handler_args *args)
 	dps_enable(p->enable);
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_USB_PD_DPS_CONTROL,
-		     hc_usb_pd_dps_control,
+DECLARE_HOST_COMMAND(EC_CMD_USB_PD_DPS_CONTROL, hc_usb_pd_dps_control,
 		     EC_VER_MASK(0));
+
+#ifdef TEST_BUILD
+__test_only bool dps_is_fake_enabled(void)
+{
+	return fake_enabled;
+}
+__test_only int dps_get_fake_mv(void)
+{
+	return fake_mv;
+}
+__test_only int dps_get_fake_ma(void)
+{
+	return fake_ma;
+}
+__test_only int *dps_get_debug_level(void)
+{
+	return &debug_level;
+}
+#endif /* TEST_BUILD */
diff --git a/common/dptf.c b/common/dptf.c
index 28ccff34f2..003ac9f32c 100644
--- a/common/dptf.c
+++ b/common/dptf.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,14 +19,14 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_DPTF, outstr)
-#define CPRINTS(format, args...) cprints(CC_DPTF, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_DPTF, format, ##args)
 
 /*****************************************************************************/
 /* DPTF temperature thresholds */
 
 static struct {
-	int temp;     /* degrees K, negative for disabled */
-	cond_t over;      /* watch for crossings */
+	int temp; /* degrees K, negative for disabled */
+	cond_t over; /* watch for crossings */
 } dptf_threshold[TEMP_SENSOR_COUNT][DPTF_THRESHOLDS_PER_SENSOR];
 _STATIC_ASSERT(TEMP_SENSOR_COUNT > 0,
 	       "CONFIG_PLATFORM_EC_DPTF enabled, but no temp sensors");
@@ -40,7 +40,6 @@ static void dptf_init(void)
 			dptf_threshold[id][t].temp = -1;
 			cond_init(&dptf_threshold[id][t].over, 0);
 		}
-
 }
 DECLARE_HOOK(HOOK_INIT, dptf_init, HOOK_PRIO_DEFAULT);
 
@@ -72,9 +71,8 @@ static int dptf_check_temp_threshold(int sensor_id, int temp)
 	}
 
 	for (i = 0; i < DPTF_THRESHOLDS_PER_SENSOR; i++) {
-
 		max = dptf_threshold[sensor_id][i].temp;
-		if (max < 0)      /* disabled? */
+		if (max < 0) /* disabled? */
 			continue;
 
 		if (temp >= max)
@@ -83,14 +81,12 @@ static int dptf_check_temp_threshold(int sensor_id, int temp)
 			cond_set_false(&dptf_threshold[sensor_id][i].over);
 
 		if (cond_went_true(&dptf_threshold[sensor_id][i].over)) {
-			CPRINTS("DPTF over threshold [%d][%d",
-				sensor_id, i);
+			CPRINTS("DPTF over threshold [%d][%d", sensor_id, i);
 			atomic_or(&dptf_seen, BIT(sensor_id));
 			tripped = 1;
 		}
 		if (cond_went_false(&dptf_threshold[sensor_id][i].over)) {
-			CPRINTS("DPTF under threshold [%d][%d",
-				sensor_id, i);
+			CPRINTS("DPTF under threshold [%d][%d", sensor_id, i);
 			atomic_or(&dptf_seen, BIT(sensor_id));
 			tripped = 1;
 		}
@@ -101,8 +97,8 @@ static int dptf_check_temp_threshold(int sensor_id, int temp)
 
 void dptf_set_temp_threshold(int sensor_id, int temp, int idx, int enable)
 {
-	CPRINTS("DPTF sensor %d, threshold %d C, index %d, %sabled",
-		sensor_id, K_TO_C(temp), idx, enable ? "en" : "dis");
+	CPRINTS("DPTF sensor %d, threshold %d C, index %d, %sabled", sensor_id,
+		K_TO_C(temp), idx, enable ? "en" : "dis");
 
 	if ((sensor_id >= TEMP_SENSOR_COUNT) ||
 	    (idx >= DPTF_THRESHOLDS_PER_SENSOR)) {
@@ -178,7 +174,7 @@ DECLARE_HOOK(HOOK_SECOND, thermal_control_dptf, HOOK_PRIO_TEMP_SENSOR_DONE);
 /*****************************************************************************/
 /* Console commands */
 
-static int command_dptftemp(int argc, char **argv)
+static int command_dptftemp(int argc, const char **argv)
 {
 	int id, t;
 	int temp, trig;
@@ -201,6 +197,5 @@ static int command_dptftemp(int argc, char **argv)
 	ccprintf("AP seen mask: 0x%08x\n", (int)dptf_seen);
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(dptftemp, command_dptftemp,
-			NULL,
+DECLARE_CONSOLE_COMMAND(dptftemp, command_dptftemp, NULL,
 			"Print DPTF thermal parameters (degrees Kelvin)");
diff --git a/common/ec.libsharedobjs.ld b/common/ec.libsharedobjs.ld
index adf5081640..57b67daecc 100644
--- a/common/ec.libsharedobjs.ld
+++ b/common/ec.libsharedobjs.ld
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/common/ec_ec_comm_client.c b/common/ec_ec_comm_client.c
index b2f2387976..193d121343 100644
--- a/common/ec_ec_comm_client.c
+++ b/common/ec_ec_comm_client.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -16,7 +16,7 @@
 #include "util.h"
 
 /* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
 
 /*
  * TODO(b:65697962): The packed structures below do not play well if we force EC
@@ -97,9 +97,8 @@ struct {
  *  - EC_ERROR_INVAL when the received header is invalid.
  *  - EC_ERROR_UNKNOWN on other error.
  */
-static int write_command(uint16_t command,
-			 uint8_t *data, int req_len, int resp_len,
-			 int timeout_us)
+static int write_command(uint16_t command, uint8_t *data, int req_len,
+			 int resp_len, int timeout_us)
 {
 	/* Sequence number. */
 	static uint8_t cur_seq;
@@ -111,11 +110,10 @@ static int write_command(uint16_t command,
 	int tx_length =
 		sizeof(*request_header) + ((req_len > 0) ? (req_len + 1) : 0);
 
-	struct ec_host_response4 *response_header =
-		(void *)&data[tx_length];
+	struct ec_host_response4 *response_header = (void *)&data[tx_length];
 	/* RX length is TX length + response from server. */
-	int rx_length = tx_length +
-		sizeof(*request_header) + ((resp_len > 0) ? (resp_len + 1) : 0);
+	int rx_length = tx_length + sizeof(*request_header) +
+			((resp_len > 0) ? (resp_len + 1) : 0);
 
 	/*
 	 * Make sure there is a gap between each command, so that the server
@@ -124,7 +122,7 @@ static int write_command(uint16_t command,
 	 * TODO(b:65697962): We can be much smarter than this, and record the
 	 * last transaction time instead of just sleeping blindly.
 	 */
-	usleep(10*MSEC);
+	usleep(10 * MSEC);
 
 #ifdef DEBUG_EC_COMM_STATS
 	if ((comm_stats.total % 128) == 0) {
@@ -136,26 +134,27 @@ static int write_command(uint16_t command,
 #endif
 
 	cur_seq = (cur_seq + 1) &
-		(EC_PACKET4_0_SEQ_NUM_MASK >> EC_PACKET4_0_SEQ_NUM_SHIFT);
+		  (EC_PACKET4_0_SEQ_NUM_MASK >> EC_PACKET4_0_SEQ_NUM_SHIFT);
 
 	memset(request_header, 0, sizeof(*request_header));
 	/* fields0: leave seq_dup and is_response as 0. */
 	request_header->fields0 =
 		EC_EC_HOSTCMD_VERSION | /* version */
-		(cur_seq << EC_PACKET4_0_SEQ_NUM_SHIFT); /* seq_num */
+		(cur_seq << EC_PACKET4_0_SEQ_NUM_SHIFT); /* seq_num
+							  */
 	/* fields1: leave command_version as 0. */
 	if (req_len > 0)
 		request_header->fields1 |= EC_PACKET4_1_DATA_CRC_PRESENT_MASK;
 	request_header->command = command;
 	request_header->data_len = req_len;
-	request_header->header_crc =
-		cros_crc8((uint8_t *)request_header, sizeof(*request_header)-1);
+	request_header->header_crc = cros_crc8((uint8_t *)request_header,
+					       sizeof(*request_header) - 1);
 	if (req_len > 0)
 		data[sizeof(*request_header) + req_len] =
 			cros_crc8(&data[sizeof(*request_header)], req_len);
 
-	ret = uart_alt_pad_write_read((void *)data, tx_length,
-				      (void *)data, rx_length, timeout_us);
+	ret = uart_alt_pad_write_read((void *)data, tx_length, (void *)data,
+				      rx_length, timeout_us);
 
 	INCR_COMM_STATS(total);
 
@@ -187,20 +186,19 @@ static int write_command(uint16_t command,
 
 	hascrc = response_header->fields1 & EC_PACKET4_1_DATA_CRC_PRESENT_MASK;
 	response_seq = (response_header->fields0 & EC_PACKET4_0_SEQ_NUM_MASK) >>
-		EC_PACKET4_0_SEQ_NUM_SHIFT;
+		       EC_PACKET4_0_SEQ_NUM_SHIFT;
 
 	/*
 	 * Validate received header.
 	 * Note that we _require_ data crc to be present if there is data to be
 	 * read back, else we would not know how many bytes to read exactly.
 	 */
-	if ((response_header->fields0 & EC_PACKET4_0_STRUCT_VERSION_MASK)
-				!= EC_EC_HOSTCMD_VERSION ||
-			!(response_header->fields0 &
-				EC_PACKET4_0_IS_RESPONSE_MASK) ||
-			response_seq != cur_seq ||
-			(response_header->data_len > 0 && !hascrc) ||
-			response_header->data_len != resp_len) {
+	if ((response_header->fields0 & EC_PACKET4_0_STRUCT_VERSION_MASK) !=
+		    EC_EC_HOSTCMD_VERSION ||
+	    !(response_header->fields0 & EC_PACKET4_0_IS_RESPONSE_MASK) ||
+	    response_seq != cur_seq ||
+	    (response_header->data_len > 0 && !hascrc) ||
+	    response_header->data_len != resp_len) {
 		INCR_COMM_STATS(errinval);
 		return EC_ERROR_INVAL;
 	}
@@ -259,9 +257,9 @@ int ec_ec_client_base_get_dynamic_info(void)
 
 	data.req.param.index = 0;
 
-	ret = write_command(EC_CMD_BATTERY_GET_DYNAMIC,
-			(void *)&data, sizeof(data.req.param),
-			sizeof(data.resp.info), 15 * MSEC);
+	ret = write_command(EC_CMD_BATTERY_GET_DYNAMIC, (void *)&data,
+			    sizeof(data.req.param), sizeof(data.resp.info),
+			    15 * MSEC);
 	ret = handle_error(__func__, ret, data.resp.head.result);
 	if (ret != EC_RES_SUCCESS)
 		return ret;
@@ -277,7 +275,7 @@ int ec_ec_client_base_get_dynamic_info(void)
 #endif
 
 	memcpy(&battery_dynamic[BATT_IDX_BASE], &data.resp.info,
-				sizeof(battery_dynamic[BATT_IDX_BASE]));
+	       sizeof(battery_dynamic[BATT_IDX_BASE]));
 	return EC_RES_SUCCESS;
 }
 
@@ -301,9 +299,9 @@ int ec_ec_client_base_get_static_info(void)
 
 	data.req.param.index = 0;
 
-	ret = write_command(EC_CMD_BATTERY_GET_STATIC,
-			(void *)&data, sizeof(data.req.param),
-			sizeof(data.resp.info), 15 * MSEC);
+	ret = write_command(EC_CMD_BATTERY_GET_STATIC, (void *)&data,
+			    sizeof(data.req.param), sizeof(data.resp.info),
+			    15 * MSEC);
 	ret = handle_error(__func__, ret, data.resp.head.result);
 	if (ret != EC_RES_SUCCESS)
 		return ret;
@@ -330,8 +328,7 @@ int ec_ec_client_base_get_static_info(void)
 	return EC_RES_SUCCESS;
 }
 
-int ec_ec_client_base_charge_control(int max_current,
-				     int otg_voltage,
+int ec_ec_client_base_charge_control(int max_current, int otg_voltage,
 				     int allow_charging)
 {
 	int ret;
@@ -350,8 +347,8 @@ int ec_ec_client_base_charge_control(int max_current,
 	data.req.ctrl.max_current = max_current;
 	data.req.ctrl.otg_voltage = otg_voltage;
 
-	ret = write_command(EC_CMD_CHARGER_CONTROL,
-		(void *)&data, sizeof(data.req.ctrl), 0, 30 * MSEC);
+	ret = write_command(EC_CMD_CHARGER_CONTROL, (void *)&data,
+			    sizeof(data.req.ctrl), 0, 30 * MSEC);
 
 	return handle_error(__func__, ret, data.resp.head.result);
 }
@@ -372,8 +369,8 @@ int ec_ec_client_hibernate(void)
 	data.req.param.cmd = EC_REBOOT_HIBERNATE;
 	data.req.param.flags = 0;
 
-	ret = write_command(EC_CMD_REBOOT_EC,
-		(void *)&data, sizeof(data.req.param), 0, 30 * MSEC);
+	ret = write_command(EC_CMD_REBOOT_EC, (void *)&data,
+			    sizeof(data.req.param), 0, 30 * MSEC);
 
 	return handle_error(__func__, ret, data.resp.head.result);
 }
diff --git a/common/ec_ec_comm_server.c b/common/ec_ec_comm_server.c
index 23b5fee139..6f37004513 100644
--- a/common/ec_ec_comm_server.c
+++ b/common/ec_ec_comm_server.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -21,8 +21,8 @@
 #include "task.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* Print extra debugging information */
 #undef EXTRA_DEBUG
@@ -37,11 +37,10 @@ static int charging_allowed;
 #define LARGEST_PARAMS_SIZE 8
 
 BUILD_ASSERT(LARGEST_PARAMS_SIZE >=
-	sizeof(struct ec_params_battery_static_info));
+	     sizeof(struct ec_params_battery_static_info));
 BUILD_ASSERT(LARGEST_PARAMS_SIZE >=
-	sizeof(struct ec_params_battery_dynamic_info));
-BUILD_ASSERT(LARGEST_PARAMS_SIZE >=
-	sizeof(struct ec_params_charger_control));
+	     sizeof(struct ec_params_battery_dynamic_info));
+BUILD_ASSERT(LARGEST_PARAMS_SIZE >= sizeof(struct ec_params_charger_control));
 
 #define COMMAND_BUFFER_PARAMS_SIZE (LARGEST_PARAMS_SIZE + 1)
 
@@ -51,7 +50,6 @@ BUILD_ASSERT(LARGEST_PARAMS_SIZE >=
  */
 #define COMMAND_TIMEOUT_US (5 * MSEC)
 
-
 void ec_ec_comm_server_written(struct consumer const *consumer, size_t count)
 {
 	task_wake(TASK_ID_ECCOMM);
@@ -67,7 +65,7 @@ static void discard_queue(void)
 {
 	do {
 		queue_advance_head(&ec_ec_comm_server_input,
-				queue_count(&ec_ec_comm_server_input));
+				   queue_count(&ec_ec_comm_server_input));
 		usleep(1 * MSEC);
 	} while (queue_count(&ec_ec_comm_server_input) > 0);
 }
@@ -78,19 +76,17 @@ static void write_response(uint16_t res, int seq, const void *data, int len)
 	struct ec_host_response4 header;
 	uint8_t crc;
 
-	header.fields0 =
-		4 | /* version */
-		EC_PACKET4_0_IS_RESPONSE_MASK | /* is_response */
-		(seq << EC_PACKET4_0_SEQ_NUM_SHIFT); /* seq_num */
+	header.fields0 = 4 | /* version */
+			 EC_PACKET4_0_IS_RESPONSE_MASK | /* is_response */
+			 (seq << EC_PACKET4_0_SEQ_NUM_SHIFT); /* seq_num */
 	/* Set data_crc_present if there is data */
 	header.fields1 = (len > 0) ? EC_PACKET4_1_DATA_CRC_PRESENT_MASK : 0;
 	header.result = res;
 	header.data_len = len;
 	header.reserved = 0;
-	header.header_crc =
-		cros_crc8((uint8_t *)&header, sizeof(header)-1);
-	QUEUE_ADD_UNITS(&ec_ec_comm_server_output,
-			(uint8_t *)&header, sizeof(header));
+	header.header_crc = cros_crc8((uint8_t *)&header, sizeof(header) - 1);
+	QUEUE_ADD_UNITS(&ec_ec_comm_server_output, (uint8_t *)&header,
+			sizeof(header));
 
 	if (len > 0) {
 		QUEUE_ADD_UNITS(&ec_ec_comm_server_output, data, len);
@@ -123,9 +119,8 @@ static int read_data(void *buffer, size_t len, uint32_t start)
 	return EC_SUCCESS;
 }
 
-static void handle_cmd_reboot_ec(
-	const struct ec_params_reboot_ec *params,
-	int data_len, int seq)
+static void handle_cmd_reboot_ec(const struct ec_params_reboot_ec *params,
+				 int data_len, int seq)
 {
 	int ret = EC_RES_SUCCESS;
 
@@ -150,9 +145,9 @@ out:
 }
 
 #ifdef CONFIG_EC_EC_COMM_BATTERY
-static void handle_cmd_charger_control(
-	const struct ec_params_charger_control *params,
-	int data_len, int seq)
+static void
+handle_cmd_charger_control(const struct ec_params_charger_control *params,
+			   int data_len, int seq)
 {
 	int ret = EC_RES_SUCCESS;
 	int prev_charging_allowed = charging_allowed;
@@ -169,7 +164,7 @@ static void handle_cmd_charger_control(
 		charging_allowed = params->allow_charging;
 	} else {
 		if (-params->max_current > MAX_OTG_CURRENT_MA ||
-				params->otg_voltage > MAX_OTG_VOLTAGE_MV) {
+		    params->otg_voltage > MAX_OTG_VOLTAGE_MV) {
 			ret = EC_RES_INVALID_PARAM;
 			goto out;
 		}
@@ -233,8 +228,8 @@ void ec_ec_comm_server_task(void *u)
 
 #ifdef EXTRA_DEBUG
 		CPRINTS("%s f0=%02x f1=%02x cmd=%02x, length=%d", __func__,
-			header.fields0, header.fields1,
-			header.command, header.data_len);
+			header.fields0, header.fields1, header.command,
+			header.data_len);
 #endif
 
 		/* Ignore response (we wrote that ourselves) */
@@ -266,7 +261,7 @@ void ec_ec_comm_server_task(void *u)
 		}
 
 		seq = (header.fields0 & EC_PACKET4_0_SEQ_NUM_MASK) >>
-			EC_PACKET4_0_SEQ_NUM_SHIFT;
+		      EC_PACKET4_0_SEQ_NUM_SHIFT;
 
 		cmdver = header.fields1 & EC_PACKET4_1_COMMAND_VERSION_MASK;
 
@@ -277,7 +272,7 @@ void ec_ec_comm_server_task(void *u)
 		}
 
 		/* Check data CRC */
-		if (hascrc && params[len-1] != cros_crc8(params, len-1)) {
+		if (hascrc && params[len - 1] != cros_crc8(params, len - 1)) {
 			CPRINTS("%s data crc error", __func__);
 			write_response(EC_RES_INVALID_CHECKSUM, seq, NULL, 0);
 			goto discard;
@@ -295,31 +290,30 @@ void ec_ec_comm_server_task(void *u)
 		case EC_CMD_BATTERY_GET_STATIC:
 			/* Note that we ignore the battery index parameter. */
 			write_response(EC_RES_SUCCESS, seq,
-				&battery_static[BATT_IDX_MAIN],
-				sizeof(battery_static[BATT_IDX_MAIN]));
+				       &battery_static[BATT_IDX_MAIN],
+				       sizeof(battery_static[BATT_IDX_MAIN]));
 			break;
 		case EC_CMD_BATTERY_GET_DYNAMIC:
 			/* Note that we ignore the battery index parameter. */
 			write_response(EC_RES_SUCCESS, seq,
-				&battery_dynamic[BATT_IDX_MAIN],
-				sizeof(battery_dynamic[BATT_IDX_MAIN]));
+				       &battery_dynamic[BATT_IDX_MAIN],
+				       sizeof(battery_dynamic[BATT_IDX_MAIN]));
 			break;
 		case EC_CMD_CHARGER_CONTROL:
 			handle_cmd_charger_control((void *)params,
-						header.data_len, seq);
+						   header.data_len, seq);
 			break;
 #endif
 		case EC_CMD_REBOOT_EC:
-			handle_cmd_reboot_ec((void *)params,
-						header.data_len, seq);
+			handle_cmd_reboot_ec((void *)params, header.data_len,
+					     seq);
 			break;
 		default:
-			write_response(EC_RES_INVALID_COMMAND, seq,
-				NULL, 0);
+			write_response(EC_RES_INVALID_COMMAND, seq, NULL, 0);
 		}
 
 		continue;
-discard:
+	discard:
 		/*
 		 * Some error occurred: discard all data in the queue.
 		 */
diff --git a/common/ec_features.c b/common/ec_features.c
index 2147c1b48a..a45204b7a1 100644
--- a/common/ec_features.c
+++ b/common/ec_features.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,97 +15,97 @@ uint32_t get_feature_flags0(void)
 {
 	uint32_t result = 0
 #ifdef CONFIG_FW_LIMITED_IMAGE
-		| EC_FEATURE_MASK_0(EC_FEATURE_LIMITED)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_LIMITED)
 #endif
 #ifdef CONFIG_FLASH_CROS
-		| EC_FEATURE_MASK_0(EC_FEATURE_FLASH)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_FLASH)
 #endif
 #ifdef CONFIG_FANS
-		| EC_FEATURE_MASK_0(EC_FEATURE_PWM_FAN)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_PWM_FAN)
 #endif
 #ifdef CONFIG_KEYBOARD_BACKLIGHT
-		| EC_FEATURE_MASK_0(EC_FEATURE_PWM_KEYB)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_PWM_KEYB)
 #endif
 #ifdef HAS_TASK_LIGHTBAR
-		| EC_FEATURE_MASK_0(EC_FEATURE_LIGHTBAR)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_LIGHTBAR)
 #endif
 #ifdef CONFIG_LED_COMMON
-		| EC_FEATURE_MASK_0(EC_FEATURE_LED)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_LED)
 #endif
 #ifdef HAS_TASK_MOTIONSENSE
-		| EC_FEATURE_MASK_0(EC_FEATURE_MOTION_SENSE)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_MOTION_SENSE)
 #endif
 #ifdef HAS_TASK_KEYSCAN
-		| EC_FEATURE_MASK_0(EC_FEATURE_KEYB)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_KEYB)
 #endif
 #ifdef CONFIG_PSTORE
-		| EC_FEATURE_MASK_0(EC_FEATURE_PSTORE)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_PSTORE)
 #endif
 #ifdef CONFIG_HOSTCMD_X86
-		| EC_FEATURE_MASK_0(EC_FEATURE_PORT80)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_PORT80)
 #endif
 #ifdef CONFIG_TEMP_SENSOR
-		| EC_FEATURE_MASK_0(EC_FEATURE_THERMAL)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_THERMAL)
 #endif
 #if (defined CONFIG_BACKLIGHT_LID) || (defined CONFIG_BACKLIGHT_REQ_GPIO)
-		| EC_FEATURE_MASK_0(EC_FEATURE_BKLIGHT_SWITCH)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_BKLIGHT_SWITCH)
 #endif
 #ifdef CONFIG_WIRELESS
-		| EC_FEATURE_MASK_0(EC_FEATURE_WIFI_SWITCH)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_WIFI_SWITCH)
 #endif
 #ifdef CONFIG_HOSTCMD_EVENTS
-		| EC_FEATURE_MASK_0(EC_FEATURE_HOST_EVENTS)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_HOST_EVENTS)
 #endif
 #ifdef CONFIG_COMMON_GPIO
-		| EC_FEATURE_MASK_0(EC_FEATURE_GPIO)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_GPIO)
 #endif
 #ifdef CONFIG_I2C_CONTROLLER
-		| EC_FEATURE_MASK_0(EC_FEATURE_I2C)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_I2C)
 #endif
 #ifdef CONFIG_CHARGER
-		| EC_FEATURE_MASK_0(EC_FEATURE_CHARGER)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_CHARGER)
 #endif
 #if (defined CONFIG_BATTERY)
-		| EC_FEATURE_MASK_0(EC_FEATURE_BATTERY)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_BATTERY)
 #endif
 #ifdef CONFIG_BATTERY_SMART
-		| EC_FEATURE_MASK_0(EC_FEATURE_SMART_BATTERY)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_SMART_BATTERY)
 #endif
 #ifdef CONFIG_AP_HANG_DETECT
-		| EC_FEATURE_MASK_0(EC_FEATURE_HANG_DETECT)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_HANG_DETECT)
 #endif
 #if 0
 		| EC_FEATURE_MASK_0(EC_FEATURE_PMU) /* Obsolete */
 #endif
 #ifdef CONFIG_HOSTCMD_PD
-		| EC_FEATURE_MASK_0(EC_FEATURE_SUB_MCU)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_SUB_MCU)
 #endif
 #ifdef CONFIG_CHARGE_MANAGER
-		| EC_FEATURE_MASK_0(EC_FEATURE_USB_PD)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_USB_PD)
 #endif
 #ifdef CONFIG_ACCEL_FIFO
-		| EC_FEATURE_MASK_0(EC_FEATURE_MOTION_SENSE_FIFO)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_MOTION_SENSE_FIFO)
 #endif
 #ifdef CONFIG_VSTORE
-		| EC_FEATURE_MASK_0(EC_FEATURE_VSTORE)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_VSTORE)
 #endif
 #ifdef CONFIG_USB_MUX_VIRTUAL
-		| EC_FEATURE_MASK_0(EC_FEATURE_USBC_SS_MUX_VIRTUAL)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_USBC_SS_MUX_VIRTUAL)
 #endif
 #ifdef CONFIG_HOSTCMD_RTC
-		| EC_FEATURE_MASK_0(EC_FEATURE_RTC)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_RTC)
 #endif
 #ifdef CONFIG_SPI_FP_PORT
-		| EC_FEATURE_MASK_0(EC_FEATURE_FINGERPRINT)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_FINGERPRINT)
 #endif
 #ifdef HAS_TASK_CENTROIDING
-		| EC_FEATURE_MASK_0(EC_FEATURE_TOUCHPAD)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_TOUCHPAD)
 #endif
 #if defined(HAS_TASK_RWSIG) || defined(HAS_TASK_RWSIG_RO)
-		| EC_FEATURE_MASK_0(EC_FEATURE_RWSIG)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_RWSIG)
 #endif
 #ifdef CONFIG_DEVICE_EVENT
-		| EC_FEATURE_MASK_0(EC_FEATURE_DEVICE_EVENT)
+			  | EC_FEATURE_MASK_0(EC_FEATURE_DEVICE_EVENT)
 #endif
 		;
 	return board_override_feature_flags0(result);
@@ -113,7 +113,8 @@ uint32_t get_feature_flags0(void)
 
 uint32_t get_feature_flags1(void)
 {
-	uint32_t result = EC_FEATURE_MASK_1(EC_FEATURE_UNIFIED_WAKE_MASKS)
+	uint32_t result =
+		EC_FEATURE_MASK_1(EC_FEATURE_UNIFIED_WAKE_MASKS)
 #ifdef CONFIG_HOST_EVENT64
 		| EC_FEATURE_MASK_1(EC_FEATURE_HOST_EVENT64)
 #endif
@@ -150,6 +151,9 @@ uint32_t get_feature_flags1(void)
 #ifdef CONFIG_POWER_S4_RESIDENCY
 		| EC_FEATURE_MASK_1(EC_FEATURE_S4_RESIDENCY)
 #endif
+#ifdef CONFIG_USB_MUX_AP_CONTROL
+		| EC_FEATURE_MASK_1(EC_FEATURE_TYPEC_AP_MUX_SET)
+#endif
 		;
 	return board_override_feature_flags1(result);
 }
@@ -164,7 +168,7 @@ __overridable uint32_t board_override_feature_flags1(uint32_t flags1)
 	return flags1;
 }
 
-static int cc_feat(int argc, char **argv)
+static int cc_feat(int argc, const char **argv)
 {
 	ccprintf(" 0-31: 0x%08x\n", get_feature_flags0());
 	ccprintf("32-63: 0x%08x\n", get_feature_flags1());
diff --git a/common/espi.c b/common/espi.c
index 0a747d3bda..dfb1f90749 100644
--- a/common/espi.c
+++ b/common/espi.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,7 +12,6 @@
 #include "timer.h"
 #include "util.h"
 
-
 const char *espi_vw_names[] = {
 	"VW_SLP_S3_L",
 	"VW_SLP_S4_L",
@@ -41,7 +40,6 @@ const char *espi_vw_names[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(espi_vw_names) == VW_SIGNAL_COUNT);
 
-
 const char *espi_vw_get_wire_name(enum espi_vw_signal signal)
 {
 	if (espi_signal_is_vw(signal))
@@ -50,7 +48,6 @@ const char *espi_vw_get_wire_name(enum espi_vw_signal signal)
 	return NULL;
 }
 
-
 int espi_signal_is_vw(int signal)
 {
 	return ((signal >= VW_SIGNAL_START) && (signal < VW_SIGNAL_END));
diff --git a/common/event_log.c b/common/event_log.c
index dc2c4ec2d7..f748b3d9a7 100644
--- a/common/event_log.c
+++ b/common/event_log.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,8 +13,8 @@
 
 /* Event log FIFO */
 #define UNIT_SIZE sizeof(struct event_log_entry)
-#define UNIT_COUNT (CONFIG_EVENT_LOG_SIZE/UNIT_SIZE)
-#define UNIT_COUNT_MASK		(UNIT_COUNT - 1)
+#define UNIT_COUNT (CONFIG_EVENT_LOG_SIZE / UNIT_SIZE)
+#define UNIT_COUNT_MASK (UNIT_COUNT - 1)
 static struct event_log_entry log_events[UNIT_COUNT];
 BUILD_ASSERT(POWER_OF_TWO(UNIT_COUNT));
 
@@ -42,10 +42,10 @@ static size_t log_tail;
 static size_t log_tail_next;
 
 /* Size of one FIFO entry */
-#define ENTRY_SIZE(payload_sz) (1+DIV_ROUND_UP((payload_sz), UNIT_SIZE))
+#define ENTRY_SIZE(payload_sz) (1 + DIV_ROUND_UP((payload_sz), UNIT_SIZE))
 
-void log_add_event(uint8_t type, uint8_t size, uint16_t data,
-			  void *payload, uint32_t timestamp)
+void log_add_event(uint8_t type, uint8_t size, uint16_t data, void *payload,
+		   uint32_t timestamp)
 {
 	struct event_log_entry *r;
 	size_t payload_size = EVENT_LOG_SIZE(size);
@@ -78,13 +78,13 @@ void log_add_event(uint8_t type, uint8_t size, uint16_t data,
 	r->size = size;
 	r->data = data;
 	/* copy the payload into the FIFO */
-	first = MIN(total_size - 1, (UNIT_COUNT -
-		    (current_tail & UNIT_COUNT_MASK)) - 1);
+	first = MIN(total_size - 1,
+		    (UNIT_COUNT - (current_tail & UNIT_COUNT_MASK)) - 1);
 	if (first)
 		memcpy(r->payload, payload, first * UNIT_SIZE);
 	if (first < total_size - 1)
 		memcpy(log_events, ((uint8_t *)payload) + first * UNIT_SIZE,
-			(total_size - first) * UNIT_SIZE);
+		       (total_size - first) * UNIT_SIZE);
 	/* mark the entry available in the queue if nobody is behind us */
 	if (current_tail == log_tail)
 		log_tail = log_tail_next;
@@ -112,7 +112,7 @@ retry:
 	first = MIN(total_size, UNIT_COUNT - (current_head & UNIT_COUNT_MASK));
 	memcpy(r, entry, first * UNIT_SIZE);
 	if (first < total_size)
-		memcpy(r + first, log_events, (total_size-first) * UNIT_SIZE);
+		memcpy(r + first, log_events, (total_size - first) * UNIT_SIZE);
 
 	/* --- critical section : remove the entry from the queue --- */
 	lock_key = irq_lock();
@@ -134,10 +134,10 @@ retry:
 /*
  * Display TPM event logs.
  */
-static int command_dlog(int argc, char **argv)
+static int command_dlog(int argc, const char **argv)
 {
 	size_t log_cur;
-	const uint8_t * const log_events_end =
+	const uint8_t *const log_events_end =
 		(uint8_t *)&log_events[UNIT_COUNT];
 
 	if (argc > 1) {
@@ -164,7 +164,7 @@ static int command_dlog(int argc, char **argv)
 		log_cur += ENTRY_SIZE(payload_bytes);
 
 		ccprintf("%10d   %4d  0x%04X   %4d   ", r->timestamp, r->type,
-			r->data, payload_bytes);
+			 r->data, payload_bytes);
 
 		/* display payload if exists */
 		payload = r->payload;
@@ -179,8 +179,6 @@ static int command_dlog(int argc, char **argv)
 	}
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(dlog,
-			command_dlog,
-			"[clear]",
+DECLARE_CONSOLE_COMMAND(dlog, command_dlog, "[clear]",
 			"Display/clear TPM event logs");
 #endif
diff --git a/common/extpower_common.c b/common/extpower_common.c
index 9021b77626..9f0947a529 100644
--- a/common/extpower_common.c
+++ b/common/extpower_common.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/common/extpower_gpio.c b/common/extpower_gpio.c
index 4cdcb834f8..8b41ec2075 100644
--- a/common/extpower_gpio.c
+++ b/common/extpower_gpio.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -31,7 +31,6 @@ static void extpower_deferred(void)
 
 	debounced_extpower_presence = extpower_presence;
 	extpower_handle_update(extpower_presence);
-
 }
 DECLARE_DEFERRED(extpower_deferred);
 
@@ -39,7 +38,7 @@ void extpower_interrupt(enum gpio_signal signal)
 {
 	/* Trigger deferred notification of external power change */
 	hook_call_deferred(&extpower_deferred_data,
-			CONFIG_EXTPOWER_DEBOUNCE_MS * MSEC);
+			   CONFIG_EXTPOWER_DEBOUNCE_MS * MSEC);
 }
 
 static void extpower_init(void)
diff --git a/common/fan.c b/common/fan.c
index 636bec04f9..ddc15a4288 100644
--- a/common/fan.c
+++ b/common/fan.c
@@ -1,11 +1,11 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Basic Chrome OS fan control */
 
-#include "assert.h"
+#include "builtin/assert.h"
 #include "chipset.h"
 #include "common.h"
 #include "console.h"
@@ -56,7 +56,7 @@ void fan_set_count(int count)
  * Convert the percentage to a target RPM. We can't simply scale all
  * the way down to zero because most fans won't turn that slowly, so
  * we'll map [1,100] => [FAN_MIN,FAN_MAX], and [0] => "off".
-*/
+ */
 int fan_percent_to_rpm(int fan, int pct)
 {
 	int rpm, max, min;
@@ -71,7 +71,7 @@ int fan_percent_to_rpm(int fan, int pct)
 
 	return rpm;
 }
-#endif	/* CONFIG_FAN_RPM_CUSTOM */
+#endif /* CONFIG_FAN_RPM_CUSTOM */
 
 /* The thermal task will only call this function with pct in [0,100]. */
 test_mockable void fan_set_percent_needed(int fan, int pct)
@@ -94,8 +94,7 @@ test_mockable void fan_set_percent_needed(int fan, int pct)
 	/* If we want to turn and the fans are currently significantly below
 	 * the minimum turning speed, we should turn at least as fast as the
 	 * necessary start speed instead. */
-	if (new_rpm &&
-	    actual_rpm < fans[fan].rpm->rpm_min * 9 / 10 &&
+	if (new_rpm && actual_rpm < fans[fan].rpm->rpm_min * 9 / 10 &&
 	    new_rpm < fans[fan].rpm->rpm_start)
 		new_rpm = fans[fan].rpm->rpm_start;
 
@@ -137,7 +136,7 @@ static void set_duty_cycle(int fan, int percent)
 /*****************************************************************************/
 /* Console commands */
 
-static int cc_fanauto(int argc, char **argv)
+static int cc_fanauto(int argc, const char **argv)
 {
 	char *e;
 	int fan = 0;
@@ -157,8 +156,7 @@ static int cc_fanauto(int argc, char **argv)
 	set_thermal_control_enabled(fan, 1);
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(fanauto, cc_fanauto,
-			"{fan}",
+DECLARE_CONSOLE_COMMAND(fanauto, cc_fanauto, "{fan}",
 			"Enable thermal fan control");
 
 /* Return 0 for off, 1 for on, -1 for unknown */
@@ -176,28 +174,27 @@ static int is_powered(int fan)
 	return is_pgood;
 }
 
-static int cc_faninfo(int argc, char **argv)
+static int cc_faninfo(int argc, const char **argv)
 {
-	static const char * const human_status[] = {
-		"not spinning", "changing", "locked", "frustrated"
-	};
+	static const char *const human_status[] = { "not spinning", "changing",
+						    "locked", "frustrated" };
 	int tmp, is_pgood;
 	int fan;
 	char leader[20] = "";
 	for (fan = 0; fan < fan_count; fan++) {
 		if (fan_count > 1)
-			snprintf(leader, sizeof(leader), "Fan %d ", fan);
+			if (snprintf(leader, sizeof(leader), "Fan %d ", fan) <
+			    0)
+				leader[0] = '\0';
 		if (fan)
 			ccprintf("\n");
 		ccprintf("%sActual: %4d rpm\n", leader,
 			 fan_get_rpm_actual(FAN_CH(fan)));
 		ccprintf("%sTarget: %4d rpm\n", leader,
 			 fan_get_rpm_target(FAN_CH(fan)));
-		ccprintf("%sDuty:   %d%%\n", leader,
-			 fan_get_duty(FAN_CH(fan)));
+		ccprintf("%sDuty:   %d%%\n", leader, fan_get_duty(FAN_CH(fan)));
 		tmp = fan_get_status(FAN_CH(fan));
-		ccprintf("%sStatus: %d (%s)\n", leader,
-			 tmp, human_status[tmp]);
+		ccprintf("%sStatus: %d (%s)\n", leader, tmp, human_status[tmp]);
 		ccprintf("%sMode:   %s\n", leader,
 			 fan_get_rpm_mode(FAN_CH(fan)) ? "rpm" : "duty");
 		ccprintf("%sAuto:   %s\n", leader,
@@ -212,11 +209,9 @@ static int cc_faninfo(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(faninfo, cc_faninfo,
-			NULL,
-			"Print fan info");
+DECLARE_CONSOLE_COMMAND(faninfo, cc_faninfo, NULL, "Print fan info");
 
-static int cc_fanset(int argc, char **argv)
+static int cc_fanset(int argc, const char **argv)
 {
 	const char *rpm_str;
 	int rpm;
@@ -247,7 +242,7 @@ static int cc_fanset(int argc, char **argv)
 	}
 
 	rpm = strtoi(rpm_str, &e, 0);
-	if (*e == '%') {		/* Wait, that's a percentage */
+	if (*e == '%') { /* Wait, that's a percentage */
 		ccprintf("Fan rpm given as %d%%\n", rpm);
 		if (rpm < 0)
 			rpm = 0;
@@ -273,11 +268,10 @@ static int cc_fanset(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(fanset, cc_fanset,
-			"[fan] (rpm | pct%)",
+DECLARE_CONSOLE_COMMAND(fanset, cc_fanset, "[fan] (rpm | pct%)",
 			"Set fan speed");
 
-static int cc_fanduty(int argc, char **argv)
+static int cc_fanduty(int argc, const char **argv)
 {
 	const char *percent_str;
 	int percent = 0;
@@ -316,8 +310,7 @@ static int cc_fanduty(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(fanduty, cc_fanduty,
-			"[fan] percent",
+DECLARE_CONSOLE_COMMAND(fanduty, cc_fanduty, "[fan] percent",
 			"Set fan duty cycle");
 
 /*****************************************************************************/
@@ -326,7 +319,7 @@ DECLARE_CONSOLE_COMMAND(fanduty, cc_fanduty,
 /* 0-100% if in duty mode. -1 if not */
 int dptf_get_fan_duty_target(void)
 {
-	int fan = 0;				/* TODO(crosbug.com/p/23803) */
+	int fan = 0; /* TODO(crosbug.com/p/23803) */
 
 	if (fan_count == 0)
 		return -1;
@@ -370,8 +363,7 @@ hc_pwm_get_fan_target_rpm(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_FAN_TARGET_RPM,
-		     hc_pwm_get_fan_target_rpm,
+DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_FAN_TARGET_RPM, hc_pwm_get_fan_target_rpm,
 		     EC_VER_MASK(0));
 
 static enum ec_status
@@ -399,7 +391,7 @@ hc_pwm_set_fan_target_rpm(struct host_cmd_handler_args *args)
 		return EC_RES_ERROR;
 
 	/* enable the fan if rpm is non-zero */
-	set_enabled(fan, (p_v1->rpm > 0) ? 1 :0);
+	set_enabled(fan, (p_v1->rpm > 0) ? 1 : 0);
 
 	set_thermal_control_enabled(fan, 0);
 	fan_set_rpm_mode(FAN_CH(fan), 1);
@@ -407,8 +399,7 @@ hc_pwm_set_fan_target_rpm(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_FAN_TARGET_RPM,
-		     hc_pwm_set_fan_target_rpm,
+DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_FAN_TARGET_RPM, hc_pwm_set_fan_target_rpm,
 		     EC_VER_MASK(0) | EC_VER_MASK(1));
 
 static enum ec_status hc_pwm_set_fan_duty(struct host_cmd_handler_args *args)
@@ -432,8 +423,7 @@ static enum ec_status hc_pwm_set_fan_duty(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_FAN_DUTY,
-		     hc_pwm_set_fan_duty,
+DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_FAN_DUTY, hc_pwm_set_fan_duty,
 		     EC_VER_MASK(0) | EC_VER_MASK(1));
 
 static enum ec_status
@@ -457,10 +447,8 @@ hc_thermal_auto_fan_ctrl(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_THERMAL_AUTO_FAN_CTRL,
-		     hc_thermal_auto_fan_ctrl,
-		     EC_VER_MASK(0)|EC_VER_MASK(1));
-
+DECLARE_HOST_COMMAND(EC_CMD_THERMAL_AUTO_FAN_CTRL, hc_thermal_auto_fan_ctrl,
+		     EC_VER_MASK(0) | EC_VER_MASK(1));
 
 /*****************************************************************************/
 /* Hooks */
@@ -471,18 +459,18 @@ DECLARE_HOST_COMMAND(EC_CMD_THERMAL_AUTO_FAN_CTRL,
  */
 BUILD_ASSERT(CONFIG_FANS <= EC_FAN_SPEED_ENTRIES);
 
-#define PWMFAN_SYSJUMP_TAG 0x5046  /* "PF" */
+#define PWMFAN_SYSJUMP_TAG 0x5046 /* "PF" */
 #define PWM_HOOK_VERSION 1
 /* Saved PWM state across sysjumps */
 struct pwm_fan_state {
 	/* TODO(crosbug.com/p/23530): Still treating all fans as one. */
 	uint16_t rpm;
-	uint8_t flag;	/* FAN_STATE_FLAG_* */
+	uint8_t flag; /* FAN_STATE_FLAG_* */
 };
 
 /* For struct pwm_fan_state.flag */
-#define FAN_STATE_FLAG_ENABLED	BIT(0)
-#define FAN_STATE_FLAG_THERMAL	BIT(1)
+#define FAN_STATE_FLAG_ENABLED BIT(0)
+#define FAN_STATE_FLAG_THERMAL BIT(1)
 
 static void pwm_fan_init(void)
 {
@@ -500,8 +488,8 @@ static void pwm_fan_init(void)
 		fan_channel_setup(FAN_CH(fan), fans[fan].conf->flags);
 
 	/* Restore previous state. */
-	prev = (const struct pwm_fan_state *)
-		system_get_jump_tag(PWMFAN_SYSJUMP_TAG, &version, &size);
+	prev = (const struct pwm_fan_state *)system_get_jump_tag(
+		PWMFAN_SYSJUMP_TAG, &version, &size);
 	if (prev && version == PWM_HOOK_VERSION && size == sizeof(*prev)) {
 		memcpy(&state, prev, sizeof(state));
 	} else {
@@ -513,7 +501,7 @@ static void pwm_fan_init(void)
 				state.flag & FAN_STATE_FLAG_ENABLED);
 		fan_set_rpm_target(FAN_CH(fan), state.rpm);
 		set_thermal_control_enabled(
-				fan, state.flag & FAN_STATE_FLAG_THERMAL);
+			fan, state.flag & FAN_STATE_FLAG_THERMAL);
 	}
 
 	/* Initialize memory-mapped data */
@@ -553,7 +541,7 @@ DECLARE_HOOK(HOOK_SECOND, pwm_fan_second, HOOK_PRIO_DEFAULT);
 
 static void pwm_fan_preserve_state(void)
 {
-	struct pwm_fan_state state = {0};
+	struct pwm_fan_state state = { 0 };
 	int fan = 0;
 
 	if (fan_count == 0)
@@ -566,8 +554,8 @@ static void pwm_fan_preserve_state(void)
 		state.flag |= FAN_STATE_FLAG_THERMAL;
 	state.rpm = fan_get_rpm_target(FAN_CH(fan));
 
-	system_add_jump_tag(PWMFAN_SYSJUMP_TAG, PWM_HOOK_VERSION,
-			    sizeof(state), &state);
+	system_add_jump_tag(PWMFAN_SYSJUMP_TAG, PWM_HOOK_VERSION, sizeof(state),
+			    &state);
 }
 DECLARE_HOOK(HOOK_SYSJUMP, pwm_fan_preserve_state, HOOK_PRIO_DEFAULT);
 
@@ -578,9 +566,11 @@ static void pwm_fan_control(int enable)
 	/* TODO(crosbug.com/p/23530): Still treating all fans as one. */
 	for (fan = 0; fan < fan_count; fan++) {
 		set_thermal_control_enabled(fan, enable);
-		fan_set_rpm_target(FAN_CH(fan), enable ?
-			fan_percent_to_rpm(FAN_CH(fan), CONFIG_FAN_INIT_SPEED) :
-			0);
+		fan_set_rpm_target(
+			FAN_CH(fan),
+			enable ? fan_percent_to_rpm(FAN_CH(fan),
+						    CONFIG_FAN_INIT_SPEED) :
+				 0);
 		set_enabled(fan, enable);
 	}
 }
diff --git a/common/firmware_image.S b/common/firmware_image.S
index 193719608f..cc9034b89d 100644
--- a/common/firmware_image.S
+++ b/common/firmware_image.S
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/common/firmware_image.lds.S b/common/firmware_image.lds.S
index 04249367b8..5bcd6efb5f 100644
--- a/common/firmware_image.lds.S
+++ b/common/firmware_image.lds.S
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/common/flash.c b/common/flash.c
index 055064d029..0a027fd312 100644
--- a/common/flash.c
+++ b/common/flash.c
@@ -1,10 +1,11 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Flash memory module for Chrome EC - common functions */
 
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
 #include "cros_board_info.h"
@@ -42,14 +43,14 @@
 /* Persistent protection state - emulates a SPI status register for flashrom */
 /* NOTE: It's not expected that RO and RW will support
  * differing PSTATE versions. */
-#define PERSIST_STATE_VERSION 3  /* Expected persist_state.version */
+#define PERSIST_STATE_VERSION 3 /* Expected persist_state.version */
 
 /* Flags for persist_state.flags */
 /* Protect persist state and RO firmware at boot */
 #define PERSIST_FLAG_PROTECT_RO 0x02
-#define PSTATE_VALID_FLAGS      BIT(0)
-#define PSTATE_VALID_SERIALNO   BIT(1)
-#define PSTATE_VALID_MAC_ADDR   BIT(2)
+#define PSTATE_VALID_FLAGS BIT(0)
+#define PSTATE_VALID_SERIALNO BIT(1)
+#define PSTATE_VALID_MAC_ADDR BIT(2)
 
 /*
  * Error correction code operates on blocks equal to CONFIG_FLASH_WRITE_SIZE
@@ -59,10 +60,10 @@
  * size of the structure to ensure that it is also a multiple of the alignment.
  */
 struct persist_state {
-	uint8_t version;            /* Version of this struct */
-	uint8_t flags;              /* Lock flags (PERSIST_FLAG_*) */
-	uint8_t valid_fields;       /* Flags for valid data. */
-	uint8_t reserved;           /* Reserved; set 0 */
+	uint8_t version; /* Version of this struct */
+	uint8_t flags; /* Lock flags (PERSIST_FLAG_*) */
+	uint8_t valid_fields; /* Flags for valid data. */
+	uint8_t reserved; /* Reserved; set 0 */
 #ifdef CONFIG_SERIALNO_LEN
 	uint8_t serialno[CONFIG_SERIALNO_LEN]; /* Serial number. */
 #endif /* CONFIG_SERIALNO_LEN */
@@ -91,11 +92,11 @@ BUILD_ASSERT(sizeof(struct persist_state) <= CONFIG_FW_PSTATE_SIZE);
  * lock the flash at boot.
  */
 #if (CONFIG_FLASH_ERASED_VALUE32 == -1U)
-#define PSTATE_MAGIC_UNLOCKED 0x4f4e5057  /* "WPNO" */
-#define PSTATE_MAGIC_LOCKED   0x00000000  /* ""     */
+#define PSTATE_MAGIC_UNLOCKED 0x4f4e5057 /* "WPNO" */
+#define PSTATE_MAGIC_LOCKED 0x00000000 /* ""     */
 #elif (CONFIG_FLASH_ERASED_VALUE32 == 0)
-#define PSTATE_MAGIC_UNLOCKED 0x4f4e5057  /* "WPNO" */
-#define PSTATE_MAGIC_LOCKED   0x5f5f5057  /* "WP__" */
+#define PSTATE_MAGIC_UNLOCKED 0x4f4e5057 /* "WPNO" */
+#define PSTATE_MAGIC_LOCKED 0x5f5f5057 /* "WP__" */
 #else
 /* What kind of wacky flash doesn't erase all bits to 1 or 0? */
 #error "PSTATE needs magic values for this flash architecture."
@@ -171,8 +172,8 @@ int crec_flash_bank_index(int offset)
 		return bank_offset;
 
 	for (i = 0; i < ARRAY_SIZE(flash_bank_array); i++) {
-		int all_sector_size = flash_bank_array[i].count <<
-			flash_bank_array[i].size_exp;
+		int all_sector_size = flash_bank_array[i].count
+				      << flash_bank_array[i].size_exp;
 		if (offset >= all_sector_size) {
 			offset -= all_sector_size;
 			bank_offset += flash_bank_array[i].count;
@@ -217,16 +218,15 @@ int crec_flash_bank_start_offset(int bank)
 	return offset;
 }
 
-#endif  /* CONFIG_FLASH_MULTIPLE_REGION */
+#endif /* CONFIG_FLASH_MULTIPLE_REGION */
 
 static int flash_range_ok(int offset, int size_req, int align)
 {
-	if (offset < 0 || size_req < 0 ||
-	    offset > CONFIG_FLASH_SIZE_BYTES ||
+	if (offset < 0 || size_req < 0 || offset > CONFIG_FLASH_SIZE_BYTES ||
 	    size_req > CONFIG_FLASH_SIZE_BYTES ||
 	    offset + size_req > CONFIG_FLASH_SIZE_BYTES ||
 	    (offset | size_req) & (align - 1))
-		return 0;  /* Invalid range */
+		return 0; /* Invalid range */
 
 	return 1;
 }
@@ -251,7 +251,7 @@ static const char *flash_physical_dataptr(int offset)
 int crec_flash_dataptr(int offset, int size_req, int align, const char **ptrp)
 {
 	if (!flash_range_ok(offset, size_req, align))
-		return -1;  /* Invalid range */
+		return -1; /* Invalid range */
 	if (ptrp)
 		*ptrp = flash_physical_dataptr(offset);
 
@@ -268,8 +268,8 @@ int crec_flash_dataptr(int offset, int size_req, int align, const char **ptrp)
 static uint32_t flash_read_pstate(void)
 {
 	const struct persist_state *pstate =
-		(const struct persist_state *)
-		flash_physical_dataptr(CONFIG_FW_PSTATE_OFF);
+		(const struct persist_state *)flash_physical_dataptr(
+			CONFIG_FW_PSTATE_OFF);
 
 	if ((pstate->version == PERSIST_STATE_VERSION) &&
 	    (pstate->valid_fields & PSTATE_VALID_FLAGS) &&
@@ -314,8 +314,6 @@ static int flash_write_pstate_data(struct persist_state *newpstate)
 					 (const char *)newpstate);
 }
 
-
-
 /**
  * Validate and Init persistent state datastructure.
  *
@@ -342,8 +340,8 @@ static int flash_write_pstate(uint32_t flags)
 {
 	struct persist_state newpstate;
 	const struct persist_state *pstate =
-		(const struct persist_state *)
-		flash_physical_dataptr(CONFIG_FW_PSTATE_OFF);
+		(const struct persist_state *)flash_physical_dataptr(
+			CONFIG_FW_PSTATE_OFF);
 
 	/* Only check the flags we write to pstate */
 	flags &= EC_FLASH_PROTECT_RO_AT_BOOT;
@@ -372,8 +370,8 @@ static int flash_write_pstate(uint32_t flags)
 const char *crec_flash_read_pstate_serial(void)
 {
 	const struct persist_state *pstate =
-		(const struct persist_state *)
-		flash_physical_dataptr(CONFIG_FW_PSTATE_OFF);
+		(const struct persist_state *)flash_physical_dataptr(
+			CONFIG_FW_PSTATE_OFF);
 
 	if ((pstate->version == PERSIST_STATE_VERSION) &&
 	    (pstate->valid_fields & PSTATE_VALID_SERIALNO)) {
@@ -394,8 +392,8 @@ int crec_flash_write_pstate_serial(const char *serialno)
 	int length;
 	struct persist_state newpstate;
 	const struct persist_state *pstate =
-		(const struct persist_state *)
-		flash_physical_dataptr(CONFIG_FW_PSTATE_OFF);
+		(const struct persist_state *)flash_physical_dataptr(
+			CONFIG_FW_PSTATE_OFF);
 
 	/* Check that this is OK */
 	if (!serialno)
@@ -432,8 +430,8 @@ int crec_flash_write_pstate_serial(const char *serialno)
 const char *crec_flash_read_pstate_mac_addr(void)
 {
 	const struct persist_state *pstate =
-		(const struct persist_state *)
-		flash_physical_dataptr(CONFIG_FW_PSTATE_OFF);
+		(const struct persist_state *)flash_physical_dataptr(
+			CONFIG_FW_PSTATE_OFF);
 
 	if ((pstate->version == PERSIST_STATE_VERSION) &&
 	    (pstate->valid_fields & PSTATE_VALID_MAC_ADDR)) {
@@ -454,8 +452,8 @@ int crec_flash_write_pstate_mac_addr(const char *mac_addr)
 	int length;
 	struct persist_state newpstate;
 	const struct persist_state *pstate =
-		(const struct persist_state *)
-		flash_physical_dataptr(CONFIG_FW_PSTATE_OFF);
+		(const struct persist_state *)flash_physical_dataptr(
+			CONFIG_FW_PSTATE_OFF);
 
 	/* Check that this is OK, data is valid and fits in the region. */
 	if (!mac_addr) {
@@ -559,10 +557,9 @@ static int flash_write_pstate(uint32_t flags)
 	 * Write a new pstate.  We can overwrite the existing value, because
 	 * we're only moving bits from the erased state to the unerased state.
 	 */
-	return crec_flash_physical_write(get_pstate_addr() -
-					 CONFIG_PROGRAM_MEMORY_BASE,
-					 sizeof(new_pstate),
-					 (const char *)&new_pstate);
+	return crec_flash_physical_write(
+		get_pstate_addr() - CONFIG_PROGRAM_MEMORY_BASE,
+		sizeof(new_pstate), (const char *)&new_pstate);
 }
 
 #endif /* !CONFIG_FLASH_PSTATE_BANK */
@@ -575,7 +572,7 @@ int crec_flash_is_erased(uint32_t offset, int size)
 #ifdef CONFIG_MAPPED_STORAGE
 	/* Use pointer directly to flash */
 	if (crec_flash_dataptr(offset, size, sizeof(uint32_t),
-			  (const char **)&ptr) < 0)
+			       (const char **)&ptr) < 0)
 		return 0;
 
 	crec_flash_lock_mapped_storage(1);
@@ -583,7 +580,7 @@ int crec_flash_is_erased(uint32_t offset, int size)
 		if (*ptr != CONFIG_FLASH_ERASED_VALUE32) {
 			crec_flash_lock_mapped_storage(0);
 			return 0;
-	}
+		}
 
 	crec_flash_lock_mapped_storage(0);
 #else
@@ -604,7 +601,6 @@ int crec_flash_is_erased(uint32_t offset, int size)
 		for (bsize /= sizeof(uint32_t); bsize > 0; bsize--, ptr++)
 			if (*ptr != CONFIG_FLASH_ERASED_VALUE32)
 				return 0;
-
 	}
 #endif
 
@@ -657,11 +653,11 @@ static void flash_abort_or_invalidate_hash(int offset, int size)
 	 * jump to RW after the timeout.
 	 */
 	if ((offset >= CONFIG_RW_MEM_OFF &&
-		    offset < (CONFIG_RW_MEM_OFF + CONFIG_RW_SIZE)) ||
+	     offset < (CONFIG_RW_MEM_OFF + CONFIG_RW_SIZE)) ||
 	    ((offset + size) > CONFIG_RW_MEM_OFF &&
-		    (offset + size) <= (CONFIG_RW_MEM_OFF + CONFIG_RW_SIZE)) ||
+	     (offset + size) <= (CONFIG_RW_MEM_OFF + CONFIG_RW_SIZE)) ||
 	    (offset < CONFIG_RW_MEM_OFF &&
-		    (offset + size) > (CONFIG_RW_MEM_OFF + CONFIG_RW_SIZE)))
+	     (offset + size) > (CONFIG_RW_MEM_OFF + CONFIG_RW_SIZE)))
 		rwsig_abort();
 #endif
 }
@@ -669,7 +665,7 @@ static void flash_abort_or_invalidate_hash(int offset, int size)
 int crec_flash_write(int offset, int size, const char *data)
 {
 	if (!flash_range_ok(offset, size, CONFIG_FLASH_WRITE_SIZE))
-		return EC_ERROR_INVAL;  /* Invalid range */
+		return EC_ERROR_INVAL; /* Invalid range */
 
 	flash_abort_or_invalidate_hash(offset, size);
 
@@ -680,7 +676,7 @@ int crec_flash_erase(int offset, int size)
 {
 #ifndef CONFIG_FLASH_MULTIPLE_REGION
 	if (!flash_range_ok(offset, size, CONFIG_FLASH_ERASE_SIZE))
-		return EC_ERROR_INVAL;  /* Invalid range */
+		return EC_ERROR_INVAL; /* Invalid range */
 #endif
 
 	flash_abort_or_invalidate_hash(offset, size);
@@ -736,7 +732,7 @@ uint32_t crec_flash_get_protect(void)
 	uint32_t flags = 0;
 	int i;
 	/* Region protection status */
-	int not_protected[FLASH_REGION_COUNT] = {0};
+	int not_protected[FLASH_REGION_COUNT] = { 0 };
 #ifdef CONFIG_ROLLBACK
 	/* Flags that must be set to set ALL_NOW flag. */
 	const uint32_t all_flags = EC_FLASH_PROTECT_RO_NOW |
@@ -759,11 +755,11 @@ uint32_t crec_flash_get_protect(void)
 	/* Scan flash protection */
 	for (i = 0; i < PHYSICAL_BANKS; i++) {
 		int is_ro = (i >= WP_BANK_OFFSET &&
-			i < WP_BANK_OFFSET + WP_BANK_COUNT);
+			     i < WP_BANK_OFFSET + WP_BANK_COUNT);
 		enum flash_region region = is_ro ? FLASH_REGION_RO :
-			FLASH_REGION_RW;
+						   FLASH_REGION_RW;
 		int bank_flag = is_ro ? EC_FLASH_PROTECT_RO_NOW :
-			EC_FLASH_PROTECT_RW_NOW;
+					EC_FLASH_PROTECT_RW_NOW;
 
 #ifdef CONFIG_ROLLBACK
 		if (i >= ROLLBACK_BANK_OFFSET &&
@@ -824,10 +820,11 @@ int crec_flash_set_protect(uint32_t mask, uint32_t flags)
 {
 	int retval = EC_SUCCESS;
 	int rv;
-	int old_flags_at_boot = crec_flash_get_protect() &
+	int old_flags_at_boot =
+		crec_flash_get_protect() &
 		(EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RW_AT_BOOT |
-			EC_FLASH_PROTECT_ROLLBACK_AT_BOOT |
-			EC_FLASH_PROTECT_ALL_AT_BOOT);
+		 EC_FLASH_PROTECT_ROLLBACK_AT_BOOT |
+		 EC_FLASH_PROTECT_ALL_AT_BOOT);
 	int new_flags_at_boot = old_flags_at_boot;
 
 	/* Sanitize input flags */
@@ -908,8 +905,8 @@ int crec_flash_set_protect(uint32_t mask, uint32_t flags)
 	 * All subsequent flags only work if write protect is enabled (that is,
 	 * hardware WP flag) *and* RO is protected at boot (software WP flag).
 	 */
-	if ((~crec_flash_get_protect()) & (EC_FLASH_PROTECT_GPIO_ASSERTED |
-				      EC_FLASH_PROTECT_RO_AT_BOOT))
+	if ((~crec_flash_get_protect()) &
+	    (EC_FLASH_PROTECT_GPIO_ASSERTED | EC_FLASH_PROTECT_RO_AT_BOOT))
 		return retval;
 
 	/*
@@ -948,8 +945,7 @@ int crec_flash_set_protect(uint32_t mask, uint32_t flags)
 		 * we're now protecting the RO region with SW WP.
 		 */
 		if (IS_ENABLED(CONFIG_EEPROM_CBI_WP) &&
-		    (EC_FLASH_PROTECT_GPIO_ASSERTED &
-		     crec_flash_get_protect()))
+		    (EC_FLASH_PROTECT_GPIO_ASSERTED & crec_flash_get_protect()))
 			cbi_latch_eeprom_wp();
 	}
 
@@ -982,7 +978,7 @@ DECLARE_DEFERRED(flash_erase_deferred);
 /* Console commands */
 
 #ifdef CONFIG_CMD_FLASHINFO
-static int command_flash_info(int argc, char **argv)
+static int command_flash_info(int argc, const char **argv)
 {
 	int i, flags;
 
@@ -992,8 +988,7 @@ static int command_flash_info(int argc, char **argv)
 #ifdef CONFIG_FLASH_MULTIPLE_REGION
 	ccprintf("Regions:\n");
 	for (i = 0; i < ARRAY_SIZE(flash_bank_array); i++) {
-		ccprintf(" %d region%s:\n",
-			 flash_bank_array[i].count,
+		ccprintf(" %d region%s:\n", flash_bank_array[i].count,
 			 (flash_bank_array[i].count == 1 ? "" : "s"));
 		ccprintf("  Erase:   %4d B (to %d-bits)\n",
 			 1 << flash_bank_array[i].erase_size_exp,
@@ -1049,13 +1044,12 @@ static int command_flash_info(int argc, char **argv)
 	ccputs("\n");
 	return EC_SUCCESS;
 }
-DECLARE_SAFE_CONSOLE_COMMAND(flashinfo, command_flash_info,
-			     NULL,
+DECLARE_SAFE_CONSOLE_COMMAND(flashinfo, command_flash_info, NULL,
 			     "Print flash info");
 #endif /* CONFIG_CMD_FLASHINFO */
 
 #ifdef CONFIG_CMD_FLASH
-static int command_flash_erase(int argc, char **argv)
+static int command_flash_erase(int argc, const char **argv)
 {
 	int offset = -1;
 	int size = -1;
@@ -1071,11 +1065,10 @@ static int command_flash_erase(int argc, char **argv)
 	ccprintf("Erasing %d bytes at 0x%x...\n", size, offset);
 	return crec_flash_erase(offset, size);
 }
-DECLARE_CONSOLE_COMMAND(flasherase, command_flash_erase,
-			"offset size",
+DECLARE_CONSOLE_COMMAND(flasherase, command_flash_erase, "offset size",
 			"Erase flash");
 
-static int command_flash_write(int argc, char **argv)
+static int command_flash_write(int argc, const char **argv)
 {
 	int offset = -1;
 	int size = -1;
@@ -1112,11 +1105,10 @@ static int command_flash_write(int argc, char **argv)
 
 	return rv;
 }
-DECLARE_CONSOLE_COMMAND(flashwrite, command_flash_write,
-			"offset size",
+DECLARE_CONSOLE_COMMAND(flashwrite, command_flash_write, "offset size",
 			"Write pattern to flash");
 
-static int command_flash_read(int argc, char **argv)
+static int command_flash_read(int argc, const char **argv)
 {
 	int offset = -1;
 	int size = 256;
@@ -1160,13 +1152,12 @@ static int command_flash_read(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(flashread, command_flash_read,
-			"offset [size]",
+DECLARE_CONSOLE_COMMAND(flashread, command_flash_read, "offset [size]",
 			"Read flash");
 #endif
 
 #ifdef CONFIG_CMD_FLASH_WP
-static int command_flash_wp(int argc, char **argv)
+static int command_flash_wp(int argc, const char **argv)
 {
 	int val;
 
@@ -1203,7 +1194,7 @@ static int command_flash_wp(int argc, char **argv)
 	/* Do this last, since anything starting with 'n' means "no" */
 	if (parse_bool(argv[1], &val))
 		return crec_flash_set_protect(EC_FLASH_PROTECT_RO_AT_BOOT,
-					 val ? -1 : 0);
+					      val ? -1 : 0);
 
 	return EC_ERROR_PARAM1;
 }
@@ -1215,7 +1206,8 @@ DECLARE_CONSOLE_COMMAND(flashwp, command_flash_wp,
 #ifdef CONFIG_ROLLBACK
 			" | rb | norb"
 #endif
-			, "Modify flash write protect");
+			,
+			"Modify flash write protect");
 #endif /* CONFIG_CMD_FLASH_WP */
 
 /*****************************************************************************/
@@ -1231,8 +1223,8 @@ DECLARE_CONSOLE_COMMAND(flashwp, command_flash_wp,
  * region belonging to the EC. TODO(crbug.com/529365): Handle fmap_base
  * correctly in flashrom, dump_fmap, etc. and remove EC_FLASH_REGION_START.
  */
-#define EC_FLASH_REGION_START MIN(CONFIG_EC_PROTECTED_STORAGE_OFF, \
-				  CONFIG_EC_WRITABLE_STORAGE_OFF)
+#define EC_FLASH_REGION_START \
+	MIN(CONFIG_EC_PROTECTED_STORAGE_OFF, CONFIG_EC_WRITABLE_STORAGE_OFF)
 
 static enum ec_status flash_command_get_info(struct host_cmd_handler_args *args)
 {
@@ -1263,8 +1255,8 @@ static enum ec_status flash_command_get_info(struct host_cmd_handler_args *args)
 	 * Compute the ideal amount of data for the host to send us,
 	 * based on the maximum response size and the ideal write size.
 	 */
-	ideal_size = (args->response_max -
-		 sizeof(struct ec_params_flash_write)) &
+	ideal_size =
+		(args->response_max - sizeof(struct ec_params_flash_write)) &
 		~(CONFIG_FLASH_WRITE_IDEAL_SIZE - 1);
 	/*
 	 * If we can't get at least one ideal block, then just want
@@ -1272,9 +1264,8 @@ static enum ec_status flash_command_get_info(struct host_cmd_handler_args *args)
 	 */
 	if (!ideal_size)
 		ideal_size = (args->response_max -
-				sizeof(struct ec_params_flash_write)) &
-				~(CONFIG_FLASH_WRITE_SIZE - 1);
-
+			      sizeof(struct ec_params_flash_write)) &
+			     ~(CONFIG_FLASH_WRITE_SIZE - 1);
 
 	if (args->version >= 2) {
 		args->response_size = sizeof(struct ec_response_flash_info_2);
@@ -1319,16 +1310,14 @@ static enum ec_status flash_command_get_info(struct host_cmd_handler_args *args)
 #endif
 	}
 	return EC_RES_SUCCESS;
-#endif  /* CONFIG_FLASH_MULTIPLE_REGION */
+#endif /* CONFIG_FLASH_MULTIPLE_REGION */
 }
 #ifdef CONFIG_FLASH_MULTIPLE_REGION
 #define FLASH_INFO_VER EC_VER_MASK(2)
 #else
 #define FLASH_INFO_VER (EC_VER_MASK(0) | EC_VER_MASK(1) | EC_VER_MASK(2))
 #endif
-DECLARE_HOST_COMMAND(EC_CMD_FLASH_INFO,
-		     flash_command_get_info, FLASH_INFO_VER);
-
+DECLARE_HOST_COMMAND(EC_CMD_FLASH_INFO, flash_command_get_info, FLASH_INFO_VER);
 
 static enum ec_status flash_command_read(struct host_cmd_handler_args *args)
 {
@@ -1345,9 +1334,7 @@ static enum ec_status flash_command_read(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_FLASH_READ,
-		     flash_command_read,
-		     EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_FLASH_READ, flash_command_read, EC_VER_MASK(0));
 
 /**
  * Flash write command
@@ -1376,8 +1363,7 @@ static enum ec_status flash_command_write(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_FLASH_WRITE,
-		     flash_command_write,
+DECLARE_HOST_COMMAND(EC_CMD_FLASH_WRITE, flash_command_write,
 		     EC_VER_MASK(0) | EC_VER_MASK(EC_VER_FLASH_WRITE));
 
 #ifndef CONFIG_FLASH_MULTIPLE_REGION
@@ -1453,13 +1439,12 @@ static enum ec_status flash_command_erase(struct host_cmd_handler_args *args)
 	return rc;
 }
 
-
 DECLARE_HOST_COMMAND(EC_CMD_FLASH_ERASE, flash_command_erase,
-		EC_VER_MASK(0)
+		     EC_VER_MASK(0)
 #ifdef CONFIG_FLASH_DEFERRED_ERASE
-		| EC_VER_MASK(1)
+			     | EC_VER_MASK(1)
 #endif
-		);
+);
 
 static enum ec_status flash_command_protect(struct host_cmd_handler_args *args)
 {
@@ -1484,12 +1469,11 @@ static enum ec_status flash_command_protect(struct host_cmd_handler_args *args)
 	r->flags = crec_flash_get_protect();
 
 	/* Indicate which flags are valid on this platform */
-	r->valid_flags =
-		EC_FLASH_PROTECT_GPIO_ASSERTED |
-		EC_FLASH_PROTECT_ERROR_STUCK |
-		EC_FLASH_PROTECT_ERROR_INCONSISTENT |
-		EC_FLASH_PROTECT_ERROR_UNKNOWN |
-		crec_flash_physical_get_valid_flags();
+	r->valid_flags = EC_FLASH_PROTECT_GPIO_ASSERTED |
+			 EC_FLASH_PROTECT_ERROR_STUCK |
+			 EC_FLASH_PROTECT_ERROR_INCONSISTENT |
+			 EC_FLASH_PROTECT_ERROR_UNKNOWN |
+			 crec_flash_physical_get_valid_flags();
 	r->writable_flags = crec_flash_physical_get_writable_flags(r->flags);
 
 	args->response_size = sizeof(*r);
@@ -1502,8 +1486,7 @@ static enum ec_status flash_command_protect(struct host_cmd_handler_args *args)
  * temporary workaround for a problem in the cros_ec driver. Drop
  * EC_VER_MASK(0) once cros_ec driver can send the correct version.
  */
-DECLARE_HOST_COMMAND(EC_CMD_FLASH_PROTECT,
-		     flash_command_protect,
+DECLARE_HOST_COMMAND(EC_CMD_FLASH_PROTECT, flash_command_protect,
 		     EC_VER_MASK(0) | EC_VER_MASK(1));
 
 static enum ec_status
@@ -1515,23 +1498,21 @@ flash_command_region_info(struct host_cmd_handler_args *args)
 	switch (p->region) {
 	case EC_FLASH_REGION_RO:
 		r->offset = CONFIG_EC_PROTECTED_STORAGE_OFF +
-			    CONFIG_RO_STORAGE_OFF -
-			    EC_FLASH_REGION_START;
+			    CONFIG_RO_STORAGE_OFF - EC_FLASH_REGION_START;
 		r->size = EC_FLASH_REGION_RO_SIZE;
 		break;
 	case EC_FLASH_REGION_ACTIVE:
 		r->offset = flash_get_rw_offset(system_get_active_copy()) -
-				EC_FLASH_REGION_START;
+			    EC_FLASH_REGION_START;
 		r->size = CONFIG_EC_WRITABLE_STORAGE_SIZE;
 		break;
 	case EC_FLASH_REGION_WP_RO:
-		r->offset = CONFIG_WP_STORAGE_OFF -
-			    EC_FLASH_REGION_START;
+		r->offset = CONFIG_WP_STORAGE_OFF - EC_FLASH_REGION_START;
 		r->size = CONFIG_WP_STORAGE_SIZE;
 		break;
 	case EC_FLASH_REGION_UPDATE:
 		r->offset = flash_get_rw_offset(system_get_update_copy()) -
-				EC_FLASH_REGION_START;
+			    EC_FLASH_REGION_START;
 		r->size = CONFIG_EC_WRITABLE_STORAGE_SIZE;
 		break;
 	default:
@@ -1541,11 +1522,9 @@ flash_command_region_info(struct host_cmd_handler_args *args)
 	args->response_size = sizeof(*r);
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_FLASH_REGION_INFO,
-		     flash_command_region_info,
+DECLARE_HOST_COMMAND(EC_CMD_FLASH_REGION_INFO, flash_command_region_info,
 		     EC_VER_MASK(EC_VER_FLASH_REGION_INFO));
 
-
 #ifdef CONFIG_FLASH_SELECT_REQUIRED
 
 static enum ec_status flash_command_select(struct host_cmd_handler_args *args)
@@ -1554,8 +1533,6 @@ static enum ec_status flash_command_select(struct host_cmd_handler_args *args)
 
 	return crec_board_flash_select(p->select);
 }
-DECLARE_HOST_COMMAND(EC_CMD_FLASH_SELECT,
-		     flash_command_select,
-		     EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_FLASH_SELECT, flash_command_select, EC_VER_MASK(0));
 
 #endif /* CONFIG_FLASH_SELECT_REQUIRED */
diff --git a/common/fmap.c b/common/fmap.c
index 6bae9c7f85..469fac0ceb 100644
--- a/common/fmap.c
+++ b/common/fmap.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2012 The Chromium OS Authors. All rights reserved.
+ * Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,7 +13,8 @@
 
 /*
  * FMAP structs.
- * See https://chromium.googlesource.com/chromiumos/third_party/flashmap/+/HEAD/lib/fmap.h
+ * See
+ * https://chromium.googlesource.com/chromiumos/third_party/flashmap/+/HEAD/lib/fmap.h
  */
 #define FMAP_NAMELEN 32
 #define FMAP_SIGNATURE "__FMAP__"
@@ -25,8 +26,8 @@
  * For address containing CONFIG_PROGRAM_MEMORY_BASE (symbols in *.RO.lds.S and
  * variable), this computes the offset to the start of the image on flash.
  */
-#define RELATIVE_RO(addr) ((addr) - CONFIG_PROGRAM_MEMORY_BASE - \
-			   CONFIG_RO_MEM_OFF)
+#define RELATIVE_RO(addr) \
+	((addr)-CONFIG_PROGRAM_MEMORY_BASE - CONFIG_RO_MEM_OFF)
 
 /*
  * All internal EC code assumes that offsets are provided relative to
@@ -45,23 +46,23 @@
 #endif
 
 struct fmap_header {
-	char        fmap_signature[FMAP_SIGNATURE_SIZE];
-	uint8_t     fmap_ver_major;
-	uint8_t     fmap_ver_minor;
-	uint64_t    fmap_base;
-	uint32_t    fmap_size;
-	char        fmap_name[FMAP_NAMELEN];
-	uint16_t    fmap_nareas;
+	char fmap_signature[FMAP_SIGNATURE_SIZE];
+	uint8_t fmap_ver_major;
+	uint8_t fmap_ver_minor;
+	uint64_t fmap_base;
+	uint32_t fmap_size;
+	char fmap_name[FMAP_NAMELEN];
+	uint16_t fmap_nareas;
 } __packed;
 
-#define FMAP_AREA_STATIC      BIT(0)	/* can be checksummed */
-#define FMAP_AREA_COMPRESSED  BIT(1)  /* may be compressed */
-#define FMAP_AREA_RO          BIT(2)  /* writes may fail */
+#define FMAP_AREA_STATIC BIT(0) /* can be checksummed */
+#define FMAP_AREA_COMPRESSED BIT(1) /* may be compressed */
+#define FMAP_AREA_RO BIT(2) /* writes may fail */
 
 struct fmap_area_header {
 	uint32_t area_offset;
 	uint32_t area_size;
-	char     area_name[FMAP_NAMELEN];
+	char area_name[FMAP_NAMELEN];
 	uint16_t area_flags;
 } __packed;
 
@@ -77,19 +78,18 @@ struct fmap_area_header {
 #define NUM_EC_FMAP_AREAS_ROLLBACK 0
 #endif
 #ifdef CONFIG_RW_B
-#  ifdef CONFIG_RWSIG_TYPE_RWSIG
-#    define NUM_EC_FMAP_AREAS_RW_B     2
-#  else
-#    define NUM_EC_FMAP_AREAS_RW_B     1
-#  endif
+#ifdef CONFIG_RWSIG_TYPE_RWSIG
+#define NUM_EC_FMAP_AREAS_RW_B 2
+#else
+#define NUM_EC_FMAP_AREAS_RW_B 1
+#endif
 #else
-#define NUM_EC_FMAP_AREAS_RW_B     0
+#define NUM_EC_FMAP_AREAS_RW_B 0
 #endif
 
-#define NUM_EC_FMAP_AREAS (7 + \
-			NUM_EC_FMAP_AREAS_RWSIG + \
-			NUM_EC_FMAP_AREAS_ROLLBACK + \
-			NUM_EC_FMAP_AREAS_RW_B)
+#define NUM_EC_FMAP_AREAS                                           \
+	(7 + NUM_EC_FMAP_AREAS_RWSIG + NUM_EC_FMAP_AREAS_ROLLBACK + \
+	 NUM_EC_FMAP_AREAS_RW_B)
 
 const struct _ec_fmap {
 	struct fmap_header header;
@@ -97,7 +97,7 @@ const struct _ec_fmap {
 } ec_fmap __keep __attribute__((section(".google"))) = {
 	/* Header */
 	{
-		.fmap_signature = {'_', '_', 'F', 'M', 'A', 'P', '_', '_'},
+		.fmap_signature = { '_', '_', 'F', 'M', 'A', 'P', '_', '_' },
 		.fmap_ver_major = FMAP_VER_MAJOR,
 		.fmap_ver_minor = FMAP_VER_MINOR,
 		.fmap_base = CONFIG_PROGRAM_MEMORY_BASE,
@@ -108,7 +108,7 @@ const struct _ec_fmap {
 	},
 
 	{
-	/* RO Firmware */
+		/* RO Firmware */
 		{
 			/*
 			 * Range of RO firmware to be updated. EC_RO
@@ -120,7 +120,7 @@ const struct _ec_fmap {
 			 */
 			.area_name = "EC_RO",
 			.area_offset = CONFIG_EC_PROTECTED_STORAGE_OFF -
-				FMAP_REGION_START,
+				       FMAP_REGION_START,
 			.area_size = CONFIG_RO_SIZE + CONFIG_RO_STORAGE_OFF,
 			.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
 		},
@@ -128,7 +128,8 @@ const struct _ec_fmap {
 			/* (Optional) RO firmware code. */
 			.area_name = "FR_MAIN",
 			.area_offset = CONFIG_EC_PROTECTED_STORAGE_OFF -
-				FMAP_REGION_START + CONFIG_RO_STORAGE_OFF,
+				       FMAP_REGION_START +
+				       CONFIG_RO_STORAGE_OFF,
 			.area_size = CONFIG_RO_SIZE,
 			.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
 		},
@@ -138,10 +139,11 @@ const struct _ec_fmap {
 			 * ASCII, and padded with \0.
 			 */
 			.area_name = "RO_FRID",
-			.area_offset = CONFIG_EC_PROTECTED_STORAGE_OFF -
+			.area_offset =
+				CONFIG_EC_PROTECTED_STORAGE_OFF -
 				FMAP_REGION_START + CONFIG_RO_STORAGE_OFF +
 				RELATIVE_RO((uint32_t)__image_data_offset) +
-				offsetof(struct image_data,  version),
+				offsetof(struct image_data, version),
 			.area_size = sizeof(current_image_data.version),
 			.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
 		},
@@ -150,8 +152,9 @@ const struct _ec_fmap {
 		{
 			.area_name = "FMAP",
 			.area_offset = CONFIG_EC_PROTECTED_STORAGE_OFF -
-				FMAP_REGION_START + CONFIG_RO_STORAGE_OFF +
-				RELATIVE_RO((uint32_t)&ec_fmap),
+				       FMAP_REGION_START +
+				       CONFIG_RO_STORAGE_OFF +
+				       RELATIVE_RO((uint32_t)&ec_fmap),
 			.area_size = sizeof(ec_fmap),
 			.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
 		},
@@ -162,8 +165,7 @@ const struct _ec_fmap {
 			 * EC_RO and aligned to hardware specification.
 			 */
 			.area_name = "WP_RO",
-			.area_offset = CONFIG_WP_STORAGE_OFF -
-				       FMAP_REGION_START,
+			.area_offset = CONFIG_WP_STORAGE_OFF - FMAP_REGION_START,
 			.area_size = CONFIG_WP_STORAGE_SIZE,
 			.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
 		},
@@ -172,8 +174,9 @@ const struct _ec_fmap {
 			/* RO public key address, for RW verification */
 			.area_name = "KEY_RO",
 			.area_offset = CONFIG_EC_PROTECTED_STORAGE_OFF -
-				FMAP_REGION_START + CONFIG_RO_PUBKEY_ADDR -
-				CONFIG_PROGRAM_MEMORY_BASE,
+				       FMAP_REGION_START +
+				       CONFIG_RO_PUBKEY_ADDR -
+				       CONFIG_PROGRAM_MEMORY_BASE,
 			.area_size = CONFIG_RO_PUBKEY_SIZE,
 			.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
 		},
@@ -181,10 +184,11 @@ const struct _ec_fmap {
 
 		/* RW Firmware */
 		{
-			 /* The range of RW firmware to be auto-updated. */
+			/* The range of RW firmware to be auto-updated. */
 			.area_name = "EC_RW",
 			.area_offset = CONFIG_EC_WRITABLE_STORAGE_OFF -
-				FMAP_REGION_START + CONFIG_RW_STORAGE_OFF,
+				       FMAP_REGION_START +
+				       CONFIG_RW_STORAGE_OFF,
 			.area_size = CONFIG_RW_SIZE,
 			.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
 		},
@@ -197,10 +201,11 @@ const struct _ec_fmap {
 			 * accommodate image asymmetry.
 			 */
 			.area_name = "RW_FWID",
-			.area_offset = CONFIG_EC_WRITABLE_STORAGE_OFF -
+			.area_offset =
+				CONFIG_EC_WRITABLE_STORAGE_OFF -
 				FMAP_REGION_START + CONFIG_RW_STORAGE_OFF +
 				RELATIVE_RO((uint32_t)__image_data_offset) +
-				offsetof(struct image_data,  version),
+				offsetof(struct image_data, version),
 			.area_size = sizeof(current_image_data.version),
 			.area_flags = FMAP_AREA_STATIC,
 		},
@@ -213,22 +218,22 @@ const struct _ec_fmap {
 			 * accommodate image asymmetry.
 			 */
 			.area_name = "RW_RBVER",
-			.area_offset = CONFIG_EC_WRITABLE_STORAGE_OFF -
+			.area_offset =
+				CONFIG_EC_WRITABLE_STORAGE_OFF -
 				FMAP_REGION_START + CONFIG_RW_STORAGE_OFF +
 				RELATIVE_RO((uint32_t)__image_data_offset) +
 				offsetof(struct image_data, rollback_version),
-			.area_size = sizeof(
-				current_image_data.rollback_version),
+			.area_size = sizeof(current_image_data.rollback_version),
 			.area_flags = FMAP_AREA_STATIC,
 		},
 #endif
 #ifdef CONFIG_RWSIG_TYPE_RWSIG
 		{
-			 /* RW image signature */
+			/* RW image signature */
 			.area_name = "SIG_RW",
 			.area_offset = CONFIG_EC_PROTECTED_STORAGE_OFF -
-				FMAP_REGION_START + CONFIG_RW_SIG_ADDR -
-				CONFIG_PROGRAM_MEMORY_BASE,
+				       FMAP_REGION_START + CONFIG_RW_SIG_ADDR -
+				       CONFIG_PROGRAM_MEMORY_BASE,
 			.area_size = CONFIG_RW_SIG_SIZE,
 			.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
 		},
@@ -236,21 +241,22 @@ const struct _ec_fmap {
 #ifdef CONFIG_RW_B
 		/* RW Firmware */
 		{
-			 /* The range of RW firmware to be auto-updated. */
+			/* The range of RW firmware to be auto-updated. */
 			.area_name = "EC_RW_B",
 			.area_offset = CONFIG_EC_WRITABLE_STORAGE_OFF -
-				FMAP_REGION_START + CONFIG_RW_STORAGE_OFF +
-				CONFIG_RW_SIZE,
+				       FMAP_REGION_START +
+				       CONFIG_RW_STORAGE_OFF + CONFIG_RW_SIZE,
 			.area_size = CONFIG_RW_SIZE,
 			.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
 		},
 #ifdef CONFIG_RWSIG_TYPE_RWSIG
 		{
-			 /* RW_B image signature */
+			/* RW_B image signature */
 			.area_name = "SIG_RW_B",
 			.area_offset = CONFIG_EC_PROTECTED_STORAGE_OFF -
-				FMAP_REGION_START + CONFIG_RW_B_SIG_ADDR -
-				CONFIG_PROGRAM_MEMORY_BASE,
+				       FMAP_REGION_START +
+				       CONFIG_RW_B_SIG_ADDR -
+				       CONFIG_PROGRAM_MEMORY_BASE,
 			.area_size = CONFIG_RW_SIG_SIZE,
 			.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
 		},
diff --git a/common/fpsensor/build.mk b/common/fpsensor/build.mk
index b2bb248efc..2b476bfa51 100644
--- a/common/fpsensor/build.mk
+++ b/common/fpsensor/build.mk
@@ -1,4 +1,4 @@
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/common/fpsensor/fpsensor.c b/common/fpsensor/fpsensor.c
index 12904c0b39..bd09ed5c3a 100644
--- a/common/fpsensor/fpsensor.c
+++ b/common/fpsensor/fpsensor.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -42,14 +42,14 @@ static timestamp_t encryption_deadline;
 #define FP_SENSOR_IMAGE_OFFSET 0
 #endif
 
-#define FP_MODE_ANY_CAPTURE (FP_MODE_CAPTURE | FP_MODE_ENROLL_IMAGE | \
-			     FP_MODE_MATCH)
-#define FP_MODE_ANY_DETECT_FINGER (FP_MODE_FINGER_DOWN | FP_MODE_FINGER_UP | \
-				   FP_MODE_ANY_CAPTURE)
-#define FP_MODE_ANY_WAIT_IRQ      (FP_MODE_FINGER_DOWN | FP_MODE_ANY_CAPTURE)
+#define FP_MODE_ANY_CAPTURE \
+	(FP_MODE_CAPTURE | FP_MODE_ENROLL_IMAGE | FP_MODE_MATCH)
+#define FP_MODE_ANY_DETECT_FINGER \
+	(FP_MODE_FINGER_DOWN | FP_MODE_FINGER_UP | FP_MODE_ANY_CAPTURE)
+#define FP_MODE_ANY_WAIT_IRQ (FP_MODE_FINGER_DOWN | FP_MODE_ANY_CAPTURE)
 
 /* Delay between 2 s of the sensor to detect finger removal */
-#define FINGER_POLLING_DELAY (100*MSEC)
+#define FINGER_POLLING_DELAY (100 * MSEC)
 
 /* Timing statistics. */
 static uint32_t capture_time_us;
@@ -76,8 +76,8 @@ static inline int is_raw_capture(uint32_t mode)
 {
 	int capture_type = FP_CAPTURE_TYPE(mode);
 
-	return (capture_type == FP_CAPTURE_VENDOR_FORMAT
-	     || capture_type == FP_CAPTURE_QUALITY_TEST);
+	return (capture_type == FP_CAPTURE_VENDOR_FORMAT ||
+		capture_type == FP_CAPTURE_QUALITY_TEST);
 }
 
 __maybe_unused static bool fp_match_success(int match_result)
@@ -92,10 +92,10 @@ static inline int is_test_capture(uint32_t mode)
 {
 	int capture_type = FP_CAPTURE_TYPE(mode);
 
-	return (mode & FP_MODE_CAPTURE)
-		&& (capture_type == FP_CAPTURE_PATTERN0
-		    || capture_type == FP_CAPTURE_PATTERN1
-		    || capture_type == FP_CAPTURE_RESET_TEST);
+	return (mode & FP_MODE_CAPTURE) &&
+	       (capture_type == FP_CAPTURE_PATTERN0 ||
+		capture_type == FP_CAPTURE_PATTERN1 ||
+		capture_type == FP_CAPTURE_RESET_TEST);
 }
 
 /*
@@ -119,8 +119,8 @@ static uint32_t fp_process_enroll(void)
 	res = fp_finger_enroll(fp_buffer, &percent);
 	CPRINTS("[%d]Enroll =>%d (%d%%)", templ_valid, res, percent);
 	if (res < 0)
-		return EC_MKBP_FP_ENROLL
-		     | EC_MKBP_FP_ERRCODE(EC_MKBP_FP_ERR_ENROLL_INTERNAL);
+		return EC_MKBP_FP_ENROLL |
+		       EC_MKBP_FP_ERRCODE(EC_MKBP_FP_ERR_ENROLL_INTERNAL);
 	templ_dirty |= BIT(templ_valid);
 	if (percent == 100) {
 		res = fp_enrollment_finish(fp_template[templ_valid]);
@@ -128,15 +128,15 @@ static uint32_t fp_process_enroll(void)
 			res = EC_MKBP_FP_ERR_ENROLL_INTERNAL;
 		} else {
 			template_newly_enrolled = templ_valid;
-			fp_enable_positive_match_secret(templ_valid,
-				&positive_match_secret_state);
+			fp_enable_positive_match_secret(
+				templ_valid, &positive_match_secret_state);
 			templ_valid++;
 		}
 		sensor_mode &= ~FP_MODE_ENROLL_SESSION;
 		enroll_session &= ~FP_MODE_ENROLL_SESSION;
 	}
-	return EC_MKBP_FP_ENROLL | EC_MKBP_FP_ERRCODE(res)
-	     | (percent << EC_MKBP_FP_ENROLL_PROGRESS_OFFSET);
+	return EC_MKBP_FP_ENROLL | EC_MKBP_FP_ERRCODE(res) |
+	       (percent << EC_MKBP_FP_ENROLL_PROGRESS_OFFSET);
 }
 
 static uint32_t fp_process_match(void)
@@ -161,8 +161,8 @@ static uint32_t fp_process_match(void)
 			 * with EC_MKBP_FP_ERR_MATCH_NO_INTERNAL.
 			 */
 			if (fgr >= 0 && fgr < FP_MAX_FINGER_COUNT) {
-				fp_enable_positive_match_secret(fgr,
-					&positive_match_secret_state);
+				fp_enable_positive_match_secret(
+					fgr, &positive_match_secret_state);
 			} else {
 				res = EC_MKBP_FP_ERR_MATCH_NO_INTERNAL;
 			}
@@ -187,8 +187,9 @@ static uint32_t fp_process_match(void)
 		timestamps_invalid |= FPSTATS_MATCHING_INV;
 
 	matching_time_us = time_since32(t0);
-	return EC_MKBP_FP_MATCH | EC_MKBP_FP_ERRCODE(res)
-	| ((fgr << EC_MKBP_FP_MATCH_IDX_OFFSET) & EC_MKBP_FP_MATCH_IDX_MASK);
+	return EC_MKBP_FP_MATCH | EC_MKBP_FP_ERRCODE(res) |
+	       ((fgr << EC_MKBP_FP_MATCH_IDX_OFFSET) &
+		EC_MKBP_FP_MATCH_IDX_MASK);
 }
 
 static void fp_process_finger(void)
@@ -260,12 +261,12 @@ void fp_task(void)
 				} else {
 					fp_enrollment_finish(NULL);
 				}
-				enroll_session =
-					sensor_mode & FP_MODE_ENROLL_SESSION;
+				enroll_session = sensor_mode &
+						 FP_MODE_ENROLL_SESSION;
 			}
 			if (is_test_capture(mode)) {
-				fp_sensor_acquire_image_with_mode(fp_buffer,
-					FP_CAPTURE_TYPE(mode));
+				fp_sensor_acquire_image_with_mode(
+					fp_buffer, FP_CAPTURE_TYPE(mode));
 				sensor_mode &= ~FP_MODE_CAPTURE;
 				send_mkbp_event(EC_MKBP_FP_IMAGE_READY);
 				continue;
@@ -343,13 +344,14 @@ static enum ec_status fp_command_passthru(struct host_cmd_handler_args *args)
 	if (system_is_locked())
 		return EC_RES_ACCESS_DENIED;
 
-	if (params->len > args->params_size +
-	    offsetof(struct ec_params_fp_passthru, data) ||
+	if (params->len >
+		    args->params_size +
+			    offsetof(struct ec_params_fp_passthru, data) ||
 	    params->len > args->response_max)
 		return EC_RES_INVALID_PARAM;
 
-	rc = spi_transaction_async(&spi_devices[0], params->data,
-				   params->len, out, SPI_READBACK_ALL);
+	rc = spi_transaction_async(&spi_devices[0], params->data, params->len,
+				   out, SPI_READBACK_ALL);
 	if (params->flags & EC_FP_FLAG_NOT_COMPLETE)
 		rc |= spi_transaction_wait(&spi_devices[0]);
 	else
@@ -381,8 +383,9 @@ static enum ec_status fp_command_info(struct host_cmd_handler_args *args)
 	r->template_version = FP_TEMPLATE_FORMAT_VERSION;
 
 	/* V1 is identical to V0 with more information appended */
-	args->response_size = args->version ? sizeof(*r) :
-			sizeof(struct ec_response_fp_info_v0);
+	args->response_size = args->version ?
+				      sizeof(*r) :
+				      sizeof(struct ec_response_fp_info_v0);
 	return EC_RES_SUCCESS;
 }
 DECLARE_HOST_COMMAND(EC_CMD_FP_INFO, fp_command_info,
@@ -472,23 +475,27 @@ static enum ec_status fp_command_frame(struct host_cmd_handler_args *args)
 		 */
 		enc_info = (void *)fp_enc_buffer;
 		enc_info->struct_version = FP_TEMPLATE_FORMAT_VERSION;
-		init_trng();
-		rand_bytes(enc_info->nonce, FP_CONTEXT_NONCE_BYTES);
-		rand_bytes(enc_info->encryption_salt,
-			   FP_CONTEXT_ENCRYPTION_SALT_BYTES);
-		exit_trng();
+		trng_init();
+		trng_rand_bytes(enc_info->nonce, FP_CONTEXT_NONCE_BYTES);
+		trng_rand_bytes(enc_info->encryption_salt,
+				FP_CONTEXT_ENCRYPTION_SALT_BYTES);
+		trng_exit();
 
-		if (fgr == template_newly_enrolled) {
+		/*
+		 * TODO(http://b/244781166): Use consistent types so cast is
+		 * not needed.
+		 */
+		if (fgr == (uint32_t)template_newly_enrolled) {
 			/*
 			 * Newly enrolled templates need new positive match
 			 * salt, new positive match secret and new validation
 			 * value.
 			 */
 			template_newly_enrolled = FP_NO_SUCH_TEMPLATE;
-			init_trng();
-			rand_bytes(fp_positive_match_salt[fgr],
-				   FP_POSITIVE_MATCH_SALT_BYTES);
-			exit_trng();
+			trng_init();
+			trng_rand_bytes(fp_positive_match_salt[fgr],
+					FP_POSITIVE_MATCH_SALT_BYTES);
+			trng_exit();
 		}
 
 		ret = derive_encryption_key(key, enc_info->encryption_salt);
@@ -508,8 +515,7 @@ static enum ec_status fp_command_frame(struct host_cmd_handler_args *args)
 
 		/* Encrypt the secret blob in-place. */
 		ret = aes_gcm_encrypt(key, SBP_ENC_KEY_LEN, encrypted_template,
-				      encrypted_template,
-				      encrypted_blob_size,
+				      encrypted_template, encrypted_blob_size,
 				      enc_info->nonce, FP_CONTEXT_NONCE_BYTES,
 				      enc_info->tag, FP_CONTEXT_TAG_BYTES);
 		always_memset(key, 0, sizeof(key));
@@ -550,12 +556,11 @@ DECLARE_HOST_COMMAND(EC_CMD_FP_STATS, fp_command_stats, EC_VER_MASK(0));
 static bool template_needs_validation_value(
 	struct ec_fp_template_encryption_metadata *enc_info)
 {
-	return enc_info->struct_version == 3
-		&& FP_TEMPLATE_FORMAT_VERSION == 4;
+	return enc_info->struct_version == 3 && FP_TEMPLATE_FORMAT_VERSION == 4;
 }
 
-static int validate_template_format(
-	struct ec_fp_template_encryption_metadata *enc_info)
+static int
+validate_template_format(struct ec_fp_template_encryption_metadata *enc_info)
 {
 	if (template_needs_validation_value(enc_info))
 		/* The host requested migration to v4. */
@@ -619,9 +624,8 @@ static enum ec_status fp_command_template(struct host_cmd_handler_args *args)
 		if (enc_info->struct_version <= 3) {
 			encrypted_blob_size = sizeof(fp_template[0]);
 		} else {
-			encrypted_blob_size =
-				sizeof(fp_template[0]) +
-				sizeof(fp_positive_match_salt[0]);
+			encrypted_blob_size = sizeof(fp_template[0]) +
+					      sizeof(fp_positive_match_salt[0]);
 		}
 
 		ret = derive_encryption_key(key, enc_info->encryption_salt);
@@ -632,8 +636,7 @@ static enum ec_status fp_command_template(struct host_cmd_handler_args *args)
 
 		/* Decrypt the secret blob in-place. */
 		ret = aes_gcm_decrypt(key, SBP_ENC_KEY_LEN, encrypted_template,
-				      encrypted_template,
-				      encrypted_blob_size,
+				      encrypted_template, encrypted_blob_size,
 				      enc_info->nonce, FP_CONTEXT_NONCE_BYTES,
 				      enc_info->tag, FP_CONTEXT_TAG_BYTES);
 		always_memset(key, 0, sizeof(key));
@@ -647,10 +650,10 @@ static enum ec_status fp_command_template(struct host_cmd_handler_args *args)
 		       sizeof(fp_template[0]));
 		if (template_needs_validation_value(enc_info)) {
 			CPRINTS("fgr%d: Generating positive match salt.", idx);
-			init_trng();
-			rand_bytes(positive_match_salt,
-				   FP_POSITIVE_MATCH_SALT_BYTES);
-			exit_trng();
+			trng_init();
+			trng_rand_bytes(positive_match_salt,
+					FP_POSITIVE_MATCH_SALT_BYTES);
+			trng_exit();
 		}
 		if (bytes_are_trivial(positive_match_salt,
 				      sizeof(fp_positive_match_salt[0]))) {
@@ -703,7 +706,8 @@ DECLARE_HOST_COMMAND(EC_CMD_FP_TEMPLATE, fp_command_template, EC_VER_MASK(0));
  * Add the following to your ${HOME}/.screenrc:
  *
  * zmodem catch
- * zmodem recvcmd '!!! bash -c "ascii-xfr -rdv /tmp/finger.pgm && display /tmp/finger.pgm"'
+ * zmodem recvcmd '!!! bash -c "ascii-xfr -rdv /tmp/finger.pgm && display
+ * /tmp/finger.pgm"'
  *
  * From *outside the chroot*, use screen to connect to UART console:
  *
@@ -761,7 +765,7 @@ static enum ec_error_list fp_console_action(uint32_t mode)
 	return EC_ERROR_TIMEOUT;
 }
 
-static int command_fpcapture(int argc, char **argv)
+static int command_fpcapture(int argc, const char **argv)
 {
 	int capture_type = FP_CAPTURE_SIMPLE_IMAGE;
 	uint32_t mode;
@@ -781,8 +785,8 @@ static int command_fpcapture(int argc, char **argv)
 		if (*e || capture_type < 0)
 			return EC_ERROR_PARAM1;
 	}
-	mode = FP_MODE_CAPTURE | ((capture_type << FP_MODE_CAPTURE_TYPE_SHIFT)
-				  & FP_MODE_CAPTURE_TYPE_MASK);
+	mode = FP_MODE_CAPTURE | ((capture_type << FP_MODE_CAPTURE_TYPE_SHIFT) &
+				  FP_MODE_CAPTURE_TYPE_MASK);
 
 	rc = fp_console_action(mode);
 	if (rc == EC_SUCCESS)
@@ -794,13 +798,13 @@ DECLARE_CONSOLE_COMMAND_FLAGS(fpcapture, command_fpcapture, NULL,
 			      "Capture fingerprint in PGM format",
 			      CMD_FLAG_RESTRICTED);
 
-static int command_fpenroll(int argc, char **argv)
+static int command_fpenroll(int argc, const char **argv)
 {
 	enum ec_error_list rc;
 	int percent = 0;
 	uint32_t event;
-	static const char * const enroll_str[] = {"OK", "Low Quality",
-						  "Immobile", "Low Coverage"};
+	static const char *const enroll_str[] = { "OK", "Low Quality",
+						  "Immobile", "Low Coverage" };
 
 	/*
 	 * TODO(b/142944002): Remove this redundant check for system_is_locked
@@ -832,11 +836,9 @@ static int command_fpenroll(int argc, char **argv)
 	return rc;
 }
 DECLARE_CONSOLE_COMMAND_FLAGS(fpenroll, command_fpenroll, NULL,
-			      "Enroll a new fingerprint",
-			      CMD_FLAG_RESTRICTED);
-
+			      "Enroll a new fingerprint", CMD_FLAG_RESTRICTED);
 
-static int command_fpmatch(int argc, char **argv)
+static int command_fpmatch(int argc, const char **argv)
 {
 	enum ec_error_list rc = fp_console_action(FP_MODE_MATCH);
 	uint32_t event = atomic_clear(&fp_events);
@@ -854,7 +856,7 @@ static int command_fpmatch(int argc, char **argv)
 DECLARE_CONSOLE_COMMAND(fpmatch, command_fpmatch, NULL,
 			"Run match algorithm against finger");
 
-static int command_fpclear(int argc, char **argv)
+static int command_fpclear(int argc, const char **argv)
 {
 	/*
 	 * We intentionally run this on the fp_task so that we use the
@@ -872,7 +874,7 @@ static int command_fpclear(int argc, char **argv)
 DECLARE_CONSOLE_COMMAND(fpclear, command_fpclear, NULL,
 			"Clear fingerprint sensor context");
 
-static int command_fpmaintenance(int argc, char **argv)
+static int command_fpmaintenance(int argc, const char **argv)
 {
 #ifdef HAVE_FP_PRIVATE_DRIVER
 	return fp_maintenance();
diff --git a/common/fpsensor/fpsensor_crypto.c b/common/fpsensor/fpsensor_crypto.c
index 73d7aca681..257042197e 100644
--- a/common/fpsensor/fpsensor_crypto.c
+++ b/common/fpsensor/fpsensor_crypto.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,7 +17,7 @@
 #error "fpsensor requires AES, AES_GCM and ROLLBACK_SECRET_SIZE"
 #endif
 
-static int get_ikm(uint8_t *ikm)
+test_export_static int get_ikm(uint8_t *ikm)
 {
 	int ret;
 
@@ -44,6 +44,14 @@ static int get_ikm(uint8_t *ikm)
 	return EC_SUCCESS;
 }
 
+test_mockable void compute_hmac_sha256(uint8_t *output, const uint8_t *key,
+				       const int key_len,
+				       const uint8_t *message,
+				       const int message_len)
+{
+	hmac_SHA256(output, key, key_len, message, message_len);
+}
+
 static void hkdf_extract(uint8_t *prk, const uint8_t *salt, size_t salt_size,
 			 const uint8_t *ikm, size_t ikm_size)
 {
@@ -51,12 +59,12 @@ static void hkdf_extract(uint8_t *prk, const uint8_t *salt, size_t salt_size,
 	 * Derive a key with the "extract" step of HKDF
 	 * https://tools.ietf.org/html/rfc5869#section-2.2
 	 */
-	hmac_SHA256(prk, salt, salt_size, ikm, ikm_size);
+	compute_hmac_sha256(prk, salt, salt_size, ikm, ikm_size);
 }
 
 static int hkdf_expand_one_step(uint8_t *out_key, size_t out_key_size,
-				uint8_t *prk, size_t prk_size,
-				uint8_t *info, size_t info_size)
+				uint8_t *prk, size_t prk_size, uint8_t *info,
+				size_t info_size)
 {
 	uint8_t key_buf[SHA256_DIGEST_SIZE];
 	uint8_t message_buf[SHA256_DIGEST_SIZE + 1];
@@ -75,7 +83,7 @@ static int hkdf_expand_one_step(uint8_t *out_key, size_t out_key_size,
 	memcpy(message_buf, info, info_size);
 	/* 1 step, set the counter byte to 1. */
 	message_buf[info_size] = 0x01;
-	hmac_SHA256(key_buf, prk, prk_size, message_buf, info_size + 1);
+	compute_hmac_sha256(key_buf, prk, prk_size, message_buf, info_size + 1);
 
 	memcpy(out_key, key_buf, out_key_size);
 	always_memset(key_buf, 0, sizeof(key_buf));
@@ -83,8 +91,8 @@ static int hkdf_expand_one_step(uint8_t *out_key, size_t out_key_size,
 	return EC_SUCCESS;
 }
 
-int hkdf_expand(uint8_t *out_key, size_t L, const uint8_t *prk,
-		size_t prk_size, const uint8_t *info, size_t info_size)
+int hkdf_expand(uint8_t *out_key, size_t L, const uint8_t *prk, size_t prk_size,
+		const uint8_t *info, size_t info_size)
 {
 	/*
 	 * "Expand" step of HKDF.
@@ -123,8 +131,8 @@ int hkdf_expand(uint8_t *out_key, size_t L, const uint8_t *prk,
 		memcpy(info_buffer, T, T_len);
 		memcpy(info_buffer + T_len, info, info_size);
 		info_buffer[T_len + info_size] = count;
-		hmac_SHA256(T_buffer, prk, prk_size, info_buffer,
-			    T_len + info_size + sizeof(count));
+		compute_hmac_sha256(T_buffer, prk, prk_size, info_buffer,
+				    T_len + info_size + sizeof(count));
 		memcpy(out_key, T_buffer, block_size);
 
 		T += T_len;
@@ -216,11 +224,9 @@ int derive_encryption_key(uint8_t *out_key, const uint8_t *salt)
 	return ret;
 }
 
-int aes_gcm_encrypt(const uint8_t *key, int key_size,
-		    const uint8_t *plaintext,
-		    uint8_t *ciphertext, int text_size,
-		    const uint8_t *nonce, int nonce_size,
-		    uint8_t *tag, int tag_size)
+int aes_gcm_encrypt(const uint8_t *key, int key_size, const uint8_t *plaintext,
+		    uint8_t *ciphertext, int text_size, const uint8_t *nonce,
+		    int nonce_size, uint8_t *tag, int tag_size)
 {
 	int res;
 	AES_KEY aes_key;
@@ -251,8 +257,8 @@ int aes_gcm_encrypt(const uint8_t *key, int key_size,
 
 int aes_gcm_decrypt(const uint8_t *key, int key_size, uint8_t *plaintext,
 		    const uint8_t *ciphertext, int text_size,
-		    const uint8_t *nonce, int nonce_size,
-		    const uint8_t *tag, int tag_size)
+		    const uint8_t *nonce, int nonce_size, const uint8_t *tag,
+		    int tag_size)
 {
 	int res;
 	AES_KEY aes_key;
diff --git a/common/fpsensor/fpsensor_detect_strings.c b/common/fpsensor/fpsensor_detect_strings.c
index 352dc90ee5..af08219ced 100644
--- a/common/fpsensor/fpsensor_detect_strings.c
+++ b/common/fpsensor/fpsensor_detect_strings.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/common/fpsensor/fpsensor_private.h b/common/fpsensor/fpsensor_private.h
index a42049dece..919c523273 100644
--- a/common/fpsensor/fpsensor_private.h
+++ b/common/fpsensor/fpsensor_private.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,8 +10,8 @@
 
 #include <stdint.h>
 
-#define CPRINTF(format, args...) cprintf(CC_FP, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_FP, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_FP, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_FP, format, ##args)
 
 int validate_fp_buffer_offset(uint32_t buffer_size, uint32_t offset,
 			      uint32_t size);
diff --git a/common/fpsensor/fpsensor_state.c b/common/fpsensor/fpsensor_state.c
index bd907e2c00..8153df9883 100644
--- a/common/fpsensor/fpsensor_state.c
+++ b/common/fpsensor/fpsensor_state.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,25 +19,25 @@
 /* Last acquired frame (aligned as it is used by arbitrary binary libraries) */
 uint8_t fp_buffer[FP_SENSOR_IMAGE_SIZE] FP_FRAME_SECTION __aligned(4);
 /* Fingers templates for the current user */
-uint8_t fp_template[FP_MAX_FINGER_COUNT][FP_ALGORITHM_TEMPLATE_SIZE]
-	FP_TEMPLATE_SECTION;
+uint8_t fp_template[FP_MAX_FINGER_COUNT]
+		   [FP_ALGORITHM_TEMPLATE_SIZE] FP_TEMPLATE_SECTION;
 /* Encryption/decryption buffer */
 /* TODO: On-the-fly encryption/decryption without a dedicated buffer */
 /*
  * Store the encryption metadata at the beginning of the buffer containing the
  * ciphered data.
  */
-uint8_t fp_enc_buffer[FP_ALGORITHM_ENCRYPTED_TEMPLATE_SIZE]
-	FP_TEMPLATE_SECTION;
+uint8_t fp_enc_buffer[FP_ALGORITHM_ENCRYPTED_TEMPLATE_SIZE] FP_TEMPLATE_SECTION;
 /* Salt used in derivation of positive match secret. */
-uint8_t fp_positive_match_salt
-	[FP_MAX_FINGER_COUNT][FP_POSITIVE_MATCH_SALT_BYTES];
+uint8_t fp_positive_match_salt[FP_MAX_FINGER_COUNT]
+			      [FP_POSITIVE_MATCH_SALT_BYTES];
 
-struct positive_match_secret_state positive_match_secret_state = {
-	.template_matched = FP_NO_SUCH_TEMPLATE,
-	.readable = false,
-	.deadline.val = 0,
-};
+struct positive_match_secret_state
+	positive_match_secret_state = { .template_matched = FP_NO_SUCH_TEMPLATE,
+					.readable = false,
+					.deadline = {
+						.val = 0,
+					} };
 
 /* Index of the last enrolled but not retrieved template. */
 int8_t template_newly_enrolled = FP_NO_SUCH_TEMPLATE;
@@ -178,7 +178,7 @@ static int validate_fp_mode(const uint32_t mode)
 	return EC_SUCCESS;
 }
 
-int fp_set_sensor_mode(uint32_t mode, uint32_t *mode_output)
+enum ec_status fp_set_sensor_mode(uint32_t mode, uint32_t *mode_output)
 {
 	int ret;
 
@@ -205,7 +205,7 @@ static enum ec_status fp_command_mode(struct host_cmd_handler_args *args)
 	const struct ec_params_fp_mode *p = args->params;
 	struct ec_response_fp_mode *r = args->response;
 
-	int ret = fp_set_sensor_mode(p->mode, &r->mode);
+	enum ec_status ret = fp_set_sensor_mode(p->mode, &r->mode);
 
 	if (ret == EC_RES_SUCCESS)
 		args->response_size = sizeof(*r);
@@ -262,23 +262,22 @@ int fp_enable_positive_match_secret(uint32_t fgr,
 	return EC_SUCCESS;
 }
 
-void fp_disable_positive_match_secret(
-	struct positive_match_secret_state *state)
+void fp_disable_positive_match_secret(struct positive_match_secret_state *state)
 {
 	state->template_matched = FP_NO_SUCH_TEMPLATE;
 	state->readable = false;
 	state->deadline.val = 0;
 }
 
-static enum ec_status fp_command_read_match_secret(
-	struct host_cmd_handler_args *args)
+static enum ec_status
+fp_command_read_match_secret(struct host_cmd_handler_args *args)
 {
 	const struct ec_params_fp_read_match_secret *params = args->params;
 	struct ec_response_fp_read_match_secret *response = args->response;
 	int8_t fgr = params->fgr;
 	timestamp_t now = get_time();
-	struct positive_match_secret_state state_copy
-		= positive_match_secret_state;
+	struct positive_match_secret_state state_copy =
+		positive_match_secret_state;
 
 	fp_disable_positive_match_secret(&positive_match_secret_state);
 
@@ -293,13 +292,14 @@ static enum ec_status fp_command_read_match_secret(
 	}
 	if (fgr != state_copy.template_matched || !state_copy.readable) {
 		CPRINTS("Positive match secret for finger %d is not meant to "
-			"be read now.", fgr);
+			"be read now.",
+			fgr);
 		return EC_RES_ACCESS_DENIED;
 	}
 
 	if (derive_positive_match_secret(response->positive_match_secret,
-					 fp_positive_match_salt[fgr])
-		!= EC_SUCCESS) {
+					 fp_positive_match_salt[fgr]) !=
+	    EC_SUCCESS) {
 		CPRINTS("Failed to derive positive match secret for finger %d",
 			fgr);
 		/* Keep the template and encryption salt. */
diff --git a/common/gesture.c b/common/gesture.c
index 0ccd358d54..99d054783d 100644
--- a/common/gesture.c
+++ b/common/gesture.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,9 +19,8 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_GESTURE, outstr)
-#define CPRINTS(format, args...) cprints(CC_GESTURE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_GESTURE, format, ## args)
-
+#define CPRINTS(format, args...) cprints(CC_GESTURE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_GESTURE, format, ##args)
 
 /*
  * Double tap detection parameters
@@ -34,16 +33,16 @@
  * which to check for relatively calm periods. In between the two impulses
  * there is a minimum and maximum interstice time allowed.
  */
-#define OUTER_WINDOW \
+#define OUTER_WINDOW                         \
 	(CONFIG_GESTURE_TAP_OUTER_WINDOW_T / \
 	 CONFIG_GESTURE_SAMPLING_INTERVAL_MS)
-#define INNER_WINDOW \
+#define INNER_WINDOW                         \
 	(CONFIG_GESTURE_TAP_INNER_WINDOW_T / \
 	 CONFIG_GESTURE_SAMPLING_INTERVAL_MS)
-#define MIN_INTERSTICE \
+#define MIN_INTERSTICE                         \
 	(CONFIG_GESTURE_TAP_MIN_INTERSTICE_T / \
 	 CONFIG_GESTURE_SAMPLING_INTERVAL_MS)
-#define MAX_INTERSTICE \
+#define MAX_INTERSTICE                         \
 	(CONFIG_GESTURE_TAP_MAX_INTERSTICE_T / \
 	 CONFIG_GESTURE_SAMPLING_INTERVAL_MS)
 #define MAX_WINDOW OUTER_WINDOW
@@ -67,10 +66,10 @@ enum tap_states {
 
 /* Tap sensor to use */
 static struct motion_sensor_t *sensor =
-&motion_sensors[CONFIG_GESTURE_TAP_SENSOR];
+	&motion_sensors[CONFIG_GESTURE_TAP_SENSOR];
 
 /* Tap state information */
-static int history_z[MAX_WINDOW];  /* Changes in Z */
+static int history_z[MAX_WINDOW]; /* Changes in Z */
 static int history_xy[MAX_WINDOW]; /* Changes in X and Y */
 static int state, history_idx;
 static int history_initialized, history_init_index;
@@ -166,7 +165,7 @@ static int gesture_tap_for_battery(void)
 			(OUTER_WINDOW - INNER_WINDOW);
 	delta_z_inner = sum_z_inner * 1000 / INNER_WINDOW;
 	delta_xy_outer = (sum_xy_outer - sum_xy_inner) * 1000 /
-			(OUTER_WINDOW - INNER_WINDOW);
+			 (OUTER_WINDOW - INNER_WINDOW);
 	delta_xy_inner = sum_xy_inner * 1000 / INNER_WINDOW;
 
 	state_cnt++;
@@ -253,13 +252,11 @@ static int gesture_tap_for_battery(void)
 	}
 
 	/* On state transitions, print debug info */
-	if (tap_debug &&
-	    (state != state_p ||
-	     (state_cnt % 10000 == 9999))) {
+	if (tap_debug && (state != state_p || (state_cnt % 10000 == 9999))) {
 		/* make sure we don't divide by 0 */
 		if (delta_z_outer == 0 || delta_xy_inner == 0)
-			CPRINTS("tap st %d->%d, error div by 0",
-				state_p, state);
+			CPRINTS("tap st %d->%d, error div by 0", state_p,
+				state);
 		else
 			CPRINTS("tap st %d->%d, st_cnt %-3d "
 				"Z_in:Z_out %-3d, Z_in:XY_in %-3d "
@@ -267,10 +264,8 @@ static int gesture_tap_for_battery(void)
 				"dZ_out %-8.3d",
 				state_p, state, state_cnt,
 				delta_z_inner / delta_z_outer,
-				delta_z_inner / delta_xy_inner,
-				delta_z_inner,
-				delta_z_inner_max,
-				delta_z_outer);
+				delta_z_inner / delta_xy_inner, delta_z_inner,
+				delta_z_inner_max, delta_z_outer);
 	}
 
 	return ret;
@@ -281,8 +276,7 @@ static void gesture_chipset_resume(void)
 	/* disable tap detection */
 	tap_detection = 0;
 }
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, gesture_chipset_resume,
-	     GESTURE_HOOK_PRIO);
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, gesture_chipset_resume, GESTURE_HOOK_PRIO);
 
 static void gesture_chipset_suspend(void)
 {
@@ -295,8 +289,7 @@ static void gesture_chipset_suspend(void)
 	state = TAP_IDLE;
 	tap_detection = 1;
 }
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, gesture_chipset_suspend,
-	     GESTURE_HOOK_PRIO);
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, gesture_chipset_suspend, GESTURE_HOOK_PRIO);
 
 void gesture_calc(uint32_t *event)
 {
@@ -306,17 +299,17 @@ void gesture_calc(uint32_t *event)
 
 	if (gesture_tap_for_battery())
 		*event |= TASK_EVENT_MOTION_ACTIVITY_INTERRUPT(
-				MOTIONSENSE_ACTIVITY_DOUBLE_TAP);
+			MOTIONSENSE_ACTIVITY_DOUBLE_TAP);
 }
 
 /*****************************************************************************/
 /* Console commands */
-static int command_tap_info(int argc, char **argv)
+static int command_tap_info(int argc, const char **argv)
 {
 	int val;
 
-	ccprintf("tap:   %s\n", (tap_detection && !lid_is_open()) ?
-					"on" : "off");
+	ccprintf("tap:   %s\n",
+		 (tap_detection && !lid_is_open()) ? "on" : "off");
 
 	if (argc > 1) {
 		if (!parse_bool(argv[1], &val))
@@ -329,6 +322,5 @@ static int command_tap_info(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(tapinfo, command_tap_info,
-			"debug on/off",
+DECLARE_CONSOLE_COMMAND(tapinfo, command_tap_info, "debug on/off",
 			"Print tap information");
diff --git a/common/gpio.c b/common/gpio.c
index 9fa8512e27..2e76116e4c 100644
--- a/common/gpio.c
+++ b/common/gpio.c
@@ -1,10 +1,11 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* GPIO common functionality for Chrome EC */
 
+#include "builtin/assert.h"
 #include "common.h"
 #include "gpio.h"
 #include "ioexpander.h"
@@ -34,9 +35,9 @@ struct gpio_alt_func {
  * Construct the gpio_alt_funcs array.  This array is used by gpio_config_module
  * to enable and disable GPIO alternate functions on a module by module basis.
  */
-#define ALTERNATE(pinmask, function, module, flagz)                            \
-	{GPIO_##pinmask, .func = (function), .module_id = (module),            \
-	 .flags = (flagz)},
+#define ALTERNATE(pinmask, function, module, flagz)                  \
+	{ GPIO_##pinmask, .func = (function), .module_id = (module), \
+	  .flags = (flagz) },
 
 static __const_data const struct gpio_alt_func gpio_alt_funcs[] = {
 #include "gpio.wrap"
@@ -74,9 +75,9 @@ static int gpio_config_pins(enum module_id id, uint32_t port, uint32_t pin_mask,
 				gpio_set_flags_by_mask(
 					af->port, (af->mask & pin_mask),
 					enable ? af->flags : GPIO_INPUT);
-			gpio_set_alternate_function(af->port,
-				    (af->mask & pin_mask),
-				    enable ? af->func : GPIO_ALT_FUNC_NONE);
+			gpio_set_alternate_function(
+				af->port, (af->mask & pin_mask),
+				enable ? af->func : GPIO_ALT_FUNC_NONE);
 			rv = EC_SUCCESS;
 			/* We're done here if we were just setting one port. */
 			if (port != GPIO_CONFIG_ALL_PORTS)
@@ -222,8 +223,8 @@ int gpio_or_ioex_get_level(int signal, int *value)
 
 int signal_is_gpio(int signal)
 {
-	return ((signal >= GPIO_SIGNAL_START)
-		&& (signal < GPIO_SIGNAL_START + GPIO_COUNT));
+	return ((signal >= GPIO_SIGNAL_START) &&
+		(signal < GPIO_SIGNAL_START + GPIO_COUNT));
 }
 
 __attribute__((weak)) void gpio_set_wakepin(enum gpio_signal signal,
diff --git a/common/gpio_commands.c b/common/gpio_commands.c
index b044524797..d6257ea61d 100644
--- a/common/gpio_commands.c
+++ b/common/gpio_commands.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -67,8 +67,13 @@ static enum ec_error_list set(const char *name, int value)
 	if (!gpio_is_implemented(signal))
 		return EC_ERROR_INVAL;
 
-	if (!(gpio_get_default_flags(signal) & GPIO_OUTPUT))
-		return EC_ERROR_INVAL;
+	if (IS_ENABLED(CONFIG_GPIO_GET_EXTENDED)) {
+		if (!(gpio_get_flags(signal) & GPIO_OUTPUT))
+			return EC_ERROR_INVAL;
+	} else {
+		if (!(gpio_get_default_flags(signal) & GPIO_OUTPUT))
+			return EC_ERROR_INVAL;
+	}
 
 	gpio_set_level(signal, value);
 
@@ -78,23 +83,18 @@ static enum ec_error_list set(const char *name, int value)
 /* Console commands */
 
 struct gpio_flag_description {
-    const int bitfield;
-    const char* name;
+	const int bitfield;
+	const char *name;
 };
 
 __maybe_unused static const struct gpio_flag_description gpio_descriptions[] = {
-	{GPIO_INPUT, "I"},
-	{GPIO_OUTPUT, "O"},
-	{GPIO_LOW, "L"},
-	{GPIO_HIGH, "H"},
-	{GPIO_OPEN_DRAIN, "ODR"},
-	{GPIO_PULL_UP, "PU"},
-	{GPIO_PULL_DOWN, "PD"},
-	{GPIO_SEL_1P8V, "1P8"},
+	{ GPIO_INPUT, "I" },	    { GPIO_OUTPUT, "O" },
+	{ GPIO_LOW, "L" },	    { GPIO_HIGH, "H" },
+	{ GPIO_OPEN_DRAIN, "ODR" }, { GPIO_PULL_UP, "PU" },
+	{ GPIO_PULL_DOWN, "PD" },   { GPIO_SEL_1P8V, "1P8" },
 #ifndef CONFIG_ZEPHYR
-	{GPIO_ANALOG, "A"},
-	{GPIO_ALTERNATE, "ALT"},
-	{GPIO_LOCKED, "LCK"}
+	{ GPIO_ANALOG, "A" },	    { GPIO_ALTERNATE, "ALT" },
+	{ GPIO_LOCKED, "LCK" }
 #endif
 };
 
@@ -103,12 +103,13 @@ static void print_gpio_info(int gpio)
 	int changed, v, i;
 
 	if (!gpio_is_implemented(gpio))
-		return;  /* Skip unsupported signals */
+		return; /* Skip unsupported signals */
 
 	v = gpio_get_level(gpio);
 	changed = last_val_changed(gpio, v);
 
-	/* Split the printf call into multiple calls to reduce the stack usage. */
+	/* Split the printf call into multiple calls to reduce the stack usage.
+	 */
 	ccprintf("  %d%c ", v, (changed ? '*' : ' '));
 
 	if (IS_ENABLED(CONFIG_CMD_GPIO_EXTENDED)) {
@@ -126,7 +127,7 @@ static void print_gpio_info(int gpio)
 	cflush();
 }
 
-static int command_gpio_get(int argc, char **argv)
+static int command_gpio_get(int argc, const char **argv)
 {
 	int i;
 
@@ -143,18 +144,17 @@ static int command_gpio_get(int argc, char **argv)
 	/* Otherwise print them all */
 	for (i = 0; i < GPIO_COUNT; i++) {
 		if (!gpio_is_implemented(i))
-			continue;  /* Skip unsupported signals */
+			continue; /* Skip unsupported signals */
 
 		print_gpio_info(i);
 	}
 
 	return EC_SUCCESS;
 }
-DECLARE_SAFE_CONSOLE_COMMAND(gpioget, command_gpio_get,
-			     "[name]",
+DECLARE_SAFE_CONSOLE_COMMAND(gpioget, command_gpio_get, "[name]",
 			     "Read GPIO value(s)");
 
-static int command_gpio_set(int argc, char **argv)
+static int command_gpio_set(int argc, const char **argv)
 {
 #ifdef CONFIG_CMD_GPIO_EXTENDED
 	int gpio;
@@ -217,9 +217,7 @@ DECLARE_CONSOLE_COMMAND_FLAGS(gpioset, command_gpio_set,
 #else
 			      "name <0 | 1>",
 #endif
-			      "Set a GPIO",
-			      CMD_FLAG_RESTRICTED
-);
+			      "Set a GPIO", CMD_FLAG_RESTRICTED);
 
 /*****************************************************************************/
 /* Host commands */
@@ -262,7 +260,7 @@ static enum ec_status gpio_command_get(struct host_cmd_handler_args *args)
 
 		i = p_v1->get_info.index;
 		len = strlen(gpio_get_name(i));
-		memcpy(r_v1->get_info.name, gpio_get_name(i), len+1);
+		memcpy(r_v1->get_info.name, gpio_get_name(i), len + 1);
 		r_v1->get_info.val = gpio_get_level(i);
 		r_v1->get_info.flags = gpio_get_default_flags(i);
 		args->response_size = sizeof(r_v1->get_info);
@@ -272,7 +270,6 @@ static enum ec_status gpio_command_get(struct host_cmd_handler_args *args)
 	}
 
 	return EC_RES_SUCCESS;
-
 }
 DECLARE_HOST_COMMAND(EC_CMD_GPIO_GET, gpio_command_get,
 		     EC_VER_MASK(0) | EC_VER_MASK(1));
diff --git a/common/gyro_cal.c b/common/gyro_cal.c
index 572e401b18..8996b85757 100644
--- a/common/gyro_cal.c
+++ b/common/gyro_cal.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/common/gyro_still_det.c b/common/gyro_still_det.c
index 4574e22e5f..303b73b15f 100644
--- a/common/gyro_still_det.c
+++ b/common/gyro_still_det.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/common/hooks.c b/common/hooks.c
index 061586c4cb..3bd9689d64 100644
--- a/common/hooks.c
+++ b/common/hooks.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,7 +14,7 @@
 
 #ifdef CONFIG_HOOK_DEBUG
 #define CPUTS(outstr) cputs(CC_HOOK, outstr)
-#define CPRINTS(format, args...) cprints(CC_HOOK, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_HOOK, format, ##args)
 #else
 #define CPUTS(outstr)
 #define CPRINTS(format, args...)
@@ -32,37 +32,38 @@ struct hook_ptrs {
  * order as enum hook_type.
  */
 static const struct hook_ptrs hook_list[] = {
-	{__hooks_init, __hooks_init_end},
-	{__hooks_pre_freq_change, __hooks_pre_freq_change_end},
-	{__hooks_freq_change, __hooks_freq_change_end},
-	{__hooks_sysjump, __hooks_sysjump_end},
-	{__hooks_chipset_pre_init, __hooks_chipset_pre_init_end},
-	{__hooks_chipset_startup, __hooks_chipset_startup_end},
-	{__hooks_chipset_resume, __hooks_chipset_resume_end},
-	{__hooks_chipset_suspend, __hooks_chipset_suspend_end},
+	{ __hooks_init, __hooks_init_end },
+	{ __hooks_pre_freq_change, __hooks_pre_freq_change_end },
+	{ __hooks_freq_change, __hooks_freq_change_end },
+	{ __hooks_sysjump, __hooks_sysjump_end },
+	{ __hooks_chipset_pre_init, __hooks_chipset_pre_init_end },
+	{ __hooks_chipset_startup, __hooks_chipset_startup_end },
+	{ __hooks_chipset_resume, __hooks_chipset_resume_end },
+	{ __hooks_chipset_suspend, __hooks_chipset_suspend_end },
 #ifdef CONFIG_CHIPSET_RESUME_INIT_HOOK
-	{__hooks_chipset_resume_init, __hooks_chipset_resume_init_end},
-	{__hooks_chipset_suspend_complete,
-	 __hooks_chipset_suspend_complete_end},
+	{ __hooks_chipset_resume_init, __hooks_chipset_resume_init_end },
+	{ __hooks_chipset_suspend_complete,
+	  __hooks_chipset_suspend_complete_end },
 #endif
-	{__hooks_chipset_shutdown, __hooks_chipset_shutdown_end},
-	{__hooks_chipset_shutdown_complete,
-	 __hooks_chipset_shutdown_complete_end},
-	{__hooks_chipset_hard_off, __hooks_chipset_hard_off_end},
-	{__hooks_chipset_reset, __hooks_chipset_reset_end},
-	{__hooks_ac_change, __hooks_ac_change_end},
-	{__hooks_lid_change, __hooks_lid_change_end},
-	{__hooks_tablet_mode_change, __hooks_tablet_mode_change_end},
-	{__hooks_base_attached_change, __hooks_base_attached_change_end},
-	{__hooks_pwrbtn_change, __hooks_pwrbtn_change_end},
-	{__hooks_battery_soc_change, __hooks_battery_soc_change_end},
+	{ __hooks_chipset_shutdown, __hooks_chipset_shutdown_end },
+	{ __hooks_chipset_shutdown_complete,
+	  __hooks_chipset_shutdown_complete_end },
+	{ __hooks_chipset_hard_off, __hooks_chipset_hard_off_end },
+	{ __hooks_chipset_reset, __hooks_chipset_reset_end },
+	{ __hooks_ac_change, __hooks_ac_change_end },
+	{ __hooks_lid_change, __hooks_lid_change_end },
+	{ __hooks_tablet_mode_change, __hooks_tablet_mode_change_end },
+	{ __hooks_base_attached_change, __hooks_base_attached_change_end },
+	{ __hooks_pwrbtn_change, __hooks_pwrbtn_change_end },
+	{ __hooks_battery_soc_change, __hooks_battery_soc_change_end },
 #ifdef CONFIG_USB_SUSPEND
-	{__hooks_usb_change, __hooks_usb_change_end},
+	{ __hooks_usb_change, __hooks_usb_change_end },
 #endif
-	{__hooks_tick, __hooks_tick_end},
-	{__hooks_second, __hooks_second_end},
-	{__hooks_usb_pd_disconnect, __hooks_usb_pd_disconnect_end},
-	{__hooks_usb_pd_connect, __hooks_usb_pd_connect_end},
+	{ __hooks_tick, __hooks_tick_end },
+	{ __hooks_second, __hooks_second_end },
+	{ __hooks_usb_pd_disconnect, __hooks_usb_pd_disconnect_end },
+	{ __hooks_usb_pd_connect, __hooks_usb_pd_connect_end },
+	{ __hooks_power_supply_change, __hooks_power_supply_change_end },
 };
 
 /* Times for deferrable functions */
@@ -149,7 +150,7 @@ int hook_call_deferred(const struct deferred_data *data, int us)
 	int i = data - __deferred_funcs;
 
 	if (data < __deferred_funcs || data >= __deferred_funcs_end)
-		return EC_ERROR_INVAL;  /* Routine not registered */
+		return EC_ERROR_INVAL; /* Routine not registered */
 
 	if (us == -1) {
 		/* Cancel */
@@ -195,7 +196,7 @@ void hook_task(void *u)
 				 */
 				__deferred_until[i] = 0;
 				interrupt_enable();
-				CPRINTS("hook call deferred 0x%pP",
+				CPRINTS("hook call deferred 0x%p",
 					__deferred_funcs[i].routine);
 				__deferred_funcs[i].routine();
 				interrupt_disable();
@@ -264,7 +265,7 @@ static void print_hook_delay(uint32_t interval, uint32_t delay, uint32_t avg)
 	ccprintf("  Average:     %7d us (%d%%)\n\n", avg, percent_avg);
 }
 
-static int command_stats(int argc, char **argv)
+static int command_stats(int argc, const char **argv)
 {
 	int i;
 
@@ -283,7 +284,5 @@ static int command_stats(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(hookstats, command_stats,
-			NULL,
-			"Print stats of hooks");
+DECLARE_CONSOLE_COMMAND(hookstats, command_stats, NULL, "Print stats of hooks");
 #endif
diff --git a/common/host_command.c b/common/host_command.c
index e05475ce48..89a835a1aa 100644
--- a/common/host_command.c
+++ b/common/host_command.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,12 +6,14 @@
 /* Host command module for Chrome EC */
 
 #include "ap_hang_detect.h"
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
 #include "ec_commands.h"
 #include "host_command.h"
 #include "link_defs.h"
 #include "lpc.h"
+#include "printf.h"
 #include "shared_mem.h"
 #include "system.h"
 #include "task.h"
@@ -20,8 +22,8 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_HOSTCMD, outstr)
-#define CPRINTF(format, args...) cprintf(CC_HOSTCMD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_HOSTCMD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_HOSTCMD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_HOSTCMD, format, ##args)
 
 #define TASK_EVENT_CMD_PENDING TASK_EVENT_CUSTOM_BIT(0)
 
@@ -42,18 +44,19 @@ static uint8_t host_memmap[EC_MEMMAP_SIZE] __aligned(4);
 #endif
 
 static enum {
-	HCDEBUG_OFF,     /* No host command debug output */
-	HCDEBUG_NORMAL,  /* Normal output mode; skips repeated commands */
-	HCDEBUG_EVERY,   /* Print every command */
-	HCDEBUG_PARAMS,  /* ... and print params for request/response */
+	HCDEBUG_OFF, /* No host command debug output */
+	HCDEBUG_NORMAL, /* Normal output mode; skips repeated commands */
+	HCDEBUG_EVERY, /* Print every command */
+	HCDEBUG_PARAMS, /* ... and print params for request/response */
 
 	/* Number of host command debug modes */
 	HCDEBUG_MODES
 } hcdebug = CONFIG_HOSTCMD_DEBUG_MODE;
 
 #ifdef CONFIG_CMD_HCDEBUG
-static const char * const hcdebug_mode_names[HCDEBUG_MODES] = {
-	"off", "normal", "every", "params"};
+static const char *const hcdebug_mode_names[HCDEBUG_MODES] = { "off", "normal",
+							       "every",
+							       "params" };
 #endif
 
 #ifdef CONFIG_HOST_COMMAND_STATUS
@@ -343,8 +346,8 @@ void host_packet_receive(struct host_packet *pkt)
 	args0.version = r->command_version;
 	args0.params_size = r->data_len;
 	args0.response = (struct ec_host_response *)(pkt->response) + 1;
-	args0.response_max = pkt->response_max -
-		sizeof(struct ec_host_response);
+	args0.response_max =
+		pkt->response_max - sizeof(struct ec_host_response);
 	args0.response_size = 0;
 	args0.result = EC_RES_SUCCESS;
 
@@ -440,7 +443,7 @@ void host_command_task(void *u)
 		/* Process it */
 		if ((evt & TASK_EVENT_CMD_PENDING) && pending_args) {
 			pending_args->result =
-					host_command_process(pending_args);
+				host_command_process(pending_args);
 			host_send_response(pending_args);
 		}
 
@@ -473,8 +476,7 @@ host_command_proto_version(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_PROTO_VERSION,
-		     host_command_proto_version,
+DECLARE_HOST_COMMAND(EC_CMD_PROTO_VERSION, host_command_proto_version,
 		     EC_VER_MASK(0));
 
 static enum ec_status host_command_hello(struct host_cmd_handler_args *args)
@@ -488,9 +490,7 @@ static enum ec_status host_command_hello(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_HELLO,
-		     host_command_hello,
-		     EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_HELLO, host_command_hello, EC_VER_MASK(0));
 
 static enum ec_status host_command_read_test(struct host_cmd_handler_args *args)
 {
@@ -511,9 +511,7 @@ static enum ec_status host_command_read_test(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_READ_TEST,
-		     host_command_read_test,
-		     EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_READ_TEST, host_command_read_test, EC_VER_MASK(0));
 
 #ifndef CONFIG_HOSTCMD_X86
 /*
@@ -543,8 +541,7 @@ host_command_read_memmap(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_READ_MEMMAP,
-		     host_command_read_memmap,
+DECLARE_HOST_COMMAND(EC_CMD_READ_MEMMAP, host_command_read_memmap,
 		     EC_VER_MASK(0));
 #endif
 
@@ -555,9 +552,9 @@ host_command_get_cmd_versions(struct host_cmd_handler_args *args)
 	const struct ec_params_get_cmd_versions_v1 *p_v1 = args->params;
 	struct ec_response_get_cmd_versions *r = args->response;
 
-	const struct host_command *cmd =
-		(args->version == 1) ? find_host_command(p_v1->cmd) :
-				       find_host_command(p->cmd);
+	const struct host_command *cmd = (args->version == 1) ?
+						 find_host_command(p_v1->cmd) :
+						 find_host_command(p->cmd);
 
 	if (!cmd)
 		return EC_RES_INVALID_PARAM;
@@ -568,8 +565,7 @@ host_command_get_cmd_versions(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_GET_CMD_VERSIONS,
-		     host_command_get_cmd_versions,
+DECLARE_HOST_COMMAND(EC_CMD_GET_CMD_VERSIONS, host_command_get_cmd_versions,
 		     EC_VER_MASK(0) | EC_VER_MASK(1));
 
 static int host_command_is_suppressed(uint16_t cmd)
@@ -594,11 +590,13 @@ static void dump_host_command_suppressed(int force)
 {
 #ifdef CONFIG_SUPPRESSED_HOST_COMMANDS
 	int i;
+	char ts_str[PRINTF_TIMESTAMP_BUF_SIZE];
 
 	if (!force && !timestamp_expired(suppressed_cmd_deadline, NULL))
 		return;
 
-	CPRINTF("[%pT HC Suppressed:", PRINTF_TIMESTAMP_NOW);
+	snprintf_timestamp_now(ts_str, sizeof(ts_str));
+	CPRINTF("[%s HC Suppressed:", ts_str);
 	for (i = 0; i < ARRAY_SIZE(hc_suppressed_cmd); i++) {
 		CPRINTF(" 0x%x=%d", hc_suppressed_cmd[i], hc_suppressed_cnt[i]);
 		hc_suppressed_cnt[i] = 0;
@@ -614,10 +612,9 @@ static void dump_host_command_suppressed_(void)
 {
 	dump_host_command_suppressed(1);
 }
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN,
-	     dump_host_command_suppressed_, HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_SYSJUMP,
-	     dump_host_command_suppressed_, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, dump_host_command_suppressed_,
+	     HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_SYSJUMP, dump_host_command_suppressed_, HOOK_PRIO_DEFAULT);
 #else
 }
 #endif /* CONFIG_SUPPRESSED_HOST_COMMANDS */
@@ -659,11 +656,14 @@ static void host_command_debug_request(struct host_cmd_handler_args *args)
 		hc_prev_cmd = args->command;
 	}
 
-	if (hcdebug >= HCDEBUG_PARAMS && args->params_size)
-		CPRINTS("HC 0x%04x.%d:%ph", args->command,
-			args->version,
-			HEX_BUF(args->params, args->params_size));
-	else
+	if (hcdebug >= HCDEBUG_PARAMS && args->params_size) {
+		char str_buf[hex_str_buf_size(args->params_size)];
+
+		snprintf_hex_buffer(str_buf, sizeof(str_buf),
+				    HEX_BUF(args->params, args->params_size));
+		CPRINTS("HC 0x%04x.%d:%s", args->command, args->version,
+			str_buf);
+	} else
 		CPRINTS("HC 0x%04x", args->command);
 }
 
@@ -693,9 +693,9 @@ uint16_t host_command_process(struct host_cmd_handler_args *args)
 	if (args->command >= EC_CMD_PASSTHRU_OFFSET(1) &&
 	    args->command <= EC_CMD_PASSTHRU_MAX(1)) {
 		rv = pd_host_command(args->command - EC_CMD_PASSTHRU_OFFSET(1),
-				     args->version,
-				     args->params, args->params_size,
-				     args->response, args->response_max);
+				     args->version, args->params,
+				     args->params_size, args->response,
+				     args->response_max);
 		if (rv >= 0) {
 			/* Success; store actual response size */
 			args->response_size = rv;
@@ -719,9 +719,14 @@ uint16_t host_command_process(struct host_cmd_handler_args *args)
 	if (rv != EC_RES_SUCCESS)
 		CPRINTS("HC 0x%04x err %d", args->command, rv);
 
-	if (hcdebug >= HCDEBUG_PARAMS && args->response_size)
-		CPRINTS("HC resp:%ph",
-			HEX_BUF(args->response, args->response_size));
+	if (hcdebug >= HCDEBUG_PARAMS && args->response_size) {
+		char str_buf[hex_str_buf_size(args->response_size)];
+
+		snprintf_hex_buffer(str_buf, sizeof(str_buf),
+				    HEX_BUF(args->response,
+					    args->response_size));
+		CPRINTS("HC resp:%s", str_buf);
+	}
 
 	return rv;
 }
@@ -739,8 +744,7 @@ host_command_get_comms_status(struct host_cmd_handler_args *args)
 	return EC_RES_SUCCESS;
 }
 
-DECLARE_HOST_COMMAND(EC_CMD_GET_COMMS_STATUS,
-		     host_command_get_comms_status,
+DECLARE_HOST_COMMAND(EC_CMD_GET_COMMS_STATUS, host_command_get_comms_status,
 		     EC_VER_MASK(0));
 
 /* Resend the last saved response */
@@ -756,8 +760,7 @@ host_command_resend_response(struct host_cmd_handler_args *args)
 	return EC_RES_SUCCESS;
 }
 
-DECLARE_HOST_COMMAND(EC_CMD_RESEND_RESPONSE,
-		     host_command_resend_response,
+DECLARE_HOST_COMMAND(EC_CMD_RESEND_RESPONSE, host_command_resend_response,
 		     EC_VER_MASK(0));
 #endif /* CONFIG_HOST_COMMAND_STATUS */
 
@@ -775,8 +778,7 @@ host_command_test_protocol(struct host_cmd_handler_args *args)
 
 	return p->ec_result;
 }
-DECLARE_HOST_COMMAND(EC_CMD_TEST_PROTOCOL,
-		     host_command_test_protocol,
+DECLARE_HOST_COMMAND(EC_CMD_TEST_PROTOCOL, host_command_test_protocol,
 		     EC_VER_MASK(0));
 
 /* Returns supported features. */
@@ -791,16 +793,14 @@ host_command_get_features(struct host_cmd_handler_args *args)
 	r->flags[1] = get_feature_flags1();
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_GET_FEATURES,
-		     host_command_get_features,
+DECLARE_HOST_COMMAND(EC_CMD_GET_FEATURES, host_command_get_features,
 		     EC_VER_MASK(0));
 
-
 /*****************************************************************************/
 /* Console commands */
 
 #ifdef CONFIG_CMD_HOSTCMD
-static int parse_byte(char *b, uint8_t *out)
+static int parse_byte(const char *b, uint8_t *out)
 {
 	int i;
 	*out = 0;
@@ -819,7 +819,7 @@ static int parse_byte(char *b, uint8_t *out)
 	return EC_SUCCESS;
 }
 
-static int parse_params(char *s, uint8_t *params)
+static int parse_params(const char *s, uint8_t *params)
 {
 	int len = 0;
 
@@ -833,7 +833,7 @@ static int parse_params(char *s, uint8_t *params)
 	return len;
 }
 
-static int command_host_command(int argc, char **argv)
+static int command_host_command(int argc, const char **argv)
 {
 	struct host_cmd_handler_args args;
 	char *cmd_params;
@@ -888,23 +888,27 @@ static int command_host_command(int argc, char **argv)
 
 	if (res != EC_RES_SUCCESS)
 		ccprintf("Command returned %d\n", res);
-	else if (args.response_size)
-		ccprintf("Response: %ph\n",
-			 HEX_BUF(cmd_params, args.response_size));
-	else
+	else if (args.response_size) {
+		char str_buf[hex_str_buf_size(args.response_size)];
+
+		snprintf_hex_buffer(str_buf, sizeof(str_buf),
+				    HEX_BUF(cmd_params, args.response_size));
+		ccprintf("Response: %s\n", str_buf);
+	} else
 		ccprintf("Command succeeded; no response.\n");
 
 	shared_mem_release(cmd_params);
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(hostcmd, command_host_command,
-			"cmd ver param",
+DECLARE_CONSOLE_COMMAND(hostcmd, command_host_command, "cmd ver param",
 			"Fake host command");
 #endif /* CONFIG_CMD_HOSTCMD */
 
 #ifdef CONFIG_CMD_HCDEBUG
-static int command_hcdebug(int argc, char **argv)
+static int command_hcdebug(int argc, const char **argv)
 {
+	if (argc >= 3)
+		return EC_ERROR_PARAM_COUNT;
 	if (argc > 1) {
 		int i;
 
diff --git a/common/host_command_controller.c b/common/host_command_controller.c
index eb35622ab3..83d4ce0c86 100644
--- a/common/host_command_controller.c
+++ b/common/host_command_controller.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,8 +16,8 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_HOSTCMD, outstr)
-#define CPRINTS(format, args...) cprints(CC_HOSTCMD, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_HOSTCMD, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_HOSTCMD, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_HOSTCMD, format, ##args)
 
 /* Number of attempts for each PD host command */
 #define PD_HOST_COMMAND_ATTEMPTS 3
@@ -81,8 +81,7 @@ static int pd_host_command_internal(int command, int version,
 	 */
 	i2c_lock(I2C_PORT_PD_MCU, 1);
 	i2c_set_timeout(I2C_PORT_PD_MCU, PD_HOST_COMMAND_TIMEOUT_US);
-	ret = i2c_xfer_unlocked(I2C_PORT_PD_MCU,
-				CONFIG_USB_PD_I2C_ADDR_FLAGS,
+	ret = i2c_xfer_unlocked(I2C_PORT_PD_MCU, CONFIG_USB_PD_I2C_ADDR_FLAGS,
 				&req_buf[0], outsize + sizeof(rq) + 1,
 				&resp_buf[0], 2, I2C_XFER_START);
 	i2c_set_timeout(I2C_PORT_PD_MCU, 0);
@@ -96,20 +95,17 @@ static int pd_host_command_internal(int command, int version,
 
 	if (resp_len > (insize + sizeof(rs))) {
 		/* Do a read to generate stop condition */
-		i2c_xfer_unlocked(I2C_PORT_PD_MCU,
-				  CONFIG_USB_PD_I2C_ADDR_FLAGS,
+		i2c_xfer_unlocked(I2C_PORT_PD_MCU, CONFIG_USB_PD_I2C_ADDR_FLAGS,
 				  0, 0, &resp_buf[2], 1, I2C_XFER_STOP);
 		i2c_lock(I2C_PORT_PD_MCU, 0);
-		CPRINTS("response size is too large %d > %d",
-			resp_len, insize + sizeof(rs));
+		CPRINTS("response size is too large %d > %d", resp_len,
+			insize + sizeof(rs));
 		return -EC_RES_RESPONSE_TOO_BIG;
 	}
 
 	/* Receive remaining data */
-	ret = i2c_xfer_unlocked(I2C_PORT_PD_MCU,
-				CONFIG_USB_PD_I2C_ADDR_FLAGS,
-				0, 0,
-				&resp_buf[2], resp_len, I2C_XFER_STOP);
+	ret = i2c_xfer_unlocked(I2C_PORT_PD_MCU, CONFIG_USB_PD_I2C_ADDR_FLAGS,
+				0, 0, &resp_buf[2], resp_len, I2C_XFER_STOP);
 	i2c_lock(I2C_PORT_PD_MCU, 0);
 	if (ret) {
 		CPRINTS("i2c transaction 2 failed: %d", ret);
@@ -152,10 +148,9 @@ static int pd_host_command_internal(int command, int version,
 		sum += *d;
 	}
 
-
 	if ((uint8_t)sum) {
-		CPRINTS("command 0x%04x bad checksum returned: %d",
-			command, sum);
+		CPRINTS("command 0x%04x bad checksum returned: %d", command,
+			sum);
 		return -EC_RES_INVALID_CHECKSUM;
 	}
 
@@ -163,8 +158,7 @@ static int pd_host_command_internal(int command, int version,
 	return resp_len;
 }
 
-int pd_host_command(int command, int version,
-		    const void *outdata, int outsize,
+int pd_host_command(int command, int version, const void *outdata, int outsize,
 		    void *indata, int insize)
 {
 	int rv;
@@ -183,13 +177,13 @@ int pd_host_command(int command, int version,
 		/* If host command error due to i2c bus error, try again. */
 		if (rv != -EC_RES_BUS_ERROR)
 			break;
-		task_wait_event(50*MSEC);
+		task_wait_event(50 * MSEC);
 	}
 
 	return rv;
 }
 
-static int command_pd_mcu(int argc, char **argv)
+static int command_pd_mcu(int argc, const char **argv)
 {
 	char *e;
 	static char outbuf[128];
@@ -212,11 +206,11 @@ static int command_pd_mcu(int argc, char **argv)
 		tmp = strtoi(argv[i], &e, 0);
 		if (*e)
 			return EC_ERROR_PARAM3;
-		outbuf[i-3] = tmp;
+		outbuf[i - 3] = tmp;
 	}
 
 	ret = pd_host_command(command, version, &outbuf, argc - 3, &inbuf,
-			sizeof(inbuf));
+			      sizeof(inbuf));
 
 	ccprintf("Host command 0x%02x, returned %d\n", command, ret);
 	for (i = 0; i < ret; i++)
@@ -224,6 +218,5 @@ static int command_pd_mcu(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(pdcmd, command_pd_mcu,
-			"cmd ver [params]",
+DECLARE_CONSOLE_COMMAND(pdcmd, command_pd_mcu, "cmd ver [params]",
 			"Send PD host command");
diff --git a/common/host_command_pd.c b/common/host_command_pd.c
index 7d82249d21..23e2710695 100644
--- a/common/host_command_pd.c
+++ b/common/host_command_pd.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,10 +20,10 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_PD_HOST_CMD, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_PD_HOST_CMD, format, ##args)
 
-#define TASK_EVENT_EXCHANGE_PD_STATUS  TASK_EVENT_CUSTOM_BIT(0)
-#define TASK_EVENT_HIBERNATING         TASK_EVENT_CUSTOM_BIT(1)
+#define TASK_EVENT_EXCHANGE_PD_STATUS TASK_EVENT_CUSTOM_BIT(0)
+#define TASK_EVENT_HIBERNATING TASK_EVENT_CUSTOM_BIT(1)
 
 /* Define local option for if we are a TCPM with an off chip TCPC */
 #if defined(CONFIG_USB_POWER_DELIVERY) && !defined(CONFIG_USB_PD_TCPM_STUB)
@@ -61,7 +61,7 @@ void host_command_pd_request_hibernate(void)
 
 #ifdef CONFIG_HOSTCMD_PD
 static int pd_send_host_command(struct ec_params_pd_status *ec_status,
-	struct ec_response_pd_status *pd_status)
+				struct ec_response_pd_status *pd_status)
 {
 	return pd_host_command(EC_CMD_PD_EXCHANGE_STATUS,
 			       EC_VER_PD_EXCHANGE_STATUS, ec_status,
@@ -126,8 +126,8 @@ static void pd_check_chg_status(struct ec_response_pd_status *pd_status)
 #endif
 
 	/* Set input current limit */
-	rv = charge_set_input_current_limit(MAX(pd_status->curr_lim_ma,
-					CONFIG_CHARGER_INPUT_CURRENT), 0);
+	rv = charge_set_input_current_limit(
+		MAX(pd_status->curr_lim_ma, CONFIG_CHARGER_INPUT_CURRENT), 0);
 	if (rv < 0)
 		CPRINTS("Failed to set input curr limit from PD MCU");
 }
@@ -201,7 +201,7 @@ static void pd_exchange_status(uint32_t ec_state)
 
 		if (!first_exchange)
 			/* Delay to prevent task starvation */
-			usleep(5*MSEC);
+			usleep(5 * MSEC);
 		first_exchange = 0;
 	} while (pd_get_alert());
 #endif /* USB_TCPM_WITH_OFF_CHIP_TCPC */
diff --git a/common/host_event_commands.c b/common/host_event_commands.c
index 177e7cb877..58bca7073e 100644
--- a/common/host_event_commands.c
+++ b/common/host_event_commands.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,13 +19,13 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_EVENTS, outstr)
-#define CPRINTS(format, args...) cprints(CC_EVENTS, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_EVENTS, format, ##args)
 
 /*
  * This is used to avoid 64-bit shifts which might require a new library
  * function.
  */
-#define HOST_EVENT_32BIT_MASK(x)	(1UL << ((x) - 1))
+#define HOST_EVENT_32BIT_MASK(x) (1UL << ((x)-1))
 static void host_event_set_bit(host_event_t *ev, uint8_t bit)
 {
 	uint32_t *ptr = (uint32_t *)ev;
@@ -49,7 +49,7 @@ static void host_event_set_bit(host_event_t *ev, uint8_t bit)
 
 #ifdef CONFIG_HOSTCMD_X86
 
-#define LPC_SYSJUMP_TAG 0x4c50  /* "LP" */
+#define LPC_SYSJUMP_TAG 0x4c50 /* "LP" */
 #define LPC_SYSJUMP_OLD_VERSION 1
 #define LPC_SYSJUMP_VERSION 2
 
@@ -72,14 +72,14 @@ static void host_event_set_bit(host_event_t *ev, uint8_t bit)
  *   - EC_HOST_EVENT_MKBP
  *
  */
-#define LPC_HOST_EVENT_ALWAYS_REPORT_DEFAULT_MASK			\
-	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY) |		\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |		\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |		\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_REBOOT) |		\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC) |			\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_FASTBOOT) |		\
-	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |			\
+#define LPC_HOST_EVENT_ALWAYS_REPORT_DEFAULT_MASK              \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |  \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |  \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_REBOOT) |       \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC) |             \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_FASTBOOT) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |              \
 	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT))
 
 static host_event_t lpc_host_events;
@@ -114,7 +114,7 @@ static host_event_t lpc_get_all_host_event_masks(void)
 	return or_mask;
 }
 
-static void lpc_set_host_event_state(host_event_t events)
+test_export_static void lpc_set_host_event_state(host_event_t events)
 {
 	if (events == lpc_host_events)
 		return;
@@ -136,7 +136,7 @@ host_event_t lpc_get_host_events(void)
 int lpc_get_next_host_event(void)
 {
 	host_event_t ev;
-	int evt_idx =  __builtin_ffs(lpc_host_events);
+	int evt_idx = __builtin_ffs(lpc_host_events);
 
 #ifdef CONFIG_HOST_EVENT64
 	if (evt_idx == 0) {
@@ -175,7 +175,7 @@ static int lpc_post_sysjump_restore_mask(void)
 	int size, version;
 
 	prev_mask = (const host_event_t *)system_get_jump_tag(LPC_SYSJUMP_TAG,
-			&version, &size);
+							      &version, &size);
 	if (!prev_mask || size != sizeof(lpc_host_event_mask) ||
 	    (version != LPC_SYSJUMP_VERSION &&
 	     version != LPC_SYSJUMP_OLD_VERSION))
@@ -332,7 +332,7 @@ void host_set_events(host_event_t mask)
 	HOST_EVENT_CPRINTS("event set", mask);
 
 	if (!IS_ENABLED(CONFIG_ZTEST) &&
-		(mask & EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)))
+	    (mask & EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)))
 		system_enter_manual_recovery();
 
 	host_events_atomic_or(&events, mask);
@@ -347,8 +347,8 @@ void host_set_events(host_event_t mask)
 #error "Config error: MKBP must not be on top of host event"
 #endif
 	host_events_send_mkbp_event(events);
-#endif  /* CONFIG_MKBP_EVENT */
-#endif  /* !CONFIG_HOSTCMD_X86 */
+#endif /* CONFIG_MKBP_EVENT */
+#endif /* !CONFIG_HOSTCMD_X86 */
 }
 
 void host_set_single_event(enum host_event_code event)
@@ -391,7 +391,7 @@ void host_clear_events(host_event_t mask)
 #ifdef CONFIG_MKBP_EVENT
 	host_events_send_mkbp_event(events);
 #endif
-#endif  /* !CONFIG_HOSTCMD_X86 */
+#endif /* !CONFIG_HOSTCMD_X86 */
 }
 
 #ifndef CONFIG_HOSTCMD_X86
@@ -459,7 +459,7 @@ DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, clear_events_copy_b, HOOK_PRIO_DEFAULT);
 
 /*****************************************************************************/
 /* Console commands */
-static int command_host_event(int argc, char **argv)
+static int command_host_event(int argc, const char **argv)
 {
 	/* Handle sub-commands */
 	if (argc == 3) {
@@ -494,19 +494,21 @@ static int command_host_event(int argc, char **argv)
 	HOST_EVENT_CCPRINTF("Events-B:           ", events_copy_b);
 #ifdef CONFIG_HOSTCMD_X86
 	HOST_EVENT_CCPRINTF("SMI mask:           ",
-		 lpc_get_host_event_mask(LPC_HOST_EVENT_SMI));
+			    lpc_get_host_event_mask(LPC_HOST_EVENT_SMI));
 	HOST_EVENT_CCPRINTF("SCI mask:           ",
-		 lpc_get_host_event_mask(LPC_HOST_EVENT_SCI));
+			    lpc_get_host_event_mask(LPC_HOST_EVENT_SCI));
 	HOST_EVENT_CCPRINTF("Wake mask:          ",
-		 lpc_get_host_event_mask(LPC_HOST_EVENT_WAKE));
-	HOST_EVENT_CCPRINTF("Always report mask: ",
-		 lpc_get_host_event_mask(LPC_HOST_EVENT_ALWAYS_REPORT));
+			    lpc_get_host_event_mask(LPC_HOST_EVENT_WAKE));
+	HOST_EVENT_CCPRINTF(
+		"Always report mask: ",
+		lpc_get_host_event_mask(LPC_HOST_EVENT_ALWAYS_REPORT));
 #endif
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(hostevent, command_host_event,
-			"[set | clear | clearb | smi | sci | wake | always_report] [mask]",
-			"Print / set host event state");
+DECLARE_CONSOLE_COMMAND(
+	hostevent, command_host_event,
+	"[set | clear | clearb | smi | sci | wake | always_report] [mask]",
+	"Print / set host event state");
 
 /*****************************************************************************/
 /* Host commands */
@@ -523,8 +525,7 @@ host_event_get_smi_mask(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_GET_SMI_MASK,
-		     host_event_get_smi_mask,
+DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_GET_SMI_MASK, host_event_get_smi_mask,
 		     EC_VER_MASK(0));
 
 static enum ec_status
@@ -537,8 +538,7 @@ host_event_get_sci_mask(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_GET_SCI_MASK,
-		     host_event_get_sci_mask,
+DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_GET_SCI_MASK, host_event_get_sci_mask,
 		     EC_VER_MASK(0));
 
 static enum ec_status
@@ -551,8 +551,7 @@ host_event_get_wake_mask(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_GET_WAKE_MASK,
-		     host_event_get_wake_mask,
+DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_GET_WAKE_MASK, host_event_get_wake_mask,
 		     EC_VER_MASK(0));
 
 static enum ec_status
@@ -563,8 +562,7 @@ host_event_set_smi_mask(struct host_cmd_handler_args *args)
 	lpc_set_host_event_mask(LPC_HOST_EVENT_SMI, p->mask);
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_SET_SMI_MASK,
-		     host_event_set_smi_mask,
+DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_SET_SMI_MASK, host_event_set_smi_mask,
 		     EC_VER_MASK(0));
 
 static enum ec_status
@@ -575,8 +573,7 @@ host_event_set_sci_mask(struct host_cmd_handler_args *args)
 	lpc_set_host_event_mask(LPC_HOST_EVENT_SCI, p->mask);
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_SET_SCI_MASK,
-		     host_event_set_sci_mask,
+DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_SET_SCI_MASK, host_event_set_sci_mask,
 		     EC_VER_MASK(0));
 
 static enum ec_status
@@ -588,8 +585,7 @@ host_event_set_wake_mask(struct host_cmd_handler_args *args)
 	active_wm_set_by_host = !!p->mask;
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_SET_WAKE_MASK,
-		     host_event_set_wake_mask,
+DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_SET_WAKE_MASK, host_event_set_wake_mask,
 		     EC_VER_MASK(0));
 
 uint8_t lpc_is_active_wm_set_by_host(void)
@@ -597,7 +593,7 @@ uint8_t lpc_is_active_wm_set_by_host(void)
 	return active_wm_set_by_host;
 }
 
-#endif  /* CONFIG_HOSTCMD_X86 */
+#endif /* CONFIG_HOSTCMD_X86 */
 
 static enum ec_status host_event_get_b(struct host_cmd_handler_args *args)
 {
@@ -608,9 +604,7 @@ static enum ec_status host_event_get_b(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_GET_B,
-		     host_event_get_b,
-		     EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_GET_B, host_event_get_b, EC_VER_MASK(0));
 
 static enum ec_status host_event_clear(struct host_cmd_handler_args *args)
 {
@@ -619,9 +613,7 @@ static enum ec_status host_event_clear(struct host_cmd_handler_args *args)
 	host_clear_events(p->mask);
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_CLEAR,
-		     host_event_clear,
-		     EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_CLEAR, host_event_clear, EC_VER_MASK(0));
 
 static enum ec_status host_event_clear_b(struct host_cmd_handler_args *args)
 {
@@ -630,8 +622,7 @@ static enum ec_status host_event_clear_b(struct host_cmd_handler_args *args)
 	host_clear_events_b(p->mask);
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_CLEAR_B,
-		     host_event_clear_b,
+DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_CLEAR_B, host_event_clear_b,
 		     EC_VER_MASK(0));
 
 static enum ec_status host_event_action_get(struct host_cmd_handler_args *args)
@@ -658,8 +649,8 @@ static enum ec_status host_event_action_get(struct host_cmd_handler_args *args)
 		r->value = lpc_get_host_event_mask(LPC_HOST_EVENT_SMI);
 		break;
 	case EC_HOST_EVENT_ALWAYS_REPORT_MASK:
-		r->value = lpc_get_host_event_mask
-				(LPC_HOST_EVENT_ALWAYS_REPORT);
+		r->value =
+			lpc_get_host_event_mask(LPC_HOST_EVENT_ALWAYS_REPORT);
 		break;
 	case EC_HOST_EVENT_ACTIVE_WAKE_MASK:
 		r->value = lpc_get_host_event_mask(LPC_HOST_EVENT_WAKE);
@@ -704,7 +695,7 @@ static enum ec_status host_event_action_set(struct host_cmd_handler_args *args)
 		break;
 	case EC_HOST_EVENT_ALWAYS_REPORT_MASK:
 		lpc_set_host_event_mask(LPC_HOST_EVENT_ALWAYS_REPORT,
-						mask_value);
+					mask_value);
 		break;
 	case EC_HOST_EVENT_ACTIVE_WAKE_MASK:
 		active_wm_set_by_host = !!mask_value;
@@ -783,12 +774,11 @@ host_command_host_event(struct host_cmd_handler_args *args)
 	}
 }
 
-DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT,
-		     host_command_host_event,
+DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT, host_command_host_event,
 		     EC_VER_MASK(0));
 
-#define LAZY_WAKE_MASK_SYSJUMP_TAG		0x4C4D /* LM - Lazy Mask*/
-#define LAZY_WAKE_MASK_HOOK_VERSION		1
+#define LAZY_WAKE_MASK_SYSJUMP_TAG 0x4C4D /* LM - Lazy Mask*/
+#define LAZY_WAKE_MASK_HOOK_VERSION 1
 
 #ifdef CONFIG_HOSTCMD_X86
 int get_lazy_wake_mask(enum power_state state, host_event_t *mask)
@@ -818,8 +808,7 @@ int get_lazy_wake_mask(enum power_state state, host_event_t *mask)
 static void preserve_lazy_wm(void)
 {
 	system_add_jump_tag(LAZY_WAKE_MASK_SYSJUMP_TAG,
-			    LAZY_WAKE_MASK_HOOK_VERSION,
-			    sizeof(lazy_wm),
+			    LAZY_WAKE_MASK_HOOK_VERSION, sizeof(lazy_wm),
 			    &lazy_wm);
 }
 DECLARE_HOOK(HOOK_SYSJUMP, preserve_lazy_wm, HOOK_PRIO_DEFAULT);
@@ -829,9 +818,8 @@ static void restore_lazy_wm(void)
 	const struct lazy_wake_masks *wm_state;
 	int version, size;
 
-	wm_state = (const struct lazy_wake_masks *)
-			system_get_jump_tag(LAZY_WAKE_MASK_SYSJUMP_TAG,
-				 &version, &size);
+	wm_state = (const struct lazy_wake_masks *)system_get_jump_tag(
+		LAZY_WAKE_MASK_SYSJUMP_TAG, &version, &size);
 
 	if (wm_state && (version == LAZY_WAKE_MASK_HOOK_VERSION) &&
 	    (size == sizeof(lazy_wm))) {
diff --git a/common/hotword_dsp_api.c b/common/hotword_dsp_api.c
index dc53cd0055..24291df8c0 100644
--- a/common/hotword_dsp_api.c
+++ b/common/hotword_dsp_api.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/common/i2c_bitbang.c b/common/i2c_bitbang.c
index 99868b2dc6..01d4f5f31e 100644
--- a/common/i2c_bitbang.c
+++ b/common/i2c_bitbang.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,7 +11,7 @@
 #include "util.h"
 
 #define CPUTS(str) cputs(CC_I2C, str)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
 
 static int started;
 
@@ -22,8 +22,8 @@ static void i2c_delay(void)
 }
 
 /* Number of attempts to unwedge each pin. */
-#define UNWEDGE_SCL_ATTEMPTS  10
-#define UNWEDGE_SDA_ATTEMPTS  3
+#define UNWEDGE_SCL_ATTEMPTS 10
+#define UNWEDGE_SDA_ATTEMPTS 3
 
 static void i2c_bitbang_unwedge(const struct i2c_port_t *i2c_port)
 {
@@ -84,7 +84,7 @@ static void i2c_bitbang_unwedge(const struct i2c_port_t *i2c_port)
 
 		/* Check if the bus is unwedged. */
 		if (gpio_get_level(i2c_port->sda) &&
-				gpio_get_level(i2c_port->scl))
+		    gpio_get_level(i2c_port->scl))
 			break;
 	}
 
@@ -263,7 +263,7 @@ static int i2c_write_byte(const struct i2c_port_t *i2c_port, uint8_t byte)
 }
 
 static int i2c_read_byte(const struct i2c_port_t *i2c_port, uint8_t *byte,
-		int nack)
+			 int nack)
 {
 	int i;
 
@@ -281,9 +281,8 @@ static int i2c_read_byte(const struct i2c_port_t *i2c_port, uint8_t *byte,
 }
 
 static int i2c_bitbang_xfer(const struct i2c_port_t *i2c_port,
-		const uint16_t addr_flags,
-		const uint8_t *out, int out_size,
-		uint8_t *in, int in_size, int flags)
+			    const uint16_t addr_flags, const uint8_t *out,
+			    int out_size, uint8_t *in, int in_size, int flags)
 {
 	uint16_t addr_8bit = addr_flags << 1, err = EC_SUCCESS;
 	int i = 0;
@@ -320,7 +319,8 @@ static int i2c_bitbang_xfer(const struct i2c_port_t *i2c_port,
 
 		for (i = 0; i < in_size; i++) {
 			err = i2c_read_byte(i2c_port, &in[i],
-				(flags & I2C_XFER_STOP) && (i == in_size - 1));
+					    (flags & I2C_XFER_STOP) &&
+						    (i == in_size - 1));
 			if (err)
 				goto exit;
 		}
@@ -353,9 +353,7 @@ __overridable void board_pre_task_i2c_peripheral_init(void)
 {
 }
 
-const struct i2c_drv bitbang_drv = {
-	.xfer = &i2c_bitbang_xfer
-};
+const struct i2c_drv bitbang_drv = { .xfer = &i2c_bitbang_xfer };
 
 #ifdef TEST_BUILD
 int bitbang_start_cond(const struct i2c_port_t *i2c_port)
diff --git a/common/i2c_controller.c b/common/i2c_controller.c
index 7a0550a93e..146d582c0d 100644
--- a/common/i2c_controller.c
+++ b/common/i2c_controller.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,6 +6,7 @@
 /* I2C cross-platform code for Chrome EC */
 
 #include "battery.h"
+#include "builtin/assert.h"
 #include "clock.h"
 #include "charge_state.h"
 #include "console.h"
@@ -15,6 +16,7 @@
 #include "i2c.h"
 #include "i2c_bitbang.h"
 #include "i2c_private.h"
+#include "printf.h"
 #include "system.h"
 #include "task.h"
 #include "usb_pd.h"
@@ -29,15 +31,15 @@
 #endif /* CONFIG_ZEPHYR */
 
 /* Delay for bitbanging i2c corresponds roughly to 100kHz. */
-#define I2C_BITBANG_DELAY_US	5
+#define I2C_BITBANG_DELAY_US 5
 
 /* Number of attempts to unwedge each pin. */
-#define UNWEDGE_SCL_ATTEMPTS  10
-#define UNWEDGE_SDA_ATTEMPTS  3
+#define UNWEDGE_SCL_ATTEMPTS 10
+#define UNWEDGE_SDA_ATTEMPTS 3
 
 #define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args)
 
 /* Only chips with multi-port controllers will define I2C_CONTROLLER_COUNT */
 #ifndef I2C_CONTROLLER_COUNT
@@ -48,14 +50,7 @@
 #define I2C_BITBANG_PORT_COUNT 0
 #endif
 
-#ifdef CONFIG_ZEPHYR
-/* I2C_PORT_COUNT is bigger than the real count of used I2C devices, so
- * use a special define for that to save RAM.
- */
-static mutex_t port_mutex[I2C_DEVICE_COUNT + I2C_BITBANG_PORT_COUNT];
-#else
 static mutex_t port_mutex[I2C_CONTROLLER_COUNT + I2C_BITBANG_PORT_COUNT];
-#endif /* CONFIG_ZEPHYR */
 
 /* A bitmap of the controllers which are currently servicing a request. */
 static volatile uint32_t i2c_port_active_list;
@@ -81,7 +76,8 @@ SYS_INIT(init_port_mutex, POST_KERNEL, 50);
  * will incorrectly return true.  However, callers which failed to statically
  * lock the port will fail quickly.
  */
-static int i2c_port_is_locked(int port)
+STATIC_IF_NOT(CONFIG_ZTEST)
+int i2c_port_is_locked(int port)
 {
 #ifdef CONFIG_I2C_MULTI_PORT_CONTROLLER
 	/* Test the controller, not the port */
@@ -91,16 +87,6 @@ static int i2c_port_is_locked(int port)
 	if (port < 0)
 		return 0;
 
-	if (IS_ENABLED(CONFIG_ZEPHYR)) {
-		/*
-		 * For Zephyr: to convert an i2c port enum value to a port
-		 * number in mutex_lock(), this number should be soc's i2c port
-		 * where the i2 device is connected to.
-		 */
-		if (i2c_get_physical_port(port) >= 0)
-			port = i2c_get_physical_port(port);
-	}
-
 	return (i2c_port_active_list >> port) & 1;
 }
 
@@ -134,10 +120,11 @@ const struct i2c_port_t *get_i2c_port(const int port)
 	return NULL;
 }
 
-__maybe_unused static int chip_i2c_xfer_with_notify(
-	const int port, const uint16_t addr_flags,
-	const uint8_t *out, int out_size,
-	uint8_t *in, int in_size, int flags)
+__maybe_unused static int chip_i2c_xfer_with_notify(const int port,
+						    const uint16_t addr_flags,
+						    const uint8_t *out,
+						    int out_size, uint8_t *in,
+						    int in_size, int flags)
 {
 	int ret;
 	uint16_t no_pec_af = addr_flags;
@@ -157,18 +144,18 @@ __maybe_unused static int chip_i2c_xfer_with_notify(
 		no_pec_af &= ~I2C_FLAG_PEC;
 
 	if (i2c_port->drv)
-		ret = i2c_port->drv->xfer(i2c_port, no_pec_af,
-					  out, out_size, in, in_size, flags);
+		ret = i2c_port->drv->xfer(i2c_port, no_pec_af, out, out_size,
+					  in, in_size, flags);
 	else
-		ret = chip_i2c_xfer(port, no_pec_af,
-				    out, out_size, in, in_size, flags);
+		ret = chip_i2c_xfer(port, no_pec_af, out, out_size, in, in_size,
+				    flags);
 
 	if (IS_ENABLED(CONFIG_I2C_XFER_BOARD_CALLBACK))
 		i2c_end_xfer_notify(port, addr_flags);
 
 	if (IS_ENABLED(CONFIG_I2C_DEBUG)) {
-		i2c_trace_notify(port, addr_flags, out, out_size,
-				 in, in_size, ret);
+		i2c_trace_notify(port, addr_flags, out, out_size, in, in_size,
+				 ret);
 	}
 
 	return ret;
@@ -179,16 +166,15 @@ __maybe_unused static int chip_i2c_xfer_with_notify(
  * Internal function that splits transfer into multiple chip_i2c_xfer() calls
  * if in_size or out_size exceeds CONFIG_I2C_CHIP_MAX_TRANSFER_SIZE.
  */
-static int i2c_xfer_no_retry(const int port,
-			     const uint16_t addr_flags,
-			     const uint8_t *out, int out_size,
-			     uint8_t *in, int in_size, int flags)
+static int i2c_xfer_no_retry(const int port, const uint16_t addr_flags,
+			     const uint8_t *out, int out_size, uint8_t *in,
+			     int in_size, int flags)
 {
 	int offset;
 
-	for (offset = 0; offset < out_size; ) {
+	for (offset = 0; offset < out_size;) {
 		int chunk_size = MIN(out_size - offset,
-				CONFIG_I2C_CHIP_MAX_TRANSFER_SIZE);
+				     CONFIG_I2C_CHIP_MAX_TRANSFER_SIZE);
 		int out_flags = 0;
 
 		if (offset == 0)
@@ -197,13 +183,13 @@ static int i2c_xfer_no_retry(const int port,
 			out_flags |= flags & I2C_XFER_STOP;
 
 		RETURN_ERROR(chip_i2c_xfer_with_notify(port, addr_flags,
-				out + offset, chunk_size, NULL, 0,
-				out_flags));
+						       out + offset, chunk_size,
+						       NULL, 0, out_flags));
 		offset += chunk_size;
 	}
-	for (offset = 0; offset < in_size; ) {
+	for (offset = 0; offset < in_size;) {
 		int chunk_size = MIN(in_size - offset,
-				CONFIG_I2C_CHIP_MAX_TRANSFER_SIZE);
+				     CONFIG_I2C_CHIP_MAX_TRANSFER_SIZE);
 		int in_flags = 0;
 
 		if (offset == 0)
@@ -211,18 +197,18 @@ static int i2c_xfer_no_retry(const int port,
 		if (offset + chunk_size == in_size)
 			in_flags |= flags & I2C_XFER_STOP;
 
-		RETURN_ERROR(chip_i2c_xfer_with_notify(port, addr_flags,
-				NULL, 0, in + offset, chunk_size, in_flags));
+		RETURN_ERROR(chip_i2c_xfer_with_notify(port, addr_flags, NULL,
+						       0, in + offset,
+						       chunk_size, in_flags));
 		offset += chunk_size;
 	}
 	return EC_SUCCESS;
 }
 #endif /* CONFIG_I2C_XFER_LARGE_TRANSFER */
 
-int i2c_xfer_unlocked(const int port,
-		      const uint16_t addr_flags,
-		      const uint8_t *out, int out_size,
-		      uint8_t *in, int in_size, int flags)
+int i2c_xfer_unlocked(const int port, const uint16_t addr_flags,
+		      const uint8_t *out, int out_size, uint8_t *in,
+		      int in_size, int flags)
 {
 	int i;
 	int ret = EC_SUCCESS;
@@ -275,14 +261,14 @@ int i2c_xfer_unlocked(const int port,
 		/* Big endian flag is used in wrappers for this call */
 		if (no_pec_af & ~(I2C_ADDR_MASK | I2C_FLAG_BIG_ENDIAN))
 			ccprintf("Ignoring flags from i2c addr_flags: %04x",
-					no_pec_af);
+				 no_pec_af);
 
-		ret =  i2c_transfer(i2c_get_device_for_port(port), msg,
-				    num_msgs, I2C_STRIP_FLAGS(no_pec_af));
+		ret = i2c_transfer(i2c_get_device_for_port(port), msg, num_msgs,
+				   I2C_STRIP_FLAGS(no_pec_af));
 
 		if (IS_ENABLED(CONFIG_I2C_DEBUG)) {
-			i2c_trace_notify(port, addr_flags, out, out_size,
-					 in, in_size, ret);
+			i2c_trace_notify(port, addr_flags, out, out_size, in,
+					 in_size, ret);
 		}
 
 		switch (ret) {
@@ -294,13 +280,11 @@ int i2c_xfer_unlocked(const int port,
 			return EC_ERROR_UNKNOWN;
 		}
 #elif defined(CONFIG_I2C_XFER_LARGE_TRANSFER)
-		ret = i2c_xfer_no_retry(port, no_pec_af,
-					    out, out_size, in,
-					    in_size, flags);
+		ret = i2c_xfer_no_retry(port, no_pec_af, out, out_size, in,
+					in_size, flags);
 #else
-		ret = chip_i2c_xfer_with_notify(port, no_pec_af,
-						    out, out_size,
-						    in, in_size, flags);
+		ret = chip_i2c_xfer_with_notify(port, no_pec_af, out, out_size,
+						in, in_size, flags);
 #endif /* CONFIG_I2C_XFER_LARGE_TRANSFER */
 		if (ret != EC_ERROR_BUSY)
 			break;
@@ -308,16 +292,13 @@ int i2c_xfer_unlocked(const int port,
 	return ret;
 }
 
-int i2c_xfer(const int port,
-	     const uint16_t addr_flags,
-	     const uint8_t *out, int out_size,
-	     uint8_t *in, int in_size)
+int i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out,
+	     int out_size, uint8_t *in, int in_size)
 {
 	int rv;
 
 	i2c_lock(port, 1);
-	rv = i2c_xfer_unlocked(port, addr_flags,
-			       out, out_size, in, in_size,
+	rv = i2c_xfer_unlocked(port, addr_flags, out, out_size, in, in_size,
 			       I2C_XFER_SINGLE);
 	i2c_lock(port, 0);
 
@@ -330,16 +311,6 @@ void i2c_lock(int port, int lock)
 	/* Lock the controller, not the port */
 	port = i2c_port_to_controller(port);
 #endif
-	if (IS_ENABLED(CONFIG_ZEPHYR)) {
-		/*
-		 * For Zephyr: to convert an i2c port enum value to a port
-		 * number in mutex_lock(), this number should be soc's i2c port
-		 * where the i2 device is connected to.
-		 */
-		if (i2c_get_physical_port(port) >= 0)
-			port = i2c_get_physical_port(port);
-	}
-
 	if (port < 0 || port >= ARRAY_SIZE(port_mutex))
 		return;
 
@@ -390,13 +361,13 @@ static int platform_ec_i2c_read(const int port, const uint16_t addr_flags,
 		int i, rv;
 		/* addr_8bit = 7 bit addr_flags + 1 bit r/w */
 		uint8_t addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1;
-		uint8_t out[3] = {addr_8bit, reg, addr_8bit | 1};
+		uint8_t out[3] = { addr_8bit, reg, addr_8bit | 1 };
 		uint8_t pec_local = 0, pec_remote;
 
 		i2c_lock(port, 1);
 		for (i = 0; i <= CONFIG_I2C_NACK_RETRY_COUNT; i++) {
-			rv = i2c_xfer_unlocked(port, addr_flags, &reg, 1,
-					       in, in_size, I2C_XFER_START);
+			rv = i2c_xfer_unlocked(port, addr_flags, &reg, 1, in,
+					       in_size, I2C_XFER_START);
 			if (rv)
 				continue;
 
@@ -421,8 +392,7 @@ static int platform_ec_i2c_read(const int port, const uint16_t addr_flags,
 }
 
 /* i2c_writeN with optional error checking */
-static int platform_ec_i2c_write(const int port,
-				 const uint16_t addr_flags,
+static int platform_ec_i2c_write(const int port, const uint16_t addr_flags,
 				 const uint8_t *out, int out_size)
 {
 	if (!IS_ENABLED(CONFIG_SMBUS_PEC) && I2C_USE_PEC(addr_flags))
@@ -438,15 +408,13 @@ static int platform_ec_i2c_write(const int port,
 
 		i2c_lock(port, 1);
 		for (i = 0; i <= CONFIG_I2C_NACK_RETRY_COUNT; i++) {
-			rv = i2c_xfer_unlocked(port, addr_flags,
-					       out, out_size, NULL, 0,
-					       I2C_XFER_START);
+			rv = i2c_xfer_unlocked(port, addr_flags, out, out_size,
+					       NULL, 0, I2C_XFER_START);
 			if (rv)
 				continue;
 
-			rv = i2c_xfer_unlocked(port, addr_flags,
-					       &pec, 1, NULL, 0,
-					       I2C_XFER_STOP);
+			rv = i2c_xfer_unlocked(port, addr_flags, &pec, 1, NULL,
+					       0, I2C_XFER_STOP);
 			if (!rv)
 				break;
 		}
@@ -458,17 +426,14 @@ static int platform_ec_i2c_write(const int port,
 	return i2c_xfer(port, addr_flags, out, out_size, NULL, 0);
 }
 
-int i2c_read32(const int port,
-	       const uint16_t addr_flags,
-	       int offset, int *data)
+int i2c_read32(const int port, const uint16_t addr_flags, int offset, int *data)
 {
 	int rv;
 	uint8_t reg, buf[sizeof(uint32_t)];
 
 	reg = offset & 0xff;
 	/* I2C read 32-bit word: transmit 8-bit offset, and read 32bits */
-	rv = platform_ec_i2c_read(port, addr_flags, reg, buf,
-				  sizeof(uint32_t));
+	rv = platform_ec_i2c_read(port, addr_flags, reg, buf, sizeof(uint32_t));
 
 	if (rv)
 		return rv;
@@ -483,9 +448,7 @@ int i2c_read32(const int port,
 	return EC_SUCCESS;
 }
 
-int i2c_write32(const int port,
-		const uint16_t addr_flags,
-		int offset, int data)
+int i2c_write32(const int port, const uint16_t addr_flags, int offset, int data)
 {
 	uint8_t buf[1 + sizeof(uint32_t)];
 
@@ -507,17 +470,14 @@ int i2c_write32(const int port,
 				     sizeof(uint32_t) + 1);
 }
 
-int i2c_read16(const int port,
-	       const uint16_t addr_flags,
-	       int offset, int *data)
+int i2c_read16(const int port, const uint16_t addr_flags, int offset, int *data)
 {
 	int rv;
 	uint8_t reg, buf[sizeof(uint16_t)];
 
 	reg = offset & 0xff;
 	/* I2C read 16-bit word: transmit 8-bit offset, and read 16bits */
-	rv = platform_ec_i2c_read(port, addr_flags, reg, buf,
-				  sizeof(uint16_t));
+	rv = platform_ec_i2c_read(port, addr_flags, reg, buf, sizeof(uint16_t));
 
 	if (rv)
 		return rv;
@@ -530,9 +490,7 @@ int i2c_read16(const int port,
 	return EC_SUCCESS;
 }
 
-int i2c_write16(const int port,
-		const uint16_t addr_flags,
-		int offset, int data)
+int i2c_write16(const int port, const uint16_t addr_flags, int offset, int data)
 {
 	uint8_t buf[1 + sizeof(uint16_t)];
 
@@ -550,9 +508,7 @@ int i2c_write16(const int port,
 				     1 + sizeof(uint16_t));
 }
 
-int i2c_read8(const int port,
-	      const uint16_t addr_flags,
-	      int offset, int *data)
+int i2c_read8(const int port, const uint16_t addr_flags, int offset, int *data)
 {
 	int rv;
 	uint8_t reg = offset;
@@ -560,17 +516,14 @@ int i2c_read8(const int port,
 
 	reg = offset;
 
-	rv = platform_ec_i2c_read(port, addr_flags, reg, &buf,
-				  sizeof(uint8_t));
+	rv = platform_ec_i2c_read(port, addr_flags, reg, &buf, sizeof(uint8_t));
 	if (!rv)
 		*data = buf;
 
 	return rv;
 }
 
-int i2c_write8(const int port,
-	       const uint16_t addr_flags,
-	       int offset, int data)
+int i2c_write8(const int port, const uint16_t addr_flags, int offset, int data)
 {
 	uint8_t buf[2];
 
@@ -580,11 +533,8 @@ int i2c_write8(const int port,
 	return platform_ec_i2c_write(port, addr_flags, buf, sizeof(buf));
 }
 
-int i2c_update8(const int port,
-		const uint16_t addr_flags,
-		const int offset,
-		const uint8_t mask,
-		const enum mask_update_action action)
+int i2c_update8(const int port, const uint16_t addr_flags, const int offset,
+		const uint8_t mask, const enum mask_update_action action)
 {
 	int rv;
 	int read_val;
@@ -594,8 +544,8 @@ int i2c_update8(const int port,
 	if (rv)
 		return rv;
 
-	write_val = (action == MASK_SET) ? (read_val | mask)
-					 : (read_val & ~mask);
+	write_val = (action == MASK_SET) ? (read_val | mask) :
+					   (read_val & ~mask);
 
 	if (IS_ENABLED(CONFIG_I2C_UPDATE_IF_CHANGED) && write_val == read_val)
 		return EC_SUCCESS;
@@ -603,11 +553,8 @@ int i2c_update8(const int port,
 	return i2c_write8(port, addr_flags, offset, write_val);
 }
 
-int i2c_update16(const int port,
-		 const uint16_t addr_flags,
-		 const int offset,
-		 const uint16_t mask,
-		 const enum mask_update_action action)
+int i2c_update16(const int port, const uint16_t addr_flags, const int offset,
+		 const uint16_t mask, const enum mask_update_action action)
 {
 	int rv;
 	int read_val;
@@ -617,8 +564,8 @@ int i2c_update16(const int port,
 	if (rv)
 		return rv;
 
-	write_val = (action == MASK_SET) ? (read_val | mask)
-					 : (read_val & ~mask);
+	write_val = (action == MASK_SET) ? (read_val | mask) :
+					   (read_val & ~mask);
 
 	if (IS_ENABLED(CONFIG_I2C_UPDATE_IF_CHANGED) && write_val == read_val)
 		return EC_SUCCESS;
@@ -626,10 +573,8 @@ int i2c_update16(const int port,
 	return i2c_write16(port, addr_flags, offset, write_val);
 }
 
-int i2c_field_update8(const int port,
-		      const uint16_t addr_flags,
-		      const int offset,
-		      const uint8_t field_mask,
+int i2c_field_update8(const int port, const uint16_t addr_flags,
+		      const int offset, const uint8_t field_mask,
 		      const uint8_t set_value)
 {
 	int rv;
@@ -648,10 +593,8 @@ int i2c_field_update8(const int port,
 	return i2c_write8(port, addr_flags, offset, write_val);
 }
 
-int i2c_field_update16(const int port,
-		       const uint16_t addr_flags,
-		       const int offset,
-		       const uint16_t field_mask,
+int i2c_field_update16(const int port, const uint16_t addr_flags,
+		       const int offset, const uint16_t field_mask,
 		       const uint16_t set_value)
 {
 	int rv;
@@ -670,8 +613,7 @@ int i2c_field_update16(const int port,
 	return i2c_write16(port, addr_flags, offset, write_val);
 }
 
-int i2c_read_offset16(const int port,
-		      const uint16_t addr_flags,
+int i2c_read_offset16(const int port, const uint16_t addr_flags,
 		      uint16_t offset, int *data, int len)
 {
 	int rv;
@@ -701,8 +643,7 @@ int i2c_read_offset16(const int port,
 	return EC_SUCCESS;
 }
 
-int i2c_write_offset16(const int port,
-		       const uint16_t addr_flags,
+int i2c_write_offset16(const int port, const uint16_t addr_flags,
 		       uint16_t offset, int data, int len)
 {
 	uint8_t buf[2 + sizeof(uint16_t)];
@@ -728,8 +669,7 @@ int i2c_write_offset16(const int port,
 	return i2c_xfer(port, addr_flags, buf, 2 + len, NULL, 0);
 }
 
-int i2c_read_offset16_block(const int port,
-			    const uint16_t addr_flags,
+int i2c_read_offset16_block(const int port, const uint16_t addr_flags,
 			    uint16_t offset, uint8_t *data, int len)
 {
 	uint8_t addr[sizeof(uint16_t)];
@@ -740,8 +680,7 @@ int i2c_read_offset16_block(const int port,
 	return i2c_xfer(port, addr_flags, addr, 2, data, len);
 }
 
-int i2c_write_offset16_block(const int port,
-			     const uint16_t addr_flags,
+int i2c_write_offset16_block(const int port, const uint16_t addr_flags,
 			     uint16_t offset, const uint8_t *data, int len)
 {
 	int rv;
@@ -758,16 +697,15 @@ int i2c_write_offset16_block(const int port,
 	rv = i2c_xfer_unlocked(port, addr_flags, addr, 2, NULL, 0,
 			       I2C_XFER_START);
 	if (!rv)
-		rv = i2c_xfer_unlocked(port, addr_flags,
-				       data, len, NULL, 0, I2C_XFER_STOP);
+		rv = i2c_xfer_unlocked(port, addr_flags, data, len, NULL, 0,
+				       I2C_XFER_STOP);
 	i2c_lock(port, 0);
 
 	return rv;
 }
 
-int i2c_read_sized_block(const int port,
-			 const uint16_t addr_flags,
-			 int offset, uint8_t *data, int max_len, int *read_len)
+int i2c_read_sized_block(const int port, const uint16_t addr_flags, int offset,
+			 uint8_t *data, int max_len, int *read_len)
 {
 	int i, rv;
 	uint8_t reg, block_length;
@@ -788,9 +726,8 @@ int i2c_read_sized_block(const int port,
 		 * Send device reg space offset, and read back block length.
 		 * Keep this session open without a stop.
 		 */
-		rv = i2c_xfer_unlocked(port, addr_flags,
-				       &reg, 1, &block_length, 1,
-				       I2C_XFER_START);
+		rv = i2c_xfer_unlocked(port, addr_flags, &reg, 1, &block_length,
+				       1, I2C_XFER_START);
 		if (rv)
 			continue;
 
@@ -799,15 +736,13 @@ int i2c_read_sized_block(const int port,
 		else
 			data_length = block_length;
 
-		if (IS_ENABLED(CONFIG_SMBUS_PEC) &&
-				I2C_USE_PEC(addr_flags)) {
-			uint8_t addr_8bit =
-				I2C_STRIP_FLAGS(addr_flags) << 1;
-			uint8_t out[3] = {addr_8bit, reg, addr_8bit | 1};
+		if (IS_ENABLED(CONFIG_SMBUS_PEC) && I2C_USE_PEC(addr_flags)) {
+			uint8_t addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1;
+			uint8_t out[3] = { addr_8bit, reg, addr_8bit | 1 };
 			uint8_t pec, pec_remote;
 
-			rv = i2c_xfer_unlocked(port, addr_flags,
-					       0, 0, data, data_length, 0);
+			rv = i2c_xfer_unlocked(port, addr_flags, 0, 0, data,
+					       data_length, 0);
 			if (rv)
 				continue;
 
@@ -820,8 +755,8 @@ int i2c_read_sized_block(const int port,
 			while (block_length) {
 				uint8_t byte;
 
-				rv = i2c_xfer_unlocked(port, addr_flags,
-						       NULL, 0, &byte, 1, 0);
+				rv = i2c_xfer_unlocked(port, addr_flags, NULL,
+						       0, &byte, 1, 0);
 				if (rv)
 					break;
 				pec = cros_crc8_arg(&byte, 1, pec);
@@ -838,9 +773,8 @@ int i2c_read_sized_block(const int port,
 			if (pec != pec_remote)
 				rv = EC_ERROR_CRC;
 		} else {
-			rv = i2c_xfer_unlocked(port, addr_flags,
-					       0, 0, data, data_length,
-					       I2C_XFER_STOP);
+			rv = i2c_xfer_unlocked(port, addr_flags, 0, 0, data,
+					       data_length, I2C_XFER_STOP);
 			if (rv)
 				continue;
 		}
@@ -854,9 +788,8 @@ int i2c_read_sized_block(const int port,
 	return rv;
 }
 
-int i2c_read_string(const int port,
-		    const uint16_t addr_flags,
-		    int offset, uint8_t *data, int len)
+int i2c_read_string(const int port, const uint16_t addr_flags, int offset,
+		    uint8_t *data, int len)
 {
 	int read_len = 0;
 	int rv = 0;
@@ -865,7 +798,7 @@ int i2c_read_string(const int port,
 		return EC_ERROR_INVAL;
 
 	rv = i2c_read_sized_block(port, addr_flags, offset, data, len - 1,
-				      &read_len);
+				  &read_len);
 	data[read_len] = 0;
 	return rv;
 }
@@ -880,9 +813,8 @@ int i2c_read_block(const int port, const uint16_t addr_flags, int offset,
 	return rv;
 }
 
-int i2c_write_block(const int port,
-		    const uint16_t addr_flags,
-		    int offset, const uint8_t *data, int len)
+int i2c_write_block(const int port, const uint16_t addr_flags, int offset,
+		    const uint8_t *data, int len)
 {
 	int i, rv;
 	uint8_t reg_address = offset, pec = 0;
@@ -903,27 +835,25 @@ int i2c_write_block(const int port,
 	 */
 	i2c_lock(port, 1);
 	for (i = 0; i <= CONFIG_I2C_NACK_RETRY_COUNT; i++) {
-		rv = i2c_xfer_unlocked(port, addr_flags,
-				       &reg_address, 1, NULL, 0,
-				       I2C_XFER_START);
+		rv = i2c_xfer_unlocked(port, addr_flags, &reg_address, 1, NULL,
+				       0, I2C_XFER_START);
 		if (rv)
 			continue;
 
 		if (I2C_USE_PEC(addr_flags)) {
-			rv = i2c_xfer_unlocked(port, addr_flags,
-					       data, len, NULL, 0, 0);
+			rv = i2c_xfer_unlocked(port, addr_flags, data, len,
+					       NULL, 0, 0);
 			if (rv)
 				continue;
 
-			rv = i2c_xfer_unlocked(port, addr_flags,
-					       &pec, sizeof(uint8_t), NULL, 0,
+			rv = i2c_xfer_unlocked(port, addr_flags, &pec,
+					       sizeof(uint8_t), NULL, 0,
 					       I2C_XFER_STOP);
 			if (rv)
 				continue;
 		} else {
-			rv = i2c_xfer_unlocked(port, addr_flags,
-					       data, len, NULL, 0,
-					       I2C_XFER_STOP);
+			rv = i2c_xfer_unlocked(port, addr_flags, data, len,
+					       NULL, 0, I2C_XFER_STOP);
 			if (rv)
 				continue;
 		}
@@ -1022,7 +952,6 @@ int i2c_raw_mode(int port, int enable)
 	return ret_sda == EC_SUCCESS ? ret_scl : ret_sda;
 }
 
-
 /*
  * Unwedge the i2c bus for the given port.
  *
@@ -1083,7 +1012,8 @@ int i2c_unwedge(int port)
 				 * clock low and there is nothing we can do.
 				 */
 				CPRINTS("I2C%d unwedge failed, "
-					"SCL is held low", port);
+					"SCL is held low",
+					port);
 				ret = EC_ERROR_UNKNOWN;
 				goto unwedge_done;
 			}
@@ -1202,8 +1132,8 @@ enum i2c_freq i2c_get_freq(int port)
 /* Host commands */
 
 #ifdef CONFIG_I2C_DEBUG_PASSTHRU
-#define PTHRUPRINTS(format, args...) CPRINTS("I2C_PTHRU " format, ## args)
-#define PTHRUPRINTF(format, args...) CPRINTF(format, ## args)
+#define PTHRUPRINTS(format, args...) CPRINTS("I2C_PTHRU " format, ##args)
+#define PTHRUPRINTF(format, args...) CPRINTF(format, ##args)
 #else
 #define PTHRUPRINTS(format, args...)
 #define PTHRUPRINTF(format, args...)
@@ -1241,7 +1171,7 @@ static int check_i2c_params(const struct host_cmd_handler_args *args)
 	}
 
 #ifdef CONFIG_I2C_PASSTHRU_RESTRICTED
-	out = (uint8_t *) args->params + size;
+	out = (uint8_t *)args->params + size;
 #endif
 
 	/* Loop and process messages */;
@@ -1252,8 +1182,7 @@ static int check_i2c_params(const struct host_cmd_handler_args *args)
 		PTHRUPRINTS("port=%d, %s, addr=0x%x(7-bit), len=%d",
 			    params->port,
 			    addr_flags & EC_I2C_FLAG_READ ? "read" : "write",
-			    addr_flags & EC_I2C_ADDR_MASK,
-			    msg->len);
+			    addr_flags & EC_I2C_ADDR_MASK, msg->len);
 
 		if (addr_flags & EC_I2C_FLAG_READ) {
 			read_len += msg->len;
@@ -1270,8 +1199,7 @@ static int check_i2c_params(const struct host_cmd_handler_args *args)
 				.addr_flags = addr_flags,
 				.cmd = cmd_id,
 			};
-			if (!board_allow_i2c_passthru(
-				&cmd_desc))
+			if (!board_allow_i2c_passthru(&cmd_desc))
 				return EC_RES_ACCESS_DENIED;
 		}
 #endif
@@ -1279,7 +1207,7 @@ static int check_i2c_params(const struct host_cmd_handler_args *args)
 
 	/* Check there is room for the data */
 	if (args->response_max <
-			sizeof(struct ec_response_i2c_passthru) + read_len) {
+	    sizeof(struct ec_response_i2c_passthru) + read_len) {
 		PTHRUPRINTS("overflow1");
 		return EC_RES_INVALID_PARAM;
 	}
@@ -1316,8 +1244,7 @@ static enum ec_status i2c_command_passthru(struct host_cmd_handler_args *args)
 	 */
 	((struct ec_params_i2c_passthru *)(args->params))->port =
 		i2c_get_port_from_remote_port(
-			((struct ec_params_i2c_passthru *)(args->params))
-			->port);
+			((struct ec_params_i2c_passthru *)(args->params))->port);
 #endif
 	const struct ec_params_i2c_passthru *params = args->params;
 	const struct ec_params_i2c_passthru_msg *msg;
@@ -1349,8 +1276,8 @@ static enum ec_status i2c_command_passthru(struct host_cmd_handler_args *args)
 			return EC_RES_ACCESS_DENIED;
 
 		for (i = 0; i < params->num_msgs; i++) {
-			if (!i2c_port->passthru_allowed(i2c_port,
-					params->msg[i].addr_flags))
+			if (!i2c_port->passthru_allowed(
+				    i2c_port, params->msg[i].addr_flags))
 				return EC_RES_ACCESS_DENIED;
 		}
 	}
@@ -1358,12 +1285,11 @@ static enum ec_status i2c_command_passthru(struct host_cmd_handler_args *args)
 	/* Loop and process messages */
 	resp->i2c_status = 0;
 	out = (uint8_t *)args->params + sizeof(*params) +
-		params->num_msgs * sizeof(*msg);
+	      params->num_msgs * sizeof(*msg);
 	in_len = 0;
 
 	for (resp->num_msgs = 0, msg = params->msg;
-	     resp->num_msgs < params->num_msgs;
-	     resp->num_msgs++, msg++) {
+	     resp->num_msgs < params->num_msgs; resp->num_msgs++, msg++) {
 		int xferflags = I2C_XFER_START;
 		int read_len = 0, write_len = 0;
 		int rv = 1;
@@ -1371,7 +1297,6 @@ static enum ec_status i2c_command_passthru(struct host_cmd_handler_args *args)
 		/* Have to remove the EC flags from the address flags */
 		uint16_t addr_flags = msg->addr_flags & EC_I2C_ADDR_MASK;
 
-
 		if (msg->addr_flags & EC_I2C_FLAG_READ)
 			read_len = msg->len;
 		else
@@ -1385,15 +1310,14 @@ static enum ec_status i2c_command_passthru(struct host_cmd_handler_args *args)
 		if (is_i2c_port_virtual_battery(params->port) &&
 		    addr_flags == VIRTUAL_BATTERY_ADDR_FLAGS) {
 			if (virtual_battery_handler(resp, in_len, &rv,
-						xferflags, read_len,
-						write_len, out))
+						    xferflags, read_len,
+						    write_len, out))
 				break;
 		}
 #endif
 		/* Transfer next message */
 		PTHRUPRINTS("xfer port=%x addr=0x%x rlen=%d flags=0x%x",
-			    params->port, addr_flags,
-			    read_len, xferflags);
+			    params->port, addr_flags, read_len, xferflags);
 		if (write_len) {
 			PTHRUPRINTF("  out:");
 			for (i = 0; i < write_len; i++)
@@ -1403,11 +1327,9 @@ static enum ec_status i2c_command_passthru(struct host_cmd_handler_args *args)
 		if (rv) {
 			if (!port_is_locked)
 				i2c_lock(params->port, (port_is_locked = 1));
-			rv = i2c_xfer_unlocked(params->port,
-					       addr_flags,
-					       out, write_len,
-					       &resp->data[in_len], read_len,
-					       xferflags);
+			rv = i2c_xfer_unlocked(params->port, addr_flags, out,
+					       write_len, &resp->data[in_len],
+					       read_len, xferflags);
 		}
 
 		if (rv) {
@@ -1436,6 +1358,11 @@ static enum ec_status i2c_command_passthru(struct host_cmd_handler_args *args)
 }
 DECLARE_HOST_COMMAND(EC_CMD_I2C_PASSTHRU, i2c_command_passthru, EC_VER_MASK(0));
 
+__test_only void i2c_passthru_protect_reset(void)
+{
+	memset(port_protected, 0, sizeof(port_protected));
+}
+
 static void i2c_passthru_protect_port(uint32_t port)
 {
 	if (port < ARRAY_SIZE(port_protected))
@@ -1476,8 +1403,7 @@ i2c_command_passthru_protect(struct host_cmd_handler_args *args)
 	 */
 	((struct ec_params_i2c_passthru_protect *)(args->params))
 		->port = i2c_get_port_from_remote_port(
-		((struct ec_params_i2c_passthru_protect *)(args->params))
-		->port);
+		((struct ec_params_i2c_passthru_protect *)(args->params))->port);
 #endif
 	const struct ec_params_i2c_passthru_protect *params = args->params;
 	struct ec_response_i2c_passthru_protect *resp = args->response;
@@ -1495,7 +1421,7 @@ i2c_command_passthru_protect(struct host_cmd_handler_args *args)
 	 */
 	if (params->subcmd == EC_CMD_I2C_PASSTHRU_PROTECT_ENABLE_TCPCS) {
 		if (IS_ENABLED(CONFIG_USB_POWER_DELIVERY) &&
-				!IS_ENABLED(CONFIG_USB_PD_TCPM_STUB))
+		    !IS_ENABLED(CONFIG_USB_PD_TCPM_STUB))
 			i2c_passthru_protect_tcpc_ports();
 		return EC_RES_SUCCESS;
 	}
@@ -1508,8 +1434,8 @@ i2c_command_passthru_protect(struct host_cmd_handler_args *args)
 	if (params->subcmd == EC_CMD_I2C_PASSTHRU_PROTECT_STATUS) {
 		if (args->response_max < sizeof(*resp)) {
 			PTHRUPRINTS("protect no response, "
-					"response_max=%d, need at least %d",
-					args->response_max, sizeof(*resp));
+				    "response_max=%d, need at least %d",
+				    args->response_max, sizeof(*resp));
 			return EC_RES_INVALID_PARAM;
 		}
 
@@ -1528,8 +1454,7 @@ DECLARE_HOST_COMMAND(EC_CMD_I2C_PASSTHRU_PROTECT, i2c_command_passthru_protect,
 
 #ifdef CONFIG_HOSTCMD_I2C_CONTROL
 
-static enum ec_status
-i2c_command_control(struct host_cmd_handler_args *args)
+static enum ec_status i2c_command_control(struct host_cmd_handler_args *args)
 {
 #ifdef CONFIG_ZEPHYR
 	/* For Zephyr, convert the received remote port number to a port number
@@ -1537,8 +1462,7 @@ i2c_command_control(struct host_cmd_handler_args *args)
 	 */
 	((struct ec_params_i2c_control *)(args->params))->port =
 		i2c_get_port_from_remote_port(
-			((struct ec_params_i2c_control *)(args->params))
-			->port);
+			((struct ec_params_i2c_control *)(args->params))->port);
 #endif
 	const struct ec_params_i2c_control *params = args->params;
 	struct ec_response_i2c_control *resp = args->response;
@@ -1559,7 +1483,7 @@ i2c_command_control(struct host_cmd_handler_args *args)
 		old_i2c_freq = i2c_get_freq(cfg->port);
 		khz = i2c_freq_to_khz(old_i2c_freq);
 		old_i2c_speed_khz = (khz != 0) ? khz :
-			EC_I2C_CONTROL_SPEED_UNKNOWN;
+						 EC_I2C_CONTROL_SPEED_UNKNOWN;
 		break;
 
 	case EC_I2C_CONTROL_SET_SPEED:
@@ -1576,9 +1500,7 @@ i2c_command_control(struct host_cmd_handler_args *args)
 			return EC_RES_ERROR;
 
 		CPRINTS("I2C%d speed changed from %d kHz to %d kHz",
-			params->port,
-			old_i2c_speed_khz,
-			new_i2c_speed_khz);
+			params->port, old_i2c_speed_khz, new_i2c_speed_khz);
 		break;
 
 	default:
@@ -1591,8 +1513,7 @@ i2c_command_control(struct host_cmd_handler_args *args)
 	return EC_RES_SUCCESS;
 }
 
-DECLARE_HOST_COMMAND(EC_CMD_I2C_CONTROL, i2c_command_control,
-		     EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_I2C_CONTROL, i2c_command_control, EC_VER_MASK(0));
 
 #endif /* CONFIG_HOSTCMD_I2C_CONTROL */
 
@@ -1600,7 +1521,7 @@ DECLARE_HOST_COMMAND(EC_CMD_I2C_CONTROL, i2c_command_control,
 /* Console commands */
 
 #ifdef CONFIG_CMD_I2C_PROTECT
-static int command_i2cprotect(int argc, char **argv)
+static int command_i2cprotect(int argc, const char **argv)
 {
 	if (argc == 1) {
 		int i, port;
@@ -1608,7 +1529,8 @@ static int command_i2cprotect(int argc, char **argv)
 		for (i = 0; i < i2c_ports_used; i++) {
 			port = i2c_ports[i].port;
 			ccprintf("Port %d: %s\n", port,
-			   port_protected[port] ? "Protected" : "Unprotected");
+				 port_protected[port] ? "Protected" :
+							"Unprotected");
 		}
 	} else if (argc == 2) {
 		int port;
@@ -1620,7 +1542,7 @@ static int command_i2cprotect(int argc, char **argv)
 
 		if (!get_i2c_port(port)) {
 			ccprintf("i2c passthru protect invalid port %d\n",
-				port);
+				 port);
 			return EC_RES_INVALID_PARAM;
 		}
 
@@ -1631,8 +1553,7 @@ static int command_i2cprotect(int argc, char **argv)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(i2cprotect, command_i2cprotect,
-			"[port]",
+DECLARE_CONSOLE_COMMAND(i2cprotect, command_i2cprotect, "[port]",
 			"Protect I2C bus");
 #endif
 
@@ -1662,12 +1583,12 @@ static void scan_bus(int port, const char *desc)
 	 */
 	for (addr_flags = I2C_FIRST_VALID_ADDR;
 	     addr_flags <= I2C_LAST_VALID_ADDR; ++addr_flags) {
-		watchdog_reload();  /* Otherwise a full scan trips watchdog */
+		watchdog_reload(); /* Otherwise a full scan trips watchdog */
 		ccputs(".");
 
 		/* Do a single read */
-		if (!i2c_xfer_unlocked(port, addr_flags,
-				       NULL, 0, &tmp, 1, I2C_XFER_SINGLE))
+		if (!i2c_xfer_unlocked(port, addr_flags, NULL, 0, &tmp, 1,
+				       I2C_XFER_SINGLE))
 			ccprintf("\n  0x%02x", addr_flags);
 	}
 
@@ -1676,7 +1597,7 @@ scan_bus_exit:
 	ccputs("\n");
 }
 
-static int command_scan(int argc, char **argv)
+static int command_scan(int argc, const char **argv)
 {
 	int port;
 	char *e;
@@ -1694,7 +1615,6 @@ static int command_scan(int argc, char **argv)
 		return EC_SUCCESS;
 	}
 
-
 	port = strtoi(argv[1], &e, 0);
 	if (*e)
 		return EC_ERROR_PARAM2;
@@ -1707,13 +1627,12 @@ static int command_scan(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(i2cscan, command_scan,
-			"i2cscan [port]",
+DECLARE_CONSOLE_COMMAND(i2cscan, command_scan, "i2cscan [port]",
 			"Scan I2C ports for devices");
 #endif
 
 #ifdef CONFIG_CMD_I2C_XFER
-static int command_i2cxfer(int argc, char **argv)
+static int command_i2cxfer(int argc, const char **argv)
 {
 	int port;
 	uint16_t addr_flags;
@@ -1750,22 +1669,18 @@ static int command_i2cxfer(int argc, char **argv)
 	if (strcasecmp(argv[1], "r") == 0) {
 		/* 8-bit read */
 		if (offset_size == 2)
-			rv = i2c_read_offset16(port, addr_flags,
-					       offset, &v, 1);
+			rv = i2c_read_offset16(port, addr_flags, offset, &v, 1);
 		else
-			rv = i2c_read8(port, addr_flags,
-				       offset, &v);
+			rv = i2c_read8(port, addr_flags, offset, &v);
 		if (!rv)
 			ccprintf("0x%02x [%d]\n", v, v);
 
 	} else if (strcasecmp(argv[1], "r16") == 0) {
 		/* 16-bit read */
 		if (offset_size == 2)
-			rv = i2c_read_offset16(port, addr_flags,
-					       offset, &v, 2);
+			rv = i2c_read_offset16(port, addr_flags, offset, &v, 2);
 		else
-			rv = i2c_read16(port, addr_flags,
-					offset, &v);
+			rv = i2c_read16(port, addr_flags, offset, &v);
 		if (!rv)
 			ccprintf("0x%04x [%d]\n", v, v);
 
@@ -1774,33 +1689,33 @@ static int command_i2cxfer(int argc, char **argv)
 		if (argc < 6 || v < 0 || v > sizeof(data))
 			return EC_ERROR_PARAM5;
 
-		rv = i2c_xfer(port, addr_flags,
-			      (uint8_t *)&offset, 1, data, v);
+		rv = i2c_xfer(port, addr_flags, (uint8_t *)&offset, 1, data, v);
 
-		if (!rv)
-			ccprintf("Data: %ph\n", HEX_BUF(data, v));
+		if (!rv) {
+			char str_buf[hex_str_buf_size(v)];
+
+			snprintf_hex_buffer(str_buf, sizeof(str_buf),
+					    HEX_BUF(data, v));
+			ccprintf("Data: %s\n", str_buf);
+		}
 
 	} else if (strcasecmp(argv[1], "w") == 0) {
 		/* 8-bit write */
 		if (argc < 6)
 			return EC_ERROR_PARAM5;
 		if (offset_size == 2)
-			rv = i2c_write_offset16(port, addr_flags,
-						offset, v, 1);
+			rv = i2c_write_offset16(port, addr_flags, offset, v, 1);
 		else
-			rv = i2c_write8(port, addr_flags,
-					offset, v);
+			rv = i2c_write8(port, addr_flags, offset, v);
 
 	} else if (strcasecmp(argv[1], "w16") == 0) {
 		/* 16-bit write */
 		if (argc < 6)
 			return EC_ERROR_PARAM5;
 		if (offset_size == 2)
-			rv = i2c_write_offset16(port, addr_flags,
-						offset, v, 2);
+			rv = i2c_write_offset16(port, addr_flags, offset, v, 2);
 		else
-			rv = i2c_write16(port, addr_flags,
-					 offset, v);
+			rv = i2c_write16(port, addr_flags, offset, v);
 #ifdef CONFIG_CMD_I2C_XFER_RAW
 	} else if (strcasecmp(argv[1], "raw") == 0) {
 		/* <port> <addr_flags> <read_count> [write_bytes..] */
@@ -1836,11 +1751,8 @@ static int command_i2cxfer(int argc, char **argv)
 				xferflags |= I2C_XFER_STOP;
 			ccprintf("Writing %d bytes\n", write_count);
 			i2c_lock(port, 1);
-			rv = i2c_xfer_unlocked(port,
-					       addr_flags,
-					       data, write_count,
-					       NULL, 0,
-					       xferflags);
+			rv = i2c_xfer_unlocked(port, addr_flags, data,
+					       write_count, NULL, 0, xferflags);
 			if (rv || read_count == 0) {
 				i2c_lock(port, 0);
 				return rv;
@@ -1850,15 +1762,17 @@ static int command_i2cxfer(int argc, char **argv)
 			ccprintf("Reading %d bytes\n", read_count);
 			if (write_count == 0)
 				i2c_lock(port, 1);
-			rv = i2c_xfer_unlocked(port,
-					       addr_flags,
-					       NULL, 0,
-					       data, read_count,
+			rv = i2c_xfer_unlocked(port, addr_flags, NULL, 0, data,
+					       read_count,
 					       I2C_XFER_START | I2C_XFER_STOP);
 			i2c_lock(port, 0);
-			if (!rv)
-				ccprintf("Data: %ph\n",
-					 HEX_BUF(data, read_count));
+			if (!rv) {
+				char str_buf[hex_str_buf_size(read_count)];
+
+				snprintf_hex_buffer(str_buf, sizeof(str_buf),
+						    HEX_BUF(data, read_count));
+				ccprintf("Data: %s\n", str_buf);
+			}
 		}
 #endif /* CONFIG_CMD_I2C_XFER_RAW */
 	} else {
@@ -1878,7 +1792,7 @@ DECLARE_CONSOLE_COMMAND(i2cxfer, command_i2cxfer,
 
 #ifdef CONFIG_CMD_I2C_SPEED
 
-static const char * const i2c_freq_str[] = {
+static const char *const i2c_freq_str[] = {
 	[I2C_FREQ_1000KHZ] = "1000 kHz",
 	[I2C_FREQ_400KHZ] = "400 kHz",
 	[I2C_FREQ_100KHZ] = "100 kHz",
@@ -1887,7 +1801,7 @@ static const char * const i2c_freq_str[] = {
 
 BUILD_ASSERT(ARRAY_SIZE(i2c_freq_str) == I2C_FREQ_COUNT + 1);
 
-static int command_i2c_speed(int argc, char **argv)
+static int command_i2c_speed(int argc, const char **argv)
 {
 	int port;
 	char *e;
@@ -1936,16 +1850,14 @@ static int command_i2c_speed(int argc, char **argv)
 
 	if (new_freq != I2C_FREQ_COUNT)
 		ccprintf("Port %d speed changed from %s to %s\n", port,
-			 i2c_freq_str[freq],
-			 i2c_freq_str[new_freq]);
+			 i2c_freq_str[freq], i2c_freq_str[new_freq]);
 	else
 		ccprintf("Port %d speed is %s\n", port, i2c_freq_str[freq]);
 
 	return EC_SUCCESS;
 }
 
-DECLARE_CONSOLE_COMMAND(i2cspeed, command_i2c_speed,
-			"port [speed in kHz]",
+DECLARE_CONSOLE_COMMAND(i2cspeed, command_i2c_speed, "port [speed in kHz]",
 			"Get or set I2C port speed");
 
 #endif /* CONFIG_CMD_I2C_SPEED */
@@ -1955,23 +1867,20 @@ static void i2c_test_status(struct i2c_test_results *i2c_test, int test_dev)
 {
 	ccprintf("test_dev=%2d, ", test_dev);
 	ccprintf("r=%5d, rs=%5d, rf=%5d, ",
-		i2c_test->read_success + i2c_test->read_fail,
-		i2c_test->read_success,
-		i2c_test->read_fail);
+		 i2c_test->read_success + i2c_test->read_fail,
+		 i2c_test->read_success, i2c_test->read_fail);
 
 	ccprintf("w=%5d, ws=%5d, wf=%5d\n",
-		i2c_test->write_success + i2c_test->write_fail,
-		i2c_test->write_success,
-		i2c_test->write_fail);
+		 i2c_test->write_success + i2c_test->write_fail,
+		 i2c_test->write_success, i2c_test->write_fail);
 
 	i2c_test->read_success = 0;
 	i2c_test->read_fail = 0;
-	i2c_test->write_success = 0,
-	i2c_test->write_fail = 0;
+	i2c_test->write_success = 0, i2c_test->write_fail = 0;
 }
 
 #define I2C_STRESS_TEST_DATA_VERIFY_RETRY_COUNT 3
-static int command_i2ctest(int argc, char **argv)
+static int command_i2ctest(int argc, const char **argv)
 {
 	char *e;
 	int i, j, rv;
@@ -2025,10 +1934,11 @@ static int command_i2ctest(int argc, char **argv)
 		if (rand & 0x1) {
 			/* read */
 			rv = i2c_s_test->i2c_read ?
-				i2c_s_test->i2c_read(port, addr_flags,
-					reg_s_info->read_reg, &data) :
-				i2c_s_test->i2c_read_dev(
-					reg_s_info->read_reg, &data);
+				     i2c_s_test->i2c_read(port, addr_flags,
+							  reg_s_info->read_reg,
+							  &data) :
+				     i2c_s_test->i2c_read_dev(
+					     reg_s_info->read_reg, &data);
 			if (rv || data != reg_s_info->read_val)
 				test_s_results->read_fail++;
 			else
@@ -2042,10 +1952,11 @@ static int command_i2ctest(int argc, char **argv)
 
 			/* Read the write register */
 			rv = i2c_s_test->i2c_read ?
-				i2c_s_test->i2c_read(port, addr_flags,
-					reg_s_info->read_reg, &data) :
-				i2c_s_test->i2c_read_dev(
-					reg_s_info->read_reg, &data);
+				     i2c_s_test->i2c_read(port, addr_flags,
+							  reg_s_info->read_reg,
+							  &data) :
+				     i2c_s_test->i2c_read_dev(
+					     reg_s_info->read_reg, &data);
 			if (rv) {
 				/* Skip writing invalid data */
 				test_s_results->read_fail++;
@@ -2057,11 +1968,13 @@ static int command_i2ctest(int argc, char **argv)
 			do {
 				/* Write same value back */
 				rv = i2c_s_test->i2c_write ?
-					i2c_s_test->i2c_write(port,
-					addr_flags,
-					reg_s_info->write_reg, data) :
-					i2c_s_test->i2c_write_dev(
-					reg_s_info->write_reg, data);
+					     i2c_s_test->i2c_write(
+						     port, addr_flags,
+						     reg_s_info->write_reg,
+						     data) :
+					     i2c_s_test->i2c_write_dev(
+						     reg_s_info->write_reg,
+						     data);
 				i++;
 				if (rv) {
 					/* Skip reading as write failed */
@@ -2072,11 +1985,13 @@ static int command_i2ctest(int argc, char **argv)
 
 				/* Read back to verify the data */
 				rv = i2c_s_test->i2c_read ?
-					i2c_s_test->i2c_read(port,
-					addr_flags,
-					reg_s_info->read_reg, &data_verify) :
-					i2c_s_test->i2c_read_dev(
-					reg_s_info->read_reg, &data_verify);
+					     i2c_s_test->i2c_read(
+						     port, addr_flags,
+						     reg_s_info->read_reg,
+						     &data_verify) :
+					     i2c_s_test->i2c_read_dev(
+						     reg_s_info->read_reg,
+						     &data_verify);
 				i++;
 				if (rv) {
 					/* Read failed try next time */
@@ -2111,7 +2026,6 @@ static int command_i2ctest(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(i2ctest, command_i2ctest,
-			"i2ctest count|udelay|dev",
+DECLARE_CONSOLE_COMMAND(i2ctest, command_i2ctest, "i2ctest count|udelay|dev",
 			"I2C stress test");
 #endif /* CONFIG_CMD_I2C_STRESS_TEST */
diff --git a/common/i2c_hid_touchpad.c b/common/i2c_hid_touchpad.c
index 29122f83d6..02261d8fa4 100644
--- a/common/i2c_hid_touchpad.c
+++ b/common/i2c_hid_touchpad.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,23 +10,23 @@
 #include "util.h"
 
 /* 2 bytes for length + 1 byte for report ID */
-#define I2C_HID_HEADER_SIZE			3
+#define I2C_HID_HEADER_SIZE 3
 
 /* Report ID */
-#define REPORT_ID_TOUCH				0x01
-#define REPORT_ID_MOUSE				0x02
-#define REPORT_ID_DEVICE_CAPS			0x0A
-#define REPORT_ID_DEVICE_CERT			0x0B
-#define REPORT_ID_INPUT_MODE			0x0C
-#define REPORT_ID_REPORTING			0x0D
+#define REPORT_ID_TOUCH 0x01
+#define REPORT_ID_MOUSE 0x02
+#define REPORT_ID_DEVICE_CAPS 0x0A
+#define REPORT_ID_DEVICE_CERT 0x0B
+#define REPORT_ID_INPUT_MODE 0x0C
+#define REPORT_ID_REPORTING 0x0D
 
-#define INPUT_MODE_MOUSE			0x00
-#define INPUT_MODE_TOUCH			0x03
+#define INPUT_MODE_MOUSE 0x00
+#define INPUT_MODE_TOUCH 0x03
 
 /* VID/PID/FW version */
-#if !defined(I2C_HID_TOUCHPAD_VENDOR_ID) || \
-    !defined(I2C_HID_TOUCHPAD_PRODUCT_ID) || \
-    !defined(I2C_HID_TOUCHPAD_FW_VERSION)
+#if !defined(I2C_HID_TOUCHPAD_VENDOR_ID) ||      \
+	!defined(I2C_HID_TOUCHPAD_PRODUCT_ID) || \
+	!defined(I2C_HID_TOUCHPAD_FW_VERSION)
 #error "Must define touchpad VID/PID/FW version"
 #endif
 /*
@@ -34,10 +34,9 @@
  *
  * Physical dimensions are in the unit of mms.
  */
-#if !defined(I2C_HID_TOUCHPAD_MAX_X) || \
-    !defined(I2C_HID_TOUCHPAD_MAX_Y) || \
-    !defined(I2C_HID_TOUCHPAD_MAX_PHYSICAL_X) || \
-    !defined(I2C_HID_TOUCHPAD_MAX_PHYSICAL_Y)
+#if !defined(I2C_HID_TOUCHPAD_MAX_X) || !defined(I2C_HID_TOUCHPAD_MAX_Y) || \
+	!defined(I2C_HID_TOUCHPAD_MAX_PHYSICAL_X) ||                        \
+	!defined(I2C_HID_TOUCHPAD_MAX_PHYSICAL_Y)
 #error "Must define finger maximum X/Y and physical dimensions"
 #endif
 /*
@@ -49,9 +48,9 @@
  * different data ranges. It is therefore recommended for the user to check the
  * device's spec and set these values manually.
  */
-#if !defined(I2C_HID_TOUCHPAD_MAX_WIDTH) || \
-    !defined(I2C_HID_TOUCHPAD_MAX_HEIGHT) || \
-    !defined(I2C_HID_TOUCHPAD_MAX_PRESSURE)
+#if !defined(I2C_HID_TOUCHPAD_MAX_WIDTH) ||      \
+	!defined(I2C_HID_TOUCHPAD_MAX_HEIGHT) || \
+	!defined(I2C_HID_TOUCHPAD_MAX_PRESSURE)
 #error "Must define finger maximum width/height/pressure"
 #endif
 /*
@@ -67,42 +66,37 @@
  * This is a bit similar to the mouse CPI and is used by mouse reports only.
  */
 #if !defined(I2C_HID_TOUCHPAD_MOUSE_SCALE_X) || \
-    !defined(I2C_HID_TOUCHPAD_MOUSE_SCALE_Y)
+	!defined(I2C_HID_TOUCHPAD_MOUSE_SCALE_Y)
 #error "Must define mouse horizontal/vertical scaling factors"
 #endif
 
 /* Helper bit-op macros */
-#define N_BITS(n) \
-( \
-		(n) < (1 << 1) ? 1 : \
-		(n) < (1 << 2) ? 2 : \
-		(n) < (1 << 3) ? 3 : \
-		(n) < (1 << 4) ? 4 : \
-		(n) < (1 << 5) ? 5 : \
-		(n) < (1 << 6) ? 6 : \
-		(n) < (1 << 7) ? 7 : \
-		(n) < (1 << 8) ? 8 : \
-		(n) < (1 << 9) ? 9 : \
-		(n) < (1 << 10) ? 10 : \
-		(n) < (1 << 11) ? 11 : \
-		(n) < (1 << 12) ? 12 : \
-		(n) < (1 << 13) ? 13 : \
-		(n) < (1 << 14) ? 14 : \
-		(n) < (1 << 15) ? 15 : \
-		16 \
-)
+#define N_BITS(n)               \
+	((n) < (1 << 1)	 ? 1 :  \
+	 (n) < (1 << 2)	 ? 2 :  \
+	 (n) < (1 << 3)	 ? 3 :  \
+	 (n) < (1 << 4)	 ? 4 :  \
+	 (n) < (1 << 5)	 ? 5 :  \
+	 (n) < (1 << 6)	 ? 6 :  \
+	 (n) < (1 << 7)	 ? 7 :  \
+	 (n) < (1 << 8)	 ? 8 :  \
+	 (n) < (1 << 9)	 ? 9 :  \
+	 (n) < (1 << 10) ? 10 : \
+	 (n) < (1 << 11) ? 11 : \
+	 (n) < (1 << 12) ? 12 : \
+	 (n) < (1 << 13) ? 13 : \
+	 (n) < (1 << 14) ? 14 : \
+	 (n) < (1 << 15) ? 15 : \
+			   16)
 /* We would need to pad some bits at the end of each finger struct to match
  * the allocation unit's boundary so the array indexing may work correctly.
  */
-#define N_VAR_BITS \
-( \
-		N_BITS(I2C_HID_TOUCHPAD_MAX_X) + \
-		N_BITS(I2C_HID_TOUCHPAD_MAX_Y) + \
-		N_BITS(I2C_HID_TOUCHPAD_MAX_WIDTH) + \
-		N_BITS(I2C_HID_TOUCHPAD_MAX_HEIGHT) + \
-		N_BITS(I2C_HID_TOUCHPAD_MAX_PRESSURE) + \
-		N_BITS(I2C_HID_TOUCHPAD_MAX_ORIENTATION) \
-)
+#define N_VAR_BITS                                                         \
+	(N_BITS(I2C_HID_TOUCHPAD_MAX_X) + N_BITS(I2C_HID_TOUCHPAD_MAX_Y) + \
+	 N_BITS(I2C_HID_TOUCHPAD_MAX_WIDTH) +                              \
+	 N_BITS(I2C_HID_TOUCHPAD_MAX_HEIGHT) +                             \
+	 N_BITS(I2C_HID_TOUCHPAD_MAX_PRESSURE) +                           \
+	 N_BITS(I2C_HID_TOUCHPAD_MAX_ORIENTATION))
 #define N_PADDING_BITS ((DIV_ROUND_UP(N_VAR_BITS, 8) * 8) - N_VAR_BITS)
 #define N_BITS_ORIENTATION \
 	(N_BITS(I2C_HID_TOUCHPAD_MAX_ORIENTATION) + N_PADDING_BITS)
@@ -121,45 +115,45 @@ struct finger {
 	 * identify unintended contacts or palms but is up to the OS
 	 * explanation.
 	 */
-	uint8_t confidence:1;
+	uint8_t confidence : 1;
 	/*
 	 * Whether a finger is touching the surface (leaving/left finger gets
 	 * 0).
 	 */
-	uint8_t tip:1;
+	uint8_t tip : 1;
 	/*
 	 * Whether a finger is within the sensor range. For example, hovering
 	 * fingers would have tip=0 and inrange=1.
 	 */
-	uint8_t inrange:1;
+	uint8_t inrange : 1;
 	/*
 	 * Contact id. This is like slot numbers in Linux MT-B.
 	 */
-	uint8_t id:5;
-	uint16_t x:N_BITS(I2C_HID_TOUCHPAD_MAX_X);
-	uint16_t y:N_BITS(I2C_HID_TOUCHPAD_MAX_Y);
-	uint16_t width:N_BITS(I2C_HID_TOUCHPAD_MAX_WIDTH);
-	uint16_t height:N_BITS(I2C_HID_TOUCHPAD_MAX_HEIGHT);
-	uint16_t pressure:N_BITS(I2C_HID_TOUCHPAD_MAX_PRESSURE);
-	uint16_t orientation:N_BITS_ORIENTATION;
+	uint8_t id : 5;
+	uint16_t x : N_BITS(I2C_HID_TOUCHPAD_MAX_X);
+	uint16_t y : N_BITS(I2C_HID_TOUCHPAD_MAX_Y);
+	uint16_t width : N_BITS(I2C_HID_TOUCHPAD_MAX_WIDTH);
+	uint16_t height : N_BITS(I2C_HID_TOUCHPAD_MAX_HEIGHT);
+	uint16_t pressure : N_BITS(I2C_HID_TOUCHPAD_MAX_PRESSURE);
+	uint16_t orientation : N_BITS_ORIENTATION;
 } __packed;
 
 struct touch_report {
-	uint8_t button:1;
-	uint8_t count:7;
+	uint8_t button : 1;
+	uint8_t count : 7;
 	uint16_t timestamp;
 	struct finger finger[I2C_HID_TOUCHPAD_MAX_FINGERS];
 } __packed;
 
 struct mouse_report {
-	uint8_t button1:1;
+	uint8_t button1 : 1;
 	/* Windows expects at least two button usages in a mouse report. Many
 	 * touchpads on the Chromebook are a single clickable surface, so
 	 * button2 isn't used. That said, we may later report a button2 event if
 	 * necessary.
 	 */
-	uint8_t button2:1;
-	uint8_t unused:6;
+	uint8_t button2 : 1;
+	uint8_t unused : 6;
 	int8_t x;
 	int8_t y;
 } __packed;
@@ -173,231 +167,215 @@ struct mouse_report {
  */
 static const uint8_t report_desc[] = {
 	/* Mouse Collection */
-	0x05, 0x01,			/* Usage Page (Generic Desktop) */
-	0x09, 0x02,			/* Usage (Mouse) */
-	0xA1, 0x01,			/* Collection (Application) */
-	0x85, REPORT_ID_MOUSE,		/* Report ID (Mouse) */
-	0x09, 0x01,			/*   Usage (Pointer) */
-	0xA1, 0x00,			/*   Collection (Physical) */
-	0x05, 0x09,			/*     Usage Page (Button) */
-	0x19, 0x01,			/*     Usage Minimum (Button 1) */
-	0x29, 0x02,			/*     Usage Maximum (Button 2) */
-	0x15, 0x00,			/*     Logical Minimum (0) */
-	0x25, 0x01,			/*     Logical Maximum (1) */
-	0x75, 0x01,			/*     Report Size (1) */
-	0x95, 0x02,			/*     Report Count (2) */
-	0x81, 0x02,			/*     Input (Data,Var,Abs) */
-	0x95, 0x06,			/*     Report Count (6) */
-	0x81, 0x03,			/*     Input (Cnst,Var,Abs) */
-	0x05, 0x01,			/*     Usage Page (Generic Desktop) */
-	0x09, 0x30,			/*     Usage (X) */
-	0x09, 0x31,			/*     Usage (Y) */
-	0x15, 0x81,			/*     Logical Minimum (-127) */
-	0x25, 0x7F,			/*     Logical Maximum (127) */
-	0x75, 0x08,			/*     Report Size (8) */
-	0x95, 0x02,			/*     Report Count (2) */
-	0x81, 0x06,			/*     Input (Data,Var,Rel) */
-	0xC0,				/*   End Collection */
-	0xC0,				/* End Collection */
+	0x05, 0x01, /* Usage Page (Generic Desktop) */
+	0x09, 0x02, /* Usage (Mouse) */
+	0xA1, 0x01, /* Collection (Application) */
+	0x85, REPORT_ID_MOUSE, /* Report ID (Mouse) */
+	0x09, 0x01, /*   Usage (Pointer) */
+	0xA1, 0x00, /*   Collection (Physical) */
+	0x05, 0x09, /*     Usage Page (Button) */
+	0x19, 0x01, /*     Usage Minimum (Button 1) */
+	0x29, 0x02, /*     Usage Maximum (Button 2) */
+	0x15, 0x00, /*     Logical Minimum (0) */
+	0x25, 0x01, /*     Logical Maximum (1) */
+	0x75, 0x01, /*     Report Size (1) */
+	0x95, 0x02, /*     Report Count (2) */
+	0x81, 0x02, /*     Input (Data,Var,Abs) */
+	0x95, 0x06, /*     Report Count (6) */
+	0x81, 0x03, /*     Input (Cnst,Var,Abs) */
+	0x05, 0x01, /*     Usage Page (Generic Desktop) */
+	0x09, 0x30, /*     Usage (X) */
+	0x09, 0x31, /*     Usage (Y) */
+	0x15, 0x81, /*     Logical Minimum (-127) */
+	0x25, 0x7F, /*     Logical Maximum (127) */
+	0x75, 0x08, /*     Report Size (8) */
+	0x95, 0x02, /*     Report Count (2) */
+	0x81, 0x06, /*     Input (Data,Var,Rel) */
+	0xC0, /*   End Collection */
+	0xC0, /* End Collection */
 
 	/* Touchpad Collection */
-	0x05, 0x0D,			/* Usage Page (Digitizer) */
-	0x09, 0x05,			/* Usage (Touch Pad) */
-	0xA1, 0x01,			/* Collection (Application) */
-	0x85, REPORT_ID_TOUCH,		/*   Report ID (Touch) */
+	0x05, 0x0D, /* Usage Page (Digitizer) */
+	0x09, 0x05, /* Usage (Touch Pad) */
+	0xA1, 0x01, /* Collection (Application) */
+	0x85, REPORT_ID_TOUCH, /*   Report ID (Touch) */
 
 	/* Button */
-	0x05, 0x09,			/*   Usage Page (Button) */
-	0x19, 0x01,			/*   Usage Minimum (0x01) */
-	0x29, 0x01,			/*   Usage Maximum (0x01) */
-	0x15, 0x00,			/*   Logical Minimum (0) */
-	0x25, 0x01,			/*   Logical Maximum (1) */
-	0x75, 0x01,			/*   Report Size (1) */
-	0x95, 0x01,			/*   Report Count (1) */
-	0x81, 0x02,			/*   Input (Data,Var,Abs) */
+	0x05, 0x09, /*   Usage Page (Button) */
+	0x19, 0x01, /*   Usage Minimum (0x01) */
+	0x29, 0x01, /*   Usage Maximum (0x01) */
+	0x15, 0x00, /*   Logical Minimum (0) */
+	0x25, 0x01, /*   Logical Maximum (1) */
+	0x75, 0x01, /*   Report Size (1) */
+	0x95, 0x01, /*   Report Count (1) */
+	0x81, 0x02, /*   Input (Data,Var,Abs) */
 
 	/* Contact count */
-	0x05, 0x0D,			/*   Usage Page (Digitizer) */
-	0x09, 0x54,			/*   Usage (Contact count) */
-	0x25, I2C_HID_TOUCHPAD_MAX_FINGERS,	/* Logical Max. (MAX_FINGERS) */
-	0x75, 0x07,			/*   Report Size (7) */
-	0x95, 0x01,			/*   Report Count (1) */
-	0x81, 0x02,			/*   Input (Data,Var,Abs) */
+	0x05, 0x0D, /*   Usage Page (Digitizer) */
+	0x09, 0x54, /*   Usage (Contact count) */
+	0x25, I2C_HID_TOUCHPAD_MAX_FINGERS, /* Logical Max. (MAX_FINGERS) */
+	0x75, 0x07, /*   Report Size (7) */
+	0x95, 0x01, /*   Report Count (1) */
+	0x81, 0x02, /*   Input (Data,Var,Abs) */
 
 	/* Scan time */
-	0x55, 0x0C,			/*   Unit Exponent (-4) */
-	0x66, 0x01, 0x10,		/*   Unit (Seconds) */
-	0x47, 0xFF, 0xFF, 0x00, 0x00,	/*   Physical Maximum (65535) */
-	0x27, 0xFF, 0xFF, 0x00, 0x00,	/*   Logical Maximum (65535) */
-	0x75, 0x10,			/*   Report Size (16) */
-	0x95, 0x01,			/*   Report Count (1) */
-	0x05, 0x0D,			/*   Usage Page (Digitizers) */
-	0x09, 0x56,			/*   Usage (Scan Time) */
-	0x81, 0x02,			/*   Input (Data,Var,Abs) */
-
-#define FINGER(FINGER_NUMBER)						       \
-	/* Finger FINGER_NUMBER */					       \
-	0x05, 0x0D,			/*   Usage Page (Digitizer) */         \
-	0x09, 0x22,			/*   Usage (Finger) */                 \
-	0xA1, 0x02,			/*   Collection (Logical) */           \
-	0x09, 0x47,			/*     Usage (Confidence) */           \
-	0x09, 0x42,			/*     Usage (Tip Switch) */           \
-	0x09, 0x32,			/*     Usage (In Range) */             \
-	0x15, 0x00,			/*     Logical Minimum (0) */          \
-	0x25, 0x01,			/*     Logical Maximum (1) */          \
-	0x75, 0x01,			/*     Report Size (1) */              \
-	0x95, 0x03,			/*     Report Count (3) */             \
-	0x81, 0x02,			/*     Input (Data,Var,Abs) */         \
-	0x09, 0x51,			/*     Usage (Contact identifier) */   \
-	0x25, 0x1F,			/*     Logical Maximum (31) */         \
-	0x75, 0x05,			/*     Report Size (5) */              \
-	0x95, 0x01,			/*     Report Count (1) */             \
-	0x81, 0x02,			/*     Input (Data,Var,Abs) */         \
-	0x05, 0x01,			/*     Usage Page (Generic Desktop) */ \
-	0x09, 0x30,			/*     Usage (X) */                    \
-	0x55, 0x0E,			/*     Unit Exponent (-2) */           \
-	0x65, 0x11,			/*     Unit (SI Linear, Length: cm) */ \
-	0x35, 0x00,			/*     Physical Minimum (0) */         \
-	0x46, I2C_HID_TOUCHPAD_MAX_PHYSICAL_X&0xff,			       \
-	      I2C_HID_TOUCHPAD_MAX_PHYSICAL_X>>8,			       \
-					/*     Physical Maximum */	       \
-	0x26, I2C_HID_TOUCHPAD_MAX_X&0xff, I2C_HID_TOUCHPAD_MAX_X>>8,	       \
-					/*     Logical Maximum */	       \
-	0x75, N_BITS(I2C_HID_TOUCHPAD_MAX_X),				       \
-					/*     Report Size */		       \
-	0x81, 0x02,			/*     Input (Data,Var,Abs) */         \
-	0x09, 0x31,			/*     Usage (Y) */                    \
-	0x46, I2C_HID_TOUCHPAD_MAX_PHYSICAL_Y&0xff,			       \
-	      I2C_HID_TOUCHPAD_MAX_PHYSICAL_Y>>8,			       \
-					/*     Physical Maximum */	       \
-	0x26, I2C_HID_TOUCHPAD_MAX_Y&0xff, I2C_HID_TOUCHPAD_MAX_Y>>8,	       \
-					/*     Logical Maximum */	       \
-	0x75, N_BITS(I2C_HID_TOUCHPAD_MAX_Y),				       \
-					/*     Report Size */		       \
-	0x81, 0x02,			/*     Input (Data,Var,Abs) */         \
-	0x05, 0x0D,			/*     Usage Page (Digitizer) */       \
-	0x09, 0x48,			/*     Usage (Width) */                \
-	0x26, I2C_HID_TOUCHPAD_MAX_WIDTH&0xff, I2C_HID_TOUCHPAD_MAX_WIDTH>>8,  \
-					/*     Logical Maximum */	       \
-	0x75, N_BITS(I2C_HID_TOUCHPAD_MAX_WIDTH),			       \
-					/*     Report Size */		       \
-	0x81, 0x02,			/*     Input (Data,Var,Abs) */         \
-	0x09, 0x49,			/*     Usage (Height) */               \
-	0x26, I2C_HID_TOUCHPAD_MAX_HEIGHT&0xff, I2C_HID_TOUCHPAD_MAX_HEIGHT>>8,\
-					/*     Logical Maximum */	       \
-	0x75, N_BITS(I2C_HID_TOUCHPAD_MAX_HEIGHT),			       \
-					/*     Report Size */		       \
-	0x81, 0x02,			/*     Input (Data,Var,Abs) */         \
-	0x09, 0x30,			/*     Usage (Tip pressure) */         \
-	0x26, I2C_HID_TOUCHPAD_MAX_PRESSURE&0xff,			       \
-	      I2C_HID_TOUCHPAD_MAX_PRESSURE>>8,				       \
-					/*     Logical Maximum */	       \
-	0x75, N_BITS(I2C_HID_TOUCHPAD_MAX_PRESSURE),			       \
-					/*     Report Size */		       \
-	0x81, 0x02,			/*     Input (Data,Var,Abs) */         \
-	0x09, 0x3f,			/*     Usage (Azimuth Orientation) */  \
-	0x16, 0x00, 0x00,		/*     Logical Minimum (0) */          \
-	0x26, I2C_HID_TOUCHPAD_MAX_ORIENTATION&0xff,			       \
-	      I2C_HID_TOUCHPAD_MAX_ORIENTATION>>8,			       \
-					/*     Logical Maximum */	       \
-	0x75, N_BITS_ORIENTATION,	/*     Report Size */		       \
-	0x81, 0x02,			/*     Input (Data,Var,Abs) */         \
-	0xC0,				/*   End Collection */
-
-	FINGER(1)
-	FINGER(2)
-	FINGER(3)
-	FINGER(4)
-	FINGER(5)
+	0x55, 0x0C, /*   Unit Exponent (-4) */
+	0x66, 0x01, 0x10, /*   Unit (Seconds) */
+	0x47, 0xFF, 0xFF, 0x00, 0x00, /*   Physical Maximum (65535) */
+	0x27, 0xFF, 0xFF, 0x00, 0x00, /*   Logical Maximum (65535) */
+	0x75, 0x10, /*   Report Size (16) */
+	0x95, 0x01, /*   Report Count (1) */
+	0x05, 0x0D, /*   Usage Page (Digitizers) */
+	0x09, 0x56, /*   Usage (Scan Time) */
+	0x81, 0x02, /*   Input (Data,Var,Abs) */
+
+#define FINGER(FINGER_NUMBER)                                                 \
+	/* Finger FINGER_NUMBER */                                            \
+	0x05, 0x0D, /*   Usage Page (Digitizer) */                            \
+		0x09, 0x22, /*   Usage (Finger) */                            \
+		0xA1, 0x02, /*   Collection (Logical) */                      \
+		0x09, 0x47, /*     Usage (Confidence) */                      \
+		0x09, 0x42, /*     Usage (Tip Switch) */                      \
+		0x09, 0x32, /*     Usage (In Range) */                        \
+		0x15, 0x00, /*     Logical Minimum (0) */                     \
+		0x25, 0x01, /*     Logical Maximum (1) */                     \
+		0x75, 0x01, /*     Report Size (1) */                         \
+		0x95, 0x03, /*     Report Count (3) */                        \
+		0x81, 0x02, /*     Input (Data,Var,Abs) */                    \
+		0x09, 0x51, /*     Usage (Contact identifier) */              \
+		0x25, 0x1F, /*     Logical Maximum (31) */                    \
+		0x75, 0x05, /*     Report Size (5) */                         \
+		0x95, 0x01, /*     Report Count (1) */                        \
+		0x81, 0x02, /*     Input (Data,Var,Abs) */                    \
+		0x05, 0x01, /*     Usage Page (Generic Desktop) */            \
+		0x09, 0x30, /*     Usage (X) */                               \
+		0x55, 0x0E, /*     Unit Exponent (-2) */                      \
+		0x65, 0x11, /*     Unit (SI Linear, Length: cm) */            \
+		0x35, 0x00, /*     Physical Minimum (0) */                    \
+		0x46, I2C_HID_TOUCHPAD_MAX_PHYSICAL_X & 0xff,                 \
+		I2C_HID_TOUCHPAD_MAX_PHYSICAL_X >> 8, /*     Physical Maximum \
+						       */                     \
+		0x26, I2C_HID_TOUCHPAD_MAX_X & 0xff,                          \
+		I2C_HID_TOUCHPAD_MAX_X >> 8, /*     Logical Maximum */        \
+		0x75, N_BITS(I2C_HID_TOUCHPAD_MAX_X), /*     Report Size */   \
+		0x81, 0x02, /*     Input (Data,Var,Abs) */                    \
+		0x09, 0x31, /*     Usage (Y) */                               \
+		0x46, I2C_HID_TOUCHPAD_MAX_PHYSICAL_Y & 0xff,                 \
+		I2C_HID_TOUCHPAD_MAX_PHYSICAL_Y >> 8, /*     Physical Maximum \
+						       */                     \
+		0x26, I2C_HID_TOUCHPAD_MAX_Y & 0xff,                          \
+		I2C_HID_TOUCHPAD_MAX_Y >> 8, /*     Logical Maximum */        \
+		0x75, N_BITS(I2C_HID_TOUCHPAD_MAX_Y), /*     Report Size */   \
+		0x81, 0x02, /*     Input (Data,Var,Abs) */                    \
+		0x05, 0x0D, /*     Usage Page (Digitizer) */                  \
+		0x09, 0x48, /*     Usage (Width) */                           \
+		0x26, I2C_HID_TOUCHPAD_MAX_WIDTH & 0xff,                      \
+		I2C_HID_TOUCHPAD_MAX_WIDTH >> 8, /*     Logical Maximum */    \
+		0x75, N_BITS(I2C_HID_TOUCHPAD_MAX_WIDTH), /*     Report Size  \
+							   */                 \
+		0x81, 0x02, /*     Input (Data,Var,Abs) */                    \
+		0x09, 0x49, /*     Usage (Height) */                          \
+		0x26, I2C_HID_TOUCHPAD_MAX_HEIGHT & 0xff,                     \
+		I2C_HID_TOUCHPAD_MAX_HEIGHT >> 8, /*     Logical Maximum */   \
+		0x75, N_BITS(I2C_HID_TOUCHPAD_MAX_HEIGHT), /*     Report Size \
+							    */                \
+		0x81, 0x02, /*     Input (Data,Var,Abs) */                    \
+		0x09, 0x30, /*     Usage (Tip pressure) */                    \
+		0x26, I2C_HID_TOUCHPAD_MAX_PRESSURE & 0xff,                   \
+		I2C_HID_TOUCHPAD_MAX_PRESSURE >> 8, /*     Logical Maximum */ \
+		0x75, N_BITS(I2C_HID_TOUCHPAD_MAX_PRESSURE), /*     Report    \
+								Size */       \
+		0x81, 0x02, /*     Input (Data,Var,Abs) */                    \
+		0x09, 0x3f, /*     Usage (Azimuth Orientation) */             \
+		0x16, 0x00, 0x00, /*     Logical Minimum (0) */               \
+		0x26, I2C_HID_TOUCHPAD_MAX_ORIENTATION & 0xff,                \
+		I2C_HID_TOUCHPAD_MAX_ORIENTATION >> 8, /*     Logical Maximum \
+							*/                    \
+		0x75, N_BITS_ORIENTATION, /*     Report Size */               \
+		0x81, 0x02, /*     Input (Data,Var,Abs) */                    \
+		0xC0, /*   End Collection */
+
+	FINGER(1) FINGER(2) FINGER(3) FINGER(4) FINGER(5)
 
 #undef FINGER
 
-	0x05, 0x0D,			/*   Usage Page (Digitizer) */
-	0x85, REPORT_ID_DEVICE_CAPS,	/*   Report ID (Device Capabilities) */
-	0x09, 0x55,			/*   Usage (Contact Count Maximum) */
-	0x09, 0x59,			/*   Usage (Pad Type) */
-	0x75, 0x08,			/*   Report Size (8) */
-	0x95, 0x02,			/*   Report Count (2) */
-	0x25, 0x0F,			/*   Logical Maximum (15) */
-	0xB1, 0x02,			/*   Feature (Data,Var,Abs) */
-	0x06, 0x00, 0xFF,		/*   Usage Page (Vendor Defined) */
-	0x85, REPORT_ID_DEVICE_CERT,	/*   Report ID (Device Certification) */
-	0x09, 0xC5,			/*   Usage (Vendor Usage 0xC5) */
-	0x15, 0x00,			/*   Logical Minimum (0) */
-	0x26, 0xFF, 0x00,		/*   Logical Maximum (255) */
-	0x75, 0x08,			/*   Report Size (8) */
-	0x96, 0x00, 0x01,		/*   Report Count (256) */
-	0xB1, 0x02,			/*   Feature (Data,Var,Abs) */
-	0xC0,				/* End Collection */
+		0x05,
+	0x0D, /*   Usage Page (Digitizer) */
+	0x85, REPORT_ID_DEVICE_CAPS, /*   Report ID (Device Capabilities) */
+	0x09, 0x55, /*   Usage (Contact Count Maximum) */
+	0x09, 0x59, /*   Usage (Pad Type) */
+	0x75, 0x08, /*   Report Size (8) */
+	0x95, 0x02, /*   Report Count (2) */
+	0x25, 0x0F, /*   Logical Maximum (15) */
+	0xB1, 0x02, /*   Feature (Data,Var,Abs) */
+	0x06, 0x00, 0xFF, /*   Usage Page (Vendor Defined) */
+	0x85, REPORT_ID_DEVICE_CERT, /*   Report ID (Device Certification) */
+	0x09, 0xC5, /*   Usage (Vendor Usage 0xC5) */
+	0x15, 0x00, /*   Logical Minimum (0) */
+	0x26, 0xFF, 0x00, /*   Logical Maximum (255) */
+	0x75, 0x08, /*   Report Size (8) */
+	0x96, 0x00, 0x01, /*   Report Count (256) */
+	0xB1, 0x02, /*   Feature (Data,Var,Abs) */
+	0xC0, /* End Collection */
 
 	/* Configuration Collection */
-	0x05, 0x0D,			/* Usage Page (Digitizer) */
-	0x09, 0x0E,			/* Usage (Configuration) */
-	0xA1, 0x01,			/* Collection (Application) */
-	0x85, REPORT_ID_INPUT_MODE,	/*   Report ID (Input Mode) */
-	0x09, 0x22,			/*   Usage (Finger) */
-	0xA1, 0x02,			/*   Collection (Logical) */
-	0x09, 0x52,			/*     Usage (Input Mode) */
-	0x15, 0x00,			/*     Logical Minimum (0) */
-	0x25, 0x0F,			/*     Logical Maximum (15) */
-	0x75, 0x08,			/*     Report Size (8) */
-	0x95, 0x01,			/*     Report Count (1) */
-	0xB1, 0x02,			/*     Feature (Data,Var,Abs) */
-	0xC0,				/*   End Collection */
-	0x09, 0x22,			/*   Usage (Finger) */
-	0xA1, 0x00,			/*   Collection (Physical) */
-	0x85, REPORT_ID_REPORTING,	/*     Report ID (Selective Reporting)*/
-	0x09, 0x57,			/*     Usage (Surface Switch) */
-	0x09, 0x58,			/*     Usage (Button Switch) */
-	0x75, 0x04,			/*     Report Size (4) */
-	0x95, 0x02,			/*     Report Count (2) */
-	0x25, 0x01,			/*     Logical Maximum (1) */
-	0xB1, 0x02,			/*     Feature (Data,Var,Abs) */
-	0xC0,				/*   End Collection */
-	0xC0,				/* End Collection */
+	0x05, 0x0D, /* Usage Page (Digitizer) */
+	0x09, 0x0E, /* Usage (Configuration) */
+	0xA1, 0x01, /* Collection (Application) */
+	0x85, REPORT_ID_INPUT_MODE, /*   Report ID (Input Mode) */
+	0x09, 0x22, /*   Usage (Finger) */
+	0xA1, 0x02, /*   Collection (Logical) */
+	0x09, 0x52, /*     Usage (Input Mode) */
+	0x15, 0x00, /*     Logical Minimum (0) */
+	0x25, 0x0F, /*     Logical Maximum (15) */
+	0x75, 0x08, /*     Report Size (8) */
+	0x95, 0x01, /*     Report Count (1) */
+	0xB1, 0x02, /*     Feature (Data,Var,Abs) */
+	0xC0, /*   End Collection */
+	0x09, 0x22, /*   Usage (Finger) */
+	0xA1, 0x00, /*   Collection (Physical) */
+	0x85, REPORT_ID_REPORTING, /*     Report ID (Selective Reporting)*/
+	0x09, 0x57, /*     Usage (Surface Switch) */
+	0x09, 0x58, /*     Usage (Button Switch) */
+	0x75, 0x04, /*     Report Size (4) */
+	0x95, 0x02, /*     Report Count (2) */
+	0x25, 0x01, /*     Logical Maximum (1) */
+	0xB1, 0x02, /*     Feature (Data,Var,Abs) */
+	0xC0, /*   End Collection */
+	0xC0, /* End Collection */
 };
 
 static const uint8_t device_caps[] = {
-	I2C_HID_TOUCHPAD_MAX_FINGERS,	/* Contact Count Maximum */
-	0x00,				/* Pad Type: Depressible click-pad */
+	I2C_HID_TOUCHPAD_MAX_FINGERS, /* Contact Count Maximum */
+	0x00, /* Pad Type: Depressible click-pad */
 };
 
 /* A 256-byte default blob for the 'device certification status' feature report
  * expected by Windows.
  */
 static const uint8_t device_cert[] = {
-	0xFC, 0x28, 0xFE, 0x84, 0x40, 0xCB, 0x9A, 0x87,
-	0x0D, 0xBE, 0x57, 0x3C, 0xB6, 0x70, 0x09, 0x88,
-	0x07, 0x97, 0x2D, 0x2B, 0xE3, 0x38, 0x34, 0xB6,
-	0x6C, 0xED, 0xB0, 0xF7, 0xE5, 0x9C, 0xF6, 0xC2,
-	0x2E, 0x84, 0x1B, 0xE8, 0xB4, 0x51, 0x78, 0x43,
-	0x1F, 0x28, 0x4B, 0x7C, 0x2D, 0x53, 0xAF, 0xFC,
-	0x47, 0x70, 0x1B, 0x59, 0x6F, 0x74, 0x43, 0xC4,
-	0xF3, 0x47, 0x18, 0x53, 0x1A, 0xA2, 0xA1, 0x71,
-	0xC7, 0x95, 0x0E, 0x31, 0x55, 0x21, 0xD3, 0xB5,
-	0x1E, 0xE9, 0x0C, 0xBA, 0xEC, 0xB8, 0x89, 0x19,
-	0x3E, 0xB3, 0xAF, 0x75, 0x81, 0x9D, 0x53, 0xB9,
-	0x41, 0x57, 0xF4, 0x6D, 0x39, 0x25, 0x29, 0x7C,
-	0x87, 0xD9, 0xB4, 0x98, 0x45, 0x7D, 0xA7, 0x26,
-	0x9C, 0x65, 0x3B, 0x85, 0x68, 0x89, 0xD7, 0x3B,
-	0xBD, 0xFF, 0x14, 0x67, 0xF2, 0x2B, 0xF0, 0x2A,
-	0x41, 0x54, 0xF0, 0xFD, 0x2C, 0x66, 0x7C, 0xF8,
-	0xC0, 0x8F, 0x33, 0x13, 0x03, 0xF1, 0xD3, 0xC1,
-	0x0B, 0x89, 0xD9, 0x1B, 0x62, 0xCD, 0x51, 0xB7,
-	0x80, 0xB8, 0xAF, 0x3A, 0x10, 0xC1, 0x8A, 0x5B,
-	0xE8, 0x8A, 0x56, 0xF0, 0x8C, 0xAA, 0xFA, 0x35,
-	0xE9, 0x42, 0xC4, 0xD8, 0x55, 0xC3, 0x38, 0xCC,
-	0x2B, 0x53, 0x5C, 0x69, 0x52, 0xD5, 0xC8, 0x73,
-	0x02, 0x38, 0x7C, 0x73, 0xB6, 0x41, 0xE7, 0xFF,
-	0x05, 0xD8, 0x2B, 0x79, 0x9A, 0xE2, 0x34, 0x60,
-	0x8F, 0xA3, 0x32, 0x1F, 0x09, 0x78, 0x62, 0xBC,
-	0x80, 0xE3, 0x0F, 0xBD, 0x65, 0x20, 0x08, 0x13,
-	0xC1, 0xE2, 0xEE, 0x53, 0x2D, 0x86, 0x7E, 0xA7,
-	0x5A, 0xC5, 0xD3, 0x7D, 0x98, 0xBE, 0x31, 0x48,
-	0x1F, 0xFB, 0xDA, 0xAF, 0xA2, 0xA8, 0x6A, 0x89,
-	0xD6, 0xBF, 0xF2, 0xD3, 0x32, 0x2A, 0x9A, 0xE4,
-	0xCF, 0x17, 0xB7, 0xB8, 0xF4, 0xE1, 0x33, 0x08,
-	0x24, 0x8B, 0xC4, 0x43, 0xA5, 0xE5, 0x24, 0xC2,
+	0xFC, 0x28, 0xFE, 0x84, 0x40, 0xCB, 0x9A, 0x87, 0x0D, 0xBE, 0x57, 0x3C,
+	0xB6, 0x70, 0x09, 0x88, 0x07, 0x97, 0x2D, 0x2B, 0xE3, 0x38, 0x34, 0xB6,
+	0x6C, 0xED, 0xB0, 0xF7, 0xE5, 0x9C, 0xF6, 0xC2, 0x2E, 0x84, 0x1B, 0xE8,
+	0xB4, 0x51, 0x78, 0x43, 0x1F, 0x28, 0x4B, 0x7C, 0x2D, 0x53, 0xAF, 0xFC,
+	0x47, 0x70, 0x1B, 0x59, 0x6F, 0x74, 0x43, 0xC4, 0xF3, 0x47, 0x18, 0x53,
+	0x1A, 0xA2, 0xA1, 0x71, 0xC7, 0x95, 0x0E, 0x31, 0x55, 0x21, 0xD3, 0xB5,
+	0x1E, 0xE9, 0x0C, 0xBA, 0xEC, 0xB8, 0x89, 0x19, 0x3E, 0xB3, 0xAF, 0x75,
+	0x81, 0x9D, 0x53, 0xB9, 0x41, 0x57, 0xF4, 0x6D, 0x39, 0x25, 0x29, 0x7C,
+	0x87, 0xD9, 0xB4, 0x98, 0x45, 0x7D, 0xA7, 0x26, 0x9C, 0x65, 0x3B, 0x85,
+	0x68, 0x89, 0xD7, 0x3B, 0xBD, 0xFF, 0x14, 0x67, 0xF2, 0x2B, 0xF0, 0x2A,
+	0x41, 0x54, 0xF0, 0xFD, 0x2C, 0x66, 0x7C, 0xF8, 0xC0, 0x8F, 0x33, 0x13,
+	0x03, 0xF1, 0xD3, 0xC1, 0x0B, 0x89, 0xD9, 0x1B, 0x62, 0xCD, 0x51, 0xB7,
+	0x80, 0xB8, 0xAF, 0x3A, 0x10, 0xC1, 0x8A, 0x5B, 0xE8, 0x8A, 0x56, 0xF0,
+	0x8C, 0xAA, 0xFA, 0x35, 0xE9, 0x42, 0xC4, 0xD8, 0x55, 0xC3, 0x38, 0xCC,
+	0x2B, 0x53, 0x5C, 0x69, 0x52, 0xD5, 0xC8, 0x73, 0x02, 0x38, 0x7C, 0x73,
+	0xB6, 0x41, 0xE7, 0xFF, 0x05, 0xD8, 0x2B, 0x79, 0x9A, 0xE2, 0x34, 0x60,
+	0x8F, 0xA3, 0x32, 0x1F, 0x09, 0x78, 0x62, 0xBC, 0x80, 0xE3, 0x0F, 0xBD,
+	0x65, 0x20, 0x08, 0x13, 0xC1, 0xE2, 0xEE, 0x53, 0x2D, 0x86, 0x7E, 0xA7,
+	0x5A, 0xC5, 0xD3, 0x7D, 0x98, 0xBE, 0x31, 0x48, 0x1F, 0xFB, 0xDA, 0xAF,
+	0xA2, 0xA8, 0x6A, 0x89, 0xD6, 0xBF, 0xF2, 0xD3, 0x32, 0x2A, 0x9A, 0xE4,
+	0xCF, 0x17, 0xB7, 0xB8, 0xF4, 0xE1, 0x33, 0x08, 0x24, 0x8B, 0xC4, 0x43,
+	0xA5, 0xE5, 0x24, 0xC2,
 };
 
 #define MAX_SIZEOF(a, b) (sizeof(a) > sizeof(b) ? sizeof(a) : sizeof(b))
@@ -431,7 +409,7 @@ static bool pending_probe;
 static bool pending_reset;
 
 /* Reports (double buffered) */
-#define MAX_REPORT_CNT	2
+#define MAX_REPORT_CNT 2
 
 static struct touch_report touch_reports[MAX_REPORT_CNT];
 static struct mouse_report mouse_reports[MAX_REPORT_CNT];
@@ -448,8 +426,8 @@ static uint8_t input_mode;
  * |reporting.button_switch|, respectively.
  */
 struct selective_reporting {
-	uint8_t surface_switch:4;
-	uint8_t button_switch:4;
+	uint8_t surface_switch : 4;
+	uint8_t button_switch : 4;
 } __packed;
 
 static struct selective_reporting reporting;
@@ -568,7 +546,7 @@ int i2c_hid_touchpad_process(unsigned int len, uint8_t *buffer,
 		break;
 	case I2C_HID_COMMAND_REGISTER:
 		*cmd = i2c_hid_touchpad_command_process(len, buffer,
-						       send_response, data);
+							send_response, data);
 		break;
 	default:
 		/* Unknown register has been received. */
@@ -697,9 +675,9 @@ void i2c_hid_compile_report(struct touchpad_event *event)
 			touch->finger[i].pressure = event->finger[i].pressure;
 			if (event->finger[i].is_palm)
 				touch->finger[i].pressure =
-						I2C_HID_TOUCHPAD_MAX_PRESSURE;
+					I2C_HID_TOUCHPAD_MAX_PRESSURE;
 			touch->finger[i].orientation =
-					event->finger[i].orientation;
+				event->finger[i].orientation;
 			contact_num++;
 		} else if (touch_old->finger[i].tip) {
 			/*
diff --git a/common/i2c_peripheral.c b/common/i2c_peripheral.c
index ebc7167f8d..3aa1951b91 100644
--- a/common/i2c_peripheral.c
+++ b/common/i2c_peripheral.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -29,6 +29,5 @@ static enum ec_status i2c_get_protocol_info(struct host_cmd_handler_args *args)
 
 	return EC_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO,
-		     i2c_get_protocol_info,
+DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, i2c_get_protocol_info,
 		     EC_VER_MASK(0));
diff --git a/common/i2c_trace.c b/common/i2c_trace.c
index af65d85210..c7207698b7 100644
--- a/common/i2c_trace.c
+++ b/common/i2c_trace.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,8 @@
 #include "util.h"
 
 #define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args)
 
 struct i2c_trace_range {
 	bool enabled;
@@ -23,18 +23,17 @@ struct i2c_trace_range {
 
 static struct i2c_trace_range trace_entries[8];
 
-void i2c_trace_notify(int port, uint16_t addr_flags,
-		      const uint8_t *out_data, size_t out_size,
-		      const uint8_t *in_data, size_t in_size, int ret)
+void i2c_trace_notify(int port, uint16_t addr_flags, const uint8_t *out_data,
+		      size_t out_size, const uint8_t *in_data, size_t in_size,
+		      int ret)
 {
 	size_t i;
 	uint16_t addr = I2C_STRIP_FLAGS(addr_flags);
 
 	for (i = 0; i < ARRAY_SIZE(trace_entries); i++)
-		if (trace_entries[i].enabled
-		    && trace_entries[i].port == port
-		    && trace_entries[i].addr_lo <= addr
-		    && trace_entries[i].addr_hi >= addr)
+		if (trace_entries[i].enabled && trace_entries[i].port == port &&
+		    trace_entries[i].addr_lo <= addr &&
+		    trace_entries[i].addr_hi >= addr)
 			goto trace_enabled;
 	return;
 
@@ -66,19 +65,16 @@ static int command_i2ctrace_list(void)
 	for (i = 0; i < ARRAY_SIZE(trace_entries); i++) {
 		if (trace_entries[i].enabled) {
 			i2c_port = get_i2c_port(trace_entries[i].port);
-			ccprintf("%-2zd %d %-8s 0x%X",
-				 i,
-				 trace_entries[i].port,
+			ccprintf("%-2zd %d %-8s 0x%X", i, trace_entries[i].port,
 #ifndef CONFIG_ZEPHYR
 				 i2c_port->name,
 #else
 				 "",
 #endif /* CONFIG_ZEPHYR */
 				 trace_entries[i].addr_lo);
-			if (trace_entries[i].addr_hi
-			    != trace_entries[i].addr_lo)
-				ccprintf(" to 0x%X",
-					 trace_entries[i].addr_hi);
+			if (trace_entries[i].addr_hi !=
+			    trace_entries[i].addr_lo)
+				ccprintf(" to 0x%X", trace_entries[i].addr_hi);
 			ccprintf("\n");
 		}
 	}
@@ -95,8 +91,7 @@ static int command_i2ctrace_disable(size_t id)
 	return EC_SUCCESS;
 }
 
-static int command_i2ctrace_enable(int port, int addr_lo,
-				   int addr_hi)
+static int command_i2ctrace_enable(int port, int addr_lo, int addr_hi)
 {
 	struct i2c_trace_range *t;
 	struct i2c_trace_range *new_entry = NULL;
@@ -111,41 +106,34 @@ static int command_i2ctrace_enable(int port, int addr_lo,
 	 * Scan thru existing entries to see if there is one we can
 	 * extend instead of making a new entry
 	 */
-	for (t = trace_entries;
-	     t < trace_entries + ARRAY_SIZE(trace_entries);
+	for (t = trace_entries; t < trace_entries + ARRAY_SIZE(trace_entries);
 	     t++) {
 		if (t->enabled && t->port == port) {
 			/* Subset of existing range, do nothing */
-			if (t->addr_lo <= addr_lo &&
-			    t->addr_hi >= addr_hi)
+			if (t->addr_lo <= addr_lo && t->addr_hi >= addr_hi)
 				return EC_SUCCESS;
 
 			/* Extends exising range on both directions, replace */
-			if (t->addr_lo >= addr_lo &&
-			    t->addr_hi <= addr_hi) {
+			if (t->addr_lo >= addr_lo && t->addr_hi <= addr_hi) {
 				t->enabled = 0;
-				return command_i2ctrace_enable(
-					port, addr_lo, addr_hi);
+				return command_i2ctrace_enable(port, addr_lo,
+							       addr_hi);
 			}
 
 			/* Extends existing range below */
 			if (t->addr_lo - 1 <= addr_hi &&
 			    t->addr_hi >= addr_hi) {
 				t->enabled = 0;
-				return command_i2ctrace_enable(
-					port,
-					addr_lo,
-					t->addr_hi);
+				return command_i2ctrace_enable(port, addr_lo,
+							       t->addr_hi);
 			}
 
 			/* Extends existing range above */
 			if (t->addr_lo <= addr_lo &&
 			    t->addr_hi + 1 >= addr_lo) {
 				t->enabled = 0;
-				return command_i2ctrace_enable(
-					port,
-					t->addr_lo,
-					addr_hi);
+				return command_i2ctrace_enable(port, t->addr_lo,
+							       addr_hi);
 			}
 		} else if (!t->enabled && !new_entry) {
 			new_entry = t;
@@ -165,8 +153,7 @@ static int command_i2ctrace_enable(int port, int addr_lo,
 	return EC_ERROR_MEMORY_ALLOCATION;
 }
 
-
-static int command_i2ctrace(int argc, char **argv)
+static int command_i2ctrace(int argc, const char **argv)
 {
 	int id_or_port;
 	int address_low;
@@ -204,14 +191,13 @@ static int command_i2ctrace(int argc, char **argv)
 			return EC_ERROR_PARAM_COUNT;
 		}
 
-		return command_i2ctrace_enable(
-			id_or_port, address_low, address_high);
+		return command_i2ctrace_enable(id_or_port, address_low,
+					       address_high);
 	}
 
 	return EC_ERROR_PARAM1;
 }
-DECLARE_CONSOLE_COMMAND(i2ctrace,
-			command_i2ctrace,
+DECLARE_CONSOLE_COMMAND(i2ctrace, command_i2ctrace,
 			"[list | disable <id> | enable <port> <address> | "
 			"enable <port> <address-low> <address-high>]",
 			"Trace I2C transactions");
diff --git a/common/i2c_wedge.c b/common/i2c_wedge.c
index fc0a5132b7..ff8c5d494f 100644
--- a/common/i2c_wedge.c
+++ b/common/i2c_wedge.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -199,8 +199,7 @@ static void i2c_bang_xfer(int addr, int reg)
 	ccprintf("  read byte: %d\n", byte);
 }
 
-static void i2c_bang_wedge_write(int addr, int byte, int bit_count,
-	int reboot)
+static void i2c_bang_wedge_write(int addr, int byte, int bit_count, int reboot)
 {
 	int i;
 
@@ -219,8 +218,7 @@ static void i2c_bang_wedge_write(int addr, int byte, int bit_count,
 		system_reset(0);
 }
 
-static void i2c_bang_wedge_read(int addr, int reg, int bit_count,
-	int reboot)
+static void i2c_bang_wedge_read(int addr, int reg, int bit_count, int reboot)
 {
 	int i;
 
@@ -244,11 +242,11 @@ static void i2c_bang_wedge_read(int addr, int reg, int bit_count,
 		system_reset(0);
 }
 
-#define WEDGE_WRITE	1
-#define WEDGE_READ	2
-#define WEDGE_REBOOT	4
+#define WEDGE_WRITE 1
+#define WEDGE_READ 2
+#define WEDGE_REBOOT 4
 
-static int command_i2c_wedge(int argc, char **argv)
+static int command_i2c_wedge(int argc, const char **argv)
 {
 	int addr, reg, wedge_flag = 0, wedge_bit_count = -1;
 	char *e;
@@ -256,17 +254,17 @@ static int command_i2c_wedge(int argc, char **argv)
 
 	/* Verify that the I2C_PORT_HOST has SDA and SCL pins defined. */
 	if (get_sda_from_i2c_port(I2C_PORT_HOST, &tmp) != EC_SUCCESS ||
-		get_scl_from_i2c_port(I2C_PORT_HOST, &tmp) != EC_SUCCESS) {
+	    get_scl_from_i2c_port(I2C_PORT_HOST, &tmp) != EC_SUCCESS) {
 		ccprintf("Cannot wedge bus because no SCL and SDA pins are"
-			"defined for this port. Check i2c_ports[].\n");
+			 "defined for this port. Check i2c_ports[].\n");
 		return EC_SUCCESS;
 	}
 
 	if (argc < 3) {
 		ccputs("Usage: i2cwedge addr out_byte "
-			"[wedge_flag [wedge_bit_count]]\n");
+		       "[wedge_flag [wedge_bit_count]]\n");
 		ccputs("  wedge_flag - (1: wedge out; 2: wedge in;"
-			" 5: wedge out+reboot; 6: wedge in+reboot)]\n");
+		       " 5: wedge out+reboot; 6: wedge in+reboot)]\n");
 		ccputs("  wedge_bit_count - 0 to 8\n");
 		return EC_ERROR_UNKNOWN;
 	}
@@ -302,12 +300,12 @@ static int command_i2c_wedge(int argc, char **argv)
 		if (wedge_bit_count < 0)
 			wedge_bit_count = 8;
 		i2c_bang_wedge_write(addr, reg, wedge_bit_count,
-			(wedge_flag & WEDGE_REBOOT));
+				     (wedge_flag & WEDGE_REBOOT));
 	} else if (wedge_flag & WEDGE_READ) {
 		if (wedge_bit_count < 0)
 			wedge_bit_count = 2;
 		i2c_bang_wedge_read(addr, reg, wedge_bit_count,
-			(wedge_flag & WEDGE_REBOOT));
+				    (wedge_flag & WEDGE_REBOOT));
 	} else {
 		i2c_bang_xfer(addr, reg);
 	}
@@ -326,15 +324,14 @@ static int command_i2c_wedge(int argc, char **argv)
 }
 DECLARE_CONSOLE_COMMAND(i2cwedge, command_i2c_wedge,
 			"i2cwedge addr out_byte "
-				"[wedge_flag [wedge_bit_count]]",
+			"[wedge_flag [wedge_bit_count]]",
 			"Wedge host I2C bus");
 
-static int command_i2c_unwedge(int argc, char **argv)
+static int command_i2c_unwedge(int argc, const char **argv)
 {
 	i2c_unwedge(I2C_PORT_HOST);
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(i2cunwedge, command_i2c_unwedge,
-	"",
-	"Unwedge host I2C bus");
+DECLARE_CONSOLE_COMMAND(i2cunwedge, command_i2c_unwedge, "",
+			"Unwedge host I2C bus");
diff --git a/common/inductive_charging.c b/common/inductive_charging.c
index 793f535afe..9700e37dcc 100644
--- a/common/inductive_charging.c
+++ b/common/inductive_charging.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/common/init_rom.c b/common/init_rom.c
index 2cee57f922..102c3a00ae 100644
--- a/common/init_rom.c
+++ b/common/init_rom.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/common/ioexpander.c b/common/ioexpander.c
index 2bed1039f4..0a08f37c46 100644
--- a/common/ioexpander.c
+++ b/common/ioexpander.c
@@ -1,18 +1,19 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* IO Expander Controller Common Code */
 
+#include "builtin/assert.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "ioexpander.h"
 #include "system.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_GPIO, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_GPIO, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
 
 int signal_is_ioex(int signal)
 {
@@ -68,7 +69,7 @@ int ioex_enable_interrupt(enum ioex_signal signal)
 
 	rv = ioex_is_valid_interrupt_signal(signal);
 	if (rv != EC_SUCCESS)
-		return  rv;
+		return rv;
 
 	drv = ioex_config[g->ioex].drv;
 	return drv->enable_interrupt(g->ioex, g->port, g->mask, 1);
@@ -82,7 +83,7 @@ int ioex_disable_interrupt(enum ioex_signal signal)
 
 	rv = ioex_is_valid_interrupt_signal(signal);
 	if (rv != EC_SUCCESS)
-		return  rv;
+		return rv;
 
 	drv = ioex_config[g->ioex].drv;
 	return drv->enable_interrupt(g->ioex, g->port, g->mask, 0);
@@ -107,8 +108,8 @@ int ioex_get_flags(enum ioex_signal signal, int *flags)
 	if (g == NULL)
 		return EC_ERROR_BUSY;
 
-	return ioex_config[g->ioex].drv->get_flags_by_mask(g->ioex,
-						g->port, g->mask, flags);
+	return ioex_config[g->ioex].drv->get_flags_by_mask(g->ioex, g->port,
+							   g->mask, flags);
 }
 
 int ioex_set_flags(enum ioex_signal signal, int flags)
@@ -118,8 +119,8 @@ int ioex_set_flags(enum ioex_signal signal, int flags)
 	if (g == NULL)
 		return EC_ERROR_BUSY;
 
-	return ioex_config[g->ioex].drv->set_flags_by_mask(g->ioex,
-						g->port, g->mask, flags);
+	return ioex_config[g->ioex].drv->set_flags_by_mask(g->ioex, g->port,
+							   g->mask, flags);
 }
 
 int ioex_get_level(enum ioex_signal signal, int *val)
@@ -129,8 +130,8 @@ int ioex_get_level(enum ioex_signal signal, int *val)
 	if (g == NULL)
 		return EC_ERROR_BUSY;
 
-	return ioex_config[g->ioex].drv->get_level(g->ioex, g->port,
-							g->mask, val);
+	return ioex_config[g->ioex].drv->get_level(g->ioex, g->port, g->mask,
+						   val);
 }
 
 int ioex_set_level(enum ioex_signal signal, int value)
@@ -140,8 +141,8 @@ int ioex_set_level(enum ioex_signal signal, int value)
 	if (g == NULL)
 		return EC_ERROR_BUSY;
 
-	return ioex_config[g->ioex].drv->set_level(g->ioex, g->port,
-							g->mask, value);
+	return ioex_config[g->ioex].drv->set_level(g->ioex, g->port, g->mask,
+						   value);
 }
 
 #ifdef CONFIG_IO_EXPANDER_SUPPORT_GET_PORT
@@ -198,7 +199,7 @@ int ioex_restore_gpio_state(int ioex, const int *state, int state_len)
 		}
 
 		rv = drv->set_flags_by_mask(g->ioex, g->port, g->mask,
-				       state[state_offset++]);
+					    state[state_offset++]);
 		if (rv) {
 			CPRINTS("%s failed to set flags rv=%d", __func__, rv);
 			return rv;
@@ -233,8 +234,8 @@ int ioex_init(int ioex)
 			if (system_jumped_late())
 				flags &= ~(GPIO_LOW | GPIO_HIGH);
 
-			drv->set_flags_by_mask(g->ioex, g->port,
-						g->mask, flags);
+			drv->set_flags_by_mask(g->ioex, g->port, g->mask,
+					       flags);
 		}
 	}
 
@@ -253,8 +254,8 @@ static void ioex_init_default(void)
 		 * If the IO Expander has been initialized or if the default
 		 * initialization is disabled, skip initializing.
 		 */
-		if (ioex_config[i].flags & (IOEX_FLAGS_INITIALIZED |
-					IOEX_FLAGS_DEFAULT_INIT_DISABLED))
+		if (ioex_config[i].flags &
+		    (IOEX_FLAGS_INITIALIZED | IOEX_FLAGS_DEFAULT_INIT_DISABLED))
 			continue;
 
 		ioex_init(i);
diff --git a/common/ioexpander_commands.c b/common/ioexpander_commands.c
index a09337ea88..38ab82565a 100644
--- a/common/ioexpander_commands.c
+++ b/common/ioexpander_commands.c
@@ -1,7 +1,9 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
+
+#include "builtin/assert.h"
 #include "console.h"
 #include "gpio.h"
 #include "ioexpander.h"
@@ -69,14 +71,13 @@ static void print_ioex_info(enum ioex_signal signal)
 
 	changed = last_val_changed(signal, val);
 
-	ccprintf("  %d%c %s%s%s%s%s%s\n", val,
-		 (changed ? '*' : ' '),
+	ccprintf("  %d%c %s%s%s%s%s%s\n", val, (changed ? '*' : ' '),
 		 (flags & GPIO_INPUT ? "I " : ""),
 		 (flags & GPIO_OUTPUT ? "O " : ""),
 		 (flags & GPIO_LOW ? "L " : ""),
 		 (flags & GPIO_HIGH ? "H " : ""),
 		 (flags & GPIO_OPEN_DRAIN ? "ODR " : ""),
-		ioex_get_name(signal));
+		 ioex_get_name(signal));
 
 	/* Flush console to avoid truncating output */
 	cflush();
@@ -99,7 +100,7 @@ static enum ec_error_list ioex_set(const char *name, int value)
 	return ioex_set_level(signal, value);
 }
 
-static int command_ioex_set(int argc, char **argv)
+static int command_ioex_set(int argc, const char **argv)
 {
 	char *e;
 	int v;
@@ -116,11 +117,10 @@ static int command_ioex_set(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(ioexset, command_ioex_set,
-			"name <0 | 1>",
+DECLARE_CONSOLE_COMMAND(ioexset, command_ioex_set, "name <0 | 1>",
 			"Set level of a IO expander pin");
 
-static int command_ioex_get(int argc, char **argv)
+static int command_ioex_get(int argc, const char **argv)
 {
 	enum ioex_signal signal;
 
@@ -140,6 +140,5 @@ static int command_ioex_get(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_SAFE_CONSOLE_COMMAND(ioexget, command_ioex_get,
-			     "[name]",
+DECLARE_SAFE_CONSOLE_COMMAND(ioexget, command_ioex_get, "[name]",
 			     "Read level of IO expander pin(s)");
diff --git a/common/irq_locking.c b/common/irq_locking.c
index 3606b7aa15..1146145c5e 100644
--- a/common/irq_locking.c
+++ b/common/irq_locking.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/common/kasa.c b/common/kasa.c
index 79c75ad55b..6b974dc574 100644
--- a/common/kasa.c
+++ b/common/kasa.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/common/keyboard_8042.c b/common/keyboard_8042.c
index 755b26f360..e0371ddd5c 100644
--- a/common/keyboard_8042.c
+++ b/common/keyboard_8042.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -6,6 +6,7 @@
  */
 
 #include "button.h"
+#include "builtin/assert.h"
 #include "chipset.h"
 #include "common.h"
 #include "console.h"
@@ -13,6 +14,7 @@
 #include "hooks.h"
 #include "host_command.h"
 #include "i8042_protocol.h"
+#include "atkbd_protocol.h"
 #include "keyboard_8042_sharedlib.h"
 #include "keyboard_config.h"
 #include "keyboard_protocol.h"
@@ -28,11 +30,11 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_KEYBOARD, outstr)
-#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ##args)
 
 #ifdef CONFIG_KEYBOARD_DEBUG
 #define CPUTS5(outstr) cputs(CC_KEYBOARD, outstr)
-#define CPRINTS5(format, args...) cprints(CC_KEYBOARD, format, ## args)
+#define CPRINTS5(format, args...) cprints(CC_KEYBOARD, format, ##args)
 #else
 #define CPUTS5(outstr)
 #define CPRINTS5(format, args...)
@@ -44,23 +46,23 @@
  * #define CMD_KEYBOARD_LOG IS_ENABLED(CONFIG_MALLOC)
  */
 #ifdef CONFIG_MALLOC
-#define CMD_KEYBOARD_LOG	1
+#define CMD_KEYBOARD_LOG 1
 #else
-#define CMD_KEYBOARD_LOG	0
+#define CMD_KEYBOARD_LOG 0
 #endif
 
 static enum {
-	STATE_NORMAL = 0,
-	STATE_SCANCODE,
-	STATE_SETLEDS,
-	STATE_EX_SETLEDS_1,		/* Expect 2-byte parameter */
-	STATE_EX_SETLEDS_2,
-	STATE_WRITE_CMD_BYTE,
-	STATE_WRITE_OUTPUT_PORT,
-	STATE_ECHO_MOUSE,
-	STATE_SETREP,
-	STATE_SEND_TO_MOUSE,
-} data_port_state = STATE_NORMAL;
+	STATE_ATKBD_CMD = 0,
+	STATE_ATKBD_SCANCODE,
+	STATE_ATKBD_SETLEDS,
+	STATE_ATKBD_EX_SETLEDS_1, /* Expect 2-byte parameter */
+	STATE_ATKBD_EX_SETLEDS_2,
+	STATE_8042_WRITE_CMD_BYTE,
+	STATE_8042_WRITE_OUTPUT_PORT,
+	STATE_8042_ECHO_MOUSE,
+	STATE_ATKBD_SETREP,
+	STATE_8042_SEND_TO_MOUSE,
+} data_port_state = STATE_ATKBD_CMD;
 
 enum scancode_set_list {
 	SCANCODE_GET_SET = 0,
@@ -123,9 +125,9 @@ static int i8042_keyboard_irq_enabled;
 static int i8042_aux_irq_enabled;
 
 /* i8042 global settings */
-static int keyboard_enabled;	/* default the keyboard is disabled. */
-static int aux_chan_enabled;	/* default the mouse is disabled. */
-static int keystroke_enabled;	/* output keystrokes */
+static int keyboard_enabled; /* default the keyboard is disabled. */
+static int aux_chan_enabled; /* default the mouse is disabled. */
+static int keystroke_enabled; /* output keystrokes */
 static uint8_t resend_command[MAX_SCAN_CODE_LEN];
 static uint8_t resend_command_len;
 static uint8_t controller_ram_address;
@@ -157,11 +159,11 @@ static enum scancode_set_list scancode_set = SCANCODE_SET_2;
 static uint8_t typematic_value_from_host;
 static int typematic_first_delay;
 static int typematic_inter_delay;
-static int typematic_len;  /* length of typematic_scan_code */
+static int typematic_len; /* length of typematic_scan_code */
 static uint8_t typematic_scan_code[MAX_SCAN_CODE_LEN];
 static timestamp_t typematic_deadline;
 
-#define KB_SYSJUMP_TAG 0x4b42  /* "KB" */
+#define KB_SYSJUMP_TAG 0x4b42 /* "KB" */
 #define KB_HOOK_VERSION 2
 /* the previous keyboard state before reboot_ec. */
 struct kb_state {
@@ -174,7 +176,7 @@ struct kb_state {
 /* Keyboard event log */
 
 /* Log the traffic between EC and host -- for debug only */
-#define MAX_KBLOG 512  /* Max events in keyboard log */
+#define MAX_KBLOG 512 /* Max events in keyboard log */
 
 struct kblog_t {
 	/*
@@ -202,8 +204,8 @@ struct kblog_t {
 	uint8_t byte;
 };
 
-static struct kblog_t *kblog_buf;	/* Log buffer; NULL if not logging */
-static int kblog_len;			/* Current log length */
+static struct kblog_t *kblog_buf; /* Log buffer; NULL if not logging */
+static int kblog_len; /* Current log length */
 
 /**
  * Add event to keyboard log.
@@ -266,8 +268,8 @@ static void aux_enable_irq(int enable)
  * @param to_host	Data to send
  * @param chan		Channel to send data on
  */
-static void i8042_send_to_host(int len, const uint8_t *bytes,
-			       uint8_t chan)
+static void i8042_send_to_host(int len, const uint8_t *bytes, uint8_t chan,
+			       int is_typematic)
 {
 	int i;
 	struct data_byte data;
@@ -275,15 +277,20 @@ static void i8042_send_to_host(int len, const uint8_t *bytes,
 	/* Enqueue output data if there's space */
 	mutex_lock(&to_host_mutex);
 
-	for (i = 0; i < len; i++)
-		kblog_put(chan == CHAN_AUX ? 'a' : 's', bytes[i]);
-
-	if (queue_space(&to_host) >= len) {
-		kblog_put('t', to_host.state->tail);
-		for (i = 0; i < len; i++) {
-			data.chan = chan;
-			data.byte = bytes[i];
-			queue_add_unit(&to_host, &data);
+	if (is_typematic && !typematic_len) {
+		for (i = 0; i < len; i++)
+			kblog_put('r', bytes[i]);
+	} else {
+		for (i = 0; i < len; i++)
+			kblog_put(chan == CHAN_AUX ? 'a' : 's', bytes[i]);
+
+		if (queue_space(&to_host) >= len) {
+			kblog_put('t', to_host.state->tail);
+			for (i = 0; i < len; i++) {
+				data.chan = chan;
+				data.byte = bytes[i];
+				queue_add_unit(&to_host, &data);
+			}
 		}
 	}
 	mutex_unlock(&to_host_mutex);
@@ -364,8 +371,8 @@ static enum ec_error_list matrix_callback(int8_t row, int8_t col,
 
 #ifdef CONFIG_KEYBOARD_SCANCODE_CALLBACK
 	{
-		enum ec_error_list r = keyboard_scancode_callback(
-				&make_code, pressed);
+		enum ec_error_list r =
+			keyboard_scancode_callback(&make_code, pressed);
 		if (r != EC_SUCCESS)
 			return r;
 	}
@@ -392,10 +399,10 @@ static enum ec_error_list matrix_callback(int8_t row, int8_t col,
 static void set_typematic_delays(uint8_t data)
 {
 	typematic_value_from_host = data;
-	typematic_first_delay = MSEC *
-		(((typematic_value_from_host & 0x60) >> 5) + 1) * 250;
-	typematic_inter_delay = SECOND *
-		(1 << ((typematic_value_from_host & 0x18) >> 3)) *
+	typematic_first_delay =
+		MSEC * (((typematic_value_from_host & 0x60) >> 5) + 1) * 250;
+	typematic_inter_delay =
+		SECOND * (1 << ((typematic_value_from_host & 0x18) >> 3)) *
 		((typematic_value_from_host & 0x7) + 8) / 240;
 }
 
@@ -442,7 +449,8 @@ void keyboard_state_changed(int row, int col, int is_pressed)
 
 	if (mylabel & KEYCAP_LONG_LABEL_BIT)
 		CPRINTS("KB (%d,%d)=%d %s", row, col, is_pressed,
-			get_keycap_long_label(mylabel & KEYCAP_LONG_LABEL_INDEX_BITMASK));
+			get_keycap_long_label(mylabel &
+					      KEYCAP_LONG_LABEL_INDEX_BITMASK));
 	else
 		CPRINTS("KB (%d,%d)=%d %c", row, col, is_pressed, mylabel);
 #endif
@@ -452,7 +460,7 @@ void keyboard_state_changed(int row, int col, int is_pressed)
 	if (ret == EC_SUCCESS) {
 		ASSERT(len > 0);
 		if (keystroke_enabled)
-			i8042_send_to_host(len, scan_code, CHAN_KBD);
+			i8042_send_to_host(len, scan_code, CHAN_KBD, 0);
 	}
 
 	if (is_pressed) {
@@ -516,8 +524,8 @@ static void update_ctl_ram(uint8_t addr, uint8_t data)
 
 	orig = controller_ram[addr];
 	controller_ram[addr] = data;
-	CPRINTS5("KB set CTR_RAM(0x%02x)=0x%02x (old:0x%02x)",
-		 addr, data, orig);
+	CPRINTS5("KB set CTR_RAM(0x%02x)=0x%02x (old:0x%02x)", addr, data,
+		 orig);
 
 	if (addr == 0x00) {
 		/* Keyboard enable/disable */
@@ -555,19 +563,19 @@ static int handle_mouse_data(uint8_t data, uint8_t *output, int *count)
 	int out_len = 0;
 
 	switch (data_port_state) {
-	case STATE_ECHO_MOUSE:
-		CPRINTS5("STATE_ECHO_MOUSE: 0x%02x", data);
+	case STATE_8042_ECHO_MOUSE:
+		CPRINTS5("STATE_8042_ECHO_MOUSE: 0x%02x", data);
 		output[out_len++] = data;
-		data_port_state = STATE_NORMAL;
+		data_port_state = STATE_ATKBD_CMD;
 		break;
 
-	case STATE_SEND_TO_MOUSE:
-		CPRINTS5("STATE_SEND_TO_MOUSE: 0x%02x", data);
+	case STATE_8042_SEND_TO_MOUSE:
+		CPRINTS5("STATE_8042_SEND_TO_MOUSE: 0x%02x", data);
 		send_aux_data_to_device(data);
-		data_port_state = STATE_NORMAL;
+		data_port_state = STATE_ATKBD_CMD;
 		break;
 
-	default:  /* STATE_NORMAL */
+	default: /* STATE_ATKBD_CMD */
 		return 0;
 	}
 
@@ -590,120 +598,119 @@ static int handle_keyboard_data(uint8_t data, uint8_t *output)
 	int i;
 
 	switch (data_port_state) {
-	case STATE_SCANCODE:
-		CPRINTS5("KB eaten by STATE_SCANCODE: 0x%02x", data);
+	case STATE_ATKBD_SCANCODE:
+		CPRINTS5("KB eaten by STATE_ATKBD_SCANCODE: 0x%02x", data);
 		if (data == SCANCODE_GET_SET) {
-			output[out_len++] = I8042_RET_ACK;
+			output[out_len++] = ATKBD_RET_ACK;
 			output[out_len++] = scancode_set;
 		} else {
 			scancode_set = data;
 			CPRINTS("KB scancode set to %d", scancode_set);
-			output[out_len++] = I8042_RET_ACK;
+			output[out_len++] = ATKBD_RET_ACK;
 		}
-		data_port_state = STATE_NORMAL;
+		data_port_state = STATE_ATKBD_CMD;
 		break;
 
-	case STATE_SETLEDS:
-		CPRINTS5("KB eaten by STATE_SETLEDS");
-		output[out_len++] = I8042_RET_ACK;
-		data_port_state = STATE_NORMAL;
+	case STATE_ATKBD_SETLEDS:
+		CPRINTS5("KB eaten by STATE_ATKBD_SETLEDS");
+		output[out_len++] = ATKBD_RET_ACK;
+		data_port_state = STATE_ATKBD_CMD;
 		break;
 
-	case STATE_EX_SETLEDS_1:
-		CPRINTS5("KB eaten by STATE_EX_SETLEDS_1");
-		output[out_len++] = I8042_RET_ACK;
-		data_port_state = STATE_EX_SETLEDS_2;
+	case STATE_ATKBD_EX_SETLEDS_1:
+		CPRINTS5("KB eaten by STATE_ATKBD_EX_SETLEDS_1");
+		output[out_len++] = ATKBD_RET_ACK;
+		data_port_state = STATE_ATKBD_EX_SETLEDS_2;
 		break;
 
-	case STATE_EX_SETLEDS_2:
-		CPRINTS5("KB eaten by STATE_EX_SETLEDS_2");
-		output[out_len++] = I8042_RET_ACK;
-		data_port_state = STATE_NORMAL;
+	case STATE_ATKBD_EX_SETLEDS_2:
+		CPRINTS5("KB eaten by STATE_ATKBD_EX_SETLEDS_2");
+		output[out_len++] = ATKBD_RET_ACK;
+		data_port_state = STATE_ATKBD_CMD;
 		break;
 
-	case STATE_WRITE_CMD_BYTE:
-		CPRINTS5("KB eaten by STATE_WRITE_CMD_BYTE: 0x%02x",
-			 data);
+	case STATE_8042_WRITE_CMD_BYTE:
+		CPRINTS5("KB eaten by STATE_8042_WRITE_CMD_BYTE: 0x%02x", data);
 		update_ctl_ram(controller_ram_address, data);
-		data_port_state = STATE_NORMAL;
+		data_port_state = STATE_ATKBD_CMD;
 		break;
 
-	case STATE_WRITE_OUTPUT_PORT:
-		CPRINTS5("KB eaten by STATE_WRITE_OUTPUT_PORT: 0x%02x",
+	case STATE_8042_WRITE_OUTPUT_PORT:
+		CPRINTS5("KB eaten by STATE_8042_WRITE_OUTPUT_PORT: 0x%02x",
 			 data);
 		A20_status = (data & BIT(1)) ? 1 : 0;
-		data_port_state = STATE_NORMAL;
+		data_port_state = STATE_ATKBD_CMD;
 		break;
 
-	case STATE_SETREP:
-		CPRINTS5("KB eaten by STATE_SETREP: 0x%02x", data);
+	case STATE_ATKBD_SETREP:
+		CPRINTS5("KB eaten by STATE_ATKBD_SETREP: 0x%02x", data);
 		set_typematic_delays(data);
 
-		output[out_len++] = I8042_RET_ACK;
-		data_port_state = STATE_NORMAL;
+		output[out_len++] = ATKBD_RET_ACK;
+		data_port_state = STATE_ATKBD_CMD;
 		break;
 
-	default:  /* STATE_NORMAL */
+	default: /* STATE_ATKBD_CMD */
 		switch (data) {
-		case I8042_CMD_GSCANSET:  /* also I8042_CMD_SSCANSET */
-			output[out_len++] = I8042_RET_ACK;
-			data_port_state = STATE_SCANCODE;
+		case ATKBD_CMD_GSCANSET: /* also ATKBD_CMD_SSCANSET */
+			output[out_len++] = ATKBD_RET_ACK;
+			data_port_state = STATE_ATKBD_SCANCODE;
 			break;
 
-		case I8042_CMD_SETLEDS:
+		case ATKBD_CMD_SETLEDS:
 			/* Chrome OS doesn't have keyboard LEDs, so ignore */
-			output[out_len++] = I8042_RET_ACK;
-			data_port_state = STATE_SETLEDS;
+			output[out_len++] = ATKBD_RET_ACK;
+			data_port_state = STATE_ATKBD_SETLEDS;
 			break;
 
-		case I8042_CMD_EX_SETLEDS:
-			output[out_len++] = I8042_RET_ACK;
-			data_port_state = STATE_EX_SETLEDS_1;
+		case ATKBD_CMD_EX_SETLEDS:
+			output[out_len++] = ATKBD_RET_ACK;
+			data_port_state = STATE_ATKBD_EX_SETLEDS_1;
 			break;
 
-		case I8042_CMD_DIAG_ECHO:
-			output[out_len++] = I8042_RET_ACK;
-			output[out_len++] = I8042_CMD_DIAG_ECHO;
+		case ATKBD_CMD_DIAG_ECHO:
+			output[out_len++] = ATKBD_RET_ACK;
+			output[out_len++] = ATKBD_RET_ECHO;
 			break;
 
-		case I8042_CMD_GETID:    /* fall-thru */
-		case I8042_CMD_OK_GETID:
-			output[out_len++] = I8042_RET_ACK;
-			output[out_len++] = 0xab;  /* Regular keyboards */
+		case ATKBD_CMD_GETID: /* fall-thru */
+		case ATKBD_CMD_OK_GETID:
+			output[out_len++] = ATKBD_RET_ACK;
+			output[out_len++] = 0xab; /* Regular keyboards */
 			output[out_len++] = 0x83;
 			break;
 
-		case I8042_CMD_SETREP:
-			output[out_len++] = I8042_RET_ACK;
-			data_port_state = STATE_SETREP;
+		case ATKBD_CMD_SETREP:
+			output[out_len++] = ATKBD_RET_ACK;
+			data_port_state = STATE_ATKBD_SETREP;
 			break;
 
-		case I8042_CMD_ENABLE:
-			output[out_len++] = I8042_RET_ACK;
+		case ATKBD_CMD_ENABLE:
+			output[out_len++] = ATKBD_RET_ACK;
 			keystroke_enable(1);
 			keyboard_clear_buffer();
 			break;
 
-		case I8042_CMD_RESET_DIS:
-			output[out_len++] = I8042_RET_ACK;
+		case ATKBD_CMD_RESET_DIS:
+			output[out_len++] = ATKBD_RET_ACK;
 			keystroke_enable(0);
 			reset_rate_and_delay();
 			keyboard_clear_buffer();
 			break;
 
-		case I8042_CMD_RESET_DEF:
-			output[out_len++] = I8042_RET_ACK;
+		case ATKBD_CMD_RESET_DEF:
+			output[out_len++] = ATKBD_RET_ACK;
 			reset_rate_and_delay();
 			keyboard_clear_buffer();
 			break;
 
-		case I8042_CMD_RESET:
+		case ATKBD_CMD_RESET:
 			reset_rate_and_delay();
 			keyboard_clear_buffer();
-			output[out_len++] = I8042_RET_ACK;
+			output[out_len++] = ATKBD_RET_ACK;
 			break;
 
-		case I8042_CMD_RESEND:
+		case ATKBD_CMD_RESEND:
 			save_for_resend = 0;
 			for (i = 0; i < resend_command_len; ++i)
 				output[out_len++] = resend_command[i];
@@ -714,12 +721,12 @@ static int handle_keyboard_data(uint8_t data, uint8_t *output)
 			/* U-boot hack.  Just ignore; don't reply. */
 			break;
 
-		case I8042_CMD_SETALL_MB:  /* fall-thru */
-		case I8042_CMD_SETALL_MBR:
-		case I8042_CMD_EX_ENABLE:
+		case ATKBD_CMD_SETALL_MB: /* fall-thru */
+		case ATKBD_CMD_SETALL_MBR:
+		case ATKBD_CMD_EX_ENABLE:
 		default:
-			output[out_len++] = I8042_RET_NAK;
-			CPRINTS("KB Unsupported i8042 data 0x%02x",
+			output[out_len++] = ATKBD_RET_RESEND;
+			CPRINTS("KB Unsupported AT keyboard command 0x%02x",
 				data);
 			break;
 		}
@@ -763,14 +770,14 @@ static int handle_keyboard_command(uint8_t command, uint8_t *output)
 		break;
 
 	case I8042_WRITE_CMD_BYTE:
-		data_port_state = STATE_WRITE_CMD_BYTE;
+		data_port_state = STATE_8042_WRITE_CMD_BYTE;
 		controller_ram_address = command - 0x60;
 		break;
 
 	case I8042_DIS_KB:
 		update_ctl_ram(0, read_ctl_ram(0) | I8042_KBD_DIS);
 		reset_rate_and_delay();
-		typematic_len = 0;  /* stop typematic */
+		typematic_len = 0; /* stop typematic */
 		keyboard_clear_buffer();
 		break;
 
@@ -784,16 +791,16 @@ static int handle_keyboard_command(uint8_t command, uint8_t *output)
 		output[out_len++] =
 			(lpc_keyboard_input_pending() ? BIT(5) : 0) |
 			(lpc_keyboard_has_char() ? BIT(4) : 0) |
-			(A20_status ? BIT(1) : 0) |
-			1;  /* Main processor in normal mode */
+			(A20_status ? BIT(1) : 0) | 1; /* Main processor in
+							  normal mode */
 		break;
 
 	case I8042_WRITE_OUTPUT_PORT:
-		data_port_state = STATE_WRITE_OUTPUT_PORT;
+		data_port_state = STATE_8042_WRITE_OUTPUT_PORT;
 		break;
 
 	case I8042_RESET_SELF_TEST:
-		output[out_len++] = 0x55;  /* Self test success */
+		output[out_len++] = 0x55; /* Self test success */
 		break;
 
 	case I8042_TEST_KB_PORT:
@@ -809,15 +816,15 @@ static int handle_keyboard_command(uint8_t command, uint8_t *output)
 		break;
 
 	case I8042_TEST_MOUSE:
-		output[out_len++] = 0;  /* No error detected */
+		output[out_len++] = 0; /* No error detected */
 		break;
 
 	case I8042_ECHO_MOUSE:
-		data_port_state = STATE_ECHO_MOUSE;
+		data_port_state = STATE_8042_ECHO_MOUSE;
 		break;
 
 	case I8042_SEND_TO_MOUSE:
-		data_port_state = STATE_SEND_TO_MOUSE;
+		data_port_state = STATE_8042_SEND_TO_MOUSE;
 		break;
 
 	case I8042_SYSTEM_RESET:
@@ -830,7 +837,7 @@ static int handle_keyboard_command(uint8_t command, uint8_t *output)
 			output[out_len++] = read_ctl_ram(command - 0x20);
 		} else if (command >= I8042_WRITE_CTL_RAM &&
 			   command <= I8042_WRITE_CTL_RAM_END) {
-			data_port_state = STATE_WRITE_CMD_BYTE;
+			data_port_state = STATE_8042_WRITE_CMD_BYTE;
 			controller_ram_address = command - 0x60;
 		} else if (command == I8042_DISABLE_A20) {
 			A20_status = 0;
@@ -848,7 +855,7 @@ static int handle_keyboard_command(uint8_t command, uint8_t *output)
 			reset_rate_and_delay();
 			keyboard_clear_buffer();
 			output[out_len++] = I8042_RET_NAK;
-			data_port_state = STATE_NORMAL;
+			data_port_state = STATE_ATKBD_CMD;
 		}
 		break;
 	}
@@ -877,7 +884,7 @@ static void i8042_handle_from_host(void)
 				ret_len = handle_keyboard_data(h.byte, output);
 		}
 
-		i8042_send_to_host(ret_len, output, chan);
+		i8042_send_to_host(ret_len, output, chan, 0);
 	}
 }
 
@@ -905,9 +912,9 @@ void keyboard_protocol_task(void *u)
 				if (keystroke_enabled)
 					i8042_send_to_host(typematic_len,
 							   typematic_scan_code,
-							   CHAN_KBD);
-				typematic_deadline.val = t.val +
-					typematic_inter_delay;
+							   CHAN_KBD, 1);
+				typematic_deadline.val =
+					t.val + typematic_inter_delay;
 				wait = typematic_inter_delay;
 			} else {
 				/* Wait for remaining interval */
@@ -970,13 +977,13 @@ static void send_aux_data_to_host_deferred(void)
 	uint8_t data;
 
 	if (IS_ENABLED(CONFIG_DEVICE_EVENT) &&
-		chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
+	    chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
 		device_set_single_event(EC_DEVICE_EVENT_TRACKPAD);
 
 	while (!queue_is_empty(&aux_to_host_queue)) {
 		queue_remove_unit(&aux_to_host_queue, &data);
 		if (aux_chan_enabled && IS_ENABLED(CONFIG_8042_AUX))
-			i8042_send_to_host(1, &data, CHAN_AUX);
+			i8042_send_to_host(1, &data, CHAN_AUX, 0);
 		else
 			CPRINTS("AUX Callback ignored");
 	}
@@ -1034,7 +1041,7 @@ test_mockable void keyboard_update_button(enum keyboard_button_type button,
 	if (keystroke_enabled) {
 		CPRINTS5("KB UPDATE BTN");
 
-		i8042_send_to_host(len, scan_code, CHAN_KBD);
+		i8042_send_to_host(len, scan_code, CHAN_KBD, 0);
 		task_wake(TASK_ID_KEYPROTO);
 	}
 }
@@ -1042,7 +1049,7 @@ test_mockable void keyboard_update_button(enum keyboard_button_type button,
 /*****************************************************************************/
 /* Console commands */
 #ifdef CONFIG_CMD_KEYBOARD
-static int command_typematic(int argc, char **argv)
+static int command_typematic(int argc, const char **argv)
 {
 	int i;
 
@@ -1064,13 +1071,13 @@ static int command_typematic(int argc, char **argv)
 	return EC_SUCCESS;
 }
 
-static int command_codeset(int argc, char **argv)
+static int command_codeset(int argc, const char **argv)
 {
 	if (argc == 2) {
 		int set = strtoi(argv[1], NULL, 0);
 		switch (set) {
-		case SCANCODE_SET_1:  /* fall-thru */
-		case SCANCODE_SET_2:  /* fall-thru */
+		case SCANCODE_SET_1: /* fall-thru */
+		case SCANCODE_SET_2: /* fall-thru */
 			scancode_set = set;
 			break;
 		default:
@@ -1083,7 +1090,7 @@ static int command_codeset(int argc, char **argv)
 	return EC_SUCCESS;
 }
 
-static int command_controller_ram(int argc, char **argv)
+static int command_controller_ram(int argc, const char **argv)
 {
 	int index;
 
@@ -1101,7 +1108,7 @@ static int command_controller_ram(int argc, char **argv)
 	return EC_SUCCESS;
 }
 
-static int command_keyboard_log(int argc, char **argv)
+static int command_keyboard_log(int argc, const char **argv)
 {
 	int i;
 
@@ -1109,8 +1116,8 @@ static int command_keyboard_log(int argc, char **argv)
 	if (argc == 1) {
 		ccprintf("KBC log (len=%d):\n", kblog_len);
 		for (i = 0; kblog_buf && i < kblog_len; ++i) {
-			ccprintf("%c.%02x ",
-				 kblog_buf[i].type, kblog_buf[i].byte);
+			ccprintf("%c.%02x ", kblog_buf[i].type,
+				 kblog_buf[i].byte);
 			if ((i & 15) == 15) {
 				ccputs("\n");
 				cflush();
@@ -1126,9 +1133,9 @@ static int command_keyboard_log(int argc, char **argv)
 
 	if (i) {
 		if (!kblog_buf) {
-			int rv = SHARED_MEM_ACQUIRE_CHECK(
-				sizeof(*kblog_buf) * MAX_KBLOG,
-				(char **)&kblog_buf);
+			int rv = SHARED_MEM_ACQUIRE_CHECK(sizeof(*kblog_buf) *
+								  MAX_KBLOG,
+							  (char **)&kblog_buf);
 			if (rv != EC_SUCCESS)
 				kblog_buf = NULL;
 			kblog_len = 0;
@@ -1144,7 +1151,7 @@ static int command_keyboard_log(int argc, char **argv)
 	return EC_SUCCESS;
 }
 
-static int command_keyboard(int argc, char **argv)
+static int command_keyboard(int argc, const char **argv)
 {
 	int ena;
 
@@ -1159,7 +1166,7 @@ static int command_keyboard(int argc, char **argv)
 	return EC_SUCCESS;
 }
 
-static int command_8042_internal(int argc, char **argv)
+static int command_8042_internal(int argc, const char **argv)
 {
 	int i;
 
@@ -1204,24 +1211,19 @@ static int command_8042_internal(int argc, char **argv)
 
 /* Zephyr only provides these as subcommands*/
 #ifndef CONFIG_ZEPHYR
-DECLARE_CONSOLE_COMMAND(typematic, command_typematic,
-			"[first] [inter]",
+DECLARE_CONSOLE_COMMAND(typematic, command_typematic, "[first] [inter]",
 			"Get/set typematic delays");
-DECLARE_CONSOLE_COMMAND(codeset, command_codeset,
-			"[set]",
+DECLARE_CONSOLE_COMMAND(codeset, command_codeset, "[set]",
 			"Get/set keyboard codeset");
-DECLARE_CONSOLE_COMMAND(ctrlram, command_controller_ram,
-			"index [value]",
+DECLARE_CONSOLE_COMMAND(ctrlram, command_controller_ram, "index [value]",
 			"Get/set keyboard controller RAM");
-DECLARE_CONSOLE_COMMAND(kblog, command_keyboard_log,
-			"[on | off]",
+DECLARE_CONSOLE_COMMAND(kblog, command_keyboard_log, "[on | off]",
 			"Print or toggle keyboard event log");
-DECLARE_CONSOLE_COMMAND(kbd, command_keyboard,
-			"[on | off]",
+DECLARE_CONSOLE_COMMAND(kbd, command_keyboard, "[on | off]",
 			"Print or toggle keyboard info");
 #endif
 
-static int command_8042(int argc, char **argv)
+static int command_8042(int argc, const char **argv)
 {
 	if (argc >= 2) {
 		if (!strcasecmp(argv[1], "internal"))
@@ -1239,16 +1241,16 @@ static int command_8042(int argc, char **argv)
 		else
 			return EC_ERROR_PARAM1;
 	} else {
-		char *ctlram_argv[] = {"ctrlram", "0"};
+		const char *ctlram_argv[] = { "ctrlram", "0" };
 
 		ccprintf("\n- Typematic:\n");
 		command_typematic(argc, argv);
 		ccprintf("\n- Codeset:\n");
 		command_codeset(argc, argv);
 		ccprintf("\n- Control RAM:\n");
-		command_controller_ram(
-			sizeof(ctlram_argv) / sizeof(ctlram_argv[0]),
-			ctlram_argv);
+		command_controller_ram(sizeof(ctlram_argv) /
+					       sizeof(ctlram_argv[0]),
+				       ctlram_argv);
 		if (CMD_KEYBOARD_LOG) {
 			ccprintf("\n- Keyboard log:\n");
 			command_keyboard_log(argc, argv);
@@ -1268,7 +1270,6 @@ DECLARE_CONSOLE_COMMAND(8042, command_8042,
 			"Print 8042 state in one place");
 #endif
 
-
 /*****************************************************************************/
 /* Hooks */
 
@@ -1290,8 +1291,8 @@ static void keyboard_preserve_state(void)
 	state.ctlram = controller_ram[0];
 	state.keystroke_enabled = keystroke_enabled;
 
-	system_add_jump_tag(KB_SYSJUMP_TAG, KB_HOOK_VERSION,
-			    sizeof(state), &state);
+	system_add_jump_tag(KB_SYSJUMP_TAG, KB_HOOK_VERSION, sizeof(state),
+			    &state);
 }
 DECLARE_HOOK(HOOK_SYSJUMP, keyboard_preserve_state, HOOK_PRIO_DEFAULT);
 
diff --git a/common/keyboard_8042_sharedlib.c b/common/keyboard_8042_sharedlib.c
index a2ed5c4445..3e98c977b7 100644
--- a/common/keyboard_8042_sharedlib.c
+++ b/common/keyboard_8042_sharedlib.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -7,6 +7,7 @@
 
 #include <stddef.h>
 
+#include "builtin/assert.h"
 #include "button.h"
 #include "keyboard_8042_sharedlib.h"
 #include "keyboard_config.h"
@@ -17,25 +18,25 @@
 #ifndef CONFIG_KEYBOARD_CUSTOMIZATION
 /* The standard Chrome OS keyboard matrix table in scan code set 2. */
 static uint16_t scancode_set2[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = {
-	{0x0000, 0x0000, 0x0014, 0xe01f, 0xe014, 0xe007, 0x0000, 0x0000},
-	{0xe01f, 0x0076, 0x000d, 0x000e, 0x001c, 0x001a, 0x0016, 0x0015},
-	{0x0005, 0x000c, 0x0004, 0x0006, 0x0023, 0x0021, 0x0026, 0x0024},
-	{0x0032, 0x0034, 0x002c, 0x002e, 0x002b, 0x002a, 0x0025, 0x002d},
-	{0x0009, 0x0083, 0x000b, 0x0003, 0x001b, 0x0022, 0x001e, 0x001d},
-	{0x0051, 0x0000, 0x005b, 0x0000, 0x0042, 0x0041, 0x003e, 0x0043},
-	{0x0031, 0x0033, 0x0035, 0x0036, 0x003b, 0x003a, 0x003d, 0x003c},
-	{0x0000, 0x0000, 0x0061, 0x0000, 0x0000, 0x0012, 0x0000, 0x0059},
-	{0x0055, 0x0052, 0x0054, 0x004e, 0x004c, 0x004a, 0x0045, 0x004d},
-	{0x0000, 0x0001, 0x000a, 0x002f, 0x004b, 0x0049, 0x0046, 0x0044},
-	{0xe011, 0x0000, 0x006a, 0x0000, 0x005d, 0x0000, 0x0011, 0x0000},
+	{ 0x0000, 0x0000, 0x0014, 0xe01f, 0xe014, 0xe007, 0x0000, 0x0000 },
+	{ 0xe01f, 0x0076, 0x000d, 0x000e, 0x001c, 0x001a, 0x0016, 0x0015 },
+	{ 0x0005, 0x000c, 0x0004, 0x0006, 0x0023, 0x0021, 0x0026, 0x0024 },
+	{ 0x0032, 0x0034, 0x002c, 0x002e, 0x002b, 0x002a, 0x0025, 0x002d },
+	{ 0x0009, 0x0083, 0x000b, 0x0003, 0x001b, 0x0022, 0x001e, 0x001d },
+	{ 0x0051, 0x0000, 0x005b, 0x0000, 0x0042, 0x0041, 0x003e, 0x0043 },
+	{ 0x0031, 0x0033, 0x0035, 0x0036, 0x003b, 0x003a, 0x003d, 0x003c },
+	{ 0x0000, 0x0000, 0x0061, 0x0000, 0x0000, 0x0012, 0x0000, 0x0059 },
+	{ 0x0055, 0x0052, 0x0054, 0x004e, 0x004c, 0x004a, 0x0045, 0x004d },
+	{ 0x0000, 0x0001, 0x000a, 0x002f, 0x004b, 0x0049, 0x0046, 0x0044 },
+	{ 0xe011, 0x0000, 0x006a, 0x0000, 0x005d, 0x0000, 0x0011, 0x0000 },
 #ifndef CONFIG_KEYBOARD_KEYPAD
-	{0x0000, 0x0066, 0x0000, 0x005d, 0x005a, 0x0029, 0xe072, 0xe075},
-	{0x0000, 0x0064, 0x0000, 0x0067, 0x0000, 0x0000, 0xe074, 0xe06b},
+	{ 0x0000, 0x0066, 0x0000, 0x005d, 0x005a, 0x0029, 0xe072, 0xe075 },
+	{ 0x0000, 0x0064, 0x0000, 0x0067, 0x0000, 0x0000, 0xe074, 0xe06b },
 #else
-	{0x0000, 0x0066, 0xe071, 0x005d, 0x005a, 0x0029, 0xe072, 0xe075},
-	{0xe06c, 0x0064, 0xe07d, 0x0067, 0xe069, 0xe07a, 0xe074, 0xe06b},
-	{0xe04a, 0x007c, 0x007b, 0x0074, 0x0071, 0x0073, 0x006b, 0x0070},
-	{0x006c, 0x0075, 0x007d, 0x0079, 0x007a, 0x0072, 0x0069, 0xe05a},
+	{ 0x0000, 0x0066, 0xe071, 0x005d, 0x005a, 0x0029, 0xe072, 0xe075 },
+	{ 0xe06c, 0x0064, 0xe07d, 0x0067, 0xe069, 0xe07a, 0xe074, 0xe06b },
+	{ 0xe04a, 0x007c, 0x007b, 0x0074, 0x0071, 0x0073, 0x006b, 0x0070 },
+	{ 0x006c, 0x0075, 0x007d, 0x0079, 0x007a, 0x0072, 0x0069, 0xe05a },
 #endif
 };
 
@@ -68,37 +69,32 @@ void set_scancode_set2(uint8_t row, uint8_t col, uint16_t val)
  * see scancode_translate_set2_to_1 below).
  */
 SHAREDLIB(const uint8_t scancode_translate_table[128] = {
-	0xff, 0x43, 0x41, 0x3f, 0x3d, 0x3b, 0x3c, 0x58,
-	0x64, 0x44, 0x42, 0x40, 0x3e, 0x0f, 0x29, 0x59,
-	0x65, 0x38, 0x2a, 0x70, 0x1d, 0x10, 0x02, 0x5a,
-	0x66, 0x71, 0x2c, 0x1f, 0x1e, 0x11, 0x03, 0x5b,
-	0x67, 0x2e, 0x2d, 0x20, 0x12, 0x05, 0x04, 0x5c,
-	0x68, 0x39, 0x2f, 0x21, 0x14, 0x13, 0x06, 0x5d,
-	0x69, 0x31, 0x30, 0x23, 0x22, 0x15, 0x07, 0x5e,
-	0x6a, 0x72, 0x32, 0x24, 0x16, 0x08, 0x09, 0x5f,
-	0x6b, 0x33, 0x25, 0x17, 0x18, 0x0b, 0x0a, 0x60,
-	0x6c, 0x34, 0x35, 0x26, 0x27, 0x19, 0x0c, 0x61,
-	0x6d, 0x73, 0x28, 0x74, 0x1a, 0x0d, 0x62, 0x6e,
-	0x3a, 0x36, 0x1c, 0x1b, 0x75, 0x2b, 0x63, 0x76,
-	0x55, 0x56, 0x77, 0x78, 0x79, 0x7a, 0x0e, 0x7b,
-	0x7c, 0x4f, 0x7d, 0x4b, 0x47, 0x7e, 0x7f, 0x6f,
-	0x52, 0x53, 0x50, 0x4c, 0x4d, 0x48, 0x01, 0x45,
-	0x57, 0x4e, 0x51, 0x4a, 0x37, 0x49, 0x46, 0x54,
-});
-
+		  0xff, 0x43, 0x41, 0x3f, 0x3d, 0x3b, 0x3c, 0x58, 0x64, 0x44,
+		  0x42, 0x40, 0x3e, 0x0f, 0x29, 0x59, 0x65, 0x38, 0x2a, 0x70,
+		  0x1d, 0x10, 0x02, 0x5a, 0x66, 0x71, 0x2c, 0x1f, 0x1e, 0x11,
+		  0x03, 0x5b, 0x67, 0x2e, 0x2d, 0x20, 0x12, 0x05, 0x04, 0x5c,
+		  0x68, 0x39, 0x2f, 0x21, 0x14, 0x13, 0x06, 0x5d, 0x69, 0x31,
+		  0x30, 0x23, 0x22, 0x15, 0x07, 0x5e, 0x6a, 0x72, 0x32, 0x24,
+		  0x16, 0x08, 0x09, 0x5f, 0x6b, 0x33, 0x25, 0x17, 0x18, 0x0b,
+		  0x0a, 0x60, 0x6c, 0x34, 0x35, 0x26, 0x27, 0x19, 0x0c, 0x61,
+		  0x6d, 0x73, 0x28, 0x74, 0x1a, 0x0d, 0x62, 0x6e, 0x3a, 0x36,
+		  0x1c, 0x1b, 0x75, 0x2b, 0x63, 0x76, 0x55, 0x56, 0x77, 0x78,
+		  0x79, 0x7a, 0x0e, 0x7b, 0x7c, 0x4f, 0x7d, 0x4b, 0x47, 0x7e,
+		  0x7f, 0x6f, 0x52, 0x53, 0x50, 0x4c, 0x4d, 0x48, 0x01, 0x45,
+		  0x57, 0x4e, 0x51, 0x4a, 0x37, 0x49, 0x46, 0x54,
+	  });
 
 #ifdef CONFIG_KEYBOARD_DEBUG
-SHAREDLIB(const
-static char * const keycap_long_label[KLLI_MAX & KEYCAP_LONG_LABEL_INDEX_BITMASK] = {
-	"UNKNOWN", "F1",    "F2",    "F3",
-	"F4",      "F5",    "F6",    "F7",
-	"F8",      "F9",    "F10",   "F11",
-	"F12",     "F13",   "F14",   "F15",
-	"L-ALT",   "R-ALT", "L-CTR", "R-CTR",
-	"L-SHT",   "R-SHT", "ENTER", "SPACE",
-	"B-SPC",   "TAB",   "SEARC", "LEFT",
-	"RIGHT",   "DOWN",  "UP",    "ESC",
-});
+SHAREDLIB(
+	const static char *const
+		keycap_long_label[KLLI_MAX & KEYCAP_LONG_LABEL_INDEX_BITMASK] = {
+			"UNKNOWN", "F1",    "F2",    "F3",    "F4",    "F5",
+			"F6",	   "F7",    "F8",    "F9",    "F10",   "F11",
+			"F12",	   "F13",   "F14",   "F15",   "L-ALT", "R-ALT",
+			"L-CTR",   "R-CTR", "L-SHT", "R-SHT", "ENTER", "SPACE",
+			"B-SPC",   "TAB",   "SEARC", "LEFT",  "RIGHT", "DOWN",
+			"UP",	   "ESC",
+		});
 
 const char *get_keycap_long_label(uint8_t idx)
 {
@@ -109,38 +105,30 @@ const char *get_keycap_long_label(uint8_t idx)
 
 #ifndef CONFIG_KEYBOARD_CUSTOMIZATION
 static char keycap_label[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = {
-	{KLLI_UNKNO, KLLI_UNKNO, KLLI_L_CTR, KLLI_SEARC,
-			KLLI_R_CTR, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO},
-	{KLLI_F11,   KLLI_ESC,   KLLI_TAB,   '~',
-			'a',        'z',        '1',        'q'},
-	{KLLI_F1,    KLLI_F4,    KLLI_F3,    KLLI_F2,
-			'd',        'c',        '3',        'e'},
-	{'b',        'g',        't',        '5',
-			'f',        'v',        '4',        'r'},
-	{KLLI_F10,   KLLI_F7,    KLLI_F6,    KLLI_F5,
-			's',        'x',        '2',        'w'},
-	{KLLI_UNKNO, KLLI_F12,   ']',        KLLI_F13,
-			'k',        ',',        '8',        'i'},
-	{'n',        'h',        'y',        '6',
-			'j',        'm',        '7',        'u'},
-	{KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
-			KLLI_UNKNO, KLLI_L_SHT, KLLI_UNKNO, KLLI_R_SHT},
-	{'=',        '\'',       '[',        '-',
-			';',        '/',        '0',        'p'},
-	{KLLI_F14,   KLLI_F9,    KLLI_F8,    KLLI_UNKNO,
-			'|',        '.',        '9',        'o'},
-	{KLLI_R_ALT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
-			KLLI_UNKNO, KLLI_UNKNO, KLLI_L_ALT, KLLI_UNKNO},
-	{KLLI_F15,   KLLI_B_SPC, KLLI_UNKNO, '\\',
-			KLLI_ENTER, KLLI_SPACE, KLLI_DOWN,  KLLI_UP},
-	{KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
-			KLLI_UNKNO, KLLI_UNKNO, KLLI_RIGHT, KLLI_LEFT},
+	{ KLLI_UNKNO, KLLI_UNKNO, KLLI_L_CTR, KLLI_SEARC, KLLI_R_CTR,
+	  KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO },
+	{ KLLI_F11, KLLI_ESC, KLLI_TAB, '~', 'a', 'z', '1', 'q' },
+	{ KLLI_F1, KLLI_F4, KLLI_F3, KLLI_F2, 'd', 'c', '3', 'e' },
+	{ 'b', 'g', 't', '5', 'f', 'v', '4', 'r' },
+	{ KLLI_F10, KLLI_F7, KLLI_F6, KLLI_F5, 's', 'x', '2', 'w' },
+	{ KLLI_UNKNO, KLLI_F12, ']', KLLI_F13, 'k', ',', '8', 'i' },
+	{ 'n', 'h', 'y', '6', 'j', 'm', '7', 'u' },
+	{ KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_L_SHT, KLLI_UNKNO, KLLI_R_SHT },
+	{ '=', '\'', '[', '-', ';', '/', '0', 'p' },
+	{ KLLI_F14, KLLI_F9, KLLI_F8, KLLI_UNKNO, '|', '.', '9', 'o' },
+	{ KLLI_R_ALT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_L_ALT, KLLI_UNKNO },
+	{ KLLI_F15, KLLI_B_SPC, KLLI_UNKNO, '\\', KLLI_ENTER, KLLI_SPACE,
+	  KLLI_DOWN, KLLI_UP },
+	{ KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_RIGHT, KLLI_LEFT },
 #ifdef CONFIG_KEYBOARD_KEYPAD
 	/* TODO: Populate these */
-	{KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
-			KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO},
-	{KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
-			KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO},
+	{ KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO },
+	{ KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO,
+	  KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO },
 #endif
 };
 
@@ -174,16 +162,16 @@ uint8_t scancode_translate_set2_to_1(uint8_t code)
  * Must be in the same order as defined in keyboard_button_type.
  */
 SHAREDLIB(const struct button_8042_t buttons_8042[] = {
-	{SCANCODE_POWER, 0},
-	{SCANCODE_VOLUME_DOWN, 1},
-	{SCANCODE_VOLUME_UP, 1},
-	{SCANCODE_1, 1},
-	{SCANCODE_2, 1},
-	{SCANCODE_3, 1},
-	{SCANCODE_4, 1},
-	{SCANCODE_5, 1},
-	{SCANCODE_6, 1},
-	{SCANCODE_7, 1},
-	{SCANCODE_8, 1},
-});
+		  { SCANCODE_POWER, 0 },
+		  { SCANCODE_VOLUME_DOWN, 1 },
+		  { SCANCODE_VOLUME_UP, 1 },
+		  { SCANCODE_1, 1 },
+		  { SCANCODE_2, 1 },
+		  { SCANCODE_3, 1 },
+		  { SCANCODE_4, 1 },
+		  { SCANCODE_5, 1 },
+		  { SCANCODE_6, 1 },
+		  { SCANCODE_7, 1 },
+		  { SCANCODE_8, 1 },
+	  });
 BUILD_ASSERT(ARRAY_SIZE(buttons_8042) == KEYBOARD_BUTTON_COUNT);
diff --git a/common/keyboard_backlight.c b/common/keyboard_backlight.c
index 62da361d73..fde20de7ef 100644
--- a/common/keyboard_backlight.c
+++ b/common/keyboard_backlight.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,16 +15,20 @@
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_KEYBOARD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_KEYBOARD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ##args)
 
 static struct kblight_conf kblight;
 static int current_percent;
 static uint8_t current_enable;
 
-__overridable void board_kblight_init(void) {}
+__overridable void board_kblight_init(void)
+{
+}
 
-__overridable void board_kblight_shutdown(void) {}
+__overridable void board_kblight_shutdown(void)
+{
+}
 
 static int kblight_init(void)
 {
@@ -89,7 +93,6 @@ int kblight_get_enabled(void)
 	return -1;
 }
 
-
 int kblight_register(const struct kblight_drv *drv)
 {
 	kblight.drv = drv;
@@ -137,7 +140,7 @@ static void kblight_resume(void)
 	}
 }
 DECLARE_HOOK(HOOK_CHIPSET_RESUME, kblight_resume, HOOK_PRIO_DEFAULT);
-#endif  /* CONFIG_AP_POWER_CONTROL */
+#endif /* CONFIG_AP_POWER_CONTROL */
 
 #ifdef CONFIG_LID_SWITCH
 static void kblight_lid_change(void)
@@ -150,7 +153,7 @@ DECLARE_HOOK(HOOK_LID_CHANGE, kblight_lid_change, HOOK_PRIO_DEFAULT);
 /*
  * Console and host commands
  */
-static int cc_kblight(int argc, char **argv)
+static int cc_kblight(int argc, const char **argv)
 {
 	if (argc >= 2) {
 		char *e;
@@ -162,12 +165,11 @@ static int cc_kblight(int argc, char **argv)
 		if (kblight_enable(i > 0))
 			return EC_ERROR_PARAM1;
 	}
-	ccprintf("Keyboard backlight: %d%% enabled: %d\n",
-		kblight_get(), kblight_get_enabled());
+	ccprintf("Keyboard backlight: %d%% enabled: %d\n", kblight_get(),
+		 kblight_get_enabled());
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(kblight, cc_kblight,
-			"percent",
+DECLARE_CONSOLE_COMMAND(kblight, cc_kblight, "percent",
 			"Get/set keyboard backlight");
 
 static enum ec_status
@@ -182,8 +184,7 @@ hc_get_keyboard_backlight(struct host_cmd_handler_args *args)
 	return EC_RES_SUCCESS;
 }
 DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_KEYBOARD_BACKLIGHT,
-		     hc_get_keyboard_backlight,
-		     EC_VER_MASK(0));
+		     hc_get_keyboard_backlight, EC_VER_MASK(0));
 
 static enum ec_status
 hc_set_keyboard_backlight(struct host_cmd_handler_args *args)
@@ -197,5 +198,11 @@ hc_set_keyboard_backlight(struct host_cmd_handler_args *args)
 	return EC_RES_SUCCESS;
 }
 DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT,
-		     hc_set_keyboard_backlight,
-		     EC_VER_MASK(0));
+		     hc_set_keyboard_backlight, EC_VER_MASK(0));
+
+#ifdef TEST_BUILD
+uint8_t kblight_get_current_enable(void)
+{
+	return current_enable;
+}
+#endif /* TEST_BUILD */
diff --git a/common/keyboard_mkbp.c b/common/keyboard_mkbp.c
index 51c17a5cee..fa003c31a2 100644
--- a/common/keyboard_mkbp.c
+++ b/common/keyboard_mkbp.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -21,7 +21,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_KEYBOARD, outstr)
-#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ##args)
 
 /* Changes to col,row here need to also be reflected in kernel.
  * drivers/input/mkbp.c ... see KEY_BATTERY.
@@ -36,9 +36,9 @@
 
 /* Config for mkbp protocol; does not include fields from scan config */
 struct ec_mkbp_protocol_config {
-	uint32_t valid_mask;	/* valid fields */
-	uint8_t flags;		/* some flags (enum mkbp_config_flags) */
-	uint8_t valid_flags;	/* which flags are valid */
+	uint32_t valid_mask; /* valid fields */
+	uint8_t flags; /* some flags (enum mkbp_config_flags) */
+	uint8_t valid_flags; /* which flags are valid */
 
 	/* maximum depth to allow for fifo (0 = no keyscan output) */
 	uint8_t fifo_max_depth;
@@ -46,9 +46,10 @@ struct ec_mkbp_protocol_config {
 
 static struct ec_mkbp_protocol_config config = {
 	.valid_mask = EC_MKBP_VALID_SCAN_PERIOD | EC_MKBP_VALID_POLL_TIMEOUT |
-		EC_MKBP_VALID_MIN_POST_SCAN_DELAY |
-		EC_MKBP_VALID_OUTPUT_SETTLE | EC_MKBP_VALID_DEBOUNCE_DOWN |
-		EC_MKBP_VALID_DEBOUNCE_UP | EC_MKBP_VALID_FIFO_MAX_DEPTH,
+		      EC_MKBP_VALID_MIN_POST_SCAN_DELAY |
+		      EC_MKBP_VALID_OUTPUT_SETTLE |
+		      EC_MKBP_VALID_DEBOUNCE_DOWN | EC_MKBP_VALID_DEBOUNCE_UP |
+		      EC_MKBP_VALID_FIFO_MAX_DEPTH,
 	.valid_flags = EC_MKBP_FLAGS_ENABLE,
 	.flags = EC_MKBP_FLAGS_ENABLE,
 	.fifo_max_depth = FIFO_DEPTH,
@@ -81,7 +82,8 @@ static int keyboard_get_next_event(uint8_t *out)
 DECLARE_EVENT_SOURCE(EC_MKBP_EVENT_KEY_MATRIX, keyboard_get_next_event);
 
 void clear_typematic_key(void)
-{ }
+{
+}
 
 static void set_keyscan_config(const struct ec_mkbp_config *src,
 			       struct ec_mkbp_protocol_config *dst,
@@ -119,11 +121,11 @@ static void set_keyscan_config(const struct ec_mkbp_config *src,
 	 * fall out of the task_wait_event() in keyboard_scan_task().
 	 */
 	if ((new_flags & EC_MKBP_FLAGS_ENABLE) &&
-			!(dst->flags & EC_MKBP_FLAGS_ENABLE))
+	    !(dst->flags & EC_MKBP_FLAGS_ENABLE))
 		task_wake(TASK_ID_KEYSCAN);
 }
 
-static void get_keyscan_config(struct ec_mkbp_config *dst)
+test_export_static void get_keyscan_config(struct ec_mkbp_config *dst)
 {
 	const struct keyboard_scan_config *ksc = keyboard_scan_get_config();
 
@@ -151,15 +153,14 @@ static void get_keyscan_config(struct ec_mkbp_config *dst)
  *			over to dst->flags
  */
 static void keyscan_copy_config(const struct ec_mkbp_config *src,
-				 struct ec_mkbp_protocol_config *dst,
-				 uint32_t valid_mask, uint8_t valid_flags)
+				struct ec_mkbp_protocol_config *dst,
+				uint32_t valid_mask, uint8_t valid_flags)
 {
 	uint8_t new_flags;
 
 	if (valid_mask & EC_MKBP_VALID_FIFO_MAX_DEPTH) {
 		/* Validity check for fifo depth */
-		dst->fifo_max_depth = MIN(src->fifo_max_depth,
-					  FIFO_DEPTH);
+		dst->fifo_max_depth = MIN(src->fifo_max_depth, FIFO_DEPTH);
 	}
 
 	new_flags = dst->flags & ~valid_flags;
@@ -182,8 +183,7 @@ host_command_mkbp_set_config(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_MKBP_SET_CONFIG,
-		     host_command_mkbp_set_config,
+DECLARE_HOST_COMMAND(EC_CMD_MKBP_SET_CONFIG, host_command_mkbp_set_config,
 		     EC_VER_MASK(0));
 
 static enum ec_status
@@ -206,6 +206,5 @@ host_command_mkbp_get_config(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_MKBP_GET_CONFIG,
-		     host_command_mkbp_get_config,
+DECLARE_HOST_COMMAND(EC_CMD_MKBP_GET_CONFIG, host_command_mkbp_get_config,
 		     EC_VER_MASK(0));
diff --git a/common/keyboard_scan.c b/common/keyboard_scan.c
index 26ffde96dc..6c3756170b 100644
--- a/common/keyboard_scan.c
+++ b/common/keyboard_scan.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,6 +19,7 @@
 #include "keyboard_scan.h"
 #include "keyboard_test.h"
 #include "lid_switch.h"
+#include "printf.h"
 #include "switch.h"
 #include "system.h"
 #include "tablet_mode.h"
@@ -27,23 +28,27 @@
 #include "usb_api.h"
 #include "util.h"
 
+#ifdef CONFIG_KEYBOARD_MULTIPLE
+#include "keyboard_customization.h"
+#endif
+
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_KEYSCAN, outstr)
-#define CPRINTF(format, args...) cprintf(CC_KEYSCAN, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_KEYSCAN, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_KEYSCAN, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_KEYSCAN, format, ##args)
 
 #ifdef CONFIG_KEYBOARD_DEBUG
 #define CPUTS5(outstr) cputs(CC_KEYSCAN, outstr)
-#define CPRINTS5(format, args...) cprints(CC_KEYBOARD, format, ## args)
+#define CPRINTS5(format, args...) cprints(CC_KEYBOARD, format, ##args)
 #else
 #define CPUTS5(outstr)
 #define CPRINTS5(format, args...)
 #endif
 
-#define SCAN_TIME_COUNT 32  /* Number of last scan times to track */
+#define SCAN_TIME_COUNT 32 /* Number of last scan times to track */
 
 /* If we're waiting for a scan to happen, we'll give it this long */
-#define SCAN_TASK_TIMEOUT_US	(100 * MSEC)
+#define SCAN_TASK_TIMEOUT_US (100 * MSEC)
 
 #ifndef CONFIG_KEYBOARD_POST_SCAN_CLOCKS
 /*
@@ -78,18 +83,20 @@ __overridable struct keyboard_scan_config keyscan_config = {
 	},
 };
 
-/* Boot key list.  Must be in same order as enum boot_key. */
-struct boot_key_entry {
-	uint8_t col;
-	uint8_t row;
-};
-
 #ifdef CONFIG_KEYBOARD_BOOT_KEYS
+#ifndef CONFIG_KEYBOARD_MULTIPLE
 static const struct boot_key_entry boot_key_list[] = {
-	{KEYBOARD_COL_ESC, KEYBOARD_ROW_ESC},   /* Esc */
-	{KEYBOARD_COL_DOWN, KEYBOARD_ROW_DOWN}, /* Down-arrow */
-	{KEYBOARD_COL_LEFT_SHIFT, KEYBOARD_ROW_LEFT_SHIFT}, /* Left-Shift */
+	{ KEYBOARD_COL_ESC, KEYBOARD_ROW_ESC }, /* Esc */
+	{ KEYBOARD_COL_DOWN, KEYBOARD_ROW_DOWN }, /* Down-arrow */
+	{ KEYBOARD_COL_LEFT_SHIFT, KEYBOARD_ROW_LEFT_SHIFT }, /* Left-Shift */
 };
+#else
+struct boot_key_entry boot_key_list[] = {
+	{ KEYBOARD_COL_ESC, KEYBOARD_ROW_ESC }, /* Esc */
+	{ KEYBOARD_COL_DOWN, KEYBOARD_ROW_DOWN }, /* Down-arrow */
+	{ KEYBOARD_COL_LEFT_SHIFT, KEYBOARD_ROW_LEFT_SHIFT }, /* Left-Shift */
+};
+#endif
 static uint32_t boot_key_value = BOOT_KEY_NONE;
 #endif
 
@@ -131,7 +138,7 @@ static volatile int kbd_polls;
 /* If true, we'll force a keyboard poll */
 static volatile int force_poll;
 
-static int keyboard_scan_is_enabled(void)
+test_export_static int keyboard_scan_is_enabled(void)
 {
 	/* NOTE: this is just an instantaneous glimpse of the variable. */
 	return !disable_scanning_mask;
@@ -160,8 +167,10 @@ void keyboard_scan_enable(int enable, enum kb_scan_disable_masks mask)
 static void print_state(const uint8_t *state, const char *msg)
 {
 	int c;
+	char ts_str[PRINTF_TIMESTAMP_BUF_SIZE];
 
-	CPRINTF("[%pT KB %s:", PRINTF_TIMESTAMP_NOW, msg);
+	snprintf_timestamp_now(ts_str, sizeof(ts_str));
+	CPRINTF("[%s KB %s:", ts_str, msg);
 	for (c = 0; c < keyboard_cols; c++) {
 		if (state[c])
 			CPRINTF(" %02x", state[c]);
@@ -208,7 +217,7 @@ static int keyboard_read_adc_rows(void)
 	/* Read each adc channel to build row byte */
 	for (int i = 0; i < KEYBOARD_ROWS; i++) {
 		if (adc_read_channel(ADC_KSI_00 + i) >
-				keyscan_config.ksi_threshold_mv)
+		    keyscan_config.ksi_threshold_mv)
 			kb_row |= (1 << i);
 	}
 
@@ -226,14 +235,20 @@ static int keyboard_read_adc_rows(void)
  */
 static void keyboard_read_refresh_key(uint8_t *state)
 {
+#ifndef CONFIG_KEYBOARD_MULTIPLE
 	if (!gpio_get_level(GPIO_RFR_KEY_L))
 		state[KEYBOARD_COL_REFRESH] |= BIT(KEYBOARD_ROW_REFRESH);
 	else
 		state[KEYBOARD_COL_REFRESH] &= ~BIT(KEYBOARD_ROW_REFRESH);
+#else
+	if (!gpio_get_level(GPIO_RFR_KEY_L))
+		state[key_typ.col_refresh] |= BIT(key_typ.row_refresh);
+	else
+		state[key_typ.col_refresh] &= ~BIT(key_typ.row_refresh);
+#endif
 }
 #endif
 
-
 /**
  * Simulate a keypress.
  *
@@ -246,7 +261,7 @@ static void simulate_key(int row, int col, int pressed)
 	int old_polls;
 
 	if ((simulated_key[col] & BIT(row)) == ((pressed ? 1 : 0) << row))
-		return;  /* No change */
+		return; /* No change */
 
 	simulated_key[col] ^= BIT(row);
 
@@ -266,8 +281,8 @@ static void simulate_key(int row, int col, int pressed)
 	 * That means it needs to have run and for enough time.
 	 */
 	ensure_keyboard_scanned(old_polls);
-	usleep(pressed ?
-	       keyscan_config.debounce_down_us : keyscan_config.debounce_up_us);
+	usleep(pressed ? keyscan_config.debounce_down_us :
+			 keyscan_config.debounce_up_us);
 	ensure_keyboard_scanned(kbd_polls);
 }
 
@@ -279,10 +294,11 @@ static void simulate_key(int row, int col, int pressed)
  *
  * @param state		Destination for new state (must be KEYBOARD_COLS_MAX
  *			long).
+ * @param at_boot	True if we are reading the boot key state.
  *
  * @return 1 if at least one key is pressed, else zero.
  */
-static int read_matrix(uint8_t *state)
+static int read_matrix(uint8_t *state, bool at_boot)
 {
 	int c;
 	int pressed = 0;
@@ -317,6 +333,31 @@ static int read_matrix(uint8_t *state)
 			state[c] = keyscan_seq_get_scan(c, state[c]);
 	}
 
+#ifdef KEYBOARD_MASK_PWRBTN
+	/*
+	 * 2. Boot key workaround.
+	 *
+	 * Check if KSI2 or KSI3 is asserted for all columns due to power
+	 * button hold, and ignore it if so.
+	 */
+	if (at_boot) {
+		for (c = 0; c < keyboard_cols; c++) {
+			if (!(state[c] & KEYBOARD_MASK_PWRBTN))
+				break;
+		}
+
+		if (c == keyboard_cols) {
+			for (c = 0; c < keyboard_cols; c++)
+				state[c] &= ~KEYBOARD_MASK_PWRBTN;
+#ifndef CONFIG_KEYBOARD_MULTIPLE
+			state[KEYBOARD_COL_REFRESH] |= KEYBOARD_MASK_PWRBTN;
+#else
+			state[key_typ.col_refresh] |= KEYBOARD_MASK_PWRBTN;
+#endif
+		}
+	}
+#endif
+
 #ifdef CONFIG_KEYBOARD_SCAN_ADC
 	/* Account for the refresh key */
 	keyboard_read_refresh_key(state);
@@ -326,7 +367,7 @@ static int read_matrix(uint8_t *state)
 	 * this check isn't required
 	 */
 #else
-	/* 2. Detect transitional ghost */
+	/* 3. Detect transitional ghost */
 	for (c = 0; c < keyboard_cols; c++) {
 		int c2;
 
@@ -351,7 +392,7 @@ static int read_matrix(uint8_t *state)
 	}
 #endif
 
-	/* 3. Fix result */
+	/* 4. Fix result */
 	for (c = 0; c < keyboard_cols; c++) {
 		/* Add in simulated keypresses */
 		state[c] |= simulated_key[c];
@@ -365,7 +406,6 @@ static int read_matrix(uint8_t *state)
 
 		/* Mask off keys that don't exist on the actual keyboard */
 		state[c] &= keyscan_config.actual_key_mask[c];
-
 	}
 
 	keyboard_raw_drive_column(KEYBOARD_COLUMN_NONE);
@@ -437,9 +477,15 @@ static int check_runtime_keys(const uint8_t *state)
 	if (state[key_vol_up_col] != KEYBOARD_ROW_TO_MASK(key_vol_up_row))
 		return 0;
 
+#ifndef CONFIG_KEYBOARD_MULTIPLE
 	if (state[KEYBOARD_COL_RIGHT_ALT] != KEYBOARD_MASK_RIGHT_ALT &&
 	    state[KEYBOARD_COL_LEFT_ALT] != KEYBOARD_MASK_LEFT_ALT)
 		return 0;
+#else
+	if (state[key_typ.col_right_alt] != KEYBOARD_MASK_RIGHT_ALT &&
+	    state[key_typ.col_left_alt] != KEYBOARD_MASK_LEFT_ALT)
+		return 0;
+#endif
 
 	/*
 	 * Count number of columns with keys pressed.  We know two columns are
@@ -454,6 +500,7 @@ static int check_runtime_keys(const uint8_t *state)
 	if (num_press != 3)
 		return 0;
 
+#ifndef CONFIG_KEYBOARD_MULTIPLE
 	/* Check individual keys */
 	if (state[KEYBOARD_COL_KEY_R] == KEYBOARD_MASK_KEY_R) {
 		/* R = reboot */
@@ -467,6 +514,21 @@ static int check_runtime_keys(const uint8_t *state)
 		system_enter_hibernate(0, 0);
 		return 1;
 	}
+#else
+	/* Check individual keys */
+	if (state[key_typ.col_key_r] == KEYBOARD_MASK_KEY_R) {
+		/* R = reboot */
+		CPRINTS("KB warm reboot");
+		keyboard_clear_buffer();
+		chipset_reset(CHIPSET_RESET_KB_WARM_REBOOT);
+		return 1;
+	} else if (state[key_typ.col_key_h] == KEYBOARD_MASK_KEY_H) {
+		/* H = hibernate */
+		CPRINTS("KB hibernate");
+		system_enter_hibernate(0, 0);
+		return 1;
+	}
+#endif
 
 	return 0;
 }
@@ -510,7 +572,7 @@ static int has_ghosting(const uint8_t *state)
 }
 
 /* Inform keyboard module if scanning is enabled */
-static void key_state_changed(int row, int col, uint8_t state)
+test_mockable_static void key_state_changed(int row, int col, uint8_t state)
 {
 	if (!keyboard_scan_is_enabled())
 		return;
@@ -540,7 +602,7 @@ static int check_keys_changed(uint8_t *state)
 	scan_time[scan_time_index] = tnow;
 
 	/* Read the raw key state */
-	any_pressed = read_matrix(new_state);
+	any_pressed = read_matrix(new_state, false);
 
 	if (!IS_ENABLED(CONFIG_KEYBOARD_SCAN_ADC)) {
 		/* Ignore if so many keys are pressed that we're ghosting. */
@@ -559,7 +621,7 @@ static int check_keys_changed(uint8_t *state)
 			if (tnow - scan_time[scan_edge_index[c][i]] <
 			    (state[c] ? keyscan_config.debounce_down_us :
 					keyscan_config.debounce_up_us))
-				continue;  /* Not done debouncing */
+				continue; /* Not done debouncing */
 			debouncing[c] &= ~BIT(i);
 
 			if (!IS_ENABLED(CONFIG_KEYBOARD_STRICT_DEBOUNCE))
@@ -604,7 +666,6 @@ static int check_keys_changed(uint8_t *state)
 	}
 
 	if (any_change) {
-
 #ifdef CONFIG_KEYBOARD_SUPPRESS_NOISE
 		/* Suppress keyboard noise */
 		keyboard_suppress_noise();
@@ -615,11 +676,14 @@ static int check_keys_changed(uint8_t *state)
 
 #ifdef CONFIG_KEYBOARD_PRINT_SCAN_TIMES
 		/* Print delta times from now back to each previous scan */
-		CPRINTF("[%pT kb deltaT", PRINTF_TIMESTAMP_NOW);
+		char ts_str[PRINTF_TIMESTAMP_BUF_SIZE];
+
+		snprintf_timestamp_now(ts_str, sizeof(ts_str));
+		CPRINTF("[%s kb deltaT", ts_str);
 		for (i = 0; i < SCAN_TIME_COUNT; i++) {
-			int tnew = scan_time[
-				(SCAN_TIME_COUNT + scan_time_index - i) %
-				SCAN_TIME_COUNT];
+			int tnew = scan_time[(SCAN_TIME_COUNT +
+					      scan_time_index - i) %
+					     SCAN_TIME_COUNT];
 			CPRINTF(" %d", tnow - tnew);
 		}
 		CPRINTF("]\n");
@@ -665,22 +729,11 @@ static uint32_t check_key_list(const uint8_t *state)
 	/* Make copy of current debounced state. */
 	memcpy(curr_state, state, sizeof(curr_state));
 
-#ifdef KEYBOARD_MASK_PWRBTN
-	/*
-	 * Check if KSI2 or KSI3 is asserted for all columns due to power
-	 * button hold, and ignore it if so.
-	 */
-	for (c = 0; c < keyboard_cols; c++)
-		if ((keyscan_config.actual_key_mask[c] & KEYBOARD_MASK_PWRBTN)
-		    && !(curr_state[c] & KEYBOARD_MASK_PWRBTN))
-			break;
-
-	if (c == keyboard_cols)
-		for (c = 0; c < keyboard_cols; c++)
-			curr_state[c] &= ~KEYBOARD_MASK_PWRBTN;
-#endif
-
+#ifndef CONFIG_KEYBOARD_MULTIPLE
 	curr_state[KEYBOARD_COL_REFRESH] &= ~keyboard_mask_refresh;
+#else
+	curr_state[key_typ.col_refresh] &= ~keyboard_mask_refresh;
+#endif
 
 	/* Update mask with all boot keys that were pressed. */
 	k = boot_key_list;
@@ -715,7 +768,7 @@ static void read_adc_boot_keys(uint8_t *state)
 		udelay(keyscan_config.output_settle_us);
 
 		if (adc_read_channel(ADC_KSI_00 + r) >
-				keyscan_config.ksi_threshold_mv)
+		    keyscan_config.ksi_threshold_mv)
 			state[c] |= BIT(r);
 	}
 
@@ -745,10 +798,16 @@ static uint32_t check_boot_key(const uint8_t *state)
 	if (system_jumped_late())
 		return BOOT_KEY_NONE;
 
-	/* If reset was not caused by reset pin, refresh must be held down */
+/* If reset was not caused by reset pin, refresh must be held down */
+#ifndef CONFIG_KEYBOARD_MULTIPLE
 	if (!(system_get_reset_flags() & EC_RESET_FLAG_RESET_PIN) &&
 	    !(state[KEYBOARD_COL_REFRESH] & keyboard_mask_refresh))
 		return BOOT_KEY_NONE;
+#else
+	if (!(system_get_reset_flags() & EC_RESET_FLAG_RESET_PIN) &&
+	    !(state[key_typ.col_refresh] & keyboard_mask_refresh))
+		return BOOT_KEY_NONE;
+#endif
 
 	return check_key_list(state);
 }
@@ -757,7 +816,7 @@ static uint32_t check_boot_key(const uint8_t *state)
 static void keyboard_freq_change(void)
 {
 	post_scan_clock_us = (CONFIG_KEYBOARD_POST_SCAN_CLOCKS * 1000) /
-		(clock_get_freq() / 1000);
+			     (clock_get_freq() / 1000);
 }
 DECLARE_HOOK(HOOK_FREQ_CHANGE, keyboard_freq_change, HOOK_PRIO_DEFAULT);
 
@@ -793,8 +852,8 @@ void keyboard_scan_init(void)
 	}
 
 	/* Configure refresh key matrix */
-	keyboard_mask_refresh = KEYBOARD_ROW_TO_MASK(
-		board_keyboard_row_refresh());
+	keyboard_mask_refresh =
+		KEYBOARD_ROW_TO_MASK(board_keyboard_row_refresh());
 
 	if (!IS_ENABLED(CONFIG_KEYBOARD_SCAN_ADC))
 		/* Configure GPIO */
@@ -805,7 +864,7 @@ void keyboard_scan_init(void)
 
 	/* Initialize raw state */
 #ifndef CONFIG_KEYBOARD_SCAN_ADC
-	read_matrix(debounced_state);
+	read_matrix(debounced_state, true);
 #else
 	read_adc_boot_keys(debounced_state);
 #endif
@@ -875,7 +934,8 @@ void keyboard_scan_task(void *u)
 
 			if (local_disable_scanning != new_disable_scanning)
 				CPRINTS("KB disable_scanning_mask changed: "
-					"0x%08x", new_disable_scanning);
+					"0x%08x",
+					new_disable_scanning);
 
 			if (!new_disable_scanning) {
 				/* Enabled now */
@@ -910,7 +970,7 @@ void keyboard_scan_task(void *u)
 #else
 			if (!local_disable_scanning &&
 			    (keyboard_read_adc_rows() || force_poll ||
-					!gpio_get_level(GPIO_RFR_KEY_L)))
+			     !gpio_get_level(GPIO_RFR_KEY_L)))
 				break;
 #endif
 			else
@@ -931,15 +991,16 @@ void keyboard_scan_task(void *u)
 
 			/* Check for keys down */
 			if (check_keys_changed(debounced_state)) {
-				poll_deadline.val = start.val
-					+ keyscan_config.poll_timeout_us;
+				poll_deadline.val =
+					start.val +
+					keyscan_config.poll_timeout_us;
 			} else if (timestamp_expired(poll_deadline, &start)) {
 				break;
 			}
 
 			/* Delay between scans */
 			wait_time = keyscan_config.scan_period_us -
-				(get_time().val - start.val);
+				    (get_time().val - start.val);
 
 			if (wait_time < keyscan_config.min_post_scan_delay_us)
 				wait_time =
@@ -1001,8 +1062,7 @@ mkbp_command_simulate_key(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_MKBP_SIMULATE_KEY,
-		     mkbp_command_simulate_key,
+DECLARE_HOST_COMMAND(EC_CMD_MKBP_SIMULATE_KEY, mkbp_command_simulate_key,
 		     EC_VER_MASK(0));
 
 #ifdef CONFIG_KEYBOARD_FACTORY_TEST
@@ -1020,17 +1080,15 @@ int keyboard_factory_test_scan(void)
 
 	/* Set all of KSO/KSI pins to internal pull-up and input */
 	for (i = 0; i < keyboard_factory_scan_pins_used; i++) {
-
 		if (keyboard_factory_scan_pins[i][0] < 0)
 			continue;
 
 		port = keyboard_factory_scan_pins[i][0];
 		id = keyboard_factory_scan_pins[i][1];
 
-		gpio_set_alternate_function(port, 1 << id,
-					GPIO_ALT_FUNC_NONE);
+		gpio_set_alternate_function(port, 1 << id, GPIO_ALT_FUNC_NONE);
 		gpio_set_flags_by_mask(port, 1 << id,
-			GPIO_INPUT | GPIO_PULL_UP);
+				       GPIO_INPUT | GPIO_PULL_UP);
 	}
 
 	/*
@@ -1038,7 +1096,6 @@ int keyboard_factory_test_scan(void)
 	 * going to low level, it indicate the two pins are shorted.
 	 */
 	for (i = 0; i < keyboard_factory_scan_pins_used; i++) {
-
 		if (keyboard_factory_scan_pins[i][0] < 0)
 			continue;
 
@@ -1048,19 +1105,18 @@ int keyboard_factory_test_scan(void)
 		gpio_set_flags_by_mask(port, 1 << id, GPIO_OUT_LOW);
 
 		for (j = 0; j < keyboard_factory_scan_pins_used; j++) {
-
 			if (keyboard_factory_scan_pins[j][0] < 0 || i == j)
 				continue;
 
 			if (keyboard_raw_is_input_low(
-					keyboard_factory_scan_pins[j][0],
-					keyboard_factory_scan_pins[j][1])) {
+				    keyboard_factory_scan_pins[j][0],
+				    keyboard_factory_scan_pins[j][1])) {
 				shorted = i << 8 | j;
 				goto done;
 			}
 		}
 		gpio_set_flags_by_mask(port, 1 << id,
-			GPIO_INPUT | GPIO_PULL_UP);
+				       GPIO_INPUT | GPIO_PULL_UP);
 	}
 done:
 	gpio_config_module(MODULE_KEYBOARD_SCAN, 1);
@@ -1088,8 +1144,7 @@ static enum ec_status keyboard_factory_test(struct host_cmd_handler_args *args)
 	return EC_RES_SUCCESS;
 }
 
-DECLARE_HOST_COMMAND(EC_CMD_KEYBOARD_FACTORY_TEST,
-		     keyboard_factory_test,
+DECLARE_HOST_COMMAND(EC_CMD_KEYBOARD_FACTORY_TEST, keyboard_factory_test,
 		     EC_VER_MASK(0));
 #endif
 
@@ -1116,7 +1171,7 @@ int keyboard_get_keyboard_id(void)
 /*****************************************************************************/
 /* Console commands */
 #ifdef CONFIG_CMD_KEYBOARD
-static int command_ksstate(int argc, char **argv)
+static int command_ksstate(int argc, const char **argv)
 {
 	if (argc > 1) {
 		if (!strcasecmp(argv[1], "force")) {
@@ -1130,17 +1185,15 @@ static int command_ksstate(int argc, char **argv)
 	print_state(debounced_state, "debounced ");
 	print_state(debouncing, "debouncing");
 
-	ccprintf("Keyboard scan disable mask: 0x%08x\n",
-		 disable_scanning_mask);
+	ccprintf("Keyboard scan disable mask: 0x%08x\n", disable_scanning_mask);
 	ccprintf("Keyboard scan state printing %s\n",
 		 print_state_changes ? "on" : "off");
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(ksstate, command_ksstate,
-			"ksstate [on | off | force]",
+DECLARE_CONSOLE_COMMAND(ksstate, command_ksstate, "ksstate [on | off | force]",
 			"Show or toggle printing keyboard scan state");
 
-static int command_keyboard_press(int argc, char **argv)
+static int command_keyboard_press(int argc, const char **argv)
 {
 	if (argc == 1) {
 		int i, j;
@@ -1181,7 +1234,18 @@ static int command_keyboard_press(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(kbpress, command_keyboard_press,
-			"[col row [0 | 1]]",
+DECLARE_CONSOLE_COMMAND(kbpress, command_keyboard_press, "[col row [0 | 1]]",
 			"Simulate keypress");
 #endif
+
+#ifdef TEST_BUILD
+__test_only int keyboard_scan_get_print_state_changes(void)
+{
+	return print_state_changes;
+}
+
+__test_only void keyboard_scan_set_print_state_changes(int val)
+{
+	print_state_changes = val;
+}
+#endif /* TEST_BUILD */
diff --git a/common/keyboard_test.c b/common/keyboard_test.c
index e7b1dfe501..eb6fc11bdd 100644
--- a/common/keyboard_test.c
+++ b/common/keyboard_test.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2013 The Chromium OS Authors. All rights reserved.
+ * Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,8 +13,8 @@
 #include <util.h>
 
 enum {
-	KEYSCAN_MAX_LENGTH		= 20,
-	KEYSCAN_SEQ_START_DELAY_US	= 10000,
+	KEYSCAN_MAX_LENGTH = 20,
+	KEYSCAN_SEQ_START_DELAY_US = 10000,
 };
 
 static uint8_t keyscan_seq_count;
@@ -151,8 +151,8 @@ static int keyscan_seq_collect(struct ec_params_keyscan_seq_ctrl *req,
 	resp->collect.num_items = end - start;
 
 	for (i = start, ksi = keyscan_items; i < end; i++, ksi++)
-		resp->collect.item[i].flags = ksi->done ?
-						EC_KEYSCAN_SEQ_FLAG_DONE : 0;
+		resp->collect.item[i].flags =
+			ksi->done ? EC_KEYSCAN_SEQ_FLAG_DONE : 0;
 
 	return sizeof(*resp) + resp->collect.num_items;
 }
@@ -186,7 +186,8 @@ static enum ec_status keyscan_seq_ctrl(struct host_cmd_handler_args *args)
 		keyscan_seq_start();
 		break;
 	case EC_KEYSCAN_SEQ_COLLECT:
-		args->response_size = keyscan_seq_collect(&req,
+		args->response_size = keyscan_seq_collect(
+			&req,
 			(struct ec_result_keyscan_seq_ctrl *)args->response);
 		break;
 	default:
@@ -196,6 +197,4 @@ static enum ec_status keyscan_seq_ctrl(struct host_cmd_handler_args *args)
 	return EC_RES_SUCCESS;
 }
 
-DECLARE_HOST_COMMAND(EC_CMD_KEYSCAN_SEQ_CTRL,
-		     keyscan_seq_ctrl,
-		     EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_KEYSCAN_SEQ_CTRL, keyscan_seq_ctrl, EC_VER_MASK(0));
diff --git a/common/keyboard_vivaldi.c b/common/keyboard_vivaldi.c
index 1cab203857..11f5b708e6 100644
--- a/common/keyboard_vivaldi.c
+++ b/common/keyboard_vivaldi.c
@@ -1,10 +1,11 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Vivali Keyboard code for Chrome EC */
 
+#include "builtin/assert.h"
 #include "keyboard_8042_sharedlib.h"
 #include "keyboard_scan.h"
 #include "ec_commands.h"
@@ -15,7 +16,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_KEYBOARD, outstr)
-#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ##args)
 
 /*
  * Row Column info for Top row keys T1 - T15. This has been sourced from
@@ -25,21 +26,21 @@ __overridable const struct key {
 	uint8_t row;
 	uint8_t col;
 } vivaldi_keys[] = {
-	{.row = 0, .col = 2},	/* T1 */
-	{.row = 3, .col = 2},	/* T2 */
-	{.row = 2, .col = 2},	/* T3 */
-	{.row = 1, .col = 2},	/* T4 */
-	{.row = 3, .col = 4},	/* T5 */
-	{.row = 2, .col = 4},	/* T6 */
-	{.row = 1, .col = 4},	/* T7 */
-	{.row = 2, .col = 9},	/* T8 */
-	{.row = 1, .col = 9},	/* T9 */
-	{.row = 0, .col = 4},	/* T10 */
-	{.row = 0, .col = 1},	/* T11 */
-	{.row = 1, .col = 5},	/* T12 */
-	{.row = 3, .col = 5},	/* T13 */
-	{.row = 0, .col = 9},	/* T14 */
-	{.row = 0, .col = 11},	/* T15 */
+	{ .row = 0, .col = 2 }, /* T1 */
+	{ .row = 3, .col = 2 }, /* T2 */
+	{ .row = 2, .col = 2 }, /* T3 */
+	{ .row = 1, .col = 2 }, /* T4 */
+	{ .row = 3, .col = 4 }, /* T5 */
+	{ .row = 2, .col = 4 }, /* T6 */
+	{ .row = 1, .col = 4 }, /* T7 */
+	{ .row = 2, .col = 9 }, /* T8 */
+	{ .row = 1, .col = 9 }, /* T9 */
+	{ .row = 0, .col = 4 }, /* T10 */
+	{ .row = 0, .col = 1 }, /* T11 */
+	{ .row = 1, .col = 5 }, /* T12 */
+	{ .row = 3, .col = 5 }, /* T13 */
+	{ .row = 0, .col = 9 }, /* T14 */
+	{ .row = 0, .col = 11 }, /* T15 */
 };
 BUILD_ASSERT(ARRAY_SIZE(vivaldi_keys) == MAX_TOP_ROW_KEYS);
 
@@ -69,8 +70,8 @@ static const uint16_t action_scancodes[] = {
 
 static const struct ec_response_keybd_config *vivaldi_keybd;
 
-static enum
-ec_status get_vivaldi_keybd_config(struct host_cmd_handler_args *args)
+static enum ec_status
+get_vivaldi_keybd_config(struct host_cmd_handler_args *args)
 {
 	struct ec_response_keybd_config *resp = args->response;
 
@@ -90,8 +91,8 @@ DECLARE_HOST_COMMAND(EC_CMD_GET_KEYBD_CONFIG, get_vivaldi_keybd_config,
  * Boards selecting CONFIG_KEYBOARD_CUSTOMIZATION are likely to not
  * want vivaldi code messing with their customized keyboards.
  */
-__overridable
-const struct ec_response_keybd_config *board_vivaldi_keybd_config(void)
+__overridable const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	return NULL;
 }
@@ -117,8 +118,8 @@ static const struct ec_response_keybd_config default_keybd = {
 	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
 };
 
-__overridable
-const struct ec_response_keybd_config *board_vivaldi_keybd_config(void)
+__overridable const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	return &default_keybd;
 }
@@ -149,7 +150,6 @@ static void vivaldi_init(void)
 	}
 
 	for (i = 0; i < ARRAY_SIZE(vivaldi_keys); i++) {
-
 		uint8_t row, col, *mask;
 		enum action_key key;
 
@@ -157,8 +157,8 @@ static void vivaldi_init(void)
 		col = vivaldi_keys[i].col;
 
 		if (col >= KEYBOARD_COLS_MAX || row >= KEYBOARD_ROWS) {
-			CPRINTS("VIVALDI: Bad (row,col) for T-%u: (%u,%u)",
-				i, row, col);
+			CPRINTS("VIVALDI: Bad (row,col) for T-%u: (%u,%u)", i,
+				row, col);
 			ASSERT(false);
 		}
 
@@ -171,18 +171,16 @@ static void vivaldi_init(void)
 		key = vivaldi_keybd->action_keys[i];
 
 		if (i < vivaldi_keybd->num_top_row_keys && key != TK_ABSENT) {
-
 			/* Enable the mask */
 			*mask |= BIT(row);
 
 			/* Populate the scancode */
 			set_scancode_set2(row, col, action_scancodes[key]);
-			CPRINTS("VIVALDI key-%u (r-%u, c-%u) = scancode-%X",
-				i, row, col, action_scancodes[key]);
+			CPRINTS("VIVALDI key-%u (r-%u, c-%u) = scancode-%X", i,
+				row, col, action_scancodes[key]);
 
 			if (key == TK_VOL_UP)
 				set_vol_up_key(row, col);
-
 		}
 	}
 }
diff --git a/common/lb_common.c b/common/lb_common.c
index 019e0e254f..eca21bfb03 100644
--- a/common/lb_common.c
+++ b/common/lb_common.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -97,12 +97,13 @@
 #include "ec_commands.h"
 #include "i2c.h"
 #include "lb_common.h"
+#include "printf.h"
 #include "util.h"
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_LIGHTBAR, outstr)
-#define CPRINTF(format, args...) cprintf(CC_LIGHTBAR, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_LIGHTBAR, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_LIGHTBAR, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_LIGHTBAR, format, ##args)
 
 /******************************************************************************/
 /* How to talk to the controller */
@@ -120,9 +121,8 @@ static inline void controller_write(int ctrl_num, uint8_t reg, uint8_t val)
 	buf[0] = reg;
 	buf[1] = val;
 	ctrl_num = ctrl_num % ARRAY_SIZE(i2c_addr_flags);
-	i2c_xfer_unlocked(I2C_PORT_LIGHTBAR, i2c_addr_flags[ctrl_num],
-			buf, 2, 0, 0,
-			I2C_XFER_SINGLE);
+	i2c_xfer_unlocked(I2C_PORT_LIGHTBAR, i2c_addr_flags[ctrl_num], buf, 2,
+			  0, 0, I2C_XFER_SINGLE);
 }
 
 static inline uint8_t controller_read(int ctrl_num, uint8_t reg)
@@ -132,7 +132,7 @@ static inline uint8_t controller_read(int ctrl_num, uint8_t reg)
 
 	ctrl_num = ctrl_num % ARRAY_SIZE(i2c_addr_flags);
 	rv = i2c_xfer_unlocked(I2C_PORT_LIGHTBAR, i2c_addr_flags[ctrl_num],
-			&reg, 1, buf, 1, I2C_XFER_SINGLE);
+			       &reg, 1, buf, 1, I2C_XFER_SINGLE);
 	return rv ? 0 : buf[0];
 }
 
@@ -149,15 +149,15 @@ static inline uint8_t controller_read(int ctrl_num, uint8_t reg)
  * I've lowered the other colors until they all appear approximately equal
  * brightness when full on. That's still pretty bright and a lot of current
  * drain on the battery, so we'll probably rarely go that high. */
-#define MAX_RED   0x5c
+#define MAX_RED 0x5c
 #define MAX_GREEN 0x30
-#define MAX_BLUE  0x67
+#define MAX_BLUE 0x67
 #endif
 #ifdef BOARD_HOST
 /* For testing only */
-#define MAX_RED   0xff
+#define MAX_RED 0xff
 #define MAX_GREEN 0xff
-#define MAX_BLUE  0xff
+#define MAX_BLUE 0xff
 #endif
 
 /* How we'd like to see the driver chips initialized. The controllers have some
@@ -169,20 +169,20 @@ struct initdata_s {
 };
 
 static const struct initdata_s init_vals[] = {
-	{0x04, 0x00},				/* no backlight function */
-	{0x05, 0x3f},				/* xRGBRGB per chip */
-	{0x0f, 0x01},				/* square law looks better */
-	{0x10, 0x3f},				/* enable independent LEDs */
-	{0x11, 0x00},				/* no auto cycling */
-	{0x12, 0x00},				/* no auto cycling */
-	{0x13, 0x00},				/* instant fade in/out */
-	{0x14, 0x00},				/* not using LED 7 */
-	{0x15, 0x00},				/* current for LED 6 (blue) */
-	{0x16, 0x00},				/* current for LED 5 (red) */
-	{0x17, 0x00},				/* current for LED 4 (green) */
-	{0x18, 0x00},				/* current for LED 3 (blue) */
-	{0x19, 0x00},				/* current for LED 2 (red) */
-	{0x1a, 0x00},				/* current for LED 1 (green) */
+	{ 0x04, 0x00 }, /* no backlight function */
+	{ 0x05, 0x3f }, /* xRGBRGB per chip */
+	{ 0x0f, 0x01 }, /* square law looks better */
+	{ 0x10, 0x3f }, /* enable independent LEDs */
+	{ 0x11, 0x00 }, /* no auto cycling */
+	{ 0x12, 0x00 }, /* no auto cycling */
+	{ 0x13, 0x00 }, /* instant fade in/out */
+	{ 0x14, 0x00 }, /* not using LED 7 */
+	{ 0x15, 0x00 }, /* current for LED 6 (blue) */
+	{ 0x16, 0x00 }, /* current for LED 5 (red) */
+	{ 0x17, 0x00 }, /* current for LED 4 (green) */
+	{ 0x18, 0x00 }, /* current for LED 3 (blue) */
+	{ 0x19, 0x00 }, /* current for LED 2 (red) */
+	{ 0x1a, 0x00 }, /* current for LED 1 (green) */
 };
 
 /* Controller register lookup tables. */
@@ -198,7 +198,7 @@ static const uint8_t led_to_isc[] = { 0x15, 0x18, 0x15, 0x18 };
 /* Scale 0-255 into max value */
 static inline uint8_t scale_abs(int val, int max)
 {
-	return (val * max)/255;
+	return (val * max) / 255;
 }
 
 /* This is the overall brightness control. */
@@ -211,7 +211,7 @@ static uint8_t current[NUM_LEDS][3];
 /* Scale 0-255 by brightness */
 static inline uint8_t scale(int val, int max)
 {
-	return scale_abs((val * brightness)/255, max);
+	return scale_abs((val * brightness) / 255, max);
 }
 
 /* Helper function to set one LED color and remember it for later */
@@ -225,8 +225,8 @@ static void setrgb(int led, int red, int green, int blue)
 	bank = led_to_isc[led];
 	i2c_lock(I2C_PORT_LIGHTBAR, 1);
 	controller_write(ctrl, bank, scale(blue, MAX_BLUE));
-	controller_write(ctrl, bank+1, scale(red, MAX_RED));
-	controller_write(ctrl, bank+2, scale(green, MAX_GREEN));
+	controller_write(ctrl, bank + 1, scale(red, MAX_RED));
+	controller_write(ctrl, bank + 2, scale(green, MAX_GREEN));
 	i2c_lock(I2C_PORT_LIGHTBAR, 0);
 }
 
@@ -275,8 +275,10 @@ uint8_t lb_get_brightness(void)
 void lb_init(int use_lock)
 {
 	int i;
+	char ts_str[PRINTF_TIMESTAMP_BUF_SIZE];
 
-	CPRINTF("[%pT LB_init_vals ", PRINTF_TIMESTAMP_NOW);
+	snprintf_timestamp_now(ts_str, sizeof(ts_str));
+	CPRINTF("[%s LB_init_vals ", ts_str);
 	for (i = 0; i < ARRAY_SIZE(init_vals); i++) {
 		CPRINTF("%c", '0' + i % 10);
 		if (use_lock)
@@ -310,12 +312,10 @@ void lb_on(void)
 	i2c_lock(I2C_PORT_LIGHTBAR, 0);
 }
 
-static const uint8_t dump_reglist[] = {
-	0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
-	0x08, 0x09, 0x0a,			  0x0f,
-	0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
-	0x18, 0x19, 0x1a
-};
+static const uint8_t dump_reglist[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
+					0x06, 0x07, 0x08, 0x09, 0x0a, 0x0f,
+					0x10, 0x11, 0x12, 0x13, 0x14, 0x15,
+					0x16, 0x17, 0x18, 0x19, 0x1a };
 
 /* Helper for host command to dump controller registers */
 void lb_hc_cmd_dump(struct ec_response_lightbar *out)
@@ -323,8 +323,7 @@ void lb_hc_cmd_dump(struct ec_response_lightbar *out)
 	int i;
 	uint8_t reg;
 
-	BUILD_ASSERT(ARRAY_SIZE(dump_reglist) ==
-		     ARRAY_SIZE(out->dump.vals));
+	BUILD_ASSERT(ARRAY_SIZE(dump_reglist) == ARRAY_SIZE(out->dump.vals));
 
 	for (i = 0; i < ARRAY_SIZE(dump_reglist); i++) {
 		reg = dump_reglist[i];
diff --git a/common/led_common.c b/common/led_common.c
index e890ad71bb..2c73ba95e6 100644
--- a/common/led_common.c
+++ b/common/led_common.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -91,8 +91,8 @@ static enum ec_status led_command_control(struct host_cmd_handler_args *args)
 }
 DECLARE_HOST_COMMAND(EC_CMD_LED_CONTROL, led_command_control, EC_VER_MASK(1));
 
-__attribute__((weak))
-void led_control(enum ec_led_id led_id, enum ec_led_state state)
+__attribute__((weak)) void led_control(enum ec_led_id led_id,
+				       enum ec_led_state state)
 {
 	/*
 	 * Default weak implementation that does not affect the state of
diff --git a/common/led_onoff_states.c b/common/led_onoff_states.c
index 48886e5de3..244257cf1d 100644
--- a/common/led_onoff_states.c
+++ b/common/led_onoff_states.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -17,14 +17,14 @@
 #include "system.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
 
 /*
  * In order to support the battery LED being optional (ex. for Chromeboxes),
  * set up default battery table, setter, and variables.
  */
-__overridable struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES];
+__overridable struct led_descriptor led_bat_state_table[LED_NUM_STATES]
+						       [LED_NUM_PHASES];
 __overridable const int led_charge_lvl_1;
 __overridable const int led_charge_lvl_2;
 __overridable void led_set_color_battery(enum ec_led_colors color)
@@ -43,7 +43,7 @@ static int led_get_charge_percent(void)
 
 static enum led_states led_get_state(void)
 {
-	int  charge_lvl;
+	int charge_lvl;
 	enum led_states new_state = LED_NUM_STATES;
 
 	if (!IS_ENABLED(CONFIG_CHARGER))
@@ -58,11 +58,10 @@ static enum led_states led_get_state(void)
 			new_state = STATE_CHARGING_LVL_1;
 		else if (charge_lvl < led_charge_lvl_2)
 			new_state = STATE_CHARGING_LVL_2;
+		else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+			new_state = STATE_CHARGING_FULL_S5;
 		else
-			if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
-				new_state = STATE_CHARGING_FULL_S5;
-			else
-				new_state = STATE_CHARGING_FULL_CHARGE;
+			new_state = STATE_CHARGING_FULL_CHARGE;
 		break;
 	case PWR_STATE_DISCHARGE_FULL:
 		if (extpower_is_present()) {
@@ -77,7 +76,7 @@ static enum led_states led_get_state(void)
 		if (chipset_in_state(CHIPSET_STATE_ON)) {
 #ifdef CONFIG_LED_ONOFF_STATES_BAT_LOW
 			if (led_get_charge_percent() <
-				CONFIG_LED_ONOFF_STATES_BAT_LOW)
+			    CONFIG_LED_ONOFF_STATES_BAT_LOW)
 				new_state = STATE_DISCHARGE_S0_BAT_LOW;
 			else
 #endif
@@ -97,13 +96,14 @@ static enum led_states led_get_state(void)
 			new_state = STATE_CHARGING_FULL_CHARGE;
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE */
-		if (charge_get_flags() & CHARGE_FLAG_FORCE_IDLE)
-			new_state = STATE_FACTORY_TEST;
-		else if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
 			new_state = STATE_DISCHARGE_S5;
 		else
 			new_state = STATE_DISCHARGE_S0;
 		break;
+	case PWR_STATE_FORCED_IDLE:
+		new_state = STATE_FACTORY_TEST;
+		break;
 	default:
 		/* Other states don't alter LED behavior */
 		break;
@@ -147,14 +147,14 @@ static void led_update_battery(void)
 		ticks = 0;
 
 		period = led_bat_state_table[led_state][LED_PHASE_0].time +
-			led_bat_state_table[led_state][LED_PHASE_1].time;
-
+			 led_bat_state_table[led_state][LED_PHASE_1].time;
 	}
 
 	/* If this state is undefined, turn the LED off */
 	if (period == 0) {
 		CPRINTS("Undefined LED behavior for battery state %d,"
-			"turning off LED", led_state);
+			"turning off LED",
+			led_state);
 		led_set_color_battery(LED_OFF);
 		return;
 	}
@@ -163,8 +163,8 @@ static void led_update_battery(void)
 	 * Determine which phase of the state table to use. The phase is
 	 * determined if it falls within first phase time duration.
 	 */
-	phase = ticks < led_bat_state_table[led_state][LED_PHASE_0].time ?
-									0 : 1;
+	phase = ticks < led_bat_state_table[led_state][LED_PHASE_0].time ? 0 :
+									   1;
 	ticks = (ticks + 1) % period;
 
 	/* Set the color for the given state and phase */
@@ -176,7 +176,7 @@ static void led_update_battery(void)
  * table and setter
  */
 __overridable const struct led_descriptor
-			led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES];
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES];
 __overridable void led_set_color_power(enum ec_led_colors color)
 {
 }
@@ -226,14 +226,14 @@ static void led_update_power(void)
 		ticks = 0;
 
 		period = led_pwr_state_table[led_state][LED_PHASE_0].time +
-			led_pwr_state_table[led_state][LED_PHASE_1].time;
-
+			 led_pwr_state_table[led_state][LED_PHASE_1].time;
 	}
 
 	/* If this state is undefined, turn the LED off */
 	if (period == 0) {
 		CPRINTS("Undefined LED behavior for power state %d,"
-			"turning off LED", led_state);
+			"turning off LED",
+			led_state);
 		led_set_color_power(LED_OFF);
 		return;
 	}
@@ -242,13 +242,12 @@ static void led_update_power(void)
 	 * Determine which phase of the state table to use. The phase is
 	 * determined if it falls within first phase time duration.
 	 */
-	phase = ticks < led_pwr_state_table[led_state][LED_PHASE_0].time ?
-									0 : 1;
+	phase = ticks < led_pwr_state_table[led_state][LED_PHASE_0].time ? 0 :
+									   1;
 	ticks = (ticks + 1) % period;
 
 	/* Set the color for the given state and phase */
 	led_set_color_power(led_pwr_state_table[led_state][phase].color);
-
 }
 
 static void led_init(void)
@@ -260,7 +259,6 @@ static void led_init(void)
 	/* If power LED is enabled, set it to "off" to start with */
 	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
 		led_set_color_power(LED_OFF);
-
 }
 DECLARE_HOOK(HOOK_INIT, led_init, HOOK_PRIO_DEFAULT);
 
diff --git a/common/led_policy_std.c b/common/led_policy_std.c
index 65bf8cedbd..fe8570df87 100644
--- a/common/led_policy_std.c
+++ b/common/led_policy_std.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -31,8 +31,8 @@
 #define POWER_LED_OFF 0
 #endif
 
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED, EC_LED_ID_POWER_LED};
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
 
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
@@ -42,7 +42,7 @@ enum led_color {
 	LED_AMBER,
 	LED_GREEN,
 	LED_WHITE,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 static int bat_led_set_color(enum led_color color)
@@ -108,15 +108,18 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 	case EC_LED_ID_BATTERY_LED:
 		gpio_set_level(GPIO_BAT_LED_RED,
 			       (brightness[EC_LED_COLOR_RED] != 0) ?
-					BAT_LED_ON : BAT_LED_OFF);
+				       BAT_LED_ON :
+				       BAT_LED_OFF);
 		gpio_set_level(GPIO_BAT_LED_GREEN,
 			       (brightness[EC_LED_COLOR_GREEN] != 0) ?
-					BAT_LED_ON : BAT_LED_OFF);
+				       BAT_LED_ON :
+				       BAT_LED_OFF);
 		break;
 	case EC_LED_ID_POWER_LED:
 		gpio_set_level(GPIO_POWER_LED,
 			       (brightness[EC_LED_COLOR_WHITE] != 0) ?
-					POWER_LED_ON : POWER_LED_OFF);
+				       POWER_LED_ON :
+				       POWER_LED_OFF);
 		break;
 	default:
 		return EC_ERROR_UNKNOWN;
@@ -149,7 +152,6 @@ static void std_led_set_power(void)
 static void std_led_set_battery(void)
 {
 	static int battery_second;
-	uint32_t chflags = charge_get_flags();
 
 	battery_second++;
 
@@ -163,11 +165,11 @@ static void std_led_set_battery(void)
 		break;
 	case PWR_STATE_DISCHARGE:
 		if (charge_get_percent() < 3)
-			bat_led_set_color((battery_second & 1)
-					? LED_OFF : LED_AMBER);
+			bat_led_set_color((battery_second & 1) ? LED_OFF :
+								 LED_AMBER);
 		else if (charge_get_percent() < 10)
-			bat_led_set_color((battery_second & 3)
-					? LED_OFF : LED_AMBER);
+			bat_led_set_color((battery_second & 3) ? LED_OFF :
+								 LED_AMBER);
 		else
 			bat_led_set_color(LED_OFF);
 		break;
@@ -178,11 +180,11 @@ static void std_led_set_battery(void)
 		bat_led_set_color(LED_GREEN);
 		break;
 	case PWR_STATE_IDLE: /* External power connected in IDLE. */
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			bat_led_set_color(
-				(battery_second & 0x2) ? LED_GREEN : LED_AMBER);
-		else
-			bat_led_set_color(LED_GREEN);
+		bat_led_set_color(LED_GREEN);
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		bat_led_set_color((battery_second & 0x2) ? LED_GREEN :
+							   LED_AMBER);
 		break;
 	default:
 		/* Other states don't alter LED behavior */
diff --git a/common/led_pwm.c b/common/led_pwm.c
index 05fe21e82b..c088ba0b40 100644
--- a/common/led_pwm.c
+++ b/common/led_pwm.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -262,10 +262,10 @@ static void update_leds(void)
 }
 DECLARE_HOOK(HOOK_TICK, update_leds, HOOK_PRIO_DEFAULT);
 
-#endif/* CONFIG_LED_PWM_TASK_DISABLED */
+#endif /* CONFIG_LED_PWM_TASK_DISABLED */
 
 #ifdef CONFIG_CMD_LEDTEST
-static int command_ledtest(int argc, char **argv)
+static int command_ledtest(int argc, const char **argv)
 {
 	int enable;
 	int pwm_led_id;
@@ -280,9 +280,8 @@ static int command_ledtest(int argc, char **argv)
 	led_id = supported_led_ids[pwm_led_id];
 
 	if (argc == 2) {
-		ccprintf("PWM LED %d: led_id=%d, auto_control=%d\n",
-			 pwm_led_id, led_id,
-			 led_auto_control_is_enabled(led_id) != 0);
+		ccprintf("PWM LED %d: led_id=%d, auto_control=%d\n", pwm_led_id,
+			 led_id, led_auto_control_is_enabled(led_id) != 0);
 		return EC_SUCCESS;
 	}
 	if (!parse_bool(argv[2], &enable))
diff --git a/common/lid_angle.c b/common/lid_angle.c
index 8a3775b959..86b6884058 100644
--- a/common/lid_angle.c
+++ b/common/lid_angle.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,7 +19,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_LIDANGLE, outstr)
-#define CPRINTS(format, args...) cprints(CC_LIDANGLE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_LIDANGLE, format, ##args)
 
 /*
  * Define the number of previous lid angle measurements to keep for determining
@@ -50,7 +50,7 @@ static int wake_large_angle = 180;
 static const int wake_small_angle = 13;
 
 /* Define hysteresis value to add stability to the flags. */
-#define LID_ANGLE_HYSTERESIS_DEG  2
+#define LID_ANGLE_HYSTERESIS_DEG 2
 
 /* Define max and min values for wake_large_angle. */
 #define LID_ANGLE_MIN_LARGE_ANGLE 0
@@ -74,8 +74,8 @@ static int lid_in_range_to_enable_peripherals(int ang)
 	else if (wake_large_angle == LID_ANGLE_MAX_LARGE_ANGLE)
 		return 1;
 
-	return  (ang >= (wake_small_angle + LID_ANGLE_HYSTERESIS_DEG)) &&
-		(ang <= (wake_large_angle - LID_ANGLE_HYSTERESIS_DEG));
+	return (ang >= (wake_small_angle + LID_ANGLE_HYSTERESIS_DEG)) &&
+	       (ang <= (wake_large_angle - LID_ANGLE_HYSTERESIS_DEG));
 }
 
 /**
@@ -96,11 +96,10 @@ static int lid_in_range_to_ignore_peripherals(int ang)
 	else if (wake_large_angle == LID_ANGLE_MAX_LARGE_ANGLE)
 		return 0;
 
-	return  (ang <= (wake_small_angle - LID_ANGLE_HYSTERESIS_DEG)) ||
-		(ang >= (wake_large_angle + LID_ANGLE_HYSTERESIS_DEG));
+	return (ang <= (wake_small_angle - LID_ANGLE_HYSTERESIS_DEG)) ||
+	       (ang >= (wake_large_angle + LID_ANGLE_HYSTERESIS_DEG));
 }
 
-
 int lid_angle_get_wake_angle(void)
 {
 	return wake_large_angle;
@@ -125,7 +124,7 @@ void lid_angle_update(int lid_ang)
 
 	/* Record most recent lid angle in circular buffer. */
 	lidangle_buffer[index] = lid_ang;
-	index = (index == LID_ANGLE_BUFFER_SIZE-1) ? 0 : index+1;
+	index = (index == LID_ANGLE_BUFFER_SIZE - 1) ? 0 : index + 1;
 
 	/*
 	 * Manage whether or not peripherals are enabled based on lid angle
diff --git a/common/lid_switch.c b/common/lid_switch.c
index 050bbd9512..f0231b1ee7 100644
--- a/common/lid_switch.c
+++ b/common/lid_switch.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,15 +16,15 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_SWITCH, outstr)
-#define CPRINTS(format, args...) cprints(CC_SWITCH, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SWITCH, format, ##args)
 
 /* if no X-macro is defined for LID switch GPIO, use GPIO_LID_OPEN as default */
 #ifndef CONFIG_LID_SWITCH_GPIO_LIST
 #define CONFIG_LID_SWITCH_GPIO_LIST LID_GPIO(GPIO_LID_OPEN)
 #endif
 
-static int debounced_lid_open;		/* Debounced lid state */
-static int forced_lid_open;	/* Forced lid open */
+static int debounced_lid_open; /* Debounced lid state */
+static int forced_lid_open; /* Forced lid open */
 
 /**
  * Get raw lid switch state.
@@ -87,7 +87,7 @@ static void lid_init(void)
 	if (raw_lid_open())
 		debounced_lid_open = 1;
 
-	/* Enable interrupts, now that we've initialized */
+		/* Enable interrupts, now that we've initialized */
 #define LID_GPIO(gpio) gpio_enable_interrupt(gpio);
 	CONFIG_LID_SWITCH_GPIO_LIST
 #undef LID_GPIO
@@ -133,33 +133,27 @@ void enable_lid_detect(bool enable)
 	}
 }
 
-static int command_lidopen(int argc, char **argv)
+static int command_lidopen(int argc, const char **argv)
 {
 	lid_switch_open();
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(lidopen, command_lidopen,
-			NULL,
-			"Simulate lid open");
+DECLARE_CONSOLE_COMMAND(lidopen, command_lidopen, NULL, "Simulate lid open");
 
-static int command_lidclose(int argc, char **argv)
+static int command_lidclose(int argc, const char **argv)
 {
 	lid_switch_close();
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(lidclose, command_lidclose,
-			NULL,
-			"Simulate lid close");
+DECLARE_CONSOLE_COMMAND(lidclose, command_lidclose, NULL, "Simulate lid close");
 
-static int command_lidstate(int argc, char **argv)
+static int command_lidstate(int argc, const char **argv)
 {
 	ccprintf("lid state: %s\n", debounced_lid_open ? "open" : "closed");
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(lidstate, command_lidstate,
-			NULL,
-			"Get state of lid");
+DECLARE_CONSOLE_COMMAND(lidstate, command_lidstate, NULL, "Get state of lid");
 
 /**
  * Host command to enable/disable lid opened.
@@ -167,14 +161,15 @@ DECLARE_CONSOLE_COMMAND(lidstate, command_lidstate,
 static enum ec_status hc_force_lid_open(struct host_cmd_handler_args *args)
 {
 	const struct ec_params_force_lid_open *p = args->params;
+	int old_state = forced_lid_open;
 
 	/* Override lid open if necessary */
 	forced_lid_open = p->enabled ? 1 : 0;
 
 	/* Make this take effect immediately; no debounce time */
-	hook_call_deferred(&lid_change_deferred_data, 0);
+	if (forced_lid_open != old_state)
+		hook_call_deferred(&lid_change_deferred_data, 0);
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_FORCE_LID_OPEN, hc_force_lid_open,
-		     EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_FORCE_LID_OPEN, hc_force_lid_open, EC_VER_MASK(0));
diff --git a/common/lightbar.c b/common/lightbar.c
index f80287941d..8a6a874b34 100644
--- a/common/lightbar.c
+++ b/common/lightbar.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2012 The Chromium OS Authors. All rights reserved.
+ * Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -33,11 +33,11 @@
  * optional features in the current version should be marked with flags.
  */
 #define LIGHTBAR_IMPLEMENTATION_VERSION 1
-#define LIGHTBAR_IMPLEMENTATION_FLAGS   0
+#define LIGHTBAR_IMPLEMENTATION_FLAGS 0
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_LIGHTBAR, outstr)
-#define CPRINTS(format, args...) cprints(CC_LIGHTBAR, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_LIGHTBAR, format, ##args)
 
 #define FP_SCALE 10000
 
@@ -61,10 +61,10 @@ static struct p_state {
 	int battery_is_power_on_prevented;
 
 	/* Pattern variables for state S0. */
-	uint16_t w0;				/* primary phase */
-	uint8_t ramp;				/* ramp-in for S3->S0 */
+	uint16_t w0; /* primary phase */
+	uint8_t ramp; /* ramp-in for S3->S0 */
 
-	uint8_t _pad0;				/* next item is __packed */
+	uint8_t _pad0; /* next item is __packed */
 
 	/* Tweakable parameters. */
 	union {
@@ -162,7 +162,7 @@ static const struct lightbar_params_v1 default_params = {
 	},
 };
 
-#define LB_SYSJUMP_TAG 0x4c42			/* "LB" */
+#define LB_SYSJUMP_TAG 0x4c42 /* "LB" */
 static void lightbar_preserve_state(void)
 {
 	system_add_jump_tag(LB_SYSJUMP_TAG, 0, sizeof(st), &st);
@@ -177,10 +177,8 @@ static void lightbar_restore_state(void)
 	old_state = system_get_jump_tag(LB_SYSJUMP_TAG, 0, &size);
 	if (old_state && size == sizeof(st)) {
 		memcpy(&st, old_state, size);
-		CPRINTS("LB state restored: %d %d - %d %d/%d",
-			st.cur_seq, st.prev_seq,
-			st.battery_is_charging,
-			st.battery_percent,
+		CPRINTS("LB state restored: %d %d - %d %d/%d", st.cur_seq,
+			st.prev_seq, st.battery_is_charging, st.battery_percent,
 			st.battery_level);
 	} else {
 		st.cur_seq = st.prev_seq = LIGHTBAR_S5;
@@ -234,7 +232,7 @@ test_export_static int lux_level_to_google_color(const int lux)
 	}
 
 	/* See if we need to decrease brightness */
-	for (i = google_color_id; i < lb_brightness_levels_count ; i++)
+	for (i = google_color_id; i < lb_brightness_levels_count; i++)
 		if (lux >= lb_brightness_levels[i].lux_down)
 			break;
 	if (i > google_color_id) {
@@ -242,7 +240,7 @@ test_export_static int lux_level_to_google_color(const int lux)
 		return 1;
 	}
 	/* See if we need to increase brightness */
-	for (i = google_color_id; i > 0;  i--)
+	for (i = google_color_id; i > 0; i--)
 		if (lux < lb_brightness_levels[i - 1].lux_up)
 			break;
 	if (i < google_color_id) {
@@ -276,8 +274,8 @@ static int get_battery_level(void)
 
 	/* Use some hysteresis to avoid flickering */
 	if (bl < st.battery_level ||
-	    (bl > st.battery_level
-	     && pct >= (st.p.battery_threshold[st.battery_level] + 1))) {
+	    (bl > st.battery_level &&
+	     pct >= (st.p.battery_threshold[st.battery_level] + 1))) {
 		st.battery_level = bl;
 		change = 1;
 	}
@@ -294,7 +292,7 @@ static int get_battery_level(void)
 	 */
 	if (pwm_get_enabled(PWM_CH_KBLIGHT)) {
 		pct = pwm_get_duty(PWM_CH_KBLIGHT);
-		pct = (255 * pct) / 100;  /* 00 - FF */
+		pct = (255 * pct) / 100; /* 00 - FF */
 		if (pct > st.p.bright_bl_on_max[st.battery_is_charging])
 			pct = st.p.bright_bl_on_max[st.battery_is_charging];
 		else if (pct < st.p.bright_bl_on_min[st.battery_is_charging])
@@ -350,8 +348,7 @@ void demo_is_charging(int ischarge)
 		return;
 
 	st.battery_is_charging = ischarge;
-	CPRINTS("LB demo: battery_is_charging=%d",
-		st.battery_is_charging);
+	CPRINTS("LB demo: battery_is_charging=%d", st.battery_is_charging);
 }
 
 /* Bright/Dim keys */
@@ -409,7 +406,7 @@ static inline int cycle_010(uint8_t i)
 	index = i & 0x3;
 
 	return _ramp_table[bucket] +
-		((_ramp_table[bucket + 1] - _ramp_table[bucket]) * index >> 2);
+	       ((_ramp_table[bucket + 1] - _ramp_table[bucket]) * index >> 2);
 }
 
 /******************************************************************************/
@@ -421,12 +418,12 @@ static uint32_t pending_msg;
 #define PENDING_MSG TASK_EVENT_CUSTOM_BIT(0)
 
 /* Interruptible delay. */
-#define WAIT_OR_RET(A)                                                         \
-	do {                                                                   \
-		uint32_t msg = task_wait_event(A);                             \
-		uint32_t p_msg = pending_msg;                                  \
-		if (msg & PENDING_MSG && p_msg != st.cur_seq)                  \
-			return p_msg;                                          \
+#define WAIT_OR_RET(A)                                        \
+	do {                                                  \
+		uint32_t msg = task_wait_event(A);            \
+		uint32_t p_msg = pending_msg;                 \
+		if (msg & PENDING_MSG && p_msg != st.cur_seq) \
+			return p_msg;                         \
 	} while (0)
 
 /******************************************************************************/
@@ -501,7 +498,7 @@ static uint32_t sequence_S3S0(void)
 	}
 
 	/* Initial conditions */
-	st.w0 = -256;				/* start cycle_npn() quietly */
+	st.w0 = -256; /* start cycle_npn() quietly */
 	st.ramp = 0;
 
 	/* Ready for S0 */
@@ -583,7 +580,7 @@ static uint32_t sequence_S0(void)
 	return 0;
 }
 
-#else  /* just simple google colors */
+#else /* just simple google colors */
 
 static uint32_t sequence_S0(void)
 {
@@ -711,7 +708,6 @@ static uint32_t sequence_S3(void)
 	return 0;
 }
 
-
 /* CPU is powering up. We generally boot fast enough that we don't have time
  * to do anything interesting in the S3 state, but go straight on to S0. */
 static uint32_t sequence_S5S3(void)
@@ -817,12 +813,10 @@ static uint32_t sequence_STOP(void)
 	do {
 		msg = task_wait_event(-1);
 		CPRINTS("LB %s() got pending_msg %d", __func__, pending_msg);
-	} while (msg != PENDING_MSG || (
-			 pending_msg != LIGHTBAR_RUN &&
-			 pending_msg != LIGHTBAR_S0S3 &&
-			 pending_msg != LIGHTBAR_S3 &&
-			 pending_msg != LIGHTBAR_S3S5 &&
-			 pending_msg != LIGHTBAR_S5));
+	} while (msg != PENDING_MSG ||
+		 (pending_msg != LIGHTBAR_RUN && pending_msg != LIGHTBAR_S0S3 &&
+		  pending_msg != LIGHTBAR_S3 && pending_msg != LIGHTBAR_S3S5 &&
+		  pending_msg != LIGHTBAR_S5));
 	return 0;
 }
 
@@ -856,73 +850,47 @@ static const struct {
 	unsigned int delay;
 } konami[] = {
 
-	{1, 0xff, 0xff, 0x00, 0},
-	{2, 0xff, 0xff, 0x00, 100000},
-	{1, 0x00, 0x00, 0x00, 0},
-	{2, 0x00, 0x00, 0x00, 100000},
-
-	{1, 0xff, 0xff, 0x00, 0},
-	{2, 0xff, 0xff, 0x00, 100000},
-	{1, 0x00, 0x00, 0x00, 0},
-	{2, 0x00, 0x00, 0x00, 100000},
-
-	{0, 0x00, 0x00, 0xff, 0},
-	{3, 0x00, 0x00, 0xff, 100000},
-	{0, 0x00, 0x00, 0x00, 0},
-	{3, 0x00, 0x00, 0x00, 100000},
-
-	{0, 0x00, 0x00, 0xff, 0},
-	{3, 0x00, 0x00, 0xff, 100000},
-	{0, 0x00, 0x00, 0x00, 0},
-	{3, 0x00, 0x00, 0x00, 100000},
-
-	{0, 0xff, 0x00, 0x00, 0},
-	{1, 0xff, 0x00, 0x00, 100000},
-	{0, 0x00, 0x00, 0x00, 0},
-	{1, 0x00, 0x00, 0x00, 100000},
-
-	{2, 0x00, 0xff, 0x00, 0},
-	{3, 0x00, 0xff, 0x00, 100000},
-	{2, 0x00, 0x00, 0x00, 0},
-	{3, 0x00, 0x00, 0x00, 100000},
-
-	{0, 0xff, 0x00, 0x00, 0},
-	{1, 0xff, 0x00, 0x00, 100000},
-	{0, 0x00, 0x00, 0x00, 0},
-	{1, 0x00, 0x00, 0x00, 100000},
-
-	{2, 0x00, 0xff, 0x00, 0},
-	{3, 0x00, 0xff, 0x00, 100000},
-	{2, 0x00, 0x00, 0x00, 0},
-	{3, 0x00, 0x00, 0x00, 100000},
-
-	{0, 0x00, 0xff, 0xff, 0},
-	{2, 0x00, 0xff, 0xff, 100000},
-	{0, 0x00, 0x00, 0x00, 0},
-	{2, 0x00, 0x00, 0x00, 150000},
-
-	{1, 0xff, 0x00, 0xff, 0},
-	{3, 0xff, 0x00, 0xff, 100000},
-	{1, 0x00, 0x00, 0x00, 0},
-	{3, 0x00, 0x00, 0x00, 250000},
-
-	{4, 0xff, 0xff, 0xff, 100000},
-	{4, 0x00, 0x00, 0x00, 100000},
-
-	{4, 0xff, 0xff, 0xff, 100000},
-	{4, 0x00, 0x00, 0x00, 100000},
-
-	{4, 0xff, 0xff, 0xff, 100000},
-	{4, 0x00, 0x00, 0x00, 100000},
-
-	{4, 0xff, 0xff, 0xff, 100000},
-	{4, 0x00, 0x00, 0x00, 100000},
-
-	{4, 0xff, 0xff, 0xff, 100000},
-	{4, 0x00, 0x00, 0x00, 100000},
-
-	{4, 0xff, 0xff, 0xff, 100000},
-	{4, 0x00, 0x00, 0x00, 100000},
+	{ 1, 0xff, 0xff, 0x00, 0 },	 { 2, 0xff, 0xff, 0x00, 100000 },
+	{ 1, 0x00, 0x00, 0x00, 0 },	 { 2, 0x00, 0x00, 0x00, 100000 },
+
+	{ 1, 0xff, 0xff, 0x00, 0 },	 { 2, 0xff, 0xff, 0x00, 100000 },
+	{ 1, 0x00, 0x00, 0x00, 0 },	 { 2, 0x00, 0x00, 0x00, 100000 },
+
+	{ 0, 0x00, 0x00, 0xff, 0 },	 { 3, 0x00, 0x00, 0xff, 100000 },
+	{ 0, 0x00, 0x00, 0x00, 0 },	 { 3, 0x00, 0x00, 0x00, 100000 },
+
+	{ 0, 0x00, 0x00, 0xff, 0 },	 { 3, 0x00, 0x00, 0xff, 100000 },
+	{ 0, 0x00, 0x00, 0x00, 0 },	 { 3, 0x00, 0x00, 0x00, 100000 },
+
+	{ 0, 0xff, 0x00, 0x00, 0 },	 { 1, 0xff, 0x00, 0x00, 100000 },
+	{ 0, 0x00, 0x00, 0x00, 0 },	 { 1, 0x00, 0x00, 0x00, 100000 },
+
+	{ 2, 0x00, 0xff, 0x00, 0 },	 { 3, 0x00, 0xff, 0x00, 100000 },
+	{ 2, 0x00, 0x00, 0x00, 0 },	 { 3, 0x00, 0x00, 0x00, 100000 },
+
+	{ 0, 0xff, 0x00, 0x00, 0 },	 { 1, 0xff, 0x00, 0x00, 100000 },
+	{ 0, 0x00, 0x00, 0x00, 0 },	 { 1, 0x00, 0x00, 0x00, 100000 },
+
+	{ 2, 0x00, 0xff, 0x00, 0 },	 { 3, 0x00, 0xff, 0x00, 100000 },
+	{ 2, 0x00, 0x00, 0x00, 0 },	 { 3, 0x00, 0x00, 0x00, 100000 },
+
+	{ 0, 0x00, 0xff, 0xff, 0 },	 { 2, 0x00, 0xff, 0xff, 100000 },
+	{ 0, 0x00, 0x00, 0x00, 0 },	 { 2, 0x00, 0x00, 0x00, 150000 },
+
+	{ 1, 0xff, 0x00, 0xff, 0 },	 { 3, 0xff, 0x00, 0xff, 100000 },
+	{ 1, 0x00, 0x00, 0x00, 0 },	 { 3, 0x00, 0x00, 0x00, 250000 },
+
+	{ 4, 0xff, 0xff, 0xff, 100000 }, { 4, 0x00, 0x00, 0x00, 100000 },
+
+	{ 4, 0xff, 0xff, 0xff, 100000 }, { 4, 0x00, 0x00, 0x00, 100000 },
+
+	{ 4, 0xff, 0xff, 0xff, 100000 }, { 4, 0x00, 0x00, 0x00, 100000 },
+
+	{ 4, 0xff, 0xff, 0xff, 100000 }, { 4, 0x00, 0x00, 0x00, 100000 },
+
+	{ 4, 0xff, 0xff, 0xff, 100000 }, { 4, 0x00, 0x00, 0x00, 100000 },
+
+	{ 4, 0xff, 0xff, 0xff, 100000 }, { 4, 0x00, 0x00, 0x00, 100000 },
 };
 
 static uint32_t sequence_KONAMI_inner(void)
@@ -930,8 +898,8 @@ static uint32_t sequence_KONAMI_inner(void)
 	int i;
 
 	for (i = 0; i < ARRAY_SIZE(konami); i++) {
-		lb_set_rgb(konami[i].led,
-			   konami[i].r, konami[i].g, konami[i].b);
+		lb_set_rgb(konami[i].led, konami[i].r, konami[i].g,
+			   konami[i].b);
 		if (konami[i].delay)
 			WAIT_OR_RET(konami[i].delay);
 	}
@@ -961,7 +929,7 @@ static int range(int val, int min, int ofs)
 {
 	if (val <= min)
 		return 0;
-	if (val >= min+ofs)
+	if (val >= min + ofs)
 		return FP_SCALE;
 	return (val - min) * FP_SCALE / ofs;
 }
@@ -977,7 +945,7 @@ static uint32_t sequence_TAP_inner(int dir)
 	uint32_t elapsed_time = 0;
 	int i, l, ci, max_led;
 	int f_osc, f_mult;
-	int gi, gr, gate[NUM_LEDS] = {0, 0, 0, 0};
+	int gi, gr, gate[NUM_LEDS] = { 0, 0, 0, 0 };
 	uint8_t w = 0;
 #ifdef CONFIG_LIGHTBAR_TAP_DIM_LAST_SEGMENT
 	int f_min, f_delta, f_power;
@@ -1010,7 +978,6 @@ static uint32_t sequence_TAP_inner(int dir)
 			gate[gi - 1] = FP_SCALE;
 
 		for (i = 0; i < NUM_LEDS; i++) {
-
 #ifdef CONFIG_LIGHTBAR_TAP_DIM_LAST_SEGMENT
 			if (max_led > i) {
 				f_mult = FP_SCALE;
@@ -1019,7 +986,8 @@ static uint32_t sequence_TAP_inner(int dir)
 			} else {
 				switch (base_color) {
 				case RED:
-					f_power = range(st.battery_percent, 0,
+					f_power = range(
+						st.battery_percent, 0,
 						st.p.battery_threshold[0] - 1);
 					break;
 				case YELLOW:
@@ -1174,9 +1142,9 @@ static inline uint32_t decode_32(uint32_t *dest)
 		CPRINTS("pc 0x%02x near or out of bounds", pc);
 		return EC_RES_INVALID_PARAM;
 	}
-	*dest  = cur_prog.data[pc++] << 24;
+	*dest = cur_prog.data[pc++] << 24;
 	*dest |= cur_prog.data[pc++] << 16;
-	*dest |= cur_prog.data[pc++] <<  8;
+	*dest |= cur_prog.data[pc++] << 8;
 	*dest |= cur_prog.data[pc++];
 	return EC_SUCCESS;
 }
@@ -1307,7 +1275,6 @@ static uint32_t lightbyte_SET_BRIGHTNESS(void)
  */
 static uint32_t lightbyte_SET_COLOR_SINGLE(void)
 {
-
 	uint8_t packed_loc, led, control, color, value;
 	int i;
 	if (decode_8(&packed_loc) != EC_SUCCESS)
@@ -1369,8 +1336,8 @@ static uint32_t lightbyte_GET_COLORS(void)
 	int i;
 	for (i = 0; i < NUM_LEDS; i++)
 		lb_get_rgb(i, &led_desc[i][LB_CONT_COLOR0][LB_COL_RED],
-			      &led_desc[i][LB_CONT_COLOR0][LB_COL_GREEN],
-			      &led_desc[i][LB_CONT_COLOR0][LB_COL_BLUE]);
+			   &led_desc[i][LB_CONT_COLOR0][LB_COL_GREEN],
+			   &led_desc[i][LB_CONT_COLOR0][LB_COL_BLUE]);
 
 	return EC_SUCCESS;
 }
@@ -1481,15 +1448,21 @@ static uint32_t lightbyte_CYCLE(void)
 
 	for (w = 0;; w++) {
 		for (i = 0; i < NUM_LEDS; i++) {
-			r = get_interp_value(i, LB_COL_RED,
-				cycle_010((w & 0xff) +
-				led_desc[i][LB_CONT_PHASE][LB_COL_RED]));
-			g = get_interp_value(i, LB_COL_GREEN,
+			r = get_interp_value(
+				i, LB_COL_RED,
+				cycle_010(
+					(w & 0xff) +
+					led_desc[i][LB_CONT_PHASE][LB_COL_RED]));
+			g = get_interp_value(
+				i, LB_COL_GREEN,
 				cycle_010((w & 0xff) +
-				led_desc[i][LB_CONT_PHASE][LB_COL_GREEN]));
-			b = get_interp_value(i, LB_COL_BLUE,
+					  led_desc[i][LB_CONT_PHASE]
+						  [LB_COL_GREEN]));
+			b = get_interp_value(
+				i, LB_COL_BLUE,
 				cycle_010((w & 0xff) +
-				led_desc[i][LB_CONT_PHASE][LB_COL_BLUE]));
+					  led_desc[i][LB_CONT_PHASE]
+						  [LB_COL_BLUE]));
 			lb_set_rgb(i, r, g, b);
 		}
 		WAIT_OR_RET(lb_ramp_delay);
@@ -1509,24 +1482,17 @@ static uint32_t lightbyte_HALT(void)
 
 #define OP(NAME, BYTES, MNEMONIC) NAME,
 #include "lightbar_opcode_list.h"
-enum lightbyte_opcode {
-	LIGHTBAR_OPCODE_TABLE
-	MAX_OPCODE
-};
+enum lightbyte_opcode { LIGHTBAR_OPCODE_TABLE MAX_OPCODE };
 #undef OP
 
-#define OP(NAME, BYTES, MNEMONIC) lightbyte_ ## NAME,
+#define OP(NAME, BYTES, MNEMONIC) lightbyte_##NAME,
 #include "lightbar_opcode_list.h"
-static uint32_t (*lightbyte_dispatch[])(void) = {
-	LIGHTBAR_OPCODE_TABLE
-};
+static uint32_t (*lightbyte_dispatch[])(void) = { LIGHTBAR_OPCODE_TABLE };
 #undef OP
 
 #define OP(NAME, BYTES, MNEMONIC) MNEMONIC,
 #include "lightbar_opcode_list.h"
-static const char * const lightbyte_names[] = {
-	LIGHTBAR_OPCODE_TABLE
-};
+static const char *const lightbyte_names[] = { LIGHTBAR_OPCODE_TABLE };
 #undef OP
 
 static uint32_t sequence_PROGRAM(void)
@@ -1563,7 +1529,7 @@ static uint32_t sequence_PROGRAM(void)
 			return EC_RES_INVALID_PARAM;
 		} else {
 			CPRINTS("LB PROGRAM pc: 0x%02x, opcode 0x%02x -> %s",
-				 old_pc, next_inst, lightbyte_names[next_inst]);
+				old_pc, next_inst, lightbyte_names[next_inst]);
 			rc = lightbyte_dispatch[next_inst]();
 			if (rc) {
 				lb_set_brightness(saved_brightness);
@@ -1588,15 +1554,16 @@ static inline int is_normal_sequence(enum lightbar_sequence seq)
 
 /* Link each sequence with a command to invoke it. */
 struct lightbar_cmd_t {
-	const char * const string;
+	const char *const string;
 	uint32_t (*sequence)(void);
 };
 
-#define LBMSG(state) { #state, sequence_##state }
+#define LBMSG(state)                     \
+	{                                \
+#state, sequence_##state \
+	}
 #include "lightbar_msg_list.h"
-static struct lightbar_cmd_t lightbar_cmds[] = {
-	LIGHTBAR_MSG_LIST
-};
+static struct lightbar_cmd_t lightbar_cmds[] = { LIGHTBAR_MSG_LIST };
 #undef LBMSG
 
 void lightbar_task(void)
@@ -1608,9 +1575,9 @@ void lightbar_task(void)
 	lightbar_restore_state();
 
 	while (1) {
-		CPRINTS("LB running cur_seq %d %s. prev_seq %d %s",
-			st.cur_seq, lightbar_cmds[st.cur_seq].string,
-			st.prev_seq, lightbar_cmds[st.prev_seq].string);
+		CPRINTS("LB running cur_seq %d %s. prev_seq %d %s", st.cur_seq,
+			lightbar_cmds[st.cur_seq].string, st.prev_seq,
+			lightbar_cmds[st.prev_seq].string);
 		next_seq = lightbar_cmds[st.cur_seq].sequence();
 		if (next_seq) {
 			CPRINTS("LB cur_seq %d %s returned pending msg %d %s",
@@ -1622,8 +1589,8 @@ void lightbar_task(void)
 				st.cur_seq = next_seq;
 			}
 		} else {
-			CPRINTS("LB cur_seq %d %s returned value 0",
-				st.cur_seq, lightbar_cmds[st.cur_seq].string);
+			CPRINTS("LB cur_seq %d %s returned value 0", st.cur_seq,
+				lightbar_cmds[st.cur_seq].string);
 			switch (st.cur_seq) {
 			case LIGHTBAR_S5S3:
 				st.cur_seq = LIGHTBAR_S3;
@@ -1733,16 +1700,12 @@ static enum ec_status lpc_cmd_lightbar(struct host_cmd_handler_args *args)
 		lb_hc_cmd_reg(in);
 		break;
 	case LIGHTBAR_CMD_SET_RGB:
-		lb_set_rgb(in->set_rgb.led,
-			   in->set_rgb.red,
-			   in->set_rgb.green,
+		lb_set_rgb(in->set_rgb.led, in->set_rgb.red, in->set_rgb.green,
 			   in->set_rgb.blue);
 		break;
 	case LIGHTBAR_CMD_GET_RGB:
-		rv = lb_get_rgb(in->get_rgb.led,
-				&out->get_rgb.red,
-				&out->get_rgb.green,
-				&out->get_rgb.blue);
+		rv = lb_get_rgb(in->get_rgb.led, &out->get_rgb.red,
+				&out->get_rgb.green, &out->get_rgb.blue);
 		if (rv == EC_RES_SUCCESS)
 			args->response_size = sizeof(out->get_rgb);
 		return rv;
@@ -1777,8 +1740,7 @@ static enum ec_status lpc_cmd_lightbar(struct host_cmd_handler_args *args)
 		break;
 	case LIGHTBAR_CMD_SET_PROGRAM:
 		CPRINTS("LB_set_program");
-		memcpy(&next_prog,
-		       &in->set_program,
+		memcpy(&next_prog, &in->set_program,
 		       sizeof(struct lightbar_program));
 		break;
 	case LIGHTBAR_CMD_VERSION:
@@ -1801,28 +1763,24 @@ static enum ec_status lpc_cmd_lightbar(struct host_cmd_handler_args *args)
 		break;
 	case LIGHTBAR_CMD_GET_PARAMS_V2_TIMING:
 		CPRINTS("LB_get_params_v2_timing");
-		memcpy(&out->get_params_v2_timing,
-		       &st.p_v2.timing,
+		memcpy(&out->get_params_v2_timing, &st.p_v2.timing,
 		       sizeof(st.p_v2.timing));
 		args->response_size = sizeof(out->get_params_v2_timing);
 		break;
 	case LIGHTBAR_CMD_SET_PARAMS_V2_TIMING:
 		CPRINTS("LB_set_params_v2_timing");
-		memcpy(&st.p_v2.timing,
-		       &in->set_v2par_timing,
+		memcpy(&st.p_v2.timing, &in->set_v2par_timing,
 		       sizeof(struct lightbar_params_v2_timing));
 		break;
 	case LIGHTBAR_CMD_GET_PARAMS_V2_TAP:
 		CPRINTS("LB_get_params_v2_tap");
-		memcpy(&out->get_params_v2_tap,
-		       &st.p_v2.tap,
+		memcpy(&out->get_params_v2_tap, &st.p_v2.tap,
 		       sizeof(struct lightbar_params_v2_tap));
 		args->response_size = sizeof(out->get_params_v2_tap);
 		break;
 	case LIGHTBAR_CMD_SET_PARAMS_V2_TAP:
 		CPRINTS("LB_set_params_v2_tap");
-		memcpy(&st.p_v2.tap,
-		       &in->set_v2par_tap,
+		memcpy(&st.p_v2.tap, &in->set_v2par_tap,
 		       sizeof(struct lightbar_params_v2_tap));
 		break;
 	case LIGHTBAR_CMD_GET_PARAMS_V2_OSCILLATION:
@@ -1833,47 +1791,40 @@ static enum ec_status lpc_cmd_lightbar(struct host_cmd_handler_args *args)
 		break;
 	case LIGHTBAR_CMD_SET_PARAMS_V2_OSCILLATION:
 		CPRINTS("LB_set_params_v2_oscillation");
-		memcpy(&st.p_v2.osc,
-		       &in->set_v2par_osc,
+		memcpy(&st.p_v2.osc, &in->set_v2par_osc,
 		       sizeof(struct lightbar_params_v2_oscillation));
 		break;
 	case LIGHTBAR_CMD_GET_PARAMS_V2_BRIGHTNESS:
 		CPRINTS("LB_get_params_v2_brightness");
-		memcpy(&out->get_params_v2_bright,
-		       &st.p_v2.bright,
+		memcpy(&out->get_params_v2_bright, &st.p_v2.bright,
 		       sizeof(struct lightbar_params_v2_brightness));
 		args->response_size = sizeof(out->get_params_v2_bright);
 		break;
 	case LIGHTBAR_CMD_SET_PARAMS_V2_BRIGHTNESS:
 		CPRINTS("LB_set_params_v2_brightness");
-		memcpy(&st.p_v2.bright,
-		       &in->set_v2par_bright,
+		memcpy(&st.p_v2.bright, &in->set_v2par_bright,
 		       sizeof(struct lightbar_params_v2_brightness));
 		break;
 	case LIGHTBAR_CMD_GET_PARAMS_V2_THRESHOLDS:
 		CPRINTS("LB_get_params_v2_thlds");
-		memcpy(&out->get_params_v2_thlds,
-		       &st.p_v2.thlds,
+		memcpy(&out->get_params_v2_thlds, &st.p_v2.thlds,
 		       sizeof(struct lightbar_params_v2_thresholds));
 		args->response_size = sizeof(out->get_params_v2_thlds);
 		break;
 	case LIGHTBAR_CMD_SET_PARAMS_V2_THRESHOLDS:
 		CPRINTS("LB_set_params_v2_thlds");
-		memcpy(&st.p_v2.thlds,
-		       &in->set_v2par_thlds,
+		memcpy(&st.p_v2.thlds, &in->set_v2par_thlds,
 		       sizeof(struct lightbar_params_v2_thresholds));
 		break;
 	case LIGHTBAR_CMD_GET_PARAMS_V2_COLORS:
 		CPRINTS("LB_get_params_v2_colors");
-		memcpy(&out->get_params_v2_colors,
-		       &st.p_v2.colors,
+		memcpy(&out->get_params_v2_colors, &st.p_v2.colors,
 		       sizeof(struct lightbar_params_v2_colors));
 		args->response_size = sizeof(out->get_params_v2_colors);
 		break;
 	case LIGHTBAR_CMD_SET_PARAMS_V2_COLORS:
 		CPRINTS("LB_set_params_v2_colors");
-		memcpy(&st.p_v2.colors,
-		       &in->set_v2par_colors,
+		memcpy(&st.p_v2.colors, &in->set_v2par_colors,
 		       sizeof(struct lightbar_params_v2_colors));
 		break;
 	default:
@@ -1884,9 +1835,7 @@ static enum ec_status lpc_cmd_lightbar(struct host_cmd_handler_args *args)
 	return EC_RES_SUCCESS;
 }
 
-DECLARE_HOST_COMMAND(EC_CMD_LIGHTBAR_CMD,
-		     lpc_cmd_lightbar,
-		     EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_LIGHTBAR_CMD, lpc_cmd_lightbar, EC_VER_MASK(0));
 
 /****************************************************************************/
 /* EC console commands */
@@ -1902,10 +1851,12 @@ static int help(const char *cmd)
 	ccprintf("  %s init                  - load default vals\n", cmd);
 	ccprintf("  %s brightness [NUM]      - set intensity (0-ff)\n", cmd);
 	ccprintf("  %s seq [NUM|SEQUENCE]    - run given pattern"
-		 " (no arg for list)\n", cmd);
+		 " (no arg for list)\n",
+		 cmd);
 	ccprintf("  %s CTRL REG VAL          - set LED controller regs\n", cmd);
 	ccprintf("  %s LED RED GREEN BLUE    - set color manually"
-		 " (LED=%d for all)\n", cmd, NUM_LEDS);
+		 " (LED=%d for all)\n",
+		 cmd, NUM_LEDS);
 	ccprintf("  %s LED                   - get current LED color\n", cmd);
 	ccprintf("  %s demo [0|1]            - turn demo mode on & off\n", cmd);
 #ifdef LIGHTBAR_SIMULATION
@@ -1936,19 +1887,18 @@ static void show_msg_names(void)
 		 lightbar_cmds[st.cur_seq].string);
 }
 
-static int command_lightbar(int argc, char **argv)
+static int command_lightbar(int argc, const char **argv)
 {
 	int i;
 	uint8_t num, led, r = 0, g = 0, b = 0;
 	struct ec_response_lightbar out;
 	char *e;
 
-	if (argc == 1) {			/* no args = dump 'em all */
+	if (argc == 1) { /* no args = dump 'em all */
 		lb_hc_cmd_dump(&out);
 		for (i = 0; i < ARRAY_SIZE(out.dump.vals); i++)
 			ccprintf(" %02x     %02x     %02x\n",
-				 out.dump.vals[i].reg,
-				 out.dump.vals[i].ic0,
+				 out.dump.vals[i].reg, out.dump.vals[i].ic0,
 				 out.dump.vals[i].ic1);
 
 		return EC_SUCCESS;
@@ -1987,8 +1937,7 @@ static int command_lightbar(int argc, char **argv)
 
 	if (!strcasecmp(argv[1], "demo")) {
 		if (argc > 2) {
-			if (!strcasecmp(argv[2], "on") ||
-			    argv[2][0] == '1')
+			if (!strcasecmp(argv[2], "on") || argv[2][0] == '1')
 				demo_mode = 1;
 			else if (!strcasecmp(argv[2], "off") ||
 				 argv[2][0] == '0')
@@ -2010,7 +1959,7 @@ static int command_lightbar(int argc, char **argv)
 			num = find_msg_by_name(argv[2]);
 		if (num >= LIGHTBAR_NUM_SEQUENCES)
 			return EC_ERROR_PARAM2;
-		if (argc > 3)			/* for testing TAP direction */
+		if (argc > 3) /* for testing TAP direction */
 			force_dir = strtoi(argv[3], 0, 0);
 		lightbar_sequence(num);
 		return EC_SUCCESS;
@@ -2056,13 +2005,11 @@ static int command_lightbar(int argc, char **argv)
 		return EC_SUCCESS;
 	}
 
-
 #ifdef CONFIG_CONSOLE_CMDHELP
 	help(argv[0]);
 #endif
 
 	return EC_ERROR_INVAL;
 }
-DECLARE_CONSOLE_COMMAND(lightbar, command_lightbar,
-			"[help | COMMAND [ARGS]]",
+DECLARE_CONSOLE_COMMAND(lightbar, command_lightbar, "[help | COMMAND [ARGS]]",
 			"Get/set lightbar state");
diff --git a/common/mag_cal.c b/common/mag_cal.c
index 13beb93af2..a9ce95798c 100644
--- a/common/mag_cal.c
+++ b/common/mag_cal.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,17 +14,17 @@
 #include "util.h"
 
 /* Data from sensor is in 16th of uT, 0.0625 uT/LSB */
-#define MAG_CAL_RAW_UT      16
+#define MAG_CAL_RAW_UT 16
 
-#define MAX_EIGEN_RATIO     FLOAT_TO_FP(25.0f)
-#define MAX_EIGEN_MAG       FLOAT_TO_FP(80.0f * MAG_CAL_RAW_UT)
-#define MIN_EIGEN_MAG       FLOAT_TO_FP(10.0f * MAG_CAL_RAW_UT)
+#define MAX_EIGEN_RATIO FLOAT_TO_FP(25.0f)
+#define MAX_EIGEN_MAG FLOAT_TO_FP(80.0f * MAG_CAL_RAW_UT)
+#define MIN_EIGEN_MAG FLOAT_TO_FP(10.0f * MAG_CAL_RAW_UT)
 
-#define MAX_FIT_MAG         MAX_EIGEN_MAG
-#define MIN_FIT_MAG         MIN_EIGEN_MAG
+#define MAX_FIT_MAG MAX_EIGEN_MAG
+#define MIN_FIT_MAG MIN_EIGEN_MAG
 
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
-#define PRINTF_FLOAT(x)  ((int)((x) * 100.0f))
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
+#define PRINTF_FLOAT(x) ((int)((x)*100.0f))
 
 /**
  * Compute the covariance element: (avg(ab) - avg(a)*avg(b))
@@ -51,34 +51,25 @@ static int moc_eigen_test(struct mag_cal_t *moc)
 	mat33_fp_t eigenvecs;
 	fp_t evmax, evmin, evmag;
 	fp_t inv = fp_div_dbz(FLOAT_TO_FP(1.0f),
-			      INT_TO_FP((int) moc->kasa_fit.nsamples));
+			      INT_TO_FP((int)moc->kasa_fit.nsamples));
 	int eigen_pass;
 
 	/* covariance matrix */
-	S[0][0] = covariance_element(moc->kasa_fit.acc_xx,
-				     moc->kasa_fit.acc_x,
-				     moc->kasa_fit.acc_x,
-				     inv);
+	S[0][0] = covariance_element(moc->kasa_fit.acc_xx, moc->kasa_fit.acc_x,
+				     moc->kasa_fit.acc_x, inv);
 	S[0][1] = S[1][0] = covariance_element(moc->kasa_fit.acc_xy,
 					       moc->kasa_fit.acc_x,
-					       moc->kasa_fit.acc_y,
-					       inv);
+					       moc->kasa_fit.acc_y, inv);
 	S[0][2] = S[2][0] = covariance_element(moc->kasa_fit.acc_xz,
 					       moc->kasa_fit.acc_x,
-					       moc->kasa_fit.acc_z,
-					       inv);
-	S[1][1] = covariance_element(moc->kasa_fit.acc_yy,
-				     moc->kasa_fit.acc_y,
-				     moc->kasa_fit.acc_y,
-				     inv);
+					       moc->kasa_fit.acc_z, inv);
+	S[1][1] = covariance_element(moc->kasa_fit.acc_yy, moc->kasa_fit.acc_y,
+				     moc->kasa_fit.acc_y, inv);
 	S[1][2] = S[2][1] = covariance_element(moc->kasa_fit.acc_yz,
 					       moc->kasa_fit.acc_y,
-					       moc->kasa_fit.acc_z,
-					       inv);
-	S[2][2] = covariance_element(moc->kasa_fit.acc_zz,
-				     moc->kasa_fit.acc_z,
-				     moc->kasa_fit.acc_z,
-				     inv);
+					       moc->kasa_fit.acc_z, inv);
+	S[2][2] = covariance_element(moc->kasa_fit.acc_zz, moc->kasa_fit.acc_z,
+				     moc->kasa_fit.acc_z, inv);
 
 	mat33_fp_get_eigenbasis(S, eigenvals, eigenvecs);
 
@@ -90,9 +81,8 @@ static int moc_eigen_test(struct mag_cal_t *moc)
 
 	evmag = fp_sqrtf(eigenvals[X] + eigenvals[Y] + eigenvals[Z]);
 
-	eigen_pass = (fp_mul(evmin, MAX_EIGEN_RATIO) > evmax)
-		&& (evmag > MIN_EIGEN_MAG)
-		&& (evmag < MAX_EIGEN_MAG);
+	eigen_pass = (fp_mul(evmin, MAX_EIGEN_RATIO) > evmax) &&
+		     (evmag > MIN_EIGEN_MAG) && (evmag < MAX_EIGEN_MAG);
 
 #if 0
 	CPRINTF("mag eigenvalues: (%.02d %.02d %.02d), ",
diff --git a/common/main.c b/common/main.c
index 93e68fb1ca..ef5aef8acf 100644
--- a/common/main.c
+++ b/common/main.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -29,6 +29,7 @@
 #ifdef CONFIG_MPU
 #include "mpu.h"
 #endif
+#include "panic.h"
 #include "rwsig.h"
 #include "system.h"
 #include "task.h"
@@ -40,8 +41,8 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 test_mockable __keep int main(void)
 {
@@ -182,12 +183,12 @@ test_mockable __keep int main(void)
 	if (IS_ENABLED(CONFIG_EEPROM_CBI_WP) && system_is_locked())
 		cbi_latch_eeprom_wp();
 
-	/*
-	 * Keyboard scan init/Button init can set recovery events to
-	 * indicate to host entry into recovery mode. Before this is
-	 * done, LPC_HOST_EVENT_ALWAYS_REPORT mask needs to be initialized
-	 * correctly.
-	 */
+		/*
+		 * Keyboard scan init/Button init can set recovery events to
+		 * indicate to host entry into recovery mode. Before this is
+		 * done, LPC_HOST_EVENT_ALWAYS_REPORT mask needs to be
+		 * initialized correctly.
+		 */
 #ifdef CONFIG_HOSTCMD_X86
 	lpc_init_mask();
 #endif
@@ -228,9 +229,9 @@ test_mockable __keep int main(void)
 #endif /* defined(CONFIG_DEDICATED_RECOVERY_BUTTON | CONFIG_VOLUME_BUTTONS) */
 
 	/* Make sure recovery boot won't be paused. */
-	if (IS_ENABLED(CONFIG_POWER_BUTTON_INIT_IDLE)
-			&& system_is_manual_recovery()
-			&& (system_get_reset_flags() & EC_RESET_FLAG_AP_IDLE)) {
+	if (IS_ENABLED(CONFIG_POWER_BUTTON_INIT_IDLE) &&
+	    system_is_manual_recovery() &&
+	    (system_get_reset_flags() & EC_RESET_FLAG_AP_IDLE)) {
 		CPRINTS("Clear AP_IDLE for recovery mode");
 		system_clear_reset_flags(EC_RESET_FLAG_AP_IDLE);
 	}
@@ -270,15 +271,14 @@ test_mockable __keep int main(void)
 				rwsig_jump_now();
 		}
 	}
-#endif  /* !CONFIG_VBOOT_EFS && CONFIG_RWSIG && !HAS_TASK_RWSIG */
+#endif /* !CONFIG_VBOOT_EFS && CONFIG_RWSIG && !HAS_TASK_RWSIG */
 
 	/*
 	 * Disable I2C raw mode for the ports which needed pre-task i2c
 	 * transactions as the task is about to start and the I2C can resume
 	 * to event based transactions.
 	 */
-	if (IS_ENABLED(CONFIG_I2C_BITBANG) &&
-		IS_ENABLED(CONFIG_I2C_CONTROLLER))
+	if (IS_ENABLED(CONFIG_I2C_BITBANG) && IS_ENABLED(CONFIG_I2C_CONTROLLER))
 		enable_i2c_raw_mode(false);
 
 	/*
diff --git a/common/mat33.c b/common/mat33.c
index 87e335db26..844fd0b8cc 100644
--- a/common/mat33.c
+++ b/common/mat33.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -59,8 +59,7 @@ void mat33_fp_swap_rows(mat33_fp_t A, const size_t i, const size_t j)
  * The i-th eigenvalue corresponds to the eigenvector in the i-th _row_ of
  * "eigenvecs".
  */
-void mat33_fp_get_eigenbasis(mat33_fp_t S, fpv3_t e_vals,
-			     mat33_fp_t e_vecs)
+void mat33_fp_get_eigenbasis(mat33_fp_t S, fpv3_t e_vals, mat33_fp_t e_vecs)
 {
 	const size_t N = 3;
 	sizev3_t ind;
@@ -176,8 +175,8 @@ size_t mat33_fp_maxind(mat33_fp_t A, size_t k)
 	return m;
 }
 
-void mat33_fp_rotate(mat33_fp_t A, fp_t c, fp_t s,
-		     size_t k, size_t l, size_t i, size_t j)
+void mat33_fp_rotate(mat33_fp_t A, fp_t c, fp_t s, size_t k, size_t l, size_t i,
+		     size_t j)
 {
 	fp_t tmp = fp_mul(c, A[k][l]) - fp_mul(s, A[i][j]);
 	A[i][j] = fp_mul(s, A[k][l]) + fp_mul(c, A[i][j]);
diff --git a/common/mat44.c b/common/mat44.c
index a4232bf8d4..d48ca4f596 100644
--- a/common/mat44.c
+++ b/common/mat44.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/common/math_util.c b/common/math_util.c
index ff305438eb..c0a279b825 100644
--- a/common/math_util.c
+++ b/common/math_util.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,18 +11,18 @@
 #include "util.h"
 
 /* For cosine lookup table, define the increment and the size of the table. */
-#define COSINE_LUT_INCR_DEG	5
-#define COSINE_LUT_SIZE		((180 / COSINE_LUT_INCR_DEG) + 1)
+#define COSINE_LUT_INCR_DEG 5
+#define COSINE_LUT_SIZE ((180 / COSINE_LUT_INCR_DEG) + 1)
 
 /* Lookup table for the value of cosine from 0 degrees to 180 degrees. */
 static const fp_t cos_lut[] = {
-	FLOAT_TO_FP( 1.00000), FLOAT_TO_FP( 0.99619), FLOAT_TO_FP( 0.98481),
-	FLOAT_TO_FP( 0.96593), FLOAT_TO_FP( 0.93969), FLOAT_TO_FP( 0.90631),
-	FLOAT_TO_FP( 0.86603), FLOAT_TO_FP( 0.81915), FLOAT_TO_FP( 0.76604),
-	FLOAT_TO_FP( 0.70711), FLOAT_TO_FP( 0.64279), FLOAT_TO_FP( 0.57358),
-	FLOAT_TO_FP( 0.50000), FLOAT_TO_FP( 0.42262), FLOAT_TO_FP( 0.34202),
-	FLOAT_TO_FP( 0.25882), FLOAT_TO_FP( 0.17365), FLOAT_TO_FP( 0.08716),
-	FLOAT_TO_FP( 0.00000), FLOAT_TO_FP(-0.08716), FLOAT_TO_FP(-0.17365),
+	FLOAT_TO_FP(1.00000),  FLOAT_TO_FP(0.99619),  FLOAT_TO_FP(0.98481),
+	FLOAT_TO_FP(0.96593),  FLOAT_TO_FP(0.93969),  FLOAT_TO_FP(0.90631),
+	FLOAT_TO_FP(0.86603),  FLOAT_TO_FP(0.81915),  FLOAT_TO_FP(0.76604),
+	FLOAT_TO_FP(0.70711),  FLOAT_TO_FP(0.64279),  FLOAT_TO_FP(0.57358),
+	FLOAT_TO_FP(0.50000),  FLOAT_TO_FP(0.42262),  FLOAT_TO_FP(0.34202),
+	FLOAT_TO_FP(0.25882),  FLOAT_TO_FP(0.17365),  FLOAT_TO_FP(0.08716),
+	FLOAT_TO_FP(0.00000),  FLOAT_TO_FP(-0.08716), FLOAT_TO_FP(-0.17365),
 	FLOAT_TO_FP(-0.25882), FLOAT_TO_FP(-0.34202), FLOAT_TO_FP(-0.42262),
 	FLOAT_TO_FP(-0.50000), FLOAT_TO_FP(-0.57358), FLOAT_TO_FP(-0.64279),
 	FLOAT_TO_FP(-0.70711), FLOAT_TO_FP(-0.76604), FLOAT_TO_FP(-0.81915),
@@ -32,7 +32,6 @@ static const fp_t cos_lut[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(cos_lut) == COSINE_LUT_SIZE);
 
-
 fp_t arc_cos(fp_t x)
 {
 	int i;
@@ -48,8 +47,8 @@ fp_t arc_cos(fp_t x)
 	 * interpolate for precision.
 	 */
 	/* TODO(crosbug.com/p/25600): Optimize with binary search. */
-	for (i = 0; i < COSINE_LUT_SIZE-1; i++) {
-		if (x >= cos_lut[i+1]) {
+	for (i = 0; i < COSINE_LUT_SIZE - 1; i++) {
+		if (x >= cos_lut[i + 1]) {
 			const fp_t interp = fp_div(cos_lut[i] - x,
 						   cos_lut[i] - cos_lut[i + 1]);
 
@@ -104,7 +103,7 @@ int int_sqrtf(fp_inter_t x)
 	 * infrequently enough it doesn't matter.
 	 */
 	if (x <= 0)
-		return 0;  /* Yeah, for imaginary numbers too */
+		return 0; /* Yeah, for imaginary numbers too */
 	else if (x >= (fp_inter_t)rmax * rmax)
 		return rmax;
 
@@ -138,9 +137,8 @@ fp_t fp_sqrtf(fp_t x)
 
 int vector_magnitude(const intv3_t v)
 {
-	fp_inter_t sum =   (fp_inter_t)v[0] * v[0] +
-			(fp_inter_t)v[1] * v[1] +
-			(fp_inter_t)v[2] * v[2];
+	fp_inter_t sum = (fp_inter_t)v[0] * v[0] + (fp_inter_t)v[1] * v[1] +
+			 (fp_inter_t)v[2] * v[2];
 
 	return int_sqrtf(sum);
 }
@@ -155,8 +153,7 @@ void cross_product(const intv3_t v1, const intv3_t v2, intv3_t v)
 
 fp_inter_t dot_product(const intv3_t v1, const intv3_t v2)
 {
-	return (fp_inter_t)v1[X] * v2[X] +
-	       (fp_inter_t)v1[Y] * v2[Y] +
+	return (fp_inter_t)v1[X] * v2[X] + (fp_inter_t)v1[Y] * v2[Y] +
 	       (fp_inter_t)v1[Z] * v2[Z];
 }
 
@@ -215,17 +212,13 @@ void rotate(const intv3_t v, const mat33_fp_t R, intv3_t res)
 		return;
 	}
 
-
 	/* Rotate */
-	t[0] =	(fp_inter_t)v[0] * R[0][0] +
-		(fp_inter_t)v[1] * R[1][0] +
-		(fp_inter_t)v[2] * R[2][0];
-	t[1] =	(fp_inter_t)v[0] * R[0][1] +
-		(fp_inter_t)v[1] * R[1][1] +
-		(fp_inter_t)v[2] * R[2][1];
-	t[2] =	(fp_inter_t)v[0] * R[0][2] +
-		(fp_inter_t)v[1] * R[1][2] +
-		(fp_inter_t)v[2] * R[2][2];
+	t[0] = (fp_inter_t)v[0] * R[0][0] + (fp_inter_t)v[1] * R[1][0] +
+	       (fp_inter_t)v[2] * R[2][0];
+	t[1] = (fp_inter_t)v[0] * R[0][1] + (fp_inter_t)v[1] * R[1][1] +
+	       (fp_inter_t)v[2] * R[2][1];
+	t[2] = (fp_inter_t)v[0] * R[0][2] + (fp_inter_t)v[1] * R[1][2] +
+	       (fp_inter_t)v[2] * R[2][2];
 
 	/* Scale by fixed point shift when writing back to result */
 	res[0] = FP_TO_INT(t[0]);
@@ -244,38 +237,39 @@ void rotate_inv(const intv3_t v, const mat33_fp_t R, intv3_t res)
 		return;
 	}
 
-	deter = fp_mul(R[0][0], (fp_mul(R[1][1], R[2][2]) -
-				 fp_mul(R[2][1], R[1][2]))) -
-		fp_mul(R[0][1], (fp_mul(R[1][0], R[2][2]) -
-				 fp_mul(R[1][2], R[2][0]))) +
-		fp_mul(R[0][2], (fp_mul(R[1][0], R[2][1]) -
-				 fp_mul(R[1][1], R[2][0])));
+	deter = fp_mul(R[0][0],
+		       (fp_mul(R[1][1], R[2][2]) - fp_mul(R[2][1], R[1][2]))) -
+		fp_mul(R[0][1],
+		       (fp_mul(R[1][0], R[2][2]) - fp_mul(R[1][2], R[2][0]))) +
+		fp_mul(R[0][2],
+		       (fp_mul(R[1][0], R[2][1]) - fp_mul(R[1][1], R[2][0])));
 
 	/*
 	 * invert the matrix: from
 	 * http://stackoverflow.com/questions/983999/
 	 * simple-3x3-matrix-inverse-code-c
 	 */
-	t[0] =  (fp_inter_t)v[0] * (fp_mul(R[1][1], R[2][2]) -
-				 fp_mul(R[2][1], R[1][2])) -
-		(fp_inter_t)v[1] * (fp_mul(R[1][0], R[2][2]) -
-				 fp_mul(R[1][2], R[2][0])) +
-		(fp_inter_t)v[2] * (fp_mul(R[1][0], R[2][1]) -
-				 fp_mul(R[2][0], R[1][1]));
-
-	t[1] =	(fp_inter_t)v[0] * (fp_mul(R[0][1], R[2][2]) -
-				 fp_mul(R[0][2], R[2][1])) * -1 +
-		(fp_inter_t)v[1] * (fp_mul(R[0][0], R[2][2]) -
-				 fp_mul(R[0][2], R[2][0])) -
-		(fp_inter_t)v[2] * (fp_mul(R[0][0], R[2][1]) -
-				 fp_mul(R[2][0], R[0][1]));
-
-	t[2] =	(fp_inter_t)v[0] * (fp_mul(R[0][1], R[1][2]) -
-				 fp_mul(R[0][2], R[1][1])) -
-		(fp_inter_t)v[1] * (fp_mul(R[0][0], R[1][2]) -
-				 fp_mul(R[1][0], R[0][2])) +
-		(fp_inter_t)v[2] * (fp_mul(R[0][0], R[1][1]) -
-				 fp_mul(R[1][0], R[0][1]));
+	t[0] = (fp_inter_t)v[0] *
+		       (fp_mul(R[1][1], R[2][2]) - fp_mul(R[2][1], R[1][2])) -
+	       (fp_inter_t)v[1] *
+		       (fp_mul(R[1][0], R[2][2]) - fp_mul(R[1][2], R[2][0])) +
+	       (fp_inter_t)v[2] *
+		       (fp_mul(R[1][0], R[2][1]) - fp_mul(R[2][0], R[1][1]));
+
+	t[1] = (fp_inter_t)v[0] *
+		       (fp_mul(R[0][1], R[2][2]) - fp_mul(R[0][2], R[2][1])) *
+		       -1 +
+	       (fp_inter_t)v[1] *
+		       (fp_mul(R[0][0], R[2][2]) - fp_mul(R[0][2], R[2][0])) -
+	       (fp_inter_t)v[2] *
+		       (fp_mul(R[0][0], R[2][1]) - fp_mul(R[2][0], R[0][1]));
+
+	t[2] = (fp_inter_t)v[0] *
+		       (fp_mul(R[0][1], R[1][2]) - fp_mul(R[0][2], R[1][1])) -
+	       (fp_inter_t)v[1] *
+		       (fp_mul(R[0][0], R[1][2]) - fp_mul(R[1][0], R[0][2])) +
+	       (fp_inter_t)v[2] *
+		       (fp_mul(R[0][0], R[1][1]) - fp_mul(R[1][0], R[0][1]));
 
 	/* Scale by fixed point shift when writing back to result */
 	res[0] = FP_TO_INT(fp_div(t[0], deter));
@@ -287,8 +281,8 @@ void rotate_inv(const intv3_t v, const mat33_fp_t R, intv3_t res)
 int round_divide(int64_t dividend, int divisor)
 {
 	return (dividend > 0) ^ (divisor > 0) ?
-		(dividend - divisor / 2) / divisor :
-		(dividend + divisor / 2) / divisor;
+		       (dividend - divisor / 2) / divisor :
+		       (dividend + divisor / 2) / divisor;
 }
 
 #if ULONG_MAX == 0xFFFFFFFFUL
@@ -303,7 +297,7 @@ uint64_t bitmask_uint64(int offset)
 {
 	union mask64_t {
 		struct {
-#if (__BYTE_ORDER__  == __ORDER_LITTLE_ENDIAN__)
+#if (__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__)
 			uint32_t lo;
 			uint32_t hi;
 #elif (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__)
diff --git a/common/memory_commands.c b/common/memory_commands.c
index 98c64d918b..cb53c4890a 100644
--- a/common/memory_commands.c
+++ b/common/memory_commands.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,7 +10,6 @@
 #include "util.h"
 #include "watchdog.h"
 
-
 enum format {
 	FMT_WORD,
 	FMT_HALF,
@@ -56,7 +55,7 @@ static void show_val(uint32_t address, uint32_t index, enum format fmt)
 	cflush();
 }
 
-static int command_mem_dump(int argc, char **argv)
+static int command_mem_dump(int argc, const char **argv)
 {
 	uint32_t address, i, num = 1;
 	char *e;
@@ -106,15 +105,14 @@ static int command_mem_dump(int argc, char **argv)
 	return EC_SUCCESS;
 }
 
-DECLARE_CONSOLE_COMMAND_FLAGS
-	(md, command_mem_dump,
-	 "[.b|.h|.s] addr [count]",
-	 "dump memory values, optionally specifying the format",
-	 CMD_FLAG_RESTRICTED);
+DECLARE_CONSOLE_COMMAND_FLAGS(
+	md, command_mem_dump, "[.b|.h|.s] addr [count]",
+	"dump memory values, optionally specifying the format",
+	CMD_FLAG_RESTRICTED);
 #endif /* CONFIG_CMD_MD */
 
 #ifdef CONFIG_CMD_RW
-static int command_read_word(int argc, char **argv)
+static int command_read_word(int argc, const char **argv)
 {
 	volatile uint32_t *address;
 	uint32_t value;
@@ -149,16 +147,16 @@ static int command_read_word(int argc, char **argv)
 	if ((argc - argc_offs) < 3) {
 		switch (access_size) {
 		case 1:
-			ccprintf("read 0x%pP = 0x%02x\n",
-				 address, *((uint8_t *)address));
+			ccprintf("read 0x%p = 0x%02x\n", address,
+				 *((uint8_t *)address));
 			break;
 		case 2:
-			ccprintf("read 0x%pP = 0x%04x\n",
-				 address, *((uint16_t *)address));
+			ccprintf("read 0x%p = 0x%04x\n", address,
+				 *((uint16_t *)address));
 			break;
 
 		default:
-			ccprintf("read 0x%pP = 0x%08x\n",  address, *address);
+			ccprintf("read 0x%p = 0x%08x\n", address, *address);
 			break;
 		}
 		return EC_SUCCESS;
@@ -171,17 +169,17 @@ static int command_read_word(int argc, char **argv)
 
 	switch (access_size) {
 	case 1:
-		ccprintf("write 0x%pP = 0x%02x\n", address, (uint8_t)value);
-		cflush();  /* Flush before writing in case this crashes */
+		ccprintf("write 0x%p = 0x%02x\n", address, (uint8_t)value);
+		cflush(); /* Flush before writing in case this crashes */
 		*((uint8_t *)address) = (uint8_t)value;
 		break;
 	case 2:
-		ccprintf("write 0x%pP = 0x%04x\n", address, (uint16_t)value);
+		ccprintf("write 0x%p = 0x%04x\n", address, (uint16_t)value);
 		cflush();
 		*((uint16_t *)address) = (uint16_t)value;
 		break;
 	default:
-		ccprintf("write 0x%pP = 0x%02x\n", address, value);
+		ccprintf("write 0x%p = 0x%02x\n", address, value);
 		cflush();
 		*address = value;
 		break;
@@ -190,9 +188,8 @@ static int command_read_word(int argc, char **argv)
 	return EC_SUCCESS;
 }
 
-DECLARE_CONSOLE_COMMAND_FLAGS
-	(rw, command_read_word,
-	 "[.b|.h] addr [value]",
-	 "Read or write a word in memory optionally specifying the size",
-	 CMD_FLAG_RESTRICTED);
-#endif	/* CONFIG_CMD_RW */
+DECLARE_CONSOLE_COMMAND_FLAGS(
+	rw, command_read_word, "[.b|.h] addr [value]",
+	"Read or write a word in memory optionally specifying the size",
+	CMD_FLAG_RESTRICTED);
+#endif /* CONFIG_CMD_RW */
diff --git a/common/mkbp_event.c b/common/mkbp_event.c
index d67951c3b3..e602f81baf 100644
--- a/common/mkbp_event.c
+++ b/common/mkbp_event.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -18,8 +18,8 @@
 #include "util.h"
 
 #define CPUTS(outstr) cputs(CC_COMMAND, outstr)
-#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ##args)
 
 /*
  * Tracks the current state of the MKBP interrupt send from the EC to the AP.
@@ -165,7 +165,7 @@ static int mkbp_set_host_active(int active, uint32_t *timestamp)
 	return mkbp_set_host_active_via_custom(active, timestamp);
 #elif defined(CONFIG_MKBP_USE_HOST_EVENT)
 	return mkbp_set_host_active_via_event(active, timestamp);
-#elif defined(CONFIG_MKBP_USE_GPIO) ||\
+#elif defined(CONFIG_MKBP_USE_GPIO) || \
 	defined(CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT)
 	return mkbp_set_host_active_via_gpio(active, timestamp);
 #elif defined(CONFIG_MKBP_USE_HECI)
@@ -185,10 +185,9 @@ static inline int host_is_sleeping(void)
 
 #ifdef CONFIG_POWER_TRACK_HOST_SLEEP_STATE
 	enum host_sleep_event sleep_state = power_get_host_sleep_state();
-	is_sleeping |=
-		(sleep_state == HOST_SLEEP_EVENT_S0IX_SUSPEND ||
-		 sleep_state == HOST_SLEEP_EVENT_S3_SUSPEND ||
-		 sleep_state == HOST_SLEEP_EVENT_S3_WAKEABLE_SUSPEND);
+	is_sleeping |= (sleep_state == HOST_SLEEP_EVENT_S0IX_SUSPEND ||
+			sleep_state == HOST_SLEEP_EVENT_S3_SUSPEND ||
+			sleep_state == HOST_SLEEP_EVENT_S3_WAKEABLE_SUSPEND);
 #endif
 	return is_sleeping;
 }
@@ -202,7 +201,7 @@ static inline int host_is_sleeping(void)
 static void force_mkbp_if_events(void);
 DECLARE_DEFERRED(force_mkbp_if_events);
 
-static void activate_mkbp_with_events(uint32_t events_to_add)
+test_export_static void activate_mkbp_with_events(uint32_t events_to_add)
 {
 	int interrupt_id = -1;
 	int skip_interrupt = 0;
@@ -216,16 +215,16 @@ static void activate_mkbp_with_events(uint32_t events_to_add)
 	 */
 	if (events_to_add == BIT(EC_MKBP_EVENT_HOST_EVENT) ||
 	    events_to_add == BIT(EC_MKBP_EVENT_HOST_EVENT64))
-		skip_interrupt = host_is_sleeping() &&
-				!(host_get_events() &
-				mkbp_host_event_wake_mask);
+		skip_interrupt =
+			host_is_sleeping() &&
+			!(host_get_events() & mkbp_host_event_wake_mask);
 #endif /* CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK */
 
 #ifdef CONFIG_MKBP_EVENT_WAKEUP_MASK
 	/* Check to see if this MKBP event should wake the system. */
 	if (!skip_interrupt)
 		skip_interrupt = host_is_sleeping() &&
-			!(events_to_add & mkbp_event_wake_mask);
+				 !(events_to_add & mkbp_event_wake_mask);
 #endif /* CONFIG_MKBP_EVENT_WAKEUP_MASK */
 
 	mutex_lock(&state.lock);
@@ -257,8 +256,8 @@ static void activate_mkbp_with_events(uint32_t events_to_add)
 	if (state.interrupt == INTERRUPT_INACTIVE_TO_ACTIVE &&
 	    interrupt_id == state.interrupt_id) {
 		schedule_deferred = 1;
-		state.interrupt = rv == EC_SUCCESS ? INTERRUPT_ACTIVE
-						   : INTERRUPT_INACTIVE;
+		state.interrupt = rv == EC_SUCCESS ? INTERRUPT_ACTIVE :
+						     INTERRUPT_INACTIVE;
 	}
 	mutex_unlock(&state.lock);
 
@@ -308,8 +307,8 @@ static void force_mkbp_if_events(void)
 		 * of events or we exceed number of attempts, so marking
 		 * interrupt as INACTIVE doesn't affect failed_attempts counter.
 		 * If we need to send interrupt once again
-		 * activate_mkbp_with_events() will set interrupt state to ACTIVE
-		 * before this function will be called.
+		 * activate_mkbp_with_events() will set interrupt state to
+		 * ACTIVE before this function will be called.
 		 */
 		if (++state.failed_attempts < 3) {
 			send_mkbp_interrupt = 1;
@@ -456,8 +455,7 @@ static enum ec_status mkbp_get_next_event(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_GET_NEXT_EVENT,
-		     mkbp_get_next_event,
+DECLARE_HOST_COMMAND(EC_CMD_GET_NEXT_EVENT, mkbp_get_next_event,
 		     EC_VER_MASK(0) | EC_VER_MASK(1) | EC_VER_MASK(2));
 
 #ifdef CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK
@@ -473,12 +471,11 @@ mkbp_get_host_event_wake_mask(struct host_cmd_handler_args *args)
 	return EC_RES_SUCCESS;
 }
 DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_GET_WAKE_MASK,
-		     mkbp_get_host_event_wake_mask,
-		     EC_VER_MASK(0));
+		     mkbp_get_host_event_wake_mask, EC_VER_MASK(0));
 #endif /* CONFIG_MKBP_USE_HOST_EVENT */
 #endif /* CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK */
 
-#if defined(CONFIG_MKBP_EVENT_WAKEUP_MASK) ||	\
+#if defined(CONFIG_MKBP_EVENT_WAKEUP_MASK) || \
 	defined(CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK)
 static enum ec_status hc_mkbp_wake_mask(struct host_cmd_handler_args *args)
 {
@@ -517,8 +514,7 @@ static enum ec_status hc_mkbp_wake_mask(struct host_cmd_handler_args *args)
 		case EC_MKBP_HOST_EVENT_WAKE_MASK:
 			CPRINTF("MKBP hostevent mask updated to: 0x%08x "
 				"(was 0x%08x)\n",
-				p->new_wake_mask,
-				mkbp_host_event_wake_mask);
+				p->new_wake_mask, mkbp_host_event_wake_mask);
 			mkbp_host_event_wake_mask = p->new_wake_mask;
 			break;
 #endif /* CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK */
@@ -543,11 +539,9 @@ static enum ec_status hc_mkbp_wake_mask(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_MKBP_WAKE_MASK,
-		     hc_mkbp_wake_mask,
-		     EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_MKBP_WAKE_MASK, hc_mkbp_wake_mask, EC_VER_MASK(0));
 
-static int command_mkbp_wake_mask(int argc, char **argv)
+static int command_mkbp_wake_mask(int argc, const char **argv)
 {
 	if (argc == 3) {
 		char *e;
@@ -582,3 +576,15 @@ DECLARE_CONSOLE_COMMAND(mkbpwakemask, command_mkbp_wake_mask,
 			"[event | hostevent] [new_mask]",
 			"Show or set MKBP event/hostevent wake mask");
 #endif /* CONFIG_MKBP_(HOST)?EVENT_WAKEUP_MASK */
+
+#ifdef TEST_BUILD
+void mkbp_event_clear_all(void)
+{
+	mutex_lock(&state.lock);
+	state.events = 0;
+	mutex_unlock(&state.lock);
+
+	/* Reset the interrupt line */
+	mkbp_set_host_active(0, NULL);
+}
+#endif
diff --git a/common/mkbp_fifo.c b/common/mkbp_fifo.c
index c394d9fc77..dfcf87814e 100644
--- a/common/mkbp_fifo.c
+++ b/common/mkbp_fifo.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -15,7 +15,7 @@
 #include "util.h"
 
 /* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ##args)
 
 /*
  * Common FIFO depth.  This needs to be big enough not to overflow if a
@@ -26,9 +26,9 @@
  * which is non-trivial but not horrible.
  */
 
-static uint32_t fifo_start;	/* first entry */
-static uint32_t fifo_end;	/* last entry */
-static atomic_t fifo_entries;	/* number of existing entries */
+static uint32_t fifo_start; /* first entry */
+static uint32_t fifo_end; /* last entry */
+static atomic_t fifo_entries; /* number of existing entries */
 static uint8_t fifo_max_depth = FIFO_DEPTH;
 static struct ec_response_get_next_event fifo[FIFO_DEPTH];
 
@@ -114,7 +114,6 @@ void mkbp_fifo_depth_update(uint8_t new_max_depth)
 	fifo_max_depth = new_max_depth;
 }
 
-
 void mkbp_fifo_clear_keyboard(void)
 {
 	int i, new_fifo_entries = 0;
@@ -180,8 +179,7 @@ test_mockable int mkbp_fifo_add(uint8_t event_type, const uint8_t *buffp)
 	mutex_lock(&fifo_add_mutex);
 	if (fifo_entries >= fifo_max_depth) {
 		mutex_unlock(&fifo_add_mutex);
-		CPRINTS("MKBP common FIFO depth %d reached",
-			fifo_max_depth);
+		CPRINTS("MKBP common FIFO depth %d reached", fifo_max_depth);
 
 		return EC_ERROR_OVERFLOW;
 	}
diff --git a/common/mkbp_info.c b/common/mkbp_info.c
index 52d26f407b..c195eda888 100644
--- a/common/mkbp_info.c
+++ b/common/mkbp_info.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors.
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,7 +25,7 @@ __overridable int mkbp_support_volume_buttons(void)
 #endif
 }
 
-static uint32_t get_supported_buttons(void)
+test_export_static uint32_t get_supported_buttons(void)
 {
 	uint32_t val = 0;
 
@@ -44,7 +44,7 @@ static uint32_t get_supported_buttons(void)
 	return val;
 }
 
-static uint32_t get_supported_switches(void)
+test_export_static uint32_t get_supported_switches(void)
 {
 	uint32_t val = 0;
 
diff --git a/common/mkbp_input_devices.c b/common/mkbp_input_devices.c
index 7cba670eb1..6cc277ab98 100644
--- a/common/mkbp_input_devices.c
+++ b/common/mkbp_input_devices.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,7 +20,7 @@
 #include "tablet_mode.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ##args)
 
 /* Buttons and switch state. */
 static uint32_t mkbp_button_state;
@@ -69,7 +69,7 @@ void mkbp_button_update(enum keyboard_button_type button, int is_pressed)
 	CPRINTS("mkbp buttons: %x", mkbp_button_state);
 
 	mkbp_fifo_add(EC_MKBP_EVENT_BUTTON,
-			(const uint8_t *)&mkbp_button_state);
+		      (const uint8_t *)&mkbp_button_state);
 };
 
 void mkbp_update_switches(uint32_t sw, int state)
@@ -86,10 +86,9 @@ void mkbp_update_switches(uint32_t sw, int state)
 	 */
 	if (mkbp_init_done)
 		mkbp_fifo_add(EC_MKBP_EVENT_SWITCH,
-				(const uint8_t *)&mkbp_switch_state);
+			      (const uint8_t *)&mkbp_switch_state);
 }
 
-
 /*****************************************************************************/
 /* Hooks */
 
@@ -99,8 +98,7 @@ void mkbp_update_switches(uint32_t sw, int state)
  */
 static void keyboard_power_button(void)
 {
-	mkbp_button_update(KEYBOARD_BUTTON_POWER,
-			       power_button_is_pressed());
+	mkbp_button_update(KEYBOARD_BUTTON_POWER, power_button_is_pressed());
 }
 DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, keyboard_power_button,
 	     HOOK_PRIO_DEFAULT);
@@ -142,7 +140,7 @@ static void mkbp_report_switch_on_init(void)
 	/* All switches initialized, report switch state to AP */
 	mkbp_init_done = true;
 	mkbp_fifo_add(EC_MKBP_EVENT_SWITCH,
-			(const uint8_t *)&mkbp_switch_state);
+		      (const uint8_t *)&mkbp_switch_state);
 }
 DECLARE_HOOK(HOOK_INIT, mkbp_report_switch_on_init, HOOK_PRIO_LAST);
 
@@ -188,7 +186,7 @@ uint8_t keyboard_cols = KEYBOARD_COLS_MAX;
 static void simulate_key(int row, int col, int pressed)
 {
 	if ((simulated_key[col] & BIT(row)) == ((pressed ? 1 : 0) << row))
-		return;  /* No change */
+		return; /* No change */
 
 	simulated_key[col] &= ~BIT(row);
 	if (pressed)
@@ -197,7 +195,7 @@ static void simulate_key(int row, int col, int pressed)
 	mkbp_fifo_add((uint8_t)EC_MKBP_EVENT_KEY_MATRIX, simulated_key);
 }
 
-static int command_mkbp_keyboard_press(int argc, char **argv)
+static int command_mkbp_keyboard_press(int argc, const char **argv)
 {
 	if (argc == 1) {
 		int i, j;
@@ -239,7 +237,6 @@ static int command_mkbp_keyboard_press(int argc, char **argv)
 	return EC_SUCCESS;
 }
 DECLARE_CONSOLE_COMMAND(kbpress, command_mkbp_keyboard_press,
-			"[col row [0 | 1]]",
-			"Simulate keypress");
+			"[col row [0 | 1]]", "Simulate keypress");
 
 #endif /* !defined(HAS_TASK_KEYSCAN) */
diff --git a/common/mock/README.md b/common/mock/README.md
index c7695531b6..62f53f5416 100644
--- a/common/mock/README.md
+++ b/common/mock/README.md
@@ -38,7 +38,7 @@ one.
 Example `.mocklist`:
 
 ```c
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/common/mock/adc_mock.c b/common/mock/adc_mock.c
index 9727c560d3..35cf4aadb5 100644
--- a/common/mock/adc_mock.c
+++ b/common/mock/adc_mock.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/common/mock/battery_mock.c b/common/mock/battery_mock.c
index 63e94c660b..0d6b4fdb22 100644
--- a/common/mock/battery_mock.c
+++ b/common/mock/battery_mock.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -141,7 +141,7 @@ void set_battery_time_to_full(int new_value)
 }
 
 #define MAX_DEVICE_NAME_LENGTH 40
-static char battery_device_name_value[MAX_DEVICE_NAME_LENGTH+1] = "?";
+static char battery_device_name_value[MAX_DEVICE_NAME_LENGTH + 1] = "?";
 int battery_device_name(char *dest, int size)
 {
 	int i;
@@ -159,12 +159,13 @@ void set_battery_device_name(char *new_value)
 
 	for (i = 0; i < size && i < MAX_DEVICE_NAME_LENGTH; ++i)
 		battery_device_name_value[i] = new_value[i];
-	for (; i < MAX_DEVICE_NAME_LENGTH+1; ++i)
+	for (; i < MAX_DEVICE_NAME_LENGTH + 1; ++i)
 		battery_device_name_value[i] = '\0';
 }
 
 #define MAX_DEVICE_CHEMISTRY_LENGTH 40
-static char battery_device_chemistry_value[MAX_DEVICE_CHEMISTRY_LENGTH+1] = "?";
+static char battery_device_chemistry_value[MAX_DEVICE_CHEMISTRY_LENGTH + 1] =
+	"?";
 int battery_device_chemistry(char *dest, int size)
 {
 	int i;
@@ -182,7 +183,7 @@ void set_battery_device_chemistry(char *new_value)
 
 	for (i = 0; i < size && i < MAX_DEVICE_CHEMISTRY_LENGTH; ++i)
 		battery_device_chemistry_value[i] = new_value[i];
-	for (; i < MAX_DEVICE_CHEMISTRY_LENGTH+1; ++i)
+	for (; i < MAX_DEVICE_CHEMISTRY_LENGTH + 1; ++i)
 		battery_device_chemistry_value[i] = '\0';
 }
 
@@ -194,7 +195,7 @@ static int battery_temperature_value = 20;
 static int battery_voltage_value = 5000;
 void battery_get_params(struct batt_params *batt)
 {
-	struct batt_params batt_new = {0};
+	struct batt_params batt_new = { 0 };
 
 	batt_new.temperature = battery_temperature_value;
 	batt_new.state_of_charge = battery_soc_value;
diff --git a/common/mock/build.mk b/common/mock/build.mk
index fd87f40990..a8b109429c 100644
--- a/common/mock/build.mk
+++ b/common/mock/build.mk
@@ -1,4 +1,4 @@
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -8,6 +8,7 @@ mock-$(HAS_MOCK_ADC) += adc_mock.o
 mock-$(HAS_MOCK_BATTERY) += battery_mock.o
 mock-$(HAS_MOCK_CHARGE_MANAGER) += charge_manager_mock.o
 mock-$(HAS_MOCK_FP_SENSOR) += fp_sensor_mock.o
+mock-$(HAS_MOCK_FPSENSOR_CRYPTO) += fpsensor_crypto_mock.o
 mock-$(HAS_MOCK_FPSENSOR_DETECT) += fpsensor_detect_mock.o
 mock-$(HAS_MOCK_FPSENSOR_STATE) += fpsensor_state_mock.o
 mock-$(HAS_MOCK_MKBP_EVENTS) += mkbp_events_mock.o
diff --git a/common/mock/charge_manager_mock.c b/common/mock/charge_manager_mock.c
index 11661d2b2e..b27e7de241 100644
--- a/common/mock/charge_manager_mock.c
+++ b/common/mock/charge_manager_mock.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -47,4 +47,4 @@ void mock_charge_manager_set_vbus_voltage(int voltage_mv)
 }
 
 struct mock_ctrl_charge_manager mock_ctrl_charge_manager =
-MOCK_CTRL_DEFAULT_CHARGE_MANAGER;
+	MOCK_CTRL_DEFAULT_CHARGE_MANAGER;
diff --git a/common/mock/dp_alt_mode_mock.c b/common/mock/dp_alt_mode_mock.c
index 29f76bdb7a..e261415aaa 100644
--- a/common/mock/dp_alt_mode_mock.c
+++ b/common/mock/dp_alt_mode_mock.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,8 +18,8 @@
 #endif
 
 #ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 #else
 #define CPRINTF(format, args...)
 #define CPRINTS(format, args...)
diff --git a/common/mock/fp_sensor_mock.c b/common/mock/fp_sensor_mock.c
index 363f092ff1..4db25a821c 100644
--- a/common/mock/fp_sensor_mock.c
+++ b/common/mock/fp_sensor_mock.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -59,9 +59,8 @@ int fp_sensor_acquire_image_with_mode(uint8_t *image_data, int mode)
 	return mock_ctrl_fp_sensor.fp_sensor_acquire_image_with_mode_return;
 }
 
-int fp_finger_match(void *templ, uint32_t templ_count,
-		    uint8_t *image, int32_t *match_index,
-		    uint32_t *update_bitmap)
+int fp_finger_match(void *templ, uint32_t templ_count, uint8_t *image,
+		    int32_t *match_index, uint32_t *update_bitmap)
 {
 	return mock_ctrl_fp_sensor.fp_finger_match_return;
 }
diff --git a/common/mock/fpsensor_crypto_mock.c b/common/mock/fpsensor_crypto_mock.c
new file mode 100644
index 0000000000..f2cc425c8f
--- /dev/null
+++ b/common/mock/fpsensor_crypto_mock.c
@@ -0,0 +1,63 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file fpsensor_crypto_mock.c
+ * @brief Mock fpsensor_crypto library
+ */
+#include "sha256.h"
+#include <stdio.h>
+#include <stdint.h>
+#include <string.h>
+#include "assert.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "fpsensor_private.h"
+#include "mock/fpsensor_crypto_mock.h"
+
+#ifndef TEST_BUILD
+#error "Mocks should only be in the test build."
+#endif
+
+struct mock_ctrl_fpsensor_crypto mock_ctrl_fpsensor_crypto =
+	MOCK_CTRL_DEFAULT_FPSENSOR_CRYPTO;
+
+#define MESSAGE_ZERO_IDX 0
+#define MESSAGE_FF_IDX 1
+typedef uint8_t key_message_pair[FP_POSITIVE_MATCH_SECRET_BYTES];
+
+key_message_pair fake_fpsensor_crypto[] = {
+	{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+	{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+};
+
+BUILD_ASSERT(sizeof(key_message_pair) == FP_POSITIVE_MATCH_SECRET_BYTES);
+
+/* Mock compute_hmac_sha256 for unit or fuzz tests. */
+void compute_hmac_sha256(uint8_t *output, const uint8_t *key, const int key_len,
+			 const uint8_t *message, const int message_len)
+{
+	switch (mock_ctrl_fpsensor_crypto.output_type) {
+	case MOCK_CTRL_FPSENSOR_CRYPTO_SHA256_TYPE_REAL:
+		hmac_SHA256(output, key, key_len, message, message_len);
+		break;
+	case MOCK_CTRL_FPSENSOR_CRYPTO_SHA256_TYPE_ZEROS:
+		memcpy(output, fake_fpsensor_crypto[MESSAGE_ZERO_IDX],
+		       FP_POSITIVE_MATCH_SECRET_BYTES);
+		break;
+	case MOCK_CTRL_FPSENSOR_CRYPTO_SHA256_TYPE_FF:
+		memcpy(output, fake_fpsensor_crypto[MESSAGE_FF_IDX],
+		       FP_POSITIVE_MATCH_SECRET_BYTES);
+		break;
+	default:
+		assert(0);
+		break;
+	};
+}
diff --git a/common/mock/fpsensor_detect_mock.c b/common/mock/fpsensor_detect_mock.c
index 6e3ca839f1..50f27f92bf 100644
--- a/common/mock/fpsensor_detect_mock.c
+++ b/common/mock/fpsensor_detect_mock.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/common/mock/fpsensor_state_mock.c b/common/mock/fpsensor_state_mock.c
index c3092fe860..cbeb29ae3c 100644
--- a/common/mock/fpsensor_state_mock.c
+++ b/common/mock/fpsensor_state_mock.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,6 +7,7 @@
 #include <string.h>
 
 #include "common.h"
+#include "driver/fingerprint/fpsensor.h"
 #include "ec_commands.h"
 #include "test_util.h"
 
@@ -21,6 +22,38 @@ const uint8_t default_fake_tpm_seed[] = {
 };
 BUILD_ASSERT(sizeof(default_fake_tpm_seed) == FP_CONTEXT_TPM_BYTES);
 
+const uint8_t default_fake_fp_positive_match_salt
+	[FP_MAX_FINGER_COUNT][FP_POSITIVE_MATCH_SALT_BYTES] = {
+		{ 0x04, 0x1f, 0x5a, 0xac, 0x5f, 0x79, 0x10, 0xaf, 0x04, 0x1d,
+		  0x46, 0x3a, 0x5f, 0x08, 0xee, 0xcb },
+		{ 0x04, 0x1f, 0x5a, 0xac, 0x5f, 0x79, 0x10, 0xaf, 0x04, 0x1d,
+		  0x46, 0x3a, 0x5f, 0x08, 0xee, 0xcb },
+		{ 0x04, 0x1f, 0x5a, 0xac, 0x5f, 0x79, 0x10, 0xaf, 0x04, 0x1d,
+		  0x46, 0x3a, 0x5f, 0x08, 0xee, 0xcb },
+		{ 0x04, 0x1f, 0x5a, 0xac, 0x5f, 0x79, 0x10, 0xaf, 0x04, 0x1d,
+		  0x46, 0x3a, 0x5f, 0x08, 0xee, 0xcb },
+		{ 0x04, 0x1f, 0x5a, 0xac, 0x5f, 0x79, 0x10, 0xaf, 0x04, 0x1d,
+		  0x46, 0x3a, 0x5f, 0x08, 0xee, 0xcb }
+	};
+BUILD_ASSERT(sizeof(default_fake_fp_positive_match_salt) ==
+	     FP_MAX_FINGER_COUNT * FP_POSITIVE_MATCH_SALT_BYTES);
+
+const uint8_t trivial_fp_positive_match_salt
+	[FP_MAX_FINGER_COUNT][FP_POSITIVE_MATCH_SALT_BYTES] = {
+		{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		  0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+		{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		  0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+		{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		  0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+		{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		  0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+		{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		  0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }
+	};
+BUILD_ASSERT(sizeof(trivial_fp_positive_match_salt) ==
+	     FP_MAX_FINGER_COUNT * FP_POSITIVE_MATCH_SALT_BYTES);
+
 int fpsensor_state_mock_set_tpm_seed(
 	const uint8_t tpm_seed[FP_CONTEXT_TPM_BYTES])
 {
diff --git a/common/mock/mkbp_events_mock.c b/common/mock/mkbp_events_mock.c
index d42c06fdec..3f4d76b659 100644
--- a/common/mock/mkbp_events_mock.c
+++ b/common/mock/mkbp_events_mock.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/common/mock/rollback_mock.c b/common/mock/rollback_mock.c
index 2b26d9d8d7..e68616df53 100644
--- a/common/mock/rollback_mock.c
+++ b/common/mock/rollback_mock.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,10 +23,9 @@
 struct mock_ctrl_rollback mock_ctrl_rollback = MOCK_CTRL_DEFAULT_ROLLBACK;
 
 static const uint8_t fake_rollback_secret[] = {
-	0xcf, 0xe3, 0x23, 0x76, 0x35, 0x04, 0xc2, 0x0f,
-	0x0d, 0xb6, 0x02, 0xa9, 0x68, 0xba, 0x2a, 0x61,
-	0x86, 0x2a, 0x85, 0xd1, 0xca, 0x09, 0x54, 0x8a,
-	0x6b, 0xe2, 0xe3, 0x38, 0xde, 0x5d, 0x59, 0x14,
+	0xcf, 0xe3, 0x23, 0x76, 0x35, 0x04, 0xc2, 0x0f, 0x0d, 0xb6, 0x02,
+	0xa9, 0x68, 0xba, 0x2a, 0x61, 0x86, 0x2a, 0x85, 0xd1, 0xca, 0x09,
+	0x54, 0x8a, 0x6b, 0xe2, 0xe3, 0x38, 0xde, 0x5d, 0x59, 0x14,
 };
 
 BUILD_ASSERT(sizeof(fake_rollback_secret) == CONFIG_ROLLBACK_SECRET_SIZE);
diff --git a/common/mock/tcpc_mock.c b/common/mock/tcpc_mock.c
index a9bb12b356..31dda7eba1 100644
--- a/common/mock/tcpc_mock.c
+++ b/common/mock/tcpc_mock.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -125,8 +125,7 @@ static int mock_set_msg_header(int port, int power_role, int data_role)
 		return EC_SUCCESS;
 
 	ccprints("[TCPC] Setting TCPM-side header to %s %s",
-		 from_pd_power_role(power_role),
-		 from_pd_data_role(data_role));
+		 from_pd_power_role(power_role), from_pd_data_role(data_role));
 
 	return EC_SUCCESS;
 }
@@ -141,8 +140,8 @@ static int mock_get_message_raw(int port, uint32_t *payload, int *head)
 	return EC_SUCCESS;
 }
 
-static int mock_transmit(int port, enum tcpci_msg_type type,
-			 uint16_t header, const uint32_t *data)
+static int mock_transmit(int port, enum tcpci_msg_type type, uint16_t header,
+			 const uint32_t *data)
 {
 	return EC_SUCCESS;
 }
diff --git a/common/mock/tcpci_i2c_mock.c b/common/mock/tcpci_i2c_mock.c
index c9b9f71738..a0e59ecc44 100644
--- a/common/mock/tcpci_i2c_mock.c
+++ b/common/mock/tcpci_i2c_mock.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,15 +18,19 @@
 #define VERIFY_TIMEOUT (5 * SECOND)
 
 struct tcpci_reg {
-	uint8_t		offset;
-	uint8_t		size;
-	uint16_t	value;
-	const char	*name;
+	uint8_t offset;
+	uint8_t size;
+	uint16_t value;
+	const char *name;
 };
 
-#define TCPCI_REG(reg_name, reg_size)					\
-	[reg_name] = { .offset = (reg_name), .size = (reg_size),	\
-			.value = 0, .name = #reg_name, }
+#define TCPCI_REG(reg_name, reg_size) \
+	[reg_name] = {                \
+		.offset = (reg_name), \
+		.size = (reg_size),   \
+		.value = 0,           \
+		.name = #reg_name,    \
+	}
 
 static struct tcpci_reg tcpci_regs[] = {
 	TCPCI_REG(TCPC_REG_VENDOR_ID, 2),
@@ -76,111 +80,109 @@ static int tx_retry_cnt = -1;
 static uint8_t rx_buffer[BUFFER_SIZE];
 static int rx_pos = -1;
 
-static const char * const ctrl_msg_name[] = {
-	[0]				= "C-RSVD_0",
-	[PD_CTRL_GOOD_CRC]		= "C-GOODCRC",
-	[PD_CTRL_GOTO_MIN]		= "C-GOTOMIN",
-	[PD_CTRL_ACCEPT]		= "C-ACCEPT",
-	[PD_CTRL_REJECT]		= "C-REJECT",
-	[PD_CTRL_PING]			= "C-PING",
-	[PD_CTRL_PS_RDY]		= "C-PSRDY",
-	[PD_CTRL_GET_SOURCE_CAP]	= "C-GET_SRC_CAP",
-	[PD_CTRL_GET_SINK_CAP]		= "C-GET_SNK_CAP",
-	[PD_CTRL_DR_SWAP]		= "C-DR_SWAP",
-	[PD_CTRL_PR_SWAP]		= "C-PR_SWAP",
-	[PD_CTRL_VCONN_SWAP]		= "C-VCONN_SW",
-	[PD_CTRL_WAIT]			= "C-WAIT",
-	[PD_CTRL_SOFT_RESET]		= "C-SOFT-RESET",
-	[14]				= "C-RSVD_14",
-	[15]				= "C-RSVD_15",
-	[PD_CTRL_NOT_SUPPORTED]		= "C-NOT_SUPPORTED",
-	[PD_CTRL_GET_SOURCE_CAP_EXT]	= "C-GET_SRC_CAP-EXT",
-	[PD_CTRL_GET_STATUS]		= "C-GET-STATUS",
-	[PD_CTRL_FR_SWAP]		= "C-FR_SWAP",
-	[PD_CTRL_GET_PPS_STATUS]	= "C-GET_PPS_STATUS",
-	[PD_CTRL_GET_COUNTRY_CODES]	= "C-GET_COUNTRY_CODES",
-	[PD_CTRL_GET_SINK_CAP_EXT]	= "C-GET_SINK_CAP_EXT",
-	[PD_CTRL_GET_SOURCE_INFO]	= "C-GET_SOURCE_INFO",
-	[PD_CTRL_GET_REVISION]		= "C-GET_REVISION",
+static const char *const ctrl_msg_name[] = {
+	[0] = "C-RSVD_0",
+	[PD_CTRL_GOOD_CRC] = "C-GOODCRC",
+	[PD_CTRL_GOTO_MIN] = "C-GOTOMIN",
+	[PD_CTRL_ACCEPT] = "C-ACCEPT",
+	[PD_CTRL_REJECT] = "C-REJECT",
+	[PD_CTRL_PING] = "C-PING",
+	[PD_CTRL_PS_RDY] = "C-PSRDY",
+	[PD_CTRL_GET_SOURCE_CAP] = "C-GET_SRC_CAP",
+	[PD_CTRL_GET_SINK_CAP] = "C-GET_SNK_CAP",
+	[PD_CTRL_DR_SWAP] = "C-DR_SWAP",
+	[PD_CTRL_PR_SWAP] = "C-PR_SWAP",
+	[PD_CTRL_VCONN_SWAP] = "C-VCONN_SW",
+	[PD_CTRL_WAIT] = "C-WAIT",
+	[PD_CTRL_SOFT_RESET] = "C-SOFT-RESET",
+	[14] = "C-RSVD_14",
+	[15] = "C-RSVD_15",
+	[PD_CTRL_NOT_SUPPORTED] = "C-NOT_SUPPORTED",
+	[PD_CTRL_GET_SOURCE_CAP_EXT] = "C-GET_SRC_CAP-EXT",
+	[PD_CTRL_GET_STATUS] = "C-GET-STATUS",
+	[PD_CTRL_FR_SWAP] = "C-FR_SWAP",
+	[PD_CTRL_GET_PPS_STATUS] = "C-GET_PPS_STATUS",
+	[PD_CTRL_GET_COUNTRY_CODES] = "C-GET_COUNTRY_CODES",
+	[PD_CTRL_GET_SINK_CAP_EXT] = "C-GET_SINK_CAP_EXT",
+	[PD_CTRL_GET_SOURCE_INFO] = "C-GET_SOURCE_INFO",
+	[PD_CTRL_GET_REVISION] = "C-GET_REVISION",
 };
 
-static const char * const data_msg_name[] = {
-	[0]				= "D-RSVD_0",
-	[PD_DATA_SOURCE_CAP]		= "D-SRC_CAP",
-	[PD_DATA_REQUEST]		= "D-REQUEST",
-	[PD_DATA_BIST]			= "D-BIST",
-	[PD_DATA_SINK_CAP]		= "D-SNK_CAP",
+static const char *const data_msg_name[] = {
+	[0] = "D-RSVD_0",
+	[PD_DATA_SOURCE_CAP] = "D-SRC_CAP",
+	[PD_DATA_REQUEST] = "D-REQUEST",
+	[PD_DATA_BIST] = "D-BIST",
+	[PD_DATA_SINK_CAP] = "D-SNK_CAP",
 	/* 5-14 Reserved for REV 2.0 */
-	[PD_DATA_BATTERY_STATUS]	= "D-BATTERY_STATUS",
-	[PD_DATA_ALERT]			= "D-ALERT",
-	[PD_DATA_GET_COUNTRY_INFO]	= "D-GET_COUNTRY_CODES",
+	[PD_DATA_BATTERY_STATUS] = "D-BATTERY_STATUS",
+	[PD_DATA_ALERT] = "D-ALERT",
+	[PD_DATA_GET_COUNTRY_INFO] = "D-GET_COUNTRY_CODES",
 	/* 8-14 Reserved for REV 3.0 */
-	[PD_DATA_ENTER_USB]		= "D-ENTER_USB",
-	[PD_DATA_EPR_REQUEST]		= "D-EPR_REQUEST",
-	[PD_DATA_EPR_MODE]		= "D-EPR_MODE",
-	[PD_DATA_SOURCE_INFO]		= "D-EPR_SOURCE_INFO",
-	[PD_DATA_REVISION]		= "D-REVISION",
+	[PD_DATA_ENTER_USB] = "D-ENTER_USB",
+	[PD_DATA_EPR_REQUEST] = "D-EPR_REQUEST",
+	[PD_DATA_EPR_MODE] = "D-EPR_MODE",
+	[PD_DATA_SOURCE_INFO] = "D-EPR_SOURCE_INFO",
+	[PD_DATA_REVISION] = "D-REVISION",
 	/* 13-14 Reserved for REV 3.0 */
-	[PD_DATA_VENDOR_DEF]		= "D-VDM",
+	[PD_DATA_VENDOR_DEF] = "D-VDM",
 };
 
-static const char * const ext_msg_name[] = {
-	[0]				= "X-RSVD_0",
-	[PD_EXT_SOURCE_CAP]		= "X-SRC_CAP",
-	[PD_EXT_STATUS]			= "X-STATUS",
-	[PD_EXT_GET_BATTERY_CAP]	= "X-GET_BATTERY_CAP",
-	[PD_EXT_GET_BATTERY_STATUS]	= "X-GET_BATTERY_STATUS",
-	[PD_EXT_BATTERY_CAP]		= "X-BATTERY_CAP",
-	[PD_EXT_GET_MANUFACTURER_INFO]	= "X-GET_MFR_INFO",
-	[PD_EXT_MANUFACTURER_INFO]	= "X-MFR_INFO",
-	[PD_EXT_SECURITY_REQUEST]	= "X-SECURITY_REQ",
-	[PD_EXT_SECURITY_RESPONSE]	= "X-SECURITY_RESP",
+static const char *const ext_msg_name[] = {
+	[0] = "X-RSVD_0",
+	[PD_EXT_SOURCE_CAP] = "X-SRC_CAP",
+	[PD_EXT_STATUS] = "X-STATUS",
+	[PD_EXT_GET_BATTERY_CAP] = "X-GET_BATTERY_CAP",
+	[PD_EXT_GET_BATTERY_STATUS] = "X-GET_BATTERY_STATUS",
+	[PD_EXT_BATTERY_CAP] = "X-BATTERY_CAP",
+	[PD_EXT_GET_MANUFACTURER_INFO] = "X-GET_MFR_INFO",
+	[PD_EXT_MANUFACTURER_INFO] = "X-MFR_INFO",
+	[PD_EXT_SECURITY_REQUEST] = "X-SECURITY_REQ",
+	[PD_EXT_SECURITY_RESPONSE] = "X-SECURITY_RESP",
 	[PD_EXT_FIRMWARE_UPDATE_REQUEST] = "X-FW_UP_REQ",
 	[PD_EXT_FIRMWARE_UPDATE_RESPONSE] = "X-FW_UP_RESP",
-	[PD_EXT_PPS_STATUS]		= "X-PPS_STATUS",
-	[PD_EXT_COUNTRY_INFO]		= "X-COUNTRY_INFO",
-	[PD_EXT_COUNTRY_CODES]		= "X-COUNTRY_CODES",
-	[PD_EXT_SINK_CAP]		= "X-SNK_CAP",
-	[PD_EXT_CONTROL]		= "X-CONTROL",
-	[PD_EXT_EPR_SOURCE_CAP]		= "X-EPR_SRC_CAP",
-	[PD_EXT_EPR_SINK_CAP]		= "X-EPR_SNK_CAP",
+	[PD_EXT_PPS_STATUS] = "X-PPS_STATUS",
+	[PD_EXT_COUNTRY_INFO] = "X-COUNTRY_INFO",
+	[PD_EXT_COUNTRY_CODES] = "X-COUNTRY_CODES",
+	[PD_EXT_SINK_CAP] = "X-SNK_CAP",
+	[PD_EXT_CONTROL] = "X-CONTROL",
+	[PD_EXT_EPR_SOURCE_CAP] = "X-EPR_SRC_CAP",
+	[PD_EXT_EPR_SINK_CAP] = "X-EPR_SNK_CAP",
 };
 
-static const char * const rev_name[] = {
+static const char *const rev_name[] = {
 	[PD_REV10] = "1.0",
 	[PD_REV20] = "2.0",
 	[PD_REV30] = "3.0",
 	[3] = "RSVD",
 };
 
-static const char * const drole_name[] = {
+static const char *const drole_name[] = {
 	[PD_ROLE_UFP] = "UFP",
 	[PD_ROLE_DFP] = "DFP",
 };
 
-static const char * const prole_name[] = {
+static const char *const prole_name[] = {
 	[PD_ROLE_SINK] = "SNK",
 	[PD_ROLE_SOURCE] = "SRC",
 };
 
 static void print_header(const char *prefix, uint16_t header)
 {
-	int type  = PD_HEADER_TYPE(header);
+	int type = PD_HEADER_TYPE(header);
 	int drole = PD_HEADER_DROLE(header);
-	int rev   = PD_HEADER_REV(header);
+	int rev = PD_HEADER_REV(header);
 	int prole = PD_HEADER_PROLE(header);
-	int id    = PD_HEADER_ID(header);
-	int cnt   = PD_HEADER_CNT(header);
-	int ext   = PD_HEADER_EXT(header);
-	const char *name = ext	? ext_msg_name[type]
-				: cnt
-					? data_msg_name[type]
-					: ctrl_msg_name[type];
-
-	ccprints("%s header=0x%x [%s %s %s %s id=%d cnt=%d ext=%d]",
-		 prefix, header,
-		 name, drole_name[drole], rev_name[rev], prole_name[prole],
-		 id, cnt, ext);
+	int id = PD_HEADER_ID(header);
+	int cnt = PD_HEADER_CNT(header);
+	int ext = PD_HEADER_EXT(header);
+	const char *name = ext ? ext_msg_name[type] :
+			   cnt ? data_msg_name[type] :
+				 ctrl_msg_name[type];
+
+	ccprints("%s header=0x%x [%s %s %s %s id=%d cnt=%d ext=%d]", prefix,
+		 header, name, drole_name[drole], rev_name[rev],
+		 prole_name[prole], id, cnt, ext);
 }
 
 static bool dead_battery(void)
@@ -193,11 +195,9 @@ static bool debug_accessory_indicator_supported(void)
 	return true;
 }
 
-static int verify_transmit(enum tcpci_msg_type want_tx_type,
-			   int want_tx_retry,
+static int verify_transmit(enum tcpci_msg_type want_tx_type, int want_tx_retry,
 			   enum pd_ctrl_msg_type want_ctrl_msg,
-			   enum pd_data_msg_type want_data_msg,
-			   int timeout)
+			   enum pd_data_msg_type want_data_msg, int timeout)
 {
 	uint64_t end_time = get_time().val + timeout;
 
@@ -215,10 +215,10 @@ static int verify_transmit(enum tcpci_msg_type want_tx_type,
 				tcpci_regs[TCPC_REG_TRANSMIT].value);
 			int tx_retry = TCPC_REG_TRANSMIT_RETRY(
 				tcpci_regs[TCPC_REG_TRANSMIT].value);
-			uint16_t header = UINT16_FROM_BYTE_ARRAY_LE(
-						tx_buffer, 1);
-			int pd_type  = PD_HEADER_TYPE(header);
-			int pd_cnt   = PD_HEADER_CNT(header);
+			uint16_t header =
+				UINT16_FROM_BYTE_ARRAY_LE(tx_buffer, 1);
+			int pd_type = PD_HEADER_TYPE(header);
+			int pd_cnt = PD_HEADER_CNT(header);
 
 			TEST_EQ(tx_type, want_tx_type, "%d");
 			if (want_tx_retry >= 0)
@@ -246,46 +246,34 @@ int verify_tcpci_transmit(enum tcpci_msg_type tx_type,
 			  enum pd_ctrl_msg_type ctrl_msg,
 			  enum pd_data_msg_type data_msg)
 {
-	return verify_transmit(tx_type, -1,
-			       ctrl_msg, data_msg,
-			       VERIFY_TIMEOUT);
+	return verify_transmit(tx_type, -1, ctrl_msg, data_msg, VERIFY_TIMEOUT);
 }
 
 int verify_tcpci_tx_timeout(enum tcpci_msg_type tx_type,
 			    enum pd_ctrl_msg_type ctrl_msg,
-			    enum pd_data_msg_type data_msg,
-			    int timeout)
+			    enum pd_data_msg_type data_msg, int timeout)
 {
-	return verify_transmit(tx_type, -1,
-			       ctrl_msg, data_msg,
-			       timeout);
+	return verify_transmit(tx_type, -1, ctrl_msg, data_msg, timeout);
 }
 
 int verify_tcpci_tx_retry_count(enum tcpci_msg_type tx_type,
 				enum pd_ctrl_msg_type ctrl_msg,
-				enum pd_data_msg_type data_msg,
-				int retry_count)
+				enum pd_data_msg_type data_msg, int retry_count)
 {
-	return verify_transmit(tx_type, retry_count,
-			       ctrl_msg, data_msg,
+	return verify_transmit(tx_type, retry_count, ctrl_msg, data_msg,
 			       VERIFY_TIMEOUT);
 }
 
 int verify_tcpci_tx_with_data(enum tcpci_msg_type tx_type,
-			      enum pd_data_msg_type data_msg,
-			      uint8_t *data,
-			      int data_bytes,
-			      int *msg_len,
-			      int timeout)
+			      enum pd_data_msg_type data_msg, uint8_t *data,
+			      int data_bytes, int *msg_len, int timeout)
 {
 	int rv;
 
 	if (timeout <= 0)
 		timeout = VERIFY_TIMEOUT;
 
-	rv = verify_transmit(tx_type, -1,
-			     0, data_msg,
-			     timeout);
+	rv = verify_transmit(tx_type, -1, 0, data_msg, timeout);
 	if (!rv) {
 		TEST_NE(data, NULL, "%p");
 		TEST_GE(data_bytes, tx_msg_cnt, "%d");
@@ -296,13 +284,9 @@ int verify_tcpci_tx_with_data(enum tcpci_msg_type tx_type,
 	return rv;
 }
 
-int verify_tcpci_possible_tx(struct possible_tx possible[],
-			     int possible_cnt,
-			     int *found_index,
-			     uint8_t *data,
-			     int data_bytes,
-			     int *msg_len,
-			     int timeout)
+int verify_tcpci_possible_tx(struct possible_tx possible[], int possible_cnt,
+			     int *found_index, uint8_t *data, int data_bytes,
+			     int *msg_len, int timeout)
 {
 	bool assert_on_timeout = true;
 	uint64_t end_time;
@@ -328,10 +312,10 @@ int verify_tcpci_possible_tx(struct possible_tx possible[],
 			int i;
 			int tx_type = TCPC_REG_TRANSMIT_TYPE(
 				tcpci_regs[TCPC_REG_TRANSMIT].value);
-			uint16_t header = UINT16_FROM_BYTE_ARRAY_LE(
-						tx_buffer, 1);
-			int pd_type  = PD_HEADER_TYPE(header);
-			int pd_cnt   = PD_HEADER_CNT(header);
+			uint16_t header =
+				UINT16_FROM_BYTE_ARRAY_LE(tx_buffer, 1);
+			int pd_type = PD_HEADER_TYPE(header);
+			int pd_cnt = PD_HEADER_CNT(header);
 
 			for (i = 0; i < possible_cnt; ++i) {
 				int want_tx_type = possible[i].tx_type;
@@ -352,8 +336,8 @@ int verify_tcpci_possible_tx(struct possible_tx possible[],
 						continue;
 
 					if (data != NULL) {
-						TEST_GE(data_bytes,
-							tx_msg_cnt, "%d");
+						TEST_GE(data_bytes, tx_msg_cnt,
+							"%d");
 						memcpy(data, tx_buffer,
 						       tx_msg_cnt);
 					}
@@ -391,9 +375,9 @@ void mock_tcpci_receive(enum tcpci_msg_type sop, uint16_t header,
 
 	for (i = 4; i < rx_buffer[0]; i += 4) {
 		rx_buffer[i] = *payload & 0xFF;
-		rx_buffer[i+1] = (*payload >> 8) & 0xFF;
-		rx_buffer[i+2] = (*payload >> 16) & 0xFF;
-		rx_buffer[i+3] = (*payload >> 24) & 0xFF;
+		rx_buffer[i + 1] = (*payload >> 8) & 0xFF;
+		rx_buffer[i + 2] = (*payload >> 16) & 0xFF;
+		rx_buffer[i + 3] = (*payload >> 24) & 0xFF;
 		payload++;
 	}
 
@@ -411,11 +395,11 @@ static void tcpci_reset_register_masks(void)
 	/*
 	 * Using table 4-1 for default mask values
 	 */
-	tcpci_regs[TCPC_REG_ALERT_MASK].value =			0x7FFF;
-	tcpci_regs[TCPC_REG_POWER_STATUS_MASK].value =		0xFF;
-	tcpci_regs[TCPC_REG_FAULT_STATUS_MASK].value =		0xFF;
-	tcpci_regs[TCPC_REG_EXT_STATUS_MASK].value =		0x01;
-	tcpci_regs[TCPC_REG_ALERT_EXTENDED_MASK].value =	0x07;
+	tcpci_regs[TCPC_REG_ALERT_MASK].value = 0x7FFF;
+	tcpci_regs[TCPC_REG_POWER_STATUS_MASK].value = 0xFF;
+	tcpci_regs[TCPC_REG_FAULT_STATUS_MASK].value = 0xFF;
+	tcpci_regs[TCPC_REG_EXT_STATUS_MASK].value = 0x01;
+	tcpci_regs[TCPC_REG_ALERT_EXTENDED_MASK].value = 0x07;
 }
 
 static void tcpci_reset_register_defaults(void)
@@ -427,69 +411,68 @@ static void tcpci_reset_register_defaults(void)
 		tcpci_regs[i].value = 0;
 
 	/* Type-C Release 1,3 */
-	tcpci_regs[TCPC_REG_TC_REV].value =			0x0013;
+	tcpci_regs[TCPC_REG_TC_REV].value = 0x0013;
 	/* PD Revision 3.0 Version 1.2 */
-	tcpci_regs[TCPC_REG_PD_REV].value =			0x3012;
+	tcpci_regs[TCPC_REG_PD_REV].value = 0x3012;
 	/* PD Interface Revision 2.0, Version 1.1 */
-	tcpci_regs[TCPC_REG_PD_INT_REV].value =			0x2011;
+	tcpci_regs[TCPC_REG_PD_INT_REV].value = 0x2011;
 
 	tcpci_reset_register_masks();
 
 	tcpci_regs[TCPC_REG_CONFIG_STD_OUTPUT].value =
-			TCPC_REG_CONFIG_STD_OUTPUT_AUDIO_CONN_N |
-			TCPC_REG_CONFIG_STD_OUTPUT_DBG_ACC_CONN_N;
+		TCPC_REG_CONFIG_STD_OUTPUT_AUDIO_CONN_N |
+		TCPC_REG_CONFIG_STD_OUTPUT_DBG_ACC_CONN_N;
 
 	tcpci_regs[TCPC_REG_POWER_CTRL].value =
-			TCPC_REG_POWER_CTRL_VOLT_ALARM_DIS |
-			TCPC_REG_POWER_CTRL_VBUS_VOL_MONITOR_DIS;
+		TCPC_REG_POWER_CTRL_VOLT_ALARM_DIS |
+		TCPC_REG_POWER_CTRL_VBUS_VOL_MONITOR_DIS;
 
 	tcpci_regs[TCPC_REG_FAULT_STATUS].value =
-			TCPC_REG_FAULT_STATUS_ALL_REGS_RESET;
+		TCPC_REG_FAULT_STATUS_ALL_REGS_RESET;
 
 	tcpci_regs[TCPC_REG_DEV_CAP_1].value =
-			TCPC_REG_DEV_CAP_1_SOURCE_VBUS |
-			TCPC_REG_DEV_CAP_1_SINK_VBUS |
-			TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP |
-			TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_3P0_1P5_DEF;
+		TCPC_REG_DEV_CAP_1_SOURCE_VBUS | TCPC_REG_DEV_CAP_1_SINK_VBUS |
+		TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP |
+		TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_3P0_1P5_DEF;
 
 	/*
 	 * Using table 4-17 to get the default Role Control and
 	 * Message Header Info register values.
 	 */
 	switch (mock_tcpci_get_reg(TCPC_REG_DEV_CAP_1) &
-			TCPC_REG_DEV_CAP_1_PWRROLE_MASK) {
+		TCPC_REG_DEV_CAP_1_PWRROLE_MASK) {
 	case TCPC_REG_DEV_CAP_1_PWRROLE_SRC_OR_SNK:
 	case TCPC_REG_DEV_CAP_1_PWRROLE_SNK:
 	case TCPC_REG_DEV_CAP_1_PWRROLE_SNK_ACC:
-		tcpci_regs[TCPC_REG_ROLE_CTRL].value =		0x0A;
-		tcpci_regs[TCPC_REG_MSG_HDR_INFO].value =	0x04;
+		tcpci_regs[TCPC_REG_ROLE_CTRL].value = 0x0A;
+		tcpci_regs[TCPC_REG_MSG_HDR_INFO].value = 0x04;
 		break;
 
 	case TCPC_REG_DEV_CAP_1_PWRROLE_DRP:
 		if (dead_battery())
-			tcpci_regs[TCPC_REG_ROLE_CTRL].value =	0x0A;
+			tcpci_regs[TCPC_REG_ROLE_CTRL].value = 0x0A;
 		else if (debug_accessory_indicator_supported())
-			tcpci_regs[TCPC_REG_ROLE_CTRL].value =	0x4A;
+			tcpci_regs[TCPC_REG_ROLE_CTRL].value = 0x4A;
 		else
-			tcpci_regs[TCPC_REG_ROLE_CTRL].value =	0x0F;
-		tcpci_regs[TCPC_REG_MSG_HDR_INFO].value =	0x04;
+			tcpci_regs[TCPC_REG_ROLE_CTRL].value = 0x0F;
+		tcpci_regs[TCPC_REG_MSG_HDR_INFO].value = 0x04;
 		break;
 
 	case TCPC_REG_DEV_CAP_1_PWRROLE_SRC:
 		if (!dead_battery())
-			tcpci_regs[TCPC_REG_ROLE_CTRL].value =	0x05;
-		tcpci_regs[TCPC_REG_MSG_HDR_INFO].value =	0x0D;
+			tcpci_regs[TCPC_REG_ROLE_CTRL].value = 0x05;
+		tcpci_regs[TCPC_REG_MSG_HDR_INFO].value = 0x0D;
 		break;
 
 	case TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP_ADPT_CBL:
 	case TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP:
 		if (dead_battery())
-			tcpci_regs[TCPC_REG_ROLE_CTRL].value =	0x0A;
+			tcpci_regs[TCPC_REG_ROLE_CTRL].value = 0x0A;
 		else if (debug_accessory_indicator_supported())
-			tcpci_regs[TCPC_REG_ROLE_CTRL].value =	0x4A;
+			tcpci_regs[TCPC_REG_ROLE_CTRL].value = 0x4A;
 		else
-			tcpci_regs[TCPC_REG_ROLE_CTRL].value =	0x0F;
-		tcpci_regs[TCPC_REG_MSG_HDR_INFO].value =	0x04;
+			tcpci_regs[TCPC_REG_ROLE_CTRL].value = 0x0F;
+		tcpci_regs[TCPC_REG_MSG_HDR_INFO].value = 0x04;
 		break;
 	}
 }
@@ -505,7 +488,7 @@ void mock_tcpci_set_reg(int reg_offset, uint16_t value)
 	struct tcpci_reg *reg = tcpci_regs + reg_offset;
 
 	reg->value = value;
-	ccprints("TCPCI mock set %s = 0x%x",  reg->name, reg->value);
+	ccprints("TCPCI mock set %s = 0x%x", reg->name, reg->value);
 }
 
 void mock_tcpci_set_reg_bits(int reg_offset, uint16_t mask)
@@ -514,8 +497,8 @@ void mock_tcpci_set_reg_bits(int reg_offset, uint16_t mask)
 	uint16_t old_value = reg->value;
 
 	reg->value |= mask;
-	ccprints("TCPCI mock set bits %s (mask=0x%x) = 0x%x -> 0x%x",
-		 reg->name, mask, old_value, reg->value);
+	ccprints("TCPCI mock set bits %s (mask=0x%x) = 0x%x -> 0x%x", reg->name,
+		 mask, old_value, reg->value);
 }
 
 void mock_tcpci_clr_reg_bits(int reg_offset, uint16_t mask)
@@ -524,8 +507,8 @@ void mock_tcpci_clr_reg_bits(int reg_offset, uint16_t mask)
 	uint16_t old_value = reg->value;
 
 	reg->value &= ~mask;
-	ccprints("TCPCI mock clr bits %s (mask=0x%x) = 0x%x -> 0x%x",
-		 reg->name, mask, old_value, reg->value);
+	ccprints("TCPCI mock clr bits %s (mask=0x%x) = 0x%x -> 0x%x", reg->name,
+		 mask, old_value, reg->value);
 }
 
 uint16_t mock_tcpci_get_reg(int reg_offset)
@@ -533,9 +516,8 @@ uint16_t mock_tcpci_get_reg(int reg_offset)
 	return tcpci_regs[reg_offset].value;
 }
 
-int tcpci_i2c_xfer(int port, uint16_t addr_flags,
-		const uint8_t *out, int out_size,
-		uint8_t *in, int in_size, int flags)
+int tcpci_i2c_xfer(int port, uint16_t addr_flags, const uint8_t *out,
+		   int out_size, uint8_t *in, int in_size, int flags)
 {
 	struct tcpci_reg *reg;
 
@@ -554,10 +536,10 @@ int tcpci_i2c_xfer(int port, uint16_t addr_flags,
 			return EC_ERROR_UNKNOWN;
 		}
 		memcpy(in, rx_buffer + rx_pos, in_size);
-		rx_pos	+= in_size;
+		rx_pos += in_size;
 		if (rx_pos == rx_buffer[0] + 1) {
-			print_header("RX", UINT16_FROM_BYTE_ARRAY_LE(
-						rx_buffer, 2));
+			print_header("RX",
+				     UINT16_FROM_BYTE_ARRAY_LE(rx_buffer, 2));
 			rx_pos = -1;
 		}
 		return EC_SUCCESS;
@@ -576,8 +558,8 @@ int tcpci_i2c_xfer(int port, uint16_t addr_flags,
 		tx_pos += out_size;
 		tx_msg_cnt = tx_pos;
 		if (tx_pos > 0 && tx_pos == tx_buffer[0] + 1) {
-			print_header("TX", UINT16_FROM_BYTE_ARRAY_LE(
-						tx_buffer, 1));
+			print_header("TX",
+				     UINT16_FROM_BYTE_ARRAY_LE(tx_buffer, 1));
 			tx_pos = -1;
 			tx_retry_cnt = -1;
 		}
@@ -638,8 +620,7 @@ int tcpci_i2c_xfer(int port, uint16_t addr_flags,
 		else if (reg->size == 2)
 			value = out[1] + (out[2] << 8);
 		ccprints("%s TCPCI write %s = 0x%x",
-			 task_get_name(task_get_current()),
-			 reg->name, value);
+			 task_get_name(task_get_current()), reg->name, value);
 		if (reg->offset == TCPC_REG_ALERT)
 			reg->value &= ~value;
 		else
diff --git a/common/mock/tcpm_mock.c b/common/mock/tcpm_mock.c
index 2c212cf8c9..a54b31839b 100644
--- a/common/mock/tcpm_mock.c
+++ b/common/mock/tcpm_mock.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -31,7 +31,7 @@ int tcpm_dequeue_message(int port, uint32_t *payload, int *header)
 
 	*header = mock_tcpm[port].mock_header;
 	memcpy(payload, mock_tcpm[port].mock_rx_chk_buf,
-		sizeof(mock_tcpm[port].mock_rx_chk_buf));
+	       sizeof(mock_tcpm[port].mock_rx_chk_buf));
 
 	return EC_SUCCESS;
 }
@@ -51,7 +51,7 @@ void mock_tcpm_reset(void)
 {
 	int port;
 
-	for (port = 0 ; port < CONFIG_USB_PD_PORT_MAX_COUNT ; ++port)
+	for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
 		mock_tcpm[port].mock_has_pending_message = 0;
 }
 
@@ -65,7 +65,7 @@ void mock_tcpm_rx_msg(int port, uint16_t header, int cnt, const uint32_t *data)
 	if (cnt > 0) {
 		int idx;
 
-		for (idx = 0 ; (idx < cnt) && (idx < MOCK_CHK_BUF_SIZE) ; ++idx)
+		for (idx = 0; (idx < cnt) && (idx < MOCK_CHK_BUF_SIZE); ++idx)
 			mock_tcpm[port].mock_rx_chk_buf[idx] = data[idx];
 	}
 	mock_tcpm[port].mock_has_pending_message = 1;
diff --git a/common/mock/timer_mock.c b/common/mock/timer_mock.c
index dc83aa24d5..0504578412 100644
--- a/common/mock/timer_mock.c
+++ b/common/mock/timer_mock.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/common/mock/usb_mux_mock.c b/common/mock/usb_mux_mock.c
index f2db5cf8bd..815cdf777c 100644
--- a/common/mock/usb_mux_mock.c
+++ b/common/mock/usb_mux_mock.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/common/mock/usb_pd_dpm_mock.c b/common/mock/usb_pd_dpm_mock.c
index 005e0090a6..158c53c650 100644
--- a/common/mock/usb_pd_dpm_mock.c
+++ b/common/mock/usb_pd_dpm_mock.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -36,12 +36,12 @@ void dpm_mode_exit_complete(int port)
 }
 
 void dpm_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count,
-		uint32_t *vdm)
+		   uint32_t *vdm)
 {
 }
 
 void dpm_vdm_naked(int port, enum tcpci_msg_type type, uint16_t svid,
-		uint8_t vdm_cmd)
+		   uint8_t vdm_cmd)
 {
 }
 
@@ -73,6 +73,14 @@ void dpm_remove_source(int port)
 {
 }
 
+void dpm_bist_shared_mode_enter(int port)
+{
+}
+
+void dpm_bist_shared_mode_exit(int port)
+{
+}
+
 int dpm_get_source_pdo(const uint32_t **src_pdo, const int port)
 {
 	*src_pdo = pd_src_pdo;
@@ -83,3 +91,7 @@ int dpm_get_status_msg(int port, uint8_t *msg, uint32_t *len)
 {
 	return EC_SUCCESS;
 }
+
+void dpm_handle_alert(int port, uint32_t ado)
+{
+}
diff --git a/common/mock/usb_pe_sm_mock.c b/common/mock/usb_pe_sm_mock.c
index 8d1a25324b..24861a73f9 100644
--- a/common/mock/usb_pe_sm_mock.c
+++ b/common/mock/usb_pe_sm_mock.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,7 +23,6 @@
 
 struct mock_pe_port_t mock_pe_port[CONFIG_USB_PD_PORT_MAX_COUNT];
 
-
 /**
  * Resets all mock PE ports to initial values
  */
@@ -31,7 +30,7 @@ void mock_pe_port_reset(void)
 {
 	int port;
 
-	for (port = 0 ; port < CONFIG_USB_PD_PORT_MAX_COUNT ; ++port) {
+	for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) {
 		mock_pe_port[port].mock_pe_error = -1;
 		/* These mock variable only get set to 1 by various functions,
 		 * so initialize them to 0. Tests can verify they are still 0
@@ -93,7 +92,7 @@ bool pe_in_local_ams(int port)
 	return false;
 }
 
-const uint32_t * const pd_get_src_caps(int port)
+const uint32_t *const pd_get_src_caps(int port)
 {
 	return NULL;
 }
@@ -108,7 +107,8 @@ void pd_set_src_caps(int port, int cnt, uint32_t *src_caps)
 }
 
 void pd_request_power_swap(int port)
-{}
+{
+}
 
 int pd_get_rev(int port, enum tcpci_msg_type type)
 {
diff --git a/common/mock/usb_prl_mock.c b/common/mock/usb_prl_mock.c
index d5f4781829..df61cfaf95 100644
--- a/common/mock/usb_prl_mock.c
+++ b/common/mock/usb_prl_mock.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -45,14 +45,15 @@ void mock_prl_reset(void)
 
 	memset(mock_prl_port, 0, sizeof(mock_prl_port));
 
-	for (port = 0 ; port < CONFIG_USB_PD_PORT_MAX_COUNT ; ++port) {
+	for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) {
 		mock_prl_port[port].last_tx_type = TCPCI_MSG_INVALID;
 		mock_prl_port[port].error_tx_type = TCPCI_MSG_INVALID;
 	}
 }
 
 void prl_end_ams(int port)
-{}
+{
+}
 
 void prl_execute_hard_reset(int port)
 {
@@ -67,7 +68,8 @@ enum pd_rev_type prl_get_rev(int port, enum tcpci_msg_type partner)
 }
 
 void prl_hard_reset_complete(int port)
-{}
+{
+}
 
 int prl_is_running(int port)
 {
@@ -80,10 +82,11 @@ __overridable bool prl_is_busy(int port)
 }
 
 void prl_reset_soft(int port)
-{}
+{
+}
 
 void prl_send_ctrl_msg(int port, enum tcpci_msg_type type,
-	enum pd_ctrl_msg_type msg)
+		       enum pd_ctrl_msg_type msg)
 {
 	mock_prl_port[port].last_ctrl_msg = msg;
 	mock_prl_port[port].last_data_msg = 0;
@@ -91,7 +94,7 @@ void prl_send_ctrl_msg(int port, enum tcpci_msg_type type,
 }
 
 void prl_send_data_msg(int port, enum tcpci_msg_type type,
-	enum pd_data_msg_type msg)
+		       enum pd_data_msg_type msg)
 {
 	mock_prl_port[port].last_data_msg = msg;
 	mock_prl_port[port].last_ctrl_msg = 0;
@@ -99,30 +102,28 @@ void prl_send_data_msg(int port, enum tcpci_msg_type type,
 }
 
 void prl_send_ext_data_msg(int port, enum tcpci_msg_type type,
-	enum pd_ext_msg_type msg)
-{}
-
-void prl_set_rev(int port, enum tcpci_msg_type partner,
-	enum pd_rev_type rev)
-{}
+			   enum pd_ext_msg_type msg)
+{
+}
 
+void prl_set_rev(int port, enum tcpci_msg_type partner, enum pd_rev_type rev)
+{
+}
 
-int mock_prl_wait_for_tx_msg(int port,
-			     enum tcpci_msg_type tx_type,
+int mock_prl_wait_for_tx_msg(int port, enum tcpci_msg_type tx_type,
 			     enum pd_ctrl_msg_type ctrl_msg,
-			     enum pd_data_msg_type data_msg,
-			     int timeout)
+			     enum pd_data_msg_type data_msg, int timeout)
 {
 	uint64_t end_time = get_time().val + timeout;
 
 	while (get_time().val < end_time) {
 		if (mock_prl_port[port].last_tx_type != TCPCI_MSG_INVALID) {
-			TEST_EQ(mock_prl_port[port].last_tx_type,
-				tx_type, "%d");
-			TEST_EQ(mock_prl_port[port].last_ctrl_msg,
-				ctrl_msg, "%d");
-			TEST_EQ(mock_prl_port[port].last_data_msg,
-				data_msg, "%d");
+			TEST_EQ(mock_prl_port[port].last_tx_type, tx_type,
+				"%d");
+			TEST_EQ(mock_prl_port[port].last_ctrl_msg, ctrl_msg,
+				"%d");
+			TEST_EQ(mock_prl_port[port].last_data_msg, data_msg,
+				"%d");
 			mock_prl_clear_last_sent_msg(port);
 			return EC_SUCCESS;
 		}
@@ -191,8 +192,7 @@ void prl_run(int port, int evt, int en)
 	}
 	if (mock_prl_port[port].error_tx_type != TCPCI_MSG_INVALID) {
 		ccprints("pe_error %d", mock_prl_port[port].error);
-		pe_report_error(port,
-				mock_prl_port[port].error,
+		pe_report_error(port, mock_prl_port[port].error,
 				mock_prl_port[port].error_tx_type);
 		mock_prl_port[port].error = 0;
 		mock_prl_port[port].error_tx_type = TCPCI_MSG_INVALID;
diff --git a/common/mock/usb_tc_sm_mock.c b/common/mock/usb_tc_sm_mock.c
index d55def12e2..5badc6eba6 100644
--- a/common/mock/usb_tc_sm_mock.c
+++ b/common/mock/usb_tc_sm_mock.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,7 +26,7 @@ void mock_tc_port_reset(void)
 {
 	int port;
 
-	for (port = 0 ; port < CONFIG_USB_PD_PORT_MAX_COUNT ; ++port) {
+	for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) {
 		mock_tc_port[port].rev = PD_REV30;
 		mock_tc_port[port].pd_enable = 0;
 		mock_tc_port[port].msg_tx_id = 0;
@@ -93,7 +93,8 @@ int tc_check_vconn_swap(int port)
 }
 
 void tc_ctvpd_detected(int port)
-{}
+{
+}
 
 int tc_is_vconn_src(int port)
 {
@@ -106,31 +107,40 @@ void tc_hard_reset_request(int port)
 }
 
 void tc_partner_dr_data(int port, int en)
-{}
+{
+}
 
 void tc_partner_dr_power(int port, int en)
-{}
+{
+}
 
 void tc_partner_unconstrainedpower(int port, int en)
-{}
+{
+}
 
 void tc_partner_usb_comm(int port, int en)
-{}
+{
+}
 
 void tc_pd_connection(int port, int en)
-{}
+{
+}
 
 void tc_pr_swap_complete(int port, bool success)
-{}
+{
+}
 
 void tc_src_power_off(int port)
-{}
+{
+}
 
 void tc_start_error_recovery(int port)
-{}
+{
+}
 
 void tc_snk_power_off(int port)
-{}
+{
+}
 
 void tc_request_power_swap(int port)
 {
@@ -200,13 +210,16 @@ enum tcpc_cc_polarity pd_get_polarity(int port)
 }
 
 void pd_request_data_swap(int port)
-{}
+{
+}
 
 void pd_request_vconn_swap_off(int port)
-{}
+{
+}
 
 void pd_request_vconn_swap_on(int port)
-{}
+{
+}
 
 bool pd_alt_mode_capable(int port)
 {
diff --git a/common/motion_lid.c b/common/motion_lid.c
index 4e76bebb66..1a254e786d 100644
--- a/common/motion_lid.c
+++ b/common/motion_lid.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,8 +26,8 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_MOTION_LID, outstr)
-#define CPRINTS(format, args...) cprints(CC_MOTION_LID, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_MOTION_LID, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_MOTION_LID, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_MOTION_LID, format, ##args)
 
 #ifdef CONFIG_TABLET_MODE
 /* Previous lid_angle. */
@@ -50,7 +50,7 @@ static int lid_angle_is_reliable;
 static intv3_t smoothed_base, smoothed_lid;
 
 /* 8.7 m/s^2 is the the maximum acceleration parallel to the hinge */
-#define SCALED_HINGE_VERTICAL_MAXIMUM  \
+#define SCALED_HINGE_VERTICAL_MAXIMUM \
 	((int)((8.7f * MOTION_SCALING_FACTOR) / MOTION_ONE_G))
 
 #define SCALED_HINGE_VERTICAL_SMOOTHING_START \
@@ -88,21 +88,21 @@ static intv3_t smoothed_base, smoothed_lid;
  * frame before calculating lid angle).
  */
 #ifdef CONFIG_ACCEL_STD_REF_FRAME_OLD
-static const intv3_t hinge_axis = { 0, 1, 0};
+static const intv3_t hinge_axis = { 0, 1, 0 };
 #define HINGE_AXIS Y
 #else
-static const intv3_t hinge_axis = { 1, 0, 0};
+static const intv3_t hinge_axis = { 1, 0, 0 };
 #define HINGE_AXIS X
 #endif
 
-static const struct motion_sensor_t * const accel_base =
+static const struct motion_sensor_t *const accel_base =
 	&motion_sensors[CONFIG_LID_ANGLE_SENSOR_BASE];
-static const struct motion_sensor_t * const accel_lid =
+static const struct motion_sensor_t *const accel_lid =
 	&motion_sensors[CONFIG_LID_ANGLE_SENSOR_LID];
 
 STATIC_IF(CONFIG_TABLET_MODE) void motion_lid_set_tablet_mode(int reliable);
-STATIC_IF(CONFIG_TABLET_MODE) int lid_angle_set_tablet_mode_threshold(
-		int angle, int hys);
+STATIC_IF(CONFIG_TABLET_MODE)
+int lid_angle_set_tablet_mode_threshold(int angle, int hys);
 
 STATIC_IF(CONFIG_TABLET_MODE) fp_t tablet_zone_lid_angle;
 STATIC_IF(CONFIG_TABLET_MODE) fp_t laptop_zone_lid_angle;
@@ -142,18 +142,16 @@ __attribute__((weak)) int board_is_lid_angle_tablet_mode(void)
  * by using MOTIONSENSE_CMD_TABLET_MODE_LID_ANGLE.
  */
 
-#define DEFAULT_TABLET_MODE_ANGLE	(180)
-#define DEFAULT_TABLET_MODE_HYS	(20)
+#define DEFAULT_TABLET_MODE_ANGLE (180)
+#define DEFAULT_TABLET_MODE_HYS (20)
 
-#define TABLET_ZONE_ANGLE(a, h)	((a) + (h))
-#define LAPTOP_ZONE_ANGLE(a, h)	((a) - (h))
+#define TABLET_ZONE_ANGLE(a, h) ((a) + (h))
+#define LAPTOP_ZONE_ANGLE(a, h) ((a) - (h))
 
-static fp_t tablet_zone_lid_angle =
-	FLOAT_TO_FP(TABLET_ZONE_ANGLE(DEFAULT_TABLET_MODE_ANGLE,
-				      DEFAULT_TABLET_MODE_HYS));
-static fp_t laptop_zone_lid_angle =
-	FLOAT_TO_FP(LAPTOP_ZONE_ANGLE(DEFAULT_TABLET_MODE_ANGLE,
-				      DEFAULT_TABLET_MODE_HYS));
+static fp_t tablet_zone_lid_angle = FLOAT_TO_FP(
+	TABLET_ZONE_ANGLE(DEFAULT_TABLET_MODE_ANGLE, DEFAULT_TABLET_MODE_HYS));
+static fp_t laptop_zone_lid_angle = FLOAT_TO_FP(
+	LAPTOP_ZONE_ANGLE(DEFAULT_TABLET_MODE_ANGLE, DEFAULT_TABLET_MODE_HYS));
 
 static int tablet_mode_lid_angle = DEFAULT_TABLET_MODE_ANGLE;
 static int tablet_mode_hys_degree = DEFAULT_TABLET_MODE_HYS;
@@ -220,8 +218,8 @@ static int lid_angle_set_tablet_mode_threshold(int angle, int hys)
 #define MOTION_LID_SET_DPTF_PROFILE
 #endif
 
-STATIC_IF(MOTION_LID_SET_DPTF_PROFILE) void motion_lid_set_dptf_profile(
-		int reliable);
+STATIC_IF(MOTION_LID_SET_DPTF_PROFILE)
+void motion_lid_set_dptf_profile(int reliable);
 
 #ifdef MOTION_LID_SET_DPTF_PROFILE
 /*
@@ -322,11 +320,11 @@ static int calculate_lid_angle(const intv3_t base, const intv3_t lid,
 	 * less than 1<<30.
 	 */
 	base_magnitude2 = scaled_base[X] * scaled_base[X] +
-		scaled_base[Y] * scaled_base[Y] +
-		scaled_base[Z] * scaled_base[Z];
+			  scaled_base[Y] * scaled_base[Y] +
+			  scaled_base[Z] * scaled_base[Z];
 	lid_magnitude2 = scaled_lid[X] * scaled_lid[X] +
-		scaled_lid[Y] * scaled_lid[Y] +
-		scaled_lid[Z] * scaled_lid[Z];
+			 scaled_lid[Y] * scaled_lid[Y] +
+			 scaled_lid[Z] * scaled_lid[Z];
 
 	/*
 	 * Check to see if they differ than more than NOISY_MAGNITUDE_DEVIATION.
@@ -358,14 +356,16 @@ static int calculate_lid_angle(const intv3_t base, const intv3_t lid,
 		goto end_calculate_lid_angle;
 	}
 
-	largest_hinge_accel = MAX(ABS(scaled_base[HINGE_AXIS]),
-				  ABS(scaled_lid[HINGE_AXIS]));
+	largest_hinge_accel =
+		MAX(ABS(scaled_base[HINGE_AXIS]), ABS(scaled_lid[HINGE_AXIS]));
 
-	smoothed_ratio = MAX(INT_TO_FP(0), MIN(INT_TO_FP(1),
-		fp_div(INT_TO_FP(largest_hinge_accel -
-				 SCALED_HINGE_VERTICAL_SMOOTHING_START),
-		       INT_TO_FP(SCALED_HINGE_VERTICAL_MAXIMUM -
-				 SCALED_HINGE_VERTICAL_SMOOTHING_START))));
+	smoothed_ratio = MAX(
+		INT_TO_FP(0),
+		MIN(INT_TO_FP(1),
+		    fp_div(INT_TO_FP(largest_hinge_accel -
+				     SCALED_HINGE_VERTICAL_SMOOTHING_START),
+			   INT_TO_FP(SCALED_HINGE_VERTICAL_MAXIMUM -
+				     SCALED_HINGE_VERTICAL_SMOOTHING_START))));
 
 	/* Check hinge is not too vertical */
 	if (largest_hinge_accel > SCALED_HINGE_VERTICAL_MAXIMUM) {
@@ -417,8 +417,7 @@ static int calculate_lid_angle(const intv3_t base, const intv3_t lid,
 
 #ifdef CONFIG_TABLET_MODE
 	/* Ignore large angles when the lid is closed. */
-	if (!lid_is_open() &&
-	    (lid_to_base_fp > SMALL_LID_ANGLE_RANGE)) {
+	if (!lid_is_open() && (lid_to_base_fp > SMALL_LID_ANGLE_RANGE)) {
 		reliable = 0;
 		goto end_calculate_lid_angle;
 	}
@@ -434,8 +433,7 @@ static int calculate_lid_angle(const intv3_t base, const intv3_t lid,
 	 * may wake us up.  This is because we require at least 4 consecutive
 	 * reliable readings over a threshold to disable key scanning.
 	 */
-	if (lid_is_open() &&
-	    (lid_to_base_fp <= SMALL_LID_ANGLE_RANGE)) {
+	if (lid_is_open() && (lid_to_base_fp <= SMALL_LID_ANGLE_RANGE)) {
 		reliable = 0;
 		goto end_calculate_lid_angle;
 	}
@@ -451,10 +449,8 @@ static int calculate_lid_angle(const intv3_t base, const intv3_t lid,
 	 * prove the small angle we see is correct so we take the angle
 	 * as is.
 	 */
-	if ((last_lid_angle_fp >=
-	     FLOAT_TO_FP(360) - DEBOUNCE_ANGLE_DELTA) &&
-	     (lid_to_base_fp <= DEBOUNCE_ANGLE_DELTA) &&
-	     (lid_is_open()))
+	if ((last_lid_angle_fp >= FLOAT_TO_FP(360) - DEBOUNCE_ANGLE_DELTA) &&
+	    (lid_to_base_fp <= DEBOUNCE_ANGLE_DELTA) && (lid_is_open()))
 		last_lid_angle_fp = FLOAT_TO_FP(360) - lid_to_base_fp;
 	else
 		last_lid_angle_fp = lid_to_base_fp;
@@ -471,7 +467,7 @@ end_calculate_lid_angle:
 
 	if (IS_ENABLED(MOTION_LID_SET_DPTF_PROFILE))
 		motion_lid_set_dptf_profile(reliable);
-#else    /* CONFIG_TABLET_MODE */
+#else /* CONFIG_TABLET_MODE */
 end_calculate_lid_angle:
 	if (reliable)
 		*lid_angle = FP_TO_INT(lid_to_base_fp + FLOAT_TO_FP(0.5));
@@ -494,8 +490,7 @@ void motion_lid_calc(void)
 {
 	/* Calculate angle of lid accel. */
 	lid_angle_is_reliable = calculate_lid_angle(
-			accel_base->xyz, accel_lid->xyz,
-			&lid_angle_deg);
+		accel_base->xyz, accel_lid->xyz, &lid_angle_deg);
 
 	if (IS_ENABLED(CONFIG_LID_ANGLE_UPDATE))
 		lid_angle_update(motion_lid_get_angle());
@@ -504,7 +499,6 @@ void motion_lid_calc(void)
 /*****************************************************************************/
 /* Host commands */
 
-
 enum ec_status host_cmd_motion_lid(struct host_cmd_handler_args *args)
 {
 	const struct ec_params_motion_sense *in = args->params;
@@ -519,7 +513,7 @@ enum ec_status host_cmd_motion_lid(struct host_cmd_handler_args *args)
 			 */
 			if (in->kb_wake_angle.data != EC_MOTION_SENSE_NO_VALUE)
 				lid_angle_set_wake_angle(
-						in->kb_wake_angle.data);
+					in->kb_wake_angle.data);
 
 			out->kb_wake_angle.ret = lid_angle_get_wake_angle();
 		} else {
@@ -542,8 +536,8 @@ enum ec_status host_cmd_motion_lid(struct host_cmd_handler_args *args)
 		if (IS_ENABLED(CONFIG_TABLET_MODE)) {
 			int ret;
 			ret = lid_angle_set_tablet_mode_threshold(
-					in->tablet_mode_threshold.lid_angle,
-					in->tablet_mode_threshold.hys_degree);
+				in->tablet_mode_threshold.lid_angle,
+				in->tablet_mode_threshold.hys_degree);
 
 			if (ret != EC_RES_SUCCESS)
 				return ret;
diff --git a/common/motion_orientation.c b/common/motion_orientation.c
index 9a20ff8499..1c52fe847e 100644
--- a/common/motion_orientation.c
+++ b/common/motion_orientation.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,9 +18,9 @@ static const intv3_t orientation_modes[] = {
 	[MOTIONSENSE_ORIENTATION_UPSIDE_DOWN_LANDSCAPE] = { 0, 1, 0 },
 };
 
-enum motionsensor_orientation motion_orientation_remap(
-		const struct motion_sensor_t *s,
-		enum motionsensor_orientation orientation)
+enum motionsensor_orientation
+motion_orientation_remap(const struct motion_sensor_t *s,
+			 enum motionsensor_orientation orientation)
 {
 	enum motionsensor_orientation rotated_orientation;
 	const intv3_t *orientation_v;
@@ -31,7 +31,8 @@ enum motionsensor_orientation motion_orientation_remap(
 
 	orientation_v = &orientation_modes[orientation];
 	rotate(*orientation_v, *s->rot_standard_ref, rotated_orientation_v);
-	rotated_orientation = ((2 * rotated_orientation_v[1] +
-			rotated_orientation_v[0] + 4) % 5);
+	rotated_orientation =
+		((2 * rotated_orientation_v[1] + rotated_orientation_v[0] + 4) %
+		 5);
 	return rotated_orientation;
 }
diff --git a/common/motion_sense.c b/common/motion_sense.c
index f61b8dfdf1..f326259497 100644
--- a/common/motion_sense.c
+++ b/common/motion_sense.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,6 +8,7 @@
 #include "accelgyro.h"
 #include "atomic.h"
 #include "body_detection.h"
+#include "builtin/assert.h"
 #include "chipset.h"
 #include "common.h"
 #include "console.h"
@@ -24,6 +25,7 @@
 #include "motion_lid.h"
 #include "motion_orientation.h"
 #include "online_calibration.h"
+#include "printf.h"
 #include "power.h"
 #include "queue.h"
 #include "tablet_mode.h"
@@ -33,9 +35,8 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_MOTION_SENSE, outstr)
-#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_MOTION_SENSE, format, ## args)
-
+#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_MOTION_SENSE, format, ##args)
 
 /* Delay between FIFO interruption. */
 static unsigned int ap_event_interval;
@@ -67,10 +68,10 @@ test_export_static enum chipset_state_mask sensor_active;
 test_export_static int wait_us;
 
 STATIC_IF(CONFIG_ACCEL_SPOOF_MODE) void print_spoof_mode_status(int id);
-STATIC_IF(CONFIG_GESTURE_DETECTION) void check_and_queue_gestures(
-		uint32_t *event);
-STATIC_IF(CONFIG_MOTION_FILL_LPC_SENSE_DATA) void update_sense_data(
-		uint8_t *lpc_status, int *psample_id);
+STATIC_IF(CONFIG_GESTURE_DETECTION)
+void check_and_queue_gestures(uint32_t *event);
+STATIC_IF(CONFIG_MOTION_FILL_LPC_SENSE_DATA)
+void update_sense_data(uint8_t *lpc_status, int *psample_id);
 
 /* Flags to control whether to send an ODR change event for a sensor */
 static atomic_t odr_event_required;
@@ -90,8 +91,8 @@ static int init_sensor_mutex(const struct device *dev)
 SYS_INIT(init_sensor_mutex, POST_KERNEL, 50);
 #endif /* CONFIG_ZEPHYR */
 
-static inline int motion_sensor_in_forced_mode(
-		const struct motion_sensor_t *sensor)
+static inline int
+motion_sensor_in_forced_mode(const struct motion_sensor_t *sensor)
 {
 #ifdef CONFIG_ACCEL_FORCE_MODE_MASK
 	/* Sensor not in force mode, its irq_handler is getting data. */
@@ -105,8 +106,9 @@ static inline int motion_sensor_in_forced_mode(
 }
 
 /* Minimal amount of time since last collection before triggering a new one */
-static inline int motion_sensor_time_to_read(const timestamp_t *ts,
-		const struct motion_sensor_t *sensor)
+static inline int
+motion_sensor_time_to_read(const timestamp_t *ts,
+			   const struct motion_sensor_t *sensor)
 {
 	if (sensor->collection_rate == 0)
 		return 0;
@@ -173,8 +175,8 @@ int motion_sense_set_data_rate(struct motion_sensor_t *sensor)
 			sensor->name, odr, roundup, config_id,
 			BASE_ODR(sensor->config[SENSOR_CONFIG_AP].odr));
 	else
-		CPRINTS("%c%d ODR %d rup %d cfg %d AP %d",
-			sensor->name[0], sensor->type, odr, roundup, config_id,
+		CPRINTS("%c%d ODR %d rup %d cfg %d AP %d", sensor->name[0],
+			sensor->type, odr, roundup, config_id,
 			BASE_ODR(sensor->config[SENSOR_CONFIG_AP].odr));
 
 	mutex_lock(&g_sensor_mutex);
@@ -195,6 +197,10 @@ int motion_sense_set_data_rate(struct motion_sensor_t *sensor)
 	sensor->collection_rate = odr > 0 ? SECOND * 1000 / odr : 0;
 	sensor->next_collection = ts.le.lo + sensor->collection_rate;
 	sensor->oversampling = 0;
+	if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
+		motion_sense_set_data_period(sensor - motion_sensors,
+					     sensor->collection_rate);
+	}
 	mutex_unlock(&g_sensor_mutex);
 	if (IS_ENABLED(CONFIG_BODY_DETECTION) &&
 	    (sensor - motion_sensors == CONFIG_BODY_DETECTION_SENSOR))
@@ -203,9 +209,9 @@ int motion_sense_set_data_rate(struct motion_sensor_t *sensor)
 	return 0;
 }
 
-static int motion_sense_set_ec_rate_from_ap(
-		const struct motion_sensor_t *sensor,
-		unsigned int new_rate_us)
+static int
+motion_sense_set_ec_rate_from_ap(const struct motion_sensor_t *sensor,
+				 unsigned int new_rate_us)
 {
 	int odr_mhz = sensor->drv->get_data_rate(sensor);
 
@@ -238,7 +244,6 @@ end_set_ec_rate_from_ap:
 	return MAX(new_rate_us, motion_min_interval);
 }
 
-
 /*
  * motion_sense_select_ec_rate
  *
@@ -253,10 +258,9 @@ end_set_ec_rate_from_ap:
  *
  * return rate in us.
  */
-static int motion_sense_select_ec_rate(
-		const struct motion_sensor_t *sensor,
-		enum sensor_config config_id,
-		int interrupt)
+static int motion_sense_select_ec_rate(const struct motion_sensor_t *sensor,
+				       enum sensor_config config_id,
+				       int interrupt)
 {
 	if (interrupt == 0 && motion_sensor_in_forced_mode(sensor)) {
 		int rate_mhz = BASE_ODR(sensor->config[config_id].odr);
@@ -283,11 +287,11 @@ static int motion_sense_ec_rate(struct motion_sensor_t *sensor)
 
 	/* Check the AP setting first. */
 	if (sensor_active != SENSOR_ACTIVE_S5)
-		ec_rate = motion_sense_select_ec_rate(
-			sensor, SENSOR_CONFIG_AP, 0);
+		ec_rate = motion_sense_select_ec_rate(sensor, SENSOR_CONFIG_AP,
+						      0);
 
 	ec_rate_from_cfg = motion_sense_select_ec_rate(
-			sensor, motion_sense_get_ec_config(), 0);
+		sensor, motion_sense_get_ec_config(), 0);
 
 	if (ec_rate_from_cfg != 0)
 		if (ec_rate == 0 || ec_rate_from_cfg < ec_rate)
@@ -315,7 +319,7 @@ static void motion_sense_set_motion_intervals(void)
 			continue;
 
 		sensor_ec_rate = motion_sense_select_ec_rate(
-				sensor, SENSOR_CONFIG_AP, 1);
+			sensor, SENSOR_CONFIG_AP, 1);
 		if (ec_int_rate == 0 ||
 		    (sensor_ec_rate && sensor_ec_rate < ec_int_rate))
 			ec_int_rate = sensor_ec_rate;
@@ -365,8 +369,8 @@ int sensor_init_done(struct motion_sensor_t *s)
 				!!(s->current_range & ROUND_UP_FLAG));
 	if (ret == EC_RES_SUCCESS) {
 		if (IS_ENABLED(CONFIG_CONSOLE_VERBOSE))
-			CPRINTS("%s: MS Done Init type:0x%X range:%d",
-				s->name, s->type, s->current_range);
+			CPRINTS("%s: MS Done Init type:0x%X range:%d", s->name,
+				s->type, s->current_range);
 		else
 			CPRINTS("%c%d InitDone r:%d", s->name[0], s->type,
 				s->current_range);
@@ -396,15 +400,14 @@ static void motion_sense_switch_sensor_rate(void)
 			 * set.
 			 */
 			if (sensor->state == SENSOR_INITIALIZED) {
-				sensor->drv->set_range(sensor,
-						       sensor->current_range,
-						       1);
+				sensor->drv->set_range(
+					sensor, sensor->current_range, 1);
 				sensor_setup_mask |= BIT(i);
 			} else {
 				ret = motion_sense_init(sensor);
 				if (ret != EC_SUCCESS)
 					CPRINTS("%s: %d: init failed: %d",
-							sensor->name, i, ret);
+						sensor->name, i, ret);
 				else
 					sensor_setup_mask |= BIT(i);
 				/*
@@ -468,19 +471,20 @@ static void motion_sense_switch_sensor_rate(void)
 			sensor = &motion_sensors[i];
 			if (sensor->state != SENSOR_INITIALIZED)
 				continue;
-			sensor->drv->list_activities(sensor,
-					&enabled, &disabled);
+			sensor->drv->list_activities(sensor, &enabled,
+						     &disabled);
 			/* exclude double tap, it is used internally. */
 			enabled &= ~BIT(MOTIONSENSE_ACTIVITY_DOUBLE_TAP);
 			while (enabled) {
 				int activity = get_next_bit(&enabled);
 
-				sensor->drv->manage_activity(
-						sensor, activity, 0, NULL);
+				sensor->drv->manage_activity(sensor, activity,
+							     0, NULL);
 			}
 			/* Re-enable double tap in case AP disabled it */
-			sensor->drv->manage_activity(sensor,
-				MOTIONSENSE_ACTIVITY_DOUBLE_TAP, 1, NULL);
+			sensor->drv->manage_activity(
+				sensor, MOTIONSENSE_ACTIVITY_DOUBLE_TAP, 1,
+				NULL);
 		}
 	}
 }
@@ -544,8 +548,7 @@ static void motion_sense_resume(void)
 	hook_call_deferred(&motion_sense_switch_sensor_rate_data,
 			   CONFIG_MOTION_SENSE_RESUME_DELAY_US);
 }
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, motion_sense_resume,
-	     MOTION_SENSE_HOOK_PRIO);
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, motion_sense_resume, MOTION_SENSE_HOOK_PRIO);
 
 static void motion_sense_startup(void)
 {
@@ -561,8 +564,7 @@ static void motion_sense_startup(void)
 	if (chipset_in_state(SENSOR_ACTIVE_S0))
 		motion_sense_resume();
 }
-DECLARE_HOOK(HOOK_INIT, motion_sense_startup,
-	     MOTION_SENSE_HOOK_PRIO);
+DECLARE_HOOK(HOOK_INIT, motion_sense_startup, MOTION_SENSE_HOOK_PRIO);
 
 /* Write to LPC status byte to represent that accelerometers are present. */
 static inline void set_present(uint8_t *lpc_status)
@@ -620,15 +622,14 @@ static void update_sense_data(uint8_t *lpc_status, int *psample_id)
 
 		for (i = 0; i < EC_ALS_ENTRIES && i < ALS_COUNT; i++)
 			lpc_als[i] = ec_motion_sensor_clamp_u16(
-					motion_als_sensors[i]->xyz[X]);
+				motion_als_sensors[i]->xyz[X]);
 	}
 
 	/*
 	 * Increment sample id and clear busy bit to signal we finished
 	 * updating data.
 	 */
-	*psample_id = (*psample_id + 1) &
-			EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK;
+	*psample_id = (*psample_id + 1) & EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK;
 	*lpc_status = EC_MEMMAP_ACC_STATUS_PRESENCE_BIT | *psample_id;
 }
 #endif
@@ -650,7 +651,6 @@ static int motion_sense_read(struct motion_sensor_t *sensor)
 	return sensor->drv->read(sensor, sensor->raw_xyz);
 }
 
-
 static inline void increment_sensor_collection(struct motion_sensor_t *sensor,
 					       const timestamp_t *ts)
 {
@@ -708,8 +708,7 @@ void motion_sense_push_raw_xyz(struct motion_sensor_t *s)
 	}
 }
 
-static int motion_sense_process(struct motion_sensor_t *sensor,
-				uint32_t *event,
+static int motion_sense_process(struct motion_sensor_t *sensor, uint32_t *event,
 				const timestamp_t *ts)
 {
 	int ret = EC_SUCCESS;
@@ -758,8 +757,8 @@ static int motion_sense_process(struct motion_sensor_t *sensor,
 		int flush_pending = atomic_clear(&sensor->flush_pending);
 
 		for (; flush_pending > 0; flush_pending--) {
-			motion_sense_fifo_insert_async_event(
-				sensor, ASYNC_EVENT_FLUSH);
+			motion_sense_fifo_insert_async_event(sensor,
+							     ASYNC_EVENT_FLUSH);
 		}
 	}
 
@@ -768,8 +767,8 @@ static int motion_sense_process(struct motion_sensor_t *sensor,
 		motion_sense_set_data_rate(sensor);
 		motion_sense_set_motion_intervals();
 		if (IS_ENABLED(CONFIG_ACCEL_FIFO))
-			motion_sense_fifo_insert_async_event(
-				sensor, ASYNC_EVENT_ODR);
+			motion_sense_fifo_insert_async_event(sensor,
+							     ASYNC_EVENT_ODR);
 	}
 	if (has_data_read) {
 		/* Run gesture recognition engine */
@@ -783,13 +782,12 @@ static int motion_sense_process(struct motion_sensor_t *sensor,
 	return ret;
 }
 
-
 #ifdef CONFIG_GESTURE_DETECTION
 static void check_and_queue_gestures(uint32_t *event)
 {
 	if (IS_ENABLED(CONFIG_GESTURE_SENSOR_DOUBLE_TAP) &&
 	    (*event & TASK_EVENT_MOTION_ACTIVITY_INTERRUPT(
-				MOTIONSENSE_ACTIVITY_DOUBLE_TAP))) {
+			      MOTIONSENSE_ACTIVITY_DOUBLE_TAP))) {
 		if (IS_ENABLED(CONFIG_GESTURE_HOST_DETECTION)) {
 			struct ec_response_motion_sensor_data vector;
 
@@ -799,14 +797,15 @@ static void check_and_queue_gestures(uint32_t *event)
 			 * AP is ignoring double tap event, do no wake up and no
 			 * automatic disable.
 			 */
-			if (IS_ENABLED(CONFIG_GESTURE_SENSOR_DOUBLE_TAP_FOR_HOST))
+			if (IS_ENABLED(
+				    CONFIG_GESTURE_SENSOR_DOUBLE_TAP_FOR_HOST))
 				vector.flags |= MOTIONSENSE_SENSOR_FLAG_WAKEUP;
 			vector.activity_data.activity =
-					MOTIONSENSE_ACTIVITY_DOUBLE_TAP;
+				MOTIONSENSE_ACTIVITY_DOUBLE_TAP;
 			vector.activity_data.state = 1 /* triggered */;
 			vector.sensor_num = MOTION_SENSE_ACTIVITY_SENSOR_ID;
 			motion_sense_fifo_stage_data(&vector, NULL, 0,
-					__hw_clock_source_read());
+						     __hw_clock_source_read());
 			motion_sense_fifo_commit_data();
 		}
 		/* Call board specific function to process tap */
@@ -814,7 +813,7 @@ static void check_and_queue_gestures(uint32_t *event)
 	}
 	if (IS_ENABLED(CONFIG_GESTURE_SIGMO) &&
 	    (*event & TASK_EVENT_MOTION_ACTIVITY_INTERRUPT(
-			MOTIONSENSE_ACTIVITY_SIG_MOTION))) {
+			      MOTIONSENSE_ACTIVITY_SIG_MOTION))) {
 		struct motion_sensor_t *activity_sensor;
 		if (IS_ENABLED(CONFIG_GESTURE_HOST_DETECTION)) {
 			struct ec_response_motion_sensor_data vector;
@@ -823,19 +822,18 @@ static void check_and_queue_gestures(uint32_t *event)
 			vector.flags = MOTIONSENSE_SENSOR_FLAG_WAKEUP |
 				       MOTIONSENSE_SENSOR_FLAG_BYPASS_FIFO;
 			vector.activity_data.activity =
-					MOTIONSENSE_ACTIVITY_SIG_MOTION;
+				MOTIONSENSE_ACTIVITY_SIG_MOTION;
 			vector.activity_data.state = 1 /* triggered */;
 			vector.sensor_num = MOTION_SENSE_ACTIVITY_SENSOR_ID;
 			motion_sense_fifo_stage_data(&vector, NULL, 0,
-					__hw_clock_source_read());
+						     __hw_clock_source_read());
 			motion_sense_fifo_commit_data();
 		}
 		/* Disable further detection */
 		activity_sensor = &motion_sensors[CONFIG_GESTURE_SIGMO_SENSOR];
 		activity_sensor->drv->manage_activity(
-				activity_sensor,
-				MOTIONSENSE_ACTIVITY_SIG_MOTION,
-				0, NULL);
+			activity_sensor, MOTIONSENSE_ACTIVITY_SIG_MOTION, 0,
+			NULL);
 	}
 	if (IS_ENABLED(CONFIG_ORIENTATION_SENSOR)) {
 		const struct motion_sensor_t *sensor =
@@ -852,24 +850,22 @@ static void check_and_queue_gestures(uint32_t *event)
 
 			mutex_lock(sensor->mutex);
 			if (motion_orientation_changed(sensor) &&
-					(*motion_orientation_ptr(sensor) !=
-					 MOTIONSENSE_ORIENTATION_UNKNOWN)) {
+			    (*motion_orientation_ptr(sensor) !=
+			     MOTIONSENSE_ORIENTATION_UNKNOWN)) {
 				motion_orientation_update(sensor);
 				vector.activity_data.state =
 					*motion_orientation_ptr(sensor);
-				motion_sense_fifo_stage_data(&vector, NULL, 0,
-						__hw_clock_source_read());
+				motion_sense_fifo_stage_data(
+					&vector, NULL, 0,
+					__hw_clock_source_read());
 				motion_sense_fifo_commit_data();
 				if (IS_ENABLED(CONFIG_DEBUG_ORIENTATION)) {
-					static const char * const mode[] = {
-						"Landscape",
-						"Portrait",
-						"Inv_Portrait",
-						"Inv_Landscape",
+					static const char *const mode[] = {
+						"Landscape", "Portrait",
+						"Inv_Portrait", "Inv_Landscape",
 						"Unknown"
 					};
-					CPRINTS(mode[
-						vector.activity_data.state]);
+					CPRINTS(mode[vector.activity_data.state]);
 				}
 			}
 			mutex_unlock(sensor->mutex);
@@ -910,7 +906,6 @@ void motion_sense_task(void *u)
 	while (1) {
 		ts_begin_task = get_time();
 		for (i = 0; i < motion_sensor_count; ++i) {
-
 			sensor = &motion_sensors[i];
 
 			/* if the sensor is active in the current power state */
@@ -920,7 +915,7 @@ void motion_sense_task(void *u)
 				}
 
 				ret = motion_sense_process(sensor, &event,
-						&ts_begin_task);
+							   &ts_begin_task);
 				if (ret != EC_SUCCESS)
 					continue;
 				ready_status |= BIT(i);
@@ -944,13 +939,14 @@ void motion_sense_task(void *u)
 			}
 		}
 		if (IS_ENABLED(CONFIG_CMD_ACCEL_INFO) && (accel_disp)) {
-			CPRINTF("[%pT event 0x%08x ",
-				PRINTF_TIMESTAMP_NOW, event);
+			char ts_str[PRINTF_TIMESTAMP_BUF_SIZE];
+
+			snprintf_timestamp_now(ts_str, sizeof(ts_str));
+			CPRINTF("[%s event 0x%08x ", ts_str, event);
 			for (i = 0; i < motion_sensor_count; ++i) {
 				sensor = &motion_sensors[i];
 				CPRINTF("%s=%-5d, %-5d, %-5d ", sensor->name,
-					sensor->xyz[X],
-					sensor->xyz[Y],
+					sensor->xyz[X], sensor->xyz[Y],
 					sensor->xyz[Z]);
 			}
 			if (IS_ENABLED(CONFIG_LID_ANGLE))
@@ -986,9 +982,9 @@ void motion_sense_task(void *u)
 			 * will resume listening until it is suspended again.
 			 */
 			if ((IS_ENABLED(CONFIG_MKBP_EVENT) &&
-			    ((fifo_int_enabled &&
-			      sensor_active == SENSOR_ACTIVE_S0) ||
-			     motion_sense_fifo_wake_up_needed()))) {
+			     ((fifo_int_enabled &&
+			       sensor_active == SENSOR_ACTIVE_S0) ||
+			      motion_sense_fifo_wake_up_needed()))) {
 				mkbp_send_event(EC_MKBP_EVENT_SENSOR_FIFO);
 			}
 			if (motion_sense_fifo_bypass_needed())
@@ -1003,7 +999,7 @@ void motion_sense_task(void *u)
 			struct motion_sensor_t *sensor = &motion_sensors[i];
 
 			if (!motion_sensor_in_forced_mode(sensor) ||
-			   sensor->collection_rate == 0)
+			    sensor->collection_rate == 0)
 				continue;
 
 			time_diff = time_until(ts_end_task.le.lo,
@@ -1021,9 +1017,9 @@ void motion_sense_task(void *u)
 
 		if (wait_us >= 0 && wait_us < motion_min_interval) {
 			/*
-			* Guarantee some minimum delay to allow other lower
-			* priority tasks to run.
-			*/
+			 * Guarantee some minimum delay to allow other lower
+			 * priority tasks to run.
+			 */
 			wait_us = motion_min_interval;
 		}
 
@@ -1035,8 +1031,7 @@ void motion_sense_task(void *u)
 /* Host commands */
 
 /* Function to map host sensor IDs to motion sensor. */
-static struct motion_sensor_t
-	*host_sensor_id_to_real_sensor(int host_id)
+static struct motion_sensor_t *host_sensor_id_to_real_sensor(int host_id)
 {
 	struct motion_sensor_t *sensor;
 
@@ -1052,8 +1047,7 @@ static struct motion_sensor_t
 	return NULL;
 }
 
-static struct motion_sensor_t
-	*host_sensor_id_to_motion_sensor(int host_id)
+static struct motion_sensor_t *host_sensor_id_to_motion_sensor(int host_id)
 {
 	/* Return the info for the first sensor that support some gestures. */
 	if (IS_ENABLED(CONFIG_GESTURE_HOST_DETECTION) &&
@@ -1081,7 +1075,8 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 		out->dump.module_flags =
 			(*(host_get_memmap(EC_MEMMAP_ACC_STATUS)) &
 			 EC_MEMMAP_ACC_STATUS_PRESENCE_BIT) ?
-			MOTIONSENSE_MODULE_FLAG_ACTIVE : 0;
+				MOTIONSENSE_MODULE_FLAG_ACTIVE :
+				0;
 		out->dump.sensor_count = ALL_MOTION_SENSORS;
 		args->response_size = sizeof(out->dump);
 		reported = MIN(ALL_MOTION_SENSORS, in->dump.max_sensor_count);
@@ -1099,13 +1094,14 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 			}
 		}
 		mutex_unlock(&g_sensor_mutex);
-		args->response_size += reported *
+		args->response_size +=
+			reported *
 			sizeof(struct ec_response_motion_sensor_data);
 		break;
 
 	case MOTIONSENSE_CMD_DATA:
 		sensor = host_sensor_id_to_real_sensor(
-				in->sensor_odr.sensor_num);
+			in->sensor_odr.sensor_num);
 		if (sensor == NULL)
 			return EC_RES_INVALID_PARAM;
 
@@ -1120,7 +1116,7 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 
 	case MOTIONSENSE_CMD_INFO:
 		sensor = host_sensor_id_to_motion_sensor(
-				in->sensor_odr.sensor_num);
+			in->sensor_odr.sensor_num);
 		if (sensor == NULL)
 			return EC_RES_INVALID_PARAM;
 
@@ -1139,7 +1135,8 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 		if (args->version >= 3) {
 			out->info_3.min_frequency = sensor->min_frequency;
 			out->info_3.max_frequency = sensor->max_frequency;
-			out->info_3.fifo_max_event_count = CONFIG_ACCEL_FIFO_SIZE;
+			out->info_3.fifo_max_event_count =
+				CONFIG_ACCEL_FIFO_SIZE;
 			args->response_size = sizeof(out->info_3);
 		}
 		if (args->version >= 4) {
@@ -1152,8 +1149,7 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 		break;
 
 	case MOTIONSENSE_CMD_EC_RATE:
-		sensor = host_sensor_id_to_real_sensor(
-				in->ec_rate.sensor_num);
+		sensor = host_sensor_id_to_real_sensor(in->ec_rate.sensor_num);
 		if (sensor == NULL)
 			return EC_RES_INVALID_PARAM;
 
@@ -1181,7 +1177,7 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 	case MOTIONSENSE_CMD_SENSOR_ODR:
 		/* Verify sensor number is valid. */
 		sensor = host_sensor_id_to_real_sensor(
-				in->sensor_odr.sensor_num);
+			in->sensor_odr.sensor_num);
 		if (sensor == NULL)
 			return EC_RES_INVALID_PARAM;
 
@@ -1210,7 +1206,7 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 	case MOTIONSENSE_CMD_SENSOR_RANGE:
 		/* Verify sensor number is valid. */
 		sensor = host_sensor_id_to_real_sensor(
-				in->sensor_range.sensor_num);
+			in->sensor_range.sensor_num);
 		if (sensor == NULL)
 			return EC_RES_INVALID_PARAM;
 		/* Set new range if the data arg has a value. */
@@ -1218,10 +1214,9 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 			if (!sensor->drv->set_range)
 				return EC_RES_INVALID_COMMAND;
 
-			if (sensor->drv->set_range(sensor,
-						   in->sensor_range.data,
-						   in->sensor_range.roundup)
-					!= EC_SUCCESS) {
+			if (sensor->drv->set_range(
+				    sensor, in->sensor_range.data,
+				    in->sensor_range.roundup) != EC_SUCCESS) {
 				return EC_RES_INVALID_PARAM;
 			}
 		}
@@ -1233,7 +1228,7 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 	case MOTIONSENSE_CMD_SENSOR_OFFSET:
 		/* Verify sensor number is valid. */
 		sensor = host_sensor_id_to_real_sensor(
-				in->sensor_offset.sensor_num);
+			in->sensor_offset.sensor_num);
 		if (sensor == NULL)
 			return EC_RES_INVALID_PARAM;
 		/* Set new range if the data arg has a value. */
@@ -1242,9 +1237,8 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 				return EC_RES_INVALID_COMMAND;
 
 			in_offset = in->sensor_offset.offset;
-			ret = sensor->drv->set_offset(sensor,
-						in_offset,
-						in->sensor_offset.temp);
+			ret = sensor->drv->set_offset(sensor, in_offset,
+						      in->sensor_offset.temp);
 			if (ret != EC_SUCCESS)
 				return ret;
 		}
@@ -1264,7 +1258,7 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 	case MOTIONSENSE_CMD_SENSOR_SCALE:
 		/* Verify sensor number is valid. */
 		sensor = host_sensor_id_to_real_sensor(
-				in->sensor_scale.sensor_num);
+			in->sensor_scale.sensor_num);
 		if (sensor == NULL)
 			return EC_RES_INVALID_PARAM;
 		/* Set new range if the data arg has a value. */
@@ -1273,8 +1267,7 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 				return EC_RES_INVALID_COMMAND;
 
 			in_scale = in->sensor_scale.scale;
-			ret = sensor->drv->set_scale(sensor,
-						     in_scale,
+			ret = sensor->drv->set_scale(sensor, in_scale,
 						     in->sensor_scale.temp);
 			if (ret != EC_SUCCESS)
 				return ret;
@@ -1284,8 +1277,7 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 			return EC_RES_INVALID_COMMAND;
 
 		out_scale = out->sensor_scale.scale;
-		ret = sensor->drv->get_scale(sensor, out_scale,
-				&out_temp);
+		ret = sensor->drv->get_scale(sensor, out_scale, &out_temp);
 		if (ret != EC_SUCCESS)
 			return ret;
 
@@ -1296,14 +1288,14 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 	case MOTIONSENSE_CMD_PERFORM_CALIB:
 		/* Verify sensor number is valid. */
 		sensor = host_sensor_id_to_real_sensor(
-				in->perform_calib.sensor_num);
+			in->perform_calib.sensor_num);
 		if (sensor == NULL)
 			return EC_RES_INVALID_PARAM;
 		if (!sensor->drv->perform_calib)
 			return EC_RES_INVALID_COMMAND;
 
-		ret = sensor->drv->perform_calib(
-				sensor, in->perform_calib.enable);
+		ret = sensor->drv->perform_calib(sensor,
+						 in->perform_calib.enable);
 		if (ret != EC_SUCCESS)
 			return ret;
 
@@ -1320,7 +1312,7 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 		if (!IS_ENABLED(CONFIG_ACCEL_FIFO))
 			return EC_RES_INVALID_PARAM;
 		sensor = host_sensor_id_to_real_sensor(
-				in->sensor_odr.sensor_num);
+			in->sensor_odr.sensor_num);
 		if (sensor == NULL)
 			return EC_RES_INVALID_PARAM;
 
@@ -1340,12 +1332,8 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 			break;
 		}
 		motion_sense_fifo_get_info(&out->fifo_info, 1);
-		for (i = 0; i < motion_sensor_count; i++) {
-			out->fifo_info.lost[i] = motion_sensors[i].lost;
-			motion_sensors[i].lost = 0;
-		}
 		args->response_size = sizeof(out->fifo_info) +
-			sizeof(uint16_t) * motion_sensor_count;
+				      sizeof(uint16_t) * motion_sensor_count;
 		break;
 
 	case MOTIONSENSE_CMD_FIFO_READ:
@@ -1353,8 +1341,7 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 			return EC_RES_INVALID_PARAM;
 		out->fifo_read.number_data = motion_sense_fifo_read(
 			args->response_max - sizeof(out->fifo_read),
-			in->fifo_read.max_data_vector,
-			out->fifo_read.data,
+			in->fifo_read.max_data_vector, out->fifo_read.data,
 			&(args->response_size));
 		args->response_size += sizeof(out->fifo_read);
 		break;
@@ -1384,9 +1371,9 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 
 		out_calib_read = &out->online_calib_read;
 		args->response_size =
-			online_calibration_read(sensor, out_calib_read)
-			? sizeof(struct ec_response_online_calibration_data)
-			: 0;
+			online_calibration_read(sensor, out_calib_read) ?
+				sizeof(struct ec_response_online_calibration_data) :
+				0;
 		break;
 #ifdef CONFIG_GESTURE_HOST_DETECTION
 	case MOTIONSENSE_CMD_LIST_ACTIVITIES: {
@@ -1399,8 +1386,8 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 		while (mask && ret == EC_RES_SUCCESS) {
 			i = get_next_bit(&mask);
 			sensor = &motion_sensors[i];
-			ret = sensor->drv->list_activities(sensor,
-					&enabled, &disabled);
+			ret = sensor->drv->list_activities(sensor, &enabled,
+							   &disabled);
 			if (ret == EC_RES_SUCCESS) {
 				out->list_activities.enabled |= enabled;
 				out->list_activities.disabled |= disabled;
@@ -1408,11 +1395,11 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 		}
 		if (IS_ENABLED(CONFIG_BODY_DETECTION)) {
 			if (body_detect_get_enable()) {
-				out->list_activities.enabled |=
-				  BIT(MOTIONSENSE_ACTIVITY_BODY_DETECTION);
+				out->list_activities.enabled |= BIT(
+					MOTIONSENSE_ACTIVITY_BODY_DETECTION);
 			} else {
-				out->list_activities.disabled |=
-				  BIT(MOTIONSENSE_ACTIVITY_BODY_DETECTION);
+				out->list_activities.disabled |= BIT(
+					MOTIONSENSE_ACTIVITY_BODY_DETECTION);
 			}
 		}
 		if (ret != EC_RES_SUCCESS)
@@ -1428,18 +1415,18 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 		while (mask && ret == EC_RES_SUCCESS) {
 			i = get_next_bit(&mask);
 			sensor = &motion_sensors[i];
-			sensor->drv->list_activities(sensor,
-					&enabled, &disabled);
+			sensor->drv->list_activities(sensor, &enabled,
+						     &disabled);
 			if ((1 << in->set_activity.activity) &
 			    (enabled | disabled))
-				ret = sensor->drv->manage_activity(sensor,
-						in->set_activity.activity,
-						in->set_activity.enable,
-						&in->set_activity);
+				ret = sensor->drv->manage_activity(
+					sensor, in->set_activity.activity,
+					in->set_activity.enable,
+					&in->set_activity);
 		}
 		if (IS_ENABLED(CONFIG_BODY_DETECTION) &&
 		    (in->set_activity.activity ==
-		    MOTIONSENSE_ACTIVITY_BODY_DETECTION))
+		     MOTIONSENSE_ACTIVITY_BODY_DETECTION))
 			body_detect_set_enable(in->set_activity.enable);
 		if (ret != EC_RES_SUCCESS)
 			return ret;
@@ -1450,8 +1437,8 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 		if (IS_ENABLED(CONFIG_BODY_DETECTION) &&
 		    (in->get_activity.activity ==
 		     MOTIONSENSE_ACTIVITY_BODY_DETECTION)) {
-			out->get_activity.state = (uint8_t)
-					body_detect_get_state();
+			out->get_activity.state =
+				(uint8_t)body_detect_get_state();
 			ret = EC_RES_SUCCESS;
 		} else {
 			ret = EC_RES_INVALID_PARAM;
@@ -1549,7 +1536,7 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 		case MOTIONSENSE_SPOOF_MODE_QUERY:
 			/* Querying the spoof status of the sensor. */
 			out->spoof.ret = !!(sensor->flags &
-					MOTIONSENSE_FLAG_IN_SPOOF_MODE);
+					    MOTIONSENSE_FLAG_IN_SPOOF_MODE);
 			args->response_size = sizeof(out->spoof);
 			break;
 
@@ -1570,7 +1557,7 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 	default:
 		/* Call other users of the motion task */
 		if (IS_ENABLED(CONFIG_LID_ANGLE) &&
-		     (ret == EC_RES_INVALID_PARAM))
+		    (ret == EC_RES_INVALID_PARAM))
 			ret = host_cmd_motion_lid(args);
 		return ret;
 	}
@@ -1580,12 +1567,12 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args)
 
 DECLARE_HOST_COMMAND(EC_CMD_MOTION_SENSE_CMD, host_cmd_motion_sense,
 		     EC_VER_MASK(1) | EC_VER_MASK(2) | EC_VER_MASK(3) |
-		     EC_VER_MASK(4));
+			     EC_VER_MASK(4));
 
 /*****************************************************************************/
 /* Console commands */
 #ifdef CONFIG_CMD_ACCELS
-static int command_accelrange(int argc, char **argv)
+static int command_accelrange(int argc, const char **argv)
 {
 	char *e;
 	int id, data, round = 1;
@@ -1618,9 +1605,8 @@ static int command_accelrange(int argc, char **argv)
 		 * Write new range, if it returns invalid arg, then return
 		 * a parameter error.
 		 */
-		if (sensor->drv->set_range(sensor,
-					   data,
-					   round) == EC_ERROR_INVAL)
+		if (sensor->drv->set_range(sensor, data, round) ==
+		    EC_ERROR_INVAL)
 			return EC_ERROR_PARAM2;
 	} else {
 		ccprintf("Sensor %d range: %d\n", id, sensor->current_range);
@@ -1628,11 +1614,10 @@ static int command_accelrange(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(accelrange, command_accelrange,
-	"id [data [roundup]]",
-	"Read or write accelerometer range");
+DECLARE_CONSOLE_COMMAND(accelrange, command_accelrange, "id [data [roundup]]",
+			"Read or write accelerometer range");
 
-static int command_accelresolution(int argc, char **argv)
+static int command_accelresolution(int argc, const char **argv)
 {
 	char *e;
 	int id, data, round = 1;
@@ -1666,8 +1651,8 @@ static int command_accelresolution(int argc, char **argv)
 		 * return a parameter error.
 		 */
 		if (sensor->drv->set_resolution &&
-		    sensor->drv->set_resolution(sensor, data, round)
-			== EC_ERROR_INVAL)
+		    sensor->drv->set_resolution(sensor, data, round) ==
+			    EC_ERROR_INVAL)
 			return EC_ERROR_PARAM2;
 	} else {
 		ccprintf("Resolution for sensor %d: %d\n", id,
@@ -1677,10 +1662,10 @@ static int command_accelresolution(int argc, char **argv)
 	return EC_SUCCESS;
 }
 DECLARE_CONSOLE_COMMAND(accelres, command_accelresolution,
-	"id [data [roundup]]",
-	"Read or write accelerometer resolution");
+			"id [data [roundup]]",
+			"Read or write accelerometer resolution");
 
-static int command_accel_data_rate(int argc, char **argv)
+static int command_accel_data_rate(int argc, const char **argv)
 {
 	char *e;
 	int id, data, round = 1;
@@ -1717,8 +1702,8 @@ static int command_accel_data_rate(int argc, char **argv)
 		 */
 		config_id = motion_sense_get_ec_config();
 		sensor->config[SENSOR_CONFIG_AP].odr = 0;
-		sensor->config[config_id].odr =
-			data | (round ? ROUND_UP_FLAG : 0);
+		sensor->config[config_id].odr = data |
+						(round ? ROUND_UP_FLAG : 0);
 
 		atomic_or(&odr_event_required, 1 << (sensor - motion_sensors));
 		task_set_event(TASK_ID_MOTIONSENSE,
@@ -1734,10 +1719,10 @@ static int command_accel_data_rate(int argc, char **argv)
 	return EC_SUCCESS;
 }
 DECLARE_CONSOLE_COMMAND(accelrate, command_accel_data_rate,
-	"id [data [roundup]]",
-	"Read or write accelerometer ODR");
+			"id [data [roundup]]",
+			"Read or write accelerometer ODR");
 
-static int command_accel_read_xyz(int argc, char **argv)
+static int command_accel_read_xyz(int argc, const char **argv)
 {
 	char *e;
 	int id, n = 1, ret;
@@ -1761,22 +1746,21 @@ static int command_accel_read_xyz(int argc, char **argv)
 	while ((n-- > 0)) {
 		ret = sensor->drv->read(sensor, v);
 		if (ret == 0)
-			ccprintf("Current data %d: %-5d %-5d %-5d\n",
-				 id, v[X], v[Y], v[Z]);
+			ccprintf("Current data %d: %-5d %-5d %-5d\n", id, v[X],
+				 v[Y], v[Z]);
 		else
 			ccprintf("vector not ready\n");
-		ccprintf("Last calib. data %d: %-5d %-5d %-5d\n",
-			 id, sensor->xyz[X], sensor->xyz[Y], sensor->xyz[Z]);
+		ccprintf("Last calib. data %d: %-5d %-5d %-5d\n", id,
+			 sensor->xyz[X], sensor->xyz[Y], sensor->xyz[Z]);
 		task_wait_event(motion_min_interval);
 	}
 	return EC_SUCCESS;
 }
 
-DECLARE_CONSOLE_COMMAND(accelread, command_accel_read_xyz,
-	"id [n]",
-	"Read sensor x/y/z");
+DECLARE_CONSOLE_COMMAND(accelread, command_accel_read_xyz, "id [n]",
+			"Read sensor x/y/z");
 
-static int command_accel_init(int argc, char **argv)
+static int command_accel_init(int argc, const char **argv)
 {
 	char *e;
 	int id, ret;
@@ -1797,12 +1781,10 @@ static int command_accel_init(int argc, char **argv)
 	ccprintf("%s: state %d - %d\n", sensor->name, sensor->state, ret);
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(accelinit, command_accel_init,
-	"id",
-	"Init sensor");
+DECLARE_CONSOLE_COMMAND(accelinit, command_accel_init, "id", "Init sensor");
 
 #ifdef CONFIG_CMD_ACCEL_INFO
-static int command_display_accel_info(int argc, char **argv)
+static int command_display_accel_info(int argc, const char **argv)
 {
 	int val, i, j;
 
@@ -1819,17 +1801,17 @@ static int command_display_accel_info(int argc, char **argv)
 		ccprintf("type: %d\n", motion_sensors[i].type);
 		ccprintf("location: %d\n", motion_sensors[i].location);
 		ccprintf("port: %d\n", motion_sensors[i].port);
-		ccprintf("addr: %d\n", I2C_STRIP_FLAGS(motion_sensors[i]
-						    .i2c_spi_addr_flags));
+		ccprintf("addr: %d\n",
+			 I2C_STRIP_FLAGS(motion_sensors[i].i2c_spi_addr_flags));
 		ccprintf("range: %d\n", motion_sensors[i].current_range);
 		ccprintf("min_freq: %d\n", motion_sensors[i].min_frequency);
 		ccprintf("max_freq: %d\n", motion_sensors[i].max_frequency);
 		ccprintf("config:\n");
 		for (j = 0; j < SENSOR_CONFIG_MAX; j++) {
 			ccprintf("%d - odr: %umHz, ec_rate: %uus\n", j,
-				motion_sensors[i].config[j].odr &
-				~ROUND_UP_FLAG,
-				motion_sensors[i].config[j].ec_rate);
+				 motion_sensors[i].config[j].odr &
+					 ~ROUND_UP_FLAG,
+				 motion_sensors[i].config[j].ec_rate);
 		}
 	}
 
@@ -1843,9 +1825,8 @@ static int command_display_accel_info(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(accelinfo, command_display_accel_info,
-	"on/off",
-	"Print motion sensor info, lid angle calculations.");
+DECLARE_CONSOLE_COMMAND(accelinfo, command_display_accel_info, "on/off",
+			"Print motion sensor info, lid angle calculations.");
 #endif /* CONFIG_CMD_ACCEL_INFO */
 
 #endif /* CONFIG_CMD_ACCELS */
@@ -1854,15 +1835,16 @@ DECLARE_CONSOLE_COMMAND(accelinfo, command_display_accel_info,
 static void print_spoof_mode_status(int id)
 {
 	CPRINTS("Sensor %d spoof mode is %s. <%d, %d, %d>", id,
-		(motion_sensors[id].flags & MOTIONSENSE_FLAG_IN_SPOOF_MODE)
-				? "enabled" : "disabled",
+		(motion_sensors[id].flags & MOTIONSENSE_FLAG_IN_SPOOF_MODE) ?
+			"enabled" :
+			"disabled",
 		motion_sensors[id].spoof_xyz[X],
 		motion_sensors[id].spoof_xyz[Y],
 		motion_sensors[id].spoof_xyz[Z]);
 }
 
 #ifdef CONFIG_CMD_ACCELSPOOF
-static int command_accelspoof(int argc, char **argv)
+static int command_accelspoof(int argc, const char **argv)
 {
 	char *e;
 	int id, enable, i;
@@ -1897,8 +1879,8 @@ static int command_accelspoof(int argc, char **argv)
 			 */
 			if (argc == 6) {
 				for (i = 0; i < 3; i++)
-					s->spoof_xyz[i] = strtoi(argv[3 + i],
-								 &e, 0);
+					s->spoof_xyz[i] =
+						strtoi(argv[3 + i], &e, 0);
 			} else if (argc == 3) {
 				for (i = X; i <= Z; i++)
 					s->spoof_xyz[i] = s->raw_xyz[i];
diff --git a/common/motion_sense_fifo.c b/common/motion_sense_fifo.c
index 5743d0fdcb..672b328420 100644
--- a/common/motion_sense_fifo.c
+++ b/common/motion_sense_fifo.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,7 +15,7 @@
 #include "online_calibration.h"
 #include "stdbool.h"
 
-#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ##args)
 
 /**
  * Staged metadata for the fifo queue.
@@ -50,6 +50,12 @@ static struct queue fifo = QUEUE_NULL(CONFIG_ACCEL_FIFO_SIZE,
 				      struct ec_response_motion_sensor_data);
 /** Count of the number of entries lost due to a small queue. */
 static int fifo_lost;
+/*
+ * How many vector events are lost in the FIFO since last time
+ * FIFO info has been transmitted.
+ */
+static uint16_t fifo_sensor_lost[MAX_MOTION_SENSORS];
+
 /** Metadata for the fifo, used for staging and spreading data. */
 static struct fifo_staged fifo_staged;
 
@@ -60,6 +66,18 @@ static struct fifo_staged fifo_staged;
 static struct timestamp_state next_timestamp[MAX_MOTION_SENSORS];
 
 /**
+ * Expected data periods:
+ * copy of collection rate, updated when ODR changes.
+ */
+static uint32_t expected_data_periods[MAX_MOTION_SENSORS];
+
+/**
+ * Calculated data periods:
+ * can be different from collection rate when spreading.
+ */
+static uint32_t data_periods[MAX_MOTION_SENSORS];
+
+/**
  * Bitmap telling which sensors have valid entries in the next_timestamp array.
  */
 static uint32_t next_timestamp_initialized;
@@ -76,8 +94,8 @@ static int wake_up_needed;
  * @param data The data entry to check.
  * @return 1 if the entry is a timestamp, 0 otherwise.
  */
-static inline int is_timestamp(
-	const struct ec_response_motion_sensor_data *data)
+static inline int
+is_timestamp(const struct ec_response_motion_sensor_data *data)
 {
 	return data->flags & MOTIONSENSE_SENSOR_FLAG_TIMESTAMP;
 }
@@ -102,8 +120,8 @@ static inline bool is_data(const struct ec_response_motion_sensor_data *data)
  */
 static inline struct ec_response_motion_sensor_data *get_fifo_head(void)
 {
-	return ((struct ec_response_motion_sensor_data *) fifo.buffer) +
-		(fifo.state->head & fifo.buffer_units_mask);
+	return ((struct ec_response_motion_sensor_data *)fifo.buffer) +
+	       (fifo.state->head & fifo.buffer_units_mask);
 }
 
 /**
@@ -149,7 +167,7 @@ static void fifo_pop(void)
 
 	/* Increment lost counter if we have valid data. */
 	if (!is_timestamp(head))
-		motion_sensors[head->sensor_num].lost++;
+		fifo_sensor_lost[head->sensor_num]++;
 
 	/*
 	 * We're done if the initial count was non-zero and we only advanced the
@@ -228,11 +246,10 @@ static inline bool is_new_timestamp(uint8_t sensor_num)
  * @param data The data to stage.
  * @param sensor The sensor that generated the data
  * @param valid_data The number of readable data entries in the data.
+ *   sensor can be NULL (for activity sensors). valid_data must be 0 then.
  */
-static void fifo_stage_unit(
-	struct ec_response_motion_sensor_data *data,
-	struct motion_sensor_t *sensor,
-	int valid_data)
+static void fifo_stage_unit(struct ec_response_motion_sensor_data *data,
+			    struct motion_sensor_t *sensor, int valid_data)
 {
 	struct queue_chunk chunk;
 	int i;
@@ -266,7 +283,7 @@ static void fifo_stage_unit(
 		if (removed) {
 			mutex_unlock(&g_sensor_mutex);
 			if (IS_ENABLED(CONFIG_ONLINE_CALIB) &&
-			    next_timestamp_initialized & BIT(data->sensor_num))
+			    !is_new_timestamp(data->sensor_num))
 				online_calibration_process_data(
 					data, sensor,
 					next_timestamp[data->sensor_num].next);
@@ -279,7 +296,8 @@ static void fifo_stage_unit(
 
 	if (IS_ENABLED(CONFIG_TABLET_MODE))
 		data->flags |= (tablet_get_mode() ?
-				MOTIONSENSE_SENSOR_FLAG_TABLET_MODE : 0);
+					MOTIONSENSE_SENSOR_FLAG_TABLET_MODE :
+					0);
 
 	/*
 	 * Get the next writable block in the fifo. We don't need to lock this
@@ -316,8 +334,7 @@ static void fifo_stage_unit(
 	 * If the new per-sensor sample count is greater than 1, we'll need to
 	 * spread.
 	 */
-	if (IS_ENABLED(CONFIG_SENSOR_TIGHT_TIMESTAMPS) &&
-	    !is_timestamp(data) &&
+	if (IS_ENABLED(CONFIG_SENSOR_TIGHT_TIMESTAMPS) && !is_timestamp(data) &&
 	    ++fifo_staged.sample_count[data->sensor_num] > 1)
 		fifo_staged.requires_spreading = 1;
 
@@ -351,8 +368,9 @@ static void fifo_stage_timestamp(uint32_t timestamp, uint8_t sensor_num)
 static inline struct ec_response_motion_sensor_data *
 peek_fifo_staged(size_t offset)
 {
-	return (struct ec_response_motion_sensor_data *)
-		queue_get_write_chunk(&fifo, offset).buffer;
+	return (struct ec_response_motion_sensor_data *)queue_get_write_chunk(
+		       &fifo, offset)
+		.buffer;
 }
 
 void motion_sense_fifo_init(void)
@@ -389,9 +407,8 @@ void motion_sense_fifo_reset_needed_flags(void)
 	mutex_unlock(&g_sensor_mutex);
 }
 
-void motion_sense_fifo_insert_async_event(
-	struct motion_sensor_t *sensor,
-	enum motion_sense_async_event event)
+void motion_sense_fifo_insert_async_event(struct motion_sensor_t *sensor,
+					  enum motion_sense_async_event event)
 {
 	struct ec_response_motion_sensor_data vector;
 
@@ -409,11 +426,9 @@ inline void motion_sense_fifo_add_timestamp(uint32_t timestamp)
 	motion_sense_fifo_commit_data();
 }
 
-void motion_sense_fifo_stage_data(
-	struct ec_response_motion_sensor_data *data,
-	struct motion_sensor_t *sensor,
-	int valid_data,
-	uint32_t time)
+void motion_sense_fifo_stage_data(struct ec_response_motion_sensor_data *data,
+				  struct motion_sensor_t *sensor,
+				  int valid_data, uint32_t time)
 {
 	if (IS_ENABLED(CONFIG_SENSOR_TIGHT_TIMESTAMPS)) {
 		/* First entry, save the time for spreading later. */
@@ -426,8 +441,6 @@ void motion_sense_fifo_stage_data(
 
 void motion_sense_fifo_commit_data(void)
 {
-	/* Cached data periods, static to store off stack. */
-	static uint32_t data_periods[MAX_MOTION_SENSORS];
 	struct ec_response_motion_sensor_data *data;
 	int i, window, sensor_num;
 
@@ -468,15 +481,15 @@ void motion_sense_fifo_commit_data(void)
 		if (!fifo_staged.sample_count[i])
 			continue;
 
-		period = motion_sensors[i].collection_rate;
+		period = expected_data_periods[i];
 		/*
 		 * Clamp the sample period to the MIN of collection_rate and the
 		 * window length / (sample count - 1).
 		 */
 		if (window && fifo_staged.sample_count[i] > 1)
-			period = MIN(
-				period,
-				window / (fifo_staged.sample_count[i] - 1));
+			period =
+				MIN(period,
+				    window / (fifo_staged.sample_count[i] - 1));
 		data_periods[i] = period;
 	}
 
@@ -519,7 +532,7 @@ commit_data_end:
 		 * sensor or the timestamp is after our computed next, skip
 		 * ahead.
 		 */
-		if (!(next_timestamp_initialized & BIT(sensor_num)) ||
+		if (is_new_timestamp(sensor_num) ||
 		    time_after(data->timestamp,
 			       next_timestamp[sensor_num].prev)) {
 			next_timestamp[sensor_num].next = data->timestamp;
@@ -531,9 +544,9 @@ commit_data_end:
 		next_timestamp[sensor_num].prev =
 			next_timestamp[sensor_num].next;
 		next_timestamp[sensor_num].next +=
-			fifo_staged.requires_spreading
-			? data_periods[sensor_num]
-			: motion_sensors[sensor_num].collection_rate;
+			fifo_staged.requires_spreading ?
+				data_periods[sensor_num] :
+				expected_data_periods[sensor_num];
 
 		/* Update online calibration if enabled. */
 		data = peek_fifo_staged(i);
@@ -549,30 +562,30 @@ commit_data_end:
 	/* Reset metadata for next staging cycle. */
 	memset(&fifo_staged, 0, sizeof(fifo_staged));
 
-	/*
-	 * Reset the initialized bits. This will allow new timestamps to be
-	 * considered as the new "source of truth".
-	 */
-	next_timestamp_initialized = 0;
-
 	mutex_unlock(&g_sensor_mutex);
 }
 
 void motion_sense_fifo_get_info(
-	struct ec_response_motion_sense_fifo_info *fifo_info,
-	int reset)
+	struct ec_response_motion_sense_fifo_info *fifo_info, int reset)
 {
+	int i;
+
 	mutex_lock(&g_sensor_mutex);
 	fifo_info->size = fifo.buffer_units;
 	fifo_info->count = queue_count(&fifo);
 	fifo_info->total_lost = fifo_lost;
+	for (i = 0; i < MAX_MOTION_SENSORS; i++) {
+		fifo_info->lost[i] = fifo_sensor_lost[i];
+	}
 	mutex_unlock(&g_sensor_mutex);
 #ifdef CONFIG_MKBP_EVENT
 	fifo_info->timestamp = mkbp_last_event_time;
 #endif
 
-	if (reset)
+	if (reset) {
 		fifo_lost = 0;
+		memset(fifo_sensor_lost, 0, sizeof(fifo_sensor_lost));
+	}
 }
 
 /* LCOV_EXCL_START - function cannot be tested due to limitations with mkbp */
@@ -615,10 +628,23 @@ int motion_sense_fifo_read(int capacity_bytes, int max_count, void *out,
 
 void motion_sense_fifo_reset(void)
 {
+	static uint8_t fifo_info_buffer
+		[sizeof(struct ec_response_motion_sense_fifo_info) +
+		 sizeof(uint16_t) * MAX_MOTION_SENSORS];
+	struct ec_response_motion_sense_fifo_info *fifo_info =
+		(void *)fifo_info_buffer;
+
 	next_timestamp_initialized = 0;
 	memset(&fifo_staged, 0, sizeof(fifo_staged));
 	motion_sense_fifo_init();
 	queue_init(&fifo);
+	motion_sense_fifo_get_info(fifo_info, /*reset=*/true);
+}
+
+void motion_sense_set_data_period(int sensor_num, uint32_t data_period)
+{
+	expected_data_periods[sensor_num] = data_period;
+	next_timestamp_initialized &= ~BIT(sensor_num);
 }
 
 #ifdef CONFIG_CMD_ACCEL_FIFO
@@ -641,7 +667,8 @@ static int motion_sense_read_fifo(int argc, char **argv)
 			memcpy(&timestamp, v.data, sizeof(v.data));
 			ccprintf("Timestamp: 0x%016llx%s\n", timestamp,
 				 (v.flags & MOTIONSENSE_SENSOR_FLAG_FLUSH ?
-				  " - Flush" : ""));
+					  " - Flush" :
+					  ""));
 		} else {
 			ccprintf("%d %d: %-5d %-5d %-5d\n", i, v.sensor_num,
 				 v.data[X], v.data[Y], v.data[Z]);
@@ -650,7 +677,6 @@ static int motion_sense_read_fifo(int argc, char **argv)
 	return EC_SUCCESS;
 }
 
-DECLARE_CONSOLE_COMMAND(fiforead, motion_sense_read_fifo,
-	"id",
-	"Read Fifo sensor");
+DECLARE_CONSOLE_COMMAND(fiforead, motion_sense_read_fifo, "id",
+			"Read Fifo sensor");
 #endif /* defined(CONFIG_CMD_ACCEL_FIFO) */
diff --git a/common/newton_fit.c b/common/newton_fit.c
index ae81a45f07..5d217bc63d 100644
--- a/common/newton_fit.c
+++ b/common/newton_fit.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -32,7 +32,7 @@ static fp_t compute_error(struct newton_fit *fit, fpv3_t center)
 
 		_it = (struct newton_fit_orientation *)it.ptr;
 		e = FLOAT_TO_FP(1.0f) -
-			distance_squared(_it->orientation, center);
+		    distance_squared(_it->orientation, center);
 		error += fp_mul(e, e);
 	}
 
@@ -138,8 +138,8 @@ void newton_fit_compute(struct newton_fit *fit, fpv3_t bias, fp_t *radius)
 	if (queue_is_empty(fit->orientations))
 		return;
 
-	inv_orient_count = fp_div(FLOAT_TO_FP(1.0f),
-				  queue_count(fit->orientations));
+	inv_orient_count =
+		fp_div(FLOAT_TO_FP(1.0f), queue_count(fit->orientations));
 
 	memcpy(new_bias, bias, sizeof(fpv3_t));
 	new_error = compute_error(fit, new_bias);
diff --git a/common/ocpc.c b/common/ocpc.c
index 89d9b9cf4f..c27cf4efe5 100644
--- a/common/ocpc.c
+++ b/common/ocpc.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -32,23 +32,22 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CHARGER, outstr)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
-#define CPRINT_VIZ(format, args...) \
-do {							\
-	if (viz_output)				\
-		cprintf(CC_CHARGER, format, ## args);	\
-} while (0)
-#define CPRINTS_DBG(format, args...) \
-do {							\
-	if (debug_output)				\
-		cprints(CC_CHARGER, format, ## args);	\
-} while (0)
-#define CPRINTF_DBG(format, args...) \
-do {							\
-	if (debug_output)				\
-		cprintf(CC_CHARGER, format, ## args);	\
-} while (0)
-
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+#define CPRINT_VIZ(format, args...)                          \
+	do {                                                 \
+		if (viz_output)                              \
+			cprintf(CC_CHARGER, format, ##args); \
+	} while (0)
+#define CPRINTS_DBG(format, args...)                         \
+	do {                                                 \
+		if (debug_output)                            \
+			cprints(CC_CHARGER, format, ##args); \
+	} while (0)
+#define CPRINTF_DBG(format, args...)                         \
+	do {                                                 \
+		if (debug_output)                            \
+			cprintf(CC_CHARGER, format, ##args); \
+	} while (0)
 
 /* Code refactor will be needed if more than 2 charger chips are present */
 BUILD_ASSERT(CHARGER_NUM == 2);
@@ -68,14 +67,14 @@ static int viz_output;
 #define RSYS_IDX 2
 static int resistance_tbl[NUM_RESISTANCE_SAMPLES][3] = {
 	/* Rsys+Rbatt                   Rbatt                    Rsys */
-	{CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0},
-	{CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0},
-	{CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0},
-	{CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0},
-	{CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0},
-	{CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0},
-	{CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0},
-	{CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0},
+	{ CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0 },
+	{ CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0 },
+	{ CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0 },
+	{ CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0 },
+	{ CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0 },
+	{ CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0 },
+	{ CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0 },
+	{ CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0 },
 };
 static int resistance_tbl_idx;
 static int mean_resistance[3];
@@ -125,8 +124,8 @@ static void calc_resistance_stats(struct ocpc_data *ocpc)
 		for (j = 0; j < NUM_RESISTANCE_SAMPLES; j++)
 			sum += POW2(resistance_tbl[j][i] - mean_resistance[i]);
 
-		stddev_resistance[i] = fp_sqrtf(INT_TO_FP(sum /
-						       NUM_RESISTANCE_SAMPLES));
+		stddev_resistance[i] =
+			fp_sqrtf(INT_TO_FP(sum / NUM_RESISTANCE_SAMPLES));
 		stddev_resistance[i] = FP_TO_INT(stddev_resistance[i]);
 		/*
 		 * Don't let our stddev collapse to 0 to continually consider
@@ -149,8 +148,7 @@ static bool is_within_range(struct ocpc_data *ocpc, int combined, int rbatt,
 	/* Discard measurements not within a 6 std. dev. window. */
 	if ((ocpc->chg_flags[act_chg] & OCPC_NO_ISYS_MEAS_CAP)) {
 		/* We only know the combined Rsys+Rbatt */
-		valid = (combined > 0) &&
-			(combined <= ub[COMBINED_IDX]) &&
+		valid = (combined > 0) && (combined <= ub[COMBINED_IDX]) &&
 			(combined >= lb[COMBINED_IDX]);
 	} else {
 		valid = (rsys <= ub[RSYS_IDX]) && (rsys >= lb[RSYS_IDX]) &&
@@ -201,12 +199,12 @@ enum ec_error_list ocpc_calc_resistances(struct ocpc_data *ocpc,
 		 * out Rsys from Rbatt.
 		 */
 		combined = ((ocpc->vsys_aux_mv - battery->voltage) * 1000) /
-			    battery->current;
+			   battery->current;
 	} else {
 		rsys = ((ocpc->vsys_aux_mv - ocpc->vsys_mv) * 1000) /
-				 ocpc->isys_ma;
+		       ocpc->isys_ma;
 		rbatt = ((ocpc->vsys_mv - battery->voltage) * 1000) /
-				 battery->current;
+			battery->current;
 		combined = rsys + rbatt;
 	}
 
@@ -222,35 +220,36 @@ enum ec_error_list ocpc_calc_resistances(struct ocpc_data *ocpc,
 		resistance_tbl[resistance_tbl_idx][COMBINED_IDX] =
 			MAX(combined, CONFIG_OCPC_DEF_RBATT_MOHMS);
 		calc_resistance_stats(ocpc);
-		resistance_tbl_idx = (resistance_tbl_idx + 1) %
-					NUM_RESISTANCE_SAMPLES;
+		resistance_tbl_idx =
+			(resistance_tbl_idx + 1) % NUM_RESISTANCE_SAMPLES;
 	}
 
 	if (seeded) {
 		ocpc->combined_rsys_rbatt_mo =
-					MAX(mean_resistance[COMBINED_IDX],
-					    CONFIG_OCPC_DEF_RBATT_MOHMS);
+			MAX(mean_resistance[COMBINED_IDX],
+			    CONFIG_OCPC_DEF_RBATT_MOHMS);
 
 		if (!(ocpc->chg_flags[act_chg] & OCPC_NO_ISYS_MEAS_CAP)) {
 			ocpc->rsys_mo = mean_resistance[RSYS_IDX];
 			ocpc->rbatt_mo = MAX(mean_resistance[RBATT_IDX],
 					     CONFIG_OCPC_DEF_RBATT_MOHMS);
-			CPRINTS_DBG("Rsys: %dmOhm Rbatt: %dmOhm",
-				    ocpc->rsys_mo, ocpc->rbatt_mo);
+			CPRINTS_DBG("Rsys: %dmOhm Rbatt: %dmOhm", ocpc->rsys_mo,
+				    ocpc->rbatt_mo);
 		}
 
 		CPRINTS_DBG("Rsys+Rbatt: %dmOhm", ocpc->combined_rsys_rbatt_mo);
 	} else {
 		seeded = ++initial_samples >= (2 * NUM_RESISTANCE_SAMPLES) ?
-			true : false;
+				 true :
+				 false;
 	}
 
 	return EC_SUCCESS;
 }
 
 int ocpc_config_secondary_charger(int *desired_input_current,
-				  struct ocpc_data *ocpc,
-				  int voltage_mv, int current_ma)
+				  struct ocpc_data *ocpc, int voltage_mv,
+				  int current_ma)
 {
 	int rv = EC_SUCCESS;
 	struct batt_params batt;
@@ -342,7 +341,6 @@ int ocpc_config_secondary_charger(int *desired_input_current,
 		iterations = 0;
 	}
 
-
 	/*
 	 * We need to induce a current flow that matches the requested current
 	 * by raising VSYS.  Let's start by getting the latest data that we
@@ -353,7 +351,6 @@ int ocpc_config_secondary_charger(int *desired_input_current,
 	ocpc_get_adcs(ocpc);
 	charger_get_params(&charger);
 
-
 	/*
 	 * If the system is in S5/G3, we can calculate the board and battery
 	 * resistances.
@@ -378,9 +375,9 @@ int ocpc_config_secondary_charger(int *desired_input_current,
 	/* Set our current target accordingly. */
 	if (batt.desired_voltage) {
 		if (((batt.voltage < batt_info->voltage_min) ||
-		    ((batt.voltage < batt_info->voltage_normal) &&
-		    (current_ma >= 0)	&&
-		    (current_ma <= batt_info->precharge_current))) &&
+		     ((batt.voltage < batt_info->voltage_normal) &&
+		      (current_ma >= 0) &&
+		      (current_ma <= batt_info->precharge_current))) &&
 		    (ph != PHASE_PRECHARGE)) {
 			/*
 			 * If the charger IC doesn't support the linear charge
@@ -396,8 +393,7 @@ int ocpc_config_secondary_charger(int *desired_input_current,
 			}
 		} else if (batt.voltage < batt.desired_voltage) {
 			if ((ph == PHASE_PRECHARGE) &&
-			    (current_ma >
-			     batt_info->precharge_current)) {
+			    (current_ma > batt_info->precharge_current)) {
 				/*
 				 * Precharge phase is complete.  Now set the
 				 * target VSYS to the battery voltage to prevent
@@ -437,7 +433,6 @@ int ocpc_config_secondary_charger(int *desired_input_current,
 			ph = ph == PHASE_CC ? PHASE_CV_TRIP : PHASE_CV_COMPLETE;
 			if (ph == PHASE_CV_TRIP)
 				i_ma_CC_CV = batt.current;
-
 		}
 	}
 
@@ -486,8 +481,7 @@ int ocpc_config_secondary_charger(int *desired_input_current,
 	CPRINTS_DBG("min_vsys_target = %d", min_vsys_target);
 
 	/* Obtain the drive from our PID controller. */
-	if ((ocpc->last_vsys != OCPC_UNINIT) &&
-	    (ph > PHASE_PRECHARGE)) {
+	if ((ocpc->last_vsys != OCPC_UNINIT) && (ph > PHASE_PRECHARGE)) {
 		drive = (k_p * error / k_p_div) +
 			(k_i * ocpc->integral / k_i_div) +
 			(k_d * derivative / k_d_div);
@@ -521,23 +515,25 @@ int ocpc_config_secondary_charger(int *desired_input_current,
 	 * desired voltage.
 	 */
 	if (ph == PHASE_CV_TRIP) {
-		vsys_target = batt.desired_voltage +
-				((i_ma_CC_CV *
-				  ocpc->combined_rsys_rbatt_mo) / 1000);
+		vsys_target =
+			batt.desired_voltage +
+			((i_ma_CC_CV * ocpc->combined_rsys_rbatt_mo) / 1000);
 		CPRINTS_DBG("i_ma_CC_CV = %d", i_ma_CC_CV);
 	}
 	if (ph == PHASE_CV_COMPLETE)
-		vsys_target = batt.desired_voltage +
-				((batt_info->precharge_current *
-				  ocpc->combined_rsys_rbatt_mo) / 1000);
+		vsys_target =
+			batt.desired_voltage + ((batt_info->precharge_current *
+						 ocpc->combined_rsys_rbatt_mo) /
+						1000);
 
 	/*
 	 * Ensure VSYS is no higher than the specified maximum battery voltage
 	 * plus the voltage drop across the system.
 	 */
-	vsys_target = CLAMP(vsys_target, min_vsys_target,
-			    batt_info->voltage_max +
-			    (i_ma * ocpc->combined_rsys_rbatt_mo / 1000));
+	vsys_target =
+		CLAMP(vsys_target, min_vsys_target,
+		      batt_info->voltage_max +
+			      (i_ma * ocpc->combined_rsys_rbatt_mo / 1000));
 
 	/* If we're input current limited, we cannot increase VSYS any more. */
 	CPRINTS_DBG("OCPC: Inst. Input Current: %dmA (Limit: %dmA)",
@@ -550,7 +546,7 @@ int ocpc_config_secondary_charger(int *desired_input_current,
 		 * 95% of the limit.
 		 */
 		if (ocpc->secondary_ibus_ma >=
-		     (*desired_input_current * 95 / 100))
+		    (*desired_input_current * 95 / 100))
 			icl_reached = true;
 	}
 
@@ -635,9 +631,8 @@ void ocpc_get_adcs(struct ocpc_data *ocpc)
 		ocpc->isys_ma = val;
 }
 
-__overridable void ocpc_get_pid_constants(int *kp, int *kp_div,
-					  int *ki, int *ki_div,
-					  int *kd, int *kd_div)
+__overridable void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+					  int *ki_div, int *kd, int *kd_div)
 {
 }
 
@@ -647,8 +642,8 @@ static enum ec_error_list ocpc_precharge_enable(bool enable)
 	int rv = charger_enable_linear_charge(CHARGER_PRIMARY, enable);
 
 	if (rv)
-		CPRINTS("OCPC: Failed to %sble linear charge!", enable ? "ena"
-			: "dis");
+		CPRINTS("OCPC: Failed to %sble linear charge!",
+			enable ? "ena" : "dis");
 
 	return rv;
 }
@@ -669,8 +664,9 @@ void ocpc_reset(struct ocpc_data *ocpc)
 	 */
 	if (ocpc->active_chg_chip > CHARGER_PRIMARY) {
 		voltage = (batt.voltage > 0 &&
-			  !(batt.flags & BATT_FLAG_BAD_VOLTAGE)) ?
-			  batt.voltage : battery_get_info()->voltage_normal;
+			   !(batt.flags & BATT_FLAG_BAD_VOLTAGE)) ?
+				  batt.voltage :
+				  battery_get_info()->voltage_normal;
 		CPRINTS("OCPC: C%d Init VSYS to %dmV", ocpc->active_chg_chip,
 			voltage);
 		charger_set_voltage(ocpc->active_chg_chip, voltage);
@@ -702,7 +698,7 @@ void ocpc_init(struct ocpc_data *ocpc)
 	board_ocpc_init(ocpc);
 }
 
-static int command_ocpcdebug(int argc, char **argv)
+static int command_ocpcdebug(int argc, const char **argv)
 {
 	if (argc < 2)
 		return EC_ERROR_PARAM_COUNT;
@@ -732,7 +728,7 @@ DECLARE_SAFE_CONSOLE_COMMAND(ocpcdebug, command_ocpcdebug,
 			     "Each segment is 5% of current target. All shows"
 			     " both. Disable shows no debug output.");
 
-static int command_ocpcpid(int argc, char **argv)
+static int command_ocpcpid(int argc, const char **argv)
 {
 	int *num, *denom;
 
diff --git a/common/onewire.c b/common/onewire.c
index cdb5837255..0b109bbdcd 100644
--- a/common/onewire.c
+++ b/common/onewire.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,16 +16,19 @@
  * Note that these timing are actually _longer_ than legacy 1-wire standard
  * speed because we're running the 1-wire bus at 3.3V instead of 5V.
  */
-#define T_RSTL 602  /* Reset low pulse; 600-960 us */
-#define T_MSP   72  /* Presence detect sample time; 70-75 us */
-#define T_RSTH (68 + 260 + 5 + 2) /* Reset high; tPDHmax + tPDLmax + tRECmin */
-#define T_SLOT  70  /* Timeslot; >67 us */
-#define T_W0L   63  /* Write 0 low; 62-120 us */
-#define T_W1L    7  /* Write 1 low; 5-15 us */
-#define T_RL     7  /* Read low; 5-15 us */
-#define T_MSR    9  /* Read sample time; <15 us.  Must be at least 200 ns after
-		     * T_RL since that's how long the signal takes to be pulled
-		     * up on our board.  */
+#define T_RSTL 602 /* Reset low pulse; 600-960 us */
+#define T_MSP 72 /* Presence detect sample time; 70-75 us */
+#define T_RSTH                                                        \
+	(68 + 260 + 5 + 2) /* Reset high; tPDHmax + tPDLmax + tRECmin \
+			    */
+#define T_SLOT 70 /* Timeslot; >67 us */
+#define T_W0L 63 /* Write 0 low; 62-120 us */
+#define T_W1L 7 /* Write 1 low; 5-15 us */
+#define T_RL 7 /* Read low; 5-15 us */
+#define T_MSR                                                         \
+	9 /* Read sample time; <15 us.  Must be at least 200 ns after \
+	   * T_RL since that's how long the signal takes to be pulled \
+	   * up on our board.  */
 
 /**
  * Output low on the bus for <usec> us, then switch back to open-drain input.
@@ -98,7 +101,6 @@ static void writebit(int bit)
 		interrupt_enable();
 		udelay(T_SLOT - T_W0L);
 	}
-
 }
 
 int onewire_reset(void)
@@ -133,7 +135,7 @@ int onewire_read(void)
 	int i;
 
 	for (i = 0; i < 8; i++)
-		data |= readbit() << i;  /* LSB first */
+		data |= readbit() << i; /* LSB first */
 
 	return data;
 }
@@ -143,5 +145,5 @@ void onewire_write(int data)
 	int i;
 
 	for (i = 0; i < 8; i++)
-		writebit((data >> i) & 0x01);  /* LSB first */
+		writebit((data >> i) & 0x01); /* LSB first */
 }
diff --git a/common/online_calibration.c b/common/online_calibration.c
index 6ff46f4714..2d79c6ae1d 100644
--- a/common/online_calibration.c
+++ b/common/online_calibration.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -202,8 +202,7 @@ void online_calibration_init(void)
 		void *type_specific_data = NULL;
 
 		s->online_calib_data->last_temperature = -1;
-		type_specific_data =
-			s->online_calib_data->type_specific_data;
+		type_specific_data = s->online_calib_data->type_specific_data;
 
 		if (!type_specific_data)
 			continue;
diff --git a/common/panic_output.c b/common/panic_output.c
index 45fd1f732a..e5a184be27 100644
--- a/common/panic_output.c
+++ b/common/panic_output.c
@@ -1,8 +1,9 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
 #include "cpu.h"
@@ -30,17 +31,13 @@ static struct panic_data zephyr_panic_data;
 #define CONFIG_PANIC_DATA_BASE (&zephyr_panic_data)
 #endif
 /* Panic data goes at the end of RAM. */
-static struct panic_data * const pdata_ptr = PANIC_DATA_PTR;
+static struct panic_data *const pdata_ptr = PANIC_DATA_PTR;
 
 /* Common SW Panic reasons strings */
-const char * const panic_sw_reasons[] = {
+const char *const panic_sw_reasons[] = {
 #ifdef CONFIG_SOFTWARE_PANIC
-	"PANIC_SW_DIV_ZERO",
-	"PANIC_SW_STACK_OVERFLOW",
-	"PANIC_SW_PD_CRASH",
-	"PANIC_SW_ASSERT",
-	"PANIC_SW_WATCHDOG",
-	"PANIC_SW_RNG",
+	"PANIC_SW_DIV_ZERO",   "PANIC_SW_STACK_OVERFLOW", "PANIC_SW_PD_CRASH",
+	"PANIC_SW_ASSERT",     "PANIC_SW_WATCHDOG",	  "PANIC_SW_RNG",
 	"PANIC_SW_PMIC_FAULT",
 #endif
 };
@@ -52,8 +49,7 @@ const char * const panic_sw_reasons[] = {
  */
 int panic_sw_reason_is_valid(uint32_t reason)
 {
-	return (IS_ENABLED(CONFIG_SOFTWARE_PANIC) &&
-		reason >= PANIC_SW_BASE &&
+	return (IS_ENABLED(CONFIG_SOFTWARE_PANIC) && reason >= PANIC_SW_BASE &&
 		(reason - PANIC_SW_BASE) < ARRAY_SIZE(panic_sw_reasons));
 }
 
@@ -125,7 +121,7 @@ void panic_reboot(void)
 }
 
 /* Complete the processing of a panic, after the initial message is shown */
-static noreturn void complete_panic(int linenum)
+test_mockable_static_noreturn void complete_panic(int linenum)
 {
 	if (IS_ENABLED(CONFIG_SOFTWARE_PANIC))
 		software_panic(PANIC_SW_ASSERT, linenum);
@@ -143,8 +139,8 @@ void panic_assert_fail(const char *fname, int linenum)
 void panic_assert_fail(const char *msg, const char *func, const char *fname,
 		       int linenum)
 {
-	panic_printf("\nASSERTION FAILURE '%s' in %s() at %s:%d\n",
-		     msg, func, fname, linenum);
+	panic_printf("\nASSERTION FAILURE '%s' in %s() at %s:%d\n", msg, func,
+		     fname, linenum);
 	complete_panic(linenum);
 }
 #endif
@@ -179,9 +175,8 @@ uintptr_t get_panic_data_start(void)
 	if (IS_ENABLED(CONFIG_BOARD_NATIVE_POSIX))
 		return (uintptr_t)pdata_ptr;
 
-	return ((uintptr_t)CONFIG_PANIC_DATA_BASE
-			   + CONFIG_PANIC_DATA_SIZE
-			   - pdata_ptr->struct_size);
+	return ((uintptr_t)CONFIG_PANIC_DATA_BASE + CONFIG_PANIC_DATA_SIZE -
+		pdata_ptr->struct_size);
 }
 
 static uint32_t get_panic_data_size(void)
@@ -212,7 +207,7 @@ struct panic_data *get_panic_data_write(void)
 	 * and magic is safe because it is always placed at the
 	 * end of RAM.
 	 */
-	struct panic_data * const pdata_ptr = PANIC_DATA_PTR;
+	struct panic_data *const pdata_ptr = PANIC_DATA_PTR;
 	const struct jump_data *jdata_ptr;
 	uintptr_t data_begin;
 	size_t move_size;
@@ -249,8 +244,8 @@ struct panic_data *get_panic_data_write(void)
 	 * anything and can just return pdata_ptr (clear memory, set magic
 	 * and struct_size first).
 	 */
-	if (jdata_ptr->magic != JUMP_DATA_MAGIC ||
-	    jdata_ptr->version < 1 || jdata_ptr->version > 3) {
+	if (jdata_ptr->magic != JUMP_DATA_MAGIC || jdata_ptr->version < 1 ||
+	    jdata_ptr->version > 3) {
 		memset(pdata_ptr, 0, CONFIG_PANIC_DATA_SIZE);
 		pdata_ptr->magic = PANIC_DATA_MAGIC;
 		pdata_ptr->struct_size = CONFIG_PANIC_DATA_SIZE;
@@ -273,7 +268,8 @@ struct panic_data *get_panic_data_write(void)
 
 	if (move_size != 0) {
 		/* Move jump_tags and jump_data */
-		memmove((void *)(data_begin - delta), (void *)data_begin, move_size);
+		memmove((void *)(data_begin - delta), (void *)data_begin,
+			move_size);
 	}
 
 	/*
@@ -312,6 +308,10 @@ DECLARE_HOOK(HOOK_CHIPSET_RESET, panic_init, HOOK_PRIO_LAST);
 #pragma clang diagnostic push
 #pragma clang diagnostic ignored "-Winfinite-recursion"
 #endif /* __clang__ */
+#if __GNUC__ >= 12
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Winfinite-recursion"
+#endif /* __GNUC__ >= 12 */
 static void stack_overflow_recurse(int n)
 {
 	ccprintf("+%d", n);
@@ -322,7 +322,7 @@ static void stack_overflow_recurse(int n)
 	 */
 	msleep(10);
 
-	stack_overflow_recurse(n+1);
+	stack_overflow_recurse(n + 1);
 
 	/*
 	 * Do work after the recursion, or else the compiler uses tail-chaining
@@ -330,6 +330,9 @@ static void stack_overflow_recurse(int n)
 	 */
 	ccprintf("-%d", n);
 }
+#if __GNUC__ >= 12
+#pragma GCC diagnostic pop
+#endif /* __GNUC__ >= 12 */
 #ifdef __clang__
 #pragma clang diagnostic pop
 #endif /* __clang__ */
@@ -338,7 +341,7 @@ static void stack_overflow_recurse(int n)
 /*****************************************************************************/
 /* Console commands */
 #ifdef CONFIG_CMD_CRASH
-static int command_crash(int argc, char **argv)
+static int command_crash(int argc, const char **argv)
 {
 	if (argc < 2)
 		return EC_ERROR_PARAM1;
@@ -382,22 +385,23 @@ static int command_crash(int argc, char **argv)
 	return EC_ERROR_UNKNOWN;
 }
 DECLARE_CONSOLE_COMMAND(crash, command_crash,
-		"[assert | divzero | udivzero"
+			"[assert | divzero | udivzero"
 #ifdef CONFIG_CMD_STACKOVERFLOW
 			" | stack"
 #endif
 			" | unaligned | watchdog | hang]",
-		"Crash the system (for testing)");
+			"Crash the system (for testing)");
 #endif /* CONFIG_CMD_CRASH */
 
-static int command_panicinfo(int argc, char **argv)
+static int command_panicinfo(int argc, const char **argv)
 {
-	struct panic_data * const pdata_ptr = panic_get_data();
+	struct panic_data *const pdata_ptr = panic_get_data();
 
 	if (pdata_ptr) {
 		ccprintf("Saved panic data:%s\n",
 			 (pdata_ptr->flags & PANIC_DATA_FLAG_OLD_CONSOLE ?
-			  "" : " (NEW)"));
+				  "" :
+				  " (NEW)"));
 
 		panic_data_print(pdata_ptr);
 
@@ -405,12 +409,11 @@ static int command_panicinfo(int argc, char **argv)
 		pdata_ptr->flags |= PANIC_DATA_FLAG_OLD_CONSOLE;
 	} else {
 		ccprintf("No saved panic data available "
-		    "or panic data can't be safely interpreted.\n");
+			 "or panic data can't be safely interpreted.\n");
 	}
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(panicinfo, command_panicinfo,
-			NULL,
+DECLARE_CONSOLE_COMMAND(panicinfo, command_panicinfo, NULL,
 			"Print info from a previous panic");
 
 /*****************************************************************************/
@@ -421,7 +424,7 @@ host_command_panic_info(struct host_cmd_handler_args *args)
 {
 	uint32_t pdata_size = get_panic_data_size();
 	uintptr_t pdata_start = get_panic_data_start();
-	struct panic_data * pdata;
+	struct panic_data *pdata;
 
 	if (pdata_start && pdata_size > 0) {
 		ASSERT(pdata_size <= args->response_max);
@@ -437,6 +440,5 @@ host_command_panic_info(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_GET_PANIC_INFO,
-		     host_command_panic_info,
+DECLARE_HOST_COMMAND(EC_CMD_GET_PANIC_INFO, host_command_panic_info,
 		     EC_VER_MASK(0));
diff --git a/common/pd_log.c b/common/pd_log.c
index 3708aad72e..477f8327eb 100644
--- a/common/pd_log.c
+++ b/common/pd_log.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,8 +21,7 @@ BUILD_ASSERT(PD_LOG_SIZE_MASK == EVENT_LOG_SIZE_MASK);
 BUILD_ASSERT(PD_LOG_TIMESTAMP_SHIFT == EVENT_LOG_TIMESTAMP_SHIFT);
 BUILD_ASSERT(PD_EVENT_NO_ENTRY == EVENT_LOG_NO_ENTRY);
 
-void pd_log_event(uint8_t type, uint8_t size_port,
-		  uint16_t data, void *payload)
+void pd_log_event(uint8_t type, uint8_t size_port, uint16_t data, void *payload)
 {
 	uint32_t timestamp = get_time().val >> PD_LOG_TIMESTAMP_SHIFT;
 
@@ -48,8 +47,8 @@ void pd_log_recv_vdm(int port, int cnt, uint32_t *payload)
 		return;
 
 	if (r->type != PD_EVENT_NO_ENTRY) {
-		timestamp = (get_time().val >> PD_LOG_TIMESTAMP_SHIFT)
-			  - r->timestamp;
+		timestamp = (get_time().val >> PD_LOG_TIMESTAMP_SHIFT) -
+			    r->timestamp;
 		log_add_event(r->type, size_port, r->data, r->payload,
 			      timestamp);
 		/* record that we have enqueued new content */
@@ -84,8 +83,7 @@ dequeue_retry:
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_PD_GET_LOG_ENTRY,
-		     hc_pd_get_log_entry,
+DECLARE_HOST_COMMAND(EC_CMD_PD_GET_LOG_ENTRY, hc_pd_get_log_entry,
 		     EC_VER_MASK(0));
 
 static enum ec_status hc_pd_write_log_entry(struct host_cmd_handler_args *args)
@@ -117,8 +115,7 @@ static enum ec_status hc_pd_write_log_entry(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_PD_WRITE_LOG_ENTRY,
-		     hc_pd_write_log_entry,
+DECLARE_HOST_COMMAND(EC_CMD_PD_WRITE_LOG_ENTRY, hc_pd_write_log_entry,
 		     EC_VER_MASK(0));
 #else /* !HAS_TASK_HOSTCMD */
 /* we are a PD accessory, send back the events as a VDM (VDO_CMD_GET_LOG) */
diff --git a/common/peci.c b/common/peci.c
index e0f03c95dd..b124d6b67b 100644
--- a/common/peci.c
+++ b/common/peci.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,12 +8,13 @@
 #include "chipset.h"
 #include "console.h"
 #include "peci.h"
+#include "printf.h"
 #include "util.h"
 
 static int peci_get_cpu_temp(int *cpu_temp)
 {
 	int rv;
-	uint8_t r_buf[PECI_GET_TEMP_READ_LENGTH] = {0};
+	uint8_t r_buf[PECI_GET_TEMP_READ_LENGTH] = { 0 };
 	struct peci_data peci = {
 		.cmd_code = PECI_CMD_GET_TEMP,
 		.addr = PECI_TARGET_ADDRESS,
@@ -72,10 +73,10 @@ int peci_temp_sensor_get_val(int idx, int *temp_ptr)
 /*****************************************************************************/
 /* Console commands */
 #ifdef CONFIG_CMD_PECI
-static int peci_cmd(int argc, char **argv)
+static int peci_cmd(int argc, const char **argv)
 {
-	uint8_t r_buf[PECI_READ_DATA_FIFO_SIZE] = {0};
-	uint8_t w_buf[PECI_WRITE_DATA_FIFO_SIZE] = {0};
+	uint8_t r_buf[PECI_READ_DATA_FIFO_SIZE] = { 0 };
+	uint8_t w_buf[PECI_WRITE_DATA_FIFO_SIZE] = { 0 };
 	struct peci_data peci = {
 		.w_buf = w_buf,
 		.r_buf = r_buf,
@@ -139,15 +140,20 @@ static int peci_cmd(int argc, char **argv)
 	if (peci_transaction(&peci)) {
 		ccprintf("PECI transaction error\n");
 		return EC_ERROR_UNKNOWN;
+	} else {
+		char str_buf[hex_str_buf_size(peci.r_len)];
+
+		snprintf_hex_buffer(str_buf, sizeof(str_buf),
+				    HEX_BUF(r_buf, sizeof(str_buf)));
+		ccprintf("PECI read data: %s\n", str_buf);
+
+		return EC_SUCCESS;
 	}
-	ccprintf("PECI read data: %ph\n", HEX_BUF(r_buf, peci.r_len));
-	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(peci, peci_cmd,
-			"addr wlen rlen cmd timeout(us)",
+DECLARE_CONSOLE_COMMAND(peci, peci_cmd, "addr wlen rlen cmd timeout(us)",
 			"PECI command");
 
-static int command_peci_temp(int argc, char **argv)
+static int command_peci_temp(int argc, const char **argv)
 {
 	int t;
 
@@ -159,7 +165,6 @@ static int command_peci_temp(int argc, char **argv)
 	ccprintf("CPU temp: %d K, %d C\n", t, K_TO_C(t));
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(pecitemp, command_peci_temp,
-			NULL,
+DECLARE_CONSOLE_COMMAND(pecitemp, command_peci_temp, NULL,
 			"Print CPU temperature");
 #endif /* CONFIG_CMD_PECI */
diff --git a/common/peripheral.c b/common/peripheral.c
index e70ec19347..557aa0ed6f 100644
--- a/common/peripheral.c
+++ b/common/peripheral.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -30,7 +30,8 @@ static enum ec_status hc_locate_chip(struct host_cmd_handler_args *args)
 #endif /* CONFIG_CBI_EEPROM */
 		break;
 	case EC_CHIP_TYPE_TCPC:
-#if defined(CONFIG_USB_POWER_DELIVERY) && defined(CONFIG_USB_PD_PORT_MAX_COUNT) && !defined(CONFIG_USB_PD_TCPC)
+#if defined(CONFIG_USB_POWER_DELIVERY) && \
+	defined(CONFIG_USB_PD_PORT_MAX_COUNT) && !defined(CONFIG_USB_PD_TCPC)
 		if (params->index >= board_get_usb_pd_port_count())
 			return EC_RES_OVERFLOW;
 		resp->bus_type = tcpc_config[params->index].bus_type;
diff --git a/common/peripheral_charger.c b/common/peripheral_charger.c
index 024379fe58..5767315a78 100644
--- a/common/peripheral_charger.c
+++ b/common/peripheral_charger.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,7 +23,7 @@
 
 /* Host event queue. Shared by all ports. */
 static struct queue const host_events =
-		QUEUE_NULL(PCHG_EVENT_QUEUE_SIZE, uint32_t);
+	QUEUE_NULL(PCHG_EVENT_QUEUE_SIZE, uint32_t);
 struct mutex host_event_mtx;
 
 static void pchg_queue_event(struct pchg *ctx, enum pchg_event event)
@@ -59,7 +59,7 @@ static void pchg_queue_host_event(struct pchg *ctx, uint32_t event)
 static const char *_text_state(enum pchg_state state)
 {
 	/* TODO: Use "S%d" for normal build. */
-	static const char * const state_names[] = EC_PCHG_STATE_TEXT;
+	static const char *const state_names[] = EC_PCHG_STATE_TEXT;
 	BUILD_ASSERT(ARRAY_SIZE(state_names) == PCHG_STATE_COUNT);
 
 	if (state >= sizeof(state_names))
@@ -71,7 +71,7 @@ static const char *_text_state(enum pchg_state state)
 static const char *_text_event(enum pchg_event event)
 {
 	/* TODO: Use "S%d" for normal build. */
-	static const char * const event_names[] = {
+	static const char *const event_names[] = {
 		[PCHG_EVENT_NONE] = "NONE",
 		[PCHG_EVENT_IRQ] = "IRQ",
 		[PCHG_EVENT_RESET] = "RESET",
@@ -118,7 +118,8 @@ static void _clear_port(struct pchg *ctx)
 }
 
 __overridable void board_pchg_power_on(int port, bool on)
-{}
+{
+}
 
 static enum pchg_state pchg_reset(struct pchg *ctx)
 {
@@ -504,7 +505,7 @@ static int pchg_run(struct pchg *ctx)
 			/* Don't wake up if the lid is closed. */
 			return 0;
 		return (ctx->event == PCHG_EVENT_DEVICE_DETECTED ||
-				ctx->event == PCHG_EVENT_DEVICE_LOST);
+			ctx->event == PCHG_EVENT_DEVICE_LOST);
 	}
 
 	if (ctx->event == PCHG_EVENT_CHARGE_UPDATE)
@@ -538,25 +539,37 @@ void pchg_irq(enum gpio_signal signal)
 	}
 }
 
-
 static void pchg_startup(void)
 {
 	struct pchg *ctx;
 	int p;
+	int active_pchg_count = 0;
+	int rv;
 
 	CPRINTS("%s", __func__);
 	queue_init(&host_events);
 
 	for (p = 0; p < pchg_count; p++) {
+		rv = EC_SUCCESS;
 		ctx = &pchgs[p];
 		_clear_port(ctx);
 		ctx->mode = PCHG_MODE_NORMAL;
+		gpio_disable_interrupt(ctx->cfg->irq_pin);
 		board_pchg_power_on(p, 1);
 		ctx->cfg->drv->reset(ctx);
-		gpio_enable_interrupt(ctx->cfg->irq_pin);
+		if (ctx->cfg->drv->get_chip_info)
+			rv = ctx->cfg->drv->get_chip_info(ctx);
+		if (rv == EC_SUCCESS) {
+			gpio_enable_interrupt(ctx->cfg->irq_pin);
+			active_pchg_count++;
+		} else {
+			CPRINTS("ERR: Failed to probe P%d", p);
+			board_pchg_power_on(p, 0);
+		}
 	}
 
-	task_wake(TASK_ID_PCHG);
+	if (active_pchg_count)
+		task_wake(TASK_ID_PCHG);
 }
 DECLARE_HOOK(HOOK_CHIPSET_STARTUP, pchg_startup, HOOK_PRIO_DEFAULT);
 
@@ -630,8 +643,8 @@ static enum ec_status hc_pchg(struct host_cmd_handler_args *args)
 
 	ctx = &pchgs[port];
 
-	if (ctx->state == PCHG_STATE_CONNECTED
-			&& ctx->battery_percent >= ctx->cfg->full_percent)
+	if (ctx->state == PCHG_STATE_CONNECTED &&
+	    ctx->battery_percent >= ctx->cfg->full_percent)
 		r->state = PCHG_STATE_FULL;
 	else
 		r->state = ctx->state;
@@ -643,7 +656,8 @@ static enum ec_status hc_pchg(struct host_cmd_handler_args *args)
 	r->dropped_host_event_count = ctx->dropped_host_event_count;
 
 	args->response_size = args->version == 1 ?
-			sizeof(struct ec_response_pchg) : sizeof(*r);
+				      sizeof(struct ec_response_pchg) :
+				      sizeof(*r);
 
 	return EC_RES_SUCCESS;
 }
@@ -743,7 +757,7 @@ static enum ec_status hc_pchg_update(struct host_cmd_handler_args *args)
 }
 DECLARE_HOST_COMMAND(EC_CMD_PCHG_UPDATE, hc_pchg_update, EC_VER_MASK(0));
 
-static int cc_pchg(int argc, char **argv)
+static int cc_pchg(int argc, const char **argv)
 {
 	int port;
 	char *end;
@@ -758,11 +772,11 @@ static int cc_pchg(int argc, char **argv)
 	ctx = &pchgs[port];
 
 	if (argc == 2) {
-		ccprintf("P%d STATE_%s EVENT_%s SOC=%d%%\n",
-			 port, _text_state(ctx->state), _text_event(ctx->event),
+		ccprintf("P%d STATE_%s EVENT_%s SOC=%d%%\n", port,
+			 _text_state(ctx->state), _text_event(ctx->event),
 			 ctx->battery_percent);
-		ccprintf("error=0x%x dropped=%u fw_version=0x%x\n",
-			 ctx->error, ctx->dropped_event_count, ctx->fw_version);
+		ccprintf("error=0x%x dropped=%u fw_version=0x%x\n", ctx->error,
+			 ctx->dropped_event_count, ctx->fw_version);
 		return EC_SUCCESS;
 	}
 
diff --git a/common/port80.c b/common/port80.c
index 231181cad8..abead59cd9 100644
--- a/common/port80.c
+++ b/common/port80.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,11 +11,12 @@
 #include "hooks.h"
 #include "host_command.h"
 #include "port80.h"
+#include "printf.h"
 #include "task.h"
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_PORT80, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_PORT80, format, ##args)
 
 #ifdef CONFIG_PORT80_4_BYTE
 typedef uint32_t port80_code_t;
@@ -23,7 +24,7 @@ typedef uint32_t port80_code_t;
 typedef uint16_t port80_code_t;
 #endif
 static port80_code_t history[CONFIG_PORT80_HISTORY_LEN];
-static int writes;    /* Number of port 80 writes so far */
+static int writes; /* Number of port 80 writes so far */
 static uint16_t last_boot; /* Last code from previous boot */
 static int scroll;
 
@@ -39,6 +40,8 @@ DECLARE_DEFERRED(port80_dump_buffer);
 
 void port_80_write(int data)
 {
+	char ts_str[PRINTF_TIMESTAMP_BUF_SIZE];
+
 	/*
 	 * By default print_in_int is disabled if:
 	 * 1. CONFIG_BRINGUP is not defined
@@ -53,15 +56,20 @@ void port_80_write(int data)
 	 * dump the current port80 buffer to EC console. This is to allow
 	 * developers to help debug BIOS progress by tracing port80 messages.
 	 */
-	if (print_in_int)
-		CPRINTF("%c[%pT Port 80: 0x%02x]",
-			scroll ? '\n' : '\r', PRINTF_TIMESTAMP_NOW, data);
+	if (print_in_int) {
+		snprintf_timestamp_now(ts_str, sizeof(ts_str));
+		CPRINTF("%c[%s Port 80: 0x%02x]", scroll ? '\n' : '\r', ts_str,
+			data);
+	}
 
-	hook_call_deferred(&port80_dump_buffer_data, 4 * SECOND);
+	if (!IS_ENABLED(CONFIG_PORT80_QUIET)) {
+		hook_call_deferred(&port80_dump_buffer_data, 4 * SECOND);
+	}
 
 	/* Save current port80 code if system is resetting */
 	if (data == PORT_80_EVENT_RESET && writes) {
-		port80_code_t prev = history[(writes-1) % ARRAY_SIZE(history)];
+		port80_code_t prev =
+			history[(writes - 1) % ARRAY_SIZE(history)];
 
 		/*
 		 * last_boot only reports 8-bit codes.
@@ -127,7 +135,7 @@ static void port80_dump_buffer(void)
 /*****************************************************************************/
 /* Console commands */
 
-static int command_port80(int argc, char **argv)
+static int command_port80(int argc, const char **argv)
 {
 	/*
 	 * 'port80 scroll' toggles whether port 80 output begins with a newline
@@ -154,8 +162,7 @@ static int command_port80(int argc, char **argv)
 	port80_dump_buffer();
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(port80, command_port80,
-			"[scroll | intprint | flush]",
+DECLARE_CONSOLE_COMMAND(port80, command_port80, "[scroll | intprint | flush]",
 			"Print port80 writes or toggle port80 scrolling");
 
 enum ec_status port80_last_boot(struct host_cmd_handler_args *args)
@@ -187,24 +194,23 @@ static enum ec_status port80_command_read(struct host_cmd_handler_args *args)
 	} else if (p->subcmd == EC_PORT80_READ_BUFFER) {
 		/* do not allow bad offset or size */
 		if (offset >= ARRAY_SIZE(history) || entries == 0 ||
-			entries > args->response_max)
+		    entries > args->response_max)
 			return EC_RES_INVALID_PARAM;
 
 		for (i = 0; i < entries; i++) {
-			uint16_t e = history[(i + offset) %
-				ARRAY_SIZE(history)];
+			uint16_t e =
+				history[(i + offset) % ARRAY_SIZE(history)];
 			rsp->data.codes[i] = e;
 		}
 
-		args->response_size = entries*sizeof(uint16_t);
+		args->response_size = entries * sizeof(uint16_t);
 		return EC_RES_SUCCESS;
 	}
 
 	return EC_RES_INVALID_PARAM;
 }
-DECLARE_HOST_COMMAND(EC_CMD_PORT80_READ,
-		port80_command_read,
-		EC_VER_MASK(0) | EC_VER_MASK(1));
+DECLARE_HOST_COMMAND(EC_CMD_PORT80_READ, port80_command_read,
+		     EC_VER_MASK(0) | EC_VER_MASK(1));
 
 static void port80_log_resume(void)
 {
diff --git a/common/power_button.c b/common/power_button.c
index 20c468301c..36d7e510d2 100644
--- a/common/power_button.c
+++ b/common/power_button.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,6 +6,7 @@
 /* Power button module for Chrome EC */
 
 #include "button.h"
+#include "chipset.h"
 #include "common.h"
 #include "console.h"
 #include "gpio.h"
@@ -21,14 +22,14 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_SWITCH, outstr)
-#define CPRINTS(format, args...) cprints(CC_SWITCH, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SWITCH, format, ##args)
 
 /* By default the power button is active low */
 #ifndef CONFIG_POWER_BUTTON_FLAGS
 #define CONFIG_POWER_BUTTON_FLAGS 0
 #endif
 
-static int debounced_power_pressed;	/* Debounced power button state */
+static int debounced_power_pressed; /* Debounced power button state */
 static int simulate_power_pressed;
 static volatile int power_button_is_stable = 1;
 
@@ -41,8 +42,11 @@ static const struct button_config power_button = {
 
 int power_button_signal_asserted(void)
 {
-	return !!(gpio_get_level(power_button.gpio)
-		== (power_button.flags & BUTTON_FLAG_ACTIVE_HIGH) ? 1 : 0);
+	return !!(
+		gpio_get_level(power_button.gpio) ==
+				(power_button.flags & BUTTON_FLAG_ACTIVE_HIGH) ?
+			1 :
+			0);
 }
 
 /**
@@ -93,8 +97,8 @@ int power_button_wait_for_release(int timeout_us)
 		 * the power button is debounced but not changed, or the power
 		 * button has not been debounced.
 		 */
-		task_wait_event(MIN(power_button.debounce_us,
-				    deadline.val - now.val));
+		task_wait_event(
+			MIN(power_button.debounce_us, deadline.val - now.val));
 	}
 
 	CPRINTS("%s released in time", power_button.name);
@@ -132,6 +136,10 @@ DECLARE_HOOK(HOOK_CHIPSET_STARTUP, pb_chipset_startup, HOOK_PRIO_DEFAULT);
 
 static void pb_chipset_shutdown(void)
 {
+	/* Don't set AP_IDLE if shutting down due to power failure. */
+	if (chipset_get_shutdown_reason() == CHIPSET_SHUTDOWN_POWERFAIL)
+		return;
+
 	chip_save_reset_flags(chip_read_reset_flags() | EC_RESET_FLAG_AP_IDLE);
 	system_set_reset_flags(EC_RESET_FLAG_AP_IDLE);
 	CPRINTS("Saved AP_IDLE flag");
@@ -164,8 +172,8 @@ static void power_button_change_deferred(void)
 	debounced_power_pressed = new_pressed;
 	power_button_is_stable = 1;
 
-	CPRINTS("%s %s",
-		power_button.name, new_pressed ? "pressed" : "released");
+	CPRINTS("%s %s", power_button.name,
+		new_pressed ? "pressed" : "released");
 
 	/* Call hooks */
 	hook_notify(HOOK_POWER_BUTTON_CHANGE);
@@ -192,35 +200,38 @@ void power_button_interrupt(enum gpio_signal signal)
 			   power_button.debounce_us);
 }
 
-/*****************************************************************************/
-/* Console commands */
-
-static int command_powerbtn(int argc, char **argv)
+void power_button_simulate_press(unsigned int duration)
 {
-	int ms = 200;  /* Press duration in ms */
-	char *e;
-
-	if (argc > 1) {
-		ms = strtoi(argv[1], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM1;
-	}
-
-	ccprintf("Simulating %d ms %s press.\n", ms, power_button.name);
+	ccprintf("Simulating %d ms %s press.\n", duration, power_button.name);
 	simulate_power_pressed = 1;
 	power_button_is_stable = 0;
 	hook_call_deferred(&power_button_change_deferred_data, 0);
 
-	if (ms > 0)
-		msleep(ms);
+	if (duration > 0)
+		msleep(duration);
 
 	ccprintf("Simulating %s release.\n", power_button.name);
 	simulate_power_pressed = 0;
 	power_button_is_stable = 0;
 	hook_call_deferred(&power_button_change_deferred_data, 0);
+}
+
+/*****************************************************************************/
+/* Console commands */
+
+static int command_powerbtn(int argc, const char **argv)
+{
+	int ms = 200; /* Press duration in ms */
+	char *e;
+
+	if (argc > 1) {
+		ms = strtoi(argv[1], &e, 0);
+		if (*e || ms < 0)
+			return EC_ERROR_PARAM1;
+	}
 
+	power_button_simulate_press(ms);
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(powerbtn, command_powerbtn,
-			"[msec]",
+DECLARE_CONSOLE_COMMAND(powerbtn, command_powerbtn, "[msec]",
 			"Simulate power button press");
diff --git a/common/power_button_x86.c b/common/power_button_x86.c
index fd24f7a75b..efa51530e5 100644
--- a/common/power_button_x86.c
+++ b/common/power_button_x86.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,7 +23,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_SWITCH, outstr)
-#define CPRINTS(format, args...) cprints(CC_SWITCH, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SWITCH, format, ##args)
 
 /*
  * x86 chipsets have a hardware timer on the power button input which causes
@@ -54,14 +54,14 @@
  *    to host    v                      v
  *     @S0   make code             break code
  */
-#define PWRBTN_DELAY_T0    (32 * MSEC)  /* 32ms (PCH requires >16ms) */
-#define PWRBTN_DELAY_T1    (4 * SECOND - PWRBTN_DELAY_T0)  /* 4 secs - t0 */
+#define PWRBTN_DELAY_T0 (32 * MSEC) /* 32ms (PCH requires >16ms) */
+#define PWRBTN_DELAY_T1 (4 * SECOND - PWRBTN_DELAY_T0) /* 4 secs - t0 */
 /*
  * Length of time to stretch initial power button press to give chipset a
  * chance to wake up (~100ms) and react to the press (~16ms).  Also used as
  * pulse length for simulated power button presses when the system is off.
  */
-#define PWRBTN_INITIAL_US  (200 * MSEC)
+#define PWRBTN_INITIAL_US (200 * MSEC)
 
 enum power_button_state {
 	/* Button up; state machine idle */
@@ -92,18 +92,9 @@ enum power_button_state {
 };
 static enum power_button_state pwrbtn_state = PWRBTN_STATE_IDLE;
 
-static const char * const state_names[] = {
-	"idle",
-	"pressed",
-	"t0",
-	"t1",
-	"held",
-	"lid-open",
-	"released",
-	"eat-release",
-	"init-on",
-	"recovery",
-	"was-off",
+static const char *const state_names[] = {
+	"idle",	    "pressed",	   "t0",      "t1",	  "held",    "lid-open",
+	"released", "eat-release", "init-on", "recovery", "was-off",
 };
 
 /*
@@ -139,7 +130,7 @@ static void set_pwrbtn_to_pch(int high, int init)
 	 */
 #ifdef CONFIG_CHARGER
 	if (chipset_in_state(CHIPSET_STATE_ANY_OFF) && !high &&
-	   (charge_want_shutdown() || charge_prevent_power_on(!init))) {
+	    (charge_want_shutdown() || charge_prevent_power_on(!init))) {
 		CPRINTS("PB PCH pwrbtn ignored due to battery level");
 		high = 1;
 	}
@@ -346,8 +337,8 @@ static void state_machine(uint64_t tnow)
 
 		if (!IS_ENABLED(CONFIG_CHARGER) || charge_prevent_power_on(0)) {
 			if (tnow >
-				(tpb_task_start +
-				 CONFIG_POWER_BUTTON_INIT_TIMEOUT * SECOND)) {
+			    (tpb_task_start +
+			     CONFIG_POWER_BUTTON_INIT_TIMEOUT * SECOND)) {
 				pwrbtn_state = PWRBTN_STATE_IDLE;
 				break;
 			}
@@ -366,9 +357,9 @@ static void state_machine(uint64_t tnow)
 #ifdef CONFIG_DELAY_DSW_PWROK_TO_PWRBTN
 		/* Check if power button is ready. If not, we'll come back. */
 		if (get_time().val - get_time_dsw_pwrok() <
-				CONFIG_DSW_PWROK_TO_PWRBTN_US) {
+		    CONFIG_DSW_PWROK_TO_PWRBTN_US) {
 			tnext_state = get_time_dsw_pwrok() +
-					CONFIG_DSW_PWROK_TO_PWRBTN_US;
+				      CONFIG_DSW_PWROK_TO_PWRBTN_US;
 			break;
 		}
 #endif
@@ -444,7 +435,7 @@ void power_button_task(void *u)
 			 * early.)
 			 */
 			CPRINTS("PB task %d = %s, wait %d", pwrbtn_state,
-			state_names[pwrbtn_state], d);
+				state_names[pwrbtn_state], d);
 			task_wait_event(d);
 		}
 	}
@@ -533,7 +524,6 @@ static enum ec_status hc_config_powerbtn_x86(struct host_cmd_handler_args *args)
 DECLARE_HOST_COMMAND(EC_CMD_CONFIG_POWER_BUTTON, hc_config_powerbtn_x86,
 		     EC_VER_MASK(0));
 
-
 /*
  * Currently, the only reason why we disable power button pulse is to allow
  * detachable menu on AP to use power button for selection purpose without
@@ -554,8 +544,8 @@ DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, power_button_pulse_setting_reset,
 DECLARE_HOOK(HOOK_CHIPSET_RESUME, power_button_pulse_setting_reset,
 	     HOOK_PRIO_DEFAULT);
 
-#define POWER_BUTTON_SYSJUMP_TAG		0x5042 /* PB */
-#define POWER_BUTTON_HOOK_VERSION		1
+#define POWER_BUTTON_SYSJUMP_TAG 0x5042 /* PB */
+#define POWER_BUTTON_HOOK_VERSION 1
 
 static void power_button_pulse_setting_restore_state(void)
 {
@@ -574,8 +564,7 @@ DECLARE_HOOK(HOOK_INIT, power_button_pulse_setting_restore_state,
 
 static void power_button_pulse_setting_preserve_state(void)
 {
-	system_add_jump_tag(POWER_BUTTON_SYSJUMP_TAG,
-			    POWER_BUTTON_HOOK_VERSION,
+	system_add_jump_tag(POWER_BUTTON_SYSJUMP_TAG, POWER_BUTTON_HOOK_VERSION,
 			    sizeof(power_button_pulse_enabled),
 			    &power_button_pulse_enabled);
 }
diff --git a/common/printf.c b/common/printf.c
index e302708a9b..d2cc78f5aa 100644
--- a/common/printf.c
+++ b/common/printf.c
@@ -1,10 +1,11 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Printf-like functionality for Chrome EC */
 
+#include "builtin/assert.h"
 #include "console.h"
 #include "printf.h"
 #include "timer.h"
@@ -12,24 +13,7 @@
 
 static const char error_str[] = "ERROR";
 
-#define MAX_FORMAT 1024  /* Maximum chars in a single format field */
-
-#ifndef CONFIG_DEBUG_PRINTF
-static inline int divmod(uint64_t *n, int d)
-{
-	return uint64divmod(n, d);
-}
-
-#else /* CONFIG_DEBUG_PRINTF */
-/* if we are optimizing for size, remove the 64-bit support */
-#define NO_UINT64_SUPPORT
-static inline int divmod(uint32_t *n, int d)
-{
-	int r = *n % d;
-	*n /= d;
-	return r;
-}
-#endif
+#define MAX_FORMAT 1024 /* Maximum chars in a single format field */
 
 /**
  * Convert the lowest nibble of a number to hex
@@ -47,27 +31,118 @@ static int hexdigit(int c)
 }
 
 /* Flags for vfnprintf() flags */
-#define PF_LEFT		BIT(0)  /* Left-justify */
-#define PF_PADZERO	BIT(1)  /* Pad with 0's not spaces */
-#define PF_SIGN		BIT(2)  /* Add sign (+) for a positive number */
+#define PF_LEFT BIT(0) /* Left-justify */
+#define PF_PADZERO BIT(1) /* Pad with 0's not spaces */
+#define PF_SIGN BIT(2) /* Add sign (+) for a positive number */
+#define PF_64BIT BIT(3) /* Number is 64-bit */
+
+test_export_static char *uint64_to_str(char *buf, int buf_len, uint64_t val,
+				       int precision, int base, bool uppercase)
+{
+	int i;
+	char *str;
+
+	if (buf_len <= 1)
+		return NULL;
+
+	if (base <= 1)
+		return NULL;
+
+	/*
+	 * Convert integer to string, starting at end of
+	 * buffer and working backwards.
+	 */
+	str = buf + buf_len - 1;
+	*(str) = '\0';
+
+	/*
+	 * Fixed-point precision must fit in our buffer.
+	 * Leave space for "0." and the terminating null.
+	 */
+	if (precision > buf_len - 3) {
+		precision = buf_len - 3;
+		if (precision < 0)
+			return NULL;
+	}
+
+	/*
+	 * Handle digits to right of decimal for fixed point numbers.
+	 */
+	for (i = 0; i < precision; i++)
+		*(--str) = '0' + uint64divmod(&val, 10);
+	if (precision >= 0)
+		*(--str) = '.';
+
+	if (!val)
+		*(--str) = '0';
+
+	while (val) {
+		int digit;
+
+		if (str <= buf)
+			return NULL;
+
+		digit = uint64divmod(&val, base);
+		if (digit < 10)
+			*(--str) = '0' + digit;
+		else if (uppercase)
+			*(--str) = 'A' + digit - 10;
+		else
+			*(--str) = 'a' + digit - 10;
+	}
+
+	return str;
+}
+
+int snprintf_timestamp_now(char *str, size_t size)
+{
+	return snprintf_timestamp(str, size, get_time().val);
+}
+
+int snprintf_timestamp(char *str, size_t size, uint64_t timestamp)
+{
+	int len;
+	int precision;
+	char *tmp_str;
+	char tmp_buf[PRINTF_TIMESTAMP_BUF_SIZE];
+	int base = 10;
 
-/* Deactivate the PF_64BIT flag is 64-bit support is disabled. */
-#ifdef NO_UINT64_SUPPORT
-#define PF_64BIT	0
-#else
-#define PF_64BIT	BIT(3)  /* Number is 64-bit */
-#endif
+	if (size == 0)
+		return -EC_ERROR_INVAL;
+
+	/* Ensure string has terminating '\0' in error cases. */
+	str[0] = '\0';
+
+	if (IS_ENABLED(CONFIG_CONSOLE_VERBOSE)) {
+		precision = 6;
+	} else {
+		precision = 3;
+		timestamp /= 1000;
+	}
+
+	tmp_str = uint64_to_str(tmp_buf, sizeof(tmp_buf), timestamp, precision,
+				base, false);
+	if (!tmp_str)
+		return -EC_ERROR_OVERFLOW;
+
+	len = strlen(tmp_str);
+	if (len + 1 > size)
+		return -EC_ERROR_OVERFLOW;
+
+	memcpy(str, tmp_str, len + 1);
+
+	return len;
+}
 
 /*
  * Print the buffer as a string of bytes in hex.
  * Returns 0 on success or an error on failure.
  */
-static int print_hex_buffer(int (*addchar)(void *context, int c),
-			    void *context, const char *vstr, int precision,
-			    int pad_width, int flags)
+static int print_hex_buffer(int (*addchar)(void *context, int c), void *context,
+			    const char *vstr, int precision, int pad_width,
+			    int flags)
 
 {
-
 	/*
 	 * Divide pad_width instead of multiplying precision to avoid overflow
 	 * error in the condition. The "/2" and "2*" can be optimized by
@@ -100,6 +175,54 @@ static int print_hex_buffer(int (*addchar)(void *context, int c),
 	return EC_SUCCESS;
 }
 
+struct hex_char_context {
+	struct hex_buffer_params hex_buf_params;
+	char *str;
+	size_t size;
+};
+
+int add_hex_char(void *context, int c)
+{
+	struct hex_char_context *ctx = context;
+
+	if (ctx->size == 0)
+		return EC_ERROR_OVERFLOW;
+
+	*(ctx->str++) = c;
+	ctx->size--;
+
+	return EC_SUCCESS;
+}
+
+size_t hex_str_buf_size(size_t num_bytes)
+{
+	return 2 * num_bytes + 1;
+}
+
+int snprintf_hex_buffer(char *str, size_t size,
+			const struct hex_buffer_params *params)
+{
+	int rv;
+	struct hex_char_context context = {
+		.hex_buf_params = *params,
+		.str = str,
+		/*
+		 * Reserve space for terminating '\0'.
+		 */
+		.size = size - 1,
+	};
+
+	if (size == 0)
+		return -EC_ERROR_INVAL;
+
+	rv = print_hex_buffer(add_hex_char, &context, params->buffer,
+			      params->size, 0, 0);
+
+	*context.str = '\0';
+
+	return (rv == EC_SUCCESS) ? (context.str - str) : -rv;
+}
+
 int vfnprintf(int (*addchar)(void *context, int c), void *context,
 	      const char *format, va_list args)
 {
@@ -215,17 +338,15 @@ int vfnprintf(int (*addchar)(void *context, int c), void *context,
 
 		} else {
 			int base = 10;
-#ifdef NO_UINT64_SUPPORT
-			uint32_t v;
-#else
 			uint64_t v;
-#endif
-			int ptrspec;
+
 			void *ptrval;
 
 			/*
 			 * Handle length:
-			 * %l - DEPRECATED (see below)
+			 * %l - supports 64-bit longs, 32-bit longs are
+			 *      supported with a config flag, see comment
+			 *      below for more details
 			 * %ll - long long
 			 * %z - size_t
 			 */
@@ -240,18 +361,23 @@ int vfnprintf(int (*addchar)(void *context, int c), void *context,
 				}
 
 				/*
-				 * %l on 32-bit systems is deliberately
-				 * deprecated. It was originally used as
-				 * shorthand for 64-bit values. When
+				 * The CONFIG_PRINTF_LONG_IS_32BITS flag is
+				 * required to enable the %l flag on systems
+				 * where it would signify a 32-bit value.
+				 * Otherwise, %l on 32-bit systems is
+				 * deliberately deprecated. %l was originally
+				 * used as shorthand for 64-bit values. When
 				 * compile-time printf format checking was
 				 * enabled, it had to be cleaned up to be
 				 * sizeof(long), which is 32 bits on today's
 				 * ECs. This presents a mismatch which can be
 				 * dangerous if a new-style printf call is
 				 * cherry-picked into an old firmware branch.
-				 * See crbug.com/984041 for more context.
+				 * For more context, see
+				 * https://issuetracker.google.com/issues/172210614
 				 */
-				if (!(flags & PF_64BIT)) {
+				if (!IS_ENABLED(CONFIG_PRINTF_LONG_IS_32BITS) &&
+				    !(flags & PF_64BIT)) {
 					format = error_str;
 					continue;
 				}
@@ -264,74 +390,11 @@ int vfnprintf(int (*addchar)(void *context, int c), void *context,
 
 			if (c == 'p') {
 				c = -1;
-				ptrspec = *format++;
 				ptrval = va_arg(args, void *);
-				/*
-				 * Avoid null pointer dereference for %ph and
-				 * %pb. %pT and %pP can accept null.
-				 */
-				if (ptrval == NULL
-				    && ptrspec != 'T' && ptrspec != 'P')
-					continue;
-				/* %pT - print a timestamp. */
-				if (ptrspec == 'T' &&
-				    !IS_ENABLED(NO_UINT64_SUPPORT) &&
-				    (!IS_ENABLED(CONFIG_ZEPHYR) ||
-				     IS_ENABLED(CONFIG_PLATFORM_EC_TIMER))) {
+				v = (unsigned long)ptrval;
+				base = 16;
+				if (sizeof(unsigned long) == sizeof(uint64_t))
 					flags |= PF_64BIT;
-					if (ptrval == PRINTF_TIMESTAMP_NOW)
-						v = get_time().val;
-					else
-						v = *(uint64_t *)ptrval;
-
-					if (IS_ENABLED(
-						CONFIG_CONSOLE_VERBOSE)) {
-						precision = 6;
-					} else {
-						precision = 3;
-						v /= 1000;
-					}
-
-				} else if (ptrspec == 'h') {
-					/* %ph - Print a hex byte buffer. */
-					struct hex_buffer_params *hexbuf =
-						ptrval;
-					int rc;
-
-					rc = print_hex_buffer(addchar,
-							      context,
-							      hexbuf->buffer,
-							      hexbuf->size,
-							      0,
-							      0);
-
-					if (rc != EC_SUCCESS)
-						return rc;
-
-					continue;
-
-				} else if (ptrspec == 'P') {
-					/* %pP - Print a raw pointer. */
-					v = (unsigned long)ptrval;
-					base = 16;
-					if (sizeof(unsigned long) ==
-					    sizeof(uint64_t))
-						flags |= PF_64BIT;
-
-				} else if (ptrspec == 'b') {
-					/* %pb - Print a binary integer */
-					struct binary_print_params *binary =
-						ptrval;
-
-					v = binary->value;
-					pad_width = binary->count;
-					flags |= PF_PADZERO;
-					base = 2;
-
-				} else {
-					return EC_ERROR_INVAL;
-				}
-
 			} else if (flags & PF_64BIT) {
 				v = va_arg(args, uint64_t);
 			} else {
@@ -339,12 +402,9 @@ int vfnprintf(int (*addchar)(void *context, int c), void *context,
 			}
 
 			switch (c) {
-#ifdef CONFIG_PRINTF_LEGACY_LI_FORMAT
+#ifdef CONFIG_PRINTF_LONG_IS_32BITS
 			case 'i':
-				/* force 32-bit for compatibility */
-				flags &= ~PF_64BIT;
-				/* fall-through */
-#endif /* CONFIG_PRINTF_LEGACY_LI_FORMAT */
+#endif /* CONFIG_PRINTF_LONG_IS_32BITS */
 			case 'd':
 				if (flags & PF_64BIT) {
 					if ((int64_t)v < 0) {
@@ -381,41 +441,9 @@ int vfnprintf(int (*addchar)(void *context, int c), void *context,
 			if (format == error_str)
 				continue; /* Bad format specifier */
 
-			/*
-			 * Convert integer to string, starting at end of
-			 * buffer and working backwards.
-			 */
-			vstr = intbuf + sizeof(intbuf) - 1;
-			*(vstr) = '\0';
-
-			/*
-			 * Fixed-point precision must fit in our buffer.
-			 * Leave space for "0." and the terminating null.
-			 */
-			if (precision > (int)(sizeof(intbuf) - 3))
-				precision = sizeof(intbuf) - 3;
-
-			/*
-			 * Handle digits to right of decimal for fixed point
-			 * numbers.
-			 */
-			for (vlen = 0; vlen < precision; vlen++)
-				*(--vstr) = '0' + divmod(&v, 10);
-			if (precision >= 0)
-				*(--vstr) = '.';
-
-			if (!v)
-				*(--vstr) = '0';
-
-			while (v) {
-				int digit = divmod(&v, base);
-				if (digit < 10)
-					*(--vstr) = '0' + digit;
-				else if (c == 'X')
-					*(--vstr) = 'A' + digit - 10;
-				else
-					*(--vstr) = 'a' + digit - 10;
-			}
+			vstr = uint64_to_str(intbuf, sizeof(intbuf), v,
+					     precision, base, c == 'X');
+			ASSERT(vstr);
 
 			if (sign)
 				*(--vstr) = sign;
@@ -443,7 +471,6 @@ int vfnprintf(int (*addchar)(void *context, int c), void *context,
 			vlen = strnlen(vstr, precision);
 		}
 
-
 		while (vlen < pad_width && !(flags & PF_LEFT)) {
 			if (addchar(context, flags & PF_PADZERO ? '0' : ' '))
 				return EC_ERROR_OVERFLOW;
@@ -462,59 +489,3 @@ int vfnprintf(int (*addchar)(void *context, int c), void *context,
 	/* If we're still here, we consumed all output */
 	return EC_SUCCESS;
 }
-
-/* Context for snprintf() */
-struct snprintf_context {
-	char *str;
-	int size;
-};
-
-/**
- * Add a character to the string context.
- *
- * @param context	Context receiving character
- * @param c		Character to add
- * @return 0 if character added, 1 if character dropped because no space.
- */
-static int snprintf_addchar(void *context, int c)
-{
-	struct snprintf_context *ctx = (struct snprintf_context *)context;
-
-	if (!ctx->size)
-		return 1;
-
-	*(ctx->str++) = c;
-	ctx->size--;
-	return 0;
-}
-
-int crec_snprintf(char *str, size_t size, const char *format, ...)
-{
-	va_list args;
-	int rv;
-
-	va_start(args, format);
-	rv = crec_vsnprintf(str, size, format, args);
-	va_end(args);
-
-	return rv;
-}
-
-int crec_vsnprintf(char *str, size_t size, const char *format, va_list args)
-{
-	struct snprintf_context ctx;
-	int rv;
-
-	if (!str || !format || size <= 0)
-		return -EC_ERROR_INVAL;
-
-	ctx.str = str;
-	ctx.size = size - 1;  /* Reserve space for terminating '\0' */
-
-	rv = vfnprintf(snprintf_addchar, &ctx, format, args);
-
-	/* Terminate string */
-	*ctx.str = '\0';
-
-	return (rv == EC_SUCCESS) ? (ctx.str - str) : -rv;
-}
diff --git a/common/pstore_commands.c b/common/pstore_commands.c
index 469af6a054..89c996379c 100644
--- a/common/pstore_commands.c
+++ b/common/pstore_commands.c
@@ -1,10 +1,11 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Persistent storage commands for Chrome EC */
 
+#include "builtin/assert.h"
 #include "common.h"
 #include "eeprom.h"
 #include "host_command.h"
@@ -23,8 +24,7 @@ pstore_command_get_info(struct host_cmd_handler_args *args)
 	args->response_size = sizeof(*r);
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_PSTORE_INFO,
-		     pstore_command_get_info,
+DECLARE_HOST_COMMAND(EC_CMD_PSTORE_INFO, pstore_command_get_info,
 		     EC_VER_MASK(0));
 
 static enum ec_status pstore_command_read(struct host_cmd_handler_args *args)
@@ -60,9 +60,7 @@ static enum ec_status pstore_command_read(struct host_cmd_handler_args *args)
 	args->response_size = p->size;
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_PSTORE_READ,
-		     pstore_command_read,
-		     EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_PSTORE_READ, pstore_command_read, EC_VER_MASK(0));
 
 static enum ec_status pstore_command_write(struct host_cmd_handler_args *args)
 {
@@ -97,6 +95,4 @@ static enum ec_status pstore_command_write(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_PSTORE_WRITE,
-		     pstore_command_write,
-		     EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_PSTORE_WRITE, pstore_command_write, EC_VER_MASK(0));
diff --git a/common/pwm.c b/common/pwm.c
index a4edfdd5a5..9019a329b4 100644
--- a/common/pwm.c
+++ b/common/pwm.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,9 +13,8 @@
 
 #ifdef CONFIG_PWM
 
-#define PWM_RAW_TO_PERCENT(v) \
-	DIV_ROUND_NEAREST((uint32_t)(v) * 100, UINT16_MAX)
-#define PWM_PERCENT_TO_RAW(v) ((uint32_t)(v) * UINT16_MAX / 100)
+#define PWM_RAW_TO_PERCENT(v) DIV_ROUND_NEAREST((uint32_t)(v)*100, UINT16_MAX)
+#define PWM_PERCENT_TO_RAW(v) ((uint32_t)(v)*UINT16_MAX / 100)
 
 /*
  * Get target channel based on type / index host command parameters.
@@ -71,8 +70,7 @@ host_command_pwm_set_duty(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_DUTY,
-		     host_command_pwm_set_duty,
+DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_DUTY, host_command_pwm_set_duty,
 		     EC_VER_MASK(0));
 
 static enum ec_status
@@ -92,8 +90,7 @@ host_command_pwm_get_duty(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_DUTY,
-		     host_command_pwm_get_duty,
+DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_DUTY, host_command_pwm_get_duty,
 		     EC_VER_MASK(0));
 
 /**
@@ -112,13 +109,13 @@ static void print_channel(enum pwm_channel ch, int max_duty)
 		ccprintf("  %d: disabled\n", ch);
 }
 
-static int cc_pwm_duty(int argc, char **argv)
+static int cc_pwm_duty(int argc, const char **argv)
 {
 	int value = 0;
 	int max_duty = 100;
 	int ch;
 	char *e;
-	char *raw;
+	const char *raw;
 
 	if (argc < 2) {
 		ccprintf("PWM channels:\n");
@@ -153,7 +150,7 @@ static int cc_pwm_duty(int argc, char **argv)
 			ccprintf("Setting channel %d to %d\n", ch, value);
 			pwm_enable(ch, 1);
 			(max_duty == 100) ? pwm_set_duty(ch, value) :
-				pwm_set_raw_duty(ch, value);
+					    pwm_set_raw_duty(ch, value);
 		}
 	}
 
diff --git a/common/pwm_kblight.c b/common/pwm_kblight.c
index 3389023ea3..5748bef700 100644
--- a/common/pwm_kblight.c
+++ b/common/pwm_kblight.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/common/queue.c b/common/queue.c
index 7b083233ad..ebe9d8b63d 100644
--- a/common/queue.c
+++ b/common/queue.c
@@ -1,21 +1,23 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Queue data structure implementation.
  */
+
+#include "builtin/assert.h"
 #include "console.h"
 #include "queue.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ##args)
 
 static void queue_action_null(struct queue_policy const *policy, size_t count)
 {
 }
 
 struct queue_policy const queue_policy_null = {
-	.add    = queue_action_null,
+	.add = queue_action_null,
 	.remove = queue_action_null,
 };
 
@@ -74,17 +76,17 @@ struct queue_chunk queue_get_write_chunk(struct queue const *q, size_t offset)
 {
 	size_t head = q->state->head & q->buffer_units_mask;
 	size_t tail = (q->state->tail + offset) & q->buffer_units_mask;
-	size_t last = (tail < head) ? head :   /* Wrapped        */
-			q->buffer_units;       /* Normal | Empty */
+	size_t last = (tail < head) ? head : /* Wrapped        */
+				      q->buffer_units; /* Normal | Empty */
 
 	/* Make sure that the offset doesn't exceed free space. */
 	if (queue_space(q) <= offset)
-		return ((struct queue_chunk) {
+		return ((struct queue_chunk){
 			.count = 0,
 			.buffer = NULL,
 		});
 
-	return ((struct queue_chunk) {
+	return ((struct queue_chunk){
 		.count = last - tail,
 		.buffer = q->buffer + (tail * q->unit_bytes),
 	});
@@ -95,10 +97,10 @@ struct queue_chunk queue_get_read_chunk(struct queue const *q)
 	size_t head = q->state->head & q->buffer_units_mask;
 	size_t tail = q->state->tail & q->buffer_units_mask;
 	size_t last = (queue_is_empty(q) ? head : /* Empty          */
-		       ((head < tail) ? tail :    /* Normal         */
-			q->buffer_units));        /* Wrapped | Full */
+			       ((head < tail) ? tail : /* Normal         */
+					q->buffer_units)); /* Wrapped | Full */
 
-	return ((struct queue_chunk) {
+	return ((struct queue_chunk){
 		.count = (last - head),
 		.buffer = q->buffer + (head * q->unit_bytes),
 	});
@@ -134,7 +136,7 @@ size_t queue_add_unit(struct queue const *q, const void *src)
 		return 0;
 
 	if (q->unit_bytes == 1)
-		q->buffer[tail] = *((uint8_t *) src);
+		q->buffer[tail] = *((uint8_t *)src);
 	else
 		memcpy(q->buffer + tail * q->unit_bytes, src, q->unit_bytes);
 
@@ -146,46 +148,33 @@ size_t queue_add_units(struct queue const *q, const void *src, size_t count)
 	return queue_add_memcpy(q, src, count, memcpy);
 }
 
-size_t queue_add_memcpy(struct queue const *q,
-			const void *src,
-			size_t count,
-			void *(*memcpy)(void *dest,
-					const void *src,
-					size_t n))
+size_t queue_add_memcpy(struct queue const *q, const void *src, size_t count,
+			void *(*memcpy)(void *dest, const void *src, size_t n))
 {
 	size_t transfer = MIN(count, queue_space(q));
-	size_t tail     = q->state->tail & q->buffer_units_mask;
-	size_t first    = MIN(transfer, q->buffer_units - tail);
+	size_t tail = q->state->tail & q->buffer_units_mask;
+	size_t first = MIN(transfer, q->buffer_units - tail);
 
-	memcpy(q->buffer + tail * q->unit_bytes,
-	       src,
-	       first * q->unit_bytes);
+	memcpy(q->buffer + tail * q->unit_bytes, src, first * q->unit_bytes);
 
 	if (first < transfer)
 		memcpy(q->buffer,
-		       ((uint8_t const *) src) + first * q->unit_bytes,
+		       ((uint8_t const *)src) + first * q->unit_bytes,
 		       (transfer - first) * q->unit_bytes);
 
 	return queue_advance_tail(q, transfer);
 }
 
-static void queue_read_safe(struct queue const *q,
-			    void *dest,
-			    size_t head,
-			    size_t transfer,
-			    void *(*memcpy)(void *dest,
-					    const void *src,
-					    size_t n))
+static void
+queue_read_safe(struct queue const *q, void *dest, size_t head, size_t transfer,
+		void *(*memcpy)(void *dest, const void *src, size_t n))
 {
 	size_t first = MIN(transfer, q->buffer_units - head);
 
-	memcpy(dest,
-	       q->buffer + head * q->unit_bytes,
-	       first * q->unit_bytes);
+	memcpy(dest, q->buffer + head * q->unit_bytes, first * q->unit_bytes);
 
 	if (first < transfer)
-		memcpy(((uint8_t *) dest) + first * q->unit_bytes,
-		       q->buffer,
+		memcpy(((uint8_t *)dest) + first * q->unit_bytes, q->buffer,
 		       (transfer - first) * q->unit_bytes);
 }
 
@@ -197,7 +186,7 @@ size_t queue_remove_unit(struct queue const *q, void *dest)
 		return 0;
 
 	if (q->unit_bytes == 1)
-		*((uint8_t *) dest) = q->buffer[head];
+		*((uint8_t *)dest) = q->buffer[head];
 	else
 		memcpy(dest, q->buffer + head * q->unit_bytes, q->unit_bytes);
 
@@ -209,39 +198,30 @@ size_t queue_remove_units(struct queue const *q, void *dest, size_t count)
 	return queue_remove_memcpy(q, dest, count, memcpy);
 }
 
-size_t queue_remove_memcpy(struct queue const *q,
-			   void *dest,
-			   size_t count,
-			   void *(*memcpy)(void *dest,
-					   const void *src,
+size_t queue_remove_memcpy(struct queue const *q, void *dest, size_t count,
+			   void *(*memcpy)(void *dest, const void *src,
 					   size_t n))
 {
 	size_t transfer = MIN(count, queue_count(q));
-	size_t head     = q->state->head & q->buffer_units_mask;
+	size_t head = q->state->head & q->buffer_units_mask;
 
 	queue_read_safe(q, dest, head, transfer, memcpy);
 
 	return queue_advance_head(q, transfer);
 }
 
-size_t queue_peek_units(struct queue const *q,
-			void *dest,
-			size_t i,
+size_t queue_peek_units(struct queue const *q, void *dest, size_t i,
 			size_t count)
 {
 	return queue_peek_memcpy(q, dest, i, count, memcpy);
 }
 
-size_t queue_peek_memcpy(struct queue const *q,
-			 void *dest,
-			 size_t i,
+size_t queue_peek_memcpy(struct queue const *q, void *dest, size_t i,
 			 size_t count,
-			 void *(*memcpy)(void *dest,
-				const void *src,
-				size_t n))
+			 void *(*memcpy)(void *dest, const void *src, size_t n))
 {
 	size_t available = queue_count(q);
-	size_t transfer  = MIN(count, available - i);
+	size_t transfer = MIN(count, available - i);
 
 	if (i < available) {
 		size_t head = (q->state->head + i) & q->buffer_units_mask;
@@ -258,7 +238,7 @@ void queue_begin(struct queue const *q, struct queue_iterator *it)
 		it->ptr = NULL;
 	else
 		it->ptr = q->buffer + (q->state->head & q->buffer_units_mask) *
-			q->unit_bytes;
+					      q->unit_bytes;
 	it->_state.offset = 0;
 	it->_state.head = q->state->head;
 	it->_state.tail = q->state->tail;
diff --git a/common/queue_policies.c b/common/queue_policies.c
index 090c837fae..6646d49cf4 100644
--- a/common/queue_policies.c
+++ b/common/queue_policies.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -29,14 +29,14 @@ void queue_remove_direct(struct queue_policy const *policy, size_t count)
 
 struct producer const null_producer = {
 	.queue = NULL,
-	.ops   = &((struct producer_ops const) {
-		 .read = NULL,
+	.ops = &((struct producer_ops const){
+		.read = NULL,
 	}),
 };
 
 struct consumer const null_consumer = {
 	.queue = NULL,
-	.ops   = &((struct consumer_ops const) {
+	.ops = &((struct consumer_ops const){
 		.written = NULL,
 	}),
 };
diff --git a/common/regulator.c b/common/regulator.c
index 54d9e87521..5b8da2adc8 100644
--- a/common/regulator.c
+++ b/common/regulator.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,7 @@
 #include "host_command.h"
 #include "regulator.h"
 
-static enum ec_status
-hc_regulator_get_info(struct host_cmd_handler_args *args)
+static enum ec_status hc_regulator_get_info(struct host_cmd_handler_args *args)
 {
 	const struct ec_params_regulator_get_info *p = args->params;
 	struct ec_response_regulator_get_info *r = args->response;
@@ -33,8 +32,7 @@ hc_regulator_get_info(struct host_cmd_handler_args *args)
 DECLARE_HOST_COMMAND(EC_CMD_REGULATOR_GET_INFO, hc_regulator_get_info,
 		     EC_VER_MASK(0));
 
-static enum ec_status
-hc_regulator_enable(struct host_cmd_handler_args *args)
+static enum ec_status hc_regulator_enable(struct host_cmd_handler_args *args)
 {
 	const struct ec_params_regulator_enable *p = args->params;
 	int rv;
diff --git a/common/rgb_keyboard.c b/common/rgb_keyboard.c
index 815e4a3435..5b5b6c6cf3 100644
--- a/common/rgb_keyboard.c
+++ b/common/rgb_keyboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,7 +24,7 @@
 #define CPRINTS(fmt, args...) cprints(CC_RGBKBD, "RGBKBD: " fmt, ##args)
 
 test_export_static enum ec_rgbkbd_demo demo =
-#if   defined(CONFIG_RGBKBD_DEMO_FLOW)
+#if defined(CONFIG_RGBKBD_DEMO_FLOW)
 	EC_RGBKBD_DEMO_FLOW;
 #elif defined(CONFIG_RGBKBD_DEMO_DOT)
 	EC_RGBKBD_DEMO_DOT;
@@ -35,15 +35,14 @@ test_export_static enum ec_rgbkbd_demo demo =
 const int default_demo_interval_ms = 250;
 test_export_static int demo_interval_ms = -1;
 
-test_export_static
-uint8_t rgbkbd_table[EC_RGBKBD_MAX_KEY_COUNT];
+test_export_static uint8_t rgbkbd_table[EC_RGBKBD_MAX_KEY_COUNT];
 
 static enum rgbkbd_state rgbkbd_state;
 
 const struct rgbkbd_init rgbkbd_init_default = {
 	.gcc = RGBKBD_MAX_GCC_LEVEL / 2,
 	.scale = { RGBKBD_MAX_SCALE, RGBKBD_MAX_SCALE, RGBKBD_MAX_SCALE },
-	.color = { .r = 0xff, .g = 0xff, .b = 0xff },  /* white */
+	.color = { .r = 0xff, .g = 0xff, .b = 0xff }, /* white */
 };
 
 const struct rgbkbd_init *rgbkbd_init_setting = &rgbkbd_init_default;
@@ -88,8 +87,8 @@ static int set_color_single(struct rgb_s color, int x, int y)
 	rv = ctx->cfg->drv->set_color(ctx, offset, &ctx->buf[offset], 1);
 
 	CPRINTS("%set (%d,%d) to color=(%d,%d,%d) grid=%u offset=%u (%d)",
-		rv ? "Failed to s" : "S",
-		x, y, color.r, color.g, color.b, grid, offset, rv);
+		rv ? "Failed to s" : "S", x, y, color.r, color.g, color.b, grid,
+		offset, rv);
 
 	return rv;
 }
@@ -214,14 +213,13 @@ static void rgbkbd_demo_run(enum ec_rgbkbd_demo id)
 	}
 }
 
-test_export_static
-void rgbkbd_init_lookup_table(void)
+test_export_static void rgbkbd_init_lookup_table(void)
 {
 	bool add = true;
 	int i, k = 0;
 
 	if (rgbkbd_map[0] != RGBKBD_DELM ||
-			rgbkbd_map[rgbkbd_map_size - 1] != RGBKBD_DELM) {
+	    rgbkbd_map[rgbkbd_map_size - 1] != RGBKBD_DELM) {
 		CPRINTS("Invalid Key-LED map");
 		return;
 	}
@@ -267,8 +265,8 @@ static int rgbkbd_set_global_brightness(uint8_t gcc)
 
 		e = ctx->cfg->drv->set_gcc(ctx, gcc);
 		if (e) {
-			CPRINTS("Failed to set GCC to %u for grid=%d (%d)",
-				gcc, grid, e);
+			CPRINTS("Failed to set GCC to %u for grid=%d (%d)", gcc,
+				grid, e);
 			rv = e;
 			continue;
 		}
@@ -356,8 +354,8 @@ static int rgbkbd_init(void)
 
 		e = ctx->cfg->drv->set_gcc(ctx, gcc);
 		if (e) {
-			CPRINTS("Failed to set GCC to %u for grid=%d (%d)",
-				gcc, i, e);
+			CPRINTS("Failed to set GCC to %u for grid=%d (%d)", gcc,
+				i, e);
 			rv = e;
 			continue;
 		}
@@ -423,8 +421,8 @@ static int rgbkbd_enable(int enable)
 	}
 
 	if (rv == EC_SUCCESS) {
-		rgbkbd_state = enable ?
-				RGBKBD_STATE_ENABLED : RGBKBD_STATE_DISABLED;
+		rgbkbd_state = enable ? RGBKBD_STATE_ENABLED :
+					RGBKBD_STATE_DISABLED;
 	}
 
 	/* Return EC_SUCCESS or the last error. */
@@ -518,8 +516,8 @@ static enum ec_status hc_rgbkbd_set_color(struct host_cmd_handler_args *args)
 			if (led.u8 == RGBKBD_DELM)
 				/* Reached end of the group. */
 				break;
-			if (set_color_single(p->color[i],
-					     led.coord.x, led.coord.y))
+			if (set_color_single(p->color[i], led.coord.x,
+					     led.coord.y))
 				return EC_RES_ERROR;
 		} while (led.u8 != RGBKBD_DELM);
 	}
@@ -532,8 +530,11 @@ DECLARE_HOST_COMMAND(EC_CMD_RGBKBD_SET_COLOR, hc_rgbkbd_set_color,
 static enum ec_status hc_rgbkbd(struct host_cmd_handler_args *args)
 {
 	const struct ec_params_rgbkbd *p = args->params;
+	struct ec_response_rgbkbd *r = args->response;
 	enum ec_status rv = EC_RES_SUCCESS;
 
+	args->response_size = sizeof(*r);
+
 	if (rgbkbd_late_init())
 		return EC_RES_ERROR;
 
@@ -550,6 +551,9 @@ static enum ec_status hc_rgbkbd(struct host_cmd_handler_args *args)
 		if (rgbkbd_set_scale(p->set_scale.scale, p->set_scale.key))
 			rv = EC_RES_ERROR;
 		break;
+	case EC_RGBKBD_SUBCMD_GET_CONFIG:
+		r->rgbkbd_type = rgbkbd_type;
+		break;
 	default:
 		rv = EC_RES_INVALID_PARAM;
 		break;
@@ -575,7 +579,7 @@ static int int_to_rgb(const char *code, struct rgb_s *rgb)
 	return EC_SUCCESS;
 }
 
-test_export_static int cc_rgb(int argc, char **argv)
+test_export_static int cc_rgb(int argc, const char **argv)
 {
 	char *end, *comma;
 	struct rgb_s rgb, scale;
@@ -606,19 +610,19 @@ test_export_static int cc_rgb(int argc, char **argv)
 
 		if (y < 0) {
 			/* Set all LEDs on column x. */
-			ccprintf("Set column %d to 0x%02x%02x%02x\n",
-				 x, rgb.r, rgb.g, rgb.b);
+			ccprintf("Set column %d to 0x%02x%02x%02x\n", x, rgb.r,
+				 rgb.g, rgb.b);
 			for (i = 0; i < rgbkbd_vsize; i++)
 				rv = set_color_single(rgb, x, i);
 		} else if (x < 0) {
 			/* Set all LEDs on row y. */
-			ccprintf("Set row %d to 0x%02x%02x%02x\n",
-				 y, rgb.r, rgb.g, rgb.b);
+			ccprintf("Set row %d to 0x%02x%02x%02x\n", y, rgb.r,
+				 rgb.g, rgb.b);
 			for (i = 0; i < rgbkbd_hsize; i++)
 				rv = set_color_single(rgb, i, y);
 		} else {
-			ccprintf("Set (%d,%d) to 0x%02x%02x%02x\n",
-				 x, y, rgb.r, rgb.g, rgb.b);
+			ccprintf("Set (%d,%d) to 0x%02x%02x%02x\n", x, y, rgb.r,
+				 rgb.g, rgb.b);
 			rv = set_color_single(rgb, x, y);
 		}
 	} else if (!strcasecmp(argv[1], "all")) {
@@ -680,6 +684,5 @@ DECLARE_CONSOLE_COMMAND(rgb, cc_rgb,
 			"4. rgb demo <id>\n"
 			"5. rgb reset/enable/disable/red\n"
 			"6. rgb scale <24-bit RGB scale>\n",
-			"Control RGB keyboard"
-			);
+			"Control RGB keyboard");
 #endif
diff --git a/common/rollback.c b/common/rollback.c
index 984058c49a..7aaba72ebb 100644
--- a/common/rollback.c
+++ b/common/rollback.c
@@ -1,10 +1,11 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Rollback protection logic. */
 
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
 #ifdef CONFIG_LIBCRYPTOC
@@ -25,7 +26,7 @@
 #include "util.h"
 
 /* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 /* Number of rollback regions */
 #define ROLLBACK_REGIONS 2
@@ -188,12 +189,12 @@ failed:
 #ifdef CONFIG_ROLLBACK_UPDATE
 
 #ifdef CONFIG_ROLLBACK_SECRET_SIZE
-static int add_entropy(uint8_t *dst, const uint8_t *src,
-		       const uint8_t *add, unsigned int add_len)
+static int add_entropy(uint8_t *dst, const uint8_t *src, const uint8_t *add,
+		       unsigned int add_len)
 {
 	int ret = 0;
 #ifdef CONFIG_SHA256
-BUILD_ASSERT(SHA256_DIGEST_SIZE == CONFIG_ROLLBACK_SECRET_SIZE);
+	BUILD_ASSERT(SHA256_DIGEST_SIZE == CONFIG_ROLLBACK_SECRET_SIZE);
 	struct sha256_ctx ctx;
 	uint8_t *hash;
 #ifdef CONFIG_ROLLBACK_SECRET_LOCAL_ENTROPY_SIZE
@@ -240,16 +241,16 @@ failed:
  *
  * @return EC_SUCCESS on success, EC_ERROR_* on error.
  */
-static int rollback_update(int32_t next_min_version,
-			   const uint8_t *entropy, unsigned int length)
+static int rollback_update(int32_t next_min_version, const uint8_t *entropy,
+			   unsigned int length)
 {
 	/*
 	 * When doing flash_write operation, the data needs to be in blocks
 	 * of CONFIG_FLASH_WRITE_SIZE, pad rollback_data as required.
 	 */
 	uint8_t block[CONFIG_FLASH_WRITE_SIZE *
-		DIV_ROUND_UP(sizeof(struct rollback_data),
-			CONFIG_FLASH_WRITE_SIZE)];
+		      DIV_ROUND_UP(sizeof(struct rollback_data),
+				   CONFIG_FLASH_WRITE_SIZE)];
 	struct rollback_data *data = (struct rollback_data *)block;
 	BUILD_ASSERT(sizeof(block) >= sizeof(*data));
 	int erase_size, offset, region, ret;
@@ -260,7 +261,7 @@ static int rollback_update(int32_t next_min_version,
 	}
 
 	/* Initialize the rest of the block. */
-	memset(&block[sizeof(*data)], 0xff, sizeof(block)-sizeof(*data));
+	memset(&block[sizeof(*data)], 0xff, sizeof(block) - sizeof(*data));
 
 	region = get_latest_rollback(data);
 
@@ -349,7 +350,7 @@ int rollback_add_entropy(const uint8_t *data, unsigned int len)
 	return rollback_update(-1, data, len);
 }
 
-static int command_rollback_update(int argc, char **argv)
+static int command_rollback_update(int argc, const char **argv)
 {
 	int32_t min_version;
 	char *e;
@@ -364,12 +365,11 @@ static int command_rollback_update(int argc, char **argv)
 
 	return rollback_update_version(min_version);
 }
-DECLARE_CONSOLE_COMMAND(rollbackupdate, command_rollback_update,
-			"min_version",
+DECLARE_CONSOLE_COMMAND(rollbackupdate, command_rollback_update, "min_version",
 			"Update rollback info");
 
 #ifdef CONFIG_ROLLBACK_SECRET_SIZE
-static int command_rollback_add_entropy(int argc, char **argv)
+static int command_rollback_add_entropy(int argc, const char **argv)
 {
 	int len;
 
@@ -380,8 +380,7 @@ static int command_rollback_add_entropy(int argc, char **argv)
 
 	return rollback_add_entropy(argv[1], len);
 }
-DECLARE_CONSOLE_COMMAND(rollbackaddent, command_rollback_add_entropy,
-			"data",
+DECLARE_CONSOLE_COMMAND(rollbackaddent, command_rollback_add_entropy, "data",
 			"Add entropy to rollback block");
 
 #ifdef CONFIG_RNG
@@ -400,9 +399,9 @@ static void add_entropy_deferred(void)
 	if (add_entropy_action == ADD_ENTROPY_RESET_ASYNC)
 		repeat = ROLLBACK_REGIONS;
 
-	init_trng();
+	trng_init();
 	do {
-		rand_bytes(rand, sizeof(rand));
+		trng_rand_bytes(rand, sizeof(rand));
 		if (rollback_add_entropy(rand, sizeof(rand)) != EC_SUCCESS) {
 			add_entropy_rv = EC_RES_ERROR;
 			goto out;
@@ -411,7 +410,7 @@ static void add_entropy_deferred(void)
 
 	add_entropy_rv = EC_RES_SUCCESS;
 out:
-	exit_trng();
+	trng_exit();
 }
 DECLARE_DEFERRED(add_entropy_deferred);
 
@@ -438,14 +437,13 @@ hc_rollback_add_entropy(struct host_cmd_handler_args *args)
 
 	return EC_RES_INVALID_PARAM;
 }
-DECLARE_HOST_COMMAND(EC_CMD_ADD_ENTROPY,
-		     hc_rollback_add_entropy,
+DECLARE_HOST_COMMAND(EC_CMD_ADD_ENTROPY, hc_rollback_add_entropy,
 		     EC_VER_MASK(0));
 #endif /* CONFIG_RNG */
 #endif /* CONFIG_ROLLBACK_SECRET_SIZE */
 #endif /* CONFIG_ROLLBACK_UPDATE */
 
-static int command_rollback_info(int argc, char **argv)
+static int command_rollback_info(int argc, const char **argv)
 {
 	int ret = EC_ERROR_UNKNOWN;
 	int region, min_region;
@@ -467,14 +465,13 @@ static int command_rollback_info(int argc, char **argv)
 		if (ret)
 			goto failed;
 
-		ccprintf("rollback %d: %08x %08x %08x",
-			region, data.id, data.rollback_min_version,
-			data.cookie);
+		ccprintf("rollback %d: %08x %08x %08x", region, data.id,
+			 data.rollback_min_version, data.cookie);
 #ifdef CONFIG_ROLLBACK_SECRET_SIZE
 		if (!system_is_locked()) {
 			/* If system is unlocked, show some of the secret. */
 			ccprintf(" [%02x..%02x]", data.secret[0],
-				data.secret[CONFIG_ROLLBACK_SECRET_SIZE-1]);
+				 data.secret[CONFIG_ROLLBACK_SECRET_SIZE - 1]);
 		}
 #endif
 		if (min_region == region)
@@ -487,8 +484,7 @@ failed:
 	clear_rollback(&data);
 	return ret;
 }
-DECLARE_SAFE_CONSOLE_COMMAND(rollbackinfo, command_rollback_info,
-			     NULL,
+DECLARE_SAFE_CONSOLE_COMMAND(rollbackinfo, command_rollback_info, NULL,
 			     "Print rollback info");
 
 static enum ec_status
@@ -515,6 +511,5 @@ failed:
 	clear_rollback(&data);
 	return ret;
 }
-DECLARE_HOST_COMMAND(EC_CMD_ROLLBACK_INFO,
-		     host_command_rollback_info,
+DECLARE_HOST_COMMAND(EC_CMD_ROLLBACK_INFO, host_command_rollback_info,
 		     EC_VER_MASK(0));
diff --git a/common/rollback_private.h b/common/rollback_private.h
index c757882f4f..1dbbd4f430 100644
--- a/common/rollback_private.h
+++ b/common/rollback_private.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/common/rsa.c b/common/rsa.c
index 10f0afa4b4..4df6fc136a 100644
--- a/common/rsa.c
+++ b/common/rsa.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -39,16 +39,14 @@ static int ge_mod(const struct rsa_public_key *key, const uint32_t *a)
 		if (a[i] > key->n[i])
 			return 1;
 	}
-	return 1;  /* equal */
+	return 1; /* equal */
 }
 
 /**
  * Montgomery c[] += a * b[] / R % mod
  */
-static void mont_mul_add(const struct rsa_public_key *key,
-			 uint32_t *c,
-			 const uint32_t a,
-			 const uint32_t *b)
+static void mont_mul_add(const struct rsa_public_key *key, uint32_t *c,
+			 const uint32_t a, const uint32_t *b)
 {
 	uint64_t A = mula32(a, b[0], c[0]);
 	uint32_t d0 = (uint32_t)A * key->n0inv;
@@ -73,9 +71,8 @@ static void mont_mul_add(const struct rsa_public_key *key,
 /**
  * Montgomery c[] += 0 * b[] / R % mod
  */
-static void mont_mul_add_0(const struct rsa_public_key *key,
-			 uint32_t *c,
-			 const uint32_t *b)
+static void mont_mul_add_0(const struct rsa_public_key *key, uint32_t *c,
+			   const uint32_t *b)
 {
 	uint32_t d0 = c[0] * key->n0inv;
 	uint64_t B = mula32(d0, key->n[0], c[0]);
@@ -90,8 +87,7 @@ static void mont_mul_add_0(const struct rsa_public_key *key,
 }
 
 /* Montgomery c[] = a[] * 1 / R % key. */
-static void mont_mul_1(const struct rsa_public_key *key,
-		       uint32_t *c,
+static void mont_mul_1(const struct rsa_public_key *key, uint32_t *c,
 		       const uint32_t *a)
 {
 	int i;
@@ -108,10 +104,8 @@ static void mont_mul_1(const struct rsa_public_key *key,
 /**
  * Montgomery c[] = a[] * b[] / R % mod
  */
-static void mont_mul(const struct rsa_public_key *key,
-		     uint32_t *c,
-		     const uint32_t *a,
-		     const uint32_t *b)
+static void mont_mul(const struct rsa_public_key *key, uint32_t *c,
+		     const uint32_t *a, const uint32_t *b)
 {
 	uint32_t i;
 	for (i = 0; i < RSANUMWORDS; ++i)
@@ -136,21 +130,20 @@ static void mod_pow(const struct rsa_public_key *key, uint8_t *inout,
 	uint32_t *a = workbuf32;
 	uint32_t *a_r = a + RSANUMWORDS;
 	uint32_t *aa_r = a_r + RSANUMWORDS;
-	uint32_t *aaa = aa_r;  /* Re-use location. */
+	uint32_t *aaa = aa_r; /* Re-use location. */
 	int i;
 
 	/* Convert from big endian byte array to little endian word array. */
 	for (i = 0; i < RSANUMWORDS; ++i) {
-		uint32_t tmp =
-			(inout[((RSANUMWORDS - 1 - i) * 4) + 0] << 24) |
-			(inout[((RSANUMWORDS - 1 - i) * 4) + 1] << 16) |
-			(inout[((RSANUMWORDS - 1 - i) * 4) + 2] << 8) |
-			(inout[((RSANUMWORDS - 1 - i) * 4) + 3] << 0);
+		uint32_t tmp = (inout[((RSANUMWORDS - 1 - i) * 4) + 0] << 24) |
+			       (inout[((RSANUMWORDS - 1 - i) * 4) + 1] << 16) |
+			       (inout[((RSANUMWORDS - 1 - i) * 4) + 2] << 8) |
+			       (inout[((RSANUMWORDS - 1 - i) * 4) + 3] << 0);
 		a[i] = tmp;
 	}
 
 	/* TODO(drinkcat): This operation could be precomputed to save time. */
-	mont_mul(key, a_r, a, key->rr);  /* a_r = a * RR / R mod M */
+	mont_mul(key, a_r, a, key->rr); /* a_r = a * RR / R mod M */
 #ifdef CONFIG_RSA_EXPONENT_3
 	mont_mul(key, aa_r, a_r, a_r);
 	mont_mul(key, a, aa_r, a_r);
@@ -159,9 +152,10 @@ static void mod_pow(const struct rsa_public_key *key, uint8_t *inout,
 	/* Exponent 65537 */
 	for (i = 0; i < 16; i += 2) {
 		mont_mul(key, aa_r, a_r, a_r); /* aa_r = a_r * a_r / R mod M */
-		mont_mul(key, a_r, aa_r, aa_r);/* a_r = aa_r * aa_r / R mod M */
+		mont_mul(key, a_r, aa_r, aa_r); /* a_r = aa_r * aa_r / R mod M
+						 */
 	}
-	mont_mul(key, aaa, a_r, a);  /* aaa = a_r * a / R mod M */
+	mont_mul(key, aaa, a_r, a); /* aaa = a_r * a / R mod M */
 #endif
 
 	/* Make sure aaa < mod; aaa is at most 1x mod too large. */
@@ -173,8 +167,8 @@ static void mod_pow(const struct rsa_public_key *key, uint8_t *inout,
 		uint32_t tmp = aaa[i];
 		*inout++ = (uint8_t)(tmp >> 24);
 		*inout++ = (uint8_t)(tmp >> 16);
-		*inout++ = (uint8_t)(tmp >>  8);
-		*inout++ = (uint8_t)(tmp >>  0);
+		*inout++ = (uint8_t)(tmp >> 8);
+		*inout++ = (uint8_t)(tmp >> 0);
 	}
 }
 
@@ -192,11 +186,9 @@ static void mod_pow(const struct rsa_public_key *key, uint8_t *inout,
  *
  * PS: octet string consisting of {Length(RSA Key) - Length(T) - 3} 0xFF
  */
-static const uint8_t sha256_tail[] = {
-	0x00, 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60,
-	0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01,
-	0x05, 0x00, 0x04, 0x20
-};
+static const uint8_t sha256_tail[] = { 0x00, 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09,
+				       0x60, 0x86, 0x48, 0x01, 0x65, 0x03, 0x04,
+				       0x02, 0x01, 0x05, 0x00, 0x04, 0x20 };
 
 #define PKCS_PAD_SIZE (RSANUMBYTES - SHA256_DIGEST_SIZE)
 
@@ -255,5 +247,5 @@ int rsa_verify(const struct rsa_public_key *key, const uint8_t *signature,
 	if (memcmp(buf + PKCS_PAD_SIZE, sha, SHA256_DIGEST_SIZE) != 0)
 		return 0;
 
-	return 1;  /* All checked out OK. */
+	return 1; /* All checked out OK. */
 }
diff --git a/common/rtc.c b/common/rtc.c
index 670e86d707..e4292e9762 100644
--- a/common/rtc.c
+++ b/common/rtc.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,9 +8,8 @@
 
 #include "rtc.h"
 
-static uint16_t days_since_year_start[12] = {
-	0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334
-};
+static uint16_t days_since_year_start[12] = { 0,   31,	59,  90,  120, 151,
+					      181, 212, 243, 273, 304, 334 };
 
 /* Conversion between calendar date and seconds eclapsed since 1970-01-01 */
 uint32_t date_to_sec(struct calendar_date time)
@@ -25,8 +24,8 @@ uint32_t date_to_sec(struct calendar_date time)
 	}
 
 	sec += (days_since_year_start[time.month - 1] +
-		(IS_LEAP_YEAR(time.year) && time.month > 2) +
-		(time.day - 1)) * SECS_PER_DAY;
+		(IS_LEAP_YEAR(time.year) && time.month > 2) + (time.day - 1)) *
+	       SECS_PER_DAY;
 
 	/* add the accumulated time in seconds from 1970 to 2000 */
 	return sec + SECS_TILL_YEAR_2K;
@@ -55,7 +54,8 @@ struct calendar_date sec_to_date(uint32_t sec)
 	}
 	for (i = 1; i < 12; i++) {
 		if (days_since_year_start[i] +
-		    (IS_LEAP_YEAR(time.year) && (i >= 2)) >= day_tmp)
+			    (IS_LEAP_YEAR(time.year) && (i >= 2)) >=
+		    day_tmp)
 			break;
 	}
 	time.month = i;
diff --git a/common/rwsig.c b/common/rwsig.c
index 676c66d79b..1ea6d6923a 100644
--- a/common/rwsig.c
+++ b/common/rwsig.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,18 +25,17 @@
 #include "vboot.h"
 
 /* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 #if !defined(CONFIG_MAPPED_STORAGE)
 #error rwsig implementation assumes mem-mapped storage.
 #endif
 
 /* RW firmware reset vector */
-static uint32_t * const rw_rst =
+static uint32_t *const rw_rst =
 	(uint32_t *)(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RW_MEM_OFF + 4);
 
-
 void rwsig_jump_now(void)
 {
 	/* Protect all flash before jumping to RW. */
@@ -74,8 +73,8 @@ void rwsig_jump_now(void)
  * Check that memory between rwdata[start] and rwdata[len-1] is filled
  * with ones. data, start and len must be aligned on 4-byte boundary.
  */
-static int check_padding(const uint8_t *data,
-			 unsigned int start, unsigned int len)
+static int check_padding(const uint8_t *data, unsigned int start,
+			 unsigned int len)
 {
 	unsigned int i;
 	const uint32_t *data32 = (const uint32_t *)data;
@@ -83,7 +82,7 @@ static int check_padding(const uint8_t *data,
 	if ((start % 4) != 0 || (len % 4) != 0)
 		return 0;
 
-	for (i = start/4; i < len/4; i++) {
+	for (i = start / 4; i < len / 4; i++) {
 		if (data32[i] != 0xffffffff)
 			return 0;
 	}
@@ -99,8 +98,8 @@ int rwsig_check_signature(void)
 	const uint8_t *sig;
 	uint8_t *hash;
 	uint32_t *rsa_workbuf = NULL;
-	const uint8_t *rwdata = (uint8_t *)CONFIG_PROGRAM_MEMORY_BASE
-					+ CONFIG_RW_MEM_OFF;
+	const uint8_t *rwdata =
+		(uint8_t *)CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RW_MEM_OFF;
 	int good = 0;
 
 	unsigned int rwlen;
@@ -125,8 +124,8 @@ int rwsig_check_signature(void)
 
 	if (rw_rollback_version < 0 || min_rollback_version < 0 ||
 	    rw_rollback_version < min_rollback_version) {
-		CPRINTS("Rollback error (%d < %d)",
-			rw_rollback_version, min_rollback_version);
+		CPRINTS("Rollback error (%d < %d)", rw_rollback_version,
+			min_rollback_version);
 		goto out;
 	}
 #endif
@@ -152,8 +151,8 @@ int rwsig_check_signature(void)
 		goto out;
 	}
 
-	key = (const struct rsa_public_key *)
-		((const uint8_t *)vb21_key + vb21_key->key_offset);
+	key = (const struct rsa_public_key *)((const uint8_t *)vb21_key +
+					      vb21_key->key_offset);
 
 	/*
 	 * TODO(crbug.com/690773): We could verify other parameters such
@@ -179,7 +178,7 @@ int rwsig_check_signature(void)
 	 * Check that unverified RW region is actually filled with ones.
 	 */
 	good = check_padding(rwdata, rwlen,
-			CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE);
+			     CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE);
 	if (!good) {
 		CPRINTS("Invalid padding.");
 		goto out;
@@ -207,11 +206,10 @@ int rwsig_check_signature(void)
 	 */
 	if (rw_rollback_version != min_rollback_version
 #ifdef CONFIG_FLASH_PROTECT_RW
-		&& ((!system_is_locked() ||
-				crec_flash_get_protect() &
-				EC_FLASH_PROTECT_RW_NOW))
+	    && ((!system_is_locked() ||
+		 crec_flash_get_protect() & EC_FLASH_PROTECT_RW_NOW))
 #endif
-			) {
+	) {
 		/*
 		 * This will fail if the rollback block is protected (RW image
 		 * will unprotect that block later on).
@@ -219,8 +217,7 @@ int rwsig_check_signature(void)
 		int ret = rollback_update_version(rw_rollback_version);
 
 		if (ret == 0) {
-			CPRINTS("Rollback updated to %d",
-				rw_rollback_version);
+			CPRINTS("Rollback updated to %d", rw_rollback_version);
 		} else if (ret != EC_ERROR_ACCESS_DENIED) {
 			CPRINTS("Rollback update error %d", ret);
 			good = 0;
@@ -315,9 +312,7 @@ static enum ec_status rwsig_cmd_action(struct host_cmd_handler_args *args)
 	args->response_size = 0;
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_RWSIG_ACTION,
-		     rwsig_cmd_action,
-		     EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_RWSIG_ACTION, rwsig_cmd_action, EC_VER_MASK(0));
 
 #else /* !HAS_TASK_RWSIG */
 static enum ec_status rwsig_cmd_check_status(struct host_cmd_handler_args *args)
@@ -330,7 +325,6 @@ static enum ec_status rwsig_cmd_check_status(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_RWSIG_CHECK_STATUS,
-		     rwsig_cmd_check_status,
+DECLARE_HOST_COMMAND(EC_CMD_RWSIG_CHECK_STATUS, rwsig_cmd_check_status,
 		     EC_VER_MASK(0));
 #endif
diff --git a/common/sha256.c b/common/sha256.c
index 8c0778c3e6..2826f6c68d 120000..100644
--- a/common/sha256.c
+++ b/common/sha256.c
@@ -1 +1,296 @@
-../third_party/sha2//sha256.c
\ No newline at end of file
+/* SHA-256 and SHA-512 implementation based on code by Oliver Gay
+ * <olivier.gay@a3.epfl.ch> under a BSD-style license. See below.
+ */
+
+/*
+ * FIPS 180-2 SHA-224/256/384/512 implementation
+ * Last update: 02/02/2007
+ * Issue date:  04/30/2005
+ *
+ * Copyright (C) 2005, 2007 Olivier Gay <olivier.gay@a3.epfl.ch>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the project nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "builtin/assert.h"
+#include "sha256.h"
+#include "util.h"
+
+#define SHFR(x, n) (x >> n)
+#define ROTR(x, n) ((x >> n) | (x << ((sizeof(x) << 3) - n)))
+#define ROTL(x, n) ((x << n) | (x >> ((sizeof(x) << 3) - n)))
+#define CH(x, y, z) ((x & y) ^ (~x & z))
+#define MAJ(x, y, z) ((x & y) ^ (x & z) ^ (y & z))
+
+#define SHA256_F1(x) (ROTR(x, 2) ^ ROTR(x, 13) ^ ROTR(x, 22))
+#define SHA256_F2(x) (ROTR(x, 6) ^ ROTR(x, 11) ^ ROTR(x, 25))
+#define SHA256_F3(x) (ROTR(x, 7) ^ ROTR(x, 18) ^ SHFR(x, 3))
+#define SHA256_F4(x) (ROTR(x, 17) ^ ROTR(x, 19) ^ SHFR(x, 10))
+
+#define UNPACK32(x, str)                             \
+	{                                            \
+		*((str) + 3) = (uint8_t)((x));       \
+		*((str) + 2) = (uint8_t)((x) >> 8);  \
+		*((str) + 1) = (uint8_t)((x) >> 16); \
+		*((str) + 0) = (uint8_t)((x) >> 24); \
+	}
+
+#define PACK32(str, x)                                    \
+	{                                                 \
+		*(x) = ((uint32_t) * ((str) + 3)) |       \
+		       ((uint32_t) * ((str) + 2) << 8) |  \
+		       ((uint32_t) * ((str) + 1) << 16) | \
+		       ((uint32_t) * ((str) + 0) << 24);  \
+	}
+
+/* Macros used for loops unrolling */
+
+#define SHA256_SCR(i)                                                          \
+	{                                                                      \
+		w[i] = SHA256_F4(w[i - 2]) + w[i - 7] + SHA256_F3(w[i - 15]) + \
+		       w[i - 16];                                              \
+	}
+
+#define SHA256_EXP(a, b, c, d, e, f, g, h, j)                             \
+	{                                                                 \
+		t1 = wv[h] + SHA256_F2(wv[e]) + CH(wv[e], wv[f], wv[g]) + \
+		     sha256_k[j] + w[j];                                  \
+		t2 = SHA256_F1(wv[a]) + MAJ(wv[a], wv[b], wv[c]);         \
+		wv[d] += t1;                                              \
+		wv[h] = t1 + t2;                                          \
+	}
+
+static const uint32_t sha256_h0[8] = { 0x6a09e667, 0xbb67ae85, 0x3c6ef372,
+				       0xa54ff53a, 0x510e527f, 0x9b05688c,
+				       0x1f83d9ab, 0x5be0cd19 };
+
+static const uint32_t sha256_k[64] = {
+	0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5, 0x3956c25b, 0x59f111f1,
+	0x923f82a4, 0xab1c5ed5, 0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3,
+	0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174, 0xe49b69c1, 0xefbe4786,
+	0x0fc19dc6, 0x240ca1cc, 0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da,
+	0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7, 0xc6e00bf3, 0xd5a79147,
+	0x06ca6351, 0x14292967, 0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13,
+	0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85, 0xa2bfe8a1, 0xa81a664b,
+	0xc24b8b70, 0xc76c51a3, 0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070,
+	0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5, 0x391c0cb3, 0x4ed8aa4a,
+	0x5b9cca4f, 0x682e6ff3, 0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208,
+	0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2
+};
+
+void SHA256_init(struct sha256_ctx *ctx)
+{
+	int i;
+
+	for (i = 0; i < 8; i++)
+		ctx->h[i] = sha256_h0[i];
+
+	ctx->len = 0;
+	ctx->tot_len = 0;
+}
+
+static void SHA256_transform(struct sha256_ctx *ctx, const uint8_t *message,
+			     unsigned int block_nb)
+{
+	/* Note: this function requires a considerable amount of stack */
+	uint32_t w[64];
+	uint32_t wv[8];
+	uint32_t t1, t2;
+	const unsigned char *sub_block;
+	int i, j;
+
+	for (i = 0; i < (int)block_nb; i++) {
+		sub_block = message + (i << 6);
+
+		for (j = 0; j < 16; j++)
+			PACK32(&sub_block[j << 2], &w[j]);
+
+#ifdef CONFIG_SHA256_UNROLLED
+		for (j = 16; j < 64; j += 8) {
+			SHA256_SCR(j);
+			SHA256_SCR(j + 1);
+			SHA256_SCR(j + 2);
+			SHA256_SCR(j + 3);
+			SHA256_SCR(j + 4);
+			SHA256_SCR(j + 5);
+			SHA256_SCR(j + 6);
+			SHA256_SCR(j + 7);
+		}
+#else
+		for (j = 16; j < 64; j++)
+			SHA256_SCR(j);
+#endif
+
+		for (j = 0; j < 8; j++)
+			wv[j] = ctx->h[j];
+
+#ifdef CONFIG_SHA256_UNROLLED
+		for (j = 0; j < 64; j += 8) {
+			SHA256_EXP(0, 1, 2, 3, 4, 5, 6, 7, j);
+			SHA256_EXP(7, 0, 1, 2, 3, 4, 5, 6, j + 1);
+			SHA256_EXP(6, 7, 0, 1, 2, 3, 4, 5, j + 2);
+			SHA256_EXP(5, 6, 7, 0, 1, 2, 3, 4, j + 3);
+			SHA256_EXP(4, 5, 6, 7, 0, 1, 2, 3, j + 4);
+			SHA256_EXP(3, 4, 5, 6, 7, 0, 1, 2, j + 5);
+			SHA256_EXP(2, 3, 4, 5, 6, 7, 0, 1, j + 6);
+			SHA256_EXP(1, 2, 3, 4, 5, 6, 7, 0, j + 7);
+		}
+#else
+		for (j = 0; j < 64; j++) {
+			t1 = wv[7] + SHA256_F2(wv[4]) +
+			     CH(wv[4], wv[5], wv[6]) + sha256_k[j] + w[j];
+			t2 = SHA256_F1(wv[0]) + MAJ(wv[0], wv[1], wv[2]);
+			wv[7] = wv[6];
+			wv[6] = wv[5];
+			wv[5] = wv[4];
+			wv[4] = wv[3] + t1;
+			wv[3] = wv[2];
+			wv[2] = wv[1];
+			wv[1] = wv[0];
+			wv[0] = t1 + t2;
+		}
+#endif
+
+		for (j = 0; j < 8; j++)
+			ctx->h[j] += wv[j];
+	}
+}
+
+void SHA256_update(struct sha256_ctx *ctx, const uint8_t *data, uint32_t len)
+{
+	unsigned int block_nb;
+	unsigned int new_len, rem_len, tmp_len;
+	const uint8_t *shifted_data;
+
+	tmp_len = SHA256_BLOCK_SIZE - ctx->len;
+	rem_len = len < tmp_len ? len : tmp_len;
+
+	memcpy(&ctx->block[ctx->len], data, rem_len);
+
+	if (ctx->len + len < SHA256_BLOCK_SIZE) {
+		ctx->len += len;
+		return;
+	}
+
+	new_len = len - rem_len;
+	block_nb = new_len / SHA256_BLOCK_SIZE;
+
+	shifted_data = data + rem_len;
+
+	SHA256_transform(ctx, ctx->block, 1);
+	SHA256_transform(ctx, shifted_data, block_nb);
+
+	rem_len = new_len % SHA256_BLOCK_SIZE;
+
+	memcpy(ctx->block, &shifted_data[block_nb << 6], rem_len);
+
+	ctx->len = rem_len;
+	ctx->tot_len += (block_nb + 1) << 6;
+}
+
+/*
+ * Specialized SHA256_init + SHA256_update that takes the first data block of
+ * size SHA256_BLOCK_SIZE as input.
+ */
+static void SHA256_init_1b(struct sha256_ctx *ctx, const uint8_t *data)
+{
+	int i;
+
+	for (i = 0; i < 8; i++)
+		ctx->h[i] = sha256_h0[i];
+
+	SHA256_transform(ctx, data, 1);
+
+	ctx->len = 0;
+	ctx->tot_len = SHA256_BLOCK_SIZE;
+}
+
+uint8_t *SHA256_final(struct sha256_ctx *ctx)
+{
+	unsigned int block_nb;
+	unsigned int pm_len;
+	unsigned int len_b;
+	int i;
+
+	block_nb = (1 +
+		    ((SHA256_BLOCK_SIZE - 9) < (ctx->len % SHA256_BLOCK_SIZE)));
+
+	len_b = (ctx->tot_len + ctx->len) << 3;
+	pm_len = block_nb << 6;
+
+	memset(ctx->block + ctx->len, 0, pm_len - ctx->len);
+	ctx->block[ctx->len] = 0x80;
+	UNPACK32(len_b, ctx->block + pm_len - 4);
+
+	SHA256_transform(ctx, ctx->block, block_nb);
+
+	for (i = 0; i < 8; i++)
+		UNPACK32(ctx->h[i], &ctx->buf[i << 2]);
+
+	return ctx->buf;
+}
+
+static void hmac_SHA256_step(uint8_t *output, uint8_t mask, const uint8_t *key,
+			     const int key_len, const uint8_t *data,
+			     const int data_len)
+{
+	struct sha256_ctx ctx;
+	uint8_t *key_pad = ctx.block;
+	uint8_t *tmp;
+	int i;
+
+	/* key_pad = key (zero-padded) ^ mask */
+	memset(key_pad, mask, SHA256_BLOCK_SIZE);
+	for (i = 0; i < key_len; i++)
+		key_pad[i] ^= key[i];
+
+	/* tmp = hash(key_pad || message) */
+	SHA256_init_1b(&ctx, key_pad);
+	SHA256_update(&ctx, data, data_len);
+	tmp = SHA256_final(&ctx);
+	memcpy(output, tmp, SHA256_DIGEST_SIZE);
+}
+
+void hmac_SHA256(uint8_t *output, const uint8_t *key, const int key_len,
+		 const uint8_t *message, const int message_len)
+{
+	/* This code does not support key_len > block_size. */
+	ASSERT(key_len <= SHA256_BLOCK_SIZE);
+
+	/*
+	 * i_key_pad = key (zero-padded) ^ 0x36
+	 * output = hash(i_key_pad || message)
+	 * (Use output as temporary buffer)
+	 */
+	hmac_SHA256_step(output, 0x36, key, key_len, message, message_len);
+
+	/*
+	 * o_key_pad = key (zero-padded) ^ 0x5c
+	 * output = hash(o_key_pad || output)
+	 */
+	hmac_SHA256_step(output, 0x5c, key, key_len, output,
+			 SHA256_DIGEST_SIZE);
+}
diff --git a/common/shared_mem.c b/common/shared_mem.c
index e435408d3b..db1ad0ca32 100644
--- a/common/shared_mem.c
+++ b/common/shared_mem.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -62,14 +62,13 @@ void shared_mem_release(void *ptr)
 }
 
 #ifdef CONFIG_CMD_SHMEM
-static int command_shmem(int argc, char **argv)
+static int command_shmem(int argc, const char **argv)
 {
 	ccprintf("Size:%6d\n", shared_mem_size());
 	ccprintf("Used:%6d\n", buf_in_use);
 	ccprintf("Max: %6d\n", max_used);
 	return EC_SUCCESS;
 }
-DECLARE_SAFE_CONSOLE_COMMAND(shmem, command_shmem,
-			     NULL,
+DECLARE_SAFE_CONSOLE_COMMAND(shmem, command_shmem, NULL,
 			     "Print shared memory stats");
 #endif
diff --git a/common/shmalloc.c b/common/shmalloc.c
index b1705b52d1..6cbf213227 100644
--- a/common/shmalloc.c
+++ b/common/shmalloc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -47,8 +47,8 @@ static void shared_mem_init(void)
 	free_buf_chain = (struct shm_buffer *)__shared_mem_buf;
 	free_buf_chain->next_buffer = NULL;
 	free_buf_chain->prev_buffer = NULL;
-	free_buf_chain->buffer_size = system_usable_ram_end() -
-		(uintptr_t)__shared_mem_buf;
+	free_buf_chain->buffer_size =
+		system_usable_ram_end() - (uintptr_t)__shared_mem_buf;
 }
 DECLARE_HOOK(HOOK_INIT, shared_mem_init, HOOK_PRIO_FIRST);
 
@@ -73,8 +73,7 @@ static void do_release(struct shm_buffer *ptr)
 		 * Saninty check: verify that the buffer is in the allocated
 		 * buffers chain.
 		 */
-		for (pfb = allocced_buf_chain->next_buffer;
-		     pfb;
+		for (pfb = allocced_buf_chain->next_buffer; pfb;
 		     pfb = pfb->next_buffer)
 			if (pfb == ptr)
 				break;
@@ -117,10 +116,9 @@ static void do_release(struct shm_buffer *ptr)
 		if (pfb == free_buf_chain) {
 			set_map_bit(BIT(1));
 			/* Merge the two buffers. */
-			ptr->buffer_size = free_buf_chain->buffer_size +
-				released_size;
-			ptr->next_buffer =
-				free_buf_chain->next_buffer;
+			ptr->buffer_size =
+				free_buf_chain->buffer_size + released_size;
+			ptr->next_buffer = free_buf_chain->next_buffer;
 		} else {
 			set_map_bit(BIT(2));
 			ptr->buffer_size = released_size;
@@ -163,8 +161,7 @@ static void do_release(struct shm_buffer *ptr)
 		if (top == pfb->next_buffer) {
 			/* Yes, it is. */
 			pfb->buffer_size += pfb->next_buffer->buffer_size;
-			pfb->next_buffer =
-				pfb->next_buffer->next_buffer;
+			pfb->next_buffer = pfb->next_buffer->next_buffer;
 			if (pfb->next_buffer) {
 				set_map_bit(BIT(5));
 				pfb->next_buffer->prev_buffer = pfb;
@@ -179,8 +176,8 @@ static void do_release(struct shm_buffer *ptr)
 	if (top == pfb->next_buffer) {
 		/* The new buffer is adjacent with the one right above it. */
 		set_map_bit(BIT(7));
-		ptr->buffer_size = released_size +
-			pfb->next_buffer->buffer_size;
+		ptr->buffer_size =
+			released_size + pfb->next_buffer->buffer_size;
 		ptr->next_buffer = pfb->next_buffer->next_buffer;
 	} else {
 		/* Just include the new free buffer into the chain. */
@@ -352,7 +349,7 @@ void shared_mem_release(void *ptr)
 
 #ifdef CONFIG_CMD_SHMEM
 
-static int command_shmem(int argc, char **argv)
+static int command_shmem(int argc, const char **argv)
 {
 	size_t allocated_size;
 	size_t free_size;
@@ -373,8 +370,7 @@ static int command_shmem(int argc, char **argv)
 			max_free = buf_room;
 	}
 
-	for (buf = allocced_buf_chain; buf;
-	     buf = buf->next_buffer)
+	for (buf = allocced_buf_chain; buf; buf = buf->next_buffer)
 		allocated_size += buf->buffer_size;
 
 	mutex_unlock(&shmem_lock);
@@ -386,8 +382,7 @@ static int command_shmem(int argc, char **argv)
 	ccprintf("Max allocated: %6d\n", max_allocated_size);
 	return EC_SUCCESS;
 }
-DECLARE_SAFE_CONSOLE_COMMAND(shmem, command_shmem,
-			     NULL,
+DECLARE_SAFE_CONSOLE_COMMAND(shmem, command_shmem, NULL,
 			     "Print shared memory stats");
 
-#endif  /* CONFIG_CMD_SHMEM  ^^^^^^^ defined */
+#endif /* CONFIG_CMD_SHMEM  ^^^^^^^ defined */
diff --git a/common/spi_commands.c b/common/spi_commands.c
index 45c2f3ce70..9810039ede 100644
--- a/common/spi_commands.c
+++ b/common/spi_commands.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,11 +8,12 @@
 
 #include "common.h"
 #include "console.h"
+#include "printf.h"
 #include "spi.h"
 #include "timer.h"
 #include "util.h"
 
-static int command_spixfer(int argc, char **argv)
+static int command_spixfer(int argc, const char **argv)
 {
 	int dev_id;
 	uint8_t offset;
@@ -45,8 +46,13 @@ static int command_spixfer(int argc, char **argv)
 
 		rv = spi_transaction(&spi_devices[dev_id], &cmd, 1, data, v);
 
-		if (!rv)
-			ccprintf("Data: %ph\n", HEX_BUF(data, v));
+		if (!rv) {
+			char str_buf[hex_str_buf_size(v)];
+
+			snprintf_hex_buffer(str_buf, sizeof(str_buf),
+					    HEX_BUF(data, v));
+			ccprintf("Data: %s\n", str_buf);
+		}
 
 	} else if (strcasecmp(argv[1], "w") == 0) {
 		/* 8-bit write */
diff --git a/common/spi_flash.c b/common/spi_flash.c
index e202e1e17d..8eaf3e8406 100644
--- a/common/spi_flash.c
+++ b/common/spi_flash.c
@@ -1,11 +1,12 @@
 /*
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
+ * Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * SPI flash driver for Chrome EC.
  */
 
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
 #include "host_command.h"
@@ -22,12 +23,12 @@
 /*
  * Time to sleep when chip is busy
  */
-#define SPI_FLASH_SLEEP_USEC	100
+#define SPI_FLASH_SLEEP_USEC 100
 
 /*
  * This is the max time for 32kb flash erase
  */
-#define SPI_FLASH_TIMEOUT_USEC	(800*MSEC)
+#define SPI_FLASH_TIMEOUT_USEC (800 * MSEC)
 
 /* Internal buffer used by SPI flash driver */
 static uint8_t buf[SPI_FLASH_MAX_MESSAGE_SIZE];
@@ -109,13 +110,12 @@ uint8_t spi_flash_get_status2(void)
  */
 int spi_flash_set_status(int reg1, int reg2)
 {
-	uint8_t cmd[3] = {SPI_FLASH_WRITE_SR, reg1, reg2};
+	uint8_t cmd[3] = { SPI_FLASH_WRITE_SR, reg1, reg2 };
 	int rv = EC_SUCCESS;
 
 	/* fail if both HW pin is asserted and SRP(s) is 1 */
 	if (spi_flash_check_wp() != SPI_WP_NONE &&
-		(crec_flash_get_protect() &
-		EC_FLASH_PROTECT_GPIO_ASSERTED) != 0)
+	    (crec_flash_get_protect() & EC_FLASH_PROTECT_GPIO_ASSERTED) != 0)
 		return EC_ERROR_ACCESS_DENIED;
 
 	/* Enable writing to SPI flash */
@@ -123,7 +123,7 @@ int spi_flash_set_status(int reg1, int reg2)
 	if (rv)
 		return rv;
 
-	/* Second status register not present */
+		/* Second status register not present */
 #ifndef CONFIG_SPI_FLASH_HAS_SR2
 	reg2 = -1;
 #endif
@@ -163,11 +163,8 @@ int spi_flash_read(uint8_t *buf_usr, unsigned int offset, unsigned int bytes)
 		cmd[2] = (spi_addr >> 8) & 0xFF;
 		cmd[3] = spi_addr & 0xFF;
 		read_size = MIN((bytes - i), SPI_FLASH_MAX_READ_SIZE);
-		ret = spi_transaction(SPI_FLASH_DEVICE,
-			cmd,
-			4,
-			buf_usr + i,
-			read_size);
+		ret = spi_transaction(SPI_FLASH_DEVICE, cmd, 4, buf_usr + i,
+				      read_size);
 		if (ret != EC_SUCCESS)
 			break;
 		msleep(CONFIG_SPI_FLASH_READ_WAIT_MS);
@@ -276,7 +273,7 @@ int spi_flash_erase(unsigned int offset, unsigned int bytes)
  * @return EC_SUCCESS, or non-zero if any error.
  */
 int spi_flash_write(unsigned int offset, unsigned int bytes,
-	const uint8_t *data)
+		    const uint8_t *data)
 {
 	int rv, write_size;
 
@@ -288,8 +285,10 @@ int spi_flash_write(unsigned int offset, unsigned int bytes,
 	while (bytes > 0) {
 		watchdog_reload();
 		/* Write length can not go beyond the end of the flash page */
-		write_size = MIN(bytes, SPI_FLASH_MAX_WRITE_SIZE -
-		(offset & (SPI_FLASH_MAX_WRITE_SIZE - 1)));
+		write_size =
+			MIN(bytes,
+			    SPI_FLASH_MAX_WRITE_SIZE -
+				    (offset & (SPI_FLASH_MAX_WRITE_SIZE - 1)));
 
 		/* Wait for previous operation to complete */
 		rv = spi_flash_wait();
@@ -310,8 +309,8 @@ int spi_flash_write(unsigned int offset, unsigned int bytes,
 		buf[2] = (offset) >> 8;
 		buf[3] = offset;
 
-		rv = spi_transaction(SPI_FLASH_DEVICE,
-				     buf, 4 + write_size, NULL, 0);
+		rv = spi_transaction(SPI_FLASH_DEVICE, buf, 4 + write_size,
+				     NULL, 0);
 		if (rv)
 			return rv;
 
@@ -345,7 +344,7 @@ int spi_flash_get_jedec_id(uint8_t *dest)
  */
 int spi_flash_get_mfr_dev_id(uint8_t *dest)
 {
-	uint8_t cmd[4] = {SPI_FLASH_MFR_DEV_ID, 0, 0, 0};
+	uint8_t cmd[4] = { SPI_FLASH_MFR_DEV_ID, 0, 0, 0 };
 
 	return spi_transaction(SPI_FLASH_DEVICE, cmd, sizeof(cmd), dest, 2);
 }
@@ -358,7 +357,7 @@ int spi_flash_get_mfr_dev_id(uint8_t *dest)
  */
 int spi_flash_get_unique_id(uint8_t *dest)
 {
-	uint8_t cmd[5] = {SPI_FLASH_UNIQUE_ID, 0, 0, 0, 0};
+	uint8_t cmd[5] = { SPI_FLASH_UNIQUE_ID, 0, 0, 0, 0 };
 
 	return spi_transaction(SPI_FLASH_DEVICE, cmd, sizeof(cmd), dest, 8);
 }
@@ -480,7 +479,7 @@ int spi_flash_set_protect(unsigned int offset, unsigned int bytes)
 	return spi_flash_set_status(sr1, sr2);
 }
 
-static int command_spi_flashinfo(int argc, char **argv)
+static int command_spi_flashinfo(int argc, const char **argv)
 {
 	uint8_t jedec[3];
 	uint8_t unique[8];
@@ -497,18 +496,17 @@ static int command_spi_flashinfo(int argc, char **argv)
 	spi_flash_get_jedec_id(jedec);
 	spi_flash_get_unique_id(unique);
 
-	ccprintf("Manufacturer ID: %02x\nDevice ID: %02x %02x\n",
-		 jedec[0], jedec[1], jedec[2]);
+	ccprintf("Manufacturer ID: %02x\nDevice ID: %02x %02x\n", jedec[0],
+		 jedec[1], jedec[2]);
 	ccprintf("Unique ID: %02x %02x %02x %02x %02x %02x %02x %02x\n",
-		 unique[0], unique[1], unique[2], unique[3],
-		 unique[4], unique[5], unique[6], unique[7]);
+		 unique[0], unique[1], unique[2], unique[3], unique[4],
+		 unique[5], unique[6], unique[7]);
 	ccprintf("Capacity: %4d kB\n", SPI_FLASH_SIZE(jedec[2]) / 1024);
 
 	return rv;
 }
-DECLARE_CONSOLE_COMMAND(spi_flashinfo, command_spi_flashinfo,
-	NULL,
-	"Print SPI flash info");
+DECLARE_CONSOLE_COMMAND(spi_flashinfo, command_spi_flashinfo, NULL,
+			"Print SPI flash info");
 
 #ifdef CONFIG_HOSTCMD_FLASH_SPI_INFO
 static enum ec_status flash_command_spi_info(struct host_cmd_handler_args *args)
@@ -524,13 +522,12 @@ static enum ec_status flash_command_spi_info(struct host_cmd_handler_args *args)
 	args->response_size = sizeof(*r);
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_FLASH_SPI_INFO,
-		     flash_command_spi_info,
+DECLARE_HOST_COMMAND(EC_CMD_FLASH_SPI_INFO, flash_command_spi_info,
 		     EC_VER_MASK(0));
-#endif  /* CONFIG_HOSTCMD_FLASH_SPI_INFO */
+#endif /* CONFIG_HOSTCMD_FLASH_SPI_INFO */
 
 #ifdef CONFIG_CMD_SPI_FLASH
-static int command_spi_flasherase(int argc, char **argv)
+static int command_spi_flasherase(int argc, const char **argv)
 {
 	int offset = -1;
 	int bytes = 4096;
@@ -549,10 +546,9 @@ static int command_spi_flasherase(int argc, char **argv)
 	return spi_flash_erase(offset, bytes);
 }
 DECLARE_CONSOLE_COMMAND(spi_flasherase, command_spi_flasherase,
-	"offset [bytes]",
-	"Erase flash");
+			"offset [bytes]", "Erase flash");
 
-static int command_spi_flashwrite(int argc, char **argv)
+static int command_spi_flashwrite(int argc, const char **argv)
 {
 	int offset = -1;
 	int bytes = SPI_FLASH_MAX_WRITE_SIZE;
@@ -578,7 +574,8 @@ static int command_spi_flashwrite(int argc, char **argv)
 	while (bytes > 0) {
 		/* First write multiples of 256, then (bytes % 256) last */
 		write_len = ((bytes % SPI_FLASH_MAX_WRITE_SIZE) == bytes) ?
-					bytes : SPI_FLASH_MAX_WRITE_SIZE;
+				    bytes :
+				    SPI_FLASH_MAX_WRITE_SIZE;
 
 		/* Perform write */
 		rv = spi_flash_write(offset, write_len, buf);
@@ -594,10 +591,9 @@ static int command_spi_flashwrite(int argc, char **argv)
 	return rv;
 }
 DECLARE_CONSOLE_COMMAND(spi_flashwrite, command_spi_flashwrite,
-	"offset [bytes]",
-	"Write pattern to flash");
+			"offset [bytes]", "Write pattern to flash");
 
-static int command_spi_flashread(int argc, char **argv)
+static int command_spi_flashread(int argc, const char **argv)
 {
 	int i;
 	int offset = -1;
@@ -627,8 +623,8 @@ static int command_spi_flashread(int argc, char **argv)
 
 		/* First read (bytes % 256), then in multiples of 256 */
 		read_len = (bytes % SPI_FLASH_MAX_READ_SIZE) ?
-					(bytes % SPI_FLASH_MAX_READ_SIZE) :
-					SPI_FLASH_MAX_READ_SIZE;
+				   (bytes % SPI_FLASH_MAX_READ_SIZE) :
+				   SPI_FLASH_MAX_READ_SIZE;
 
 		rv = spi_flash_read(buf, offset, read_len);
 		if (rv)
@@ -651,11 +647,10 @@ static int command_spi_flashread(int argc, char **argv)
 	ASSERT(bytes == 0);
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(spi_flashread, command_spi_flashread,
-	"offset bytes",
-	"Read flash");
+DECLARE_CONSOLE_COMMAND(spi_flashread, command_spi_flashread, "offset bytes",
+			"Read flash");
 
-static int command_spi_flashread_sr(int argc, char **argv)
+static int command_spi_flashread_sr(int argc, const char **argv)
 {
 	spi_enable(SPI_FLASH_DEVICE, 1);
 
@@ -664,11 +659,10 @@ static int command_spi_flashread_sr(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(spi_flash_rsr, command_spi_flashread_sr,
-	NULL,
-	"Read status registers");
+DECLARE_CONSOLE_COMMAND(spi_flash_rsr, command_spi_flashread_sr, NULL,
+			"Read status registers");
 
-static int command_spi_flashwrite_sr(int argc, char **argv)
+static int command_spi_flashwrite_sr(int argc, const char **argv)
 {
 	int val1 = 0;
 	int val2 = 0;
@@ -684,10 +678,9 @@ static int command_spi_flashwrite_sr(int argc, char **argv)
 	return spi_flash_set_status(val1, val2);
 }
 DECLARE_CONSOLE_COMMAND(spi_flash_wsr, command_spi_flashwrite_sr,
-	"value1 value2",
-	"Write to status registers");
+			"value1 value2", "Write to status registers");
 
-static int command_spi_flashprotect(int argc, char **argv)
+static int command_spi_flashprotect(int argc, const char **argv)
 {
 	int val1 = 0;
 	int val2 = 0;
@@ -698,10 +691,10 @@ static int command_spi_flashprotect(int argc, char **argv)
 
 	spi_enable(SPI_FLASH_DEVICE, 1);
 
-	ccprintf("Setting protection for 0x%06x to 0x%06x\n", val1, val1+val2);
+	ccprintf("Setting protection for 0x%06x to 0x%06x\n", val1,
+		 val1 + val2);
 	return spi_flash_set_protect(val1, val2);
 }
-DECLARE_CONSOLE_COMMAND(spi_flash_prot, command_spi_flashprotect,
-	"offset len",
-	"Set block protection");
+DECLARE_CONSOLE_COMMAND(spi_flash_prot, command_spi_flashprotect, "offset len",
+			"Set block protection");
 #endif
diff --git a/common/spi_flash_reg.c b/common/spi_flash_reg.c
index ee8d31fa06..fa71ab5eb6 100644
--- a/common/spi_flash_reg.c
+++ b/common/spi_flash_reg.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -21,7 +21,7 @@ struct protect_range {
 	enum bit_state cmp;
 	enum bit_state sec;
 	enum bit_state tb;
-	enum bit_state bp[3];    /* Ordered {BP2, BP1, BP0} */
+	enum bit_state bp[3]; /* Ordered {BP2, BP1, BP0} */
 	uint32_t protect_start;
 	uint32_t protect_len;
 };
@@ -39,7 +39,7 @@ struct protect_range {
  */
 #if defined(CONFIG_SPI_FLASH_W25X40) || defined(CONFIG_SPI_FLASH_GD25Q41B)
 static const struct protect_range spi_flash_protect_ranges[] = {
-	{ IGN, IGN, IGN, { 0, 0, 0 }, 0, 0 },     /* No protection */
+	{ IGN, IGN, IGN, { 0, 0, 0 }, 0, 0 }, /* No protection */
 	{ IGN, IGN, 1, { 0, 1, 1 }, 0, 0x40000 }, /* Lower 1/2 */
 	{ IGN, IGN, 1, { 0, 1, 0 }, 0, 0x20000 }, /* Lower 1/4 */
 };
@@ -49,17 +49,17 @@ static const struct protect_range spi_flash_protect_ranges[] = {
 /* For GD25LQ40, BP3 and BP4 have same meaning as TB and SEC */
 static const struct protect_range spi_flash_protect_ranges[] = {
 	/* CMP = 0 */
-	{ 0, IGN, IGN, { 0, 0, 0 }, 0, 0 },         /* No protection */
-	{ 0, 0, 1, { 0, 1, 0 }, 0, 0x20000 },       /* Lower 1/4 */
-	{ 0, 0, 1, { 0, 1, 1 }, 0, 0x40000 },       /* Lower 1/2 */
+	{ 0, IGN, IGN, { 0, 0, 0 }, 0, 0 }, /* No protection */
+	{ 0, 0, 1, { 0, 1, 0 }, 0, 0x20000 }, /* Lower 1/4 */
+	{ 0, 0, 1, { 0, 1, 1 }, 0, 0x40000 }, /* Lower 1/2 */
 	/* CMP = 1 */
-	{ 1, 0, 0, { 0, 1, 1 }, 0, 0x40000 },       /* Lower 1/2 */
-	{ 1, 0, IGN, { 1, IGN, IGN }, 0, 0 },       /* None (W25Q40EW only) */
+	{ 1, 0, 0, { 0, 1, 1 }, 0, 0x40000 }, /* Lower 1/2 */
+	{ 1, 0, IGN, { 1, IGN, IGN }, 0, 0 }, /* None (W25Q40EW only) */
 };
 
 #elif defined(CONFIG_SPI_FLASH_W25Q64)
 static const struct protect_range spi_flash_protect_ranges[] = {
-	{ 0, IGN, IGN, { 0, 0, 0 }, 0, 0 },    /* No protection */
+	{ 0, IGN, IGN, { 0, 0, 0 }, 0, 0 }, /* No protection */
 	{ 0, 0, 1, { 1, 1, 0 }, 0, 0x400000 }, /* Lower 1/2 */
 	{ 0, 0, 1, { 1, 0, 1 }, 0, 0x200000 }, /* Lower 1/4 */
 };
@@ -67,7 +67,7 @@ static const struct protect_range spi_flash_protect_ranges[] = {
 #elif defined(CONFIG_SPI_FLASH_W25Q80)
 static const struct protect_range spi_flash_protect_ranges[] = {
 	/* CMP = 0 */
-	{ 0, IGN, IGN, { 0, 0, 0 }, 0, 0 },   /* No protection */
+	{ 0, IGN, IGN, { 0, 0, 0 }, 0, 0 }, /* No protection */
 	{ 0, 0, 1, { 0, 1, 0 }, 0, 0x20000 }, /* Lower 1/8 */
 	{ 0, 0, 1, { 0, 1, 1 }, 0, 0x40000 }, /* Lower 1/4 */
 	{ 0, 0, 1, { 1, 0, 0 }, 0, 0x80000 }, /* Lower 1/2 */
@@ -75,7 +75,7 @@ static const struct protect_range spi_flash_protect_ranges[] = {
 #elif defined(CONFIG_SPI_FLASH_W25Q128)
 static const struct protect_range spi_flash_protect_ranges[] = {
 	/* CMP = 0 */
-	{ 0, IGN, IGN, { 0, 0, 0 }, 0, 0 },   /* No protection */
+	{ 0, IGN, IGN, { 0, 0, 0 }, 0, 0 }, /* No protection */
 	{ 0, 0, 1, { 1, 0, 0 }, 0, 0x20000 }, /* Lower 1/8 */
 	{ 0, 0, 1, { 1, 0, 1 }, 0, 0x40000 }, /* Lower 1/4 */
 	{ 0, 0, 1, { 1, 1, 0 }, 0, 0x80000 }, /* Lower 1/2 */
@@ -107,8 +107,9 @@ int spi_flash_reg_to_protect(uint8_t sr1, uint8_t sr2, unsigned int *start,
 	cmp = (sr2 & SPI_FLASH_SR2_CMP) ? 1 : 0;
 	sec = (sr1 & SPI_FLASH_SR1_SEC) ? 1 : 0;
 	tb = (sr1 & SPI_FLASH_SR1_TB) ? 1 : 0;
-	bp = (sr1 & (SPI_FLASH_SR1_BP2 | SPI_FLASH_SR1_BP1 | SPI_FLASH_SR1_BP0))
-		 >> 2;
+	bp = (sr1 &
+	      (SPI_FLASH_SR1_BP2 | SPI_FLASH_SR1_BP1 | SPI_FLASH_SR1_BP0)) >>
+	     2;
 
 	/* Bad pointers or invalid data */
 	if (!start || !len || sr1 == 0xff || sr2 == 0xff)
@@ -174,12 +175,10 @@ int spi_flash_protect_to_reg(unsigned int start, unsigned int len, uint8_t *sr1,
 			sec = GET_BIT(range->sec);
 			tb = GET_BIT(range->tb);
 			bp = GET_BIT(range->bp[0]) << 2 |
-			     GET_BIT(range->bp[1]) << 1 |
-			     GET_BIT(range->bp[2]);
+			     GET_BIT(range->bp[1]) << 1 | GET_BIT(range->bp[2]);
 
 			*sr1 = (sec ? SPI_FLASH_SR1_SEC : 0) |
-			       (tb ? SPI_FLASH_SR1_TB : 0) |
-			       (bp << 2);
+			       (tb ? SPI_FLASH_SR1_TB : 0) | (bp << 2);
 			*sr2 = (cmp ? SPI_FLASH_SR2_CMP : 0);
 			return EC_SUCCESS;
 		}
diff --git a/common/spi_nor.c b/common/spi_nor.c
index 0a719d63b3..015cb7077c 100644
--- a/common/spi_nor.c
+++ b/common/spi_nor.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,7 +18,7 @@
 
 #ifdef CONFIG_SPI_NOR_DEBUG
 #define CPRINTS(dev, string, args...) \
-	cprints(CC_SPI, "SPI NOR %s: " string, (dev)->name, ## args)
+	cprints(CC_SPI, "SPI NOR %s: " string, (dev)->name, ##args)
 #else
 #define CPRINTS(dev, string, args...)
 #endif
@@ -74,8 +74,8 @@ static int spi_nor_write_enable(const struct spi_nor_device_t *spi_nor_device)
 	int rv = EC_SUCCESS;
 
 	/* Set the write enable latch. */
-	rv = spi_transaction(&spi_devices[spi_nor_device->spi_controller],
-			     &cmd, 1, NULL, 0);
+	rv = spi_transaction(&spi_devices[spi_nor_device->spi_controller], &cmd,
+			     1, NULL, 0);
 	if (rv)
 		return rv;
 
@@ -84,7 +84,7 @@ static int spi_nor_write_enable(const struct spi_nor_device_t *spi_nor_device)
 	if (rv)
 		return rv;
 	if ((status_register_value & SPI_NOR_STATUS_REGISTER_WEL) == 0)
-		return EC_ERROR_UNKNOWN;  /* WEL not set but should be. */
+		return EC_ERROR_UNKNOWN; /* WEL not set but should be. */
 
 	return rv;
 }
@@ -101,7 +101,7 @@ static int spi_nor_read_ear(const struct spi_nor_device_t *spi_nor_device,
 	uint8_t command = SPI_NOR_OPCODE_RDEAR;
 
 	return spi_transaction(&spi_devices[spi_nor_device->spi_controller],
-			&command, sizeof(command), value, 1);
+			       &command, sizeof(command), value, 1);
 }
 
 int spi_nor_write_ear(const struct spi_nor_device_t *spi_nor_device,
@@ -122,8 +122,8 @@ int spi_nor_write_ear(const struct spi_nor_device_t *spi_nor_device,
 	buf[0] = SPI_NOR_OPCODE_WREAR;
 	buf[1] = value;
 
-	rv = spi_transaction(&spi_devices[spi_nor_device->spi_controller],
-			     buf, sizeof(buf), NULL, 0);
+	rv = spi_transaction(&spi_devices[spi_nor_device->spi_controller], buf,
+			     sizeof(buf), NULL, 0);
 	if (rv) {
 		CPRINTS(spi_nor_device, "Failed to write EAR, rv=%d", rv);
 		goto err_free;
@@ -134,9 +134,9 @@ int spi_nor_write_ear(const struct spi_nor_device_t *spi_nor_device,
 		goto err_free;
 
 	if (ear != value) {
-		CPRINTS(spi_nor_device,
-			"Write EAR error: write=%d, read=%d", value, ear);
-		rv = EC_ERROR_UNKNOWN;  /* WEL not set but should be. */
+		CPRINTS(spi_nor_device, "Write EAR error: write=%d, read=%d",
+			value, ear);
+		rv = EC_ERROR_UNKNOWN; /* WEL not set but should be. */
 		goto err_free;
 	}
 
@@ -157,8 +157,7 @@ static int spi_nor_wait(const struct spi_nor_device_t *spi_nor_device)
 	rv = spi_nor_read_status(spi_nor_device, &status_register_value);
 	if (rv)
 		return rv;
-	timeout.val =
-		get_time().val + spi_nor_device->timeout_usec;
+	timeout.val = get_time().val + spi_nor_device->timeout_usec;
 	while (status_register_value & SPI_NOR_STATUS_REGISTER_WIP) {
 		/* Reload the watchdog before sleeping. */
 		watchdog_reload();
@@ -181,10 +180,9 @@ static int spi_nor_wait(const struct spi_nor_device_t *spi_nor_device)
 /**
  * Read the Manufacturer bank and ID out of the JEDEC ID.
  */
-static int spi_nor_read_jedec_mfn_id(
-		const struct spi_nor_device_t *spi_nor_device,
-		uint8_t *out_mfn_bank,
-		uint8_t *out_mfn_id)
+static int
+spi_nor_read_jedec_mfn_id(const struct spi_nor_device_t *spi_nor_device,
+			  uint8_t *out_mfn_bank, uint8_t *out_mfn_id)
 {
 	int rv = EC_SUCCESS;
 	uint8_t jedec_id[SPI_NOR_JEDEC_ID_BANKS];
@@ -192,8 +190,8 @@ static int spi_nor_read_jedec_mfn_id(
 	uint8_t cmd = SPI_NOR_OPCODE_JEDEC_ID;
 
 	/* Read the standardized part of the JEDEC ID. */
-	rv = spi_transaction(&spi_devices[spi_nor_device->spi_controller],
-			     &cmd, 1, jedec_id, SPI_NOR_JEDEC_ID_BANKS);
+	rv = spi_transaction(&spi_devices[spi_nor_device->spi_controller], &cmd,
+			     1, jedec_id, SPI_NOR_JEDEC_ID_BANKS);
 	if (rv)
 		return rv;
 
@@ -214,11 +212,11 @@ static int spi_nor_read_jedec_mfn_id(
 /**
  * Read a doubleword out of a SFDP table (DWs are 1-based like the SFDP spec).
  */
-static int spi_nor_read_sfdp_dword(
-		const struct spi_nor_device_t *spi_nor_device,
-		uint32_t table_offset,
-		uint8_t table_double_word,
-		uint32_t *out_dw) {
+static int
+spi_nor_read_sfdp_dword(const struct spi_nor_device_t *spi_nor_device,
+			uint32_t table_offset, uint8_t table_double_word,
+			uint32_t *out_dw)
+{
 	uint8_t sfdp_cmd[5];
 	/* Calculate the byte offset based on the double word. */
 	uint32_t sfdp_offset = table_offset + ((table_double_word - 1) * 4);
@@ -228,7 +226,7 @@ static int spi_nor_read_sfdp_dword(
 	sfdp_cmd[1] = (sfdp_offset & 0xFF0000) >> 16;
 	sfdp_cmd[2] = (sfdp_offset & 0xFF00) >> 8;
 	sfdp_cmd[3] = (sfdp_offset & 0xFF);
-	sfdp_cmd[4] = 0;  /* Required extra cycle. */
+	sfdp_cmd[4] = 0; /* Required extra cycle. */
 	return spi_transaction(&spi_devices[spi_nor_device->spi_controller],
 			       sfdp_cmd, 5, (uint8_t *)out_dw, 4);
 }
@@ -248,10 +246,10 @@ static int is_basic_flash_parameter_table(uint8_t sfdp_major_rev,
 			BASIC_FLASH_PARAMETER_TABLE_1_0_ID);
 	} else if (sfdp_major_rev == 1 && sfdp_minor_rev >= 5) {
 		return ((SFDP_GET_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW1_ID_LSB,
-					  parameter_header_dw1) ==
+					   parameter_header_dw1) ==
 			 BASIC_FLASH_PARAMETER_TABLE_1_5_ID_LSB) &&
 			(SFDP_GET_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW2_ID_MSB,
-					  parameter_header_dw2) ==
+					   parameter_header_dw2) ==
 			 BASIC_FLASH_PARAMETER_TABLE_1_5_ID_MSB));
 	}
 
@@ -262,13 +260,10 @@ static int is_basic_flash_parameter_table(uint8_t sfdp_major_rev,
  * Helper function to locate the SFDP Basic SPI Flash NOR Parameter Table.
  */
 static int locate_sfdp_basic_parameter_table(
-		const struct spi_nor_device_t *spi_nor_device,
-		uint8_t *out_sfdp_major_rev,
-		uint8_t *out_sfdp_minor_rev,
-		uint8_t *out_table_major_rev,
-		uint8_t *out_table_minor_rev,
-		uint32_t *out_table_offset,
-		size_t *out_table_size)
+	const struct spi_nor_device_t *spi_nor_device,
+	uint8_t *out_sfdp_major_rev, uint8_t *out_sfdp_minor_rev,
+	uint8_t *out_table_major_rev, uint8_t *out_table_minor_rev,
+	uint32_t *out_table_offset, size_t *out_table_size)
 {
 	int rv = EC_SUCCESS;
 	uint8_t number_parameter_headers;
@@ -296,8 +291,8 @@ static int locate_sfdp_basic_parameter_table(
 		SFDP_GET_BITFIELD(SFDP_HEADER_DW2_SFDP_MAJOR, dw2);
 	*out_sfdp_minor_rev =
 		SFDP_GET_BITFIELD(SFDP_HEADER_DW2_SFDP_MINOR, dw2);
-	CPRINTS(spi_nor_device, "SFDP v%d.%d discovered",
-		*out_sfdp_major_rev, *out_sfdp_minor_rev);
+	CPRINTS(spi_nor_device, "SFDP v%d.%d discovered", *out_sfdp_major_rev,
+		*out_sfdp_minor_rev);
 
 	/* NPH is 0-based, so add 1. */
 	number_parameter_headers =
@@ -315,17 +310,16 @@ static int locate_sfdp_basic_parameter_table(
 		number_parameter_headers--;
 
 		/* Read this parameter header's two dwords. */
-		rv = spi_nor_read_sfdp_dword(
-			spi_nor_device, table_offset, 1, &dw1);
-		rv |= spi_nor_read_sfdp_dword(
-			spi_nor_device, table_offset, 2, &dw2);
+		rv = spi_nor_read_sfdp_dword(spi_nor_device, table_offset, 1,
+					     &dw1);
+		rv |= spi_nor_read_sfdp_dword(spi_nor_device, table_offset, 2,
+					      &dw2);
 		if (rv)
 			return rv;
 
 		/* Ensure it's the basic flash parameter table. */
-		if (!is_basic_flash_parameter_table(*out_sfdp_major_rev,
-						    *out_sfdp_minor_rev,
-						    dw1, dw2))
+		if (!is_basic_flash_parameter_table(
+			    *out_sfdp_major_rev, *out_sfdp_minor_rev, dw1, dw2))
 			continue;
 
 		/* The parameter header major and minor versioning is still the
@@ -352,8 +346,10 @@ static int locate_sfdp_basic_parameter_table(
 		*out_table_offset = SFDP_GET_BITFIELD(
 			SFDP_1_0_PARAMETER_HEADER_DW2_PTP, dw2);
 		/* Convert the size from DW to Bytes. */
-		*out_table_size = SFDP_GET_BITFIELD(
-			SFDP_1_0_PARAMETER_HEADER_DW1_PTL, dw1) * 4;
+		*out_table_size =
+			SFDP_GET_BITFIELD(SFDP_1_0_PARAMETER_HEADER_DW1_PTL,
+					  dw1) *
+			4;
 	}
 
 	if (!table_found) {
@@ -376,8 +372,7 @@ static int spi_nor_device_discover_sfdp_page_size(
 	struct spi_nor_device_t *spi_nor_device,
 	uint8_t basic_parameter_table_major_version,
 	uint8_t basic_parameter_table_minor_version,
-	uint32_t basic_parameter_table_offset,
-	size_t *page_size)
+	uint32_t basic_parameter_table_offset, size_t *page_size)
 {
 	int rv = EC_SUCCESS;
 	uint32_t dw;
@@ -397,12 +392,12 @@ static int spi_nor_device_discover_sfdp_page_size(
 	} else if (basic_parameter_table_major_version == 1 &&
 		   basic_parameter_table_minor_version >= 5) {
 		/* Use the Basic Flash Parameter v1.5 page size reporting. */
-		rv = spi_nor_read_sfdp_dword(spi_nor_device,
-				     basic_parameter_table_offset, 11, &dw);
+		rv = spi_nor_read_sfdp_dword(
+			spi_nor_device, basic_parameter_table_offset, 11, &dw);
 		if (rv)
 			return rv;
-		*page_size =
-			1 << SFDP_GET_BITFIELD(BFPT_1_5_DW11_PAGE_SIZE, dw);
+		*page_size = 1
+			     << SFDP_GET_BITFIELD(BFPT_1_5_DW11_PAGE_SIZE, dw);
 	}
 
 	return EC_SUCCESS;
@@ -413,11 +408,10 @@ static int spi_nor_device_discover_sfdp_page_size(
  * NOR Parameter Table.
  */
 static int spi_nor_device_discover_sfdp_capacity(
-		struct spi_nor_device_t *spi_nor_device,
-		uint8_t basic_parameter_table_major_version,
-		uint8_t basic_parameter_table_minor_version,
-		uint32_t basic_parameter_table_offset,
-		uint32_t *capacity)
+	struct spi_nor_device_t *spi_nor_device,
+	uint8_t basic_parameter_table_major_version,
+	uint8_t basic_parameter_table_minor_version,
+	uint32_t basic_parameter_table_offset, uint32_t *capacity)
 {
 	int rv = EC_SUCCESS;
 	uint32_t dw;
@@ -425,15 +419,16 @@ static int spi_nor_device_discover_sfdp_capacity(
 	/* First attempt to discover the device's capacity. */
 	if (basic_parameter_table_major_version == 1) {
 		/* Use the Basic Flash Parameter v1.0 capacity reporting. */
-		rv = spi_nor_read_sfdp_dword(spi_nor_device,
-				     basic_parameter_table_offset, 2, &dw);
+		rv = spi_nor_read_sfdp_dword(
+			spi_nor_device, basic_parameter_table_offset, 2, &dw);
 		if (rv)
 			return rv;
 
 		if (SFDP_GET_BITFIELD(BFPT_1_0_DW2_GT_2_GIBIBITS, dw)) {
 			/* Ensure the capacity is less than 4GiB. */
-			uint64_t tmp_capacity = 1 <<
-				(SFDP_GET_BITFIELD(BFPT_1_0_DW2_N, dw) - 3);
+			uint64_t tmp_capacity =
+				1
+				<< (SFDP_GET_BITFIELD(BFPT_1_0_DW2_N, dw) - 3);
 			if (tmp_capacity > UINT32_MAX)
 				return EC_ERROR_OVERFLOW;
 			*capacity = tmp_capacity;
@@ -456,8 +451,7 @@ static int spi_nor_read_internal(const struct spi_nor_device_t *spi_nor_device,
 	 * is larger than the maximum read size.
 	 */
 	while (size > 0) {
-		size_t read_size =
-			MIN(size, CONFIG_SPI_NOR_MAX_READ_SIZE);
+		size_t read_size = MIN(size, CONFIG_SPI_NOR_MAX_READ_SIZE);
 		size_t read_command_size;
 
 		/* Set up the read command in the TX buffer. */
@@ -468,7 +462,7 @@ static int spi_nor_read_internal(const struct spi_nor_device_t *spi_nor_device,
 			buf[3] = (offset & 0xFF00) >> 8;
 			buf[4] = (offset & 0xFF);
 			read_command_size = 5;
-		} else {  /* in 3 byte addressing mode */
+		} else { /* in 3 byte addressing mode */
 			buf[1] = (offset & 0xFF0000) >> 16;
 			buf[2] = (offset & 0xFF00) >> 8;
 			buf[3] = (offset & 0xFF);
@@ -476,8 +470,8 @@ static int spi_nor_read_internal(const struct spi_nor_device_t *spi_nor_device,
 		}
 
 		rv = spi_transaction(
-			&spi_devices[spi_nor_device->spi_controller],
-			buf, read_command_size, data, read_size);
+			&spi_devices[spi_nor_device->spi_controller], buf,
+			read_command_size, data, read_size);
 		if (rv)
 			return rv;
 
@@ -513,16 +507,12 @@ int spi_nor_init(void)
 		uint8_t table_major_rev, table_minor_rev;
 		uint32_t table_offset;
 		size_t table_size;
-		struct spi_nor_device_t *spi_nor_device =
-			&spi_nor_devices[i];
+		struct spi_nor_device_t *spi_nor_device = &spi_nor_devices[i];
 
-		rv |= locate_sfdp_basic_parameter_table(spi_nor_device,
-							&sfdp_major_rev,
-							&sfdp_minor_rev,
-							&table_major_rev,
-							&table_minor_rev,
-							&table_offset,
-							&table_size);
+		rv |= locate_sfdp_basic_parameter_table(
+			spi_nor_device, &sfdp_major_rev, &sfdp_minor_rev,
+			&table_major_rev, &table_minor_rev, &table_offset,
+			&table_size);
 
 		/* If we failed to find a compatible SFDP Basic Flash Parameter
 		 * table, use the default capacity, page size, and addressing
@@ -532,13 +522,11 @@ int spi_nor_init(void)
 			uint32_t capacity = 0;
 
 			rv |= spi_nor_device_discover_sfdp_page_size(
-				spi_nor_device,
-				table_major_rev, table_minor_rev, table_offset,
-				&page_size);
+				spi_nor_device, table_major_rev,
+				table_minor_rev, table_offset, &page_size);
 			rv |= spi_nor_device_discover_sfdp_capacity(
-				spi_nor_device,
-				table_major_rev, table_minor_rev, table_offset,
-				&capacity);
+				spi_nor_device, table_major_rev,
+				table_minor_rev, table_offset, &capacity);
 			if (rv == EC_SUCCESS) {
 				mutex_lock(&driver_mutex);
 				spi_nor_device->capacity = capacity;
@@ -595,8 +583,8 @@ int spi_nor_set_4b_mode(struct spi_nor_device_t *spi_nor_device,
 	/* Claim the driver mutex to modify the device state. */
 	mutex_lock(&driver_mutex);
 
-	rv = spi_transaction(&spi_devices[spi_nor_device->spi_controller],
-			     &cmd, 1, NULL, 0);
+	rv = spi_transaction(&spi_devices[spi_nor_device->spi_controller], &cmd,
+			     1, NULL, 0);
 	if (rv == EC_SUCCESS) {
 		spi_nor_device->in_4b_addressing_mode =
 			enter_4b_addressing_mode;
@@ -619,7 +607,8 @@ int spi_nor_set_4b_mode(struct spi_nor_device_t *spi_nor_device,
  * @return ec_error_list (non-zero on error and timeout).
  */
 int spi_nor_read_jedec_id(const struct spi_nor_device_t *spi_nor_device,
-			  size_t size, uint8_t *data) {
+			  size_t size, uint8_t *data)
+{
 	int rv;
 	uint8_t cmd = SPI_NOR_OPCODE_JEDEC_ID;
 
@@ -628,8 +617,8 @@ int spi_nor_read_jedec_id(const struct spi_nor_device_t *spi_nor_device,
 	/* Claim the driver mutex. */
 	mutex_lock(&driver_mutex);
 	/* Read the JEDEC ID. */
-	rv = spi_transaction(&spi_devices[spi_nor_device->spi_controller],
-			     &cmd, 1, data, size);
+	rv = spi_transaction(&spi_devices[spi_nor_device->spi_controller], &cmd,
+			     1, data, size);
 	/* Release the driver mutex. */
 	mutex_unlock(&driver_mutex);
 
@@ -645,8 +634,8 @@ int spi_nor_read_jedec_id(const struct spi_nor_device_t *spi_nor_device,
  * @param data Destination buffer for data.
  * @return ec_error_list (non-zero on error and timeout).
  */
-int spi_nor_read(const struct spi_nor_device_t *spi_nor_device,
-		 uint32_t offset, size_t size, uint8_t *data)
+int spi_nor_read(const struct spi_nor_device_t *spi_nor_device, uint32_t offset,
+		 size_t size, uint8_t *data)
 {
 	int rv;
 
@@ -708,8 +697,8 @@ int spi_nor_erase(const struct spi_nor_device_t *spi_nor_device,
 		read_offset = offset;
 		read_left = erase_size;
 		while (read_left) {
-			read_size = MIN(read_left,
-					CONFIG_SPI_NOR_MAX_READ_SIZE);
+			read_size =
+				MIN(read_left, CONFIG_SPI_NOR_MAX_READ_SIZE);
 			/* Since CONFIG_SPI_NOR_MAX_READ_SIZE & erase_size are
 			 * both guaranteed to be multiples of 4.
 			 */
@@ -731,8 +720,8 @@ int spi_nor_erase(const struct spi_nor_device_t *spi_nor_device,
 			 */
 			verify_offset = 0;
 			while (verify_offset <= read_size - 4) {
-				if (*(uint32_t *)(buffer + verify_offset)
-				    != 0xffffffff) {
+				if (*(uint32_t *)(buffer + verify_offset) !=
+				    0xffffffff) {
 					break;
 				}
 				verify_offset += 4;
@@ -767,7 +756,7 @@ int spi_nor_erase(const struct spi_nor_device_t *spi_nor_device,
 			buf[3] = (offset & 0xFF00) >> 8;
 			buf[4] = (offset & 0xFF);
 			erase_command_size = 5;
-		} else {  /* in 3 byte addressing mode */
+		} else { /* in 3 byte addressing mode */
 			buf[1] = (offset & 0xFF0000) >> 16;
 			buf[2] = (offset & 0xFF00) >> 8;
 			buf[3] = (offset & 0xFF);
@@ -775,8 +764,8 @@ int spi_nor_erase(const struct spi_nor_device_t *spi_nor_device,
 		}
 
 		rv = spi_transaction(
-			&spi_devices[spi_nor_device->spi_controller],
-			buf, erase_command_size, NULL, 0);
+			&spi_devices[spi_nor_device->spi_controller], buf,
+			erase_command_size, NULL, 0);
 		if (rv)
 			goto err_free;
 
@@ -814,8 +803,8 @@ int spi_nor_write(const struct spi_nor_device_t *spi_nor_device,
 
 	/* Ensure the device's page size fits in the driver's buffer, if not
 	 * emulate a smaller page size based on the buffer size. */
-	effective_page_size = MIN(spi_nor_device->page_size,
-			       CONFIG_SPI_NOR_MAX_WRITE_SIZE);
+	effective_page_size =
+		MIN(spi_nor_device->page_size, CONFIG_SPI_NOR_MAX_WRITE_SIZE);
 
 	/* Split the write into multiple writes if the size is too large. */
 	while (size > 0) {
@@ -843,7 +832,7 @@ int spi_nor_write(const struct spi_nor_device_t *spi_nor_device,
 			buf[3] = (offset & 0xFF00) >> 8;
 			buf[4] = (offset & 0xFF);
 			prefix_size = 5;
-		} else {  /* in 3 byte addressing mode */
+		} else { /* in 3 byte addressing mode */
 			buf[1] = (offset & 0xFF0000) >> 16;
 			buf[2] = (offset & 0xFF00) >> 8;
 			buf[3] = (offset & 0xFF);
@@ -853,8 +842,8 @@ int spi_nor_write(const struct spi_nor_device_t *spi_nor_device,
 		memmove(buf + prefix_size, data, write_size);
 
 		rv = spi_transaction(
-			&spi_devices[spi_nor_device->spi_controller],
-			buf, prefix_size + write_size, NULL, 0);
+			&spi_devices[spi_nor_device->spi_controller], buf,
+			prefix_size + write_size, NULL, 0);
 		if (rv)
 			goto err_free;
 
@@ -877,7 +866,7 @@ err_free:
 /* Serial NOR Flash console commands. */
 
 #ifdef CONFIG_CMD_SPI_NOR
-static int command_spi_nor_info(int argc, char **argv)
+static int command_spi_nor_info(int argc, const char **argv)
 {
 	int rv = EC_SUCCESS;
 
@@ -908,14 +897,13 @@ static int command_spi_nor_info(int argc, char **argv)
 		ccprintf("\tName: %s\n", spi_nor_device->name);
 		ccprintf("\tSPI controller index: %d\n",
 			 spi_nor_device->spi_controller);
-		ccprintf("\tTimeout: %d uSec\n",
-			 spi_nor_device->timeout_usec);
+		ccprintf("\tTimeout: %d uSec\n", spi_nor_device->timeout_usec);
 		ccprintf("\tCapacity: %d KiB\n",
 			 spi_nor_device->capacity >> 10),
-		ccprintf("\tAddressing: %s addressing mode\n",
-			 spi_nor_device->in_4b_addressing_mode ? "4B" : "3B");
-		ccprintf("\tPage Size: %d Bytes\n",
-			 spi_nor_device->page_size);
+			ccprintf("\tAddressing: %s addressing mode\n",
+				 spi_nor_device->in_4b_addressing_mode ? "4B" :
+									 "3B");
+		ccprintf("\tPage Size: %d Bytes\n", spi_nor_device->page_size);
 
 		/* Get JEDEC ID info. */
 		rv = spi_nor_read_jedec_mfn_id(spi_nor_device, &mfn_bank,
@@ -927,27 +915,26 @@ static int command_spi_nor_info(int argc, char **argv)
 
 		/* Get SFDP info. */
 		if (locate_sfdp_basic_parameter_table(
-			spi_nor_device, &sfdp_major_rev, &sfdp_minor_rev,
-			&table_major_rev, &table_minor_rev, &table_offset,
-			&table_size) != EC_SUCCESS) {
+			    spi_nor_device, &sfdp_major_rev, &sfdp_minor_rev,
+			    &table_major_rev, &table_minor_rev, &table_offset,
+			    &table_size) != EC_SUCCESS) {
 			ccputs("\tNo JEDEC SFDP support detected\n");
-			continue;  /* Go on to the next device. */
+			continue; /* Go on to the next device. */
 		}
 		ccprintf("\tSFDP v%d.%d\n", sfdp_major_rev, sfdp_minor_rev);
 		ccprintf("\tFlash Parameter Table v%d.%d (%dB @ 0x%x)\n",
-			 table_major_rev, table_minor_rev,
-			 table_size, table_offset);
+			 table_major_rev, table_minor_rev, table_size,
+			 table_offset);
 	}
 
 	return rv;
 }
-DECLARE_CONSOLE_COMMAND(spinorinfo, command_spi_nor_info,
-			"[device]",
+DECLARE_CONSOLE_COMMAND(spinorinfo, command_spi_nor_info, "[device]",
 			"Report Serial NOR Flash device information");
-#endif  /* CONFIG_CMD_SPI_NOR */
+#endif /* CONFIG_CMD_SPI_NOR */
 
 #ifdef CONFIG_CMD_SPI_NOR
-static int command_spi_nor_erase(int argc, char **argv)
+static int command_spi_nor_erase(int argc, const char **argv)
 {
 	const struct spi_nor_device_t *spi_nor_device;
 	int spi_nor_device_index;
@@ -967,17 +954,16 @@ static int command_spi_nor_erase(int argc, char **argv)
 	if (rv)
 		return rv;
 
-	ccprintf("Erasing %d bytes at 0x%x on %s...\n",
-		 size, offset, spi_nor_device->name);
+	ccprintf("Erasing %d bytes at 0x%x on %s...\n", size, offset,
+		 spi_nor_device->name);
 	return spi_nor_erase(spi_nor_device, offset, size);
 }
 DECLARE_CONSOLE_COMMAND(spinorerase, command_spi_nor_erase,
-			"device [offset] [size]",
-			"Erase flash");
-#endif  /* CONFIG_CMD_SPI_NOR */
+			"device [offset] [size]", "Erase flash");
+#endif /* CONFIG_CMD_SPI_NOR */
 
 #ifdef CONFIG_CMD_SPI_NOR
-static int command_spi_nor_write(int argc, char **argv)
+static int command_spi_nor_write(int argc, const char **argv)
 {
 	const struct spi_nor_device_t *spi_nor_device;
 	int spi_nor_device_index;
@@ -1013,8 +999,8 @@ static int command_spi_nor_write(int argc, char **argv)
 	for (i = 0; i < size; i++)
 		data[i] = i;
 
-	ccprintf("Writing %d bytes to 0x%x on %s...\n",
-		 size, offset, spi_nor_device->name);
+	ccprintf("Writing %d bytes to 0x%x on %s...\n", size, offset,
+		 spi_nor_device->name);
 	rv = spi_nor_write(spi_nor_device, offset, size, data);
 
 	/* Free the buffer */
@@ -1023,12 +1009,11 @@ static int command_spi_nor_write(int argc, char **argv)
 	return rv;
 }
 DECLARE_CONSOLE_COMMAND(spinorwrite, command_spi_nor_write,
-			"device [offset] [size]",
-			"Write pattern to flash");
-#endif  /* CONFIG_CMD_SPI_NOR */
+			"device [offset] [size]", "Write pattern to flash");
+#endif /* CONFIG_CMD_SPI_NOR */
 
 #ifdef CONFIG_CMD_SPI_NOR
-static int command_spi_nor_read(int argc, char **argv)
+static int command_spi_nor_read(int argc, const char **argv)
 {
 	const struct spi_nor_device_t *spi_nor_device;
 	int spi_nor_device_index;
@@ -1061,8 +1046,7 @@ static int command_spi_nor_read(int argc, char **argv)
 	}
 
 	/* Read the data */
-	ccprintf("Reading %d bytes from %s...",
-		 size, spi_nor_device->name);
+	ccprintf("Reading %d bytes from %s...", size, spi_nor_device->name);
 	if (spi_nor_read(spi_nor_device, offset, size, data)) {
 		rv = EC_ERROR_INVAL;
 		goto err_free;
@@ -1086,6 +1070,5 @@ err_free:
 	return rv;
 }
 DECLARE_CONSOLE_COMMAND(spinorread, command_spi_nor_read,
-			"device [offset] [size]",
-			"Read flash");
-#endif  /* CONFIG_CMD_SPI_NOR */
+			"device [offset] [size]", "Read flash");
+#endif /* CONFIG_CMD_SPI_NOR */
diff --git a/common/stillness_detector.c b/common/stillness_detector.c
index c33472aa22..c43e19873e 100644
--- a/common/stillness_detector.c
+++ b/common/stillness_detector.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,8 +23,8 @@ static bool stillness_batch_complete(struct still_det *still_det,
 				     uint32_t sample_time)
 {
 	bool complete = false;
-	uint32_t batch_window = time_until(still_det->window_start_time,
-					   sample_time);
+	uint32_t batch_window =
+		time_until(still_det->window_start_time, sample_time);
 
 	/* Checking if enough data is accumulated */
 	if (batch_window >= still_det->min_batch_window &&
@@ -51,8 +51,8 @@ static inline fp_t compute_variance(fp_t acc_squared, fp_t acc, fp_t inv)
 	return fp_mul((acc_squared - fp_mul(fp_sq(acc), inv)), inv);
 }
 
-bool still_det_update(struct still_det *still_det, uint32_t sample_time,
-		      fp_t x, fp_t y, fp_t z)
+bool still_det_update(struct still_det *still_det, uint32_t sample_time, fp_t x,
+		      fp_t y, fp_t z)
 {
 	fp_t inv = FLOAT_TO_FP(0.0f), var_x, var_y, var_z;
 	bool complete = false;
@@ -88,12 +88,12 @@ bool still_det_update(struct still_det *still_det, uint32_t sample_time,
 			return complete;
 		}
 		/* Calculating the VAR = sum(x^2)/n - sum(x)^2/n^2 */
-		var_x = compute_variance(
-			still_det->acc_xx, still_det->acc_x, inv);
-		var_y = compute_variance(
-			still_det->acc_yy, still_det->acc_y, inv);
-		var_z = compute_variance(
-			still_det->acc_zz, still_det->acc_z, inv);
+		var_x = compute_variance(still_det->acc_xx, still_det->acc_x,
+					 inv);
+		var_y = compute_variance(still_det->acc_yy, still_det->acc_y,
+					 inv);
+		var_z = compute_variance(still_det->acc_zz, still_det->acc_z,
+					 inv);
 		/* Checking if sensor is still */
 		if (var_x < still_det->var_threshold &&
 		    var_y < still_det->var_threshold &&
diff --git a/common/switch.c b/common/switch.c
index 40a5ab217f..f2a3266ed0 100644
--- a/common/switch.c
+++ b/common/switch.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,7 +19,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_SWITCH, outstr)
-#define CPRINTS(format, args...) cprints(CC_SWITCH, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SWITCH, format, ##args)
 
 static uint8_t *memmap_switches;
 
@@ -99,18 +99,14 @@ void switch_interrupt(enum gpio_signal signal)
 }
 
 #ifdef CONFIG_CMD_MMAPINFO
-static int command_mmapinfo(int argc, char **argv)
+static int command_mmapinfo(int argc, const char **argv)
 {
 	uint8_t *memmap_switches = host_get_memmap(EC_MEMMAP_SWITCHES);
 	uint8_t val = *memmap_switches;
 	int i;
 	const char *explanation[] = {
-		"lid_open",
-		"powerbtn",
-		"wp_off",
-		"kbd_rec",
-		"gpio_rec",
-		"fake_dev",
+		"lid_open", "powerbtn", "wp_off",
+		"kbd_rec",  "gpio_rec", "fake_dev",
 	};
 	ccprintf("memmap switches = 0x%x\n", val);
 	for (i = 0; i < ARRAY_SIZE(explanation); i++)
@@ -119,7 +115,6 @@ static int command_mmapinfo(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(mmapinfo, command_mmapinfo,
-			NULL,
+DECLARE_CONSOLE_COMMAND(mmapinfo, command_mmapinfo, NULL,
 			"Print memmap switch state");
 #endif
diff --git a/common/system.c b/common/system.c
index 013452c21a..b4387f5257 100644
--- a/common/system.c
+++ b/common/system.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -41,17 +41,17 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 /* Round up to a multiple of 4 */
 #define ROUNDUP4(x) (((x) + 3) & ~3)
 
 /* Data for an individual jump tag */
 struct jump_tag {
-	uint16_t tag;		/* Tag ID */
-	uint8_t data_size;	/* Size of data which follows */
-	uint8_t data_version;	/* Data version */
+	uint16_t tag; /* Tag ID */
+	uint8_t data_size; /* Size of data which follows */
+	uint8_t data_version; /* Data version */
 
 	/* Followed by data_size bytes of data */
 };
@@ -59,10 +59,10 @@ struct jump_tag {
 /* Jump data (at end of RAM, or preceding panic data) */
 static struct jump_data *jdata;
 
-static uint32_t reset_flags;  /* EC_RESET_FLAG_* */
+static uint32_t reset_flags; /* EC_RESET_FLAG_* */
 static int jumped_to_image;
-static int disable_jump;  /* Disable ALL jumps if system is locked */
-static int force_locked;  /* Force system locked even if WP isn't enabled */
+static int disable_jump; /* Disable ALL jumps if system is locked */
+static int force_locked; /* Force system locked even if WP isn't enabled */
 static enum ec_reboot_cmd reboot_at_shutdown;
 
 static enum sysinfo_flags system_info_flags;
@@ -83,8 +83,8 @@ static uint32_t ap_sku_id;
 
 #ifdef CONFIG_HOSTCMD_AP_SET_SKUID
 
-#define AP_SKUID_SYSJUMP_TAG		0x4153 /* AS */
-#define AP_SKUID_HOOK_VERSION		1
+#define AP_SKUID_SYSJUMP_TAG 0x4153 /* AS */
+#define AP_SKUID_HOOK_VERSION 1
 
 /**
  * Preserve AP SKUID across a sysjump.
@@ -109,7 +109,7 @@ static void ap_sku_id_restore_state(void)
 		AP_SKUID_SYSJUMP_TAG, &version, &size);
 
 	if (prev_ap_sku_id && version == AP_SKUID_HOOK_VERSION &&
-		size == sizeof(prev_ap_sku_id)) {
+	    size == sizeof(prev_ap_sku_id)) {
 		memcpy(&ap_sku_id, prev_ap_sku_id, sizeof(ap_sku_id));
 	}
 }
@@ -271,8 +271,8 @@ static void print_reset_flags(uint32_t flags)
 {
 	int count = 0;
 	int i;
-	static const char * const reset_flag_descs[] = {
-		#include "reset_flag_desc.inc"
+	static const char *const reset_flag_descs[] = {
+#include "reset_flag_desc.inc"
 	};
 
 	if (!flags) {
@@ -311,9 +311,8 @@ void system_print_banner(void)
 			CPRINTS("UART initialized after sysjump");
 		else
 			CPUTS("\n--- UART initialized after reboot ---\n");
-		CPRINTF("[Image: %s, %s]\n",
-			 system_get_image_copy_string(),
-			 system_get_build_info());
+		CPRINTF("[Image: %s, %s]\n", system_get_image_copy_string(),
+			system_get_build_info());
 		CPUTS("[Reset cause: ");
 		system_print_reset_flags();
 		CPUTS("]\n");
@@ -415,9 +414,8 @@ void system_disable_jump(void)
 		 */
 		ret = mpu_protect_data_ram();
 		if (ret == EC_SUCCESS) {
-			CPRINTS("data RAM locked. Exclusion %pP-%pP",
-				&__iram_text_start,
-				&__iram_text_end);
+			CPRINTS("data RAM locked. Exclusion %p-%p",
+				&__iram_text_start, &__iram_text_end);
 		} else {
 			CPRINTS("Failed to lock data RAM (%d)", ret);
 			return;
@@ -441,11 +439,11 @@ void system_disable_jump(void)
 		 */
 		switch (system_get_image_copy()) {
 		case EC_IMAGE_RO:
-			ret =  mpu_lock_rw_flash();
+			ret = mpu_lock_rw_flash();
 			copy = EC_IMAGE_RW;
 			break;
 		case EC_IMAGE_RW:
-			ret =  mpu_lock_ro_flash();
+			ret = mpu_lock_ro_flash();
 			copy = EC_IMAGE_RO;
 			break;
 		default:
@@ -453,8 +451,7 @@ void system_disable_jump(void)
 			ret = !EC_SUCCESS;
 		}
 		if (ret == EC_SUCCESS) {
-			CPRINTS("%s image locked",
-				ec_image_to_string(copy));
+			CPRINTS("%s image locked", ec_image_to_string(copy));
 		} else {
 			CPRINTS("Failed to lock %s image (%d)",
 				ec_image_to_string(copy), ret);
@@ -477,8 +474,8 @@ test_mockable enum ec_image system_get_image_copy(void)
 	/* Return which region is used in program memory */
 	return system_get_shrspi_image_copy();
 #else
-	uintptr_t my_addr = (uintptr_t)system_get_image_copy -
-			    CONFIG_PROGRAM_MEMORY_BASE;
+	uintptr_t my_addr =
+		(uintptr_t)system_get_image_copy - CONFIG_PROGRAM_MEMORY_BASE;
 
 	if (my_addr >= CONFIG_RO_MEM_OFF &&
 	    my_addr < (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE))
@@ -541,9 +538,8 @@ const char *system_get_image_copy_string(void)
 
 const char *ec_image_to_string(enum ec_image copy)
 {
-	static const char * const image_names[] = {
-		"unknown", "RO", "RW", "RO_B", "RW_B"
-	};
+	static const char *const image_names[] = { "unknown", "RO", "RW",
+						   "RO_B", "RW_B" };
 	return image_names[copy < ARRAY_SIZE(image_names) ? copy : 0];
 }
 
@@ -604,7 +600,7 @@ static void jump_to_image(uintptr_t init_addr)
 	jdata->magic = JUMP_DATA_MAGIC;
 	jdata->version = JUMP_DATA_VERSION;
 	jdata->reset_flags = reset_flags;
-	jdata->jump_tag_total = 0;  /* Reset tags */
+	jdata->jump_tag_total = 0; /* Reset tags */
 	jdata->struct_size = sizeof(struct jump_data);
 
 	/* Call other hooks; these may add tags */
@@ -619,7 +615,7 @@ static void jump_to_image(uintptr_t init_addr)
 #endif /* CONFIG_DMA */
 
 	/* Jump to the reset vector */
-	resetvec = (void(*)(void))init_addr;
+	resetvec = (void (*)(void))init_addr;
 	resetvec();
 }
 
@@ -688,8 +684,8 @@ static int system_run_image_copy_with_flags(enum ec_image copy,
 	if (copy == EC_IMAGE_RO)
 		system_clear_reset_flags(EC_RESET_FLAG_EFS);
 
-	CPRINTS("Jumping to image %s (0x%08x)",
-		ec_image_to_string(copy), system_get_reset_flags());
+	CPRINTS("Jumping to image %s (0x%08x)", ec_image_to_string(copy),
+		system_get_reset_flags());
 
 	jump_to_image(init_addr);
 
@@ -715,9 +711,9 @@ enum ec_image system_get_active_copy(void)
 
 enum ec_image system_get_update_copy(void)
 {
-#ifdef CONFIG_VBOOT_EFS		/* Not needed for EFS2, which is single-slot. */
-	return system_get_active_copy() == EC_IMAGE_RW_A ?
-			EC_IMAGE_RW_B : EC_IMAGE_RW_A;
+#ifdef CONFIG_VBOOT_EFS /* Not needed for EFS2, which is single-slot. */
+	return system_get_active_copy() == EC_IMAGE_RW_A ? EC_IMAGE_RW_B :
+							   EC_IMAGE_RW_A;
 #else
 	return EC_IMAGE_RW_A;
 #endif
@@ -764,7 +760,7 @@ const struct image_data *system_get_image_data(enum ec_image copy)
 	 * it's the same offset as in the current image.  Find that offset.
 	 */
 	addr = ((uintptr_t)&current_image_data -
-	       get_program_memory_addr(active_copy));
+		get_program_memory_addr(active_copy));
 
 	/*
 	 * Read the version information from the proper location
@@ -792,24 +788,23 @@ const struct image_data *system_get_image_data(enum ec_image copy)
 	return NULL;
 }
 
-__attribute__((weak))	   /* Weird chips may need their own implementations */
-const char *system_get_version(enum ec_image copy)
+__attribute__((weak)) /* Weird chips may need their own implementations */
+const char *
+system_get_version(enum ec_image copy)
 {
 	const struct image_data *data = system_get_image_data(copy);
 
 	return data ? data->version : "";
 }
 
-
 const char *system_get_cros_fwid(enum ec_image copy)
 {
 	const struct image_data *data;
 
 	if (IS_ENABLED(CONFIG_CROS_FWID_VERSION)) {
 		data = system_get_image_data(copy);
-		if (data &&
-		    (data->cookie3 & CROS_EC_IMAGE_DATA_COOKIE3_MASK) ==
-			    CROS_EC_IMAGE_DATA_COOKIE3)
+		if (data && (data->cookie3 & CROS_EC_IMAGE_DATA_COOKIE3_MASK) ==
+				    CROS_EC_IMAGE_DATA_COOKIE3)
 			return data->cros_fwid;
 		else
 			return CROS_FWID_MISSING_STR;
@@ -870,8 +865,9 @@ int system_get_board_version(void)
 	return board_get_version();
 }
 
-__attribute__((weak))	   /* Weird chips may need their own implementations */
-const char *system_get_build_info(void)
+__attribute__((weak)) /* Weird chips may need their own implementations */
+const char *
+system_get_build_info(void)
 {
 	return build_info;
 }
@@ -917,7 +913,7 @@ void system_common_pre_init(void)
 		 * the new fields below.
 		 */
 		if (jdata->version == 1)
-			delta = 0;  /* No tags in v1, so no need for move */
+			delta = 0; /* No tags in v1, so no need for move */
 		else if (jdata->version == 2)
 			delta = sizeof(struct jump_data) - JUMP_DATA_SIZE_V2;
 		else
@@ -975,8 +971,8 @@ static int handle_pending_reboot(enum ec_reboot_cmd cmd)
 	case EC_REBOOT_CANCEL:
 		return EC_SUCCESS;
 	case EC_REBOOT_JUMP_RO:
-		return system_run_image_copy_with_flags(EC_IMAGE_RO,
-						EC_RESET_FLAG_STAY_IN_RO);
+		return system_run_image_copy_with_flags(
+			EC_IMAGE_RO, EC_RESET_FLAG_STAY_IN_RO);
 	case EC_REBOOT_JUMP_RW:
 		return system_run_image_copy(system_get_active_copy());
 	case EC_REBOOT_COLD:
@@ -1046,7 +1042,8 @@ static int handle_pending_reboot(enum ec_reboot_cmd cmd)
 	}
 }
 
-void system_enter_hibernate(uint32_t seconds, uint32_t microseconds)
+test_mockable void system_enter_hibernate(uint32_t seconds,
+					  uint32_t microseconds)
 {
 	if (!IS_ENABLED(CONFIG_HIBERNATE))
 		return;
@@ -1059,8 +1056,8 @@ void system_enter_hibernate(uint32_t seconds, uint32_t microseconds)
 	 * this is to prevent an action triggered by developers.
 	 * See: b/192259035
 	 */
-	if (IS_ENABLED(CONFIG_EXTPOWER) && IS_ENABLED(CONFIG_AP_POWER_CONTROL)
-	    && extpower_is_present()) {
+	if (IS_ENABLED(CONFIG_EXTPOWER) &&
+	    IS_ENABLED(CONFIG_AP_POWER_CONTROL) && extpower_is_present()) {
 		CPRINTS("AC on, skip hibernate");
 		return;
 	}
@@ -1125,7 +1122,7 @@ static int sysinfo(struct ec_response_sysinfo *info)
 	return EC_SUCCESS;
 }
 
-static int command_sysinfo(int argc, char **argv)
+static int command_sysinfo(int argc, const char **argv)
 {
 	struct ec_response_sysinfo info;
 	int rv;
@@ -1160,8 +1157,7 @@ static int command_sysinfo(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_SAFE_CONSOLE_COMMAND(sysinfo, command_sysinfo,
-			     NULL,
+DECLARE_SAFE_CONSOLE_COMMAND(sysinfo, command_sysinfo, NULL,
 			     "Print system info");
 
 static enum ec_status host_command_sysinfo(struct host_cmd_handler_args *args)
@@ -1181,7 +1177,7 @@ DECLARE_HOST_COMMAND(EC_CMD_SYSINFO, host_command_sysinfo,
 #endif
 
 #ifdef CONFIG_CMD_SCRATCHPAD
-static int command_scratchpad(int argc, char **argv)
+static int command_scratchpad(int argc, const char **argv)
 {
 	int rv = EC_SUCCESS;
 	uint32_t scratchpad_value;
@@ -1207,12 +1203,11 @@ static int command_scratchpad(int argc, char **argv)
 		ccprintf("Scratchpad: 0x%08x\n", scratchpad_value);
 	return rv;
 }
-DECLARE_CONSOLE_COMMAND(scratchpad, command_scratchpad,
-			"[val]",
+DECLARE_CONSOLE_COMMAND(scratchpad, command_scratchpad, "[val]",
 			"Get or set scratchpad value");
 #endif /* CONFIG_CMD_SCRATCHPAD */
 
-__maybe_unused static int command_hibernate(int argc, char **argv)
+__maybe_unused static int command_hibernate(int argc, const char **argv)
 {
 	int seconds = 0;
 	int microseconds = 0;
@@ -1238,8 +1233,7 @@ __maybe_unused static int command_hibernate(int argc, char **argv)
 	return EC_SUCCESS;
 }
 #ifdef CONFIG_HIBERNATE
-DECLARE_CONSOLE_COMMAND(hibernate, command_hibernate,
-			"[sec] [usec]",
+DECLARE_CONSOLE_COMMAND(hibernate, command_hibernate, "[sec] [usec]",
 			"Hibernate the EC");
 #endif /* CONFIG_HIBERNATE */
 
@@ -1284,7 +1278,7 @@ static void print_build_string(void)
 	ccprintf("\n");
 }
 
-static int command_version(int argc, char **argv)
+static int command_version(int argc, const char **argv)
 {
 	int board_version;
 	const char *fw_version;
@@ -1353,12 +1347,10 @@ static int command_version(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_SAFE_CONSOLE_COMMAND(version, command_version,
-			     NULL,
-			     "Print versions");
+DECLARE_SAFE_CONSOLE_COMMAND(version, command_version, NULL, "Print versions");
 
 #ifdef CONFIG_CMD_SYSJUMP
-static int command_sysjump(int argc, char **argv)
+static int command_sysjump(int argc, const char **argv)
 {
 	uint32_t addr;
 	char *e;
@@ -1368,8 +1360,8 @@ static int command_sysjump(int argc, char **argv)
 
 	/* Handle named images */
 	if (!strcasecmp(argv[1], "RO"))
-		return system_run_image_copy_with_flags(EC_IMAGE_RO,
-						EC_RESET_FLAG_STAY_IN_RO);
+		return system_run_image_copy_with_flags(
+			EC_IMAGE_RO, EC_RESET_FLAG_STAY_IN_RO);
 	else if (!strcasecmp(argv[1], "RW") || !strcasecmp(argv[1], "A"))
 		return system_run_image_copy(EC_IMAGE_RW);
 	else if (!strcasecmp(argv[1], "B")) {
@@ -1402,7 +1394,7 @@ DECLARE_CONSOLE_COMMAND(sysjump, command_sysjump,
 			"Jump to a system image or address");
 #endif
 
-static int command_reboot(int argc, char **argv)
+static int command_reboot(int argc, const char **argv)
 {
 	int flags = SYSTEM_RESET_MANUALLY_TRIGGERED;
 	int i;
@@ -1449,13 +1441,12 @@ DECLARE_CONSOLE_COMMAND(
 	"Reboot the EC");
 
 #ifdef CONFIG_CMD_SYSLOCK
-static int command_system_lock(int argc, char **argv)
+static int command_system_lock(int argc, const char **argv)
 {
 	force_locked = 1;
 	return EC_SUCCESS;
 }
-DECLARE_SAFE_CONSOLE_COMMAND(syslock, command_system_lock,
-			     NULL,
+DECLARE_SAFE_CONSOLE_COMMAND(syslock, command_system_lock, NULL,
 			     "Lock the system, even if WP is disabled");
 #endif
 
@@ -1464,7 +1455,7 @@ DECLARE_SAFE_CONSOLE_COMMAND(syslock, command_system_lock,
  * Modify and print the sleep mask which controls access to deep sleep
  * mode in the idle task.
  */
-static int command_sleepmask(int argc, char **argv)
+static int command_sleepmask(int argc, const char **argv)
 {
 #ifdef CONFIG_CMD_SLEEPMASK_SET
 	int v;
@@ -1496,7 +1487,7 @@ DECLARE_SAFE_CONSOLE_COMMAND(sleepmask, command_sleepmask,
 #endif
 
 #ifdef CONFIG_CMD_JUMPTAGS
-static int command_jumptags(int argc, char **argv)
+static int command_jumptags(int argc, const char **argv)
 {
 	const struct jump_tag *t;
 	int used = 0;
@@ -1510,21 +1501,18 @@ static int command_jumptags(int argc, char **argv)
 		t = (const struct jump_tag *)(system_usable_ram_end() + used);
 		used += sizeof(struct jump_tag) + ROUNDUP4(t->data_size);
 
-		ccprintf("%08x: 0x%04x %c%c.%d %3d\n",
-			 (uintptr_t)t,
-			 t->tag, t->tag >> 8, (uint8_t)t->tag,
-			 t->data_version, t->data_size);
+		ccprintf("%08x: 0x%04x %c%c.%d %3d\n", (uintptr_t)t, t->tag,
+			 t->tag >> 8, (uint8_t)t->tag, t->data_version,
+			 t->data_size);
 	}
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(jumptags, command_jumptags,
-			NULL,
-			"List jump tags");
+DECLARE_CONSOLE_COMMAND(jumptags, command_jumptags, NULL, "List jump tags");
 #endif /* CONFIG_CMD_JUMPTAGS */
 
 #ifdef CONFIG_EMULATED_SYSRQ
-static int command_sysrq(int argc, char **argv)
+static int command_sysrq(int argc, const char **argv)
 {
 	char key = 'x';
 
@@ -1535,20 +1523,18 @@ static int command_sysrq(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(sysrq, command_sysrq,
-			"[key]",
+DECLARE_CONSOLE_COMMAND(sysrq, command_sysrq, "[key]",
 			"Simulate sysrq press (default: x)");
 #endif /* CONFIG_EMULATED_SYSRQ */
 
 #ifdef CONFIG_CMD_RESET_FLAGS
-static int command_rflags(int argc, char **argv)
+static int command_rflags(int argc, const char **argv)
 {
 	print_reset_flags(chip_read_reset_flags());
 	ccprintf("\n");
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(rflags, command_rflags,
-			NULL,
+DECLARE_CONSOLE_COMMAND(rflags, command_rflags, NULL,
 			"Print reset flags saved in non-volatile memory");
 #endif
 
@@ -1606,8 +1592,7 @@ host_command_get_version(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_GET_VERSION,
-		     host_command_get_version,
+DECLARE_HOST_COMMAND(EC_CMD_GET_VERSION, host_command_get_version,
 		     EC_VER_MASK(0) | EC_VER_MASK(1));
 
 #ifdef CONFIG_HOSTCMD_SKUID
@@ -1621,8 +1606,7 @@ host_command_get_sku_id(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_GET_SKU_ID,
-		     host_command_get_sku_id,
+DECLARE_HOST_COMMAND(EC_CMD_GET_SKU_ID, host_command_get_sku_id,
 		     EC_VER_MASK(0));
 #endif
 
@@ -1636,8 +1620,7 @@ host_command_set_sku_id(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_SET_SKU_ID,
-		     host_command_set_sku_id,
+DECLARE_HOST_COMMAND(EC_CMD_SET_SKU_ID, host_command_set_sku_id,
 		     EC_VER_MASK(0));
 #endif
 
@@ -1652,8 +1635,7 @@ host_command_get_keyboard_id(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_GET_KEYBOARD_ID,
-		     host_command_get_keyboard_id,
+DECLARE_HOST_COMMAND(EC_CMD_GET_KEYBOARD_ID, host_command_get_keyboard_id,
 		     EC_VER_MASK(0));
 #endif
 
@@ -1665,8 +1647,7 @@ host_command_build_info(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_GET_BUILD_INFO,
-		     host_command_build_info,
+DECLARE_HOST_COMMAND(EC_CMD_GET_BUILD_INFO, host_command_build_info,
 		     EC_VER_MASK(0));
 
 static enum ec_status
@@ -1682,8 +1663,7 @@ host_command_get_chip_info(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_GET_CHIP_INFO,
-		     host_command_get_chip_info,
+DECLARE_HOST_COMMAND(EC_CMD_GET_CHIP_INFO, host_command_get_chip_info,
 		     EC_VER_MASK(0));
 
 static enum ec_status
@@ -1703,8 +1683,7 @@ host_command_get_board_version(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_GET_BOARD_VERSION,
-		     host_command_get_board_version,
+DECLARE_HOST_COMMAND(EC_CMD_GET_BOARD_VERSION, host_command_get_board_version,
 		     EC_VER_MASK(0));
 
 static enum ec_status host_command_reboot(struct host_cmd_handler_args *args)
@@ -1738,10 +1717,8 @@ static enum ec_status host_command_reboot(struct host_cmd_handler_args *args)
 	}
 
 #ifdef HAS_TASK_HOSTCMD
-	if (p.cmd == EC_REBOOT_JUMP_RO ||
-	    p.cmd == EC_REBOOT_JUMP_RW ||
-	    p.cmd == EC_REBOOT_COLD ||
-	    p.cmd == EC_REBOOT_HIBERNATE ||
+	if (p.cmd == EC_REBOOT_JUMP_RO || p.cmd == EC_REBOOT_JUMP_RW ||
+	    p.cmd == EC_REBOOT_COLD || p.cmd == EC_REBOOT_HIBERNATE ||
 	    p.cmd == EC_REBOOT_COLD_AP_OFF) {
 		/* Clean busy bits on host for commands that won't return */
 		args->result = EC_RES_SUCCESS;
@@ -1761,21 +1738,18 @@ static enum ec_status host_command_reboot(struct host_cmd_handler_args *args)
 		return EC_RES_ERROR;
 	}
 }
-DECLARE_HOST_COMMAND(EC_CMD_REBOOT_EC,
-		     host_command_reboot,
-		     EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_REBOOT_EC, host_command_reboot, EC_VER_MASK(0));
 
 int system_can_boot_ap(void)
 {
 	int soc = -1;
 	int pow = -1;
 
-#if defined(CONFIG_BATTERY) && \
-	defined(CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON)
+#if defined(CONFIG_BATTERY) && defined(CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON)
 	/* Require a minimum battery level to power on. If battery isn't
 	 * present, battery_state_of_charge_abs returns false. */
 	if (battery_state_of_charge_abs(&soc) == EC_SUCCESS &&
-			soc >= CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON)
+	    soc >= CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON)
 		return 1;
 #endif
 
@@ -1816,7 +1790,7 @@ __overridable int board_write_serial(const char *serialno)
 	else
 		return EC_ERROR_UNIMPLEMENTED;
 }
-#endif  /* CONFIG_SERIALNO_LEN */
+#endif /* CONFIG_SERIALNO_LEN */
 
 #ifdef CONFIG_MAC_ADDR_LEN
 /* By default, read MAC address from flash, can be overridden. */
@@ -1838,10 +1812,10 @@ __overridable int board_write_mac_addr(const char *mac_addr)
 	else
 		return EC_ERROR_UNIMPLEMENTED;
 }
-#endif  /* CONFIG_MAC_ADDR_LEN */
+#endif /* CONFIG_MAC_ADDR_LEN */
 
-__attribute__((weak))
-void clock_enable_module(enum module_id module, int enable)
+__attribute__((weak)) void clock_enable_module(enum module_id module,
+					       int enable)
 {
 	/*
 	 * Default weak implementation - for chips that don't support this
@@ -1854,4 +1828,14 @@ __test_only void system_common_reset_state(void)
 	jdata = 0;
 	reset_flags = 0;
 	jumped_to_image = 0;
+	system_info_flags = 0;
+}
+
+__test_only enum ec_reboot_cmd system_common_get_reset_reboot_at_shutdown(void)
+{
+	int ret = reboot_at_shutdown;
+
+	reboot_at_shutdown = 0;
+
+	return ret;
 }
diff --git a/common/tablet_mode.c b/common/tablet_mode.c
index d6780f34a2..576e80c0ef 100644
--- a/common/tablet_mode.c
+++ b/common/tablet_mode.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,8 +13,8 @@
 #include "tablet_mode.h"
 #include "timer.h"
 
-#define CPRINTS(format, args...) cprints(CC_MOTION_LID, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_MOTION_LID, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_MOTION_LID, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_MOTION_LID, format, ##args)
 
 /*
  * Other code modules assume that notebook mode (i.e. tablet_mode = 0) at
@@ -58,7 +58,6 @@ static void notify_tablet_mode_change(void)
 	 */
 	if (IS_ENABLED(CONFIG_HOSTCMD_EVENTS))
 		host_set_single_event(EC_HOST_EVENT_MODE_CHANGE);
-
 }
 
 void tablet_set_mode(int mode, uint32_t trigger)
@@ -105,9 +104,9 @@ void tablet_disable(void)
 #endif
 static void gmr_tablet_switch_interrupt_debounce(void)
 {
-	gmr_sensor_at_360 = IS_ENABLED(CONFIG_GMR_TABLET_MODE_CUSTOM)
-				     ? board_sensor_at_360()
-				     : !gpio_get_level(GPIO_TABLET_MODE_L);
+	gmr_sensor_at_360 = IS_ENABLED(CONFIG_GMR_TABLET_MODE_CUSTOM) ?
+				    board_sensor_at_360() :
+				    !gpio_get_level(GPIO_TABLET_MODE_L);
 
 	/*
 	 * DPTF table is updated only when the board enters/exits completely
@@ -116,9 +115,9 @@ static void gmr_tablet_switch_interrupt_debounce(void)
 	 * calculation and update DPTF table when lid angle > 300 degrees.
 	 */
 	if (IS_ENABLED(CONFIG_HOSTCMD_X86) && IS_ENABLED(CONFIG_DPTF)) {
-		acpi_dptf_set_profile_num(gmr_sensor_at_360 ?
-					  DPTF_PROFILE_FLIPPED_360_MODE :
-					  DPTF_PROFILE_CLAMSHELL);
+		acpi_dptf_set_profile_num(
+			gmr_sensor_at_360 ? DPTF_PROFILE_FLIPPED_360_MODE :
+					    DPTF_PROFILE_CLAMSHELL);
 	}
 	/*
 	 * 1. Peripherals are disabled only when lid reaches 360 position (It's
@@ -142,7 +141,7 @@ static void gmr_tablet_switch_interrupt_debounce(void)
 DECLARE_DEFERRED(gmr_tablet_switch_interrupt_debounce);
 
 /* Debounce time for gmr sensor tablet mode interrupt */
-#define GMR_SENSOR_DEBOUNCE_US    (30 * MSEC)
+#define GMR_SENSOR_DEBOUNCE_US (30 * MSEC)
 
 void gmr_tablet_switch_isr(enum gpio_signal signal)
 {
@@ -175,7 +174,7 @@ void gmr_tablet_switch_disable(void)
 #endif
 
 #ifdef CONFIG_TABLET_MODE
-static int command_settabletmode(int argc, char **argv)
+static int command_settabletmode(int argc, const char **argv)
 {
 	static uint32_t tablet_mode_store;
 
@@ -206,7 +205,13 @@ static int command_settabletmode(int argc, char **argv)
 	notify_tablet_mode_change();
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(tabletmode, command_settabletmode,
-	"[on | off | reset]",
-	"Manually force tablet mode to on, off or reset.");
+DECLARE_CONSOLE_COMMAND(tabletmode, command_settabletmode, "[on | off | reset]",
+			"Manually force tablet mode to on, off or reset.");
 #endif
+
+__test_only void tablet_reset(void)
+{
+	tablet_mode = 0;
+	tablet_mode_forced = false;
+	disabled = false;
+}
diff --git a/common/temp_sensor.c b/common/temp_sensor.c
index 66ba5298dc..f2a764c151 100644
--- a/common/temp_sensor.c
+++ b/common/temp_sensor.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -44,8 +44,7 @@ static void update_mapped_memory(void)
 		 */
 		if (i == EC_TEMP_SENSOR_ENTRIES)
 			mptr = host_get_memmap(EC_MEMMAP_TEMP_SENSOR_B);
-		else if (i >= EC_TEMP_SENSOR_ENTRIES +
-			 EC_TEMP_SENSOR_B_ENTRIES)
+		else if (i >= EC_TEMP_SENSOR_ENTRIES + EC_TEMP_SENSOR_B_ENTRIES)
 			break;
 
 		switch (temp_sensor_read(i, &t)) {
@@ -143,12 +142,11 @@ int print_temps(void)
 /* Console commands */
 
 #ifdef CONFIG_CMD_TEMP_SENSOR
-static int command_temps(int argc, char **argv)
+static int command_temps(int argc, const char **argv)
 {
 	return print_temps();
 }
-DECLARE_CONSOLE_COMMAND(temps, command_temps,
-			NULL,
+DECLARE_CONSOLE_COMMAND(temps, command_temps, NULL,
 			"Print temp sensors and fan speed");
 #endif
 
@@ -172,6 +170,5 @@ temp_sensor_command_get_info(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_TEMP_SENSOR_GET_INFO,
-		     temp_sensor_command_get_info,
+DECLARE_HOST_COMMAND(EC_CMD_TEMP_SENSOR_GET_INFO, temp_sensor_command_get_info,
 		     EC_VER_MASK(0));
diff --git a/common/test_util.c b/common/test_util.c
index 37cc42000c..f15b99f302 100644
--- a/common/test_util.c
+++ b/common/test_util.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -29,23 +29,33 @@ struct test_util_tag {
 int __test_error_count;
 
 /* Weak reference function as an entry point for unit test */
-test_mockable void run_test(int argc, char **argv) { }
+test_mockable void run_test(int argc, const char **argv)
+{
+}
 
 /* Default mock test init */
-test_mockable void test_init(void) { }
+test_mockable void test_init(void)
+{
+}
 
 /* Default mock before test */
-test_mockable void before_test(void) { }
+test_mockable void before_test(void)
+{
+}
 
 /* Default mock after test */
-test_mockable void after_test(void) { }
+test_mockable void after_test(void)
+{
+}
 
 #ifdef TEST_COVERAGE
-extern void __gcov_flush(void);
+extern void __gcov_dump(void);
+extern void __gcov_reset(void);
 
 void emulator_flush(void)
 {
-	__gcov_flush();
+	__gcov_dump();
+	__gcov_reset();
 }
 #else
 void emulator_flush(void)
@@ -167,7 +177,7 @@ int test_send_host_command(int command, int version, const void *params,
 
 	return host_command_process(&args);
 }
-#endif  /* TASK_HAS_HOSTCMD */
+#endif /* TASK_HAS_HOSTCMD */
 
 /* Linear congruential pseudo random number generator */
 uint32_t prng(uint32_t seed)
@@ -188,8 +198,7 @@ static void restore_state(void)
 
 	tag = (const struct test_util_tag *)system_get_jump_tag(
 		TEST_UTIL_SYSJUMP_TAG, &version, &size);
-	if (tag && version == TEST_UTIL_SYSJUMP_VERSION &&
-	    size == sizeof(*tag))
+	if (tag && version == TEST_UTIL_SYSJUMP_VERSION && size == sizeof(*tag))
 		__test_error_count = tag->error_count;
 	else
 		__test_error_count = 0;
@@ -205,13 +214,12 @@ static void preserve_state(void)
 }
 DECLARE_HOOK(HOOK_SYSJUMP, preserve_state, HOOK_PRIO_DEFAULT);
 
-static int command_run_test(int argc, char **argv)
+static int command_run_test(int argc, const char **argv)
 {
 	run_test(argc, argv);
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(runtest, command_run_test,
-			NULL, NULL);
+DECLARE_CONSOLE_COMMAND(runtest, command_run_test, NULL, NULL);
 
 #ifndef CONFIG_ZEPHYR
 void z_ztest_run_test_suite(const char *name, struct unit_test *suite)
diff --git a/common/thermal.c b/common/thermal.c
index 50bf3e27f1..975afed3d1 100644
--- a/common/thermal.c
+++ b/common/thermal.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,7 +25,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_THERMAL, outstr)
-#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
 
 /*****************************************************************************/
 /* EC-specific thermal controls */
@@ -93,7 +93,6 @@ static void thermal_control(void)
 
 	/* go through all the sensors */
 	for (i = 0; i < TEMP_SENSOR_COUNT; ++i) {
-
 		/* read one */
 		rv = temp_sensor_read(i, &t);
 
@@ -242,30 +241,26 @@ DECLARE_HOOK(HOOK_SECOND, thermal_control, HOOK_PRIO_TEMP_SENSOR_DONE);
 /*****************************************************************************/
 /* Console commands */
 
-static int command_thermalget(int argc, char **argv)
+static int command_thermalget(int argc, const char **argv)
 {
 	int i;
 
 	ccprintf("sensor  warn  high  halt   fan_off fan_max   name\n");
 	for (i = 0; i < TEMP_SENSOR_COUNT; i++) {
 		ccprintf(" %2d      %3d   %3d    %3d    %3d     %3d     %s\n",
-			 i,
-			 thermal_params[i].temp_host[EC_TEMP_THRESH_WARN],
+			 i, thermal_params[i].temp_host[EC_TEMP_THRESH_WARN],
 			 thermal_params[i].temp_host[EC_TEMP_THRESH_HIGH],
 			 thermal_params[i].temp_host[EC_TEMP_THRESH_HALT],
 			 thermal_params[i].temp_fan_off,
-			 thermal_params[i].temp_fan_max,
-			 temp_sensors[i].name);
+			 thermal_params[i].temp_fan_max, temp_sensors[i].name);
 	}
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(thermalget, command_thermalget,
-			NULL,
+DECLARE_CONSOLE_COMMAND(thermalget, command_thermalget, NULL,
 			"Print thermal parameters (degrees Kelvin)");
 
-
-static int command_thermalset(int argc, char **argv)
+static int command_thermalset(int argc, const char **argv)
 {
 	unsigned int n;
 	int i, val;
@@ -329,8 +324,7 @@ thermal_command_set_threshold(struct host_cmd_handler_args *args)
 	return EC_RES_SUCCESS;
 }
 DECLARE_HOST_COMMAND(EC_CMD_THERMAL_SET_THRESHOLD,
-		     thermal_command_set_threshold,
-		     EC_VER_MASK(1));
+		     thermal_command_set_threshold, EC_VER_MASK(1));
 
 static enum ec_status
 thermal_command_get_threshold(struct host_cmd_handler_args *args)
@@ -346,5 +340,4 @@ thermal_command_get_threshold(struct host_cmd_handler_args *args)
 	return EC_RES_SUCCESS;
 }
 DECLARE_HOST_COMMAND(EC_CMD_THERMAL_GET_THRESHOLD,
-		     thermal_command_get_threshold,
-		     EC_VER_MASK(1));
+		     thermal_command_get_threshold, EC_VER_MASK(1));
diff --git a/common/throttle_ap.c b/common/throttle_ap.c
index 33e004ba7b..39223f9829 100644
--- a/common/throttle_ap.c
+++ b/common/throttle_ap.c
@@ -1,10 +1,11 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Common chipset throttling code for Chrome EC */
 
+#include "builtin/assert.h"
 #include "chipset.h"
 #include "common.h"
 #include "console.h"
@@ -19,15 +20,15 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_THERMAL, outstr)
-#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
 
 /*
  * When C10 deasserts, PROCHOT may also change state when the corresponding
  * power rail is turned back on. Recheck PROCHOT directly from the C10 exit
  * using a shorter debounce than the PROCHOT interrupt.
  */
-#define PROCHOT_IN_DEBOUNCE_US		(100 * MSEC)
-#define C10_IN_DEBOUNCE_US		(10 * MSEC)
+#define PROCHOT_IN_DEBOUNCE_US (100 * MSEC)
+#define C10_IN_DEBOUNCE_US (10 * MSEC)
 
 /*****************************************************************************/
 /* This enforces the virtual OR of all throttling sources. */
@@ -36,8 +37,7 @@ static uint32_t throttle_request[NUM_THROTTLE_TYPES];
 static int debounced_prochot_in;
 static const struct prochot_cfg *prochot_cfg;
 
-void throttle_ap(enum throttle_level level,
-		 enum throttle_type type,
+void throttle_ap(enum throttle_level level, enum throttle_type type,
 		 enum throttle_sources source)
 {
 	uint32_t tmpval, bitmask;
@@ -55,7 +55,7 @@ void throttle_ap(enum throttle_level level,
 		break;
 	}
 
-	tmpval = throttle_request[type];	/* save for printing */
+	tmpval = throttle_request[type]; /* save for printing */
 
 	switch (type) {
 	case THROTTLE_SOFT:
@@ -79,9 +79,8 @@ void throttle_ap(enum throttle_level level,
 	mutex_unlock(&throttle_mutex);
 
 	/* print outside the mutex */
-	CPRINTS("set AP throttling type %d to %s (0x%08x)",
-		type, tmpval ? "on" : "off", tmpval);
-
+	CPRINTS("set AP throttling type %d to %s (0x%08x)", type,
+		tmpval ? "on" : "off", tmpval);
 }
 
 void throttle_ap_config_prochot(const struct prochot_cfg *cfg)
@@ -128,7 +127,7 @@ static void prochot_input_deferred(void)
 	 * asserting low is normal behavior and not a concern
 	 * for PROCHOT# event.  Ignore all PROCHOT changes while the AP is off
 	 */
-	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF | CHIPSET_STATE_ANY_SUSPEND))
 		return;
 
 	/*
@@ -163,7 +162,7 @@ void throttle_ap_prochot_input_interrupt(enum gpio_signal signal)
 	 * any pulses that are too short.
 	 */
 	hook_call_deferred(&prochot_input_deferred_data,
-		PROCHOT_IN_DEBOUNCE_US);
+			   PROCHOT_IN_DEBOUNCE_US);
 }
 
 #ifdef CONFIG_CPU_PROCHOT_GATE_ON_C10
@@ -181,7 +180,7 @@ void throttle_ap_c10_input_interrupt(enum gpio_signal signal)
 /*****************************************************************************/
 /* Console commands */
 #ifdef CONFIG_CMD_APTHROTTLE
-static int command_apthrottle(int argc, char **argv)
+static int command_apthrottle(int argc, const char **argv)
 {
 	int i;
 	uint32_t tmpval;
@@ -197,7 +196,6 @@ static int command_apthrottle(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(apthrottle, command_apthrottle,
-			NULL,
+DECLARE_CONSOLE_COMMAND(apthrottle, command_apthrottle, NULL,
 			"Display the AP throttling state");
 #endif
diff --git a/common/timer.c b/common/timer.c
index a8d02e7ece..eea773619b 100644
--- a/common/timer.c
+++ b/common/timer.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,6 +6,7 @@
 /* Timer module for Chrome EC operating system */
 
 #include "atomic.h"
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
 #include "hooks.h"
@@ -19,19 +20,19 @@
 #ifdef CONFIG_ZEPHYR
 #include <zephyr/kernel.h> /* For k_usleep() */
 #else
-extern __error("k_usleep() should only be called from Zephyr code")
-int32_t k_usleep(int32_t);
+extern __error("k_usleep() should only be called from Zephyr code") int32_t
+	k_usleep(int32_t);
 #endif /* CONFIG_ZEPHYR */
 
 #ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 #else
 #define CPRINTS(format, args...)
 #define CPRINTF(format, args...)
 #endif
 
-#define TIMER_SYSJUMP_TAG 0x4d54  /* "TM" */
+#define TIMER_SYSJUMP_TAG 0x4d54 /* "TM" */
 
 /* High 32-bits of the 64-bit timestamp counter. */
 STATIC_IF_NOT(CONFIG_HWTIMER_64BIT) volatile uint32_t clksrc_high;
@@ -82,7 +83,6 @@ void process_timers(int overflow)
 			/* read atomically the current state of timer running */
 			check_timer = running_t0 = timer_running;
 			while (check_timer) {
-
 				int tskid = __fls(check_timer);
 				/* timer has expired ? */
 				if (timer_deadline[tskid].val <= now.val)
@@ -95,7 +95,7 @@ void process_timers(int overflow)
 
 				check_timer &= ~BIT(tskid);
 			}
-		/* if there is a new timer, let's retry */
+			/* if there is a new timer, let's retry */
 		} while (timer_running & ~running_t0);
 
 		if (next.le.hi == 0xffffffff) {
@@ -203,7 +203,7 @@ void usleep(unsigned us)
 	do {
 		evt |= task_wait_event(us);
 	} while (!(evt & TASK_EVENT_TIMER) &&
-		((__hw_clock_source_read() - t0) < us));
+		 ((__hw_clock_source_read() - t0) < us));
 
 	/* Re-queue other events which happened in the meanwhile */
 	if (evt)
@@ -246,7 +246,7 @@ timestamp_t get_time(void)
 clock_t clock(void)
 {
 	/* __hw_clock_source_read() returns a microsecond resolution timer.*/
-	return (clock_t) __hw_clock_source_read() / 1000;
+	return (clock_t)__hw_clock_source_read() / 1000;
 }
 
 void force_time(timestamp_t ts)
@@ -299,8 +299,7 @@ void __hw_clock_source_set(uint32_t ts)
 void timer_print_info(void)
 {
 	timestamp_t t = get_time();
-	uint64_t deadline = (uint64_t)t.le.hi << 32 |
-		__hw_clock_event_get();
+	uint64_t deadline = (uint64_t)t.le.hi << 32 | __hw_clock_event_get();
 	int tskid;
 
 	ccprintf("Time:     0x%016llx us, %11.6lld s\n"
@@ -354,7 +353,7 @@ static void timer_sysjump(void)
 DECLARE_HOOK(HOOK_SYSJUMP, timer_sysjump, HOOK_PRIO_DEFAULT);
 
 #ifdef CONFIG_CMD_WAITMS
-static int command_wait(int argc, char **argv)
+static int command_wait(int argc, const char **argv)
 {
 	char *e;
 	int i;
@@ -366,6 +365,9 @@ static int command_wait(int argc, char **argv)
 	if (*e)
 		return EC_ERROR_PARAM1;
 
+	if (i < 0)
+		return EC_ERROR_PARAM1;
+
 	/*
 	 * Reload the watchdog so that issuing multiple small waitms commands
 	 * quickly one after the other will not cause a reset.
@@ -384,8 +386,7 @@ static int command_wait(int argc, char **argv)
 	return EC_SUCCESS;
 }
 /* Typically a large delay (e.g. 3s) will cause a reset */
-DECLARE_CONSOLE_COMMAND(waitms, command_wait,
-			"msec",
+DECLARE_CONSOLE_COMMAND(waitms, command_wait, "msec",
 			"Busy-wait for msec (large delays will reset)");
 #endif
 
@@ -395,7 +396,7 @@ DECLARE_CONSOLE_COMMAND(waitms, command_wait,
  * especially when going "backward" in time, because task deadlines are
  * left un-adjusted.
  */
-static int command_force_time(int argc, char **argv)
+static int command_force_time(int argc, const char **argv)
 {
 	char *e;
 	timestamp_t new;
@@ -416,32 +417,29 @@ static int command_force_time(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(forcetime, command_force_time,
-			"hi lo",
+DECLARE_CONSOLE_COMMAND(forcetime, command_force_time, "hi lo",
 			"Force current time");
 #endif
 
 #ifdef CONFIG_CMD_GETTIME
-static int command_get_time(int argc, char **argv)
+static int command_get_time(int argc, const char **argv)
 {
 	timestamp_t ts = get_time();
 	ccprintf("Time: 0x%016llx = %.6lld s\n", ts.val, ts.val);
 
 	return EC_SUCCESS;
 }
-DECLARE_SAFE_CONSOLE_COMMAND(gettime, command_get_time,
-			     NULL,
+DECLARE_SAFE_CONSOLE_COMMAND(gettime, command_get_time, NULL,
 			     "Print current time");
 #endif
 
 #ifdef CONFIG_CMD_TIMERINFO
-static int command_timer_info(int argc, char **argv)
+static int command_timer_info(int argc, const char **argv)
 {
 	timer_print_info();
 
 	return EC_SUCCESS;
 }
-DECLARE_SAFE_CONSOLE_COMMAND(timerinfo, command_timer_info,
-			     NULL,
+DECLARE_SAFE_CONSOLE_COMMAND(timerinfo, command_timer_info, NULL,
 			     "Print timer info");
 #endif
diff --git a/common/typec_control.c b/common/typec_control.c
index 1fea258389..94070d47df 100644
--- a/common/typec_control.c
+++ b/common/typec_control.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -28,7 +28,7 @@ void typec_set_sbu(int port, bool enable)
 }
 
 __overridable void typec_set_source_current_limit(int port,
-						enum tcpc_rp_value rp)
+						  enum tcpc_rp_value rp)
 {
 	if (IS_ENABLED(CONFIG_USBC_PPC))
 		ppc_set_vbus_source_current_limit(port, rp);
@@ -45,8 +45,8 @@ void typec_set_vconn(int port, bool enable)
 	 * the PD state machine detects a disconnection on the CC lines, we will
 	 * reset our OC event counter.
 	 */
-	if (IS_ENABLED(CONFIG_USBC_OCP) &&
-	    enable && usbc_ocp_is_port_latched_off(port))
+	if (IS_ENABLED(CONFIG_USBC_OCP) && enable &&
+	    usbc_ocp_is_port_latched_off(port))
 		return;
 
 	/*
diff --git a/common/uart_buffering.c b/common/uart_buffering.c
index d993eab345..1aa6e9ef35 100644
--- a/common/uart_buffering.c
+++ b/common/uart_buffering.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,7 +22,7 @@
 /* Macros to advance in the circular buffers */
 #define TX_BUF_NEXT(i) (((i) + 1) & (CONFIG_UART_TX_BUF_SIZE - 1))
 #define RX_BUF_NEXT(i) (((i) + 1) & (CONFIG_UART_RX_BUF_SIZE - 1))
-#define RX_BUF_PREV(i) (((i) - 1) & (CONFIG_UART_RX_BUF_SIZE - 1))
+#define RX_BUF_PREV(i) (((i)-1) & (CONFIG_UART_RX_BUF_SIZE - 1))
 
 /* Macros to calculate difference of pointers in the circular buffers. */
 #define TX_BUF_DIFF(i, j) (((i) - (j)) & (CONFIG_UART_TX_BUF_SIZE - 1))
@@ -37,12 +37,12 @@ BUILD_ASSERT((CONFIG_UART_RX_BUF_SIZE & (CONFIG_UART_RX_BUF_SIZE - 1)) == 0);
  * of input has been detected by the normal tick task.  There will be
  * CONFIG_UART_RX_DMA_RECHECKS rechecks between this tick and the next tick.
  */
-#define RX_DMA_RECHECK_INTERVAL (HOOK_TICK_INTERVAL /			\
-				 (CONFIG_UART_RX_DMA_RECHECKS + 1))
+#define RX_DMA_RECHECK_INTERVAL \
+	(HOOK_TICK_INTERVAL / (CONFIG_UART_RX_DMA_RECHECKS + 1))
 
 /* Transmit and receive buffers */
-static volatile char tx_buf[CONFIG_UART_TX_BUF_SIZE]
-			__uncached __preserved_logs(tx_buf);
+static volatile char tx_buf[CONFIG_UART_TX_BUF_SIZE] __uncached
+	__preserved_logs(tx_buf);
 static volatile int tx_buf_head __preserved_logs(tx_buf_head);
 static volatile int tx_buf_tail __preserved_logs(tx_buf_tail);
 static volatile char rx_buf[CONFIG_UART_RX_BUF_SIZE] __uncached;
@@ -59,7 +59,6 @@ static int uart_buffer_calc_checksum(void)
 	return tx_buf_head ^ tx_buf_tail;
 }
 
-
 void uart_init_buffer(void)
 {
 	if (tx_checksum != uart_buffer_calc_checksum() ||
@@ -81,8 +80,8 @@ int uart_tx_char_raw(void *context, int c)
 	int tx_buf_next, tx_buf_new_tail;
 
 #if defined CONFIG_POLLING_UART
-	(void) tx_buf_next;
-	(void) tx_buf_new_tail;
+	(void)tx_buf_next;
+	(void)tx_buf_new_tail;
 	uart_write_char(c);
 #else
 
@@ -137,7 +136,7 @@ void uart_process_output(void)
 	/* If a previous DMA transfer completed, free up the buffer it used */
 	if (tx_dma_in_progress) {
 		tx_buf_tail = (tx_buf_tail + tx_dma_in_progress) &
-			(CONFIG_UART_TX_BUF_SIZE - 1);
+			      (CONFIG_UART_TX_BUF_SIZE - 1);
 		tx_dma_in_progress = 0;
 
 		if (IS_ENABLED(CONFIG_PRESERVE_LOGS))
@@ -154,8 +153,9 @@ void uart_process_output(void)
 	 * Get the largest contiguous block of output.  If the transmit buffer
 	 * wraps, only use the part before the wrap.
 	 */
-	tx_dma_in_progress = (head > tx_buf_tail ? head :
-			      CONFIG_UART_TX_BUF_SIZE) - tx_buf_tail;
+	tx_dma_in_progress =
+		(head > tx_buf_tail ? head : CONFIG_UART_TX_BUF_SIZE) -
+		tx_buf_tail;
 
 	uart_tx_dma_start((char *)(tx_buf + tx_buf_tail), tx_dma_in_progress);
 }
@@ -181,7 +181,7 @@ void uart_process_output(void)
 #endif /* !CONFIG_UART_TX_DMA */
 
 #ifdef CONFIG_UART_RX_DMA
-#ifdef CONFIG_UART_INPUT_FILTER  /* TODO(crosbug.com/p/36745): */
+#ifdef CONFIG_UART_INPUT_FILTER /* TODO(crosbug.com/p/36745): */
 #error "Filtering the UART input with DMA enabled is NOT SUPPORTED!"
 #endif
 
@@ -245,7 +245,7 @@ void uart_process_input(void)
 
 void uart_clear_input(void)
 {
-	int scratch __attribute__ ((unused));
+	int scratch __attribute__((unused));
 	while (uart_rx_available())
 		scratch = uart_read_char();
 	rx_buf_head = rx_buf_tail = 0;
@@ -347,9 +347,7 @@ enum ec_status uart_console_read_buffer_init(void)
 	return EC_RES_SUCCESS;
 }
 
-int uart_console_read_buffer(uint8_t type,
-			     char *dest,
-			     uint16_t dest_size,
+int uart_console_read_buffer(uint8_t type, char *dest, uint16_t dest_size,
 			     uint16_t *write_count)
 {
 	int *tail;
@@ -371,7 +369,6 @@ int uart_console_read_buffer(uint8_t type,
 
 	/* Copy data to response */
 	while (*tail != tx_snapshot_head && *write_count < dest_size - 1) {
-
 		/*
 		 * Copy only non-zero bytes, so that we don't copy unused
 		 * bytes if the buffer hasn't completely rolled at boot.
diff --git a/common/uart_hostcmd.c b/common/uart_hostcmd.c
index 5cef2a8e24..7b4ff5b461 100644
--- a/common/uart_hostcmd.c
+++ b/common/uart_hostcmd.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/common/uart_printf.c b/common/uart_printf.c
index 198d076971..6f8ebb5cbc 100644
--- a/common/uart_printf.c
+++ b/common/uart_printf.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/common/update_fw.c b/common/update_fw.c
index 068758e7b0..85b805191c 100644
--- a/common/update_fw.c
+++ b/common/update_fw.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,13 +25,13 @@
 #include "touchpad_fw_hash.h"
 
 BUILD_ASSERT(sizeof(touchpad_fw_hashes) ==
-		(CONFIG_TOUCHPAD_FW_CHUNKS * SHA256_DIGEST_SIZE));
+	     (CONFIG_TOUCHPAD_FW_CHUNKS * SHA256_DIGEST_SIZE));
 BUILD_ASSERT(sizeof(touchpad_fw_hashes[0]) == SHA256_DIGEST_SIZE);
 
 BUILD_ASSERT(sizeof(touchpad_fw_full_hash) == SHA256_DIGEST_SIZE);
 #endif
 
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args)
 
 /* Section to be updated (i.e. not the current section). */
 struct {
@@ -47,9 +47,8 @@ struct {
 static int is_touchpad_block(uint32_t block_offset, size_t body_size)
 {
 	return (block_offset >= CONFIG_TOUCHPAD_VIRTUAL_OFF) &&
-	       (block_offset + body_size) <=
-			(CONFIG_TOUCHPAD_VIRTUAL_OFF +
-				CONFIG_TOUCHPAD_VIRTUAL_SIZE);
+	       (block_offset + body_size) <= (CONFIG_TOUCHPAD_VIRTUAL_OFF +
+					      CONFIG_TOUCHPAD_VIRTUAL_SIZE);
 }
 #endif
 
@@ -71,17 +70,15 @@ static uint8_t check_update_chunk(uint32_t block_offset, size_t body_size)
 	if (update_section.base_offset != update_section.top_offset &&
 	    (block_offset >= update_section.base_offset) &&
 	    ((block_offset + body_size) <= update_section.top_offset)) {
-
 		base = update_section.base_offset;
-		size = update_section.top_offset -
-			 update_section.base_offset;
+		size = update_section.top_offset - update_section.base_offset;
 		/*
 		 * If this is the first chunk for this section, it needs to
 		 * be erased.
 		 */
 		if (block_offset == base) {
 			if (crec_flash_physical_erase(base, size) !=
-				EC_SUCCESS) {
+			    EC_SUCCESS) {
 				CPRINTF("%s:%d erase failure of 0x%x..+0x%x\n",
 					__func__, __LINE__, base, size);
 				return UPDATE_ERASE_FAILURE;
@@ -96,14 +93,11 @@ static uint8_t check_update_chunk(uint32_t block_offset, size_t body_size)
 		return UPDATE_SUCCESS;
 #endif
 
-	CPRINTF("%s:%d %x, %d section base %x top %x\n",
-		__func__, __LINE__,
-		block_offset, body_size,
-		update_section.base_offset,
+	CPRINTF("%s:%d %x, %d section base %x top %x\n", __func__, __LINE__,
+		block_offset, body_size, update_section.base_offset,
 		update_section.top_offset);
 
 	return UPDATE_BAD_ADDR;
-
 }
 
 int update_pdu_valid(struct update_command *cmd_body, size_t cmd_size)
@@ -120,8 +114,8 @@ static void new_chunk_written(uint32_t block_offset)
 {
 }
 
-static int contents_allowed(uint32_t block_offset,
-			    size_t body_size, void *update_data)
+static int contents_allowed(uint32_t block_offset, size_t body_size,
+			    void *update_data)
 {
 #if defined(CONFIG_TOUCHPAD_VIRTUAL_OFF) && defined(CONFIG_TOUCHPAD_HASH_FW)
 	if (is_touchpad_block(block_offset, body_size)) {
@@ -132,9 +126,9 @@ static int contents_allowed(uint32_t block_offset,
 		int good = 0;
 
 		if (chunk >= CONFIG_TOUCHPAD_FW_CHUNKS ||
-				(fw_offset % CONFIG_UPDATE_PDU_SIZE) != 0) {
-			CPRINTF("%s: TP invalid offset %08x\n",
-				__func__, fw_offset);
+		    (fw_offset % CONFIG_UPDATE_PDU_SIZE) != 0) {
+			CPRINTF("%s: TP invalid offset %08x\n", __func__,
+				fw_offset);
 			return 0;
 		}
 
@@ -143,10 +137,10 @@ static int contents_allowed(uint32_t block_offset,
 		tmp = SHA256_final(&ctx);
 
 		good = !memcmp(tmp, touchpad_fw_hashes[chunk],
-				SHA256_DIGEST_SIZE);
+			       SHA256_DIGEST_SIZE);
 
-		CPRINTF("%s: TP %08x %02x..%02x (%s)\n", __func__,
-			fw_offset, tmp[0], tmp[31], good ? "GOOD" : "BAD");
+		CPRINTF("%s: TP %08x %02x..%02x (%s)\n", __func__, fw_offset,
+			tmp[0], tmp[31], good ? "GOOD" : "BAD");
 
 		return good;
 	}
@@ -194,7 +188,7 @@ void fw_update_start(struct first_response_pdu *rpdu)
 	rpdu->common.offset = htobe32(update_section.base_offset);
 	if (version)
 		memcpy(rpdu->common.version, version,
-			sizeof(rpdu->common.version));
+		       sizeof(rpdu->common.version));
 
 #ifdef CONFIG_ROLLBACK
 	rpdu->common.min_rollback = htobe32(rollback_get_minimum_version());
@@ -216,13 +210,12 @@ void fw_update_start(struct first_response_pdu *rpdu)
 #endif
 }
 
-void fw_update_command_handler(void *body,
-			       size_t cmd_size,
+void fw_update_command_handler(void *body, size_t cmd_size,
 			       size_t *response_size)
 {
 	struct update_command *cmd_body = body;
 	void *update_data;
-	uint8_t *error_code = body;  /* Cache the address for code clarity. */
+	uint8_t *error_code = body; /* Cache the address for code clarity. */
 	size_t body_size;
 	uint32_t block_offset;
 
@@ -285,11 +278,11 @@ void fw_update_command_handler(void *body,
 #ifdef CONFIG_TOUCHPAD_VIRTUAL_OFF
 	if (is_touchpad_block(block_offset, body_size)) {
 		if (touchpad_update_write(
-				block_offset - CONFIG_TOUCHPAD_VIRTUAL_OFF,
-				body_size, update_data)	!= EC_SUCCESS) {
+			    block_offset - CONFIG_TOUCHPAD_VIRTUAL_OFF,
+			    body_size, update_data) != EC_SUCCESS) {
 			*error_code = UPDATE_WRITE_FAILURE;
-			CPRINTF("%s:%d update write error\n",
-				__func__, __LINE__);
+			CPRINTF("%s:%d update write error\n", __func__,
+				__LINE__);
 			return;
 		}
 
@@ -301,8 +294,8 @@ void fw_update_command_handler(void *body,
 #endif
 
 	CPRINTF("update: 0x%x\n", block_offset + CONFIG_PROGRAM_MEMORY_BASE);
-	if (crec_flash_physical_write(block_offset, body_size, update_data)
-	    != EC_SUCCESS) {
+	if (crec_flash_physical_write(block_offset, body_size, update_data) !=
+	    EC_SUCCESS) {
 		*error_code = UPDATE_WRITE_FAILURE;
 		CPRINTF("%s:%d update write error\n", __func__, __LINE__);
 		return;
@@ -311,12 +304,12 @@ void fw_update_command_handler(void *body,
 	new_chunk_written(block_offset);
 
 	/* Verify that data was written properly. */
-	if (memcmp(update_data, (void *)
-		   (block_offset + CONFIG_PROGRAM_MEMORY_BASE),
+	if (memcmp(update_data,
+		   (void *)(block_offset + CONFIG_PROGRAM_MEMORY_BASE),
 		   body_size)) {
 		*error_code = UPDATE_VERIFY_ERROR;
-		CPRINTF("%s:%d update verification error\n",
-			__func__, __LINE__);
+		CPRINTF("%s:%d update verification error\n", __func__,
+			__LINE__);
 		return;
 	}
 
diff --git a/common/uptime.c b/common/uptime.c
index 3c3be3e55c..3b2c68fd34 100644
--- a/common/uptime.c
+++ b/common/uptime.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -32,14 +32,12 @@ host_command_get_uptime_info(struct host_cmd_handler_args *args)
 	r->ec_reset_flags = system_get_reset_flags();
 
 	memset(r->recent_ap_reset, 0, sizeof(r->recent_ap_reset));
-	rc = get_ap_reset_stats(recent_ap_reset,
-				ARRAY_SIZE(r->recent_ap_reset),
+	rc = get_ap_reset_stats(recent_ap_reset, ARRAY_SIZE(r->recent_ap_reset),
 				&ap_resets_since_ec_boot);
 
 	r->ap_resets_since_ec_boot = ap_resets_since_ec_boot;
 	args->response_size = sizeof(*r);
 	return rc == EC_SUCCESS ? EC_RES_SUCCESS : EC_RES_ERROR;
 }
-DECLARE_HOST_COMMAND(EC_CMD_GET_UPTIME_INFO,
-	host_command_get_uptime_info,
-	EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_GET_UPTIME_INFO, host_command_get_uptime_info,
+		     EC_VER_MASK(0));
diff --git a/common/usb_charger.c b/common/usb_charger.c
index d0b6dd3ca1..60deade0ef 100644
--- a/common/usb_charger.c
+++ b/common/usb_charger.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,6 +12,7 @@
  * is necessary to update charge_manager with detected charger attributes.
  */
 
+#include "builtin/assert.h"
 #include "charge_manager.h"
 #include "charger.h"
 #include "common.h"
@@ -48,7 +49,7 @@ BUILD_ASSERT(BIT(3) == TASK_EVENT_CUSTOM_BIT(3));
 
 static void update_vbus_supplier(int port, int vbus_level)
 {
-	struct charge_port_info charge = {0};
+	struct charge_port_info charge = { 0 };
 
 	if (vbus_level && !usb_charger_port_is_sourcing_vbus(port)) {
 		charge.voltage = USB_CHARGER_VOLTAGE_MV;
@@ -104,7 +105,7 @@ void usb_charger_vbus_change(int port, int vbus_level)
 #endif
 
 	if ((get_usb_pd_vbus_detect() == USB_PD_VBUS_DETECT_CHARGER) ||
-		(get_usb_pd_vbus_detect() == USB_PD_VBUS_DETECT_PPC)) {
+	    (get_usb_pd_vbus_detect() == USB_PD_VBUS_DETECT_PPC)) {
 		/* USB PD task */
 		task_wake(PD_PORT_TO_TASK_ID(port));
 	}
@@ -112,29 +113,14 @@ void usb_charger_vbus_change(int port, int vbus_level)
 
 void usb_charger_reset_charge(int port)
 {
-	charge_manager_update_charge(CHARGE_SUPPLIER_PROPRIETARY,
-				     port, NULL);
-	charge_manager_update_charge(CHARGE_SUPPLIER_BC12_CDP,
-				     port, NULL);
-	charge_manager_update_charge(CHARGE_SUPPLIER_BC12_DCP,
-				     port, NULL);
-	charge_manager_update_charge(CHARGE_SUPPLIER_BC12_SDP,
-				     port, NULL);
-	charge_manager_update_charge(CHARGE_SUPPLIER_OTHER,
-				     port, NULL);
+	charge_manager_update_charge(CHARGE_SUPPLIER_PROPRIETARY, port, NULL);
+	charge_manager_update_charge(CHARGE_SUPPLIER_BC12_CDP, port, NULL);
+	charge_manager_update_charge(CHARGE_SUPPLIER_BC12_DCP, port, NULL);
+	charge_manager_update_charge(CHARGE_SUPPLIER_BC12_SDP, port, NULL);
+	charge_manager_update_charge(CHARGE_SUPPLIER_OTHER, port, NULL);
 #if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
-	charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED,
-				     port, NULL);
+	charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED, port, NULL);
 #endif
-#ifdef CONFIG_WIRELESS_CHARGER_P9221_R7
-	charge_manager_update_charge(CHARGE_SUPPLIER_WPC_BPP,
-				     port, NULL);
-	charge_manager_update_charge(CHARGE_SUPPLIER_WPC_EPP,
-				     port, NULL);
-	charge_manager_update_charge(CHARGE_SUPPLIER_WPC_GPP,
-				     port, NULL);
-#endif
-
 }
 
 void usb_charger_task_set_event(int port, uint8_t event)
@@ -185,8 +171,7 @@ void usb_charger_task_shared(void *u)
 			}
 
 			port_evt = PORT_EVENT_UNPACK(
-					port,
-					atomic_get(&usb_charger_port_events));
+				port, atomic_get(&usb_charger_port_events));
 			atomic_and(&usb_charger_port_events,
 				   ~PORT_EVENT_PACK(port, port_evt));
 
diff --git a/common/usb_common.c b/common/usb_common.c
index 12316f5ca3..805bc5d551 100644
--- a/common/usb_common.c
+++ b/common/usb_common.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -36,8 +36,8 @@
 #include "util.h"
 
 #ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
 #else
 #define CPRINTS(format, args...)
 #define CPRINTF(format, args...)
@@ -78,7 +78,7 @@ int hex8tou32(char *str, uint32_t *val)
 int remote_flashing(int argc, char **argv)
 {
 	int port, cnt, cmd;
-	uint32_t data[VDO_MAX_SIZE-1];
+	uint32_t data[VDO_MAX_SIZE - 1];
 	char *e;
 	static int flash_offset[CONFIG_USB_PD_PORT_MAX_COUNT];
 
@@ -111,12 +111,11 @@ int remote_flashing(int argc, char **argv)
 
 		argc -= 3;
 		for (i = 0; i < argc; i++)
-			if (hex8tou32(argv[i+3], data + i))
+			if (hex8tou32(argv[i + 3], data + i))
 				return EC_ERROR_INVAL;
 		cmd = VDO_CMD_FLASH_WRITE;
 		cnt = argc;
-		ccprintf("WRITE %d @%04x ...", argc * 4,
-			 flash_offset[port]);
+		ccprintf("WRITE %d @%04x ...", argc * 4, flash_offset[port]);
 		flash_offset[port] += argc * 4;
 	}
 
@@ -124,7 +123,7 @@ int remote_flashing(int argc, char **argv)
 
 	/* Wait until VDM is done */
 	while (pd[port].vdm_state > 0)
-		task_wait_event(100*MSEC);
+		task_wait_event(100 * MSEC);
 
 	ccprintf("DONE %d\n", pd[port].vdm_state);
 	return EC_SUCCESS;
@@ -151,11 +150,10 @@ bool pd_firmware_upgrade_check_power_readiness(int port)
 		 */
 		battery_get_params(&batt);
 		if (batt.flags & BATT_FLAG_BAD_STATE_OF_CHARGE ||
-			batt.state_of_charge <
-				MIN_BATTERY_FOR_PD_UPGRADE_PERCENT) {
+		    batt.state_of_charge < MIN_BATTERY_FOR_PD_UPGRADE_PERCENT) {
 			CPRINTS("C%d: Cannot suspend for upgrade, not "
-					"enough battery (%d%%)!",
-					port, batt.state_of_charge);
+				"enough battery (%d%%)!",
+				port, batt.state_of_charge);
 			return false;
 		}
 	} else {
@@ -181,8 +179,8 @@ int usb_get_battery_soc(void)
 #endif
 }
 
-#if defined(CONFIG_USB_PD_PREFER_MV) && defined(PD_PREFER_LOW_VOLTAGE) + \
-	defined(PD_PREFER_HIGH_VOLTAGE) > 1
+#if defined(CONFIG_USB_PD_PREFER_MV) && \
+	defined(PD_PREFER_LOW_VOLTAGE) + defined(PD_PREFER_HIGH_VOLTAGE) > 1
 #error "PD preferred voltage strategy should be mutually exclusive."
 #endif
 
@@ -200,7 +198,8 @@ int usb_get_battery_soc(void)
  */
 
 typec_current_t usb_get_typec_current_limit(enum tcpc_cc_polarity polarity,
-	enum tcpc_cc_voltage_status cc1, enum tcpc_cc_voltage_status cc2)
+					    enum tcpc_cc_voltage_status cc1,
+					    enum tcpc_cc_voltage_status cc2)
 {
 	typec_current_t charge = 0;
 	enum tcpc_cc_voltage_status cc;
@@ -236,7 +235,7 @@ typec_current_t usb_get_typec_current_limit(enum tcpc_cc_polarity polarity,
 }
 
 enum tcpc_cc_polarity get_snk_polarity(enum tcpc_cc_voltage_status cc1,
-	enum tcpc_cc_voltage_status cc2)
+				       enum tcpc_cc_voltage_status cc2)
 {
 	/* The following assumes:
 	 *
@@ -251,13 +250,13 @@ enum tcpc_cc_polarity get_snk_polarity(enum tcpc_cc_voltage_status cc1,
 }
 
 enum tcpc_cc_polarity get_src_polarity(enum tcpc_cc_voltage_status cc1,
-	enum tcpc_cc_voltage_status cc2)
+				       enum tcpc_cc_voltage_status cc2)
 {
 	return (cc1 == TYPEC_CC_VOLT_RD) ? POLARITY_CC1 : POLARITY_CC2;
 }
 
-enum pd_cc_states pd_get_cc_state(
-	enum tcpc_cc_voltage_status cc1, enum tcpc_cc_voltage_status cc2)
+enum pd_cc_states pd_get_cc_state(enum tcpc_cc_voltage_status cc1,
+				  enum tcpc_cc_voltage_status cc2)
 {
 	/* Port partner is a SNK */
 	if (cc_is_snk_dbg_acc(cc1, cc2))
@@ -289,7 +288,7 @@ bool pd_is_debug_acc(int port)
 	enum pd_cc_states cc_state = pd_get_task_cc_state(port);
 
 	return cc_state == PD_CC_UFP_DEBUG_ACC ||
-		cc_state == PD_CC_DFP_DEBUG_ACC;
+	       cc_state == PD_CC_DFP_DEBUG_ACC;
 }
 
 __overridable int pd_board_check_request(uint32_t rdo, int pdo_cnt)
@@ -303,7 +302,7 @@ int pd_get_source_pdo(const uint32_t **src_pdo_p, const int port)
 	const uint32_t *src_pdo;
 	const int pdo_cnt = dpm_get_source_pdo(&src_pdo, port);
 #elif defined(CONFIG_USB_PD_DYNAMIC_SRC_CAP) || \
-		defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT)
+	defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT)
 	const uint32_t *src_pdo;
 	const int pdo_cnt = charge_manager_get_source_pdo(&src_pdo, port);
 #else
@@ -346,8 +345,8 @@ int pd_check_requested_voltage(uint32_t rdo, const int port)
 		return EC_ERROR_INVAL; /* too much max current */
 
 	CPRINTF("Requested %d mV %d mA (for %d/%d mA)\n",
-		 ((pdo >> 10) & 0x3ff) * 50, (pdo & 0x3ff) * 10,
-		 op_ma * 10, max_ma * 10);
+		((pdo >> 10) & 0x3ff) * 50, (pdo & 0x3ff) * 10, op_ma * 10,
+		max_ma * 10);
 
 	/* Accept the requested voltage */
 	return EC_SUCCESS;
@@ -382,16 +381,12 @@ int pd_get_retry_count(int port, enum tcpci_msg_type type)
 }
 
 enum pd_drp_next_states drp_auto_toggle_next_state(
-	uint64_t *drp_sink_time,
-	enum pd_power_role power_role,
-	enum pd_dual_role_states drp_state,
-	enum tcpc_cc_voltage_status cc1,
-	enum tcpc_cc_voltage_status cc2,
-	bool auto_toggle_supported)
+	uint64_t *drp_sink_time, enum pd_power_role power_role,
+	enum pd_dual_role_states drp_state, enum tcpc_cc_voltage_status cc1,
+	enum tcpc_cc_voltage_status cc2, bool auto_toggle_supported)
 {
 	const bool hardware_debounced_unattached =
-				((drp_state == PD_DRP_TOGGLE_ON) &&
-				 auto_toggle_supported);
+		((drp_state == PD_DRP_TOGGLE_ON) && auto_toggle_supported);
 
 	/* Set to appropriate port state */
 	if (cc_is_open(cc1, cc2)) {
@@ -425,13 +420,13 @@ enum pd_drp_next_states drp_auto_toggle_next_state(
 			return DRP_TC_DRP_AUTO_TOGGLE;
 		}
 	} else if ((cc_is_rp(cc1) || cc_is_rp(cc2)) &&
-		drp_state != PD_DRP_FORCE_SOURCE) {
+		   drp_state != PD_DRP_FORCE_SOURCE) {
 		/* SNK allowed unless ForceSRC */
 		if (hardware_debounced_unattached)
 			return DRP_TC_ATTACHED_WAIT_SNK;
 		return DRP_TC_UNATTACHED_SNK;
 	} else if (cc_is_at_least_one_rd(cc1, cc2) ||
-					cc_is_audio_acc(cc1, cc2)) {
+		   cc_is_audio_acc(cc1, cc2)) {
 		/*
 		 * SRC allowed unless ForceSNK or Toggle Off
 		 *
@@ -447,10 +442,10 @@ enum pd_drp_next_states drp_auto_toggle_next_state(
 		 * ready for a new connection.
 		 */
 		if (drp_state == PD_DRP_TOGGLE_OFF ||
-			drp_state == PD_DRP_FORCE_SINK) {
-			if (get_time().val > *drp_sink_time + 200*MSEC)
+		    drp_state == PD_DRP_FORCE_SINK) {
+			if (get_time().val > *drp_sink_time + 200 * MSEC)
 				*drp_sink_time = get_time().val;
-			if (get_time().val < *drp_sink_time + 100*MSEC)
+			if (get_time().val < *drp_sink_time + 100 * MSEC)
 				return DRP_TC_UNATTACHED_SNK;
 			else
 				return DRP_TC_DRP_AUTO_TOGGLE;
@@ -502,8 +497,8 @@ mux_state_t get_mux_mode_to_set(int port)
 	 * conditions which are checked below. The default function returns
 	 * false, so only boards that override this check will be affected.
 	 */
-	if (usb_ufp_check_usb3_enable(port) && pd_get_data_role(port)
-	    == PD_ROLE_UFP)
+	if (usb_ufp_check_usb3_enable(port) &&
+	    pd_get_data_role(port) == PD_ROLE_UFP)
 		return USB_PD_MUX_USB_ENABLED;
 
 	/* If new data role isn't DFP & we only support DFP, also disconnect. */
@@ -544,21 +539,19 @@ void set_usb_mux_with_current_data_role(int port)
 	if (IS_ENABLED(CONFIG_USBC_SS_MUX)) {
 		mux_state_t mux_mode = get_mux_mode_to_set(port);
 		enum usb_switch usb_switch_mode =
-				(mux_mode == USB_PD_MUX_NONE) ?
-				USB_SWITCH_DISCONNECT : USB_SWITCH_CONNECT;
+			(mux_mode == USB_PD_MUX_NONE) ? USB_SWITCH_DISCONNECT :
+							USB_SWITCH_CONNECT;
 
 		usb_mux_set(port, mux_mode, usb_switch_mode,
-				polarity_rm_dts(pd_get_polarity(port)));
+			    polarity_rm_dts(pd_get_polarity(port)));
 	}
 }
 
 void usb_mux_set_safe_mode(int port)
 {
 	if (IS_ENABLED(CONFIG_USBC_SS_MUX)) {
-		usb_mux_set(port, IS_ENABLED(CONFIG_USB_MUX_VIRTUAL) ?
-			USB_PD_MUX_SAFE_MODE : USB_PD_MUX_NONE,
-			USB_SWITCH_CONNECT,
-			polarity_rm_dts(pd_get_polarity(port)));
+		usb_mux_set(port, USB_PD_MUX_SAFE_MODE, USB_SWITCH_CONNECT,
+			    polarity_rm_dts(pd_get_polarity(port)));
 	}
 
 	/* Isolate the SBU lines. */
@@ -617,8 +610,7 @@ __overridable int pd_board_checks(void)
 	return EC_SUCCESS;
 }
 
-__overridable int pd_check_data_swap(int port,
-	enum pd_data_role data_role)
+__overridable int pd_check_data_swap(int port, enum pd_data_role data_role)
 {
 	/* Allow data swap if we are a UFP, otherwise don't allow. */
 	return (data_role == PD_ROLE_UFP) ? 1 : 0;
@@ -639,8 +631,7 @@ __overridable int pd_check_power_swap(int port)
 	return 0;
 }
 
-__overridable void pd_execute_data_swap(int port,
-	enum pd_data_role data_role)
+__overridable void pd_execute_data_swap(int port, enum pd_data_role data_role)
 {
 }
 
@@ -699,7 +690,7 @@ __overridable int pd_custom_vdm(int port, int cnt, uint32_t *payload,
 	case VDO_CMD_VERSION:
 		/* guarantee last byte of payload is null character */
 		*(payload + cnt - 1) = 0;
-		CPRINTF("version: %s\n", (char *)(payload+1));
+		CPRINTF("version: %s\n", (char *)(payload + 1));
 		break;
 	case VDO_CMD_READ_INFO:
 	case VDO_CMD_SEND_INFO:
@@ -720,10 +711,8 @@ __overridable int pd_custom_vdm(int port, int cnt, uint32_t *payload,
 				pd_send_host_event(PD_EVENT_UPDATE_DEVICE);
 
 			CPRINTF("DevId:%d.%d SW:%d RW:%d\n",
-				HW_DEV_ID_MAJ(dev_id),
-				HW_DEV_ID_MIN(dev_id),
-				VDO_INFO_SW_DBG_VER(payload[6]),
-				is_rw);
+				HW_DEV_ID_MAJ(dev_id), HW_DEV_ID_MIN(dev_id),
+				VDO_INFO_SW_DBG_VER(payload[6]), is_rw);
 		} else if (cnt == 6) {
 			/* really old devices don't have last byte */
 			pd_dev_store_rw_hash(port, dev_id, payload + 1,
@@ -757,9 +746,9 @@ __overridable bool vboot_allow_usb_pd(void)
 static void pd_usb_billboard_deferred(void)
 {
 	if (IS_ENABLED(CONFIG_USB_PD_ALT_MODE) &&
-		!IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP) &&
-		!IS_ENABLED(CONFIG_USB_PD_SIMPLE_DFP) &&
-		IS_ENABLED(CONFIG_USB_BOS)) {
+	    !IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP) &&
+	    !IS_ENABLED(CONFIG_USB_PD_SIMPLE_DFP) &&
+	    IS_ENABLED(CONFIG_USB_BOS)) {
 		/*
 		 * TODO(tbroch)
 		 * 1. Will we have multiple type-C port UFPs
@@ -859,10 +848,9 @@ __overridable int pd_snk_is_vbus_provided(int port)
 __overridable bool pd_check_vbus_level(int port, enum vbus_level level)
 {
 	if (IS_ENABLED(CONFIG_USB_PD_VBUS_DETECT_TCPC) &&
-		(get_usb_pd_vbus_detect() == USB_PD_VBUS_DETECT_TCPC)) {
+	    (get_usb_pd_vbus_detect() == USB_PD_VBUS_DETECT_TCPC)) {
 		return tcpm_check_vbus_level(port, level);
-	}
-	else if (level == VBUS_PRESENT)
+	} else if (level == VBUS_PRESENT)
 		return pd_snk_is_vbus_provided(port);
 	else
 		return !pd_snk_is_vbus_provided(port);
@@ -899,7 +887,7 @@ int pd_set_frs_enable(int port, int enable)
  * Dump TCPC registers.
  */
 void tcpc_dump_registers(int port, const struct tcpc_reg_dump_map *reg,
-			  int count)
+			 int count)
 {
 	int i, val;
 
@@ -907,21 +895,20 @@ void tcpc_dump_registers(int port, const struct tcpc_reg_dump_map *reg,
 		switch (reg->size) {
 		case 1:
 			tcpc_read(port, reg->addr, &val);
-			ccprintf("  %-30s(0x%02x) =   0x%02x\n",
-				reg->name, reg->addr, (uint8_t)val);
+			ccprintf("  %-30s(0x%02x) =   0x%02x\n", reg->name,
+				 reg->addr, (uint8_t)val);
 			break;
 		case 2:
 			tcpc_read16(port, reg->addr, &val);
-			ccprintf("  %-30s(0x%02x) = 0x%04x\n",
-				reg->name, reg->addr, (uint16_t)val);
+			ccprintf("  %-30s(0x%02x) = 0x%04x\n", reg->name,
+				 reg->addr, (uint16_t)val);
 			break;
 		}
 		cflush();
 	}
-
 }
 
-static int command_tcpc_dump(int argc, char **argv)
+static int command_tcpc_dump(int argc, const char **argv)
 {
 	int port;
 
@@ -995,7 +982,7 @@ void pd_srccaps_dump(int port)
 		if (range_flag)
 			ccprintf("-%dmV", min_mv);
 		ccprintf("/%dm%c", max_ma,
-				 pdo_mask == PDO_TYPE_BATTERY ? 'W' : 'A');
+			 pdo_mask == PDO_TYPE_BATTERY ? 'W' : 'A');
 
 		if (pdo & PDO_FIXED_DUAL_ROLE)
 			ccprintf(" DRP");
@@ -1034,6 +1021,23 @@ int pd_send_alert_msg(int port, uint32_t ado)
 {
 #if defined(CONFIG_USB_PD_TCPMV2) && defined(CONFIG_USB_PE_SM) && \
 	!defined(CONFIG_USB_VPD) && !defined(CONFIG_USB_CTVPD)
+	struct rmdo partner_rmdo;
+
+	/*
+	 * The Alert Data Object (ADO) definition changed between USB PD
+	 * Revision 3.0 and 3.1. Clear reserved bits from the USB PD 3.0
+	 * ADO before sending to a USB PD 3.0 partner and block the
+	 * message if the ADO is empty.
+	 */
+	partner_rmdo = pe_get_partner_rmdo(port);
+	if (partner_rmdo.major_rev == 0) {
+		ado &= ~(ADO_EXTENDED_ALERT_EVENT |
+			 ADO_EXTENDED_ALERT_EVENT_TYPE);
+	}
+
+	if (!ado)
+		return EC_ERROR_INVAL;
+
 	if (pe_set_ado(port, ado) != EC_SUCCESS)
 		return EC_ERROR_BUSY;
 
@@ -1057,6 +1061,15 @@ void pd_send_host_event(int mask)
 }
 #endif /* defined(HAS_TASK_HOSTCMD) && !defined(TEST_BUILD) */
 
+#ifdef CONFIG_MKBP_EVENT
+static int dp_alt_mode_entry_get_next_event(uint8_t *data)
+{
+	return EC_SUCCESS;
+}
+DECLARE_EVENT_SOURCE(EC_MKBP_EVENT_DP_ALT_MODE_ENTERED,
+		     dp_alt_mode_entry_get_next_event);
+#endif /* CONFIG_MKBP_EVENT */
+
 __overridable void pd_notify_dp_alt_mode_entry(int port)
 {
 	if (IS_ENABLED(CONFIG_MKBP_EVENT)) {
diff --git a/common/usb_console_stream.c b/common/usb_console_stream.c
index 13dd7f8264..629e7ba1f8 100644
--- a/common/usb_console_stream.c
+++ b/common/usb_console_stream.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,13 +25,12 @@
 /* Console output macro */
 #define USB_CONSOLE_TIMEOUT_US (30 * MSEC)
 
-#define QUEUE_SIZE_USB_TX     CONFIG_USB_CONSOLE_TX_BUF_SIZE
-#define QUEUE_SIZE_USB_RX     USB_MAX_PACKET_SIZE
+#define QUEUE_SIZE_USB_TX CONFIG_USB_CONSOLE_TX_BUF_SIZE
+#define QUEUE_SIZE_USB_RX USB_MAX_PACKET_SIZE
 
 static void usb_console_wr(struct queue_policy const *policy, size_t count);
 static void uart_console_rd(struct queue_policy const *policy, size_t count);
 
-
 static int last_tx_ok = 1;
 
 /*
@@ -52,24 +51,19 @@ static int is_readonly = 1;
  * usb-stream.c.
  */
 static struct queue_policy const usb_console_policy = {
-	.add    = usb_console_wr,
+	.add = usb_console_wr,
 	.remove = uart_console_rd,
 };
 
 static struct queue const tx_q = QUEUE_NULL(QUEUE_SIZE_USB_TX, uint8_t);
-static struct queue const rx_q = QUEUE(QUEUE_SIZE_USB_RX, uint8_t,
-				       usb_console_policy);
+static struct queue const rx_q =
+	QUEUE(QUEUE_SIZE_USB_RX, uint8_t, usb_console_policy);
 
 struct usb_stream_config const usb_console;
 
-USB_STREAM_CONFIG(usb_console,
-		  USB_IFACE_CONSOLE,
-		  USB_STR_CONSOLE_NAME,
-		  USB_EP_CONSOLE,
-		  USB_MAX_PACKET_SIZE,
-		  USB_MAX_PACKET_SIZE,
-		  rx_q,
-		  tx_q)
+USB_STREAM_CONFIG(usb_console, USB_IFACE_CONSOLE, USB_STR_CONSOLE_NAME,
+		  USB_EP_CONSOLE, USB_MAX_PACKET_SIZE, USB_MAX_PACKET_SIZE,
+		  rx_q, tx_q)
 
 static void usb_console_wr(struct queue_policy const *policy, size_t count)
 {
@@ -185,7 +179,7 @@ int usb_puts(const char *outstr)
 	if (!is_enabled)
 		return EC_SUCCESS;
 
-	ret  = usb_wait_console();
+	ret = usb_wait_console();
 	if (ret)
 		return ret;
 
diff --git a/common/usb_host_command.c b/common/usb_host_command.c
index ccae57dd43..83a6e24a7d 100644
--- a/common/usb_host_command.c
+++ b/common/usb_host_command.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,6 +9,7 @@
 #include "ec_commands.h"
 #include "queue_policies.h"
 #include "host_command.h"
+#include "printf.h"
 #include "system.h"
 #include "usb_api.h"
 #include "usb_hw.h"
@@ -16,13 +17,11 @@
 #include "util.h"
 
 #define CPUTS(outstr) cputs(CC_USB, outstr)
-#define CPRINTS(format, args...) cprints(CC_HOSTCMD, "USBHC: " format, ## args)
+#define CPRINTS(format, args...) cprints(CC_HOSTCMD, "USBHC: " format, ##args)
 
 enum usbhc_state {
-	/* Not enabled (initial state, and when chipset is off) */
-	USBHC_STATE_DISABLED = 0,
-	/* Ready to receive next request */
-	USBHC_STATE_READY_TO_RX,
+	/* Initial State - Ready to receive next request */
+	USBHC_STATE_READY_TO_RX = 0,
 	/* Receiving request */
 	USBHC_STATE_RECEIVING,
 	/* Processing request */
@@ -38,26 +37,16 @@ struct producer const hostcmd_producer;
 struct usb_stream_config const usbhc_stream;
 
 /* RX (Host->EC) queue */
-static struct queue const usb_to_hostcmd = QUEUE_DIRECT(64,
-							uint8_t,
-							usbhc_stream.producer,
-							hostcmd_consumer);
+static struct queue const usb_to_hostcmd =
+	QUEUE_DIRECT(64, uint8_t, usbhc_stream.producer, hostcmd_consumer);
 /* TX (EC->Host) queue */
-static struct queue const hostcmd_to_usb = QUEUE_DIRECT(64,
-							uint8_t,
-							hostcmd_producer,
-							usbhc_stream.consumer);
-
-USB_STREAM_CONFIG_FULL(usbhc_stream,
-		       USB_IFACE_HOSTCMD,
-		       USB_CLASS_VENDOR_SPEC,
-		       USB_SUBCLASS_GOOGLE_HOSTCMD,
-		       USB_PROTOCOL_GOOGLE_HOSTCMD,
-		       USB_STR_HOSTCMD_NAME,
-		       USB_EP_HOSTCMD,
-		       USB_MAX_PACKET_SIZE,
-		       USB_MAX_PACKET_SIZE,
-		       usb_to_hostcmd,
+static struct queue const hostcmd_to_usb =
+	QUEUE_DIRECT(64, uint8_t, hostcmd_producer, usbhc_stream.consumer);
+
+USB_STREAM_CONFIG_FULL(usbhc_stream, USB_IFACE_HOSTCMD, USB_CLASS_VENDOR_SPEC,
+		       USB_SUBCLASS_GOOGLE_HOSTCMD, USB_PROTOCOL_GOOGLE_HOSTCMD,
+		       USB_STR_HOSTCMD_NAME, USB_EP_HOSTCMD,
+		       USB_MAX_PACKET_SIZE, USB_MAX_PACKET_SIZE, usb_to_hostcmd,
 		       hostcmd_to_usb)
 
 static uint8_t in_msg[USBHC_MAX_REQUEST_SIZE];
@@ -94,7 +83,7 @@ static void usbhc_read(struct producer const *producer, size_t count)
 
 struct producer const hostcmd_producer = {
 	.queue = &hostcmd_to_usb,
-	.ops   = &((struct producer_ops const) {
+	.ops = &((struct producer_ops const){
 		.read = usbhc_read,
 	}),
 };
@@ -171,8 +160,13 @@ static void usbhc_written(struct consumer const *consumer, size_t count)
 		block_index = 0;
 		/* Only version 3 is supported. Using in_msg as a courtesy. */
 		QUEUE_REMOVE_UNITS(consumer->queue, in_msg, count);
-		if (IS_ENABLED(DEBUG))
-			CPRINTS("%ph", HEX_BUF(in_msg, count));
+		if (IS_ENABLED(DEBUG)) {
+			char str_buf[hex_str_buf_size(count)];
+
+			snprintf_hex_buffer(str_buf, sizeof(str_buf),
+					    HEX_BUF(in_msg, count));
+			CPRINTS("%s", str_buf);
+		}
 		if (in_msg[0] != EC_HOST_REQUEST_VERSION) {
 			CPRINTS("Unsupported version: %u", in_msg[0]);
 			return;
@@ -206,7 +200,6 @@ static void usbhc_written(struct consumer const *consumer, size_t count)
 		return;
 	case USBHC_STATE_PROCESSING:
 	case USBHC_STATE_SENDING:
-	case USBHC_STATE_DISABLED:
 		/*
 		 * Take no action and return though we may have resource to
 		 * receive a new request. Host will get a buffer full error or
@@ -229,7 +222,7 @@ static void usbhc_written(struct consumer const *consumer, size_t count)
 	block_index += count;
 
 	if (block_index < expected_size)
-		return;	/* More to come. */
+		return; /* More to come. */
 
 	if (IS_ENABLED(DEBUG))
 		CPRINTS("Rx complete (%d bytes)", block_index);
@@ -247,13 +240,13 @@ static void usbhc_written(struct consumer const *consumer, size_t count)
 
 struct consumer const hostcmd_consumer = {
 	.queue = &usb_to_hostcmd,
-	.ops   = &((struct consumer_ops const) {
+	.ops = &((struct consumer_ops const){
 		.written = usbhc_written,
 	}),
 };
 
-static enum ec_status host_command_protocol_info(
-		struct host_cmd_handler_args *args)
+static enum ec_status
+host_command_protocol_info(struct host_cmd_handler_args *args)
 {
 	struct ec_response_get_protocol_info *r = args->response;
 
@@ -267,6 +260,5 @@ static enum ec_status host_command_protocol_info(
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO,
-		     host_command_protocol_info,
+DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, host_command_protocol_info,
 		     EC_VER_MASK(0));
diff --git a/common/usb_i2c.c b/common/usb_i2c.c
index ace2e7139c..8482ec0967 100644
--- a/common/usb_i2c.c
+++ b/common/usb_i2c.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,27 +20,24 @@
 #include "usb-stream.h"
 #include "usb_i2c.h"
 
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
 
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
+USB_I2C_CONFIG(i2c, USB_IFACE_I2C, USB_STR_I2C_NAME, USB_EP_I2C)
 
-
-USB_I2C_CONFIG(i2c,
-	       USB_IFACE_I2C,
-	       USB_STR_I2C_NAME,
-	       USB_EP_I2C)
-
-static int (*cros_cmd_handler)(void *data_in,
-			       size_t in_size,
-			       void *data_out,
+static int (*cros_cmd_handler)(void *data_in, size_t in_size, void *data_out,
 			       size_t out_size);
 
 static int16_t usb_i2c_map_error(int error)
 {
 	switch (error) {
-	case EC_SUCCESS:       return USB_I2C_SUCCESS;
-	case EC_ERROR_TIMEOUT: return USB_I2C_TIMEOUT;
-	case EC_ERROR_BUSY:    return USB_I2C_BUSY;
-	default:               return USB_I2C_UNKNOWN_ERROR | (error & 0x7fff);
+	case EC_SUCCESS:
+		return USB_I2C_SUCCESS;
+	case EC_ERROR_TIMEOUT:
+		return USB_I2C_TIMEOUT;
+	case EC_ERROR_BUSY:
+		return USB_I2C_BUSY;
+	default:
+		return USB_I2C_UNKNOWN_ERROR | (error & 0x7fff);
 	}
 }
 
@@ -52,7 +49,7 @@ static int16_t usb_i2c_map_error(int error)
 static uint32_t usb_i2c_read_packet(struct usb_i2c_config const *config)
 {
 	return QUEUE_REMOVE_UNITS(config->consumer.queue, config->buffer,
-		queue_count(config->consumer.queue));
+				  queue_count(config->consumer.queue));
 }
 
 static void usb_i2c_write_packet(struct usb_i2c_config const *config,
@@ -72,9 +69,8 @@ static uint8_t usb_i2c_executable(struct usb_i2c_config const *config)
 		 * In order to support larger write payload, we need to peek
 		 * the queue to see if we need to wait for more data.
 		 */
-		if (queue_peek_units(config->consumer.queue,
-				     peek, 0, sizeof(peek))
-		    != sizeof(peek)) {
+		if (queue_peek_units(config->consumer.queue, peek, 0,
+				     sizeof(peek)) != sizeof(peek)) {
 			/* Not enough data to calculate expected_size. */
 			return 0;
 		}
@@ -92,7 +88,6 @@ static uint8_t usb_i2c_executable(struct usb_i2c_config const *config)
 		expected_size += (((size_t)peek[0] & 0xf0) << 4) | peek[2];
 	}
 
-
 	if (queue_count(config->consumer.queue) >= expected_size) {
 		expected_size = 0;
 		return 1;
@@ -104,20 +99,20 @@ static uint8_t usb_i2c_executable(struct usb_i2c_config const *config)
 static void usb_i2c_execute(struct usb_i2c_config const *config)
 {
 	/* Payload is ready to execute. */
-	uint32_t count      = usb_i2c_read_packet(config);
-	int portindex       = (config->buffer[0] >> 0) & 0xf;
+	uint32_t count = usb_i2c_read_packet(config);
+	int portindex = (config->buffer[0] >> 0) & 0xf;
 	uint16_t addr_flags = (config->buffer[0] >> 8) & 0x7f;
-	int write_count     = ((config->buffer[0] << 4) & 0xf00) |
-		((config->buffer[1] >> 0) & 0xff);
-	int read_count      = (config->buffer[1] >> 8) & 0xff;
-	int offset          = 0;    /* Offset for extended reading header. */
+	int write_count = ((config->buffer[0] << 4) & 0xf00) |
+			  ((config->buffer[1] >> 0) & 0xff);
+	int read_count = (config->buffer[1] >> 8) & 0xff;
+	int offset = 0; /* Offset for extended reading header. */
 
 	config->buffer[0] = 0;
 	config->buffer[1] = 0;
 
 	if (read_count & 0x80) {
 		read_count = ((config->buffer[2] & 0xff) << 7) |
-			(read_count & 0x7f);
+			     (read_count & 0x7f);
 		offset = 2;
 	}
 
@@ -127,7 +122,7 @@ static void usb_i2c_execute(struct usb_i2c_config const *config)
 	if (!usb_i2c_board_is_enabled()) {
 		config->buffer[0] = USB_I2C_DISABLED;
 	} else if (write_count > CONFIG_USB_I2C_MAX_WRITE_COUNT ||
-		write_count != (count - 4 - offset)) {
+		   write_count != (count - 4 - offset)) {
 		config->buffer[0] = USB_I2C_WRITE_COUNT_INVALID;
 	} else if (read_count > CONFIG_USB_I2C_MAX_READ_COUNT) {
 		config->buffer[0] = USB_I2C_READ_COUNT_INVALID;
@@ -156,8 +151,7 @@ static void usb_i2c_execute(struct usb_i2c_config const *config)
 		 */
 		ret = i2c_xfer(i2c_ports[portindex].port, addr_flags,
 			       (uint8_t *)(config->buffer + 2) + offset,
-			       write_count,
-			       (uint8_t *)(config->buffer + 2),
+			       write_count, (uint8_t *)(config->buffer + 2),
 			       read_count);
 		config->buffer[0] = usb_i2c_map_error(ret);
 	}
@@ -183,11 +177,8 @@ struct consumer_ops const usb_i2c_consumer_ops = {
 	.written = usb_i2c_written,
 };
 
-int usb_i2c_register_cros_cmd_handler(int (*cmd_handler)
-				      (void *data_in,
-				       size_t in_size,
-				       void *data_out,
-				       size_t out_size))
+int usb_i2c_register_cros_cmd_handler(int (*cmd_handler)(
+	void *data_in, size_t in_size, void *data_out, size_t out_size))
 {
 	if (cros_cmd_handler)
 		return -1;
diff --git a/common/usb_pd_alt_mode_dfp.c b/common/usb_pd_alt_mode_dfp.c
index 1de01f9c48..45a47ed9a5 100644
--- a/common/usb_pd_alt_mode_dfp.c
+++ b/common/usb_pd_alt_mode_dfp.c
@@ -1,10 +1,11 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Alternate Mode Downstream Facing Port (DFP) USB-PD module.
  */
 
+#include "builtin/assert.h"
 #include "chipset.h"
 #include "console.h"
 #include "gpio.h"
@@ -23,8 +24,8 @@
 #include "util.h"
 
 #ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
 #else
 #define CPRINTS(format, args...)
 #define CPRINTF(format, args...)
@@ -51,8 +52,8 @@ uint32_t dp_status[CONFIG_USB_PD_PORT_MAX_COUNT];
 /* Console command multi-function preference set for a PD port. */
 
 __maybe_unused bool dp_port_mf_allow[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-		[0 ... CONFIG_USB_PD_PORT_MAX_COUNT - 1] = true};
-
+	[0 ... CONFIG_USB_PD_PORT_MAX_COUNT - 1] = true
+};
 
 __overridable const struct svdm_response svdm_rsp = {
 	.identity = NULL,
@@ -60,8 +61,7 @@ __overridable const struct svdm_response svdm_rsp = {
 	.modes = NULL,
 };
 
-static int pd_get_mode_idx(int port, enum tcpci_msg_type type,
-		uint16_t svid)
+static int pd_get_mode_idx(int port, enum tcpci_msg_type type, uint16_t svid)
 {
 	int amode_idx;
 	struct partner_active_modes *active =
@@ -75,8 +75,7 @@ static int pd_get_mode_idx(int port, enum tcpci_msg_type type,
 	return -1;
 }
 
-static int pd_allocate_mode(int port, enum tcpci_msg_type type,
-		uint16_t svid)
+static int pd_allocate_mode(int port, enum tcpci_msg_type type, uint16_t svid)
 {
 	int i, j;
 	struct svdm_amode_data *modep;
@@ -122,21 +121,20 @@ static int pd_allocate_mode(int port, enum tcpci_msg_type type,
 	return -1;
 }
 
-static int validate_mode_request(struct svdm_amode_data *modep,
-				 uint16_t svid, int opos)
+static int validate_mode_request(struct svdm_amode_data *modep, uint16_t svid,
+				 int opos)
 {
 	if (!modep->fx)
 		return 0;
 
 	if (svid != modep->fx->svid) {
-		CPRINTF("ERR:svid r:0x%04x != c:0x%04x\n",
-			svid, modep->fx->svid);
+		CPRINTF("ERR:svid r:0x%04x != c:0x%04x\n", svid,
+			modep->fx->svid);
 		return 0;
 	}
 
 	if (opos != modep->opos) {
-		CPRINTF("ERR:opos r:%d != c:%d\n",
-			opos, modep->opos);
+		CPRINTF("ERR:opos r:%d != c:%d\n", opos, modep->opos);
 		return 0;
 	}
 
@@ -199,7 +197,7 @@ int pd_dfp_dp_get_pin_mode(int port, uint32_t status)
 
 	if (IS_ENABLED(CONFIG_CMD_MFALLOW))
 		mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]) &&
-			dp_port_mf_allow[port];
+			  dp_port_mf_allow[port];
 	else
 		mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]);
 
@@ -229,8 +227,8 @@ int pd_dfp_dp_get_pin_mode(int port, uint32_t status)
 	return 1 << get_next_bit(&pin_caps);
 }
 
-struct svdm_amode_data *pd_get_amode_data(int port,
-		enum tcpci_msg_type type, uint16_t svid)
+struct svdm_amode_data *pd_get_amode_data(int port, enum tcpci_msg_type type,
+					  uint16_t svid)
 {
 	int idx = pd_get_mode_idx(port, type, svid);
 	struct partner_active_modes *active =
@@ -244,8 +242,8 @@ struct svdm_amode_data *pd_get_amode_data(int port,
  * Enter default mode ( payload[0] == 0 ) or attempt to enter mode via svid &
  * opos
  */
-uint32_t pd_dfp_enter_mode(int port, enum tcpci_msg_type type,
-		uint16_t svid, int opos)
+uint32_t pd_dfp_enter_mode(int port, enum tcpci_msg_type type, uint16_t svid,
+			   int opos)
 {
 	int mode_idx = pd_allocate_mode(port, type, svid);
 	struct svdm_amode_data *modep;
@@ -285,7 +283,7 @@ uint32_t pd_dfp_enter_mode(int port, enum tcpci_msg_type type,
 
 /* TODO(b/170372521) : Incorporate exit mode specific changes to DPM SM */
 int pd_dfp_exit_mode(int port, enum tcpci_msg_type type, uint16_t svid,
-		int opos)
+		     int opos)
 {
 	struct svdm_amode_data *modep;
 	struct partner_active_modes *active =
@@ -358,7 +356,7 @@ void dfp_consume_attention(int port, uint32_t *payload)
 }
 
 void dfp_consume_identity(int port, enum tcpci_msg_type type, int cnt,
-		uint32_t *payload)
+			  uint32_t *payload)
 {
 	int ptype;
 	struct pd_discovery *disc;
@@ -372,8 +370,8 @@ void dfp_consume_identity(int port, enum tcpci_msg_type type, int cnt,
 
 	ptype = PD_IDH_PTYPE(payload[VDO_I(IDH)]);
 	disc = pd_get_am_discovery_and_notify_access(port, type);
-	identity_size = MIN(sizeof(union disc_ident_ack),
-				   (cnt - 1) * sizeof(uint32_t));
+	identity_size =
+		MIN(sizeof(union disc_ident_ack), (cnt - 1) * sizeof(uint32_t));
 
 	/* Note: only store VDOs, not the VDM header */
 	memcpy(disc->identity.raw_value, payload + 1, identity_size);
@@ -383,14 +381,14 @@ void dfp_consume_identity(int port, enum tcpci_msg_type type, int cnt,
 	case IDH_PTYPE_AMA:
 		/* Leave vbus ON if the following macro is false */
 		if (IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE) &&
-			IS_ENABLED(CONFIG_USBC_VCONN_SWAP)) {
+		    IS_ENABLED(CONFIG_USBC_VCONN_SWAP)) {
 			/* Adapter is requesting vconn, try to supply it */
 			if (PD_VDO_AMA_VCONN_REQ(payload[VDO_I(AMA)]))
 				pd_try_vconn_src(port);
 
 			/* Only disable vbus if vconn was requested */
 			if (PD_VDO_AMA_VCONN_REQ(payload[VDO_I(AMA)]) &&
-				!PD_VDO_AMA_VBUS_REQ(payload[VDO_I(AMA)]))
+			    !PD_VDO_AMA_VBUS_REQ(payload[VDO_I(AMA)]))
 				pd_power_supply_reset(port);
 		}
 		break;
@@ -401,14 +399,14 @@ void dfp_consume_identity(int port, enum tcpci_msg_type type, int cnt,
 }
 
 void dfp_consume_svids(int port, enum tcpci_msg_type type, int cnt,
-		uint32_t *payload)
+		       uint32_t *payload)
 {
 	int i;
 	uint32_t *ptr = payload + 1;
 	int vdo = 1;
 	uint16_t svid0, svid1;
 	struct pd_discovery *disc =
-			pd_get_am_discovery_and_notify_access(port, type);
+		pd_get_am_discovery_and_notify_access(port, type);
 
 	for (i = disc->svid_cnt; i < disc->svid_cnt + 12; i += 2) {
 		if (i >= SVID_DISCOVERY_MAX) {
@@ -447,13 +445,13 @@ void dfp_consume_svids(int port, enum tcpci_msg_type type, int cnt,
 }
 
 void dfp_consume_modes(int port, enum tcpci_msg_type type, int cnt,
-		uint32_t *payload)
+		       uint32_t *payload)
 {
 	int svid_idx;
 	struct svid_mode_data *mode_discovery = NULL;
 	struct pd_discovery *disc =
-			pd_get_am_discovery_and_notify_access(port, type);
-	uint16_t response_svid = (uint16_t) PD_VDO_VID(payload[0]);
+		pd_get_am_discovery_and_notify_access(port, type);
+	uint16_t response_svid = (uint16_t)PD_VDO_VID(payload[0]);
 
 	for (svid_idx = 0; svid_idx < disc->svid_cnt; ++svid_idx) {
 		uint16_t svid = disc->svids[svid_idx].svid;
@@ -467,15 +465,15 @@ void dfp_consume_modes(int port, enum tcpci_msg_type type, int cnt,
 		const struct svid_mode_data *requested_mode_data =
 			pd_get_next_mode(port, type);
 		CPRINTF("C%d: Mode response for undiscovered SVID %x, but TCPM "
-				"requested SVID %x\n",
-				port, response_svid, requested_mode_data->svid);
+			"requested SVID %x\n",
+			port, response_svid, requested_mode_data->svid);
 		/*
 		 * Although SVIDs discovery seemed like it succeeded before, the
 		 * partner is now responding with undiscovered SVIDs. Discovery
 		 * cannot reasonably continue under these circumstances.
 		 */
 		pd_set_modes_discovery(port, type, requested_mode_data->svid,
-				PD_DISC_FAIL);
+				       PD_DISC_FAIL);
 		return;
 	}
 
@@ -483,15 +481,15 @@ void dfp_consume_modes(int port, enum tcpci_msg_type type, int cnt,
 	if (mode_discovery->mode_cnt < 1) {
 		CPRINTF("ERR:NOMODE\n");
 		pd_set_modes_discovery(port, type, mode_discovery->svid,
-				PD_DISC_FAIL);
+				       PD_DISC_FAIL);
 		return;
 	}
 
 	memcpy(mode_discovery->mode_vdo, &payload[1],
-			sizeof(uint32_t) * mode_discovery->mode_cnt);
+	       sizeof(uint32_t) * mode_discovery->mode_cnt);
 	disc->svid_idx++;
 	pd_set_modes_discovery(port, type, mode_discovery->svid,
-			PD_DISC_COMPLETE);
+			       PD_DISC_COMPLETE);
 }
 
 int pd_alt_mode(int port, enum tcpci_msg_type type, uint16_t svid)
@@ -505,7 +503,7 @@ void pd_set_identity_discovery(int port, enum tcpci_msg_type type,
 			       enum pd_discovery_state disc)
 {
 	struct pd_discovery *pd =
-			pd_get_am_discovery_and_notify_access(port, type);
+		pd_get_am_discovery_and_notify_access(port, type);
 
 	pd->identity_discovery = disc;
 }
@@ -519,7 +517,7 @@ enum pd_discovery_state pd_get_identity_discovery(int port,
 }
 
 const union disc_ident_ack *pd_get_identity_response(int port,
-					       enum tcpci_msg_type type)
+						     enum tcpci_msg_type type)
 {
 	if (type >= DISCOVERY_TYPE_COUNT)
 		return NULL;
@@ -529,39 +527,39 @@ const union disc_ident_ack *pd_get_identity_response(int port,
 
 uint16_t pd_get_identity_vid(int port)
 {
-	const union disc_ident_ack *resp = pd_get_identity_response(port,
-								TCPCI_MSG_SOP);
+	const union disc_ident_ack *resp =
+		pd_get_identity_response(port, TCPCI_MSG_SOP);
 
 	return resp->idh.usb_vendor_id;
 }
 
 uint16_t pd_get_identity_pid(int port)
 {
-	const union disc_ident_ack *resp = pd_get_identity_response(port,
-								TCPCI_MSG_SOP);
+	const union disc_ident_ack *resp =
+		pd_get_identity_response(port, TCPCI_MSG_SOP);
 
 	return resp->product.product_id;
 }
 
 uint8_t pd_get_product_type(int port)
 {
-	const union disc_ident_ack *resp = pd_get_identity_response(port,
-								TCPCI_MSG_SOP);
+	const union disc_ident_ack *resp =
+		pd_get_identity_response(port, TCPCI_MSG_SOP);
 
 	return resp->idh.product_type;
 }
 
 void pd_set_svids_discovery(int port, enum tcpci_msg_type type,
-			       enum pd_discovery_state disc)
+			    enum pd_discovery_state disc)
 {
 	struct pd_discovery *pd =
-			pd_get_am_discovery_and_notify_access(port, type);
+		pd_get_am_discovery_and_notify_access(port, type);
 
 	pd->svids_discovery = disc;
 }
 
 enum pd_discovery_state pd_get_svids_discovery(int port,
-		enum tcpci_msg_type type)
+					       enum tcpci_msg_type type)
 {
 	const struct pd_discovery *disc = pd_get_am_discovery(port, type);
 
@@ -582,11 +580,11 @@ uint16_t pd_get_svid(int port, uint16_t svid_idx, enum tcpci_msg_type type)
 	return disc->svids[svid_idx].svid;
 }
 
-void pd_set_modes_discovery(int port, enum tcpci_msg_type type,
-		uint16_t svid, enum pd_discovery_state disc)
+void pd_set_modes_discovery(int port, enum tcpci_msg_type type, uint16_t svid,
+			    enum pd_discovery_state disc)
 {
 	struct pd_discovery *pd =
-			pd_get_am_discovery_and_notify_access(port, type);
+		pd_get_am_discovery_and_notify_access(port, type);
 	int svid_idx;
 
 	for (svid_idx = 0; svid_idx < pd->svid_cnt; ++svid_idx) {
@@ -601,7 +599,7 @@ void pd_set_modes_discovery(int port, enum tcpci_msg_type type,
 }
 
 enum pd_discovery_state pd_get_modes_discovery(int port,
-		enum tcpci_msg_type type)
+					       enum tcpci_msg_type type)
 {
 	const struct svid_mode_data *mode_data = pd_get_next_mode(port, type);
 
@@ -615,8 +613,8 @@ enum pd_discovery_state pd_get_modes_discovery(int port,
 	return mode_data->discovery;
 }
 
-int pd_get_mode_vdo_for_svid(int port, enum tcpci_msg_type type,
-		uint16_t svid, uint32_t *vdo_out)
+int pd_get_mode_vdo_for_svid(int port, enum tcpci_msg_type type, uint16_t svid,
+			     uint32_t *vdo_out)
 {
 	int idx;
 	const struct pd_discovery *disc;
@@ -637,7 +635,7 @@ int pd_get_mode_vdo_for_svid(int port, enum tcpci_msg_type type,
 }
 
 const struct svid_mode_data *pd_get_next_mode(int port,
-		enum tcpci_msg_type type)
+					      enum tcpci_msg_type type)
 {
 	const struct pd_discovery *disc = pd_get_am_discovery(port, type);
 	const struct svid_mode_data *failed_mode_data = NULL;
@@ -672,7 +670,7 @@ const struct svid_mode_data *pd_get_next_mode(int port,
 }
 
 const uint32_t *pd_get_mode_vdo(int port, uint16_t svid_idx,
-		enum tcpci_msg_type type)
+				enum tcpci_msg_type type)
 {
 	const struct pd_discovery *disc = pd_get_am_discovery(port, type);
 
@@ -680,15 +678,15 @@ const uint32_t *pd_get_mode_vdo(int port, uint16_t svid_idx,
 }
 
 bool pd_is_mode_discovered_for_svid(int port, enum tcpci_msg_type type,
-		uint16_t svid)
+				    uint16_t svid)
 {
 	const struct pd_discovery *disc = pd_get_am_discovery(port, type);
 	const struct svid_mode_data *mode_data;
 
 	for (mode_data = disc->svids; mode_data < disc->svids + disc->svid_cnt;
-			++mode_data) {
+	     ++mode_data) {
 		if (mode_data->svid == svid &&
-				mode_data->discovery == PD_DISC_COMPLETE)
+		    mode_data->discovery == PD_DISC_COMPLETE)
 			return true;
 	}
 
@@ -726,69 +724,6 @@ bool is_vpd_ct_supported(int port)
 	return vpd.ct_support;
 }
 
-uint8_t get_vpd_ct_gnd_impedance(int port)
-{
-	const struct pd_discovery *disc =
-		pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
-	union vpd_vdo vpd = disc->identity.product_t1.vpd;
-
-	return vpd.gnd_impedance;
-}
-
-uint8_t get_vpd_ct_vbus_impedance(int port)
-{
-	const struct pd_discovery *disc =
-		pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
-	union vpd_vdo vpd = disc->identity.product_t1.vpd;
-
-	return vpd.vbus_impedance;
-}
-
-uint8_t get_vpd_ct_current_support(int port)
-{
-	const struct pd_discovery *disc =
-		pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
-	union vpd_vdo vpd = disc->identity.product_t1.vpd;
-
-	return vpd.ct_current_support;
-}
-
-uint8_t get_vpd_ct_max_vbus_voltage(int port)
-{
-	const struct pd_discovery *disc =
-		pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
-	union vpd_vdo vpd = disc->identity.product_t1.vpd;
-
-	return vpd.max_vbus_voltage;
-}
-
-uint8_t get_vpd_ct_vdo_version(int port)
-{
-	const struct pd_discovery *disc =
-		pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
-	union vpd_vdo vpd = disc->identity.product_t1.vpd;
-
-	return vpd.vdo_version;
-}
-
-uint8_t get_vpd_ct_firmware_verion(int port)
-{
-	const struct pd_discovery *disc =
-		pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
-	union vpd_vdo vpd = disc->identity.product_t1.vpd;
-
-	return vpd.firmware_version;
-}
-
-uint8_t get_vpd_ct_hw_version(int port)
-{
-	const struct pd_discovery *disc =
-		pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
-	union vpd_vdo vpd = disc->identity.product_t1.vpd;
-
-	return vpd.hw_version;
-}
-
 /*
  * ############################################################################
  *
@@ -812,7 +747,7 @@ bool is_usb2_cable_support(int port)
 	return disc->identity.idh.product_type == IDH_PTYPE_PCABLE ||
 	       pd_get_vdo_ver(port, TCPCI_MSG_SOP_PRIME) < VDM_VER20 ||
 	       disc->identity.product_t2.a2_rev30.usb_20_support ==
-							USB2_SUPPORTED;
+		       USB2_SUPPORTED;
 }
 
 bool is_cable_speed_gen2_capable(int port)
@@ -823,13 +758,13 @@ bool is_cable_speed_gen2_capable(int port)
 	switch (pd_get_rev(port, TCPCI_MSG_SOP_PRIME)) {
 	case PD_REV20:
 		return disc->identity.product_t1.p_rev20.ss ==
-						USB_R20_SS_U31_GEN1_GEN2;
+		       USB_R20_SS_U31_GEN1_GEN2;
 
 	case PD_REV30:
 		return disc->identity.product_t1.p_rev30.ss ==
-						USB_R30_SS_U32_U40_GEN2 ||
+			       USB_R30_SS_U32_U40_GEN2 ||
 		       disc->identity.product_t1.p_rev30.ss ==
-						USB_R30_SS_U40_GEN3;
+			       USB_R30_SS_U40_GEN3;
 	default:
 		return false;
 	}
@@ -844,310 +779,8 @@ bool is_active_cable_element_retimer(int port)
 	 * Revision 2 Active cables do not have Active element support.
 	 */
 	return is_pd_rev3(port, TCPCI_MSG_SOP_PRIME) &&
-		disc->identity.idh.product_type == IDH_PTYPE_ACABLE &&
-		disc->identity.product_t2.a2_rev30.active_elem ==
-							ACTIVE_RETIMER;
-}
-
-/*
- * ############################################################################
- *
- * Thunderbolt-Compatible functions
- *
- * ############################################################################
- */
-
-uint32_t pd_get_tbt_mode_vdo(int port, enum tcpci_msg_type type)
-{
-	uint32_t tbt_mode_vdo[PDO_MODES];
-
-	return pd_get_mode_vdo_for_svid(port, type, USB_VID_INTEL,
-					tbt_mode_vdo) ? tbt_mode_vdo[0] : 0;
-}
-
-/* TODO (b/148528713): Need to enable Thunderbolt-compatible mode on TCPMv2 */
-void set_tbt_compat_mode_ready(int port)
-{
-	if (IS_ENABLED(CONFIG_USBC_SS_MUX) &&
-	    IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE)) {
-		/* Connect the SBU and USB lines to the connector. */
-		typec_set_sbu(port, true);
-
-		/* Set usb mux to Thunderbolt-compatible mode */
-		usb_mux_set(port, USB_PD_MUX_TBT_COMPAT_ENABLED,
-			USB_SWITCH_CONNECT,
-			polarity_rm_dts(pd_get_polarity(port)));
-	}
-}
-
-/*
- * Ref: USB Type-C Cable and Connector Specification
- * Figure F-1 TBT3 Discovery Flow
- */
-static bool is_tbt_cable_superspeed(int port)
-{
-	const struct pd_discovery *disc;
-
-	if (!IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE) ||
-	    !IS_ENABLED(CONFIG_USB_PD_DECODE_SOP))
-		return false;
-
-	disc = pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
-
-	/* Product type is Active cable, hence don't check for speed */
-	if (disc->identity.idh.product_type == IDH_PTYPE_ACABLE)
-		return true;
-
-	if (disc->identity.idh.product_type != IDH_PTYPE_PCABLE)
-		return false;
-
-	if (IS_ENABLED(CONFIG_USB_PD_REV30) &&
-	   is_pd_rev3(port, TCPCI_MSG_SOP_PRIME))
-		return  disc->identity.product_t1.p_rev30.ss ==
-						USB_R30_SS_U32_U40_GEN1 ||
-			disc->identity.product_t1.p_rev30.ss ==
-						USB_R30_SS_U32_U40_GEN2 ||
-			disc->identity.product_t1.p_rev30.ss ==
-						USB_R30_SS_U40_GEN3;
-
-	return  disc->identity.product_t1.p_rev20.ss ==
-						USB_R20_SS_U31_GEN1 ||
-		disc->identity.product_t1.p_rev20.ss ==
-						USB_R20_SS_U31_GEN1_GEN2;
-}
-
-static enum tbt_compat_cable_speed usb_rev30_to_tbt_speed(enum usb_rev30_ss ss)
-{
-	switch (ss) {
-	case USB_R30_SS_U32_U40_GEN1:
-		return TBT_SS_U31_GEN1;
-	case USB_R30_SS_U32_U40_GEN2:
-		return TBT_SS_U32_GEN1_GEN2;
-	case USB_R30_SS_U40_GEN3:
-		return TBT_SS_TBT_GEN3;
-	default:
-		return TBT_SS_U32_GEN1_GEN2;
-	}
-}
-
-enum tbt_compat_cable_speed get_tbt_cable_speed(int port)
-{
-	union tbt_mode_resp_cable cable_mode_resp;
-	enum tbt_compat_cable_speed max_tbt_speed;
-	enum tbt_compat_cable_speed cable_tbt_speed;
-
-	if (!is_tbt_cable_superspeed(port))
-		return TBT_SS_RES_0;
-
-	cable_mode_resp.raw_value =
-		pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME);
-	max_tbt_speed = board_get_max_tbt_speed(port);
-
-	/*
-	 * Ref: TBT4 PD Discovery Flow Application Notes Revision 0.9, Figure 2
-	 * For passive cable, if cable doesn't support USB_VID_INTEL, enter
-	 * Thunderbolt alternate mode with speed from USB Highest Speed field of
-	 * the Passive Cable VDO
-	 * For active cable, if the cable doesn't support USB_VID_INTEL, do not
-	 * enter Thunderbolt alternate mode.
-	 */
-	if (!cable_mode_resp.raw_value) {
-		const struct pd_discovery *disc;
-
-		if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE)
-			return TBT_SS_RES_0;
-
-		disc = pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
-		cable_tbt_speed =
-		   usb_rev30_to_tbt_speed(disc->identity.product_t1.p_rev30.ss);
-	} else {
-		cable_tbt_speed = cable_mode_resp.tbt_cable_speed;
-	}
-
-	return max_tbt_speed < cable_tbt_speed ?
-		max_tbt_speed : cable_tbt_speed;
-}
-
-/* Note: Assumes that pins have already been set in safe state */
-int enter_tbt_compat_mode(int port, enum tcpci_msg_type sop,
-			uint32_t *payload)
-{
-	union tbt_dev_mode_enter_cmd enter_dev_mode = { .raw_value = 0 };
-	union tbt_mode_resp_device dev_mode_resp;
-	union tbt_mode_resp_cable cable_mode_resp;
-	enum tcpci_msg_type enter_mode_sop =
-					sop == TCPCI_MSG_SOP_PRIME_PRIME ?
-						TCPCI_MSG_SOP_PRIME : sop;
-
-	/* Table F-12 TBT3 Cable Enter Mode Command */
-	/*
-	 * The port doesn't query Discover SOP'' to the cable so, the port
-	 * doesn't have opos for SOP''. Hence, send Enter Mode SOP'' with same
-	 * opos and revision as SOP'.
-	 */
-	payload[0] = pd_dfp_enter_mode(port, enter_mode_sop, USB_VID_INTEL, 0) |
-		     VDO_CMDT(CMDT_INIT) |
-		     VDO_SVDM_VERS(pd_get_vdo_ver(port, enter_mode_sop));
-
-	/* For TBT3 Cable Enter Mode Command, number of Objects is 1 */
-	if ((sop == TCPCI_MSG_SOP_PRIME) ||
-	    (sop == TCPCI_MSG_SOP_PRIME_PRIME))
-		return 1;
-
-	dev_mode_resp.raw_value = pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP);
-	cable_mode_resp.raw_value =
-			pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME);
-
-	/* Table F-13 TBT3 Device Enter Mode Command */
-	enter_dev_mode.vendor_spec_b1 = dev_mode_resp.vendor_spec_b1;
-	enter_dev_mode.vendor_spec_b0 = dev_mode_resp.vendor_spec_b0;
-	enter_dev_mode.intel_spec_b0 = dev_mode_resp.intel_spec_b0;
-
-	if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE ||
-	    cable_mode_resp.tbt_active_passive == TBT_CABLE_ACTIVE)
-		enter_dev_mode.cable = TBT_ENTER_ACTIVE_CABLE;
-
-	enter_dev_mode.lsrx_comm = cable_mode_resp.lsrx_comm;
-	enter_dev_mode.retimer_type = cable_mode_resp.retimer_type;
-	enter_dev_mode.tbt_cable = cable_mode_resp.tbt_cable;
-	enter_dev_mode.tbt_rounded = cable_mode_resp.tbt_rounded;
-	enter_dev_mode.tbt_cable_speed = get_tbt_cable_speed(port);
-	enter_dev_mode.tbt_alt_mode = TBT_ALTERNATE_MODE;
-
-	payload[1] = enter_dev_mode.raw_value;
-
-	/* For TBT3 Device Enter Mode Command, number of Objects are 2 */
-	return 2;
-}
-
-enum tbt_compat_rounded_support get_tbt_rounded_support(int port)
-{
-	union tbt_mode_resp_cable cable_mode_resp = {
-		.raw_value = pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME) };
-
-	/* tbt_rounded_support is zero when uninitialized */
-	return cable_mode_resp.tbt_rounded;
-}
-
-__overridable enum tbt_compat_cable_speed board_get_max_tbt_speed(int port)
-{
-	return TBT_SS_TBT_GEN3;
-}
-/*
- * ############################################################################
- *
- * USB4 functions
- *
- * ############################################################################
- */
-
-/*
- * For Cable rev 3.0: USB4 cable speed is set according to speed supported by
- * the port and the response received from the cable, whichever is least.
- *
- * For Cable rev 2.0: If get_tbt_cable_speed() is less than
- * TBT_SS_U31_GEN1, return USB_R30_SS_U2_ONLY speed since the board
- * doesn't support superspeed else the USB4 cable speed is set according to
- * the cable response.
- */
-enum usb_rev30_ss get_usb4_cable_speed(int port)
-{
-	enum tbt_compat_cable_speed tbt_speed = get_tbt_cable_speed(port);
-	enum usb_rev30_ss max_usb4_speed;
-
-
-	if (tbt_speed < TBT_SS_U31_GEN1)
-		return USB_R30_SS_U2_ONLY;
-
-	/*
-	 * Converting Thunderbolt-Compatible board speed to equivalent USB4
-	 * speed.
-	 */
-	max_usb4_speed = tbt_speed == TBT_SS_TBT_GEN3 ?
-		USB_R30_SS_U40_GEN3 : USB_R30_SS_U32_U40_GEN2;
-
-	if ((get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE) &&
-	     is_pd_rev3(port, TCPCI_MSG_SOP_PRIME)) {
-		const struct pd_discovery *disc =
-			pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
-		union active_cable_vdo1_rev30 a_rev30 =
-			disc->identity.product_t1.a_rev30;
-
-		if (a_rev30.vdo_ver >= VDO_VERSION_1_3) {
-			return max_usb4_speed < a_rev30.ss ?
-			       max_usb4_speed : a_rev30.ss;
-		}
-	}
-
-	return max_usb4_speed;
-}
-
-uint32_t get_enter_usb_msg_payload(int port)
-{
-	/*
-	 * Ref: USB Power Delivery Specification Revision 3.0, Version 2.0
-	 * Table 6-47 Enter_USB Data Object
-	 */
-	union enter_usb_data_obj eudo;
-	const struct pd_discovery *disc;
-	union tbt_mode_resp_cable cable_mode_resp;
-
-	if (!IS_ENABLED(CONFIG_USB_PD_USB4))
-		return 0;
-
-	disc = pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
-	eudo.mode = USB_PD_40;
-	eudo.usb4_drd_cap = IS_ENABLED(CONFIG_USB_PD_USB4_DRD);
-	eudo.usb3_drd_cap = IS_ENABLED(CONFIG_USB_PD_USB32_DRD);
-	eudo.cable_speed = get_usb4_cable_speed(port);
-
-	if (disc->identity.idh.product_type == IDH_PTYPE_ACABLE) {
-		if (is_pd_rev3(port, TCPCI_MSG_SOP_PRIME)) {
-			enum retimer_active_element active_element =
-				disc->identity.product_t2.a2_rev30.active_elem;
-			eudo.cable_type = active_element == ACTIVE_RETIMER ?
-				CABLE_TYPE_ACTIVE_RETIMER :
-				CABLE_TYPE_ACTIVE_REDRIVER;
-		} else {
-			cable_mode_resp.raw_value =
-				pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME);
-
-			eudo.cable_type =
-				cable_mode_resp.retimer_type  == USB_RETIMER ?
-				CABLE_TYPE_ACTIVE_RETIMER :
-				CABLE_TYPE_ACTIVE_REDRIVER;
-		}
-	} else {
-		cable_mode_resp.raw_value =
-			pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME);
-
-		eudo.cable_type =
-			cable_mode_resp.tbt_active_passive == TBT_CABLE_ACTIVE ?
-			CABLE_TYPE_ACTIVE_REDRIVER : CABLE_TYPE_PASSIVE;
-	}
-
-	switch (disc->identity.product_t1.p_rev20.vbus_cur) {
-	case USB_VBUS_CUR_3A:
-		eudo.cable_current = USB4_CABLE_CURRENT_3A;
-		break;
-	case USB_VBUS_CUR_5A:
-		eudo.cable_current = USB4_CABLE_CURRENT_5A;
-		break;
-	default:
-		eudo.cable_current = USB4_CABLE_CURRENT_INVALID;
-		break;
-	}
-	eudo.pcie_supported = IS_ENABLED(CONFIG_USB_PD_PCIE_TUNNELING);
-	eudo.dp_supported = IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP);
-	eudo.tbt_supported = IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE);
-	eudo.host_present = 1;
-
-	return eudo.raw_value;
-}
-
-__overridable bool board_is_tbt_usb4_port(int port)
-{
-	return true;
+	       disc->identity.idh.product_type == IDH_PTYPE_ACABLE &&
+	       disc->identity.product_t2.a2_rev30.active_elem == ACTIVE_RETIMER;
 }
 
 __overridable void svdm_safe_dp_mode(int port)
@@ -1179,17 +812,17 @@ __overridable int svdm_enter_dp_mode(int port, uint32_t mode_caps)
 		return -1;
 #endif
 
-	/*
-	 * TCPMv2: Enable logging of CCD line state CCD_MODE_ODL.
-	 * DisplayPort Alternate mode requires that the SBU lines are used for
-	 * AUX communication.
-	 * However, in Chromebooks SBU signals are repurposed as USB2 signals
-	 * for CCD. This functionality is accomplished by override fets whose
-	 * state is controlled by CCD_MODE_ODL.
-	 *
-	 * This condition helps in debugging unexpected AUX timeout issues by
-	 * indicating the state of the CCD override fets.
-	 */
+		/*
+		 * TCPMv2: Enable logging of CCD line state CCD_MODE_ODL.
+		 * DisplayPort Alternate mode requires that the SBU lines are
+		 * used for AUX communication. However, in Chromebooks SBU
+		 * signals are repurposed as USB2 signals for CCD. This
+		 * functionality is accomplished by override fets whose state is
+		 * controlled by CCD_MODE_ODL.
+		 *
+		 * This condition helps in debugging unexpected AUX timeout
+		 * issues by indicating the state of the CCD override fets.
+		 */
 #ifdef GPIO_CCD_MODE_ODL
 	if (!gpio_get_level(GPIO_CCD_MODE_ODL))
 		CPRINTS("WARNING: Tried to EnterMode DP with [CCD on AUX/SBU]");
@@ -1216,8 +849,8 @@ __overridable int svdm_dp_status(int port, uint32_t *payload)
 {
 	int opos = pd_alt_mode(port, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT);
 
-	payload[0] = VDO(USB_SID_DISPLAYPORT, 1,
-			 CMD_DP_STATUS | VDO_OPOS(opos));
+	payload[0] =
+		VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_STATUS | VDO_OPOS(opos));
 	payload[1] = VDO_DP_STATUS(0, /* HPD IRQ  ... not applicable */
 				   0, /* HPD level ... not applicable */
 				   0, /* exit DP? ... no */
@@ -1242,7 +875,7 @@ mux_state_t svdm_dp_get_mux_mode(int port)
 
 	if (IS_ENABLED(CONFIG_CMD_MFALLOW))
 		mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]) &&
-			dp_port_mf_allow[port];
+			  dp_port_mf_allow[port];
 	else
 		mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]);
 
@@ -1267,7 +900,7 @@ __overridable int svdm_dp_config(int port, uint32_t *payload)
 
 	if (IS_ENABLED(CONFIG_CMD_MFALLOW))
 		mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]) &&
-			dp_port_mf_allow[port];
+			  dp_port_mf_allow[port];
 	else
 		mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]);
 
@@ -1276,11 +909,11 @@ __overridable int svdm_dp_config(int port, uint32_t *payload)
 
 	CPRINTS("pin_mode: %x, mf: %d, mux: %d", pin_mode, mf_pref, mux_mode);
 
-	payload[0] = VDO(USB_SID_DISPLAYPORT, 1,
-			 CMD_DP_CONFIG | VDO_OPOS(opos));
-	payload[1] = VDO_DP_CFG(pin_mode,      /* pin mode */
-				1,	       /* DPv1.3 signaling */
-				2);	       /* UFP connected */
+	payload[0] =
+		VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_CONFIG | VDO_OPOS(opos));
+	payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */
+				1, /* DPv1.3 signaling */
+				2); /* UFP connected */
 	return 2;
 };
 
@@ -1304,7 +937,7 @@ __overridable void svdm_dp_post_config(int port)
 	typec_set_sbu(port, true);
 
 	usb_mux_set(port, mux_mode, USB_SWITCH_CONNECT,
-		polarity_rm_dts(pd_get_polarity(port)));
+		    polarity_rm_dts(pd_get_polarity(port)));
 
 	dp_flags[port] |= DP_FLAGS_DP_ON;
 	if (!(dp_flags[port] & DP_FLAGS_HPD_HI_PENDING))
@@ -1317,8 +950,8 @@ __overridable void svdm_dp_post_config(int port)
 	svdm_hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
 #endif /* CONFIG_USB_PD_DP_HPD_GPIO */
 
-	usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL |
-				 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+	usb_mux_hpd_update(port,
+			   USB_PD_MUX_HPD_LVL | USB_PD_MUX_HPD_IRQ_DEASSERTED);
 
 #ifdef USB_PD_PORT_TCPC_MST
 	if (port == USB_PD_PORT_TCPC_MST)
@@ -1337,8 +970,7 @@ __overridable int svdm_dp_attention(int port, uint32_t *payload)
 
 	dp_status[port] = payload[1];
 
-	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
-	    (irq || lvl))
+	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && (irq || lvl))
 		/*
 		 * Wake up the AP.  IRQ or level high indicates a DP sink is now
 		 * present.
@@ -1402,7 +1034,7 @@ __overridable void svdm_exit_dp_mode(int port)
 	svdm_set_hpd_gpio(port, 0);
 #endif /* CONFIG_USB_PD_DP_HPD_GPIO */
 	usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-				 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 #ifdef USB_PD_PORT_TCPC_MST
 	if (port == USB_PD_PORT_TCPC_MST)
 		baseboard_mst_enable_control(port, 0);
@@ -1502,7 +1134,7 @@ const struct svdm_amode_fx supported_modes[] = {
 const int supported_modes_cnt = ARRAY_SIZE(supported_modes);
 
 #ifdef CONFIG_CMD_MFALLOW
-static int command_mfallow(int argc, char **argv)
+static int command_mfallow(int argc, const char **argv)
 {
 	char *e;
 	int port;
@@ -1526,5 +1158,5 @@ static int command_mfallow(int argc, char **argv)
 }
 
 DECLARE_CONSOLE_COMMAND(mfallow, command_mfallow, "port [true | false]",
-		"Controls Multifunction choice during DP Altmode.");
+			"Controls Multifunction choice during DP Altmode.");
 #endif
diff --git a/common/usb_pd_alt_mode_ufp.c b/common/usb_pd_alt_mode_ufp.c
index 3db60166d2..5585056b58 100644
--- a/common/usb_pd_alt_mode_ufp.c
+++ b/common/usb_pd_alt_mode_ufp.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/common/usb_pd_console_cmd.c b/common/usb_pd_console_cmd.c
index 3ad1944494..23f2a27b1e 100644
--- a/common/usb_pd_console_cmd.c
+++ b/common/usb_pd_console_cmd.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -23,24 +23,24 @@ static void dump_pe(int port)
 	const struct pd_discovery *disc =
 		pd_get_am_discovery(port, TCPCI_MSG_SOP);
 
-	static const char * const idh_ptype_names[]  = {
-		"UNDEF", "Hub", "Periph", "PCable", "ACable", "AMA",
-		"RSV6", "RSV7"};
-	static const char * const tx_names[] = {"SOP", "SOP'", "SOP''"};
+	static const char *const idh_ptype_names[] = { "UNDEF",	 "Hub",
+						       "Periph", "PCable",
+						       "ACable", "AMA",
+						       "RSV6",	 "RSV7" };
+	static const char *const tx_names[] = { "SOP", "SOP'", "SOP''" };
 
 	for (type = TCPCI_MSG_SOP; type < DISCOVERY_TYPE_COUNT; type++) {
 		resp = pd_get_identity_response(port, type);
 		if (pd_get_identity_discovery(port, type) != PD_DISC_COMPLETE) {
 			ccprintf("No %s identity discovered yet.\n",
-								tx_names[type]);
+				 tx_names[type]);
 			continue;
 		}
 
 		idh_ptype = resp->idh.product_type;
 		ccprintf("IDENT %s:\n", tx_names[type]);
 		ccprintf("\t[ID Header] %08x :: %s, VID:%04x\n",
-			 resp->raw_value[0],
-			 idh_ptype_names[idh_ptype],
+			 resp->raw_value[0], idh_ptype_names[idh_ptype],
 			 resp->idh.usb_vendor_id);
 
 		ccprintf("\t[Cert Stat] %08x\n", resp->cert.xid);
@@ -62,11 +62,11 @@ static void dump_pe(int port)
 		ccprintf("SVID[%d]: %04x MODES:", i, disc->svids[i].svid);
 		for (j = 0; j < disc->svids[j].mode_cnt; j++)
 			ccprintf(" [%d] %08x", j + 1,
-					disc->svids[i].mode_vdo[j]);
+				 disc->svids[i].mode_vdo[j]);
 		ccprintf("\n");
 
 		modep = pd_get_amode_data(port, TCPCI_MSG_SOP,
-				disc->svids[i].svid);
+					  disc->svids[i].svid);
 		if (modep) {
 			mode_caps = modep->data->mode_vdo[modep->opos - 1];
 			ccprintf("MODE[%d]: svid:%04x caps:%08x\n", modep->opos,
@@ -75,7 +75,7 @@ static void dump_pe(int port)
 	}
 }
 
-static int command_pe(int argc, char **argv)
+static int command_pe(int argc, const char **argv)
 {
 	int port;
 	char *e;
@@ -92,23 +92,21 @@ static int command_pe(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(pe, command_pe,
-			"<port> dump",
-			"USB PE");
+DECLARE_CONSOLE_COMMAND(pe, command_pe, "<port> dump", "USB PE");
 #endif /* CONFIG_CMD_USB_PD_PE */
 
 #ifdef CONFIG_CMD_USB_PD_CABLE
-static const char * const cable_type[] = {
+static const char *const cable_type[] = {
 	[IDH_PTYPE_PCABLE] = "Passive",
 	[IDH_PTYPE_ACABLE] = "Active",
 };
 
-static const char * const cable_curr[] = {
+static const char *const cable_curr[] = {
 	[USB_VBUS_CUR_3A] = "3A",
 	[USB_VBUS_CUR_5A] = "5A",
 };
 
-static int command_cable(int argc, char **argv)
+static int command_cable(int argc, const char **argv)
 {
 	int port;
 	char *e;
@@ -127,8 +125,7 @@ static int command_cable(int argc, char **argv)
 	ptype = get_usb_pd_cable_type(port);
 
 	ccprintf("Cable Type: ");
-	if (ptype != IDH_PTYPE_PCABLE &&
-		ptype != IDH_PTYPE_ACABLE) {
+	if (ptype != IDH_PTYPE_PCABLE && ptype != IDH_PTYPE_ACABLE) {
 		ccprintf("Not Emark Cable\n");
 		return EC_SUCCESS;
 	}
@@ -137,8 +134,9 @@ static int command_cable(int argc, char **argv)
 	cable_rev = pd_get_rev(port, TCPCI_MSG_SOP_PRIME);
 	disc = pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
 	cable_mode_resp.raw_value =
-		pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME);
-
+		IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE) ?
+			pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME) :
+			0;
 
 	/* Cable revision */
 	ccprintf("Cable Rev: %d.0\n", cable_rev + 1);
@@ -148,13 +146,15 @@ static int command_cable(int argc, char **argv)
 	 * connector type (Bit 19:18) and current handling capability bit 6:5
 	 */
 	ccprintf("Connector Type: %d\n",
-				disc->identity.product_t1.p_rev20.connector);
+		 disc->identity.product_t1.p_rev20.connector);
 
 	if (disc->identity.product_t1.p_rev20.vbus_cur) {
 		ccprintf("Cable Current: %s\n",
-		   disc->identity.product_t1.p_rev20.vbus_cur >
-		      ARRAY_SIZE(cable_curr) ? "Invalid" :
-		      cable_curr[disc->identity.product_t1.p_rev20.vbus_cur]);
+			 disc->identity.product_t1.p_rev20.vbus_cur >
+					 ARRAY_SIZE(cable_curr) ?
+				 "Invalid" :
+				 cable_curr[disc->identity.product_t1.p_rev20
+						    .vbus_cur]);
 	} else
 		ccprintf("Cable Current: Invalid\n");
 
@@ -164,7 +164,7 @@ static int command_cable(int argc, char **argv)
 	 */
 	if (ptype == IDH_PTYPE_PCABLE)
 		ccprintf("USB Superspeed Signaling support: %d\n",
-			disc->identity.product_t1.p_rev20.ss);
+			 disc->identity.product_t1.p_rev20.ss);
 
 	/*
 	 * For Rev 3.0 active cables and Rev 2.0 active and passive cables,
@@ -172,7 +172,8 @@ static int command_cable(int argc, char **argv)
 	 */
 	if (ptype == IDH_PTYPE_ACABLE)
 		ccprintf("SOP'' Controller: %s present\n",
-		      disc->identity.product_t1.a_rev20.sop_p_p ? "" : "Not");
+			 disc->identity.product_t1.a_rev20.sop_p_p ? "" :
+								     "Not");
 
 	if (cable_rev == PD_REV30) {
 		/*
@@ -180,15 +181,16 @@ static int command_cable(int argc, char **argv)
 		 * same bits 10:9.
 		 */
 		ccprintf("Max vbus voltage: %d\n",
-			20 + 10 * disc->identity.product_t1.p_rev30.vbus_max);
+			 20 + 10 * disc->identity.product_t1.p_rev30.vbus_max);
 
 		/* For Rev 3.0 Active cables */
 		if (ptype == IDH_PTYPE_ACABLE) {
 			ccprintf("SS signaling: USB_SS_GEN%u\n",
-				disc->identity.product_t2.a2_rev30.usb_gen ?
-									2 : 1);
+				 disc->identity.product_t2.a2_rev30.usb_gen ?
+					 2 :
+					 1);
 			ccprintf("Number of SS lanes supported: %u\n",
-				disc->identity.product_t2.a2_rev30.usb_lanes);
+				 disc->identity.product_t2.a2_rev30.usb_lanes);
 		}
 	}
 
@@ -196,28 +198,29 @@ static int command_cable(int argc, char **argv)
 		return EC_SUCCESS;
 
 	ccprintf("Rounded support: %s\n",
-		cable_mode_resp.tbt_rounded ==
-			TBT_GEN3_GEN4_ROUNDED_NON_ROUNDED ? "Yes" : "No");
+		 cable_mode_resp.tbt_rounded ==
+				 TBT_GEN3_GEN4_ROUNDED_NON_ROUNDED ?
+			 "Yes" :
+			 "No");
 
 	ccprintf("Optical cable: %s\n",
-		cable_mode_resp.tbt_cable == TBT_CABLE_OPTICAL ? "Yes" : "No");
+		 cable_mode_resp.tbt_cable == TBT_CABLE_OPTICAL ? "Yes" : "No");
 
 	ccprintf("Retimer support: %s\n",
-		cable_mode_resp.retimer_type == USB_RETIMER ?
-			"Yes" : "No");
+		 cable_mode_resp.retimer_type == USB_RETIMER ? "Yes" : "No");
 
 	ccprintf("Link training: %s-directional\n",
-		cable_mode_resp.lsrx_comm == BIDIR_LSRX_COMM ? "Bi" : "Uni");
+		 cable_mode_resp.lsrx_comm == BIDIR_LSRX_COMM ? "Bi" : "Uni");
 
 	ccprintf("Thunderbolt cable type: %s\n",
-		cable_mode_resp.tbt_active_passive == TBT_CABLE_ACTIVE ?
-		"Active" : "Passive");
+		 cable_mode_resp.tbt_active_passive == TBT_CABLE_ACTIVE ?
+			 "Active" :
+			 "Passive");
 
 	return EC_SUCCESS;
 }
 
-DECLARE_CONSOLE_COMMAND(pdcable, command_cable,
-			"<port>",
+DECLARE_CONSOLE_COMMAND(pdcable, command_cable, "<port>",
 			"Cable Characteristics");
 #endif /* CONFIG_CMD_USB_PD_CABLE */
 
diff --git a/common/usb_pd_dual_role.c b/common/usb_pd_dual_role.c
index a748f8377b..6498e0853f 100644
--- a/common/usb_pd_dual_role.c
+++ b/common/usb_pd_dual_role.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -13,7 +13,7 @@
 #include "usb_pd.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 /* The macro is used to prevent a DBZ exception while decoding PDOs. */
 #define PROCESS_ZERO_DIVISOR(x) ((x) == 0 ? 1 : (x))
@@ -66,8 +66,8 @@ static bool pd_get_usb_comm_capable(int port)
  * PD_MAX_VOLTAGE_MV and PD_OPERATING_POWER_MW. And in turn, does not
  * use the following functions.
  */
-int pd_find_pdo_index(uint32_t src_cap_cnt, const uint32_t * const src_caps,
-					int max_mv, uint32_t *selected_pdo)
+int pd_find_pdo_index(uint32_t src_cap_cnt, const uint32_t *const src_caps,
+		      int max_mv, uint32_t *selected_pdo)
 {
 	int i, uw, mv;
 	int ret = 0;
@@ -157,10 +157,10 @@ int pd_find_pdo_index(uint32_t src_cap_cnt, const uint32_t * const src_caps,
 						 mv < cur_mv)
 						prefer_cur = 1;
 				}
-			/*
-			 * pick the largest power if we don't see one staisfy
-			 * desired power
-			 */
+				/*
+				 * pick the largest power if we don't see one
+				 * staisfy desired power
+				 */
 			} else if (cur_uw == 0 || uw > cur_uw) {
 				prefer_cur = 1;
 			}
@@ -225,7 +225,7 @@ void pd_extract_pdo_power(uint32_t pdo, uint32_t *ma, uint32_t *max_mv,
 }
 
 void pd_build_request(int32_t vpd_vdo, uint32_t *rdo, uint32_t *ma,
-			uint32_t *mv, int port)
+		      uint32_t *mv, int port)
 {
 	uint32_t pdo;
 	int pdo_index, flags = 0;
@@ -236,7 +236,7 @@ void pd_build_request(int32_t vpd_vdo, uint32_t *rdo, uint32_t *ma,
 	int vpd_vbus_dcr;
 	int vpd_gnd_dcr;
 	uint32_t src_cap_cnt = pd_get_src_cap_cnt(port);
-	const uint32_t * const src_caps = pd_get_src_caps(port);
+	const uint32_t *const src_caps = pd_get_src_caps(port);
 	int charging_allowed;
 	int max_request_allowed;
 	uint32_t max_request_mv = pd_get_max_voltage();
@@ -265,8 +265,7 @@ void pd_build_request(int32_t vpd_vdo, uint32_t *rdo, uint32_t *ma,
 		max_request_allowed = 1;
 
 	if (IS_ENABLED(CONFIG_USB_PD_DPS) && dps_is_enabled())
-		max_request_mv =
-			MIN(max_request_mv, dps_get_dynamic_voltage());
+		max_request_mv = MIN(max_request_mv, dps_get_dynamic_voltage());
 
 	/*
 	 * If currently charging on a different port, or we are not allowed to
@@ -275,7 +274,7 @@ void pd_build_request(int32_t vpd_vdo, uint32_t *rdo, uint32_t *ma,
 	if (charging_allowed && max_request_allowed) {
 		/* find pdo index for max voltage we can request */
 		pdo_index = pd_find_pdo_index(src_cap_cnt, src_caps,
-						max_request_mv, &pdo);
+					      max_request_mv, &pdo);
 	} else {
 		/* src cap 0 should be vSafe5V */
 		pdo_index = 0;
@@ -319,28 +318,28 @@ void pd_build_request(int32_t vpd_vdo, uint32_t *rdo, uint32_t *ma,
 		flags |= RDO_CAP_MISMATCH;
 
 #ifdef CONFIG_USB_PD_GIVE_BACK
-		/* Tell source we are give back capable. */
-		flags |= RDO_GIVE_BACK;
+	/* Tell source we are give back capable. */
+	flags |= RDO_GIVE_BACK;
 
-		/*
-		 * BATTERY PDO: Inform the source that the sink will reduce
-		 * power to this minimum level on receipt of a GotoMin Request.
-		 */
-		max_or_min_mw = PD_MIN_POWER_MW;
+	/*
+	 * BATTERY PDO: Inform the source that the sink will reduce
+	 * power to this minimum level on receipt of a GotoMin Request.
+	 */
+	max_or_min_mw = PD_MIN_POWER_MW;
 
-		/*
-		 * FIXED or VARIABLE PDO: Inform the source that the sink will
-		 * reduce current to this minimum level on receipt of a GotoMin
-		 * Request.
-		 */
-		max_or_min_ma = PD_MIN_CURRENT_MA;
+	/*
+	 * FIXED or VARIABLE PDO: Inform the source that the sink will
+	 * reduce current to this minimum level on receipt of a GotoMin
+	 * Request.
+	 */
+	max_or_min_ma = PD_MIN_CURRENT_MA;
 #else
-		/*
-		 * Can't give back, so set maximum current and power to
-		 * operating level.
-		 */
-		max_or_min_ma = *ma;
-		max_or_min_mw = uw / 1000;
+	/*
+	 * Can't give back, so set maximum current and power to
+	 * operating level.
+	 */
+	max_or_min_ma = *ma;
+	max_or_min_mw = uw / 1000;
 #endif
 
 	if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_BATTERY) {
@@ -381,8 +380,7 @@ void pd_process_source_cap(int port, int cnt, uint32_t *src_caps)
 
 		/* Get max power info that we could request */
 		pd_find_pdo_index(pd_get_src_cap_cnt(port),
-					pd_get_src_caps(port),
-					max_mv, &pdo);
+				  pd_get_src_caps(port), max_mv, &pdo);
 		pd_extract_pdo_power(pdo, &ma, &mv, &unused);
 
 		/* Set max. limit, but apply 500mA ceiling */
@@ -397,8 +395,7 @@ bool pd_is_battery_capable(void)
 	bool capable;
 
 	/* Battery is present and at some minimum percentage. */
-	capable = (usb_get_battery_soc() >=
-		   CONFIG_USB_PD_TRY_SRC_MIN_BATT_SOC);
+	capable = (usb_get_battery_soc() >= CONFIG_USB_PD_TRY_SRC_MIN_BATT_SOC);
 
 #ifdef CONFIG_BATTERY_REVIVE_DISCONNECT
 	/*
@@ -406,9 +403,8 @@ bool pd_is_battery_capable(void)
 	 * FET may not be enabled and so attempting being a SRC may cut off
 	 * our only power source at the time.
 	 */
-	capable &= (battery_get_disconnect_state() ==
-		    BATTERY_NOT_DISCONNECTED);
-#elif defined(CONFIG_BATTERY_PRESENT_CUSTOM) ||	\
+	capable &= (battery_get_disconnect_state() == BATTERY_NOT_DISCONNECTED);
+#elif defined(CONFIG_BATTERY_PRESENT_CUSTOM) || \
 	defined(CONFIG_BATTERY_PRESENT_GPIO)
 	/*
 	 * When battery is cutoff in ship mode it may not be reliable to
@@ -443,7 +439,7 @@ bool pd_is_try_source_capable(void)
 	 * therefore allow Try.Src if we're toggling.
 	 */
 	new_try_src = try_src && (charge_manager_get_supplier() ==
-			     CHARGE_SUPPLIER_DEDICATED);
+				  CHARGE_SUPPLIER_DEDICATED);
 #endif /* CONFIG_DEDICATED_CHARGE_PORT_COUNT */
 
 	return new_try_src;
diff --git a/common/usb_pd_flags.c b/common/usb_pd_flags.c
index 073637e05b..89225f7730 100644
--- a/common/usb_pd_flags.c
+++ b/common/usb_pd_flags.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,7 +17,7 @@ BUILD_ASSERT(sizeof(usb_pd_flags) == sizeof(uint32_t));
 enum usb_pd_vbus_detect get_usb_pd_vbus_detect(void)
 {
 	if (IS_ENABLED(CONFIG_USB_PD_RUNTIME_FLAGS))
-		return (enum usb_pd_vbus_detect) usb_pd_flags.vbus_detect;
+		return (enum usb_pd_vbus_detect)usb_pd_flags.vbus_detect;
 	else if (IS_ENABLED(CONFIG_USB_PD_VBUS_DETECT_TCPC))
 		return (enum usb_pd_vbus_detect)USB_PD_VBUS_DETECT_TCPC;
 	else if (IS_ENABLED(CONFIG_USD_PD_VBUS_DETECT_GPIO))
diff --git a/common/usb_pd_host_cmd.c b/common/usb_pd_host_cmd.c
index 09a5697829..8d43571a3f 100644
--- a/common/usb_pd_host_cmd.c
+++ b/common/usb_pd_host_cmd.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -20,8 +20,8 @@
 #include "usb_pd_tcpm.h"
 #include "usb_pd.h"
 #ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 #else /* CONFIG_COMMON_RUNTIME */
 #define CPRINTF(format, args...)
 #define CPRINTS(format, args...)
@@ -38,9 +38,7 @@ static enum ec_status hc_pd_ports(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_USB_PD_PORTS,
-		     hc_pd_ports,
-		     EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_USB_PD_PORTS, hc_pd_ports, EC_VER_MASK(0));
 
 #ifdef CONFIG_HOSTCMD_RWHASHPD
 static enum ec_status
@@ -71,8 +69,7 @@ hc_remote_rw_hash_entry(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_USB_PD_RW_HASH_ENTRY,
-		     hc_remote_rw_hash_entry,
+DECLARE_HOST_COMMAND(EC_CMD_USB_PD_RW_HASH_ENTRY, hc_remote_rw_hash_entry,
 		     EC_VER_MASK(0));
 #endif /* CONFIG_HOSTCMD_RWHASHPD */
 
@@ -93,15 +90,14 @@ static enum ec_status hc_remote_pd_chip_info(struct host_cmd_handler_args *args)
 	 * same layout for v0 data. (v1 just appends data)
 	 */
 	args->response_size =
-		args->version ? sizeof(struct ec_response_pd_chip_info_v1)
-			      : sizeof(struct ec_response_pd_chip_info);
+		args->version ? sizeof(struct ec_response_pd_chip_info_v1) :
+				sizeof(struct ec_response_pd_chip_info);
 
 	memcpy(args->response, &info, args->response_size);
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_PD_CHIP_INFO,
-		     hc_remote_pd_chip_info,
+DECLARE_HOST_COMMAND(EC_CMD_PD_CHIP_INFO, hc_remote_pd_chip_info,
 		     EC_VER_MASK(0) | EC_VER_MASK(1));
 #endif /* CONFIG_EC_CMD_PD_CHIP_INFO && !CONFIG_USB_PD_TCPC */
 
@@ -110,8 +106,8 @@ static enum ec_status hc_remote_pd_set_amode(struct host_cmd_handler_args *args)
 {
 	const struct ec_params_usb_pd_set_mode_request *p = args->params;
 
-	if ((p->port >= board_get_usb_pd_port_count()) ||
-	    (!p->svid) || (!p->opos))
+	if ((p->port >= board_get_usb_pd_port_count()) || (!p->svid) ||
+	    (!p->opos))
 		return EC_RES_INVALID_PARAM;
 
 	switch (p->cmd) {
@@ -126,16 +122,16 @@ static enum ec_status hc_remote_pd_set_amode(struct host_cmd_handler_args *args)
 		break;
 	case PD_ENTER_MODE:
 		if (pd_dfp_enter_mode(p->port, TCPCI_MSG_SOP, p->svid, p->opos))
-			pd_send_vdm(p->port, p->svid, CMD_ENTER_MODE |
-				    VDO_OPOS(p->opos), NULL, 0);
+			pd_send_vdm(p->port, p->svid,
+				    CMD_ENTER_MODE | VDO_OPOS(p->opos), NULL,
+				    0);
 		break;
 	default:
 		return EC_RES_INVALID_PARAM;
 	}
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_USB_PD_SET_AMODE,
-		     hc_remote_pd_set_amode,
+DECLARE_HOST_COMMAND(EC_CMD_USB_PD_SET_AMODE, hc_remote_pd_set_amode,
 		     EC_VER_MASK(0));
 
 static enum ec_status hc_remote_pd_discovery(struct host_cmd_handler_args *args)
@@ -156,8 +152,7 @@ static enum ec_status hc_remote_pd_discovery(struct host_cmd_handler_args *args)
 	args->response_size = sizeof(*r);
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_USB_PD_DISCOVERY,
-		     hc_remote_pd_discovery,
+DECLARE_HOST_COMMAND(EC_CMD_USB_PD_DISCOVERY, hc_remote_pd_discovery,
 		     EC_VER_MASK(0));
 
 static enum ec_status hc_remote_pd_get_amode(struct host_cmd_handler_args *args)
@@ -180,7 +175,7 @@ static enum ec_status hc_remote_pd_get_amode(struct host_cmd_handler_args *args)
 	r->svid = pd_get_svid(p->port, p->svid_idx, TCPCI_MSG_SOP);
 	r->opos = 0;
 	memcpy(r->vdo, pd_get_mode_vdo(p->port, p->svid_idx, TCPCI_MSG_SOP),
-		sizeof(uint32_t) * PDO_MODES);
+	       sizeof(uint32_t) * PDO_MODES);
 	modep = pd_get_amode_data(p->port, TCPCI_MSG_SOP, r->svid);
 
 	if (modep)
@@ -189,8 +184,7 @@ static enum ec_status hc_remote_pd_get_amode(struct host_cmd_handler_args *args)
 	args->response_size = sizeof(*r);
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_USB_PD_GET_AMODE,
-		     hc_remote_pd_get_amode,
+DECLARE_HOST_COMMAND(EC_CMD_USB_PD_GET_AMODE, hc_remote_pd_get_amode,
 		     EC_VER_MASK(0));
 
 #endif /* CONFIG_USB_PD_ALT_MODE_DFP */
@@ -215,23 +209,22 @@ static enum ec_status hc_remote_pd_dev_info(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_USB_PD_DEV_INFO,
-		     hc_remote_pd_dev_info,
+DECLARE_HOST_COMMAND(EC_CMD_USB_PD_DEV_INFO, hc_remote_pd_dev_info,
 		     EC_VER_MASK(0));
 
 static const enum pd_dual_role_states dual_role_map[USB_PD_CTRL_ROLE_COUNT] = {
-	[USB_PD_CTRL_ROLE_TOGGLE_ON]    = PD_DRP_TOGGLE_ON,
-	[USB_PD_CTRL_ROLE_TOGGLE_OFF]   = PD_DRP_TOGGLE_OFF,
-	[USB_PD_CTRL_ROLE_FORCE_SINK]   = PD_DRP_FORCE_SINK,
+	[USB_PD_CTRL_ROLE_TOGGLE_ON] = PD_DRP_TOGGLE_ON,
+	[USB_PD_CTRL_ROLE_TOGGLE_OFF] = PD_DRP_TOGGLE_OFF,
+	[USB_PD_CTRL_ROLE_FORCE_SINK] = PD_DRP_FORCE_SINK,
 	[USB_PD_CTRL_ROLE_FORCE_SOURCE] = PD_DRP_FORCE_SOURCE,
-	[USB_PD_CTRL_ROLE_FREEZE]       = PD_DRP_FREEZE,
+	[USB_PD_CTRL_ROLE_FREEZE] = PD_DRP_FREEZE,
 };
 
 static const mux_state_t typec_mux_map[USB_PD_CTRL_MUX_COUNT] = {
 	[USB_PD_CTRL_MUX_NONE] = USB_PD_MUX_NONE,
-	[USB_PD_CTRL_MUX_USB]  = USB_PD_MUX_USB_ENABLED,
+	[USB_PD_CTRL_MUX_USB] = USB_PD_MUX_USB_ENABLED,
 	[USB_PD_CTRL_MUX_AUTO] = USB_PD_MUX_DP_ENABLED,
-	[USB_PD_CTRL_MUX_DP]   = USB_PD_MUX_DP_ENABLED,
+	[USB_PD_CTRL_MUX_DP] = USB_PD_MUX_DP_ENABLED,
 	[USB_PD_CTRL_MUX_DOCK] = USB_PD_MUX_DOCK,
 };
 
@@ -248,7 +241,8 @@ static uint8_t get_pd_control_flags(int port)
 	union tbt_mode_resp_device device_resp;
 	uint8_t control_flags = 0;
 
-	if (!IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP))
+	if (!IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP) ||
+	    !IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE))
 		return 0;
 
 	cable_resp.raw_value = pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME);
@@ -260,14 +254,18 @@ static uint8_t get_pd_control_flags(int port)
 	 * For Passive cables, Active Cable Plug link training is set to 0
 	 */
 	control_flags |= (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE ||
-			 cable_resp.tbt_active_passive == TBT_CABLE_ACTIVE) ?
-			 USB_PD_CTRL_ACTIVE_CABLE : 0;
+			  cable_resp.tbt_active_passive == TBT_CABLE_ACTIVE) ?
+				 USB_PD_CTRL_ACTIVE_CABLE :
+				 0;
 	control_flags |= cable_resp.tbt_cable == TBT_CABLE_OPTICAL ?
-			 USB_PD_CTRL_OPTICAL_CABLE : 0;
+				 USB_PD_CTRL_OPTICAL_CABLE :
+				 0;
 	control_flags |= device_resp.tbt_adapter == TBT_ADAPTER_TBT2_LEGACY ?
-			 USB_PD_CTRL_TBT_LEGACY_ADAPTER : 0;
+				 USB_PD_CTRL_TBT_LEGACY_ADAPTER :
+				 0;
 	control_flags |= cable_resp.lsrx_comm == UNIDIR_LSRX_COMM ?
-			 USB_PD_CTRL_ACTIVE_LINK_UNIDIR : 0;
+				 USB_PD_CTRL_ACTIVE_LINK_UNIDIR :
+				 0;
 
 	return control_flags;
 }
@@ -275,19 +273,23 @@ static uint8_t get_pd_control_flags(int port)
 static uint8_t pd_get_role_flags(int port)
 {
 	return (pd_get_power_role(port) == PD_ROLE_SOURCE ?
-			PD_CTRL_RESP_ROLE_POWER : 0) |
-		(pd_get_data_role(port) == PD_ROLE_DFP ?
-			PD_CTRL_RESP_ROLE_DATA : 0) |
-		(pd_get_vconn_state(port) ?
-			PD_CTRL_RESP_ROLE_VCONN : 0) |
-		(pd_get_partner_dual_role_power(port) ?
-			PD_CTRL_RESP_ROLE_DR_POWER : 0) |
-		(pd_get_partner_data_swap_capable(port) ?
-			PD_CTRL_RESP_ROLE_DR_DATA : 0) |
-		(pd_get_partner_usb_comm_capable(port) ?
-			PD_CTRL_RESP_ROLE_USB_COMM : 0) |
-		(pd_get_partner_unconstr_power(port) ?
-			PD_CTRL_RESP_ROLE_UNCONSTRAINED : 0);
+			PD_CTRL_RESP_ROLE_POWER :
+			0) |
+	       (pd_get_data_role(port) == PD_ROLE_DFP ? PD_CTRL_RESP_ROLE_DATA :
+							0) |
+	       (pd_get_vconn_state(port) ? PD_CTRL_RESP_ROLE_VCONN : 0) |
+	       (pd_get_partner_dual_role_power(port) ?
+			PD_CTRL_RESP_ROLE_DR_POWER :
+			0) |
+	       (pd_get_partner_data_swap_capable(port) ?
+			PD_CTRL_RESP_ROLE_DR_DATA :
+			0) |
+	       (pd_get_partner_usb_comm_capable(port) ?
+			PD_CTRL_RESP_ROLE_USB_COMM :
+			0) |
+	       (pd_get_partner_unconstr_power(port) ?
+			PD_CTRL_RESP_ROLE_UNCONSTRAINED :
+			0);
 }
 
 static enum ec_status hc_usb_pd_control(struct host_cmd_handler_args *args)
@@ -313,11 +315,11 @@ static enum ec_status hc_usb_pd_control(struct host_cmd_handler_args *args)
 	}
 
 	if (IS_ENABLED(CONFIG_USBC_SS_MUX) &&
-		p->mux != USB_PD_CTRL_MUX_NO_CHANGE)
+	    p->mux != USB_PD_CTRL_MUX_NO_CHANGE)
 		usb_mux_set(p->port, typec_mux_map[p->mux],
 			    typec_mux_map[p->mux] == USB_PD_MUX_NONE ?
-			    USB_SWITCH_DISCONNECT :
-			    USB_SWITCH_CONNECT,
+				    USB_SWITCH_DISCONNECT :
+				    USB_SWITCH_CONNECT,
 			    polarity_rm_dts(pd_get_polarity(p->port)));
 
 	if (p->swap == USB_PD_CTRL_SWAP_DATA) {
@@ -326,7 +328,7 @@ static enum ec_status hc_usb_pd_control(struct host_cmd_handler_args *args)
 		if (p->swap == USB_PD_CTRL_SWAP_POWER)
 			pd_request_power_swap(p->port);
 		else if (IS_ENABLED(CONFIG_USBC_VCONN_SWAP) &&
-			p->swap == USB_PD_CTRL_SWAP_VCONN)
+			 p->swap == USB_PD_CTRL_SWAP_VCONN)
 			pd_request_vconn_swap(p->port);
 	}
 
@@ -340,17 +342,19 @@ static enum ec_status hc_usb_pd_control(struct host_cmd_handler_args *args)
 		break;
 	case 1:
 	case 2:
-		r_v2->enabled =
-			(pd_comm_is_enabled(p->port) ?
-				PD_CTRL_RESP_ENABLED_COMMS : 0) |
-			(pd_is_connected(p->port) ?
-				PD_CTRL_RESP_ENABLED_CONNECTED : 0) |
-			(pd_capable(p->port) ?
-				PD_CTRL_RESP_ENABLED_PD_CAPABLE : 0);
+		r_v2->enabled = (pd_comm_is_enabled(p->port) ?
+					 PD_CTRL_RESP_ENABLED_COMMS :
+					 0) |
+				(pd_is_connected(p->port) ?
+					 PD_CTRL_RESP_ENABLED_CONNECTED :
+					 0) |
+				(pd_capable(p->port) ?
+					 PD_CTRL_RESP_ENABLED_PD_CAPABLE :
+					 0);
 		r_v2->role = pd_get_role_flags(p->port);
 		r_v2->polarity = pd_get_polarity(p->port);
 
-		r_v2->cc_state =  pd_get_task_cc_state(p->port);
+		r_v2->cc_state = pd_get_task_cc_state(p->port);
 		task_state_name = pd_get_task_state_name(p->port);
 		if (task_state_name)
 			strzcpy(r_v2->state, task_state_name,
@@ -361,8 +365,12 @@ static enum ec_status hc_usb_pd_control(struct host_cmd_handler_args *args)
 		r_v2->control_flags = get_pd_control_flags(p->port);
 		if (IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP)) {
 			r_v2->dp_mode = get_dp_pin_mode(p->port);
-			r_v2->cable_speed = get_tbt_cable_speed(p->port);
-			r_v2->cable_gen = get_tbt_rounded_support(p->port);
+			if (IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE)) {
+				r_v2->cable_speed =
+					get_tbt_cable_speed(p->port);
+				r_v2->cable_gen =
+					get_tbt_rounded_support(p->port);
+			}
 		}
 
 		if (args->version == 1)
@@ -376,8 +384,7 @@ static enum ec_status hc_usb_pd_control(struct host_cmd_handler_args *args)
 	}
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_USB_PD_CONTROL,
-		     hc_usb_pd_control,
+DECLARE_HOST_COMMAND(EC_CMD_USB_PD_CONTROL, hc_usb_pd_control,
 		     EC_VER_MASK(0) | EC_VER_MASK(1) | EC_VER_MASK(2));
 #endif /* CONFIG_COMMON_RUNTIME */
 
@@ -397,14 +404,14 @@ static enum ec_status hc_remote_flash(struct host_cmd_handler_args *args)
 		return EC_RES_INVALID_PARAM;
 
 #if defined(CONFIG_CHARGE_MANAGER) && defined(CONFIG_BATTERY) && \
-	(defined(CONFIG_BATTERY_PRESENT_CUSTOM) ||   \
+	(defined(CONFIG_BATTERY_PRESENT_CUSTOM) ||               \
 	 defined(CONFIG_BATTERY_PRESENT_GPIO))
 	/*
 	 * Do not allow PD firmware update if no battery and this port
 	 * is sinking power, because we will lose power.
 	 */
 	if (battery_is_present() != BP_YES &&
-			charge_manager_get_active_charge_port() == port)
+	    charge_manager_get_active_charge_port() == port)
 		return EC_RES_UNAVAILABLE;
 #endif
 
@@ -437,7 +444,7 @@ static enum ec_status hc_remote_flash(struct host_cmd_handler_args *args)
 		size = p->size / 4;
 		for (i = 0; i < size; i += VDO_MAX_SIZE - 1) {
 			pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_FLASH_WRITE,
-				data + i, MIN(size - i, VDO_MAX_SIZE - 1));
+				    data + i, MIN(size - i, VDO_MAX_SIZE - 1));
 		}
 		return EC_RES_SUCCESS;
 
@@ -447,12 +454,9 @@ static enum ec_status hc_remote_flash(struct host_cmd_handler_args *args)
 
 	return rv;
 }
-DECLARE_HOST_COMMAND(EC_CMD_USB_PD_FW_UPDATE,
-			hc_remote_flash,
-			EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_USB_PD_FW_UPDATE, hc_remote_flash, EC_VER_MASK(0));
 #endif /* CONFIG_HOSTCMD_FLASHPD && CONFIG_USB_PD_TCPMV2 */
 
-
 __overridable enum ec_pd_port_location board_get_pd_port_location(int port)
 {
 	(void)port;
@@ -479,8 +483,7 @@ static enum ec_status hc_get_pd_port_caps(struct host_cmd_handler_args *args)
 	else
 		r->pd_try_power_role_cap = EC_PD_TRY_POWER_ROLE_NONE;
 
-	if (IS_ENABLED(CONFIG_USB_VPD) ||
-	    IS_ENABLED(CONFIG_USB_CTVPD))
+	if (IS_ENABLED(CONFIG_USB_VPD) || IS_ENABLED(CONFIG_USB_CTVPD))
 		r->pd_data_role_cap = EC_PD_DATA_ROLE_UFP;
 	else
 		r->pd_data_role_cap = EC_PD_DATA_ROLE_DUAL;
@@ -492,14 +495,22 @@ static enum ec_status hc_get_pd_port_caps(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_GET_PD_PORT_CAPS,
-		     hc_get_pd_port_caps,
+DECLARE_HOST_COMMAND(EC_CMD_GET_PD_PORT_CAPS, hc_get_pd_port_caps,
 		     EC_VER_MASK(0));
 
 #ifdef CONFIG_HOSTCMD_PD_CONTROL
+static int pd_control_disabled[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+/* Only allow port re-enable in unit tests */
+#ifdef TEST_BUILD
+void pd_control_port_enable(int port)
+{
+	pd_control_disabled[port] = 0;
+}
+#endif /* TEST_BUILD */
+
 static enum ec_status pd_control(struct host_cmd_handler_args *args)
 {
-	static int pd_control_disabled[CONFIG_USB_PD_PORT_MAX_COUNT];
 	const struct ec_params_pd_control *cmd = args->params;
 	int enable = 0;
 
diff --git a/common/usb_pd_pdo.c b/common/usb_pd_pdo.c
index cfa355bf0e..3141af34a9 100644
--- a/common/usb_pd_pdo.c
+++ b/common/usb_pd_pdo.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/common/usb_pd_policy.c b/common/usb_pd_policy.c
index 30aa936f28..c63cde6301 100644
--- a/common/usb_pd_policy.c
+++ b/common/usb_pd_policy.c
@@ -1,9 +1,10 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "atomic.h"
+#include "builtin/assert.h"
 #include "charge_manager.h"
 #include "common.h"
 #include "console.h"
@@ -77,20 +78,11 @@ __overridable void pd_check_dr_role(int port, enum pd_data_role dr_role,
 		pd_request_data_swap(port);
 }
 
-#ifdef CONFIG_MKBP_EVENT
-static int dp_alt_mode_entry_get_next_event(uint8_t *data)
-{
-	return EC_SUCCESS;
-}
-DECLARE_EVENT_SOURCE(EC_MKBP_EVENT_DP_ALT_MODE_ENTERED,
-		     dp_alt_mode_entry_get_next_event);
-#endif /* CONFIG_MKBP_EVENT */
-
 /* Last received source cap */
 static uint32_t pd_src_caps[CONFIG_USB_PD_PORT_MAX_COUNT][PDO_MAX_OBJECTS];
 static uint8_t pd_src_cap_cnt[CONFIG_USB_PD_PORT_MAX_COUNT];
 
-const uint32_t * const pd_get_src_caps(int port)
+const uint32_t *const pd_get_src_caps(int port)
 {
 	return pd_src_caps[port];
 }
@@ -110,76 +102,6 @@ uint8_t pd_get_src_cap_cnt(int port)
 	return pd_src_cap_cnt[port];
 }
 
-static struct pd_cable cable[CONFIG_USB_PD_PORT_MAX_COUNT];
-
-enum pd_rev_type get_usb_pd_cable_revision(int port)
-{
-	return cable[port].rev;
-}
-
-bool consume_sop_prime_repeat_msg(int port, uint8_t msg_id)
-{
-	if (cable[port].last_sop_p_msg_id != msg_id) {
-		cable[port].last_sop_p_msg_id = msg_id;
-		return false;
-	}
-	CPRINTF("C%d SOP Prime repeat msg_id %d\n", port, msg_id);
-	return true;
-}
-
-bool consume_sop_prime_prime_repeat_msg(int port, uint8_t msg_id)
-{
-	if (cable[port].last_sop_p_p_msg_id != msg_id) {
-		cable[port].last_sop_p_p_msg_id = msg_id;
-		return false;
-	}
-	CPRINTF("C%d SOP Prime Prime repeat msg_id %d\n", port, msg_id);
-	return true;
-}
-
-__maybe_unused static uint8_t is_sop_prime_ready(int port)
-{
-	/*
-	 * Ref: USB PD 3.0 sec 2.5.4: When an Explicit Contract is in place the
-	 * VCONN Source (either the DFP or the UFP) can communicate with the
-	 * Cable Plug(s) using SOP’/SOP’’ Packets
-	 *
-	 * Ref: USB PD 2.0 sec 2.4.4: When an Explicit Contract is in place the
-	 * DFP (either the Source or the Sink) can communicate with the
-	 * Cable Plug(s) using SOP’/SOP” Packets.
-	 * Sec 3.6.11 : Before communicating with a Cable Plug a Port Should
-	 * ensure that it is the Vconn Source
-	 */
-	return (pd_get_vconn_state(port) &&
-		(IS_ENABLED(CONFIG_USB_PD_REV30) ||
-		 (pd_get_data_role(port) == PD_ROLE_DFP)));
-}
-
-void reset_pd_cable(int port)
-{
-	memset(&cable[port], 0, sizeof(cable[port]));
-	cable[port].last_sop_p_msg_id = INVALID_MSG_ID_COUNTER;
-	cable[port].last_sop_p_p_msg_id = INVALID_MSG_ID_COUNTER;
-}
-
-bool should_enter_usb4_mode(int port)
-{
-	return IS_ENABLED(CONFIG_USB_PD_USB4) &&
-	       cable[port].flags & CABLE_FLAGS_ENTER_USB_MODE;
-}
-
-void enable_enter_usb4_mode(int port)
-{
-	if (IS_ENABLED(CONFIG_USB_PD_USB4))
-		cable[port].flags |= CABLE_FLAGS_ENTER_USB_MODE;
-}
-
-void disable_enter_usb4_mode(int port)
-{
-	if (IS_ENABLED(CONFIG_USB_PD_USB4))
-		cable[port].flags &= ~CABLE_FLAGS_ENTER_USB_MODE;
-}
-
 #ifdef CONFIG_USB_PD_ALT_MODE
 
 #ifdef CONFIG_USB_PD_ALT_MODE_DFP
@@ -189,168 +111,6 @@ static struct pd_discovery discovery[CONFIG_USB_PD_PORT_MAX_COUNT]
 static struct partner_active_modes partner_amodes[CONFIG_USB_PD_PORT_MAX_COUNT]
 						 [AMODE_TYPE_COUNT];
 
-static bool is_vdo_present(int cnt, int index)
-{
-	return cnt > index;
-}
-
-static bool is_modal(int port, int cnt, const uint32_t *payload)
-{
-	return is_vdo_present(cnt, VDO_INDEX_IDH) &&
-	       PD_IDH_IS_MODAL(payload[VDO_INDEX_IDH]);
-}
-
-static bool is_tbt_compat_mode(int port, int cnt, const uint32_t *payload)
-{
-	/*
-	 * Ref: USB Type-C cable and connector specification
-	 * F.2.5 TBT3 Device Discover Mode Responses
-	 */
-	return is_vdo_present(cnt, VDO_INDEX_IDH) &&
-	       PD_VDO_RESP_MODE_INTEL_TBT(payload[VDO_INDEX_IDH]);
-}
-
-static bool cable_supports_tbt_speed(int port)
-{
-	enum tbt_compat_cable_speed tbt_cable_speed = get_tbt_cable_speed(port);
-
-	return (tbt_cable_speed == TBT_SS_TBT_GEN3 ||
-		tbt_cable_speed == TBT_SS_U32_GEN1_GEN2);
-}
-
-static bool is_tbt_compat_enabled(int port)
-{
-	return (IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE) &&
-		(cable[port].flags & CABLE_FLAGS_TBT_COMPAT_ENABLE));
-}
-
-static void enable_tbt_compat_mode(int port)
-{
-	if (IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE))
-		cable[port].flags |= CABLE_FLAGS_TBT_COMPAT_ENABLE;
-}
-
-static inline void disable_tbt_compat_mode(int port)
-{
-	if (IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE))
-		cable[port].flags &= ~CABLE_FLAGS_TBT_COMPAT_ENABLE;
-}
-
-static inline void limit_tbt_cable_speed(int port)
-{
-	/* Cable flags are cleared when cable reset is called */
-	cable[port].flags |= CABLE_FLAGS_TBT_COMPAT_LIMIT_SPEED;
-}
-
-static inline bool is_limit_tbt_cable_speed(int port)
-{
-	return !!(cable[port].flags & CABLE_FLAGS_TBT_COMPAT_LIMIT_SPEED);
-}
-
-static bool is_intel_svid(int port, enum tcpci_msg_type type)
-{
-	int i;
-
-	for (i = 0; i < discovery[port][type].svid_cnt; i++) {
-		if (pd_get_svid(port, i, type) == USB_VID_INTEL)
-			return true;
-	}
-
-	return false;
-}
-
-static inline bool is_usb4_mode_enabled(int port)
-{
-	return (IS_ENABLED(CONFIG_USB_PD_USB4) &&
-		(cable[port].flags & CABLE_FLAGS_USB4_CAPABLE));
-}
-
-static inline void enable_usb4_mode(int port)
-{
-	if (IS_ENABLED(CONFIG_USB_PD_USB4))
-		cable[port].flags |= CABLE_FLAGS_USB4_CAPABLE;
-}
-
-static inline void disable_usb4_mode(int port)
-{
-	if (IS_ENABLED(CONFIG_USB_PD_USB4))
-		cable[port].flags &= ~CABLE_FLAGS_USB4_CAPABLE;
-}
-
-/*
- * Ref: USB Type-C Cable and Connector Specification
- * Figure 5-1 USB4 Discovery and Entry Flow Model.
- *
- * Note: USB Type-C Cable and Connector Specification
- * doesn't include details for Revision 2 cables.
- *
- *                         Passive Cable
- *                                |
- *                -----------------------------------
- *                |                                 |
- *           Revision 2                        Revision 3
- *          USB Signalling                   USB Signalling
- *             |                                     |
- *     ------------------            -------------------------
- *     |       |        |            |       |       |       |
- * USB2.0   USB3.1    USB3.1       USB3.2   USB4   USB3.2   USB2
- *   |      Gen1      Gen1 Gen2    Gen2     Gen3   Gen1       |
- *   |       |          |           |        |       |       Exit
- *   --------           ------------         --------        USB4
- *      |                    |                  |          Discovery.
- *    Exit          Is DFP Gen3 Capable?     Enter USB4
- *    USB4                  |                with respective
- *   Discovery.   --- No ---|--- Yes ---     cable speed.
- *                |                    |
- *    Enter USB4 with             Is Cable TBT3
- *    respective cable                 |
- *    speed.                 --- No ---|--- Yes ---
- *                           |                    |
- *                   Enter USB4 with        Enter USB4 with
- *                   TBT Gen2 passive       TBT Gen3 passive
- *                   cable.                 cable.
- *
- */
-static bool is_cable_ready_to_enter_usb4(int port, int cnt)
-{
-	/* TODO: USB4 enter mode for Active cables */
-	struct pd_discovery *disc = &discovery[port][TCPCI_MSG_SOP_PRIME];
-	if (IS_ENABLED(CONFIG_USB_PD_USB4) &&
-	    (get_usb_pd_cable_type(port) == IDH_PTYPE_PCABLE) &&
-	    is_vdo_present(cnt, VDO_INDEX_PTYPE_CABLE1)) {
-		switch (cable[port].rev) {
-		case PD_REV30:
-			switch (disc->identity.product_t1.p_rev30.ss) {
-			case USB_R30_SS_U40_GEN3:
-			case USB_R30_SS_U32_U40_GEN1:
-				return true;
-			case USB_R30_SS_U32_U40_GEN2:
-				/* Check if DFP is Gen 3 capable */
-				if (IS_ENABLED(CONFIG_USB_PD_TBT_GEN3_CAPABLE))
-					return false;
-				return true;
-			default:
-				disable_usb4_mode(port);
-				return false;
-			}
-		case PD_REV20:
-			switch (disc->identity.product_t1.p_rev20.ss) {
-			case USB_R20_SS_U31_GEN1_GEN2:
-				/* Check if DFP is Gen 3 capable */
-				if (IS_ENABLED(CONFIG_USB_PD_TBT_GEN3_CAPABLE))
-					return false;
-				return true;
-			default:
-				disable_usb4_mode(port);
-				return false;
-			}
-		default:
-			disable_usb4_mode(port);
-		}
-	}
-	return false;
-}
-
 void pd_dfp_discovery_init(int port)
 {
 	memset(&discovery[port], 0, sizeof(struct pd_discovery));
@@ -361,26 +121,20 @@ void pd_dfp_mode_init(int port)
 	memset(&partner_amodes[port], 0, sizeof(partner_amodes[0]));
 }
 
-static int dfp_discover_ident(uint32_t *payload)
-{
-	payload[0] = VDO(USB_SID_PD, 1, CMD_DISCOVER_IDENT);
-	return 1;
-}
-
 static int dfp_discover_svids(uint32_t *payload)
 {
 	payload[0] = VDO(USB_SID_PD, 1, CMD_DISCOVER_SVID);
 	return 1;
 }
 
-struct pd_discovery *pd_get_am_discovery_and_notify_access(
-				int port, enum tcpci_msg_type type)
+struct pd_discovery *
+pd_get_am_discovery_and_notify_access(int port, enum tcpci_msg_type type)
 {
 	return (struct pd_discovery *)pd_get_am_discovery(port, type);
 }
 
 const struct pd_discovery *pd_get_am_discovery(int port,
-			enum tcpci_msg_type type)
+					       enum tcpci_msg_type type)
 {
 	return &discovery[port][type];
 }
@@ -407,7 +161,7 @@ void pd_set_dfp_enter_mode_flag(int port, bool set)
 static int dfp_discover_modes(int port, uint32_t *payload)
 {
 	const struct pd_discovery *disc =
-			pd_get_am_discovery(port, TCPCI_MSG_SOP);
+		pd_get_am_discovery(port, TCPCI_MSG_SOP);
 	uint16_t svid = disc->svids[disc->svid_idx].svid;
 
 	if (disc->svid_idx >= disc->svid_cnt)
@@ -418,23 +172,6 @@ static int dfp_discover_modes(int port, uint32_t *payload)
 	return 1;
 }
 
-static bool is_usb4_vdo(int port, int cnt, uint32_t *payload)
-{
-	enum idh_ptype ptype = PD_IDH_PTYPE(payload[VDO_I(IDH)]);
-
-	if (IS_PD_IDH_UFP_PTYPE(ptype)) {
-		/*
-		 * Ref: USB Type-C Cable and Connector Specification
-		 * Figure 5-1 USB4 Discovery and Entry Flow Model
-		 * Device USB4 VDO detection.
-		 */
-		return IS_ENABLED(CONFIG_USB_PD_USB4) &&
-		       is_vdo_present(cnt, VDO_INDEX_PTYPE_UFP1_VDO) &&
-		       PD_PRODUCT_IS_USB4(payload[VDO_INDEX_PTYPE_UFP1_VDO]);
-	}
-	return false;
-}
-
 static int process_am_discover_ident_sop(int port, int cnt, uint32_t head,
 					 uint32_t *payload,
 					 enum tcpci_msg_type *rtype)
@@ -443,63 +180,6 @@ static int process_am_discover_ident_sop(int port, int cnt, uint32_t head,
 	pd_dfp_mode_init(port);
 	dfp_consume_identity(port, TCPCI_MSG_SOP, cnt, payload);
 
-	if (IS_ENABLED(CONFIG_USB_PD_DECODE_SOP) && is_sop_prime_ready(port) &&
-	    board_is_tbt_usb4_port(port)) {
-		/* Enable USB4 mode if USB4 VDO present and port partner
-		 * supports USB Rev 3.0.
-		 */
-		if (is_usb4_vdo(port, cnt, payload) &&
-		    PD_HEADER_REV(head) == PD_REV30)
-			enable_usb4_mode(port);
-
-		/*
-		 * Enable Thunderbolt-compatible mode if the modal operation is
-		 * supported.
-		 */
-		if (is_modal(port, cnt, payload))
-			enable_tbt_compat_mode(port);
-
-		if (is_modal(port, cnt, payload) ||
-		    is_usb4_vdo(port, cnt, payload)) {
-			*rtype = TCPCI_MSG_SOP_PRIME;
-			return dfp_discover_ident(payload);
-		}
-	}
-
-	return dfp_discover_svids(payload);
-}
-
-static int process_am_discover_ident_sop_prime(int port, int cnt, uint32_t head,
-					       uint32_t *payload)
-{
-	dfp_consume_identity(port, TCPCI_MSG_SOP_PRIME, cnt, payload);
-	cable[port].rev = PD_HEADER_REV(head);
-
-	/*
-	 * Enter USB4 mode if the cable supports USB4 operation and has USB4
-	 * VDO.
-	 */
-	if (is_usb4_mode_enabled(port) &&
-	    is_cable_ready_to_enter_usb4(port, cnt)) {
-		enable_enter_usb4_mode(port);
-		usb_mux_set_safe_mode(port);
-		/*
-		 * To change the mode of operation from USB4 the port needs to
-		 * be reconfigured.
-		 * Ref: USB Type-C Cable and Connectot Spec section 5.4.4.
-		 */
-		disable_tbt_compat_mode(port);
-		return 0;
-	}
-
-	/*
-	 * Disable Thunderbolt-compatible mode if the cable does not support
-	 * superspeed.
-	 */
-	if (is_tbt_compat_enabled(port) &&
-	    get_tbt_cable_speed(port) < TBT_SS_U31_GEN1)
-		disable_tbt_compat_mode(port);
-
 	return dfp_discover_svids(payload);
 }
 
@@ -514,133 +194,8 @@ static int process_am_discover_svids(int port, int cnt, uint32_t *payload,
 	 */
 	dfp_consume_svids(port, sop, cnt, payload);
 
-	/*
-	 * Ref: USB Type-C Cable and Connector Specification,
-	 * figure F-1: TBT3 Discovery Flow
-	 *
-	 * For USB4 mode if device or cable doesn't have Intel SVID,
-	 * disable Thunderbolt-Compatible mode directly enter USB4 mode
-	 * with USB3.2 Gen1/Gen2 speed.
-	 *
-	 * For Thunderbolt-compatible, check if 0x8087 is received for
-	 * Discover SVID SOP. If not, disable Thunderbolt-compatible mode
-	 *
-	 * If 0x8087 is not received for Discover SVID SOP' limit to TBT
-	 * passive Gen 2 cable.
-	 */
-	if (is_tbt_compat_enabled(port)) {
-		bool intel_svid = is_intel_svid(port, sop);
-		if (!intel_svid) {
-			if (is_usb4_mode_enabled(port)) {
-				disable_tbt_compat_mode(port);
-				cable[port].cable_mode_resp.tbt_cable_speed =
-					TBT_SS_U32_GEN1_GEN2;
-				enable_enter_usb4_mode(port);
-				usb_mux_set_safe_mode(port);
-				return 0;
-			}
-
-			if (sop == TCPCI_MSG_SOP_PRIME)
-				limit_tbt_cable_speed(port);
-			else
-				disable_tbt_compat_mode(port);
-		} else if (sop == TCPCI_MSG_SOP) {
-			*rtype = TCPCI_MSG_SOP_PRIME;
-			return dfp_discover_svids(payload);
-		}
-	}
-
 	return dfp_discover_modes(port, payload);
 }
-
-static int process_tbt_compat_discover_modes(int port,
-					     enum tcpci_msg_type sop,
-					     uint32_t *payload,
-					     enum tcpci_msg_type *rtype)
-{
-	int rsize;
-
-	/* Initialize transmit type to SOP */
-	*rtype = TCPCI_MSG_SOP;
-
-	/*
-	 * For active cables, Enter mode: SOP', SOP'', SOP
-	 * Ref: USB Type-C Cable and Connector Specification, figure F-1: TBT3
-	 * Discovery Flow and Section F.2.7 TBT3 Cable Enter Mode Command.
-	 */
-	if (sop == TCPCI_MSG_SOP_PRIME) {
-		/* Store Discover Mode SOP' response */
-		cable[port].cable_mode_resp.raw_value = payload[1];
-
-		if (is_usb4_mode_enabled(port)) {
-			/*
-			 * If Cable is not Thunderbolt Gen 3
-			 * capable or Thunderbolt Gen1_Gen2
-			 * capable, disable USB4 mode and
-			 * continue flow for
-			 * Thunderbolt-compatible mode
-			 */
-			if (cable_supports_tbt_speed(port)) {
-				enable_enter_usb4_mode(port);
-				usb_mux_set_safe_mode(port);
-				return 0;
-			}
-			disable_usb4_mode(port);
-		}
-
-		/*
-		 * Send TBT3 Cable Enter Mode (SOP') for active cables,
-		 * otherwise send TBT3 Device Enter Mode (SOP).
-		 */
-		if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE)
-			*rtype = TCPCI_MSG_SOP_PRIME;
-
-		rsize = enter_tbt_compat_mode(port, *rtype, payload);
-	} else {
-		/* Store Discover Mode SOP response */
-		cable[port].dev_mode_resp.raw_value = payload[1];
-
-		if (is_limit_tbt_cable_speed(port)) {
-			/*
-			 * Passive cable has Nacked for Discover SVID.
-			 * No need to do Discover modes of cable.
-			 * Enter into device Thunderbolt-compatible mode.
-			 */
-			rsize = enter_tbt_compat_mode(port, *rtype, payload);
-		} else {
-			/* Discover modes for SOP' */
-			discovery[port][TCPCI_MSG_SOP].svid_idx--;
-			rsize = dfp_discover_modes(port, payload);
-			*rtype = TCPCI_MSG_SOP_PRIME;
-		}
-	}
-
-	return rsize;
-}
-
-static int obj_cnt_enter_tbt_compat_mode(int port, enum tcpci_msg_type sop,
-					 uint32_t *payload,
-					 enum tcpci_msg_type *rtype)
-{
-	struct pd_discovery *disc = &discovery[port][TCPCI_MSG_SOP_PRIME];
-
-	/* Enter mode SOP' for active cables */
-	if (sop == TCPCI_MSG_SOP_PRIME) {
-		/* Check if the cable has a SOP'' controller */
-		if (disc->identity.product_t1.a_rev20.sop_p_p)
-			*rtype = TCPCI_MSG_SOP_PRIME_PRIME;
-		return enter_tbt_compat_mode(port, *rtype, payload);
-	}
-
-	/* Enter Mode SOP'' for active cables with SOP'' controller */
-	if (sop == TCPCI_MSG_SOP_PRIME_PRIME)
-		return enter_tbt_compat_mode(port, *rtype, payload);
-
-	/* Update Mux state to Thunderbolt-compatible mode. */
-	set_tbt_compat_mode_ready(port);
-	/* No response once device (and cable) acks */
-	return 0;
-}
 #endif /* CONFIG_USB_PD_ALT_MODE_DFP */
 
 int pd_svdm(int port, int cnt, uint32_t *payload, uint32_t **rpayload,
@@ -725,15 +280,9 @@ int pd_svdm(int port, int cnt, uint32_t *payload, uint32_t **rpayload,
 		switch (cmd) {
 #ifdef CONFIG_USB_PD_ALT_MODE_DFP
 		case CMD_DISCOVER_IDENT:
-			/* Received a SOP' Discover Ident msg */
-			if (sop == TCPCI_MSG_SOP_PRIME) {
-				rsize = process_am_discover_ident_sop_prime(
-					port, cnt, head, payload);
-				/* Received a SOP Discover Ident Message */
-			} else {
-				rsize = process_am_discover_ident_sop(
-					port, cnt, head, payload, rtype);
-			}
+			/* Received a SOP Discover Ident Message */
+			rsize = process_am_discover_ident_sop(port, cnt, head,
+							      payload, rtype);
 			break;
 		case CMD_DISCOVER_SVID:
 			rsize = process_am_discover_svids(port, cnt, payload,
@@ -741,22 +290,10 @@ int pd_svdm(int port, int cnt, uint32_t *payload, uint32_t **rpayload,
 			break;
 		case CMD_DISCOVER_MODES:
 			dfp_consume_modes(port, sop, cnt, payload);
-			if (is_tbt_compat_enabled(port) &&
-			    is_tbt_compat_mode(port, cnt, payload)) {
-				rsize = process_tbt_compat_discover_modes(
-					port, sop, payload, rtype);
-				break;
-			}
 
 			rsize = dfp_discover_modes(port, payload);
 			/* enter the default mode for DFP */
 			if (!rsize) {
-				/*
-				 * Disabling Thunderbolt-Compatible mode if
-				 * discover mode response doesn't include Intel
-				 * SVID.
-				 */
-				disable_tbt_compat_mode(port);
 				payload[0] = pd_dfp_enter_mode(
 					port, TCPCI_MSG_SOP, 0, 0);
 				if (payload[0])
@@ -764,19 +301,12 @@ int pd_svdm(int port, int cnt, uint32_t *payload, uint32_t **rpayload,
 			}
 			break;
 		case CMD_ENTER_MODE:
-			if (is_tbt_compat_enabled(port)) {
-				rsize = obj_cnt_enter_tbt_compat_mode(
-					port, sop, payload, rtype);
-				/*
-				 * Continue with PD flow if
-				 * Thunderbolt-compatible mode is disabled.
-				 */
-			} else if (!modep) {
+			if (!modep) {
 				rsize = 0;
 			} else {
 				if (!modep->opos)
 					pd_dfp_enter_mode(port, TCPCI_MSG_SOP,
-							0, 0);
+							  0, 0);
 
 				if (modep->opos) {
 					rsize = modep->fx->status(port,
@@ -805,7 +335,7 @@ int pd_svdm(int port, int cnt, uint32_t *payload, uint32_t **rpayload,
 				 * config ack).
 				 */
 				if (svdm_dp_get_mux_mode(port) ==
-							USB_PD_MUX_DP_ENABLED)
+				    USB_PD_MUX_DP_ENABLED)
 					usb_mux_set_safe_mode(port);
 				rsize = modep->fx->config(port, payload);
 			} else {
@@ -856,15 +386,7 @@ int pd_svdm(int port, int cnt, uint32_t *payload, uint32_t **rpayload,
 			rsize = 0;
 		}
 	} else if (cmd_type == CMDT_RSP_NAK) {
-		/* Passive cable Nacked for Discover SVID */
-		if (cmd == CMD_DISCOVER_SVID && is_tbt_compat_enabled(port) &&
-		    sop == TCPCI_MSG_SOP_PRIME &&
-		    get_usb_pd_cable_type(port) == IDH_PTYPE_PCABLE) {
-			limit_tbt_cable_speed(port);
-			rsize = dfp_discover_modes(port, payload);
-		} else {
-			rsize = 0;
-		}
+		rsize = 0;
 #endif /* CONFIG_USB_PD_ALT_MODE_DFP */
 	} else {
 		CPRINTF("ERR:CMDT:%d\n", cmd);
@@ -952,7 +474,7 @@ int pd_custom_flash_vdm(int port, int cnt, uint32_t *payload)
 		flash_offset =
 			CONFIG_EC_WRITABLE_STORAGE_OFF + CONFIG_RW_STORAGE_OFF;
 		crec_flash_physical_erase(CONFIG_EC_WRITABLE_STORAGE_OFF +
-					  CONFIG_RW_STORAGE_OFF,
+						  CONFIG_RW_STORAGE_OFF,
 					  CONFIG_RW_SIZE);
 		rw_flash_changed = 1;
 		break;
@@ -963,7 +485,7 @@ int pd_custom_flash_vdm(int port, int cnt, uint32_t *payload)
 		     CONFIG_EC_WRITABLE_STORAGE_OFF + CONFIG_RW_STORAGE_OFF))
 			break;
 		crec_flash_physical_write(flash_offset, 4 * (cnt - 1),
-				     (const char *)(payload + 1));
+					  (const char *)(payload + 1));
 		flash_offset += 4 * (cnt - 1);
 		rw_flash_changed = 1;
 		break;
@@ -976,7 +498,7 @@ int pd_custom_flash_vdm(int port, int cnt, uint32_t *payload)
 			for (offset = FW_RW_END - RSANUMBYTES;
 			     offset < FW_RW_END; offset += 4)
 				crec_flash_physical_write(offset, 4,
-						     (const char *)&zero);
+							  (const char *)&zero);
 		}
 		break;
 	default:
diff --git a/common/usb_pd_protocol.c b/common/usb_pd_protocol.c
index 3f0408eedf..80d3b400da 100644
--- a/common/usb_pd_protocol.c
+++ b/common/usb_pd_protocol.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,6 +7,7 @@
 #include "battery.h"
 #include "battery_smart.h"
 #include "board.h"
+#include "builtin/assert.h"
 #include "charge_manager.h"
 #include "charge_state.h"
 #include "chipset.h"
@@ -38,27 +39,19 @@
 #include "vboot.h"
 
 /* Flags to clear on a disconnect */
-#define PD_FLAGS_RESET_ON_DISCONNECT_MASK (PD_FLAGS_PARTNER_DR_POWER | \
-					   PD_FLAGS_PARTNER_DR_DATA | \
-					   PD_FLAGS_CHECK_IDENTITY | \
-					   PD_FLAGS_SNK_CAP_RECVD | \
-					   PD_FLAGS_TCPC_DRP_TOGGLE | \
-					   PD_FLAGS_EXPLICIT_CONTRACT | \
-					   PD_FLAGS_PREVIOUS_PD_CONN | \
-					   PD_FLAGS_CHECK_PR_ROLE | \
-					   PD_FLAGS_CHECK_DR_ROLE | \
-					   PD_FLAGS_PARTNER_UNCONSTR | \
-					   PD_FLAGS_VCONN_ON | \
-					   PD_FLAGS_TRY_SRC | \
-					   PD_FLAGS_PARTNER_USB_COMM | \
-					   PD_FLAGS_UPDATE_SRC_CAPS | \
-					   PD_FLAGS_TS_DTS_PARTNER | \
-					   PD_FLAGS_SNK_WAITING_BATT | \
-					   PD_FLAGS_CHECK_VCONN_STATE)
+#define PD_FLAGS_RESET_ON_DISCONNECT_MASK                                   \
+	(PD_FLAGS_PARTNER_DR_POWER | PD_FLAGS_PARTNER_DR_DATA |             \
+	 PD_FLAGS_CHECK_IDENTITY | PD_FLAGS_SNK_CAP_RECVD |                 \
+	 PD_FLAGS_TCPC_DRP_TOGGLE | PD_FLAGS_EXPLICIT_CONTRACT |            \
+	 PD_FLAGS_PREVIOUS_PD_CONN | PD_FLAGS_CHECK_PR_ROLE |               \
+	 PD_FLAGS_CHECK_DR_ROLE | PD_FLAGS_PARTNER_UNCONSTR |               \
+	 PD_FLAGS_VCONN_ON | PD_FLAGS_TRY_SRC | PD_FLAGS_PARTNER_USB_COMM | \
+	 PD_FLAGS_UPDATE_SRC_CAPS | PD_FLAGS_TS_DTS_PARTNER |               \
+	 PD_FLAGS_SNK_WAITING_BATT | PD_FLAGS_CHECK_VCONN_STATE)
 
 #ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 static int tcpc_prints(const char *string, int port)
 {
@@ -105,11 +98,11 @@ static const int debug_level;
 #define DUAL_ROLE_IF_ELSE(port, sink_clause, src_clause) (src_clause)
 #endif
 
-#define READY_RETURN_STATE(port) DUAL_ROLE_IF_ELSE(port, PD_STATE_SNK_READY, \
-							 PD_STATE_SRC_READY)
+#define READY_RETURN_STATE(port) \
+	DUAL_ROLE_IF_ELSE(port, PD_STATE_SNK_READY, PD_STATE_SRC_READY)
 
 /* Type C supply voltage (mV) */
-#define TYPE_C_VOLTAGE	5000 /* mV */
+#define TYPE_C_VOLTAGE 5000 /* mV */
 
 /* PD counter definitions */
 #define PD_MESSAGE_ID_COUNT 7
@@ -153,8 +146,9 @@ enum vdm_states {
 #ifdef CONFIG_USB_PD_DUAL_ROLE
 /* Port dual-role state */
 enum pd_dual_role_states drp_state[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[0 ... (CONFIG_USB_PD_PORT_MAX_COUNT - 1)] =
-		CONFIG_USB_PD_INITIAL_DRP_STATE};
+	[0 ...(CONFIG_USB_PD_PORT_MAX_COUNT - 1)] =
+		CONFIG_USB_PD_INITIAL_DRP_STATE
+};
 
 /* Enable variable for Try.SRC states */
 static bool pd_try_src_enable;
@@ -183,8 +177,7 @@ static bool pd_try_src_enable;
  *  Rev 1 (VDO 1.0) - return VDM_VER10
  *  Rev 2 (VDO 2.0) - return VDM_VER20
  */
-static const uint8_t vdo_ver[] = {
-	VDM_VER10, VDM_VER10, VDM_VER20};
+static const uint8_t vdo_ver[] = { VDM_VER10, VDM_VER10, VDM_VER20 };
 #define VDO_VER(v) vdo_ver[v]
 #else
 #define VDO_VER(v) VDM_VER10
@@ -277,7 +270,7 @@ static struct pd_protocol {
 
 	/* Attached ChromeOS device id, RW hash, and current RO / RW image */
 	uint16_t dev_id;
-	uint32_t dev_rw_hash[PD_RW_HASH_SIZE/4];
+	uint32_t dev_rw_hash[PD_RW_HASH_SIZE / 4];
 	enum ec_image current_image;
 #ifdef CONFIG_USB_PD_REV30
 	/* protocol revision */
@@ -298,24 +291,46 @@ static struct pd_protocol {
 } pd[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 #ifdef CONFIG_USB_PD_TCPMV1_DEBUG
-static const char * const pd_state_names[] = {
-	"DISABLED", "SUSPENDED",
-	"SNK_DISCONNECTED", "SNK_DISCONNECTED_DEBOUNCE",
+static const char *const pd_state_names[] = {
+	"DISABLED",
+	"SUSPENDED",
+	"SNK_DISCONNECTED",
+	"SNK_DISCONNECTED_DEBOUNCE",
 	"SNK_HARD_RESET_RECOVER",
-	"SNK_DISCOVERY", "SNK_REQUESTED", "SNK_TRANSITION", "SNK_READY",
-	"SNK_SWAP_INIT", "SNK_SWAP_SNK_DISABLE",
-	"SNK_SWAP_SRC_DISABLE", "SNK_SWAP_STANDBY", "SNK_SWAP_COMPLETE",
-	"SRC_DISCONNECTED", "SRC_DISCONNECTED_DEBOUNCE",
-	"SRC_HARD_RESET_RECOVER", "SRC_STARTUP",
-	"SRC_DISCOVERY", "SRC_NEGOCIATE", "SRC_ACCEPTED", "SRC_POWERED",
-	"SRC_TRANSITION", "SRC_READY", "SRC_GET_SNK_CAP", "DR_SWAP",
-	"SRC_SWAP_INIT", "SRC_SWAP_SNK_DISABLE", "SRC_SWAP_SRC_DISABLE",
+	"SNK_DISCOVERY",
+	"SNK_REQUESTED",
+	"SNK_TRANSITION",
+	"SNK_READY",
+	"SNK_SWAP_INIT",
+	"SNK_SWAP_SNK_DISABLE",
+	"SNK_SWAP_SRC_DISABLE",
+	"SNK_SWAP_STANDBY",
+	"SNK_SWAP_COMPLETE",
+	"SRC_DISCONNECTED",
+	"SRC_DISCONNECTED_DEBOUNCE",
+	"SRC_HARD_RESET_RECOVER",
+	"SRC_STARTUP",
+	"SRC_DISCOVERY",
+	"SRC_NEGOCIATE",
+	"SRC_ACCEPTED",
+	"SRC_POWERED",
+	"SRC_TRANSITION",
+	"SRC_READY",
+	"SRC_GET_SNK_CAP",
+	"DR_SWAP",
+	"SRC_SWAP_INIT",
+	"SRC_SWAP_SNK_DISABLE",
+	"SRC_SWAP_SRC_DISABLE",
 	"SRC_SWAP_STANDBY",
-	"VCONN_SWAP_SEND", "VCONN_SWAP_INIT", "VCONN_SWAP_READY",
-	"SOFT_RESET", "HARD_RESET_SEND", "HARD_RESET_EXECUTE", "BIST_RX",
+	"VCONN_SWAP_SEND",
+	"VCONN_SWAP_INIT",
+	"VCONN_SWAP_READY",
+	"SOFT_RESET",
+	"HARD_RESET_SEND",
+	"HARD_RESET_EXECUTE",
+	"BIST_RX",
 	"BIST_TX",
 	"DRP_AUTO_TOGGLE",
-	"ENTER_USB",
 };
 BUILD_ASSERT(ARRAY_SIZE(pd_state_names) == PD_STATE_COUNT);
 #endif
@@ -336,11 +351,10 @@ bool pd_alt_mode_capable(int port)
 	 * the port is not suspended.
 	 */
 	return pd_comm_is_enabled(port) &&
-		!(pd[port].task_state == PD_STATE_SUSPENDED);
+	       !(pd[port].task_state == PD_STATE_SUSPENDED);
 }
 
-static inline void set_state_timeout(int port,
-				     uint64_t timeout,
+static inline void set_state_timeout(int port, uint64_t timeout,
 				     enum pd_states timeout_state)
 {
 	pd[port].timeout = timeout;
@@ -353,9 +367,6 @@ int pd_get_rev(int port, enum tcpci_msg_type type)
 	/* TCPMv1 Only stores PD revision for SOP and SOP' types */
 	ASSERT(type < NUM_SOP_STAR_TYPES - 1);
 
-	if (type == TCPCI_MSG_SOP_PRIME)
-		return get_usb_pd_cable_revision(port);
-
 	return pd[port].rev;
 #else
 	return PD_REV20;
@@ -365,9 +376,6 @@ int pd_get_rev(int port, enum tcpci_msg_type type)
 int pd_get_vdo_ver(int port, enum tcpci_msg_type type)
 {
 #ifdef CONFIG_USB_PD_REV30
-	if (type == TCPCI_MSG_SOP_PRIME)
-		return vdo_ver[get_usb_pd_cable_revision(port)];
-
 	return vdo_ver[pd[port].rev];
 #else
 	return VDM_VER10;
@@ -385,13 +393,16 @@ int pd_is_connected(int port)
 		return 0;
 #endif
 
-	return DUAL_ROLE_IF_ELSE(port,
+	return DUAL_ROLE_IF_ELSE(
+		port,
 		/* sink */
 		pd[port].task_state != PD_STATE_SNK_DISCONNECTED &&
-		pd[port].task_state != PD_STATE_SNK_DISCONNECTED_DEBOUNCE,
+			pd[port].task_state !=
+				PD_STATE_SNK_DISCONNECTED_DEBOUNCE,
 		/* source */
 		pd[port].task_state != PD_STATE_SRC_DISCONNECTED &&
-		pd[port].task_state != PD_STATE_SRC_DISCONNECTED_DEBOUNCE);
+			pd[port].task_state !=
+				PD_STATE_SRC_DISCONNECTED_DEBOUNCE);
 }
 
 /* Return true if partner port is known to be PD capable. */
@@ -425,7 +436,6 @@ void pd_vbus_low(int port)
 }
 #endif
 
-
 #ifdef CONFIG_USBC_VCONN
 static void set_vconn(int port, int enable)
 {
@@ -485,12 +495,12 @@ static void handle_device_access(int port)
 	pd[port].low_power_time = get_time().val + PD_LPM_DEBOUNCE_US;
 	if (pd[port].flags & PD_FLAGS_LPM_ENGAGED) {
 		tcpc_prints("Exit Low Power Mode", port);
-		pd[port].flags &= ~(PD_FLAGS_LPM_ENGAGED |
-				    PD_FLAGS_LPM_REQUESTED);
+		pd[port].flags &=
+			~(PD_FLAGS_LPM_ENGAGED | PD_FLAGS_LPM_REQUESTED);
 		pd[port].flags |= PD_FLAGS_LPM_EXIT;
 
-		pd[port].low_power_exit_time = get_time().val
-			+ PD_LPM_EXIT_DEBOUNCE_US;
+		pd[port].low_power_exit_time =
+			get_time().val + PD_LPM_EXIT_DEBOUNCE_US;
 		/*
 		 * Wake to ensure we make another pass through the main task
 		 * loop after clearing the flags.
@@ -675,28 +685,18 @@ static bool consume_sop_repeat_message(int port, uint8_t msg_id)
  * @param port USB PD TCPC port number
  * @param msg_header Message Header containing the RX message ID
  * @return True if the received message is a duplicate one, False otherwise.
- *
- * From USB PD version 1.3 section 6.7.1, the port which communicates
- * using SOP* Packets Shall maintain copies of the last MessageID for
- * each type of SOP* it uses.
  */
 static bool consume_repeat_message(int port, uint32_t msg_header)
 {
 	uint8_t msg_id = PD_HEADER_ID(msg_header);
-	enum tcpci_msg_type sop = PD_HEADER_GET_SOP(msg_header);
 
 	/* If repeat message ignore, except softreset control request. */
 	if (PD_HEADER_TYPE(msg_header) == PD_CTRL_SOFT_RESET &&
 	    PD_HEADER_CNT(msg_header) == 0) {
 		return false;
-	} else if (sop == TCPCI_MSG_SOP_PRIME) {
-		return consume_sop_prime_repeat_msg(port, msg_id);
-	} else if (sop == TCPCI_MSG_SOP_PRIME_PRIME) {
-		return consume_sop_prime_prime_repeat_msg(port, msg_id);
 	} else {
 		return consume_sop_repeat_message(port, msg_id);
 	}
-
 }
 
 /**
@@ -791,15 +791,13 @@ static inline void set_state(int port, enum pd_states next_state)
 		if (last_state != PD_STATE_SNK_DISCONNECTED_DEBOUNCE &&
 		    last_state != PD_STATE_SRC_DISCONNECTED_DEBOUNCE) {
 			pd[port].flags &= ~PD_FLAGS_RESET_ON_DISCONNECT_MASK;
-			reset_pd_cable(port);
 		}
 
 		/* Clear the input current limit */
 		pd_set_input_current_limit(port, 0, 0);
 #ifdef CONFIG_CHARGE_MANAGER
 		typec_set_input_current_limit(port, 0, 0);
-		charge_manager_set_ceil(port,
-					CEIL_REQUESTOR_PD,
+		charge_manager_set_ceil(port, CEIL_REQUESTOR_PD,
 					CHARGE_CEIL_NONE);
 #endif
 #ifdef CONFIG_BC12_DETECT_DATA_ROLE_TRIGGER
@@ -868,7 +866,7 @@ static inline void set_state(int port, enum pd_states next_state)
 	/* Upon entering SRC_READY, it is safe for the sink to transmit */
 	if (next_state == PD_STATE_SRC_READY) {
 		if (pd[port].rev == PD_REV30 &&
-			pd[port].flags & PD_FLAGS_EXPLICIT_CONTRACT)
+		    pd[port].flags & PD_FLAGS_EXPLICIT_CONTRACT)
 			sink_can_xmit(port, SINK_TX_OK);
 	}
 #endif
@@ -888,7 +886,7 @@ static inline void set_state(int port, enum pd_states next_state)
 #ifdef CONFIG_USB_PD_TCPMV1_DEBUG
 	if (debug_level > 0)
 		CPRINTF("C%d st%d %s\n", port, next_state,
-					 pd_state_names[next_state]);
+			pd_state_names[next_state]);
 	else
 #endif
 		CPRINTF("C%d st%d\n", port, next_state);
@@ -909,8 +907,8 @@ void pd_transmit_complete(int port, int status)
 	task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_TX);
 }
 
-static int pd_transmit(int port, enum tcpci_msg_type type,
-		       uint16_t header, const uint32_t *data, enum ams_seq ams)
+static int pd_transmit(int port, enum tcpci_msg_type type, uint16_t header,
+		       const uint32_t *data, enum ams_seq ams)
 {
 	int evt;
 	int res;
@@ -922,9 +920,9 @@ static int pd_transmit(int port, enum tcpci_msg_type type,
 	if (!pd_comm_is_enabled(port))
 		return -1;
 
-	 /* Don't try to transmit anything until we have processed
-	  * all RX messages.
-	  */
+	/* Don't try to transmit anything until we have processed
+	 * all RX messages.
+	 */
 	if (tcpm_has_pending_message(port))
 		return -1;
 
@@ -951,7 +949,7 @@ static int pd_transmit(int port, enum tcpci_msg_type type,
 	 * Note: a Sink can still send Hard Reset signaling at any time.
 	 */
 	if ((pd[port].rev == PD_REV30) && ams == AMS_START &&
-		(pd[port].flags & PD_FLAGS_EXPLICIT_CONTRACT)) {
+	    (pd[port].flags & PD_FLAGS_EXPLICIT_CONTRACT)) {
 		if (pd[port].power_role == PD_ROLE_SOURCE) {
 			/*
 			 * Inform Sink that it can't transmit. If a sink
@@ -967,7 +965,7 @@ static int pd_transmit(int port, enum tcpci_msg_type type,
 
 			tcpm_get_cc(port, &cc1, &cc2);
 			if (cc1 == TYPEC_CC_VOLT_RP_1_5 ||
-				cc2 == TYPEC_CC_VOLT_RP_1_5) {
+			    cc2 == TYPEC_CC_VOLT_RP_1_5) {
 				/* Sink can't transmit now. */
 				/* Return failure, pd_task can retry later */
 				return -1;
@@ -1004,15 +1002,15 @@ static int send_control(int port, int type)
 {
 	int bit_len;
 	uint16_t header = PD_HEADER(type, pd[port].power_role,
-				pd[port].data_role, pd[port].msg_id, 0,
-				pd_get_rev(port, TCPCI_MSG_SOP), 0);
+				    pd[port].data_role, pd[port].msg_id, 0,
+				    pd_get_rev(port, TCPCI_MSG_SOP), 0);
 	/*
 	 * For PD 3.0, collision avoidance logic needs to know if this message
 	 * will begin a new Atomic Message Sequence (AMS)
 	 */
-	enum ams_seq ams = ((1 << type) & PD_CTRL_AMS_START_MASK)
-			    ? AMS_START : AMS_RESPONSE;
-
+	enum ams_seq ams = ((1 << type) & PD_CTRL_AMS_START_MASK) ?
+				   AMS_START :
+				   AMS_RESPONSE;
 
 	bit_len = pd_transmit(port, TCPCI_MSG_SOP, header, NULL, ams);
 	if (debug_level >= 2)
@@ -1030,7 +1028,7 @@ static int send_source_cap(int port, enum ams_seq ams)
 {
 	int bit_len;
 #if defined(CONFIG_USB_PD_DYNAMIC_SRC_CAP) || \
-		defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT)
+	defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT)
 	const uint32_t *src_pdo;
 	const int src_pdo_cnt = charge_manager_get_source_pdo(&src_pdo, port);
 #else
@@ -1042,12 +1040,13 @@ static int send_source_cap(int port, enum ams_seq ams)
 	if (src_pdo_cnt == 0)
 		/* No source capabilities defined, sink only */
 		header = PD_HEADER(PD_CTRL_REJECT, pd[port].power_role,
-			pd[port].data_role, pd[port].msg_id, 0,
-			pd_get_rev(port, TCPCI_MSG_SOP), 0);
+				   pd[port].data_role, pd[port].msg_id, 0,
+				   pd_get_rev(port, TCPCI_MSG_SOP), 0);
 	else
 		header = PD_HEADER(PD_DATA_SOURCE_CAP, pd[port].power_role,
-			pd[port].data_role, pd[port].msg_id, src_pdo_cnt,
-			pd_get_rev(port, TCPCI_MSG_SOP), 0);
+				   pd[port].data_role, pd[port].msg_id,
+				   src_pdo_cnt, pd_get_rev(port, TCPCI_MSG_SOP),
+				   0);
 
 	bit_len = pd_transmit(port, TCPCI_MSG_SOP, header, src_pdo, ams);
 	if (debug_level >= 2)
@@ -1060,21 +1059,19 @@ static int send_source_cap(int port, enum ams_seq ams)
 static int send_battery_cap(int port, uint32_t *payload)
 {
 	int bit_len;
-	uint16_t msg[6] = {0, 0, 0, 0, 0, 0};
-	uint16_t header = PD_HEADER(PD_EXT_BATTERY_CAP,
-				    pd[port].power_role,
-				    pd[port].data_role,
-				    pd[port].msg_id,
+	uint16_t msg[6] = { 0, 0, 0, 0, 0, 0 };
+	uint16_t header = PD_HEADER(PD_EXT_BATTERY_CAP, pd[port].power_role,
+				    pd[port].data_role, pd[port].msg_id,
 				    3, /* Number of Data Objects */
-				    pd[port].rev,
-				    1  /* This is an exteded message */
-				   );
+				    pd[port].rev, 1 /* This is an exteded
+						       message */
+	);
 
 	/* Set extended header */
 	msg[0] = PD_EXT_HEADER(0, /* Chunk Number */
 			       0, /* Request Chunk */
-			       9  /* Data Size in bytes */
-			      );
+			       9 /* Data Size in bytes */
+	);
 	/* Set VID */
 	msg[1] = USB_VID_GOOGLE;
 
@@ -1121,7 +1118,7 @@ static int send_battery_cap(int port, uint32_t *payload)
 					 * 10th of a Wh = Wh * 10
 					 */
 					msg[3] = DIV_ROUND_NEAREST((c * v),
-								100000);
+								   100000);
 				}
 
 				if (battery_full_charge_capacity(&c) == 0) {
@@ -1130,7 +1127,7 @@ static int send_battery_cap(int port, uint32_t *payload)
 					 * 10th of a Wh = Wh * 10
 					 */
 					msg[4] = DIV_ROUND_NEAREST((c * v),
-								100000);
+								   100000);
 				}
 			}
 		}
@@ -1143,18 +1140,16 @@ static int send_battery_cap(int port, uint32_t *payload)
 	return bit_len;
 }
 
-static int send_battery_status(int port,  uint32_t *payload)
+static int send_battery_status(int port, uint32_t *payload)
 {
 	int bit_len;
 	uint32_t msg = 0;
-	uint16_t header = PD_HEADER(PD_DATA_BATTERY_STATUS,
-				    pd[port].power_role,
-				    pd[port].data_role,
-				    pd[port].msg_id,
+	uint16_t header = PD_HEADER(PD_DATA_BATTERY_STATUS, pd[port].power_role,
+				    pd[port].data_role, pd[port].msg_id,
 				    1, /* Number of Data Objects */
-				    pd[port].rev,
-				    0 /* This is NOT an extended message */
-				  );
+				    pd[port].rev, 0 /* This is NOT an extended
+						       message */
+	);
 
 	if (battery_is_present()) {
 		/*
@@ -1169,15 +1164,15 @@ static int send_battery_status(int port,  uint32_t *payload)
 			uint32_t c;
 
 			if (battery_design_voltage(&v) != 0 ||
-					battery_remaining_capacity(&c) != 0) {
+			    battery_remaining_capacity(&c) != 0) {
 				msg |= BSDO_CAP(BSDO_CAP_UNKNOWN);
 			} else {
 				/*
 				 * Wh = (c * v) / 1000000
 				 * 10th of a Wh = Wh * 10
 				 */
-				msg |= BSDO_CAP(DIV_ROUND_NEAREST((c * v),
-								100000));
+				msg |= BSDO_CAP(
+					DIV_ROUND_NEAREST((c * v), 100000));
 			}
 
 			/* Battery is present */
@@ -1217,8 +1212,9 @@ static void send_sink_cap(int port)
 {
 	int bit_len;
 	uint16_t header = PD_HEADER(PD_DATA_SINK_CAP, pd[port].power_role,
-			pd[port].data_role, pd[port].msg_id, pd_snk_pdo_cnt,
-			pd_get_rev(port, TCPCI_MSG_SOP), 0);
+				    pd[port].data_role, pd[port].msg_id,
+				    pd_snk_pdo_cnt,
+				    pd_get_rev(port, TCPCI_MSG_SOP), 0);
 
 	bit_len = pd_transmit(port, TCPCI_MSG_SOP, header, pd_snk_pdo,
 			      AMS_RESPONSE);
@@ -1230,8 +1226,8 @@ static int send_request(int port, uint32_t rdo)
 {
 	int bit_len;
 	uint16_t header = PD_HEADER(PD_DATA_REQUEST, pd[port].power_role,
-			pd[port].data_role, pd[port].msg_id, 1,
-			pd_get_rev(port, TCPCI_MSG_SOP), 0);
+				    pd[port].data_role, pd[port].msg_id, 1,
+				    pd_get_rev(port, TCPCI_MSG_SOP), 0);
 
 	/* Note: ams will need to be AMS_START if used for PPS keep alive */
 	bit_len = pd_transmit(port, TCPCI_MSG_SOP, header, &rdo, AMS_RESPONSE);
@@ -1250,8 +1246,8 @@ static int send_bist_cmd(int port)
 	uint32_t bdo = BDO(BDO_MODE_CARRIER2, 0);
 	int bit_len;
 	uint16_t header = PD_HEADER(PD_DATA_BIST, pd[port].power_role,
-			pd[port].data_role, pd[port].msg_id, 1,
-			pd_get_rev(port, TCPCI_MSG_SOP), 0);
+				    pd[port].data_role, pd[port].msg_id, 1,
+				    pd_get_rev(port, TCPCI_MSG_SOP), 0);
 
 	bit_len = pd_transmit(port, TCPCI_MSG_SOP, header, &bdo, AMS_START);
 	CPRINTF("C%d BIST>%d\n", port, bit_len);
@@ -1261,19 +1257,18 @@ static int send_bist_cmd(int port)
 #endif
 
 static void queue_vdm(int port, uint32_t *header, const uint32_t *data,
-			     int data_cnt, enum tcpci_msg_type type)
+		      int data_cnt, enum tcpci_msg_type type)
 {
 	pd[port].vdo_count = data_cnt + 1;
 	pd[port].vdo_data[0] = header[0];
 	pd[port].xmit_type = type;
-	memcpy(&pd[port].vdo_data[1], data,
-		sizeof(uint32_t) * data_cnt);
+	memcpy(&pd[port].vdo_data[1], data, sizeof(uint32_t) * data_cnt);
 	/* Set ready, pd task will actually send */
 	pd[port].vdm_state = VDM_STATE_READY;
 }
 
 static void handle_vdm_request(int port, int cnt, uint32_t *payload,
-				uint32_t head)
+			       uint32_t head)
 {
 	int rlen = 0;
 	uint32_t *rdata;
@@ -1282,11 +1277,11 @@ static void handle_vdm_request(int port, int cnt, uint32_t *payload,
 	if (pd[port].vdm_state == VDM_STATE_BUSY) {
 		/* If UFP responded busy retry after timeout */
 		if (PD_VDO_CMDT(payload[0]) == CMDT_RSP_BUSY) {
-			pd[port].vdm_timeout.val = get_time().val +
-				PD_T_VDM_BUSY;
+			pd[port].vdm_timeout.val =
+				get_time().val + PD_T_VDM_BUSY;
 			pd[port].vdm_state = VDM_STATE_WAIT_RSP_BUSY;
 			pd[port].vdo_retry = (payload[0] & ~VDO_CMDT_MASK) |
-				CMDT_INIT;
+					     CMDT_INIT;
 			return;
 		} else {
 			pd[port].vdm_state = VDM_STATE_DONE;
@@ -1310,8 +1305,8 @@ static void handle_vdm_request(int port, int cnt, uint32_t *payload,
 	}
 
 	if (debug_level >= 2)
-		CPRINTF("C%d Unhandled VDM VID %04x CMD %04x\n",
-			port, PD_VDO_VID(payload[0]), payload[0] & 0xFFFF);
+		CPRINTF("C%d Unhandled VDM VID %04x CMD %04x\n", port,
+			PD_VDO_VID(payload[0]), payload[0] & 0xFFFF);
 }
 
 bool pd_is_disconnected(int port)
@@ -1401,8 +1396,7 @@ void pd_execute_hard_reset(int port)
 		/* Clear the input current limit */
 		pd_set_input_current_limit(port, 0, 0);
 #ifdef CONFIG_CHARGE_MANAGER
-		charge_manager_set_ceil(port,
-					CEIL_REQUESTOR_PD,
+		charge_manager_set_ceil(port, CEIL_REQUESTOR_PD,
 					CHARGE_CEIL_NONE);
 #endif /* CONFIG_CHARGE_MANAGER */
 
@@ -1442,7 +1436,7 @@ static void execute_soft_reset(int port)
 {
 	invalidate_last_message_id(port);
 	set_state(port, DUAL_ROLE_IF_ELSE(port, PD_STATE_SNK_DISCOVERY,
-						PD_STATE_SRC_DISCOVERY));
+					  PD_STATE_SRC_DISCOVERY));
 	CPRINTF("C%d Soft Rst\n", port);
 }
 
@@ -1484,8 +1478,8 @@ static int pd_send_request_msg(int port, int always_send_request)
 #endif
 	}
 
-	CPRINTF("C%d Req [%d] %dmV %dmA", port, RDO_POS(rdo),
-		supply_voltage, curr_limit);
+	CPRINTF("C%d Req [%d] %dmV %dmA", port, RDO_POS(rdo), supply_voltage,
+		curr_limit);
 	if (rdo & RDO_CAP_MISMATCH)
 		CPRINTF(" Mismatch");
 	CPRINTF("\n");
@@ -1543,8 +1537,7 @@ static void pd_update_pdo_flags(int port, int pdo_cnt, uint32_t *pdos)
 		 * Get max power that the partner offers (not necessarily what
 		 * this board will request)
 		 */
-		pd_find_pdo_index(pdo_cnt, pdos, PD_REV3_MAX_VOLTAGE,
-				  &max_pdo);
+		pd_find_pdo_index(pdo_cnt, pdos, PD_REV3_MAX_VOLTAGE, &max_pdo);
 		pd_extract_pdo_power(max_pdo, &max_ma, &max_mv, &unused);
 		max_mw = max_ma * max_mv / 1000;
 
@@ -1557,8 +1550,7 @@ static void pd_update_pdo_flags(int port, int pdo_cnt, uint32_t *pdos)
 	}
 }
 
-static void handle_data_request(int port, uint32_t head,
-		uint32_t *payload)
+static void handle_data_request(int port, uint32_t head, uint32_t *payload)
 {
 	int type = PD_HEADER_TYPE(head);
 	int cnt = PD_HEADER_CNT(head);
@@ -1566,14 +1558,12 @@ static void handle_data_request(int port, uint32_t head,
 	switch (type) {
 #ifdef CONFIG_USB_PD_DUAL_ROLE
 	case PD_DATA_SOURCE_CAP:
-		if ((pd[port].task_state == PD_STATE_SNK_DISCOVERY)
-			|| (pd[port].task_state == PD_STATE_SNK_TRANSITION)
-			|| (pd[port].task_state == PD_STATE_SNK_REQUESTED)
-			|| ((get_usb_pd_vbus_detect() ==
-					USB_PD_VBUS_DETECT_NONE)
-				&& (pd[port].task_state ==
-					PD_STATE_SNK_HARD_RESET_RECOVER))
-			|| (pd[port].task_state == PD_STATE_SNK_READY)) {
+		if ((pd[port].task_state == PD_STATE_SNK_DISCOVERY) ||
+		    (pd[port].task_state == PD_STATE_SNK_TRANSITION) ||
+		    (pd[port].task_state == PD_STATE_SNK_REQUESTED) ||
+		    ((get_usb_pd_vbus_detect() == USB_PD_VBUS_DETECT_NONE) &&
+		     (pd[port].task_state == PD_STATE_SNK_HARD_RESET_RECOVER)) ||
+		    (pd[port].task_state == PD_STATE_SNK_READY)) {
 #ifdef CONFIG_USB_PD_REV30
 			/*
 			 * Only adjust sink rev if source rev is higher.
@@ -1630,18 +1620,20 @@ static void handle_data_request(int port, uint32_t head,
 		break;
 	case PD_DATA_BIST:
 		/* If not in READY state, then don't start BIST */
-		if (DUAL_ROLE_IF_ELSE(port,
-				pd[port].task_state == PD_STATE_SNK_READY,
-				pd[port].task_state == PD_STATE_SRC_READY)) {
+		if (DUAL_ROLE_IF_ELSE(
+			    port, pd[port].task_state == PD_STATE_SNK_READY,
+			    pd[port].task_state == PD_STATE_SRC_READY)) {
 			/* currently only support sending bist carrier mode 2 */
 			if ((payload[0] >> 28) == 5) {
 				/* bist data object mode is 2 */
 				pd_transmit(port, TCPCI_MSG_TX_BIST_MODE_2, 0,
 					    NULL, AMS_RESPONSE);
 				/* Set to appropriate port disconnected state */
-				set_state(port, DUAL_ROLE_IF_ELSE(port,
-						PD_STATE_SNK_DISCONNECTED,
-						PD_STATE_SRC_DISCONNECTED));
+				set_state(port,
+					  DUAL_ROLE_IF_ELSE(
+						  port,
+						  PD_STATE_SNK_DISCONNECTED,
+						  PD_STATE_SRC_DISCONNECTED));
 			}
 		}
 		break;
@@ -1655,12 +1647,6 @@ static void handle_data_request(int port, uint32_t head,
 #ifdef CONFIG_USB_PD_REV30
 	case PD_DATA_BATTERY_STATUS:
 		break;
-	/* TODO : Add case PD_DATA_RESET for exiting USB4 */
-
-	/*
-	 * TODO : Add case PD_DATA_ENTER_USB to accept or reject
-	 * Enter_USB request from port partner.
-	 */
 #endif
 	case PD_DATA_VENDOR_DEF:
 		handle_vdm_request(port, cnt, payload, head);
@@ -1705,9 +1691,8 @@ void pd_try_vconn_src(int port)
 
 void pd_request_data_swap(int port)
 {
-	if (DUAL_ROLE_IF_ELSE(port,
-				pd[port].task_state == PD_STATE_SNK_READY,
-				pd[port].task_state == PD_STATE_SRC_READY))
+	if (DUAL_ROLE_IF_ELSE(port, pd[port].task_state == PD_STATE_SNK_READY,
+			      pd[port].task_state == PD_STATE_SRC_READY))
 		set_state(port, PD_STATE_DR_SWAP);
 	task_wake(PD_PORT_TO_TASK_ID(port));
 }
@@ -1726,8 +1711,7 @@ static void pd_dr_swap(int port)
 	pd[port].flags |= PD_FLAGS_CHECK_IDENTITY;
 }
 
-static void handle_ctrl_request(int port, uint32_t head,
-		uint32_t *payload)
+static void handle_ctrl_request(int port, uint32_t head, uint32_t *payload)
 {
 	int type = PD_HEADER_TYPE(head);
 	int res;
@@ -1768,7 +1752,7 @@ static void handle_ctrl_request(int port, uint32_t head,
 			 * later time.
 			 */
 			pd_snk_give_back(port, &pd[port].curr_limit,
-				&pd[port].supply_voltage);
+					 &pd[port].supply_voltage);
 			set_state(port, PD_STATE_SNK_TRANSITION);
 		}
 #endif
@@ -1813,37 +1797,21 @@ static void handle_ctrl_request(int port, uint32_t head,
 			 */
 			if (pd[port].task_state == PD_STATE_SNK_TRANSITION)
 				pd[port].ready_state_holdoff_timer =
-					get_time().val + SNK_READY_HOLD_OFF_US
-					+ (get_time().le.lo & 0xf) * 12 * MSEC;
+					get_time().val + SNK_READY_HOLD_OFF_US +
+					(get_time().le.lo & 0xf) * 12 * MSEC;
 
 			set_state(port, PD_STATE_SNK_READY);
 			pd_set_input_current_limit(port, pd[port].curr_limit,
 						   pd[port].supply_voltage);
 #ifdef CONFIG_CHARGE_MANAGER
 			/* Set ceiling based on what's negotiated */
-			charge_manager_set_ceil(port,
-						CEIL_REQUESTOR_PD,
+			charge_manager_set_ceil(port, CEIL_REQUESTOR_PD,
 						pd[port].curr_limit);
 #endif
 		}
 		break;
 #endif
 	case PD_CTRL_REJECT:
-		if (pd[port].task_state == PD_STATE_ENTER_USB) {
-			if (!IS_ENABLED(CONFIG_USBC_SS_MUX))
-				break;
-
-			/*
-			 * Since Enter USB sets the mux state to SAFE mode,
-			 * resetting the mux state back to USB mode on
-			 * recieveing a NACK.
-			 */
-			usb_mux_set(port, USB_PD_MUX_USB_ENABLED,
-				USB_SWITCH_CONNECT, pd[port].polarity);
-
-			set_state(port, READY_RETURN_STATE(port));
-			break;
-		}
 	case PD_CTRL_WAIT:
 		if (pd[port].task_state == PD_STATE_DR_SWAP) {
 			if (type == PD_CTRL_WAIT) /* try again ... */
@@ -1898,28 +1866,15 @@ static void handle_ctrl_request(int port, uint32_t head,
 				const int in_contract =
 					pd[port].flags &
 					PD_FLAGS_EXPLICIT_CONTRACT;
-				set_state(port,
-					  in_contract ? PD_STATE_SNK_READY
-						      : PD_STATE_SNK_DISCOVERY);
+				set_state(port, in_contract ?
+							PD_STATE_SNK_READY :
+							PD_STATE_SNK_DISCOVERY);
 			}
 		}
 #endif
 		break;
 	case PD_CTRL_ACCEPT:
-		if (pd[port].task_state == PD_STATE_ENTER_USB) {
-			if (!IS_ENABLED(CONFIG_USBC_SS_MUX))
-				break;
-
-			/* Connect the SBU and USB lines to the connector */
-			if (IS_ENABLED(CONFIG_USBC_PPC_SBU))
-				ppc_set_sbu(port, 1);
-
-			/* Set usb mux to USB4 mode */
-			usb_mux_set(port, USB_PD_MUX_USB4_ENABLED,
-				USB_SWITCH_CONNECT, pd[port].polarity);
-
-			set_state(port, READY_RETURN_STATE(port));
-		} else if (pd[port].task_state == PD_STATE_SOFT_RESET) {
+		if (pd[port].task_state == PD_STATE_SOFT_RESET) {
 			/*
 			 * For the case that we sent soft reset in SNK_DISCOVERY
 			 * on startup due to VBUS never low, clear the flag.
@@ -1939,23 +1894,20 @@ static void handle_ctrl_request(int port, uint32_t head,
 		} else if (pd[port].task_state == PD_STATE_SRC_SWAP_INIT) {
 			/* explicit contract goes away for power swap */
 			pd[port].flags &= ~PD_FLAGS_EXPLICIT_CONTRACT;
-			pd_update_saved_port_flags(port,
-						   PD_BBRMFLG_EXPLICIT_CONTRACT,
-						   0);
+			pd_update_saved_port_flags(
+				port, PD_BBRMFLG_EXPLICIT_CONTRACT, 0);
 			set_state(port, PD_STATE_SRC_SWAP_SNK_DISABLE);
 		} else if (pd[port].task_state == PD_STATE_SNK_SWAP_INIT) {
 			/* explicit contract goes away for power swap */
 			pd[port].flags &= ~PD_FLAGS_EXPLICIT_CONTRACT;
-			pd_update_saved_port_flags(port,
-						   PD_BBRMFLG_EXPLICIT_CONTRACT,
-						   0);
+			pd_update_saved_port_flags(
+				port, PD_BBRMFLG_EXPLICIT_CONTRACT, 0);
 			set_state(port, PD_STATE_SNK_SWAP_SNK_DISABLE);
 		} else if (pd[port].task_state == PD_STATE_SNK_REQUESTED) {
 			/* explicit contract is now in place */
 			pd[port].flags |= PD_FLAGS_EXPLICIT_CONTRACT;
-			pd_update_saved_port_flags(port,
-						   PD_BBRMFLG_EXPLICIT_CONTRACT,
-						   1);
+			pd_update_saved_port_flags(
+				port, PD_BBRMFLG_EXPLICIT_CONTRACT, 1);
 			set_state(port, PD_STATE_SNK_TRANSITION);
 #endif
 		}
@@ -1976,9 +1928,9 @@ static void handle_ctrl_request(int port, uint32_t head,
 			 */
 			pd[port].flags &= ~PD_FLAGS_CHECK_PR_ROLE;
 			set_state(port,
-				  DUAL_ROLE_IF_ELSE(port,
-					PD_STATE_SNK_SWAP_SNK_DISABLE,
-					PD_STATE_SRC_SWAP_SNK_DISABLE));
+				  DUAL_ROLE_IF_ELSE(
+					  port, PD_STATE_SNK_SWAP_SNK_DISABLE,
+					  PD_STATE_SRC_SWAP_SNK_DISABLE));
 		} else {
 			send_control(port, PD_CTRL_REJECT);
 		}
@@ -1998,7 +1950,6 @@ static void handle_ctrl_request(int port, uint32_t head,
 				pd_dr_swap(port);
 		} else {
 			send_control(port, PD_CTRL_REJECT);
-
 		}
 		break;
 	case PD_CTRL_VCONN_SWAP:
@@ -2045,8 +1996,7 @@ static void handle_ext_request(int port, uint16_t head, uint32_t *payload)
 }
 #endif
 
-static void handle_request(int port, uint32_t head,
-		uint32_t *payload)
+static void handle_request(int port, uint32_t head, uint32_t *payload)
 {
 	int cnt = PD_HEADER_CNT(head);
 	int data_role = PD_HEADER_DROLE(head);
@@ -2091,8 +2041,7 @@ static void handle_request(int port, uint32_t head,
 							    TYPEC_CC_RP));
 		}
 		set_state(port,
-			  DUAL_ROLE_IF_ELSE(port,
-					    PD_STATE_SNK_DISCONNECTED,
+			  DUAL_ROLE_IF_ELSE(port, PD_STATE_SNK_DISCONNECTED,
 					    PD_STATE_SRC_DISCONNECTED));
 		return;
 	}
@@ -2119,8 +2068,11 @@ void pd_send_vdm(int port, uint32_t vid, int cmd, const uint32_t *data,
 	}
 
 	/* set VDM header with VID & CMD */
-	pd[port].vdo_data[0] = VDO(vid, ((vid & USB_SID_PD) == USB_SID_PD) ?
-				   1 : (PD_VDO_CMD(cmd) <= CMD_ATTENTION), cmd);
+	pd[port].vdo_data[0] = VDO(vid,
+				   ((vid & USB_SID_PD) == USB_SID_PD) ?
+					   1 :
+					   (PD_VDO_CMD(cmd) <= CMD_ATTENTION),
+				   cmd);
 #ifdef CONFIG_USB_PD_REV30
 	pd[port].vdo_data[0] |= VDO_SVDM_VERS(vdo_ver[pd[port].rev]);
 #endif
@@ -2150,7 +2102,7 @@ static uint64_t vdm_get_ready_timeout(uint32_t vdm_hdr)
 
 	/* its not a structured VDM command */
 	if (!PD_VDO_SVDM(vdm_hdr))
-		return 500*MSEC;
+		return 500 * MSEC;
 
 	switch (PD_VDO_CMDT(vdm_hdr)) {
 	case CMDT_INIT:
@@ -2169,50 +2121,10 @@ static uint64_t vdm_get_ready_timeout(uint32_t vdm_hdr)
 	return timeout;
 }
 
-static void exit_tbt_mode_sop_prime(int port)
-{
-	/* Exit Thunderbolt-Compatible mode SOP' */
-	uint16_t header;
-	int opos;
-
-	if (!IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE))
-		return;
-
-	opos = pd_alt_mode(port, TCPCI_MSG_SOP, USB_VID_INTEL);
-	if (opos <= 0)
-		return;
-
-	CPRINTS("C%d Cable exiting TBT Compat mode", port);
-	/*
-	 * Note: TCPMv2 contemplates separate discovery structures for each SOP
-	 * type. TCPMv1 only uses one discovery structure, so all accesses
-	 * specify TCPCI_MSG_SOP.
-	 */
-	if (pd_dfp_exit_mode(port, TCPCI_MSG_SOP, USB_VID_INTEL, opos))
-		usb_mux_set_safe_mode(port);
-	else
-		return;
-
-	header = PD_HEADER(PD_DATA_VENDOR_DEF, pd[port].power_role,
-			pd[port].data_role, pd[port].msg_id,
-			(int)pd[port].vdo_count,
-			pd_get_rev(port, TCPCI_MSG_SOP), 0);
-
-	pd[port].vdo_data[0] = VDO(USB_VID_INTEL, 1,
-				   CMD_EXIT_MODE | VDO_OPOS(opos));
-
-	pd_transmit(port, TCPCI_MSG_SOP_PRIME, header, pd[port].vdo_data,
-		    AMS_START);
-
-	usb_mux_set(port, USB_PD_MUX_USB_ENABLED, USB_SWITCH_CONNECT,
-		   polarity_rm_dts(pd_get_polarity(port)));
-}
-
 static void pd_vdm_send_state_machine(int port)
 {
 	int res;
 	uint16_t header;
-	enum tcpci_msg_type msg_type = pd[port].xmit_type;
 
 	switch (pd[port].vdm_state) {
 	case VDM_STATE_READY:
@@ -2229,82 +2141,20 @@ static void pd_vdm_send_state_machine(int port)
 		if (pdo_busy(port))
 			break;
 
-		/*
-		 * To communicate with the cable plug, an explicit contract
-		 * should be established, VCONN should be enabled and data role
-		 * that can communicate with the cable plug should be in place.
-		 * For USB3.0, UFP/DFP can communicate whereas in case of
-		 * USB2.0 only DFP can talk to the cable plug.
-		 *
-		 * For communication between USB2.0 UFP and cable plug,
-		 * data role swap takes place during source and sink
-		 * negotiation and in case of failure, a soft reset is issued.
-		 */
-		if ((msg_type == TCPCI_MSG_SOP_PRIME) ||
-		    (msg_type == TCPCI_MSG_SOP_PRIME_PRIME)) {
-			/* Prepare SOP'/SOP'' header and send VDM */
-			header = PD_HEADER(
-				PD_DATA_VENDOR_DEF,
-				PD_PLUG_FROM_DFP_UFP,
-				0,
-				pd[port].msg_id,
-				(int)pd[port].vdo_count,
-				pd_get_rev(port, TCPCI_MSG_SOP),
-				0);
-			res = pd_transmit(port, msg_type, header,
-					  pd[port].vdo_data, AMS_START);
-			/*
-			 * In the case of SOP', if there is no response from
-			 * the cable, it's a non-emark cable and therefore the
-			 * pd flow should continue irrespective of cable
-			 * response, sending discover_identity so the pd flow
-			 * remains intact.
-			 *
-			 * In the case of SOP'', if there is no response from
-			 * the cable, exit Thunderbolt-Compatible mode
-			 * discovery, reset the mux state since, the mux will
-			 * be set to a safe state before entering
-			 * Thunderbolt-Compatible mode and enter the default
-			 * mode.
-			 */
-			if (res < 0) {
-				header = PD_HEADER(PD_DATA_VENDOR_DEF,
-						   pd[port].power_role,
-						   pd[port].data_role,
-						   pd[port].msg_id,
-						   (int)pd[port].vdo_count,
-						   pd_get_rev
-							(port, TCPCI_MSG_SOP),
-						   0);
-
-				if ((msg_type == TCPCI_MSG_SOP_PRIME_PRIME) &&
-				     IS_ENABLED(CONFIG_USBC_SS_MUX)) {
-					exit_tbt_mode_sop_prime(port);
-				} else if (msg_type == TCPCI_MSG_SOP_PRIME) {
-					pd[port].vdo_data[0] = VDO(USB_SID_PD,
-						1, CMD_DISCOVER_SVID);
-				}
-				res = pd_transmit(port, TCPCI_MSG_SOP, header,
-						  pd[port].vdo_data, AMS_START);
-				reset_pd_cable(port);
-			}
-		} else {
-			/* Prepare SOP header and send VDM */
-			header = PD_HEADER(PD_DATA_VENDOR_DEF,
-					   pd[port].power_role,
-					   pd[port].data_role,
-					   pd[port].msg_id,
-					   (int)pd[port].vdo_count,
-					   pd_get_rev(port, TCPCI_MSG_SOP), 0);
-			res = pd_transmit(port, TCPCI_MSG_SOP, header,
-					  pd[port].vdo_data, AMS_START);
-		}
+		/* Prepare SOP header and send VDM */
+		header = PD_HEADER(PD_DATA_VENDOR_DEF, pd[port].power_role,
+				   pd[port].data_role, pd[port].msg_id,
+				   (int)pd[port].vdo_count,
+				   pd_get_rev(port, TCPCI_MSG_SOP), 0);
+		res = pd_transmit(port, TCPCI_MSG_SOP, header,
+				  pd[port].vdo_data, AMS_START);
 
 		if (res < 0) {
 			pd[port].vdm_state = VDM_STATE_ERR_SEND;
 		} else {
 			pd[port].vdm_state = VDM_STATE_BUSY;
-			pd[port].vdm_timeout.val = get_time().val +
+			pd[port].vdm_timeout.val =
+				get_time().val +
 				vdm_get_ready_timeout(pd[port].vdo_data[0]);
 		}
 		break;
@@ -2366,15 +2216,14 @@ int pd_dev_store_rw_hash(int port, uint16_t dev_id, uint32_t *rw_hash,
 	/* Search table for matching device / hash */
 	for (i = 0; i < RW_HASH_ENTRIES; i++)
 		if (dev_id == rw_hash_table[i].dev_id)
-			return !memcmp(rw_hash,
-				       rw_hash_table[i].dev_rw_hash,
+			return !memcmp(rw_hash, rw_hash_table[i].dev_rw_hash,
 				       PD_RW_HASH_SIZE);
 #endif
 	return 0;
 }
 
 void pd_dev_get_rw_hash(int port, uint16_t *dev_id, uint8_t *rw_hash,
-			 uint32_t *current_image)
+			uint32_t *current_image)
 {
 	*dev_id = pd[port].dev_id;
 	*current_image = pd[port].current_image;
@@ -2391,10 +2240,11 @@ __maybe_unused static void exit_supported_alt_mode(int port)
 
 	for (i = 0; i < supported_modes_cnt; i++) {
 		int opos = pd_alt_mode(port, TCPCI_MSG_SOP,
-				supported_modes[i].svid);
+				       supported_modes[i].svid);
 
-		if (opos > 0 && pd_dfp_exit_mode(port, TCPCI_MSG_SOP,
-					supported_modes[i].svid, opos)) {
+		if (opos > 0 &&
+		    pd_dfp_exit_mode(port, TCPCI_MSG_SOP,
+				     supported_modes[i].svid, opos)) {
 			CPRINTS("C%d Exiting ALT mode with SVID = 0x%x", port,
 				supported_modes[i].svid);
 			usb_mux_set_safe_mode(port);
@@ -2409,7 +2259,6 @@ __maybe_unused static void exit_supported_alt_mode(int port)
 #ifdef CONFIG_POWER_COMMON
 static void handle_new_power_state(int port)
 {
-
 	if (chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF)) {
 		/*
 		 * The SoC will negotiate the alternate mode again when
@@ -2473,8 +2322,8 @@ static void pd_update_snk_reset(void)
 
 			if (pd[i].task_state == PD_STATE_SNK_DISCOVERY) {
 				CPRINTS("C%d: Starting soft reset timer", i);
-				set_state_timeout(i,
-					get_time().val + PD_T_SINK_WAIT_CAP,
+				set_state_timeout(
+					i, get_time().val + PD_T_SINK_WAIT_CAP,
 					PD_STATE_SOFT_RESET);
 			}
 		}
@@ -2518,13 +2367,13 @@ void pd_set_dual_role(int port, enum pd_dual_role_states state)
 static int pd_is_power_swapping(int port)
 {
 	/* return true if in the act of swapping power roles */
-	return  pd[port].task_state == PD_STATE_SNK_SWAP_SNK_DISABLE ||
-		pd[port].task_state == PD_STATE_SNK_SWAP_SRC_DISABLE ||
-		pd[port].task_state == PD_STATE_SNK_SWAP_STANDBY ||
-		pd[port].task_state == PD_STATE_SNK_SWAP_COMPLETE ||
-		pd[port].task_state == PD_STATE_SRC_SWAP_SNK_DISABLE ||
-		pd[port].task_state == PD_STATE_SRC_SWAP_SRC_DISABLE ||
-		pd[port].task_state == PD_STATE_SRC_SWAP_STANDBY;
+	return pd[port].task_state == PD_STATE_SNK_SWAP_SNK_DISABLE ||
+	       pd[port].task_state == PD_STATE_SNK_SWAP_SRC_DISABLE ||
+	       pd[port].task_state == PD_STATE_SNK_SWAP_STANDBY ||
+	       pd[port].task_state == PD_STATE_SNK_SWAP_COMPLETE ||
+	       pd[port].task_state == PD_STATE_SRC_SWAP_SNK_DISABLE ||
+	       pd[port].task_state == PD_STATE_SRC_SWAP_SRC_DISABLE ||
+	       pd[port].task_state == PD_STATE_SRC_SWAP_STANDBY;
 }
 
 /* This must only be called from the PD task */
@@ -2536,9 +2385,9 @@ static void pd_update_dual_role_config(int port)
 	 * source disconnected state).
 	 */
 	if (pd[port].power_role == PD_ROLE_SOURCE &&
-	    (drp_state[port] == PD_DRP_FORCE_SINK
-	     || (drp_state[port] == PD_DRP_TOGGLE_OFF
-		 && pd[port].task_state == PD_STATE_SRC_DISCONNECTED))) {
+	    (drp_state[port] == PD_DRP_FORCE_SINK ||
+	     (drp_state[port] == PD_DRP_TOGGLE_OFF &&
+	      pd[port].task_state == PD_STATE_SRC_DISCONNECTED))) {
 		pd_set_power_role(port, PD_ROLE_SINK);
 		set_state(port, PD_STATE_SNK_DISCONNECTED);
 		tcpm_set_cc(port, TYPEC_CC_RD);
@@ -2695,8 +2544,7 @@ void pd_comm_enable(int port, int enable)
 	 * any port in PD_SNK_DISCOVERY.
 	 */
 	if (enable && pd[port].task_state == PD_STATE_SNK_DISCOVERY)
-		set_state_timeout(port,
-				  get_time().val + PD_T_SINK_WAIT_CAP,
+		set_state_timeout(port, get_time().val + PD_T_SINK_WAIT_CAP,
 				  PD_STATE_HARD_RESET_SEND);
 #endif
 }
@@ -2794,57 +2642,12 @@ static int pd_restart_tcpc(int port)
 }
 #endif
 
-static void pd_send_enter_usb(int port, int *timeout)
-{
-	uint32_t usb4_payload;
-	uint16_t header;
-	int res;
-
-	/*
-	 * TODO: Enable Enter USB for cables (SOP').
-	 * This is needed for active cables
-	 */
-	if (!IS_ENABLED(CONFIG_USBC_SS_MUX) ||
-	    !IS_ENABLED(CONFIG_USB_PD_USB4) ||
-	    !IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP))
-		return;
-
-	usb4_payload = get_enter_usb_msg_payload(port);
-
-	header = PD_HEADER(PD_DATA_ENTER_USB,
-		pd[port].power_role,
-		pd[port].data_role,
-		pd[port].msg_id,
-		1,
-		PD_REV30,
-		0);
-
-	res = pd_transmit(port, TCPCI_MSG_SOP, header, &usb4_payload,
-			AMS_START);
-	if (res < 0) {
-		*timeout = 10*MSEC;
-		/*
-		 * If failed to get goodCRC, send soft reset, otherwise ignore
-		 * failure.
-		 */
-		set_state(port, res == -1 ?
-			   PD_STATE_SOFT_RESET :
-			   READY_RETURN_STATE(port));
-		return;
-	}
-
-	/* Disable Enter USB4 mode prevent re-entry */
-	disable_enter_usb4_mode(port);
-
-	set_state(port, PD_STATE_ENTER_USB);
-}
-
 void pd_task(void *u)
 {
 	uint32_t head;
 	int port = TASK_ID_TO_PD_PORT(task_get_current());
 	uint32_t payload[7];
-	int timeout = 10*MSEC;
+	int timeout = 10 * MSEC;
 	enum tcpc_cc_voltage_status cc1, cc2;
 	int res, incoming_packet = 0;
 	int hard_reset_count = 0;
@@ -2922,8 +2725,7 @@ void pd_task(void *u)
 	if (!res) {
 		struct ec_response_pd_chip_info_v1 info;
 
-		if (tcpm_get_chip_info(port, 0, &info) ==
-		    EC_SUCCESS) {
+		if (tcpm_get_chip_info(port, 0, &info) == EC_SUCCESS) {
 			CPRINTS("TCPC p%d VID:0x%x PID:0x%x DID:0x%x "
 				"FWV:0x%" PRIx64,
 				port, info.vendor_id, info.product_id,
@@ -2943,8 +2745,8 @@ void pd_task(void *u)
 	 * present. This flag is used to maintain a PD connection after a
 	 * reset by sending a soft reset.
 	 */
-	pd[port].flags |=
-		pd_is_vbus_present(port) ? PD_FLAGS_VBUS_NEVER_LOW : 0;
+	pd[port].flags |= pd_is_vbus_present(port) ? PD_FLAGS_VBUS_NEVER_LOW :
+						     0;
 #endif
 
 	/* Disable TCPC RX until connection is established */
@@ -2968,14 +2770,17 @@ void pd_task(void *u)
 		if ((saved_flgs & PD_BBRMFLG_POWER_ROLE) == PD_ROLE_SINK) {
 			pd_set_power_role(port,
 					  (saved_flgs & PD_BBRMFLG_POWER_ROLE) ?
-					  PD_ROLE_SOURCE : PD_ROLE_SINK);
+						  PD_ROLE_SOURCE :
+						  PD_ROLE_SINK);
 			pd_set_data_role(port,
 					 (saved_flgs & PD_BBRMFLG_DATA_ROLE) ?
-					 PD_ROLE_DFP : PD_ROLE_UFP);
+						 PD_ROLE_DFP :
+						 PD_ROLE_UFP);
 #ifdef CONFIG_USBC_VCONN
 			pd_set_vconn_role(port,
 					  (saved_flgs & PD_BBRMFLG_VCONN_ROLE) ?
-					  PD_ROLE_VCONN_ON : PD_ROLE_VCONN_OFF);
+						  PD_ROLE_VCONN_ON :
+						  PD_ROLE_VCONN_OFF);
 #endif /* CONFIG_USBC_VCONN */
 
 			/*
@@ -2997,9 +2802,8 @@ void pd_task(void *u)
 			 * earlier, so clear the contract flag and re-start as
 			 * default role
 			 */
-			pd_update_saved_port_flags(port,
-					PD_BBRMFLG_EXPLICIT_CONTRACT, 0);
-
+			pd_update_saved_port_flags(
+				port, PD_BBRMFLG_EXPLICIT_CONTRACT, 0);
 		}
 		/*
 		 * Set the TCPC reset event such that we can set our CC
@@ -3026,7 +2830,8 @@ void pd_task(void *u)
 	if (!(saved_flgs & PD_BBRMFLG_EXPLICIT_CONTRACT))
 #endif /* CONFIG_USB_PD_DUAL_ROLE */
 		tcpm_set_cc(port, PD_ROLE_DEFAULT(port) == PD_ROLE_SOURCE ?
-			    TYPEC_CC_RP : TYPEC_CC_RD);
+					  TYPEC_CC_RP :
+					  TYPEC_CC_RD);
 
 #ifdef CONFIG_USBC_PPC
 	/*
@@ -3126,7 +2931,8 @@ void pd_task(void *u)
 				 * role.
 				 */
 				tcpm_set_cc(port, pd[port].power_role ?
-					    TYPEC_CC_RP : TYPEC_CC_RD);
+							  TYPEC_CC_RP :
+							  TYPEC_CC_RD);
 
 				/* Determine the polarity. */
 				tcpm_get_cc(port, &cc1, &cc2);
@@ -3136,7 +2942,7 @@ void pd_task(void *u)
 				} else if (cc_is_snk_dbg_acc(cc1, cc2)) {
 					pd[port].polarity =
 						board_get_src_dts_polarity(
-								port);
+							port);
 				} else {
 					pd[port].polarity =
 						get_src_polarity(cc1, cc2);
@@ -3145,9 +2951,11 @@ void pd_task(void *u)
 #endif /* CONFIG_USB_PD_DUAL_ROLE */
 			{
 				/* Ensure CC termination is default */
-				tcpm_set_cc(port, PD_ROLE_DEFAULT(port) ==
-					    PD_ROLE_SOURCE ? TYPEC_CC_RP :
-					    TYPEC_CC_RD);
+				tcpm_set_cc(port,
+					    PD_ROLE_DEFAULT(port) ==
+							    PD_ROLE_SOURCE ?
+						    TYPEC_CC_RP :
+						    TYPEC_CC_RD);
 			}
 
 			/*
@@ -3157,14 +2965,18 @@ void pd_task(void *u)
 			 * Otherwise, go to the default disconnected state
 			 * and force renegotiation.
 			 */
-			if (pd[port].vdm_state == VDM_STATE_DONE && (
+			if (pd[port].vdm_state == VDM_STATE_DONE &&
+			    (
 #ifdef CONFIG_USB_PD_DUAL_ROLE
-			     (PD_ROLE_DEFAULT(port) == PD_ROLE_SINK &&
-			     pd[port].task_state == PD_STATE_SNK_READY) ||
-			     (pd[port].task_state == PD_STATE_SOFT_RESET) ||
-#endif
-			     (PD_ROLE_DEFAULT(port) == PD_ROLE_SOURCE &&
-			     pd[port].task_state == PD_STATE_SRC_READY))) {
+				    (PD_ROLE_DEFAULT(port) == PD_ROLE_SINK &&
+				     pd[port].task_state ==
+					     PD_STATE_SNK_READY) ||
+				    (pd[port].task_state ==
+				     PD_STATE_SOFT_RESET) ||
+#endif
+				    (PD_ROLE_DEFAULT(port) == PD_ROLE_SOURCE &&
+				     pd[port].task_state ==
+					     PD_STATE_SRC_READY))) {
 				typec_set_polarity(port, pd[port].polarity);
 				tcpm_set_msg_header(port, pd[port].power_role,
 						    pd[port].data_role);
@@ -3198,9 +3010,8 @@ void pd_task(void *u)
 		if (incoming_packet) {
 			/* Dequeue and consume duplicate message ID. */
 			if (tcpm_dequeue_message(port, payload, &head) ==
-								EC_SUCCESS
-			    && !consume_repeat_message(port, head)
-			   )
+				    EC_SUCCESS &&
+			    !consume_repeat_message(port, head))
 				handle_request(port, head, payload);
 
 			/* Check if there are any more messages */
@@ -3214,13 +3025,13 @@ void pd_task(void *u)
 
 		/* if nothing to do, verify the state of the world in 500ms */
 		this_state = pd[port].task_state;
-		timeout = 500*MSEC;
+		timeout = 500 * MSEC;
 		switch (this_state) {
 		case PD_STATE_DISABLED:
 			/* Nothing to do */
 			break;
 		case PD_STATE_SRC_DISCONNECTED:
-			timeout = 10*MSEC;
+			timeout = 10 * MSEC;
 			pd_set_src_caps(port, 0, NULL);
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
 			/*
@@ -3242,10 +3053,9 @@ void pd_task(void *u)
 			 */
 			if (auto_toggle_supported &&
 			    !(pd[port].flags & PD_FLAGS_TCPC_DRP_TOGGLE) &&
-			    !is_try_src(port) &&
-			    cc_is_open(cc1, cc2)) {
+			    !is_try_src(port) && cc_is_open(cc1, cc2)) {
 				set_state(port, PD_STATE_DRP_AUTO_TOGGLE);
-				timeout = 2*MSEC;
+				timeout = 2 * MSEC;
 				break;
 			}
 #endif
@@ -3275,7 +3085,7 @@ void pd_task(void *u)
 #endif
 				pd[port].cc_state = PD_CC_NONE;
 				set_state(port,
-					PD_STATE_SRC_DISCONNECTED_DEBOUNCE);
+					  PD_STATE_SRC_DISCONNECTED_DEBOUNCE);
 				break;
 			}
 #if defined(CONFIG_USB_PD_DUAL_ROLE)
@@ -3331,7 +3141,7 @@ void pd_task(void *u)
 #endif
 			break;
 		case PD_STATE_SRC_DISCONNECTED_DEBOUNCE:
-			timeout = 20*MSEC;
+			timeout = 20 * MSEC;
 			tcpm_get_cc(port, &cc1, &cc2);
 
 			if (cc_is_snk_dbg_acc(cc1, cc2)) {
@@ -3346,7 +3156,7 @@ void pd_task(void *u)
 			} else {
 				/* No UFP */
 				set_state(port, PD_STATE_SRC_DISCONNECTED);
-				timeout = 5*MSEC;
+				timeout = 5 * MSEC;
 				break;
 			}
 
@@ -3354,8 +3164,8 @@ void pd_task(void *u)
 			if (new_cc_state != pd[port].cc_state) {
 				pd[port].cc_debounce =
 					get_time().val +
-					(is_try_src(port) ? PD_T_DEBOUNCE
-							  : PD_T_CC_DEBOUNCE);
+					(is_try_src(port) ? PD_T_DEBOUNCE :
+							    PD_T_CC_DEBOUNCE);
 				pd[port].cc_state = new_cc_state;
 				break;
 			}
@@ -3455,7 +3265,7 @@ void pd_task(void *u)
 				pd[port].flags |= PD_FLAGS_CHECK_PR_ROLE |
 						  PD_FLAGS_CHECK_DR_ROLE;
 				hard_reset_count = 0;
-				timeout = 5*MSEC;
+				timeout = 5 * MSEC;
 
 				set_state(port, PD_STATE_SRC_STARTUP);
 			}
@@ -3467,7 +3277,7 @@ void pd_task(void *u)
 		case PD_STATE_SRC_HARD_RESET_RECOVER:
 			/* Do not continue until hard reset recovery time */
 			if (get_time().val < pd[port].src_recover) {
-				timeout = 50*MSEC;
+				timeout = 50 * MSEC;
 				break;
 			}
 
@@ -3481,7 +3291,7 @@ void pd_task(void *u)
 #endif
 
 			/* Enable VBUS */
-			timeout = 10*MSEC;
+			timeout = 10 * MSEC;
 			if (pd_set_power_supply_ready(port)) {
 				set_state(port, PD_STATE_SRC_DISCONNECTED);
 				break;
@@ -3501,8 +3311,6 @@ void pd_task(void *u)
 			set_state(port, PD_STATE_SRC_STARTUP);
 			break;
 		case PD_STATE_SRC_STARTUP:
-			/* Reset cable attributes and flags */
-			reset_pd_cable(port);
 			/* Wait for power source to enable */
 			if (pd[port].last_state != pd[port].task_state) {
 				pd[port].flags |= PD_FLAGS_CHECK_IDENTITY;
@@ -3520,13 +3328,14 @@ void pd_task(void *u)
 					 * on during debounce.
 					 */
 					get_time().val +
-					PD_POWER_SUPPLY_TURN_ON_DELAY -
-					  (pd[port].last_state ==
-					   PD_STATE_SRC_DISCONNECTED_DEBOUNCE
-						? PD_T_CC_DEBOUNCE : 0),
+						PD_POWER_SUPPLY_TURN_ON_DELAY -
+						(pd[port].last_state ==
+								 PD_STATE_SRC_DISCONNECTED_DEBOUNCE ?
+							 PD_T_CC_DEBOUNCE :
+							 0),
 #else
 					get_time().val +
-					PD_POWER_SUPPLY_TURN_ON_DELAY,
+						PD_POWER_SUPPLY_TURN_ON_DELAY,
 #endif
 					PD_STATE_SRC_DISCOVERY);
 			}
@@ -3541,25 +3350,25 @@ void pd_task(void *u)
 				 * partner, then start NoResponseTimer.
 				 */
 				if (pd_capable(port))
-					set_state_timeout(port,
+					set_state_timeout(
+						port,
 						get_time().val +
-						PD_T_NO_RESPONSE,
+							PD_T_NO_RESPONSE,
 						hard_reset_count <
-						  PD_HARD_RESET_COUNT ?
-						    PD_STATE_HARD_RESET_SEND :
-						    PD_STATE_SRC_DISCONNECTED);
+								PD_HARD_RESET_COUNT ?
+							PD_STATE_HARD_RESET_SEND :
+							PD_STATE_SRC_DISCONNECTED);
 			}
 
 			/* Send source cap some minimum number of times */
-			if (caps_count < PD_CAPS_COUNT  &&
-						next_src_cap <= now.val) {
+			if (caps_count < PD_CAPS_COUNT &&
+			    next_src_cap <= now.val) {
 				/* Query capabilities of the other side */
 				res = send_source_cap(port, AMS_START);
 				/* packet was acked => PD capable device) */
 				if (res >= 0) {
-					set_state(port,
-						  PD_STATE_SRC_NEGOCIATE);
-					timeout = 10*MSEC;
+					set_state(port, PD_STATE_SRC_NEGOCIATE);
+					timeout = 10 * MSEC;
 					hard_reset_count = 0;
 					caps_count = 0;
 					/* Port partner is PD capable */
@@ -3567,8 +3376,8 @@ void pd_task(void *u)
 						PD_FLAGS_PREVIOUS_PD_CONN;
 				} else { /* failed, retry later */
 					timeout = PD_T_SEND_SOURCE_CAP;
-					next_src_cap = now.val +
-							PD_T_SEND_SOURCE_CAP;
+					next_src_cap =
+						now.val + PD_T_SEND_SOURCE_CAP;
 					caps_count++;
 				}
 			} else if (caps_count < PD_CAPS_COUNT) {
@@ -3580,17 +3389,16 @@ void pd_task(void *u)
 			if (pd[port].last_state != pd[port].task_state)
 				set_state_timeout(port,
 						  get_time().val +
-						  PD_T_SENDER_RESPONSE,
+							  PD_T_SENDER_RESPONSE,
 						  PD_STATE_HARD_RESET_SEND);
 			break;
 		case PD_STATE_SRC_ACCEPTED:
 			/* Accept sent, wait for enabling the new voltage */
 			if (pd[port].last_state != pd[port].task_state)
-				set_state_timeout(
-					port,
-					get_time().val +
-					PD_T_SINK_TRANSITION,
-					PD_STATE_SRC_POWERED);
+				set_state_timeout(port,
+						  get_time().val +
+							  PD_T_SINK_TRANSITION,
+						  PD_STATE_SRC_POWERED);
 			break;
 		case PD_STATE_SRC_POWERED:
 			/* Switch to the new requested voltage */
@@ -3600,7 +3408,7 @@ void pd_task(void *u)
 				set_state_timeout(
 					port,
 					get_time().val +
-					PD_POWER_SUPPLY_TURN_ON_DELAY,
+						PD_POWER_SUPPLY_TURN_ON_DELAY,
 					PD_STATE_SRC_TRANSITION);
 			}
 			break;
@@ -3608,7 +3416,7 @@ void pd_task(void *u)
 			/* the voltage output is good, notify the source */
 			res = send_control(port, PD_CTRL_PS_RDY);
 			if (res >= 0) {
-				timeout = 10*MSEC;
+				timeout = 10 * MSEC;
 
 				/*
 				 * Give the sink some time to send any messages
@@ -3621,8 +3429,8 @@ void pd_task(void *u)
 				 * SRC_READY state.
 				 */
 				pd[port].ready_state_holdoff_timer =
-					get_time().val + SRC_READY_HOLD_OFF_US
-					+ (get_time().le.lo & 0xf) * 12 * MSEC;
+					get_time().val + SRC_READY_HOLD_OFF_US +
+					(get_time().le.lo & 0xf) * 12 * MSEC;
 
 				/* it's time to ping regularly the sink */
 				set_state(port, PD_STATE_SRC_READY);
@@ -3658,8 +3466,7 @@ void pd_task(void *u)
 			if (pd[port].flags & PD_FLAGS_UPDATE_SRC_CAPS) {
 				res = send_source_cap(port, AMS_START);
 				if (res >= 0) {
-					set_state(port,
-						  PD_STATE_SRC_NEGOCIATE);
+					set_state(port, PD_STATE_SRC_NEGOCIATE);
 					pd[port].flags &=
 						~PD_FLAGS_UPDATE_SRC_CAPS;
 				}
@@ -3669,12 +3476,16 @@ void pd_task(void *u)
 			/* Send get sink cap if haven't received it yet */
 			if (!(pd[port].flags & PD_FLAGS_SNK_CAP_RECVD)) {
 				if (++snk_cap_count <= PD_SNK_CAP_RETRIES) {
-					/* Get sink cap to know if dual-role device */
-					send_control(port, PD_CTRL_GET_SINK_CAP);
-					set_state(port, PD_STATE_SRC_GET_SINK_CAP);
+					/* Get sink cap to know if dual-role
+					 * device */
+					send_control(port,
+						     PD_CTRL_GET_SINK_CAP);
+					set_state(port,
+						  PD_STATE_SRC_GET_SINK_CAP);
 					break;
 				} else if (debug_level >= 2 &&
-					   snk_cap_count == PD_SNK_CAP_RETRIES+1) {
+					   snk_cap_count ==
+						   PD_SNK_CAP_RETRIES + 1) {
 					CPRINTF("C%d ERR SNK_CAP\n", port);
 				}
 			}
@@ -3686,7 +3497,6 @@ void pd_task(void *u)
 				pd[port].flags &= ~PD_FLAGS_CHECK_PR_ROLE;
 			}
 
-
 			/* Check data role policy, which may trigger a swap */
 			if (pd[port].flags & PD_FLAGS_CHECK_DR_ROLE) {
 				pd_check_dr_role(port, pd[port].data_role,
@@ -3705,8 +3515,7 @@ void pd_task(void *u)
 				 * initiate or receive a request an exchange
 				 * of VCONN Source.
 				 */
-				pd_try_execute_vconn_swap(port,
-							  pd[port].flags);
+				pd_try_execute_vconn_swap(port, pd[port].flags);
 				pd[port].flags &= ~PD_FLAGS_CHECK_VCONN_STATE;
 				break;
 			}
@@ -3722,15 +3531,6 @@ void pd_task(void *u)
 				break;
 			}
 
-			/*
-			 * Enter_USB if port partner and cable are
-			 * USB4 compatible.
-			 */
-			if (should_enter_usb4_mode(port)) {
-				pd_send_enter_usb(port, &timeout);
-				break;
-			}
-
 			if (!(pd[port].flags & PD_FLAGS_PING_ENABLED))
 				break;
 
@@ -3747,28 +3547,30 @@ void pd_task(void *u)
 			if (pd[port].last_state != pd[port].task_state)
 				set_state_timeout(port,
 						  get_time().val +
-						  PD_T_SENDER_RESPONSE,
+							  PD_T_SENDER_RESPONSE,
 						  PD_STATE_SRC_READY);
 			break;
 		case PD_STATE_DR_SWAP:
 			if (pd[port].last_state != pd[port].task_state) {
 				res = send_control(port, PD_CTRL_DR_SWAP);
 				if (res < 0) {
-					timeout = 10*MSEC;
+					timeout = 10 * MSEC;
 					/*
 					 * If failed to get goodCRC, send
 					 * soft reset, otherwise ignore
 					 * failure.
 					 */
-					set_state(port, res == -1 ?
-						   PD_STATE_SOFT_RESET :
-						   READY_RETURN_STATE(port));
+					set_state(port,
+						  res == -1 ?
+							  PD_STATE_SOFT_RESET :
+							  READY_RETURN_STATE(
+								  port));
 					break;
 				}
 				/* Wait for accept or reject */
 				set_state_timeout(port,
 						  get_time().val +
-						  PD_T_SENDER_RESPONSE,
+							  PD_T_SENDER_RESPONSE,
 						  READY_RETURN_STATE(port));
 			}
 			break;
@@ -3777,31 +3579,32 @@ void pd_task(void *u)
 			if (pd[port].last_state != pd[port].task_state) {
 				res = send_control(port, PD_CTRL_PR_SWAP);
 				if (res < 0) {
-					timeout = 10*MSEC;
+					timeout = 10 * MSEC;
 					/*
 					 * If failed to get goodCRC, send
 					 * soft reset, otherwise ignore
 					 * failure.
 					 */
-					set_state(port, res == -1 ?
-						   PD_STATE_SOFT_RESET :
-						   PD_STATE_SRC_READY);
+					set_state(port,
+						  res == -1 ?
+							  PD_STATE_SOFT_RESET :
+							  PD_STATE_SRC_READY);
 					break;
 				}
 				/* Wait for accept or reject */
 				set_state_timeout(port,
 						  get_time().val +
-						  PD_T_SENDER_RESPONSE,
+							  PD_T_SENDER_RESPONSE,
 						  PD_STATE_SRC_READY);
 			}
 			break;
 		case PD_STATE_SRC_SWAP_SNK_DISABLE:
 			/* Give time for sink to stop drawing current */
 			if (pd[port].last_state != pd[port].task_state)
-				set_state_timeout(port,
-						  get_time().val +
-						  PD_T_SINK_TRANSITION,
-						  PD_STATE_SRC_SWAP_SRC_DISABLE);
+				set_state_timeout(
+					port,
+					get_time().val + PD_T_SINK_TRANSITION,
+					PD_STATE_SRC_SWAP_SRC_DISABLE);
 			break;
 		case PD_STATE_SRC_SWAP_SRC_DISABLE:
 			if (pd[port].last_state != pd[port].task_state) {
@@ -3824,10 +3627,11 @@ void pd_task(void *u)
 				/* Inform TCPC of power role update. */
 				pd_update_roles(port);
 
-				set_state_timeout(port,
-						  get_time().val +
-						  PD_POWER_SUPPLY_TURN_OFF_DELAY,
-						  PD_STATE_SRC_SWAP_STANDBY);
+				set_state_timeout(
+					port,
+					get_time().val +
+						PD_POWER_SUPPLY_TURN_OFF_DELAY,
+					PD_STATE_SRC_SWAP_STANDBY);
 			}
 			break;
 		case PD_STATE_SRC_SWAP_STANDBY:
@@ -3836,7 +3640,7 @@ void pd_task(void *u)
 				/* Send PS_RDY */
 				res = send_control(port, PD_CTRL_PS_RDY);
 				if (res < 0) {
-					timeout = 10*MSEC;
+					timeout = 10 * MSEC;
 					set_state(port,
 						  PD_STATE_SRC_DISCONNECTED);
 					break;
@@ -3844,7 +3648,7 @@ void pd_task(void *u)
 				/* Wait for PS_RDY from new source */
 				set_state_timeout(port,
 						  get_time().val +
-						  PD_T_PS_SOURCE_ON,
+							  PD_T_PS_SOURCE_ON,
 						  PD_STATE_SNK_DISCONNECTED);
 			}
 			break;
@@ -3895,8 +3699,8 @@ void pd_task(void *u)
 			/* Set the CC termination and state back to default */
 			tcpm_set_cc(port,
 				    PD_ROLE_DEFAULT(port) == PD_ROLE_SOURCE ?
-					TYPEC_CC_RP :
-					TYPEC_CC_RD);
+					    TYPEC_CC_RP :
+					    TYPEC_CC_RD);
 			set_state(port, PD_DEFAULT_STATE(port));
 			tcpc_prints("resumed!", port);
 #endif
@@ -3904,10 +3708,11 @@ void pd_task(void *u)
 		}
 		case PD_STATE_SNK_DISCONNECTED:
 #ifdef CONFIG_USB_PD_LOW_POWER
-			timeout = (drp_state[port] !=
-				PD_DRP_TOGGLE_ON ? SECOND : 10*MSEC);
+			timeout = (drp_state[port] != PD_DRP_TOGGLE_ON ?
+					   SECOND :
+					   10 * MSEC);
 #else
-			timeout = 10*MSEC;
+			timeout = 10 * MSEC;
 #endif
 			pd_set_src_caps(port, 0, NULL);
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
@@ -3931,11 +3736,10 @@ void pd_task(void *u)
 			 */
 			if (auto_toggle_supported &&
 			    !(pd[port].flags & PD_FLAGS_TCPC_DRP_TOGGLE) &&
-			    !is_try_src(port) &&
-			    cc_is_open(cc1, cc2) &&
-				(drp_state[port] == PD_DRP_TOGGLE_ON)) {
+			    !is_try_src(port) && cc_is_open(cc1, cc2) &&
+			    (drp_state[port] == PD_DRP_TOGGLE_ON)) {
 				set_state(port, PD_STATE_DRP_AUTO_TOGGLE);
-				timeout = 2*MSEC;
+				timeout = 2 * MSEC;
 				break;
 			}
 #endif
@@ -3945,11 +3749,11 @@ void pd_task(void *u)
 				pd[port].cc_state = PD_CC_NONE;
 				hard_reset_count = 0;
 				new_cc_state = PD_CC_NONE;
-				pd[port].cc_debounce = get_time().val +
-							PD_T_CC_DEBOUNCE;
+				pd[port].cc_debounce =
+					get_time().val + PD_T_CC_DEBOUNCE;
 				set_state(port,
-					PD_STATE_SNK_DISCONNECTED_DEBOUNCE);
-				timeout = 10*MSEC;
+					  PD_STATE_SNK_DISCONNECTED_DEBOUNCE);
+				timeout = 10 * MSEC;
 				break;
 			}
 
@@ -3983,7 +3787,7 @@ void pd_task(void *u)
 #endif
 
 				/* Swap states quickly */
-				timeout = 2*MSEC;
+				timeout = 2 * MSEC;
 				break;
 			}
 
@@ -3994,7 +3798,7 @@ void pd_task(void *u)
 			 * CC status.
 			 */
 			pd[port].flags |= PD_FLAGS_LPM_REQUESTED;
-#endif/* CONFIG_USB_PD_TCPC_LOW_POWER */
+#endif /* CONFIG_USB_PD_TCPC_LOW_POWER */
 			break;
 
 		case PD_STATE_SNK_DISCONNECTED_DEBOUNCE:
@@ -4008,16 +3812,16 @@ void pd_task(void *u)
 			} else {
 				/* No connection any more */
 				set_state(port, PD_STATE_SNK_DISCONNECTED);
-				timeout = 5*MSEC;
+				timeout = 5 * MSEC;
 				break;
 			}
 
-			timeout = 20*MSEC;
+			timeout = 20 * MSEC;
 
 			/* Debounce the cc state */
 			if (new_cc_state != pd[port].cc_state) {
-				pd[port].cc_debounce = get_time().val +
-					PD_T_CC_DEBOUNCE;
+				pd[port].cc_debounce =
+					get_time().val + PD_T_CC_DEBOUNCE;
 				pd[port].cc_state = new_cc_state;
 				break;
 			}
@@ -4032,14 +3836,14 @@ void pd_task(void *u)
 				 * If TRY_SRC is enabled, but not active,
 				 * then force attempt to connect as source.
 				 */
-				pd[port].try_src_marker = get_time().val
-					+ PD_T_DRP_TRY;
-				pd[port].try_timeout = get_time().val
-					+ PD_T_TRY_TIMEOUT;
+				pd[port].try_src_marker =
+					get_time().val + PD_T_DRP_TRY;
+				pd[port].try_timeout =
+					get_time().val + PD_T_TRY_TIMEOUT;
 				/* Swap roles to source */
 				pd_set_power_role(port, PD_ROLE_SOURCE);
 				tcpm_set_cc(port, TYPEC_CC_RP);
-				timeout = 2*MSEC;
+				timeout = 2 * MSEC;
 				set_state(port, PD_STATE_SRC_DISCONNECTED);
 				/* Set flag after the state change */
 				pd[port].flags |= PD_FLAGS_TRY_SRC;
@@ -4060,8 +3864,8 @@ void pd_task(void *u)
 #if defined(CONFIG_CHARGE_MANAGER)
 			typec_curr = usb_get_typec_current_limit(
 				pd[port].polarity, cc1, cc2);
-			typec_set_input_current_limit(
-				port, typec_curr, TYPE_C_VOLTAGE);
+			typec_set_input_current_limit(port, typec_curr,
+						      TYPE_C_VOLTAGE);
 #endif
 
 #ifdef CONFIG_USBC_PPC
@@ -4081,14 +3885,11 @@ void pd_task(void *u)
 				pd[port].flags |= PD_FLAGS_CHECK_PR_ROLE |
 						  PD_FLAGS_CHECK_DR_ROLE |
 						  PD_FLAGS_CHECK_IDENTITY;
-				/* Reset cable attributes and flags */
-				reset_pd_cable(port);
-
 				if (new_cc_state == PD_CC_DFP_DEBUG_ACC)
 					pd[port].flags |=
 						PD_FLAGS_TS_DTS_PARTNER;
 				set_state(port, PD_STATE_SNK_DISCOVERY);
-				timeout = 10*MSEC;
+				timeout = 10 * MSEC;
 				hook_call_deferred(
 					&pd_usb_billboard_deferred_data,
 					PD_T_AME);
@@ -4099,47 +3900,49 @@ void pd_task(void *u)
 				pd[port].flags |= PD_FLAGS_CHECK_IDENTITY;
 
 			if (get_usb_pd_vbus_detect() ==
-					USB_PD_VBUS_DETECT_NONE) {
+			    USB_PD_VBUS_DETECT_NONE) {
 				/*
 				 * Can't measure vbus state so this is the
 				 * maximum recovery time for the source.
 				 */
 				if (pd[port].last_state != pd[port].task_state)
-					set_state_timeout(port, get_time().val +
-						  PD_T_SAFE_0V +
-						  PD_T_SRC_RECOVER_MAX +
-						  PD_T_SRC_TURN_ON,
-						  PD_STATE_SNK_DISCONNECTED);
+					set_state_timeout(
+						port,
+						get_time().val + PD_T_SAFE_0V +
+							PD_T_SRC_RECOVER_MAX +
+							PD_T_SRC_TURN_ON,
+						PD_STATE_SNK_DISCONNECTED);
 			} else {
 #ifndef CONFIG_USB_PD_VBUS_DETECT_NONE
 				/* Wait for VBUS to go low and then high*/
 				if (pd[port].last_state !=
-						pd[port].task_state) {
+				    pd[port].task_state) {
 					snk_hard_reset_vbus_off = 0;
-					set_state_timeout(port,
-						  get_time().val +
-						  PD_T_SAFE_0V,
-						  hard_reset_count <
-						    PD_HARD_RESET_COUNT ?
-						     PD_STATE_HARD_RESET_SEND :
-						     PD_STATE_SNK_DISCOVERY);
+					set_state_timeout(
+						port,
+						get_time().val + PD_T_SAFE_0V,
+						hard_reset_count <
+								PD_HARD_RESET_COUNT ?
+							PD_STATE_HARD_RESET_SEND :
+							PD_STATE_SNK_DISCOVERY);
 				}
 
 				if (!pd_is_vbus_present(port) &&
 				    !snk_hard_reset_vbus_off) {
 					/* VBUS has gone low, reset timeout */
 					snk_hard_reset_vbus_off = 1;
-					set_state_timeout(port,
-						  get_time().val +
-						  PD_T_SRC_RECOVER_MAX +
-						  PD_T_SRC_TURN_ON,
-						  PD_STATE_SNK_DISCONNECTED);
+					set_state_timeout(
+						port,
+						get_time().val +
+							PD_T_SRC_RECOVER_MAX +
+							PD_T_SRC_TURN_ON,
+						PD_STATE_SNK_DISCONNECTED);
 				}
 				if (pd_is_vbus_present(port) &&
 				    snk_hard_reset_vbus_off) {
 					/* VBUS went high again */
 					set_state(port, PD_STATE_SNK_DISCOVERY);
-					timeout = 10*MSEC;
+					timeout = 10 * MSEC;
 				}
 
 				/*
@@ -4152,8 +3955,8 @@ void pd_task(void *u)
 			break;
 		case PD_STATE_SNK_DISCOVERY:
 			/* Wait for source cap expired only if we are enabled */
-			if ((pd[port].last_state != pd[port].task_state)
-			    && pd_comm_is_enabled(port)) {
+			if ((pd[port].last_state != pd[port].task_state) &&
+			    pd_comm_is_enabled(port)) {
 #if defined(CONFIG_USB_PD_TCPM_TCPCI) || defined(CONFIG_USB_PD_TCPM_STUB)
 				/*
 				 * If we come from hard reset recover state,
@@ -4176,58 +3979,64 @@ void pd_task(void *u)
 				 */
 				int batt_soc = usb_get_battery_soc();
 
-				if (batt_soc < CONFIG_USB_PD_RESET_MIN_BATT_SOC ||
+				if (batt_soc <
+					    CONFIG_USB_PD_RESET_MIN_BATT_SOC ||
 				    battery_get_disconnect_state() !=
-						BATTERY_NOT_DISCONNECTED)
+					    BATTERY_NOT_DISCONNECTED)
 					pd[port].flags |=
-						    PD_FLAGS_SNK_WAITING_BATT;
+						PD_FLAGS_SNK_WAITING_BATT;
 				else
 					pd[port].flags &=
-						    ~PD_FLAGS_SNK_WAITING_BATT;
+						~PD_FLAGS_SNK_WAITING_BATT;
 #endif
 
 				if (pd[port].flags &
-						    PD_FLAGS_SNK_WAITING_BATT) {
+				    PD_FLAGS_SNK_WAITING_BATT) {
 #ifdef CONFIG_CHARGE_MANAGER
 					/*
 					 * Configure this port as dedicated for
 					 * now, so it won't be de-selected by
 					 * the charge manager leaving safe mode.
 					 */
-					charge_manager_update_dualrole(port,
-								CAP_DEDICATED);
+					charge_manager_update_dualrole(
+						port, CAP_DEDICATED);
 #endif
 					CPRINTS("C%d: Battery low. "
-						"Hold reset timer", port);
-				/*
-				 * If VBUS has never been low, and we timeout
-				 * waiting for source cap, try a soft reset
-				 * first, in case we were already in a stable
-				 * contract before this boot.
-				 */
+						"Hold reset timer",
+						port);
+					/*
+					 * If VBUS has never been low, and we
+					 * timeout waiting for source cap, try a
+					 * soft reset first, in case we were
+					 * already in a stable contract before
+					 * this boot.
+					 */
 				} else if (pd[port].flags &
-						PD_FLAGS_VBUS_NEVER_LOW) {
-					set_state_timeout(port,
-						  get_time().val +
-						  PD_T_SINK_WAIT_CAP,
-						  PD_STATE_SOFT_RESET);
-				/*
-				 * If we haven't passed hard reset counter,
-				 * start SinkWaitCapTimer, otherwise start
-				 * NoResponseTimer.
-				 */
+					   PD_FLAGS_VBUS_NEVER_LOW) {
+					set_state_timeout(
+						port,
+						get_time().val +
+							PD_T_SINK_WAIT_CAP,
+						PD_STATE_SOFT_RESET);
+					/*
+					 * If we haven't passed hard reset
+					 * counter, start SinkWaitCapTimer,
+					 * otherwise start NoResponseTimer.
+					 */
 				} else if (hard_reset_count <
-						PD_HARD_RESET_COUNT) {
-					set_state_timeout(port,
-						  get_time().val +
-						  PD_T_SINK_WAIT_CAP,
-						  PD_STATE_HARD_RESET_SEND);
+					   PD_HARD_RESET_COUNT) {
+					set_state_timeout(
+						port,
+						get_time().val +
+							PD_T_SINK_WAIT_CAP,
+						PD_STATE_HARD_RESET_SEND);
 				} else if (pd_capable(port)) {
 					/* ErrorRecovery */
-					set_state_timeout(port,
-						  get_time().val +
-						  PD_T_NO_RESPONSE,
-						  PD_STATE_SNK_DISCONNECTED);
+					set_state_timeout(
+						port,
+						get_time().val +
+							PD_T_NO_RESPONSE,
+						PD_STATE_SNK_DISCONNECTED);
 				}
 #if defined(CONFIG_CHARGE_MANAGER)
 				/*
@@ -4247,17 +4056,17 @@ void pd_task(void *u)
 
 			/* Check if CC pull-up has changed */
 			tcpm_get_cc(port, &cc1, &cc2);
-			if (typec_curr != usb_get_typec_current_limit(
-						pd[port].polarity, cc1, cc2)) {
+			if (typec_curr !=
+			    usb_get_typec_current_limit(pd[port].polarity, cc1,
+							cc2)) {
 				/* debounce signal by requiring two reads */
 				if (typec_curr_change) {
 					/* set new input current limit */
-					typec_curr =
-						usb_get_typec_current_limit(
-							pd[port].polarity,
-							cc1, cc2);
+					typec_curr = usb_get_typec_current_limit(
+						pd[port].polarity, cc1, cc2);
 					typec_set_input_current_limit(
-					  port, typec_curr, TYPE_C_VOLTAGE);
+						port, typec_curr,
+						TYPE_C_VOLTAGE);
 				} else {
 					/* delay for debounce */
 					timeout = PD_T_DEBOUNCE;
@@ -4275,7 +4084,7 @@ void pd_task(void *u)
 				hard_reset_count = 0;
 				set_state_timeout(port,
 						  get_time().val +
-						  PD_T_SENDER_RESPONSE,
+							  PD_T_SENDER_RESPONSE,
 						  PD_STATE_HARD_RESET_SEND);
 			}
 			break;
@@ -4284,11 +4093,11 @@ void pd_task(void *u)
 			if (pd[port].last_state != pd[port].task_state)
 				set_state_timeout(port,
 						  get_time().val +
-						  PD_T_PS_TRANSITION,
+							  PD_T_PS_TRANSITION,
 						  PD_STATE_HARD_RESET_SEND);
 			break;
 		case PD_STATE_SNK_READY:
-			timeout = 20*MSEC;
+			timeout = 20 * MSEC;
 
 			/*
 			 * Don't send any traffic yet until our holdoff timer
@@ -4343,52 +4152,43 @@ void pd_task(void *u)
 				 * initiate or receive a request an exchange
 				 * of VCONN Source.
 				 */
-				pd_try_execute_vconn_swap(port,
-							  pd[port].flags);
+				pd_try_execute_vconn_swap(port, pd[port].flags);
 				pd[port].flags &= ~PD_FLAGS_CHECK_VCONN_STATE;
 				break;
 			}
 
 			/* If DFP, send discovery SVDMs */
 			if (pd[port].data_role == PD_ROLE_DFP &&
-			     (pd[port].flags & PD_FLAGS_CHECK_IDENTITY)) {
+			    (pd[port].flags & PD_FLAGS_CHECK_IDENTITY)) {
 				pd_send_vdm(port, USB_SID_PD,
 					    CMD_DISCOVER_IDENT, NULL, 0);
 				pd[port].flags &= ~PD_FLAGS_CHECK_IDENTITY;
 				break;
 			}
 
-			/*
-			 * Enter_USB if port partner and cable are
-			 * USB4 compatible.
-			 */
-			if (should_enter_usb4_mode(port)) {
-				pd_send_enter_usb(port, &timeout);
-				break;
-			}
-
 			/* Sent all messages, don't need to wake very often */
-			timeout = 200*MSEC;
+			timeout = 200 * MSEC;
 			break;
 		case PD_STATE_SNK_SWAP_INIT:
 			if (pd[port].last_state != pd[port].task_state) {
 				res = send_control(port, PD_CTRL_PR_SWAP);
 				if (res < 0) {
-					timeout = 10*MSEC;
+					timeout = 10 * MSEC;
 					/*
 					 * If failed to get goodCRC, send
 					 * soft reset, otherwise ignore
 					 * failure.
 					 */
-					set_state(port, res == -1 ?
-						   PD_STATE_SOFT_RESET :
-						   PD_STATE_SNK_READY);
+					set_state(port,
+						  res == -1 ?
+							  PD_STATE_SOFT_RESET :
+							  PD_STATE_SNK_READY);
 					break;
 				}
 				/* Wait for accept or reject */
 				set_state_timeout(port,
 						  get_time().val +
-						  PD_T_SENDER_RESPONSE,
+							  PD_T_SENDER_RESPONSE,
 						  PD_STATE_SNK_READY);
 			}
 			break;
@@ -4397,19 +4197,18 @@ void pd_task(void *u)
 			pd_set_input_current_limit(port, 0, 0);
 #ifdef CONFIG_CHARGE_MANAGER
 			typec_set_input_current_limit(port, 0, 0);
-			charge_manager_set_ceil(port,
-						CEIL_REQUESTOR_PD,
+			charge_manager_set_ceil(port, CEIL_REQUESTOR_PD,
 						CHARGE_CEIL_NONE);
 #endif
 			set_state(port, PD_STATE_SNK_SWAP_SRC_DISABLE);
-			timeout = 10*MSEC;
+			timeout = 10 * MSEC;
 			break;
 		case PD_STATE_SNK_SWAP_SRC_DISABLE:
 			/* Wait for PS_RDY */
 			if (pd[port].last_state != pd[port].task_state)
 				set_state_timeout(port,
 						  get_time().val +
-						  PD_T_PS_SOURCE_OFF,
+							  PD_T_PS_SOURCE_OFF,
 						  PD_STATE_HARD_RESET_SEND);
 			break;
 		case PD_STATE_SNK_SWAP_STANDBY:
@@ -4419,7 +4218,7 @@ void pd_task(void *u)
 				if (pd_set_power_supply_ready(port)) {
 					/* Restore Rd */
 					tcpm_set_cc(port, TYPEC_CC_RD);
-					timeout = 10*MSEC;
+					timeout = 10 * MSEC;
 					set_state(port,
 						  PD_STATE_SNK_DISCONNECTED);
 					break;
@@ -4428,7 +4227,7 @@ void pd_task(void *u)
 				set_state_timeout(
 					port,
 					get_time().val +
-					PD_POWER_SUPPLY_TURN_ON_DELAY,
+						PD_POWER_SUPPLY_TURN_ON_DELAY,
 					PD_STATE_SNK_SWAP_COMPLETE);
 			}
 			break;
@@ -4445,34 +4244,36 @@ void pd_task(void *u)
 			}
 
 			/* Don't send GET_SINK_CAP on swap */
-			snk_cap_count = PD_SNK_CAP_RETRIES+1;
+			snk_cap_count = PD_SNK_CAP_RETRIES + 1;
 			caps_count = 0;
 			pd[port].msg_id = 0;
 			pd_set_power_role(port, PD_ROLE_SOURCE);
 			pd_update_roles(port);
 			set_state(port, PD_STATE_SRC_DISCOVERY);
-			timeout = 10*MSEC;
+			timeout = 10 * MSEC;
 			break;
 #ifdef CONFIG_USBC_VCONN_SWAP
 		case PD_STATE_VCONN_SWAP_SEND:
 			if (pd[port].last_state != pd[port].task_state) {
 				res = send_control(port, PD_CTRL_VCONN_SWAP);
 				if (res < 0) {
-					timeout = 10*MSEC;
+					timeout = 10 * MSEC;
 					/*
 					 * If failed to get goodCRC, send
 					 * soft reset, otherwise ignore
 					 * failure.
 					 */
-					set_state(port, res == -1 ?
-						   PD_STATE_SOFT_RESET :
-						   READY_RETURN_STATE(port));
+					set_state(port,
+						  res == -1 ?
+							  PD_STATE_SOFT_RESET :
+							  READY_RETURN_STATE(
+								  port));
 					break;
 				}
 				/* Wait for accept or reject */
 				set_state_timeout(port,
 						  get_time().val +
-						  PD_T_SENDER_RESPONSE,
+							  PD_T_SENDER_RESPONSE,
 						  READY_RETURN_STATE(port));
 			}
 			break;
@@ -4481,12 +4282,14 @@ void pd_task(void *u)
 				if (!(pd[port].flags & PD_FLAGS_VCONN_ON)) {
 					/* Turn VCONN on and wait for it */
 					set_vconn(port, 1);
-					set_state_timeout(port,
+					set_state_timeout(
+						port,
 						get_time().val +
-						CONFIG_USBC_VCONN_SWAP_DELAY_US,
+							CONFIG_USBC_VCONN_SWAP_DELAY_US,
 						PD_STATE_VCONN_SWAP_READY);
 				} else {
-					set_state_timeout(port,
+					set_state_timeout(
+						port,
 						get_time().val +
 							PD_T_VCONN_SOURCE_ON,
 						READY_RETURN_STATE(port));
@@ -4498,29 +4301,30 @@ void pd_task(void *u)
 				if (!(pd[port].flags & PD_FLAGS_VCONN_ON)) {
 					/* VCONN is now on, send PS_RDY */
 					pd_set_vconn_role(port,
-							PD_ROLE_VCONN_ON);
+							  PD_ROLE_VCONN_ON);
 					res = send_control(port,
-							PD_CTRL_PS_RDY);
+							   PD_CTRL_PS_RDY);
 					if (res == -1) {
-						timeout = 10*MSEC;
+						timeout = 10 * MSEC;
 						/*
 						 * If failed to get goodCRC,
 						 * send soft reset
 						 */
 						set_state(port,
-							PD_STATE_SOFT_RESET);
+							  PD_STATE_SOFT_RESET);
 						break;
 					}
 					set_state(port,
-						READY_RETURN_STATE(port));
+						  READY_RETURN_STATE(port));
 				} else {
 					/* Turn VCONN off and wait for it */
 					set_vconn(port, 0);
 					pd_set_vconn_role(port,
-							PD_ROLE_VCONN_OFF);
-					set_state_timeout(port,
+							  PD_ROLE_VCONN_OFF);
+					set_state_timeout(
+						port,
 						get_time().val +
-						CONFIG_USBC_VCONN_SWAP_DELAY_US,
+							CONFIG_USBC_VCONN_SWAP_DELAY_US,
 						READY_RETURN_STATE(port));
 				}
 			}
@@ -4538,14 +4342,14 @@ void pd_task(void *u)
 				if (res < 0) {
 					set_state(port,
 						  PD_STATE_HARD_RESET_SEND);
-					timeout = 5*MSEC;
+					timeout = 5 * MSEC;
 					break;
 				}
 
-				set_state_timeout(
-					port,
-					get_time().val + PD_T_SENDER_RESPONSE,
-					PD_STATE_HARD_RESET_SEND);
+				set_state_timeout(port,
+						  get_time().val +
+							  PD_T_SENDER_RESPONSE,
+						  PD_STATE_HARD_RESET_SEND);
 			}
 			break;
 		case PD_STATE_HARD_RESET_SEND:
@@ -4577,7 +4381,7 @@ void pd_task(void *u)
 				break;
 
 			if (pd_transmit(port, TCPCI_MSG_TX_HARD_RESET, 0, NULL,
-				AMS_START) < 0) {
+					AMS_START) < 0) {
 				/*
 				 * likely a non-idle channel
 				 * TCPCI r2.0 v1.0 4.4.15:
@@ -4614,7 +4418,8 @@ void pd_task(void *u)
 			 */
 			if (pd[port].power_role == PD_ROLE_SOURCE) {
 				set_state_timeout(port,
-					get_time().val + PD_T_PS_HARD_RESET,
+						  get_time().val +
+							  PD_T_PS_HARD_RESET,
 						  PD_STATE_HARD_RESET_EXECUTE);
 			} else {
 				set_state(port, PD_STATE_HARD_RESET_EXECUTE);
@@ -4633,32 +4438,31 @@ void pd_task(void *u)
 
 			/* reset our own state machine */
 			pd_execute_hard_reset(port);
-			timeout = 10*MSEC;
+			timeout = 10 * MSEC;
 			break;
 #ifdef CONFIG_COMMON_RUNTIME
 		case PD_STATE_BIST_RX:
 			send_bist_cmd(port);
 			/* Delay at least enough for partner to finish BIST */
-			timeout = PD_T_BIST_RECEIVE + 20*MSEC;
+			timeout = PD_T_BIST_RECEIVE + 20 * MSEC;
 			/* Set to appropriate port disconnected state */
-			set_state(port, DUAL_ROLE_IF_ELSE(port,
-						PD_STATE_SNK_DISCONNECTED,
+			set_state(port, DUAL_ROLE_IF_ELSE(
+						port, PD_STATE_SNK_DISCONNECTED,
 						PD_STATE_SRC_DISCONNECTED));
 			break;
 		case PD_STATE_BIST_TX:
 			pd_transmit(port, TCPCI_MSG_TX_BIST_MODE_2, 0, NULL,
 				    AMS_START);
 			/* Delay at least enough to finish sending BIST */
-			timeout = PD_T_BIST_TRANSMIT + 20*MSEC;
+			timeout = PD_T_BIST_TRANSMIT + 20 * MSEC;
 			/* Set to appropriate port disconnected state */
-			set_state(port, DUAL_ROLE_IF_ELSE(port,
-						PD_STATE_SNK_DISCONNECTED,
+			set_state(port, DUAL_ROLE_IF_ELSE(
+						port, PD_STATE_SNK_DISCONNECTED,
 						PD_STATE_SRC_DISCONNECTED));
 			break;
 #endif
 #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-		case PD_STATE_DRP_AUTO_TOGGLE:
-		{
+		case PD_STATE_DRP_AUTO_TOGGLE: {
 			enum pd_drp_next_states next_state;
 
 			assert(auto_toggle_supported);
@@ -4701,10 +4505,8 @@ void pd_task(void *u)
 			tcpm_get_cc(port, &cc1, &cc2);
 
 			next_state = drp_auto_toggle_next_state(
-						&pd[port].drp_sink_time,
-						pd[port].power_role,
-						drp_state[port],
-						cc1, cc2, false);
+				&pd[port].drp_sink_time, pd[port].power_role,
+				drp_state[port], cc1, cc2, false);
 
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
 			/*
@@ -4718,7 +4520,7 @@ void pd_task(void *u)
 #endif
 			if (next_state == DRP_TC_DEFAULT) {
 				if (PD_DEFAULT_STATE(port) ==
-						PD_STATE_SNK_DISCONNECTED)
+				    PD_STATE_SNK_DISCONNECTED)
 					next_state = DRP_TC_UNATTACHED_SNK;
 				else
 					next_state = DRP_TC_UNATTACHED_SRC;
@@ -4737,7 +4539,7 @@ void pd_task(void *u)
 
 				tcpm_set_cc(port, TYPEC_CC_RD);
 				pd_set_power_role(port, PD_ROLE_SINK);
-				timeout = 2*MSEC;
+				timeout = 2 * MSEC;
 				set_state(port, PD_STATE_SNK_DISCONNECTED);
 			} else if (next_state == DRP_TC_UNATTACHED_SRC) {
 				/*
@@ -4752,7 +4554,7 @@ void pd_task(void *u)
 
 				tcpm_set_cc(port, TYPEC_CC_RP);
 				pd_set_power_role(port, PD_ROLE_SOURCE);
-				timeout = 2*MSEC;
+				timeout = 2 * MSEC;
 				set_state(port, PD_STATE_SRC_DISCONNECTED);
 			} else {
 				/*
@@ -4767,13 +4569,6 @@ void pd_task(void *u)
 			break;
 		}
 #endif
-		case PD_STATE_ENTER_USB:
-			if (pd[port].last_state != pd[port].task_state) {
-				set_state_timeout(port,
-					get_time().val + PD_T_SENDER_RESPONSE,
-					READY_RETURN_STATE(port));
-			}
-			break;
 		default:
 			break;
 		}
@@ -4789,7 +4584,8 @@ void pd_task(void *u)
 			if (now.val >= pd[port].timeout) {
 				set_state(port, pd[port].timeout_state);
 				/* On a state timeout, run next state soon */
-				timeout = timeout < 10*MSEC ? timeout : 10*MSEC;
+				timeout = timeout < 10 * MSEC ? timeout :
+								10 * MSEC;
 			} else if (pd[port].timeout - now.val < timeout) {
 				timeout = pd[port].timeout - now.val;
 			}
@@ -4836,7 +4632,7 @@ void pd_task(void *u)
 			if (cc1 == TYPEC_CC_VOLT_OPEN) {
 				set_state(port, PD_STATE_SRC_DISCONNECTED);
 				/* Debouncing */
-				timeout = 10*MSEC;
+				timeout = 10 * MSEC;
 #ifdef CONFIG_USB_PD_DUAL_ROLE
 				/*
 				 * If Try.SRC is configured, then ATTACHED_SRC
@@ -4848,8 +4644,8 @@ void pd_task(void *u)
 					pd_set_power_role(port, PD_ROLE_SINK);
 					tcpm_set_cc(port, TYPEC_CC_RD);
 					/* Set timer for TryWait.SNK state */
-					pd[port].try_src_marker = get_time().val
-						+ PD_T_DEBOUNCE;
+					pd[port].try_src_marker =
+						get_time().val + PD_T_DEBOUNCE;
 					/* Advance to TryWait.SNK state */
 					set_state(port,
 						  PD_STATE_SNK_DISCONNECTED);
@@ -4874,7 +4670,7 @@ void pd_task(void *u)
 			/* Sink: detect disconnect by monitoring VBUS */
 			set_state(port, PD_STATE_SNK_DISCONNECTED);
 			/* set timeout small to reconnect fast */
-			timeout = 5*MSEC;
+			timeout = 5 * MSEC;
 		}
 #endif /* CONFIG_USB_PD_DUAL_ROLE */
 	}
@@ -4915,8 +4711,6 @@ static void pd_chipset_startup(void)
 	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
 		pd_set_dual_role_no_wakeup(i, PD_DRP_TOGGLE_OFF);
 		pd[i].flags |= PD_FLAGS_CHECK_IDENTITY;
-		/* Reset cable attributes and flags */
-		reset_pd_cable(i);
 		task_set_event(PD_PORT_TO_TASK_ID(i),
 			       PD_EVENT_POWER_STATE_CHANGE |
 				       PD_EVENT_UPDATE_DUAL_ROLE);
@@ -5013,16 +4807,16 @@ void pd_send_hpd(int port, enum hpd_event hpd)
 	if (!opos)
 		return;
 
-	data[0] = VDO_DP_STATUS((hpd == hpd_irq),  /* IRQ_HPD */
-				(hpd != hpd_low),  /* HPD_HI|LOW */
-				0,		      /* request exit DP */
-				0,		      /* request exit USB */
-				0,		      /* MF pref */
-				1,                    /* enabled */
-				0,		      /* power low */
+	data[0] = VDO_DP_STATUS((hpd == hpd_irq), /* IRQ_HPD */
+				(hpd != hpd_low), /* HPD_HI|LOW */
+				0, /* request exit DP */
+				0, /* request exit USB */
+				0, /* MF pref */
+				1, /* enabled */
+				0, /* power low */
 				0x2);
-	pd_send_vdm(port, USB_SID_DISPLAYPORT,
-		    VDO_OPOS(opos) | CMD_ATTENTION, data, 1);
+	pd_send_vdm(port, USB_SID_DISPLAYPORT, VDO_OPOS(opos) | CMD_ATTENTION,
+		    data, 1);
 	/* Wait until VDM is done. */
 	while (pd[0].vdm_state > 0)
 		task_wait_event(USB_PD_RX_TMOUT_US *
@@ -5037,15 +4831,15 @@ int pd_fetch_acc_log_entry(int port)
 	/* Cannot send a VDM now, the host should retry */
 	if (pd[port].vdm_state > 0)
 		return pd[port].vdm_state == VDM_STATE_BUSY ?
-				EC_RES_BUSY : EC_RES_UNAVAILABLE;
+			       EC_RES_BUSY :
+			       EC_RES_UNAVAILABLE;
 
 	pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_GET_LOG, NULL, 0);
-	timeout.val = get_time().val + 75*MSEC;
+	timeout.val = get_time().val + 75 * MSEC;
 
 	/* Wait until VDM is done */
-	while ((pd[port].vdm_state > 0) &&
-	       (get_time().val < timeout.val))
-		task_wait_event(10*MSEC);
+	while ((pd[port].vdm_state > 0) && (get_time().val < timeout.val))
+		task_wait_event(10 * MSEC);
 
 	if (pd[port].vdm_state > 0)
 		return EC_RES_TIMEOUT;
@@ -5096,7 +4890,7 @@ void pd_update_contract(int port)
 
 #endif /* CONFIG_USB_PD_DUAL_ROLE */
 
-static int command_pd(int argc, char **argv)
+static int command_pd(int argc, const char **argv)
 {
 	int port;
 	char *e;
@@ -5119,7 +4913,6 @@ static int command_pd(int argc, char **argv)
 
 		return EC_SUCCESS;
 	}
-
 #ifdef CONFIG_CMD_PD
 #ifdef CONFIG_CMD_PD_DEV_DUMP_INFO
 	else if (!strncasecmp(argv[1], "rwhashtable", 3)) {
@@ -5234,8 +5027,8 @@ static int command_pd(int argc, char **argv)
 		}
 
 		ccprintf("Pings %s\n",
-			 (pd[port].flags & PD_FLAGS_PING_ENABLED) ?
-			 "on" : "off");
+			 (pd[port].flags & PD_FLAGS_PING_ENABLED) ? "on" :
+								    "off");
 	} else if (!strncasecmp(argv[2], "vdm", 3)) {
 		if (argc < 4)
 			return EC_ERROR_PARAM_COUNT;
@@ -5250,11 +5043,11 @@ static int command_pd(int argc, char **argv)
 			pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_PING_ENABLE,
 				    &enable, 1);
 		} else if (!strncasecmp(argv[3], "curr", 4)) {
-			pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_CURRENT,
-				    NULL, 0);
+			pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_CURRENT, NULL,
+				    0);
 		} else if (!strncasecmp(argv[3], "vers", 4)) {
-			pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_VERSION,
-				    NULL, 0);
+			pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_VERSION, NULL,
+				    0);
 		} else {
 			return EC_ERROR_PARAM_COUNT;
 		}
@@ -5293,8 +5086,7 @@ static int command_pd(int argc, char **argv)
 			else if (!strcasecmp(argv[3], "sink"))
 				pd_set_dual_role(port, PD_DRP_FORCE_SINK);
 			else if (!strcasecmp(argv[3], "source"))
-				pd_set_dual_role(port,
-					PD_DRP_FORCE_SOURCE);
+				pd_set_dual_role(port, PD_DRP_FORCE_SOURCE);
 			else
 				return EC_ERROR_PARAM4;
 		}
@@ -5302,17 +5094,17 @@ static int command_pd(int argc, char **argv)
 #endif
 	} else
 #endif
-	if (!strncasecmp(argv[2], "state", 5)) {
+		if (!strncasecmp(argv[2], "state", 5)) {
 		ccprintf("Port C%d CC%d, %s - Role: %s-%s%s "
 			 "State: %d(%s), Flags: 0x%04x\n",
-			port, pd[port].polarity + 1,
-			pd_comm_is_enabled(port) ? "Ena" : "Dis",
-			pd[port].power_role == PD_ROLE_SOURCE ? "SRC" : "SNK",
-			pd[port].data_role == PD_ROLE_DFP ? "DFP" : "UFP",
-			(pd[port].flags & PD_FLAGS_VCONN_ON) ? "-VC" : "",
-			pd[port].task_state,
-			debug_level > 0 ? pd_get_task_state_name(port) : "",
-			pd[port].flags);
+			 port, pd[port].polarity + 1,
+			 pd_comm_is_enabled(port) ? "Ena" : "Dis",
+			 pd[port].power_role == PD_ROLE_SOURCE ? "SRC" : "SNK",
+			 pd[port].data_role == PD_ROLE_DFP ? "DFP" : "UFP",
+			 (pd[port].flags & PD_FLAGS_VCONN_ON) ? "-VC" : "",
+			 pd[port].task_state,
+			 debug_level > 0 ? pd_get_task_state_name(port) : "",
+			 pd[port].flags);
 	} else {
 		return EC_ERROR_PARAM1;
 	}
@@ -5360,9 +5152,8 @@ static enum ec_status hc_remote_flash(struct host_cmd_handler_args *args)
 	if (p->size + sizeof(*p) > args->params_size)
 		return EC_RES_INVALID_PARAM;
 
-#if defined(CONFIG_BATTERY) && \
-	(defined(CONFIG_BATTERY_PRESENT_CUSTOM) ||	\
-	 defined(CONFIG_BATTERY_PRESENT_GPIO))
+#if defined(CONFIG_BATTERY) && (defined(CONFIG_BATTERY_PRESENT_CUSTOM) || \
+				defined(CONFIG_BATTERY_PRESENT_GPIO))
 	/*
 	 * Do not allow PD firmware update if no battery and this port
 	 * is sinking power, because we will lose power.
@@ -5400,7 +5191,7 @@ static enum ec_status hc_remote_flash(struct host_cmd_handler_args *args)
 
 	case USB_PD_FW_ERASE_SIG:
 		pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_ERASE_SIG, NULL, 0);
-		timeout.val = get_time().val + 500*MSEC;
+		timeout.val = get_time().val + 500 * MSEC;
 		break;
 
 	case USB_PD_FW_FLASH_WRITE:
@@ -5412,12 +5203,12 @@ static enum ec_status hc_remote_flash(struct host_cmd_handler_args *args)
 		for (i = 0; i < size; i += VDO_MAX_SIZE - 1) {
 			pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_FLASH_WRITE,
 				    data + i, MIN(size - i, VDO_MAX_SIZE - 1));
-			timeout.val = get_time().val + 500*MSEC;
+			timeout.val = get_time().val + 500 * MSEC;
 
 			/* Wait until VDM is done */
 			while ((pd[port].vdm_state > 0) &&
 			       (get_time().val < timeout.val))
-				task_wait_event(10*MSEC);
+				task_wait_event(10 * MSEC);
 
 			if (pd[port].vdm_state > 0)
 				return EC_RES_TIMEOUT;
@@ -5431,7 +5222,7 @@ static enum ec_status hc_remote_flash(struct host_cmd_handler_args *args)
 
 	/* Wait until VDM is done or timeout */
 	while ((pd[port].vdm_state > 0) && (get_time().val < timeout.val))
-		task_wait_event(50*MSEC);
+		task_wait_event(50 * MSEC);
 
 	if ((pd[port].vdm_state > 0) ||
 	    (pd[port].vdm_state == VDM_STATE_ERR_TMOUT))
@@ -5441,12 +5232,8 @@ static enum ec_status hc_remote_flash(struct host_cmd_handler_args *args)
 
 	return rv;
 }
-DECLARE_HOST_COMMAND(EC_CMD_USB_PD_FW_UPDATE,
-		     hc_remote_flash,
-		     EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_USB_PD_FW_UPDATE, hc_remote_flash, EC_VER_MASK(0));
 #endif /* CONFIG_HOSTCMD_FLASHPD */
 
 #endif /* HAS_TASK_HOSTCMD */
-
-
 #endif /* CONFIG_COMMON_RUNTIME */
diff --git a/common/usb_pd_tcpc.c b/common/usb_pd_tcpc.c
index 1aaee29abc..c8010a5005 100644
--- a/common/usb_pd_tcpc.c
+++ b/common/usb_pd_tcpc.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,8 +24,8 @@
 #include "usb_pd_tcpm.h"
 
 #ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 /*
  * Debug log level - higher number == more log
@@ -45,93 +45,93 @@ static const int debug_level;
 #endif
 
 /* Encode 5 bits using Biphase Mark Coding */
-#define BMC(x)   ((x &  1 ? 0x001 : 0x3FF) \
-		^ (x &  2 ? 0x004 : 0x3FC) \
-		^ (x &  4 ? 0x010 : 0x3F0) \
-		^ (x &  8 ? 0x040 : 0x3C0) \
-		^ (x & 16 ? 0x100 : 0x300))
+#define BMC(x)                                               \
+	((x & 1 ? 0x001 : 0x3FF) ^ (x & 2 ? 0x004 : 0x3FC) ^ \
+	 (x & 4 ? 0x010 : 0x3F0) ^ (x & 8 ? 0x040 : 0x3C0) ^ \
+	 (x & 16 ? 0x100 : 0x300))
 
 /* 4b/5b + Bimark Phase encoding */
 static const uint16_t bmc4b5b[] = {
-/* 0 = 0000 */ BMC(0x1E) /* 11110 */,
-/* 1 = 0001 */ BMC(0x09) /* 01001 */,
-/* 2 = 0010 */ BMC(0x14) /* 10100 */,
-/* 3 = 0011 */ BMC(0x15) /* 10101 */,
-/* 4 = 0100 */ BMC(0x0A) /* 01010 */,
-/* 5 = 0101 */ BMC(0x0B) /* 01011 */,
-/* 6 = 0110 */ BMC(0x0E) /* 01110 */,
-/* 7 = 0111 */ BMC(0x0F) /* 01111 */,
-/* 8 = 1000 */ BMC(0x12) /* 10010 */,
-/* 9 = 1001 */ BMC(0x13) /* 10011 */,
-/* A = 1010 */ BMC(0x16) /* 10110 */,
-/* B = 1011 */ BMC(0x17) /* 10111 */,
-/* C = 1100 */ BMC(0x1A) /* 11010 */,
-/* D = 1101 */ BMC(0x1B) /* 11011 */,
-/* E = 1110 */ BMC(0x1C) /* 11100 */,
-/* F = 1111 */ BMC(0x1D) /* 11101 */,
-/* Sync-1      K-code       11000 Startsynch #1 */
-/* Sync-2      K-code       10001 Startsynch #2 */
-/* RST-1       K-code       00111 Hard Reset #1 */
-/* RST-2       K-code       11001 Hard Reset #2 */
-/* EOP         K-code       01101 EOP End Of Packet */
-/* Reserved    Error        00000 */
-/* Reserved    Error        00001 */
-/* Reserved    Error        00010 */
-/* Reserved    Error        00011 */
-/* Reserved    Error        00100 */
-/* Reserved    Error        00101 */
-/* Reserved    Error        00110 */
-/* Reserved    Error        01000 */
-/* Reserved    Error        01100 */
-/* Reserved    Error        10000 */
-/* Reserved    Error        11111 */
+	/* 0 = 0000 */ BMC(0x1E) /* 11110 */,
+	/* 1 = 0001 */ BMC(0x09) /* 01001 */,
+	/* 2 = 0010 */ BMC(0x14) /* 10100 */,
+	/* 3 = 0011 */ BMC(0x15) /* 10101 */,
+	/* 4 = 0100 */ BMC(0x0A) /* 01010 */,
+	/* 5 = 0101 */ BMC(0x0B) /* 01011 */,
+	/* 6 = 0110 */ BMC(0x0E) /* 01110 */,
+	/* 7 = 0111 */ BMC(0x0F) /* 01111 */,
+	/* 8 = 1000 */ BMC(0x12) /* 10010 */,
+	/* 9 = 1001 */ BMC(0x13) /* 10011 */,
+	/* A = 1010 */ BMC(0x16) /* 10110 */,
+	/* B = 1011 */ BMC(0x17) /* 10111 */,
+	/* C = 1100 */ BMC(0x1A) /* 11010 */,
+	/* D = 1101 */ BMC(0x1B) /* 11011 */,
+	/* E = 1110 */ BMC(0x1C) /* 11100 */,
+	/* F = 1111 */ BMC(0x1D) /* 11101 */,
+	/* Sync-1      K-code       11000 Startsynch #1 */
+	/* Sync-2      K-code       10001 Startsynch #2 */
+	/* RST-1       K-code       00111 Hard Reset #1 */
+	/* RST-2       K-code       11001 Hard Reset #2 */
+	/* EOP         K-code       01101 EOP End Of Packet */
+	/* Reserved    Error        00000 */
+	/* Reserved    Error        00001 */
+	/* Reserved    Error        00010 */
+	/* Reserved    Error        00011 */
+	/* Reserved    Error        00100 */
+	/* Reserved    Error        00101 */
+	/* Reserved    Error        00110 */
+	/* Reserved    Error        01000 */
+	/* Reserved    Error        01100 */
+	/* Reserved    Error        10000 */
+	/* Reserved    Error        11111 */
 };
 
 static const uint8_t dec4b5b[] = {
-/* Error    */ 0x10 /* 00000 */,
-/* Error    */ 0x10 /* 00001 */,
-/* Error    */ 0x10 /* 00010 */,
-/* Error    */ 0x10 /* 00011 */,
-/* Error    */ 0x10 /* 00100 */,
-/* Error    */ 0x10 /* 00101 */,
-/* Error    */ 0x10 /* 00110 */,
-/* RST-1    */ 0x13 /* 00111 K-code: Hard Reset #1 */,
-/* Error    */ 0x10 /* 01000 */,
-/* 1 = 0001 */ 0x01 /* 01001 */,
-/* 4 = 0100 */ 0x04 /* 01010 */,
-/* 5 = 0101 */ 0x05 /* 01011 */,
-/* Error    */ 0x10 /* 01100 */,
-/* EOP      */ 0x15 /* 01101 K-code: EOP End Of Packet */,
-/* 6 = 0110 */ 0x06 /* 01110 */,
-/* 7 = 0111 */ 0x07 /* 01111 */,
-/* Error    */ 0x10 /* 10000 */,
-/* Sync-2   */ 0x12 /* 10001 K-code: Startsynch #2 */,
-/* 8 = 1000 */ 0x08 /* 10010 */,
-/* 9 = 1001 */ 0x09 /* 10011 */,
-/* 2 = 0010 */ 0x02 /* 10100 */,
-/* 3 = 0011 */ 0x03 /* 10101 */,
-/* A = 1010 */ 0x0A /* 10110 */,
-/* B = 1011 */ 0x0B /* 10111 */,
-/* Sync-1   */ 0x11 /* 11000 K-code: Startsynch #1 */,
-/* RST-2    */ 0x14 /* 11001 K-code: Hard Reset #2 */,
-/* C = 1100 */ 0x0C /* 11010 */,
-/* D = 1101 */ 0x0D /* 11011 */,
-/* E = 1110 */ 0x0E /* 11100 */,
-/* F = 1111 */ 0x0F /* 11101 */,
-/* 0 = 0000 */ 0x00 /* 11110 */,
-/* Error    */ 0x10 /* 11111 */,
+	/* Error    */ 0x10 /* 00000 */,
+	/* Error    */ 0x10 /* 00001 */,
+	/* Error    */ 0x10 /* 00010 */,
+	/* Error    */ 0x10 /* 00011 */,
+	/* Error    */ 0x10 /* 00100 */,
+	/* Error    */ 0x10 /* 00101 */,
+	/* Error    */ 0x10 /* 00110 */,
+	/* RST-1    */ 0x13 /* 00111 K-code: Hard Reset #1 */,
+	/* Error    */ 0x10 /* 01000 */,
+	/* 1 = 0001 */ 0x01 /* 01001 */,
+	/* 4 = 0100 */ 0x04 /* 01010 */,
+	/* 5 = 0101 */ 0x05 /* 01011 */,
+	/* Error    */ 0x10 /* 01100 */,
+	/* EOP      */ 0x15 /* 01101 K-code: EOP End Of Packet */,
+	/* 6 = 0110 */ 0x06 /* 01110 */,
+	/* 7 = 0111 */ 0x07 /* 01111 */,
+	/* Error    */ 0x10 /* 10000 */,
+	/* Sync-2   */ 0x12 /* 10001 K-code: Startsynch #2 */,
+	/* 8 = 1000 */ 0x08 /* 10010 */,
+	/* 9 = 1001 */ 0x09 /* 10011 */,
+	/* 2 = 0010 */ 0x02 /* 10100 */,
+	/* 3 = 0011 */ 0x03 /* 10101 */,
+	/* A = 1010 */ 0x0A /* 10110 */,
+	/* B = 1011 */ 0x0B /* 10111 */,
+	/* Sync-1   */ 0x11 /* 11000 K-code: Startsynch #1 */,
+	/* RST-2    */ 0x14 /* 11001 K-code: Hard Reset #2 */,
+	/* C = 1100 */ 0x0C /* 11010 */,
+	/* D = 1101 */ 0x0D /* 11011 */,
+	/* E = 1110 */ 0x0E /* 11100 */,
+	/* F = 1111 */ 0x0F /* 11101 */,
+	/* 0 = 0000 */ 0x00 /* 11110 */,
+	/* Error    */ 0x10 /* 11111 */,
 };
 
 /* Start of Packet sequence : three Sync-1 K-codes, then one Sync-2 K-code */
-#define PD_SOP (PD_SYNC1 | (PD_SYNC1<<5) | (PD_SYNC1<<10) | (PD_SYNC2<<15))
-#define PD_SOP_PRIME	(PD_SYNC1 | (PD_SYNC1<<5) | \
-			(PD_SYNC3<<10) | (PD_SYNC3<<15))
-#define PD_SOP_PRIME_PRIME	(PD_SYNC1 | (PD_SYNC3<<5) | \
-				(PD_SYNC1<<10) | (PD_SYNC3<<15))
+#define PD_SOP \
+	(PD_SYNC1 | (PD_SYNC1 << 5) | (PD_SYNC1 << 10) | (PD_SYNC2 << 15))
+#define PD_SOP_PRIME \
+	(PD_SYNC1 | (PD_SYNC1 << 5) | (PD_SYNC3 << 10) | (PD_SYNC3 << 15))
+#define PD_SOP_PRIME_PRIME \
+	(PD_SYNC1 | (PD_SYNC3 << 5) | (PD_SYNC1 << 10) | (PD_SYNC3 << 15))
 
 /* Hard Reset sequence : three RST-1 K-codes, then one RST-2 K-code */
-#define PD_HARD_RESET (PD_RST1 | (PD_RST1 << 5) |\
-		      (PD_RST1 << 10) | (PD_RST2 << 15))
+#define PD_HARD_RESET \
+	(PD_RST1 | (PD_RST1 << 5) | (PD_RST1 << 10) | (PD_RST2 << 15))
 
 /*
  * Polarity based on 'DFP Perspective' (see table USB Type-C Cable and Connector
@@ -159,11 +159,11 @@ static const uint8_t dec4b5b[] = {
 #endif
 
 #ifndef CC_RA
-#define CC_RA(port, cc, sel)  (cc < PD_SRC_RD_THRESHOLD)
+#define CC_RA(port, cc, sel) (cc < PD_SRC_RD_THRESHOLD)
 #endif
 #define CC_RD(cc) ((cc >= PD_SRC_RD_THRESHOLD) && (cc < PD_SRC_VNC))
 #ifndef CC_NC
-#define CC_NC(port, cc, sel)  (cc >= PD_SRC_VNC)
+#define CC_NC(port, cc, sel) (cc >= PD_SRC_VNC)
 #endif
 
 /*
@@ -180,16 +180,16 @@ static const uint8_t dec4b5b[] = {
 #define PD_SNK_VA PD_SNK_VA_MV
 #endif
 
-#define CC_RP(cc)  (cc >= PD_SNK_VA)
+#define CC_RP(cc) (cc >= PD_SNK_VA)
 
 /*
  * Type C power source charge current limits are identified by their cc
  * voltage (set by selecting the proper Rd resistor). Any voltage below
  * TYPE_C_SRC_500_THRESHOLD will not be identified as a type C charger.
  */
-#define TYPE_C_SRC_500_THRESHOLD	PD_SRC_RD_THRESHOLD
-#define TYPE_C_SRC_1500_THRESHOLD	660  /* mV */
-#define TYPE_C_SRC_3000_THRESHOLD	1230 /* mV */
+#define TYPE_C_SRC_500_THRESHOLD PD_SRC_RD_THRESHOLD
+#define TYPE_C_SRC_1500_THRESHOLD 660 /* mV */
+#define TYPE_C_SRC_3000_THRESHOLD 1230 /* mV */
 
 /* Convert TCPC Alert register to index into pd.alert[] */
 #define ALERT_REG_TO_INDEX(reg) (reg - TCPC_REG_ALERT)
@@ -254,8 +254,8 @@ static struct pd_port_controller {
 #endif
 
 	/* Last received */
-	int rx_head[RX_BUFFER_SIZE+1];
-	uint32_t rx_payload[RX_BUFFER_SIZE+1][7];
+	int rx_head[RX_BUFFER_SIZE + 1];
+	uint32_t rx_payload[RX_BUFFER_SIZE + 1][7];
 	int rx_buf_head, rx_buf_tail;
 
 	/* Next transmit */
@@ -309,7 +309,7 @@ int encode_word(int port, int off, uint32_t val32)
 
 /* prepare a 4b/5b-encoded PD message to send */
 int prepare_message(int port, uint16_t header, uint8_t cnt,
-		   const uint32_t *data)
+		    const uint32_t *data)
 {
 	int off, i;
 	/* 64-bit preamble */
@@ -387,8 +387,8 @@ static int send_validate_message(int port, uint16_t header,
 	uint8_t expected_msg_id = PD_HEADER_ID(header);
 	uint8_t cnt = PD_HEADER_CNT(header);
 	int retries = PD_HEADER_TYPE(header) == PD_DATA_SOURCE_CAP ?
-				    0 :
-				    CONFIG_PD_RETRY_COUNT;
+			      0 :
+			      CONFIG_PD_RETRY_COUNT;
 
 	/* retry 3 times if we are not getting a valid answer */
 	for (r = 0; r <= retries; r++) {
@@ -464,7 +464,7 @@ static int send_validate_message(int port, uint16_t header,
 static void send_goodcrc(int port, int id)
 {
 	uint16_t header = PD_HEADER(PD_CTRL_GOOD_CRC, pd[port].power_role,
-			pd[port].data_role, id, 0, 0, 0);
+				    pd[port].data_role, id, 0, 0, 0);
 	int bit_len = prepare_message(port, header, 0, NULL);
 
 	if (pd_start_tx(port, pd[port].polarity, bit_len) < 0)
@@ -536,7 +536,7 @@ static void bist_mode_2_tx(int port)
 	 * build context buffer with 5 bytes, where the data is
 	 * alternating 1's and 0's.
 	 */
-	bit = pd_write_sym(port, 0,   BMC(0x15));
+	bit = pd_write_sym(port, 0, BMC(0x15));
 	bit = pd_write_sym(port, bit, BMC(0x0a));
 	bit = pd_write_sym(port, bit, BMC(0x15));
 	bit = pd_write_sym(port, bit, BMC(0x0a));
@@ -566,10 +566,9 @@ static inline int decode_short(int port, int off, uint16_t *val16)
 		dec4b5b[(w >> 15) & 0x1f], dec4b5b[(w >> 10) & 0x1f],
 		dec4b5b[(w >>  5) & 0x1f], dec4b5b[(w >>  0) & 0x1f]);
 #endif
-	*val16 = dec4b5b[w & 0x1f] |
-		(dec4b5b[(w >>  5) & 0x1f] << 4) |
-		(dec4b5b[(w >> 10) & 0x1f] << 8) |
-		(dec4b5b[(w >> 15) & 0x1f] << 12);
+	*val16 = dec4b5b[w & 0x1f] | (dec4b5b[(w >> 5) & 0x1f] << 4) |
+		 (dec4b5b[(w >> 10) & 0x1f] << 8) |
+		 (dec4b5b[(w >> 15) & 0x1f] << 12);
 	return end;
 }
 
@@ -674,7 +673,7 @@ int pd_analyze_rx(int port, uint32_t *payload)
 #else /* CONFIG_USB_VPD || CONFIG_USB_CTVPD */
 #ifdef CONFIG_USB_PD_DECODE_SOP
 		if (val == PD_SOP || val == PD_SOP_PRIME ||
-						val == PD_SOP_PRIME_PRIME)
+		    val == PD_SOP_PRIME_PRIME)
 			break;
 #else
 		if (val == PD_SOP) {
@@ -734,7 +733,7 @@ int pd_analyze_rx(int port, uint32_t *payload)
 
 	/* read payload data */
 	for (p = 0; p < cnt && bit > 0; p++) {
-		bit = decode_word(port, bit, payload+p);
+		bit = decode_word(port, bit, payload + p);
 		crc32_hash32(payload[p]);
 	}
 	ccrc = crc32_result();
@@ -801,7 +800,7 @@ static int cc_voltage_to_status(int port, int cc_volt, int cc_sel)
 			return TYPEC_CC_VOLT_RA;
 		else
 			return TYPEC_CC_VOLT_RD;
-	/* If we have a pull-down, then we are sink, check for Rp. */
+		/* If we have a pull-down, then we are sink, check for Rp. */
 	}
 #ifdef CONFIG_USB_PD_DUAL_ROLE
 	else if (pd[port].cc_pull == TYPEC_CC_RD) {
@@ -843,9 +842,8 @@ int tcpc_run(int port, int evt)
 	/* incoming packet ? */
 	if (pd_rx_started(port) && pd[port].rx_enabled) {
 		/* Get message and place at RX buffer head */
-		res = pd[port].rx_head[pd[port].rx_buf_head] =
-			pd_analyze_rx(port,
-				pd[port].rx_payload[pd[port].rx_buf_head]);
+		res = pd[port].rx_head[pd[port].rx_buf_head] = pd_analyze_rx(
+			port, pd[port].rx_payload[pd[port].rx_buf_head]);
 		pd_rx_complete(port);
 
 		/*
@@ -872,9 +870,8 @@ int tcpc_run(int port, int evt)
 #else
 		case TCPCI_MSG_SOP:
 #endif
-			res = send_validate_message(port,
-					pd[port].tx_head,
-					pd[port].tx_data);
+			res = send_validate_message(port, pd[port].tx_head,
+						    pd[port].tx_data);
 			break;
 		case TCPCI_MSG_TX_BIST_MODE_2:
 			bist_mode_2_tx(port);
@@ -929,11 +926,11 @@ int tcpc_run(int port, int evt)
 	 */
 	return (get_time().val >= pd[port].low_power_ts.val &&
 		pd[port].cc_pull == TYPEC_CC_RD &&
-		cc_is_open(pd[port].cc_status[0], pd[port].cc_status[1]))
-		       ? 200 * MSEC
-		       : 10 * MSEC;
+		cc_is_open(pd[port].cc_status[0], pd[port].cc_status[1])) ?
+		       200 * MSEC :
+		       10 * MSEC;
 #else
-	return 10*MSEC;
+	return 10 * MSEC;
 #endif
 }
 
@@ -941,7 +938,7 @@ int tcpc_run(int port, int evt)
 void pd_task(void *u)
 {
 	int port = TASK_ID_TO_PD_PORT(task_get_current());
-	int timeout = 10*MSEC;
+	int timeout = 10 * MSEC;
 	int evt;
 
 	/* initialize phy task */
@@ -1024,8 +1021,8 @@ int tcpc_set_cc(int port, int pull)
 	 * because we only want to go into low power mode when we are not
 	 * dual-role toggling.
 	 */
-	pd[port].low_power_ts.val = get_time().val +
-					2*(PD_T_DRP_SRC + PD_T_DRP_SNK);
+	pd[port].low_power_ts.val =
+		get_time().val + 2 * (PD_T_DRP_SRC + PD_T_DRP_SNK);
 #endif
 
 	/*
@@ -1047,7 +1044,7 @@ int tcpc_set_cc(int port, int pull)
 }
 
 int tcpc_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2)
+		enum tcpc_cc_voltage_status *cc2)
 {
 	*cc2 = pd[port].cc_status[1];
 	*cc1 = pd[port].cc_status[0];
@@ -1184,8 +1181,9 @@ void tcpc_init(int port)
 
 	/* Initialize physical layer */
 	pd_hw_init(port, PD_ROLE_DEFAULT(port));
-	pd[port].cc_pull = PD_ROLE_DEFAULT(port) ==
-		PD_ROLE_SOURCE ? TYPEC_CC_RP : TYPEC_CC_RD;
+	pd[port].cc_pull = PD_ROLE_DEFAULT(port) == PD_ROLE_SOURCE ?
+				   TYPEC_CC_RP :
+				   TYPEC_CC_RD;
 #ifdef TCPC_LOW_POWER
 	/* Don't use low power immediately after boot */
 	pd[port].low_power_ts.val = get_time().val + SECOND;
@@ -1196,16 +1194,15 @@ void tcpc_init(int port)
 
 	/* make initial readings of CC voltages */
 	for (i = 0; i < 2; i++) {
-		pd[port].cc_status[i] = cc_voltage_to_status(port,
-							     pd_adc_read(port, i),
-							     i);
+		pd[port].cc_status[i] =
+			cc_voltage_to_status(port, pd_adc_read(port, i), i);
 	}
 
 #ifdef CONFIG_USB_PD_TCPC_TRACK_VBUS
 #if CONFIG_USB_PD_PORT_MAX_COUNT >= 2
-	tcpc_set_power_status(port, !gpio_get_level(port ?
-			      GPIO_USB_C1_VBUS_WAKE_L :
-			      GPIO_USB_C0_VBUS_WAKE_L));
+	tcpc_set_power_status(port,
+			      !gpio_get_level(port ? GPIO_USB_C1_VBUS_WAKE_L :
+						     GPIO_USB_C0_VBUS_WAKE_L));
 #else
 	tcpc_set_power_status(port, !gpio_get_level(GPIO_USB_C0_VBUS_WAKE_L));
 #endif /* CONFIG_USB_PD_PORT_MAX_COUNT >= 2 */
@@ -1223,7 +1220,7 @@ void tcpc_init(int port)
 void pd_vbus_evt_p0(enum gpio_signal signal)
 {
 	tcpc_set_power_status(TASK_ID_TO_PD_PORT(TASK_ID_PD_C0),
-				 !gpio_get_level(GPIO_USB_C0_VBUS_WAKE_L));
+			      !gpio_get_level(GPIO_USB_C0_VBUS_WAKE_L));
 	task_wake(TASK_ID_PD_C0);
 }
 
@@ -1234,7 +1231,7 @@ void pd_vbus_evt_p1(enum gpio_signal signal)
 		return;
 
 	tcpc_set_power_status(TASK_ID_TO_PD_PORT(TASK_ID_PD_C1),
-				 !gpio_get_level(GPIO_USB_C1_VBUS_WAKE_L));
+			      !gpio_get_level(GPIO_USB_C1_VBUS_WAKE_L));
 	task_wake(TASK_ID_PD_C1);
 }
 #endif /* PD_PORT_COUNT >= 2 */
@@ -1277,8 +1274,8 @@ static void tcpc_i2c_write(int port, int reg, int len, uint8_t *payload)
 		tcpc_alert_mask_set(port, alert);
 		break;
 	case TCPC_REG_RX_DETECT:
-		tcpc_set_rx_enable(port, payload[1] &
-					 TCPC_REG_RX_DETECT_SOP_HRST_MASK);
+		tcpc_set_rx_enable(
+			port, payload[1] & TCPC_REG_RX_DETECT_SOP_HRST_MASK);
 		break;
 	case TCPC_REG_POWER_STATUS_MASK:
 		tcpc_set_power_status_mask(port, payload[1]);
@@ -1308,12 +1305,11 @@ static int tcpc_i2c_read(int port, int reg, uint8_t *payload)
 	case TCPC_REG_CC_STATUS:
 		tcpc_get_cc(port, &cc1, &cc2);
 		payload[0] = TCPC_REG_CC_STATUS_SET(
-				pd[port].cc_pull == TYPEC_CC_RD,
-				pd[port].cc_status[0], pd[port].cc_status[1]);
+			pd[port].cc_pull == TYPEC_CC_RD, pd[port].cc_status[0],
+			pd[port].cc_status[1]);
 		return 1;
 	case TCPC_REG_ROLE_CTRL:
-		payload[0] = TCPC_REG_ROLE_CTRL_SET(0, 0,
-						    pd[port].cc_pull,
+		payload[0] = TCPC_REG_ROLE_CTRL_SET(0, 0, pd[port].cc_pull,
 						    pd[port].cc_pull);
 		return 1;
 	case TCPC_REG_TCPC_CTRL:
@@ -1325,7 +1321,8 @@ static int tcpc_i2c_read(int port, int reg, uint8_t *payload)
 		return 1;
 	case TCPC_REG_RX_DETECT:
 		payload[0] = pd[port].rx_enabled ?
-				TCPC_REG_RX_DETECT_SOP_HRST_MASK : 0;
+				     TCPC_REG_RX_DETECT_SOP_HRST_MASK :
+				     0;
 		return 1;
 	case TCPC_REG_ALERT:
 		tcpc_alert_status(port, &alert);
@@ -1337,13 +1334,14 @@ static int tcpc_i2c_read(int port, int reg, uint8_t *payload)
 		payload[1] = (pd[port].alert_mask >> 8) & 0xff;
 		return 2;
 	case TCPC_REG_RX_BYTE_CNT:
-		payload[0] = 3 + 4 *
-			PD_HEADER_CNT(pd[port].rx_head[pd[port].rx_buf_tail]);
+		payload[0] =
+			3 + 4 * PD_HEADER_CNT(
+					pd[port].rx_head[pd[port].rx_buf_tail]);
 		return 1;
 	case TCPC_REG_RX_HDR:
 		payload[0] = pd[port].rx_head[pd[port].rx_buf_tail] & 0xff;
-		payload[1] =
-			(pd[port].rx_head[pd[port].rx_buf_tail] >> 8) & 0xff;
+		payload[1] = (pd[port].rx_head[pd[port].rx_buf_tail] >> 8) &
+			     0xff;
 		return 2;
 	case TCPC_REG_RX_DATA:
 		memcpy(payload, pd[port].rx_payload[pd[port].rx_buf_tail],
@@ -1408,7 +1406,7 @@ void tcpc_i2c_process(int read, int port, int len, uint8_t *payload,
 #endif
 
 #ifdef CONFIG_COMMON_RUNTIME
-static int command_tcpc(int argc, char **argv)
+static int command_tcpc(int argc, const char **argv)
 {
 	int port;
 	char *e;
@@ -1452,12 +1450,12 @@ static int command_tcpc(int argc, char **argv)
 	} else if (!strncasecmp(argv[2], "state", 5)) {
 		ccprintf("Port C%d, %s - CC:%d, CC0:%d, CC1:%d\n"
 			 "Alert: 0x%02x Mask: 0x%04x\n"
-			 "Power Status: 0x%02x Mask: 0x%02x\n", port,
-			 pd[port].rx_enabled ? "Ena" : "Dis",
-			 pd[port].cc_pull,
-			 pd[port].cc_status[0], pd[port].cc_status[1],
-			 pd[port].alert, pd[port].alert_mask,
-			 pd[port].power_status, pd[port].power_status_mask);
+			 "Power Status: 0x%02x Mask: 0x%02x\n",
+			 port, pd[port].rx_enabled ? "Ena" : "Dis",
+			 pd[port].cc_pull, pd[port].cc_status[0],
+			 pd[port].cc_status[1], pd[port].alert,
+			 pd[port].alert_mask, pd[port].power_status,
+			 pd[port].power_status_mask);
 	}
 
 	return EC_SUCCESS;
diff --git a/common/usb_port_power_dumb.c b/common/usb_port_power_dumb.c
index ea2d4eb668..10eca3ffb7 100644
--- a/common/usb_port_power_dumb.c
+++ b/common/usb_port_power_dumb.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,7 @@
 #include "util.h"
 
 #define CPUTS(outstr) cputs(CC_USBCHARGE, outstr)
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
 
 static uint8_t charge_mode[USB_PORT_COUNT];
 
@@ -75,20 +75,19 @@ usb_port_command_set_mode(struct host_cmd_handler_args *args)
 {
 	const struct ec_params_usb_charge_set_mode *p = args->params;
 
-	if (usb_charge_set_mode(p->usb_port_id, p->mode,
-		p->inhibit_charge) != EC_SUCCESS)
+	if (usb_charge_set_mode(p->usb_port_id, p->mode, p->inhibit_charge) !=
+	    EC_SUCCESS)
 		return EC_RES_ERROR;
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_USB_CHARGE_SET_MODE,
-		     usb_port_command_set_mode,
+DECLARE_HOST_COMMAND(EC_CMD_USB_CHARGE_SET_MODE, usb_port_command_set_mode,
 		     EC_VER_MASK(0));
 
 /*****************************************************************************/
 /* Console commands */
 
-static int command_set_mode(int argc, char **argv)
+static int command_set_mode(int argc, const char **argv)
 {
 	int port_id = -1;
 	int mode = -1;
@@ -108,18 +107,16 @@ static int command_set_mode(int argc, char **argv)
 		/* fallthrough */
 	case 1:
 		for (i = 0; i < USB_PORT_COUNT; i++)
-			ccprintf("Port %d: %s\n",
-				 i, charge_mode[i] ? "on" : "off");
+			ccprintf("Port %d: %s\n", i,
+				 charge_mode[i] ? "on" : "off");
 		return EC_SUCCESS;
 	}
 
 	return EC_ERROR_PARAM_COUNT;
 }
-DECLARE_CONSOLE_COMMAND(usbchargemode, command_set_mode,
-			"[<port> <on | off>]",
+DECLARE_CONSOLE_COMMAND(usbchargemode, command_set_mode, "[<port> <on | off>]",
 			"Set USB charge mode");
 
-
 /*****************************************************************************/
 /* Hooks */
 
@@ -135,10 +132,10 @@ static void usb_port_init(void)
 	const uint8_t *prev;
 	int version, size, i;
 
-	prev = (const uint8_t *)system_get_jump_tag(USB_SYSJUMP_TAG,
-						    &version, &size);
+	prev = (const uint8_t *)system_get_jump_tag(USB_SYSJUMP_TAG, &version,
+						    &size);
 	if (!prev || version != USB_HOOK_VERSION ||
-			size != sizeof(charge_mode)) {
+	    size != sizeof(charge_mode)) {
 		usb_port_all_ports_off();
 		return;
 	}
@@ -162,4 +159,4 @@ static void usb_port_shutdown(void)
 	usb_port_all_ports_off();
 }
 DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, usb_port_shutdown, HOOK_PRIO_DEFAULT);
-#endif  /* CONFIG_USB_PORT_POWER_DUMB_CUSTOM_HOOK */
+#endif /* CONFIG_USB_PORT_POWER_DUMB_CUSTOM_HOOK */
diff --git a/common/usb_port_power_smart.c b/common/usb_port_power_smart.c
index 3143bdf400..42fbc7dd64 100644
--- a/common/usb_port_power_smart.c
+++ b/common/usb_port_power_smart.c
@@ -1,10 +1,11 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* USB charging control module for Chrome EC */
 
+#include "builtin/assert.h"
 #include "chipset.h"
 #include "common.h"
 #include "console.h"
@@ -16,15 +17,15 @@
 #include "util.h"
 
 #define CPUTS(outstr) cputs(CC_USBCHARGE, outstr)
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
 
 #ifndef CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE
 #define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_SDP2
 #endif
 
 struct charge_mode_t {
-	uint8_t mode:7;
-	uint8_t inhibit_charging_in_suspend:1;
+	uint8_t mode : 7;
+	uint8_t inhibit_charging_in_suspend : 1;
 } __pack;
 
 static struct charge_mode_t charge_mode[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT];
@@ -34,7 +35,9 @@ static struct charge_mode_t charge_mode[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT];
  * If we only support CDP and SDP, the control signals are hard-wired so
  * there's nothing to do.  The only to do is set ILIM_SEL.
  */
-static void usb_charge_set_control_mode(int port_id, int mode) {}
+static void usb_charge_set_control_mode(int port_id, int mode)
+{
+}
 #else /* !defined(CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY) */
 static void usb_charge_set_control_mode(int port_id, int mode)
 {
@@ -74,7 +77,7 @@ static void usb_charge_set_ilim(int port_id, int sel)
 {
 	int ilim_sel;
 
-#if defined(CONFIG_USB_PORT_POWER_SMART_SIMPLE) ||	\
+#if defined(CONFIG_USB_PORT_POWER_SMART_SIMPLE) || \
 	defined(CONFIG_USB_PORT_POWER_SMART_INVERTED)
 	/* ILIM_SEL is inverted. */
 	sel = !sel;
@@ -142,7 +145,7 @@ int usb_charge_set_mode(int port_id, enum usb_charge_mode mode,
 /*****************************************************************************/
 /* Console commands */
 
-static int command_set_mode(int argc, char **argv)
+static int command_set_mode(int argc, const char **argv)
 {
 	int port_id = -1;
 	int mode = -1, inhibit_charge = 0;
@@ -152,7 +155,7 @@ static int command_set_mode(int argc, char **argv)
 	if (argc == 1) {
 		for (i = 0; i < CONFIG_USB_PORT_POWER_SMART_PORT_COUNT; i++)
 			ccprintf("Port %d: %d,%d\n", i, charge_mode[i].mode,
-				charge_mode[i].inhibit_charging_in_suspend);
+				 charge_mode[i].inhibit_charging_in_suspend);
 		return EC_SUCCESS;
 	}
 
@@ -188,14 +191,13 @@ usb_charge_command_set_mode(struct host_cmd_handler_args *args)
 {
 	const struct ec_params_usb_charge_set_mode *p = args->params;
 
-	if (usb_charge_set_mode(p->usb_port_id, p->mode,
-				p->inhibit_charge) != EC_SUCCESS)
+	if (usb_charge_set_mode(p->usb_port_id, p->mode, p->inhibit_charge) !=
+	    EC_SUCCESS)
 		return EC_RES_ERROR;
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_USB_CHARGE_SET_MODE,
-		     usb_charge_command_set_mode,
+DECLARE_HOST_COMMAND(EC_CMD_USB_CHARGE_SET_MODE, usb_charge_command_set_mode,
 		     EC_VER_MASK(0));
 
 /*****************************************************************************/
@@ -213,18 +215,18 @@ static void usb_charge_init(void)
 	const struct charge_mode_t *prev;
 	int version, size, i;
 
-	prev = (const struct charge_mode_t *)system_get_jump_tag(USB_SYSJUMP_TAG,
-						    &version, &size);
+	prev = (const struct charge_mode_t *)system_get_jump_tag(
+		USB_SYSJUMP_TAG, &version, &size);
 
 	if (!prev || version != USB_HOOK_VERSION ||
-			size != sizeof(charge_mode)) {
+	    size != sizeof(charge_mode)) {
 		usb_charge_all_ports_ctrl(USB_CHARGE_MODE_DISABLED);
 		return;
 	}
 
 	for (i = 0; i < CONFIG_USB_PORT_POWER_SMART_PORT_COUNT; i++)
 		usb_charge_set_mode(i, prev[i].mode,
-			prev[i].inhibit_charging_in_suspend);
+				    prev[i].inhibit_charging_in_suspend);
 }
 DECLARE_HOOK(HOOK_INIT, usb_charge_init, HOOK_PRIO_DEFAULT);
 
@@ -234,9 +236,8 @@ static void usb_charge_resume(void)
 
 	/* Turn on USB ports on as we go into S0 from S3 or S5. */
 	for (i = 0; i < CONFIG_USB_PORT_POWER_SMART_PORT_COUNT; i++)
-		usb_charge_set_mode(i,
-			CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE,
-			charge_mode[i].inhibit_charging_in_suspend);
+		usb_charge_set_mode(i, CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE,
+				    charge_mode[i].inhibit_charging_in_suspend);
 }
 DECLARE_HOOK(HOOK_CHIPSET_RESUME, usb_charge_resume, HOOK_PRIO_DEFAULT);
 
diff --git a/common/usb_update.c b/common/usb_update.c
index 3b307ede9a..444a4d6949 100644
--- a/common/usb_update.c
+++ b/common/usb_update.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,8 +20,8 @@
 #include "usb-stream.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USB, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args)
 
 /*
  * This file is an adaptation layer between the USB interface and the firmware
@@ -47,37 +47,27 @@
 struct consumer const update_consumer;
 struct usb_stream_config const usb_update;
 
-static struct queue const update_to_usb = QUEUE_DIRECT(64, uint8_t,
-						     null_producer,
-						     usb_update.consumer);
-static struct queue const usb_to_update = QUEUE_DIRECT(64, uint8_t,
-						     usb_update.producer,
-						     update_consumer);
-
-USB_STREAM_CONFIG_FULL(usb_update,
-		       USB_IFACE_UPDATE,
-		       USB_CLASS_VENDOR_SPEC,
-		       USB_SUBCLASS_GOOGLE_UPDATE,
-		       USB_PROTOCOL_GOOGLE_UPDATE,
-		       USB_STR_UPDATE_NAME,
-		       USB_EP_UPDATE,
-		       USB_MAX_PACKET_SIZE,
-		       USB_MAX_PACKET_SIZE,
-		       usb_to_update,
-		       update_to_usb)
+static struct queue const update_to_usb =
+	QUEUE_DIRECT(64, uint8_t, null_producer, usb_update.consumer);
+static struct queue const usb_to_update =
+	QUEUE_DIRECT(64, uint8_t, usb_update.producer, update_consumer);
 
+USB_STREAM_CONFIG_FULL(usb_update, USB_IFACE_UPDATE, USB_CLASS_VENDOR_SPEC,
+		       USB_SUBCLASS_GOOGLE_UPDATE, USB_PROTOCOL_GOOGLE_UPDATE,
+		       USB_STR_UPDATE_NAME, USB_EP_UPDATE, USB_MAX_PACKET_SIZE,
+		       USB_MAX_PACKET_SIZE, usb_to_update, update_to_usb)
 
 /* The receiver can be in one of the states below. */
 enum rx_state {
-	rx_idle,	   /* Nothing happened yet. */
-	rx_inside_block,   /* Assembling a block to pass to the programmer. */
-	rx_outside_block,  /* Waiting for the next block to start or for the
-			      reset command. */
+	rx_idle, /* Nothing happened yet. */
+	rx_inside_block, /* Assembling a block to pass to the programmer. */
+	rx_outside_block, /* Waiting for the next block to start or for the
+			     reset command. */
 };
 
 enum rx_state rx_state_ = rx_idle;
-static uint8_t block_buffer[sizeof(struct update_command) +
-			    CONFIG_UPDATE_PDU_SIZE];
+static uint8_t
+	block_buffer[sizeof(struct update_command) + CONFIG_UPDATE_PDU_SIZE];
 static uint32_t block_size;
 static uint32_t block_index;
 
@@ -117,8 +107,8 @@ static int pair_challenge(struct pair_challenge *challenge)
 	 * tmp2 = device_private
 	 *      = HMAC_SHA256(device_secret, "device-identity")
 	 */
-	hmac_SHA256(tmp2, tmp, CONFIG_ROLLBACK_SECRET_SIZE,
-		    KEY_CONTEXT, sizeof(KEY_CONTEXT) - 1);
+	hmac_SHA256(tmp2, tmp, CONFIG_ROLLBACK_SECRET_SIZE, KEY_CONTEXT,
+		    sizeof(KEY_CONTEXT) - 1);
 
 	/* tmp = device_public = x25519(device_private, x25519_base_point) */
 	X25519_public_from_private(tmp, tmp2);
@@ -128,10 +118,11 @@ static int pair_challenge(struct pair_challenge *challenge)
 	X25519(tmp, tmp2, challenge->host_public);
 
 	/* tmp2 = authenticator = HMAC_SHA256(shared_secret, nonce) */
-	hmac_SHA256(tmp2, tmp, sizeof(tmp),
-		    challenge->nonce, sizeof(challenge->nonce));
+	hmac_SHA256(tmp2, tmp, sizeof(tmp), challenge->nonce,
+		    sizeof(challenge->nonce));
 	QUEUE_ADD_UNITS(&update_to_usb, tmp2,
-		member_size(struct pair_challenge_response, authenticator));
+			member_size(struct pair_challenge_response,
+				    authenticator));
 	return 1;
 }
 #endif
@@ -198,7 +189,8 @@ static int try_vendor_command(struct consumer const *consumer, size_t count)
 
 	/* Looks like this is a vendor command, let's verify it. */
 	if (update_pdu_valid(&cmd_buffer->cmd,
-			  count - offsetof(struct update_frame_header, cmd))) {
+			     count - offsetof(struct update_frame_header,
+					      cmd))) {
 		enum update_extra_command subcommand;
 		uint8_t response;
 		size_t response_size = sizeof(response);
@@ -267,8 +259,8 @@ static int try_vendor_command(struct consumer const *consumer, size_t count)
 			break;
 #ifdef CONFIG_ROLLBACK
 		case UPDATE_EXTRA_CMD_UNLOCK_ROLLBACK:
-			crec_flash_set_protect(EC_FLASH_PROTECT_ROLLBACK_AT_BOOT
-					       , 0);
+			crec_flash_set_protect(
+				EC_FLASH_PROTECT_ROLLBACK_AT_BOOT, 0);
 			response = EC_RES_SUCCESS;
 			break;
 #ifdef CONFIG_ROLLBACK_SECRET_SIZE
@@ -295,8 +287,8 @@ static int try_vendor_command(struct consumer const *consumer, size_t count)
 			}
 
 			/* pair_challenge takes care of answering */
-			return pair_challenge((struct pair_challenge *)
-						(buffer + header_size));
+			return pair_challenge((
+				struct pair_challenge *)(buffer + header_size));
 		}
 #endif
 #endif /* CONFIG_ROLLBACK_SECRET_SIZE */
@@ -322,11 +314,10 @@ static int try_vendor_command(struct consumer const *consumer, size_t count)
 
 #ifdef CONFIG_TOUCHPAD_HASH_FW
 			memcpy(tp.allowed_fw_hash, touchpad_fw_full_hash,
-				sizeof(tp.allowed_fw_hash));
+			       sizeof(tp.allowed_fw_hash));
 #endif
 #endif /* CONFIG_TOUCHPAD_VIRTUAL_OFF */
-			QUEUE_ADD_UNITS(&update_to_usb,
-					&tp, response_size);
+			QUEUE_ADD_UNITS(&update_to_usb, &tp, response_size);
 			return 1;
 		}
 		case UPDATE_EXTRA_CMD_TOUCHPAD_DEBUG: {
@@ -338,7 +329,8 @@ static int try_vendor_command(struct consumer const *consumer, size_t count)
 			 * with the payload data, and put the response in data.
 			 */
 			response = touchpad_debug(buffer + header_size,
-					data_count, &data, &write_count);
+						  data_count, &data,
+						  &write_count);
 
 			/*
 			 * On error, or if there is no data to write back, just
@@ -374,11 +366,10 @@ static int try_vendor_command(struct consumer const *consumer, size_t count)
 			}
 
 			response = uart_console_read_buffer(
-					data[0],
-					(char *)output,
-					MIN(sizeof(output),
-					    queue_space(&update_to_usb)),
-					&write_count);
+				data[0], (char *)output,
+				MIN(sizeof(output),
+				    queue_space(&update_to_usb)),
+				&write_count);
 			if (response != EC_RES_SUCCESS || write_count == 0)
 				break;
 
@@ -406,7 +397,7 @@ static uint64_t prev_activity_timestamp;
  * A flag indicating that at least one valid PDU containing flash update block
  * has been received in the current transfer session.
  */
-static uint8_t  data_was_transferred;
+static uint8_t data_was_transferred;
 
 /* Reply with an error to remote side, reset state. */
 static void send_error_reset(uint8_t resp_value)
@@ -459,10 +450,10 @@ static void update_out_handler(struct consumer const *consumer, size_t count)
 		 * digest = 0, and base = 0.
 		 */
 		if (!fetch_transfer_start(consumer, count, &u.upfr) ||
-			be32toh(u.upfr.block_size) !=
-					sizeof(struct update_frame_header) ||
-				u.upfr.cmd.block_digest != 0 ||
-				u.upfr.cmd.block_base != 0) {
+		    be32toh(u.upfr.block_size) !=
+			    sizeof(struct update_frame_header) ||
+		    u.upfr.cmd.block_digest != 0 ||
+		    u.upfr.cmd.block_base != 0) {
 			/*
 			 * Something is wrong, this payload is not a valid
 			 * update start PDU. Let'w indicate this by returning
@@ -474,14 +465,14 @@ static void update_out_handler(struct consumer const *consumer, size_t count)
 		}
 
 		CPRINTS("FW update: starting...");
-		fw_update_command_handler(&u.upfr.cmd, count -
-					   offsetof(struct update_frame_header,
-						    cmd),
-					   &resp_size);
+		fw_update_command_handler(
+			&u.upfr.cmd,
+			count - offsetof(struct update_frame_header, cmd),
+			&resp_size);
 
 		if (!u.startup_resp.return_value) {
-			rx_state_ = rx_outside_block;  /* We're in business. */
-			data_was_transferred = 0;   /* No data received yet. */
+			rx_state_ = rx_outside_block; /* We're in business. */
+			data_was_transferred = 0; /* No data received yet. */
 		}
 
 		/* Let the host know what updater had to say. */
@@ -509,8 +500,7 @@ static void update_out_handler(struct consumer const *consumer, size_t count)
 				}
 
 				resp_value = 0;
-				QUEUE_ADD_UNITS(&update_to_usb,
-						&resp_value, 1);
+				QUEUE_ADD_UNITS(&update_to_usb, &resp_value, 1);
 				rx_state_ = rx_idle;
 				return;
 			}
@@ -528,7 +518,7 @@ static void update_out_handler(struct consumer const *consumer, size_t count)
 
 		/* Let's allocate a large enough buffer. */
 		block_size = be32toh(upfr.block_size) -
-			offsetof(struct update_frame_header, cmd);
+			     offsetof(struct update_frame_header, cmd);
 
 		/*
 		 * Only update start PDU is allowed to have a size 0 payload.
@@ -545,7 +535,7 @@ static void update_out_handler(struct consumer const *consumer, size_t count)
 		 * to the updater.
 		 */
 		block_index = sizeof(upfr) -
-			offsetof(struct update_frame_header, cmd);
+			      offsetof(struct update_frame_header, cmd);
 		memcpy(block_buffer, &upfr.cmd, block_index);
 		block_size -= block_index;
 		rx_state_ = rx_inside_block;
@@ -567,7 +557,7 @@ static void update_out_handler(struct consumer const *consumer, size_t count)
 			send_error_reset(UPDATE_GEN_ERROR);
 			return;
 		}
-		return;	/* More to come. */
+		return; /* More to come. */
 	}
 
 	/*
@@ -588,7 +578,7 @@ static void update_out_handler(struct consumer const *consumer, size_t count)
 
 struct consumer const update_consumer = {
 	.queue = &usb_to_update,
-	.ops   = &((struct consumer_ops const) {
+	.ops = &((struct consumer_ops const){
 		.written = update_out_handler,
 	}),
 };
diff --git a/common/usbc/build.mk b/common/usbc/build.mk
index 60e2347741..15c9f06001 100644
--- a/common/usbc/build.mk
+++ b/common/usbc/build.mk
@@ -1,4 +1,4 @@
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/common/usbc/dp_alt_mode.c b/common/usbc/dp_alt_mode.c
index 5cf3c03ba8..0f2a42ec2a 100644
--- a/common/usbc/dp_alt_mode.c
+++ b/common/usbc/dp_alt_mode.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,8 @@
 
 #include <stdbool.h>
 #include <stdint.h>
-#include "assert.h"
 #include "atomic.h"
+#include "builtin/assert.h"
 #include "console.h"
 #include "usb_common.h"
 #include "usb_dp_alt_mode.h"
@@ -20,8 +20,8 @@
 #include "usb_pd_tcpm.h"
 
 #ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 #else
 #define CPRINTF(format, args...)
 #define CPRINTS(format, args...)
@@ -47,24 +47,20 @@ static enum dp_states dp_state[CONFIG_USB_PD_PORT_MAX_COUNT];
  * Default of 0 indicates no command expected.
  */
 static const uint8_t state_vdm_cmd[DP_STATE_COUNT] = {
-	[DP_START] = CMD_ENTER_MODE,
-	[DP_ENTER_ACKED] = CMD_DP_STATUS,
-	[DP_PREPARE_CONFIG] = CMD_DP_CONFIG,
-	[DP_PREPARE_EXIT] = CMD_EXIT_MODE,
+	[DP_START] = CMD_ENTER_MODE,	     [DP_ENTER_ACKED] = CMD_DP_STATUS,
+	[DP_PREPARE_CONFIG] = CMD_DP_CONFIG, [DP_PREPARE_EXIT] = CMD_EXIT_MODE,
 	[DP_ENTER_RETRY] = CMD_ENTER_MODE,
 };
 
 /*
  * Track if we're retrying due to an Enter Mode NAK
  */
-#define DP_FLAG_RETRY	BIT(0)
+#define DP_FLAG_RETRY BIT(0)
 
 static atomic_t dpm_dp_flags[CONFIG_USB_PD_PORT_MAX_COUNT];
 
-#define DP_SET_FLAG(port, flag) \
-	atomic_or(&dpm_dp_flags[port], (flag))
-#define DP_CLR_FLAG(port, flag) \
-	atomic_clear_bits(&dpm_dp_flags[port], (flag))
+#define DP_SET_FLAG(port, flag) atomic_or(&dpm_dp_flags[port], (flag))
+#define DP_CLR_FLAG(port, flag) atomic_clear_bits(&dpm_dp_flags[port], (flag))
 #define DP_CHK_FLAG(port, flag) (dpm_dp_flags[port] & (flag))
 
 bool dp_is_active(int port)
@@ -72,6 +68,11 @@ bool dp_is_active(int port)
 	return dp_state[port] == DP_ACTIVE || dp_state[port] == DP_PREPARE_EXIT;
 }
 
+bool dp_is_idle(int port)
+{
+	return dp_state[port] == DP_INACTIVE || dp_state[port] == DP_START;
+}
+
 void dp_init(int port)
 {
 	dp_state[port] = DP_START;
@@ -80,8 +81,7 @@ void dp_init(int port)
 
 bool dp_entry_is_done(int port)
 {
-	return dp_state[port] == DP_ACTIVE ||
-		dp_state[port] == DP_INACTIVE;
+	return dp_state[port] == DP_ACTIVE || dp_state[port] == DP_INACTIVE;
 }
 
 static void dp_entry_failed(int port)
@@ -91,8 +91,8 @@ static void dp_entry_failed(int port)
 	dpm_dp_flags[port] = 0;
 }
 
-static bool dp_response_valid(int port, enum tcpci_msg_type type,
-			     char *cmdt, int vdm_cmd)
+static bool dp_response_valid(int port, enum tcpci_msg_type type, char *cmdt,
+			      int vdm_cmd)
 {
 	enum dp_states st = dp_state[port];
 
@@ -103,7 +103,8 @@ static bool dp_response_valid(int port, enum tcpci_msg_type type,
 	if (type != TCPCI_MSG_SOP ||
 	    (st != DP_INACTIVE && state_vdm_cmd[st] != vdm_cmd)) {
 		CPRINTS("C%d: Received unexpected DP VDM %s (cmd %d) from"
-			" %s in state %d", port, cmdt, vdm_cmd,
+			" %s in state %d",
+			port, cmdt, vdm_cmd,
 			type == TCPCI_MSG_SOP ? "port partner" : "cable plug",
 			st);
 		dp_entry_failed(port);
@@ -120,17 +121,17 @@ static void dp_exit_to_usb_mode(int port)
 	set_usb_mux_with_current_data_role(port);
 
 	CPRINTS("C%d: Exited DP mode", port);
-    /*
-     * If the EC exits an alt mode autonomously, don't try to enter it again. If
-     * the AP commands the EC to exit DP mode, it might command the EC to enter
-     * again later, so leave the state machine ready for that possibility.
-     */
-	dp_state[port] = IS_ENABLED(CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY)
-		? DP_START : DP_INACTIVE;
+	/*
+	 * If the EC exits an alt mode autonomously, don't try to enter it
+	 * again. If the AP commands the EC to exit DP mode, it might command
+	 * the EC to enter again later, so leave the state machine ready for
+	 * that possibility.
+	 */
+	dp_state[port] = DP_INACTIVE;
 }
 
 void dp_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count,
-		uint32_t *vdm)
+		  uint32_t *vdm)
 {
 	const struct svdm_amode_data *modep =
 		pd_get_amode_data(port, type, USB_SID_DISPLAYPORT);
@@ -180,8 +181,8 @@ void dp_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count,
 		break;
 	default:
 		/* Invalid or unexpected negotiation state */
-		CPRINTF("%s called with invalid state %d\n",
-				__func__, dp_state[port]);
+		CPRINTF("%s called with invalid state %d\n", __func__,
+			dp_state[port]);
 		dp_entry_failed(port);
 		break;
 	}
@@ -216,8 +217,8 @@ void dp_vdm_naked(int port, enum tcpci_msg_type type, uint8_t vdm_cmd)
 		dp_exit_to_usb_mode(port);
 		break;
 	default:
-		CPRINTS("C%d: NAK for cmd %d in state %d", port,
-			vdm_cmd, dp_state[port]);
+		CPRINTS("C%d: NAK for cmd %d in state %d", port, vdm_cmd,
+			dp_state[port]);
 		dp_entry_failed(port);
 		break;
 	}
@@ -226,8 +227,8 @@ void dp_vdm_naked(int port, enum tcpci_msg_type type, uint8_t vdm_cmd)
 enum dpm_msg_setup_status dp_setup_next_vdm(int port, int *vdo_count,
 					    uint32_t *vdm)
 {
-	const struct svdm_amode_data *modep = pd_get_amode_data(port,
-			TCPCI_MSG_SOP, USB_SID_DISPLAYPORT);
+	const struct svdm_amode_data *modep =
+		pd_get_amode_data(port, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT);
 	int vdo_count_ret;
 
 	if (*vdo_count < VDO_MAX_SIZE)
@@ -238,7 +239,7 @@ enum dpm_msg_setup_status dp_setup_next_vdm(int port, int *vdo_count,
 	case DP_ENTER_RETRY:
 		/* Enter the first supported mode for DisplayPort. */
 		vdm[0] = pd_dfp_enter_mode(port, TCPCI_MSG_SOP,
-				USB_SID_DISPLAYPORT, 0);
+					   USB_SID_DISPLAYPORT, 0);
 		if (vdm[0] == 0)
 			return MSG_SETUP_ERROR;
 		/* CMDT_INIT is 0, so this is a no-op */
@@ -311,8 +312,7 @@ enum dpm_msg_setup_status dp_setup_next_vdm(int port, int *vdo_count,
 		return MSG_SETUP_MUX_WAIT;
 	case DP_PREPARE_EXIT:
 		/* DPM should call setup only after safe state is set */
-		vdm[0] = VDO(USB_SID_DISPLAYPORT,
-			     1, /* structured */
+		vdm[0] = VDO(USB_SID_DISPLAYPORT, 1, /* structured */
 			     CMD_EXIT_MODE);
 
 		vdm[0] |= VDO_OPOS(modep->opos);
@@ -326,8 +326,8 @@ enum dpm_msg_setup_status dp_setup_next_vdm(int port, int *vdo_count,
 		 */
 		return MSG_SETUP_ERROR;
 	default:
-		CPRINTF("%s called with invalid state %d\n",
-				__func__, dp_state[port]);
+		CPRINTF("%s called with invalid state %d\n", __func__,
+			dp_state[port]);
 		return MSG_SETUP_ERROR;
 	}
 
diff --git a/common/usbc/tbt_alt_mode.c b/common/usbc/tbt_alt_mode.c
index 5baf9d1a73..d1ad031fad 100644
--- a/common/usbc/tbt_alt_mode.c
+++ b/common/usbc/tbt_alt_mode.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,6 +14,7 @@
 #include "compile_time_macros.h"
 #include "console.h"
 #include "tcpm/tcpm.h"
+#include "typec_control.h"
 #include "usb_common.h"
 #include "usb_mux.h"
 #include "usb_pd.h"
@@ -57,8 +58,8 @@
  */
 
 #ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 #else
 #define CPRINTF(format, args...)
 #define CPRINTS(format, args...)
@@ -70,8 +71,8 @@
  * with a partner. It may be fixed in b/159495742, in which case this
  * logic is unneeded.
  */
-#define TBT_FLAG_RETRY_DONE       BIT(0)
-#define TBT_FLAG_EXIT_DONE        BIT(1)
+#define TBT_FLAG_RETRY_DONE BIT(0)
+#define TBT_FLAG_EXIT_DONE BIT(1)
 #define TBT_FLAG_CABLE_ENTRY_DONE BIT(2)
 
 static uint8_t tbt_flags[CONFIG_USB_PD_PORT_MAX_COUNT];
@@ -123,14 +124,12 @@ void tbt_init(int port)
 
 bool tbt_is_active(int port)
 {
-	return tbt_state[port] != TBT_INACTIVE &&
-	       tbt_state[port] != TBT_START;
+	return tbt_state[port] != TBT_INACTIVE && tbt_state[port] != TBT_START;
 }
 
 bool tbt_entry_is_done(int port)
 {
-	return tbt_state[port] == TBT_ACTIVE ||
-		tbt_state[port] == TBT_INACTIVE;
+	return tbt_state[port] == TBT_ACTIVE || tbt_state[port] == TBT_INACTIVE;
 }
 
 bool tbt_cable_entry_is_done(int port)
@@ -140,13 +139,15 @@ bool tbt_cable_entry_is_done(int port)
 
 static void tbt_exit_done(int port)
 {
-    /*
-     * If the EC exits an alt mode autonomously, don't try to enter it again. If
-     * the AP commands the EC to exit DP mode, it might command the EC to enter
-     * again later, so leave the state machine ready for that possibility.
-     */
-	tbt_state[port] = IS_ENABLED(CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY)
-		? TBT_START : TBT_INACTIVE;
+	/*
+	 * If the EC exits an alt mode autonomously, don't try to enter it
+	 * again. If the AP commands the EC to exit DP mode, it might command
+	 * the EC to enter again later, so leave the state machine ready for
+	 * that possibility.
+	 */
+	tbt_state[port] = IS_ENABLED(CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY) ?
+				  TBT_START :
+				  TBT_INACTIVE;
 	TBT_CLR_FLAG(port, TBT_FLAG_RETRY_DONE);
 	TBT_CLR_FLAG(port, TBT_FLAG_CABLE_ENTRY_DONE);
 
@@ -159,10 +160,47 @@ static void tbt_exit_done(int port)
 	tbt_prints("alt mode protocol failed!", port);
 }
 
-void tbt_exit_mode_request(int port)
+static bool tbt_is_lrd_active_cable(int port)
 {
 	union tbt_mode_resp_cable cable_mode_resp;
 
+	cable_mode_resp.raw_value =
+		pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME);
+	if (get_usb_pd_cable_type(port) == IDH_PTYPE_PCABLE &&
+	    cable_mode_resp.tbt_active_passive == TBT_CABLE_ACTIVE)
+		return true;
+
+	return false;
+}
+
+/* Check if this port requires SOP' mode entry and exit */
+static bool tbt_sop_prime_needed(int port)
+{
+	/*
+	 * We require SOP' entry if cable is
+	 * active cable, or
+	 * an LRD cable (passive in DiscoverIdentity, active in TBT mode)
+	 */
+	if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE ||
+	    tbt_is_lrd_active_cable(port))
+		return true;
+	return false;
+}
+
+/* Check if this port requires SOP'' mode entry and exit */
+static bool tbt_sop_prime_prime_needed(int port)
+{
+	const struct pd_discovery *disc;
+
+	disc = pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
+	if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE &&
+	    disc->identity.product_t1.a_rev20.sop_p_p)
+		return true;
+	return false;
+}
+
+void tbt_exit_mode_request(int port)
+{
 	TBT_SET_FLAG(port, TBT_FLAG_RETRY_DONE);
 	TBT_CLR_FLAG(port, TBT_FLAG_EXIT_DONE);
 	/*
@@ -172,26 +210,24 @@ void tbt_exit_mode_request(int port)
 	 * TODO (b/156749387): Remove once data reset feature is in place.
 	 */
 	if (tbt_state[port] == TBT_ENTER_SOP) {
-		cable_mode_resp.raw_value =
-			pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME);
-
 		/*
 		 * For Linear re-driver cables, the port enters USB4 mode
 		 * with Thunderbolt mode for SOP prime. Hence, on request to
 		 * exit, only exit Thunderbolt mode SOP prime
 		 */
-		tbt_state[port] =
-			cable_mode_resp.tbt_active_passive == TBT_CABLE_ACTIVE ?
-			TBT_EXIT_SOP_PRIME : TBT_EXIT_SOP_PRIME_PRIME;
+		tbt_state[port] = tbt_sop_prime_prime_needed(port) ?
+					  TBT_EXIT_SOP_PRIME_PRIME :
+					  TBT_EXIT_SOP_PRIME;
 	}
 }
 
-static bool tbt_response_valid(int port, enum tcpci_msg_type type,
-				char *cmdt, int vdm_cmd)
+static bool tbt_response_valid(int port, enum tcpci_msg_type type, char *cmdt,
+			       int vdm_cmd)
 {
 	enum tbt_states st = tbt_state[port];
 	union tbt_mode_resp_cable cable_mode_resp = {
-		.raw_value = pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME) };
+		.raw_value = pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME)
+	};
 
 	/*
 	 * Check for an unexpected response.
@@ -216,71 +252,50 @@ static void tbt_retry_enter_mode(int port)
 	TBT_SET_FLAG(port, TBT_FLAG_RETRY_DONE);
 }
 
-/* Send Exit Mode to SOP''(if supported), or SOP' */
-static void tbt_active_cable_exit_mode(int port)
-{
-	const struct pd_discovery *disc;
-
-	disc = pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
-
-	if (disc->identity.product_t1.a_rev20.sop_p_p)
-		tbt_state[port] = TBT_EXIT_SOP_PRIME_PRIME;
-	else
-		tbt_state[port] = TBT_EXIT_SOP_PRIME;
-}
-
 bool tbt_cable_entry_required_for_usb4(int port)
 {
 	const struct pd_discovery *disc_sop_prime;
-	union tbt_mode_resp_cable cable_mode_resp;
 
-	/* Request to enter Thunderbolt mode for the cable prior to entering
-	 * USB4 mode if -
-	 * 1. Thunderbolt Mode SOP' VDO active/passive bit (B25) is
-	 *    TBT_CABLE_ACTIVE or
-	 * 2. It's an active cable with VDM version < 2.0 or
-	 *    VDO version < 1.3
-	 */
 	if (tbt_cable_entry_is_done(port))
 		return false;
 
-	cable_mode_resp.raw_value =
-			pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME);
-
-	if (cable_mode_resp.tbt_active_passive == TBT_CABLE_ACTIVE)
+	/*
+	 * For some cables, the TCPM may need to enter TBT mode with the
+	 * cable to support USB4 mode with the partner. Request to enter
+	 * Thunderbolt mode for the cable prior to entering USB4 for
+	 * the port partner if
+	 * 1. The cable advertises itself as passive in its Identity VDO
+	 * but active in its TBT mode VDO, or
+	 * 2. The cable advertises itself as active, but its PD support
+	 * is not new enough to support Enter_USB.
+	 */
+	if (tbt_is_lrd_active_cable(port))
 		return true;
 
 	if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE) {
 		disc_sop_prime = pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
 		if (pd_get_vdo_ver(port, TCPCI_MSG_SOP_PRIME) < VDM_VER20 ||
 		    disc_sop_prime->identity.product_t1.a_rev30.vdo_ver <
-							VDO_VERSION_1_3)
+			    VDO_VERSION_1_3)
 			return true;
 	}
 	return false;
 }
 
 void intel_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count,
-		uint32_t *vdm)
+		     uint32_t *vdm)
 {
-	const struct pd_discovery *disc;
 	const uint8_t vdm_cmd = PD_VDO_CMD(vdm[0]);
 	int opos_sop, opos_sop_prime;
-	union tbt_mode_resp_cable cable_mode_resp;
 
 	if (!tbt_response_valid(port, type, "ACK", vdm_cmd))
 		return;
 
-	disc = pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
-
 	switch (tbt_state[port]) {
 	case TBT_ENTER_SOP_PRIME:
 		tbt_prints("enter mode SOP'", port);
-		cable_mode_resp.raw_value =
-				pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME);
 		/* For LRD cables, Enter mode SOP' -> Enter mode SOP */
-		if (disc->identity.product_t1.a_rev20.sop_p_p &&
-		    cable_mode_resp.tbt_active_passive != TBT_CABLE_ACTIVE) {
+		if (tbt_sop_prime_prime_needed(port)) {
 			tbt_state[port] = TBT_ENTER_SOP_PRIME_PRIME;
 		} else {
 			TBT_SET_FLAG(port, TBT_FLAG_CABLE_ENTRY_DONE);
@@ -308,8 +323,11 @@ void intel_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count,
 		if (opos_sop > 0)
 			pd_dfp_exit_mode(port, TCPCI_MSG_SOP, USB_VID_INTEL,
 					 opos_sop);
-		if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE) {
-			tbt_active_cable_exit_mode(port);
+
+		if (tbt_sop_prime_prime_needed(port)) {
+			tbt_state[port] = TBT_EXIT_SOP_PRIME_PRIME;
+		} else if (tbt_sop_prime_needed(port)) {
+			tbt_state[port] = TBT_EXIT_SOP_PRIME;
 		} else {
 			set_usb_mux_with_current_data_role(port);
 			if (TBT_CHK_FLAG(port, TBT_FLAG_RETRY_DONE))
@@ -330,13 +348,12 @@ void intel_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count,
 			 * Exit mode process is complete; go to inactive state.
 			 */
 			tbt_exit_done(port);
-			opos_sop_prime =
-				pd_alt_mode(port, TCPCI_MSG_SOP_PRIME,
-					    USB_VID_INTEL);
+			opos_sop_prime = pd_alt_mode(port, TCPCI_MSG_SOP_PRIME,
+						     USB_VID_INTEL);
 
 			/* Clear Thunderbolt related signals */
 			pd_dfp_exit_mode(port, TCPCI_MSG_SOP_PRIME,
-					USB_VID_INTEL, opos_sop_prime);
+					 USB_VID_INTEL, opos_sop_prime);
 			set_usb_mux_with_current_data_role(port);
 		} else {
 			tbt_retry_enter_mode(port);
@@ -351,8 +368,8 @@ void intel_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count,
 		break;
 	default:
 		/* Invalid or unexpected negotiation state */
-		 CPRINTF("%s called with invalid state %d\n",
-				__func__, tbt_state[port]);
+		CPRINTF("%s called with invalid state %d\n", __func__,
+			tbt_state[port]);
 		tbt_exit_done(port);
 		break;
 	}
@@ -378,9 +395,12 @@ void intel_vdm_naked(int port, enum tcpci_msg_type type, uint8_t vdm_cmd)
 	case TBT_EXIT_SOP:
 		/* Exit SOP got NAK'ed */
 		tbt_prints("exit mode SOP failed", port);
-		if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE)
-			tbt_active_cable_exit_mode(port);
-		else {
+
+		if (tbt_sop_prime_prime_needed(port)) {
+			tbt_state[port] = TBT_EXIT_SOP_PRIME_PRIME;
+		} else if (tbt_sop_prime_needed(port)) {
+			tbt_state[port] = TBT_EXIT_SOP_PRIME;
+		} else {
 			set_usb_mux_with_current_data_role(port);
 			if (TBT_CHK_FLAG(port, TBT_FLAG_RETRY_DONE))
 				/* Retried enter mode, still failed, give up */
@@ -406,8 +426,8 @@ void intel_vdm_naked(int port, enum tcpci_msg_type type, uint8_t vdm_cmd)
 		}
 		break;
 	default:
-		CPRINTS("C%d: NAK for cmd %d in state %d", port,
-			vdm_cmd, tbt_state[port]);
+		CPRINTS("C%d: NAK for cmd %d in state %d", port, vdm_cmd,
+			tbt_state[port]);
 		tbt_exit_done(port);
 		break;
 	}
@@ -416,7 +436,7 @@ void intel_vdm_naked(int port, enum tcpci_msg_type type, uint8_t vdm_cmd)
 static bool tbt_mode_is_supported(int port, int vdo_count)
 {
 	const struct pd_discovery *disc =
-			pd_get_am_discovery(port, TCPCI_MSG_SOP);
+		pd_get_am_discovery(port, TCPCI_MSG_SOP);
 
 	if (!disc->identity.idh.modal_support)
 		return false;
@@ -430,8 +450,8 @@ static bool tbt_mode_is_supported(int port, int vdo_count)
 	 * SVID USB_VID_INTEL to enter Thunderbolt alt mode
 	 */
 	if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE &&
-		!pd_is_mode_discovered_for_svid(
-			port, TCPCI_MSG_SOP_PRIME, USB_VID_INTEL))
+	    !pd_is_mode_discovered_for_svid(port, TCPCI_MSG_SOP_PRIME,
+					    USB_VID_INTEL))
 		return false;
 
 	return true;
@@ -443,7 +463,6 @@ enum dpm_msg_setup_status tbt_setup_next_vdm(int port, int *vdo_count,
 {
 	struct svdm_amode_data *modep;
 	int vdo_count_ret = 0;
-	union tbt_mode_resp_cable cable_mode_resp;
 
 	*tx_type = TCPCI_MSG_SOP;
 
@@ -467,12 +486,8 @@ enum dpm_msg_setup_status tbt_setup_next_vdm(int port, int *vdo_count,
 		 */
 		usb_mux_set_safe_mode(port);
 
-		cable_mode_resp.raw_value =
-			pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME);
-
 		/* Active cable and LRD cables send Enter Mode SOP' first */
-		if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE ||
-		    cable_mode_resp.tbt_active_passive == TBT_CABLE_ACTIVE) {
+		if (tbt_sop_prime_needed(port)) {
 			tbt_state[port] = TBT_ENTER_SOP_PRIME;
 		} else {
 			/* Passive cable send Enter Mode SOP */
@@ -486,14 +501,12 @@ enum dpm_msg_setup_status tbt_setup_next_vdm(int port, int *vdo_count,
 		*tx_type = TCPCI_MSG_SOP_PRIME;
 		break;
 	case TBT_ENTER_SOP_PRIME_PRIME:
-		vdo_count_ret =
-			enter_tbt_compat_mode(
-				port, TCPCI_MSG_SOP_PRIME_PRIME, vdm);
+		vdo_count_ret = enter_tbt_compat_mode(
+			port, TCPCI_MSG_SOP_PRIME_PRIME, vdm);
 		*tx_type = TCPCI_MSG_SOP_PRIME_PRIME;
 		break;
 	case TBT_ENTER_SOP:
-		vdo_count_ret =
-			enter_tbt_compat_mode(port, TCPCI_MSG_SOP, vdm);
+		vdo_count_ret = enter_tbt_compat_mode(port, TCPCI_MSG_SOP, vdm);
 		break;
 	case TBT_ACTIVE:
 		/*
@@ -515,43 +528,38 @@ enum dpm_msg_setup_status tbt_setup_next_vdm(int port, int *vdo_count,
 		return MSG_SETUP_MUX_WAIT;
 	case TBT_EXIT_SOP:
 		/* DPM will only call this after safe state set is done */
-		modep = pd_get_amode_data(port,
-					  TCPCI_MSG_SOP, USB_VID_INTEL);
+		modep = pd_get_amode_data(port, TCPCI_MSG_SOP, USB_VID_INTEL);
 		if (!(modep && modep->opos))
 			return MSG_SETUP_ERROR;
 
 		vdm[0] = VDO(USB_VID_INTEL, 1, CMD_EXIT_MODE) |
-			VDO_OPOS(modep->opos) |
-			VDO_CMDT(CMDT_INIT) |
-			VDO_SVDM_VERS(
-				pd_get_vdo_ver(port, TCPCI_MSG_SOP));
+			 VDO_OPOS(modep->opos) | VDO_CMDT(CMDT_INIT) |
+			 VDO_SVDM_VERS(pd_get_vdo_ver(port, TCPCI_MSG_SOP));
 		vdo_count_ret = 1;
 		break;
 	case TBT_EXIT_SOP_PRIME_PRIME:
-		modep = pd_get_amode_data(port,
-			TCPCI_MSG_SOP_PRIME, USB_VID_INTEL);
+		modep = pd_get_amode_data(port, TCPCI_MSG_SOP_PRIME,
+					  USB_VID_INTEL);
 		if (!(modep && modep->opos))
 			return MSG_SETUP_ERROR;
 
 		vdm[0] = VDO(USB_VID_INTEL, 1, CMD_EXIT_MODE) |
-			VDO_OPOS(modep->opos) |
-			VDO_CMDT(CMDT_INIT) |
-			VDO_SVDM_VERS(pd_get_vdo_ver(port,
-				TCPCI_MSG_SOP_PRIME_PRIME));
+			 VDO_OPOS(modep->opos) | VDO_CMDT(CMDT_INIT) |
+			 VDO_SVDM_VERS(pd_get_vdo_ver(
+				 port, TCPCI_MSG_SOP_PRIME_PRIME));
 		vdo_count_ret = 1;
 		*tx_type = TCPCI_MSG_SOP_PRIME_PRIME;
 		break;
 	case TBT_EXIT_SOP_PRIME:
-		modep = pd_get_amode_data(port,
-				TCPCI_MSG_SOP_PRIME, USB_VID_INTEL);
+		modep = pd_get_amode_data(port, TCPCI_MSG_SOP_PRIME,
+					  USB_VID_INTEL);
 		if (!(modep && modep->opos))
 			return MSG_SETUP_ERROR;
 
 		vdm[0] = VDO(USB_VID_INTEL, 1, CMD_EXIT_MODE) |
-			VDO_OPOS(modep->opos) |
-			VDO_CMDT(CMDT_INIT) |
-			VDO_SVDM_VERS(pd_get_vdo_ver(port,
-						TCPCI_MSG_SOP_PRIME));
+			 VDO_OPOS(modep->opos) | VDO_CMDT(CMDT_INIT) |
+			 VDO_SVDM_VERS(
+				 pd_get_vdo_ver(port, TCPCI_MSG_SOP_PRIME));
 		vdo_count_ret = 1;
 		*tx_type = TCPCI_MSG_SOP_PRIME;
 		break;
@@ -559,8 +567,8 @@ enum dpm_msg_setup_status tbt_setup_next_vdm(int port, int *vdo_count,
 		/* Thunderbolt mode is inactive */
 		return MSG_SETUP_UNSUPPORTED;
 	default:
-		 CPRINTF("%s called with invalid state %d\n",
-				__func__, tbt_state[port]);
+		CPRINTF("%s called with invalid state %d\n", __func__,
+			tbt_state[port]);
 		return MSG_SETUP_ERROR;
 	}
 
@@ -571,3 +579,177 @@ enum dpm_msg_setup_status tbt_setup_next_vdm(int port, int *vdo_count,
 
 	return MSG_SETUP_UNSUPPORTED;
 }
+
+uint32_t pd_get_tbt_mode_vdo(int port, enum tcpci_msg_type type)
+{
+	uint32_t tbt_mode_vdo[PDO_MODES];
+
+	return pd_get_mode_vdo_for_svid(port, type, USB_VID_INTEL,
+					tbt_mode_vdo) ?
+		       tbt_mode_vdo[0] :
+		       0;
+}
+
+void set_tbt_compat_mode_ready(int port)
+{
+	if (IS_ENABLED(CONFIG_USBC_SS_MUX) &&
+	    IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE)) {
+		/* Connect the SBU and USB lines to the connector. */
+		typec_set_sbu(port, true);
+
+		/* Set usb mux to Thunderbolt-compatible mode */
+		usb_mux_set(port, USB_PD_MUX_TBT_COMPAT_ENABLED,
+			    USB_SWITCH_CONNECT,
+			    polarity_rm_dts(pd_get_polarity(port)));
+	}
+}
+
+/*
+ * Ref: USB Type-C Cable and Connector Specification
+ * Figure F-1 TBT3 Discovery Flow
+ */
+static bool is_tbt_cable_superspeed(int port)
+{
+	const struct pd_discovery *disc;
+
+	if (!IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE) ||
+	    !IS_ENABLED(CONFIG_USB_PD_DECODE_SOP))
+		return false;
+
+	disc = pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
+
+	/* Product type is Active cable, hence don't check for speed */
+	if (disc->identity.idh.product_type == IDH_PTYPE_ACABLE)
+		return true;
+
+	if (disc->identity.idh.product_type != IDH_PTYPE_PCABLE)
+		return false;
+
+	if (IS_ENABLED(CONFIG_USB_PD_REV30) &&
+	    pd_get_rev(port, TCPCI_MSG_SOP_PRIME) == PD_REV30)
+		return disc->identity.product_t1.p_rev30.ss ==
+			       USB_R30_SS_U32_U40_GEN1 ||
+		       disc->identity.product_t1.p_rev30.ss ==
+			       USB_R30_SS_U32_U40_GEN2 ||
+		       disc->identity.product_t1.p_rev30.ss ==
+			       USB_R30_SS_U40_GEN3;
+
+	return disc->identity.product_t1.p_rev20.ss == USB_R20_SS_U31_GEN1 ||
+	       disc->identity.product_t1.p_rev20.ss == USB_R20_SS_U31_GEN1_GEN2;
+}
+
+static enum tbt_compat_cable_speed usb_rev30_to_tbt_speed(enum usb_rev30_ss ss)
+{
+	switch (ss) {
+	case USB_R30_SS_U32_U40_GEN1:
+		return TBT_SS_U31_GEN1;
+	case USB_R30_SS_U32_U40_GEN2:
+		return TBT_SS_U32_GEN1_GEN2;
+	case USB_R30_SS_U40_GEN3:
+		return TBT_SS_TBT_GEN3;
+	default:
+		return TBT_SS_U32_GEN1_GEN2;
+	}
+}
+
+enum tbt_compat_cable_speed get_tbt_cable_speed(int port)
+{
+	union tbt_mode_resp_cable cable_mode_resp;
+	enum tbt_compat_cable_speed max_tbt_speed;
+	enum tbt_compat_cable_speed cable_tbt_speed;
+
+	if (!is_tbt_cable_superspeed(port))
+		return TBT_SS_RES_0;
+
+	cable_mode_resp.raw_value =
+		pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME);
+	max_tbt_speed = board_get_max_tbt_speed(port);
+
+	/*
+	 * Ref: TBT4 PD Discovery Flow Application Notes Revision 0.9, Figure 2
+	 * For passive cable, if cable doesn't support USB_VID_INTEL, enter
+	 * Thunderbolt alternate mode with speed from USB Highest Speed field of
+	 * the Passive Cable VDO
+	 * For active cable, if the cable doesn't support USB_VID_INTEL, do not
+	 * enter Thunderbolt alternate mode.
+	 */
+	if (!cable_mode_resp.raw_value) {
+		const struct pd_discovery *disc;
+
+		if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE)
+			return TBT_SS_RES_0;
+
+		disc = pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
+		cable_tbt_speed = usb_rev30_to_tbt_speed(
+			disc->identity.product_t1.p_rev30.ss);
+	} else {
+		cable_tbt_speed = cable_mode_resp.tbt_cable_speed;
+	}
+
+	return max_tbt_speed < cable_tbt_speed ? max_tbt_speed :
+						 cable_tbt_speed;
+}
+
+/* Note: Assumes that pins have already been set in safe state */
+int enter_tbt_compat_mode(int port, enum tcpci_msg_type sop, uint32_t *payload)
+{
+	union tbt_dev_mode_enter_cmd enter_dev_mode = { .raw_value = 0 };
+	union tbt_mode_resp_device dev_mode_resp;
+	union tbt_mode_resp_cable cable_mode_resp;
+	enum tcpci_msg_type enter_mode_sop =
+		sop == TCPCI_MSG_SOP_PRIME_PRIME ? TCPCI_MSG_SOP_PRIME : sop;
+
+	/* Table F-12 TBT3 Cable Enter Mode Command */
+	/*
+	 * The port doesn't query Discover SOP'' to the cable so, the port
+	 * doesn't have opos for SOP''. Hence, send Enter Mode SOP'' with same
+	 * opos and revision as SOP'.
+	 */
+	payload[0] = pd_dfp_enter_mode(port, enter_mode_sop, USB_VID_INTEL, 0) |
+		     VDO_CMDT(CMDT_INIT) |
+		     VDO_SVDM_VERS(pd_get_vdo_ver(port, enter_mode_sop));
+
+	/* For TBT3 Cable Enter Mode Command, number of Objects is 1 */
+	if ((sop == TCPCI_MSG_SOP_PRIME) || (sop == TCPCI_MSG_SOP_PRIME_PRIME))
+		return 1;
+
+	dev_mode_resp.raw_value = pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP);
+	cable_mode_resp.raw_value =
+		pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME);
+
+	/* Table F-13 TBT3 Device Enter Mode Command */
+	enter_dev_mode.vendor_spec_b1 = dev_mode_resp.vendor_spec_b1;
+	enter_dev_mode.vendor_spec_b0 = dev_mode_resp.vendor_spec_b0;
+	enter_dev_mode.intel_spec_b0 = dev_mode_resp.intel_spec_b0;
+
+	if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE ||
+	    cable_mode_resp.tbt_active_passive == TBT_CABLE_ACTIVE)
+		enter_dev_mode.cable = TBT_ENTER_ACTIVE_CABLE;
+
+	enter_dev_mode.lsrx_comm = cable_mode_resp.lsrx_comm;
+	enter_dev_mode.retimer_type = cable_mode_resp.retimer_type;
+	enter_dev_mode.tbt_cable = cable_mode_resp.tbt_cable;
+	enter_dev_mode.tbt_rounded = cable_mode_resp.tbt_rounded;
+	enter_dev_mode.tbt_cable_speed = get_tbt_cable_speed(port);
+	enter_dev_mode.tbt_alt_mode = TBT_ALTERNATE_MODE;
+
+	payload[1] = enter_dev_mode.raw_value;
+
+	/* For TBT3 Device Enter Mode Command, number of Objects are 2 */
+	return 2;
+}
+
+enum tbt_compat_rounded_support get_tbt_rounded_support(int port)
+{
+	union tbt_mode_resp_cable cable_mode_resp = {
+		.raw_value = pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME)
+	};
+
+	/* tbt_rounded_support is zero when uninitialized */
+	return cable_mode_resp.tbt_rounded;
+}
+
+__overridable enum tbt_compat_cable_speed board_get_max_tbt_speed(int port)
+{
+	return TBT_SS_TBT_GEN3;
+}
diff --git a/common/usbc/usb_mode.c b/common/usbc/usb_mode.c
index e7c385c59c..8f4824e4e9 100644
--- a/common/usbc/usb_mode.c
+++ b/common/usbc/usb_mode.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,8 +26,8 @@
 #include "usbc_ppc.h"
 
 #ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 #else
 #define CPRINTF(format, args...)
 #define CPRINTS(format, args...)
@@ -117,7 +117,7 @@ static void usb4_debug_prints(int port, enum usb4_mode_status usb4_status)
 bool enter_usb_entry_is_done(int port)
 {
 	return usb4_state[port] == USB4_ACTIVE ||
-		usb4_state[port] == USB4_INACTIVE;
+	       usb4_state[port] == USB4_INACTIVE;
 }
 
 void usb4_exit_mode_request(int port)
@@ -153,7 +153,7 @@ static bool enter_usb_response_valid(int port, enum tcpci_msg_type type)
 	 * Check for an unexpected response.
 	 */
 	if (get_usb_pd_cable_type(port) == IDH_PTYPE_PCABLE &&
-	     type != TCPCI_MSG_SOP) {
+	    type != TCPCI_MSG_SOP) {
 		enter_usb_failed(port);
 		return false;
 	}
@@ -163,7 +163,7 @@ static bool enter_usb_response_valid(int port, enum tcpci_msg_type type)
 bool enter_usb_port_partner_is_capable(int port)
 {
 	const struct pd_discovery *disc =
-			pd_get_am_discovery(port, TCPCI_MSG_SOP);
+		pd_get_am_discovery(port, TCPCI_MSG_SOP);
 
 	if (usb4_state[port] == USB4_INACTIVE)
 		return false;
@@ -185,7 +185,7 @@ bool enter_usb_cable_is_capable(int port)
 
 		if (pd_get_vdo_ver(port, TCPCI_MSG_SOP_PRIME) >= VDM_VER20 &&
 		    disc_sop_prime->identity.product_t1.a_rev30.vdo_ver >=
-							VDO_VERSION_1_3) {
+			    VDO_VERSION_1_3) {
 			union active_cable_vdo2_rev30 a2_rev30 =
 				disc_sop_prime->identity.product_t2.a2_rev30;
 			/*
@@ -195,25 +195,25 @@ bool enter_usb_cable_is_capable(int port)
 			 */
 			if (a2_rev30.usb_40_support == USB4_NOT_SUPPORTED)
 				return false;
-		/*
-		 * For VDM version < 2.0 or VDO version < 1.3, do not enter USB4
-		 * mode if the cable -
-		 * doesn't support modal operation or
-		 * doesn't support Intel SVID or
-		 * doesn't have rounded support.
-		 */
+			/*
+			 * For VDM version < 2.0 or VDO version < 1.3, do not
+			 * enter USB4 mode if the cable - doesn't support modal
+			 * operation or doesn't support Intel SVID or doesn't
+			 * have rounded support.
+			 */
 		} else {
 			const struct pd_discovery *disc =
 				pd_get_am_discovery(port, TCPCI_MSG_SOP);
 			union tbt_mode_resp_cable cable_mode_resp = {
-				.raw_value = pd_get_tbt_mode_vdo(port,
-							TCPCI_MSG_SOP_PRIME) };
+				.raw_value = pd_get_tbt_mode_vdo(
+					port, TCPCI_MSG_SOP_PRIME)
+			};
 
 			if (!disc->identity.idh.modal_support ||
-			   !pd_is_mode_discovered_for_svid(port,
-					TCPCI_MSG_SOP_PRIME, USB_VID_INTEL) ||
+			    !pd_is_mode_discovered_for_svid(
+				    port, TCPCI_MSG_SOP_PRIME, USB_VID_INTEL) ||
 			    cable_mode_resp.tbt_rounded !=
-					TBT_GEN3_GEN4_ROUNDED_NON_ROUNDED)
+				    TBT_GEN3_GEN4_ROUNDED_NON_ROUNDED)
 				return false;
 		}
 	} else {
@@ -288,7 +288,7 @@ uint32_t enter_usb_setup_next_msg(int port, enum tcpci_msg_type *type)
 
 		if (pd_get_vdo_ver(port, TCPCI_MSG_SOP_PRIME) < VDM_VER20 ||
 		    disc_sop_prime->identity.product_t1.a_rev30.vdo_ver <
-							VDO_VERSION_1_3 ||
+			    VDO_VERSION_1_3 ||
 		    get_usb_pd_cable_type(port) == IDH_PTYPE_PCABLE) {
 			usb4_state[port] = USB4_ENTER_SOP;
 		} else {
@@ -312,3 +312,107 @@ uint32_t enter_usb_setup_next_msg(int port, enum tcpci_msg_type *type)
 	}
 	return get_enter_usb_msg_payload(port);
 }
+
+/*
+ * For Cable rev 3.0: USB4 cable speed is set according to speed supported by
+ * the port and the response received from the cable, whichever is least.
+ *
+ * For Cable rev 2.0: If get_tbt_cable_speed() is less than
+ * TBT_SS_U31_GEN1, return USB_R30_SS_U2_ONLY speed since the board
+ * doesn't support superspeed else the USB4 cable speed is set according to
+ * the cable response.
+ */
+enum usb_rev30_ss get_usb4_cable_speed(int port)
+{
+	enum tbt_compat_cable_speed tbt_speed = get_tbt_cable_speed(port);
+	enum usb_rev30_ss max_usb4_speed;
+
+	if (tbt_speed < TBT_SS_U31_GEN1)
+		return USB_R30_SS_U2_ONLY;
+
+	/*
+	 * Converting Thunderbolt-Compatible board speed to equivalent USB4
+	 * speed.
+	 */
+	max_usb4_speed = tbt_speed == TBT_SS_TBT_GEN3 ? USB_R30_SS_U40_GEN3 :
+							USB_R30_SS_U32_U40_GEN2;
+
+	if ((get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE) &&
+	    pd_get_rev(port, TCPCI_MSG_SOP_PRIME) == PD_REV30) {
+		const struct pd_discovery *disc =
+			pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
+		union active_cable_vdo1_rev30 a_rev30 =
+			disc->identity.product_t1.a_rev30;
+
+		if (a_rev30.vdo_ver >= VDO_VERSION_1_3) {
+			return max_usb4_speed < a_rev30.ss ? max_usb4_speed :
+							     a_rev30.ss;
+		}
+	}
+
+	return max_usb4_speed;
+}
+
+uint32_t get_enter_usb_msg_payload(int port)
+{
+	/*
+	 * Ref: USB Power Delivery Specification Revision 3.0, Version 2.0
+	 * Table 6-47 Enter_USB Data Object
+	 */
+	union enter_usb_data_obj eudo;
+	const struct pd_discovery *disc;
+	union tbt_mode_resp_cable cable_mode_resp;
+
+	if (!IS_ENABLED(CONFIG_USB_PD_USB4))
+		return 0;
+
+	disc = pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME);
+	eudo.mode = USB_PD_40;
+	eudo.usb4_drd_cap = IS_ENABLED(CONFIG_USB_PD_USB4_DRD);
+	eudo.usb3_drd_cap = IS_ENABLED(CONFIG_USB_PD_USB32_DRD);
+	eudo.cable_speed = get_usb4_cable_speed(port);
+
+	if (disc->identity.idh.product_type == IDH_PTYPE_ACABLE) {
+		if (pd_get_rev(port, TCPCI_MSG_SOP_PRIME) == PD_REV30) {
+			enum retimer_active_element active_element =
+				disc->identity.product_t2.a2_rev30.active_elem;
+			eudo.cable_type = active_element == ACTIVE_RETIMER ?
+						  CABLE_TYPE_ACTIVE_RETIMER :
+						  CABLE_TYPE_ACTIVE_REDRIVER;
+		} else {
+			cable_mode_resp.raw_value =
+				pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME);
+
+			eudo.cable_type = cable_mode_resp.retimer_type ==
+							  USB_RETIMER ?
+						  CABLE_TYPE_ACTIVE_RETIMER :
+						  CABLE_TYPE_ACTIVE_REDRIVER;
+		}
+	} else {
+		cable_mode_resp.raw_value =
+			pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME);
+
+		eudo.cable_type = cable_mode_resp.tbt_active_passive ==
+						  TBT_CABLE_ACTIVE ?
+					  CABLE_TYPE_ACTIVE_REDRIVER :
+					  CABLE_TYPE_PASSIVE;
+	}
+
+	switch (disc->identity.product_t1.p_rev20.vbus_cur) {
+	case USB_VBUS_CUR_3A:
+		eudo.cable_current = USB4_CABLE_CURRENT_3A;
+		break;
+	case USB_VBUS_CUR_5A:
+		eudo.cable_current = USB4_CABLE_CURRENT_5A;
+		break;
+	default:
+		eudo.cable_current = USB4_CABLE_CURRENT_INVALID;
+		break;
+	}
+	eudo.pcie_supported = IS_ENABLED(CONFIG_USB_PD_PCIE_TUNNELING);
+	eudo.dp_supported = IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP);
+	eudo.tbt_supported = IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE);
+	eudo.host_present = 1;
+
+	return eudo.raw_value;
+}
diff --git a/common/usbc/usb_pd_console.c b/common/usbc/usb_pd_console.c
index 6b1ea259eb..027a0d66c5 100644
--- a/common/usbc/usb_pd_console.c
+++ b/common/usbc/usb_pd_console.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,8 @@
 #ifndef TEST_USB_PD_CONSOLE
 static
 #endif
-int command_pd(int argc, char **argv)
+	int
+	command_pd(int argc, const char **argv)
 {
 	int port;
 	char *e;
@@ -43,7 +44,7 @@ int command_pd(int argc, char **argv)
 			return EC_SUCCESS;
 		}
 	} else if (IS_ENABLED(CONFIG_USB_PD_TRY_SRC) &&
-				!strcasecmp(argv[1], "trysrc")) {
+		   !strcasecmp(argv[1], "trysrc")) {
 		enum try_src_override_t ov = tc_get_try_src_override();
 
 		if (argc >= 3) {
@@ -111,7 +112,7 @@ int command_pd(int argc, char **argv)
 			else if (!strcasecmp(argv[3], "data"))
 				pd_dpm_request(port, DPM_REQUEST_DR_SWAP);
 			else if (IS_ENABLED(CONFIG_USBC_VCONN_SWAP) &&
-					!strcasecmp(argv[3], "vconn"))
+				 !strcasecmp(argv[3], "vconn"))
 				pd_dpm_request(port, DPM_REQUEST_VCONN_SWAP);
 			else
 				return EC_ERROR_PARAM3;
@@ -135,60 +136,66 @@ int command_pd(int argc, char **argv)
 				case PD_DRP_FORCE_SOURCE:
 					ccprintf("force source\n");
 					break;
-				cflush();
+					cflush();
 				}
 			} else {
 				if (!strcasecmp(argv[3], "on"))
 					pd_set_dual_role(port,
-							PD_DRP_TOGGLE_ON);
+							 PD_DRP_TOGGLE_ON);
 				else if (!strcasecmp(argv[3], "off"))
 					pd_set_dual_role(port,
-							PD_DRP_TOGGLE_OFF);
+							 PD_DRP_TOGGLE_OFF);
 				else if (!strcasecmp(argv[3], "freeze"))
 					pd_set_dual_role(port, PD_DRP_FREEZE);
 				else if (!strcasecmp(argv[3], "sink"))
 					pd_set_dual_role(port,
-							PD_DRP_FORCE_SINK);
+							 PD_DRP_FORCE_SINK);
 				else if (!strcasecmp(argv[3], "source"))
 					pd_set_dual_role(port,
-							PD_DRP_FORCE_SOURCE);
+							 PD_DRP_FORCE_SOURCE);
 				else
 					return EC_ERROR_PARAM4;
 			}
 			return EC_SUCCESS;
+		} else if (!strcasecmp(argv[2], "suspend")) {
+			pd_comm_enable(port, 0);
+			pd_set_suspend(port, 1);
+		} else if (!strcasecmp(argv[2], "resume")) {
+			pd_comm_enable(port, 1);
+			pd_set_suspend(port, 0);
 		}
 	}
 
 	if (!strcasecmp(argv[2], "state")) {
 		cflush();
-		ccprintf("Port C%d CC%d, %s - Role: %s-%s",
-		port, pd_get_polarity(port) + 1,
-		pd_comm_is_enabled(port) ? "Enable" : "Disable",
-		pd_get_power_role(port) ==
-					PD_ROLE_SOURCE ? "SRC" : "SNK",
-		pd_get_data_role(port) == PD_ROLE_DFP ? "DFP" : "UFP");
+		ccprintf("Port C%d CC%d, %s - Role: %s-%s", port,
+			 pd_get_polarity(port) + 1,
+			 pd_comm_is_enabled(port) ? "Enable" : "Disable",
+			 pd_get_power_role(port) == PD_ROLE_SOURCE ? "SRC" :
+								     "SNK",
+			 pd_get_data_role(port) == PD_ROLE_DFP ? "DFP" : "UFP");
 
 		if (IS_ENABLED(CONFIG_USBC_VCONN))
 			ccprintf("%s ", tc_is_vconn_src(port) ? "-VC" : "");
 
 		ccprintf("TC State: %s, Flags: 0x%04x",
-			tc_get_current_state(port),
-			tc_get_flags(port));
+			 tc_get_current_state(port), tc_get_flags(port));
 
 		if (IS_ENABLED(CONFIG_USB_PE_SM))
 			ccprintf(" PE State: %s, Flags: 0x%04x\n",
-				pe_get_current_state(port),
-				pe_get_flags(port));
+				 pe_get_current_state(port),
+				 pe_get_flags(port));
 		else
 			ccprintf("\n");
 
 		cflush();
 	} else if (!strcasecmp(argv[2], "srccaps")) {
 		pd_srccaps_dump(port);
+	} else if (!strcasecmp(argv[2], "cc")) {
+		ccprintf("Port C%d CC%d\n", port, pd_get_task_cc_state(port));
 	}
 
-	if (IS_ENABLED(CONFIG_CMD_PD_TIMER) &&
-	    !strcasecmp(argv[2], "timer")) {
+	if (IS_ENABLED(CONFIG_CMD_PD_TIMER) && !strcasecmp(argv[2], "timer")) {
 		pd_timer_dump(port);
 	}
 
@@ -196,22 +203,24 @@ int command_pd(int argc, char **argv)
 }
 #ifndef TEST_USB_PD_CONSOLE
 DECLARE_CONSOLE_COMMAND(pd, command_pd,
-	 "version"
-	 "\ndump [0|1|2|3]"
+			"version"
+			"\ndump [0|1|2|3]"
 #ifdef CONFIG_USB_PD_TRY_SRC
-	"\ntrysrc [0|1|2]"
+			"\ntrysrc [0|1|2]"
 #endif
-	"\n\t<port> state"
-	"\n\t<port> srccaps"
+			"\n\t<port> state"
+			"\n\t<port> srccaps"
+			"\n\t<port> cc"
 #ifdef CONFIG_CMD_PD_TIMER
-	"\n\t<port> timer"
+			"\n\t<port> timer"
 #endif /* CONFIG_CMD_PD_TIMER */
 #ifdef CONFIG_USB_PD_DUAL_ROLE
-	"|tx|charger|dev"
-	"\n\t<port> disable|enable|soft|hard"
-	"\n\t<port> dualrole [on|off|freeze|sink|source]"
-	"\n\t<port> swap [power|data|vconn]"
+			"|tx|charger|dev"
+			"\n\t<port> disable|enable|soft|hard"
+			"\n\t<port> suspend|resume"
+			"\n\t<port> dualrole [on|off|freeze|sink|source]"
+			"\n\t<port> swap [power|data|vconn]"
 #endif /* CONFIG_USB_PD_DUAL_ROLE */
-	,
-	"USB PD");
+			,
+			"USB PD");
 #endif
diff --git a/common/usbc/usb_pd_dp_ufp.c b/common/usbc/usb_pd_dp_ufp.c
index 0009b5c710..d88ee17aaf 100644
--- a/common/usbc/usb_pd_dp_ufp.c
+++ b/common/usbc/usb_pd_dp_ufp.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,9 +15,8 @@
 #include "usb_pd.h"
 #include "usb_pd_dp_ufp.h"
 
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 enum hpd_state {
 	LOW_WAIT,
@@ -105,17 +104,17 @@ static void hpd_to_dp_attention(void)
 	 * the DP_STATUS VDO.
 	 */
 	svdm_header = VDO_SVDM_VERS(pd_get_vdo_ver(port, TCPCI_MSG_SOP)) |
-			       VDO_OPOS(opos) | CMD_ATTENTION;
+		      VDO_OPOS(opos) | CMD_ATTENTION;
 	vdm[0] = VDO(USB_SID_DISPLAYPORT, 1, svdm_header);
 
 	vdm[1] = VDO_DP_STATUS((evt == hpd_irq), /* IRQ_HPD */
-				(evt != hpd_low), /* HPD_HI|LOW */
-				0, /* request exit DP */
-				0, /* request exit USB */
-				dock_get_mf_preference(), /* MF pref */
-				1, /* enabled */
-				0, /* power low */
-				0x2);
+			       (evt != hpd_low), /* HPD_HI|LOW */
+			       0, /* request exit DP */
+			       0, /* request exit USB */
+			       dock_get_mf_preference(), /* MF pref */
+			       1, /* enabled */
+			       0, /* power low */
+			       0x2);
 
 	/* Send request to DPM to send an attention VDM */
 	pd_request_vdm_attention(port, vdm, ARRAY_SIZE(vdm));
@@ -154,10 +153,10 @@ static void hpd_queue_event(enum hpd_event evt)
 	 * are kept in the queue.
 	 */
 	if (evt == hpd_irq) {
-		if ((hpd.count >= HPD_QUEUE_DEPTH) || ((hpd.count  >= 2) &&
-			(hpd.queue[hpd.count - 2] == hpd_irq))) {
-			CPRINTS("hpd: discard hpd: count - %d",
-				hpd.count);
+		if ((hpd.count >= HPD_QUEUE_DEPTH) ||
+		    ((hpd.count >= 2) &&
+		     (hpd.queue[hpd.count - 2] == hpd_irq))) {
+			CPRINTS("hpd: discard hpd: count - %d", hpd.count);
 			return;
 		}
 	}
@@ -238,13 +237,13 @@ static void hpd_to_pd_converter(int level, uint64_t ts)
 		 */
 		if (!level) {
 			/* Still low, now wait for IRQ or LOW determination */
-			hpd.timer = ts + (HPD_T_IRQ_MAX_PULSE -
-					  HPD_T_IRQ_MIN_PULSE);
+			hpd.timer = ts +
+				    (HPD_T_IRQ_MAX_PULSE - HPD_T_IRQ_MIN_PULSE);
 			hpd.state = IRQ_CHECK;
 
 		} else {
 			uint64_t irq_ts = hpd.timer + HPD_T_IRQ_MAX_PULSE -
-				HPD_T_IRQ_MIN_PULSE;
+					  HPD_T_IRQ_MIN_PULSE;
 			/*
 			 * If hpd is high now, this must have been an edge
 			 * event, but still need to determine if the pulse width
@@ -271,7 +270,7 @@ static void hpd_to_pd_converter(int level, uint64_t ts)
 			if (ts <= hpd.timer) {
 				hpd_queue_event(hpd_irq);
 			}
-		} else if (ts >  hpd.timer) {
+		} else if (ts > hpd.timer) {
 			hpd.state = LOW_WAIT;
 			hpd_queue_event(hpd_low);
 		}
@@ -287,7 +286,7 @@ static void manage_hpd(void)
 	int level;
 	uint64_t ts = get_time().val;
 	uint32_t num_hpd_events = (hpd.edges.head - hpd.edges.tail) &
-		EDGE_QUEUE_MASK;
+				  EDGE_QUEUE_MASK;
 
 	/*
 	 * HPD edges are detected via GPIO interrupts. The ISR routine adds edge
@@ -305,7 +304,7 @@ static void manage_hpd(void)
 	}
 
 	if (num_hpd_events) {
-		while(num_hpd_events-- > 0) {
+		while (num_hpd_events-- > 0) {
 			int idx = hpd.edges.tail;
 
 			level = hpd.edges.buffer[idx].level;
@@ -331,9 +330,8 @@ static void manage_hpd(void)
 		 * a DP_ATTENTION message if a DP_CONFIG message has been
 		 * received and have passed the minimum spacing interval.
 		 */
-		if (hpd.send_enable &&
-		    ((get_time().val - hpd.last_send_ts) >
-		     HPD_T_MIN_DP_ATTEN)) {
+		if (hpd.send_enable && ((get_time().val - hpd.last_send_ts) >
+					HPD_T_MIN_DP_ATTEN)) {
 			/* Generate DP_ATTENTION event pending in queue */
 			hpd_to_dp_attention();
 		} else {
@@ -352,7 +350,7 @@ static void manage_hpd(void)
 			 * the minimum time spacing.
 			 */
 			callback_us = HPD_T_MIN_DP_ATTEN -
-				(get_time().val - hpd.last_send_ts);
+				      (get_time().val - hpd.last_send_ts);
 			if (callback_us <= 0 ||
 			    callback_us > HPD_T_MIN_DP_ATTEN)
 				callback_us = HPD_T_MIN_DP_ATTEN;
@@ -403,7 +401,7 @@ void usb_pd_hpd_converter_enable(int enable)
 		hpd.state = LOW_WAIT;
 		hpd.count = 0;
 		hpd.timer = 0;
-	        hpd.last_send_ts = 0;
+		hpd.last_send_ts = 0;
 		hpd.send_enable = 0;
 
 		/* Reset hpd signal edges queue */
@@ -427,7 +425,7 @@ void usb_pd_hpd_converter_enable(int enable)
 
 void usb_pd_hpd_edge_event(int signal)
 {
-	int  next_head = (hpd.edges.head + 1) & EDGE_QUEUE_MASK;
+	int next_head = (hpd.edges.head + 1) & EDGE_QUEUE_MASK;
 	struct hpd_mark mark;
 
 	/* Get current timestamp and level */
diff --git a/common/usbc/usb_pd_dpm.c b/common/usbc/usb_pd_dpm.c
index 159331171e..8141e92fd7 100644
--- a/common/usbc/usb_pd_dpm.c
+++ b/common/usbc/usb_pd_dpm.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,12 +8,15 @@
  * Refer to USB PD 3.0 spec, version 2.0, sections 8.2 and 8.3
  */
 
+#include "builtin/assert.h"
 #include "charge_state.h"
+#include "chipset.h"
 #include "compile_time_macros.h"
 #include "console.h"
 #include "ec_commands.h"
 #include "hooks.h"
 #include "power.h"
+#include "power_button.h"
 #include "system.h"
 #include "task.h"
 #include "tcpm/tcpm.h"
@@ -23,8 +26,9 @@
 #include "usb_mux.h"
 #include "usb_pd.h"
 #include "usb_pd_dpm.h"
-#include "usb_pd_tcpm.h"
 #include "usb_pd_pdo.h"
+#include "usb_pd_tcpm.h"
+#include "usb_pd_timer.h"
 #include "usb_pe_sm.h"
 #include "usb_tbt_alt_mode.h"
 
@@ -33,8 +37,8 @@
 #endif
 
 #ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 #else
 #define CPRINTF(format, args...)
 #define CPRINTS(format, args...)
@@ -48,6 +52,7 @@ static struct {
 	uint32_t vdm_attention[DPM_ATTENION_MAX_VDO];
 	int vdm_cnt;
 	mutex_t vdm_attention_mutex;
+	enum dpm_pd_button_state pd_button_state;
 } dpm[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 #define DPM_SET_FLAG(port, flag) atomic_or(&dpm[(port)].flags, (flag))
@@ -55,16 +60,18 @@ static struct {
 #define DPM_CHK_FLAG(port, flag) (dpm[(port)].flags & (flag))
 
 /* Flags for internal DPM state */
-#define DPM_FLAG_MODE_ENTRY_DONE      BIT(0)
-#define DPM_FLAG_EXIT_REQUEST         BIT(1)
-#define DPM_FLAG_ENTER_DP             BIT(2)
-#define DPM_FLAG_ENTER_TBT            BIT(3)
-#define DPM_FLAG_ENTER_USB4           BIT(4)
-#define DPM_FLAG_ENTER_ANY            (DPM_FLAG_ENTER_DP | DPM_FLAG_ENTER_TBT \
-					| DPM_FLAG_ENTER_USB4)
-#define DPM_FLAG_SEND_ATTENTION       BIT(5)
+#define DPM_FLAG_MODE_ENTRY_DONE BIT(0)
+#define DPM_FLAG_EXIT_REQUEST BIT(1)
+#define DPM_FLAG_ENTER_DP BIT(2)
+#define DPM_FLAG_ENTER_TBT BIT(3)
+#define DPM_FLAG_ENTER_USB4 BIT(4)
+#define DPM_FLAG_ENTER_ANY \
+	(DPM_FLAG_ENTER_DP | DPM_FLAG_ENTER_TBT | DPM_FLAG_ENTER_USB4)
+#define DPM_FLAG_SEND_ATTENTION BIT(5)
 #define DPM_FLAG_DATA_RESET_REQUESTED BIT(6)
-#define DPM_FLAG_DATA_RESET_DONE      BIT(7)
+#define DPM_FLAG_DATA_RESET_DONE BIT(7)
+#define DPM_FLAG_PD_BUTTON_PRESSED BIT(8)
+#define DPM_FLAG_PD_BUTTON_RELEASED BIT(9)
 
 #ifdef CONFIG_ZEPHYR
 static int init_vdm_attention_mutex(const struct device *dev)
@@ -81,6 +88,11 @@ static int init_vdm_attention_mutex(const struct device *dev)
 SYS_INIT(init_vdm_attention_mutex, POST_KERNEL, 50);
 #endif /* CONFIG_ZEPHYR */
 
+__overridable bool board_is_tbt_usb4_port(int port)
+{
+	return true;
+}
+
 enum ec_status pd_request_vdm_attention(int port, const uint32_t *data,
 					int vdo_count)
 {
@@ -120,17 +132,22 @@ enum ec_status pd_request_enter_mode(int port, enum typec_mode mode)
 		return EC_RES_INVALID_PARAM;
 
 	/* Only one enter request may be active at a time. */
-	if (DPM_CHK_FLAG(port, DPM_FLAG_ENTER_DP |
-				DPM_FLAG_ENTER_TBT |
-				DPM_FLAG_ENTER_USB4))
+	if (DPM_CHK_FLAG(port, DPM_FLAG_ENTER_DP | DPM_FLAG_ENTER_TBT |
+				       DPM_FLAG_ENTER_USB4))
 		return EC_RES_BUSY;
 
 	switch (mode) {
 	case TYPEC_MODE_DP:
+		if (dp_is_idle(port))
+			dp_init(port);
 		DPM_SET_FLAG(port, DPM_FLAG_ENTER_DP);
 		break;
 #ifdef CONFIG_USB_PD_TBT_COMPAT_MODE
 	case TYPEC_MODE_TBT:
+		/* TODO(b/235984702#comment21): Refactor alt mode modules
+		 * to better support mode reentry. */
+		if (dp_is_idle(port))
+			dp_init(port);
 		DPM_SET_FLAG(port, DPM_FLAG_ENTER_TBT);
 		break;
 #endif /* CONFIG_USB_PD_TBT_COMPAT_MODE */
@@ -153,19 +170,20 @@ enum ec_status pd_request_enter_mode(int port, enum typec_mode mode)
 void dpm_init(int port)
 {
 	dpm[port].flags = 0;
+	dpm[port].pd_button_state = DPM_PD_BUTTON_IDLE;
 }
 
 void dpm_mode_exit_complete(int port)
 {
 	DPM_CLR_FLAG(port, DPM_FLAG_MODE_ENTRY_DONE | DPM_FLAG_EXIT_REQUEST |
-			DPM_FLAG_SEND_ATTENTION);
+				   DPM_FLAG_SEND_ATTENTION);
 }
 
 static void dpm_set_mode_entry_done(int port)
 {
 	DPM_SET_FLAG(port, DPM_FLAG_MODE_ENTRY_DONE);
 	DPM_CLR_FLAG(port, DPM_FLAG_ENTER_DP | DPM_FLAG_ENTER_TBT |
-			DPM_FLAG_ENTER_USB4);
+				   DPM_FLAG_ENTER_USB4);
 }
 
 void dpm_set_mode_exit_request(int port)
@@ -210,7 +228,7 @@ static bool dpm_mode_entry_requested(int port, enum typec_mode mode)
 }
 
 void dpm_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count,
-		uint32_t *vdm)
+		   uint32_t *vdm)
 {
 	const uint16_t svid = PD_VDO_VID(vdm[0]);
 
@@ -227,12 +245,12 @@ void dpm_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count,
 		}
 	default:
 		CPRINTS("C%d: Received unexpected VDM ACK for SVID %d", port,
-				svid);
+			svid);
 	}
 }
 
 void dpm_vdm_naked(int port, enum tcpci_msg_type type, uint16_t svid,
-		uint8_t vdm_cmd)
+		   uint8_t vdm_cmd)
 {
 	switch (svid) {
 	case USB_SID_DISPLAYPORT:
@@ -245,7 +263,7 @@ void dpm_vdm_naked(int port, enum tcpci_msg_type type, uint16_t svid,
 		}
 	default:
 		CPRINTS("C%d: Received unexpected VDM NAK for SVID %d", port,
-				svid);
+			svid);
 	}
 }
 
@@ -261,16 +279,15 @@ static void dpm_attempt_mode_entry(int port)
 	uint32_t vdm[VDO_MAX_SIZE];
 	enum tcpci_msg_type tx_type = TCPCI_MSG_SOP;
 	bool enter_mode_requested =
-		IS_ENABLED(CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY) ?  false : true;
+		IS_ENABLED(CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY) ? false : true;
 	enum dpm_msg_setup_status status = MSG_SETUP_UNSUPPORTED;
 
 	if (pd_get_data_role(port) != PD_ROLE_DFP) {
-		if (DPM_CHK_FLAG(port, DPM_FLAG_ENTER_DP |
-					DPM_FLAG_ENTER_TBT |
-					DPM_FLAG_ENTER_USB4))
+		if (DPM_CHK_FLAG(port, DPM_FLAG_ENTER_DP | DPM_FLAG_ENTER_TBT |
+					       DPM_FLAG_ENTER_USB4))
 			DPM_CLR_FLAG(port, DPM_FLAG_ENTER_DP |
-					DPM_FLAG_ENTER_TBT |
-					DPM_FLAG_ENTER_USB4);
+						   DPM_FLAG_ENTER_TBT |
+						   DPM_FLAG_ENTER_USB4);
 		/*
 		 * TODO(b/168030639): Notify the AP that the enter mode request
 		 * failed.
@@ -298,9 +315,9 @@ static void dpm_attempt_mode_entry(int port)
 		return;
 
 	if (dp_entry_is_done(port) ||
-	   (IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE) &&
-				tbt_entry_is_done(port)) ||
-	   (IS_ENABLED(CONFIG_USB_PD_USB4) && enter_usb_entry_is_done(port))) {
+	    (IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE) &&
+	     tbt_entry_is_done(port)) ||
+	    (IS_ENABLED(CONFIG_USB_PD_USB4) && enter_usb_entry_is_done(port))) {
 		dpm_set_mode_entry_done(port);
 		return;
 	}
@@ -314,24 +331,23 @@ static void dpm_attempt_mode_entry(int port)
 		return;
 
 	if (IS_ENABLED(CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY) &&
-			IS_ENABLED(CONFIG_USB_PD_DATA_RESET_MSG) &&
-			DPM_CHK_FLAG(port, DPM_FLAG_ENTER_ANY) &&
-			!DPM_CHK_FLAG(port, DPM_FLAG_DATA_RESET_REQUESTED) &&
-			!DPM_CHK_FLAG(port, DPM_FLAG_DATA_RESET_DONE)) {
+	    IS_ENABLED(CONFIG_USB_PD_DATA_RESET_MSG) &&
+	    DPM_CHK_FLAG(port, DPM_FLAG_ENTER_ANY) &&
+	    !DPM_CHK_FLAG(port, DPM_FLAG_DATA_RESET_REQUESTED) &&
+	    !DPM_CHK_FLAG(port, DPM_FLAG_DATA_RESET_DONE)) {
 		pd_dpm_request(port, DPM_REQUEST_DATA_RESET);
 		DPM_SET_FLAG(port, DPM_FLAG_DATA_RESET_REQUESTED);
 		return;
 	}
 
 	if (IS_ENABLED(CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY) &&
-			IS_ENABLED(CONFIG_USB_PD_DATA_RESET_MSG) &&
-			!DPM_CHK_FLAG(port, DPM_FLAG_DATA_RESET_DONE)) {
+	    IS_ENABLED(CONFIG_USB_PD_DATA_RESET_MSG) &&
+	    !DPM_CHK_FLAG(port, DPM_FLAG_DATA_RESET_DONE)) {
 		return;
 	}
 
 	/* Check if port, port partner and cable support USB4. */
-	if (IS_ENABLED(CONFIG_USB_PD_USB4) &&
-	    board_is_tbt_usb4_port(port) &&
+	if (IS_ENABLED(CONFIG_USB_PD_USB4) && board_is_tbt_usb4_port(port) &&
 	    enter_usb_port_partner_is_capable(port) &&
 	    enter_usb_cable_is_capable(port) &&
 	    dpm_mode_entry_requested(port, TYPEC_MODE_USB4)) {
@@ -351,14 +367,13 @@ static void dpm_attempt_mode_entry(int port)
 
 	/* If not, check if they support Thunderbolt alt mode. */
 	if (IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE) &&
-			board_is_tbt_usb4_port(port) &&
-			pd_is_mode_discovered_for_svid(port, TCPCI_MSG_SOP,
-				USB_VID_INTEL) &&
-			dpm_mode_entry_requested(port, TYPEC_MODE_TBT)) {
+	    board_is_tbt_usb4_port(port) &&
+	    pd_is_mode_discovered_for_svid(port, TCPCI_MSG_SOP,
+					   USB_VID_INTEL) &&
+	    dpm_mode_entry_requested(port, TYPEC_MODE_TBT)) {
 		enter_mode_requested = true;
 		vdo_count = ARRAY_SIZE(vdm);
-		status = tbt_setup_next_vdm(port, &vdo_count, vdm,
-					    &tx_type);
+		status = tbt_setup_next_vdm(port, &vdo_count, vdm, &tx_type);
 	}
 
 	/* If not, check if they support DisplayPort alt mode. */
@@ -381,7 +396,7 @@ static void dpm_attempt_mode_entry(int port)
 	 * just mark setup done and get out of here.
 	 */
 	if (status != MSG_SETUP_SUCCESS &&
-				!DPM_CHK_FLAG(port, DPM_FLAG_MODE_ENTRY_DONE)) {
+	    !DPM_CHK_FLAG(port, DPM_FLAG_MODE_ENTRY_DONE)) {
 		if (enter_mode_requested) {
 			/*
 			 * TODO(b/168030639): Notify the AP that mode entry
@@ -427,9 +442,8 @@ static void dpm_attempt_mode_exit(int port)
 	 * is not supported, exit active modes individually.
 	 */
 	if (IS_ENABLED(CONFIG_USB_PD_DATA_RESET_MSG)) {
-		if (!DPM_CHK_FLAG(port, DPM_FLAG_DATA_RESET_REQUESTED)
-				&& !DPM_CHK_FLAG(port,
-					DPM_FLAG_DATA_RESET_DONE)) {
+		if (!DPM_CHK_FLAG(port, DPM_FLAG_DATA_RESET_REQUESTED) &&
+		    !DPM_CHK_FLAG(port, DPM_FLAG_DATA_RESET_DONE)) {
 			pd_dpm_request(port, DPM_REQUEST_DATA_RESET);
 			DPM_SET_FLAG(port, DPM_FLAG_DATA_RESET_REQUESTED);
 			return;
@@ -495,6 +509,118 @@ static void dpm_send_attention_vdm(int port)
 	DPM_CLR_FLAG(port, DPM_FLAG_SEND_ATTENTION);
 }
 
+void dpm_handle_alert(int port, uint32_t ado)
+{
+	if (ado & ADO_EXTENDED_ALERT_EVENT) {
+		/* Extended Alert */
+		if (pd_get_data_role(port) == PD_ROLE_DFP &&
+		    (ADO_EXTENDED_ALERT_EVENT_TYPE & ado) ==
+			    ADO_POWER_BUTTON_PRESS) {
+			DPM_SET_FLAG(port, DPM_FLAG_PD_BUTTON_PRESSED);
+		} else if (pd_get_data_role(port) == PD_ROLE_DFP &&
+			   (ADO_EXTENDED_ALERT_EVENT_TYPE & ado) ==
+				   ADO_POWER_BUTTON_RELEASE) {
+			DPM_SET_FLAG(port, DPM_FLAG_PD_BUTTON_RELEASED);
+		}
+	}
+}
+
+static void dpm_run_pd_button_sm(int port)
+{
+#ifdef CONFIG_AP_POWER_CONTROL
+	if (!IS_ENABLED(CONFIG_POWER_BUTTON_X86) &&
+	    !IS_ENABLED(CONFIG_CHIPSET_SC7180) &&
+	    !IS_ENABLED(CONFIG_CHIPSET_SC7280)) {
+		/* Insufficient chipset API support for USB PD power button. */
+		DPM_CLR_FLAG(port, DPM_FLAG_PD_BUTTON_PRESSED);
+		DPM_CLR_FLAG(port, DPM_FLAG_PD_BUTTON_RELEASED);
+		return;
+	}
+
+	/*
+	 * Check for invalid flag combination. Alerts can only send a press or
+	 * release event at once and only one flag should be set. If press and
+	 * release flags are both set, we cannot know the order they were
+	 * received. Clear the flags, disable the timer and return to an idle
+	 * state.
+	 */
+	if (DPM_CHK_FLAG(port, DPM_FLAG_PD_BUTTON_PRESSED) &&
+	    DPM_CHK_FLAG(port, DPM_FLAG_PD_BUTTON_RELEASED)) {
+		DPM_CLR_FLAG(port, DPM_FLAG_PD_BUTTON_PRESSED |
+					   DPM_FLAG_PD_BUTTON_RELEASED);
+		pd_timer_disable(port, DPM_TIMER_PD_BUTTON_SHORT_PRESS);
+		pd_timer_disable(port, DPM_TIMER_PD_BUTTON_LONG_PRESS);
+		dpm[port].pd_button_state = DPM_PD_BUTTON_IDLE;
+		return;
+	}
+
+	switch (dpm[port].pd_button_state) {
+	case DPM_PD_BUTTON_IDLE:
+		if (DPM_CHK_FLAG(port, DPM_FLAG_PD_BUTTON_PRESSED)) {
+			pd_timer_enable(port, DPM_TIMER_PD_BUTTON_SHORT_PRESS,
+					CONFIG_USB_PD_SHORT_PRESS_MAX_MS *
+						MSEC);
+			pd_timer_enable(port, DPM_TIMER_PD_BUTTON_LONG_PRESS,
+					CONFIG_USB_PD_LONG_PRESS_MAX_MS * MSEC);
+			dpm[port].pd_button_state = DPM_PD_BUTTON_PRESSED;
+		}
+		break;
+	case DPM_PD_BUTTON_PRESSED:
+		if (DPM_CHK_FLAG(port, DPM_FLAG_PD_BUTTON_PRESSED)) {
+			pd_timer_enable(port, DPM_TIMER_PD_BUTTON_SHORT_PRESS,
+					CONFIG_USB_PD_SHORT_PRESS_MAX_MS *
+						MSEC);
+			pd_timer_enable(port, DPM_TIMER_PD_BUTTON_LONG_PRESS,
+					CONFIG_USB_PD_LONG_PRESS_MAX_MS * MSEC);
+		} else if (pd_timer_is_expired(
+				   port, DPM_TIMER_PD_BUTTON_LONG_PRESS)) {
+			pd_timer_disable(port, DPM_TIMER_PD_BUTTON_SHORT_PRESS);
+			pd_timer_disable(port, DPM_TIMER_PD_BUTTON_LONG_PRESS);
+			dpm[port].pd_button_state = DPM_PD_BUTTON_IDLE;
+		} else if (DPM_CHK_FLAG(port, DPM_FLAG_PD_BUTTON_RELEASED)) {
+			if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
+				/*
+				 * Wake chipset on any button press when the
+				 * system is off.
+				 */
+				chipset_power_on();
+			} else if (chipset_in_state(
+					   CHIPSET_STATE_ANY_SUSPEND) ||
+				   chipset_in_state(CHIPSET_STATE_ON)) {
+				if (pd_timer_is_expired(
+					    port,
+					    DPM_TIMER_PD_BUTTON_SHORT_PRESS)) {
+					/*
+					 * Shutdown chipset on long USB PD power
+					 * button press.
+					 */
+					chipset_force_shutdown(
+						CHIPSET_SHUTDOWN_BUTTON);
+				} else {
+					/*
+					 * Simulate a short power button press
+					 * on short USB PD power button press.
+					 * This will wake the system from
+					 * suspend, or bring up the power UI
+					 * when the system is on.
+					 */
+					power_button_simulate_press(
+						USB_PD_SHORT_BUTTON_PRESS_MS);
+				}
+			}
+			pd_timer_disable(port, DPM_TIMER_PD_BUTTON_SHORT_PRESS);
+			pd_timer_disable(port, DPM_TIMER_PD_BUTTON_LONG_PRESS);
+			dpm[port].pd_button_state = DPM_PD_BUTTON_IDLE;
+		}
+		break;
+	}
+#endif /* CONFIG_AP_POWER_CONTROL */
+
+	/* After checking flags, clear them. */
+	DPM_CLR_FLAG(port, DPM_FLAG_PD_BUTTON_PRESSED);
+	DPM_CLR_FLAG(port, DPM_FLAG_PD_BUTTON_RELEASED);
+}
+
 void dpm_run(int port)
 {
 	if (pd_get_data_role(port) == PD_ROLE_DFP) {
@@ -503,6 +629,9 @@ void dpm_run(int port)
 			dpm_attempt_mode_exit(port);
 		else if (!DPM_CHK_FLAG(port, DPM_FLAG_MODE_ENTRY_DONE))
 			dpm_attempt_mode_entry(port);
+
+		/* Run USB PD Power button state machine */
+		dpm_run_pd_button_sm(port);
 	} else {
 		/* Run UFP related DPM requests */
 		if (DPM_CHK_FLAG(port, DPM_FLAG_SEND_ATTENTION))
@@ -523,7 +652,7 @@ void dpm_run(int port)
  * Note: request bitmasks should be accessed atomically as other ports may alter
  * them
  */
-static uint32_t		max_current_claimed;
+static uint32_t max_current_claimed;
 K_MUTEX_DEFINE(max_current_claimed_lock);
 
 /* Ports with PD sink needing > 1.5 A */
@@ -533,7 +662,10 @@ static atomic_t source_frs_max_requested;
 /* Ports with non-PD sinks, so current requirements are unknown */
 static atomic_t non_pd_sink_max_requested;
 
-#define LOWEST_PORT(p) __builtin_ctz(p)  /* Undefined behavior if p == 0 */
+/* BIST shared test mode */
+static bool bist_shared_mode_enabled;
+
+#define LOWEST_PORT(p) __builtin_ctz(p) /* Undefined behavior if p == 0 */
 
 static int count_port_bits(uint32_t bitmask)
 {
@@ -568,12 +700,19 @@ static void balance_source_ports(void)
 	if (deferred_waiting)
 		return;
 
+	/*
+	 * Turn off all shared power logic while BIST shared test mode is active
+	 * on the system.
+	 */
+	if (bist_shared_mode_enabled)
+		return;
+
 	mutex_lock(&max_current_claimed_lock);
 
 	/* Remove any ports which no longer require 3.0 A */
-	removed_ports = max_current_claimed & ~(sink_max_pdo_requested |
-						source_frs_max_requested |
-						non_pd_sink_max_requested);
+	removed_ports = max_current_claimed &
+			~(sink_max_pdo_requested | source_frs_max_requested |
+			  non_pd_sink_max_requested);
 	max_current_claimed &= ~removed_ports;
 
 	/* Allocate 3.0 A to new PD sink ports that need it */
@@ -582,7 +721,7 @@ static void balance_source_ports(void)
 		int new_max_port = LOWEST_PORT(new_ports);
 
 		if (count_port_bits(max_current_claimed) <
-						CONFIG_USB_PD_3A_PORTS) {
+		    CONFIG_USB_PD_3A_PORTS) {
 			max_current_claimed |= BIT(new_max_port);
 			typec_select_src_current_limit_rp(new_max_port,
 							  TYPEC_RP_3A0);
@@ -590,7 +729,8 @@ static void balance_source_ports(void)
 			/* Always downgrade non-PD ports first */
 			int rem_non_pd = LOWEST_PORT(non_pd_sink_max_requested &
 						     max_current_claimed);
-			typec_select_src_current_limit_rp(rem_non_pd,
+			typec_select_src_current_limit_rp(
+				rem_non_pd,
 				typec_get_default_current_limit_rp(rem_non_pd));
 			max_current_claimed &= ~BIT(rem_non_pd);
 
@@ -602,7 +742,7 @@ static void balance_source_ports(void)
 		} else if (source_frs_max_requested & max_current_claimed) {
 			/* Downgrade lowest FRS port from 3.0 A slot */
 			int rem_frs = LOWEST_PORT(source_frs_max_requested &
-						 max_current_claimed);
+						  max_current_claimed);
 			pd_dpm_request(rem_frs, DPM_REQUEST_FRS_DET_DISABLE);
 			max_current_claimed &= ~BIT(rem_frs);
 
@@ -624,14 +764,15 @@ static void balance_source_ports(void)
 		int new_frs_port = LOWEST_PORT(new_ports);
 
 		if (count_port_bits(max_current_claimed) <
-						CONFIG_USB_PD_3A_PORTS) {
+		    CONFIG_USB_PD_3A_PORTS) {
 			max_current_claimed |= BIT(new_frs_port);
 			pd_dpm_request(new_frs_port,
 				       DPM_REQUEST_FRS_DET_ENABLE);
 		} else if (non_pd_sink_max_requested & max_current_claimed) {
 			int rem_non_pd = LOWEST_PORT(non_pd_sink_max_requested &
 						     max_current_claimed);
-			typec_select_src_current_limit_rp(rem_non_pd,
+			typec_select_src_current_limit_rp(
+				rem_non_pd,
 				typec_get_default_current_limit_rp(rem_non_pd));
 			max_current_claimed &= ~BIT(rem_non_pd);
 
@@ -653,7 +794,7 @@ static void balance_source_ports(void)
 		int new_max_port = LOWEST_PORT(new_ports);
 
 		if (count_port_bits(max_current_claimed) <
-						CONFIG_USB_PD_3A_PORTS) {
+		    CONFIG_USB_PD_3A_PORTS) {
 			max_current_claimed |= BIT(new_max_port);
 			typec_select_src_current_limit_rp(new_max_port,
 							  TYPEC_RP_3A0);
@@ -741,7 +882,7 @@ void dpm_evaluate_request_rdo(int port, uint32_t rdo)
 		return;
 
 	op_ma = (rdo >> 10) & 0x3FF;
-	if ((BIT(port) && sink_max_pdo_requested) && (op_ma <= 150)) {
+	if ((BIT(port) & sink_max_pdo_requested) && (op_ma <= 150)) {
 		/*
 		 * sink_max_pdo_requested will be set when we get 5V/3A sink
 		 * capability from port partner. If port partner only request
@@ -766,8 +907,8 @@ void dpm_remove_sink(int port)
 	atomic_clear_bits(&non_pd_sink_max_requested, BIT(port));
 
 	/* Restore selected default Rp on the port */
-	typec_select_src_current_limit_rp(port,
-		typec_get_default_current_limit_rp(port));
+	typec_select_src_current_limit_rp(
+		port, typec_get_default_current_limit_rp(port));
 
 	balance_source_ports();
 }
@@ -788,16 +929,83 @@ void dpm_remove_source(int port)
 	balance_source_ports();
 }
 
+void dpm_bist_shared_mode_enter(int port)
+{
+	/*
+	 * From 6.4.3.3.1 BIST Shared Test Mode Entry:
+	 *
+	 * "When any Master Port in a shared capacity group receives a BIST
+	 * Message with a BIST Shared Test Mode Entry BIST Data Object, while
+	 * in the PE_SRC_Ready State, the UUT Shall enter a compliance test
+	 * mode where the maximum source capability is always offered on every
+	 * port, regardless of the availability of shared power i.e. all shared
+	 * power management is disabled.
+	 * . . .
+	 * On entering this mode, the UUT Shall send a new Source_Capabilities
+	 * Message from each Port in the shared capacity group within
+	 * tBISTSharedTestMode. The Tester will not exceed the shared capacity
+	 * during this mode."
+	 */
+
+	/* Shared mode is unnecessary without at least one 3.0 A port */
+	if (CONFIG_USB_PD_3A_PORTS == 0)
+		return;
+
+	/* Enter mode only if this port had been in PE_SRC_Ready */
+	if (pd_get_power_role(port) != PD_ROLE_SOURCE)
+		return;
+
+	bist_shared_mode_enabled = true;
+
+	/* Trigger new source caps on all source ports */
+	for (int i = 0; i < board_get_usb_pd_port_count(); i++) {
+		if (pd_get_power_role(i) == PD_ROLE_SOURCE)
+			typec_select_src_current_limit_rp(i, TYPEC_RP_3A0);
+	}
+}
+
+void dpm_bist_shared_mode_exit(int port)
+{
+	/*
+	 * From 6.4.3.3.2 BIST Shared Test Mode Exit:
+	 *
+	 * "Upon receipt of a BIST Message, with a BIST Shared Test Mode Exit
+	 * BIST Data Object, the UUT Shall return a GoodCRC Message and Shall
+	 * exit the BIST Shared Capacity Test Mode.
+	 * . . .
+	 * On exiting the mode, the UUT May send a new Source_Capabilities
+	 * Message to each port in the shared capacity group or the UUT May
+	 * perform ErrorRecovery on each port."
+	 */
+
+	/* Shared mode is unnecessary without at least one 3.0 A port */
+	if (CONFIG_USB_PD_3A_PORTS == 0)
+		return;
+
+	/* Do nothing if Exit was received with no Entry */
+	if (!bist_shared_mode_enabled)
+		return;
+
+	bist_shared_mode_enabled = false;
+
+	/* Declare error recovery bankruptcy */
+	for (int i = 0; i < board_get_usb_pd_port_count(); i++) {
+		pd_set_error_recovery(i);
+	}
+}
+
 /*
  * Note: all ports receive the 1.5 A source offering until they are found to
  * match a criteria on the 3.0 A priority list (ex. through sink capability
  * probing), at which point they will be offered a new 3.0 A source capability.
+ *
+ * All ports must be offered our full capability while in BIST shared test mode.
  */
 __overridable int dpm_get_source_pdo(const uint32_t **src_pdo, const int port)
 {
 	/* Max PDO may not exist on boards which don't offer 3 A */
 #if CONFIG_USB_PD_3A_PORTS > 0
-	if (max_current_claimed & BIT(port)) {
+	if (max_current_claimed & BIT(port) || bist_shared_mode_enabled) {
 		*src_pdo = pd_src_pdo_max;
 		return pd_src_pdo_max_cnt;
 	}
@@ -812,7 +1020,7 @@ int dpm_get_source_current(const int port)
 	if (pd_get_power_role(port) == PD_ROLE_SINK)
 		return 0;
 
-	if (max_current_claimed & BIT(port))
+	if (max_current_claimed & BIT(port) || bist_shared_mode_enabled)
 		return 3000;
 	else if (typec_get_default_current_limit_rp(port) == TYPEC_RP_1A5)
 		return 1500;
@@ -820,8 +1028,8 @@ int dpm_get_source_current(const int port)
 		return 500;
 }
 
-__overridable enum pd_sdb_power_indicator board_get_pd_sdb_power_indicator(
-enum pd_sdb_power_state power_state)
+__overridable enum pd_sdb_power_indicator
+board_get_pd_sdb_power_indicator(enum pd_sdb_power_state power_state)
 {
 	/*
 	 *  LED on for S0 and blinking for S0ix/S3.
@@ -856,7 +1064,7 @@ static uint8_t get_status_internal_temp(void)
 	else if (temp_c < 2)
 		temp_c = 1;
 
-	return (uint8_t) temp_c;
+	return (uint8_t)temp_c;
 #else
 	return 0;
 #endif
diff --git a/common/usbc/usb_pd_host.c b/common/usbc/usb_pd_host.c
index d6bd61057f..5d22e8ecd3 100644
--- a/common/usbc/usb_pd_host.c
+++ b/common/usbc/usb_pd_host.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -15,8 +15,8 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 /* Retrieve all discovery results for the given port and transmit type */
 static enum ec_status hc_typec_discovery(struct host_cmd_handler_args *args)
@@ -35,8 +35,8 @@ static enum ec_status hc_typec_discovery(struct host_cmd_handler_args *args)
 	if (p->partner_type > TYPEC_PARTNER_SOP_PRIME)
 		return EC_RES_INVALID_PARAM;
 
-	type = p->partner_type == TYPEC_PARTNER_SOP ?
-		TCPCI_MSG_SOP : TCPCI_MSG_SOP_PRIME;
+	type = p->partner_type == TYPEC_PARTNER_SOP ? TCPCI_MSG_SOP :
+						      TCPCI_MSG_SOP_PRIME;
 
 	/*
 	 * Clear out access mask so we can track if tasks have touched data
@@ -61,8 +61,9 @@ static enum ec_status hc_typec_discovery(struct host_cmd_handler_args *args)
 
 	if (pd_get_modes_discovery(p->port, type) == PD_DISC_COMPLETE) {
 		int svid_i;
-		int max_resp_svids = (args->response_max - args->response_size)/
-				      sizeof(struct svid_mode_info);
+		int max_resp_svids =
+			(args->response_max - args->response_size) /
+			sizeof(struct svid_mode_info);
 
 		if (disc->svid_cnt > max_resp_svids) {
 			CPRINTS("Warn: SVIDS exceeded HC response");
@@ -74,7 +75,7 @@ static enum ec_status hc_typec_discovery(struct host_cmd_handler_args *args)
 		for (svid_i = 0; svid_i < r->svid_count; svid_i++) {
 			r->svids[svid_i].svid = disc->svids[svid_i].svid;
 			r->svids[svid_i].mode_count =
-						disc->svids[svid_i].mode_cnt;
+				disc->svids[svid_i].mode_cnt;
 			memcpy(r->svids[svid_i].mode_vdo,
 			       disc->svids[svid_i].mode_vdo,
 			       sizeof(r->svids[svid_i].mode_vdo));
@@ -96,14 +97,12 @@ static enum ec_status hc_typec_discovery(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_TYPEC_DISCOVERY,
-		     hc_typec_discovery,
+DECLARE_HOST_COMMAND(EC_CMD_TYPEC_DISCOVERY, hc_typec_discovery,
 		     EC_VER_MASK(0));
 
 /* Default to feature unavailable, with boards supporting it overriding */
 __overridable enum ec_status
-			board_set_tbt_ufp_reply(int port,
-						enum typec_tbt_ufp_reply reply)
+board_set_tbt_ufp_reply(int port, enum typec_tbt_ufp_reply reply)
 {
 	return EC_RES_UNAVAILABLE;
 }
@@ -111,6 +110,7 @@ __overridable enum ec_status
 static enum ec_status hc_typec_control(struct host_cmd_handler_args *args)
 {
 	const struct ec_params_typec_control *p = args->params;
+	mux_state_t mode;
 
 	if (p->port >= board_get_usb_pd_port_count())
 		return EC_RES_INVALID_PARAM;
@@ -127,11 +127,13 @@ static enum ec_status hc_typec_control(struct host_cmd_handler_args *args)
 	case TYPEC_CONTROL_COMMAND_TBT_UFP_REPLY:
 		return board_set_tbt_ufp_reply(p->port, p->tbt_ufp_reply);
 	case TYPEC_CONTROL_COMMAND_USB_MUX_SET:
+		/* The EC will fill in polarity, so filter flip out */
+		mode = p->mux_params.mux_flags & ~USB_PD_MUX_POLARITY_INVERTED;
+
 		if (!IS_ENABLED(CONFIG_USB_MUX_AP_CONTROL))
 			return EC_RES_INVALID_PARAM;
-		/* TODO: Check if AP wants to set usb mode or polarity */
-		usb_mux_set_single(p->port, p->mux_params.mux_index,
-				   p->mux_params.mux_flags,
+
+		usb_mux_set_single(p->port, p->mux_params.mux_index, mode,
 				   USB_SWITCH_CONNECT,
 				   polarity_rm_dts(pd_get_polarity(p->port)));
 		return EC_RES_SUCCESS;
@@ -139,7 +141,6 @@ static enum ec_status hc_typec_control(struct host_cmd_handler_args *args)
 		return EC_RES_INVALID_PARAM;
 	}
 
-
 	return EC_RES_SUCCESS;
 }
 DECLARE_HOST_COMMAND(EC_CMD_TYPEC_CONTROL, hc_typec_control, EC_VER_MASK(0));
@@ -177,13 +178,15 @@ static enum ec_status hc_typec_status(struct host_cmd_handler_args *args)
 	r->events = pd_get_events(p->port);
 
 	r->sop_revision = r->sop_connected ?
-		PD_STATUS_REV_SET_MAJOR(pd_get_rev(p->port, TCPCI_MSG_SOP)) : 0;
+				  PD_STATUS_REV_SET_MAJOR(
+					  pd_get_rev(p->port, TCPCI_MSG_SOP)) :
+				  0;
 	r->sop_prime_revision =
 		pd_get_identity_discovery(p->port, TCPCI_MSG_SOP_PRIME) ==
-		PD_DISC_COMPLETE ?
-		PD_STATUS_REV_SET_MAJOR(pd_get_rev(p->port,
-					TCPCI_MSG_SOP_PRIME))
-		: 0;
+				PD_DISC_COMPLETE ?
+			PD_STATUS_REV_SET_MAJOR(
+				pd_get_rev(p->port, TCPCI_MSG_SOP_PRIME)) :
+			0;
 
 	r->source_cap_count = pd_get_src_cap_cnt(p->port);
 	memcpy(r->source_cap_pdos, pd_get_src_caps(p->port),
diff --git a/common/usbc/usb_pd_timer.c b/common/usbc/usb_pd_timer.c
index a1859ac9e9..a6ec07125d 100644
--- a/common/usbc/usb_pd_timer.c
+++ b/common/usbc/usb_pd_timer.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,36 +14,35 @@
 #include "usb_pd_timer.h"
 #include "usb_tc_sm.h"
 
-#define MAX_PD_PORTS	CONFIG_USB_PD_PORT_MAX_COUNT
-#define MAX_PD_TIMERS	PD_TIMER_COUNT
+#define MAX_PD_PORTS CONFIG_USB_PD_PORT_MAX_COUNT
+#define MAX_PD_TIMERS PD_TIMER_COUNT
 #define PD_TIMERS_ALL_MASK (UINT64_MAX >> (64 - PD_TIMER_COUNT))
 
-#define MAX_EXPIRE	(0x7FFFFFFF)
-#define NO_TIMEOUT	(-1)
-#define EXPIRE_NOW	(0)
+#define MAX_EXPIRE (0x7FFFFFFF)
+#define NO_TIMEOUT (-1)
+#define EXPIRE_NOW (0)
 
 #define PD_SET_ACTIVE(p, bit) \
-	atomic_set_bit(timer_active, (p) * PD_TIMER_COUNT + (bit))
+	atomic_set_bit(timer_active, (p)*PD_TIMER_COUNT + (bit))
 
 #define PD_CLR_ACTIVE(p, bit) \
-	atomic_clear_bit(timer_active, (p) * PD_TIMER_COUNT + (bit))
+	atomic_clear_bit(timer_active, (p)*PD_TIMER_COUNT + (bit))
 
 #define PD_CHK_ACTIVE(p, bit) \
-	atomic_test_bit(timer_active, (p) * PD_TIMER_COUNT + (bit))
+	atomic_test_bit(timer_active, (p)*PD_TIMER_COUNT + (bit))
 
 #define PD_SET_DISABLED(p, bit) \
-	atomic_set_bit(timer_disabled, (p) * PD_TIMER_COUNT + (bit))
+	atomic_set_bit(timer_disabled, (p)*PD_TIMER_COUNT + (bit))
 
 #define PD_CLR_DISABLED(p, bit) \
-	atomic_clear_bit(timer_disabled, (p) * PD_TIMER_COUNT + (bit))
+	atomic_clear_bit(timer_disabled, (p)*PD_TIMER_COUNT + (bit))
 
 #define PD_CHK_DISABLED(p, bit) \
-	atomic_test_bit(timer_disabled, (p) * PD_TIMER_COUNT + (bit))
+	atomic_test_bit(timer_disabled, (p)*PD_TIMER_COUNT + (bit))
 
-test_mockable_static
-ATOMIC_DEFINE(timer_active, PD_TIMER_COUNT * MAX_PD_PORTS);
-test_mockable_static
-ATOMIC_DEFINE(timer_disabled, PD_TIMER_COUNT * MAX_PD_PORTS);
+test_mockable_static ATOMIC_DEFINE(timer_active, PD_TIMER_COUNT *MAX_PD_PORTS);
+test_mockable_static ATOMIC_DEFINE(timer_disabled,
+				   PD_TIMER_COUNT *MAX_PD_PORTS);
 static uint64_t timer_expires[MAX_PD_PORTS][PD_TIMER_COUNT];
 
 /*
@@ -52,42 +51,43 @@ static uint64_t timer_expires[MAX_PD_PORTS][PD_TIMER_COUNT];
 static int count[MAX_PD_PORTS];
 static int max_count[MAX_PD_PORTS];
 
-__maybe_unused static __const_data const char * const pd_timer_names[] = {
-	[PE_TIMER_BIST_CONT_MODE]	= "PE-BIST_CONT_MODE",
+__maybe_unused static __const_data const char *const pd_timer_names[] = {
+	[DPM_TIMER_PD_BUTTON_LONG_PRESS] = "DPM-PD_BUTTON_LONG_PRESS",
+	[DPM_TIMER_PD_BUTTON_SHORT_PRESS] = "DPM-PD_BUTTON_SHORT_PRESS",
+	[PE_TIMER_BIST_CONT_MODE] = "PE-BIST_CONT_MODE",
 	[PE_TIMER_CHUNKING_NOT_SUPPORTED] = "PE-CHUNKING_NOT_SUPPORTED",
-	[PE_TIMER_DISCOVER_IDENTITY]	= "PE-DISCOVER_IDENTITY",
-	[PE_TIMER_NO_RESPONSE]		= "PE-NO_RESPONSE",
-	[PE_TIMER_PR_SWAP_WAIT]		= "PE-PR_SWAP_WAIT",
-	[PE_TIMER_PS_HARD_RESET]	= "PE-PS_HARD_RESET",
-	[PE_TIMER_PS_SOURCE]		= "PE-PS_SOURCE",
-	[PE_TIMER_PS_TRANSITION]	= "PE-PS_TRANSITION",
-	[PE_TIMER_SENDER_RESPONSE]	= "PE-SENDER_RESPONSE",
-	[PE_TIMER_SINK_REQUEST]		= "PE-SINK_REQUEST",
-	[PE_TIMER_SOURCE_CAP]		= "PE-SOURCE_CAP",
-	[PE_TIMER_SRC_TRANSITION]	= "PE-SRC_TRANSITION",
-	[PE_TIMER_SWAP_SOURCE_START]	= "PE-SWAP_SOURCE_START",
-	[PE_TIMER_TIMEOUT]		= "PE-TIMEOUT",
-	[PE_TIMER_VCONN_ON]		= "PE-VCONN_ON",
-	[PE_TIMER_VDM_RESPONSE]		= "PE-VDM_RESPONSE",
-	[PE_TIMER_WAIT_AND_ADD_JITTER]	= "PE-WAIT_AND_ADD_JITTER",
-	[PE_TIMER_VCONN_DISCHARGE]	= "PE-VCONN_DISCHARGE",
-	[PE_TIMER_VCONN_REAPPLIED]	= "PE-VCONN_REAPPLIED",
-	[PE_TIMER_DATA_RESET_FAIL]	= "PE-DATA_RESET_FAIL",
-
-	[PR_TIMER_CHUNK_SENDER_REQUEST]	= "PR-CHUNK_SENDER_REQUEST",
+	[PE_TIMER_DISCOVER_IDENTITY] = "PE-DISCOVER_IDENTITY",
+	[PE_TIMER_NO_RESPONSE] = "PE-NO_RESPONSE",
+	[PE_TIMER_PR_SWAP_WAIT] = "PE-PR_SWAP_WAIT",
+	[PE_TIMER_PS_HARD_RESET] = "PE-PS_HARD_RESET",
+	[PE_TIMER_PS_SOURCE] = "PE-PS_SOURCE",
+	[PE_TIMER_PS_TRANSITION] = "PE-PS_TRANSITION",
+	[PE_TIMER_SENDER_RESPONSE] = "PE-SENDER_RESPONSE",
+	[PE_TIMER_SINK_REQUEST] = "PE-SINK_REQUEST",
+	[PE_TIMER_SOURCE_CAP] = "PE-SOURCE_CAP",
+	[PE_TIMER_SRC_TRANSITION] = "PE-SRC_TRANSITION",
+	[PE_TIMER_SWAP_SOURCE_START] = "PE-SWAP_SOURCE_START",
+	[PE_TIMER_TIMEOUT] = "PE-TIMEOUT",
+	[PE_TIMER_VCONN_ON] = "PE-VCONN_ON",
+	[PE_TIMER_VDM_RESPONSE] = "PE-VDM_RESPONSE",
+	[PE_TIMER_WAIT_AND_ADD_JITTER] = "PE-WAIT_AND_ADD_JITTER",
+	[PE_TIMER_VCONN_DISCHARGE] = "PE-VCONN_DISCHARGE",
+	[PE_TIMER_VCONN_REAPPLIED] = "PE-VCONN_REAPPLIED",
+	[PE_TIMER_DATA_RESET_FAIL] = "PE-DATA_RESET_FAIL",
+
+	[PR_TIMER_CHUNK_SENDER_REQUEST] = "PR-CHUNK_SENDER_REQUEST",
 	[PR_TIMER_CHUNK_SENDER_RESPONSE] = "PR-CHUNK_SENDER_RESPONSE",
-	[PR_TIMER_HARD_RESET_COMPLETE]	= "PR-HARD_RESET_COMPLETE",
-	[PR_TIMER_SINK_TX]		= "PR-SINK_TX",
-	[PR_TIMER_TCPC_TX_TIMEOUT]	= "PR-TCPC_TX_TIMEOUT",
-
-	[TC_TIMER_CC_DEBOUNCE]		= "TC-CC_DEBOUNCE",
-	[TC_TIMER_LOW_POWER_EXIT_TIME]	= "TC-LOW_POWER_EXIT_TIME",
-	[TC_TIMER_LOW_POWER_TIME]	= "TC-LOW_POWER_TIME",
-	[TC_TIMER_NEXT_ROLE_SWAP]	= "TC-NEXT_ROLE_SWAP",
-	[TC_TIMER_PD_DEBOUNCE]		= "TC-PD_DEBOUNCE",
-	[TC_TIMER_TIMEOUT]		= "TC-TIMEOUT",
-	[TC_TIMER_TRY_WAIT_DEBOUNCE]	= "TC-TRY_WAIT_DEBOUNCE",
-	[TC_TIMER_VBUS_DEBOUNCE]	= "TC-VBUS_DEBOUNCE",
+	[PR_TIMER_HARD_RESET_COMPLETE] = "PR-HARD_RESET_COMPLETE",
+	[PR_TIMER_SINK_TX] = "PR-SINK_TX",
+	[PR_TIMER_TCPC_TX_TIMEOUT] = "PR-TCPC_TX_TIMEOUT",
+	[TC_TIMER_CC_DEBOUNCE] = "TC-CC_DEBOUNCE",
+	[TC_TIMER_LOW_POWER_EXIT_TIME] = "TC-LOW_POWER_EXIT_TIME",
+	[TC_TIMER_LOW_POWER_TIME] = "TC-LOW_POWER_TIME",
+	[TC_TIMER_NEXT_ROLE_SWAP] = "TC-NEXT_ROLE_SWAP",
+	[TC_TIMER_PD_DEBOUNCE] = "TC-PD_DEBOUNCE",
+	[TC_TIMER_TIMEOUT] = "TC-TIMEOUT",
+	[TC_TIMER_TRY_WAIT_DEBOUNCE] = "TC-TRY_WAIT_DEBOUNCE",
+	[TC_TIMER_VBUS_DEBOUNCE] = "TC-VBUS_DEBOUNCE",
 };
 
 /*****************************************************************************
@@ -171,17 +171,21 @@ void pd_timer_disable_range(int port, enum pd_timer_range range)
 	enum pd_task_timer timer;
 
 	switch (range) {
+	case DPM_TIMER_RANGE:
+		start = DPM_TIMER_START;
+		end = DPM_TIMER_END;
+		break;
 	case PE_TIMER_RANGE:
-		start	= PE_TIMER_START;
-		end	= PE_TIMER_END;
+		start = PE_TIMER_START;
+		end = PE_TIMER_END;
 		break;
 	case PR_TIMER_RANGE:
-		start	= PR_TIMER_START;
-		end	= PR_TIMER_END;
+		start = PR_TIMER_START;
+		end = PR_TIMER_END;
 		break;
 	case TC_TIMER_RANGE:
-		start	= TC_TIMER_START;
-		end	= TC_TIMER_END;
+		start = TC_TIMER_START;
+		end = TC_TIMER_END;
 		break;
 	default:
 		return;
@@ -253,8 +257,8 @@ test_mockable_static void pd_timer_dump(int port)
 	int timer;
 	uint64_t now = get_time().val;
 
-	ccprints("Timers(%d): cur=%d max=%d",
-		port, count[port], max_count[port]);
+	ccprints("Timers(%d): cur=%d max=%d", port, count[port],
+		 max_count[port]);
 
 	for (timer = 0; timer < PD_TIMER_COUNT; ++timer) {
 		if (pd_timer_is_disabled(port, timer)) {
@@ -265,14 +269,13 @@ test_mockable_static void pd_timer_dump(int port)
 			if (now < timer_expires[port][timer])
 				delta = timer_expires[port][timer] - now;
 
-			ccprints("[%2d] Active:   %s (%d%s)",
-				timer, pd_timer_names[timer], (uint32_t)delta,
-				tc_event_loop_is_paused(port)
-					? "-PAUSED"
-					: "");
+			ccprints("[%2d] Active:   %s (%d%s)", timer,
+				 pd_timer_names[timer], (uint32_t)delta,
+				 tc_event_loop_is_paused(port) ? "-PAUSED" :
+								 "");
 		} else {
-			ccprints("[%2d] Inactive: %s",
-				timer, pd_timer_names[timer]);
+			ccprints("[%2d] Inactive: %s", timer,
+				 pd_timer_names[timer]);
 		}
 	}
 }
diff --git a/common/usbc/usb_pe_ctvpd_sm.c b/common/usbc/usb_pe_ctvpd_sm.c
index 346a57a461..f3f3d8af9b 100644
--- a/common/usbc/usb_pe_ctvpd_sm.c
+++ b/common/usbc/usb_pe_ctvpd_sm.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -167,55 +167,48 @@ static void pe_request_run(const int port)
 		/* Prepare to send ACK */
 
 		/* VDM Header */
-		payload[0] = VDO(
-			USB_VID_GOOGLE,
-			1, /* Structured VDM */
-			VDO_SVDM_VERS(1) |
-			VDO_CMDT(CMDT_RSP_ACK) |
-			CMD_DISCOVER_IDENT);
+		payload[0] = VDO(USB_VID_GOOGLE, 1, /* Structured VDM */
+				 VDO_SVDM_VERS(1) | VDO_CMDT(CMDT_RSP_ACK) |
+					 CMD_DISCOVER_IDENT);
 
 		/* ID Header VDO */
-		payload[1] = VDO_IDH(
-			0, /* Not a USB Host */
-			1, /* Capable of being enumerated as USB Device */
-			IDH_PTYPE_VPD,
-			0, /* Modal Operation Not Supported */
-			USB_VID_GOOGLE);
+		payload[1] = VDO_IDH(0, /* Not a USB Host */
+				     1, /* Capable of being enumerated as USB
+					   Device */
+				     IDH_PTYPE_VPD, 0, /* Modal Operation Not
+							  Supported */
+				     USB_VID_GOOGLE);
 
 		/* Cert State VDO */
 		payload[2] = 0;
 
 		/* Product VDO */
-		payload[3] = VDO_PRODUCT(
-			CONFIG_USB_PID,
-			USB_BCD_DEVICE);
+		payload[3] = VDO_PRODUCT(CONFIG_USB_PID, USB_BCD_DEVICE);
 
 		/* VPD VDO */
 		payload[4] = VDO_VPD(
-			VPD_HW_VERSION,
-			VPD_FW_VERSION,
-			VPD_MAX_VBUS_20V,
-			IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_CT_CURRENT
-						     : 0,
-			IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_VBUS_IMP(
-							VPD_VBUS_IMPEDANCE)
-						     : 0,
-			IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_GND_IMP(
-							VPD_GND_IMPEDANCE)
-						     : 0,
-			IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_CTS_SUPPORTED
-						     : VPD_CTS_NOT_SUPPORTED);
+			VPD_HW_VERSION, VPD_FW_VERSION, VPD_MAX_VBUS_20V,
+			IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_CT_CURRENT : 0,
+			IS_ENABLED(CONFIG_USB_CTVPD) ?
+				VPD_VBUS_IMP(VPD_VBUS_IMPEDANCE) :
+				0,
+			IS_ENABLED(CONFIG_USB_CTVPD) ?
+				VPD_GND_IMP(VPD_GND_IMPEDANCE) :
+				0,
+			IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_CTS_SUPPORTED :
+						       VPD_CTS_NOT_SUPPORTED);
 
 		/* 20 bytes, 5 data objects */
 		tx_emsg[port].len = 20;
 
 		/* Set to highest revision supported by both ports. */
 		prl_set_rev(port, TCPCI_MSG_SOP_PRIME,
-					(PD_HEADER_REV(header) > PD_REV30) ?
-					PD_REV30 : PD_HEADER_REV(header));
+			    (PD_HEADER_REV(header) > PD_REV30) ?
+				    PD_REV30 :
+				    PD_HEADER_REV(header));
 		/* Send the ACK */
 		prl_send_data_msg(port, TCPCI_MSG_SOP_PRIME,
-					PD_DATA_VENDOR_DEF);
+				  PD_DATA_VENDOR_DEF);
 	}
 }
 
diff --git a/common/usbc/usb_pe_drp_sm.c b/common/usbc/usb_pe_drp_sm.c
index baa2c98ec8..1094e4180c 100644
--- a/common/usbc/usb_pe_drp_sm.c
+++ b/common/usbc/usb_pe_drp_sm.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,6 +6,7 @@
 #include "atomic.h"
 #include "battery.h"
 #include "battery_smart.h"
+#include "builtin/assert.h"
 #include "charge_manager.h"
 #include "charge_state.h"
 #include "common.h"
@@ -15,6 +16,7 @@
 #include "ec_commands.h"
 #include "hooks.h"
 #include "host_command.h"
+#include "power_button.h"
 #include "stdbool.h"
 #include "system.h"
 #include "task.h"
@@ -47,41 +49,42 @@
  */
 
 #ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 #else
 #define CPRINTF(format, args...)
 #define CPRINTS(format, args...)
 #endif
 
-#define CPRINTF_LX(x, format, args...) \
-	do { \
-		if (pe_debug_level >= x) \
-			CPRINTF(format, ## args); \
+#define CPRINTF_LX(x, format, args...)           \
+	do {                                     \
+		if (pe_debug_level >= x)         \
+			CPRINTF(format, ##args); \
 	} while (0)
-#define CPRINTF_L1(format, args...) CPRINTF_LX(1, format, ## args)
-#define CPRINTF_L2(format, args...) CPRINTF_LX(2, format, ## args)
-#define CPRINTF_L3(format, args...) CPRINTF_LX(3, format, ## args)
-
-#define CPRINTS_LX(x, format, args...) \
-	do { \
-		if (pe_debug_level >= x) \
-			CPRINTS(format, ## args); \
+#define CPRINTF_L1(format, args...) CPRINTF_LX(1, format, ##args)
+#define CPRINTF_L2(format, args...) CPRINTF_LX(2, format, ##args)
+#define CPRINTF_L3(format, args...) CPRINTF_LX(3, format, ##args)
+
+#define CPRINTS_LX(x, format, args...)           \
+	do {                                     \
+		if (pe_debug_level >= x)         \
+			CPRINTS(format, ##args); \
 	} while (0)
-#define CPRINTS_L1(format, args...) CPRINTS_LX(1, format, ## args)
-#define CPRINTS_L2(format, args...) CPRINTS_LX(2, format, ## args)
-#define CPRINTS_L3(format, args...) CPRINTS_LX(3, format, ## args)
-
-#define PE_SET_FN(port, _fn) atomic_or(ATOMIC_ELEM(pe[port].flags_a, (_fn)), \
-				       ATOMIC_MASK(_fn))
-#define PE_CLR_FN(port, _fn) atomic_clear_bits(ATOMIC_ELEM(pe[port].flags_a, \
-						(_fn)), ATOMIC_MASK(_fn))
-#define PE_CHK_FN(port, _fn) (pe[port].flags_a[ATOMIC_ELEM(0, (_fn))] & \
-			      ATOMIC_MASK(_fn))
-
-#define PE_SET_FLAG(port, name) PE_SET_FN(port, (name ## _FN))
-#define PE_CLR_FLAG(port, name) PE_CLR_FN(port, (name ## _FN))
-#define PE_CHK_FLAG(port, name) PE_CHK_FN(port, (name ## _FN))
+#define CPRINTS_L1(format, args...) CPRINTS_LX(1, format, ##args)
+#define CPRINTS_L2(format, args...) CPRINTS_LX(2, format, ##args)
+#define CPRINTS_L3(format, args...) CPRINTS_LX(3, format, ##args)
+
+#define PE_SET_FN(port, _fn) \
+	atomic_or(ATOMIC_ELEM(pe[port].flags_a, (_fn)), ATOMIC_MASK(_fn))
+#define PE_CLR_FN(port, _fn)                                    \
+	atomic_clear_bits(ATOMIC_ELEM(pe[port].flags_a, (_fn)), \
+			  ATOMIC_MASK(_fn))
+#define PE_CHK_FN(port, _fn) \
+	(pe[port].flags_a[ATOMIC_ELEM(0, (_fn))] & ATOMIC_MASK(_fn))
+
+#define PE_SET_FLAG(port, name) PE_SET_FN(port, (name##_FN))
+#define PE_CLR_FLAG(port, name) PE_CLR_FN(port, (name##_FN))
+#define PE_CHK_FLAG(port, name) PE_CHK_FN(port, (name##_FN))
 
 /*
  * TODO(b/229655319): support more than 32 bits
@@ -99,10 +102,11 @@
 #define PE_CHK_DPM_REQUEST(port, req) (pe[port].dpm_request & (req))
 
 /* Message flags which should not persist on returning to ready state */
-#define PE_MASK_READY_CLR	(BIT(PE_FLAGS_LOCALLY_INITIATED_AMS_FN) | \
-				 BIT(PE_FLAGS_MSG_DISCARDED_FN) |	\
-				 BIT(PE_FLAGS_VDM_REQUEST_TIMEOUT_FN) |	\
-				 BIT(PE_FLAGS_INTERRUPTIBLE_AMS_FN))
+#define PE_MASK_READY_CLR                         \
+	(BIT(PE_FLAGS_LOCALLY_INITIATED_AMS_FN) | \
+	 BIT(PE_FLAGS_MSG_DISCARDED_FN) |         \
+	 BIT(PE_FLAGS_VDM_REQUEST_TIMEOUT_FN) |   \
+	 BIT(PE_FLAGS_INTERRUPTIBLE_AMS_FN))
 
 /*
  * Combination to check whether a reply to a message was received.  Our message
@@ -113,8 +117,9 @@
  * on the same run cycle.  With chunking, received message will take an
  * additional cycle to be flagged.
  */
-#define PE_CHK_REPLY(port)	(PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED) && \
-				 !PE_CHK_FLAG(port, PE_FLAGS_MSG_DISCARDED))
+#define PE_CHK_REPLY(port)                           \
+	(PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED) && \
+	 !PE_CHK_FLAG(port, PE_FLAGS_MSG_DISCARDED))
 /* 6.7.3 Hard Reset Counter */
 #define N_HARD_RESET_COUNT 2
 
@@ -136,20 +141,20 @@
  * solely from VCONN. Limit the number of retries without a contract to
  * ensure we attempt some cable discovery after a contract is in place.
  */
-#define N_DISCOVER_IDENTITY_PRECONTRACT_LIMIT	2
+#define N_DISCOVER_IDENTITY_PRECONTRACT_LIMIT 2
 
 /*
  * Once this limit of SOP' Discover Identity messages has been set, downgrade
  * to PD 2.0 in case the cable is non-compliant about GoodCRC-ing higher
  * revisions.  This limit should be higher than the precontract limit.
  */
-#define N_DISCOVER_IDENTITY_PD3_0_LIMIT		4
+#define N_DISCOVER_IDENTITY_PD3_0_LIMIT 4
 
 /*
  * tDiscoverIdentity is only defined while an explicit contract is in place, so
  * extend the interval between retries pre-contract.
  */
-#define PE_T_DISCOVER_IDENTITY_NO_CONTRACT	(200*MSEC)
+#define PE_T_DISCOVER_IDENTITY_NO_CONTRACT (200 * MSEC)
 
 /*
  * Only VCONN source can communicate with the cable plug. Hence, try VCONN swap
@@ -278,6 +283,7 @@ enum usb_pe_state {
 	PE_GIVE_BATTERY_STATUS,
 	PE_GIVE_STATUS,
 	PE_SEND_ALERT,
+	PE_ALERT_RECEIVED,
 	PE_SRC_CHUNK_RECEIVED,
 	PE_SNK_CHUNK_RECEIVED,
 	PE_VCS_FORCE_VCONN,
@@ -316,15 +322,14 @@ static const struct usb_state pe_states[];
  * If we can't print or the CONFIG_USB_PD_DEBUG_LEVEL is defined to be 0
  * then the DEBUG LABELS will be removed from the build.
  */
-#if defined(CONFIG_COMMON_RUNTIME) && \
-	(!defined(CONFIG_USB_PD_DEBUG_LEVEL) || \
-	 (CONFIG_USB_PD_DEBUG_LEVEL > 0))
+#if defined(CONFIG_COMMON_RUNTIME) && (!defined(CONFIG_USB_PD_DEBUG_LEVEL) || \
+				       (CONFIG_USB_PD_DEBUG_LEVEL > 0))
 #define USB_PD_DEBUG_LABELS
 #endif
 
 /* List of human readable state names for console debugging */
-__maybe_unused static __const_data const char * const pe_state_names[] = {
-	/* Super States */
+__maybe_unused static __const_data const char *const pe_state_names[] = {
+/* Super States */
 #ifdef CONFIG_USB_PD_REV30
 	[PE_PRS_FRS_SHARED] = "SS:PE_PRS_FRS_SHARED",
 #endif
@@ -381,7 +386,7 @@ __maybe_unused static __const_data const char * const pe_state_names[] = {
 #endif
 	[PE_VDM_IDENTITY_REQUEST_CBL] = "PE_VDM_Identity_Request_Cbl",
 	[PE_INIT_PORT_VDM_IDENTITY_REQUEST] =
-					   "PE_INIT_PORT_VDM_Identity_Request",
+		"PE_INIT_PORT_VDM_Identity_Request",
 	[PE_INIT_VDM_SVIDS_REQUEST] = "PE_INIT_VDM_SVIDs_Request",
 	[PE_INIT_VDM_MODES_REQUEST] = "PE_INIT_VDM_Modes_Request",
 	[PE_VDM_REQUEST_DPM] = "PE_VDM_Request_DPM",
@@ -389,12 +394,12 @@ __maybe_unused static __const_data const char * const pe_state_names[] = {
 	[PE_HANDLE_CUSTOM_VDM_REQUEST] = "PE_Handle_Custom_Vdm_Request",
 	[PE_WAIT_FOR_ERROR_RECOVERY] = "PE_Wait_For_Error_Recovery",
 	[PE_BIST_TX] = "PE_Bist_TX",
-	[PE_DEU_SEND_ENTER_USB]  = "PE_DEU_Send_Enter_USB",
+	[PE_DEU_SEND_ENTER_USB] = "PE_DEU_Send_Enter_USB",
 	[PE_DR_GET_SINK_CAP] = "PE_DR_Get_Sink_Cap",
 	[PE_DR_SNK_GIVE_SOURCE_CAP] = "PE_DR_SNK_Give_Source_Cap",
 	[PE_DR_SRC_GET_SOURCE_CAP] = "PE_DR_SRC_Get_Source_Cap",
 
-	/* PD3.0 only states below here*/
+/* PD3.0 only states below here*/
 #ifdef CONFIG_USB_PD_REV30
 	[PE_FRS_SNK_SRC_START_AMS] = "PE_FRS_SNK_SRC_Start_Ams",
 	[PE_GET_REVISION] = "PE_Get_Revision",
@@ -403,6 +408,7 @@ __maybe_unused static __const_data const char * const pe_state_names[] = {
 	[PE_GIVE_BATTERY_STATUS] = "PE_Give_Battery_Status",
 	[PE_GIVE_STATUS] = "PE_Give_Status",
 	[PE_SEND_ALERT] = "PE_Send_Alert",
+	[PE_ALERT_RECEIVED] = "PE_Alert_Received",
 #else
 	[PE_SRC_CHUNK_RECEIVED] = "PE_SRC_Chunk_Received",
 	[PE_SNK_CHUNK_RECEIVED] = "PE_SNK_Chunk_Received",
@@ -416,7 +422,7 @@ __maybe_unused static __const_data const char * const pe_state_names[] = {
 	[PE_UDR_TURN_OFF_VCONN] = "PE_UDR_Turn_Off_VCONN",
 	[PE_UDR_SEND_PS_RDY] = "PE_UDR_Send_Ps_Rdy",
 	[PE_UDR_WAIT_FOR_DATA_RESET_COMPLETE] =
-				"PE_UDR_Wait_For_Data_Reset_Complete",
+		"PE_UDR_Wait_For_Data_Reset_Complete",
 	[PE_DDR_SEND_DATA_RESET] = "PE_DDR_Send_Data_Reset",
 	[PE_DDR_DATA_RESET_RECEIVED] = "PE_DDR_Data_Reset_Received",
 	[PE_DDR_WAIT_FOR_VCONN_OFF] = "PE_DDR_Wait_For_VCONN_Off",
@@ -451,6 +457,8 @@ GEN_NOT_SUPPORTED(PE_SNK_CHUNK_RECEIVED);
 #define PE_SNK_CHUNK_RECEIVED PE_SNK_CHUNK_RECEIVED_NOT_SUPPORTED
 GEN_NOT_SUPPORTED(PE_GET_REVISION);
 #define PE_GET_REVISION PE_GET_REVISION_NOT_SUPPORTED
+GEN_NOT_SUPPORTED(PE_ALERT_RECEIVED);
+#define PE_ALERT_RECEIVED PE_ALERT_RECEIVED_NOT_SUPPORTED
 #endif /* CONFIG_USB_PD_REV30 */
 
 #if !defined(CONFIG_USBC_VCONN) || !defined(CONFIG_USB_PD_REV30)
@@ -529,12 +537,12 @@ static enum sm_local_state local_state[CONFIG_USB_PD_PORT_MAX_COUNT];
  *                        what ever is needed to handle the Discard.
  */
 enum pe_msg_check {
-	PE_MSG_SEND_PENDING	= BIT(0),
-	PE_MSG_SENT		= BIT(1),
-	PE_MSG_DISCARDED	= BIT(2),
+	PE_MSG_SEND_PENDING = BIT(0),
+	PE_MSG_SENT = BIT(1),
+	PE_MSG_DISCARDED = BIT(2),
 
-	PE_MSG_SEND_COMPLETED	= BIT(3) | PE_MSG_SENT,
-	PE_MSG_DPM_DISCARDED	= BIT(4) | PE_MSG_DISCARDED,
+	PE_MSG_SEND_COMPLETED = BIT(3) | PE_MSG_SENT,
+	PE_MSG_DPM_DISCARDED = BIT(4) | PE_MSG_DISCARDED,
 };
 static void pe_sender_response_msg_entry(const int port);
 static enum pe_msg_check pe_sender_response_msg_run(const int port);
@@ -543,6 +551,8 @@ static void pe_sender_response_msg_exit(const int port);
 /* Debug log level - higher number == more log */
 #ifdef CONFIG_USB_PD_DEBUG_LEVEL
 static const enum debug_level pe_debug_level = CONFIG_USB_PD_DEBUG_LEVEL;
+#elif defined(CONFIG_USB_PD_INITIAL_DEBUG_LEVEL)
+static enum debug_level pe_debug_level = CONFIG_USB_PD_INITIAL_DEBUG_LEVEL;
 #else
 static enum debug_level pe_debug_level = DEBUG_LEVEL_1;
 #endif
@@ -654,7 +664,7 @@ static struct policy_engine {
 
 	/* Attached ChromeOS device id, RW hash, and current RO / RW image */
 	uint16_t dev_id;
-	uint32_t dev_rw_hash[PD_RW_HASH_SIZE/4];
+	uint32_t dev_rw_hash[PD_RW_HASH_SIZE / 4];
 	enum ec_image current_image;
 } pe[CONFIG_USB_PD_PORT_MAX_COUNT];
 
@@ -713,8 +723,8 @@ static inline void send_data_msg(int port, enum tcpci_msg_type type,
 	prl_send_data_msg(port, type, msg);
 }
 
-static __maybe_unused inline void send_ext_data_msg(
-	int port, enum tcpci_msg_type type, enum pd_ext_msg_type msg)
+static __maybe_unused inline void
+send_ext_data_msg(int port, enum tcpci_msg_type type, enum pd_ext_msg_type msg)
 {
 	/* Clear any previous TX status before sending a new message */
 	PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
@@ -744,15 +754,15 @@ static void init_cable_rev(int port)
 	 * also be PD 2.0
 	 */
 	if (prl_get_rev(port, TCPCI_MSG_SOP) == PD_REV20) {
-	/*
-	 * If the cable supports PD 3.0, but the port partner supports PD 2.0,
-	 * redo the cable discover with PD 2.0
-	 */
+		/*
+		 * If the cable supports PD 3.0, but the port partner supports
+		 * PD 2.0, redo the cable discover with PD 2.0
+		 */
 		if (prl_get_rev(port, TCPCI_MSG_SOP_PRIME) == PD_REV30 &&
 		    pd_get_identity_discovery(port, TCPCI_MSG_SOP_PRIME) ==
-					PD_DISC_COMPLETE) {
+			    PD_DISC_COMPLETE) {
 			pd_set_identity_discovery(port, TCPCI_MSG_SOP_PRIME,
-					PD_DISC_NEEDED);
+						  PD_DISC_NEEDED);
 		}
 		set_cable_rev(port, PD_REV20);
 	}
@@ -850,8 +860,8 @@ void pe_run(int port, int evt, int en)
 						   DPM_REQUEST_HARD_RESET_SEND);
 				set_state_pe(port, PE_WAIT_FOR_ERROR_RECOVERY);
 			} else {
-				pe_set_dpm_curr_request(port,
-						DPM_REQUEST_HARD_RESET_SEND);
+				pe_set_dpm_curr_request(
+					port, DPM_REQUEST_HARD_RESET_SEND);
 				pe_set_hard_reset(port);
 			}
 		}
@@ -864,7 +874,7 @@ void pe_run(int port, int evt, int en)
 		 * make sure to handle it immediately.
 		 */
 		if (IS_ENABLED(CONFIG_USB_PD_REV30) &&
-		PE_CHK_FLAG(port, PE_FLAGS_FAST_ROLE_SWAP_SIGNALED)) {
+		    PE_CHK_FLAG(port, PE_FLAGS_FAST_ROLE_SWAP_SIGNALED)) {
 			PE_CLR_FLAG(port, PE_FLAGS_FAST_ROLE_SWAP_SIGNALED);
 			set_state_pe(port, PE_FRS_SNK_SRC_START_AMS);
 		}
@@ -968,13 +978,13 @@ static void pe_set_frs_enable(int port, int enable)
 
 	pd_set_frs_enable(port, enable);
 	if (enable) {
-		int curr_limit = *pd_get_snk_caps(port)
-						& PDO_FIXED_FRS_CURR_MASK;
+		int curr_limit = *pd_get_snk_caps(port) &
+				 PDO_FIXED_FRS_CURR_MASK;
 
-		typec_select_src_current_limit_rp(port,
-						  curr_limit ==
-						  PDO_FIXED_FRS_CURR_3A0_AT_5V ?
-						  TYPEC_RP_3A0 : TYPEC_RP_1A5);
+		typec_select_src_current_limit_rp(
+			port, curr_limit == PDO_FIXED_FRS_CURR_3A0_AT_5V ?
+				      TYPEC_RP_3A0 :
+				      TYPEC_RP_1A5);
 		PE_SET_FLAG(port, PE_FLAGS_FAST_ROLE_SWAP_ENABLED);
 	} else {
 		PE_CLR_FLAG(port, PE_FLAGS_FAST_ROLE_SWAP_ENABLED);
@@ -1026,7 +1036,7 @@ void pe_set_snk_caps(int port, int cnt, uint32_t *snk_caps)
 	memcpy(pe[port].snk_caps, snk_caps, sizeof(uint32_t) * cnt);
 }
 
-const uint32_t * const pd_get_snk_caps(int port)
+const uint32_t *const pd_get_snk_caps(int port)
 {
 	return pe[port].snk_caps;
 }
@@ -1066,12 +1076,12 @@ static bool pe_can_send_sop_prime(int port)
 		if (PE_CHK_FLAG(port, PE_FLAGS_EXPLICIT_CONTRACT)) {
 			if (prl_get_rev(port, TCPCI_MSG_SOP) == PD_REV20)
 				return tc_is_vconn_src(port) &&
-					pe[port].data_role == PD_ROLE_DFP;
+				       pe[port].data_role == PD_ROLE_DFP;
 			else
 				return tc_is_vconn_src(port);
 		} else {
 			return tc_is_vconn_src(port) &&
-				pe[port].power_role == PD_ROLE_SOURCE;
+			       pe[port].power_role == PD_ROLE_SOURCE;
 		}
 	} else {
 		return false;
@@ -1146,9 +1156,9 @@ static bool pe_check_outgoing_discard(int port)
 	 * Version 2.0 Specification.
 	 */
 	if (PE_CHK_FLAG(port, PE_FLAGS_MSG_DISCARDED) &&
-				PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
+	    PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
 		enum tcpci_msg_type sop =
-				PD_HEADER_GET_SOP(rx_emsg[port].header);
+			PD_HEADER_GET_SOP(rx_emsg[port].header);
 
 		PE_CLR_FLAG(port, PE_FLAGS_MSG_DISCARDED);
 		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
@@ -1190,28 +1200,26 @@ void pe_report_error(int port, enum pe_error e, enum tcpci_msg_type type)
 	 * TODO(b/150774779): TCPMv2: Improve pe_error documentation
 	 */
 	if ((get_state_pe(port) == PE_SRC_SEND_CAPABILITIES ||
-			get_state_pe(port) == PE_SRC_TRANSITION_SUPPLY ||
-			get_state_pe(port) == PE_PRS_SNK_SRC_EVALUATE_SWAP ||
-			get_state_pe(port) == PE_PRS_SNK_SRC_SOURCE_ON ||
-			get_state_pe(port) == PE_PRS_SRC_SNK_WAIT_SOURCE_ON ||
-			get_state_pe(port) == PE_SRC_DISABLED ||
-			get_state_pe(port) == PE_SRC_DISCOVERY ||
-			get_state_pe(port) == PE_VCS_CBL_SEND_SOFT_RESET ||
-			get_state_pe(port) == PE_VDM_IDENTITY_REQUEST_CBL) ||
-			(IS_ENABLED(CONFIG_USB_PD_DATA_RESET_MSG) &&
-			 (get_state_pe(port) == PE_UDR_SEND_DATA_RESET ||
-			  get_state_pe(port) == PE_UDR_DATA_RESET_RECEIVED ||
-			  get_state_pe(port) == PE_UDR_TURN_OFF_VCONN ||
-			  get_state_pe(port) == PE_UDR_SEND_PS_RDY ||
-			  get_state_pe(port) ==
-			  PE_UDR_WAIT_FOR_DATA_RESET_COMPLETE ||
-			  get_state_pe(port) == PE_DDR_SEND_DATA_RESET ||
-			  get_state_pe(port) == PE_DDR_DATA_RESET_RECEIVED ||
-			  get_state_pe(port) == PE_DDR_WAIT_FOR_VCONN_OFF ||
-			  get_state_pe(port) == PE_DDR_PERFORM_DATA_RESET)) ||
-			(pe_in_frs_mode(port) &&
-			    get_state_pe(port) == PE_PRS_SNK_SRC_SEND_SWAP)
-			) {
+	     get_state_pe(port) == PE_SRC_TRANSITION_SUPPLY ||
+	     get_state_pe(port) == PE_PRS_SNK_SRC_EVALUATE_SWAP ||
+	     get_state_pe(port) == PE_PRS_SNK_SRC_SOURCE_ON ||
+	     get_state_pe(port) == PE_PRS_SRC_SNK_WAIT_SOURCE_ON ||
+	     get_state_pe(port) == PE_SRC_DISABLED ||
+	     get_state_pe(port) == PE_SRC_DISCOVERY ||
+	     get_state_pe(port) == PE_VCS_CBL_SEND_SOFT_RESET ||
+	     get_state_pe(port) == PE_VDM_IDENTITY_REQUEST_CBL) ||
+	    (IS_ENABLED(CONFIG_USB_PD_DATA_RESET_MSG) &&
+	     (get_state_pe(port) == PE_UDR_SEND_DATA_RESET ||
+	      get_state_pe(port) == PE_UDR_DATA_RESET_RECEIVED ||
+	      get_state_pe(port) == PE_UDR_TURN_OFF_VCONN ||
+	      get_state_pe(port) == PE_UDR_SEND_PS_RDY ||
+	      get_state_pe(port) == PE_UDR_WAIT_FOR_DATA_RESET_COMPLETE ||
+	      get_state_pe(port) == PE_DDR_SEND_DATA_RESET ||
+	      get_state_pe(port) == PE_DDR_DATA_RESET_RECEIVED ||
+	      get_state_pe(port) == PE_DDR_WAIT_FOR_VCONN_OFF ||
+	      get_state_pe(port) == PE_DDR_PERFORM_DATA_RESET)) ||
+	    (pe_in_frs_mode(port) &&
+	     get_state_pe(port) == PE_PRS_SNK_SRC_SEND_SWAP)) {
 		PE_SET_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
 		task_wake(PD_PORT_TO_TASK_ID(port));
 		return;
@@ -1234,10 +1242,10 @@ void pe_report_error(int port, enum pe_error e, enum tcpci_msg_type type)
 	 */
 	/* All error types besides transmit errors are Protocol Errors. */
 	if ((e != ERR_TCH_XMIT &&
-				!PE_CHK_FLAG(port, PE_FLAGS_INTERRUPTIBLE_AMS))
-			|| e == ERR_TCH_XMIT
-			|| (!PE_CHK_FLAG(port, PE_FLAGS_EXPLICIT_CONTRACT) &&
-				type == TCPCI_MSG_SOP)) {
+	     !PE_CHK_FLAG(port, PE_FLAGS_INTERRUPTIBLE_AMS)) ||
+	    e == ERR_TCH_XMIT ||
+	    (!PE_CHK_FLAG(port, PE_FLAGS_EXPLICIT_CONTRACT) &&
+	     type == TCPCI_MSG_SOP)) {
 		pe_send_soft_reset(port, type);
 	}
 	/*
@@ -1262,7 +1270,7 @@ void pe_got_soft_reset(int port)
 }
 
 __overridable bool pd_can_charge_from_device(int port, const int pdo_cnt,
-				      const uint32_t *pdos)
+					     const uint32_t *pdos)
 {
 	/*
 	 * Don't attempt to charge from a device we have no SrcCaps from. Or, if
@@ -1292,9 +1300,7 @@ __overridable bool pd_can_charge_from_device(int port, const int pdo_cnt,
 		 * Get max power that the partner offers (not necessarily what
 		 * this board will request)
 		 */
-		pd_find_pdo_index(pdo_cnt, pdos,
-				  PD_REV3_MAX_VOLTAGE,
-				  &max_pdo);
+		pd_find_pdo_index(pdo_cnt, pdos, PD_REV3_MAX_VOLTAGE, &max_pdo);
 		pd_extract_pdo_power(max_pdo, &max_ma, &max_mv, &unused);
 		max_mw = max_ma * max_mv / 1000;
 
@@ -1351,14 +1357,15 @@ void pe_message_sent(int port)
 }
 
 void pd_send_vdm(int port, uint32_t vid, int cmd, const uint32_t *data,
-						int count)
+		 int count)
 {
 	/* Copy VDM Header */
 	pe[port].vdm_data[0] =
-		VDO(vid, ((vid & USB_SID_PD) == USB_SID_PD) ?  1 :
-				(PD_VDO_CMD(cmd) <= CMD_ATTENTION),
-			VDO_SVDM_VERS(pd_get_vdo_ver(port, TCPCI_MSG_SOP)) |
-				cmd);
+		VDO(vid,
+		    ((vid & USB_SID_PD) == USB_SID_PD) ?
+			    1 :
+			    (PD_VDO_CMD(cmd) <= CMD_ATTENTION),
+		    VDO_SVDM_VERS(pd_get_vdo_ver(port, TCPCI_MSG_SOP)) | cmd);
 
 	/*
 	 * Copy VDOs after the VDM Header. Note that the count refers to VDO
@@ -1485,21 +1492,21 @@ static void pe_update_waiting_batt_flag(void)
 			 * flag and perform Hard Reset.
 			 */
 			PE_CLR_FLAG(i, PE_FLAGS_SNK_WAITING_BATT);
-			CPRINTS("C%d: Battery has enough charge (%d%%) " \
-			    "to withstand a hard reset", i, batt_soc);
+			CPRINTS("C%d: Battery has enough charge (%d%%) "
+				"to withstand a hard reset",
+				i, batt_soc);
 			pd_dpm_request(i, DPM_REQUEST_HARD_RESET_SEND);
 		}
 	}
 }
 DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, pe_update_waiting_batt_flag,
-							HOOK_PRIO_DEFAULT);
+	     HOOK_PRIO_DEFAULT);
 #endif
 
 /*
  * Private functions
  */
-static void pe_set_dpm_curr_request(const int port,
-				    const int request)
+static void pe_set_dpm_curr_request(const int port, const int request)
 {
 	PE_CLR_DPM_REQUEST(port, request);
 	pe[port].dpm_curr_request = request;
@@ -1527,33 +1534,24 @@ test_export_static enum usb_pe_state get_state_pe(const int port)
  */
 static bool common_src_snk_dpm_requests(int port)
 {
-	if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES) &&
-			PE_CHK_DPM_REQUEST(port, DPM_REQUEST_SEND_ALERT)) {
-		pe_set_dpm_curr_request(port, DPM_REQUEST_SEND_ALERT);
-		set_state_pe(port, PE_SEND_ALERT);
-		return true;
-	} else if (IS_ENABLED(CONFIG_USBC_VCONN) &&
-			PE_CHK_DPM_REQUEST(port, DPM_REQUEST_VCONN_SWAP)) {
+	if (IS_ENABLED(CONFIG_USBC_VCONN) &&
+	    PE_CHK_DPM_REQUEST(port, DPM_REQUEST_VCONN_SWAP)) {
 		pe_set_dpm_curr_request(port, DPM_REQUEST_VCONN_SWAP);
 		set_state_pe(port, PE_VCS_SEND_SWAP);
 		return true;
-	} else if (PE_CHK_DPM_REQUEST(port,
-					DPM_REQUEST_BIST_TX)) {
+	} else if (PE_CHK_DPM_REQUEST(port, DPM_REQUEST_BIST_TX)) {
 		pe_set_dpm_curr_request(port, DPM_REQUEST_BIST_TX);
 		set_state_pe(port, PE_BIST_TX);
 		return true;
-	} else if (PE_CHK_DPM_REQUEST(port,
-					DPM_REQUEST_SNK_STARTUP)) {
+	} else if (PE_CHK_DPM_REQUEST(port, DPM_REQUEST_SNK_STARTUP)) {
 		pe_set_dpm_curr_request(port, DPM_REQUEST_SNK_STARTUP);
 		set_state_pe(port, PE_SNK_STARTUP);
 		return true;
-	} else if (PE_CHK_DPM_REQUEST(port,
-					DPM_REQUEST_SRC_STARTUP)) {
+	} else if (PE_CHK_DPM_REQUEST(port, DPM_REQUEST_SRC_STARTUP)) {
 		pe_set_dpm_curr_request(port, DPM_REQUEST_SRC_STARTUP);
 		set_state_pe(port, PE_SRC_STARTUP);
 		return true;
-	} else if (PE_CHK_DPM_REQUEST(port,
-					DPM_REQUEST_SOFT_RESET_SEND)) {
+	} else if (PE_CHK_DPM_REQUEST(port, DPM_REQUEST_SOFT_RESET_SEND)) {
 		pe_set_dpm_curr_request(port, DPM_REQUEST_SOFT_RESET_SEND);
 		/* Currently only support sending soft reset to SOP */
 		pe_send_soft_reset(port, TCPCI_MSG_SOP);
@@ -1593,14 +1591,13 @@ static bool common_src_snk_dpm_requests(int port)
 		dpm_set_mode_exit_request(port);
 		return true;
 	} else if (PE_CHK_DPM_REQUEST(port, DPM_REQUEST_GET_SNK_CAPS)) {
-		pe_set_dpm_curr_request(port,
-					DPM_REQUEST_GET_SNK_CAPS);
+		pe_set_dpm_curr_request(port, DPM_REQUEST_GET_SNK_CAPS);
 		set_state_pe(port, PE_DR_GET_SINK_CAP);
 		return true;
 	} else if (PE_CHK_DPM_REQUEST(port,
 				      DPM_REQUEST_SOP_PRIME_SOFT_RESET_SEND)) {
 		pe_set_dpm_curr_request(port,
-			DPM_REQUEST_SOP_PRIME_SOFT_RESET_SEND);
+					DPM_REQUEST_SOP_PRIME_SOFT_RESET_SEND);
 		pe[port].tx_type = TCPCI_MSG_SOP_PRIME;
 		set_state_pe(port, PE_VCS_CBL_SEND_SOFT_RESET);
 		return true;
@@ -1617,8 +1614,9 @@ static bool common_src_snk_dpm_requests(int port)
 			set_state_pe(port, PE_DRS_SEND_SWAP);
 		return true;
 	} else if (IS_ENABLED(CONFIG_USB_PD_DATA_RESET_MSG) &&
-			PE_CHK_DPM_REQUEST(port, DPM_REQUEST_DATA_RESET)) {
+		   PE_CHK_DPM_REQUEST(port, DPM_REQUEST_DATA_RESET)) {
 		if (prl_get_rev(port, TCPCI_MSG_SOP) < PD_REV30) {
+			PE_CLR_DPM_REQUEST(port, DPM_REQUEST_DATA_RESET);
 			dpm_data_reset_complete(port);
 			return false;
 		}
@@ -1631,9 +1629,22 @@ static bool common_src_snk_dpm_requests(int port)
 		return true;
 	} else if (IS_ENABLED(CONFIG_USB_PD_REV30) &&
 		   PE_CHK_DPM_REQUEST(port, DPM_REQUEST_GET_REVISION)) {
+		if (prl_get_rev(port, TCPCI_MSG_SOP) < PD_REV30) {
+			PE_CLR_DPM_REQUEST(port, DPM_REQUEST_GET_REVISION);
+			return false;
+		}
 		pe_set_dpm_curr_request(port, DPM_REQUEST_GET_REVISION);
 		set_state_pe(port, PE_GET_REVISION);
 		return true;
+	} else if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES) &&
+		   PE_CHK_DPM_REQUEST(port, DPM_REQUEST_SEND_ALERT)) {
+		if (prl_get_rev(port, TCPCI_MSG_SOP) < PD_REV30) {
+			PE_CLR_DPM_REQUEST(port, DPM_REQUEST_SEND_ALERT);
+			return false;
+		}
+		pe_set_dpm_curr_request(port, DPM_REQUEST_SEND_ALERT);
+		set_state_pe(port, PE_SEND_ALERT);
+		return true;
 	}
 
 	return false;
@@ -1654,9 +1665,9 @@ static bool source_dpm_requests(int port)
 	 *   DPM_REQURST_FRS_DET_DISABLE
 	 */
 	PE_CLR_DPM_REQUEST(port, DPM_REQUEST_NEW_POWER_LEVEL |
-				 DPM_REQUEST_SOURCE_CAP |
-				 DPM_REQUEST_FRS_DET_ENABLE |
-				 DPM_REQUEST_FRS_DET_DISABLE);
+					 DPM_REQUEST_SOURCE_CAP |
+					 DPM_REQUEST_FRS_DET_ENABLE |
+					 DPM_REQUEST_FRS_DET_DISABLE);
 
 	if (pe[port].dpm_request) {
 		uint32_t dpm_request = pe[port].dpm_request;
@@ -1668,8 +1679,7 @@ static bool source_dpm_requests(int port)
 			set_state_pe(port, PE_PRS_SRC_SNK_SEND_SWAP);
 			return true;
 		} else if (PE_CHK_DPM_REQUEST(port, DPM_REQUEST_GOTO_MIN)) {
-			pe_set_dpm_curr_request(port,
-						DPM_REQUEST_GOTO_MIN);
+			pe_set_dpm_curr_request(port, DPM_REQUEST_GOTO_MIN);
 			set_state_pe(port, PE_SRC_TRANSITION_SUPPLY);
 			return true;
 		} else if (PE_CHK_DPM_REQUEST(port,
@@ -1679,21 +1689,18 @@ static bool source_dpm_requests(int port)
 			set_state_pe(port, PE_SRC_SEND_CAPABILITIES);
 			return true;
 		} else if (PE_CHK_DPM_REQUEST(port, DPM_REQUEST_GET_SRC_CAPS)) {
-			pe_set_dpm_curr_request(port,
-						DPM_REQUEST_GET_SRC_CAPS);
+			pe_set_dpm_curr_request(port, DPM_REQUEST_GET_SRC_CAPS);
 			set_state_pe(port, PE_DR_SRC_GET_SOURCE_CAP);
 			return true;
 		} else if (PE_CHK_DPM_REQUEST(port, DPM_REQUEST_SEND_PING)) {
-			pe_set_dpm_curr_request(port,
-						DPM_REQUEST_SEND_PING);
+			pe_set_dpm_curr_request(port, DPM_REQUEST_SEND_PING);
 			set_state_pe(port, PE_SRC_PING);
 			return true;
 		} else if (common_src_snk_dpm_requests(port)) {
 			return true;
 		}
 
-		CPRINTF("Unhandled DPM Request %x received\n",
-			dpm_request);
+		CPRINTF("Unhandled DPM Request %x received\n", dpm_request);
 		PE_CLR_DPM_REQUEST(port, dpm_request);
 		PE_CLR_FLAG(port, PE_FLAGS_LOCALLY_INITIATED_AMS);
 	}
@@ -1714,8 +1721,8 @@ static bool sink_dpm_requests(int port)
 	 *   DPM_REQUEST_SEND_PING
 	 */
 	PE_CLR_DPM_REQUEST(port, DPM_REQUEST_GOTO_MIN |
-			   DPM_REQUEST_SRC_CAP_CHANGE |
-			   DPM_REQUEST_SEND_PING);
+					 DPM_REQUEST_SRC_CAP_CHANGE |
+					 DPM_REQUEST_SEND_PING);
 
 	if (pe[port].dpm_request) {
 		uint32_t dpm_request = pe[port].dpm_request;
@@ -1727,8 +1734,7 @@ static bool sink_dpm_requests(int port)
 			set_state_pe(port, PE_PRS_SNK_SRC_SEND_SWAP);
 			return true;
 		} else if (PE_CHK_DPM_REQUEST(port, DPM_REQUEST_SOURCE_CAP)) {
-			pe_set_dpm_curr_request(port,
-						DPM_REQUEST_SOURCE_CAP);
+			pe_set_dpm_curr_request(port, DPM_REQUEST_SOURCE_CAP);
 			set_state_pe(port, PE_SNK_GET_SOURCE_CAP);
 			return true;
 		} else if (PE_CHK_DPM_REQUEST(port,
@@ -1775,13 +1781,12 @@ static void print_current_state(const int port)
 {
 	const char *mode = "";
 
-	if (IS_ENABLED(CONFIG_USB_PD_REV30) &&
-			pe_in_frs_mode(port))
+	if (IS_ENABLED(CONFIG_USB_PD_REV30) && pe_in_frs_mode(port))
 		mode = " FRS-MODE";
 
 	if (IS_ENABLED(USB_PD_DEBUG_LABELS))
 		CPRINTS_L1("C%d: %s%s", port,
-			pe_state_names[get_state_pe(port)], mode);
+			   pe_state_names[get_state_pe(port)], mode);
 	else
 		CPRINTS("C%d: pe-st%d", port, get_state_pe(port));
 }
@@ -1817,20 +1822,20 @@ static void pe_send_request_msg(int port)
 	 * might need adjusting.
 	 */
 	if ((get_usb_pd_cable_type(port) == IDH_PTYPE_VPD) &&
-						is_vpd_ct_supported(port)) {
-		union vpd_vdo vpd = pd_get_am_discovery(port,
-				TCPCI_MSG_SOP_PRIME)->identity.product_t1.vpd;
+	    is_vpd_ct_supported(port)) {
+		union vpd_vdo vpd =
+			pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME)
+				->identity.product_t1.vpd;
 
 		/* The raw vpd_vdo is passed to pd_build_request */
 		vpd_vdo = vpd.raw_value;
 	}
 
 	/* Build and send request RDO */
-	pd_build_request(vpd_vdo, &rdo, &curr_limit,
-			&supply_voltage, port);
+	pd_build_request(vpd_vdo, &rdo, &curr_limit, &supply_voltage, port);
 
-	CPRINTF("C%d: Req [%d] %dmV %dmA", port, RDO_POS(rdo),
-					supply_voltage, curr_limit);
+	CPRINTF("C%d: Req [%d] %dmV %dmA", port, RDO_POS(rdo), supply_voltage,
+		curr_limit);
 	if (rdo & RDO_CAP_MISMATCH)
 		CPRINTF(" Mismatch");
 	CPRINTF("\n");
@@ -1931,18 +1936,35 @@ __maybe_unused static bool pe_attempt_port_discovery(int port)
 		return false;
 
 	/* Apply Port Discovery DR Swap Policy */
-	if (port_discovery_dr_swap_policy(port, pe[port].data_role,
-			PE_CHK_FLAG(port, PE_FLAGS_DR_SWAP_TO_DFP))) {
+	if (port_discovery_dr_swap_policy(
+		    port, pe[port].data_role,
+		    PE_CHK_FLAG(port, PE_FLAGS_DR_SWAP_TO_DFP))) {
 		PE_SET_FLAG(port, PE_FLAGS_LOCALLY_INITIATED_AMS);
 		PE_CLR_FLAG(port, PE_FLAGS_DR_SWAP_TO_DFP);
 		set_state_pe(port, PE_DRS_SEND_SWAP);
 		return true;
 	}
 
+	/*
+	 * An edge case of DR Swap fail (port still UFP) and partner in PD 2.0.
+	 * PD 2.0 allows only DFP to initiate Discover Identity, but partner may
+	 * reject a DR Swap.
+	 */
+	if (pe[port].data_role == PD_ROLE_UFP &&
+	    prl_get_rev(port, TCPCI_MSG_SOP) == PD_REV20) {
+		pd_set_identity_discovery(port, TCPCI_MSG_SOP, PD_DISC_FAIL);
+		pd_set_identity_discovery(port, TCPCI_MSG_SOP_PRIME,
+					  PD_DISC_FAIL);
+		pd_notify_event(port, PD_STATUS_EVENT_SOP_DISC_DONE);
+		pd_notify_event(port, PD_STATUS_EVENT_SOP_PRIME_DISC_DONE);
+		PE_SET_FLAG(port, PE_FLAGS_VDM_SETUP_DONE);
+		return false;
+	}
+
 	/* Apply Port Discovery VCONN Swap Policy */
 	if (IS_ENABLED(CONFIG_USBC_VCONN) &&
-			port_discovery_vconn_swap_policy(port,
-			PE_CHK_FLAG(port, PE_FLAGS_VCONN_SWAP_TO_ON))) {
+	    port_discovery_vconn_swap_policy(
+		    port, PE_CHK_FLAG(port, PE_FLAGS_VCONN_SWAP_TO_ON))) {
 		PE_SET_FLAG(port, PE_FLAGS_LOCALLY_INITIATED_AMS);
 		PE_CLR_FLAG(port, PE_FLAGS_VCONN_SWAP_TO_ON);
 		set_state_pe(port, PE_VCS_SEND_SWAP);
@@ -1961,36 +1983,35 @@ __maybe_unused static bool pe_attempt_port_discovery(int port)
 	 */
 	if (pd_timer_is_expired(port, PE_TIMER_DISCOVER_IDENTITY)) {
 		if (pd_get_identity_discovery(port, TCPCI_MSG_SOP_PRIME) ==
-				PD_DISC_NEEDED) {
+		    PD_DISC_NEEDED) {
 			pe[port].tx_type = TCPCI_MSG_SOP_PRIME;
 			set_state_pe(port, PE_VDM_IDENTITY_REQUEST_CBL);
 			return true;
 		} else if (pd_get_identity_discovery(port, TCPCI_MSG_SOP) ==
-				PD_DISC_NEEDED &&
-				pe_can_send_sop_vdm(port, CMD_DISCOVER_IDENT)) {
+				   PD_DISC_NEEDED &&
+			   pe_can_send_sop_vdm(port, CMD_DISCOVER_IDENT)) {
 			pe[port].tx_type = TCPCI_MSG_SOP;
-			set_state_pe(port,
-				     PE_INIT_PORT_VDM_IDENTITY_REQUEST);
+			set_state_pe(port, PE_INIT_PORT_VDM_IDENTITY_REQUEST);
 			return true;
 		} else if (pd_get_svids_discovery(port, TCPCI_MSG_SOP) ==
-				PD_DISC_NEEDED &&
-				pe_can_send_sop_vdm(port, CMD_DISCOVER_SVID)) {
+				   PD_DISC_NEEDED &&
+			   pe_can_send_sop_vdm(port, CMD_DISCOVER_SVID)) {
 			pe[port].tx_type = TCPCI_MSG_SOP;
 			set_state_pe(port, PE_INIT_VDM_SVIDS_REQUEST);
 			return true;
 		} else if (pd_get_modes_discovery(port, TCPCI_MSG_SOP) ==
-				PD_DISC_NEEDED &&
-				pe_can_send_sop_vdm(port, CMD_DISCOVER_MODES)) {
+				   PD_DISC_NEEDED &&
+			   pe_can_send_sop_vdm(port, CMD_DISCOVER_MODES)) {
 			pe[port].tx_type = TCPCI_MSG_SOP;
 			set_state_pe(port, PE_INIT_VDM_MODES_REQUEST);
 			return true;
-		} else if (pd_get_svids_discovery(port, TCPCI_MSG_SOP_PRIME)
-				== PD_DISC_NEEDED) {
+		} else if (pd_get_svids_discovery(port, TCPCI_MSG_SOP_PRIME) ==
+			   PD_DISC_NEEDED) {
 			pe[port].tx_type = TCPCI_MSG_SOP_PRIME;
 			set_state_pe(port, PE_INIT_VDM_SVIDS_REQUEST);
 			return true;
 		} else if (pd_get_modes_discovery(port, TCPCI_MSG_SOP_PRIME) ==
-				PD_DISC_NEEDED) {
+			   PD_DISC_NEEDED) {
 			pe[port].tx_type = TCPCI_MSG_SOP_PRIME;
 			set_state_pe(port, PE_INIT_VDM_MODES_REQUEST);
 			return true;
@@ -2000,8 +2021,8 @@ __maybe_unused static bool pe_attempt_port_discovery(int port)
 	return false;
 }
 
-bool pd_setup_vdm_request(int port, enum tcpci_msg_type tx_type,
-		uint32_t *vdm, uint32_t vdo_cnt)
+bool pd_setup_vdm_request(int port, enum tcpci_msg_type tx_type, uint32_t *vdm,
+			  uint32_t vdo_cnt)
 {
 	if (vdo_cnt < VDO_HDR_SIZE || vdo_cnt > VDO_MAX_SIZE)
 		return false;
@@ -2014,7 +2035,7 @@ bool pd_setup_vdm_request(int port, enum tcpci_msg_type tx_type,
 }
 
 int pd_dev_store_rw_hash(int port, uint16_t dev_id, uint32_t *rw_hash,
-					uint32_t current_image)
+			 uint32_t current_image)
 {
 	pe[port].dev_id = dev_id;
 	memcpy(pe[port].dev_rw_hash, rw_hash, PD_RW_HASH_SIZE);
@@ -2038,7 +2059,7 @@ int pd_dev_store_rw_hash(int port, uint16_t dev_id, uint32_t *rw_hash,
 }
 
 void pd_dev_get_rw_hash(int port, uint16_t *dev_id, uint8_t *rw_hash,
-			 uint32_t *current_image)
+			uint32_t *current_image)
 {
 	*dev_id = pe[port].dev_id;
 	*current_image = pe[port].current_image;
@@ -2079,7 +2100,7 @@ static void pe_update_wait_and_add_jitter_timer(int port)
 	    pd_timer_is_disabled(port, PE_TIMER_WAIT_AND_ADD_JITTER)) {
 		pd_timer_enable(port, PE_TIMER_WAIT_AND_ADD_JITTER,
 				SRC_SNK_READY_HOLD_OFF_US +
-				(get_time().le.lo & 0xf) * 23 * MSEC);
+					(get_time().le.lo & 0xf) * 23 * MSEC);
 	}
 }
 
@@ -2263,8 +2284,7 @@ static void pe_src_startup_entry(int port)
 
 		/* Request partner sink caps if a feature requires them */
 		if (IS_ENABLED(CONFIG_USB_PD_HOST_CMD) ||
-						CONFIG_USB_PD_3A_PORTS > 0 ||
-						IS_ENABLED(CONFIG_USB_PD_FRS))
+		    CONFIG_USB_PD_3A_PORTS > 0 || IS_ENABLED(CONFIG_USB_PD_FRS))
 			pd_dpm_request(port, DPM_REQUEST_GET_SNK_CAPS);
 
 		/*
@@ -2273,7 +2293,6 @@ static void pe_src_startup_entry(int port)
 		 * revision 3.0
 		 */
 		pd_dpm_request(port, DPM_REQUEST_GET_REVISION);
-
 	}
 }
 
@@ -2336,6 +2355,19 @@ static void pe_src_discovery_run(int port)
 			set_state_pe(port, PE_SRC_SEND_CAPABILITIES);
 			return;
 		} else if (!PE_CHK_FLAG(port, PE_FLAGS_PD_CONNECTION)) {
+			/*
+			 * Cable identity may be discovered without a PD
+			 * contract in place. If it has been discovered, notify
+			 * the AP.
+			 */
+			if (pd_get_identity_discovery(port,
+						      TCPCI_MSG_SOP_PRIME) ==
+			    PD_DISC_COMPLETE) {
+				pd_notify_event(
+					port,
+					PD_STATUS_EVENT_SOP_PRIME_DISC_DONE);
+			}
+
 			set_state_pe(port, PE_SRC_DISABLED);
 			return;
 		}
@@ -2347,11 +2379,11 @@ static void pe_src_discovery_run(int port)
 	 * requests properly.
 	 */
 	if (pd_get_identity_discovery(port, TCPCI_MSG_SOP_PRIME) ==
-				PD_DISC_NEEDED
-			&& pd_timer_is_expired(port, PE_TIMER_DISCOVER_IDENTITY)
-			&& pe_can_send_sop_prime(port)
-			&& (pe[port].discover_identity_counter <
-				N_DISCOVER_IDENTITY_PRECONTRACT_LIMIT)) {
+		    PD_DISC_NEEDED &&
+	    pd_timer_is_expired(port, PE_TIMER_DISCOVER_IDENTITY) &&
+	    pe_can_send_sop_prime(port) &&
+	    (pe[port].discover_identity_counter <
+	     N_DISCOVER_IDENTITY_PRECONTRACT_LIMIT)) {
 		pe[port].tx_type = TCPCI_MSG_SOP_PRIME;
 		set_state_pe(port, PE_VDM_IDENTITY_REQUEST_CBL);
 		return;
@@ -2441,15 +2473,14 @@ static void pe_src_send_capabilities_run(int port)
 		 * Request Message Received?
 		 */
 		if (PD_HEADER_CNT(rx_emsg[port].header) > 0 &&
-			PD_HEADER_TYPE(rx_emsg[port].header) ==
-							PD_DATA_REQUEST) {
-
+		    PD_HEADER_TYPE(rx_emsg[port].header) == PD_DATA_REQUEST) {
 			/*
 			 * Set to highest revision supported by both
 			 * ports.
 			 */
 			prl_set_rev(port, TCPCI_MSG_SOP,
-			MIN(PD_REVISION, PD_HEADER_REV(rx_emsg[port].header)));
+				    MIN(PD_REVISION,
+					PD_HEADER_REV(rx_emsg[port].header)));
 
 			init_cable_rev(port);
 
@@ -2620,7 +2651,7 @@ static void pe_src_transition_supply_run(int port)
 			if (!pe_is_explicit_contract(port)) {
 				PE_SET_FLAG(port, PE_FLAGS_FIRST_MSG);
 				pd_timer_disable(port,
-						PE_TIMER_WAIT_AND_ADD_JITTER);
+						 PE_TIMER_WAIT_AND_ADD_JITTER);
 			}
 
 			/* NOTE: Second pass through this code block */
@@ -2680,13 +2711,13 @@ static void extended_message_not_supported(int port, uint32_t *payload)
 	uint16_t ext_header = GET_EXT_HEADER(*payload);
 
 	if (IS_ENABLED(CONFIG_USB_PD_REV30) &&
-			!IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES) &&
-			PD_EXT_HEADER_CHUNKED(ext_header) &&
-			PD_EXT_HEADER_DATA_SIZE(ext_header) >
-			PD_MAX_EXTENDED_MSG_CHUNK_LEN) {
-		set_state_pe(port,
-				pe[port].power_role == PD_ROLE_SOURCE ?
-				PE_SRC_CHUNK_RECEIVED : PE_SNK_CHUNK_RECEIVED);
+	    !IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES) &&
+	    PD_EXT_HEADER_CHUNKED(ext_header) &&
+	    PD_EXT_HEADER_DATA_SIZE(ext_header) >
+		    PD_MAX_EXTENDED_MSG_CHUNK_LEN) {
+		set_state_pe(port, pe[port].power_role == PD_ROLE_SOURCE ?
+					   PE_SRC_CHUNK_RECEIVED :
+					   PE_SNK_CHUNK_RECEIVED);
 		return;
 	}
 
@@ -2753,18 +2784,24 @@ static void pe_src_ready_run(int port)
 				break;
 			case PD_DATA_VENDOR_DEF:
 				if (PD_HEADER_TYPE(rx_emsg[port].header) ==
-							PD_DATA_VENDOR_DEF) {
+				    PD_DATA_VENDOR_DEF) {
 					if (PD_VDO_SVDM(*payload)) {
 						set_state_pe(port,
-							PE_VDM_RESPONSE);
+							     PE_VDM_RESPONSE);
 					} else
-						set_state_pe(port,
-						PE_HANDLE_CUSTOM_VDM_REQUEST);
+						set_state_pe(
+							port,
+							PE_HANDLE_CUSTOM_VDM_REQUEST);
 				}
 				return;
 			case PD_DATA_BIST:
 				set_state_pe(port, PE_BIST_TX);
 				return;
+#ifdef CONFIG_USB_PD_REV30
+			case PD_DATA_ALERT:
+				set_state_pe(port, PE_ALERT_RECEIVED);
+				return;
+#endif /* CONFIG_USB_PD_REV30 */
 			default:
 				set_state_pe(port, PE_SEND_NOT_SUPPORTED);
 				return;
@@ -2789,7 +2826,7 @@ static void pe_src_ready_run(int port)
 				break;
 			case PD_CTRL_PR_SWAP:
 				set_state_pe(port,
-					PE_PRS_SRC_SNK_EVALUATE_SWAP);
+					     PE_PRS_SRC_SNK_EVALUATE_SWAP);
 				return;
 			case PD_CTRL_DR_SWAP:
 				if (PE_CHK_FLAG(port,
@@ -2803,10 +2840,10 @@ static void pe_src_ready_run(int port)
 			case PD_CTRL_VCONN_SWAP:
 				if (IS_ENABLED(CONFIG_USBC_VCONN))
 					set_state_pe(port,
-							PE_VCS_EVALUATE_SWAP);
+						     PE_VCS_EVALUATE_SWAP);
 				else
 					set_state_pe(port,
-							PE_SEND_NOT_SUPPORTED);
+						     PE_SEND_NOT_SUPPORTED);
 				return;
 			/*
 			 * USB PD 3.0 6.8.1:
@@ -2817,16 +2854,19 @@ static void pe_src_ready_run(int port)
 			case PD_CTRL_REJECT:
 			case PD_CTRL_WAIT:
 			case PD_CTRL_PS_RDY:
-				pe_send_soft_reset(port,
-				  PD_HEADER_GET_SOP(rx_emsg[port].header));
+				pe_send_soft_reset(
+					port, PD_HEADER_GET_SOP(
+						      rx_emsg[port].header));
 				return;
 #ifdef CONFIG_USB_PD_DATA_RESET_MSG
 			case PD_CTRL_DATA_RESET:
 				if (pe[port].data_role == PD_ROLE_DFP)
-					set_state_pe(port,
+					set_state_pe(
+						port,
 						PE_DDR_DATA_RESET_RECEIVED);
 				else
-					set_state_pe(port,
+					set_state_pe(
+						port,
 						PE_UDR_DATA_RESET_RECEIVED);
 				return;
 #endif /* CONFIG_USB_PD_DATA_RESET_MSG */
@@ -2835,10 +2875,11 @@ static void pe_src_ready_run(int port)
 				set_state_pe(port, PE_GIVE_STATUS);
 				return;
 #endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
-			/*
-			 * Receiving an unknown or unsupported message
-			 * shall be responded to with a not supported message.
-			 */
+				/*
+				 * Receiving an unknown or unsupported message
+				 * shall be responded to with a not supported
+				 * message.
+				 */
 
 			default:
 				set_state_pe(port, PE_SEND_NOT_SUPPORTED);
@@ -2868,7 +2909,6 @@ static void pe_src_ready_run(int port)
 
 	if (pd_timer_is_disabled(port, PE_TIMER_WAIT_AND_ADD_JITTER) ||
 	    pd_timer_is_expired(port, PE_TIMER_WAIT_AND_ADD_JITTER)) {
-
 		PE_CLR_FLAG(port, PE_FLAGS_FIRST_MSG);
 		pd_timer_disable(port, PE_TIMER_WAIT_AND_ADD_JITTER);
 
@@ -2898,7 +2938,7 @@ static void pe_src_disabled_entry(int port)
 	print_current_state(port);
 
 	if ((get_usb_pd_cable_type(port) == IDH_PTYPE_VPD) &&
-						is_vpd_ct_supported(port)) {
+	    is_vpd_ct_supported(port)) {
 		/*
 		 * Inform the Device Policy Manager that a Charge-Through VCONN
 		 * Powered Device was detected.
@@ -2988,10 +3028,9 @@ static void pe_src_hard_reset_entry(int port)
 	pd_timer_enable(port, PE_TIMER_PS_HARD_RESET, PD_T_PS_HARD_RESET);
 
 	/* Clear error flags */
-	PE_CLR_MASK(port,
-		    BIT(PE_FLAGS_VDM_REQUEST_NAKED_FN) |
-		    BIT(PE_FLAGS_PROTOCOL_ERROR_FN) |
-		    BIT(PE_FLAGS_VDM_REQUEST_BUSY_FN));
+	PE_CLR_MASK(port, BIT(PE_FLAGS_VDM_REQUEST_NAKED_FN) |
+				  BIT(PE_FLAGS_PROTOCOL_ERROR_FN) |
+				  BIT(PE_FLAGS_VDM_REQUEST_BUSY_FN));
 }
 
 static void pe_src_hard_reset_run(int port)
@@ -3158,9 +3197,8 @@ static void pe_snk_startup_entry(int port)
 	 * Swap, then the Policy Engine Shall do the following:
 	 * - Send a Get_Sink_Cap Message
 	 */
-	if (IS_ENABLED(CONFIG_USB_PD_HOST_CMD) ||
-					CONFIG_USB_PD_3A_PORTS > 0 ||
-					IS_ENABLED(CONFIG_USB_PD_FRS))
+	if (IS_ENABLED(CONFIG_USB_PD_HOST_CMD) || CONFIG_USB_PD_3A_PORTS > 0 ||
+	    IS_ENABLED(CONFIG_USB_PD_FRS))
 		pd_dpm_request(port, DPM_REQUEST_GET_SNK_CAPS);
 
 	/*
@@ -3169,7 +3207,6 @@ static void pe_snk_startup_entry(int port)
 	 * revision 3.0
 	 */
 	pd_dpm_request(port, DPM_REQUEST_GET_REVISION);
-
 }
 
 static void pe_snk_startup_run(int port)
@@ -3264,7 +3301,7 @@ static void pe_snk_evaluate_capability_entry(int port)
 
 	/* Set to highest revision supported by both ports. */
 	prl_set_rev(port, TCPCI_MSG_SOP,
-			MIN(PD_REVISION, PD_HEADER_REV(rx_emsg[port].header)));
+		    MIN(PD_REVISION, PD_HEADER_REV(rx_emsg[port].header)));
 
 	init_cable_rev(port);
 
@@ -3385,7 +3422,7 @@ static void pe_snk_select_capability_run(int port)
 			 * Reject or Wait Message Received
 			 */
 			else if (type == PD_CTRL_REJECT ||
-							type == PD_CTRL_WAIT) {
+				 type == PD_CTRL_WAIT) {
 				if (type == PD_CTRL_WAIT)
 					PE_SET_FLAG(port, PE_FLAGS_WAIT);
 
@@ -3403,7 +3440,8 @@ static void pe_snk_select_capability_run(int port)
 				 * to PE_SNK_Wait_For_Capabilities
 				 */
 				else
-					set_state_pe(port,
+					set_state_pe(
+						port,
 						PE_SNK_WAIT_FOR_CAPABILITIES);
 				return;
 			}
@@ -3464,8 +3502,7 @@ static void pe_snk_transition_sink_run(int port)
 		 * PS_RDY message received
 		 */
 		if ((PD_HEADER_CNT(rx_emsg[port].header) == 0) &&
-			   (PD_HEADER_TYPE(rx_emsg[port].header) ==
-			   PD_CTRL_PS_RDY)) {
+		    (PD_HEADER_TYPE(rx_emsg[port].header) == PD_CTRL_PS_RDY)) {
 			/*
 			 * Set first message flag to trigger a wait and add
 			 * jitter delay when operating in PD2.0 mode.
@@ -3488,8 +3525,8 @@ static void pe_snk_transition_sink_run(int port)
 			 * already available
 			 */
 			if (pd_get_snk_cap_cnt(port) > 0)
-				dpm_evaluate_sink_fixed_pdo(port,
-							*pd_get_snk_caps(port));
+				dpm_evaluate_sink_fixed_pdo(
+					port, *pd_get_snk_caps(port));
 
 			set_state_pe(port, PE_SNK_READY);
 		} else {
@@ -3515,13 +3552,13 @@ static void pe_snk_transition_sink_run(int port)
 static void pe_snk_transition_sink_exit(int port)
 {
 	/* Transition Sink's power supply to the new power level */
-	pd_set_input_current_limit(port,
-				pe[port].curr_limit, pe[port].supply_voltage);
+	pd_set_input_current_limit(port, pe[port].curr_limit,
+				   pe[port].supply_voltage);
 
 	if (IS_ENABLED(CONFIG_CHARGE_MANAGER))
 		/* Set ceiling based on what's negotiated */
-		charge_manager_set_ceil(port,
-				CEIL_REQUESTOR_PD, pe[port].curr_limit);
+		charge_manager_set_ceil(port, CEIL_REQUESTOR_PD,
+					pe[port].curr_limit);
 
 	pd_timer_disable(port, PE_TIMER_PS_TRANSITION);
 
@@ -3530,7 +3567,6 @@ static void pe_snk_transition_sink_exit(int port)
 			dps_update_stabilized_time(port);
 }
 
-
 /**
  * PE_SNK_Ready State
  */
@@ -3551,8 +3587,7 @@ static void pe_snk_ready_entry(int port)
 	 */
 	if (PE_CHK_FLAG(port, PE_FLAGS_WAIT)) {
 		PE_CLR_FLAG(port, PE_FLAGS_WAIT);
-		pd_timer_enable(port, PE_TIMER_SINK_REQUEST,
-				PD_T_SINK_REQUEST);
+		pd_timer_enable(port, PE_TIMER_SINK_REQUEST, PD_T_SINK_REQUEST);
 	}
 
 	/*
@@ -3596,23 +3631,28 @@ static void pe_snk_ready_run(int port)
 		else if (cnt > 0) {
 			switch (type) {
 			case PD_DATA_SOURCE_CAP:
-				set_state_pe(port,
-					PE_SNK_EVALUATE_CAPABILITY);
+				set_state_pe(port, PE_SNK_EVALUATE_CAPABILITY);
 				break;
 			case PD_DATA_VENDOR_DEF:
 				if (PD_HEADER_TYPE(rx_emsg[port].header) ==
-							PD_DATA_VENDOR_DEF) {
+				    PD_DATA_VENDOR_DEF) {
 					if (PD_VDO_SVDM(*payload))
 						set_state_pe(port,
-							PE_VDM_RESPONSE);
+							     PE_VDM_RESPONSE);
 					else
-						set_state_pe(port,
-						PE_HANDLE_CUSTOM_VDM_REQUEST);
+						set_state_pe(
+							port,
+							PE_HANDLE_CUSTOM_VDM_REQUEST);
 				}
 				break;
 			case PD_DATA_BIST:
 				set_state_pe(port, PE_BIST_TX);
 				break;
+#ifdef CONFIG_USB_PD_REV30
+			case PD_DATA_ALERT:
+				set_state_pe(port, PE_ALERT_RECEIVED);
+				return;
+#endif /* CONFIG_USB_PD_REV30 */
 			default:
 				set_state_pe(port, PE_SEND_NOT_SUPPORTED);
 			}
@@ -3638,30 +3678,32 @@ static void pe_snk_ready_run(int port)
 				return;
 			case PD_CTRL_PR_SWAP:
 				set_state_pe(port,
-						PE_PRS_SNK_SRC_EVALUATE_SWAP);
+					     PE_PRS_SNK_SRC_EVALUATE_SWAP);
 				return;
 			case PD_CTRL_DR_SWAP:
 				if (PE_CHK_FLAG(port, PE_FLAGS_MODAL_OPERATION))
 					pe_set_hard_reset(port);
 				else
 					set_state_pe(port,
-							PE_DRS_EVALUATE_SWAP);
+						     PE_DRS_EVALUATE_SWAP);
 				return;
 			case PD_CTRL_VCONN_SWAP:
 				if (IS_ENABLED(CONFIG_USBC_VCONN))
 					set_state_pe(port,
-							PE_VCS_EVALUATE_SWAP);
+						     PE_VCS_EVALUATE_SWAP);
 				else
 					set_state_pe(port,
-							PE_SEND_NOT_SUPPORTED);
+						     PE_SEND_NOT_SUPPORTED);
 				return;
 #ifdef CONFIG_USB_PD_DATA_RESET_MSG
 			case PD_CTRL_DATA_RESET:
 				if (pe[port].data_role == PD_ROLE_DFP)
-					set_state_pe(port,
+					set_state_pe(
+						port,
 						PE_DDR_DATA_RESET_RECEIVED);
 				else
-					set_state_pe(port,
+					set_state_pe(
+						port,
 						PE_UDR_DATA_RESET_RECEIVED);
 				return;
 #endif /* CONFIG_USB_PD_DATA_RESET_MSG */
@@ -3682,8 +3724,9 @@ static void pe_snk_ready_run(int port)
 			case PD_CTRL_REJECT:
 			case PD_CTRL_WAIT:
 			case PD_CTRL_PS_RDY:
-				pe_send_soft_reset(port,
-				  PD_HEADER_GET_SOP(rx_emsg[port].header));
+				pe_send_soft_reset(
+					port, PD_HEADER_GET_SOP(
+						      rx_emsg[port].header));
 				return;
 			/*
 			 * Receiving an unknown or unsupported message
@@ -3735,7 +3778,6 @@ static void pe_snk_ready_run(int port)
 
 		/* No DPM requests; attempt mode entry/exit if needed */
 		dpm_run(port);
-
 	}
 }
 
@@ -3756,7 +3798,7 @@ static void pe_snk_hard_reset_entry(int port)
 	 *       Source is non-responsive.
 	 */
 	if (PE_CHK_FLAG(port, PE_FLAGS_SNK_WAIT_CAP_TIMEOUT) &&
-			pe[port].hard_reset_counter > N_HARD_RESET_COUNT) {
+	    pe[port].hard_reset_counter > N_HARD_RESET_COUNT) {
 		set_state_pe(port, PE_SRC_DISABLED);
 		return;
 	}
@@ -3776,13 +3818,13 @@ static void pe_snk_hard_reset_entry(int port)
 	if (IS_ENABLED(CONFIG_BATTERY) && (battery_is_present() == BP_NO) &&
 	    IS_ENABLED(CONFIG_CHARGE_MANAGER) &&
 	    ((port == charge_manager_get_active_charge_port() ||
-	     (charge_manager_get_active_charge_port() == CHARGE_PORT_NONE))) &&
+	      (charge_manager_get_active_charge_port() == CHARGE_PORT_NONE))) &&
 	    system_get_reset_flags() & EC_RESET_FLAG_SYSJUMP) {
 		CPRINTS("C%d: Disabling port to avoid brown out, "
-			"please reboot EC to enable port again", port);
+			"please reboot EC to enable port again",
+			port);
 		set_state_pe(port, PE_SRC_DISABLED);
 		return;
-
 	}
 
 #ifdef CONFIG_USB_PD_RESET_MIN_BATT_SOC
@@ -3803,19 +3845,18 @@ static void pe_snk_hard_reset_entry(int port)
 	if (batt_soc < CONFIG_USB_PD_RESET_MIN_BATT_SOC ||
 	    battery_get_disconnect_state() != BATTERY_NOT_DISCONNECTED) {
 		PE_SET_FLAG(port, PE_FLAGS_SNK_WAITING_BATT);
-		CPRINTS("C%d: Battery low %d%%! Stay in disabled state " \
-			"until battery level reaches %d%%", port, batt_soc,
-			CONFIG_USB_PD_RESET_MIN_BATT_SOC);
+		CPRINTS("C%d: Battery low %d%%! Stay in disabled state "
+			"until battery level reaches %d%%",
+			port, batt_soc, CONFIG_USB_PD_RESET_MIN_BATT_SOC);
 		set_state_pe(port, PE_SRC_DISABLED);
 		return;
 	}
 #endif
 
-	PE_CLR_MASK(port,
-		    BIT(PE_FLAGS_SNK_WAIT_CAP_TIMEOUT_FN) |
-		    BIT(PE_FLAGS_VDM_REQUEST_NAKED_FN) |
-		    BIT(PE_FLAGS_PROTOCOL_ERROR_FN) |
-		    BIT(PE_FLAGS_VDM_REQUEST_BUSY_FN));
+	PE_CLR_MASK(port, BIT(PE_FLAGS_SNK_WAIT_CAP_TIMEOUT_FN) |
+				  BIT(PE_FLAGS_VDM_REQUEST_NAKED_FN) |
+				  BIT(PE_FLAGS_PROTOCOL_ERROR_FN) |
+				  BIT(PE_FLAGS_VDM_REQUEST_BUSY_FN));
 
 	/* Request the generation of Hard Reset Signaling by the PHY Layer */
 	prl_execute_hard_reset(port);
@@ -3832,11 +3873,11 @@ static void pe_snk_hard_reset_entry(int port)
 
 		/* Transition Sink's power supply to the new power level */
 		pd_set_input_current_limit(port, pe[port].curr_limit,
-						pe[port].supply_voltage);
+					   pe[port].supply_voltage);
 		if (IS_ENABLED(CONFIG_CHARGE_MANAGER))
 			/* Set ceiling based on what's negotiated */
 			charge_manager_set_ceil(port, CEIL_REQUESTOR_PD,
-							pe[port].curr_limit);
+						pe[port].curr_limit);
 	}
 }
 
@@ -3943,8 +3984,8 @@ static void pe_send_soft_reset_run(int port)
 		 * unexpected incoming message type
 		 */
 		/* Send Soft Reset message */
-		send_ctrl_msg(port,
-			pe[port].soft_reset_sop, PD_CTRL_SOFT_RESET);
+		send_ctrl_msg(port, pe[port].soft_reset_sop,
+			      PD_CTRL_SOFT_RESET);
 
 		return;
 	}
@@ -3978,10 +4019,9 @@ static void pe_send_soft_reset_run(int port)
 		if ((ext == 0) && (cnt == 0) && (type == PD_CTRL_ACCEPT)) {
 			if (pe[port].power_role == PD_ROLE_SINK)
 				set_state_pe(port,
-						PE_SNK_WAIT_FOR_CAPABILITIES);
+					     PE_SNK_WAIT_FOR_CAPABILITIES);
 			else
-				set_state_pe(port,
-						PE_SRC_SEND_CAPABILITIES);
+				set_state_pe(port, PE_SRC_SEND_CAPABILITIES);
 			return;
 		}
 	}
@@ -3991,7 +4031,7 @@ static void pe_send_soft_reset_run(int port)
 	 * Response Timer Timeout or Protocol Layer or Protocol Error
 	 */
 	if (pd_timer_is_expired(port, PE_TIMER_SENDER_RESPONSE) ||
-			PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) {
+	    PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) {
 		PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
 		pe_set_hard_reset(port);
 		return;
@@ -4014,7 +4054,7 @@ static void pe_soft_reset_entry(int port)
 	send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_ACCEPT);
 }
 
-static void  pe_soft_reset_run(int port)
+static void pe_soft_reset_run(int port)
 {
 	if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
 		PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
@@ -4054,7 +4094,6 @@ static void pe_send_not_supported_run(int port)
 	if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
 		PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
 		pe_set_ready_state(port);
-
 	}
 }
 
@@ -4176,32 +4215,28 @@ static void pe_give_battery_cap_entry(int port)
 		 */
 		msg[BCDB_FULL_CAP] = 0xffff;
 
-
 		if (IS_ENABLED(HAS_TASK_HOSTCMD) &&
 		    *host_get_memmap(EC_MEMMAP_BATTERY_VERSION) != 0) {
 			int design_volt, design_cap, full_cap;
 
-			design_volt = *(int *)host_get_memmap(
-						EC_MEMMAP_BATT_DVLT);
-			design_cap = *(int *)host_get_memmap(
-						EC_MEMMAP_BATT_DCAP);
-			full_cap = *(int *)host_get_memmap(
-						EC_MEMMAP_BATT_LFCC);
+			design_volt =
+				*(int *)host_get_memmap(EC_MEMMAP_BATT_DVLT);
+			design_cap =
+				*(int *)host_get_memmap(EC_MEMMAP_BATT_DCAP);
+			full_cap = *(int *)host_get_memmap(EC_MEMMAP_BATT_LFCC);
 
 			/*
 			 * Wh = (c * v) / 1000000
 			 * 10th of a Wh = Wh * 10
 			 */
 			msg[BCDB_DESIGN_CAP] = DIV_ROUND_NEAREST(
-					(design_cap * design_volt),
-					 100000);
+				(design_cap * design_volt), 100000);
 			/*
 			 * Wh = (c * v) / 1000000
 			 * 10th of a Wh = Wh * 10
 			 */
 			msg[BCDB_FULL_CAP] = DIV_ROUND_NEAREST(
-					(design_cap * full_cap),
-					 100000);
+				(design_cap * full_cap), 100000);
 		} else {
 			uint32_t v;
 			uint32_t c;
@@ -4213,24 +4248,19 @@ static void pe_give_battery_cap_entry(int port)
 					 * 10th of a Wh = Wh * 10
 					 */
 					msg[BCDB_DESIGN_CAP] =
-						DIV_ROUND_NEAREST(
-						(c * v),
-						 100000);
+						DIV_ROUND_NEAREST((c * v),
+								  100000);
 				}
 
-				if (battery_full_charge_capacity(&c)
-								== 0) {
+				if (battery_full_charge_capacity(&c) == 0) {
 					/*
 					 * Wh = (c * v) / 1000000
 					 * 10th of a Wh = Wh * 10
 					 */
-					msg[BCDB_FULL_CAP] =
-						DIV_ROUND_NEAREST(
-						(c * v),
-						 100000);
+					msg[BCDB_FULL_CAP] = DIV_ROUND_NEAREST(
+						(c * v), 100000);
 				}
 			}
-
 		}
 		/* Valid battery selected */
 		msg[BCDB_BATT_TYPE] = 0;
@@ -4286,24 +4316,23 @@ static void pe_give_battery_status_entry(int port)
 			if (IS_ENABLED(HAS_TASK_HOSTCMD) &&
 			    *host_get_memmap(EC_MEMMAP_BATTERY_VERSION) != 0) {
 				v = *(int *)host_get_memmap(
-							EC_MEMMAP_BATT_DVLT);
-				c = *(int *)host_get_memmap(
-							EC_MEMMAP_BATT_CAP);
+					EC_MEMMAP_BATT_DVLT);
+				c = *(int *)host_get_memmap(EC_MEMMAP_BATT_CAP);
 
 				/*
 				 * Wh = (c * v) / 1000000
 				 * 10th of a Wh = Wh * 10
 				 */
-				*msg = BSDO_CAP(DIV_ROUND_NEAREST((c * v),
-						 100000));
+				*msg = BSDO_CAP(
+					DIV_ROUND_NEAREST((c * v), 100000));
 			} else if (battery_design_voltage(&v) == 0 &&
 				   battery_remaining_capacity(&c) == 0) {
 				/*
 				 * Wh = (c * v) / 1000000
 				 * 10th of a Wh = Wh * 10
 				 */
-				*msg = BSDO_CAP(DIV_ROUND_NEAREST((c * v),
-								  100000));
+				*msg = BSDO_CAP(
+					DIV_ROUND_NEAREST((c * v), 100000));
 			}
 
 			/* Battery is present */
@@ -4377,7 +4406,6 @@ static void pe_give_status_run(int port)
 	}
 }
 
-
 /**
  * PE_SRC_Send_Source_Alert and
  * PE_SNK_Send_Sink_Alert
@@ -4411,6 +4439,20 @@ static void pe_send_alert_run(int port)
 		pe_set_ready_state(port);
 	}
 }
+
+/**
+ * PE_SNK_Source_Alert_Received and
+ * PE_SRC_Sink_Alert_Received
+ */
+static void pe_alert_received_entry(int port)
+{
+	uint32_t *ado = (uint32_t *)rx_emsg[port].buf;
+
+	print_current_state(port);
+	dpm_handle_alert(port, *ado);
+	pe_set_ready_state(port);
+}
+
 #endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
 
 /**
@@ -4539,8 +4581,8 @@ static void pe_drs_send_swap_run(int port)
 				set_state_pe(port, PE_DRS_CHANGE);
 				return;
 			} else if ((type == PD_CTRL_REJECT) ||
-					(type == PD_CTRL_WAIT) ||
-					(type == PD_CTRL_NOT_SUPPORTED)) {
+				   (type == PD_CTRL_WAIT) ||
+				   (type == PD_CTRL_NOT_SUPPORTED)) {
 				pe_set_ready_state(port);
 				return;
 			}
@@ -4742,8 +4784,7 @@ static void pe_prs_src_snk_wait_source_on_run(int port)
 static void pe_prs_src_snk_wait_source_on_exit(int port)
 {
 	pd_timer_disable(port, PE_TIMER_PS_SOURCE);
-	tc_pr_swap_complete(port,
-			    PE_CHK_FLAG(port, PE_FLAGS_PR_SWAP_COMPLETE));
+	tc_pr_swap_complete(port, PE_CHK_FLAG(port, PE_FLAGS_PR_SWAP_COMPLETE));
 }
 
 /**
@@ -4794,7 +4835,7 @@ static void pe_prs_src_snk_send_swap_run(int port)
 				pe[port].src_snk_pr_swap_counter = 0;
 				tc_request_power_swap(port);
 				set_state_pe(port,
-					PE_PRS_SRC_SNK_TRANSITION_TO_OFF);
+					     PE_PRS_SRC_SNK_TRANSITION_TO_OFF);
 			} else if (type == PD_CTRL_REJECT) {
 				pe[port].src_snk_pr_swap_counter = 0;
 				set_state_pe(port, PE_SRC_READY);
@@ -4802,7 +4843,7 @@ static void pe_prs_src_snk_send_swap_run(int port)
 				if (pe[port].src_snk_pr_swap_counter <
 				    N_SNK_SRC_PR_SWAP_COUNT) {
 					PE_SET_FLAG(port,
-						PE_FLAGS_WAITING_PR_SWAP);
+						    PE_FLAGS_WAITING_PR_SWAP);
 					pd_timer_enable(port,
 							PE_TIMER_PR_SWAP_WAIT,
 							PD_T_PR_SWAP_WAIT);
@@ -4902,8 +4943,7 @@ static void pe_prs_snk_src_transition_to_off_entry(int port)
 {
 	print_current_state(port);
 
-	if (!IS_ENABLED(CONFIG_USB_PD_REV30) ||
-			!pe_in_frs_mode(port))
+	if (!IS_ENABLED(CONFIG_USB_PD_REV30) || !pe_in_frs_mode(port))
 		tc_snk_power_off(port);
 
 	pd_timer_enable(port, PE_TIMER_PS_SOURCE, PD_T_PS_SOURCE_OFF);
@@ -4970,8 +5010,7 @@ static void pe_prs_snk_src_assert_rp_run(int port)
 {
 	/* Wait until TypeC is in the Attached.SRC state */
 	if (tc_is_attached_src(port)) {
-		if (!IS_ENABLED(CONFIG_USB_PD_REV30) ||
-			!pe_in_frs_mode(port)) {
+		if (!IS_ENABLED(CONFIG_USB_PD_REV30) || !pe_in_frs_mode(port)) {
 			/* Contract is invalid now */
 			pe_invalidate_explicit_contract(port);
 		}
@@ -5032,8 +5071,7 @@ static void pe_prs_snk_src_source_on_run(int port)
 static void pe_prs_snk_src_source_on_exit(int port)
 {
 	pd_timer_disable(port, PE_TIMER_PS_SOURCE);
-	tc_pr_swap_complete(port,
-			    PE_CHK_FLAG(port, PE_FLAGS_PR_SWAP_COMPLETE));
+	tc_pr_swap_complete(port, PE_CHK_FLAG(port, PE_FLAGS_PR_SWAP_COMPLETE));
 }
 
 /**
@@ -5056,11 +5094,9 @@ static void pe_prs_snk_src_send_swap_entry(int port)
 	 *     Request the Protocol Layer to send a FR_Swap Message.
 	 */
 	if (IS_ENABLED(CONFIG_USB_PD_REV30)) {
-		send_ctrl_msg(port,
-			TCPCI_MSG_SOP,
-			pe_in_frs_mode(port)
-				? PD_CTRL_FR_SWAP
-				: PD_CTRL_PR_SWAP);
+		send_ctrl_msg(port, TCPCI_MSG_SOP,
+			      pe_in_frs_mode(port) ? PD_CTRL_FR_SWAP :
+						     PD_CTRL_PR_SWAP);
 	} else {
 		send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_PR_SWAP);
 	}
@@ -5113,12 +5149,13 @@ static void pe_prs_snk_src_send_swap_run(int port)
 				set_state_pe(port,
 					     PE_PRS_SNK_SRC_TRANSITION_TO_OFF);
 			} else if ((type == PD_CTRL_REJECT) ||
-						(type == PD_CTRL_WAIT)) {
+				   (type == PD_CTRL_WAIT)) {
 				if (IS_ENABLED(CONFIG_USB_PD_REV30))
-					set_state_pe(port,
-						pe_in_frs_mode(port)
-					   ? PE_WAIT_FOR_ERROR_RECOVERY
-					   : PE_SNK_READY);
+					set_state_pe(
+						port,
+						pe_in_frs_mode(port) ?
+							PE_WAIT_FOR_ERROR_RECOVERY :
+							PE_SNK_READY);
 				else
 					set_state_pe(port, PE_SNK_READY);
 			}
@@ -5133,10 +5170,9 @@ static void pe_prs_snk_src_send_swap_run(int port)
 	 */
 	if (pd_timer_is_expired(port, PE_TIMER_SENDER_RESPONSE)) {
 		if (IS_ENABLED(CONFIG_USB_PD_REV30))
-			set_state_pe(port,
-				pe_in_frs_mode(port)
-				? PE_WAIT_FOR_ERROR_RECOVERY
-				: PE_SNK_READY);
+			set_state_pe(port, pe_in_frs_mode(port) ?
+						   PE_WAIT_FOR_ERROR_RECOVERY :
+						   PE_SNK_READY);
 		else
 			set_state_pe(port, PE_SNK_READY);
 		return;
@@ -5147,9 +5183,8 @@ static void pe_prs_snk_src_send_swap_run(int port)
 	 *      has not been received). A soft reset Shall Not be initiated in
 	 *      this case.
 	 */
-	if (IS_ENABLED(CONFIG_USB_PD_REV30) &&
-	    pe_in_frs_mode(port) &&
-		PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) {
+	if (IS_ENABLED(CONFIG_USB_PD_REV30) && pe_in_frs_mode(port) &&
+	    PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) {
 		PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
 		set_state_pe(port, PE_WAIT_FOR_ERROR_RECOVERY);
 	}
@@ -5269,6 +5304,18 @@ static void pe_bist_tx_entry(int port)
 		 */
 		if (tcpc_set_bist_test_mode(port, true) != EC_SUCCESS)
 			CPRINTS("C%d: Failed to enter BIST Test Mode", port);
+	} else if (IS_ENABLED(CONFIG_USB_PD_REV30) &&
+		   mode == BIST_SHARED_MODE_ENTER) {
+		/* Notify the DPM and return to ready */
+		dpm_bist_shared_mode_enter(port);
+		pe_set_ready_state(port);
+		return;
+	} else if (IS_ENABLED(CONFIG_USB_PD_REV30) &&
+		   mode == BIST_SHARED_MODE_EXIT) {
+		/* Notify the DPM and return to ready */
+		dpm_bist_shared_mode_exit(port);
+		pe_set_ready_state(port);
+		return;
 	} else {
 		/* Ignore unsupported BIST messages. */
 		pe_set_ready_state(port);
@@ -5415,10 +5462,10 @@ static enum vdm_response_result parse_vdm_response_common(int port)
 	cnt = PD_HEADER_CNT(rx_emsg[port].header);
 	ext = PD_HEADER_EXT(rx_emsg[port].header);
 
-	if (sop == pe[port].tx_type && type == PD_DATA_VENDOR_DEF && cnt >= 1
-			&& ext == 0) {
+	if (sop == pe[port].tx_type && type == PD_DATA_VENDOR_DEF && cnt >= 1 &&
+	    ext == 0) {
 		if (PD_VDO_CMDT(payload[0]) == CMDT_RSP_ACK &&
-				cnt >= pe[port].vdm_ack_min_data_objects) {
+		    cnt >= pe[port].vdm_ack_min_data_objects) {
 			/* Handle ACKs in state-specific code. */
 			return VDM_RESULT_ACK;
 		} else if (PD_VDO_CMDT(payload[0]) == CMDT_RSP_NAK) {
@@ -5430,7 +5477,7 @@ static enum vdm_response_result parse_vdm_response_common(int port)
 			 * tVDMBusy
 			 */
 			CPRINTS("C%d: Partner BUSY, request will be retried",
-					port);
+				port);
 			pd_timer_enable(port, PE_TIMER_DISCOVER_IDENTITY,
 					PD_T_VDM_BUSY);
 
@@ -5448,11 +5495,11 @@ static enum vdm_response_result parse_vdm_response_common(int port)
 		 * Partner gave us an incorrect size or command; mark discovery
 		 * as failed.
 		 */
-		CPRINTS("C%d: Unexpected VDM response: 0x%04x 0x%04x",
-				port, rx_emsg[port].header, payload[0]);
+		CPRINTS("C%d: Unexpected VDM response: 0x%04x 0x%04x", port,
+			rx_emsg[port].header, payload[0]);
 		return VDM_RESULT_NAK;
 	} else if (sop == pe[port].tx_type && ext == 0 && cnt == 0 &&
-			type == PD_CTRL_NOT_SUPPORTED) {
+		   type == PD_CTRL_NOT_SUPPORTED) {
 		/*
 		 * A NAK would be more expected here, but Not Supported is still
 		 * allowed with the same meaning.
@@ -5483,16 +5530,16 @@ static void pe_vdm_send_request_entry(int port)
 
 	if ((pe[port].tx_type == TCPCI_MSG_SOP_PRIME ||
 	     pe[port].tx_type == TCPCI_MSG_SOP_PRIME_PRIME) &&
-	    !tc_is_vconn_src(port) && port_discovery_vconn_swap_policy(port,
-					BIT(PE_FLAGS_VCONN_SWAP_TO_ON_FN))) {
+	    !tc_is_vconn_src(port) &&
+	    port_discovery_vconn_swap_policy(
+		    port, BIT(PE_FLAGS_VCONN_SWAP_TO_ON_FN))) {
 		if (port_try_vconn_swap(port))
 			return;
 	}
 
 	/* All VDM sequences are Interruptible */
-	PE_SET_MASK(port,
-		    BIT(PE_FLAGS_LOCALLY_INITIATED_AMS_FN) |
-		    BIT(PE_FLAGS_INTERRUPTIBLE_AMS_FN));
+	PE_SET_MASK(port, BIT(PE_FLAGS_LOCALLY_INITIATED_AMS_FN) |
+				  BIT(PE_FLAGS_INTERRUPTIBLE_AMS_FN));
 }
 
 static void pe_vdm_send_request_run(int port)
@@ -5504,8 +5551,7 @@ static void pe_vdm_send_request_run(int port)
 
 		/* Start no response timer */
 		/* TODO(b/155890173): Support DPM-supplied timeout */
-		pd_timer_enable(port, PE_TIMER_VDM_RESPONSE,
-				PD_T_VDM_SNDR_RSP);
+		pd_timer_enable(port, PE_TIMER_VDM_RESPONSE, PD_T_VDM_SNDR_RSP);
 	}
 
 	if (PE_CHK_FLAG(port, PE_FLAGS_MSG_DISCARDED)) {
@@ -5523,8 +5569,7 @@ static void pe_vdm_send_request_run(int port)
 	 */
 	if (pd_timer_is_expired(port, PE_TIMER_VDM_RESPONSE)) {
 		CPRINTF("VDM %s Response Timeout\n",
-				pe[port].tx_type == TCPCI_MSG_SOP ?
-				"Port" : "Cable");
+			pe[port].tx_type == TCPCI_MSG_SOP ? "Port" : "Cable");
 		/*
 		 * Flag timeout so child state can mark appropriate discovery
 		 * item as failed.
@@ -5572,8 +5617,8 @@ static void pe_vdm_identity_request_cbl_entry(int port)
 	}
 
 	msg[0] = VDO(USB_SID_PD, 1,
-			VDO_SVDM_VERS(pd_get_vdo_ver(port, pe[port].tx_type)) |
-			CMD_DISCOVER_IDENT);
+		     VDO_SVDM_VERS(pd_get_vdo_ver(port, pe[port].tx_type)) |
+			     CMD_DISCOVER_IDENT);
 	tx_emsg[port].len = sizeof(uint32_t);
 
 	send_data_msg(port, pe[port].tx_type, PD_DATA_VENDOR_DEF);
@@ -5590,7 +5635,7 @@ static void pe_vdm_identity_request_cbl_entry(int port)
 static void pe_vdm_identity_request_cbl_run(int port)
 {
 	/* Retrieve the message information */
-	uint32_t *payload = (uint32_t *) rx_emsg[port].buf;
+	uint32_t *payload = (uint32_t *)rx_emsg[port].buf;
 	int sop = PD_HEADER_GET_SOP(rx_emsg[port].header);
 	uint8_t type = PD_HEADER_TYPE(rx_emsg[port].header);
 	uint8_t cnt = PD_HEADER_CNT(rx_emsg[port].header);
@@ -5623,9 +5668,8 @@ static void pe_vdm_identity_request_cbl_run(int port)
 		 * state.
 		 */
 		if (get_last_state_pe(port) == PE_SRC_DISCOVERY &&
-					(sop != pe[port].tx_type ||
-					 type != PD_DATA_VENDOR_DEF ||
-					 cnt == 0 || ext != 0)) {
+		    (sop != pe[port].tx_type || type != PD_DATA_VENDOR_DEF ||
+		     cnt == 0 || ext != 0)) {
 			/*
 			 * Unexpected non-VDM received: Before an explicit
 			 * contract, an unexpected message shall generate a soft
@@ -5689,10 +5733,9 @@ static void pe_vdm_identity_request_cbl_exit(int port)
 	 * Not send any further SOP’/SOP’’ Messages.
 	 */
 	if (pe[port].discover_identity_counter >= N_DISCOVER_IDENTITY_COUNT)
-		pd_set_identity_discovery(port, pe[port].tx_type,
-				PD_DISC_FAIL);
+		pd_set_identity_discovery(port, pe[port].tx_type, PD_DISC_FAIL);
 	else if (pe[port].discover_identity_counter ==
-			N_DISCOVER_IDENTITY_PD3_0_LIMIT)
+		 N_DISCOVER_IDENTITY_PD3_0_LIMIT)
 		/*
 		 * Downgrade to PD 2.0 if the partner hasn't replied before
 		 * all retries are exhausted in case the cable is
@@ -5703,8 +5746,9 @@ static void pe_vdm_identity_request_cbl_exit(int port)
 	/*
 	 * Set discover identity timer unless BUSY case already did so.
 	 */
-	if (pd_get_identity_discovery(port, pe[port].tx_type) == PD_DISC_NEEDED
-	    && pd_timer_is_expired(port, PE_TIMER_DISCOVER_IDENTITY)) {
+	if (pd_get_identity_discovery(port, pe[port].tx_type) ==
+		    PD_DISC_NEEDED &&
+	    pd_timer_is_expired(port, PE_TIMER_DISCOVER_IDENTITY)) {
 		/*
 		 * The tDiscoverIdentity timer is used during an explicit
 		 * contract when discovering whether a cable is PD capable.
@@ -5714,17 +5758,18 @@ static void pe_vdm_identity_request_cbl_exit(int port)
 		 * power the SOP' responder from VBUS instead of VCONN.
 		 */
 		pd_timer_enable(port, PE_TIMER_DISCOVER_IDENTITY,
-				pe_is_explicit_contract(port)
-					? PD_T_DISCOVER_IDENTITY
-					: PE_T_DISCOVER_IDENTITY_NO_CONTRACT);
+				pe_is_explicit_contract(port) ?
+					PD_T_DISCOVER_IDENTITY :
+					PE_T_DISCOVER_IDENTITY_NO_CONTRACT);
 	}
 
 	/* Do not attempt further discovery if identity discovery failed. */
 	if (pd_get_identity_discovery(port, pe[port].tx_type) == PD_DISC_FAIL) {
 		pd_set_svids_discovery(port, pe[port].tx_type, PD_DISC_FAIL);
-		pd_notify_event(port, pe[port].tx_type == TCPCI_MSG_SOP ?
-				PD_STATUS_EVENT_SOP_DISC_DONE :
-				PD_STATUS_EVENT_SOP_PRIME_DISC_DONE);
+		pd_notify_event(port,
+				pe[port].tx_type == TCPCI_MSG_SOP ?
+					PD_STATUS_EVENT_SOP_DISC_DONE :
+					PD_STATUS_EVENT_SOP_PRIME_DISC_DONE);
 	}
 }
 
@@ -5743,8 +5788,8 @@ static void pe_init_port_vdm_identity_request_entry(int port)
 	print_current_state(port);
 
 	msg[0] = VDO(USB_SID_PD, 1,
-			VDO_SVDM_VERS(pd_get_vdo_ver(port, pe[port].tx_type)) |
-			CMD_DISCOVER_IDENT);
+		     VDO_SVDM_VERS(pd_get_vdo_ver(port, pe[port].tx_type)) |
+			     CMD_DISCOVER_IDENT);
 	tx_emsg[port].len = sizeof(uint32_t);
 
 	send_data_msg(port, pe[port].tx_type, PD_DATA_VENDOR_DEF);
@@ -5771,7 +5816,7 @@ static void pe_init_port_vdm_identity_request_run(int port)
 		break;
 	case VDM_RESULT_ACK: {
 		/* Retrieve the message information. */
-		uint32_t *payload = (uint32_t *) rx_emsg[port].buf;
+		uint32_t *payload = (uint32_t *)rx_emsg[port].buf;
 		int sop = PD_HEADER_GET_SOP(rx_emsg[port].header);
 		uint8_t cnt = PD_HEADER_CNT(rx_emsg[port].header);
 
@@ -5779,7 +5824,7 @@ static void pe_init_port_vdm_identity_request_run(int port)
 		dfp_consume_identity(port, sop, cnt, payload);
 
 		break;
-		}
+	}
 	case VDM_RESULT_NAK:
 		/* PE_INIT_PORT_VDM_IDENTITY_NAKed embedded here */
 		pd_set_identity_discovery(port, pe[port].tx_type, PD_DISC_FAIL);
@@ -5809,9 +5854,10 @@ static void pe_init_port_vdm_identity_request_exit(int port)
 	/* Do not attempt further discovery if identity discovery failed. */
 	if (pd_get_identity_discovery(port, pe[port].tx_type) == PD_DISC_FAIL) {
 		pd_set_svids_discovery(port, pe[port].tx_type, PD_DISC_FAIL);
-		pd_notify_event(port, pe[port].tx_type == TCPCI_MSG_SOP ?
-				PD_STATUS_EVENT_SOP_DISC_DONE :
-				PD_STATUS_EVENT_SOP_PRIME_DISC_DONE);
+		pd_notify_event(port,
+				pe[port].tx_type == TCPCI_MSG_SOP ?
+					PD_STATUS_EVENT_SOP_DISC_DONE :
+					PD_STATUS_EVENT_SOP_PRIME_DISC_DONE);
 	}
 }
 
@@ -5838,8 +5884,8 @@ static void pe_init_vdm_svids_request_entry(int port)
 	}
 
 	msg[0] = VDO(USB_SID_PD, 1,
-			VDO_SVDM_VERS(pd_get_vdo_ver(port, pe[port].tx_type)) |
-			CMD_DISCOVER_SVID);
+		     VDO_SVDM_VERS(pd_get_vdo_ver(port, pe[port].tx_type)) |
+			     CMD_DISCOVER_SVID);
 	tx_emsg[port].len = sizeof(uint32_t);
 
 	send_data_msg(port, pe[port].tx_type, PD_DATA_VENDOR_DEF);
@@ -5866,14 +5912,14 @@ static void pe_init_vdm_svids_request_run(int port)
 		break;
 	case VDM_RESULT_ACK: {
 		/* Retrieve the message information. */
-		uint32_t *payload = (uint32_t *) rx_emsg[port].buf;
+		uint32_t *payload = (uint32_t *)rx_emsg[port].buf;
 		int sop = PD_HEADER_GET_SOP(rx_emsg[port].header);
 		uint8_t cnt = PD_HEADER_CNT(rx_emsg[port].header);
 
 		/* PE_INIT_VDM_SVIDs_ACKed embedded here */
 		dfp_consume_svids(port, sop, cnt, payload);
 		break;
-		}
+	}
 	case VDM_RESULT_NAK:
 		/* PE_INIT_VDM_SVIDs_NAKed embedded here */
 		pd_set_svids_discovery(port, pe[port].tx_type, PD_DISC_FAIL);
@@ -5902,9 +5948,10 @@ static void pe_init_vdm_svids_request_exit(int port)
 
 	/* If SVID discovery failed, discovery is done at this point */
 	if (pd_get_svids_discovery(port, pe[port].tx_type) == PD_DISC_FAIL)
-		pd_notify_event(port, pe[port].tx_type == TCPCI_MSG_SOP ?
-				PD_STATUS_EVENT_SOP_DISC_DONE :
-				PD_STATUS_EVENT_SOP_PRIME_DISC_DONE);
+		pd_notify_event(port,
+				pe[port].tx_type == TCPCI_MSG_SOP ?
+					PD_STATUS_EVENT_SOP_DISC_DONE :
+					PD_STATUS_EVENT_SOP_PRIME_DISC_DONE);
 }
 
 /**
@@ -5935,14 +5982,14 @@ static void pe_init_vdm_modes_request_entry(int port)
 		 * is still disabled, there's nothing left to try.
 		 */
 		pd_set_modes_discovery(port, pe[port].tx_type, svid,
-				PD_DISC_FAIL);
+				       PD_DISC_FAIL);
 		set_state_pe(port, get_last_state_pe(port));
 		return;
 	}
 
-	msg[0] = VDO((uint16_t) svid, 1,
-			VDO_SVDM_VERS(pd_get_vdo_ver(port, pe[port].tx_type)) |
-			CMD_DISCOVER_MODES);
+	msg[0] = VDO((uint16_t)svid, 1,
+		     VDO_SVDM_VERS(pd_get_vdo_ver(port, pe[port].tx_type)) |
+			     CMD_DISCOVER_MODES);
 	tx_emsg[port].len = sizeof(uint32_t);
 
 	send_data_msg(port, pe[port].tx_type, PD_DATA_VENDOR_DEF);
@@ -5978,10 +6025,10 @@ static void pe_init_vdm_modes_request_run(int port)
 		break;
 	case VDM_RESULT_ACK: {
 		/* Retrieve the message information. */
-		uint32_t *payload = (uint32_t *) rx_emsg[port].buf;
+		uint32_t *payload = (uint32_t *)rx_emsg[port].buf;
 		int sop = PD_HEADER_GET_SOP(rx_emsg[port].header);
 		uint8_t cnt = PD_HEADER_CNT(rx_emsg[port].header);
-		uint16_t response_svid = (uint16_t) PD_VDO_VID(payload[0]);
+		uint16_t response_svid = (uint16_t)PD_VDO_VID(payload[0]);
 
 		/*
 		 * Accept ACK if the request and response SVIDs are equal;
@@ -5995,12 +6042,12 @@ static void pe_init_vdm_modes_request_run(int port)
 			dfp_consume_modes(port, sop, cnt, payload);
 			break;
 		}
-		}
+	}
 		/* Fall Through */
 	case VDM_RESULT_NAK:
 		/* PE_INIT_VDM_Modes_NAKed embedded here */
 		pd_set_modes_discovery(port, pe[port].tx_type, requested_svid,
-				PD_DISC_FAIL);
+				       PD_DISC_FAIL);
 		break;
 	}
 
@@ -6012,10 +6059,10 @@ static void pe_init_vdm_modes_request_exit(int port)
 {
 	if (pd_get_modes_discovery(port, pe[port].tx_type) != PD_DISC_NEEDED)
 		/* Mode discovery done, notify the AP */
-		pd_notify_event(port, pe[port].tx_type == TCPCI_MSG_SOP ?
-				PD_STATUS_EVENT_SOP_DISC_DONE :
-				PD_STATUS_EVENT_SOP_PRIME_DISC_DONE);
-
+		pd_notify_event(port,
+				pe[port].tx_type == TCPCI_MSG_SOP ?
+					PD_STATUS_EVENT_SOP_DISC_DONE :
+					PD_STATUS_EVENT_SOP_PRIME_DISC_DONE);
 }
 
 /**
@@ -6030,7 +6077,7 @@ static void pe_vdm_request_dpm_entry(int port)
 
 	if ((pe[port].tx_type == TCPCI_MSG_SOP_PRIME ||
 	     pe[port].tx_type == TCPCI_MSG_SOP_PRIME_PRIME) &&
-	     !pe_can_send_sop_prime(port)) {
+	    !pe_can_send_sop_prime(port)) {
 		/*
 		 * The parent state already tried to enable SOP' traffic. If it
 		 * is still disabled, there's nothing left to try.
@@ -6045,9 +6092,8 @@ static void pe_vdm_request_dpm_entry(int port)
 	/* Copy Vendor Data Objects (VDOs) into message buffer */
 	if (pe[port].vdm_cnt > 0) {
 		/* Copy data after header */
-		memcpy(&tx_emsg[port].buf,
-			(uint8_t *)pe[port].vdm_data,
-			pe[port].vdm_cnt * 4);
+		memcpy(&tx_emsg[port].buf, (uint8_t *)pe[port].vdm_data,
+		       pe[port].vdm_cnt * 4);
 		/* Update len with the number of VDO bytes */
 		tx_emsg[port].len = pe[port].vdm_cnt * 4;
 	}
@@ -6085,8 +6131,8 @@ static void pe_vdm_request_dpm_run(int port)
 		 * transmit is complete.
 		 */
 		vdm_hdr = pe[port].vdm_data[0];
-		if(PD_VDO_SVDM(vdm_hdr) &&
-		   (PD_VDO_CMD(vdm_hdr) == CMD_ATTENTION)) {
+		if (PD_VDO_SVDM(vdm_hdr) &&
+		    (PD_VDO_CMD(vdm_hdr) == CMD_ATTENTION)) {
 			if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) {
 				PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
 				break;
@@ -6108,7 +6154,7 @@ static void pe_vdm_request_dpm_run(int port)
 		break;
 	case VDM_RESULT_ACK: {
 		/* Retrieve the message information. */
-		uint32_t *payload = (uint32_t *) rx_emsg[port].buf;
+		uint32_t *payload = (uint32_t *)rx_emsg[port].buf;
 		int sop = PD_HEADER_GET_SOP(rx_emsg[port].header);
 		uint8_t cnt = PD_HEADER_CNT(rx_emsg[port].header);
 		uint16_t svid = PD_VDO_VID(payload[0]);
@@ -6121,11 +6167,11 @@ static void pe_vdm_request_dpm_run(int port)
 		dpm_vdm_acked(port, sop, cnt, payload);
 
 		if (sop == TCPCI_MSG_SOP && svid == USB_SID_DISPLAYPORT &&
-				vdm_cmd == CMD_DP_CONFIG) {
+		    vdm_cmd == CMD_DP_CONFIG) {
 			PE_SET_FLAG(port, PE_FLAGS_VDM_SETUP_DONE);
 		}
 		break;
-		}
+	}
 	case VDM_RESULT_NAK:
 		/*
 		 * PE initiator VDM-NAKed state for requested VDM, like
@@ -6139,8 +6185,8 @@ static void pe_vdm_request_dpm_run(int port)
 		 * Extract the needed information from the sent VDM.
 		 */
 		dpm_vdm_naked(port, pe[port].tx_type,
-				PD_VDO_VID(pe[port].vdm_data[0]),
-				PD_VDO_CMD(pe[port].vdm_data[0]));
+			      PD_VDO_VID(pe[port].vdm_data[0]),
+			      PD_VDO_CMD(pe[port].vdm_data[0]));
 		break;
 	}
 
@@ -6150,6 +6196,24 @@ static void pe_vdm_request_dpm_run(int port)
 
 static void pe_vdm_request_dpm_exit(int port)
 {
+	if (PE_CHK_FLAG(port, PE_FLAGS_VDM_REQUEST_TIMEOUT)) {
+		PE_CLR_FLAG(port, PE_FLAGS_VDM_REQUEST_TIMEOUT);
+		PE_SET_FLAG(port, PE_FLAGS_VDM_SETUP_DONE);
+
+		/*
+		 * Mark failure to respond as discovery failure.
+		 *
+		 * For PD 2.0 partners (6.10.3 Applicability of Structured VDM
+		 * Commands Note 3):
+		 *
+		 * If Structured VDMs are not supported, a Structured VDM
+		 * Command received by a DFP or UFP Shall be Ignored.
+		 */
+		dpm_vdm_naked(port, pe[port].tx_type,
+			      PD_VDO_VID(pe[port].vdm_data[0]),
+			      PD_VDO_CMD(pe[port].vdm_data[0]));
+	}
+
 	/*
 	 * Force Tx type to be reset before reentering a VDM state, unless the
 	 * current VDM request will be resumed.
@@ -6323,11 +6387,9 @@ static void pe_vdm_response_run(int port)
 	if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE) ||
 	    PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR) ||
 	    PE_CHK_FLAG(port, PE_FLAGS_MSG_DISCARDED)) {
-
-		PE_CLR_MASK(port,
-			    BIT(PE_FLAGS_TX_COMPLETE_FN) |
-			    BIT(PE_FLAGS_PROTOCOL_ERROR_FN) |
-			    BIT(PE_FLAGS_MSG_DISCARDED_FN));
+		PE_CLR_MASK(port, BIT(PE_FLAGS_TX_COMPLETE_FN) |
+					  BIT(PE_FLAGS_PROTOCOL_ERROR_FN) |
+					  BIT(PE_FLAGS_MSG_DISCARDED_FN));
 
 		pe_set_ready_state(port);
 	}
@@ -6360,7 +6422,7 @@ static void pe_enter_usb_entry(int port)
 
 	if ((pe[port].tx_type == TCPCI_MSG_SOP_PRIME ||
 	     pe[port].tx_type == TCPCI_MSG_SOP_PRIME_PRIME) &&
-	     !tc_is_vconn_src(port)) {
+	    !tc_is_vconn_src(port)) {
 		if (port_try_vconn_swap(port))
 			return;
 	}
@@ -6566,11 +6628,12 @@ static void pe_vcs_send_swap_run(int port)
 			 */
 			if (type == PD_CTRL_ACCEPT) {
 				if (tc_is_vconn_src(port)) {
-					set_state_pe(port,
+					set_state_pe(
+						port,
 						PE_VCS_WAIT_FOR_VCONN_SWAP);
 				} else {
 					set_state_pe(port,
-						PE_VCS_TURN_ON_VCONN_SWAP);
+						     PE_VCS_TURN_ON_VCONN_SWAP);
 				}
 				return;
 			}
@@ -6593,7 +6656,7 @@ static void pe_vcs_send_swap_run(int port)
 			 */
 			if (type == PD_CTRL_NOT_SUPPORTED) {
 				if (IS_ENABLED(CONFIG_USB_PD_REV30) &&
-							!tc_is_vconn_src(port))
+				    !tc_is_vconn_src(port))
 					set_state_pe(port, PE_VCS_FORCE_VCONN);
 				else
 					pe_set_ready_state(port);
@@ -6675,8 +6738,8 @@ static void pe_vcs_wait_for_vconn_swap_run(int port)
 			 * the incoming message.
 			 */
 			PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
-			pe_send_soft_reset(port,
-				PD_HEADER_GET_SOP(rx_emsg[port].header));
+			pe_send_soft_reset(
+				port, PD_HEADER_GET_SOP(rx_emsg[port].header));
 			return;
 		}
 	}
@@ -6718,7 +6781,6 @@ static void pe_vcs_turn_on_vconn_swap_entry(int port)
 
 static void pe_vcs_turn_on_vconn_swap_run(int port)
 {
-
 	/*
 	 * Transition to the PE_VCS_Send_Ps_Rdy state when:
 	 *  1) The Port’s VCONN is on.
@@ -6778,7 +6840,7 @@ static void pe_vcs_send_ps_rdy_swap_entry(int port)
 	/* Check for any interruptions to this non-interruptible AMS */
 	if (PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
 		enum tcpci_msg_type sop =
-				PD_HEADER_GET_SOP(rx_emsg[port].header);
+			PD_HEADER_GET_SOP(rx_emsg[port].header);
 
 		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
 
@@ -6906,7 +6968,7 @@ static void pe_vcs_cbl_send_soft_reset_run(int port)
 
 	/* Got ACCEPT or REJECT from Cable Plug */
 	if ((msg_check & PE_MSG_SENT) &&
-				PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
+	    PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
 		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
 		cable_soft_reset_complete = true;
 
@@ -7003,16 +7065,17 @@ static void pe_dr_get_sink_cap_run(int port)
 			if ((cnt > 0) && (type == PD_DATA_SINK_CAP)) {
 				uint32_t *payload =
 					(uint32_t *)rx_emsg[port].buf;
-				uint8_t cap_cnt = rx_emsg[port].len /
-							sizeof(uint32_t);
+				uint8_t cap_cnt =
+					rx_emsg[port].len / sizeof(uint32_t);
 
 				pe_set_snk_caps(port, cap_cnt, payload);
 
 				dpm_evaluate_sink_fixed_pdo(port, payload[0]);
 				pe_set_ready_state(port);
 				return;
-			} else if (cnt == 0 && (type == PD_CTRL_REJECT ||
-				   type == PD_CTRL_NOT_SUPPORTED)) {
+			} else if (cnt == 0 &&
+				   (type == PD_CTRL_REJECT ||
+				    type == PD_CTRL_NOT_SUPPORTED)) {
 				pe_set_ready_state(port);
 				return;
 			}
@@ -7126,12 +7189,13 @@ static void pe_dr_src_get_source_cap_run(int port)
 				 */
 				if (IS_ENABLED(CONFIG_CHARGE_MANAGER) &&
 				    pd_get_partner_dual_role_power(port))
-					charge_manager_update_dualrole(port,
-								CAP_DUALROLE);
+					charge_manager_update_dualrole(
+						port, CAP_DUALROLE);
 
 				set_state_pe(port, PE_SRC_READY);
-			} else if ((cnt == 0) && (type == PD_CTRL_REJECT ||
-					type == PD_CTRL_NOT_SUPPORTED)) {
+			} else if ((cnt == 0) &&
+				   (type == PD_CTRL_REJECT ||
+				    type == PD_CTRL_NOT_SUPPORTED)) {
 				pd_set_src_caps(port, -1, NULL);
 				set_state_pe(port, PE_SRC_READY);
 			} else {
@@ -7172,15 +7236,6 @@ __maybe_unused static void pe_get_revision_entry(int port)
 {
 	print_current_state(port);
 
-	/*
-	 * Only USB PD partners with major revision 3.0 could potentially
-	 * respond to Get_Revision.
-	 */
-	if (prl_get_rev(port, TCPCI_MSG_SOP) != PD_REV30) {
-		pe_set_ready_state(port);
-		return;
-	}
-
 	/* Send a Get_Revision message */
 	send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_GET_REVISION);
 	pe_sender_response_msg_entry(port);
@@ -7193,14 +7248,11 @@ __maybe_unused static void pe_get_revision_run(int port)
 	int ext;
 	enum pe_msg_check msg_check;
 
-	if (prl_get_rev(port, TCPCI_MSG_SOP) != PD_REV30)
-		return;
-
 	/* Check the state of the message sent */
 	msg_check = pe_sender_response_msg_run(port);
 
 	if ((msg_check & PE_MSG_SENT) &&
-	     PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
+	    PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) {
 		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
 
 		type = PD_HEADER_TYPE(rx_emsg[port].header);
@@ -7210,7 +7262,7 @@ __maybe_unused static void pe_get_revision_run(int port)
 		if (ext == 0 && cnt == 1 && type == PD_DATA_REVISION) {
 			/* Revision returned by partner */
 			pe[port].partner_rmdo =
-			    *((struct rmdo *) rx_emsg[port].buf);
+				*((struct rmdo *)rx_emsg[port].buf);
 		} else if (type != PD_CTRL_NOT_SUPPORTED) {
 			/*
 			 * If the partner response with a message other than
@@ -7235,14 +7287,10 @@ __maybe_unused static void pe_get_revision_run(int port)
 	if ((msg_check & PE_MSG_DISCARDED) ||
 	    pd_timer_is_expired(port, PE_TIMER_SENDER_RESPONSE))
 		pe_set_ready_state(port);
-
 }
 
 __maybe_unused static void pe_get_revision_exit(int port)
 {
-	if (prl_get_rev(port, TCPCI_MSG_SOP) != PD_REV30)
-		return;
-
 	pe_sender_response_msg_exit(port);
 }
 
@@ -7284,17 +7332,17 @@ static void pe_udr_send_data_reset_run(int port)
 		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
 
 		if (PD_HEADER_GET_SOP(hdr) == TCPCI_MSG_SOP &&
-				PD_HEADER_CNT(hdr) == 0 &&
-				!PD_HEADER_EXT(hdr) &&
-				PD_HEADER_TYPE(hdr) == PD_CTRL_ACCEPT) {
-			set_state_pe(port, tc_is_vconn_src(port) ?
+		    PD_HEADER_CNT(hdr) == 0 && !PD_HEADER_EXT(hdr) &&
+		    PD_HEADER_TYPE(hdr) == PD_CTRL_ACCEPT) {
+			set_state_pe(
+				port,
+				tc_is_vconn_src(port) ?
 					PE_UDR_TURN_OFF_VCONN :
 					PE_UDR_WAIT_FOR_DATA_RESET_COMPLETE);
 			return;
 		} else if (PD_HEADER_GET_SOP(hdr) == TCPCI_MSG_SOP &&
-				PD_HEADER_CNT(hdr) == 0 &&
-				!PD_HEADER_EXT(hdr) &&
-				PD_HEADER_TYPE(hdr) == PD_CTRL_NOT_SUPPORTED) {
+			   PD_HEADER_CNT(hdr) == 0 && !PD_HEADER_EXT(hdr) &&
+			   PD_HEADER_TYPE(hdr) == PD_CTRL_NOT_SUPPORTED) {
 			/* Just pretend it worked. */
 			dpm_data_reset_complete(port);
 			pe_set_ready_state(port);
@@ -7306,7 +7354,7 @@ static void pe_udr_send_data_reset_run(int port)
 	}
 
 	if (pd_timer_is_expired(port, PE_TIMER_SENDER_RESPONSE) ||
-			PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) {
+	    PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) {
 		PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
 		set_state_pe(port, PE_WAIT_FOR_ERROR_RECOVERY);
 		return;
@@ -7333,10 +7381,9 @@ static void pe_udr_data_reset_received_run(int port)
 		if (tc_is_vconn_src(port))
 			set_state_pe(port, PE_UDR_TURN_OFF_VCONN);
 		else
-			set_state_pe(port,
-					PE_UDR_WAIT_FOR_DATA_RESET_COMPLETE);
+			set_state_pe(port, PE_UDR_WAIT_FOR_DATA_RESET_COMPLETE);
 	} else if (PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR) ||
-			PE_CHK_FLAG(port, PE_FLAGS_MSG_DISCARDED)) {
+		   PE_CHK_FLAG(port, PE_FLAGS_MSG_DISCARDED)) {
 		PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
 		PE_CLR_FLAG(port, PE_FLAGS_MSG_DISCARDED);
 		set_state_pe(port, PE_WAIT_FOR_ERROR_RECOVERY);
@@ -7355,7 +7402,7 @@ static void pe_udr_turn_off_vconn_run(int port)
 {
 	/* Wait until VCONN is fully discharged */
 	if (pd_timer_is_disabled(port, PE_TIMER_TIMEOUT) &&
-			PE_CHK_FLAG(port, PE_FLAGS_VCONN_SWAP_COMPLETE)) {
+	    PE_CHK_FLAG(port, PE_FLAGS_VCONN_SWAP_COMPLETE)) {
 		PE_CLR_FLAG(port, PE_FLAGS_VCONN_SWAP_COMPLETE);
 		pd_timer_enable(port, PE_TIMER_TIMEOUT,
 				CONFIG_USBC_VCONN_SWAP_DELAY_US);
@@ -7379,7 +7426,7 @@ static void pe_udr_send_ps_rdy_run(int port)
 		PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE);
 		set_state_pe(port, PE_UDR_WAIT_FOR_DATA_RESET_COMPLETE);
 	} else if (PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR) ||
-			PE_CHK_FLAG(port, PE_FLAGS_MSG_DISCARDED)) {
+		   PE_CHK_FLAG(port, PE_FLAGS_MSG_DISCARDED)) {
 		PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
 		PE_CLR_FLAG(port, PE_FLAGS_MSG_DISCARDED);
 		set_state_pe(port, PE_WAIT_FOR_ERROR_RECOVERY);
@@ -7461,9 +7508,8 @@ static void pe_ddr_send_data_reset_run(int port)
 		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
 
 		if (PD_HEADER_GET_SOP(hdr) == TCPCI_MSG_SOP &&
-				PD_HEADER_CNT(hdr) == 0 &&
-				!PD_HEADER_EXT(hdr) &&
-				PD_HEADER_TYPE(hdr) == PD_CTRL_ACCEPT) {
+		    PD_HEADER_CNT(hdr) == 0 && !PD_HEADER_EXT(hdr) &&
+		    PD_HEADER_TYPE(hdr) == PD_CTRL_ACCEPT) {
 			/*
 			 * Start DataResetFailTimer NOTE: This timer continues
 			 * to run in every state until it is stopped or it times
@@ -7472,13 +7518,12 @@ static void pe_ddr_send_data_reset_run(int port)
 			pd_timer_enable(port, PE_TIMER_DATA_RESET_FAIL,
 					PD_T_DATA_RESET_FAIL);
 			set_state_pe(port, tc_is_vconn_src(port) ?
-					PE_DDR_PERFORM_DATA_RESET :
-					PE_DDR_WAIT_FOR_VCONN_OFF);
+						   PE_DDR_PERFORM_DATA_RESET :
+						   PE_DDR_WAIT_FOR_VCONN_OFF);
 			return;
 		} else if (PD_HEADER_GET_SOP(hdr) == TCPCI_MSG_SOP &&
-				PD_HEADER_CNT(hdr) == 0 &&
-				!PD_HEADER_EXT(hdr) &&
-				PD_HEADER_TYPE(hdr) == PD_CTRL_NOT_SUPPORTED) {
+			   PD_HEADER_CNT(hdr) == 0 && !PD_HEADER_EXT(hdr) &&
+			   PD_HEADER_TYPE(hdr) == PD_CTRL_NOT_SUPPORTED) {
 			/* Just pretend it worked. */
 			dpm_data_reset_complete(port);
 			pe_set_ready_state(port);
@@ -7490,7 +7535,7 @@ static void pe_ddr_send_data_reset_run(int port)
 	}
 
 	if (pd_timer_is_expired(port, PE_TIMER_SENDER_RESPONSE) ||
-			PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) {
+	    PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) {
 		PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
 		set_state_pe(port, PE_WAIT_FOR_ERROR_RECOVERY);
 		return;
@@ -7554,9 +7599,8 @@ static void pe_ddr_wait_for_vconn_off_run(int port)
 		PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED);
 
 		if (PD_HEADER_GET_SOP(hdr) == TCPCI_MSG_SOP &&
-				PD_HEADER_CNT(hdr) == 0 &&
-				!PD_HEADER_EXT(hdr) &&
-				PD_HEADER_TYPE(hdr) == PD_CTRL_PS_RDY) {
+		    PD_HEADER_CNT(hdr) == 0 && !PD_HEADER_EXT(hdr) &&
+		    PD_HEADER_TYPE(hdr) == PD_CTRL_PS_RDY) {
 			/* PS_RDY message received */
 			pd_timer_enable(port, PE_TIMER_VCONN_REAPPLIED,
 					PD_T_VCONN_REAPPLIED);
@@ -7569,7 +7613,7 @@ static void pe_ddr_wait_for_vconn_off_run(int port)
 	}
 
 	if (pd_timer_is_expired(port, PE_TIMER_VCONN_DISCHARGE) ||
-				PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) {
+	    PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) {
 		PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
 		set_state_pe(port, PE_WAIT_FOR_ERROR_RECOVERY);
 		return;
@@ -7596,7 +7640,7 @@ static void pe_ddr_perform_data_reset_entry(int port)
 	 *    c) If operating in [USB4] drive the port’s SBTX to a logic low.
 	 */
 	usb_mux_set(port, USB_PD_MUX_NONE, USB_SWITCH_DISCONNECT,
-			polarity_rm_dts(pd_get_polarity(port)));
+		    polarity_rm_dts(pd_get_polarity(port)));
 
 	/* 2) Both the DFP and UFP Shall exit all Alternate Modes if any. */
 	if (IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP)) {
@@ -7635,18 +7679,18 @@ static void pe_ddr_perform_data_reset_run(int port)
 	 * expires. At this point, the Data Reset process is complete.
 	 */
 	if (IS_ENABLED(CONFIG_USBC_VCONN) && !tc_is_vconn_src(port) &&
-			PE_CHK_FLAG(port, PE_FLAGS_VCONN_SWAP_COMPLETE)) {
+	    PE_CHK_FLAG(port, PE_FLAGS_VCONN_SWAP_COMPLETE)) {
 		PE_CLR_FLAG(port, PE_FLAGS_VCONN_SWAP_COMPLETE);
 		/* Wait until VCONN has discharged to start tVconnReapplied. */
 		pd_timer_enable(port, PE_TIMER_TIMEOUT,
-			CONFIG_USBC_VCONN_SWAP_DELAY_US);
+				CONFIG_USBC_VCONN_SWAP_DELAY_US);
 	} else if (IS_ENABLED(CONFIG_USBC_VCONN) &&
-			pd_timer_is_expired(port, PE_TIMER_TIMEOUT)) {
+		   pd_timer_is_expired(port, PE_TIMER_TIMEOUT)) {
 		pd_timer_disable(port, PE_TIMER_TIMEOUT);
 		pd_timer_enable(port, PE_TIMER_VCONN_REAPPLIED,
 				PD_T_VCONN_REAPPLIED);
 	} else if (IS_ENABLED(CONFIG_USBC_VCONN) &&
-			pd_timer_is_expired(port, PE_TIMER_VCONN_REAPPLIED)) {
+		   pd_timer_is_expired(port, PE_TIMER_VCONN_REAPPLIED)) {
 		pd_request_vconn_swap_on(port);
 		pd_timer_disable(port, PE_TIMER_VCONN_REAPPLIED);
 
@@ -7664,15 +7708,21 @@ static void pe_ddr_perform_data_reset_run(int port)
 		 * ambiguity and update this implementation.
 		 */
 		usb_mux_set(port, USB_PD_MUX_NONE, USB_SWITCH_DISCONNECT,
-				polarity_rm_dts(pd_get_polarity(port)));
+			    polarity_rm_dts(pd_get_polarity(port)));
 	} else if (IS_ENABLED(CONFIG_USBC_VCONN) &&
-			PE_CHK_FLAG(port, PE_FLAGS_VCONN_SWAP_COMPLETE) &&
-			tc_is_vconn_src(port)) {
+		   PE_CHK_FLAG(port, PE_FLAGS_VCONN_SWAP_COMPLETE) &&
+		   tc_is_vconn_src(port)) {
 		PE_CLR_FLAG(port, PE_FLAGS_VCONN_SWAP_COMPLETE);
 		PE_SET_FLAG(port, PE_FLAGS_DATA_RESET_COMPLETE);
 	} else if (PE_CHK_FLAG(port, PE_FLAGS_DATA_RESET_COMPLETE) &&
-			!pd_timer_is_disabled(port, PE_TIMER_DATA_RESET_FAIL)) {
+		   !pd_timer_is_disabled(port, PE_TIMER_DATA_RESET_FAIL)) {
 		pd_timer_disable(port, PE_TIMER_DATA_RESET_FAIL);
+		/*
+		 * Because the cable power-cycled, reset the Tx (optional) and
+		 * cached Rx (mandatory) message IDs.
+		 */
+		prl_reset_msg_ids(port, TCPCI_MSG_SOP_PRIME);
+		prl_reset_msg_ids(port, TCPCI_MSG_SOP_PRIME_PRIME);
 		send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_DATA_RESET_COMPLETE);
 	} else if (PE_CHK_FLAG(port, PE_FLAGS_DATA_RESET_COMPLETE)) {
 		/*
@@ -7689,7 +7739,7 @@ static void pe_ddr_perform_data_reset_run(int port)
 		}
 		return;
 	} else if (pd_timer_is_expired(port, PE_TIMER_DATA_RESET_FAIL) ||
-				PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) {
+		   PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) {
 		PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR);
 		set_state_pe(port, PE_WAIT_FOR_ERROR_RECOVERY);
 		return;
@@ -7709,11 +7759,12 @@ static void pe_ddr_perform_data_reset_exit(int port)
 	pd_timer_disable(port, PE_TIMER_VCONN_REAPPLIED);
 	pd_timer_disable(port, PE_TIMER_DATA_RESET_FAIL);
 	PE_CLR_FLAG(port, PE_FLAGS_DATA_RESET_COMPLETE);
+	pd_dpm_request(port, DPM_REQUEST_PORT_DISCOVERY);
 	dpm_data_reset_complete(port);
 }
 #endif /* CONFIG_USB_PD_DATA_RESET_MSG */
 
-const uint32_t * const pd_get_src_caps(int port)
+const uint32_t *const pd_get_src_caps(int port)
 {
 	return pe[port].src_caps;
 }
@@ -7746,7 +7797,6 @@ void pd_dfp_discovery_init(int port)
 		  BIT(task_get_current()));
 
 	memset(pe[port].discovery, 0, sizeof(pe[port].discovery));
-
 }
 
 void pd_dfp_mode_init(int port)
@@ -7755,9 +7805,8 @@ void pd_dfp_mode_init(int port)
 	 * Clear the VDM Setup Done and Modal Operation flags so we will
 	 * have a fresh discovery
 	 */
-	PE_CLR_MASK(port,
-		    BIT(PE_FLAGS_VDM_SETUP_DONE_FN) |
-		    BIT(PE_FLAGS_MODAL_OPERATION_FN));
+	PE_CLR_MASK(port, BIT(PE_FLAGS_VDM_SETUP_DONE_FN) |
+				  BIT(PE_FLAGS_MODAL_OPERATION_FN));
 
 	memset(pe[port].partner_amodes, 0, sizeof(pe[port].partner_amodes));
 
@@ -7776,7 +7825,7 @@ void pd_dfp_mode_init(int port)
 }
 
 __maybe_unused void pd_discovery_access_clear(int port,
-			enum tcpci_msg_type type)
+					      enum tcpci_msg_type type)
 {
 	if (!IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP))
 		assert(0);
@@ -7785,7 +7834,7 @@ __maybe_unused void pd_discovery_access_clear(int port,
 }
 
 __maybe_unused bool pd_discovery_access_validate(int port,
-			enum tcpci_msg_type type)
+						 enum tcpci_msg_type type)
 {
 	if (!IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP))
 		assert(0);
@@ -7793,15 +7842,15 @@ __maybe_unused bool pd_discovery_access_validate(int port,
 	return !(task_access[port][type] & ~BIT(task_get_current()));
 }
 
-__maybe_unused struct pd_discovery *pd_get_am_discovery_and_notify_access(
-				int port, enum tcpci_msg_type type)
+__maybe_unused struct pd_discovery *
+pd_get_am_discovery_and_notify_access(int port, enum tcpci_msg_type type)
 {
 	atomic_or(&task_access[port][type], BIT(task_get_current()));
 	return (struct pd_discovery *)pd_get_am_discovery(port, type);
 }
 
-__maybe_unused const struct pd_discovery *pd_get_am_discovery(int port,
-			enum tcpci_msg_type type)
+__maybe_unused const struct pd_discovery *
+pd_get_am_discovery(int port, enum tcpci_msg_type type)
 {
 	if (!IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP))
 		assert(0);
@@ -7810,8 +7859,8 @@ __maybe_unused const struct pd_discovery *pd_get_am_discovery(int port,
 	return &pe[port].discovery[type];
 }
 
-__maybe_unused struct partner_active_modes *pd_get_partner_active_modes(
-			int port, enum tcpci_msg_type type)
+__maybe_unused struct partner_active_modes *
+pd_get_partner_active_modes(int port, enum tcpci_msg_type type)
 {
 	if (!IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP))
 		assert(0);
@@ -7847,7 +7896,7 @@ uint32_t pe_get_flags(int port)
 }
 
 static __const_data const struct usb_state pe_states[] = {
-	/* Super States */
+/* Super States */
 #ifdef CONFIG_USB_PD_REV30
 	[PE_PRS_FRS_SHARED] = {
 		.entry = pe_prs_frs_shared_entry,
@@ -8179,6 +8228,9 @@ static __const_data const struct usb_state pe_states[] = {
 		.entry = pe_send_alert_entry,
 		.run   = pe_send_alert_run,
 	},
+	[PE_ALERT_RECEIVED] = {
+		.entry = pe_alert_received_entry,
+	},
 #else
 	[PE_SRC_CHUNK_RECEIVED] = {
 		.entry = pe_chunk_received_entry,
diff --git a/common/usbc/usb_pe_private.h b/common/usbc/usb_pe_private.h
index e68c4c2fcd..bfe534dcca 100644
--- a/common/usbc/usb_pe_private.h
+++ b/common/usbc/usb_pe_private.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,76 +13,84 @@
  */
 
 enum {
-/* At least one successful PD communication packet received from port partner */
+	/* At least one successful PD communication packet received from port
+	   partner */
 	PE_FLAGS_PD_CONNECTION_FN = 0,
-/* Accept message received from port partner */
+	/* Accept message received from port partner */
 	PE_FLAGS_ACCEPT_FN,
-/* Power Supply Ready message received from port partner */
+	/* Power Supply Ready message received from port partner */
 	PE_FLAGS_PS_READY_FN,
-/* Protocol Error was determined based on error recovery current state */
+	/* Protocol Error was determined based on error recovery current state
+	 */
 	PE_FLAGS_PROTOCOL_ERROR_FN,
-/* Set if we are in Modal Operation */
+	/* Set if we are in Modal Operation */
 	PE_FLAGS_MODAL_OPERATION_FN,
-/* A message we requested to be sent has been transmitted */
+	/* A message we requested to be sent has been transmitted */
 	PE_FLAGS_TX_COMPLETE_FN,
-/* A message sent by a port partner has been received */
+	/* A message sent by a port partner has been received */
 	PE_FLAGS_MSG_RECEIVED_FN,
-/* A hard reset has been requested but has not been sent, not currently used */
+	/* A hard reset has been requested but has not been sent, not currently
+	   used */
 	PE_FLAGS_HARD_RESET_PENDING_FN,
-/* Port partner sent a Wait message. Wait before we resend our message */
+	/* Port partner sent a Wait message. Wait before we resend our message
+	 */
 	PE_FLAGS_WAIT_FN,
-/* An explicit contract is in place with our port partner */
+	/* An explicit contract is in place with our port partner */
 	PE_FLAGS_EXPLICIT_CONTRACT_FN,
-/* Waiting for Sink Capabailities timed out.  Used for retry error handling */
+	/* Waiting for Sink Capabailities timed out.  Used for retry error
+	   handling */
 	PE_FLAGS_SNK_WAIT_CAP_TIMEOUT_FN,
-/* Power Supply voltage/current transition timed out */
+	/* Power Supply voltage/current transition timed out */
 	PE_FLAGS_PS_TRANSITION_TIMEOUT_FN,
-/* Flag to note current Atomic Message Sequence is interruptible */
+	/* Flag to note current Atomic Message Sequence is interruptible */
 	PE_FLAGS_INTERRUPTIBLE_AMS_FN,
-/* Flag to note Power Supply reset has completed */
+	/* Flag to note Power Supply reset has completed */
 	PE_FLAGS_PS_RESET_COMPLETE_FN,
-/* VCONN swap operation has completed */
+	/* VCONN swap operation has completed */
 	PE_FLAGS_VCONN_SWAP_COMPLETE_FN,
-/* Flag to note no more setup VDMs (discovery, etc.) should be sent */
+	/* Flag to note no more setup VDMs (discovery, etc.) should be sent */
 	PE_FLAGS_VDM_SETUP_DONE_FN,
-/* Flag to note PR Swap just completed for Startup entry */
+	/* Flag to note PR Swap just completed for Startup entry */
 	PE_FLAGS_PR_SWAP_COMPLETE_FN,
-/* Flag to note Port Discovery port partner replied with BUSY */
+	/* Flag to note Port Discovery port partner replied with BUSY */
 	PE_FLAGS_VDM_REQUEST_BUSY_FN,
-/* Flag to note Port Discovery port partner replied with NAK */
+	/* Flag to note Port Discovery port partner replied with NAK */
 	PE_FLAGS_VDM_REQUEST_NAKED_FN,
-/* Flag to note FRS/PRS context in shared state machine path */
+	/* Flag to note FRS/PRS context in shared state machine path */
 	PE_FLAGS_FAST_ROLE_SWAP_PATH_FN,
-/* Flag to note if FRS listening is enabled */
+	/* Flag to note if FRS listening is enabled */
 	PE_FLAGS_FAST_ROLE_SWAP_ENABLED_FN,
-/* Flag to note TCPC passed on FRS signal from port partner */
+	/* Flag to note TCPC passed on FRS signal from port partner */
 	PE_FLAGS_FAST_ROLE_SWAP_SIGNALED_FN,
-/* TODO: POLICY decision: Triggers a DR SWAP attempt from UFP to DFP */
+	/* TODO: POLICY decision: Triggers a DR SWAP attempt from UFP to DFP */
 	PE_FLAGS_DR_SWAP_TO_DFP_FN,
-/*
- * TODO: POLICY decision
- * Flag to trigger a message resend after receiving a WAIT from port partner
- */
+	/*
+	 * TODO: POLICY decision
+	 * Flag to trigger a message resend after receiving a WAIT from port
+	 * partner
+	 */
 	PE_FLAGS_WAITING_PR_SWAP_FN,
-/* FLAG is set when an AMS is initiated locally. ie. AP requested a PR_SWAP */
+	/* FLAG is set when an AMS is initiated locally. ie. AP requested a
+	   PR_SWAP */
 	PE_FLAGS_LOCALLY_INITIATED_AMS_FN,
-/* Flag to note the first message sent in PE_SRC_READY and PE_SNK_READY */
+	/* Flag to note the first message sent in PE_SRC_READY and PE_SNK_READY
+	 */
 	PE_FLAGS_FIRST_MSG_FN,
-/* Flag to continue a VDM request if it was interrupted */
+	/* Flag to continue a VDM request if it was interrupted */
 	PE_FLAGS_VDM_REQUEST_CONTINUE_FN,
-/* TODO: POLICY decision: Triggers a Vconn SWAP attempt to on */
+	/* TODO: POLICY decision: Triggers a Vconn SWAP attempt to on */
 	PE_FLAGS_VCONN_SWAP_TO_ON_FN,
-/* FLAG to track that VDM request to port partner timed out */
+	/* FLAG to track that VDM request to port partner timed out */
 	PE_FLAGS_VDM_REQUEST_TIMEOUT_FN,
-/* FLAG to note message was discarded due to incoming message */
+	/* FLAG to note message was discarded due to incoming message */
 	PE_FLAGS_MSG_DISCARDED_FN,
-/* FLAG to note that hard reset can't be performed due to battery low */
+	/* FLAG to note that hard reset can't be performed due to battery low */
 	PE_FLAGS_SNK_WAITING_BATT_FN,
-/* FLAG to note that a data reset is complete */
+	/* FLAG to note that a data reset is complete */
 	PE_FLAGS_DATA_RESET_COMPLETE_FN,
-/* Waiting for SRC to SNK settle time */
+	/* Waiting for SRC to SNK settle time */
 	PE_FLAGS_SRC_SNK_SETTLE_FN,
-/* Last element */
+	/* Last element */
 	PE_FLAGS_COUNT
 };
 
diff --git a/common/usbc/usb_prl_sm.c b/common/usbc/usb_prl_sm.c
index 805e6dfcd8..b1843da6eb 100644
--- a/common/usbc/usb_prl_sm.c
+++ b/common/usbc/usb_prl_sm.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,6 +6,7 @@
 #include "battery.h"
 #include "battery_smart.h"
 #include "board.h"
+#include "builtin/assert.h"
 #include "charge_manager.h"
 #include "charge_state.h"
 #include "chipset.h"
@@ -33,8 +34,8 @@
 #include "vpd_api.h"
 
 #ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 #else
 #define CPRINTF(format, args...)
 #define CPRINTS(format, args...)
@@ -46,27 +47,25 @@
 #undef DEBUG_PRINT_FLAG_NAMES
 
 #ifdef DEBUG_PRINT_FLAG_NAMES
-__maybe_unused static void print_flag(const char *group,
-				      int set_or_clear,
+__maybe_unused static void print_flag(const char *group, int set_or_clear,
 				      int flag);
-#define SET_FLAG(group, flags, flag)                     \
-	do {                                             \
-		print_flag(group, 1, flag);              \
-		atomic_or(flags, (flag));                \
+#define SET_FLAG(group, flags, flag)        \
+	do {                                \
+		print_flag(group, 1, flag); \
+		atomic_or(flags, (flag));   \
 	} while (0)
-#define CLR_FLAG(group, flags, flag)                     \
-	do {                                             \
-		int before = *flags;                     \
-		atomic_clear_bits(flags, (flag));        \
-		if (*flags != before)                    \
-			print_flag(group, 0, flag);      \
+#define CLR_FLAG(group, flags, flag)                \
+	do {                                        \
+		int before = *flags;                \
+		atomic_clear_bits(flags, (flag));   \
+		if (*flags != before)               \
+			print_flag(group, 0, flag); \
 	} while (0)
 #else
 #define SET_FLAG(group, flags, flag) atomic_or(flags, (flag))
 #define CLR_FLAG(group, flags, flag) atomic_clear_bits(flags, (flag))
 #endif
 
-
 #define RCH_SET_FLAG(port, flag) SET_FLAG("RCH", &rch[port].flags, (flag))
 #define RCH_CLR_FLAG(port, flag) CLR_FLAG("RCH", &rch[port].flags, (flag))
 #define RCH_CHK_FLAG(port, flag) (rch[port].flags & (flag))
@@ -98,34 +97,34 @@ __maybe_unused static void print_flag(const char *group,
  *	different meanings in each state machine.
  */
 /* Flag to note message transmission completed */
-#define PRL_FLAGS_TX_COMPLETE             BIT(0)
+#define PRL_FLAGS_TX_COMPLETE BIT(0)
 /* Flag to note that PRL requested to set SINK_NG CC state */
-#define PRL_FLAGS_SINK_NG                 BIT(1)
+#define PRL_FLAGS_SINK_NG BIT(1)
 /* Flag to note PRL waited for SINK_OK CC state before transmitting */
-#define PRL_FLAGS_WAIT_SINK_OK            BIT(2)
+#define PRL_FLAGS_WAIT_SINK_OK BIT(2)
 /* Flag to note transmission error occurred */
-#define PRL_FLAGS_TX_ERROR                BIT(3)
+#define PRL_FLAGS_TX_ERROR BIT(3)
 /* Flag to note PE triggered a hard reset */
-#define PRL_FLAGS_PE_HARD_RESET           BIT(4)
+#define PRL_FLAGS_PE_HARD_RESET BIT(4)
 /* Flag to note hard reset has completed */
-#define PRL_FLAGS_HARD_RESET_COMPLETE     BIT(5)
+#define PRL_FLAGS_HARD_RESET_COMPLETE BIT(5)
 /* Flag to note port partner sent a hard reset */
 #define PRL_FLAGS_PORT_PARTNER_HARD_RESET BIT(6)
 /*
  * Flag to note a message transmission has been requested. It is only cleared
  * when we send the message to the TCPC layer.
  */
-#define PRL_FLAGS_MSG_XMIT                BIT(7)
+#define PRL_FLAGS_MSG_XMIT BIT(7)
 /* Flag to note a message was received */
-#define PRL_FLAGS_MSG_RECEIVED            BIT(8)
+#define PRL_FLAGS_MSG_RECEIVED BIT(8)
 /* Flag to note aborting current TX message, not currently set */
-#define PRL_FLAGS_ABORT                   BIT(9)
+#define PRL_FLAGS_ABORT BIT(9)
 /* Flag to note current TX message uses chunking */
-#define PRL_FLAGS_CHUNKING                BIT(10)
+#define PRL_FLAGS_CHUNKING BIT(10)
 
 struct bit_name {
-	int		value;
-	const char	*name;
+	int value;
+	const char *name;
 };
 
 static __const_data const struct bit_name flag_bit_names[] = {
@@ -136,17 +135,15 @@ static __const_data const struct bit_name flag_bit_names[] = {
 	{ PRL_FLAGS_PE_HARD_RESET, "PRL_FLAGS_PE_HARD_RESET" },
 	{ PRL_FLAGS_HARD_RESET_COMPLETE, "PRL_FLAGS_HARD_RESET_COMPLETE" },
 	{ PRL_FLAGS_PORT_PARTNER_HARD_RESET,
-		"PRL_FLAGS_PORT_PARTNER_HARD_RESET" },
+	  "PRL_FLAGS_PORT_PARTNER_HARD_RESET" },
 	{ PRL_FLAGS_MSG_XMIT, "PRL_FLAGS_MSG_XMIT" },
 	{ PRL_FLAGS_MSG_RECEIVED, "PRL_FLAGS_MSG_RECEIVED" },
 	{ PRL_FLAGS_ABORT, "PRL_FLAGS_ABORT" },
 	{ PRL_FLAGS_CHUNKING, "PRL_FLAGS_CHUNKING" },
 };
 
-__maybe_unused static void print_bits(const char *group,
-				      const char *desc,
-				      int value,
-				      const struct bit_name *names,
+__maybe_unused static void print_bits(const char *group, const char *desc,
+				      int value, const struct bit_name *names,
 				      int names_size)
 {
 	int i;
@@ -162,8 +159,7 @@ __maybe_unused static void print_bits(const char *group,
 	CPRINTF("\n");
 }
 
-__maybe_unused static void print_flag(const char *group,
-				      int set_or_clear,
+__maybe_unused static void print_flag(const char *group, int set_or_clear,
 				      int flag)
 {
 	print_bits(group, set_or_clear ? "Set" : "Clr", flag, flag_bit_names,
@@ -189,6 +185,8 @@ __maybe_unused static void print_flag(const char *group,
  */
 #ifdef CONFIG_USB_PD_DEBUG_LEVEL
 static const enum debug_level prl_debug_level = CONFIG_USB_PD_DEBUG_LEVEL;
+#elif defined(CONFIG_USB_PD_INITIAL_DEBUG_LEVEL)
+static enum debug_level prl_debug_level = CONFIG_USB_PD_INITIAL_DEBUG_LEVEL;
 #else
 static enum debug_level prl_debug_level = DEBUG_LEVEL_1;
 #endif
@@ -238,7 +236,7 @@ enum usb_tch_state {
 	TCH_REPORT_ERROR,
 };
 
-static const char * const prl_tx_state_names[] = {
+static const char *const prl_tx_state_names[] = {
 	[PRL_TX_PHY_LAYER_RESET] = "PRL_TX_PHY_LAYER_RESET",
 	[PRL_TX_WAIT_FOR_MESSAGE_REQUEST] = "PRL_TX_WAIT_FOR_MESSAGE_REQUEST",
 	[PRL_TX_LAYER_RESET_FOR_TRANSMIT] = "PRL_TX_LAYER_RESET_FOR_TRANSMIT",
@@ -250,18 +248,18 @@ static const char * const prl_tx_state_names[] = {
 	[PRL_TX_DISCARD_MESSAGE] = "PRL_TX_DISCARD_MESSAGE",
 };
 
-static const char * const prl_hr_state_names[] = {
+static const char *const prl_hr_state_names[] = {
 	[PRL_HR_WAIT_FOR_REQUEST] = "PRL_HR_WAIT_FOR_REQUEST",
 	[PRL_HR_RESET_LAYER] = "PRL_HR_RESET_LAYER",
-	[PRL_HR_WAIT_FOR_PHY_HARD_RESET_COMPLETE]
-		= "PRL_HR_WAIT_FOR_PHY_HARD_RESET_COMPLETE",
-	[PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE]
-		= "PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE",
+	[PRL_HR_WAIT_FOR_PHY_HARD_RESET_COMPLETE] =
+		"PRL_HR_WAIT_FOR_PHY_HARD_RESET_COMPLETE",
+	[PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE] =
+		"PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE",
 };
 
-__maybe_unused static const char * const rch_state_names[] = {
-	[RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER]
-		= "RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER",
+__maybe_unused static const char *const rch_state_names[] = {
+	[RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER] =
+		"RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER",
 	[RCH_PASS_UP_MESSAGE] = "RCH_PASS_UP_MESSAGE",
 	[RCH_PROCESSING_EXTENDED_MESSAGE] = "RCH_PROCESSING_EXTENDED_MESSAGE",
 	[RCH_REQUESTING_CHUNK] = "RCH_REQUESTING_CHUNK",
@@ -269,11 +267,11 @@ __maybe_unused static const char * const rch_state_names[] = {
 	[RCH_REPORT_ERROR] = "RCH_REPORT_ERROR",
 };
 
-__maybe_unused static const char * const tch_state_names[] = {
-	[TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE]
-		= "TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE",
-	[TCH_WAIT_FOR_TRANSMISSION_COMPLETE]
-		= "TCH_WAIT_FOR_TRANSMISSION_COMPLETE",
+__maybe_unused static const char *const tch_state_names[] = {
+	[TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE] =
+		"TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE",
+	[TCH_WAIT_FOR_TRANSMISSION_COMPLETE] =
+		"TCH_WAIT_FOR_TRANSMISSION_COMPLETE",
 	[TCH_CONSTRUCT_CHUNKED_MESSAGE] = "TCH_CONSTRUCT_CHUNKED_MESSAGE",
 	[TCH_SENDING_CHUNKED_MESSAGE] = "TCH_SENDING_CHUNKED_MESSAGE",
 	[TCH_WAIT_CHUNK_REQUEST] = "TCH_WAIT_CHUNK_REQUEST",
@@ -380,12 +378,12 @@ GEN_NOT_SUPPORTED(PRL_TX_SNK_START_AMS);
 
 GEN_NOT_SUPPORTED(RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER);
 #define RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER \
-		RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER_NOT_SUPPORTED
+	RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER_NOT_SUPPORTED
 GEN_NOT_SUPPORTED(RCH_PASS_UP_MESSAGE);
 #define RCH_PASS_UP_MESSAGE RCH_PASS_UP_MESSAGE_NOT_SUPPORTED
 GEN_NOT_SUPPORTED(RCH_PROCESSING_EXTENDED_MESSAGE);
 #define RCH_PROCESSING_EXTENDED_MESSAGE \
-		RCH_PROCESSING_EXTENDED_MESSAGE_NOT_SUPPORTED
+	RCH_PROCESSING_EXTENDED_MESSAGE_NOT_SUPPORTED
 GEN_NOT_SUPPORTED(RCH_REQUESTING_CHUNK);
 #define RCH_REQUESTING_CHUNK RCH_REQUESTING_CHUNK_NOT_SUPPORTED
 GEN_NOT_SUPPORTED(RCH_WAITING_CHUNK);
@@ -395,13 +393,13 @@ GEN_NOT_SUPPORTED(RCH_REPORT_ERROR);
 
 GEN_NOT_SUPPORTED(TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE);
 #define TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE \
-		TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE_NOT_SUPPORTED
+	TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE_NOT_SUPPORTED
 GEN_NOT_SUPPORTED(TCH_WAIT_FOR_TRANSMISSION_COMPLETE);
 #define TCH_WAIT_FOR_TRANSMISSION_COMPLETE \
-		TCH_WAIT_FOR_TRANSMISSION_COMPLETE_NOT_SUPPORTED
+	TCH_WAIT_FOR_TRANSMISSION_COMPLETE_NOT_SUPPORTED
 GEN_NOT_SUPPORTED(TCH_CONSTRUCT_CHUNKED_MESSAGE);
 #define TCH_CONSTRUCT_CHUNKED_MESSAGE \
-		TCH_CONSTRUCT_CHUNKED_MESSAGE_NOT_SUPPORTED
+	TCH_CONSTRUCT_CHUNKED_MESSAGE_NOT_SUPPORTED
 GEN_NOT_SUPPORTED(TCH_SENDING_CHUNKED_MESSAGE);
 #define TCH_SENDING_CHUNKED_MESSAGE TCH_SENDING_CHUNKED_MESSAGE_NOT_SUPPORTED
 GEN_NOT_SUPPORTED(TCH_WAIT_CHUNK_REQUEST);
@@ -435,7 +433,7 @@ static void print_current_prl_tx_state(const int port)
 {
 	if (prl_debug_level >= DEBUG_LEVEL_3)
 		CPRINTS("C%d: %s", port,
-				prl_tx_state_names[prl_tx_get_state(port)]);
+			prl_tx_state_names[prl_tx_get_state(port)]);
 }
 
 /* Set the hard reset statemachine to a new state. */
@@ -456,7 +454,7 @@ static void print_current_prl_hr_state(const int port)
 {
 	if (prl_debug_level >= DEBUG_LEVEL_3)
 		CPRINTS("C%d: %s", port,
-				prl_hr_state_names[prl_hr_get_state(port)]);
+			prl_hr_state_names[prl_hr_get_state(port)]);
 }
 
 /* Set the chunked Rx statemachine to a new state. */
@@ -477,8 +475,7 @@ test_export_static enum usb_rch_state rch_get_state(const int port)
 static void print_current_rch_state(const int port)
 {
 	if (prl_debug_level >= DEBUG_LEVEL_3)
-		CPRINTS("C%d: %s", port,
-				rch_state_names[rch_get_state(port)]);
+		CPRINTS("C%d: %s", port, rch_state_names[rch_get_state(port)]);
 }
 #endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
 
@@ -503,12 +500,10 @@ test_export_static enum usb_tch_state tch_get_state(const int port)
 static void print_current_tch_state(const int port)
 {
 	if (prl_debug_level >= DEBUG_LEVEL_3)
-		CPRINTS("C%d: %s", port,
-				tch_state_names[tch_get_state(port)]);
+		CPRINTS("C%d: %s", port, tch_state_names[tch_get_state(port)]);
 }
 #endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
 
-
 timestamp_t prl_get_tcpc_tx_success_ts(int port)
 {
 	return tcpc_tx_success_ts[port];
@@ -578,10 +573,8 @@ static void prl_init(int port)
 
 	prl_hr[port].flags = 0;
 
-	for (i = 0; i < NUM_SOP_STAR_TYPES; i++) {
-		prl_rx[port].msg_id[i] = -1;
-		prl_tx[port].msg_id_counter[i] = 0;
-	}
+	for (i = 0; i < NUM_SOP_STAR_TYPES; i++)
+		prl_reset_msg_ids(port, i);
 
 	pd_timer_disable_range(port, PR_TIMER_RANGE);
 
@@ -605,9 +598,8 @@ bool prl_is_busy(int port)
 {
 #ifdef CONFIG_USB_PD_EXTENDED_MESSAGES
 	return rch_get_state(port) !=
-			RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER ||
-		tch_get_state(port) !=
-			TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE;
+		       RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER ||
+	       tch_get_state(port) != TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE;
 #else
 	return false;
 #endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
@@ -626,9 +618,8 @@ void prl_hard_reset_complete(int port)
 	task_wake(PD_PORT_TO_TASK_ID(port));
 }
 
-void prl_send_ctrl_msg(int port,
-		      enum tcpci_msg_type type,
-		      enum pd_ctrl_msg_type msg)
+void prl_send_ctrl_msg(int port, enum tcpci_msg_type type,
+		       enum pd_ctrl_msg_type msg)
 {
 	pdmsg[port].xmit_type = type;
 	pdmsg[port].msg_type = msg;
@@ -646,9 +637,8 @@ void prl_send_ctrl_msg(int port,
 	task_wake(PD_PORT_TO_TASK_ID(port));
 }
 
-void prl_send_data_msg(int port,
-		      enum tcpci_msg_type type,
-		      enum pd_data_msg_type msg)
+void prl_send_data_msg(int port, enum tcpci_msg_type type,
+		       enum pd_data_msg_type msg)
 {
 	pdmsg[port].xmit_type = type;
 	pdmsg[port].msg_type = msg;
@@ -666,9 +656,8 @@ void prl_send_data_msg(int port,
 }
 
 #ifdef CONFIG_USB_PD_EXTENDED_MESSAGES
-void prl_send_ext_data_msg(int port,
-			  enum tcpci_msg_type type,
-			  enum pd_ext_msg_type msg)
+void prl_send_ext_data_msg(int port, enum tcpci_msg_type type,
+			   enum pd_ext_msg_type msg)
 {
 	pdmsg[port].xmit_type = type;
 	pdmsg[port].msg_type = msg;
@@ -736,11 +725,9 @@ void prl_run(int port, int evt, int en)
 		 * reset.
 		 */
 		if (prl_hr_get_state(port) == PRL_HR_WAIT_FOR_REQUEST) {
-
 			/* Run Protocol Layer Message Reception */
 			prl_rx_wait_for_phy_message(port, evt);
 
-
 			if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES)) {
 				/*
 				 * Run RX Chunked state machine after prl_rx.
@@ -772,8 +759,7 @@ void prl_run(int port, int evt, int en)
 	}
 }
 
-void prl_set_rev(int port, enum tcpci_msg_type type,
-						enum pd_rev_type rev)
+void prl_set_rev(int port, enum tcpci_msg_type type, enum pd_rev_type rev)
 {
 	/* We only store revisions for SOP* types. */
 	ASSERT(type < NUM_SOP_STAR_TYPES);
@@ -789,6 +775,12 @@ enum pd_rev_type prl_get_rev(int port, enum tcpci_msg_type type)
 	return pdmsg[port].rev[type];
 }
 
+void prl_reset_msg_ids(int port, enum tcpci_msg_type type)
+{
+	prl_tx[port].msg_id_counter[type] = 0;
+	prl_rx[port].msg_id[type] = -1;
+}
+
 static void prl_copy_msg_to_buffer(int port)
 {
 	/*
@@ -814,7 +806,7 @@ static void prl_copy_msg_to_buffer(int port)
 	/* Copy message to chunked buffer */
 	memset((uint8_t *)pdmsg[port].tx_chk_buf, 0, CHK_BUF_SIZE_BYTES);
 	memcpy((uint8_t *)pdmsg[port].tx_chk_buf, (uint8_t *)tx_emsg[port].buf,
-		tx_emsg[port].len);
+	       tx_emsg[port].len);
 	/*
 	 * Pad length to 4-byte boundary and
 	 * convert to number of 32-bit objects.
@@ -828,8 +820,8 @@ static void prl_copy_msg_to_buffer(int port)
 static __maybe_unused int pdmsg_xmit_type_is_rev30(const int port)
 {
 	if (IS_ENABLED(CONFIG_USB_PD_REV30))
-		return ((pdmsg[port].xmit_type < NUM_SOP_STAR_TYPES)
-		&& (prl_get_rev(port, pdmsg[port].xmit_type) == PD_REV30));
+		return ((pdmsg[port].xmit_type < NUM_SOP_STAR_TYPES) &&
+			(prl_get_rev(port, pdmsg[port].xmit_type) == PD_REV30));
 	else
 		return 0;
 }
@@ -846,8 +838,7 @@ static void prl_tx_phy_layer_reset_entry(const int port)
 {
 	print_current_prl_tx_state(port);
 
-	if (IS_ENABLED(CONFIG_USB_CTVPD)
-	 || IS_ENABLED(CONFIG_USB_VPD)) {
+	if (IS_ENABLED(CONFIG_USB_CTVPD) || IS_ENABLED(CONFIG_USB_VPD)) {
 		vpd_rx_enable(pd_is_connected(port));
 	} else {
 		/* Note: can't clear PHY messages due to TCPC architecture */
@@ -884,7 +875,7 @@ static void prl_tx_wait_for_message_request_run(const int port)
 	if (IS_ENABLED(CONFIG_USB_PD_REV30) && is_sop_rev30(port) &&
 	    pe_in_local_ams(port)) {
 		if (PRL_TX_CHK_FLAG(port, PRL_FLAGS_SINK_NG |
-					  PRL_FLAGS_WAIT_SINK_OK)) {
+						  PRL_FLAGS_WAIT_SINK_OK)) {
 			/*
 			 * If we are already in an AMS then allow the
 			 * multi-message AMS to continue, even if we
@@ -915,7 +906,7 @@ static void prl_tx_wait_for_message_request_run(const int port)
 		 * Soft Reset Message Message pending
 		 */
 		if ((pdmsg[port].msg_type == PD_CTRL_SOFT_RESET) &&
-						(tx_emsg[port].len == 0)) {
+		    (tx_emsg[port].len == 0)) {
 			set_state_prl_tx(port, PRL_TX_LAYER_RESET_FOR_TRANSMIT);
 		}
 		/*
@@ -1031,16 +1022,14 @@ static void prl_tx_layer_reset_for_transmit_entry(const int port)
 		 * From section 6.3.13 Soft Reset Message in the USB PD 3.0
 		 * v2.0 spec, Soft_Reset Message Shall be targeted at a
 		 * specific entity depending on the type of SOP* Packet used.
-		 */
-		prl_tx[port].msg_id_counter[pdmsg[port].xmit_type] = 0;
-
-		/*
+		 *
+		 *
 		 * From section 6.11.2.3.2, the MessageID should be cleared
 		 * from the PRL_Rx_Layer_Reset_for_Receive state. However, we
 		 * don't implement a full state machine for PRL RX states so
 		 * clear the MessageID here.
 		 */
-		prl_rx[port].msg_id[pdmsg[port].xmit_type] = -1;
+		prl_reset_msg_ids(port, pdmsg[port].xmit_type);
 	}
 }
 
@@ -1063,23 +1052,21 @@ static uint32_t get_sop_star_header(const int port)
 #endif
 
 	/* SOP vs SOP'/SOP" headers are different. Replace fields as needed */
-	return PD_HEADER(
-		pdmsg[port].msg_type,
-		is_sop_packet ?
-			pd_get_power_role(port) : tc_get_cable_plug(port),
-		is_sop_packet ?
-			pd_get_data_role(port) : 0,
-		prl_tx[port].msg_id_counter[pdmsg[port].xmit_type],
-		pdmsg[port].data_objs,
-		pdmsg[port].rev[pdmsg[port].xmit_type],
-		ext);
+	return PD_HEADER(pdmsg[port].msg_type,
+			 is_sop_packet ? pd_get_power_role(port) :
+					 tc_get_cable_plug(port),
+			 is_sop_packet ? pd_get_data_role(port) : 0,
+			 prl_tx[port].msg_id_counter[pdmsg[port].xmit_type],
+			 pdmsg[port].data_objs,
+			 pdmsg[port].rev[pdmsg[port].xmit_type], ext);
 }
 
 static void prl_tx_construct_message(const int port)
 {
 	/* The header is unused for hard reset, etc. */
 	const uint32_t header = pdmsg[port].xmit_type < NUM_SOP_STAR_TYPES ?
-		get_sop_star_header(port) : 0;
+					get_sop_star_header(port) :
+					0;
 
 	/* Save SOP* so the correct msg_id_counter can be incremented */
 	prl_tx[port].last_xmit_type = pdmsg[port].xmit_type;
@@ -1199,7 +1186,7 @@ static void prl_tx_src_pending_run(const int port)
 		 * SinkTxTimer timeout
 		 */
 		if ((tx_emsg[port].len == 0) &&
-			(pdmsg[port].msg_type == PD_CTRL_SOFT_RESET)) {
+		    (pdmsg[port].msg_type == PD_CTRL_SOFT_RESET)) {
 			set_state_prl_tx(port, PRL_TX_LAYER_RESET_FOR_TRANSMIT);
 		}
 		/* Message pending (except Soft Reset) &
@@ -1259,7 +1246,7 @@ static void prl_tx_snk_pending_run(const int port)
 		 * Rp = SinkTxOk
 		 */
 		if ((pdmsg[port].msg_type == PD_CTRL_SOFT_RESET) &&
-					(tx_emsg[port].len == 0)) {
+		    (tx_emsg[port].len == 0)) {
 			set_state_prl_tx(port, PRL_TX_LAYER_RESET_FOR_TRANSMIT);
 		}
 		/*
@@ -1305,7 +1292,7 @@ static void prl_hr_wait_for_request_entry(const int port)
 static void prl_hr_wait_for_request_run(const int port)
 {
 	if (PRL_HR_CHK_FLAG(port, PRL_FLAGS_PE_HARD_RESET |
-				PRL_FLAGS_PORT_PARTNER_HARD_RESET))
+					  PRL_FLAGS_PORT_PARTNER_HARD_RESET))
 		set_state_prl_hr(port, PRL_HR_RESET_LAYER);
 }
 
@@ -1327,13 +1314,11 @@ static void prl_hr_reset_layer_entry(const int port)
 
 	/* Hard reset resets messageIDCounters for all TX types */
 	for (i = 0; i < NUM_SOP_STAR_TYPES; i++) {
-		prl_rx[port].msg_id[i] = -1;
-		prl_tx[port].msg_id_counter[i] = 0;
+		prl_reset_msg_ids(port, i);
 	}
 
 	/* Disable RX */
-	if (IS_ENABLED(CONFIG_USB_CTVPD) ||
-	    IS_ENABLED(CONFIG_USB_VPD))
+	if (IS_ENABLED(CONFIG_USB_CTVPD) || IS_ENABLED(CONFIG_USB_VPD))
 		vpd_rx_enable(0);
 	else
 		tcpm_set_rx_enable(port, 0);
@@ -1396,8 +1381,7 @@ static void prl_hr_wait_for_phy_hard_reset_complete_entry(const int port)
 	print_current_prl_hr_state(port);
 
 	/* Start HardResetCompleteTimer */
-	pd_timer_enable(port, PR_TIMER_HARD_RESET_COMPLETE,
-			PD_T_PS_HARD_RESET);
+	pd_timer_enable(port, PR_TIMER_HARD_RESET_COMPLETE, PD_T_PS_HARD_RESET);
 }
 
 static void prl_hr_wait_for_phy_hard_reset_complete_run(const int port)
@@ -1455,11 +1439,11 @@ static void copy_chunk_to_ext(int port)
 {
 	/* Calculate number of bytes */
 	pdmsg[port].num_bytes_received =
-				(PD_HEADER_CNT(rx_emsg[port].header) * 4);
+		(PD_HEADER_CNT(rx_emsg[port].header) * 4);
 
 	/* Copy chunk into extended message */
 	memcpy((uint8_t *)rx_emsg[port].buf, (uint8_t *)pdmsg[port].rx_chk_buf,
-		pdmsg[port].num_bytes_received);
+	       pdmsg[port].num_bytes_received);
 
 	/* Set extended message length */
 	rx_emsg[port].len = pdmsg[port].num_bytes_received;
@@ -1491,10 +1475,10 @@ static void rch_wait_for_message_from_protocol_layer_run(const int port)
 		 * Are we communicating with a PD3.0 device and is
 		 * this an extended message?
 		 */
-		if (pdmsg_xmit_type_is_rev30(port)
-		    && PD_HEADER_EXT(rx_emsg[port].header)) {
+		if (pdmsg_xmit_type_is_rev30(port) &&
+		    PD_HEADER_EXT(rx_emsg[port].header)) {
 			uint16_t exhdr =
-					GET_EXT_HEADER(*pdmsg[port].rx_chk_buf);
+				GET_EXT_HEADER(*pdmsg[port].rx_chk_buf);
 			uint8_t chunked = PD_EXT_HEADER_CHUNKED(exhdr);
 
 			/*
@@ -1502,7 +1486,7 @@ static void rch_wait_for_message_from_protocol_layer_run(const int port)
 			 * (Chunking = 1 & Chunked = 1)
 			 */
 			if ((RCH_CHK_FLAG(port, PRL_FLAGS_CHUNKING)) &&
-								chunked) {
+			    chunked) {
 				/*
 				 * RCH_Processing_Extended_Message first chunk
 				 * entry processing embedded here
@@ -1524,7 +1508,7 @@ static void rch_wait_for_message_from_protocol_layer_run(const int port)
 			 * (Chunking = 0 & Chunked = 0))
 			 */
 			else if (!RCH_CHK_FLAG(port, PRL_FLAGS_CHUNKING) &&
-								!chunked) {
+				 !chunked) {
 				/* Copy chunk to extended buffer */
 				copy_chunk_to_ext(port);
 				set_state_rch(port, RCH_PASS_UP_MESSAGE);
@@ -1602,8 +1586,8 @@ static void rch_processing_extended_message_run(const int port)
 			byte_num = PD_MAX_EXTENDED_MSG_CHUNK_LEN;
 
 		/* Make sure extended message buffer does not overflow */
-		if (pdmsg[port].num_bytes_received +
-					byte_num > EXTENDED_BUFFER_SIZE) {
+		if (pdmsg[port].num_bytes_received + byte_num >
+		    EXTENDED_BUFFER_SIZE) {
 			rch[port].error = ERR_RCH_CHUNKED;
 			set_state_rch(port, RCH_REPORT_ERROR);
 			return;
@@ -1612,9 +1596,8 @@ static void rch_processing_extended_message_run(const int port)
 		/* Append data */
 		/* Add 2 to chk_buf to skip over extended message header */
 		memcpy(((uint8_t *)rx_emsg[port].buf +
-				pdmsg[port].num_bytes_received),
-				(uint8_t *)pdmsg[port].rx_chk_buf + 2,
-				byte_num);
+			pdmsg[port].num_bytes_received),
+		       (uint8_t *)pdmsg[port].rx_chk_buf + 2, byte_num);
 		/* increment chunk number expected */
 		pdmsg[port].chunk_number_expected++;
 		/* adjust num bytes received */
@@ -1623,7 +1606,7 @@ static void rch_processing_extended_message_run(const int port)
 		/* Was that the last chunk? */
 		if (pdmsg[port].num_bytes_received >= data_size) {
 			rx_emsg[port].len = pdmsg[port].num_bytes_received;
-			 /* Pass Message to Policy Engine */
+			/* Pass Message to Policy Engine */
 			set_state_rch(port, RCH_PASS_UP_MESSAGE);
 		}
 		/*
@@ -1652,11 +1635,11 @@ static void rch_requesting_chunk_entry(const int port)
 	 * Send Chunk Request to Protocol Layer
 	 * with chunk number = Chunk_Number_Expected
 	 */
-	pdmsg[port].tx_chk_buf[0] = PD_EXT_HEADER(
-				pdmsg[port].chunk_number_expected,
-				1, /* Request Chunk */
-				0 /* Data Size */
-				);
+	pdmsg[port].tx_chk_buf[0] =
+		PD_EXT_HEADER(pdmsg[port].chunk_number_expected, 1, /* Request
+								       Chunk */
+			      0 /* Data Size */
+		);
 
 	pdmsg[port].data_objs = 1;
 	pdmsg[port].ext = 1;
@@ -1827,16 +1810,15 @@ static void tch_wait_for_message_request_from_pe_run(const int port)
 		 * Discard the Message
 		 */
 		if (rch_get_state(port) !=
-				RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER) {
+		    RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER) {
 			tch[port].error = ERR_TCH_XMIT;
 			set_state_tch(port, TCH_REPORT_ERROR);
 		} else {
 			/*
 			 * Extended Message Request & Chunking
 			 */
-			if (pdmsg_xmit_type_is_rev30(port)
-			    && pdmsg[port].ext
-			    && TCH_CHK_FLAG(port, PRL_FLAGS_CHUNKING)) {
+			if (pdmsg_xmit_type_is_rev30(port) && pdmsg[port].ext &&
+			    TCH_CHK_FLAG(port, PRL_FLAGS_CHUNKING)) {
 				/*
 				 * NOTE: TCH_Prepare_To_Send_Chunked_Message
 				 * embedded here.
@@ -1855,7 +1837,8 @@ static void tch_wait_for_message_request_from_pe_run(const int port)
 
 				/* Pass Message to Protocol Layer */
 				PRL_TX_SET_FLAG(port, PRL_FLAGS_MSG_XMIT);
-				set_state_tch(port,
+				set_state_tch(
+					port,
 					TCH_WAIT_FOR_TRANSMISSION_COMPLETE);
 			}
 		}
@@ -1900,7 +1883,7 @@ static void tch_wait_for_transmission_complete_run(const int port)
 	 * the tx message was sent successfully.
 	 */
 	if (TCH_CHK_FLAG(port, PRL_FLAGS_MSG_RECEIVED) &&
-	     prl_tx[port].xmit_status != TCPC_TX_COMPLETE_SUCCESS) {
+	    prl_tx[port].xmit_status != TCPC_TX_COMPLETE_SUCCESS) {
 		TCH_CLR_FLAG(port, PRL_FLAGS_MSG_RECEIVED);
 		set_state_tch(port, TCH_MESSAGE_RECEIVED);
 		return;
@@ -1937,8 +1920,9 @@ static void tch_construct_chunked_message_entry(const int port)
 		num = PD_MAX_EXTENDED_MSG_CHUNK_LEN;
 
 	/* Set the chunks extended header */
-	*ext_hdr = PD_EXT_HEADER(pdmsg[port].chunk_number_to_send,
-				 0, /* Chunk Request */
+	*ext_hdr = PD_EXT_HEADER(pdmsg[port].chunk_number_to_send, 0, /* Chunk
+									 Request
+								       */
 				 tx_emsg[port].len);
 
 	/* Copy the message chunk into chk_buf */
@@ -2036,7 +2020,8 @@ static void tch_wait_chunk_request_run(const int port)
 				 */
 				if (PD_EXT_HEADER_CHUNK_NUM(exthdr) ==
 				    pdmsg[port].chunk_number_to_send) {
-					set_state_tch(port,
+					set_state_tch(
+						port,
 						TCH_CONSTRUCT_CHUNKED_MESSAGE);
 				}
 				/*
@@ -2111,8 +2096,6 @@ static void tch_message_sent_entry(const int port)
 		return;
 	}
 
-
-
 	set_state_tch(port, TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE);
 }
 
@@ -2136,7 +2119,6 @@ static void tch_report_error_entry(const int port)
 		return;
 	}
 
-
 	set_state_tch(port, TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE);
 }
 #endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */
@@ -2176,7 +2158,7 @@ static void prl_rx_wait_for_phy_message(const int port, int evt)
 
 	/* dump received packet content (only dump ping at debug level MAX) */
 	if ((prl_debug_level >= DEBUG_LEVEL_2 && type != PD_CTRL_PING) ||
-		prl_debug_level >= DEBUG_LEVEL_3) {
+	    prl_debug_level >= DEBUG_LEVEL_3) {
 		int p;
 
 		ccprintf("C%d: RECV %04x/%d ", port, header, cnt);
@@ -2189,8 +2171,7 @@ static void prl_rx_wait_for_phy_message(const int port, int evt)
 	 * Ignore messages sent to the cable from our
 	 * port partner if we aren't Vconn powered device.
 	 */
-	if (!IS_ENABLED(CONFIG_USB_CTVPD) &&
-	    !IS_ENABLED(CONFIG_USB_VPD) &&
+	if (!IS_ENABLED(CONFIG_USB_CTVPD) && !IS_ENABLED(CONFIG_USB_VPD) &&
 	    PD_HEADER_GET_SOP(header) != TCPCI_MSG_SOP &&
 	    PD_HEADER_PROLE(header) == PD_PLUG_FROM_DFP_UFP)
 		return;
@@ -2214,19 +2195,17 @@ static void prl_rx_wait_for_phy_message(const int port, int evt)
 
 	/* Handle incoming soft reset as special case */
 	if (cnt == 0 && type == PD_CTRL_SOFT_RESET) {
-		/* Clear MessageIdCounter */
-		prl_tx[port].msg_id_counter[prl_rx[port].sop] = 0;
-		/* Clear stored MessageID value */
-		prl_rx[port].msg_id[prl_rx[port].sop] = -1;
+		/* Clear MessageIdCounter and stored MessageID value. */
+		prl_reset_msg_ids(port, prl_rx[port].sop);
 
 		/* Soft Reset occurred */
 		set_state_prl_tx(port, PRL_TX_PHY_LAYER_RESET);
 
 		if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES)) {
 			set_state_rch(port,
-				RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER);
+				      RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER);
 			set_state_tch(port,
-				TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE);
+				      TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE);
 		}
 
 		/*
@@ -2286,7 +2265,7 @@ static void prl_rx_wait_for_phy_message(const int port, int evt)
 		 * tch_wait_for_message_request_from_pe has been run
 		 */
 		else if (tch_get_state(port) !=
-				TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE ||
+				 TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE ||
 			 TCH_CHK_FLAG(port, PRL_FLAGS_MSG_XMIT)) {
 			/* NOTE: RTR_TX_CHUNKS State embedded here. */
 			/*
diff --git a/common/usbc/usb_retimer_fw_update.c b/common/usbc/usb_retimer_fw_update.c
index 1c3023db9b..3f9b1b4c72 100644
--- a/common/usbc/usb_retimer_fw_update.c
+++ b/common/usbc/usb_retimer_fw_update.c
@@ -1,10 +1,12 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include <stdbool.h>
 #include <stdint.h>
+
+#include "builtin/assert.h"
 #include "compile_time_macros.h"
 #include "console.h"
 #include "hooks.h"
@@ -14,14 +16,20 @@
 #include "usb_tc_sm.h"
 
 #ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
 #else
 #define CPRINTS(format, args...)
 #define CPRINTF(format, args...)
 #endif
 
 /*
+ * Update retimer firmware of no device attached (NDA) ports
+ *
+ * https://docs.kernel.org/admin-guide/thunderbolt.html#
+ * upgrading-on-board-retimer-nvm-when-there-is-no-cable-connected
+ *
+ * On EC side:
  * Retimer firmware update is initiated by AP.
  * The operations requested by AP are:
  * 0 - USB_RETIMER_FW_UPDATE_QUERY_PORT
@@ -43,10 +51,52 @@
  * If 4/5/6/7 is received, TC_FLAGS_USB_RETIMER_FW_UPDATE_LTD_RUN is
  * set, PD task should be in suspended mode and process it.
  *
+ * On host side:
+ * 1. Put NDA ports into offline mode.
+ *    This forces retimer to power on, and requests EC to suspend
+ *    PD port, set USB mux to USB, Safe then TBT.
+ * 2. Scan for retimers
+ * 3. Update retimer NVM firmware.
+ * 4. Authenticate.
+ * 5. Wait 5 or more seconds for retimer to come back.
+ * 6. Put NDA ports into online mode -- the functional state.
+ *    This requestes EC to disconnect(set USB mux to 0), resume PD port.
+ *
+ * Error recovery:
+ * As mentioned above, to put port online, host sends two requests to EC
+ * 1. Disconnect USB MUX: USB_RETIMER_FW_UPDATE_DISCONNECT
+ * if step 1 is successful, then
+ * 2. Resume PD port: USB_RETIMER_FW_UPDATE_RESUME_PD
+ *
+ * If step 1 fails, host will not send step 2. This means no
+ * resume request from host. PD port stays in suspended state.
+ * EC needs an error recovery to resume PD port by itself.
+ *
+ * Below is how error recovery works:
+ * PD port state is set to RETIMER_ONLINE_REQUESTED when receives
+ * "Disconnect USB MUX"; a deferred call is set up too. When EC resumes
+ * port upon host's request, port state will be set to RETIMER_ONLINE;
+ * or port state stays RETIMER_ONLINE_REQUESTED if host doesn't request.
+ * By the time the deferrred call is fired, it will check if any port is
+ * still in RETIMER_ONLINE_REQUESTED state. If true, EC will put the
+ * port online by itself. That is, retry disconnect and unconditionally
+ * resume the port.
  */
 
 #define SUSPEND 1
-#define RESUME  0
+#define RESUME 0
+
+enum retimer_port_state {
+	RETIMER_ONLINE,
+	RETIMER_OFFLINE,
+	RETIMER_ONLINE_REQUESTED
+};
+
+/*
+ * Two seconds buffer is added on top of required 5 seconds;
+ * to cover the time to disconnect and resume.
+ */
+#define RETIMTER_ONLINE_DELAY (7 * SECOND)
 
 /* Track current port AP requested to update retimer firmware */
 static int cur_port;
@@ -54,7 +104,7 @@ static int last_op; /* Operation received from AP via ACPI_WRITE */
 /* Operation result returned to ACPI_READ */
 static int last_result;
 /* Track port state: SUSPEND or RESUME */
-static int port_state[CONFIG_USB_PD_PORT_MAX_COUNT];
+static enum retimer_port_state port_state[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 int usb_retimer_fw_update_get_result(void)
 {
@@ -87,12 +137,13 @@ int usb_retimer_fw_update_get_result(void)
 	return result;
 }
 
-static void retimer_fw_update_set_port_state(int port, int state)
+static void retimer_fw_update_set_port_state(int port,
+					     enum retimer_port_state state)
 {
 	port_state[port] = state;
 }
 
-static int retimer_fw_update_get_port_state(int port)
+static enum retimer_port_state retimer_fw_update_get_port_state(int port)
 {
 	return port_state[port];
 }
@@ -101,16 +152,16 @@ static int retimer_fw_update_get_port_state(int port)
  * @brief Suspend or resume PD task and update the state of the port.
  *
  * @param port PD port
- * @param state
- * SUSPEND: suspend PD task for firmware update; and set state to SUSPEND
- * RESUME: resume PD task after firmware update is done; and set state
- * to RESUME.
+ * @param suspend
+ * SUSPEND: suspend PD task; set state to RETIMER_OFFLINE
+ * RESUME: resume PD task; set state to RETIMER_ONLINE.
  *
  */
-static void retimer_fw_update_port_handler(int port, int state)
+static void retimer_fw_update_port_handler(int port, bool suspend)
 {
-	pd_set_suspend(port, state);
-	retimer_fw_update_set_port_state(port, state);
+	pd_set_suspend(port, suspend);
+	retimer_fw_update_set_port_state(
+		port, suspend == SUSPEND ? RETIMER_OFFLINE : RETIMER_ONLINE);
 }
 
 static void deferred_pd_suspend(void)
@@ -124,14 +175,74 @@ static inline mux_state_t retimer_fw_update_usb_mux_get(int port)
 	return usb_mux_get(port) & USB_RETIMER_FW_UPDATE_MUX_MASK;
 }
 
+/*
+ * Host will wait maximum 300ms for result; otherwise it's error.
+ * so the polling takes 300ms too.
+ */
+#define POLLING_CYCLE 15
+#define POLLING_TIME_MS 20
+
+static bool query_usb_mux_set_completed_timeout(int port)
+{
+	int i;
+
+	for (i = 0; i < POLLING_CYCLE; i++) {
+		if (!usb_mux_set_completed(port))
+			msleep(POLLING_TIME_MS);
+		else
+			return false;
+	}
+
+	return true;
+}
+
+static void retry_online(int port)
+{
+	usb_mux_set(port, USB_PD_MUX_NONE, USB_SWITCH_DISCONNECT,
+		    pd_get_polarity(port));
+	/* Wait maximum 300 ms for USB mux to be set */
+	query_usb_mux_set_completed_timeout(port);
+	/* Resume the port unconditionally */
+	retimer_fw_update_port_handler(port, RESUME);
+}
+
+/*
+ * After NVM update, if AP skips step 5, not wait 5+ seconds for retimer
+ * to come back; then do step 6 immediately, requesting EC to put
+ * retimer online. Step 6 will fail; port is still offline afterwards.
+ *
+ * This deferred function monitors if any port has this problem and retry
+ * online one more time.
+ */
+static void retimer_check_online(void)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		if (retimer_fw_update_get_port_state(i) ==
+		    RETIMER_ONLINE_REQUESTED) {
+			/*
+			 * Now the time has passed RETIMTER_ONLINE_DELAY;
+			 * retry online.
+			 * The port is suspended; if the port is not
+			 * suspended, DISCONNECT request won't go through,
+			 * we couldn't be here.
+			 */
+			retry_online(i);
+			/* PD port is resumed */
+		}
+	}
+}
+DECLARE_DEFERRED(retimer_check_online);
+
 /* Allow mux results to be filled in during HOOKS if needed */
 static void last_result_mux_get(void);
 DECLARE_DEFERRED(last_result_mux_get);
 
 static void last_result_mux_get(void)
 {
-	if (!usb_mux_set_completed(cur_port)) {
-		hook_call_deferred(&last_result_mux_get_data, 20 * MSEC);
+	if (query_usb_mux_set_completed_timeout(cur_port)) {
+		last_result = USB_RETIMER_FW_UPDATE_ERR;
 		return;
 	}
 
@@ -175,8 +286,8 @@ void usb_retimer_fw_update_process_op_cb(int port)
 		result_mux_get = true;
 		break;
 	case USB_RETIMER_FW_UPDATE_SET_USB:
-		usb_mux_set(port, USB_PD_MUX_USB_ENABLED,
-			USB_SWITCH_CONNECT, pd_get_polarity(port));
+		usb_mux_set(port, USB_PD_MUX_USB_ENABLED, USB_SWITCH_CONNECT,
+			    pd_get_polarity(port));
 		result_mux_get = true;
 		break;
 	case USB_RETIMER_FW_UPDATE_SET_SAFE:
@@ -185,13 +296,21 @@ void usb_retimer_fw_update_process_op_cb(int port)
 		break;
 	case USB_RETIMER_FW_UPDATE_SET_TBT:
 		usb_mux_set(port, USB_PD_MUX_TBT_COMPAT_ENABLED,
-			USB_SWITCH_CONNECT, pd_get_polarity(port));
+			    USB_SWITCH_CONNECT, pd_get_polarity(port));
 		result_mux_get = true;
 		break;
 	case USB_RETIMER_FW_UPDATE_DISCONNECT:
-		usb_mux_set(port, USB_PD_MUX_NONE,
-			USB_SWITCH_DISCONNECT, pd_get_polarity(port));
+		usb_mux_set(port, USB_PD_MUX_NONE, USB_SWITCH_DISCONNECT,
+			    pd_get_polarity(port));
 		result_mux_get = true;
+		/*
+		 * Host decides to put retimer online; now disconnects USB MUX
+		 * and sets port state to "RETIMER_ONLINE_REQUESTED".
+		 */
+		retimer_fw_update_set_port_state(port,
+						 RETIMER_ONLINE_REQUESTED);
+		hook_call_deferred(&retimer_check_online_data,
+				   RETIMTER_ONLINE_DELAY);
 		break;
 	default:
 		break;
@@ -210,12 +329,32 @@ void usb_retimer_fw_update_process_op(int port, int op)
 	ASSERT(port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 
 	/*
-	 * TODO(b/179220036): check not overlapping requests;
-	 * not change cur_port if retimer scan is in progress
+	 * The order of requests from host are:
+	 *
+	 * Port 0 offline
+	 * Port 0 rescan retimers
+	 * Port 1 offline
+	 * Port 1 rescan retimers
+	 * ...
+	 * Port 0 online
+	 * Port 1 online
+	 * ...
 	 */
 	last_op = op;
 	cur_port = port;
 
+	/*
+	 * Host has requested to put this port back online, and haven't
+	 * finished online process. During this period, don't accept any
+	 * requests, except USB_RETIMER_FW_UPDATE_RESUME_PD.
+	 */
+	if (port_state[port] == RETIMER_ONLINE_REQUESTED) {
+		if (op != USB_RETIMER_FW_UPDATE_RESUME_PD) {
+			last_result = USB_RETIMER_FW_UPDATE_ERR;
+			return;
+		}
+	}
+
 	switch (op) {
 	case USB_RETIMER_FW_UPDATE_QUERY_PORT:
 		break;
@@ -253,9 +392,10 @@ static void restore_port(void)
 {
 	int port;
 
-	for  (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++) {
+	for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++) {
 		if (retimer_fw_update_get_port_state(port))
 			retimer_fw_update_port_handler(port, RESUME);
 	}
 }
 DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, restore_port, HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_CHIPSET_RESET, restore_port, HOOK_PRIO_DEFAULT);
diff --git a/common/usbc/usb_sm.c b/common/usbc/usb_sm.c
index 04b7193c0f..96b0b81e33 100644
--- a/common/usbc/usb_sm.c
+++ b/common/usbc/usb_sm.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,8 +12,8 @@
 #include "util.h"
 
 #ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USB, format, ##args)
 #else /* CONFIG_COMMON_RUNTIME */
 #define CPRINTF(format, args...)
 #define CPRINTS(format, args...)
@@ -23,8 +23,8 @@
 struct internal_ctx {
 	usb_state_ptr last_entered;
 	uint32_t running : 1;
-	uint32_t enter	 : 1;
-	uint32_t exit	 : 1;
+	uint32_t enter : 1;
+	uint32_t exit : 1;
 };
 BUILD_ASSERT(sizeof(struct internal_ctx) ==
 	     member_size(struct sm_ctx, internal));
@@ -65,9 +65,9 @@ static usb_state_ptr shared_parent_state(usb_state_ptr a, usb_state_ptr b)
  * functions.
  */
 static void call_entry_functions(const int port,
-			       struct internal_ctx *const internal,
-			       const usb_state_ptr stop,
-			       const usb_state_ptr current)
+				 struct internal_ctx *const internal,
+				 const usb_state_ptr stop,
+				 const usb_state_ptr current)
 {
 	if (current == stop)
 		return;
@@ -92,7 +92,7 @@ static void call_entry_functions(const int port,
  * during an exit function.
  */
 static void call_exit_functions(const int port, const usb_state_ptr stop,
-			      const usb_state_ptr current)
+				const usb_state_ptr current)
 {
 	if (current == stop)
 		return;
@@ -106,7 +106,7 @@ static void call_exit_functions(const int port, const usb_state_ptr stop,
 void set_state(const int port, struct sm_ctx *const ctx,
 	       const usb_state_ptr new_state)
 {
-	struct internal_ctx * const internal = (void *) ctx->internal;
+	struct internal_ctx *const internal = (void *)ctx->internal;
 	usb_state_ptr last_state;
 	usb_state_ptr shared_parent;
 
@@ -116,8 +116,8 @@ void set_state(const int port, struct sm_ctx *const ctx,
 	 * intended state to transition into.
 	 */
 	if (internal->exit) {
-		CPRINTF("C%d: Ignoring set state to 0x%pP within 0x%pP",
-			port, new_state, ctx->current);
+		CPRINTF("C%d: Ignoring set state to 0x%p within 0x%p", port,
+			new_state, ctx->current);
 		return;
 	}
 
@@ -176,8 +176,8 @@ void set_state(const int port, struct sm_ctx *const ctx,
  * functions.
  */
 static void call_run_functions(const int port,
-			     const struct internal_ctx *const internal,
-			     const usb_state_ptr current)
+			       const struct internal_ctx *const internal,
+			       const usb_state_ptr current)
 {
 	if (!current)
 		return;
@@ -194,7 +194,7 @@ static void call_run_functions(const int port,
 
 void run_state(const int port, struct sm_ctx *const ctx)
 {
-	struct internal_ctx * const internal = (void *) ctx->internal;
+	struct internal_ctx *const internal = (void *)ctx->internal;
 
 	internal->running = true;
 	call_run_functions(port, internal, ctx->current);
diff --git a/common/usbc/usb_tc_ctvpd_sm.c b/common/usbc/usb_tc_ctvpd_sm.c
index 46550978ed..045cca55c4 100644
--- a/common/usbc/usb_tc_ctvpd_sm.c
+++ b/common/usbc/usb_tc_ctvpd_sm.c
@@ -1,8 +1,9 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
 #include "system.h"
@@ -16,18 +17,18 @@
 /* USB Type-C CTVPD module */
 
 #ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 #else /* CONFIG_COMMON_RUNTIME */
 #define CPRINTF(format, args...)
 #define CPRINTS(format, args...)
 #endif
 
 /* Type-C Layer Flags */
-#define TC_FLAGS_VCONN_ON           BIT(0)
+#define TC_FLAGS_VCONN_ON BIT(0)
 
-#define SUPPORT_TIMER_RESET_INIT     0
-#define SUPPORT_TIMER_RESET_REQUEST  1
+#define SUPPORT_TIMER_RESET_INIT 0
+#define SUPPORT_TIMER_RESET_REQUEST 1
 #define SUPPORT_TIMER_RESET_COMPLETE 2
 
 /**
@@ -105,9 +106,8 @@ enum usb_tc_state {
 /* Forward declare the full list of states. This is indexed by usb_tc_state */
 static const struct usb_state tc_states[];
 
-
 /* List of human readable state names for console debugging */
-__maybe_unused const char * const tc_state_names[] = {
+__maybe_unused const char *const tc_state_names[] = {
 #ifdef CONFIG_COMMON_RUNTIME
 	[TC_DISABLED] = "Disabled",
 	[TC_UNATTACHED_SNK] = "Unattached.SNK",
@@ -257,9 +257,9 @@ test_mockable_static void print_current_state(const int port)
 int pd_is_connected(int port)
 {
 	return (get_state_tc(port) == TC_ATTACHED_SNK) ||
-			(get_state_tc(port) == TC_ATTACHED_SRC) ||
-			(get_state_tc(port) == TC_CT_ATTACHED_UNSUPPORTED) ||
-			(get_state_tc(port) == TC_CT_ATTACHED_VPD);
+	       (get_state_tc(port) == TC_ATTACHED_SRC) ||
+	       (get_state_tc(port) == TC_CT_ATTACHED_UNSUPPORTED) ||
+	       (get_state_tc(port) == TC_CT_ATTACHED_VPD);
 }
 
 bool pd_is_disconnected(int port)
@@ -398,7 +398,7 @@ static void tc_unattached_snk_run(const int port)
 	 *   2) VBUS is detected
 	 */
 	if (vpd_is_ct_vbus_present() &&
-				tc[port].cc_state == PD_CC_DFP_ATTACHED) {
+	    tc[port].cc_state == PD_CC_DFP_ATTACHED) {
 		set_state_tc(port, TC_UNATTACHED_SRC);
 		return;
 	}
@@ -436,11 +436,11 @@ static void tc_attach_wait_snk_run(const int port)
 	if (tc[port].host_cc_state != host_new_cc_state) {
 		tc[port].host_cc_state = host_new_cc_state;
 		if (host_new_cc_state == PD_CC_DFP_ATTACHED)
-			tc[port].host_cc_debounce = get_time().val +
-							PD_T_CC_DEBOUNCE;
+			tc[port].host_cc_debounce =
+				get_time().val + PD_T_CC_DEBOUNCE;
 		else
-			tc[port].host_cc_debounce = get_time().val +
-							PD_T_PD_DEBOUNCE;
+			tc[port].host_cc_debounce =
+				get_time().val + PD_T_PD_DEBOUNCE;
 		return;
 	}
 
@@ -458,7 +458,7 @@ static void tc_attach_wait_snk_run(const int port)
 	 * CC2 pins is SNK.Open for at least tPDDebounce.
 	 */
 	if (tc[port].host_cc_state == PD_CC_DFP_ATTACHED &&
-			(vpd_is_vconn_present() || vpd_is_host_vbus_present()))
+	    (vpd_is_vconn_present() || vpd_is_host_vbus_present()))
 		set_state_tc(port, TC_ATTACHED_SNK);
 	else if (tc[port].host_cc_state == PD_CC_NONE)
 		set_state_tc(port, TC_UNATTACHED_SNK);
@@ -551,7 +551,7 @@ static void tc_attached_snk_run(const int port)
 
 	/* Check the Support Timer */
 	if (get_time().val > tc[port].support_timer &&
-					!tc[port].billboard_presented) {
+	    !tc[port].billboard_presented) {
 		/*
 		 * Present USB Billboard Device Class interface
 		 * indicating that Charge-Through is not supported
@@ -654,7 +654,7 @@ static void tc_unattached_src_run(const int port)
 	 * if Charge-Through VBUS is removed.
 	 */
 	if (!vpd_is_ct_vbus_present() ||
-				get_time().val > tc[port].next_role_swap) {
+	    get_time().val > tc[port].next_role_swap) {
 		set_state_tc(port, TC_UNATTACHED_SNK);
 		return;
 	}
@@ -719,7 +719,7 @@ static void tc_attach_wait_src_run(const int port)
 	 * state is on the Host-side port’s CC pin for at least tCCDebounce.
 	 */
 	if (tc[port].host_cc_state == PD_CC_UFP_ATTACHED &&
-						!vpd_is_host_vbus_present()) {
+	    !vpd_is_host_vbus_present()) {
 		set_state_tc(port, TC_TRY_SNK);
 		return;
 	}
@@ -847,7 +847,7 @@ static void tc_try_snk_run(const int port)
 	 * for tTryCCDebounce.
 	 */
 	if (tc[port].host_cc_state == PD_CC_DFP_ATTACHED &&
-			(vpd_is_host_vbus_present() || vpd_is_vconn_present()))
+	    (vpd_is_host_vbus_present() || vpd_is_vconn_present()))
 		set_state_tc(port, TC_ATTACHED_SNK);
 	else if (tc[port].host_cc_state == PD_CC_NONE)
 		set_state_tc(port, TC_TRY_WAIT_SRC);
@@ -887,7 +887,7 @@ static void tc_try_wait_src_run(const int port)
 	if (tc[port].host_cc_state != host_new_cc_state) {
 		tc[port].host_cc_state = host_new_cc_state;
 		tc[port].host_cc_debounce =
-					get_time().val + PD_T_TRY_CC_DEBOUNCE;
+			get_time().val + PD_T_TRY_CC_DEBOUNCE;
 		return;
 	}
 
@@ -899,7 +899,7 @@ static void tc_try_wait_src_run(const int port)
 		 * at least tTryCCDebounce.
 		 */
 		if (tc[port].host_cc_state == PD_CC_UFP_ATTACHED &&
-						!vpd_is_host_vbus_present()) {
+		    !vpd_is_host_vbus_present()) {
 			set_state_tc(port, TC_ATTACHED_SRC);
 			return;
 		}
@@ -988,7 +988,7 @@ static void tc_ct_try_snk_run(const int port)
 		 * Charge-Through port.
 		 */
 		if (tc[port].cc_state == PD_CC_DFP_ATTACHED &&
-				vpd_is_ct_vbus_present()) {
+		    vpd_is_ct_vbus_present()) {
 			set_state_tc(port, TC_CT_ATTACHED_VPD);
 			return;
 		}
@@ -1001,8 +1001,7 @@ static void tc_ct_try_snk_run(const int port)
 		 * for tDRPTryWait.
 		 */
 		if (tc[port].cc_state == PD_CC_NONE) {
-			set_state_tc(port,
-					TC_CT_ATTACHED_UNSUPPORTED);
+			set_state_tc(port, TC_CT_ATTACHED_UNSUPPORTED);
 			return;
 		}
 	}
@@ -1181,8 +1180,7 @@ static void tc_ct_unattached_unsupported_run(const int port)
 	 * on both the CC1 and CC2 pins.
 	 */
 	if (cc_is_at_least_one_rd(cc1, cc2) || cc_is_audio_acc(cc1, cc2)) {
-		set_state_tc(port,
-				TC_CT_ATTACH_WAIT_UNSUPPORTED);
+		set_state_tc(port, TC_CT_ATTACH_WAIT_UNSUPPORTED);
 		return;
 	}
 
@@ -1343,7 +1341,7 @@ static void tc_ct_attached_vpd_entry(const int port)
 	 * pins is connected through the cable
 	 */
 	vpd_ct_get_cc(&cc1, &cc2);
-	tc[port].ct_cc  = cc_is_rp(cc2) ? CT_CC2 : CT_CC1;
+	tc[port].ct_cc = cc_is_rp(cc2) ? CT_CC2 : CT_CC1;
 
 	/*
 	 * 1. Remove or reduce any additional capacitance on the
@@ -1468,10 +1466,8 @@ static void tc_ct_attach_wait_vpd_run(const int port)
 	/* Debounce the cc state */
 	if (new_cc_state != tc[port].cc_state) {
 		tc[port].cc_state = new_cc_state;
-		tc[port].cc_debounce = get_time().val +
-						PD_T_CC_DEBOUNCE;
-		tc[port].pd_debounce = get_time().val +
-						PD_T_PD_DEBOUNCE;
+		tc[port].cc_debounce = get_time().val + PD_T_CC_DEBOUNCE;
+		tc[port].pd_debounce = get_time().val + PD_T_PD_DEBOUNCE;
 		return;
 	}
 
@@ -1482,7 +1478,7 @@ static void tc_ct_attach_wait_vpd_run(const int port)
 		 * port’s CC1 and CC2 pins are SNK.Open for at least
 		 * tPDDebounce.
 		 */
-		if (tc[port].cc_state  == PD_CC_NONE) {
+		if (tc[port].cc_state == PD_CC_NONE) {
 			set_state_tc(port, TC_CT_UNATTACHED_VPD);
 			return;
 		}
@@ -1496,8 +1492,8 @@ static void tc_ct_attach_wait_vpd_run(const int port)
 		 * least tCCDebounce and VBUS on the Charge-Through port is
 		 * detected.
 		 */
-		if (tc[port].cc_state  == PD_CC_DFP_ATTACHED &&
-						vpd_is_ct_vbus_present()) {
+		if (tc[port].cc_state == PD_CC_DFP_ATTACHED &&
+		    vpd_is_ct_vbus_present()) {
 			set_state_tc(port, TC_CT_ATTACHED_VPD);
 			return;
 		}
diff --git a/common/usbc/usb_tc_drp_acc_trysrc_sm.c b/common/usbc/usb_tc_drp_acc_trysrc_sm.c
index 2da6b59f0a..e68b0139db 100644
--- a/common/usbc/usb_tc_drp_acc_trysrc_sm.c
+++ b/common/usbc/usb_tc_drp_acc_trysrc_sm.c
@@ -1,8 +1,9 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "builtin/assert.h"
 #include "charge_manager.h"
 #include "charge_state.h"
 #include "common.h"
@@ -32,30 +33,30 @@
  *   See Figure 4-16 in Release 1.4 of USB Type-C Spec.
  */
 #ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 #else /* CONFIG_COMMON_RUNTIME */
 #define CPRINTF(format, args...)
 #define CPRINTS(format, args...)
 #endif
 
-#define CPRINTF_LX(x, format, args...) \
-	do { \
-		if (tc_debug_level >= x) \
-			CPRINTF(format, ## args); \
+#define CPRINTF_LX(x, format, args...)           \
+	do {                                     \
+		if (tc_debug_level >= x)         \
+			CPRINTF(format, ##args); \
 	} while (0)
-#define CPRINTF_L1(format, args...) CPRINTF_LX(1, format, ## args)
-#define CPRINTF_L2(format, args...) CPRINTF_LX(2, format, ## args)
-#define CPRINTF_L3(format, args...) CPRINTF_LX(3, format, ## args)
-
-#define CPRINTS_LX(x, format, args...) \
-	do { \
-		if (tc_debug_level >= x) \
-			CPRINTS(format, ## args); \
+#define CPRINTF_L1(format, args...) CPRINTF_LX(1, format, ##args)
+#define CPRINTF_L2(format, args...) CPRINTF_LX(2, format, ##args)
+#define CPRINTF_L3(format, args...) CPRINTF_LX(3, format, ##args)
+
+#define CPRINTS_LX(x, format, args...)           \
+	do {                                     \
+		if (tc_debug_level >= x)         \
+			CPRINTS(format, ##args); \
 	} while (0)
-#define CPRINTS_L1(format, args...) CPRINTS_LX(1, format, ## args)
-#define CPRINTS_L2(format, args...) CPRINTS_LX(2, format, ## args)
-#define CPRINTS_L3(format, args...) CPRINTS_LX(3, format, ## args)
+#define CPRINTS_L1(format, args...) CPRINTS_LX(1, format, ##args)
+#define CPRINTS_L2(format, args...) CPRINTS_LX(2, format, ##args)
+#define CPRINTS_L3(format, args...) CPRINTS_LX(3, format, ##args)
 
 /*
  * Define DEBUG_PRINT_FLAG_AND_EVENT_NAMES to print flag names when set and
@@ -83,57 +84,58 @@ void print_flag(int port, int set_or_clear, int flag);
 
 /* Type-C Layer Flags */
 /* Flag to note we are sourcing VCONN */
-#define TC_FLAGS_VCONN_ON               BIT(0)
+#define TC_FLAGS_VCONN_ON BIT(0)
 /* Flag to note port partner has Rp/Rp or Rd/Rd */
-#define TC_FLAGS_TS_DTS_PARTNER         BIT(1)
+#define TC_FLAGS_TS_DTS_PARTNER BIT(1)
 /* Flag to note VBus input has never been low */
-#define TC_FLAGS_VBUS_NEVER_LOW         BIT(2)
+#define TC_FLAGS_VBUS_NEVER_LOW BIT(2)
 /* Flag to note Low Power Mode transition is currently happening */
-#define TC_FLAGS_LPM_TRANSITION         BIT(3)
+#define TC_FLAGS_LPM_TRANSITION BIT(3)
 /* Flag to note Low Power Mode is currently on */
-#define TC_FLAGS_LPM_ENGAGED            BIT(4)
+#define TC_FLAGS_LPM_ENGAGED BIT(4)
 /* Flag to note CVTPD has been detected */
-#define TC_FLAGS_CTVPD_DETECTED         BIT(5)
+#define TC_FLAGS_CTVPD_DETECTED BIT(5)
 /* Flag to note request to swap to VCONN on */
-#define TC_FLAGS_REQUEST_VC_SWAP_ON     BIT(6)
+#define TC_FLAGS_REQUEST_VC_SWAP_ON BIT(6)
 /* Flag to note request to swap to VCONN off */
-#define TC_FLAGS_REQUEST_VC_SWAP_OFF    BIT(7)
+#define TC_FLAGS_REQUEST_VC_SWAP_OFF BIT(7)
 /* Flag to note request to swap VCONN is being rejected */
-#define TC_FLAGS_REJECT_VCONN_SWAP      BIT(8)
+#define TC_FLAGS_REJECT_VCONN_SWAP BIT(8)
 /* Flag to note request to power role swap */
-#define TC_FLAGS_REQUEST_PR_SWAP        BIT(9)
+#define TC_FLAGS_REQUEST_PR_SWAP BIT(9)
 /* Flag to note request to data role swap */
-#define TC_FLAGS_REQUEST_DR_SWAP        BIT(10)
+#define TC_FLAGS_REQUEST_DR_SWAP BIT(10)
 /* Flag to note request to power off sink */
-#define TC_FLAGS_POWER_OFF_SNK          BIT(11)
+#define TC_FLAGS_POWER_OFF_SNK BIT(11)
 /* Flag to note port partner is Power Delivery capable */
-#define TC_FLAGS_PARTNER_PD_CAPABLE     BIT(12)
+#define TC_FLAGS_PARTNER_PD_CAPABLE BIT(12)
 /* Flag to note hard reset has been requested */
-#define TC_FLAGS_HARD_RESET_REQUESTED   BIT(13)
+#define TC_FLAGS_HARD_RESET_REQUESTED BIT(13)
 /* Flag to note we are currently performing PR Swap */
-#define TC_FLAGS_PR_SWAP_IN_PROGRESS    BIT(14)
+#define TC_FLAGS_PR_SWAP_IN_PROGRESS BIT(14)
 /* Flag to note we should check for connection */
-#define TC_FLAGS_CHECK_CONNECTION       BIT(15)
+#define TC_FLAGS_CHECK_CONNECTION BIT(15)
 /* Flag to note request from pd_set_suspend to enter TC_DISABLED state */
-#define TC_FLAGS_REQUEST_SUSPEND        BIT(16)
+#define TC_FLAGS_REQUEST_SUSPEND BIT(16)
 /* Flag to note we are in TC_DISABLED state */
-#define TC_FLAGS_SUSPENDED              BIT(17)
+#define TC_FLAGS_SUSPENDED BIT(17)
 /* Flag to indicate the port current limit has changed */
-#define TC_FLAGS_UPDATE_CURRENT		BIT(18)
+#define TC_FLAGS_UPDATE_CURRENT BIT(18)
 /* Flag to indicate USB mux should be updated */
-#define TC_FLAGS_UPDATE_USB_MUX		BIT(19)
+#define TC_FLAGS_UPDATE_USB_MUX BIT(19)
 /* Flag for retimer firmware update */
-#define TC_FLAGS_USB_RETIMER_FW_UPDATE_RUN     BIT(20)
+#define TC_FLAGS_USB_RETIMER_FW_UPDATE_RUN BIT(20)
 #define TC_FLAGS_USB_RETIMER_FW_UPDATE_LTD_RUN BIT(21)
 /* Flag for asynchronous call to request Error Recovery */
-#define TC_FLAGS_REQUEST_ERROR_RECOVERY	BIT(22)
+#define TC_FLAGS_REQUEST_ERROR_RECOVERY BIT(22)
 
 /* For checking flag_bit_names[] array */
-#define TC_FLAGS_COUNT			23
+#define TC_FLAGS_COUNT 23
 
 /* On disconnect, clear most of the flags. */
-#define CLR_FLAGS_ON_DISCONNECT(port) TC_CLR_FLAG(port, \
-	~(TC_FLAGS_LPM_ENGAGED | TC_FLAGS_REQUEST_SUSPEND | TC_FLAGS_SUSPENDED))
+#define CLR_FLAGS_ON_DISCONNECT(port)                                         \
+	TC_CLR_FLAG(port, ~(TC_FLAGS_LPM_ENGAGED | TC_FLAGS_REQUEST_SUSPEND | \
+			    TC_FLAGS_SUSPENDED))
 
 /*
  * 10 ms is enough time for any TCPC transaction to complete
@@ -166,14 +168,14 @@ void print_flag(int port, int set_or_clear, int flag);
  * The TypeC state machine uses this bit to disable/enable PD
  * This bit corresponds to bit-0 of pd_disabled_mask
  */
-#define PD_DISABLED_NO_CONNECTION  BIT(0)
+#define PD_DISABLED_NO_CONNECTION BIT(0)
 /*
  * Console and Host commands use this bit to override the
  * PD_DISABLED_NO_CONNECTION bit that was set by the TypeC
  * state machine.
  * This bit corresponds to bit-1 of pd_disabled_mask
  */
-#define PD_DISABLED_BY_POLICY       BIT(1)
+#define PD_DISABLED_BY_POLICY BIT(1)
 
 /* Unreachable time in future */
 #define TIMER_DISABLED 0xffffffffffffffff
@@ -250,9 +252,8 @@ extern int _GPIO_CCD_MODE_ODL;
  * If we can't print or the CONFIG_USB_PD_DEBUG_LEVEL is defined to be 0
  * then the DEBUG LABELS will be removed from the build.
  */
-#if defined(CONFIG_COMMON_RUNTIME) && \
-	(!defined(CONFIG_USB_PD_DEBUG_LEVEL) || \
-	 (CONFIG_USB_PD_DEBUG_LEVEL > 0))
+#if defined(CONFIG_COMMON_RUNTIME) && (!defined(CONFIG_USB_PD_DEBUG_LEVEL) || \
+				       (CONFIG_USB_PD_DEBUG_LEVEL > 0))
 #define USB_PD_DEBUG_LABELS
 #endif
 
@@ -268,9 +269,8 @@ extern int _GPIO_CCD_MODE_ODL;
  */
 #define IS_ATTACHED_SNK(port) (get_state_tc(port) == TC_ATTACHED_SNK)
 
-
 /* List of human readable state names for console debugging */
-__maybe_unused static __const_data const char * const tc_state_names[] = {
+__maybe_unused static __const_data const char *const tc_state_names[] = {
 #ifdef USB_PD_DEBUG_LABELS
 	[TC_DISABLED] = "Disabled",
 	[TC_ERROR_RECOVERY] = "ErrorRecovery",
@@ -289,7 +289,7 @@ __maybe_unused static __const_data const char * const tc_state_names[] = {
 	[TC_LOW_POWER_MODE] = "LowPowerMode",
 #endif
 #ifdef CONFIG_USB_PE_SM
-	[TC_CT_UNATTACHED_SNK] =  "CTUnattached.SNK",
+	[TC_CT_UNATTACHED_SNK] = "CTUnattached.SNK",
 	[TC_CT_ATTACHED_SNK] = "CTAttached.SNK",
 #endif
 	/* Super States */
@@ -304,14 +304,16 @@ __maybe_unused static __const_data const char * const tc_state_names[] = {
 /* Debug log level - higher number == more log */
 #ifdef CONFIG_USB_PD_DEBUG_LEVEL
 static const enum debug_level tc_debug_level = CONFIG_USB_PD_DEBUG_LEVEL;
+#elif defined(CONFIG_USB_PD_INITIAL_DEBUG_LEVEL)
+static enum debug_level tc_debug_level = CONFIG_USB_PD_INITIAL_DEBUG_LEVEL;
 #else
 static enum debug_level tc_debug_level = DEBUG_LEVEL_1;
 #endif
 
 #ifdef DEBUG_PRINT_FLAG_AND_EVENT_NAMES
 struct bit_name {
-	int		value;
-	const char	*name;
+	int value;
+	const char *name;
 };
 
 static struct bit_name flag_bit_names[] = {
@@ -335,11 +337,10 @@ static struct bit_name flag_bit_names[] = {
 	{ TC_FLAGS_SUSPENDED, "SUSPENDED" },
 	{ TC_FLAGS_UPDATE_CURRENT, "UPDATE_CURRENT" },
 	{ TC_FLAGS_UPDATE_USB_MUX, "UPDATE_USB_MUX" },
-	{ TC_FLAGS_USB_RETIMER_FW_UPDATE_RUN,
-			"USB_RETIMER_FW_UPDATE_RUN" },
+	{ TC_FLAGS_USB_RETIMER_FW_UPDATE_RUN, "USB_RETIMER_FW_UPDATE_RUN" },
 	{ TC_FLAGS_USB_RETIMER_FW_UPDATE_LTD_RUN,
-			"USB_RETIMER_FW_UPDATE_LTD_RUN" },
-	{ TC_FLAGS_REQUEST_ERROR_RECOVERY, "REQUEST_ERROR_RECOCVERY"},
+	  "USB_RETIMER_FW_UPDATE_LTD_RUN" },
+	{ TC_FLAGS_REQUEST_ERROR_RECOVERY, "REQUEST_ERROR_RECOCVERY" },
 };
 BUILD_ASSERT(ARRAY_SIZE(flag_bit_names) == TC_FLAGS_COUNT);
 
@@ -394,8 +395,8 @@ void print_flag(int port, int set_or_clear, int flag)
 #ifndef CONFIG_USB_PD_TRY_SRC
 extern int TC_TRY_SRC_UNDEFINED;
 extern int TC_TRY_WAIT_SNK_UNDEFINED;
-#define TC_TRY_SRC	TC_TRY_SRC_UNDEFINED
-#define TC_TRY_WAIT_SNK	TC_TRY_WAIT_SNK_UNDEFINED
+#define TC_TRY_SRC TC_TRY_SRC_UNDEFINED
+#define TC_TRY_WAIT_SNK TC_TRY_WAIT_SNK_UNDEFINED
 #endif
 
 static struct type_c {
@@ -444,10 +445,11 @@ static struct type_c {
 } tc[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 /* Port dual-role state */
-static volatile __maybe_unused
-enum pd_dual_role_states drp_state[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[0 ... (CONFIG_USB_PD_PORT_MAX_COUNT - 1)] =
-		CONFIG_USB_PD_INITIAL_DRP_STATE};
+static volatile __maybe_unused enum pd_dual_role_states
+	drp_state[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+		[0 ...(CONFIG_USB_PD_PORT_MAX_COUNT - 1)] =
+			CONFIG_USB_PD_INITIAL_DRP_STATE
+	};
 
 static void set_vconn(int port, int enable);
 
@@ -516,7 +518,7 @@ __overridable void pd_set_vbus_discharge(int port, int enable)
 /*
  * These pd_ functions are implemented in the PE layer
  */
-const uint32_t * const pd_get_src_caps(int port)
+const uint32_t *const pd_get_src_caps(int port)
 {
 	return NULL;
 }
@@ -526,7 +528,7 @@ uint8_t pd_get_src_cap_cnt(int port)
 	return 0;
 }
 
-const uint32_t * const pd_get_snk_caps(int port)
+const uint32_t *const pd_get_snk_caps(int port)
 {
 	return NULL;
 }
@@ -718,7 +720,7 @@ __maybe_unused static void tc_enable_try_src(int en)
 static void tc_set_modes_exit(int port)
 {
 	if (IS_ENABLED(CONFIG_USB_PE_SM) &&
-			IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP)) {
+	    IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP)) {
 		pd_dfp_exit_mode(port, TCPCI_MSG_SOP, 0, 0);
 		pd_dfp_exit_mode(port, TCPCI_MSG_SOP_PRIME, 0, 0);
 		pd_dfp_exit_mode(port, TCPCI_MSG_SOP_PRIME_PRIME, 0, 0);
@@ -738,12 +740,13 @@ static void tc_detached(int port)
 
 	/* Clear any mux connection on detach */
 	if (IS_ENABLED(CONFIG_USBC_SS_MUX))
-		usb_mux_set(port, USB_PD_MUX_NONE,
-			    USB_SWITCH_DISCONNECT, tc[port].polarity);
+		usb_mux_set(port, USB_PD_MUX_NONE, USB_SWITCH_DISCONNECT,
+			    tc[port].polarity);
 }
 
 static inline void pd_set_dual_role_and_event(int port,
-				enum pd_dual_role_states state, uint32_t event)
+					      enum pd_dual_role_states state,
+					      uint32_t event)
 {
 	drp_state[port] = state;
 
@@ -1072,8 +1075,8 @@ static void tc_set_partner_role(int port, enum ppc_device_role role,
  * to run.  So build in 1ms delays, for up to 300ms, to wait for
  * the suspend to actually happen.
  */
-#define SUSPEND_SLEEP_DELAY	1
-#define SUSPEND_SLEEP_RETRIES	300
+#define SUSPEND_SLEEP_DELAY 1
+#define SUSPEND_SLEEP_RETRIES 300
 
 void pd_set_suspend(int port, int suspend)
 {
@@ -1098,8 +1101,8 @@ void pd_set_suspend(int port, int suspend)
 		/* Sleep this task if we are not suspended */
 		while (pd_is_port_enabled(port)) {
 			if (++wait > SUSPEND_SLEEP_RETRIES) {
-				CPRINTS("C%d: NOT SUSPENDED after %dms",
-					port, wait * SUSPEND_SLEEP_DELAY);
+				CPRINTS("C%d: NOT SUSPENDED after %dms", port,
+					wait * SUSPEND_SLEEP_DELAY);
 				return;
 			}
 			msleep(SUSPEND_SLEEP_DELAY);
@@ -1177,8 +1180,8 @@ int pd_is_connected(int port)
 {
 	return (IS_ATTACHED_SRC(port) ||
 		(IS_ENABLED(CONFIG_USB_PE_SM) &&
-		((get_state_tc(port) == TC_CT_UNATTACHED_SNK) ||
-		(get_state_tc(port) == TC_CT_ATTACHED_SNK))) ||
+		 ((get_state_tc(port) == TC_CT_UNATTACHED_SNK) ||
+		  (get_state_tc(port) == TC_CT_ATTACHED_SNK))) ||
 		IS_ATTACHED_SNK(port));
 }
 
@@ -1235,7 +1238,7 @@ bool pd_get_partner_unconstr_power(int port)
 }
 
 static void bc12_role_change_handler(int port, enum pd_data_role prev_data_role,
-	enum pd_data_role data_role)
+				     enum pd_data_role data_role)
 {
 	int event = 0;
 	bool role_changed = (data_role != prev_data_role);
@@ -1290,8 +1293,7 @@ void typec_select_src_collision_rp(int port, enum tcpc_rp_value rp)
 static enum tcpc_rp_value typec_get_active_select_rp(int port)
 {
 	/* Explicit contract will use the collision Rp */
-	if (IS_ENABLED(CONFIG_USB_PD_REV30) &&
-	    pe_is_explicit_contract(port))
+	if (IS_ENABLED(CONFIG_USB_PD_REV30) && pe_is_explicit_contract(port))
 		return tc[port].select_collision_rp;
 	return tc[port].select_current_limit_rp;
 }
@@ -1412,7 +1414,7 @@ static bool tc_perform_snk_hard_reset(int port)
 			tc[port].ps_reset_state = PS_STATE2;
 			pd_timer_enable(port, TC_TIMER_TIMEOUT,
 					PD_T_SRC_RECOVER_MAX +
-					PD_T_SRC_TURN_ON);
+						PD_T_SRC_TURN_ON);
 		}
 
 		if (pd_timer_is_expired(port, TC_TIMER_TIMEOUT)) {
@@ -1423,7 +1425,7 @@ static bool tc_perform_snk_hard_reset(int port)
 			tc[port].ps_reset_state = PS_STATE2;
 			pd_timer_enable(port, TC_TIMER_TIMEOUT,
 					PD_T_SRC_RECOVER_MAX +
-					PD_T_SRC_TURN_ON);
+						PD_T_SRC_TURN_ON);
 		}
 		return false;
 	case PS_STATE2:
@@ -1497,8 +1499,8 @@ static void restart_tc_sm(int port, enum usb_tc_state start_state)
 	 * Update the Rp Value. We don't need to update CC lines though as that
 	 * happens in below set_state transition.
 	 */
-	typec_select_src_current_limit_rp(port,
-		typec_get_default_current_limit_rp(port));
+	typec_select_src_current_limit_rp(
+		port, typec_get_default_current_limit_rp(port));
 
 	/* Disable if restart failed, otherwise start in default state. */
 	set_state_tc(port, res ? TC_DISABLED : start_state);
@@ -1567,7 +1569,6 @@ void tc_state_init(int port)
 		return;
 	}
 
-
 	/* Allow system to set try src enable */
 	if (IS_ENABLED(CONFIG_USB_PD_TRY_SRC))
 		tc_try_src_override(TRY_SRC_NO_OVERRIDE);
@@ -1582,11 +1583,13 @@ void tc_state_init(int port)
 	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
 		pd_set_dual_role_and_event(port, PD_DRP_FORCE_SINK, 0);
 	else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND))
-		pd_set_dual_role_and_event(port, pd_get_drp_state_in_suspend(), 0);
+		pd_set_dual_role_and_event(port, pd_get_drp_state_in_suspend(),
+					   0);
 	else /* CHIPSET_STATE_ON */
 		pd_set_dual_role_and_event(port, pd_get_drp_state_in_s0(), 0);
 #else
-	pd_set_dual_role_and_event(port, board_tc_get_initial_drp_mode(port), 0);
+	pd_set_dual_role_and_event(port, board_tc_get_initial_drp_mode(port),
+				   0);
 #endif
 
 	/*
@@ -1771,8 +1774,7 @@ void tc_event_check(int port, int evt)
 		 * Notify all ports of sysjump
 		 */
 		if (evt & PD_EVENT_SYSJUMP) {
-			for (i = 0; i <
-				CONFIG_USB_PD_PORT_MAX_COUNT; i++)
+			for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
 				dpm_set_mode_exit_request(i);
 			notify_sysjump_ready();
 		}
@@ -1834,8 +1836,8 @@ static void sink_stop_drawing_current(int port)
 
 	if (IS_ENABLED(CONFIG_CHARGE_MANAGER)) {
 		typec_set_input_current_limit(port, 0, 0);
-		charge_manager_set_ceil(port,
-				CEIL_REQUESTOR_PD, CHARGE_CEIL_NONE);
+		charge_manager_set_ceil(port, CEIL_REQUESTOR_PD,
+					CHARGE_CEIL_NONE);
 	}
 }
 
@@ -1861,9 +1863,9 @@ static void set_vconn(int port, int enable)
 static void pd_update_dual_role_config(int port)
 {
 	if (tc[port].power_role == PD_ROLE_SOURCE &&
-			(drp_state[port] == PD_DRP_FORCE_SINK ||
-			(drp_state[port] == PD_DRP_TOGGLE_OFF &&
-			get_state_tc(port) == TC_UNATTACHED_SRC))) {
+	    (drp_state[port] == PD_DRP_FORCE_SINK ||
+	     (drp_state[port] == PD_DRP_TOGGLE_OFF &&
+	      get_state_tc(port) == TC_UNATTACHED_SRC))) {
 		/*
 		 * Change to sink if port is currently a source AND (new DRP
 		 * state is force sink OR new DRP state is toggle off and we are
@@ -1871,7 +1873,7 @@ static void pd_update_dual_role_config(int port)
 		 */
 		set_state_tc(port, TC_UNATTACHED_SNK);
 	} else if (tc[port].power_role == PD_ROLE_SINK &&
-			drp_state[port] == PD_DRP_FORCE_SOURCE) {
+		   drp_state[port] == PD_DRP_FORCE_SOURCE) {
 		/*
 		 * Change to source if port is currently a sink and the
 		 * new DRP state is force source.
@@ -1885,10 +1887,9 @@ __maybe_unused static void handle_new_power_state(int port)
 	if (!IS_ENABLED(CONFIG_POWER_COMMON))
 		assert(0);
 
-	if (IS_ENABLED(CONFIG_POWER_COMMON) &&
-	    IS_ENABLED(CONFIG_USB_PE_SM)) {
+	if (IS_ENABLED(CONFIG_POWER_COMMON) && IS_ENABLED(CONFIG_USB_PE_SM)) {
 		if (chipset_in_or_transitioning_to_state(
-					CHIPSET_STATE_ANY_OFF)) {
+			    CHIPSET_STATE_ANY_OFF)) {
 			/*
 			 * The SoC will negotiate alternate mode again when it
 			 * boots up
@@ -1905,8 +1906,7 @@ __maybe_unused static void handle_new_power_state(int port)
 	 */
 	if (IS_ENABLED(CONFIG_USB_PE_SM)) {
 		if (tc_is_vconn_src(port) && tc_is_attached_snk(port) &&
-						!pd_check_vconn_swap(port) &&
-						pd_is_battery_capable())
+		    !pd_check_vconn_swap(port) && pd_is_battery_capable())
 			pd_dpm_request(port, DPM_REQUEST_HARD_RESET_SEND);
 	}
 
@@ -1928,7 +1928,7 @@ __maybe_unused static void handle_new_power_state(int port)
 void pd_request_vconn_swap_off(int port)
 {
 	if (get_state_tc(port) == TC_ATTACHED_SRC ||
-			get_state_tc(port) == TC_ATTACHED_SNK) {
+	    get_state_tc(port) == TC_ATTACHED_SNK) {
 		TC_SET_FLAG(port, TC_FLAGS_REQUEST_VC_SWAP_OFF);
 		task_wake(PD_PORT_TO_TASK_ID(port));
 	}
@@ -1937,7 +1937,7 @@ void pd_request_vconn_swap_off(int port)
 void pd_request_vconn_swap_on(int port)
 {
 	if (get_state_tc(port) == TC_ATTACHED_SRC ||
-			get_state_tc(port) == TC_ATTACHED_SNK) {
+	    get_state_tc(port) == TC_ATTACHED_SNK) {
 		TC_SET_FLAG(port, TC_FLAGS_REQUEST_VC_SWAP_ON);
 		task_wake(PD_PORT_TO_TASK_ID(port));
 	}
@@ -2090,14 +2090,13 @@ static void sink_power_sub_states(int port)
 			tc[port].typec_curr = usb_get_typec_current_limit(
 				tc[port].polarity, cc1, cc2);
 
-			typec_set_input_current_limit(port,
-				tc[port].typec_curr, TYPE_C_VOLTAGE);
+			typec_set_input_current_limit(port, tc[port].typec_curr,
+						      TYPE_C_VOLTAGE);
 			charge_manager_update_dualrole(port, CAP_DEDICATED);
 		}
 	}
 }
 
-
 /*
  * TYPE-C State Implementations
  */
@@ -2117,6 +2116,7 @@ static void tc_disabled_entry(const int port)
 	 * to indicate to pd_is_port_enabled that we are now suspended.
 	 */
 	TC_SET_FLAG(port, TC_FLAGS_SUSPENDED);
+	tcpm_release(port);
 }
 
 static void tc_disabled_run(const int port)
@@ -2124,13 +2124,16 @@ static void tc_disabled_run(const int port)
 	/* If pd_set_suspend clears the request, go to TC_UNATTACHED_SNK/SRC. */
 	if (!TC_CHK_FLAG(port, TC_FLAGS_REQUEST_SUSPEND)) {
 		set_state_tc(port, drp_state[port] == PD_DRP_FORCE_SOURCE ?
-			     TC_UNATTACHED_SRC : TC_UNATTACHED_SNK);
+					   TC_UNATTACHED_SRC :
+					   TC_UNATTACHED_SNK);
 	} else {
 		if (IS_ENABLED(CONFIG_USBC_RETIMER_FW_UPDATE)) {
-			if (TC_CHK_FLAG(port,
-				TC_FLAGS_USB_RETIMER_FW_UPDATE_LTD_RUN)) {
-				TC_CLR_FLAG(port,
-				TC_FLAGS_USB_RETIMER_FW_UPDATE_LTD_RUN);
+			if (TC_CHK_FLAG(
+				    port,
+				    TC_FLAGS_USB_RETIMER_FW_UPDATE_LTD_RUN)) {
+				TC_CLR_FLAG(
+					port,
+					TC_FLAGS_USB_RETIMER_FW_UPDATE_LTD_RUN);
 				usb_retimer_fw_update_process_op_cb(port);
 			}
 		}
@@ -2179,7 +2182,8 @@ static void tc_error_recovery_run(const int port)
 	 */
 	if (tc[port].ctx.previous == NULL) {
 		set_state_tc(port, drp_state[port] == PD_DRP_FORCE_SOURCE ?
-			     TC_UNATTACHED_SRC : TC_UNATTACHED_SNK);
+					   TC_UNATTACHED_SRC :
+					   TC_UNATTACHED_SNK);
 		return;
 	}
 
@@ -2230,11 +2234,10 @@ static void tc_unattached_snk_entry(const int port)
 	 */
 	tcpm_debug_detach(port);
 	typec_select_pull(port, TYPEC_CC_RD);
-	typec_select_src_current_limit_rp(port,
-		typec_get_default_current_limit_rp(port));
+	typec_select_src_current_limit_rp(
+		port, typec_get_default_current_limit_rp(port));
 	typec_update_cc(port);
 
-
 	prev_data_role = tc[port].data_role;
 	tc[port].data_role = PD_ROLE_DISCONNECTED;
 	/*
@@ -2256,10 +2259,11 @@ static void tc_unattached_snk_entry(const int port)
 	pd_execute_data_swap(port, PD_ROLE_DISCONNECTED);
 	pd_timer_enable(port, TC_TIMER_NEXT_ROLE_SWAP, PD_T_DRP_SNK);
 
-	if (IS_ENABLED(CONFIG_USB_PE_SM)) {
-		CLR_FLAGS_ON_DISCONNECT(port);
-		tc_enable_pd(port, 0);
-	}
+#ifdef CONFIG_USB_PE_SM
+	CLR_FLAGS_ON_DISCONNECT(port);
+	tc_enable_pd(port, 0);
+	tc[port].ps_reset_state = PS_STATE0;
+#endif
 }
 
 static void tc_unattached_snk_run(const int port)
@@ -2383,9 +2387,9 @@ static void tc_attach_wait_snk_run(const int port)
 	if (new_cc_state == PD_CC_NONE &&
 	    pd_timer_is_expired(port, TC_TIMER_PD_DEBOUNCE)) {
 		/* We are detached */
-		if (drp_state[port] == PD_DRP_TOGGLE_OFF
-		    || drp_state[port] == PD_DRP_FREEZE
-		    || drp_state[port] == PD_DRP_FORCE_SINK)
+		if (drp_state[port] == PD_DRP_TOGGLE_OFF ||
+		    drp_state[port] == PD_DRP_FREEZE ||
+		    drp_state[port] == PD_DRP_FORCE_SINK)
 			set_state_tc(port, TC_UNATTACHED_SNK);
 		else
 			set_state_tc(port, TC_UNATTACHED_SRC);
@@ -2425,9 +2429,9 @@ static void tc_attach_wait_snk_run(const int port)
 		}
 
 		if (IS_ENABLED(CONFIG_USB_PE_SM) &&
-				IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP)) {
+		    IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP)) {
 			hook_call_deferred(&pd_usb_billboard_deferred_data,
-								PD_T_AME);
+					   PD_T_AME);
 		}
 	}
 }
@@ -2471,7 +2475,7 @@ static void tc_attached_snk_entry(const int port)
 		/* Change role to sink */
 		tc_set_power_role(port, PD_ROLE_SINK);
 		tcpm_set_msg_header(port, tc[port].power_role,
-							tc[port].data_role);
+				    tc[port].data_role);
 
 		/*
 		 * Maintain VCONN supply state, whether ON or OFF, and its
@@ -2490,11 +2494,10 @@ static void tc_attached_snk_entry(const int port)
 		hook_notify(HOOK_USB_PD_CONNECT);
 
 		if (IS_ENABLED(CONFIG_CHARGE_MANAGER)) {
-			tc[port].typec_curr =
-			usb_get_typec_current_limit(tc[port].polarity,
-								cc1, cc2);
-			typec_set_input_current_limit(port,
-					tc[port].typec_curr, TYPE_C_VOLTAGE);
+			tc[port].typec_curr = usb_get_typec_current_limit(
+				tc[port].polarity, cc1, cc2);
+			typec_set_input_current_limit(port, tc[port].typec_curr,
+						      TYPE_C_VOLTAGE);
 			/*
 			 * Start new connections as dedicated until source caps
 			 * are received, at which point the PE will update the
@@ -2550,8 +2553,8 @@ static bool tc_snk_check_vbus_removed(const int port)
 						 TC_TIMER_VBUS_DEBOUNCE)) {
 				pd_timer_enable(port, TC_TIMER_VBUS_DEBOUNCE,
 						PD_T_FRS_VBUS_DEBOUNCE);
-			} else if (pd_timer_is_expired(port,
-						TC_TIMER_VBUS_DEBOUNCE)) {
+			} else if (pd_timer_is_expired(
+					   port, TC_TIMER_VBUS_DEBOUNCE)) {
 				set_state_tc(port, TC_UNATTACHED_SNK);
 				return true;
 			}
@@ -2658,8 +2661,9 @@ static void tc_attached_snk_run(const int port)
 
 			/* Perform Data Role Swap */
 			tc_set_data_role(port,
-				tc[port].data_role == PD_ROLE_UFP ?
-					PD_ROLE_DFP : PD_ROLE_UFP);
+					 tc[port].data_role == PD_ROLE_UFP ?
+						 PD_ROLE_DFP :
+						 PD_ROLE_UFP);
 		}
 
 		/*
@@ -2787,8 +2791,8 @@ static void tc_unattached_src_entry(const int port)
 	 */
 	tcpm_debug_detach(port);
 	typec_select_pull(port, TYPEC_CC_RP);
-	typec_select_src_current_limit_rp(port,
-		typec_get_default_current_limit_rp(port));
+	typec_select_src_current_limit_rp(
+		port, typec_get_default_current_limit_rp(port));
 	typec_update_cc(port);
 
 	prev_data_role = tc[port].data_role;
@@ -2806,10 +2810,11 @@ static void tc_unattached_src_entry(const int port)
 	if (IS_ENABLED(CONFIG_CHARGE_MANAGER))
 		charge_manager_update_dualrole(port, CAP_UNKNOWN);
 
-	if (IS_ENABLED(CONFIG_USB_PE_SM)) {
-		CLR_FLAGS_ON_DISCONNECT(port);
-		tc_enable_pd(port, 0);
-	}
+#ifdef CONFIG_USB_PE_SM
+	CLR_FLAGS_ON_DISCONNECT(port);
+	tc_enable_pd(port, 0);
+	tc[port].ps_reset_state = PS_STATE0;
+#endif
 
 	pd_timer_enable(port, TC_TIMER_NEXT_ROLE_SWAP, PD_T_DRP_SRC);
 }
@@ -2983,9 +2988,8 @@ static void tc_attached_src_entry(const int port)
 		if (TC_CHK_FLAG(port, TC_FLAGS_PR_SWAP_IN_PROGRESS)) {
 			/* Change role to source */
 			tc_set_power_role(port, PD_ROLE_SOURCE);
-			tcpm_set_msg_header(port,
-					tc[port].power_role,
-					tc[port].data_role);
+			tcpm_set_msg_header(port, tc[port].power_role,
+					    tc[port].data_role);
 
 			/* Enable VBUS */
 			tc_src_power_on(port);
@@ -3040,10 +3044,9 @@ static void tc_attached_src_entry(const int port)
 					set_vconn(port, 0);
 
 				if (IS_ENABLED(CONFIG_USBC_SS_MUX))
-					usb_mux_set(port,
-						USB_PD_MUX_NONE,
-						USB_SWITCH_DISCONNECT,
-						tc[port].polarity);
+					usb_mux_set(port, USB_PD_MUX_NONE,
+						    USB_SWITCH_DISCONNECT,
+						    tc[port].polarity);
 			}
 
 			tc_enable_pd(port, 0);
@@ -3093,7 +3096,8 @@ static void tc_attached_src_entry(const int port)
 
 			if (IS_ENABLED(CONFIG_USBC_SS_MUX))
 				usb_mux_set(port, USB_PD_MUX_NONE,
-				USB_SWITCH_DISCONNECT, tc[port].polarity);
+					    USB_SWITCH_DISCONNECT,
+					    tc[port].polarity);
 		}
 	}
 
@@ -3161,13 +3165,13 @@ static void tc_attached_src_run(const int port)
 
 		if (IS_ENABLED(CONFIG_USB_PD_TRY_SRC))
 			tryWait = is_try_src_enabled(port) &&
-				!TC_CHK_FLAG(port, TC_FLAGS_TS_DTS_PARTNER);
+				  !TC_CHK_FLAG(port, TC_FLAGS_TS_DTS_PARTNER);
 
 		if (drp_state[port] == PD_DRP_FORCE_SOURCE)
 			new_tc_state = TC_UNATTACHED_SRC;
-		else if(IS_ENABLED(CONFIG_USB_PD_TRY_SRC))
-			new_tc_state = tryWait ?
-				TC_TRY_WAIT_SNK : TC_UNATTACHED_SNK;
+		else if (IS_ENABLED(CONFIG_USB_PD_TRY_SRC))
+			new_tc_state = tryWait ? TC_TRY_WAIT_SNK :
+						 TC_UNATTACHED_SNK;
 
 		set_state_tc(port, new_tc_state);
 		return;
@@ -3221,8 +3225,9 @@ static void tc_attached_src_run(const int port)
 
 			/* Perform Data Role Swap */
 			tc_set_data_role(port,
-				tc[port].data_role == PD_ROLE_DFP ?
-					PD_ROLE_UFP : PD_ROLE_DFP);
+					 tc[port].data_role == PD_ROLE_DFP ?
+						 PD_ROLE_UFP :
+						 PD_ROLE_DFP);
 		}
 
 		/*
@@ -3230,7 +3235,7 @@ static void tc_attached_src_run(const int port)
 		 * UnorientedDebugAccessory.SRC shall not drive Vconn
 		 */
 		if (IS_ENABLED(CONFIG_USBC_VCONN) &&
-				!TC_CHK_FLAG(port, TC_FLAGS_TS_DTS_PARTNER)) {
+		    !TC_CHK_FLAG(port, TC_FLAGS_TS_DTS_PARTNER)) {
 			/*
 			 * VCONN Swap Request
 			 */
@@ -3239,7 +3244,7 @@ static void tc_attached_src_run(const int port)
 				set_vconn(port, 1);
 				pe_vconn_swap_complete(port);
 			} else if (TC_CHK_FLAG(port,
-						TC_FLAGS_REQUEST_VC_SWAP_OFF)) {
+					       TC_FLAGS_REQUEST_VC_SWAP_OFF)) {
 				TC_CLR_FLAG(port, TC_FLAGS_REQUEST_VC_SWAP_OFF);
 				set_vconn(port, 0);
 				pe_vconn_swap_complete(port);
@@ -3265,8 +3270,7 @@ static void tc_attached_src_run(const int port)
 		 * applied.
 		 */
 		if (!TC_CHK_FLAG(port, TC_FLAGS_TS_DTS_PARTNER) &&
-			TC_CHK_FLAG(port, TC_FLAGS_CTVPD_DETECTED)) {
-
+		    TC_CHK_FLAG(port, TC_FLAGS_CTVPD_DETECTED)) {
 			set_state_tc(port, TC_CT_UNATTACHED_SNK);
 		}
 	}
@@ -3274,13 +3278,13 @@ static void tc_attached_src_run(const int port)
 
 	if (TC_CHK_FLAG(port, TC_FLAGS_UPDATE_CURRENT)) {
 		TC_CLR_FLAG(port, TC_FLAGS_UPDATE_CURRENT);
-		typec_set_source_current_limit(port,
-					tc[port].select_current_limit_rp);
+		typec_set_source_current_limit(
+			port, tc[port].select_current_limit_rp);
 		pd_update_contract(port);
 
 		/* Update Rp if no contract is present */
 		if (!IS_ENABLED(CONFIG_USB_PE_SM) ||
-						!pe_is_explicit_contract(port))
+		    !pe_is_explicit_contract(port))
 			typec_update_cc(port);
 	}
 }
@@ -3302,7 +3306,7 @@ static void tc_attached_src_exit(const int port)
 		 * a CTVPD was not detected
 		 */
 		if (TC_CHK_FLAG(port, TC_FLAGS_VCONN_ON) &&
-				!TC_CHK_FLAG(port, TC_FLAGS_CTVPD_DETECTED))
+		    !TC_CHK_FLAG(port, TC_FLAGS_CTVPD_DETECTED))
 			set_vconn(port, 0);
 	}
 
@@ -3332,14 +3336,14 @@ static __maybe_unused void check_drp_connection(const int port)
 	tc[port].drp_sink_time = get_time().val;
 
 	/* Get the next toggle state */
-	next_state = drp_auto_toggle_next_state(&tc[port].drp_sink_time,
-		tc[port].power_role, drp_state[port], cc1, cc2,
-		tcpm_auto_toggle_supported(port));
+	next_state = drp_auto_toggle_next_state(
+		&tc[port].drp_sink_time, tc[port].power_role, drp_state[port],
+		cc1, cc2, tcpm_auto_toggle_supported(port));
 
 	if (next_state == DRP_TC_DEFAULT)
-		next_state = (PD_ROLE_DEFAULT(port) == PD_ROLE_SOURCE)
-				? DRP_TC_UNATTACHED_SRC
-				: DRP_TC_UNATTACHED_SNK;
+		next_state = (PD_ROLE_DEFAULT(port) == PD_ROLE_SOURCE) ?
+				     DRP_TC_UNATTACHED_SRC :
+				     DRP_TC_UNATTACHED_SNK;
 
 	switch (next_state) {
 	case DRP_TC_UNATTACHED_SNK:
@@ -3491,8 +3495,8 @@ static void tc_try_src_entry(const int port)
 	 */
 	typec_select_pull(port, TYPEC_CC_RP);
 
-	typec_select_src_current_limit_rp(port,
-		typec_get_default_current_limit_rp(port));
+	typec_select_src_current_limit_rp(
+		port, typec_get_default_current_limit_rp(port));
 
 	/* Apply Rp */
 	typec_update_cc(port);
@@ -3507,7 +3511,7 @@ static void tc_try_src_run(const int port)
 	tcpm_get_cc(port, &cc1, &cc2);
 
 	if ((cc1 == TYPEC_CC_VOLT_RD && cc2 != TYPEC_CC_VOLT_RD) ||
-	     (cc1 != TYPEC_CC_VOLT_RD && cc2 == TYPEC_CC_VOLT_RD))
+	    (cc1 != TYPEC_CC_VOLT_RD && cc2 == TYPEC_CC_VOLT_RD))
 		new_cc_state = PD_CC_UFP_ATTACHED;
 	else
 		new_cc_state = PD_CC_NONE;
@@ -3801,7 +3805,6 @@ static void tc_cc_rd_entry(const int port)
 	tcpm_set_msg_header(port, tc[port].power_role, tc[port].data_role);
 }
 
-
 /**
  * Super State CC_RP
  */
@@ -3887,8 +3890,8 @@ void tc_run(const int port)
 	 * If pd_set_suspend set TC_FLAGS_REQUEST_SUSPEND, go directly to
 	 * TC_DISABLED.
 	 */
-	if (get_state_tc(port) != TC_DISABLED
-	    && TC_CHK_FLAG(port, TC_FLAGS_REQUEST_SUSPEND)) {
+	if (get_state_tc(port) != TC_DISABLED &&
+	    TC_CHK_FLAG(port, TC_FLAGS_REQUEST_SUSPEND)) {
 		/* Invalidate a contract, if there is one */
 		if (IS_ENABLED(CONFIG_USB_PE_SM))
 			pe_invalidate_explicit_contract(port);
@@ -3918,17 +3921,16 @@ static void pd_chipset_resume(void)
 	int i;
 
 	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		if(IS_ENABLED(CONFIG_USB_PE_SM))
+		if (IS_ENABLED(CONFIG_USB_PE_SM))
 			pd_resume_check_pr_swap_needed(i);
 
-		pd_set_dual_role_and_event(i,
-					   pd_get_drp_state_in_s0(),
-					   PD_EVENT_UPDATE_DUAL_ROLE
-					   | PD_EVENT_POWER_STATE_CHANGE);
+		pd_set_dual_role_and_event(i, pd_get_drp_state_in_s0(),
+					   PD_EVENT_UPDATE_DUAL_ROLE |
+						   PD_EVENT_POWER_STATE_CHANGE);
 
 		if (tc[i].data_role == PD_ROLE_DFP) {
 			pd_send_alert_msg(i, ADO_EXTENDED_ALERT_EVENT |
-					  ADO_POWER_STATE_CHANGE);
+						     ADO_POWER_STATE_CHANGE);
 		}
 	}
 
@@ -3941,14 +3943,13 @@ static void pd_chipset_suspend(void)
 	int i;
 
 	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		pd_set_dual_role_and_event(i,
-					   pd_get_drp_state_in_suspend(),
-					   PD_EVENT_UPDATE_DUAL_ROLE
-					   | PD_EVENT_POWER_STATE_CHANGE);
+		pd_set_dual_role_and_event(i, pd_get_drp_state_in_suspend(),
+					   PD_EVENT_UPDATE_DUAL_ROLE |
+						   PD_EVENT_POWER_STATE_CHANGE);
 
 		if (tc[i].data_role == PD_ROLE_DFP) {
 			pd_send_alert_msg(i, ADO_EXTENDED_ALERT_EVENT |
-					  ADO_POWER_STATE_CHANGE);
+						     ADO_POWER_STATE_CHANGE);
 		}
 	}
 
@@ -3974,12 +3975,15 @@ static void pd_chipset_reset(void)
 		 * kernel knows to consume discovery information for them.
 		 */
 		for (tx = TCPCI_MSG_SOP; tx <= TCPCI_MSG_SOP_PRIME; tx++) {
-			if (pd_get_identity_discovery(i, tx) != PD_DISC_NEEDED
-			    && pd_get_svids_discovery(i, tx) != PD_DISC_NEEDED
-			    && pd_get_modes_discovery(i, tx) != PD_DISC_NEEDED)
-				pd_notify_event(i, tx == TCPCI_MSG_SOP ?
-					PD_STATUS_EVENT_SOP_DISC_DONE :
-					PD_STATUS_EVENT_SOP_PRIME_DISC_DONE);
+			if (pd_get_identity_discovery(i, tx) !=
+				    PD_DISC_NEEDED &&
+			    pd_get_svids_discovery(i, tx) != PD_DISC_NEEDED &&
+			    pd_get_modes_discovery(i, tx) != PD_DISC_NEEDED)
+				pd_notify_event(
+					i,
+					tx == TCPCI_MSG_SOP ?
+						PD_STATUS_EVENT_SOP_DISC_DONE :
+						PD_STATUS_EVENT_SOP_PRIME_DISC_DONE);
 		}
 
 		/* Exit mode so AP can enter mode again after reset */
@@ -3995,10 +3999,9 @@ static void pd_chipset_startup(void)
 
 	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
 		TC_SET_FLAG(i, TC_FLAGS_UPDATE_USB_MUX);
-		pd_set_dual_role_and_event(i,
-					   pd_get_drp_state_in_suspend(),
-					   PD_EVENT_UPDATE_DUAL_ROLE
-					   | PD_EVENT_POWER_STATE_CHANGE);
+		pd_set_dual_role_and_event(i, pd_get_drp_state_in_suspend(),
+					   PD_EVENT_UPDATE_DUAL_ROLE |
+						   PD_EVENT_POWER_STATE_CHANGE);
 		/*
 		 * Request port discovery to restore any
 		 * alt modes.
@@ -4010,7 +4013,7 @@ static void pd_chipset_startup(void)
 
 		if (tc[i].data_role == PD_ROLE_DFP) {
 			pd_send_alert_msg(i, ADO_EXTENDED_ALERT_EVENT |
-					  ADO_POWER_STATE_CHANGE);
+						     ADO_POWER_STATE_CHANGE);
 		}
 	}
 
@@ -4024,14 +4027,13 @@ static void pd_chipset_shutdown(void)
 
 	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
 		TC_SET_FLAG(i, TC_FLAGS_UPDATE_USB_MUX);
-		pd_set_dual_role_and_event(i,
-					   PD_DRP_FORCE_SINK,
-					   PD_EVENT_UPDATE_DUAL_ROLE
-					   | PD_EVENT_POWER_STATE_CHANGE);
+		pd_set_dual_role_and_event(i, PD_DRP_FORCE_SINK,
+					   PD_EVENT_UPDATE_DUAL_ROLE |
+						   PD_EVENT_POWER_STATE_CHANGE);
 
 		if (tc[i].data_role == PD_ROLE_DFP) {
 			pd_send_alert_msg(i, ADO_EXTENDED_ALERT_EVENT |
-					  ADO_POWER_STATE_CHANGE);
+						     ADO_POWER_STATE_CHANGE);
 		}
 	}
 
diff --git a/common/usbc/usb_tc_vpd_sm.c b/common/usbc/usb_tc_vpd_sm.c
index 70f3ed6327..40b855db9b 100644
--- a/common/usbc/usb_tc_vpd_sm.c
+++ b/common/usbc/usb_tc_vpd_sm.c
@@ -1,8 +1,9 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
 #include "system.h"
@@ -17,15 +18,15 @@
 /* USB Type-C VCONN Powered Device module */
 
 #ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USB, format, ##args)
 #else /* CONFIG_COMMON_RUNTIME */
 #define CPRINTF(format, args...)
 #define CPRINTS(format, args...)
 #endif
 
 /* Type-C Layer Flags */
-#define TC_FLAGS_VCONN_ON           BIT(0)
+#define TC_FLAGS_VCONN_ON BIT(0)
 
 /**
  * This is the Type-C Port object that contains information needed to
@@ -61,7 +62,7 @@ enum usb_tc_state {
 static const struct usb_state tc_states[];
 
 /* List of human readable state names for console debugging */
-__maybe_unused static const char * const tc_state_names[] = {
+__maybe_unused static const char *const tc_state_names[] = {
 #ifdef CONFIG_COMMON_RUNTIME
 	[TC_DISABLED] = "Disabled",
 	[TC_UNATTACHED_SNK] = "Unattached.SNK",
@@ -270,11 +271,11 @@ static void tc_attach_wait_snk_run(const int port)
 	if (tc[port].host_cc_state != host_new_cc_state) {
 		tc[port].host_cc_state = host_new_cc_state;
 		if (host_new_cc_state == PD_CC_DFP_ATTACHED)
-			tc[port].cc_debounce = get_time().val +
-							PD_T_CC_DEBOUNCE;
+			tc[port].cc_debounce =
+				get_time().val + PD_T_CC_DEBOUNCE;
 		else
-			tc[port].cc_debounce = get_time().val +
-							PD_T_PD_DEBOUNCE;
+			tc[port].cc_debounce =
+				get_time().val + PD_T_PD_DEBOUNCE;
 
 		return;
 	}
@@ -293,7 +294,7 @@ static void tc_attach_wait_snk_run(const int port)
 	 * CC2 pins is SNK.Open for at least tPDDebounce.
 	 */
 	if (tc[port].host_cc_state == PD_CC_DFP_ATTACHED &&
-			(vpd_is_vconn_present() || vpd_is_host_vbus_present()))
+	    (vpd_is_vconn_present() || vpd_is_host_vbus_present()))
 		set_state_tc(port, TC_ATTACHED_SNK);
 	else if (tc[port].host_cc_state == PD_CC_NONE)
 		set_state_tc(port, TC_UNATTACHED_SNK);
diff --git a/common/usbc/usbc_pd_policy.c b/common/usbc/usbc_pd_policy.c
index 6a06d4014f..6d82ed114c 100644
--- a/common/usbc/usbc_pd_policy.c
+++ b/common/usbc/usbc_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,8 +19,8 @@
  * 1) If dr_swap_to_dfp_flag == true and port data role is UFP,
  *    transition to pe_drs_send_swap
  */
-__overridable bool port_discovery_dr_swap_policy(int port,
-	enum pd_data_role dr, bool dr_swap_flag)
+__overridable bool port_discovery_dr_swap_policy(int port, enum pd_data_role dr,
+						 bool dr_swap_flag)
 {
 	if (dr_swap_flag && dr == PD_ROLE_UFP)
 		return true;
@@ -37,10 +37,10 @@ __overridable bool port_discovery_dr_swap_policy(int port,
  *    then transition to pe_vcs_send_swap
  */
 __overridable bool port_discovery_vconn_swap_policy(int port,
-		bool vconn_swap_flag)
+						    bool vconn_swap_flag)
 {
 	if (IS_ENABLED(CONFIG_USBC_VCONN) && vconn_swap_flag &&
-		!tc_is_vconn_src(port) && tc_check_vconn_swap(port))
+	    !tc_is_vconn_src(port) && tc_check_vconn_swap(port))
 		return true;
 
 	/* Do not perform a VCONN swap */
diff --git a/common/usbc/usbc_task.c b/common/usbc/usbc_task.c
index 915827b692..56ea3d4d10 100644
--- a/common/usbc/usbc_task.c
+++ b/common/usbc/usbc_task.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,6 +6,7 @@
 #include "battery.h"
 #include "battery_smart.h"
 #include "board.h"
+#include "builtin/assert.h"
 #include "charge_manager.h"
 #include "charge_state.h"
 #include "chipset.h"
@@ -36,8 +37,8 @@
 #define USBC_EVENT_TIMEOUT (5 * MSEC)
 #define USBC_MIN_EVENT_TIMEOUT (1 * MSEC)
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 /*
  * If CONFIG_ASSERT_CCD_MODE_ON_DTS_CONNECT is not defined then
diff --git a/common/usbc_intr_task.c b/common/usbc_intr_task.c
index 0532645a35..3c67ba4102 100644
--- a/common/usbc_intr_task.c
+++ b/common/usbc_intr_task.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,7 +7,7 @@
 
 #include <stdint.h>
 
-#include "assert.h"
+#include "builtin/assert.h"
 #include "common.h"
 #include "compile_time_macros.h"
 #include "console.h"
@@ -18,19 +18,19 @@
 #include "usb_pd.h"
 #include "usb_pd_tcpm.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 /* Events for pd_interrupt_handler_task */
-#define PD_PROCESS_INTERRUPT  BIT(0)
+#define PD_PROCESS_INTERRUPT BIT(0)
 
 /*
  * Theoretically, we may need to support up to 480 USB-PD packets per second for
  * intensive operations such as FW update over PD. This value has tested well
  * preventing watchdog resets with a single bad port partner plugged in.
  */
-#define ALERT_STORM_MAX_COUNT   480
-#define ALERT_STORM_INTERVAL    SECOND
+#define ALERT_STORM_MAX_COUNT 480
+#define ALERT_STORM_INTERVAL SECOND
 
 static uint8_t pd_int_task_id[CONFIG_USB_PD_PORT_MAX_COUNT];
 
@@ -57,8 +57,7 @@ static void service_one_port(int port)
 	tcpc_alert(port);
 
 	now = get_time();
-	if (timestamp_expired(storm_tracker[port].time,
-			      &now)) {
+	if (timestamp_expired(storm_tracker[port].time, &now)) {
 		/* Reset timer into future */
 		storm_tracker[port].time.val = now.val + ALERT_STORM_INTERVAL;
 
@@ -91,7 +90,7 @@ __overridable void board_process_pd_alert(int port)
  */
 void pd_interrupt_handler_task(void *p)
 {
-	const int port = (int) ((intptr_t) p);
+	const int port = (int)((intptr_t)p);
 	const int port_mask = (PD_STATUS_TCPC_ALERT_0 << port);
 
 	ASSERT(port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
@@ -122,7 +121,6 @@ void pd_interrupt_handler_task(void *p)
 		 */
 		while ((tcpc_get_alert_status() & port_mask) &&
 		       pd_is_port_enabled(port)) {
-
 			service_one_port(port);
 		}
 
@@ -145,9 +143,10 @@ BUILD_ASSERT(PD_STATUS_TCPC_ALERT_3 == (PD_STATUS_TCPC_ALERT_0 << 3));
  * is not.
  */
 
+#if !defined(CONFIG_ZEPHYR) || defined(CONFIG_HAS_TASK_PD_INT_SHARED)
 void pd_shared_alert_task(void *p)
 {
-	const int sources_mask = (int) ((intptr_t) p);
+	const int sources_mask = (int)((intptr_t)p);
 	int want_alerts = 0;
 	int port;
 	int port_mask;
@@ -211,3 +210,4 @@ void pd_shared_alert_task(void *p)
 		} while (have_alerts != 0);
 	}
 }
+#endif /* !CONFIG_ZEPHYR || CONFIG_HAS_TASK_PD_INT_SHARED */
diff --git a/common/usbc_ocp.c b/common/usbc_ocp.c
index 3694cfec7e..ba975b6105 100644
--- a/common/usbc_ocp.c
+++ b/common/usbc_ocp.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,37 +16,14 @@
 #include "util.h"
 
 #ifndef TEST_BUILD
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 #else
 #define CPRINTF(args...)
 #define CPRINTS(args...)
 #endif
 
 /*
- * PD 3.1 Ver 1.3 7.1.7.1 Output Over Current Protection
- *
- * "After three consecutive over current events Source Shall go to
- * ErrorRecovery.
- *
- * Sources Should attempt to send a Hard Reset message when over
- * current protection engages followed by an Alert Message indicating
- * an OCP event once an Explicit Contract has been established.
- *
- * The Source Shall prevent continual system or port cycling if over
- * current protection continues to engage after initially resuming
- * either default operation or renegotiation. Latching off the port or
- * system is an acceptable response to recurring over current."
- *
- * Our policy will be first two OCPs -> hard reset
- * 3rd -> ErrorRecovery
- * 4th -> port latched off
- */
-#define OCP_HR_CNT 2
-
-#define OCP_MAX_CNT 4
-
-/*
  * Number of seconds until a latched-off port is re-enabled for sourcing after
  * detecting a physical disconnect.
  */
@@ -102,7 +79,6 @@ static void re_enable_ports(void)
 }
 DECLARE_DEFERRED(re_enable_ports);
 
-
 int usbc_ocp_add_event(int port)
 {
 	int delay = 0;
@@ -122,8 +98,8 @@ int usbc_ocp_add_event(int port)
 
 	if (oc_event_cnt_tbl[port] >= OCP_MAX_CNT) {
 		CPRINTS("C%d: OC event limit reached! "
-			   "Source path disabled until physical disconnect.",
-			   port);
+			"Source path disabled until physical disconnect.",
+			port);
 		pd_power_supply_reset(port);
 	} else if (oc_event_cnt_tbl[port] <= OCP_HR_CNT) {
 		/*
@@ -132,7 +108,7 @@ int usbc_ocp_add_event(int port)
 		 * contract.
 		 */
 		pd_send_hard_reset(port);
-		delay = PD_T_SRC_RECOVER + 100*MSEC;
+		delay = PD_T_SRC_RECOVER + 100 * MSEC;
 	} else {
 		/*
 		 * ErrorRecovery must be performed past the third OCP event,
@@ -140,7 +116,7 @@ int usbc_ocp_add_event(int port)
 		 * contract is in place
 		 */
 		pd_set_error_recovery(port);
-		delay = PD_T_ERROR_RECOVERY + 100*MSEC;
+		delay = PD_T_ERROR_RECOVERY + 100 * MSEC;
 	}
 
 	if (delay) {
@@ -148,11 +124,9 @@ int usbc_ocp_add_event(int port)
 		hook_call_deferred(&re_enable_ports_data, delay);
 	}
 
-
 	return EC_SUCCESS;
 }
 
-
 int usbc_ocp_clear_event_counter(int port)
 {
 	if ((port < 0) || (port >= board_get_usb_pd_port_count())) {
@@ -168,8 +142,7 @@ int usbc_ocp_clear_event_counter(int port)
 	 * actually detect the physical disconnect.
 	 */
 	if (oc_event_cnt_tbl[port]) {
-		hook_call_deferred(&clear_oc_tbl_data,
-				   OCP_COOLDOWN_DELAY_US);
+		hook_call_deferred(&clear_oc_tbl_data, OCP_COOLDOWN_DELAY_US);
 	}
 	return EC_SUCCESS;
 }
diff --git a/common/usbc_ppc.c b/common/usbc_ppc.c
index f6c7f6876d..bc626097f7 100644
--- a/common/usbc_ppc.c
+++ b/common/usbc_ppc.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,8 +15,8 @@
 #include "util.h"
 
 #ifndef TEST_BUILD
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 #else
 #define CPRINTF(args...)
 #define CPRINTS(args...)
@@ -24,20 +24,20 @@
 
 int ppc_prints(const char *string, int port)
 {
-#ifndef TEST_BUILD
-	return CPRINTS("ppc p%d %s", port, string);
-#else
+#if defined(TEST_BUILD) || !defined(CONFIG_USBC_PPC_LOGGING)
 	return 0;
-#endif
+#else
+	return CPRINTS("ppc p%d %s", port, string);
+#endif /* defined(TEST_BUILD) || !defined(CONFIG_USBC_PPC_LOGGING) */
 }
 
 int ppc_err_prints(const char *string, int port, int error)
 {
-#ifndef TEST_BUILD
-	return CPRINTS("ppc p%d %s (%d)", port, string, error);
-#else
+#if defined(TEST_BUILD) || !defined(CONFIG_USBC_PPC_LOGGING)
 	return 0;
-#endif
+#else
+	return CPRINTS("ppc p%d %s (%d)", port, string, error);
+#endif /* defined(TEST_BUILD) || !defined(CONFIG_USBC_PPC_LOGGING) */
 }
 
 __overridable bool board_port_has_ppc(int port)
@@ -277,7 +277,7 @@ int ppc_set_frs_enable(int port, int enable)
 	ppc = &ppc_chips[port];
 
 	if (ppc->drv->set_frs_enable)
-		rv = ppc->drv->set_frs_enable(port,enable);
+		rv = ppc->drv->set_frs_enable(port, enable);
 
 	return rv;
 }
@@ -304,7 +304,7 @@ int ppc_is_vbus_present(int port)
 #endif /* defined(CONFIG_USB_PD_VBUS_DETECT_PPC) */
 
 #ifdef CONFIG_CMD_PPC_DUMP
-static int command_ppc_dump(int argc, char **argv)
+static int command_ppc_dump(int argc, const char **argv)
 {
 	int port;
 	int rv = EC_ERROR_UNIMPLEMENTED;
diff --git a/common/util.c b/common/util.c
index 7b33cc097e..7672dc1325 100644
--- a/common/util.c
+++ b/common/util.c
@@ -1,30 +1,19 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Utility functions for Chrome EC */
 
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
 #include "util.h"
 
-__stdlib_compat int strcasecmp(const char *s1, const char *s2)
+int find_base(int base, int *c, const char **nptr)
 {
-	int diff;
-
-	do {
-		diff = tolower(*s1) - tolower(*s2);
-		if (diff)
-			return diff;
-	} while (*(s1++) && *(s2++));
-	return 0;
-}
-
-static int find_base(int base, int *c, const char **nptr)
-{
-	if ((base == 0 || base == 16) && *c == '0'
-	    && (**nptr == 'x' || **nptr == 'X')) {
+	if ((base == 0 || base == 16) && *c == '0' &&
+	    (**nptr == 'x' || **nptr == 'X')) {
 		*c = (*nptr)[1];
 		(*nptr) += 2;
 		base = 16;
@@ -35,7 +24,7 @@ static int find_base(int base, int *c, const char **nptr)
 }
 
 /* Like strtol(), but for integers */
-__stdlib_compat int strtoi(const char *nptr, char **endptr, int base)
+int strtoi(const char *nptr, char **endptr, int base)
 {
 	int result = 0;
 	int neg = 0;
@@ -71,58 +60,20 @@ __stdlib_compat int strtoi(const char *nptr, char **endptr, int base)
 	return neg ? -result : result;
 }
 
-#ifndef CONFIG_ZEPHYR
-__stdlib_compat unsigned long long int strtoull(const char *nptr, char **endptr,
-						int base)
-{
-	uint64_t result = 0;
-	int c = '\0';
-
-	while ((c = *nptr++) && isspace(c))
-		;
-
-	if (c == '+') {
-		c = *nptr++;
-	} else if (c == '-') {
-		if (endptr)
-			*endptr = (char *)nptr - 1;
-		return result;
-	}
-
-	base = find_base(base, &c, &nptr);
-
-	while (c) {
-		if (c >= '0' && c < '0' + MIN(base, 10))
-			result = result * base + (c - '0');
-		else if (c >= 'A' && c < 'A' + base - 10)
-			result = result * base + (c - 'A' + 10);
-		else if (c >= 'a' && c < 'a' + base - 10)
-			result = result * base + (c - 'a' + 10);
-		else
-			break;
-
-		c = *nptr++;
-	}
-
-	if (endptr)
-		*endptr = (char *)nptr - 1;
-	return result;
-}
-#endif /* !CONFIG_ZEPHYR */
-BUILD_ASSERT(sizeof(unsigned long long int) == sizeof(uint64_t));
-
-__stdlib_compat int parse_bool(const char *s, int *dest)
+int parse_bool(const char *s, int *dest)
 {
 	/* off, disable, false, no */
 	if (!strcasecmp(s, "off") || !strncasecmp(s, "dis", 3) ||
-	    tolower(*s) == 'f' || tolower(*s) == 'n') {
+	    tolower((unsigned char)*s) == 'f' ||
+	    tolower((unsigned char)*s) == 'n') {
 		*dest = 0;
 		return 1;
 	}
 
 	/* on, enable, true, yes */
 	if (!strcasecmp(s, "on") || !strncasecmp(s, "ena", 3) ||
-	    tolower(*s) == 't' || tolower(*s) == 'y') {
+	    tolower((unsigned char)*s) == 't' ||
+	    tolower((unsigned char)*s) == 'y') {
 		*dest = 1;
 		return 1;
 	}
@@ -131,7 +82,6 @@ __stdlib_compat int parse_bool(const char *s, int *dest)
 	return 0;
 }
 
-
 /* Constant-time memory comparison */
 int safe_memcmp(const void *s1, const void *s2, size_t size)
 {
@@ -166,7 +116,7 @@ void reverse(void *dest, size_t len)
 	}
 }
 
-__stdlib_compat char *strzcpy(char *dest, const char *src, int len)
+char *strzcpy(char *dest, const char *src, int len)
 {
 	char *d = dest;
 	if (len <= 0)
@@ -253,7 +203,7 @@ bool is_aligned(uint32_t addr, uint32_t align)
 
 int alignment_log2(unsigned int x)
 {
-	ASSERT(x != 0);	/* ctz(0) is undefined */
+	ASSERT(x != 0); /* ctz(0) is undefined */
 	return __builtin_ctz(x);
 }
 
@@ -261,9 +211,9 @@ int alignment_log2(unsigned int x)
 /* stateful conditional stuff */
 
 enum cond_internal_bits {
-	COND_CURR_MASK = BIT(0),		/* current value */
-	COND_RISE_MASK = BIT(1),		/* set if 0->1 */
-	COND_FALL_MASK = BIT(2),		/* set if 1->0 */
+	COND_CURR_MASK = BIT(0), /* current value */
+	COND_RISE_MASK = BIT(1), /* set if 0->1 */
+	COND_FALL_MASK = BIT(2), /* set if 1->0 */
 };
 
 void cond_init(cond_t *c, int val)
@@ -319,8 +269,8 @@ int cond_went(cond_t *c, int val)
  * *offset<0.  If argc<shift+1, leaves size unchanged, returning error if
  * *size<0.
  */
-int parse_offset_size(int argc, char **argv, int shift,
-			     int *offset, int *size)
+int parse_offset_size(int argc, const char **argv, int shift, int *offset,
+		      int *size)
 {
 	char *e;
 	int i;
@@ -417,10 +367,10 @@ int binary_first_base3_from_bits(int *bits, int nbits)
 			switch (bits[i]) {
 			case 0: /* Ignore '0' digits. */
 				break;
-			case 1:	/* Account for binaries 0 to 2^i - 1. */
+			case 1: /* Account for binaries 0 to 2^i - 1. */
 				binary_below += 1 << i;
 				break;
-			case 2:	/* Account for binaries 0 to 2^(i+1) - 1. */
+			case 2: /* Account for binaries 0 to 2^(i+1) - 1. */
 				binary_below += 1 << (i + 1);
 				has_z = 1;
 			}
diff --git a/common/vboot/common.c b/common/vboot/common.c
index 39f8c193c7..a92652364b 100644
--- a/common/vboot/common.c
+++ b/common/vboot/common.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,8 +10,8 @@
 #include "shared_mem.h"
 #include "vboot.h"
 
-#define CPRINTS(format, args...) cprints(CC_VBOOT, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_VBOOT, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_VBOOT, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_VBOOT, format, ##args)
 
 int vboot_is_padding_valid(const uint8_t *data, uint32_t start, uint32_t end)
 {
@@ -32,8 +32,8 @@ int vboot_is_padding_valid(const uint8_t *data, uint32_t start, uint32_t end)
 	return EC_SUCCESS;
 }
 
-int vboot_verify(const uint8_t *data, int len,
-		 const struct rsa_public_key *key, const uint8_t *sig)
+int vboot_verify(const uint8_t *data, int len, const struct rsa_public_key *key,
+		 const uint8_t *sig)
 {
 	struct sha256_ctx ctx;
 	uint8_t *hash;
diff --git a/common/vboot/efs2.c b/common/vboot/efs2.c
index a410c274f5..b45109029d 100644
--- a/common/vboot/efs2.c
+++ b/common/vboot/efs2.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,19 +26,23 @@
 #include "vboot.h"
 #include "vboot_hash.h"
 
-#define CPRINTS(format, args...) cprints(CC_VBOOT,"VB " format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_VBOOT,"VB " format, ## args)
+#define CPRINTS(format, args...) cprints(CC_VBOOT, "VB " format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_VBOOT, "VB " format, ##args)
 
+/* LCOV_EXCL_START - TODO(b/172210316) implement is_battery_ready(), and remove
+ * this lcov excl.
+ */
 static const char *boot_mode_to_string(uint8_t mode)
 {
 	static const char *boot_mode_str[] = {
-		[BOOT_MODE_NORMAL] =		"NORMAL",
-		[BOOT_MODE_NO_BOOT] =		"NO_BOOT",
+		[BOOT_MODE_NORMAL] = "NORMAL",
+		[BOOT_MODE_NO_BOOT] = "NO_BOOT",
 	};
 	if (mode < ARRAY_SIZE(boot_mode_str))
 		return boot_mode_str[mode];
 	return "UNDEF";
 }
+/* LCOV_EXCL_STOP */
 
 /*
  * Check whether the session has successfully ended or not. ERR_TIMEOUT is
@@ -46,8 +50,8 @@ static const char *boot_mode_to_string(uint8_t mode)
  */
 static bool is_valid_cr50_response(enum cr50_comm_err code)
 {
-	return code != CR50_COMM_ERR_TIMEOUT
-			&& (code >> 8) == CR50_COMM_ERR_PREFIX;
+	return code != CR50_COMM_ERR_TIMEOUT &&
+	       (code >> 8) == CR50_COMM_ERR_PREFIX;
 }
 
 __overridable void board_enable_packet_mode(bool enable)
@@ -74,8 +78,13 @@ static enum cr50_comm_err send_to_cr50(const uint8_t *data, size_t size)
 
 	if (uart_shell_stop()) {
 		/* Failed to stop the shell. */
+		/* LCOV_EXCL_START - At least on posix systems, uart_shell_stop
+		 * will never fail, it will crash the binary or hang forever on
+		 * error.
+		 */
 		board_enable_packet_mode(false);
 		return CR50_COMM_ERR_UNKNOWN;
+		/* LCOV_EXCL_STOP */
 	}
 
 	/*
@@ -108,7 +117,7 @@ static enum cr50_comm_err send_to_cr50(const uint8_t *data, size_t size)
 		while (!timeout) {
 			int c = uart_getc();
 			if (c != -1) {
-				res.error = res.error | c << (i*8);
+				res.error = res.error | c << (i * 8);
 				break;
 			}
 			msleep(1);
@@ -159,7 +168,7 @@ static enum cr50_comm_err cmd_to_cr50(enum cr50_comm_cmd cmd,
 	p->size = size;
 	memcpy(p->data, data, size);
 	p->crc = cros_crc8((uint8_t *)&p->type,
-		      sizeof(p->type) + sizeof(p->size) + size);
+			   sizeof(p->type) + sizeof(p->size) + size);
 
 	do {
 		rv = send_to_cr50((uint8_t *)&s,
@@ -191,17 +200,21 @@ static enum cr50_comm_err verify_hash(void)
 	return cmd_to_cr50(CR50_COMM_CMD_VERIFY_HASH, hash, SHA256_DIGEST_SIZE);
 }
 
+/* LCOV_EXCL_START - TODO(b/172210316) implement is_battery_ready(), and remove
+ * this lcov excl.
+ */
 static enum cr50_comm_err set_boot_mode(uint8_t mode)
 {
 	enum cr50_comm_err rv;
 
 	CPRINTS("Setting boot mode to %s(%d)", boot_mode_to_string(mode), mode);
-	rv = cmd_to_cr50(CR50_COMM_CMD_SET_BOOT_MODE,
-			 &mode, sizeof(enum boot_mode));
+	rv = cmd_to_cr50(CR50_COMM_CMD_SET_BOOT_MODE, &mode,
+			 sizeof(enum boot_mode));
 	if (rv != CR50_COMM_SUCCESS)
 		CPRINTS("Failed to set boot mode");
 	return rv;
 }
+/* LCOV_EXCL_STOP */
 
 static bool pd_comm_enabled;
 
@@ -216,10 +229,19 @@ bool vboot_allow_usb_pd(void)
 	return pd_comm_enabled;
 }
 
+#ifdef TEST_BUILD
+void vboot_disable_pd(void)
+{
+	pd_comm_enabled = false;
+}
+#endif
+
+/* LCOV_EXCL_START - This is just a stub intended to be overridden */
 __overridable void show_critical_error(void)
 {
 	CPRINTS("%s", __func__);
 }
+/* LCOV_EXCL_STOP */
 
 static void verify_and_jump(void)
 {
@@ -244,14 +266,16 @@ static void verify_and_jump(void)
 	}
 }
 
+/* LCOV_EXCL_START - This is just a stub intended to be overridden */
 __overridable void show_power_shortage(void)
 {
 	CPRINTS("%s", __func__);
 }
+/* LCOV_EXCL_STOP */
 
 static bool is_battery_ready(void)
 {
-	/* TODO: Add battery check (https://crbug.com/1045216) */
+	/* TODO(b/172210316): Add battery check */
 	return true;
 }
 
@@ -274,8 +298,8 @@ void vboot_main(void)
 	    (system_get_reset_flags() & EC_RESET_FLAG_STAY_IN_RO)) {
 		if (system_is_manual_recovery())
 			CPRINTS("In recovery mode");
-		if (!IS_ENABLED(CONFIG_BATTERY)
-				&& !IS_ENABLED(HAS_TASK_KEYSCAN)) {
+		if (!IS_ENABLED(CONFIG_BATTERY) &&
+		    !IS_ENABLED(HAS_TASK_KEYSCAN)) {
 			/*
 			 * For Chromeboxes, we relax security by allowing PD in
 			 * RO. Attackers don't gain meaningful advantage on
@@ -293,12 +317,16 @@ void vboot_main(void)
 		 * If battery is drained or bad, we will boot in NO_BOOT mode to
 		 * inform the user of the problem.
 		 */
+		/* LCOV_EXCL_START - TODO(b/172210316) implement
+		 * is_battery_ready(), and remove this lcov excl.
+		 */
 		if (!is_battery_ready()) {
 			CPRINTS("Battery not ready or bad");
 			if (set_boot_mode(BOOT_MODE_NO_BOOT) ==
-					CR50_COMM_SUCCESS)
+			    CR50_COMM_SUCCESS)
 				enable_pd();
 		}
+		/* LCOV_EXCL_STOP */
 
 		/* We'll enter recovery mode immediately, later, or never. */
 		return;
diff --git a/common/vboot/vb21_lib.c b/common/vboot/vb21_lib.c
index 4e215c14e5..ab7628371f 100644
--- a/common/vboot/vb21_lib.c
+++ b/common/vboot/vb21_lib.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -52,7 +52,6 @@ const struct vb21_packed_key *vb21_get_packed_key(void)
 
 static void read_rwsig_info(struct ec_response_rwsig_info *r)
 {
-
 	const struct vb21_packed_key *vb21_key;
 	int rv;
 
@@ -61,17 +60,21 @@ static void read_rwsig_info(struct ec_response_rwsig_info *r)
 	r->sig_alg = vb21_key->sig_alg;
 	r->hash_alg = vb21_key->hash_alg;
 	r->key_version = vb21_key->key_version;
-	{ BUILD_ASSERT(sizeof(r->key_id) == sizeof(vb21_key->id),
-		       "key ID sizes must match"); }
-	{ BUILD_ASSERT(sizeof(vb21_key->id) == sizeof(vb21_key->id.raw),
-		       "key ID sizes must match"); }
+	{
+		BUILD_ASSERT(sizeof(r->key_id) == sizeof(vb21_key->id),
+			     "key ID sizes must match");
+	}
+	{
+		BUILD_ASSERT(sizeof(vb21_key->id) == sizeof(vb21_key->id.raw),
+			     "key ID sizes must match");
+	}
 	memcpy(r->key_id, vb21_key->id.raw, sizeof(r->key_id));
 
 	rv = vb21_is_packed_key_valid(vb21_key);
 	r->key_is_valid = (rv == EC_SUCCESS);
 }
 
-static int command_rwsig_info(int argc, char **argv)
+static int command_rwsig_info(int argc, const char **argv)
 {
 	int i;
 	struct ec_response_rwsig_info r;
diff --git a/common/vboot/vboot.c b/common/vboot/vboot.c
index 910156335d..cf449da1b8 100644
--- a/common/vboot/vboot.c
+++ b/common/vboot/vboot.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,8 +25,8 @@
 #include "vboot.h"
 #include "vb21_struct.h"
 
-#define CPRINTS(format, args...) cprints(CC_VBOOT,"VB " format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_VBOOT,"VB " format, ## args)
+#define CPRINTS(format, args...) cprints(CC_VBOOT, "VB " format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_VBOOT, "VB " format, ##args)
 
 static int has_matrix_keyboard(void)
 {
@@ -45,34 +45,34 @@ static int verify_slot(enum ec_image slot)
 
 	CPRINTS("Verifying %s", ec_image_to_string(slot));
 
-	vb21_key = (const struct vb21_packed_key *)(
-			CONFIG_MAPPED_STORAGE_BASE +
-			CONFIG_EC_PROTECTED_STORAGE_OFF +
-			CONFIG_RO_PUBKEY_STORAGE_OFF);
+	vb21_key =
+		(const struct vb21_packed_key *)(CONFIG_MAPPED_STORAGE_BASE +
+						 CONFIG_EC_PROTECTED_STORAGE_OFF +
+						 CONFIG_RO_PUBKEY_STORAGE_OFF);
 	rv = vb21_is_packed_key_valid(vb21_key);
 	if (rv) {
 		CPRINTS("Invalid key (%d)", rv);
 		return EC_ERROR_VBOOT_KEY;
 	}
-	key = (const struct rsa_public_key *)
-		((const uint8_t *)vb21_key + vb21_key->key_offset);
+	key = (const struct rsa_public_key *)((const uint8_t *)vb21_key +
+					      vb21_key->key_offset);
 
 	if (slot == EC_IMAGE_RW_A) {
 		data = (const uint8_t *)(CONFIG_MAPPED_STORAGE_BASE +
-				CONFIG_EC_WRITABLE_STORAGE_OFF +
-				CONFIG_RW_A_STORAGE_OFF);
-		vb21_sig = (const struct vb21_signature *)(
-				CONFIG_MAPPED_STORAGE_BASE +
-				CONFIG_EC_WRITABLE_STORAGE_OFF +
-				CONFIG_RW_A_SIGN_STORAGE_OFF);
+					 CONFIG_EC_WRITABLE_STORAGE_OFF +
+					 CONFIG_RW_A_STORAGE_OFF);
+		vb21_sig = (const struct vb21_signature
+				    *)(CONFIG_MAPPED_STORAGE_BASE +
+				       CONFIG_EC_WRITABLE_STORAGE_OFF +
+				       CONFIG_RW_A_SIGN_STORAGE_OFF);
 	} else {
 		data = (const uint8_t *)(CONFIG_MAPPED_STORAGE_BASE +
-				CONFIG_EC_WRITABLE_STORAGE_OFF +
-				CONFIG_RW_B_STORAGE_OFF);
-		vb21_sig = (const struct vb21_signature *)(
-				CONFIG_MAPPED_STORAGE_BASE +
-				CONFIG_EC_WRITABLE_STORAGE_OFF +
-				CONFIG_RW_B_SIGN_STORAGE_OFF);
+					 CONFIG_EC_WRITABLE_STORAGE_OFF +
+					 CONFIG_RW_B_STORAGE_OFF);
+		vb21_sig = (const struct vb21_signature
+				    *)(CONFIG_MAPPED_STORAGE_BASE +
+				       CONFIG_EC_WRITABLE_STORAGE_OFF +
+				       CONFIG_RW_B_SIGN_STORAGE_OFF);
 	}
 
 	rv = vb21_is_signature_valid(vb21_sig, vb21_key);
diff --git a/common/vboot_hash.c b/common/vboot_hash.c
index 33172e7c74..ad41269794 100644
--- a/common/vboot_hash.c
+++ b/common/vboot_hash.c
@@ -1,16 +1,18 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Verified boot hash computing module for Chrome EC */
 
+#include "builtin/assert.h"
 #include "clock.h"
 #include "common.h"
 #include "console.h"
 #include "flash.h"
 #include "hooks.h"
 #include "host_command.h"
+#include "printf.h"
 #include "sha256.h"
 #include "shared_mem.h"
 #include "stdbool.h"
@@ -23,7 +25,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_VBOOT, outstr)
-#define CPRINTS(format, args...) cprints(CC_VBOOT, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_VBOOT, format, ##args)
 
 struct vboot_hash_tag {
 	uint8_t hash[SHA256_DIGEST_SIZE];
@@ -31,8 +33,8 @@ struct vboot_hash_tag {
 	uint32_t size;
 };
 
-#define CHUNK_SIZE 1024       /* Bytes to hash per deferred call */
-#define WORK_INTERVAL_US 100  /* Delay between deferred calls */
+#define CHUNK_SIZE 1024 /* Bytes to hash per deferred call */
+#define WORK_INTERVAL_US 100 /* Delay between deferred calls */
 
 /* Check that CHUNK_SIZE fits in shared memory. */
 SHARED_MEM_CHECK_SIZE(CHUNK_SIZE);
@@ -40,11 +42,11 @@ SHARED_MEM_CHECK_SIZE(CHUNK_SIZE);
 static uint32_t data_offset;
 static uint32_t data_size;
 static uint32_t curr_pos;
-static const uint8_t *hash;   /* Hash, or NULL if not valid */
+static const uint8_t *hash; /* Hash, or NULL if not valid */
 static int want_abort;
 static int in_progress;
-#define VBOOT_HASH_DEFERRED	true
-#define VBOOT_HASH_BLOCKING	false
+#define VBOOT_HASH_DEFERRED true
+#define VBOOT_HASH_BLOCKING false
 
 static struct sha256_ctx ctx;
 
@@ -117,9 +119,10 @@ static void hash_next_chunk(size_t size)
 {
 #ifdef CONFIG_MAPPED_STORAGE
 	crec_flash_lock_mapped_storage(1);
-	SHA256_update(&ctx, (const uint8_t *)
-				((uintptr_t)CONFIG_MAPPED_STORAGE_BASE +
-				 data_offset + curr_pos), size);
+	SHA256_update(&ctx,
+		      (const uint8_t *)((uintptr_t)CONFIG_MAPPED_STORAGE_BASE +
+					data_offset + curr_pos),
+		      size);
 	crec_flash_lock_mapped_storage(0);
 #else
 	if (read_and_hash_chunk(data_offset + curr_pos, size) != EC_SUCCESS)
@@ -129,6 +132,8 @@ static void hash_next_chunk(size_t size)
 
 static void vboot_hash_all_chunks(void)
 {
+	char str_buf[hex_str_buf_size(SHA256_PRINT_SIZE)];
+
 	do {
 		size_t size = MIN(CHUNK_SIZE, data_size - curr_pos);
 		hash_next_chunk(size);
@@ -136,7 +141,9 @@ static void vboot_hash_all_chunks(void)
 	} while (curr_pos < data_size);
 
 	hash = SHA256_final(&ctx);
-	CPRINTS("hash done %ph", HEX_BUF(hash, SHA256_PRINT_SIZE));
+	snprintf_hex_buffer(str_buf, sizeof(str_buf),
+			    HEX_BUF(hash, SHA256_PRINT_SIZE));
+	CPRINTS("hash done %s", str_buf);
 	in_progress = 0;
 	clock_enable_module(MODULE_FAST_CPU, 0);
 
@@ -164,9 +171,14 @@ static void vboot_hash_next_chunk(void)
 
 	curr_pos += size;
 	if (curr_pos >= data_size) {
+		char str_buf[hex_str_buf_size(SHA256_PRINT_SIZE)];
+
 		/* Store the final hash */
 		hash = SHA256_final(&ctx);
-		CPRINTS("hash done %ph", HEX_BUF(hash, SHA256_PRINT_SIZE));
+
+		snprintf_hex_buffer(str_buf, sizeof(str_buf),
+				    HEX_BUF(hash, SHA256_PRINT_SIZE));
+		CPRINTS("hash done %s", str_buf);
 
 		in_progress = 0;
 
@@ -271,9 +283,9 @@ int vboot_hash_invalidate(int offset, int size)
  */
 static uint32_t get_rw_size(void)
 {
-#ifdef CONFIG_VBOOT_EFS		/* Only needed for EFS, which signs and verifies
-				 * entire RW, thus not needed for EFS2, which
-				 * verifies only the used image size. */
+#ifdef CONFIG_VBOOT_EFS /* Only needed for EFS, which signs and verifies \
+			 * entire RW, thus not needed for EFS2, which    \
+			 * verifies only the used image size. */
 	return CONFIG_RW_SIZE;
 #else
 	return system_get_image_used(EC_IMAGE_RW);
@@ -327,10 +339,10 @@ static int get_offset(int offset)
 /****************************************************************************/
 /* Console commands */
 #ifdef CONFIG_CMD_HASH
-static int command_hash(int argc, char **argv)
+static int command_hash(int argc, const char **argv)
 {
-	uint32_t offset = CONFIG_EC_WRITABLE_STORAGE_OFF +
-			  CONFIG_RW_STORAGE_OFF;
+	uint32_t offset =
+		CONFIG_EC_WRITABLE_STORAGE_OFF + CONFIG_RW_STORAGE_OFF;
 	uint32_t size = CONFIG_RW_SIZE;
 	char *e;
 
@@ -342,9 +354,13 @@ static int command_hash(int argc, char **argv)
 			ccprintf("(aborting)\n");
 		else if (in_progress)
 			ccprintf("(in progress)\n");
-		else if (hash)
-			ccprintf("%ph\n", HEX_BUF(hash, SHA256_DIGEST_SIZE));
-		else
+		else if (hash) {
+			char str_buf[hex_str_buf_size(SHA256_DIGEST_SIZE)];
+
+			snprintf_hex_buffer(str_buf, sizeof(str_buf),
+					    HEX_BUF(hash, SHA256_DIGEST_SIZE));
+			ccprintf("%s\n", str_buf);
+		} else
 			ccprintf("(invalid)\n");
 
 		return EC_SUCCESS;
@@ -356,15 +372,14 @@ static int command_hash(int argc, char **argv)
 			return EC_SUCCESS;
 		} else if (!strcasecmp(argv[1], "rw")) {
 			return vboot_hash_start(
-					get_offset(EC_VBOOT_HASH_OFFSET_ACTIVE),
-					get_rw_size(),
-					NULL, 0, VBOOT_HASH_DEFERRED);
+				get_offset(EC_VBOOT_HASH_OFFSET_ACTIVE),
+				get_rw_size(), NULL, 0, VBOOT_HASH_DEFERRED);
 		} else if (!strcasecmp(argv[1], "ro")) {
 			return vboot_hash_start(
 				CONFIG_EC_PROTECTED_STORAGE_OFF +
-				CONFIG_RO_STORAGE_OFF,
-				system_get_image_used(EC_IMAGE_RO),
-				NULL, 0, VBOOT_HASH_DEFERRED);
+					CONFIG_RO_STORAGE_OFF,
+				system_get_image_used(EC_IMAGE_RO), NULL, 0,
+				VBOOT_HASH_DEFERRED);
 		}
 		return EC_ERROR_PARAM2;
 	}
@@ -384,12 +399,11 @@ static int command_hash(int argc, char **argv)
 		if (*e)
 			return EC_ERROR_PARAM3;
 
-		return vboot_hash_start(offset, size,
-					(const uint8_t *)&nonce,
+		return vboot_hash_start(offset, size, (const uint8_t *)&nonce,
 					sizeof(nonce), VBOOT_HASH_DEFERRED);
 	} else
-		return vboot_hash_start(offset, size,
-					NULL, 0, VBOOT_HASH_DEFERRED);
+		return vboot_hash_start(offset, size, NULL, 0,
+					VBOOT_HASH_DEFERRED);
 }
 DECLARE_CONSOLE_COMMAND(hash, command_hash,
 			"[abort | ro | rw] | [<offset> <size> [<nonce>]]",
@@ -399,8 +413,7 @@ DECLARE_CONSOLE_COMMAND(hash, command_hash,
 /* Host commands */
 
 /* Fill in the response with the current hash status */
-static void fill_response(struct ec_response_vboot_hash *r,
-			  int request_offset)
+static void fill_response(struct ec_response_vboot_hash *r, int request_offset)
 {
 	if (in_progress)
 		r->status = EC_VBOOT_HASH_STATUS_BUSY;
@@ -439,7 +452,7 @@ static int host_start_hash(const struct ec_params_vboot_hash *p)
 	if (offset == EC_VBOOT_HASH_OFFSET_RO)
 		size = system_get_image_used(EC_IMAGE_RO);
 	else if ((offset == EC_VBOOT_HASH_OFFSET_ACTIVE) ||
-			(offset == EC_VBOOT_HASH_OFFSET_UPDATE))
+		 (offset == EC_VBOOT_HASH_OFFSET_UPDATE))
 		size = get_rw_size();
 	offset = get_offset(offset);
 	rv = vboot_hash_start(offset, size, p->nonce_data, p->nonce_size,
@@ -493,6 +506,5 @@ host_command_vboot_hash(struct host_cmd_handler_args *args)
 		return EC_RES_INVALID_PARAM;
 	}
 }
-DECLARE_HOST_COMMAND(EC_CMD_VBOOT_HASH,
-		     host_command_vboot_hash,
+DECLARE_HOST_COMMAND(EC_CMD_VBOOT_HASH, host_command_vboot_hash,
 		     EC_VER_MASK(0));
diff --git a/common/vec3.c b/common/vec3.c
index dadf7715ff..67a6049dea 100644
--- a/common/vec3.c
+++ b/common/vec3.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,9 +9,8 @@
 #include "vec3.h"
 #include "util.h"
 
-static fpv3_t zero_initialized_vector = {
-	FLOAT_TO_FP(0.0f), FLOAT_TO_FP(0.0f), FLOAT_TO_FP(0.0f)
-};
+static fpv3_t zero_initialized_vector = { FLOAT_TO_FP(0.0f), FLOAT_TO_FP(0.0f),
+					  FLOAT_TO_FP(0.0f) };
 
 void fpv3_zero(fpv3_t v)
 {
diff --git a/common/version.c b/common/version.c
index 3978e796b5..8b1ac5e53d 100644
--- a/common/version.c
+++ b/common/version.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,8 +17,7 @@
 BUILD_ASSERT(CONFIG_ROLLBACK_VERSION >= 0);
 BUILD_ASSERT(CONFIG_ROLLBACK_VERSION <= INT32_MAX);
 
-const struct image_data __keep current_image_data
-	FIXED_SECTION("ver") = {
+const struct image_data __keep current_image_data FIXED_SECTION("ver") = {
 	.cookie1 = CROS_EC_IMAGE_DATA_COOKIE1,
 	.version = CROS_EC_VERSION32,
 #ifndef TEST_BUILD
@@ -69,7 +68,6 @@ static int get_num_commits(const struct image_data *data)
 	}
 
 	return (i == sizeof(data->version) ? 0 : ret);
-
 }
 /* LCOV_EXCL_STOP */
 
diff --git a/common/virtual_battery.c b/common/virtual_battery.c
index 8e88e22bcb..a9ad77e22b 100644
--- a/common/virtual_battery.c
+++ b/common/virtual_battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,7 +14,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
 
 #define BATT_MODE_UNINITIALIZED -1
 
@@ -34,12 +34,10 @@ static uint8_t cache_hit;
 static const uint8_t *batt_cmd_head;
 static int acc_write_len;
 
-int virtual_battery_handler(struct ec_response_i2c_passthru *resp,
-				   int in_len, int *err_code, int xferflags,
-				   int read_len, int write_len,
-				   const uint8_t *out)
+int virtual_battery_handler(struct ec_response_i2c_passthru *resp, int in_len,
+			    int *err_code, int xferflags, int read_len,
+			    int write_len, const uint8_t *out)
 {
-
 #if defined(CONFIG_BATTERY_PRESENT_GPIO) || \
 	defined(CONFIG_BATTERY_PRESENT_CUSTOM)
 	/*
@@ -74,7 +72,7 @@ int virtual_battery_handler(struct ec_response_i2c_passthru *resp,
 		} else {
 			sb_cmd_state = READ_VB;
 			*err_code = virtual_battery_operation(batt_cmd_head,
-						NULL, 0, 0);
+							      NULL, 0, 0);
 			/*
 			 * If the reg is not handled by virtual battery, we
 			 * do not support it.
@@ -118,10 +116,8 @@ int virtual_battery_handler(struct ec_response_i2c_passthru *resp,
 		/* write to virtual battery */
 		case START:
 		case WRITE_VB:
-			virtual_battery_operation(batt_cmd_head,
-						NULL,
-						0,
-						acc_write_len);
+			virtual_battery_operation(batt_cmd_head, NULL, 0,
+						  acc_write_len);
 			break;
 		/* read from virtual battery */
 		case READ_VB:
@@ -129,15 +125,13 @@ int virtual_battery_handler(struct ec_response_i2c_passthru *resp,
 				read_len += in_len;
 				memset(&resp->data[0], 0, read_len);
 				virtual_battery_operation(batt_cmd_head,
-							&resp->data[0],
-							read_len,
-							0);
+							  &resp->data[0],
+							  read_len, 0);
 			}
 			break;
 		default:
 			reset_parse_state();
 			return EC_ERROR_INVAL;
-
 		}
 		/* Reset the state in the end of messages */
 		reset_parse_state();
@@ -156,7 +150,7 @@ void reset_parse_state(void)
  * Copy memmap string data from offset to dest, up to size len, in the format
  * expected by SBS (first byte of dest contains strlen).
  */
-void copy_memmap_string(uint8_t *dest, int offset, int len)
+static void copy_memmap_string(uint8_t *dest, int offset, int len)
 {
 	uint8_t *memmap_str;
 	uint8_t memmap_strlen;
@@ -166,7 +160,8 @@ void copy_memmap_string(uint8_t *dest, int offset, int len)
 	memmap_str = host_get_memmap(offset);
 	/* memmap_str might not be NULL terminated */
 	memmap_strlen = *(memmap_str + EC_MEMMAP_TEXT_MAX - 1) == '\0' ?
-			strlen(memmap_str) : EC_MEMMAP_TEXT_MAX;
+				strlen(memmap_str) :
+				EC_MEMMAP_TEXT_MAX;
 	dest[0] = memmap_strlen;
 	memcpy(dest + 1, memmap_str, MIN(memmap_strlen, len - 1));
 }
@@ -180,10 +175,8 @@ static void copy_battery_info_string(uint8_t *dst, const uint8_t *src, int len)
 	strncpy(dst + 1, src, len - 1);
 }
 
-int virtual_battery_operation(const uint8_t *batt_cmd_head,
-			      uint8_t *dest,
-			      int read_len,
-			      int write_len)
+int virtual_battery_operation(const uint8_t *batt_cmd_head, uint8_t *dest,
+			      int read_len, int write_len)
 {
 	int val;
 	int year, month, day;
@@ -233,9 +226,8 @@ int virtual_battery_operation(const uint8_t *batt_cmd_head,
 					 * typical SB defaults.
 					 */
 					batt_mode_cache =
-					   MODE_INTERNAL_CHARGE_CONTROLLER |
-					   MODE_ALARM |
-					   MODE_CHARGER;
+						MODE_INTERNAL_CHARGE_CONTROLLER |
+						MODE_ALARM | MODE_CHARGER;
 
 			memcpy(dest, &batt_mode_cache, bounded_read_len);
 		}
@@ -278,7 +270,7 @@ int virtual_battery_operation(const uint8_t *batt_cmd_head,
 		break;
 	case SB_FULL_CHARGE_CAPACITY:
 		if (curr_batt->flags & BATT_FLAG_BAD_FULL_CAPACITY ||
-				curr_batt->flags & BATT_FLAG_BAD_VOLTAGE)
+		    curr_batt->flags & BATT_FLAG_BAD_VOLTAGE)
 			return EC_ERROR_BUSY;
 		val = curr_batt->full_capacity;
 		if (batt_mode_cache & MODE_CAPACITY)
@@ -308,7 +300,7 @@ int virtual_battery_operation(const uint8_t *batt_cmd_head,
 		break;
 	case SB_REMAINING_CAPACITY:
 		if (curr_batt->flags & BATT_FLAG_BAD_REMAINING_CAPACITY ||
-				curr_batt->flags & BATT_FLAG_BAD_VOLTAGE)
+		    curr_batt->flags & BATT_FLAG_BAD_VOLTAGE)
 			return EC_ERROR_BUSY;
 		val = curr_batt->remaining_capacity;
 		if (batt_mode_cache & MODE_CAPACITY)
diff --git a/common/vstore.c b/common/vstore.c
index 9b4636397c..254a515b48 100644
--- a/common/vstore.c
+++ b/common/vstore.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,7 +22,7 @@
 #include "system.h"
 #include "util.h"
 
-#define VSTORE_SYSJUMP_TAG  0x5653 /* "VS" */
+#define VSTORE_SYSJUMP_TAG 0x5653 /* "VS" */
 #define VSTORE_HOOK_VERSION 1
 
 struct vstore_slot {
@@ -32,7 +32,7 @@ struct vstore_slot {
 
 static struct vstore_slot vstore_slots[CONFIG_VSTORE_SLOT_COUNT];
 static const int vstore_size =
-		sizeof(struct vstore_slot) * CONFIG_VSTORE_SLOT_COUNT;
+	sizeof(struct vstore_slot) * CONFIG_VSTORE_SLOT_COUNT;
 BUILD_ASSERT(ARRAY_SIZE(vstore_slots) <= EC_VSTORE_SLOT_MAX);
 
 /*
@@ -97,7 +97,7 @@ static enum ec_status vstore_write(struct host_cmd_handler_args *args)
 }
 DECLARE_HOST_COMMAND(EC_CMD_VSTORE_WRITE, vstore_write, EC_VER_MASK(0));
 
-static void vstore_clear_lock(void)
+test_export_static void vstore_clear_lock(void)
 {
 	int i;
 
diff --git a/common/webusb_desc.c b/common/webusb_desc.c
index 41d39006e0..e2f51b4c0f 100644
--- a/common/webusb_desc.c
+++ b/common/webusb_desc.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/common/wireless.c b/common/wireless.c
index d1f5cad645..dfc2d4843e 100644
--- a/common/wireless.c
+++ b/common/wireless.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -34,13 +34,11 @@ static int suspend_flags = CONFIG_WIRELESS_SUSPEND;
 static void wireless_enable(int flags)
 {
 #ifdef WIRELESS_GPIO_WLAN
-	gpio_set_level(WIRELESS_GPIO_WLAN,
-		       flags & EC_WIRELESS_SWITCH_WLAN);
+	gpio_set_level(WIRELESS_GPIO_WLAN, flags & EC_WIRELESS_SWITCH_WLAN);
 #endif
 
 #ifdef WIRELESS_GPIO_WWAN
-	gpio_set_level(WIRELESS_GPIO_WWAN,
-		       flags & EC_WIRELESS_SWITCH_WWAN);
+	gpio_set_level(WIRELESS_GPIO_WWAN, flags & EC_WIRELESS_SWITCH_WWAN);
 #endif
 
 #ifdef WIRELESS_GPIO_BLUETOOTH
@@ -57,7 +55,6 @@ static void wireless_enable(int flags)
 		       !(flags & EC_WIRELESS_SWITCH_WLAN_POWER));
 #endif /* CONFIG_WLAN_POWER_ACTIVE_LOW */
 #endif
-
 }
 
 static int wireless_get(void)
@@ -126,7 +123,7 @@ static enum ec_status wireless_enable_cmd(struct host_cmd_handler_args *args)
 			(p->now_flags & p->now_mask));
 
 	suspend_flags = (suspend_flags & ~p->suspend_mask) |
-		(p->suspend_flags & p->suspend_mask);
+			(p->suspend_flags & p->suspend_mask);
 
 	/* And return the current flags */
 	r->now_flags = wireless_get();
@@ -134,11 +131,10 @@ static enum ec_status wireless_enable_cmd(struct host_cmd_handler_args *args)
 	args->response_size = sizeof(*r);
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_SWITCH_ENABLE_WIRELESS,
-		     wireless_enable_cmd,
+DECLARE_HOST_COMMAND(EC_CMD_SWITCH_ENABLE_WIRELESS, wireless_enable_cmd,
 		     EC_VER_MASK(0) | EC_VER_MASK(1));
 
-static int command_wireless(int argc, char **argv)
+static int command_wireless(int argc, const char **argv)
 {
 	char *e;
 	int i;
@@ -164,6 +160,5 @@ static int command_wireless(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(wireless, command_wireless,
-			"[now [suspend]]",
+DECLARE_CONSOLE_COMMAND(wireless, command_wireless, "[now [suspend]]",
 			"Get/set wireless flags");
diff --git a/core/cortex-m/atomic.h b/core/cortex-m/atomic.h
index a09f5cc8be..92ecdd96e5 100644
--- a/core/cortex-m/atomic.h
+++ b/core/cortex-m/atomic.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -41,4 +41,4 @@ static inline atomic_val_t atomic_and(atomic_t *addr, atomic_val_t bits)
 	return __atomic_fetch_and(addr, bits, __ATOMIC_SEQ_CST);
 }
 
-#endif  /* __CROS_EC_ATOMIC_H */
+#endif /* __CROS_EC_ATOMIC_H */
diff --git a/core/cortex-m/build.mk b/core/cortex-m/build.mk
index bcffe16e8d..1e2c47297b 100644
--- a/core/cortex-m/build.mk
+++ b/core/cortex-m/build.mk
@@ -1,24 +1,11 @@
 # -*- makefile -*-
-# Copyright 2012 The Chromium OS Authors. All rights reserved.
+# Copyright 2012 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
 # Cortex-M4 core OS files build
 #
 
-
-ifeq ($(cc-name),gcc)
-# coreboot sdk
-CROSS_COMPILE_ARM_DEFAULT:=/opt/coreboot-sdk/bin/arm-eabi-
-else
-# llvm sdk
-CROSS_COMPILE_ARM_DEFAULT:=armv7m-cros-eabi-
-endif
-
-$(call set-option,CROSS_COMPILE,\
-	$(CROSS_COMPILE_arm),\
-	$(CROSS_COMPILE_ARM_DEFAULT))
-
 # FPU compilation flags
 CFLAGS_FPU-$(CONFIG_FPU)=-mfloat-abi=hard
 ifeq ($(cc-name),gcc)
diff --git a/core/cortex-m/cache.S b/core/cortex-m/cache.S
index 0a3d3bb67d..d5089a920e 100644
--- a/core/cortex-m/cache.S
+++ b/core/cortex-m/cache.S
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/cortex-m/config_core.h b/core/cortex-m/config_core.h
index 0665b28852..949df7ee21 100644
--- a/core/cortex-m/config_core.h
+++ b/core/cortex-m/config_core.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/core/cortex-m/cpu.c b/core/cortex-m/cpu.c
index 7c31892c18..ffb6b7780c 100644
--- a/core/cortex-m/cpu.c
+++ b/core/cortex-m/cpu.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -16,7 +16,8 @@ void cpu_init(void)
 
 	/* Enable reporting of memory faults, bus faults and usage faults */
 	CPU_NVIC_SHCSR |= CPU_NVIC_SHCSR_MEMFAULTENA |
-		CPU_NVIC_SHCSR_BUSFAULTENA | CPU_NVIC_SHCSR_USGFAULTENA;
+			  CPU_NVIC_SHCSR_BUSFAULTENA |
+			  CPU_NVIC_SHCSR_USGFAULTENA;
 }
 
 #ifdef CONFIG_ARMV7M_CACHE
diff --git a/core/cortex-m/cpu.h b/core/cortex-m/cpu.h
index e3137cd864..8c284d6132 100644
--- a/core/cortex-m/cpu.h
+++ b/core/cortex-m/cpu.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,68 +10,69 @@
 
 #include <stdint.h>
 #include "compile_time_macros.h"
+#include "debug.h"
 
 /* Macro to access 32-bit registers */
-#define CPUREG(addr) (*(volatile uint32_t*)(addr))
+#define CPUREG(addr) (*(volatile uint32_t *)(addr))
 
-#define CPU_NVIC_ST_CTRL       CPUREG(0xE000E010)
-#define ST_ENABLE              BIT(0)
-#define ST_TICKINT             BIT(1)
-#define ST_CLKSOURCE           BIT(2)
-#define ST_COUNTFLAG           BIT(16)
+#define CPU_NVIC_ST_CTRL CPUREG(0xE000E010)
+#define ST_ENABLE BIT(0)
+#define ST_TICKINT BIT(1)
+#define ST_CLKSOURCE BIT(2)
+#define ST_COUNTFLAG BIT(16)
 
 /* Nested Vectored Interrupt Controller */
-#define CPU_NVIC_EN(x)         CPUREG(0xe000e100 + 4 * (x))
-#define CPU_NVIC_DIS(x)        CPUREG(0xe000e180 + 4 * (x))
-#define CPU_NVIC_UNPEND(x)     CPUREG(0xe000e280 + 4 * (x))
-#define CPU_NVIC_PRI(x)        CPUREG(0xe000e400 + 4 * (x))
+#define CPU_NVIC_EN(x) CPUREG(0xe000e100 + 4 * (x))
+#define CPU_NVIC_DIS(x) CPUREG(0xe000e180 + 4 * (x))
+#define CPU_NVIC_UNPEND(x) CPUREG(0xe000e280 + 4 * (x))
+#define CPU_NVIC_PRI(x) CPUREG(0xe000e400 + 4 * (x))
 /* SCB AIRCR : Application interrupt and reset control register */
-#define CPU_NVIC_APINT         CPUREG(0xe000ed0c)
-#define  CPU_NVIC_APINT_SYSRST  BIT(2)            /* System reset request */
-#define  CPU_NVIC_APINT_PRIOGRP (BIT(8)|BIT(9)|BIT(10))
-#define  CPU_NVIC_APINT_ENDIAN  BIT(15)           /* Endianness */
-#define  CPU_NVIC_APINT_KEY_RD  (0xFA05U << 16)
-#define  CPU_NVIC_APINT_KEY_WR  (0x05FAU << 16)
+#define CPU_NVIC_APINT CPUREG(0xe000ed0c)
+#define CPU_NVIC_APINT_SYSRST BIT(2) /* System reset request */
+#define CPU_NVIC_APINT_PRIOGRP (BIT(8) | BIT(9) | BIT(10))
+#define CPU_NVIC_APINT_ENDIAN BIT(15) /* Endianness */
+#define CPU_NVIC_APINT_KEY_RD (0xFA05U << 16)
+#define CPU_NVIC_APINT_KEY_WR (0x05FAU << 16)
 /* NVIC STIR : Software Trigger Interrupt Register */
-#define CPU_NVIC_SWTRIG        CPUREG(0xe000ef00)
+#define CPU_NVIC_SWTRIG CPUREG(0xe000ef00)
 /* SCB SCR : System Control Register */
-#define CPU_SCB_SYSCTRL        CPUREG(0xe000ed10)
+#define CPU_SCB_SYSCTRL CPUREG(0xe000ed10)
 
-#define CPU_NVIC_CCR           CPUREG(0xe000ed14)
-#define CPU_NVIC_SHCSR         CPUREG(0xe000ed24)
-#define CPU_NVIC_CFSR          CPUREG(0xe000ed28)
-#define CPU_NVIC_HFSR          CPUREG(0xe000ed2c)
-#define CPU_NVIC_DFSR          CPUREG(0xe000ed30)
-#define CPU_NVIC_MFAR          CPUREG(0xe000ed34)
-#define CPU_NVIC_BFAR          CPUREG(0xe000ed38)
+#define CPU_NVIC_CCR CPUREG(0xe000ed14)
+#define CPU_NVIC_SHCSR CPUREG(0xe000ed24)
+#define CPU_NVIC_CFSR CPUREG(0xe000ed28)
+#define CPU_NVIC_HFSR CPUREG(0xe000ed2c)
+#define CPU_NVIC_DFSR CPUREG(0xe000ed30)
+#define CPU_NVIC_MFAR CPUREG(0xe000ed34)
+#define CPU_NVIC_BFAR CPUREG(0xe000ed38)
 
 enum {
-	CPU_NVIC_CFSR_BFARVALID		= BIT(15),
-	CPU_NVIC_CFSR_MFARVALID		= BIT(7),
+	CPU_NVIC_CFSR_BFARVALID = BIT(15),
+	CPU_NVIC_CFSR_MFARVALID = BIT(7),
 
-	CPU_NVIC_CCR_ICACHE		= BIT(17),
-	CPU_NVIC_CCR_DCACHE		= BIT(16),
-	CPU_NVIC_CCR_DIV_0_TRAP		= BIT(4),
-	CPU_NVIC_CCR_UNALIGN_TRAP	= BIT(3),
+	CPU_NVIC_CCR_ICACHE = BIT(17),
+	CPU_NVIC_CCR_DCACHE = BIT(16),
+	CPU_NVIC_CCR_DIV_0_TRAP = BIT(4),
+	CPU_NVIC_CCR_UNALIGN_TRAP = BIT(3),
 
-	CPU_NVIC_HFSR_DEBUGEVT		= 1UL << 31,
-	CPU_NVIC_HFSR_FORCED		= BIT(30),
-	CPU_NVIC_HFSR_VECTTBL		= BIT(1),
+	CPU_NVIC_HFSR_DEBUGEVT = 1UL << 31,
+	CPU_NVIC_HFSR_FORCED = BIT(30),
+	CPU_NVIC_HFSR_VECTTBL = BIT(1),
 
-	CPU_NVIC_SHCSR_MEMFAULTENA	= BIT(16),
-	CPU_NVIC_SHCSR_BUSFAULTENA	= BIT(17),
-	CPU_NVIC_SHCSR_USGFAULTENA	= BIT(18),
+	CPU_NVIC_SHCSR_MEMFAULTENA = BIT(16),
+	CPU_NVIC_SHCSR_BUSFAULTENA = BIT(17),
+	CPU_NVIC_SHCSR_USGFAULTENA = BIT(18),
 };
 
 /* System Control Block: cache registers */
-#define CPU_SCB_CCSIDR         CPUREG(0xe000ed80)
-#define CPU_SCB_CCSELR         CPUREG(0xe000ed84)
-#define CPU_SCB_ICIALLU        CPUREG(0xe000ef50)
-#define CPU_SCB_DCISW          CPUREG(0xe000ef60)
-#define CPU_SCB_DCCISW         CPUREG(0xe000ef74)
+#define CPU_SCB_CCSIDR CPUREG(0xe000ed80)
+#define CPU_SCB_CCSELR CPUREG(0xe000ed84)
+#define CPU_SCB_ICIALLU CPUREG(0xe000ef50)
+#define CPU_SCB_DCISW CPUREG(0xe000ef60)
+#define CPU_SCB_DCCISW CPUREG(0xe000ef74)
 
 /* Floating Point Context Address Register */
-#define CPU_FPU_FPCAR          CPUREG(0xe000ef38)
+#define CPU_FPU_FPCAR CPUREG(0xe000ef38)
 
 /*
  * As defined by Armv7-M Reference Manual B1.5.7 "Context state stacking on
@@ -85,28 +86,29 @@ enum {
 #define FPU_FPSCR_UFC BIT(3) /* Underflow */
 #define FPU_FPSCR_IXC BIT(4) /* Inexact */
 #define FPU_FPSCR_IDC BIT(7) /* Input denormal */
-#define FPU_FPSCR_EXC_FLAGS (FPU_FPSCR_IOC | FPU_FPSCR_DZC | FPU_FPSCR_OFC | \
-			     FPU_FPSCR_UFC | FPU_FPSCR_IXC | FPU_FPSCR_IDC)
+#define FPU_FPSCR_EXC_FLAGS                                              \
+	(FPU_FPSCR_IOC | FPU_FPSCR_DZC | FPU_FPSCR_OFC | FPU_FPSCR_UFC | \
+	 FPU_FPSCR_IXC | FPU_FPSCR_IDC)
 
 /* Bitfield values for EXC_RETURN. */
-#define EXC_RETURN_ES_MASK	BIT(0)
+#define EXC_RETURN_ES_MASK BIT(0)
 #define EXC_RETURN_ES_NON_SECURE 0
-#define EXC_RETURN_ES_SECURE	BIT(0)
-#define EXC_RETURN_SPSEL_MASK	BIT(2)
-#define EXC_RETURN_SPSEL_MSP	0
-#define EXC_RETURN_SPSEL_PSP	BIT(2)
-#define EXC_RETURN_MODE_MASK	BIT(3)
-#define EXC_RETURN_MODE_HANDLER	0
-#define EXC_RETURN_MODE_THREAD	BIT(3)
-#define EXC_RETURN_FTYPE_MASK	BIT(4)
-#define EXC_RETURN_FTYPE_ON	0
-#define EXC_RETURN_FTYPE_OFF	BIT(4)
-#define EXC_RETURN_DCRS_MASK	BIT(5)
-#define EXC_RETURN_DCRS_OFF	0
-#define EXC_RETURN_DCRS_ON	BIT(5)
-#define EXC_RETURN_S_MASK	BIT(6)
-#define EXC_RETURN_S_NON_SECURE	0
-#define EXC_RETURN_S_SECURE	BIT(6)
+#define EXC_RETURN_ES_SECURE BIT(0)
+#define EXC_RETURN_SPSEL_MASK BIT(2)
+#define EXC_RETURN_SPSEL_MSP 0
+#define EXC_RETURN_SPSEL_PSP BIT(2)
+#define EXC_RETURN_MODE_MASK BIT(3)
+#define EXC_RETURN_MODE_HANDLER 0
+#define EXC_RETURN_MODE_THREAD BIT(3)
+#define EXC_RETURN_FTYPE_MASK BIT(4)
+#define EXC_RETURN_FTYPE_ON 0
+#define EXC_RETURN_FTYPE_OFF BIT(4)
+#define EXC_RETURN_DCRS_MASK BIT(5)
+#define EXC_RETURN_DCRS_OFF 0
+#define EXC_RETURN_DCRS_ON BIT(5)
+#define EXC_RETURN_S_MASK BIT(6)
+#define EXC_RETURN_S_NON_SECURE 0
+#define EXC_RETURN_S_SECURE BIT(6)
 
 /* Set up the cpu to detect faults */
 void cpu_init(void);
@@ -132,10 +134,16 @@ static inline void cpu_set_interrupt_priority(uint8_t irq, uint8_t priority)
 	if (priority > 7)
 		priority = 7;
 
-	CPU_NVIC_PRI(irq / 4) =
-		(CPU_NVIC_PRI(irq / 4) &
-		 ~(7 << prio_shift)) |
-		(priority << prio_shift);
+	CPU_NVIC_PRI(irq / 4) = (CPU_NVIC_PRI(irq / 4) & ~(7 << prio_shift)) |
+				(priority << prio_shift);
+}
+
+static inline void cpu_enter_suspend_mode(void)
+{
+	/* Preserve debug sessions by not suspending when connected */
+	if (!debugger_is_connected()) {
+		asm("wfi");
+	}
 }
 
 #endif /* __CROS_EC_CPU_H */
diff --git a/core/cortex-m/debug.c b/core/cortex-m/debug.c
index db8891b5d8..214e8dd177 100644
--- a/core/cortex-m/debug.c
+++ b/core/cortex-m/debug.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/core/cortex-m/debug.h b/core/cortex-m/debug.h
index ae5ef08d06..30643268cb 100644
--- a/core/cortex-m/debug.h
+++ b/core/cortex-m/debug.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/core/cortex-m/ec.lds.S b/core/cortex-m/ec.lds.S
index f85b262c18..8580e366b7 100644
--- a/core/cortex-m/ec.lds.S
+++ b/core/cortex-m/ec.lds.S
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -309,6 +309,10 @@ SECTIONS
 		KEEP(*(.rodata.HOOK_USB_PD_CONNECT))
 		__hooks_usb_pd_connect_end = .;
 
+		__hooks_power_supply_change = .;
+		KEEP(*(.rodata.HOOK_POWER_SUPPLY_CHANGE))
+		__hooks_power_supply_change_end = .;
+
 		__deferred_funcs = .;
 		KEEP(*(.rodata.deferred))
 		__deferred_funcs_end = .;
@@ -457,6 +461,12 @@ SECTIONS
 		__data_end = .;
 
 		/*
+		 * _sbrk in newlib expects "end" symbol to point to start of
+		 * free memory.
+		 */
+		end = .;
+
+		/*
 		 * Shared memory buffer must be at the end of preallocated
 		 * RAM, so it can expand to use all the remaining RAM.
 		 */
diff --git a/core/cortex-m/fpu.c b/core/cortex-m/fpu.c
index 29fa568fd8..6e897a5266 100644
--- a/core/cortex-m/fpu.c
+++ b/core/cortex-m/fpu.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,8 +9,8 @@
 #include "hooks.h"
 #include "task.h"
 
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-#define CPUTS(format, args...) cputs(CC_SYSTEM, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+#define CPUTS(format, args...) cputs(CC_SYSTEM, format, ##args)
 
 /* Floating point unit common code */
 
@@ -65,8 +65,7 @@ static void fpu_warn(void)
 
 DECLARE_DEFERRED(fpu_warn);
 
-test_mockable
-void __keep fpu_irq(uint32_t excep_lr, uint32_t excep_sp)
+test_mockable void __keep fpu_irq(uint32_t excep_lr, uint32_t excep_sp)
 {
 	/*
 	 * Get address of exception FPU exception frame. FPCAR register points
diff --git a/core/cortex-m/include/fpu.h b/core/cortex-m/include/fpu.h
index 0949d336e2..74862d00ab 100644
--- a/core/cortex-m/include/fpu.h
+++ b/core/cortex-m/include/fpu.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,24 +12,16 @@
 static inline float sqrtf(float v)
 {
 	float root;
-	asm volatile(
-		"fsqrts %0, %1"
-		: "=w" (root)
-		: "w" (v)
-	);
+	asm volatile("fsqrts %0, %1" : "=w"(root) : "w"(v));
 	return root;
 }
 
 static inline float fabsf(float v)
 {
 	float root;
-	asm volatile(
-		"fabss %0, %1"
-		: "=w" (root)
-		: "w" (v)
-	);
+	asm volatile("fabss %0, %1" : "=w"(root) : "w"(v));
 	return root;
 }
-#endif  /* CONFIG_FPU */
+#endif /* CONFIG_FPU */
 
-#endif  /* __CROS_EC_FPU_H */
+#endif /* __CROS_EC_FPU_H */
diff --git a/core/cortex-m/include/mpu.h b/core/cortex-m/include/mpu.h
index 610728b501..75f95e7000 100644
--- a/core/cortex-m/include/mpu.h
+++ b/core/cortex-m/include/mpu.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,7 +14,7 @@
 /*
  * ARMv7-M SRAM region
  */
-#define CORTEX_M_SRAM_BASE	0x20000000
+#define CORTEX_M_SRAM_BASE 0x20000000
 
 /*
  * Region assignment. 7 as the highest, a higher index has a higher priority.
@@ -26,64 +26,64 @@
  * made mutually exclusive.
  */
 enum mpu_region {
-	REGION_DATA_RAM = 0,		/* For internal data RAM */
-	REGION_DATA_RAM2 = 1,		/* Second region for unaligned size */
-	REGION_CODE_RAM = 2,		/* For internal code RAM */
-	REGION_CODE_RAM2 = 3,		/* Second region for unaligned size */
-	REGION_STORAGE = 4,		/* For mapped internal storage */
-	REGION_STORAGE2 = 5,		/* Second region for unaligned size */
-	REGION_DATA_RAM_TEXT = 6,	/* Exempt region of data RAM */
-	REGION_CHIP_RESERVED = 7,	/* Reserved for use in chip/ */
+	REGION_DATA_RAM = 0, /* For internal data RAM */
+	REGION_DATA_RAM2 = 1, /* Second region for unaligned size */
+	REGION_CODE_RAM = 2, /* For internal code RAM */
+	REGION_CODE_RAM2 = 3, /* Second region for unaligned size */
+	REGION_STORAGE = 4, /* For mapped internal storage */
+	REGION_STORAGE2 = 5, /* Second region for unaligned size */
+	REGION_DATA_RAM_TEXT = 6, /* Exempt region of data RAM */
+	REGION_CHIP_RESERVED = 7, /* Reserved for use in chip/ */
 	/* only for chips with MPU supporting 16 regions */
-	REGION_UNCACHED_RAM = 8,        /* For uncached data RAM */
-	REGION_UNCACHED_RAM2 = 9,       /* Second region for unaligned size */
-	REGION_ROLLBACK = 10,           /* For rollback */
+	REGION_UNCACHED_RAM = 8, /* For uncached data RAM */
+	REGION_UNCACHED_RAM2 = 9, /* Second region for unaligned size */
+	REGION_ROLLBACK = 10, /* For rollback */
 };
 
-#define MPU_TYPE		REG32(0xe000ed90)
-#define MPU_CTRL		REG32(0xe000ed94)
-#define MPU_NUMBER		REG32(0xe000ed98)
-#define MPU_BASE		REG32(0xe000ed9c)
-#define MPU_SIZE		REG16(0xe000eda0)
-#define MPU_ATTR		REG16(0xe000eda2)
+#define MPU_TYPE REG32(0xe000ed90)
+#define MPU_CTRL REG32(0xe000ed94)
+#define MPU_NUMBER REG32(0xe000ed98)
+#define MPU_BASE REG32(0xe000ed9c)
+#define MPU_SIZE REG16(0xe000eda0)
+#define MPU_ATTR REG16(0xe000eda2)
 
 /*
  * See ARM v7-M Architecture Reference Manual
  * Section B3.5.5 MPU Type Register, MPU_TYPE
  */
-#define MPU_TYPE_UNIFIED_MASK	0x00FF0001
-#define MPU_TYPE_REG_COUNT(t)	(((t) >> 8) & 0xFF)
+#define MPU_TYPE_UNIFIED_MASK 0x00FF0001
+#define MPU_TYPE_REG_COUNT(t) (((t) >> 8) & 0xFF)
 
-#define MPU_CTRL_PRIVDEFEN	BIT(2)
-#define MPU_CTRL_HFNMIENA	BIT(1)
-#define MPU_CTRL_ENABLE		BIT(0)
+#define MPU_CTRL_PRIVDEFEN BIT(2)
+#define MPU_CTRL_HFNMIENA BIT(1)
+#define MPU_CTRL_ENABLE BIT(0)
 
 /*
  * Minimum region size is 32 bytes, 5 bits of address space
  */
-#define MPU_SIZE_BITS_MIN	5
+#define MPU_SIZE_BITS_MIN 5
 
 /*
  * XN (execute never) bit. It's bit 12 if accessed by halfword.
  *   0: XN off
  *   1: XN on
  */
-#define MPU_ATTR_XN		BIT(12)
+#define MPU_ATTR_XN BIT(12)
 
 /* AP bit. See table 3-5 of Stellaris LM4F232H5QC datasheet for details */
-#define MPU_ATTR_NO_NO (0 << 8)  /* previleged no access, unprev no access */
-#define MPU_ATTR_RW_NO (1 << 8)  /* previleged ReadWrite, unprev no access */
-#define MPU_ATTR_RW_RO (2 << 8)  /* previleged ReadWrite, unprev Read-only */
-#define MPU_ATTR_RW_RW (3 << 8)  /* previleged ReadWrite, unprev ReadWrite */
-#define MPU_ATTR_RO_NO (5 << 8)  /* previleged Read-only, unprev no access */
+#define MPU_ATTR_NO_NO (0 << 8) /* previleged no access, unprev no access */
+#define MPU_ATTR_RW_NO (1 << 8) /* previleged ReadWrite, unprev no access */
+#define MPU_ATTR_RW_RO (2 << 8) /* previleged ReadWrite, unprev Read-only */
+#define MPU_ATTR_RW_RW (3 << 8) /* previleged ReadWrite, unprev ReadWrite */
+#define MPU_ATTR_RO_NO (5 << 8) /* previleged Read-only, unprev no access */
 
 /* Suggested value for TEX S/C/B bit. See table 3-6 of Stellaris LM4F232H5QC
  * datasheet and table 38 of STM32F10xxx Cortex-M3 programming manual. */
 #ifndef MPU_ATTR_INTERNAL_SRAM
-#define MPU_ATTR_INTERNAL_SRAM  6  /* for Internal SRAM */
+#define MPU_ATTR_INTERNAL_SRAM 6 /* for Internal SRAM */
 #endif
 #ifndef MPU_ATTR_FLASH_MEMORY
-#define MPU_ATTR_FLASH_MEMORY   2  /* for flash memory */
+#define MPU_ATTR_FLASH_MEMORY 2 /* for flash memory */
 #endif
 
 /* Represent RW with at most 2 MPU regions. */
diff --git a/core/cortex-m/include/mpu_private.h b/core/cortex-m/include/mpu_private.h
index e6030114c2..eca474e14d 100644
--- a/core/cortex-m/include/mpu_private.h
+++ b/core/cortex-m/include/mpu_private.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/core/cortex-m/init.S b/core/cortex-m/init.S
index 9d4815ac79..5cde406a58 100644
--- a/core/cortex-m/init.S
+++ b/core/cortex-m/init.S
@@ -1,4 +1,4 @@
-/* Copyright 2011 The Chromium OS Authors. All rights reserved.
+/* Copyright 2011 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/cortex-m/irq_handler.h b/core/cortex-m/irq_handler.h
index dceda73958..eb23de7049 100644
--- a/core/cortex-m/irq_handler.h
+++ b/core/cortex-m/irq_handler.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,20 +23,20 @@
  * ensure it is enabled in the interrupt controller with the right priority.
  */
 #define DECLARE_IRQ(irq, routine, priority) DECLARE_IRQ_(irq, routine, priority)
-#define DECLARE_IRQ_(irq, routine, priority)                    \
-	void IRQ_HANDLER(irq)(void);				\
-	typedef struct {					\
-		int fake[irq >= CONFIG_IRQ_COUNT ? -1 : 1];	\
-	} irq_num_check_##irq;					\
-	static void __keep routine(void);			\
-	void IRQ_HANDLER(irq)(void)				\
-	{							\
-		void *ret = __builtin_return_address(0);	\
-		TASK_START_IRQ_HANDLER(ret);			\
-		routine();					\
-		task_resched_if_needed(ret);			\
-	}							\
-	const struct irq_priority __keep IRQ_PRIORITY(irq)	\
-	__attribute__((section(".rodata.irqprio")))		\
-			= {irq, priority}
-#endif  /* __CROS_EC_IRQ_HANDLER_H */
+#define DECLARE_IRQ_(irq, routine, priority)                         \
+	void IRQ_HANDLER(irq)(void);                                 \
+	typedef struct {                                             \
+		int fake[irq >= CONFIG_IRQ_COUNT ? -1 : 1];          \
+	} irq_num_check_##irq;                                       \
+	static void __keep routine(void);                            \
+	void IRQ_HANDLER(irq)(void)                                  \
+	{                                                            \
+		void *ret = __builtin_return_address(0);             \
+		TASK_START_IRQ_HANDLER(ret);                         \
+		routine();                                           \
+		task_resched_if_needed(ret);                         \
+	}                                                            \
+	const struct irq_priority __keep IRQ_PRIORITY(irq)           \
+		__attribute__((section(".rodata.irqprio"))) = { irq, \
+								priority }
+#endif /* __CROS_EC_IRQ_HANDLER_H */
diff --git a/core/cortex-m/llsr.c b/core/cortex-m/llsr.c
index 616b8653db..0ab920f628 100644
--- a/core/cortex-m/llsr.c
+++ b/core/cortex-m/llsr.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -29,7 +29,7 @@ uint64_t __keep __aeabi_llsr(uint64_t v, uint32_t shift)
 
 #ifdef CONFIG_LLSR_TEST
 
-static int command_llsr(int argc, char **argv)
+static int command_llsr(int argc, const char **argv)
 {
 	/* Volatile to prevent compilier optimization from interfering. */
 	volatile uint64_t start = 0x123456789ABCDEF0ull;
@@ -38,13 +38,11 @@ static int command_llsr(int argc, char **argv)
 	const struct {
 		uint32_t shift_by;
 		uint64_t result;
-	} cases[] = {
-		{0, start},
-		{16, 0x123456789ABCull},
-		{32, 0x12345678u},
-		{48, 0x1234u},
-		{64, 0u}
-	};
+	} cases[] = { { 0, start },
+		      { 16, 0x123456789ABCull },
+		      { 32, 0x12345678u },
+		      { 48, 0x1234u },
+		      { 64, 0u } };
 
 	for (x = 0; x < ARRAY_SIZE(cases); ++x) {
 		if ((start >> cases[x].shift_by) != cases[x].result) {
@@ -58,8 +56,7 @@ static int command_llsr(int argc, char **argv)
 }
 
 DECLARE_CONSOLE_COMMAND(
-		llsrtest, command_llsr,
-		"",
-		"Run tests against the LLSR ABI. Prints SUCCESS or FAILURE.");
+	llsrtest, command_llsr, "",
+	"Run tests against the LLSR ABI. Prints SUCCESS or FAILURE.");
 
-#endif  /* CONFIG_LLSR_TEST */
+#endif /* CONFIG_LLSR_TEST */
diff --git a/core/cortex-m/mpu.c b/core/cortex-m/mpu.c
index 29da931a28..c0793180dc 100644
--- a/core/cortex-m/mpu.c
+++ b/core/cortex-m/mpu.c
@@ -1,10 +1,11 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* MPU module for Chrome EC */
 
+#include "builtin/assert.h"
 #include "mpu.h"
 #include "console.h"
 #include "cpu.h"
@@ -37,7 +38,6 @@ bool mpu_is_unified(void)
 	return (mpu_get_type() & MPU_TYPE_UNIFIED_MASK) == 0;
 }
 
-
 /**
  * Update a memory region.
  *
@@ -74,7 +74,7 @@ int mpu_update_region(uint8_t region, uint32_t addr, uint8_t size_bit,
 	asm volatile("isb; dsb;");
 
 	MPU_NUMBER = region;
-	MPU_SIZE &= ~1;					/* Disable */
+	MPU_SIZE &= ~1; /* Disable */
 	if (enable) {
 		MPU_BASE = addr;
 		/*
@@ -85,8 +85,8 @@ int mpu_update_region(uint8_t region, uint32_t addr, uint8_t size_bit,
 		 * according to the doc, but they don't ..., do a single 32-bit
 		 * one.
 		 */
-		REG32(&MPU_SIZE) = ((uint32_t)attr << 16)
-				 | (srd << 8) | ((size_bit - 1) << 1) | 1;
+		REG32(&MPU_SIZE) = ((uint32_t)attr << 16) | (srd << 8) |
+				   ((size_bit - 1) << 1) | 1;
 	}
 
 	asm volatile("isb; dsb;");
@@ -117,7 +117,7 @@ static int mpu_config_region_greedy(uint8_t region, uint32_t addr,
 	 * regions must be naturally aligned to their size.
 	 */
 	uint8_t natural_alignment = MIN(addr == 0 ? 32 : alignment_log2(addr),
-				     alignment_log2(size));
+					alignment_log2(size));
 	uint8_t subregion_disable = 0;
 
 	if (natural_alignment >= 5) {
@@ -159,10 +159,9 @@ static int mpu_config_region_greedy(uint8_t region, uint32_t addr,
 		*consumed = 1 << natural_alignment;
 	}
 
-	return mpu_update_region(region,
-			       addr & ~((1 << natural_alignment) - 1),
-			       natural_alignment,
-			       attr, enable, subregion_disable);
+	return mpu_update_region(region, addr & ~((1 << natural_alignment) - 1),
+				 natural_alignment, attr, enable,
+				 subregion_disable);
 }
 
 /**
@@ -188,8 +187,8 @@ int mpu_config_region(uint8_t region, uint32_t addr, uint32_t size,
 	if (size == 0)
 		return EC_SUCCESS;
 
-	rv = mpu_config_region_greedy(region, addr, size,
-				      attr, enable, &consumed);
+	rv = mpu_config_region_greedy(region, addr, size, attr, enable,
+				      &consumed);
 	if (rv != EC_SUCCESS)
 		return rv;
 	ASSERT(consumed <= size);
@@ -198,8 +197,8 @@ int mpu_config_region(uint8_t region, uint32_t addr, uint32_t size,
 
 	/* Regions other than DATA_RAM_TEXT may use two MPU regions */
 	if (size > 0 && region != REGION_DATA_RAM_TEXT) {
-		rv = mpu_config_region_greedy(region + 1, addr, size,
-					      attr, enable, &consumed);
+		rv = mpu_config_region_greedy(region + 1, addr, size, attr,
+					      enable, &consumed);
 		if (rv != EC_SUCCESS)
 			return rv;
 		ASSERT(consumed <= size);
@@ -223,8 +222,8 @@ int mpu_config_region(uint8_t region, uint32_t addr, uint32_t size,
 static int mpu_unlock_region(uint8_t region, uint32_t addr, uint32_t size,
 			     uint8_t texscb)
 {
-	return mpu_config_region(region, addr, size,
-				 MPU_ATTR_RW_RW | texscb, 1);
+	return mpu_config_region(region, addr, size, MPU_ATTR_RW_RW | texscb,
+				 1);
 }
 
 void mpu_enable(void)
@@ -247,13 +246,9 @@ int mpu_protect_data_ram(void)
 	int ret;
 
 	/* Prevent code execution from data RAM */
-	ret = mpu_config_region(REGION_DATA_RAM,
-				CONFIG_RAM_BASE,
-				CONFIG_DATA_RAM_SIZE,
-				MPU_ATTR_XN |
-				MPU_ATTR_RW_RW |
-				MPU_ATTR_INTERNAL_SRAM,
-				1);
+	ret = mpu_config_region(
+		REGION_DATA_RAM, CONFIG_RAM_BASE, CONFIG_DATA_RAM_SIZE,
+		MPU_ATTR_XN | MPU_ATTR_RW_RW | MPU_ATTR_INTERNAL_SRAM, 1);
 	if (ret != EC_SUCCESS)
 		return ret;
 
@@ -271,18 +266,16 @@ int mpu_protect_code_ram(void)
 	return mpu_config_region(REGION_STORAGE,
 				 CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RO_MEM_OFF,
 				 CONFIG_CODE_RAM_SIZE,
-				 MPU_ATTR_RO_NO | MPU_ATTR_INTERNAL_SRAM,
-				 1);
+				 MPU_ATTR_RO_NO | MPU_ATTR_INTERNAL_SRAM, 1);
 }
 #else
 int mpu_lock_ro_flash(void)
 {
 	/* Prevent execution from internal mapped RO flash */
-	return mpu_config_region(REGION_STORAGE,
-				 CONFIG_MAPPED_STORAGE_BASE + CONFIG_RO_MEM_OFF,
-				 CONFIG_RO_SIZE,
-				 MPU_ATTR_XN | MPU_ATTR_RW_RW |
-				 MPU_ATTR_FLASH_MEMORY, 1);
+	return mpu_config_region(
+		REGION_STORAGE, CONFIG_MAPPED_STORAGE_BASE + CONFIG_RO_MEM_OFF,
+		CONFIG_RO_SIZE,
+		MPU_ATTR_XN | MPU_ATTR_RW_RW | MPU_ATTR_FLASH_MEMORY, 1);
 }
 
 /* Represent RW with at most 2 MPU regions. */
@@ -298,8 +291,7 @@ struct mpu_rw_regions mpu_get_rw_regions(void)
 	 * the region because on the Cortex-M3, Cortex-M4 and Cortex-M7, the
 	 * address used for an MPU region must be aligned to the size.
 	 */
-	aligned_size_bit =
-		__fls(regions.addr[0] & -regions.addr[0]);
+	aligned_size_bit = __fls(regions.addr[0] & -regions.addr[0]);
 	regions.size[0] = MIN(BIT(aligned_size_bit), CONFIG_RW_SIZE);
 	regions.addr[1] = regions.addr[0] + regions.size[0];
 	regions.size[1] = CONFIG_RW_SIZE - regions.size[0];
@@ -386,10 +378,10 @@ int mpu_lock_rollback(int lock)
 
 #ifdef CONFIG_CHIP_UNCACHED_REGION
 /* Store temporarily the regions ranges to use them for the MPU configuration */
-#define REGION(_name, _flag, _start, _size) \
-	static const uint32_t CONCAT2(_region_start_, _name) \
+#define REGION(_name, _flag, _start, _size)                           \
+	static const uint32_t CONCAT2(_region_start_, _name)          \
 		__attribute__((unused, section(".unused"))) = _start; \
-	static const uint32_t CONCAT2(_region_size_, _name) \
+	static const uint32_t CONCAT2(_region_size_, _name)           \
 		__attribute__((unused, section(".unused"))) = _size;
 #include "memory_regions.inc"
 #undef REGION
@@ -424,7 +416,7 @@ int mpu_pre_init(void)
 		 * to the region size.
 		 */
 		rv = mpu_update_region(i, CORTEX_M_SRAM_BASE, MPU_SIZE_BITS_MIN,
-			0, 0, 0);
+				       0, 0, 0);
 		if (rv != EC_SUCCESS)
 			return rv;
 	}
diff --git a/core/cortex-m/panic-internal.h b/core/cortex-m/panic-internal.h
index 1a58afa8a2..6fa6440006 100644
--- a/core/cortex-m/panic-internal.h
+++ b/core/cortex-m/panic-internal.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,4 +8,4 @@
 
 void exception_panic(void) __attribute__((naked));
 
-#endif  /* __CROS_EC_PANIC_INTERNAL_H */
+#endif /* __CROS_EC_PANIC_INTERNAL_H */
diff --git a/core/cortex-m/panic.c b/core/cortex-m/panic.c
index 2f71080392..3a59fcf201 100644
--- a/core/cortex-m/panic.c
+++ b/core/cortex-m/panic.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,9 +20,8 @@
 /* Whether bus fault is ignored */
 static int bus_fault_ignored;
 
-
 /* Panic data goes at the end of RAM. */
-static struct panic_data * const pdata_ptr = PANIC_DATA_PTR;
+static struct panic_data *const pdata_ptr = PANIC_DATA_PTR;
 
 /* Preceded by stack, rounded down to nearest 64-bit-aligned boundary */
 static const uint32_t pstack_addr = ((uint32_t)pdata_ptr) & ~7;
@@ -77,7 +76,7 @@ static int32_t is_frame_in_handler_stack(const uint32_t exc_return)
 
 #ifdef CONFIG_DEBUG_EXCEPTIONS
 /* Names for each of the bits in the cfs register, starting at bit 0 */
-static const char * const cfsr_name[32] = {
+static const char *const cfsr_name[32] = {
 	/* MMFSR */
 	[0] = "Instruction access violation",
 	[1] = "Data access violation",
@@ -101,11 +100,9 @@ static const char * const cfsr_name[32] = {
 };
 
 /* Names for the first 5 bits in the DFSR */
-static const char * const dfsr_name[] = {
-	"Halt request",
-	"Breakpoint",
-	"Data watchpoint/trace",
-	"Vector catch",
+static const char *const dfsr_name[] = {
+	"Halt request",		  "Breakpoint",
+	"Data watchpoint/trace",  "Vector catch",
 	"External debug request",
 };
 
@@ -281,7 +278,7 @@ void panic_data_print(const struct panic_data *pdata)
 	print_reg(12, sregs, CORTEX_PANIC_FRAME_REGISTER_R12);
 	print_reg(13, lregs,
 		  in_handler ? CORTEX_PANIC_REGISTER_MSP :
-				     CORTEX_PANIC_REGISTER_PSP);
+			       CORTEX_PANIC_REGISTER_PSP);
 	print_reg(14, sregs, CORTEX_PANIC_FRAME_REGISTER_LR);
 	print_reg(15, sregs, CORTEX_PANIC_FRAME_REGISTER_PC);
 
@@ -310,24 +307,23 @@ void __keep report_panic(void)
 	sp = is_frame_in_handler_stack(
 		     pdata->cm.regs[CORTEX_PANIC_REGISTER_LR]) ?
 		     pdata->cm.regs[CORTEX_PANIC_REGISTER_MSP] :
-			   pdata->cm.regs[CORTEX_PANIC_REGISTER_PSP];
+		     pdata->cm.regs[CORTEX_PANIC_REGISTER_PSP];
 	/* If stack is valid, copy exception frame to pdata */
-	if ((sp & 3) == 0 &&
-	    sp >= CONFIG_RAM_BASE &&
+	if ((sp & 3) == 0 && sp >= CONFIG_RAM_BASE &&
 	    sp <= CONFIG_RAM_BASE + CONFIG_RAM_SIZE - 8 * sizeof(uint32_t)) {
 		const uint32_t *sregs = (const uint32_t *)sp;
 		int i;
 
 		/* Skip r0-r3 and r12 registers if necessary */
 		for (i = CORTEX_PANIC_FRAME_REGISTER_R0;
-		    i <= CORTEX_PANIC_FRAME_REGISTER_R12; i++)
+		     i <= CORTEX_PANIC_FRAME_REGISTER_R12; i++)
 			if (IS_ENABLED(CONFIG_PANIC_STRIP_GPR))
 				pdata->cm.frame[i] = 0;
 			else
 				pdata->cm.frame[i] = sregs[i];
 
 		for (i = CORTEX_PANIC_FRAME_REGISTER_LR;
-		    i < NUM_CORTEX_PANIC_FRAME_REGISTERS; i++)
+		     i < NUM_CORTEX_PANIC_FRAME_REGISTERS; i++)
 			pdata->cm.frame[i] = sregs[i];
 
 		pdata->flags |= PANIC_DATA_FLAG_FRAME_VALID;
@@ -401,38 +397,41 @@ void exception_panic(void)
 #endif
 		"stmia %[pregs], {r1-r11, lr}\n"
 		"mov sp, %[pstack]\n"
-		"bl report_panic\n" : :
-			[pregs] "r" (pdata_ptr->cm.regs),
-			[pstack] "r" (pstack_addr) :
-			/* Constraints protecting these from being clobbered.
-			 * Gcc should be using r0 & r12 for pregs and pstack. */
-			"r1", "r2", "r3", "r4", "r5", "r6",
-		/* clang warns that we're clobbering a reserved register:
-		 * inline asm clobber list contains reserved registers: R7
-		 * [-Werror,-Winline-asm]. The intent of the clobber list is
-		 * to force pregs and pstack to be in R0 and R12, which
-		 * still holds.
-		 */
+		"bl report_panic\n"
+		:
+		: [pregs] "r"(pdata_ptr->cm.regs), [pstack] "r"(pstack_addr)
+		:
+		/* Constraints protecting these from being clobbered.
+		 * Gcc should be using r0 & r12 for pregs and pstack. */
+		"r1", "r2", "r3", "r4", "r5", "r6",
+	/* clang warns that we're clobbering a reserved register:
+	 * inline asm clobber list contains reserved registers: R7
+	 * [-Werror,-Winline-asm]. The intent of the clobber list is
+	 * to force pregs and pstack to be in R0 and R12, which
+	 * still holds.
+	 */
 #ifndef __clang__
-			"r7",
+		"r7",
 #endif
-			"r8", "r9", "r10", "r11", "cc", "memory"
-		);
+		"r8", "r9", "r10", "r11", "cc", "memory");
 }
 
 #ifdef CONFIG_SOFTWARE_PANIC
 void software_panic(uint32_t reason, uint32_t info)
 {
-	__asm__("mov " STRINGIFY(SOFTWARE_PANIC_INFO_REG) ", %0\n"
-		"mov " STRINGIFY(SOFTWARE_PANIC_REASON_REG) ", %1\n"
-		"bl exception_panic\n"
-		: : "r"(info), "r"(reason));
+	__asm__("mov " STRINGIFY(
+			SOFTWARE_PANIC_INFO_REG) ", %0\n"
+						 "mov " STRINGIFY(
+							 SOFTWARE_PANIC_REASON_REG) ", %1\n"
+										    "bl exception_panic\n"
+		:
+		: "r"(info), "r"(reason));
 	__builtin_unreachable();
 }
 
 void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
 {
-	struct panic_data * const pdata = get_panic_data_write();
+	struct panic_data *const pdata = get_panic_data_write();
 	uint32_t *lregs;
 
 	lregs = pdata->cm.regs;
@@ -452,7 +451,7 @@ void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
 
 void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception)
 {
-	struct panic_data * const pdata = panic_get_data();
+	struct panic_data *const pdata = panic_get_data();
 	uint32_t *lregs;
 
 	if (pdata && pdata->struct_version == 2) {
diff --git a/core/cortex-m/switch.S b/core/cortex-m/switch.S
index 6573e0ecaa..512b48036f 100644
--- a/core/cortex-m/switch.S
+++ b/core/cortex-m/switch.S
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/cortex-m/task.c b/core/cortex-m/task.c
index 2ec1ec1dc2..ce6c8c9615 100644
--- a/core/cortex-m/task.c
+++ b/core/cortex-m/task.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,9 +6,11 @@
 /* Task scheduling / events module for Chrome EC operating system */
 
 #include "atomic.h"
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
 #include "cpu.h"
+#include "debug.h"
 #include "link_defs.h"
 #include "panic.h"
 #include "task.h"
@@ -21,10 +23,10 @@ typedef union {
 		 * Note that sp must be the first element in the task struct
 		 * for __switchto() to work.
 		 */
-		uint32_t sp;       /* Saved stack pointer for context switch */
-		atomic_t events;   /* Bitmaps of received events */
-		uint64_t runtime;  /* Time spent in task */
-		uint32_t *stack;   /* Start of stack */
+		uint32_t sp; /* Saved stack pointer for context switch */
+		atomic_t events; /* Bitmaps of received events */
+		uint64_t runtime; /* Time spent in task */
+		uint32_t *stack; /* Start of stack */
 	};
 } task_;
 
@@ -40,12 +42,10 @@ CONFIG_CTS_TASK_LIST
 #undef TASK
 
 /* Task names for easier debugging */
-#define TASK(n, r, d, s)  #n,
-static const char * const task_names[] = {
+#define TASK(n, r, d, s) #n,
+static const char *const task_names[] = {
 	"<< idle >>",
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
-	CONFIG_CTS_TASK_LIST
+	CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST CONFIG_CTS_TASK_LIST
 };
 #undef TASK
 
@@ -55,12 +55,12 @@ static uint64_t task_start_time; /* Time task scheduling started */
  * We only keep 32-bit values for exception start/end time, to avoid
  * accounting errors when we service interrupt when the timer wraps around.
  */
-static uint32_t exc_start_time;  /* Time of task->exception transition */
-static uint32_t exc_end_time;    /* Time of exception->task transition */
-static uint64_t exc_total_time;  /* Total time in exceptions */
-static uint32_t svc_calls;       /* Number of service calls */
-static uint32_t task_switches;   /* Number of times active task changed */
-static uint32_t irq_dist[CONFIG_IRQ_COUNT];  /* Distribution of IRQ calls */
+static uint32_t exc_start_time; /* Time of task->exception transition */
+static uint32_t exc_end_time; /* Time of exception->task transition */
+static uint64_t exc_total_time; /* Total time in exceptions */
+static uint32_t svc_calls; /* Number of service calls */
+static uint32_t task_switches; /* Number of times active task changed */
+static uint32_t irq_dist[CONFIG_IRQ_COUNT]; /* Distribution of IRQ calls */
 #endif
 
 extern void __switchto(task_ *from, task_ *to);
@@ -91,21 +91,20 @@ void __idle(void)
 		 * shortly therefore, resumes execution on exiting idle mode.
 		 * Workaround: Replace the idle function with the followings
 		 */
-		asm (
-			"cpsid i\n"             /* Disable interrupt */
-			"push {r0-r5}\n"        /* Save needed registers */
-			"wfi\n"                 /* Wait for int to enter idle */
-			"ldm %0, {r0-r5}\n"     /* Add a delay after WFI */
-			"pop {r0-r5}\n" /* Restore regs before enabling ints */
-			"isb\n"                 /* Flush the cpu pipeline */
-			"cpsie i\n" :: "r" (0x100A8000)  /* Enable interrupts */
+		asm("cpsid i\n" /* Disable interrupt */
+		    "push {r0-r5}\n" /* Save needed registers */
+		    "wfi\n" /* Wait for int to enter idle */
+		    "ldm %0, {r0-r5}\n" /* Add a delay after WFI */
+		    "pop {r0-r5}\n" /* Restore regs before enabling ints */
+		    "isb\n" /* Flush the cpu pipeline */
+		    "cpsie i\n" ::"r"(0x100A8000) /* Enable interrupts */
 		);
 #else
 		/*
 		 * Wait for the next irq event.  This stops the CPU clock
 		 * (sleep / deep sleep, depending on chip config).
 		 */
-		asm("wfi");
+		cpu_enter_suspend_mode();
 #endif
 	}
 }
@@ -121,20 +120,19 @@ static void task_exit_trap(void)
 }
 
 /* Startup parameters for all tasks. */
-#define TASK(n, r, d, s)  {	\
-	.r0 = (uint32_t)d,	\
-	.pc = (uint32_t)r,	\
-	.stack_size = s,	\
-},
+#define TASK(n, r, d, s)           \
+	{                          \
+		.r0 = (uint32_t)d, \
+		.pc = (uint32_t)r, \
+		.stack_size = s,   \
+	},
 static const struct {
 	uint32_t r0;
 	uint32_t pc;
 	uint16_t stack_size;
 } tasks_init[] = {
 	TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
-	CONFIG_CTS_TASK_LIST
+		CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST CONFIG_CTS_TASK_LIST
 };
 #undef TASK
 
@@ -142,17 +140,16 @@ static const struct {
 static task_ tasks[TASK_ID_COUNT];
 
 /* Reset constants and state for all tasks */
-#define TASK_RESET_SUPPORTED		BIT(31)
-#define TASK_RESET_LOCK			BIT(30)
-#define TASK_RESET_STATE_MASK		(TASK_RESET_SUPPORTED | TASK_RESET_LOCK)
-#define TASK_RESET_WAITERS_MASK		~TASK_RESET_STATE_MASK
-#define TASK_RESET_UNSUPPORTED		0
-#define TASK_RESET_STATE_LOCKED		(TASK_RESET_SUPPORTED | TASK_RESET_LOCK)
-#define TASK_RESET_STATE_UNLOCKED	TASK_RESET_SUPPORTED
+#define TASK_RESET_SUPPORTED BIT(31)
+#define TASK_RESET_LOCK BIT(30)
+#define TASK_RESET_STATE_MASK (TASK_RESET_SUPPORTED | TASK_RESET_LOCK)
+#define TASK_RESET_WAITERS_MASK ~TASK_RESET_STATE_MASK
+#define TASK_RESET_UNSUPPORTED 0
+#define TASK_RESET_STATE_LOCKED (TASK_RESET_SUPPORTED | TASK_RESET_LOCK)
+#define TASK_RESET_STATE_UNLOCKED TASK_RESET_SUPPORTED
 
 #ifdef CONFIG_TASK_RESET_LIST
-#define ENABLE_RESET(n) \
-	[TASK_ID_##n] = TASK_RESET_SUPPORTED,
+#define ENABLE_RESET(n) [TASK_ID_##n] = TASK_RESET_SUPPORTED,
 static uint32_t task_reset_state[TASK_ID_COUNT] = {
 #ifdef CONFIG_TASK_RESET_LIST
 	CONFIG_TASK_RESET_LIST
@@ -167,13 +164,10 @@ BUILD_ASSERT(TASK_ID_COUNT < (1 << (sizeof(task_id_t) * 8)));
 BUILD_ASSERT(BIT(TASK_ID_COUNT) < TASK_RESET_LOCK);
 
 /* Stacks for all tasks */
-#define TASK(n, r, d, s)  + s
-uint8_t task_stacks[0
-		    TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
-		    CONFIG_TASK_LIST
-		    CONFIG_TEST_TASK_LIST
-		    CONFIG_CTS_TASK_LIST
-] __aligned(8);
+#define TASK(n, r, d, s) +s
+uint8_t task_stacks[0 TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
+			    CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST
+				    CONFIG_CTS_TASK_LIST] __aligned(8);
 
 #undef TASK
 
@@ -210,7 +204,7 @@ static atomic_t tasks_ready = BIT(TASK_ID_HOOKS);
  */
 static atomic_t tasks_enabled = BIT(TASK_ID_HOOKS) | BIT(TASK_ID_IDLE);
 
-static int start_called;  /* Has task swapping started */
+static int start_called; /* Has task swapping started */
 
 static inline task_ *__task_id_to_ptr(task_id_t id)
 {
@@ -232,7 +226,7 @@ inline bool is_interrupt_enabled(void)
 	int primask;
 
 	/* Interrupts are enabled when PRIMASK bit is 0 */
-	asm("mrs %0, primask":"=r"(primask));
+	asm("mrs %0, primask" : "=r"(primask));
 
 	return !(primask & 0x1);
 }
@@ -240,8 +234,9 @@ inline bool is_interrupt_enabled(void)
 inline bool in_interrupt_context(void)
 {
 	int ret;
-	asm("mrs %0, ipsr \n"             /* read exception number */
-	    "lsl %0, #23  \n":"=r"(ret)); /* exception bits are the 9 LSB */
+	asm("mrs %0, ipsr \n" /* read exception number */
+	    "lsl %0, #23  \n"
+	    : "=r"(ret)); /* exception bits are the 9 LSB */
 	return ret;
 }
 
@@ -249,8 +244,8 @@ inline bool in_interrupt_context(void)
 static inline int get_interrupt_context(void)
 {
 	int ret;
-	asm("mrs %0, ipsr \n":"=r"(ret)); /* read exception number */
-	return ret & 0x1ff;               /* exception bits are the 9 LSB */
+	asm("mrs %0, ipsr \n" : "=r"(ret)); /* read exception number */
+	return ret & 0x1ff; /* exception bits are the 9 LSB */
 }
 #endif
 
@@ -351,7 +346,7 @@ void svc_handler(int desched, task_id_t resched)
 	if (next == current)
 		return;
 
-	/* Switch to new task */
+		/* Switch to new task */
 #ifdef CONFIG_TASK_PROFILING
 	task_switches++;
 #endif
@@ -364,7 +359,7 @@ void __schedule(int desched, int resched)
 	register int p0 asm("r0") = desched;
 	register int p1 asm("r1") = resched;
 
-	asm("svc 0"::"r"(p0),"r"(p1));
+	asm("svc 0" ::"r"(p0), "r"(p1));
 }
 
 #ifdef CONFIG_TASK_PROFILING
@@ -389,9 +384,9 @@ void __keep task_start_irq_handler(void *excep_return)
 	 * and we are not called from another exception (this must match the
 	 * logic for when we chain to svc_handler() below).
 	 */
-	if (!need_resched_or_profiling
-	    || (((uint32_t)excep_return & EXC_RETURN_MODE_MASK)
-		== EXC_RETURN_MODE_HANDLER))
+	if (!need_resched_or_profiling ||
+	    (((uint32_t)excep_return & EXC_RETURN_MODE_MASK) ==
+	     EXC_RETURN_MODE_HANDLER))
 		return;
 
 	exc_start_time = t;
@@ -404,9 +399,9 @@ void __keep task_resched_if_needed(void *excep_return)
 	 * Continue iff a rescheduling event happened or profiling is active,
 	 * and we are not called from another exception.
 	 */
-	if (!need_resched_or_profiling
-	    || (((uint32_t)excep_return & EXC_RETURN_MODE_MASK)
-		== EXC_RETURN_MODE_HANDLER))
+	if (!need_resched_or_profiling ||
+	    (((uint32_t)excep_return & EXC_RETURN_MODE_MASK) ==
+	     EXC_RETURN_MODE_HANDLER))
 		return;
 
 	svc_handler(0, 0);
@@ -570,10 +565,10 @@ static uint32_t init_task_context(task_id_t id)
 	tasks[id].sp = (uint32_t)sp;
 
 	/* Initial context on stack (see __switchto()) */
-	sp[8] = tasks_init[id].r0;          /* r0 */
-	sp[13] = (uint32_t)task_exit_trap;  /* lr */
-	sp[14] = tasks_init[id].pc;         /* pc */
-	sp[15] = 0x01000000;                /* psr */
+	sp[8] = tasks_init[id].r0; /* r0 */
+	sp[13] = (uint32_t)task_exit_trap; /* lr */
+	sp[14] = tasks_init[id].pc; /* pc */
+	sp[15] = 0x01000000; /* psr */
 
 	/* Fill unused stack; also used to detect stack overflow. */
 	for (sp = tasks[id].stack; sp < (uint32_t *)tasks[id].sp; sp++)
@@ -618,8 +613,7 @@ DECLARE_DEFERRED(deferred_task_reset);
  * and if it matches if_value, updates the state to new_value, and returns
  * TRUE.
  */
-static int update_reset_state(uint32_t *state,
-			      uint32_t if_value,
+static int update_reset_state(uint32_t *state, uint32_t if_value,
 			      uint32_t to_value)
 {
 	int update;
@@ -675,8 +669,7 @@ void task_enable_resets(void)
 	uint32_t *state = &task_reset_state[id];
 
 	if (*state == TASK_RESET_UNSUPPORTED) {
-		cprints(CC_TASK,
-			"%s called from non-resettable task, id: %d",
+		cprints(CC_TASK, "%s called from non-resettable task, id: %d",
 			__func__, id);
 		return;
 	}
@@ -719,8 +712,7 @@ void task_disable_resets(void)
 	uint32_t *state = &task_reset_state[id];
 
 	if (*state == TASK_RESET_UNSUPPORTED) {
-		cprints(CC_TASK,
-			"%s called from non-resettable task, id %d",
+		cprints(CC_TASK, "%s called from non-resettable task, id %d",
 			__func__, id);
 		return;
 	}
@@ -775,8 +767,8 @@ int task_reset_cleanup(void)
 	if (cleanup_req) {
 		while (!try_release_reset_lock(state)) {
 			/* Find the first waiter to notify. */
-			task_id_t notify_id = __fls(
-			    *state & TASK_RESET_WAITERS_MASK);
+			task_id_t notify_id =
+				__fls(*state & TASK_RESET_WAITERS_MASK);
 			/*
 			 * Remove the task from waiters first, so that
 			 * when it wakes after being notified, it is in
@@ -912,8 +904,9 @@ void mutex_lock(struct mutex *mtx)
 				     "   teq     %0, #0\n"
 				     "   it eq\n"
 				     "   strexeq %0, %2, [%1]\n"
-				     : "=&r" (value)
-				     : "r" (&mtx->lock), "r" (2) : "cc");
+				     : "=&r"(value)
+				     : "r"(&mtx->lock), "r"(2)
+				     : "cc");
 		/*
 		 * "value" is equals to 1 if the store conditional failed,
 		 * 2 if somebody else owns the mutex, 0 else.
@@ -976,7 +969,7 @@ void task_print_list(void)
 	}
 }
 
-static int command_task_info(int argc, char **argv)
+static int command_task_info(int argc, const char **argv)
 {
 #ifdef CONFIG_TASK_PROFILING
 	int total = 0;
@@ -1005,12 +998,11 @@ static int command_task_info(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_SAFE_CONSOLE_COMMAND(taskinfo, command_task_info,
-			     NULL,
+DECLARE_SAFE_CONSOLE_COMMAND(taskinfo, command_task_info, NULL,
 			     "Print task info");
 
 #ifdef CONFIG_CMD_TASKREADY
-static int command_task_ready(int argc, char **argv)
+static int command_task_ready(int argc, const char **argv)
 {
 	if (argc < 2) {
 		ccprintf("tasks_ready: 0x%08x\n", (int)tasks_ready);
@@ -1022,8 +1014,7 @@ static int command_task_ready(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(taskready, command_task_ready,
-			"[setmask]",
+DECLARE_CONSOLE_COMMAND(taskready, command_task_ready, "[setmask]",
 			"Print/set ready tasks");
 #endif
 
@@ -1078,7 +1069,7 @@ int task_start(void)
 }
 
 #ifdef CONFIG_CMD_TASK_RESET
-static int command_task_reset(int argc, char **argv)
+static int command_task_reset(int argc, const char **argv)
 {
 	task_id_t id;
 	char *e;
@@ -1093,7 +1084,6 @@ static int command_task_reset(int argc, char **argv)
 
 	return EC_ERROR_PARAM_COUNT;
 }
-DECLARE_CONSOLE_COMMAND(taskreset, command_task_reset,
-			"task_id",
+DECLARE_CONSOLE_COMMAND(taskreset, command_task_reset, "task_id",
 			"Reset a task");
-#endif  /* CONFIG_CMD_TASK_RESET */
+#endif /* CONFIG_CMD_TASK_RESET */
diff --git a/core/cortex-m/toolchain.mk b/core/cortex-m/toolchain.mk
new file mode 100644
index 0000000000..55ca2d74cd
--- /dev/null
+++ b/core/cortex-m/toolchain.mk
@@ -0,0 +1,15 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+ifeq ($(cc-name),gcc)
+# coreboot sdk
+CROSS_COMPILE_ARM_DEFAULT:=/opt/coreboot-sdk/bin/arm-eabi-
+else
+# llvm sdk
+CROSS_COMPILE_ARM_DEFAULT:=armv7m-cros-eabi-
+endif
+
+$(call set-option,CROSS_COMPILE,\
+	$(CROSS_COMPILE_arm),\
+	$(CROSS_COMPILE_ARM_DEFAULT))
diff --git a/core/cortex-m/vecttable.c b/core/cortex-m/vecttable.c
index 4897376c1b..433898c00a 100644
--- a/core/cortex-m/vecttable.c
+++ b/core/cortex-m/vecttable.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -20,20 +20,18 @@ typedef void (*func)(void);
 #if PASS == 1
 /* Default exception handler */
 void __attribute__((used, naked)) default_handler(void);
-void default_handler()
+void default_handler(void)
 {
-	asm(
-	".thumb_func\n"
-	"	b exception_panic"
-	);
+	asm(".thumb_func\n"
+	    "	b exception_panic");
 }
 
 #define table(x) x
 
-#define weak_with_default __attribute__((used,weak,alias("default_handler")))
+#define weak_with_default __attribute__((used, weak, alias("default_handler")))
 
-#define vec(name) extern void weak_with_default name ## _handler(void);
-#define irq(num) vec(irq_ ## num)
+#define vec(name) extern void weak_with_default name##_handler(void);
+#define irq(num) vec(irq_##num)
 
 #define item(name) extern void name(void);
 #define null
@@ -59,21 +57,19 @@ void weak_with_default svc_handler(int desched, task_id_t resched);
  * This approach differs slightly from the one in the document,
  * it only loads r0 (desched) and r1 (resched) for svc_handler.
  */
-void __attribute__((used,naked)) svc_helper_handler(void);
-void svc_helper_handler()
+void __attribute__((used, naked)) svc_helper_handler(void);
+void svc_helper_handler(void)
 {
-	asm(
-	".thumb_func\n"
-	"	tst lr, #4		/* see if called from supervisor mode */\n"
-	"	mrs r2, msp		/* get the correct stack pointer into r2 */\n"
-	"	it ne\n"
-	"	mrsne r2, psp\n"
-	"	ldr r1, [r2, #4]	/* get regs from stack frame */\n"
-	"	ldr r0, [r2]\n"
-	"	b %0			/* call svc_handler */\n"
-	:
-	: "i"(svc_handler)
-	);
+	asm(".thumb_func\n"
+	    "	tst lr, #4		/* see if called from supervisor mode */\n"
+	    "	mrs r2, msp		/* get the correct stack pointer into r2 */\n"
+	    "	it ne\n"
+	    "	mrsne r2, psp\n"
+	    "	ldr r1, [r2, #4]	/* get regs from stack frame */\n"
+	    "	ldr r0, [r2]\n"
+	    "	b %0			/* call svc_handler */\n"
+	    :
+	    : "i"(svc_handler));
 }
 
 #endif /* PASS 1 */
@@ -100,277 +96,64 @@ void svc_helper_handler()
 #pragma clang diagnostic ignored "-Winitializer-overrides"
 #endif /* __clang__ */
 
-#define table(x)								\
-	const func vectors[] __attribute__((section(".text.vecttable"))) = {	\
-		x								\
-		[IRQ_UNUSED_OFFSET] = null					\
-	};
+#define table(x)                                     \
+	const func vectors[] __attribute__((section( \
+		".text.vecttable"))) = { x[IRQ_UNUSED_OFFSET] = null };
 
-#define vec(name) name ## _handler,
-#define irq(num) [num < CONFIG_IRQ_COUNT ? num + IRQ_OFFSET : IRQ_UNUSED_OFFSET] = vec(irq_ ## num)
+#define vec(name) name##_handler,
+#define irq(num)                                                          \
+	[num < CONFIG_IRQ_COUNT ? num + IRQ_OFFSET : IRQ_UNUSED_OFFSET] = \
+		vec(irq_##num)
 
 #define item(name) name,
-#define null (void*)0,
+#define null (void *)0,
 #endif /* PASS 2 */
 
-table(
-	item(stack_end)
-	item(reset)
-	vec(nmi)
-	vec(hard_fault)
-	vec(mpu_fault)
-	vec(bus_fault)
-	vec(usage_fault)
-	null
-	null
-	null
-	null
-	item(svc_helper_handler)
-	vec(debug)
-	null
-	vec(pendsv)
-	vec(sys_tick)
-	irq(0)
-	irq(1)
-	irq(2)
-	irq(3)
-	irq(4)
-	irq(5)
-	irq(6)
-	irq(7)
-	irq(8)
-	irq(9)
-	irq(10)
-	irq(11)
-	irq(12)
-	irq(13)
-	irq(14)
-	irq(15)
-	irq(16)
-	irq(17)
-	irq(18)
-	irq(19)
-	irq(20)
-	irq(21)
-	irq(22)
-	irq(23)
-	irq(24)
-	irq(25)
-	irq(26)
-	irq(27)
-	irq(28)
-	irq(29)
-	irq(30)
-	irq(31)
-	irq(32)
-	irq(33)
-	irq(34)
-	irq(35)
-	irq(36)
-	irq(37)
-	irq(38)
-	irq(39)
-	irq(40)
-	irq(41)
-	irq(42)
-	irq(43)
-	irq(44)
-	irq(45)
-	irq(46)
-	irq(47)
-	irq(48)
-	irq(49)
-	irq(50)
-	irq(51)
-	irq(52)
-	irq(53)
-	irq(54)
-	irq(55)
-	irq(56)
-	irq(57)
-	irq(58)
-	irq(59)
-	irq(60)
-	irq(61)
-	irq(62)
-	irq(63)
-	irq(64)
-	irq(65)
-	irq(66)
-	irq(67)
-	irq(68)
-	irq(69)
-	irq(70)
-	irq(71)
-	irq(72)
-	irq(73)
-	irq(74)
-	irq(75)
-	irq(76)
-	irq(77)
-	irq(78)
-	irq(79)
-	irq(80)
-	irq(81)
-	irq(82)
-	irq(83)
-	irq(84)
-	irq(85)
-	irq(86)
-	irq(87)
-	irq(88)
-	irq(89)
-	irq(90)
-	irq(91)
-	irq(92)
-	irq(93)
-	irq(94)
-	irq(95)
-	irq(96)
-	irq(97)
-	irq(98)
-	irq(99)
-	irq(100)
-	irq(101)
-	irq(102)
-	irq(103)
-	irq(104)
-	irq(105)
-	irq(106)
-	irq(107)
-	irq(108)
-	irq(109)
-	irq(110)
-	irq(111)
-	irq(112)
-	irq(113)
-	irq(114)
-	irq(115)
-	irq(116)
-	irq(117)
-	irq(118)
-	irq(119)
-	irq(120)
-	irq(121)
-	irq(122)
-	irq(123)
-	irq(124)
-	irq(125)
-	irq(126)
-	irq(127)
-	irq(128)
-	irq(129)
-	irq(130)
-	irq(131)
-	irq(132)
-	irq(133)
-	irq(134)
-	irq(135)
-	irq(136)
-	irq(137)
-	irq(138)
-	irq(139)
-	irq(140)
-	irq(141)
-	irq(142)
-	irq(143)
-	irq(144)
-	irq(145)
-	irq(146)
-	irq(147)
-	irq(148)
-	irq(149)
-	irq(150)
-	irq(151)
-	irq(152)
-	irq(153)
-	irq(154)
-	irq(155)
-	irq(156)
-	irq(157)
-	irq(158)
-	irq(159)
-	irq(160)
-	irq(161)
-	irq(162)
-	irq(163)
-	irq(164)
-	irq(165)
-	irq(166)
-	irq(167)
-	irq(168)
-	irq(169)
-	irq(170)
-	irq(171)
-	irq(172)
-	irq(173)
-	irq(174)
-	irq(175)
-	irq(176)
-	irq(177)
-	irq(178)
-	irq(179)
-	irq(180)
-	irq(181)
-	irq(182)
-	irq(183)
-	irq(184)
-	irq(185)
-	irq(186)
-	irq(187)
-	irq(188)
-	irq(189)
-	irq(190)
-	irq(191)
-	irq(192)
-	irq(193)
-	irq(194)
-	irq(195)
-	irq(196)
-	irq(197)
-	irq(198)
-	irq(199)
-	irq(200)
-	irq(201)
-	irq(202)
-	irq(203)
-	irq(204)
-	irq(205)
-	irq(206)
-	irq(207)
-	irq(208)
-	irq(209)
-	irq(210)
-	irq(211)
-	irq(212)
-	irq(213)
-	irq(214)
-	irq(215)
-	irq(216)
-	irq(217)
-	irq(218)
-	irq(219)
-	irq(220)
-	irq(221)
-	irq(222)
-	irq(223)
-	irq(224)
-	irq(225)
-	irq(226)
-	irq(227)
-	irq(228)
-	irq(229)
-	irq(230)
-	irq(231)
-	irq(232)
-	irq(233)
-	irq(234)
-	irq(235)
-	irq(236)
-	irq(237)
-	irq(238)
-	irq(239)
-)
+table(item(stack_end) item(reset) vec(nmi) vec(hard_fault) vec(mpu_fault) vec(
+	bus_fault) vec(usage_fault) null null null null item(svc_helper_handler) vec(debug)
+	      null vec(pendsv) vec(sys_tick) irq(0) irq(1) irq(2) irq(3) irq(4) irq(
+		      5) irq(6) irq(7) irq(8) irq(9) irq(10) irq(11) irq(12) irq(13)
+		      irq(14) irq(15) irq(16) irq(17) irq(18) irq(19) irq(20) irq(
+			      21) irq(22) irq(23) irq(24) irq(25) irq(26) irq(27)
+			      irq(28) irq(29) irq(30) irq(31) irq(32) irq(33) irq(
+				      34) irq(35) irq(36) irq(37) irq(38) irq(39)
+				      irq(40) irq(41) irq(42) irq(43) irq(44) irq(
+					      45) irq(46) irq(47) irq(48) irq(49)
+					      irq(50) irq(51) irq(52) irq(53) irq(
+						      54) irq(55) irq(56) irq(57)
+						      irq(58) irq(59) irq(60) irq(
+							      61) irq(62) irq(63)
+							      irq(64) irq(65) irq(
+								      66) irq(67)
+								      irq(68) irq(
+									      69) irq(70)
+									      irq(71) irq(72) irq(73) irq(74) irq(75) irq(76) irq(77) irq(78) irq(79) irq(80) irq(81) irq(82) irq(83) irq(84) irq(85) irq(86) irq(87) irq(88) irq(89) irq(90) irq(91) irq(92) irq(93) irq(94) irq(95) irq(96) irq(97) irq(
+										      98) irq(99)
+										      irq(100) irq(101) irq(102) irq(103) irq(104) irq(105) irq(106) irq(
+											      107) irq(108) irq(109) irq(110) irq(111) irq(112) irq(113) irq(114) irq(115)
+											      irq(116) irq(117) irq(118) irq(119) irq(120) irq(121) irq(122) irq(
+												      123) irq(124) irq(125) irq(126) irq(127) irq(128) irq(129) irq(130) irq(131)
+												      irq(132) irq(133) irq(134) irq(135) irq(136) irq(137) irq(138) irq(
+													      139) irq(140) irq(141) irq(142) irq(143) irq(144) irq(145) irq(146) irq(147)
+													      irq(148) irq(149) irq(150) irq(151) irq(152) irq(153) irq(154) irq(
+														      155) irq(156) irq(157) irq(158) irq(159) irq(160) irq(161) irq(162) irq(163)
+														      irq(164) irq(165) irq(166) irq(167) irq(168) irq(169) irq(170) irq(
+															      171) irq(172) irq(173) irq(174) irq(175) irq(176) irq(177) irq(178)
+															      irq(179) irq(180) irq(181) irq(182) irq(183) irq(184) irq(185) irq(
+																      186) irq(187) irq(188) irq(189) irq(190) irq(191) irq(192)
+																      irq(193) irq(194) irq(195) irq(196) irq(197) irq(198) irq(
+																	      199) irq(200) irq(201) irq(202) irq(203) irq(204)
+																	      irq(205) irq(206) irq(207) irq(208) irq(209) irq(
+																		      210) irq(211) irq(212) irq(213) irq(214)
+																		      irq(215) irq(216) irq(217) irq(218) irq(
+																			      219) irq(220) irq(221) irq(222)
+																			      irq(223) irq(224) irq(225) irq(
+																				      226) irq(227) irq(228)
+																				      irq(229) irq(230) irq(231) irq(
+																					      232) irq(233) irq(234)
+																					      irq(235) irq(236) irq(
+																						      237) irq(238)
+																						      irq(239))
 
 #if PASS == 2
 #ifdef __clang__
diff --git a/core/cortex-m/watchdog.c b/core/cortex-m/watchdog.c
index c9faf54b2b..a94c6a9c25 100644
--- a/core/cortex-m/watchdog.c
+++ b/core/cortex-m/watchdog.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/core/cortex-m0/__builtin.c b/core/cortex-m0/__builtin.c
index 4bf495a011..8e2bf984ff 100644
--- a/core/cortex-m0/__builtin.c
+++ b/core/cortex-m0/__builtin.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/core/cortex-m0/atomic.h b/core/cortex-m0/atomic.h
index 7ec856ed62..9fd3ab849b 100644
--- a/core/cortex-m0/atomic.h
+++ b/core/cortex-m0/atomic.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,22 +16,22 @@
  *
  * There is no load/store exclusive on ARMv6-M, just disable interrupts
  */
-#define ATOMIC_OP(asm_op, a, v)					\
-({								\
-	uint32_t reg0, reg1;					\
-								\
-	__asm__ __volatile__(".syntax unified\n"		\
-			     "   cpsid i\n"			\
-			     "   ldr  %0, [%2]\n"		\
-			     "   mov  %1, %0\n"			\
-			     #asm_op" %0, %0, %3\n"		\
-			     "   str  %0, [%2]\n"		\
-			     "   cpsie i\n"			\
-			     : "=&l"(reg0), "=&l"(reg1)		\
-			     : "l"(a), "r"(v)			\
-			     : "cc", "memory");			\
-	reg1;							\
-})
+#define ATOMIC_OP(asm_op, a, v)                                 \
+	({                                                      \
+		uint32_t reg0, reg1;                            \
+                                                                \
+		__asm__ __volatile__(".syntax unified\n"        \
+				     "   cpsid i\n"             \
+				     "   ldr  %0, [%2]\n"       \
+				     "   mov  %1, %0\n" #asm_op \
+				     " %0, %0, %3\n"            \
+				     "   str  %0, [%2]\n"       \
+				     "   cpsie i\n"             \
+				     : "=&l"(reg0), "=&l"(reg1) \
+				     : "l"(a), "r"(v)           \
+				     : "cc", "memory");         \
+		reg1;                                           \
+	})
 
 static inline atomic_val_t atomic_clear_bits(atomic_t *addr, atomic_val_t bits)
 {
@@ -62,8 +62,8 @@ static inline atomic_val_t atomic_clear(atomic_t *addr)
 			     "   ldr     %0, [%1]\n"
 			     "   str     %2, [%1]\n"
 			     "   cpsie   i\n"
-			     : "=&l" (ret)
-			     : "l" (addr), "r" (0)
+			     : "=&l"(ret)
+			     : "l"(addr), "r"(0)
 			     : "cc", "memory");
 
 	return ret;
@@ -74,4 +74,4 @@ static inline atomic_val_t atomic_and(atomic_t *addr, atomic_val_t bits)
 	return ATOMIC_OP(ands, addr, bits);
 }
 
-#endif  /* __CROS_EC_ATOMIC_H */
+#endif /* __CROS_EC_ATOMIC_H */
diff --git a/core/cortex-m0/build.mk b/core/cortex-m0/build.mk
index eab2a1eb1c..0bea9d09ab 100644
--- a/core/cortex-m0/build.mk
+++ b/core/cortex-m0/build.mk
@@ -1,23 +1,11 @@
 # -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
+# Copyright 2014 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
 # Cortex-M0 core OS files build
 #
 
-ifeq ($(cc-name),gcc)
-# coreboot sdk
-CROSS_COMPILE_ARM_DEFAULT:=/opt/coreboot-sdk/bin/arm-eabi-
-else
-# llvm sdk
-CROSS_COMPILE_ARM_DEFAULT:=arm-none-eabi-
-endif
-
-$(call set-option,CROSS_COMPILE,\
-	$(CROSS_COMPILE_arm),\
-	$(CROSS_COMPILE_ARM_DEFAULT))
-
 # CPU specific compilation flags
 CFLAGS_CPU+=-mthumb
 ifeq ($(cc-name),clang)
diff --git a/core/cortex-m0/config_core.h b/core/cortex-m0/config_core.h
index a40756fb49..e954e5e0af 100644
--- a/core/cortex-m0/config_core.h
+++ b/core/cortex-m0/config_core.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/core/cortex-m0/cpu.c b/core/cortex-m0/cpu.c
index b354cc03e2..e180570863 100644
--- a/core/cortex-m0/cpu.c
+++ b/core/cortex-m0/cpu.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/cortex-m0/cpu.h b/core/cortex-m0/cpu.h
index c30095fd65..568b16eedb 100644
--- a/core/cortex-m0/cpu.h
+++ b/core/cortex-m0/cpu.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,41 +10,42 @@
 
 #include <stdint.h>
 #include "compile_time_macros.h"
+#include "debug.h"
 
 /* Macro to access 32-bit registers */
-#define CPUREG(addr) (*(volatile uint32_t*)(addr))
+#define CPUREG(addr) (*(volatile uint32_t *)(addr))
 
 /* Nested Vectored Interrupt Controller */
-#define CPU_NVIC_EN(x)         CPUREG(0xe000e100)
-#define CPU_NVIC_DIS(x)        CPUREG(0xe000e180)
-#define CPU_NVIC_UNPEND(x)     CPUREG(0xe000e280)
-#define CPU_NVIC_ISPR(x)       CPUREG(0xe000e200)
-#define CPU_NVIC_PRI(x)        CPUREG(0xe000e400 + 4 * (x))
+#define CPU_NVIC_EN(x) CPUREG(0xe000e100)
+#define CPU_NVIC_DIS(x) CPUREG(0xe000e180)
+#define CPU_NVIC_UNPEND(x) CPUREG(0xe000e280)
+#define CPU_NVIC_ISPR(x) CPUREG(0xe000e200)
+#define CPU_NVIC_PRI(x) CPUREG(0xe000e400 + 4 * (x))
 
 /* System Control Block */
-#define CPU_SCB_ICSR           CPUREG(0xe000ed04)
+#define CPU_SCB_ICSR CPUREG(0xe000ed04)
 
 /* SCB AIRCR : Application interrupt and reset control register */
-#define CPU_NVIC_APINT         CPUREG(0xe000ed0c)
-#define  CPU_NVIC_APINT_SYSRST  BIT(2)            /* System reset request */
-#define  CPU_NVIC_APINT_ENDIAN  BIT(15)           /* Endianness */
-#define  CPU_NVIC_APINT_KEY_RD  (0U)
-#define  CPU_NVIC_APINT_KEY_WR  (0x05FAU << 16)
+#define CPU_NVIC_APINT CPUREG(0xe000ed0c)
+#define CPU_NVIC_APINT_SYSRST BIT(2) /* System reset request */
+#define CPU_NVIC_APINT_ENDIAN BIT(15) /* Endianness */
+#define CPU_NVIC_APINT_KEY_RD (0U)
+#define CPU_NVIC_APINT_KEY_WR (0x05FAU << 16)
 /* SCB SCR : System Control Register */
-#define CPU_SCB_SYSCTRL        CPUREG(0xe000ed10)
-#define CPU_NVIC_CCR           CPUREG(0xe000ed14)
-#define CPU_NVIC_SHCSR2        CPUREG(0xe000ed1c)
-#define CPU_NVIC_SHCSR3        CPUREG(0xe000ed20)
+#define CPU_SCB_SYSCTRL CPUREG(0xe000ed10)
+#define CPU_NVIC_CCR CPUREG(0xe000ed14)
+#define CPU_NVIC_SHCSR2 CPUREG(0xe000ed1c)
+#define CPU_NVIC_SHCSR3 CPUREG(0xe000ed20)
 
 #define CPU_NVIC_CCR_UNALIGN_TRAP BIT(3)
 
 /* Bitfield values for EXC_RETURN. */
-#define EXC_RETURN_SPSEL_MASK	BIT(2)
-#define EXC_RETURN_SPSEL_MSP	0
-#define EXC_RETURN_SPSEL_PSP	BIT(2)
-#define EXC_RETURN_MODE_MASK	BIT(3)
-#define EXC_RETURN_MODE_HANDLER	0
-#define EXC_RETURN_MODE_THREAD	BIT(3)
+#define EXC_RETURN_SPSEL_MASK BIT(2)
+#define EXC_RETURN_SPSEL_MSP 0
+#define EXC_RETURN_SPSEL_PSP BIT(2)
+#define EXC_RETURN_MODE_MASK BIT(3)
+#define EXC_RETURN_MODE_HANDLER 0
+#define EXC_RETURN_MODE_THREAD BIT(3)
 
 /* Set up the cpu to detect faults */
 void cpu_init(void);
@@ -57,10 +58,16 @@ static inline void cpu_set_interrupt_priority(uint8_t irq, uint8_t priority)
 	if (priority > 3)
 		priority = 3;
 
-	CPU_NVIC_PRI(irq / 4) =
-		(CPU_NVIC_PRI(irq / 4) &
-		 ~(3 << prio_shift)) |
-		(priority << prio_shift);
+	CPU_NVIC_PRI(irq / 4) = (CPU_NVIC_PRI(irq / 4) & ~(3 << prio_shift)) |
+				(priority << prio_shift);
+}
+
+static inline void cpu_enter_suspend_mode(void)
+{
+	/* Preserve debug sessions by not suspending when connected */
+	if (!debugger_is_connected()) {
+		asm("wfi");
+	}
 }
 
 #endif /* __CROS_EC_CPU_H */
diff --git a/core/cortex-m0/ec.lds.S b/core/cortex-m0/ec.lds.S
index ce67760cf2..3c2076b9e4 100644
--- a/core/cortex-m0/ec.lds.S
+++ b/core/cortex-m0/ec.lds.S
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -189,6 +189,10 @@ SECTIONS
 		KEEP(*(.rodata.HOOK_USB_PD_CONNECT))
 		__hooks_usb_pd_connect_end = .;
 
+		__hooks_power_supply_change = .;
+		KEEP(*(.rodata.HOOK_POWER_SUPPLY_CHANGE))
+		__hooks_power_supply_change_end = .;
+
 		__deferred_funcs = .;
 		KEEP(*(.rodata.deferred))
 		__deferred_funcs_end = .;
@@ -291,6 +295,12 @@ SECTIONS
 		__data_end = .;
 
 		/*
+		 * _sbrk in newlib expects "end" symbol to point to start of
+		 * free memory.
+		 */
+		end = .;
+
+		/*
 		 * Shared memory buffer must be at the end of preallocated
 		 * RAM, so it can expand to use all the remaining RAM.
 		 */
diff --git a/core/cortex-m0/include/fpu.h b/core/cortex-m0/include/fpu.h
index 3acec557a7..1054f388b0 100644
--- a/core/cortex-m0/include/fpu.h
+++ b/core/cortex-m0/include/fpu.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,4 +8,4 @@
 #ifndef __CROS_EC_FPU_H
 #define __CROS_EC_FPU_H
 
-#endif  /* __CROS_EC_FPU_H */
+#endif /* __CROS_EC_FPU_H */
diff --git a/core/cortex-m0/init.S b/core/cortex-m0/init.S
index 6ccb75bbe8..58316e92d6 100644
--- a/core/cortex-m0/init.S
+++ b/core/cortex-m0/init.S
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/cortex-m0/irq_handler.h b/core/cortex-m0/irq_handler.h
index 302befe7a6..f2f6a220e4 100644
--- a/core/cortex-m0/irq_handler.h
+++ b/core/cortex-m0/irq_handler.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,25 +20,26 @@
  */
 #define DECLARE_IRQ(irq, routine, priority) DECLARE_IRQ_(irq, routine, priority)
 #ifdef CONFIG_TASK_PROFILING
-#define DECLARE_IRQ_(irq, routine, priority)                    \
-	static void routine(void);				\
-	void IRQ_HANDLER(irq)(void)				\
-	{							\
-		void *ret = __builtin_return_address(0);	\
-		task_start_irq_handler(ret);			\
-		routine();					\
-		task_end_irq_handler(ret);			\
-	}							\
-	const struct irq_priority __keep IRQ_PRIORITY(irq)	\
-	__attribute__((section(".rodata.irqprio")))		\
-			= {irq, priority}
+#define DECLARE_IRQ_(irq, routine, priority)                         \
+	static void routine(void);                                   \
+	void IRQ_HANDLER(irq)(void)                                  \
+	{                                                            \
+		void *ret = __builtin_return_address(0);             \
+		task_start_irq_handler(ret);                         \
+		routine();                                           \
+		task_end_irq_handler(ret);                           \
+	}                                                            \
+	const struct irq_priority __keep IRQ_PRIORITY(irq)           \
+		__attribute__((section(".rodata.irqprio"))) = { irq, \
+								priority }
 #else /* CONFIG_TASK_PROFILING */
 /* No Profiling : connect directly the IRQ vector */
-#define DECLARE_IRQ_(irq, routine, priority)                    \
-	static void __keep routine(void);			\
-	void IRQ_HANDLER(irq)(void) __attribute__((alias(STRINGIFY(routine))));\
-	const struct irq_priority __keep IRQ_PRIORITY(irq)	\
-	__attribute__((section(".rodata.irqprio")))		\
-			= {irq, priority}
+#define DECLARE_IRQ_(irq, routine, priority)                         \
+	static void __keep routine(void);                            \
+	void IRQ_HANDLER(irq)(void)                                  \
+		__attribute__((alias(STRINGIFY(routine))));          \
+	const struct irq_priority __keep IRQ_PRIORITY(irq)           \
+		__attribute__((section(".rodata.irqprio"))) = { irq, \
+								priority }
 #endif /* CONFIG_TASK_PROFILING */
-#endif  /* __CROS_EC_IRQ_HANDLER_H */
+#endif /* __CROS_EC_IRQ_HANDLER_H */
diff --git a/core/cortex-m0/mula.S b/core/cortex-m0/mula.S
index 02e617c328..7bb54263b4 100644
--- a/core/cortex-m0/mula.S
+++ b/core/cortex-m0/mula.S
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/cortex-m0/panic-internal.h b/core/cortex-m0/panic-internal.h
index 51c12f65b2..9f831495ff 100644
--- a/core/cortex-m0/panic-internal.h
+++ b/core/cortex-m0/panic-internal.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,4 +10,4 @@
 
 noreturn void exception_panic(void) __attribute__((naked));
 
-#endif  /* __CROS_EC_PANIC_INTERNAL_H */
+#endif /* __CROS_EC_PANIC_INTERNAL_H */
diff --git a/core/cortex-m0/panic.c b/core/cortex-m0/panic.c
index f1ee816c60..f20908eb7c 100644
--- a/core/cortex-m0/panic.c
+++ b/core/cortex-m0/panic.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,9 +19,8 @@
 /* Whether bus fault is ignored */
 static int bus_fault_ignored;
 
-
 /* Panic data goes at the end of RAM. */
-static struct panic_data * const pdata_ptr = PANIC_DATA_PTR;
+static struct panic_data *const pdata_ptr = PANIC_DATA_PTR;
 
 /* Preceded by stack, rounded down to nearest 64-bit-aligned boundary */
 static const uint32_t pstack_addr = ((uint32_t)pdata_ptr) & ~7;
@@ -101,7 +100,7 @@ void panic_data_print(const struct panic_data *pdata)
 	print_reg(12, sregs, CORTEX_PANIC_FRAME_REGISTER_R12);
 	print_reg(13, lregs,
 		  in_handler ? CORTEX_PANIC_REGISTER_MSP :
-				     CORTEX_PANIC_REGISTER_PSP);
+			       CORTEX_PANIC_REGISTER_PSP);
 	print_reg(14, sregs, CORTEX_PANIC_FRAME_REGISTER_LR);
 	print_reg(15, sregs, CORTEX_PANIC_FRAME_REGISTER_PC);
 }
@@ -126,10 +125,9 @@ void __keep report_panic(void)
 	sp = is_frame_in_handler_stack(
 		     pdata->cm.regs[CORTEX_PANIC_REGISTER_LR]) ?
 		     pdata->cm.regs[CORTEX_PANIC_REGISTER_MSP] :
-			   pdata->cm.regs[CORTEX_PANIC_REGISTER_PSP];
+		     pdata->cm.regs[CORTEX_PANIC_REGISTER_PSP];
 	/* If stack is valid, copy exception frame to pdata */
-	if ((sp & 3) == 0 &&
-	    sp >= CONFIG_RAM_BASE &&
+	if ((sp & 3) == 0 && sp >= CONFIG_RAM_BASE &&
 	    sp <= CONFIG_RAM_BASE + CONFIG_RAM_SIZE - 8 * sizeof(uint32_t)) {
 		const uint32_t *sregs = (const uint32_t *)sp;
 		int i;
@@ -162,38 +160,41 @@ void exception_panic(void)
 		"mov r5, lr\n"
 		"stmia %[pregs]!, {r1-r5}\n"
 		"mov sp, %[pstack]\n"
-		"bl report_panic\n" : :
-			[pregs] "r" (pdata_ptr->cm.regs),
-			[pstack] "r" (pstack_addr) :
-			/* Constraints protecting these from being clobbered.
-			 * Gcc should be using r0 & r12 for pregs and pstack. */
-			"r1", "r2", "r3", "r4", "r5", "r6",
-		/* clang warns that we're clobbering a reserved register:
-		 * inline asm clobber list contains reserved registers: R7
-		 * [-Werror,-Winline-asm]. The intent of the clobber list is
-		 * to force pregs and pstack to be in R0 and R12, which
-		 * still holds.
-		 */
+		"bl report_panic\n"
+		:
+		: [pregs] "r"(pdata_ptr->cm.regs), [pstack] "r"(pstack_addr)
+		:
+		/* Constraints protecting these from being clobbered.
+		 * Gcc should be using r0 & r12 for pregs and pstack. */
+		"r1", "r2", "r3", "r4", "r5", "r6",
+	/* clang warns that we're clobbering a reserved register:
+	 * inline asm clobber list contains reserved registers: R7
+	 * [-Werror,-Winline-asm]. The intent of the clobber list is
+	 * to force pregs and pstack to be in R0 and R12, which
+	 * still holds.
+	 */
 #ifndef __clang__
-			"r7",
+		"r7",
 #endif
-			"r8", "r9", "r10", "r11", "cc", "memory"
-		);
+		"r8", "r9", "r10", "r11", "cc", "memory");
 }
 
 #ifdef CONFIG_SOFTWARE_PANIC
 void software_panic(uint32_t reason, uint32_t info)
 {
-	__asm__("mov " STRINGIFY(SOFTWARE_PANIC_INFO_REG) ", %0\n"
-		"mov " STRINGIFY(SOFTWARE_PANIC_REASON_REG) ", %1\n"
-		"bl exception_panic\n"
-		: : "r"(info), "r"(reason));
+	__asm__("mov " STRINGIFY(
+			SOFTWARE_PANIC_INFO_REG) ", %0\n"
+						 "mov " STRINGIFY(
+							 SOFTWARE_PANIC_REASON_REG) ", %1\n"
+										    "bl exception_panic\n"
+		:
+		: "r"(info), "r"(reason));
 	__builtin_unreachable();
 }
 
 void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
 {
-	struct panic_data * const pdata = get_panic_data_write();
+	struct panic_data *const pdata = get_panic_data_write();
 	uint32_t *lregs;
 
 	lregs = pdata->cm.regs;
@@ -213,7 +214,7 @@ void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
 
 void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception)
 {
-	struct panic_data * const pdata = panic_get_data();
+	struct panic_data *const pdata = panic_get_data();
 	uint32_t *lregs;
 
 	if (pdata && pdata->struct_version == 2) {
diff --git a/core/cortex-m0/switch.S b/core/cortex-m0/switch.S
index a75daad939..4914788460 100644
--- a/core/cortex-m0/switch.S
+++ b/core/cortex-m0/switch.S
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/cortex-m0/task.c b/core/cortex-m0/task.c
index 52a6921ae6..b34e920e09 100644
--- a/core/cortex-m0/task.c
+++ b/core/cortex-m0/task.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,6 +6,7 @@
 /* Task scheduling / events module for Chrome EC operating system */
 
 #include "atomic.h"
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
 #include "cpu.h"
@@ -21,10 +22,10 @@ typedef union {
 		 * Note that sp must be the first element in the task struct
 		 * for __switchto() to work.
 		 */
-		uint32_t sp;       /* Saved stack pointer for context switch */
-		atomic_t events;   /* Bitmaps of received events */
-		uint64_t runtime;  /* Time spent in task */
-		uint32_t *stack;   /* Start of stack */
+		uint32_t sp; /* Saved stack pointer for context switch */
+		atomic_t events; /* Bitmaps of received events */
+		uint64_t runtime; /* Time spent in task */
+		uint32_t *stack; /* Start of stack */
 	};
 } task_;
 
@@ -40,12 +41,10 @@ CONFIG_CTS_TASK_LIST
 #undef TASK
 
 /* Task names for easier debugging */
-#define TASK(n, r, d, s)  #n,
-static const char * const task_names[] = {
+#define TASK(n, r, d, s) #n,
+static const char *const task_names[] = {
 	"<< idle >>",
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
-	CONFIG_CTS_TASK_LIST
+	CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST CONFIG_CTS_TASK_LIST
 };
 #undef TASK
 
@@ -55,12 +54,12 @@ static uint64_t task_start_time; /* Time task scheduling started */
  * We only keep 32-bit values for exception start/end time, to avoid
  * accounting errors when we service interrupt when the timer wraps around.
  */
-static uint32_t exc_start_time;  /* Time of task->exception transition */
-static uint32_t exc_end_time;    /* Time of exception->task transition */
-static uint64_t exc_total_time;  /* Total time in exceptions */
-static uint32_t svc_calls;       /* Number of service calls */
-static uint32_t task_switches;   /* Number of times active task changed */
-static uint32_t irq_dist[CONFIG_IRQ_COUNT];  /* Distribution of IRQ calls */
+static uint32_t exc_start_time; /* Time of task->exception transition */
+static uint32_t exc_end_time; /* Time of exception->task transition */
+static uint64_t exc_total_time; /* Total time in exceptions */
+static uint32_t svc_calls; /* Number of service calls */
+static uint32_t task_switches; /* Number of times active task changed */
+static uint32_t irq_dist[CONFIG_IRQ_COUNT]; /* Distribution of IRQ calls */
 #endif
 
 extern int __task_start(int *task_stack_ready);
@@ -74,7 +73,7 @@ void __idle(void)
 		 * Wait for the next irq event.  This stops the CPU clock
 		 * (sleep / deep sleep, depending on chip config).
 		 */
-		asm("wfi");
+		cpu_enter_suspend_mode();
 	}
 }
 #endif /* !CONFIG_LOW_POWER_IDLE */
@@ -89,20 +88,19 @@ static void task_exit_trap(void)
 }
 
 /* Startup parameters for all tasks. */
-#define TASK(n, r, d, s)  {	\
-	.r0 = (uint32_t)d,	\
-	.pc = (uint32_t)r,	\
-	.stack_size = s,	\
-},
+#define TASK(n, r, d, s)           \
+	{                          \
+		.r0 = (uint32_t)d, \
+		.pc = (uint32_t)r, \
+		.stack_size = s,   \
+	},
 static const struct {
 	uint32_t r0;
 	uint32_t pc;
 	uint16_t stack_size;
 } tasks_init[] = {
 	TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
-	CONFIG_CTS_TASK_LIST
+		CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST CONFIG_CTS_TASK_LIST
 };
 #undef TASK
 
@@ -112,15 +110,11 @@ static task_ tasks[TASK_ID_COUNT];
 BUILD_ASSERT(TASK_ID_COUNT <= sizeof(unsigned) * 8);
 BUILD_ASSERT(TASK_ID_COUNT < (1 << (sizeof(task_id_t) * 8)));
 
-
 /* Stacks for all tasks */
-#define TASK(n, r, d, s)  + s
-uint8_t task_stacks[0
-		    TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
-		    CONFIG_TASK_LIST
-		    CONFIG_TEST_TASK_LIST
-		    CONFIG_CTS_TASK_LIST
-] __aligned(8);
+#define TASK(n, r, d, s) +s
+uint8_t task_stacks[0 TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
+			    CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST
+				    CONFIG_CTS_TASK_LIST] __aligned(8);
 
 #undef TASK
 
@@ -144,7 +138,7 @@ static atomic_t tasks_ready = BIT(TASK_ID_HOOKS);
  */
 static atomic_t tasks_enabled = BIT(TASK_ID_HOOKS) | BIT(TASK_ID_IDLE);
 
-static int start_called;  /* Has task swapping started */
+static int start_called; /* Has task swapping started */
 
 static inline task_ *__task_id_to_ptr(task_id_t id)
 {
@@ -166,7 +160,7 @@ inline bool is_interrupt_enabled(void)
 	int primask;
 
 	/* Interrupts are enabled when PRIMASK bit is 0 */
-	asm("mrs %0, primask":"=r"(primask));
+	asm("mrs %0, primask" : "=r"(primask));
 
 	return !(primask & 0x1);
 }
@@ -184,7 +178,7 @@ static inline int get_interrupt_context(void)
 {
 	int ret;
 	asm("mrs %0, ipsr\n" : "=r"(ret)); /* read exception number */
-	return ret & 0x1ff;                /* exception bits are the 9 LSB */
+	return ret & 0x1ff; /* exception bits are the 9 LSB */
 }
 #endif
 
@@ -211,7 +205,7 @@ int task_start_called(void)
 /**
  * Scheduling system call
  */
-task_  __attribute__((noinline)) *__svc_handler(int desched, task_id_t resched)
+task_ __attribute__((noinline)) * __svc_handler(int desched, task_id_t resched)
 {
 	task_ *current, *next;
 #ifdef CONFIG_TASK_PROFILING
@@ -304,9 +298,8 @@ void task_start_irq_handler(void *excep_return)
 	 * Continue iff the tasks are ready and we are not called from another
 	 * exception (as the time accouting is done in the outer irq).
 	 */
-	if (!start_called
-	    || (((uint32_t)excep_return & EXC_RETURN_MODE_MASK)
-		== EXC_RETURN_MODE_HANDLER))
+	if (!start_called || (((uint32_t)excep_return & EXC_RETURN_MODE_MASK) ==
+			      EXC_RETURN_MODE_HANDLER))
 		return;
 
 	exc_start_time = t;
@@ -324,9 +317,8 @@ void task_end_irq_handler(void *excep_return)
 	 * Continue iff the tasks are ready and we are not called from another
 	 * exception (as the time accouting is done in the outer irq).
 	 */
-	if (!start_called
-	    || (((uint32_t)excep_return & EXC_RETURN_MODE_MASK)
-		== EXC_RETURN_MODE_HANDLER))
+	if (!start_called || (((uint32_t)excep_return & EXC_RETURN_MODE_MASK) ==
+			      EXC_RETURN_MODE_HANDLER))
 		return;
 
 	/* Track time in interrupts */
@@ -584,7 +576,7 @@ void task_print_list(void)
 	}
 }
 
-static int command_task_info(int argc, char **argv)
+static int command_task_info(int argc, const char **argv)
 {
 #ifdef CONFIG_TASK_PROFILING
 	int total = 0;
@@ -613,12 +605,10 @@ static int command_task_info(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(taskinfo, command_task_info,
-			NULL,
-			"Print task info");
+DECLARE_CONSOLE_COMMAND(taskinfo, command_task_info, NULL, "Print task info");
 
 #ifdef CONFIG_CMD_TASKREADY
-static int command_task_ready(int argc, char **argv)
+static int command_task_ready(int argc, const char **argv)
 {
 	if (argc < 2) {
 		ccprintf("tasks_ready: 0x%08x\n", (int)tasks_ready);
@@ -630,8 +620,7 @@ static int command_task_ready(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(taskready, command_task_ready,
-			"[setmask]",
+DECLARE_CONSOLE_COMMAND(taskready, command_task_ready, "[setmask]",
 			"Print/set ready tasks");
 #endif
 
@@ -657,10 +646,10 @@ void task_pre_init(void)
 		tasks[i].sp = (uint32_t)sp;
 
 		/* Initial context on stack (see __switchto()) */
-		sp[8] = tasks_init[i].r0;           /* r0 */
-		sp[13] = (uint32_t)task_exit_trap;  /* lr */
-		sp[14] = tasks_init[i].pc;          /* pc */
-		sp[15] = 0x01000000;                /* psr */
+		sp[8] = tasks_init[i].r0; /* r0 */
+		sp[13] = (uint32_t)task_exit_trap; /* lr */
+		sp[14] = tasks_init[i].pc; /* pc */
+		sp[15] = 0x01000000; /* psr */
 
 		/* Fill unused stack; also used to detect stack overflow. */
 		for (sp = stack_next; sp < (uint32_t *)tasks[i].sp; sp++)
diff --git a/core/cortex-m0/thumb_case.S b/core/cortex-m0/thumb_case.S
index 5628361a94..9148a33427 100644
--- a/core/cortex-m0/thumb_case.S
+++ b/core/cortex-m0/thumb_case.S
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/cortex-m0/toolchain.mk b/core/cortex-m0/toolchain.mk
new file mode 100644
index 0000000000..6b5f07ccf6
--- /dev/null
+++ b/core/cortex-m0/toolchain.mk
@@ -0,0 +1,15 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+ifeq ($(cc-name),gcc)
+# coreboot sdk
+CROSS_COMPILE_ARM_DEFAULT:=/opt/coreboot-sdk/bin/arm-eabi-
+else
+# llvm sdk
+CROSS_COMPILE_ARM_DEFAULT:=arm-none-eabi-
+endif
+
+$(call set-option,CROSS_COMPILE,\
+	$(CROSS_COMPILE_arm),\
+	$(CROSS_COMPILE_ARM_DEFAULT))
diff --git a/core/cortex-m0/vecttable.c b/core/cortex-m0/vecttable.c
index 5c69f6d6c8..3871a30055 100644
--- a/core/cortex-m0/vecttable.c
+++ b/core/cortex-m0/vecttable.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -13,7 +13,7 @@
 #include "config.h"
 #include "panic-internal.h"
 #include "task.h"
-#endif  /* __INIT */
+#endif /* __INIT */
 
 typedef void (*func)(void);
 
@@ -30,7 +30,7 @@ void __attribute__((naked)) default_handler(void)
 	 * restricting the relative placement of default_handler and
 	 * exception_panic.
 	 */
-	asm volatile("bx %0\n" : : "r" (exception_panic));
+	asm volatile("bx %0\n" : : "r"(exception_panic));
 }
 
 #define table(x) x
@@ -38,8 +38,8 @@ void __attribute__((naked)) default_handler(void)
 /* Note: the alias target must be defined in this translation unit */
 #define weak_with_default __attribute__((used, weak, alias("default_handler")))
 
-#define vec(name) extern void weak_with_default name ## _handler(void);
-#define irq(num) vec(irq_ ## num)
+#define vec(name) extern void weak_with_default name##_handler(void);
+#define irq(num) vec(irq_##num)
 
 #define item(name) extern void name(void);
 #define null
@@ -47,12 +47,6 @@ void __attribute__((naked)) default_handler(void)
 extern void stack_end(void); /* not technically correct, it's just a pointer */
 extern void reset(void);
 
-#pragma GCC diagnostic push
-#if __GNUC__ >= 8
-#pragma GCC diagnostic ignored "-Wattribute-alias"
-#endif
-#pragma GCC diagnostic pop
-
 #endif /* PASS 1 */
 
 #if PASS == 2
@@ -77,69 +71,28 @@ extern void reset(void);
 #pragma clang diagnostic ignored "-Winitializer-overrides"
 #endif /* __clang__ */
 
-#define table(x)							     \
-	const func vectors[] __attribute__((section(".text.vecttable"))) = { \
-		x							     \
-		[IRQ_UNUSED_OFFSET] = null				     \
-	}
+#define table(x)                             \
+	const func vectors[] __attribute__(( \
+		section(".text.vecttable"))) = { x[IRQ_UNUSED_OFFSET] = null }
 
-#define vec(name) name ## _handler,
-#define irq(num) [num < CONFIG_IRQ_COUNT ? num + IRQ_OFFSET : IRQ_UNUSED_OFFSET] = vec(irq_ ## num)
+#define vec(name) name##_handler,
+#define irq(num)                                                          \
+	[num < CONFIG_IRQ_COUNT ? num + IRQ_OFFSET : IRQ_UNUSED_OFFSET] = \
+		vec(irq_##num)
 
 #define item(name) name,
 #define null (void *)0,
 #endif /* PASS 2 */
 
-table(
-	item(stack_end)
-	item(reset)
-	vec(nmi)
-	vec(hard_fault)
-	vec(mpu_fault)
-	vec(bus_fault)
-	vec(usage_fault)
-	null
-	null
-	null
-	null
-	vec(svc)
-	vec(debug)
-	null
-	vec(pendsv)
-	vec(sys_tick)
-	irq(0)
-	irq(1)
-	irq(2)
-	irq(3)
-	irq(4)
-	irq(5)
-	irq(6)
-	irq(7)
-	irq(8)
-	irq(9)
-	irq(10)
-	irq(11)
-	irq(12)
-	irq(13)
-	irq(14)
-	irq(15)
-	irq(16)
-	irq(17)
-	irq(18)
-	irq(19)
-	irq(20)
-	irq(21)
-	irq(22)
-	irq(23)
-	irq(24)
-	irq(25)
-	irq(26)
-	irq(27)
-	irq(28)
-	irq(29)
-	irq(30)
-	irq(31)
-);
+table(item(stack_end) item(reset) vec(nmi) vec(hard_fault) vec(mpu_fault) vec(
+	bus_fault) vec(usage_fault) null null null null vec(svc) vec(debug)
+	      null vec(pendsv) vec(sys_tick) irq(0) irq(1) irq(2) irq(3) irq(4)
+		      irq(5) irq(6) irq(7) irq(8) irq(9) irq(10) irq(11) irq(12)
+			      irq(13) irq(14) irq(15) irq(16) irq(17) irq(18)
+				      irq(19) irq(20) irq(21) irq(22) irq(23)
+					      irq(24) irq(25) irq(26) irq(27)
+						      irq(28) irq(29) irq(30)
+							      irq(31));
 
 #if PASS == 2
 #ifdef __clang__
diff --git a/core/cortex-m0/watchdog.c b/core/cortex-m0/watchdog.c
index 9961922ee5..b4d5c086f0 100644
--- a/core/cortex-m0/watchdog.c
+++ b/core/cortex-m0/watchdog.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/core/host/atomic.h b/core/host/atomic.h
index a8d6882d0e..0d27e1bc6f 100644
--- a/core/host/atomic.h
+++ b/core/host/atomic.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -40,4 +40,4 @@ static inline atomic_val_t atomic_and(atomic_t *addr, atomic_val_t bits)
 {
 	return __atomic_fetch_and(addr, bits, __ATOMIC_SEQ_CST);
 }
-#endif  /* __CROS_EC_ATOMIC_H */
+#endif /* __CROS_EC_ATOMIC_H */
diff --git a/core/host/build.mk b/core/host/build.mk
index 503aa5538a..3995e7e4e4 100644
--- a/core/host/build.mk
+++ b/core/host/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
+# Copyright 2013 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/core/host/cpu.h b/core/host/cpu.h
index d990e06afa..f63e0b9d23 100644
--- a/core/host/cpu.h
+++ b/core/host/cpu.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,6 +8,8 @@
 #ifndef __CROS_EC_CPU_H
 #define __CROS_EC_CPU_H
 
-static inline void cpu_init(void) { }
+static inline void cpu_init(void)
+{
+}
 
 #endif /* __CROS_EC_CPU_H */
diff --git a/core/host/disabled.c b/core/host/disabled.c
index 759c215ebd..8f05e5e1d6 100644
--- a/core/host/disabled.c
+++ b/core/host/disabled.c
@@ -1,10 +1,13 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Disabled functions */
 
-#define DISABLED(proto) proto { }
+#define DISABLED(proto) \
+	proto           \
+	{               \
+	}
 
 DISABLED(void clock_init(void));
diff --git a/core/host/host_exe.lds b/core/host/host_exe.lds
index ab8d352ecc..b4c94c12ff 100644
--- a/core/host/host_exe.lds
+++ b/core/host/host_exe.lds
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -113,6 +113,10 @@ SECTIONS {
 		KEEP(*(.rodata.HOOK_USB_PD_CONNECT))
 		__hooks_usb_pd_connect_end = .;
 
+		__hooks_power_supply_change = .;
+		KEEP(*(.rodata.HOOK_POWER_SUPPLY_CHANGE))
+		__hooks_power_supply_change_end = .;
+
 		__deferred_funcs = .;
 		*(.rodata.deferred)
 		__deferred_funcs_end = .;
diff --git a/core/host/host_task.h b/core/host/host_task.h
index 30cd2ff594..82b33f96c5 100644
--- a/core/host/host_task.h
+++ b/core/host/host_task.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -34,4 +34,4 @@ void task_register_interrupt(void);
  */
 pid_t getpid(void);
 
-#endif  /* __CROS_EC_HOST_TASK_H */
+#endif /* __CROS_EC_HOST_TASK_H */
diff --git a/core/host/irq_handler.h b/core/host/irq_handler.h
index 17e3df52d9..8bbf596a57 100644
--- a/core/host/irq_handler.h
+++ b/core/host/irq_handler.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,16 +15,16 @@
  * Macro to connect the interrupt handler "routine" to the irq number "irq" and
  * ensure it is enabled in the interrupt controller with the right priority.
  */
-#define DECLARE_IRQ(irq, routine, priority)                     \
-	static void __keep routine(void);			\
-	void IRQ_HANDLER(irq)(void)				\
-	{							\
-		void *ret = __builtin_return_address(0);	\
-		task_start_irq_handler(ret);			\
-		routine();					\
-		task_resched_if_needed(ret);			\
-	}							\
-	const struct irq_priority __keep IRQ_PRIORITY(irq)	\
-	__attribute__((section(".rodata.irqprio")))		\
-			= {irq, priority}
-#endif  /* __CROS_EC_IRQ_HANDLER_H */
+#define DECLARE_IRQ(irq, routine, priority)                          \
+	static void __keep routine(void);                            \
+	void IRQ_HANDLER(irq)(void)                                  \
+	{                                                            \
+		void *ret = __builtin_return_address(0);             \
+		task_start_irq_handler(ret);                         \
+		routine();                                           \
+		task_resched_if_needed(ret);                         \
+	}                                                            \
+	const struct irq_priority __keep IRQ_PRIORITY(irq)           \
+		__attribute__((section(".rodata.irqprio"))) = { irq, \
+								priority }
+#endif /* __CROS_EC_IRQ_HANDLER_H */
diff --git a/core/host/main.c b/core/host/main.c
index ed7032eb63..1af5fa928c 100644
--- a/core/host/main.c
+++ b/core/host/main.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,7 +19,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 const char *__prog_name;
 
@@ -85,7 +85,7 @@ int LLVMFuzzerTestOneInput(const uint8_t *data, size_t size)
 	 * We lose the program name as LLVM fuzzer takes over main function:
 	 * make up one.
 	 */
-	static const char *name = STRINGIFY(PROJECT)".exe";
+	static const char *name = STRINGIFY(PROJECT) ".exe";
 
 	if (!initialized) {
 		__prog_name = name;
diff --git a/core/host/panic.c b/core/host/panic.c
index 7b0829989d..ed1994f82e 100644
--- a/core/host/panic.c
+++ b/core/host/panic.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,8 @@
 void panic_assert_fail(const char *msg, const char *func, const char *fname,
 		       int linenum)
 {
-	fprintf(stderr, "ASSERTION FAIL: %s:%d:%s - %s\n",
-		fname, linenum, func, msg);
+	fprintf(stderr, "ASSERTION FAIL: %s:%d:%s - %s\n", fname, linenum, func,
+		msg);
 	task_dump_trace();
 
 	puts("Fail!"); /* Inform test runner */
diff --git a/core/host/stack_trace.c b/core/host/stack_trace.c
index adef66dd44..f8918b1c57 100644
--- a/core/host/stack_trace.c
+++ b/core/host/stack_trace.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -44,9 +44,8 @@ static void __attribute__((noinline)) _task_dump_trace_impl(int offset)
 
 	for (i = 0; i < sz - offset; ++i) {
 		fprintf(stderr, "#%-2d %s\n", i, messages[i]);
-		/* %p is correct (as opposed to %pP) since this is the host */
-		sprintf(buf, "addr2line %p -e %s",
-			trace[i + offset], __get_prog_name());
+		sprintf(buf, "addr2line %p -e %s", trace[i + offset],
+			__get_prog_name());
 		file = popen(buf, "r");
 		if (file) {
 			nb = fread(buf, 1, sizeof(buf) - 1, file);
@@ -77,8 +76,8 @@ static void __attribute__((noinline)) _task_dump_trace_dispatch(int sig)
 	} else if (in_interrupt_context()) {
 		fprintf(stderr, "Stack trace of ISR:\n");
 	} else {
-		fprintf(stderr, "Stack trace of task %d (%s):\n",
-				running, task_get_name(running));
+		fprintf(stderr, "Stack trace of task %d (%s):\n", running,
+			task_get_name(running));
 	}
 
 	if (need_dispatch) {
diff --git a/core/host/task.c b/core/host/task.c
index f8f8dfb661..3ba241198b 100644
--- a/core/host/task.c
+++ b/core/host/task.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -96,22 +96,18 @@ void _run_test(void *d)
 	run_test(0, NULL);
 }
 
-#define TASK(n, r, d, s) {r, d},
+#define TASK(n, r, d, s) { r, d },
 const struct task_args task_info[TASK_ID_COUNT] = {
-	{__idle, NULL},
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
-	CONFIG_CTS_TASK_LIST
-	{_run_test, NULL},
+	{ __idle, NULL },
+	CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST CONFIG_CTS_TASK_LIST{ _run_test,
+								     NULL },
 };
 #undef TASK
 
 #define TASK(n, r, d, s) #n,
-static const char * const task_names[] = {
+static const char *const task_names[] = {
 	"<< idle >>",
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
-	CONFIG_CTS_TASK_LIST
+	CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST CONFIG_CTS_TASK_LIST
 	"<< test runner >>",
 };
 #undef TASK
@@ -319,14 +315,13 @@ void task_print_list(void)
 	}
 }
 
-static int command_task_info(int argc, char **argv)
+static int command_task_info(int argc, const char **argv)
 {
 	task_print_list();
 
 	return EC_SUCCESS;
 }
-DECLARE_SAFE_CONSOLE_COMMAND(taskinfo, command_task_info,
-			     NULL,
+DECLARE_SAFE_CONSOLE_COMMAND(taskinfo, command_task_info, NULL,
 			     "Print task info");
 
 static void _wait_for_task_started(int can_sleep)
@@ -519,8 +514,8 @@ int task_start(void)
 	 */
 	pthread_mutex_lock(&interrupt_lock);
 
-	pthread_create(&interrupt_thread, NULL,
-		       _task_int_generator_start, NULL);
+	pthread_create(&interrupt_thread, NULL, _task_int_generator_start,
+		       NULL);
 
 	/*
 	 * Tell the hooks task to continue so that it can call back to enable
@@ -557,7 +552,6 @@ static void task_enable_all_tasks_callback(void)
 		pthread_mutex_unlock(&interrupt_lock);
 		pthread_cond_wait(&scheduler_cond, &run_lock);
 	}
-
 }
 
 void task_enable_all_tasks(void)
diff --git a/core/host/timer.c b/core/host/timer.c
index 3c3695cad4..66f047cd4d 100644
--- a/core/host/timer.c
+++ b/core/host/timer.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,6 +8,7 @@
 #include <stdint.h>
 #include <stdio.h>
 
+#include "builtin/assert.h"
 #include "task.h"
 #include "test_util.h"
 #include "timer.h"
@@ -90,15 +91,12 @@ int timestamp_expired(timestamp_t deadline, const timestamp_t *now)
 
 void timer_init(void)
 {
-
 	if (!time_set) {
 		/*
 		 * Start the timer just before the 64-bit rollover to try
 		 * and catch 32-bit rollover/truncation bugs.
 		 */
-		timestamp_t ts = {
-			.val = 0xFFFFFFF0
-		};
+		timestamp_t ts = { .val = 0xFFFFFFF0 };
 
 		force_time(ts);
 	}
diff --git a/core/host/toolchain.mk b/core/host/toolchain.mk
new file mode 100644
index 0000000000..168d0e24c2
--- /dev/null
+++ b/core/host/toolchain.mk
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CROSS_COMPILE_HOST_DEFAULT:=x86_64-pc-linux-gnu-
+
+$(call set-option,CROSS_COMPILE,\
+	$(CROSS_COMPILE_host),\
+	$(CROSS_COMPILE_HOST_DEFAULT))
diff --git a/core/minute-ia/atomic.h b/core/minute-ia/atomic.h
index dbcd04b7de..e722d799c8 100644
--- a/core/minute-ia/atomic.h
+++ b/core/minute-ia/atomic.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,13 +13,13 @@
 #include "util.h"
 
 static inline int bool_compare_and_swap_u32(uint32_t *var, uint32_t old_value,
-		uint32_t new_value)
+					    uint32_t new_value)
 {
 	uint32_t _old_value = old_value;
 
 	__asm__ __volatile__(ASM_LOCK_PREFIX "cmpxchgl %2, %1"
-			     : "=a" (old_value), "+m" (*var)
-			     : "r" (new_value), "0" (old_value)
+			     : "=a"(old_value), "+m"(*var)
+			     : "r"(new_value), "0"(old_value)
 			     : "memory");
 
 	return (_old_value == old_value);
@@ -65,4 +65,4 @@ static inline atomic_val_t atomic_clear(atomic_t *addr)
 	return __atomic_exchange_n(addr, 0, __ATOMIC_SEQ_CST);
 }
 
-#endif  /* __CROS_EC_ATOMIC_H */
+#endif /* __CROS_EC_ATOMIC_H */
diff --git a/core/minute-ia/build.mk b/core/minute-ia/build.mk
index b51512c16e..cd92c5618f 100644
--- a/core/minute-ia/build.mk
+++ b/core/minute-ia/build.mk
@@ -1,15 +1,11 @@
 # -*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
 # Minute-IA core build
 #
 
-# Select Minute-IA bare-metal toolchain
-$(call set-option,CROSS_COMPILE,$(CROSS_COMPILE_i386),\
-	/opt/coreboot-sdk/bin/i386-elf-)
-
 # FPU compilation flags
 CFLAGS_FPU-$(CONFIG_FPU)=
 
diff --git a/core/minute-ia/config_core.h b/core/minute-ia/config_core.h
index 47121642a4..1dce51720d 100644
--- a/core/minute-ia/config_core.h
+++ b/core/minute-ia/config_core.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -29,6 +29,6 @@
 /*
  * Flag indicates the task uses FPU H/W
  */
-#define MIA_TASK_FLAG_USE_FPU                   0x00000001
+#define MIA_TASK_FLAG_USE_FPU 0x00000001
 
 #endif /* __CROS_EC_CONFIG_CORE_H */
diff --git a/core/minute-ia/cpu.c b/core/minute-ia/cpu.c
index cef39fe1ce..0157fec90b 100644
--- a/core/minute-ia/cpu.c
+++ b/core/minute-ia/cpu.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -7,7 +7,6 @@
 
 #include <cpu.h>
 
-
 void cpu_init(void)
 {
 	/* Nothing to do now */
diff --git a/core/minute-ia/cpu.h b/core/minute-ia/cpu.h
index 09eb50e4ca..bf5f3c5bbd 100644
--- a/core/minute-ia/cpu.h
+++ b/core/minute-ia/cpu.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,6 +8,5 @@
 #ifndef __CROS_EC_CPU_H
 #define __CROS_EC_CPU_H
 
-
 void cpu_init(void);
-#endif	/* __CROS_EC_CPU_H */
+#endif /* __CROS_EC_CPU_H */
diff --git a/core/minute-ia/ec.lds.S b/core/minute-ia/ec.lds.S
index beda1dbfae..be3e0fbf2e 100644
--- a/core/minute-ia/ec.lds.S
+++ b/core/minute-ia/ec.lds.S
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -156,6 +156,10 @@ SECTIONS
 		KEEP(*(.rodata.HOOK_USB_PD_CONNECT))
 		__hooks_usb_pd_connect_end = .;
 
+		__hooks_power_supply_change = .;
+		KEEP(*(.rodata.HOOK_POWER_SUPPLY_CHANGE))
+		__hooks_power_supply_change_end = .;
+
 		__deferred_funcs = .;
 		KEEP(*(.rodata.deferred))
 		__deferred_funcs_end = .;
@@ -216,6 +220,12 @@ SECTIONS
 		 __bss_end = .;
 		 __bss_size_words = ABSOLUTE((__bss_end - __bss_start) / 4);
 
+		 /*
+		 * _sbrk in newlib expects "end" symbol to point to start of
+		 * free memory.
+		 */
+		end = .;
+
 		/*
 		 * Shared memory buffer must be at the end of
 		 * preallocated RAM, so it can expand to use all the
diff --git a/core/minute-ia/ia_structs.h b/core/minute-ia/ia_structs.h
index 29bbb6c005..83214e2c1b 100644
--- a/core/minute-ia/ia_structs.h
+++ b/core/minute-ia/ia_structs.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,7 +10,6 @@
 
 #include "common.h"
 
-
 /**
  * IA32/x86 architecture related data structure definitions.
  * including: Global Descriptor Table (GDT), Local Descriptor Table (LDT),
@@ -24,16 +23,16 @@
 struct gdt_entry {
 	union {
 		struct {
-			uint32_t dword_lo;	/* lower dword */
-			uint32_t dword_up;	/* upper dword */
+			uint32_t dword_lo; /* lower dword */
+			uint32_t dword_up; /* upper dword */
 		};
 		struct {
-			uint16_t limit_lw;	/* limit (0:15) */
-			uint16_t base_addr_lw;	/* base address (0:15) */
-			uint8_t base_addr_mb;	/* base address (16:23) */
-			uint8_t flags;		/* flags */
-			uint8_t limit_ub;	/* limit (16:19) */
-			uint8_t base_addr_ub;	/* base address (24:31) */
+			uint16_t limit_lw; /* limit (0:15) */
+			uint16_t base_addr_lw; /* base address (0:15) */
+			uint8_t base_addr_mb; /* base address (16:23) */
+			uint8_t flags; /* flags */
+			uint8_t limit_ub; /* limit (16:19) */
+			uint8_t base_addr_ub; /* base address (24:31) */
 		};
 	};
 
@@ -43,32 +42,32 @@ typedef struct gdt_entry ldt_entry;
 
 /* GDT header */
 struct gdt_header {
-	uint16_t limit;			/* GDT limit size */
-	struct gdt_entry *entries;	/* pointer to GDT entries */
+	uint16_t limit; /* GDT limit size */
+	struct gdt_entry *entries; /* pointer to GDT entries */
 } __packed;
 
 /* IDT entry descriptor */
 struct idt_entry {
 	union {
 		struct {
-			uint32_t dword_lo;	/* lower dword */
-			uint32_t dword_up;	/* upper dword */
+			uint32_t dword_lo; /* lower dword */
+			uint32_t dword_up; /* upper dword */
 		};
 
 		struct {
-			uint16_t offset_lw;	/* offset (0:15) */
-			uint16_t seg_selector;	/* segment selector */
-			uint8_t zero;		/* must be set to zero */
-			uint8_t flags;		/* flags */
-			uint16_t offset_uw;	/* offset (16:31) */
+			uint16_t offset_lw; /* offset (0:15) */
+			uint16_t seg_selector; /* segment selector */
+			uint8_t zero; /* must be set to zero */
+			uint8_t flags; /* flags */
+			uint16_t offset_uw; /* offset (16:31) */
 		};
 	};
 } __packed;
 
 /* IDT header */
 struct idt_header {
-	uint16_t limit;			/* IDT limit size */
-	struct idt_entry *entries;	/* pointer to IDT entries */
+	uint16_t limit; /* IDT limit size */
+	struct idt_entry *entries; /* pointer to IDT entries */
 } __packed;
 
 /* TSS entry descriptor */
@@ -117,22 +116,22 @@ struct tss_entry {
 #endif
 
 /* code segment flag,  E/R, Present = 1, DPL = 0, Acesssed = 1 */
-#define GDT_DESC_CODE_FLAGS	(0x9B)
+#define GDT_DESC_CODE_FLAGS (0x9B)
 
 /* data segment flag,  R/W, Present = 1, DPL = 0, Acesssed = 1 */
-#define GDT_DESC_DATA_FLAGS	(0x93)
+#define GDT_DESC_DATA_FLAGS (0x93)
 
 /* TSS segment limit size */
-#define GDT_DESC_TSS_LIMIT	(0x67)
+#define GDT_DESC_TSS_LIMIT (0x67)
 
 /* TSS segment flag, Present = 1, DPL = 0, Acesssed = 1 */
-#define GDT_DESC_TSS_FLAGS	(0x89)
+#define GDT_DESC_TSS_FLAGS (0x89)
 
 /* LDT segment flag, Present = 1, DPL = 0 */
-#define GDT_DESC_LDT_FLAGS	(0x82)
+#define GDT_DESC_LDT_FLAGS (0x82)
 
 /* IDT descriptor flag, Present = 1, DPL = 0, 32-bit interrupt gate */
-#define IDT_DESC_FLAGS		(0x8E)
+#define IDT_DESC_FLAGS (0x8E)
 
 /**
  * macros helper to create a GDT entry descriptor
@@ -141,21 +140,20 @@ struct tss_entry {
  * limit: 32bit limit size of bytes (will covert to unit of 4096-byte pages)
  * flags: 8bit flags
  */
-#define GEN_GDT_DESC_LO(base, limit, flags)                                    \
-	((((limit) >> 12) & 0xFFFF) | (((base) & 0xFFFF) << 16))
-
-#define GEN_GDT_DESC_UP(base, limit, flags)                                    \
-	((((base) >> 16) & 0xFF) | (((flags) << 8) & 0xFF00) |                 \
-	(((limit) >> 12) & 0xFF0000) | ((base) & 0xFF000000) | 0xc00000)
+#define GEN_GDT_DESC_LO(base, limit, flags) \
+	((((limit) >> 12) & 0xFFFF) | (((base)&0xFFFF) << 16))
 
+#define GEN_GDT_DESC_UP(base, limit, flags)                    \
+	((((base) >> 16) & 0xFF) | (((flags) << 8) & 0xFF00) | \
+	 (((limit) >> 12) & 0xFF0000) | ((base)&0xFF000000) | 0xc00000)
 
 /**
  * macro helper to create a IDT entry descriptor
  */
-#define GEN_IDT_DESC_LO(offset, selector, flags)                               \
-	(((uint32_t)(offset) & 0xFFFF) | (((selector) & 0xFFFF) << 16))
+#define GEN_IDT_DESC_LO(offset, selector, flags) \
+	(((uint32_t)(offset)&0xFFFF) | (((selector)&0xFFFF) << 16))
 
-#define GEN_IDT_DESC_UP(offset, selector, flags)                               \
-	(((uint32_t)(offset) & 0xFFFF0000) | (((flags) & 0xFF) << 8))
+#define GEN_IDT_DESC_UP(offset, selector, flags) \
+	(((uint32_t)(offset)&0xFFFF0000) | (((flags)&0xFF) << 8))
 
 #endif /* __CROS_EC_IA_STRUCTS_H */
diff --git a/core/minute-ia/include/fpu.h b/core/minute-ia/include/fpu.h
index 553807352a..9c0e818099 100644
--- a/core/minute-ia/include/fpu.h
+++ b/core/minute-ia/include/fpu.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,19 +12,15 @@
 
 #ifdef CONFIG_FPU
 
-#define M_PI            3.14159265358979323846
-#define M_PI_2          1.57079632679489661923
+#define M_PI 3.14159265358979323846
+#define M_PI_2 1.57079632679489661923
 
 static inline float sqrtf(float v)
 {
 	float root;
 
 	/* root = fsqart (v); */
-	asm volatile(
-		"fsqrt"
-		: "=t" (root)
-		: "0" (v)
-	);
+	asm volatile("fsqrt" : "=t"(root) : "0"(v));
 	return root;
 }
 
@@ -34,11 +30,7 @@ static inline float fabsf(float v)
 	float root;
 
 	/* root = fabs (v); */
-	asm volatile(
-		"fabs"
-		: "=t" (root)
-		: "0" (v)
-	);
+	asm volatile("fabs" : "=t"(root) : "0"(v));
 	return root;
 }
 
@@ -51,12 +43,11 @@ static inline float logf(float v)
 {
 	float res;
 
-	asm volatile(
-		"fldln2\n"
-		"fxch\n"
-		"fyl2x\n"
-		: "=t" (res)
-		: "0" (v));
+	asm volatile("fldln2\n"
+		     "fxch\n"
+		     "fyl2x\n"
+		     : "=t"(res)
+		     : "0"(v));
 
 	return res;
 }
@@ -70,20 +61,19 @@ static inline float expf(float v)
 {
 	float res;
 
-	asm volatile(
-		"fldl2e\n"
-		"fmulp\n"
-		"fld %%st(0)\n"
-		"frndint\n"
-		"fsubr %%st(0),%%st(1)\n" /* bug-binutils/19054 */
-		"fxch %%st(1)\n"
-		"f2xm1\n"
-		"fld1\n"
-		"faddp\n"
-		"fscale\n"
-		"fstp %%st(1)\n"
-		: "=t" (res)
-		: "0" (v));
+	asm volatile("fldl2e\n"
+		     "fmulp\n"
+		     "fld %%st(0)\n"
+		     "frndint\n"
+		     "fsubr %%st(0),%%st(1)\n" /* bug-binutils/19054 */
+		     "fxch %%st(1)\n"
+		     "f2xm1\n"
+		     "fld1\n"
+		     "faddp\n"
+		     "fscale\n"
+		     "fstp %%st(1)\n"
+		     : "=t"(res)
+		     : "0"(v));
 
 	return res;
 }
@@ -97,24 +87,23 @@ static inline float powf(float x, float y)
 {
 	float res;
 
-	asm volatile(
-		"fyl2x\n"
-		"fld %%st(0)\n"
-		"frndint\n"
-		"fsub %%st,%%st(1)\n"
-		"fxch\n"
-		"fchs\n"
-		"f2xm1\n"
-		"fld1\n"
-		"faddp\n"
-		"fxch\n"
-		"fld1\n"
-		"fscale\n"
-		"fstp %%st(1)\n"
-		"fmulp\n"
-		: "=t" (res)
-		: "0" (x), "u" (y)
-		: "st(1)");
+	asm volatile("fyl2x\n"
+		     "fld %%st(0)\n"
+		     "frndint\n"
+		     "fsub %%st,%%st(1)\n"
+		     "fxch\n"
+		     "fchs\n"
+		     "f2xm1\n"
+		     "fld1\n"
+		     "faddp\n"
+		     "fxch\n"
+		     "fld1\n"
+		     "fscale\n"
+		     "fstp %%st(1)\n"
+		     "fmulp\n"
+		     : "=t"(res)
+		     : "0"(x), "u"(y)
+		     : "st(1)");
 
 	return res;
 }
@@ -125,16 +114,15 @@ static inline float ceilf(float v)
 	float res;
 	unsigned short control_word, control_word_tmp;
 
-	asm volatile("fnstcw %0" : "=m" (control_word));
+	asm volatile("fnstcw %0" : "=m"(control_word));
 	/* Set Rounding Mode to 10B, round up toward +infinity */
 	control_word_tmp = (control_word | 0x0800) & 0xfbff;
-	asm volatile(
-		"fld %3\n"
-		"fldcw %1\n"
-		"frndint\n"
-		"fldcw %2"
-		: "=t" (res)
-		: "m" (control_word_tmp), "m"(control_word), "m" (v));
+	asm volatile("fld %3\n"
+		     "fldcw %1\n"
+		     "frndint\n"
+		     "fldcw %2"
+		     : "=t"(res)
+		     : "m"(control_word_tmp), "m"(control_word), "m"(v));
 
 	return res;
 }
@@ -144,7 +132,7 @@ static inline float atan2f(float y, float x)
 {
 	float res;
 
-	asm volatile("fpatan" : "=t" (res) : "0" (x), "u" (y) : "st(1)");
+	asm volatile("fpatan" : "=t"(res) : "0"(x), "u"(y) : "st(1)");
 
 	return res;
 }
@@ -154,11 +142,10 @@ static inline float atanf(float v)
 {
 	float res;
 
-	asm volatile(
-		"fld1\n"
-		"fpatan\n"
-		: "=t" (res)
-		: "0" (v));
+	asm volatile("fld1\n"
+		     "fpatan\n"
+		     : "=t"(res)
+		     : "0"(v));
 
 	return res;
 }
@@ -168,7 +155,7 @@ static inline float sinf(float v)
 {
 	float res;
 
-	asm volatile("fsin" : "=t" (res) : "0" (v));
+	asm volatile("fsin" : "=t"(res) : "0"(v));
 
 	return res;
 }
@@ -178,7 +165,7 @@ static inline float cosf(float v)
 {
 	float res;
 
-	asm volatile("fcos" : "=t" (res) : "0" (v));
+	asm volatile("fcos" : "=t"(res) : "0"(v));
 
 	return res;
 }
@@ -189,5 +176,5 @@ static inline float acosf(float v)
 	return atan2f(sqrtf(1.0 - v * v), v);
 }
 
-#endif  /* CONFIG_FPU */
-#endif  /* __CROS_EC_FPU_H */
+#endif /* CONFIG_FPU */
+#endif /* __CROS_EC_FPU_H */
diff --git a/core/minute-ia/init.S b/core/minute-ia/init.S
index b8e51ccc91..4d3ac47da6 100644
--- a/core/minute-ia/init.S
+++ b/core/minute-ia/init.S
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/minute-ia/interrupts.c b/core/minute-ia/interrupts.c
index 2d55d3129e..34baa68fa8 100644
--- a/core/minute-ia/interrupts.c
+++ b/core/minute-ia/interrupts.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -20,8 +20,8 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 /* The IDT  - initialized in init.S */
 extern struct idt_entry __idt[NUM_VECTORS];
@@ -54,7 +54,7 @@ static void set_ioapic_redtbl_raw(const uint32_t irq, const uint32_t val)
  * bitmap for current IRQ's mask status
  * ISH support max 64 IRQs, 64 bit bitmap value is ok
  */
-#define ISH_MAX_IOAPIC_IRQS	(64)
+#define ISH_MAX_IOAPIC_IRQS (64)
 uint64_t ioapic_irq_mask_bitmap;
 
 /**
@@ -70,7 +70,7 @@ uint64_t disable_all_interrupts(void)
 	uint64_t saved_map;
 	int i;
 
-	saved_map =  ioapic_irq_mask_bitmap;
+	saved_map = ioapic_irq_mask_bitmap;
 
 	for (i = 0; i < ISH_MAX_IOAPIC_IRQS; i++) {
 		if (((uint64_t)0x1 << i) & saved_map)
@@ -179,27 +179,27 @@ static const irq_desc_t system_irqs[] = {
  * and go directly to the CPU core, so get_current_interrupt_vector
  * cannot be used.
  */
-#define DEFINE_EXN_HANDLER(vector)			\
+#define DEFINE_EXN_HANDLER(vector) \
 	_DEFINE_EXN_HANDLER(vector, exception_panic_##vector)
-#define _DEFINE_EXN_HANDLER(vector, name)		\
-	void __keep name(void);				\
-	noreturn void name(void)	\
-	{						\
-		__asm__ ("push $0\n"			\
-			 "push $" #vector "\n"		\
-			 "call exception_panic\n");	\
-		__builtin_unreachable();		\
+#define _DEFINE_EXN_HANDLER(vector, name)          \
+	void __keep name(void);                    \
+	noreturn void name(void)                   \
+	{                                          \
+		__asm__("push $0\n"                \
+			"push $" #vector "\n"      \
+			"call exception_panic\n"); \
+		__builtin_unreachable();           \
 	}
 
-#define DEFINE_EXN_HANDLER_W_ERRORCODE(vector)		\
+#define DEFINE_EXN_HANDLER_W_ERRORCODE(vector) \
 	_DEFINE_EXN_HANDLER_W_ERRORCODE(vector, exception_panic_##vector)
-#define _DEFINE_EXN_HANDLER_W_ERRORCODE(vector, name)	\
-	void __keep name(void);				\
-	noreturn void name(void)	\
-	{						\
-		__asm__ ("push $" #vector "\n"		\
-			 "call exception_panic\n");	\
-		__builtin_unreachable();		\
+#define _DEFINE_EXN_HANDLER_W_ERRORCODE(vector, name) \
+	void __keep name(void);                       \
+	noreturn void name(void)                      \
+	{                                             \
+		__asm__("push $" #vector "\n"         \
+			"call exception_panic\n");    \
+		__builtin_unreachable();              \
 	}
 
 DEFINE_EXN_HANDLER(0);
@@ -228,15 +228,10 @@ DEFINE_EXN_HANDLER(20);
  * watchdog timer expiration. However, this time, hardware does not
  * push errorcode, and we must account for that by pushing zero.
  */
-noreturn __keep
-void exception_panic_wdt(uint32_t cs)
+noreturn __keep void exception_panic_wdt(uint32_t cs)
 {
-	exception_panic(
-		CONFIG_MIA_WDT_VEC,
-		0,
-		(uint32_t)__builtin_return_address(0),
-		cs,
-		0);
+	exception_panic(CONFIG_MIA_WDT_VEC, 0,
+			(uint32_t)__builtin_return_address(0), cs, 0);
 }
 
 void set_interrupt_gate(uint8_t num, isr_handler_t func, uint8_t flags)
@@ -244,7 +239,7 @@ void set_interrupt_gate(uint8_t num, isr_handler_t func, uint8_t flags)
 	uint16_t code_segment;
 
 	/* When the flat model is used the CS will never change. */
-	__asm volatile ("mov %%cs, %0":"=r" (code_segment));
+	__asm volatile("mov %%cs, %0" : "=r"(code_segment));
 
 	__idt[num].dword_lo = GEN_IDT_DESC_LO(func, code_segment, flags);
 	__idt[num].dword_up = GEN_IDT_DESC_UP(func, code_segment, flags);
@@ -384,26 +379,28 @@ void handle_lapic_lvt_error(void)
 
 /* LAPIC LVT error is not an IRQ and can not use DECLARE_IRQ() to call. */
 void _lapic_error_handler(void);
-__asm__ (
-	".section .text._lapic_error_handler\n"
+__asm__(".section .text._lapic_error_handler\n"
 	"_lapic_error_handler:\n"
-		"pusha\n"
-		ASM_LOCK_PREFIX "addl $1, __in_isr\n"
-		"movl %esp, %eax\n"
-		"movl $stack_end, %esp\n"
-		"push %eax\n"
+	"pusha\n" ASM_LOCK_PREFIX "addl $1, __in_isr\n"
+	"movl %esp, %eax\n"
+	"movl $stack_end, %esp\n"
+	"push %eax\n"
 #ifdef CONFIG_TASK_PROFILING
-		"push $" STRINGIFY(CONFIG_IRQ_COUNT) "\n"
-		"call task_start_irq_handler\n"
-		"addl $0x04, %esp\n"
+	"push $" STRINGIFY(
+		CONFIG_IRQ_COUNT) "\n"
+				  "call task_start_irq_handler\n"
+				  "addl $0x04, %esp\n"
 #endif
-		"call handle_lapic_lvt_error\n"
-		"pop %esp\n"
-		"movl $0x00, (0xFEE000B0)\n"	/* Set EOI for LAPIC */
-		ASM_LOCK_PREFIX "subl $1, __in_isr\n"
-		"popa\n"
-		"iret\n"
-	);
+				  "call handle_lapic_lvt_error\n"
+				  "pop %esp\n"
+				  "movl $0x00, (0xFEE000B0)\n" /* Set
+								  EOI
+								  for
+								  LAPIC
+								*/
+	ASM_LOCK_PREFIX "subl $1, __in_isr\n"
+				  "popa\n"
+				  "iret\n");
 
 /* Should only be called in interrupt context */
 void unhandled_vector(void)
@@ -411,7 +408,7 @@ void unhandled_vector(void)
 	uint32_t vec = get_current_interrupt_vector();
 	CPRINTF("Ignoring vector 0x%0x!\n", vec);
 	/* Put the vector number in eax so default_int_handler can use it */
-	asm("" : : "a" (vec));
+	asm("" : : "a"(vec));
 }
 
 /**
@@ -454,8 +451,7 @@ void init_interrupts(void)
 
 	/* Setup gates for IRQs declared by drivers using DECLARE_IRQ */
 	for (p = __irq_data; p < __irq_data_end; p++)
-		set_interrupt_gate(IRQ_TO_VEC(p->irq),
-				   p->handler,
+		set_interrupt_gate(IRQ_TO_VEC(p->irq), p->handler,
 				   IDT_DESC_FLAGS);
 
 	/* Software generated IRQ */
@@ -474,11 +470,11 @@ void init_interrupts(void)
 	for (entry = 0; entry < num_system_irqs; entry++)
 		set_ioapic_redtbl_raw(system_irqs[entry].irq,
 				      system_irqs[entry].vector |
-				      IOAPIC_REDTBL_DELMOD_FIXED |
-				      IOAPIC_REDTBL_DESTMOD_PHYS |
-				      IOAPIC_REDTBL_MASK |
-				      system_irqs[entry].polarity |
-				      system_irqs[entry].trigger);
+					      IOAPIC_REDTBL_DELMOD_FIXED |
+					      IOAPIC_REDTBL_DESTMOD_PHYS |
+					      IOAPIC_REDTBL_MASK |
+					      system_irqs[entry].polarity |
+					      system_irqs[entry].trigger);
 
 	set_interrupt_gate(ISH_TS_VECTOR, __switchto, IDT_DESC_FLAGS);
 
diff --git a/core/minute-ia/interrupts.h b/core/minute-ia/interrupts.h
index 3a951a5ddb..65b26c437e 100644
--- a/core/minute-ia/interrupts.h
+++ b/core/minute-ia/interrupts.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,7 +11,7 @@
 #ifndef __ASSEMBLER__
 #include <stdint.h>
 
-#define USHRT_MAX		0xFFFF
+#define USHRT_MAX 0xFFFF
 typedef struct {
 	unsigned irq;
 	unsigned trigger;
@@ -19,13 +19,11 @@ typedef struct {
 	unsigned vector;
 } irq_desc_t;
 
-#define INTR_DESC(__irq,__vector,__trig)                    \
-    {                                                       \
-        .irq            = __irq,                            \
-        .trigger        = __trig,                           \
-        .polarity       = IOAPIC_REDTBL_INTPOL_HIGH,        \
-        .vector         = __vector	                    \
-    }
+#define INTR_DESC(__irq, __vector, __trig)                                \
+	{                                                                 \
+		.irq = __irq, .trigger = __trig,                          \
+		.polarity = IOAPIC_REDTBL_INTPOL_HIGH, .vector = __vector \
+	}
 
 #define LEVEL_INTR(__irq, __vector) \
 	INTR_DESC(__irq, __vector, IOAPIC_REDTBL_TRIGGER_LEVEL)
@@ -34,18 +32,18 @@ typedef struct {
 #endif
 
 /* ISH has a single core processor */
-#define DEST_APIC_ID			0
-#define NUM_VECTORS			256
+#define DEST_APIC_ID 0
+#define NUM_VECTORS 256
 
 /* APIC bit definitions. */
-#define APIC_DIV_16			0x03
-#define APIC_ENABLE_BIT			(1UL << 8UL)
-#define APIC_SPURIOUS_INT		REG32(ISH_LAPIC_BASE + 0xF0UL )
-#define APIC_LVT_ERROR			REG32(ISH_LAPIC_BASE + 0x370UL)
+#define APIC_DIV_16 0x03
+#define APIC_ENABLE_BIT (1UL << 8UL)
+#define APIC_SPURIOUS_INT REG32(ISH_LAPIC_BASE + 0xF0UL)
+#define APIC_LVT_ERROR REG32(ISH_LAPIC_BASE + 0x370UL)
 
 #ifndef __ASSEMBLER__
 
-typedef void (*isr_handler_t) (void);
+typedef void (*isr_handler_t)(void);
 
 void init_interrupts(void);
 void mask_interrupt(unsigned int irq);
@@ -66,4 +64,4 @@ void restore_interrupts(uint64_t irq_map);
 uint32_t get_current_interrupt_vector(void);
 #endif
 
-#endif	/* __CROS_EC_IA32_INTERRUPTS_H */
+#endif /* __CROS_EC_IA32_INTERRUPTS_H */
diff --git a/core/minute-ia/irq_handler.h b/core/minute-ia/irq_handler.h
index 30106603d6..deb8048e12 100644
--- a/core/minute-ia/irq_handler.h
+++ b/core/minute-ia/irq_handler.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,7 +12,7 @@
 #include "task.h"
 #include "task_defs.h"
 
-asm (".include \"core/minute-ia/irq_handler_common.S\"");
+asm(".include \"core/minute-ia/irq_handler_common.S\"");
 
 /* Helper macros to build the IRQ handler and priority struct names */
 #define IRQ_HANDLER(irqname) CONCAT3(_irq_, irqname, _handler)
@@ -30,26 +30,24 @@ asm (".include \"core/minute-ia/irq_handler_common.S\"");
  * Each irq has a irq_data structure placed in .rodata.irqs section,
  * to be used for dynamically setting up interrupt gates
  */
-#define DECLARE_IRQ_(irq_, routine_, vector)				\
-	static void __keep routine_(void);				\
-	void IRQ_HANDLER(irq_)(void);					\
-	__asm__ (".section .rodata.irqs\n");				\
-	const struct irq_def __keep CONCAT4(__irq_, irq_, _, routine_)	\
-	__attribute__((section(".rodata.irqs"))) = {			\
-		.irq = irq_,						\
-		.routine = routine_,					\
-		.handler = IRQ_HANDLER(irq_)				\
-	};								\
-	__asm__ (							\
-		".section .text._irq_" #irq_ "_handler\n"		\
-		"_irq_" #irq_ "_handler:\n"				\
-		"pusha\n"						\
-		ASM_LOCK_PREFIX "addl  $1, __in_isr\n"			\
-		"irq_handler_common $0 $0 $" #irq_ "\n"			\
-		"movl $"#vector ", " STRINGIFY(IOAPIC_EOI_REG_ADDR) "\n" \
-		"movl $0x00, " STRINGIFY(LAPIC_EOI_REG_ADDR) "\n"	\
-		ASM_LOCK_PREFIX "subl  $1, __in_isr\n"			\
-		"popa\n"						\
-		"iret\n"						\
-	)
-#endif  /* __CROS_EC_IRQ_HANDLER_H */
+#define DECLARE_IRQ_(irq_, routine_, vector)                                                    \
+	static void __keep routine_(void);                                                      \
+	void IRQ_HANDLER(irq_)(void);                                                           \
+	__asm__(".section .rodata.irqs\n");                                                     \
+	const struct irq_def __keep CONCAT4(__irq_, irq_, _, routine_)                          \
+		__attribute__((section(                                                         \
+			".rodata.irqs"))) = { .irq = irq_,                                      \
+					      .routine = routine_,                              \
+					      .handler = IRQ_HANDLER(irq_) };                   \
+	__asm__(".section .text._irq_" #irq_ "_handler\n"                                       \
+		"_irq_" #irq_ "_handler:\n"                                                     \
+		"pusha\n" ASM_LOCK_PREFIX "addl  $1, __in_isr\n"                                \
+		"irq_handler_common $0 $0 $" #irq_ "\n"                                         \
+		"movl $" #vector ", " STRINGIFY(                                                \
+			IOAPIC_EOI_REG_ADDR) "\n"                                               \
+					     "movl $0x00, " STRINGIFY(                          \
+						     LAPIC_EOI_REG_ADDR) "\n" ASM_LOCK_PREFIX   \
+									 "subl  $1, __in_isr\n" \
+									 "popa\n"               \
+									 "iret\n")
+#endif /* __CROS_EC_IRQ_HANDLER_H */
diff --git a/core/minute-ia/irq_handler_common.S b/core/minute-ia/irq_handler_common.S
index e07cf26ce1..2445f83730 100644
--- a/core/minute-ia/irq_handler_common.S
+++ b/core/minute-ia/irq_handler_common.S
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/minute-ia/mia_panic_internal.h b/core/minute-ia/mia_panic_internal.h
index 748ccbf2dd..d9d213ca85 100644
--- a/core/minute-ia/mia_panic_internal.h
+++ b/core/minute-ia/mia_panic_internal.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,10 +8,5 @@
  * convenientely in the same order as pushed by hardwared during a
  * processor exception.
  */
-noreturn
-void exception_panic(
-	uint32_t vector,
-	uint32_t errorcode,
-	uint32_t eip,
-	uint32_t cs,
-	uint32_t eflags);
+noreturn void exception_panic(uint32_t vector, uint32_t errorcode, uint32_t eip,
+			      uint32_t cs, uint32_t eflags);
diff --git a/core/minute-ia/mpu.c b/core/minute-ia/mpu.c
index 389668ea6f..d91d71f99c 100644
--- a/core/minute-ia/mpu.c
+++ b/core/minute-ia/mpu.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/core/minute-ia/panic.c b/core/minute-ia/panic.c
index b4299d9e17..d02778891d 100644
--- a/core/minute-ia/panic.c
+++ b/core/minute-ia/panic.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -57,13 +57,12 @@ void panic_data_print(const struct panic_data *pdata)
 	else if (pdata->x86.vector <= 20)
 		panic_printf("Reason: %s\n", panic_reason[pdata->x86.vector]);
 	else if (panic_sw_reason_is_valid(pdata->x86.vector)) {
-		panic_printf("Software panic reason %s\n",
-			     panic_sw_reasons[pdata->x86.vector -
-					      PANIC_SW_BASE]);
+		panic_printf(
+			"Software panic reason %s\n",
+			panic_sw_reasons[pdata->x86.vector - PANIC_SW_BASE]);
 		panic_printf("Software panic info 0x%x\n",
 			     pdata->x86.error_code);
-	}
-	else
+	} else
 		panic_printf("Interrupt vector number: 0x%08X (unknown)\n",
 			     pdata->x86.vector);
 	panic_printf("\n");
@@ -91,12 +90,8 @@ void panic_data_print(const struct panic_data *pdata)
  * order pushed to the stack by hardware: see "Intel 64 and IA-32
  * Architectures Software Developer's Manual", Volume 3A, Figure 6-4.
  */
-void exception_panic(
-	uint32_t vector,
-	uint32_t error_code,
-	uint32_t eip,
-	uint32_t cs,
-	uint32_t eflags)
+void exception_panic(uint32_t vector, uint32_t error_code, uint32_t eip,
+		     uint32_t cs, uint32_t eflags)
 {
 	/*
 	 * If a panic were to occur during the reset procedure, we want
@@ -176,26 +171,22 @@ void exception_panic(
 	__builtin_unreachable();
 }
 
-noreturn
-void software_panic(uint32_t reason, uint32_t info)
+noreturn void software_panic(uint32_t reason, uint32_t info)
 {
 	uint16_t code_segment;
 
 	/* Get the current code segment */
-	__asm__ volatile ("movw  %%cs, %0":"=m" (code_segment));
+	__asm__ volatile("movw  %%cs, %0" : "=m"(code_segment));
 
-	exception_panic(reason,
-			info,
-			(uint32_t)__builtin_return_address(0),
-			code_segment,
-			0);
+	exception_panic(reason, info, (uint32_t)__builtin_return_address(0),
+			code_segment, 0);
 
 	__builtin_unreachable();
 }
 
 void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
 {
-	struct panic_data * const pdata = get_panic_data_write();
+	struct panic_data *const pdata = get_panic_data_write();
 
 	/* Setup panic data structure */
 	memset(pdata, 0, CONFIG_PANIC_DATA_SIZE);
@@ -212,7 +203,7 @@ void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
 
 void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception)
 {
-	struct panic_data * const pdata = panic_get_data();
+	struct panic_data *const pdata = panic_get_data();
 
 	if (pdata && pdata->struct_version == 2) {
 		*reason = pdata->x86.vector;
diff --git a/core/minute-ia/switch.S b/core/minute-ia/switch.S
index cec3f904f9..b014bb4c29 100644
--- a/core/minute-ia/switch.S
+++ b/core/minute-ia/switch.S
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/minute-ia/task.c b/core/minute-ia/task.c
index 4eb33e295a..79ce82fd89 100644
--- a/core/minute-ia/task.c
+++ b/core/minute-ia/task.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,6 +13,7 @@
 #define TEST_TASK_EXTRA_ARGS 0
 
 #include "atomic.h"
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
 #include "link_defs.h"
@@ -26,8 +27,8 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 /* Value to store in unused stack */
 #define STACK_UNUSED_VALUE 0xdeadd00d
@@ -43,11 +44,9 @@ CONFIG_TEST_TASK_LIST
 extern volatile uint32_t __in_isr;
 
 /* Task names for easier debugging */
-#define TASK(n, r, d, s, f)  #n,
-static const char * const task_names[] = {
-	"<< idle >>",
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
+#define TASK(n, r, d, s, f) #n,
+static const char *const task_names[] = {
+	"<< idle >>", CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST
 };
 #undef TASK
 
@@ -57,12 +56,12 @@ static uint64_t task_start_time; /* Time task scheduling started */
  * We only keep 32-bit values for exception start/end time, to avoid
  * accounting errors when we service interrupt when the timer wraps around.
  */
-static uint32_t exc_start_time;  /* Time of task->exception transition */
-static uint32_t exc_end_time;    /* Time of exception->task transition */
-static uint64_t exc_total_time;  /* Total time in exceptions */
-static atomic_t svc_calls;	 /* Number of service calls */
-static uint32_t task_switches;	/* Number of times active task changed */
-static uint32_t irq_dist[CONFIG_IRQ_COUNT];	/* Distribution of IRQ calls */
+static uint32_t exc_start_time; /* Time of task->exception transition */
+static uint32_t exc_end_time; /* Time of exception->task transition */
+static uint64_t exc_total_time; /* Total time in exceptions */
+static atomic_t svc_calls; /* Number of service calls */
+static uint32_t task_switches; /* Number of times active task changed */
+static uint32_t irq_dist[CONFIG_IRQ_COUNT]; /* Distribution of IRQ calls */
 #endif
 
 void __schedule(int desched, int resched);
@@ -97,22 +96,20 @@ static void task_exit_trap(void)
 }
 
 /* Startup parameters for all tasks. */
-#define TASK(n, r, d, s, f)  {	\
-	.r0 = (uint32_t)d,	\
-	.pc = (uint32_t)r,	\
-	.stack_size = s,	\
-	.flags = f,		\
-},
+#define TASK(n, r, d, s, f)        \
+	{                          \
+		.r0 = (uint32_t)d, \
+		.pc = (uint32_t)r, \
+		.stack_size = s,   \
+		.flags = f,        \
+	},
 static const struct {
 	uint32_t r0;
 	uint32_t pc;
 	uint16_t stack_size;
 	uint32_t flags;
-} tasks_init[] = {
-	TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE, 0)
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
-};
+} tasks_init[] = { TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE, 0)
+			   CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST };
 
 #undef TASK
 
@@ -122,18 +119,13 @@ static task_ tasks[TASK_ID_COUNT];
 BUILD_ASSERT(TASK_ID_COUNT <= sizeof(unsigned) * 8);
 BUILD_ASSERT(TASK_ID_COUNT < (1 << (sizeof(task_id_t) * 8)));
 
-
 /* Stacks for all tasks */
-#define TASK(n, r, d, s, f)  + s
-uint8_t task_stacks[0
-		    TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE, 0)
-		    CONFIG_TASK_LIST
-		    CONFIG_TEST_TASK_LIST
-] __aligned(8);
+#define TASK(n, r, d, s, f) +s
+uint8_t task_stacks[0 TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE, 0)
+			    CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST] __aligned(8);
 
 #undef TASK
 
-
 task_ *current_task, *next_task;
 
 /*
@@ -151,7 +143,7 @@ static atomic_t tasks_ready = BIT(TASK_ID_HOOKS);
  */
 static atomic_t tasks_enabled = BIT(TASK_ID_HOOKS) | BIT(TASK_ID_IDLE);
 
-static int start_called;  /* Has task swapping started */
+static int start_called; /* Has task swapping started */
 
 static inline task_ *__task_id_to_ptr(task_id_t id)
 {
@@ -160,7 +152,7 @@ static inline task_ *__task_id_to_ptr(task_id_t id)
 
 void interrupt_disable(void)
 {
-	__asm__ __volatile__ ("cli");
+	__asm__ __volatile__("cli");
 }
 
 void interrupt_enable(void)
@@ -170,16 +162,16 @@ void interrupt_enable(void)
 	 */
 	ASSERT(task_start_called() != 1);
 
-	__asm__ __volatile__ ("sti");
+	__asm__ __volatile__("sti");
 }
 
 inline bool is_interrupt_enabled(void)
 {
 	uint32_t eflags = 0;
 
-	__asm__ __volatile__ ("pushfl\n"
-			      "popl %0\n"
-			      : "=r"(eflags));
+	__asm__ __volatile__("pushfl\n"
+			     "popl %0\n"
+			     : "=r"(eflags));
 
 	/* Check Interrupt Enable flag */
 	return eflags & 0x200;
@@ -251,8 +243,7 @@ uint32_t switch_handler(int desched, task_id_t resched)
 	next = __task_id_to_ptr(__fls(tasks_ready & tasks_enabled));
 
 	/* Only the first ISR on the (nested IRQ) stack calculates time */
-	if (IS_ENABLED(CONFIG_TASK_PROFILING) &&
-	    __in_isr == 1) {
+	if (IS_ENABLED(CONFIG_TASK_PROFILING) && __in_isr == 1) {
 		/* Track time in interrupts */
 		uint32_t t = get_time().le.lo;
 
@@ -465,11 +456,10 @@ void mutex_lock(struct mutex *mtx)
 
 	do {
 		old_val = 0;
-		__asm__ __volatile__(
-				ASM_LOCK_PREFIX "cmpxchg %1, %2\n"
-				: "=a" (old_val)
-				: "r" (value), "m" (mtx->lock), "a" (old_val)
-				: "memory");
+		__asm__ __volatile__(ASM_LOCK_PREFIX "cmpxchg %1, %2\n"
+				     : "=a"(old_val)
+				     : "r"(value), "m"(mtx->lock), "a"(old_val)
+				     : "memory");
 
 		if (old_val != 0) {
 			/* Contention on the mutex */
@@ -486,11 +476,10 @@ void mutex_unlock(struct mutex *mtx)
 	uint32_t old_val = 1, val = 0;
 	task_ *tsk = current_task;
 
-	__asm__ __volatile__(
-			ASM_LOCK_PREFIX "cmpxchg %1, %2\n"
-			: "=a" (old_val)
-			: "r" (val), "m" (mtx->lock), "a" (old_val)
-			: "memory");
+	__asm__ __volatile__(ASM_LOCK_PREFIX "cmpxchg %1, %2\n"
+			     : "=a"(old_val)
+			     : "r"(val), "m"(mtx->lock), "a"(old_val)
+			     : "memory");
 	if (old_val == 1)
 		waiters = mtx->waiters;
 	/* else? Does unlock fail - what to do then ? */
@@ -532,13 +521,13 @@ void task_print_list(void)
 		if (IS_ENABLED(CONFIG_FPU)) {
 			char use_fpu = tasks[i].use_fpu ? 'Y' : 'N';
 
-			ccprintf("%4d %c %-16s %08x %11.6lld  %3d/%3d %c\n",
-				 i, is_ready, task_get_name(i),
+			ccprintf("%4d %c %-16s %08x %11.6lld  %3d/%3d %c\n", i,
+				 is_ready, task_get_name(i),
 				 (int)tasks[i].events, tasks[i].runtime,
 				 stackused, tasks_init[i].stack_size, use_fpu);
 		} else {
-			ccprintf("%4d %c %-16s %08x %11.6lld  %3d/%3d\n",
-				 i, is_ready, task_get_name(i),
+			ccprintf("%4d %c %-16s %08x %11.6lld  %3d/%3d\n", i,
+				 is_ready, task_get_name(i),
 				 (int)tasks[i].events, tasks[i].runtime,
 				 stackused, tasks_init[i].stack_size);
 		}
@@ -547,7 +536,7 @@ void task_print_list(void)
 	}
 }
 
-static int command_task_info(int argc, char **argv)
+static int command_task_info(int argc, const char **argv)
 {
 	task_print_list();
 
@@ -577,12 +566,9 @@ static int command_task_info(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(taskinfo, command_task_info,
-			NULL,
-			"Print task info");
+DECLARE_CONSOLE_COMMAND(taskinfo, command_task_info, NULL, "Print task info");
 
-__maybe_unused
-static int command_task_ready(int argc, char **argv)
+__maybe_unused static int command_task_ready(int argc, const char **argv)
 {
 	if (argc < 2) {
 		ccprintf("tasks_ready: 0x%08x\n", (int)tasks_ready);
@@ -596,8 +582,7 @@ static int command_task_ready(int argc, char **argv)
 }
 
 #ifdef CONFIG_CMD_TASKREADY
-DECLARE_CONSOLE_COMMAND(taskready, command_task_ready,
-			"[setmask]",
+DECLARE_CONSOLE_COMMAND(taskready, command_task_ready, "[setmask]",
 			"Print/set ready tasks");
 #endif
 
@@ -606,7 +591,7 @@ void task_pre_init(void)
 	int i, cs;
 	uint32_t *stack_next = (uint32_t *)task_stacks;
 
-	__asm__ __volatile__ ("movl %%cs, %0":"=r" (cs));
+	__asm__ __volatile__("movl %%cs, %0" : "=r"(cs));
 
 	/* Fill the task memory with initial values */
 	for (i = 0; i < TASK_ID_COUNT; i++) {
@@ -638,12 +623,12 @@ void task_pre_init(void)
 		sp[7] = 0xea;	/* EAX */
 #endif
 		/* For IRET */
-		sp[8] = tasks_init[i].pc;	/* pc */
+		sp[8] = tasks_init[i].pc; /* pc */
 		sp[9] = cs;
 		sp[10] = INITIAL_EFLAGS;
 
-		sp[11] = (uint32_t) task_exit_trap;
-		sp[12] = tasks_init[i].r0;	/* task argument */
+		sp[11] = (uint32_t)task_exit_trap;
+		sp[12] = tasks_init[i].r0; /* task argument */
 		sp[13] = 0x00;
 		sp[14] = 0x00;
 		sp[15] = 0x00;
@@ -656,7 +641,8 @@ void task_pre_init(void)
 				0x00, 0x00, /* Status[0-15] */
 				0xff, 0xff, /* unused */
 				0xff, 0xff, /* Tag[0-15] */
-				0xff, 0xff};/* unused */
+				0xff, 0xff
+			}; /* unused */
 
 			/* Copy default x86 FPU state for each task */
 			memcpy(tasks[i].fp_ctx, default_fp_ctx,
diff --git a/core/minute-ia/task_defs.h b/core/minute-ia/task_defs.h
index 18458b1533..dac80e0eb9 100644
--- a/core/minute-ia/task_defs.h
+++ b/core/minute-ia/task_defs.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,9 +7,9 @@
 #define __CROS_EC_TASK_DEFS_H
 
 #ifdef CONFIG_FPU
-#define FPU_CTX_SZ		108  /* 28 bytes header + 80 bytes registers */
-#define USE_FPU_OFFSET		20   /* offsetof(task_, use_fpu */
-#define FPU_CTX_OFFSET		24   /* offsetof(task_, fp_ctx) */
+#define FPU_CTX_SZ 108 /* 28 bytes header + 80 bytes registers */
+#define USE_FPU_OFFSET 20 /* offsetof(task_, use_fpu */
+#define FPU_CTX_OFFSET 24 /* offsetof(task_, fp_ctx) */
 
 /*
  * defines for inline asm
@@ -18,11 +18,11 @@
 #include "atomic.h"
 #include "common.h"
 
-#define USE_FPU_OFFSET_STR	STRINGIFY(USE_FPU_OFFSET)	/* "20" */
-#define FPU_CTX_OFFSET_STR	STRINGIFY(FPU_CTX_OFFSET)	/* "24" */
+#define USE_FPU_OFFSET_STR STRINGIFY(USE_FPU_OFFSET) /* "20" */
+#define FPU_CTX_OFFSET_STR STRINGIFY(FPU_CTX_OFFSET) /* "24" */
 
-asm (".equ USE_FPU_OFFSET, "USE_FPU_OFFSET_STR);
-asm (".equ FPU_CTX_OFFSET, "FPU_CTX_OFFSET_STR);
+asm(".equ USE_FPU_OFFSET, " USE_FPU_OFFSET_STR);
+asm(".equ FPU_CTX_OFFSET, " FPU_CTX_OFFSET_STR);
 
 #endif
 #endif /* CONFIG_FPU */
@@ -34,12 +34,12 @@ typedef union {
 		 * Note that sp must be the first element in the task struct
 		 * for __switchto() to work.
 		 */
-		uint32_t sp;	/* Saved stack pointer for context switch */
-		atomic_t events;	/* Bitmaps of received events */
-		uint64_t runtime;	/* Time spent in task */
-		uint32_t *stack;	/* Start of stack */
+		uint32_t sp; /* Saved stack pointer for context switch */
+		atomic_t events; /* Bitmaps of received events */
+		uint64_t runtime; /* Time spent in task */
+		uint32_t *stack; /* Start of stack */
 #ifdef CONFIG_FPU
-		uint32_t use_fpu;	/* set if task uses FPU */
+		uint32_t use_fpu; /* set if task uses FPU */
 		uint8_t fp_ctx[FPU_CTX_SZ]; /* x87 FPU context */
 #endif
 	};
@@ -50,7 +50,7 @@ void __switchto(void);
 void sw_irq_handler(void);
 
 /* Only the IF bit is set so tasks start with interrupts enabled. */
-#define INITIAL_EFLAGS		(0x200UL)
+#define INITIAL_EFLAGS (0x200UL)
 
 /* LAPIC ICR bit fields
  *	7:0	- vector
@@ -61,7 +61,7 @@ void sw_irq_handler(void);
  *	15	- Trigger mode (0 = edge)
  *	20:18	- Destination (1 = self)
  */
-#define LAPIC_ICR_BITS		0x44000
+#define LAPIC_ICR_BITS 0x44000
 
 #endif /* __ASSEMBLER__ */
 #endif /* __CROS_EC_TASK_DEFS_H */
diff --git a/core/minute-ia/toolchain.mk b/core/minute-ia/toolchain.mk
new file mode 100644
index 0000000000..ed7ebfb2c8
--- /dev/null
+++ b/core/minute-ia/toolchain.mk
@@ -0,0 +1,7 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Select Minute-IA bare-metal toolchain
+$(call set-option,CROSS_COMPILE,$(CROSS_COMPILE_i386),\
+	/opt/coreboot-sdk/bin/i386-elf-)
diff --git a/core/nds32/__builtin.c b/core/nds32/__builtin.c
index 7b1d5eea62..ae8aa4b053 100644
--- a/core/nds32/__builtin.c
+++ b/core/nds32/__builtin.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/core/nds32/__divdi3.S b/core/nds32/__divdi3.S
index d86e8f6273..36fe00a917 100644
--- a/core/nds32/__divdi3.S
+++ b/core/nds32/__divdi3.S
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/nds32/__libsoftfpu.S b/core/nds32/__libsoftfpu.S
index 672e6bbb3d..3f2e60767f 100644
--- a/core/nds32/__libsoftfpu.S
+++ b/core/nds32/__libsoftfpu.S
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/core/nds32/__muldi3.S b/core/nds32/__muldi3.S
index ef4a491183..0e766de3cb 100644
--- a/core/nds32/__muldi3.S
+++ b/core/nds32/__muldi3.S
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/nds32/__udivdi3.S b/core/nds32/__udivdi3.S
index 4cb3b058fe..624faff2c5 100644
--- a/core/nds32/__udivdi3.S
+++ b/core/nds32/__udivdi3.S
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/nds32/atomic.h b/core/nds32/atomic.h
index 592834faae..746093c919 100644
--- a/core/nds32/atomic.h
+++ b/core/nds32/atomic.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -85,4 +85,4 @@ static inline atomic_val_t atomic_and(atomic_t *addr, atomic_val_t bits)
 	return ret;
 }
 
-#endif  /* __CROS_EC_ATOMIC_H */
+#endif /* __CROS_EC_ATOMIC_H */
diff --git a/core/nds32/build.mk b/core/nds32/build.mk
index ddd65c680b..7790b96009 100644
--- a/core/nds32/build.mk
+++ b/core/nds32/build.mk
@@ -1,17 +1,11 @@
 # -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
+# Copyright 2013 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
 # Andestar v3m architecture core OS files build
 #
 
-# Set coreboot-sdk as the default toolchain for nds32
-NDS32_DEFAULT_COMPILE=/opt/coreboot-sdk/bin/nds32le-elf-
-
-# Select Andes bare-metal toolchain
-$(call set-option,CROSS_COMPILE,$(CROSS_COMPILE_nds32),$(NDS32_DEFAULT_COMPILE))
-
 # CPU specific compilation flags
 CFLAGS_CPU+=-march=v3m -Os
 LDFLAGS_EXTRA+=-mrelax
diff --git a/core/nds32/config_core.h b/core/nds32/config_core.h
index 7670e5cfad..096b244643 100644
--- a/core/nds32/config_core.h
+++ b/core/nds32/config_core.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/core/nds32/cpu.c b/core/nds32/cpu.c
index 6a3f3b5bc4..cfdddb334e 100644
--- a/core/nds32/cpu.c
+++ b/core/nds32/cpu.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -12,5 +12,5 @@ void cpu_init(void)
 {
 	/* DLM initialization is done in init.S */
 	/* Global interrupt enable */
-	asm volatile ("setgie.e");
+	asm volatile("setgie.e");
 }
diff --git a/core/nds32/cpu.h b/core/nds32/cpu.h
index 3bd5a93efc..54d1a243ba 100644
--- a/core/nds32/cpu.h
+++ b/core/nds32/cpu.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -15,9 +15,9 @@
 #define TASK_SCRATCHPAD_SIZE (18)
 
 /* Process Status Word bits */
-#define PSW_GIE		BIT(0) /* Global Interrupt Enable */
-#define PSW_INTL_SHIFT	1        /* Interrupt Stack Level */
-#define PSW_INTL_MASK	(0x3 << PSW_INTL_SHIFT)
+#define PSW_GIE BIT(0) /* Global Interrupt Enable */
+#define PSW_INTL_SHIFT 1 /* Interrupt Stack Level */
+#define PSW_INTL_MASK (0x3 << PSW_INTL_SHIFT)
 
 #ifndef __ASSEMBLER__
 
@@ -26,28 +26,28 @@
 /* write Process Status Word privileged register */
 static inline void set_psw(uint32_t val)
 {
-	asm volatile ("mtsr %0, $PSW" : : "r"(val));
+	asm volatile("mtsr %0, $PSW" : : "r"(val));
 }
 
 /* read Process Status Word privileged register */
 static inline uint32_t get_psw(void)
 {
 	uint32_t ret;
-	asm volatile ("mfsr %0, $PSW" : "=r"(ret));
+	asm volatile("mfsr %0, $PSW" : "=r"(ret));
 	return ret;
 }
 
 /* write Interruption Program Counter privileged register */
 static inline void set_ipc(uint32_t val)
 {
-	asm volatile ("mtsr %0, $IPC" : : "r"(val));
+	asm volatile("mtsr %0, $IPC" : : "r"(val));
 }
 
 /* read Interruption Program Counter privileged register */
 static inline uint32_t get_ipc(void)
 {
 	uint32_t ret;
-	asm volatile ("mfsr %0, $IPC" : "=r"(ret));
+	asm volatile("mfsr %0, $IPC" : "=r"(ret));
 	return ret;
 }
 
@@ -55,7 +55,7 @@ static inline uint32_t get_ipc(void)
 static inline uint32_t get_itype(void)
 {
 	uint32_t ret;
-	asm volatile ("mfsr %0, $ITYPE" : "=r"(ret));
+	asm volatile("mfsr %0, $ITYPE" : "=r"(ret));
 	return ret;
 }
 
diff --git a/core/nds32/ec.lds.S b/core/nds32/ec.lds.S
index fbc5ceaafd..87f6d2041a 100644
--- a/core/nds32/ec.lds.S
+++ b/core/nds32/ec.lds.S
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -185,6 +185,10 @@ SECTIONS
 		KEEP(*(.rodata.HOOK_USB_PD_CONNECT))
 		__hooks_usb_pd_connect_end = .;
 
+		__hooks_power_supply_change = .;
+		KEEP(*(.rodata.HOOK_POWER_SUPPLY_CHANGE))
+		__hooks_power_supply_change_end = .;
+
 		__deferred_funcs = .;
 		KEEP(*(.rodata.deferred))
 		__deferred_funcs_end = .;
@@ -263,6 +267,12 @@ SECTIONS
 		__bss_end = .;
 
 		/*
+		 * _sbrk in newlib expects "end" symbol to point to start of
+		 * free memory.
+		 */
+		end = .;
+
+		/*
 		 * Shared memory buffer must be at the end of preallocated RAM,
 		 * so it can expand to use all the remaining RAM.
 		 */
diff --git a/core/nds32/include/fpu.h b/core/nds32/include/fpu.h
index 4f3efc2e5a..80c3395d14 100644
--- a/core/nds32/include/fpu.h
+++ b/core/nds32/include/fpu.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,4 +11,4 @@
 float sqrtf(float x);
 float fabsf(float x);
 
-#endif  /* __CROS_EC_FPU_H */
+#endif /* __CROS_EC_FPU_H */
diff --git a/core/nds32/init.S b/core/nds32/init.S
index 159f3709d3..648e3d8183 100644
--- a/core/nds32/init.S
+++ b/core/nds32/init.S
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/nds32/irq_chip.h b/core/nds32/irq_chip.h
index ca517558b3..a339bb516c 100644
--- a/core/nds32/irq_chip.h
+++ b/core/nds32/irq_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/nds32/irq_handler.h b/core/nds32/irq_handler.h
index 7e404b5d0c..b1feaa44c3 100644
--- a/core/nds32/irq_handler.h
+++ b/core/nds32/irq_handler.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,12 +15,12 @@
  * Macro to connect the interrupt handler "routine" to the irq number "irq" and
  * ensure it is enabled in the interrupt controller with the right priority.
  */
-#define DECLARE_IRQ(irq, routine, priority)				\
-	static void __keep routine(void);				\
-	void IRQ_HANDLER(CPU_INT(irq))(void)				\
-		__attribute__ ((alias(STRINGIFY(routine))));		\
-	const struct irq_priority __keep IRQ_PRIORITY(CPU_INT(irq))	\
-	__attribute__((section(".rodata.irqprio")))			\
-			= {CPU_INT(irq), priority}
+#define DECLARE_IRQ(irq, routine, priority)                                   \
+	static void __keep routine(void);                                     \
+	void IRQ_HANDLER(CPU_INT(irq))(void)                                  \
+		__attribute__((alias(STRINGIFY(routine))));                   \
+	const struct irq_priority __keep IRQ_PRIORITY(CPU_INT(irq))           \
+		__attribute__((section(".rodata.irqprio"))) = { CPU_INT(irq), \
+								priority }
 
-#endif  /* __CROS_EC_IRQ_HANDLER_H */
+#endif /* __CROS_EC_IRQ_HANDLER_H */
diff --git a/core/nds32/math.c b/core/nds32/math.c
index 496fcc0e5d..d0c8fc5c33 100644
--- a/core/nds32/math.c
+++ b/core/nds32/math.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,19 +12,19 @@ union ieee_float_shape_type {
 };
 
 /* Get a 32 bit int from a float.  */
-#define GET_FLOAT_WORD(i, d) \
-	do { \
+#define GET_FLOAT_WORD(i, d)                      \
+	do {                                      \
 		union ieee_float_shape_type gf_u; \
-		gf_u.value = (d); \
-		(i) = gf_u.word; \
+		gf_u.value = (d);                 \
+		(i) = gf_u.word;                  \
 	} while (0)
 
 /* Set a float from a 32 bit int. */
-#define SET_FLOAT_WORD(d, i) \
-	do { \
+#define SET_FLOAT_WORD(d, i)                      \
+	do {                                      \
 		union ieee_float_shape_type sf_u; \
-		sf_u.word = (i); \
-		(d) = sf_u.value; \
+		sf_u.word = (i);                  \
+		(d) = sf_u.value;                 \
 	} while (0)
 
 float fabsf(float x)
diff --git a/core/nds32/panic.c b/core/nds32/panic.c
index 70e2cae3e0..a1eca1574f 100644
--- a/core/nds32/panic.c
+++ b/core/nds32/panic.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,7 +17,7 @@
 /* General purpose register (r6) for saving software panic reason */
 #define SOFT_PANIC_GPR_REASON 6
 /* General purpose register (r7) for saving software panic information */
-#define SOFT_PANIC_GPR_INFO   7
+#define SOFT_PANIC_GPR_INFO 7
 
 #ifdef CONFIG_DEBUG_EXCEPTIONS
 /**
@@ -46,7 +46,7 @@
  * All other exceptions not in the abovetable should have the INST field of
  * the ITYPE register set to 0.
  */
-static const char * const itype_inst[2] = {
+static const char *const itype_inst[2] = {
 	"a data memory access",
 	"an instruction fetch access",
 };
@@ -54,7 +54,7 @@ static const char * const itype_inst[2] = {
 /**
  * bit[3-0] @ ITYPE, general exception type information.
  */
-static const char * const itype_exc_type[16] = {
+static const char *const itype_exc_type[16] = {
 	"Alignment check",
 	"Reserved instruction",
 	"Trap",
@@ -78,8 +78,8 @@ static const char * const itype_exc_type[16] = {
 #ifdef CONFIG_SOFTWARE_PANIC
 void software_panic(uint32_t reason, uint32_t info)
 {
-	asm volatile ("mov55  $r6, %0" : : "r"(reason));
-	asm volatile ("mov55  $r7, %0" : : "r"(info));
+	asm volatile("mov55  $r6, %0" : : "r"(reason));
+	asm volatile("mov55  $r7, %0" : : "r"(info));
 	if (in_interrupt_context())
 		asm("j excep_handler");
 	else
@@ -94,7 +94,7 @@ void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
 	 * If it was called earlier (eg. when saving nds_n8.ipc) calling it
 	 * once again won't remove any data
 	 */
-	struct panic_data * const pdata = get_panic_data_write();
+	struct panic_data *const pdata = get_panic_data_write();
 	uint32_t warning_ipc;
 	uint32_t *regs;
 
@@ -121,7 +121,7 @@ void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
 
 void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception)
 {
-	struct panic_data * const pdata = panic_get_data();
+	struct panic_data *const pdata = panic_get_data();
 	uint32_t *regs;
 
 	if (pdata && pdata->struct_version == 2) {
@@ -136,17 +136,17 @@ void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception)
 #endif /* CONFIG_SOFTWARE_PANIC */
 
 static void print_panic_information(uint32_t *regs, uint32_t itype,
-					uint32_t ipc, uint32_t ipsw)
+				    uint32_t ipc, uint32_t ipsw)
 {
 	panic_printf("=== EXCEP: ITYPE=%x ===\n", itype);
-	panic_printf("R0  %08x R1  %08x R2  %08x R3  %08x\n",
-		     regs[0], regs[1], regs[2], regs[3]);
-	panic_printf("R4  %08x R5  %08x R6  %08x R7  %08x\n",
-		     regs[4], regs[5], regs[6], regs[7]);
-	panic_printf("R8  %08x R9  %08x R10 %08x R15 %08x\n",
-		     regs[8], regs[9], regs[10], regs[11]);
-	panic_printf("FP  %08x GP  %08x LP  %08x SP  %08x\n",
-		     regs[12], regs[13], regs[14], regs[15]);
+	panic_printf("R0  %08x R1  %08x R2  %08x R3  %08x\n", regs[0], regs[1],
+		     regs[2], regs[3]);
+	panic_printf("R4  %08x R5  %08x R6  %08x R7  %08x\n", regs[4], regs[5],
+		     regs[6], regs[7]);
+	panic_printf("R8  %08x R9  %08x R10 %08x R15 %08x\n", regs[8], regs[9],
+		     regs[10], regs[11]);
+	panic_printf("FP  %08x GP  %08x LP  %08x SP  %08x\n", regs[12],
+		     regs[13], regs[14], regs[15]);
 	panic_printf("IPC %08x IPSW   %05x\n", ipc, ipsw);
 	if ((ipsw & PSW_INTL_MASK) == (2 << PSW_INTL_SHIFT)) {
 		/* 2nd level exception */
@@ -161,16 +161,16 @@ static void print_panic_information(uint32_t *regs, uint32_t itype,
 	if (panic_sw_reason_is_valid(regs[SOFT_PANIC_GPR_REASON])) {
 #ifdef CONFIG_SOFTWARE_PANIC
 		panic_printf("Software panic reason %s\n",
-			panic_sw_reasons[(regs[SOFT_PANIC_GPR_REASON] -
-					  PANIC_SW_BASE)]);
+			     panic_sw_reasons[(regs[SOFT_PANIC_GPR_REASON] -
+					       PANIC_SW_BASE)]);
 		panic_printf("Software panic info 0x%x\n",
-			regs[SOFT_PANIC_GPR_INFO]);
+			     regs[SOFT_PANIC_GPR_INFO]);
 #endif
 	} else {
 		panic_printf("Exception type: General exception [%s]\n",
-			itype_exc_type[(itype & 0xf)]);
+			     itype_exc_type[(itype & 0xf)]);
 		panic_printf("Exception is caused by %s\n",
-			itype_inst[(itype & BIT(4))]);
+			     itype_inst[(itype & BIT(4))]);
 	}
 #endif
 }
@@ -178,7 +178,7 @@ static void print_panic_information(uint32_t *regs, uint32_t itype,
 void report_panic(uint32_t *regs, uint32_t itype)
 {
 	int i;
-	struct panic_data * const pdata = get_panic_data_write();
+	struct panic_data *const pdata = get_panic_data_write();
 
 	pdata->magic = PANIC_DATA_MAGIC;
 	pdata->struct_size = CONFIG_PANIC_DATA_SIZE;
diff --git a/core/nds32/switch.S b/core/nds32/switch.S
index 13d1b14345..e7a8584ce5 100644
--- a/core/nds32/switch.S
+++ b/core/nds32/switch.S
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/nds32/task.c b/core/nds32/task.c
index 5fc86d6050..d9ea6f191f 100644
--- a/core/nds32/task.c
+++ b/core/nds32/task.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,6 +6,7 @@
 /* Task scheduling / events module for Chrome EC operating system */
 
 #include "atomic.h"
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
 #include "cpu.h"
@@ -13,6 +14,7 @@
 #include "intc.h"
 #include "irq_chip.h"
 #include "link_defs.h"
+#include "panic.h"
 #include "registers.h"
 #include "task.h"
 #include "timer.h"
@@ -24,10 +26,10 @@ typedef union {
 		 * Note that sp must be the first element in the task struct
 		 * for __switchto() to work.
 		 */
-		uint32_t sp;       /* Saved stack pointer for context switch */
-		atomic_t events;   /* Bitmaps of received events */
-		uint64_t runtime;  /* Time spent in task */
-		uint32_t *stack;   /* Start of stack */
+		uint32_t sp; /* Saved stack pointer for context switch */
+		atomic_t events; /* Bitmaps of received events */
+		uint64_t runtime; /* Time spent in task */
+		uint32_t *stack; /* Start of stack */
 	};
 } task_;
 
@@ -42,11 +44,9 @@ CONFIG_TEST_TASK_LIST
 #undef TASK
 
 /* Task names for easier debugging */
-#define TASK(n, r, d, s)  #n,
-static const char * const task_names[] = {
-	"<< idle >>",
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
+#define TASK(n, r, d, s) #n,
+static const char *const task_names[] = {
+	"<< idle >>", CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST
 };
 #undef TASK
 
@@ -54,12 +54,12 @@ static const char * const task_names[] = {
 static int task_will_switch;
 static uint32_t exc_sub_time;
 static uint64_t task_start_time; /* Time task scheduling started */
-static uint32_t exc_start_time;  /* Time of task->exception transition */
-static uint32_t exc_end_time;    /* Time of exception->task transition */
-static uint64_t exc_total_time;  /* Total time in exceptions */
-static uint32_t svc_calls;       /* Number of service calls */
-static uint32_t task_switches;   /* Number of times active task changed */
-static uint32_t irq_dist[CONFIG_IRQ_COUNT];  /* Distribution of IRQ calls */
+static uint32_t exc_start_time; /* Time of task->exception transition */
+static uint32_t exc_end_time; /* Time of exception->task transition */
+static uint64_t exc_total_time; /* Total time in exceptions */
+static uint32_t svc_calls; /* Number of service calls */
+static uint32_t task_switches; /* Number of times active task changed */
+static uint32_t irq_dist[CONFIG_IRQ_COUNT]; /* Distribution of IRQ calls */
 #endif
 
 extern int __task_start(void);
@@ -80,7 +80,7 @@ void __idle(void)
 		/* doze mode */
 		IT83XX_ECPM_PLLCTRL = EC_PLL_DOZE;
 #endif
-		asm volatile ("dsb");
+		asm volatile("dsb");
 		/*
 		 * Wait for the next irq event.  This stops the CPU clock
 		 * (sleep / deep sleep, depending on chip config).
@@ -100,20 +100,18 @@ static void task_exit_trap(void)
 }
 
 /* Startup parameters for all tasks. */
-#define TASK(n, r, d, s)  {	\
-	.r0 = (uint32_t)d,	\
-	.pc = (uint32_t)r,	\
-	.stack_size = s,	\
-},
+#define TASK(n, r, d, s)           \
+	{                          \
+		.r0 = (uint32_t)d, \
+		.pc = (uint32_t)r, \
+		.stack_size = s,   \
+	},
 static const struct {
 	uint32_t r0;
 	uint32_t pc;
 	uint16_t stack_size;
-} tasks_init[] = {
-	TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
-};
+} tasks_init[] = { TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
+			   CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST };
 #undef TASK
 
 /* Contexts for all tasks */
@@ -122,20 +120,16 @@ static task_ tasks[TASK_ID_COUNT];
 BUILD_ASSERT(TASK_ID_COUNT <= sizeof(unsigned) * 8);
 BUILD_ASSERT(TASK_ID_COUNT < (1 << (sizeof(task_id_t) * 8)));
 
-
 /* Stacks for all tasks */
-#define TASK(n, r, d, s)  + s
-uint8_t task_stacks[0
-		    TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
-		    CONFIG_TASK_LIST
-		    CONFIG_TEST_TASK_LIST
-] __aligned(8);
+#define TASK(n, r, d, s) +s
+uint8_t task_stacks[0 TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
+			    CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST] __aligned(8);
 
 #undef TASK
 
 /* Reserve space to discard context on first context switch. */
-uint32_t scratchpad[TASK_SCRATCHPAD_SIZE] __attribute__
-					((section(".bss.task_scratchpad")));
+uint32_t scratchpad[TASK_SCRATCHPAD_SIZE]
+	__attribute__((section(".bss.task_scratchpad")));
 
 task_ *current_task = (task_ *)scratchpad;
 
@@ -167,7 +161,7 @@ static atomic_t tasks_ready = BIT(TASK_ID_HOOKS);
  */
 static atomic_t tasks_enabled = BIT(TASK_ID_HOOKS) | BIT(TASK_ID_IDLE);
 
-int start_called;  /* Has task swapping started */
+int start_called; /* Has task swapping started */
 
 /* interrupt number of sw interrupt */
 static int sw_int_num;
@@ -213,22 +207,22 @@ void __ram_code interrupt_disable(void)
 {
 	/* Mask all interrupts, only keep division by zero exception */
 	uint32_t val = BIT(30);
-	asm volatile ("mtsr %0, $INT_MASK" : : "r"(val));
-	asm volatile ("dsb");
+	asm volatile("mtsr %0, $INT_MASK" : : "r"(val));
+	asm volatile("dsb");
 }
 
 void __ram_code interrupt_enable(void)
 {
 	/* Enable HW2 ~ HW15 and division by zero exception interrupts */
 	uint32_t val = (BIT(30) | 0xFFFC);
-	asm volatile ("mtsr %0, $INT_MASK" : : "r"(val));
+	asm volatile("mtsr %0, $INT_MASK" : : "r"(val));
 }
 
 inline bool is_interrupt_enabled(void)
 {
 	uint32_t val = 0;
 
-	asm volatile ("mfsr %0, $INT_MASK" : "=r"(val));
+	asm volatile("mfsr %0, $INT_MASK" : "=r"(val));
 
 	/* Interrupts are enabled if any of HW2 ~ HW15 is enabled */
 	return val & 0xFFFC;
@@ -267,7 +261,7 @@ int task_start_called(void)
  * Also includes emulation of software triggering interrupt vector
  */
 void __ram_code __keep syscall_handler(int desched, task_id_t resched,
-								int swirq)
+				       int swirq)
 {
 	/* are we emulating an interrupt ? */
 	if (swirq) {
@@ -307,7 +301,7 @@ task_ *next_sched_task(void)
 #ifdef CONFIG_TASK_PROFILING
 	if (current_task != new_task) {
 		current_task->runtime +=
-				(exc_start_time - exc_end_time - exc_sub_time);
+			(exc_start_time - exc_end_time - exc_sub_time);
 		task_will_switch = 1;
 	}
 #endif
@@ -348,7 +342,7 @@ volatile int ec_int;
 void __ram_code start_irq_handler(void)
 {
 	/* save r0, r1, and r2 for syscall */
-	asm volatile ("smw.adm $r0, [$sp], $r2, 0");
+	asm volatile("smw.adm $r0, [$sp], $r2, 0");
 	/* If this is a SW interrupt */
 	if (get_itype() & 8)
 		ec_int = sw_int_num;
@@ -369,7 +363,7 @@ void __ram_code start_irq_handler(void)
 		irq_dist[ec_int]++;
 #endif
 	/* restore r0, r1, and r2 */
-	asm volatile ("lmw.bim $r0, [$sp], $r2, 0");
+	asm volatile("lmw.bim $r0, [$sp], $r2, 0");
 }
 
 void end_irq_handler(void)
@@ -380,7 +374,7 @@ void end_irq_handler(void)
 	 * save r0 and fp (fp for restore r0-r5, r15, fp, lp and sp
 	 * while interrupt exit.
 	 */
-	asm volatile ("smw.adm $r0, [$sp], $r0, 8");
+	asm volatile("smw.adm $r0, [$sp], $r0, 8");
 
 	t = get_time().le.lo;
 	p = t - exc_start_time;
@@ -395,7 +389,7 @@ void end_irq_handler(void)
 	}
 
 	/* restore r0 and fp */
-	asm volatile ("lmw.bim $r0, [$sp], $r0, 8");
+	asm volatile("lmw.bim $r0, [$sp], $r0, 8");
 #endif
 }
 
@@ -483,37 +477,36 @@ uint32_t __ram_code read_clear_int_mask(void)
 {
 	uint32_t int_mask, int_dis = BIT(30);
 
-	asm volatile(
-		"mfsr %0, $INT_MASK\n\t"
-		"mtsr %1, $INT_MASK\n\t"
-		"dsb\n\t"
-		: "=&r"(int_mask)
-		: "r"(int_dis));
+	asm volatile("mfsr %0, $INT_MASK\n\t"
+		     "mtsr %1, $INT_MASK\n\t"
+		     "dsb\n\t"
+		     : "=&r"(int_mask)
+		     : "r"(int_dis));
 
 	return int_mask;
 }
 
 void __ram_code set_int_mask(uint32_t val)
 {
-	asm volatile ("mtsr %0, $INT_MASK" : : "r"(val));
+	asm volatile("mtsr %0, $INT_MASK" : : "r"(val));
 }
 
 static void set_int_priority(uint32_t val)
 {
-	asm volatile ("mtsr %0, $INT_PRI" : : "r"(val));
+	asm volatile("mtsr %0, $INT_PRI" : : "r"(val));
 }
 
 uint32_t get_int_ctrl(void)
 {
 	uint32_t ret;
 
-	asm volatile ("mfsr %0, $INT_CTRL" : "=r"(ret));
+	asm volatile("mfsr %0, $INT_CTRL" : "=r"(ret));
 	return ret;
 }
 
 void set_int_ctrl(uint32_t val)
 {
-	asm volatile ("mtsr %0, $INT_CTRL" : : "r"(val));
+	asm volatile("mtsr %0, $INT_CTRL" : : "r"(val));
 }
 
 void task_enable_all_tasks(void)
@@ -599,7 +592,7 @@ static void ivic_init_irqs(void)
 	for (i = 0; i < exc_calls; i++) {
 		uint8_t irq = __irqprio[i].irq;
 		uint8_t prio = __irqprio[i].priority;
-		all_priorities |= (prio & 0x3)  << (irq * 2);
+		all_priorities |= (prio & 0x3) << (irq * 2);
 	}
 	set_int_priority(all_priorities);
 }
@@ -685,7 +678,7 @@ void task_print_list(void)
 	}
 }
 
-static int command_task_info(int argc, char **argv)
+static int command_task_info(int argc, const char **argv)
 {
 #ifdef CONFIG_TASK_PROFILING
 	int total = 0;
@@ -715,11 +708,9 @@ static int command_task_info(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(taskinfo, command_task_info,
-			NULL,
-			"Print task info");
+DECLARE_CONSOLE_COMMAND(taskinfo, command_task_info, NULL, "Print task info");
 
-static int command_task_ready(int argc, char **argv)
+static int command_task_ready(int argc, const char **argv)
 {
 	if (argc < 2) {
 		ccprintf("tasks_ready: 0x%08x\n", (int)tasks_ready);
@@ -731,8 +722,7 @@ static int command_task_ready(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(taskready, command_task_ready,
-			"[setmask]",
+DECLARE_CONSOLE_COMMAND(taskready, command_task_ready, "[setmask]",
 			"Print/set ready tasks");
 
 void task_pre_init(void)
@@ -755,11 +745,11 @@ void task_pre_init(void)
 		tasks[i].sp = (uint32_t)sp;
 
 		/* Initial context on stack (see __switchto()) */
-		sp[7] = tasks_init[i].r0;           /* r0 */
-		sp[15] = (uint32_t)task_exit_trap;  /* lr */
-		sp[1] = tasks_init[i].pc;           /* pc */
-		sp[0] = 0x70009;                    /* psw */
-		sp[16] = (uint32_t)(sp + 17);       /* sp */
+		sp[7] = tasks_init[i].r0; /* r0 */
+		sp[15] = (uint32_t)task_exit_trap; /* lr */
+		sp[1] = tasks_init[i].pc; /* pc */
+		sp[0] = 0x70009; /* psw */
+		sp[16] = (uint32_t)(sp + 17); /* sp */
 
 		/* Fill unused stack; also used to detect stack overflow. */
 		for (sp = stack_next; sp < (uint32_t *)tasks[i].sp; sp++)
diff --git a/core/nds32/toolchain.mk b/core/nds32/toolchain.mk
new file mode 100644
index 0000000000..e2405d3054
--- /dev/null
+++ b/core/nds32/toolchain.mk
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Set coreboot-sdk as the default toolchain for nds32
+NDS32_DEFAULT_COMPILE=/opt/coreboot-sdk/bin/nds32le-elf-
+
+# Select Andes bare-metal toolchain
+$(call set-option,CROSS_COMPILE,$(CROSS_COMPILE_nds32),$(NDS32_DEFAULT_COMPILE))
diff --git a/core/riscv-rv32i/__builtin.c b/core/riscv-rv32i/__builtin.c
index 4bf495a011..8e2bf984ff 100644
--- a/core/riscv-rv32i/__builtin.c
+++ b/core/riscv-rv32i/__builtin.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/core/riscv-rv32i/__it8xxx2_arithmetic.S b/core/riscv-rv32i/__it8xxx2_arithmetic.S
index 8e477863fc..de6dd220ad 100644
--- a/core/riscv-rv32i/__it8xxx2_arithmetic.S
+++ b/core/riscv-rv32i/__it8xxx2_arithmetic.S
@@ -1,5 +1,5 @@
 /*
- * Copyright 2022 The ChromiumOS Authors.
+ * Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/riscv-rv32i/atomic.h b/core/riscv-rv32i/atomic.h
index 4d6114cd53..edd27f20e8 100644
--- a/core/riscv-rv32i/atomic.h
+++ b/core/riscv-rv32i/atomic.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -53,4 +53,4 @@ static inline atomic_val_t atomic_and(atomic_t *addr, atomic_val_t bits)
 	return __atomic_fetch_and(addr, bits, __ATOMIC_SEQ_CST);
 }
 
-#endif  /* __CROS_EC_ATOMIC_H */
+#endif /* __CROS_EC_ATOMIC_H */
diff --git a/core/riscv-rv32i/build.mk b/core/riscv-rv32i/build.mk
index 7e5ce0e8a7..99171a422d 100644
--- a/core/riscv-rv32i/build.mk
+++ b/core/riscv-rv32i/build.mk
@@ -1,15 +1,11 @@
 # -*- makefile -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
 # RISC-V core OS files build
 #
 
-# Select RISC-V bare-metal toolchain
-$(call set-option,CROSS_COMPILE,$(CROSS_COMPILE_riscv),\
-	/opt/coreboot-sdk/bin/riscv64-elf-)
-
 # Enable FPU extension if config option of FPU is enabled.
 _FPU_EXTENSION=$(if $(CONFIG_FPU),f,)
 # Enable the 'M' extension if config option of RISCV_EXTENSION_M is enabled.
diff --git a/core/riscv-rv32i/config_core.h b/core/riscv-rv32i/config_core.h
index fe6135683d..2adcd2783f 100644
--- a/core/riscv-rv32i/config_core.h
+++ b/core/riscv-rv32i/config_core.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/core/riscv-rv32i/cpu.c b/core/riscv-rv32i/cpu.c
index fd18896846..911d170801 100644
--- a/core/riscv-rv32i/cpu.c
+++ b/core/riscv-rv32i/cpu.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,5 +10,5 @@
 void cpu_init(void)
 {
 	/* bit3: Global interrupt enable (M-mode) */
-	asm volatile ("csrsi mstatus, 0x8");
+	asm volatile("csrsi mstatus, 0x8");
 }
diff --git a/core/riscv-rv32i/cpu.h b/core/riscv-rv32i/cpu.h
index e46b893ad6..39ee3fe126 100644
--- a/core/riscv-rv32i/cpu.h
+++ b/core/riscv-rv32i/cpu.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -25,7 +25,7 @@
 /* write Exception Program Counter register */
 static inline void set_mepc(uint32_t val)
 {
-	asm volatile ("csrw mepc, %0" : : "r"(val));
+	asm volatile("csrw mepc, %0" : : "r"(val));
 }
 
 /* read Exception Program Counter register */
@@ -33,7 +33,7 @@ static inline uint32_t get_mepc(void)
 {
 	uint32_t ret;
 
-	asm volatile ("csrr %0, mepc" : "=r"(ret));
+	asm volatile("csrr %0, mepc" : "=r"(ret));
 	return ret;
 }
 
@@ -42,7 +42,7 @@ static inline uint32_t get_mcause(void)
 {
 	uint32_t ret;
 
-	asm volatile ("csrr %0, mcause" : "=r"(ret));
+	asm volatile("csrr %0, mcause" : "=r"(ret));
 	return ret;
 }
 
diff --git a/core/riscv-rv32i/ec.lds.S b/core/riscv-rv32i/ec.lds.S
index 1e629a5779..e62a7d1427 100644
--- a/core/riscv-rv32i/ec.lds.S
+++ b/core/riscv-rv32i/ec.lds.S
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -233,6 +233,10 @@ SECTIONS
 		KEEP(*(.rodata.HOOK_USB_PD_CONNECT))
 		__hooks_usb_pd_connect_end = .;
 
+		__hooks_power_supply_change = .;
+		KEEP(*(.rodata.HOOK_POWER_SUPPLY_CHANGE))
+		__hooks_power_supply_change_end = .;
+
 		__deferred_funcs = .;
 		KEEP(*(.rodata.deferred))
 		__deferred_funcs_end = .;
@@ -334,6 +338,12 @@ SECTIONS
 		__bss_end = .;
 
 		/*
+		 * _sbrk in newlib expects "end" symbol to point to start of
+		 * free memory.
+		 */
+		end = .;
+
+		/*
 		 * Shared memory buffer must be at the end of preallocated RAM,
 		 * so it can expand to use all the remaining RAM.
 		 */
diff --git a/core/riscv-rv32i/include/fpu.h b/core/riscv-rv32i/include/fpu.h
index 25d83f228f..da48139d1c 100644
--- a/core/riscv-rv32i/include/fpu.h
+++ b/core/riscv-rv32i/include/fpu.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,4 +10,4 @@
 
 float sqrtf(float x);
 
-#endif  /* __CROS_EC_FPU_H */
+#endif /* __CROS_EC_FPU_H */
diff --git a/core/riscv-rv32i/init.S b/core/riscv-rv32i/init.S
index 8ee5479e0e..6231ad94c0 100644
--- a/core/riscv-rv32i/init.S
+++ b/core/riscv-rv32i/init.S
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/riscv-rv32i/irq_chip.h b/core/riscv-rv32i/irq_chip.h
index 45cabf346e..b45a754f45 100644
--- a/core/riscv-rv32i/irq_chip.h
+++ b/core/riscv-rv32i/irq_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/riscv-rv32i/irq_handler.h b/core/riscv-rv32i/irq_handler.h
index 6fe7769684..b980e8e0bc 100644
--- a/core/riscv-rv32i/irq_handler.h
+++ b/core/riscv-rv32i/irq_handler.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,12 +20,12 @@
  * Macro to connect the interrupt handler "routine" to the irq number "irq" and
  * ensure it is enabled in the interrupt controller with the right priority.
  */
-#define DECLARE_IRQ(irq, routine, priority)				\
-	static void __keep routine(void);				\
-	void IRQ_HANDLER(CPU_INT(irq))(void)				\
-		__attribute__ ((alias(STRINGIFY(routine))));		\
-	const struct irq_priority __keep IRQ_PRIORITY(CPU_INT(irq))	\
-	__attribute__((section(".rodata.irqprio")))			\
-			= {CPU_INT(irq), priority}
+#define DECLARE_IRQ(irq, routine, priority)                                   \
+	static void __keep routine(void);                                     \
+	void IRQ_HANDLER(CPU_INT(irq))(void)                                  \
+		__attribute__((alias(STRINGIFY(routine))));                   \
+	const struct irq_priority __keep IRQ_PRIORITY(CPU_INT(irq))           \
+		__attribute__((section(".rodata.irqprio"))) = { CPU_INT(irq), \
+								priority }
 
-#endif  /* __CROS_EC_IRQ_HANDLER_H */
+#endif /* __CROS_EC_IRQ_HANDLER_H */
diff --git a/core/riscv-rv32i/math.c b/core/riscv-rv32i/math.c
index 591a67eb8f..425814f185 100644
--- a/core/riscv-rv32i/math.c
+++ b/core/riscv-rv32i/math.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,10 +9,7 @@
 /* Single precision floating point square root. */
 float sqrtf(float x)
 {
-	asm volatile (
-		"fsqrt.s %0, %1"
-		: "=f" (x)
-		: "f" (x));
+	asm volatile("fsqrt.s %0, %1" : "=f"(x) : "f"(x));
 
 	return x;
 }
diff --git a/core/riscv-rv32i/panic.c b/core/riscv-rv32i/panic.c
index 5860fba072..a2ce9213d9 100644
--- a/core/riscv-rv32i/panic.c
+++ b/core/riscv-rv32i/panic.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,7 +13,7 @@
 /**
  * bit[3-0] @ mcause, general exception type information.
  */
-static const char * const exc_type[16] = {
+static const char *const exc_type[16] = {
 	"Instruction address misaligned",
 	"Instruction access fault",
 	"Illegal instruction",
@@ -38,12 +38,12 @@ static const char * const exc_type[16] = {
 /* General purpose register (s0) for saving software panic reason */
 #define SOFT_PANIC_GPR_REASON 11
 /* General purpose register (s1) for saving software panic information */
-#define SOFT_PANIC_GPR_INFO   10
+#define SOFT_PANIC_GPR_INFO 10
 
 void software_panic(uint32_t reason, uint32_t info)
 {
-	asm volatile ("mv s0, %0" : : "r"(reason) : "s0");
-	asm volatile ("mv s1, %0" : : "r"(info)   : "s1");
+	asm volatile("mv s0, %0" : : "r"(reason) : "s0");
+	asm volatile("mv s1, %0" : : "r"(info) : "s1");
 	if (in_interrupt_context())
 		asm("j excep_handler");
 	else
@@ -58,7 +58,7 @@ void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
 	 * If it was called earlier (eg. when saving riscv.mepc) calling it
 	 * once again won't remove any data
 	 */
-	struct panic_data * const pdata = get_panic_data_write();
+	struct panic_data *const pdata = get_panic_data_write();
 	uint32_t warning_mepc;
 	uint32_t *regs;
 
@@ -85,7 +85,7 @@ void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
 
 void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception)
 {
-	struct panic_data * const pdata = panic_get_data();
+	struct panic_data *const pdata = panic_get_data();
 	uint32_t *regs;
 
 	if (pdata && pdata->struct_version == 2) {
@@ -100,34 +100,34 @@ void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception)
 #endif /* CONFIG_SOFTWARE_PANIC */
 
 static void print_panic_information(uint32_t *regs, uint32_t mcause,
-					uint32_t mepc)
+				    uint32_t mepc)
 {
 	panic_printf("=== EXCEPTION: MCAUSE=%x ===\n", mcause);
-	panic_printf("S11 %08x S10 %08x  S9 %08x  S8   %08x\n",
-		     regs[0], regs[1], regs[2], regs[3]);
-	panic_printf("S7  %08x S6  %08x  S5 %08x  S4   %08x\n",
-		     regs[4], regs[5], regs[6], regs[7]);
-	panic_printf("S3  %08x S2  %08x  S1 %08x  S0   %08x\n",
-		     regs[8], regs[9], regs[10], regs[11]);
-	panic_printf("T6  %08x T5  %08x  T4 %08x  T3   %08x\n",
-		     regs[12], regs[13], regs[14], regs[15]);
-	panic_printf("T2  %08x T1  %08x  T0 %08x  A7   %08x\n",
-		     regs[16], regs[17], regs[18], regs[19]);
-	panic_printf("A6  %08x A5  %08x  A4 %08x  A3   %08x\n",
-		     regs[20], regs[21], regs[22], regs[23]);
-	panic_printf("A2  %08x A1  %08x  A0 %08x  TP   %08x\n",
-		     regs[24], regs[25], regs[26], regs[27]);
-	panic_printf("GP  %08x RA  %08x  SP %08x  MEPC %08x\n",
-		     regs[28], regs[29], regs[30], mepc);
+	panic_printf("S11 %08x S10 %08x  S9 %08x  S8   %08x\n", regs[0],
+		     regs[1], regs[2], regs[3]);
+	panic_printf("S7  %08x S6  %08x  S5 %08x  S4   %08x\n", regs[4],
+		     regs[5], regs[6], regs[7]);
+	panic_printf("S3  %08x S2  %08x  S1 %08x  S0   %08x\n", regs[8],
+		     regs[9], regs[10], regs[11]);
+	panic_printf("T6  %08x T5  %08x  T4 %08x  T3   %08x\n", regs[12],
+		     regs[13], regs[14], regs[15]);
+	panic_printf("T2  %08x T1  %08x  T0 %08x  A7   %08x\n", regs[16],
+		     regs[17], regs[18], regs[19]);
+	panic_printf("A6  %08x A5  %08x  A4 %08x  A3   %08x\n", regs[20],
+		     regs[21], regs[22], regs[23]);
+	panic_printf("A2  %08x A1  %08x  A0 %08x  TP   %08x\n", regs[24],
+		     regs[25], regs[26], regs[27]);
+	panic_printf("GP  %08x RA  %08x  SP %08x  MEPC %08x\n", regs[28],
+		     regs[29], regs[30], mepc);
 
 #ifdef CONFIG_DEBUG_EXCEPTIONS
 	if ((regs[SOFT_PANIC_GPR_REASON] & 0xfffffff0) == PANIC_SW_BASE) {
 #ifdef CONFIG_SOFTWARE_PANIC
 		panic_printf("Software panic reason: %s\n",
-			panic_sw_reasons[(regs[SOFT_PANIC_GPR_REASON] -
-						PANIC_SW_BASE)]);
+			     panic_sw_reasons[(regs[SOFT_PANIC_GPR_REASON] -
+					       PANIC_SW_BASE)]);
 		panic_printf("Software panic info:   %d\n",
-			regs[SOFT_PANIC_GPR_INFO]);
+			     regs[SOFT_PANIC_GPR_INFO]);
 #endif
 	} else {
 		panic_printf("Exception type: %s\n", exc_type[(mcause & 0xf)]);
@@ -138,7 +138,7 @@ static void print_panic_information(uint32_t *regs, uint32_t mcause,
 void report_panic(uint32_t *regs)
 {
 	uint32_t i, mcause, mepc;
-	struct panic_data * const pdata = get_panic_data_write();
+	struct panic_data *const pdata = get_panic_data_write();
 
 	mepc = get_mepc();
 	mcause = get_mcause();
@@ -171,36 +171,36 @@ void panic_data_print(const struct panic_data *pdata)
 
 #ifdef CONFIG_PANIC_CONSOLE_OUTPUT
 static void ccprint_panic_information(uint32_t *regs, uint32_t mcause,
-					uint32_t mepc)
+				      uint32_t mepc)
 {
 	ccprintf("=== EXCEPTION: MCAUSE=%x ===\n", mcause);
-	ccprintf("S11 %08x S10 %08x  S9 %08x  S8   %08x\n",
-		     regs[0], regs[1], regs[2], regs[3]);
-	ccprintf("S7  %08x S6  %08x  S5 %08x  S4   %08x\n",
-		     regs[4], regs[5], regs[6], regs[7]);
-	ccprintf("S3  %08x S2  %08x  S1 %08x  S0   %08x\n",
-		     regs[8], regs[9], regs[10], regs[11]);
-	ccprintf("T6  %08x T5  %08x  T4 %08x  T3   %08x\n",
-		     regs[12], regs[13], regs[14], regs[15]);
-	ccprintf("T2  %08x T1  %08x  T0 %08x  A7   %08x\n",
-		     regs[16], regs[17], regs[18], regs[19]);
+	ccprintf("S11 %08x S10 %08x  S9 %08x  S8   %08x\n", regs[0], regs[1],
+		 regs[2], regs[3]);
+	ccprintf("S7  %08x S6  %08x  S5 %08x  S4   %08x\n", regs[4], regs[5],
+		 regs[6], regs[7]);
+	ccprintf("S3  %08x S2  %08x  S1 %08x  S0   %08x\n", regs[8], regs[9],
+		 regs[10], regs[11]);
+	ccprintf("T6  %08x T5  %08x  T4 %08x  T3   %08x\n", regs[12], regs[13],
+		 regs[14], regs[15]);
+	ccprintf("T2  %08x T1  %08x  T0 %08x  A7   %08x\n", regs[16], regs[17],
+		 regs[18], regs[19]);
 	cflush();
 
-	ccprintf("A6  %08x A5  %08x  A4 %08x  A3   %08x\n",
-		     regs[20], regs[21], regs[22], regs[23]);
-	ccprintf("A2  %08x A1  %08x  A0 %08x  TP   %08x\n",
-		     regs[24], regs[25], regs[26], regs[27]);
-	ccprintf("GP  %08x RA  %08x  SP %08x  MEPC %08x\n",
-		     regs[28], regs[29], regs[30], mepc);
+	ccprintf("A6  %08x A5  %08x  A4 %08x  A3   %08x\n", regs[20], regs[21],
+		 regs[22], regs[23]);
+	ccprintf("A2  %08x A1  %08x  A0 %08x  TP   %08x\n", regs[24], regs[25],
+		 regs[26], regs[27]);
+	ccprintf("GP  %08x RA  %08x  SP %08x  MEPC %08x\n", regs[28], regs[29],
+		 regs[30], mepc);
 
 #ifdef CONFIG_DEBUG_EXCEPTIONS
 	if ((regs[SOFT_PANIC_GPR_REASON] & 0xfffffff0) == PANIC_SW_BASE) {
 #ifdef CONFIG_SOFTWARE_PANIC
 		ccprintf("Software panic reason: %s\n",
-			panic_sw_reasons[(regs[SOFT_PANIC_GPR_REASON] -
-						PANIC_SW_BASE)]);
+			 panic_sw_reasons[(regs[SOFT_PANIC_GPR_REASON] -
+					   PANIC_SW_BASE)]);
 		ccprintf("Software panic info:   %d\n",
-			regs[SOFT_PANIC_GPR_INFO]);
+			 regs[SOFT_PANIC_GPR_INFO]);
 #endif /* CONFIG_SOFTWARE_PANIC */
 	} else {
 		ccprintf("Exception type: %s\n", exc_type[(mcause & 0xf)]);
diff --git a/core/riscv-rv32i/switch.S b/core/riscv-rv32i/switch.S
index f58ac26e63..f8b88f9235 100644
--- a/core/riscv-rv32i/switch.S
+++ b/core/riscv-rv32i/switch.S
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/core/riscv-rv32i/task.c b/core/riscv-rv32i/task.c
index edc31a872e..84415dcda9 100644
--- a/core/riscv-rv32i/task.c
+++ b/core/riscv-rv32i/task.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,10 +6,12 @@
 /* Task scheduling / events module for Chrome EC operating system */
 
 #include "atomic.h"
+#include "builtin/assert.h"
 #include "console.h"
 #include "cpu.h"
 #include "irq_chip.h"
 #include "link_defs.h"
+#include "panic.h"
 #include "task.h"
 #include "timer.h"
 #include "util.h"
@@ -19,10 +21,10 @@ typedef struct {
 	 * Note that sp must be the first element in the task struct
 	 * for __switchto() to work.
 	 */
-	uint32_t sp;       /* Saved stack pointer for context switch */
-	atomic_t events;   /* Bitmaps of received events */
-	uint64_t runtime;  /* Time spent in task */
-	uint32_t *stack;   /* Start of stack */
+	uint32_t sp; /* Saved stack pointer for context switch */
+	atomic_t events; /* Bitmaps of received events */
+	uint64_t runtime; /* Time spent in task */
+	uint32_t *stack; /* Start of stack */
 } task_;
 
 /* Value to store in unused stack */
@@ -36,11 +38,9 @@ CONFIG_TEST_TASK_LIST
 #undef TASK
 
 /* Task names for easier debugging */
-#define TASK(n, r, d, s)  #n,
-static const char * const task_names[] = {
-	"<< idle >>",
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
+#define TASK(n, r, d, s) #n,
+static const char *const task_names[] = {
+	"<< idle >>", CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST
 };
 #undef TASK
 
@@ -48,12 +48,12 @@ static const char * const task_names[] = {
 static int task_will_switch;
 static uint32_t exc_sub_time;
 static uint64_t task_start_time; /* Time task scheduling started */
-static uint32_t exc_start_time;  /* Time of task->exception transition */
-static uint32_t exc_end_time;    /* Time of exception->task transition */
-static uint64_t exc_total_time;  /* Total time in exceptions */
-static uint32_t svc_calls;       /* Number of service calls */
-static uint32_t task_switches;   /* Number of times active task changed */
-static uint32_t irq_dist[CONFIG_IRQ_COUNT];  /* Distribution of IRQ calls */
+static uint32_t exc_start_time; /* Time of task->exception transition */
+static uint32_t exc_end_time; /* Time of exception->task transition */
+static uint64_t exc_total_time; /* Total time in exceptions */
+static uint32_t svc_calls; /* Number of service calls */
+static uint32_t task_switches; /* Number of times active task changed */
+static uint32_t irq_dist[CONFIG_IRQ_COUNT]; /* Distribution of IRQ calls */
 #endif
 
 extern int __task_start(void);
@@ -96,41 +96,36 @@ static void task_exit_trap(void)
 }
 
 /* Startup parameters for all tasks. */
-#define TASK(n, r, d, s)  {	\
-	.a0 = (uint32_t)d,	\
-	.pc = (uint32_t)r,	\
-	.stack_size = s,	\
-},
+#define TASK(n, r, d, s)           \
+	{                          \
+		.a0 = (uint32_t)d, \
+		.pc = (uint32_t)r, \
+		.stack_size = s,   \
+	},
 static const struct {
 	uint32_t a0;
 	uint32_t pc;
 	uint16_t stack_size;
-} tasks_init[] = {
-	TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
-	CONFIG_TASK_LIST
-	CONFIG_TEST_TASK_LIST
-};
+} tasks_init[] = { TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
+			   CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST };
 #undef TASK
 
 /* Contexts for all tasks */
-static task_ tasks[TASK_ID_COUNT] __attribute__ ((section(".bss.tasks")));
+static task_ tasks[TASK_ID_COUNT] __attribute__((section(".bss.tasks")));
 /* Validity checks about static task invariants */
 BUILD_ASSERT(TASK_ID_COUNT <= (sizeof(unsigned) * 8));
 BUILD_ASSERT(TASK_ID_COUNT < (1 << (sizeof(task_id_t) * 8)));
 
 /* Stacks for all tasks */
-#define TASK(n, r, d, s)  + s
-uint8_t task_stacks[0
-		    TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
-		    CONFIG_TASK_LIST
-		    CONFIG_TEST_TASK_LIST
-] __aligned(8);
+#define TASK(n, r, d, s) +s
+uint8_t task_stacks[0 TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE)
+			    CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST] __aligned(8);
 
 #undef TASK
 
 /* Reserve space to discard context on first context switch. */
-uint32_t scratchpad[TASK_SCRATCHPAD_SIZE] __attribute__
-					((section(".bss.task_scratchpad")));
+uint32_t scratchpad[TASK_SCRATCHPAD_SIZE]
+	__attribute__((section(".bss.task_scratchpad")));
 
 task_ *current_task = (task_ *)scratchpad;
 
@@ -162,7 +157,7 @@ static atomic_t tasks_ready = BIT(TASK_ID_HOOKS);
  */
 static atomic_t tasks_enabled = BIT(TASK_ID_HOOKS) | BIT(TASK_ID_IDLE);
 
-int start_called;  /* Has task swapping started */
+int start_called; /* Has task swapping started */
 
 /* in interrupt context */
 volatile bool in_interrupt;
@@ -188,22 +183,22 @@ static inline task_ *__task_id_to_ptr(task_id_t id)
 void __ram_code interrupt_disable(void)
 {
 	/* bit11: disable MEIE */
-	asm volatile ("li t0, 0x800");
-	asm volatile ("csrc mie, t0");
+	asm volatile("li t0, 0x800");
+	asm volatile("csrc mie, t0");
 }
 
 void __ram_code interrupt_enable(void)
 {
 	/* bit11: enable MEIE */
-	asm volatile ("li t0, 0x800");
-	asm volatile ("csrs  mie, t0");
+	asm volatile("li t0, 0x800");
+	asm volatile("csrs  mie, t0");
 }
 
 inline bool is_interrupt_enabled(void)
 {
 	int mie = 0;
 
-	asm volatile ("csrr %0, mie" : "=r"(mie));
+	asm volatile("csrr %0, mie" : "=r"(mie));
 
 	/* Check if MEIE bit is set in MIE register */
 	return mie & 0x800;
@@ -229,7 +224,7 @@ task_id_t __ram_code task_get_current(void)
 	return current_task - tasks;
 }
 
-atomic_t * __ram_code task_get_event_bitmap(task_id_t tskid)
+atomic_t *__ram_code task_get_event_bitmap(task_id_t tskid)
 {
 	task_ *tsk = __task_id_to_ptr(tskid);
 
@@ -247,7 +242,7 @@ int task_start_called(void)
  * Also includes emulation of software triggering interrupt vector
  */
 void __ram_code __keep syscall_handler(int desched, task_id_t resched,
-								int swirq)
+				       int swirq)
 {
 	/* are we emulating an interrupt ? */
 	if (swirq) {
@@ -279,14 +274,14 @@ void __ram_code __keep syscall_handler(int desched, task_id_t resched,
 	set_mepc(get_mepc() + 4);
 }
 
-task_ * __ram_code next_sched_task(void)
+task_ *__ram_code next_sched_task(void)
 {
 	task_ *new_task = __task_id_to_ptr(__fls(tasks_ready & tasks_enabled));
 
 #ifdef CONFIG_TASK_PROFILING
 	if (current_task != new_task) {
 		current_task->runtime +=
-				(exc_start_time - exc_end_time - exc_sub_time);
+			(exc_start_time - exc_end_time - exc_sub_time);
 		task_will_switch = 1;
 	}
 #endif
@@ -466,14 +461,14 @@ uint32_t __ram_code read_clear_int_mask(void)
 	uint32_t mie, meie = BIT(11);
 
 	/* Read and clear MEIE bit of MIE register. */
-	asm volatile ("csrrc %0, mie, %1" : "=r"(mie) : "r"(meie));
+	asm volatile("csrrc %0, mie, %1" : "=r"(mie) : "r"(meie));
 
 	return mie;
 }
 
 void __ram_code set_int_mask(uint32_t val)
 {
-	asm volatile ("csrw mie, %0" : : "r"(val));
+	asm volatile("csrw mie, %0" : : "r"(val));
 }
 
 void task_enable_all_tasks(void)
@@ -553,12 +548,12 @@ void __ram_code mutex_lock(struct mutex *mtx)
 	atomic_or(&mtx->waiters, id);
 
 	while (1) {
-		asm volatile (
+		asm volatile(
 			/* set lock value */
 			"li %0, 2\n\t"
 			/* attempt to acquire lock */
 			"amoswap.w.aq %0, %0, %1\n\t"
-			: "=&r" (locked), "+A" (mtx->lock));
+			: "=&r"(locked), "+A"(mtx->lock));
 		/* we got it ! */
 		if (!locked)
 			break;
@@ -576,9 +571,7 @@ void __ram_code mutex_unlock(struct mutex *mtx)
 	task_ *tsk = current_task;
 
 	/* give back the lock */
-	asm volatile (
-		"amoswap.w.aqrl zero, zero, %0\n\t"
-		: "+A" (mtx->lock));
+	asm volatile("amoswap.w.aqrl zero, zero, %0\n\t" : "+A"(mtx->lock));
 	waiters = mtx->waiters;
 
 	while (waiters) {
@@ -618,7 +611,7 @@ void task_print_list(void)
 	}
 }
 
-static int command_task_info(int argc, char **argv)
+static int command_task_info(int argc, const char **argv)
 {
 #ifdef CONFIG_TASK_PROFILING
 	unsigned int total = 0;
@@ -648,11 +641,9 @@ static int command_task_info(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(taskinfo, command_task_info,
-			NULL,
-			"Print task info");
+DECLARE_CONSOLE_COMMAND(taskinfo, command_task_info, NULL, "Print task info");
 
-static int command_task_ready(int argc, char **argv)
+static int command_task_ready(int argc, const char **argv)
 {
 	if (argc < 2) {
 		ccprintf("tasks_ready: 0x%08x\n", (int)tasks_ready);
@@ -664,8 +655,7 @@ static int command_task_ready(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(taskready, command_task_ready,
-			"[setmask]",
+DECLARE_CONSOLE_COMMAND(taskready, command_task_ready, "[setmask]",
 			"Print/set ready tasks");
 
 void task_pre_init(void)
@@ -688,9 +678,10 @@ void task_pre_init(void)
 		tasks[i].sp = (uint32_t)sp;
 
 		/* Initial context on stack (see __switchto()) */
-		sp[TASK_SCRATCHPAD_SIZE-2] = tasks_init[i].a0;         /* a0 */
-		sp[TASK_SCRATCHPAD_SIZE-1] = (uint32_t)task_exit_trap; /* ra */
-		sp[0] = tasks_init[i].pc;  /* pc/mepc */
+		sp[TASK_SCRATCHPAD_SIZE - 2] = tasks_init[i].a0; /* a0 */
+		sp[TASK_SCRATCHPAD_SIZE - 1] = (uint32_t)task_exit_trap; /* ra
+									  */
+		sp[0] = tasks_init[i].pc; /* pc/mepc */
 
 		/* Fill unused stack; also used to detect stack overflow. */
 		for (sp = stack_next; sp < (uint32_t *)tasks[i].sp; sp++)
diff --git a/core/riscv-rv32i/toolchain.mk b/core/riscv-rv32i/toolchain.mk
new file mode 100644
index 0000000000..aa833d1ca3
--- /dev/null
+++ b/core/riscv-rv32i/toolchain.mk
@@ -0,0 +1,7 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Select RISC-V bare-metal toolchain
+$(call set-option,CROSS_COMPILE,$(CROSS_COMPILE_riscv),\
+	/opt/coreboot-sdk/bin/riscv64-elf-)
diff --git a/cts/build.mk b/cts/build.mk
index 817b69b25c..44db306f40 100644
--- a/cts/build.mk
+++ b/cts/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/cts/common/board.py b/cts/common/board.py
index d2c8e02b04..3f92ff50ad 100644
--- a/cts/common/board.py
+++ b/cts/common/board.py
@@ -1,388 +1,421 @@
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
 
 # Note: This is a py2/3 compatible file.
 
 from __future__ import print_function
 
-from abc import ABCMeta
-from abc import abstractmethod
 import os
 import shutil
 import subprocess as sp
-import serial
+from abc import ABCMeta, abstractmethod
 
+import serial  # pylint:disable=import-error
 import six
 
-
-OCD_SCRIPT_DIR = '/usr/share/openocd/scripts'
+OCD_SCRIPT_DIR = "/usr/share/openocd/scripts"
 OPENOCD_CONFIGS = {
-    'stm32l476g-eval': 'board/stm32l4discovery.cfg',
-    'nucleo-f072rb': 'board/st_nucleo_f0.cfg',
-    'nucleo-f411re': 'board/st_nucleo_f4.cfg',
+    "stm32l476g-eval": "board/stm32l4discovery.cfg",
+    "nucleo-f072rb": "board/st_nucleo_f0.cfg",
+    "nucleo-f411re": "board/st_nucleo_f4.cfg",
 }
 FLASH_OFFSETS = {
-    'stm32l476g-eval': '0x08000000',
-    'nucleo-f072rb': '0x08000000',
-    'nucleo-f411re': '0x08000000',
+    "stm32l476g-eval": "0x08000000",
+    "nucleo-f072rb": "0x08000000",
+    "nucleo-f411re": "0x08000000",
 }
-REBOOT_MARKER = 'UART initialized after reboot'
+REBOOT_MARKER = "UART initialized after reboot"
 
 
 def get_subprocess_args():
-  if six.PY3:
-    return {'encoding': 'utf-8'}
-  return {}
+    if six.PY3:
+        return {"encoding": "utf-8"}
+    return {}
 
 
 class Board(six.with_metaclass(ABCMeta, object)):
-  """Class representing a single board connected to a host machine.
-
-  Attributes:
-    board: String containing actual type of board, i.e. nucleo-f072rb
-    config: Directory of board config file relative to openocd's
-        scripts directory
-    hla_serial: String containing board's hla_serial number (if board
-    is an stm32 board)
-    tty_port: String that is the path to the tty port which board's
-        UART outputs to
-    tty: String of file descriptor for tty_port
-  """
-
-  def __init__(self, board, module, hla_serial=None):
-    """Initializes a board object with given attributes.
-
-    Args:
-      board: String containing board name
-      module: String of the test module you are building,
-        i.e. gpio, timer, etc.
-      hla_serial: Serial number if board's adaptor is an HLA
-
-    Raises:
-      RuntimeError: Board is not supported
-    """
-    if board not in OPENOCD_CONFIGS:
-      msg = 'OpenOcd configuration not found for ' + board
-      raise RuntimeError(msg)
-    if board not in FLASH_OFFSETS:
-      msg = 'Flash offset not found for ' + board
-      raise RuntimeError(msg)
-    self.board = board
-    self.flash_offset = FLASH_OFFSETS[self.board]
-    self.openocd_config = OPENOCD_CONFIGS[self.board]
-    self.module = module
-    self.hla_serial = hla_serial
-    self.tty_port = None
-    self.tty = None
-
-  def reset_log_dir(self):
-    """Reset log directory."""
-    if os.path.isdir(self.log_dir):
-      shutil.rmtree(self.log_dir)
-    os.makedirs(self.log_dir)
-
-  @staticmethod
-  def get_stlink_serials():
-    """Gets serial numbers of all st-link v2.1 board attached to host.
-
-    Returns:
-      List of serials
+    """Class representing a single board connected to a host machine.
+
+    Attributes:
+      board: String containing actual type of board, i.e. nucleo-f072rb
+      config: Directory of board config file relative to openocd's
+          scripts directory
+      hla_serial: String containing board's hla_serial number (if board
+      is an stm32 board)
+      tty_port: String that is the path to the tty port which board's
+          UART outputs to
+      tty: String of file descriptor for tty_port
     """
-    usb_args = ['sudo', 'lsusb', '-v', '-d', '0x0483:0x374b']
-    st_link_info = sp.check_output(usb_args, **get_subprocess_args())
-    st_serials = []
-    for line in st_link_info.split('\n'):
-      if 'iSerial' not in line:
-        continue
-      words = line.split()
-      if len(words) <= 2:
-        continue
-      st_serials.append(words[2].strip())
-    return st_serials
-
-  @abstractmethod
-  def get_serial(self):
-    """Subclass should implement this."""
-    pass
-
-  def send_openocd_commands(self, commands):
-    """Send a command to the board via openocd.
-
-    Args:
-      commands: A list of commands to send
-
-    Returns:
-      True if execution is successful or False otherwise.
-    """
-    args = ['sudo', 'openocd', '-s', OCD_SCRIPT_DIR,
-            '-f', self.openocd_config, '-c', 'hla_serial ' + self.hla_serial]
-
-    for cmd in commands:
-      args += ['-c', cmd]
-    args += ['-c', 'shutdown']
-
-    rv = 1
-    with open(self.openocd_log, 'a') as output:
-      rv = sp.call(args, stdout=output, stderr=sp.STDOUT)
-
-    if rv != 0:
-      self.dump_openocd_log()
-
-    return rv == 0
 
-  def dump_openocd_log(self):
-    with open(self.openocd_log) as log:
-      print(log.read())
-
-  def build(self, ec_dir):
-    """Builds test suite module for board.
-
-    Args:
-      ec_dir: String of the ec directory path
-
-    Returns:
-      True if build is successful or False otherwise.
-    """
-    cmds = ['make',
-            '--directory=' + ec_dir,
-            'BOARD=' + self.board,
-            'CTS_MODULE=' + self.module,
-            '-j']
-
-    rv = 1
-    with open(self.build_log, 'a') as output:
-      rv = sp.call(cmds, stdout=output, stderr=sp.STDOUT)
-
-    if rv != 0:
-      self.dump_build_log()
-
-    return rv == 0
-
-  def dump_build_log(self):
-    with open(self.build_log) as log:
-      print(log.read())
-
-  def flash(self, image_path):
-    """Flashes board with most recent build ec.bin."""
-    cmd = ['reset_config connect_assert_srst',
-           'init',
-           'reset init',
-           'flash write_image erase %s %s' % (image_path, self.flash_offset)]
-    return self.send_openocd_commands(cmd)
-
-  def to_string(self):
-    s = ('Type: Board\n'
-         'board: ' + self.board + '\n'
-         'hla_serial: ' + self.hla_serial + '\n'
-         'openocd_config: ' + self.openocd_config + '\n'
-         'tty_port: ' + self.tty_port + '\n'
-         'tty: ' + str(self.tty) + '\n')
-    return s
-
-  def reset_halt(self):
-    """Reset then halt board."""
-    return self.send_openocd_commands(['init', 'reset halt'])
-
-  def resume(self):
-    """Resume halting board."""
-    return self.send_openocd_commands(['init', 'resume'])
-
-  def setup_tty(self):
-    """Call this before calling read_tty for the first time.
-
-    This is not in the initialization because caller only should call
-    this function after serial numbers are setup
-    """
-    self.get_serial()
-    self.reset_halt()
-    self.identify_tty_port()
-
-    tty = None
-    try:
-      tty = serial.Serial(self.tty_port, 115200, timeout=1)
-    except serial.SerialException:
-      raise ValueError('Failed to open ' + self.tty_port + ' of ' + self.board +
-                       '. Please make sure the port is available and you have' +
-                       ' permission to read it. Create dialout group and run:' +
-                       ' sudo usermod -a -G dialout <username>.')
-    self.tty = tty
-
-  def read_tty(self, max_boot_count=1):
-    """Read info from a serial port described by a file descriptor.
-
-    Args:
-      max_boot_count: Stop reading if boot count exceeds this number
-
-    Returns:
-      result: characters read from tty
-      boot: boot counts
-    """
-    buf = []
-    line = []
-    boot = 0
-    while True:
-      c = self.tty.read().decode('utf-8')
-      if not c:
-        break
-      line.append(c)
-      if c == '\n':
-        l = ''.join(line)
-        buf.append(l)
-        if REBOOT_MARKER in l:
-          boot += 1
+    def __init__(self, board, module, hla_serial=None):
+        """Initializes a board object with given attributes.
+
+        Args:
+          board: String containing board name
+          module: String of the test module you are building,
+            i.e. gpio, timer, etc.
+          hla_serial: Serial number if board's adaptor is an HLA
+
+        Raises:
+          RuntimeError: Board is not supported
+        """
+        if board not in OPENOCD_CONFIGS:
+            msg = "OpenOcd configuration not found for " + board
+            raise RuntimeError(msg)
+        if board not in FLASH_OFFSETS:
+            msg = "Flash offset not found for " + board
+            raise RuntimeError(msg)
+        self.board = board
+        self.flash_offset = FLASH_OFFSETS[self.board]
+        self.openocd_config = OPENOCD_CONFIGS[self.board]
+        self.module = module
+        self.hla_serial = hla_serial
+        self.tty_port = None
+        self.tty = None
+        self.log_dir = None
+        self.openocd_log = os.devnull
+        self.build_log = os.devnull
+
+    def reset_log_dir(self):
+        """Reset log directory."""
+        if self.log_dir:
+            if os.path.isdir(self.log_dir):
+                shutil.rmtree(self.log_dir)
+            os.makedirs(self.log_dir)
+
+    @staticmethod
+    def get_stlink_serials():
+        """Gets serial numbers of all st-link v2.1 board attached to host.
+
+        Returns:
+          List of serials
+        """
+        usb_args = ["sudo", "lsusb", "-v", "-d", "0x0483:0x374b"]
+        st_link_info = sp.check_output(usb_args, **get_subprocess_args())
+        st_serials = []
+        for line in st_link_info.split("\n"):
+            if "iSerial" not in line:
+                continue
+            words = line.split()
+            if len(words) <= 2:
+                continue
+            st_serials.append(words[2].strip())
+        return st_serials
+
+    @abstractmethod
+    def get_serial(self):
+        """Subclass should implement this."""
+        pass
+
+    def send_openocd_commands(self, commands):
+        """Send a command to the board via openocd.
+
+        Args:
+          commands: A list of commands to send
+
+        Returns:
+          True if execution is successful or False otherwise.
+        """
+        args = [
+            "sudo",
+            "openocd",
+            "-s",
+            OCD_SCRIPT_DIR,
+            "-f",
+            self.openocd_config,
+            "-c",
+            "hla_serial " + self.hla_serial,
+        ]
+
+        for cmd in commands:
+            args += ["-c", cmd]
+        args += ["-c", "shutdown"]
+
+        rv = 1
+        with open(self.openocd_log, "a") as output:
+            rv = sp.call(args, stdout=output, stderr=sp.STDOUT)
+
+        if rv != 0:
+            self.dump_openocd_log()
+
+        return rv == 0
+
+    def dump_openocd_log(self):
+        with open(self.openocd_log) as log:
+            print(log.read())
+
+    def build(self, ec_dir):
+        """Builds test suite module for board.
+
+        Args:
+          ec_dir: String of the ec directory path
+
+        Returns:
+          True if build is successful or False otherwise.
+        """
+        cmds = [
+            "make",
+            "--directory=" + ec_dir,
+            "BOARD=" + self.board,
+            "CTS_MODULE=" + self.module,
+            "-j",
+        ]
+
+        rv = 1
+        with open(self.build_log, "a") as output:
+            rv = sp.call(cmds, stdout=output, stderr=sp.STDOUT)
+
+        if rv != 0:
+            self.dump_build_log()
+
+        return rv == 0
+
+    def dump_build_log(self):
+        with open(self.build_log) as log:
+            print(log.read())
+
+    def flash(self, image_path):
+        """Flashes board with most recent build ec.bin."""
+        cmd = [
+            "reset_config connect_assert_srst",
+            "init",
+            "reset init",
+            "flash write_image erase %s %s" % (image_path, self.flash_offset),
+        ]
+        return self.send_openocd_commands(cmd)
+
+    def to_string(self):
+        s = (
+            "Type: Board\n"
+            "board: " + self.board + "\n"
+            "hla_serial: " + self.hla_serial + "\n"
+            "openocd_config: " + self.openocd_config + "\n"
+            "tty_port: " + self.tty_port + "\n"
+            "tty: " + str(self.tty) + "\n"
+        )
+        return s
+
+    def reset_halt(self):
+        """Reset then halt board."""
+        return self.send_openocd_commands(["init", "reset halt"])
+
+    def resume(self):
+        """Resume halting board."""
+        return self.send_openocd_commands(["init", "resume"])
+
+    def setup_tty(self):
+        """Call this before calling read_tty for the first time.
+
+        This is not in the initialization because caller only should call
+        this function after serial numbers are setup
+        """
+        self.get_serial()
+        self.reset_halt()
+        self.identify_tty_port()
+
+        tty = None
+        try:
+            tty = serial.Serial(self.tty_port, 115200, timeout=1)
+        except serial.SerialException:
+            raise ValueError(
+                "Failed to open "
+                + self.tty_port
+                + " of "
+                + self.board
+                + ". Please make sure the port is available and you have"
+                + " permission to read it. Create dialout group and run:"
+                + " sudo usermod -a -G dialout <username>."
+            )
+        self.tty = tty
+
+    def read_tty(self, max_boot_count=1):
+        """Read info from a serial port described by a file descriptor.
+
+        Args:
+          max_boot_count: Stop reading if boot count exceeds this number
+
+        Returns:
+          result: characters read from tty
+          boot: boot counts
+        """
+        buf = []
         line = []
-        if boot > max_boot_count:
-          break
-
-    l = ''.join(line)
-    buf.append(l)
-    result = ''.join(buf)
-
-    return result, boot
-
-  def identify_tty_port(self):
-    """Saves this board's serial port."""
-    dev_dir = '/dev'
-    id_prefix = 'ID_SERIAL_SHORT='
-    com_devices = [f for f in os.listdir(dev_dir) if f.startswith('ttyACM')]
-
-    for device in com_devices:
-      self.tty_port = os.path.join(dev_dir, device)
-      properties = sp.check_output(
-          ['udevadm', 'info', '-a', '-n', self.tty_port, '--query=property'],
-          **get_subprocess_args())
-      for line in [l.strip() for l in properties.split('\n')]:
-        if line.startswith(id_prefix):
-          if self.hla_serial == line[len(id_prefix):]:
-            return
-
-    # If we get here without returning, something is wrong
-    raise RuntimeError('The device dev path could not be found')
-
-  def close_tty(self):
-    """Close tty."""
-    self.tty.close()
+        boot = 0
+        while True:
+            c = self.tty.read().decode("utf-8")
+            if not c:
+                break
+            line.append(c)
+            if c == "\n":
+                l = "".join(line)
+                buf.append(l)
+                if REBOOT_MARKER in l:
+                    boot += 1
+                line = []
+                if boot > max_boot_count:
+                    break
+
+        l = "".join(line)
+        buf.append(l)
+        result = "".join(buf)
+
+        return result, boot
+
+    def identify_tty_port(self):
+        """Saves this board's serial port."""
+        dev_dir = "/dev"
+        id_prefix = "ID_SERIAL_SHORT="
+        com_devices = [f for f in os.listdir(dev_dir) if f.startswith("ttyACM")]
+
+        for device in com_devices:
+            self.tty_port = os.path.join(dev_dir, device)
+            properties = sp.check_output(
+                [
+                    "udevadm",
+                    "info",
+                    "-a",
+                    "-n",
+                    self.tty_port,
+                    "--query=property",
+                ],
+                **get_subprocess_args()
+            )
+            for line in [l.strip() for l in properties.split("\n")]:
+                if line.startswith(id_prefix):
+                    if self.hla_serial == line[len(id_prefix) :]:
+                        return
+
+        # If we get here without returning, something is wrong
+        raise RuntimeError("The device dev path could not be found")
+
+    def close_tty(self):
+        """Close tty."""
+        self.tty.close()
 
 
 class TestHarness(Board):
-  """Subclass of Board representing a Test Harness.
+    """Subclass of Board representing a Test Harness.
 
-  Attributes:
-    serial_path: Path to file containing serial number
-  """
-
-  def __init__(self, board, module, log_dir, serial_path):
-    """Initializes a board object with given attributes.
-
-    Args:
-      board: board name
-      module: module name
-      log_dir: Directory where log file is stored
+    Attributes:
       serial_path: Path to file containing serial number
     """
-    Board.__init__(self, board, module)
-    self.log_dir = log_dir
-    self.openocd_log = os.path.join(log_dir, 'openocd_th.log')
-    self.build_log = os.path.join(log_dir, 'build_th.log')
-    self.serial_path = serial_path
-    self.reset_log_dir()
-
-  def get_serial(self):
-    """Loads serial number from saved location."""
-    if self.hla_serial:
-      return  # serial was already loaded
-    try:
-      with open(self.serial_path, mode='r') as f:
-        s = f.read()
-        self.hla_serial = s.strip()
+
+    def __init__(self, board, module, log_dir, serial_path):
+        """Initializes a board object with given attributes.
+
+        Args:
+          board: board name
+          module: module name
+          log_dir: Directory where log file is stored
+          serial_path: Path to file containing serial number
+        """
+        Board.__init__(self, board, module)
+        self.log_dir = log_dir
+        self.openocd_log = os.path.join(log_dir, "openocd_th.log")
+        self.build_log = os.path.join(log_dir, "build_th.log")
+        self.serial_path = serial_path
+        self.reset_log_dir()
+
+    def get_serial(self):
+        """Loads serial number from saved location."""
+        if self.hla_serial:
+            return  # serial was already loaded
+        try:
+            with open(self.serial_path, mode="r") as f:
+                s = f.read()
+                self.hla_serial = s.strip()
+                return
+        except IOError:
+            msg = (
+                "Your TH board has not been identified.\n"
+                "Connect only TH and run the script --setup, then try again."
+            )
+            raise RuntimeError(msg)
+
+    def save_serial(self):
+        """Saves the TH serial number to a file."""
+        serials = Board.get_stlink_serials()
+        if len(serials) > 1:
+            msg = (
+                "There are more than one test board connected to the host."
+                "\nConnect only the test harness and remove other boards."
+            )
+            raise RuntimeError(msg)
+        if len(serials) < 1:
+            msg = "No test boards were found.\n" "Check boards are connected."
+            raise RuntimeError(msg)
+
+        s = serials[0]
+        serial_dir = os.path.dirname(self.serial_path)
+        if not os.path.exists(serial_dir):
+            os.makedirs(serial_dir)
+        with open(self.serial_path, mode="w") as f:
+            f.write(s)
+            self.hla_serial = s
+
+        print("Your TH serial", s, "has been saved as", self.serial_path)
         return
-    except IOError:
-      msg = ('Your TH board has not been identified.\n'
-             'Connect only TH and run the script --setup, then try again.')
-      raise RuntimeError(msg)
-
-  def save_serial(self):
-    """Saves the TH serial number to a file."""
-    serials = Board.get_stlink_serials()
-    if len(serials) > 1:
-      msg = ('There are more than one test board connected to the host.'
-             '\nConnect only the test harness and remove other boards.')
-      raise RuntimeError(msg)
-    if len(serials) < 1:
-      msg = ('No test boards were found.\n'
-             'Check boards are connected.')
-      raise RuntimeError(msg)
-
-    s = serials[0]
-    serial_dir = os.path.dirname(self.serial_path)
-    if not os.path.exists(serial_dir):
-      os.makedirs(serial_dir)
-    with open(self.serial_path, mode='w') as f:
-      f.write(s)
-      self.hla_serial = s
-
-    print('Your TH serial', s, 'has been saved as', self.serial_path)
-    return
 
 
 class DeviceUnderTest(Board):
-  """Subclass of Board representing a DUT board.
+    """Subclass of Board representing a DUT board.
 
-  Attributes:
-    th: Reference to test harness board to which this DUT is attached
-  """
-
-  def __init__(self, board, th, module, log_dir, hla_ser=None):
-    """Initializes a DUT object.
-
-    Args:
-      board: String containing board name
+    Attributes:
       th: Reference to test harness board to which this DUT is attached
-      module: module name
-      log_dir: Directory where log file is stored
-      hla_ser: Serial number if board uses an HLA adaptor
     """
-    Board.__init__(self, board, module, hla_serial=hla_ser)
-    self.th = th
-    self.log_dir = log_dir
-    self.openocd_log = os.path.join(log_dir, 'openocd_dut.log')
-    self.build_log = os.path.join(log_dir, 'build_dut.log')
-    self.reset_log_dir()
-
-  def get_serial(self):
-    """Get serial number.
 
-    Precondition: The DUT and TH must both be connected, and th.hla_serial
-    must hold the correct value (the th's serial #)
+    def __init__(self, board, th, module, log_dir, hla_ser=None):
+        """Initializes a DUT object.
+
+        Args:
+          board: String containing board name
+          th: Reference to test harness board to which this DUT is attached
+          module: module name
+          log_dir: Directory where log file is stored
+          hla_ser: Serial number if board uses an HLA adaptor
+        """
+        Board.__init__(self, board, module, hla_serial=hla_ser)
+        self.th = th
+        self.log_dir = log_dir
+        self.openocd_log = os.path.join(log_dir, "openocd_dut.log")
+        self.build_log = os.path.join(log_dir, "build_dut.log")
+        self.reset_log_dir()
+
+    def get_serial(self):
+        """Get serial number.
+
+        Precondition: The DUT and TH must both be connected, and th.hla_serial
+        must hold the correct value (the th's serial #)
+
+        Raises:
+          RuntimeError: DUT isn't found or multiple DUTs are found.
+        """
+        if self.hla_serial is not None:
+            # serial was already set ('' is a valid serial)
+            return
 
-    Raises:
-      RuntimeError: DUT isn't found or multiple DUTs are found.
-    """
-    if self.hla_serial is not None:
-      # serial was already set ('' is a valid serial)
-      return
-
-    serials = Board.get_stlink_serials()
-    dut = [s for s in serials if self.th.hla_serial != s]
-
-    # If len(dut) is 0 then your dut doesn't use an st-link device, so we
-    # don't have to worry about its serial number
-    if not dut:
-      msg = ('Failed to find serial for DUT.\n'
-             'Is ' + self.board + ' connected?')
-      raise RuntimeError(msg)
-    if len(dut) > 1:
-      msg = ('Found multiple DUTs.\n'
-             'You can connect only one DUT at a time. This may be caused by\n'
-             'an incorrect TH serial. Check if ' + self.th.serial_path + '\n'
-             'contains a correct serial.')
-      raise RuntimeError(msg)
-
-    # Found your other st-link device serial!
-    self.hla_serial = dut[0]
-    return
+        serials = Board.get_stlink_serials()
+        dut = [s for s in serials if self.th.hla_serial != s]
+
+        # If len(dut) is 0 then your dut doesn't use an st-link device, so we
+        # don't have to worry about its serial number
+        if not dut:
+            msg = (
+                "Failed to find serial for DUT.\nIs "
+                + self.board
+                + " connected?"
+            )
+            raise RuntimeError(msg)
+        if len(dut) > 1:
+            msg = (
+                "Found multiple DUTs.\n"
+                "You can connect only one DUT at a time. This may be caused by\n"
+                "an incorrect TH serial. Check if " + self.th.serial_path + "\n"
+                "contains a correct serial."
+            )
+            raise RuntimeError(msg)
+
+        # Found your other st-link device serial!
+        self.hla_serial = dut[0]
+        return
diff --git a/cts/common/cts.rc b/cts/common/cts.rc
index 264b982655..fe27b2c308 100644
--- a/cts/common/cts.rc
+++ b/cts/common/cts.rc
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/cts/common/cts_common.c b/cts/common/cts_common.c
index 8975636655..4b56456a3c 100644
--- a/cts/common/cts_common.c
+++ b/cts/common/cts_common.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,7 +11,7 @@ __attribute__((weak)) void clean_state(void)
 	/* Each test overrides as needed */
 }
 
-void cts_main_loop(const struct cts_test* tests, const char *name)
+void cts_main_loop(const struct cts_test *tests, const char *name)
 {
 	enum cts_rc rc;
 	int i;
diff --git a/cts/common/cts_common.h b/cts/common/cts_common.h
index 13a435e655..8fd9073c62 100644
--- a/cts/common/cts_common.h
+++ b/cts/common/cts_common.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,16 +10,16 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTL(format, args...) CPRINTS("%s:%d: "format, \
-					 __func__, __LINE__, ## args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTL(format, args...) \
+	CPRINTS("%s:%d: " format, __func__, __LINE__, ##args)
 
-#define READ_WAIT_TIME_MS		100
-#define CTS_INTERRUPT_TRIGGER_DELAY_US	(250 * MSEC)
+#define READ_WAIT_TIME_MS 100
+#define CTS_INTERRUPT_TRIGGER_DELAY_US (250 * MSEC)
 
 enum cts_rc {
-	#include "cts.rc"
+#include "cts.rc"
 };
 
 struct cts_test {
@@ -38,7 +38,7 @@ extern const int cts_test_count;
  * @test: List of tests to run
  * @name: Name of the test to be printed on EC console
  */
-void cts_main_loop(const struct cts_test* tests, const char *name);
+void cts_main_loop(const struct cts_test *tests, const char *name);
 
 /**
  * Callback function called at the beginning of the main loop
diff --git a/cts/common/cts_testlist.h b/cts/common/cts_testlist.h
index 1586c1348e..ee3ea58d39 100644
--- a/cts/common/cts_testlist.h
+++ b/cts/common/cts_testlist.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,7 +22,7 @@
 
 #undef CTS_TEST
 #define CTS_TEST(test, th_rc, th_string, dut_rc, dut_string) \
-	{test, STRINGIFY(test)},
+	{ test, STRINGIFY(test) },
 struct cts_test tests[] = {
 #include "cts.testlist"
 };
diff --git a/cts/common/dut_common.c b/cts/common/dut_common.c
index c9644b66e8..aa68436d41 100644
--- a/cts/common/dut_common.c
+++ b/cts/common/dut_common.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/cts/common/th_common.c b/cts/common/th_common.c
index 1d692b7843..3084579b99 100644
--- a/cts/common/th_common.c
+++ b/cts/common/th_common.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/cts/cts.py b/cts/cts.py
index c3e0335cab..f61de47398 100755
--- a/cts/cts.py
+++ b/cts/cts.py
@@ -1,12 +1,8 @@
 #!/usr/bin/env python
 #
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
 
 # A script which builds, flashes, and runs EC CTS
 #
@@ -28,416 +24,443 @@ import argparse
 import os
 import shutil
 import time
-import common.board as board
 
+import common.board as board
 
-CTS_RC_PREFIX = 'CTS_RC_'
-DEFAULT_TH = 'stm32l476g-eval'
-DEFAULT_DUT = 'nucleo-f072rb'
+CTS_RC_PREFIX = "CTS_RC_"
+DEFAULT_TH = "stm32l476g-eval"
+DEFAULT_DUT = "nucleo-f072rb"
 MAX_SUITE_TIME_SEC = 5
-CTS_TEST_RESULT_DIR = '/tmp/ects'
+CTS_TEST_RESULT_DIR = "/tmp/ects"
 
 # Host only return codes. Make sure they match values in cts.rc
-CTS_RC_DID_NOT_START = -1          # test did not run.
-CTS_RC_DID_NOT_END = -2            # test did not run.
-CTS_RC_DUPLICATE_RUN = -3          # test was run multiple times.
-CTS_RC_INVALID_RETURN_CODE = -4    # failed to parse return code
+CTS_RC_DID_NOT_START = -1  # test did not run.
+CTS_RC_DID_NOT_END = -2  # test did not run.
+CTS_RC_DUPLICATE_RUN = -3  # test was run multiple times.
+CTS_RC_INVALID_RETURN_CODE = -4  # failed to parse return code
 
 
 class Cts(object):
-  """Class that represents a eCTS run.
-
-  Attributes:
-    dut: DeviceUnderTest object representing DUT
-    th: TestHarness object representing a test harness
-    module: Name of module to build/run tests for
-    testlist: List of strings of test names contained in given module
-    return_codes: Dict of strings of return codes, with a code's integer
-      value being the index for the corresponding string representation
-  """
-
-  def __init__(self, ec_dir, th, dut, module):
-    """Initializes cts class object with given arguments.
-
-    Args:
-      ec_dir: Path to ec directory
-      th: Name of the test harness board
-      dut: Name of the device under test board
-      module: Name of module to build/run tests for (e.g. gpio, interrupt)
-    """
-    self.results_dir = os.path.join(CTS_TEST_RESULT_DIR, dut, module)
-    if os.path.isdir(self.results_dir):
-      shutil.rmtree(self.results_dir)
-    else:
-      os.makedirs(self.results_dir)
-    self.ec_dir = ec_dir
-    self.module = module
-    serial_path = os.path.join(CTS_TEST_RESULT_DIR, 'th_serial')
-    self.th = board.TestHarness(th, module, self.results_dir, serial_path)
-    self.dut = board.DeviceUnderTest(dut, self.th, module, self.results_dir)
-    cts_dir = os.path.join(self.ec_dir, 'cts')
-    testlist_path = os.path.join(cts_dir, self.module, 'cts.testlist')
-    return_codes_path = os.path.join(cts_dir, 'common', 'cts.rc')
-    self.get_return_codes(return_codes_path)
-    self.testlist = self.get_macro_args(testlist_path, 'CTS_TEST')
-
-  def build(self):
-    """Build images for DUT and TH."""
-    print('Building DUT image...')
-    if not self.dut.build(self.ec_dir):
-      raise RuntimeError('Building module %s for DUT failed' % (self.module))
-    print('Building TH image...')
-    if not self.th.build(self.ec_dir):
-      raise RuntimeError('Building module %s for TH failed' % (self.module))
-
-  def flash_boards(self):
-    """Flashes TH and DUT with their most recently built ec.bin."""
-    cts_module = 'cts_' + self.module
-    image_path = os.path.join('build', self.th.board, cts_module, 'ec.bin')
-    self.identify_boards()
-    print('Flashing TH with', image_path)
-    if not self.th.flash(image_path):
-      raise RuntimeError('Flashing TH failed')
-    image_path = os.path.join('build', self.dut.board, cts_module, 'ec.bin')
-    print('Flashing DUT with', image_path)
-    if not self.dut.flash(image_path):
-      raise RuntimeError('Flashing DUT failed')
-
-  def setup(self):
-    """Setup boards."""
-    self.th.save_serial()
-
-  def identify_boards(self):
-    """Updates serials of TH and DUT in that order (order matters)."""
-    self.th.get_serial()
-    self.dut.get_serial()
-
-  def get_macro_args(self, filepath, macro):
-    """Get list of args of a macro in a file when macro.
-
-    Args:
-      filepath: String containing absolute path to the file
-      macro: String containing text of macro to get args of
-
-    Returns:
-      List of dictionaries where each entry is:
-        'name': Test name,
-        'th_string': Expected string from TH,
-        'dut_string': Expected string from DUT,
+    """Class that represents a eCTS run.
+
+    Attributes:
+      dut: DeviceUnderTest object representing DUT
+      th: TestHarness object representing a test harness
+      module: Name of module to build/run tests for
+      testlist: List of strings of test names contained in given module
+      return_codes: Dict of strings of return codes, with a code's integer
+        value being the index for the corresponding string representation
     """
-    tests = []
-    with open(filepath, 'r') as f:
-      lines = f.readlines()
-      joined = ''.join(lines).replace('\\\n', '').splitlines()
-      for l in joined:
-        if not l.strip().startswith(macro):
-          continue
-        d = {}
-        l = l.strip()[len(macro):]
-        l = l.strip('()').split(',')
-        d['name'] = l[0].strip()
-        d['th_rc'] = self.get_return_code_value(l[1].strip().strip('"'))
-        d['th_string'] = l[2].strip().strip('"')
-        d['dut_rc'] = self.get_return_code_value(l[3].strip().strip('"'))
-        d['dut_string'] = l[4].strip().strip('"')
-        tests.append(d)
-    return tests
-
-  def get_return_codes(self, filepath):
-    """Read return code names from the return code definition file."""
-    self.return_codes = {}
-    val = 0
-    with open(filepath, 'r') as f:
-      for line in f:
-        line = line.strip()
-        if not line.startswith(CTS_RC_PREFIX):
-          continue
-        line = line.split(',')[0]
-        if '=' in line:
-          tokens = line.split('=')
-          line = tokens[0].strip()
-          val = int(tokens[1].strip())
-        self.return_codes[line] = val
-        val += 1
-
-  def parse_output(self, output):
-    """Parse console output from DUT or TH.
-
-    Args:
-      output: String containing consoule output
-
-    Returns:
-      List of dictionaries where each key and value are:
-        name = 'ects_test_x',
-        started = True/False,
-        ended = True/False,
-        rc = CTS_RC_*,
-        output = All text between 'ects_test_x start' and 'ects_test_x end'
-    """
-    results = []
-    i = 0
-    for test in self.testlist:
-      results.append({})
-      results[i]['name'] = test['name']
-      results[i]['started'] = False
-      results[i]['rc'] = CTS_RC_DID_NOT_START
-      results[i]['string'] = False
-      results[i]['output'] = []
-      i += 1
-
-    i = 0
-    for ln in [ln.strip() for ln in output.split('\n')]:
-      if i + 1 > len(results):
-        break
-      tokens = ln.split()
-      if len(tokens) >= 2:
-        if tokens[0].strip() == results[i]['name']:
-          if tokens[1].strip() == 'start':
-            # start line found
-            if results[i]['started']:   # Already started
-              results[i]['rc'] = CTS_RC_DUPLICATE_RUN
-            else:
-              results[i]['rc'] = CTS_RC_DID_NOT_END
-              results[i]['started'] = True
-            continue
-          elif results[i]['started'] and tokens[1].strip() == 'end':
-            # end line found
-            results[i]['rc'] = CTS_RC_INVALID_RETURN_CODE
-            if len(tokens) == 3:
-              try:
-                results[i]['rc'] = int(tokens[2].strip())
-              except ValueError:
-                pass
-            # Since index is incremented when 'end' is encountered, we don't
-            # need to check duplicate 'end'.
-            i += 1
-            continue
-      if results[i]['started']:
-        results[i]['output'].append(ln)
-
-    return results
-
-  def get_return_code_name(self, code, strip_prefix=False):
-    name = ''
-    for k, v in self.return_codes.items():
-      if v == code:
-        if strip_prefix:
-          name = k[len(CTS_RC_PREFIX):]
-        else:
-          name = k
-    return name
-
-  def get_return_code_value(self, name):
-    if name:
-      return self.return_codes[name]
-    return  0
-
-  def evaluate_run(self, dut_output, th_output):
-    """Parse outputs to derive test results.
 
-    Args:
-      dut_output: String output of DUT
-      th_output: String output of TH
-
-    Returns:
-      th_results: list of test results for TH
-      dut_results: list of test results for DUT
-    """
-    th_results = self.parse_output(th_output)
-    dut_results = self.parse_output(dut_output)
-
-    # Search for expected string in each output
-    for i, v in enumerate(self.testlist):
-      if v['th_string'] in th_results[i]['output'] or not v['th_string']:
-        th_results[i]['string'] = True
-      if v['dut_string'] in dut_results[i]['output'] or not v['dut_string']:
-        dut_results[i]['string'] = True
+    def __init__(self, ec_dir, th, dut, module):
+        """Initializes cts class object with given arguments.
+
+        Args:
+          ec_dir: Path to ec directory
+          th: Name of the test harness board
+          dut: Name of the device under test board
+          module: Name of module to build/run tests for (e.g. gpio, interrupt)
+        """
+        self.results_dir = os.path.join(CTS_TEST_RESULT_DIR, dut, module)
+        if os.path.isdir(self.results_dir):
+            shutil.rmtree(self.results_dir)
+        else:
+            os.makedirs(self.results_dir)
+        self.ec_dir = ec_dir
+        self.module = module
+        serial_path = os.path.join(CTS_TEST_RESULT_DIR, "th_serial")
+        self.th = board.TestHarness(th, module, self.results_dir, serial_path)
+        self.dut = board.DeviceUnderTest(dut, self.th, module, self.results_dir)
+        cts_dir = os.path.join(self.ec_dir, "cts")
+        testlist_path = os.path.join(cts_dir, self.module, "cts.testlist")
+        return_codes_path = os.path.join(cts_dir, "common", "cts.rc")
+        self.get_return_codes(return_codes_path)
+        self.testlist = self.get_macro_args(testlist_path, "CTS_TEST")
+
+    def build(self):
+        """Build images for DUT and TH."""
+        print("Building DUT image...")
+        if not self.dut.build(self.ec_dir):
+            raise RuntimeError(
+                "Building module %s for DUT failed" % (self.module)
+            )
+        print("Building TH image...")
+        if not self.th.build(self.ec_dir):
+            raise RuntimeError(
+                "Building module %s for TH failed" % (self.module)
+            )
+
+    def flash_boards(self):
+        """Flashes TH and DUT with their most recently built ec.bin."""
+        cts_module = "cts_" + self.module
+        image_path = os.path.join("build", self.th.board, cts_module, "ec.bin")
+        self.identify_boards()
+        print("Flashing TH with", image_path)
+        if not self.th.flash(image_path):
+            raise RuntimeError("Flashing TH failed")
+        image_path = os.path.join("build", self.dut.board, cts_module, "ec.bin")
+        print("Flashing DUT with", image_path)
+        if not self.dut.flash(image_path):
+            raise RuntimeError("Flashing DUT failed")
+
+    def setup(self):
+        """Setup boards."""
+        self.th.save_serial()
+
+    def identify_boards(self):
+        """Updates serials of TH and DUT in that order (order matters)."""
+        self.th.get_serial()
+        self.dut.get_serial()
+
+    def get_macro_args(self, filepath, macro):
+        """Get list of args of a macro in a file when macro.
+
+        Args:
+          filepath: String containing absolute path to the file
+          macro: String containing text of macro to get args of
+
+        Returns:
+          List of dictionaries where each entry is:
+            'name': Test name,
+            'th_string': Expected string from TH,
+            'dut_string': Expected string from DUT,
+        """
+        tests = []
+        with open(filepath, "r") as f:
+            lines = f.readlines()
+            joined = "".join(lines).replace("\\\n", "").splitlines()
+            for l in joined:
+                if not l.strip().startswith(macro):
+                    continue
+                d = {}
+                l = l.strip()[len(macro) :]
+                l = l.strip("()").split(",")
+                d["name"] = l[0].strip()
+                d["th_rc"] = self.get_return_code_value(l[1].strip().strip('"'))
+                d["th_string"] = l[2].strip().strip('"')
+                d["dut_rc"] = self.get_return_code_value(
+                    l[3].strip().strip('"')
+                )
+                d["dut_string"] = l[4].strip().strip('"')
+                tests.append(d)
+        return tests
+
+    def get_return_codes(self, filepath):
+        """Read return code names from the return code definition file."""
+        self.return_codes = {}
+        val = 0
+        with open(filepath, "r") as f:
+            for line in f:
+                line = line.strip()
+                if not line.startswith(CTS_RC_PREFIX):
+                    continue
+                line = line.split(",")[0]
+                if "=" in line:
+                    tokens = line.split("=")
+                    line = tokens[0].strip()
+                    val = int(tokens[1].strip())
+                self.return_codes[line] = val
+                val += 1
+
+    def parse_output(self, output):
+        """Parse console output from DUT or TH.
+
+        Args:
+          output: String containing consoule output
+
+        Returns:
+          List of dictionaries where each key and value are:
+            name = 'ects_test_x',
+            started = True/False,
+            ended = True/False,
+            rc = CTS_RC_*,
+            output = All text between 'ects_test_x start' and 'ects_test_x end'
+        """
+        results = []
+        i = 0
+        for test in self.testlist:
+            results.append({})
+            results[i]["name"] = test["name"]
+            results[i]["started"] = False
+            results[i]["rc"] = CTS_RC_DID_NOT_START
+            results[i]["string"] = False
+            results[i]["output"] = []
+            i += 1
 
-    return th_results, dut_results
+        i = 0
+        for ln in [ln.strip() for ln in output.split("\n")]:
+            if i + 1 > len(results):
+                break
+            tokens = ln.split()
+            if len(tokens) >= 2:
+                if tokens[0].strip() == results[i]["name"]:
+                    if tokens[1].strip() == "start":
+                        # start line found
+                        if results[i]["started"]:  # Already started
+                            results[i]["rc"] = CTS_RC_DUPLICATE_RUN
+                        else:
+                            results[i]["rc"] = CTS_RC_DID_NOT_END
+                            results[i]["started"] = True
+                        continue
+                    elif results[i]["started"] and tokens[1].strip() == "end":
+                        # end line found
+                        results[i]["rc"] = CTS_RC_INVALID_RETURN_CODE
+                        if len(tokens) == 3:
+                            try:
+                                results[i]["rc"] = int(tokens[2].strip())
+                            except ValueError:
+                                pass
+                        # Since index is incremented when 'end' is encountered, we don't
+                        # need to check duplicate 'end'.
+                        i += 1
+                        continue
+            if results[i]["started"]:
+                results[i]["output"].append(ln)
+
+        return results
+
+    def get_return_code_name(self, code, strip_prefix=False):
+        name = ""
+        for k, v in self.return_codes.items():
+            if v == code:
+                if strip_prefix:
+                    name = k[len(CTS_RC_PREFIX) :]
+                else:
+                    name = k
+        return name
+
+    def get_return_code_value(self, name):
+        if name:
+            return self.return_codes[name]
+        return 0
+
+    def evaluate_run(self, dut_output, th_output):
+        """Parse outputs to derive test results.
+
+        Args:
+          dut_output: String output of DUT
+          th_output: String output of TH
+
+        Returns:
+          th_results: list of test results for TH
+          dut_results: list of test results for DUT
+        """
+        th_results = self.parse_output(th_output)
+        dut_results = self.parse_output(dut_output)
+
+        # Search for expected string in each output
+        for i, v in enumerate(self.testlist):
+            if v["th_string"] in th_results[i]["output"] or not v["th_string"]:
+                th_results[i]["string"] = True
+            if (
+                v["dut_string"] in dut_results[i]["output"]
+                or not v["dut_string"]
+            ):
+                dut_results[i]["string"] = True
+
+        return th_results, dut_results
+
+    def print_result(self, th_results, dut_results):
+        """Print results to the screen.
+
+        Args:
+          th_results: list of test results for TH
+          dut_results: list of test results for DUT
+        """
+        len_test_name = max(len(s["name"]) for s in self.testlist)
+        len_code_name = max(
+            len(self.get_return_code_name(v, True))
+            for v in self.return_codes.values()
+        )
+
+        head = "{:^" + str(len_test_name) + "} "
+        head += "{:^" + str(len_code_name) + "} "
+        head += "{:^" + str(len_code_name) + "}"
+        head += "{:^" + str(len(" TH_STR")) + "}"
+        head += "{:^" + str(len(" DUT_STR")) + "}"
+        head += "{:^" + str(len(" RESULT")) + "}\n"
+        fmt = "{:" + str(len_test_name) + "} "
+        fmt += "{:>" + str(len_code_name) + "} "
+        fmt += "{:>" + str(len_code_name) + "}"
+        fmt += "{:>" + str(len(" TH_STR")) + "}"
+        fmt += "{:>" + str(len(" DUT_STR")) + "}"
+        fmt += "{:>" + str(len(" RESULT")) + "}\n"
+
+        self.formatted_results = head.format(
+            "TEST NAME", "TH_RC", "DUT_RC", " TH_STR", " DUT_STR", " RESULT"
+        )
+        for i, d in enumerate(dut_results):
+            th_cn = self.get_return_code_name(th_results[i]["rc"], True)
+            dut_cn = self.get_return_code_name(dut_results[i]["rc"], True)
+            th_res = self.evaluate_result(
+                th_results[i],
+                self.testlist[i]["th_rc"],
+                self.testlist[i]["th_string"],
+            )
+            dut_res = self.evaluate_result(
+                dut_results[i],
+                self.testlist[i]["dut_rc"],
+                self.testlist[i]["dut_string"],
+            )
+            self.formatted_results += fmt.format(
+                d["name"],
+                th_cn,
+                dut_cn,
+                "YES" if th_results[i]["string"] else "NO",
+                "YES" if dut_results[i]["string"] else "NO",
+                "PASS" if th_res and dut_res else "FAIL",
+            )
+
+    def evaluate_result(self, result, expected_rc, expected_string):
+        if result["rc"] != expected_rc:
+            return False
+        if expected_string and expected_string not in result["output"]:
+            return False
+        return True
+
+    def run(self):
+        """Resets boards, records test results in results dir."""
+        print("Reading serials...")
+        self.identify_boards()
+        print("Opening DUT tty...")
+        self.dut.setup_tty()
+        print("Opening TH tty...")
+        self.th.setup_tty()
+
+        # Boards might be still writing to tty. Wait a few seconds before flashing.
+        time.sleep(3)
+
+        # clear buffers
+        print("Clearing DUT tty...")
+        self.dut.read_tty()
+        print("Clearing TH tty...")
+        self.th.read_tty()
+
+        # Resets the boards and allows them to run tests
+        # Due to current (7/27/16) version of sync function,
+        # both boards must be rest and halted, with the th
+        # resuming first, in order for the test suite to run in sync
+        print("Halting TH...")
+        if not self.th.reset_halt():
+            raise RuntimeError("Failed to halt TH")
+        print("Halting DUT...")
+        if not self.dut.reset_halt():
+            raise RuntimeError("Failed to halt DUT")
+        print("Resuming TH...")
+        if not self.th.resume():
+            raise RuntimeError("Failed to resume TH")
+        print("Resuming DUT...")
+        if not self.dut.resume():
+            raise RuntimeError("Failed to resume DUT")
+
+        time.sleep(MAX_SUITE_TIME_SEC)
+
+        print("Reading DUT tty...")
+        dut_output, _ = self.dut.read_tty()
+        self.dut.close_tty()
+        print("Reading TH tty...")
+        th_output, _ = self.th.read_tty()
+        self.th.close_tty()
+
+        print("Halting TH...")
+        if not self.th.reset_halt():
+            raise RuntimeError("Failed to halt TH")
+        print("Halting DUT...")
+        if not self.dut.reset_halt():
+            raise RuntimeError("Failed to halt DUT")
+
+        if not dut_output or not th_output:
+            raise ValueError(
+                "Output missing from boards. If you have a process "
+                "reading ttyACMx, please kill that process and try "
+                "again."
+            )
+
+            print("Pursing results...")
+        th_results, dut_results = self.evaluate_run(dut_output, th_output)
+
+        # Print out results
+        self.print_result(th_results, dut_results)
+
+        # Write results
+        dest = os.path.join(self.results_dir, "results.log")
+        with open(dest, "w") as fl:
+            fl.write(self.formatted_results)
+
+        # Write UART outputs
+        dest = os.path.join(self.results_dir, "uart_th.log")
+        with open(dest, "w") as fl:
+            fl.write(th_output)
+        dest = os.path.join(self.results_dir, "uart_dut.log")
+        with open(dest, "w") as fl:
+            fl.write(dut_output)
+
+        print(self.formatted_results)
+
+        # TODO(chromium:735652): Should set exit code for the shell
 
-  def print_result(self, th_results, dut_results):
-    """Print results to the screen.
 
-    Args:
-      th_results: list of test results for TH
-      dut_results: list of test results for DUT
-    """
-    len_test_name = max(len(s['name']) for s in self.testlist)
-    len_code_name = max(len(self.get_return_code_name(v, True))
-                        for v in self.return_codes.values())
-
-    head = '{:^' + str(len_test_name) + '} '
-    head += '{:^' + str(len_code_name) + '} '
-    head += '{:^' + str(len_code_name) + '}'
-    head += '{:^' + str(len(' TH_STR')) + '}'
-    head += '{:^' + str(len(' DUT_STR')) + '}'
-    head += '{:^' + str(len(' RESULT')) + '}\n'
-    fmt = '{:' + str(len_test_name) + '} '
-    fmt += '{:>' + str(len_code_name) + '} '
-    fmt += '{:>' + str(len_code_name) + '}'
-    fmt += '{:>' + str(len(' TH_STR')) + '}'
-    fmt += '{:>' + str(len(' DUT_STR')) + '}'
-    fmt += '{:>' + str(len(' RESULT')) + '}\n'
-
-    self.formatted_results = head.format(
-        'TEST NAME', 'TH_RC', 'DUT_RC',
-        ' TH_STR', ' DUT_STR', ' RESULT')
-    for i, d in enumerate(dut_results):
-      th_cn = self.get_return_code_name(th_results[i]['rc'], True)
-      dut_cn = self.get_return_code_name(dut_results[i]['rc'], True)
-      th_res = self.evaluate_result(th_results[i],
-                                    self.testlist[i]['th_rc'],
-                                    self.testlist[i]['th_string'])
-      dut_res = self.evaluate_result(dut_results[i],
-                                     self.testlist[i]['dut_rc'],
-                                     self.testlist[i]['dut_string'])
-      self.formatted_results += fmt.format(
-          d['name'], th_cn, dut_cn,
-          'YES' if th_results[i]['string'] else 'NO',
-          'YES' if dut_results[i]['string'] else 'NO',
-          'PASS' if th_res and dut_res else 'FAIL')
-
-  def evaluate_result(self, result, expected_rc, expected_string):
-    if result['rc'] != expected_rc:
-      return False
-    if expected_string and expected_string not in result['output']:
-      return False
-    return True
-
-  def run(self):
-    """Resets boards, records test results in results dir."""
-    print('Reading serials...')
-    self.identify_boards()
-    print('Opening DUT tty...')
-    self.dut.setup_tty()
-    print('Opening TH tty...')
-    self.th.setup_tty()
-
-    # Boards might be still writing to tty. Wait a few seconds before flashing.
-    time.sleep(3)
-
-    # clear buffers
-    print('Clearing DUT tty...')
-    self.dut.read_tty()
-    print('Clearing TH tty...')
-    self.th.read_tty()
-
-    # Resets the boards and allows them to run tests
-    # Due to current (7/27/16) version of sync function,
-    # both boards must be rest and halted, with the th
-    # resuming first, in order for the test suite to run in sync
-    print('Halting TH...')
-    if not self.th.reset_halt():
-      raise RuntimeError('Failed to halt TH')
-    print('Halting DUT...')
-    if not self.dut.reset_halt():
-      raise RuntimeError('Failed to halt DUT')
-    print('Resuming TH...')
-    if not self.th.resume():
-      raise RuntimeError('Failed to resume TH')
-    print('Resuming DUT...')
-    if not self.dut.resume():
-      raise RuntimeError('Failed to resume DUT')
-
-    time.sleep(MAX_SUITE_TIME_SEC)
-
-    print('Reading DUT tty...')
-    dut_output, _ = self.dut.read_tty()
-    self.dut.close_tty()
-    print('Reading TH tty...')
-    th_output, _ = self.th.read_tty()
-    self.th.close_tty()
-
-    print('Halting TH...')
-    if not self.th.reset_halt():
-      raise RuntimeError('Failed to halt TH')
-    print('Halting DUT...')
-    if not self.dut.reset_halt():
-      raise RuntimeError('Failed to halt DUT')
-
-    if not dut_output or not th_output:
-      raise ValueError('Output missing from boards. If you have a process '
-                       'reading ttyACMx, please kill that process and try '
-                       'again.')
-
-      print('Pursing results...')
-    th_results, dut_results = self.evaluate_run(dut_output, th_output)
-
-    # Print out results
-    self.print_result(th_results, dut_results)
-
-    # Write results
-    dest = os.path.join(self.results_dir, 'results.log')
-    with open(dest, 'w') as fl:
-      fl.write(self.formatted_results)
-
-    # Write UART outputs
-    dest = os.path.join(self.results_dir, 'uart_th.log')
-    with open(dest, 'w') as fl:
-      fl.write(th_output)
-    dest = os.path.join(self.results_dir, 'uart_dut.log')
-    with open(dest, 'w') as fl:
-      fl.write(dut_output)
-
-    print(self.formatted_results)
-
-    # TODO(chromium:735652): Should set exit code for the shell
+def main():
+    ec_dir = os.path.realpath(
+        os.path.join(os.path.dirname(os.path.abspath(__file__)), "..")
+    )
+    os.chdir(ec_dir)
+
+    dut = DEFAULT_DUT
+    module = "meta"
+
+    parser = argparse.ArgumentParser(description="Used to build/flash boards")
+    parser.add_argument(
+        "-d", "--dut", help="Specify DUT you want to build/flash"
+    )
+    parser.add_argument(
+        "-m", "--module", help="Specify module you want to build/flash"
+    )
+    parser.add_argument(
+        "-s",
+        "--setup",
+        action="store_true",
+        help="Connect only the TH to save its serial",
+    )
+    parser.add_argument(
+        "-b",
+        "--build",
+        action="store_true",
+        help="Build test suite (no flashing)",
+    )
+    parser.add_argument(
+        "-f",
+        "--flash",
+        action="store_true",
+        help="Flash boards with most recent images",
+    )
+    parser.add_argument(
+        "-r", "--run", action="store_true", help="Run tests without flashing"
+    )
+
+    args = parser.parse_args()
+
+    if args.module:
+        module = args.module
+
+    if args.dut:
+        dut = args.dut
+
+    cts = Cts(ec_dir, DEFAULT_TH, dut=dut, module=module)
+
+    if args.setup:
+        cts.setup()
+    elif args.build:
+        cts.build()
+    elif args.flash:
+        cts.flash_boards()
+    elif args.run:
+        cts.run()
+    else:
+        cts.build()
+        cts.flash_boards()
+        cts.run()
 
 
-def main():
-  ec_dir = os.path.realpath(os.path.join(
-      os.path.dirname(os.path.abspath(__file__)), '..'))
-  os.chdir(ec_dir)
-
-  dut = DEFAULT_DUT
-  module = 'meta'
-
-  parser = argparse.ArgumentParser(description='Used to build/flash boards')
-  parser.add_argument('-d',
-                      '--dut',
-                      help='Specify DUT you want to build/flash')
-  parser.add_argument('-m',
-                      '--module',
-                      help='Specify module you want to build/flash')
-  parser.add_argument('-s',
-                      '--setup',
-                      action='store_true',
-                      help='Connect only the TH to save its serial')
-  parser.add_argument('-b',
-                      '--build',
-                      action='store_true',
-                      help='Build test suite (no flashing)')
-  parser.add_argument('-f',
-                      '--flash',
-                      action='store_true',
-                      help='Flash boards with most recent images')
-  parser.add_argument('-r',
-                      '--run',
-                      action='store_true',
-                      help='Run tests without flashing')
-
-  args = parser.parse_args()
-
-  if args.module:
-    module = args.module
-
-  if args.dut:
-    dut = args.dut
-
-  cts = Cts(ec_dir, DEFAULT_TH, dut=dut, module=module)
-
-  if args.setup:
-    cts.setup()
-  elif args.build:
-    cts.build()
-  elif args.flash:
-    cts.flash_boards()
-  elif args.run:
-    cts.run()
-  else:
-    cts.build()
-    cts.flash_boards()
-    cts.run()
-
-if __name__ == '__main__':
-  main()
+if __name__ == "__main__":
+    main()
diff --git a/cts/cts.tasklist b/cts/cts.tasklist
index 152b0d02b2..40dfb21e10 100644
--- a/cts/cts.tasklist
+++ b/cts/cts.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/cts/gpio/cts.testlist b/cts/gpio/cts.testlist
index 113d2b405f..a5b7482675 100644
--- a/cts/gpio/cts.testlist
+++ b/cts/gpio/cts.testlist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/cts/gpio/dut.c b/cts/gpio/dut.c
index 7ed613911c..92ae893a48 100644
--- a/cts/gpio/dut.c
+++ b/cts/gpio/dut.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,7 +21,7 @@ enum cts_rc set_high_test(void)
 {
 	gpio_set_flags(GPIO_OUTPUT_TEST, GPIO_ODR_LOW);
 	gpio_set_level(GPIO_OUTPUT_TEST, 1);
-	msleep(READ_WAIT_TIME_MS*2);
+	msleep(READ_WAIT_TIME_MS * 2);
 	return CTS_RC_SUCCESS;
 }
 
@@ -29,7 +29,7 @@ enum cts_rc set_low_test(void)
 {
 	gpio_set_flags(GPIO_OUTPUT_TEST, GPIO_ODR_LOW);
 	gpio_set_level(GPIO_OUTPUT_TEST, 0);
-	msleep(READ_WAIT_TIME_MS*2);
+	msleep(READ_WAIT_TIME_MS * 2);
 	return CTS_RC_SUCCESS;
 }
 
diff --git a/cts/gpio/th.c b/cts/gpio/th.c
index 30f33b21bf..98fc232d1c 100644
--- a/cts/gpio/th.c
+++ b/cts/gpio/th.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -47,7 +47,7 @@ enum cts_rc read_high_test(void)
 {
 	gpio_set_flags(GPIO_OUTPUT_TEST, GPIO_ODR_LOW);
 	gpio_set_level(GPIO_OUTPUT_TEST, 1);
-	msleep(READ_WAIT_TIME_MS*2);
+	msleep(READ_WAIT_TIME_MS * 2);
 	return CTS_RC_SUCCESS;
 }
 
@@ -55,14 +55,14 @@ enum cts_rc read_low_test(void)
 {
 	gpio_set_flags(GPIO_OUTPUT_TEST, GPIO_ODR_LOW);
 	gpio_set_level(GPIO_OUTPUT_TEST, 0);
-	msleep(READ_WAIT_TIME_MS*2);
+	msleep(READ_WAIT_TIME_MS * 2);
 	return CTS_RC_SUCCESS;
 }
 
 enum cts_rc od_read_high_test(void)
 {
 	gpio_set_flags(GPIO_INPUT_TEST, GPIO_OUTPUT | GPIO_ODR_LOW);
-	msleep(READ_WAIT_TIME_MS*2);
+	msleep(READ_WAIT_TIME_MS * 2);
 	return CTS_RC_SUCCESS;
 }
 
diff --git a/cts/hook/cts.testlist b/cts/hook/cts.testlist
index 97b25575d4..75e1a11324 100644
--- a/cts/hook/cts.testlist
+++ b/cts/hook/cts.testlist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/cts/hook/dut.c b/cts/hook/dut.c
index f3a52ddaf4..fc6187cade 100644
--- a/cts/hook/dut.c
+++ b/cts/hook/dut.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -88,8 +88,7 @@ static enum cts_rc test_ticks(void)
 	msleep(1300);
 
 	interval = tick_time[1].val - tick_time[0].val;
-	error_pct = (interval - HOOK_TICK_INTERVAL) * 100 /
-		    HOOK_TICK_INTERVAL;
+	error_pct = (interval - HOOK_TICK_INTERVAL) * 100 / HOOK_TICK_INTERVAL;
 	if (error_pct < -10 || 10 < error_pct) {
 		CPRINTS("tick error=%d%% interval=%lld", error_pct, interval);
 		return CTS_RC_FAILURE;
@@ -142,8 +141,8 @@ static enum cts_rc test_deferred(void)
 
 	/* Invalid deferred function */
 	deferred_call_count = 0;
-	if (hook_call_deferred(&invalid_deferred_func_data, 50 * MSEC)
-			== EC_SUCCESS) {
+	if (hook_call_deferred(&invalid_deferred_func_data, 50 * MSEC) ==
+	    EC_SUCCESS) {
 		CPRINTL("non_deferred_func_data");
 		return CTS_RC_FAILURE;
 	}
diff --git a/cts/hook/th.c b/cts/hook/th.c
index 41eab28462..fc6187cade 120000..100644
--- a/cts/hook/th.c
+++ b/cts/hook/th.c
@@ -1 +1,164 @@
-dut.c
\ No newline at end of file
+/* Copyright 2013 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Test hooks.
+ */
+
+#include "common.h"
+#include "console.h"
+#include "cts_common.h"
+#include "hooks.h"
+#include "task.h"
+#include "timer.h"
+#include "util.h"
+#include "watchdog.h"
+
+static int init_hook_count;
+static int tick_hook_count;
+static int tick2_hook_count;
+static int tick_count_seen_by_tick2;
+static timestamp_t tick_time[2];
+static int second_hook_count;
+static timestamp_t second_time[2];
+static int deferred_call_count;
+
+static void init_hook(void)
+{
+	init_hook_count++;
+}
+DECLARE_HOOK(HOOK_INIT, init_hook, HOOK_PRIO_DEFAULT);
+
+static void tick_hook(void)
+{
+	tick_hook_count++;
+	tick_time[0] = tick_time[1];
+	tick_time[1] = get_time();
+}
+DECLARE_HOOK(HOOK_TICK, tick_hook, HOOK_PRIO_DEFAULT);
+
+static void tick2_hook(void)
+{
+	tick2_hook_count++;
+	tick_count_seen_by_tick2 = tick_hook_count;
+}
+/* tick2_hook() prio means it should be called after tick_hook() */
+DECLARE_HOOK(HOOK_TICK, tick2_hook, HOOK_PRIO_DEFAULT + 1);
+
+static void second_hook(void)
+{
+	second_hook_count++;
+	second_time[0] = second_time[1];
+	second_time[1] = get_time();
+}
+DECLARE_HOOK(HOOK_SECOND, second_hook, HOOK_PRIO_DEFAULT);
+
+static void deferred_func(void)
+{
+	deferred_call_count++;
+}
+DECLARE_DEFERRED(deferred_func);
+
+static void invalid_deferred_func(void)
+{
+	deferred_call_count++;
+}
+
+static const struct deferred_data invalid_deferred_func_data = {
+	invalid_deferred_func
+};
+
+static enum cts_rc test_init_hook(void)
+{
+	if (init_hook_count != 1)
+		return CTS_RC_FAILURE;
+	return CTS_RC_SUCCESS;
+}
+
+static enum cts_rc test_ticks(void)
+{
+	int64_t interval;
+	int error_pct;
+
+	/*
+	 * HOOK_SECOND must have been fired at least once when HOOK
+	 * task starts. We only need to wait for just more than a second
+	 * to allow it fires for the second time.
+	 */
+	msleep(1300);
+
+	interval = tick_time[1].val - tick_time[0].val;
+	error_pct = (interval - HOOK_TICK_INTERVAL) * 100 / HOOK_TICK_INTERVAL;
+	if (error_pct < -10 || 10 < error_pct) {
+		CPRINTS("tick error=%d%% interval=%lld", error_pct, interval);
+		return CTS_RC_FAILURE;
+	}
+
+	interval = second_time[1].val - second_time[0].val;
+	error_pct = (interval - SECOND) * 100 / SECOND;
+	if (error_pct < -10 || 10 < error_pct) {
+		CPRINTS("second error=%d%% interval=%lld", error_pct, interval);
+		return CTS_RC_FAILURE;
+	}
+
+	return CTS_RC_SUCCESS;
+}
+
+static enum cts_rc test_priority(void)
+{
+	usleep(HOOK_TICK_INTERVAL);
+	if (tick_hook_count != tick2_hook_count)
+		return CTS_RC_FAILURE;
+	if (tick_hook_count != tick_count_seen_by_tick2)
+		return CTS_RC_FAILURE;
+	return CTS_RC_SUCCESS;
+}
+
+static enum cts_rc test_deferred(void)
+{
+	deferred_call_count = 0;
+	hook_call_deferred(&deferred_func_data, 50 * MSEC);
+	if (deferred_call_count != 0) {
+		CPRINTL("deferred_call_count=%d", deferred_call_count);
+		return CTS_RC_FAILURE;
+	}
+	msleep(100);
+	if (deferred_call_count != 1) {
+		CPRINTL("deferred_call_count=%d", deferred_call_count);
+		return CTS_RC_FAILURE;
+	}
+
+	/* Test cancellation */
+	deferred_call_count = 0;
+	hook_call_deferred(&deferred_func_data, 50 * MSEC);
+	msleep(25);
+	hook_call_deferred(&deferred_func_data, -1);
+	msleep(75);
+	if (deferred_call_count != 0) {
+		CPRINTL("deferred_call_count=%d", deferred_call_count);
+		return CTS_RC_FAILURE;
+	}
+
+	/* Invalid deferred function */
+	deferred_call_count = 0;
+	if (hook_call_deferred(&invalid_deferred_func_data, 50 * MSEC) ==
+	    EC_SUCCESS) {
+		CPRINTL("non_deferred_func_data");
+		return CTS_RC_FAILURE;
+	}
+	msleep(100);
+	if (deferred_call_count != 0) {
+		CPRINTL("deferred_call_count=%d", deferred_call_count);
+		return CTS_RC_FAILURE;
+	}
+
+	return CTS_RC_SUCCESS;
+}
+
+#include "cts_testlist.h"
+
+void cts_task(void)
+{
+	cts_main_loop(tests, "Hook");
+	task_wait_event(-1);
+}
diff --git a/cts/i2c/cts.testlist b/cts/i2c/cts.testlist
index 7b6461e84d..b52e247680 100644
--- a/cts/i2c/cts.testlist
+++ b/cts/i2c/cts.testlist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/cts/i2c/cts_i2c.h b/cts/i2c/cts_i2c.h
index 2914d92a99..ae4aab9878 100644
--- a/cts/i2c/cts_i2c.h
+++ b/cts/i2c/cts_i2c.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,9 +12,9 @@ enum cts_i2c_packets {
 	READ32_OFF,
 };
 
-#define WRITE8_DATA	0x42
-#define WRITE16_DATA	0x1234
-#define WRITE32_DATA	0xDEADBEEF
-#define READ8_DATA	0x23
-#define READ16_DATA	0xACED
-#define READ32_DATA	0x01ABCDEF
+#define WRITE8_DATA 0x42
+#define WRITE16_DATA 0x1234
+#define WRITE32_DATA 0xDEADBEEF
+#define READ8_DATA 0x23
+#define READ16_DATA 0xACED
+#define READ32_DATA 0x01ABCDEF
diff --git a/cts/i2c/dut.c b/cts/i2c/dut.c
index c7a3f9fccf..d2d721fdd6 100644
--- a/cts/i2c/dut.c
+++ b/cts/i2c/dut.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,24 +17,24 @@
 
 enum cts_rc write8_test(void)
 {
-	if (i2c_write8(i2c_ports[0].port, TH_ADDR_FLAGS,
-		       WRITE8_OFF, WRITE8_DATA))
+	if (i2c_write8(i2c_ports[0].port, TH_ADDR_FLAGS, WRITE8_OFF,
+		       WRITE8_DATA))
 		return CTS_RC_FAILURE;
 	return CTS_RC_SUCCESS;
 }
 
 enum cts_rc write16_test(void)
 {
-	if (i2c_write16(i2c_ports[0].port, TH_ADDR_FLAGS,
-			WRITE16_OFF, WRITE16_DATA))
+	if (i2c_write16(i2c_ports[0].port, TH_ADDR_FLAGS, WRITE16_OFF,
+			WRITE16_DATA))
 		return CTS_RC_FAILURE;
 	return CTS_RC_SUCCESS;
 }
 
 enum cts_rc write32_test(void)
 {
-	if (i2c_write32(i2c_ports[0].port, TH_ADDR_FLAGS,
-			WRITE32_OFF, WRITE32_DATA))
+	if (i2c_write32(i2c_ports[0].port, TH_ADDR_FLAGS, WRITE32_OFF,
+			WRITE32_DATA))
 		return CTS_RC_FAILURE;
 	return CTS_RC_SUCCESS;
 }
@@ -43,8 +43,7 @@ enum cts_rc read8_test(void)
 {
 	int data;
 
-	if (i2c_read8(i2c_ports[0].port, TH_ADDR_FLAGS,
-		      READ8_OFF, &data))
+	if (i2c_read8(i2c_ports[0].port, TH_ADDR_FLAGS, READ8_OFF, &data))
 		return CTS_RC_FAILURE;
 	if (data != READ8_DATA) {
 		CPRINTL("Expecting 0x%x but read 0x%x", READ8_DATA, data);
@@ -58,8 +57,7 @@ enum cts_rc read16_test(void)
 {
 	int data;
 
-	if (i2c_read16(i2c_ports[0].port, TH_ADDR_FLAGS,
-		       READ16_OFF, &data))
+	if (i2c_read16(i2c_ports[0].port, TH_ADDR_FLAGS, READ16_OFF, &data))
 		return CTS_RC_FAILURE;
 	if (data != READ16_DATA) {
 		CPRINTL("Expecting 0x%x but read 0x%x", READ16_DATA, data);
@@ -73,8 +71,7 @@ enum cts_rc read32_test(void)
 {
 	int data;
 
-	if (i2c_read32(i2c_ports[0].port, TH_ADDR_FLAGS,
-		       READ32_OFF, &data))
+	if (i2c_read32(i2c_ports[0].port, TH_ADDR_FLAGS, READ32_OFF, &data))
 		return CTS_RC_FAILURE;
 	if (data != READ32_DATA) {
 		CPRINTL("Read 0x%x expecting 0x%x", data, READ32_DATA);
@@ -84,7 +81,6 @@ enum cts_rc read32_test(void)
 	return CTS_RC_SUCCESS;
 }
 
-
 #include "cts_testlist.h"
 
 void cts_task(void)
diff --git a/cts/i2c/th.c b/cts/i2c/th.c
index 78035cb1b2..ef57f6300c 100644
--- a/cts/i2c/th.c
+++ b/cts/i2c/th.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/cts/interrupt/cts.testlist b/cts/interrupt/cts.testlist
index 0fdaf6fca2..e48208d900 100644
--- a/cts/interrupt/cts.testlist
+++ b/cts/interrupt/cts.testlist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/cts/interrupt/dut.c b/cts/interrupt/dut.c
index a479918c5f..c2e0af0f81 100644
--- a/cts/interrupt/dut.c
+++ b/cts/interrupt/dut.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/cts/interrupt/th.c b/cts/interrupt/th.c
index 1639a1868c..ff9a3b303b 100644
--- a/cts/interrupt/th.c
+++ b/cts/interrupt/th.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/cts/meta/cts.testlist b/cts/meta/cts.testlist
index 28ac7e325f..2d41848737 100644
--- a/cts/meta/cts.testlist
+++ b/cts/meta/cts.testlist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/cts/meta/dut.c b/cts/meta/dut.c
index c321676aec..8880c7ba13 100644
--- a/cts/meta/dut.c
+++ b/cts/meta/dut.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/cts/meta/th.c b/cts/meta/th.c
index 57b2f492bd..ec7f061793 100644
--- a/cts/meta/th.c
+++ b/cts/meta/th.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/cts/mutex/cts.tasklist b/cts/mutex/cts.tasklist
index 3387e1de09..ad0c75c601 100644
--- a/cts/mutex/cts.tasklist
+++ b/cts/mutex/cts.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/cts/mutex/cts.testlist b/cts/mutex/cts.testlist
index 5b1cdb1dae..5cea62c079 100644
--- a/cts/mutex/cts.testlist
+++ b/cts/mutex/cts.testlist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/cts/mutex/dut.c b/cts/mutex/dut.c
index 9cbbd8badb..c48dfcaa64 100644
--- a/cts/mutex/dut.c
+++ b/cts/mutex/dut.c
@@ -1,7 +1,7 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
- * Copyright 2011 Google Inc.
+ * Copyright 2011 Google LLC
  *
  * Tasks for mutexes basic tests.
  */
@@ -23,7 +23,7 @@ static struct mutex mtx;
 
 int mutex_random_task(void *unused)
 {
-	char letter = 'A'+(TASK_ID_MTX3A - task_get_current());
+	char letter = 'A' + (TASK_ID_MTX3A - task_get_current());
 	/* wait to be activated */
 
 	while (1) {
diff --git a/cts/mutex/th.c b/cts/mutex/th.c
index 9cbbd8badb..c48dfcaa64 100644
--- a/cts/mutex/th.c
+++ b/cts/mutex/th.c
@@ -1,7 +1,7 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
- * Copyright 2011 Google Inc.
+ * Copyright 2011 Google LLC
  *
  * Tasks for mutexes basic tests.
  */
@@ -23,7 +23,7 @@ static struct mutex mtx;
 
 int mutex_random_task(void *unused)
 {
-	char letter = 'A'+(TASK_ID_MTX3A - task_get_current());
+	char letter = 'A' + (TASK_ID_MTX3A - task_get_current());
 	/* wait to be activated */
 
 	while (1) {
diff --git a/cts/task/cts.tasklist b/cts/task/cts.tasklist
index 6477d74c2c..1adbf211ec 100644
--- a/cts/task/cts.tasklist
+++ b/cts/task/cts.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/cts/task/cts.testlist b/cts/task/cts.testlist
index c4b7bc3231..3ad8e33928 100644
--- a/cts/task/cts.testlist
+++ b/cts/task/cts.testlist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/cts/task/dut.c b/cts/task/dut.c
index 71fe4050ec..257809b4b8 100644
--- a/cts/task/dut.c
+++ b/cts/task/dut.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -70,15 +70,15 @@ enum cts_rc test_task_switch(void)
 	}
 
 	if (wake_count[0] != repeat_count || wake_count[1] != repeat_count) {
-		CPRINTS("Unexpected counter values: %d %d %d",
-			wake_count[0], wake_count[1], wake_count[2]);
+		CPRINTS("Unexpected counter values: %d %d %d", wake_count[0],
+			wake_count[1], wake_count[2]);
 		return CTS_RC_FAILURE;
 	}
 
 	/* TODO: Verify no tasks are ready, no events are pending. */
-	if (*task_get_event_bitmap(TASK_ID_A)
-			|| *task_get_event_bitmap(TASK_ID_B)
-			|| *task_get_event_bitmap(TASK_ID_C)) {
+	if (*task_get_event_bitmap(TASK_ID_A) ||
+	    *task_get_event_bitmap(TASK_ID_B) ||
+	    *task_get_event_bitmap(TASK_ID_C)) {
 		CPRINTS("Events are pending");
 		return CTS_RC_FAILURE;
 	}
@@ -102,17 +102,17 @@ enum cts_rc test_task_priority(void)
 		return CTS_RC_FAILURE;
 	}
 
-	if (wake_count[0] != repeat_count - 1
-			|| wake_count[1] != repeat_count - 1) {
-		CPRINTS("Unexpected counter values: %d %d %d",
-			wake_count[0], wake_count[1], wake_count[2]);
+	if (wake_count[0] != repeat_count - 1 ||
+	    wake_count[1] != repeat_count - 1) {
+		CPRINTS("Unexpected counter values: %d %d %d", wake_count[0],
+			wake_count[1], wake_count[2]);
 		return CTS_RC_FAILURE;
 	}
 
 	/* TODO: Verify no tasks are ready, no events are pending. */
-	if (*task_get_event_bitmap(TASK_ID_A)
-			|| *task_get_event_bitmap(TASK_ID_B)
-			|| *task_get_event_bitmap(TASK_ID_C)) {
+	if (*task_get_event_bitmap(TASK_ID_A) ||
+	    *task_get_event_bitmap(TASK_ID_B) ||
+	    *task_get_event_bitmap(TASK_ID_C)) {
 		CPRINTS("Events are pending");
 		return CTS_RC_FAILURE;
 	}
diff --git a/cts/task/th.c b/cts/task/th.c
index 41eab28462..257809b4b8 120000..100644
--- a/cts/task/th.c
+++ b/cts/task/th.c
@@ -1 +1,144 @@
-dut.c
\ No newline at end of file
+/* Copyright 2013 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Tasks for scheduling test.
+ */
+
+#include "common.h"
+#include "cts_common.h"
+#include "task.h"
+#include "timer.h"
+
+static int repeat_count;
+static int wake_count[3];
+
+void clean_state(void)
+{
+	wake_count[0] = wake_count[1] = wake_count[2] = 0;
+}
+
+void task_abc(void *data)
+{
+	int task_id = task_get_current();
+	int id = task_id - TASK_ID_A;
+	task_id_t next = task_id + 1;
+
+	if (next > TASK_ID_C)
+		next = TASK_ID_A;
+
+	task_wait_event(-1);
+
+	CPRINTS("%c Starting", 'A' + id);
+	cflush();
+
+	while (1) {
+		wake_count[id]++;
+		if (id == 2 && wake_count[id] == repeat_count) {
+			task_set_event(TASK_ID_CTS, TASK_EVENT_WAKE);
+			task_wait_event(0);
+		} else {
+			task_set_event(next, TASK_EVENT_WAKE);
+			task_wait_event(0);
+		}
+	}
+}
+
+void task_tick(void *data)
+{
+	task_wait_event(-1);
+	ccprintf("\n[starting Task T]\n");
+
+	/* Wake up every tick */
+	while (1)
+		/* Wait for timer interrupt message */
+		usleep(3000);
+}
+
+enum cts_rc test_task_switch(void)
+{
+	uint32_t event;
+
+	repeat_count = 3000;
+
+	task_wake(TASK_ID_A);
+	event = task_wait_event(5 * SECOND);
+
+	if (event != TASK_EVENT_WAKE) {
+		CPRINTS("Woken up by unexpected event: 0x%08x", event);
+		return CTS_RC_FAILURE;
+	}
+
+	if (wake_count[0] != repeat_count || wake_count[1] != repeat_count) {
+		CPRINTS("Unexpected counter values: %d %d %d", wake_count[0],
+			wake_count[1], wake_count[2]);
+		return CTS_RC_FAILURE;
+	}
+
+	/* TODO: Verify no tasks are ready, no events are pending. */
+	if (*task_get_event_bitmap(TASK_ID_A) ||
+	    *task_get_event_bitmap(TASK_ID_B) ||
+	    *task_get_event_bitmap(TASK_ID_C)) {
+		CPRINTS("Events are pending");
+		return CTS_RC_FAILURE;
+	}
+
+	return CTS_RC_SUCCESS;
+}
+
+enum cts_rc test_task_priority(void)
+{
+	uint32_t event;
+
+	repeat_count = 2;
+
+	task_wake(TASK_ID_A);
+	task_wake(TASK_ID_C);
+
+	event = task_wait_event(5 * SECOND);
+
+	if (event != TASK_EVENT_WAKE) {
+		CPRINTS("Woken up by unexpected event: 0x%08x", event);
+		return CTS_RC_FAILURE;
+	}
+
+	if (wake_count[0] != repeat_count - 1 ||
+	    wake_count[1] != repeat_count - 1) {
+		CPRINTS("Unexpected counter values: %d %d %d", wake_count[0],
+			wake_count[1], wake_count[2]);
+		return CTS_RC_FAILURE;
+	}
+
+	/* TODO: Verify no tasks are ready, no events are pending. */
+	if (*task_get_event_bitmap(TASK_ID_A) ||
+	    *task_get_event_bitmap(TASK_ID_B) ||
+	    *task_get_event_bitmap(TASK_ID_C)) {
+		CPRINTS("Events are pending");
+		return CTS_RC_FAILURE;
+	}
+
+	return CTS_RC_SUCCESS;
+}
+
+static void recurse(int x)
+{
+	CPRINTS("+%d", x);
+	msleep(1);
+	recurse(x + 1);
+	CPRINTS("-%d", x);
+}
+
+enum cts_rc test_stack_overflow(void)
+{
+	recurse(0);
+	return CTS_RC_FAILURE;
+}
+
+#include "cts_testlist.h"
+
+void cts_task(void)
+{
+	task_wake(TASK_ID_TICK);
+	cts_main_loop(tests, "Task");
+	task_wait_event(-1);
+}
diff --git a/cts/timer/cts.testlist b/cts/timer/cts.testlist
index 9b5da0d6c9..6567757ced 100644
--- a/cts/timer/cts.testlist
+++ b/cts/timer/cts.testlist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/cts/timer/dut.c b/cts/timer/dut.c
index 96d7c5a3cf..9f94b9a398 100644
--- a/cts/timer/dut.c
+++ b/cts/timer/dut.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/cts/timer/th.c b/cts/timer/th.c
index e82cac71ab..e301ce0e38 100644
--- a/cts/timer/th.c
+++ b/cts/timer/th.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/docs/code_coverage.md b/docs/code_coverage.md
index a15c61b358..7f0c544692 100644
--- a/docs/code_coverage.md
+++ b/docs/code_coverage.md
@@ -23,6 +23,29 @@ data into a code coverage report using the `lcov` and `genhtml` tools.
 
 The coverage report top-level page is `build/coverage/coverage_rpt/index.html`.
 
+To get a report for one specific board's coverage run these commands:
+
+```
+BOARD=eldrid
+make -j$(nproc) build/coverage/initial-${BOARD}.info test-coverage
+# Merge board coverage and test coverage
+lcov -o build/coverage/${BOARD}_merged.info --rc lcov_branch_coverage=1 \
+  -a build/coverage/initial-${BOARD}.info -a build/coverage/lcov.info
+# Filter out some unhelpful paths
+lcov -o build/coverage/${BOARD}_filtered.info --rc lcov_branch_coverage=1 \
+  -r build/coverage/${BOARD}_merged.info ${PWD}'/third_party/**' \
+  ${PWD}'/build/**' '/usr/include/**' '/usr/lib/**' '${PWD}/test/**' \
+  ${PWD}'/private/fingerprint/google-fpalg/mcutest/**'
+# Restrict to only files used by the board
+grep "SF:" "build/coverage/initial-${BOARD}.info" | sort -u | \
+      sed -e 's|^SF:||' | xargs lcov --rc lcov_branch_coverage=1 \
+      -o build/coverage/${BOARD}_final.info \
+      -e build/coverage/${BOARD}_filtered.info
+# Generate HTML
+genhtml --branch-coverage -q -o build/coverage/${BOARD}_rpt \
+  -t "${BOARD} coverage" -s build/coverage/${BOARD}_final.info
+```
+
 ### Noise in the build output
 
 When building for code coverage, you may see multiple warnings of the form
@@ -38,28 +61,90 @@ appear to be caused in part by using relative paths instead of absolute paths.)
 
 To build the Zephyr unit tests for code coverage run:
 
-`zmake test --host-tests-only --coverage`
-`genhtml -q -o build/zephyr/coverage_rpt/ build/zephyr/all_tests.info`
+`./twister -v -i --coverage -p native_posix -p unit_testing`
 
 The coverage report top-level page is
-`build/zephyr/coverage_rpt/index.html`.
+`twister-out/coverage/index.html`.
 
 However you probably want to merge that with a single board's coverage report
 also, so that you can include code that is not part of any test as well.
 
 ```
 zmake build --coverage herobrine
-zmake test --host-tests-only --coverage
+./twister -v -i --coverage -p native_posix -p unit_testing
 genhtml -q -s --branch-coverage -o build/zephyr/coverage_rpt/ \
-  build/zephyr/all_tests.info build/zephyr/herobrine/output/zephyr.info
+  twister-out/coverage.info build/zephyr/herobrine/output/zephyr.info
 ```
 
 The coverage report top-level page is
 `build/zephyr/coverage_rpt/index.html`.
 
 For coverage report for a single test you can run:
-`zmake test --coverage <TESTNAME>`
+`./twister -v -i --coverage -p native_posix -p unit_testing -s <pathToTest>/<testName>`
+
+Example of running test tasks.default from zephyr/test/tasks/testcase.yaml:
+`./twister -v -i --coverage -p native_posix -p unit_testing -s zephyr/test/tasks/tasks.default`
+
+## Code Coverage in CQ
+
+There are several ways to see the code coverage without running the tests
+locally, depending on what information you want to see. Many of the links
+below are only available to Googlers or TVCs with google.com accounts.
+
+### Code search
+
+To see the coverage of each directory, visit
+http://cs/chromeos_public/src/platform/ec/ and turn on the "Directory Coverage"
+layer.  The denominator for the percentage covered is not clear, so these
+numbers are really only useful if you are looking in very general terms. I.e.
+zephyr is covered better than common. Don't get too fixated on the specific
+percent shown. The results are also the last 7 days of builds combined, so there
+may be some odd results if the code has changed greatly in the last week.
+
+![Directory coverage screenshot](images/dir_coverage.png)
+
+The coverage of files is much more useful. If you are about to write a test
+and not sure what to focus on, you can look at the uncovered lines in code
+search. Visit [a file](http://cs/chromeos_public/src/platform/ec/common/mkbp_event.c)
+in code search and make sure the "File Coverage" layer is enabled. Lines that
+are not covered by any test are in red, tested lines are in green, and uncolored
+lines were not built at all in any board or test.
+
+![File coverage screenshot](images/file_coverage.png)
+
+### Presubmit
+
+Every gerrit cl, if you did a dry-run or full run of the CQ will have coverage
+results. They are slightly difficult to get to, but are very useful.
+
+On the "Checks" tab, find the build "firmware-zephyr-cov-cq" and open it.
+
+![Gerrit screenshot](images/gerrit_coverage_links.png)
+
+On the LUCI page, expand the "test firmware" step and click on "response". That
+will show you a very basic summary of the coverage.
+
+![LUCI screenshot test firmware](images/test_firmware.png)
+
+For a detailed report, you can download the coverage report. Expand "try to
+upload artifacts", then "upload artifacts", and click on "gs upload dir".
+
+![LUCI screenshot artifacts](images/artifacts.png)
+
+From there, click on the download icon for the html.tbz2 file, and untar it
+locally. Open lcov_rpt/index.html to view your results.
+
+![GCS screenshot](images/download_html.png)
+
+### Post-submit
+
+If you are interested in the state of the world, not a specific CL, and the
+coverage info in Code Search is not sufficient, you can download the coverage
+report from the post-submit CQ build.
+
+Visit https://ci.chromium.org/p/chromeos/builders/postsubmit/firmware-zephyr-cov-postsubmit
+and click on the latest successful build.
+
+![LUCI post-submit screenshot](images/postsubmit.png)
 
-Example:
-`zmake test --coverage test-drivers`
-`genhtml -q -o build/zephyr/test-drivers/output/coverage_rpt/ build/zephyr/test-drivers/output/zephyr.info`
+From there, it is exactly the same steps as above to get to the artifacts.
diff --git a/docs/configuration/ap_power_sequencing.md b/docs/configuration/ap_power_sequencing.md
index c5073d5809..ba9fc89f29 100644
--- a/docs/configuration/ap_power_sequencing.md
+++ b/docs/configuration/ap_power_sequencing.md
@@ -15,7 +15,7 @@ states (G3, S5, S3, S0, S0iX, etc). This includes the following tasks:
 
 The AP chipset options are grouped together in [config.h]. Select exactly one of
 the available AP chipset options (e.g. `CONFIG_CHIPSET_APOLLOLAKE`,
-`CONFIG_CHIPSET_BRASWELL`, etc). If the AP chipset support is not available,
+`CONFIG_CHIPSET_COMETLAKE`, etc). If the AP chipset support is not available,
 select `CONFIG_CHIPSET_ECDRIVEN` to enable basic support for handling S3 and S0
 power states.
 
diff --git a/docs/fingerprint/fingerprint-debugging.md b/docs/fingerprint/fingerprint-debugging.md
index d098ca4427..84e5c13c9c 100644
--- a/docs/fingerprint/fingerprint-debugging.md
+++ b/docs/fingerprint/fingerprint-debugging.md
@@ -197,7 +197,7 @@ In your editor, specify the IP address and port for `gdbserver`:
 You will also want to provide the symbol files:
 
 *   RW image: `build/<board>/RW/ec.RW.elf`
-*   RO image: `build/<board>/RO.ec.RO.elf`
+*   RO image: `build/<board>/RO/ec.RO.elf`
 
 Also, since we're compiling the firmware in the chroot, but your editor is
 running outside of the chroot, you'll want to remap the source code path to
diff --git a/docs/fingerprint/fingerprint-dev-for-partners.md b/docs/fingerprint/fingerprint-dev-for-partners.md
index e78fde5caa..20b89845aa 100644
--- a/docs/fingerprint/fingerprint-dev-for-partners.md
+++ b/docs/fingerprint/fingerprint-dev-for-partners.md
@@ -315,6 +315,11 @@ You can get a summary of the power over `N` seconds with:
 (chroot) $ dut-control -t N pp3300_dx_mcu_mv pp3300_dx_fp_mv pp1800_dx_fp_mv pp3300_dx_mcu_mw pp3300_dx_fp_mw pp1800_dx_fp_mw
 ```
 
+When measuring the power, make sure that any debuggers are disconnected. The
+most reliable way to make sure it is disconnected is to physically disconnect
+the debugger and servo_micro from the board. Then re-attach servo_micro and
+restart `servod`.
+
 <!-- mdformat off(b/139308852) -->
 *** note
 The `_mv` suffix denotes millivolt and `_mw` suffix denotes milliwatt.
@@ -485,6 +490,8 @@ From the DUT, flash the firmware you copied:
 
 ![CQ Prototype Environment]
 
+![FPMCU devboard environment v2 with satlab]
+
 ## Troubleshooting
 
 ### Dragonclaw Rev 0.2 Rework {#dragonclaw-rev-0.2-rework}
@@ -526,7 +533,7 @@ supply.
 (chroot) $ lsusb
 
 Bus 002 Device 003: ID 0897:0004 Lauterbach  # ← This is my Lauterbach (debugger)
-Bus 001 Device 013: ID 18d1:5002 Google Inc. # ← This is servo
+Bus 001 Device 013: ID 18d1:5002 Google LLC # ← This is servo
 ```
 
 ### "No servos found" when running servod
@@ -601,3 +608,7 @@ Make sure that this interface is disabled:
 <!-- https://docs.google.com/drawings/d/1w2qbb4AsSxY-KTK2vXZ6TKeWHveWvS3Dkgh61ocu0wc -->
 
 [CQ Prototype Environment]: ../images/CQ_Prototype_Environment.jpg
+
+<!-- https://docs.google.com/drawings/d/13hsnPBa1aeMVU7CjrK1nz-aeYSQcdLxrylOEJNOiEA0 -->
+
+[FPMCU devboard environment v2 with satlab]: ../images/FPMCU_devboard_environment_v2_with_Satlab.jpg
diff --git a/docs/fingerprint/fingerprint-factory-requirements.md b/docs/fingerprint/fingerprint-factory-requirements.md
index 76b3ada517..5116b2c77a 100644
--- a/docs/fingerprint/fingerprint-factory-requirements.md
+++ b/docs/fingerprint/fingerprint-factory-requirements.md
@@ -474,7 +474,7 @@ sensor (in nocturne), not the FPC 1025 sensor (hatch).
 Convert the buffer in proprietary format into png:
 
 ```bash
-(dut) $ /opt/fpc/fputils.py /tmp/fp.raw --png
+(dut) $ /usr/local/opt/fpc/fputils.py /tmp/fp.raw --png
 Extraction found 2 images
 Wrote /tmp/fp.0.png (14085 bytes)
 Wrote /tmp/fp.1.png (14025 bytes)
diff --git a/docs/fingerprint/fingerprint.md b/docs/fingerprint/fingerprint.md
index 04f5a6bab9..8d4995a0fa 100644
--- a/docs/fingerprint/fingerprint.md
+++ b/docs/fingerprint/fingerprint.md
@@ -322,7 +322,8 @@ a lot easier during both development and testing.
 ## Power
 
 See [Measuring Power] for instructions on how to measure power with the
-fingerprint development boards.
+fingerprint development boards. *Make sure that any debuggers are completely
+disconnected.*
 
 ### Dragonclaw v0.2
 
@@ -331,7 +332,7 @@ fingerprint development boards.
 ```
 
 **Firmware Version**:
-`bloonchipper_v2.0.4277-9f652bb3-RO_v2.0.7314-3dfc5ff6-RW.bin`
+`bloonchipper_v2.0.4277-9f652bb3-RO_v2.0.14348-e5fb0b9-RW.bin`
 
 #### MCU is idle
 
@@ -341,13 +342,13 @@ fingerprint development boards.
 
 ```
 @@               NAME  COUNT  AVERAGE  STDDEV      MAX      MIN
-@@       sample_msecs    113   533.56   40.91   658.52   447.06
-@@    pp1800_dx_fp_mv    113  1800.00    0.00  1800.00  1800.00
-@@    pp1800_dx_fp_mw    113     0.00    0.00     0.00     0.00
-@@    pp3300_dx_fp_mv    113  3280.00    0.00  3280.00  3280.00
-@@    pp3300_dx_fp_mw    113     0.01    0.05     0.26     0.00
-@@   pp3300_dx_mcu_mv    113  3280.00    0.00  3280.00  3280.00
-@@   pp3300_dx_mcu_mw    113    24.67    0.00    24.67    24.67
+@@       sample_msecs    478   125.49   26.02   431.96    92.23
+@@    pp1800_dx_fp_mv    478  1800.00    0.00  1800.00  1800.00
+@@    pp1800_dx_fp_mw    478     0.00    0.00     0.00     0.00
+@@    pp3300_dx_fp_mv    478  3280.00    0.00  3280.00  3280.00
+@@    pp3300_dx_fp_mw    478     0.00    0.03     0.26     0.00
+@@   pp3300_dx_mcu_mv    478  3280.00    0.00  3280.00  3280.00
+@@   pp3300_dx_mcu_mw    478    21.78    0.06    23.09    21.78
 ```
 
 #### MCU in low power mode (suspend)
@@ -358,13 +359,13 @@ fingerprint development boards.
 
 ```
 @@               NAME  COUNT  AVERAGE  STDDEV      MAX      MIN
-@@       sample_msecs    115   526.56   36.79   607.60   426.58
-@@    pp1800_dx_fp_mv    115  1800.00    0.00  1800.00  1800.00
-@@    pp1800_dx_fp_mw    115     0.00    0.00     0.00     0.00
-@@    pp3300_dx_fp_mv    115  3287.30    2.25  3288.00  3280.00
-@@    pp3300_dx_fp_mw    115     0.00    0.02     0.26     0.00
-@@   pp3300_dx_mcu_mv    115  3280.97    2.62  3288.00  3280.00
-@@   pp3300_dx_mcu_mw    115     4.02    0.64    10.76     3.94
+@@       sample_msecs    488   122.99   26.37   458.47    92.69
+@@    pp1800_dx_fp_mv    488  1800.00    0.00  1800.00  1800.00
+@@    pp1800_dx_fp_mw    488     0.00    0.00     0.00     0.00
+@@    pp3300_dx_fp_mv    488  3287.79    1.29  3288.00  3280.00
+@@    pp3300_dx_fp_mw    488     0.01    0.04     0.26     0.00
+@@   pp3300_dx_mcu_mv    488  3283.38    3.95  3288.00  3280.00
+@@   pp3300_dx_mcu_mw    488     1.57    0.59     9.73     1.31
 ```
 
 ### Icetower v0.1
@@ -385,7 +386,7 @@ measure releases before that point.
 ```
 
 **Firmware Version**:
-`dartmonkey_v2.0.2887-311310808-RO_v2.0.7304-441100b93-RW.bin`
+`dartmonkey_v2.0.2887-311310808-RO_v2.0.14340-6c1587ca7-RW.bin`
 
 #### MCU is idle
 
@@ -395,11 +396,11 @@ measure releases before that point.
 
 ```
 @@               NAME  COUNT  AVERAGE  STDDEV      MAX      MIN
-@@       sample_msecs    178   337.13   20.91   404.32   289.82
-@@    pp3300_dx_fp_mv    178  3256.00    0.00  3256.00  3256.00
-@@    pp3300_dx_fp_mw    178     0.00    0.00     0.00     0.00
-@@   pp3300_dx_mcu_mv    178  3248.00    0.00  3248.00  3248.00
-@@   pp3300_dx_mcu_mw    178    45.17    0.09    45.21    44.95
+@@       sample_msecs    523   114.85   18.33   386.55    88.95
+@@    pp3300_dx_fp_mv    523  3256.00    0.00  3256.00  3256.00
+@@    pp3300_dx_fp_mw    523     0.00    0.00     0.00     0.00
+@@   pp3300_dx_mcu_mv    523  3248.00    0.00  3248.00  3248.00
+@@   pp3300_dx_mcu_mw    523    43.86    0.10    43.91    43.65
 ```
 
 #### MCU in low power mode (suspend)
@@ -410,11 +411,11 @@ measure releases before that point.
 
 ```
 @@               NAME  COUNT  AVERAGE  STDDEV      MAX      MIN
-@@       sample_msecs    174   345.60   31.93   457.62   283.00
-@@    pp3300_dx_fp_mv    174  3264.00    0.00  3264.00  3264.00
-@@    pp3300_dx_fp_mw    174     0.00    0.00     0.00     0.00
-@@   pp3300_dx_mcu_mv    174  3260.69    3.94  3264.00  3256.00
-@@   pp3300_dx_mcu_mw    174     5.47    0.10     5.48     4.17
+@@       sample_msecs    501   119.79   14.72   381.92    89.22
+@@    pp3300_dx_fp_mv    501  3256.00    0.00  3256.00  3256.00
+@@    pp3300_dx_fp_mw    501     0.00    0.00     0.00     0.00
+@@   pp3300_dx_mcu_mv    501  3256.00    0.00  3256.00  3256.00
+@@   pp3300_dx_mcu_mw    501     5.74    0.28    11.98     5.73
 ```
 
 ## ChromeOS Build (portage / ebuild)
diff --git a/docs/gitlab.md b/docs/gitlab.md
new file mode 100644
index 0000000000..9f8d07ceec
--- /dev/null
+++ b/docs/gitlab.md
@@ -0,0 +1,84 @@
+# Gitlab CI
+
+The Zephyr EC Test Team uses external Gitlab CI jobs to generate code coverage
+reports. These CI jobs are defined in the `.gitlab-ci.yml` file in
+`platform/ec`.
+
+[TOC]
+
+## Running CI jobs locally
+
+For development purposes, it is possible to run the CI jobs on a local machine
+using Docker and `gitlab-runner`.
+
+Note: not all features of Gitlab CI are available when running builds locally.
+For example, the local runner cannot build dependencies specified in the
+`needs:` sections. (But you can run jobs individually). More details can be
+found in the [`gitlab-runner` docs]
+(https://docs.gitlab.com/runner/commands/#limitations-of-gitlab-runner-exec).
+
+### Installation
+
+First, you must [install Docker](https://docs.docker.com/get-docker/) on your
+system. This is out of the scope of this guide, but there are many resources
+on the Internet describing how to do this. Docker allows the CI jobs to run in a
+controlled environment using containers, ensuring that the jobs run consistently
+and without needing to pollute your own system with the many dependencies.
+
+Next, install the Gitlab Runner. This application is able interpret the
+`.gitlab-ci.yml` file, spawn Docker containers to run jobs, and report back
+results and artifacts. Usually, runners are deployed in fleets and configured to
+register with a Gitlab server, which can push CI jobs to individual runners to
+execute. However, it is also possible to use the runner in a purely local mode
+using `gitlab-runner exec`.
+
+Full instructions are available on the
+[Gitlab website](https://docs.gitlab.com/runner/install/), but the fastest way
+to get it for Debian-based systems is to download and install the package
+directly:
+
+```
+wget https://gitlab-runner-downloads.s3.amazonaws.com/latest/deb/gitlab-runner_amd64.deb
+sudo dpkg -i gitlab-runner_amd64.deb
+```
+
+### Running a Job
+
+Once Docker and the Gitlab Runner are installed, invoke it as follows. This
+takes place outside of the
+
+```
+(outside)
+mkdir ~/gitlab-runner-output  # Do once
+
+cd ~/chromiumos/src/platform/ec
+sudo gitlab-runner exec docker \
+    --docker-volumes "$HOME/chromiumos/:$HOME/chromiumos/" \
+    --docker-volumes "$HOME/gitlab-runner-output:/builds" \
+    <name of job>
+```
+
+Please note:
+  * `$HOME/chromiumos` should be adjusted to wherever your tree is checked out
+    to. The reason it is necessary to mount the entire source tree to the
+    Docker container (as opposed to just `platform/ec`, which is done
+    automatically) is because the runner needs access to the Git database in
+    order to clone the source code. Because the `platform/ec` repository is
+    governed by the `repo` tool, the Git database is actually located at
+    `$HOME/chromiumos/.repo/projects/src/platform/ec.git`. (The `.git` directory
+    in `platform/ec` is merely a symlink)
+  * The second mount causes the runner's work directory to be backed by a
+    directory on your own system so that you can examine the artifacts after the
+    job finishes and the container is stopped.
+  * `<name of job>` is one of the jobs defined in `.gitlab-ci.yml`, such as
+    `twister_coverage`.
+  * You may see error messages like `ERROR: Could not create cache adapter`.
+    These appear to be benign, although getting the cache to work might improve
+    subsequent build times. This may be investigated at a later date.
+
+### Accessing Artifacts
+
+If you used the command as shown above, all of the build artifacts and source,
+as checked out by the Gitlab runner, should be under `~/gitlab-runner-output`.
+This will persist after the container exits but also get overwritten again on
+the next run.
diff --git a/docs/ide-support.md b/docs/ide-support.md
index cec196be58..1a8abda422 100644
--- a/docs/ide-support.md
+++ b/docs/ide-support.md
@@ -1,5 +1,7 @@
 # IDE Support
 
+This document explains how to configure IDEs to better support the EC codebase.
+
 [TOC]
 
 ## Odd File Types
@@ -12,16 +14,17 @@ Patterns                                              | Vague Type
 ----------------------------------------------------- | ----------
 `README.*`                                            | Text
 `Makefile.rules`, `Makefile.toolchain`                | Makefile
+`Makefile.ide`                                        | Makefile
 `gpio.wrap`                                           | C Header
 `gpio.inc`                                            | C Header
 `*.tasklist`, `*.irqlist`, `*.mocklist`, `*.testlist` | C Header
 
 ## IDE Configuration Primitives
 
-Due to the way most EC code has been structured, you can typically only safely
-inspect a configuration for a single image (RO or RW) for a single board. Thus,
-you need to specify the specific board/image pair when requesting defines and
-includes.
+EC firmware presents some unique challenges because it is designed to support a
+number of different MCUs and board configurations, each of which is split across
+separate RO (Read-Only) and RW (Read-Write) applications. For this reason, you
+must specify the specific board/image pair when requesting defines and includes.
 
 Command                                      | Description
 -------------------------------------------- | ------------------------------
@@ -36,8 +39,11 @@ includes selectable sub-configurations for every board/image pair.
 1.  From the root `ec` directory, do the following:
 
     ```bash
-    mkdir -p .vscode
-    ./util/ide-config.sh vscode all:RW all:RO | tee .vscode/c_cpp_properties.json
+    (outside) $ mkdir -p .vscode
+    ```
+
+    ```bash
+    (chroot) $ ./util/ide-config.sh vscode all:RW all:RO | tee .vscode/c_cpp_properties.json
     ```
 
 2.  Open VSCode and navigate to some C source file.
@@ -53,5 +59,63 @@ includes selectable sub-configurations for every board/image pair.
     to copy the default settings to `.vscode/settings.json`:
 
     ```bash
-    cp .vscode/settings.json.default .vscode/settings.json
+    (outside) $ cp .vscode/settings.json.default .vscode/settings.json
+    ```
+
+## VSCode CrOS IDE
+
+CrOS IDE is a VSCode extension to enable code completion and navigation for
+ChromeOS source files.
+
+Support for `platform/ec` is not available out of the box (yet), but can be
+manually enabled following these steps.
+
+### Prerequisites
+
+Install CrOS IDE following the [quickstart guide]
+
+<!-- mdformat off(b/139308852) -->
+*** note
+NOTE: CrOS IDE uses the VSCode extension `clangd` for code completion and
+navigation. The installation of CrOS IDE disables the built-in
+`C/C++ IntelliSense` because it is not compatible with `clangd`.
+***
+<!-- mdformat on -->
+
+### Configure EC Board
+
+1.  Enter the EC repository:
+
+    ```bash
+    (chroot) $ cd ~/chromiumos/src/platform/ec
     ```
+
+1.  Create a `compile_commands.json` for the all EC boards:
+
+    ```bash
+    (chroot) $ make all-ide-compile-cmds -j
+    ```
+
+1.  Select a particular board:
+
+    ```bash
+    (chroot) $ export BOARD=bloonchipper
+    ```
+
+1.  Copy the new `compile_commands.json` in the root of the EC repository:
+
+    ```bash
+    cp build/${BOARD}/RW/compile_commands.json .
+    ```
+
+Note: a single `compile_commands.json` can only cover one specific build
+configuration. Only the `compile_commands.json`placed in the root of the EC
+repository is considered active. When the build configuration changes (e.g. user
+wants to use a different board), repeat steps 3 and 4 to replace the active
+`compile_commands.json` file.
+
+To create a `compile_commands.json` for a specific EC board:
+
+```bash
+(chroot) $ make BOARD=${BOARD} ide-compile-cmds
+```
diff --git a/docs/images/CQ_Prototype_Environment.jpg b/docs/images/CQ_Prototype_Environment.jpg
index 77b39d9470..192fe139fe 100644
--- a/docs/images/CQ_Prototype_Environment.jpg
+++ b/docs/images/CQ_Prototype_Environment.jpg
diff --git a/docs/images/FPMCU_devboard_environment_v2_with_Satlab.jpg b/docs/images/FPMCU_devboard_environment_v2_with_Satlab.jpg
new file mode 100644
index 0000000000..c3663f7401
--- /dev/null
+++ b/docs/images/FPMCU_devboard_environment_v2_with_Satlab.jpg
diff --git a/docs/images/artifacts.png b/docs/images/artifacts.png
new file mode 100644
index 0000000000..2981509362
--- /dev/null
+++ b/docs/images/artifacts.png
diff --git a/docs/images/dir_coverage.png b/docs/images/dir_coverage.png
new file mode 100644
index 0000000000..152b2711a2
--- /dev/null
+++ b/docs/images/dir_coverage.png
diff --git a/docs/images/download_html.png b/docs/images/download_html.png
new file mode 100644
index 0000000000..399d098936
--- /dev/null
+++ b/docs/images/download_html.png
diff --git a/docs/images/file_coverage.png b/docs/images/file_coverage.png
new file mode 100644
index 0000000000..f110e44200
--- /dev/null
+++ b/docs/images/file_coverage.png
diff --git a/docs/images/gerrit_coverage_links.png b/docs/images/gerrit_coverage_links.png
new file mode 100644
index 0000000000..43afac943e
--- /dev/null
+++ b/docs/images/gerrit_coverage_links.png
diff --git a/docs/images/postsubmit.png b/docs/images/postsubmit.png
new file mode 100644
index 0000000000..65c630276f
--- /dev/null
+++ b/docs/images/postsubmit.png
diff --git a/docs/images/test_firmware.png b/docs/images/test_firmware.png
new file mode 100644
index 0000000000..42f707810a
--- /dev/null
+++ b/docs/images/test_firmware.png
diff --git a/docs/ite-ec-reflashing.md b/docs/ite-ec-reflashing.md
new file mode 100644
index 0000000000..59cfc8f303
--- /dev/null
+++ b/docs/ite-ec-reflashing.md
@@ -0,0 +1,194 @@
+# ITE EC firmware reflashing via Servo: How it works
+
+This doc: [http://go/cros-ite-reflash-design](https://goto.google.com/cros-ite-ec-reflash-design)
+<br>
+First written: 2022-08-15
+<br>
+Last updated: 2022-08-24
+
+Familiarity with [Chromium OS](https://www.chromium.org/chromium-os) and
+[Embedded Controller (EC)](../README.md) development is assumed.
+
+[TOC]
+
+## Background
+
+### Other documents
+* [Reflashing an ITE EC](../util/iteflash.md)
+* Googlers, and Partners involved in ITE EC projects only:
+  [The State of ITE CrOS EC Reflashing](https://goto.google.com/cros-ite-ec-reflash-state)
+  * That document is not public, do not request access if you lack it.
+* `i2c-pseudo` [README](../extra/i2c_pseudo/README)
+* `i2c-pseudo` [Documentation.txt](../extra/i2c_pseudo/Documentation.txt)
+
+### Terminology
+
+**EC** refers to an
+[Embedded Controller](https://en.wikipedia.org/wiki/Embedded_controller)
+(microcontroller).
+
+**ITE EC** refers to the [ITE](http://www.ite.com.tw/)
+[IT8320](http://www.ite.com.tw/en/product/view?mid=96)
+[Embedded Controller (EC)](https://en.wikipedia.org/wiki/Embedded_controller)
+microcontroller when used as a Chromium OS / Chrome OS EC.
+
+**CrOS** refers to Chromium OS, Chrome OS, or both, depending on the context.
+The distinction between Chromium OS and Chrome OS is largely immaterial to this
+document.
+
+**DUT Controller Servo** refers to a device that provides direct access
+to various circuits on a Chrome OS device motherboard. As of this writing, the
+most common DUT controller [servos](https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/refs/heads/main/docs/servo.md) used by
+CrOS developers are
+[CR50 (CCD)](https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/refs/heads/main/docs/ccd.md),
+`C2D2`,
+[Servo Micro](https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/refs/heads/main/docs/servo_micro.md), and
+[Servo v2](https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/refs/heads/main/docs/servo_v2.md). (Note that
+[Servo v4](https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/refs/heads/main/docs/servo_v4.md) and
+[Servo v4.1](https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/refs/heads/main/docs/servo_v4p1.md) are **not**
+DUT Controller Servos. They are Hub Servos, and are typically used in conjection with a DUT Controller Servo. Hub Servos are not directly involved in EC reflashing.)  See also
+[Case-Closed Debug in Chromebooks and Servo Micro](https://chromium.googlesource.com/chromiumos/platform/ec/+/refs/heads/main/board/servo_micro/ccd.md).
+
+**Servod** refers to a piece of software that runs on a USB host and provides
+interfaces for controlling a Servo connected to the host as a USB device. See [servod](https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/refs/heads/main/docs/servod.md).
+
+## Core steps
+
+Two things need to happen:
+
+1.  Send special non-I2C waveforms over I2C clock and data lines to the ITE EC,
+    to enable a debug mode in the EC where it will respond at a predefined
+    I2C address as an I2C peripheral.
+    * This debug mode is implemented by ITE in silicon and/or immutable
+      firmware, it is not part of Chrome OS EC firmware. It is available even
+      if Chrome OS RO+RW firmware on the EC is corrupted.
+
+1.  Communicate with and control the ITE EC using its I2C-based debug mode. All
+    signals on the I2C bus in question are now actual I2C, with the ITE EC
+    acting as an I2C peripheral device. The EC firmware gets sent as I2C
+    payload.
+    * If the previous step is not successful, then the EC will not respond to
+      I2C messages.
+
+The DUT Controller Servo performs these steps.
+
+## Control flow
+
+[flash_ec](https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/util/flash_ec)
+is the user interface for all Chrome OS device EC reflashing via Servos.
+`servod` must be running to use `flash_ec`.
+
+### Original control flow, for Servo v2 only
+
+The original implementation of ITE EC reflashing via Servo is only compatible
+with Servo v2, due to interfacing directly with its FTDI USB to MPSSE IC
+(FTDI FT4232HL).
+
+1.  `flash_ec` tells `servod` to close its interface for controlling the
+    `Servo v2` FTDI USB device.
+    * This breaks the layering of `servod` as the interface through which
+      servos are controlled, and is a maintenance + complexity burden to
+      support in `servod`. No other servo I2C interfaces in `servod` support or
+      need this functionality of relinquishing control.
+1.  `flash_ec` invokes [iteflash](https://chromium.googlesource.com/chromiumos/platform/ec/+/refs/heads/main/util/iteflash.c).
+1.  `iteflash` takes control of the `Servo v2` FTDI USB device.
+1.  `iteflash` [bit-bangs](https://en.wikipedia.org/wiki/Bit_banging) the
+    special waveforms using the `Servo v2` FTDI USB device.
+1.  `iteflash` uses FTDI I2C functionality (not bit-banging) to talk I2C with
+    the ITE EC, including sending the EC firmware as payload in I2C messages.
+1.  `flash_ec` tells `servod` to reopen its `Servo v2` FTDI USB interface.
+
+### New control flow through servod, for all other DUT controller servo types
+
+1.  When `servod` starts, it creates a pseudo I2C adapter in Linux for every
+    servo I2C bus it controls, if the `i2c-pseudo` module is loaded.
+    * This pseudo I2C adapter can be used on the host system as if it were a
+      native I2C bus, including from userspace if the `i2c-dev` module is
+      loaded.
+    * For more information on the `i2c-pseudo` module see
+      [Reflashing an ITE EC](../util/iteflash.md), as well as `i2c-pseudo`'s
+      [README](../extra/i2c_pseudo/README) and
+      [Documentation.txt](../extra/i2c_pseudo/Documentation.txt).
+1.  `flash_ec` issues a `servod` command for the DUT controller servo to send
+    the special waveforms.
+    * For `Servo Micro` and `C2D2` all `servod` needs to do is issue a
+      servo console command, `enable_ite_dfu`, which triggers a
+      servo firmware function to perform the special waveforms.
+      * The servo does not know what kind of DUT it is connected to, thus the
+        `enable_ite_dfu` console commands are always available. The
+        special waveforms will not do anything useful unless the DUT has
+        an ITE EC.
+    * `CR50` (CCD) is mostly the same, except:
+      1.  CCD must be unlocked and the `ccd_i2c_en` CCD capability must be set
+          to `Always`.
+      1.  The `CR50` firmware function for sending the special waveforms is
+          invoked by a special I2C message, not a console command.
+      1.  `CR50` must reboot itself to perform the special waveforms. During
+          normal operation `CR50` has deliberate clock jitter which would
+          prevent accurately preforming the waveforms. This jitter cannot
+          safely be disabled, except on reset, and only while the `AP` is held
+          in reset.
+    * [Future] If we were to support this control flow with `Servo v2`, the
+      cleanest way would be to move the FTDI-based bit-banging of the
+      special waveforms from `iteflash` into `servod` itself, as a C/C++
+      extension, so that `flash_ec` can trigger it with a `servod` command the
+      same as for other servo types. This would allow removing the hack in
+      `servod` to relinquish control of the `Servo v2` FTDI USB interface.
+      * Proof-of-concept [CL:1522847](https://crrev.com/c/1522847) adds support
+        for using Servo v2 via `servod`. However as of this writing that CL
+        ([patchset 14](https://crrev.com/c/1522847/14)) only changes the I2C
+        communication path, it does NOT move the special waveforms into
+        `servod`, which is needed to remove the `servod` I2C interface
+        close + reopen hack and fully merge the Servo v2 ITE EC reflashing into
+        this new control flow.
+1.  `flash_ec` asks `servod` for the local Linux i2c-dev path of the
+    DUT Controller Servo's DUT-connected I2C interface (which is backed by
+    `servod` itself via the `i2c-pseudo` module).
+1.  `flash_ec` invokes `iteflash`, passing it the i2c-dev path given by
+    `servod`.
+1.  `iteflash` performs the EC firmware update via the i2c-dev interface.
+
+## Why `i2c-pseudo` and alternative implementations considered
+
+Instead of using `i2c-dev` Linux I2C interfaces, `iteflash` could communicate
+directly with `servod` using a custom protocol. This would make `iteflash`
+dependent on `servod` and whatever custom protocol we come up with, as there is
+no standard userspace<->userspace I2C interface to implement.
+
+In the future we may choose to implement Servo I2C interfaces as actual
+host-side Linux drivers, which `servod` would use via `i2c-dev`
+(which it supports already!). Since the `flash_ec` and `iteflash` portions of
+this process are built around `i2c-dev` now, they should continue working with
+no changes needed for this scenario.
+
+Why bother with i2c-pseudo at all then? Why not go straight to reimplementing
+the Servo I2C interfaces as new Linux I2C adapter drivers, instead of
+implementing the new `i2c-pseudo` driver?
+
+Rearchitecting the Servo I2C interfaces is not something to be considered
+lightly, and not worthwhile just for ITE EC reflashing. By staying with the
+existing `servod` Servo I2C implementations we have not introduced any
+dependency on new kernel modules for *existing* `servod` functionality. Only
+the new ITE EC reflashing functionality depends on `i2c-pseudo`. As with
+`i2c-pseudo` we would need to rely on out-of-tree kernel module distribution
+for these new Servo I2C modules until eventual upstream acceptance +
+percolation down to distribution Linux kernels, with no guarantee of acceptance
+for our obscure Servo hardware. Depending on a new kernel module for this one
+new function of ITE EC reflashing is one thing. Requiring new modules for all
+`servod` use would be quite another. Realistically we would need to maintain
+fallback code in `servod` to use its existing internal Servo I2C interface
+implementations when the kernel ones aren't available, but that has a
+maintenance cost too. These same issues would be faced with every new
+generation of Servo, so this broad Servo + `servod` architectural change is not
+something to be considered lightly or just for ITE EC reflashing.
+
+`i2c-pseudo` has potential uses in the CrOS ecosystem beyond ITE EC reflashing.
+A big one is mocking I2C interfaces for driver and system tests. There is the
+longstanding `i2c-stub` module for this purpose, but its functionality is
+limited compared to `i2c-pseudo`, not all I2C device behavior can be modeled
+with `i2c-stub`. Also by having the `servod` I2C pseudo interfaces, one can
+conveniently use the standard Linux I2C command line tools
+(i2cget(8), i2cset(8), i2ctransfer(8), etc) for interfacing with Servo and DUT
+I2C devices. While it is unlikely that i2c-pseudo will have any use in CrOS
+itself, it is expected to have further uses in both developer tooling and
+code tests.
diff --git a/docs/reducing_ec_image_size.md b/docs/reducing_ec_image_size.md
index 5e09c99e51..58ed66e25c 100644
--- a/docs/reducing_ec_image_size.md
+++ b/docs/reducing_ec_image_size.md
@@ -175,13 +175,13 @@ prj.conf file to disable the console command.
 | | CONFIG_CMD_CHGRAMP | `chgramp` | |
 | | CONFIG_CMD_CLOCKGATES | `clockgates` | |
 | | CONFIG_CMD_COMXTEST | `comxtest` | |
-| x | CONFIG_CMD_CRASH | `crash` | |
+| x | CONFIG_CMD_CRASH | `crash` | Used by TAST `crash.ECCrash`, FAFT `firmware_ECSharedMem` |
 | | CONFIG_CMD_DEVICE_EVENT | `deviceevent` | |
 | | CONFIG_CMD_DLOG | `dlog` | |
 | | CONFIG_CMD_ECTEMP | `ectemp` | |
 | | CONFIG_CMD_FASTCHARGE | `fastcharge` | Obsolete? use CONFIG_CMD_CHARGER_PROFILE_OVERRIDE? |
 | | CONFIG_CMD_FLASH | `flasherase`<br>`flashwrite`<br>`flashread` | |
-| | CONFIG_CMD_FLASHINFO | `flashinfo` | |
+| x | CONFIG_CMD_FLASHINFO | `flashinfo` | Used by TAST `firmware.ECSize` |
 | | CONFIG_CMD_FLASH_TRISTATE | `fpcapture`<br>`flash_tristate` | |
 | | CONFIG_CMD_FLASH_WP | `flashwp` | |
 | | CONFIG_CMD_FORCETIME | `forcetime` | |
@@ -208,14 +208,14 @@ prj.conf file to disable the console command.
 | | CONFIG_CMD_IDLE_STATS | `idlestats` | |
 | | CONFIG_CMD_INA | `ina` | |
 | | CONFIG_CMD_JUMPTAGS | `jumptags` | |
-| x | CONFIG_CMD_KEYBOARD | `8042`<br>`ksstate`<br>`kbpress` | |
+| x | CONFIG_CMD_KEYBOARD | `8042`<br>`ksstate`<br>`kbpress` | Used by `firmware_ECKeyboard` |
 | | CONFIG_CMD_LEDTEST | `ledtest` | |
 | | CONFIG_CMD_MCDP | `mcdp` | |
 | | CONFIG_CMD_MD | `md` | |
 | | CONFIG_CMD_MEM | | Not a console command - gates `md` and `rw` |
 | | CONFIG_CMD_MFALLOW | `mfallow` | |
 | | CONFIG_CMD_MMAPINFO | `mmapinfo` | |
-| x | CONFIG_CMD_PD | `pd` | Used by FAFT PD |
+| x | CONFIG_CMD_PD | `pd` | Used by FAFT PD, TAST `firmware.ECSystemLocked` |
 | | CONFIG_CMD_PD_DEV_DUMP_INFO | | Not a console command |
 | | CONFIG_CMD_PD_FLASH | `pd flash` | Not supported by TCPMv2 |
 | | CONFIG_CMD_PD_SRCCAPS_REDUCED_SIZE | `pd <port> srccaps` | Defining this reduces the verbosity of this command, saving bytes |
@@ -347,13 +347,14 @@ Disable all debug from ASSERT() calls.<br> EC is reset using a software breakpoi
 It is not recommended to disable `CONFIG_PLATFORM_EC_DEBUG_ASSERT_REBOOTS` on
 shipping firmware.
 
-### Disable console help
+### Disable console help and history
 
 The help strings can be removed from the final build, saving about 5000 bytes of
-flash space.
+flash space. The history command can also be disabled to save another 200 bytes
+of flash space.
 
-For cros-ec builds, add `#undef CONFIG_CONSOLE_CMDHELP` to the
-board.h/baseboard.h file.
+For cros-ec builds, add `#undef CONFIG_CONSOLE_CMDHELP` and `#undef
+CONFIG_CONSOLE_HISTORY` to the board.h/baseboard.h file.
 
 zephyr-ec builds use Zephyr's shell subsystem and by default enable the
 `CONFIG_SHELL_MINIMAL` option.  This option already disables shell help along
diff --git a/docs/zephyr/README.md b/docs/zephyr/README.md
index ded31b8d6d..3b8b8dc05e 100644
--- a/docs/zephyr/README.md
+++ b/docs/zephyr/README.md
@@ -26,6 +26,9 @@ new project variant.
 The [Zephyr New Board Checklist](zephyr_new_board_checklist.md) links to the
 documentation needed to configure individual EC features.
 
+The [Zephyr Troubleshooting](zephyr_troubleshooting.md) page lists few common
+errors and troubleshooting techniques used when working with Zephyr.
+
 ## Source Code Organization
 
 Zephyr EC images rely on multiple Chromium repositories to build Zephyr EC images.
@@ -119,4 +122,4 @@ The following provides an overview of the sub-directories found under
 [`third_party/zephyr/main`]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/zephyr/main
 [`third_party/zephyr/cmsis`]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/zephyr/cmsis
 [`platform/ec`]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec
-[`ec_app_main()`]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/app/ec/ec_app_main.c
\ No newline at end of file
+[`ec_app_main()`]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/app/ec/ec_app_main.c
diff --git a/docs/zephyr/project_config.md b/docs/zephyr/project_config.md
index f12d47ba36..f930908502 100644
--- a/docs/zephyr/project_config.md
+++ b/docs/zephyr/project_config.md
@@ -112,7 +112,7 @@ This file, should at minimum contain the following:
 ``` cmake
 cmake_minimum_required(VERSION 3.20.1)
 
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
 project(ec)
 ```
 
@@ -148,7 +148,7 @@ Below is an example of how programs may wish to structure this in
 `BUILD.py`:
 
 ``` python
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/docs/zephyr/zephyr_adc.md b/docs/zephyr/zephyr_adc.md
index c57f4bd3a6..0511668517 100644
--- a/docs/zephyr/zephyr_adc.md
+++ b/docs/zephyr/zephyr_adc.md
@@ -8,19 +8,11 @@
 
 ## Kconfig Options
 
-Kconfig Option                     | Default state | Documentation
-:--------------------------------- | :------------ | :------------
-`CONFIG_PLATFORM_EC_ADC`           | Enabled       | [EC ADC]
+The [`CONFIG_ADC`] option enables ADC support in the Zephyr EC application.
+Use the [`CONFIG_ADC_SHELL`] option to enable ADC related shell commands.
 
-The following options are available only when `CONFIG_PLATFORM_EC_ADC=y`.
-
-Kconfig sub-option                               | Default | Documentation
-:----------------------------------------------- | :-----: | :------------
-`CONFIG_ADC_SHELL`                               | n       | [CONFIG_ADC_SHELL]
-`CONFIG_PLATFORM_EC_ADC_CMD`                     | y       | [ADC cmd]
-`CONFIG_PLATFORM_EC_ADC_RESOLUTION`              | 10      | [ADC resolution]
-`CONFIG_PLATFORM_EC_ADC_OVERSAMPLING`            | 0       | [ADC oversampling]
-`CONFIG_PLATFORM_EC_ADC_CHANNELS_RUNTIME_CONFIG` | n       | [ADC runtime config]
+Refer to [Kconfig.adc] for all sub-options related to ADC support that are
+specific to the Zephyr EC application.
 
 ## Devicetree Nodes
 
@@ -56,7 +48,6 @@ enumeration and the Zephyr ADC driver's channel_id.
 named-adc-channels {
 	compatible = "named-adc-channels";
 	vbus {
-		label = "VBUS";
 		enum-name = "ADC_VBUS";
 		io-channels = <&adc0 1>;
 		/* Measure VBUS through a 1/10 voltage divider */
@@ -158,22 +149,18 @@ named-adc-channels {
 	compatible = "named-adc-channels";
 
 	adc_charger: charger {
-		label = "TEMP_CHARGER";
 		enum-name = "ADC_TEMP_SENSOR_CHARGER";
 		io-channels = <&adc0 0>;
 	};
 	adc_pp3300_regulator: pp3300_regulator {
-		label = "TEMP_PP3300_REGULATOR";
 		enum-name = "ADC_TEMP_SENSOR_PP3300_REGULATOR";
 		io-channels = <&adc0 1>;
 	};
 	adc_ddr_soc: ddr_soc {
-		label = "TEMP_DDR_SOC";
 		enum-name = "ADC_TEMP_SENSOR_DDR_SOC";
 		io-channels = <&adc0 8>;
 	};
 	adc_fan: fan {
-		label = "TEMP_FAN";
 		enum-name = "ADC_TEMP_SENSOR_FAN";
 		io-channels = <&adc0 3>;
 	};
@@ -182,17 +169,10 @@ named-adc-channels {
 
 [ADC]: ../ec_terms.md#adc
 [ADC Example]: ../images/volteer_adc.png
-[EC ADC]:
-https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.adc?q=%22menuconfig%20PLATFORM_EC_ADC%22&ss=chromiumos
-[CONFIG_ADC_SHELL]:
+[Kconfig.adc]: ../../zephyr/Kconfig.adc
+[`CONFIG_ADC`]:
+https://docs.zephyrproject.org/latest/kconfig.html#CONFIG_ADC
+[`CONFIG_ADC_SHELL`]:
 https://docs.zephyrproject.org/latest/kconfig.html#CONFIG_ADC_SHELL
-[ADC cmd]:
-https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.adc?q=%22config%20PLATFORM_EC_ADC_CMD%22&ss=chromiumos
-[ADC resolution]:
-https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.adc?q=%22config%20PLATFORM_EC_ADC_RESOLUTION%22&ss=chromiumos
-[ADC oversampling]:
-https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.adc?q=%22config%20PLATFORM_EC_ADC_OVERSAMPLING%22&ss=chromiumos
-[ADC runtime config]:
-https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/Kconfig.adc?q=%22config%20PLATFORM_EC_ADC_CHANNELS_RUNTIME_CONFIG%22&ss=chromiumos
 [named-adc.yaml]:
 ../../zephyr/dts/bindings/adc/named-adc.yaml
diff --git a/docs/zephyr/zephyr_battery.md b/docs/zephyr/zephyr_battery.md
index c84bcc3b8e..3dde8cb9cf 100644
--- a/docs/zephyr/zephyr_battery.md
+++ b/docs/zephyr/zephyr_battery.md
@@ -86,7 +86,7 @@ named-i2c-ports {
 	battery {
 		i2c-port = <{i2c_phandle}>;
 		remote-port = <{I2C_PASSTHRU-PORT-NUMBER}>;
-		enum-name = "I2C_PORT_BATTERY";
+		enum-names = "I2C_PORT_BATTERY";
 	};
 	...
 	...
diff --git a/docs/zephyr/zephyr_bc12.md b/docs/zephyr/zephyr_bc12.md
index 6fffc16358..a7f3431829 100644
--- a/docs/zephyr/zephyr_bc12.md
+++ b/docs/zephyr/zephyr_bc12.md
@@ -18,9 +18,14 @@ sub-options related to BC1.2 support.
 
 ## Devicetree Nodes
 
-A BC1.2 device node should be child of an USBC port node with a compatible
-property equals to "named-usbc-port". The USBC port node should have only one
-BC1.2 device node.
+The BC1.2 device node is added to the I2C bus node, and the  bc12  property on
+the USBC port node refers to the BC1.2 device.
+
+### Richtek RT1718S
+
+There are two nodes describing the Richtek RT1718, one for BC1.2
+[richtek,rt1718-bc12.yaml] and one for TCPC[richtek,rt1718s-tcpc.yaml]. The node
+for the TCPC contains information about I2C bus and address.
 
 ### Richtek RT1739
 
@@ -58,15 +63,6 @@ found in [shimmed_task_id.h].
 Example of defining a BC1.2 chip in DTS:
 
 ```
-named-i2c-ports {
-    compatible = "named-i2c-ports";
-    ...
-    c0_bc12: c0_bc12 {
-        i2c-port = <&i2c0_0>;
-        enum-name = "I2C_PORT_USB_C0_BC12";
-    };
-};
-
 gpio-interrupts {
     compatible = "cros-ec,gpio-interrupts"
     int_usb_c0_bc12: usb_c0_bc12 {
@@ -76,23 +72,26 @@ gpio-interrupts {
     };
 };
 
+&i2c2_0 {
+	bc12_port0: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+		irq = <&int_usb_c0_bc12>;
+	};
+};
+
 port0@0 {
     compatible = "named-usbc-port";
     reg = <0>;
-    bc12 {
-        compatible = "pericom,pi3usb9201";
-        status = "okay";
-        irq = <&int_usb_c0_bc12>;
-        port = <&c0_bc12>;
-        i2c-addr-flags = "PI3USB9201_I2C_ADDR_3_FLAGS";
-    };
+    bc12 = <&bc12_port0>;
 };
 ```
 
-`bc12` is a BC1.2 device node ("pericom,pi3usb9201" is a compatible that is
-used by one of the BC1.2 devices). The `bc12` is child of the `port0@0` which
-has to be the "named-usbc-port". Each "named-usbc-port" can have no more than
-one BC1.2 device node.
+`bc12_port0` is a BC1.2 device node ("pericom,pi3usb9201" is a compatible that
+is used by one of the BC1.2 devices). The `bc12_port0` is child of the `i2c2_0`
+which is an I2C controller device. Each "named-usbc-port" node can point one
+BC1.2 device node.
 
 [Kconfig.usb_charger]: https://source.chromium.org/chromium/chromiumos/platform/ec/+/HEAD:zephyr/Kconfig.usb_charger
 [richtek,rt1739-bc12.yaml]: https://source.chromium.org/chromium/chromiumos/platform/ec/+/HEAD:zephyr/dts/bindings/usbc/richtek,rt1739-bc12.yaml
diff --git a/docs/zephyr/zephyr_build.md b/docs/zephyr/zephyr_build.md
index 8668c50e11..a80fe06d98 100644
--- a/docs/zephyr/zephyr_build.md
+++ b/docs/zephyr/zephyr_build.md
@@ -38,7 +38,7 @@ For example, to build the EC for `skyrim`, run:
 (chroot) $ zmake build skyrim
 ```
 
-The output binary will then be located at `build/zephyr/skyrim/output/zephyr.bin`.
+The output binary will then be located at `build/zephyr/skyrim/output/ec.bin`.
 
 Additional output files you may find useful:
 
diff --git a/docs/zephyr/zephyr_charger.md b/docs/zephyr/zephyr_charger.md
index 3857571ad2..8bb4f8d3f5 100644
--- a/docs/zephyr/zephyr_charger.md
+++ b/docs/zephyr/zephyr_charger.md
@@ -56,7 +56,7 @@ named-i2c-ports {
 		/* TODO(b/228237412): Update this comment once charger chg_chips[] is
 		 * created by a shim driver.
 		 */
-   		enum-name = "I2C_PORT_CHARGER";
+   		enum-names = "I2C_PORT_CHARGER";
    	};
 };
 ```
diff --git a/docs/zephyr/zephyr_eeprom.md b/docs/zephyr/zephyr_eeprom.md
index f18669fd75..9bc2f8b092 100644
--- a/docs/zephyr/zephyr_eeprom.md
+++ b/docs/zephyr/zephyr_eeprom.md
@@ -41,7 +41,6 @@ An example definition of the Atmel AT24 is:
         cbi_eeprom: eeprom@50 {
             compatible = "atmel,at24";
             reg = <0x50>;
-            label = "EEPROM_CBI";
             size = <2048>;
             pagesize = <16>;
             address-width = <8>;
diff --git a/docs/zephyr/zephyr_gpio.md b/docs/zephyr/zephyr_gpio.md
index 5e70562ab9..5204e6107f 100644
--- a/docs/zephyr/zephyr_gpio.md
+++ b/docs/zephyr/zephyr_gpio.md
@@ -70,6 +70,15 @@ included from the main board DTS file.
 For platform specific features, other flags may be available in the Zephyr
 [dt-bindings/gpio/gpio.h] file, such as `GPIO_VOLTAGE_1P8`.
 
+### Alternate functions
+
+All pins are configured as GPIO by default, so normally pinctrl configuration
+for GPIO pins is not required. Note that on NPCX ECs some pins default to a
+non-GPIO function after reset. These are explicitly set to GPIO during
+initialization, based on the `def-io-conf-list` node in [npcx9.dtsi], so they
+do not need to be set to GPIO usage, but they need an explicit `pinctrl-x`
+entry to be set back to the specific function.
+
 ### Legacy enum-name usage
 
 Only GPIOs that require referencing from legacy common code should have
@@ -241,18 +250,18 @@ For example on the Volteer reference board:
 
 Low voltage pins configuration depends on the specific chip family.
 
-For Nuvoton, this is done using a [nuvoton,npcx-lvolctrl-def] devicetree node,
-with a `lvol-io-pads` property listing all the pins that have to be configured
-for low-voltage operation. For example:
+For Nuvoton, this is done using the `GPIO_VOLTAGE_1P8` flag in the `named-gpios`
+child node. For example
 
 ```
-def-lvol-io-list {
-        compatible = "nuvoton,npcx-lvolctrl-def";
-        lvol-io-pads = <
-                &lvol_iob3 /* EC_I2C_SENSOR_SCL */
-                &lvol_iob2 /* EC_I2C_SENSOR_SDA */
-        >;
-};
+named-gpios {
+        compatible = "named-gpios";
+        ...
+        ec-i2c-sensor-scl {
+                gpios = <&gpiob 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+        };
+        ...
+}
 ```
 
 For ITE, this is done using the `GPIO_VOLTAGE_1P8` flag in the `named-gpios`
@@ -456,4 +465,5 @@ project.
 [gpio.dts]: ../../zephyr/projects/volteer/volteer/gpio.dts
 [interrupts.dts]: ../../zephyr/projects/volteer/volteer/interrupts.dts
 [BUILD.py]: ../../zephyr/projects/volteer/volteer/BUILD.py
-[*node label*]: https://docs.zephyrproject.org/latest/build/dts/intro.html#dt-node-labels
\ No newline at end of file
+[*node label*]: https://docs.zephyrproject.org/latest/build/dts/intro.html#dt-node-labels
+[npcx9.dtsi]: https://github.com/zephyrproject-rtos/zephyr/blob/main/dts/arm/nuvoton/npcx9.dtsi
diff --git a/docs/zephyr/zephyr_i2c.md b/docs/zephyr/zephyr_i2c.md
index da54a373a5..f8d17381d7 100644
--- a/docs/zephyr/zephyr_i2c.md
+++ b/docs/zephyr/zephyr_i2c.md
@@ -101,7 +101,7 @@ named-i2c-ports {
         battery {
                 i2c-port = <&i2c0_0>;
                 remote-port = <0>;
-                enum-name = "I2C_PORT_BATTERY";
+                enum-names = "I2C_PORT_BATTERY";
         }
 };
 ```
@@ -115,13 +115,9 @@ named-i2c-ports {
         battery {
                 i2c-port = <&i2c0_0>;
                 remote-port = <0>;
-                enum-name = "I2C_PORT_BATTERY";
+                enum-names = "I2C_PORT_BATTERY",
+                	"I2C_PORT_CHARGER";
         }
-        charger {
-                i2c-port = <&i2c0_0>;
-                remote-port = <0>;
-                enum-name = "I2C_PORT_CHARGER";
-        };
 };
 ```
 
@@ -307,39 +303,30 @@ below:
 
 		i2c_sensor: sensor {
 			i2c-port = <&i2c0_0>;
-			enum-name = "I2C_PORT_SENSOR";
-		};
-		i2c-accel {
-			i2c-port = <&i2c0_0>;
-			enum-name = "I2C_PORT_ACCEL";
+			enum-names = "I2C_PORT_SENSOR",
+				"I2C_PORT_ACCEL";
 		};
 		i2c_usb_c0: usb-c0 {
 			i2c-port = <&i2c1_0>;
-			enum-name = "I2C_PORT_USB_C0";
+			enum-names = "I2C_PORT_USB_C0";
 		};
 		i2c_usb_c1: usb-c1 {
 			i2c-port = <&i2c2_0>;
-			enum-name = "I2C_PORT_USB_C1";
+			enum-names = "I2C_PORT_USB_C1";
 		};
 		usb1-mix {
 			i2c-port = <&i2c3_0>;
-			enum-name = "I2C_PORT_USB_1_MIX";
+			enum-names = "I2C_PORT_USB_1_MIX";
 		};
 		power {
 			i2c-port = <&i2c5_0>;
-			enum-name = "I2C_PORT_POWER";
-		};
-		battery {
-			i2c-port = <&i2c5_0>;
-			enum-name = "I2C_PORT_BATTERY";
+			enum-names = "I2C_PORT_POWER",
+				"I2C_PORT_BATTERY";
 		};
 		eeprom {
 			i2c-port = <&i2c7_0>;
-			enum-name = "I2C_PORT_EEPROM";
-		};
-		charger {
-			i2c-port = <&i2c7_0>;
-			enum-name = "I2C_PORT_CHARGER";
+			enum-names = "I2C_PORT_EEPROM",
+				"I2C_PORT_CHARGER";
 		};
 	};
 ```
diff --git a/docs/zephyr/zephyr_leds.md b/docs/zephyr/zephyr_leds.md
new file mode 100644
index 0000000000..b29b4ab610
--- /dev/null
+++ b/docs/zephyr/zephyr_leds.md
@@ -0,0 +1,223 @@
+# Zephyr EC LEDs
+
+[TOC]
+
+## Overview
+
+[LEDs](../ec_terms.md#led) provide status about the following:
+
+-   Dedicated battery state/charging state
+-   Chromebook power
+-   Adapter power
+-   Left side USB-C port (battery state/charging state)
+-   Right side USB-C port (battery state/charging state)
+-   Recovery mode
+-   Debug mode
+
+LEDs can be configured as simple GPIOs, with on/off control only, or as [PWM](../ec_terms.md#pwm) with
+adjustment brightness and color.
+
+## Kconfig Options
+
+The `CONFIG_PLATFORM_EC_LED_DT` option, found in the [Kconfig.led_dt](../../zephyr/Kconfig.led_dt) file, enables devicetree based configuration of LED
+policies and colors.
+
+Enabling the devicetree LED implementation requires that you disable the legacy EC implementation.
+
+Example:
+```
+# LED
+CONFIG_PLATFORM_EC_LED_COMMON=n
+CONFIG_PLATFORM_EC_LED_DT=y
+```
+
+Enable other [config options](../configuration/leds.md) supported in the legacy code.
+
+## Devicetree Nodes
+
+LEDs are configured in two steps.
+
+### Configure LED colors
+The LED colors are configured using either GPIO based LEDs or PWM based LEDs.
+
+#### GPIO based LEDs
+Configure GPIO based LEDs using `cros-ec,gpio-led-pins` compatible node described by [cros-ec,gpio_led_pins.yaml].
+
+Example:
+
+For this example, the board contains dual-channel LED, one channel turns on the blue color, and one channel turns on the amber color.
+To set the LED color to amber, the yellow channel is enabled and the blue channel is disabled.
+
+```
+gpio-led-pins {
+	compatible = "cros-ec,gpio-led-pins";
+        /* Amber - turn on yellow LED */
+	color_amber: color-amber {
+		led-pins = <&gpio_ec_chg_led_y_c1 1>,
+			   <&gpio_ec_chg_led_b_c1 0>;
+	};
+	/* Blue - turn on blue LED */
+	color_blue: color-blue {
+		led-pins = <&gpio_ec_chg_led_y_c1 0>,
+			   <&gpio_ec_chg_led_b_c1 1>;
+	};
+	/* White - turn on both LEDs */
+	color_white: color-white {
+		led-pins = <&gpio_ec_chg_led_y_c1 1>,
+			   <&gpio_ec_chg_led_b_c1 1>;
+	};
+	/* Off - turn off both LEDs */
+	color_off: color-off {
+		led-pins = <&gpio_ec_chg_led_y_c1 0>,
+			   <&gpio_ec_chg_led_b_c1 0>;
+	};
+};
+```
+GPIO LED Pins dts file example: [led_pins_herobrine.dts]
+
+#### PWM based LEDs
+Configure PWM based LEDs with two separate nodes.
+The `cros-ec,pwm-pin-config` node, described in [cros-ec,pwm_led_pin_config.yaml], configures the PWM channel and frequency.
+The `cros-ec,pwm-led-pins` node, described in [cros-ec,pwm_led_pins.yaml], configures the LED colors.
+PWM LEDs can vary duty-cycle percentage, providing finer color control over GPIO LEDs.
+
+Example:
+
+For this example, the board contains dual-channel LED, one channel controls white color intensity, and one channel controls the amber color intensity.
+To set the LED color to amber, the yellow channel duty-cycle is set to 100 percentage and white channel duty-cycle is set to 0.
+```
+pwm_pins {
+	compatible = "cros-ec,pwm-pin-config";
+
+	pwm_y: pwm_y {
+		#led-pin-cells = <1>;
+		pwms = <&pwm2 0 PWM_HZ(100) PWM_POLARITY_INVERTED>;
+	};
+
+	pwm_w: pwm_w {
+		#led-pin-cells = <1>;
+		pwms = <&pwm3 0 PWM_HZ(100) PWM_POLARITY_INVERTED>;
+	};
+};
+
+pwm-led-pins {
+	compatible = "cros-ec,pwm-led-pins";
+	pwm-frequency = <100>;
+	/* Amber - turn on yellow LED */
+	color_amber: color-amber {
+		led-pins = <&pwm_y 100>,
+			   <&pwm_w 0>;
+	};
+	/* White - turn on white LED */
+	color_white: color-white {
+		led-pins = <&pwm_y 0>,
+			   <&pwm_w 100>;
+	};
+	/* Off - turn off both LEDs */
+	color_off: color-off {
+		led-pins = <&pwm_y 0>,
+			   <&pwm_w 0>;
+	};
+};
+```
+
+PWM LED Pins dts file example: [led_pins_skyrim.dts]
+
+### Configure LED Policies
+`cros-ec,led-policy` nodes describe the LED policy and set the LED behavior by referencing `cros-ec,gpio-led-pins` or `cros-ec,pwm-led-pins` nodes.
+These are described in [cros-ec,led_policy.yaml]
+
+
+Example:
+
+Color policies to configure physical behavior of an LED
+
+e.g. If you want an LED to blink, create 2 color policies, one to turn on the LED and one to turn off the LED.
+
+```
+color-0 {
+	led-color = <&color_amber>;
+        period-ms = <1000>;
+        };
+color-1 {
+	led-color = <&color-off>;
+        period-ms = <1000>;
+        };
+```
+
+To tie this behavior with a system state, properties defining system state and color policies are added to `cros-ec,led-policy` node.
+
+e.g. To add a blinking behavior for a system state where charge-state is "PWR_STATE_DISCHARGE and chipset-state is "POWER_S3", a policy node
+is defined as below.
+
+```
+led-policy {
+	compatible = "cros-ec,led-policy";
+	...
+	...
+	power-state-discharge-s3 {
+		charge-state = "PWR_STATE_DISCHARGE";
+		chipset-state = "POWER_S3";
+
+		/* Amber 1 sec, off 3 sec */
+		color-0 {
+			led-color = <&color_amber>;
+			period-ms = <1000>;
+		};
+		color-1 {
+			led-color = <&color_off>;
+			period-ms = <3000>;
+		};
+	};
+	...
+	...
+}
+```
+
+Note: It is recommended to split the policy specification and the pins specification into two devicetree files. e.g. [led_policy_skyrim.dts],  [led_pins_skyrim.dts]
+
+LED policy dts file examples
+[led_policy_skyrim.dts], [led_policy_herobrine.dts]
+
+## Board Specific Code
+
+None
+
+## Threads
+
+The LEDs are controlled by hook task in the file [led_driver/led.c](https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/shim/src/led_driver/led.c).
+
+## Testing and Debugging
+TODO: Enable support for ledtest
+
+## Examples
+
+### How to setup LEDs and add nodes
+
+![Alt text](https://screenshot.googleplex.com/4eqXmo2jLcSD6eL.png)
+
+-   Look for the gpio/pwm pins in the schematic with which the LEDs are attached to.
+-   In the above snippet, LEDs are configured to use PWM pins and attached to PWM2 and PWM3.
+-   Add PWM config nodes as shown in [cros-ec,pwm_led_pin_config.yaml] and [led_pins_skyrim.dts].
+-   Add pin nodes based on the color of the LEDs attached as shown in [cros-ec,pwm_led_pins.yaml] and [led_pins_skyrim.dts]. Name the nodes according to the LED color for readability. e.g. `color-amber`
+-   Based on the device LED policy, create led_policy nodes as shown in [cros-ec,led_policy.yaml] and [led_policy_skyrim.dts].
+
+### PWM
+
+[Example CL enabling single port pwm based LEDs]
+
+### GPIO
+
+[Example CL enabling dual port gpio based LEDs]
+
+<!-- Reference Links -->
+[cros-ec,led_policy.yaml]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/dts/bindings/leds/cros-ec,led-colors.yaml
+[cros-ec,gpio_led_pins.yaml]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/dts/bindings/leds/cros-ec,gpio-led-pins.yaml
+[cros-ec,pwm_led_pins.yaml]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/dts/bindings/leds/cros-ec,pwm-led-pins.yaml
+[cros-ec,pwm_led_pin_config.yaml]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/dts/bindings/leds/cros-ec,pwm-led-pin-config.yaml
+[led_policy_skyrim.dts]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/projects/skyrim/led_policy_skyrim.dts
+[led_pins_skyrim.dts]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/projects/skyrim/led_pins_skyrim.dts
+[led_policy_herobrine.dts]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/projects/herobrine/led_policy_herobrine.dts
+[led_pins_herobrine.dts]: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/zephyr/projects/herobrine/led_pins_herobrine.dts
+[Example CL enabling single port pwm based LEDs]: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3651490
+[Example CL enabling dual port gpio based LEDs]: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3635067
diff --git a/docs/zephyr/zephyr_new_board_checklist.md b/docs/zephyr/zephyr_new_board_checklist.md
index eb4584af2c..9baaaf4c42 100644
--- a/docs/zephyr/zephyr_new_board_checklist.md
+++ b/docs/zephyr/zephyr_new_board_checklist.md
@@ -64,7 +64,7 @@ EC Feature                                                                  | Ne
 [Configure Batteries](./zephyr_battery.md)                                  | no
 [Configure CrOS Board Information (CBI)](./zephyr_cbi.md)                   | no
 [Configure Keyboard (TODO)](./zephyr_template.md)                           | no
-[Configure LEDs (TODO)](./zephyr_template.md)                               | no
+[Configure LEDs](./zephyr_leds.md)                                          | no
 [Configure Motion Sensors](./zephyr_motionsense.md)                         | no
 [Configure BC1.2 Charger Detector (TODO)](./zephyr_template.md)             | no
 [Configure ADC](./zephyr_adc.md)                                            | no
diff --git a/docs/zephyr/zephyr_temperature_sensor.md b/docs/zephyr/zephyr_temperature_sensor.md
index 15e93e1e4e..8ee87a84f7 100644
--- a/docs/zephyr/zephyr_temperature_sensor.md
+++ b/docs/zephyr/zephyr_temperature_sensor.md
@@ -74,22 +74,26 @@ on Zephyr-based boards.
 
 ## Device Tree Nodes
 
-Temperature sensors are declared in a `named-temp-sensors section` in the device
-tree. This example is from [zephyr/boards/arm/brya/brya.dts](../../zephyr/boards/arm/brya/brya.dts):
+Temperature sensors are declared as separate nodes and additional properties are
+defined by the `cros-ec,temp-sensors` node in the device tree. This example is
+from [zephyr/projects/brya/temp_sensors.dts](../../zephyr/projects/brya/temp_sensors.dts):
 
 ```
+	temp_ddr_soc: ddr_soc {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_30K9_47K_4050B>;
+		adc = <&adc_ddr_soc>;
+	};
+
 	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
 		ddr_soc {
-			compatible = "cros-ec,temp-sensor";
-			thermistor = <&thermistor_3V3_30K9_47K_4050B>;
-			label = "DDR and SOC";
-			enum-name = "TEMP_SENSOR_1_DDR_SOC";
 			temp_fan_off = <35>;
 			temp_fan_max = <60>;
 			temp_host_high = <85>;
 			temp_host_halt = <90>;
 			temp_host_release_high = <80>;
-			adc = <&adc_ddr_soc>;
+			sensor = <&temp_ddr_soc>;
 		};
 ```
 
diff --git a/docs/zephyr/zephyr_testing.md b/docs/zephyr/zephyr_testing.md
new file mode 100644
index 0000000000..5f5987686c
--- /dev/null
+++ b/docs/zephyr/zephyr_testing.md
@@ -0,0 +1,53 @@
+# Zephyr Testing Resources
+
+This is a compilation of resources for developers participating in the Zephyr
+EC Fix-it Week, running from 15 - 19 Aug 2022.
+
+Please note: many of the links in this document will only be accessible to
+Googlers.
+
+[TOC]
+
+## Introductory materials
+
+ * [Fix-it week Training Presentation](https://goto.google.com/cros-ec-fixit-week-presentation) -
+   by Yuval Peress (Start here - Googlers only)
+   * Ask questions during the live presentation using the
+     [Dory](https://goto.google.com/cros-ec-fixit-week-dory) (Google only)
+ * Sample CLs for your reference:
+   * [Writing a new emulator](https://crrev.com/c/2903206)
+   * [Writing a console command test ](https://crrev.com/c/3594484)
+   * [Writing a host command test](https://crrev.com/c/3530114)
+   * [Using test fixtures and local FFF mocks](https://crrev.com/c/3607055)
+   * [Defining global FFF mocks](https://crrev.com/c/3252365)
+   * [Resetting global FFF mocks](https://crrev.com/c/3500299)
+
+## Finding Work to do
+
+We have assembled a [hotlist](http://b/hotlists/4300616) of low-coverage areas
+in the codebase. Please remember to assign bugs to yourself to avoid duplicate
+work being performed and do not take bugs until you are ready to actively work
+on it.
+
+We also encourage you to check our coverage reports to identify files needing
+additional test coverage:
+
+ * [Gitlab coverage reports](https://gitlab.com/zephyr-ec/ec/-/jobs/artifacts/main/file/build/all_builds_filtered_rpt/index.html?job=merged_coverage)
+ * [Internal Code Search](https://goto.google.com/cros-ec-fixit-week-cs)
+   (enable the coverage layer - Googlers only)
+
+## Submitting tests for review
+
+The fastest way to have your code reviewed is to add
+`zephyr-test-eng@google.com` to your CL. This will randomly assign a
+member of the Zephyr EC Testing team to your CL. The team will be monitoring
+Gerrit extra closely during Fix-it week to streamline reviews. Please do _not_
+send CLs directly to individuals or to the wider Zephyr reviewers group.
+
+## Getting Help
+
+Questions on writing, running, and debugging tests should be asked in [YAQS with
+the zephyr-rtos-test topic](https://goto.google.com/cros-ec-fixit-week-yaqs).
+Part of our goal during Fix-it Week is to assemble a knowledge base of testing
+information. Your questions and the resulting dialogue will be very beneficial
+to future developers, so please ask away! (Googlers only)
diff --git a/docs/zephyr/zephyr_troubleshooting.md b/docs/zephyr/zephyr_troubleshooting.md
new file mode 100644
index 0000000000..646240ce18
--- /dev/null
+++ b/docs/zephyr/zephyr_troubleshooting.md
@@ -0,0 +1,184 @@
+# Zephyr Troubleshooting
+
+[TOC]
+
+## Devicetree
+
+The devicetree is made out of different dts and dtsi files, gets aggregated
+into a single `zephyr.dts` file and generates a `devicetree_generated.h` header
+with all the definitions used by the `DT_` macros.
+
+The build system lists the various overlay files specified by `BUILD.py`, for
+example:
+
+```
+-- Found devicetree overlay: /mnt/host/source/src/platform/ec/zephyr/projects/brya/adc.dts
+-- Found devicetree overlay: /mnt/host/source/src/platform/ec/zephyr/projects/brya/battery.dts
+-- Found devicetree overlay: /mnt/host/source/src/platform/ec/zephyr/projects/brya/cbi_eeprom.dts
+-- Found devicetree overlay: /mnt/host/source/src/platform/ec/zephyr/projects/brya/fan.dts
+...
+```
+
+Useful artifacts (always present):
+
+Aggregated devicetree file, after all the overlays, preprocessor and
+`gen_defines.py`:
+
+```
+build/zephyr/$PROJECT/build-ro/zephyr/zephyr.dts
+```
+
+Main devicetree output, flat representation of the tree and various node
+references, including ordinals of `dts_ord_...` structs:
+
+```
+./build/zephyr/$PROJECT/build-ro/zephyr/include/generated/devicetree_generated.h
+```
+
+For more details see: [CMake configuration phase](https://docs.zephyrproject.org/latest/build/cmake/index.html?highlight=gen_defines%20py#configuration-phase)
+
+## Node nomenclature
+
+```
+/ {
+        a-node {
+                subnode_nodelabel: a-sub-node {
+                        foo = <3>;
+                        label = "SUBNODE";
+                };
+        };
+};
+```
+
+- `/` is the root node
+- `a-node` and `a-sub-node` are node names
+- `subnode_nodelabel` is a nodelabel
+- `foo` is a property, `3` is the value
+- `label` is a property, `SUBNODE` is the value
+
+NOTE: `subnode_nodelabel` is a nodelabel, `label` is a label property.
+
+## Adding multiple nodelabels
+
+Code can have hardcoded nodelables, so sometimes it's useful to add extra
+nodelabels to an existing node (referenced by another nodelabel). To do that
+add an overlay with something similar to:
+
+```
+another_node_label: &subnode_nodelabel {
+};
+```
+
+## Undefined reference to \_\_device\_dts\_ord\_...
+
+This happens when some code refer to a device using `DT_DEVICE_GET`, but the
+corresponding `struct device` is not instantiated, either because the driver
+has not been enabled or because of a devicetree misconfiguration (missing
+`status = "okay"`).
+
+Quick fix: enable the corresponding driver (CONFIG_...=y) or fix the devicetree.
+
+Proper fix: find the code referencing to the undefined node, make sure that the
+corresponding Kconfig option depends on the subsystem being enabled (ADC,
+I2C...), make sure that the specific platform driver is enabled based on the
+devicetree (`default y` and `depends on DT_HAS_...`).
+
+## error: 'CONFIG_..._LOG_LEVEL' undeclared
+
+The `CONFIG_..._LOG_LEVEL` symbols are not defined directly (i.e. there's no
+Kconfig `config ..._LOG_LEVEL`), they are generated using the
+`subsys/logging/Kconfig.template.log_config` template.
+
+Quick fix: enable the logging subsystem (normally `CONFIG_LOG=y`
+`CONFIG_LOG_MODE_MINIMAL=y` in the project `prj.conf`), or change the code so
+that the driver builds without this config.
+
+Fix: make the driver depends on the logging subsystem being enabled (`depends
+on LOG`) or change the code to compile with `CONFIG_LOG=n`.
+
+## Menuconfig
+
+Sometimes it's useful to run the `menuconfig` target on a specific project,
+this can be done with:
+
+```
+ninja -C build/zephyr/$PROJECT/build-ro menuconfig
+```
+
+This exposes all the available options from the various Kconfig fragments and
+can be useful to validate that config constraints are working correctly.
+
+For example, searching for `^SSHELL$` (using the `/` key) shows:
+
+```
+Name: SHELL
+Prompt: Shell
+Type: bool
+Value: y
+
+Symbols currently n-selecting this symbol (no effect):
+...
+
+Symbols currently y-implying this symbol:
+  - CROS_EC
+  - PLATFORM_EC
+```
+
+## LTO
+
+Many compiler and linker error are very uninformative if LTO is enabled, for
+example a missing `struct device` can show as
+
+```
+/tmp/ccCiGy7c.ltrans0.ltrans.o:(.rodata+0x6a0): undefined reference to `__device_dts_ord_75'
+```
+
+Adding `CONFIG_LTO=n` to the corresponding `prj.conf` usually results in more
+useful error messages, for example:
+
+```
+modules/ec/libec_shim.a(adc.c.obj):(.rodata.adc_channels+0x58): undefined reference to `__device_dts_ord_75'
+```
+
+## Build artifacts
+
+The buildsystem can be configured to leave the build artifact next to the
+object files, this is useful to inspect the macro output. To do that use the
+`zmake` flag:
+
+```
+zmake build $PROJECT --extra-cflags=-save-temps=obj
+```
+
+This leaves a bunch of `.i` files in the build/ directory.
+
+For more information see: [Look at the preprocessor output](https://docs.zephyrproject.org/latest/build/dts/troubleshooting.html?highlight=save%20temps#look-at-the-preprocessor-output).
+
+This is also useful to analyze assembly errors, for example
+
+```
+/tmp/cctFuB4N.s: Assembler messages:
+/tmp/cctFuB4N.s:1869: Error: missing expression
+```
+
+becomes
+
+```
+zephyr/CMakeFiles/zephyr.dir/misc/generated/configs.c.s: Assembler messages:
+zephyr/CMakeFiles/zephyr.dir/misc/generated/configs.c.s:1869: Error: missing expression
+```
+
+## Statically initialized objects
+
+The `zephyr.elf` output file can be used with gdb to analyze all the statically
+allocated structures, for example:
+
+```
+$ arm-none-eabi-gdb build/zephyr/$PROJECT/output/zephyr-ro.elf
+(gdb) p fan_config
+$1 = {{pwm = {dev = 0x100ad244 <__device_dts_ord_169>, channel = 0, period = 1000000, flags = 0}, tach = 0x100ad43c <__device_dts_ord_172>}}
+(gdb) p __device_dts_ord_172.name
+$3 = 0x100ba480 "tach@400e1000"
+```
+
+If the symbol has been optimized, try rebuilding with `CONFIG_LTO=n`.
diff --git a/docs/zephyr/ztest.md b/docs/zephyr/ztest.md
index 6bb121045d..d782631cc3 100644
--- a/docs/zephyr/ztest.md
+++ b/docs/zephyr/ztest.md
@@ -142,7 +142,6 @@ find-and-replace.
 *   `TEST_BITS_CLEARED(a, bits)` to `zassert_true(a & (int)bits == 0, "%u, 0", a
     & (int)bits)`
 *   `TEST_ASSERT_ARRAY_EQ(s, d, n)` to `zassert_mem_equal(s, d, b, NULL)`
-*   `TEST_CHECK(n)` to `zassert_true(n, NULL)`
 *   `TEST_NEAR(a, b, epsilon, fmt)` to `zassert_within(a, b, epsilon, fmt, a)`
     *   Currently, every usage of `TEST_NEAR` involves floating point values
 *   `TEST_ASSERT_ABS_LESS(n, t)` to `zassert_true(abs(n) < t, "%d, %d", n, t)`
diff --git a/driver/accel_bma2x2.c b/driver/accel_bma2x2.c
index 6d2d596bea..08e818cb8d 100644
--- a/driver/accel_bma2x2.c
+++ b/driver/accel_bma2x2.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,6 +10,7 @@
  */
 
 #include "accelgyro.h"
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
 #include "accel_bma2x2.h"
@@ -20,7 +21,7 @@
 #include "util.h"
 
 #define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
 
 /* Number of times to attempt to enable sensor before giving up. */
 #define SENSOR_ENABLE_ATTEMPTS 5
@@ -45,7 +46,7 @@ static inline int raw_write8(const int port, const uint16_t i2c_addr_flags,
 
 static int set_range(struct motion_sensor_t *s, int range, int rnd)
 {
-	int ret,  range_val, reg_val, range_reg_val;
+	int ret, range_val, reg_val, range_reg_val;
 
 	/* Range has to be between 2G-16G */
 	if (range < 2)
@@ -105,16 +106,16 @@ static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
 	mutex_lock(s->mutex);
 
 	/* Determine the new value of control reg and attempt to write it. */
-	ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-			BMA2x2_BW_SELECT_ADDR, &odr_reg_val);
+	ret = raw_read8(s->port, s->i2c_spi_addr_flags, BMA2x2_BW_SELECT_ADDR,
+			&odr_reg_val);
 	if (ret != EC_SUCCESS) {
 		mutex_unlock(s->mutex);
 		return ret;
 	}
 	reg_val = (odr_reg_val & ~BMA2x2_BW_MSK) | odr_val;
 	/* Set output data rate. */
-	ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-			 BMA2x2_BW_SELECT_ADDR, reg_val);
+	ret = raw_write8(s->port, s->i2c_spi_addr_flags, BMA2x2_BW_SELECT_ADDR,
+			 reg_val);
 
 	/* If successfully written, then save the new data rate. */
 	if (ret == EC_SUCCESS)
@@ -212,8 +213,8 @@ static int perform_calib(struct motion_sensor_t *s, int enable)
 	if (!enable)
 		return EC_SUCCESS;
 
-	ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-			BMA2x2_OFFSET_CTRL_ADDR, &val);
+	ret = raw_read8(s->port, s->i2c_spi_addr_flags, BMA2x2_OFFSET_CTRL_ADDR,
+			&val);
 	if (ret)
 		return ret;
 	if (!(val & BMA2x2_OFFSET_CAL_READY))
@@ -237,8 +238,8 @@ static int perform_calib(struct motion_sensor_t *s, int enable)
 	val = ((BMA2x2_OFC_TARGET_0G << BMA2x2_OFC_TARGET_AXIS(X)) |
 	       (BMA2x2_OFC_TARGET_0G << BMA2x2_OFC_TARGET_AXIS(Y)) |
 	       (val << BMA2x2_OFC_TARGET_AXIS(Z)));
-	raw_write8(s->port, s->i2c_spi_addr_flags,
-		   BMA2x2_OFC_SETTING_ADDR, val);
+	raw_write8(s->port, s->i2c_spi_addr_flags, BMA2x2_OFC_SETTING_ADDR,
+		   val);
 
 	for (i = X; i <= Z; i++) {
 		val = (i + 1) << BMA2x2_OFFSET_TRIGGER_OFF;
@@ -275,8 +276,8 @@ static int init(struct motion_sensor_t *s)
 	/* This driver requires a mutex */
 	ASSERT(s->mutex);
 
-	ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-			BMA2x2_CHIP_ID_ADDR, &val);
+	ret = raw_read8(s->port, s->i2c_spi_addr_flags, BMA2x2_CHIP_ID_ADDR,
+			&val);
 	if (ret)
 		return EC_ERROR_UNKNOWN;
 
diff --git a/driver/accel_bma422.h b/driver/accel_bma422.h
index 0ab580235c..0b4f644101 100644
--- a/driver/accel_bma422.h
+++ b/driver/accel_bma422.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,6 +11,6 @@
 #include "accel_bma4xx.h"
 
 /* Chip ID of BMA422 */
-#define BMA422_CHIP_ID			0x12
+#define BMA422_CHIP_ID 0x12
 
 #endif /* __CROS_EC_ACCEL_BMA422_H */
diff --git a/driver/accel_bma4xx.c b/driver/accel_bma4xx.c
index 9b383edf80..a77b5ba589 100644
--- a/driver/accel_bma4xx.c
+++ b/driver/accel_bma4xx.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,6 +11,7 @@
 
 #include "accelgyro.h"
 #include "accel_bma422.h"
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
 #include "i2c.h"
@@ -20,7 +21,7 @@
 #include "util.h"
 
 #define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
 
 /**
  * Read 8bit register from accelerometer.
@@ -97,20 +98,19 @@ static int set_foc_config(struct motion_sensor_t *s)
 				   BMA4_NV_ACCEL_OFFSET_MSK));
 
 	/* Set accelerometer configurations to 50Hz,CIC, continuous mode */
-	RETURN_ERROR(bma4_write8(s, BMA4_ACCEL_CONFIG_ADDR,
-				 BMA4_FOC_ACC_CONF_VAL));
-
+	RETURN_ERROR(
+		bma4_write8(s, BMA4_ACCEL_CONFIG_ADDR, BMA4_FOC_ACC_CONF_VAL));
 
 	/* Set accelerometer to normal mode by enabling it */
 	RETURN_ERROR(bma4_set_reg8(s, BMA4_POWER_CTRL_ADDR,
-				   (BMA4_ENABLE <<  BMA4_ACCEL_ENABLE_POS),
+				   (BMA4_ENABLE << BMA4_ACCEL_ENABLE_POS),
 				   BMA4_ACCEL_ENABLE_MSK));
 
 	/* Disable advance power save mode */
-	RETURN_ERROR(bma4_set_reg8(s, BMA4_POWER_CONF_ADDR,
-				   (BMA4_DISABLE
-				    << BMA4_ADVANCE_POWER_SAVE_POS),
-				   BMA4_ADVANCE_POWER_SAVE_MSK));
+	RETURN_ERROR(
+		bma4_set_reg8(s, BMA4_POWER_CONF_ADDR,
+			      (BMA4_DISABLE << BMA4_ADVANCE_POWER_SAVE_POS),
+			      BMA4_ADVANCE_POWER_SAVE_MSK));
 
 	return EC_SUCCESS;
 }
@@ -120,7 +120,7 @@ static int wait_and_read_data(struct motion_sensor_t *s, intv3_t v)
 	int i;
 
 	/* Retry 5 times */
-	uint8_t reg_data[6] = {0}, try_cnt = 5;
+	uint8_t reg_data[6] = { 0 }, try_cnt = 5;
 
 	/* Check if data is ready */
 	while (try_cnt && (!(reg_data[0] & BMA4_STAT_DATA_RDY_ACCEL_MSK))) {
@@ -142,8 +142,8 @@ static int wait_and_read_data(struct motion_sensor_t *s, intv3_t v)
 				    BMA4_DATA_8_ADDR, reg_data, 6));
 
 	for (i = X; i <= Z; i++) {
-		v[i] = (((int8_t)reg_data[i * 2 + 1]) << 8)
-		       | (reg_data[i * 2] & 0xf0);
+		v[i] = (((int8_t)reg_data[i * 2 + 1]) << 8) |
+		       (reg_data[i * 2] & 0xf0);
 
 		/* Since the resolution is only 12 bits*/
 		v[i] = (v[i] / 0x10);
@@ -160,7 +160,7 @@ static int8_t perform_accel_foc(struct motion_sensor_t *s, int *target,
 	intv3_t accel_data, offset;
 
 	/* Structure to store accelerometer data temporarily */
-	int32_t delta_value[3] = {0, 0, 0};
+	int32_t delta_value[3] = { 0, 0, 0 };
 
 	/* Variable to define count */
 	uint8_t i, loop, sample_count = 0;
@@ -181,8 +181,10 @@ static int8_t perform_accel_foc(struct motion_sensor_t *s, int *target,
 	 * (unit of offset:mg)
 	 */
 	for (i = X; i <= Z; ++i) {
-		offset[i] = ((((delta_value[i] * 1000 * sens_range)
-			     / sample_count) / 2048) * -1);
+		offset[i] = ((((delta_value[i] * 1000 * sens_range) /
+			       sample_count) /
+			      2048) *
+			     -1);
 	}
 
 	RETURN_ERROR(write_accel_offset(s, offset));
@@ -199,7 +201,7 @@ static int perform_calib(struct motion_sensor_t *s, int enable)
 {
 	uint8_t config[2];
 	int pwr_ctrl, pwr_conf;
-	intv3_t target = {0, 0, 0};
+	intv3_t target = { 0, 0, 0 };
 	int sens_range = s->current_range;
 
 	if (!enable)
@@ -207,7 +209,7 @@ static int perform_calib(struct motion_sensor_t *s, int enable)
 
 	/* Read accelerometer configurations */
 	RETURN_ERROR(i2c_read_block(s->port, s->i2c_spi_addr_flags,
-			BMA4_ACCEL_CONFIG_ADDR, config, 2));
+				    BMA4_ACCEL_CONFIG_ADDR, config, 2));
 
 	/* Get accelerometer enable status to be saved */
 	RETURN_ERROR(bma4_read8(s, BMA4_POWER_CTRL_ADDR, &pwr_ctrl));
@@ -225,7 +227,7 @@ static int perform_calib(struct motion_sensor_t *s, int enable)
 
 	/* Set the saved sensor configuration */
 	RETURN_ERROR(i2c_write_block(s->port, s->i2c_spi_addr_flags,
-			BMA4_ACCEL_CONFIG_ADDR, config, 2));
+				     BMA4_ACCEL_CONFIG_ADDR, config, 2));
 
 	RETURN_ERROR(bma4_write8(s, BMA4_POWER_CTRL_ADDR, pwr_ctrl));
 
@@ -236,7 +238,7 @@ static int perform_calib(struct motion_sensor_t *s, int enable)
 
 static int set_range(struct motion_sensor_t *s, int range, int round)
 {
-	int ret,  range_reg_val;
+	int ret, range_reg_val;
 
 	range_reg_val = BMA4_RANGE_TO_REG(range);
 
@@ -366,8 +368,8 @@ static int read(const struct motion_sensor_t *s, intv3_t v)
 	mutex_lock(s->mutex);
 
 	/* Read 6 bytes starting at X_AXIS_LSB. */
-	ret = i2c_read_block(s->port, s->i2c_spi_addr_flags,
-			     BMA4_DATA_8_ADDR, acc, 6);
+	ret = i2c_read_block(s->port, s->i2c_spi_addr_flags, BMA4_DATA_8_ADDR,
+			     acc, 6);
 
 	mutex_unlock(s->mutex);
 
diff --git a/driver/accel_bma4xx.h b/driver/accel_bma4xx.h
index 13c9da4a92..ad3dd711e5 100644
--- a/driver/accel_bma4xx.h
+++ b/driver/accel_bma4xx.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,158 +8,158 @@
 #ifndef __CROS_EC_ACCEL_BMA4XX_H
 #define __CROS_EC_ACCEL_BMA4XX_H
 
-#define BMA4_I2C_ADDR_PRIMARY			0x18
-#define BMA4_I2C_ADDR_SECONDARY			0x19
-#define BMA4_I2C_BMM150_ADDR			0x10
+#define BMA4_I2C_ADDR_PRIMARY 0x18
+#define BMA4_I2C_ADDR_SECONDARY 0x19
+#define BMA4_I2C_BMM150_ADDR 0x10
 
 /* Chip-specific registers */
-#define BMA4_CHIP_ID_ADDR			0x00
-#define BMA4_CHIP_ID_MIN			0x10
-#define BMA4_CHIP_ID_MAX			0x15
-
-#define BMA4_ERROR_ADDR				0x02
-#define BMA4_FATAL_ERR_MSK			0x01
-#define BMA4_CMD_ERR_POS			1
-#define BMA4_CMD_ERR_MSK			0x02
-#define BMA4_ERR_CODE_POS			2
-#define BMA4_ERR_CODE_MSK			0x1C
-#define BMA4_FIFO_ERR_POS			6
-#define BMA4_FIFO_ERR_MSK			0x40
-#define BMA4_AUX_ERR_POS			7
-#define BMA4_AUX_ERR_MSK			0x80
-
-#define BMA4_STATUS_ADDR			0x03
-#define BMA4_STAT_DATA_RDY_ACCEL_POS		7
-#define BMA4_STAT_DATA_RDY_ACCEL_MSK		0x80
-
-#define BMA4_DATA_0_ADDR			0x0A
-#define BMA4_DATA_8_ADDR			0x12
-
-#define BMA4_SENSORTIME_0_ADDR			0x18
-#define BMA4_INT_STAT_0_ADDR			0x1C
-#define BMA4_INT_STAT_1_ADDR			0x1D
-#define BMA4_STEP_CNT_OUT_0_ADDR		0x1E
-#define BMA4_HIGH_G_OUT_ADDR			0x1F
-#define BMA4_TEMPERATURE_ADDR			0x22
-
-#define BMA4_FIFO_LENGTH_0_ADDR			0x24
-#define BMA4_FIFO_DATA_ADDR			0x26
-#define BMA4_ACTIVITY_OUT_ADDR			0x27
-#define BMA4_ORIENTATION_OUT_ADDR		0x28
-
-#define BMA4_INTERNAL_STAT			0x2A
-#define BMA4_ASIC_INITIALIZED			0x01
-
-#define BMA4_ACCEL_CONFIG_ADDR			0x40
-#define BMA4_ACCEL_ODR_POS			0
-#define BMA4_ACCEL_ODR_MSK			0x0F
-#define BMA4_ACCEL_BW_POS			4
-#define BMA4_ACCEL_BW_MSK			0x70
-#define BMA4_ACCEL_PERFMODE_POS			7
-#define BMA4_ACCEL_PERFMODE_MSK			0x80
-#define BMA4_OUTPUT_DATA_RATE_0_78HZ		0x01
-#define BMA4_OUTPUT_DATA_RATE_1_56HZ		0x02
-#define BMA4_OUTPUT_DATA_RATE_3_12HZ		0x03
-#define BMA4_OUTPUT_DATA_RATE_6_25HZ		0x04
-#define BMA4_OUTPUT_DATA_RATE_12_5HZ		0x05
-#define BMA4_OUTPUT_DATA_RATE_25HZ		0x06
-#define BMA4_OUTPUT_DATA_RATE_50HZ		0x07
-#define BMA4_OUTPUT_DATA_RATE_100HZ		0x08
-#define BMA4_OUTPUT_DATA_RATE_200HZ		0x09
-#define BMA4_OUTPUT_DATA_RATE_400HZ		0x0A
-#define BMA4_OUTPUT_DATA_RATE_800HZ		0x0B
-#define BMA4_OUTPUT_DATA_RATE_1600HZ		0x0C
-#define BMA4_ACCEL_OSR4_AVG1			0
-#define BMA4_ACCEL_OSR2_AVG2			1
-#define BMA4_ACCEL_NORMAL_AVG4			2
-#define BMA4_ACCEL_CIC_AVG8			3
-#define BMA4_ACCEL_RES_AVG16			4
-#define BMA4_ACCEL_RES_AVG32			5
-#define BMA4_ACCEL_RES_AVG64			6
-#define BMA4_ACCEL_RES_AVG128			7
-#define BMA4_CIC_AVG_MODE			0
-#define BMA4_CONTINUOUS_MODE			1
-
-#define BMA4_ACCEL_RANGE_ADDR			0x41
-#define BMA4_ACCEL_RANGE_POS			0
-#define BMA4_ACCEL_RANGE_MSK			0x03
-#define BMA4_ACCEL_RANGE_2G			0
-#define BMA4_ACCEL_RANGE_4G			1
-#define BMA4_ACCEL_RANGE_8G			2
-#define BMA4_ACCEL_RANGE_16G			3
-
-#define BMA4_RESERVED_REG_5B_ADDR		0x5B
-#define BMA4_RESERVED_REG_5C_ADDR		0x5C
-#define BMA4_FEATURE_CONFIG_ADDR		0x5E
-#define BMA4_INTERNAL_ERROR			0x5F
-#define BMA4_IF_CONFIG_ADDR			0x6B
-#define BMA4_FOC_ACC_CONF_VAL			0xB7
-
-#define BMA4_NV_CONFIG_ADDR			0x70
-#define BMA4_NV_ACCEL_OFFSET_POS		3
-#define BMA4_NV_ACCEL_OFFSET_MSK		0x08
-
-#define BMA4_OFFSET_0_ADDR			0x71
-#define BMA4_OFFSET_1_ADDR			0x72
-#define BMA4_OFFSET_2_ADDR			0x73
-
-#define BMA4_POWER_CONF_ADDR			0x7C
-#define BMA4_ADVANCE_POWER_SAVE_POS		0
-#define BMA4_ADVANCE_POWER_SAVE_MSK		0x01
-
-#define BMA4_POWER_CTRL_ADDR			0x7D
-#define BMA4_ACCEL_ENABLE_POS			2
-#define BMA4_ACCEL_ENABLE_MSK			0x04
-#define BMA4_ENABLE				0x01
-#define BMA4_DISABLE				0x00
-
-#define BMA4_CMD_ADDR				0x7E
-#define BMA4_NVM_PROG				0xA0
-#define BMA4_FIFO_FLUSH				0xB0
-#define BMA4_SOFT_RESET				0xB6
+#define BMA4_CHIP_ID_ADDR 0x00
+#define BMA4_CHIP_ID_MIN 0x10
+#define BMA4_CHIP_ID_MAX 0x15
+
+#define BMA4_ERROR_ADDR 0x02
+#define BMA4_FATAL_ERR_MSK 0x01
+#define BMA4_CMD_ERR_POS 1
+#define BMA4_CMD_ERR_MSK 0x02
+#define BMA4_ERR_CODE_POS 2
+#define BMA4_ERR_CODE_MSK 0x1C
+#define BMA4_FIFO_ERR_POS 6
+#define BMA4_FIFO_ERR_MSK 0x40
+#define BMA4_AUX_ERR_POS 7
+#define BMA4_AUX_ERR_MSK 0x80
+
+#define BMA4_STATUS_ADDR 0x03
+#define BMA4_STAT_DATA_RDY_ACCEL_POS 7
+#define BMA4_STAT_DATA_RDY_ACCEL_MSK 0x80
+
+#define BMA4_DATA_0_ADDR 0x0A
+#define BMA4_DATA_8_ADDR 0x12
+
+#define BMA4_SENSORTIME_0_ADDR 0x18
+#define BMA4_INT_STAT_0_ADDR 0x1C
+#define BMA4_INT_STAT_1_ADDR 0x1D
+#define BMA4_STEP_CNT_OUT_0_ADDR 0x1E
+#define BMA4_HIGH_G_OUT_ADDR 0x1F
+#define BMA4_TEMPERATURE_ADDR 0x22
+
+#define BMA4_FIFO_LENGTH_0_ADDR 0x24
+#define BMA4_FIFO_DATA_ADDR 0x26
+#define BMA4_ACTIVITY_OUT_ADDR 0x27
+#define BMA4_ORIENTATION_OUT_ADDR 0x28
+
+#define BMA4_INTERNAL_STAT 0x2A
+#define BMA4_ASIC_INITIALIZED 0x01
+
+#define BMA4_ACCEL_CONFIG_ADDR 0x40
+#define BMA4_ACCEL_ODR_POS 0
+#define BMA4_ACCEL_ODR_MSK 0x0F
+#define BMA4_ACCEL_BW_POS 4
+#define BMA4_ACCEL_BW_MSK 0x70
+#define BMA4_ACCEL_PERFMODE_POS 7
+#define BMA4_ACCEL_PERFMODE_MSK 0x80
+#define BMA4_OUTPUT_DATA_RATE_0_78HZ 0x01
+#define BMA4_OUTPUT_DATA_RATE_1_56HZ 0x02
+#define BMA4_OUTPUT_DATA_RATE_3_12HZ 0x03
+#define BMA4_OUTPUT_DATA_RATE_6_25HZ 0x04
+#define BMA4_OUTPUT_DATA_RATE_12_5HZ 0x05
+#define BMA4_OUTPUT_DATA_RATE_25HZ 0x06
+#define BMA4_OUTPUT_DATA_RATE_50HZ 0x07
+#define BMA4_OUTPUT_DATA_RATE_100HZ 0x08
+#define BMA4_OUTPUT_DATA_RATE_200HZ 0x09
+#define BMA4_OUTPUT_DATA_RATE_400HZ 0x0A
+#define BMA4_OUTPUT_DATA_RATE_800HZ 0x0B
+#define BMA4_OUTPUT_DATA_RATE_1600HZ 0x0C
+#define BMA4_ACCEL_OSR4_AVG1 0
+#define BMA4_ACCEL_OSR2_AVG2 1
+#define BMA4_ACCEL_NORMAL_AVG4 2
+#define BMA4_ACCEL_CIC_AVG8 3
+#define BMA4_ACCEL_RES_AVG16 4
+#define BMA4_ACCEL_RES_AVG32 5
+#define BMA4_ACCEL_RES_AVG64 6
+#define BMA4_ACCEL_RES_AVG128 7
+#define BMA4_CIC_AVG_MODE 0
+#define BMA4_CONTINUOUS_MODE 1
+
+#define BMA4_ACCEL_RANGE_ADDR 0x41
+#define BMA4_ACCEL_RANGE_POS 0
+#define BMA4_ACCEL_RANGE_MSK 0x03
+#define BMA4_ACCEL_RANGE_2G 0
+#define BMA4_ACCEL_RANGE_4G 1
+#define BMA4_ACCEL_RANGE_8G 2
+#define BMA4_ACCEL_RANGE_16G 3
+
+#define BMA4_RESERVED_REG_5B_ADDR 0x5B
+#define BMA4_RESERVED_REG_5C_ADDR 0x5C
+#define BMA4_FEATURE_CONFIG_ADDR 0x5E
+#define BMA4_INTERNAL_ERROR 0x5F
+#define BMA4_IF_CONFIG_ADDR 0x6B
+#define BMA4_FOC_ACC_CONF_VAL 0xB7
+
+#define BMA4_NV_CONFIG_ADDR 0x70
+#define BMA4_NV_ACCEL_OFFSET_POS 3
+#define BMA4_NV_ACCEL_OFFSET_MSK 0x08
+
+#define BMA4_OFFSET_0_ADDR 0x71
+#define BMA4_OFFSET_1_ADDR 0x72
+#define BMA4_OFFSET_2_ADDR 0x73
+
+#define BMA4_POWER_CONF_ADDR 0x7C
+#define BMA4_ADVANCE_POWER_SAVE_POS 0
+#define BMA4_ADVANCE_POWER_SAVE_MSK 0x01
+
+#define BMA4_POWER_CTRL_ADDR 0x7D
+#define BMA4_ACCEL_ENABLE_POS 2
+#define BMA4_ACCEL_ENABLE_MSK 0x04
+#define BMA4_ENABLE 0x01
+#define BMA4_DISABLE 0x00
+
+#define BMA4_CMD_ADDR 0x7E
+#define BMA4_NVM_PROG 0xA0
+#define BMA4_FIFO_FLUSH 0xB0
+#define BMA4_SOFT_RESET 0xB6
 
 /* Other definitions */
-#define BMA4_X_AXIS				0
-#define BMA4_Y_AXIS				1
-#define BMA4_Z_AXIS				2
+#define BMA4_X_AXIS 0
+#define BMA4_Y_AXIS 1
+#define BMA4_Z_AXIS 2
 
-#define BMA4_12_BIT_RESOLUTION			12
-#define BMA4_14_BIT_RESOLUTION			14
-#define BMA4_16_BIT_RESOLUTION			16
+#define BMA4_12_BIT_RESOLUTION 12
+#define BMA4_14_BIT_RESOLUTION 14
+#define BMA4_16_BIT_RESOLUTION 16
 
 /*
  * The max positive value of accel data is 0x07FF, equal to range(g)
  * So, in order to get +1g, divide the 0x07FF by range
  */
-#define BMA4_ACC_DATA_PLUS_1G(range)		(0x07FF / (range))
+#define BMA4_ACC_DATA_PLUS_1G(range) (0x07FF / (range))
 
 /* For offset registers 1LSB - 3.9mg */
-#define BMA4_OFFSET_ACC_MULTI_MG		(3900 * 1000)
-#define BMA4_OFFSET_ACC_DIV_MG			1000000
+#define BMA4_OFFSET_ACC_MULTI_MG (3900 * 1000)
+#define BMA4_OFFSET_ACC_DIV_MG 1000000
 
-#define BMA4_FOC_SAMPLE_LIMIT			32
+#define BMA4_FOC_SAMPLE_LIMIT 32
 
 /* Min and Max sampling frequency in mHz */
-#define BMA4_ACCEL_MIN_FREQ	12500
-#define BMA4_ACCEL_MAX_FREQ	MOTION_MAX_SENSOR_FREQUENCY(1600000, 6250)
+#define BMA4_ACCEL_MIN_FREQ 12500
+#define BMA4_ACCEL_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(1600000, 6250)
 
-#define BMA4_RANGE_TO_REG(_range) \
+#define BMA4_RANGE_TO_REG(_range)                              \
 	((_range) < 8 ? BMA4_ACCEL_RANGE_2G + ((_range) / 4) : \
 			BMA4_ACCEL_RANGE_8G + ((_range) / 16))
 
-#define BMA4_REG_TO_RANGE(_reg) \
-	((_reg) < BMA4_ACCEL_RANGE_8G ? 2 + (_reg) * 2 : \
-					8 + ((_reg) - BMA4_ACCEL_RANGE_8G) * 8)
+#define BMA4_REG_TO_RANGE(_reg)                        \
+	((_reg) < BMA4_ACCEL_RANGE_8G ? 2 + (_reg)*2 : \
+					8 + ((_reg)-BMA4_ACCEL_RANGE_8G) * 8)
 
-#define BMA4_ODR_TO_REG(_odr) \
-	((_odr) < 125000 ? \
-	 BMA4_OUTPUT_DATA_RATE_0_78HZ + __fls(((_odr) * 10) / 7800) : \
-	 BMA4_OUTPUT_DATA_RATE_25HZ + __fls((_odr) / 25000))
+#define BMA4_ODR_TO_REG(_odr)                                               \
+	((_odr) < 125000 ?                                                  \
+		 BMA4_OUTPUT_DATA_RATE_0_78HZ + __fls(((_odr)*10) / 7800) : \
+		 BMA4_OUTPUT_DATA_RATE_25HZ + __fls((_odr) / 25000))
 
-#define  BMA4_REG_TO_ODR(_reg) \
-	((_reg) < BMA4_OUTPUT_DATA_RATE_25HZ ? \
-	 (7800 << ((_reg) - BMA4_OUTPUT_DATA_RATE_0_78HZ)) / 10 : \
-	 25000 << ((_reg) - BMA4_OUTPUT_DATA_RATE_25HZ))
+#define BMA4_REG_TO_ODR(_reg)                                           \
+	((_reg) < BMA4_OUTPUT_DATA_RATE_25HZ ?                          \
+		 (7800 << ((_reg)-BMA4_OUTPUT_DATA_RATE_0_78HZ)) / 10 : \
+		 25000 << ((_reg)-BMA4_OUTPUT_DATA_RATE_25HZ))
 
 extern const struct accelgyro_drv bma4_accel_drv;
 
diff --git a/driver/accel_kionix.c b/driver/accel_kionix.c
index 3b75e33e0b..cc12987f40 100644
--- a/driver/accel_kionix.c
+++ b/driver/accel_kionix.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,7 +23,7 @@
 #include "util.h"
 
 #define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
 
 /* Number of times to attempt to enable sensor before giving up. */
 #define SENSOR_ENABLE_ATTEMPTS 3
@@ -46,32 +46,28 @@
 #define T(s_) V(s_)
 #endif /* !defined(CONFIG_ACCEL_KXCJ9) || !defined(CONFIG_ACCEL_KX022) */
 
-STATIC_IF(CONFIG_KX022_ORIENTATION_SENSOR) int check_orientation_locked(
-					const struct motion_sensor_t *s);
+STATIC_IF(CONFIG_KX022_ORIENTATION_SENSOR)
+int check_orientation_locked(const struct motion_sensor_t *s);
 
 /* List of range values in +/-G's and their associated register values. */
 static const struct accel_param_pair ranges[][3] = {
 #ifdef CONFIG_ACCEL_KX022
-	{ {2, KX022_GSEL_2G},
-	  {4, KX022_GSEL_4G},
-	  {8, KX022_GSEL_8G} },
+	{ { 2, KX022_GSEL_2G }, { 4, KX022_GSEL_4G }, { 8, KX022_GSEL_8G } },
 #endif /* defined(CONFIG_ACCEL_KX022) */
 #ifdef CONFIG_ACCEL_KXCJ9
-	{ {2, KXCJ9_GSEL_2G},
-	  {4, KXCJ9_GSEL_4G},
-	  {8, KXCJ9_GSEL_8G_14BIT} },
+	{ { 2, KXCJ9_GSEL_2G },
+	  { 4, KXCJ9_GSEL_4G },
+	  { 8, KXCJ9_GSEL_8G_14BIT } },
 #endif /* defined(CONFIG_ACCEL_KXCJ9) */
 };
 
 /* List of resolution values in bits and their associated register values. */
 static const struct accel_param_pair resolutions[][2] = {
 #ifdef CONFIG_ACCEL_KX022
-	{ {8,  KX022_RES_8BIT},
-	  {16, KX022_RES_16BIT} },
+	{ { 8, KX022_RES_8BIT }, { 16, KX022_RES_16BIT } },
 #endif /* defined(CONFIG_ACCEL_KX022) */
 #ifdef CONFIG_ACCEL_KXCJ9
-	{ {8,  KXCJ9_RES_8BIT},
-	  {12, KXCJ9_RES_12BIT} },
+	{ { 8, KXCJ9_RES_8BIT }, { 12, KXCJ9_RES_12BIT } },
 #endif /* defined(CONFIG_ACCEL_KXCJ9) */
 };
 
@@ -79,34 +75,34 @@ static const struct accel_param_pair resolutions[][2] = {
 static const struct accel_param_pair datarates[][13] = {
 #ifdef CONFIG_ACCEL_KX022
 	/* One duplicate because table sizes must match. */
-	{ {781,     KX022_OSA_0_781HZ},
-	  {781,     KX022_OSA_0_781HZ},
-	  {1563,    KX022_OSA_1_563HZ},
-	  {3125,    KX022_OSA_3_125HZ},
-	  {6250,    KX022_OSA_6_250HZ},
-	  {12500,   KX022_OSA_12_50HZ},
-	  {25000,   KX022_OSA_25_00HZ},
-	  {50000,   KX022_OSA_50_00HZ},
-	  {100000,  KX022_OSA_100_0HZ},
-	  {200000,  KX022_OSA_200_0HZ},
-	  {400000,  KX022_OSA_400_0HZ},
-	  {800000,  KX022_OSA_800_0HZ},
-	  {1600000, KX022_OSA_1600HZ} },
+	{ { 781, KX022_OSA_0_781HZ },
+	  { 781, KX022_OSA_0_781HZ },
+	  { 1563, KX022_OSA_1_563HZ },
+	  { 3125, KX022_OSA_3_125HZ },
+	  { 6250, KX022_OSA_6_250HZ },
+	  { 12500, KX022_OSA_12_50HZ },
+	  { 25000, KX022_OSA_25_00HZ },
+	  { 50000, KX022_OSA_50_00HZ },
+	  { 100000, KX022_OSA_100_0HZ },
+	  { 200000, KX022_OSA_200_0HZ },
+	  { 400000, KX022_OSA_400_0HZ },
+	  { 800000, KX022_OSA_800_0HZ },
+	  { 1600000, KX022_OSA_1600HZ } },
 #endif /* defined(CONFIG_ACCEL_KX022) */
 #ifdef CONFIG_ACCEL_KXCJ9
-	{ {0,       KXCJ9_OSA_0_000HZ},
-	  {781,     KXCJ9_OSA_0_781HZ},
-	  {1563,    KXCJ9_OSA_1_563HZ},
-	  {3125,    KXCJ9_OSA_3_125HZ},
-	  {6250,    KXCJ9_OSA_6_250HZ},
-	  {12500,   KXCJ9_OSA_12_50HZ},
-	  {25000,   KXCJ9_OSA_25_00HZ},
-	  {50000,   KXCJ9_OSA_50_00HZ},
-	  {100000,  KXCJ9_OSA_100_0HZ},
-	  {200000,  KXCJ9_OSA_200_0HZ},
-	  {400000,  KXCJ9_OSA_400_0HZ},
-	  {800000,  KXCJ9_OSA_800_0HZ},
-	  {1600000, KXCJ9_OSA_1600_HZ} },
+	{ { 0, KXCJ9_OSA_0_000HZ },
+	  { 781, KXCJ9_OSA_0_781HZ },
+	  { 1563, KXCJ9_OSA_1_563HZ },
+	  { 3125, KXCJ9_OSA_3_125HZ },
+	  { 6250, KXCJ9_OSA_6_250HZ },
+	  { 12500, KXCJ9_OSA_12_50HZ },
+	  { 25000, KXCJ9_OSA_25_00HZ },
+	  { 50000, KXCJ9_OSA_50_00HZ },
+	  { 100000, KXCJ9_OSA_100_0HZ },
+	  { 200000, KXCJ9_OSA_200_0HZ },
+	  { 400000, KXCJ9_OSA_400_0HZ },
+	  { 800000, KXCJ9_OSA_800_0HZ },
+	  { 1600000, KXCJ9_OSA_1600_HZ } },
 #endif /* defined(CONFIG_ACCEL_KXCJ9) */
 };
 
@@ -127,7 +123,7 @@ static int find_param_index(const int eng_val, const int round_up,
 		if (eng_val <= pairs[i].val)
 			return i;
 
-		if (eng_val < pairs[i+1].val) {
+		if (eng_val < pairs[i + 1].val) {
 			if (round_up)
 				return i + 1;
 			else
@@ -141,8 +137,7 @@ static int find_param_index(const int eng_val, const int round_up,
 /**
  * Read register from accelerometer.
  */
-static int raw_read8(const int port,
-		     const uint16_t i2c_spi_addr_flags,
+static int raw_read8(const int port, const uint16_t i2c_spi_addr_flags,
 		     const int reg, int *data_ptr)
 {
 	int rv = EC_ERROR_INVAL;
@@ -160,8 +155,7 @@ static int raw_read8(const int port,
 
 #endif
 	} else {
-		rv = i2c_read8(port, i2c_spi_addr_flags,
-			       reg, data_ptr);
+		rv = i2c_read8(port, i2c_spi_addr_flags, reg, data_ptr);
 	}
 	return rv;
 }
@@ -169,8 +163,7 @@ static int raw_read8(const int port,
 /**
  * Write register from accelerometer.
  */
-static int raw_write8(const int port,
-		      const uint16_t i2c_spi_addr_flags,
+static int raw_write8(const int port, const uint16_t i2c_spi_addr_flags,
 		      const int reg, int data)
 {
 	int rv = EC_ERROR_INVAL;
@@ -184,14 +177,12 @@ static int raw_write8(const int port,
 			cmd, 2, NULL, 0);
 #endif
 	} else {
-		rv = i2c_write8(port, i2c_spi_addr_flags,
-				reg, data);
+		rv = i2c_write8(port, i2c_spi_addr_flags, reg, data);
 	}
 	return rv;
 }
 
-static int raw_read_multi(const int port,
-			  const uint16_t i2c_spi_addr_flags,
+static int raw_read_multi(const int port, const uint16_t i2c_spi_addr_flags,
 			  uint8_t reg, uint8_t *rxdata, int rxlen)
 {
 	int rv = EC_ERROR_INVAL;
@@ -204,8 +195,8 @@ static int raw_read_multi(const int port,
 			&reg, 1, rxdata, rxlen);
 #endif
 	} else {
-		rv = i2c_read_block(port, i2c_spi_addr_flags,
-				    reg, rxdata, rxlen);
+		rv = i2c_read_block(port, i2c_spi_addr_flags, reg, rxdata,
+				    rxlen);
 	}
 	return rv;
 }
@@ -233,15 +224,13 @@ static int disable_sensor(const struct motion_sensor_t *s, int *reg_val)
 	 * so that we can restore it later.
 	 */
 	for (i = 0; i < SENSOR_ENABLE_ATTEMPTS; i++) {
-		ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-				reg, reg_val);
+		ret = raw_read8(s->port, s->i2c_spi_addr_flags, reg, reg_val);
 		if (ret != EC_SUCCESS)
 			continue;
 
 		*reg_val &= ~pc1_field;
 
-		ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-				 reg, *reg_val);
+		ret = raw_write8(s->port, s->i2c_spi_addr_flags, reg, *reg_val);
 		if (ret == EC_SUCCESS)
 			return EC_SUCCESS;
 	}
@@ -266,20 +255,18 @@ static int enable_sensor(const struct motion_sensor_t *s, int reg_val)
 	pc1_field = KIONIX_PC1_FIELD(V(s));
 
 	for (i = 0; i < SENSOR_ENABLE_ATTEMPTS; i++) {
-		ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-				reg, &reg_val);
+		ret = raw_read8(s->port, s->i2c_spi_addr_flags, reg, &reg_val);
 		if (ret != EC_SUCCESS)
 			continue;
 
 		/* Enable tilt orientation mode  if lid sensor */
 		if (IS_ENABLED(CONFIG_KX022_ORIENTATION_SENSOR) &&
-		    (s->location == MOTIONSENSE_LOC_LID) &&
-		    (V(s) == 0))
+		    (s->location == MOTIONSENSE_LOC_LID) && (V(s) == 0))
 			reg_val |= KX022_CNTL1_TPE;
 
 		/* Enable accelerometer based on reg_val value. */
-		ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-				 reg, reg_val | pc1_field);
+		ret = raw_write8(s->port, s->i2c_spi_addr_flags, reg,
+				 reg_val | pc1_field);
 
 		/* On first success, we are done. */
 		if (ret == EC_SUCCESS)
@@ -313,8 +300,7 @@ static int set_value(const struct motion_sensor_t *s, int reg, int val,
 
 	/* Determine new value of control reg and attempt to write it. */
 	reg_val_new = (reg_val & ~field) | val;
-	ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-			 reg, reg_val_new);
+	ret = raw_write8(s->port, s->i2c_spi_addr_flags, reg, reg_val_new);
 
 	/* If successfully written, then save the range. */
 	if (ret == EC_SUCCESS)
@@ -381,7 +367,7 @@ static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
 
 	ret = set_value(s, reg, odr_val, odr_field);
 	if (ret == EC_SUCCESS)
-		data->base.odr =  datarates[T(s)][index].val;
+		data->base.odr = datarates[T(s)][index].val;
 	return ret;
 }
 
@@ -414,9 +400,8 @@ static int get_offset(const struct motion_sensor_t *s, int16_t *offset,
 	return EC_SUCCESS;
 }
 
-static __maybe_unused enum motionsensor_orientation kx022_convert_orientation(
-		const struct motion_sensor_t *s,
-		int orientation)
+static __maybe_unused enum motionsensor_orientation
+kx022_convert_orientation(const struct motion_sensor_t *s, int orientation)
 {
 	enum motionsensor_orientation res = MOTIONSENSE_ORIENTATION_UNKNOWN;
 
@@ -447,8 +432,8 @@ static int check_orientation_locked(const struct motion_sensor_t *s)
 	int orientation, raw_orientation;
 	int ret;
 
-	ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-			KX022_TSCP, &raw_orientation);
+	ret = raw_read8(s->port, s->i2c_spi_addr_flags, KX022_TSCP,
+			&raw_orientation);
 	if (ret != EC_SUCCESS)
 		return ret;
 
@@ -465,11 +450,11 @@ static int check_orientation_locked(const struct motion_sensor_t *s)
 bool motion_orientation_changed(const struct motion_sensor_t *s)
 {
 	return ((struct kionix_accel_data *)s->drv_data)->orientation !=
-		((struct kionix_accel_data *)s->drv_data)->last_orientation;
+	       ((struct kionix_accel_data *)s->drv_data)->last_orientation;
 }
 
-enum motionsensor_orientation *motion_orientation_ptr(
-		const struct motion_sensor_t *s)
+enum motionsensor_orientation *
+motion_orientation_ptr(const struct motion_sensor_t *s)
 {
 	return &((struct kionix_accel_data *)s->drv_data)->orientation;
 }
@@ -494,8 +479,7 @@ static int read(const struct motion_sensor_t *s, intv3_t v)
 	mutex_lock(s->mutex);
 	ret = raw_read_multi(s->port, s->i2c_spi_addr_flags, reg, acc, 6);
 	if (IS_ENABLED(CONFIG_KX022_ORIENTATION_SENSOR) &&
-	    (s->location == MOTIONSENSE_LOC_LID) &&
-	    (V(s) == 0) &&
+	    (s->location == MOTIONSENSE_LOC_LID) && (V(s) == 0) &&
 	    (ret == EC_SUCCESS))
 		ret = check_orientation_locked(s);
 	mutex_unlock(s->mutex);
@@ -520,7 +504,7 @@ static int read(const struct motion_sensor_t *s, intv3_t v)
 	for (i = X; i <= Z; i++) {
 		if (V(s)) {
 			v[i] = (((int8_t)acc[i * 2 + 1]) << 4) |
-				(acc[i * 2] >> 4);
+			       (acc[i * 2] >> 4);
 			v[i] <<= 16 - resolution;
 		} else {
 			if (resolution == 8)
@@ -550,8 +534,8 @@ static int init(struct motion_sensor_t *s)
 		do {
 			msleep(1);
 			/* Read WHO_AM_I to be sure the device has booted */
-			ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-					reg, &val);
+			ret = raw_read8(s->port, s->i2c_spi_addr_flags, reg,
+					&val);
 			if (ret == EC_SUCCESS)
 				break;
 
@@ -564,8 +548,7 @@ static int init(struct motion_sensor_t *s)
 	} else {
 		/* Write 0x00 to the internal register for KX022 */
 		reg = KX022_INTERNAL;
-		ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-				 reg, 0x0);
+		ret = raw_write8(s->port, s->i2c_spi_addr_flags, reg, 0x0);
 		if (ret != EC_SUCCESS) {
 			/*
 			 * For I2C communication, if ACK was not received
@@ -574,11 +557,9 @@ static int init(struct motion_sensor_t *s)
 			 */
 			if (!ACCEL_ADDR_IS_SPI(s->i2c_spi_addr_flags)) {
 				const uint16_t i2c_alt_addr_flags =
-					I2C_STRIP_FLAGS(
-						s->i2c_spi_addr_flags)
-					& ~2;
-				ret = raw_write8(s->port,
-						 i2c_alt_addr_flags,
+					I2C_STRIP_FLAGS(s->i2c_spi_addr_flags) &
+					~2;
+				ret = raw_write8(s->port, i2c_alt_addr_flags,
 						 reg, 0x0);
 			}
 		}
@@ -620,8 +601,8 @@ static int init(struct motion_sensor_t *s)
 		do {
 			msleep(1);
 
-			ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-					reg, &val);
+			ret = raw_read8(s->port, s->i2c_spi_addr_flags, reg,
+					&val);
 			/* Reset complete. */
 			if ((ret == EC_SUCCESS) && !(val & reset_field))
 				break;
@@ -672,9 +653,7 @@ static int probe(const struct motion_sensor_t *s)
 {
 	int val;
 
-	if (i2c_read8(s->port,
-		      s->i2c_spi_addr_flags,
-		      KIONIX_WHO_AM_I(V(s)),
+	if (i2c_read8(s->port, s->i2c_spi_addr_flags, KIONIX_WHO_AM_I(V(s)),
 		      &val) != EC_SUCCESS)
 		return EC_ERROR_HW_INTERNAL;
 
diff --git a/driver/accel_kionix.h b/driver/accel_kionix.h
index 5ec83411e9..8777396e01 100644
--- a/driver/accel_kionix.h
+++ b/driver/accel_kionix.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -47,30 +47,26 @@ extern const struct accelgyro_drv kionix_accel_drv;
  * |    SPI device ID              | 1 |
  * +-------------------------------+---+
  */
-#define KIONIX_CTRL1_REG(v) (KX022_CNTL1 +	\
-			     (v) * (KXCJ9_CTRL1 - KX022_CNTL1))
-#define KIONIX_CTRL2_REG(v) (KX022_CNTL2 +	\
-			     (v) * (KXCJ9_CTRL2 - KX022_CNTL2))
-#define KIONIX_ODR_REG(v) (KX022_ODCNTL +	\
-			   (v) * (KXCJ9_DATA_CTRL - KX022_ODCNTL))
-#define KIONIX_ODR_FIELD(v) (KX022_OSA_FIELD +		\
-			     (v) * (KXCJ9_OSA_FIELD - KX022_OSA_FIELD))
-#define KIONIX_PC1_FIELD(v) (KX022_CNTL1_PC1 +		\
-			     (v) * (KXCJ9_CTRL1_PC1 - KX022_CNTL1_PC1))
-#define KIONIX_RANGE_FIELD(v) (KX022_GSEL_FIELD +	\
-			       (v) * (KXCJ9_GSEL_ALL - KX022_GSEL_FIELD))
-#define KIONIX_RES_FIELD(v) (KX022_RES_16BIT +		\
-			     (v) * (KXCJ9_RES_12BIT - KX022_RES_16BIT))
-#define KIONIX_RESET_FIELD(v) (KX022_CNTL2_SRST +	\
-			       (v) * (KXCJ9_CTRL2_SRST - KX022_CNTL2_SRST))
-#define KIONIX_XOUT_L(v) (KX022_XOUT_L +	\
-			  (v) * (KXCJ9_XOUT_L - KX022_XOUT_L))
+#define KIONIX_CTRL1_REG(v) (KX022_CNTL1 + (v) * (KXCJ9_CTRL1 - KX022_CNTL1))
+#define KIONIX_CTRL2_REG(v) (KX022_CNTL2 + (v) * (KXCJ9_CTRL2 - KX022_CNTL2))
+#define KIONIX_ODR_REG(v) \
+	(KX022_ODCNTL + (v) * (KXCJ9_DATA_CTRL - KX022_ODCNTL))
+#define KIONIX_ODR_FIELD(v) \
+	(KX022_OSA_FIELD + (v) * (KXCJ9_OSA_FIELD - KX022_OSA_FIELD))
+#define KIONIX_PC1_FIELD(v) \
+	(KX022_CNTL1_PC1 + (v) * (KXCJ9_CTRL1_PC1 - KX022_CNTL1_PC1))
+#define KIONIX_RANGE_FIELD(v) \
+	(KX022_GSEL_FIELD + (v) * (KXCJ9_GSEL_ALL - KX022_GSEL_FIELD))
+#define KIONIX_RES_FIELD(v) \
+	(KX022_RES_16BIT + (v) * (KXCJ9_RES_12BIT - KX022_RES_16BIT))
+#define KIONIX_RESET_FIELD(v) \
+	(KX022_CNTL2_SRST + (v) * (KXCJ9_CTRL2_SRST - KX022_CNTL2_SRST))
+#define KIONIX_XOUT_L(v) (KX022_XOUT_L + (v) * (KXCJ9_XOUT_L - KX022_XOUT_L))
 
-#define KIONIX_WHO_AM_I(v) (KX022_WHOAMI + \
-			    (v) * (KXCJ9_WHOAMI - KX022_WHOAMI))
+#define KIONIX_WHO_AM_I(v) (KX022_WHOAMI + (v) * (KXCJ9_WHOAMI - KX022_WHOAMI))
 
-#define KIONIX_WHO_AM_I_VAL(v) (KX022_WHO_AM_I_VAL + \
-			(v) * (KXCJ9_WHO_AM_I_VAL - KX022_WHO_AM_I_VAL))
+#define KIONIX_WHO_AM_I_VAL(v) \
+	(KX022_WHO_AM_I_VAL + (v) * (KXCJ9_WHO_AM_I_VAL - KX022_WHO_AM_I_VAL))
 
 #ifdef CONFIG_CMD_I2C_STRESS_TEST_ACCEL
 extern struct i2c_stress_test_dev kionix_i2c_stress_test_dev;
diff --git a/driver/accel_kx022.h b/driver/accel_kx022.h
index a806568c59..089270aca4 100644
--- a/driver/accel_kx022.h
+++ b/driver/accel_kx022.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,130 +12,128 @@
  * 7-bit address is 001111Xb. Where 'X' is determined
  * by the voltage on the ADDR pin.
  */
-#define KX022_ADDR0_FLAGS	0x1e
-#define KX022_ADDR1_FLAGS	0x1f
-#define KX022_WHO_AM_I_VAL	0x14
+#define KX022_ADDR0_FLAGS 0x1e
+#define KX022_ADDR1_FLAGS 0x1f
+#define KX022_WHO_AM_I_VAL 0x14
 
 /* Chip-specific registers */
-#define KX022_XHP_L		0x00
-#define KX022_XHP_H		0x01
-#define KX022_YHP_L		0x02
-#define KX022_YHP_H		0x03
-#define KX022_ZHP_L		0x04
-#define KX022_ZHP_H		0x05
-#define KX022_XOUT_L		0x06
-#define KX022_XOUT_H		0x07
-#define KX022_YOUT_L		0x08
-#define KX022_YOUT_H		0x09
-#define KX022_ZOUT_L		0x0a
-#define KX022_ZOUT_H		0x0b
-#define KX022_COTR		0x0c
-#define KX022_COTR_VAL_COTC	0xAA
-#define KX022_COTR_VAL_DEFAULT	0x55
-#define KX022_WHOAMI		0x0f
-#define KX022_TSCP		0x10
-#define KX022_TSPP		0x11
-#define KX022_INS1		0x12
-#define KX022_INS2		0x13
-#define KX022_INS3		0x14
-#define KX022_STATUS_REG	0x15
-#define KX022_INT_REL		0x17
-#define KX022_CNTL1		0x18
-#define KX022_CNTL2		0x19
-#define KX022_CNTL3		0x1a
-#define KX022_ODCNTL		0x1b
-#define KX022_INC1		0x1c
-#define KX022_INC2		0x1d
-#define KX022_INC3		0x1e
-#define KX022_INC4		0x1f
-#define KX022_INC5		0x20
-#define KX022_INC6		0x21
-#define KX022_TILT_TIMER	0x22
-#define KX022_WUFC		0x23
-#define KX022_TDTRC		0x24
-#define KX022_TDTC		0x25
-#define KX022_TTH		0x26
-#define KX022_TTL		0x27
-#define KX022_FTD		0x28
-#define KX022_STD		0x29
-#define KX022_TLT		0x2a
-#define KX022_TWS		0x2b
-#define KX022_ATH		0x30
-#define KX022_TILT_ANGLE_LL	0x32
-#define KX022_TILT_ANGLE_HL	0x33
-#define KX022_HYST_SET		0x34
-#define KX022_LP_CNTL		0x35
-#define KX022_BUF_CNTL1	0x3a
-#define KX022_BUF_CNTL2	0x3b
-#define KX022_BUF_STATUS_1	0x3c
-#define KX022_BUF_STATUS_2	0x3d
-#define KX022_BUF_CLEAR	0x3e
-#define KX022_BUF_READ		0x3f
-#define KX022_SELF_TEST	0x60
-#define KX022_INTERNAL		0x7f
-
-
-#define KX022_CNTL1_PC1		BIT(7)
-#define KX022_CNTL1_WUFE	BIT(1)
-#define KX022_CNTL1_TPE		BIT(0)
+#define KX022_XHP_L 0x00
+#define KX022_XHP_H 0x01
+#define KX022_YHP_L 0x02
+#define KX022_YHP_H 0x03
+#define KX022_ZHP_L 0x04
+#define KX022_ZHP_H 0x05
+#define KX022_XOUT_L 0x06
+#define KX022_XOUT_H 0x07
+#define KX022_YOUT_L 0x08
+#define KX022_YOUT_H 0x09
+#define KX022_ZOUT_L 0x0a
+#define KX022_ZOUT_H 0x0b
+#define KX022_COTR 0x0c
+#define KX022_COTR_VAL_COTC 0xAA
+#define KX022_COTR_VAL_DEFAULT 0x55
+#define KX022_WHOAMI 0x0f
+#define KX022_TSCP 0x10
+#define KX022_TSPP 0x11
+#define KX022_INS1 0x12
+#define KX022_INS2 0x13
+#define KX022_INS3 0x14
+#define KX022_STATUS_REG 0x15
+#define KX022_INT_REL 0x17
+#define KX022_CNTL1 0x18
+#define KX022_CNTL2 0x19
+#define KX022_CNTL3 0x1a
+#define KX022_ODCNTL 0x1b
+#define KX022_INC1 0x1c
+#define KX022_INC2 0x1d
+#define KX022_INC3 0x1e
+#define KX022_INC4 0x1f
+#define KX022_INC5 0x20
+#define KX022_INC6 0x21
+#define KX022_TILT_TIMER 0x22
+#define KX022_WUFC 0x23
+#define KX022_TDTRC 0x24
+#define KX022_TDTC 0x25
+#define KX022_TTH 0x26
+#define KX022_TTL 0x27
+#define KX022_FTD 0x28
+#define KX022_STD 0x29
+#define KX022_TLT 0x2a
+#define KX022_TWS 0x2b
+#define KX022_ATH 0x30
+#define KX022_TILT_ANGLE_LL 0x32
+#define KX022_TILT_ANGLE_HL 0x33
+#define KX022_HYST_SET 0x34
+#define KX022_LP_CNTL 0x35
+#define KX022_BUF_CNTL1 0x3a
+#define KX022_BUF_CNTL2 0x3b
+#define KX022_BUF_STATUS_1 0x3c
+#define KX022_BUF_STATUS_2 0x3d
+#define KX022_BUF_CLEAR 0x3e
+#define KX022_BUF_READ 0x3f
+#define KX022_SELF_TEST 0x60
+#define KX022_INTERNAL 0x7f
+
+#define KX022_CNTL1_PC1 BIT(7)
+#define KX022_CNTL1_WUFE BIT(1)
+#define KX022_CNTL1_TPE BIT(0)
 
 /* TSCP orientations */
-#define KX022_ORIENT_PORTRAIT		BIT(2)
-#define KX022_ORIENT_INVERT_PORTRAIT	BIT(3)
-#define KX022_ORIENT_LANDSCAPE		BIT(4)
-#define KX022_ORIENT_INVERT_LANDSCAPE	BIT(5)
-#define KX022_ORIENT_MASK		(KX022_ORIENT_PORTRAIT | \
-					 KX022_ORIENT_INVERT_PORTRAIT | \
-					 KX022_ORIENT_LANDSCAPE | \
-					 KX022_ORIENT_INVERT_LANDSCAPE)
-
-#define KX022_CNTL2_SRST	BIT(7)
-
-#define KX022_CNTL3_OWUF_FIELD	7
-
-#define KX022_INC1_IEA		BIT(4)
-#define KX022_INC1_IEN		BIT(5)
-
-#define KX022_GSEL_2G		(0 << 3)
-#define KX022_GSEL_4G		BIT(3)
-#define KX022_GSEL_8G		(2 << 3)
-#define KX022_GSEL_FIELD	(3 << 3)
-
-#define KX022_RES_8BIT		(0 << 6)
-#define KX022_RES_16BIT		BIT(6)
-
-#define KX022_OSA_0_781HZ	8
-#define KX022_OSA_1_563HZ	9
-#define KX022_OSA_3_125HZ	0xa
-#define KX022_OSA_6_250HZ	0xb
-#define KX022_OSA_12_50HZ	0
-#define KX022_OSA_25_00HZ	1
-#define KX022_OSA_50_00HZ	2
-#define KX022_OSA_100_0HZ	3
-#define KX022_OSA_200_0HZ	4
-#define KX022_OSA_400_0HZ	5
-#define KX022_OSA_800_0HZ	6
-#define KX022_OSA_1600HZ	7
-#define KX022_OSA_FIELD		0xf
-
-#define KX022_OWUF_0_781HZ	0
-#define KX022_OWUF_1_563HZ	1
-#define KX022_OWUF_3_125HZ	2
-#define KX022_OWUF_6_250HZ	3
-#define KX022_OWUF_12_50HZ	4
-#define KX022_OWUF_25_00HZ	5
-#define KX022_OWUF_50_00HZ	6
-#define KX022_OWUF_100_0HZ	7
-
-#define KX022_INC2_ZPWUE	BIT(0)
-#define KX022_INC2_ZNWUE	BIT(1)
-#define KX022_INC2_YPWUE	BIT(2)
-#define KX022_INC2_YNWUE	BIT(3)
-#define KX022_INC2_XPWUE	BIT(4)
-#define KX022_INC2_XNWUE	BIT(5)
+#define KX022_ORIENT_PORTRAIT BIT(2)
+#define KX022_ORIENT_INVERT_PORTRAIT BIT(3)
+#define KX022_ORIENT_LANDSCAPE BIT(4)
+#define KX022_ORIENT_INVERT_LANDSCAPE BIT(5)
+#define KX022_ORIENT_MASK                                       \
+	(KX022_ORIENT_PORTRAIT | KX022_ORIENT_INVERT_PORTRAIT | \
+	 KX022_ORIENT_LANDSCAPE | KX022_ORIENT_INVERT_LANDSCAPE)
+
+#define KX022_CNTL2_SRST BIT(7)
+
+#define KX022_CNTL3_OWUF_FIELD 7
+
+#define KX022_INC1_IEA BIT(4)
+#define KX022_INC1_IEN BIT(5)
+
+#define KX022_GSEL_2G (0 << 3)
+#define KX022_GSEL_4G BIT(3)
+#define KX022_GSEL_8G (2 << 3)
+#define KX022_GSEL_FIELD (3 << 3)
+
+#define KX022_RES_8BIT (0 << 6)
+#define KX022_RES_16BIT BIT(6)
+
+#define KX022_OSA_0_781HZ 8
+#define KX022_OSA_1_563HZ 9
+#define KX022_OSA_3_125HZ 0xa
+#define KX022_OSA_6_250HZ 0xb
+#define KX022_OSA_12_50HZ 0
+#define KX022_OSA_25_00HZ 1
+#define KX022_OSA_50_00HZ 2
+#define KX022_OSA_100_0HZ 3
+#define KX022_OSA_200_0HZ 4
+#define KX022_OSA_400_0HZ 5
+#define KX022_OSA_800_0HZ 6
+#define KX022_OSA_1600HZ 7
+#define KX022_OSA_FIELD 0xf
+
+#define KX022_OWUF_0_781HZ 0
+#define KX022_OWUF_1_563HZ 1
+#define KX022_OWUF_3_125HZ 2
+#define KX022_OWUF_6_250HZ 3
+#define KX022_OWUF_12_50HZ 4
+#define KX022_OWUF_25_00HZ 5
+#define KX022_OWUF_50_00HZ 6
+#define KX022_OWUF_100_0HZ 7
+
+#define KX022_INC2_ZPWUE BIT(0)
+#define KX022_INC2_ZNWUE BIT(1)
+#define KX022_INC2_YPWUE BIT(2)
+#define KX022_INC2_YNWUE BIT(3)
+#define KX022_INC2_XPWUE BIT(4)
+#define KX022_INC2_XNWUE BIT(5)
 
 /* Min and Max sampling frequency in mHz */
-#define KX022_ACCEL_MIN_FREQ    12500
-#define KX022_ACCEL_MAX_FREQ    MOTION_MAX_SENSOR_FREQUENCY(1600000, 6250)
+#define KX022_ACCEL_MIN_FREQ 12500
+#define KX022_ACCEL_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(1600000, 6250)
 
 #endif /* __CROS_EC_ACCEL_KX022_H */
diff --git a/driver/accel_kxcj9.h b/driver/accel_kxcj9.h
index f7488317f0..e8d3c71929 100644
--- a/driver/accel_kxcj9.h
+++ b/driver/accel_kxcj9.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,98 +14,98 @@
  * 7-bit address is 000111Xb. Where 'X' is determined
  * by the voltage on the ADDR pin.
  */
-#define KXCJ9_ADDR0_FLAGS	0x0E
-#define KXCJ9_ADDR1_FLAGS	0x0D
-#define KXCJ9_WHO_AM_I_VAL	0x0A
+#define KXCJ9_ADDR0_FLAGS 0x0E
+#define KXCJ9_ADDR1_FLAGS 0x0D
+#define KXCJ9_WHO_AM_I_VAL 0x0A
 
 /* Chip-specific registers */
-#define KXCJ9_XOUT_L		0x06
-#define KXCJ9_XOUT_H		0x07
-#define KXCJ9_YOUT_L		0x08
-#define KXCJ9_YOUT_H		0x09
-#define KXCJ9_ZOUT_L		0x0a
-#define KXCJ9_ZOUT_H		0x0b
-#define KXCJ9_DCST_RESP		0x0c
-#define KXCJ9_WHOAMI		0x0f
-#define KXCJ9_INT_SRC1		0x16
-#define KXCJ9_INT_SRC2		0x17
-#define KXCJ9_STATUS		0x18
-#define KXCJ9_INT_REL		0x1a
-#define KXCJ9_CTRL1		0x1b
-#define KXCJ9_CTRL2		0x1d
-#define KXCJ9_INT_CTRL1		0x1e
-#define KXCJ9_INT_CTRL2		0x1f
-#define KXCJ9_DATA_CTRL		0x21
-#define KXCJ9_WAKEUP_TIMER	0x29
-#define KXCJ9_SELF_TEST		0x3a
-#define KXCJ9_WAKEUP_THRESHOLD	0x6a
-
-#define KXCJ9_INT_SRC1_WUFS	BIT(1)
-#define KXCJ9_INT_SRC1_DRDY	BIT(4)
-
-#define KXCJ9_INT_SRC2_ZPWU	BIT(0)
-#define KXCJ9_INT_SRC2_ZNWU	BIT(1)
-#define KXCJ9_INT_SRC2_YPWU	BIT(2)
-#define KXCJ9_INT_SRC2_YNWU	BIT(3)
-#define KXCJ9_INT_SRC2_XPWU	BIT(4)
-#define KXCJ9_INT_SRC2_XNWU	BIT(5)
-
-#define KXCJ9_STATUS_INT	BIT(4)
-
-#define KXCJ9_CTRL1_WUFE	BIT(1)
-#define KXCJ9_CTRL1_DRDYE	BIT(5)
-#define KXCJ9_CTRL1_PC1		BIT(7)
-
-#define KXCJ9_GSEL_2G		(0 << 3)
-#define KXCJ9_GSEL_4G		BIT(3)
-#define KXCJ9_GSEL_8G		(2 << 3)
-#define KXCJ9_GSEL_8G_14BIT	(3 << 3)
-#define KXCJ9_GSEL_ALL          (3 << 3)
-
-#define KXCJ9_RES_8BIT		(0 << 6)
-#define KXCJ9_RES_12BIT		BIT(6)
-
-#define KXCJ9_CTRL2_OWUF	(7 << 0)
-#define KXCJ9_CTRL2_DCST	BIT(4)
-#define KXCJ9_CTRL2_SRST	BIT(7)
-
-#define KXCJ9_OWUF_0_781HZ	0
-#define KXCJ9_OWUF_1_563HZ	1
-#define KXCJ9_OWUF_3_125HZ	2
-#define KXCJ9_OWUF_6_250HZ	3
-#define KXCJ9_OWUF_12_50HZ	4
-#define KXCJ9_OWUF_25_00HZ	5
-#define KXCJ9_OWUF_50_00HZ	6
-#define KXCJ9_OWUF_100_0HZ	7
-
-#define KXCJ9_INT_CTRL1_IEL		BIT(3)
-#define KXCJ9_INT_CTRL1_IEA		BIT(4)
-#define KXCJ9_INT_CTRL1_IEN		BIT(5)
-
-#define KXCJ9_INT_CTRL2_ZPWUE		BIT(0)
-#define KXCJ9_INT_CTRL2_ZNWUE		BIT(1)
-#define KXCJ9_INT_CTRL2_YPWUE		BIT(2)
-#define KXCJ9_INT_CTRL2_YNWUE		BIT(3)
-#define KXCJ9_INT_CTRL2_XPWUE		BIT(4)
-#define KXCJ9_INT_CTRL2_XNWUE		BIT(5)
-
-#define KXCJ9_OSA_0_000HZ	0
-#define KXCJ9_OSA_0_781HZ	8
-#define KXCJ9_OSA_1_563HZ	9
-#define KXCJ9_OSA_3_125HZ	0xa
-#define KXCJ9_OSA_6_250HZ	0xb
-#define KXCJ9_OSA_12_50HZ	0
-#define KXCJ9_OSA_25_00HZ	1
-#define KXCJ9_OSA_50_00HZ	2
-#define KXCJ9_OSA_100_0HZ	3
-#define KXCJ9_OSA_200_0HZ	4
-#define KXCJ9_OSA_400_0HZ	5
-#define KXCJ9_OSA_800_0HZ	6
-#define KXCJ9_OSA_1600_HZ	7
-#define KXCJ9_OSA_FIELD		0xf
+#define KXCJ9_XOUT_L 0x06
+#define KXCJ9_XOUT_H 0x07
+#define KXCJ9_YOUT_L 0x08
+#define KXCJ9_YOUT_H 0x09
+#define KXCJ9_ZOUT_L 0x0a
+#define KXCJ9_ZOUT_H 0x0b
+#define KXCJ9_DCST_RESP 0x0c
+#define KXCJ9_WHOAMI 0x0f
+#define KXCJ9_INT_SRC1 0x16
+#define KXCJ9_INT_SRC2 0x17
+#define KXCJ9_STATUS 0x18
+#define KXCJ9_INT_REL 0x1a
+#define KXCJ9_CTRL1 0x1b
+#define KXCJ9_CTRL2 0x1d
+#define KXCJ9_INT_CTRL1 0x1e
+#define KXCJ9_INT_CTRL2 0x1f
+#define KXCJ9_DATA_CTRL 0x21
+#define KXCJ9_WAKEUP_TIMER 0x29
+#define KXCJ9_SELF_TEST 0x3a
+#define KXCJ9_WAKEUP_THRESHOLD 0x6a
+
+#define KXCJ9_INT_SRC1_WUFS BIT(1)
+#define KXCJ9_INT_SRC1_DRDY BIT(4)
+
+#define KXCJ9_INT_SRC2_ZPWU BIT(0)
+#define KXCJ9_INT_SRC2_ZNWU BIT(1)
+#define KXCJ9_INT_SRC2_YPWU BIT(2)
+#define KXCJ9_INT_SRC2_YNWU BIT(3)
+#define KXCJ9_INT_SRC2_XPWU BIT(4)
+#define KXCJ9_INT_SRC2_XNWU BIT(5)
+
+#define KXCJ9_STATUS_INT BIT(4)
+
+#define KXCJ9_CTRL1_WUFE BIT(1)
+#define KXCJ9_CTRL1_DRDYE BIT(5)
+#define KXCJ9_CTRL1_PC1 BIT(7)
+
+#define KXCJ9_GSEL_2G (0 << 3)
+#define KXCJ9_GSEL_4G BIT(3)
+#define KXCJ9_GSEL_8G (2 << 3)
+#define KXCJ9_GSEL_8G_14BIT (3 << 3)
+#define KXCJ9_GSEL_ALL (3 << 3)
+
+#define KXCJ9_RES_8BIT (0 << 6)
+#define KXCJ9_RES_12BIT BIT(6)
+
+#define KXCJ9_CTRL2_OWUF (7 << 0)
+#define KXCJ9_CTRL2_DCST BIT(4)
+#define KXCJ9_CTRL2_SRST BIT(7)
+
+#define KXCJ9_OWUF_0_781HZ 0
+#define KXCJ9_OWUF_1_563HZ 1
+#define KXCJ9_OWUF_3_125HZ 2
+#define KXCJ9_OWUF_6_250HZ 3
+#define KXCJ9_OWUF_12_50HZ 4
+#define KXCJ9_OWUF_25_00HZ 5
+#define KXCJ9_OWUF_50_00HZ 6
+#define KXCJ9_OWUF_100_0HZ 7
+
+#define KXCJ9_INT_CTRL1_IEL BIT(3)
+#define KXCJ9_INT_CTRL1_IEA BIT(4)
+#define KXCJ9_INT_CTRL1_IEN BIT(5)
+
+#define KXCJ9_INT_CTRL2_ZPWUE BIT(0)
+#define KXCJ9_INT_CTRL2_ZNWUE BIT(1)
+#define KXCJ9_INT_CTRL2_YPWUE BIT(2)
+#define KXCJ9_INT_CTRL2_YNWUE BIT(3)
+#define KXCJ9_INT_CTRL2_XPWUE BIT(4)
+#define KXCJ9_INT_CTRL2_XNWUE BIT(5)
+
+#define KXCJ9_OSA_0_000HZ 0
+#define KXCJ9_OSA_0_781HZ 8
+#define KXCJ9_OSA_1_563HZ 9
+#define KXCJ9_OSA_3_125HZ 0xa
+#define KXCJ9_OSA_6_250HZ 0xb
+#define KXCJ9_OSA_12_50HZ 0
+#define KXCJ9_OSA_25_00HZ 1
+#define KXCJ9_OSA_50_00HZ 2
+#define KXCJ9_OSA_100_0HZ 3
+#define KXCJ9_OSA_200_0HZ 4
+#define KXCJ9_OSA_400_0HZ 5
+#define KXCJ9_OSA_800_0HZ 6
+#define KXCJ9_OSA_1600_HZ 7
+#define KXCJ9_OSA_FIELD 0xf
 
 /* Min and Max sampling frequency in mHz */
-#define KXCJ9_ACCEL_MIN_FREQ    12500
-#define KXCJ9_ACCEL_MAX_FREQ    MOTION_MAX_SENSOR_FREQUENCY(1600000, 6250)
+#define KXCJ9_ACCEL_MIN_FREQ 12500
+#define KXCJ9_ACCEL_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(1600000, 6250)
 
 #endif /* __CROS_EC_ACCEL_KXCJ9_H */
diff --git a/driver/accel_lis2dh.c b/driver/accel_lis2dh.c
index 35d275b379..eaedb216d7 100644
--- a/driver/accel_lis2dh.c
+++ b/driver/accel_lis2dh.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,8 +21,8 @@
 #include "driver/stm_mems_common.h"
 
 #define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
 
 /**
  * set_range - set full scale range
@@ -78,9 +78,9 @@ static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
 
 	if (rate == 0) {
 		/* Power Off device */
-		ret = st_write_data_with_mask(
-				s, LIS2DH_CTRL1_ADDR,
-				LIS2DH_ACC_ODR_MASK, LIS2DH_ODR_0HZ_VAL);
+		ret = st_write_data_with_mask(s, LIS2DH_CTRL1_ADDR,
+					      LIS2DH_ACC_ODR_MASK,
+					      LIS2DH_ODR_0HZ_VAL);
 		goto unlock_rate;
 	}
 
@@ -101,7 +101,7 @@ static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
 	 * to write accel parameters until we are done
 	 */
 	ret = st_write_data_with_mask(s, LIS2DH_CTRL1_ADDR, LIS2DH_ACC_ODR_MASK,
-			reg_val);
+				      reg_val);
 	if (ret == EC_SUCCESS)
 		data->base.odr = normalized_rate;
 
@@ -114,8 +114,8 @@ static int is_data_ready(const struct motion_sensor_t *s, int *ready)
 {
 	int ret, tmp;
 
-	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags,
-			   LIS2DH_STATUS_REG, &tmp);
+	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, LIS2DH_STATUS_REG,
+			   &tmp);
 	if (ret != EC_SUCCESS) {
 		CPRINTS("%s type:0x%X RS Error", s->name, s->type);
 		return ret;
@@ -147,8 +147,8 @@ static int read(const struct motion_sensor_t *s, intv3_t v)
 	}
 
 	/* Read output data bytes starting at LIS2DH_OUT_X_L_ADDR */
-	ret = st_raw_read_n(s->port, s->i2c_spi_addr_flags,
-			    LIS2DH_OUT_X_L_ADDR, raw, OUT_XYZ_SIZE);
+	ret = st_raw_read_n(s->port, s->i2c_spi_addr_flags, LIS2DH_OUT_X_L_ADDR,
+			    raw, OUT_XYZ_SIZE);
 	if (ret != EC_SUCCESS) {
 		CPRINTS("%s type:0x%X RD XYZ Error", s->name, s->type);
 		return ret;
@@ -195,34 +195,34 @@ static int init(struct motion_sensor_t *s)
 	 * register must be restored to it's default.
 	 */
 	/* Enable all accel axes data and clear old settings */
-	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-			    LIS2DH_CTRL1_ADDR, LIS2DH_ENABLE_ALL_AXES);
+	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags, LIS2DH_CTRL1_ADDR,
+			    LIS2DH_ENABLE_ALL_AXES);
 	if (ret != EC_SUCCESS)
 		goto err_unlock;
 
-	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-			    LIS2DH_CTRL2_ADDR, LIS2DH_CTRL2_RESET_VAL);
+	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags, LIS2DH_CTRL2_ADDR,
+			    LIS2DH_CTRL2_RESET_VAL);
 	if (ret != EC_SUCCESS)
 		goto err_unlock;
 
-	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-			    LIS2DH_CTRL3_ADDR, LIS2DH_CTRL3_RESET_VAL);
+	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags, LIS2DH_CTRL3_ADDR,
+			    LIS2DH_CTRL3_RESET_VAL);
 	if (ret != EC_SUCCESS)
 		goto err_unlock;
 
 	/* Enable BDU */
-	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-			    LIS2DH_CTRL4_ADDR, LIS2DH_BDU_MASK);
+	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags, LIS2DH_CTRL4_ADDR,
+			    LIS2DH_BDU_MASK);
 	if (ret != EC_SUCCESS)
 		goto err_unlock;
 
-	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-			    LIS2DH_CTRL5_ADDR, LIS2DH_CTRL5_RESET_VAL);
+	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags, LIS2DH_CTRL5_ADDR,
+			    LIS2DH_CTRL5_RESET_VAL);
 	if (ret != EC_SUCCESS)
 		goto err_unlock;
 
-	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-			    LIS2DH_CTRL6_ADDR, LIS2DH_CTRL6_RESET_VAL);
+	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags, LIS2DH_CTRL6_ADDR,
+			    LIS2DH_CTRL6_RESET_VAL);
 	if (ret != EC_SUCCESS)
 		goto err_unlock;
 
diff --git a/driver/accel_lis2dh.h b/driver/accel_lis2dh.h
index 2a3108aab8..a645c3403c 100644
--- a/driver/accel_lis2dh.h
+++ b/driver/accel_lis2dh.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,8 +16,8 @@
  * 7-bit address is 0011 00X b. Where 'X' is determined
  * by the voltage on the ADDR pin
  */
-#define LIS2DH_ADDR0_FLAGS	0x18
-#define LIS2DH_ADDR1_FLAGS	0x19
+#define LIS2DH_ADDR0_FLAGS 0x18
+#define LIS2DH_ADDR1_FLAGS 0x19
 
 /*
  * LNG2DM:
@@ -25,54 +25,54 @@
  * 8-bit address is 0101 00XW b. Where 'X' is determined
  * by the voltage on the ADDR pin, and 'W' is read write bit
  */
-#define LNG2DM_ADDR0_FLAGS	0x28
-#define LNG2DM_ADDR1_FLAGS	0x29
+#define LNG2DM_ADDR0_FLAGS 0x28
+#define LNG2DM_ADDR1_FLAGS 0x29
 
 /* Who Am I  */
-#define LIS2DH_WHO_AM_I_REG	0x0f
-#define LIS2DH_WHO_AM_I		0x33
+#define LIS2DH_WHO_AM_I_REG 0x0f
+#define LIS2DH_WHO_AM_I 0x33
 
 /* COMMON DEFINE FOR ACCEL SENSOR */
-#define LIS2DH_EN_BIT		0x01
-#define LIS2DH_DIS_BIT		0x00
+#define LIS2DH_EN_BIT 0x01
+#define LIS2DH_DIS_BIT 0x00
 
-#define LIS2DH_INT2_ON_INT1_ADDR	0x13
-#define LIS2DH_INT2_ON_INT1_MASK	0x20
+#define LIS2DH_INT2_ON_INT1_ADDR 0x13
+#define LIS2DH_INT2_ON_INT1_MASK 0x20
 
-#define LIS2DH_OUT_X_L_ADDR	0x28
+#define LIS2DH_OUT_X_L_ADDR 0x28
 
-#define LIS2DH_CTRL1_ADDR	0x20
-#define LIS2DH_INT2_ON_INT1_MASK	0x20
-#define LIS2DH_ENABLE_ALL_AXES	0x07
+#define LIS2DH_CTRL1_ADDR 0x20
+#define LIS2DH_INT2_ON_INT1_MASK 0x20
+#define LIS2DH_ENABLE_ALL_AXES 0x07
 
-#define LIS2DH_CTRL2_ADDR	0x21
-#define LIS2DH_CTRL2_RESET_VAL	0x00
+#define LIS2DH_CTRL2_ADDR 0x21
+#define LIS2DH_CTRL2_RESET_VAL 0x00
 
-#define LIS2DH_CTRL3_ADDR	0x22
-#define LIS2DH_CTRL3_RESET_VAL	0x00
+#define LIS2DH_CTRL3_ADDR 0x22
+#define LIS2DH_CTRL3_RESET_VAL 0x00
 
-#define LIS2DH_CTRL4_ADDR	0x23
-#define LIS2DH_BDU_MASK		0x80
+#define LIS2DH_CTRL4_ADDR 0x23
+#define LIS2DH_BDU_MASK 0x80
 
-#define LIS2DH_CTRL5_ADDR	0x24
-#define LIS2DH_CTRL5_RESET_VAL	0x00
+#define LIS2DH_CTRL5_ADDR 0x24
+#define LIS2DH_CTRL5_RESET_VAL 0x00
 
-#define LIS2DH_CTRL6_ADDR	0x25
-#define LIS2DH_CTRL6_RESET_VAL	0x00
+#define LIS2DH_CTRL6_ADDR 0x25
+#define LIS2DH_CTRL6_RESET_VAL 0x00
 
-#define LIS2DH_STATUS_REG	0x27
-#define LIS2DH_STS_XLDA_UP	0x80
+#define LIS2DH_STATUS_REG 0x27
+#define LIS2DH_STS_XLDA_UP 0x80
 
-#define LIS2DH_FS_2G_VAL         0x00
-#define LIS2DH_FS_4G_VAL         0x01
-#define LIS2DH_FS_8G_VAL         0x02
-#define LIS2DH_FS_16G_VAL        0x03
+#define LIS2DH_FS_2G_VAL 0x00
+#define LIS2DH_FS_4G_VAL 0x01
+#define LIS2DH_FS_8G_VAL 0x02
+#define LIS2DH_FS_16G_VAL 0x03
 
 /* Interrupt source status register */
-#define LIS2DH_INT1_SRC_REG	0x31
+#define LIS2DH_INT1_SRC_REG 0x31
 
 /* Output data rate Mask register */
-#define LIS2DH_ACC_ODR_MASK	0xf0
+#define LIS2DH_ACC_ODR_MASK 0xf0
 
 /* Acc data rate */
 enum lis2dh_odr {
@@ -88,28 +88,29 @@ enum lis2dh_odr {
 };
 
 /* Absolute maximum rate for sensor */
-#define LIS2DH_ODR_MIN_VAL		1000
-#define LIS2DH_ODR_MAX_VAL \
-	MOTION_MAX_SENSOR_FREQUENCY(400000, 25000)
+#define LIS2DH_ODR_MIN_VAL 1000
+#define LIS2DH_ODR_MAX_VAL MOTION_MAX_SENSOR_FREQUENCY(400000, 25000)
 
 /* Return ODR reg value based on data rate set */
-#define LIS2DH_ODR_TO_REG(_odr) \
-	(_odr <= 1000) ? LIS2DH_ODR_1HZ_VAL : \
+#define LIS2DH_ODR_TO_REG(_odr)                 \
+	(_odr <= 1000)	? LIS2DH_ODR_1HZ_VAL :  \
 	(_odr <= 10000) ? LIS2DH_ODR_10HZ_VAL : \
-	((31 - __builtin_clz(_odr / 25000))) + 3
+			  ((31 - __builtin_clz(_odr / 25000))) + 3
 
 /* Return ODR real value normalized to sensor capabilities */
 #define LIS2DH_ODR_TO_NORMALIZE(_odr) \
-	(_odr <= 1000) ? 1000 : (_odr <= 10000) ? 10000 : \
-	(25000 * (1 << (31 - __builtin_clz(_odr / 25000))))
+	(_odr <= 1000)	? 1000 :      \
+	(_odr <= 10000) ? 10000 :     \
+			  (25000 * (1 << (31 - __builtin_clz(_odr / 25000))))
 
 /* Return ODR real value normalized to sensor capabilities from reg value */
-#define LIS2DH_REG_TO_NORMALIZE(_reg) \
-	(_reg == LIS2DH_ODR_1HZ_VAL) ? 1000 : \
-	(_reg == LIS2DH_ODR_10HZ_VAL) ? 10000 : (25000 * (1 << (_reg - 3)))
+#define LIS2DH_REG_TO_NORMALIZE(_reg)           \
+	(_reg == LIS2DH_ODR_1HZ_VAL)  ? 1000 :  \
+	(_reg == LIS2DH_ODR_10HZ_VAL) ? 10000 : \
+					(25000 * (1 << (_reg - 3)))
 
 /* Full scale range Mask register */
-#define LIS2DH_FS_MASK		0x30
+#define LIS2DH_FS_MASK 0x30
 
 /* FS reg value from Full Scale */
 #define LIS2DH_FS_TO_REG(_fs) (__fls(_fs) - 1)
@@ -123,9 +124,9 @@ enum lis2dh_odr {
  * lis2de/lng2dm only support 8bit resolution.
  */
 #if defined(CONFIG_ACCEL_LIS2DE) || defined(CONFIG_ACCEL_LNG2DM)
-#define LIS2DH_RESOLUTION       8
+#define LIS2DH_RESOLUTION 8
 #elif defined(CONFIG_ACCEL_LIS2DH)
-#define LIS2DH_RESOLUTION      	10
+#define LIS2DH_RESOLUTION 10
 #endif
 
 extern const struct accelgyro_drv lis2dh_drv;
diff --git a/driver/accel_lis2ds.c b/driver/accel_lis2ds.c
index 0743b428eb..2fea7524e5 100644
--- a/driver/accel_lis2ds.c
+++ b/driver/accel_lis2ds.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -28,10 +28,10 @@
 #define ACCEL_LIS2DS_INT_ENABLE
 #endif
 
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args)
 
 STATIC_IF(ACCEL_LIS2DS_INT_ENABLE)
-	volatile uint32_t last_interrupt_timestamp;
+volatile uint32_t last_interrupt_timestamp;
 
 /**
  * lis2ds_enable_fifo - Enable/Disable FIFO in LIS2DS12
@@ -49,8 +49,8 @@ static int lis2ds_config_interrupt(const struct motion_sensor_t *s)
 	int ret = EC_SUCCESS;
 
 	/* Interrupt trigger level of power-on-reset is HIGH */
-	RETURN_ERROR(st_write_data_with_mask(s, LIS2DS_H_ACTIVE_ADDR,
-				LIS2DS_H_ACTIVE_MASK, LIS2DS_EN_BIT));
+	RETURN_ERROR(st_write_data_with_mask(
+		s, LIS2DS_H_ACTIVE_ADDR, LIS2DS_H_ACTIVE_MASK, LIS2DS_EN_BIT));
 
 	/*
 	 * Configure FIFO threshold to 1 sample: interrupt on watermark
@@ -60,13 +60,13 @@ static int lis2ds_config_interrupt(const struct motion_sensor_t *s)
 	 * configured threshold.
 	 */
 	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-			LIS2DS_FIFO_THS_ADDR, 1);
+			    LIS2DS_FIFO_THS_ADDR, 1);
 	if (ret != EC_SUCCESS)
 		return ret;
 
 	/* Enable interrupt on FIFO watermark and route to int1. */
-	ret = st_write_data_with_mask(s, LIS2DS_CTRL4_ADDR,
-			LIS2DS_INT1_FTH, LIS2DS_EN_BIT);
+	ret = st_write_data_with_mask(s, LIS2DS_CTRL4_ADDR, LIS2DS_INT1_FTH,
+				      LIS2DS_EN_BIT);
 
 	return ret;
 }
@@ -137,20 +137,17 @@ void lis2ds_interrupt(enum gpio_signal signal)
 /**
  * lis2ds_irq_handler - bottom half of the interrupt stack.
  */
-static int lis2ds_irq_handler(struct motion_sensor_t *s,
-					     uint32_t *event)
+static int lis2ds_irq_handler(struct motion_sensor_t *s, uint32_t *event)
 {
 	int ret = EC_SUCCESS;
 	uint16_t nsamples = 0;
 	uint8_t fifo_src_samples[2];
 
-
 	if ((s->type != MOTIONSENSE_TYPE_ACCEL) ||
 	    (!(*event & CONFIG_ACCEL_LIS2DS_INT_EVENT)))
 		return EC_ERROR_NOT_HANDLED;
 
-	ret = st_raw_read_n_noinc(s->port,
-				  s->i2c_spi_addr_flags,
+	ret = st_raw_read_n_noinc(s->port, s->i2c_spi_addr_flags,
 				  LIS2DS_FIFO_SRC_ADDR,
 				  (uint8_t *)fifo_src_samples,
 				  sizeof(fifo_src_samples));
@@ -169,7 +166,7 @@ static int lis2ds_irq_handler(struct motion_sensor_t *s,
 	return lis2ds_load_fifo(s, nsamples, last_interrupt_timestamp);
 }
 
-#endif  /* ACCEL_LIS2DS_INT_ENABLE */
+#endif /* ACCEL_LIS2DS_INT_ENABLE */
 
 /**
  * set_range - set full scale range
@@ -257,8 +254,8 @@ static int is_data_ready(const struct motion_sensor_t *s, int *ready)
 {
 	int ret, tmp;
 
-	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags,
-			   LIS2DS_STATUS_REG, &tmp);
+	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, LIS2DS_STATUS_REG,
+			   &tmp);
 	if (ret != EC_SUCCESS) {
 		CPRINTS("%s: type:0x%X RD XYZ Error %d", s->name, s->type, ret);
 		return ret;
@@ -309,8 +306,8 @@ static int init(struct motion_sensor_t *s)
 	int ret = 0, tmp;
 	struct stprivate_data *data = s->drv_data;
 
-	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags,
-			   LIS2DS_WHO_AM_I_REG, &tmp);
+	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, LIS2DS_WHO_AM_I_REG,
+			   &tmp);
 	if (ret != EC_SUCCESS)
 		return EC_ERROR_UNKNOWN;
 
diff --git a/driver/accel_lis2ds.h b/driver/accel_lis2ds.h
index e25bc5954f..3f821b3514 100644
--- a/driver/accel_lis2ds.h
+++ b/driver/accel_lis2ds.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,95 +14,93 @@
  * 7-bit address is 110101Xb. Where 'X' is determined
  * by the voltage on the ADDR pin.
  */
-#define LIS2DS_ADDR0_FLAGS		0x1a
-#define LIS2DS_ADDR1_FLAGS		0x1e
+#define LIS2DS_ADDR0_FLAGS 0x1a
+#define LIS2DS_ADDR1_FLAGS 0x1e
 
 /* who am I  */
-#define LIS2DS_WHO_AM_I_REG		0x0f
-#define LIS2DS_WHO_AM_I			0x43
+#define LIS2DS_WHO_AM_I_REG 0x0f
+#define LIS2DS_WHO_AM_I 0x43
 
 /* X, Y, Z axis data len */
-#define LIS2DS_OUT_XYZ_SIZE		6
+#define LIS2DS_OUT_XYZ_SIZE 6
 
 /* COMMON DEFINE FOR ACCEL SENSOR */
-#define LIS2DS_EN_BIT			0x01
-#define LIS2DS_DIS_BIT			0x00
-
-#define LIS2DS_CTRL1_ADDR		0x20
-#define LIS2DS_CTRL2_ADDR		0x21
-#define LIS2DS_CTRL3_ADDR		0x22
-#define LIS2DS_TAP_X_EN			0x20
-#define LIS2DS_TAP_Y_EN			0x10
-#define LIS2DS_TAP_Z_EN			0x08
-#define LIS2DS_TAP_EN_MASK		(LIS2DS_TAP_X_EN | \
-					 LIS2DS_TAP_Y_EN | \
-					 LIS2DS_TAP_Z_EN)
-#define LIS2DS_TAP_EN_ALL		0x07
-
-#define LIS2DS_CTRL4_ADDR		0x23
-#define LIS2DS_INT1_FTH			0x02
-#define LIS2DS_INT1_D_TAP		0x08
-#define LIS2DS_INT1_S_TAP		0x40
-
-#define LIS2DS_CTRL5_ADDR		0x24
-#define LIS2DS_FIFO_CTRL_ADDR		0x25
-#define LIS2DS_FIFO_MODE_MASK		0xe0
-#define LIS2DS_FIFO_BYPASS_MODE		0
-#define LIS2DS_FIFO_MODE		1
-#define LIS2DS_FIFO_CONT_MODE		6
-
-#define LIS2DS_STATUS_REG		0x27
-#define LIS2DS_STS_XLDA_UP		0x01
-#define LIS2DS_SINGLE_TAP_UP		0x08
-#define LIS2DS_DOUBLE_TAP_UP		0x10
-#define LIS2DS_FIFO_THS_UP		0x80
-
-#define LIS2DS_OUT_X_L_ADDR		0x28
-#define LIS2DS_FIFO_THS_ADDR		0x2e
-
-#define LIS2DS_FIFO_SRC_ADDR		0x2f
-#define LIS2DS_FIFO_DIFF_MASK		0xff
-#define LIS2DS_FIFO_DIFF8_MASK		0x20
-#define LIS2DS_FIFO_OVR_MASK		0x40
-#define LIS2DS_FIFO_FTH_MASK		0x80
+#define LIS2DS_EN_BIT 0x01
+#define LIS2DS_DIS_BIT 0x00
+
+#define LIS2DS_CTRL1_ADDR 0x20
+#define LIS2DS_CTRL2_ADDR 0x21
+#define LIS2DS_CTRL3_ADDR 0x22
+#define LIS2DS_TAP_X_EN 0x20
+#define LIS2DS_TAP_Y_EN 0x10
+#define LIS2DS_TAP_Z_EN 0x08
+#define LIS2DS_TAP_EN_MASK (LIS2DS_TAP_X_EN | LIS2DS_TAP_Y_EN | LIS2DS_TAP_Z_EN)
+#define LIS2DS_TAP_EN_ALL 0x07
+
+#define LIS2DS_CTRL4_ADDR 0x23
+#define LIS2DS_INT1_FTH 0x02
+#define LIS2DS_INT1_D_TAP 0x08
+#define LIS2DS_INT1_S_TAP 0x40
+
+#define LIS2DS_CTRL5_ADDR 0x24
+#define LIS2DS_FIFO_CTRL_ADDR 0x25
+#define LIS2DS_FIFO_MODE_MASK 0xe0
+#define LIS2DS_FIFO_BYPASS_MODE 0
+#define LIS2DS_FIFO_MODE 1
+#define LIS2DS_FIFO_CONT_MODE 6
+
+#define LIS2DS_STATUS_REG 0x27
+#define LIS2DS_STS_XLDA_UP 0x01
+#define LIS2DS_SINGLE_TAP_UP 0x08
+#define LIS2DS_DOUBLE_TAP_UP 0x10
+#define LIS2DS_FIFO_THS_UP 0x80
+
+#define LIS2DS_OUT_X_L_ADDR 0x28
+#define LIS2DS_FIFO_THS_ADDR 0x2e
+
+#define LIS2DS_FIFO_SRC_ADDR 0x2f
+#define LIS2DS_FIFO_DIFF_MASK 0xff
+#define LIS2DS_FIFO_DIFF8_MASK 0x20
+#define LIS2DS_FIFO_OVR_MASK 0x40
+#define LIS2DS_FIFO_FTH_MASK 0x80
 
 /*
  * Concatenated with DIFF8 bit in FIFO_SRC (2Fh) register, it represents the
  * number of unread samples stored in FIFO. (000000000 = FIFO empty;
  * 100000000 = FIFO full, 256 unread samples).
  */
-#define LIS2DS_FIFO_SAMPLES_ADDR	0x30
-#define LIS2DS_TAP_6D_THS_ADDR		0x31
-#define LIS2DS_INT_DUR_ADDR		0x32
-#define LIS2DS_WAKE_UP_THS_ADDR		0x33
+#define LIS2DS_FIFO_SAMPLES_ADDR 0x30
+#define LIS2DS_TAP_6D_THS_ADDR 0x31
+#define LIS2DS_INT_DUR_ADDR 0x32
+#define LIS2DS_WAKE_UP_THS_ADDR 0x33
 
-#define LIS2DS_TAP_SRC_ADDR		0x38
-#define LIS2DS_TAP_EVENT_DETECT		0x40
+#define LIS2DS_TAP_SRC_ADDR 0x38
+#define LIS2DS_TAP_EVENT_DETECT 0x40
 
 /* Alias Register/Mask */
-#define LIS2DS_ACC_ODR_ADDR		LIS2DS_CTRL1_ADDR
-#define LIS2DS_ACC_ODR_MASK		0xf0
+#define LIS2DS_ACC_ODR_ADDR LIS2DS_CTRL1_ADDR
+#define LIS2DS_ACC_ODR_MASK 0xf0
 
-#define LIS2DS_BDU_ADDR			LIS2DS_CTRL1_ADDR
-#define LIS2DS_BDU_MASK			0x01
+#define LIS2DS_BDU_ADDR LIS2DS_CTRL1_ADDR
+#define LIS2DS_BDU_MASK 0x01
 
-#define LIS2DS_SOFT_RESET_ADDR		LIS2DS_CTRL2_ADDR
-#define LIS2DS_SOFT_RESET_MASK		0x40
+#define LIS2DS_SOFT_RESET_ADDR LIS2DS_CTRL2_ADDR
+#define LIS2DS_SOFT_RESET_MASK 0x40
 
-#define LIS2DS_LIR_ADDR			LIS2DS_CTRL3_ADDR
-#define LIS2DS_LIR_MASK			0x04
+#define LIS2DS_LIR_ADDR LIS2DS_CTRL3_ADDR
+#define LIS2DS_LIR_MASK 0x04
 
-#define LIS2DS_H_ACTIVE_ADDR		LIS2DS_CTRL3_ADDR
-#define LIS2DS_H_ACTIVE_MASK		0x02
+#define LIS2DS_H_ACTIVE_ADDR LIS2DS_CTRL3_ADDR
+#define LIS2DS_H_ACTIVE_MASK 0x02
 
-#define LIS2DS_INT1_FTH_ADDR		LIS2DS_CTRL4_ADDR
-#define LIS2DS_INT1_FTH_MASK		0x02
+#define LIS2DS_INT1_FTH_ADDR LIS2DS_CTRL4_ADDR
+#define LIS2DS_INT1_FTH_MASK 0x02
 
-#define LIS2DS_INT2_ON_INT1_ADDR	LIS2DS_CTRL5_ADDR
-#define LIS2DS_INT2_ON_INT1_MASK	0x20
+#define LIS2DS_INT2_ON_INT1_ADDR LIS2DS_CTRL5_ADDR
+#define LIS2DS_INT2_ON_INT1_MASK 0x20
 
-#define LIS2DS_DRDY_PULSED_ADDR		LIS2DS_CTRL5_ADDR
-#define LIS2DS_DRDY_PULSED_MASK		0x80
+#define LIS2DS_DRDY_PULSED_ADDR LIS2DS_CTRL5_ADDR
+#define LIS2DS_DRDY_PULSED_MASK 0x80
 
 /* Acc data rate for HR mode */
 enum lis2ds_odr {
@@ -118,7 +116,7 @@ enum lis2ds_odr {
 };
 
 /* Absolute Acc rate */
-#define LIS2DS_ODR_MIN_VAL		12500
+#define LIS2DS_ODR_MIN_VAL 12500
 #define LIS2DS_ODR_MAX_VAL \
 	MOTION_MAX_SENSOR_FREQUENCY(800000, LIS2DS_ODR_MIN_VAL)
 
@@ -130,8 +128,8 @@ enum lis2ds_odr {
 	(LIS2DS_ODR_MIN_VAL << (_reg - LIS2DS_ODR_12HZ_VAL))
 
 /* Full scale range registers */
-#define LIS2DS_FS_ADDR			LIS2DS_CTRL1_ADDR
-#define LIS2DS_FS_MASK			0x0c
+#define LIS2DS_FS_ADDR LIS2DS_CTRL1_ADDR
+#define LIS2DS_FS_MASK 0x0c
 
 /* Acc FS value */
 enum lis2ds_fs {
@@ -142,20 +140,20 @@ enum lis2ds_fs {
 	LIS2DS_FS_LIST_NUM
 };
 
-#define LIS2DS_ACCEL_FS_MAX_VAL		16
-#define LIS2DS_ACCEL_FS_MIN_VAL		2
+#define LIS2DS_ACCEL_FS_MAX_VAL 16
+#define LIS2DS_ACCEL_FS_MIN_VAL 2
 
 /* Reg value from Full Scale */
-#define LIS2DS_FS_REG(_fs) \
-	(_fs == 2 ? LIS2DS_FS_2G_VAL : \
-	_fs == 16 ? LIS2DS_FS_16G_VAL : \
-	__fls(_fs))
+#define LIS2DS_FS_REG(_fs)               \
+	(_fs == 2  ? LIS2DS_FS_2G_VAL :  \
+	 _fs == 16 ? LIS2DS_FS_16G_VAL : \
+		     __fls(_fs))
 
 /*
  * Sensor resolution in number of bits. Sensor has two resolution:
  * 10 and 14 bit for LP and HR mode resp.
  */
-#define LIS2DS_RESOLUTION		16
+#define LIS2DS_RESOLUTION 16
 
 extern const struct accelgyro_drv lis2ds_drv;
 
diff --git a/driver/accel_lis2dw12.c b/driver/accel_lis2dw12.c
index eef1cc6f8f..3cf3e4b64a 100644
--- a/driver/accel_lis2dw12.c
+++ b/driver/accel_lis2dw12.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,11 +22,11 @@
 #define ACCEL_LIS2DW12_INT_ENABLE
 #endif
 
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args)
 
 STATIC_IF(ACCEL_LIS2DW12_INT_ENABLE)
-	volatile uint32_t last_interrupt_timestamp;
+volatile uint32_t last_interrupt_timestamp;
 
 /**
  * lis2dw12_enable_fifo - Enable/Disable FIFO in LIS2DW12
@@ -34,7 +34,7 @@ STATIC_IF(ACCEL_LIS2DW12_INT_ENABLE)
  * @mode: fifo_modes
  */
 static __maybe_unused int lis2dw12_enable_fifo(const struct motion_sensor_t *s,
-			enum lis2dw12_fmode mode)
+					       enum lis2dw12_fmode mode)
 {
 	return st_write_data_with_mask(s, LIS2DW12_FIFO_CTRL_ADDR,
 				       LIS2DW12_FIFO_MODE_MASK, mode);
@@ -46,16 +46,17 @@ static __maybe_unused int lis2dw12_enable_fifo(const struct motion_sensor_t *s,
  *
  * Must works with interface mutex locked
  */
-static __maybe_unused int lis2dw12_config_interrupt(
-		const struct motion_sensor_t *s)
+static __maybe_unused int
+lis2dw12_config_interrupt(const struct motion_sensor_t *s)
 {
 	/* Configure FIFO watermark level. */
 	RETURN_ERROR(st_write_data_with_mask(s, LIS2DW12_FIFO_CTRL_ADDR,
-				LIS2DW12_FIFO_THRESHOLD_MASK, 1));
+					     LIS2DW12_FIFO_THRESHOLD_MASK, 1));
 
 	/* Enable interrupt on FIFO watermark and route to int1. */
 	RETURN_ERROR(st_write_data_with_mask(s, LIS2DW12_INT1_FTH_ADDR,
-				LIS2DW12_INT1_FTH_MASK, LIS2DW12_EN_BIT));
+					     LIS2DW12_INT1_FTH_MASK,
+					     LIS2DW12_EN_BIT));
 
 	if (IS_ENABLED(CONFIG_GESTURE_SENSOR_DOUBLE_TAP)) {
 		/*
@@ -63,27 +64,26 @@ static __maybe_unused int lis2dw12_config_interrupt(
 		 * For more details please refer to AN5038.
 		 */
 		RETURN_ERROR(st_raw_write8(s->port, s->i2c_spi_addr_flags,
-				LIS2DW12_TAP_THS_X_ADDR, 0x09));
+					   LIS2DW12_TAP_THS_X_ADDR, 0x09));
 		RETURN_ERROR(st_raw_write8(s->port, s->i2c_spi_addr_flags,
-				LIS2DW12_TAP_THS_Y_ADDR, 0x09));
+					   LIS2DW12_TAP_THS_Y_ADDR, 0x09));
 		RETURN_ERROR(st_raw_write8(s->port, s->i2c_spi_addr_flags,
-				LIS2DW12_TAP_THS_Z_ADDR, 0xE9));
+					   LIS2DW12_TAP_THS_Z_ADDR, 0xE9));
 		RETURN_ERROR(st_raw_write8(s->port, s->i2c_spi_addr_flags,
-				LIS2DW12_INT_DUR_ADDR, 0x7F));
+					   LIS2DW12_INT_DUR_ADDR, 0x7F));
 
 		/* Enable D-TAP event detection. */
-		RETURN_ERROR(st_write_data_with_mask(s,
-					LIS2DW12_WAKE_UP_THS_ADDR,
-					LIS2DW12_SINGLE_DOUBLE_TAP,
-					LIS2DW12_EN_BIT));
+		RETURN_ERROR(st_write_data_with_mask(
+			s, LIS2DW12_WAKE_UP_THS_ADDR,
+			LIS2DW12_SINGLE_DOUBLE_TAP, LIS2DW12_EN_BIT));
 
 		/*
 		 * Enable D-TAP detection on int_1 pad. In any case D-TAP event
 		 * can be detected only if ODR is over 200 Hz.
 		 */
 		RETURN_ERROR(st_write_data_with_mask(s, LIS2DW12_INT1_TAP_ADDR,
-				LIS2DW12_INT1_DTAP_MASK,
-				LIS2DW12_EN_BIT));
+						     LIS2DW12_INT1_DTAP_MASK,
+						     LIS2DW12_EN_BIT));
 	}
 	return EC_SUCCESS;
 }
@@ -93,8 +93,7 @@ static __maybe_unused int lis2dw12_config_interrupt(
  * Load data from internal sensor FIFO.
  * @s: Motion sensor pointer
  */
-static int lis2dw12_load_fifo(struct motion_sensor_t *s,
-			      int nsamples)
+static int lis2dw12_load_fifo(struct motion_sensor_t *s, int nsamples)
 {
 	int ret, left, length, i;
 	uint32_t interrupt_timestamp = last_interrupt_timestamp;
@@ -131,8 +130,8 @@ static int lis2dw12_load_fifo(struct motion_sensor_t *s,
 				vect.data[Z] = axis[Z];
 				vect.flags = 0;
 				vect.sensor_num = s - motion_sensors;
-				motion_sense_fifo_stage_data(&vect, s, 3,
-						interrupt_timestamp);
+				motion_sense_fifo_stage_data(
+					&vect, s, 3, interrupt_timestamp);
 			} else {
 				motion_sense_push_raw_xyz(s);
 			}
@@ -146,8 +145,7 @@ static int lis2dw12_load_fifo(struct motion_sensor_t *s,
 /**
  * lis2dw12_get_fifo_samples - check for stored FIFO samples.
  */
-static int lis2dw12_get_fifo_samples(struct motion_sensor_t *s,
-				     int *nsamples)
+static int lis2dw12_get_fifo_samples(struct motion_sensor_t *s, int *nsamples)
 {
 	int ret, tmp;
 
@@ -175,8 +173,7 @@ void lis2dw12_interrupt(enum gpio_signal signal)
 /**
  * lis2dw12_irq_handler - bottom half of the interrupt stack.
  */
-static int lis2dw12_irq_handler(struct motion_sensor_t *s,
-					       uint32_t *event)
+static int lis2dw12_irq_handler(struct motion_sensor_t *s, uint32_t *event)
 {
 	bool commit_needed = false;
 	int nsamples;
@@ -194,7 +191,7 @@ static int lis2dw12_irq_handler(struct motion_sensor_t *s,
 			     LIS2DW12_STATUS_TAP, &status);
 		if (status & LIS2DW12_DOUBLE_TAP)
 			*event |= TASK_EVENT_MOTION_ACTIVITY_INTERRUPT(
-					MOTIONSENSE_ACTIVITY_DOUBLE_TAP);
+				MOTIONSENSE_ACTIVITY_DOUBLE_TAP);
 	}
 
 	do {
@@ -231,8 +228,7 @@ int lis2dw12_set_power_mode(const struct motion_sensor_t *s,
 {
 	int ret = EC_SUCCESS;
 
-	if (mode == LIS2DW12_LOW_POWER &&
-	    lpmode == LIS2DW12_LOW_POWER_MODE_1)
+	if (mode == LIS2DW12_LOW_POWER && lpmode == LIS2DW12_LOW_POWER_MODE_1)
 		return EC_ERROR_UNIMPLEMENTED;
 
 	/* Set Mode and Low Power Mode. */
@@ -364,8 +360,9 @@ static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
 		if (reg_val > LIS2DW12_ODR_200HZ_VAL)
 			ret = lis2dw12_set_power_mode(s, LIS2DW12_HIGH_PERF, 0);
 		else
-			ret = lis2dw12_set_power_mode(s, LIS2DW12_LOW_POWER,
-					LIS2DW12_LOW_POWER_MODE_2);
+			ret = lis2dw12_set_power_mode(
+				s, LIS2DW12_LOW_POWER,
+				LIS2DW12_LOW_POWER_MODE_2);
 	}
 
 	ret = st_write_data_with_mask(s, LIS2DW12_ACC_ODR_ADDR,
@@ -387,8 +384,8 @@ static int is_data_ready(const struct motion_sensor_t *s, int *ready)
 {
 	int ret, tmp;
 
-	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags,
-			   LIS2DW12_STATUS_REG, &tmp);
+	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, LIS2DW12_STATUS_REG,
+			   &tmp);
 	if (ret != EC_SUCCESS)
 		return ret;
 
@@ -419,8 +416,7 @@ static int read(const struct motion_sensor_t *s, intv3_t v)
 
 	/* Read 6 bytes starting at xyz_reg. */
 	ret = st_raw_read_n_noinc(s->port, s->i2c_spi_addr_flags,
-				  LIS2DW12_OUT_X_L_ADDR, raw,
-				  OUT_XYZ_SIZE);
+				  LIS2DW12_OUT_X_L_ADDR, raw, OUT_XYZ_SIZE);
 	if (ret != EC_SUCCESS) {
 		CPRINTS("%s type:0x%X RD XYZ Error", s->name, s->type);
 		return ret;
@@ -466,7 +462,7 @@ static int init(struct motion_sensor_t *s)
 		msleep(1);
 		timeout += 1;
 		ret = st_raw_read8(s->port, s->i2c_spi_addr_flags,
-				  LIS2DW12_SOFT_RESET_ADDR, &status);
+				   LIS2DW12_SOFT_RESET_ADDR, &status);
 	} while (ret != EC_SUCCESS || (status & LIS2DW12_SOFT_RESET_MASK) != 0);
 
 	/* Enable BDU. */
@@ -483,8 +479,8 @@ static int init(struct motion_sensor_t *s)
 	/* Interrupt trigger level of power-on-reset is HIGH */
 	if (IS_ENABLED(ACCEL_LIS2DW12_INT_ENABLE)) {
 		ret = st_write_data_with_mask(s, LIS2DW12_H_ACTIVE_ADDR,
-						LIS2DW12_H_ACTIVE_MASK,
-						LIS2DW12_EN_BIT);
+					      LIS2DW12_H_ACTIVE_MASK,
+					      LIS2DW12_EN_BIT);
 		if (ret != EC_SUCCESS)
 			goto err_unlock;
 	}
@@ -498,7 +494,7 @@ static int init(struct motion_sensor_t *s)
 	else
 		/* Set default Mode and Low Power Mode. */
 		ret = lis2dw12_set_power_mode(s, LIS2DW12_LOW_POWER,
-				     LIS2DW12_LOW_POWER_MODE_2);
+					      LIS2DW12_LOW_POWER_MODE_2);
 	if (ret != EC_SUCCESS)
 		goto err_unlock;
 
diff --git a/driver/accel_lis2dw12.h b/driver/accel_lis2dw12.h
index c0f32427ff..f0c7174123 100644
--- a/driver/accel_lis2dw12.h
+++ b/driver/accel_lis2dw12.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,46 +15,46 @@
 #include "stm_mems_common.h"
 
 /* Who am I. */
-#define LIS2DW12_WHO_AM_I_REG		0x0f
-#define LIS2DW12_WHO_AM_I		0x44
+#define LIS2DW12_WHO_AM_I_REG 0x0f
+#define LIS2DW12_WHO_AM_I 0x44
 
 /* Registers sensor. */
-#define LIS2DW12_CTRL1_ADDR		0x20
-#define LIS2DW12_CTRL2_ADDR		0x21
-#define LIS2DW12_CTRL3_ADDR		0x22
+#define LIS2DW12_CTRL1_ADDR 0x20
+#define LIS2DW12_CTRL2_ADDR 0x21
+#define LIS2DW12_CTRL3_ADDR 0x22
 
-#define LIS2DW12_CTRL4_ADDR		0x23
+#define LIS2DW12_CTRL4_ADDR 0x23
 
 /* CTRL4 bits. */
-#define LIS2DW12_INT1_FTH		0x02
-#define LIS2DW12_INT1_D_TAP		0x08
-#define LIS2DW12_INT1_S_TAP		0x40
+#define LIS2DW12_INT1_FTH 0x02
+#define LIS2DW12_INT1_D_TAP 0x08
+#define LIS2DW12_INT1_S_TAP 0x40
 
-#define LIS2DW12_CTRL5_ADDR		0x24
+#define LIS2DW12_CTRL5_ADDR 0x24
 
 /* CTRL5 bits. */
-#define LIS2DW12_INT2_FTH		0x02
+#define LIS2DW12_INT2_FTH 0x02
 
-#define LIS2DW12_CTRL6_ADDR		0x25
-#define LIS2DW12_STATUS_REG		0x27
+#define LIS2DW12_CTRL6_ADDR 0x25
+#define LIS2DW12_STATUS_REG 0x27
 
 /* STATUS bits. */
-#define LIS2DW12_STS_DRDY_UP		0x01
-#define LIS2DW12_SINGLE_TAP_UP		0x08
-#define LIS2DW12_DOUBLE_TAP_UP		0x10
-#define LIS2DW12_FIFO_THS_UP		0x80
+#define LIS2DW12_STS_DRDY_UP 0x01
+#define LIS2DW12_SINGLE_TAP_UP 0x08
+#define LIS2DW12_DOUBLE_TAP_UP 0x10
+#define LIS2DW12_FIFO_THS_UP 0x80
 
-#define LIS2DW12_OUT_X_L_ADDR		0x28
-#define LIS2DW12_OUT_X_H_ADDR		0x29
-#define LIS2DW12_OUT_Y_L_ADDR		0x2a
-#define LIS2DW12_OUT_Y_H_ADDR		0x2b
-#define LIS2DW12_OUT_Z_L_ADDR		0x2c
-#define LIS2DW12_OUT_Z_H_ADDR		0x2d
+#define LIS2DW12_OUT_X_L_ADDR 0x28
+#define LIS2DW12_OUT_X_H_ADDR 0x29
+#define LIS2DW12_OUT_Y_L_ADDR 0x2a
+#define LIS2DW12_OUT_Y_H_ADDR 0x2b
+#define LIS2DW12_OUT_Z_L_ADDR 0x2c
+#define LIS2DW12_OUT_Z_H_ADDR 0x2d
 
-#define LIS2DW12_FIFO_CTRL_ADDR		0x2e
+#define LIS2DW12_FIFO_CTRL_ADDR 0x2e
 
 /* FIFO_CTRL bits. */
-#define LIS2DW12_FIFO_MODE_MASK		0xe0
+#define LIS2DW12_FIFO_MODE_MASK 0xe0
 
 /* List of supported FIFO mode. */
 enum lis2dw12_fmode {
@@ -63,37 +63,37 @@ enum lis2dw12_fmode {
 	LIS2DW12_FIFO_CONT_MODE = 6
 };
 
-#define LIS2DW12_FIFO_THRESHOLD_MASK	0x1f
+#define LIS2DW12_FIFO_THRESHOLD_MASK 0x1f
 
-#define LIS2DW12_FIFO_SAMPLES_ADDR	0x2f
-#define LIS2DW12_TAP_THS_X_ADDR		0x30
-#define LIS2DW12_TAP_THS_Y_ADDR		0x31
-#define LIS2DW12_TAP_THS_Z_ADDR		0x32
-#define LIS2DW12_INT_DUR_ADDR		0x33
+#define LIS2DW12_FIFO_SAMPLES_ADDR 0x2f
+#define LIS2DW12_TAP_THS_X_ADDR 0x30
+#define LIS2DW12_TAP_THS_Y_ADDR 0x31
+#define LIS2DW12_TAP_THS_Z_ADDR 0x32
+#define LIS2DW12_INT_DUR_ADDR 0x33
 
-#define LIS2DW12_WAKE_UP_THS_ADDR	0x34
+#define LIS2DW12_WAKE_UP_THS_ADDR 0x34
 
 /* TAP bits. */
-#define LIS2DW12_SINGLE_DOUBLE_TAP	0x80
+#define LIS2DW12_SINGLE_DOUBLE_TAP 0x80
 
 /* FIFO_SAMPLES bits. */
-#define LIS2DW12_FIFO_DIFF_MASK		0x3f
-#define LIS2DW12_FIFO_OVR_MASK		0x40
-#define LIS2DW12_FIFO_FTH_MASK		0x80
+#define LIS2DW12_FIFO_DIFF_MASK 0x3f
+#define LIS2DW12_FIFO_OVR_MASK 0x40
+#define LIS2DW12_FIFO_FTH_MASK 0x80
 
-#define LIS2DW12_ABS_INT_CFG_ADDR	0x3f
+#define LIS2DW12_ABS_INT_CFG_ADDR 0x3f
 
 /* INT Configuration bits. */
-#define LIS2DW12_DRDY_PULSED		0x80
-#define LIS2DW12_INT2_ON_INT1		0x40
-#define LIS2DW12_INT_ENABLE		0x20
+#define LIS2DW12_DRDY_PULSED 0x80
+#define LIS2DW12_INT2_ON_INT1 0x40
+#define LIS2DW12_INT_ENABLE 0x20
 
 /* Alias Registers/Masks. */
-#define LIS2DW12_ACC_ODR_ADDR		LIS2DW12_CTRL1_ADDR
-#define LIS2DW12_ACC_ODR_MASK		0xf0
+#define LIS2DW12_ACC_ODR_ADDR LIS2DW12_CTRL1_ADDR
+#define LIS2DW12_ACC_ODR_MASK 0xf0
 
-#define LIS2DW12_ACC_MODE_ADDR		LIS2DW12_CTRL1_ADDR
-#define LIS2DW12_ACC_MODE_MASK		0x0c
+#define LIS2DW12_ACC_MODE_ADDR LIS2DW12_CTRL1_ADDR
+#define LIS2DW12_ACC_MODE_MASK 0x0c
 
 /* Power mode selection. */
 enum lis2sw12_mode {
@@ -103,8 +103,8 @@ enum lis2sw12_mode {
 	LIS2DW12_LOW_POWER_LIST_NUM
 };
 
-#define LIS2DW12_ACC_LPMODE_ADDR	LIS2DW12_CTRL1_ADDR
-#define LIS2DW12_ACC_LPMODE_MASK	0x03
+#define LIS2DW12_ACC_LPMODE_ADDR LIS2DW12_CTRL1_ADDR
+#define LIS2DW12_ACC_LPMODE_MASK 0x03
 
 /*
  * Low power mode selection.
@@ -119,39 +119,39 @@ enum lis2sw12_lpmode {
 	LIS2DW12_LOW_POWER_MODE_LIST_NUM
 };
 
-#define LIS2DW12_BDU_ADDR		LIS2DW12_CTRL2_ADDR
-#define LIS2DW12_BDU_MASK		0x08
+#define LIS2DW12_BDU_ADDR LIS2DW12_CTRL2_ADDR
+#define LIS2DW12_BDU_MASK 0x08
 
-#define LIS2DW12_SOFT_RESET_ADDR	LIS2DW12_CTRL2_ADDR
-#define LIS2DW12_SOFT_RESET_MASK	0x40
+#define LIS2DW12_SOFT_RESET_ADDR LIS2DW12_CTRL2_ADDR
+#define LIS2DW12_SOFT_RESET_MASK 0x40
 
-#define LIS2DW12_BOOT_ADDR		LIS2DW12_CTRL2_ADDR
-#define LIS2DW12_BOOT_MASK		0x80
+#define LIS2DW12_BOOT_ADDR LIS2DW12_CTRL2_ADDR
+#define LIS2DW12_BOOT_MASK 0x80
 
-#define LIS2DW12_LIR_ADDR		LIS2DW12_CTRL3_ADDR
-#define LIS2DW12_LIR_MASK		0x10
+#define LIS2DW12_LIR_ADDR LIS2DW12_CTRL3_ADDR
+#define LIS2DW12_LIR_MASK 0x10
 
-#define LIS2DW12_H_ACTIVE_ADDR		LIS2DW12_CTRL3_ADDR
-#define LIS2DW12_H_ACTIVE_MASK		0x08
+#define LIS2DW12_H_ACTIVE_ADDR LIS2DW12_CTRL3_ADDR
+#define LIS2DW12_H_ACTIVE_MASK 0x08
 
-#define LIS2DW12_INT1_FTH_ADDR		LIS2DW12_CTRL4_ADDR
-#define LIS2DW12_INT1_FTH_MASK		LIS2DW12_INT1_FTH
+#define LIS2DW12_INT1_FTH_ADDR LIS2DW12_CTRL4_ADDR
+#define LIS2DW12_INT1_FTH_MASK LIS2DW12_INT1_FTH
 
-#define LIS2DW12_INT1_TAP_ADDR		LIS2DW12_CTRL4_ADDR
-#define LIS2DW12_INT1_DTAP_MASK		0x08
-#define LIS2DW12_INT1_STAP_MASK		0x40
+#define LIS2DW12_INT1_TAP_ADDR LIS2DW12_CTRL4_ADDR
+#define LIS2DW12_INT1_DTAP_MASK 0x08
+#define LIS2DW12_INT1_STAP_MASK 0x40
 
-#define LIS2DW12_INT1_D_TAP_EN		LIS2DW12_INT1_DTAP_MASK
+#define LIS2DW12_INT1_D_TAP_EN LIS2DW12_INT1_DTAP_MASK
 
-#define LIS2DW12_STATUS_TAP		LIS2DW12_STS_DRDY_UP
-#define LIS2DW12_SINGLE_TAP		LIS2DW12_SINGLE_TAP_UP
-#define LIS2DW12_DOUBLE_TAP		LIS2DW12_DOUBLE_TAP_UP
+#define LIS2DW12_STATUS_TAP LIS2DW12_STS_DRDY_UP
+#define LIS2DW12_SINGLE_TAP LIS2DW12_SINGLE_TAP_UP
+#define LIS2DW12_DOUBLE_TAP LIS2DW12_DOUBLE_TAP_UP
 
-#define LIS2DW12_INT2_ON_INT1_ADDR	LIS2DW12_ABS_INT_CFG_ADDR
-#define LIS2DW12_INT2_ON_INT1_MASK	LIS2DW12_INT2_ON_INT1
+#define LIS2DW12_INT2_ON_INT1_ADDR LIS2DW12_ABS_INT_CFG_ADDR
+#define LIS2DW12_INT2_ON_INT1_MASK LIS2DW12_INT2_ON_INT1
 
-#define LIS2DW12_DRDY_PULSED_ADDR	LIS2DW12_ABS_INT_CFG_ADDR
-#define LIS2DW12_DRDY_PULSED_MASK	LIS2DW12_DRDY_PULSED
+#define LIS2DW12_DRDY_PULSED_ADDR LIS2DW12_ABS_INT_CFG_ADDR
+#define LIS2DW12_DRDY_PULSED_MASK LIS2DW12_DRDY_PULSED
 
 /* Acc data rate for HR mode. */
 enum lis2dw12_odr {
@@ -168,8 +168,8 @@ enum lis2dw12_odr {
 };
 
 /* Full scale range registers. */
-#define LIS2DW12_FS_ADDR		LIS2DW12_CTRL6_ADDR
-#define LIS2DW12_FS_MASK		0x30
+#define LIS2DW12_FS_ADDR LIS2DW12_CTRL6_ADDR
+#define LIS2DW12_FS_MASK 0x30
 
 /* Acc FS value. */
 enum lis2dw12_fs {
@@ -180,42 +180,39 @@ enum lis2dw12_fs {
 	LIS2DW12_FS_LIST_NUM
 };
 
-#define LIS2DW12_ACCEL_FS_MAX_VAL	16
+#define LIS2DW12_ACCEL_FS_MAX_VAL 16
 
 /* Acc Gain value. */
-#define LIS2DW12_FS_2G_GAIN		3904
-#define LIS2DW12_FS_4G_GAIN		(LIS2DW12_FS_2G_GAIN << 1)
-#define LIS2DW12_FS_8G_GAIN		(LIS2DW12_FS_2G_GAIN << 2)
-#define LIS2DW12_FS_16G_GAIN		(LIS2DW12_FS_2G_GAIN << 3)
+#define LIS2DW12_FS_2G_GAIN 3904
+#define LIS2DW12_FS_4G_GAIN (LIS2DW12_FS_2G_GAIN << 1)
+#define LIS2DW12_FS_8G_GAIN (LIS2DW12_FS_2G_GAIN << 2)
+#define LIS2DW12_FS_16G_GAIN (LIS2DW12_FS_2G_GAIN << 3)
 
 /* FS Full Scale value from Gain. */
 #define LIS2DW12_GAIN_FS(_gain) \
 	(2 << (31 - __builtin_clz(_gain / LIS2DW12_FS_2G_GAIN)))
 
 /* Gain value from selected Full Scale. */
-#define LIS2DW12_FS_GAIN(_fs) \
-	(LIS2DW12_FS_2G_GAIN << (30 - __builtin_clz(_fs)))
+#define LIS2DW12_FS_GAIN(_fs) (LIS2DW12_FS_2G_GAIN << (30 - __builtin_clz(_fs)))
 
 /* Reg value from Full Scale. */
-#define LIS2DW12_FS_REG(_fs) \
-	(30 - __builtin_clz(_fs))
+#define LIS2DW12_FS_REG(_fs) (30 - __builtin_clz(_fs))
 
 /* Normalized FS value from Full Scale. */
-#define LIS2DW12_NORMALIZE_FS(_fs) \
-	(1 << (30 - __builtin_clz(_fs)))
+#define LIS2DW12_NORMALIZE_FS(_fs) (1 << (30 - __builtin_clz(_fs)))
 
 /*
  * Sensor resolution in number of bits.
  * Sensor driver support 14 bits resolution.
  * TODO: Support all "LP Power Mode" (res. 12/14 bits).
  */
-#define LIS2DW12_RESOLUTION		14
+#define LIS2DW12_RESOLUTION 14
 
 /** Maximum possible sample */
-#define LIS2DW12_SAMPLE_MAX		((1<<(LIS2DW12_RESOLUTION-1))-1)
+#define LIS2DW12_SAMPLE_MAX ((1 << (LIS2DW12_RESOLUTION - 1)) - 1)
 
 /** Smallest possible sample */
-#define LIS2DW12_SAMPLE_MIN		(-(1<<(LIS2DW12_RESOLUTION-1)))
+#define LIS2DW12_SAMPLE_MIN (-(1 << (LIS2DW12_RESOLUTION - 1)))
 
 #ifdef CONFIG_ZTEST
 int lis2dw12_set_power_mode(const struct motion_sensor_t *s,
diff --git a/driver/accelgyro_bmi160.c b/driver/accelgyro_bmi160.c
index 184e20c9f5..0a736760d0 100644
--- a/driver/accelgyro_bmi160.c
+++ b/driver/accelgyro_bmi160.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,6 +9,7 @@
  */
 
 #include "accelgyro.h"
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
 #include "accelgyro_bmi_common.h"
@@ -25,25 +26,22 @@
 #include "util.h"
 
 #define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args)
 
 #ifdef CONFIG_ACCELGYRO_BMI160_INT_EVENT
 #define ACCELGYRO_BMI160_INT_ENABLE
 #endif
 
-STATIC_IF(CONFIG_BMI_ORIENTATION_SENSOR) void irq_set_orientation(
-				struct motion_sensor_t *s,
-				int interrupt);
+STATIC_IF(CONFIG_BMI_ORIENTATION_SENSOR)
+void irq_set_orientation(struct motion_sensor_t *s, int interrupt);
 
 STATIC_IF(ACCELGYRO_BMI160_INT_ENABLE)
-	volatile uint32_t last_interrupt_timestamp;
+volatile uint32_t last_interrupt_timestamp;
 
-static int wakeup_time[] = {
-	[MOTIONSENSE_TYPE_ACCEL] = 4,
-	[MOTIONSENSE_TYPE_GYRO] = 80,
-	[MOTIONSENSE_TYPE_MAG] = 1
-};
+static int wakeup_time[] = { [MOTIONSENSE_TYPE_ACCEL] = 4,
+			     [MOTIONSENSE_TYPE_GYRO] = 80,
+			     [MOTIONSENSE_TYPE_MAG] = 1 };
 
 /**
  * Control access to the compass on the secondary i2c interface:
@@ -51,14 +49,12 @@ static int wakeup_time[] = {
  * 1: manual access, we can issue i2c to the compass
  * 0: data access: BMI160 gather data periodically from the compass.
  */
-static __maybe_unused int bmi160_sec_access_ctrl(
-		const int port,
-		const uint16_t i2c_spi_addr_flags,
-		const int enable)
+static __maybe_unused int
+bmi160_sec_access_ctrl(const int port, const uint16_t i2c_spi_addr_flags,
+		       const int enable)
 {
 	int mag_if_ctrl;
-	bmi_read8(port, i2c_spi_addr_flags,
-		  BMI160_MAG_IF_1, &mag_if_ctrl);
+	bmi_read8(port, i2c_spi_addr_flags, BMI160_MAG_IF_1, &mag_if_ctrl);
 	if (enable) {
 		mag_if_ctrl |= BMI160_MAG_MANUAL_EN;
 		mag_if_ctrl &= ~BMI160_MAG_READ_BURST_MASK;
@@ -68,42 +64,36 @@ static __maybe_unused int bmi160_sec_access_ctrl(
 		mag_if_ctrl &= ~BMI160_MAG_READ_BURST_MASK;
 		mag_if_ctrl |= BMI160_MAG_READ_BURST_8;
 	}
-	return bmi_write8(port, i2c_spi_addr_flags,
-			  BMI160_MAG_IF_1, mag_if_ctrl);
+	return bmi_write8(port, i2c_spi_addr_flags, BMI160_MAG_IF_1,
+			  mag_if_ctrl);
 }
 
 /**
  * Read register from compass.
  * Assuming we are in manual access mode, read compass i2c register.
  */
-int bmi160_sec_raw_read8(const int port,
-			 const uint16_t i2c_spi_addr_flags,
+int bmi160_sec_raw_read8(const int port, const uint16_t i2c_spi_addr_flags,
 			 const uint8_t reg, int *data_ptr)
 {
 	/* Only read 1 bytes */
-	bmi_write8(port, i2c_spi_addr_flags,
-		   BMI160_MAG_I2C_READ_ADDR, reg);
-	return bmi_read8(port, i2c_spi_addr_flags,
-			 BMI160_MAG_I2C_READ_DATA, data_ptr);
+	bmi_write8(port, i2c_spi_addr_flags, BMI160_MAG_I2C_READ_ADDR, reg);
+	return bmi_read8(port, i2c_spi_addr_flags, BMI160_MAG_I2C_READ_DATA,
+			 data_ptr);
 }
 
 /**
  * Write register from compass.
  * Assuming we are in manual access mode, write to compass i2c register.
  */
-int bmi160_sec_raw_write8(const int port,
-			  const uint16_t i2c_spi_addr_flags,
+int bmi160_sec_raw_write8(const int port, const uint16_t i2c_spi_addr_flags,
 			  const uint8_t reg, int data)
 {
-	bmi_write8(port, i2c_spi_addr_flags,
-		   BMI160_MAG_I2C_WRITE_DATA, data);
-	return bmi_write8(port, i2c_spi_addr_flags,
-			  BMI160_MAG_I2C_WRITE_ADDR, reg);
+	bmi_write8(port, i2c_spi_addr_flags, BMI160_MAG_I2C_WRITE_DATA, data);
+	return bmi_write8(port, i2c_spi_addr_flags, BMI160_MAG_I2C_WRITE_ADDR,
+			  reg);
 }
 
-static int set_data_rate(const struct motion_sensor_t *s,
-				int rate,
-				int rnd)
+static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
 {
 	int ret, normalized_rate;
 	uint8_t reg_val;
@@ -115,8 +105,7 @@ static int set_data_rate(const struct motion_sensor_t *s,
 			bmi_enable_fifo(s, 0);
 
 		/* go to suspend mode */
-		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-				 BMI160_CMD_REG,
+		ret = bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_CMD_REG,
 				 BMI160_CMD_MODE_SUSPEND(s->type));
 		msleep(3);
 		data->odr = 0;
@@ -130,8 +119,7 @@ static int set_data_rate(const struct motion_sensor_t *s,
 		return ret;
 	} else if (data->odr == 0) {
 		/* back from suspend mode. */
-		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-				 BMI160_CMD_REG,
+		ret = bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_CMD_REG,
 				 BMI160_CMD_MODE_NORMAL(s->type));
 		msleep(wakeup_time[s->type]);
 	}
@@ -146,8 +134,7 @@ static int set_data_rate(const struct motion_sensor_t *s,
 	 */
 	mutex_lock(s->mutex);
 
-	ret = bmi_set_reg8(s, BMI_CONF_REG(s->type),
-			   reg_val, BMI_ODR_MASK);
+	ret = bmi_set_reg8(s, BMI_CONF_REG(s->type), reg_val, BMI_ODR_MASK);
 	if (ret != EC_SUCCESS)
 		goto accel_cleanup;
 
@@ -165,9 +152,9 @@ static int set_data_rate(const struct motion_sensor_t *s,
 		 * for at least MIN_BATCH_WINDOW_US.
 		 * Given odr is in mHz, multiply by 1000x
 		 */
-		moc->batch_size = MAX(
-			MAG_CAL_MIN_BATCH_SIZE,
-			(data->odr * 1000) / (MAG_CAL_MIN_BATCH_WINDOW_US));
+		moc->batch_size =
+			MAX(MAG_CAL_MIN_BATCH_SIZE,
+			    (data->odr * 1000) / (MAG_CAL_MIN_BATCH_WINDOW_US));
 		CPRINTS("Batch size: %d", moc->batch_size);
 	}
 
@@ -183,17 +170,16 @@ accel_cleanup:
 	return ret;
 }
 
-static int set_offset(const struct motion_sensor_t *s,
-			const int16_t *offset,
-			int16_t    temp)
+static int set_offset(const struct motion_sensor_t *s, const int16_t *offset,
+		      int16_t temp)
 {
 	int ret, val98;
 	intv3_t v = { offset[X], offset[Y], offset[Z] };
 
 	rotate_inv(v, *s->rot_standard_ref, v);
 
-	ret = bmi_read8(s->port, s->i2c_spi_addr_flags,
-			BMI160_OFFSET_EN_GYR98, &val98);
+	ret = bmi_read8(s->port, s->i2c_spi_addr_flags, BMI160_OFFSET_EN_GYR98,
+			&val98);
 	if (ret != 0)
 		return ret;
 
@@ -258,8 +244,8 @@ static int perform_calib(struct motion_sensor_t *s, int enable)
 		else
 			val = BMI160_FOC_ACC_MINUS_1G;
 		val = (BMI160_FOC_ACC_0G << BMI160_FOC_ACC_X_OFFSET) |
-			(BMI160_FOC_ACC_0G << BMI160_FOC_ACC_Y_OFFSET) |
-			(val << BMI160_FOC_ACC_Z_OFFSET);
+		      (BMI160_FOC_ACC_0G << BMI160_FOC_ACC_Y_OFFSET) |
+		      (val << BMI160_FOC_ACC_Z_OFFSET);
 		en_flag = BMI160_OFFSET_ACC_EN;
 		/*
 		 * Temporary set range to minimum to run calibration with
@@ -285,12 +271,11 @@ static int perform_calib(struct motion_sensor_t *s, int enable)
 		/* Unreachable due to sensor type check above. */
 		ASSERT(false);
 		return EC_RES_INVALID_PARAM;
-	/* LCOV_EXCL_STOP */
+		/* LCOV_EXCL_STOP */
 	}
-	ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-			 BMI160_FOC_CONF, val);
-	ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-			 BMI160_CMD_REG, BMI160_CMD_START_FOC);
+	ret = bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_FOC_CONF, val);
+	ret = bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_CMD_REG,
+			 BMI160_CMD_START_FOC);
 	deadline.val = get_time().val + timeout.val;
 	do {
 		if (timestamp_expired(deadline, NULL)) {
@@ -298,8 +283,8 @@ static int perform_calib(struct motion_sensor_t *s, int enable)
 			goto end_perform_calib;
 		}
 		msleep(50);
-		ret = bmi_read8(s->port, s->i2c_spi_addr_flags,
-				BMI160_STATUS, &status);
+		ret = bmi_read8(s->port, s->i2c_spi_addr_flags, BMI160_STATUS,
+				&status);
 		if (ret != EC_SUCCESS)
 			goto end_perform_calib;
 	} while ((status & BMI160_FOC_RDY) == 0);
@@ -319,8 +304,7 @@ end_perform_calib:
  */
 #ifdef CONFIG_GESTURE_HOST_DETECTION
 static int manage_activity(const struct motion_sensor_t *s,
-			   enum motionsensor_activity activity,
-			   int enable,
+			   enum motionsensor_activity activity, int enable,
 			   const struct ec_motion_sense_activity *param)
 {
 	int ret;
@@ -332,23 +316,23 @@ static int manage_activity(const struct motion_sensor_t *s,
 		if (enable) {
 			/* We should use parameters from caller */
 			bmi_write8(s->port, s->i2c_spi_addr_flags,
-				BMI160_INT_MOTION_3,
-				BMI160_MOTION_PROOF_TIME(
-					CONFIG_GESTURE_SIGMO_PROOF_MS) <<
-				BMI160_MOTION_PROOF_OFF |
-				BMI160_MOTION_SKIP_TIME(
-					CONFIG_GESTURE_SIGMO_SKIP_MS) <<
-				BMI160_MOTION_SKIP_OFF |
-				BMI160_MOTION_SIG_MOT_SEL);
+				   BMI160_INT_MOTION_3,
+				   BMI160_MOTION_PROOF_TIME(
+					   CONFIG_GESTURE_SIGMO_PROOF_MS)
+						   << BMI160_MOTION_PROOF_OFF |
+					   BMI160_MOTION_SKIP_TIME(
+						   CONFIG_GESTURE_SIGMO_SKIP_MS)
+						   << BMI160_MOTION_SKIP_OFF |
+					   BMI160_MOTION_SIG_MOT_SEL);
 			bmi_write8(s->port, s->i2c_spi_addr_flags,
-				BMI160_INT_MOTION_1,
-				BMI160_MOTION_TH(s,
-					CONFIG_GESTURE_SIGMO_THRES_MG));
+				   BMI160_INT_MOTION_1,
+				   BMI160_MOTION_TH(
+					   s, CONFIG_GESTURE_SIGMO_THRES_MG));
 		}
 		ret = bmi_enable_reg8(s, BMI160_INT_EN_0,
 				      BMI160_INT_ANYMO_X_EN |
-				      BMI160_INT_ANYMO_Y_EN |
-				      BMI160_INT_ANYMO_Z_EN,
+					      BMI160_INT_ANYMO_Y_EN |
+					      BMI160_INT_ANYMO_Z_EN,
 				      enable);
 		if (ret)
 			ret = EC_RES_UNAVAILABLE;
@@ -358,8 +342,7 @@ static int manage_activity(const struct motion_sensor_t *s,
 #ifdef CONFIG_GESTURE_SENSOR_DOUBLE_TAP
 	case MOTIONSENSE_ACTIVITY_DOUBLE_TAP: {
 		/* Set double tap interrupt */
-		ret = bmi_enable_reg8(s, BMI160_INT_EN_0,
-				      BMI160_INT_D_TAP_EN,
+		ret = bmi_enable_reg8(s, BMI160_INT_EN_0, BMI160_INT_D_TAP_EN,
 				      enable);
 		if (ret)
 			ret = EC_RES_UNAVAILABLE;
@@ -382,6 +365,13 @@ static int manage_activity(const struct motion_sensor_t *s,
 }
 #endif
 
+#ifdef CONFIG_BODY_DETECTION
+static int get_rms_noise(const struct motion_sensor_t *s)
+{
+	return bmi_get_rms_noise(s, BMI160_ACCEL_RMS_NOISE_100HZ);
+}
+#endif
+
 /** Requires that the passed sensor `*s` is an accelerometer */
 static __maybe_unused int
 config_accel_interrupt(const struct motion_sensor_t *s)
@@ -389,18 +379,18 @@ config_accel_interrupt(const struct motion_sensor_t *s)
 	int ret, tmp;
 
 	mutex_lock(s->mutex);
-	bmi_write8(s->port, s->i2c_spi_addr_flags,
-		   BMI160_CMD_REG, BMI160_CMD_FIFO_FLUSH);
-	bmi_write8(s->port, s->i2c_spi_addr_flags,
-		   BMI160_CMD_REG, BMI160_CMD_INT_RESET);
+	bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_CMD_REG,
+		   BMI160_CMD_FIFO_FLUSH);
+	bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_CMD_REG,
+		   BMI160_CMD_INT_RESET);
 
 	if (IS_ENABLED(CONFIG_GESTURE_SENSOR_DOUBLE_TAP)) {
-		bmi_write8(s->port, s->i2c_spi_addr_flags,
-				BMI160_INT_TAP_0,
-				BMI160_TAP_DUR(s, CONFIG_GESTURE_TAP_MAX_INTERSTICE_T));
+		bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_INT_TAP_0,
+			   BMI160_TAP_DUR(s,
+					  CONFIG_GESTURE_TAP_MAX_INTERSTICE_T));
 		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-				BMI160_INT_TAP_1,
-				BMI160_TAP_TH(s, CONFIG_GESTURE_TAP_THRES_MG));
+				 BMI160_INT_TAP_1,
+				 BMI160_TAP_TH(s, CONFIG_GESTURE_TAP_THRES_MG));
 	}
 	/* only use orientation sensor on the lid sensor */
 	if (IS_ENABLED(CONFIG_BMI_ORIENTATION_SENSOR) &&
@@ -415,17 +405,16 @@ config_accel_interrupt(const struct motion_sensor_t *s)
 
 	if (IS_ENABLED(CONFIG_ACCELGYRO_BMI160_INT2_OUTPUT)) {
 		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-				BMI160_INT_LATCH, BMI160_LATCH_5MS);
+				 BMI160_INT_LATCH, BMI160_LATCH_5MS);
 	} else {
 		/* Also, configure int2 as an external input. */
 		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-				BMI160_INT_LATCH,
-				BMI160_INT2_INPUT_EN | BMI160_LATCH_5MS);
+				 BMI160_INT_LATCH,
+				 BMI160_INT2_INPUT_EN | BMI160_LATCH_5MS);
 	}
 
 	/* configure int1 as an interrupt */
-	ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-			 BMI160_INT_OUT_CTRL,
+	ret = bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_INT_OUT_CTRL,
 			 BMI160_INT_CTRL(1, OUTPUT_EN));
 
 	/* Map activity interrupt to int 1 */
@@ -439,15 +428,14 @@ config_accel_interrupt(const struct motion_sensor_t *s)
 		/* enable orientation interrupt for lid sensor only */
 		tmp |= BMI160_INT_ORIENT;
 	}
-	ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-			 BMI160_INT_MAP_REG(1), tmp);
+	ret = bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_INT_MAP_REG(1),
+			 tmp);
 
 	if (IS_ENABLED(ACCELGYRO_BMI160_INT_ENABLE)) {
 		/* map fifo water mark to int 1 */
-		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-				 BMI160_INT_FIFO_MAP,
-				 BMI160_INT_MAP(1, FWM) |
-				 BMI160_INT_MAP(1, FFULL));
+		ret = bmi_write8(
+			s->port, s->i2c_spi_addr_flags, BMI160_INT_FIFO_MAP,
+			BMI160_INT_MAP(1, FWM) | BMI160_INT_MAP(1, FFULL));
 
 		/*
 		 * Configure fifo watermark to int whenever there's any data in
@@ -457,13 +445,13 @@ config_accel_interrupt(const struct motion_sensor_t *s)
 				 BMI160_FIFO_CONFIG_0, 1);
 		if (IS_ENABLED(CONFIG_ACCELGYRO_BMI160_INT2_OUTPUT))
 			ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-					BMI160_FIFO_CONFIG_1,
-					BMI160_FIFO_HEADER_EN);
+					 BMI160_FIFO_CONFIG_1,
+					 BMI160_FIFO_HEADER_EN);
 		else
 			ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-					BMI160_FIFO_CONFIG_1,
-					BMI160_FIFO_TAG_INT2_EN |
-					BMI160_FIFO_HEADER_EN);
+					 BMI160_FIFO_CONFIG_1,
+					 BMI160_FIFO_TAG_INT2_EN |
+						 BMI160_FIFO_HEADER_EN);
 
 		/* Set fifo*/
 		bmi_enable_reg8(s, BMI160_INT_EN_1,
@@ -475,17 +463,15 @@ config_accel_interrupt(const struct motion_sensor_t *s)
 
 #ifdef ACCELGYRO_BMI160_INT_ENABLE
 #ifdef CONFIG_BMI_ORIENTATION_SENSOR
-static void irq_set_orientation(struct motion_sensor_t *s,
-				int interrupt)
+static void irq_set_orientation(struct motion_sensor_t *s, int interrupt)
 {
-	int shifted_masked_orientation =
-		(interrupt >> 24) & BMI160_ORIENT_XY_MASK;
+	int shifted_masked_orientation = (interrupt >> 24) &
+					 BMI160_ORIENT_XY_MASK;
 	if (BMI_GET_DATA(s)->raw_orientation != shifted_masked_orientation) {
 		enum motionsensor_orientation orientation =
 			MOTIONSENSE_ORIENTATION_UNKNOWN;
 
-		BMI_GET_DATA(s)->raw_orientation =
-			shifted_masked_orientation;
+		BMI_GET_DATA(s)->raw_orientation = shifted_masked_orientation;
 
 		switch (shifted_masked_orientation) {
 		case BMI160_ORIENT_PORTRAIT:
@@ -509,7 +495,7 @@ static void irq_set_orientation(struct motion_sensor_t *s,
 		*motion_orientation_ptr(s) = orientation;
 	}
 }
-#endif  /* CONFIG_BMI_ORIENTATION_SENSOR */
+#endif /* CONFIG_BMI_ORIENTATION_SENSOR */
 
 /**
  * bmi160_interrupt - called when the sensor activates the interrupt line.
@@ -531,15 +517,14 @@ void bmi160_interrupt(enum gpio_signal signal)
  * For now, we just print out. We should set a bitmask motion sense code will
  * act upon.
  */
-static int irq_handler(struct motion_sensor_t *s,
-				      uint32_t *event)
+static int irq_handler(struct motion_sensor_t *s, uint32_t *event)
 {
 	uint32_t interrupt;
 	int8_t has_read_fifo = 0;
 	int rv;
 
 	if ((s->type != MOTIONSENSE_TYPE_ACCEL) ||
-			(!(*event & CONFIG_ACCELGYRO_BMI160_INT_EVENT)))
+	    (!(*event & CONFIG_ACCELGYRO_BMI160_INT_EVENT)))
 		return EC_ERROR_NOT_HANDLED;
 
 	do {
@@ -554,11 +539,11 @@ static int irq_handler(struct motion_sensor_t *s,
 		if (IS_ENABLED(CONFIG_GESTURE_SENSOR_DOUBLE_TAP) &&
 		    (interrupt & BMI160_D_TAP_INT))
 			*event |= TASK_EVENT_MOTION_ACTIVITY_INTERRUPT(
-					MOTIONSENSE_ACTIVITY_DOUBLE_TAP);
+				MOTIONSENSE_ACTIVITY_DOUBLE_TAP);
 		if (IS_ENABLED(CONFIG_GESTURE_SIGMO) &&
 		    (interrupt & BMI160_SIGMOT_INT))
 			*event |= TASK_EVENT_MOTION_ACTIVITY_INTERRUPT(
-					MOTIONSENSE_ACTIVITY_SIG_MOTION);
+				MOTIONSENSE_ACTIVITY_SIG_MOTION);
 		if (interrupt & (BMI160_FWM_INT | BMI160_FFULL_INT)) {
 			bmi_load_fifo(s, last_interrupt_timestamp);
 			has_read_fifo = 1;
@@ -572,26 +557,25 @@ static int irq_handler(struct motion_sensor_t *s,
 
 	return EC_SUCCESS;
 }
-#endif  /* ACCELGYRO_BMI160_INT_ENABLE */
+#endif /* ACCELGYRO_BMI160_INT_ENABLE */
 
 static int init(struct motion_sensor_t *s)
 {
 	int ret = 0, tmp, i;
 	struct accelgyro_saved_data_t *saved_data = BMI_GET_SAVED_DATA(s);
 
-	ret = bmi_read8(s->port, s->i2c_spi_addr_flags,
-			BMI160_CHIP_ID, &tmp);
+	ret = bmi_read8(s->port, s->i2c_spi_addr_flags, BMI160_CHIP_ID, &tmp);
 	if (ret)
 		return EC_ERROR_UNKNOWN;
 
 	if (tmp != BMI160_CHIP_ID_MAJOR && tmp != BMI168_CHIP_ID_MAJOR) {
 		/* The device may be lock on paging mode. Try to unlock it. */
-		bmi_write8(s->port, s->i2c_spi_addr_flags,
-			   BMI160_CMD_REG, BMI160_CMD_EXT_MODE_EN_B0);
-		bmi_write8(s->port, s->i2c_spi_addr_flags,
-			   BMI160_CMD_REG, BMI160_CMD_EXT_MODE_EN_B1);
-		bmi_write8(s->port, s->i2c_spi_addr_flags,
-			   BMI160_CMD_REG, BMI160_CMD_EXT_MODE_EN_B2);
+		bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_CMD_REG,
+			   BMI160_CMD_EXT_MODE_EN_B0);
+		bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_CMD_REG,
+			   BMI160_CMD_EXT_MODE_EN_B1);
+		bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_CMD_REG,
+			   BMI160_CMD_EXT_MODE_EN_B2);
 		bmi_write8(s->port, s->i2c_spi_addr_flags,
 			   BMI160_CMD_EXT_MODE_ADDR, BMI160_CMD_PAGING_EN);
 		bmi_write8(s->port, s->i2c_spi_addr_flags,
@@ -599,17 +583,15 @@ static int init(struct motion_sensor_t *s)
 		return EC_ERROR_ACCESS_DENIED;
 	}
 
-
 	if (s->type == MOTIONSENSE_TYPE_ACCEL) {
 		struct bmi_drv_data_t *data = BMI_GET_DATA(s);
 
 		/* Reset the chip to be in a good state */
-		bmi_write8(s->port, s->i2c_spi_addr_flags,
-			   BMI160_CMD_REG, BMI160_CMD_SOFT_RESET);
+		bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_CMD_REG,
+			   BMI160_CMD_SOFT_RESET);
 		msleep(1);
 		data->flags &= ~(BMI_FLAG_SEC_I2C_ENABLED |
-				(BMI_FIFO_ALL_MASK <<
-				 BMI_FIFO_FLAG_OFFSET));
+				 (BMI_FIFO_ALL_MASK << BMI_FIFO_FLAG_OFFSET));
 		if (IS_ENABLED(CONFIG_GESTURE_HOST_DETECTION)) {
 			data->enabled_activities = 0;
 			data->disabled_activities = 0;
@@ -621,8 +603,8 @@ static int init(struct motion_sensor_t *s)
 					BIT(MOTIONSENSE_ACTIVITY_DOUBLE_TAP);
 		}
 		/* To avoid gyro wakeup */
-		bmi_write8(s->port, s->i2c_spi_addr_flags,
-			   BMI160_PMU_TRIGGER, 0);
+		bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_PMU_TRIGGER,
+			   0);
 	}
 
 #ifdef CONFIG_BMI_SEC_I2C
@@ -633,8 +615,8 @@ static int init(struct motion_sensor_t *s)
 		 * To be able to configure the real magnetometer, we must set
 		 * the BMI160 magnetometer part (a pass through) in normal mode.
 		 */
-		bmi_write8(s->port, s->i2c_spi_addr_flags,
-			   BMI160_CMD_REG, BMI160_CMD_MODE_NORMAL(s->type));
+		bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_CMD_REG,
+			   BMI160_CMD_MODE_NORMAL(s->type));
 		msleep(wakeup_time[s->type]);
 
 		if ((data->flags & BMI_FLAG_SEC_I2C_ENABLED) == 0) {
@@ -670,21 +652,18 @@ static int init(struct motion_sensor_t *s)
 				  BMI160_CMD_EXT_MODE_ADDR, &ext_page_reg);
 
 			/* Set the i2c address of the compass */
-			ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-					 BMI160_MAG_IF_0,
-					 I2C_STRIP_FLAGS(
-					     CONFIG_ACCELGYRO_SEC_ADDR_FLAGS)
-					 << 1);
+			ret = bmi_write8(
+				s->port, s->i2c_spi_addr_flags, BMI160_MAG_IF_0,
+				I2C_STRIP_FLAGS(CONFIG_ACCELGYRO_SEC_ADDR_FLAGS)
+					<< 1);
 
 			/* Enable the secondary interface as I2C */
-			ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-					 BMI160_IF_CONF,
-					 BMI160_IF_MODE_AUTO_I2C <<
-					     BMI160_IF_MODE_OFF);
+			ret = bmi_write8(
+				s->port, s->i2c_spi_addr_flags, BMI160_IF_CONF,
+				BMI160_IF_MODE_AUTO_I2C << BMI160_IF_MODE_OFF);
 			data->flags |= BMI_FLAG_SEC_I2C_ENABLED;
 		}
 
-
 		bmi160_sec_access_ctrl(s->port, s->i2c_spi_addr_flags, 1);
 
 		ret = bmm150_init(s);
@@ -746,7 +725,7 @@ const struct accelgyro_drv bmi160_drv = {
 	.list_activities = bmi_list_activities,
 #endif
 #ifdef CONFIG_BODY_DETECTION
-	.get_rms_noise = bmi_get_rms_noise,
+	.get_rms_noise = get_rms_noise,
 #endif
 };
 
diff --git a/driver/accelgyro_bmi260.c b/driver/accelgyro_bmi260.c
index cf2b019cb2..f0b16be4d5 100644
--- a/driver/accelgyro_bmi260.c
+++ b/driver/accelgyro_bmi260.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,6 +9,7 @@
  */
 
 #include "accelgyro.h"
+#include "builtin/assert.h"
 #include "console.h"
 #include "accelgyro_bmi_common.h"
 #include "accelgyro_bmi260.h"
@@ -23,7 +24,6 @@
 #include "util.h"
 #include "watchdog.h"
 
-
 #ifdef CONFIG_ACCELGYRO_BMI260_INT_EVENT
 #define ACCELGYRO_BMI260_INT_ENABLE
 #endif
@@ -37,52 +37,43 @@
 #include "bmi260/accelgyro_bmi260_config_tbin.h"
 #endif /* CONFIG_ACCELGYRO_BMI260 */
 
-
 #define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args)
 
 STATIC_IF(ACCELGYRO_BMI260_INT_ENABLE)
-	volatile uint32_t last_interrupt_timestamp;
+volatile uint32_t last_interrupt_timestamp;
 
 /*
  * The gyro start-up time is 45ms in normal mode
  *                            2ms in fast start-up mode
  */
-static int wakeup_time[] = {
-	[MOTIONSENSE_TYPE_ACCEL] = 2,
-	[MOTIONSENSE_TYPE_GYRO] = 45,
-	[MOTIONSENSE_TYPE_MAG] = 1
-};
+static int wakeup_time[] = { [MOTIONSENSE_TYPE_ACCEL] = 2,
+			     [MOTIONSENSE_TYPE_GYRO] = 45,
+			     [MOTIONSENSE_TYPE_MAG] = 1 };
 
 static int enable_sensor(const struct motion_sensor_t *s, int enable)
 {
 	int ret;
 
-	ret = bmi_enable_reg8(s, BMI260_PWR_CTRL,
-			      BMI260_PWR_EN(s->type),
+	ret = bmi_enable_reg8(s, BMI260_PWR_CTRL, BMI260_PWR_EN(s->type),
 			      enable);
 	if (ret)
 		return ret;
 
 	if (s->type == MOTIONSENSE_TYPE_GYRO) {
 		/* switch to performance mode */
-		ret = bmi_enable_reg8(s, BMI_CONF_REG(s->type),
-				      BMI260_FILTER_PERF |
-				      BMI260_GYR_NOISE_PERF,
-				      enable);
+		ret = bmi_enable_reg8(
+			s, BMI_CONF_REG(s->type),
+			BMI260_FILTER_PERF | BMI260_GYR_NOISE_PERF, enable);
 	} else {
 		ret = bmi_enable_reg8(s, BMI_CONF_REG(s->type),
-				      BMI260_FILTER_PERF,
-				      enable);
+				      BMI260_FILTER_PERF, enable);
 	}
 	return ret;
-
 }
 
-static int set_data_rate(const struct motion_sensor_t *s,
-			 int rate,
-			 int rnd)
+static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
 {
 	int ret, normalized_rate;
 	uint8_t reg_val;
@@ -106,8 +97,7 @@ static int set_data_rate(const struct motion_sensor_t *s,
 		msleep(wakeup_time[s->type]);
 	}
 
-	ret = bmi_get_normalized_rate(s, rate, rnd,
-				      &normalized_rate, &reg_val);
+	ret = bmi_get_normalized_rate(s, rate, rnd, &normalized_rate, &reg_val);
 	if (ret)
 		return ret;
 
@@ -117,8 +107,7 @@ static int set_data_rate(const struct motion_sensor_t *s,
 	 */
 	mutex_lock(s->mutex);
 
-	ret = bmi_set_reg8(s, BMI_CONF_REG(s->type),
-			   reg_val, BMI_ODR_MASK);
+	ret = bmi_set_reg8(s, BMI_CONF_REG(s->type), reg_val, BMI_ODR_MASK);
 	if (ret != EC_SUCCESS)
 		goto accel_cleanup;
 
@@ -136,21 +125,20 @@ accel_cleanup:
 	return ret;
 }
 
-static int set_offset(const struct motion_sensor_t *s,
-			const int16_t *offset,
-			int16_t    temp)
+static int set_offset(const struct motion_sensor_t *s, const int16_t *offset,
+		      int16_t temp)
 {
 	int ret, val98, val_nv_conf;
 	intv3_t v = { offset[X], offset[Y], offset[Z] };
 
 	rotate_inv(v, *s->rot_standard_ref, v);
 
-	ret = bmi_read8(s->port, s->i2c_spi_addr_flags,
-			BMI260_OFFSET_EN_GYR98, &val98);
+	ret = bmi_read8(s->port, s->i2c_spi_addr_flags, BMI260_OFFSET_EN_GYR98,
+			&val98);
 	if (ret)
 		return ret;
-	ret = bmi_read8(s->port, s->i2c_spi_addr_flags,
-			BMI260_NV_CONF, &val_nv_conf);
+	ret = bmi_read8(s->port, s->i2c_spi_addr_flags, BMI260_NV_CONF,
+			&val_nv_conf);
 	if (ret)
 		return ret;
 
@@ -160,8 +148,7 @@ static int set_offset(const struct motion_sensor_t *s,
 		if (ret != EC_SUCCESS)
 			return ret;
 
-		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-				 BMI260_NV_CONF,
+		ret = bmi_write8(s->port, s->i2c_spi_addr_flags, BMI260_NV_CONF,
 				 val_nv_conf | BMI260_ACC_OFFSET_EN);
 		break;
 	case MOTIONSENSE_TYPE_GYRO:
@@ -179,8 +166,15 @@ static int set_offset(const struct motion_sensor_t *s,
 	return ret;
 }
 
-static int wait_and_read_data(const struct motion_sensor_t *s,
-			      intv3_t v, int try_cnt, int msec)
+#ifdef CONFIG_BODY_DETECTION
+static int get_rms_noise(const struct motion_sensor_t *s)
+{
+	return bmi_get_rms_noise(s, BMI260_ACCEL_RMS_NOISE_100HZ);
+}
+#endif
+
+static int wait_and_read_data(const struct motion_sensor_t *s, intv3_t v,
+			      int try_cnt, int msec)
 {
 	uint8_t data[6];
 	int ret, status = 0;
@@ -188,8 +182,8 @@ static int wait_and_read_data(const struct motion_sensor_t *s,
 	/* Check if data is ready */
 	while (try_cnt && !(status & BMI260_DRDY_ACC)) {
 		msleep(msec);
-		ret = bmi_read8(s->port, s->i2c_spi_addr_flags,
-				BMI260_STATUS, &status);
+		ret = bmi_read8(s->port, s->i2c_spi_addr_flags, BMI260_STATUS,
+				&status);
 		if (ret)
 			return ret;
 		try_cnt -= 1;
@@ -197,18 +191,18 @@ static int wait_and_read_data(const struct motion_sensor_t *s,
 	if (!(status & BMI260_DRDY_ACC))
 		return EC_ERROR_TIMEOUT;
 	/* Read 6 bytes starting at xyz_reg */
-	ret = bmi_read_n(s->port, s->i2c_spi_addr_flags,
-			 bmi_get_xyz_reg(s), data, 6);
+	ret = bmi_read_n(s->port, s->i2c_spi_addr_flags, bmi_get_xyz_reg(s),
+			 data, 6);
 	bmi_normalize(s, v, data);
 	return ret;
 }
 
-static int calibrate_offset(const struct motion_sensor_t *s,
-			    int range, intv3_t target, int16_t *offset)
+static int calibrate_offset(const struct motion_sensor_t *s, int range,
+			    intv3_t target, int16_t *offset)
 {
 	int ret = EC_ERROR_UNKNOWN;
 	int i, n_sample = 32;
-	int data_diff[3] = {0};
+	int data_diff[3] = { 0 };
 
 	/* Manually offset compensation */
 	for (i = 0; i < n_sample; ++i) {
@@ -224,8 +218,9 @@ static int calibrate_offset(const struct motion_sensor_t *s,
 
 	/* The data LSB: 1000 * range / 32768 (mdps | mg)*/
 	for (i = X; i <= Z; ++i)
-		offset[i] -= ((int64_t)(data_diff[i] / n_sample) *
-			     1000 * range) >> 15;
+		offset[i] -=
+			((int64_t)(data_diff[i] / n_sample) * 1000 * range) >>
+			15;
 	return ret;
 }
 
@@ -234,7 +229,7 @@ static int perform_calib(struct motion_sensor_t *s, int enable)
 	int ret, rate;
 	int16_t temp;
 	int16_t offset[3];
-	intv3_t target = {0, 0, 0};
+	intv3_t target = { 0, 0, 0 };
 	/* Get sensor range for calibration*/
 	int range = s->current_range;
 
@@ -266,7 +261,7 @@ static int perform_calib(struct motion_sensor_t *s, int enable)
 		/* Unreachable due to sensor type check above. */
 		ASSERT(false);
 		break;
-	/* LCOV_EXCL_STOP */
+		/* LCOV_EXCL_STOP */
 	}
 
 	/* Get the calibrated offset */
@@ -296,52 +291,45 @@ static __maybe_unused int config_interrupt(const struct motion_sensor_t *s)
 	int ret;
 
 	mutex_lock(s->mutex);
-	bmi_write8(s->port, s->i2c_spi_addr_flags,
-		   BMI260_CMD_REG, BMI260_CMD_FIFO_FLUSH);
+	bmi_write8(s->port, s->i2c_spi_addr_flags, BMI260_CMD_REG,
+		   BMI260_CMD_FIFO_FLUSH);
 
 	/* configure int1 as an interrupt */
-	ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-			 BMI260_INT1_IO_CTRL,
+	ret = bmi_write8(s->port, s->i2c_spi_addr_flags, BMI260_INT1_IO_CTRL,
 			 BMI260_INT1_OUTPUT_EN);
 	if (IS_ENABLED(CONFIG_ACCELGYRO_BMI260_INT2_OUTPUT))
 		/* TODO(chingkang): Test it if we want int2 as an interrupt */
 		/* configure int2 as an interrupt */
 		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-				 BMI260_INT2_IO_CTRL,
-				 BMI260_INT2_OUTPUT_EN);
+				 BMI260_INT2_IO_CTRL, BMI260_INT2_OUTPUT_EN);
 	else
 		/* configure int2 as an external input. */
 		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-				 BMI260_INT2_IO_CTRL,
-				 BMI260_INT2_INPUT_EN);
+				 BMI260_INT2_IO_CTRL, BMI260_INT2_INPUT_EN);
 
 	/* map fifo water mark to int 1 */
-	ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-			 BMI260_INT_MAP_DATA,
+	ret = bmi_write8(s->port, s->i2c_spi_addr_flags, BMI260_INT_MAP_DATA,
 			 BMI260_INT_MAP_DATA_REG(1, FWM) |
-			 BMI260_INT_MAP_DATA_REG(1, FFULL));
+				 BMI260_INT_MAP_DATA_REG(1, FFULL));
 
 	/*
 	 * Configure fifo watermark to int whenever there's any data in
 	 * there
 	 */
-	ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-			 BMI260_FIFO_WTM_0, 1);
-	ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-			 BMI260_FIFO_WTM_1, 0);
+	ret = bmi_write8(s->port, s->i2c_spi_addr_flags, BMI260_FIFO_WTM_0, 1);
+	ret = bmi_write8(s->port, s->i2c_spi_addr_flags, BMI260_FIFO_WTM_1, 0);
 	if (IS_ENABLED(CONFIG_ACCELGYRO_BMI260_INT2_OUTPUT))
 		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-				 BMI260_FIFO_CONFIG_1,
-				 BMI260_FIFO_HEADER_EN);
+				 BMI260_FIFO_CONFIG_1, BMI260_FIFO_HEADER_EN);
 	else
 		ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
 				 BMI260_FIFO_CONFIG_1,
-				 (BMI260_FIFO_TAG_INT_LEVEL <<
-				  BMI260_FIFO_TAG_INT2_EN_OFFSET) |
-				 BMI260_FIFO_HEADER_EN);
+				 (BMI260_FIFO_TAG_INT_LEVEL
+				  << BMI260_FIFO_TAG_INT2_EN_OFFSET) |
+					 BMI260_FIFO_HEADER_EN);
 	/* disable FIFO sensortime frame */
-	ret = bmi_write8(s->port, s->i2c_spi_addr_flags,
-			BMI260_FIFO_CONFIG_0, 0);
+	ret = bmi_write8(s->port, s->i2c_spi_addr_flags, BMI260_FIFO_CONFIG_0,
+			 0);
 	mutex_unlock(s->mutex);
 	return ret;
 }
@@ -375,7 +363,7 @@ static int irq_handler(struct motion_sensor_t *s, uint32_t *event)
 	int rv;
 
 	if ((s->type != MOTIONSENSE_TYPE_ACCEL) ||
-			(!(*event & CONFIG_ACCELGYRO_BMI260_INT_EVENT)))
+	    (!(*event & CONFIG_ACCELGYRO_BMI260_INT_EVENT)))
 		return EC_ERROR_NOT_HANDLED;
 
 	do {
@@ -398,17 +386,17 @@ static int irq_handler(struct motion_sensor_t *s, uint32_t *event)
 
 	return EC_SUCCESS;
 }
-#endif  /* ACCELGYRO_BMI260_INT_ENABLE */
+#endif /* ACCELGYRO_BMI260_INT_ENABLE */
 
 /*
  * If the .init_rom section is not memory mapped, we need a static
  * buffer in RAM to access the BMI configuration data.
  */
 #ifdef CONFIG_CHIP_INIT_ROM_REGION
-#define BMI_RAM_BUFFER_SIZE		256
+#define BMI_RAM_BUFFER_SIZE 256
 static uint8_t bmi_ram_buffer[BMI_RAM_BUFFER_SIZE];
 #else
-#define BMI_RAM_BUFFER_SIZE		0
+#define BMI_RAM_BUFFER_SIZE 0
 static uint8_t *bmi_ram_buffer;
 #endif
 
@@ -464,8 +452,7 @@ static int bmi_config_load(const struct motion_sensor_t *s)
 
 	for (i = 0; i < bmi_config_tbin_len; i += burst_write_len) {
 		uint8_t addr[2];
-		const int len = MIN(burst_write_len,
-				    bmi_config_tbin_len - i);
+		const int len = MIN(burst_write_len, bmi_config_tbin_len - i);
 
 		addr[0] = (i / 2) & 0xF;
 		addr[1] = (i / 2) >> 4;
@@ -480,17 +467,17 @@ static int bmi_config_load(const struct motion_sensor_t *s)
 			 * data through a RAM buffer.
 			 */
 			ret = init_rom_copy((int)&bmi_config_tbin[i], len,
-				bmi_ram_buffer);
+					    bmi_ram_buffer);
 			if (ret)
 				break;
 
 			ret = bmi_write_n(s->port, s->i2c_spi_addr_flags,
-					  BMI260_INIT_DATA,
-					  bmi_ram_buffer, len);
+					  BMI260_INIT_DATA, bmi_ram_buffer,
+					  len);
 		} else {
 			ret = bmi_write_n(s->port, s->i2c_spi_addr_flags,
-					  BMI260_INIT_DATA,
-					  &bmi_config[i], len);
+					  BMI260_INIT_DATA, &bmi_config[i],
+					  len);
 		}
 
 		if (ret)
@@ -530,7 +517,7 @@ static int init_config(const struct motion_sensor_t *s)
 	for (i = 0; i < 15; ++i) {
 		msleep(10);
 		ret = bmi_read8(s->port, s->i2c_spi_addr_flags,
-			BMI260_INTERNAL_STATUS, &init_status);
+				BMI260_INTERNAL_STATUS, &init_status);
 		if (ret)
 			break;
 		init_status &= BMI260_MESSAGE_MASK;
@@ -547,8 +534,7 @@ static int init(struct motion_sensor_t *s)
 	int ret = 0, tmp, i;
 	struct accelgyro_saved_data_t *saved_data = BMI_GET_SAVED_DATA(s);
 
-	ret = bmi_read8(s->port, s->i2c_spi_addr_flags,
-			BMI260_CHIP_ID, &tmp);
+	ret = bmi_read8(s->port, s->i2c_spi_addr_flags, BMI260_CHIP_ID, &tmp);
 	if (ret)
 		return EC_ERROR_UNKNOWN;
 
@@ -567,20 +553,18 @@ static int init(struct motion_sensor_t *s)
 		return EC_ERROR_ACCESS_DENIED;
 	}
 
-
 	if (s->type == MOTIONSENSE_TYPE_ACCEL) {
 		struct bmi_drv_data_t *data = BMI_GET_DATA(s);
 
 		/* Reset the chip to be in a good state */
-		bmi_write8(s->port, s->i2c_spi_addr_flags,
-				 BMI260_CMD_REG, BMI260_CMD_SOFT_RESET);
+		bmi_write8(s->port, s->i2c_spi_addr_flags, BMI260_CMD_REG,
+			   BMI260_CMD_SOFT_RESET);
 		msleep(2);
 		if (init_config(s))
 			return EC_ERROR_INVALID_CONFIG;
 
 		data->flags &= ~(BMI_FLAG_SEC_I2C_ENABLED |
-				(BMI_FIFO_ALL_MASK <<
-				 BMI_FIFO_FLAG_OFFSET));
+				 (BMI_FIFO_ALL_MASK << BMI_FIFO_FLAG_OFFSET));
 	}
 
 	for (i = X; i <= Z; i++)
@@ -618,7 +602,7 @@ const struct accelgyro_drv bmi260_drv = {
 	.list_activities = bmi_list_activities,
 #endif
 #ifdef CONFIG_BODY_DETECTION
-	.get_rms_noise = bmi_get_rms_noise,
+	.get_rms_noise = get_rms_noise,
 #endif
 };
 
diff --git a/driver/accelgyro_bmi323.h b/driver/accelgyro_bmi323.h
index 544e9a4527..9b014448bd 100644
--- a/driver/accelgyro_bmi323.h
+++ b/driver/accelgyro_bmi323.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,6 +10,6 @@
 
 #include "accelgyro_bmi3xx.h"
 
-#define BMI323_CHIP_ID			0x43
+#define BMI323_CHIP_ID 0x43
 
 #endif /* __CROS_EC_ACCELGYRO_BMI323_H */
diff --git a/driver/accelgyro_bmi3xx.c b/driver/accelgyro_bmi3xx.c
index 6c14768708..cf2bd0b3a2 100644
--- a/driver/accelgyro_bmi3xx.c
+++ b/driver/accelgyro_bmi3xx.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,6 +11,7 @@
 #include "accelgyro.h"
 #include "accelgyro_bmi323.h"
 #include "accelgyro_bmi_common.h"
+#include "builtin/assert.h"
 #include "console.h"
 #include "hwtimer.h"
 #include "i2c.h"
@@ -28,15 +29,17 @@
 #endif
 
 #define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args)
+
+#define OFFSET_UPDATE_PER_TRY 10
 
 /* Sensor definition */
 STATIC_IF(CONFIG_BMI_ORIENTATION_SENSOR)
-	void irq_set_orientation(struct motion_sensor_t *s);
+void irq_set_orientation(struct motion_sensor_t *s);
 
 STATIC_IF(ACCELGYRO_BMI3XX_INT_ENABLE)
-	volatile uint32_t last_interrupt_timestamp;
+volatile uint32_t last_interrupt_timestamp;
 
 static inline int bmi3_read_n(const struct motion_sensor_t *s, const int reg,
 			      uint8_t *data_ptr, const int len)
@@ -61,7 +64,7 @@ static void irq_set_orientation(struct motion_sensor_t *s)
 	uint8_t orient_data;
 
 	enum motionsensor_orientation orientation =
-					MOTIONSENSE_ORIENTATION_UNKNOWN;
+		MOTIONSENSE_ORIENTATION_UNKNOWN;
 
 	RETURN_ERROR(bmi3_read_n(s, BMI3_FEATURE_EVENT_EXT, reg_data, 4));
 
@@ -94,7 +97,7 @@ static void irq_set_orientation(struct motion_sensor_t *s)
 	}
 }
 
-#endif  /* CONFIG_BMI_ORIENTATION_SENSOR */
+#endif /* CONFIG_BMI_ORIENTATION_SENSOR */
 
 /*
  * bmi3xx_interrupt - called when the sensor activates the interrupt line.
@@ -121,14 +124,14 @@ static int enable_fifo(const struct motion_sensor_t *s, int enable)
 		if (s->type == MOTIONSENSE_TYPE_ACCEL)
 			reg_data[3] |= BMI3_FIFO_ACC_EN;
 		else
-			reg_data[3] |=  BMI3_FIFO_GYR_EN;
+			reg_data[3] |= BMI3_FIFO_GYR_EN;
 
 		data->flags |= 1 << (s->type + BMI_FIFO_FLAG_OFFSET);
 	} else {
 		if (s->type == MOTIONSENSE_TYPE_ACCEL)
 			reg_data[3] &= ~BMI3_FIFO_ACC_EN;
 		else
-			reg_data[3] &=  ~BMI3_FIFO_GYR_EN;
+			reg_data[3] &= ~BMI3_FIFO_GYR_EN;
 
 		data->flags &= ~(1 << (s->type + BMI_FIFO_FLAG_OFFSET));
 	}
@@ -139,7 +142,7 @@ static int enable_fifo(const struct motion_sensor_t *s, int enable)
 static int config_interrupt(const struct motion_sensor_t *s)
 {
 	int ret;
-	uint8_t reg_data[6] = {0};
+	uint8_t reg_data[6] = { 0 };
 
 	if (s->type != MOTIONSENSE_TYPE_ACCEL)
 		return EC_SUCCESS;
@@ -162,8 +165,8 @@ static int config_interrupt(const struct motion_sensor_t *s)
 	reg_data[5] = BMI3_SET_BITS(reg_data[5], BMI3_FFULL_INT, BMI3_INT1);
 	if (IS_ENABLED(CONFIG_BMI_ORIENTATION_SENSOR)) {
 		/* Map orientation to INT1 pin */
-		reg_data[2] = BMI3_SET_BITS(reg_data[2], BMI3_ORIENT_INT,
-						BMI3_INT1);
+		reg_data[2] =
+			BMI3_SET_BITS(reg_data[2], BMI3_ORIENT_INT, BMI3_INT1);
 	}
 
 	ret = bmi3_write_n(s, BMI3_REG_INT_MAP1, &reg_data[2], 4);
@@ -186,8 +189,8 @@ static int config_interrupt(const struct motion_sensor_t *s)
 	reg_data[2] = BMI3_SET_BIT_POS0(reg_data[2], BMI3_INT1_LVL,
 					BMI3_INT_ACTIVE_LOW);
 
-	reg_data[2] = BMI3_SET_BITS(reg_data[2], BMI3_INT1_OD,
-				    BMI3_INT_PUSH_PULL);
+	reg_data[2] =
+		BMI3_SET_BITS(reg_data[2], BMI3_INT1_OD, BMI3_INT_PUSH_PULL);
 
 	reg_data[2] = BMI3_SET_BITS(reg_data[2], BMI3_INT1_OUTPUT_EN,
 				    BMI3_INT_OUTPUT_ENABLE);
@@ -287,17 +290,17 @@ static void bmi3_parse_fifo_data(struct motion_sensor_t *s,
 				rotate(v, *sens_output->rot_standard_ref, v);
 
 				if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
-					struct ec_response_motion_sensor_data vect;
+					struct ec_response_motion_sensor_data
+						vect;
 
 					vect.data[X] = v[X];
 					vect.data[Y] = v[Y];
 					vect.data[Z] = v[Z];
 					vect.flags = 0;
-					vect.sensor_num = sens_output -
-						motion_sensors;
-					motion_sense_fifo_stage_data(&vect,
-							sens_output, 3,
-							last_ts);
+					vect.sensor_num =
+						sens_output - motion_sensors;
+					motion_sense_fifo_stage_data(
+						&vect, sens_output, 3, last_ts);
 				} else {
 					motion_sense_push_raw_xyz(sens_output);
 				}
@@ -313,8 +316,7 @@ static void bmi3_parse_fifo_data(struct motion_sensor_t *s,
  * For now, we just print out. We should set a bitmask motion sense code will
  * act upon.
  */
-static int irq_handler(struct motion_sensor_t *s,
-		uint32_t *event)
+static int irq_handler(struct motion_sensor_t *s, uint32_t *event)
 {
 	bool has_read_fifo = false;
 	uint16_t int_status[2];
@@ -335,15 +337,15 @@ static int irq_handler(struct motion_sensor_t *s,
 			irq_set_orientation(s);
 
 		if ((int_status[1] &
-		    (BMI3_INT_STATUS_FWM | BMI3_INT_STATUS_FFULL)) == 0)
+		     (BMI3_INT_STATUS_FWM | BMI3_INT_STATUS_FFULL)) == 0)
 			break;
 
 		/* Get the FIFO fill level in words */
 		RETURN_ERROR(bmi3_read_n(s, BMI3_REG_FIFO_FILL_LVL,
 					 (uint8_t *)reg_data, 4));
 
-		reg_data[1] = BMI3_GET_BIT_POS0(reg_data[1],
-						BMI3_FIFO_FILL_LVL);
+		reg_data[1] =
+			BMI3_GET_BIT_POS0(reg_data[1], BMI3_FIFO_FILL_LVL);
 
 		/* Add space for the initial 16bit read. */
 		fifo_frame.available_fifo_len = reg_data[1] + 1;
@@ -354,16 +356,15 @@ static int irq_handler(struct motion_sensor_t *s,
 		 */
 		if (fifo_frame.available_fifo_len > ARRAY_SIZE(fifo_frame.data))
 			CPRINTS("unexpected large FIFO: %d",
-					fifo_frame.available_fifo_len);
+				fifo_frame.available_fifo_len);
 
 		fifo_frame.available_fifo_len =
 			MIN(fifo_frame.available_fifo_len,
-					ARRAY_SIZE(fifo_frame.data));
+			    ARRAY_SIZE(fifo_frame.data));
 		/* Read FIFO data */
-		RETURN_ERROR(bmi3_read_n(s, BMI3_REG_FIFO_DATA,
-					 (uint8_t *)fifo_frame.data,
-					 fifo_frame.available_fifo_len *
-					 sizeof(uint16_t)));
+		RETURN_ERROR(bmi3_read_n(
+			s, BMI3_REG_FIFO_DATA, (uint8_t *)fifo_frame.data,
+			fifo_frame.available_fifo_len * sizeof(uint16_t)));
 
 		bmi3_parse_fifo_data(s, &fifo_frame, last_interrupt_timestamp);
 		has_read_fifo = true;
@@ -381,50 +382,13 @@ static int read_temp(const struct motion_sensor_t *s, int *temp_ptr)
 	return EC_ERROR_UNIMPLEMENTED;
 }
 
-static int reset_offset(const struct motion_sensor_t *s, uint8_t offset_en)
-{
-	uint8_t offset_sel[2] = { BMI3_REG_UGAIN_OFF_SEL, 0 };
-	uint8_t reg_data[4] = { 0 };
-
-	/* Reset the existing offset values by setting the bits in DMA*/
-	RETURN_ERROR(bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX,
-				offset_sel, 2));
-
-	reg_data[0] = offset_en;
-	reg_data[1] = 0;
-
-	RETURN_ERROR(bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX_DATA,
-				reg_data, 2));
-
-	/* Update the offset change to the sensor engine */
-	reg_data[0] = (uint8_t)(BMI3_CMD_USR_GAIN_OFFS_UPDATE &
-				BMI3_SET_LOW_BYTE);
-	reg_data[1] = (uint8_t)((BMI3_CMD_USR_GAIN_OFFS_UPDATE &
-				 BMI3_SET_HIGH_BYTE) >> 8);
-	RETURN_ERROR(bmi3_write_n(s, BMI3_REG_CMD, reg_data, 2));
-
-	/* Delay time for offset update */
-	msleep(OFFSET_UPDATE_DELAY);
-
-	/* Read the configuration from the feature engine register */
-	RETURN_ERROR(bmi3_read_n(s, BMI3_FEATURE_IO_1, reg_data, 4));
-
-	if ((reg_data[3] & BMI3_UGAIN_OFFS_UPD_COMPLETE)
-		&& ((reg_data[2] & BMI3_FEATURE_IO_1_ERROR_MASK)
-			    == BMI3_FEATURE_IO_1_NO_ERROR)) {
-		return EC_SUCCESS;
-	}
-
-	return EC_ERROR_NOT_CALIBRATED;
-}
-
 int get_gyro_offset(const struct motion_sensor_t *s, intv3_t v)
 {
 	int i;
 	uint8_t reg_data[14] = { 0 };
 
 	/* Get the accel offset values */
-	RETURN_ERROR(bmi3_read_n(s, GYR_DP_OFF_X, reg_data, 14));
+	RETURN_ERROR(bmi3_read_n(s, BMI3_GYR_DP_OFF_X, reg_data, 14));
 
 	v[0] = ((uint16_t)(reg_data[3] << 8) | reg_data[2]) & 0x03FF;
 	v[1] = ((uint16_t)(reg_data[7] << 8) | reg_data[6]) & 0x03FF;
@@ -444,53 +408,23 @@ int get_gyro_offset(const struct motion_sensor_t *s, intv3_t v)
 static int write_gyro_offset(const struct motion_sensor_t *s, int *val)
 {
 	uint8_t reg_data[6] = { 0 };
-	uint8_t base_addr[2] = { BMI3_GYRO_OFFSET_ADDR, 0 };
-	uint8_t offset_sel[2] = { BMI3_REG_UGAIN_OFF_SEL, 0 };
-
-	/* Enable user gain/offset update*/
-	RETURN_ERROR(bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX,
-				    offset_sel, 2));
-	reg_data[0] = 0;
-	reg_data[1] = 0;
-	RETURN_ERROR(bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX_DATA,
-				    reg_data, 2));
-	/*
-	 * Set the user gyro offset base address to feature engine
-	 * transmission address to start DMA transaction
-	 */
-	RETURN_ERROR(bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX,
-				    base_addr, 2));
 
+	/* x-axis offset */
 	reg_data[0] = (uint8_t)(val[0] & BMI3_SET_LOW_BYTE);
 	reg_data[1] = (uint8_t)((val[0] & 0x0300) >> 8);
+	/* y-axis offset */
 	reg_data[2] = (uint8_t)(val[1] & BMI3_SET_LOW_BYTE);
 	reg_data[3] = (uint8_t)((val[1] & 0x0300) >> 8);
+	/* z-axis offset */
 	reg_data[4] = (uint8_t)(val[2] & BMI3_SET_LOW_BYTE);
 	reg_data[5] = (uint8_t)((val[2] & 0x0300) >> 8);
 
-	/* Set the configuration to the feature engine register */
-	RETURN_ERROR(bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX_DATA,
-				    reg_data, 6));
-
-	/* Update the offset to the sensor engine */
-	reg_data[0] = (uint8_t)(BMI3_CMD_USR_GAIN_OFFS_UPDATE &
-				 BMI3_SET_LOW_BYTE);
-	reg_data[1] = (uint8_t)((BMI3_CMD_USR_GAIN_OFFS_UPDATE &
-				 BMI3_SET_HIGH_BYTE) >> 8);
-	RETURN_ERROR(bmi3_write_n(s, BMI3_REG_CMD, reg_data, 2));
-
-	msleep(OFFSET_UPDATE_DELAY);
-
-	/* Read the configuration from the feature engine register */
-	RETURN_ERROR(bmi3_read_n(s, BMI3_FEATURE_IO_1, reg_data, 4));
-
-	if ((reg_data[3] & BMI3_UGAIN_OFFS_UPD_COMPLETE)
-		&& ((reg_data[2] & BMI3_FEATURE_IO_1_ERROR_MASK)
-			    == BMI3_FEATURE_IO_1_NO_ERROR)) {
-		return EC_SUCCESS;
-	}
+	/* Update the gyro data path offset registers */
+	RETURN_ERROR(bmi3_write_n(s, BMI3_GYR_DP_OFF_X, &reg_data[0], 2));
+	RETURN_ERROR(bmi3_write_n(s, BMI3_GYR_DP_OFF_Y, &reg_data[2], 2));
+	RETURN_ERROR(bmi3_write_n(s, BMI3_GYR_DP_OFF_Z, &reg_data[4], 2));
 
-	return EC_ERROR_NOT_CALIBRATED;
+	return EC_SUCCESS;
 }
 
 int set_gyro_offset(const struct motion_sensor_t *s, intv3_t v)
@@ -501,7 +435,7 @@ int set_gyro_offset(const struct motion_sensor_t *s, intv3_t v)
 
 	for (i = X; i <= Z; ++i) {
 		val[i] = round_divide((int64_t)v[i] * BMI_OFFSET_GYRO_DIV_MDS,
-					BMI_OFFSET_GYRO_MULTI_MDS);
+				      BMI3_OFFSET_GYR_MDPS);
 		if (val[i] > 511)
 			val[i] = 511;
 		if (val[i] < -512)
@@ -520,9 +454,6 @@ int set_gyro_offset(const struct motion_sensor_t *s, intv3_t v)
 	reg_data[3] = 0x00;
 	RETURN_ERROR(bmi3_write_n(s, BMI3_REG_ACC_CONF, reg_data, 4));
 
-	/* Reset the existing offset values */
-	RETURN_ERROR(reset_offset(s, 2));
-
 	/* Set the gyro offset in the sensor registers */
 	RETURN_ERROR(write_gyro_offset(s, val));
 
@@ -538,15 +469,15 @@ int get_accel_offset(const struct motion_sensor_t *s, intv3_t v)
 	uint8_t reg_data[14] = { 0 };
 
 	/* Get the accel offset values from user registers */
-	RETURN_ERROR(bmi3_read_n(s, ACC_DP_OFF_X, reg_data, 14));
+	RETURN_ERROR(bmi3_read_n(s, BMI3_ACC_DP_OFF_X, reg_data, 14));
 
-	v[0] = ((uint16_t)(reg_data[3] << 8) | reg_data[2]) & 0x1FFF;
-	v[1] = ((uint16_t)(reg_data[7] << 8) | reg_data[6]) & 0x1FFF;
-	v[2] = ((uint16_t)(reg_data[11] << 8) | reg_data[10]) & 0x1FFF;
+	v[0] = ((uint16_t)(reg_data[3] << 8) | reg_data[2]) & 0x3FFF;
+	v[1] = ((uint16_t)(reg_data[7] << 8) | reg_data[6]) & 0x3FFF;
+	v[2] = ((uint16_t)(reg_data[11] << 8) | reg_data[10]) & 0x3FFF;
 
 	for (i = X; i <= Z; ++i) {
-		if (v[i] > 0x0FFF)
-			v[i] = -8192 + v[i];
+		if (v[i] > 0x1FFF)
+			v[i] = -16384 + v[i];
 
 		v[i] = round_divide((int64_t)v[i] * BMI3_OFFSET_ACC_MULTI_MG,
 				    BMI_OFFSET_ACC_DIV_MG);
@@ -557,60 +488,27 @@ int get_accel_offset(const struct motion_sensor_t *s, intv3_t v)
 
 static int write_accel_offsets(const struct motion_sensor_t *s, int *val)
 {
-	uint8_t base_addr[2] = { BMI3_ACC_OFFSET_ADDR, 0 };
-	uint8_t offset_sel[2] = { BMI3_REG_UGAIN_OFF_SEL, 0 };
-	uint8_t reg_data[6] = {0};
-
-	/* Enable user gain/offset update*/
-	RETURN_ERROR(bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX,
-				    offset_sel, 2));
-	reg_data[0] = 0;
-	reg_data[1] = 0;
-	RETURN_ERROR(bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX_DATA,
-				    reg_data, 2));
-	/*
-	 * Set the user accel offset base address to feature engine
-	 * transmission address to start DMA transaction
-	 */
-	RETURN_ERROR(bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX,
-				    base_addr, 2));
+	uint8_t reg_data[6] = { 0 };
 
+	/* x-axis offset */
 	reg_data[0] = (uint8_t)(val[0] & BMI3_SET_LOW_BYTE);
-	reg_data[1] = (uint8_t)((val[0] & 0x1F00) >> 8);
+	reg_data[1] = (uint8_t)((val[0] & 0x3F00) >> 8);
+	/* y-axis offset */
 	reg_data[2] = (uint8_t)(val[1] & BMI3_SET_LOW_BYTE);
-	reg_data[3] = (uint8_t)((val[1] & 0x1F00) >> 8);
+	reg_data[3] = (uint8_t)((val[1] & 0x3F00) >> 8);
+	/* z-axis offset */
 	reg_data[4] = (uint8_t)(val[2] & BMI3_SET_LOW_BYTE);
-	reg_data[5] = (uint8_t)((val[2] & 0x1F00) >> 8);
-
-	/* Set the configuration to the feature engine register */
-	RETURN_ERROR(bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX_DATA,
-				    reg_data, 6));
+	reg_data[5] = (uint8_t)((val[2] & 0x3F00) >> 8);
 
-	/* Update the offset to the sensor engine */
-	reg_data[0] = (uint8_t)(BMI3_CMD_USR_GAIN_OFFS_UPDATE &
-				BMI3_SET_LOW_BYTE);
+	/* Update the acc data path offset registers */
+	RETURN_ERROR(bmi3_write_n(s, BMI3_ACC_DP_OFF_X, &reg_data[0], 2));
+	RETURN_ERROR(bmi3_write_n(s, BMI3_ACC_DP_OFF_Y, &reg_data[2], 2));
+	RETURN_ERROR(bmi3_write_n(s, BMI3_ACC_DP_OFF_Z, &reg_data[4], 2));
 
-	reg_data[1] = (uint8_t)((BMI3_CMD_USR_GAIN_OFFS_UPDATE &
-				 BMI3_SET_HIGH_BYTE) >> 8);
-
-	RETURN_ERROR(bmi3_write_n(s, BMI3_REG_CMD, reg_data, 2));
-
-	msleep(OFFSET_UPDATE_DELAY);
-
-	/* Read the configuration from the feature engine register */
-	RETURN_ERROR(bmi3_read_n(s, BMI3_FEATURE_IO_1, reg_data, 4));
-
-	if ((reg_data[3] & BMI3_UGAIN_OFFS_UPD_COMPLETE)
-		&& ((reg_data[2] & BMI3_FEATURE_IO_1_ERROR_MASK)
-			    == BMI3_FEATURE_IO_1_NO_ERROR)) {
-		return EC_SUCCESS;
-	}
-
-	return EC_ERROR_NOT_CALIBRATED;
+	return EC_SUCCESS;
 }
 
-int set_accel_offset(const struct motion_sensor_t *s, intv3_t v,
-					    uint8_t reset_en)
+int set_accel_offset(const struct motion_sensor_t *s, intv3_t v)
 {
 	uint8_t reg_data[4] = { 0 };
 	uint8_t saved_conf[6] = { 0 };
@@ -619,12 +517,12 @@ int set_accel_offset(const struct motion_sensor_t *s, intv3_t v,
 	for (i = X; i <= Z; ++i) {
 		val[i] = round_divide((int64_t)v[i] * BMI_OFFSET_ACC_DIV_MG,
 				      BMI3_OFFSET_ACC_MULTI_MG);
-		if (val[i] > 4095)
-			val[i] = 4095;
-		if (val[i] < -4096)
-			val[i] = -4096;
+		if (val[i] > 8191)
+			val[i] = 8191;
+		if (val[i] < -8192)
+			val[i] = -8192;
 		if (val[i] < 0)
-			val[i] += 8192;
+			val[i] += 16384;
 	}
 
 	/* Set the power mode as suspend */
@@ -637,12 +535,6 @@ int set_accel_offset(const struct motion_sensor_t *s, intv3_t v,
 	reg_data[3] = 0x00;
 	RETURN_ERROR(bmi3_write_n(s, BMI3_REG_ACC_CONF, reg_data, 4));
 
-	/* Reset the existing offset values */
-	if (reset_en) {
-		/* Reset is only done for writing offset and not for FOC */
-		RETURN_ERROR(reset_offset(s, 1));
-	}
-
 	/* Set the accel offset in the sensor registers */
 	RETURN_ERROR(write_accel_offsets(s, val));
 
@@ -652,79 +544,6 @@ int set_accel_offset(const struct motion_sensor_t *s, intv3_t v,
 	return EC_SUCCESS;
 }
 
-static int wait_and_read_data(const struct motion_sensor_t *s,
-			      intv3_t accel_data)
-{
-	uint8_t reg_data[8] = {0};
-
-	/* Retry 5 times */
-	uint8_t try_cnt = FOC_TRY_COUNT;
-
-	/* Check if data is ready */
-	while (try_cnt && (!(reg_data[2] & BMI3_STAT_DATA_RDY_ACCEL_MSK))) {
-		/* 20ms delay for 50Hz ODR */
-		msleep(FOC_DELAY);
-
-		/* Read the status register */
-		RETURN_ERROR(bmi3_read_n(s, BMI3_REG_STATUS, reg_data, 4));
-		try_cnt--;
-	}
-
-	if (!(reg_data[2] & BMI3_STAT_DATA_RDY_ACCEL_MSK))
-		return EC_ERROR_TIMEOUT;
-
-	/* Read the sensor data */
-	RETURN_ERROR(bmi3_read_n(s, BMI3_REG_ACC_DATA_X, reg_data, 8));
-
-	accel_data[0] = ((int16_t)((reg_data[3] << 8) | reg_data[2]));
-	accel_data[1] = ((int16_t)((reg_data[5] << 8) | reg_data[4]));
-	accel_data[2] = ((int16_t)((reg_data[7] << 8) | reg_data[6]));
-
-	rotate(accel_data, *s->rot_standard_ref, accel_data);
-
-	return EC_SUCCESS;
-}
-
-/*!
- * @brief This internal API performs Fast Offset Compensation for accelerometer.
- */
-static int8_t perform_accel_foc(struct motion_sensor_t *s, int *target,
-				int sens_range)
-{
-	intv3_t accel_data, offset;
-	int32_t delta_value[3] = {0, 0, 0};
-
-	/* Variable to define count */
-	uint8_t i, loop, sample_count = 0;
-
-	for (loop = 0; loop < BMI3_FOC_SAMPLE_LIMIT; loop++) {
-
-		RETURN_ERROR(wait_and_read_data(s, accel_data));
-
-		sample_count++;
-
-		/* Store the data in a temporary structure */
-		delta_value[0] += accel_data[0] - target[X];
-		delta_value[1] += accel_data[1] - target[Y];
-		delta_value[2] += accel_data[2] - target[Z];
-	}
-
-	/* The data is in LSB so -> [(LSB)*1000*range/2^15] (mdps | mg) */
-	for (i = X; i <= Z; ++i) {
-		offset[i] = (((int64_t)(delta_value[i] * 1000 * sens_range
-			     / sample_count) >> 15) * -1);
-	}
-
-	rotate_inv(offset, *s->rot_standard_ref, offset);
-
-	/* Set accel offset without resetting the existing offsets
-	 * since we calculated the bias with the existing offsets
-	 */
-	RETURN_ERROR(set_accel_offset(s, offset, BMI3_DISABLE));
-
-	return EC_SUCCESS;
-}
-
 static int set_gyro_foc_config(struct motion_sensor_t *s)
 {
 	uint8_t reg_data[4] = { 0 };
@@ -737,8 +556,8 @@ static int set_gyro_foc_config(struct motion_sensor_t *s)
 	RETURN_ERROR(bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX, base_addr, 2));
 
 	/* Read the configuration from the feature engine register */
-	RETURN_ERROR(bmi3_read_n(s, BMI3_FEATURE_ENGINE_DMA_TX_DATA, reg_data,
-			4));
+	RETURN_ERROR(
+		bmi3_read_n(s, BMI3_FEATURE_ENGINE_DMA_TX_DATA, reg_data, 4));
 	/* Enable self calibration */
 	reg_data[2] |= 0x07;
 
@@ -746,12 +565,12 @@ static int set_gyro_foc_config(struct motion_sensor_t *s)
 
 	/* Set the configuration to the feature engine register */
 	RETURN_ERROR(bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX_DATA,
-			&reg_data[2], 2));
+				  &reg_data[2], 2));
 
 	/* Trigger bmi3 gyro self calibration */
 	reg_data[0] = (uint8_t)(BMI3_CMD_SELF_CALIB & BMI3_SET_LOW_BYTE);
-	reg_data[1] = (uint8_t)((BMI3_CMD_SELF_CALIB & BMI3_SET_HIGH_BYTE)
-				>> 8);
+	reg_data[1] =
+		(uint8_t)((BMI3_CMD_SELF_CALIB & BMI3_SET_HIGH_BYTE) >> 8);
 
 	RETURN_ERROR(bmi3_write_n(s, BMI3_REG_CMD, reg_data, 2));
 
@@ -770,13 +589,6 @@ static int get_calib_result(struct motion_sensor_t *s)
 		RETURN_ERROR(bmi3_read_n(s, BMI3_FEATURE_IO_1, reg_data, 4));
 
 		switch (s->type) {
-		case MOTIONSENSE_TYPE_ACCEL:
-			if ((reg_data[3] & BMI3_UGAIN_OFFS_UPD_COMPLETE)
-			    && ((reg_data[2] & BMI3_FEATURE_IO_1_ERROR_MASK)
-			    == BMI3_FEATURE_IO_1_NO_ERROR)) {
-				return EC_SUCCESS;
-			}
-			break;
 		case MOTIONSENSE_TYPE_GYRO:
 			if (reg_data[2] & BMI3_SC_ST_STATUS_MASK) {
 				/* Check calibration result */
@@ -795,22 +607,17 @@ static int get_calib_result(struct motion_sensor_t *s)
 static int perform_calib(struct motion_sensor_t *s, int enable)
 {
 	int ret;
-	intv3_t target = {0, 0, 0};
-	uint8_t saved_conf[6] = {0};
-
-	/* Sensor is configured to be in 16G range */
-	int sens_range = 16;
+	uint8_t saved_conf[6] = { 0 };
 
 	/* Variable to set the accelerometer configuration value 50Hz for FOC */
-	uint8_t acc_conf_data[2] = {BMI3_FOC_ACC_CONF_VAL_LSB,
-					BMI3_FOC_ACC_CONF_VAL_MSB};
+	uint8_t acc_conf_data[2] = { BMI3_FOC_ACC_CONF_VAL_LSB,
+				     BMI3_FOC_ACC_CONF_VAL_MSB };
 
 	if (!enable)
 		return EC_SUCCESS;
 
 	/* Get default configurations for the type of feature selected. */
-	RETURN_ERROR(bmi3_read_n(s, BMI3_REG_ACC_CONF, saved_conf,
-				6));
+	RETURN_ERROR(bmi3_read_n(s, BMI3_REG_ACC_CONF, saved_conf, 6));
 
 	ret = bmi3_write_n(s, BMI3_REG_ACC_CONF, acc_conf_data, 2);
 	if (ret)
@@ -820,19 +627,8 @@ static int perform_calib(struct motion_sensor_t *s, int enable)
 
 	switch (s->type) {
 	case MOTIONSENSE_TYPE_ACCEL:
-		target[Z] = BMI3_ACC_DATA_PLUS_1G(sens_range);
-
-		/* Perform accel calibration */
-		ret = perform_accel_foc(s, target, sens_range);
-		if (ret)
-			goto end_calib;
-
-		/* Get caliration results */
-		ret = get_calib_result(s);
-		if (ret)
-			goto end_calib;
-
-		break;
+		ret = EC_RES_INVALID_COMMAND;
+		goto end_calib;
 	case MOTIONSENSE_TYPE_GYRO:
 		ret = set_gyro_foc_config(s);
 		if (ret)
@@ -849,7 +645,6 @@ static int perform_calib(struct motion_sensor_t *s, int enable)
 		goto end_calib;
 	}
 
-
 end_calib:
 	/* Restore ACC_CONF before exiting */
 	RETURN_ERROR(bmi3_write_n(s, BMI3_REG_ACC_CONF, &saved_conf[2], 4));
@@ -858,7 +653,7 @@ end_calib:
 }
 
 static int get_offset(const struct motion_sensor_t *s, int16_t *offset,
-		    int16_t *temp)
+		      int16_t *temp)
 {
 	int i;
 	intv3_t v;
@@ -891,9 +686,8 @@ static int get_offset(const struct motion_sensor_t *s, int16_t *offset,
 	return EC_SUCCESS;
 }
 
-static int set_offset(const struct motion_sensor_t *s,
-		      const int16_t *offset,
-		      int16_t    temp)
+static int set_offset(const struct motion_sensor_t *s, const int16_t *offset,
+		      int16_t temp)
 {
 	intv3_t v = { offset[X], offset[Y], offset[Z] };
 	(void)temp;
@@ -903,7 +697,7 @@ static int set_offset(const struct motion_sensor_t *s,
 	switch (s->type) {
 	case MOTIONSENSE_TYPE_ACCEL:
 		/* Offset should be in units of mg */
-		RETURN_ERROR(set_accel_offset(s, v, BMI3_ENABLE));
+		RETURN_ERROR(set_accel_offset(s, v));
 		break;
 	case MOTIONSENSE_TYPE_GYRO:
 		/* Offset should be in units of mdps */
@@ -917,9 +711,9 @@ static int set_offset(const struct motion_sensor_t *s,
 }
 
 #ifdef CONFIG_BODY_DETECTION
-int get_rms_noise(const struct motion_sensor_t *s)
+static int get_rms_noise(const struct motion_sensor_t *s)
 {
-	return EC_ERROR_UNIMPLEMENTED;
+	return bmi_get_rms_noise(s, BMI3_ACCEL_RMS_NOISE_100HZ);
 }
 #endif
 
@@ -936,7 +730,7 @@ static int set_scale(const struct motion_sensor_t *s, const uint16_t *scale,
 }
 
 static int get_scale(const struct motion_sensor_t *s, uint16_t *scale,
-		   int16_t *temp)
+		     int16_t *temp)
 {
 	struct accelgyro_saved_data_t *saved_data = BMI_GET_SAVED_DATA(s);
 
@@ -949,7 +743,6 @@ static int get_scale(const struct motion_sensor_t *s, uint16_t *scale,
 	return EC_SUCCESS;
 }
 
-
 static int get_data_rate(const struct motion_sensor_t *s)
 {
 	struct accelgyro_saved_data_t *saved_data = BMI_GET_SAVED_DATA(s);
@@ -957,8 +750,7 @@ static int get_data_rate(const struct motion_sensor_t *s)
 	return saved_data->odr;
 }
 
-static int set_data_rate(const struct motion_sensor_t *s,
-			 int rate, int rnd)
+static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
 {
 	int ret;
 	int normalized_rate = 0;
@@ -968,8 +760,8 @@ static int set_data_rate(const struct motion_sensor_t *s,
 	struct accelgyro_saved_data_t *saved_data = BMI_GET_SAVED_DATA(s);
 
 	if (rate > 0)
-		RETURN_ERROR(bmi_get_normalized_rate(s, rate, rnd,
-						 &normalized_rate, &reg_val));
+		RETURN_ERROR(bmi_get_normalized_rate(
+			s, rate, rnd, &normalized_rate, &reg_val));
 
 	/*
 	 * Lock accel resource to prevent another task from attempting
@@ -997,8 +789,8 @@ static int set_data_rate(const struct motion_sensor_t *s,
 			 * Accel does not have suspend mode.
 			 */
 			reg_data[3] = BMI3_SET_BITS(reg_data[3],
-				BMI3_POWER_MODE,
-				BMI3_ACC_MODE_DISABLE);
+						    BMI3_POWER_MODE,
+						    BMI3_ACC_MODE_DISABLE);
 
 			saved_data->odr = 0;
 		} else if (saved_data->odr == 0) {
@@ -1007,8 +799,8 @@ static int set_data_rate(const struct motion_sensor_t *s,
 			 * normal
 			 */
 			reg_data[3] = BMI3_SET_BITS(reg_data[3],
-				      BMI3_POWER_MODE,
-				      BMI3_ACC_MODE_NORMAL);
+						    BMI3_POWER_MODE,
+						    BMI3_ACC_MODE_NORMAL);
 		}
 	} else if (s->type == MOTIONSENSE_TYPE_GYRO) {
 		if (rate == 0) {
@@ -1021,8 +813,8 @@ static int set_data_rate(const struct motion_sensor_t *s,
 			 * however keep internal driver enabled
 			 */
 			reg_data[3] = BMI3_SET_BITS(reg_data[3],
-				      BMI3_POWER_MODE,
-				      BMI3_GYR_MODE_SUSPEND);
+						    BMI3_POWER_MODE,
+						    BMI3_GYR_MODE_SUSPEND);
 
 			saved_data->odr = 0;
 		} else if (saved_data->odr == 0) {
@@ -1030,8 +822,8 @@ static int set_data_rate(const struct motion_sensor_t *s,
 			 * normal
 			 */
 			reg_data[3] = BMI3_SET_BITS(reg_data[3],
-				      BMI3_POWER_MODE,
-				      BMI3_GYR_MODE_NORMAL);
+						    BMI3_POWER_MODE,
+						    BMI3_GYR_MODE_NORMAL);
 		}
 	}
 
@@ -1068,7 +860,7 @@ static int set_range(struct motion_sensor_t *s, int range, int rnd)
 	int ret;
 	uint8_t index, sens_size = 0;
 	uint8_t reg_data[4] = { 0 };
-	int (*sensor_range)[2];
+	int(*sensor_range)[2];
 
 	int acc_sensor_range[4][2] = {
 		{ 2, BMI3_ACC_RANGE_2G },
@@ -1119,8 +911,8 @@ static int set_range(struct motion_sensor_t *s, int range, int rnd)
 					    sensor_range[index][1]);
 
 		/* Set the accel/gyro configurations. */
-		ret = bmi3_write_n(s, BMI3_REG_ACC_CONF + s->type,
-				   &reg_data[2], 2);
+		ret = bmi3_write_n(s, BMI3_REG_ACC_CONF + s->type, &reg_data[2],
+				   2);
 
 		/* Now that we have set the range, update the driver's value. */
 		if (ret == EC_SUCCESS)
@@ -1198,8 +990,8 @@ static int init(struct motion_sensor_t *s)
 	 * BMI3xx driver only supports MOTIONSENSE_TYPE_ACCEL and
 	 * MOTIONSENSE_TYPE_GYR0
 	 */
-	if (s->type != MOTIONSENSE_TYPE_ACCEL
-	    && s->type != MOTIONSENSE_TYPE_GYRO)
+	if (s->type != MOTIONSENSE_TYPE_ACCEL &&
+	    s->type != MOTIONSENSE_TYPE_GYRO)
 		return EC_ERROR_UNIMPLEMENTED;
 
 	/* Read chip id */
@@ -1210,10 +1002,11 @@ static int init(struct motion_sensor_t *s)
 
 	if (s->type == MOTIONSENSE_TYPE_ACCEL) {
 		/* Reset bmi3 device */
-		reg_data[0] = (uint8_t)(BMI3_CMD_SOFT_RESET
-					& BMI3_SET_LOW_BYTE);
-		reg_data[1] = (uint8_t)((BMI3_CMD_SOFT_RESET
-					 & BMI3_SET_HIGH_BYTE) >> 8);
+		reg_data[0] =
+			(uint8_t)(BMI3_CMD_SOFT_RESET & BMI3_SET_LOW_BYTE);
+		reg_data[1] =
+			(uint8_t)((BMI3_CMD_SOFT_RESET & BMI3_SET_HIGH_BYTE) >>
+				  8);
 
 		RETURN_ERROR(bmi3_write_n(s, BMI3_REG_CMD, reg_data, 2));
 
@@ -1238,8 +1031,8 @@ static int init(struct motion_sensor_t *s)
 	saved_data->odr = 0;
 
 	/* Flags used in FIFO parsing */
-	data->flags &= ~(BMI_FLAG_SEC_I2C_ENABLED
-			| (BMI_FIFO_ALL_MASK << BMI_FIFO_FLAG_OFFSET));
+	data->flags &= ~(BMI_FLAG_SEC_I2C_ENABLED |
+			 (BMI_FIFO_ALL_MASK << BMI_FIFO_FLAG_OFFSET));
 
 	return sensor_init_done(s);
 }
diff --git a/driver/accelgyro_bmi3xx.h b/driver/accelgyro_bmi3xx.h
index 13037fbe51..e128b8381c 100644
--- a/driver/accelgyro_bmi3xx.h
+++ b/driver/accelgyro_bmi3xx.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,199 +9,201 @@
 #define __CROS_EC_ACCELGYRO_BMI3XX_H
 
 /* Sensor Specific macros */
-#define BMI3_ADDR_I2C_PRIM			0x68
-#define BMI3_ADDR_I2C_SEC			0x69
-#define BMI3_16_BIT_RESOLUTION			16
+#define BMI3_ADDR_I2C_PRIM 0x68
+#define BMI3_ADDR_I2C_SEC 0x69
+#define BMI3_16_BIT_RESOLUTION 16
 
 /* Chip-specific registers */
-#define BMI3_REG_CHIP_ID			0x00
-
-#define BMI3_REG_STATUS				0x02
-#define BMI3_STAT_DATA_RDY_ACCEL_POS		7
-#define BMI3_STAT_DATA_RDY_ACCEL_MSK		0x80
-
-#define BMI3_REG_ACC_DATA_X			0x03
-#define BMI3_ACC_RANGE_2G			0x00
-#define BMI3_ACC_RANGE_4G			0x01
-#define BMI3_ACC_RANGE_8G			0x02
-#define BMI3_ACC_RANGE_16G			0x03
-#define BMI3_ACC_MODE_DISABLE			0x00
-#define BMI3_ACC_MODE_LOW_PWR			0x03
-#define BMI3_ACC_MODE_NORMAL			0X04
-#define BMI3_ACC_MODE_HIGH_PERF			0x07
-
-#define BMI3_REG_GYR_DATA_X			0x06
-#define BMI3_GYR_RANGE_125DPS			0x00
-#define BMI3_GYR_RANGE_250DPS			0x01
-#define BMI3_GYR_RANGE_500DPS			0x02
-#define BMI3_GYR_RANGE_1000DPS			0x03
-#define BMI3_GYR_RANGE_2000DPS			0x04
-#define BMI3_GYR_MODE_DISABLE			0x00
-#define BMI3_GYR_MODE_SUSPEND			0X01
-#define BMI3_GYR_MODE_ULTRA_LOW_PWR		0X02
-#define BMI3_GYR_MODE_LOW_PWR			0x03
-#define BMI3_GYR_MODE_NORMAL			0X04
-#define BMI3_GYR_MODE_HIGH_PERF			0x07
-
-#define BMI3_REG_INT_STATUS_INT1		0x0D
-#define BMI3_REG_FIFO_FILL_LVL			0x15
-#define BMI3_REG_FIFO_DATA			0x16
-#define BMI3_REG_ACC_CONF			0x20
-#define BMI3_REG_GYR_CONF			0x21
-#define BMI3_REG_INT_MAP1			0x3A
-#define BMI3_REG_FIFO_WATERMARK			0x35
-#define BMI3_REG_UGAIN_OFF_SEL		0x3F
-#define BMI3_REG_FIFO_CONF			0x36
-#define BMI3_FIFO_STOP_ON_FULL			0x01
-#define BMI3_FIFO_TIME_EN			0x01
-#define BMI3_FIFO_ACC_EN			0x02
-#define BMI3_FIFO_GYR_EN			0x04
-#define BMI3_FIFO_TEMP_EN			0x08
-#define BMI3_FIFO_ALL_EN			0x0F
-
-#define BMI3_REG_FIFO_CTRL			0x37
-#define BMI3_REG_IO_INT_CTRL			0x38
-#define BMI3_INT1_LVL_MASK			0x01
-#define BMI3_INT1_OD_MASK			0x02
-#define BMI3_INT1_OD_POS			1
-#define BMI3_INT1_OUTPUT_EN_MASK		0x04
-#define BMI3_INT1_OUTPUT_EN_POS			2
-#define BMI3_INT_PUSH_PULL			0
-#define BMI3_INT_OPEN_DRAIN			1
-#define BMI3_INT_ACTIVE_LOW			0
-#define BMI3_INT_ACTIVE_HIGH			1
-
-#define BMI3_REG_IO_INT_CONF			0x39
-#define BMI3_INT_LATCH_EN			1
-#define BMI3_INT_LATCH_DISABLE			0
-
-#define BMI3_REG_FEATURE_ENGINE_GLOB_CTRL	0x40
-
-#define BMI3_FEATURE_EVENT_EXT			0x47
-#define BMI3_PORTRAIT_LANDSCAPE_MASK		0x03
-#define BMI3_PORTRAIT				0
-#define BMI3_LANDSCAPE				1
-#define BMI3_PORTRAIT_INVERT			2
-#define BMI3_LANDSCAPE_INVERT			3
-
-#define ACC_DP_OFF_X				0x60
-#define GYR_DP_OFF_X				0x66
-
-#define BMI3_REG_CMD				0x7E
-#define BMI3_CMD_SOFT_RESET			0xDEAF
+#define BMI3_REG_CHIP_ID 0x00
+
+#define BMI3_REG_STATUS 0x02
+#define BMI3_STAT_DATA_RDY_ACCEL_POS 7
+#define BMI3_STAT_DATA_RDY_ACCEL_MSK 0x80
+
+#define BMI3_REG_ACC_DATA_X 0x03
+#define BMI3_ACC_RANGE_2G 0x00
+#define BMI3_ACC_RANGE_4G 0x01
+#define BMI3_ACC_RANGE_8G 0x02
+#define BMI3_ACC_RANGE_16G 0x03
+#define BMI3_ACC_MODE_DISABLE 0x00
+#define BMI3_ACC_MODE_LOW_PWR 0x03
+#define BMI3_ACC_MODE_NORMAL 0X04
+#define BMI3_ACC_MODE_HIGH_PERF 0x07
+
+#define BMI3_REG_GYR_DATA_X 0x06
+#define BMI3_GYR_RANGE_125DPS 0x00
+#define BMI3_GYR_RANGE_250DPS 0x01
+#define BMI3_GYR_RANGE_500DPS 0x02
+#define BMI3_GYR_RANGE_1000DPS 0x03
+#define BMI3_GYR_RANGE_2000DPS 0x04
+#define BMI3_GYR_MODE_DISABLE 0x00
+#define BMI3_GYR_MODE_SUSPEND 0X01
+#define BMI3_GYR_MODE_ULTRA_LOW_PWR 0X02
+#define BMI3_GYR_MODE_LOW_PWR 0x03
+#define BMI3_GYR_MODE_NORMAL 0X04
+#define BMI3_GYR_MODE_HIGH_PERF 0x07
+
+#define BMI3_REG_INT_STATUS_INT1 0x0D
+#define BMI3_REG_FIFO_FILL_LVL 0x15
+#define BMI3_REG_FIFO_DATA 0x16
+#define BMI3_REG_ACC_CONF 0x20
+#define BMI3_REG_GYR_CONF 0x21
+#define BMI3_REG_INT_MAP1 0x3A
+#define BMI3_REG_FIFO_WATERMARK 0x35
+#define BMI3_REG_UGAIN_OFF_SEL 0x3F
+#define BMI3_REG_FIFO_CONF 0x36
+#define BMI3_FIFO_STOP_ON_FULL 0x01
+#define BMI3_FIFO_TIME_EN 0x01
+#define BMI3_FIFO_ACC_EN 0x02
+#define BMI3_FIFO_GYR_EN 0x04
+#define BMI3_FIFO_TEMP_EN 0x08
+#define BMI3_FIFO_ALL_EN 0x0F
+
+#define BMI3_REG_FIFO_CTRL 0x37
+#define BMI3_REG_IO_INT_CTRL 0x38
+#define BMI3_INT1_LVL_MASK 0x01
+#define BMI3_INT1_OD_MASK 0x02
+#define BMI3_INT1_OD_POS 1
+#define BMI3_INT1_OUTPUT_EN_MASK 0x04
+#define BMI3_INT1_OUTPUT_EN_POS 2
+#define BMI3_INT_PUSH_PULL 0
+#define BMI3_INT_OPEN_DRAIN 1
+#define BMI3_INT_ACTIVE_LOW 0
+#define BMI3_INT_ACTIVE_HIGH 1
+
+#define BMI3_REG_IO_INT_CONF 0x39
+#define BMI3_INT_LATCH_EN 1
+#define BMI3_INT_LATCH_DISABLE 0
+
+#define BMI3_REG_FEATURE_ENGINE_GLOB_CTRL 0x40
+
+#define BMI3_FEATURE_EVENT_EXT 0x47
+#define BMI3_PORTRAIT_LANDSCAPE_MASK 0x03
+#define BMI3_PORTRAIT 0
+#define BMI3_LANDSCAPE 1
+#define BMI3_PORTRAIT_INVERT 2
+#define BMI3_LANDSCAPE_INVERT 3
+
+#define BMI3_ACC_DP_OFF_X 0x60
+#define BMI3_ACC_DP_OFF_Y 0x62
+#define BMI3_ACC_DP_OFF_Z 0x64
+
+#define BMI3_GYR_DP_OFF_X 0x66
+#define BMI3_GYR_DP_OFF_Y 0x68
+#define BMI3_GYR_DP_OFF_Z 0x6A
+
+#define BMI3_REG_CMD 0x7E
+#define BMI3_CMD_SOFT_RESET 0xDEAF
 
 /* BMI3 Interrupt Output Enable */
-#define BMI3_INT_OUTPUT_DISABLE			0
-#define BMI3_INT_OUTPUT_ENABLE			1
+#define BMI3_INT_OUTPUT_DISABLE 0
+#define BMI3_INT_OUTPUT_ENABLE 1
 
 /* FIFO sensor data length (in word), Accel or Gyro */
-#define BMI3_FIFO_ENTRY			0x3
+#define BMI3_FIFO_ENTRY 0x3
 /* Macro to define accelerometer configuration value for FOC */
-#define BMI3_FOC_ACC_CONF_VAL_LSB		0xB7
-#define BMI3_FOC_ACC_CONF_VAL_MSB		0x40
+#define BMI3_FOC_ACC_CONF_VAL_LSB 0xB7
+#define BMI3_FOC_ACC_CONF_VAL_MSB 0x40
 /* Macro to define the accel FOC range */
-#define BMI3_ACC_FOC_2G_REF			16384
-#define BMI3_ACC_FOC_4G_REF			8192
-#define BMI3_ACC_FOC_8G_REF			4096
-#define BMI3_ACC_FOC_16G_REF			2048
-#define BMI3_FOC_SAMPLE_LIMIT			32
+#define BMI3_ACC_FOC_2G_REF 16384
+#define BMI3_ACC_FOC_4G_REF 8192
+#define BMI3_ACC_FOC_8G_REF 4096
+#define BMI3_ACC_FOC_16G_REF 2048
+#define BMI3_FOC_SAMPLE_LIMIT 32
 
-#define FOC_TRY_COUNT				5
+#define FOC_TRY_COUNT 5
 /* 20ms delay for 50Hz ODR */
-#define FOC_DELAY				20
-#define OFFSET_UPDATE_DELAY			120
-#define BMI3_INT_STATUS_FWM			0x4000
-#define BMI3_INT_STATUS_FFULL			0x8000
-#define BMI3_INT_STATUS_ORIENTATION		0x0008
+#define FOC_DELAY 20
+#define OFFSET_UPDATE_DELAY 120
+#define BMI3_INT_STATUS_FWM 0x4000
+#define BMI3_INT_STATUS_FFULL 0x8000
+#define BMI3_INT_STATUS_ORIENTATION 0x0008
 
-
-#define BMI3_FIFO_GYRO_I2C_SYNC_FRAME		0x7f02
-#define BMI3_FIFO_ACCEL_I2C_SYNC_FRAME		0x7f01
+#define BMI3_FIFO_GYRO_I2C_SYNC_FRAME 0x7f02
+#define BMI3_FIFO_ACCEL_I2C_SYNC_FRAME 0x7f01
 
 /* Gyro self calibration address */
-#define BMI3_BASE_ADDR_SC			0x26
-#define BMI3_CMD_SELF_CALIB			0x0101
+#define BMI3_BASE_ADDR_SC 0x26
+#define BMI3_CMD_SELF_CALIB 0x0101
 
 /* Feature engine General purpose register 1. */
-#define BMI3_FEATURE_IO_0			0x10
-#define BMI3_ANY_MOTION_X_EN_MASK		0x08
+#define BMI3_FEATURE_IO_0 0x10
+#define BMI3_ANY_MOTION_X_EN_MASK 0x08
 
-#define BMI3_FEATURE_IO_1			0x11
-#define BMI3_FEATURE_IO_1_ERROR_MASK		0x0F
-#define BMI3_FEATURE_IO_1_NO_ERROR		0x05
-#define BMI3_SC_ST_STATUS_MASK			0x10
-#define BMI3_SC_RESULT_MASK			0x20
-#define BMI3_UGAIN_OFFS_UPD_COMPLETE		0x01
+#define BMI3_FEATURE_IO_1 0x11
+#define BMI3_FEATURE_IO_1_ERROR_MASK 0x0F
+#define BMI3_FEATURE_IO_1_NO_ERROR 0x05
+#define BMI3_SC_ST_STATUS_MASK 0x10
+#define BMI3_SC_RESULT_MASK 0x20
+#define BMI3_UGAIN_OFFS_UPD_COMPLETE 0x01
 
-#define BMI3_FEATURE_IO_STATUS			0x14
+#define BMI3_FEATURE_IO_STATUS 0x14
 
 /*
  * The max positive value of accel data is 0x7FFF, equal to range(g)
  * So, in order to get +1g, divide the 0x7FFF by range
  */
-#define BMI3_ACC_DATA_PLUS_1G(range)  (0x7FFF / (range))
+#define BMI3_ACC_DATA_PLUS_1G(range) (0x7FFF / (range))
 #define BMI3_ACC_DATA_MINUS_1G(range) (-BMI3_ACC_DATA_PLUS_1G(range))
 
 /* Offset DMA registers */
-#define BMI3_ACC_OFFSET_ADDR			0x40
-#define BMI3_GYRO_OFFSET_ADDR			0x46
+#define BMI3_ACC_OFFSET_ADDR 0x40
+#define BMI3_GYRO_OFFSET_ADDR 0x46
 
 /*
  * Start address of the DMA transaction. Has to be written to initiate a
  * transaction.
  */
-#define BMI3_FEATURE_ENGINE_DMA_TX		0x41
+#define BMI3_FEATURE_ENGINE_DMA_TX 0x41
 
 /* DMA read/write data. On read transaction expect first word to be zero. */
-#define BMI3_FEATURE_ENGINE_DMA_TX_DATA		0x42
+#define BMI3_FEATURE_ENGINE_DMA_TX_DATA 0x42
 
 /* Command for offset update */
-#define BMI3_CMD_USR_GAIN_OFFS_UPDATE		0x301
+#define BMI3_CMD_USR_GAIN_OFFS_UPDATE 0x301
 
 /* 1LSB - 31 Micro-G */
-#define BMI3_OFFSET_ACC_MULTI_MG		(31 * 1000)
+#define BMI3_OFFSET_ACC_MULTI_MG (31 * 1000)
 
 /* 1LSB = 61 milli-dps*/
-#define BMI3_OFFSET_GYR_MDPS			(61 * 1000)
+#define BMI3_OFFSET_GYR_MDPS (61 * 1000)
 
-#define BMI3_FIFO_BUFFER			32
+#define BMI3_FIFO_BUFFER 32
 
 /* General Macro Definitions */
 /* LSB and MSB mask definitions */
-#define BMI3_SET_LOW_BYTE			0x00FF
-#define BMI3_SET_HIGH_BYTE			0xFF00
+#define BMI3_SET_LOW_BYTE 0x00FF
+#define BMI3_SET_HIGH_BYTE 0xFF00
 
 /* For enable and disable */
-#define BMI3_ENABLE				0x1
-#define BMI3_DISABLE				0x0
+#define BMI3_ENABLE 0x1
+#define BMI3_DISABLE 0x0
 
 /* Defines mode of operation for Accelerometer */
-#define BMI3_POWER_MODE_MASK			0x70
-#define BMI3_POWER_MODE_POS			4
+#define BMI3_POWER_MODE_MASK 0x70
+#define BMI3_POWER_MODE_POS 4
 
-#define BMI3_SENS_ODR_MASK			0x0F
+#define BMI3_SENS_ODR_MASK 0x0F
 
 /* Full scale, Resolution */
-#define BMI3_SENS_RANGE_MASK			0x70
-#define BMI3_SENS_RANGE_POS			4
+#define BMI3_SENS_RANGE_MASK 0x70
+#define BMI3_SENS_RANGE_POS 4
 
-#define BMI3_CHIP_ID_MASK			0xFF
+#define BMI3_CHIP_ID_MASK 0xFF
 
 /* Map FIFO water-mark interrupt to either INT1 or INT2 or IBI */
-#define BMI3_FWM_INT_MASK			0x30
-#define BMI3_FWM_INT_POS			4
+#define BMI3_FWM_INT_MASK 0x30
+#define BMI3_FWM_INT_POS 4
 
 /* Map FIFO full interrupt to either INT1 or INT2 or IBI */
-#define BMI3_FFULL_INT_MASK			0xC0
-#define BMI3_FFULL_INT_POS			6
-
-#define BMI3_ORIENT_INT_MASK			0xC0
-#define BMI3_ORIENT_INT_POS			6
-
+#define BMI3_FFULL_INT_MASK 0xC0
+#define BMI3_FFULL_INT_POS 6
 
+#define BMI3_ORIENT_INT_MASK 0xC0
+#define BMI3_ORIENT_INT_POS 6
 
 /*  Mask definitions for interrupt pin configuration */
-#define BMI3_INT_LATCH_MASK			0x0001
+#define BMI3_INT_LATCH_MASK 0x0001
 
 /**
  * Current fill level of FIFO buffer
@@ -210,7 +212,10 @@
  * fifo_flush. The word counter is updated each time a complete frame was read
  * or written.
  */
-#define BMI3_FIFO_FILL_LVL_MASK			0x07FF
+#define BMI3_FIFO_FILL_LVL_MASK 0x07FF
+
+/* Root mean square noise of 100 Hz accelerometer, units: ug */
+#define BMI3_ACCEL_RMS_NOISE_100HZ 1200
 
 /* Enum to define interrupt lines */
 enum bmi3_hw_int_pin {
@@ -236,24 +241,21 @@ enum sensor_index_t {
 	NUM_OF_PRIMARY_SENSOR,
 };
 
-#define BMI3_DRDY_OFF(_sensor)   (7 - (_sensor))
-#define BMI3_DRDY_MASK(_sensor)  (1 << BMI3_DRDY_OFF(_sensor))
+#define BMI3_DRDY_OFF(_sensor) (7 - (_sensor))
+#define BMI3_DRDY_MASK(_sensor) (1 << BMI3_DRDY_OFF(_sensor))
 
 /* Utility macros */
-#define BMI3_SET_BITS(reg_data, bitname, data)         \
-		     ((reg_data & ~(bitname##_MASK)) | \
-		     ((data << bitname##_POS) & bitname##_MASK))
+#define BMI3_SET_BITS(reg_data, bitname, data) \
+	((reg_data & ~(bitname##_MASK)) |      \
+	 ((data << bitname##_POS) & bitname##_MASK))
 
-#define BMI3_GET_BITS(reg_data, bitname)               \
-		     ((reg_data & (bitname##_MASK)) >> \
-		     (bitname##_POS))
+#define BMI3_GET_BITS(reg_data, bitname) \
+	((reg_data & (bitname##_MASK)) >> (bitname##_POS))
 
-#define BMI3_SET_BIT_POS0(reg_data, bitname, data)         \
-			 ((reg_data & ~(bitname##_MASK)) | \
-			 (data & bitname##_MASK))
+#define BMI3_SET_BIT_POS0(reg_data, bitname, data) \
+	((reg_data & ~(bitname##_MASK)) | (data & bitname##_MASK))
 
-#define BMI3_GET_BIT_POS0(reg_data, bitname) \
-			 (reg_data & (bitname##_MASK))
+#define BMI3_GET_BIT_POS0(reg_data, bitname) (reg_data & (bitname##_MASK))
 
 extern const struct accelgyro_drv bmi3xx_drv;
 
@@ -274,9 +276,9 @@ void bmi3xx_interrupt(enum gpio_signal signal);
  *     bmi3xx-int = &base_accel;
  * };
  */
-#define CONFIG_ACCELGYRO_BMI3XX_INT_EVENT	\
+#define CONFIG_ACCELGYRO_BMI3XX_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(SENSOR_ID(DT_ALIAS(bmi3xx_int)))
 #endif
-#endif  /* CONFIG_ZEPHYR */
+#endif /* CONFIG_ZEPHYR */
 
 #endif /* __CROS_EC_ACCELGYRO_BMI3XX_H */
diff --git a/driver/accelgyro_bmi_common.c b/driver/accelgyro_bmi_common.c
index 210cfd37ce..73131b0aae 100644
--- a/driver/accelgyro_bmi_common.c
+++ b/driver/accelgyro_bmi_common.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,7 +8,6 @@
  * 3D digital accelerometer & 3D digital gyroscope
  */
 
-
 #include "accelgyro.h"
 #include "console.h"
 #include "accelgyro_bmi_common.h"
@@ -20,29 +19,29 @@
 #include "spi.h"
 
 #define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args)
 
-#if !defined(CONFIG_ACCELGYRO_BMI160) && \
-    !defined(CONFIG_ACCELGYRO_BMI220) && \
-    !defined(CONFIG_ACCELGYRO_BMI260) && \
-    !defined(CONFIG_ACCELGYRO_BMI3XX)
+#if !defined(CONFIG_ACCELGYRO_BMI160) && !defined(CONFIG_ACCELGYRO_BMI220) && \
+	!defined(CONFIG_ACCELGYRO_BMI260) && !defined(CONFIG_ACCELGYRO_BMI3XX)
 #error "Must use following sensors BMI160 BMI220 BMI260 BMI3XX"
 #endif
 
 #if (defined(CONFIG_ACCELGYRO_BMI260) || defined(CONFIG_ACCELGYRO_BMI220)) && \
-    !defined(CONFIG_ACCELGYRO_BMI160)
+	!defined(CONFIG_ACCELGYRO_BMI160)
 #define V(s_) 1
-#elif defined(CONFIG_ACCELGYRO_BMI160) && \
-      !(defined(CONFIG_ACCELGYRO_BMI260) || defined(CONFIG_ACCELGYRO_BMI220))
+#elif defined(CONFIG_ACCELGYRO_BMI160) &&     \
+	!(defined(CONFIG_ACCELGYRO_BMI260) || \
+	  defined(CONFIG_ACCELGYRO_BMI220))
 #define V(s_) 0
 #else
-#define V(s_) ((s_)->chip == MOTIONSENSE_CHIP_BMI260 || \
-	       (s_)->chip == MOTIONSENSE_CHIP_BMI220)
+#define V(s_)                                     \
+	((s_)->chip == MOTIONSENSE_CHIP_BMI260 || \
+	 (s_)->chip == MOTIONSENSE_CHIP_BMI220)
 #endif
 /* Index for which table to use. */
 #if defined(CONFIG_ACCELGYRO_BMI160) && \
-    (defined(CONFIG_ACCELGYRO_BMI220) || defined(CONFIG_ACCELGYRO_BMI260))
+	(defined(CONFIG_ACCELGYRO_BMI220) || defined(CONFIG_ACCELGYRO_BMI260))
 #define T(s_) V(s_)
 #else
 #define T(s_) 0
@@ -51,16 +50,16 @@
 /* List of range values in +/-G's and their associated register values. */
 const struct bmi_accel_param_pair g_ranges[][4] = {
 #ifdef CONFIG_ACCELGYRO_BMI160
-	{ {2,  BMI160_GSEL_2G},
-	  {4,  BMI160_GSEL_4G},
-	  {8,  BMI160_GSEL_8G},
-	  {16, BMI160_GSEL_16G} },
+	{ { 2, BMI160_GSEL_2G },
+	  { 4, BMI160_GSEL_4G },
+	  { 8, BMI160_GSEL_8G },
+	  { 16, BMI160_GSEL_16G } },
 #endif
 #if defined(CONFIG_ACCELGYRO_BMI220) || defined(CONFIG_ACCELGYRO_BMI260)
-	{ {2,  BMI260_GSEL_2G},
-	  {4,  BMI260_GSEL_4G},
-	  {8,  BMI260_GSEL_8G},
-	  {16, BMI260_GSEL_16G} },
+	{ { 2, BMI260_GSEL_2G },
+	  { 4, BMI260_GSEL_4G },
+	  { 8, BMI260_GSEL_8G },
+	  { 16, BMI260_GSEL_16G } },
 #endif
 };
 
@@ -70,18 +69,18 @@ const struct bmi_accel_param_pair g_ranges[][4] = {
  */
 const struct bmi_accel_param_pair dps_ranges[][5] = {
 #ifdef CONFIG_ACCELGYRO_BMI160
-	{ {125,  BMI160_DPS_SEL_125},
-	  {250,  BMI160_DPS_SEL_250},
-	  {500,  BMI160_DPS_SEL_500},
-	  {1000, BMI160_DPS_SEL_1000},
-	  {2000, BMI160_DPS_SEL_2000} },
+	{ { 125, BMI160_DPS_SEL_125 },
+	  { 250, BMI160_DPS_SEL_250 },
+	  { 500, BMI160_DPS_SEL_500 },
+	  { 1000, BMI160_DPS_SEL_1000 },
+	  { 2000, BMI160_DPS_SEL_2000 } },
 #endif
 #if defined(CONFIG_ACCELGYRO_BMI220) || defined(CONFIG_ACCELGYRO_BMI260)
-	{ {125,  BMI260_DPS_SEL_125},
-	  {250,  BMI260_DPS_SEL_250},
-	  {500,  BMI260_DPS_SEL_500},
-	  {1000, BMI260_DPS_SEL_1000},
-	  {2000, BMI260_DPS_SEL_2000} },
+	{ { 125, BMI260_DPS_SEL_125 },
+	  { 250, BMI260_DPS_SEL_250 },
+	  { 500, BMI260_DPS_SEL_500 },
+	  { 1000, BMI260_DPS_SEL_1000 },
+	  { 2000, BMI260_DPS_SEL_2000 } },
 #endif
 };
 
@@ -99,8 +98,8 @@ int bmi_get_xyz_reg(const struct motion_sensor_t *s)
 	}
 }
 
-const struct bmi_accel_param_pair *bmi_get_range_table(
-		const struct motion_sensor_t *s, int *psize)
+const struct bmi_accel_param_pair *
+bmi_get_range_table(const struct motion_sensor_t *s, int *psize)
 {
 	if (s->type == MOTIONSENSE_TYPE_ACCEL) {
 		if (psize)
@@ -119,8 +118,7 @@ const struct bmi_accel_param_pair *bmi_get_range_table(
  * outside the range of values, it returns the closest valid reg value.
  */
 int bmi_get_reg_val(const int eng_val, const int round_up,
-		    const struct bmi_accel_param_pair *pairs,
-		    const int size)
+		    const struct bmi_accel_param_pair *pairs, const int size)
 {
 	int i;
 
@@ -128,7 +126,7 @@ int bmi_get_reg_val(const int eng_val, const int round_up,
 		if (eng_val <= pairs[i].val)
 			break;
 
-		if (eng_val < pairs[i+1].val) {
+		if (eng_val < pairs[i + 1].val) {
 			if (round_up)
 				i += 1;
 			break;
@@ -154,8 +152,8 @@ int bmi_get_engineering_val(const int reg_val,
 }
 
 #ifdef CONFIG_ACCELGYRO_BMI_COMM_SPI
-static int bmi_spi_raw_read(const int addr, const uint8_t reg,
-		     uint8_t *data, const int len)
+static int bmi_spi_raw_read(const int addr, const uint8_t reg, uint8_t *data,
+			    const int len)
 {
 	uint8_t cmd = 0x80 | reg;
 
@@ -166,8 +164,8 @@ static int bmi_spi_raw_read(const int addr, const uint8_t reg,
 /**
  * Read 8bit register from accelerometer.
  */
-int bmi_read8(const int port, const uint16_t i2c_spi_addr_flags,
-	      const int reg, int *data_ptr)
+int bmi_read8(const int port, const uint16_t i2c_spi_addr_flags, const int reg,
+	      int *data_ptr)
 {
 	int rv;
 
@@ -189,8 +187,8 @@ int bmi_read8(const int port, const uint16_t i2c_spi_addr_flags,
 /**
  * Write 8bit register from accelerometer.
  */
-int bmi_write8(const int port, const uint16_t i2c_spi_addr_flags,
-	       const int reg, int data)
+int bmi_write8(const int port, const uint16_t i2c_spi_addr_flags, const int reg,
+	       int data)
 {
 	int rv;
 
@@ -381,16 +379,16 @@ int bmi_decode_header(struct motion_sensor_t *accel, enum fifo_header hdr,
 				    s->flags & MOTIONSENSE_FLAG_IN_SPOOF_MODE)
 					v = s->spoof_xyz;
 				if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
-					struct ec_response_motion_sensor_data vector;
+					struct ec_response_motion_sensor_data
+						vector;
 
 					vector.flags = 0;
 					vector.data[X] = v[X];
 					vector.data[Y] = v[Y];
 					vector.data[Z] = v[Z];
 					vector.sensor_num = s - motion_sensors;
-					motion_sense_fifo_stage_data(&vector, s,
-								     3,
-								     last_ts);
+					motion_sense_fifo_stage_data(
+						&vector, s, 3, last_ts);
 				} else {
 					motion_sense_push_raw_xyz(s);
 				}
@@ -626,30 +624,21 @@ int bmi_get_offset(const struct motion_sensor_t *s, int16_t *offset,
 }
 
 #ifdef CONFIG_BODY_DETECTION
-int bmi_get_rms_noise(const struct motion_sensor_t *s)
+int bmi_get_rms_noise(const struct motion_sensor_t *accel,
+		      int rms_noise_100hz_mg)
 {
-	int ret;
-	fp_t noise_100hz, rate, sqrt_rate_ratio;
+	fp_t rate, sqrt_rate_ratio;
 
-	switch (s->type) {
-	case MOTIONSENSE_TYPE_ACCEL:
-		/* change unit of ODR to Hz to prevent INT_TO_FP() overflow */
-		rate = INT_TO_FP(bmi_get_data_rate(s) / 1000);
-		/*
-		 * Since the noise is proportional to sqrt(ODR) in BMI, and we
-		 * have rms noise in 100 Hz, we multiply it with the sqrt(ratio
-		 * of ODR to 100Hz) to get current noise.
-		 */
-		noise_100hz = INT_TO_FP(BMI_ACCEL_RMS_NOISE_100HZ(V(s)));
-		sqrt_rate_ratio =
-			fp_sqrtf(fp_div(rate, INT_TO_FP(BMI_ACCEL_100HZ)));
-		ret = FP_TO_INT(fp_mul(noise_100hz, sqrt_rate_ratio));
-		break;
-	default:
-		CPRINTS("%s with gyro/mag is not implemented", __func__);
-		return 0;
-	}
-	return ret;
+	/* change unit of ODR to Hz to prevent INT_TO_FP() overflow */
+	rate = INT_TO_FP(bmi_get_data_rate(accel) / 1000);
+	/*
+	 * Since the noise is proportional to sqrt(ODR) in BMI, and we
+	 * have rms noise in 100 Hz, we multiply it with the sqrt(ratio
+	 * of ODR to 100Hz) to get current noise.
+	 */
+	sqrt_rate_ratio = fp_sqrtf(fp_div(rate, INT_TO_FP(BMI_ACCEL_100HZ)));
+	return FP_TO_INT(
+		fp_mul(INT_TO_FP(rms_noise_100hz_mg), sqrt_rate_ratio));
 }
 #endif
 
@@ -859,7 +848,7 @@ int bmi_set_accel_offset(const struct motion_sensor_t *accel, intv3_t v)
 }
 
 int bmi_set_gyro_offset(const struct motion_sensor_t *gyro, intv3_t v,
-			 int *val98_ptr)
+			int *val98_ptr)
 {
 	int i, val, ret;
 
@@ -903,8 +892,7 @@ void motion_orientation_update(const struct motion_sensor_t *s)
 }
 #endif
 
-int bmi_list_activities(const struct motion_sensor_t *s,
-			uint32_t *enabled,
+int bmi_list_activities(const struct motion_sensor_t *s, uint32_t *enabled,
 			uint32_t *disabled)
 {
 	struct bmi_drv_data_t *data = BMI_GET_DATA(s);
diff --git a/driver/accelgyro_icm42607.c b/driver/accelgyro_icm42607.c
index 0edb1426ab..28a131d33f 100644
--- a/driver/accelgyro_icm42607.c
+++ b/driver/accelgyro_icm42607.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,11 +27,11 @@
 #endif
 
 #define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args)
 
 STATIC_IF(ACCELGYRO_ICM42607_INT_ENABLE)
-	volatile uint32_t last_interrupt_timestamp;
+volatile uint32_t last_interrupt_timestamp;
 
 static int icm_switch_on_mclk(const struct motion_sensor_t *s)
 {
@@ -156,8 +156,7 @@ static int icm42607_normalize(const struct motion_sensor_t *s, intv3_t v,
 	v[Z] = (int16_t)UINT16_FROM_BYTE_ARRAY_LE(raw, 4);
 
 	/* check if data is valid */
-	if (v[X] == ICM42607_INVALID_DATA &&
-	    v[Y] == ICM42607_INVALID_DATA &&
+	if (v[X] == ICM42607_INVALID_DATA && v[Y] == ICM42607_INVALID_DATA &&
 	    v[Z] == ICM42607_INVALID_DATA) {
 		return EC_ERROR_INVAL;
 	}
@@ -212,8 +211,8 @@ static int __maybe_unused icm42607_flush_fifo(const struct motion_sensor_t *s)
 }
 
 /* use FIFO threshold interrupt on INT1 */
-#define ICM42607_FIFO_INT_EN		ICM42607_FIFO_THS_INT1_EN
-#define ICM42607_FIFO_INT_STATUS	ICM42607_FIFO_THS_INT
+#define ICM42607_FIFO_INT_EN ICM42607_FIFO_THS_INT1_EN
+#define ICM42607_FIFO_INT_STATUS ICM42607_FIFO_THS_INT
 
 static int __maybe_unused icm42607_enable_fifo(const struct motion_sensor_t *s,
 					       int enable)
@@ -363,8 +362,8 @@ static int __maybe_unused icm42607_load_fifo(struct motion_sensor_t *s,
 		return ret;
 
 	for (i = 0; i < count; i += size) {
-		size = icm_fifo_decode_packet(&st->fifo_buffer[i],
-				&accel, &gyro);
+		size = icm_fifo_decode_packet(&st->fifo_buffer[i], &accel,
+					      &gyro);
 		/* exit if error or FIFO is empty */
 		if (size <= 0)
 			return -size;
@@ -464,7 +463,7 @@ static int icm42607_config_interrupt(const struct motion_sensor_t *s)
 	return EC_SUCCESS;
 }
 
-#endif	/* ACCELGYRO_ICM42607_INT_ENABLE */
+#endif /* ACCELGYRO_ICM42607_INT_ENABLE */
 
 static int icm42607_enable_sensor(const struct motion_sensor_t *s, int enable)
 {
@@ -571,7 +570,7 @@ static int icm42607_set_data_rate(const struct motion_sensor_t *s, int rate,
 
 	if (rate > 0) {
 		if ((normalized_rate < min_rate) ||
-				(normalized_rate > max_rate))
+		    (normalized_rate > max_rate))
 			return EC_RES_INVALID_PARAM;
 	}
 
@@ -612,8 +611,7 @@ out_unlock:
 	return ret;
 }
 
-static int icm42607_set_range(struct motion_sensor_t *s, int range,
-			      int rnd)
+static int icm42607_set_range(struct motion_sensor_t *s, int range, int rnd)
 {
 	int reg, ret, reg_val;
 	int newrange;
@@ -1016,7 +1014,7 @@ static int icm42607_init_config(const struct motion_sensor_t *s)
 	if (ret)
 		return ret;
 
-	ret = icm_write8(s, ICM42607_REG_APEX_CONFIG1,  0x02);
+	ret = icm_write8(s, ICM42607_REG_APEX_CONFIG1, 0x02);
 	if (ret)
 		return ret;
 
diff --git a/driver/accelgyro_icm42607.h b/driver/accelgyro_icm42607.h
index e2d2b3469a..53ae7a37df 100644
--- a/driver/accelgyro_icm42607.h
+++ b/driver/accelgyro_icm42607.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,59 +15,55 @@
  * 7-bit address is 110100Xb. Where 'X' is determined
  * by the logic level on pin AP_AD0.
  */
-#define ICM42607_ADDR0_FLAGS		0x68
-#define ICM42607_ADDR1_FLAGS		0x69
+#define ICM42607_ADDR0_FLAGS 0x68
+#define ICM42607_ADDR1_FLAGS 0x69
 
 /* Min and Max sampling frequency in mHz */
-#define ICM42607_ACCEL_MIN_FREQ		1562
-#define ICM42607_ACCEL_MAX_FREQ		\
-		MOTION_MAX_SENSOR_FREQUENCY(400000, 100000)
-#define ICM42607_GYRO_MIN_FREQ		12500
-#define ICM42607_GYRO_MAX_FREQ		\
-		MOTION_MAX_SENSOR_FREQUENCY(1600000, 100000)
+#define ICM42607_ACCEL_MIN_FREQ 1562
+#define ICM42607_ACCEL_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(400000, 100000)
+#define ICM42607_GYRO_MIN_FREQ 12500
+#define ICM42607_GYRO_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(1600000, 100000)
 
 /* Min and Max Accel FS in g */
-#define ICM42607_ACCEL_FS_MIN_VAL	2
-#define ICM42607_ACCEL_FS_MAX_VAL	16
+#define ICM42607_ACCEL_FS_MIN_VAL 2
+#define ICM42607_ACCEL_FS_MAX_VAL 16
 
 /* Min and Max Gyro FS in dps */
-#define ICM42607_GYRO_FS_MIN_VAL	250
-#define ICM42607_GYRO_FS_MAX_VAL	2000
+#define ICM42607_GYRO_FS_MIN_VAL 250
+#define ICM42607_GYRO_FS_MAX_VAL 2000
 
 /* accel stabilization time in us */
-#define ICM42607_ACCEL_START_TIME	20000
-#define ICM42607_ACCEL_STOP_TIME	0
+#define ICM42607_ACCEL_START_TIME 20000
+#define ICM42607_ACCEL_STOP_TIME 0
 
 /* gyro stabilization time in us */
-#define ICM42607_GYRO_START_TIME	40000
-#define ICM42607_GYRO_STOP_TIME		20000
+#define ICM42607_GYRO_START_TIME 40000
+#define ICM42607_GYRO_STOP_TIME 20000
 
 /* Reg value from Accel FS in G */
-#define ICM42607_ACCEL_FS_TO_REG(_fs)	((_fs) <= 2 ? 3 : \
-					 (_fs) >= 16 ? 0 : \
-					 3 - __fls((_fs) / 2))
+#define ICM42607_ACCEL_FS_TO_REG(_fs) \
+	((_fs) <= 2 ? 3 : (_fs) >= 16 ? 0 : 3 - __fls((_fs) / 2))
 
 /* Accel FSR in G from Reg value */
-#define ICM42607_ACCEL_REG_TO_FS(_reg)	((1 << (3 - (_reg))) * 2)
+#define ICM42607_ACCEL_REG_TO_FS(_reg) ((1 << (3 - (_reg))) * 2)
 
 /* Reg value from Gyro FS in dps */
-#define ICM42607_GYRO_FS_TO_REG(_fs)	((_fs) <= 250 ? 3 : \
-					 (_fs) >= 2000 ? 0 : \
-					 3 - __fls((_fs) / 250))
+#define ICM42607_GYRO_FS_TO_REG(_fs) \
+	((_fs) <= 250 ? 3 : (_fs) >= 2000 ? 0 : 3 - __fls((_fs) / 250))
 
 /* Gyro FSR in dps from Reg value */
-#define ICM42607_GYRO_REG_TO_FS(_reg)	((1 << (3 - (_reg))) * 250)
+#define ICM42607_GYRO_REG_TO_FS(_reg) ((1 << (3 - (_reg))) * 250)
 
 /* Reg value from ODR in mHz */
-#define ICM42607_ODR_TO_REG(_odr)	((_odr) == 0 ? 0 : \
-					 (__fls(1600000 / (_odr)) + 5))
+#define ICM42607_ODR_TO_REG(_odr) \
+	((_odr) == 0 ? 0 : (__fls(1600000 / (_odr)) + 5))
 
 /* ODR in mHz from Reg value */
-#define ICM42607_REG_TO_ODR(_reg)	((_reg) <= 5 ? 1600000 : \
-					 (1600000 / (1 << ((_reg) - 5))))
+#define ICM42607_REG_TO_ODR(_reg) \
+	((_reg) <= 5 ? 1600000 : (1600000 / (1 << ((_reg)-5))))
 
 /* Reg value for the next higher ODR */
-#define ICM42607_ODR_REG_UP(_reg)	((_reg) - 1)
+#define ICM42607_ODR_REG_UP(_reg) ((_reg)-1)
 
 /*
  * Filter bandwidth values from ODR reg
@@ -77,10 +73,8 @@
  *   50Hz (10) -> 25Hz (6)
  *   <= 25Hz (11) -> 16Hz (7)
  */
-#define ICM42607_ODR_TO_FILT_BW(_odr)	((_odr) <= 7 ? 1 : \
-					 (_odr) <= 9 ? (_odr) - 5 : \
-					 (_odr) == 10 ? 6 : \
-					 7)
+#define ICM42607_ODR_TO_FILT_BW(_odr) \
+	((_odr) <= 7 ? 1 : (_odr) <= 9 ? (_odr)-5 : (_odr) == 10 ? 6 : 7)
 
 /*
  * Register addresses are virtual address on 16 bits.
@@ -88,53 +82,53 @@
  * and LSB real register address.
  * ex: MREG2 (block 0x28) register 03 => 0x2803
  */
-#define ICM42607_REG_MCLK_RDY		0x0000
-#define ICM42607_MCLK_RDY		BIT(3)
+#define ICM42607_REG_MCLK_RDY 0x0000
+#define ICM42607_MCLK_RDY BIT(3)
 
-#define ICM42607_REG_DEVICE_CONFIG	0x0001
-#define ICM42607_SPI_MODE_1_2		BIT(0)
-#define ICM42607_SPI_AP_4WIRE		BIT(2)
+#define ICM42607_REG_DEVICE_CONFIG 0x0001
+#define ICM42607_SPI_MODE_1_2 BIT(0)
+#define ICM42607_SPI_AP_4WIRE BIT(2)
 
-#define ICM42607_REG_SIGNAL_PATH_RESET	0x0002
-#define ICM42607_SOFT_RESET_DEV_CONFIG	BIT(4)
-#define ICM42607_FIFO_FLUSH		BIT(2)
+#define ICM42607_REG_SIGNAL_PATH_RESET 0x0002
+#define ICM42607_SOFT_RESET_DEV_CONFIG BIT(4)
+#define ICM42607_FIFO_FLUSH BIT(2)
 
-#define ICM42607_REG_DRIVE_CONFIG1	0x0003
+#define ICM42607_REG_DRIVE_CONFIG1 0x0003
 
-#define ICM42607_REG_DRIVE_CONFIG2	0x0004
+#define ICM42607_REG_DRIVE_CONFIG2 0x0004
 
-#define ICM42607_REG_DRIVE_CONFIG3	0x0005
+#define ICM42607_REG_DRIVE_CONFIG3 0x0005
 
 /* default int configuration is pulsed mode, open drain, and active low */
-#define ICM42607_REG_INT_CONFIG		0x0006
-#define ICM42607_INT2_MASK		GENMASK(5, 3)
-#define ICM42607_INT2_LATCHED		BIT(5)
-#define ICM42607_INT2_PUSH_PULL		BIT(4)
-#define ICM42607_INT2_ACTIVE_HIGH	BIT(3)
-#define ICM42607_INT1_MASK		GENMASK(2, 0)
-#define ICM42607_INT1_LATCHED		BIT(2)
-#define ICM42607_INT1_PUSH_PULL		BIT(1)
-#define ICM42607_INT1_ACTIVE_HIGH	BIT(0)
+#define ICM42607_REG_INT_CONFIG 0x0006
+#define ICM42607_INT2_MASK GENMASK(5, 3)
+#define ICM42607_INT2_LATCHED BIT(5)
+#define ICM42607_INT2_PUSH_PULL BIT(4)
+#define ICM42607_INT2_ACTIVE_HIGH BIT(3)
+#define ICM42607_INT1_MASK GENMASK(2, 0)
+#define ICM42607_INT1_LATCHED BIT(2)
+#define ICM42607_INT1_PUSH_PULL BIT(1)
+#define ICM42607_INT1_ACTIVE_HIGH BIT(0)
 
 /* data are 16 bits */
-#define ICM42607_REG_TEMP_DATA		0x0009
+#define ICM42607_REG_TEMP_DATA 0x0009
 
 /* X + Y + Z: 3 * 16 bits */
-#define ICM42607_REG_ACCEL_DATA_XYZ	0x000B
-#define ICM42607_REG_GYRO_DATA_XYZ	0x0011
+#define ICM42607_REG_ACCEL_DATA_XYZ 0x000B
+#define ICM42607_REG_GYRO_DATA_XYZ 0x0011
 
-#define ICM42607_INVALID_DATA		-32768
+#define ICM42607_INVALID_DATA -32768
 
 /* data are 16 bits */
-#define ICM42607_REG_TMST_FSYNCH	0x0017
+#define ICM42607_REG_TMST_FSYNCH 0x0017
 
-#define ICM42607_REG_PWR_MGMT0		0x001F
-#define ICM42607_ACCEL_LP_CLK_SEL	BIT(7)
-#define ICM42607_IDLE			BIT(4)
-#define ICM42607_GYRO_MODE_MASK		GENMASK(3, 2)
-#define ICM42607_GYRO_MODE(_m)		(((_m) & 0x03) << 2)
-#define ICM42607_ACCEL_MODE_MASK	GENMASK(1, 0)
-#define ICM42607_ACCEL_MODE(_m)		((_m) & 0x03)
+#define ICM42607_REG_PWR_MGMT0 0x001F
+#define ICM42607_ACCEL_LP_CLK_SEL BIT(7)
+#define ICM42607_IDLE BIT(4)
+#define ICM42607_GYRO_MODE_MASK GENMASK(3, 2)
+#define ICM42607_GYRO_MODE(_m) (((_m)&0x03) << 2)
+#define ICM42607_ACCEL_MODE_MASK GENMASK(1, 0)
+#define ICM42607_ACCEL_MODE(_m) ((_m)&0x03)
 
 enum icm42607_sensor_mode {
 	ICM42607_MODE_OFF,
@@ -143,14 +137,14 @@ enum icm42607_sensor_mode {
 	ICM42607_MODE_LOW_NOISE,
 };
 
-#define ICM42607_REG_GYRO_CONFIG0	0x0020
-#define ICM42607_REG_ACCEL_CONFIG0	0x0021
-#define ICM42607_FS_MASK		GENMASK(6, 5)
-#define ICM42607_FS_SEL(_fs)		(((_fs) & 0x03) << 5)
-#define ICM42607_ODR_MASK		GENMASK(3, 0)
-#define ICM42607_ODR(_odr)		((_odr) & 0x0F)
+#define ICM42607_REG_GYRO_CONFIG0 0x0020
+#define ICM42607_REG_ACCEL_CONFIG0 0x0021
+#define ICM42607_FS_MASK GENMASK(6, 5)
+#define ICM42607_FS_SEL(_fs) (((_fs)&0x03) << 5)
+#define ICM42607_ODR_MASK GENMASK(3, 0)
+#define ICM42607_ODR(_odr) ((_odr)&0x0F)
 
-#define ICM42607_REG_TEMP_CONFIG0	0x0022
+#define ICM42607_REG_TEMP_CONFIG0 0x0022
 
 enum icm42607_ui_avg {
 	ICM42607_UI_AVG_2X,
@@ -172,122 +166,122 @@ enum icm42607_ui_filt_bw {
 	ICM42607_UI_FILT_BW_16HZ,
 };
 
-#define ICM42607_REG_GYRO_CONFIG1	0x0023
-#define ICM42607_REG_ACCEL_CONFIG1	0x0024
-#define ICM42607_UI_AVG_MASK		GENMASK(6, 4)
-#define ICM42607_UI_AVG_SET(_avg)	(((_avg) & 0x07) << 4)
-#define ICM42607_UI_FILT_BW_MASK	GENMASK(2, 0)
-#define ICM42607_UI_FILT_BW_SET(_filt)	((_filt) & 0x07)
+#define ICM42607_REG_GYRO_CONFIG1 0x0023
+#define ICM42607_REG_ACCEL_CONFIG1 0x0024
+#define ICM42607_UI_AVG_MASK GENMASK(6, 4)
+#define ICM42607_UI_AVG_SET(_avg) (((_avg)&0x07) << 4)
+#define ICM42607_UI_FILT_BW_MASK GENMASK(2, 0)
+#define ICM42607_UI_FILT_BW_SET(_filt) ((_filt)&0x07)
 
-#define ICM42607_REG_FIFO_CONFIG1	0x0028
-#define ICM42607_REG_FIFO_CONFIG2	0x0029
-#define ICM42607_REG_FIFO_CONFIG3	0x002A
-#define ICM42607_FIFO_STOP_ON_FULL_MODE	BIT(1)
-#define ICM42607_FIFO_BYPASS		BIT(0)
-#define ICM42607_FIFO_MODE_STREAM	0x00
+#define ICM42607_REG_FIFO_CONFIG1 0x0028
+#define ICM42607_REG_FIFO_CONFIG2 0x0029
+#define ICM42607_REG_FIFO_CONFIG3 0x002A
+#define ICM42607_FIFO_STOP_ON_FULL_MODE BIT(1)
+#define ICM42607_FIFO_BYPASS BIT(0)
+#define ICM42607_FIFO_MODE_STREAM 0x00
 
 /* FIFO watermark value is 16 bits little endian */
-#define ICM42607_REG_FIFO_WM		0x0029
-
-#define ICM42607_REG_INT_SOURCE0	0x002B
-#define ICM42607_ST_INT1_EN		BIT(7)
-#define ICM42607_FSYNC_INT1_EN		BIT(6)
-#define ICM42607_PLL_RDY_INT1_EN	BIT(5)
-#define ICM42607_RESET_DONE_INT1_EN	BIT(4)
-#define ICM42607_DRDY_INT1_EN		BIT(3)
-#define ICM42607_FIFO_THS_INT1_EN	BIT(2)
-#define ICM42607_FIFO_FULL_INT1_EN	BIT(1)
-#define ICM42607_UI_AGC_RDY_INT1_EN	BIT(0)
-
-#define ICM42607_REG_INTF_CONFIG0	0x0035
-#define ICM42607_FIFO_COUNT_FORMAT	BIT(6)
-#define ICM42607_FIFO_COUNT_ENDIAN	BIT(5)
-#define ICM42607_SENSOR_DATA_ENDIAN	BIT(4)
-
-#define ICM42607_REG_INTF_CONFIG1	0x0036
-#define ICM42607_I3C_SDR_EN		BIT(3)
-#define ICM42607_I3C_DDR_EN		BIT(2)
-#define ICM42607_CLKSEL_MASK		GENMASK(1, 0)
-#define ICM42607_CLKSEL_PLL_ENABLE	0x01
-
-#define ICM42607_REG_INT_STATUS_DRDY	0x0039
-#define ICM42607_DATA_RDY_INT		BIT(0)
-
-#define ICM42607_REG_INT_STATUS		0x003A
-#define ICM42607_ST_INT			BIT(7)
-#define ICM42607_FSYNC_INT		BIT(6)
-#define ICM42607_PLL_RDY_INT		BIT(5)
-#define ICM42607_RESET_DONE_INT		BIT(4)
-#define ICM42607_FIFO_THS_INT		BIT(2)
-#define ICM42607_FIFO_FULL_INT		BIT(1)
-#define ICM42607_AGC_RDY_INT		BIT(0)
+#define ICM42607_REG_FIFO_WM 0x0029
+
+#define ICM42607_REG_INT_SOURCE0 0x002B
+#define ICM42607_ST_INT1_EN BIT(7)
+#define ICM42607_FSYNC_INT1_EN BIT(6)
+#define ICM42607_PLL_RDY_INT1_EN BIT(5)
+#define ICM42607_RESET_DONE_INT1_EN BIT(4)
+#define ICM42607_DRDY_INT1_EN BIT(3)
+#define ICM42607_FIFO_THS_INT1_EN BIT(2)
+#define ICM42607_FIFO_FULL_INT1_EN BIT(1)
+#define ICM42607_UI_AGC_RDY_INT1_EN BIT(0)
+
+#define ICM42607_REG_INTF_CONFIG0 0x0035
+#define ICM42607_FIFO_COUNT_FORMAT BIT(6)
+#define ICM42607_FIFO_COUNT_ENDIAN BIT(5)
+#define ICM42607_SENSOR_DATA_ENDIAN BIT(4)
+
+#define ICM42607_REG_INTF_CONFIG1 0x0036
+#define ICM42607_I3C_SDR_EN BIT(3)
+#define ICM42607_I3C_DDR_EN BIT(2)
+#define ICM42607_CLKSEL_MASK GENMASK(1, 0)
+#define ICM42607_CLKSEL_PLL_ENABLE 0x01
+
+#define ICM42607_REG_INT_STATUS_DRDY 0x0039
+#define ICM42607_DATA_RDY_INT BIT(0)
+
+#define ICM42607_REG_INT_STATUS 0x003A
+#define ICM42607_ST_INT BIT(7)
+#define ICM42607_FSYNC_INT BIT(6)
+#define ICM42607_PLL_RDY_INT BIT(5)
+#define ICM42607_RESET_DONE_INT BIT(4)
+#define ICM42607_FIFO_THS_INT BIT(2)
+#define ICM42607_FIFO_FULL_INT BIT(1)
+#define ICM42607_AGC_RDY_INT BIT(0)
 
 /* FIFO count is 16 bits */
-#define ICM42607_REG_FIFO_COUNT		0x003D
+#define ICM42607_REG_FIFO_COUNT 0x003D
 
-#define ICM42607_REG_FIFO_DATA		0x003F
+#define ICM42607_REG_FIFO_DATA 0x003F
 
-#define ICM42607_REG_APEX_CONFIG0	0x0025
-#define ICM42607_DMP_SRAM_RESET_APEX	BIT(0)
+#define ICM42607_REG_APEX_CONFIG0 0x0025
+#define ICM42607_DMP_SRAM_RESET_APEX BIT(0)
 
-#define ICM42607_REG_APEX_CONFIG1	0x0026
-#define ICM42607_DMP_ODR_50HZ		BIT(1)
+#define ICM42607_REG_APEX_CONFIG1 0x0026
+#define ICM42607_DMP_ODR_50HZ BIT(1)
 
-#define ICM42607_REG_WHO_AM_I		0x0075
-#define ICM42607_CHIP_ICM42607P		0x60
+#define ICM42607_REG_WHO_AM_I 0x0075
+#define ICM42607_CHIP_ICM42607P 0x60
 
 /* MREG read access registers */
-#define ICM42607_REG_BLK_SEL_W		0x0079
-#define ICM42607_REG_MADDR_W		0x007A
-#define ICM42607_REG_M_W		0x007B
+#define ICM42607_REG_BLK_SEL_W 0x0079
+#define ICM42607_REG_MADDR_W 0x007A
+#define ICM42607_REG_M_W 0x007B
 
 /* MREG write access registers */
-#define ICM42607_REG_BLK_SEL_R		0x007C
-#define ICM42607_REG_MADDR_R		0x007D
-#define ICM42607_REG_M_R		0x007E
+#define ICM42607_REG_BLK_SEL_R 0x007C
+#define ICM42607_REG_MADDR_R 0x007D
+#define ICM42607_REG_M_R 0x007E
 
 /* USER BANK MREG1 */
-#define ICM42607_MREG_FIFO_CONFIG5	0x0001
-#define ICM42607_FIFO_WM_GT_TH		BIT(5)
-#define ICM42607_FIFO_RESUME_PARTIAL_RD	BIT(4)
-#define ICM42607_FIFO_HIRES_EN		BIT(3)
-#define ICM42607_FIFO_TMST_FSYNC_EN	BIT(2)
-#define ICM42607_FIFO_GYRO_EN		BIT(1)
-#define ICM42607_FIFO_ACCEL_EN		BIT(0)
-
-#define ICM42607_MREG_OTP_CONFIG	0x002B
-#define ICM42607_OTP_COPY_MODE_MASK	GENMASK(3, 2)
-#define ICM42607_OTP_COPY_TRIM		(0x01 << 2)
-#define ICM42607_OTP_COPY_ST_DATA	(0x03 << 2)
-
-#define ICM42607_MREG_INT_SOURCE7	0x0030
-#define ICM42607_MREG_INT_SOURCE8	0x0031
-#define ICM42607_MREG_INT_SOURCE9	0x0032
-#define ICM42607_MREG_INT_SOURCE10	0x0033
-
-#define ICM42607_MREG_APEX_CONFIG2	0x0044
-#define ICM42607_MREG_APEX_CONFIG3	0x0045
-#define ICM42607_MREG_APEX_CONFIG4	0x0046
-#define ICM42607_MREG_APEX_CONFIG5	0x0047
-#define ICM42607_MREG_APEX_CONFIG9	0x0048
-#define ICM42607_MREG_APEX_CONFIG10	0x0049
-#define ICM42607_MREG_APEX_CONFIG11	0x004A
-#define ICM42607_MREG_APEX_CONFIG12	0x0067
-
-#define ICM42607_MREG_OFFSET_USER0	0x004E
-#define ICM42607_MREG_OFFSET_USER1	0x004F
-#define ICM42607_MREG_OFFSET_USER2	0x0050
-#define ICM42607_MREG_OFFSET_USER3	0x0051
-#define ICM42607_MREG_OFFSET_USER4	0x0052
-#define ICM42607_MREG_OFFSET_USER5	0x0053
-#define ICM42607_MREG_OFFSET_USER6	0x0054
-#define ICM42607_MREG_OFFSET_USER7	0x0055
-#define ICM42607_MREG_OFFSET_USER8	0x0056
+#define ICM42607_MREG_FIFO_CONFIG5 0x0001
+#define ICM42607_FIFO_WM_GT_TH BIT(5)
+#define ICM42607_FIFO_RESUME_PARTIAL_RD BIT(4)
+#define ICM42607_FIFO_HIRES_EN BIT(3)
+#define ICM42607_FIFO_TMST_FSYNC_EN BIT(2)
+#define ICM42607_FIFO_GYRO_EN BIT(1)
+#define ICM42607_FIFO_ACCEL_EN BIT(0)
+
+#define ICM42607_MREG_OTP_CONFIG 0x002B
+#define ICM42607_OTP_COPY_MODE_MASK GENMASK(3, 2)
+#define ICM42607_OTP_COPY_TRIM (0x01 << 2)
+#define ICM42607_OTP_COPY_ST_DATA (0x03 << 2)
+
+#define ICM42607_MREG_INT_SOURCE7 0x0030
+#define ICM42607_MREG_INT_SOURCE8 0x0031
+#define ICM42607_MREG_INT_SOURCE9 0x0032
+#define ICM42607_MREG_INT_SOURCE10 0x0033
+
+#define ICM42607_MREG_APEX_CONFIG2 0x0044
+#define ICM42607_MREG_APEX_CONFIG3 0x0045
+#define ICM42607_MREG_APEX_CONFIG4 0x0046
+#define ICM42607_MREG_APEX_CONFIG5 0x0047
+#define ICM42607_MREG_APEX_CONFIG9 0x0048
+#define ICM42607_MREG_APEX_CONFIG10 0x0049
+#define ICM42607_MREG_APEX_CONFIG11 0x004A
+#define ICM42607_MREG_APEX_CONFIG12 0x0067
+
+#define ICM42607_MREG_OFFSET_USER0 0x004E
+#define ICM42607_MREG_OFFSET_USER1 0x004F
+#define ICM42607_MREG_OFFSET_USER2 0x0050
+#define ICM42607_MREG_OFFSET_USER3 0x0051
+#define ICM42607_MREG_OFFSET_USER4 0x0052
+#define ICM42607_MREG_OFFSET_USER5 0x0053
+#define ICM42607_MREG_OFFSET_USER6 0x0054
+#define ICM42607_MREG_OFFSET_USER7 0x0055
+#define ICM42607_MREG_OFFSET_USER8 0x0056
 
 /* USER BANK MREG2 */
-#define ICM42607_MREG_OTP_CTRL7		0x2806
-#define ICM42607_OTP_RELOAD		BIT(3)
-#define ICM42607_OTP_PWR_DOWN		BIT(1)
+#define ICM42607_MREG_OTP_CTRL7 0x2806
+#define ICM42607_OTP_RELOAD BIT(3)
+#define ICM42607_OTP_PWR_DOWN BIT(1)
 
 extern const struct accelgyro_drv icm42607_drv;
 
diff --git a/driver/accelgyro_icm426xx.c b/driver/accelgyro_icm426xx.c
index 1c88d4b305..0311ed8187 100644
--- a/driver/accelgyro_icm426xx.c
+++ b/driver/accelgyro_icm426xx.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,11 +27,11 @@
 #endif
 
 #define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args)
 
 STATIC_IF(ACCELGYRO_ICM426XX_INT_ENABLE)
-	volatile uint32_t last_interrupt_timestamp;
+volatile uint32_t last_interrupt_timestamp;
 
 static int icm426xx_normalize(const struct motion_sensor_t *s, intv3_t v,
 			      const uint8_t *raw)
@@ -45,8 +45,7 @@ static int icm426xx_normalize(const struct motion_sensor_t *s, intv3_t v,
 	v[Z] = (int16_t)UINT16_FROM_BYTE_ARRAY_LE(raw, 4);
 
 	/* check if data is valid */
-	if (v[X] == ICM426XX_INVALID_DATA &&
-	    v[Y] == ICM426XX_INVALID_DATA &&
+	if (v[X] == ICM426XX_INVALID_DATA && v[Y] == ICM426XX_INVALID_DATA &&
 	    v[Z] == ICM426XX_INVALID_DATA) {
 		return EC_ERROR_INVAL;
 	}
@@ -76,8 +75,8 @@ static int icm426xx_check_sensor_stabilized(const struct motion_sensor_t *s,
 }
 
 /* use FIFO threshold interrupt on INT1 */
-#define ICM426XX_FIFO_INT_EN		ICM426XX_FIFO_THS_INT1_EN
-#define ICM426XX_FIFO_INT_STATUS	ICM426XX_FIFO_THS_INT
+#define ICM426XX_FIFO_INT_EN ICM426XX_FIFO_THS_INT1_EN
+#define ICM426XX_FIFO_INT_STATUS ICM426XX_FIFO_THS_INT
 
 static int __maybe_unused icm426xx_enable_fifo(const struct motion_sensor_t *s,
 					       int enable)
@@ -184,7 +183,8 @@ out_unlock:
 }
 
 static void __maybe_unused icm426xx_push_fifo_data(struct motion_sensor_t *s,
-						const uint8_t *raw, uint32_t ts)
+						   const uint8_t *raw,
+						   uint32_t ts)
 {
 	intv3_t v;
 	struct ec_response_motion_sensor_data vect;
@@ -232,8 +232,8 @@ static int __maybe_unused icm426xx_load_fifo(struct motion_sensor_t *s,
 		return ret;
 
 	for (i = 0; i < count; i += size) {
-		size = icm_fifo_decode_packet(&st->fifo_buffer[i],
-				&accel, &gyro);
+		size = icm_fifo_decode_packet(&st->fifo_buffer[i], &accel,
+					      &gyro);
 		/* exit if error or FIFO is empty */
 		if (size <= 0)
 			return -size;
@@ -310,7 +310,7 @@ static int icm426xx_config_interrupt(const struct motion_sensor_t *s)
 
 	/* deassert async reset for proper INT pin operation */
 	ret = icm_field_update8(s, ICM426XX_REG_INT_CONFIG1,
-			ICM426XX_INT_ASYNC_RESET, 0);
+				ICM426XX_INT_ASYNC_RESET, 0);
 	if (ret != EC_SUCCESS)
 		return ret;
 
@@ -322,8 +322,7 @@ static int icm426xx_config_interrupt(const struct motion_sensor_t *s)
 	 */
 	val = ICM426XX_FIFO_PARTIAL_READ | ICM426XX_FIFO_WM_GT_TH;
 	ret = icm_field_update8(s, ICM426XX_REG_FIFO_CONFIG1,
-			GENMASK(6, 5) | ICM426XX_FIFO_EN_MASK,
-			val);
+				GENMASK(6, 5) | ICM426XX_FIFO_EN_MASK, val);
 	if (ret != EC_SUCCESS)
 		return ret;
 
@@ -337,7 +336,7 @@ static int icm426xx_config_interrupt(const struct motion_sensor_t *s)
 	return ret;
 }
 
-#endif	/* ACCELGYRO_ICM426XX_INT_ENABLE */
+#endif /* ACCELGYRO_ICM426XX_INT_ENABLE */
 
 static int icm426xx_enable_sensor(const struct motion_sensor_t *s, int enable)
 {
@@ -431,7 +430,7 @@ static int icm426xx_set_data_rate(const struct motion_sensor_t *s, int rate,
 
 	if (rate > 0) {
 		if ((normalized_rate < min_rate) ||
-			(normalized_rate > max_rate))
+		    (normalized_rate > max_rate))
 			return EC_RES_INVALID_PARAM;
 	}
 
@@ -470,8 +469,7 @@ out_unlock:
 	return ret;
 }
 
-static int icm426xx_set_range(struct motion_sensor_t *s, int range,
-			      int rnd)
+static int icm426xx_set_range(struct motion_sensor_t *s, int range, int rnd)
 {
 	int reg, ret, reg_val;
 	int newrange;
@@ -536,8 +534,8 @@ static int icm426xx_get_hw_offset(const struct motion_sensor_t *s,
 	switch (s->type) {
 	case MOTIONSENSE_TYPE_ACCEL:
 		mutex_lock(s->mutex);
-		ret = icm_read_n(s, ICM426XX_REG_OFFSET_USER4,
-				raw, sizeof(raw));
+		ret = icm_read_n(s, ICM426XX_REG_OFFSET_USER4, raw,
+				 sizeof(raw));
 		mutex_unlock(s->mutex);
 		if (ret != EC_SUCCESS)
 			return ret;
@@ -554,8 +552,8 @@ static int icm426xx_get_hw_offset(const struct motion_sensor_t *s,
 		break;
 	case MOTIONSENSE_TYPE_GYRO:
 		mutex_lock(s->mutex);
-		ret = icm_read_n(s, ICM426XX_REG_OFFSET_USER0,
-				raw, sizeof(raw));
+		ret = icm_read_n(s, ICM426XX_REG_OFFSET_USER0, raw,
+				 sizeof(raw));
 		mutex_unlock(s->mutex);
 		if (ret != EC_SUCCESS)
 			return ret;
diff --git a/driver/accelgyro_icm426xx.h b/driver/accelgyro_icm426xx.h
index 9162f27b8c..704256cb68 100644
--- a/driver/accelgyro_icm426xx.h
+++ b/driver/accelgyro_icm426xx.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,72 +15,69 @@
  * 7-bit address is 110100Xb. Where 'X' is determined
  * by the logic level on pin AP_AD0.
  */
-#define ICM426XX_ADDR0_FLAGS		0x68
-#define ICM426XX_ADDR1_FLAGS		0x69
+#define ICM426XX_ADDR0_FLAGS 0x68
+#define ICM426XX_ADDR1_FLAGS 0x69
 
 /* Min and Max sampling frequency in mHz */
-#define ICM426XX_ACCEL_MIN_FREQ	3125
-#define ICM426XX_ACCEL_MAX_FREQ	MOTION_MAX_SENSOR_FREQUENCY(500000, 100000)
-#define ICM426XX_GYRO_MIN_FREQ	12500
-#define ICM426XX_GYRO_MAX_FREQ	MOTION_MAX_SENSOR_FREQUENCY(4000000, 100000)
+#define ICM426XX_ACCEL_MIN_FREQ 3125
+#define ICM426XX_ACCEL_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(500000, 100000)
+#define ICM426XX_GYRO_MIN_FREQ 12500
+#define ICM426XX_GYRO_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(4000000, 100000)
 
 /* Min and Max Accel FS in G */
-#define ICM426XX_ACCEL_FS_MIN_VAL	2
-#define ICM426XX_ACCEL_FS_MAX_VAL	16
+#define ICM426XX_ACCEL_FS_MIN_VAL 2
+#define ICM426XX_ACCEL_FS_MAX_VAL 16
 
 /* Min and Max Gyro FS in dps */
-#define ICM426XX_GYRO_FS_MIN_VAL	125
-#define ICM426XX_GYRO_FS_MAX_VAL	2000
+#define ICM426XX_GYRO_FS_MIN_VAL 125
+#define ICM426XX_GYRO_FS_MAX_VAL 2000
 
 /* accel stabilization time in us */
-#define ICM426XX_ACCEL_START_TIME	20000
-#define ICM426XX_ACCEL_STOP_TIME	0
+#define ICM426XX_ACCEL_START_TIME 20000
+#define ICM426XX_ACCEL_STOP_TIME 0
 
 /* gyro stabilization time in us */
-#define ICM426XX_GYRO_START_TIME	60000
-#define ICM426XX_GYRO_STOP_TIME		150000
+#define ICM426XX_GYRO_START_TIME 60000
+#define ICM426XX_GYRO_STOP_TIME 150000
 
 /* Reg value from Accel FS in G */
-#define ICM426XX_ACCEL_FS_TO_REG(_fs)	((_fs) < 2 ? 3 : \
-					(_fs) > 16 ? 0 : \
-					3 - __fls((_fs) / 2))
+#define ICM426XX_ACCEL_FS_TO_REG(_fs) \
+	((_fs) < 2 ? 3 : (_fs) > 16 ? 0 : 3 - __fls((_fs) / 2))
 
 /* Accel FSR in G from Reg value */
-#define ICM426XX_ACCEL_REG_TO_FS(_reg)	((1 << (3 - (_reg))) * 2)
+#define ICM426XX_ACCEL_REG_TO_FS(_reg) ((1 << (3 - (_reg))) * 2)
 
 /* Reg value from Gyro FS in dps */
-#define ICM426XX_GYRO_FS_TO_REG(_fs)	((_fs) < 125 ? 4 : \
-					(_fs) > 2000 ? 0 : \
-					4 - __fls((_fs) / 125))
+#define ICM426XX_GYRO_FS_TO_REG(_fs) \
+	((_fs) < 125 ? 4 : (_fs) > 2000 ? 0 : 4 - __fls((_fs) / 125))
 
 /* Gyro FSR in dps from Reg value */
-#define ICM426XX_GYRO_REG_TO_FS(_reg)	((1 << (4 - (_reg))) * 125)
+#define ICM426XX_GYRO_REG_TO_FS(_reg) ((1 << (4 - (_reg))) * 125)
 
 /* Reg value from ODR in mHz */
-#define ICM426XX_ODR_TO_REG(_odr)	((_odr) <= 200000 ? \
-					13 - __fls((_odr) / 3125) : \
-					(_odr) < 500000 ? 7 : \
-					(_odr) < 1000000 ? 15 : \
-					6 - __fls((_odr) / 1000000))
+#define ICM426XX_ODR_TO_REG(_odr)                       \
+	((_odr) <= 200000 ? 13 - __fls((_odr) / 3125) : \
+	 (_odr) < 500000  ? 7 :                         \
+	 (_odr) < 1000000 ? 15 :                        \
+			    6 - __fls((_odr) / 1000000))
 
 /* ODR in mHz from Reg value */
-#define ICM426XX_REG_TO_ODR(_reg)	((_reg) == 15 ? 500000 : \
-					(_reg) >= 7 ? \
-					(1 << (13 - (_reg))) * 3125 : \
-					(1 << (6 - (_reg))) * 1000000)
+#define ICM426XX_REG_TO_ODR(_reg)                     \
+	((_reg) == 15 ? 500000 :                      \
+	 (_reg) >= 7  ? (1 << (13 - (_reg))) * 3125 : \
+			(1 << (6 - (_reg))) * 1000000)
 
 /* Reg value for the next higher ODR */
-#define ICM426XX_ODR_REG_UP(_reg)	((_reg) == 15 ? 6 : \
-					(_reg) == 7 ? 15 : \
-					(_reg) - 1)
+#define ICM426XX_ODR_REG_UP(_reg) \
+	((_reg) == 15 ? 6 : (_reg) == 7 ? 15 : (_reg)-1)
 
 /*
  * Register addresses are virtual address on 16 bits.
  * MSB is coding register bank and LSB real register address.
  * ex: bank 4, register 1F => 0x041F
  */
-#define ICM426XX_REG_DEVICE_CONFIG	0x0011
-#define ICM426XX_SOFT_RESET_CONFIG	BIT(0)
+#define ICM426XX_REG_DEVICE_CONFIG 0x0011
+#define ICM426XX_SOFT_RESET_CONFIG BIT(0)
 
 enum icm426xx_slew_rate {
 	ICM426XX_SLEW_RATE_20NS_60NS,
@@ -90,63 +87,63 @@ enum icm426xx_slew_rate {
 	ICM426XX_SLEW_RATE_2NS_6NS,
 	ICM426XX_SLEW_RATE_INF_2NS,
 };
-#define ICM426XX_REG_DRIVE_CONFIG	0x0013
-#define ICM426XX_DRIVE_CONFIG_MASK	GENMASK(5, 0)
-#define ICM426XX_I2C_SLEW_RATE(_s)	(((_s) & 0x07) << 3)
-#define ICM426XX_SPI_SLEW_RATE(_s)	((_s) & 0x07)
+#define ICM426XX_REG_DRIVE_CONFIG 0x0013
+#define ICM426XX_DRIVE_CONFIG_MASK GENMASK(5, 0)
+#define ICM426XX_I2C_SLEW_RATE(_s) (((_s)&0x07) << 3)
+#define ICM426XX_SPI_SLEW_RATE(_s) ((_s)&0x07)
 
 /* default int configuration is pulsed mode, open drain, and active low */
-#define ICM426XX_REG_INT_CONFIG		0x0014
-#define ICM426XX_INT2_LATCHED		BIT(5)
-#define ICM426XX_INT2_PUSH_PULL		BIT(4)
-#define ICM426XX_INT2_ACTIVE_HIGH	BIT(3)
-#define ICM426XX_INT1_LATCHED		BIT(2)
-#define ICM426XX_INT1_PUSH_PULL		BIT(1)
-#define ICM426XX_INT1_ACTIVE_HIGH	BIT(0)
-
-#define ICM426XX_REG_FIFO_CONFIG	0x0016
-#define ICM426XX_FIFO_MODE_BYPASS	(0x00 << 6)
-#define ICM426XX_FIFO_MODE_STREAM	(0x01 << 6)
-#define ICM426XX_FIFO_MODE_STOP_FULL	(0x02 << 6)
+#define ICM426XX_REG_INT_CONFIG 0x0014
+#define ICM426XX_INT2_LATCHED BIT(5)
+#define ICM426XX_INT2_PUSH_PULL BIT(4)
+#define ICM426XX_INT2_ACTIVE_HIGH BIT(3)
+#define ICM426XX_INT1_LATCHED BIT(2)
+#define ICM426XX_INT1_PUSH_PULL BIT(1)
+#define ICM426XX_INT1_ACTIVE_HIGH BIT(0)
+
+#define ICM426XX_REG_FIFO_CONFIG 0x0016
+#define ICM426XX_FIFO_MODE_BYPASS (0x00 << 6)
+#define ICM426XX_FIFO_MODE_STREAM (0x01 << 6)
+#define ICM426XX_FIFO_MODE_STOP_FULL (0x02 << 6)
 
 /* data are 16 bits */
-#define ICM426XX_REG_TEMP_DATA		0x001D
+#define ICM426XX_REG_TEMP_DATA 0x001D
 /* X + Y + Z: 3 * 16 bits */
-#define ICM426XX_REG_ACCEL_DATA_XYZ	0x001F
-#define ICM426XX_REG_GYRO_DATA_XYZ	0x0025
+#define ICM426XX_REG_ACCEL_DATA_XYZ 0x001F
+#define ICM426XX_REG_GYRO_DATA_XYZ 0x0025
 
-#define ICM426XX_INVALID_DATA		-32768
+#define ICM426XX_INVALID_DATA -32768
 
-#define ICM426XX_REG_INT_STATUS		0x002D
-#define ICM426XX_UI_FSYNC_INT		BIT(6)
-#define ICM426XX_PLL_RDY_INT		BIT(5)
-#define ICM426XX_RESET_DONE_INT		BIT(4)
-#define ICM426XX_DATA_RDY_INT		BIT(3)
-#define ICM426XX_FIFO_THS_INT		BIT(2)
-#define ICM426XX_FIFO_FULL_INT		BIT(1)
-#define ICM426XX_AGC_RDY_INT		BIT(0)
+#define ICM426XX_REG_INT_STATUS 0x002D
+#define ICM426XX_UI_FSYNC_INT BIT(6)
+#define ICM426XX_PLL_RDY_INT BIT(5)
+#define ICM426XX_RESET_DONE_INT BIT(4)
+#define ICM426XX_DATA_RDY_INT BIT(3)
+#define ICM426XX_FIFO_THS_INT BIT(2)
+#define ICM426XX_FIFO_FULL_INT BIT(1)
+#define ICM426XX_AGC_RDY_INT BIT(0)
 
 /* FIFO count is 16 bits */
-#define ICM426XX_REG_FIFO_COUNT		0x002E
-#define ICM426XX_REG_FIFO_DATA		0x0030
-
-#define ICM426XX_REG_SIGNAL_PATH_RESET	0x004B
-#define ICM426XX_ABORT_AND_RESET	BIT(3)
-#define ICM426XX_TMST_STROBE		BIT(2)
-#define ICM426XX_FIFO_FLUSH		BIT(1)
-
-#define ICM426XX_REG_INTF_CONFIG0	0x004C
-#define ICM426XX_DATA_CONF_MASK		GENMASK(7, 4)
-#define ICM426XX_FIFO_HOLD_LAST_DATA	BIT(7)
-#define ICM426XX_FIFO_COUNT_REC		BIT(6)
-#define ICM426XX_FIFO_COUNT_BE		BIT(5)
-#define ICM426XX_SENSOR_DATA_BE		BIT(4)
-#define ICM426XX_UI_SIFS_CFG_MASK	GENMASK(1, 0)
-#define ICM426XX_UI_SIFS_CFG_SPI_DIS	0x02
-#define ICM426XX_UI_SIFS_CFG_I2C_DIS	0x03
-
-#define ICM426XX_REG_INTF_CONFIG1	0x004D
-#define ICM426XX_ACCEL_LP_CLK_SEL	BIT(3)
+#define ICM426XX_REG_FIFO_COUNT 0x002E
+#define ICM426XX_REG_FIFO_DATA 0x0030
+
+#define ICM426XX_REG_SIGNAL_PATH_RESET 0x004B
+#define ICM426XX_ABORT_AND_RESET BIT(3)
+#define ICM426XX_TMST_STROBE BIT(2)
+#define ICM426XX_FIFO_FLUSH BIT(1)
+
+#define ICM426XX_REG_INTF_CONFIG0 0x004C
+#define ICM426XX_DATA_CONF_MASK GENMASK(7, 4)
+#define ICM426XX_FIFO_HOLD_LAST_DATA BIT(7)
+#define ICM426XX_FIFO_COUNT_REC BIT(6)
+#define ICM426XX_FIFO_COUNT_BE BIT(5)
+#define ICM426XX_SENSOR_DATA_BE BIT(4)
+#define ICM426XX_UI_SIFS_CFG_MASK GENMASK(1, 0)
+#define ICM426XX_UI_SIFS_CFG_SPI_DIS 0x02
+#define ICM426XX_UI_SIFS_CFG_I2C_DIS 0x03
+
+#define ICM426XX_REG_INTF_CONFIG1 0x004D
+#define ICM426XX_ACCEL_LP_CLK_SEL BIT(3)
 
 enum icm426xx_sensor_mode {
 	ICM426XX_MODE_OFF,
@@ -154,20 +151,20 @@ enum icm426xx_sensor_mode {
 	ICM426XX_MODE_LOW_POWER,
 	ICM426XX_MODE_LOW_NOISE,
 };
-#define ICM426XX_REG_PWR_MGMT0		0x004E
-#define ICM426XX_TEMP_DIS		BIT(5)
-#define ICM426XX_IDLE			BIT(4)
-#define ICM426XX_GYRO_MODE_MASK		GENMASK(3, 2)
-#define ICM426XX_GYRO_MODE(_m)		(((_m) & 0x03) << 2)
-#define ICM426XX_ACCEL_MODE_MASK	GENMASK(1, 0)
-#define ICM426XX_ACCEL_MODE(_m)		((_m) & 0x03)
-
-#define ICM426XX_REG_GYRO_CONFIG0	0x004F
-#define ICM426XX_REG_ACCEL_CONFIG0	0x0050
-#define ICM426XX_FS_MASK		GENMASK(7, 5)
-#define ICM426XX_FS_SEL(_fs)		(((_fs) & 0x07) << 5)
-#define ICM426XX_ODR_MASK		GENMASK(3, 0)
-#define ICM426XX_ODR(_odr)		((_odr) & 0x0F)
+#define ICM426XX_REG_PWR_MGMT0 0x004E
+#define ICM426XX_TEMP_DIS BIT(5)
+#define ICM426XX_IDLE BIT(4)
+#define ICM426XX_GYRO_MODE_MASK GENMASK(3, 2)
+#define ICM426XX_GYRO_MODE(_m) (((_m)&0x03) << 2)
+#define ICM426XX_ACCEL_MODE_MASK GENMASK(1, 0)
+#define ICM426XX_ACCEL_MODE(_m) ((_m)&0x03)
+
+#define ICM426XX_REG_GYRO_CONFIG0 0x004F
+#define ICM426XX_REG_ACCEL_CONFIG0 0x0050
+#define ICM426XX_FS_MASK GENMASK(7, 5)
+#define ICM426XX_FS_SEL(_fs) (((_fs)&0x07) << 5)
+#define ICM426XX_ODR_MASK GENMASK(3, 0)
+#define ICM426XX_ODR(_odr) ((_odr)&0x0F)
 
 enum icm426xx_filter_bw {
 	/* low noise mode */
@@ -178,87 +175,87 @@ enum icm426xx_filter_bw {
 	ICM426XX_FILTER_BW_AVG_16X = 6,
 };
 
-#define ICM426XX_REG_GYRO_ACCEL_CONFIG0	0x0052
-#define ICM426XX_ACCEL_UI_FILT_MASK	GENMASK(7, 4)
-#define ICM426XX_ACCEL_UI_FILT_BW(_f)	(((_f) & 0x0F) << 4)
-#define ICM426XX_GYRO_UI_FILT_MASK	GENMASK(3, 0)
-#define ICM426XX_GYRO_UI_FILT_BW(_f)	((_f) & 0x0F)
-
-#define ICM426XX_REG_FIFO_CONFIG1	0x005F
-#define ICM426XX_FIFO_PARTIAL_READ	BIT(6)
-#define ICM426XX_FIFO_WM_GT_TH		BIT(5)
-#define ICM426XX_FIFO_EN_MASK		GENMASK(3, 0)
-#define ICM426XX_FIFO_TMST_FSYNC_EN	BIT(3)
-#define ICM426XX_FIFO_TEMP_EN		BIT(2)
-#define ICM426XX_FIFO_GYRO_EN		BIT(1)
-#define ICM426XX_FIFO_ACCEL_EN		BIT(0)
+#define ICM426XX_REG_GYRO_ACCEL_CONFIG0 0x0052
+#define ICM426XX_ACCEL_UI_FILT_MASK GENMASK(7, 4)
+#define ICM426XX_ACCEL_UI_FILT_BW(_f) (((_f)&0x0F) << 4)
+#define ICM426XX_GYRO_UI_FILT_MASK GENMASK(3, 0)
+#define ICM426XX_GYRO_UI_FILT_BW(_f) ((_f)&0x0F)
+
+#define ICM426XX_REG_FIFO_CONFIG1 0x005F
+#define ICM426XX_FIFO_PARTIAL_READ BIT(6)
+#define ICM426XX_FIFO_WM_GT_TH BIT(5)
+#define ICM426XX_FIFO_EN_MASK GENMASK(3, 0)
+#define ICM426XX_FIFO_TMST_FSYNC_EN BIT(3)
+#define ICM426XX_FIFO_TEMP_EN BIT(2)
+#define ICM426XX_FIFO_GYRO_EN BIT(1)
+#define ICM426XX_FIFO_ACCEL_EN BIT(0)
 
 /* FIFO watermark value is 16 bits little endian */
-#define ICM426XX_REG_FIFO_WATERMARK	0x0060
-
-#define ICM426XX_REG_INT_CONFIG1	0x0064
-#define ICM426XX_INT_PULSE_DURATION	BIT(6)
-#define ICM426XX_INT_TDEASSERT_DIS	BIT(5)
-#define ICM426XX_INT_ASYNC_RESET	BIT(4)
-
-#define ICM426XX_REG_INT_SOURCE0	0x0065
-#define ICM426XX_UI_FSYNC_INT1_EN	BIT(6)
-#define ICM426XX_PLL_RDY_INT1_EN	BIT(5)
-#define ICM426XX_RESET_DONE_INT1_EN	BIT(4)
-#define ICM426XX_UI_DRDY_INT1_EN	BIT(3)
-#define ICM426XX_FIFO_THS_INT1_EN	BIT(2)
-#define ICM426XX_FIFO_FULL_INT1_EN	BIT(1)
-#define ICM426XX_UI_AGC_RDY_INT1_EN	BIT(0)
-
-#define ICM426XX_REG_INT_SOURCE3	0x0068
-#define ICM426XX_UI_FSYNC_INT2_EN	BIT(6)
-#define ICM426XX_PLL_RDY_INT2_EN	BIT(5)
-#define ICM426XX_RESET_DONE_INT2_EN	BIT(4)
-#define ICM426XX_UI_DRDY_INT2_EN	BIT(3)
-#define ICM426XX_FIFO_THS_INT2_EN	BIT(2)
-#define ICM426XX_FIFO_FULL_INT2_EN	BIT(1)
-#define ICM426XX_UI_AGC_RDY_INT2_EN	BIT(0)
-
-#define ICM426XX_REG_WHO_AM_I		0x0075
-#define ICM426XX_CHIP_ICM40608		0x39
-#define ICM426XX_CHIP_ICM42605		0x42
-
-#define ICM426XX_REG_BANK_SEL		0x0076
-#define ICM426XX_BANK_SEL(_b)		((_b) & 0x07)
-
-#define ICM426XX_REG_INTF_CONFIG4	0x017A
-#define ICM426XX_I3C_BUS_MODE		BIT(6)
-#define ICM426XX_SPI_AP_4WIRE		BIT(1)
-
-#define ICM426XX_REG_INTF_CONFIG5	0x017B
-#define ICM426XX_PIN9_FUNC_INT2		(0x00 << 1)
-#define ICM426XX_PIN9_FUNC_FSYNC	(0x01 << 1)
-
-#define ICM426XX_REG_INTF_CONFIG6	0x017C
-#define ICM426XX_INTF_CONFIG6_MASK	GENMASK(4, 0)
-#define ICM426XX_I3C_EN			BIT(4)
-#define ICM426XX_I3C_IBI_BYTE_EN	BIT(3)
-#define ICM426XX_I3C_IBI_EN		BIT(2)
-#define ICM426XX_I3C_DDR_EN		BIT(1)
-#define ICM426XX_I3C_SDR_EN		BIT(0)
-
-#define ICM426XX_REG_INT_SOURCE8	0x044F
-#define ICM426XX_FSYNC_IBI_EN		BIT(5)
-#define ICM426XX_PLL_RDY_IBI_EN		BIT(4)
-#define ICM426XX_UI_DRDY_IBI_EN		BIT(3)
-#define ICM426XX_FIFO_THS_IBI_EN	BIT(2)
-#define ICM426XX_FIFO_FULL_IBI_EN	BIT(1)
-#define ICM426XX_AGC_RDY_IBI_EN		BIT(0)
-
-#define ICM426XX_REG_OFFSET_USER0	0x0477
-#define ICM426XX_REG_OFFSET_USER1	0x0478
-#define ICM426XX_REG_OFFSET_USER2	0x0479
-#define ICM426XX_REG_OFFSET_USER3	0x047A
-#define ICM426XX_REG_OFFSET_USER4	0x047B
-#define ICM426XX_REG_OFFSET_USER5	0x047C
-#define ICM426XX_REG_OFFSET_USER6	0x047D
-#define ICM426XX_REG_OFFSET_USER7	0x047E
-#define ICM426XX_REG_OFFSET_USER8	0x047F
+#define ICM426XX_REG_FIFO_WATERMARK 0x0060
+
+#define ICM426XX_REG_INT_CONFIG1 0x0064
+#define ICM426XX_INT_PULSE_DURATION BIT(6)
+#define ICM426XX_INT_TDEASSERT_DIS BIT(5)
+#define ICM426XX_INT_ASYNC_RESET BIT(4)
+
+#define ICM426XX_REG_INT_SOURCE0 0x0065
+#define ICM426XX_UI_FSYNC_INT1_EN BIT(6)
+#define ICM426XX_PLL_RDY_INT1_EN BIT(5)
+#define ICM426XX_RESET_DONE_INT1_EN BIT(4)
+#define ICM426XX_UI_DRDY_INT1_EN BIT(3)
+#define ICM426XX_FIFO_THS_INT1_EN BIT(2)
+#define ICM426XX_FIFO_FULL_INT1_EN BIT(1)
+#define ICM426XX_UI_AGC_RDY_INT1_EN BIT(0)
+
+#define ICM426XX_REG_INT_SOURCE3 0x0068
+#define ICM426XX_UI_FSYNC_INT2_EN BIT(6)
+#define ICM426XX_PLL_RDY_INT2_EN BIT(5)
+#define ICM426XX_RESET_DONE_INT2_EN BIT(4)
+#define ICM426XX_UI_DRDY_INT2_EN BIT(3)
+#define ICM426XX_FIFO_THS_INT2_EN BIT(2)
+#define ICM426XX_FIFO_FULL_INT2_EN BIT(1)
+#define ICM426XX_UI_AGC_RDY_INT2_EN BIT(0)
+
+#define ICM426XX_REG_WHO_AM_I 0x0075
+#define ICM426XX_CHIP_ICM40608 0x39
+#define ICM426XX_CHIP_ICM42605 0x42
+
+#define ICM426XX_REG_BANK_SEL 0x0076
+#define ICM426XX_BANK_SEL(_b) ((_b)&0x07)
+
+#define ICM426XX_REG_INTF_CONFIG4 0x017A
+#define ICM426XX_I3C_BUS_MODE BIT(6)
+#define ICM426XX_SPI_AP_4WIRE BIT(1)
+
+#define ICM426XX_REG_INTF_CONFIG5 0x017B
+#define ICM426XX_PIN9_FUNC_INT2 (0x00 << 1)
+#define ICM426XX_PIN9_FUNC_FSYNC (0x01 << 1)
+
+#define ICM426XX_REG_INTF_CONFIG6 0x017C
+#define ICM426XX_INTF_CONFIG6_MASK GENMASK(4, 0)
+#define ICM426XX_I3C_EN BIT(4)
+#define ICM426XX_I3C_IBI_BYTE_EN BIT(3)
+#define ICM426XX_I3C_IBI_EN BIT(2)
+#define ICM426XX_I3C_DDR_EN BIT(1)
+#define ICM426XX_I3C_SDR_EN BIT(0)
+
+#define ICM426XX_REG_INT_SOURCE8 0x044F
+#define ICM426XX_FSYNC_IBI_EN BIT(5)
+#define ICM426XX_PLL_RDY_IBI_EN BIT(4)
+#define ICM426XX_UI_DRDY_IBI_EN BIT(3)
+#define ICM426XX_FIFO_THS_IBI_EN BIT(2)
+#define ICM426XX_FIFO_FULL_IBI_EN BIT(1)
+#define ICM426XX_AGC_RDY_IBI_EN BIT(0)
+
+#define ICM426XX_REG_OFFSET_USER0 0x0477
+#define ICM426XX_REG_OFFSET_USER1 0x0478
+#define ICM426XX_REG_OFFSET_USER2 0x0479
+#define ICM426XX_REG_OFFSET_USER3 0x047A
+#define ICM426XX_REG_OFFSET_USER4 0x047B
+#define ICM426XX_REG_OFFSET_USER5 0x047C
+#define ICM426XX_REG_OFFSET_USER6 0x047D
+#define ICM426XX_REG_OFFSET_USER7 0x047E
+#define ICM426XX_REG_OFFSET_USER8 0x047F
 
 extern const struct accelgyro_drv icm426xx_drv;
 
diff --git a/driver/accelgyro_icm_common.c b/driver/accelgyro_icm_common.c
index 94db99407d..22a2b0820d 100644
--- a/driver/accelgyro_icm_common.c
+++ b/driver/accelgyro_icm_common.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,12 +16,12 @@
 #include "driver/accelgyro_icm426xx.h"
 
 #define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args)
 
 #ifdef CONFIG_ACCELGYRO_ICM_COMM_SPI
-static int icm_spi_raw_read(const int addr, const uint8_t reg,
-			    uint8_t *data, const int len)
+static int icm_spi_raw_read(const int addr, const uint8_t reg, uint8_t *data,
+			    const int len)
 {
 	uint8_t cmd = 0x80 | reg;
 
@@ -151,8 +151,7 @@ int icm_read16(const struct motion_sensor_t *s, const int reg, int *data_ptr)
 		}
 	}
 #else
-	ret = i2c_read16(s->port, s->i2c_spi_addr_flags,
-			addr, data_ptr);
+	ret = i2c_read16(s->port, s->i2c_spi_addr_flags, addr, data_ptr);
 #endif
 
 	return ret;
@@ -287,12 +286,12 @@ int icm_get_scale(const struct motion_sensor_t *s, uint16_t *scale,
 }
 
 /* FIFO header: 1 byte */
-#define ICM_FIFO_HEADER_MSG		BIT(7)
-#define ICM_FIFO_HEADER_ACCEL		BIT(6)
-#define ICM_FIFO_HEADER_GYRO		BIT(5)
-#define ICM_FIFO_HEADER_TMST_FSYNC	GENMASK(3, 2)
-#define ICM_FIFO_HEADER_ODR_ACCEL	BIT(1)
-#define ICM_FIFO_HEADER_ODR_GYRO	BIT(0)
+#define ICM_FIFO_HEADER_MSG BIT(7)
+#define ICM_FIFO_HEADER_ACCEL BIT(6)
+#define ICM_FIFO_HEADER_GYRO BIT(5)
+#define ICM_FIFO_HEADER_TMST_FSYNC GENMASK(3, 2)
+#define ICM_FIFO_HEADER_ODR_ACCEL BIT(1)
+#define ICM_FIFO_HEADER_ODR_GYRO BIT(0)
 
 /* FIFO data packet */
 struct icm_fifo_sensor_data {
@@ -306,7 +305,7 @@ struct icm_fifo_1sensor_packet {
 	struct icm_fifo_sensor_data data;
 	int8_t temp;
 } __packed;
-#define ICM_FIFO_1SENSOR_PACKET_SIZE	8
+#define ICM_FIFO_1SENSOR_PACKET_SIZE 8
 
 struct icm_fifo_2sensors_packet {
 	uint8_t header;
@@ -315,10 +314,10 @@ struct icm_fifo_2sensors_packet {
 	int8_t temp;
 	uint16_t timestamp;
 } __packed;
-#define ICM_FIFO_2SENSORS_PACKET_SIZE	16
+#define ICM_FIFO_2SENSORS_PACKET_SIZE 16
 
 ssize_t icm_fifo_decode_packet(const void *packet, const uint8_t **accel,
-		const uint8_t **gyro)
+			       const uint8_t **gyro)
 {
 	const struct icm_fifo_1sensor_packet *pack1 = packet;
 	const struct icm_fifo_2sensors_packet *pack2 = packet;
diff --git a/driver/accelgyro_icm_common.h b/driver/accelgyro_icm_common.h
index c6e6ce2ff2..400c56ba6f 100644
--- a/driver/accelgyro_icm_common.h
+++ b/driver/accelgyro_icm_common.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,6 +8,8 @@
 #ifndef __CROS_EC_ACCELGYRO_ICM_COMMON_H
 #define __CROS_EC_ACCELGYRO_ICM_COMMON_H
 
+#include <sys/types.h>
+
 #include "accelgyro.h"
 #include "hwtimer.h"
 #include "timer.h"
@@ -20,9 +22,9 @@
 
 #ifdef CONFIG_ACCEL_FIFO
 /* reserve maximum 4 samples of 16 bytes */
-#define ICM_FIFO_BUFFER	64
+#define ICM_FIFO_BUFFER 64
 #else
-#define ICM_FIFO_BUFFER	0
+#define ICM_FIFO_BUFFER 0
 #endif
 
 struct icm_drv_data_t {
@@ -35,21 +37,19 @@ struct icm_drv_data_t {
 	uint8_t fifo_buffer[ICM_FIFO_BUFFER] __aligned(sizeof(long));
 };
 
-#define ICM_GET_DATA(_s) \
-	((struct icm_drv_data_t *)(_s)->drv_data)
-#define ICM_GET_SAVED_DATA(_s) \
-	(&ICM_GET_DATA(_s)->saved_data[(_s)->type])
+#define ICM_GET_DATA(_s) ((struct icm_drv_data_t *)(_s)->drv_data)
+#define ICM_GET_SAVED_DATA(_s) (&ICM_GET_DATA(_s)->saved_data[(_s)->type])
 
 /*
  * Virtual register address is 16 bits:
  * - 8 bits MSB coding bank number
  * - 8 bits LSB coding physical address
  */
-#define ICM426XX_REG_GET_BANK(_r)	(((_r) & 0xFF00) >> 8)
-#define ICM426XX_REG_GET_ADDR(_r)	((_r) & 0x00FF)
+#define ICM426XX_REG_GET_BANK(_r) (((_r)&0xFF00) >> 8)
+#define ICM426XX_REG_GET_ADDR(_r) ((_r)&0x00FF)
 
 /* Sensor resolution in number of bits */
-#define ICM_RESOLUTION		16
+#define ICM_RESOLUTION 16
 
 /**
  * sign_extend - sign extend a standard int value using the given sign-bit
@@ -105,7 +105,7 @@ int icm_get_scale(const struct motion_sensor_t *s, uint16_t *scale,
 		  int16_t *temp);
 
 ssize_t icm_fifo_decode_packet(const void *packet, const uint8_t **accel,
-		const uint8_t **gyro);
+			       const uint8_t **gyro);
 
 static inline void icm_set_stabilize_ts(const struct motion_sensor_t *s,
 					uint32_t delay)
@@ -125,9 +125,8 @@ static inline void icm_reset_stabilize_ts(const struct motion_sensor_t *s)
 	st->stabilize_ts[s->type] = 0;
 }
 
-static inline
-int32_t icm_get_sensor_stabilized(const struct motion_sensor_t *s,
-				  uint32_t ts)
+static inline int32_t icm_get_sensor_stabilized(const struct motion_sensor_t *s,
+						uint32_t ts)
 {
 	struct icm_drv_data_t *st = ICM_GET_DATA(s);
 	uint32_t stabilize_ts = st->stabilize_ts[s->type];
@@ -138,4 +137,4 @@ int32_t icm_get_sensor_stabilized(const struct motion_sensor_t *s,
 	return time_until(ts, stabilize_ts);
 }
 
-#endif	/* __CROS_EC_ACCELGYRO_ICM_COMMON_H */
+#endif /* __CROS_EC_ACCELGYRO_ICM_COMMON_H */
diff --git a/driver/accelgyro_lsm6ds0.c b/driver/accelgyro_lsm6ds0.c
index beee41b815..265d89e18c 100644
--- a/driver/accelgyro_lsm6ds0.c
+++ b/driver/accelgyro_lsm6ds0.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,8 +19,8 @@
 #include "util.h"
 
 #define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
 
 /*
  * Struct for pairing an engineering value with the register value for a
@@ -32,25 +32,21 @@ struct accel_param_pair {
 };
 
 /* List of range values in +/-G's and their associated register values. */
-static const struct accel_param_pair g_ranges[] = {
-	{2, LSM6DS0_GSEL_2G},
-	{4, LSM6DS0_GSEL_4G},
-	{8, LSM6DS0_GSEL_8G}
-};
+static const struct accel_param_pair g_ranges[] = { { 2, LSM6DS0_GSEL_2G },
+						    { 4, LSM6DS0_GSEL_4G },
+						    { 8, LSM6DS0_GSEL_8G } };
 
 /*
  * List of angular rate range values in +/-dps's
  * and their associated register values.
  */
-const struct accel_param_pair dps_ranges[] = {
-	{245, LSM6DS0_DPS_SEL_245},
-	{500, LSM6DS0_DPS_SEL_500},
-	{1000, LSM6DS0_DPS_SEL_1000},
-	{2000, LSM6DS0_DPS_SEL_2000}
-};
+const struct accel_param_pair dps_ranges[] = { { 245, LSM6DS0_DPS_SEL_245 },
+					       { 500, LSM6DS0_DPS_SEL_500 },
+					       { 1000, LSM6DS0_DPS_SEL_1000 },
+					       { 2000, LSM6DS0_DPS_SEL_2000 } };
 
-static inline const struct accel_param_pair *get_range_table(
-		enum motionsensor_type type, int *psize)
+static inline const struct accel_param_pair *
+get_range_table(enum motionsensor_type type, int *psize)
 {
 	if (MOTIONSENSE_TYPE_ACCEL == type) {
 		if (psize)
@@ -65,28 +61,22 @@ static inline const struct accel_param_pair *get_range_table(
 
 /* List of ODR (gyro off) values in mHz and their associated register values.*/
 const struct accel_param_pair gyro_on_odr[] = {
-	{0,        LSM6DS0_ODR_PD},
-	{15000,    LSM6DS0_ODR_15HZ},
-	{59000,    LSM6DS0_ODR_59HZ},
-	{119000,   LSM6DS0_ODR_119HZ},
-	{238000,   LSM6DS0_ODR_238HZ},
-	{476000,   LSM6DS0_ODR_476HZ},
-	{952000,   LSM6DS0_ODR_952HZ}
+	{ 0, LSM6DS0_ODR_PD },	       { 15000, LSM6DS0_ODR_15HZ },
+	{ 59000, LSM6DS0_ODR_59HZ },   { 119000, LSM6DS0_ODR_119HZ },
+	{ 238000, LSM6DS0_ODR_238HZ }, { 476000, LSM6DS0_ODR_476HZ },
+	{ 952000, LSM6DS0_ODR_952HZ }
 };
 
 /* List of ODR (gyro on) values in mHz and their associated register values. */
 const struct accel_param_pair gyro_off_odr[] = {
-	{0,        LSM6DS0_ODR_PD},
-	{10000,    LSM6DS0_ODR_10HZ},
-	{50000,    LSM6DS0_ODR_50HZ},
-	{119000,   LSM6DS0_ODR_119HZ},
-	{238000,   LSM6DS0_ODR_238HZ},
-	{476000,   LSM6DS0_ODR_476HZ},
-	{952000,   LSM6DS0_ODR_952HZ}
+	{ 0, LSM6DS0_ODR_PD },	       { 10000, LSM6DS0_ODR_10HZ },
+	{ 50000, LSM6DS0_ODR_50HZ },   { 119000, LSM6DS0_ODR_119HZ },
+	{ 238000, LSM6DS0_ODR_238HZ }, { 476000, LSM6DS0_ODR_476HZ },
+	{ 952000, LSM6DS0_ODR_952HZ }
 };
 
-static inline const struct accel_param_pair *get_odr_table(
-		enum motionsensor_type type, int *psize)
+static inline const struct accel_param_pair *
+get_odr_table(enum motionsensor_type type, int *psize)
 {
 	if (MOTIONSENSE_TYPE_ACCEL == type) {
 		if (psize)
@@ -101,14 +91,14 @@ static inline const struct accel_param_pair *get_odr_table(
 
 static inline int get_ctrl_reg(enum motionsensor_type type)
 {
-	return (MOTIONSENSE_TYPE_ACCEL == type) ?
-		LSM6DS0_CTRL_REG6_XL : LSM6DS0_CTRL_REG1_G;
+	return (MOTIONSENSE_TYPE_ACCEL == type) ? LSM6DS0_CTRL_REG6_XL :
+						  LSM6DS0_CTRL_REG1_G;
 }
 
 static inline int get_xyz_reg(enum motionsensor_type type)
 {
-	return (MOTIONSENSE_TYPE_ACCEL == type) ?
-		LSM6DS0_OUT_X_L_XL : LSM6DS0_OUT_X_L_G;
+	return (MOTIONSENSE_TYPE_ACCEL == type) ? LSM6DS0_OUT_X_L_XL :
+						  LSM6DS0_OUT_X_L_G;
 }
 
 /**
@@ -118,14 +108,14 @@ static inline int get_xyz_reg(enum motionsensor_type type)
  * outside the range of values, it returns the closest valid reg value.
  */
 static int get_reg_val(const int eng_val, const int round_up,
-		const struct accel_param_pair *pairs, const int size)
+		       const struct accel_param_pair *pairs, const int size)
 {
 	int i;
 	for (i = 0; i < size - 1; i++) {
 		if (eng_val <= pairs[i].val)
 			break;
 
-		if (eng_val < pairs[i+1].val) {
+		if (eng_val < pairs[i + 1].val) {
 			if (round_up)
 				i += 1;
 			break;
@@ -138,7 +128,8 @@ static int get_reg_val(const int eng_val, const int round_up,
  * @return engineering value that matches the given reg val
  */
 static int get_engineering_val(const int reg_val,
-		const struct accel_param_pair *pairs, const int size)
+			       const struct accel_param_pair *pairs,
+			       const int size)
 {
 	int i;
 	for (i = 0; i < size; i++) {
@@ -166,9 +157,7 @@ static inline int raw_write8(const int port, const uint16_t i2c_addr_flags,
 	return i2c_write8(port, i2c_addr_flags, reg, data);
 }
 
-static int set_range(struct motion_sensor_t *s,
-				int range,
-				int rnd)
+static int set_range(struct motion_sensor_t *s, int range, int rnd)
 {
 	int ret, ctrl_val, range_tbl_size;
 	uint8_t ctrl_reg, reg_val;
@@ -185,19 +174,17 @@ static int set_range(struct motion_sensor_t *s,
 	 */
 	mutex_lock(s->mutex);
 
-	ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-			ctrl_reg, &ctrl_val);
+	ret = raw_read8(s->port, s->i2c_spi_addr_flags, ctrl_reg, &ctrl_val);
 	if (ret != EC_SUCCESS)
 		goto accel_cleanup;
 
 	ctrl_val = (ctrl_val & ~LSM6DS0_RANGE_MASK) | reg_val;
-	ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-			 ctrl_reg, ctrl_val);
+	ret = raw_write8(s->port, s->i2c_spi_addr_flags, ctrl_reg, ctrl_val);
 
 	/* Now that we have set the range, update the driver's value. */
 	if (ret == EC_SUCCESS)
-		s->current_range = get_engineering_val(reg_val, ranges,
-						       range_tbl_size);
+		s->current_range =
+			get_engineering_val(reg_val, ranges, range_tbl_size);
 
 accel_cleanup:
 	mutex_unlock(s->mutex);
@@ -209,9 +196,7 @@ static int get_resolution(const struct motion_sensor_t *s)
 	return LSM6DS0_RESOLUTION;
 }
 
-static int set_data_rate(const struct motion_sensor_t *s,
-				int rate,
-				int rnd)
+static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
 {
 	int ret, val, odr_tbl_size;
 	uint8_t ctrl_reg, reg_val;
@@ -237,8 +222,8 @@ static int set_data_rate(const struct motion_sensor_t *s,
 
 	/* Now that we have set the odr, update the driver's value. */
 	if (ret == EC_SUCCESS)
-		data->base.odr = get_engineering_val(reg_val, data_rates,
-						       odr_tbl_size);
+		data->base.odr =
+			get_engineering_val(reg_val, data_rates, odr_tbl_size);
 
 	/* CTRL_REG3_G 12h
 	 * [7] low-power mode = 0;
@@ -254,8 +239,8 @@ static int set_data_rate(const struct motion_sensor_t *s,
 			goto accel_cleanup;
 		val &= ~(0x3 << 4); /* clear bit [5:4] */
 		val = (rate > 119000) ?
-			(val | (1<<7))   /* set high-power mode */ :
-			(val & ~(1<<7)); /* set low-power mode */
+			      (val | (1 << 7)) /* set high-power mode */ :
+			      (val & ~(1 << 7)); /* set low-power mode */
 		ret = raw_write8(s->port, s->i2c_spi_addr_flags,
 				 LSM6DS0_CTRL_REG3_G, val);
 	}
@@ -272,9 +257,8 @@ static int get_data_rate(const struct motion_sensor_t *s)
 	return data->base.odr;
 }
 
-static int set_offset(const struct motion_sensor_t *s,
-			const int16_t *offset,
-			int16_t    temp)
+static int set_offset(const struct motion_sensor_t *s, const int16_t *offset,
+		      int16_t temp)
 {
 	/* temperature is ignored */
 	struct lsm6ds0_data *data = s->drv_data;
@@ -284,9 +268,8 @@ static int set_offset(const struct motion_sensor_t *s,
 	return EC_SUCCESS;
 }
 
-static int get_offset(const struct motion_sensor_t *s,
-			int16_t    *offset,
-			int16_t    *temp)
+static int get_offset(const struct motion_sensor_t *s, int16_t *offset,
+		      int16_t *temp)
 {
 	struct lsm6ds0_data *data = s->drv_data;
 	offset[X] = data->offset[X];
@@ -300,8 +283,8 @@ static int is_data_ready(const struct motion_sensor_t *s, int *ready)
 {
 	int ret, tmp;
 
-	ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-			LSM6DS0_STATUS_REG, &tmp);
+	ret = raw_read8(s->port, s->i2c_spi_addr_flags, LSM6DS0_STATUS_REG,
+			&tmp);
 
 	if (ret != EC_SUCCESS) {
 		CPRINTS("%s type:0x%X RS Error", s->name, s->type);
@@ -341,12 +324,10 @@ static int read(const struct motion_sensor_t *s, intv3_t v)
 	xyz_reg = get_xyz_reg(s->type);
 
 	/* Read 6 bytes starting at xyz_reg */
-	ret = i2c_read_block(s->port, s->i2c_spi_addr_flags,
-			     xyz_reg, raw, 6);
+	ret = i2c_read_block(s->port, s->i2c_spi_addr_flags, xyz_reg, raw, 6);
 
 	if (ret != EC_SUCCESS) {
-		CPRINTS("%s type:0x%X RD XYZ Error",
-			s->name, s->type);
+		CPRINTS("%s type:0x%X RD XYZ Error", s->name, s->type);
 		return ret;
 	}
 
@@ -366,8 +347,8 @@ static int init(struct motion_sensor_t *s)
 {
 	int ret = 0, tmp;
 
-	ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-			LSM6DS0_WHO_AM_I_REG, &tmp);
+	ret = raw_read8(s->port, s->i2c_spi_addr_flags, LSM6DS0_WHO_AM_I_REG,
+			&tmp);
 	if (ret)
 		return EC_ERROR_UNKNOWN;
 
@@ -387,7 +368,6 @@ static int init(struct motion_sensor_t *s)
 	 * SW_RESET is down for accel only!
 	 */
 	if (MOTIONSENSE_TYPE_ACCEL == s->type) {
-
 		mutex_lock(s->mutex);
 		ret = raw_read8(s->port, s->i2c_spi_addr_flags,
 				LSM6DS0_CTRL_REG8, &tmp);
diff --git a/driver/accelgyro_lsm6ds0.h b/driver/accelgyro_lsm6ds0.h
index c6b0789c08..149a32ea7a 100644
--- a/driver/accelgyro_lsm6ds0.h
+++ b/driver/accelgyro_lsm6ds0.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,95 +15,95 @@
  * 7-bit address is 110101Xb. Where 'X' is determined
  * by the voltage on the ADDR pin.
  */
-#define LSM6DS0_ADDR0_FLAGS       0x6a
-#define LSM6DS0_ADDR1_FLAGS       0x6b
+#define LSM6DS0_ADDR0_FLAGS 0x6a
+#define LSM6DS0_ADDR1_FLAGS 0x6b
 
 /* who am I  */
-#define LSM6DS0_WHO_AM_I          0x68
+#define LSM6DS0_WHO_AM_I 0x68
 
 /* Chip specific registers. */
-#define LSM6DS0_ACT_THS           0x04
-#define LSM6DS0_ACT_DUR           0x05
-#define LSM6DS0_INT_GEN_CFG_XL    0x06
-#define LSM6DS0_INT_GEN_THS_X_XL  0x07
-#define LSM6DS0_INT_GEN_THS_Y_XL  0x08
-#define LSM6DS0_INT_GEN_THS_Z_XL  0x09
-#define LSM6DS0_INT_GEN_DUR_XL    0x0a
-#define LSM6DS0_REFERENCE_G       0x0b
-#define LSM6DS0_INT_CTRL          0x0c
-#define LSM6DS0_WHO_AM_I_REG      0x0f
-#define LSM6DS0_CTRL_REG1_G       0x10
-#define LSM6DS0_CTRL_REG2_G       0x11
-#define LSM6DS0_CTRL_REG3_G       0x12
-#define LSM6DS0_ORIENT_CFG_G      0x13
-#define LSM6DS0_INT_GEN_SRC_G     0x14
-#define LSM6DS0_OUT_TEMP_L        0x15
-#define LSM6DS0_OUT_TEMP_H        0x16
-#define LSM6DS0_OUT_X_L_G         0x18
-#define LSM6DS0_OUT_X_H_G         0x19
-#define LSM6DS0_OUT_Y_L_G         0x1a
-#define LSM6DS0_OUT_Y_H_G         0x1b
-#define LSM6DS0_OUT_Z_L_G         0x1c
-#define LSM6DS0_OUT_Z_H_G         0x1d
-#define LSM6DS0_CTRL_REG4         0x1e
-#define LSM6DS0_CTRL_REG5_XL      0x1f
-#define LSM6DS0_CTRL_REG6_XL      0x20
-#define LSM6DS0_CTRL_REG7_XL      0x21
-#define LSM6DS0_CTRL_REG8         0x22
-#define LSM6DS0_CTRL_REG9         0x23
-#define LSM6DS0_CTRL_REG10        0x24
-#define LSM6DS0_INT_GEN_SRC_XL    0x26
-#define LSM6DS0_STATUS_REG        0x27
-#define LSM6DS0_OUT_X_L_XL        0x28
-#define LSM6DS0_OUT_X_H_XL        0x29
-#define LSM6DS0_OUT_Y_L_XL        0x2a
-#define LSM6DS0_OUT_Y_H_XL        0x2b
-#define LSM6DS0_OUT_Z_L_XL        0x2c
-#define LSM6DS0_OUT_Z_H_XL        0x2d
-#define LSM6DS0_FIFO_CTRL         0x2e
-#define LSM6DS0_FIFO_SRC          0x2f
-#define LSM6DS0_INT_GEN_CFG_G     0x30
-#define LSM6DS0_INT_GEN_THS_XH_G  0x31
-#define LSM6DS0_INT_GEN_THS_XL_G  0x32
-#define LSM6DS0_INT_GEN_THS_YH_G  0x33
-#define LSM6DS0_INT_GEN_THS_YL_G  0x34
-#define LSM6DS0_INT_GEN_THS_ZH_G  0x35
-#define LSM6DS0_INT_GEN_THS_ZL_G  0x36
-#define LSM6DS0_INT_GEN_DUR_G     0x37
-
-#define LSM6DS0_DPS_SEL_245     (0 << 3)
-#define LSM6DS0_DPS_SEL_500     BIT(3)
-#define LSM6DS0_DPS_SEL_1000    (2 << 3)
-#define LSM6DS0_DPS_SEL_2000    (3 << 3)
-#define LSM6DS0_GSEL_2G         (0 << 3)
-#define LSM6DS0_GSEL_4G         (2 << 3)
-#define LSM6DS0_GSEL_8G         (3 << 3)
-
-#define LSM6DS0_RANGE_MASK      (3 << 3)
-
-#define LSM6DS0_ODR_PD          (0 << 5)
-#define LSM6DS0_ODR_10HZ        BIT(5)
-#define LSM6DS0_ODR_15HZ        BIT(5)
-#define LSM6DS0_ODR_50HZ        (2 << 5)
-#define LSM6DS0_ODR_59HZ        (2 << 5)
-#define LSM6DS0_ODR_119HZ       (3 << 5)
-#define LSM6DS0_ODR_238HZ       (4 << 5)
-#define LSM6DS0_ODR_476HZ       (5 << 5)
-#define LSM6DS0_ODR_952HZ       (6 << 5)
-
-#define LSM6DS0_ODR_MASK        (7 << 5)
+#define LSM6DS0_ACT_THS 0x04
+#define LSM6DS0_ACT_DUR 0x05
+#define LSM6DS0_INT_GEN_CFG_XL 0x06
+#define LSM6DS0_INT_GEN_THS_X_XL 0x07
+#define LSM6DS0_INT_GEN_THS_Y_XL 0x08
+#define LSM6DS0_INT_GEN_THS_Z_XL 0x09
+#define LSM6DS0_INT_GEN_DUR_XL 0x0a
+#define LSM6DS0_REFERENCE_G 0x0b
+#define LSM6DS0_INT_CTRL 0x0c
+#define LSM6DS0_WHO_AM_I_REG 0x0f
+#define LSM6DS0_CTRL_REG1_G 0x10
+#define LSM6DS0_CTRL_REG2_G 0x11
+#define LSM6DS0_CTRL_REG3_G 0x12
+#define LSM6DS0_ORIENT_CFG_G 0x13
+#define LSM6DS0_INT_GEN_SRC_G 0x14
+#define LSM6DS0_OUT_TEMP_L 0x15
+#define LSM6DS0_OUT_TEMP_H 0x16
+#define LSM6DS0_OUT_X_L_G 0x18
+#define LSM6DS0_OUT_X_H_G 0x19
+#define LSM6DS0_OUT_Y_L_G 0x1a
+#define LSM6DS0_OUT_Y_H_G 0x1b
+#define LSM6DS0_OUT_Z_L_G 0x1c
+#define LSM6DS0_OUT_Z_H_G 0x1d
+#define LSM6DS0_CTRL_REG4 0x1e
+#define LSM6DS0_CTRL_REG5_XL 0x1f
+#define LSM6DS0_CTRL_REG6_XL 0x20
+#define LSM6DS0_CTRL_REG7_XL 0x21
+#define LSM6DS0_CTRL_REG8 0x22
+#define LSM6DS0_CTRL_REG9 0x23
+#define LSM6DS0_CTRL_REG10 0x24
+#define LSM6DS0_INT_GEN_SRC_XL 0x26
+#define LSM6DS0_STATUS_REG 0x27
+#define LSM6DS0_OUT_X_L_XL 0x28
+#define LSM6DS0_OUT_X_H_XL 0x29
+#define LSM6DS0_OUT_Y_L_XL 0x2a
+#define LSM6DS0_OUT_Y_H_XL 0x2b
+#define LSM6DS0_OUT_Z_L_XL 0x2c
+#define LSM6DS0_OUT_Z_H_XL 0x2d
+#define LSM6DS0_FIFO_CTRL 0x2e
+#define LSM6DS0_FIFO_SRC 0x2f
+#define LSM6DS0_INT_GEN_CFG_G 0x30
+#define LSM6DS0_INT_GEN_THS_XH_G 0x31
+#define LSM6DS0_INT_GEN_THS_XL_G 0x32
+#define LSM6DS0_INT_GEN_THS_YH_G 0x33
+#define LSM6DS0_INT_GEN_THS_YL_G 0x34
+#define LSM6DS0_INT_GEN_THS_ZH_G 0x35
+#define LSM6DS0_INT_GEN_THS_ZL_G 0x36
+#define LSM6DS0_INT_GEN_DUR_G 0x37
+
+#define LSM6DS0_DPS_SEL_245 (0 << 3)
+#define LSM6DS0_DPS_SEL_500 BIT(3)
+#define LSM6DS0_DPS_SEL_1000 (2 << 3)
+#define LSM6DS0_DPS_SEL_2000 (3 << 3)
+#define LSM6DS0_GSEL_2G (0 << 3)
+#define LSM6DS0_GSEL_4G (2 << 3)
+#define LSM6DS0_GSEL_8G (3 << 3)
+
+#define LSM6DS0_RANGE_MASK (3 << 3)
+
+#define LSM6DS0_ODR_PD (0 << 5)
+#define LSM6DS0_ODR_10HZ BIT(5)
+#define LSM6DS0_ODR_15HZ BIT(5)
+#define LSM6DS0_ODR_50HZ (2 << 5)
+#define LSM6DS0_ODR_59HZ (2 << 5)
+#define LSM6DS0_ODR_119HZ (3 << 5)
+#define LSM6DS0_ODR_238HZ (4 << 5)
+#define LSM6DS0_ODR_476HZ (5 << 5)
+#define LSM6DS0_ODR_952HZ (6 << 5)
+
+#define LSM6DS0_ODR_MASK (7 << 5)
 
 /*
  * Register      : STATUS_REG
  * Address       : 0X27
  */
 enum lsm6ds0_status {
-	LSM6DS0_STS_DOWN                = 0x00,
-	LSM6DS0_STS_XLDA_UP             = 0x01,
-	LSM6DS0_STS_GDA_UP              = 0x02,
+	LSM6DS0_STS_DOWN = 0x00,
+	LSM6DS0_STS_XLDA_UP = 0x01,
+	LSM6DS0_STS_GDA_UP = 0x02,
 };
-#define         LSM6DS0_STS_XLDA_MASK       0x01
-#define         LSM6DS0_STS_GDA_MASK        0x02
+#define LSM6DS0_STS_XLDA_MASK 0x01
+#define LSM6DS0_STS_GDA_MASK 0x02
 
 /*
  * Register      : CTRL_REG8
@@ -111,18 +111,18 @@ enum lsm6ds0_status {
  * Bit Group Name: BDU
  */
 enum lsm6ds0_bdu {
-	LSM6DS0_BDU_DISABLE              = 0x00,
-	LSM6DS0_BDU_ENABLE               = 0x40,
+	LSM6DS0_BDU_DISABLE = 0x00,
+	LSM6DS0_BDU_ENABLE = 0x40,
 };
 /* Sensor resolution in number of bits. This sensor has fixed resolution. */
-#define LSM6DS0_RESOLUTION      16
+#define LSM6DS0_RESOLUTION 16
 
 /* Min and Max sampling frequency in mHz */
-#define LSM6DS0_ACCEL_MIN_FREQ  14900
-#define LSM6DS0_ACCEL_MAX_FREQ  MOTION_MAX_SENSOR_FREQUENCY(952000, 119000)
+#define LSM6DS0_ACCEL_MIN_FREQ 14900
+#define LSM6DS0_ACCEL_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(952000, 119000)
 
-#define LSM6DS0_GYRO_MIN_FREQ   14900
-#define LSM6DS0_GYRO_MAX_FREQ  MOTION_MAX_SENSOR_FREQUENCY(952000, 119000)
+#define LSM6DS0_GYRO_MIN_FREQ 14900
+#define LSM6DS0_GYRO_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(952000, 119000)
 
 extern const struct accelgyro_drv lsm6ds0_drv;
 struct lsm6ds0_data {
diff --git a/driver/accelgyro_lsm6dsm.c b/driver/accelgyro_lsm6dsm.c
index 78dafc0e52..2bf0215315 100644
--- a/driver/accelgyro_lsm6dsm.c
+++ b/driver/accelgyro_lsm6dsm.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,6 +9,7 @@
  * This driver supports both devices LSM6DSM and LSM6DSL
  */
 
+#include "builtin/assert.h"
 #include "driver/accelgyro_lsm6dsm.h"
 #include "driver/mag_lis2mdl.h"
 #include "hooks.h"
@@ -25,11 +26,11 @@
 #endif
 
 #define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args)
 
 STATIC_IF(ACCEL_LSM6DSM_INT_ENABLE)
-	volatile uint32_t last_interrupt_timestamp;
+volatile uint32_t last_interrupt_timestamp;
 
 /**
  * Gets the sensor type associated with the dev_fifo enum. This type can be used
@@ -55,7 +56,7 @@ static inline uint8_t get_sensor_type(enum dev_fifo fifo_type)
 static inline int get_xyz_reg(enum motionsensor_type type)
 {
 	return LSM6DSM_ACCEL_OUT_X_L_ADDR -
-		(LSM6DSM_ACCEL_OUT_X_L_ADDR - LSM6DSM_GYRO_OUT_X_L_ADDR) * type;
+	       (LSM6DSM_ACCEL_OUT_X_L_ADDR - LSM6DSM_GYRO_OUT_X_L_ADDR) * type;
 }
 
 /**
@@ -77,13 +78,12 @@ __maybe_unused static int config_interrupt(const struct motion_sensor_t *accel)
 				   LSM6DSM_FIFO_CTRL1_ADDR,
 				   OUT_XYZ_SIZE / sizeof(uint16_t)));
 	int1_ctrl_val |= LSM6DSM_INT_FIFO_TH | LSM6DSM_INT_FIFO_OVR |
-		LSM6DSM_INT_FIFO_FULL;
+			 LSM6DSM_INT_FIFO_FULL;
 
 	return st_raw_write8(accel->port, accel->i2c_spi_addr_flags,
-			LSM6DSM_INT1_CTRL, int1_ctrl_val);
+			     LSM6DSM_INT1_CTRL, int1_ctrl_val);
 }
 
-
 /**
  * fifo_disable - set fifo mode
  * @accel: Motion sensor pointer: must be MOTIONSENSE_TYPE_ACCEL.
@@ -132,7 +132,6 @@ static int fifo_enable(const struct motion_sensor_t *accel)
 		MOTIONSENSE_TYPE_MAG,
 	};
 
-
 	/* Search for min and max odr values for acc, gyro. */
 	for (i = FIFO_DEV_GYRO; i < FIFO_DEV_NUM; i++) {
 		/* Check if sensor enabled with ODR. */
@@ -151,8 +150,7 @@ static int fifo_enable(const struct motion_sensor_t *accel)
 	}
 
 	/* FIFO ODR must be set before the decimation factors */
-	odr_reg_val = LSM6DSM_ODR_TO_REG(max_odr) <<
-					LSM6DSM_FIFO_CTRL5_ODR_OFF;
+	odr_reg_val = LSM6DSM_ODR_TO_REG(max_odr) << LSM6DSM_FIFO_CTRL5_ODR_OFF;
 	err = st_raw_write8(accel->port, accel->i2c_spi_addr_flags,
 			    LSM6DSM_FIFO_CTRL5_ADDR, odr_reg_val);
 
@@ -174,12 +172,13 @@ static int fifo_enable(const struct motion_sensor_t *accel)
 	st_raw_write8(accel->port, accel->i2c_spi_addr_flags,
 		      LSM6DSM_FIFO_CTRL3_ADDR,
 		      (decimators[FIFO_DEV_GYRO] << LSM6DSM_FIFO_DEC_G_OFF) |
-		      (decimators[FIFO_DEV_ACCEL] << LSM6DSM_FIFO_DEC_XL_OFF));
+			      (decimators[FIFO_DEV_ACCEL]
+			       << LSM6DSM_FIFO_DEC_XL_OFF));
 	if (IS_ENABLED(CONFIG_LSM6DSM_SEC_I2C)) {
 		ASSERT(ARRAY_SIZE(decimators) > FIFO_DEV_MAG);
 		st_raw_write8(accel->port, accel->i2c_spi_addr_flags,
-				LSM6DSM_FIFO_CTRL4_ADDR,
-				decimators[FIFO_DEV_MAG]);
+			      LSM6DSM_FIFO_CTRL4_ADDR,
+			      decimators[FIFO_DEV_MAG]);
 
 		/*
 		 * FIFO ODR is limited by odr of gyro or accel.
@@ -204,12 +203,12 @@ static int fifo_enable(const struct motion_sensor_t *accel)
 		 */
 		if (max_odr > MAX(odrs[FIFO_DEV_ACCEL], odrs[FIFO_DEV_GYRO])) {
 			st_write_data_with_mask(accel,
-				LSM6DSM_ODR_REG(accel->type),
-				LSM6DSM_ODR_MASK,
-				LSM6DSM_ODR_TO_REG(max_odr));
+						LSM6DSM_ODR_REG(accel->type),
+						LSM6DSM_ODR_MASK,
+						LSM6DSM_ODR_TO_REG(max_odr));
 		} else {
-			st_write_data_with_mask(accel,
-				LSM6DSM_ODR_REG(accel->type),
+			st_write_data_with_mask(
+				accel, LSM6DSM_ODR_REG(accel->type),
 				LSM6DSM_ODR_MASK,
 				LSM6DSM_ODR_TO_REG(odrs[FIFO_DEV_ACCEL]));
 		}
@@ -275,8 +274,7 @@ static int fifo_next(struct lsm6dsm_data *private)
  * push_fifo_data - Scan data pattern and push upside
  */
 static void push_fifo_data(struct motion_sensor_t *accel, uint8_t *fifo,
-			   uint16_t flen,
-			   uint32_t timestamp)
+			   uint16_t flen, uint32_t timestamp)
 {
 	struct motion_sensor_t *s;
 	struct lsm6dsm_data *private = LSM6DSM_GET_DATA(accel);
@@ -310,7 +308,6 @@ static void push_fifo_data(struct motion_sensor_t *accel, uint8_t *fifo,
 				st_normalize(s, axis, fifo);
 			}
 
-
 			if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
 				struct ec_response_motion_sensor_data vect;
 
@@ -356,8 +353,7 @@ static int load_fifo(struct motion_sensor_t *s, const struct fstatus *fsts)
 
 		/* Read data and copy in buffer. */
 		err = st_raw_read_n_noinc(s->port, s->i2c_spi_addr_flags,
-					  LSM6DSM_FIFO_DATA_ADDR,
-					  fifo, length);
+					  LSM6DSM_FIFO_DATA_ADDR, fifo, length);
 		if (err != EC_SUCCESS)
 			return err;
 
@@ -398,17 +394,13 @@ static int irq_handler(struct motion_sensor_t *s, uint32_t *event)
 	    (!(*event & CONFIG_ACCEL_LSM6DSM_INT_EVENT)))
 		return EC_ERROR_NOT_HANDLED;
 
-
 	while (!fifo_empty) {
 		/* Read how many data pattern on FIFO to read. */
-		RETURN_ERROR(st_raw_read_n_noinc(s->port,
-						 s->i2c_spi_addr_flags,
-						 LSM6DSM_FIFO_STS1_ADDR,
-						 (uint8_t *)&fsts,
-						 sizeof(fsts)));
+		RETURN_ERROR(st_raw_read_n_noinc(
+			s->port, s->i2c_spi_addr_flags, LSM6DSM_FIFO_STS1_ADDR,
+			(uint8_t *)&fsts, sizeof(fsts)));
 		if (fsts.len & (LSM6DSM_FIFO_DATA_OVR | LSM6DSM_FIFO_FULL))
-			CPRINTS("%s FIFO Overrun: %04x",
-					s->name, fsts.len);
+			CPRINTS("%s FIFO Overrun: %04x", s->name, fsts.len);
 		fifo_empty = fsts.len & LSM6DSM_FIFO_EMPTY;
 		if (!fifo_empty) {
 			commit_needed = true;
@@ -420,7 +412,7 @@ static int irq_handler(struct motion_sensor_t *s, uint32_t *event)
 
 	return EC_SUCCESS;
 }
-#endif  /* ACCEL_LSM6DSM_INT_ENABLE */
+#endif /* ACCEL_LSM6DSM_INT_ENABLE */
 
 /**
  * set_range - set full scale range
@@ -520,10 +512,10 @@ int lsm6dsm_set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
 		 * less often.
 		 */
 		if (normalized_rate > 0)
-			cal->batch_size = MAX(
-				MAG_CAL_MIN_BATCH_SIZE,
-				(normalized_rate * 1000) /
-					MAG_CAL_MIN_BATCH_WINDOW_US);
+			cal->batch_size =
+				MAX(MAG_CAL_MIN_BATCH_SIZE,
+				    (normalized_rate * 1000) /
+					    MAG_CAL_MIN_BATCH_WINDOW_US);
 		else
 			cal->batch_size = 0;
 		CPRINTS("Batch size: %d", cal->batch_size);
@@ -554,8 +546,8 @@ static int is_data_ready(const struct motion_sensor_t *s, int *ready)
 {
 	int ret, tmp;
 
-	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags,
-			   LSM6DSM_STATUS_REG, &tmp);
+	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, LSM6DSM_STATUS_REG,
+			   &tmp);
 	if (ret != EC_SUCCESS) {
 		CPRINTS("%s type:0x%X RS Error", s->name, s->type);
 		return ret;
@@ -610,8 +602,8 @@ static int init(struct motion_sensor_t *s)
 	struct stprivate_data *data = s->drv_data;
 	uint8_t ctrl_reg, reg_val = 0;
 
-	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags,
-			   LSM6DSM_WHO_AM_I_REG, &tmp);
+	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, LSM6DSM_WHO_AM_I_REG,
+			   &tmp);
 	if (ret != EC_SUCCESS)
 		return EC_ERROR_UNKNOWN;
 
@@ -648,8 +640,8 @@ static int init(struct motion_sensor_t *s)
 			goto err_unlock;
 
 		/* Power ON Accel. */
-		ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-				    ctrl_reg, reg_val);
+		ret = st_raw_write8(s->port, s->i2c_spi_addr_flags, ctrl_reg,
+				    reg_val);
 		if (ret != EC_SUCCESS)
 			goto err_unlock;
 
@@ -669,12 +661,12 @@ static int init(struct motion_sensor_t *s)
 
 			/* Power ON Accel. */
 			ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-					ctrl_reg, reg_val);
+					    ctrl_reg, reg_val);
 			if (ret != EC_SUCCESS)
 				goto err_unlock;
 
 			ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-					LSM6DSM_CTRL3_ADDR, LSM6DSM_BOOT);
+					    LSM6DSM_CTRL3_ADDR, LSM6DSM_BOOT);
 			if (ret != EC_SUCCESS)
 				goto err_unlock;
 
@@ -686,7 +678,7 @@ static int init(struct motion_sensor_t *s)
 
 			/* Power OFF Accel. */
 			ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-					ctrl_reg, 0);
+					    ctrl_reg, 0);
 			if (ret != EC_SUCCESS)
 				goto err_unlock;
 		}
@@ -695,11 +687,9 @@ static int init(struct motion_sensor_t *s)
 		 * Output data not updated until have been read.
 		 * Prefer interrupt to be active low.
 		 */
-		ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-				    LSM6DSM_CTRL3_ADDR,
-				    LSM6DSM_BDU
-				    | LSM6DSM_H_L_ACTIVE
-				    | LSM6DSM_IF_INC);
+		ret = st_raw_write8(
+			s->port, s->i2c_spi_addr_flags, LSM6DSM_CTRL3_ADDR,
+			LSM6DSM_BDU | LSM6DSM_H_L_ACTIVE | LSM6DSM_IF_INC);
 		if (ret != EC_SUCCESS)
 			goto err_unlock;
 
@@ -736,6 +726,17 @@ static int read_temp(const struct motion_sensor_t *s, int *temp)
 	return EC_SUCCESS;
 }
 
+#ifdef CONFIG_BODY_DETECTION
+static int get_rms_noise(const struct motion_sensor_t *s)
+{
+	/*
+	 * RMS | Acceleration RMS noise in normal/low-power mode
+	 * FS = ±4 g | 2.0 mg(RMS)
+	 */
+	return 2000;
+}
+#endif
+
 const struct accelgyro_drv lsm6dsm_drv = {
 	.init = init,
 	.read = read,
@@ -749,4 +750,10 @@ const struct accelgyro_drv lsm6dsm_drv = {
 #ifdef ACCEL_LSM6DSM_INT_ENABLE
 	.irq_handler = irq_handler,
 #endif /* ACCEL_LSM6DSM_INT_ENABLE */
+#ifdef CONFIG_BODY_DETECTION
+	.get_rms_noise = get_rms_noise,
+#endif
+#ifdef CONFIG_GESTURE_HOST_DETECTION
+	.list_activities = st_list_activities,
+#endif
 };
diff --git a/driver/accelgyro_lsm6dsm.h b/driver/accelgyro_lsm6dsm.h
index 907429257a..51da2a42fb 100644
--- a/driver/accelgyro_lsm6dsm.h
+++ b/driver/accelgyro_lsm6dsm.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,165 +17,163 @@
  * 7-bit address is 110101xb. Where 'x' is determined
  * by the voltage on the ADDR pin
  */
-#define LSM6DSM_ADDR0_FLAGS		0x6a
-#define LSM6DSM_ADDR1_FLAGS		0x6b
+#define LSM6DSM_ADDR0_FLAGS 0x6a
+#define LSM6DSM_ADDR1_FLAGS 0x6b
 
 /* COMMON DEFINE FOR ACCEL-GYRO SENSORS */
-#define LSM6DSM_EN_BIT			0x01
-#define LSM6DSM_DIS_BIT			0x00
+#define LSM6DSM_EN_BIT 0x01
+#define LSM6DSM_DIS_BIT 0x00
 
 /* Access to embedded sensor hub register bank */
-#define LSM6DSM_FUNC_CFG_ACC_ADDR	0x01
-#define LSM6DSM_FUNC_CFG_EN			0x80
-#define LSM6DSM_FUNC_CFG_EN_B			0x20
+#define LSM6DSM_FUNC_CFG_ACC_ADDR 0x01
+#define LSM6DSM_FUNC_CFG_EN 0x80
+#define LSM6DSM_FUNC_CFG_EN_B 0x20
 
 /* FIFO decimator registers and bitmask */
-#define LSM6DSM_FIFO_CTRL1_ADDR		0x06
+#define LSM6DSM_FIFO_CTRL1_ADDR 0x06
 
 /* Output data rate registers and masks */
-#define LSM6DSM_ODR_REG(_sensor) \
-	(LSM6DSM_CTRL1_ADDR + _sensor)
-#define LSM6DSM_ODR_MASK		0xf0
+#define LSM6DSM_ODR_REG(_sensor) (LSM6DSM_CTRL1_ADDR + _sensor)
+#define LSM6DSM_ODR_MASK 0xf0
 
-#define LSM6DSM_FIFO_CTRL2_ADDR		0x07
+#define LSM6DSM_FIFO_CTRL2_ADDR 0x07
 
-#define LSM6DSM_FIFO_CTRL3_ADDR		0x08
-#define LSM6DSM_FIFO_DEC_XL_OFF			0
-#define LSM6DSM_FIFO_DEC_G_OFF			3
+#define LSM6DSM_FIFO_CTRL3_ADDR 0x08
+#define LSM6DSM_FIFO_DEC_XL_OFF 0
+#define LSM6DSM_FIFO_DEC_G_OFF 3
 
-#define LSM6DSM_FIFO_CTRL4_ADDR		0x09
+#define LSM6DSM_FIFO_CTRL4_ADDR 0x09
 
 #define LSM6DSM_FIFO_DECIMATOR(_dec) \
 	(_dec < 8 ? _dec : (2 + __builtin_ctz(_dec)))
 
 /* Hardware FIFO size in byte */
-#define LSM6DSM_MAX_FIFO_SIZE		4096
-#define LSM6DSM_MAX_FIFO_LENGTH	(LSM6DSM_MAX_FIFO_SIZE / OUT_XYZ_SIZE)
+#define LSM6DSM_MAX_FIFO_SIZE 4096
+#define LSM6DSM_MAX_FIFO_LENGTH (LSM6DSM_MAX_FIFO_SIZE / OUT_XYZ_SIZE)
 
-#define LSM6DSM_FIFO_CTRL5_ADDR		0x0a
-#define LSM6DSM_FIFO_CTRL5_ODR_OFF		3
-#define LSM6DSM_FIFO_CTRL5_ODR_MASK \
-	(0xf << LSM6DSM_FIFO_CTRL5_ODR_OFF)
-#define LSM6DSM_FIFO_CTRL5_MODE_MASK		0x07
+#define LSM6DSM_FIFO_CTRL5_ADDR 0x0a
+#define LSM6DSM_FIFO_CTRL5_ODR_OFF 3
+#define LSM6DSM_FIFO_CTRL5_ODR_MASK (0xf << LSM6DSM_FIFO_CTRL5_ODR_OFF)
+#define LSM6DSM_FIFO_CTRL5_MODE_MASK 0x07
 
-#define LSM6DSM_INT1_CTRL		0x0d
-#define LSM6DSM_INT_FIFO_TH			0x08
-#define LSM6DSM_INT_FIFO_OVR			0x10
-#define LSM6DSM_INT_FIFO_FULL			0x20
-#define LSM6DSM_INT_SIGMO			0x40
+#define LSM6DSM_INT1_CTRL 0x0d
+#define LSM6DSM_INT_FIFO_TH 0x08
+#define LSM6DSM_INT_FIFO_OVR 0x10
+#define LSM6DSM_INT_FIFO_FULL 0x20
+#define LSM6DSM_INT_SIGMO 0x40
 
 /* Who Am I */
-#define LSM6DSM_WHO_AM_I_REG		0x0f
+#define LSM6DSM_WHO_AM_I_REG 0x0f
 /* LSM6DSM/LSM6DSL/LSM6DS3TR-C */
-#define LSM6DSM_WHO_AM_I			0x6a
+#define LSM6DSM_WHO_AM_I 0x6a
 /* LSM6DS3 */
-#define LSM6DS3_WHO_AM_I			0x69
+#define LSM6DS3_WHO_AM_I 0x69
 
-#define LSM6DSM_CTRL1_ADDR		0x10
-#define LSM6DSM_XL_ODR_MASK			0xf0
+#define LSM6DSM_CTRL1_ADDR 0x10
+#define LSM6DSM_XL_ODR_MASK 0xf0
 
-#define LSM6DSM_CTRL2_ADDR		0x11
-#define LSM6DSM_CTRL3_ADDR		0x12
-#define LSM6DSM_SW_RESET			0x01
-#define LSM6DSM_IF_INC				0x04
-#define LSM6DSM_PP_OD				0x10
-#define LSM6DSM_H_L_ACTIVE			0x20
-#define LSM6DSM_BDU				0x40
-#define LSM6DSM_BOOT				0x80
+#define LSM6DSM_CTRL2_ADDR 0x11
+#define LSM6DSM_CTRL3_ADDR 0x12
+#define LSM6DSM_SW_RESET 0x01
+#define LSM6DSM_IF_INC 0x04
+#define LSM6DSM_PP_OD 0x10
+#define LSM6DSM_H_L_ACTIVE 0x20
+#define LSM6DSM_BDU 0x40
+#define LSM6DSM_BOOT 0x80
 
-#define LSM6DSM_CTRL4_ADDR		0x13
-#define LSM6DSM_INT2_ON_INT1_MASK		0x20
+#define LSM6DSM_CTRL4_ADDR 0x13
+#define LSM6DSM_INT2_ON_INT1_MASK 0x20
 
-#define LSM6DSM_CTRL6_ADDR		0x15
-#define LSM6DSM_CTRL7_ADDR		0x16
+#define LSM6DSM_CTRL6_ADDR 0x15
+#define LSM6DSM_CTRL7_ADDR 0x16
 
-#define LSM6DSM_CTRL10_ADDR		0x19
-#define LSM6DSM_FUNC_EN_MASK			0x04
-#define LSM6DSM_SIG_MOT_MASK			0x01
-#define LSM6DSM_EMBED_FUNC_EN			0x04
-#define LSM6DSM_SIG_MOT_EN			0x01
+#define LSM6DSM_CTRL10_ADDR 0x19
+#define LSM6DSM_FUNC_EN_MASK 0x04
+#define LSM6DSM_SIG_MOT_MASK 0x01
+#define LSM6DSM_EMBED_FUNC_EN 0x04
+#define LSM6DSM_SIG_MOT_EN 0x01
 
 /* Controller mode configuration register */
-#define LSM6DSM_CONTROLLER_CFG_ADDR	0x1a
-#define LSM6DSM_PASSTROUGH_MASK			0x1f
-#define LSM6DSM_EXT_TRIGGER_EN			0x10
-#define LSM6DSM_PULLUP_EN			0x08
-#define LSM6DSM_I2C_PASS_THRU_MODE		0x04
-#define LSM6DSM_I2C_CONTROLLER_ON		0x01
+#define LSM6DSM_CONTROLLER_CFG_ADDR 0x1a
+#define LSM6DSM_PASSTROUGH_MASK 0x1f
+#define LSM6DSM_EXT_TRIGGER_EN 0x10
+#define LSM6DSM_PULLUP_EN 0x08
+#define LSM6DSM_I2C_PASS_THRU_MODE 0x04
+#define LSM6DSM_I2C_CONTROLLER_ON 0x01
 
-#define LSM6DSM_TAP_SRC_ADDR		0x1c
-#define LSM6DSM_STAP_DETECT			0x20
-#define LSM6DSM_DTAP_DETECT			0x10
+#define LSM6DSM_TAP_SRC_ADDR 0x1c
+#define LSM6DSM_STAP_DETECT 0x20
+#define LSM6DSM_DTAP_DETECT 0x10
 
-#define LSM6DSM_STATUS_REG		0x1e
+#define LSM6DSM_STATUS_REG 0x1e
 
-#define LSM6DSM_OUT_TEMP_L_ADDR		0x20
+#define LSM6DSM_OUT_TEMP_L_ADDR 0x20
 
-#define LSM6DSM_GYRO_OUT_X_L_ADDR	0x22
-#define LSM6DSM_ACCEL_OUT_X_L_ADDR	0x28
+#define LSM6DSM_GYRO_OUT_X_L_ADDR 0x22
+#define LSM6DSM_ACCEL_OUT_X_L_ADDR 0x28
 
-#define LSM6DSM_SENSORHUB1_REG		0x2e
+#define LSM6DSM_SENSORHUB1_REG 0x2e
 
-#define LSM6DSM_FIFO_STS1_ADDR		0x3a
-#define LSM6DSM_FIFO_STS2_ADDR		0x3b
-#define LSM6DSM_FIFO_DIFF_MASK			0x0fff
-#define LSM6DSM_FIFO_EMPTY			0x1000
-#define LSM6DSM_FIFO_FULL			0x2000
-#define LSM6DSM_FIFO_DATA_OVR			0x4000
-#define LSM6DSM_FIFO_WATERMARK			0x8000
-#define LSM6DSM_FIFO_NODECIM			0x01
+#define LSM6DSM_FIFO_STS1_ADDR 0x3a
+#define LSM6DSM_FIFO_STS2_ADDR 0x3b
+#define LSM6DSM_FIFO_DIFF_MASK 0x0fff
+#define LSM6DSM_FIFO_EMPTY 0x1000
+#define LSM6DSM_FIFO_FULL 0x2000
+#define LSM6DSM_FIFO_DATA_OVR 0x4000
+#define LSM6DSM_FIFO_WATERMARK 0x8000
+#define LSM6DSM_FIFO_NODECIM 0x01
 
 /* Out data register */
-#define LSM6DSM_FIFO_DATA_ADDR		0x3e
+#define LSM6DSM_FIFO_DATA_ADDR 0x3e
 
 /* Registers value for supported FIFO mode */
-#define LSM6DSM_FIFO_MODE_BYPASS_VAL		0x00
-#define LSM6DSM_FIFO_MODE_CONTINUOUS_VAL	0x06
+#define LSM6DSM_FIFO_MODE_BYPASS_VAL 0x00
+#define LSM6DSM_FIFO_MODE_CONTINUOUS_VAL 0x06
 
-#define LSM6DSM_FUNC_SRC1_ADDR		0x53
-#define LSM6DSM_SENSORHUB_END_OP		0x01
-#define LSM6DSM_SIGN_MOTION_IA			0x40
+#define LSM6DSM_FUNC_SRC1_ADDR 0x53
+#define LSM6DSM_SENSORHUB_END_OP 0x01
+#define LSM6DSM_SIGN_MOTION_IA 0x40
 
-#define LSM6DSM_LIR_ADDR		0x58
-#define LSM6DSM_LIR_MASK			0x01
-#define LSM6DSM_EN_INT				0x80
-#define LSM6DSM_EN_TAP				0x0e
-#define LSM6DSM_TAP_MASK			0x8e
+#define LSM6DSM_LIR_ADDR 0x58
+#define LSM6DSM_LIR_MASK 0x01
+#define LSM6DSM_EN_INT 0x80
+#define LSM6DSM_EN_TAP 0x0e
+#define LSM6DSM_TAP_MASK 0x8e
 
-#define LSM6DSM_TAP_THS_6D		0x59
-#define LSM6DSM_D4D_EN_MASK			0x80
-#define LSM6DSM_TAP_TH_MASK			0x1f
+#define LSM6DSM_TAP_THS_6D 0x59
+#define LSM6DSM_D4D_EN_MASK 0x80
+#define LSM6DSM_TAP_TH_MASK 0x1f
 
-#define LSM6DSM_INT_DUR2_ADDR		0x5a
-#define LSM6DSM_TAP_DUR_MASK			0xf0
-#define LSM6DSM_TAP_QUIET_MASK			0x0c
+#define LSM6DSM_INT_DUR2_ADDR 0x5a
+#define LSM6DSM_TAP_DUR_MASK 0xf0
+#define LSM6DSM_TAP_QUIET_MASK 0x0c
 
-#define LSM6DSM_WUP_THS_ADDR		0x5b
-#define LSM6DSM_S_D_TAP_MASK			0x80
-#define LSM6DSM_STAP_EN				0
-#define LSM6DSM_DTAP_EN				1
+#define LSM6DSM_WUP_THS_ADDR 0x5b
+#define LSM6DSM_S_D_TAP_MASK 0x80
+#define LSM6DSM_STAP_EN 0
+#define LSM6DSM_DTAP_EN 1
 
-#define LSM6DSM_MD1_CFG_ADDR		0x5e
-#define LSM6DSM_INT1_STAP			0x40
-#define LSM6DSM_INT1_DTAP			0x08
+#define LSM6DSM_MD1_CFG_ADDR 0x5e
+#define LSM6DSM_INT1_STAP 0x40
+#define LSM6DSM_INT1_DTAP 0x08
 
 /* Register values for Sensor Hub Slave 0 / Bank A */
-#define LSM6DSM_SLV0_ADD_ADDR		0x02
-#define LSM6DSM_SLV0_ADDR_SHFT			1
-#define LSM6DSM_SLV0_ADDR_MASK			0xfe
-#define LSM6DSM_SLV0_RD_BIT			0x01
+#define LSM6DSM_SLV0_ADD_ADDR 0x02
+#define LSM6DSM_SLV0_ADDR_SHFT 1
+#define LSM6DSM_SLV0_ADDR_MASK 0xfe
+#define LSM6DSM_SLV0_RD_BIT 0x01
 
-#define LSM6DSM_SLV0_SUBADD_ADDR	0x03
+#define LSM6DSM_SLV0_SUBADD_ADDR 0x03
 
-#define LSM6DSM_SLV0_CONFIG_ADDR	0x04
-#define LSM6DSM_SLV0_SLV_RATE_SHFT		6
-#define LSM6DSM_SLV0_SLV_RATE_MASK		0xc0
-#define LSM6DSM_SLV0_AUX_SENS_SHFT		4
-#define LSM6DSM_SLV0_AUX_SENS_MASK		0x30
-#define LSM6DSM_SLV0_NUM_OPS_MASK		0x07
+#define LSM6DSM_SLV0_CONFIG_ADDR 0x04
+#define LSM6DSM_SLV0_SLV_RATE_SHFT 6
+#define LSM6DSM_SLV0_SLV_RATE_MASK 0xc0
+#define LSM6DSM_SLV0_AUX_SENS_SHFT 4
+#define LSM6DSM_SLV0_AUX_SENS_MASK 0x30
+#define LSM6DSM_SLV0_NUM_OPS_MASK 0x07
 
-#define LSM6DSM_SLV1_CONFIG_ADDR	0x07
-#define LSM6DSM_SLV0_WR_ONCE_MASK		0x20
+#define LSM6DSM_SLV1_CONFIG_ADDR 0x07
+#define LSM6DSM_SLV0_WR_ONCE_MASK 0x20
 
 #define LSM6DSM_DATA_WRITE_SUB_SLV0_ADDR 0x0e
 
@@ -188,9 +186,9 @@ enum dev_fifo {
 };
 
 #ifdef CONFIG_LSM6DSM_SEC_I2C
-#define	FIFO_DEV_NUM (FIFO_DEV_MAG + 1)
+#define FIFO_DEV_NUM (FIFO_DEV_MAG + 1)
 #else
-#define	FIFO_DEV_NUM (FIFO_DEV_ACCEL + 1)
+#define FIFO_DEV_NUM (FIFO_DEV_ACCEL + 1)
 #endif
 
 struct fstatus {
@@ -199,7 +197,7 @@ struct fstatus {
 };
 
 /* Absolute maximum rate for acc and gyro sensors */
-#define LSM6DSM_ODR_MIN_VAL		13000
+#define LSM6DSM_ODR_MIN_VAL 13000
 #define LSM6DSM_ODR_MAX_VAL \
 	MOTION_MAX_SENSOR_FREQUENCY(416000, LSM6DSM_ODR_MIN_VAL)
 
@@ -210,31 +208,30 @@ struct fstatus {
 #define LSM6DSM_REG_TO_ODR(_reg) (LSM6DSM_ODR_MIN_VAL << (_reg - 1))
 
 /* Full Scale range value and gain for Acc */
-#define LSM6DSM_FS_LIST_NUM		4
+#define LSM6DSM_FS_LIST_NUM 4
 
-#define LSM6DSM_ACCEL_FS_ADDR		0x10
-#define LSM6DSM_ACCEL_FS_MASK		0x0c
+#define LSM6DSM_ACCEL_FS_ADDR 0x10
+#define LSM6DSM_ACCEL_FS_MASK 0x0c
 
-#define LSM6DSM_ACCEL_FS_2G_VAL		0x00
-#define LSM6DSM_ACCEL_FS_4G_VAL		0x02
-#define LSM6DSM_ACCEL_FS_8G_VAL		0x03
-#define LSM6DSM_ACCEL_FS_16G_VAL	0x01
+#define LSM6DSM_ACCEL_FS_2G_VAL 0x00
+#define LSM6DSM_ACCEL_FS_4G_VAL 0x02
+#define LSM6DSM_ACCEL_FS_8G_VAL 0x03
+#define LSM6DSM_ACCEL_FS_16G_VAL 0x01
 
-#define LSM6DSM_ACCEL_FS_MAX_VAL	16
+#define LSM6DSM_ACCEL_FS_MAX_VAL 16
 
 /* Accel Reg value from Full Scale */
-#define LSM6DSM_ACCEL_FS_REG(_fs) \
-	(_fs == 2 ? LSM6DSM_ACCEL_FS_2G_VAL : \
-	_fs == 16 ? LSM6DSM_ACCEL_FS_16G_VAL : \
-	__fls(_fs))
+#define LSM6DSM_ACCEL_FS_REG(_fs)               \
+	(_fs == 2  ? LSM6DSM_ACCEL_FS_2G_VAL :  \
+	 _fs == 16 ? LSM6DSM_ACCEL_FS_16G_VAL : \
+		     __fls(_fs))
 
 /* Accel normalized FS value from Full Scale */
 #define LSM6DSM_ACCEL_NORMALIZE_FS(_fs) (1 << __fls(_fs))
 
 /* Full Scale range value and gain for Gyro */
-#define LSM6DSM_GYRO_FS_ADDR		0x11
-#define LSM6DSM_GYRO_FS_MASK		0x0c
-
+#define LSM6DSM_GYRO_FS_ADDR 0x11
+#define LSM6DSM_GYRO_FS_MASK 0x0c
 
 /* Supported gyroscope ranges:
  * name(dps) | register | gain(udps/LSB) | actual value(dps)
@@ -255,8 +252,8 @@ struct fstatus {
 	((LSM6DSM_GYRO_FS_MIN_VAL_MDPS << (_reg)) / 1000)
 
 /* FS register address/mask for Acc/Gyro sensors */
-#define LSM6DSM_RANGE_REG(_sensor)  (LSM6DSM_ACCEL_FS_ADDR + (_sensor))
-#define LSM6DSM_RANGE_MASK		0x0c
+#define LSM6DSM_RANGE_REG(_sensor) (LSM6DSM_ACCEL_FS_ADDR + (_sensor))
+#define LSM6DSM_RANGE_MASK 0x0c
 
 /* Status register bitmask for Acc/Gyro data ready */
 enum lsm6dsm_status {
@@ -265,11 +262,11 @@ enum lsm6dsm_status {
 	LSM6DSM_STS_GDA_UP = 0x02
 };
 
-#define LSM6DSM_STS_XLDA_MASK		0x01
-#define LSM6DSM_STS_GDA_MASK		0x02
+#define LSM6DSM_STS_XLDA_MASK 0x01
+#define LSM6DSM_STS_GDA_MASK 0x02
 
 /* Sensor resolution in number of bits: fixed 16 bit */
-#define LSM6DSM_RESOLUTION		16
+#define LSM6DSM_RESOLUTION 16
 
 extern const struct accelgyro_drv lsm6dsm_drv;
 
@@ -347,24 +344,24 @@ struct lsm6dsm_data {
 #if defined(CONFIG_LSM6DSM_SEC_I2C) && defined(CONFIG_MAG_CALIBRATE)
 	union {
 #ifdef CONFIG_MAG_LSM6DSM_BMM150
-		struct bmm150_private_data   compass;
+		struct bmm150_private_data compass;
 #endif
 #ifdef CONFIG_MAG_LSM6DSM_LIS2MDL
-		struct lis2mdl_private_data  compass;
+		struct lis2mdl_private_data compass;
 #endif
-		struct mag_cal_t             cal;
+		struct mag_cal_t cal;
 	};
-#endif  /* CONFIG_MAG_CALIBRATE */
+#endif /* CONFIG_MAG_CALIBRATE */
 };
 
 #ifdef CONFIG_ACCEL_FIFO
-#define LSM6DSM_ACCEL_FIFO_STATE (&((struct lsm6dsm_accel_fifo_state) {}))
+#define LSM6DSM_ACCEL_FIFO_STATE (&((struct lsm6dsm_accel_fifo_state){}))
 #else
 #define LSM6DSM_ACCEL_FIFO_STATE NULL
 #endif
 
-#define LSM6DSM_DATA \
-	((struct lsm6dsm_data) { \
+#define LSM6DSM_DATA                                          \
+	((struct lsm6dsm_data){                               \
 		.accel_fifo_state = LSM6DSM_ACCEL_FIFO_STATE, \
 	})
 
@@ -389,5 +386,21 @@ struct lsm6dsm_data {
 
 int lsm6dsm_set_data_rate(const struct motion_sensor_t *s, int rate, int rnd);
 
+#if defined(CONFIG_ZEPHYR)
+/* Get the motion sensor ID of the LSM6DSM sensor that generates the
+ * interrupt. The interrupt is converted to the event and transferred to
+ * motion sense task that actually handles the interrupt.
+ *
+ * Here we use an alias (lsm6dsm_int) to get the motion sensor ID. This alias
+ * MUST be defined for this driver to work.
+ * aliases {
+ *   lsm6dsm-int = &lid_accel;
+ * };
+ */
+#if DT_NODE_EXISTS(DT_ALIAS(lsm6dsm_int))
+#define CONFIG_ACCEL_LSM6DSM_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(SENSOR_ID(DT_ALIAS(lsm6dsm_int)))
+#endif
+#endif
 
 #endif /* __CROS_EC_ACCELGYRO_LSM6DSM_H */
diff --git a/driver/accelgyro_lsm6dso.c b/driver/accelgyro_lsm6dso.c
index 74731fad27..3123d8f114 100644
--- a/driver/accelgyro_lsm6dso.c
+++ b/driver/accelgyro_lsm6dso.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,10 +23,10 @@
 #define ACCEL_LSM6DSO_INT_ENABLE
 #endif
 
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args)
 
 STATIC_IF(ACCEL_LSM6DSO_INT_ENABLE)
-	volatile uint32_t last_interrupt_timestamp;
+volatile uint32_t last_interrupt_timestamp;
 
 /*
  * When ODR change, the sensor filters need settling time;
@@ -75,7 +75,7 @@ static int config_interrupt(const struct motion_sensor_t *s)
 		return ret;
 
 	int1_ctrl_val |= LSM6DSO_INT_FIFO_TH | LSM6DSO_INT_FIFO_OVR |
-		LSM6DSO_INT_FIFO_FULL;
+			 LSM6DSO_INT_FIFO_FULL;
 
 	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags, LSM6DSO_INT1_CTRL,
 			    int1_ctrl_val);
@@ -171,10 +171,9 @@ static inline int load_fifo(struct motion_sensor_t *main_s,
 	int i;
 
 	for (i = 0; i < fifo_len; i++) {
-		RETURN_ERROR(st_raw_read_n_noinc(main_s->port,
-						 main_s->i2c_spi_addr_flags,
-						 LSM6DSO_FIFO_DATA_ADDR_TAG,
-						 fifo, sizeof(fifo)));
+		RETURN_ERROR(st_raw_read_n_noinc(
+			main_s->port, main_s->i2c_spi_addr_flags,
+			LSM6DSO_FIFO_DATA_ADDR_TAG, fifo, sizeof(fifo)));
 
 		push_fifo_data(main_s, fifo, last_interrupt_timestamp);
 	}
@@ -188,7 +187,7 @@ static inline int load_fifo(struct motion_sensor_t *main_s,
 static int accelgyro_config_fifo(const struct motion_sensor_t *s)
 {
 	int err;
-	struct stprivate_data *data = LSM6DSO_GET_DATA(s);
+	struct stprivate_data *data = s->drv_data;
 	uint8_t reg_val;
 	uint8_t fifo_odr_mask;
 
@@ -205,8 +204,8 @@ static int accelgyro_config_fifo(const struct motion_sensor_t *s)
 
 	fifo_odr_mask = LSM6DSO_FIFO_ODR_MASK(s);
 	reg_val = LSM6DSO_ODR_TO_REG(data->base.odr);
-	err = st_write_data_with_mask(s, LSM6DSO_FIFO_CTRL3_ADDR,
-				      fifo_odr_mask, reg_val);
+	err = st_write_data_with_mask(s, LSM6DSO_FIFO_CTRL3_ADDR, fifo_odr_mask,
+				      reg_val);
 	if (err != EC_SUCCESS)
 		return err;
 
@@ -238,9 +237,9 @@ static int irq_handler(struct motion_sensor_t *s, uint32_t *event)
 
 	do {
 		/* Read how many data patterns on FIFO to read. */
-		RETURN_ERROR(st_raw_read_n_noinc(s->port, s->i2c_spi_addr_flags,
-					LSM6DSO_FIFO_STS1_ADDR,
-					(uint8_t *)&fsts, sizeof(fsts)));
+		RETURN_ERROR(st_raw_read_n_noinc(
+			s->port, s->i2c_spi_addr_flags, LSM6DSO_FIFO_STS1_ADDR,
+			(uint8_t *)&fsts, sizeof(fsts)));
 		if (fsts.len & (LSM6DSO_FIFO_DATA_OVR | LSM6DSO_FIFO_FULL))
 			CPRINTS("%s FIFO Overrun: %04x", s->name, fsts.len);
 
@@ -294,8 +293,7 @@ static int set_range(struct motion_sensor_t *s, int range, int rnd)
 	}
 
 	mutex_lock(s->mutex);
-	err = st_write_data_with_mask(s, ctrl_reg, LSM6DSO_RANGE_MASK,
-				      reg_val);
+	err = st_write_data_with_mask(s, ctrl_reg, LSM6DSO_RANGE_MASK, reg_val);
 	if (err == EC_SUCCESS)
 		s->current_range = newrange;
 
@@ -313,7 +311,7 @@ static int set_range(struct motion_sensor_t *s, int range, int rnd)
 static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
 {
 	int ret, normalized_rate = 0;
-	struct stprivate_data *data = LSM6DSO_GET_DATA(s);
+	struct stprivate_data *data = s->drv_data;
 	uint8_t ctrl_reg, reg_val = 0;
 
 	ctrl_reg = LSM6DSO_ODR_REG(s->type);
@@ -348,8 +346,8 @@ static int is_data_ready(const struct motion_sensor_t *s, int *ready)
 {
 	int ret, tmp;
 
-	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags,
-			   LSM6DSO_STATUS_REG, &tmp);
+	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, LSM6DSO_STATUS_REG,
+			   &tmp);
 	if (ret != EC_SUCCESS) {
 		CPRINTS("%s type:0x%X RS Error", s->name, s->type);
 
@@ -394,8 +392,8 @@ static int read(const struct motion_sensor_t *s, intv3_t v)
 	xyz_reg = get_xyz_reg(s->type);
 
 	/* Read data bytes starting at xyz_reg. */
-	ret = st_raw_read_n_noinc(s->port, s->i2c_spi_addr_flags,
-				  xyz_reg, raw, OUT_XYZ_SIZE);
+	ret = st_raw_read_n_noinc(s->port, s->i2c_spi_addr_flags, xyz_reg, raw,
+				  OUT_XYZ_SIZE);
 	if (ret != EC_SUCCESS)
 		return ret;
 
@@ -408,10 +406,10 @@ static int read(const struct motion_sensor_t *s, intv3_t v)
 static int init(struct motion_sensor_t *s)
 {
 	int ret = 0, tmp;
-	struct stprivate_data *data = LSM6DSO_GET_DATA(s);
+	struct stprivate_data *data = s->drv_data;
 
-	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags,
-			   LSM6DSO_WHO_AM_I_REG, &tmp);
+	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, LSM6DSO_WHO_AM_I_REG,
+			   &tmp);
 	if (ret != EC_SUCCESS)
 		return EC_ERROR_UNKNOWN;
 
@@ -438,10 +436,9 @@ static int init(struct motion_sensor_t *s)
 		 * Output data not updated until have been read.
 		 * Require interrupt to be active low.
 		 */
-		ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-				    LSM6DSO_CTRL3_ADDR,
-				    LSM6DSO_BDU | LSM6DSO_IF_INC
-					| LSM6DSO_H_L_ACTIVE);
+		ret = st_raw_write8(
+			s->port, s->i2c_spi_addr_flags, LSM6DSO_CTRL3_ADDR,
+			LSM6DSO_BDU | LSM6DSO_IF_INC | LSM6DSO_H_L_ACTIVE);
 		if (ret != EC_SUCCESS)
 			goto err_unlock;
 
@@ -471,7 +468,7 @@ err_unlock:
 }
 
 #ifdef CONFIG_BODY_DETECTION
-int get_rms_noise(const struct motion_sensor_t *s)
+static int get_rms_noise(const struct motion_sensor_t *s)
 {
 	/*
 	 * RMS | Acceleration RMS noise in normal/low-power mode
@@ -481,18 +478,6 @@ int get_rms_noise(const struct motion_sensor_t *s)
 }
 #endif
 
-#ifdef CONFIG_GESTURE_HOST_DETECTION
-int lsm_list_activities(const struct motion_sensor_t *s,
-			uint32_t *enabled,
-			uint32_t *disabled)
-{
-	struct stprivate_data *data = LSM6DSO_GET_DATA(s);
-	*enabled = data->enabled_activities;
-	*disabled = data->disabled_activities;
-	return EC_RES_SUCCESS;
-}
-#endif /* CONFIG_GESTURE_HOST_DETECTION */
-
 const struct accelgyro_drv lsm6dso_drv = {
 	.init = init,
 	.read = read,
@@ -508,7 +493,7 @@ const struct accelgyro_drv lsm6dso_drv = {
 	.get_rms_noise = get_rms_noise,
 #endif
 #ifdef CONFIG_GESTURE_HOST_DETECTION
-	.list_activities = lsm_list_activities,
+	.list_activities = st_list_activities,
 #endif
 #endif /* ACCEL_LSM6DSO_INT_ENABLE */
 };
diff --git a/driver/accelgyro_lsm6dso.h b/driver/accelgyro_lsm6dso.h
index 6b7f1138b6..ccc1fa0e84 100644
--- a/driver/accelgyro_lsm6dso.h
+++ b/driver/accelgyro_lsm6dso.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,78 +12,77 @@
 #include "stm_mems_common.h"
 
 /* Access to embedded sensor hub register bank */
-#define LSM6DSO_FUNC_CFG_ACC_ADDR	0x01
-#define LSM6DSO_FUNC_CFG_EN			0x80
+#define LSM6DSO_FUNC_CFG_ACC_ADDR 0x01
+#define LSM6DSO_FUNC_CFG_EN 0x80
 
 /* Who Am I */
-#define LSM6DSO_WHO_AM_I_REG		0x0f
-#define LSM6DSO_WHO_AM_I		0x6c
+#define LSM6DSO_WHO_AM_I_REG 0x0f
+#define LSM6DSO_WHO_AM_I 0x6c
 
 /* Common defines for Acc and Gyro sensors */
-#define LSM6DSO_EN_BIT				0x01
-#define LSM6DSO_DIS_BIT				0x00
+#define LSM6DSO_EN_BIT 0x01
+#define LSM6DSO_DIS_BIT 0x00
 
-#define LSM6DSO_GYRO_OUT_X_L_ADDR	0x22
-#define LSM6DSO_ACCEL_OUT_X_L_ADDR	0x28
+#define LSM6DSO_GYRO_OUT_X_L_ADDR 0x22
+#define LSM6DSO_ACCEL_OUT_X_L_ADDR 0x28
 
-#define LSM6DSO_CTRL1_ADDR		0x10
-#define LSM6DSO_CTRL2_ADDR		0x11
-#define LSM6DSO_CTRL3_ADDR		0x12
-#define LSM6DSO_SW_RESET			0x01
-#define LSM6DSO_IF_INC				0x04
-#define LSM6DSO_PP_OD				0x10
-#define LSM6DSO_H_L_ACTIVE			0x20
-#define LSM6DSO_BDU				0x40
+#define LSM6DSO_CTRL1_ADDR 0x10
+#define LSM6DSO_CTRL2_ADDR 0x11
+#define LSM6DSO_CTRL3_ADDR 0x12
+#define LSM6DSO_SW_RESET 0x01
+#define LSM6DSO_IF_INC 0x04
+#define LSM6DSO_PP_OD 0x10
+#define LSM6DSO_H_L_ACTIVE 0x20
+#define LSM6DSO_BDU 0x40
 
-#define LSM6DSO_CTRL4_ADDR		0x13
-#define LSM6DSO_INT2_ON_INT1_MASK		0x20
+#define LSM6DSO_CTRL4_ADDR 0x13
+#define LSM6DSO_INT2_ON_INT1_MASK 0x20
 
-#define LSM6DSO_CTRL5_ADDR		0x14
-#define LSM6DSO_CTRL6_ADDR		0x15
-#define LSM6DSO_CTRL7_ADDR		0x16
-#define LSM6DSO_CTRL8_ADDR		0x17
-#define LSM6DSO_CTRL9_ADDR		0x18
+#define LSM6DSO_CTRL5_ADDR 0x14
+#define LSM6DSO_CTRL6_ADDR 0x15
+#define LSM6DSO_CTRL7_ADDR 0x16
+#define LSM6DSO_CTRL8_ADDR 0x17
+#define LSM6DSO_CTRL9_ADDR 0x18
 
-#define LSM6DSO_CTRL10_ADDR		0x19
-#define LSM6DSO_TIMESTAMP_EN    		0x20
+#define LSM6DSO_CTRL10_ADDR 0x19
+#define LSM6DSO_TIMESTAMP_EN 0x20
 
-#define LSM6DSO_STATUS_REG		0x1e
+#define LSM6DSO_STATUS_REG 0x1e
 
 /* Output data rate registers and masks */
-#define LSM6DSO_ODR_REG(_sensor) \
-	(LSM6DSO_CTRL1_ADDR + (_sensor))
-#define LSM6DSO_ODR_MASK			0xf0
+#define LSM6DSO_ODR_REG(_sensor) (LSM6DSO_CTRL1_ADDR + (_sensor))
+#define LSM6DSO_ODR_MASK 0xf0
 
 /* FIFO decimator registers and bitmask */
-#define LSM6DSO_FIFO_CTRL1_ADDR		0x07
-#define LSM6DSO_FIFO_CTRL2_ADDR		0x08
+#define LSM6DSO_FIFO_CTRL1_ADDR 0x07
+#define LSM6DSO_FIFO_CTRL2_ADDR 0x08
 
-#define LSM6DSO_FIFO_CTRL3_ADDR		0x09
-#define LSM6DSO_FIFO_ODR_XL_MASK		0x0f
-#define LSM6DSO_FIFO_ODR_G_MASK			0xf0
+#define LSM6DSO_FIFO_CTRL3_ADDR 0x09
+#define LSM6DSO_FIFO_ODR_XL_MASK 0x0f
+#define LSM6DSO_FIFO_ODR_G_MASK 0xf0
 
-#define LSM6DSO_FIFO_CTRL4_ADDR		0x0a
-#define LSM6DSO_FIFO_MODE_MASK			0x07
+#define LSM6DSO_FIFO_CTRL4_ADDR 0x0a
+#define LSM6DSO_FIFO_MODE_MASK 0x07
 
-#define LSM6DSO_INT1_CTRL		0x0d
-#define LSM6DSO_INT2_CTRL		0x0e
-#define LSM6DSO_INT_FIFO_TH			0x08
-#define LSM6DSO_INT_FIFO_OVR			0x10
-#define LSM6DSO_INT_FIFO_FULL			0x20
+#define LSM6DSO_INT1_CTRL 0x0d
+#define LSM6DSO_INT2_CTRL 0x0e
+#define LSM6DSO_INT_FIFO_TH 0x08
+#define LSM6DSO_INT_FIFO_OVR 0x10
+#define LSM6DSO_INT_FIFO_FULL 0x20
 
-#define LSM6DSO_FIFO_STS1_ADDR		0x3a
-#define LSM6DSO_FIFO_STS2_ADDR		0x3b
-#define LSM6DSO_FIFO_DIFF_MASK			0x07ff
-#define LSM6DSO_FIFO_FULL			0x2000
-#define LSM6DSO_FIFO_DATA_OVR			0x4000
-#define LSM6DSO_FIFO_WATERMARK			0x8000
+#define LSM6DSO_FIFO_STS1_ADDR 0x3a
+#define LSM6DSO_FIFO_STS2_ADDR 0x3b
+#define LSM6DSO_FIFO_DIFF_MASK 0x07ff
+#define LSM6DSO_FIFO_FULL 0x2000
+#define LSM6DSO_FIFO_DATA_OVR 0x4000
+#define LSM6DSO_FIFO_WATERMARK 0x8000
 
 /* Out FIFO data register */
-#define LSM6DSO_FIFO_DATA_ADDR_TAG	0x78
+#define LSM6DSO_FIFO_DATA_ADDR_TAG 0x78
 
 /* Registers value for supported FIFO mode */
-#define LSM6DSO_FIFO_MODE_BYPASS_VAL	0x00
-#define LSM6DSO_FIFO_MODE_CONTINUOUS_VAL	0x06
+#define LSM6DSO_FIFO_MODE_BYPASS_VAL 0x00
+#define LSM6DSO_FIFO_MODE_CONTINUOUS_VAL 0x06
 
 /* Define device available in FIFO pattern */
 enum lsm6dso_dev_fifo {
@@ -94,8 +93,8 @@ enum lsm6dso_dev_fifo {
 };
 
 /* Define FIFO data pattern, tag and len */
-#define LSM6DSO_TAG_SIZE		1
-#define LSM6DSO_FIFO_SAMPLE_SIZE	(OUT_XYZ_SIZE + LSM6DSO_TAG_SIZE)
+#define LSM6DSO_TAG_SIZE 1
+#define LSM6DSO_FIFO_SAMPLE_SIZE (OUT_XYZ_SIZE + LSM6DSO_TAG_SIZE)
 
 enum lsm6dso_tag_fifo {
 	LSM6DSO_GYRO_TAG = 0x01,
@@ -110,32 +109,32 @@ struct lsm6dso_fstatus {
 /* ODR reg value from selected data rate in mHz */
 #define LSM6DSO_ODR_TO_REG(_odr) (__fls(_odr / LSM6DSO_ODR_MIN_VAL) + 1)
 
-#define LSM6DSO_FIFO_ODR_MASK(_s) \
+#define LSM6DSO_FIFO_ODR_MASK(_s)                                        \
 	(_s->type == MOTIONSENSE_TYPE_ACCEL ? LSM6DSO_FIFO_ODR_XL_MASK : \
-	 LSM6DSO_FIFO_ODR_G_MASK)
+					      LSM6DSO_FIFO_ODR_G_MASK)
 
 /* Normalized ODR values from selected data rate in mHz */
 #define LSM6DSO_REG_TO_ODR(_reg) (LSM6DSO_ODR_MIN_VAL << (_reg - 1))
 
 /* Full Scale ranges value and gain for Acc */
-#define LSM6DSO_FS_LIST_NUM		4
+#define LSM6DSO_FS_LIST_NUM 4
 
-#define LSM6DSO_ACCEL_FS_ADDR		0x10
-#define LSM6DSO_ACCEL_FS_MASK			0x0c
+#define LSM6DSO_ACCEL_FS_ADDR 0x10
+#define LSM6DSO_ACCEL_FS_MASK 0x0c
 
-#define LSM6DSO_ACCEL_FS_2G_VAL		0x00
-#define LSM6DSO_ACCEL_FS_4G_VAL		0x02
-#define LSM6DSO_ACCEL_FS_8G_VAL		0x03
-#define LSM6DSO_ACCEL_FS_16G_VAL	0x01
+#define LSM6DSO_ACCEL_FS_2G_VAL 0x00
+#define LSM6DSO_ACCEL_FS_4G_VAL 0x02
+#define LSM6DSO_ACCEL_FS_8G_VAL 0x03
+#define LSM6DSO_ACCEL_FS_16G_VAL 0x01
 
-#define LSM6DSO_ACCEL_FS_MAX_VAL	16
+#define LSM6DSO_ACCEL_FS_MAX_VAL 16
 
 /* Accel reg value from Full Scale range */
 static inline uint8_t lsm6dso_accel_fs_reg(int fs)
 {
 	uint8_t ret;
 
-	switch(fs) {
+	switch (fs) {
 	case 2:
 		ret = LSM6DSO_ACCEL_FS_2G_VAL;
 		break;
@@ -154,8 +153,8 @@ static inline uint8_t lsm6dso_accel_fs_reg(int fs)
 #define LSM6DSO_ACCEL_NORMALIZE_FS(_fs) (1 << __fls(_fs))
 
 /* Full Scale range value and gain for Gyro */
-#define LSM6DSO_GYRO_FS_ADDR		0x11
-#define LSM6DSO_GYRO_FS_MASK			0x0c
+#define LSM6DSO_GYRO_FS_ADDR 0x11
+#define LSM6DSO_GYRO_FS_MASK 0x0c
 
 /* Minimal Gyro range in mDPS */
 #define LSM6DSO_GYRO_FS_MIN_VAL_MDPS ((8750 << 15) / 1000)
@@ -170,8 +169,8 @@ static inline uint8_t lsm6dso_accel_fs_reg(int fs)
 	((LSM6DSO_GYRO_FS_MIN_VAL_MDPS << (_reg)) / 1000)
 
 /* FS register address/mask for Acc/Gyro sensors */
-#define LSM6DSO_RANGE_REG(_sensor)  	(LSM6DSO_ACCEL_FS_ADDR + (_sensor))
-#define LSM6DSO_RANGE_MASK  			0x0c
+#define LSM6DSO_RANGE_REG(_sensor) (LSM6DSO_ACCEL_FS_ADDR + (_sensor))
+#define LSM6DSO_RANGE_MASK 0x0c
 
 /* Status register bit for Acc/Gyro data ready */
 enum lsm6dso_status {
@@ -181,11 +180,11 @@ enum lsm6dso_status {
 };
 
 /* Status register bitmask for Acc/Gyro data ready */
-#define LSM6DSO_STS_XLDA_MASK			0x01
-#define LSM6DSO_STS_GDA_MASK			0x02
+#define LSM6DSO_STS_XLDA_MASK 0x01
+#define LSM6DSO_STS_GDA_MASK 0x02
 
 /* Sensor resolution in number of bits: fixed 16 bit */
-#define LSM6DSO_RESOLUTION      	16
+#define LSM6DSO_RESOLUTION 16
 
 /* Aggregate private data for all supported sensor (Acc, Gyro) */
 struct lsm6dso_data {
@@ -200,8 +199,6 @@ struct lsm6dso_data {
  */
 #define LSM6DSO_DISCARD_SAMPLES 3
 
-#define LSM6DSO_GET_DATA(_s) ((struct stprivate_data *)((_s)->drv_data))
-
 /* Macro to initialize motion_sensors structure */
 #define LSM6DSO_ST_DATA(g, type) (&((g).st_data[type]))
 
@@ -224,6 +221,6 @@ void lsm6dso_interrupt(enum gpio_signal signal);
 #define CONFIG_ACCEL_LSM6DSO_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(SENSOR_ID(DT_ALIAS(lsm6dso_int)))
 #endif
-#endif  /* CONFIG_ZEPHYR */
+#endif /* CONFIG_ZEPHYR */
 
 #endif /* __CROS_EC_ACCELGYRO_LSM6DSO_H */
diff --git a/driver/als_al3010.c b/driver/als_al3010.c
index b129dc2f57..b3afe31790 100644
--- a/driver/als_al3010.c
+++ b/driver/als_al3010.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -15,13 +15,13 @@ int al3010_init(void)
 {
 	int ret;
 
-	ret = i2c_write8(I2C_PORT_ALS, AL3010_I2C_ADDR,
-			 AL3010_REG_CONFIG, AL3010_GAIN << 4);
+	ret = i2c_write8(I2C_PORT_ALS, AL3010_I2C_ADDR, AL3010_REG_CONFIG,
+			 AL3010_GAIN << 4);
 	if (ret)
 		return ret;
 
-	return i2c_write8(I2C_PORT_ALS, AL3010_I2C_ADDR,
-			  AL3010_REG_SYSTEM, AL3010_ENABLE);
+	return i2c_write8(I2C_PORT_ALS, AL3010_I2C_ADDR, AL3010_REG_SYSTEM,
+			  AL3010_ENABLE);
 }
 
 /**
@@ -33,8 +33,8 @@ int al3010_read_lux(int *lux, int af)
 	int val;
 	long long val64;
 
-	ret = i2c_read16(I2C_PORT_ALS, AL3010_I2C_ADDR,
-			 AL3010_REG_DATA_LOW, &val);
+	ret = i2c_read16(I2C_PORT_ALS, AL3010_I2C_ADDR, AL3010_REG_DATA_LOW,
+			 &val);
 
 	if (ret)
 		return ret;
diff --git a/driver/als_al3010.h b/driver/als_al3010.h
index 288e255990..6d8db9e7d9 100644
--- a/driver/als_al3010.h
+++ b/driver/als_al3010.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -9,32 +9,32 @@
 #define __CROS_EC_ALS_AL3010_H
 
 /* I2C interface */
-#define AL3010_I2C_ADDR1_FLAGS		0x1C
-#define AL3010_I2C_ADDR2_FLAGS		0x1D
-#define AL3010_I2C_ADDR3_FLAGS		0x1E
+#define AL3010_I2C_ADDR1_FLAGS 0x1C
+#define AL3010_I2C_ADDR2_FLAGS 0x1D
+#define AL3010_I2C_ADDR3_FLAGS 0x1E
 
 /* AL3010 registers */
-#define AL3010_REG_SYSTEM		0x00
-#define AL3010_REG_INT_STATUS		0x01
-#define AL3010_REG_CONFIG		0x10
-#define AL3010_REG_DATA_LOW		0x0C
+#define AL3010_REG_SYSTEM 0x00
+#define AL3010_REG_INT_STATUS 0x01
+#define AL3010_REG_CONFIG 0x10
+#define AL3010_REG_DATA_LOW 0x0C
 
-#define AL3010_ENABLE	0x01
+#define AL3010_ENABLE 0x01
 #define AL3010_GAIN_SELECT 3
 
-#define	AL3010_GAIN_1 0 /* 77806 lx */
-#define	AL3010_GAIN_2 1 /* 19452 lx  */
-#define	AL3010_GAIN_3 2 /* 4863  lx  */
-#define	AL3010_GAIN_4 3 /* 1216  lx  */
-#define AL3010_GAIN	CONCAT2(AL3010_GAIN_, AL3010_GAIN_SELECT)
+#define AL3010_GAIN_1 0 /* 77806 lx */
+#define AL3010_GAIN_2 1 /* 19452 lx  */
+#define AL3010_GAIN_3 2 /* 4863  lx  */
+#define AL3010_GAIN_4 3 /* 1216  lx  */
+#define AL3010_GAIN CONCAT2(AL3010_GAIN_, AL3010_GAIN_SELECT)
 
-#define AL3010_GAIN_SCALE_1 11872	/* 1.1872 lux/count */
-#define AL3010_GAIN_SCALE_2 2968	/* 0.2968 lux/count */
-#define AL3010_GAIN_SCALE_3 742		/* 0.0742 lux/count */
-#define AL3010_GAIN_SCALE_4 186		/* 0.0186 lux/count */
+#define AL3010_GAIN_SCALE_1 11872 /* 1.1872 lux/count */
+#define AL3010_GAIN_SCALE_2 2968 /* 0.2968 lux/count */
+#define AL3010_GAIN_SCALE_3 742 /* 0.0742 lux/count */
+#define AL3010_GAIN_SCALE_4 186 /* 0.0186 lux/count */
 #define AL3010_GAIN_SCALE CONCAT2(AL3010_GAIN_SCALE_, AL3010_GAIN_SELECT)
 
 int al3010_init(void);
 int al3010_read_lux(int *lux, int af);
 
-#endif	/* __CROS_EC_ALS_AL3010_H */
+#endif /* __CROS_EC_ALS_AL3010_H */
diff --git a/driver/als_bh1730.c b/driver/als_bh1730.c
index d4e3a810a5..3e0684dbdb 100644
--- a/driver/als_bh1730.c
+++ b/driver/als_bh1730.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,8 +11,8 @@
 #include "driver/als_bh1730.h"
 #include "i2c.h"
 
-#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_MOTION_SENSE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_MOTION_SENSE, format, ##args)
 
 /**
  * Convert BH1730 data0, data1 to lux
@@ -32,16 +32,16 @@ static int bh1730_convert_to_lux(uint32_t data0_1)
 	else
 		d_temp = d1_1k / data0;
 
-	if(d_temp < BH1730_LUXTH1_1K) {
+	if (d_temp < BH1730_LUXTH1_1K) {
 		d0_1k = BH1730_LUXTH1_D0_1K * data0;
 		d1_1k = BH1730_LUXTH1_D1_1K * data1;
-	} else if(d_temp < BH1730_LUXTH2_1K) {
+	} else if (d_temp < BH1730_LUXTH2_1K) {
 		d0_1k = BH1730_LUXTH2_D0_1K * data0;
 		d1_1k = BH1730_LUXTH2_D1_1K * data1;
-	} else if(d_temp < BH1730_LUXTH3_1K) {
+	} else if (d_temp < BH1730_LUXTH3_1K) {
 		d0_1k = BH1730_LUXTH3_D0_1K * data0;
 		d1_1k = BH1730_LUXTH3_D1_1K * data1;
-	} else if(d_temp < BH1730_LUXTH4_1K) {
+	} else if (d_temp < BH1730_LUXTH4_1K) {
 		d0_1k = BH1730_LUXTH4_D0_1K * data0;
 		d1_1k = BH1730_LUXTH4_D1_1K * data1;
 	} else
@@ -64,8 +64,8 @@ static int bh1730_read_lux(const struct motion_sensor_t *s, intv3_t v)
 	int data0_1;
 
 	/* read data0 and data1 from sensor */
-	ret = i2c_read32(s->port, s->i2c_spi_addr_flags,
-			 BH1730_DATA0LOW, &data0_1);
+	ret = i2c_read32(s->port, s->i2c_spi_addr_flags, BH1730_DATA0LOW,
+			 &data0_1);
 	if (ret != EC_SUCCESS) {
 		CPRINTF("bh1730_read_lux - fail %d\n", ret);
 		return ret;
@@ -88,8 +88,7 @@ static int bh1730_read_lux(const struct motion_sensor_t *s, intv3_t v)
 	}
 }
 
-static int bh1730_set_range(struct motion_sensor_t *s, int range,
-			     int rnd)
+static int bh1730_set_range(struct motion_sensor_t *s, int range, int rnd)
 {
 	/* Range is fixed by hardware */
 	if (range != s->default_range)
@@ -99,8 +98,8 @@ static int bh1730_set_range(struct motion_sensor_t *s, int range,
 	return EC_SUCCESS;
 }
 
-static int bh1730_set_data_rate(const struct motion_sensor_t *s,
-				int rate, int roundup)
+static int bh1730_set_data_rate(const struct motion_sensor_t *s, int rate,
+				int roundup)
 {
 	struct bh1730_drv_data_t *drv_data = BH1730_GET_DATA(s);
 
@@ -118,15 +117,13 @@ static int bh1730_get_data_rate(const struct motion_sensor_t *s)
 }
 
 static int bh1730_set_offset(const struct motion_sensor_t *s,
-			const int16_t *offset,
-			int16_t    temp)
+			     const int16_t *offset, int16_t temp)
 {
 	return EC_SUCCESS;
 }
 
-static int bh1730_get_offset(const struct motion_sensor_t *s,
-			int16_t   *offset,
-			int16_t    *temp)
+static int bh1730_get_offset(const struct motion_sensor_t *s, int16_t *offset,
+			     int16_t *temp)
 {
 	*offset = 0;
 
@@ -141,10 +138,9 @@ static int bh1730_init(struct motion_sensor_t *s)
 	int ret;
 
 	/* power and measurement bit high */
-	ret = i2c_write8(s->port, s->i2c_spi_addr_flags,
-			BH1730_CONTROL,
-			BH1730_CONTROL_POWER_ENABLE
-			      | BH1730_CONTROL_ADC_EN_ENABLE);
+	ret = i2c_write8(s->port, s->i2c_spi_addr_flags, BH1730_CONTROL,
+			 BH1730_CONTROL_POWER_ENABLE |
+				 BH1730_CONTROL_ADC_EN_ENABLE);
 
 	if (ret != EC_SUCCESS) {
 		CPRINTF("bh1730_init_sensor - enable fail %d\n", ret);
@@ -152,15 +148,15 @@ static int bh1730_init(struct motion_sensor_t *s)
 	}
 
 	/* set timing */
-	ret = i2c_write8(s->port, s->i2c_spi_addr_flags,
-			 BH1730_TIMING, BH1730_CONF_ITIME);
+	ret = i2c_write8(s->port, s->i2c_spi_addr_flags, BH1730_TIMING,
+			 BH1730_CONF_ITIME);
 	if (ret != EC_SUCCESS) {
 		CPRINTF("bh1730_init_sensor - time fail %d\n", ret);
 		return ret;
 	}
 	/* set ADC gain */
-	ret = i2c_write8(s->port, s->i2c_spi_addr_flags,
-			 BH1730_GAIN, BH1730_CONF_GAIN);
+	ret = i2c_write8(s->port, s->i2c_spi_addr_flags, BH1730_GAIN,
+			 BH1730_CONF_GAIN);
 
 	if (ret != EC_SUCCESS) {
 		CPRINTF("bh1730_init_sensor - gain fail %d\n", ret);
diff --git a/driver/als_bh1730.h b/driver/als_bh1730.h
index f4bbc37a13..ab5a34b92b 100644
--- a/driver/als_bh1730.h
+++ b/driver/als_bh1730.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -9,42 +9,42 @@
 #define __CROS_EC_ALS_BH1730_H
 
 /* I2C interface */
-#define BH1730_I2C_ADDR_FLAGS	0x29
+#define BH1730_I2C_ADDR_FLAGS 0x29
 
 /* BH1730 registers */
-#define BH1730_CONTROL		0x80
-#define BH1730_TIMING		0x81
-#define BH1730_INTERRUPT	0x82
-#define BH1730_THLLOW		0x83
-#define BH1730_THLHIGH		0x84
-#define BH1730_THHLOW		0x85
-#define BH1730_THHHIGH		0x86
-#define BH1730_GAIN		0x87
-#define BH1730_OPART_ID		0x92
-#define BH1730_DATA0LOW		0x94
-#define BH1730_DATA0HIGH	0x95
-#define BH1730_DATA1LOW		0x96
-#define BH1730_DATA1HIGH	0x97
+#define BH1730_CONTROL 0x80
+#define BH1730_TIMING 0x81
+#define BH1730_INTERRUPT 0x82
+#define BH1730_THLLOW 0x83
+#define BH1730_THLHIGH 0x84
+#define BH1730_THHLOW 0x85
+#define BH1730_THHHIGH 0x86
+#define BH1730_GAIN 0x87
+#define BH1730_OPART_ID 0x92
+#define BH1730_DATA0LOW 0x94
+#define BH1730_DATA0HIGH 0x95
+#define BH1730_DATA1LOW 0x96
+#define BH1730_DATA1HIGH 0x97
 /* Software reset */
-#define BH1730_RESET		0xE4
+#define BH1730_RESET 0xE4
 
 /* Registers bits */
-#define BH1730_CONTROL_ADC_INTR_INACTIVE	(0x00 << 5)
-#define BH1730_CONTROL_ADC_INTR_ACTIVE		(0x01 << 5)
-#define BH1730_CONTROL_ADC_VALID		(0x01 << 4)
-#define BH1730_CONTROL_ONE_TIME_CONTINOUS	(0x00 << 3)
-#define BH1730_CONTROL_ONE_TIME_ONETIME		(0x01 << 3)
-#define BH1730_CONTROL_DATA_SEL_TYPE0_AND_1	(0x00 << 2)
-#define BH1730_CONTROL_DATA_SEL_TYPE0		(0x01 << 2)
-#define BH1730_CONTROL_ADC_EN_DISABLE		(0x00 << 1)
-#define BH1730_CONTROL_ADC_EN_ENABLE		(0x01 << 1)
-#define BH1730_CONTROL_POWER_DISABLE		(0x00 << 0)
-#define BH1730_CONTROL_POWER_ENABLE		(0x01 << 0)
+#define BH1730_CONTROL_ADC_INTR_INACTIVE (0x00 << 5)
+#define BH1730_CONTROL_ADC_INTR_ACTIVE (0x01 << 5)
+#define BH1730_CONTROL_ADC_VALID (0x01 << 4)
+#define BH1730_CONTROL_ONE_TIME_CONTINOUS (0x00 << 3)
+#define BH1730_CONTROL_ONE_TIME_ONETIME (0x01 << 3)
+#define BH1730_CONTROL_DATA_SEL_TYPE0_AND_1 (0x00 << 2)
+#define BH1730_CONTROL_DATA_SEL_TYPE0 (0x01 << 2)
+#define BH1730_CONTROL_ADC_EN_DISABLE (0x00 << 1)
+#define BH1730_CONTROL_ADC_EN_ENABLE (0x01 << 1)
+#define BH1730_CONTROL_POWER_DISABLE (0x00 << 0)
+#define BH1730_CONTROL_POWER_ENABLE (0x01 << 0)
 
-#define BH1730_GAIN_GAIN_X1_GAIN		(0x00 << 0)
-#define BH1730_GAIN_GAIN_X2_GAIN		(0x01 << 0)
-#define BH1730_GAIN_GAIN_X64_GAIN		(0x02 << 0)
-#define BH1730_GAIN_GAIN_X128_GAIN		(0x03 << 0)
+#define BH1730_GAIN_GAIN_X1_GAIN (0x00 << 0)
+#define BH1730_GAIN_GAIN_X2_GAIN (0x01 << 0)
+#define BH1730_GAIN_GAIN_X64_GAIN (0x02 << 0)
+#define BH1730_GAIN_GAIN_X128_GAIN (0x03 << 0)
 
 /* Sensor configuration */
 /* Select Gain */
@@ -54,10 +54,10 @@
 /* Select Itime, 0xDA is 102.6ms = 38*2.7ms */
 #define BH1730_CONF_ITIME 0xDA
 #define ITIME_MS_X_10 ((256 - BH1730_CONF_ITIME) * 27)
-#define ITIME_MS_X_1K (ITIME_MS_X_10*100)
+#define ITIME_MS_X_1K (ITIME_MS_X_10 * 100)
 
 /* default Itime is about 10Hz */
-#define BH1730_10000_MHZ (10*1000)
+#define BH1730_10000_MHZ (10 * 1000)
 #define BH1730_MAX_FREQ BH1730_10000_MHZ
 /*
  * 10Hz is too fast for the AP: allow the AP query data less often, the EC will
@@ -70,21 +70,21 @@
  * parameters are not defined.
  */
 #ifndef CONFIG_ALS_BH1730_LUXTH_PARAMS
-#define BH1730_LUXTH1_1K                260
-#define BH1730_LUXTH1_D0_1K             1290
-#define BH1730_LUXTH1_D1_1K             2733
-#define BH1730_LUXTH2_1K                550
-#define BH1730_LUXTH2_D0_1K             797
-#define BH1730_LUXTH2_D1_1K             859
-#define BH1730_LUXTH3_1K                1090
-#define BH1730_LUXTH3_D0_1K             510
-#define BH1730_LUXTH3_D1_1K             345
-#define BH1730_LUXTH4_1K                2130
-#define BH1730_LUXTH4_D0_1K             276
-#define BH1730_LUXTH4_D1_1K             130
+#define BH1730_LUXTH1_1K 260
+#define BH1730_LUXTH1_D0_1K 1290
+#define BH1730_LUXTH1_D1_1K 2733
+#define BH1730_LUXTH2_1K 550
+#define BH1730_LUXTH2_D0_1K 797
+#define BH1730_LUXTH2_D1_1K 859
+#define BH1730_LUXTH3_1K 1090
+#define BH1730_LUXTH3_D0_1K 510
+#define BH1730_LUXTH3_D1_1K 345
+#define BH1730_LUXTH4_1K 2130
+#define BH1730_LUXTH4_D0_1K 276
+#define BH1730_LUXTH4_D1_1K 130
 #endif
 
-#define BH1730_GET_DATA(_s)    ((struct bh1730_drv_data_t *)(_s)->drv_data)
+#define BH1730_GET_DATA(_s) ((struct bh1730_drv_data_t *)(_s)->drv_data)
 
 struct bh1730_drv_data_t {
 	int rate;
@@ -93,4 +93,4 @@ struct bh1730_drv_data_t {
 
 extern const struct accelgyro_drv bh1730_drv;
 
-#endif	/* __CROS_EC_ALS_BH1730_H */
+#endif /* __CROS_EC_ALS_BH1730_H */
diff --git a/driver/als_cm32183.c b/driver/als_cm32183.c
index 13ea942dd1..d97c179fe8 100644
--- a/driver/als_cm32183.c
+++ b/driver/als_cm32183.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -20,7 +20,7 @@ struct cm32183_drv_data {
 	int16_t offset;
 };
 
-#define CM32183_GET_DATA(_s)	((struct cm32183_drv_data *)(_s)->drv_data)
+#define CM32183_GET_DATA(_s) ((struct cm32183_drv_data *)(_s)->drv_data)
 
 /*
  * Read CM32183 light sensor data.
@@ -31,7 +31,7 @@ static int cm32183_read_lux(int *lux)
 	int data;
 
 	ret = i2c_read16(I2C_PORT_SENSOR, CM32183_I2C_ADDR,
-		CM32183_REG_ALS_RESULT, &data);
+			 CM32183_REG_ALS_RESULT, &data);
 
 	if (ret)
 		return ret;
@@ -39,7 +39,7 @@ static int cm32183_read_lux(int *lux)
 	/*
 	 * lux = data * 0.016
 	 */
-	*lux = (data * 16)/1000;
+	*lux = (data * 16) / 1000;
 
 	return EC_SUCCESS;
 }
@@ -60,7 +60,7 @@ static int cm32183_read(const struct motion_sensor_t *s, intv3_t v)
 
 	lux_data += drv_data->offset;
 	lux_data = lux_data * drv_data->scale +
-		lux_data * drv_data->uscale / 10000;
+		   lux_data * drv_data->uscale / 10000;
 
 	v[0] = lux_data;
 	v[1] = 0;
@@ -77,14 +77,13 @@ static int cm32183_read(const struct motion_sensor_t *s, intv3_t v)
 	return EC_SUCCESS;
 }
 
-static int cm32183_set_range(struct motion_sensor_t *s, int range,
-			     int rnd)
+static int cm32183_set_range(struct motion_sensor_t *s, int range, int rnd)
 {
 	return EC_SUCCESS;
 }
 
-static int cm32183_set_data_rate(const struct motion_sensor_t *s,
-				int rate, int roundup)
+static int cm32183_set_data_rate(const struct motion_sensor_t *s, int rate,
+				 int roundup)
 {
 	CM32183_GET_DATA(s)->rate = rate;
 	return EC_SUCCESS;
@@ -96,14 +95,14 @@ static int cm32183_get_data_rate(const struct motion_sensor_t *s)
 }
 
 static int cm32183_set_offset(const struct motion_sensor_t *s,
-			const int16_t *offset, int16_t temp)
+			      const int16_t *offset, int16_t temp)
 {
 	/* TODO: check calibration method */
 	return EC_SUCCESS;
 }
 
-static int cm32183_get_offset(const struct motion_sensor_t *s,
-			int16_t *offset, int16_t *temp)
+static int cm32183_get_offset(const struct motion_sensor_t *s, int16_t *offset,
+			      int16_t *temp)
 {
 	*offset = CM32183_GET_DATA(s)->offset;
 	return EC_SUCCESS;
@@ -117,14 +116,14 @@ static int cm32183_init(struct motion_sensor_t *s)
 	int ret;
 	int data;
 
-	ret = i2c_write16(s->port, s->i2c_spi_addr_flags,
-		CM32183_REG_CONFIGURE, CM32183_REG_CONFIGURE_CH_EN);
+	ret = i2c_write16(s->port, s->i2c_spi_addr_flags, CM32183_REG_CONFIGURE,
+			  CM32183_REG_CONFIGURE_CH_EN);
 
 	if (ret)
 		return ret;
 
-	ret = i2c_read16(s->port, s->i2c_spi_addr_flags,
-		CM32183_REG_ALS_RESULT, &data);
+	ret = i2c_read16(s->port, s->i2c_spi_addr_flags, CM32183_REG_ALS_RESULT,
+			 &data);
 
 	if (ret)
 		return ret;
diff --git a/driver/als_cm32183.h b/driver/als_cm32183.h
index 57802e9f96..f0dbaf3c03 100644
--- a/driver/als_cm32183.h
+++ b/driver/als_cm32183.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -9,27 +9,27 @@
 #define __CROS_EC_ALS_CM32183_H
 
 /* I2C interface */
-#define CM32183_I2C_ADDR		0x29
+#define CM32183_I2C_ADDR 0x29
 
 /* CM32183 registers */
-#define CM32183_REG_CONFIGURE		0x00
+#define CM32183_REG_CONFIGURE 0x00
 
-#define CM32183_REG_CONFIGURE_CH_EN			0x0004
+#define CM32183_REG_CONFIGURE_CH_EN 0x0004
 
 /* ALS Sensitivity_mode (BIT 12:11) */
-#define CM32183_REG_CONFIGURE_ALS_SENSITIVITY_MASK	GENMASK(12, 11)
-#define CM32183_REG_CONFIGURE_ALS_SENSITIVITY_SHIFT		11
-#define CM32183_REG_CONFIGURE_ALS_SENSITIVITY_1		0
-#define CM32183_REG_CONFIGURE_ALS_SENSITIVITY_2		1
-#define CM32183_REG_CONFIGURE_ALS_SENSITIVITY_1_DIV_8		2
-#define CM32183_REG_CONFIGURE_ALS_SENSITIVITY_1_DIV_4		3
+#define CM32183_REG_CONFIGURE_ALS_SENSITIVITY_MASK GENMASK(12, 11)
+#define CM32183_REG_CONFIGURE_ALS_SENSITIVITY_SHIFT 11
+#define CM32183_REG_CONFIGURE_ALS_SENSITIVITY_1 0
+#define CM32183_REG_CONFIGURE_ALS_SENSITIVITY_2 1
+#define CM32183_REG_CONFIGURE_ALS_SENSITIVITY_1_DIV_8 2
+#define CM32183_REG_CONFIGURE_ALS_SENSITIVITY_1_DIV_4 3
 
 /*
  * Gain mode
  * 0 Gain*1
  * 1 Gain*2  (bit 10)
  */
-#define CM32183_REG_CONFIGURE_GAIN  BIT(10)
+#define CM32183_REG_CONFIGURE_GAIN BIT(10)
 
 /*
  * ALS integration time setting which represents how long
@@ -40,12 +40,12 @@
  *  0010         400ms
  *  0011         800ms
  */
-#define CM32183_REG_CONFIGURE_ALS_INTEGRATION_MASK	GENMASK(9, 6)
-#define CM32183_REG_CONFIGURE_ALS_INTEGRATION_SHIFT		6
-#define CM32183_REG_CONFIGURE_ALS_INTEGRATION_SET100MS	0
-#define CM32183_REG_CONFIGURE_ALS_INTEGRATION_SET200MS	1
-#define CM32183_REG_CONFIGURE_ALS_INTEGRATION_SET400MS	2
-#define CM32183_REG_CONFIGURE_ALS_INTEGRATION_SET800MS	3
+#define CM32183_REG_CONFIGURE_ALS_INTEGRATION_MASK GENMASK(9, 6)
+#define CM32183_REG_CONFIGURE_ALS_INTEGRATION_SHIFT 6
+#define CM32183_REG_CONFIGURE_ALS_INTEGRATION_SET100MS 0
+#define CM32183_REG_CONFIGURE_ALS_INTEGRATION_SET200MS 1
+#define CM32183_REG_CONFIGURE_ALS_INTEGRATION_SET400MS 2
+#define CM32183_REG_CONFIGURE_ALS_INTEGRATION_SET800MS 3
 
 /*
  * ALS interrupt persistence setting.The interrupt pin is
@@ -57,47 +57,47 @@
  *    10                 4
  *    11                 8
  */
-#define CM32183_REG_CONFIGURE_MEASUREMENT_MASK	GENMASK(5, 4)
-#define CM32183_REG_CONFIGURE_MEASUREMENT_SHIFT		4
-#define CM32183_REG_CONFIGURE_MEASUREMENT_CYCLE_1	0
-#define CM32183_REG_CONFIGURE_MEASUREMENT_CYCLE_2	1
-#define CM32183_REG_CONFIGURE_MEASUREMENT_CYCLE_4	2
-#define CM32183_REG_CONFIGURE_MEASUREMENT_CYCLE_8	3
+#define CM32183_REG_CONFIGURE_MEASUREMENT_MASK GENMASK(5, 4)
+#define CM32183_REG_CONFIGURE_MEASUREMENT_SHIFT 4
+#define CM32183_REG_CONFIGURE_MEASUREMENT_CYCLE_1 0
+#define CM32183_REG_CONFIGURE_MEASUREMENT_CYCLE_2 1
+#define CM32183_REG_CONFIGURE_MEASUREMENT_CYCLE_4 2
+#define CM32183_REG_CONFIGURE_MEASUREMENT_CYCLE_8 3
 
 /*
  * channel selection of interrupt (BIT 3)
  * 0   ALS CH interrupt
  * 1   White CH interrupt
  */
-#define CM32183_REG_CONFIGURE_CHANNEL_SELECTION  BIT(3)
+#define CM32183_REG_CONFIGURE_CHANNEL_SELECTION BIT(3)
 
 /*
  * Channel enable (BIT 2)
  *  0   ALS CH enable only
  *  1   ALS & White CH enable
  */
-#define CM32183_REG_CONFIGURE_CHANNEL_ENABLE  BIT(2)
+#define CM32183_REG_CONFIGURE_CHANNEL_ENABLE BIT(2)
 
 /* enable/disable interrupt function (BIT 1) */
-#define CM32183_REG_CONFIGURE_INTERRUPT_ENABLE  BIT(1)
+#define CM32183_REG_CONFIGURE_INTERRUPT_ENABLE BIT(1)
 
 /*
  * how to power on and shutdown sensor (BIT 0)
  * 0   power on
  * 1   shutdown
  */
-#define CM32183_REG_CONFIGURE_POWER  BIT(0)
+#define CM32183_REG_CONFIGURE_POWER BIT(0)
 
-#define CM32183_REG_INT_HSB		0x01
-#define CM32183_REG_INT_LSB		0x02
-#define CM32183_REG_ALS_RESULT		0x04
-#define CM32183_REG_WHITE_RESULT		0x05
+#define CM32183_REG_INT_HSB 0x01
+#define CM32183_REG_INT_LSB 0x02
+#define CM32183_REG_ALS_RESULT 0x04
+#define CM32183_REG_WHITE_RESULT 0x05
 
-#define CM32183_REG_TRIGGER      0x06
+#define CM32183_REG_TRIGGER 0x06
 
-#define CM32183_REG_TRIGGER_LOW_THRESHOLD     BIT(15)
-#define CM32183_REG_TRIGGER_HIGH_THRESHOLD    BIT(14)
+#define CM32183_REG_TRIGGER_LOW_THRESHOLD BIT(15)
+#define CM32183_REG_TRIGGER_HIGH_THRESHOLD BIT(14)
 
 extern const struct accelgyro_drv cm32183_drv;
 
-#endif	/* __CROS_EC_ALS_CM32183_H */
+#endif /* __CROS_EC_ALS_CM32183_H */
diff --git a/driver/als_isl29035.c b/driver/als_isl29035.c
index db77a19f09..3391a25e01 100644
--- a/driver/als_isl29035.c
+++ b/driver/als_isl29035.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -9,16 +9,16 @@
 #include "i2c.h"
 
 /* I2C interface */
-#define ILS29035_I2C_ADDR_FLAGS	0x44
-#define ILS29035_REG_COMMAND_I  0
+#define ILS29035_I2C_ADDR_FLAGS 0x44
+#define ILS29035_REG_COMMAND_I 0
 #define ILS29035_REG_COMMAND_II 1
-#define ILS29035_REG_DATA_LSB   2
-#define ILS29035_REG_DATA_MSB   3
+#define ILS29035_REG_DATA_LSB 2
+#define ILS29035_REG_DATA_MSB 3
 #define ILS29035_REG_INT_LT_LSB 4
 #define ILS29035_REG_INT_LT_MSB 5
 #define ILS29035_REG_INT_HT_LSB 6
 #define ILS29035_REG_INT_HT_MSB 7
-#define ILS29035_REG_ID         15
+#define ILS29035_REG_ID 15
 
 int isl29035_init(void)
 {
diff --git a/driver/als_isl29035.h b/driver/als_isl29035.h
index 153ba148f9..db67837375 100644
--- a/driver/als_isl29035.h
+++ b/driver/als_isl29035.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,4 +11,4 @@
 int isl29035_init(void);
 int isl29035_read_lux(int *lux, int af);
 
-#endif	/* __CROS_EC_ALS_ISL29035_H */
+#endif /* __CROS_EC_ALS_ISL29035_H */
diff --git a/driver/als_opt3001.c b/driver/als_opt3001.c
index 53f2b7df89..6939e330dd 100644
--- a/driver/als_opt3001.c
+++ b/driver/als_opt3001.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -17,11 +17,10 @@ static int opt3001_i2c_read(const int reg, int *data_ptr)
 {
 	int ret;
 
-	ret = i2c_read16(I2C_PORT_ALS, OPT3001_I2C_ADDR_FLAGS,
-			 reg, data_ptr);
+	ret = i2c_read16(I2C_PORT_ALS, OPT3001_I2C_ADDR_FLAGS, reg, data_ptr);
 	if (!ret)
 		*data_ptr = ((*data_ptr << 8) & 0xFF00) |
-				((*data_ptr >> 8) & 0x00FF);
+			    ((*data_ptr >> 8) & 0x00FF);
 
 	return ret;
 }
@@ -32,8 +31,7 @@ static int opt3001_i2c_read(const int reg, int *data_ptr)
 static int opt3001_i2c_write(const int reg, int data)
 {
 	data = ((data << 8) & 0xFF00) | ((data >> 8) & 0x00FF);
-	return i2c_write16(I2C_PORT_ALS, OPT3001_I2C_ADDR_FLAGS,
-			   reg, data);
+	return i2c_write16(I2C_PORT_ALS, OPT3001_I2C_ADDR_FLAGS, reg, data);
 }
 
 /**
@@ -102,25 +100,23 @@ struct i2c_stress_test_dev opt3001_i2c_stress_test_dev = {
 	.i2c_read_dev = &opt3001_i2c_read,
 	.i2c_write_dev = &opt3001_i2c_write,
 };
-#endif  /* CONFIG_CMD_I2C_STRESS_TEST_ALS */
-#else  /* HAS_TASK_ALS */
+#endif /* CONFIG_CMD_I2C_STRESS_TEST_ALS */
+#else /* HAS_TASK_ALS */
 #include "accelgyro.h"
 #include "math_util.h"
 
 /**
  *  Read register from OPT3001 light sensor.
  */
-static int opt3001_i2c_read(const int port,
-			    const uint16_t i2c_addr_flags,
+static int opt3001_i2c_read(const int port, const uint16_t i2c_addr_flags,
 			    const int reg, int *data_ptr)
 {
 	int ret;
 
-	ret = i2c_read16(port, i2c_addr_flags,
-			 reg, data_ptr);
+	ret = i2c_read16(port, i2c_addr_flags, reg, data_ptr);
 	if (!ret)
 		*data_ptr = ((*data_ptr << 8) & 0xFF00) |
-				((*data_ptr >> 8) & 0x00FF);
+			    ((*data_ptr >> 8) & 0x00FF);
 
 	return ret;
 }
@@ -128,8 +124,7 @@ static int opt3001_i2c_read(const int port,
 /**
  *  Write register to OPT3001 light sensor.
  */
-static int opt3001_i2c_write(const int port,
-			     const uint16_t i2c_addr_flags,
+static int opt3001_i2c_write(const int port, const uint16_t i2c_addr_flags,
 			     const int reg, int data)
 {
 	data = ((data << 8) & 0xFF00) | ((data >> 8) & 0x00FF);
@@ -177,8 +172,7 @@ int opt3001_read_lux(const struct motion_sensor_t *s, intv3_t v)
 	}
 }
 
-static int opt3001_set_range(struct motion_sensor_t *s, int range,
-			     int rnd)
+static int opt3001_set_range(struct motion_sensor_t *s, int range, int rnd)
 {
 	struct opt3001_drv_data_t *drv_data = OPT3001_GET_DATA(s);
 
@@ -188,8 +182,8 @@ static int opt3001_set_range(struct motion_sensor_t *s, int range,
 	return EC_SUCCESS;
 }
 
-static int opt3001_set_data_rate(const struct motion_sensor_t *s,
-				int rate, int roundup)
+static int opt3001_set_data_rate(const struct motion_sensor_t *s, int rate,
+				 int roundup)
 {
 	struct opt3001_drv_data_t *drv_data = OPT3001_GET_DATA(s);
 	int rv;
@@ -216,10 +210,9 @@ static int opt3001_set_data_rate(const struct motion_sensor_t *s,
 	if (rv)
 		return rv;
 
-	rv = opt3001_i2c_write(s->port, s->i2c_spi_addr_flags,
-			       OPT3001_REG_CONFIGURE,
-			       (reg & OPT3001_MODE_MASK) |
-				   (mode << OPT3001_MODE_OFFSET));
+	rv = opt3001_i2c_write(
+		s->port, s->i2c_spi_addr_flags, OPT3001_REG_CONFIGURE,
+		(reg & OPT3001_MODE_MASK) | (mode << OPT3001_MODE_OFFSET));
 	if (rv)
 		return rv;
 
@@ -235,8 +228,7 @@ static int opt3001_get_data_rate(const struct motion_sensor_t *s)
 }
 
 static int opt3001_set_offset(const struct motion_sensor_t *s,
-			const int16_t *offset,
-			int16_t    temp)
+			      const int16_t *offset, int16_t temp)
 {
 	struct opt3001_drv_data_t *drv_data = OPT3001_GET_DATA(s);
 
@@ -244,9 +236,8 @@ static int opt3001_set_offset(const struct motion_sensor_t *s,
 	return EC_SUCCESS;
 }
 
-static int opt3001_get_offset(const struct motion_sensor_t *s,
-			int16_t   *offset,
-			int16_t    *temp)
+static int opt3001_get_offset(const struct motion_sensor_t *s, int16_t *offset,
+			      int16_t *temp)
 {
 	struct opt3001_drv_data_t *drv_data = OPT3001_GET_DATA(s);
 
@@ -283,8 +274,8 @@ static int opt3001_init(struct motion_sensor_t *s)
 	 * [11]   : 1b    Conversion time 800ms
 	 * [4]    : 1b    Latched window-style comparison operation
 	 */
-	opt3001_i2c_write(s->port, s->i2c_spi_addr_flags,
-			  OPT3001_REG_CONFIGURE, 0xC810);
+	opt3001_i2c_write(s->port, s->i2c_spi_addr_flags, OPT3001_REG_CONFIGURE,
+			  0xC810);
 
 	opt3001_set_range(s, s->default_range, 0);
 
@@ -311,5 +302,5 @@ struct i2c_stress_test_dev opt3001_i2c_stress_test_dev = {
 	.i2c_read = &opt3001_i2c_read,
 	.i2c_write = &opt3001_i2c_write,
 };
-#endif  /* CONFIG_CMD_I2C_STRESS_TEST_ALS */
-#endif  /* HAS_TASK_ALS */
+#endif /* CONFIG_CMD_I2C_STRESS_TEST_ALS */
+#endif /* HAS_TASK_ALS */
diff --git a/driver/als_opt3001.h b/driver/als_opt3001.h
index 96b47232d1..54885c74ae 100644
--- a/driver/als_opt3001.h
+++ b/driver/als_opt3001.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -9,39 +9,39 @@
 #define __CROS_EC_ALS_OPT3001_H
 
 /* I2C interface */
-#define OPT3001_I2C_ADDR1_FLAGS		0x44
-#define OPT3001_I2C_ADDR2_FLAGS		0x45
-#define OPT3001_I2C_ADDR3_FLAGS		0x46
-#define OPT3001_I2C_ADDR4_FLAGS		0x47
+#define OPT3001_I2C_ADDR1_FLAGS 0x44
+#define OPT3001_I2C_ADDR2_FLAGS 0x45
+#define OPT3001_I2C_ADDR3_FLAGS 0x46
+#define OPT3001_I2C_ADDR4_FLAGS 0x47
 
 /* OPT3001 registers */
-#define OPT3001_REG_RESULT		0x00
-#define OPT3001_REG_CONFIGURE		0x01
-#define OPT3001_RANGE_OFFSET			12
-#define OPT3001_RANGE_MASK			0x0fff
-#define OPT3001_MODE_OFFSET			9
-#define OPT3001_MODE_MASK			0xf9ff
+#define OPT3001_REG_RESULT 0x00
+#define OPT3001_REG_CONFIGURE 0x01
+#define OPT3001_RANGE_OFFSET 12
+#define OPT3001_RANGE_MASK 0x0fff
+#define OPT3001_MODE_OFFSET 9
+#define OPT3001_MODE_MASK 0xf9ff
 enum opt3001_mode {
 	OPT3001_MODE_SUSPEND,
 	OPT3001_MODE_FORCED,
 	OPT3001_MODE_CONTINUOUS,
 };
 
-#define OPT3001_REG_INT_LIMIT_LSB	0x02
-#define OPT3001_REG_INT_LIMIT_MSB	0x03
-#define OPT3001_REG_MAN_ID		0x7e
-#define OPT3001_REG_DEV_ID		0x7f
+#define OPT3001_REG_INT_LIMIT_LSB 0x02
+#define OPT3001_REG_INT_LIMIT_MSB 0x03
+#define OPT3001_REG_MAN_ID 0x7e
+#define OPT3001_REG_DEV_ID 0x7f
 
 /* OPT3001 register values */
-#define OPT3001_MANUFACTURER_ID		0x5449
-#define OPT3001_DEVICE_ID		0x3001
+#define OPT3001_MANUFACTURER_ID 0x5449
+#define OPT3001_DEVICE_ID 0x3001
 
 /*
  * Min and Max sampling frequency in mHz.
  * Due to integration set at 800ms, we limit max frequency to 1Hz.
  */
-#define OPT3001_LIGHT_MIN_FREQ          100
-#define OPT3001_LIGHT_MAX_FREQ          1000
+#define OPT3001_LIGHT_MIN_FREQ 100
+#define OPT3001_LIGHT_MAX_FREQ 1000
 #if (CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ <= OPT3001_LIGHT_MAX_FREQ)
 #error "EC too slow for light sensor"
 #endif
@@ -50,7 +50,7 @@ enum opt3001_mode {
 int opt3001_init(void);
 int opt3001_read_lux(int *lux, int af);
 #else
-#define OPT3001_GET_DATA(_s)	((struct opt3001_drv_data_t *)(_s)->drv_data)
+#define OPT3001_GET_DATA(_s) ((struct opt3001_drv_data_t *)(_s)->drv_data)
 
 struct opt3001_drv_data_t {
 	int rate;
@@ -68,4 +68,4 @@ extern const struct accelgyro_drv opt3001_drv;
 extern struct i2c_stress_test_dev opt3001_i2c_stress_test_dev;
 #endif
 
-#endif	/* __CROS_EC_ALS_OPT3001_H */
+#endif /* __CROS_EC_ALS_OPT3001_H */
diff --git a/driver/als_si114x.c b/driver/als_si114x.c
index 28b8364609..3355fd0bd1 100644
--- a/driver/als_si114x.c
+++ b/driver/als_si114x.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -24,8 +24,8 @@
 #endif
 
 #define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args)
 
 static int init(struct motion_sensor_t *s);
 
@@ -57,10 +57,8 @@ static inline int raw_read16(const int port, const uint16_t i2c_addr_flags,
 }
 
 /* helper function to operate on parameter values: op can be query/set/or/and */
-static int si114x_param_op(const struct motion_sensor_t *s,
-			   uint8_t op,
-			   uint8_t param,
-			   int *value)
+static int si114x_param_op(const struct motion_sensor_t *s, uint8_t op,
+			   uint8_t param, int *value)
 {
 	int ret;
 
@@ -73,13 +71,12 @@ static int si114x_param_op(const struct motion_sensor_t *s,
 			goto error;
 	}
 
-	ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-			 SI114X_COMMAND, op | (param & 0x1F));
+	ret = raw_write8(s->port, s->i2c_spi_addr_flags, SI114X_COMMAND,
+			 op | (param & 0x1F));
 	if (ret != EC_SUCCESS)
 		goto error;
 
-	ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-			SI114X_PARAM_RD, value);
+	ret = raw_read8(s->port, s->i2c_spi_addr_flags, SI114X_PARAM_RD, value);
 	if (ret != EC_SUCCESS)
 		goto error;
 
@@ -101,8 +98,7 @@ static int si114x_read_results(struct motion_sensor_t *s, int nb)
 	/* Read ALX result */
 	for (i = 0; i < nb; i++) {
 		ret = raw_read16(s->port, s->i2c_spi_addr_flags,
-				 type_data->base_data_reg + i * 2,
-				 &val);
+				 type_data->base_data_reg + i * 2, &val);
 		if (ret)
 			break;
 		if (val == SI114X_OVERFLOW) {
@@ -122,8 +118,7 @@ static int si114x_read_results(struct motion_sensor_t *s, int nb)
 		 */
 		if (s->type == MOTIONSENSE_TYPE_PROX)
 			val = BIT(16) / val;
-		val = val * type_data->scale +
-			val * type_data->uscale / 10000;
+		val = val * type_data->scale + val * type_data->uscale / 10000;
 		s->raw_xyz[i] = val;
 	}
 
@@ -184,8 +179,8 @@ static int irq_handler(struct motion_sensor_t *s, uint32_t *event)
 	if (!(*event & CONFIG_ALS_SI114X_INT_EVENT))
 		return EC_ERROR_NOT_HANDLED;
 
-	ret = raw_read8(s->port, s->i2c_spi_addr_flags,
-			SI114X_IRQ_STATUS, &val);
+	ret = raw_read8(s->port, s->i2c_spi_addr_flags, SI114X_IRQ_STATUS,
+			&val);
 	if (ret)
 		return ret;
 
@@ -193,8 +188,7 @@ static int irq_handler(struct motion_sensor_t *s, uint32_t *event)
 		return EC_ERROR_INVAL;
 
 	/* clearing IRQ */
-	ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-			 SI114X_IRQ_STATUS,
+	ret = raw_write8(s->port, s->i2c_spi_addr_flags, SI114X_IRQ_STATUS,
 			 val & type_data->irq_flags);
 	if (ret != EC_SUCCESS)
 		CPRINTS("clearing irq failed");
@@ -274,8 +268,8 @@ static int read(const struct motion_sensor_t *s, intv3_t v)
 			CPRINTS("Invalid sensor type");
 			return EC_ERROR_INVAL;
 		}
-		ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-				 SI114X_COMMAND, cmd);
+		ret = raw_write8(s->port, s->i2c_spi_addr_flags, SI114X_COMMAND,
+				 cmd);
 #ifdef CONFIG_ALS_SI114X_POLLING
 		hook_call_deferred(&si114x_read_deferred_data,
 				   SI114x_POLLING_DELAY);
@@ -330,8 +324,8 @@ static int si114x_set_chlist(const struct motion_sensor_t *s)
 		break;
 	}
 
-	return si114x_param_op(s, SI114X_COMMAND_PARAM_SET,
-			SI114X_PARAM_CHLIST, &reg);
+	return si114x_param_op(s, SI114X_COMMAND_PARAM_SET, SI114X_PARAM_CHLIST,
+			       &reg);
 }
 
 #ifdef CONFIG_ALS_SI114X_CHECK_REVISION
@@ -363,58 +357,53 @@ static int si114x_initialize(const struct motion_sensor_t *s)
 	int ret, val;
 
 	/* send reset command */
-	ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-			 SI114X_COMMAND, SI114X_COMMAND_RESET);
+	ret = raw_write8(s->port, s->i2c_spi_addr_flags, SI114X_COMMAND,
+			 SI114X_COMMAND_RESET);
 	if (ret != EC_SUCCESS)
 		return ret;
 	msleep(20);
 
 	/* hardware key, magic value */
-	ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-			 SI114X_HW_KEY, SI114X_HW_KEY_VALUE);
+	ret = raw_write8(s->port, s->i2c_spi_addr_flags, SI114X_HW_KEY,
+			 SI114X_HW_KEY_VALUE);
 	if (ret != EC_SUCCESS)
 		return ret;
 	msleep(20);
 
 	/* interrupt configuration, interrupt output enable */
-	ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-			 SI114X_INT_CFG, SI114X_INT_CFG_INT_OE);
+	ret = raw_write8(s->port, s->i2c_spi_addr_flags, SI114X_INT_CFG,
+			 SI114X_INT_CFG_INT_OE);
 	if (ret != EC_SUCCESS)
 		return ret;
 
 	/* enable interrupt for certain activities */
-	ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-			 SI114X_IRQ_ENABLE,
-			 SI114X_IRQ_ENABLE_PS3_IE |
-			 SI114X_IRQ_ENABLE_PS2_IE |
-			 SI114X_IRQ_ENABLE_PS1_IE |
-			 SI114X_IRQ_ENABLE_ALS_IE_INT0);
+	ret = raw_write8(s->port, s->i2c_spi_addr_flags, SI114X_IRQ_ENABLE,
+			 SI114X_IRQ_ENABLE_PS3_IE | SI114X_IRQ_ENABLE_PS2_IE |
+				 SI114X_IRQ_ENABLE_PS1_IE |
+				 SI114X_IRQ_ENABLE_ALS_IE_INT0);
 	if (ret != EC_SUCCESS)
 		return ret;
 
 	/* Only forced mode */
-	ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-			 SI114X_MEAS_RATE, 0);
+	ret = raw_write8(s->port, s->i2c_spi_addr_flags, SI114X_MEAS_RATE, 0);
 	if (ret != EC_SUCCESS)
 		return ret;
 
 	/* measure ALS every time device wakes up */
-	ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-			 SI114X_ALS_RATE, 0);
+	ret = raw_write8(s->port, s->i2c_spi_addr_flags, SI114X_ALS_RATE, 0);
 	if (ret != EC_SUCCESS)
 		return ret;
 
 	/* measure proximity every time device wakes up */
-	ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-			 SI114X_PS_RATE, 0);
+	ret = raw_write8(s->port, s->i2c_spi_addr_flags, SI114X_PS_RATE, 0);
 	if (ret != EC_SUCCESS)
 		return ret;
 
 	/* set LED currents to maximum */
 	switch (SI114X_NUM_LEDS) {
 	case 3:
-		ret = raw_write8(s->port, s->i2c_spi_addr_flags,
-				 SI114X_PS_LED3, 0x0f);
+		ret = raw_write8(s->port, s->i2c_spi_addr_flags, SI114X_PS_LED3,
+				 0x0f);
 		if (ret != EC_SUCCESS)
 			return ret;
 		ret = raw_write8(s->port, s->i2c_spi_addr_flags,
@@ -444,9 +433,7 @@ static int si114x_initialize(const struct motion_sensor_t *s)
 	return ret;
 }
 
-static int set_resolution(const struct motion_sensor_t *s,
-				int res,
-				int rnd)
+static int set_resolution(const struct motion_sensor_t *s, int res, int rnd)
 {
 	int ret, reg1, reg2, val;
 	/* override on resolution: set the gain. between 0 to 7 */
@@ -489,9 +476,7 @@ static int get_resolution(const struct motion_sensor_t *s)
 	return val & 0x07;
 }
 
-static int set_range(struct motion_sensor_t *s,
-				int range,
-				int rnd)
+static int set_range(struct motion_sensor_t *s, int range, int rnd)
 {
 	struct si114x_typed_data_t *data = SI114X_GET_TYPED_DATA(s);
 	data->scale = range >> 16;
@@ -507,27 +492,23 @@ static int get_data_rate(const struct motion_sensor_t *s)
 	return data->rate;
 }
 
-static int set_data_rate(const struct motion_sensor_t *s,
-				int rate,
-				int rnd)
+static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
 {
 	struct si114x_typed_data_t *data = SI114X_GET_TYPED_DATA(s);
 	data->rate = rate;
 	return EC_SUCCESS;
 }
 
-static int set_offset(const struct motion_sensor_t *s,
-			const int16_t *offset,
-			int16_t    temp)
+static int set_offset(const struct motion_sensor_t *s, const int16_t *offset,
+		      int16_t temp)
 {
 	struct si114x_typed_data_t *data = SI114X_GET_TYPED_DATA(s);
 	data->offset = offset[X];
 	return EC_SUCCESS;
 }
 
-static int get_offset(const struct motion_sensor_t *s,
-			int16_t   *offset,
-			int16_t    *temp)
+static int get_offset(const struct motion_sensor_t *s, int16_t *offset,
+		      int16_t *temp)
 {
 	struct si114x_typed_data_t *data = SI114X_GET_TYPED_DATA(s);
 	offset[X] = data->offset;
diff --git a/driver/als_si114x.h b/driver/als_si114x.h
index 2084c55f09..57ef6f8021 100644
--- a/driver/als_si114x.h
+++ b/driver/als_si114x.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,75 +8,75 @@
 #ifndef __CROS_EC_ALS_SI114X_H
 #define __CROS_EC_ALS_SI114X_H
 
-#define SI114X_ADDR_FLAGS               0x5a
+#define SI114X_ADDR_FLAGS 0x5a
 
-#define SI114X_PART_ID		0x00
-#define SI114X_SEQ_ID		0x02
+#define SI114X_PART_ID 0x00
+#define SI114X_SEQ_ID 0x02
 
-#define SI114X_INT_CFG		0x03
-#define SI114X_INT_CFG_INT_OE		BIT(0)
+#define SI114X_INT_CFG 0x03
+#define SI114X_INT_CFG_INT_OE BIT(0)
 
-#define SI114X_IRQ_ENABLE	0x04
-#define SI114X_IRQ_ENABLE_PS3_IE	BIT(4)
-#define SI114X_IRQ_ENABLE_PS2_IE	BIT(3)
-#define SI114X_IRQ_ENABLE_PS1_IE	BIT(2)
-#define SI114X_IRQ_ENABLE_ALS_IE_INT1	BIT(1)
-#define SI114X_IRQ_ENABLE_ALS_IE_INT0	BIT(0)
+#define SI114X_IRQ_ENABLE 0x04
+#define SI114X_IRQ_ENABLE_PS3_IE BIT(4)
+#define SI114X_IRQ_ENABLE_PS2_IE BIT(3)
+#define SI114X_IRQ_ENABLE_PS1_IE BIT(2)
+#define SI114X_IRQ_ENABLE_ALS_IE_INT1 BIT(1)
+#define SI114X_IRQ_ENABLE_ALS_IE_INT0 BIT(0)
 
-#define SI114X_HW_KEY		0x07
-#define SI114X_HW_KEY_VALUE		0x17
+#define SI114X_HW_KEY 0x07
+#define SI114X_HW_KEY_VALUE 0x17
 
-#define SI114X_MEAS_RATE	0x08
-#define SI114X_ALS_RATE		0x09
-#define SI114X_PS_RATE		0x0A
+#define SI114X_MEAS_RATE 0x08
+#define SI114X_ALS_RATE 0x09
+#define SI114X_PS_RATE 0x0A
 
-#define SI114X_PS_LED21		0x0F
-#define SI114X_PS_LED3		0x10
-#define SI114X_NUM_LEDS  (CONFIG_ALS_SI114X - 0x40)
+#define SI114X_PS_LED21 0x0F
+#define SI114X_PS_LED3 0x10
+#define SI114X_NUM_LEDS (CONFIG_ALS_SI114X - 0x40)
 
-#define SI114X_PARAM_WR		0x17
-#define SI114X_COMMAND		0x18
+#define SI114X_PARAM_WR 0x17
+#define SI114X_COMMAND 0x18
 
-#define SI114X_COMMAND_PARAM_QUERY	0x80
-#define SI114X_COMMAND_PARAM_SET	0xA0
-#define SI114X_PARAM_CHLIST			0x01
-#define SI114X_PARAM_CHLIST_EN_ALS_VIS			BIT(4)
-#define SI114X_PARAM_CHLIST_EN_PS3			BIT(2)
-#define SI114X_PARAM_CHLIST_EN_PS2			BIT(1)
-#define SI114X_PARAM_CHLIST_EN_PS1			BIT(0)
-#define SI114X_PARAM_PS_ADC_COUNTER		0x0A
-#define SI114X_PARAM_PS_ADC_GAIN		0x0B
-#define SI114X_PARAM_PS_ADC_MISC		0x0C
-#define SI114X_PARAM_PS_ADC_MISC_MODE			BIT(2)
-#define SI114X_PARAM_PS_ADC_MISC_MODE_NORMAL_PROXIMITY	BIT(2)
-#define SI114X_PARAM_ALS_VIS_ADC_COUNTER	0x10
-#define SI114X_PARAM_ALS_VIS_ADC_GAIN		0x11
-#define SI114X_PARAM_ALS_VIS_ADC_MISC		0x12
+#define SI114X_COMMAND_PARAM_QUERY 0x80
+#define SI114X_COMMAND_PARAM_SET 0xA0
+#define SI114X_PARAM_CHLIST 0x01
+#define SI114X_PARAM_CHLIST_EN_ALS_VIS BIT(4)
+#define SI114X_PARAM_CHLIST_EN_PS3 BIT(2)
+#define SI114X_PARAM_CHLIST_EN_PS2 BIT(1)
+#define SI114X_PARAM_CHLIST_EN_PS1 BIT(0)
+#define SI114X_PARAM_PS_ADC_COUNTER 0x0A
+#define SI114X_PARAM_PS_ADC_GAIN 0x0B
+#define SI114X_PARAM_PS_ADC_MISC 0x0C
+#define SI114X_PARAM_PS_ADC_MISC_MODE BIT(2)
+#define SI114X_PARAM_PS_ADC_MISC_MODE_NORMAL_PROXIMITY BIT(2)
+#define SI114X_PARAM_ALS_VIS_ADC_COUNTER 0x10
+#define SI114X_PARAM_ALS_VIS_ADC_GAIN 0x11
+#define SI114X_PARAM_ALS_VIS_ADC_MISC 0x12
 
-#define SI114X_COMMAND_RESET		0x01
-#define SI114X_COMMAND_PS_FORCE		0x05
-#define SI114X_COMMAND_ALS_FORCE	0x06
+#define SI114X_COMMAND_RESET 0x01
+#define SI114X_COMMAND_PS_FORCE 0x05
+#define SI114X_COMMAND_ALS_FORCE 0x06
 
-#define SI114X_IRQ_STATUS	0x21
-#define SI114X_ALS_VIS_DATA0	0x22
+#define SI114X_IRQ_STATUS 0x21
+#define SI114X_ALS_VIS_DATA0 0x22
 
-#define SI114X_PARAM_RD		0x2E
+#define SI114X_PARAM_RD 0x2E
 
 /* Proximity sensor finds an object within 5 cm, disable light sensor */
-#define SI114X_COVERED_THRESHOLD        5
-#define SI114X_OVERFLOW                 0xffff
+#define SI114X_COVERED_THRESHOLD 5
+#define SI114X_OVERFLOW 0xffff
 
 /* Time to wait before re-initializing the device if access is denied */
-#define SI114X_DENIED_THRESHOLD		(10 * SECOND)
+#define SI114X_DENIED_THRESHOLD (10 * SECOND)
 
 /* Delay used for deferred callback when polling is enabled */
 #define SI114x_POLLING_DELAY (8 * MSEC)
 
 /* Min and Max sampling frequency in mHz */
-#define SI114X_PROX_MIN_FREQ            504
-#define SI114X_PROX_MAX_FREQ            50000
-#define SI114X_LIGHT_MIN_FREQ           504
-#define SI114X_LIGHT_MAX_FREQ           50000
+#define SI114X_PROX_MIN_FREQ 504
+#define SI114X_PROX_MAX_FREQ 50000
+#define SI114X_LIGHT_MIN_FREQ 504
+#define SI114X_LIGHT_MAX_FREQ 50000
 #if (CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ <= SI114X_PROX_MAX_FREQ)
 #error "EC too slow for light sensor"
 #endif
@@ -109,12 +109,11 @@ struct si114x_drv_data_t {
 	struct si114x_typed_data_t type_data[2];
 };
 
-#define SI114X_GET_DATA(_s) \
-	((struct si114x_drv_data_t *)(_s)->drv_data)
+#define SI114X_GET_DATA(_s) ((struct si114x_drv_data_t *)(_s)->drv_data)
 
 #define SI114X_GET_TYPED_DATA(_s) \
 	(&SI114X_GET_DATA(_s)->type_data[(_s)->type - MOTIONSENSE_TYPE_PROX])
 
 void si114x_interrupt(enum gpio_signal signal);
 
-#endif	/* __CROS_EC_ALS_SI114X_H */
+#endif /* __CROS_EC_ALS_SI114X_H */
diff --git a/driver/als_tcs3400.c b/driver/als_tcs3400.c
index 4e1fdb9d4f..002e269ada 100644
--- a/driver/als_tcs3400.c
+++ b/driver/als_tcs3400.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -20,7 +20,7 @@
 #define ALS_TCS3400_INT_ENABLE
 #endif
 
-#define CPRINTS(fmt, args...) cprints(CC_ACCEL, "%s "fmt, __func__, ## args)
+#define CPRINTS(fmt, args...) cprints(CC_ACCEL, "%s " fmt, __func__, ##args)
 
 volatile uint32_t last_interrupt_timestamp;
 
@@ -32,32 +32,34 @@ volatile uint32_t last_interrupt_timestamp;
  * Values in array are TCS_ATIME_GAIN_FACTOR (100x) times actual value to allow
  * for fractions using integers.
  */
-static const uint16_t
-range_atime[TCS_MAX_AGAIN - TCS_MIN_AGAIN + 1][TCS_MAX_ATIME_RANGES] = {
-{11200, 5600, 5600, 7200, 5500, 4500, 3800, 3800, 3300, 2900, 2575, 2275, 2075},
-{11200, 5100, 2700, 1840, 1400, 1133, 981, 963, 833, 728, 650, 577, 525},
-{250, 1225, 643, 441, 337, 276, 253, 235, 203, 176, 150, 0, 0},
-{790, 261, 163, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} };
+static const uint16_t range_atime[TCS_MAX_AGAIN - TCS_MIN_AGAIN +
+				  1][TCS_MAX_ATIME_RANGES] = {
+	{ 11200, 5600, 5600, 7200, 5500, 4500, 3800, 3800, 3300, 2900, 2575,
+	  2275, 2075 },
+	{ 11200, 5100, 2700, 1840, 1400, 1133, 981, 963, 833, 728, 650, 577,
+	  525 },
+	{ 250, 1225, 643, 441, 337, 276, 253, 235, 203, 176, 150, 0, 0 },
+	{ 790, 261, 163, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+};
 
-static void
-decrement_atime(struct tcs_saturation_t *sat_p, uint16_t cur_lux, int percent)
+static void decrement_atime(struct tcs_saturation_t *sat_p, uint16_t cur_lux,
+			    int percent)
 {
 	int atime;
 	uint16_t steps;
 	int lux = MIN(cur_lux, TCS_GAIN_TABLE_MAX_LUX);
 
 	steps = percent * range_atime[sat_p->again][lux / 1000] /
-			TCS_ATIME_GAIN_FACTOR;
+		TCS_ATIME_GAIN_FACTOR;
 	atime = MAX(sat_p->atime - steps, TCS_MIN_ATIME);
 	sat_p->atime = MIN(atime, TCS_MAX_ATIME);
 }
 
 #else
 
-static void
-decrement_atime(struct tcs_saturation_t *sat_p,
-		uint16_t __attribute__((unused)) cur_lux,
-		int __attribute__((unused)) percent)
+static void decrement_atime(struct tcs_saturation_t *sat_p,
+			    uint16_t __attribute__((unused)) cur_lux,
+			    int __attribute__((unused)) percent)
 {
 	sat_p->atime = MAX(sat_p->atime - TCS_ATIME_DEC_STEP, TCS_MIN_ATIME);
 }
@@ -69,14 +71,14 @@ static void increment_atime(struct tcs_saturation_t *sat_p)
 	sat_p->atime = MIN(sat_p->atime + TCS_ATIME_INC_STEP, TCS_MAX_ATIME);
 }
 
-static inline int tcs3400_i2c_read8(const struct motion_sensor_t *s,
-				    int reg, int *data)
+static inline int tcs3400_i2c_read8(const struct motion_sensor_t *s, int reg,
+				    int *data)
 {
 	return i2c_read8(s->port, s->i2c_spi_addr_flags, reg, data);
 }
 
-static inline int tcs3400_i2c_write8(const struct motion_sensor_t *s,
-				     int reg, int data)
+static inline int tcs3400_i2c_write8(const struct motion_sensor_t *s, int reg,
+				     int data)
 {
 	return i2c_write8(s->port, s->i2c_spi_addr_flags, reg, data);
 }
@@ -107,12 +109,12 @@ static int tcs3400_read(const struct motion_sensor_t *s, intv3_t v)
 	int ret;
 
 	/* Chip may have been off, make sure to setup important registers */
-	if (TCS3400_RGB_DRV_DATA(s+1)->calibration_mode) {
+	if (TCS3400_RGB_DRV_DATA(s + 1)->calibration_mode) {
 		atime = TCS_CALIBRATION_ATIME;
 		again = TCS_CALIBRATION_AGAIN;
 	} else {
-		atime = TCS3400_RGB_DRV_DATA(s+1)->saturation.atime;
-		again = TCS3400_RGB_DRV_DATA(s+1)->saturation.again;
+		atime = TCS3400_RGB_DRV_DATA(s + 1)->saturation.atime;
+		again = TCS3400_RGB_DRV_DATA(s + 1)->saturation.again;
 	}
 	ret = tcs3400_i2c_write8(s, TCS_I2C_ATIME, atime);
 	if (ret)
@@ -159,17 +161,16 @@ static int tcs3400_rgb_read(const struct motion_sensor_t *s, intv3_t v)
  * AGAIN if it is not already at its maximum, or if it is, decrease
  * ATIME if it is not at it's minimum already.
  */
-static int
-tcs3400_adjust_sensor_for_saturation(struct motion_sensor_t *s,
-				     uint16_t cur_lux,
-				     uint16_t *crgb_data,
-				     uint32_t status)
+static int tcs3400_adjust_sensor_for_saturation(struct motion_sensor_t *s,
+						uint16_t cur_lux,
+						uint16_t *crgb_data,
+						uint32_t status)
 {
 	struct tcs_saturation_t *sat_p =
-			&TCS3400_RGB_DRV_DATA(s+1)->saturation;
+		&TCS3400_RGB_DRV_DATA(s + 1)->saturation;
 	const uint8_t save_again = sat_p->again;
 	const uint8_t save_atime = sat_p->atime;
-	uint16_t max_val =  0;
+	uint16_t max_val = 0;
 	int ret;
 	int percent_left = 0;
 
@@ -182,7 +183,7 @@ tcs3400_adjust_sensor_for_saturation(struct motion_sensor_t *s,
 
 	/* Don't process if status isn't valid yet */
 	if ((status & TCS_I2C_STATUS_ALS_SATURATED) ||
-			(max_val >= TCS_SATURATION_LEVEL)) {
+	    (max_val >= TCS_SATURATION_LEVEL)) {
 		/* Saturation occurred, decrease AGAIN if we can */
 		if (sat_p->again > TCS_MIN_AGAIN)
 			sat_p->again--;
@@ -199,14 +200,15 @@ tcs3400_adjust_sensor_for_saturation(struct motion_sensor_t *s,
 				 * increase accumulation time by decrementing
 				 * ATIME register
 				 */
-				percent_left = TSC_SATURATION_LOW_BAND_PERCENT -
+				percent_left =
+					TSC_SATURATION_LOW_BAND_PERCENT -
 					(max_val * 100 / TCS_SATURATION_LEVEL);
 				decrement_atime(sat_p, cur_lux, percent_left);
 			}
 		} else if (sat_p->atime > TCS_MIN_ATIME) {
 			/* calculate percentage between current and desired */
 			percent_left = TSC_SATURATION_LOW_BAND_PERCENT -
-				(max_val * 100 / TCS_SATURATION_LEVEL);
+				       (max_val * 100 / TCS_SATURATION_LEVEL);
 
 			/* increase accumulation time by decrementing ATIME */
 			decrement_atime(sat_p, cur_lux, percent_left);
@@ -233,7 +235,7 @@ tcs3400_adjust_sensor_for_saturation(struct motion_sensor_t *s,
 	/* If atime or gain setting changed, update atime and gain registers */
 	if (save_again != sat_p->again) {
 		ret = tcs3400_i2c_write8(s, TCS_I2C_CONTROL,
-				(sat_p->again & TCS_I2C_CONTROL_MASK));
+					 (sat_p->again & TCS_I2C_CONTROL_MASK));
 		if (ret)
 			return ret;
 	}
@@ -252,24 +254,25 @@ tcs3400_adjust_sensor_for_saturation(struct motion_sensor_t *s,
  * different atime and again settings from the sample.
  */
 static uint32_t normalize_channel_data(struct motion_sensor_t *s,
-					uint32_t  sample)
+				       uint32_t sample)
 {
 	struct tcs_saturation_t *sat_p =
-				&(TCS3400_RGB_DRV_DATA(s+1)->saturation);
+		&(TCS3400_RGB_DRV_DATA(s + 1)->saturation);
 	const uint16_t cur_gain = (1 << (2 * sat_p->again));
 	const uint16_t cal_again = (1 << (2 * TCS_CALIBRATION_AGAIN));
 
-	return DIV_ROUND_NEAREST(sample * (TCS_ATIME_GRANULARITY -
-				TCS_CALIBRATION_ATIME) * cal_again,
-				(TCS_ATIME_GRANULARITY - sat_p->atime) *
-				cur_gain);
+	return DIV_ROUND_NEAREST(
+		sample * (TCS_ATIME_GRANULARITY - TCS_CALIBRATION_ATIME) *
+			cal_again,
+		(TCS_ATIME_GRANULARITY - sat_p->atime) * cur_gain);
 }
 
-
 __overridable void tcs3400_translate_to_xyz(struct motion_sensor_t *s,
-				     int32_t *crgb_data, int32_t *xyz_data)
+					    int32_t *crgb_data,
+					    int32_t *xyz_data)
 {
-	struct tcs3400_rgb_drv_data_t *rgb_drv_data = TCS3400_RGB_DRV_DATA(s+1);
+	struct tcs3400_rgb_drv_data_t *rgb_drv_data =
+		TCS3400_RGB_DRV_DATA(s + 1);
 	int32_t crgb_prime[CRGB_COUNT];
 	int32_t ir;
 	int i;
@@ -280,8 +283,9 @@ __overridable void tcs3400_translate_to_xyz(struct motion_sensor_t *s,
 
 	/* IR removal */
 	ir = FP_TO_INT(fp_mul(INT_TO_FP(crgb_data[1] + crgb_data[2] +
-			      crgb_data[3] - crgb_data[0]),
-			      rgb_drv_data->calibration.irt) / 2);
+					crgb_data[3] - crgb_data[0]),
+			      rgb_drv_data->calibration.irt) /
+		       2);
 
 	for (i = 0; i < ARRAY_SIZE(crgb_prime); i++) {
 		if (crgb_data[i] < ir)
@@ -297,17 +301,17 @@ __overridable void tcs3400_translate_to_xyz(struct motion_sensor_t *s,
 	/* regression fit to XYZ space */
 	for (i = 0; i < 3; i++) {
 		const struct rgb_channel_calibration_t *p =
-				&rgb_drv_data->calibration.rgb_cal[i];
-
-		xyz_data[i] = p->offset + FP_TO_INT(
-			(fp_inter_t)p->coeff[RED_CRGB_IDX] *
-					crgb_prime[RED_CRGB_IDX] +
-			(fp_inter_t)p->coeff[GREEN_CRGB_IDX] *
-					crgb_prime[GREEN_CRGB_IDX] +
-			(fp_inter_t)p->coeff[BLUE_CRGB_IDX] *
-					crgb_prime[BLUE_CRGB_IDX] +
-			(fp_inter_t)p->coeff[CLEAR_CRGB_IDX] *
-					crgb_prime[CLEAR_CRGB_IDX]);
+			&rgb_drv_data->calibration.rgb_cal[i];
+
+		xyz_data[i] = p->offset +
+			      FP_TO_INT((fp_inter_t)p->coeff[RED_CRGB_IDX] *
+						crgb_prime[RED_CRGB_IDX] +
+					(fp_inter_t)p->coeff[GREEN_CRGB_IDX] *
+						crgb_prime[GREEN_CRGB_IDX] +
+					(fp_inter_t)p->coeff[BLUE_CRGB_IDX] *
+						crgb_prime[BLUE_CRGB_IDX] +
+					(fp_inter_t)p->coeff[CLEAR_CRGB_IDX] *
+						crgb_prime[CLEAR_CRGB_IDX]);
 
 		if (xyz_data[i] < 0)
 			xyz_data[i] = 0;
@@ -315,14 +319,16 @@ __overridable void tcs3400_translate_to_xyz(struct motion_sensor_t *s,
 }
 
 static void tcs3400_process_raw_data(struct motion_sensor_t *s,
-				    uint8_t *raw_data_buf,
-				    uint16_t *raw_light_data, int32_t *xyz_data)
+				     uint8_t *raw_data_buf,
+				     uint16_t *raw_light_data,
+				     int32_t *xyz_data)
 {
 	struct als_drv_data_t *als_drv_data = TCS3400_DRV_DATA(s);
-	struct tcs3400_rgb_drv_data_t *rgb_drv_data = TCS3400_RGB_DRV_DATA(s+1);
+	struct tcs3400_rgb_drv_data_t *rgb_drv_data =
+		TCS3400_RGB_DRV_DATA(s + 1);
 	const uint8_t calibration_mode = rgb_drv_data->calibration_mode;
-	uint16_t  k_channel_scale =
-			als_drv_data->als_cal.channel_scale.k_channel_scale;
+	uint16_t k_channel_scale =
+		als_drv_data->als_cal.channel_scale.k_channel_scale;
 	uint16_t cover_scale = als_drv_data->als_cal.channel_scale.cover_scale;
 	int32_t crgb_data[CRGB_COUNT];
 	int i;
@@ -333,7 +339,7 @@ static void tcs3400_process_raw_data(struct motion_sensor_t *s,
 
 		/* assemble the light value for this channel */
 		crgb_data[i] = raw_light_data[i] =
-			((raw_data_buf[index+1] << 8) | raw_data_buf[index]);
+			((raw_data_buf[index + 1] << 8) | raw_data_buf[index]);
 
 		/* in calibration mode, we only assemble the raw data */
 		if (calibration_mode)
@@ -342,14 +348,14 @@ static void tcs3400_process_raw_data(struct motion_sensor_t *s,
 		/* rgb data at index 1, 2, and 3 owned by rgb driver, not ALS */
 		if (i > 0) {
 			struct als_channel_scale_t *csp =
-				&rgb_drv_data->calibration.rgb_cal[i-1].scale;
+				&rgb_drv_data->calibration.rgb_cal[i - 1].scale;
 			k_channel_scale = csp->k_channel_scale;
 			cover_scale = csp->cover_scale;
 		}
 
 		/* Step 1: divide by individual channel scale value */
-		crgb_data[i] = SENSOR_APPLY_DIV_SCALE(crgb_data[i],
-							k_channel_scale);
+		crgb_data[i] =
+			SENSOR_APPLY_DIV_SCALE(crgb_data[i], k_channel_scale);
 
 		/* compensate for the light cover */
 		crgb_data[i] = SENSOR_APPLY_SCALE(crgb_data[i], cover_scale);
@@ -365,7 +371,7 @@ static void tcs3400_process_raw_data(struct motion_sensor_t *s,
 
 		/* calibration mode returns raw data */
 		for (i = 0; i < 3; i++)
-			xyz_data[i] = crgb_data[i+1];
+			xyz_data[i] = crgb_data[i + 1];
 	}
 }
 
@@ -373,7 +379,7 @@ static int32_t get_lux_from_xyz(struct motion_sensor_t *s, int32_t *xyz_data)
 {
 	int32_t lux = xyz_data[Y];
 	const int32_t offset =
-		TCS3400_RGB_DRV_DATA(s+1)->calibration.rgb_cal[Y].offset;
+		TCS3400_RGB_DRV_DATA(s + 1)->calibration.rgb_cal[Y].offset;
 
 	/*
 	 * Do not include the offset when determining LUX from XYZ.
@@ -389,8 +395,7 @@ static bool is_spoof(struct motion_sensor_t *s)
 	       (s->flags & MOTIONSENSE_FLAG_IN_SPOOF_MODE);
 }
 
-static int tcs3400_post_events(struct motion_sensor_t *s,
-			       uint32_t last_ts,
+static int tcs3400_post_events(struct motion_sensor_t *s, uint32_t last_ts,
 			       uint32_t status)
 {
 	/*
@@ -399,7 +404,7 @@ static int tcs3400_post_events(struct motion_sensor_t *s,
 	 */
 	struct motion_sensor_t *rgb_s = s + 1;
 	const uint8_t is_calibration =
-			TCS3400_RGB_DRV_DATA(rgb_s)->calibration_mode;
+		TCS3400_RGB_DRV_DATA(rgb_s)->calibration_mode;
 	uint8_t buf[TCS_RGBC_DATA_SIZE]; /* holds raw data read from chip */
 	int32_t xyz_data[3] = { 0, 0, 0 };
 	uint16_t raw_data[CRGB_COUNT]; /* holds raw CRGB assembled from buf[] */
@@ -408,7 +413,7 @@ static int tcs3400_post_events(struct motion_sensor_t *s,
 	int ret;
 
 	if (IS_ENABLED(CONFIG_ALS_TCS3400_EMULATED_IRQ_EVENT)) {
-		int i = 5;	/* 100ms max */
+		int i = 5; /* 100ms max */
 
 		while (i--) {
 			/* Make sure data is valid */
@@ -431,8 +436,7 @@ static int tcs3400_post_events(struct motion_sensor_t *s,
 
 	/* Read the light registers */
 	ret = i2c_read_block(s->port, s->i2c_spi_addr_flags,
-			TCS_DATA_START_LOCATION,
-			buf, sizeof(buf));
+			     TCS_DATA_START_LOCATION, buf, sizeof(buf));
 	if (ret)
 		return ret;
 
@@ -450,7 +454,8 @@ static int tcs3400_post_events(struct motion_sensor_t *s,
 		if (is_spoof(s))
 			last_v[X] = s->spoof_xyz[X];
 		else
-			last_v[X] = is_calibration ? raw_data[CLEAR_CRGB_IDX] : lux;
+			last_v[X] = is_calibration ? raw_data[CLEAR_CRGB_IDX] :
+						     lux;
 
 		if (IS_ENABLED(CONFIG_ACCEL_FIFO)) {
 			struct ec_response_motion_sensor_data vector = {
@@ -475,12 +480,13 @@ static int tcs3400_post_events(struct motion_sensor_t *s,
 	last_v = rgb_s->raw_xyz;
 	if (is_calibration ||
 	    (((last_v[X] != xyz_data[X]) || (last_v[Y] != xyz_data[Y]) ||
-	     (last_v[Z] != xyz_data[Z])) &&
+	      (last_v[Z] != xyz_data[Z])) &&
 	     ((raw_data[RED_CRGB_IDX] != TCS_SATURATION_LEVEL) &&
 	      (raw_data[BLUE_CRGB_IDX] != TCS_SATURATION_LEVEL) &&
 	      (raw_data[GREEN_CRGB_IDX] != TCS_SATURATION_LEVEL)))) {
 		if (is_spoof(rgb_s)) {
-			memcpy(last_v, rgb_s->spoof_xyz, sizeof(rgb_s->spoof_xyz));
+			memcpy(last_v, rgb_s->spoof_xyz,
+			       sizeof(rgb_s->spoof_xyz));
 		} else if (is_calibration) {
 			last_v[0] = raw_data[RED_CRGB_IDX];
 			last_v[1] = raw_data[GREEN_CRGB_IDX];
@@ -498,7 +504,8 @@ static int tcs3400_post_events(struct motion_sensor_t *s,
 			ec_motion_sensor_clamp_u16s(udata, last_v);
 
 			vector.sensor_num = rgb_s - motion_sensors;
-			motion_sense_fifo_stage_data(&vector, rgb_s, 3, last_ts);
+			motion_sense_fifo_stage_data(&vector, rgb_s, 3,
+						     last_ts);
 		} else {
 			motion_sense_push_raw_xyz(rgb_s);
 		}
@@ -558,11 +565,10 @@ static int tcs3400_irq_handler(struct motion_sensor_t *s, uint32_t *event)
 }
 
 static int tcs3400_rgb_get_scale(const struct motion_sensor_t *s,
-				 uint16_t *scale,
-				 int16_t *temp)
+				 uint16_t *scale, int16_t *temp)
 {
 	struct rgb_channel_calibration_t *rgb_cal =
-			TCS3400_RGB_DRV_DATA(s)->calibration.rgb_cal;
+		TCS3400_RGB_DRV_DATA(s)->calibration.rgb_cal;
 
 	scale[X] = rgb_cal[RED_RGB_IDX].scale.k_channel_scale;
 	scale[Y] = rgb_cal[GREEN_RGB_IDX].scale.k_channel_scale;
@@ -572,11 +578,10 @@ static int tcs3400_rgb_get_scale(const struct motion_sensor_t *s,
 }
 
 static int tcs3400_rgb_set_scale(const struct motion_sensor_t *s,
-				 const uint16_t *scale,
-				 int16_t temp)
+				 const uint16_t *scale, int16_t temp)
 {
 	struct rgb_channel_calibration_t *rgb_cal =
-			TCS3400_RGB_DRV_DATA(s)->calibration.rgb_cal;
+		TCS3400_RGB_DRV_DATA(s)->calibration.rgb_cal;
 
 	if (scale[X] == 0 || scale[Y] == 0 || scale[Z] == 0)
 		return EC_ERROR_INVAL;
@@ -587,8 +592,7 @@ static int tcs3400_rgb_set_scale(const struct motion_sensor_t *s,
 }
 
 static int tcs3400_rgb_get_offset(const struct motion_sensor_t *s,
-				  int16_t *offset,
-				  int16_t *temp)
+				  int16_t *offset, int16_t *temp)
 {
 	offset[X] = TCS3400_RGB_DRV_DATA(s)->calibration.rgb_cal[X].offset;
 	offset[Y] = TCS3400_RGB_DRV_DATA(s)->calibration.rgb_cal[Y].offset;
@@ -598,15 +602,13 @@ static int tcs3400_rgb_get_offset(const struct motion_sensor_t *s,
 }
 
 static int tcs3400_rgb_set_offset(const struct motion_sensor_t *s,
-				  const int16_t *offset,
-				  int16_t temp)
+				  const int16_t *offset, int16_t temp)
 {
 	/* do not allow offset to be changed, it's predetermined */
 	return EC_SUCCESS;
 }
 
-static int tcs3400_rgb_set_data_rate(const struct motion_sensor_t *s,
-				     int rate,
+static int tcs3400_rgb_set_data_rate(const struct motion_sensor_t *s, int rate,
 				     int rnd)
 {
 	return EC_SUCCESS;
@@ -615,20 +617,16 @@ static int tcs3400_rgb_set_data_rate(const struct motion_sensor_t *s,
 /* Enable/disable special factory calibration mode */
 static int tcs3400_perform_calib(struct motion_sensor_t *s, int enable)
 {
-	TCS3400_RGB_DRV_DATA(s+1)->calibration_mode = enable;
+	TCS3400_RGB_DRV_DATA(s + 1)->calibration_mode = enable;
 	return EC_SUCCESS;
 }
 
-static int tcs3400_rgb_set_range(struct motion_sensor_t *s,
-				 int range,
-				 int rnd)
+static int tcs3400_rgb_set_range(struct motion_sensor_t *s, int range, int rnd)
 {
 	return EC_SUCCESS;
 }
 
-static int tcs3400_set_range(struct motion_sensor_t *s,
-			     int range,
-			     int rnd)
+static int tcs3400_set_range(struct motion_sensor_t *s, int range, int rnd)
 {
 	TCS3400_DRV_DATA(s)->als_cal.scale = range >> 16;
 	TCS3400_DRV_DATA(s)->als_cal.uscale = range & 0xffff;
@@ -636,9 +634,8 @@ static int tcs3400_set_range(struct motion_sensor_t *s,
 	return EC_SUCCESS;
 }
 
-static int tcs3400_get_scale(const struct motion_sensor_t *s,
-				 uint16_t *scale,
-				 int16_t *temp)
+static int tcs3400_get_scale(const struct motion_sensor_t *s, uint16_t *scale,
+			     int16_t *temp)
 {
 	scale[X] = TCS3400_DRV_DATA(s)->als_cal.channel_scale.k_channel_scale;
 	scale[Y] = 0;
@@ -648,8 +645,7 @@ static int tcs3400_get_scale(const struct motion_sensor_t *s,
 }
 
 static int tcs3400_set_scale(const struct motion_sensor_t *s,
-				 const uint16_t *scale,
-				 int16_t temp)
+			     const uint16_t *scale, int16_t temp)
 {
 	if (scale[X] == 0)
 		return EC_ERROR_INVAL;
@@ -657,8 +653,7 @@ static int tcs3400_set_scale(const struct motion_sensor_t *s,
 	return EC_SUCCESS;
 }
 
-static int tcs3400_get_offset(const struct motion_sensor_t *s,
-			      int16_t *offset,
+static int tcs3400_get_offset(const struct motion_sensor_t *s, int16_t *offset,
 			      int16_t *temp)
 {
 	offset[X] = TCS3400_DRV_DATA(s)->als_cal.offset;
@@ -669,8 +664,7 @@ static int tcs3400_get_offset(const struct motion_sensor_t *s,
 }
 
 static int tcs3400_set_offset(const struct motion_sensor_t *s,
-			      const int16_t *offset,
-			      int16_t temp)
+			      const int16_t *offset, int16_t temp)
 {
 	/* do not allow offset to be changed, it's predetermined */
 	return EC_SUCCESS;
@@ -686,8 +680,7 @@ static int tcs3400_rgb_get_data_rate(const struct motion_sensor_t *s)
 	return tcs3400_get_data_rate(s - 1);
 }
 
-static int tcs3400_set_data_rate(const struct motion_sensor_t *s,
-				 int rate,
+static int tcs3400_set_data_rate(const struct motion_sensor_t *s, int rate,
 				 int rnd)
 {
 	enum tcs3400_mode mode;
@@ -737,22 +730,21 @@ static int tcs3400_init(struct motion_sensor_t *s)
 	const struct reg_data {
 		uint8_t reg;
 		uint8_t data;
-	} defaults[] = {
-		{ TCS_I2C_ENABLE, 0 },
-		{ TCS_I2C_ATIME, TCS_DEFAULT_ATIME },
-		{ TCS_I2C_WTIME, 0xFF },
-		{ TCS_I2C_AILTL, 0 },
-		{ TCS_I2C_AILTH, 0 },
-		{ TCS_I2C_AIHTL, 0 },
-		{ TCS_I2C_AIHTH, 0 },
-		{ TCS_I2C_PERS, 0 },
-		{ TCS_I2C_CONFIG, 0x40 },
-		{ TCS_I2C_CONTROL, (TCS_DEFAULT_AGAIN & TCS_I2C_CONTROL_MASK) },
-		{ TCS_I2C_AUX, 0 },
-		{ TCS_I2C_IR, 0 },
-		{ TCS_I2C_CICLEAR, 0 },
-		{ TCS_I2C_AICLEAR, 0 }
-	};
+	} defaults[] = { { TCS_I2C_ENABLE, 0 },
+			 { TCS_I2C_ATIME, TCS_DEFAULT_ATIME },
+			 { TCS_I2C_WTIME, 0xFF },
+			 { TCS_I2C_AILTL, 0 },
+			 { TCS_I2C_AILTH, 0 },
+			 { TCS_I2C_AIHTL, 0 },
+			 { TCS_I2C_AIHTH, 0 },
+			 { TCS_I2C_PERS, 0 },
+			 { TCS_I2C_CONFIG, 0x40 },
+			 { TCS_I2C_CONTROL,
+			   (TCS_DEFAULT_AGAIN & TCS_I2C_CONTROL_MASK) },
+			 { TCS_I2C_AUX, 0 },
+			 { TCS_I2C_IR, 0 },
+			 { TCS_I2C_CICLEAR, 0 },
+			 { TCS_I2C_AICLEAR, 0 } };
 	int data = 0;
 	int ret;
 
diff --git a/driver/amd_stt.c b/driver/amd_stt.c
index 90fd82523b..93da8cecb5 100644
--- a/driver/amd_stt.c
+++ b/driver/amd_stt.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,9 +18,9 @@ static bool amd_stt_debug;
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_THERMAL, outstr)
-#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
 
-static const char * const amd_stt_sensor_name[] = {
+static const char *const amd_stt_sensor_name[] = {
 	[AMD_STT_PCB_SENSOR_APU] = "APU",
 	[AMD_STT_PCB_SENSOR_REMOTE] = "Ambient",
 	[AMD_STT_PCB_SENSOR_GPU] = "GPU",
@@ -108,9 +108,9 @@ static void amd_stt_handler(void)
 		return;
 	}
 }
-DECLARE_HOOK(HOOK_SECOND, amd_stt_handler, HOOK_PRIO_TEMP_SENSOR+1);
+DECLARE_HOOK(HOOK_SECOND, amd_stt_handler, HOOK_PRIO_TEMP_SENSOR + 1);
 
-static int command_stt(int argc, char **argv)
+static int command_stt(int argc, const char **argv)
 {
 	int sensor_id;
 	int temp;
diff --git a/driver/baro_bmp280.c b/driver/baro_bmp280.c
index 037a77d963..0175dc7e4a 100644
--- a/driver/baro_bmp280.c
+++ b/driver/baro_bmp280.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -63,10 +63,12 @@
 #include "i2c.h"
 #include "timer.h"
 
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args)
 
-static const uint16_t standby_durn[] = {1, 63, 125, 250, 500, 1000, 2000, 4000};
+static const uint16_t standby_durn[] = {
+	1, 63, 125, 250, 500, 1000, 2000, 4000
+};
 
 /*
  * This function is used to get calibration parameters used for
@@ -95,19 +97,19 @@ static int bmp280_get_calib_param(const struct motion_sensor_t *s)
 {
 	int ret;
 
-	uint8_t a_data_u8[BMP280_CALIB_DATA_SIZE] = {0};
+	uint8_t a_data_u8[BMP280_CALIB_DATA_SIZE] = { 0 };
 	struct bmp280_drv_data_t *data = BMP280_GET_DATA(s);
 
 	ret = i2c_read_block(s->port, s->i2c_spi_addr_flags,
-			BMP280_TEMPERATURE_CALIB_DIG_T1_LSB_REG,
-			a_data_u8, BMP280_CALIB_DATA_SIZE);
+			     BMP280_TEMPERATURE_CALIB_DIG_T1_LSB_REG, a_data_u8,
+			     BMP280_CALIB_DATA_SIZE);
 
 	if (ret)
 		return ret;
 
 	/* read calibration values*/
 	data->calib_param.dig_T1 = (a_data_u8[1] << 8) | a_data_u8[0];
-	data->calib_param.dig_T2 = (a_data_u8[3] << 8  | a_data_u8[2]);
+	data->calib_param.dig_T2 = (a_data_u8[3] << 8 | a_data_u8[2]);
 	data->calib_param.dig_T3 = (a_data_u8[5] << 8) | a_data_u8[4];
 
 	data->calib_param.dig_P1 = (a_data_u8[7] << 8) | a_data_u8[6];
@@ -124,21 +126,20 @@ static int bmp280_get_calib_param(const struct motion_sensor_t *s)
 }
 
 static int bmp280_read_uncomp_pressure(const struct motion_sensor_t *s,
-					int *uncomp_pres)
+				       int *uncomp_pres)
 {
 	int ret;
-	uint8_t a_data_u8[BMP280_PRESSURE_DATA_SIZE] = {0};
+	uint8_t a_data_u8[BMP280_PRESSURE_DATA_SIZE] = { 0 };
 
 	ret = i2c_read_block(s->port, s->i2c_spi_addr_flags,
-			BMP280_PRESSURE_MSB_REG,
-			a_data_u8, BMP280_PRESSURE_DATA_SIZE);
+			     BMP280_PRESSURE_MSB_REG, a_data_u8,
+			     BMP280_PRESSURE_DATA_SIZE);
 
 	if (ret)
 		return ret;
 
-	*uncomp_pres = (int32_t)((a_data_u8[0] << 12) |
-		     (a_data_u8[1] << 4) |
-		     (a_data_u8[2] >> 4));
+	*uncomp_pres = (int32_t)((a_data_u8[0] << 12) | (a_data_u8[1] << 4) |
+				 (a_data_u8[2] >> 4));
 
 	return EC_SUCCESS;
 }
@@ -153,34 +154,33 @@ static int bmp280_read_uncomp_pressure(const struct motion_sensor_t *s,
  *
  */
 static int bmp280_compensate_pressure(const struct motion_sensor_t *s,
-					int uncomp_pressure)
+				      int uncomp_pressure)
 {
 	int var1, var2;
 	uint32_t p;
 	struct bmp280_drv_data_t *data = BMP280_GET_DATA(s);
 
 	/* calculate x1 */
-	var1 = (((int32_t)data->calib_param.t_fine)
-		>> 1) - 64000;
+	var1 = (((int32_t)data->calib_param.t_fine) >> 1) - 64000;
 	/* calculate x2 */
-	var2 = (((var1 >> 2) * (var1 >> 2)) >> 11)
-		* ((int32_t)data->calib_param.dig_P6);
+	var2 = (((var1 >> 2) * (var1 >> 2)) >> 11) *
+	       ((int32_t)data->calib_param.dig_P6);
 	var2 = var2 + ((var1 * ((int32_t)data->calib_param.dig_P5)) << 1);
 	var2 = (var2 >> 2) + (((int32_t)data->calib_param.dig_P4) << 16);
 	/* calculate x1 */
 	var1 = (((data->calib_param.dig_P3 *
-		(((var1 >> 2) * (var1 >> 2)) >> 13)) >> 3) +
-		((((int32_t)data->calib_param.dig_P2) * var1) >> 1)) >> 18;
-	var1 = ((((32768 + var1)) *
-		((int32_t)data->calib_param.dig_P1)) >> 15);
+		  (((var1 >> 2) * (var1 >> 2)) >> 13)) >>
+		 3) +
+		((((int32_t)data->calib_param.dig_P2) * var1) >> 1)) >>
+	       18;
+	var1 = ((((32768 + var1)) * ((int32_t)data->calib_param.dig_P1)) >> 15);
 
 	/* Avoid exception caused by division by zero */
 	if (!var1)
 		return 0;
 
 	/* calculate pressure */
-	p = (((uint32_t)((1048576) - uncomp_pressure) -
-		(var2 >> 12))) * 3125;
+	p = (((uint32_t)((1048576) - uncomp_pressure) - (var2 >> 12))) * 3125;
 
 	/* check overflow */
 	if (p < 0x80000000)
@@ -190,13 +190,14 @@ static int bmp280_compensate_pressure(const struct motion_sensor_t *s,
 
 	/* calculate x1 */
 	var1 = (((int32_t)data->calib_param.dig_P9) *
-		((int32_t)(((p >> 3) * (p >> 3)) >> 13))) >> 12;
+		((int32_t)(((p >> 3) * (p >> 3)) >> 13))) >>
+	       12;
 	/* calculate x2 */
-	var2 = (((int32_t)(p >> 2)) *
-		((int32_t)data->calib_param.dig_P8)) >> 13;
+	var2 = (((int32_t)(p >> 2)) * ((int32_t)data->calib_param.dig_P8)) >>
+	       13;
 	/* calculate true pressure */
-	return (uint32_t)((int32_t)p + ((var1 + var2 +
-		data->calib_param.dig_P7) >> 4));
+	return (uint32_t)((int32_t)p +
+			  ((var1 + var2 + data->calib_param.dig_P7) >> 4));
 }
 
 /*
@@ -214,38 +215,36 @@ static int bmp280_compensate_pressure(const struct motion_sensor_t *s,
  *    0x07    | 4000_MS
  */
 static int bmp280_set_standby_durn(const struct motion_sensor_t *s,
-				uint8_t durn)
+				   uint8_t durn)
 {
 	int ret, val;
 
-	ret = i2c_read8(s->port, s->i2c_spi_addr_flags,
-			BMP280_CONFIG_REG, &val);
+	ret = i2c_read8(s->port, s->i2c_spi_addr_flags, BMP280_CONFIG_REG,
+			&val);
 
 	if (ret == EC_SUCCESS) {
 		val = (val & 0xE0) | ((durn << 5) & 0xE0);
 		/* write the standby duration*/
 		ret = i2c_write8(s->port, s->i2c_spi_addr_flags,
-			   BMP280_CONFIG_REG, val);
+				 BMP280_CONFIG_REG, val);
 	}
 
 	return ret;
 }
 
 static int bmp280_set_power_mode(const struct motion_sensor_t *s,
-				uint8_t power_mode)
+				 uint8_t power_mode)
 {
 	int val;
 
-	val = (BMP280_OVERSAMP_TEMP << 5) +
-		(BMP280_OVERSAMP_PRES << 2) + power_mode;
+	val = (BMP280_OVERSAMP_TEMP << 5) + (BMP280_OVERSAMP_PRES << 2) +
+	      power_mode;
 
-	return i2c_write8(s->port, s->i2c_spi_addr_flags,
-			  BMP280_CTRL_MEAS_REG, val);
+	return i2c_write8(s->port, s->i2c_spi_addr_flags, BMP280_CTRL_MEAS_REG,
+			  val);
 }
 
-static int bmp280_set_range(struct motion_sensor_t *s,
-				int range,
-				int rnd)
+static int bmp280_set_range(struct motion_sensor_t *s, int range, int rnd)
 {
 	struct bmp280_drv_data_t *data = BMP280_GET_DATA(s);
 	/*
@@ -272,8 +271,8 @@ static int bmp280_init(struct motion_sensor_t *s)
 		return EC_ERROR_INVAL;
 
 	/* Read chip id */
-	ret = i2c_read8(s->port, s->i2c_spi_addr_flags,
-			BMP280_CHIP_ID_REG, &val);
+	ret = i2c_read8(s->port, s->i2c_spi_addr_flags, BMP280_CHIP_ID_REG,
+			&val);
 	if (ret)
 		return ret;
 
@@ -314,7 +313,7 @@ static int bmp280_read(const struct motion_sensor_t *s, intv3_t v)
  * Calculate the delay (in ms) to apply.
  */
 static int bmp280_set_data_rate(const struct motion_sensor_t *s, int rate,
-							int roundup)
+				int roundup)
 {
 	struct bmp280_drv_data_t *data = BMP280_GET_DATA(s);
 	int durn, i, ret;
@@ -335,12 +334,12 @@ static int bmp280_set_data_rate(const struct motion_sensor_t *s, int rate,
 	}
 
 	durn = 0;
-	for (i = BMP280_STANDBY_CNT-1;  i > 0; i--) {
+	for (i = BMP280_STANDBY_CNT - 1; i > 0; i--) {
 		if (period >= standby_durn[i] + BMP280_COMPUTE_TIME) {
 			durn = i;
 			break;
-		} else if (period > standby_durn[i-1] + BMP280_COMPUTE_TIME) {
-			durn = roundup ? i-1 : i;
+		} else if (period > standby_durn[i - 1] + BMP280_COMPUTE_TIME) {
+			durn = roundup ? i - 1 : i;
 			break;
 		}
 	}
diff --git a/driver/baro_bmp280.h b/driver/baro_bmp280.h
index ee95bd886f..605f3db4fa 100644
--- a/driver/baro_bmp280.h
+++ b/driver/baro_bmp280.h
@@ -1,62 +1,62 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 /** \mainpage
-*
-****************************************************************************
-* Copyright (C) 2012 - 2015 Bosch Sensortec GmbH
-*
-* File : bmp280.h
-*
-* Date : 2015/03/27
-*
-* Revision : 2.0.4(Pressure and Temperature compensation code revision is 1.1)
-*
-* Usage: Sensor Driver for BMP280 sensor
-*
-****************************************************************************
-*
-* \section License
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions are met:
-*
-*   Redistributions of source code must retain the above copyright
-*   notice, this list of conditions and the following disclaimer.
-*
-*   Redistributions in binary form must reproduce the above copyright
-*   notice, this list of conditions and the following disclaimer in the
-*   documentation and/or other materials provided with the distribution.
-*
-*   Neither the name of the copyright holder nor the names of the
-*   contributors may be used to endorse or promote products derived from
-*   this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
-* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDER
-* OR CONTRIBUTORS BE LIABLE FOR ANY
-* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-* OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT NOT LIMITED TO,
-* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
-*
-* The information provided is believed to be accurate and reliable.
-* The copyright holder assumes no responsibility
-* for the consequences of use
-* of such information nor for any infringement of patents or
-* other rights of third parties which may result from its use.
-* No license is granted by implication or otherwise under any patent or
-* patent rights of the copyright holder.
-**************************************************************************/
+ *
+ ****************************************************************************
+ * Copyright (C) 2012 - 2015 Bosch Sensortec GmbH
+ *
+ * File : bmp280.h
+ *
+ * Date : 2015/03/27
+ *
+ * Revision : 2.0.4(Pressure and Temperature compensation code revision is 1.1)
+ *
+ * Usage: Sensor Driver for BMP280 sensor
+ *
+ ****************************************************************************
+ *
+ * \section License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *   Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ *   Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ *
+ *   Neither the name of the copyright holder nor the names of the
+ *   contributors may be used to endorse or promote products derived from
+ *   this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ * The information provided is believed to be accurate and reliable.
+ * The copyright holder assumes no responsibility
+ * for the consequences of use
+ * of such information nor for any infringement of patents or
+ * other rights of third parties which may result from its use.
+ * No license is granted by implication or otherwise under any patent or
+ * patent rights of the copyright holder.
+ **************************************************************************/
 /* BMP280 pressure and temperature module for Chrome EC */
 
 #ifndef __CROS_EC_BARO_BMP280_H
@@ -74,80 +74,81 @@
  * Bit 1 of 7-bit address: 0 - If SDO is connected to GND
  * Bit 1 of 7-bit address: 1 - If SDO is connected to Vddio
  */
-#define BMP280_I2C_ADDRESS1_FLAGS	0x76
-#define BMP280_I2C_ADDRESS2_FLAGS	0x77
+#define BMP280_I2C_ADDRESS1_FLAGS 0x76
+#define BMP280_I2C_ADDRESS2_FLAGS 0x77
 
 /*
  *     CHIP ID
  */
-#define BMP280_CHIP_ID			0x58
+#define BMP280_CHIP_ID 0x58
 /************************************************/
 /*	CALIBRATION PARAMETERS DEFINITION       */
 /************************************************/
 
-#define BMP280_TEMPERATURE_CALIB_DIG_T1_LSB_REG	0x88
+#define BMP280_TEMPERATURE_CALIB_DIG_T1_LSB_REG 0x88
 
 /************************************************/
 /*	REGISTER ADDRESS DEFINITION             */
 /************************************************/
-#define BMP280_CHIP_ID_REG		     0xD0
-#define BMP280_RST_REG                       0xE0  /*Softreset Register */
-#define BMP280_STAT_REG                      0xF3  /*Status Register */
-#define BMP280_CTRL_MEAS_REG                 0xF4  /*Ctrl Measure Register */
-#define BMP280_CONFIG_REG                    0xF5  /*Configuration Register */
-#define BMP280_PRESSURE_MSB_REG              0xF7  /*Pressure MSB Register */
-#define BMP280_PRESSURE_LSB_REG              0xF8  /*Pressure LSB Register */
-#define BMP280_PRESSURE_XLSB_REG             0xF9  /*Pressure XLSB Register */
+#define BMP280_CHIP_ID_REG 0xD0
+#define BMP280_RST_REG 0xE0 /*Softreset Register */
+#define BMP280_STAT_REG 0xF3 /*Status Register */
+#define BMP280_CTRL_MEAS_REG 0xF4 /*Ctrl Measure Register */
+#define BMP280_CONFIG_REG 0xF5 /*Configuration Register */
+#define BMP280_PRESSURE_MSB_REG 0xF7 /*Pressure MSB Register */
+#define BMP280_PRESSURE_LSB_REG 0xF8 /*Pressure LSB Register */
+#define BMP280_PRESSURE_XLSB_REG 0xF9 /*Pressure XLSB Register */
 /************************************************/
 /*	POWER MODE DEFINITION                   */
 /************************************************/
 /* Sensor Specific constants */
-#define BMP280_SLEEP_MODE                    0x00
-#define BMP280_FORCED_MODE                   0x01
-#define BMP280_NORMAL_MODE                   0x03
-#define BMP280_SOFT_RESET_CODE               0xB6
+#define BMP280_SLEEP_MODE 0x00
+#define BMP280_FORCED_MODE 0x01
+#define BMP280_NORMAL_MODE 0x03
+#define BMP280_SOFT_RESET_CODE 0xB6
 /************************************************/
 /*	STANDBY TIME DEFINITION                 */
 /************************************************/
-#define BMP280_STANDBY_TIME_1_MS              0x00
-#define BMP280_STANDBY_TIME_63_MS             0x01
-#define BMP280_STANDBY_TIME_125_MS            0x02
-#define BMP280_STANDBY_TIME_250_MS            0x03
-#define BMP280_STANDBY_TIME_500_MS            0x04
-#define BMP280_STANDBY_TIME_1000_MS           0x05
-#define BMP280_STANDBY_TIME_2000_MS           0x06
-#define BMP280_STANDBY_TIME_4000_MS           0x07
+#define BMP280_STANDBY_TIME_1_MS 0x00
+#define BMP280_STANDBY_TIME_63_MS 0x01
+#define BMP280_STANDBY_TIME_125_MS 0x02
+#define BMP280_STANDBY_TIME_250_MS 0x03
+#define BMP280_STANDBY_TIME_500_MS 0x04
+#define BMP280_STANDBY_TIME_1000_MS 0x05
+#define BMP280_STANDBY_TIME_2000_MS 0x06
+#define BMP280_STANDBY_TIME_4000_MS 0x07
 /************************************************/
 /*	OVERSAMPLING DEFINITION                 */
 /************************************************/
-#define BMP280_OVERSAMP_SKIPPED          0x00
-#define BMP280_OVERSAMP_1X               0x01
-#define BMP280_OVERSAMP_2X               0x02
-#define BMP280_OVERSAMP_4X               0x03
-#define BMP280_OVERSAMP_8X               0x04
-#define BMP280_OVERSAMP_16X              0x05
+#define BMP280_OVERSAMP_SKIPPED 0x00
+#define BMP280_OVERSAMP_1X 0x01
+#define BMP280_OVERSAMP_2X 0x02
+#define BMP280_OVERSAMP_4X 0x03
+#define BMP280_OVERSAMP_8X 0x04
+#define BMP280_OVERSAMP_16X 0x05
 /************************************************/
 /*	DEFINITIONS FOR ARRAY SIZE OF DATA      */
 /************************************************/
-#define	BMP280_PRESSURE_DATA_SIZE	3
-#define	BMP280_DATA_FRAME_SIZE		6
-#define	BMP280_CALIB_DATA_SIZE		24
+#define BMP280_PRESSURE_DATA_SIZE 3
+#define BMP280_DATA_FRAME_SIZE 6
+#define BMP280_CALIB_DATA_SIZE 24
 /*******************************************************/
 /*         SAMPLING PERIOD COMPUTATION CONSTANT	       */
 /*******************************************************/
-#define BMP280_STANDBY_CNT		8
-#define T_INIT_MAX			(20) /* (20/16 = 1.25ms) */
-#define T_MEASURE_PER_OSRS_MAX		(37) /* (37/16 = 2.31ms) */
-#define T_SETUP_PRESSURE_MAX		(10) /* (10/16 = 0.62ms) */
+#define BMP280_STANDBY_CNT 8
+#define T_INIT_MAX (20) /* (20/16 = 1.25ms) */
+#define T_MEASURE_PER_OSRS_MAX (37) /* (37/16 = 2.31ms) */
+#define T_SETUP_PRESSURE_MAX (10) /* (10/16 = 0.62ms) */
 
 /*
  * This is the measurement time required for pressure and temp
  */
-#define BMP280_COMPUTE_TIME \
-	((T_INIT_MAX + T_MEASURE_PER_OSRS_MAX * \
-	  ((BIT(BMP280_OVERSAMP_TEMP) >> 1) + \
-	   (BIT(BMP280_OVERSAMP_PRES) >> 1)) + \
-	  (BMP280_OVERSAMP_PRES ? T_SETUP_PRESSURE_MAX : 0) + 15) / 16)
+#define BMP280_COMPUTE_TIME                                             \
+	((T_INIT_MAX +                                                  \
+	  T_MEASURE_PER_OSRS_MAX * ((BIT(BMP280_OVERSAMP_TEMP) >> 1) +  \
+				    (BIT(BMP280_OVERSAMP_PRES) >> 1)) + \
+	  (BMP280_OVERSAMP_PRES ? T_SETUP_PRESSURE_MAX : 0) + 15) /     \
+	 16)
 
 /*
  * These values are selected as per Bosch recommendation for
@@ -158,15 +159,14 @@
 /*******************************************************/
 /*             GET DRIVER DATA			       */
 /*******************************************************/
-#define BMP280_GET_DATA(_s) \
-	((struct bmp280_drv_data_t *)(_s)->drv_data)
+#define BMP280_GET_DATA(_s) ((struct bmp280_drv_data_t *)(_s)->drv_data)
 
 /* Min and Max sampling frequency in mHz based on x4 oversampling used */
 /* FIXME - verify how chip is setup to make sure MAX is correct, manual says
  * "Typical", not Max.
  */
-#define BMP280_BARO_MIN_FREQ  75000
-#define BMP280_BARO_MAX_FREQ  87000
+#define BMP280_BARO_MIN_FREQ 75000
+#define BMP280_BARO_MAX_FREQ 87000
 #if (CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ <= BMP280_BARO_MAX_FREQ)
 #error "EC too slow for accelerometer"
 #endif
@@ -208,8 +208,7 @@ struct bmp280_calib_param_t {
  * @range:		bit offset to fit data in 16 bit or less.
  */
 struct bmp280_drv_data_t {
-
-	struct   bmp280_calib_param_t calib_param;
+	struct bmp280_calib_param_t calib_param;
 	uint16_t rate;
 	uint16_t range;
 };
diff --git a/driver/battery/bq20z453.c b/driver/battery/bq20z453.c
index 2eea73742b..943dfe41b2 100644
--- a/driver/battery/bq20z453.c
+++ b/driver/battery/bq20z453.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/driver/battery/bq27541.c b/driver/battery/bq27541.c
index b59bfc0b18..f190c942ac 100644
--- a/driver/battery/bq27541.c
+++ b/driver/battery/bq27541.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -13,52 +13,52 @@
 #include "i2c.h"
 #include "util.h"
 
-#define BQ27541_ADDR_FLAGS          0x55
-#define BQ27541_TYPE_ID             0x0541
-#define BQ27542_TYPE_ID             0x0542
-#define BQ27741_TYPE_ID             0x0741
-#define BQ27742_TYPE_ID             0x0742
-
-#define REG_CTRL                    0x00
-#define REG_AT_RATE                 0x02
-#define REG_AT_RATE_TIME_TO_EMPTY   0x04
-#define REG_TEMPERATURE             0x06
-#define REG_VOLTAGE                 0x08
-#define REG_FLAGS                   0x0a
-#define REG_NOMINAL_CAPACITY        0x0c
+#define BQ27541_ADDR_FLAGS 0x55
+#define BQ27541_TYPE_ID 0x0541
+#define BQ27542_TYPE_ID 0x0542
+#define BQ27741_TYPE_ID 0x0741
+#define BQ27742_TYPE_ID 0x0742
+
+#define REG_CTRL 0x00
+#define REG_AT_RATE 0x02
+#define REG_AT_RATE_TIME_TO_EMPTY 0x04
+#define REG_TEMPERATURE 0x06
+#define REG_VOLTAGE 0x08
+#define REG_FLAGS 0x0a
+#define REG_NOMINAL_CAPACITY 0x0c
 #define REG_FULL_AVAILABLE_CAPACITY 0x0e
-#define REG_REMAINING_CAPACITY      0x10
-#define REG_FULL_CHARGE_CAPACITY    0x12
-#define REG_AVERAGE_CURRENT         0x14
-#define REG_TIME_TO_EMPTY           0x16
-#define REG_TIME_TO_FULL            0x18
-#define REG_STANDBY_CURRENT         0x1a
-#define REG_STANDBY_TIME_TO_EMPTY   0x1c
-#define REG_MAX_LOAD_CURRENT        0x1e
-#define REG_MAX_LOAD_TIME_TO_EMPTY  0x20
-#define REG_AVAILABLE_ENERGY        0x22
-#define REG_AVERAGE_POEWR           0x24
-#define REG_TT_EAT_CONSTANT_POWER   0x26
-#define REG_CYCLE_COUNT             0x2a
-#define REG_STATE_OF_CHARGE         0x2c
-#define	REG_DATA_FLASH_BLOCK	    0x3f
-#define REG_DESIGN_CAPACITY         0x3c
-#define REG_MANUFACTURER_INFO	    0x52
-#define REG_DEVICE_NAME_LENGTH      0x62
-#define MAX_DEVICE_NAME_LENGTH      7
-#define REG_DEVICE_NAME             0x63
-#define REG_PROTECTOR               0x6d
+#define REG_REMAINING_CAPACITY 0x10
+#define REG_FULL_CHARGE_CAPACITY 0x12
+#define REG_AVERAGE_CURRENT 0x14
+#define REG_TIME_TO_EMPTY 0x16
+#define REG_TIME_TO_FULL 0x18
+#define REG_STANDBY_CURRENT 0x1a
+#define REG_STANDBY_TIME_TO_EMPTY 0x1c
+#define REG_MAX_LOAD_CURRENT 0x1e
+#define REG_MAX_LOAD_TIME_TO_EMPTY 0x20
+#define REG_AVAILABLE_ENERGY 0x22
+#define REG_AVERAGE_POEWR 0x24
+#define REG_TT_EAT_CONSTANT_POWER 0x26
+#define REG_CYCLE_COUNT 0x2a
+#define REG_STATE_OF_CHARGE 0x2c
+#define REG_DATA_FLASH_BLOCK 0x3f
+#define REG_DESIGN_CAPACITY 0x3c
+#define REG_MANUFACTURER_INFO 0x52
+#define REG_DEVICE_NAME_LENGTH 0x62
+#define MAX_DEVICE_NAME_LENGTH 7
+#define REG_DEVICE_NAME 0x63
+#define REG_PROTECTOR 0x6d
 
 /* Over-charge */
-#define BQ27542_FLAG_BATHI           BIT(13)
+#define BQ27542_FLAG_BATHI BIT(13)
 /* Over Temperature in discharge */
-#define BQ27542_FLAG_OTD             BIT(11)
+#define BQ27542_FLAG_OTD BIT(11)
 /* Over Temperature in charge */
-#define BQ27542_FLAG_OTC             BIT(7)
+#define BQ27542_FLAG_OTC BIT(7)
 /* Charge allowed */
-#define BQ27542_FLAG_CHG             BIT(3)
+#define BQ27542_FLAG_CHG BIT(3)
 /* Discharge */
-#define BQ27542_FLAG_DSG             BIT(0)
+#define BQ27542_FLAG_DSG BIT(0)
 
 static int battery_type_id;
 static int fake_state_of_charge = -1;
@@ -273,10 +273,9 @@ enum battery_present battery_is_present(void)
 void battery_get_params(struct batt_params *batt)
 {
 	int v;
-	const uint32_t flags_to_check = BATT_FLAG_BAD_TEMPERATURE |
-					BATT_FLAG_BAD_STATE_OF_CHARGE |
-					BATT_FLAG_BAD_VOLTAGE |
-					BATT_FLAG_BAD_CURRENT;
+	const uint32_t flags_to_check =
+		BATT_FLAG_BAD_TEMPERATURE | BATT_FLAG_BAD_STATE_OF_CHARGE |
+		BATT_FLAG_BAD_VOLTAGE | BATT_FLAG_BAD_CURRENT;
 
 	/* Reset flags */
 	batt->flags = 0;
@@ -287,8 +286,8 @@ void battery_get_params(struct batt_params *batt)
 	if (bq27541_read8(REG_STATE_OF_CHARGE, &v) && fake_state_of_charge < 0)
 		batt->flags |= BATT_FLAG_BAD_STATE_OF_CHARGE;
 
-	batt->state_of_charge = fake_state_of_charge >= 0 ?
-					fake_state_of_charge : v;
+	batt->state_of_charge =
+		fake_state_of_charge >= 0 ? fake_state_of_charge : v;
 
 	if (bq27541_read(REG_VOLTAGE, &batt->voltage))
 		batt->flags |= BATT_FLAG_BAD_VOLTAGE;
@@ -312,8 +311,7 @@ void battery_get_params(struct batt_params *batt)
 		batt->flags |= BATT_FLAG_RESPONSIVE;
 		batt->is_present = BP_YES;
 	} else {
-
-	/* If all of those reads error, the battery is not present */
+		/* If all of those reads error, the battery is not present */
 		batt->is_present = BP_NO;
 	}
 
@@ -391,7 +389,7 @@ enum battery_disconnect_state battery_get_disconnect_state(void)
 }
 #endif /* CONFIG_BATTERY_REVIVE_DISCONNECT */
 
-static int command_battfake(int argc, char **argv)
+static int command_battfake(int argc, const char **argv)
 {
 	char *e;
 	int v;
@@ -405,8 +403,7 @@ static int command_battfake(int argc, char **argv)
 	}
 
 	if (fake_state_of_charge >= 0)
-		ccprintf("Fake batt %d%%\n",
-			 fake_state_of_charge);
+		ccprintf("Fake batt %d%%\n", fake_state_of_charge);
 
 	return EC_SUCCESS;
 }
diff --git a/driver/battery/bq27621_g1.c b/driver/battery/bq27621_g1.c
index 96b0ed6975..f29039f0c1 100644
--- a/driver/battery/bq27621_g1.c
+++ b/driver/battery/bq27621_g1.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -6,6 +6,7 @@
  */
 
 #include "battery.h"
+#include "builtin/assert.h"
 #include "console.h"
 #include "extpower.h"
 #include "hooks.h"
@@ -13,95 +14,95 @@
 #include "util.h"
 #include "timer.h"
 
-#define BQ27621_ADDR_FLAGS                  0x55
-#define BQ27621_TYPE_ID                     0x0621
-
-#define REG_CTRL                            0x00
-#define REG_TEMPERATURE                     0x02
-#define REG_VOLTAGE                         0x04
-#define REG_FLAGS                           0x06
-#define REG_NOMINAL_CAPACITY                0x08
-#define REG_FULL_AVAILABLE_CAPACITY         0x0a
-#define REG_REMAINING_CAPACITY              0x0c
-#define REG_FULL_CHARGE_CAPACITY            0x0e
-#define REG_EFFECTIVE_CURRENT               0x10
-#define REG_AVERAGE_POWER                   0x18
-#define REG_STATE_OF_CHARGE                 0x1c
-#define REG_INTERNAL_TEMPERATURE            0x1e
-#define REG_REMAINING_CAPACITY_UNFILTERED   0x28
-#define REG_REMAINING_CAPACITY_FILTERED     0x2a
+#define BQ27621_ADDR_FLAGS 0x55
+#define BQ27621_TYPE_ID 0x0621
+
+#define REG_CTRL 0x00
+#define REG_TEMPERATURE 0x02
+#define REG_VOLTAGE 0x04
+#define REG_FLAGS 0x06
+#define REG_NOMINAL_CAPACITY 0x08
+#define REG_FULL_AVAILABLE_CAPACITY 0x0a
+#define REG_REMAINING_CAPACITY 0x0c
+#define REG_FULL_CHARGE_CAPACITY 0x0e
+#define REG_EFFECTIVE_CURRENT 0x10
+#define REG_AVERAGE_POWER 0x18
+#define REG_STATE_OF_CHARGE 0x1c
+#define REG_INTERNAL_TEMPERATURE 0x1e
+#define REG_REMAINING_CAPACITY_UNFILTERED 0x28
+#define REG_REMAINING_CAPACITY_FILTERED 0x2a
 #define REG_FULL_CHARGE_CAPACITY_UNFILTERED 0x28
-#define REG_FULL_CHARGE_CAPACITY_FILTERED   0x2a
-#define REG_STATE_OF_CHARGE_UNFILTERED      0x30
-#define REG_OP_CONFIG                       0x3a
-#define REG_DESIGN_CAPACITY                 0x3c
-#define REG_DATA_CLASS                      0x3e
-#define REG_DATA_BLOCK                      0x3f
-#define REG_BLOCK_DATA_CHECKSUM             0x60
-#define REG_BLOCK_DATA_CONTROL              0x61
-
-#define REGISTERS_BLOCK_OFFSET                64
-#define REGISTERS_BLOCK_OP_CONFIG           0x40
-#define REGISTERS_BLOCK_OP_CONFIG_B         0x42
-#define REGISTERS_BLOCK_DF_VERSION          0x43
+#define REG_FULL_CHARGE_CAPACITY_FILTERED 0x2a
+#define REG_STATE_OF_CHARGE_UNFILTERED 0x30
+#define REG_OP_CONFIG 0x3a
+#define REG_DESIGN_CAPACITY 0x3c
+#define REG_DATA_CLASS 0x3e
+#define REG_DATA_BLOCK 0x3f
+#define REG_BLOCK_DATA_CHECKSUM 0x60
+#define REG_BLOCK_DATA_CONTROL 0x61
+
+#define REGISTERS_BLOCK_OFFSET 64
+#define REGISTERS_BLOCK_OP_CONFIG 0x40
+#define REGISTERS_BLOCK_OP_CONFIG_B 0x42
+#define REGISTERS_BLOCK_DF_VERSION 0x43
 
 /* State block */
-#define STATE_BLOCK_OFFSET                    82
-#define STATE_BLOCK_DESIGN_CAPACITY         0x43
-#define STATE_BLOCK_DESIGN_ENERGY           0x45
-#define STATE_BLOCK_TERMINATE_VOLTAGE       0x49
-#define STATE_BLOCK_TAPER_RATE              0x54
+#define STATE_BLOCK_OFFSET 82
+#define STATE_BLOCK_DESIGN_CAPACITY 0x43
+#define STATE_BLOCK_DESIGN_ENERGY 0x45
+#define STATE_BLOCK_TERMINATE_VOLTAGE 0x49
+#define STATE_BLOCK_TAPER_RATE 0x54
 
 /* BQ27621 Control subcommands */
-#define CONTROL_CONTROL_STATUS   0x00
-#define CONTROL_DEVICE_TYPE      0x01
-#define CONTROL_FW_VERSION       0x02
-#define CONTROL_PREV_MACWRITE    0x07
-#define CONTROL_CHEM_ID          0x08
-#define CONTROL_BAT_INSERT       0x0C
-#define CONTROL_BAT_REMOVE       0x0D
-#define CONTROL_TOGGLE_POWERMIN  0x10
-#define CONTROL_SET_HIBERNATE    0x11
-#define CONTROL_CLEAR_HIBERNATE  0x12
-#define CONTROL_SET_CFGUPDATE    0x13
-#define CONTROL_SHUTDOWN_ENABLE  0x1B
-#define CONTROL_SHUTDOWN         0x1C
-#define CONTROL_SEALED           0x20
-#define CONTROL_TOGGLE_GPOUT     0x23
-#define CONTROL_ALT_CHEM1        0x31
-#define CONTROL_ALT_CHEM2        0x32
-#define CONTROL_RESET            0x41
-#define CONTROL_SOFT_RESET       0x42
-#define CONTROL_EXIT_CFGUPDATE   0x43
-#define CONTROL_EXIT_RESIM       0x44
-#define CONTROL_UNSEAL           0x8000
+#define CONTROL_CONTROL_STATUS 0x00
+#define CONTROL_DEVICE_TYPE 0x01
+#define CONTROL_FW_VERSION 0x02
+#define CONTROL_PREV_MACWRITE 0x07
+#define CONTROL_CHEM_ID 0x08
+#define CONTROL_BAT_INSERT 0x0C
+#define CONTROL_BAT_REMOVE 0x0D
+#define CONTROL_TOGGLE_POWERMIN 0x10
+#define CONTROL_SET_HIBERNATE 0x11
+#define CONTROL_CLEAR_HIBERNATE 0x12
+#define CONTROL_SET_CFGUPDATE 0x13
+#define CONTROL_SHUTDOWN_ENABLE 0x1B
+#define CONTROL_SHUTDOWN 0x1C
+#define CONTROL_SEALED 0x20
+#define CONTROL_TOGGLE_GPOUT 0x23
+#define CONTROL_ALT_CHEM1 0x31
+#define CONTROL_ALT_CHEM2 0x32
+#define CONTROL_RESET 0x41
+#define CONTROL_SOFT_RESET 0x42
+#define CONTROL_EXIT_CFGUPDATE 0x43
+#define CONTROL_EXIT_RESIM 0x44
+#define CONTROL_UNSEAL 0x8000
 
 /* BQ27621 Status bits */
-#define STATUS_SHUTDOWNEN        0x8000
-#define STATUS_WDRESET           0x4000
-#define STATUS_SS                0x2000
-#define STATUS_CALMODE           0x1000
-#define STATUS_OCVCMDCOMP        0x0200
-#define STATUS_OCVFAIL           0x0100
-#define STATUS_INITCOMP          0x0080
-#define STATUS_HIBERNATE         0x0040
-#define STATUS_POWERMIN          0x0020
-#define STATUS_SLEEP             0x0010
-#define STATUS_LDMD              0x0008
-#define STATUS_CHEMCHNG          0x0001
+#define STATUS_SHUTDOWNEN 0x8000
+#define STATUS_WDRESET 0x4000
+#define STATUS_SS 0x2000
+#define STATUS_CALMODE 0x1000
+#define STATUS_OCVCMDCOMP 0x0200
+#define STATUS_OCVFAIL 0x0100
+#define STATUS_INITCOMP 0x0080
+#define STATUS_HIBERNATE 0x0040
+#define STATUS_POWERMIN 0x0020
+#define STATUS_SLEEP 0x0010
+#define STATUS_LDMD 0x0008
+#define STATUS_CHEMCHNG 0x0001
 
 /* BQ27621 Flags bits */
-#define FLAGS_OT                 0x8000
-#define FLAGS_UT                 0x4000
-#define FLAGS_FC                 0x0200
-#define FLAGS_CHG                0x0100
-#define FLAGS_OCVTAKEN           0x0080
-#define FLAGS_ITPOR              0x0020
-#define FLAGS_CFGUPD             0x0010
-#define FLAGS_BAT_DET            0x0008
-#define FLAGS_SOC1               0x0004
-#define FLAGS_SOCF               0x0002
-#define FLAGS_DSG                0x0001
+#define FLAGS_OT 0x8000
+#define FLAGS_UT 0x4000
+#define FLAGS_FC 0x0200
+#define FLAGS_CHG 0x0100
+#define FLAGS_OCVTAKEN 0x0080
+#define FLAGS_ITPOR 0x0020
+#define FLAGS_CFGUPD 0x0010
+#define FLAGS_BAT_DET 0x0008
+#define FLAGS_SOC1 0x0004
+#define FLAGS_SOCF 0x0002
+#define FLAGS_DSG 0x0001
 
 /*
  * There are some parameters that need to be defined in the board file:
@@ -119,19 +120,23 @@
  *
  */
 
-#define BQ27621_SCALE_FACTOR (BQ27621_DESIGN_CAPACITY < 150 ? 10.0 : \
-				(BQ27621_DESIGN_CAPACITY > 6000 ? 0.1 : 1))
+#define BQ27621_SCALE_FACTOR             \
+	(BQ27621_DESIGN_CAPACITY < 150 ? \
+		 10.0 :                  \
+		 (BQ27621_DESIGN_CAPACITY > 6000 ? 0.1 : 1))
 
-#define BQ27621_UNSCALE(x)   (BQ27621_SCALE_FACTOR == 10 ? (x) / 10 : \
-				(BQ27621_SCALE_FACTOR == 0.1 ? (x) * 10 : (x)))
+#define BQ27621_UNSCALE(x)            \
+	(BQ27621_SCALE_FACTOR == 10 ? \
+		 (x) / 10 :           \
+		 (BQ27621_SCALE_FACTOR == 0.1 ? (x)*10 : (x)))
 
-#define BQ27621_TAPER_RATE  ((int)(BQ27621_DESIGN_CAPACITY/    \
-				(0.1 * BQ27621_TAPER_CURRENT)))
+#define BQ27621_TAPER_RATE \
+	((int)(BQ27621_DESIGN_CAPACITY / (0.1 * BQ27621_TAPER_CURRENT)))
 
-#define BQ27621_SCALED_DESIGN_CAPACITY ((int)(BQ27621_DESIGN_CAPACITY *   \
-					BQ27621_SCALE_FACTOR))
-#define BQ27621_SCALED_DESIGN_ENERGY   ((int)(BQ27621_DESIGN_CAPACITY *   \
-					BQ27621_SCALE_FACTOR))
+#define BQ27621_SCALED_DESIGN_CAPACITY \
+	((int)(BQ27621_DESIGN_CAPACITY * BQ27621_SCALE_FACTOR))
+#define BQ27621_SCALED_DESIGN_ENERGY \
+	((int)(BQ27621_DESIGN_CAPACITY * BQ27621_SCALE_FACTOR))
 
 /*
  *Everything is LSB first.  Parameters need to be converted.
@@ -139,11 +144,11 @@
  * The values from the data sheet are already LSB-first.
  */
 
-#define ENDIAN_SWAP_2B(x)     ((((x) & 0xff) << 8) | (((x) & 0xff00) >> 8))
-#define DESIGN_CAPACITY       ENDIAN_SWAP_2B(BQ27621_SCALED_DESIGN_CAPACITY)
-#define DESIGN_ENERGY         ENDIAN_SWAP_2B(BQ27621_SCALED_DESIGN_ENERGY)
-#define TAPER_RATE            ENDIAN_SWAP_2B(BQ27621_TAPER_RATE)
-#define TERMINATE_VOLTAGE     ENDIAN_SWAP_2B(BQ27621_TERMINATE_VOLTAGE)
+#define ENDIAN_SWAP_2B(x) ((((x)&0xff) << 8) | (((x)&0xff00) >> 8))
+#define DESIGN_CAPACITY ENDIAN_SWAP_2B(BQ27621_SCALED_DESIGN_CAPACITY)
+#define DESIGN_ENERGY ENDIAN_SWAP_2B(BQ27621_SCALED_DESIGN_ENERGY)
+#define TAPER_RATE ENDIAN_SWAP_2B(BQ27621_TAPER_RATE)
+#define TERMINATE_VOLTAGE ENDIAN_SWAP_2B(BQ27621_TERMINATE_VOLTAGE)
 
 struct battery_info battery_params;
 
@@ -192,7 +197,7 @@ static int bq27621_probe(void)
 static inline int bq27621_unseal(void)
 {
 	return bq27621_write(REG_CTRL, CONTROL_UNSEAL) |
-				bq27621_write(REG_CTRL, CONTROL_UNSEAL);
+	       bq27621_write(REG_CTRL, CONTROL_UNSEAL);
 }
 
 static int bq27621_enter_config_update(void)
@@ -200,8 +205,9 @@ static int bq27621_enter_config_update(void)
 	int tries, flags = 0, rv = EC_SUCCESS;
 
 	/* Enter Config Update Mode (Can take up to a second) */
-	for (tries = 2000; tries > 0 && !(flags & FLAGS_CFGUPD) &&
-					(rv == EC_SUCCESS); tries--) {
+	for (tries = 2000;
+	     tries > 0 && !(flags & FLAGS_CFGUPD) && (rv == EC_SUCCESS);
+	     tries--) {
 		rv |= bq27621_write(REG_CTRL, CONTROL_SET_CFGUPDATE);
 		rv |= bq27621_read(REG_FLAGS, &flags);
 	}
@@ -255,7 +261,7 @@ static int bq27621_seal(void)
 	rv = bq27621_read8(REGISTERS_BLOCK_OP_CONFIG_B, &param);
 	checksum -= param; /* 1B */
 
-	param |= 1<<5; /* Set DEF_SEAL */
+	param |= 1 << 5; /* Set DEF_SEAL */
 
 	rv = bq27621_write8(REGISTERS_BLOCK_OP_CONFIG_B, param);
 	checksum += param; /* 1B */
@@ -273,7 +279,7 @@ static int bq27621_seal(void)
 	return rv;
 }
 
-#define CHECKSUM_2B(x) ((x & 0xff) + ((x>>8) & 0xff))
+#define CHECKSUM_2B(x) ((x & 0xff) + ((x >> 8) & 0xff))
 
 static int bq27621_init(void)
 {
@@ -308,18 +314,18 @@ static int bq27621_init(void)
 
 			if (BQ27621_CHEM_ID == 0x1210)
 				rv |= bq27621_write(REG_CTRL,
-					CONTROL_ALT_CHEM1);
+						    CONTROL_ALT_CHEM1);
 			if (BQ27621_CHEM_ID == 0x0354)
 				rv |= bq27621_write(REG_CTRL,
-					CONTROL_ALT_CHEM2);
+						    CONTROL_ALT_CHEM2);
 
-		/*
-		 * The datasheet recommends checking the status here.
-		 *
-		 * If the CHEMCHG is active, it wasn't successful.
-		 *
-		 * There's no recommendation for what to do if it isn't.
-		 */
+			/*
+			 * The datasheet recommends checking the status here.
+			 *
+			 * If the CHEMCHG is active, it wasn't successful.
+			 *
+			 * There's no recommendation for what to do if it isn't.
+			 */
 
 			rv |= bq27621_write(REG_CTRL, CONTROL_EXIT_CFGUPDATE);
 		}
@@ -374,7 +380,6 @@ static int bq27621_init(void)
 
 	checksum = 0xff - (0xff & checksum);
 
-
 	if (rv)
 		return rv;
 
@@ -403,7 +408,7 @@ static void probe_type_id_init(void)
 
 	if (rv) { /* Try it once more */
 		rv = bq27621_write(REG_CTRL, CONTROL_RESET);
-	  rv |= bq27621_init();
+		rv |= bq27621_init();
 	}
 }
 
@@ -555,14 +560,14 @@ int battery_wait_for_stable(void)
 }
 
 #ifdef CONFIG_CMD_BATDEBUG
-	#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args)
 #else
-	#define CPRINTF(format, args...)
+#define CPRINTF(format, args...)
 #endif
 
 #ifdef CONFIG_CMD_BATDEBUG
 
-static int command_fgunseal(int argc, char **argv)
+static int command_fgunseal(int argc, const char **argv)
 {
 	int rv = EC_SUCCESS;
 
@@ -574,11 +579,9 @@ static int command_fgunseal(int argc, char **argv)
 	return rv;
 }
 
-DECLARE_CONSOLE_COMMAND(fgunseal, command_fgunseal,
-			"",
-			"Unseal the fg");
+DECLARE_CONSOLE_COMMAND(fgunseal, command_fgunseal, "", "Unseal the fg");
 
-static int command_fgseal(int argc, char **argv)
+static int command_fgseal(int argc, const char **argv)
 {
 	int rv = EC_SUCCESS;
 
@@ -590,11 +593,9 @@ static int command_fgseal(int argc, char **argv)
 	return rv;
 }
 
-DECLARE_CONSOLE_COMMAND(fgseal, command_fgseal,
-			"",
-			"Seal the fg");
+DECLARE_CONSOLE_COMMAND(fgseal, command_fgseal, "", "Seal the fg");
 
-static int command_fginit(int argc, char **argv)
+static int command_fginit(int argc, const char **argv)
 {
 	int rv = EC_SUCCESS;
 	int force = 0;
@@ -625,11 +626,9 @@ static int command_fginit(int argc, char **argv)
 	return rv;
 }
 
-DECLARE_CONSOLE_COMMAND(fginit, command_fginit,
-			"[force]",
-			"Initialize the fg");
+DECLARE_CONSOLE_COMMAND(fginit, command_fginit, "[force]", "Initialize the fg");
 
-static int command_fgprobe(int argc, char **argv)
+static int command_fgprobe(int argc, const char **argv)
 {
 	int rv = EC_SUCCESS;
 
@@ -641,11 +640,9 @@ static int command_fgprobe(int argc, char **argv)
 	return rv;
 }
 
-DECLARE_CONSOLE_COMMAND(fgprobe, command_fgprobe,
-			"",
-			"Probe the fg");
+DECLARE_CONSOLE_COMMAND(fgprobe, command_fgprobe, "", "Probe the fg");
 
-static int command_fgrd(int argc, char **argv)
+static int command_fgrd(int argc, const char **argv)
 {
 	int cmd, len;
 	int rv = EC_SUCCESS;
@@ -675,11 +672,10 @@ static int command_fgrd(int argc, char **argv)
 	return rv;
 }
 
-DECLARE_CONSOLE_COMMAND(fgrd, command_fgrd,
-			"cmd len",
+DECLARE_CONSOLE_COMMAND(fgrd, command_fgrd, "cmd len",
 			"Read _len_ words from the fg");
 
-static int command_fgcmd(int argc, char **argv)
+static int command_fgcmd(int argc, const char **argv)
 {
 	int cmd, data, byte = 0;
 	char *e;
@@ -708,14 +704,12 @@ static int command_fgcmd(int argc, char **argv)
 		CPRINTF("Write 2 bytes @0xaa %0x: 0x%0x\n", cmd, data);
 		return bq27621_write(cmd, data);
 	}
-
 }
 
-DECLARE_CONSOLE_COMMAND(fgcmd, command_fgcmd,
-			"cmd data [byte]",
+DECLARE_CONSOLE_COMMAND(fgcmd, command_fgcmd, "cmd data [byte]",
 			"Send a cmd to the fg");
 
-static int command_fgcmdrd(int argc, char **argv)
+static int command_fgcmdrd(int argc, const char **argv)
 {
 	int cmd, data, val;
 	int rv = EC_SUCCESS;
@@ -739,8 +733,8 @@ static int command_fgcmdrd(int argc, char **argv)
 	return rv;
 }
 
-DECLARE_CONSOLE_COMMAND(fgcmdrd, command_fgcmdrd,
-			"cmd data",
-			"Send a 2-byte cmd to the fg, read back the 2-byte result");
+DECLARE_CONSOLE_COMMAND(
+	fgcmdrd, command_fgcmdrd, "cmd data",
+	"Send a 2-byte cmd to the fg, read back the 2-byte result");
 
 #endif /* CONFIG_CMD_BATDEBUG */
diff --git a/driver/battery/bq4050.c b/driver/battery/bq4050.c
index 32fc858d08..9ba9a7304c 100644
--- a/driver/battery/bq4050.c
+++ b/driver/battery/bq4050.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -18,9 +18,8 @@ int battery_bq4050_imbalance_mv(void)
 	 * returns a voltage for each cell, regardless of the number of cells
 	 * actually installed in the pack.  Unpopulated cells read exactly zero.
 	 */
-	static const uint8_t cell_voltage_address[4] = {
-		0x3c, 0x3d, 0x3e, 0x3f
-	};
+	static const uint8_t cell_voltage_address[4] = { 0x3c, 0x3d, 0x3e,
+							 0x3f };
 	int i, res, cell_voltage;
 	int n_cells = 0;
 	int max_voltage = 0;
diff --git a/driver/battery/max17055.c b/driver/battery/max17055.c
index bb0b941937..4610be64b6 100644
--- a/driver/battery/max17055.c
+++ b/driver/battery/max17055.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -6,6 +6,7 @@
  */
 
 #include "battery.h"
+#include "builtin/assert.h"
 #include "console.h"
 #include "extpower.h"
 #include "hooks.h"
@@ -16,13 +17,13 @@
 #include "util.h"
 
 /* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 /*
  * For max17055 to finish battery presence detection, this is the minimal time
  * we have to wait since the last POR. LSB = 175ms.
  */
-#define RELIABLE_BATT_DETECT_TIME	0x10
+#define RELIABLE_BATT_DETECT_TIME 0x10
 
 /*
  * Convert the register values to the units that match
@@ -30,50 +31,48 @@
  */
 
 /* Voltage reg value to mV */
-#define VOLTAGE_CONV(REG)       ((REG * 5) >> 6)
+#define VOLTAGE_CONV(REG) ((REG * 5) >> 6)
 /* Current reg value to mA */
-#define CURRENT_CONV(REG)       (((REG * 25) >> 4) / BATTERY_MAX17055_RSENSE)
+#define CURRENT_CONV(REG) (((REG * 25) >> 4) / BATTERY_MAX17055_RSENSE)
 /* Capacity reg value to mAh */
-#define CAPACITY_CONV(REG)      (REG * 5 / BATTERY_MAX17055_RSENSE)
+#define CAPACITY_CONV(REG) (REG * 5 / BATTERY_MAX17055_RSENSE)
 /* Time reg value to minute */
-#define TIME_CONV(REG)          ((REG * 3) >> 5)
+#define TIME_CONV(REG) ((REG * 3) >> 5)
 /* Temperature reg value to 0.1K */
-#define TEMPERATURE_CONV(REG)   (((REG * 10) >> 8) + 2731)
+#define TEMPERATURE_CONV(REG) (((REG * 10) >> 8) + 2731)
 /* Percentage reg value to 1% */
-#define PERCENTAGE_CONV(REG)    (REG >> 8)
+#define PERCENTAGE_CONV(REG) (REG >> 8)
 /* Cycle count reg value (LSB = 1%) to absolute count (100%) */
-#define CYCLE_COUNT_CONV(REG)	((REG * 5) >> 9)
+#define CYCLE_COUNT_CONV(REG) ((REG * 5) >> 9)
 
 /* Useful macros */
-#define MAX17055_READ_DEBUG(offset, ptr_reg) \
-	do { \
-		if (max17055_read(offset, ptr_reg)) { \
-			CPRINTS("%s: failed to read reg %02x", \
-				__func__, offset); \
-			return; \
-		} \
+#define MAX17055_READ_DEBUG(offset, ptr_reg)                             \
+	do {                                                             \
+		if (max17055_read(offset, ptr_reg)) {                    \
+			CPRINTS("%s: failed to read reg %02x", __func__, \
+				offset);                                 \
+			return;                                          \
+		}                                                        \
 	} while (0)
-#define MAX17055_WRITE_DEBUG(offset, reg) \
-	do { \
-		if (max17055_write(offset, reg)) { \
-			CPRINTS("%s: failed to read reg %02x", \
-				__func__, offset); \
-			return; \
-		} \
+#define MAX17055_WRITE_DEBUG(offset, reg)                                \
+	do {                                                             \
+		if (max17055_write(offset, reg)) {                       \
+			CPRINTS("%s: failed to read reg %02x", __func__, \
+				offset);                                 \
+			return;                                          \
+		}                                                        \
 	} while (0)
 
 static int fake_state_of_charge = -1;
 
 static int max17055_read(int offset, int *data)
 {
-	return i2c_read16(I2C_PORT_BATTERY, MAX17055_ADDR_FLAGS,
-			  offset, data);
+	return i2c_read16(I2C_PORT_BATTERY, MAX17055_ADDR_FLAGS, offset, data);
 }
 
 static int max17055_write(int offset, int data)
 {
-	return i2c_write16(I2C_PORT_BATTERY, MAX17055_ADDR_FLAGS,
-			   offset, data);
+	return i2c_write16(I2C_PORT_BATTERY, MAX17055_ADDR_FLAGS, offset, data);
 }
 
 /* Return 1 if the device id is correct. */
@@ -94,10 +93,13 @@ int battery_device_name(char *device_name, int buf_size)
 	int rv;
 
 	rv = max17055_read(REG_DEVICE_NAME, &dev_id);
-	if (!rv)
-		snprintf(device_name, buf_size, "0x%04x", dev_id);
+	if (rv != EC_SUCCESS)
+		return rv;
 
-	return rv;
+	if (snprintf(device_name, buf_size, "0x%04x", dev_id) <= 0)
+		return EC_ERROR_UNKNOWN;
+
+	return EC_SUCCESS;
 }
 
 int battery_state_of_charge_abs(int *percent)
@@ -269,7 +271,7 @@ enum battery_present battery_is_present(void)
 void battery_get_params(struct batt_params *batt)
 {
 	int reg = 0;
-	struct batt_params batt_new = {0};
+	struct batt_params batt_new = { 0 };
 
 	/*
 	 * Assuming the battery is responsive as long as
@@ -293,7 +295,8 @@ void battery_get_params(struct batt_params *batt)
 		batt_new.flags |= BATT_FLAG_BAD_STATE_OF_CHARGE;
 
 	batt_new.state_of_charge = fake_state_of_charge >= 0 ?
-				fake_state_of_charge : PERCENTAGE_CONV(reg);
+					   fake_state_of_charge :
+					   PERCENTAGE_CONV(reg);
 
 	if (max17055_read(REG_VOLTAGE, &reg))
 		batt_new.flags |= BATT_FLAG_BAD_VOLTAGE;
@@ -319,8 +322,7 @@ void battery_get_params(struct batt_params *batt)
 	 * and battery isn't full (and we read them all correctly).
 	 */
 	if (!(batt_new.flags & BATT_FLAG_BAD_STATE_OF_CHARGE) &&
-	    batt_new.desired_voltage &&
-	    batt_new.desired_current &&
+	    batt_new.desired_voltage && batt_new.desired_current &&
 	    batt_new.state_of_charge < BATTERY_LEVEL_FULL)
 		batt_new.flags |= BATT_FLAG_WANT_CHARGE;
 
diff --git a/driver/battery/max17055.h b/driver/battery/max17055.h
index 0f97fb90f0..6828ed6502 100644
--- a/driver/battery/max17055.h
+++ b/driver/battery/max17055.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,105 +8,105 @@
 #ifndef __CROS_EC_MAX17055_H
 #define __CROS_EC_MAX17055_H
 
-#define MAX17055_ADDR_FLAGS         0x36
-#define MAX17055_DEVICE_ID          0x4010
-#define MAX17055_OCV_TABLE_SIZE     48
-
-#define REG_STATUS                  0x00
-#define REG_VALRTTH                 0x01
-#define REG_TALRTTH                 0x02
-#define REG_SALRTTH                 0x03
-#define REG_AT_RATE                 0x04
-#define REG_REMAINING_CAPACITY      0x05
-#define REG_STATE_OF_CHARGE         0x06
-#define REG_TEMPERATURE             0x08
-#define REG_VOLTAGE                 0x09
-#define REG_CURRENT                 0x0a
-#define REG_AVERAGE_CURRENT         0x0b
-#define REG_MIXCAP                  0x0f
-#define REG_FULL_CHARGE_CAPACITY    0x10
-#define REG_TIME_TO_EMPTY           0x11
-#define REG_QR_TABLE00              0x12
-#define REG_CONFIG                  0x1D
-#define REG_AVERAGE_TEMPERATURE     0x16
-#define REG_CYCLE_COUNT             0x17
-#define REG_DESIGN_CAPACITY         0x18
-#define REG_AVERAGE_VOLTAGE         0x19
-#define REG_MAX_MIN_TEMP            0x1a
-#define REG_MAX_MIN_VOLT            0x1b
-#define REG_MAX_MIN_CURR            0x1c
-#define REG_CHARGE_TERM_CURRENT     0x1e
-#define REG_TIME_TO_FULL            0x20
-#define REG_DEVICE_NAME             0x21
-#define REG_QR_TABLE10              0x22
-#define REG_FULLCAPNOM              0x23
-#define REG_LEARNCFG                0x28
-#define REG_QR_TABLE20              0x32
-#define REG_RCOMP0                  0x38
-#define REG_TEMPCO                  0x39
-#define REG_EMPTY_VOLTAGE           0x3a
-#define REG_FSTAT                   0x3d
-#define REG_TIMER                   0x3e
-#define REG_QR_TABLE30              0x42
-#define REG_DQACC                   0x45
-#define REG_DPACC                   0x46
-#define REG_VFSOC0                  0x48
-#define REG_COMMAND                 0x60
-#define REG_LOCK1                   0x62
-#define REG_LOCK2                   0x63
-#define REG_OCV_TABLE_START         0x80
-#define REG_STATUS2                 0xb0
-#define REG_IALRTTH                 0xb4
-#define REG_HIBCFG                  0xba
-#define REG_CONFIG2                 0xbb
-#define REG_TIMERH                  0xbe
-#define REG_MODELCFG                0xdb
-#define REG_VFSOC                   0xff
+#define MAX17055_ADDR_FLAGS 0x36
+#define MAX17055_DEVICE_ID 0x4010
+#define MAX17055_OCV_TABLE_SIZE 48
+
+#define REG_STATUS 0x00
+#define REG_VALRTTH 0x01
+#define REG_TALRTTH 0x02
+#define REG_SALRTTH 0x03
+#define REG_AT_RATE 0x04
+#define REG_REMAINING_CAPACITY 0x05
+#define REG_STATE_OF_CHARGE 0x06
+#define REG_TEMPERATURE 0x08
+#define REG_VOLTAGE 0x09
+#define REG_CURRENT 0x0a
+#define REG_AVERAGE_CURRENT 0x0b
+#define REG_MIXCAP 0x0f
+#define REG_FULL_CHARGE_CAPACITY 0x10
+#define REG_TIME_TO_EMPTY 0x11
+#define REG_QR_TABLE00 0x12
+#define REG_CONFIG 0x1D
+#define REG_AVERAGE_TEMPERATURE 0x16
+#define REG_CYCLE_COUNT 0x17
+#define REG_DESIGN_CAPACITY 0x18
+#define REG_AVERAGE_VOLTAGE 0x19
+#define REG_MAX_MIN_TEMP 0x1a
+#define REG_MAX_MIN_VOLT 0x1b
+#define REG_MAX_MIN_CURR 0x1c
+#define REG_CHARGE_TERM_CURRENT 0x1e
+#define REG_TIME_TO_FULL 0x20
+#define REG_DEVICE_NAME 0x21
+#define REG_QR_TABLE10 0x22
+#define REG_FULLCAPNOM 0x23
+#define REG_LEARNCFG 0x28
+#define REG_QR_TABLE20 0x32
+#define REG_RCOMP0 0x38
+#define REG_TEMPCO 0x39
+#define REG_EMPTY_VOLTAGE 0x3a
+#define REG_FSTAT 0x3d
+#define REG_TIMER 0x3e
+#define REG_QR_TABLE30 0x42
+#define REG_DQACC 0x45
+#define REG_DPACC 0x46
+#define REG_VFSOC0 0x48
+#define REG_COMMAND 0x60
+#define REG_LOCK1 0x62
+#define REG_LOCK2 0x63
+#define REG_OCV_TABLE_START 0x80
+#define REG_STATUS2 0xb0
+#define REG_IALRTTH 0xb4
+#define REG_HIBCFG 0xba
+#define REG_CONFIG2 0xbb
+#define REG_TIMERH 0xbe
+#define REG_MODELCFG 0xdb
+#define REG_VFSOC 0xff
 
 /* Status reg (0x00) flags */
-#define STATUS_POR                  BIT(1)
-#define STATUS_IMN                  BIT(2)
-#define STATUS_BST                  BIT(3)
-#define STATUS_IMX                  BIT(6)
-#define STATUS_VMN                  BIT(8)
-#define STATUS_TMN                  BIT(9)
-#define STATUS_SMN                  BIT(10)
-#define STATUS_VMX                  BIT(12)
-#define STATUS_TMX                  BIT(13)
-#define STATUS_SMX                  BIT(14)
-#define STATUS_ALL_ALRT                                                        \
-	(STATUS_IMN | STATUS_IMX | STATUS_VMN | STATUS_VMX | STATUS_TMN |      \
+#define STATUS_POR BIT(1)
+#define STATUS_IMN BIT(2)
+#define STATUS_BST BIT(3)
+#define STATUS_IMX BIT(6)
+#define STATUS_VMN BIT(8)
+#define STATUS_TMN BIT(9)
+#define STATUS_SMN BIT(10)
+#define STATUS_VMX BIT(12)
+#define STATUS_TMX BIT(13)
+#define STATUS_SMX BIT(14)
+#define STATUS_ALL_ALRT                                                   \
+	(STATUS_IMN | STATUS_IMX | STATUS_VMN | STATUS_VMX | STATUS_TMN | \
 	 STATUS_TMX | STATUS_SMN | STATUS_SMX)
 
 /* Alert disable values (0x01, 0x02, 0x03, 0xb4) */
-#define VALRT_DISABLE               0xff00
-#define TALRT_DISABLE               0x7f80
-#define SALRT_DISABLE               0xff00
-#define IALRT_DISABLE               0x7f80
+#define VALRT_DISABLE 0xff00
+#define TALRT_DISABLE 0x7f80
+#define SALRT_DISABLE 0xff00
+#define IALRT_DISABLE 0x7f80
 
 /* Config reg (0x1d) flags */
-#define CONF_AEN                    BIT(2)
-#define CONF_IS                     BIT(11)
-#define CONF_VS                     BIT(12)
-#define CONF_TS                     BIT(13)
-#define CONF_SS                     BIT(14)
-#define CONF_TSEL                   BIT(15)
-#define CONF_ALL_STICKY             (CONF_IS | CONF_VS | CONF_TS | CONF_SS)
+#define CONF_AEN BIT(2)
+#define CONF_IS BIT(11)
+#define CONF_VS BIT(12)
+#define CONF_TS BIT(13)
+#define CONF_SS BIT(14)
+#define CONF_TSEL BIT(15)
+#define CONF_ALL_STICKY (CONF_IS | CONF_VS | CONF_TS | CONF_SS)
 
 /* FStat reg (0x3d) flags */
-#define FSTAT_DNR                   0x0001
-#define FSTAT_FQ                    0x0080
+#define FSTAT_DNR 0x0001
+#define FSTAT_FQ 0x0080
 
 /* Config2 reg (0xbb) flags */
-#define CONFIG2_LDMDL               BIT(5)
+#define CONFIG2_LDMDL BIT(5)
 
 /* ModelCfg reg (0xdb) flags */
-#define MODELCFG_REFRESH            BIT(15)
-#define MODELCFG_VCHG               BIT(10)
+#define MODELCFG_REFRESH BIT(15)
+#define MODELCFG_VCHG BIT(10)
 
 /* Smart battery status bits (sbs reg 0x16) */
-#define BATTERY_DISCHARGING         0x40
-#define BATTERY_FULLY_CHARGED       0x20
+#define BATTERY_DISCHARGING 0x40
+#define BATTERY_FULLY_CHARGED 0x20
 
 /*
  * Before we have the battery fully characterized, we use these macros to
@@ -125,28 +125,27 @@
  * VE. max17055 reenables empty detection when the cell voltage rises above VR.
  * VE ranges from 0 to 5110mV, and VR ranges from 0 to 5080mV.
  */
-#define MAX17055_VEMPTY_REG(ve_mv, vr_mv) \
-	(((ve_mv / 10) << 7) | (vr_mv / 40))
+#define MAX17055_VEMPTY_REG(ve_mv, vr_mv) (((ve_mv / 10) << 7) | (vr_mv / 40))
 
 #define MAX17055_MAX_MIN_REG(mx, mn) ((((int16_t)(mx)) << 8) | ((mn)))
 /* Converts voltages alert range for VALRTTH_REG */
 #define MAX17055_VALRTTH_RESOLUTION 20
-#define MAX17055_VALRTTH_REG(mx, mn)                                           \
-	MAX17055_MAX_MIN_REG((uint8_t)(mx / MAX17055_VALRTTH_RESOLUTION),      \
+#define MAX17055_VALRTTH_REG(mx, mn)                                      \
+	MAX17055_MAX_MIN_REG((uint8_t)(mx / MAX17055_VALRTTH_RESOLUTION), \
 			     (uint8_t)(mn / MAX17055_VALRTTH_RESOLUTION))
 /* Converts temperature alert range for TALRTTH_REG */
-#define MAX17055_TALRTTH_REG(mx, mn)                                           \
+#define MAX17055_TALRTTH_REG(mx, mn) \
 	MAX17055_MAX_MIN_REG((int8_t)(mx), (int8_t)(mn))
 /* Converts state-of-charge alert range for SALRTTH_REG */
-#define MAX17055_SALRTTH_REG(mx, mn)                                           \
+#define MAX17055_SALRTTH_REG(mx, mn) \
 	MAX17055_MAX_MIN_REG((uint8_t)(mx), (uint8_t)(mn))
 /* Converts current alert range for IALRTTH_REG */
 /* Current resolution: 0.4mV/RSENSE */
 #define MAX17055_IALRTTH_MUL (10 * BATTERY_MAX17055_RSENSE)
 #define MAX17055_IALRTTH_DIV 4
-#define MAX17055_IALRTTH_REG(mx, mn)                                           \
-	MAX17055_MAX_MIN_REG(                                                  \
-		(int8_t)(mx * MAX17055_IALRTTH_MUL / MAX17055_IALRTTH_DIV),    \
+#define MAX17055_IALRTTH_REG(mx, mn)                                        \
+	MAX17055_MAX_MIN_REG(                                               \
+		(int8_t)(mx * MAX17055_IALRTTH_MUL / MAX17055_IALRTTH_DIV), \
 		(int8_t)(mn * MAX17055_IALRTTH_MUL / MAX17055_IALRTTH_DIV))
 
 /*
diff --git a/driver/battery/mm8013.c b/driver/battery/mm8013.c
index 04503da2f5..5d9f6e7a8d 100644
--- a/driver/battery/mm8013.c
+++ b/driver/battery/mm8013.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -34,8 +34,8 @@ static int mm8013_read_block(int offset, uint8_t *data, int len)
 {
 	int rv;
 
-	rv = i2c_read_block(I2C_PORT_BATTERY, MM8013_ADDR_FLAGS,
-			    offset, data, len);
+	rv = i2c_read_block(I2C_PORT_BATTERY, MM8013_ADDR_FLAGS, offset, data,
+			    len);
 	usleep(I2C_WAIT_TIME);
 	if (rv)
 		return rv;
@@ -52,8 +52,8 @@ static int battery_current(int *current)
 	int16_t tmp;
 	int rv;
 
-	rv = mm8013_read_block(REG_AVERAGE_CURRENT,
-			(uint8_t *)&tmp, sizeof(int16_t));
+	rv = mm8013_read_block(REG_AVERAGE_CURRENT, (uint8_t *)&tmp,
+			       sizeof(int16_t));
 	if (rv)
 		return rv;
 	*current = tmp;
@@ -66,8 +66,8 @@ int battery_device_name(char *device_name, int buf_size)
 	int rv;
 	char out_buf[BATTERY_PACK_INFO_LENGTH + 1];
 
-	rv = mm8013_read_block(REG_PRODUCT_INFORMATION,
-			(uint8_t *)out_buf, BATTERY_PACK_INFO_LENGTH);
+	rv = mm8013_read_block(REG_PRODUCT_INFORMATION, (uint8_t *)out_buf,
+			       BATTERY_PACK_INFO_LENGTH);
 	if (rv)
 		return rv;
 
@@ -181,7 +181,7 @@ enum battery_present battery_is_present(void)
 
 void battery_get_params(struct batt_params *batt)
 {
-	struct batt_params batt_new = {0};
+	struct batt_params batt_new = { 0 };
 	int flag = 0;
 
 	/*
diff --git a/driver/battery/mm8013.h b/driver/battery/mm8013.h
index 2ffaca7b5d..40cb31a355 100644
--- a/driver/battery/mm8013.h
+++ b/driver/battery/mm8013.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,33 +8,32 @@
 #ifndef __CROS_EC_MM8013_H
 #define __CROS_EC_MM8013_H
 
-#define MM8013_ADDR_FLAGS           0x55
+#define MM8013_ADDR_FLAGS 0x55
 
-#define REG_TEMPERATURE             0x06
-#define REG_VOLTAGE                 0x08
-#define REG_FLAGS                   0x0a
-#define REG_FULL_CHARGE_CAPACITY    0x0e
-#define REG_REMAINING_CAPACITY      0x10
-#define REG_AVERAGE_CURRENT         0x14
-#define REG_AVERAGE_TIME_TO_EMPTY   0x16
-#define REG_AVERAGE_TIME_TO_FULL    0x18
-#define REG_STATE_OF_CHARGE         0x2c
-#define REG_CYCLE_COUNT             0x2a
-#define REG_DESIGN_CAPACITY         0x3c
-#define REG_PRODUCT_INFORMATION     0x64
+#define REG_TEMPERATURE 0x06
+#define REG_VOLTAGE 0x08
+#define REG_FLAGS 0x0a
+#define REG_FULL_CHARGE_CAPACITY 0x0e
+#define REG_REMAINING_CAPACITY 0x10
+#define REG_AVERAGE_CURRENT 0x14
+#define REG_AVERAGE_TIME_TO_EMPTY 0x16
+#define REG_AVERAGE_TIME_TO_FULL 0x18
+#define REG_STATE_OF_CHARGE 0x2c
+#define REG_CYCLE_COUNT 0x2a
+#define REG_DESIGN_CAPACITY 0x3c
+#define REG_PRODUCT_INFORMATION 0x64
 
 /* Over Temperature in charge */
-#define MM8013_FLAG_OTC             BIT(15)
+#define MM8013_FLAG_OTC BIT(15)
 /* Over Temperature in discharge */
-#define MM8013_FLAG_OTD             BIT(14)
+#define MM8013_FLAG_OTD BIT(14)
 /* Over-charge */
-#define MM8013_FLAG_BATHI           BIT(13)
+#define MM8013_FLAG_BATHI BIT(13)
 /* Full Charge */
-#define MM8013_FLAG_FC              BIT(9)
+#define MM8013_FLAG_FC BIT(9)
 /* Charge allowed */
-#define MM8013_FLAG_CHG             BIT(8)
+#define MM8013_FLAG_CHG BIT(8)
 /* Discharge */
-#define MM8013_FLAG_DSG             BIT(0)
-
+#define MM8013_FLAG_DSG BIT(0)
 
 #endif /* __CROS_EC_MM8013_H */
diff --git a/driver/battery/smart.c b/driver/battery/smart.c
index c87a1a6cdc..0a6cd145f3 100644
--- a/driver/battery/smart.c
+++ b/driver/battery/smart.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -15,9 +15,9 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CHARGER, outstr);
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
-#define BATTERY_NO_RESPONSE_TIMEOUT	(1000*MSEC)
+#define BATTERY_NO_RESPONSE_TIMEOUT (1000 * MSEC)
 
 static int fake_state_of_charge = -1;
 static int fake_temperature = -1;
@@ -92,8 +92,7 @@ int sb_read_string(int offset, uint8_t *data, int len)
 	if (battery_supports_pec())
 		addr_flags |= I2C_FLAG_PEC;
 
-	return i2c_read_string(I2C_PORT_BATTERY, addr_flags, offset, data,
-			       len);
+	return i2c_read_string(I2C_PORT_BATTERY, addr_flags, offset, data, len);
 }
 
 int sb_read_sized_block(int offset, uint8_t *data, int len)
@@ -315,12 +314,12 @@ test_mockable int battery_manufacture_date(int *year, int *month, int *day)
 	/* battery date format:
 	 * ymd = day + month * 32 + (year - 1980) * 512
 	 */
-	*year  = ((ymd & MANUFACTURE_DATE_YEAR_MASK) >>
-		  MANUFACTURE_DATE_YEAR_SHIFT) + MANUFACTURE_DATE_YEAR_OFFSET;
+	*year = ((ymd & MANUFACTURE_DATE_YEAR_MASK) >>
+		 MANUFACTURE_DATE_YEAR_SHIFT) +
+		MANUFACTURE_DATE_YEAR_OFFSET;
 	*month = (ymd & MANUFACTURE_DATE_MONTH_MASK) >>
 		 MANUFACTURE_DATE_MONTH_SHIFT;
-	*day   = (ymd & MANUFACTURE_DATE_DAY_MASK) >>
-		 MANUFACTURE_DATE_DAY_SHIFT;
+	*day = (ymd & MANUFACTURE_DATE_DAY_MASK) >> MANUFACTURE_DATE_DAY_SHIFT;
 
 	return EC_SUCCESS;
 }
@@ -408,16 +407,16 @@ void battery_get_params(struct batt_params *batt)
 	memcpy(&batt_new, batt, sizeof(*batt));
 	batt_new.flags = 0;
 
-	if (sb_read(SB_TEMPERATURE, &batt_new.temperature)
-			&& fake_temperature < 0)
+	if (sb_read(SB_TEMPERATURE, &batt_new.temperature) &&
+	    fake_temperature < 0)
 		batt_new.flags |= BATT_FLAG_BAD_TEMPERATURE;
 
 	/* If temperature is faked, override with faked data */
 	if (fake_temperature >= 0)
 		batt_new.temperature = fake_temperature;
 
-	if (sb_read(SB_RELATIVE_STATE_OF_CHARGE, &batt_new.state_of_charge)
-	    && fake_state_of_charge < 0)
+	if (sb_read(SB_RELATIVE_STATE_OF_CHARGE, &batt_new.state_of_charge) &&
+	    fake_state_of_charge < 0)
 		batt_new.flags |= BATT_FLAG_BAD_STATE_OF_CHARGE;
 
 	if (sb_read(SB_VOLTAGE, &batt_new.voltage))
@@ -455,7 +454,7 @@ void battery_get_params(struct batt_params *batt)
 		batt_new.flags |= BATT_FLAG_IMBALANCED_CELL;
 #endif
 
-#if defined(CONFIG_BATTERY_PRESENT_CUSTOM) ||	\
+#if defined(CONFIG_BATTERY_PRESENT_CUSTOM) || \
 	defined(CONFIG_BATTERY_PRESENT_GPIO)
 	/* Hardware can tell us for certain */
 	batt_new.is_present = battery_is_present();
@@ -471,23 +470,20 @@ void battery_get_params(struct batt_params *batt)
 	 * Charging allowed if both desired voltage and current are nonzero
 	 * and battery isn't full (and we read them all correctly).
 	 */
-	if (!(batt_new.flags & (BATT_FLAG_BAD_DESIRED_VOLTAGE |
-				BATT_FLAG_BAD_DESIRED_CURRENT |
-				BATT_FLAG_BAD_STATE_OF_CHARGE)) &&
+	if (!(batt_new.flags &
+	      (BATT_FLAG_BAD_DESIRED_VOLTAGE | BATT_FLAG_BAD_DESIRED_CURRENT |
+	       BATT_FLAG_BAD_STATE_OF_CHARGE)) &&
 #ifdef CONFIG_BATTERY_REQUESTS_NIL_WHEN_DEAD
-		/*
-		 * TODO (crosbug.com/p/29467): remove this workaround
-		 * for dead battery that requests no voltage/current
-		 */
-		((batt_new.desired_voltage &&
-			batt_new.desired_current &&
-			batt_new.state_of_charge < BATTERY_LEVEL_FULL) ||
-		(batt_new.desired_voltage == 0 &&
-			batt_new.desired_current == 0 &&
-			batt_new.state_of_charge == 0)))
+	    /*
+	     * TODO (crosbug.com/p/29467): remove this workaround
+	     * for dead battery that requests no voltage/current
+	     */
+	    ((batt_new.desired_voltage && batt_new.desired_current &&
+	      batt_new.state_of_charge < BATTERY_LEVEL_FULL) ||
+	     (batt_new.desired_voltage == 0 && batt_new.desired_current == 0 &&
+	      batt_new.state_of_charge == 0)))
 #else
-	    batt_new.desired_voltage &&
-	    batt_new.desired_current &&
+	    batt_new.desired_voltage && batt_new.desired_current &&
 	    batt_new.state_of_charge < BATTERY_LEVEL_FULL)
 #endif
 		batt_new.flags |= BATT_FLAG_WANT_CHARGE;
@@ -515,7 +511,7 @@ int battery_wait_for_stable(void)
 	uint64_t wait_timeout = get_time().val + BATTERY_NO_RESPONSE_TIMEOUT;
 
 	CPRINTS("Wait for battery stabilized during %d",
-			 BATTERY_NO_RESPONSE_TIMEOUT);
+		BATTERY_NO_RESPONSE_TIMEOUT);
 	while (get_time().val < wait_timeout) {
 		/* Starting pinging battery */
 		if (battery_status(&status) == EC_SUCCESS) {
@@ -530,7 +526,7 @@ int battery_wait_for_stable(void)
 }
 
 #if defined(CONFIG_CMD_BATTFAKE)
-static int command_battfake(int argc, char **argv)
+static int command_battfake(int argc, const char **argv)
 {
 	char *e;
 	int v;
@@ -552,7 +548,7 @@ DECLARE_CONSOLE_COMMAND(battfake, command_battfake,
 			"percent (-1 = use real level)",
 			"Set fake battery level");
 
-static int command_batttempfake(int argc, char **argv)
+static int command_batttempfake(int argc, const char **argv)
 {
 	char *e;
 	int t;
@@ -571,13 +567,14 @@ static int command_batttempfake(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(batttempfake, command_batttempfake,
-			"temperature (-1 = use real temperature)",
-			"Set fake battery temperature in deciKelvin (2731 = 273.1 K = 0 deg C)");
+DECLARE_CONSOLE_COMMAND(
+	batttempfake, command_batttempfake,
+	"temperature (-1 = use real temperature)",
+	"Set fake battery temperature in deciKelvin (2731 = 273.1 K = 0 deg C)");
 #endif
 
 #ifdef CONFIG_CMD_BATT_MFG_ACCESS
-static int command_batt_mfg_access_read(int argc, char **argv)
+static int command_batt_mfg_access_read(int argc, const char **argv)
 {
 	char *e;
 	uint8_t data[32];
@@ -643,8 +640,7 @@ host_command_sb_read_word(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_SB_READ_WORD,
-		     host_command_sb_read_word,
+DECLARE_HOST_COMMAND(EC_CMD_SB_READ_WORD, host_command_sb_read_word,
 		     EC_VER_MASK(0));
 
 static enum ec_status
@@ -661,8 +657,7 @@ host_command_sb_write_word(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_SB_WRITE_WORD,
-		     host_command_sb_write_word,
+DECLARE_HOST_COMMAND(EC_CMD_SB_WRITE_WORD, host_command_sb_write_word,
 		     EC_VER_MASK(0));
 
 static enum ec_status
@@ -672,10 +667,8 @@ host_command_sb_read_block(struct host_cmd_handler_args *args)
 	const struct ec_params_sb_rd *p = args->params;
 	struct ec_response_sb_rd_block *r = args->response;
 
-	if ((p->reg != SB_MANUFACTURER_NAME) &&
-	    (p->reg != SB_DEVICE_NAME) &&
-	    (p->reg != SB_DEVICE_CHEMISTRY) &&
-	    (p->reg != SB_MANUFACTURER_DATA))
+	if ((p->reg != SB_MANUFACTURER_NAME) && (p->reg != SB_DEVICE_NAME) &&
+	    (p->reg != SB_DEVICE_CHEMISTRY) && (p->reg != SB_MANUFACTURER_DATA))
 		return EC_RES_INVALID_PARAM;
 	rv = sb_read_string(p->reg, r->data, 32);
 	if (rv)
@@ -685,8 +678,7 @@ host_command_sb_read_block(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_SB_READ_BLOCK,
-		     host_command_sb_read_block,
+DECLARE_HOST_COMMAND(EC_CMD_SB_READ_BLOCK, host_command_sb_read_block,
 		     EC_VER_MASK(0));
 
 static enum ec_status
@@ -695,8 +687,7 @@ host_command_sb_write_block(struct host_cmd_handler_args *args)
 	/* Not implemented */
 	return EC_RES_INVALID_COMMAND;
 }
-DECLARE_HOST_COMMAND(EC_CMD_SB_WRITE_BLOCK,
-		     host_command_sb_write_block,
+DECLARE_HOST_COMMAND(EC_CMD_SB_WRITE_BLOCK, host_command_sb_write_block,
 		     EC_VER_MASK(0));
 #endif
 
@@ -707,8 +698,8 @@ test_mockable int sb_i2c_test_read(int cmd, int *param)
 	int rv;
 
 	if (cmd == SB_DEVICE_CHEMISTRY) {
-		rv = battery_device_chemistry(chemistry,
-			sizeof(CONFIG_BATTERY_DEVICE_CHEMISTRY));
+		rv = battery_device_chemistry(
+			chemistry, sizeof(CONFIG_BATTERY_DEVICE_CHEMISTRY));
 		if (rv)
 			return rv;
 		if (strcasecmp(chemistry, CONFIG_BATTERY_DEVICE_CHEMISTRY))
@@ -718,7 +709,6 @@ test_mockable int sb_i2c_test_read(int cmd, int *param)
 		return EC_SUCCESS;
 	}
 
-
 	return sb_read(cmd, param);
 }
 
diff --git a/driver/bc12/max14637.c b/driver/bc12/max14637.c
index 4c7cbffd18..09fa009c45 100644
--- a/driver/bc12/max14637.c
+++ b/driver/bc12/max14637.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,6 +12,7 @@
  * the system will have to charge ramp.
  */
 
+#include "builtin/assert.h"
 #include "max14637.h"
 #include "charge_manager.h"
 #include "chipset.h"
@@ -28,7 +29,7 @@
 #include "usb_pd.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 #if defined(CONFIG_CHARGE_RAMP_SW) || defined(CONFIG_CHARGE_RAMP_HW)
 /**
@@ -38,10 +39,10 @@
  * @return 1 if charger detect is activated (high when active high or
  *	low with active low), otherwise 0.
  */
-static int is_chg_det_activated(const struct max14637_config_t * const cfg)
+static int is_chg_det_activated(const struct max14637_config_t *const cfg)
 {
 	return !!gpio_get_level(cfg->chg_det_pin) ^
-		!!(cfg->flags & MAX14637_FLAGS_CHG_DET_ACTIVE_LOW);
+	       !!(cfg->flags & MAX14637_FLAGS_CHG_DET_ACTIVE_LOW);
 }
 #endif
 
@@ -52,12 +53,12 @@ static int is_chg_det_activated(const struct max14637_config_t * const cfg)
  * @param enable 1 to activate gpio (high for active high and low for active
  *	low).
  */
-static void activate_chip_enable(
-	const struct max14637_config_t * const cfg, const int enable)
+static void activate_chip_enable(const struct max14637_config_t *const cfg,
+				 const int enable)
 {
-	gpio_set_level(
-		cfg->chip_enable_pin,
-		!!enable ^ !!(cfg->flags & MAX14637_FLAGS_ENABLE_ACTIVE_LOW));
+	gpio_set_level(cfg->chip_enable_pin,
+		       !!enable ^ !!(cfg->flags &
+				     MAX14637_FLAGS_ENABLE_ACTIVE_LOW));
 }
 
 /**
@@ -67,7 +68,7 @@ static void activate_chip_enable(
  */
 static void update_bc12_status_to_charger_manager(const int port)
 {
-	const struct max14637_config_t * const cfg = &max14637_config[port];
+	const struct max14637_config_t *const cfg = &max14637_config[port];
 	struct charge_port_info new_chg;
 
 	new_chg.voltage = USB_CHARGER_VOLTAGE_MV;
@@ -100,7 +101,7 @@ static void update_bc12_status_to_charger_manager(const int port)
  */
 static void bc12_detect(const int port)
 {
-	const struct max14637_config_t * const cfg = &max14637_config[port];
+	const struct max14637_config_t *const cfg = &max14637_config[port];
 
 	/*
 	 * Enable the IC to begin detection and connect switches if
@@ -176,7 +177,7 @@ static void detect_or_power_down_ic(const int port)
 
 static void max14637_usb_charger_task_init(const int port)
 {
-	const struct max14637_config_t * const cfg = &max14637_config[port];
+	const struct max14637_config_t *const cfg = &max14637_config[port];
 
 	ASSERT(port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	/*
diff --git a/driver/bc12/max14637.h b/driver/bc12/max14637.h
index 2b18bc222b..119437d9da 100644
--- a/driver/bc12/max14637.h
+++ b/driver/bc12/max14637.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,8 +7,8 @@
 
 #include "gpio.h"
 
-#define MAX14637_FLAGS_ENABLE_ACTIVE_LOW		BIT(0)
-#define MAX14637_FLAGS_CHG_DET_ACTIVE_LOW		BIT(1)
+#define MAX14637_FLAGS_ENABLE_ACTIVE_LOW BIT(0)
+#define MAX14637_FLAGS_CHG_DET_ACTIVE_LOW BIT(1)
 
 struct max14637_config_t {
 	/*
@@ -29,5 +29,5 @@ struct max14637_config_t {
  * Array that contains boards-specific configuration for BC 1.2 charging chips.
  */
 extern const struct max14637_config_t
-				max14637_config[CONFIG_USB_PD_PORT_MAX_COUNT];
+	max14637_config[CONFIG_USB_PD_PORT_MAX_COUNT];
 extern const struct bc12_drv max14637_drv;
diff --git a/driver/bc12/mt6360.c b/driver/bc12/mt6360.c
index 487883ec62..49ec031e09 100644
--- a/driver/bc12/mt6360.c
+++ b/driver/bc12/mt6360.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,20 +19,20 @@
 #include "util.h"
 
 /* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
 #define CPRINTS(format, args...) \
-	cprints(CC_USBCHARGE, "%s " format, "MT6360", ## args)
+	cprints(CC_USBCHARGE, "%s " format, "MT6360", ##args)
 
 static enum ec_error_list mt6360_read8(int reg, int *val)
 {
 	return i2c_read8(mt6360_config.i2c_port, mt6360_config.i2c_addr_flags,
-			reg, val);
+			 reg, val);
 }
 
 static enum ec_error_list mt6360_write8(int reg, int val)
 {
 	return i2c_write8(mt6360_config.i2c_port, mt6360_config.i2c_addr_flags,
-			reg, val);
+			  reg, val);
 }
 
 static int mt6360_update_bits(int reg, int mask, int val)
@@ -121,7 +121,7 @@ static void mt6360_update_charge_manager(int port,
 	if (new_bc12_type != current_bc12_type) {
 		if (current_bc12_type >= 0)
 			charge_manager_update_charge(current_bc12_type, port,
-							NULL);
+						     NULL);
 
 		if (new_bc12_type != CHARGE_SUPPLIER_NONE) {
 			struct charge_port_info chg = {
@@ -146,10 +146,9 @@ static void mt6360_handle_bc12_irq(int port)
 		/* Check vbus again to avoid timing issue */
 		if (pd_snk_is_vbus_provided(port))
 			mt6360_update_charge_manager(
-					port, mt6360_get_bc12_device_type());
+				port, mt6360_get_bc12_device_type());
 		else
-			mt6360_update_charge_manager(
-					0, CHARGE_SUPPLIER_NONE);
+			mt6360_update_charge_manager(0, CHARGE_SUPPLIER_NONE);
 	}
 
 	/* write clear */
@@ -168,9 +167,8 @@ static void mt6360_usb_charger_task_event(const int port, uint32_t evt)
 	/* vbus change, start bc12 detection */
 	if (evt & USB_CHG_EVENT_VBUS) {
 		bool is_sink = pd_get_power_role(port) == PD_ROLE_SINK;
-		bool is_non_pd_sink = !pd_capable(port) &&
-			is_sink &&
-			pd_snk_is_vbus_provided(port);
+		bool is_non_pd_sink = !pd_capable(port) && is_sink &&
+				      pd_snk_is_vbus_provided(port);
 
 		if (is_sink)
 			mt6360_clr_bit(MT6360_REG_CHG_CTRL1, MT6360_MASK_HZ);
@@ -197,15 +195,15 @@ static int mt6360_regulator_write8(uint8_t addr, int reg, int val)
 	 * Note: The checksum from I2C_FLAG_PEC happens to be correct because
 	 * length == 1 -> the high 3 bits of the offset byte is 0.
 	 */
-	return i2c_write8(mt6360_config.i2c_port,
-			  addr | I2C_FLAG_PEC, reg, val);
+	return i2c_write8(mt6360_config.i2c_port, addr | I2C_FLAG_PEC, reg,
+			  val);
 }
 
 static int mt6360_regulator_read8(int addr, int reg, int *val)
 {
 	int rv;
 	uint8_t crc = 0, real_crc;
-	uint8_t out[3] = {(addr << 1) | 1, reg};
+	uint8_t out[3] = { (addr << 1) | 1, reg };
 
 	rv = i2c_read16(mt6360_config.i2c_port, addr, reg, val);
 	if (rv)
@@ -262,22 +260,10 @@ static const uint16_t MT6360_LDO5_VOSEL_TABLE[8] = {
 };
 
 static const uint16_t MT6360_LDO6_VOSEL_TABLE[16] = {
-	[0x0] = 500,
-	[0x1] = 600,
-	[0x2] = 700,
-	[0x3] = 800,
-	[0x4] = 900,
-	[0x5] = 1000,
-	[0x6] = 1100,
-	[0x7] = 1200,
-	[0x8] = 1300,
-	[0x9] = 1400,
-	[0xA] = 1500,
-	[0xB] = 1600,
-	[0xC] = 1700,
-	[0xD] = 1800,
-	[0xE] = 1900,
-	[0xF] = 2000,
+	[0x0] = 500,  [0x1] = 600,  [0x2] = 700,  [0x3] = 800,
+	[0x4] = 900,  [0x5] = 1000, [0x6] = 1100, [0x7] = 1200,
+	[0x8] = 1300, [0x9] = 1400, [0xA] = 1500, [0xB] = 1600,
+	[0xC] = 1700, [0xD] = 1800, [0xE] = 1900, [0xF] = 2000,
 };
 
 /* LDO7 VOSEL table is the same as LDO6's. */
@@ -410,14 +396,12 @@ int mt6360_regulator_enable(enum mt6360_regulator_id id, uint8_t enable)
 
 	if (enable)
 		return mt6360_regulator_update_bits(
-			data->addr,
-			data->reg_en_ctrl2,
+			data->addr, data->reg_en_ctrl2,
 			MT6360_MASK_RGL_SW_OP_EN | MT6360_MASK_RGL_SW_EN,
 			MT6360_MASK_RGL_SW_OP_EN | MT6360_MASK_RGL_SW_EN);
 	else
 		return mt6360_regulator_update_bits(
-			data->addr,
-			data->reg_en_ctrl2,
+			data->addr, data->reg_en_ctrl2,
 			MT6360_MASK_RGL_SW_OP_EN | MT6360_MASK_RGL_SW_EN,
 			MT6360_MASK_RGL_SW_OP_EN);
 }
@@ -468,8 +452,7 @@ int mt6360_regulator_set_voltage(enum mt6360_regulator_id id, int min_mv,
 
 		step = (mv - MT6360_BUCK_VOSEL_MIN) / MT6360_BUCK_VOSEL_STEP_MV;
 
-		return mt6360_regulator_update_bits(data->addr,
-						    data->reg_ctrl3,
+		return mt6360_regulator_update_bits(data->addr, data->reg_ctrl3,
 						    data->mask_vosel, step);
 	}
 
@@ -489,8 +472,7 @@ int mt6360_regulator_set_voltage(enum mt6360_regulator_id id, int min_mv,
 		if (mv + step * MT6360_LDO_VOCAL_STEP_MV > max_mv)
 			continue;
 		return mt6360_regulator_update_bits(
-			data->addr,
-			data->reg_ctrl3,
+			data->addr, data->reg_ctrl3,
 			data->mask_vosel | data->mask_vocal,
 			(i << data->shift_vosel) | step);
 	}
diff --git a/driver/bc12/mt6360.h b/driver/bc12/mt6360.h
index 781bed2f57..85dab2b6ad 100644
--- a/driver/bc12/mt6360.h
+++ b/driver/bc12/mt6360.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/driver/bc12/pi3usb9201.c b/driver/bc12/pi3usb9201.c
index 9e60c9b4fd..e892c34e8c 100644
--- a/driver/bc12/pi3usb9201.c
+++ b/driver/bc12/pi3usb9201.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,7 +18,7 @@
 #include "usb_pd.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
 
 enum pi3usb9201_client_sts {
 	CHG_OTHER = 0,
@@ -45,21 +45,21 @@ static enum charge_supplier bc12_supplier[CONFIG_USB_PD_PORT_MAX_COUNT];
  * will continue to allow those.
  */
 static const struct bc12_status bc12_chg_limits[] = {
-	[CHG_OTHER] = {CHARGE_SUPPLIER_OTHER, 500},
-	[CHG_2_4A] = {CHARGE_SUPPLIER_PROPRIETARY, USB_CHARGER_MAX_CURR_MA},
-	[CHG_2_0A] = {CHARGE_SUPPLIER_PROPRIETARY, USB_CHARGER_MAX_CURR_MA},
-	[CHG_1_0A] = {CHARGE_SUPPLIER_PROPRIETARY, 1000},
-	[CHG_RESERVED] = {CHARGE_SUPPLIER_NONE, 0},
-	[CHG_CDP] = {CHARGE_SUPPLIER_BC12_CDP, USB_CHARGER_MAX_CURR_MA},
-	[CHG_SDP] = {CHARGE_SUPPLIER_BC12_SDP, 500},
-	[CHG_DCP] = {CHARGE_SUPPLIER_BC12_DCP, USB_CHARGER_MAX_CURR_MA},
+	[CHG_OTHER] = { CHARGE_SUPPLIER_OTHER, 500 },
+	[CHG_2_4A] = { CHARGE_SUPPLIER_PROPRIETARY, USB_CHARGER_MAX_CURR_MA },
+	[CHG_2_0A] = { CHARGE_SUPPLIER_PROPRIETARY, USB_CHARGER_MAX_CURR_MA },
+	[CHG_1_0A] = { CHARGE_SUPPLIER_PROPRIETARY, 1000 },
+	[CHG_RESERVED] = { CHARGE_SUPPLIER_NONE, 0 },
+	[CHG_CDP] = { CHARGE_SUPPLIER_BC12_CDP, USB_CHARGER_MAX_CURR_MA },
+	[CHG_SDP] = { CHARGE_SUPPLIER_BC12_SDP, 500 },
+	[CHG_DCP] = { CHARGE_SUPPLIER_BC12_DCP, USB_CHARGER_MAX_CURR_MA },
 };
 
 static inline int raw_read8(int port, int offset, int *value)
 {
 	return i2c_read8(pi3usb9201_bc12_chips[port].i2c_port,
-			 pi3usb9201_bc12_chips[port].i2c_addr_flags,
-			 offset, value);
+			 pi3usb9201_bc12_chips[port].i2c_addr_flags, offset,
+			 value);
 }
 
 static int pi3usb9201_raw(int port, int reg, int mask, int val)
@@ -73,8 +73,7 @@ static int pi3usb9201_raw(int port, int reg, int mask, int val)
 static int pi3usb9201_interrupt_mask(int port, int enable)
 {
 	return pi3usb9201_raw(port, PI3USB9201_REG_CTRL_1,
-			  PI3USB9201_REG_CTRL_1_INT_MASK,
-			  enable);
+			      PI3USB9201_REG_CTRL_1_INT_MASK, enable);
 }
 
 static int pi3usb9201_bc12_detect_ctrl(int port, int enable)
@@ -91,7 +90,7 @@ static int pi3usb9201_set_mode(int port, int desired_mode)
 			      desired_mode << PI3USB9201_REG_CTRL_1_MODE_SHIFT);
 }
 
-static int pi3usb9201_get_mode(int port, int *mode)
+static __maybe_unused int pi3usb9201_get_mode(int port, int *mode)
 {
 	int rv;
 
@@ -121,7 +120,7 @@ static int pi3usb9201_get_status(int port, int *client, int *host)
 }
 
 static void bc12_update_supplier(enum charge_supplier supplier, int port,
-			  struct charge_port_info *new_chg)
+				 struct charge_port_info *new_chg)
 {
 	/*
 	 * If most recent supplier type is not CHARGE_SUPPLIER_NONE, then the
@@ -155,8 +154,8 @@ static void bc12_update_charge_manager(int port, int client_status)
 	new_chg.current = bc12_chg_limits[bit_pos].current_limit;
 	supplier = bc12_chg_limits[bit_pos].supplier;
 
-	CPRINTS("pi3usb9201[p%d]: sts = 0x%x, lim = %d mA, supplier = %d",
-		port, client_status, new_chg.current, supplier);
+	CPRINTS("pi3usb9201[p%d]: sts = 0x%x, lim = %d mA, supplier = %d", port,
+		client_status, new_chg.current, supplier);
 	/* bc1.2 is complete and start bit does not auto clear */
 	pi3usb9201_bc12_detect_ctrl(port, 0);
 	/* Inform charge manager of new supplier type and current limit */
@@ -257,6 +256,9 @@ static void pi3usb9201_usb_charger_task_event(const int port, uint32_t evt)
 			 */
 			bc12_update_charge_manager(port, client);
 		if (!rv && host) {
+#ifdef CONFIG_BC12_CLIENT_MODE_ONLY_PI3USB9201
+			pi3usb9201_set_mode(port, PI3USB9201_USB_PATH_ON);
+#else
 			/*
 			 * Switch to SDP after device is plugged in to avoid
 			 * noise (pulse on D-) causing USB disconnect
@@ -272,6 +274,7 @@ static void pi3usb9201_usb_charger_task_event(const int port, uint32_t evt)
 			if (host & PI3USB9201_REG_HOST_STS_DEV_UNPLUG)
 				pi3usb9201_set_mode(port,
 						    PI3USB9201_CDP_HOST_MODE);
+#endif
 		}
 		/*
 		 * TODO(b/124061702): Use host status to allocate power more
@@ -281,8 +284,7 @@ static void pi3usb9201_usb_charger_task_event(const int port, uint32_t evt)
 
 	if (!IS_ENABLED(CONFIG_USB_PD_VBUS_DETECT_TCPC) &&
 	    (evt & USB_CHG_EVENT_VBUS))
-		CPRINTS("VBUS p%d %d", port,
-			pd_snk_is_vbus_provided(port));
+		CPRINTS("VBUS p%d %d", port, pd_snk_is_vbus_provided(port));
 
 	if (evt & USB_CHG_EVENT_DR_UFP) {
 		bc12_power_up(port);
@@ -298,14 +300,17 @@ static void pi3usb9201_usb_charger_task_event(const int port, uint32_t evt)
 			new_chg.voltage = USB_CHARGER_VOLTAGE_MV;
 			new_chg.current = USB_CHARGER_MIN_CURR_MA;
 			/* Save supplier type and notify chg manager */
-			bc12_update_supplier(CHARGE_SUPPLIER_OTHER,
-					     port, &new_chg);
+			bc12_update_supplier(CHARGE_SUPPLIER_OTHER, port,
+					     &new_chg);
 			CPRINTS("pi3usb9201[p%d]: bc1.2 failed use defaults",
 				port);
 		}
 	}
 
 	if (evt & USB_CHG_EVENT_DR_DFP) {
+#ifdef CONFIG_BC12_CLIENT_MODE_ONLY_PI3USB9201
+		pi3usb9201_set_mode(port, PI3USB9201_USB_PATH_ON);
+#else
 		int mode;
 		int rv;
 
@@ -335,6 +340,7 @@ static void pi3usb9201_usb_charger_task_event(const int port, uint32_t evt)
 			 */
 			pi3usb9201_interrupt_mask(port, 0);
 		}
+#endif
 	}
 
 	if (evt & USB_CHG_EVENT_CC_OPEN)
@@ -383,9 +389,8 @@ const struct bc12_drv pi3usb9201_drv = {
 
 #ifdef CONFIG_BC12_SINGLE_DRIVER
 /* provide a default bc12_ports[] for backward compatibility */
-struct bc12_config bc12_ports[CHARGE_PORT_COUNT] = {
-	[0 ... (CHARGE_PORT_COUNT - 1)] = {
-		.drv = &pi3usb9201_drv,
-	}
-};
+struct bc12_config
+	bc12_ports[CHARGE_PORT_COUNT] = { [0 ...(CHARGE_PORT_COUNT - 1)] = {
+						  .drv = &pi3usb9201_drv,
+					  } };
 #endif /* CONFIG_BC12_SINGLE_DRIVER */
diff --git a/driver/bc12/pi3usb9201.h b/driver/bc12/pi3usb9201.h
index 3163a3eebc..61728cce2a 100644
--- a/driver/bc12/pi3usb9201.h
+++ b/driver/bc12/pi3usb9201.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,8 +21,8 @@
 /* Control_1 regiter bit definitions */
 #define PI3USB9201_REG_CTRL_1_INT_MASK BIT(0)
 #define PI3USB9201_REG_CTRL_1_MODE_SHIFT 1
-#define PI3USB9201_REG_CTRL_1_MODE_MASK (0x7 << \
-					 PI3USB9201_REG_CTRL_1_MODE_SHIFT)
+#define PI3USB9201_REG_CTRL_1_MODE_MASK \
+	(0x7 << PI3USB9201_REG_CTRL_1_MODE_SHIFT)
 
 /* Control_2 regiter bit definitions */
 #define PI3USB9201_REG_CTRL_2_AUTO_SW BIT(1)
diff --git a/driver/bc12/pi3usb9281.c b/driver/bc12/pi3usb9281.c
index 3c3a0a7256..9e92d0f273 100644
--- a/driver/bc12/pi3usb9281.c
+++ b/driver/bc12/pi3usb9281.c
@@ -1,10 +1,11 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Pericom PI3USB3281 USB port switch driver.
  */
 
+#include "builtin/assert.h"
 #include "charge_manager.h"
 #include "common.h"
 #include "console.h"
@@ -19,9 +20,9 @@
 #include "usb_pd.h"
 #include "util.h"
 
- /* Console output macros */
+/* Console output macros */
 #define CPUTS(outstr) cputs(CC_USBCHARGE, outstr)
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
 
 /* I2C address */
 #define PI3USB9281_I2C_ADDR_FLAGS 0x25
@@ -30,10 +31,10 @@
 #define PI3USB9281_SW_RESET_DELAY 20
 
 /* Wait after a charger is detected to debounce pin contact order */
-#define PI3USB9281_DETECT_DEBOUNCE_MS			1000
-#define PI3USB9281_RESET_DEBOUNCE_MS			100
-#define PI3USB9281_RESET_STARTUP_DELAY			(200 * MSEC)
-#define PI3USB9281_RESET_STARTUP_DELAY_INTERVAL_MS	40
+#define PI3USB9281_DETECT_DEBOUNCE_MS 1000
+#define PI3USB9281_RESET_DEBOUNCE_MS 100
+#define PI3USB9281_RESET_STARTUP_DELAY (200 * MSEC)
+#define PI3USB9281_RESET_STARTUP_DELAY_INTERVAL_MS 40
 
 /* Store the state of our USB data switches so that they can be restored. */
 static int usb_switch_state[CONFIG_USB_PD_PORT_MAX_COUNT];
@@ -69,8 +70,7 @@ static uint8_t pi3usb9281_do_read(int port, uint8_t reg, int with_lock)
 	if (with_lock)
 		select_chip(port);
 
-	res = i2c_read8(chip->i2c_port, PI3USB9281_I2C_ADDR_FLAGS,
-			reg, &val);
+	res = i2c_read8(chip->i2c_port, PI3USB9281_I2C_ADDR_FLAGS, reg, &val);
 
 	if (with_lock)
 		unselect_chip(port);
@@ -91,8 +91,8 @@ static uint8_t pi3usb9281_read(int port, uint8_t reg)
 	return pi3usb9281_do_read(port, reg, 1);
 }
 
-static int pi3usb9281_do_write(
-	int port, uint8_t reg, uint8_t val, int with_lock)
+static int pi3usb9281_do_write(int port, uint8_t reg, uint8_t val,
+			       int with_lock)
 {
 	struct pi3usb9281_config *chip = &pi3usb9281_chips[port];
 	int res;
@@ -100,8 +100,7 @@ static int pi3usb9281_do_write(
 	if (with_lock)
 		select_chip(port);
 
-	res = i2c_write8(chip->i2c_port, PI3USB9281_I2C_ADDR_FLAGS,
-			 reg, val);
+	res = i2c_write8(chip->i2c_port, PI3USB9281_I2C_ADDR_FLAGS, reg, val);
 
 	if (with_lock)
 		unselect_chip(port);
@@ -120,8 +119,9 @@ static int pi3usb9281_write(int port, uint8_t reg, uint8_t val)
 static int pi3usb9281_do_write_ctrl(int port, uint8_t ctrl, int with_lock)
 {
 	return pi3usb9281_do_write(port, PI3USB9281_REG_CONTROL,
-				(ctrl & PI3USB9281_CTRL_MASK) |
-				PI3USB9281_CTRL_RSVD_1, with_lock);
+				   (ctrl & PI3USB9281_CTRL_MASK) |
+					   PI3USB9281_CTRL_RSVD_1,
+				   with_lock);
 }
 
 static int pi3usb9281_write_ctrl(int port, uint8_t ctrl)
@@ -156,7 +156,6 @@ static void pi3usb9281_init(int port)
 	pi3usb9281_enable_interrupts(port);
 }
 
-
 int pi3usb9281_enable_interrupts(int port)
 {
 	uint8_t ctrl;
@@ -297,7 +296,7 @@ static int pc3usb9281_read_interrupt(int port)
 	do {
 		/* Read (& clear) possible attach & detach interrupt */
 		if (pi3usb9281_get_interrupts(port) &
-				PI3USB9281_INT_ATTACH_DETACH)
+		    PI3USB9281_INT_ATTACH_DETACH)
 			return EC_SUCCESS;
 		msleep(PI3USB9281_RESET_STARTUP_DELAY_INTERVAL_MS);
 	} while (get_time().val < timeout.val);
@@ -418,7 +417,6 @@ static uint32_t bc12_detect(int port)
 
 static void pi3usb9281_usb_charger_task_event(const int port, uint32_t evt)
 {
-
 	/* Interrupt from the Pericom chip, determine charger type */
 	if (evt & USB_CHG_EVENT_BC12) {
 		/* Read interrupt register to clear on chip */
@@ -443,7 +441,8 @@ static void pi3usb9281_usb_charger_task_event(const int port, uint32_t evt)
 	if (evt & USB_CHG_EVENT_VBUS) {
 		pi3usb9281_enable_interrupts(port);
 		if (!IS_ENABLED(CONFIG_USB_PD_VBUS_DETECT_TCPC))
-		    CPRINTS("VBUS p%d %d", port, pd_snk_is_vbus_provided(port));
+			CPRINTS("VBUS p%d %d", port,
+				pd_snk_is_vbus_provided(port));
 	}
 }
 
diff --git a/driver/bc12/pi3usb9281.h b/driver/bc12/pi3usb9281.h
index ca1828f49c..7910502df8 100644
--- a/driver/bc12/pi3usb9281.h
+++ b/driver/bc12/pi3usb9281.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,55 +8,55 @@
 #ifndef __CROS_EC_PI3USB9281_H
 #define __CROS_EC_PI3USB9281_H
 
-#define PI3USB9281_REG_DEV_ID       0x01
-#define PI3USB9281_REG_CONTROL      0x02
-#define PI3USB9281_REG_INT          0x03
-#define PI3USB9281_REG_INT_MASK     0x05
-#define PI3USB9281_REG_DEV_TYPE     0x0a
-#define PI3USB9281_REG_CHG_STATUS   0x0e
-#define PI3USB9281_REG_MANUAL       0x13
-#define PI3USB9281_REG_RESET        0x1b
-#define PI3USB9281_REG_VBUS         0x1d
+#define PI3USB9281_REG_DEV_ID 0x01
+#define PI3USB9281_REG_CONTROL 0x02
+#define PI3USB9281_REG_INT 0x03
+#define PI3USB9281_REG_INT_MASK 0x05
+#define PI3USB9281_REG_DEV_TYPE 0x0a
+#define PI3USB9281_REG_CHG_STATUS 0x0e
+#define PI3USB9281_REG_MANUAL 0x13
+#define PI3USB9281_REG_RESET 0x1b
+#define PI3USB9281_REG_VBUS 0x1d
 
-#define PI3USB9281_DEV_ID           0x10
-#define PI3USB9281_DEV_ID_A         0x18
+#define PI3USB9281_DEV_ID 0x10
+#define PI3USB9281_DEV_ID_A 0x18
 
-#define PI3USB9281_CTRL_INT_DIS     BIT(0)
-#define PI3USB9281_CTRL_AUTO        BIT(2)
+#define PI3USB9281_CTRL_INT_DIS BIT(0)
+#define PI3USB9281_CTRL_AUTO BIT(2)
 #define PI3USB9281_CTRL_SWITCH_AUTO BIT(4)
 /* Bits 5 thru 7 are read X, write 0 */
-#define PI3USB9281_CTRL_MASK        0x1f
+#define PI3USB9281_CTRL_MASK 0x1f
 /* Bits 1 and 3 are read 1, write 1 */
-#define PI3USB9281_CTRL_RSVD_1      0x0a
+#define PI3USB9281_CTRL_RSVD_1 0x0a
 
-#define PI3USB9281_PIN_MANUAL_VBUS  (3 << 0)
-#define PI3USB9281_PIN_MANUAL_DP    BIT(2)
-#define PI3USB9281_PIN_MANUAL_DM    BIT(5)
+#define PI3USB9281_PIN_MANUAL_VBUS (3 << 0)
+#define PI3USB9281_PIN_MANUAL_DP BIT(2)
+#define PI3USB9281_PIN_MANUAL_DM BIT(5)
 
-#define PI3USB9281_INT_ATTACH       BIT(0)
-#define PI3USB9281_INT_DETACH       BIT(1)
-#define PI3USB9281_INT_OVP          BIT(5)
-#define PI3USB9281_INT_OCP          BIT(6)
-#define PI3USB9281_INT_OVP_OC       BIT(7)
-#define PI3USB9281_INT_ATTACH_DETACH (PI3USB9281_INT_ATTACH | \
-				      PI3USB9281_INT_DETACH)
+#define PI3USB9281_INT_ATTACH BIT(0)
+#define PI3USB9281_INT_DETACH BIT(1)
+#define PI3USB9281_INT_OVP BIT(5)
+#define PI3USB9281_INT_OCP BIT(6)
+#define PI3USB9281_INT_OVP_OC BIT(7)
+#define PI3USB9281_INT_ATTACH_DETACH \
+	(PI3USB9281_INT_ATTACH | PI3USB9281_INT_DETACH)
 
-#define PI3USB9281_TYPE_NONE        0
-#define PI3USB9281_TYPE_MHL         BIT(0)
-#define PI3USB9281_TYPE_OTG         BIT(1)
-#define PI3USB9281_TYPE_SDP         BIT(2)
-#define PI3USB9281_TYPE_CAR         BIT(4)
-#define PI3USB9281_TYPE_CDP         BIT(5)
-#define PI3USB9281_TYPE_DCP         BIT(6)
+#define PI3USB9281_TYPE_NONE 0
+#define PI3USB9281_TYPE_MHL BIT(0)
+#define PI3USB9281_TYPE_OTG BIT(1)
+#define PI3USB9281_TYPE_SDP BIT(2)
+#define PI3USB9281_TYPE_CAR BIT(4)
+#define PI3USB9281_TYPE_CDP BIT(5)
+#define PI3USB9281_TYPE_DCP BIT(6)
 
-#define PI3USB9281_CHG_NONE         0
-#define PI3USB9281_CHG_CAR_TYPE1    BIT(1)
-#define PI3USB9281_CHG_CAR_TYPE2    (3 << 0)
-#define PI3USB9281_CHG_APPLE_1A     BIT(2)
-#define PI3USB9281_CHG_APPLE_2A     BIT(3)
-#define PI3USB9281_CHG_APPLE_2_4A   BIT(4)
+#define PI3USB9281_CHG_NONE 0
+#define PI3USB9281_CHG_CAR_TYPE1 BIT(1)
+#define PI3USB9281_CHG_CAR_TYPE2 (3 << 0)
+#define PI3USB9281_CHG_APPLE_1A BIT(2)
+#define PI3USB9281_CHG_APPLE_2A BIT(3)
+#define PI3USB9281_CHG_APPLE_2_4A BIT(4)
 /* Check if charge status has any connection */
-#define PI3USB9281_CHG_STATUS_ANY(x) (((x) & 0x1f) > 1)
+#define PI3USB9281_CHG_STATUS_ANY(x) (((x)&0x1f) > 1)
 
 /* Define configuration of one pi3usb9281 part */
 struct pi3usb9281_config {
diff --git a/driver/build.mk b/driver/build.mk
index f8abe50742..622201e886 100644
--- a/driver/build.mk
+++ b/driver/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
+# Copyright 2014 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -118,6 +118,9 @@ driver-$(CONFIG_LED_DRIVER_TLC59116F)+=led/tlc59116f.o
 # 7-segment display
 driver-$(CONFIG_MAX695X_SEVEN_SEGMENT_DISPLAY)+=led/max695x.o
 
+# Nvidia GPU D-Notify driver
+driver-$(CONFIG_GPU_NVIDIA)+=nvidia_gpu.o
+
 # Voltage regulators
 driver-$(CONFIG_REGULATOR_IR357X)+=regulator_ir357x.o
 
@@ -162,6 +165,7 @@ endif
 driver-$(CONFIG_USB_PD_TCPM_ANX74XX)+=tcpm/anx74xx.o
 driver-$(CONFIG_USB_PD_TCPM_ANX7688)+=tcpm/anx7688.o
 driver-$(CONFIG_USB_PD_TCPM_ANX7447)+=tcpm/anx7447.o
+driver-$(CONFIG_USB_PD_TCPM_PS8745)+=tcpm/ps8xxx.o
 driver-$(CONFIG_USB_PD_TCPM_PS8751)+=tcpm/ps8xxx.o
 driver-$(CONFIG_USB_PD_TCPM_PS8755)+=tcpm/ps8xxx.o
 driver-$(CONFIG_USB_PD_TCPM_PS8705)+=tcpm/ps8xxx.o
@@ -241,4 +245,4 @@ driver-$(CONFIG_MP2964)+=mp2964.o
 
 # SOC Interface
 driver-$(CONFIG_AMD_SB_RMI)+=sb_rmi.o
-driver-$(CONFIG_AMD_STT)+=amd_stt.o
+driver-$(CONFIG_AMD_STT)+=amd_stt.o
\ No newline at end of file
diff --git a/driver/charger/bd9995x.c b/driver/charger/bd9995x.c
index 8fee94ad7b..a6303d41b4 100644
--- a/driver/charger/bd9995x.c
+++ b/driver/charger/bd9995x.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -15,13 +15,14 @@
 #include "ec_commands.h"
 #include "hooks.h"
 #include "i2c.h"
+#include "panic.h"
 #include "task.h"
 #include "time.h"
 #include "util.h"
 #include "usb_charge.h"
 #include "usb_pd.h"
 
-#define OTPROM_LOAD_WAIT_RETRY	3
+#define OTPROM_LOAD_WAIT_RETRY 3
 
 #define BD9995X_CHARGE_PORT_COUNT 2
 
@@ -29,11 +30,11 @@
  * BC1.2 detection starts 100ms after VBUS/VCC attach and typically
  * completes 312ms after VBUS/VCC attach.
  */
-#define BC12_DETECT_US (312*MSEC)
+#define BC12_DETECT_US (312 * MSEC)
 #define BD9995X_VSYS_PRECHARGE_OFFSET_MV 200
 
 /* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 #ifdef CONFIG_BD9995X_DELAY_INPUT_PORT_SELECT
 /*
@@ -44,18 +45,18 @@
 #define VBUS_DELTA 1000
 
 /* VBUS is debounced if it's stable for this length of time */
-#define VBUS_MSEC (100*MSEC)
+#define VBUS_MSEC (100 * MSEC)
 
 /* VBUS debouncing sample interval */
-#define VBUS_CHECK_MSEC (10*MSEC)
+#define VBUS_CHECK_MSEC (10 * MSEC)
 
 /* Time to wait before VBUS debouncing begins */
-#define STABLE_TIMEOUT (500*MSEC)
+#define STABLE_TIMEOUT (500 * MSEC)
 
 /* Maximum time to wait until VBUS is debounced */
-#define DEBOUNCE_TIMEOUT (500*MSEC)
+#define DEBOUNCE_TIMEOUT (500 * MSEC)
 
-enum vstate {START, STABLE, DEBOUNCE};
+enum vstate { START, STABLE, DEBOUNCE };
 static enum vstate vbus_state;
 
 static int vbus_voltage;
@@ -67,29 +68,29 @@ static int select_input_port_update;
 #endif
 
 /* Charger parameters */
-#define CHARGER_NAME    BD9995X_CHARGER_NAME
-#define CHARGE_V_MAX    19200
-#define CHARGE_V_MIN    3072
-#define CHARGE_V_STEP   16
-#define CHARGE_I_MAX    16320
-#define CHARGE_I_MIN    128
-#define CHARGE_I_OFF    0
-#define CHARGE_I_STEP   64
-#define INPUT_I_MAX     16352
-#define INPUT_I_MIN     512
-#define INPUT_I_STEP    32
+#define CHARGER_NAME BD9995X_CHARGER_NAME
+#define CHARGE_V_MAX 19200
+#define CHARGE_V_MIN 3072
+#define CHARGE_V_STEP 16
+#define CHARGE_I_MAX 16320
+#define CHARGE_I_MIN 128
+#define CHARGE_I_OFF 0
+#define CHARGE_I_STEP 64
+#define INPUT_I_MAX 16352
+#define INPUT_I_MIN 512
+#define INPUT_I_STEP 32
 
 /* Charger parameters */
 static const struct charger_info bd9995x_charger_info = {
-	.name         = CHARGER_NAME,
-	.voltage_max  = CHARGE_V_MAX,
-	.voltage_min  = CHARGE_V_MIN,
+	.name = CHARGER_NAME,
+	.voltage_max = CHARGE_V_MAX,
+	.voltage_min = CHARGE_V_MIN,
 	.voltage_step = CHARGE_V_STEP,
-	.current_max  = CHARGE_I_MAX,
-	.current_min  = CHARGE_I_MIN,
+	.current_max = CHARGE_I_MAX,
+	.current_min = CHARGE_I_MIN,
 	.current_step = CHARGE_I_STEP,
-	.input_current_max  = INPUT_I_MAX,
-	.input_current_min  = INPUT_I_MIN,
+	.input_current_max = INPUT_I_MAX,
+	.input_current_min = INPUT_I_MIN,
 	.input_current_step = INPUT_I_STEP,
 };
 
@@ -164,8 +165,7 @@ static inline enum ec_error_list ch_raw_read16(int chgnum, int cmd, int *param,
 	}
 
 	rv = i2c_read16(chg_chips[chgnum].i2c_port,
-			chg_chips[chgnum].i2c_addr_flags,
-			cmd, param);
+			chg_chips[chgnum].i2c_addr_flags, cmd, param);
 
 bd9995x_read_cleanup:
 	mutex_unlock(&bd9995x_map_mutex);
@@ -193,8 +193,7 @@ static inline enum ec_error_list ch_raw_write16(int chgnum, int cmd, int param,
 	}
 
 	rv = i2c_write16(chg_chips[chgnum].i2c_port,
-			 chg_chips[chgnum].i2c_addr_flags,
-			 cmd, param);
+			 chg_chips[chgnum].i2c_addr_flags, cmd, param);
 
 bd9995x_write_cleanup:
 	mutex_unlock(&bd9995x_map_mutex);
@@ -206,12 +205,11 @@ bd9995x_write_cleanup:
 
 static int bd9995x_set_vfastchg(int chgnum, int voltage)
 {
-
 	int rv;
 
 	/* Fast Charge Voltage Regulation Settings for fast charging. */
 	rv = ch_raw_write16(chgnum, BD9995X_CMD_VFASTCHG_REG_SET1,
-			voltage & 0x7FF0, BD9995X_EXTENDED_COMMAND);
+			    voltage & 0x7FF0, BD9995X_EXTENDED_COMMAND);
 	if (rv)
 		return rv;
 
@@ -221,12 +219,12 @@ static int bd9995x_set_vfastchg(int chgnum, int voltage)
 	 * to same voltage.
 	 */
 	rv = ch_raw_write16(chgnum, BD9995X_CMD_VFASTCHG_REG_SET2,
-			voltage & 0x7FF0, BD9995X_EXTENDED_COMMAND);
+			    voltage & 0x7FF0, BD9995X_EXTENDED_COMMAND);
 	if (rv)
 		return rv;
 
 	rv = ch_raw_write16(chgnum, BD9995X_CMD_VFASTCHG_REG_SET3,
-			voltage & 0x7FF0, BD9995X_EXTENDED_COMMAND);
+			    voltage & 0x7FF0, BD9995X_EXTENDED_COMMAND);
 #endif
 
 	return rv;
@@ -246,7 +244,7 @@ static int bd9995x_is_discharging_on_ac(int chgnum)
 	int reg;
 
 	if (ch_raw_read16(chgnum, BD9995X_CMD_CHGOP_SET2, &reg,
-				BD9995X_EXTENDED_COMMAND))
+			  BD9995X_EXTENDED_COMMAND))
 		return 0;
 
 	return !!(reg & BD9995X_CMD_CHGOP_SET2_BATT_LEARN);
@@ -292,8 +290,9 @@ static int bd9995x_charger_enable(int chgnum, int enable)
 		 * Set VSYSREG_SET > VBAT so that the charger is in Pre-Charge
 		 * state when not charging or discharging.
 		 */
-		rv = bd9995x_set_vsysreg(chgnum, bi->voltage_max +
-					 BD9995X_VSYS_PRECHARGE_OFFSET_MV);
+		rv = bd9995x_set_vsysreg(
+			chgnum,
+			bi->voltage_max + BD9995X_VSYS_PRECHARGE_OFFSET_MV);
 
 		/*
 		 * Allow charger in pre-charge state for 50ms before disabling
@@ -306,7 +305,7 @@ static int bd9995x_charger_enable(int chgnum, int enable)
 		return rv;
 
 	rv = ch_raw_read16(chgnum, BD9995X_CMD_CHGOP_SET2, &reg,
-				BD9995X_EXTENDED_COMMAND);
+			   BD9995X_EXTENDED_COMMAND);
 	if (rv)
 		return rv;
 
@@ -316,7 +315,7 @@ static int bd9995x_charger_enable(int chgnum, int enable)
 		reg &= ~BD9995X_CMD_CHGOP_SET2_CHG_EN;
 
 	return ch_raw_write16(chgnum, BD9995X_CMD_CHGOP_SET2, reg,
-				BD9995X_EXTENDED_COMMAND);
+			      BD9995X_EXTENDED_COMMAND);
 }
 
 static int bd9995x_por_reset(int chgnum)
@@ -326,9 +325,9 @@ static int bd9995x_por_reset(int chgnum)
 	int i;
 
 	rv = ch_raw_write16(chgnum, BD9995X_CMD_SYSTEM_CTRL_SET,
-			BD9995X_CMD_SYSTEM_CTRL_SET_OTPLD |
-			BD9995X_CMD_SYSTEM_CTRL_SET_ALLRST,
-			BD9995X_EXTENDED_COMMAND);
+			    BD9995X_CMD_SYSTEM_CTRL_SET_OTPLD |
+				    BD9995X_CMD_SYSTEM_CTRL_SET_ALLRST,
+			    BD9995X_EXTENDED_COMMAND);
 	if (rv)
 		return rv;
 
@@ -336,10 +335,10 @@ static int bd9995x_por_reset(int chgnum)
 	for (i = 0; i < OTPROM_LOAD_WAIT_RETRY; i++) {
 		msleep(10);
 		rv = ch_raw_read16(chgnum, BD9995X_CMD_SYSTEM_STATUS, &reg,
-				BD9995X_EXTENDED_COMMAND);
+				   BD9995X_EXTENDED_COMMAND);
 
 		if (!rv && (reg & BD9995X_CMD_SYSTEM_STATUS_OTPLD_STATE) &&
-			(reg & BD9995X_CMD_SYSTEM_STATUS_ALLRST_STATE))
+		    (reg & BD9995X_CMD_SYSTEM_STATUS_ALLRST_STATE))
 			break;
 	}
 
@@ -349,7 +348,7 @@ static int bd9995x_por_reset(int chgnum)
 		return EC_ERROR_TIMEOUT;
 
 	return ch_raw_write16(chgnum, BD9995X_CMD_SYSTEM_CTRL_SET, 0,
-				BD9995X_EXTENDED_COMMAND);
+			      BD9995X_EXTENDED_COMMAND);
 }
 
 static int bd9995x_reset_to_zero(int chgnum)
@@ -366,7 +365,7 @@ static int bd9995x_reset_to_zero(int chgnum)
 static int bd9995x_get_charger_op_status(int chgnum, int *status)
 {
 	return ch_raw_read16(chgnum, BD9995X_CMD_CHGOP_STATUS, status,
-				BD9995X_EXTENDED_COMMAND);
+			     BD9995X_EXTENDED_COMMAND);
 }
 
 #ifdef HAS_TASK_USB_CHG
@@ -379,10 +378,11 @@ static int bd9995x_get_bc12_device_type(int chgnum, int port)
 	int rv;
 	int reg;
 
-	rv = ch_raw_read16(chgnum, (port == BD9995X_CHARGE_PORT_VBUS) ?
-				BD9995X_CMD_VBUS_UCD_STATUS :
-				BD9995X_CMD_VCC_UCD_STATUS,
-				&reg, BD9995X_EXTENDED_COMMAND);
+	rv = ch_raw_read16(chgnum,
+			   (port == BD9995X_CHARGE_PORT_VBUS) ?
+				   BD9995X_CMD_VBUS_UCD_STATUS :
+				   BD9995X_CMD_VCC_UCD_STATUS,
+			   &reg, BD9995X_EXTENDED_COMMAND);
 	if (rv)
 		return CHARGE_SUPPLIER_NONE;
 
@@ -415,7 +415,8 @@ static int bd9995x_update_ucd_set_reg(int chgnum, int port, uint16_t mask,
 	int rv;
 	int reg;
 	int port_reg = (port == BD9995X_CHARGE_PORT_VBUS) ?
-		BD9995X_CMD_VBUS_UCD_SET : BD9995X_CMD_VCC_UCD_SET;
+			       BD9995X_CMD_VBUS_UCD_SET :
+			       BD9995X_CMD_VCC_UCD_SET;
 
 	mutex_lock(&ucd_set_mutex[port]);
 	rv = ch_raw_read16(chgnum, port_reg, &reg, BD9995X_EXTENDED_COMMAND);
@@ -484,32 +485,33 @@ static int bd9995x_enable_vbus_detect_interrupts(int chgnum, int port,
 
 	/* 1st Level Interrupt Setting */
 	rv = ch_raw_read16(chgnum, BD9995X_CMD_INT0_SET, &reg,
-			BD9995X_EXTENDED_COMMAND);
+			   BD9995X_EXTENDED_COMMAND);
 	if (rv)
 		return rv;
 
 	mask_val = ((port == BD9995X_CHARGE_PORT_VBUS) ?
-			BD9995X_CMD_INT0_SET_INT1_EN :
-			BD9995X_CMD_INT0_SET_INT2_EN) |
-			BD9995X_CMD_INT0_SET_INT0_EN;
+			    BD9995X_CMD_INT0_SET_INT1_EN :
+			    BD9995X_CMD_INT0_SET_INT2_EN) |
+		   BD9995X_CMD_INT0_SET_INT0_EN;
 	if (enable)
 		reg |= mask_val;
 	else
 		reg &= ~mask_val;
 
 	rv = ch_raw_write16(chgnum, BD9995X_CMD_INT0_SET, reg,
-			BD9995X_EXTENDED_COMMAND);
+			    BD9995X_EXTENDED_COMMAND);
 	if (rv)
 		return rv;
 
 	/* 2nd Level Interrupt Setting */
-	port_reg = (port == BD9995X_CHARGE_PORT_VBUS) ?
-			BD9995X_CMD_INT1_SET : BD9995X_CMD_INT2_SET;
+	port_reg = (port == BD9995X_CHARGE_PORT_VBUS) ? BD9995X_CMD_INT1_SET :
+							BD9995X_CMD_INT2_SET;
 	rv = ch_raw_read16(chgnum, port_reg, &reg, BD9995X_EXTENDED_COMMAND);
 	if (rv)
 		return rv;
 
-	/* Enable threshold interrupts if we need to control discharge */
+		/* Enable threshold interrupts if we need to control discharge
+		 */
 #ifdef CONFIG_USB_PD_DISCHARGE
 	mask_val = BD9995X_CMD_INT_VBUS_DET | BD9995X_CMD_INT_VBUS_TH;
 #else
@@ -531,7 +533,8 @@ static int bd9995x_get_interrupts(int chgnum, int port)
 	int port_reg;
 
 	port_reg = (port == BD9995X_CHARGE_PORT_VBUS) ?
-			BD9995X_CMD_INT1_STATUS : BD9995X_CMD_INT2_STATUS;
+			   BD9995X_CMD_INT1_STATUS :
+			   BD9995X_CMD_INT2_STATUS;
 
 	rv = ch_raw_read16(chgnum, port_reg, &reg, BD9995X_EXTENDED_COMMAND);
 
@@ -553,8 +556,8 @@ static int bd9995x_bc12_detect(int chgnum, int port, int enable)
 {
 	return bd9995x_update_ucd_set_reg(chgnum, port,
 					  BD9995X_CMD_UCD_SET_BCSRETRY |
-					  BD9995X_CMD_UCD_SET_USBDETEN |
-					  BD9995X_CMD_UCD_SET_USB_SW_EN,
+						  BD9995X_CMD_UCD_SET_USBDETEN |
+						  BD9995X_CMD_UCD_SET_USB_SW_EN,
 					  enable);
 }
 
@@ -626,12 +629,12 @@ static enum ec_error_list bd9995x_set_input_current_limit(int chgnum,
 		input_current = bd9995x_charger_info.input_current_min;
 
 	rv = ch_raw_write16(chgnum, BD9995X_CMD_IBUS_LIM_SET, input_current,
-				BD9995X_BAT_CHG_COMMAND);
+			    BD9995X_BAT_CHG_COMMAND);
 	if (rv)
 		return rv;
 
 	return ch_raw_write16(chgnum, BD9995X_CMD_ICC_LIM_SET, input_current,
-				BD9995X_BAT_CHG_COMMAND);
+			      BD9995X_BAT_CHG_COMMAND);
 }
 
 static enum ec_error_list bd9995x_get_input_current_limit(int chgnum,
@@ -658,12 +661,12 @@ static enum ec_error_list bd9995x_get_option(int chgnum, int *option)
 	int reg;
 
 	rv = ch_raw_read16(chgnum, BD9995X_CMD_CHGOP_SET1, option,
-				BD9995X_EXTENDED_COMMAND);
+			   BD9995X_EXTENDED_COMMAND);
 	if (rv)
 		return rv;
 
 	rv = ch_raw_read16(chgnum, BD9995X_CMD_CHGOP_SET2, &reg,
-				BD9995X_EXTENDED_COMMAND);
+			   BD9995X_EXTENDED_COMMAND);
 	if (rv)
 		return rv;
 
@@ -677,7 +680,7 @@ static enum ec_error_list bd9995x_set_option(int chgnum, int option)
 	int rv;
 
 	rv = ch_raw_write16(chgnum, BD9995X_CMD_CHGOP_SET1, option & 0xFFFF,
-				BD9995X_EXTENDED_COMMAND);
+			    BD9995X_EXTENDED_COMMAND);
 	if (rv)
 		return rv;
 
@@ -704,7 +707,7 @@ static enum ec_error_list bd9995x_get_status(int chgnum, int *status)
 
 	/* charger enable/inhibit */
 	rv = ch_raw_read16(chgnum, BD9995X_CMD_CHGOP_SET2, &reg,
-				BD9995X_EXTENDED_COMMAND);
+			   BD9995X_EXTENDED_COMMAND);
 	if (rv)
 		return rv;
 
@@ -713,15 +716,15 @@ static enum ec_error_list bd9995x_get_status(int chgnum, int *status)
 
 	/* charger alarm enable/inhibit */
 	rv = ch_raw_read16(chgnum, BD9995X_CMD_PROCHOT_CTRL_SET, &reg,
-				BD9995X_EXTENDED_COMMAND);
+			   BD9995X_EXTENDED_COMMAND);
 	if (rv)
 		return rv;
 
 	if (!(reg & (BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN4 |
-			BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN3 |
-			BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN2 |
-			BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN1 |
-			BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN0)))
+		     BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN3 |
+		     BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN2 |
+		     BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN1 |
+		     BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN0)))
 		*status |= CHARGER_ALARM_INHIBITED;
 
 	rv = bd9995x_get_charger_op_status(chgnum, &reg);
@@ -788,7 +791,7 @@ static enum ec_error_list bd9995x_set_mode(int chgnum, int mode)
 static enum ec_error_list bd9995x_get_current(int chgnum, int *current)
 {
 	return ch_raw_read16(chgnum, BD9995X_CMD_CHG_CURRENT, current,
-				BD9995X_BAT_CHG_COMMAND);
+			     BD9995X_BAT_CHG_COMMAND);
 }
 
 static enum ec_error_list bd9995x_set_current(int chgnum, int current)
@@ -824,7 +827,7 @@ static enum ec_error_list bd9995x_set_current(int chgnum, int current)
 		return rv;
 
 	rv = ch_raw_write16(chgnum, BD9995X_CMD_CHG_CURRENT, current,
-			      BD9995X_BAT_CHG_COMMAND);
+			    BD9995X_BAT_CHG_COMMAND);
 	if (rv)
 		return rv;
 
@@ -869,7 +872,7 @@ static enum ec_error_list bd9995x_get_voltage(int chgnum, int *voltage)
 	}
 
 	return ch_raw_read16(chgnum, BD9995X_CMD_CHG_VOLTAGE, voltage,
-				BD9995X_BAT_CHG_COMMAND);
+			     BD9995X_BAT_CHG_COMMAND);
 }
 
 static enum ec_error_list bd9995x_set_voltage(int chgnum, int voltage)
@@ -880,11 +883,9 @@ static enum ec_error_list bd9995x_set_voltage(int chgnum, int voltage)
 	 * Regulate the system voltage to battery max if the battery
 	 * is not present or the battery is discharging on AC.
 	 */
-	if (voltage == 0 ||
-		bd9995x_is_discharging_on_ac(chgnum) ||
-		battery_is_present() != BP_YES ||
-		battery_is_cut_off() ||
-		voltage > battery_voltage_max)
+	if (voltage == 0 || bd9995x_is_discharging_on_ac(chgnum) ||
+	    battery_is_present() != BP_YES || battery_is_cut_off() ||
+	    voltage > battery_voltage_max)
 		voltage = battery_voltage_max;
 
 	/* Charge voltage step 16 mV */
@@ -921,8 +922,7 @@ static void bd9995x_battery_charging_profile_settings(int chgnum)
 		       BD9995X_EXTENDED_COMMAND);
 
 	/* Re-charge Battery Voltage Setting */
-	ch_raw_write16(chgnum, BD9995X_CMD_VRECHG_SET,
-		       bi->voltage_max & 0x7FF0,
+	ch_raw_write16(chgnum, BD9995X_CMD_VRECHG_SET, bi->voltage_max & 0x7FF0,
 		       BD9995X_EXTENDED_COMMAND);
 
 	/* Set battery OVP to 500 + maximum battery voltage */
@@ -972,8 +972,9 @@ static void bd9995x_init(void)
 	 * that the charger is in Pre-Charge state and that the input current
 	 * disable setting below will be active.
 	 */
-	bd9995x_set_vsysreg(CHARGER_SOLO, battery_get_info()->voltage_max +
-			    BD9995X_VSYS_PRECHARGE_OFFSET_MV);
+	bd9995x_set_vsysreg(CHARGER_SOLO,
+			    battery_get_info()->voltage_max +
+				    BD9995X_VSYS_PRECHARGE_OFFSET_MV);
 
 	/* Enable BC1.2 USB charging and DC/DC converter @ 1200KHz */
 	if (ch_raw_read16(CHARGER_SOLO, BD9995X_CMD_CHGOP_SET2, &reg,
@@ -1060,7 +1061,7 @@ static enum ec_error_list bd9995x_discharge_on_ac(int chgnum, int enable)
 	int reg;
 
 	rv = ch_raw_read16(chgnum, BD9995X_CMD_CHGOP_SET2, &reg,
-				BD9995X_EXTENDED_COMMAND);
+			   BD9995X_EXTENDED_COMMAND);
 	if (rv)
 		return rv;
 
@@ -1072,13 +1073,13 @@ static enum ec_error_list bd9995x_discharge_on_ac(int chgnum, int enable)
 	 */
 	if (enable)
 		reg |= BD9995X_CMD_CHGOP_SET2_BATT_LEARN |
-			BD9995X_CMD_CHGOP_SET2_USB_SUS;
+		       BD9995X_CMD_CHGOP_SET2_USB_SUS;
 	else
 		reg &= ~(BD9995X_CMD_CHGOP_SET2_BATT_LEARN |
-			BD9995X_CMD_CHGOP_SET2_USB_SUS);
+			 BD9995X_CMD_CHGOP_SET2_USB_SUS);
 
 	return ch_raw_write16(chgnum, BD9995X_CMD_CHGOP_SET2, reg,
-				BD9995X_EXTENDED_COMMAND);
+			      BD9995X_EXTENDED_COMMAND);
 }
 
 static enum ec_error_list bd9995x_get_vbus_voltage(int chgnum, int port,
@@ -1143,7 +1144,7 @@ int bd9995x_select_input_port(enum bd9995x_charge_port port, int select)
 		} else if (port == BD9995X_CHARGE_PORT_BOTH) {
 			/* Enable both the ports for PG3 */
 			reg |= BD9995X_CMD_VIN_CTRL_SET_VBUS_EN |
-				BD9995X_CMD_VIN_CTRL_SET_VCC_EN;
+			       BD9995X_CMD_VIN_CTRL_SET_VCC_EN;
 		} else {
 			/* Invalid charge port */
 			panic("Invalid charge port");
@@ -1161,7 +1162,7 @@ int bd9995x_select_input_port(enum bd9995x_charge_port port, int select)
 	}
 
 	rv = ch_raw_write16(CHARGER_SOLO, BD9995X_CMD_VIN_CTRL_SET, reg,
-			      BD9995X_EXTENDED_COMMAND);
+			    BD9995X_EXTENDED_COMMAND);
 select_input_port_exit:
 	mutex_unlock(&bd9995x_vin_mutex);
 	return rv;
@@ -1192,8 +1193,8 @@ static int bd9995x_vbus_debounce(int chgnum, enum bd9995x_charge_port port)
 	int vbus_reg;
 	int voltage;
 
-	vbus_reg = (port == BD9995X_CHARGE_PORT_VBUS) ?
-		BD9995X_CMD_VBUS_VAL : BD9995X_CMD_VCC_VAL;
+	vbus_reg = (port == BD9995X_CHARGE_PORT_VBUS) ? BD9995X_CMD_VBUS_VAL :
+							BD9995X_CMD_VCC_VAL;
 	if (ch_raw_read16(chgnum, vbus_reg, &voltage, BD9995X_EXTENDED_COMMAND))
 		voltage = 0;
 
@@ -1209,14 +1210,13 @@ static int bd9995x_vbus_debounce(int chgnum, enum bd9995x_charge_port port)
 }
 #endif
 
-
 #ifdef CONFIG_CHARGER_BATTERY_TSENSE
 int bd9995x_get_battery_temp(int *temp_ptr)
 {
 	int rv;
 
 	rv = ch_raw_read16(CHARGER_SOLO, BD9995X_CMD_THERM_VAL, temp_ptr,
-			BD9995X_EXTENDED_COMMAND);
+			   BD9995X_EXTENDED_COMMAND);
 	if (rv)
 		return rv;
 
@@ -1237,7 +1237,7 @@ int bd9995x_get_battery_voltage(void)
 	int vbat_val, rv;
 
 	rv = ch_raw_read16(CHARGER_SOLO, BD9995X_CMD_VBAT_VAL, &vbat_val,
-			BD9995X_EXTENDED_COMMAND);
+			   BD9995X_EXTENDED_COMMAND);
 
 	return rv ? 0 : vbat_val;
 }
@@ -1255,15 +1255,15 @@ int bd9995x_bc12_enable_charging(int port, int enable)
 	 * for USB-C.
 	 */
 	rv = ch_raw_read16(CHARGER_SOLO, BD9995X_CMD_CHGOP_SET1, &reg,
-			BD9995X_EXTENDED_COMMAND);
+			   BD9995X_EXTENDED_COMMAND);
 	if (rv)
 		return rv;
 
 	mask_val = (BD9995X_CMD_CHGOP_SET1_SDP_CHG_TRIG_EN |
-		BD9995X_CMD_CHGOP_SET1_SDP_CHG_TRIG |
-		((port == BD9995X_CHARGE_PORT_VBUS) ?
-		BD9995X_CMD_CHGOP_SET1_VBUS_BC_DISEN :
-		BD9995X_CMD_CHGOP_SET1_VCC_BC_DISEN));
+		    BD9995X_CMD_CHGOP_SET1_SDP_CHG_TRIG |
+		    ((port == BD9995X_CHARGE_PORT_VBUS) ?
+			     BD9995X_CMD_CHGOP_SET1_VBUS_BC_DISEN :
+			     BD9995X_CMD_CHGOP_SET1_VCC_BC_DISEN));
 
 	if (enable)
 		reg &= ~mask_val;
@@ -1271,7 +1271,7 @@ int bd9995x_bc12_enable_charging(int port, int enable)
 		reg |= mask_val;
 
 	return ch_raw_write16(CHARGER_SOLO, BD9995X_CMD_CHGOP_SET1, reg,
-			BD9995X_EXTENDED_COMMAND);
+			      BD9995X_EXTENDED_COMMAND);
 }
 
 static void bd9995x_set_switches(int port, enum usb_switch setting)
@@ -1283,17 +1283,18 @@ static void bd9995x_set_switches(int port, enum usb_switch setting)
 	if (setting != USB_SWITCH_RESTORE)
 		usb_switch_state[port] = setting;
 
-	/* ensure we disable power saving when we are using DP/DN */
+		/* ensure we disable power saving when we are using DP/DN */
 #ifdef CONFIG_BD9995X_POWER_SAVE_MODE
 	bd9995x_set_power_save_mode(
 		(usb_switch_state[0] == USB_SWITCH_DISCONNECT &&
-		usb_switch_state[1] == USB_SWITCH_DISCONNECT)
-		? CONFIG_BD9995X_POWER_SAVE_MODE : BD9995X_PWR_SAVE_OFF);
+		 usb_switch_state[1] == USB_SWITCH_DISCONNECT) ?
+			CONFIG_BD9995X_POWER_SAVE_MODE :
+			BD9995X_PWR_SAVE_OFF);
 #endif
 
-	bd9995x_update_ucd_set_reg(CHARGER_SOLO, port,
-				   BD9995X_CMD_UCD_SET_USB_SW,
-				usb_switch_state[port] == USB_SWITCH_CONNECT);
+	bd9995x_update_ucd_set_reg(
+		CHARGER_SOLO, port, BD9995X_CMD_UCD_SET_USB_SW,
+		usb_switch_state[port] == USB_SWITCH_CONNECT);
 }
 
 void bd9995x_vbus_interrupt(enum gpio_signal signal)
@@ -1337,8 +1338,11 @@ static void bd9995x_usb_charger_task_init(const int unused)
 				 * provided, then disable wait for this port.
 				 */
 				bc12_det_mark[port] =
-					usb_charger_process(CHARGER_SOLO, port)
-					? get_time().val + BC12_DETECT_US : 0;
+					usb_charger_process(CHARGER_SOLO,
+							    port) ?
+						get_time().val +
+							BC12_DETECT_US :
+						0;
 				changed = 1;
 			}
 #ifdef CONFIG_USB_PD_DISCHARGE
@@ -1346,21 +1350,22 @@ static void bd9995x_usb_charger_task_init(const int unused)
 			    !initialized) {
 				/* Get VBUS voltage */
 				vbus_reg = (port == BD9995X_CHARGE_PORT_VBUS) ?
-					   BD9995X_CMD_VBUS_VAL :
-					   BD9995X_CMD_VCC_VAL;
+						   BD9995X_CMD_VBUS_VAL :
+						   BD9995X_CMD_VCC_VAL;
 				if (ch_raw_read16(CHARGER_SOLO, vbus_reg,
 						  &voltage,
 						  BD9995X_EXTENDED_COMMAND))
 					voltage = 0;
 
 				/* Set discharge accordingly */
-				pd_set_vbus_discharge(port,
+				pd_set_vbus_discharge(
+					port,
 					voltage < BD9995X_VBUS_DISCHARGE_TH);
 				changed = 1;
 			}
 #endif
-			if (bc12_det_mark[port] && (get_time().val >
-						    bc12_det_mark[port])) {
+			if (bc12_det_mark[port] &&
+			    (get_time().val > bc12_det_mark[port])) {
 				/*
 				 * bc12_type result should be available. If not
 				 * available still, then function will return
@@ -1371,7 +1376,8 @@ static void bd9995x_usb_charger_task_init(const int unused)
 				bc12_det_mark[port] =
 					bd9995x_bc12_check_type(CHARGER_SOLO,
 								port) ?
-					get_time().val + 100 * MSEC : 0;
+						get_time().val + 100 * MSEC :
+						0;
 				/* Reset BC1.2 regs to skip auto-detection. */
 				bd9995x_bc12_detect(CHARGER_SOLO, port, 0);
 			}
@@ -1386,8 +1392,8 @@ static void bd9995x_usb_charger_task_init(const int unused)
 			if (bc12_det_mark[port]) {
 				int bc12_wait_usec;
 
-				bc12_wait_usec = bc12_det_mark[port]
-					- get_time().val;
+				bc12_wait_usec =
+					bc12_det_mark[port] - get_time().val;
 				if ((sleep_usec < 0) ||
 				    (sleep_usec > bc12_wait_usec))
 					sleep_usec = bc12_wait_usec;
@@ -1396,40 +1402,43 @@ static void bd9995x_usb_charger_task_init(const int unused)
 
 		initialized = 1;
 #ifdef CONFIG_BD9995X_DELAY_INPUT_PORT_SELECT
-/*
- * When a charge port is selected and VBUS is 5V, the inrush current on some
- * devices causes VBUS to droop, which could signal a sink disconnection.
- *
- * To mitigate the problem, charge port selection is delayed until VBUS
- * is stable or one second has passed. Hopefully PD has negotiated a VBUS
- * voltage of at least 9V before the one second timeout.
- */
-	if (select_input_port_update) {
-		sleep_usec = VBUS_CHECK_MSEC;
-		changed = 0;
-
-		switch (vbus_state) {
-		case START:
-			vbus_timeout = get_time().val + STABLE_TIMEOUT;
-			vbus_state = STABLE;
-			break;
-		case STABLE:
-			if (get_time().val > vbus_timeout) {
-				vbus_state = DEBOUNCE;
-				vbus_timeout = get_time().val +
-							DEBOUNCE_TIMEOUT;
-			}
-			break;
-		case DEBOUNCE:
-			if (bd9995x_vbus_debounce(CHARGER_SOLO, port_update) ||
-					get_time().val > vbus_timeout) {
-				select_input_port_update = 0;
-				bd9995x_select_input_port_private(
+		/*
+		 * When a charge port is selected and VBUS is 5V, the inrush
+		 * current on some devices causes VBUS to droop, which could
+		 * signal a sink disconnection.
+		 *
+		 * To mitigate the problem, charge port selection is delayed
+		 * until VBUS is stable or one second has passed. Hopefully PD
+		 * has negotiated a VBUS voltage of at least 9V before the one
+		 * second timeout.
+		 */
+		if (select_input_port_update) {
+			sleep_usec = VBUS_CHECK_MSEC;
+			changed = 0;
+
+			switch (vbus_state) {
+			case START:
+				vbus_timeout = get_time().val + STABLE_TIMEOUT;
+				vbus_state = STABLE;
+				break;
+			case STABLE:
+				if (get_time().val > vbus_timeout) {
+					vbus_state = DEBOUNCE;
+					vbus_timeout = get_time().val +
+						       DEBOUNCE_TIMEOUT;
+				}
+				break;
+			case DEBOUNCE:
+				if (bd9995x_vbus_debounce(CHARGER_SOLO,
+							  port_update) ||
+				    get_time().val > vbus_timeout) {
+					select_input_port_update = 0;
+					bd9995x_select_input_port_private(
 						port_update, select_update);
+				}
+				break;
 			}
-			break;
 		}
-	}
 #endif
 
 		/*
@@ -1445,7 +1454,6 @@ static void bd9995x_usb_charger_task_init(const int unused)
 }
 #endif /* HAS_TASK_USB_CHG */
 
-
 /*** Console commands ***/
 #ifdef CONFIG_CMD_CHARGER_DUMP
 static int read_bat(int chgnum, uint8_t cmd)
@@ -1472,8 +1480,8 @@ static void console_bd9995x_dump_regs(int chgnum)
 
 	/* Battery group registers */
 	for (i = 0; i < ARRAY_SIZE(regs); ++i)
-		ccprintf("BAT REG %4x:  %4x\n", regs[i], read_bat(CHARGER_SOLO,
-								  regs[i]));
+		ccprintf("BAT REG %4x:  %4x\n", regs[i],
+			 read_bat(CHARGER_SOLO, regs[i]));
 
 	/* Extended group registers */
 	for (i = 0; i < 0x7f; ++i) {
@@ -1484,7 +1492,7 @@ static void console_bd9995x_dump_regs(int chgnum)
 #endif /* CONFIG_CMD_CHARGER_DUMP */
 
 #ifdef CONFIG_CMD_CHARGER
-static int console_command_bd9995x(int argc, char **argv)
+static int console_command_bd9995x(int argc, const char **argv)
 {
 	int rv, reg, data, val;
 	char rw, *e;
@@ -1538,7 +1546,7 @@ static int bd9995x_psys_charger_adc(int chgnum)
 
 	for (i = 0; i < BD9995X_PMON_IOUT_ADC_READ_COUNT; i++) {
 		if (ch_raw_read16(chgnum, BD9995X_CMD_PMON_DACIN_VAL, &reg,
-				BD9995X_EXTENDED_COMMAND))
+				  BD9995X_EXTENDED_COMMAND))
 			return 0;
 
 		/* Conversion Interval is 200us */
@@ -1550,8 +1558,8 @@ static int bd9995x_psys_charger_adc(int chgnum)
 	 * Calculate power in mW
 	 * PSYS = VACP×IACP+VBAT×IBAT = IPMON / GPMON
 	 */
-	return (int) ((ipmon * 1000) / (BIT(BD9995X_PSYS_GAIN_SELECT) *
-		BD9995X_PMON_IOUT_ADC_READ_COUNT));
+	return (int)((ipmon * 1000) / (BIT(BD9995X_PSYS_GAIN_SELECT) *
+				       BD9995X_PMON_IOUT_ADC_READ_COUNT));
 }
 
 static int bd9995x_enable_psys(int chgnum)
@@ -1560,7 +1568,7 @@ static int bd9995x_enable_psys(int chgnum)
 	int reg;
 
 	rv = ch_raw_read16(chgnum, BD9995X_CMD_PMON_IOUT_CTRL_SET, &reg,
-			BD9995X_EXTENDED_COMMAND);
+			   BD9995X_EXTENDED_COMMAND);
 	if (rv)
 		return rv;
 
@@ -1571,7 +1579,7 @@ static int bd9995x_enable_psys(int chgnum)
 		BD9995X_PSYS_GAIN_SELECT);
 
 	return ch_raw_write16(chgnum, BD9995X_CMD_PMON_IOUT_CTRL_SET, reg,
-			BD9995X_EXTENDED_COMMAND);
+			      BD9995X_EXTENDED_COMMAND);
 }
 
 /**
@@ -1582,7 +1590,7 @@ static int bd9995x_enable_psys(int chgnum)
  * update "psys" console command to use charger_get_system_power and move it
  * to some common code.
  */
-static int console_command_psys(int argc, char **argv)
+static int console_command_psys(int argc, const char **argv)
 {
 	int rv;
 
@@ -1591,12 +1599,11 @@ static int console_command_psys(int argc, char **argv)
 		return rv;
 
 	CPRINTS("PSYS from chg_adc: %d mW",
-			bd9995x_psys_charger_adc(CHARGER_SOLO));
+		bd9995x_psys_charger_adc(CHARGER_SOLO));
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(psys, console_command_psys,
-			NULL,
+DECLARE_CONSOLE_COMMAND(psys, console_command_psys, NULL,
 			"Get the system power in mW");
 #endif /* CONFIG_CHARGER_PSYS_READ */
 
@@ -1609,7 +1616,7 @@ static int bd9995x_amon_bmon_chg_adc(int chgnum)
 
 	for (i = 0; i < BD9995X_PMON_IOUT_ADC_READ_COUNT; i++) {
 		ch_raw_read16(chgnum, BD9995X_CMD_IOUT_DACIN_VAL, &reg,
-				BD9995X_EXTENDED_COMMAND);
+			      BD9995X_EXTENDED_COMMAND);
 		iout += reg;
 
 		/* Conversion Interval is 200us */
@@ -1625,7 +1632,7 @@ static int bd9995x_amon_bmon_chg_adc(int chgnum)
 	 * VIADP = GIADP * (VACP- VACN) = GIADP * IADP / IADP_RES
 	 */
 	return (iout * (5 << BD9995X_IOUT_GAIN_SELECT)) /
-		(10 * BD9995X_PMON_IOUT_ADC_READ_COUNT);
+	       (10 * BD9995X_PMON_IOUT_ADC_READ_COUNT);
 }
 
 static int bd9995x_amon_bmon(int chgnum, int amon_bmon)
@@ -1636,7 +1643,7 @@ static int bd9995x_amon_bmon(int chgnum, int amon_bmon)
 	int sns_res;
 
 	rv = ch_raw_read16(chgnum, BD9995X_CMD_PMON_IOUT_CTRL_SET, &reg,
-			BD9995X_EXTENDED_COMMAND);
+			   BD9995X_EXTENDED_COMMAND);
 	if (rv)
 		return rv;
 
@@ -1655,16 +1662,14 @@ static int bd9995x_amon_bmon(int chgnum, int amon_bmon)
 	}
 
 	rv = ch_raw_write16(chgnum, BD9995X_CMD_PMON_IOUT_CTRL_SET, reg,
-			BD9995X_EXTENDED_COMMAND);
+			    BD9995X_EXTENDED_COMMAND);
 	if (rv)
 		return rv;
 
 	imon = bd9995x_amon_bmon_chg_adc(chgnum);
 
-	CPRINTS("%cMON from chg_adc: %d uV, %d mA]",
-		amon_bmon ? 'A' : 'B',
-		imon * sns_res,
-		imon);
+	CPRINTS("%cMON from chg_adc: %d uV, %d mA]", amon_bmon ? 'A' : 'B',
+		imon * sns_res, imon);
 
 	return EC_SUCCESS;
 }
@@ -1672,7 +1677,7 @@ static int bd9995x_amon_bmon(int chgnum, int amon_bmon)
 /**
  * Get charger AMON and BMON current.
  */
-static int console_command_amon_bmon(int argc, char **argv)
+static int console_command_amon_bmon(int argc, const char **argv)
 {
 	int rv = EC_ERROR_PARAM1;
 
@@ -1686,8 +1691,7 @@ static int console_command_amon_bmon(int argc, char **argv)
 
 	return rv;
 }
-DECLARE_CONSOLE_COMMAND(amonbmon, console_command_amon_bmon,
-			"amonbmon [a|b]",
+DECLARE_CONSOLE_COMMAND(amonbmon, console_command_amon_bmon, "amonbmon [a|b]",
 			"Get charger AMON/BMON voltage diff, current");
 #endif /* CONFIG_CMD_CHARGER_ADC_AMON_BMON */
 
@@ -1741,28 +1745,32 @@ const struct charger_drv bd9995x_drv = {
 /* provide a default bc12_ports[] for backward compatibility */
 struct bc12_config bc12_ports[BD9995X_CHARGE_PORT_COUNT] = {
 	{
-		.drv = &(const struct bc12_drv) {
-			.usb_charger_task_init = bd9995x_usb_charger_task_init,
-			/* events handled in init */
-			.usb_charger_task_event = NULL,
-			.set_switches = bd9995x_set_switches,
+		.drv =
+			&(const struct bc12_drv){
+				.usb_charger_task_init =
+					bd9995x_usb_charger_task_init,
+				/* events handled in init */
+				.usb_charger_task_event = NULL,
+				.set_switches = bd9995x_set_switches,
 #if defined(CONFIG_CHARGE_RAMP_SW)
-			.ramp_allowed = bd9995x_ramp_allowed,
-			.ramp_max = bd9995x_ramp_max,
+				.ramp_allowed = bd9995x_ramp_allowed,
+				.ramp_max = bd9995x_ramp_max,
 #endif /* CONFIG_CHARGE_RAMP_SW */
-		},
+			},
 	},
 	{
-		.drv = &(const struct bc12_drv) {
-			/* bd9995x uses a single task thread for both ports */
-			.usb_charger_task_init = NULL,
-			.usb_charger_task_event = NULL,
-			.set_switches = bd9995x_set_switches,
+		.drv =
+			&(const struct bc12_drv){
+				/* bd9995x uses a single task thread for both
+				   ports */
+				.usb_charger_task_init = NULL,
+				.usb_charger_task_event = NULL,
+				.set_switches = bd9995x_set_switches,
 #if defined(CONFIG_CHARGE_RAMP_SW)
-			.ramp_allowed = bd9995x_ramp_allowed,
-			.ramp_max = bd9995x_ramp_max,
+				.ramp_allowed = bd9995x_ramp_allowed,
+				.ramp_max = bd9995x_ramp_max,
 #endif /* CONFIG_CHARGE_RAMP_SW */
-		},
+			},
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(bc12_ports) == CHARGE_PORT_COUNT);
diff --git a/driver/charger/bd9995x.h b/driver/charger/bd9995x.h
index a1f1bdb64f..f50712ead0 100644
--- a/driver/charger/bd9995x.h
+++ b/driver/charger/bd9995x.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,11 +8,11 @@
 #ifndef __CROS_EC_BD9995X_H
 #define __CROS_EC_BD9995X_H
 
-#define BD9995X_ADDR_FLAGS	0x09
+#define BD9995X_ADDR_FLAGS 0x09
 
-#define BD9995X_CHARGER_NAME	"bd9995x"
-#define BD99955_CHIP_ID		0x221
-#define BD99956_CHIP_ID		0x331
+#define BD9995X_CHARGER_NAME "bd9995x"
+#define BD99955_CHIP_ID 0x221
+#define BD99956_CHIP_ID 0x331
 
 /* BD9995X commands to change the command code map */
 enum bd9995x_command {
@@ -35,7 +35,7 @@ enum bd9995x_charge_port {
 };
 
 /* Min. charge current w/ no battery to prevent collapse */
-#define BD9995X_NO_BATTERY_CHARGE_I_MIN	512
+#define BD9995X_NO_BATTERY_CHARGE_I_MIN 512
 
 /*
  * BC1.2 minimum voltage threshold.
@@ -43,285 +43,283 @@ enum bd9995x_charge_port {
  * BD9995X Anti-Collapse Threshold Voltage Accuracy is -100mV to +100mV,
  * and Delta of 50mV.
  */
-#define BD9995X_BC12_MIN_VOLTAGE	4600
+#define BD9995X_BC12_MIN_VOLTAGE 4600
 
 /* Battery Charger Commands */
-#define BD9995X_CMD_CHG_CURRENT		0x14
-#define BD9995X_CMD_CHG_VOLTAGE		0x15
-#define BD9995X_CMD_IBUS_LIM_SET	0x3C
-#define BD9995X_CMD_ICC_LIM_SET		0x3D
-#define BD9995X_CMD_PROTECT_SET		0x3E
-#define BD9995X_CMD_MAP_SET		0x3F
+#define BD9995X_CMD_CHG_CURRENT 0x14
+#define BD9995X_CMD_CHG_VOLTAGE 0x15
+#define BD9995X_CMD_IBUS_LIM_SET 0x3C
+#define BD9995X_CMD_ICC_LIM_SET 0x3D
+#define BD9995X_CMD_PROTECT_SET 0x3E
+#define BD9995X_CMD_MAP_SET 0x3F
 
 /* Extended commands */
-#define BD9995X_CMD_CHGSTM_STATUS	0x00
-#define BD9995X_CMD_VBAT_VSYS_STATUS	0x01
-#define BD9995X_CMD_VBUS_VCC_STATUS	0x02
-#define BD9995X_CMD_VBUS_VCC_STATUS_VCC_DETECT  BIT(8)
+#define BD9995X_CMD_CHGSTM_STATUS 0x00
+#define BD9995X_CMD_VBAT_VSYS_STATUS 0x01
+#define BD9995X_CMD_VBUS_VCC_STATUS 0x02
+#define BD9995X_CMD_VBUS_VCC_STATUS_VCC_DETECT BIT(8)
 #define BD9995X_CMD_VBUS_VCC_STATUS_VBUS_DETECT BIT(0)
 
-#define BD9995X_CMD_CHGOP_STATUS	0x03
-#define BD9995X_CMD_CHGOP_STATUS_BATTEMP2	BIT(10)
-#define BD9995X_CMD_CHGOP_STATUS_BATTEMP1	BIT(9)
-#define BD9995X_CMD_CHGOP_STATUS_BATTEMP0	BIT(8)
-#define BD9995X_BATTTEMP_MASK			0x700
-#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_ROOMTEMP	0
-#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_HOT1		1
-#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_HOT2		2
-#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_HOT3		3
-#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_COLD1		4
-#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_COLD2		5
-#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_DISABLE	6
-#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_BATOPEN	7
-#define BD9995X_CMD_CHGOP_STATUS_RBOOST_UV	BIT(1)
-
-#define BD9995X_CMD_WDT_STATUS		0x04
-#define BD9995X_CMD_CUR_ILIM_VAL	0x05
-#define BD9995X_CMD_SEL_ILIM_VAL	0x06
-#define BD9995X_CMD_EXT_IBUS_LIM_SET	0x07
-#define BD9995X_CMD_EXT_ICC_LIM_SET	0x08
-#define BD9995X_CMD_IOTG_LIM_SET	0x09
-#define BD9995X_CMD_VIN_CTRL_SET	0x0A
-#define BD9995X_CMD_VIN_CTRL_SET_VSYS_PRIORITY	BIT(4)
-
-#define BD9995X_CMD_VIN_CTRL_SET_PP_BOTH_THRU  BIT(11)
+#define BD9995X_CMD_CHGOP_STATUS 0x03
+#define BD9995X_CMD_CHGOP_STATUS_BATTEMP2 BIT(10)
+#define BD9995X_CMD_CHGOP_STATUS_BATTEMP1 BIT(9)
+#define BD9995X_CMD_CHGOP_STATUS_BATTEMP0 BIT(8)
+#define BD9995X_BATTTEMP_MASK 0x700
+#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_ROOMTEMP 0
+#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_HOT1 1
+#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_HOT2 2
+#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_HOT3 3
+#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_COLD1 4
+#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_COLD2 5
+#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_DISABLE 6
+#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_BATOPEN 7
+#define BD9995X_CMD_CHGOP_STATUS_RBOOST_UV BIT(1)
+
+#define BD9995X_CMD_WDT_STATUS 0x04
+#define BD9995X_CMD_CUR_ILIM_VAL 0x05
+#define BD9995X_CMD_SEL_ILIM_VAL 0x06
+#define BD9995X_CMD_EXT_IBUS_LIM_SET 0x07
+#define BD9995X_CMD_EXT_ICC_LIM_SET 0x08
+#define BD9995X_CMD_IOTG_LIM_SET 0x09
+#define BD9995X_CMD_VIN_CTRL_SET 0x0A
+#define BD9995X_CMD_VIN_CTRL_SET_VSYS_PRIORITY BIT(4)
+
+#define BD9995X_CMD_VIN_CTRL_SET_PP_BOTH_THRU BIT(11)
 #define BD9995X_CMD_VIN_CTRL_SET_VBUS_PRIORITY BIT(7)
-#define BD9995X_CMD_VIN_CTRL_SET_VBUS_EN       BIT(6)
-#define BD9995X_CMD_VIN_CTRL_SET_VCC_EN        BIT(5)
+#define BD9995X_CMD_VIN_CTRL_SET_VBUS_EN BIT(6)
+#define BD9995X_CMD_VIN_CTRL_SET_VCC_EN BIT(5)
 
-#define BD9995X_CMD_CHGOP_SET1		0x0B
-#define BD9995X_CMD_CHGOP_SET1_DCP_2500_SEL    BIT(15)
-#define BD9995X_CMD_CHGOP_SET1_SDP_500_SEL     BIT(14)
+#define BD9995X_CMD_CHGOP_SET1 0x0B
+#define BD9995X_CMD_CHGOP_SET1_DCP_2500_SEL BIT(15)
+#define BD9995X_CMD_CHGOP_SET1_SDP_500_SEL BIT(14)
 #define BD9995X_CMD_CHGOP_SET1_ILIM_AUTO_DISEN BIT(13)
-#define BD9995X_CMD_CHGOP_SET1_VCC_BC_DISEN    BIT(11)
-#define BD9995X_CMD_CHGOP_SET1_VBUS_BC_DISEN   BIT(10)
+#define BD9995X_CMD_CHGOP_SET1_VCC_BC_DISEN BIT(11)
+#define BD9995X_CMD_CHGOP_SET1_VBUS_BC_DISEN BIT(10)
 #define BD9995X_CMD_CHGOP_SET1_SDP_CHG_TRIG_EN BIT(9)
-#define BD9995X_CMD_CHGOP_SET1_SDP_CHG_TRIG    BIT(8)
-
-#define BD9995X_CMD_CHGOP_SET2		0x0C
-#define BD9995X_CMD_CHGOP_SET2_BATT_LEARN	 BIT(8)
-#define BD9995X_CMD_CHGOP_SET2_CHG_EN		 BIT(7)
-#define BD9995X_CMD_CHGOP_SET2_USB_SUS		 BIT(6)
-#define BD9995X_CMD_CHGOP_SET2_DCDC_CLK_SEL      (3 << 2)
-#define BD9995X_CMD_CHGOP_SET2_DCDC_CLK_SEL_600  (0 << 2)
-#define BD9995X_CMD_CHGOP_SET2_DCDC_CLK_SEL_857  BIT(2)
+#define BD9995X_CMD_CHGOP_SET1_SDP_CHG_TRIG BIT(8)
+
+#define BD9995X_CMD_CHGOP_SET2 0x0C
+#define BD9995X_CMD_CHGOP_SET2_BATT_LEARN BIT(8)
+#define BD9995X_CMD_CHGOP_SET2_CHG_EN BIT(7)
+#define BD9995X_CMD_CHGOP_SET2_USB_SUS BIT(6)
+#define BD9995X_CMD_CHGOP_SET2_DCDC_CLK_SEL (3 << 2)
+#define BD9995X_CMD_CHGOP_SET2_DCDC_CLK_SEL_600 (0 << 2)
+#define BD9995X_CMD_CHGOP_SET2_DCDC_CLK_SEL_857 BIT(2)
 #define BD9995X_CMD_CHGOP_SET2_DCDC_CLK_SEL_1000 (2 << 2)
 #define BD9995X_CMD_CHGOP_SET2_DCDC_CLK_SEL_1200 (3 << 2)
 
-#define BD9995X_CMD_VBUSCLPS_TH_SET	0x0D
-#define BD9995X_CMD_VCCCLPS_TH_SET	0x0E
-#define BD9995X_CMD_CHGWDT_SET		0x0F
-#define BD9995X_CMD_BATTWDT_SET		0x10
-#define BD9995X_CMD_VSYSREG_SET		0x11
-#define BD9995X_CMD_VSYSVAL_THH_SET	0x12
-#define BD9995X_CMD_VSYSVAL_THL_SET	0x13
-#define BD9995X_CMD_ITRICH_SET		0x14
-
-#define BD9995X_CMD_IPRECH_SET		0x15
-#define BD9995X_IPRECH_MAX		1024
-
-#define BD9995X_CMD_ICHG_SET		0x16
-#define BD9995X_CMD_ITERM_SET		0x17
-#define BD9995X_CMD_VPRECHG_TH_SET	0x18
-#define BD9995X_CMD_VRBOOST_SET		0x19
-#define BD9995X_CMD_VFASTCHG_REG_SET1	0x1A
-#define BD9995X_CMD_VFASTCHG_REG_SET2	0x1B
-#define BD9995X_CMD_VFASTCHG_REG_SET3	0x1C
-#define BD9995X_CMD_VRECHG_SET		0x1D
-#define BD9995X_CMD_VBATOVP_SET		0x1E
-#define BD9995X_CMD_IBATSHORT_SET	0x1F
-#define BD9995X_CMD_PROCHOT_CTRL_SET	0x20
-#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN4	BIT(4)
-#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN3	BIT(3)
-#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN2	BIT(2)
-#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN1	BIT(1)
-#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN0	BIT(0)
-
-#define BD9995X_CMD_PROCHOT_ICRIT_SET	0x21
-#define BD9995X_CMD_PROCHOT_INORM_SET	0x22
-#define BD9995X_CMD_PROCHOT_IDCHG_SET	0x23
-#define BD9995X_CMD_PROCHOT_VSYS_SET	0x24
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET	0x25
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IMON_INSEL	BIT(9)
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_INSEL	BIT(8)
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_OUT_EN	BIT(7)
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_SOURCE_SEL	BIT(6)
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_MASK	0x30
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_40V	0x03
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V	0x02
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_10V	0x01
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_05V	0x00
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_OUT_EN	BIT(3)
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_MASK	0x07
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_64UAW	0x06
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_32UAW	0x05
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_16UAW	0x04
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_08UAW	0x03
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_04UAW	0x02
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_02UAW	0x01
-#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_01UAW	0x00
-#define BD9995X_PMON_IOUT_ADC_READ_COUNT	128
-
-#define BD9995X_CMD_PMON_DACIN_VAL	0x26
-#define BD9995X_CMD_IOUT_DACIN_VAL	0x27
-#define BD9995X_CMD_VCC_UCD_SET		0x28
+#define BD9995X_CMD_VBUSCLPS_TH_SET 0x0D
+#define BD9995X_CMD_VCCCLPS_TH_SET 0x0E
+#define BD9995X_CMD_CHGWDT_SET 0x0F
+#define BD9995X_CMD_BATTWDT_SET 0x10
+#define BD9995X_CMD_VSYSREG_SET 0x11
+#define BD9995X_CMD_VSYSVAL_THH_SET 0x12
+#define BD9995X_CMD_VSYSVAL_THL_SET 0x13
+#define BD9995X_CMD_ITRICH_SET 0x14
+
+#define BD9995X_CMD_IPRECH_SET 0x15
+#define BD9995X_IPRECH_MAX 1024
+
+#define BD9995X_CMD_ICHG_SET 0x16
+#define BD9995X_CMD_ITERM_SET 0x17
+#define BD9995X_CMD_VPRECHG_TH_SET 0x18
+#define BD9995X_CMD_VRBOOST_SET 0x19
+#define BD9995X_CMD_VFASTCHG_REG_SET1 0x1A
+#define BD9995X_CMD_VFASTCHG_REG_SET2 0x1B
+#define BD9995X_CMD_VFASTCHG_REG_SET3 0x1C
+#define BD9995X_CMD_VRECHG_SET 0x1D
+#define BD9995X_CMD_VBATOVP_SET 0x1E
+#define BD9995X_CMD_IBATSHORT_SET 0x1F
+#define BD9995X_CMD_PROCHOT_CTRL_SET 0x20
+#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN4 BIT(4)
+#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN3 BIT(3)
+#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN2 BIT(2)
+#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN1 BIT(1)
+#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN0 BIT(0)
+
+#define BD9995X_CMD_PROCHOT_ICRIT_SET 0x21
+#define BD9995X_CMD_PROCHOT_INORM_SET 0x22
+#define BD9995X_CMD_PROCHOT_IDCHG_SET 0x23
+#define BD9995X_CMD_PROCHOT_VSYS_SET 0x24
+#define BD9995X_CMD_PMON_IOUT_CTRL_SET 0x25
+#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IMON_INSEL BIT(9)
+#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_INSEL BIT(8)
+#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_OUT_EN BIT(7)
+#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_SOURCE_SEL BIT(6)
+#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_MASK 0x30
+#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_40V 0x03
+#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V 0x02
+#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_10V 0x01
+#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_05V 0x00
+#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_OUT_EN BIT(3)
+#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_MASK 0x07
+#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_64UAW 0x06
+#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_32UAW 0x05
+#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_16UAW 0x04
+#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_08UAW 0x03
+#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_04UAW 0x02
+#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_02UAW 0x01
+#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_01UAW 0x00
+#define BD9995X_PMON_IOUT_ADC_READ_COUNT 128
+
+#define BD9995X_CMD_PMON_DACIN_VAL 0x26
+#define BD9995X_CMD_IOUT_DACIN_VAL 0x27
+#define BD9995X_CMD_VCC_UCD_SET 0x28
 /* Bits for both VCC_UCD_SET and VBUS_UCD_SET regs */
 /*  Retry BC1.2 detection on set */
-#define BD9995X_CMD_UCD_SET_BCSRETRY	BIT(12)
+#define BD9995X_CMD_UCD_SET_BCSRETRY BIT(12)
 /* Enable BC1.2 detection, will automatically occur on VBUS detect */
-#define BD9995X_CMD_UCD_SET_USBDETEN	BIT(7)
+#define BD9995X_CMD_UCD_SET_USBDETEN BIT(7)
 /* USB switch state auto-control */
-#define BD9995X_CMD_UCD_SET_USB_SW_EN	BIT(1)
+#define BD9995X_CMD_UCD_SET_USB_SW_EN BIT(1)
 /* USB switch state, 1 = ON, only meaningful when USB_SW_EN = 0 */
-#define BD9995X_CMD_UCD_SET_USB_SW	BIT(0)
+#define BD9995X_CMD_UCD_SET_USB_SW BIT(0)
 
-#define BD9995X_CMD_VCC_UCD_STATUS	0x29
+#define BD9995X_CMD_VCC_UCD_STATUS 0x29
 /* Bits for both VCC_UCD_STATUS and VBUS_UCD_STATUS regs */
-#define BD9995X_CMD_UCD_STATUS_DCDFAIL	BIT(15)
-#define BD9995X_CMD_UCD_STATUS_CHGPORT1	BIT(13)
-#define BD9995X_CMD_UCD_STATUS_CHGPORT0	BIT(12)
-#define BD9995X_CMD_UCD_STATUS_PUPDET	BIT(11)
-#define BD9995X_CMD_UCD_STATUS_CHGDET	BIT(6)
-#define BD9995X_TYPE_MASK		(BD9995X_CMD_UCD_STATUS_DCDFAIL | \
-					 BD9995X_CMD_UCD_STATUS_CHGPORT1 | \
-					 BD9995X_CMD_UCD_STATUS_CHGPORT0 | \
-					 BD9995X_CMD_UCD_STATUS_PUPDET | \
-					 BD9995X_CMD_UCD_STATUS_CHGDET)
+#define BD9995X_CMD_UCD_STATUS_DCDFAIL BIT(15)
+#define BD9995X_CMD_UCD_STATUS_CHGPORT1 BIT(13)
+#define BD9995X_CMD_UCD_STATUS_CHGPORT0 BIT(12)
+#define BD9995X_CMD_UCD_STATUS_PUPDET BIT(11)
+#define BD9995X_CMD_UCD_STATUS_CHGDET BIT(6)
+#define BD9995X_TYPE_MASK                                                   \
+	(BD9995X_CMD_UCD_STATUS_DCDFAIL | BD9995X_CMD_UCD_STATUS_CHGPORT1 | \
+	 BD9995X_CMD_UCD_STATUS_CHGPORT0 | BD9995X_CMD_UCD_STATUS_PUPDET |  \
+	 BD9995X_CMD_UCD_STATUS_CHGDET)
 
 /* BC1.2 chargers */
-#define BD9995X_TYPE_CDP		(BD9995X_CMD_UCD_STATUS_CHGPORT1 | \
-					 BD9995X_CMD_UCD_STATUS_CHGDET)
-#define BD9995X_TYPE_DCP		(BD9995X_CMD_UCD_STATUS_CHGPORT1 | \
-					 BD9995X_CMD_UCD_STATUS_CHGPORT0 | \
-					 BD9995X_CMD_UCD_STATUS_CHGDET)
-#define BD9995X_TYPE_SDP		(BD9995X_CMD_UCD_STATUS_CHGPORT0)
+#define BD9995X_TYPE_CDP \
+	(BD9995X_CMD_UCD_STATUS_CHGPORT1 | BD9995X_CMD_UCD_STATUS_CHGDET)
+#define BD9995X_TYPE_DCP                                                     \
+	(BD9995X_CMD_UCD_STATUS_CHGPORT1 | BD9995X_CMD_UCD_STATUS_CHGPORT0 | \
+	 BD9995X_CMD_UCD_STATUS_CHGDET)
+#define BD9995X_TYPE_SDP (BD9995X_CMD_UCD_STATUS_CHGPORT0)
 /* non-standard BC1.2 chargers */
-#define BD9995X_TYPE_OTHER		(BD9995X_CMD_UCD_STATUS_DCDFAIL | \
-					 BD9995X_CMD_UCD_STATUS_CHGPORT1 | \
-					 BD9995X_CMD_UCD_STATUS_CHGPORT0 | \
-					 BD9995X_CMD_UCD_STATUS_CHGDET)
-#define BD9995X_TYPE_PUP_PORT		(BD9995X_CMD_UCD_STATUS_DCDFAIL | \
-					 BD9995X_CMD_UCD_STATUS_CHGPORT0 | \
-					 BD9995X_CMD_UCD_STATUS_PUPDET)
+#define BD9995X_TYPE_OTHER                                                  \
+	(BD9995X_CMD_UCD_STATUS_DCDFAIL | BD9995X_CMD_UCD_STATUS_CHGPORT1 | \
+	 BD9995X_CMD_UCD_STATUS_CHGPORT0 | BD9995X_CMD_UCD_STATUS_CHGDET)
+#define BD9995X_TYPE_PUP_PORT                                               \
+	(BD9995X_CMD_UCD_STATUS_DCDFAIL | BD9995X_CMD_UCD_STATUS_CHGPORT0 | \
+	 BD9995X_CMD_UCD_STATUS_PUPDET)
 /* Open ports */
-#define BD9995X_TYPE_OPEN_PORT		(BD9995X_CMD_UCD_STATUS_DCDFAIL | \
-					 BD9995X_CMD_UCD_STATUS_CHGPORT0)
-#define BD9995X_TYPE_VBUS_OPEN		0
-
-#define BD9995X_CMD_VCC_IDD_STATUS	0x2A
-#define BD9995X_CMD_VCC_UCD_FCTRL_SET	0x2B
-#define BD9995X_CMD_VCC_UCD_FCTRL_EN	0x2C
-#define BD9995X_CMD_VBUS_UCD_SET	0x30
-#define BD9995X_CMD_VBUS_UCD_STATUS	0x31
-#define BD9995X_CMD_VBUS_IDD_STATUS	0x32
-#define BD9995X_CMD_VBUS_UCD_FCTRL_SET	0x33
-#define BD9995X_CMD_VBUS_UCD_FCTRL_EN	0x34
-#define BD9995X_CMD_CHIP_ID		0x38
-#define BD9995X_CMD_CHIP_REV		0x39
-#define BD9995X_CMD_IC_SET1		0x3A
-#define BD9995X_CMD_IC_SET2		0x3B
-#define BD9995X_CMD_SYSTEM_STATUS	0x3C
-#define BD9995X_CMD_SYSTEM_STATUS_OTPLD_STATE	BIT(1)
-#define BD9995X_CMD_SYSTEM_STATUS_ALLRST_STATE	BIT(0)
-
-#define BD9995X_CMD_SYSTEM_CTRL_SET	0x3D
-#define BD9995X_CMD_SYSTEM_CTRL_SET_OTPLD	BIT(1)
-#define BD9995X_CMD_SYSTEM_CTRL_SET_ALLRST	BIT(0)
-
-#define BD9995X_CMD_EXT_PROTECT_SET	0x3E
-#define BD9995X_CMD_EXT_MAP_SET		0x3F
-#define BD9995X_CMD_VM_CTRL_SET		0x40
-#define BD9995X_CMD_VM_CTRL_SET_EXTIADPEN	BIT(9)
-#define BD9995X_CMD_THERM_WINDOW_SET1	0x41
-#define BD9995X_CMD_THERM_WINDOW_SET2	0x42
-#define BD9995X_CMD_THERM_WINDOW_SET3	0x43
-#define BD9995X_CMD_THERM_WINDOW_SET4	0x44
-#define BD9995X_CMD_THERM_WINDOW_SET5	0x45
-#define BD9995X_CMD_IBATP_TH_SET	0x46
-#define BD9995X_CMD_IBATM_TH_SET	0x47
-#define BD9995X_CMD_VBAT_TH_SET		0x48
-#define BD9995X_CMD_THERM_TH_SET	0x49
-#define BD9995X_CMD_IACP_TH_SET		0x4A
-#define BD9995X_CMD_VACP_TH_SET		0x4B
+#define BD9995X_TYPE_OPEN_PORT \
+	(BD9995X_CMD_UCD_STATUS_DCDFAIL | BD9995X_CMD_UCD_STATUS_CHGPORT0)
+#define BD9995X_TYPE_VBUS_OPEN 0
+
+#define BD9995X_CMD_VCC_IDD_STATUS 0x2A
+#define BD9995X_CMD_VCC_UCD_FCTRL_SET 0x2B
+#define BD9995X_CMD_VCC_UCD_FCTRL_EN 0x2C
+#define BD9995X_CMD_VBUS_UCD_SET 0x30
+#define BD9995X_CMD_VBUS_UCD_STATUS 0x31
+#define BD9995X_CMD_VBUS_IDD_STATUS 0x32
+#define BD9995X_CMD_VBUS_UCD_FCTRL_SET 0x33
+#define BD9995X_CMD_VBUS_UCD_FCTRL_EN 0x34
+#define BD9995X_CMD_CHIP_ID 0x38
+#define BD9995X_CMD_CHIP_REV 0x39
+#define BD9995X_CMD_IC_SET1 0x3A
+#define BD9995X_CMD_IC_SET2 0x3B
+#define BD9995X_CMD_SYSTEM_STATUS 0x3C
+#define BD9995X_CMD_SYSTEM_STATUS_OTPLD_STATE BIT(1)
+#define BD9995X_CMD_SYSTEM_STATUS_ALLRST_STATE BIT(0)
+
+#define BD9995X_CMD_SYSTEM_CTRL_SET 0x3D
+#define BD9995X_CMD_SYSTEM_CTRL_SET_OTPLD BIT(1)
+#define BD9995X_CMD_SYSTEM_CTRL_SET_ALLRST BIT(0)
+
+#define BD9995X_CMD_EXT_PROTECT_SET 0x3E
+#define BD9995X_CMD_EXT_MAP_SET 0x3F
+#define BD9995X_CMD_VM_CTRL_SET 0x40
+#define BD9995X_CMD_VM_CTRL_SET_EXTIADPEN BIT(9)
+#define BD9995X_CMD_THERM_WINDOW_SET1 0x41
+#define BD9995X_CMD_THERM_WINDOW_SET2 0x42
+#define BD9995X_CMD_THERM_WINDOW_SET3 0x43
+#define BD9995X_CMD_THERM_WINDOW_SET4 0x44
+#define BD9995X_CMD_THERM_WINDOW_SET5 0x45
+#define BD9995X_CMD_IBATP_TH_SET 0x46
+#define BD9995X_CMD_IBATM_TH_SET 0x47
+#define BD9995X_CMD_VBAT_TH_SET 0x48
+#define BD9995X_CMD_THERM_TH_SET 0x49
+#define BD9995X_CMD_IACP_TH_SET 0x4A
+#define BD9995X_CMD_VACP_TH_SET 0x4B
 
 /* Enable discharge when VBUS falls below BD9995X_VBUS_DISCHARGE_TH */
-#define BD9995X_VBUS_DISCHARGE_TH	3900
-#define BD9995X_CMD_VBUS_TH_SET		0x4C
-#define BD9995X_CMD_VCC_TH_SET		0x4D
-
-#define BD9995X_CMD_VSYS_TH_SET		0x4E
-#define BD9995X_CMD_EXTIADP_TH_SET	0x4F
-#define BD9995X_CMD_IBATP_VAL		0x50
-#define BD9995X_CMD_IBATP_AVE_VAL	0x51
-#define BD9995X_CMD_IBATM_VAL		0x52
-#define BD9995X_CMD_IBATM_AVE_VAL	0x53
-#define BD9995X_CMD_VBAT_VAL		0x54
-#define BD9995X_CMD_VBAT_AVE_VAL	0x55
-#define BD9995X_CMD_THERM_VAL		0x56
-#define BD9995X_CMD_VTH_VAL		0x57
-#define BD9995X_CMD_IACP_VAL		0x58
-#define BD9995X_CMD_IACP_AVE_VAL	0x59
-#define BD9995X_CMD_VACP_VAL		0x5A
-#define BD9995X_CMD_VACP_AVE_VAL	0x5B
-#define BD9995X_CMD_VBUS_VAL		0x5C
-#define BD9995X_CMD_VBUS_AVE_VAL	0x5D
-#define BD9995X_CMD_VCC_VAL		0x5E
-#define BD9995X_CMD_VCC_AVE_VAL		0x5F
-#define BD9995X_CMD_VSYS_VAL		0x60
-#define BD9995X_CMD_VSYS_AVE_VAL	0x61
-#define BD9995X_CMD_EXTIADP_VAL		0x62
-#define BD9995X_CMD_EXTIADP_AVE_VAL	0x63
-#define BD9995X_CMD_VACPCLPS_TH_SET	0x64
-#define BD9995X_CMD_INT0_SET		0x68
-#define BD9995X_CMD_INT0_SET_INT2_EN	BIT(2)
-#define BD9995X_CMD_INT0_SET_INT1_EN	BIT(1)
-#define BD9995X_CMD_INT0_SET_INT0_EN	BIT(0)
-
-#define BD9995X_CMD_INT1_SET		0x69
+#define BD9995X_VBUS_DISCHARGE_TH 3900
+#define BD9995X_CMD_VBUS_TH_SET 0x4C
+#define BD9995X_CMD_VCC_TH_SET 0x4D
+
+#define BD9995X_CMD_VSYS_TH_SET 0x4E
+#define BD9995X_CMD_EXTIADP_TH_SET 0x4F
+#define BD9995X_CMD_IBATP_VAL 0x50
+#define BD9995X_CMD_IBATP_AVE_VAL 0x51
+#define BD9995X_CMD_IBATM_VAL 0x52
+#define BD9995X_CMD_IBATM_AVE_VAL 0x53
+#define BD9995X_CMD_VBAT_VAL 0x54
+#define BD9995X_CMD_VBAT_AVE_VAL 0x55
+#define BD9995X_CMD_THERM_VAL 0x56
+#define BD9995X_CMD_VTH_VAL 0x57
+#define BD9995X_CMD_IACP_VAL 0x58
+#define BD9995X_CMD_IACP_AVE_VAL 0x59
+#define BD9995X_CMD_VACP_VAL 0x5A
+#define BD9995X_CMD_VACP_AVE_VAL 0x5B
+#define BD9995X_CMD_VBUS_VAL 0x5C
+#define BD9995X_CMD_VBUS_AVE_VAL 0x5D
+#define BD9995X_CMD_VCC_VAL 0x5E
+#define BD9995X_CMD_VCC_AVE_VAL 0x5F
+#define BD9995X_CMD_VSYS_VAL 0x60
+#define BD9995X_CMD_VSYS_AVE_VAL 0x61
+#define BD9995X_CMD_EXTIADP_VAL 0x62
+#define BD9995X_CMD_EXTIADP_AVE_VAL 0x63
+#define BD9995X_CMD_VACPCLPS_TH_SET 0x64
+#define BD9995X_CMD_INT0_SET 0x68
+#define BD9995X_CMD_INT0_SET_INT2_EN BIT(2)
+#define BD9995X_CMD_INT0_SET_INT1_EN BIT(1)
+#define BD9995X_CMD_INT0_SET_INT0_EN BIT(0)
+
+#define BD9995X_CMD_INT1_SET 0x69
 /* Bits for both INT1 & INT2 reg */
-#define BD9995X_CMD_INT_SET_TH_DET	BIT(9)
-#define BD9995X_CMD_INT_SET_TH_RES	BIT(8)
-#define BD9995X_CMD_INT_SET_DET		BIT(1)
-#define BD9995X_CMD_INT_SET_RES		BIT(0)
-#define BD9995X_CMD_INT_VBUS_DET	(BD9995X_CMD_INT_SET_RES | \
-					 BD9995X_CMD_INT_SET_DET)
-#define BD9995X_CMD_INT_VBUS_TH         (BD9995X_CMD_INT_SET_TH_RES | \
-					 BD9995X_CMD_INT_SET_TH_DET)
-
-#define BD9995X_CMD_INT2_SET		0x6A
-#define BD9995X_CMD_INT3_SET		0x6B
-#define BD9995X_CMD_INT4_SET		0x6C
-#define BD9995X_CMD_INT5_SET		0x6D
-#define BD9995X_CMD_INT6_SET		0x6E
-#define BD9995X_CMD_INT7_SET		0x6F
-#define BD9995X_CMD_INT0_STATUS		0x70
-#define BD9995X_CMD_INT1_STATUS		0x71
+#define BD9995X_CMD_INT_SET_TH_DET BIT(9)
+#define BD9995X_CMD_INT_SET_TH_RES BIT(8)
+#define BD9995X_CMD_INT_SET_DET BIT(1)
+#define BD9995X_CMD_INT_SET_RES BIT(0)
+#define BD9995X_CMD_INT_VBUS_DET \
+	(BD9995X_CMD_INT_SET_RES | BD9995X_CMD_INT_SET_DET)
+#define BD9995X_CMD_INT_VBUS_TH \
+	(BD9995X_CMD_INT_SET_TH_RES | BD9995X_CMD_INT_SET_TH_DET)
+
+#define BD9995X_CMD_INT2_SET 0x6A
+#define BD9995X_CMD_INT3_SET 0x6B
+#define BD9995X_CMD_INT4_SET 0x6C
+#define BD9995X_CMD_INT5_SET 0x6D
+#define BD9995X_CMD_INT6_SET 0x6E
+#define BD9995X_CMD_INT7_SET 0x6F
+#define BD9995X_CMD_INT0_STATUS 0x70
+#define BD9995X_CMD_INT1_STATUS 0x71
 /* Bits for both INT1_STATUS & INT2_STATUS reg */
-#define BD9995X_CMD_INT_STATUS_DET	BIT(1)
-#define BD9995X_CMD_INT_STATUS_RES	BIT(0)
-
-#define BD9995X_CMD_INT2_STATUS		0x72
-#define BD9995X_CMD_INT3_STATUS		0x73
-#define BD9995X_CMD_INT4_STATUS		0x74
-#define BD9995X_CMD_INT5_STATUS		0x75
-#define BD9995X_CMD_INT6_STATUS		0x76
-#define BD9995X_CMD_INT7_STATUS		0x77
-#define BD9995X_CMD_REG0		0x78
-#define BD9995X_CMD_REG1		0x79
-#define BD9995X_CMD_OTPREG0		0x7A
-#define BD9995X_CMD_OTPREG1		0x7B
-#define BD9995X_CMD_SMBREG		0x7C
+#define BD9995X_CMD_INT_STATUS_DET BIT(1)
+#define BD9995X_CMD_INT_STATUS_RES BIT(0)
+
+#define BD9995X_CMD_INT2_STATUS 0x72
+#define BD9995X_CMD_INT3_STATUS 0x73
+#define BD9995X_CMD_INT4_STATUS 0x74
+#define BD9995X_CMD_INT5_STATUS 0x75
+#define BD9995X_CMD_INT6_STATUS 0x76
+#define BD9995X_CMD_INT7_STATUS 0x77
+#define BD9995X_CMD_REG0 0x78
+#define BD9995X_CMD_REG1 0x79
+#define BD9995X_CMD_OTPREG0 0x7A
+#define BD9995X_CMD_OTPREG1 0x7B
+#define BD9995X_CMD_SMBREG 0x7C
 /* Normal functionality - power save mode disabled. */
-#define BD9995X_PWR_SAVE_OFF		0
+#define BD9995X_PWR_SAVE_OFF 0
 /* BGATE ON w/ PROCHOT# monitored only system voltage. */
-#define BD9995X_PWR_SAVE_LOW		0x1
+#define BD9995X_PWR_SAVE_LOW 0x1
 /* BGATE ON w/ PROCHOT# monitored only system voltage every 1ms. */
-#define BD9995X_PWR_SAVE_MED		0x2
+#define BD9995X_PWR_SAVE_MED 0x2
 /* BGATE ON w/o PROCHOT# monitoring. */
-#define BD9995X_PWR_SAVE_HIGH		0x5
+#define BD9995X_PWR_SAVE_HIGH 0x5
 /* BGATE OFF */
-#define BD9995X_PWR_SAVE_MAX		0x6
-#define BD9995X_CMD_DEBUG_MODE_SET	0x7F
+#define BD9995X_PWR_SAVE_MAX 0x6
+#define BD9995X_CMD_DEBUG_MODE_SET 0x7F
 
 /*
  * Non-standard interface functions - bd9995x integrates additional
diff --git a/driver/charger/bq24715.c b/driver/charger/bq24715.c
index d2eb0e432a..8e8e0efd50 100644
--- a/driver/charger/bq24715.c
+++ b/driver/charger/bq24715.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -16,37 +16,35 @@
 /* Sense resistor configurations and macros */
 #define DEFAULT_SENSE_RESISTOR 10
 #define R_SNS CONFIG_CHARGER_SENSE_RESISTOR
-#define R_AC  CONFIG_CHARGER_SENSE_RESISTOR_AC
-#define REG_TO_CURRENT(REG, RS) ((REG) * DEFAULT_SENSE_RESISTOR / (RS))
+#define R_AC CONFIG_CHARGER_SENSE_RESISTOR_AC
+#define REG_TO_CURRENT(REG, RS) ((REG)*DEFAULT_SENSE_RESISTOR / (RS))
 #define CURRENT_TO_REG(CUR, RS) ((CUR) * (RS) / DEFAULT_SENSE_RESISTOR)
 
 /* Note: it is assumed that the sense resistors are 10mOhm. */
 
 static const struct charger_info bq24715_charger_info = {
-	.name         = "bq24715",
-	.voltage_max  = CHARGE_V_MAX,
-	.voltage_min  = CHARGE_V_MIN,
+	.name = "bq24715",
+	.voltage_max = CHARGE_V_MAX,
+	.voltage_min = CHARGE_V_MIN,
 	.voltage_step = CHARGE_V_STEP,
-	.current_max  = REG_TO_CURRENT(CHARGE_I_MAX, R_SNS),
-	.current_min  = REG_TO_CURRENT(CHARGE_I_MIN, R_SNS),
+	.current_max = REG_TO_CURRENT(CHARGE_I_MAX, R_SNS),
+	.current_min = REG_TO_CURRENT(CHARGE_I_MIN, R_SNS),
 	.current_step = REG_TO_CURRENT(CHARGE_I_STEP, R_SNS),
-	.input_current_max  = REG_TO_CURRENT(INPUT_I_MAX, R_AC),
-	.input_current_min  = REG_TO_CURRENT(INPUT_I_MIN, R_AC),
+	.input_current_max = REG_TO_CURRENT(INPUT_I_MAX, R_AC),
+	.input_current_min = REG_TO_CURRENT(INPUT_I_MIN, R_AC),
 	.input_current_step = REG_TO_CURRENT(INPUT_I_STEP, R_AC),
 };
 
 static inline enum ec_error_list sbc_read(int chgnum, int cmd, int *param)
 {
 	return i2c_read16(chg_chips[chgnum].i2c_port,
-			  chg_chips[chgnum].i2c_addr_flags,
-			  cmd, param);
+			  chg_chips[chgnum].i2c_addr_flags, cmd, param);
 }
 
 static inline enum ec_error_list sbc_write(int chgnum, int cmd, int param)
 {
 	return i2c_write16(chg_chips[chgnum].i2c_port,
-			   chg_chips[chgnum].i2c_addr_flags,
-			   cmd, param);
+			   chg_chips[chgnum].i2c_addr_flags, cmd, param);
 }
 
 static enum ec_error_list bq24715_set_input_current_limit(int chgnum,
diff --git a/driver/charger/bq24715.h b/driver/charger/bq24715.h
index 644f995f2e..905cdf47be 100644
--- a/driver/charger/bq24715.h
+++ b/driver/charger/bq24715.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -14,118 +14,117 @@
  */
 
 /* Chip specific registers */
-#define BQ24715_CHARGE_OPTION           0x12
-#define BQ24715_CHARGE_CURRENT          0x14
-#define BQ24715_MAX_CHARGE_VOLTAGE      0x15
-#define BQ24715_MIN_SYSTEM_VOLTAGE      0x3e
-#define BQ24715_INPUT_CURRENT           0x3f
-#define BQ24715_MANUFACTURER_ID         0xfe
-#define BQ24715_DEVICE_ID               0xff
+#define BQ24715_CHARGE_OPTION 0x12
+#define BQ24715_CHARGE_CURRENT 0x14
+#define BQ24715_MAX_CHARGE_VOLTAGE 0x15
+#define BQ24715_MIN_SYSTEM_VOLTAGE 0x3e
+#define BQ24715_INPUT_CURRENT 0x3f
+#define BQ24715_MANUFACTURER_ID 0xfe
+#define BQ24715_DEVICE_ID 0xff
 
 /* ChargeOption Register - 0x12 */
-#define OPT_LOWPOWER_MASK               BIT(15)
-#define   OPT_LOWPOWER_DSCHRG_I_MON_ON    (0 << 15)
-#define   OPT_LOWPOWER_DSCHRG_I_MON_OFF   BIT(15)
-#define OPT_WATCHDOG_MASK               (3 << 13)
-#define   OPT_WATCHDOG_DISABLE            (0 << 13)
-#define   OPT_WATCHDOG_44SEC              BIT(13)
-#define   OPT_WATCHDOG_88SEC              (2 << 13)
-#define   OPT_WATCHDOG_175SEC             (3 << 13)
-#define OPT_SYSOVP_MASK                 BIT(12)
-#define   OPT_SYSOVP_15P1_3SEC_10P1_2SEC  (0 << 12)
-#define   OPT_SYSOVP_17P0_3SEC_11P3_2SEC  BIT(12)
-#define OPT_SYSOVP_STATUS_MASK          BIT(11)
-#define   OPT_SYSOVP_STATUS               BIT(11)
-#define OPT_AUDIO_FREQ_LIMIT_MASK       BIT(10)
-#define   OPT_AUDIO_FREQ_NO_LIMIT         (0 << 10)
-#define   OPT_AUDIO_FREQ_40KHZ_LIMIT      BIT(10)
-#define OPT_SWITCH_FREQ_MASK            (3 << 8)
-#define   OPT_SWITCH_FREQ_600KHZ          (0 << 8)
-#define   OPT_SWITCH_FREQ_800KHZ          BIT(8)
-#define   OPT_SWITCH_FREQ_1MHZ            (2 << 8)
-#define   OPT_SWITCH_FREQ_800KHZ_DUP      (3 << 8)
-#define OPT_ACOC_MASK                   BIT(7)
-#define   OPT_ACOC_DISABLED               (0 << 7)
-#define   OPT_ACOC_333PCT_IPDM            BIT(7)
-#define OPT_LSFET_OCP_MASK              BIT(6)
-#define   OPT_LSFET_OCP_250MV             (0 << 6)
-#define   OPT_LSFET_OCP_350MV             BIT(6)
-#define OPT_LEARN_MASK                  BIT(5)
-#define   OPT_LEARN_DISABLE               (0 << 5)
-#define   OPT_LEARN_ENABLE                BIT(5)
-#define OPT_IOUT_MASK                   BIT(4)
-#define   OPT_IOUT_40X                    (0 << 4)
-#define   OPT_IOUT_16X                    BIT(4)
-#define OPT_FIX_IOUT_MASK               BIT(3)
-#define   OPT_FIX_IOUT_IDPM_EN            (0 << 3)
-#define   OPT_FIX_IOUT_ALWAYS             BIT(3)
-#define OPT_LDO_MODE_MASK               BIT(2)
-#define   OPT_LDO_DISABLE                 (0 << 2)
-#define   OPT_LDO_ENABLE                  BIT(2)
-#define OPT_IDPM_MASK                   BIT(1)
-#define   OPT_IDPM_DISABLE                (0 << 1)
-#define   OPT_IDPM_ENABLE                 BIT(1)
-#define OPT_CHARGE_INHIBIT_MASK         BIT(0)
-#define   OPT_CHARGE_ENABLE               (0 << 0)
-#define   OPT_CHARGE_DISABLE              BIT(0)
-
+#define OPT_LOWPOWER_MASK BIT(15)
+#define OPT_LOWPOWER_DSCHRG_I_MON_ON (0 << 15)
+#define OPT_LOWPOWER_DSCHRG_I_MON_OFF BIT(15)
+#define OPT_WATCHDOG_MASK (3 << 13)
+#define OPT_WATCHDOG_DISABLE (0 << 13)
+#define OPT_WATCHDOG_44SEC BIT(13)
+#define OPT_WATCHDOG_88SEC (2 << 13)
+#define OPT_WATCHDOG_175SEC (3 << 13)
+#define OPT_SYSOVP_MASK BIT(12)
+#define OPT_SYSOVP_15P1_3SEC_10P1_2SEC (0 << 12)
+#define OPT_SYSOVP_17P0_3SEC_11P3_2SEC BIT(12)
+#define OPT_SYSOVP_STATUS_MASK BIT(11)
+#define OPT_SYSOVP_STATUS BIT(11)
+#define OPT_AUDIO_FREQ_LIMIT_MASK BIT(10)
+#define OPT_AUDIO_FREQ_NO_LIMIT (0 << 10)
+#define OPT_AUDIO_FREQ_40KHZ_LIMIT BIT(10)
+#define OPT_SWITCH_FREQ_MASK (3 << 8)
+#define OPT_SWITCH_FREQ_600KHZ (0 << 8)
+#define OPT_SWITCH_FREQ_800KHZ BIT(8)
+#define OPT_SWITCH_FREQ_1MHZ (2 << 8)
+#define OPT_SWITCH_FREQ_800KHZ_DUP (3 << 8)
+#define OPT_ACOC_MASK BIT(7)
+#define OPT_ACOC_DISABLED (0 << 7)
+#define OPT_ACOC_333PCT_IPDM BIT(7)
+#define OPT_LSFET_OCP_MASK BIT(6)
+#define OPT_LSFET_OCP_250MV (0 << 6)
+#define OPT_LSFET_OCP_350MV BIT(6)
+#define OPT_LEARN_MASK BIT(5)
+#define OPT_LEARN_DISABLE (0 << 5)
+#define OPT_LEARN_ENABLE BIT(5)
+#define OPT_IOUT_MASK BIT(4)
+#define OPT_IOUT_40X (0 << 4)
+#define OPT_IOUT_16X BIT(4)
+#define OPT_FIX_IOUT_MASK BIT(3)
+#define OPT_FIX_IOUT_IDPM_EN (0 << 3)
+#define OPT_FIX_IOUT_ALWAYS BIT(3)
+#define OPT_LDO_MODE_MASK BIT(2)
+#define OPT_LDO_DISABLE (0 << 2)
+#define OPT_LDO_ENABLE BIT(2)
+#define OPT_IDPM_MASK BIT(1)
+#define OPT_IDPM_DISABLE (0 << 1)
+#define OPT_IDPM_ENABLE BIT(1)
+#define OPT_CHARGE_INHIBIT_MASK BIT(0)
+#define OPT_CHARGE_ENABLE (0 << 0)
+#define OPT_CHARGE_DISABLE BIT(0)
 
 /* ChargeCurrent Register - 0x14
  * The ChargeCurrent register controls a DAC. Therefore
  * the below definitions are cummulative. */
-#define CHARGE_I_64MA                   BIT(6)
-#define CHARGE_I_128MA                  BIT(7)
-#define CHARGE_I_256MA                  BIT(8)
-#define CHARGE_I_512MA                  BIT(9)
-#define CHARGE_I_1024MA                 BIT(10)
-#define CHARGE_I_2048MA                 BIT(11)
-#define CHARGE_I_4096MA                 BIT(12)
-#define CHARGE_I_OFF                    (0)
-#define CHARGE_I_MIN                    (128)
-#define CHARGE_I_MAX                    (8128)
-#define CHARGE_I_STEP                   (64)
+#define CHARGE_I_64MA BIT(6)
+#define CHARGE_I_128MA BIT(7)
+#define CHARGE_I_256MA BIT(8)
+#define CHARGE_I_512MA BIT(9)
+#define CHARGE_I_1024MA BIT(10)
+#define CHARGE_I_2048MA BIT(11)
+#define CHARGE_I_4096MA BIT(12)
+#define CHARGE_I_OFF (0)
+#define CHARGE_I_MIN (128)
+#define CHARGE_I_MAX (8128)
+#define CHARGE_I_STEP (64)
 
 /* MaxChargeVoltage Register - 0x15
  * The MaxChargeVoltage register controls a DAC. Therefore
  * the below definitions are cummulative. */
-#define CHARGE_V_16MV                   BIT(4)
-#define CHARGE_V_32MV                   BIT(5)
-#define CHARGE_V_64MV                   BIT(6)
-#define CHARGE_V_128MV                  BIT(7)
-#define CHARGE_V_256MV                  BIT(8)
-#define CHARGE_V_512MV                  BIT(9)
-#define CHARGE_V_1024MV                 BIT(10)
-#define CHARGE_V_2048MV                 BIT(11)
-#define CHARGE_V_4096MV                 BIT(12)
-#define CHARGE_V_8192MV                 BIT(13)
-#define CHARGE_V_MIN                    (4096)
-#define CHARGE_V_MAX                    (0x3ff0)
-#define CHARGE_V_STEP                   (16)
+#define CHARGE_V_16MV BIT(4)
+#define CHARGE_V_32MV BIT(5)
+#define CHARGE_V_64MV BIT(6)
+#define CHARGE_V_128MV BIT(7)
+#define CHARGE_V_256MV BIT(8)
+#define CHARGE_V_512MV BIT(9)
+#define CHARGE_V_1024MV BIT(10)
+#define CHARGE_V_2048MV BIT(11)
+#define CHARGE_V_4096MV BIT(12)
+#define CHARGE_V_8192MV BIT(13)
+#define CHARGE_V_MIN (4096)
+#define CHARGE_V_MAX (0x3ff0)
+#define CHARGE_V_STEP (16)
 
 /* MinSystemVoltage Register - 0x3e
  * The MinSystemVoltage register controls a DAC. Therefore
  * the below definitions are cummulative. */
-#define MIN_SYS_V_256MV                 BIT(8)
-#define MIN_SYS_V_512MV                 BIT(9)
-#define MIN_SYS_V_1024MV                BIT(10)
-#define MIN_SYS_V_2048MV                BIT(11)
-#define MIN_SYS_V_4096MV                BIT(12)
-#define MIN_SYS_V_8192MV                BIT(13)
-#define MIN_SYS_V_MIN                   (4096)
+#define MIN_SYS_V_256MV BIT(8)
+#define MIN_SYS_V_512MV BIT(9)
+#define MIN_SYS_V_1024MV BIT(10)
+#define MIN_SYS_V_2048MV BIT(11)
+#define MIN_SYS_V_4096MV BIT(12)
+#define MIN_SYS_V_8192MV BIT(13)
+#define MIN_SYS_V_MIN (4096)
 
 /* InputCurrent Register - 0x3f
  * The InputCurrent register controls a DAC. Therefore
  * the below definitions are cummulative. */
-#define INPUT_I_64MA                   BIT(6)
-#define INPUT_I_128MA                  BIT(7)
-#define INPUT_I_256MA                  BIT(8)
-#define INPUT_I_512MA                  BIT(9)
-#define INPUT_I_1024MA                 BIT(10)
-#define INPUT_I_2048MA                 BIT(11)
-#define INPUT_I_4096MA                 BIT(12)
-#define INPUT_I_MIN                    (128)
-#define INPUT_I_MAX                    (8064)
-#define INPUT_I_STEP                   (64)
+#define INPUT_I_64MA BIT(6)
+#define INPUT_I_128MA BIT(7)
+#define INPUT_I_256MA BIT(8)
+#define INPUT_I_512MA BIT(9)
+#define INPUT_I_1024MA BIT(10)
+#define INPUT_I_2048MA BIT(11)
+#define INPUT_I_4096MA BIT(12)
+#define INPUT_I_MIN (128)
+#define INPUT_I_MAX (8064)
+#define INPUT_I_STEP (64)
 
 extern const struct charger_drv bq24715_drv;
 
diff --git a/driver/charger/bq24773.c b/driver/charger/bq24773.c
index d242f105c6..bfa0aa36e7 100644
--- a/driver/charger/bq24773.c
+++ b/driver/charger/bq24773.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -22,39 +22,39 @@
 /* Sense resistor configurations and macros */
 #define DEFAULT_SENSE_RESISTOR 10
 #define R_SNS CONFIG_CHARGER_SENSE_RESISTOR
-#define R_AC  (CONFIG_CHARGER_SENSE_RESISTOR_AC)
-#define REG_TO_CURRENT(REG, RS) ((REG) * DEFAULT_SENSE_RESISTOR / (RS))
+#define R_AC (CONFIG_CHARGER_SENSE_RESISTOR_AC)
+#define REG_TO_CURRENT(REG, RS) ((REG)*DEFAULT_SENSE_RESISTOR / (RS))
 #define CURRENT_TO_REG(CUR, RS) ((CUR) * (RS) / DEFAULT_SENSE_RESISTOR)
-#define REG8_TO_CURRENT(REG, RS) ((REG) * DEFAULT_SENSE_RESISTOR / (RS) * R8)
+#define REG8_TO_CURRENT(REG, RS) ((REG)*DEFAULT_SENSE_RESISTOR / (RS)*R8)
 #define CURRENT_TO_REG8(CUR, RS) ((CUR) * (RS) / DEFAULT_SENSE_RESISTOR / R8)
 
 /* ChargeCurrent Register - 0x14 (mA) */
-#define CHARGE_I_OFF                    0
-#define CHARGE_I_MIN                    128
-#define CHARGE_I_MAX                    8128
-#define CHARGE_I_STEP                   64
+#define CHARGE_I_OFF 0
+#define CHARGE_I_MIN 128
+#define CHARGE_I_MAX 8128
+#define CHARGE_I_STEP 64
 
 /* MaxChargeVoltage Register - 0x15 (mV) */
-#define CHARGE_V_MIN                    1024
-#define CHARGE_V_MAX                    19200
-#define CHARGE_V_STEP                   16
+#define CHARGE_V_MIN 1024
+#define CHARGE_V_MAX 19200
+#define CHARGE_V_STEP 16
 
 /* InputCurrent Register - 0x3f (mA) */
-#define INPUT_I_MIN                    128
-#define INPUT_I_MAX                    8128
-#define INPUT_I_STEP                   64
+#define INPUT_I_MIN 128
+#define INPUT_I_MAX 8128
+#define INPUT_I_STEP 64
 
 /* Charger parameters */
 static const struct charger_info bq2477x_charger_info = {
-	.name         = CHARGER_NAME,
-	.voltage_max  = CHARGE_V_MAX,
-	.voltage_min  = CHARGE_V_MIN,
+	.name = CHARGER_NAME,
+	.voltage_max = CHARGE_V_MAX,
+	.voltage_min = CHARGE_V_MIN,
 	.voltage_step = CHARGE_V_STEP,
-	.current_max  = REG_TO_CURRENT(CHARGE_I_MAX, R_SNS),
-	.current_min  = REG_TO_CURRENT(CHARGE_I_MIN, R_SNS),
+	.current_max = REG_TO_CURRENT(CHARGE_I_MAX, R_SNS),
+	.current_min = REG_TO_CURRENT(CHARGE_I_MIN, R_SNS),
 	.current_step = REG_TO_CURRENT(CHARGE_I_STEP, R_SNS),
-	.input_current_max  = REG_TO_CURRENT(INPUT_I_MAX, R_AC),
-	.input_current_min  = REG_TO_CURRENT(INPUT_I_MIN, R_AC),
+	.input_current_max = REG_TO_CURRENT(INPUT_I_MAX, R_AC),
+	.input_current_min = REG_TO_CURRENT(INPUT_I_MIN, R_AC),
 	.input_current_step = REG_TO_CURRENT(INPUT_I_STEP, R_AC),
 };
 
@@ -62,33 +62,28 @@ static const struct charger_info bq2477x_charger_info = {
 static inline enum ec_error_list raw_read8(int chgnum, int offset, int *value)
 {
 	return i2c_read8(chg_chips[chgnum].i2c_port,
-			 chg_chips[chgnum].i2c_addr_flags,
-			 offset, value);
+			 chg_chips[chgnum].i2c_addr_flags, offset, value);
 }
 
 static inline enum ec_error_list raw_write8(int chgnum, int offset, int value)
 {
 	return i2c_write8(chg_chips[chgnum].i2c_port,
-			  chg_chips[chgnum].i2c_addr_flags,
-			  offset, value);
+			  chg_chips[chgnum].i2c_addr_flags, offset, value);
 }
 #endif
 
 static inline enum ec_error_list raw_read16(int chgnum, int offset, int *value)
 {
 	return i2c_read16(chg_chips[chgnum].i2c_port,
-			  chg_chips[chgnum].i2c_addr_flags,
-			  offset, value);
+			  chg_chips[chgnum].i2c_addr_flags, offset, value);
 }
 
 static inline enum ec_error_list raw_write16(int chgnum, int offset, int value)
 {
 	return i2c_write16(chg_chips[chgnum].i2c_port,
-			   chg_chips[chgnum].i2c_addr_flags,
-			   offset, value);
+			   chg_chips[chgnum].i2c_addr_flags, offset, value);
 }
 
-
 /* chip specific interfaces */
 
 static enum ec_error_list bq2477x_set_input_current_limit(int chgnum,
diff --git a/driver/charger/bq24773.h b/driver/charger/bq24773.h
index 46f8939036..ede480e9d0 100644
--- a/driver/charger/bq24773.h
+++ b/driver/charger/bq24773.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -12,78 +12,78 @@
 #include "i2c.h"
 
 /* I2C address */
-#define BQ24770_ADDR_FLAGS	0x09
-#define BQ24773_ADDR_FLAGS	0x6a
+#define BQ24770_ADDR_FLAGS 0x09
+#define BQ24773_ADDR_FLAGS 0x6a
 
 /* Chip specific commands */
-#define BQ24770_CHARGE_OPTION0          0x12
-#define BQ24770_CHARGE_OPTION1          0x3B
-#define BQ24770_CHARGE_OPTION2          0x38
-#define BQ24770_PROCHOT_OPTION0         0x3C
-#define BQ24770_PROCHOT_OPTION1         0x3D
-#define BQ24770_CHARGE_CURRENT          0x14
-#define BQ24770_MAX_CHARGE_VOLTAGE      0x15
-#define BQ24770_MIN_SYSTEM_VOLTAGE      0x3E
-#define BQ24770_INPUT_CURRENT           0x3F
-#define BQ24770_MANUFACTURE_ID          0xFE
-#define BQ24770_DEVICE_ADDRESS          0xFF
+#define BQ24770_CHARGE_OPTION0 0x12
+#define BQ24770_CHARGE_OPTION1 0x3B
+#define BQ24770_CHARGE_OPTION2 0x38
+#define BQ24770_PROCHOT_OPTION0 0x3C
+#define BQ24770_PROCHOT_OPTION1 0x3D
+#define BQ24770_CHARGE_CURRENT 0x14
+#define BQ24770_MAX_CHARGE_VOLTAGE 0x15
+#define BQ24770_MIN_SYSTEM_VOLTAGE 0x3E
+#define BQ24770_INPUT_CURRENT 0x3F
+#define BQ24770_MANUFACTURE_ID 0xFE
+#define BQ24770_DEVICE_ADDRESS 0xFF
 
-#define BQ24773_CHARGE_OPTION0          0x00
-#define BQ24773_CHARGE_OPTION1          0x02
-#define BQ24773_PROCHOT_OPTION0         0x04
-#define BQ24773_PROCHOT_OPTION1         0x06
-#define BQ24773_PROCHOT_STATUS          0x08
-#define BQ24773_DEVICE_ADDRESS          0x09
-#define BQ24773_CHARGE_CURRENT          0x0A
-#define BQ24773_MAX_CHARGE_VOLTAGE      0x0C
-#define BQ24773_MIN_SYSTEM_VOLTAGE      0x0E
-#define BQ24773_INPUT_CURRENT           0x0F
-#define BQ24773_CHARGE_OPTION2          0x10
+#define BQ24773_CHARGE_OPTION0 0x00
+#define BQ24773_CHARGE_OPTION1 0x02
+#define BQ24773_PROCHOT_OPTION0 0x04
+#define BQ24773_PROCHOT_OPTION1 0x06
+#define BQ24773_PROCHOT_STATUS 0x08
+#define BQ24773_DEVICE_ADDRESS 0x09
+#define BQ24773_CHARGE_CURRENT 0x0A
+#define BQ24773_MAX_CHARGE_VOLTAGE 0x0C
+#define BQ24773_MIN_SYSTEM_VOLTAGE 0x0E
+#define BQ24773_INPUT_CURRENT 0x0F
+#define BQ24773_CHARGE_OPTION2 0x10
 
 /* Option bits */
-#define OPTION0_CHARGE_INHIBIT          BIT(0)
-#define OPTION0_LEARN_ENABLE            BIT(5)
-#define OPTION0_SWITCHING_FREQ_MASK     (3 << 8)
-#define OPTION0_SWITCHING_FREQ_600KHZ   (0 << 8)
-#define OPTION0_SWITCHING_FREQ_800KHZ   BIT(8)
-#define OPTION0_SWITCHING_FREQ_1000KHZ  (2 << 8)
-#define OPTION0_SWITCHING_FREQ_1200KHZ  (3 << 8)
+#define OPTION0_CHARGE_INHIBIT BIT(0)
+#define OPTION0_LEARN_ENABLE BIT(5)
+#define OPTION0_SWITCHING_FREQ_MASK (3 << 8)
+#define OPTION0_SWITCHING_FREQ_600KHZ (0 << 8)
+#define OPTION0_SWITCHING_FREQ_800KHZ BIT(8)
+#define OPTION0_SWITCHING_FREQ_1000KHZ (2 << 8)
+#define OPTION0_SWITCHING_FREQ_1200KHZ (3 << 8)
 
-#define OPTION2_EN_EXTILIM              BIT(7)
+#define OPTION2_EN_EXTILIM BIT(7)
 
 /* Prochot Option bits */
-#define PROCHOT_OPTION1_SELECTOR_MASK   0x7f /* [6:0] PROCHOT SELECTOR */
+#define PROCHOT_OPTION1_SELECTOR_MASK 0x7f /* [6:0] PROCHOT SELECTOR */
 
 #ifdef CONFIG_CHARGER_BQ24770
-	#define CHARGER_NAME		"bq24770"
-	#define I2C_ADDR_CHARGER_FLAGS	BQ24770_ADDR_FLAGS
+#define CHARGER_NAME "bq24770"
+#define I2C_ADDR_CHARGER_FLAGS BQ24770_ADDR_FLAGS
 
-	#define REG_CHARGE_OPTION0	BQ24770_CHARGE_OPTION0
-	#define REG_CHARGE_OPTION1	BQ24770_CHARGE_OPTION1
-	#define REG_CHARGE_OPTION2	BQ24770_CHARGE_OPTION2
-	#define REG_PROCHOT_OPTION0	BQ24770_PROCHOT_OPTION0
-	#define REG_PROCHOT_OPTION1	BQ24770_PROCHOT_OPTION1
-	#define REG_CHARGE_CURRENT	BQ24770_CHARGE_CURRENT
-	#define REG_MAX_CHARGE_VOLTAGE	BQ24770_MAX_CHARGE_VOLTAGE
-	#define REG_MIN_SYSTEM_VOLTAGE	BQ24770_MIN_SYSTEM_VOLTAGE
-	#define REG_INPUT_CURRENT	BQ24770_INPUT_CURRENT
-	#define REG_MANUFACTURE_ID	BQ24770_MANUFACTURE_ID
-	#define REG_DEVICE_ADDRESS	BQ24770_DEVICE_ADDRESS
+#define REG_CHARGE_OPTION0 BQ24770_CHARGE_OPTION0
+#define REG_CHARGE_OPTION1 BQ24770_CHARGE_OPTION1
+#define REG_CHARGE_OPTION2 BQ24770_CHARGE_OPTION2
+#define REG_PROCHOT_OPTION0 BQ24770_PROCHOT_OPTION0
+#define REG_PROCHOT_OPTION1 BQ24770_PROCHOT_OPTION1
+#define REG_CHARGE_CURRENT BQ24770_CHARGE_CURRENT
+#define REG_MAX_CHARGE_VOLTAGE BQ24770_MAX_CHARGE_VOLTAGE
+#define REG_MIN_SYSTEM_VOLTAGE BQ24770_MIN_SYSTEM_VOLTAGE
+#define REG_INPUT_CURRENT BQ24770_INPUT_CURRENT
+#define REG_MANUFACTURE_ID BQ24770_MANUFACTURE_ID
+#define REG_DEVICE_ADDRESS BQ24770_DEVICE_ADDRESS
 
 #elif defined(CONFIG_CHARGER_BQ24773)
-	#define CHARGER_NAME		"bq24773"
-	#define I2C_ADDR_CHARGER_FLAGS	BQ24773_ADDR_FLAGS
+#define CHARGER_NAME "bq24773"
+#define I2C_ADDR_CHARGER_FLAGS BQ24773_ADDR_FLAGS
 
-	#define REG_CHARGE_OPTION0	BQ24773_CHARGE_OPTION0
-	#define REG_CHARGE_OPTION1	BQ24773_CHARGE_OPTION1
-	#define REG_CHARGE_OPTION2	BQ24773_CHARGE_OPTION2
-	#define REG_PROCHOT_OPTION0	BQ24773_PROCHOT_OPTION0
-	#define REG_PROCHOT_OPTION1	BQ24773_PROCHOT_OPTION1
-	#define REG_CHARGE_CURRENT	BQ24773_CHARGE_CURRENT
-	#define REG_MAX_CHARGE_VOLTAGE	BQ24773_MAX_CHARGE_VOLTAGE
-	#define REG_MIN_SYSTEM_VOLTAGE	BQ24773_MIN_SYSTEM_VOLTAGE
-	#define REG_INPUT_CURRENT	BQ24773_INPUT_CURRENT
-	#define REG_DEVICE_ADDRESS	BQ24773_DEVICE_ADDRESS
+#define REG_CHARGE_OPTION0 BQ24773_CHARGE_OPTION0
+#define REG_CHARGE_OPTION1 BQ24773_CHARGE_OPTION1
+#define REG_CHARGE_OPTION2 BQ24773_CHARGE_OPTION2
+#define REG_PROCHOT_OPTION0 BQ24773_PROCHOT_OPTION0
+#define REG_PROCHOT_OPTION1 BQ24773_PROCHOT_OPTION1
+#define REG_CHARGE_CURRENT BQ24773_CHARGE_CURRENT
+#define REG_MAX_CHARGE_VOLTAGE BQ24773_MAX_CHARGE_VOLTAGE
+#define REG_MIN_SYSTEM_VOLTAGE BQ24773_MIN_SYSTEM_VOLTAGE
+#define REG_INPUT_CURRENT BQ24773_INPUT_CURRENT
+#define REG_DEVICE_ADDRESS BQ24773_DEVICE_ADDRESS
 #endif
 
 extern const struct charger_drv bq2477x_drv;
diff --git a/driver/charger/bq25710.c b/driver/charger/bq25710.c
index 1bf9b7cc8a..831f7e110d 100644
--- a/driver/charger/bq25710.c
+++ b/driver/charger/bq25710.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -22,8 +22,7 @@
 #include "timer.h"
 #include "util.h"
 
-#if !defined(CONFIG_CHARGER_BQ25710) &&	\
-	!defined(CONFIG_CHARGER_BQ25720)
+#if !defined(CONFIG_CHARGER_BQ25710) && !defined(CONFIG_CHARGER_BQ25720)
 #error Only the BQ25720 and BQ25710 are supported by bq25710 driver.
 #endif
 
@@ -32,10 +31,8 @@
 #endif
 
 #ifndef CONFIG_CHARGER_BQ25720_VSYS_TH2_CUSTOM
-#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV	GET_BQ_FIELD(BQ25720, \
-							     VMIN_AP,	\
-							     VSYS_TH2, \
-							     UINT16_MAX)
+#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV \
+	GET_BQ_FIELD(BQ25720, VMIN_AP, VSYS_TH2, UINT16_MAX)
 #endif
 
 #ifndef CONFIG_CHARGER_BQ25710_VSYS_MIN_VOLTAGE_CUSTOM
@@ -69,49 +66,38 @@
  * Helper macros
  */
 
-#define SET_CO1_BY_NAME(_field, _c, _x)	SET_BQ_FIELD_BY_NAME(BQ257X0,	\
-							     CHARGE_OPTION_1, \
-							     _field, _c, (_x))
+#define SET_CO1_BY_NAME(_field, _c, _x) \
+	SET_BQ_FIELD_BY_NAME(BQ257X0, CHARGE_OPTION_1, _field, _c, (_x))
 
-#define SET_CO2(_field, _v, _x)		SET_BQ_FIELD(BQ257X0,	\
-						     CHARGE_OPTION_2,	\
-						     _field, _v, (_x))
+#define SET_CO2(_field, _v, _x) \
+	SET_BQ_FIELD(BQ257X0, CHARGE_OPTION_2, _field, _v, (_x))
 
-#define SET_CO2_BY_NAME(_field, _c, _x)	SET_BQ_FIELD_BY_NAME(BQ257X0,	\
-							     CHARGE_OPTION_2, \
-							     _field, _c, (_x))
+#define SET_CO2_BY_NAME(_field, _c, _x) \
+	SET_BQ_FIELD_BY_NAME(BQ257X0, CHARGE_OPTION_2, _field, _c, (_x))
 
-#define SET_CO3(_field, _v, _x)		SET_BQ_FIELD(BQ257X0,	\
-						     CHARGE_OPTION_3,	\
-						     _field, _v, (_x))
+#define SET_CO3(_field, _v, _x) \
+	SET_BQ_FIELD(BQ257X0, CHARGE_OPTION_3, _field, _v, (_x))
 
-#define SET_CO3_BY_NAME(_field, _c, _x)	SET_BQ_FIELD_BY_NAME(BQ257X0,	\
-							     CHARGE_OPTION_3, \
-							     _field, _c, (_x))
+#define SET_CO3_BY_NAME(_field, _c, _x) \
+	SET_BQ_FIELD_BY_NAME(BQ257X0, CHARGE_OPTION_3, _field, _c, (_x))
 
-#define SET_CO4(_field, _v, _x)		SET_BQ_FIELD(BQ25720,	\
-						     CHARGE_OPTION_4,	\
-						     _field, _v, (_x))
+#define SET_CO4(_field, _v, _x) \
+	SET_BQ_FIELD(BQ25720, CHARGE_OPTION_4, _field, _v, (_x))
 
-#define SET_CO4_BY_NAME(_field, _c, _x)	SET_BQ_FIELD_BY_NAME(BQ25720,	\
-							     CHARGE_OPTION_4, \
-							     _field, _c, (_x))
+#define SET_CO4_BY_NAME(_field, _c, _x) \
+	SET_BQ_FIELD_BY_NAME(BQ25720, CHARGE_OPTION_4, _field, _c, (_x))
 
-#define SET_PO0(_field, _v, _x)		SET_BQ_FIELD(BQ257X0,	\
-						     PROCHOT_OPTION_0,	\
-						     _field, _v, (_x))
+#define SET_PO0(_field, _v, _x) \
+	SET_BQ_FIELD(BQ257X0, PROCHOT_OPTION_0, _field, _v, (_x))
 
-#define SET_PO0_BY_NAME(_field, _c, _x)	SET_BQ_FIELD_BY_NAME(BQ257X0,	\
-							     PROCHOT_OPTION_0, \
-							     _field, _c, (_x))
+#define SET_PO0_BY_NAME(_field, _c, _x) \
+	SET_BQ_FIELD_BY_NAME(BQ257X0, PROCHOT_OPTION_0, _field, _c, (_x))
 
-#define SET_PO1(_field, _v, _x)		SET_BQ_FIELD(BQ257X0,	\
-						     PROCHOT_OPTION_1,	\
-						     _field, _v, (_x))
+#define SET_PO1(_field, _v, _x) \
+	SET_BQ_FIELD(BQ257X0, PROCHOT_OPTION_1, _field, _v, (_x))
 
-#define SET_PO1_BY_NAME(_field, _c, _x)	SET_BQ_FIELD_BY_NAME(BQ257X0,	\
-							     PROCHOT_OPTION_1, \
-							     _field, _c, (_x))
+#define SET_PO1_BY_NAME(_field, _c, _x) \
+	SET_BQ_FIELD_BY_NAME(BQ257X0, PROCHOT_OPTION_1, _field, _c, (_x))
 
 /*
  * Delay required from taking the bq25710 out of low power mode and having the
@@ -124,16 +110,17 @@
 /* Sense resistor configurations and macros */
 #define DEFAULT_SENSE_RESISTOR 10
 
-#define REG_TO_CHARGING_CURRENT(REG) ((REG) * \
-	DEFAULT_SENSE_RESISTOR / CONFIG_CHARGER_BQ25710_SENSE_RESISTOR)
-#define REG_TO_CHARGING_CURRENT_AC(REG) ((REG) * \
-	DEFAULT_SENSE_RESISTOR / CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC)
-#define CHARGING_CURRENT_TO_REG(CUR) ((CUR) * \
-	CONFIG_CHARGER_BQ25710_SENSE_RESISTOR / DEFAULT_SENSE_RESISTOR)
-#define VMIN_AP_VSYS_TH2_TO_REG(DV) ((DV) - 32)
+#define REG_TO_CHARGING_CURRENT(REG) \
+	((REG)*DEFAULT_SENSE_RESISTOR / CONFIG_CHARGER_BQ25710_SENSE_RESISTOR)
+#define REG_TO_CHARGING_CURRENT_AC(REG) \
+	((REG)*DEFAULT_SENSE_RESISTOR / \
+	 CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC)
+#define CHARGING_CURRENT_TO_REG(CUR) \
+	((CUR)*CONFIG_CHARGER_BQ25710_SENSE_RESISTOR / DEFAULT_SENSE_RESISTOR)
+#define VMIN_AP_VSYS_TH2_TO_REG(DV) ((DV)-32)
 
 /* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
 
 #ifdef CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA
 /*
@@ -153,15 +140,15 @@ static struct mutex bq25710_perf_mode_mutex;
 
 /* Charger parameters */
 static const struct charger_info bq25710_charger_info = {
-	.name         = "bq25710",
-	.voltage_max  = 19200,
-	.voltage_min  = 1024,
+	.name = "bq25710",
+	.voltage_max = 19200,
+	.voltage_min = 1024,
 	.voltage_step = 8,
-	.current_max  = REG_TO_CHARGING_CURRENT(8128),
-	.current_min  = REG_TO_CHARGING_CURRENT(64),
+	.current_max = REG_TO_CHARGING_CURRENT(8128),
+	.current_min = REG_TO_CHARGING_CURRENT(64),
 	.current_step = REG_TO_CHARGING_CURRENT(64),
-	.input_current_max  = REG_TO_CHARGING_CURRENT_AC(6400),
-	.input_current_min  = REG_TO_CHARGING_CURRENT_AC(50),
+	.input_current_max = REG_TO_CHARGING_CURRENT_AC(6400),
+	.input_current_min = REG_TO_CHARGING_CURRENT_AC(50),
 	.input_current_step = REG_TO_CHARGING_CURRENT_AC(50),
 };
 
@@ -180,8 +167,8 @@ static inline int iin_dpm_reg_to_current(int reg)
 	if (reg == 0)
 		return BQ25710_IIN_DPM_CODE0_OFFSET;
 	else
-		return REG_TO_CHARGING_CURRENT_AC(reg *
-			BQ257X0_IIN_DPM_CURRENT_STEP_MA);
+		return REG_TO_CHARGING_CURRENT_AC(
+			reg * BQ257X0_IIN_DPM_CURRENT_STEP_MA);
 }
 
 static inline int iin_host_current_to_reg(int current)
@@ -193,8 +180,7 @@ static inline int iin_host_current_to_reg(int current)
 static inline enum ec_error_list raw_read16(int chgnum, int offset, int *value)
 {
 	return i2c_read16(chg_chips[chgnum].i2c_port,
-			  chg_chips[chgnum].i2c_addr_flags,
-			  offset, value);
+			  chg_chips[chgnum].i2c_addr_flags, offset, value);
 }
 
 static inline int min_system_voltage_to_reg(int voltage_mv)
@@ -215,8 +201,7 @@ static inline int min_system_voltage_to_reg(int voltage_mv)
 static inline enum ec_error_list raw_write16(int chgnum, int offset, int value)
 {
 	return i2c_write16(chg_chips[chgnum].i2c_port,
-			   chg_chips[chgnum].i2c_addr_flags,
-			   offset, value);
+			   chg_chips[chgnum].i2c_addr_flags, offset, value);
 }
 
 #if defined(CONFIG_CHARGE_RAMP_HW) || \
@@ -312,7 +297,7 @@ static int bq25710_adc_start(int chgnum, int adc_en_mask)
 	 * maps to bit[7:0] in ADCOption register.
 	 */
 	reg = (adc_en_mask & BQ257X0_ADC_OPTION_EN_ADC_ALL) |
-		BQ_FIELD_MASK(BQ257X0, ADC_OPTION, ADC_START);
+	      BQ_FIELD_MASK(BQ257X0, ADC_OPTION, ADC_START);
 	if (raw_write16(chgnum, BQ25710_REG_ADC_OPTION, reg))
 		return EC_ERROR_UNKNOWN;
 
@@ -326,8 +311,8 @@ static int bq25710_adc_start(int chgnum, int adc_en_mask)
 		/* sleep 2 ms so we time out after 2x the expected time */
 		msleep(2);
 		raw_read16(chgnum, BQ25710_REG_ADC_OPTION, &reg);
-	} while (--tries_left && (reg & BQ_FIELD_MASK(BQ257X0, ADC_OPTION,
-						      ADC_START)));
+	} while (--tries_left &&
+		 (reg & BQ_FIELD_MASK(BQ257X0, ADC_OPTION, ADC_START)));
 
 	/* ADC reading attempt complete, go back to low power mode */
 	if (bq25710_set_low_power_mode(chgnum, mode))
@@ -409,8 +394,7 @@ static int bq257x0_init_prochot_option_1(int chgnum)
 	 * so the actual IDCHG limit will be the value stored in
 	 * IDCHG_VTH + 128 mA.
 	 */
-	reg = SET_PO1(IDCHG_VTH,
-		      CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA >> 9,
+	reg = SET_PO1(IDCHG_VTH, CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA >> 9,
 		      reg);
 
 	/*  Enable IDCHG trigger for prochot. */
@@ -576,8 +560,8 @@ static void bq25710_init(int chgnum)
 			vsys = min_system_voltage_to_reg(
 				CONFIG_CHARGER_BQ25710_VSYS_MIN_VOLTAGE_MV);
 		} else {
-			rv |= raw_read16(chgnum,
-					 BQ25710_REG_MIN_SYSTEM_VOLTAGE, &vsys);
+			rv |= raw_read16(chgnum, BQ25710_REG_MIN_SYSTEM_VOLTAGE,
+					 &vsys);
 		}
 
 		rv |= raw_read16(chgnum, BQ25710_REG_CHARGE_OPTION_3, &reg);
@@ -694,7 +678,7 @@ static enum ec_error_list bq25710_get_current(int chgnum, int *current)
 static enum ec_error_list bq25710_set_current(int chgnum, int current)
 {
 	return raw_write16(chgnum, BQ25710_REG_CHARGE_CURRENT,
-		CHARGING_CURRENT_TO_REG(current));
+			   CHARGING_CURRENT_TO_REG(current));
 }
 
 /* Get/set charge voltage limit in mV */
@@ -749,9 +733,8 @@ static enum ec_error_list bq25710_get_input_current_limit(int chgnum,
 	 */
 	rv = raw_read16(chgnum, BQ25710_REG_IIN_DPM, &reg);
 	if (!rv)
-		*input_current =
-			iin_dpm_reg_to_current(reg >>
-					       BQ257X0_IIN_DPM_CURRENT_SHIFT);
+		*input_current = iin_dpm_reg_to_current(
+			reg >> BQ257X0_IIN_DPM_CURRENT_SHIFT);
 
 	return rv;
 }
@@ -786,8 +769,9 @@ static int reg_adc_vbus_to_mv(int reg)
 	 * LSB => 64mV.
 	 * Return 0 when VBUS <= 3.2V as ADC can't measure it.
 	 */
-	return reg ?
-		(reg * BQ25710_ADC_VBUS_STEP_MV + BQ25710_ADC_VBUS_BASE_MV) : 0;
+	return reg ? (reg * BQ25710_ADC_VBUS_STEP_MV +
+		      BQ25710_ADC_VBUS_BASE_MV) :
+		     0;
 }
 
 #else
@@ -799,8 +783,8 @@ static enum ec_error_list bq25710_get_vbus_voltage(int chgnum, int port,
 {
 	int reg, rv;
 
-	rv = bq25710_adc_start(chgnum, BQ_FIELD_MASK(BQ257X0, ADC_OPTION,
-						     EN_ADC_VBUS));
+	rv = bq25710_adc_start(chgnum,
+			       BQ_FIELD_MASK(BQ257X0, ADC_OPTION, EN_ADC_VBUS));
 	if (rv)
 		goto error;
 
@@ -895,7 +879,7 @@ static enum ec_error_list bq25710_set_hw_ramp(int chgnum, int enable)
 
 		/* Set InputVoltage register to BC1.2 minimum ramp voltage */
 		rv = raw_write16(chgnum, BQ25710_REG_INPUT_VOLTAGE,
-			BQ25710_BC12_MIN_VOLTAGE_MV);
+				 BQ25710_BC12_MIN_VOLTAGE_MV);
 		if (rv)
 			return rv;
 
@@ -904,8 +888,8 @@ static enum ec_error_list bq25710_set_hw_ramp(int chgnum, int enable)
 					   EN_ICO_MODE, 1, option3_reg);
 
 		/* 0b: Input current limit is set by BQ25710_REG_IIN_HOST */
-		option2_reg = SET_BQ_FIELD(BQ257X0, CHARGE_OPTION_2,
-					   EN_EXTILIM, 0, option2_reg);
+		option2_reg = SET_BQ_FIELD(BQ257X0, CHARGE_OPTION_2, EN_EXTILIM,
+					   0, option2_reg);
 
 		/* Charge ramp may take up to 2s to settle down */
 		hook_call_deferred(&bq25710_chg_ramp_handle_data, (4 * SECOND));
@@ -918,8 +902,8 @@ static enum ec_error_list bq25710_set_hw_ramp(int chgnum, int enable)
 		 * 1b: Input current limit is set by the lower value of
 		 * ILIM_HIZ pin and BQ25710_REG_IIN_HOST
 		 */
-		option2_reg = SET_BQ_FIELD(BQ257X0, CHARGE_OPTION_2,
-					    EN_EXTILIM, 1, option2_reg);
+		option2_reg = SET_BQ_FIELD(BQ257X0, CHARGE_OPTION_2, EN_EXTILIM,
+					   1, option2_reg);
 	}
 
 	rv = raw_write16(chgnum, BQ25710_REG_CHARGE_OPTION_2, option2_reg);
@@ -962,7 +946,6 @@ static void bq25710_chipset_startup(void)
 DECLARE_HOOK(HOOK_CHIPSET_STARTUP, bq25710_chipset_startup, HOOK_PRIO_DEFAULT);
 DECLARE_HOOK(HOOK_CHIPSET_RESUME, bq25710_chipset_startup, HOOK_PRIO_DEFAULT);
 
-
 /* Called on AP S0 -> S0iX/S3 or S3 -> S5 transition */
 static void bq25710_chipset_suspend(void)
 {
diff --git a/driver/charger/bq25710.h b/driver/charger/bq25710.h
index bb1ee1ba99..078160e66e 100644
--- a/driver/charger/bq25710.h
+++ b/driver/charger/bq25710.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,57 +11,57 @@
 /* SMBUS Interface */
 #define BQ25710_SMBUS_ADDR1_FLAGS 0x09
 
-#define BQ25710_BC12_MIN_VOLTAGE_MV	1408
+#define BQ25710_BC12_MIN_VOLTAGE_MV 1408
 
 /* Registers */
-#define BQ25710_REG_CHARGE_OPTION_0		0x12
-#define BQ25710_REG_CHARGE_CURRENT		0x14
-#define BQ25710_REG_MAX_CHARGE_VOLTAGE		0x15
-#define BQ25710_REG_CHARGER_STATUS		0x20
-#define BQ25710_REG_PROCHOT_STATUS		0x21
-#define BQ25710_REG_IIN_DPM			0x22
-#define BQ25710_REG_ADC_VBUS_PSYS		0x23
-#define BQ25710_REG_ADC_IBAT			0x24
-#define BQ25710_REG_ADC_CMPIN_IIN		0x25
-#define BQ25710_REG_ADC_VSYS_VBAT		0x26
-#define BQ25710_REG_CHARGE_OPTION_1		0x30
-#define BQ25710_REG_CHARGE_OPTION_2		0x31
-#define BQ25710_REG_CHARGE_OPTION_3		0x32
-#define BQ25710_REG_PROCHOT_OPTION_0		0x33
-#define BQ25710_REG_PROCHOT_OPTION_1		0x34
-#define BQ25710_REG_ADC_OPTION			0x35
-#define BQ25720_REG_CHARGE_OPTION_4		0x36
-#define BQ25720_REG_VMIN_ACTIVE_PROTECTION	0x37
-#define BQ25710_REG_OTG_VOLTAGE			0x3B
-#define BQ25710_REG_OTG_CURRENT			0x3C
-#define BQ25710_REG_INPUT_VOLTAGE		0x3D
-#define BQ25710_REG_MIN_SYSTEM_VOLTAGE		0x3E
-#define BQ25710_REG_IIN_HOST			0x3F
-#define BQ25710_REG_MANUFACTURER_ID		0xFE
-#define BQ25710_REG_DEVICE_ADDRESS		0xFF
+#define BQ25710_REG_CHARGE_OPTION_0 0x12
+#define BQ25710_REG_CHARGE_CURRENT 0x14
+#define BQ25710_REG_MAX_CHARGE_VOLTAGE 0x15
+#define BQ25710_REG_CHARGER_STATUS 0x20
+#define BQ25710_REG_PROCHOT_STATUS 0x21
+#define BQ25710_REG_IIN_DPM 0x22
+#define BQ25710_REG_ADC_VBUS_PSYS 0x23
+#define BQ25710_REG_ADC_IBAT 0x24
+#define BQ25710_REG_ADC_CMPIN_IIN 0x25
+#define BQ25710_REG_ADC_VSYS_VBAT 0x26
+#define BQ25710_REG_CHARGE_OPTION_1 0x30
+#define BQ25710_REG_CHARGE_OPTION_2 0x31
+#define BQ25710_REG_CHARGE_OPTION_3 0x32
+#define BQ25710_REG_PROCHOT_OPTION_0 0x33
+#define BQ25710_REG_PROCHOT_OPTION_1 0x34
+#define BQ25710_REG_ADC_OPTION 0x35
+#define BQ25720_REG_CHARGE_OPTION_4 0x36
+#define BQ25720_REG_VMIN_ACTIVE_PROTECTION 0x37
+#define BQ25710_REG_OTG_VOLTAGE 0x3B
+#define BQ25710_REG_OTG_CURRENT 0x3C
+#define BQ25710_REG_INPUT_VOLTAGE 0x3D
+#define BQ25710_REG_MIN_SYSTEM_VOLTAGE 0x3E
+#define BQ25710_REG_IIN_HOST 0x3F
+#define BQ25710_REG_MANUFACTURER_ID 0xFE
+#define BQ25710_REG_DEVICE_ADDRESS 0xFF
 
 /* ADC conversion time ins ms */
 #if defined(CONFIG_CHARGER_BQ25720)
-#define BQ25710_ADC_OPTION_ADC_CONV_MS		25
+#define BQ25710_ADC_OPTION_ADC_CONV_MS 25
 #elif defined(CONFIG_CHARGER_BQ25710)
-#define BQ25710_ADC_OPTION_ADC_CONV_MS		10
+#define BQ25710_ADC_OPTION_ADC_CONV_MS 10
 #else
 #error Only the BQ25720 and BQ25710 are supported by bq25710 driver.
 #endif
 
 /* ADCVBUS/PSYS Register */
 #if defined(CONFIG_CHARGER_BQ25720)
-#define BQ25720_ADC_VBUS_STEP_MV		96
+#define BQ25720_ADC_VBUS_STEP_MV 96
 #elif defined(CONFIG_CHARGER_BQ25710)
-#define BQ25710_ADC_VBUS_STEP_MV		64
-#define BQ25710_ADC_VBUS_BASE_MV		3200
+#define BQ25710_ADC_VBUS_STEP_MV 64
+#define BQ25710_ADC_VBUS_BASE_MV 3200
 #else
 #error Only the BQ25720 and BQ25710 are supported by bq25710 driver.
 #endif
 
 /* Min System Voltage Register */
-#define BQ25710_MIN_SYSTEM_VOLTAGE_STEP_MV	256
-#define BQ25720_VSYS_MIN_VOLTAGE_STEP_MV	100
+#define BQ25710_MIN_SYSTEM_VOLTAGE_STEP_MV 256
+#define BQ25720_VSYS_MIN_VOLTAGE_STEP_MV 100
 
 extern const struct charger_drv bq25710_drv;
 
diff --git a/driver/charger/bq257x0_regs.h b/driver/charger/bq257x0_regs.h
index fcec8f7469..69b218436a 100644
--- a/driver/charger/bq257x0_regs.h
+++ b/driver/charger/bq257x0_regs.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -21,221 +21,221 @@
 /*
  * ChargerStatus Register (0x20)
  */
-#define BQ257X0_CHARGER_STATUS_ICO_DONE_SHIFT		14
-#define BQ257X0_CHARGER_STATUS_ICO_DONE_BITS		1
+#define BQ257X0_CHARGER_STATUS_ICO_DONE_SHIFT 14
+#define BQ257X0_CHARGER_STATUS_ICO_DONE_BITS 1
 
 /*
  * ChargeOption0 Register (0x12)
  */
-#define BQ257X0_CHARGE_OPTION_0_EN_LWPWR_SHIFT		15
-#define BQ257X0_CHARGE_OPTION_0_EN_LWPWR_BITS		1
-#define BQ257X0_CHARGE_OPTION_0_EN_LEARN_SHIFT		5
-#define BQ257X0_CHARGE_OPTION_0_EN_LEARN_BITS		1
-#define BQ257X0_CHARGE_OPTION_0_IADP_GAIN_SHIFT		4
-#define BQ257X0_CHARGE_OPTION_0_IADP_GAIN_BITS		1
-#define BQ257X0_CHARGE_OPTION_0_EN_IDPM_SHIFT		1
-#define BQ257X0_CHARGE_OPTION_0_EN_IDPM_BITS		1
-#define BQ257X0_CHARGE_OPTION_0_CHRG_INHIBIT_SHIFT	0
-#define BQ257X0_CHARGE_OPTION_0_CHRG_INHIBIT_BITS	1
+#define BQ257X0_CHARGE_OPTION_0_EN_LWPWR_SHIFT 15
+#define BQ257X0_CHARGE_OPTION_0_EN_LWPWR_BITS 1
+#define BQ257X0_CHARGE_OPTION_0_EN_LEARN_SHIFT 5
+#define BQ257X0_CHARGE_OPTION_0_EN_LEARN_BITS 1
+#define BQ257X0_CHARGE_OPTION_0_IADP_GAIN_SHIFT 4
+#define BQ257X0_CHARGE_OPTION_0_IADP_GAIN_BITS 1
+#define BQ257X0_CHARGE_OPTION_0_EN_IDPM_SHIFT 1
+#define BQ257X0_CHARGE_OPTION_0_EN_IDPM_BITS 1
+#define BQ257X0_CHARGE_OPTION_0_CHRG_INHIBIT_SHIFT 0
+#define BQ257X0_CHARGE_OPTION_0_CHRG_INHIBIT_BITS 1
 
 /*
  * ChargeOption1 Register (0x30)
  */
-#define BQ25710_CHARGE_OPTION_1_EN_PSYS_SHIFT		12
-#define BQ25710_CHARGE_OPTION_1_EN_PSYS_BITS		1
+#define BQ25710_CHARGE_OPTION_1_EN_PSYS_SHIFT 12
+#define BQ25710_CHARGE_OPTION_1_EN_PSYS_BITS 1
 
-#define BQ25720_CHARGE_OPTION_1_PSYS_CONFIG_SHIFT	12
-#define BQ25720_CHARGE_OPTION_1_PSYS_CONFIG_BITS	2
-#define BQ25720_CHARGE_OPTION_1_PSYS_CONFIG__PBUS_PBAT	0
-#define BQ25720_CHARGE_OPTION_1_PSYS_CONFIG__OFF	3
+#define BQ25720_CHARGE_OPTION_1_PSYS_CONFIG_SHIFT 12
+#define BQ25720_CHARGE_OPTION_1_PSYS_CONFIG_BITS 2
+#define BQ25720_CHARGE_OPTION_1_PSYS_CONFIG__PBUS_PBAT 0
+#define BQ25720_CHARGE_OPTION_1_PSYS_CONFIG__OFF 3
 
-#define BQ257X0_CHARGE_OPTION_1_CMP_REF_SHIFT		7
-#define BQ257X0_CHARGE_OPTION_1_CMP_REF_BITS		1
-#define BQ257X0_CHARGE_OPTION_1_CMP_REF__2P3		0
-#define BQ257X0_CHARGE_OPTION_1_CMP_REF__1P2		1
+#define BQ257X0_CHARGE_OPTION_1_CMP_REF_SHIFT 7
+#define BQ257X0_CHARGE_OPTION_1_CMP_REF_BITS 1
+#define BQ257X0_CHARGE_OPTION_1_CMP_REF__2P3 0
+#define BQ257X0_CHARGE_OPTION_1_CMP_REF__1P2 1
 
-#define BQ257X0_CHARGE_OPTION_1_CMP_POL_SHIFT		6
-#define BQ257X0_CHARGE_OPTION_1_CMP_POL_BITS		1
-#define BQ257X0_CHARGE_OPTION_1_CMP_POL__INTERNAL	0
-#define BQ257X0_CHARGE_OPTION_1_CMP_POL__EXTERNAL	1
+#define BQ257X0_CHARGE_OPTION_1_CMP_POL_SHIFT 6
+#define BQ257X0_CHARGE_OPTION_1_CMP_POL_BITS 1
+#define BQ257X0_CHARGE_OPTION_1_CMP_POL__INTERNAL 0
+#define BQ257X0_CHARGE_OPTION_1_CMP_POL__EXTERNAL 1
 
 /*
  * ChargeOption2 Register (0x31)
  */
-#define BQ257X0_CHARGE_OPTION_2_PKPWR_TOVLD_DEG_SHIFT	14
-#define BQ257X0_CHARGE_OPTION_2_PKPWR_TOVLD_DEG_BITS	2
-#define BQ25720_CHARGE_OPTION_2_PKPWR_TOVLD_DEG__10MS	3
+#define BQ257X0_CHARGE_OPTION_2_PKPWR_TOVLD_DEG_SHIFT 14
+#define BQ257X0_CHARGE_OPTION_2_PKPWR_TOVLD_DEG_BITS 2
+#define BQ25720_CHARGE_OPTION_2_PKPWR_TOVLD_DEG__10MS 3
 
-#define BQ257X0_CHARGE_OPTION_2_PKPWR_TMAX_SHIFT	8
-#define BQ257X0_CHARGE_OPTION_2_PKPWR_TMAX_BITS		2
+#define BQ257X0_CHARGE_OPTION_2_PKPWR_TMAX_SHIFT 8
+#define BQ257X0_CHARGE_OPTION_2_PKPWR_TMAX_BITS 2
 
-#define BQ257X0_CHARGE_OPTION_2_EN_EXTILIM_SHIFT	7
-#define BQ257X0_CHARGE_OPTION_2_EN_EXTILIM_BITS		1
+#define BQ257X0_CHARGE_OPTION_2_EN_EXTILIM_SHIFT 7
+#define BQ257X0_CHARGE_OPTION_2_EN_EXTILIM_BITS 1
 
-#define BQ257X0_CHARGE_OPTION_2_EN_ACOC_SHIFT		3
-#define BQ257X0_CHARGE_OPTION_2_EN_ACOC_BITS		1
-#define BQ257X0_CHARGE_OPTION_2_EN_ACOC__DISABLE	0
-#define BQ257X0_CHARGE_OPTION_2_EN_ACOC__ENABLE		1
+#define BQ257X0_CHARGE_OPTION_2_EN_ACOC_SHIFT 3
+#define BQ257X0_CHARGE_OPTION_2_EN_ACOC_BITS 1
+#define BQ257X0_CHARGE_OPTION_2_EN_ACOC__DISABLE 0
+#define BQ257X0_CHARGE_OPTION_2_EN_ACOC__ENABLE 1
 
-#define BQ257X0_CHARGE_OPTION_2_ACOC_VTH_SHIFT		2
-#define BQ257X0_CHARGE_OPTION_2_ACOC_VTH_BITS		1
-#define BQ257X0_CHARGE_OPTION_2_ACOC_VTH__1P33		0
-#define BQ257X0_CHARGE_OPTION_2_ACOC_VTH__2P00		1
+#define BQ257X0_CHARGE_OPTION_2_ACOC_VTH_SHIFT 2
+#define BQ257X0_CHARGE_OPTION_2_ACOC_VTH_BITS 1
+#define BQ257X0_CHARGE_OPTION_2_ACOC_VTH__1P33 0
+#define BQ257X0_CHARGE_OPTION_2_ACOC_VTH__2P00 1
 
-#define BQ257X0_CHARGE_OPTION_2_BATOC_VTH_SHIFT		0
-#define BQ257X0_CHARGE_OPTION_2_BATOC_VTH_BITS		1
-#define BQ257X0_CHARGE_OPTION_2_BATOC_VTH__1P33		0
-#define BQ257X0_CHARGE_OPTION_2_BATOC_VTH__2P00		1
+#define BQ257X0_CHARGE_OPTION_2_BATOC_VTH_SHIFT 0
+#define BQ257X0_CHARGE_OPTION_2_BATOC_VTH_BITS 1
+#define BQ257X0_CHARGE_OPTION_2_BATOC_VTH__1P33 0
+#define BQ257X0_CHARGE_OPTION_2_BATOC_VTH__2P00 1
 
 /*
  * ChargeOption3 Register (0x32)
  */
-#define BQ257X0_CHARGE_OPTION_3_RESET_REG_SHIFT		14
-#define BQ257X0_CHARGE_OPTION_3_RESET_REG_BITS		1
+#define BQ257X0_CHARGE_OPTION_3_RESET_REG_SHIFT 14
+#define BQ257X0_CHARGE_OPTION_3_RESET_REG_BITS 1
 
-#define BQ257X0_CHARGE_OPTION_3_EN_ICO_MODE_SHIFT	11
-#define BQ257X0_CHARGE_OPTION_3_EN_ICO_MODE_BITS	1
+#define BQ257X0_CHARGE_OPTION_3_EN_ICO_MODE_SHIFT 11
+#define BQ257X0_CHARGE_OPTION_3_EN_ICO_MODE_BITS 1
 
-#define BQ257X0_CHARGE_OPTION_3_IL_AVG_SHIFT		3
-#define BQ257X0_CHARGE_OPTION_3_IL_AVG_BITS		2
-#define BQ257X0_CHARGE_OPTION_3_IL_AVG__10A		1
+#define BQ257X0_CHARGE_OPTION_3_IL_AVG_SHIFT 3
+#define BQ257X0_CHARGE_OPTION_3_IL_AVG_BITS 2
+#define BQ257X0_CHARGE_OPTION_3_IL_AVG__10A 1
 
 /*
  * ChargeOption4 Register (0x36)
  */
-#define BQ25720_CHARGE_OPTION_4_VSYS_UVP_SHIFT		13
-#define BQ25720_CHARGE_OPTION_4_VSYS_UVP_BITS		3
-#define BQ25720_CHARGE_OPTION_4_VSYS_UVP__2P4		0
-#define BQ25720_CHARGE_OPTION_4_VSYS_UVP__3P2		1
-#define BQ25720_CHARGE_OPTION_4_VSYS_UVP__4P0		2
-#define BQ25720_CHARGE_OPTION_4_VSYS_UVP__4P8		3
-#define BQ25720_CHARGE_OPTION_4_VSYS_UVP__5P6		4
-#define BQ25720_CHARGE_OPTION_4_VSYS_UVP__6P4		5
-#define BQ25720_CHARGE_OPTION_4_VSYS_UVP__7P2		6
-#define BQ25720_CHARGE_OPTION_4_VSYS_UVP__8P0		7
-
-#define BQ25720_CHARGE_OPTION_4_IDCHG_DEG2_SHIFT	6
-#define BQ25720_CHARGE_OPTION_4_IDCHG_DEG2_BITS		2
-#define BQ25720_CHARGE_OPTION_4_IDCHG_DEG2__1P6MS	1
-#define BQ25720_CHARGE_OPTION_4_IDCHG_DEG2__12MS	3
-
-#define BQ25720_CHARGE_OPTION_4_IDCHG_TH2_SHIFT		3
-#define BQ25720_CHARGE_OPTION_4_IDCHG_TH2_BITS		3
-#define BQ25720_CHARGE_OPTION_4_IDCHG_TH2__1P25		0
-#define BQ25720_CHARGE_OPTION_4_IDCHG_TH2__1P5		1
-
-#define BQ25720_CHARGE_OPTION_4_PP_IDCHG2_SHIFT		2
-#define BQ25720_CHARGE_OPTION_4_PP_IDCHG2_BITS		1
-#define BQ25720_CHARGE_OPTION_4_PP_IDCHG2__DISABLE	0
-#define BQ25720_CHARGE_OPTION_4_PP_IDCHG2__ENABLE	1
+#define BQ25720_CHARGE_OPTION_4_VSYS_UVP_SHIFT 13
+#define BQ25720_CHARGE_OPTION_4_VSYS_UVP_BITS 3
+#define BQ25720_CHARGE_OPTION_4_VSYS_UVP__2P4 0
+#define BQ25720_CHARGE_OPTION_4_VSYS_UVP__3P2 1
+#define BQ25720_CHARGE_OPTION_4_VSYS_UVP__4P0 2
+#define BQ25720_CHARGE_OPTION_4_VSYS_UVP__4P8 3
+#define BQ25720_CHARGE_OPTION_4_VSYS_UVP__5P6 4
+#define BQ25720_CHARGE_OPTION_4_VSYS_UVP__6P4 5
+#define BQ25720_CHARGE_OPTION_4_VSYS_UVP__7P2 6
+#define BQ25720_CHARGE_OPTION_4_VSYS_UVP__8P0 7
+
+#define BQ25720_CHARGE_OPTION_4_IDCHG_DEG2_SHIFT 6
+#define BQ25720_CHARGE_OPTION_4_IDCHG_DEG2_BITS 2
+#define BQ25720_CHARGE_OPTION_4_IDCHG_DEG2__1P6MS 1
+#define BQ25720_CHARGE_OPTION_4_IDCHG_DEG2__12MS 3
+
+#define BQ25720_CHARGE_OPTION_4_IDCHG_TH2_SHIFT 3
+#define BQ25720_CHARGE_OPTION_4_IDCHG_TH2_BITS 3
+#define BQ25720_CHARGE_OPTION_4_IDCHG_TH2__1P25 0
+#define BQ25720_CHARGE_OPTION_4_IDCHG_TH2__1P5 1
+
+#define BQ25720_CHARGE_OPTION_4_PP_IDCHG2_SHIFT 2
+#define BQ25720_CHARGE_OPTION_4_PP_IDCHG2_BITS 1
+#define BQ25720_CHARGE_OPTION_4_PP_IDCHG2__DISABLE 0
+#define BQ25720_CHARGE_OPTION_4_PP_IDCHG2__ENABLE 1
 
 /*
  * Vmin Active Protection Register (0x37)
  */
-#define BQ25720_VMIN_AP_VSYS_TH2_SHIFT			2
-#define BQ25720_VMIN_AP_VSYS_TH2_BITS			6
+#define BQ25720_VMIN_AP_VSYS_TH2_SHIFT 2
+#define BQ25720_VMIN_AP_VSYS_TH2_BITS 6
 
 /*
  * ProchotOption0 Register (0x33)
  */
-#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH_SHIFT	11
-#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH_BITS		5
-#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH__1P10	1
-#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH__1P40	7
-#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH__1P50	9
-#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH__2P30	25
-#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH__2P50	26
-#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH__4P50	30
-#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH__NA		31
+#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH_SHIFT 11
+#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH_BITS 5
+#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH__1P10 1
+#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH__1P40 7
+#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH__1P50 9
+#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH__2P30 25
+#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH__2P50 26
+#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH__4P50 30
+#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH__NA 31
 
 /*
  * ProchotOption1 Register (0x34)
  */
-#define BQ257X0_PROCHOT_OPTION_1_IDCHG_VTH_SHIFT	10
-#define BQ257X0_PROCHOT_OPTION_1_IDCHG_VTH_BITS		6
-
-#define BQ257X0_PROCHOT_OPTION_1_PP_COMP_SHIFT		6
-#define BQ257X0_PROCHOT_OPTION_1_PP_COMP_BITS		1
-#define BQ257X0_PROCHOT_OPTION_1_PP_COMP__DISABLE	0
-#define BQ257X0_PROCHOT_OPTION_1_PP_COMP__ENABLE	1
-
-#define BQ257X0_PROCHOT_OPTION_1_PP_INOM_SHIFT		4
-#define BQ257X0_PROCHOT_OPTION_1_PP_INOM_BITS		1
-#define BQ257X0_PROCHOT_OPTION_1_PP_INOM__DISABLE	0
-#define BQ257X0_PROCHOT_OPTION_1_PP_INOM__ENABLE	1
-
-#define BQ257X0_PROCHOT_OPTION_1_PP_IDCHG_SHIFT		3
-#define BQ257X0_PROCHOT_OPTION_1_PP_IDCHG_BITS		1
-#define BQ257X0_PROCHOT_OPTION_1_PP_IDCHG__DISABLE	0
-#define BQ257X0_PROCHOT_OPTION_1_PP_IDCHG__ENABLE	1
-
-#define BQ257X0_PROCHOT_OPTION_1_PP_VDPM_SHIFT		7
-#define BQ257X0_PROCHOT_OPTION_1_PP_VDPM_BITS		1
-#define BQ257X0_PROCHOT_OPTION_1_PP_VDPM__DISABLE	0
-#define BQ257X0_PROCHOT_OPTION_1_PP_VDPM__ENABLE	1
-
-#define BQ257X0_PROCHOT_OPTION_1_PP_VSYS_SHIFT		2
-#define BQ257X0_PROCHOT_OPTION_1_PP_VSYS_BITS		1
-#define BQ257X0_PROCHOT_OPTION_1_PP_VSYS__DISABLE	0
-#define BQ257X0_PROCHOT_OPTION_1_PP_VSYS__ENABLE	1
-
-#define BQ257X0_PROCHOT_OPTION_1_PP_BATPRES_SHIFT	1
-#define BQ257X0_PROCHOT_OPTION_1_PP_BATPRES_BITS	1
-#define BQ257X0_PROCHOT_OPTION_1_PP_BATPRES__DISABLE	0
-#define BQ257X0_PROCHOT_OPTION_1_PP_BATPRES__ENABLE	1
-
-#define BQ257X0_PROCHOT_OPTION_1_PP_ACOK_SHIFT		0
-#define BQ257X0_PROCHOT_OPTION_1_PP_ACOK_BITS		1
-#define BQ257X0_PROCHOT_OPTION_1_PP_ACOK__DISABLE	0
-#define BQ257X0_PROCHOT_OPTION_1_PP_ACOK__ENABLE	1
+#define BQ257X0_PROCHOT_OPTION_1_IDCHG_VTH_SHIFT 10
+#define BQ257X0_PROCHOT_OPTION_1_IDCHG_VTH_BITS 6
+
+#define BQ257X0_PROCHOT_OPTION_1_PP_COMP_SHIFT 6
+#define BQ257X0_PROCHOT_OPTION_1_PP_COMP_BITS 1
+#define BQ257X0_PROCHOT_OPTION_1_PP_COMP__DISABLE 0
+#define BQ257X0_PROCHOT_OPTION_1_PP_COMP__ENABLE 1
+
+#define BQ257X0_PROCHOT_OPTION_1_PP_INOM_SHIFT 4
+#define BQ257X0_PROCHOT_OPTION_1_PP_INOM_BITS 1
+#define BQ257X0_PROCHOT_OPTION_1_PP_INOM__DISABLE 0
+#define BQ257X0_PROCHOT_OPTION_1_PP_INOM__ENABLE 1
+
+#define BQ257X0_PROCHOT_OPTION_1_PP_IDCHG_SHIFT 3
+#define BQ257X0_PROCHOT_OPTION_1_PP_IDCHG_BITS 1
+#define BQ257X0_PROCHOT_OPTION_1_PP_IDCHG__DISABLE 0
+#define BQ257X0_PROCHOT_OPTION_1_PP_IDCHG__ENABLE 1
+
+#define BQ257X0_PROCHOT_OPTION_1_PP_VDPM_SHIFT 7
+#define BQ257X0_PROCHOT_OPTION_1_PP_VDPM_BITS 1
+#define BQ257X0_PROCHOT_OPTION_1_PP_VDPM__DISABLE 0
+#define BQ257X0_PROCHOT_OPTION_1_PP_VDPM__ENABLE 1
+
+#define BQ257X0_PROCHOT_OPTION_1_PP_VSYS_SHIFT 2
+#define BQ257X0_PROCHOT_OPTION_1_PP_VSYS_BITS 1
+#define BQ257X0_PROCHOT_OPTION_1_PP_VSYS__DISABLE 0
+#define BQ257X0_PROCHOT_OPTION_1_PP_VSYS__ENABLE 1
+
+#define BQ257X0_PROCHOT_OPTION_1_PP_BATPRES_SHIFT 1
+#define BQ257X0_PROCHOT_OPTION_1_PP_BATPRES_BITS 1
+#define BQ257X0_PROCHOT_OPTION_1_PP_BATPRES__DISABLE 0
+#define BQ257X0_PROCHOT_OPTION_1_PP_BATPRES__ENABLE 1
+
+#define BQ257X0_PROCHOT_OPTION_1_PP_ACOK_SHIFT 0
+#define BQ257X0_PROCHOT_OPTION_1_PP_ACOK_BITS 1
+#define BQ257X0_PROCHOT_OPTION_1_PP_ACOK__DISABLE 0
+#define BQ257X0_PROCHOT_OPTION_1_PP_ACOK__ENABLE 1
 
 /*
  * ChargeCurrent Register (0x14)
  */
-#define BQ257X0_CHARGE_CURRENT_CHARGE_CURRENT_SHIFT	6
-#define BQ257X0_CHARGE_CURRENT_CHARGE_CURRENT_BITS	7
+#define BQ257X0_CHARGE_CURRENT_CHARGE_CURRENT_SHIFT 6
+#define BQ257X0_CHARGE_CURRENT_CHARGE_CURRENT_BITS 7
 
 /*
  * IIN_DPM Register (0x22)
  */
-#define BQ257X0_IIN_DPM_CURRENT_SHIFT			8
-#define BQ257X0_IIN_DPM_CURRENT_BITS			7
-#define BQ257X0_IIN_DPM_CURRENT_STEP_MA			50
+#define BQ257X0_IIN_DPM_CURRENT_SHIFT 8
+#define BQ257X0_IIN_DPM_CURRENT_BITS 7
+#define BQ257X0_IIN_DPM_CURRENT_STEP_MA 50
 
 /*
  * IIN_HOST Register (0x3f)
  */
-#define BQ257X0_IIN_HOST_CURRENT_SHIFT			8
-#define BQ257X0_IIN_HOST_CURRENT_BITS			7
-#define BQ257X0_IIN_HOST_CURRENT_STEP_MA		50
+#define BQ257X0_IIN_HOST_CURRENT_SHIFT 8
+#define BQ257X0_IIN_HOST_CURRENT_BITS 7
+#define BQ257X0_IIN_HOST_CURRENT_STEP_MA 50
 
 /*
  * ADCOption Register (0x35)
  */
-#define BQ257X0_ADC_OPTION_ADC_START_SHIFT		14
-#define BQ257X0_ADC_OPTION_ADC_START_BITS		1
-#define BQ257X0_ADC_OPTION_ADC_FULLSCALE_SHIFT		13
-#define BQ257X0_ADC_OPTION_ADC_FULLSCALE_BITS		1
+#define BQ257X0_ADC_OPTION_ADC_START_SHIFT 14
+#define BQ257X0_ADC_OPTION_ADC_START_BITS 1
+#define BQ257X0_ADC_OPTION_ADC_FULLSCALE_SHIFT 13
+#define BQ257X0_ADC_OPTION_ADC_FULLSCALE_BITS 1
 
-#define BQ257X0_ADC_OPTION_EN_ADC_VBUS_SHIFT		6
-#define BQ257X0_ADC_OPTION_EN_ADC_VBUS_BITS		1
-#define BQ257X0_ADC_OPTION_EN_ADC_ALL			GENMASK(7, 0)
+#define BQ257X0_ADC_OPTION_EN_ADC_VBUS_SHIFT 6
+#define BQ257X0_ADC_OPTION_EN_ADC_VBUS_BITS 1
+#define BQ257X0_ADC_OPTION_EN_ADC_ALL GENMASK(7, 0)
 
 /*
  * ADCVBUS/PSYS Register (0x23)
  */
-#define BQ257X0_ADC_VBUS_PSYS_VBUS_SHIFT		8
-#define BQ257X0_ADC_VBUS_PSYS_VBUS_BITS			8
-#define BQ257X0_ADC_VBUS_PSYS_PSYS_SHIFT		0
-#define BQ257X0_ADC_VBUS_PSYS_PSYS_BITS			8
+#define BQ257X0_ADC_VBUS_PSYS_VBUS_SHIFT 8
+#define BQ257X0_ADC_VBUS_PSYS_VBUS_BITS 8
+#define BQ257X0_ADC_VBUS_PSYS_PSYS_SHIFT 0
+#define BQ257X0_ADC_VBUS_PSYS_PSYS_BITS 8
 
 /*
  * VSYS_MIN Register (0x3e)
  */
-#define BQ25710_MIN_SYSTEM_VOLTAGE_SHIFT		8
-#define BQ25710_MIN_SYSTEM_VOLTAGE_BITS			6
-#define BQ25720_VSYS_MIN_VOLTAGE_SHIFT			8
-#define BQ25720_VSYS_MIN_VOLTAGE_BITS			8
+#define BQ25710_MIN_SYSTEM_VOLTAGE_SHIFT 8
+#define BQ25710_MIN_SYSTEM_VOLTAGE_BITS 6
+#define BQ25720_VSYS_MIN_VOLTAGE_SHIFT 8
+#define BQ25720_VSYS_MIN_VOLTAGE_BITS 8
 
 /*
  * BQ257x0 register field accessor macros.
@@ -249,10 +249,9 @@
  *  _field	register field name
  */
 
-#define BQ_FIELD_MASK(_chip, _reg, _field)				\
-	GENMASK(							\
-		(_chip##_##_reg##_##_field##_SHIFT +			\
-		 _chip##_##_reg##_##_field##_BITS - 1),			\
+#define BQ_FIELD_MASK(_chip, _reg, _field)              \
+	GENMASK((_chip##_##_reg##_##_field##_SHIFT +    \
+		 _chip##_##_reg##_##_field##_BITS - 1), \
 		_chip##_##_reg##_##_field##_SHIFT)
 
 /*
@@ -264,8 +263,8 @@
  *  _x		the value of the register to be examined
  */
 
-#define GET_BQ_FIELD(_chip, _reg, _field, _x)			\
-	(((_x) >> _chip##_##_reg##_##_field##_SHIFT) &		\
+#define GET_BQ_FIELD(_chip, _reg, _field, _x)          \
+	(((_x) >> _chip##_##_reg##_##_field##_SHIFT) & \
 	 GENMASK(_chip##_##_reg##_##_field##_BITS - 1, 0))
 
 /*
@@ -279,11 +278,10 @@
  *  _x		the initial value of the register
  */
 
-#define SET_BQ_FIELD(_chip, _reg, _field, _v, _x)			\
-	(((_x) & ~BQ_FIELD_MASK(_chip, _reg, _field)) |			\
-	 (((_v) &							\
-	   GENMASK(_chip##_##_reg##_##_field##_BITS - 1, 0)) <<		\
-	  _chip##_##_reg##_##_field##_SHIFT))
+#define SET_BQ_FIELD(_chip, _reg, _field, _v, _x)                 \
+	(((_x) & ~BQ_FIELD_MASK(_chip, _reg, _field)) |           \
+	 (((_v)&GENMASK(_chip##_##_reg##_##_field##_BITS - 1, 0)) \
+	  << _chip##_##_reg##_##_field##_SHIFT))
 
 /*
  * Given a register value, sets the specified field to the predefined
@@ -296,8 +294,8 @@
  *  _x		the initial value of the register
  */
 
-#define SET_BQ_FIELD_BY_NAME(_chip, _reg, _field, _c, _x)		\
-	SET_BQ_FIELD(_chip, _reg, _field,				\
-		     _chip##_##_reg##_##_field##__##_c, (_x))
+#define SET_BQ_FIELD_BY_NAME(_chip, _reg, _field, _c, _x)                    \
+	SET_BQ_FIELD(_chip, _reg, _field, _chip##_##_reg##_##_field##__##_c, \
+		     (_x))
 
 #endif /* __CROS_EC_BQ257X0_REGS_H */
diff --git a/driver/charger/isl923x.c b/driver/charger/isl923x.c
index c90fe5224e..84f833cc64 100644
--- a/driver/charger/isl923x.c
+++ b/driver/charger/isl923x.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,6 +8,7 @@
 #include "adc.h"
 #include "battery.h"
 #include "battery_smart.h"
+#include "builtin/assert.h"
 #include "charge_state_v2.h"
 #include "charger.h"
 #include "compile_time_macros.h"
@@ -32,62 +33,61 @@
 #endif
 
 #ifdef CONFIG_CHARGER_SENSE_RESISTOR_AC_ISL9238
-	#undef CONFIG_CHARGER_SENSE_RESISTOR_AC
-	#define CONFIG_CHARGER_SENSE_RESISTOR_AC \
-		CONFIG_CHARGER_SENSE_RESISTOR_AC_ISL9238
+#undef CONFIG_CHARGER_SENSE_RESISTOR_AC
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC \
+	CONFIG_CHARGER_SENSE_RESISTOR_AC_ISL9238
 #endif
 
-
 #define DEFAULT_R_AC 20
 #define DEFAULT_R_SNS 10
 #define R_AC CONFIG_CHARGER_SENSE_RESISTOR_AC
 #define R_SNS CONFIG_CHARGER_SENSE_RESISTOR
-#define REG_TO_CURRENT(REG) ((REG) * DEFAULT_R_SNS / R_SNS)
-#define CURRENT_TO_REG(CUR) ((CUR) * R_SNS / DEFAULT_R_SNS)
-#define AC_REG_TO_CURRENT(REG) ((REG) * DEFAULT_R_AC / R_AC)
-#define AC_CURRENT_TO_REG(CUR) ((CUR) * R_AC / DEFAULT_R_AC)
+#define REG_TO_CURRENT(REG) ((REG)*DEFAULT_R_SNS / R_SNS)
+#define CURRENT_TO_REG(CUR) ((CUR)*R_SNS / DEFAULT_R_SNS)
+#define AC_REG_TO_CURRENT(REG) ((REG)*DEFAULT_R_AC / R_AC)
+#define AC_CURRENT_TO_REG(CUR) ((CUR)*R_AC / DEFAULT_R_AC)
 
 #if defined(CONFIG_CHARGER_ISL9237)
-#define CHARGER_NAME  "isl9237"
-#define CHARGE_V_MAX  ISL9237_SYS_VOLTAGE_REG_MAX
-#define CHARGE_V_MIN  ISL923X_SYS_VOLTAGE_REG_MIN
+#define CHARGER_NAME "isl9237"
+#define CHARGE_V_MAX ISL9237_SYS_VOLTAGE_REG_MAX
+#define CHARGE_V_MIN ISL923X_SYS_VOLTAGE_REG_MIN
 #define CHARGE_V_STEP 8
 #elif defined(CONFIG_CHARGER_ISL9238)
-#define CHARGER_NAME  "isl9238"
-#define CHARGE_V_MAX  ISL9238_SYS_VOLTAGE_REG_MAX
-#define CHARGE_V_MIN  ISL923X_SYS_VOLTAGE_REG_MIN
+#define CHARGER_NAME "isl9238"
+#define CHARGE_V_MAX ISL9238_SYS_VOLTAGE_REG_MAX
+#define CHARGE_V_MIN ISL923X_SYS_VOLTAGE_REG_MIN
 #define CHARGE_V_STEP 8
 #elif defined(CONFIG_CHARGER_ISL9238C)
-#define CHARGER_NAME  "isl9238c"
-#define CHARGE_V_MAX  ISL9238_SYS_VOLTAGE_REG_MAX
-#define CHARGE_V_MIN  ISL923X_SYS_VOLTAGE_REG_MIN
+#define CHARGER_NAME "isl9238c"
+#define CHARGE_V_MAX ISL9238_SYS_VOLTAGE_REG_MAX
+#define CHARGE_V_MIN ISL923X_SYS_VOLTAGE_REG_MIN
 #define CHARGE_V_STEP 8
 #elif defined(CONFIG_CHARGER_RAA489000)
-#define CHARGER_NAME  "raa489000"
-#define CHARGE_V_MAX  RAA489000_SYS_VOLTAGE_REG_MAX
-#define CHARGE_V_MIN  RAA489000_SYS_VOLTAGE_REG_MIN
+#define CHARGER_NAME "raa489000"
+#define CHARGE_V_MAX RAA489000_SYS_VOLTAGE_REG_MAX
+#define CHARGE_V_MIN RAA489000_SYS_VOLTAGE_REG_MIN
 #define CHARGE_V_STEP 8
 #endif
 
 #ifdef CONFIG_CHARGER_RAA489000
-#define CHARGE_I_MAX  RAA489000_CURRENT_REG_MAX
+#define CHARGE_I_MAX RAA489000_CURRENT_REG_MAX
 #else
-#define CHARGE_I_MAX  ISL923X_CURRENT_REG_MAX
+#define CHARGE_I_MAX ISL923X_CURRENT_REG_MAX
 #endif /* CONFIG_CHARGER_RAA489000 */
-#define CHARGE_I_MIN  4
-#define CHARGE_I_OFF  0
+#define CHARGE_I_MIN 4
+#define CHARGE_I_OFF 0
 #define CHARGE_I_STEP 4
 #ifdef CONFIG_CHARGER_RAA489000
-#define INPUT_I_MAX   RAA489000_CURRENT_REG_MAX
+#define INPUT_I_MAX RAA489000_CURRENT_REG_MAX
 #else
-#define INPUT_I_MAX   ISL923X_CURRENT_REG_MAX
+#define INPUT_I_MAX ISL923X_CURRENT_REG_MAX
 #endif /* CONFIG_CHARGER_RAA489000 */
-#define INPUT_I_MIN   4
-#define INPUT_I_STEP  4
+#define INPUT_I_MIN 4
+#define INPUT_I_STEP 4
 
 /* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 enum isl923x_amon_bmon { AMON, BMON };
 enum isl923x_mon_dir { MON_CHARGE = 0, MON_DISCHARGE = 1 };
@@ -102,38 +102,36 @@ static enum ec_error_list isl923x_discharge_on_ac_weak_disable(int chgnum);
 
 /* Charger parameters */
 static const struct charger_info isl9237_charger_info = {
-	.name         = CHARGER_NAME,
-	.voltage_max  = CHARGE_V_MAX,
-	.voltage_min  = CHARGE_V_MIN,
+	.name = CHARGER_NAME,
+	.voltage_max = CHARGE_V_MAX,
+	.voltage_min = CHARGE_V_MIN,
 	.voltage_step = CHARGE_V_STEP,
-	.current_max  = REG_TO_CURRENT(CHARGE_I_MAX),
-	.current_min  = REG_TO_CURRENT(CHARGE_I_MIN),
+	.current_max = REG_TO_CURRENT(CHARGE_I_MAX),
+	.current_min = REG_TO_CURRENT(CHARGE_I_MIN),
 	.current_step = REG_TO_CURRENT(CHARGE_I_STEP),
-	.input_current_max  = AC_REG_TO_CURRENT(INPUT_I_MAX),
-	.input_current_min  = AC_REG_TO_CURRENT(INPUT_I_MIN),
+	.input_current_max = AC_REG_TO_CURRENT(INPUT_I_MAX),
+	.input_current_min = AC_REG_TO_CURRENT(INPUT_I_MIN),
 	.input_current_step = AC_REG_TO_CURRENT(INPUT_I_STEP),
 };
 
 static inline enum ec_error_list raw_read16(int chgnum, int offset, int *value)
 {
 	return i2c_read16(chg_chips[chgnum].i2c_port,
-			  chg_chips[chgnum].i2c_addr_flags,
-			  offset, value);
+			  chg_chips[chgnum].i2c_addr_flags, offset, value);
 }
 
 static inline enum ec_error_list raw_write16(int chgnum, int offset, int value)
 {
 	return i2c_write16(chg_chips[chgnum].i2c_port,
-			   chg_chips[chgnum].i2c_addr_flags,
-			   offset, value);
+			   chg_chips[chgnum].i2c_addr_flags, offset, value);
 }
 
 static inline enum ec_error_list raw_update16(int chgnum, int offset, int mask,
 					      enum mask_update_action action)
 {
 	return i2c_update16(chg_chips[chgnum].i2c_port,
-			    chg_chips[chgnum].i2c_addr_flags,
-			    offset, mask, action);
+			    chg_chips[chgnum].i2c_addr_flags, offset, mask,
+			    action);
 }
 
 static enum ec_error_list isl9237_set_current(int chgnum, uint16_t current)
@@ -236,7 +234,7 @@ static enum ec_error_list isl923x_get_input_current_limit(int chgnum,
 
 #ifdef CONFIG_CHARGER_RAA489000
 static enum ec_error_list raa489000_get_input_current(int chgnum,
-						    int *input_current)
+						      int *input_current)
 {
 	int rv;
 	int regval;
@@ -305,13 +303,13 @@ static enum ec_error_list isl923x_set_otg_current_voltage(int chgnum,
 {
 	int rv;
 	uint16_t volt_reg = (output_voltage / ISL9238_OTG_VOLTAGE_STEP)
-			<< ISL9238_OTG_VOLTAGE_SHIFT;
+			    << ISL9238_OTG_VOLTAGE_SHIFT;
 	uint16_t current_reg =
 		DIV_ROUND_UP(output_current, ISL923X_OTG_CURRENT_STEP)
-			<< ISL923X_OTG_CURRENT_SHIFT;
+		<< ISL923X_OTG_CURRENT_SHIFT;
 
 	if (output_current < 0 || output_current > ISL923X_OTG_CURRENT_MAX ||
-			output_voltage > ISL9238_OTG_VOLTAGE_MAX)
+	    output_voltage > ISL9238_OTG_VOLTAGE_MAX)
 		return EC_ERROR_INVAL;
 
 	/* Set voltage. */
@@ -554,8 +552,8 @@ int isl923x_set_comparator_inversion(int chgnum, int invert)
 	int regval;
 
 	rv = i2c_read16(chg_chips[chgnum].i2c_port,
-			chg_chips[chgnum].i2c_addr_flags,
-			ISL923X_REG_CONTROL2, &regval);
+			chg_chips[chgnum].i2c_addr_flags, ISL923X_REG_CONTROL2,
+			&regval);
 	if (invert)
 		regval |= ISL923X_C2_INVERT_CMOUT;
 	else
@@ -577,8 +575,8 @@ static void isl923x_init(int chgnum)
 {
 	int reg;
 	const struct battery_info *bi = battery_get_info();
-	int precharge_voltage = bi->precharge_voltage ?
-		bi->precharge_voltage : bi->voltage_min;
+	int precharge_voltage = bi->precharge_voltage ? bi->precharge_voltage :
+							bi->voltage_min;
 
 	if (IS_ENABLED(CONFIG_CHARGER_RAA489000)) {
 		if (CONFIG_CHARGER_SENSE_RESISTOR ==
@@ -590,9 +588,9 @@ static void isl923x_init(int chgnum)
 			if (raw_read16(chgnum, ISL9238_REG_CONTROL4, &reg))
 				goto init_fail;
 
-			if (raw_write16(chgnum, ISL9238_REG_CONTROL4,
-					reg |
-					RAA489000_C4_PSYS_RSNS_RATIO_1_TO_1))
+			if (raw_write16(
+				    chgnum, ISL9238_REG_CONTROL4,
+				    reg | RAA489000_C4_PSYS_RSNS_RATIO_1_TO_1))
 				goto init_fail;
 		}
 
@@ -603,8 +601,7 @@ static void isl923x_init(int chgnum)
 			goto init_fail;
 
 		if (raw_write16(chgnum, ISL9238_REG_CONTROL3,
-				reg |
-				RAA489000_C3_DCM_CCM_HYSTERESIS_ENABLE))
+				reg | RAA489000_C3_DCM_CCM_HYSTERESIS_ENABLE))
 			goto init_fail;
 
 		/* Set switching frequency to 600KHz to help with ripple. */
@@ -614,8 +611,7 @@ static void isl923x_init(int chgnum)
 		reg &= ~ISL923X_C1_SWITCH_FREQ_MASK;
 
 		if (raw_write16(chgnum, ISL923X_REG_CONTROL1,
-				reg |
-				ISL9237_C1_SWITCH_FREQ_599K))
+				reg | ISL9237_C1_SWITCH_FREQ_599K))
 			goto init_fail;
 	}
 
@@ -650,8 +646,7 @@ static void isl923x_init(int chgnum)
 		reg |= ISL923X_C2_PROCHOT_DEBOUNCE_1000;
 
 	if (raw_write16(chgnum, ISL923X_REG_CONTROL2,
-			reg |
-			ISL923X_C2_ADAPTER_DEBOUNCE_150))
+			reg | ISL923X_C2_ADAPTER_DEBOUNCE_150))
 		goto init_fail;
 
 	/*
@@ -687,10 +682,10 @@ static void isl923x_init(int chgnum)
 			 */
 			if (IS_ENABLED(CONFIG_CHARGER_RAA489000))
 				reg = (4437 / RAA489000_INPUT_VOLTAGE_REF_STEP)
-					<< RAA489000_INPUT_VOLTAGE_REF_SHIFT;
+				      << RAA489000_INPUT_VOLTAGE_REF_SHIFT;
 			else
 				reg = (4439 / ISL9238_INPUT_VOLTAGE_REF_STEP)
-					<< ISL9238_INPUT_VOLTAGE_REF_SHIFT;
+				      << ISL9238_INPUT_VOLTAGE_REF_SHIFT;
 
 			if (raw_write16(chgnum, ISL9238_REG_INPUT_VOLTAGE, reg))
 				goto init_fail;
@@ -762,7 +757,7 @@ static void isl923x_init(int chgnum)
 		 * Initialize the input current limit to the board's default.
 		 */
 		if (isl923x_set_input_current_limit(
-				chgnum, CONFIG_CHARGER_INPUT_CURRENT))
+			    chgnum, CONFIG_CHARGER_INPUT_CURRENT))
 			goto init_fail;
 	}
 
@@ -975,16 +970,15 @@ enum ec_error_list isl9238c_hibernate(int chgnum)
 {
 	/* Disable PSYS */
 	RETURN_ERROR(raw_update16(chgnum, ISL923X_REG_CONTROL1,
-				ISL923X_C1_ENABLE_PSYS, MASK_CLR));
+				  ISL923X_C1_ENABLE_PSYS, MASK_CLR));
 
 	/* Disable GP comparator */
 	RETURN_ERROR(raw_update16(chgnum, ISL923X_REG_CONTROL2,
-				ISL923X_C2_COMPARATOR, MASK_SET));
+				  ISL923X_C2_COMPARATOR, MASK_SET));
 
 	/* Force BGATE off */
 	RETURN_ERROR(raw_update16(chgnum, ISL9238_REG_CONTROL3,
-				ISL9238_C3_BGATE_OFF, MASK_SET));
-
+				  ISL9238_C3_BGATE_OFF, MASK_SET));
 
 	return EC_SUCCESS;
 }
@@ -993,18 +987,17 @@ enum ec_error_list isl9238c_resume(int chgnum)
 {
 	/* Revert everything in isl9238c_hibernate() */
 	RETURN_ERROR(raw_update16(chgnum, ISL923X_REG_CONTROL1,
-				ISL923X_C1_ENABLE_PSYS, MASK_SET));
+				  ISL923X_C1_ENABLE_PSYS, MASK_SET));
 
 	RETURN_ERROR(raw_update16(chgnum, ISL923X_REG_CONTROL2,
-				ISL923X_C2_COMPARATOR, MASK_CLR));
+				  ISL923X_C2_COMPARATOR, MASK_CLR));
 
 	RETURN_ERROR(raw_update16(chgnum, ISL9238_REG_CONTROL3,
-				ISL9238_C3_BGATE_OFF, MASK_CLR));
+				  ISL9238_C3_BGATE_OFF, MASK_CLR));
 
 	return EC_SUCCESS;
 }
 
-
 /*****************************************************************************/
 /* Hardware current ramping */
 
@@ -1038,7 +1031,6 @@ static int isl923x_ramp_get_current_limit(int chgnum)
 }
 #endif /* CONFIG_CHARGE_RAMP_HW */
 
-
 #ifdef CONFIG_CHARGER_PSYS
 static int psys_enabled;
 /*
@@ -1115,13 +1107,12 @@ int charger_get_system_power(void)
 	return adc;
 }
 
-static int console_command_psys(int argc, char **argv)
+static int console_command_psys(int argc, const char **argv)
 {
 	ccprintf("PSYS = %d uW\n", charger_get_system_power());
 	return 0;
 }
-DECLARE_CONSOLE_COMMAND(psys, console_command_psys,
-			NULL,
+DECLARE_CONSOLE_COMMAND(psys, console_command_psys, NULL,
 			"Get the system power in mW");
 #endif /* CONFIG_CHARGER_PSYS_READ */
 #endif /* CONFIG_CHARGER_PSYS */
@@ -1138,7 +1129,7 @@ static int print_amon_bmon(int chgnum, enum isl923x_amon_bmon amon,
 
 	curr = adc / resistor;
 	ccprintf("%cMON(%sharging): %d uV, %d mA\n", amon == AMON ? 'A' : 'B',
-		direction == MON_DISCHARGE ? "Disc" : "C", adc, curr);
+		 direction == MON_DISCHARGE ? "Disc" : "C", adc, curr);
 
 	return ret;
 }
@@ -1146,7 +1137,7 @@ static int print_amon_bmon(int chgnum, enum isl923x_amon_bmon amon,
 /**
  * Get charger AMON and BMON current.
  */
-static int console_command_amon_bmon(int argc, char **argv)
+static int console_command_amon_bmon(int argc, const char **argv)
 {
 	int ret = EC_SUCCESS;
 	int print_ac = 1;
@@ -1172,24 +1163,27 @@ static int console_command_amon_bmon(int argc, char **argv)
 
 	if (print_ac) {
 		if (print_charge)
-			ret |= print_amon_bmon(chgnum, AMON, MON_CHARGE,
-					CONFIG_CHARGER_SENSE_RESISTOR_AC);
+			ret |= print_amon_bmon(
+				chgnum, AMON, MON_CHARGE,
+				CONFIG_CHARGER_SENSE_RESISTOR_AC);
 		if (IS_ENABLED(CHARGER_ISL9238X) && print_discharge)
-			ret |= print_amon_bmon(chgnum, AMON, MON_DISCHARGE,
-					CONFIG_CHARGER_SENSE_RESISTOR_AC);
+			ret |= print_amon_bmon(
+				chgnum, AMON, MON_DISCHARGE,
+				CONFIG_CHARGER_SENSE_RESISTOR_AC);
 	}
 
 	if (print_battery) {
 		if (IS_ENABLED(CHARGER_ISL9238X) && print_charge)
-			ret |= print_amon_bmon(chgnum, BMON, MON_CHARGE,
-					/*
-					 * charging current monitor has
-					 * 2x amplification factor
-					 */
-					2 * CONFIG_CHARGER_SENSE_RESISTOR);
+			ret |= print_amon_bmon(
+				chgnum, BMON, MON_CHARGE,
+				/*
+				 * charging current monitor has
+				 * 2x amplification factor
+				 */
+				2 * CONFIG_CHARGER_SENSE_RESISTOR);
 		if (print_discharge)
 			ret |= print_amon_bmon(chgnum, BMON, MON_DISCHARGE,
-					CONFIG_CHARGER_SENSE_RESISTOR);
+					       CONFIG_CHARGER_SENSE_RESISTOR);
 	}
 
 	return ret;
@@ -1213,8 +1207,7 @@ static void dump_reg_range(int chgnum, int low, int high)
 	for (reg = low; reg <= high; reg++) {
 		CPRINTF("[%Xh] = ", reg);
 		rv = i2c_read16(chg_chips[chgnum].i2c_port,
-				chg_chips[chgnum].i2c_addr_flags,
-				reg, &regval);
+				chg_chips[chgnum].i2c_addr_flags, reg, &regval);
 		if (!rv)
 			CPRINTF("0x%04x\n", regval);
 		else
@@ -1275,15 +1268,14 @@ static enum ec_error_list raa489000_enable_linear_charge(int chgnum,
 
 		/* Disable charge current loop for the aux charger. */
 		rv |= raw_update16(act_chg, RAA489000_REG_CONTROL10,
-				   RAA489000_C10_DISABLE_DVC_CC_LOOP,
-				   MASK_SET);
+				   RAA489000_C10_DISABLE_DVC_CC_LOOP, MASK_SET);
 
 		/*
 		 * Set primary charger charge current to the desired precharge
 		 * current.
 		 */
 		rv |= isl9237_set_current(CHARGER_PRIMARY,
-				    batt_info->precharge_current);
+					  batt_info->precharge_current);
 
 		/*
 		 * Set primary charger max VSYS to the max of the battery.
@@ -1307,10 +1299,11 @@ static enum ec_error_list raa489000_enable_linear_charge(int chgnum,
 				  regval);
 
 		/* Enable DVC trickle charge and DVC charge mode. */
-		rv |= raw_update16(CHARGER_PRIMARY, RAA489000_REG_CONTROL10,
-				   RAA489000_C10_ENABLE_DVC_MODE |
-				   RAA489000_C10_ENABLE_DVC_TRICKLE_CHARGE,
-				   MASK_SET);
+		rv |= raw_update16(
+			CHARGER_PRIMARY, RAA489000_REG_CONTROL10,
+			RAA489000_C10_ENABLE_DVC_MODE |
+				RAA489000_C10_ENABLE_DVC_TRICKLE_CHARGE,
+			MASK_SET);
 
 		if (rv)
 			return EC_ERROR_UNKNOWN;
diff --git a/driver/charger/isl923x.h b/driver/charger/isl923x.h
index 0de2a32ae5..e4ce34ee66 100644
--- a/driver/charger/isl923x.h
+++ b/driver/charger/isl923x.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -12,29 +12,29 @@
 #include "driver/charger/isl923x_public.h"
 
 /* Registers */
-#define ISL923X_REG_CHG_CURRENT            0x14
+#define ISL923X_REG_CHG_CURRENT 0x14
 #define ISL923X_REG_ADAPTER_CURRENT_LIMIT1 0x3f
 #define ISL923X_REG_ADAPTER_CURRENT_LIMIT2 0x3b
-#define ISL923X_REG_SYS_VOLTAGE_MAX        0x15
-#define ISL923X_REG_SYS_VOLTAGE_MIN        0x3e
-#define ISL923X_REG_PROCHOT_AC             0x47
-#define ISL923X_REG_PROCHOT_DC             0x48
-#define ISL923X_REG_T1_T2                  0x38
-#define ISL923X_REG_CONTROL0               0x39
-#define ISL923X_REG_CONTROL1               0x3c
-#define ISL923X_REG_CONTROL2               0x3d
-#define ISL9238_REG_CONTROL3               0x4c
-#define ISL9238_REG_CONTROL4               0x4e
-#define ISL9238C_REG_CONTROL6              0x37
-#define ISL923X_REG_INFO                   0x3a
-#define ISL9238_REG_INFO2                  0x4d
-#define ISL923X_REG_OTG_VOLTAGE            0x49
-#define ISL923X_REG_OTG_CURRENT            0x4a
-#define ISL9238_REG_INPUT_VOLTAGE          0x4b
-#define ISL923X_REG_MANUFACTURER_ID        0xfe
-#define ISL923X_REG_DEVICE_ID              0xff
-#define RAA489000_REG_CONTROL8             0x37
-#define RAA489000_REG_CONTROL10            0x35
+#define ISL923X_REG_SYS_VOLTAGE_MAX 0x15
+#define ISL923X_REG_SYS_VOLTAGE_MIN 0x3e
+#define ISL923X_REG_PROCHOT_AC 0x47
+#define ISL923X_REG_PROCHOT_DC 0x48
+#define ISL923X_REG_T1_T2 0x38
+#define ISL923X_REG_CONTROL0 0x39
+#define ISL923X_REG_CONTROL1 0x3c
+#define ISL923X_REG_CONTROL2 0x3d
+#define ISL9238_REG_CONTROL3 0x4c
+#define ISL9238_REG_CONTROL4 0x4e
+#define ISL9238C_REG_CONTROL6 0x37
+#define ISL923X_REG_INFO 0x3a
+#define ISL9238_REG_INFO2 0x4d
+#define ISL923X_REG_OTG_VOLTAGE 0x49
+#define ISL923X_REG_OTG_CURRENT 0x4a
+#define ISL9238_REG_INPUT_VOLTAGE 0x4b
+#define ISL923X_REG_MANUFACTURER_ID 0xfe
+#define ISL923X_REG_DEVICE_ID 0xff
+#define RAA489000_REG_CONTROL8 0x37
+#define RAA489000_REG_CONTROL10 0x35
 
 /* Sense resistor default values in mOhm */
 #define ISL923X_DEFAULT_SENSE_RESISTOR_AC 20
@@ -48,18 +48,18 @@
 #define ISL923X_T1_10000 0x00
 #define ISL923X_T1_20000 0x01
 #define ISL923X_T1_15000 0x02
-#define ISL923X_T1_5000  0x03
-#define ISL923X_T1_1000  0x04
-#define ISL923X_T1_500   0x05
-#define ISL923X_T1_100   0x06
-#define ISL923X_T1_0     0x07
-#define ISL923X_T2_10    (0x00 << 8)
-#define ISL923X_T2_100   (0x01 << 8)
-#define ISL923X_T2_500   (0x02 << 8)
-#define ISL923X_T2_1000  (0x03 << 8)
-#define ISL923X_T2_300   (0x04 << 8)
-#define ISL923X_T2_750   (0x05 << 8)
-#define ISL923X_T2_2000  (0x06 << 8)
+#define ISL923X_T1_5000 0x03
+#define ISL923X_T1_1000 0x04
+#define ISL923X_T1_500 0x05
+#define ISL923X_T1_100 0x06
+#define ISL923X_T1_0 0x07
+#define ISL923X_T2_10 (0x00 << 8)
+#define ISL923X_T2_100 (0x01 << 8)
+#define ISL923X_T2_500 (0x02 << 8)
+#define ISL923X_T2_1000 (0x03 << 8)
+#define ISL923X_T2_300 (0x04 << 8)
+#define ISL923X_T2_750 (0x05 << 8)
+#define ISL923X_T2_2000 (0x06 << 8)
 #define ISL923X_T2_10000 (0x07 << 8)
 
 #define ISL9237_SYS_VOLTAGE_REG_MAX 13824
@@ -69,19 +69,19 @@
 #define RAA489000_SYS_VOLTAGE_REG_MIN 64
 
 /* PROCHOT# debounce time and duration time in micro seconds */
-#define ISL923X_PROCHOT_DURATION_10000  (0 << 6)
-#define ISL923X_PROCHOT_DURATION_20000  BIT(6)
-#define ISL923X_PROCHOT_DURATION_15000  (2 << 6)
-#define ISL923X_PROCHOT_DURATION_5000   (3 << 6)
-#define ISL923X_PROCHOT_DURATION_1000   (4 << 6)
-#define ISL923X_PROCHOT_DURATION_500    (5 << 6)
+#define ISL923X_PROCHOT_DURATION_10000 (0 << 6)
+#define ISL923X_PROCHOT_DURATION_20000 BIT(6)
+#define ISL923X_PROCHOT_DURATION_15000 (2 << 6)
+#define ISL923X_PROCHOT_DURATION_5000 (3 << 6)
+#define ISL923X_PROCHOT_DURATION_1000 (4 << 6)
+#define ISL923X_PROCHOT_DURATION_500 (5 << 6)
 #define ISL923X_PROCHOT_DURATION_100000 (6 << 6)
-#define ISL923X_PROCHOT_DURATION_0      (7 << 6)
-#define ISL923X_PROCHOT_DURATION_MASK   (7 << 6)
+#define ISL923X_PROCHOT_DURATION_0 (7 << 6)
+#define ISL923X_PROCHOT_DURATION_MASK (7 << 6)
 
-#define ISL923X_PROCHOT_DEBOUNCE_10   (0 << 9)
-#define ISL923X_PROCHOT_DEBOUNCE_100  BIT(9)
-#define ISL923X_PROCHOT_DEBOUNCE_500  (2 << 9)
+#define ISL923X_PROCHOT_DEBOUNCE_10 (0 << 9)
+#define ISL923X_PROCHOT_DEBOUNCE_100 BIT(9)
+#define ISL923X_PROCHOT_DEBOUNCE_500 (2 << 9)
 #define ISL923X_PROCHOT_DEBOUNCE_1000 (3 << 9)
 #define ISL923X_PROCHOT_DEBOUNCE_MASK (3 << 9)
 
@@ -100,10 +100,10 @@
 #define ISL923X_C0_DISABLE_VREG BIT(2)
 
 /* Control0: battery DCHOT reference for RS2 == 20mOhm */
-#define ISL923X_C0_DCHOT_6A   (0 << 3)
-#define ISL923X_C0_DCHOT_5A   BIT(3)
-#define ISL923X_C0_DCHOT_4A   (2 << 3)
-#define ISL923X_C0_DCHOT_3A   (3 << 3)
+#define ISL923X_C0_DCHOT_6A (0 << 3)
+#define ISL923X_C0_DCHOT_5A BIT(3)
+#define ISL923X_C0_DCHOT_4A (2 << 3)
+#define ISL923X_C0_DCHOT_3A (3 << 3)
 #define ISL923X_C0_DCHOT_MASK (3 << 3)
 
 /* Control0: BGATE force on */
@@ -111,15 +111,15 @@
 #define RAA489000_C0_EN_CHG_PUMPS_TO_100PCT BIT(6)
 
 /* Control1: general purpose comparator debounce time in micro second */
-#define ISL923X_C1_GP_DEBOUNCE_2       (0 << 14)
-#define ISL923X_C1_GP_DEBOUNCE_12      BIT(14)
-#define ISL923X_C1_GP_DEBOUNCE_2000    (2 << 14)
+#define ISL923X_C1_GP_DEBOUNCE_2 (0 << 14)
+#define ISL923X_C1_GP_DEBOUNCE_12 BIT(14)
+#define ISL923X_C1_GP_DEBOUNCE_2000 (2 << 14)
 #define ISL923X_C1_GP_DEBOUNCE_5000000 (3 << 14)
-#define ISL923X_C1_GP_DEBOUNCE_MASK    (3 << 14)
+#define ISL923X_C1_GP_DEBOUNCE_MASK (3 << 14)
 
 /* Control1: learn mode */
 #define ISL923X_C1_LEARN_MODE_AUTOEXIT BIT(13)
-#define ISL923X_C1_LEARN_MODE_ENABLE   BIT(12)
+#define ISL923X_C1_LEARN_MODE_ENABLE BIT(12)
 
 /* Control1: OTG enable */
 #define ISL923X_C1_OTG BIT(11)
@@ -161,15 +161,15 @@
 #define RAA489000_C1_BGATE_FORCE_OFF BIT(6)
 
 /* Control2: trickle charging current in mA */
-#define ISL923X_C2_TRICKLE_256  (0 << 14)
-#define ISL923X_C2_TRICKLE_128  BIT(14)
-#define ISL923X_C2_TRICKLE_64   (2 << 14)
-#define ISL923X_C2_TRICKLE_512  (3 << 14)
+#define ISL923X_C2_TRICKLE_256 (0 << 14)
+#define ISL923X_C2_TRICKLE_128 BIT(14)
+#define ISL923X_C2_TRICKLE_64 (2 << 14)
+#define ISL923X_C2_TRICKLE_512 (3 << 14)
 #define ISL923X_C2_TRICKLE_MASK (3 << 14)
 
 /* Control2: OTGEN debounce time in ms */
 #define ISL923X_C2_OTG_DEBOUNCE_1300 (0 << 13)
-#define ISL923X_C2_OTG_DEBOUNCE_150  BIT(13)
+#define ISL923X_C2_OTG_DEBOUNCE_150 BIT(13)
 #define ISL923X_C2_OTG_DEBOUNCE_MASK BIT(13)
 
 /* Control2: 2-level adapter over current */
@@ -177,14 +177,14 @@
 
 /* Control2: adapter insertion debounce time in ms */
 #define ISL923X_C2_ADAPTER_DEBOUNCE_1300 (0 << 11)
-#define ISL923X_C2_ADAPTER_DEBOUNCE_150  BIT(11)
+#define ISL923X_C2_ADAPTER_DEBOUNCE_150 BIT(11)
 #define ISL923X_C2_ADAPTER_DEBOUNCE_MASK BIT(11)
 
 /* Control2: PROCHOT debounce time in uS */
-#define ISL9238_C2_PROCHOT_DEBOUNCE_7    (0 << 9)
-#define ISL9237_C2_PROCHOT_DEBOUNCE_10   (0 << 9)
-#define ISL923X_C2_PROCHOT_DEBOUNCE_100  BIT(9)
-#define ISL923X_C2_PROCHOT_DEBOUNCE_500  (2 << 9)
+#define ISL9238_C2_PROCHOT_DEBOUNCE_7 (0 << 9)
+#define ISL9237_C2_PROCHOT_DEBOUNCE_10 (0 << 9)
+#define ISL923X_C2_PROCHOT_DEBOUNCE_100 BIT(9)
+#define ISL923X_C2_PROCHOT_DEBOUNCE_500 (2 << 9)
 #define ISL923X_C2_PROCHOT_DEBOUNCE_1000 (3 << 9)
 #define ISL923X_C2_PROCHOT_DEBOUNCE_MASK (3 << 9)
 
@@ -192,12 +192,12 @@
 #define ISL923X_C2_PROCHOT_DURATION_10000 (0 << 6)
 #define ISL923X_C2_PROCHOT_DURATION_20000 BIT(6)
 #define ISL923X_C2_PROCHOT_DURATION_15000 (2 << 6)
-#define ISL923X_C2_PROCHOT_DURATION_5000  (3 << 6)
-#define ISL923X_C2_PROCHOT_DURATION_1000  (4 << 6)
-#define ISL923X_C2_PROCHOT_DURATION_500   (5 << 6)
-#define ISL923X_C2_PROCHOT_DURATION_100   (6 << 6)
-#define ISL923X_C2_PROCHOT_DURATION_0     (7 << 6)
-#define ISL923X_C2_PROCHOT_DURATION_MASK  (7 << 6)
+#define ISL923X_C2_PROCHOT_DURATION_5000 (3 << 6)
+#define ISL923X_C2_PROCHOT_DURATION_1000 (4 << 6)
+#define ISL923X_C2_PROCHOT_DURATION_500 (5 << 6)
+#define ISL923X_C2_PROCHOT_DURATION_100 (6 << 6)
+#define ISL923X_C2_PROCHOT_DURATION_0 (7 << 6)
+#define ISL923X_C2_PROCHOT_DURATION_MASK (7 << 6)
 
 /* Control2: turn off ASGATE in OTG mode */
 #define ISL923X_C2_ASGATE_OFF BIT(5)
@@ -346,7 +346,7 @@ enum isl9237_fsm_state {
 
 #define I2C_ADDR_CHARGER_FLAGS ISL923X_ADDR_FLAGS
 
-#define ISL923X_AC_PROCHOT_CURRENT_MAX	6400	/* mA */
-#define ISL923X_DC_PROCHOT_CURRENT_MAX	12800	/* mA */
+#define ISL923X_AC_PROCHOT_CURRENT_MAX 6400 /* mA */
+#define ISL923X_DC_PROCHOT_CURRENT_MAX 12800 /* mA */
 
 #endif /* __CROS_EC_ISL923X_H */
diff --git a/driver/charger/isl9241.c b/driver/charger/isl9241.c
index bd84d30755..9ca2e9f3e0 100644
--- a/driver/charger/isl9241.c
+++ b/driver/charger/isl9241.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -29,20 +29,20 @@
 #endif
 
 /* Sense resistor default values in milli Ohm */
-#define ISL9241_DEFAULT_RS1 20	/* Input current sense resistor */
-#define ISL9241_DEFAULT_RS2 10	/* Battery charge current sense resistor */
+#define ISL9241_DEFAULT_RS1 20 /* Input current sense resistor */
+#define ISL9241_DEFAULT_RS2 10 /* Battery charge current sense resistor */
 
 #define BOARD_RS1 CONFIG_CHARGER_SENSE_RESISTOR_AC
 #define BOARD_RS2 CONFIG_CHARGER_SENSE_RESISTOR
 
-#define BC_REG_TO_CURRENT(REG) (((REG) * ISL9241_DEFAULT_RS2) / BOARD_RS2)
-#define BC_CURRENT_TO_REG(CUR) (((CUR) * BOARD_RS2) / ISL9241_DEFAULT_RS2)
+#define BC_REG_TO_CURRENT(REG) (((REG)*ISL9241_DEFAULT_RS2) / BOARD_RS2)
+#define BC_CURRENT_TO_REG(CUR) (((CUR)*BOARD_RS2) / ISL9241_DEFAULT_RS2)
 
-#define AC_REG_TO_CURRENT(REG) (((REG) * ISL9241_DEFAULT_RS1) / BOARD_RS1)
-#define AC_CURRENT_TO_REG(CUR) (((CUR) * BOARD_RS1) / ISL9241_DEFAULT_RS1)
+#define AC_REG_TO_CURRENT(REG) (((REG)*ISL9241_DEFAULT_RS1) / BOARD_RS1)
+#define AC_CURRENT_TO_REG(CUR) (((CUR)*BOARD_RS1) / ISL9241_DEFAULT_RS1)
 
 /* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, "ISL9241 " format, ##args)
 
 static int learn_mode;
 
@@ -51,29 +51,28 @@ K_MUTEX_DEFINE(control1_mutex_isl9241);
 
 /* Charger parameters */
 static const struct charger_info isl9241_charger_info = {
-	.name         = CHARGER_NAME,
-	.voltage_max  = CHARGE_V_MAX,
-	.voltage_min  = CHARGE_V_MIN,
+	.name = CHARGER_NAME,
+	.voltage_max = CHARGE_V_MAX,
+	.voltage_min = CHARGE_V_MIN,
 	.voltage_step = CHARGE_V_STEP,
-	.current_max  = BC_REG_TO_CURRENT(CHARGE_I_MAX),
-	.current_min  = BC_REG_TO_CURRENT(CHARGE_I_MIN),
+	.current_max = BC_REG_TO_CURRENT(CHARGE_I_MAX),
+	.current_min = BC_REG_TO_CURRENT(CHARGE_I_MIN),
 	.current_step = BC_REG_TO_CURRENT(CHARGE_I_STEP),
-	.input_current_max  = AC_REG_TO_CURRENT(INPUT_I_MAX),
-	.input_current_min  = AC_REG_TO_CURRENT(INPUT_I_MIN),
+	.input_current_max = AC_REG_TO_CURRENT(INPUT_I_MAX),
+	.input_current_min = AC_REG_TO_CURRENT(INPUT_I_MIN),
 	.input_current_step = AC_REG_TO_CURRENT(INPUT_I_STEP),
 };
 
 static enum ec_error_list isl9241_discharge_on_ac(int chgnum, int enable);
 static enum ec_error_list isl9241_discharge_on_ac_unsafe(int chgnum,
-						int enable);
+							 int enable);
 static enum ec_error_list isl9241_discharge_on_ac_weak_disable(int chgnum);
 
 static inline enum ec_error_list isl9241_read(int chgnum, int offset,
 					      int *value)
 {
 	int rv = i2c_read16(chg_chips[chgnum].i2c_port,
-			    chg_chips[chgnum].i2c_addr_flags,
-			    offset, value);
+			    chg_chips[chgnum].i2c_addr_flags, offset, value);
 	if (rv)
 		CPRINTS("%s failed (%d)", __func__, rv);
 
@@ -84,8 +83,7 @@ static inline enum ec_error_list isl9241_write(int chgnum, int offset,
 					       int value)
 {
 	int rv = i2c_write16(chg_chips[chgnum].i2c_port,
-			     chg_chips[chgnum].i2c_addr_flags,
-			     offset, value);
+			     chg_chips[chgnum].i2c_addr_flags, offset, value);
 	if (rv)
 		CPRINTS("%s failed (%d)", __func__, rv);
 
@@ -97,8 +95,8 @@ static inline enum ec_error_list isl9241_update(int chgnum, int offset,
 						enum mask_update_action action)
 {
 	int rv = i2c_update16(chg_chips[chgnum].i2c_port,
-			      chg_chips[chgnum].i2c_addr_flags,
-			      offset, mask, action);
+			      chg_chips[chgnum].i2c_addr_flags, offset, mask,
+			      action);
 	if (rv)
 		CPRINTS("%s failed (%d)", __func__, rv);
 
@@ -183,6 +181,19 @@ static const struct charger_info *isl9241_get_info(int chgnum)
 	return &isl9241_charger_info;
 }
 
+static enum ec_error_list isl9241_bypass_mode_enabled(int chgnum, int *enabled)
+{
+	int reg, rv;
+
+	rv = isl9241_read(chgnum, ISL9241_REG_CONTROL0, &reg);
+	if (rv)
+		return rv;
+
+	*enabled = !!(reg & ISL9241_CONTROL0_EN_BYPASS_GATE);
+
+	return EC_SUCCESS;
+}
+
 static enum ec_error_list isl9241_get_status(int chgnum, int *status)
 {
 	int rv;
@@ -207,6 +218,13 @@ static enum ec_error_list isl9241_get_status(int chgnum, int *status)
 	if (reg & ISL9241_INFORMATION2_ACOK_PIN)
 		*status |= CHARGER_AC_PRESENT;
 
+	/* Bypass mode status */
+	rv = isl9241_bypass_mode_enabled(chgnum, &reg);
+	if (rv)
+		return rv;
+	if (reg)
+		*status |= CHARGER_BYPASS_MODE;
+
 	return EC_SUCCESS;
 }
 
@@ -227,15 +245,16 @@ static enum ec_error_list isl9241_set_mode(int chgnum, int mode)
 	 * MinSystemVoltage 0x00h = disables all battery charging
 	 */
 	rv = isl9241_write(chgnum, ISL9241_REG_MIN_SYSTEM_VOLTAGE,
-		mode & CHARGE_FLAG_INHIBIT_CHARGE ?
-		0 : battery_get_info()->voltage_min);
+			   mode & CHARGE_FLAG_INHIBIT_CHARGE ?
+				   0 :
+				   battery_get_info()->voltage_min);
 	if (rv)
 		return rv;
 
 	/* POR reset */
 	if (mode & CHARGE_FLAG_POR_RESET) {
 		rv = isl9241_write(chgnum, ISL9241_REG_CONTROL3,
-			ISL9241_CONTROL3_DIGITAL_RESET);
+				   ISL9241_CONTROL3_DIGITAL_RESET);
 	}
 
 	return rv;
@@ -256,7 +275,7 @@ static enum ec_error_list isl9241_get_current(int chgnum, int *current)
 static enum ec_error_list isl9241_set_current(int chgnum, int current)
 {
 	return isl9241_write(chgnum, ISL9241_REG_CHG_CURRENT_LIMIT,
-				BC_CURRENT_TO_REG(current));
+			     BC_CURRENT_TO_REG(current));
 }
 
 static enum ec_error_list isl9241_get_voltage(int chgnum, int *voltage)
@@ -317,6 +336,38 @@ error:
 	return rv;
 }
 
+static enum ec_error_list isl9241_get_vsys_voltage(int chgnum, int port,
+						   int *voltage)
+{
+	int val = 0;
+	int rv;
+
+	rv = isl9241_update(chgnum, ISL9241_REG_CONTROL3,
+			    ISL9241_CONTROL3_ENABLE_ADC, MASK_SET);
+	if (rv) {
+		CPRINTS("Could not enable ADC for Vsys. (rv=%d)", rv);
+		return rv;
+	}
+
+	usleep(ISL9241_ADC_POLLING_TIME_US);
+
+	/* Read voltage ADC value */
+	rv = isl9241_read(chgnum, ISL9241_REG_VSYS_ADC_RESULTS, &val);
+	if (rv) {
+		CPRINTS("Could not read Vsys. (rv=%d)", rv);
+		isl9241_update(chgnum, ISL9241_REG_CONTROL3,
+			       ISL9241_CONTROL3_ENABLE_ADC, MASK_CLR);
+		return rv;
+	}
+
+	/* Adjust adc_val. Same as Vin. */
+	val >>= ISL9241_VIN_ADC_BIT_OFFSET;
+	val *= ISL9241_VIN_ADC_STEP_MV;
+	*voltage = val;
+
+	return EC_SUCCESS;
+}
+
 static enum ec_error_list isl9241_post_init(int chgnum)
 {
 	return EC_SUCCESS;
@@ -326,12 +377,11 @@ static enum ec_error_list isl9241_post_init(int chgnum)
  * Writes to ISL9241_REG_CONTROL1, unsafe as it does not lock
  * control1_mutex_isl9241.
  */
-static enum ec_error_list isl9241_discharge_on_ac_unsafe(int chgnum,
-						int enable)
+static enum ec_error_list isl9241_discharge_on_ac_unsafe(int chgnum, int enable)
 {
 	int rv = isl9241_update(chgnum, ISL9241_REG_CONTROL1,
-			    ISL9241_CONTROL1_LEARN_MODE,
-			    (enable) ? MASK_SET : MASK_CLR);
+				ISL9241_CONTROL1_LEARN_MODE,
+				(enable) ? MASK_SET : MASK_CLR);
 	if (!rv)
 		learn_mode = enable;
 
@@ -417,7 +467,7 @@ static bool isl9241_is_ac_present(int chgnum)
 	if (rv == EC_SUCCESS)
 		ac_is_present = !!(reg & ISL9241_INFORMATION2_ACOK_PIN);
 
-	return  ac_is_present;
+	return ac_is_present;
 }
 
 /*
@@ -448,26 +498,33 @@ static enum ec_error_list isl9241_bypass_to_bat(int chgnum)
 {
 	const struct battery_info *bi = battery_get_info();
 
+	CPRINTS("bypass -> bat");
+
 	/* 1: Disable force forward buck/reverse boost. */
 	isl9241_update(chgnum, ISL9241_REG_CONTROL4,
 		       ISL9241_CONTROL4_FORCE_BUCK_MODE, MASK_CLR);
+
 	/*
 	 * 2: Turn off BYPSG, turn on NGATE, disable charge pump 100%, disable
 	 *    Vin<Vout comparator.
 	 */
 	isl9241_write(chgnum, ISL9241_REG_CONTROL0, 0);
+
 	/* 3: Set MaxSysVoltage to full charge. */
 	isl9241_write(chgnum, ISL9241_REG_MAX_SYSTEM_VOLTAGE, bi->voltage_max);
+
 	/* 4: Disable ADC. */
 	isl9241_update(chgnum, ISL9241_REG_CONTROL3,
 		       ISL9241_CONTROL3_ENABLE_ADC, MASK_CLR);
+
 	/* 5: Set BGATE to normal operation. */
-	isl9241_update(chgnum, ISL9241_REG_CONTROL1,
-		       ISL9241_CONTROL1_BGATE_OFF, MASK_CLR);
+	isl9241_update(chgnum, ISL9241_REG_CONTROL1, ISL9241_CONTROL1_BGATE_OFF,
+		       MASK_CLR);
+
 	/* 6: Set ACOK reference to normal value. TODO: Revisit. */
 	isl9241_write(chgnum, ISL9241_REG_ACOK_REFERENCE,
 		      ISL9241_MV_TO_ACOK_REFERENCE(
-				      ISL9241_ACOK_REF_LOW_VOLTAGE_ADAPTER_MV));
+			      ISL9241_ACOK_REF_LOW_VOLTAGE_ADAPTER_MV));
 
 	return EC_SUCCESS;
 }
@@ -477,6 +534,8 @@ static enum ec_error_list isl9241_bypass_to_bat(int chgnum)
  */
 static enum ec_error_list isl9241_bypass_chrg_to_bat(int chgnum)
 {
+	CPRINTS("bypass_chrg -> bat");
+
 	/* 1: Disable force forward buck/reverse boost. */
 	isl9241_update(chgnum, ISL9241_REG_CONTROL4,
 		       ISL9241_CONTROL4_FORCE_BUCK_MODE, MASK_CLR);
@@ -493,8 +552,8 @@ static enum ec_error_list isl9241_bypass_chrg_to_bat(int chgnum)
 	isl9241_update(chgnum, ISL9241_REG_CONTROL3,
 		       ISL9241_CONTROL3_ENABLE_ADC, MASK_CLR);
 	/* 6: Set BGATE to normal operation. */
-	isl9241_update(chgnum, ISL9241_REG_CONTROL1,
-		       ISL9241_CONTROL1_BGATE_OFF, MASK_CLR);
+	isl9241_update(chgnum, ISL9241_REG_CONTROL1, ISL9241_CONTROL1_BGATE_OFF,
+		       MASK_CLR);
 	/* 7: Set ACOK reference to normal value. TODO: Revisit. */
 	isl9241_write(chgnum, ISL9241_REG_ACOK_REFERENCE,
 		      ISL9241_MV_TO_ACOK_REFERENCE(3600));
@@ -509,6 +568,8 @@ static enum ec_error_list isl9241_nvdc_chrg_to_nvdc(int chgnum)
 {
 	enum ec_error_list rv;
 
+	CPRINTS("nvdc_chrg -> nvdc");
+
 	/* L: If we're in NVDC+Chg, first transition to NVDC. */
 	/* 1: Disable fast charge. */
 	rv = isl9241_set_current(chgnum, 0);
@@ -530,52 +591,82 @@ static enum ec_error_list isl9241_enable_bypass_mode(int chgnum, bool enable);
  */
 static enum ec_error_list isl9241_nvdc_to_bypass(int chgnum)
 {
-	int voltage;
+	const struct battery_info *bi = battery_get_info();
+	const int charge_current = charge_manager_get_charger_current();
+	const int charge_voltage = charge_manager_get_charger_voltage();
+	int vsys, vsys_target;
+	timestamp_t deadline;
+
+	CPRINTS("nvdc -> bypass");
 
 	/* 1: Set adapter current limit. */
-	isl9241_set_input_current_limit(
-			chgnum, charge_manager_get_charger_current());
+	isl9241_set_input_current_limit(chgnum, charge_current);
+
 	/* 2: Set charge pumps to 100%. */
 	isl9241_update(chgnum, ISL9241_REG_CONTROL0,
 		       ISL9241_CONTROL0_EN_CHARGE_PUMPS, MASK_SET);
+
 	/* 3: Enable ADC. */
 	isl9241_update(chgnum, ISL9241_REG_CONTROL3,
 		       ISL9241_CONTROL3_ENABLE_ADC, MASK_SET);
+
 	/* 4: Turn on Vin/Vout comparator. */
 	isl9241_update(chgnum, ISL9241_REG_CONTROL0,
 		       ISL9241_CONTROL0_EN_VIN_VOUT_COMP, MASK_SET);
-	/* 5: Set ACOK reference higher than battery full voltage.
+
+	/* 5: Set ACOK reference higher than battery full voltage. */
 	isl9241_write(chgnum, ISL9241_REG_ACOK_REFERENCE,
-		      ISL9241_MV_TO_ACOK_REFERENCE(
-				      battery_full_voltage_mv + 800));
-	*/
+		      ISL9241_MV_TO_ACOK_REFERENCE(bi->voltage_max + 800));
+
 	/* 6*: Reduce system load below ACLIM. */
 	/* 7: Turn off BGATE */
-	isl9241_update(chgnum, ISL9241_REG_CONTROL1,
-		       ISL9241_CONTROL1_BGATE_OFF, MASK_SET);
+	isl9241_update(chgnum, ISL9241_REG_CONTROL1, ISL9241_CONTROL1_BGATE_OFF,
+		       MASK_SET);
+
 	/* 8*: Set MaxSysVoltage to VADP. */
-	isl9241_get_vbus_voltage(chgnum, 0, &voltage);
-	isl9241_write(chgnum, ISL9241_REG_MAX_SYSTEM_VOLTAGE, voltage - 256);
+	vsys_target = MIN(charge_voltage - 256, CHARGE_V_MAX);
+	isl9241_write(chgnum, ISL9241_REG_MAX_SYSTEM_VOLTAGE, vsys_target);
+
 	/* 9*: Wait until VSYS == MaxSysVoltage. */
+	deadline.val = get_time().val + ISL9241_BYPASS_VSYS_TIMEOUT_MS * MSEC;
+	do {
+		msleep(ISL9241_BYPASS_VSYS_TIMEOUT_MS / 10);
+		if (isl9241_get_vsys_voltage(chgnum, 0, &vsys)) {
+			CPRINTS("Aborting bypass mode. Vsys is unknown.");
+			return EC_ERROR_UNKNOWN;
+		}
+		if (timestamp_expired(deadline, NULL)) {
+			CPRINTS("Aborting bypass mode. Vsys too low (%d < %d)",
+				vsys, vsys_target);
+			return EC_ERROR_TIMEOUT;
+		}
+	} while (vsys < vsys_target - 256);
+
 	/* 10*: Turn on Bypass gate */
 	isl9241_update(chgnum, ISL9241_REG_CONTROL0,
 		       ISL9241_CONTROL0_EN_BYPASS_GATE, MASK_SET);
+
 	/* 11: Wait 1 ms. */
 	msleep(1);
+
 	/* 12*: Turn off NGATE. */
-	isl9241_update(chgnum, ISL9241_REG_CONTROL0,
-		       ISL9241_CONTROL0_NGATE_OFF, MASK_SET);
+	isl9241_update(chgnum, ISL9241_REG_CONTROL0, ISL9241_CONTROL0_NGATE_OFF,
+		       MASK_SET);
+
 	/* 14*: Stop switching. */
 	isl9241_write(chgnum, ISL9241_REG_MAX_SYSTEM_VOLTAGE, 0);
+
 	/* 15: Set BGATE to normal operation. */
-	isl9241_update(chgnum, ISL9241_REG_CONTROL1,
-		       ISL9241_CONTROL1_BGATE_OFF, MASK_CLR);
-	/*
-	 * Suggestion-1: If ACOK goes low before step A16, stop here
-	 * then execute the steps for Bypass to BAT to abort.
-	 */
+	isl9241_update(chgnum, ISL9241_REG_CONTROL1, ISL9241_CONTROL1_BGATE_OFF,
+		       MASK_CLR);
+
 	if (!isl9241_is_ac_present(chgnum))
-		return isl9241_enable_bypass_mode(chgnum, false);
+		/*
+		 * Suggestion: If ACOK goes low before step A16, stop
+		 * executing commands and complete steps for Bypass to BAT.
+		 */
+		return EC_ERROR_PARAM1;
+
 	/* 16: Enable 10 mA discharge on CSOP. */
 	/* 17: Read diode emulation active bit. */
 	/* 18: Disable 10mA discharge on CSOP. */
@@ -583,12 +674,12 @@ static enum ec_error_list isl9241_nvdc_to_bypass(int chgnum)
 	isl9241_update(chgnum, ISL9241_REG_CONTROL4,
 		       ISL9241_CONTROL4_FORCE_BUCK_MODE, MASK_SET);
 
-	/*
-	 * Suggestion-2 and 3: If AC is removed on or after A16,
-	 * complete all steps then execute Bypass to BAT to revert.
-	 */
 	if (!isl9241_is_ac_present(chgnum))
-		return isl9241_enable_bypass_mode(chgnum, false);
+		/*
+		 * Suggestion: If AC is removed on or after A16, complete all
+		 * 19 steps then execute Bypass to BAT.
+		 */
+		return EC_ERROR_PARAM2;
 
 	return EC_SUCCESS;
 }
@@ -598,12 +689,24 @@ static enum ec_error_list isl9241_nvdc_to_bypass(int chgnum)
  */
 static enum ec_error_list isl9241_bypass_chrg_to_bypass(int chgnum)
 {
+	int rv;
+
+	CPRINTS("bypass_chrg -> bypass");
+
 	/* 1: Stop switching. */
-	isl9241_write(chgnum, ISL9241_REG_MAX_SYSTEM_VOLTAGE, 0);
+	rv = isl9241_write(chgnum, ISL9241_REG_MAX_SYSTEM_VOLTAGE, 0);
+	if (rv)
+		return rv;
+
 	/* 2: Disable fast charge. */
-	isl9241_write(chgnum, ISL9241_REG_CHG_CURRENT_LIMIT, 0);
+	rv = isl9241_write(chgnum, ISL9241_REG_CHG_CURRENT_LIMIT, 0);
+	if (rv)
+		return rv;
+
 	/* 3: Disable trickle charge. */
-	isl9241_write(chgnum, ISL9241_REG_MIN_SYSTEM_VOLTAGE, 0);
+	rv = isl9241_write(chgnum, ISL9241_REG_MIN_SYSTEM_VOLTAGE, 0);
+	if (rv)
+		return rv;
 
 	return EC_SUCCESS;
 }
@@ -615,26 +718,44 @@ static enum ec_error_list isl9241_bypass_to_nvdc(int chgnum)
 {
 	const struct battery_info *bi = battery_get_info();
 	int voltage;
+	int rv;
+
+	CPRINTS("bypass -> nvdc");
 
 	/* 1*: Reduce system load below ACLIM. */
 	/* 3*: Disable force forward buck/reverse boost. */
-	isl9241_update(chgnum, ISL9241_REG_CONTROL4,
-		       ISL9241_CONTROL4_FORCE_BUCK_MODE, MASK_CLR);
+	rv = isl9241_update(chgnum, ISL9241_REG_CONTROL4,
+			    ISL9241_CONTROL4_FORCE_BUCK_MODE, MASK_CLR);
+	if (rv)
+		return rv;
+
 	/* 6*: Set MaxSysVoltage to VADP. */
-	isl9241_get_vbus_voltage(chgnum, 0, &voltage);
-	isl9241_write(chgnum, ISL9241_REG_MAX_SYSTEM_VOLTAGE, voltage - 256);
+	rv = isl9241_get_vbus_voltage(chgnum, 0, &voltage);
+	if (rv)
+		return rv;
+	rv = isl9241_write(chgnum, ISL9241_REG_MAX_SYSTEM_VOLTAGE,
+			   voltage - 256);
+	if (rv)
+		return rv;
+
 	/* 7*: Wait until VSYS == MaxSysVoltage. */
 	msleep(1);
+
 	/* 8*: Turn on NGATE. */
-	isl9241_update(chgnum, ISL9241_REG_CONTROL0,
-		       ISL9241_CONTROL0_NGATE_OFF, MASK_CLR);
+	rv = isl9241_update(chgnum, ISL9241_REG_CONTROL0,
+			    ISL9241_CONTROL0_NGATE_OFF, MASK_CLR);
+	if (rv)
+		return rv;
+
 	/* 10*: Turn off Bypass gate */
-	isl9241_update(chgnum, ISL9241_REG_CONTROL0,
-		       ISL9241_CONTROL0_EN_BYPASS_GATE, MASK_CLR);
-	/* 12*: Set MaxSysVoltage to full charge. */
-	isl9241_write(chgnum, ISL9241_REG_MAX_SYSTEM_VOLTAGE, bi->voltage_max);
+	rv = isl9241_update(chgnum, ISL9241_REG_CONTROL0,
+			    ISL9241_CONTROL0_EN_BYPASS_GATE, MASK_CLR);
+	if (rv)
+		return rv;
 
-	return EC_SUCCESS;
+	/* 12*: Set MaxSysVoltage to full charge. */
+	return isl9241_write(chgnum, ISL9241_REG_MAX_SYSTEM_VOLTAGE,
+			     bi->voltage_max);
 }
 
 static enum ec_error_list isl9241_enable_bypass_mode(int chgnum, bool enable)
@@ -646,37 +767,48 @@ static enum ec_error_list isl9241_enable_bypass_mode(int chgnum, bool enable)
 		if (isl9241_is_in_chrg(chgnum)) {
 			/* (Optional) L (then A) */
 			rv = isl9241_nvdc_chrg_to_nvdc(chgnum);
-			CPRINTS("%s nvdc_chrg -> nvdc",
-				rv ? "Failed" : "Succeeded");
+			if (rv)
+				CPRINTS("nvdc_chrg -> nvdc failed(%d)", rv);
 		}
 		/* A */
 		rv = isl9241_nvdc_to_bypass(chgnum);
-		CPRINTS("%s nvdc -> bypass", rv ? "Failed" : "Succeeded");
+		if (rv == EC_ERROR_PARAM1 || rv == EC_ERROR_PARAM2) {
+			CPRINTS("AC removed (%d) in nvdc -> bypass mode", rv);
+			return isl9241_bypass_to_bat(chgnum);
+		} else if (rv) {
+			CPRINTS("Failed to enable bypass mode(%d)", rv);
+			return isl9241_bypass_to_nvdc(chgnum);
+		}
 		return rv;
-	} else if (isl9241_is_ac_present(chgnum)) {
-		/* Switch to NVDC (e.g. BJ -> Type-C) */
+	}
+
+	/* Disable */
+	if (isl9241_is_ac_present(chgnum)) {
+		/* Switch to another AC (e.g. BJ -> Type-C) */
 		if (isl9241_is_in_chrg(chgnum)) {
 			/* J (then B) */
 			rv = isl9241_bypass_chrg_to_bypass(chgnum);
-			CPRINTS("%s bypass_chrg -> bypass",
-				rv ? "Failed" : "Succeeded");
+			if (rv)
+				CPRINTS("bypass_chrg -> bypass failed(%d)", rv);
 		}
 		/* B */
 		rv = isl9241_bypass_to_nvdc(chgnum);
-		CPRINTS("%s bypass -> nvdc", rv ? "Failed" : "Succeeded");
+		if (rv)
+			CPRINTS("bypass -> nvdc failed(%d)", rv);
 		return rv;
 	} else {
 		/* AC removal */
 		if (isl9241_is_in_chrg(chgnum)) {
 			/* M */
 			rv = isl9241_bypass_chrg_to_bat(chgnum);
-			CPRINTS("%s bypass_chrg -> bat",
-				rv ? "Failed" : "Succeeded");
-			return rv;
+			if (rv)
+				CPRINTS("bypass_chrg -> bat failed(%d)", rv);
+		} else {
+			/* M' */
+			rv = isl9241_bypass_to_bat(chgnum);
+			if (rv)
+				CPRINTS("bypass -> bat failed(%d)", rv);
 		}
-		/* M */
-		rv = isl9241_bypass_to_bat(chgnum);
-		CPRINTS("%s bypass -> bat", rv ? "Failed" : "Succeeded");
 		return rv;
 	}
 
@@ -714,11 +846,11 @@ static void isl9241_init(int chgnum)
 	 * [15:13]: Trickle Charging Current (battery pre-charge current)
 	 * [10:9] : Prochot# Debounce time (1000us)
 	 */
-	if (isl9241_update(chgnum, ISL9241_REG_CONTROL2,
-			   (ISL9241_CONTROL2_TRICKLE_CHG_CURR(
-				bi->precharge_current) |
-			    ISL9241_CONTROL2_PROCHOT_DEBOUNCE_1000),
-			   MASK_SET))
+	if (isl9241_update(
+		    chgnum, ISL9241_REG_CONTROL2,
+		    (ISL9241_CONTROL2_TRICKLE_CHG_CURR(bi->precharge_current) |
+		     ISL9241_CONTROL2_PROCHOT_DEBOUNCE_1000),
+		    MASK_SET))
 		goto init_fail;
 
 	/*
@@ -726,8 +858,7 @@ static void isl9241_init(int chgnum)
 	 * [14]: ACLIM Reload (Do not reload)
 	 */
 	if (isl9241_update(chgnum, ISL9241_REG_CONTROL3,
-			   ISL9241_CONTROL3_ACLIM_RELOAD,
-			   MASK_SET))
+			   ISL9241_CONTROL3_ACLIM_RELOAD, MASK_SET))
 		goto init_fail;
 
 	/*
@@ -735,14 +866,12 @@ static void isl9241_init(int chgnum)
 	 * [13]: Slew rate control enable (sets VSYS ramp to 8mV/us)
 	 */
 	if (isl9241_update(chgnum, ISL9241_REG_CONTROL4,
-			   ISL9241_CONTROL4_SLEW_RATE_CTRL,
-			   MASK_SET))
+			   ISL9241_CONTROL4_SLEW_RATE_CTRL, MASK_SET))
 		goto init_fail;
 
 #ifndef CONFIG_CHARGE_RAMP_HW
 	if (isl9241_update(chgnum, ISL9241_REG_CONTROL0,
-			   ISL9241_CONTROL0_INPUT_VTG_REGULATION,
-			   MASK_SET))
+			   ISL9241_CONTROL0_INPUT_VTG_REGULATION, MASK_SET))
 		goto init_fail;
 #endif
 
@@ -751,7 +880,7 @@ static void isl9241_init(int chgnum)
 		goto init_fail;
 	ctl_val &= ~ISL9241_CONTROL1_SWITCHING_FREQ_MASK;
 	ctl_val |= ((CONFIG_ISL9241_SWITCHING_FREQ << 7) &
-		     ISL9241_CONTROL1_SWITCHING_FREQ_MASK);
+		    ISL9241_CONTROL1_SWITCHING_FREQ_MASK);
 	if (isl9241_write(chgnum, ISL9241_REG_CONTROL1, ctl_val))
 		goto init_fail;
 #endif
@@ -823,22 +952,19 @@ static int isl9241_ramp_get_current_limit(int chgnum)
  */
 static void isl9241_restart_charge_voltage_when_full(void)
 {
-	if (!chipset_in_or_transitioning_to_state(CHIPSET_STATE_ON)
-	    && charge_get_state() == PWR_STATE_CHARGE_NEAR_FULL
-	    && battery_get_disconnect_state() == BATTERY_NOT_DISCONNECTED) {
+	if (!chipset_in_or_transitioning_to_state(CHIPSET_STATE_ON) &&
+	    charge_get_state() == PWR_STATE_CHARGE_NEAR_FULL &&
+	    battery_get_disconnect_state() == BATTERY_NOT_DISCONNECTED) {
 		charger_discharge_on_ac(1);
 		msleep(50);
 		charger_discharge_on_ac(0);
 	}
 }
-DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE,
-	     isl9241_restart_charge_voltage_when_full,
+DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, isl9241_restart_charge_voltage_when_full,
 	     HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND,
-	     isl9241_restart_charge_voltage_when_full,
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, isl9241_restart_charge_voltage_when_full,
 	     HOOK_PRIO_DEFAULT);
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN,
-	     isl9241_restart_charge_voltage_when_full,
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, isl9241_restart_charge_voltage_when_full,
 	     HOOK_PRIO_DEFAULT);
 
 /*****************************************************************************/
@@ -884,6 +1010,7 @@ const struct charger_drv isl9241_drv = {
 	.set_voltage = &isl9241_set_voltage,
 	.discharge_on_ac = &isl9241_discharge_on_ac,
 	.get_vbus_voltage = &isl9241_get_vbus_voltage,
+	.get_vsys_voltage = &isl9241_get_vsys_voltage,
 	.set_input_current_limit = &isl9241_set_input_current_limit,
 	.get_input_current_limit = &isl9241_get_input_current_limit,
 	.manufacturer_id = &isl9241_manufacturer_id,
diff --git a/driver/charger/isl9241.h b/driver/charger/isl9241.h
index f6f7844ef5..e1b4d18b14 100644
--- a/driver/charger/isl9241.h
+++ b/driver/charger/isl9241.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,21 +10,21 @@
 
 #include "driver/charger/isl9241_public.h"
 
-#define CHARGER_NAME	"ISL9241"
-#define CHARGE_V_MAX	18304
-#define CHARGE_V_MIN	64
-#define CHARGE_V_STEP	8
+#define CHARGER_NAME "ISL9241"
+#define CHARGE_V_MAX 18304
+#define CHARGE_V_MIN 64
+#define CHARGE_V_STEP 8
 /*
  * When the default sense resistor value is used, register values
  * represent mA. For other sense resistors values, register
  * values must be scaled accordingly to convert to mA.
  */
-#define CHARGE_I_MAX	6140
-#define CHARGE_I_MIN	4
-#define CHARGE_I_STEP	4
-#define INPUT_I_MAX	6140
-#define INPUT_I_MIN	4
-#define	INPUT_I_STEP	4
+#define CHARGE_I_MAX 6140
+#define CHARGE_I_MIN 4
+#define CHARGE_I_STEP 4
+#define INPUT_I_MAX 6140
+#define INPUT_I_MIN 4
+#define INPUT_I_STEP 4
 
 /* Registers */
 
@@ -32,30 +32,30 @@
  * ChargeCurrentLimit [12:2] 11-bit (0x0000h = disables fast charging,
  * trickle charging is allowed)
  */
-#define ISL9241_REG_CHG_CURRENT_LIMIT	0x14
+#define ISL9241_REG_CHG_CURRENT_LIMIT 0x14
 
 /* MaxSystemVoltage [14:3] 12-bit, (0x0000h = disables switching) */
-#define ISL9241_REG_MAX_SYSTEM_VOLTAGE	0x15
+#define ISL9241_REG_MAX_SYSTEM_VOLTAGE 0x15
 
-#define ISL9241_REG_CONTROL7		0x38
+#define ISL9241_REG_CONTROL7 0x38
 
 /* Configures various charger options */
-#define ISL9241_REG_CONTROL0		0x39
+#define ISL9241_REG_CONTROL0 0x39
 /* 2: Input Voltage Regulation (0 = Enable (default), 1 = Disable) */
-#define ISL9241_CONTROL0_INPUT_VTG_REGULATION	BIT(2)
-#define ISL9241_CONTROL0_EN_VIN_VOUT_COMP	BIT(5)
-#define ISL9241_CONTROL0_EN_CHARGE_PUMPS	BIT(6)
-#define ISL9241_CONTROL0_EN_BYPASS_GATE		BIT(11)
-#define ISL9241_CONTROL0_NGATE_OFF		BIT(12)
+#define ISL9241_CONTROL0_INPUT_VTG_REGULATION BIT(2)
+#define ISL9241_CONTROL0_EN_VIN_VOUT_COMP BIT(5)
+#define ISL9241_CONTROL0_EN_CHARGE_PUMPS BIT(6)
+#define ISL9241_CONTROL0_EN_BYPASS_GATE BIT(11)
+#define ISL9241_CONTROL0_NGATE_OFF BIT(12)
 
-#define ISL9241_REG_INFORMATION1	0x3A
-#define ISL9241_REG_ADAPTER_CUR_LIMIT2	0x3B
+#define ISL9241_REG_INFORMATION1 0x3A
+#define ISL9241_REG_ADAPTER_CUR_LIMIT2 0x3B
 
 /* Configures various charger options */
-#define ISL9241_REG_CONTROL1		0x3C
-#define ISL9241_CONTROL1_PSYS		BIT(3)
-#define ISL9241_CONTROL1_BGATE_OFF	BIT(6)
-#define ISL9241_CONTROL1_LEARN_MODE	BIT(12)
+#define ISL9241_REG_CONTROL1 0x3C
+#define ISL9241_CONTROL1_PSYS BIT(3)
+#define ISL9241_CONTROL1_BGATE_OFF BIT(6)
+#define ISL9241_CONTROL1_LEARN_MODE BIT(12)
 /*
  * 9:7 - Switching Frequency
  */
@@ -63,14 +63,14 @@
 #define ISL9241_CONTROL1_SWITCHING_FREQ_1420KHZ 0
 #define ISL9241_CONTROL1_SWITCHING_FREQ_1180KHZ 1
 #define ISL9241_CONTROL1_SWITCHING_FREQ_1020KHZ 2
-#define ISL9241_CONTROL1_SWITCHING_FREQ_890KHZ  3
-#define ISL9241_CONTROL1_SWITCHING_FREQ_808KHZ  4
-#define ISL9241_CONTROL1_SWITCHING_FREQ_724KHZ  5
-#define ISL9241_CONTROL1_SWITCHING_FREQ_656KHZ  6
-#define ISL9241_CONTROL1_SWITCHING_FREQ_600KHZ  7
+#define ISL9241_CONTROL1_SWITCHING_FREQ_890KHZ 3
+#define ISL9241_CONTROL1_SWITCHING_FREQ_808KHZ 4
+#define ISL9241_CONTROL1_SWITCHING_FREQ_724KHZ 5
+#define ISL9241_CONTROL1_SWITCHING_FREQ_656KHZ 6
+#define ISL9241_CONTROL1_SWITCHING_FREQ_600KHZ 7
 
 /* Configures various charger options */
-#define ISL9241_REG_CONTROL2		0x3D
+#define ISL9241_REG_CONTROL2 0x3D
 /*
  * 15:13 - Trickle Charging Current
  *         <000> 32mA (do not use)
@@ -82,79 +82,87 @@
  *         <110> 224mA
  *         <111> 256mA
  */
-#define ISL9241_CONTROL2_TRICKLE_CHG_CURR(curr)	((((curr) >> 5) - 1) << 13)
+#define ISL9241_CONTROL2_TRICKLE_CHG_CURR(curr) ((((curr) >> 5) - 1) << 13)
 /* 12 - Two-Level Adapter Current Limit */
-#define ISL9241_CONTROL2_TWO_LEVEL_ADP_CURR	BIT(12)
+#define ISL9241_CONTROL2_TWO_LEVEL_ADP_CURR BIT(12)
 /* 10:9 PROCHOT# debounce time in uS */
-#define ISL9241_CONTROL2_PROCHOT_DEBOUNCE_MASK  GENMASK(10, 9)
-#define ISL9241_CONTROL2_PROCHOT_DEBOUNCE_500	(2 << 9)
-#define ISL9241_CONTROL2_PROCHOT_DEBOUNCE_1000	(3 << 9)
+#define ISL9241_CONTROL2_PROCHOT_DEBOUNCE_MASK GENMASK(10, 9)
+#define ISL9241_CONTROL2_PROCHOT_DEBOUNCE_500 (2 << 9)
+#define ISL9241_CONTROL2_PROCHOT_DEBOUNCE_1000 (3 << 9)
 
 /* MinSystemVoltage [13:6] 8-bit (0x0000h = disables all battery charging) */
-#define ISL9241_REG_MIN_SYSTEM_VOLTAGE	0x3E
+#define ISL9241_REG_MIN_SYSTEM_VOLTAGE 0x3E
 
-#define ISL9241_REG_ADAPTER_CUR_LIMIT1	0x3F
-#define ISL9241_REG_ACOK_REFERENCE	0x40
-#define ISL9241_REG_CONTROL6		0x43
-#define ISL9241_REG_AC_PROCHOT		0x47
-#define ISL9241_REG_DC_PROCHOT		0x48
-#define ISL9241_REG_OTG_VOLTAGE		0x49
-#define ISL9241_REG_OTG_CURRENT		0x4A
+#define ISL9241_REG_ADAPTER_CUR_LIMIT1 0x3F
+#define ISL9241_REG_ACOK_REFERENCE 0x40
+#define ISL9241_REG_CONTROL6 0x43
+#define ISL9241_REG_AC_PROCHOT 0x47
+#define ISL9241_REG_DC_PROCHOT 0x48
+#define ISL9241_REG_OTG_VOLTAGE 0x49
+#define ISL9241_REG_OTG_CURRENT 0x4A
 
-#define ISL9241_MV_TO_ACOK_REFERENCE(mv)	(((mv) / 96) << 6)
+#define ISL9241_MV_TO_ACOK_REFERENCE(mv) (((mv) / 96) << 6)
 
 /* VIN Voltage (ADP Min Voltage) (default 4.096V) */
-#define ISL9241_REG_VIN_VOLTAGE		0x4B
+#define ISL9241_REG_VIN_VOLTAGE 0x4B
 
 /* Configures various charger options */
-#define ISL9241_REG_CONTROL3		0x4C
+#define ISL9241_REG_CONTROL3 0x4C
 /* 14: ACLIM Reload (0 - reload, 1 - Do not reload */
-#define ISL9241_CONTROL3_ACLIM_RELOAD	BIT(14)
+#define ISL9241_CONTROL3_ACLIM_RELOAD BIT(14)
 /* 5: Input Current Limit Loop (0 - Enable, 1 - Disable */
-#define ISL9241_CONTROL3_INPUT_CURRENT_LIMIT	BIT(5)
+#define ISL9241_CONTROL3_INPUT_CURRENT_LIMIT BIT(5)
 /* 2: Digital Reset (0 - Idle, 1 - Reset */
-#define ISL9241_CONTROL3_DIGITAL_RESET	BIT(2)
+#define ISL9241_CONTROL3_DIGITAL_RESET BIT(2)
 /* 0: Enable ADC (0 - Active when charging, 1 - Active always) */
-#define ISL9241_CONTROL3_ENABLE_ADC	BIT(0)
+#define ISL9241_CONTROL3_ENABLE_ADC BIT(0)
 
 /* Indicates various charger status */
-#define ISL9241_REG_INFORMATION2	0x4D
+#define ISL9241_REG_INFORMATION2 0x4D
 /* 12: BATGONE pin status (0 = Battery is present, 1 = No battery) */
-#define ISL9241_INFORMATION2_BATGONE_PIN	BIT(12)
+#define ISL9241_INFORMATION2_BATGONE_PIN BIT(12)
 /* 14: ACOK pin status (0 = No adapter, 1 = Adapter is present) */
-#define ISL9241_INFORMATION2_ACOK_PIN		BIT(14)
+#define ISL9241_INFORMATION2_ACOK_PIN BIT(14)
 
-#define ISL9241_REG_CONTROL4		0x4E
-#define ISL9241_CONTROL4_FORCE_BUCK_MODE	BIT(10)
+#define ISL9241_REG_CONTROL4 0x4E
+#define ISL9241_CONTROL4_FORCE_BUCK_MODE BIT(10)
 /* 11: Rsense (Rs1:Rs2) ratio for PSYS (0 - 2:1, 1 - 1:1) */
-#define ISL9241_CONTROL4_PSYS_RSENSE_RATIO  BIT(11)
+#define ISL9241_CONTROL4_PSYS_RSENSE_RATIO BIT(11)
 /* 13: Enable VSYS slew rate control (0 - disable, 1 - enable) */
-#define ISL9241_CONTROL4_SLEW_RATE_CTRL     BIT(13)
+#define ISL9241_CONTROL4_SLEW_RATE_CTRL BIT(13)
 
-#define ISL9241_REG_CONTROL5		0x4F
-#define ISL9241_REG_NTC_ADC_RESULTS	0x80
-#define ISL9241_REG_VBAT_ADC_RESULTS	0x81
-#define ISL9241_REG_TJ_ADC_RESULTS	0x82
+#define ISL9241_REG_CONTROL5 0x4F
+#define ISL9241_REG_NTC_ADC_RESULTS 0x80
+#define ISL9241_REG_VBAT_ADC_RESULTS 0x81
+#define ISL9241_REG_TJ_ADC_RESULTS 0x82
 
 /* ADC result for adapter current measurements, LSB = 22.2mA */
-#define ISL9241_REG_IADP_ADC_RESULTS	0x83
+#define ISL9241_REG_IADP_ADC_RESULTS 0x83
 
-#define ISL9241_REG_DC_ADC_RESULTS	0x84
-#define ISL9241_REG_CC_ADC_RESULTS	0x85
-#define ISL9241_REG_VSYS_ADC_RESULTS	0x86
-#define ISL9241_REG_VIN_ADC_RESULTS	0x87
-#define ISL9241_REG_INFORMATION3	0x90
-#define ISL9241_REG_INFORMATION4	0x91
-#define ISL9241_REG_MANUFACTURER_ID	0xFE
-#define ISL9241_REG_DEVICE_ID		0xFF
+#define ISL9241_REG_DC_ADC_RESULTS 0x84
+#define ISL9241_REG_CC_ADC_RESULTS 0x85
+#define ISL9241_REG_VSYS_ADC_RESULTS 0x86
+#define ISL9241_REG_VIN_ADC_RESULTS 0x87
+#define ISL9241_REG_INFORMATION3 0x90
+#define ISL9241_REG_INFORMATION4 0x91
+#define ISL9241_REG_MANUFACTURER_ID 0xFE
+#define ISL9241_REG_DEVICE_ID 0xFF
 
-#define ISL9241_VIN_ADC_BIT_OFFSET	6
-#define ISL9241_VIN_ADC_STEP_MV		96
+#define ISL9241_VIN_ADC_BIT_OFFSET 6
+#define ISL9241_VIN_ADC_STEP_MV 96
+
+#define ISL9241_ADC_POLLING_TIME_US 400
 
 /*
  * Used to reset ACOKref register to normal value to detect low voltage (5V or
  * 9V) adapter during next plug in event
  */
-#define ISL9241_ACOK_REF_LOW_VOLTAGE_ADAPTER_MV	3600
+#define ISL9241_ACOK_REF_LOW_VOLTAGE_ADAPTER_MV 3600
+
+/*
+ * Max wait time for Vsys to be close to Vin (Vadp) before turning on the bypass
+ * gate. See 2.5.1 of application notes for details.
+ */
+#define ISL9241_BYPASS_VSYS_TIMEOUT_MS 500
 
 #endif /* __CROS_EC_ISL9241_H */
diff --git a/driver/charger/rt946x.c b/driver/charger/rt946x.c
index 1f932b87f5..acf5dc012d 100644
--- a/driver/charger/rt946x.c
+++ b/driver/charger/rt946x.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -27,34 +27,34 @@
 #include "util.h"
 
 /* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
 #define CPRINTS(format, args...) \
-	cprints(CC_CHARGER, "%s " format, "RT946X", ## args)
+	cprints(CC_CHARGER, "%s " format, "RT946X", ##args)
 
 /* Charger parameters */
-#define CHARGER_NAME    RT946X_CHARGER_NAME
-#define CHARGE_V_MAX    4710
-#define CHARGE_V_MIN    3900
-#define CHARGE_V_STEP   10
-#define CHARGE_I_MAX    5000
-#define CHARGE_I_MIN    100
-#define CHARGE_I_OFF    0
-#define CHARGE_I_STEP   100
-#define INPUT_I_MAX     3250
-#define INPUT_I_MIN     100
-#define INPUT_I_STEP    50
+#define CHARGER_NAME RT946X_CHARGER_NAME
+#define CHARGE_V_MAX 4710
+#define CHARGE_V_MIN 3900
+#define CHARGE_V_STEP 10
+#define CHARGE_I_MAX 5000
+#define CHARGE_I_MIN 100
+#define CHARGE_I_OFF 0
+#define CHARGE_I_STEP 100
+#define INPUT_I_MAX 3250
+#define INPUT_I_MIN 100
+#define INPUT_I_STEP 50
 
 /* Charger parameters */
 static const struct charger_info rt946x_charger_info = {
-	.name         = CHARGER_NAME,
-	.voltage_max  = CHARGE_V_MAX,
-	.voltage_min  = CHARGE_V_MIN,
+	.name = CHARGER_NAME,
+	.voltage_max = CHARGE_V_MAX,
+	.voltage_min = CHARGE_V_MIN,
 	.voltage_step = CHARGE_V_STEP,
-	.current_max  = CHARGE_I_MAX,
-	.current_min  = CHARGE_I_MIN,
+	.current_max = CHARGE_I_MAX,
+	.current_min = CHARGE_I_MIN,
 	.current_step = CHARGE_I_STEP,
-	.input_current_max  = INPUT_I_MAX,
-	.input_current_min  = INPUT_I_MIN,
+	.input_current_max = INPUT_I_MAX,
+	.input_current_min = INPUT_I_MIN,
 	.input_current_step = INPUT_I_STEP,
 };
 
@@ -67,8 +67,8 @@ static const struct rt946x_init_setting default_init_setting = {
 	.boost_current = 1500,
 };
 
-__attribute__((weak))
-const struct rt946x_init_setting *board_rt946x_init_setting(void)
+__attribute__((weak)) const struct rt946x_init_setting *
+board_rt946x_init_setting(void)
 {
 	return &default_init_setting;
 }
@@ -135,11 +135,17 @@ static const unsigned char mt6370_reg_en_hidden_mode[] = {
 };
 
 static const unsigned char mt6370_val_en_hidden_mode[] = {
-	0x96, 0x69, 0xC3, 0x3C,
+	0x96,
+	0x69,
+	0xC3,
+	0x3C,
 };
 
 static const unsigned char mt6370_val_en_test_mode[] = {
-	0x69, 0x96, 0x63, 0x70,
+	0x69,
+	0x96,
+	0x63,
+	0x70,
 };
 #endif /* CONFIG_CHARGER_MT6370 */
 
@@ -192,17 +198,13 @@ enum rt946x_irq {
 };
 
 static uint8_t rt946x_irqmask[RT946X_IRQ_COUNT] = {
-	0xBF, 0xFF, 0xFF, 0xFF, 0xFF,
-	0xFF, 0xFC, 0xFF, 0xFF, 0xFF,
-	0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-	0xFF,
+	0xBF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
 };
 
 static const uint8_t rt946x_irq_maskall[RT946X_IRQ_COUNT] = {
-	0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-	0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-	0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-	0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
 };
 #endif
 
@@ -233,8 +235,7 @@ static enum ec_error_list rt946x_block_write(int chgnum, int reg,
 					     const uint8_t *val, int len)
 {
 	return i2c_write_block(chg_chips[chgnum].i2c_port,
-			       chg_chips[chgnum].i2c_addr_flags,
-			       reg, val, len);
+			       chg_chips[chgnum].i2c_addr_flags, reg, val, len);
 }
 
 static int rt946x_update_bits(int chgnum, int reg, int mask, int val)
@@ -309,13 +310,13 @@ static int mt6370_enable_hidden_mode(int chgnum, int en)
 	if (in_interrupt_context()) {
 		CPRINTS("Err: use hidden mode in IRQ");
 		return EC_ERROR_INVAL;
-        }
+	}
 
 	mutex_lock(&hidden_mode_lock);
 	if (en) {
 		if (hidden_mode_cnt == 0) {
-			rv = rt946x_block_write(chgnum,
-				mt6370_reg_en_hidden_mode[0],
+			rv = rt946x_block_write(
+				chgnum, mt6370_reg_en_hidden_mode[0],
 				mt6370_val_en_hidden_mode,
 				ARRAY_SIZE(mt6370_val_en_hidden_mode));
 			if (rv)
@@ -386,15 +387,15 @@ static int mt6370_ichg_workaround(int chgnum, int new_ichg)
 
 static inline int rt946x_enable_wdt(int chgnum, int en)
 {
-	return (en ? rt946x_set_bit : rt946x_clr_bit)
-		(chgnum, RT946X_REG_CHGCTRL13, RT946X_MASK_WDT_EN);
+	return (en ? rt946x_set_bit : rt946x_clr_bit)(
+		chgnum, RT946X_REG_CHGCTRL13, RT946X_MASK_WDT_EN);
 }
 
 /* Enable high-impedance mode */
 static inline int rt946x_enable_hz(int chgnum, int en)
 {
-	return (en ? rt946x_set_bit : rt946x_clr_bit)
-		(chgnum, RT946X_REG_CHGCTRL1, RT946X_MASK_HZ_EN);
+	return (en ? rt946x_set_bit : rt946x_clr_bit)(
+		chgnum, RT946X_REG_CHGCTRL1, RT946X_MASK_HZ_EN);
 }
 
 int rt946x_por_reset(void)
@@ -470,7 +471,7 @@ static int rt946x_set_ieoc(int chgnum, unsigned int ieoc)
 	CPRINTS("ieoc=%d", ieoc);
 
 	return rt946x_update_bits(chgnum, RT946X_REG_CHGCTRL9, RT946X_MASK_IEOC,
-				reg_ieoc << RT946X_SHIFT_IEOC);
+				  reg_ieoc << RT946X_SHIFT_IEOC);
 }
 
 static int rt946x_set_mivr(int chgnum, unsigned int mivr)
@@ -478,12 +479,12 @@ static int rt946x_set_mivr(int chgnum, unsigned int mivr)
 	uint8_t reg_mivr = 0;
 
 	reg_mivr = rt946x_closest_reg(RT946X_MIVR_MIN, RT946X_MIVR_MAX,
-		RT946X_MIVR_STEP, mivr);
+				      RT946X_MIVR_STEP, mivr);
 
 	CPRINTS("mivr=%d", mivr);
 
 	return rt946x_update_bits(chgnum, RT946X_REG_CHGCTRL6, RT946X_MASK_MIVR,
-		reg_mivr << RT946X_SHIFT_MIVR);
+				  reg_mivr << RT946X_SHIFT_MIVR);
 }
 
 static int rt946x_set_boost_voltage(int chgnum, unsigned int voltage)
@@ -491,13 +492,14 @@ static int rt946x_set_boost_voltage(int chgnum, unsigned int voltage)
 	uint8_t reg_voltage = 0;
 
 	reg_voltage = rt946x_closest_reg(RT946X_BOOST_VOLTAGE_MIN,
-		RT946X_BOOST_VOLTAGE_MAX, RT946X_BOOST_VOLTAGE_STEP, voltage);
+					 RT946X_BOOST_VOLTAGE_MAX,
+					 RT946X_BOOST_VOLTAGE_STEP, voltage);
 
 	CPRINTS("voltage=%d", voltage);
 
 	return rt946x_update_bits(chgnum, RT946X_REG_CHGCTRL5,
-		RT946X_MASK_BOOST_VOLTAGE,
-		reg_voltage << RT946X_SHIFT_BOOST_VOLTAGE);
+				  RT946X_MASK_BOOST_VOLTAGE,
+				  reg_voltage << RT946X_SHIFT_BOOST_VOLTAGE);
 }
 
 static int rt946x_set_boost_current(int chgnum, unsigned int current)
@@ -517,8 +519,8 @@ static int rt946x_set_boost_current(int chgnum, unsigned int current)
 	CPRINTS("current=%d", current);
 
 	return rt946x_update_bits(chgnum, RT946X_REG_CHGCTRL10,
-		RT946X_MASK_BOOST_CURRENT,
-		i << RT946X_SHIFT_BOOST_CURRENT);
+				  RT946X_MASK_BOOST_CURRENT,
+				  i << RT946X_SHIFT_BOOST_CURRENT);
 }
 
 static int rt946x_set_ircmp_vclamp(int chgnum, unsigned int vclamp)
@@ -526,13 +528,14 @@ static int rt946x_set_ircmp_vclamp(int chgnum, unsigned int vclamp)
 	uint8_t reg_vclamp = 0;
 
 	reg_vclamp = rt946x_closest_reg(RT946X_IRCMP_VCLAMP_MIN,
-		RT946X_IRCMP_VCLAMP_MAX, RT946X_IRCMP_VCLAMP_STEP, vclamp);
+					RT946X_IRCMP_VCLAMP_MAX,
+					RT946X_IRCMP_VCLAMP_STEP, vclamp);
 
 	CPRINTS("vclamp=%d", vclamp);
 
 	return rt946x_update_bits(chgnum, RT946X_REG_CHGCTRL18,
-		RT946X_MASK_IRCMP_VCLAMP,
-		reg_vclamp << RT946X_SHIFT_IRCMP_VCLAMP);
+				  RT946X_MASK_IRCMP_VCLAMP,
+				  reg_vclamp << RT946X_SHIFT_IRCMP_VCLAMP);
 }
 
 static int rt946x_set_ircmp_res(int chgnum, unsigned int res)
@@ -540,7 +543,7 @@ static int rt946x_set_ircmp_res(int chgnum, unsigned int res)
 	uint8_t reg_res = 0;
 
 	reg_res = rt946x_closest_reg(RT946X_IRCMP_RES_MIN, RT946X_IRCMP_RES_MAX,
-		RT946X_IRCMP_RES_STEP, res);
+				     RT946X_IRCMP_RES_STEP, res);
 
 	CPRINTS("res=%d", res);
 
@@ -554,7 +557,7 @@ static int rt946x_set_vprec(int chgnum, unsigned int vprec)
 	uint8_t reg_vprec = 0;
 
 	reg_vprec = rt946x_closest_reg(RT946X_VPREC_MIN, RT946X_VPREC_MAX,
-		RT946X_VPREC_STEP, vprec);
+				       RT946X_VPREC_STEP, vprec);
 
 	CPRINTS("vprec=%d", vprec);
 
@@ -568,7 +571,7 @@ static int rt946x_set_iprec(int chgnum, unsigned int iprec)
 	uint8_t reg_iprec = 0;
 
 	reg_iprec = rt946x_closest_reg(RT946X_IPREC_MIN, RT946X_IPREC_MAX,
-		RT946X_IPREC_STEP, iprec);
+				       RT946X_IPREC_STEP, iprec);
 
 	CPRINTS("iprec=%d", iprec);
 
@@ -642,12 +645,10 @@ static int rt946x_init_setting(int chgnum)
 	rv = rt946x_set_ieoc(chgnum, setting->eoc_current);
 	if (rv)
 		return rv;
-	rv = rt946x_set_boost_voltage(chgnum,
-		setting->boost_voltage);
+	rv = rt946x_set_boost_voltage(chgnum, setting->boost_voltage);
 	if (rv)
 		return rv;
-	rv = rt946x_set_boost_current(chgnum,
-		setting->boost_current);
+	rv = rt946x_set_boost_current(chgnum, setting->boost_current);
 	if (rv)
 		return rv;
 	rv = rt946x_set_ircmp_vclamp(chgnum, setting->ircmp_vclamp);
@@ -657,7 +658,8 @@ static int rt946x_init_setting(int chgnum)
 	if (rv)
 		return rv;
 	rv = rt946x_set_vprec(chgnum, batt_info->precharge_voltage ?
-			batt_info->precharge_voltage : batt_info->voltage_min);
+					      batt_info->precharge_voltage :
+					      batt_info->voltage_min);
 	if (rv)
 		return rv;
 	rv = rt946x_set_iprec(chgnum, batt_info->precharge_current);
@@ -665,8 +667,9 @@ static int rt946x_init_setting(int chgnum)
 		return rv;
 
 #ifdef CONFIG_CHARGER_MT6370_BACKLIGHT
-	rt946x_write8(chgnum, MT6370_BACKLIGHT_BLEN,
-		      MT6370_MASK_BLED_EXT_EN | MT6370_MASK_BLED_EN |
+	rt946x_write8(
+		chgnum, MT6370_BACKLIGHT_BLEN,
+		MT6370_MASK_BLED_EXT_EN | MT6370_MASK_BLED_EN |
 			MT6370_MASK_BLED_1CH_EN | MT6370_MASK_BLED_2CH_EN |
 			MT6370_MASK_BLED_3CH_EN | MT6370_MASK_BLED_4CH_EN |
 			MT6370_BLED_CODE_LINEAR);
@@ -681,8 +684,8 @@ static int rt946x_init_setting(int chgnum)
 #ifdef CONFIG_CHARGER_OTG
 static enum ec_error_list rt946x_enable_otg_power(int chgnum, int enabled)
 {
-	return (enabled ? rt946x_set_bit : rt946x_clr_bit)
-		(chgnum, RT946X_REG_CHGCTRL1, RT946X_MASK_OPA_MODE);
+	return (enabled ? rt946x_set_bit : rt946x_clr_bit)(
+		chgnum, RT946X_REG_CHGCTRL1, RT946X_MASK_OPA_MODE);
 }
 
 static int rt946x_is_sourcing_otg_power(int chgnum, int port)
@@ -700,16 +703,16 @@ static enum ec_error_list rt946x_set_input_current_limit(int chgnum,
 							 int input_current)
 {
 	uint8_t reg_iin = 0;
-	const struct charger_info * const info = rt946x_get_info(chgnum);
+	const struct charger_info *const info = rt946x_get_info(chgnum);
 
 	reg_iin = rt946x_closest_reg(info->input_current_min,
-		info->input_current_max, info->input_current_step,
-		input_current);
+				     info->input_current_max,
+				     info->input_current_step, input_current);
 
 	CPRINTS("iin=%d", input_current);
 
 	return rt946x_update_bits(chgnum, RT946X_REG_CHGCTRL3, RT946X_MASK_AICR,
-		reg_iin << RT946X_SHIFT_AICR);
+				  reg_iin << RT946X_SHIFT_AICR);
 }
 
 static enum ec_error_list rt946x_get_input_current_limit(int chgnum,
@@ -717,15 +720,15 @@ static enum ec_error_list rt946x_get_input_current_limit(int chgnum,
 {
 	int rv;
 	int val = 0;
-	const struct charger_info * const info = rt946x_get_info(chgnum);
+	const struct charger_info *const info = rt946x_get_info(chgnum);
 
 	rv = rt946x_read8(chgnum, RT946X_REG_CHGCTRL3, &val);
 	if (rv)
 		return rv;
 
 	val = (val & RT946X_MASK_AICR) >> RT946X_SHIFT_AICR;
-	*input_current = val * info->input_current_step
-		+ info->input_current_min;
+	*input_current =
+		val * info->input_current_step + info->input_current_min;
 
 	return EC_SUCCESS;
 }
@@ -781,7 +784,6 @@ static enum ec_error_list rt946x_get_status(int chgnum, int *status)
 	if (val & RT946X_MASK_CHG_VBATOV)
 		*status |= CHARGER_VOLTAGE_OR;
 
-
 	rv = rt946x_read8(chgnum, RT946X_REG_CHGNTC, &val);
 	if (rv)
 		return rv;
@@ -832,7 +834,7 @@ static enum ec_error_list rt946x_get_current(int chgnum, int *current)
 {
 	int rv;
 	int val = 0;
-	const struct charger_info * const info = rt946x_get_info(chgnum);
+	const struct charger_info *const info = rt946x_get_info(chgnum);
 
 	rv = rt946x_read8(chgnum, RT946X_REG_CHGCTRL7, &val);
 	if (rv)
@@ -905,7 +907,7 @@ static enum ec_error_list rt946x_get_voltage(int chgnum, int *voltage)
 {
 	int rv;
 	int val = 0;
-	const struct charger_info * const info = rt946x_get_info(chgnum);
+	const struct charger_info *const info = rt946x_get_info(chgnum);
 
 	rv = rt946x_read8(chgnum, RT946X_REG_CHGCTRL4, &val);
 	if (rv)
@@ -920,13 +922,13 @@ static enum ec_error_list rt946x_get_voltage(int chgnum, int *voltage)
 static enum ec_error_list rt946x_set_voltage(int chgnum, int voltage)
 {
 	uint8_t reg_cv = 0;
-	const struct charger_info * const info = rt946x_get_info(chgnum);
+	const struct charger_info *const info = rt946x_get_info(chgnum);
 
 	reg_cv = rt946x_closest_reg(info->voltage_min, info->voltage_max,
-		info->voltage_step, voltage);
+				    info->voltage_step, voltage);
 
 	return rt946x_update_bits(chgnum, RT946X_REG_CHGCTRL4, RT946X_MASK_CV,
-		reg_cv << RT946X_SHIFT_CV);
+				  reg_cv << RT946X_SHIFT_CV);
 }
 
 static enum ec_error_list rt946x_discharge_on_ac(int chgnum, int enable)
@@ -940,8 +942,8 @@ static int rt946x_enable_ilim_pin(int chgnum, int en)
 {
 	int ret;
 
-	ret = (en ? rt946x_set_bit : rt946x_clr_bit)
-		(chgnum, RT946X_REG_CHGCTRL3, RT946X_MASK_ILIMEN);
+	ret = (en ? rt946x_set_bit : rt946x_clr_bit)(
+		chgnum, RT946X_REG_CHGCTRL3, RT946X_MASK_ILIMEN);
 
 	return ret;
 }
@@ -1001,7 +1003,8 @@ static int rt946x_set_aicl_vth(int chgnum, uint8_t aicl_vth)
 	uint8_t reg_aicl_vth = 0;
 
 	reg_aicl_vth = rt946x_closest_reg(RT946X_AICLVTH_MIN,
-		RT946X_AICLVTH_MAX, RT946X_AICLVTH_STEP, aicl_vth);
+					  RT946X_AICLVTH_MAX,
+					  RT946X_AICLVTH_STEP, aicl_vth);
 
 	return rt946x_update_bits(chgnum, RT946X_REG_CHGCTRL14,
 				  RT946X_MASK_AICLVTH,
@@ -1079,14 +1082,13 @@ static void rt946x_init(int chgnum)
 static int mt6370_detect_apple_samsung_ta(int chgnum, int usb_stat)
 {
 	int ret, reg;
-	int chg_type =
-		(usb_stat & MT6370_MASK_USB_STATUS) >> MT6370_SHIFT_USB_STATUS;
+	int chg_type = (usb_stat & MT6370_MASK_USB_STATUS) >>
+		       MT6370_SHIFT_USB_STATUS;
 	int dp_2_3v, dm_2_3v;
 
 	/* Only SDP/CDP/DCP could possibly be Apple/Samsung TA */
 	if (chg_type != MT6370_CHG_TYPE_SDPNSTD &&
-	    chg_type != MT6370_CHG_TYPE_CDP &&
-	    chg_type != MT6370_CHG_TYPE_DCP)
+	    chg_type != MT6370_CHG_TYPE_CDP && chg_type != MT6370_CHG_TYPE_DCP)
 		return chg_type;
 
 	if (chg_type == MT6370_CHG_TYPE_SDPNSTD ||
@@ -1115,13 +1117,13 @@ static int mt6370_detect_apple_samsung_ta(int chgnum, int usb_stat)
 	ret = rt946x_update_bits(chgnum, MT6370_REG_QCSTATUS2,
 				 MT6360_MASK_CHECK_DPDM,
 				 MT6370_MASK_APP_REF | MT6370_MASK_APP_SS_PL |
-				 MT6370_MASK_APP_SS_EN);
+					 MT6370_MASK_APP_SS_EN);
 	ret |= rt946x_read8(chgnum, MT6370_REG_QCSTATUS2, &reg);
 	dp_2_3v = reg & MT6370_MASK_APP_OUT;
 
 	/* Check D- > 2.3 V */
-	ret |= rt946x_update_bits(chgnum,
-		MT6370_REG_QCSTATUS2, MT6360_MASK_CHECK_DPDM,
+	ret |= rt946x_update_bits(
+		chgnum, MT6370_REG_QCSTATUS2, MT6360_MASK_CHECK_DPDM,
 		MT6370_MASK_APP_REF | MT6370_MASK_APP_DPDM_IN |
 			MT6370_MASK_APP_SS_PL | MT6370_MASK_APP_SS_EN);
 	ret |= rt946x_read8(chgnum, MT6370_REG_QCSTATUS2, &reg);
@@ -1327,7 +1329,7 @@ int rt946x_get_adc(enum rt946x_adc_in_sel adc_sel, int *adc_val)
 	if (in_interrupt_context()) {
 		CPRINTS("Err: use ADC in IRQ");
 		return EC_ERROR_INVAL;
-        }
+	}
 	mutex_lock(&adc_access_lock);
 #ifdef CONFIG_CHARGER_MT6370
 	mt6370_enable_hidden_mode(CHARGER_SOLO, 1);
@@ -1355,8 +1357,8 @@ int rt946x_get_adc(enum rt946x_adc_in_sel adc_sel, int *adc_val)
 	for (i = 0; i < max_wait_times; i++) {
 		msleep(35);
 		rv = mt6370_pmu_reg_test_bit(CHARGER_SOLO, RT946X_REG_CHGADC,
-					      RT946X_SHIFT_ADC_START,
-					      &adc_start);
+					     RT946X_SHIFT_ADC_START,
+					     &adc_start);
 		if (!adc_start && rv == 0)
 			break;
 	}
@@ -1377,8 +1379,9 @@ int rt946x_get_adc(enum rt946x_adc_in_sel adc_sel, int *adc_val)
 	*adc_val = adc_result;
 #elif defined(CONFIG_CHARGER_MT6370)
 	/* Calculate ADC value */
-	adc_result = (adc_data_h * 256 + adc_data_l)
-			* mt6370_adc_unit[adc_sel] + mt6370_adc_offset[adc_sel];
+	adc_result =
+		(adc_data_h * 256 + adc_data_l) * mt6370_adc_unit[adc_sel] +
+		mt6370_adc_offset[adc_sel];
 
 	/* For TS_BAT/TS_BUS, the real unit is 0.25, here we use 25(unit) */
 	if (adc_sel == MT6370_ADC_TS_BAT)
@@ -1447,7 +1450,7 @@ static int mt6370_pmu_chg_mivr_irq_handler(int chgnum)
 	int rv, ibus = 0, mivr_stat;
 
 	rv = mt6370_pmu_reg_test_bit(chgnum, MT6370_REG_CHGSTAT1,
-				MT6370_SHIFT_MIVR_STAT, &mivr_stat);
+				     MT6370_SHIFT_MIVR_STAT, &mivr_stat);
 	if (rv)
 		return rv;
 
@@ -1557,33 +1560,26 @@ static void rt946x_usb_charger_task_init(const int unused_port)
 					mt6370_get_bc12_device_type(chg_type);
 				chg.current = mt6370_get_bc12_ilim(bc12_type);
 			} else {
-				bc12_type =
-				    rt946x_get_bc12_device_type(CHARGER_SOLO,
-								    chg_type);
+				bc12_type = rt946x_get_bc12_device_type(
+					CHARGER_SOLO, chg_type);
 				chg.current = rt946x_get_bc12_ilim(bc12_type);
 			}
 			CPRINTS("BC12 type %d", bc12_type);
 			if (bc12_type == CHARGE_SUPPLIER_NONE)
 				goto bc12_none;
-			if (IS_ENABLED(CONFIG_WIRELESS_CHARGER_P9221_R7) &&
-			    bc12_type == CHARGE_SUPPLIER_BC12_SDP &&
-			    wpc_chip_is_online()) {
-					p9221_notify_vbus_change(1);
-					CPRINTS("WPC ON");
-			}
 			if (bc12_type == CHARGE_SUPPLIER_BC12_SDP &&
 			    ++bc12_cnt < max_bc12_cnt) {
 				/*
 				 * defer the workaround and awaiting for
 				 * waken up by the interrupt.
 				 */
-				hook_call_deferred(
-					&rt946x_bc12_workaround_data, 5);
+				hook_call_deferred(&rt946x_bc12_workaround_data,
+						   5);
 				goto wait_event;
 			}
 
 			charge_manager_update_charge(bc12_type, 0, &chg);
-bc12_none:
+		bc12_none:
 			rt946x_enable_bc12_detection(CHARGER_SOLO, 0);
 		}
 
@@ -1592,13 +1588,10 @@ bc12_none:
 		    bc12_type != CHARGE_SUPPLIER_NONE) {
 			CPRINTS("VBUS detached");
 			bc12_cnt = 0;
-#ifdef CONFIG_WIRELESS_CHARGER_P9221_R7
-			p9221_notify_vbus_change(0);
-#endif
 			charge_manager_update_charge(bc12_type, 0, NULL);
 		}
 
-wait_event:
+	wait_event:
 		task_wait_event(-1);
 	}
 }
@@ -1618,8 +1611,8 @@ static int rt946x_ramp_max(int supplier, int sup_curr)
 
 int rt946x_enable_charger_boost(int en)
 {
-	return (en ? rt946x_set_bit : rt946x_clr_bit)
-		(CHARGER_SOLO, RT946X_REG_CHGCTRL2, RT946X_MASK_CHG_EN);
+	return (en ? rt946x_set_bit : rt946x_clr_bit)(
+		CHARGER_SOLO, RT946X_REG_CHGCTRL2, RT946X_MASK_CHG_EN);
 }
 
 /*
@@ -1631,7 +1624,8 @@ int rt946x_is_vbus_ready(void)
 	int val = 0;
 
 	return rt946x_read8(CHARGER_SOLO, RT946X_REG_CHGSTATC, &val) ?
-	       0 : !!(val & RT946X_MASK_PWR_RDY);
+		       0 :
+		       !!(val & RT946X_MASK_PWR_RDY);
 }
 
 int rt946x_is_charge_done(void)
@@ -1649,10 +1643,10 @@ int rt946x_is_charge_done(void)
 int rt946x_cutoff_battery(void)
 {
 #ifdef CONFIG_CHARGER_MT6370
-/*
- * We should lock ADC usage to prevent from using ADC while
- * cut-off. Or this might cause the ADC power not turning off.
- */
+	/*
+	 * We should lock ADC usage to prevent from using ADC while
+	 * cut-off. Or this might cause the ADC power not turning off.
+	 */
 
 	int rv;
 
@@ -1675,7 +1669,7 @@ int rt946x_cutoff_battery(void)
 	/* disable chg auto sensing */
 	mt6370_enable_hidden_mode(CHARGER_SOLO, 1);
 	rv = rt946x_clr_bit(CHARGER_SOLO, MT6370_REG_CHGHIDDENCTRL15,
-				MT6370_MASK_ADC_TS_AUTO);
+			    MT6370_MASK_ADC_TS_AUTO);
 	mt6370_enable_hidden_mode(CHARGER_SOLO, 0);
 	if (rv)
 		goto out;
@@ -1695,14 +1689,14 @@ out:
 
 int rt946x_enable_charge_termination(int en)
 {
-	return (en ? rt946x_set_bit : rt946x_clr_bit)
-		(CHARGER_SOLO, RT946X_REG_CHGCTRL2, RT946X_MASK_TE);
+	return (en ? rt946x_set_bit : rt946x_clr_bit)(
+		CHARGER_SOLO, RT946X_REG_CHGCTRL2, RT946X_MASK_TE);
 }
 
 int rt946x_enable_charge_eoc(int en)
 {
-	return (en ? rt946x_set_bit : rt946x_clr_bit)
-		(CHARGER_SOLO, RT946X_REG_CHGCTRL9, RT946X_MASK_EOC);
+	return (en ? rt946x_set_bit : rt946x_clr_bit)(
+		CHARGER_SOLO, RT946X_REG_CHGCTRL9, RT946X_MASK_EOC);
 }
 
 #ifdef CONFIG_CHARGER_MT6370
@@ -1745,29 +1739,26 @@ int mt6370_db_set_voltages(int vbst, int vpos, int vneg)
 	int rv;
 
 	/* set display bias VBST */
-	rv = rt946x_update_bits(CHARGER_SOLO, MT6370_REG_DBVBST,
-				MT6370_MASK_DB_VBST,
-				rt946x_closest_reg(MT6370_DB_VBST_MIN,
-						   MT6370_DB_VBST_MAX,
-						   MT6370_DB_VBST_STEP, vbst));
+	rv = rt946x_update_bits(
+		CHARGER_SOLO, MT6370_REG_DBVBST, MT6370_MASK_DB_VBST,
+		rt946x_closest_reg(MT6370_DB_VBST_MIN, MT6370_DB_VBST_MAX,
+				   MT6370_DB_VBST_STEP, vbst));
 
 	/* set display bias VPOS */
-	rv |= rt946x_update_bits(CHARGER_SOLO, MT6370_REG_DBVPOS,
-				 MT6370_MASK_DB_VPOS,
-				 rt946x_closest_reg(MT6370_DB_VPOS_MIN,
-						    MT6370_DB_VPOS_MAX,
-						    MT6370_DB_VPOS_STEP, vpos));
+	rv |= rt946x_update_bits(
+		CHARGER_SOLO, MT6370_REG_DBVPOS, MT6370_MASK_DB_VPOS,
+		rt946x_closest_reg(MT6370_DB_VPOS_MIN, MT6370_DB_VPOS_MAX,
+				   MT6370_DB_VPOS_STEP, vpos));
 
 	/* set display bias VNEG */
-	rv |= rt946x_update_bits(CHARGER_SOLO, MT6370_REG_DBVNEG,
-				 MT6370_MASK_DB_VNEG,
-				 rt946x_closest_reg(MT6370_DB_VNEG_MIN,
-						    MT6370_DB_VNEG_MAX,
-						    MT6370_DB_VNEG_STEP, vneg));
+	rv |= rt946x_update_bits(
+		CHARGER_SOLO, MT6370_REG_DBVNEG, MT6370_MASK_DB_VNEG,
+		rt946x_closest_reg(MT6370_DB_VNEG_MIN, MT6370_DB_VNEG_MAX,
+				   MT6370_DB_VNEG_STEP, vneg));
 
 	/* Enable VNEG/VPOS discharge when VNEG/VPOS rails disabled. */
-	rv |= rt946x_update_bits(CHARGER_SOLO,
-		MT6370_REG_DBCTRL2,
+	rv |= rt946x_update_bits(
+		CHARGER_SOLO, MT6370_REG_DBCTRL2,
 		MT6370_MASK_DB_VNEG_DISC | MT6370_MASK_DB_VPOS_DISC,
 		MT6370_MASK_DB_VNEG_DISC | MT6370_MASK_DB_VPOS_DISC);
 
diff --git a/driver/charger/rt946x.h b/driver/charger/rt946x.h
index 8c8cdf03ff..9d0247ac5d 100644
--- a/driver/charger/rt946x.h
+++ b/driver/charger/rt946x.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,693 +10,691 @@
 
 /* Registers for rt9466, rt9467 */
 #if defined(CONFIG_CHARGER_RT9466) || defined(CONFIG_CHARGER_RT9467)
-#define RT946X_REG_CORECTRL0		0x00
-#define RT946X_REG_CORECTRL_RST		RT946X_REG_CORECTRL0
-#define RT946X_REG_CHGCTRL1		0x01
-#define RT946X_REG_CHGCTRL2		0x02
-#define RT946X_REG_CHGCTRL3		0x03
-#define RT946X_REG_CHGCTRL4		0x04
-#define RT946X_REG_CHGCTRL5		0x05
-#define RT946X_REG_CHGCTRL6		0x06
-#define RT946X_REG_CHGCTRL7		0x07
-#define RT946X_REG_CHGCTRL8		0x08
-#define RT946X_REG_CHGCTRL9		0x09
-#define RT946X_REG_CHGCTRL10		0x0A
-#define RT946X_REG_CHGCTRL11		0x0B
-#define RT946X_REG_CHGCTRL12		0x0C
-#define RT946X_REG_CHGCTRL13		0x0D
-#define RT946X_REG_CHGCTRL14		0x0E
-#define RT946X_REG_CHGCTRL15		0x0F
-#define RT946X_REG_CHGCTRL16		0x10
-#define RT946X_REG_CHGADC		0x11
+#define RT946X_REG_CORECTRL0 0x00
+#define RT946X_REG_CORECTRL_RST RT946X_REG_CORECTRL0
+#define RT946X_REG_CHGCTRL1 0x01
+#define RT946X_REG_CHGCTRL2 0x02
+#define RT946X_REG_CHGCTRL3 0x03
+#define RT946X_REG_CHGCTRL4 0x04
+#define RT946X_REG_CHGCTRL5 0x05
+#define RT946X_REG_CHGCTRL6 0x06
+#define RT946X_REG_CHGCTRL7 0x07
+#define RT946X_REG_CHGCTRL8 0x08
+#define RT946X_REG_CHGCTRL9 0x09
+#define RT946X_REG_CHGCTRL10 0x0A
+#define RT946X_REG_CHGCTRL11 0x0B
+#define RT946X_REG_CHGCTRL12 0x0C
+#define RT946X_REG_CHGCTRL13 0x0D
+#define RT946X_REG_CHGCTRL14 0x0E
+#define RT946X_REG_CHGCTRL15 0x0F
+#define RT946X_REG_CHGCTRL16 0x10
+#define RT946X_REG_CHGADC 0x11
 
 #ifdef CONFIG_CHARGER_RT9467
-#define RT946X_REG_DPDM1		0x12
-#define RT946X_REG_DPDM2		0x13
-#define RT946X_REG_DPDM3		0x14
+#define RT946X_REG_DPDM1 0x12
+#define RT946X_REG_DPDM2 0x13
+#define RT946X_REG_DPDM3 0x14
 #endif
 
-#define RT946X_REG_CHGCTRL19		0x18
-#define RT946X_REG_CHGCTRL17		0x19
-#define RT946X_REG_CHGCTRL18		0x1A
-#define RT946X_REG_CHGHIDDENCTRL2	0x21
-#define RT946X_REG_CHGHIDDENCTRL4	0x23
-#define RT946X_REG_CHGHIDDENCTRL6	0x25
-#define RT946X_REG_CHGHIDDENCTRL7	0x26
-#define RT946X_REG_CHGHIDDENCTRL8	0x27
-#define RT946X_REG_CHGHIDDENCTRL9	0x28
-#define RT946X_REG_CHGHIDDENCTRL15	0x2E
-#define RT946X_REG_DEVICEID		0x40
-#define RT946X_REG_CHGSTAT		0x42
-#define RT946X_REG_CHGNTC		0x43
-#define RT946X_REG_ADCDATAH		0x44
-#define RT946X_REG_ADCDATAL		0x45
-#define RT946X_REG_CHGSTATC		0x50
-#define RT946X_REG_CHGFAULT		0x51
-#define RT946X_REG_TSSTATC		0x52
-#define RT946X_REG_CHGIRQ1		0x53
-#define RT946X_REG_CHGIRQ2		0x54
-#define RT946X_REG_CHGIRQ3		0x55
+#define RT946X_REG_CHGCTRL19 0x18
+#define RT946X_REG_CHGCTRL17 0x19
+#define RT946X_REG_CHGCTRL18 0x1A
+#define RT946X_REG_CHGHIDDENCTRL2 0x21
+#define RT946X_REG_CHGHIDDENCTRL4 0x23
+#define RT946X_REG_CHGHIDDENCTRL6 0x25
+#define RT946X_REG_CHGHIDDENCTRL7 0x26
+#define RT946X_REG_CHGHIDDENCTRL8 0x27
+#define RT946X_REG_CHGHIDDENCTRL9 0x28
+#define RT946X_REG_CHGHIDDENCTRL15 0x2E
+#define RT946X_REG_DEVICEID 0x40
+#define RT946X_REG_CHGSTAT 0x42
+#define RT946X_REG_CHGNTC 0x43
+#define RT946X_REG_ADCDATAH 0x44
+#define RT946X_REG_ADCDATAL 0x45
+#define RT946X_REG_CHGSTATC 0x50
+#define RT946X_REG_CHGFAULT 0x51
+#define RT946X_REG_TSSTATC 0x52
+#define RT946X_REG_CHGIRQ1 0x53
+#define RT946X_REG_CHGIRQ2 0x54
+#define RT946X_REG_CHGIRQ3 0x55
 
 #ifdef CONFIG_CHARGER_RT9467
-#define RT946X_REG_DPDMIRQ		0x56
+#define RT946X_REG_DPDMIRQ 0x56
 #endif
 
-#define RT946X_REG_CHGSTATCCTRL		0x60
-#define RT946X_REG_CHGFAULTCTRL		0x61
-#define RT946X_REG_TSSTATCCTRL		0x62
-#define RT946X_REG_CHGIRQ1CTRL		0x63
-#define RT946X_REG_CHGIRQ2CTRL		0x64
-#define RT946X_REG_CHGIRQ3CTRL		0x65
+#define RT946X_REG_CHGSTATCCTRL 0x60
+#define RT946X_REG_CHGFAULTCTRL 0x61
+#define RT946X_REG_TSSTATCCTRL 0x62
+#define RT946X_REG_CHGIRQ1CTRL 0x63
+#define RT946X_REG_CHGIRQ2CTRL 0x64
+#define RT946X_REG_CHGIRQ3CTRL 0x65
 
 #ifdef CONFIG_CHARGER_RT9467
-#define RT946X_REG_DPDMIRQCTRL		0x66
+#define RT946X_REG_DPDMIRQCTRL 0x66
 #endif
 
 #elif defined(CONFIG_CHARGER_MT6370)
 /* Registers for mt6370 */
-#define RT946X_REG_DEVICEID		0x00
-#define RT946X_REG_CORECTRL1		0x01
-#define RT946X_REG_CORECTRL2		0x02
-#define RT946X_REG_CORECTRL_RST		RT946X_REG_CORECTRL2
-#define MT6370_REG_RSTPASCODE1		0x03
-#define MT6370_REG_RSTPASCODE2		0x04
-#define MT6370_REG_HIDDENPASCODE1	0x07
-#define MT6370_REG_HIDDENPASCODE2	0x08
-#define MT6370_REG_HIDDENPASCODE3	0x09
-#define MT6370_REG_HIDDENPASCODE4	0x0A
-#define MT6370_REG_IRQIND		0x0B
-#define MT6370_REG_IRQMASK		0x0C
-#define MT6370_REG_OSCCTRL		0x10
-#define RT946X_REG_CHGCTRL1		0x11
-#define RT946X_REG_CHGCTRL2		0x12
-#define RT946X_REG_CHGCTRL3		0x13
-#define RT946X_REG_CHGCTRL4		0x14
-#define RT946X_REG_CHGCTRL5		0x15
-#define RT946X_REG_CHGCTRL6		0x16
-#define RT946X_REG_CHGCTRL7		0x17
-#define RT946X_REG_CHGCTRL8		0x18
-#define RT946X_REG_CHGCTRL9		0x19
-#define RT946X_REG_CHGCTRL10		0x1A
-#define RT946X_REG_CHGCTRL11		0x1B
-#define RT946X_REG_CHGCTRL12		0x1C
-#define RT946X_REG_CHGCTRL13		0x1D
-#define RT946X_REG_CHGCTRL14		0x1E
-#define RT946X_REG_CHGCTRL15		0x1F
-#define RT946X_REG_CHGCTRL16		0x20
-#define RT946X_REG_CHGADC		0x21
-#define MT6370_REG_DEVICETYPE		0x22
-#define RT946X_REG_DPDM1		MT6370_REG_DEVICETYPE
-#define MT6370_REG_USBSTATUS1		0x27
-#define MT6370_REG_QCSTATUS2		0x29
-#define RT946X_REG_CHGCTRL17		0X2B
-#define RT946X_REG_CHGCTRL18		0X2C
-#define RT946X_REG_CHGHIDDENCTRL7	0x36
-#define MT6370_REG_CHGHIDDENCTRL15	0x3E
-#define RT946X_REG_CHGSTAT		0X4A
-#define RT946X_REG_CHGNTC		0X4B
-#define RT946X_REG_ADCDATAH		0X4C
-#define RT946X_REG_ADCDATAL		0X4D
+#define RT946X_REG_DEVICEID 0x00
+#define RT946X_REG_CORECTRL1 0x01
+#define RT946X_REG_CORECTRL2 0x02
+#define RT946X_REG_CORECTRL_RST RT946X_REG_CORECTRL2
+#define MT6370_REG_RSTPASCODE1 0x03
+#define MT6370_REG_RSTPASCODE2 0x04
+#define MT6370_REG_HIDDENPASCODE1 0x07
+#define MT6370_REG_HIDDENPASCODE2 0x08
+#define MT6370_REG_HIDDENPASCODE3 0x09
+#define MT6370_REG_HIDDENPASCODE4 0x0A
+#define MT6370_REG_IRQIND 0x0B
+#define MT6370_REG_IRQMASK 0x0C
+#define MT6370_REG_OSCCTRL 0x10
+#define RT946X_REG_CHGCTRL1 0x11
+#define RT946X_REG_CHGCTRL2 0x12
+#define RT946X_REG_CHGCTRL3 0x13
+#define RT946X_REG_CHGCTRL4 0x14
+#define RT946X_REG_CHGCTRL5 0x15
+#define RT946X_REG_CHGCTRL6 0x16
+#define RT946X_REG_CHGCTRL7 0x17
+#define RT946X_REG_CHGCTRL8 0x18
+#define RT946X_REG_CHGCTRL9 0x19
+#define RT946X_REG_CHGCTRL10 0x1A
+#define RT946X_REG_CHGCTRL11 0x1B
+#define RT946X_REG_CHGCTRL12 0x1C
+#define RT946X_REG_CHGCTRL13 0x1D
+#define RT946X_REG_CHGCTRL14 0x1E
+#define RT946X_REG_CHGCTRL15 0x1F
+#define RT946X_REG_CHGCTRL16 0x20
+#define RT946X_REG_CHGADC 0x21
+#define MT6370_REG_DEVICETYPE 0x22
+#define RT946X_REG_DPDM1 MT6370_REG_DEVICETYPE
+#define MT6370_REG_USBSTATUS1 0x27
+#define MT6370_REG_QCSTATUS2 0x29
+#define RT946X_REG_CHGCTRL17 0X2B
+#define RT946X_REG_CHGCTRL18 0X2C
+#define RT946X_REG_CHGHIDDENCTRL7 0x36
+#define MT6370_REG_CHGHIDDENCTRL15 0x3E
+#define RT946X_REG_CHGSTAT 0X4A
+#define RT946X_REG_CHGNTC 0X4B
+#define RT946X_REG_ADCDATAH 0X4C
+#define RT946X_REG_ADCDATAL 0X4D
 /* FLED */
-#define MT6370_REG_FLEDEN		0x7E
+#define MT6370_REG_FLEDEN 0x7E
 /* LDO */
-#define MT6370_REG_LDOCFG		0X80
-#define MT6370_REG_LDOVOUT		0X81
+#define MT6370_REG_LDOCFG 0X80
+#define MT6370_REG_LDOVOUT 0X81
 /* RGB led */
-#define MT6370_REG_RGBDIM_BASE		0x81
-#define MT6370_REG_RGB1DIM		0x82
-#define MT6370_REG_RGB2DIM		0x83
-#define MT6370_REG_RGB3DIM		0x84
-#define MT6370_REG_RGBEN		0x85
-#define MT6370_REG_RGBISNK_BASE		0x85
-#define MT6370_REG_RGB1ISNK		0x86
-#define MT6370_REG_RGB2ISNK		0x87
-#define MT6370_REG_RGB3ISNK		0x88
-#define MT6370_REG_RGBCHRINDDIM		0x92
-#define MT6370_REG_RGBCHRINDCTRL	0x93
+#define MT6370_REG_RGBDIM_BASE 0x81
+#define MT6370_REG_RGB1DIM 0x82
+#define MT6370_REG_RGB2DIM 0x83
+#define MT6370_REG_RGB3DIM 0x84
+#define MT6370_REG_RGBEN 0x85
+#define MT6370_REG_RGBISNK_BASE 0x85
+#define MT6370_REG_RGB1ISNK 0x86
+#define MT6370_REG_RGB2ISNK 0x87
+#define MT6370_REG_RGB3ISNK 0x88
+#define MT6370_REG_RGBCHRINDDIM 0x92
+#define MT6370_REG_RGBCHRINDCTRL 0x93
 
 /* backlight */
-#define MT6370_BACKLIGHT_BLEN		0xA0
-#define MT6370_BACKLIGHT_BLPWM		0xA2
-#define MT6370_BACKLIGHT_BLDIM2		0xA4
-#define MT6370_BACKLIGHT_BLDIM		0xA5
+#define MT6370_BACKLIGHT_BLEN 0xA0
+#define MT6370_BACKLIGHT_BLPWM 0xA2
+#define MT6370_BACKLIGHT_BLDIM2 0xA4
+#define MT6370_BACKLIGHT_BLDIM 0xA5
 
 /* Display bias */
-#define MT6370_REG_DBCTRL1		0XB0
-#define MT6370_REG_DBCTRL2		0XB1
-#define MT6370_REG_DBVBST		0XB2
-#define MT6370_REG_DBVPOS		0XB3
-#define MT6370_REG_DBVNEG		0XB4
-#define MT6370_REG_CHGIRQ1		0xC0
-#define RT946X_REG_DPDMIRQ		0xC6
+#define MT6370_REG_DBCTRL1 0XB0
+#define MT6370_REG_DBCTRL2 0XB1
+#define MT6370_REG_DBVBST 0XB2
+#define MT6370_REG_DBVPOS 0XB3
+#define MT6370_REG_DBVNEG 0XB4
+#define MT6370_REG_CHGIRQ1 0xC0
+#define RT946X_REG_DPDMIRQ 0xC6
 
 /* status event */
-#define MT6370_REG_CHGSTAT1		0xD0
-#define RT946X_REG_CHGSTATC		MT6370_REG_CHGSTAT1
-#define MT6370_REG_CHGSTAT2		0xD1
-#define RT946X_REG_CHGFAULT		MT6370_REG_CHGSTAT2
-#define MT6370_REG_CHGSTAT3		0xD2
-#define MT6370_REG_CHGSTAT4		0xD3
-#define MT6370_REG_CHGSTAT5		0xD4
-#define MT6370_REG_CHGSTAT6		0xD5
-#define MT6370_REG_DPDMSTAT		0xD6
-#define MT6370_REG_DICHGSTAT		0xD7
-#define MT6370_REG_OVPCTRLSTAT		0xD8
-#define MT6370_REG_FLEDSTAT1		0xD9
-#define MT6370_REG_FLEDSTAT2		0xDA
-#define MT6370_REG_BASESTAT		0xDB
-#define MT6370_REG_LDOSTAT		0xDC
-#define MT6370_REG_RGBSTAT		0xDD
-#define MT6370_REG_BLSTAT		0xDE
-#define MT6370_REG_DBSTAT		0xDF
+#define MT6370_REG_CHGSTAT1 0xD0
+#define RT946X_REG_CHGSTATC MT6370_REG_CHGSTAT1
+#define MT6370_REG_CHGSTAT2 0xD1
+#define RT946X_REG_CHGFAULT MT6370_REG_CHGSTAT2
+#define MT6370_REG_CHGSTAT3 0xD2
+#define MT6370_REG_CHGSTAT4 0xD3
+#define MT6370_REG_CHGSTAT5 0xD4
+#define MT6370_REG_CHGSTAT6 0xD5
+#define MT6370_REG_DPDMSTAT 0xD6
+#define MT6370_REG_DICHGSTAT 0xD7
+#define MT6370_REG_OVPCTRLSTAT 0xD8
+#define MT6370_REG_FLEDSTAT1 0xD9
+#define MT6370_REG_FLEDSTAT2 0xDA
+#define MT6370_REG_BASESTAT 0xDB
+#define MT6370_REG_LDOSTAT 0xDC
+#define MT6370_REG_RGBSTAT 0xDD
+#define MT6370_REG_BLSTAT 0xDE
+#define MT6370_REG_DBSTAT 0xDF
 /* irq mask */
-#define MT6370_REG_CHGMASK1		0xE0
-#define RT946X_REG_CHGSTATCCTRL		MT6370_REG_CHGMASK1
-#define MT6370_REG_CHGMASK2		0xE1
-#define MT6370_REG_CHGMASK3		0xE2
-#define MT6370_REG_CHGMASK4		0xE3
-#define MT6370_REG_CHGMASK5		0xE4
-#define MT6370_REG_CHGMASK6		0xE5
-#define MT6370_REG_DPDMMASK1		0xE6
-#define MT6370_REG_DICHGMASK		0xE7
-#define MT6370_REG_OVPCTRLMASK		0xE8
-#define MT6370_REG_FLEDMASK1		0xE9
-#define MT6370_REG_FLEDMASK2		0xEA
-#define MT6370_REG_BASEMASK		0xEB
-#define MT6370_REG_LDOMASK		0xEC
-#define MT6370_REG_RGBMASK		0xED
-#define MT6370_REG_BLMASK		0xEE
-#define MT6370_REG_DBMASK		0xEF
-#define MT6370_REG_TM_PAS_CODE1		0xF0
-#define MT6370_REG_BANK			0xFF
+#define MT6370_REG_CHGMASK1 0xE0
+#define RT946X_REG_CHGSTATCCTRL MT6370_REG_CHGMASK1
+#define MT6370_REG_CHGMASK2 0xE1
+#define MT6370_REG_CHGMASK3 0xE2
+#define MT6370_REG_CHGMASK4 0xE3
+#define MT6370_REG_CHGMASK5 0xE4
+#define MT6370_REG_CHGMASK6 0xE5
+#define MT6370_REG_DPDMMASK1 0xE6
+#define MT6370_REG_DICHGMASK 0xE7
+#define MT6370_REG_OVPCTRLMASK 0xE8
+#define MT6370_REG_FLEDMASK1 0xE9
+#define MT6370_REG_FLEDMASK2 0xEA
+#define MT6370_REG_BASEMASK 0xEB
+#define MT6370_REG_LDOMASK 0xEC
+#define MT6370_REG_RGBMASK 0xED
+#define MT6370_REG_BLMASK 0xEE
+#define MT6370_REG_DBMASK 0xEF
+#define MT6370_REG_TM_PAS_CODE1 0xF0
+#define MT6370_REG_BANK 0xFF
 /* TM REGISTER */
-#define MT6370_TM_REG_BL3		0x34
-#define MT6370_TM_REG_DSV1		0x37
+#define MT6370_TM_REG_BL3 0x34
+#define MT6370_TM_REG_DSV1 0x37
 #else
 #error "No suitable charger option defined"
 #endif
 
 /* EOC current */
-#define RT946X_IEOC_MIN		100
-#define RT946X_IEOC_MAX		850
-#define RT946X_IEOC_STEP	50
+#define RT946X_IEOC_MIN 100
+#define RT946X_IEOC_MAX 850
+#define RT946X_IEOC_STEP 50
 
 /* Minimum Input Voltage Regulator */
-#define RT946X_MIVR_MIN		3900
-#define RT946X_MIVR_MAX		13400
-#define RT946X_MIVR_STEP	100
+#define RT946X_MIVR_MIN 3900
+#define RT946X_MIVR_MAX 13400
+#define RT946X_MIVR_STEP 100
 
 /* Boost voltage */
-#define RT946X_BOOST_VOLTAGE_MIN	4425
-#define RT946X_BOOST_VOLTAGE_MAX	5825
-#define RT946X_BOOST_VOLTAGE_STEP	25
+#define RT946X_BOOST_VOLTAGE_MIN 4425
+#define RT946X_BOOST_VOLTAGE_MAX 5825
+#define RT946X_BOOST_VOLTAGE_STEP 25
 
 /* IR compensation resistor */
-#define RT946X_IRCMP_RES_MIN	0
-#define RT946X_IRCMP_RES_MAX	175
-#define RT946X_IRCMP_RES_STEP	25
+#define RT946X_IRCMP_RES_MIN 0
+#define RT946X_IRCMP_RES_MAX 175
+#define RT946X_IRCMP_RES_STEP 25
 
 /* IR compensation voltage clamp */
-#define RT946X_IRCMP_VCLAMP_MIN		0
-#define RT946X_IRCMP_VCLAMP_MAX		224
-#define RT946X_IRCMP_VCLAMP_STEP	32
+#define RT946X_IRCMP_VCLAMP_MIN 0
+#define RT946X_IRCMP_VCLAMP_MAX 224
+#define RT946X_IRCMP_VCLAMP_STEP 32
 
 /* Pre-charge mode threshold voltage */
-#define RT946X_VPREC_MIN		2000
-#define RT946X_VPREC_MAX		3500
-#define RT946X_VPREC_STEP		100
+#define RT946X_VPREC_MIN 2000
+#define RT946X_VPREC_MAX 3500
+#define RT946X_VPREC_STEP 100
 
 /* Pre-charge current */
-#define RT946X_IPREC_MIN		100
-#define RT946X_IPREC_MAX		850
-#define RT946X_IPREC_STEP		50
+#define RT946X_IPREC_MIN 100
+#define RT946X_IPREC_MAX 850
+#define RT946X_IPREC_STEP 50
 
 /* AICLVTH */
-#define RT946X_AICLVTH_MIN	4100
-#define RT946X_AICLVTH_MAX	4800
-#define RT946X_AICLVTH_STEP	100
+#define RT946X_AICLVTH_MIN 4100
+#define RT946X_AICLVTH_MAX 4800
+#define RT946X_AICLVTH_STEP 100
 
 /* NTC */
-#define RT946X_BATTEMP_NORMAL	0x00
-#define RT946X_BATTEMP_WARM	0x02
-#define RT946X_BATTEMP_COOL	0x03
-#define RT946X_BATTEMP_COLD	0x05
-#define RT946X_BATTEMP_HOT	0x06
+#define RT946X_BATTEMP_NORMAL 0x00
+#define RT946X_BATTEMP_WARM 0x02
+#define RT946X_BATTEMP_COOL 0x03
+#define RT946X_BATTEMP_COLD 0x05
+#define RT946X_BATTEMP_HOT 0x06
 
 /* LDO voltage */
-#define MT6370_LDO_MIN		1600
-#define MT6370_LDO_MAX		4000
-#define MT6370_LDO_STEP		200
+#define MT6370_LDO_MIN 1600
+#define MT6370_LDO_MAX 4000
+#define MT6370_LDO_STEP 200
 
 /* ========== CORECTRL0 0x00 ============ */
-#define RT946X_SHIFT_RST	7
-#define RT946X_SHIFT_CHG_RST	6
-#define RT946X_SHIFT_FLED_RST	5
-#define RT946X_SHIFT_LDO_RST	4
-#define RT946X_SHIFT_RGB_RST	3
-#define RT946X_SHIFT_BL_RST	2
-#define RT946X_SHIFT_DB_RST	1
-#define RT946X_SHIFT_REG_RST	0
-
-#define RT946X_MASK_RST		BIT(RT946X_SHIFT_RST)
-#define RT946X_MASK_CHG_RST	BIT(RT946X_SHIFT_CHG_RST)
-#define RT946X_MASK_FLED_RST	BIT(RT946X_SHIFT_FLED_RST)
-#define RT946X_MASK_LDO_RST	BIT(RT946X_SHIFT_LDO_RST)
-#define RT946X_MASK_RGB_RST	BIT(RT946X_SHIFT_RGB_RST)
-#define RT946X_MASK_BL_RST	BIT(RT946X_SHIFT_BL_RST)
-#define RT946X_MASK_DB_RST	BIT(RT946X_SHIFT_DB_RST)
-#define RT946X_MASK_REG_RST	BIT(RT946X_SHIFT_REG_RST)
-#define RT946X_MASK_SOFT_RST                                                   \
-	(RT946X_MASK_CHG_RST | RT946X_MASK_FLED_RST | RT946X_MASK_LDO_RST |    \
-	 RT946X_MASK_RGB_RST | RT946X_MASK_BL_RST | RT946X_MASK_DB_RST |       \
+#define RT946X_SHIFT_RST 7
+#define RT946X_SHIFT_CHG_RST 6
+#define RT946X_SHIFT_FLED_RST 5
+#define RT946X_SHIFT_LDO_RST 4
+#define RT946X_SHIFT_RGB_RST 3
+#define RT946X_SHIFT_BL_RST 2
+#define RT946X_SHIFT_DB_RST 1
+#define RT946X_SHIFT_REG_RST 0
+
+#define RT946X_MASK_RST BIT(RT946X_SHIFT_RST)
+#define RT946X_MASK_CHG_RST BIT(RT946X_SHIFT_CHG_RST)
+#define RT946X_MASK_FLED_RST BIT(RT946X_SHIFT_FLED_RST)
+#define RT946X_MASK_LDO_RST BIT(RT946X_SHIFT_LDO_RST)
+#define RT946X_MASK_RGB_RST BIT(RT946X_SHIFT_RGB_RST)
+#define RT946X_MASK_BL_RST BIT(RT946X_SHIFT_BL_RST)
+#define RT946X_MASK_DB_RST BIT(RT946X_SHIFT_DB_RST)
+#define RT946X_MASK_REG_RST BIT(RT946X_SHIFT_REG_RST)
+#define RT946X_MASK_SOFT_RST                                                \
+	(RT946X_MASK_CHG_RST | RT946X_MASK_FLED_RST | RT946X_MASK_LDO_RST | \
+	 RT946X_MASK_RGB_RST | RT946X_MASK_BL_RST | RT946X_MASK_DB_RST |    \
 	 RT946X_MASK_REG_RST)
 
 /* ========== CHGCTRL1 0x01 ============ */
-#define RT946X_SHIFT_OPA_MODE   0
-#define RT946X_SHIFT_HZ_EN      2
-#define RT946X_SHIFT_STAT_EN	4
+#define RT946X_SHIFT_OPA_MODE 0
+#define RT946X_SHIFT_HZ_EN 2
+#define RT946X_SHIFT_STAT_EN 4
 
-#define RT946X_MASK_OPA_MODE	BIT(RT946X_SHIFT_OPA_MODE)
-#define RT946X_MASK_HZ_EN	BIT(RT946X_SHIFT_HZ_EN)
-#define RT946X_MASK_STAT_EN	BIT(RT946X_SHIFT_STAT_EN)
+#define RT946X_MASK_OPA_MODE BIT(RT946X_SHIFT_OPA_MODE)
+#define RT946X_MASK_HZ_EN BIT(RT946X_SHIFT_HZ_EN)
+#define RT946X_MASK_STAT_EN BIT(RT946X_SHIFT_STAT_EN)
 
 /* ========== CHGCTRL2 0x02 ============ */
-#define RT946X_SHIFT_SHIP_MODE		7
-#define RT946X_SHIFT_BATDET_DIS_DLY	6
-#define RT946X_SHIFT_TE			4
-#define RT946X_SHIFT_ILMTSEL		2
-#define RT946X_SHIFT_CFO_EN		1
-#define RT946X_SHIFT_CHG_EN		0
-
-#define RT946X_MASK_SHIP_MODE	BIT(RT946X_SHIFT_SHIP_MODE)
-#define RT946X_MASK_TE		BIT(RT946X_SHIFT_TE)
-#define RT946X_MASK_ILMTSEL	(0x3 << RT946X_SHIFT_ILMTSEL)
-#define RT946X_MASK_CFO_EN	BIT(RT946X_SHIFT_CFO_EN)
-#define RT946X_MASK_CHG_EN	BIT(RT946X_SHIFT_CHG_EN)
+#define RT946X_SHIFT_SHIP_MODE 7
+#define RT946X_SHIFT_BATDET_DIS_DLY 6
+#define RT946X_SHIFT_TE 4
+#define RT946X_SHIFT_ILMTSEL 2
+#define RT946X_SHIFT_CFO_EN 1
+#define RT946X_SHIFT_CHG_EN 0
+
+#define RT946X_MASK_SHIP_MODE BIT(RT946X_SHIFT_SHIP_MODE)
+#define RT946X_MASK_TE BIT(RT946X_SHIFT_TE)
+#define RT946X_MASK_ILMTSEL (0x3 << RT946X_SHIFT_ILMTSEL)
+#define RT946X_MASK_CFO_EN BIT(RT946X_SHIFT_CFO_EN)
+#define RT946X_MASK_CHG_EN BIT(RT946X_SHIFT_CHG_EN)
 
 /* ========== RSTPASCODE1 0x03 (mt6370) ============ */
-#define MT6370_MASK_RSTPASCODE1	0xA9
+#define MT6370_MASK_RSTPASCODE1 0xA9
 
 /* ========== CHGCTRL3 0x03 ============ */
-#define RT946X_SHIFT_AICR	2
-#define RT946X_SHIFT_ILIMEN	0
+#define RT946X_SHIFT_AICR 2
+#define RT946X_SHIFT_ILIMEN 0
 
-#define RT946X_MASK_AICR	(0x3F << RT946X_SHIFT_AICR)
-#define RT946X_MASK_ILIMEN	BIT(RT946X_SHIFT_ILIMEN)
+#define RT946X_MASK_AICR (0x3F << RT946X_SHIFT_AICR)
+#define RT946X_MASK_ILIMEN BIT(RT946X_SHIFT_ILIMEN)
 
 /*
  * The accuracy of AICR is 7%.  So if AICR = 2150,
  * then Max=2150, Typ=2000, Min=1860. And plus 25 since the AICR
  * is 50ma a step.
  */
-#define RT946X_AICR_TYP2MAX(x)	((x) * 107 / 100 + 25)
+#define RT946X_AICR_TYP2MAX(x) ((x)*107 / 100 + 25)
 
 /* ========== RSTPASCODE2 0x04 (mt6370) ============ */
-#define MT6370_MASK_RSTPASCODE2	0x96
+#define MT6370_MASK_RSTPASCODE2 0x96
 
 /* ========== CHGCTRL4 0x04 ============ */
-#define RT946X_SHIFT_CV	1
+#define RT946X_SHIFT_CV 1
 
-#define RT946X_MASK_CV	0xFE
+#define RT946X_MASK_CV 0xFE
 
 /* ========== CHGCTRL5 0x05 ============ */
-#define RT946X_SHIFT_BOOST_VOLTAGE	2
+#define RT946X_SHIFT_BOOST_VOLTAGE 2
 
-#define RT946X_MASK_BOOST_VOLTAGE	0xFC
+#define RT946X_MASK_BOOST_VOLTAGE 0xFC
 
 /* ========== CHGCTRL6 0x06 ============ */
-#define RT946X_SHIFT_MIVR	1
+#define RT946X_SHIFT_MIVR 1
 
-#define RT946X_MASK_MIVR	(0x7F << RT946X_SHIFT_MIVR)
+#define RT946X_MASK_MIVR (0x7F << RT946X_SHIFT_MIVR)
 
 /* ========== CHGCTRL7 0x07 ============ */
-#define RT946X_SHIFT_ICHG	2
+#define RT946X_SHIFT_ICHG 2
 
-#define RT946X_MASK_ICHG	(0x3F << RT946X_SHIFT_ICHG)
+#define RT946X_MASK_ICHG (0x3F << RT946X_SHIFT_ICHG)
 
 /* ========== CHGCTRL8 0x08 ============ */
-#define RT946X_SHIFT_VPREC	4
-#define RT946X_SHIFT_IPREC	0
+#define RT946X_SHIFT_VPREC 4
+#define RT946X_SHIFT_IPREC 0
 
-#define RT946X_MASK_VPREC	(0xF << RT946X_SHIFT_VPREC)
-#define RT946X_MASK_IPREC	(0xF << RT946X_SHIFT_IPREC)
+#define RT946X_MASK_VPREC (0xF << RT946X_SHIFT_VPREC)
+#define RT946X_MASK_IPREC (0xF << RT946X_SHIFT_IPREC)
 
 /* ========== CHGCTRL9 0x09 ============ */
-#define RT946X_SHIFT_EOC	3
-#define RT946X_SHIFT_IEOC	4
+#define RT946X_SHIFT_EOC 3
+#define RT946X_SHIFT_IEOC 4
 
-#define RT946X_MASK_EOC		BIT(RT946X_SHIFT_EOC)
-#define RT946X_MASK_IEOC	(0xF << RT946X_SHIFT_IEOC)
+#define RT946X_MASK_EOC BIT(RT946X_SHIFT_EOC)
+#define RT946X_MASK_IEOC (0xF << RT946X_SHIFT_IEOC)
 
 /* ========== CHGCTRL10 0x0A ============ */
-#define RT946X_SHIFT_BOOST_CURRENT	0
+#define RT946X_SHIFT_BOOST_CURRENT 0
 
-#define RT946X_MASK_BOOST_CURRENT	0x07
+#define RT946X_MASK_BOOST_CURRENT 0x07
 
 /* ========== CHGCTRL12 0x0C ============ */
-#define RT946X_SHIFT_TMR_EN	1
-#define MT6370_IRQ_MASK_ALL	0xFE
+#define RT946X_SHIFT_TMR_EN 1
+#define MT6370_IRQ_MASK_ALL 0xFE
 
-#define RT946X_MASK_TMR_EN	BIT(RT946X_SHIFT_TMR_EN)
+#define RT946X_MASK_TMR_EN BIT(RT946X_SHIFT_TMR_EN)
 
 /* ========== CHGCTRL13 0x0D ============ */
-#define RT946X_SHIFT_WDT_EN	7
+#define RT946X_SHIFT_WDT_EN 7
 
-#define RT946X_MASK_WDT_EN	BIT(RT946X_SHIFT_WDT_EN)
+#define RT946X_MASK_WDT_EN BIT(RT946X_SHIFT_WDT_EN)
 
 /* ========== CHGCTRL14 0x0E ============ */
-#define RT946X_SHIFT_AICLMEAS	7
-#define RT946X_SHIFT_AICLVTH	0
+#define RT946X_SHIFT_AICLMEAS 7
+#define RT946X_SHIFT_AICLVTH 0
 
-#define RT946X_MASK_AICLMEAS	BIT(RT946X_SHIFT_AICLMEAS)
-#define RT946X_MASK_AICLVTH	0x07
+#define RT946X_MASK_AICLMEAS BIT(RT946X_SHIFT_AICLMEAS)
+#define RT946X_MASK_AICLVTH 0x07
 
 /* ========== CHGCTRL16 0x10 ============ */
-#define RT946X_SHIFT_JEITA_EN	4
+#define RT946X_SHIFT_JEITA_EN 4
 
-#define RT946X_MASK_JEITA_EN	BIT(RT946X_SHIFT_JEITA_EN)
+#define RT946X_MASK_JEITA_EN BIT(RT946X_SHIFT_JEITA_EN)
 
 /* ========== CHGADC 0x11 ============ */
-#define RT946X_SHIFT_ADC_IN_SEL	4
-#define RT946X_SHIFT_ADC_START	0
+#define RT946X_SHIFT_ADC_IN_SEL 4
+#define RT946X_SHIFT_ADC_START 0
 
-#define RT946X_MASK_ADC_IN_SEL	(0xF << RT946X_SHIFT_ADC_IN_SEL)
-#define RT946X_MASK_ADC_START	BIT(RT946X_SHIFT_ADC_START)
+#define RT946X_MASK_ADC_IN_SEL (0xF << RT946X_SHIFT_ADC_IN_SEL)
+#define RT946X_MASK_ADC_START BIT(RT946X_SHIFT_ADC_START)
 
 /* ========== CHGDPDM1 0x12 (rt946x) DEVICETYPE 0x22 (mt6370) ============ */
-#define RT946X_SHIFT_USBCHGEN	7
-#define RT946X_SHIFT_DCDTIMEOUT	6
-#define RT946X_SHIFT_DCP	2
-#define RT946X_SHIFT_CDP	1
-#define RT946X_SHIFT_SDP	0
-
-#define RT946X_MASK_USBCHGEN	BIT(RT946X_SHIFT_USBCHGEN)
-#define RT946X_MASK_DCDTIMEOUT	BIT(RT946X_SHIFT_DCDTIMEOUT)
-#define RT946X_MASK_DCP		BIT(RT946X_SHIFT_DCP)
-#define RT946X_MASK_CDP		BIT(RT946X_SHIFT_CDP)
-#define RT946X_MASK_SDP		BIT(RT946X_SHIFT_SDP)
-
-#define RT946X_MASK_BC12_TYPE	(RT946X_MASK_DCP | \
-				 RT946X_MASK_CDP | \
-				 RT946X_MASK_SDP)
+#define RT946X_SHIFT_USBCHGEN 7
+#define RT946X_SHIFT_DCDTIMEOUT 6
+#define RT946X_SHIFT_DCP 2
+#define RT946X_SHIFT_CDP 1
+#define RT946X_SHIFT_SDP 0
+
+#define RT946X_MASK_USBCHGEN BIT(RT946X_SHIFT_USBCHGEN)
+#define RT946X_MASK_DCDTIMEOUT BIT(RT946X_SHIFT_DCDTIMEOUT)
+#define RT946X_MASK_DCP BIT(RT946X_SHIFT_DCP)
+#define RT946X_MASK_CDP BIT(RT946X_SHIFT_CDP)
+#define RT946X_MASK_SDP BIT(RT946X_SHIFT_SDP)
+
+#define RT946X_MASK_BC12_TYPE \
+	(RT946X_MASK_DCP | RT946X_MASK_CDP | RT946X_MASK_SDP)
 
 /* ========== USBSTATUS1 0x27 (mt6370) ============ */
-#define MT6370_SHIFT_DCD_TIMEOUT 	2
-#define MT6370_SHIFT_USB_STATUS		4
+#define MT6370_SHIFT_DCD_TIMEOUT 2
+#define MT6370_SHIFT_USB_STATUS 4
 
-#define MT6370_MASK_USB_STATUS	0x70
+#define MT6370_MASK_USB_STATUS 0x70
 
-#define MT6370_CHG_TYPE_NOVBUS			0
-#define MT6370_CHG_TYPE_BUSY			1
-#define MT6370_CHG_TYPE_SDP			2
-#define MT6370_CHG_TYPE_SDPNSTD			3
-#define MT6370_CHG_TYPE_DCP			4
-#define MT6370_CHG_TYPE_CDP			5
-#define MT6370_CHG_TYPE_SAMSUNG_CHARGER		6
-#define MT6370_CHG_TYPE_APPLE_0_5A_CHARGER	7
-#define MT6370_CHG_TYPE_APPLE_1_0A_CHARGER	8
-#define MT6370_CHG_TYPE_APPLE_2_1A_CHARGER	9
-#define MT6370_CHG_TYPE_APPLE_2_4A_CHARGER	10
+#define MT6370_CHG_TYPE_NOVBUS 0
+#define MT6370_CHG_TYPE_BUSY 1
+#define MT6370_CHG_TYPE_SDP 2
+#define MT6370_CHG_TYPE_SDPNSTD 3
+#define MT6370_CHG_TYPE_DCP 4
+#define MT6370_CHG_TYPE_CDP 5
+#define MT6370_CHG_TYPE_SAMSUNG_CHARGER 6
+#define MT6370_CHG_TYPE_APPLE_0_5A_CHARGER 7
+#define MT6370_CHG_TYPE_APPLE_1_0A_CHARGER 8
+#define MT6370_CHG_TYPE_APPLE_2_1A_CHARGER 9
+#define MT6370_CHG_TYPE_APPLE_2_4A_CHARGER 10
 
-#define MT6370_MASK_DCD_TIMEOUT		BIT(MT6370_SHIFT_DCD_TIMEOUT)
+#define MT6370_MASK_DCD_TIMEOUT BIT(MT6370_SHIFT_DCD_TIMEOUT)
 
 /* ========== QCSTATUS2 0x29 (mt6370) ============ */
-#define MT6370_SHIFT_APP_OUT		5
-#define MT6370_SHIFT_SS_OUT		4
-#define MT6370_SHIFT_APP_REF		3
-#define MT6370_SHIFT_APP_DPDM_IN	2
-#define MT6370_SHIFT_APP_SS_PL		1
-#define MT6370_SHIFT_APP_SS_EN		0
-
-#define MT6370_MASK_APP_OUT	BIT(MT6370_SHIFT_APP_OUT)
-#define MT6370_MASK_SS_OUT	BIT(MT6370_SHIFT_SS_OUT)
-#define MT6370_MASK_APP_REF	BIT(MT6370_SHIFT_APP_REF)
-#define MT6370_MASK_APP_DPDM_IN	BIT(MT6370_SHIFT_APP_DPDM_IN)
-#define MT6370_MASK_APP_SS_PL	BIT(MT6370_SHIFT_APP_SS_PL)
-#define MT6370_MASK_APP_SS_EN	BIT(MT6370_SHIFT_APP_SS_EN)
-
-#define MT6360_MASK_CHECK_DPDM	(MT6370_MASK_APP_SS_EN | \
-				MT6370_MASK_APP_SS_PL | \
-				MT6370_MASK_APP_DPDM_IN | \
-				MT6370_MASK_APP_REF)
+#define MT6370_SHIFT_APP_OUT 5
+#define MT6370_SHIFT_SS_OUT 4
+#define MT6370_SHIFT_APP_REF 3
+#define MT6370_SHIFT_APP_DPDM_IN 2
+#define MT6370_SHIFT_APP_SS_PL 1
+#define MT6370_SHIFT_APP_SS_EN 0
+
+#define MT6370_MASK_APP_OUT BIT(MT6370_SHIFT_APP_OUT)
+#define MT6370_MASK_SS_OUT BIT(MT6370_SHIFT_SS_OUT)
+#define MT6370_MASK_APP_REF BIT(MT6370_SHIFT_APP_REF)
+#define MT6370_MASK_APP_DPDM_IN BIT(MT6370_SHIFT_APP_DPDM_IN)
+#define MT6370_MASK_APP_SS_PL BIT(MT6370_SHIFT_APP_SS_PL)
+#define MT6370_MASK_APP_SS_EN BIT(MT6370_SHIFT_APP_SS_EN)
+
+#define MT6360_MASK_CHECK_DPDM                           \
+	(MT6370_MASK_APP_SS_EN | MT6370_MASK_APP_SS_PL | \
+	 MT6370_MASK_APP_DPDM_IN | MT6370_MASK_APP_REF)
 
 /* ========= CHGHIDDENCTRL7 0x36 (mt6370) ======== */
-#define RT946X_ENABLE_VSYS_PROTECT		0x40
+#define RT946X_ENABLE_VSYS_PROTECT 0x40
 
-#define RT946X_SHIFT_HIDDENCTRL7_VSYS_PROTECT	5
+#define RT946X_SHIFT_HIDDENCTRL7_VSYS_PROTECT 5
 #define RT946X_MASK_HIDDENCTRL7_VSYS_PROTECT \
 	(0x3 << RT946X_SHIFT_HIDDENCTRL7_VSYS_PROTECT)
 
 /* ========== CHGCTRL18 0x1A ============ */
-#define RT946X_SHIFT_IRCMP_RES		3
-#define RT946X_SHIFT_IRCMP_VCLAMP	0
+#define RT946X_SHIFT_IRCMP_RES 3
+#define RT946X_SHIFT_IRCMP_VCLAMP 0
 
-#define RT946X_MASK_IRCMP_RES		(0x7 << RT946X_SHIFT_IRCMP_RES)
-#define RT946X_MASK_IRCMP_VCLAMP	(0x7 << RT946X_SHIFT_IRCMP_VCLAMP)
+#define RT946X_MASK_IRCMP_RES (0x7 << RT946X_SHIFT_IRCMP_RES)
+#define RT946X_MASK_IRCMP_VCLAMP (0x7 << RT946X_SHIFT_IRCMP_VCLAMP)
 
 /* ========== HIDDEN CTRL15 0x3E ============ */
-#define MT6370_SHIFT_ADC_TS_AUTO	0
-#define MT6370_MASK_ADC_TS_AUTO		BIT(MT6370_SHIFT_ADC_TS_AUTO)
+#define MT6370_SHIFT_ADC_TS_AUTO 0
+#define MT6370_MASK_ADC_TS_AUTO BIT(MT6370_SHIFT_ADC_TS_AUTO)
 
 /* ========== DEVICE_ID 0x40 ============ */
-#define RT946X_MASK_VENDOR_ID	0xF0
-#define RT946X_MASK_CHIP_REV	0x0F
+#define RT946X_MASK_VENDOR_ID 0xF0
+#define RT946X_MASK_CHIP_REV 0x0F
 
 /* ========== CHGSTAT 0x42 ============ */
-#define RT946X_SHIFT_CHG_STAT	6
-#define RT946X_SHIFT_ADC_STAT	0
+#define RT946X_SHIFT_CHG_STAT 6
+#define RT946X_SHIFT_ADC_STAT 0
 
-#define RT946X_MASK_CHG_STAT	(0x3 << RT946X_SHIFT_CHG_STAT)
-#define RT946X_MASK_ADC_STAT	BIT(RT946X_SHIFT_ADC_STAT)
+#define RT946X_MASK_CHG_STAT (0x3 << RT946X_SHIFT_CHG_STAT)
+#define RT946X_MASK_ADC_STAT BIT(RT946X_SHIFT_ADC_STAT)
 
 /* ========== CHGNTC 0x43 ============ */
-#define RT946X_SHIFT_BATNTC_FAULT	4
+#define RT946X_SHIFT_BATNTC_FAULT 4
 
-#define RT946X_MASK_BATNTC_FAULT	0x70
+#define RT946X_MASK_BATNTC_FAULT 0x70
 
 /* ========== CHGSTATC 0x50 (rt946x) ============ */
-#define RT946X_SHIFT_PWR_RDY    7
+#define RT946X_SHIFT_PWR_RDY 7
 
-#define RT946X_MASK_PWR_RDY     BIT(RT946X_SHIFT_PWR_RDY)
+#define RT946X_MASK_PWR_RDY BIT(RT946X_SHIFT_PWR_RDY)
 
 /* ========== CHGFAULT 0x51 (rt946x) ============ */
 #if defined(CONFIG_CHARGER_RT9466) || defined(CONFIG_CHARGER_RT9467)
-#define RT946X_SHIFT_CHG_VSYSUV	4
-#define RT946X_SHIFT_CHG_VSYSOV	5
-#define RT946X_SHIFT_CHG_VBATOV	6
-#define RT946X_SHIFT_CHG_VBUSOV	7
-
-#define RT946X_MASK_CHG_VSYSUV	BIT(RT946X_SHIFT_CHG_VSYSUV)
-#define RT946X_MASK_CHG_VSYSOV	BIT(RT946X_SHIFT_CHG_VSYSOV)
-#define RT946X_MASK_CHG_VBATOV	BIT(RT946X_SHIFT_CHG_VBATOV)
-#define RT946X_MASK_CHG_VBUSOV	BIT(RT946X_SHIFT_CHG_VBUSOV)
+#define RT946X_SHIFT_CHG_VSYSUV 4
+#define RT946X_SHIFT_CHG_VSYSOV 5
+#define RT946X_SHIFT_CHG_VBATOV 6
+#define RT946X_SHIFT_CHG_VBUSOV 7
+
+#define RT946X_MASK_CHG_VSYSUV BIT(RT946X_SHIFT_CHG_VSYSUV)
+#define RT946X_MASK_CHG_VSYSOV BIT(RT946X_SHIFT_CHG_VSYSOV)
+#define RT946X_MASK_CHG_VBATOV BIT(RT946X_SHIFT_CHG_VBATOV)
+#define RT946X_MASK_CHG_VBUSOV BIT(RT946X_SHIFT_CHG_VBUSOV)
 #endif
 
 /* ========== DPDMIRQ 0x56 ============ */
 #if defined(CONFIG_CHARGER_RT9467) || defined(CONFIG_CHARGER_MT6370)
-#define RT946X_SHIFT_DPDMIRQ_DETACH	1
-#define RT946X_SHIFT_DPDMIRQ_ATTACH	0
+#define RT946X_SHIFT_DPDMIRQ_DETACH 1
+#define RT946X_SHIFT_DPDMIRQ_ATTACH 0
 
-#define RT946X_MASK_DPDMIRQ_DETACH	BIT(RT946X_SHIFT_DPDMIRQ_DETACH)
-#define RT946X_MASK_DPDMIRQ_ATTACH	BIT(RT946X_SHIFT_DPDMIRQ_ATTACH)
+#define RT946X_MASK_DPDMIRQ_DETACH BIT(RT946X_SHIFT_DPDMIRQ_DETACH)
+#define RT946X_MASK_DPDMIRQ_ATTACH BIT(RT946X_SHIFT_DPDMIRQ_ATTACH)
 #endif
 
 /* ========== FLED EN 0x7E (mt6370) ============ */
-#define MT6370_STROBE_EN_MASK		0x04
+#define MT6370_STROBE_EN_MASK 0x04
 
 /* ========== LDOCFG 0x80 (mt6370) ============ */
-#define MT6370_SHIFT_LDOCFG_OMS	6
+#define MT6370_SHIFT_LDOCFG_OMS 6
 
-#define MT6370_MASK_LDOCFG_OMS		BIT(MT6370_SHIFT_LDOCFG_OMS)
+#define MT6370_MASK_LDOCFG_OMS BIT(MT6370_SHIFT_LDOCFG_OMS)
 
 /* ========== LDOVOUT 0x81 (mt6370) ============ */
-#define MT6370_SHIFT_LDOVOUT_EN		7
-#define MT6370_SHIFT_LDOVOUT_VOUT	0
+#define MT6370_SHIFT_LDOVOUT_EN 7
+#define MT6370_SHIFT_LDOVOUT_VOUT 0
 
-#define MT6370_MASK_LDOVOUT_EN		BIT(MT6370_SHIFT_LDOVOUT_EN)
-#define MT6370_MASK_LDOVOUT_VOUT	(0xf << MT6370_SHIFT_LDOVOUT_VOUT)
+#define MT6370_MASK_LDOVOUT_EN BIT(MT6370_SHIFT_LDOVOUT_EN)
+#define MT6370_MASK_LDOVOUT_VOUT (0xf << MT6370_SHIFT_LDOVOUT_VOUT)
 
 /* ========== RGBDIM 0x82/0x83/0x84 (mt6370) ============ */
-#define MT6370_LED_PWM_DIMDUTY_MIN	0x00
-#define MT6370_LED_PWM_DIMDUTY_MAX	0x1f
+#define MT6370_LED_PWM_DIMDUTY_MIN 0x00
+#define MT6370_LED_PWM_DIMDUTY_MAX 0x1f
 
-#define MT6370_SHIFT_RGB_DIMMODE	5
-#define MT6370_SHIFT_RGB_DIMDUTY	0
+#define MT6370_SHIFT_RGB_DIMMODE 5
+#define MT6370_SHIFT_RGB_DIMDUTY 0
 
-#define MT6370_MASK_RGB_DIMMODE		(3 << MT6370_SHIFT_RGB_DIMMODE)
-#define MT6370_MASK_RGB_DIMDUTY		(0x1f << MT6370_SHIFT_RGB_DIMDUTY)
+#define MT6370_MASK_RGB_DIMMODE (3 << MT6370_SHIFT_RGB_DIMMODE)
+#define MT6370_MASK_RGB_DIMDUTY (0x1f << MT6370_SHIFT_RGB_DIMDUTY)
 
 /* ========== RGBEN 0x85 (mt6370) ============ */
-#define MT6370_SHIFT_RGB_ISNK1DIM	7
-#define MT6370_SHIFT_RGB_ISNK2DIM	6
-#define MT6370_SHIFT_RGB_ISNK3DIM	5
-#define MT6370_SHIFT_RGB_ISNKDIM_BASE	8
-
-#define MT6370_MASK_RGB_ISNK1DIM_EN	BIT(MT6370_SHIFT_RGB_ISNK1DIM)
-#define MT6370_MASK_RGB_ISNK2DIM_EN	BIT(MT6370_SHIFT_RGB_ISNK2DIM)
-#define MT6370_MASK_RGB_ISNK3DIM_EN	BIT(MT6370_SHIFT_RGB_ISNK3DIM)
-#define MT6370_MASK_RGB_ISNK_ALL_EN	(MT6370_MASK_RGB_ISNK1DIM_EN | \
-					 MT6370_MASK_RGB_ISNK2DIM_EN | \
-					 MT6370_MASK_RGB_ISNK3DIM_EN)
+#define MT6370_SHIFT_RGB_ISNK1DIM 7
+#define MT6370_SHIFT_RGB_ISNK2DIM 6
+#define MT6370_SHIFT_RGB_ISNK3DIM 5
+#define MT6370_SHIFT_RGB_ISNKDIM_BASE 8
+
+#define MT6370_MASK_RGB_ISNK1DIM_EN BIT(MT6370_SHIFT_RGB_ISNK1DIM)
+#define MT6370_MASK_RGB_ISNK2DIM_EN BIT(MT6370_SHIFT_RGB_ISNK2DIM)
+#define MT6370_MASK_RGB_ISNK3DIM_EN BIT(MT6370_SHIFT_RGB_ISNK3DIM)
+#define MT6370_MASK_RGB_ISNK_ALL_EN                                  \
+	(MT6370_MASK_RGB_ISNK1DIM_EN | MT6370_MASK_RGB_ISNK2DIM_EN | \
+	 MT6370_MASK_RGB_ISNK3DIM_EN)
 
 /* ========== RGB_ISNK 0x86/0x87/0x88 (mt6370) ============ */
 #define MT6370_LED_BRIGHTNESS_MIN 0
 #define MT6370_LED_BRIGHTNESS_MAX 7
 
-#define MT6370_SHIFT_RGBISNK_CURSEL	0
-#define MT6370_SHIFT_RGBISNK_DIMFSEL	3
-#define MT6370_MASK_RGBISNK_CURSEL	(0x7 << MT6370_SHIFT_RGBISNK_CURSEL)
-#define MT6370_MASK_RGBISNK_DIMFSEL	(0x7 << MT6370_SHIFT_RGBISNK_DIMFSEL)
+#define MT6370_SHIFT_RGBISNK_CURSEL 0
+#define MT6370_SHIFT_RGBISNK_DIMFSEL 3
+#define MT6370_MASK_RGBISNK_CURSEL (0x7 << MT6370_SHIFT_RGBISNK_CURSEL)
+#define MT6370_MASK_RGBISNK_DIMFSEL (0x7 << MT6370_SHIFT_RGBISNK_DIMFSEL)
 
 /* ========== DBCTRL1 (mt6370) ============ */
-#define MT6370_SHIFT_DB_EXT_EN		0
-#define MT6370_SHIFT_DB_PERIODIC_FIX	4
-#define MT6370_SHIFT_DB_SINGLE_PIN	5
-#define MT6370_SHIFT_DB_FREQ_PM		6
-#define MT6370_SHIFT_DB_PERIODIC_MODE	7
-
-#define MT6370_MASK_DB_EXT_EN		1
-#define MT6370_MASK_DB_PERIODIC_FIX	1
-#define MT6370_MASK_DB_SINGLE_PIN	1
-#define MT6370_MASK_DB_FREQ_PM		1
-#define MT6370_MASK_DB_PERIODIC_MODE	1
+#define MT6370_SHIFT_DB_EXT_EN 0
+#define MT6370_SHIFT_DB_PERIODIC_FIX 4
+#define MT6370_SHIFT_DB_SINGLE_PIN 5
+#define MT6370_SHIFT_DB_FREQ_PM 6
+#define MT6370_SHIFT_DB_PERIODIC_MODE 7
+
+#define MT6370_MASK_DB_EXT_EN 1
+#define MT6370_MASK_DB_PERIODIC_FIX 1
+#define MT6370_MASK_DB_SINGLE_PIN 1
+#define MT6370_MASK_DB_FREQ_PM 1
+#define MT6370_MASK_DB_PERIODIC_MODE 1
 
 /* ========== DBCTRL1 (mt6370) ============ */
-#define MT6370_MASK_DB_VNEG_DISC	BIT(2)
-#define MT6370_MASK_DB_VPOS_DISC	BIT(5)
+#define MT6370_MASK_DB_VNEG_DISC BIT(2)
+#define MT6370_MASK_DB_VPOS_DISC BIT(5)
 
 /* ========== DBVBST (mt6370) ============ */
-#define MT6370_SHIFT_DB_VBST		0
+#define MT6370_SHIFT_DB_VBST 0
 
-#define MT6370_MASK_DB_VBST		0x3f
+#define MT6370_MASK_DB_VBST 0x3f
 
-#define MT6370_DB_VBST_MAX		6200
-#define MT6370_DB_VBST_MIN		4000
-#define MT6370_DB_VBST_STEP		50
+#define MT6370_DB_VBST_MAX 6200
+#define MT6370_DB_VBST_MIN 4000
+#define MT6370_DB_VBST_STEP 50
 
 /* ========== DBVPOS (mt6370) ============ */
-#define MT6370_SHIFT_DB_VPOS		0
+#define MT6370_SHIFT_DB_VPOS 0
 
-#define MT6370_MASK_DB_VPOS		0x3f
+#define MT6370_MASK_DB_VPOS 0x3f
 
-#define MT6370_DB_VPOS_MAX		6000
-#define MT6370_DB_VPOS_MIN		4000
-#define MT6370_DB_VPOS_STEP		50
+#define MT6370_DB_VPOS_MAX 6000
+#define MT6370_DB_VPOS_MIN 4000
+#define MT6370_DB_VPOS_STEP 50
 
 /* ========== DBVNEG (mt6370) ============ */
-#define MT6370_SHIFT_DB_VNEG		0
+#define MT6370_SHIFT_DB_VNEG 0
 
-#define MT6370_MASK_DB_VNEG		0x3f
+#define MT6370_MASK_DB_VNEG 0x3f
 
-#define MT6370_DB_VNEG_MAX		6000
-#define MT6370_DB_VNEG_MIN		4000
-#define MT6370_DB_VNEG_STEP		50
+#define MT6370_DB_VNEG_MAX 6000
+#define MT6370_DB_VNEG_MIN 4000
+#define MT6370_DB_VNEG_STEP 50
 
 /* ========== BLEN 0xA0 (mt6370) ============ */
-#define MT6370_SHIFT_BLED_EXT_EN	7
-#define MT6370_SHIFT_BLED_EN		6
-#define MT6370_SHIFT_BLED_1CH_EN	5
-#define MT6370_SHIFT_BLED_2CH_EN	4
-#define MT6370_SHIFT_BLED_3CH_EN	3
-#define MT6370_SHIFT_BLED_4CH_EN	2
-#define MT6370_SHIFT_BLED_CODE		1
-#define MT6370_SHIFT_BLED_CONFIG	0
-
-#define MT6370_MASK_BLED_EXT_EN		BIT(MT6370_SHIFT_BLED_EXT_EN)
-#define MT6370_MASK_BLED_EN		BIT(MT6370_SHIFT_BLED_EN)
-#define MT6370_MASK_BLED_1CH_EN		BIT(MT6370_SHIFT_BLED_1CH_EN)
-#define MT6370_MASK_BLED_2CH_EN		BIT(MT6370_SHIFT_BLED_2CH_EN)
-#define MT6370_MASK_BLED_3CH_EN		BIT(MT6370_SHIFT_BLED_3CH_EN)
-#define MT6370_MASK_BLED_4CH_EN		BIT(MT6370_SHIFT_BLED_4CH_EN)
-
-#define MT6370_BLED_CODE_LINEAR		BIT(MT6370_SHIFT_BLED_CODE)
-#define MT6370_BLED_CODE_EXP		0
-
-#define MT6370_BLED_CONFIG_ACTIVE_HIGH	BIT(MT6370_SHIFT_BLED_CONFIG)
-#define MT6370_BLED_CONFIG_ACTIVE_LOW	0
+#define MT6370_SHIFT_BLED_EXT_EN 7
+#define MT6370_SHIFT_BLED_EN 6
+#define MT6370_SHIFT_BLED_1CH_EN 5
+#define MT6370_SHIFT_BLED_2CH_EN 4
+#define MT6370_SHIFT_BLED_3CH_EN 3
+#define MT6370_SHIFT_BLED_4CH_EN 2
+#define MT6370_SHIFT_BLED_CODE 1
+#define MT6370_SHIFT_BLED_CONFIG 0
+
+#define MT6370_MASK_BLED_EXT_EN BIT(MT6370_SHIFT_BLED_EXT_EN)
+#define MT6370_MASK_BLED_EN BIT(MT6370_SHIFT_BLED_EN)
+#define MT6370_MASK_BLED_1CH_EN BIT(MT6370_SHIFT_BLED_1CH_EN)
+#define MT6370_MASK_BLED_2CH_EN BIT(MT6370_SHIFT_BLED_2CH_EN)
+#define MT6370_MASK_BLED_3CH_EN BIT(MT6370_SHIFT_BLED_3CH_EN)
+#define MT6370_MASK_BLED_4CH_EN BIT(MT6370_SHIFT_BLED_4CH_EN)
+
+#define MT6370_BLED_CODE_LINEAR BIT(MT6370_SHIFT_BLED_CODE)
+#define MT6370_BLED_CODE_EXP 0
+
+#define MT6370_BLED_CONFIG_ACTIVE_HIGH BIT(MT6370_SHIFT_BLED_CONFIG)
+#define MT6370_BLED_CONFIG_ACTIVE_LOW 0
 
 /* ========== BLPWM 0xA2 (mt6370) ============ */
-#define MT6370_SHIFT_BLPWM_BLED_PWM	7
+#define MT6370_SHIFT_BLPWM_BLED_PWM 7
 
-#define MT6370_MASK_BLPWM_BLED_PWM	BIT(MT6370_SHIFT_BLPWM_BLED_PWM)
+#define MT6370_MASK_BLPWM_BLED_PWM BIT(MT6370_SHIFT_BLPWM_BLED_PWM)
 
 /* ========== BLDIM2 0xA4 (mt6370) ============ */
-#define MT6370_MASK_BLDIM2		0x7
+#define MT6370_MASK_BLDIM2 0x7
 
 /* ========== BLDIM 0xA5 (mt6370) ============ */
-#define MT6370_SHIFT_BLDIM_MSB		3
-#define MT6370_MASK_BLDIM		0xff
+#define MT6370_SHIFT_BLDIM_MSB 3
+#define MT6370_MASK_BLDIM 0xff
 
-#define MT6370_BLDIM_DEFAULT		0x7ff
+#define MT6370_BLDIM_DEFAULT 0x7ff
 
 /* ========== CHG_IRQ1 0xC0 (mt6370) ============ */
-#define MT6370_SHIFT_MIVR_EVT		6
-#define MT6370_MASK_MIVR_EVT		BIT(MT6370_SHIFT_MIVR_EVT)
+#define MT6370_SHIFT_MIVR_EVT 6
+#define MT6370_MASK_MIVR_EVT BIT(MT6370_SHIFT_MIVR_EVT)
 
 /* ========== CHGSTAT2 0xD0 (mt6370) ============ */
-#define MT6370_SHIFT_MIVR_STAT		6
+#define MT6370_SHIFT_MIVR_STAT 6
 
 /* ========== CHGSTAT2 0xD1 (mt6370) ============ */
 #ifdef CONFIG_CHARGER_MT6370
-#define MT6370_SHIFT_CHG_VBUSOV_STAT	7
-#define MT6370_SHIFT_CHG_VBATOV_STAT	6
+#define MT6370_SHIFT_CHG_VBUSOV_STAT 7
+#define MT6370_SHIFT_CHG_VBATOV_STAT 6
 
-#define RT946X_MASK_CHG_VBATOV		MT6370_SHIFT_CHG_VBATOV_STAT
+#define RT946X_MASK_CHG_VBATOV MT6370_SHIFT_CHG_VBATOV_STAT
 
-#define MT6370_MASK_CHG_VBUSOV_STAT	BIT(MT6370_SHIFT_CHG_VBUSOV_STAT)
-#define MT6370_MASK_CHG_VBATOV_STAT	BIT(MT6370_SHIFT_CHG_VBATOV_STAT)
+#define MT6370_MASK_CHG_VBUSOV_STAT BIT(MT6370_SHIFT_CHG_VBUSOV_STAT)
+#define MT6370_MASK_CHG_VBATOV_STAT BIT(MT6370_SHIFT_CHG_VBATOV_STAT)
 #endif
 
 /* ========== TM PAS CODE1 0xF0 (mt6370) ============ */
-#define MT6370_LEAVE_TM			0x00
+#define MT6370_LEAVE_TM 0x00
 
 /* ========== BANK REG 0xFF (mt6370) ============ */
-#define MT6370_MASK_REG_TM		0x69
+#define MT6370_MASK_REG_TM 0x69
 
 /* ========== TM REG 0x34 (mt6370) ============ */
-#define MT6370_TM_MASK_BL3_SL		0xC0
-#define MT6370_TM_REDUCE_BL3_SL		0xC0
+#define MT6370_TM_MASK_BL3_SL 0xC0
+#define MT6370_TM_REDUCE_BL3_SL 0xC0
 
 /* ========== TM REG 0x37 (mt6370) ============ */
-#define MT6370_TM_MASK_DSV1_SL		0xC0
-#define MT6370_TM_REDUCE_DSV1_SL	0x00
+#define MT6370_TM_MASK_DSV1_SL 0xC0
+#define MT6370_TM_REDUCE_DSV1_SL 0x00
 
 /* ADC unit/offset */
-#define MT6370_ADC_UNIT_VBUS_DIV5	25000	/* uV */
-#define MT6370_ADC_UNIT_VBUS_DIV2	10000	/* uV */
-#define MT6370_ADC_UNIT_VSYS		5000	/* uV */
-#define MT6370_ADC_UNIT_VBAT		5000	/* uV */
-#define MT6370_ADC_UNIT_TS_BAT		25	/* 0.01% */
-#define MT6370_ADC_UNIT_IBUS		50000	/* uA */
-#define MT6370_ADC_UNIT_IBAT		50000	/* uA */
-#define MT6370_ADC_UNIT_CHG_VDDP	5000	/* uV */
-#define MT6370_ADC_UNIT_TEMP_JC		2	/* degree */
-
-#define MT6370_ADC_OFFSET_VBUS_DIV5	0	/* mV */
-#define MT6370_ADC_OFFSET_VBUS_DIV2	0	/* mV */
-#define MT6370_ADC_OFFSET_VSYS		0	/* mV */
-#define MT6370_ADC_OFFSET_VBAT		0	/* mV */
-#define MT6370_ADC_OFFSET_TS_BAT	0	/* % */
-#define MT6370_ADC_OFFSET_IBUS		0	/* mA */
-#define MT6370_ADC_OFFSET_IBAT		0	/* mA */
-#define MT6370_ADC_OFFSET_CHG_VDDP	0	/* mV */
-#define MT6370_ADC_OFFSET_TEMP_JC	(-40)	/* degree */
+#define MT6370_ADC_UNIT_VBUS_DIV5 25000 /* uV */
+#define MT6370_ADC_UNIT_VBUS_DIV2 10000 /* uV */
+#define MT6370_ADC_UNIT_VSYS 5000 /* uV */
+#define MT6370_ADC_UNIT_VBAT 5000 /* uV */
+#define MT6370_ADC_UNIT_TS_BAT 25 /* 0.01% */
+#define MT6370_ADC_UNIT_IBUS 50000 /* uA */
+#define MT6370_ADC_UNIT_IBAT 50000 /* uA */
+#define MT6370_ADC_UNIT_CHG_VDDP 5000 /* uV */
+#define MT6370_ADC_UNIT_TEMP_JC 2 /* degree */
+
+#define MT6370_ADC_OFFSET_VBUS_DIV5 0 /* mV */
+#define MT6370_ADC_OFFSET_VBUS_DIV2 0 /* mV */
+#define MT6370_ADC_OFFSET_VSYS 0 /* mV */
+#define MT6370_ADC_OFFSET_VBAT 0 /* mV */
+#define MT6370_ADC_OFFSET_TS_BAT 0 /* % */
+#define MT6370_ADC_OFFSET_IBUS 0 /* mA */
+#define MT6370_ADC_OFFSET_IBAT 0 /* mA */
+#define MT6370_ADC_OFFSET_CHG_VDDP 0 /* mV */
+#define MT6370_ADC_OFFSET_TEMP_JC (-40) /* degree */
 
 /* ========== Variant-specific configuration ============ */
 #if defined(CONFIG_CHARGER_RT9466)
-	#define RT946X_CHARGER_NAME	"rt9466"
-	#define RT946X_VENDOR_ID	0x80
-	#define RT946X_ADDR_FLAGS	0x53
+#define RT946X_CHARGER_NAME "rt9466"
+#define RT946X_VENDOR_ID 0x80
+#define RT946X_ADDR_FLAGS 0x53
 #elif defined(CONFIG_CHARGER_RT9467)
-	#define RT946X_CHARGER_NAME	"rt9467"
-	#define RT946X_VENDOR_ID	0x90
-	#define RT946X_ADDR_FLAGS	0x5B
+#define RT946X_CHARGER_NAME "rt9467"
+#define RT946X_VENDOR_ID 0x90
+#define RT946X_ADDR_FLAGS 0x5B
 #elif defined(CONFIG_CHARGER_MT6370)
-	#define RT946X_CHARGER_NAME	"mt6370"
-	#define RT946X_VENDOR_ID	0xE0
-	#define RT946X_ADDR_FLAGS	0x34
+#define RT946X_CHARGER_NAME "mt6370"
+#define RT946X_VENDOR_ID 0xE0
+#define RT946X_ADDR_FLAGS 0x34
 #else
-	#error "No suitable charger option defined"
+#error "No suitable charger option defined"
 #endif
 
 /* RT946x specific interface functions */
diff --git a/driver/charger/rt9490.c b/driver/charger/rt9490.c
index 2d69e843e9..a1c73c47d5 100644
--- a/driver/charger/rt9490.c
+++ b/driver/charger/rt9490.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -7,6 +7,7 @@
 
 #include "battery.h"
 #include "battery_smart.h"
+#include "builtin/assert.h"
 #include "builtin/endian.h"
 #include "charger.h"
 #include "charge_manager.h"
@@ -20,35 +21,45 @@
 #include "usb_charge.h"
 #include "usb_pd.h"
 #include "util.h"
+#include "temp_sensor/temp_sensor.h"
+#include "temp_sensor/thermistor.h"
 
 /* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
 #define CPRINTS(format, args...) \
-	cprints(CC_CHARGER, "%s " format, "RT9490", ## args)
+	cprints(CC_CHARGER, "%s " format, "RT9490", ##args)
 
 /* Charger parameters */
-#define CHARGER_NAME    "rt9490"
-#define CHARGE_V_MAX    18800
-#define CHARGE_V_MIN    3000
-#define CHARGE_V_STEP   10
-#define CHARGE_I_MAX    5000
-#define CHARGE_I_MIN    50
-#define CHARGE_I_STEP   10
-#define INPUT_I_MAX     3300
-#define INPUT_I_MIN     100
-#define INPUT_I_STEP    10
+#define CHARGER_NAME "rt9490"
+#define CHARGE_V_MAX 18800
+#define CHARGE_V_MIN 3000
+#define CHARGE_V_STEP 10
+#define CHARGE_I_MAX 5000
+
+/* b/238980988
+ * RT9490 can't measure the 50mA charge current precisely due to insufficient
+ * ADC resolution, and faulty leads it into battery supply mode.
+ * the final number would be expected between 100mA ~ 200mA.
+ * Vendor has done the FT correlation and will revise the datasheet's
+ * CHARGE_I_MIN value from 50mA to 150mA as the final solution.
+ */
+#define CHARGE_I_MIN 150
+#define CHARGE_I_STEP 10
+#define INPUT_I_MAX 3300
+#define INPUT_I_MIN 100
+#define INPUT_I_STEP 10
 
 /* Charger parameters */
 static const struct charger_info rt9490_charger_info = {
-	.name         = CHARGER_NAME,
-	.voltage_max  = CHARGE_V_MAX,
-	.voltage_min  = CHARGE_V_MIN,
+	.name = CHARGER_NAME,
+	.voltage_max = CHARGE_V_MAX,
+	.voltage_min = CHARGE_V_MIN,
 	.voltage_step = CHARGE_V_STEP,
-	.current_max  = CHARGE_I_MAX,
-	.current_min  = CHARGE_I_MIN,
+	.current_max = CHARGE_I_MAX,
+	.current_min = CHARGE_I_MIN,
 	.current_step = CHARGE_I_STEP,
-	.input_current_max  = INPUT_I_MAX,
-	.input_current_min  = INPUT_I_MIN,
+	.input_current_max = INPUT_I_MAX,
+	.input_current_min = INPUT_I_MIN,
 	.input_current_step = INPUT_I_STEP,
 };
 
@@ -62,13 +73,13 @@ static const struct rt9490_init_setting default_init_setting = {
 static enum ec_error_list rt9490_read8(int chgnum, int reg, int *val)
 {
 	return i2c_read8(chg_chips[chgnum].i2c_port,
-			chg_chips[chgnum].i2c_addr_flags, reg, val);
+			 chg_chips[chgnum].i2c_addr_flags, reg, val);
 }
 
 static enum ec_error_list rt9490_write8(int chgnum, int reg, int val)
 {
 	return i2c_write8(chg_chips[chgnum].i2c_port,
-			chg_chips[chgnum].i2c_addr_flags, reg, val);
+			  chg_chips[chgnum].i2c_addr_flags, reg, val);
 }
 
 static enum ec_error_list rt9490_read16(int chgnum, int reg, uint16_t *val)
@@ -76,7 +87,8 @@ static enum ec_error_list rt9490_read16(int chgnum, int reg, uint16_t *val)
 	int reg_val;
 
 	RETURN_ERROR(i2c_read16(chg_chips[chgnum].i2c_port,
-			chg_chips[chgnum].i2c_addr_flags, reg, &reg_val));
+				chg_chips[chgnum].i2c_addr_flags, reg,
+				&reg_val));
 
 	*val = be16toh(reg_val);
 
@@ -88,22 +100,21 @@ static enum ec_error_list rt9490_write16(int chgnum, int reg, uint16_t val)
 	int reg_val = htobe16(val);
 
 	return i2c_write16(chg_chips[chgnum].i2c_port,
-			chg_chips[chgnum].i2c_addr_flags, reg, reg_val);
+			   chg_chips[chgnum].i2c_addr_flags, reg, reg_val);
 }
 
 static int rt9490_field_update8(int chgnum, int reg, int mask, int val)
 {
 	return i2c_field_update8(chg_chips[chgnum].i2c_port,
-				 chg_chips[chgnum].i2c_addr_flags,
-				 reg, mask, val);
+				 chg_chips[chgnum].i2c_addr_flags, reg, mask,
+				 val);
 }
 
 static inline int rt9490_update8(int chgnum, int reg, int mask,
 				 enum mask_update_action action)
 {
 	return i2c_update8(chg_chips[chgnum].i2c_port,
-			   chg_chips[chgnum].i2c_addr_flags,
-			   reg, mask, action);
+			   chg_chips[chgnum].i2c_addr_flags, reg, mask, action);
 }
 
 static inline int rt9490_set_bit(int chgnum, int reg, int mask)
@@ -130,7 +141,7 @@ static const struct charger_info *rt9490_get_info(int chgnum)
 static enum ec_error_list rt9490_get_current(int chgnum, int *current)
 {
 	uint16_t val = 0;
-	const struct charger_info * const info = rt9490_get_info(chgnum);
+	const struct charger_info *const info = rt9490_get_info(chgnum);
 
 	RETURN_ERROR(rt9490_read16(chgnum, RT9490_REG_ICHG_CTRL, &val));
 
@@ -159,7 +170,7 @@ static enum ec_error_list rt9490_set_current(int chgnum, int current)
 static enum ec_error_list rt9490_get_voltage(int chgnum, int *voltage)
 {
 	uint16_t val = 0;
-	const struct charger_info * const info = rt9490_get_info(chgnum);
+	const struct charger_info *const info = rt9490_get_info(chgnum);
 
 	RETURN_ERROR(rt9490_read16(chgnum, RT9490_REG_VCHG_CTRL, &val));
 
@@ -287,48 +298,37 @@ static int rt9490_init_setting(int chgnum)
 	/*  Disable boost-mode output voltage */
 	RETURN_ERROR(rt9490_enable_otg_power(chgnum, 0));
 	RETURN_ERROR(rt9490_set_otg_current_voltage(
-			chgnum,
-			default_init_setting.boost_current,
-			default_init_setting.boost_voltage));
+		chgnum, default_init_setting.boost_current,
+		default_init_setting.boost_voltage));
 #endif
 	/* Disable ILIM_HZ pin current limit */
-	RETURN_ERROR(rt9490_clr_bit(
-			chgnum, RT9490_REG_CHG_CTRL5, RT9490_ILIM_HZ_EN));
+	RETURN_ERROR(rt9490_clr_bit(chgnum, RT9490_REG_CHG_CTRL5,
+				    RT9490_ILIM_HZ_EN));
 	/* Disable BC 1.2 detection by default. It will be enabled on demand */
 	RETURN_ERROR(rt9490_enable_chgdet_flow(chgnum, false));
 	/* Disable WDT */
 	RETURN_ERROR(rt9490_enable_wdt(chgnum, false));
 	/* Disable battery thermal protection */
-	RETURN_ERROR(rt9490_set_bit(
-			chgnum, RT9490_REG_ADD_CTRL0, RT9490_JEITA_COLD_HOT));
+	RETURN_ERROR(rt9490_set_bit(chgnum, RT9490_REG_ADD_CTRL0,
+				    RT9490_JEITA_COLD_HOT));
 	/* Disable AUTO_AICR / AUTO_MIVR */
-	RETURN_ERROR(rt9490_clr_bit(
-			chgnum,
-			RT9490_REG_ADD_CTRL0,
-			RT9490_AUTO_AICR | RT9490_AUTO_MIVR));
-	/* Disable charge timer */
-	RETURN_ERROR(rt9490_clr_bit(
-			chgnum,
-			RT9490_REG_SAFETY_TMR_CTRL,
-			RT9490_EN_TRICHG_TMR |
-			RT9490_EN_PRECHG_TMR |
-			RT9490_EN_FASTCHG_TMR));
+	RETURN_ERROR(rt9490_clr_bit(chgnum, RT9490_REG_ADD_CTRL0,
+				    RT9490_AUTO_AICR | RT9490_AUTO_MIVR));
 	RETURN_ERROR(rt9490_set_mivr(chgnum, default_init_setting.mivr));
 	RETURN_ERROR(rt9490_set_ieoc(chgnum, default_init_setting.eoc_current));
 	RETURN_ERROR(rt9490_set_iprec(chgnum, batt_info->precharge_current));
 	RETURN_ERROR(rt9490_enable_adc(chgnum, true));
 	RETURN_ERROR(rt9490_enable_jeita(chgnum, false));
 	RETURN_ERROR(rt9490_field_update8(
-			chgnum, RT9490_REG_CHG_CTRL1, RT9490_VAC_OVP_MASK,
-			RT9490_VAC_OVP_26V << RT9490_VAC_OVP_SHIFT));
-
+		chgnum, RT9490_REG_CHG_CTRL1, RT9490_VAC_OVP_MASK,
+		RT9490_VAC_OVP_26V << RT9490_VAC_OVP_SHIFT));
 
 	/* Mask all interrupts except BC12 done */
 	RETURN_ERROR(rt9490_set_bit(chgnum, RT9490_REG_CHG_IRQ_MASK0,
 				    RT9490_CHG_IRQ_MASK0_ALL));
 	RETURN_ERROR(rt9490_set_bit(chgnum, RT9490_REG_CHG_IRQ_MASK1,
 				    RT9490_CHG_IRQ_MASK1_ALL &
-				    ~RT9490_BC12_DONE_MASK));
+					    ~RT9490_BC12_DONE_MASK));
 	RETURN_ERROR(rt9490_set_bit(chgnum, RT9490_REG_CHG_IRQ_MASK2,
 				    RT9490_CHG_IRQ_MASK2_ALL));
 	RETURN_ERROR(rt9490_set_bit(chgnum, RT9490_REG_CHG_IRQ_MASK3,
@@ -337,6 +337,10 @@ static int rt9490_init_setting(int chgnum)
 				    RT9490_CHG_IRQ_MASK4_ALL));
 	RETURN_ERROR(rt9490_set_bit(chgnum, RT9490_REG_CHG_IRQ_MASK5,
 				    RT9490_CHG_IRQ_MASK5_ALL));
+	/* Reduce SW freq from 1.5MHz to 1MHz
+	 * for 10% higher current rating b/215294785
+	 */
+	RETURN_ERROR(rt9490_enable_pwm_1mhz(CHARGER_SOLO, true));
 
 	return EC_SUCCESS;
 }
@@ -344,7 +348,7 @@ static int rt9490_init_setting(int chgnum)
 int rt9490_enable_pwm_1mhz(int chgnum, bool en)
 {
 	return rt9490_update8(chgnum, RT9490_REG_ADD_CTRL1, RT9490_PWM_1MHZ_EN,
-			en ? MASK_SET : MASK_CLR);
+			      en ? MASK_SET : MASK_CLR);
 }
 
 static void rt9490_init(int chgnum)
@@ -409,7 +413,7 @@ static enum ec_error_list rt9490_get_actual_current(int chgnum, int *current)
 	uint16_t reg_val;
 
 	RETURN_ERROR(rt9490_read16(chgnum, RT9490_REG_IBAT_ADC, &reg_val));
-	*current = (int)reg_val * 1000;
+	*current = (int)reg_val;
 	return EC_SUCCESS;
 }
 
@@ -418,7 +422,7 @@ static enum ec_error_list rt9490_get_actual_voltage(int chgnum, int *voltage)
 	uint16_t reg_val;
 
 	RETURN_ERROR(rt9490_read16(chgnum, RT9490_REG_VBAT_ADC, &reg_val));
-	*voltage = (int)reg_val * 1000;
+	*voltage = (int)reg_val;
 	return EC_SUCCESS;
 }
 
@@ -433,7 +437,7 @@ static enum ec_error_list rt9490_get_vbus_voltage(int chgnum, int port,
 	uint16_t reg_val;
 
 	RETURN_ERROR(rt9490_read16(chgnum, RT9490_REG_VBUS_ADC, &reg_val));
-	*voltage = (int)reg_val * 1000;
+	*voltage = (int)reg_val;
 	return EC_SUCCESS;
 }
 
@@ -460,10 +464,11 @@ static enum ec_error_list rt9490_get_input_current_limit(int chgnum,
 static enum ec_error_list rt9490_get_input_current(int chgnum,
 						   int *input_current)
 {
-	uint16_t reg_val;
+	int16_t reg_val;
 
-	RETURN_ERROR(rt9490_read16(chgnum, RT9490_REG_IBUS_ADC, &reg_val));
-	*input_current = (int)reg_val * 1000;
+	RETURN_ERROR(rt9490_read16(chgnum, RT9490_REG_IBUS_ADC,
+				   (uint16_t *)&reg_val));
+	*input_current = reg_val;
 	return EC_SUCCESS;
 }
 
@@ -623,7 +628,7 @@ static void rt9490_update_charge_manager(int port,
 	if (new_bc12_type != current_bc12_type) {
 		if (current_bc12_type >= 0)
 			charge_manager_update_charge(current_bc12_type, port,
-							NULL);
+						     NULL);
 
 		if (new_bc12_type != CHARGE_SUPPLIER_NONE) {
 			struct charge_port_info chg = {
@@ -660,17 +665,16 @@ static void rt9490_usb_charger_task_event(const int port, uint32_t evt)
 	 * to always trigger bc1.2 detection for other cases.
 	 */
 	bool is_non_pd_sink = !pd_capable(port) &&
-		!usb_charger_port_is_sourcing_vbus(port) &&
-		pd_check_vbus_level(port, VBUS_PRESENT);
+			      !usb_charger_port_is_sourcing_vbus(port) &&
+			      pd_check_vbus_level(port, VBUS_PRESENT);
 
 	/* vbus change, start bc12 detection */
 	if (evt & USB_CHG_EVENT_VBUS) {
-
 		if (is_non_pd_sink)
 			rt9490_enable_chgdet_flow(CHARGER_SOLO, true);
 		else
-			rt9490_update_charge_manager(
-					port, CHARGE_SUPPLIER_NONE);
+			rt9490_update_charge_manager(port,
+						     CHARGE_SUPPLIER_NONE);
 	}
 
 	/* detection done, update charge_manager and stop detection */
@@ -733,3 +737,21 @@ struct bc12_config bc12_ports[CHARGE_PORT_COUNT] = {
 	},
 };
 #endif /* CONFIG_BC12_SINGLE_DRIVER */
+
+int rt9490_get_thermistor_val(const struct temp_sensor_t *sensor, int *temp_ptr)
+{
+	uint16_t mv;
+	int idx = sensor->idx;
+#if IS_ENABLED(CONFIG_ZEPHYR) && IS_ENABLED(CONFIG_TEMP_SENSOR)
+	const struct thermistor_info *info = sensor->zephyr_info->thermistor;
+#else
+	const struct thermistor_info *info = &rt9490_thermistor_info;
+#endif
+
+	if (idx != 0)
+		return EC_ERROR_PARAM1;
+	RETURN_ERROR(rt9490_read16(idx, RT9490_REG_TS_ADC, &mv));
+	*temp_ptr = thermistor_linear_interpolate(mv, info);
+	*temp_ptr = C_TO_K(*temp_ptr);
+	return EC_SUCCESS;
+}
diff --git a/driver/charger/rt9490.h b/driver/charger/rt9490.h
index 2fd0edbac2..b814ecf842 100644
--- a/driver/charger/rt9490.h
+++ b/driver/charger/rt9490.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -6,74 +6,76 @@
  */
 #include <stdbool.h>
 
+#include "temp_sensor.h"
+
 #ifndef __CROS_EC_RT9490_H
 #define __CROS_EC_RT9490_H
 
-#define RT9490_ADDR_FLAGS	0x53
+#define RT9490_ADDR_FLAGS 0x53
 
 /* Registers */
-#define RT9490_REG_SYS_MIN_REGU		0x00
-#define RT9490_REG_VCHG_CTRL		0x01
-#define RT9490_REG_ICHG_CTRL		0x03
-#define RT9490_REG_MIVR_CTRL		0x05
-#define RT9490_REG_AICR_CTRL		0x06
-#define RT9490_REG_PRE_CHG		0x08
-#define RT9490_REG_EOC_CTRL		0x09
-#define RT9490_REG_RECHG		0x0A
-#define RT9490_REG_VOTG_REGU		0x0B
-#define RT9490_REG_IOTG_REGU		0x0D
-#define RT9490_REG_SAFETY_TMR_CTRL	0x0E
-#define RT9490_REG_CHG_CTRL0		0x0F
-#define RT9490_REG_CHG_CTRL1		0x10
-#define RT9490_REG_CHG_CTRL2		0x11
-#define RT9490_REG_CHG_CTRL3		0x12
-#define RT9490_REG_CHG_CTRL4		0x13
-#define RT9490_REG_CHG_CTRL5		0x14
-#define RT9490_REG_THREG_CTRL		0x16
-#define RT9490_REG_JEITA_CTRL0		0x17
-#define RT9490_REG_JEITA_CTRL1		0x18
-#define RT9490_REG_AICC_CTRL		0x19
-#define RT9490_REG_CHG_STATUS0		0x1B
-#define RT9490_REG_CHG_STATUS1		0x1C
-#define RT9490_REG_CHG_STATUS2		0x1D
-#define RT9490_REG_CHG_STATUS3		0x1E
-#define RT9490_REG_CHG_STATUS4		0x1F
-#define RT9490_REG_FAULT_STATUS0	0x20
-#define RT9490_REG_FAULT_STATUS1	0x21
-#define RT9490_REG_CHG_IRQ_FLAG0	0x22
-#define RT9490_REG_CHG_IRQ_FLAG1	0x23
-#define RT9490_REG_CHG_IRQ_FLAG2	0x24
-#define RT9490_REG_CHG_IRQ_FLAG3	0x25
-#define RT9490_REG_CHG_IRQ_FLAG4	0x26
-#define RT9490_REG_CHG_IRQ_FLAG5	0x27
-#define RT9490_REG_CHG_IRQ_MASK0	0x28
-#define RT9490_REG_CHG_IRQ_MASK1	0x29
-#define RT9490_REG_CHG_IRQ_MASK2	0x2A
-#define RT9490_REG_CHG_IRQ_MASK3	0x2B
-#define RT9490_REG_CHG_IRQ_MASK4	0x2C
-#define RT9490_REG_CHG_IRQ_MASK5	0x2D
-#define RT9490_REG_ADC_CTRL		0x2E
-#define RT9490_REG_ADC_CHANNEL0		0x2F
-#define RT9490_REG_ADC_CHANNEL1		0x30
-#define RT9490_REG_IBUS_ADC		0x31
-#define RT9490_REG_IBAT_ADC		0x33
-#define RT9490_REG_VBUS_ADC		0x35
-#define RT9490_REG_VAC1_ADC		0x37
-#define RT9490_REG_VAC2_ADC		0x39
-#define RT9490_REG_VBAT_ADC		0x3B
-#define RT9490_REG_VSYS_ADC		0x3D
-#define RT9490_REG_TS_ADC		0x3F
-#define RT9490_REG_TDIE_ADC		0x41
-#define RT9490_REG_DP_ADC		0x43
-#define RT9490_REG_DM_ADC		0x45
-#define RT9490_REG_DPDM_MANU_CTRL	0x47
-#define RT9490_REG_DEVICE_INFO		0x48
-#define RT9490_REG_PUMP_EXP		0x49
-#define RT9490_REG_ADD_CTRL0		0x4A
-#define RT9490_REG_ADD_CTRL1		0x4B
-#define RT9490_REG_ADD_CTRL2		0x4C
-#define RT9490_REG_ADD_IRQ_FLAG		0x4D
-#define RT9490_REG_ADD_IRQ_MASK6	0x4E
+#define RT9490_REG_SYS_MIN_REGU 0x00
+#define RT9490_REG_VCHG_CTRL 0x01
+#define RT9490_REG_ICHG_CTRL 0x03
+#define RT9490_REG_MIVR_CTRL 0x05
+#define RT9490_REG_AICR_CTRL 0x06
+#define RT9490_REG_PRE_CHG 0x08
+#define RT9490_REG_EOC_CTRL 0x09
+#define RT9490_REG_RECHG 0x0A
+#define RT9490_REG_VOTG_REGU 0x0B
+#define RT9490_REG_IOTG_REGU 0x0D
+#define RT9490_REG_SAFETY_TMR_CTRL 0x0E
+#define RT9490_REG_CHG_CTRL0 0x0F
+#define RT9490_REG_CHG_CTRL1 0x10
+#define RT9490_REG_CHG_CTRL2 0x11
+#define RT9490_REG_CHG_CTRL3 0x12
+#define RT9490_REG_CHG_CTRL4 0x13
+#define RT9490_REG_CHG_CTRL5 0x14
+#define RT9490_REG_THREG_CTRL 0x16
+#define RT9490_REG_JEITA_CTRL0 0x17
+#define RT9490_REG_JEITA_CTRL1 0x18
+#define RT9490_REG_AICC_CTRL 0x19
+#define RT9490_REG_CHG_STATUS0 0x1B
+#define RT9490_REG_CHG_STATUS1 0x1C
+#define RT9490_REG_CHG_STATUS2 0x1D
+#define RT9490_REG_CHG_STATUS3 0x1E
+#define RT9490_REG_CHG_STATUS4 0x1F
+#define RT9490_REG_FAULT_STATUS0 0x20
+#define RT9490_REG_FAULT_STATUS1 0x21
+#define RT9490_REG_CHG_IRQ_FLAG0 0x22
+#define RT9490_REG_CHG_IRQ_FLAG1 0x23
+#define RT9490_REG_CHG_IRQ_FLAG2 0x24
+#define RT9490_REG_CHG_IRQ_FLAG3 0x25
+#define RT9490_REG_CHG_IRQ_FLAG4 0x26
+#define RT9490_REG_CHG_IRQ_FLAG5 0x27
+#define RT9490_REG_CHG_IRQ_MASK0 0x28
+#define RT9490_REG_CHG_IRQ_MASK1 0x29
+#define RT9490_REG_CHG_IRQ_MASK2 0x2A
+#define RT9490_REG_CHG_IRQ_MASK3 0x2B
+#define RT9490_REG_CHG_IRQ_MASK4 0x2C
+#define RT9490_REG_CHG_IRQ_MASK5 0x2D
+#define RT9490_REG_ADC_CTRL 0x2E
+#define RT9490_REG_ADC_CHANNEL0 0x2F
+#define RT9490_REG_ADC_CHANNEL1 0x30
+#define RT9490_REG_IBUS_ADC 0x31
+#define RT9490_REG_IBAT_ADC 0x33
+#define RT9490_REG_VBUS_ADC 0x35
+#define RT9490_REG_VAC1_ADC 0x37
+#define RT9490_REG_VAC2_ADC 0x39
+#define RT9490_REG_VBAT_ADC 0x3B
+#define RT9490_REG_VSYS_ADC 0x3D
+#define RT9490_REG_TS_ADC 0x3F
+#define RT9490_REG_TDIE_ADC 0x41
+#define RT9490_REG_DP_ADC 0x43
+#define RT9490_REG_DM_ADC 0x45
+#define RT9490_REG_DPDM_MANU_CTRL 0x47
+#define RT9490_REG_DEVICE_INFO 0x48
+#define RT9490_REG_PUMP_EXP 0x49
+#define RT9490_REG_ADD_CTRL0 0x4A
+#define RT9490_REG_ADD_CTRL1 0x4B
+#define RT9490_REG_ADD_CTRL2 0x4C
+#define RT9490_REG_ADD_IRQ_FLAG 0x4D
+#define RT9490_REG_ADD_IRQ_MASK6 0x4E
 
 struct rt9490_init_setting {
 	int eoc_current;
@@ -83,164 +85,164 @@ struct rt9490_init_setting {
 };
 
 /* CV */
-#define RT9490_CV_MASK				0x7FF
-#define RT9490_CV_MIN				3000
-#define RT9490_CV_MAX				18800
-#define RT9490_CV_STEP				10
+#define RT9490_CV_MASK 0x7FF
+#define RT9490_CV_MIN 3000
+#define RT9490_CV_MAX 18800
+#define RT9490_CV_STEP 10
 
 /* ICGH */
-#define RT9490_ICHG_MASK			0x1FF
-#define RT9490_ICHG_SHIFT			0
-#define RT9490_ICHG_MIN				50
-#define RT9490_ICHG_MAX				5000
-#define RT9490_ICHG_STEP			10
-#define RT9490_ICHG_MIN_REG_VAL			0x0005
+#define RT9490_ICHG_MASK 0x1FF
+#define RT9490_ICHG_SHIFT 0
+#define RT9490_ICHG_MIN 50
+#define RT9490_ICHG_MAX 5000
+#define RT9490_ICHG_STEP 10
+#define RT9490_ICHG_MIN_REG_VAL 0x0005
 
 /* PRE CHG */
-#define RT9490_IPRE_CHG_MASK			0x1F
-#define RT9490_IPRE_CHG_MIN			40
-#define RT9490_IPRE_CHG_MAX			2000
-#define RT9490_IPRE_CHG_STEP			40
-#define RT9490_IPREC_SHIFT			0
+#define RT9490_IPRE_CHG_MASK 0x1F
+#define RT9490_IPRE_CHG_MIN 40
+#define RT9490_IPRE_CHG_MAX 2000
+#define RT9490_IPRE_CHG_STEP 40
+#define RT9490_IPREC_SHIFT 0
 
 /* MIVR */
-#define RT9490_MIVR_MIN				3600
-#define RT9490_MIVR_MAX				22000
-#define RT9490_MIVR_STEP			100
-#define RT9490_MIVR_MIN_REG_VAL			0x24
+#define RT9490_MIVR_MIN 3600
+#define RT9490_MIVR_MAX 22000
+#define RT9490_MIVR_STEP 100
+#define RT9490_MIVR_MIN_REG_VAL 0x24
 
 /* AICR */
-#define RT9490_AICR_MASK			0x1FF
-#define RT9490_AICR_SHIFT			0
-#define RT9490_AICR_MIN				100
-#define RT9490_AICR_MAX				3300
-#define RT9490_AICR_STEP			10
-#define RT9490_AICR_MIN_REG_VAL			0x000A
+#define RT9490_AICR_MASK 0x1FF
+#define RT9490_AICR_SHIFT 0
+#define RT9490_AICR_MIN 100
+#define RT9490_AICR_MAX 3300
+#define RT9490_AICR_STEP 10
+#define RT9490_AICR_MIN_REG_VAL 0x000A
 
 /* EOC */
-#define RT9490_IEOC_MIN				40
-#define RT9490_IEOC_MAX				1000
-#define RT9490_IEOC_STEP			40
-#define RT9490_IEOC_MIN_REG_VAL			0x01
-#define RT9490_IEOC_SHIFT			0
-#define RT9490_IEOC_MASK			0x1F
+#define RT9490_IEOC_MIN 40
+#define RT9490_IEOC_MAX 1000
+#define RT9490_IEOC_STEP 40
+#define RT9490_IEOC_MIN_REG_VAL 0x01
+#define RT9490_IEOC_SHIFT 0
+#define RT9490_IEOC_MASK 0x1F
 
 /* DEVICE INFO */
-#define RT9490_DEVICE_ID			0x60
-#define RT9490_DEVICE_INFO_MASK			0x78
+#define RT9490_DEVICE_ID 0x60
+#define RT9490_DEVICE_INFO_MASK 0x78
 
 /* EOC_CTRL */
-#define RT9490_RST_ALL_MASK			BIT(7)
+#define RT9490_RST_ALL_MASK BIT(7)
 
 /* CHG_CTRL0 */
-#define RT9490_EN_CHG				BIT(5)
-#define RT9490_EN_AICC				BIT(4)
-#define RT9490_FORCE_AICC			BIT(3)
-#define RT9490_EN_HZ				BIT(2)
+#define RT9490_EN_CHG BIT(5)
+#define RT9490_EN_AICC BIT(4)
+#define RT9490_FORCE_AICC BIT(3)
+#define RT9490_EN_HZ BIT(2)
 
 /* CHG_CTRL1 */
-#define RT9490_VAC_OVP_SHIFT			4
-#define RT9490_VAC_OVP_MASK			(3 << RT9490_VAC_OVP_SHIFT)
-#define RT9490_VAC_OVP_26V			0
-#define RT9490_VAC_OVP_22V			1
-#define RT9490_VAC_OVP_12V			2
-#define RT9490_VAC_OVP_7V			3
-
-#define RT9490_WATCHDOG_MASK			0x07
-#define RT9490_WATCHDOG_DISABLE			0
-#define RT9490_WATCHDOG_0_5_SEC			1 /* 0.5 sec */
-#define RT9490_WATCHDOG_1_SEC			2
-#define RT9490_WATCHDOG_2_SEC			3
-#define RT9490_WATCHDOG_20_SEC			4
-#define RT9490_WATCHDOG_40_SEC			5
-#define RT9490_WATCHDOG_80_SEC			6
-#define RT9490_WATCHDOG_160_SEC			7
+#define RT9490_VAC_OVP_SHIFT 4
+#define RT9490_VAC_OVP_MASK (3 << RT9490_VAC_OVP_SHIFT)
+#define RT9490_VAC_OVP_26V 0
+#define RT9490_VAC_OVP_22V 1
+#define RT9490_VAC_OVP_12V 2
+#define RT9490_VAC_OVP_7V 3
+
+#define RT9490_WATCHDOG_MASK 0x07
+#define RT9490_WATCHDOG_DISABLE 0
+#define RT9490_WATCHDOG_0_5_SEC 1 /* 0.5 sec */
+#define RT9490_WATCHDOG_1_SEC 2
+#define RT9490_WATCHDOG_2_SEC 3
+#define RT9490_WATCHDOG_20_SEC 4
+#define RT9490_WATCHDOG_40_SEC 5
+#define RT9490_WATCHDOG_80_SEC 6
+#define RT9490_WATCHDOG_160_SEC 7
 
 /* CHG_CTRL2 */
-#define RT9490_BC12_EN				BIT(6)
+#define RT9490_BC12_EN BIT(6)
 
 /* CHG_CTRL3 */
-#define RT9490_EN_OTG				BIT(6)
+#define RT9490_EN_OTG BIT(6)
 
 /* CHG_CTRL5 */
-#define RT9490_ILIM_HZ_EN			BIT(1)
+#define RT9490_ILIM_HZ_EN BIT(1)
 
 /* CHG_STATUS4 */
-#define RT9490_JEITA_COLD_MASK			BIT(3)
-#define RT9490_JEITA_COOL_MASK			BIT(2)
-#define RT9490_JEITA_WARM_MASK			BIT(1)
-#define RT9490_JEITA_HOT_MASK			BIT(0)
+#define RT9490_JEITA_COLD_MASK BIT(3)
+#define RT9490_JEITA_COOL_MASK BIT(2)
+#define RT9490_JEITA_WARM_MASK BIT(1)
+#define RT9490_JEITA_HOT_MASK BIT(0)
 
 /* CHG_IRQ_FLAG1 */
-#define RT9490_BC12_DONE_FLAG			BIT(0)
+#define RT9490_BC12_DONE_FLAG BIT(0)
 
 /* CHG_IRQ_MASK0 */
-#define RT9490_CHG_IRQ_MASK0_ALL		0xFF
+#define RT9490_CHG_IRQ_MASK0_ALL 0xFF
 
 /* CHG_IRQ_MASK1 */
-#define RT9490_BC12_DONE_MASK			BIT(0)
-#define RT9490_CHG_IRQ_MASK1_ALL		0xD7
+#define RT9490_BC12_DONE_MASK BIT(0)
+#define RT9490_CHG_IRQ_MASK1_ALL 0xD7
 
 /* CHG_IRQ_MASK2 */
-#define RT9490_CHG_IRQ_MASK2_ALL		0x7F
+#define RT9490_CHG_IRQ_MASK2_ALL 0x7F
 
 /* CHG_IRQ_MASK3 */
-#define RT9490_CHG_IRQ_MASK3_ALL		0x1F
+#define RT9490_CHG_IRQ_MASK3_ALL 0x1F
 
 /* CHG_IRQ_MASK4 */
-#define RT9490_CHG_IRQ_MASK4_ALL		0xFF
+#define RT9490_CHG_IRQ_MASK4_ALL 0xFF
 
 /* CHG_IRQ_MASK5 */
-#define RT9490_CHG_IRQ_MASK5_ALL		0xF4
+#define RT9490_CHG_IRQ_MASK5_ALL 0xF4
 
 /* SAFETY TMR CTRL */
-#define RT9490_EN_TRICHG_TMR			BIT(5)
-#define RT9490_EN_PRECHG_TMR			BIT(4)
-#define RT9490_EN_FASTCHG_TMR			BIT(3)
+#define RT9490_EN_TRICHG_TMR BIT(5)
+#define RT9490_EN_PRECHG_TMR BIT(4)
+#define RT9490_EN_FASTCHG_TMR BIT(3)
 
 /* VOTG REGU */
-#define RT9490_VOTG_MASK			0x7FF
-#define RT9490_VOTG_MIN				2800
-#define RT9490_VOTG_MAX				22000
-#define RT9490_VOTG_STEP			10
+#define RT9490_VOTG_MASK 0x7FF
+#define RT9490_VOTG_MIN 2800
+#define RT9490_VOTG_MAX 22000
+#define RT9490_VOTG_STEP 10
 
 /* IOTG REGU */
-#define RT9490_IOTG_MASK			0x7F
-#define RT9490_IOTG_MIN				120
-#define RT9490_IOTG_MAX				3320
-#define RT9490_IOTG_STEP			40
+#define RT9490_IOTG_MASK 0x7F
+#define RT9490_IOTG_MIN 120
+#define RT9490_IOTG_MAX 3320
+#define RT9490_IOTG_STEP 40
 
 /* JEITA_CTRL1 */
-#define RT9490_JEITA_DIS			BIT(0)
+#define RT9490_JEITA_DIS BIT(0)
 
 /* CHG_STATUS1 */
-#define RT9490_CHG_STAT_MASK			0xE0
-#define RT9490_CHG_STAT_SHIFT			5
-#define RT9490_VBUS_STAT_MASK			0x1E
-#define RT9490_VBUS_STAT_SHIFT			1
-#define RT9490_BC12_DONE_STAT			BIT(0)
+#define RT9490_CHG_STAT_MASK 0xE0
+#define RT9490_CHG_STAT_SHIFT 5
+#define RT9490_VBUS_STAT_MASK 0x1E
+#define RT9490_VBUS_STAT_SHIFT 1
+#define RT9490_BC12_DONE_STAT BIT(0)
 
-#define RT9490_SDP				0x1
-#define RT9490_CDP				0x2
-#define RT9490_DCP				0x3
+#define RT9490_SDP 0x1
+#define RT9490_CDP 0x2
+#define RT9490_DCP 0x3
 
 /* FAULT STATUS0 */
-#define RT9490_VBAT_OVP_STAT			BIT(5)
+#define RT9490_VBAT_OVP_STAT BIT(5)
 
 /* ADC CTRL */
-#define RT9490_ADC_EN				BIT(7)
+#define RT9490_ADC_EN BIT(7)
 
 /* ADC CHANNEL0 */
-#define RT9490_VSYS_ADC_DIS			BIT(3)
+#define RT9490_VSYS_ADC_DIS BIT(3)
 
 /* ADD CTRL0 */
-#define RT9490_AUTO_AICR			BIT(5)
-#define RT9490_TD_EOC				BIT(4)
-#define RT9490_AUTO_MIVR			BIT(2)
-#define RT9490_JEITA_COLD_HOT			BIT(0)
+#define RT9490_AUTO_AICR BIT(5)
+#define RT9490_TD_EOC BIT(4)
+#define RT9490_AUTO_MIVR BIT(2)
+#define RT9490_JEITA_COLD_HOT BIT(0)
 
 /* ADD CTRL1 */
-#define RT9490_PWM_1MHZ_EN			BIT(4)
+#define RT9490_PWM_1MHZ_EN BIT(4)
 
 extern const struct charger_drv rt9490_drv;
 extern const struct bc12_drv rt9490_bc12_drv;
@@ -252,3 +254,12 @@ int rt9490_enable_adc(int chgnum, bool en);
 int rt9490_enable_pwm_1mhz(int chgnum, bool en);
 
 #endif /* __CROS_EC_RT9490_H */
+
+/*
+ * Required for TS_ADC temperature calculation.
+ * Non-zephyr devices that using TS_ADC must define this in board layer.
+ */
+extern const struct thermistor_info rt9490_thermistor_info;
+
+int rt9490_get_thermistor_val(const struct temp_sensor_t *sensor,
+			      int *temp_ptr);
diff --git a/driver/charger/sm5803.c b/driver/charger/sm5803.c
index 131c611842..b8940cf8ff 100644
--- a/driver/charger/sm5803.c
+++ b/driver/charger/sm5803.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -28,23 +28,34 @@
 #error "SM5803 is a NVDC charger, please enable CONFIG_CHARGER_NARROW_VDC."
 #endif
 
+#ifdef PD_MAX_VOLTAGE_MV
+#if PD_MAX_VOLTAGE_MV > 15000
+/* See https://issuetracker.google.com/230712704 for details. */
+#error "VBUS >15V is forbidden for SM5803 because it can cause hardware damage"
+#endif
+#endif
+
+#ifdef CONFIG_CHARGER_SINGLE_CHIP
+#define CHARGER_PRIMARY CHARGER_SOLO
+#endif
+
 /* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 #define UNKNOWN_DEV_ID -1
 static int dev_id = UNKNOWN_DEV_ID;
 
 static const struct charger_info sm5803_charger_info = {
-	.name         = CHARGER_NAME,
-	.voltage_max  = CHARGE_V_MAX,
-	.voltage_min  = CHARGE_V_MIN,
+	.name = CHARGER_NAME,
+	.voltage_max = CHARGE_V_MAX,
+	.voltage_min = CHARGE_V_MIN,
 	.voltage_step = CHARGE_V_STEP,
-	.current_max  = CHARGE_I_MAX,
-	.current_min  = CHARGE_I_MIN,
+	.current_max = CHARGE_I_MAX,
+	.current_min = CHARGE_I_MIN,
 	.current_step = CHARGE_I_STEP,
-	.input_current_max  = INPUT_I_MAX,
-	.input_current_min  = INPUT_I_MIN,
+	.input_current_max = INPUT_I_MAX,
+	.input_current_min = INPUT_I_MIN,
 	.input_current_step = INPUT_I_STEP,
 };
 
@@ -77,9 +88,8 @@ static int attempt_bfet_enable;
  */
 static bool fast_charge_disabled;
 
-
-#define CHARGING_FAILURE_MAX_COUNT	5
-#define CHARGING_FAILURE_INTERVAL	MINUTE
+#define CHARGING_FAILURE_MAX_COUNT 5
+#define CHARGING_FAILURE_INTERVAL MINUTE
 
 static int sm5803_is_sourcing_otg_power(int chgnum, int port);
 static enum ec_error_list sm5803_get_dev_id(int chgnum, int *id);
@@ -88,62 +98,105 @@ static enum ec_error_list sm5803_set_current(int chgnum, int current);
 static inline enum ec_error_list chg_read8(int chgnum, int offset, int *value)
 {
 	return i2c_read8(chg_chips[chgnum].i2c_port,
-			 chg_chips[chgnum].i2c_addr_flags,
-			 offset, value);
+			 chg_chips[chgnum].i2c_addr_flags, offset, value);
 }
 
 static inline enum ec_error_list chg_write8(int chgnum, int offset, int value)
 {
 	return i2c_write8(chg_chips[chgnum].i2c_port,
-			  chg_chips[chgnum].i2c_addr_flags,
-			  offset, value);
+			  chg_chips[chgnum].i2c_addr_flags, offset, value);
 }
 
 static inline enum ec_error_list meas_read8(int chgnum, int offset, int *value)
 {
-	return i2c_read8(chg_chips[chgnum].i2c_port,
-			 SM5803_ADDR_MEAS_FLAGS,
+	return i2c_read8(chg_chips[chgnum].i2c_port, SM5803_ADDR_MEAS_FLAGS,
 			 offset, value);
 }
 
 static inline enum ec_error_list meas_write8(int chgnum, int offset, int value)
 {
-	return i2c_write8(chg_chips[chgnum].i2c_port,
-			 SM5803_ADDR_MEAS_FLAGS,
-			 offset, value);
+	return i2c_write8(chg_chips[chgnum].i2c_port, SM5803_ADDR_MEAS_FLAGS,
+			  offset, value);
 }
 
 static inline enum ec_error_list main_read8(int chgnum, int offset, int *value)
 {
-	return i2c_read8(chg_chips[chgnum].i2c_port,
-			 SM5803_ADDR_MAIN_FLAGS,
+	return i2c_read8(chg_chips[chgnum].i2c_port, SM5803_ADDR_MAIN_FLAGS,
 			 offset, value);
 }
 
 static inline enum ec_error_list main_write8(int chgnum, int offset, int value)
 {
-	return i2c_write8(chg_chips[chgnum].i2c_port,
-			 SM5803_ADDR_MAIN_FLAGS,
-			 offset, value);
+	return i2c_write8(chg_chips[chgnum].i2c_port, SM5803_ADDR_MAIN_FLAGS,
+			  offset, value);
 }
 
 static inline enum ec_error_list test_write8(int chgnum, int offset, int value)
 {
-	return i2c_write8(chg_chips[chgnum].i2c_port,
-			 SM5803_ADDR_TEST_FLAGS,
-			 offset, value);
+	return i2c_write8(chg_chips[chgnum].i2c_port, SM5803_ADDR_TEST_FLAGS,
+			  offset, value);
 }
 
-static inline enum ec_error_list test_update8(int chgnum, const int offset,
-					      const uint8_t mask,
-					const enum mask_update_action action)
+static inline enum ec_error_list
+test_update8(int chgnum, const int offset, const uint8_t mask,
+	     const enum mask_update_action action)
 {
-	return i2c_update8(chg_chips[chgnum].i2c_port,
-			   SM5803_ADDR_TEST_FLAGS, offset, mask, action);
+	return i2c_update8(chg_chips[chgnum].i2c_port, SM5803_ADDR_TEST_FLAGS,
+			   offset, mask, action);
+}
+
+/*
+ * Ensure the charger configuration is safe for operation, updating registers
+ * as necessary to become safe.
+ *
+ * The SM5803 runs multiple digital control loops that are important to correct
+ * operation. The CLOCK_SEL_LOW register reduces their speed by about 10x, which
+ * is dangerous when either sinking or sourcing is to be enabled because the
+ * control loops will respond much more slowly. Leaving clocks at low speed can
+ * cause incorrect operation or even hardware damage.
+ *
+ * The GPADCs are inputs to the control loops, and disabling them can also cause
+ * incorrect operation or hardware damage. They must be enabled for the charger
+ * to be safe to operate.
+ *
+ * This function is used by the functions that enable sinking or sourcing to
+ * ensure the current configuration is safe before enabling switching on the
+ * charger.
+ */
+static int sm5803_set_active_safe(int chgnum)
+{
+	int rv, val;
+
+	/*
+	 * Set clocks to full speed.
+	 *
+	 * This should occur first because enabling GPADCs with clocks slowed
+	 * can cause spurious acquisition.
+	 */
+	rv = main_read8(chgnum, SM5803_REG_CLOCK_SEL, &val);
+	if (rv == 0 && val & SM5803_CLOCK_SEL_LOW) {
+		rv = main_write8(chgnum, SM5803_REG_CLOCK_SEL,
+				 val & ~SM5803_CLOCK_SEL_LOW);
+	}
+	if (rv) {
+		goto out;
+	}
+
+	/* Enable default GPADCs */
+	rv = meas_write8(chgnum, SM5803_REG_GPADC_CONFIG1,
+			 SM5803_GPADCC1_DEFAULT_ENABLE);
+
+out:
+	if (rv) {
+		CPRINTS("%s %d: failed to set clocks to full speed: %d",
+			CHARGER_NAME, chgnum, rv);
+	}
+	return rv;
 }
 
-static enum ec_error_list sm5803_flow1_update(int chgnum, const uint8_t mask,
-					const enum mask_update_action action)
+static enum ec_error_list
+sm5803_flow1_update(int chgnum, const uint8_t mask,
+		    const enum mask_update_action action)
 {
 	int rv;
 
@@ -151,8 +204,7 @@ static enum ec_error_list sm5803_flow1_update(int chgnum, const uint8_t mask,
 	mutex_lock(&flow1_access_lock[chgnum]);
 
 	rv = i2c_update8(chg_chips[chgnum].i2c_port,
-			 chg_chips[chgnum].i2c_addr_flags,
-			 SM5803_REG_FLOW1,
+			 chg_chips[chgnum].i2c_addr_flags, SM5803_REG_FLOW1,
 			 mask, action);
 
 	mutex_unlock(&flow1_access_lock[chgnum]);
@@ -160,16 +212,16 @@ static enum ec_error_list sm5803_flow1_update(int chgnum, const uint8_t mask,
 	return rv;
 }
 
-static enum ec_error_list sm5803_flow2_update(int chgnum, const uint8_t mask,
-					const enum mask_update_action action)
+static enum ec_error_list
+sm5803_flow2_update(int chgnum, const uint8_t mask,
+		    const enum mask_update_action action)
 {
 	int rv;
 
 	mutex_lock(&flow2_access_lock[chgnum]);
 
 	rv = i2c_update8(chg_chips[chgnum].i2c_port,
-			 chg_chips[chgnum].i2c_addr_flags,
-			 SM5803_REG_FLOW2,
+			 chg_chips[chgnum].i2c_addr_flags, SM5803_REG_FLOW2,
 			 mask, action);
 
 	mutex_unlock(&flow2_access_lock[chgnum]);
@@ -292,6 +344,11 @@ enum ec_error_list sm5803_vbus_sink_enable(int chgnum, int enable)
 		return rv;
 
 	if (enable) {
+		rv = sm5803_set_active_safe(chgnum);
+		if (rv) {
+			return rv;
+		}
+
 		if (chgnum == CHARGER_PRIMARY) {
 			/* Magic for new silicon */
 			if (dev_id >= 3) {
@@ -303,17 +360,19 @@ enum ec_error_list sm5803_vbus_sink_enable(int chgnum, int enable)
 			 * Only enable auto fast charge when a battery is
 			 * connected and out of cutoff.
 			 */
-			if (battery_get_disconnect_state() ==
-			    BATTERY_NOT_DISCONNECTED) {
-				rv = sm5803_flow2_update(chgnum,
-						 SM5803_FLOW2_AUTO_ENABLED,
-						 MASK_SET);
+			if (IS_ENABLED(CONFIG_BATTERY) &&
+			    battery_get_disconnect_state() ==
+				    BATTERY_NOT_DISCONNECTED) {
+				rv = sm5803_flow2_update(
+					chgnum, SM5803_FLOW2_AUTO_ENABLED,
+					MASK_SET);
 				fast_charge_disabled = false;
 			} else {
-				rv = sm5803_flow2_update(chgnum,
-						SM5803_FLOW2_AUTO_TRKL_EN |
+				rv = sm5803_flow2_update(
+					chgnum,
+					SM5803_FLOW2_AUTO_TRKL_EN |
 						SM5803_FLOW2_AUTO_PRECHG_EN,
-						MASK_SET);
+					MASK_SET);
 				fast_charge_disabled = true;
 			}
 		} else {
@@ -340,10 +399,10 @@ enum ec_error_list sm5803_vbus_sink_enable(int chgnum, int enable)
 		rv |= sm5803_flow1_update(chgnum, CHARGER_MODE_SINK, MASK_SET);
 	} else {
 		if (chgnum == CHARGER_PRIMARY)
-			rv |= sm5803_flow2_update(chgnum,
-						  SM5803_FLOW2_AUTO_ENABLED,
-						  MASK_CLR);
+			rv |= sm5803_flow2_update(
+				chgnum, SM5803_FLOW2_AUTO_ENABLED, MASK_CLR);
 
+#ifndef CONFIG_CHARGER_SINGLE_CHIP
 		if (chgnum == CHARGER_SECONDARY) {
 			rv |= sm5803_flow1_update(CHARGER_PRIMARY,
 						  SM5803_FLOW1_LINEAR_CHARGE_EN,
@@ -355,7 +414,7 @@ enum ec_error_list sm5803_vbus_sink_enable(int chgnum, int enable)
 			rv |= chg_write8(CHARGER_PRIMARY, SM5803_REG_FLOW3,
 					 regval);
 		}
-
+#endif
 
 		/* Disable sink mode, unless currently sourcing out */
 		if (!sm5803_is_sourcing_otg_power(chgnum, chgnum))
@@ -364,7 +423,6 @@ enum ec_error_list sm5803_vbus_sink_enable(int chgnum, int enable)
 	}
 
 	return rv;
-
 }
 
 /*
@@ -372,8 +430,8 @@ enum ec_error_list sm5803_vbus_sink_enable(int chgnum, int enable)
  * boot.  This should prevent us from re-running inits after sysjumps.
  */
 static bool chip_inited[CHARGER_NUM];
-#define SM5803_SYSJUMP_TAG	0x534D /* SM */
-#define SM5803_HOOK_VERSION	1
+#define SM5803_SYSJUMP_TAG 0x534D /* SM */
+#define SM5803_HOOK_VERSION 1
 
 static void init_status_preserve(void)
 {
@@ -387,10 +445,9 @@ static void init_status_retrieve(void)
 	const uint8_t *tag_contents;
 	int version, size;
 
-	tag_contents = system_get_jump_tag(SM5803_SYSJUMP_TAG,
-						  &version, &size);
+	tag_contents = system_get_jump_tag(SM5803_SYSJUMP_TAG, &version, &size);
 	if (tag_contents && (version == SM5803_HOOK_VERSION) &&
-					(size == sizeof(chip_inited)))
+	    (size == sizeof(chip_inited)))
 		/* Valid init status found, restore before charger chip init */
 		memcpy(&chip_inited, tag_contents, size);
 }
@@ -414,15 +471,15 @@ static void sm5803_init(int chgnum)
 	enum ec_error_list rv;
 	int reg;
 	int vbus_mv;
-	const struct battery_info *batt_info;
-	int pre_term;
-	int cells;
 
 	/*
 	 * If a charger is not currently present, disable switching per OCPC
 	 * requirements
 	 */
-	rv = charger_get_vbus_voltage(chgnum, &vbus_mv);
+	/* Reset clocks and enable GPADCs */
+	rv = sm5803_set_active_safe(chgnum);
+
+	rv |= charger_get_vbus_voltage(chgnum, &vbus_mv);
 	if (rv == EC_SUCCESS) {
 		if (vbus_mv < 4000) {
 			/*
@@ -508,7 +565,7 @@ static void sm5803_init(int chgnum)
 		rv = main_read8(chgnum, SM5803_REG_PLATFORM, &platform_id);
 		if (rv) {
 			CPRINTS("%s %d: Failed to read platform during init",
-							CHARGER_NAME, chgnum);
+				CHARGER_NAME, chgnum);
 			return;
 		}
 		platform_id &= SM5803_PLATFORM_ID;
@@ -517,10 +574,10 @@ static void sm5803_init(int chgnum)
 			/* 3S Battery inits */
 			/* set 13.3V VBAT_SNSP TH GPADC THRESHOLD*/
 			rv |= meas_write8(chgnum, 0x26,
-				SM5803_VBAT_SNSP_MAXTH_3S_LEVEL);
+					  SM5803_VBAT_SNSP_MAXTH_3S_LEVEL);
 			/* OV_VBAT HW second level (14.1V) */
 			rv |= chg_write8(chgnum, 0x21,
-				SM5803_VBAT_PWR_MINTH_3S_LEVEL);
+					 SM5803_VBAT_PWR_MINTH_3S_LEVEL);
 			rv |= main_write8(chgnum, 0x30, 0xC0);
 			rv |= main_write8(chgnum, 0x80, 0x01);
 			rv |= main_write8(chgnum, 0x1A, 0x08);
@@ -566,11 +623,11 @@ static void sm5803_init(int chgnum)
 			 * threshold for interrupt generation.
 			 */
 			rv |= meas_write8(chgnum, 0x26,
-				SM5803_VBAT_SNSP_MAXTH_2S_LEVEL);
+					  SM5803_VBAT_SNSP_MAXTH_2S_LEVEL);
 
 			/* Set OV_VBAT HW second level threshold as 9.4V */
 			rv |= chg_write8(chgnum, 0x21,
-				SM5803_VBAT_PWR_MINTH_2S_LEVEL);
+					 SM5803_VBAT_PWR_MINTH_2S_LEVEL);
 
 			rv |= main_write8(chgnum, 0x30, 0xC0);
 			rv |= main_write8(chgnum, 0x80, 0x01);
@@ -627,24 +684,6 @@ static void sm5803_init(int chgnum)
 	reg &= ~(BIT(0) | BIT(1));
 	rv |= main_write8(chgnum, SM5803_REG_REFERENCE, reg);
 
-	/* Set a higher clock speed in case it was lowered for z-state */
-	rv |= main_read8(chgnum, SM5803_REG_CLOCK_SEL, &reg);
-	reg &= ~SM5803_CLOCK_SEL_LOW;
-	rv |= main_write8(chgnum, SM5803_REG_CLOCK_SEL, reg);
-
-	/*
-	 * Turn on GPADCs to default.  Enable the IBAT_CHG ADC in order to
-	 * measure battery current and calculate system resistance.
-	 */
-	reg = SM5803_GPADCC1_TINT_EN     |
-	      SM5803_GPADCC1_VSYS_EN     |
-	      SM5803_GPADCC1_VCHGPWR_EN  |
-	      SM5803_GPADCC1_VBUS_EN     |
-	      SM5803_GPADCC1_IBAT_CHG_EN |
-	      SM5803_GPADCC1_IBAT_DIS_EN |
-	      SM5803_GPADCC1_VBATSNSP_EN;
-	rv |= meas_write8(chgnum, SM5803_REG_GPADC_CONFIG1, reg);
-
 	/* Enable Psys DAC */
 	rv |= meas_read8(chgnum, SM5803_REG_PSYS1, &reg);
 	reg |= SM5803_PSYS1_DAC_EN;
@@ -667,26 +706,26 @@ static void sm5803_init(int chgnum)
 	rv |= chg_write8(chgnum, SM5803_REG_DPM_VL_SET_LSB, (reg & 0x7));
 
 	/* Set default input current */
-	reg = SM5803_CURRENT_TO_REG(CONFIG_CHARGER_INPUT_CURRENT)
-		& SM5803_CHG_ILIM_RAW;
+	reg = SM5803_CURRENT_TO_REG(CONFIG_CHARGER_INPUT_CURRENT) &
+	      SM5803_CHG_ILIM_RAW;
 	rv |= chg_write8(chgnum, SM5803_REG_CHG_ILIM, reg);
 
 	/* Configure charger insertion interrupts */
 	rv |= main_write8(chgnum, SM5803_REG_INT1_EN, SM5803_INT1_CHG);
 	/* Enable end of charge interrupts for logging */
-	rv |= main_write8(chgnum, SM5803_REG_INT4_EN, SM5803_INT4_CHG_FAIL |
-						      SM5803_INT4_CHG_DONE |
-						      SM5803_INT4_OTG_FAIL);
+	rv |= main_write8(chgnum, SM5803_REG_INT4_EN,
+			  SM5803_INT4_CHG_FAIL | SM5803_INT4_CHG_DONE |
+				  SM5803_INT4_OTG_FAIL);
 
 	/* Set TINT interrupts for higher threshold 360 K */
 	rv |= meas_write8(chgnum, SM5803_REG_TINT_HIGH_TH,
-						SM5803_TINT_HIGH_LEVEL);
+			  SM5803_TINT_HIGH_LEVEL);
 	/*
 	 * Set TINT interrupts for lower threshold to 0 when not
 	 * throttled to prevent trigger interrupts continually
 	 */
 	rv |= meas_write8(chgnum, SM5803_REG_TINT_LOW_TH,
-						SM5803_TINT_MIN_LEVEL);
+			  SM5803_TINT_MIN_LEVEL);
 
 	/*
 	 * Configure VBAT_SNSP high interrupt to fire after thresholds are set.
@@ -695,7 +734,6 @@ static void sm5803_init(int chgnum)
 	reg |= SM5803_INT2_VBATSNSP;
 	rv |= main_write8(chgnum, SM5803_REG_INT2_EN, reg);
 
-
 	/* Configure TINT interrupts to fire after thresholds are set */
 	rv |= main_write8(chgnum, SM5803_REG_INT2_EN, SM5803_INT2_TINT);
 
@@ -706,40 +744,52 @@ static void sm5803_init(int chgnum)
 	rv |= chg_write8(chgnum, SM5803_REG_FLOW2, SM5803_FLOW2_HOST_MODE_EN);
 
 	if (chgnum == CHARGER_PRIMARY) {
-		int ibat_eoc_ma;
+		if (IS_ENABLED(CONFIG_BATTERY)) {
+			const struct battery_info *batt_info;
+			int ibat_eoc_ma;
+			int pre_term;
+			int cells;
+
+			/* Set end of fast charge threshold */
+			batt_info = battery_get_info();
+			ibat_eoc_ma = batt_info->precharge_current - 50;
+			ibat_eoc_ma /= 100;
+			ibat_eoc_ma =
+				CLAMP(ibat_eoc_ma, 0, SM5803_CONF5_IBAT_EOC_TH);
+			rv |= chg_read8(chgnum, SM5803_REG_FAST_CONF5, &reg);
+			reg &= ~SM5803_CONF5_IBAT_EOC_TH;
+			reg |= ibat_eoc_ma;
+			rv |= chg_write8(CHARGER_PRIMARY, SM5803_REG_FAST_CONF5,
+					 reg);
+
+			/* Setup the proper precharge thresholds. */
+			cells = batt_info->voltage_max / 4;
+			pre_term = batt_info->voltage_min / cells;
+			/* Convert to decivolts. */
+			pre_term /= 100;
+			pre_term = CLAMP(pre_term, SM5803_VBAT_PRE_TERM_MIN_DV,
+					 SM5803_VBAT_PRE_TERM_MAX_DV);
+			/* Convert to regval */
+			pre_term -= SM5803_VBAT_PRE_TERM_MIN_DV;
+
+			rv |= chg_read8(chgnum, SM5803_REG_PRE_FAST_CONF_REG1,
+					&reg);
+			reg &= ~SM5803_VBAT_PRE_TERM;
+			reg |= pre_term << SM5803_VBAT_PRE_TERM_SHIFT;
+			rv |= chg_write8(chgnum, SM5803_REG_PRE_FAST_CONF_REG1,
+					 reg);
 
-		/* Set end of fast charge threshold */
-		batt_info = battery_get_info();
-		ibat_eoc_ma = batt_info->precharge_current - 50;
-		ibat_eoc_ma /= 100;
-		ibat_eoc_ma = CLAMP(ibat_eoc_ma, 0, SM5803_CONF5_IBAT_EOC_TH);
-		rv |= chg_read8(chgnum, SM5803_REG_FAST_CONF5, &reg);
-		reg &= ~SM5803_CONF5_IBAT_EOC_TH;
-		reg |= ibat_eoc_ma;
-		rv |= chg_write8(CHARGER_PRIMARY, SM5803_REG_FAST_CONF5, reg);
-
-		/* Setup the proper precharge thresholds. */
-		cells = batt_info->voltage_max / 4;
-		pre_term = batt_info->voltage_min / cells;
-		pre_term /= 100; /* Convert to decivolts. */
-		pre_term = CLAMP(pre_term, SM5803_VBAT_PRE_TERM_MIN_DV,
-				 SM5803_VBAT_PRE_TERM_MAX_DV);
-		pre_term -= SM5803_VBAT_PRE_TERM_MIN_DV; /* Convert to regval */
-
-		rv |= chg_read8(chgnum, SM5803_REG_PRE_FAST_CONF_REG1, &reg);
-		reg &= ~SM5803_VBAT_PRE_TERM;
-		reg |= pre_term << SM5803_VBAT_PRE_TERM_SHIFT;
-		rv |= chg_write8(chgnum, SM5803_REG_PRE_FAST_CONF_REG1, reg);
-
-		/*
-		 * Set up precharge current
-		 * Note it is preferred to under-shoot the precharge current
-		 * requested. Upper bits of this register are read/write 1 to
-		 * clear
-		 */
-		reg = SM5803_CURRENT_TO_REG(batt_info->precharge_current);
-		reg = MIN(reg, SM5803_PRECHG_ICHG_PRE_SET);
-		rv |= chg_write8(chgnum, SM5803_REG_PRECHG, reg);
+			/*
+			 * Set up precharge current
+			 * Note it is preferred to under-shoot the precharge
+			 * current requested. Upper bits of this register are
+			 * read/write 1 to clear
+			 */
+			reg = SM5803_CURRENT_TO_REG(
+				batt_info->precharge_current);
+			reg = MIN(reg, SM5803_PRECHG_ICHG_PRE_SET);
+			rv |= chg_write8(chgnum, SM5803_REG_PRECHG, reg);
+		}
 
 		/*
 		 * Set up BFET alerts
@@ -752,7 +802,7 @@ static void sm5803_init(int chgnum)
 		rv |= meas_write8(chgnum, SM5803_REG_BFET_PWR_MAX_TH, reg);
 		reg = (6000 * 10) / 292;
 		rv |= meas_write8(chgnum, SM5803_REG_BFET_PWR_HWSAFE_MAX_TH,
-				 reg);
+				  reg);
 		rv |= main_read8(chgnum, SM5803_REG_INT3_EN, &reg);
 		reg |= SM5803_INT3_BFET_PWR_LIMIT |
 		       SM5803_INT3_BFET_PWR_HWSAFE_LIMIT;
@@ -838,10 +888,9 @@ static void sm5803_disable_runtime_low_power_mode(void)
 			chgnum);
 		return;
 	}
-	/* Set a higher clock speed */
-	rv |= main_read8(chgnum, SM5803_REG_CLOCK_SEL, &reg);
-	reg &= ~SM5803_CLOCK_SEL_LOW;
-	rv |= main_write8(chgnum, SM5803_REG_CLOCK_SEL, reg);
+
+	/* Reset clocks and enable GPADCs */
+	rv = sm5803_set_active_safe(chgnum);
 
 	/* Enable ADC sigma delta */
 	rv |= chg_read8(chgnum, SM5803_REG_CC_CONFIG1, &reg);
@@ -852,10 +901,10 @@ static void sm5803_disable_runtime_low_power_mode(void)
 		CPRINTS("%s %d: Failed to set in disable runtime LPM",
 			CHARGER_NAME, chgnum);
 }
-DECLARE_HOOK(HOOK_USB_PD_CONNECT,
-		sm5803_disable_runtime_low_power_mode,
-		HOOK_PRIO_FIRST);
+DECLARE_HOOK(HOOK_USB_PD_CONNECT, sm5803_disable_runtime_low_power_mode,
+	     HOOK_PRIO_FIRST);
 
+#ifdef CONFIG_BATTERY
 static enum ec_error_list sm5803_enable_linear_charge(int chgnum, bool enable)
 {
 	int rv;
@@ -883,18 +932,15 @@ static enum ec_error_list sm5803_enable_linear_charge(int chgnum, bool enable)
 					 batt_info->precharge_current);
 
 		/* Enable linear charge mode. */
-		rv |= sm5803_flow1_update(chgnum,
-					  SM5803_FLOW1_LINEAR_CHARGE_EN,
-					 MASK_SET);
+		rv |= sm5803_flow1_update(chgnum, SM5803_FLOW1_LINEAR_CHARGE_EN,
+					  MASK_SET);
 		rv |= chg_read8(chgnum, SM5803_REG_FLOW3, &regval);
 		regval |= BIT(6) | BIT(5) | BIT(4);
 		rv |= chg_write8(chgnum, SM5803_REG_FLOW3, regval);
 	} else {
-		rv = sm5803_flow1_update(chgnum,
-					 SM5803_FLOW1_LINEAR_CHARGE_EN,
+		rv = sm5803_flow1_update(chgnum, SM5803_FLOW1_LINEAR_CHARGE_EN,
 					 MASK_CLR);
-		rv |= sm5803_flow2_update(chgnum,
-					  SM5803_FLOW2_AUTO_ENABLED,
+		rv |= sm5803_flow2_update(chgnum, SM5803_FLOW2_AUTO_ENABLED,
 					  MASK_CLR);
 		rv |= chg_read8(chgnum, SM5803_REG_FLOW3, &regval);
 		regval &= ~(BIT(6) | BIT(5) | BIT(4) |
@@ -907,6 +953,7 @@ static enum ec_error_list sm5803_enable_linear_charge(int chgnum, bool enable)
 
 	return rv;
 }
+#endif
 
 static void sm5803_enable_runtime_low_power_mode(void)
 {
@@ -921,10 +968,22 @@ static void sm5803_enable_runtime_low_power_mode(void)
 			chgnum);
 		return;
 	}
-	/* Slow the clock speed */
-	rv |= main_read8(chgnum, SM5803_REG_CLOCK_SEL, &reg);
-	reg |= SM5803_CLOCK_SEL_LOW;
-	rv |= main_write8(chgnum, SM5803_REG_CLOCK_SEL, reg);
+
+	/*
+	 * Turn off GPADCs.
+	 *
+	 * This is only safe to do if the charger is inactive. We ensure that
+	 * they are enabled again in sm5803_set_active_safe() before the charger
+	 * is enabled, and verify here that the charger is not currently active.
+	 */
+	rv |= chg_read8(chgnum, SM5803_REG_FLOW1, &reg);
+	if (rv == 0 && (reg & SM5803_FLOW1_MODE) == CHARGER_MODE_DISABLED) {
+		rv |= meas_write8(chgnum, SM5803_REG_GPADC_CONFIG1, 0);
+		rv |= meas_write8(chgnum, SM5803_REG_GPADC_CONFIG2, 0);
+	} else {
+		CPRINTS("%s %d: FLOW1 %x is active! Not disabling GPADCs",
+			CHARGER_NAME, chgnum, reg);
+	}
 
 	/* Disable ADC sigma delta */
 	rv |= chg_read8(chgnum, SM5803_REG_CC_CONFIG1, &reg);
@@ -939,13 +998,17 @@ static void sm5803_enable_runtime_low_power_mode(void)
 		rv |= chg_write8(chgnum, SM5803_REG_PHOT1, reg);
 	}
 
+	/* Slow the clock speed */
+	rv |= main_read8(chgnum, SM5803_REG_CLOCK_SEL, &reg);
+	reg |= SM5803_CLOCK_SEL_LOW;
+	rv |= main_write8(chgnum, SM5803_REG_CLOCK_SEL, reg);
+
 	if (rv)
 		CPRINTS("%s %d: Failed to set in enable runtime LPM",
 			CHARGER_NAME, chgnum);
 }
-DECLARE_HOOK(HOOK_USB_PD_DISCONNECT,
-		sm5803_enable_runtime_low_power_mode,
-		HOOK_PRIO_LAST);
+DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, sm5803_enable_runtime_low_power_mode,
+	     HOOK_PRIO_LAST);
 
 void sm5803_disable_low_power_mode(int chgnum)
 {
@@ -1004,7 +1067,6 @@ void sm5803_enable_low_power_mode(int chgnum)
 		reg |= SM5803_PHOT1_VBUS_MON_EN;
 	rv |= chg_write8(chgnum, SM5803_REG_PHOT1, reg);
 
-
 	if (rv)
 		CPRINTS("%s %d: Failed to set in enable low power mode",
 			CHARGER_NAME, chgnum);
@@ -1025,8 +1087,8 @@ void sm5803_restart_charging(void)
 			 * Enough time has passed since our last failure,
 			 * restart the timing and count from now.
 			 */
-			failure_tracker[act_chg].time.val = now.val +
-						CHARGING_FAILURE_INTERVAL;
+			failure_tracker[act_chg].time.val =
+				now.val + CHARGING_FAILURE_INTERVAL;
 			failure_tracker[act_chg].count = 1;
 
 			sm5803_vbus_sink_enable(act_chg, 1);
@@ -1052,8 +1114,7 @@ void sm5803_handle_interrupt(int chgnum)
 	enum ec_error_list rv;
 	int int_reg, meas_reg;
 	static bool throttled;
-	struct batt_params bp;
-	int act_chg, val;
+	int act_chg;
 
 	/* Note: Interrupt registers are clear on read */
 	rv = main_read8(chgnum, SM5803_REG_INT1_REQ, &int_reg);
@@ -1089,27 +1150,27 @@ void sm5803_handle_interrupt(int chgnum)
 		if ((meas_reg <= SM5803_TINT_LOW_LEVEL) && throttled) {
 			throttled = false;
 			throttle_ap(THROTTLE_OFF, THROTTLE_HARD,
-							THROTTLE_SRC_THERMAL);
+				    THROTTLE_SRC_THERMAL);
 			/*
 			 * Set back higher threshold to 360 K and set lower
 			 * threshold to 0.
 			 */
 			rv |= meas_write8(chgnum, SM5803_REG_TINT_LOW_TH,
-							SM5803_TINT_MIN_LEVEL);
+					  SM5803_TINT_MIN_LEVEL);
 			rv |= meas_write8(chgnum, SM5803_REG_TINT_HIGH_TH,
-							SM5803_TINT_HIGH_LEVEL);
+					  SM5803_TINT_HIGH_LEVEL);
 		} else if (meas_reg >= SM5803_TINT_HIGH_LEVEL) {
 			throttled = true;
 			throttle_ap(THROTTLE_ON, THROTTLE_HARD,
-							THROTTLE_SRC_THERMAL);
+				    THROTTLE_SRC_THERMAL);
 			/*
 			 * Set back lower threshold to 330 K and set higher
 			 * threshold to maximum.
 			 */
 			rv |= meas_write8(chgnum, SM5803_REG_TINT_HIGH_TH,
-							SM5803_TINT_MAX_LEVEL);
+					  SM5803_TINT_MAX_LEVEL);
 			rv |= meas_write8(chgnum, SM5803_REG_TINT_LOW_TH,
-							SM5803_TINT_LOW_LEVEL);
+					  SM5803_TINT_LOW_LEVEL);
 		}
 		/*
 		 * If the interrupt came in and we're not currently throttling
@@ -1125,25 +1186,23 @@ void sm5803_handle_interrupt(int chgnum)
 		rv = main_read8(chgnum, SM5803_REG_PLATFORM, &platform_id);
 		if (rv) {
 			CPRINTS("%s %d: Failed to read platform in interrupt",
-							CHARGER_NAME, chgnum);
+				CHARGER_NAME, chgnum);
 			return;
 		}
 		platform_id &= SM5803_PLATFORM_ID;
 		act_chg = charge_manager_get_active_charge_port();
-		rv = meas_read8(CHARGER_PRIMARY,
-					SM5803_REG_VBATSNSP_MEAS_MSB,
-					&meas_reg);
+		rv = meas_read8(CHARGER_PRIMARY, SM5803_REG_VBATSNSP_MEAS_MSB,
+				&meas_reg);
 		if (rv)
 			return;
 		meas_volt = meas_reg << 2;
-		rv = meas_read8(CHARGER_PRIMARY,
-					SM5803_REG_VBATSNSP_MEAS_LSB,
-					&meas_reg);
+		rv = meas_read8(CHARGER_PRIMARY, SM5803_REG_VBATSNSP_MEAS_LSB,
+				&meas_reg);
 		if (rv)
 			return;
 		meas_volt |= meas_reg & 0x03;
-		rv = meas_read8(CHARGER_PRIMARY,
-			SM5803_REG_VBATSNSP_MAX_TH, &meas_reg);
+		rv = meas_read8(CHARGER_PRIMARY, SM5803_REG_VBATSNSP_MAX_TH,
+				&meas_reg);
 		if (rv)
 			return;
 
@@ -1152,8 +1211,7 @@ void sm5803_handle_interrupt(int chgnum)
 			CPRINTS("%s %d : VBAT_SNSP_HIGH_TH: %d mV ! - "
 				"VBAT %d mV",
 				CHARGER_NAME, CHARGER_PRIMARY,
-				meas_reg * 408/10,
-				meas_volt * 102/10);
+				meas_reg * 408 / 10, meas_volt * 102 / 10);
 		}
 
 		if (is_platform_id_3s(platform_id)) {
@@ -1161,28 +1219,27 @@ void sm5803_handle_interrupt(int chgnum)
 			CPRINTS("%s %d : VBAT_SNSP_HIGH_TH: %d mV ! "
 				"- VBAT %d mV",
 				CHARGER_NAME, CHARGER_PRIMARY,
-				meas_reg * 616/10,
-				meas_volt * 154/10);
+				meas_reg * 616 / 10, meas_volt * 154 / 10);
 		}
 
 		/* Set Vbat Threshold to Max value to re-arm the interrupt */
-		rv = meas_write8(CHARGER_PRIMARY,
-			SM5803_REG_VBATSNSP_MAX_TH, 0xFF);
+		rv = meas_write8(CHARGER_PRIMARY, SM5803_REG_VBATSNSP_MAX_TH,
+				 0xFF);
 
 		/* Disable battery charge */
 		rv |= sm5803_flow1_update(chgnum, CHARGER_MODE_DISABLED,
-			MASK_CLR);
+					  MASK_CLR);
 		if (is_platform_id_2s(platform_id)) {
 			/* 2S battery: set VBAT_SENSP TH 9V */
 			rv |= meas_write8(CHARGER_PRIMARY,
-				SM5803_REG_VBATSNSP_MAX_TH,
-				SM5803_VBAT_SNSP_MAXTH_2S_LEVEL);
+					  SM5803_REG_VBATSNSP_MAX_TH,
+					  SM5803_VBAT_SNSP_MAXTH_2S_LEVEL);
 		}
 		if (is_platform_id_3s(platform_id)) {
 			/* 3S battery: set VBAT_SENSP TH 13.3V */
 			rv |= meas_write8(CHARGER_PRIMARY,
-				SM5803_REG_VBATSNSP_MAX_TH,
-				SM5803_VBAT_SNSP_MAXTH_3S_LEVEL);
+					  SM5803_REG_VBATSNSP_MAX_TH,
+					  SM5803_VBAT_SNSP_MAXTH_3S_LEVEL);
 		}
 
 		active_restart_port = act_chg;
@@ -1197,13 +1254,17 @@ void sm5803_handle_interrupt(int chgnum)
 		return;
 	}
 
-	if ((int_reg & SM5803_INT3_BFET_PWR_LIMIT) ||
-	    (int_reg & SM5803_INT3_BFET_PWR_HWSAFE_LIMIT)) {
+	if (IS_ENABLED(CONFIG_BATTERY) &&
+	    ((int_reg & SM5803_INT3_BFET_PWR_LIMIT) ||
+	     (int_reg & SM5803_INT3_BFET_PWR_HWSAFE_LIMIT))) {
+		struct batt_params bp;
+		int val;
+
 		battery_get_params(&bp);
 		act_chg = charge_manager_get_active_charge_port();
 		CPRINTS("%s BFET power limit reached! (%s)", CHARGER_NAME,
 			(int_reg & SM5803_INT3_BFET_PWR_LIMIT) ? "warn" :
-			"FATAL");
+								 "FATAL");
 		CPRINTS("\tVbat: %dmV", bp.voltage);
 		CPRINTS("\tIbat: %dmA", bp.current);
 		charger_get_voltage(act_chg, &val);
@@ -1240,7 +1301,7 @@ void sm5803_handle_interrupt(int chgnum)
 			hook_call_deferred(&sm5803_restart_charging_data,
 					   30 * SECOND);
 		} else if ((status_reg & SM5803_STATUS_CHG_OV_VBAT) &&
-						act_chg == CHARGER_PRIMARY) {
+			   act_chg == CHARGER_PRIMARY) {
 			active_restart_port = act_chg;
 			hook_call_deferred(&sm5803_restart_charging_data,
 					   1 * SECOND);
@@ -1272,11 +1333,12 @@ void sm5803_handle_interrupt(int chgnum)
 		 * will detect us as sinking in this failure case.
 		 */
 		if (status_reg == 0)
-			rv = sm5803_flow1_update(chgnum, CHARGER_MODE_SOURCE |
-						 SM5803_FLOW1_DIRECTCHG_SRC_EN,
-						 MASK_CLR);
+			rv = sm5803_flow1_update(
+				chgnum,
+				CHARGER_MODE_SOURCE |
+					SM5803_FLOW1_DIRECTCHG_SRC_EN,
+				MASK_CLR);
 	}
-
 }
 
 static void sm5803_irq_deferred(void)
@@ -1307,7 +1369,6 @@ static enum ec_error_list sm5803_get_dev_id(int chgnum, int *id)
 		*id = dev_id;
 
 	return rv;
-
 }
 
 static const struct charger_info *sm5803_get_info(int chgnum)
@@ -1327,7 +1388,6 @@ static enum ec_error_list sm5803_get_status(int chgnum, int *status)
 	if (rv)
 		return rv;
 
-
 	if ((reg & SM5803_FLOW1_MODE) == CHARGER_MODE_DISABLED &&
 	    !(reg & SM5803_FLOW1_LINEAR_CHARGE_EN))
 		*status |= CHARGER_CHARGE_INHIBITED;
@@ -1389,6 +1449,18 @@ static enum ec_error_list sm5803_set_current(int chgnum, int current)
 	enum ec_error_list rv;
 	int reg;
 
+	if (current == 0) {
+		/*
+		 * Per Silicon Mitus, setting the fast charge current limit to 0
+		 * causes "much unstable". This normally happens when the
+		 * battery is fully charged (so we don't expect fast charge to
+		 * be in use): turn 0 into the minimum nonzero value so we
+		 * avoid setting this register to 0 but still make the requested
+		 * current as small as possible.
+		 */
+		current = SM5803_REG_TO_CURRENT(1);
+	}
+
 	rv = chg_read8(chgnum, SM5803_REG_FAST_CONF4, &reg);
 	if (rv)
 		return rv;
@@ -1459,9 +1531,9 @@ static enum ec_error_list sm5803_set_voltage(int chgnum, int voltage)
 
 	/* Once battery is connected, set up fast charge enable */
 	if (fast_charge_disabled && chgnum == CHARGER_PRIMARY &&
+	    IS_ENABLED(CONFIG_BATTERY) &&
 	    battery_get_disconnect_state() == BATTERY_NOT_DISCONNECTED) {
-		rv = sm5803_flow2_update(chgnum,
-					 SM5803_FLOW2_AUTO_ENABLED,
+		rv = sm5803_flow2_update(chgnum, SM5803_FLOW2_AUTO_ENABLED,
 					 MASK_SET);
 		fast_charge_disabled = false;
 	}
@@ -1509,12 +1581,20 @@ static enum ec_error_list sm5803_discharge_on_ac(int chgnum, int enable)
 }
 
 static enum ec_error_list sm5803_get_vbus_voltage(int chgnum, int port,
-						   int *voltage)
+						  int *voltage)
 {
 	enum ec_error_list rv;
 	int reg;
 	int volt_bits;
 
+	rv = meas_read8(chgnum, SM5803_REG_GPADC_CONFIG1, &reg);
+	if (rv)
+		return rv;
+	if ((reg & SM5803_GPADCC1_VBUS_EN) == 0) {
+		/* VBUS ADC is currently disabled */
+		return EC_ERROR_NOT_POWERED;
+	}
+
 	rv = meas_read8(chgnum, SM5803_REG_VBUS_MEAS_MSB, &reg);
 	if (rv)
 		return rv;
@@ -1530,6 +1610,54 @@ static enum ec_error_list sm5803_get_vbus_voltage(int chgnum, int port,
 	return rv;
 }
 
+bool sm5803_check_vbus_level(int chgnum, enum vbus_level level)
+{
+	int rv, vbus_voltage;
+
+	/*
+	 * Analog reading of VBUS is more accurate and helps reliability when
+	 * doing power role swaps, but if the charger is in LPM with the GPADCs
+	 * disabled then the reading won't update.
+	 *
+	 * Digital VBUS presence (with transitions flagged by STATUS1_CHG_DET
+	 * interrupt) still works when GPADCs are off, and shouldn't otherwise
+	 * impact performance because the GPADCs should be enabled in any
+	 * situation where we're doing a PRS.
+	 */
+	rv = sm5803_get_vbus_voltage(chgnum, chgnum, &vbus_voltage);
+	if (rv == EC_ERROR_NOT_POWERED) {
+		/* VBUS ADC is disabled, use digital presence */
+		switch (level) {
+		case VBUS_PRESENT:
+			return sm5803_is_vbus_present(chgnum);
+		case VBUS_SAFE0V:
+		case VBUS_REMOVED:
+			return !sm5803_is_vbus_present(chgnum);
+		default:
+			CPRINTS("%s: unrecognized vbus_level value: %d",
+				__func__, level);
+			return false;
+		}
+	}
+	if (rv != EC_SUCCESS) {
+		/* Unhandled communication error; assume unsatisfied */
+		return false;
+	}
+
+	switch (level) {
+	case VBUS_PRESENT:
+		return vbus_voltage > PD_V_SAFE5V_MIN;
+	case VBUS_SAFE0V:
+		return vbus_voltage < PD_V_SAFE0V_MAX;
+	case VBUS_REMOVED:
+		return vbus_voltage < PD_V_SINK_DISCONNECT_MAX;
+	default:
+		CPRINTS("%s: unrecognized vbus_level value: %d", __func__,
+			level);
+		return false;
+	}
+}
+
 static enum ec_error_list sm5803_set_input_current_limit(int chgnum,
 							 int input_current)
 {
@@ -1678,13 +1806,13 @@ static enum ec_error_list sm5803_set_otg_current_voltage(int chgnum,
 
 	reg &= ~SM5803_DISCH_CONF5_CLS_LIMIT;
 	reg |= MIN((output_current / SM5803_CLS_CURRENT_STEP),
-						SM5803_DISCH_CONF5_CLS_LIMIT);
+		   SM5803_DISCH_CONF5_CLS_LIMIT);
 	rv |= chg_write8(chgnum, SM5803_REG_DISCH_CONF5, reg);
 
 	reg = SM5803_VOLTAGE_TO_REG(output_voltage);
 	rv = chg_write8(chgnum, SM5803_REG_VPWR_MSB, (reg >> 3));
 	rv |= chg_write8(chgnum, SM5803_REG_DISCH_CONF2,
-					reg & SM5803_DISCH_CONF5_VPWR_LSB);
+			 reg & SM5803_DISCH_CONF5_VPWR_LSB);
 
 	return rv;
 }
@@ -1697,6 +1825,11 @@ static enum ec_error_list sm5803_enable_otg_power(int chgnum, int enabled)
 	if (enabled) {
 		int selected_current;
 
+		rv = sm5803_set_active_safe(chgnum);
+		if (rv) {
+			return rv;
+		}
+
 		rv = chg_read8(chgnum, SM5803_REG_ANA_EN1, &reg);
 		if (rv)
 			return rv;
@@ -1720,7 +1853,7 @@ static enum ec_error_list sm5803_enable_otg_power(int chgnum, int enabled)
 			return rv;
 
 		selected_current = (reg & SM5803_DISCH_CONF5_CLS_LIMIT) *
-			SM5803_CLS_CURRENT_STEP;
+				   SM5803_CLS_CURRENT_STEP;
 		sm5803_set_otg_current_voltage(chgnum, selected_current, 4800);
 
 		/*
@@ -1728,8 +1861,9 @@ static enum ec_error_list sm5803_enable_otg_power(int chgnum, int enabled)
 		 *	   DIRECTCHG_SOURCE_EN - enable current loop
 		 *	   (for designs with no external Vbus FET)
 		 */
-		rv = sm5803_flow1_update(chgnum, CHARGER_MODE_SOURCE |
-					 SM5803_FLOW1_DIRECTCHG_SRC_EN,
+		rv = sm5803_flow1_update(chgnum,
+					 CHARGER_MODE_SOURCE |
+						 SM5803_FLOW1_DIRECTCHG_SRC_EN,
 					 MASK_SET);
 		usleep(4000);
 
@@ -1765,9 +1899,11 @@ static enum ec_error_list sm5803_enable_otg_power(int chgnum, int enabled)
 			return rv;
 
 		if ((reg & SM5803_FLOW1_MODE) != CHARGER_MODE_SINK || status)
-			rv = sm5803_flow1_update(chgnum, CHARGER_MODE_SOURCE |
-						 SM5803_FLOW1_DIRECTCHG_SRC_EN,
-						 MASK_CLR);
+			rv = sm5803_flow1_update(
+				chgnum,
+				CHARGER_MODE_SOURCE |
+					SM5803_FLOW1_DIRECTCHG_SRC_EN,
+				MASK_CLR);
 	}
 
 	return rv;
@@ -1794,7 +1930,6 @@ static enum ec_error_list sm5803_set_vsys_compensation(int chgnum,
 						       int current_ma,
 						       int voltage_mv)
 {
-
 	int rv;
 	int regval;
 	int r;
@@ -1928,7 +2063,9 @@ const struct charger_drv sm5803_drv = {
 	.is_sourcing_otg_power = &sm5803_is_sourcing_otg_power,
 	.set_vsys_compensation = &sm5803_set_vsys_compensation,
 	.is_icl_reached = &sm5803_is_input_current_limit_reached,
+#ifdef CONFIG_BATTERY
 	.enable_linear_charge = &sm5803_enable_linear_charge,
+#endif
 #ifdef CONFIG_CHARGE_RAMP_HW
 	.set_hw_ramp = &sm5803_set_hw_ramp,
 	.ramp_is_stable = &sm5803_ramp_is_stable,
diff --git a/driver/charger/sm5803.h b/driver/charger/sm5803.h
index b7638411e4..0343561f2f 100644
--- a/driver/charger/sm5803.h
+++ b/driver/charger/sm5803.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -9,94 +9,95 @@
 #define __CROS_EC_SM5803_H
 
 #include "common.h"
+#include "usb_pd_tcpm.h"
 
 /* Note: configure charger struct with CHARGER_FLAGS */
-#define SM5803_ADDR_MAIN_FLAGS		0x30
-#define SM5803_ADDR_MEAS_FLAGS		0x31
-#define SM5803_ADDR_CHARGER_FLAGS	0x32
-#define SM5803_ADDR_TEST_FLAGS		0x37
+#define SM5803_ADDR_MAIN_FLAGS 0x30
+#define SM5803_ADDR_MEAS_FLAGS 0x31
+#define SM5803_ADDR_CHARGER_FLAGS 0x32
+#define SM5803_ADDR_TEST_FLAGS 0x37
 
 /* Main registers (address 0x30) */
 
-#define SM5803_REG_CHIP_ID		0x00
-
-#define SM5803_REG_STATUS1		0x01
-#define SM5803_STATUS1_VSYS_OK		BIT(0)
-#define SM5803_STATUS1_VPWR_OK		BIT(1)
-#define SM5803_STATUS1_VBUS_UVL		BIT(3)
-#define SM5803_STATUS1_VBUS_SHORT	BIT(4)
-#define SM5803_STATUS1_VBUS_OVH		BIT(5)
-#define SM5803_STATUS1_CHG_DET		BIT(6)
-#define SM5803_STATUS1_BAT_DET		BIT(7)
-
-#define SM5803_REG_STATUS2		0x02
-#define SM5803_STATUS2_BAT_DET_FG	BIT(1)
-#define SM5803_STATUS2_VBAT_SHORT	BIT(0)
-
-#define SM5803_REG_INT1_REQ			0x05
-#define SM5803_REG_INT1_EN			0x0A
-#define SM5803_INT1_VBUS_PWR_HWSAFE_LIMIT	BIT(0)
-#define SM5803_INT1_CHG				BIT(2)
-#define SM5803_INT1_BAT				BIT(3)
-#define SM5803_INT1_CLS_OC			BIT(4)
-#define SM5803_INT1_SLV_DET			BIT(5)
-#define SM5803_INT1_SWL_DISCH			BIT(6)
-#define SM5803_INT1_PREREG			BIT(7)
-
-#define SM5803_REG_INT2_REQ		0x06
-#define SM5803_REG_INT2_EN		0x0B
-#define SM5803_INT2_VBATSNSP		BIT(0)
-#define SM5803_INT2_IBAT_DISCHG		BIT(1)
-#define SM5803_INT2_IBAT_CHG		BIT(2)
-#define SM5803_INT2_IBUS		BIT(3)
-#define SM5803_INT2_VBUS		BIT(4)
-#define SM5803_INT2_VCHGPWR		BIT(5)
-#define SM5803_INT2_VSYS		BIT(6)
-#define SM5803_INT2_TINT		BIT(7)
-
-#define SM5803_REG_INT3_REQ			0x07
-#define SM5803_REG_INT3_EN			0x0C
-#define SM5803_INT3_GPADC0			BIT(0)
-#define SM5803_INT3_BFET_PWR_LIMIT		BIT(1)
-#define SM5803_INT3_BFET_PWR_HWSAFE_LIMIT	BIT(2)
-#define SM5803_INT3_SPARE			BIT(3)
-#define SM5803_INT3_VBUS_PWR_LIMIT		BIT(4)
-#define SM5803_INT3_IBAT			BIT(5)
-
-#define SM5803_REG_INT4_REQ		0x08
-#define SM5803_REG_INT4_EN		0x0D
-#define SM5803_INT4_CHG_FAIL		BIT(0)
-#define SM5803_INT4_CHG_DONE		BIT(1)
-#define SM5803_INT4_CHG_START		BIT(2)
-#define SM5803_INT4_SLP_EXIT		BIT(3)
-#define SM5803_INT4_OTG_FAIL		BIT(4)
-#define SM5803_INT4_CHG_ILIM		BIT(5)
-#define SM5803_INT4_IBAT_CC		BIT(6)
-#define SM5803_INT4_CC			BIT(7)
-
-#define SM5803_REG_MISC_CONFIG		0x15
-#define SM5803_MISC_INV_INT		BIT(0)
-#define SM5803_INT_CLEAR_MODE		BIT(1)
-#define SM5803_INT_MASK_MODE		BIT(2)
-
-#define SM5803_REG_PLATFORM		0x18
-#define SM5803_PLATFORM_ID		GENMASK(4, 0)
-
-#define SM5803_REG_REFERENCE		0x20
-#define SM5803_REFERENCE_LDO3P3_PGOOD	BIT(4)
-#define SM5803_REFERENCE_LDO5_PGOOD	BIT(5)
-
-#define SM5803_REG_CLOCK_SEL		0x2A
-#define SM5803_CLOCK_SEL_LOW		BIT(0)
-
-#define SM5803_REG_GPIO0_CTRL		0x30
-#define SM5803_GPIO0_VAL		BIT(0)
-#define SM5803_GPIO0_MODE_MASK		GENMASK(2, 1)
-#define SM5803_GPIO0_OPEN_DRAIN_EN	BIT(6)
-#define SM5803_CHG_DET_OPEN_DRAIN_EN	BIT(7)
-
-#define SM5803_REG_VBATSNSP_MEAS_MSB	0x40
-#define SM5803_REG_VBATSNSP_MEAS_LSB	0x41
+#define SM5803_REG_CHIP_ID 0x00
+
+#define SM5803_REG_STATUS1 0x01
+#define SM5803_STATUS1_VSYS_OK BIT(0)
+#define SM5803_STATUS1_VPWR_OK BIT(1)
+#define SM5803_STATUS1_VBUS_UVL BIT(3)
+#define SM5803_STATUS1_VBUS_SHORT BIT(4)
+#define SM5803_STATUS1_VBUS_OVH BIT(5)
+#define SM5803_STATUS1_CHG_DET BIT(6)
+#define SM5803_STATUS1_BAT_DET BIT(7)
+
+#define SM5803_REG_STATUS2 0x02
+#define SM5803_STATUS2_BAT_DET_FG BIT(1)
+#define SM5803_STATUS2_VBAT_SHORT BIT(0)
+
+#define SM5803_REG_INT1_REQ 0x05
+#define SM5803_REG_INT1_EN 0x0A
+#define SM5803_INT1_VBUS_PWR_HWSAFE_LIMIT BIT(0)
+#define SM5803_INT1_CHG BIT(2)
+#define SM5803_INT1_BAT BIT(3)
+#define SM5803_INT1_CLS_OC BIT(4)
+#define SM5803_INT1_SLV_DET BIT(5)
+#define SM5803_INT1_SWL_DISCH BIT(6)
+#define SM5803_INT1_PREREG BIT(7)
+
+#define SM5803_REG_INT2_REQ 0x06
+#define SM5803_REG_INT2_EN 0x0B
+#define SM5803_INT2_VBATSNSP BIT(0)
+#define SM5803_INT2_IBAT_DISCHG BIT(1)
+#define SM5803_INT2_IBAT_CHG BIT(2)
+#define SM5803_INT2_IBUS BIT(3)
+#define SM5803_INT2_VBUS BIT(4)
+#define SM5803_INT2_VCHGPWR BIT(5)
+#define SM5803_INT2_VSYS BIT(6)
+#define SM5803_INT2_TINT BIT(7)
+
+#define SM5803_REG_INT3_REQ 0x07
+#define SM5803_REG_INT3_EN 0x0C
+#define SM5803_INT3_GPADC0 BIT(0)
+#define SM5803_INT3_BFET_PWR_LIMIT BIT(1)
+#define SM5803_INT3_BFET_PWR_HWSAFE_LIMIT BIT(2)
+#define SM5803_INT3_SPARE BIT(3)
+#define SM5803_INT3_VBUS_PWR_LIMIT BIT(4)
+#define SM5803_INT3_IBAT BIT(5)
+
+#define SM5803_REG_INT4_REQ 0x08
+#define SM5803_REG_INT4_EN 0x0D
+#define SM5803_INT4_CHG_FAIL BIT(0)
+#define SM5803_INT4_CHG_DONE BIT(1)
+#define SM5803_INT4_CHG_START BIT(2)
+#define SM5803_INT4_SLP_EXIT BIT(3)
+#define SM5803_INT4_OTG_FAIL BIT(4)
+#define SM5803_INT4_CHG_ILIM BIT(5)
+#define SM5803_INT4_IBAT_CC BIT(6)
+#define SM5803_INT4_CC BIT(7)
+
+#define SM5803_REG_MISC_CONFIG 0x15
+#define SM5803_MISC_INV_INT BIT(0)
+#define SM5803_INT_CLEAR_MODE BIT(1)
+#define SM5803_INT_MASK_MODE BIT(2)
+
+#define SM5803_REG_PLATFORM 0x18
+#define SM5803_PLATFORM_ID GENMASK(4, 0)
+
+#define SM5803_REG_REFERENCE 0x20
+#define SM5803_REFERENCE_LDO3P3_PGOOD BIT(4)
+#define SM5803_REFERENCE_LDO5_PGOOD BIT(5)
+
+#define SM5803_REG_CLOCK_SEL 0x2A
+#define SM5803_CLOCK_SEL_LOW BIT(0)
+
+#define SM5803_REG_GPIO0_CTRL 0x30
+#define SM5803_GPIO0_VAL BIT(0)
+#define SM5803_GPIO0_MODE_MASK GENMASK(2, 1)
+#define SM5803_GPIO0_OPEN_DRAIN_EN BIT(6)
+#define SM5803_CHG_DET_OPEN_DRAIN_EN BIT(7)
+
+#define SM5803_REG_VBATSNSP_MEAS_MSB 0x40
+#define SM5803_REG_VBATSNSP_MEAS_LSB 0x41
 
 enum sm5803_gpio0_modes {
 	GPIO0_MODE_PROCHOT,
@@ -104,14 +105,14 @@ enum sm5803_gpio0_modes {
 	GPIO0_MODE_INPUT
 };
 
-#define SM5803_REG_BFET_PWR_MAX_TH		0x35
-#define SM5803_REG_BFET_PWR_HWSAFE_MAX_TH	0x36
+#define SM5803_REG_BFET_PWR_MAX_TH 0x35
+#define SM5803_REG_BFET_PWR_HWSAFE_MAX_TH 0x36
 
-#define SM5803_REG_PORTS_CTRL		0x40
-#define SM5803_PORTS_VBUS_DISCH		BIT(0)
-#define SM5803_PORTS_VBUS_PULLDOWN	BIT(1)
-#define SM5803_PORTS_VBUS_SNS_DISCH	BIT(2)
-#define SM5803_PORTS_VBUS_SNS_PULLDOWN	BIT(3)
+#define SM5803_REG_PORTS_CTRL 0x40
+#define SM5803_PORTS_VBUS_DISCH BIT(0)
+#define SM5803_PORTS_VBUS_PULLDOWN BIT(1)
+#define SM5803_PORTS_VBUS_SNS_DISCH BIT(2)
+#define SM5803_PORTS_VBUS_SNS_PULLDOWN BIT(3)
 
 /* ADC Registers (address 0x31) */
 
@@ -119,48 +120,58 @@ enum sm5803_gpio0_modes {
  * Note: Some register bits must be enabled for the DC-DC converter to properly
  * handle transitions.
  */
-#define SM5803_REG_GPADC_CONFIG1	0x01
-#define SM5803_GPADCC1_VBATSNSP_EN	BIT(0)
-#define SM5803_GPADCC1_IBAT_DIS_EN	BIT(1)
-#define SM5803_GPADCC1_IBAT_CHG_EN	BIT(2)
-#define SM5803_GPADCC1_IBUS_EN		BIT(3)
-#define SM5803_GPADCC1_VBUS_EN		BIT(4)
-#define SM5803_GPADCC1_VCHGPWR_EN	BIT(5)  /* NOTE: DO NOT CLEAR */
-#define SM5803_GPADCC1_VSYS_EN		BIT(6)  /* NOTE: DO NOT CLEAR */
-#define SM5803_GPADCC1_TINT_EN		BIT(7)
+#define SM5803_REG_GPADC_CONFIG1 0x01
+#define SM5803_GPADCC1_VBATSNSP_EN BIT(0)
+#define SM5803_GPADCC1_IBAT_DIS_EN BIT(1)
+#define SM5803_GPADCC1_IBAT_CHG_EN BIT(2)
+#define SM5803_GPADCC1_IBUS_EN BIT(3)
+#define SM5803_GPADCC1_VBUS_EN BIT(4)
+#define SM5803_GPADCC1_VCHGPWR_EN BIT(5) /* NOTE: DO NOT CLEAR */
+#define SM5803_GPADCC1_VSYS_EN BIT(6) /* NOTE: DO NOT CLEAR */
+#define SM5803_GPADCC1_TINT_EN BIT(7)
 
-#define SM5803_REG_GPADC_CONFIG2	0x02
+/*
+ * Default value for GPADCC1, set at initialization: the normal operating state.
+ *
+ * IBAT_CHG is enabled in order to measure battery current and calculate system
+ * resistance.
+ */
+#define SM5803_GPADCC1_DEFAULT_ENABLE                              \
+	(SM5803_GPADCC1_TINT_EN | SM5803_GPADCC1_VSYS_EN |         \
+	 SM5803_GPADCC1_VCHGPWR_EN | SM5803_GPADCC1_VBUS_EN |      \
+	 SM5803_GPADCC1_IBAT_CHG_EN | SM5803_GPADCC1_IBAT_DIS_EN | \
+	 SM5803_GPADCC1_VBATSNSP_EN)
 
-#define SM5803_REG_PSYS1		0x04
-#define SM5803_PSYS1_DAC_EN		BIT(0)
+#define SM5803_REG_GPADC_CONFIG2 0x02
+
+#define SM5803_REG_PSYS1 0x04
+#define SM5803_PSYS1_DAC_EN BIT(0)
 
 /* Note: Threshold registers all assume lower 2 bits are 0 */
-#define SM5803_REG_VBUS_LOW_TH		0x1A
-#define SM5803_REG_VBATSNSP_MAX_TH  0x26
-#define SM5803_REG_VBUS_HIGH_TH		0x2A
-#define SM5803_REG_VCHG_PWR_LOW_TH	0x1B
-#define SM5803_REG_VCHG_PWR_HIGH_TH	0x2B
-#define SM5803_REG_TINT_LOW_TH		0x1D
-#define SM5803_REG_TINT_HIGH_TH		0x2D
+#define SM5803_REG_VBUS_LOW_TH 0x1A
+#define SM5803_REG_VBATSNSP_MAX_TH 0x26
+#define SM5803_REG_VBUS_HIGH_TH 0x2A
+#define SM5803_REG_VCHG_PWR_LOW_TH 0x1B
+#define SM5803_REG_VCHG_PWR_HIGH_TH 0x2B
+#define SM5803_REG_TINT_LOW_TH 0x1D
+#define SM5803_REG_TINT_HIGH_TH 0x2D
 
 /*
  * Vbus levels increment in 23.4 mV, set thresholds to below 3.5V and above 4.0V
  * to mirror what TCPCI uses for Vbus present indication
  */
-#define SM5803_VBUS_LOW_LEVEL		0x25
-#define SM5803_VBUS_HIGH_LEVEL		0x2C
-
-
+#define SM5803_VBUS_LOW_LEVEL 0x25
+#define SM5803_VBUS_HIGH_LEVEL 0x2C
 
 /*
  * TINT thresholds.  TINT steps are in 0.43 K with the upper threshold set to
  * 360 K and lower threshold to de-assert PROCHOT at 330 K.
  */
-#define SM5803_TINT_LOW_LEVEL		0xBF
-#define SM5803_TINT_HIGH_LEVEL		0xD1
+#define SM5803_TINT_LOW_LEVEL 0xBF
+#define SM5803_TINT_HIGH_LEVEL 0xD1
 
-#define SM5803_TINT_MAX_LEVEL		0xFF
-#define SM5803_TINT_MIN_LEVEL		0x00
+#define SM5803_TINT_MAX_LEVEL 0xFF
+#define SM5803_TINT_MIN_LEVEL 0x00
 
 /*
  * Set minimum thresholds for VBUS_PWR_LOW_TH interrupt generation
@@ -179,47 +190,47 @@ enum sm5803_gpio0_modes {
 #define SM5803_VBAT_SNSP_MAXTH_2S_LEVEL 0xDC
 
 /* IBAT levels - The IBAT levels increment in 7.32mA */
-#define SM5803_REG_IBAT_CHG_MEAS_MSB		0x44
-#define SM5803_REG_IBAT_CHG_MEAS_LSB		0x45
-#define SM5803_REG_IBAT_CHG_AVG_MEAS_MSB	0xC4
-#define SM5803_REG_IBAT_CHG_AVG_MEAS_LSB	0xC5
-#define SM5803_IBAT_CHG_MEAS_LSB	GENMASK(1, 0)
+#define SM5803_REG_IBAT_CHG_MEAS_MSB 0x44
+#define SM5803_REG_IBAT_CHG_MEAS_LSB 0x45
+#define SM5803_REG_IBAT_CHG_AVG_MEAS_MSB 0xC4
+#define SM5803_REG_IBAT_CHG_AVG_MEAS_LSB 0xC5
+#define SM5803_IBAT_CHG_MEAS_LSB GENMASK(1, 0)
 
 /* IBUS levels - The IBUS levels increment in 7.32mA */
-#define SM5803_REG_IBUS_CHG_MEAS_MSB	0x46
-#define SM5803_REG_IBUS_CHG_MEAS_LSB	0x47
-#define SM5803_IBUS_CHG_MEAS_LSB	GENMASK(1, 0)
-
-#define SM5803_REG_VBUS_MEAS_MSB	0x48
-#define SM5803_REG_VBUS_MEAS_LSB	0x49
-#define SM5803_VBUS_MEAS_LSB		GENMASK(1, 0)
-#define SM5803_VBUS_MEAS_BAT_DET	BIT(2)
-#define SM5803_VBUS_MEAS_VBUS_SHORT	BIT(4)
-#define SM5803_VBUS_MEAS_OV_TEMP	BIT(5)
-#define SM5803_VBUS_MEAS_CHG_DET	BIT(6)
+#define SM5803_REG_IBUS_CHG_MEAS_MSB 0x46
+#define SM5803_REG_IBUS_CHG_MEAS_LSB 0x47
+#define SM5803_IBUS_CHG_MEAS_LSB GENMASK(1, 0)
+
+#define SM5803_REG_VBUS_MEAS_MSB 0x48
+#define SM5803_REG_VBUS_MEAS_LSB 0x49
+#define SM5803_VBUS_MEAS_LSB GENMASK(1, 0)
+#define SM5803_VBUS_MEAS_BAT_DET BIT(2)
+#define SM5803_VBUS_MEAS_VBUS_SHORT BIT(4)
+#define SM5803_VBUS_MEAS_OV_TEMP BIT(5)
+#define SM5803_VBUS_MEAS_CHG_DET BIT(6)
 
 /* VCHGPWR levels - The VCHGPWR levels increment in 23.4mV steps. */
-#define SM5803_REG_VCHG_PWR_MSB		0x4A
+#define SM5803_REG_VCHG_PWR_MSB 0x4A
 
-#define SM5803_REG_TINT_MEAS_MSB	0x4E
+#define SM5803_REG_TINT_MEAS_MSB 0x4E
 
 /* VSYS levels - The VSYS levels increment in  23.4mV steps. */
-#define SM5803_REG_VSYS_MEAS_MSB	0x4C
-#define SM5803_REG_VSYS_MEAS_LSB	0x4D
-#define SM5803_REG_VSYS_AVG_MEAS_MSB	0xCC
-#define SM5803_REG_VSYS_AVG_MEAS_LSB	0xCD
-#define SM5803_VSYS_MEAS_LSB		GENMASK(1, 0)
+#define SM5803_REG_VSYS_MEAS_MSB 0x4C
+#define SM5803_REG_VSYS_MEAS_LSB 0x4D
+#define SM5803_REG_VSYS_AVG_MEAS_MSB 0xCC
+#define SM5803_REG_VSYS_AVG_MEAS_LSB 0xCD
+#define SM5803_VSYS_MEAS_LSB GENMASK(1, 0)
 
 /* Charger registers (address 0x32) */
 
-#define SM5803_REG_CC_CONFIG1		0x01
-#define SM5803_CC_CONFIG1_SD_PWRUP	BIT(3)
+#define SM5803_REG_CC_CONFIG1 0x01
+#define SM5803_CC_CONFIG1_SD_PWRUP BIT(3)
 
-#define SM5803_REG_FLOW1		0x1C
-#define SM5803_FLOW1_MODE		GENMASK(1, 0)
-#define SM5803_FLOW1_DIRECTCHG_SRC_EN	BIT(2)
-#define SM5803_FLOW1_LINEAR_CHARGE_EN	BIT(3)
-#define SM5803_FLOW1_USB_SUSP		BIT(7)
+#define SM5803_REG_FLOW1 0x1C
+#define SM5803_FLOW1_MODE GENMASK(1, 0)
+#define SM5803_FLOW1_DIRECTCHG_SRC_EN BIT(2)
+#define SM5803_FLOW1_LINEAR_CHARGE_EN BIT(3)
+#define SM5803_FLOW1_USB_SUSP BIT(7)
 
 enum sm5803_charger_modes {
 	CHARGER_MODE_DISABLED,
@@ -228,157 +239,157 @@ enum sm5803_charger_modes {
 	CHARGER_MODE_SOURCE,
 };
 
-#define SM5803_REG_FLOW2		0x1D
-#define SM5803_FLOW2_AUTO_TRKL_EN	BIT(0)
-#define SM5803_FLOW2_AUTO_PRECHG_EN	BIT(1)
-#define SM5803_FLOW2_AUTO_FASTCHG_EN	BIT(2)
-#define SM5803_FLOW2_AUTO_ENABLED	GENMASK(2, 0)
-#define SM5803_FLOW2_FW_TRKL_CMD	BIT(3)
-#define SM5803_FLOW2_FW_PRECHG_CMD	BIT(4)
-#define SM5803_FLOW2_FW_FASTCHG_CMD	BIT(5)
-#define SM5803_FLOW2_HOST_MODE_EN	BIT(6)
-#define SM5803_FLOW2_AUTO_CHGEN_SET	BIT(7)
-
-#define SM5803_REG_FLOW3		0x1E
-#define SM5803_FLOW3_SWITCH_BCK_BST	BIT(0)
-#define SM5803_FLOW3_FW_SWITCH_RESUME	BIT(1)
-#define SM5803_FLOW3_FW_SWITCH_PAUSE	BIT(2)
-#define SM5803_FLOW3_SOFT_DISABLE_EN	BIT(3)
-
-#define SM5803_REG_SWITCHER_CONF	0x1F
-#define SM5803_SW_BCK_BST_CONF_AUTO	BIT(0)
-
-#define SM5803_REG_ANA_EN1		0x21
-#define SM5803_ANA_EN1_CLS_DISABLE	BIT(7)
+#define SM5803_REG_FLOW2 0x1D
+#define SM5803_FLOW2_AUTO_TRKL_EN BIT(0)
+#define SM5803_FLOW2_AUTO_PRECHG_EN BIT(1)
+#define SM5803_FLOW2_AUTO_FASTCHG_EN BIT(2)
+#define SM5803_FLOW2_AUTO_ENABLED GENMASK(2, 0)
+#define SM5803_FLOW2_FW_TRKL_CMD BIT(3)
+#define SM5803_FLOW2_FW_PRECHG_CMD BIT(4)
+#define SM5803_FLOW2_FW_FASTCHG_CMD BIT(5)
+#define SM5803_FLOW2_HOST_MODE_EN BIT(6)
+#define SM5803_FLOW2_AUTO_CHGEN_SET BIT(7)
+
+#define SM5803_REG_FLOW3 0x1E
+#define SM5803_FLOW3_SWITCH_BCK_BST BIT(0)
+#define SM5803_FLOW3_FW_SWITCH_RESUME BIT(1)
+#define SM5803_FLOW3_FW_SWITCH_PAUSE BIT(2)
+#define SM5803_FLOW3_SOFT_DISABLE_EN BIT(3)
+
+#define SM5803_REG_SWITCHER_CONF 0x1F
+#define SM5803_SW_BCK_BST_CONF_AUTO BIT(0)
+
+#define SM5803_REG_ANA_EN1 0x21
+#define SM5803_ANA_EN1_CLS_DISABLE BIT(7)
 
 /*
  * Input current limit is CHG_ILIM_RAW *100 mA
  */
-#define SM5803_REG_CHG_ILIM		0x24
-#define SM5803_CHG_ILIM_RAW		GENMASK(4, 0)
-#define SM5803_CURRENT_STEP		100
-#define SM5803_REG_TO_CURRENT(r)	((r) * SM5803_CURRENT_STEP)
-#define SM5803_CURRENT_TO_REG(c)	((c) / SM5803_CURRENT_STEP)
+#define SM5803_REG_CHG_ILIM 0x24
+#define SM5803_CHG_ILIM_RAW GENMASK(4, 0)
+#define SM5803_CURRENT_STEP 100
+#define SM5803_REG_TO_CURRENT(r) ((r)*SM5803_CURRENT_STEP)
+#define SM5803_CURRENT_TO_REG(c) ((c) / SM5803_CURRENT_STEP)
 
 /*
  * DPM Voltage loop regulation contains the 8 bits with MSB register
  * and the lower 3 bits with LSB register.
  * The regulation value is 2.72 V + DPM_VL_SET * 10mV
  */
-#define SM5803_REG_DPM_VL_SET_MSB		0x26
-#define SM5803_REG_DPM_VL_SET_LSB		0x27
+#define SM5803_REG_DPM_VL_SET_MSB 0x26
+#define SM5803_REG_DPM_VL_SET_LSB 0x27
 
 /*
  * Output voltage uses the same equation as Vsys
  * Lower saturation value is 3 V, upper 20.5 V
  */
-#define SM5803_REG_VPWR_MSB		0x30
-#define SM5803_REG_DISCH_CONF2		0x31
-#define SM5803_DISCH_CONF5_VPWR_LSB	GENMASK(2, 0)
+#define SM5803_REG_VPWR_MSB 0x30
+#define SM5803_REG_DISCH_CONF2 0x31
+#define SM5803_DISCH_CONF5_VPWR_LSB GENMASK(2, 0)
 
 /*
  * Output current limit is CLS_LIMIT * 50 mA and saturates to 3.2 A
  */
-#define SM5803_REG_DISCH_CONF5		0x34
-#define SM5803_DISCH_CONF5_CLS_LIMIT	GENMASK(6, 0)
-#define SM5803_CLS_CURRENT_STEP		50
+#define SM5803_REG_DISCH_CONF5 0x34
+#define SM5803_DISCH_CONF5_CLS_LIMIT GENMASK(6, 0)
+#define SM5803_CLS_CURRENT_STEP 50
 
-#define SM5803_REG_DISCH_CONF6		0x35
-#define SM5803_DISCH_CONF6_RAMPS_DIS	BIT(0)
-#define SM5803_DISCH_CONF6_SMOOTH_DIS	BIT(1)
+#define SM5803_REG_DISCH_CONF6 0x35
+#define SM5803_DISCH_CONF6_RAMPS_DIS BIT(0)
+#define SM5803_DISCH_CONF6_SMOOTH_DIS BIT(1)
 
 /*
  * Vsys is 11 bits, with the lower 3 bits in the LSB register.
  * The pre-regulation value is 2.72 V + Vsys_prereg * 10 mV
  * Lower saturation value is 3V, upper is 20V
  */
-#define SM5803_REG_VSYS_PREREG_MSB	0x36
-#define SM5803_REG_VSYS_PREREG_LSB	0x37
-#define SM5803_VOLTAGE_STEP		10
-#define SM5803_VOLTAGE_SHIFT		2720
-#define SM5803_REG_TO_VOLTAGE(r)	(SM5803_VOLTAGE_SHIFT + \
-					 (r) * SM5803_VOLTAGE_STEP)
-#define SM5803_VOLTAGE_TO_REG(v)	(((v) - SM5803_VOLTAGE_SHIFT) \
-					 / SM5803_VOLTAGE_STEP)
+#define SM5803_REG_VSYS_PREREG_MSB 0x36
+#define SM5803_REG_VSYS_PREREG_LSB 0x37
+#define SM5803_VOLTAGE_STEP 10
+#define SM5803_VOLTAGE_SHIFT 2720
+#define SM5803_REG_TO_VOLTAGE(r) \
+	(SM5803_VOLTAGE_SHIFT + (r)*SM5803_VOLTAGE_STEP)
+#define SM5803_VOLTAGE_TO_REG(v) \
+	(((v)-SM5803_VOLTAGE_SHIFT) / SM5803_VOLTAGE_STEP)
 
 /*
  * Precharge Termination threshold.
  */
-#define SM5803_REG_PRE_FAST_CONF_REG1	0x39
-#define SM5803_VBAT_PRE_TERM_MIN_DV	23
+#define SM5803_REG_PRE_FAST_CONF_REG1 0x39
+#define SM5803_VBAT_PRE_TERM_MIN_DV 23
 /* 3.8V+ gets rounded to 4V */
-#define SM5803_VBAT_PRE_TERM_MAX_DV	38
-#define SM5803_VBAT_PRE_TERM		GENMASK(7, 4)
-#define SM5803_VBAT_PRE_TERM_SHIFT	4
+#define SM5803_VBAT_PRE_TERM_MAX_DV 38
+#define SM5803_VBAT_PRE_TERM GENMASK(7, 4)
+#define SM5803_VBAT_PRE_TERM_SHIFT 4
 
 /*
  * Vbat for fast charge uses the same equation as Vsys
  * Lower saturation value is 3V, upper is dependent on number of cells
  */
-#define SM5803_REG_VBAT_FAST_MSB	0x3A
-#define SM5803_REG_VBAT_FAST_LSB	0x3B
+#define SM5803_REG_VBAT_FAST_MSB 0x3A
+#define SM5803_REG_VBAT_FAST_LSB 0x3B
 
 /*
  * Fast charge current limit is ICHG_FAST * 100 mA
  * Value read back may be adjusted if tempearture limits are exceeded
  */
-#define SM5803_REG_FAST_CONF4		0x3C
-#define SM5803_CONF4_ICHG_FAST		GENMASK(5, 0)
+#define SM5803_REG_FAST_CONF4 0x3C
+#define SM5803_CONF4_ICHG_FAST GENMASK(5, 0)
 
 /* Fast charge Termination */
-#define SM5803_REG_FAST_CONF5		0x3D
-#define SM5803_CONF5_IBAT_EOC_TH	GENMASK(3, 0)
+#define SM5803_REG_FAST_CONF5 0x3D
+#define SM5803_CONF5_IBAT_EOC_TH GENMASK(3, 0)
 
 /* IR drop compensation */
-#define SM5803_REG_IR_COMP1		0x3F
-#define SM5803_IR_COMP_RES_SET_MSB	GENMASK(7, 6)
+#define SM5803_REG_IR_COMP1 0x3F
+#define SM5803_IR_COMP_RES_SET_MSB GENMASK(7, 6)
 #define SM5803_IR_COMP_RES_SET_MSB_SHIFT 6
-#define SM5803_IR_COMP_EN		BIT(5)
+#define SM5803_IR_COMP_EN BIT(5)
 
 /* LSB is in 1.67mOhm steps. */
-#define SM5803_REG_IR_COMP2		0x40
+#define SM5803_REG_IR_COMP2 0x40
 
 /* Precharge current limit is also intervals of 100 mA */
-#define SM5803_REG_PRECHG		0x41
-#define SM5803_PRECHG_ICHG_PRE_SET	GENMASK(5, 0)
-
-#define SM5803_REG_LOG1			0x42
-#define SM5803_BATFET_ON		BIT(2)
-
-#define SM5803_REG_LOG2			0x43
-#define SM5803_ISOLOOP_ON		BIT(1)
-
-#define SM5803_REG_STATUS_CHG_REG	0x48
-#define SM5803_STATUS_CHG_BATT_REMOVAL	BIT(0)
-#define SM5803_STATUS_CHG_CHG_REMOVAL	BIT(1)
-#define SM5803_STATUS_CHG_BATTEMP_NOK	BIT(2)
-#define SM5803_STATUS_CHG_CHGWDG_EXP	BIT(3)
-#define SM5803_STATUS_CHG_VBUS_OC	BIT(4)
-#define SM5803_STATUS_CHG_OV_VBAT	BIT(5)
-#define SM5803_STATUS_CHG_TIMEOUT	BIT(6)
-#define SM5803_STATUS_CHG_OV_ITEMP	BIT(7)
-
-#define SM5803_REG_STATUS_DISCHG	0x49
-#define SM5803_STATUS_DISCHG_BATT_REM	BIT(0)
-#define SM5803_STATUS_DISCHG_UV_VBAT	BIT(1)
-#define SM5803_STATUS_DISCHG_VBUS_OC	BIT(2)
-#define SM5803_STATUS_DISCHG_VBUS_PWR	GENMASK(4, 3)
-#define SM5803_STATUS_DISCHG_ISO_CURR	BIT(5)
-#define SM5803_STATUS_DISCHG_VBUS_SHORT	BIT(6)
-#define SM5803_STATUS_DISCHG_OV_ITEMP	BIT(7)
-
-#define SM5803_REG_CHG_MON_REG		0x5C
-#define SM5803_DPM_LOOP_EN		BIT(0)
-
-#define SM5803_REG_PHOT1		0x72
-#define SM5803_PHOT1_IBAT_PHOT_COMP_EN	BIT(0)
-#define SM5803_PHOT1_IBUS_PHOT_COMP_EN	BIT(1)
-#define SM5803_PHOT1_VSYS_MON_EN	BIT(2)
-#define SM5803_PHOT1_VBUS_MON_EN	BIT(3)
-#define SM5803_PHOT1_COMPARATOR_EN	GENMASK(3, 0)
-#define SM5803_PHOT1_DURATION		GENMASK(6, 4)
-#define SM5803_PHOT1_DURATION_SHIFT	4
-#define SM5803_PHOT1_IRQ_MODE		BIT(7)
+#define SM5803_REG_PRECHG 0x41
+#define SM5803_PRECHG_ICHG_PRE_SET GENMASK(5, 0)
+
+#define SM5803_REG_LOG1 0x42
+#define SM5803_BATFET_ON BIT(2)
+
+#define SM5803_REG_LOG2 0x43
+#define SM5803_ISOLOOP_ON BIT(1)
+
+#define SM5803_REG_STATUS_CHG_REG 0x48
+#define SM5803_STATUS_CHG_BATT_REMOVAL BIT(0)
+#define SM5803_STATUS_CHG_CHG_REMOVAL BIT(1)
+#define SM5803_STATUS_CHG_BATTEMP_NOK BIT(2)
+#define SM5803_STATUS_CHG_CHGWDG_EXP BIT(3)
+#define SM5803_STATUS_CHG_VBUS_OC BIT(4)
+#define SM5803_STATUS_CHG_OV_VBAT BIT(5)
+#define SM5803_STATUS_CHG_TIMEOUT BIT(6)
+#define SM5803_STATUS_CHG_OV_ITEMP BIT(7)
+
+#define SM5803_REG_STATUS_DISCHG 0x49
+#define SM5803_STATUS_DISCHG_BATT_REM BIT(0)
+#define SM5803_STATUS_DISCHG_UV_VBAT BIT(1)
+#define SM5803_STATUS_DISCHG_VBUS_OC BIT(2)
+#define SM5803_STATUS_DISCHG_VBUS_PWR GENMASK(4, 3)
+#define SM5803_STATUS_DISCHG_ISO_CURR BIT(5)
+#define SM5803_STATUS_DISCHG_VBUS_SHORT BIT(6)
+#define SM5803_STATUS_DISCHG_OV_ITEMP BIT(7)
+
+#define SM5803_REG_CHG_MON_REG 0x5C
+#define SM5803_DPM_LOOP_EN BIT(0)
+
+#define SM5803_REG_PHOT1 0x72
+#define SM5803_PHOT1_IBAT_PHOT_COMP_EN BIT(0)
+#define SM5803_PHOT1_IBUS_PHOT_COMP_EN BIT(1)
+#define SM5803_PHOT1_VSYS_MON_EN BIT(2)
+#define SM5803_PHOT1_VBUS_MON_EN BIT(3)
+#define SM5803_PHOT1_COMPARATOR_EN GENMASK(3, 0)
+#define SM5803_PHOT1_DURATION GENMASK(6, 4)
+#define SM5803_PHOT1_DURATION_SHIFT 4
+#define SM5803_PHOT1_IRQ_MODE BIT(7)
 
 #define CHARGER_NAME "sm5803"
 
@@ -420,6 +431,21 @@ void sm5803_interrupt(int chgnum);
  */
 enum ec_error_list sm5803_is_acok(int chgnum, bool *acok);
 
+/**
+ * Test whether the current voltage on VBUS corresponds to the given range.
+ *
+ * Users should prefer this function to manually evaluating the result of
+ * charger_get_vbus_voltage because that function may behave incorrectly when
+ * the charger is in low power mode. This function will return correct results
+ * regardless of the charger state.
+ *
+ * @param chgnum charger index to test
+ * @param level VBUS range
+ * @return true if the current VBUS voltage is in the given range, false if it
+ *         is not or if there is a problem communicating with the charger.
+ */
+bool sm5803_check_vbus_level(int chgnum, enum vbus_level level);
+
 /* Expose low power mode functions */
 void sm5803_disable_low_power_mode(int chgnum);
 void sm5803_enable_low_power_mode(int chgnum);
diff --git a/driver/charger/sy21612.c b/driver/charger/sy21612.c
index 7bc6caa4ea..bded1474b6 100644
--- a/driver/charger/sy21612.c
+++ b/driver/charger/sy21612.c
@@ -1,11 +1,10 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * SILERGY SY21612 buck-boost converter driver.
  */
 
-
 #include "console.h"
 #include "hooks.h"
 #include "i2c.h"
@@ -15,8 +14,8 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CHARGER, outstr)
-#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
 
 static int sy21612_clear_set_reg(int reg, int clear, int set)
 {
@@ -31,8 +30,7 @@ static int sy21612_clear_set_reg(int reg, int clear, int set)
 	val |= set;
 
 	if (val != old_val || clear || set)
-		rv = i2c_write8(I2C_PORT_SY21612, SY21612_ADDR_FLAGS,
-				reg, val);
+		rv = i2c_write8(I2C_PORT_SY21612, SY21612_ADDR_FLAGS, reg, val);
 
 	return rv;
 }
@@ -44,64 +42,62 @@ static int sy21612_read(int reg, int *val)
 
 int sy21612_enable_regulator(int enable)
 {
-	return enable ?
-		sy21612_clear_set_reg(SY21612_CTRL1, 0, SY21612_CTRL1_REG_EN) :
-		sy21612_clear_set_reg(SY21612_CTRL1, SY21612_CTRL1_REG_EN, 0);
+	return enable ? sy21612_clear_set_reg(SY21612_CTRL1, 0,
+					      SY21612_CTRL1_REG_EN) :
+			sy21612_clear_set_reg(SY21612_CTRL1,
+					      SY21612_CTRL1_REG_EN, 0);
 }
 
 int sy21612_enable_adc(int enable)
 {
-	return enable ?
-		sy21612_clear_set_reg(SY21612_CTRL1, 0, SY21612_CTRL1_ADC_EN) :
-		sy21612_clear_set_reg(SY21612_CTRL1, SY21612_CTRL1_ADC_EN, 0);
+	return enable ? sy21612_clear_set_reg(SY21612_CTRL1, 0,
+					      SY21612_CTRL1_ADC_EN) :
+			sy21612_clear_set_reg(SY21612_CTRL1,
+					      SY21612_CTRL1_ADC_EN, 0);
 }
 
 int sy21612_set_adc_mode(int auto_mode)
 {
 	return auto_mode ?
-		sy21612_clear_set_reg(SY21612_CTRL1,
-				      0, SY21612_CTRL1_ADC_AUTO_MODE) :
-		sy21612_clear_set_reg(SY21612_CTRL1,
-				      SY21612_CTRL1_ADC_AUTO_MODE, 0);
+		       sy21612_clear_set_reg(SY21612_CTRL1, 0,
+					     SY21612_CTRL1_ADC_AUTO_MODE) :
+		       sy21612_clear_set_reg(SY21612_CTRL1,
+					     SY21612_CTRL1_ADC_AUTO_MODE, 0);
 }
 
 int sy21612_set_vbus_discharge(int auto_discharge)
 {
 	return auto_discharge ?
-		sy21612_clear_set_reg(SY21612_CTRL1,
-				      SY21612_CTRL1_VBUS_NDISCHG, 0) :
-		sy21612_clear_set_reg(SY21612_CTRL1,
-				      0, SY21612_CTRL1_VBUS_NDISCHG);
+		       sy21612_clear_set_reg(SY21612_CTRL1,
+					     SY21612_CTRL1_VBUS_NDISCHG, 0) :
+		       sy21612_clear_set_reg(SY21612_CTRL1, 0,
+					     SY21612_CTRL1_VBUS_NDISCHG);
 }
 
 int sy21612_set_switching_freq(enum sy21612_switching_freq freq)
 {
-	return sy21612_clear_set_reg(SY21612_CTRL2,
-				     SY21612_CTRL2_FREQ_MASK,
+	return sy21612_clear_set_reg(SY21612_CTRL2, SY21612_CTRL2_FREQ_MASK,
 				     freq << SY21612_CTRL2_FREQ_SHIFT);
 }
 
 int sy21612_set_vbus_volt(enum sy21612_vbus_volt volt)
 {
-	return sy21612_clear_set_reg(SY21612_CTRL2,
-				     SY21612_CTRL2_VBUS_MASK,
+	return sy21612_clear_set_reg(SY21612_CTRL2, SY21612_CTRL2_VBUS_MASK,
 				     volt << SY21612_CTRL2_VBUS_SHIFT);
 }
 
 int sy21612_set_vbus_adj(enum sy21612_vbus_adj adj)
 {
-	return sy21612_clear_set_reg(SY21612_CTRL2,
-				     SY21612_CTRL2_VBUS_ADJ_MASK,
+	return sy21612_clear_set_reg(SY21612_CTRL2, SY21612_CTRL2_VBUS_ADJ_MASK,
 				     adj << SY21612_CTRL2_VBUS_ADJ_SHIFT);
 }
 
 int sy21612_set_sink_mode(int sink_mode)
 {
-	return sink_mode ?
-		sy21612_clear_set_reg(SY21612_PROT2,
-				      0, SY21612_PROT2_SINK_MODE) :
-		sy21612_clear_set_reg(SY21612_PROT2,
-				      SY21612_PROT2_SINK_MODE, 0);
+	return sink_mode ? sy21612_clear_set_reg(SY21612_PROT2, 0,
+						 SY21612_PROT2_SINK_MODE) :
+			   sy21612_clear_set_reg(SY21612_PROT2,
+						 SY21612_PROT2_SINK_MODE, 0);
 }
 
 int sy21612_is_power_good(void)
@@ -188,7 +184,7 @@ void sy21612_task(void *u)
 #endif
 
 #ifdef CONFIG_CMD_CHARGER
-static int command_sy21612(int argc, char **argv)
+static int command_sy21612(int argc, const char **argv)
 {
 	int i, val, rv;
 
@@ -199,7 +195,7 @@ static int command_sy21612(int argc, char **argv)
 		if (rv)
 			ccprintf(" x (%d)\n", rv);
 		else
-			ccprintf("%02x - %pb\n", val, BINARY_VALUE(val, 8));
+			ccprintf("%02x\n", val);
 	}
 
 	ccprintf("vbat voltage: %d mV\n", sy21612_get_vbat_voltage());
@@ -208,6 +204,5 @@ static int command_sy21612(int argc, char **argv)
 
 	return 0;
 }
-DECLARE_CONSOLE_COMMAND(sy21612, command_sy21612,
-			NULL, NULL);
+DECLARE_CONSOLE_COMMAND(sy21612, command_sy21612, NULL, NULL);
 #endif
diff --git a/driver/charger/sy21612.h b/driver/charger/sy21612.h
index befb8e6a35..bc6d45797b 100644
--- a/driver/charger/sy21612.h
+++ b/driver/charger/sy21612.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,7 +11,7 @@
 #include "gpio.h"
 
 #ifndef SY21612_ADDR_FLAGS
-#define SY21612_ADDR_FLAGS		0x71
+#define SY21612_ADDR_FLAGS 0x71
 #endif
 
 enum sy21612_switching_freq {
@@ -40,94 +40,94 @@ enum sy21612_vbus_adj {
 	SY21612_VBUS_5,
 };
 
-#define SY21612_CTRL1        0x00
-#define SY21612_CTRL1_REG_EN         BIT(7)
-#define SY21612_CTRL1_LOW_BAT_MASK   (7 << 4)
-#define SY21612_CTRL1_LOW_BAT_10_2V  (0 << 4)
-#define SY21612_CTRL1_LOW_BAT_10_7V  BIT(4)
-#define SY21612_CTRL1_LOW_BAT_11_2V  (2 << 4)
-#define SY21612_CTRL1_LOW_BAT_11_7V  (3 << 4)
-#define SY21612_CTRL1_LOW_BAT_22_0V  (4 << 4)
-#define SY21612_CTRL1_LOW_BAT_22_5V  (5 << 4)
-#define SY21612_CTRL1_LOW_BAT_23_0V  (6 << 4)
-#define SY21612_CTRL1_LOW_BAT_23_5V  (7 << 4)
-#define SY21612_CTRL1_ADC_EN         BIT(3)
-#define SY21612_CTRL1_ADC_AUTO_MODE  BIT(2)
-#define SY21612_CTRL1_VBUS_NDISCHG   BIT(1)
-
-#define SY21612_CTRL2        0x01
-#define SY21612_CTRL2_FREQ_MASK      (3 << 6)
-#define SY21612_CTRL2_FREQ_SHIFT     6
-#define SY21612_CTRL2_FREQ_250K      (0 << 6)
-#define SY21612_CTRL2_FREQ_500K      BIT(6)
-#define SY21612_CTRL2_FREQ_750K      (2 << 6)
-#define SY21612_CTRL2_FREQ_1M        (3 << 6)
-#define SY21612_CTRL2_VBUS_MASK      (7 << 3)
-#define SY21612_CTRL2_VBUS_SHIFT     3
-#define SY21612_CTRL2_VBUS_5V        (2 << 3)
-#define SY21612_CTRL2_VBUS_7V        (3 << 3)
-#define SY21612_CTRL2_VBUS_9V        (4 << 3)
-#define SY21612_CTRL2_VBUS_12V       (5 << 3)
-#define SY21612_CTRL2_VBUS_15V       (6 << 3)
-#define SY21612_CTRL2_VBUS_20V       (7 << 3)
-#define SY21612_CTRL2_VBUS_ADJ_MASK  7
+#define SY21612_CTRL1 0x00
+#define SY21612_CTRL1_REG_EN BIT(7)
+#define SY21612_CTRL1_LOW_BAT_MASK (7 << 4)
+#define SY21612_CTRL1_LOW_BAT_10_2V (0 << 4)
+#define SY21612_CTRL1_LOW_BAT_10_7V BIT(4)
+#define SY21612_CTRL1_LOW_BAT_11_2V (2 << 4)
+#define SY21612_CTRL1_LOW_BAT_11_7V (3 << 4)
+#define SY21612_CTRL1_LOW_BAT_22_0V (4 << 4)
+#define SY21612_CTRL1_LOW_BAT_22_5V (5 << 4)
+#define SY21612_CTRL1_LOW_BAT_23_0V (6 << 4)
+#define SY21612_CTRL1_LOW_BAT_23_5V (7 << 4)
+#define SY21612_CTRL1_ADC_EN BIT(3)
+#define SY21612_CTRL1_ADC_AUTO_MODE BIT(2)
+#define SY21612_CTRL1_VBUS_NDISCHG BIT(1)
+
+#define SY21612_CTRL2 0x01
+#define SY21612_CTRL2_FREQ_MASK (3 << 6)
+#define SY21612_CTRL2_FREQ_SHIFT 6
+#define SY21612_CTRL2_FREQ_250K (0 << 6)
+#define SY21612_CTRL2_FREQ_500K BIT(6)
+#define SY21612_CTRL2_FREQ_750K (2 << 6)
+#define SY21612_CTRL2_FREQ_1M (3 << 6)
+#define SY21612_CTRL2_VBUS_MASK (7 << 3)
+#define SY21612_CTRL2_VBUS_SHIFT 3
+#define SY21612_CTRL2_VBUS_5V (2 << 3)
+#define SY21612_CTRL2_VBUS_7V (3 << 3)
+#define SY21612_CTRL2_VBUS_9V (4 << 3)
+#define SY21612_CTRL2_VBUS_12V (5 << 3)
+#define SY21612_CTRL2_VBUS_15V (6 << 3)
+#define SY21612_CTRL2_VBUS_20V (7 << 3)
+#define SY21612_CTRL2_VBUS_ADJ_MASK 7
 #define SY21612_CTRL2_VBUS_ADJ_SHIFT 0
-#define SY21612_CTRL2_VBUS_ADJ_M2_5  0
+#define SY21612_CTRL2_VBUS_ADJ_M2_5 0
 #define SY21612_CTRL2_VBUS_ADJ_M1_25 1
-#define SY21612_CTRL2_VBUS_ADJ_0     2
-#define SY21612_CTRL2_VBUS_ADJ_1_25  3
-#define SY21612_CTRL2_VBUS_ADJ_2_5   4
-#define SY21612_CTRL2_VBUS_ADJ_3_75  5
-#define SY21612_CTRL2_VBUS_ADJ_5     6
-
-#define SY21612_PROT1        0x02
-#define SY21612_PROT1_I_THRESH_MASK   (7 << 5)
-#define SY21612_PROT1_I_THRESH_18MV   (0 << 5)
-#define SY21612_PROT1_I_THRESH_22MV   BIT(5)
-#define SY21612_PROT1_I_THRESH_27MV   (2 << 5)
-#define SY21612_PROT1_I_THRESH_31MV   (3 << 5)
-#define SY21612_PROT1_I_THRESH_36MV   (4 << 5)
-#define SY21612_PROT1_I_THRESH_45MV   (5 << 5)
-#define SY21612_PROT1_I_THRESH_54MV   (6 << 5)
-#define SY21612_PROT1_I_THRESH_64MV   (7 << 5)
+#define SY21612_CTRL2_VBUS_ADJ_0 2
+#define SY21612_CTRL2_VBUS_ADJ_1_25 3
+#define SY21612_CTRL2_VBUS_ADJ_2_5 4
+#define SY21612_CTRL2_VBUS_ADJ_3_75 5
+#define SY21612_CTRL2_VBUS_ADJ_5 6
+
+#define SY21612_PROT1 0x02
+#define SY21612_PROT1_I_THRESH_MASK (7 << 5)
+#define SY21612_PROT1_I_THRESH_18MV (0 << 5)
+#define SY21612_PROT1_I_THRESH_22MV BIT(5)
+#define SY21612_PROT1_I_THRESH_27MV (2 << 5)
+#define SY21612_PROT1_I_THRESH_31MV (3 << 5)
+#define SY21612_PROT1_I_THRESH_36MV (4 << 5)
+#define SY21612_PROT1_I_THRESH_45MV (5 << 5)
+#define SY21612_PROT1_I_THRESH_54MV (6 << 5)
+#define SY21612_PROT1_I_THRESH_64MV (7 << 5)
 #define SY21612_PROT1_OVP_THRESH_MASK (3 << 3)
-#define SY21612_PROT1_OVP_THRESH_110  (0 << 3)
-#define SY21612_PROT1_OVP_THRESH_115  BIT(3)
-#define SY21612_PROT1_OVP_THRESH_120  (2 << 3)
-#define SY21612_PROT1_OVP_THRESH_125  (3 << 3)
+#define SY21612_PROT1_OVP_THRESH_110 (0 << 3)
+#define SY21612_PROT1_OVP_THRESH_115 BIT(3)
+#define SY21612_PROT1_OVP_THRESH_120 (2 << 3)
+#define SY21612_PROT1_OVP_THRESH_125 (3 << 3)
 #define SY21612_PROT1_UVP_THRESH_MASK (3 << 1)
-#define SY21612_PROT1_UVP_THRESH_50   (0 << 1)
-#define SY21612_PROT1_UVP_THRESH_60   BIT(1)
-#define SY21612_PROT1_UVP_THRESH_70   (2 << 1)
-#define SY21612_PROT1_UVP_THRESH_80   (3 << 1)
-
-#define SY21612_PROT2        0x03
-#define SY21612_PROT2_I_LIMIT_MASK    (3 << 6)
-#define SY21612_PROT2_I_LIMIT_6A      (0 << 6)
-#define SY21612_PROT2_I_LIMIT_8A      (2 << 6)
-#define SY21612_PROT2_I_LIMIT_10A     (3 << 6)
+#define SY21612_PROT1_UVP_THRESH_50 (0 << 1)
+#define SY21612_PROT1_UVP_THRESH_60 BIT(1)
+#define SY21612_PROT1_UVP_THRESH_70 (2 << 1)
+#define SY21612_PROT1_UVP_THRESH_80 (3 << 1)
+
+#define SY21612_PROT2 0x03
+#define SY21612_PROT2_I_LIMIT_MASK (3 << 6)
+#define SY21612_PROT2_I_LIMIT_6A (0 << 6)
+#define SY21612_PROT2_I_LIMIT_8A (2 << 6)
+#define SY21612_PROT2_I_LIMIT_10A (3 << 6)
 #define SY21612_PROT2_OCP_AUTORECOVER BIT(5)
 #define SY21612_PROT2_UVP_AUTORECOVER BIT(4)
 #define SY21612_PROT2_OTP_AUTORECOVER BIT(3)
-#define SY21612_PROT2_SINK_MODE       BIT(2)
+#define SY21612_PROT2_SINK_MODE BIT(2)
 
-#define SY21612_STATE        0x04
-#define SY21612_STATE_POWER_GOOD      BIT(7)
-#define SY21612_STATE_VBAT_LT_VBUS    BIT(6)
-#define SY21612_STATE_VBAT_LOW        BIT(5)
+#define SY21612_STATE 0x04
+#define SY21612_STATE_POWER_GOOD BIT(7)
+#define SY21612_STATE_VBAT_LT_VBUS BIT(6)
+#define SY21612_STATE_VBAT_LOW BIT(5)
 
-#define SY21612_INT          0x05
-#define SY21612_INT_ADC_READY         BIT(7)
-#define SY21612_INT_VBUS_OCP          BIT(6)
-#define SY21612_INT_INDUCTOR_OCP      BIT(5)
-#define SY21612_INT_UVP               BIT(4)
-#define SY21612_INT_OTP               BIT(3)
+#define SY21612_INT 0x05
+#define SY21612_INT_ADC_READY BIT(7)
+#define SY21612_INT_VBUS_OCP BIT(6)
+#define SY21612_INT_INDUCTOR_OCP BIT(5)
+#define SY21612_INT_UVP BIT(4)
+#define SY21612_INT_OTP BIT(3)
 
 /* Battery voltage range: 0 ~ 25V */
-#define SY21612_VBAT_VOLT    0x06
+#define SY21612_VBAT_VOLT 0x06
 
 /* VBUS voltage range: 0 ~ 25V */
-#define SY21612_VBUS_VOLT    0x07
+#define SY21612_VBUS_VOLT 0x07
 
 /* Output current sense voltage range 0 ~ 67mV */
 #define SY21612_VBUS_CURRENT 0x08
diff --git a/driver/fingerprint/build.mk b/driver/fingerprint/build.mk
index 6cb9dc7adb..d0d92cb011 100644
--- a/driver/fingerprint/build.mk
+++ b/driver/fingerprint/build.mk
@@ -1,4 +1,4 @@
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/driver/fingerprint/elan/build.mk b/driver/fingerprint/elan/build.mk
index 2e4ad2d46f..791cce9e73 100644
--- a/driver/fingerprint/elan/build.mk
+++ b/driver/fingerprint/elan/build.mk
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/driver/fingerprint/elan/elan_private.c b/driver/fingerprint/elan/elan_private.c
index 555ad14ba0..fc95ceb685 100644
--- a/driver/fingerprint/elan/elan_private.c
+++ b/driver/fingerprint/elan/elan_private.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/driver/fingerprint/elan/elan_sensor.h b/driver/fingerprint/elan/elan_sensor.h
index 490b1acf16..f294a00f4b 100644
--- a/driver/fingerprint/elan/elan_sensor.h
+++ b/driver/fingerprint/elan/elan_sensor.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/driver/fingerprint/elan/elan_sensor_pal.c b/driver/fingerprint/elan/elan_sensor_pal.c
index b59368b835..4056c52f38 100644
--- a/driver/fingerprint/elan/elan_sensor_pal.c
+++ b/driver/fingerprint/elan/elan_sensor_pal.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/driver/fingerprint/elan/elan_sensor_pal.h b/driver/fingerprint/elan/elan_sensor_pal.h
index 067b693245..235dcd5fa8 100644
--- a/driver/fingerprint/elan/elan_sensor_pal.h
+++ b/driver/fingerprint/elan/elan_sensor_pal.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/driver/fingerprint/elan/elan_setting.h b/driver/fingerprint/elan/elan_setting.h
index feaf5e1550..7e62653b8f 100644
--- a/driver/fingerprint/elan/elan_setting.h
+++ b/driver/fingerprint/elan/elan_setting.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/driver/fingerprint/fpc/bep/build.mk b/driver/fingerprint/fpc/bep/build.mk
index ac7f05fb60..ac5879a913 100644
--- a/driver/fingerprint/fpc/bep/build.mk
+++ b/driver/fingerprint/fpc/bep/build.mk
@@ -1,4 +1,4 @@
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/driver/fingerprint/fpc/bep/fpc1025_private.h b/driver/fingerprint/fpc/bep/fpc1025_private.h
index 2da127741f..35745c3119 100644
--- a/driver/fingerprint/fpc/bep/fpc1025_private.h
+++ b/driver/fingerprint/fpc/bep/fpc1025_private.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,19 +13,19 @@
 #define FP_SENSOR_NAME "FPC1025"
 
 /* Sensor pixel resolution */
-#define FP_SENSOR_RES_X     (160) /**< Sensor width                          */
-#define FP_SENSOR_RES_Y     (160) /**< Sensor height                         */
-#define FP_SENSOR_RES_BPP   (8)   /**< Resolution bits per pixel             */
+#define FP_SENSOR_RES_X (160) /**< Sensor width                          */
+#define FP_SENSOR_RES_Y (160) /**< Sensor height                         */
+#define FP_SENSOR_RES_BPP (8) /**< Resolution bits per pixel             */
 
 /*
  * Sensor image size
  *
  * Value from fpc_bep_image_get_buffer_size(): (160*160)+660
  */
-#define FP_SENSOR_IMAGE_SIZE        (26260)
-#define FP_SENSOR_REAL_IMAGE_SIZE   (FP_SENSOR_RES_X * FP_SENSOR_RES_Y)
+#define FP_SENSOR_IMAGE_SIZE (26260)
+#define FP_SENSOR_REAL_IMAGE_SIZE (FP_SENSOR_RES_X * FP_SENSOR_RES_Y)
 /* Offset of image data in fp_buffer */
-#define FP_SENSOR_IMAGE_OFFSET      (400)
+#define FP_SENSOR_IMAGE_OFFSET (400)
 
 /*
  * Constant value for the enrollment data size
@@ -41,9 +41,9 @@
  *
  * Template size + alignment padding + size of template size variable
  */
-#define FP_ALGORITHM_TEMPLATE_SIZE      (5088 + 0 + 4)
+#define FP_ALGORITHM_TEMPLATE_SIZE (5088 + 0 + 4)
 
 /* Max number of templates stored / matched against */
-#define FP_MAX_FINGER_COUNT     (5)
+#define FP_MAX_FINGER_COUNT (5)
 
 #endif /* __CROS_EC_FPC1025_PRIVATE_H */
diff --git a/driver/fingerprint/fpc/bep/fpc1035_private.h b/driver/fingerprint/fpc/bep/fpc1035_private.h
index 695228898b..41112b96c2 100644
--- a/driver/fingerprint/fpc/bep/fpc1035_private.h
+++ b/driver/fingerprint/fpc/bep/fpc1035_private.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,19 +13,19 @@
 #define FP_SENSOR_NAME "FPC1035"
 
 /* Sensor pixel resolution */
-#define FP_SENSOR_RES_X     (112) /**< Sensor width                          */
-#define FP_SENSOR_RES_Y     (88)  /**< Sensor height                         */
-#define FP_SENSOR_RES_BPP   (8)   /**< Resolution bits per pixel             */
+#define FP_SENSOR_RES_X (112) /**< Sensor width                          */
+#define FP_SENSOR_RES_Y (88) /**< Sensor height                         */
+#define FP_SENSOR_RES_BPP (8) /**< Resolution bits per pixel             */
 
 /*
  * Sensor image size
  *
  * Value from fpc_bep_image_get_buffer_size(): (112*88)+660
  */
-#define FP_SENSOR_IMAGE_SIZE        (10516)
-#define FP_SENSOR_REAL_IMAGE_SIZE   (FP_SENSOR_RES_X * FP_SENSOR_RES_Y)
+#define FP_SENSOR_IMAGE_SIZE (10516)
+#define FP_SENSOR_REAL_IMAGE_SIZE (FP_SENSOR_RES_X * FP_SENSOR_RES_Y)
 /* Offset of image data in fp_buffer */
-#define FP_SENSOR_IMAGE_OFFSET      (400)
+#define FP_SENSOR_IMAGE_OFFSET (400)
 
 /*
  * Constant value for the enrollment data size
@@ -41,9 +41,9 @@
  *
  * Template size + alignment padding + size of template size variable
  */
-#define FP_ALGORITHM_TEMPLATE_SIZE      (14373 + 3 + 4)
+#define FP_ALGORITHM_TEMPLATE_SIZE (14373 + 3 + 4)
 
 /* Max number of templates stored / matched against */
-#define FP_MAX_FINGER_COUNT     (5)
+#define FP_MAX_FINGER_COUNT (5)
 
 #endif /* __CROS_EC_FPC1035_PRIVATE_H */
diff --git a/driver/fingerprint/fpc/bep/fpc_bio_algorithm.h b/driver/fingerprint/fpc/bep/fpc_bio_algorithm.h
index 1bf598a3ee..1da01d0a08 100644
--- a/driver/fingerprint/fpc/bep/fpc_bio_algorithm.h
+++ b/driver/fingerprint/fpc/bep/fpc_bio_algorithm.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -66,12 +66,12 @@ int bio_algorithm_exit(void);
  * - BIO_TEMPLATE_LOW_COVERAGE when matching could not be performed due to
  *   finger covering too little area of the sensor
  */
-#define BIO_TEMPLATE_NO_MATCH            0
-#define BIO_TEMPLATE_MATCH               1
-#define BIO_TEMPLATE_MATCH_UPDATED       3
+#define BIO_TEMPLATE_NO_MATCH 0
+#define BIO_TEMPLATE_MATCH 1
+#define BIO_TEMPLATE_MATCH_UPDATED 3
 #define BIO_TEMPLATE_MATCH_UPDATE_FAILED 5
-#define BIO_TEMPLATE_LOW_QUALITY         2
-#define BIO_TEMPLATE_LOW_COVERAGE        4
+#define BIO_TEMPLATE_LOW_QUALITY 2
+#define BIO_TEMPLATE_LOW_COVERAGE 4
 
 int bio_template_image_match_list(bio_template_t templ, uint32_t num_templ,
 				  bio_image_t image, int32_t *match_index,
@@ -101,14 +101,14 @@ int bio_enrollment_begin(bio_enrollment_t *enrollment);
  *   finger covering too little area of the sensor
  * - BIO_ENROLLMENT_INTERNAL_ERROR when an internal error occurred
  */
-#define BIO_ENROLLMENT_OK               0
-#define BIO_ENROLLMENT_LOW_QUALITY      1
-#define BIO_ENROLLMENT_IMMOBILE         2
-#define BIO_ENROLLMENT_LOW_COVERAGE     3
-#define BIO_ENROLLMENT_INTERNAL_ERROR   5
+#define BIO_ENROLLMENT_OK 0
+#define BIO_ENROLLMENT_LOW_QUALITY 1
+#define BIO_ENROLLMENT_IMMOBILE 2
+#define BIO_ENROLLMENT_LOW_COVERAGE 3
+#define BIO_ENROLLMENT_INTERNAL_ERROR 5
 
 /* Can be used to detect if image was usable for enrollment or not. */
-#define BIO_ENROLLMENT_PROBLEM_MASK     1
+#define BIO_ENROLLMENT_PROBLEM_MASK 1
 int bio_enrollment_add_image(bio_enrollment_t enrollment, bio_image_t image);
 /*
  * Returns percent of coverage accumulated during enrollment process.
diff --git a/driver/fingerprint/fpc/bep/fpc_misc.c b/driver/fingerprint/fpc/bep/fpc_misc.c
index c4c779b702..4eed7c603b 100644
--- a/driver/fingerprint/fpc/bep/fpc_misc.c
+++ b/driver/fingerprint/fpc/bep/fpc_misc.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/driver/fingerprint/fpc/bep/fpc_private.c b/driver/fingerprint/fpc/bep/fpc_private.c
index 03ea84b899..ac20e10758 100644
--- a/driver/fingerprint/fpc/bep/fpc_private.c
+++ b/driver/fingerprint/fpc/bep/fpc_private.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,10 +16,10 @@
 #include "driver/fingerprint/fpc/fpc_sensor.h"
 
 /* Console output macros */
-#define CPRINTF(format, args...) cprintf(CC_FP, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_FP, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_FP, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_FP, format, ##args)
 
-static uint8_t enroll_ctx[FP_ALGORITHM_ENROLLMENT_SIZE] __aligned(4) = {0};
+static uint8_t enroll_ctx[FP_ALGORITHM_ENROLLMENT_SIZE] __aligned(4) = { 0 };
 
 /* Recorded error flags */
 static uint16_t errors;
@@ -91,8 +91,8 @@ const fpc_bio_info_t fpc_bio_info = {
 
 /* Sensor IC commands */
 enum fpc_cmd {
-	FPC_CMD_DEEPSLEEP         = 0x2C,
-	FPC_CMD_HW_ID             = 0xFC,
+	FPC_CMD_DEEPSLEEP = 0x2C,
+	FPC_CMD_HW_ID = 0xFC,
 };
 
 /* Maximum size of a sensor command SPI transfer */
diff --git a/driver/fingerprint/fpc/bep/fpc_private.h b/driver/fingerprint/fpc/bep/fpc_private.h
index 1c01d61207..ca5b98fa8e 100644
--- a/driver/fingerprint/fpc/bep/fpc_private.h
+++ b/driver/fingerprint/fpc/bep/fpc_private.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -46,4 +46,4 @@ int fp_sensor_maintenance(uint8_t *image_data,
  */
 int fpc_get_hwid(uint16_t *id);
 
-#endif  /* __CROS_EC_FPC_PRIVATE_H */
+#endif /* __CROS_EC_FPC_PRIVATE_H */
diff --git a/driver/fingerprint/fpc/bep/fpc_sensor_spi.c b/driver/fingerprint/fpc/bep/fpc_sensor_spi.c
index 225752bdb6..752b9909bc 100644
--- a/driver/fingerprint/fpc/bep/fpc_sensor_spi.c
+++ b/driver/fingerprint/fpc/bep/fpc_sensor_spi.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,10 +22,10 @@
 #define CPRINTF(format, args...) cprintf(CC_FP, format, ##args)
 #define CPRINTS(format, args...) cprints(CC_FP, format, ##args)
 
-#define SPI_BUF_SIZE              (1024)
+#define SPI_BUF_SIZE (1024)
 
-#define FPC_RESULT_OK                (0)
-#define FPC_RESULT_IO_ERROR         (-8)
+#define FPC_RESULT_OK (0)
+#define FPC_RESULT_IO_ERROR (-8)
 
 static uint8_t spi_buf[SPI_BUF_SIZE] FP_FRAME_SECTION __aligned(4);
 
diff --git a/driver/fingerprint/fpc/bep/fpc_sensor_spi.h b/driver/fingerprint/fpc/bep/fpc_sensor_spi.h
index 25d29d77a3..ad7e5411d8 100644
--- a/driver/fingerprint/fpc/bep/fpc_sensor_spi.h
+++ b/driver/fingerprint/fpc/bep/fpc_sensor_spi.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/driver/fingerprint/fpc/bep/fpc_timebase.c b/driver/fingerprint/fpc/bep/fpc_timebase.c
index 113e150ed9..a63a4c3d6d 100644
--- a/driver/fingerprint/fpc/bep/fpc_timebase.c
+++ b/driver/fingerprint/fpc/bep/fpc_timebase.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/driver/fingerprint/fpc/bep/fpc_timebase.h b/driver/fingerprint/fpc/bep/fpc_timebase.h
index 388d13293e..ce9018461b 100644
--- a/driver/fingerprint/fpc/bep/fpc_timebase.h
+++ b/driver/fingerprint/fpc/bep/fpc_timebase.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/driver/fingerprint/fpc/build.mk b/driver/fingerprint/fpc/build.mk
index 5c18a1f096..f17af5e496 100644
--- a/driver/fingerprint/fpc/build.mk
+++ b/driver/fingerprint/fpc/build.mk
@@ -1,4 +1,4 @@
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/driver/fingerprint/fpc/fpc_sensor.c b/driver/fingerprint/fpc/fpc_sensor.c
index a15502521f..bbab729b12 100644
--- a/driver/fingerprint/fpc/fpc_sensor.c
+++ b/driver/fingerprint/fpc/fpc_sensor.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/driver/fingerprint/fpc/fpc_sensor.h b/driver/fingerprint/fpc/fpc_sensor.h
index 2ab9248eeb..22e670afd0 100644
--- a/driver/fingerprint/fpc/fpc_sensor.h
+++ b/driver/fingerprint/fpc/fpc_sensor.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/driver/fingerprint/fpc/libfp/build.mk b/driver/fingerprint/fpc/libfp/build.mk
index 3fabab38e9..f22700f309 100644
--- a/driver/fingerprint/fpc/libfp/build.mk
+++ b/driver/fingerprint/fpc/libfp/build.mk
@@ -1,4 +1,4 @@
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/driver/fingerprint/fpc/libfp/fpc1145_private.h b/driver/fingerprint/fpc/libfp/fpc1145_private.h
index 399c75118b..993d1e1ea9 100644
--- a/driver/fingerprint/fpc/libfp/fpc1145_private.h
+++ b/driver/fingerprint/fpc/libfp/fpc1145_private.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,9 +21,9 @@
 #define FP_SENSOR_NAME "FPC1145"
 
 /* Sensor pixel resolution */
-#define FP_SENSOR_RES_Y        192
-#define FP_SENSOR_RES_X        56
-#define FP_SENSOR_RES_BPP      8
+#define FP_SENSOR_RES_Y 192
+#define FP_SENSOR_RES_X 56
+#define FP_SENSOR_RES_BPP 8
 
 /* Acquired finger frame definitions */
 #define FP_SENSOR_IMAGE_SIZE_MODE_VENDOR (35460)
@@ -33,17 +33,17 @@
  * corresponding value in the MQT tool fputils.py must be changed too.
  * See b/111443750 for context.
  */
-#define FP_SENSOR_IMAGE_SIZE_MODE_QUAL   (24408)
+#define FP_SENSOR_IMAGE_SIZE_MODE_QUAL (24408)
 
-#define FP_SENSOR_IMAGE_SIZE   FP_SENSOR_IMAGE_SIZE_MODE_VENDOR
+#define FP_SENSOR_IMAGE_SIZE FP_SENSOR_IMAGE_SIZE_MODE_VENDOR
 #define FP_SENSOR_IMAGE_OFFSET 2340
 
 /* Opaque FPC context */
 #define FP_SENSOR_CONTEXT_SIZE 4944
 
 /* Algorithm buffer sizes */
-#define FP_ALGORITHM_ENROLLMENT_SIZE    28
-#define FP_ALGORITHM_TEMPLATE_SIZE   47552
+#define FP_ALGORITHM_ENROLLMENT_SIZE 28
+#define FP_ALGORITHM_TEMPLATE_SIZE 47552
 
 /* Max number of templates stored / matched against */
 #define FP_MAX_FINGER_COUNT 5
diff --git a/driver/fingerprint/fpc/libfp/fpc_bio_algorithm.h b/driver/fingerprint/fpc/libfp/fpc_bio_algorithm.h
index 9c00b14640..7dda6d46de 100644
--- a/driver/fingerprint/fpc/libfp/fpc_bio_algorithm.h
+++ b/driver/fingerprint/fpc/libfp/fpc_bio_algorithm.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -196,12 +196,12 @@ int bio_enrollment_begin(bio_sensor_t sensor, bio_enrollment_t *enrollment);
  * - BIO_ENROLLMENT_LOW_COVERAGE when image could not be used  due to
  *   finger covering too little area of the sensor
  */
-#define BIO_ENROLLMENT_OK               0
-#define BIO_ENROLLMENT_IMMOBILE         2
-#define BIO_ENROLLMENT_LOW_QUALITY      1
-#define BIO_ENROLLMENT_LOW_COVERAGE     3
+#define BIO_ENROLLMENT_OK 0
+#define BIO_ENROLLMENT_IMMOBILE 2
+#define BIO_ENROLLMENT_LOW_QUALITY 1
+#define BIO_ENROLLMENT_LOW_COVERAGE 3
 /* Can be used to detect if image was usable for enrollment or not. */
-#define BIO_ENROLLMENT_PROBLEM_MASK     1
+#define BIO_ENROLLMENT_PROBLEM_MASK 1
 int bio_enrollment_add_image(bio_enrollment_t enrollment, bio_image_t image);
 /*
  * Indicates whether there is enough data in the enrollment for it to be
@@ -236,10 +236,10 @@ int bio_enrollment_get_percent_complete(bio_enrollment_t enrollment);
 int bio_enrollment_finish(bio_enrollment_t enrollment, bio_template_t *tmpl);
 
 typedef struct {
-	int32_t coverage;     /* Sensor coverage in range [0..100]        */
-	int32_t quality;      /* Image quality in range [0..100]          */
+	int32_t coverage; /* Sensor coverage in range [0..100]        */
+	int32_t quality; /* Image quality in range [0..100]          */
 	int32_t min_coverage; /* Minimum coverage accepted by enroll      */
-	int32_t min_quality;  /* Minimum image quality accepted by enroll */
+	int32_t min_quality; /* Minimum image quality accepted by enroll */
 } bio_image_status_t;
 
 /*
diff --git a/driver/fingerprint/fpc/libfp/fpc_private.c b/driver/fingerprint/fpc/libfp/fpc_private.c
index 7e7befcfdc..fcc0180784 100644
--- a/driver/fingerprint/fpc/libfp/fpc_private.c
+++ b/driver/fingerprint/fpc/libfp/fpc_private.c
@@ -1,12 +1,12 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include <stddef.h>
+#include <sys/types.h>
 #include "common.h"
 #include "console.h"
-#include "endian.h"
 #include "fpc_bio_algorithm.h"
 #include "fpc_private.h"
 #include "fpsensor.h"
@@ -19,8 +19,8 @@
 
 #include "driver/fingerprint/fpc/fpc_sensor.h"
 
-#define CPRINTF(format, args...) cprintf(CC_FP, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_FP, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_FP, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_FP, format, ##args)
 
 /* Minimum reset duration */
 #define FP_SENSOR_RESET_DURATION_US (10 * MSEC)
@@ -32,7 +32,7 @@
 #define FP_SENSOR_OPEN_DELAY_US (500 * MSEC)
 
 /* Decode internal error codes from FPC's sensor library */
-#define FPC_GET_INTERNAL_CODE(res) (((res) & 0x000fc000) >> 14)
+#define FPC_GET_INTERNAL_CODE(res) (((res)&0x000fc000) >> 14)
 /* There was a finger on the sensor when calibrating finger detect */
 #define FPC_INTERNAL_FINGER_DFD FPC_ERROR_INTERNAL_38
 
@@ -64,14 +64,14 @@ static struct ec_response_fp_info fpc1145_info = {
 
 /* Sensor IC commands */
 enum fpc_cmd {
-	FPC_CMD_STATUS            = 0x14,
-	FPC_CMD_INT_STS           = 0x18,
-	FPC_CMD_INT_CLR           = 0x1C,
-	FPC_CMD_FINGER_QUERY      = 0x20,
-	FPC_CMD_SLEEP             = 0x28,
-	FPC_CMD_DEEPSLEEP         = 0x2C,
-	FPC_CMD_SOFT_RESET        = 0xF8,
-	FPC_CMD_HW_ID             = 0xFC,
+	FPC_CMD_STATUS = 0x14,
+	FPC_CMD_INT_STS = 0x18,
+	FPC_CMD_INT_CLR = 0x1C,
+	FPC_CMD_FINGER_QUERY = 0x20,
+	FPC_CMD_SLEEP = 0x28,
+	FPC_CMD_DEEPSLEEP = 0x2C,
+	FPC_CMD_SOFT_RESET = 0xF8,
+	FPC_CMD_HW_ID = 0xFC,
 };
 
 /* Maximum size of a sensor command SPI transfer */
diff --git a/driver/fingerprint/fpc/libfp/fpc_private.h b/driver/fingerprint/fpc/libfp/fpc_private.h
index bd9ff711b6..19ac3b7a13 100644
--- a/driver/fingerprint/fpc/libfp/fpc_private.h
+++ b/driver/fingerprint/fpc/libfp/fpc_private.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,83 +10,103 @@
 
 /* External error codes from FPC's sensor library */
 enum fpc_error_code_external {
-	FPC_ERROR_NONE                        = 0,
-	FPC_ERROR_NOT_FOUND                   = 1,
-	FPC_ERROR_CAN_BE_USED_2               = 2,
-	FPC_ERROR_CAN_BE_USED_3               = 3,
-	FPC_ERROR_CAN_BE_USED_4               = 4,
-	FPC_ERROR_PAL                         = 5,
-	FPC_ERROR_IO                          = 6,
-	FPC_ERROR_CANCELLED                   = 7,
-	FPC_ERROR_UNKNOWN                     = 8,
-	FPC_ERROR_MEMORY                      = 9,
-	FPC_ERROR_PARAMETER                   = 10,
-	FPC_ERROR_TEST_FAILED                 = 11,
-	FPC_ERROR_TIMEDOUT                    = 12,
-	FPC_ERROR_SENSOR                      = 13,
-	FPC_ERROR_SPI                         = 14,
-	FPC_ERROR_NOT_SUPPORTED               = 15,
-	FPC_ERROR_OTP                         = 16,
-	FPC_ERROR_STATE                       = 17,
-	FPC_ERROR_PN                          = 18,
-	FPC_ERROR_DEAD_PIXELS                 = 19,
-	FPC_ERROR_TEMPLATE_CORRUPTED          = 20,
-	FPC_ERROR_CRC                         = 21,
-	FPC_ERROR_STORAGE                     = 22, /**< Errors related to storage                  **/
-	FPC_ERROR_MAXIMUM_REACHED             = 23, /**< The allowed maximum has been reached       **/
-	FPC_ERROR_MINIMUM_NOT_REACHED         = 24, /**< The required minimum was not reached       **/
-	FPC_ERROR_SENSOR_LOW_COVERAGE         = 25, /**< Minimum sensor coverage was not reached    **/
-	FPC_ERROR_SENSOR_LOW_QUALITY          = 26, /**< Sensor image is considered low quality     **/
-	FPC_ERROR_SENSOR_FINGER_NOT_STABLE    = 27, /**< Finger was not stable during image capture **/
+	FPC_ERROR_NONE = 0,
+	FPC_ERROR_NOT_FOUND = 1,
+	FPC_ERROR_CAN_BE_USED_2 = 2,
+	FPC_ERROR_CAN_BE_USED_3 = 3,
+	FPC_ERROR_CAN_BE_USED_4 = 4,
+	FPC_ERROR_PAL = 5,
+	FPC_ERROR_IO = 6,
+	FPC_ERROR_CANCELLED = 7,
+	FPC_ERROR_UNKNOWN = 8,
+	FPC_ERROR_MEMORY = 9,
+	FPC_ERROR_PARAMETER = 10,
+	FPC_ERROR_TEST_FAILED = 11,
+	FPC_ERROR_TIMEDOUT = 12,
+	FPC_ERROR_SENSOR = 13,
+	FPC_ERROR_SPI = 14,
+	FPC_ERROR_NOT_SUPPORTED = 15,
+	FPC_ERROR_OTP = 16,
+	FPC_ERROR_STATE = 17,
+	FPC_ERROR_PN = 18,
+	FPC_ERROR_DEAD_PIXELS = 19,
+	FPC_ERROR_TEMPLATE_CORRUPTED = 20,
+	FPC_ERROR_CRC = 21,
+	FPC_ERROR_STORAGE = 22, /**< Errors related to storage **/
+	FPC_ERROR_MAXIMUM_REACHED = 23, /**< The allowed maximum has been
+					   reached       **/
+	FPC_ERROR_MINIMUM_NOT_REACHED = 24, /**< The required minimum was not
+					       reached       **/
+	FPC_ERROR_SENSOR_LOW_COVERAGE = 25, /**< Minimum sensor coverage was not
+					       reached    **/
+	FPC_ERROR_SENSOR_LOW_QUALITY = 26, /**< Sensor image is considered low
+					      quality     **/
+	FPC_ERROR_SENSOR_FINGER_NOT_STABLE = 27, /**< Finger was not stable
+						    during image capture **/
 };
 
 /* Internal error codes from FPC's sensor library */
 enum fpc_error_code_internal {
-	FPC_ERROR_INTERNAL_0  = 0,  /* Indicates that no internal code was set.                         */
-	FPC_ERROR_INTERNAL_1  = 1,  /* Not supported by sensor.                                         */
-	FPC_ERROR_INTERNAL_2  = 2,  /* Sensor got a NULL response (from other module).                  */
-	FPC_ERROR_INTERNAL_3  = 3,  /* Runtime config not supported by firmware.                        */
-	FPC_ERROR_INTERNAL_4  = 4,  /* CAC has not been created.                                        */
-	FPC_ERROR_INTERNAL_5  = 5,  /* CAC returned an error to the sensor.                             */
-	FPC_ERROR_INTERNAL_6  = 6,  /* CAC fasttap image capture failed.                                */
-	FPC_ERROR_INTERNAL_7  = 7,  /* CAC fasttap image capture failed.                                */
-	FPC_ERROR_INTERNAL_8  = 8,  /* CAC Simple image capture failed.                                 */
-	FPC_ERROR_INTERNAL_9  = 9,  /* CAC custom image capture failed.                                 */
-	FPC_ERROR_INTERNAL_10 = 10, /* CAC MQT image capture failed.                                    */
-	FPC_ERROR_INTERNAL_11 = 11, /* CAC PN image capture failed.                                     */
-	FPC_ERROR_INTERNAL_12 = 12, /* Reading CAC context size.                                        */
-	FPC_ERROR_INTERNAL_13 = 13, /* Reading CAC context size.                                        */
-	FPC_ERROR_INTERNAL_14 = 14, /* Sensor context invalid.                                          */
-	FPC_ERROR_INTERNAL_15 = 15, /* Buffer reference is invalid.                                     */
-	FPC_ERROR_INTERNAL_16 = 16, /* Buffer size reference is invalid.                                */
-	FPC_ERROR_INTERNAL_17 = 17, /* Image data reference is invalid.                                 */
-	FPC_ERROR_INTERNAL_18 = 18, /* Capture type specified is invalid.                               */
-	FPC_ERROR_INTERNAL_19 = 19, /* Capture config specified is invalid.                             */
-	FPC_ERROR_INTERNAL_20 = 20, /* Sensor type in hw desc could not be extracted.                   */
-	FPC_ERROR_INTERNAL_21 = 21, /* Failed to create BNC component.                                  */
-	FPC_ERROR_INTERNAL_22 = 22, /* BN calibration failed.                                           */
-	FPC_ERROR_INTERNAL_23 = 23, /* BN memory allocation failed.                                     */
-	FPC_ERROR_INTERNAL_24 = 24, /* Companion type in hw desc could not be extracted.                */
-	FPC_ERROR_INTERNAL_25 = 25, /* Coating type in hw desc could not be extracted.                  */
-	FPC_ERROR_INTERNAL_26 = 26, /* Sensor mode type is invalid.                                     */
-	FPC_ERROR_INTERNAL_27 = 27, /* Wrong Sensor state in OTP read.                                  */
-	FPC_ERROR_INTERNAL_28 = 28, /* Mismatch of register size in overlay vs rrs.                     */
-	FPC_ERROR_INTERNAL_29 = 29, /* Checkerboard capture failed.                                     */
-	FPC_ERROR_INTERNAL_30 = 30, /* Error converting to fpc_image in dp calibration.                 */
-	FPC_ERROR_INTERNAL_31 = 31, /* Failed to capture reset pixel image.                             */
-	FPC_ERROR_INTERNAL_32 = 32, /* API level not support in dp calibration.                         */
-	FPC_ERROR_INTERNAL_33 = 33, /* The image data in parameter is invalid.                          */
-	FPC_ERROR_INTERNAL_34 = 34, /* PAL delay function has failed.                                   */
-	FPC_ERROR_INTERNAL_35 = 35, /* AFD sensor commad did not complete.                              */
-	FPC_ERROR_INTERNAL_36 = 36, /* AFD wrong runlevel detected after calibration.                   */
-	FPC_ERROR_INTERNAL_37 = 37, /* Wrong rrs size.                                                  */
-	FPC_ERROR_INTERNAL_38 = 38, /* There was a finger on the sensor when calibrating finger detect. */
-	FPC_ERROR_INTERNAL_39 = 39, /* The calculated calibration value is larger than max.             */
-	FPC_ERROR_INTERNAL_40 = 40, /* The sensor fifo always underflows                                */
-	FPC_ERROR_INTERNAL_41 = 41, /* The oscillator calibration resulted in a too high or low value   */
-	FPC_ERROR_INTERNAL_42 = 42, /* Sensor driver was opened with NULL configuration                 */
-	FPC_ERROR_INTERNAL_43 = 43, /* Sensor driver as opened with NULL hw descriptor                  */
-	FPC_ERROR_INTERNAL_44 = 44, /* Error occured during image drive test                            */
+	FPC_ERROR_INTERNAL_0 = 0, /* Indicates that no internal code was set. */
+	FPC_ERROR_INTERNAL_1 = 1, /* Not supported by sensor. */
+	FPC_ERROR_INTERNAL_2 = 2, /* Sensor got a NULL response (from other
+				     module).                  */
+	FPC_ERROR_INTERNAL_3 = 3, /* Runtime config not supported by firmware.
+				   */
+	FPC_ERROR_INTERNAL_4 = 4, /* CAC has not been created. */
+	FPC_ERROR_INTERNAL_5 = 5, /* CAC returned an error to the sensor. */
+	FPC_ERROR_INTERNAL_6 = 6, /* CAC fasttap image capture failed. */
+	FPC_ERROR_INTERNAL_7 = 7, /* CAC fasttap image capture failed. */
+	FPC_ERROR_INTERNAL_8 = 8, /* CAC Simple image capture failed. */
+	FPC_ERROR_INTERNAL_9 = 9, /* CAC custom image capture failed. */
+	FPC_ERROR_INTERNAL_10 = 10, /* CAC MQT image capture failed. */
+	FPC_ERROR_INTERNAL_11 = 11, /* CAC PN image capture failed. */
+	FPC_ERROR_INTERNAL_12 = 12, /* Reading CAC context size. */
+	FPC_ERROR_INTERNAL_13 = 13, /* Reading CAC context size. */
+	FPC_ERROR_INTERNAL_14 = 14, /* Sensor context invalid. */
+	FPC_ERROR_INTERNAL_15 = 15, /* Buffer reference is invalid. */
+	FPC_ERROR_INTERNAL_16 = 16, /* Buffer size reference is invalid. */
+	FPC_ERROR_INTERNAL_17 = 17, /* Image data reference is invalid. */
+	FPC_ERROR_INTERNAL_18 = 18, /* Capture type specified is invalid. */
+	FPC_ERROR_INTERNAL_19 = 19, /* Capture config specified is invalid. */
+	FPC_ERROR_INTERNAL_20 = 20, /* Sensor type in hw desc could not be
+				       extracted.                   */
+	FPC_ERROR_INTERNAL_21 = 21, /* Failed to create BNC component. */
+	FPC_ERROR_INTERNAL_22 = 22, /* BN calibration failed. */
+	FPC_ERROR_INTERNAL_23 = 23, /* BN memory allocation failed. */
+	FPC_ERROR_INTERNAL_24 = 24, /* Companion type in hw desc could not be
+				       extracted.                */
+	FPC_ERROR_INTERNAL_25 = 25, /* Coating type in hw desc could not be
+				       extracted.                  */
+	FPC_ERROR_INTERNAL_26 = 26, /* Sensor mode type is invalid. */
+	FPC_ERROR_INTERNAL_27 = 27, /* Wrong Sensor state in OTP read. */
+	FPC_ERROR_INTERNAL_28 = 28, /* Mismatch of register size in overlay vs
+				       rrs.                     */
+	FPC_ERROR_INTERNAL_29 = 29, /* Checkerboard capture failed. */
+	FPC_ERROR_INTERNAL_30 = 30, /* Error converting to fpc_image in dp
+				       calibration.                 */
+	FPC_ERROR_INTERNAL_31 = 31, /* Failed to capture reset pixel image. */
+	FPC_ERROR_INTERNAL_32 = 32, /* API level not support in dp calibration.
+				     */
+	FPC_ERROR_INTERNAL_33 = 33, /* The image data in parameter is invalid.
+				     */
+	FPC_ERROR_INTERNAL_34 = 34, /* PAL delay function has failed. */
+	FPC_ERROR_INTERNAL_35 = 35, /* AFD sensor commad did not complete. */
+	FPC_ERROR_INTERNAL_36 = 36, /* AFD wrong runlevel detected after
+				       calibration.                   */
+	FPC_ERROR_INTERNAL_37 = 37, /* Wrong rrs size. */
+	FPC_ERROR_INTERNAL_38 = 38, /* There was a finger on the sensor when
+				       calibrating finger detect. */
+	FPC_ERROR_INTERNAL_39 = 39, /* The calculated calibration value is
+				       larger than max.             */
+	FPC_ERROR_INTERNAL_40 = 40, /* The sensor fifo always underflows */
+	FPC_ERROR_INTERNAL_41 = 41, /* The oscillator calibration resulted in a
+				       too high or low value   */
+	FPC_ERROR_INTERNAL_42 = 42, /* Sensor driver was opened with NULL
+				       configuration                 */
+	FPC_ERROR_INTERNAL_43 = 43, /* Sensor driver as opened with NULL hw
+				       descriptor                  */
+	FPC_ERROR_INTERNAL_44 = 44, /* Error occured during image drive test */
 };
 
 /* FPC specific initialization function to fill their context */
diff --git a/driver/fingerprint/fpc/libfp/fpc_sensor_pal.c b/driver/fingerprint/fpc/libfp/fpc_sensor_pal.c
index 35c07b464a..c0578bc09b 100644
--- a/driver/fingerprint/fpc/libfp/fpc_sensor_pal.c
+++ b/driver/fingerprint/fpc/libfp/fpc_sensor_pal.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,8 +14,8 @@
 #include "uart.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_FP, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_FP, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_FP, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_FP, format, ##args)
 
 void fpc_pal_log_entry(const char *tag, int log_level, const char *format, ...)
 {
diff --git a/driver/fingerprint/fpc/libfp/fpc_sensor_pal.h b/driver/fingerprint/fpc/libfp/fpc_sensor_pal.h
index 78376863f1..844f1d7498 100644
--- a/driver/fingerprint/fpc/libfp/fpc_sensor_pal.h
+++ b/driver/fingerprint/fpc/libfp/fpc_sensor_pal.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,8 +14,10 @@ typedef void *fpc_device_t;
  * @brief Used to describe an interrupt
  */
 typedef enum {
-    IRQ_INT_TRIG = 0x01, /**< Internally triggered by sensor (fast interrupt)                   **/
-    IRQ_EXT_TRIG = 0x02  /**< Externally triggered by event outside sensor (may take long time) **/
+	IRQ_INT_TRIG = 0x01, /**< Internally triggered by sensor (fast
+				interrupt)                   **/
+	IRQ_EXT_TRIG = 0x02 /**< Externally triggered by event outside sensor
+			       (may take long time) **/
 } fpc_pal_irq_t;
 
 /**
@@ -109,9 +111,9 @@ int fpc_pal_spi_get_speed_hz(fpc_device_t device, uint32_t *speed_hz);
  * @param[in] ...        additional arguments.
  *
  */
-#define FPC_SENSOR_SDK_LOG_LEVEL_DEBUG    (1)
-#define FPC_SENSOR_SDK_LOG_LEVEL_INFO     (2)
-#define FPC_SENSOR_SDK_LOG_LEVEL_ERROR    (3)
+#define FPC_SENSOR_SDK_LOG_LEVEL_DEBUG (1)
+#define FPC_SENSOR_SDK_LOG_LEVEL_INFO (2)
+#define FPC_SENSOR_SDK_LOG_LEVEL_ERROR (3)
 #define FPC_SENSOR_SDK_LOG_LEVEL_DISABLED (4)
 void fpc_pal_log_entry(const char *tag, int log_level, const char *format, ...);
 
diff --git a/driver/fingerprint/fpsensor.h b/driver/fingerprint/fpsensor.h
index ac7e31fb6a..83e3143a55 100644
--- a/driver/fingerprint/fpsensor.h
+++ b/driver/fingerprint/fpsensor.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/driver/gl3590.c b/driver/gl3590.c
index cb8d914d8c..da374fbc88 100644
--- a/driver/gl3590.c
+++ b/driver/gl3590.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,8 +12,8 @@
 
 #include "gl3590.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args)
 
 /* GL3590 is unique in terms of i2c_read, since it doesn't support repeated
  * start sequence. One need to issue two separate transactions - first is write
@@ -25,11 +25,8 @@ int gl3590_read(int hub, uint8_t reg, uint8_t *data, int count)
 	struct uhub_i2c_iface_t *uhub_p = &uhub_config[hub];
 
 	i2c_lock(uhub_p->i2c_host_port, 1);
-	rv = i2c_xfer_unlocked(uhub_p->i2c_host_port,
-			       uhub_p->i2c_addr,
-			       &reg, 1,
-			       NULL, 0,
-			       I2C_XFER_SINGLE);
+	rv = i2c_xfer_unlocked(uhub_p->i2c_host_port, uhub_p->i2c_addr, &reg, 1,
+			       NULL, 0, I2C_XFER_SINGLE);
 	i2c_lock(uhub_p->i2c_host_port, 0);
 
 	if (rv)
@@ -39,11 +36,8 @@ int gl3590_read(int hub, uint8_t reg, uint8_t *data, int count)
 	udelay(MSEC);
 
 	i2c_lock(uhub_p->i2c_host_port, 1);
-	rv = i2c_xfer_unlocked(uhub_p->i2c_host_port,
-			       uhub_p->i2c_addr,
-			       NULL, 0,
-			       data, count,
-			       I2C_XFER_SINGLE);
+	rv = i2c_xfer_unlocked(uhub_p->i2c_host_port, uhub_p->i2c_addr, NULL, 0,
+			       data, count, I2C_XFER_SINGLE);
 	i2c_lock(uhub_p->i2c_host_port, 0);
 
 	/*
@@ -71,11 +65,8 @@ int gl3590_write(int hub, uint8_t reg, uint8_t *data, int count)
 	memcpy(&buf[1], data, count);
 
 	i2c_lock(uhub_p->i2c_host_port, 1);
-	rv = i2c_xfer_unlocked(uhub_p->i2c_host_port,
-			       uhub_p->i2c_addr,
-			       buf, count + 1,
-			       NULL, 0,
-			       I2C_XFER_SINGLE);
+	rv = i2c_xfer_unlocked(uhub_p->i2c_host_port, uhub_p->i2c_addr, buf,
+			       count + 1, NULL, 0, I2C_XFER_SINGLE);
 	i2c_lock(uhub_p->i2c_host_port, 0);
 
 	/*
@@ -164,7 +155,7 @@ void gl3590_irq_handler(int hub)
 	else
 		ccprintf("Host hub event! ");
 
-	switch(res_reg[0]) {
+	switch (res_reg[0]) {
 	case 0x0:
 		ccprintf("No response");
 		break;
@@ -247,7 +238,7 @@ enum ec_error_list gl3590_ufp_pwr(int hub, struct pwr_con_t *pwr)
 			return EC_SUCCESS;
 		} else {
 			CPRINTF("GL3590: Neither USB3 nor USB2 hubs "
-				 "configured\n");
+				"configured\n");
 			return EC_ERROR_HW_INTERNAL;
 		}
 	case GL3590_1_5_A_HOST_PWR_SRC:
@@ -262,11 +253,11 @@ enum ec_error_list gl3590_ufp_pwr(int hub, struct pwr_con_t *pwr)
 	}
 }
 
-#define GL3590_EN_PORT_MAX_RETRY_COUNT	10
+#define GL3590_EN_PORT_MAX_RETRY_COUNT 10
 
 int gl3590_enable_ports(int hub, uint8_t port_mask, bool enable)
 {
-	uint8_t buf[4] = {0};
+	uint8_t buf[4] = { 0 };
 	uint8_t en_mask = 0;
 	uint8_t tmp;
 	int rv, i;
@@ -306,15 +297,16 @@ int gl3590_enable_ports(int hub, uint8_t port_mask, bool enable)
 		}
 
 		CPRINTF("GL3590: Port %s retrying.. %d/%d\n"
-			"Port status is 0x%x\n", enable ? "enable" : "disable",
-			i, GL3590_EN_PORT_MAX_RETRY_COUNT, tmp);
+			"Port status is 0x%x\n",
+			enable ? "enable" : "disable", i,
+			GL3590_EN_PORT_MAX_RETRY_COUNT, tmp);
 	}
 
 	return EC_SUCCESS;
 }
 
 #ifdef CONFIG_CMD_GL3590
-static int command_gl3590(int argc, char **argv)
+static int command_gl3590(int argc, const char **argv)
 {
 	char *e;
 	int port;
diff --git a/driver/gl3590.h b/driver/gl3590.h
index 931035d95e..ef429c04f1 100644
--- a/driver/gl3590.h
+++ b/driver/gl3590.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,23 +7,23 @@
 #include "stdbool.h"
 
 /* Registers definitions */
-#define GL3590_HUB_MODE_REG		0x0
-#define GL3590_HUB_MODE_I2C_READY	0x1
-#define GL3590_HUB_MODE_USB2_EN		0x2
-#define GL3590_HUB_MODE_USB3_EN		0x4
-#define GL3590_INT_REG			0x1
-#define GL3590_INT_PENDING		0x1
-#define GL3590_INT_CLEAR		0x1
-#define GL3590_RESPONSE_REG		0x2
-#define GL3590_RESPONSE_REG_SYNC_MASK	0x80
-#define GL3590_PORT_DISABLED_REG	0x4
-#define GL3590_PORT_EN_STS_REG		0x8
-#define GL3590_HUB_STS_REG 		0xA
-#define GL3590_HUB_STS_HOST_PWR_MASK	0x30
-#define GL3590_HUB_STS_HOST_PWR_SHIFT	4
-#define GL3590_DEFAULT_HOST_PWR_SRC	0x0
-#define GL3590_1_5_A_HOST_PWR_SRC	0x1
-#define GL3590_3_0_A_HOST_PWR_SRC	0x2
+#define GL3590_HUB_MODE_REG 0x0
+#define GL3590_HUB_MODE_I2C_READY 0x1
+#define GL3590_HUB_MODE_USB2_EN 0x2
+#define GL3590_HUB_MODE_USB3_EN 0x4
+#define GL3590_INT_REG 0x1
+#define GL3590_INT_PENDING 0x1
+#define GL3590_INT_CLEAR 0x1
+#define GL3590_RESPONSE_REG 0x2
+#define GL3590_RESPONSE_REG_SYNC_MASK 0x80
+#define GL3590_PORT_DISABLED_REG 0x4
+#define GL3590_PORT_EN_STS_REG 0x8
+#define GL3590_HUB_STS_REG 0xA
+#define GL3590_HUB_STS_HOST_PWR_MASK 0x30
+#define GL3590_HUB_STS_HOST_PWR_SHIFT 4
+#define GL3590_DEFAULT_HOST_PWR_SRC 0x0
+#define GL3590_1_5_A_HOST_PWR_SRC 0x1
+#define GL3590_3_0_A_HOST_PWR_SRC 0x2
 
 #define GL3590_I2C_ADDR0 0x50
 
@@ -42,14 +42,14 @@ void gl3590_irq_handler(int hub);
 /* Get power capabilities of UFP host connection */
 enum ec_error_list gl3590_ufp_pwr(int hub, struct pwr_con_t *pwr);
 
-#define GL3590_DFP1	BIT(0)
-#define GL3590_DFP2	BIT(1)
-#define GL3590_DFP3	BIT(2)
-#define GL3590_DFP4	BIT(3)
-#define GL3590_DFP5	BIT(4)
-#define GL3590_DFP6	BIT(5)
-#define GL3590_DFP7	BIT(6)
-#define GL3590_DFP8	BIT(7)
+#define GL3590_DFP1 BIT(0)
+#define GL3590_DFP2 BIT(1)
+#define GL3590_DFP3 BIT(2)
+#define GL3590_DFP4 BIT(3)
+#define GL3590_DFP5 BIT(4)
+#define GL3590_DFP6 BIT(5)
+#define GL3590_DFP7 BIT(6)
+#define GL3590_DFP8 BIT(7)
 
 /* Enable/disable power to particular downstream facing ports */
 int gl3590_enable_ports(int hub, uint8_t port_mask, bool enable);
diff --git a/driver/gyro_l3gd20h.c b/driver/gyro_l3gd20h.c
index 77dd888542..9e47b86893 100644
--- a/driver/gyro_l3gd20h.c
+++ b/driver/gyro_l3gd20h.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,8 +17,8 @@
 #include "util.h"
 
 #define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
 
 /*
  * Struct for pairing an engineering value with the register value for a
@@ -33,15 +33,13 @@ struct gyro_param_pair {
  * List of angular rate range values in +/-dps's
  * and their associated register values.
  */
-const struct gyro_param_pair dps_ranges[] = {
-	{245, L3GD20_DPS_SEL_245},
-	{500, L3GD20_DPS_SEL_500},
-	{2000, L3GD20_DPS_SEL_2000_0},
-	{2000, L3GD20_DPS_SEL_2000_1}
-};
+const struct gyro_param_pair dps_ranges[] = { { 245, L3GD20_DPS_SEL_245 },
+					      { 500, L3GD20_DPS_SEL_500 },
+					      { 2000, L3GD20_DPS_SEL_2000_0 },
+					      { 2000, L3GD20_DPS_SEL_2000_1 } };
 
-static inline const struct gyro_param_pair *get_range_table(
-		enum motionsensor_type type, int *psize)
+static inline const struct gyro_param_pair *
+get_range_table(enum motionsensor_type type, int *psize)
 {
 	if (psize)
 		*psize = ARRAY_SIZE(dps_ranges);
@@ -50,19 +48,19 @@ static inline const struct gyro_param_pair *get_range_table(
 
 /* List of ODR values in mHz and their associated register values. */
 const struct gyro_param_pair gyro_odr[] = {
-	{0,      L3GD20_ODR_PD | L3GD20_LOW_ODR_MASK},
-	{12500,  L3GD20_ODR_12_5HZ | L3GD20_ODR_PD_MASK | L3GD20_LOW_ODR_MASK},
-	{25000,  L3GD20_ODR_25HZ | L3GD20_ODR_PD_MASK | L3GD20_LOW_ODR_MASK},
-	{50000,  L3GD20_ODR_50HZ_0 | L3GD20_ODR_PD_MASK | L3GD20_LOW_ODR_MASK},
-	{50000,  L3GD20_ODR_50HZ_1 | L3GD20_ODR_PD_MASK | L3GD20_LOW_ODR_MASK},
-	{100000, L3GD20_ODR_100HZ | L3GD20_ODR_PD_MASK},
-	{200000, L3GD20_ODR_200HZ | L3GD20_ODR_PD_MASK},
-	{400000, L3GD20_ODR_400HZ | L3GD20_ODR_PD_MASK},
-	{800000, L3GD20_ODR_800HZ | L3GD20_ODR_PD_MASK},
+	{ 0, L3GD20_ODR_PD | L3GD20_LOW_ODR_MASK },
+	{ 12500, L3GD20_ODR_12_5HZ | L3GD20_ODR_PD_MASK | L3GD20_LOW_ODR_MASK },
+	{ 25000, L3GD20_ODR_25HZ | L3GD20_ODR_PD_MASK | L3GD20_LOW_ODR_MASK },
+	{ 50000, L3GD20_ODR_50HZ_0 | L3GD20_ODR_PD_MASK | L3GD20_LOW_ODR_MASK },
+	{ 50000, L3GD20_ODR_50HZ_1 | L3GD20_ODR_PD_MASK | L3GD20_LOW_ODR_MASK },
+	{ 100000, L3GD20_ODR_100HZ | L3GD20_ODR_PD_MASK },
+	{ 200000, L3GD20_ODR_200HZ | L3GD20_ODR_PD_MASK },
+	{ 400000, L3GD20_ODR_400HZ | L3GD20_ODR_PD_MASK },
+	{ 800000, L3GD20_ODR_800HZ | L3GD20_ODR_PD_MASK },
 };
 
-static inline const struct gyro_param_pair *get_odr_table(
-		enum motionsensor_type type, int *psize)
+static inline const struct gyro_param_pair *
+get_odr_table(enum motionsensor_type type, int *psize)
 {
 	if (psize)
 		*psize = ARRAY_SIZE(gyro_odr);
@@ -86,14 +84,14 @@ static inline int get_xyz_reg(enum motionsensor_type type)
  * outside the range of values, it returns the closest valid reg value.
  */
 static int get_reg_val(const int eng_val, const int round_up,
-		const struct gyro_param_pair *pairs, const int size)
+		       const struct gyro_param_pair *pairs, const int size)
 {
 	int i;
 	for (i = 0; i < size - 1; i++) {
 		if (eng_val <= pairs[i].val)
 			break;
 
-		if (eng_val < pairs[i+1].val) {
+		if (eng_val < pairs[i + 1].val) {
 			if (round_up)
 				i += 1;
 			break;
@@ -106,7 +104,8 @@ static int get_reg_val(const int eng_val, const int round_up,
  * @return engineering value that matches the given reg val
  */
 static int get_engineering_val(const int reg_val,
-		const struct gyro_param_pair *pairs, const int size)
+			       const struct gyro_param_pair *pairs,
+			       const int size)
 {
 	int i;
 	for (i = 0; i < size; i++) {
@@ -120,7 +119,7 @@ static int get_engineering_val(const int reg_val,
  * Read register from Gyrometer.
  */
 static inline int raw_read8(const int port, const int addr, const int reg,
-							int *data_ptr)
+			    int *data_ptr)
 {
 	return i2c_read8(port, addr, reg, data_ptr);
 }
@@ -129,14 +128,12 @@ static inline int raw_read8(const int port, const int addr, const int reg,
  * Write register from Gyrometer.
  */
 static inline int raw_write8(const int port, const int addr, const int reg,
-							 int data)
+			     int data)
 {
 	return i2c_write8(port, addr, reg, data);
 }
 
-static int set_range(struct motion_sensor_t *s,
-				int range,
-				int rnd)
+static int set_range(struct motion_sensor_t *s, int range, int rnd)
 {
 	int ret, ctrl_val, range_tbl_size;
 	uint8_t ctrl_reg, reg_val;
@@ -162,8 +159,8 @@ static int set_range(struct motion_sensor_t *s,
 
 	/* Now that we have set the range, update the driver's value. */
 	if (ret == EC_SUCCESS)
-		s->current_range = get_engineering_val(reg_val, ranges,
-						       range_tbl_size);
+		s->current_range =
+			get_engineering_val(reg_val, ranges, range_tbl_size);
 
 gyro_cleanup:
 	mutex_unlock(s->mutex);
@@ -175,9 +172,7 @@ static int get_resolution(const struct motion_sensor_t *s)
 	return L3GD20_RESOLUTION;
 }
 
-static int set_data_rate(const struct motion_sensor_t *s,
-				int rate,
-				int rnd)
+static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
 {
 	int ret, val, odr_tbl_size;
 	uint8_t ctrl_reg, reg_val;
@@ -199,13 +194,13 @@ static int set_data_rate(const struct motion_sensor_t *s,
 		goto gyro_cleanup;
 
 	val = (val & ~(L3GD20_ODR_MASK | L3GD20_ODR_PD_MASK)) |
-		(reg_val & ~L3GD20_LOW_ODR_MASK);
+	      (reg_val & ~L3GD20_LOW_ODR_MASK);
 	ret = raw_write8(s->port, s->addr, ctrl_reg, val);
 
 	/* Now that we have set the odr, update the driver's value. */
 	if (ret == EC_SUCCESS)
-		data->base.odr = get_engineering_val(reg_val, data_rates,
-						       odr_tbl_size);
+		data->base.odr =
+			get_engineering_val(reg_val, data_rates, odr_tbl_size);
 
 	ret = raw_read8(s->port, s->addr, L3GD20_LOW_ODR, &val);
 	if (ret != EC_SUCCESS)
@@ -263,9 +258,8 @@ static int get_data_rate(const struct motion_sensor_t *s)
 	return data->base.odr;
 }
 
-static int set_offset(const struct motion_sensor_t *s,
-			const int16_t *offset,
-			int16_t    temp)
+static int set_offset(const struct motion_sensor_t *s, const int16_t *offset,
+		      int16_t temp)
 {
 	/* temperature is ignored */
 	struct l3gd20_data *data = s->drv_data;
@@ -275,9 +269,8 @@ static int set_offset(const struct motion_sensor_t *s,
 	return EC_SUCCESS;
 }
 
-static int get_offset(const struct motion_sensor_t *s,
-			int16_t    *offset,
-			int16_t    *temp)
+static int get_offset(const struct motion_sensor_t *s, int16_t *offset,
+		      int16_t *temp)
 {
 	struct l3gd20_data *data = s->drv_data;
 	offset[X] = data->offset[X];
diff --git a/driver/gyro_l3gd20h.h b/driver/gyro_l3gd20h.h
index 7a7ed6b7da..26e4e55d10 100644
--- a/driver/gyro_l3gd20h.h
+++ b/driver/gyro_l3gd20h.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,65 +15,65 @@
  * 7-bit address is 110101Xb. Where 'X' is determined
  * by the voltage on the ADDR pin.
  */
-#define L3GD20_ADDR0_FLAGS       0x6a
-#define L3GD20_ADDR1_FLAGS       0x6b
+#define L3GD20_ADDR0_FLAGS 0x6a
+#define L3GD20_ADDR1_FLAGS 0x6b
 
 /* who am I  */
-#define L3GD20_WHO_AM_I          0xd7
+#define L3GD20_WHO_AM_I 0xd7
 
 /* Chip specific registers. */
-#define L3GD20_WHO_AM_I_REG      0x0f
-#define L3GD20_CTRL_REG1         0x20
-#define L3GD20_CTRL_REG2         0x21
-#define L3GD20_CTRL_REG3         0x22
-#define L3GD20_CTRL_REG4         0x23
-#define L3GD20_CTRL_REG5         0x24
-#define L3GD20_CTRL_REFERENCE    0x25
-#define L3GD20_OUT_TEMP          0x26
-#define L3GD20_STATUS_REG        0x27
-#define L3GD20_OUT_X_L           0x28
-#define L3GD20_OUT_X_H           0x29
-#define L3GD20_OUT_Y_L           0x2a
-#define L3GD20_OUT_Y_H           0x2b
-#define L3GD20_OUT_Z_L           0x2c
-#define L3GD20_OUT_Z_H           0x2d
-#define L3GD20_FIFO_CTRL_REG     0x2e
-#define L3GD20_FIFO_SRC_REG      0x2f
-#define L3GD20_INT1_CFG          0x30
-#define L3GD20_INT1_SRC          0x31
-#define L3GD20_INT1_TSH_XH       0x32
-#define L3GD20_INT1_TSH_XL       0x33
-#define L3GD20_INT1_TSH_YH       0x34
-#define L3GD20_INT1_TSH_YL       0x35
-#define L3GD20_INT1_TSH_ZH       0x36
-#define L3GD20_INT1_TSH_ZL       0x37
-#define L3GD20_INT1_DURATION     0x38
-#define L3GD20_LOW_ODR           0x39
+#define L3GD20_WHO_AM_I_REG 0x0f
+#define L3GD20_CTRL_REG1 0x20
+#define L3GD20_CTRL_REG2 0x21
+#define L3GD20_CTRL_REG3 0x22
+#define L3GD20_CTRL_REG4 0x23
+#define L3GD20_CTRL_REG5 0x24
+#define L3GD20_CTRL_REFERENCE 0x25
+#define L3GD20_OUT_TEMP 0x26
+#define L3GD20_STATUS_REG 0x27
+#define L3GD20_OUT_X_L 0x28
+#define L3GD20_OUT_X_H 0x29
+#define L3GD20_OUT_Y_L 0x2a
+#define L3GD20_OUT_Y_H 0x2b
+#define L3GD20_OUT_Z_L 0x2c
+#define L3GD20_OUT_Z_H 0x2d
+#define L3GD20_FIFO_CTRL_REG 0x2e
+#define L3GD20_FIFO_SRC_REG 0x2f
+#define L3GD20_INT1_CFG 0x30
+#define L3GD20_INT1_SRC 0x31
+#define L3GD20_INT1_TSH_XH 0x32
+#define L3GD20_INT1_TSH_XL 0x33
+#define L3GD20_INT1_TSH_YH 0x34
+#define L3GD20_INT1_TSH_YL 0x35
+#define L3GD20_INT1_TSH_ZH 0x36
+#define L3GD20_INT1_TSH_ZL 0x37
+#define L3GD20_INT1_DURATION 0x38
+#define L3GD20_LOW_ODR 0x39
 
-#define L3GD20_DPS_SEL_245       (0 << 4)
-#define L3GD20_DPS_SEL_500       BIT(4)
-#define L3GD20_DPS_SEL_2000_0    (2 << 4)
-#define L3GD20_DPS_SEL_2000_1    (3 << 4)
+#define L3GD20_DPS_SEL_245 (0 << 4)
+#define L3GD20_DPS_SEL_500 BIT(4)
+#define L3GD20_DPS_SEL_2000_0 (2 << 4)
+#define L3GD20_DPS_SEL_2000_1 (3 << 4)
 
-#define L3GD20_ODR_PD            (0 << 3)
-#define L3GD20_ODR_12_5HZ        (0 << 6)
-#define L3GD20_ODR_25HZ          BIT(6)
-#define L3GD20_ODR_50HZ_0        (2 << 6)
-#define L3GD20_ODR_50HZ_1        (3 << 6)
-#define L3GD20_ODR_100HZ         (0 << 6)
-#define L3GD20_ODR_200HZ         BIT(6)
-#define L3GD20_ODR_400HZ         (2 << 6)
-#define L3GD20_ODR_800HZ         (3 << 6)
+#define L3GD20_ODR_PD (0 << 3)
+#define L3GD20_ODR_12_5HZ (0 << 6)
+#define L3GD20_ODR_25HZ BIT(6)
+#define L3GD20_ODR_50HZ_0 (2 << 6)
+#define L3GD20_ODR_50HZ_1 (3 << 6)
+#define L3GD20_ODR_100HZ (0 << 6)
+#define L3GD20_ODR_200HZ BIT(6)
+#define L3GD20_ODR_400HZ (2 << 6)
+#define L3GD20_ODR_800HZ (3 << 6)
 
-#define L3GD20_ODR_MASK          (3 << 6)
-#define L3GD20_STS_ZYXDA_MASK    BIT(3)
-#define L3GD20_RANGE_MASK        (3 << 4)
-#define L3GD20_LOW_ODR_MASK      BIT(0)
-#define L3GD20_ODR_PD_MASK       BIT(3)
+#define L3GD20_ODR_MASK (3 << 6)
+#define L3GD20_STS_ZYXDA_MASK BIT(3)
+#define L3GD20_RANGE_MASK (3 << 4)
+#define L3GD20_LOW_ODR_MASK BIT(0)
+#define L3GD20_ODR_PD_MASK BIT(3)
 
 /* Min and Max sampling frequency in mHz */
-#define L3GD20_GYRO_MIN_FREQ     12500
-#define L3GD20_GYRO_MAX_FREQ     \
+#define L3GD20_GYRO_MIN_FREQ 12500
+#define L3GD20_GYRO_MAX_FREQ \
 	MOTION_MAX_SENSOR_FREQUENCY(800000, L3GD20_GYRO_MIN_FREQ)
 
 /*
@@ -81,8 +81,8 @@
  * Address       : 0X27
  */
 enum l3gd20_status {
-	L3GD20_STS_DOWN          = 0x00,
-	L3GD20_STS_ZYXDA_UP      = 0x08,
+	L3GD20_STS_DOWN = 0x00,
+	L3GD20_STS_ZYXDA_UP = 0x08,
 };
 
 /*
@@ -91,12 +91,12 @@ enum l3gd20_status {
  * Bit Group Name: BDU
  */
 enum l3gd20_bdu {
-	L3GD20_BDU_DISABLE       = 0x00,
-	L3GD20_BDU_ENABLE        = 0x80,
+	L3GD20_BDU_DISABLE = 0x00,
+	L3GD20_BDU_ENABLE = 0x80,
 };
 
 /* Sensor resolution in number of bits. This sensor has fixed resolution. */
-#define L3GD20_RESOLUTION        16
+#define L3GD20_RESOLUTION 16
 
 extern const struct accelgyro_drv l3gd20h_drv;
 struct l3gd20_data {
diff --git a/driver/ina2xx.c b/driver/ina2xx.c
index cf4389ba49..e09c141f50 100644
--- a/driver/ina2xx.c
+++ b/driver/ina2xx.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -14,7 +14,7 @@
 #include "util.h"
 
 /* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
 
 /* I2C base address */
 #define INA2XX_I2C_ADDR_FLAGS 0x40
@@ -24,8 +24,8 @@ uint16_t ina2xx_read(uint8_t idx, uint8_t reg)
 	int res;
 	int val;
 
-	res = i2c_read16(I2C_PORT_MASTER, INA2XX_I2C_ADDR_FLAGS | idx,
-			 reg, &val);
+	res = i2c_read16(I2C_PORT_MASTER, INA2XX_I2C_ADDR_FLAGS | idx, reg,
+			 &val);
 	if (res) {
 		CPRINTS("INA2XX I2C read failed");
 		return 0x0bad;
@@ -38,8 +38,8 @@ int ina2xx_write(uint8_t idx, uint8_t reg, uint16_t val)
 	int res;
 	uint16_t be_val = (val >> 8) | ((val & 0xff) << 8);
 
-	res = i2c_write16(I2C_PORT_MASTER, INA2XX_I2C_ADDR_FLAGS | idx,
-			  reg, be_val);
+	res = i2c_write16(I2C_PORT_MASTER, INA2XX_I2C_ADDR_FLAGS | idx, reg,
+			  be_val);
 	if (res)
 		CPRINTS("INA2XX I2C write failed");
 	return res;
@@ -109,11 +109,10 @@ static void ina2xx_dump(uint8_t idx)
 
 	ccprintf("Configuration: %04x\n", cfg);
 	ccprintf("Shunt voltage: %04x => %d uV\n", sv,
-						   INA2XX_SHUNT_UV((int)sv));
-	ccprintf("Bus voltage  : %04x => %d mV\n", bv,
-						   INA2XX_BUS_MV((int)bv));
+		 INA2XX_SHUNT_UV((int)sv));
+	ccprintf("Bus voltage  : %04x => %d mV\n", bv, INA2XX_BUS_MV((int)bv));
 	ccprintf("Power        : %04x => %d mW\n", pow,
-						   INA2XX_POW_MW((int)pow));
+		 INA2XX_POW_MW((int)pow));
 	ccprintf("Current      : %04x => %d mA\n", curr, curr);
 	ccprintf("Calibration  : %04x\n", calib);
 	ccprintf("Mask/Enable  : %04x\n", mask);
@@ -123,7 +122,7 @@ static void ina2xx_dump(uint8_t idx)
 /*****************************************************************************/
 /* Console commands */
 
-static int command_ina(int argc, char **argv)
+static int command_ina(int argc, const char **argv)
 {
 	char *e;
 	int idx;
diff --git a/driver/ina2xx.h b/driver/ina2xx.h
index ec1e1ed92f..654283578c 100644
--- a/driver/ina2xx.h
+++ b/driver/ina2xx.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,28 +8,28 @@
 #ifndef __CROS_EC_INA2XX_H
 #define __CROS_EC_INA2XX_H
 
-#define INA2XX_REG_CONFIG     0x00
+#define INA2XX_REG_CONFIG 0x00
 #define INA2XX_REG_SHUNT_VOLT 0x01
-#define INA2XX_REG_BUS_VOLT   0x02
-#define INA2XX_REG_POWER      0x03
-#define INA2XX_REG_CURRENT    0x04
-#define INA2XX_REG_CALIB      0x05
-#define INA2XX_REG_MASK       0x06
-#define INA2XX_REG_ALERT      0x07
-
-#define INA2XX_CONFIG_MODE_MASK     (7 << 0)
-#define INA2XX_CONFIG_MODE_PWRDWN   (0 << 0)
-#define INA2XX_CONFIG_MODE_SHUNT    BIT(0)
-#define INA2XX_CONFIG_MODE_BUS      BIT(1)
-#define INA2XX_CONFIG_MODE_TRG      (0 << 2)
-#define INA2XX_CONFIG_MODE_CONT     BIT(2)
+#define INA2XX_REG_BUS_VOLT 0x02
+#define INA2XX_REG_POWER 0x03
+#define INA2XX_REG_CURRENT 0x04
+#define INA2XX_REG_CALIB 0x05
+#define INA2XX_REG_MASK 0x06
+#define INA2XX_REG_ALERT 0x07
+
+#define INA2XX_CONFIG_MODE_MASK (7 << 0)
+#define INA2XX_CONFIG_MODE_PWRDWN (0 << 0)
+#define INA2XX_CONFIG_MODE_SHUNT BIT(0)
+#define INA2XX_CONFIG_MODE_BUS BIT(1)
+#define INA2XX_CONFIG_MODE_TRG (0 << 2)
+#define INA2XX_CONFIG_MODE_CONT BIT(2)
 
 /* Conversion time for bus and shunt in micro-seconds */
 enum ina2xx_conv_time {
-	INA2XX_CONV_TIME_140  = 0x00,
-	INA2XX_CONV_TIME_204  = 0x01,
-	INA2XX_CONV_TIME_332  = 0x02,
-	INA2XX_CONV_TIME_588  = 0x03,
+	INA2XX_CONV_TIME_140 = 0x00,
+	INA2XX_CONV_TIME_204 = 0x01,
+	INA2XX_CONV_TIME_332 = 0x02,
+	INA2XX_CONV_TIME_588 = 0x03,
 	INA2XX_CONV_TIME_1100 = 0x04,
 	INA2XX_CONV_TIME_2116 = 0x05,
 	INA2XX_CONV_TIME_4156 = 0x06,
@@ -37,29 +37,28 @@ enum ina2xx_conv_time {
 };
 #define INA2XX_CONV_TIME_MASK 0x7
 #define INA2XX_CONFIG_SHUNT_CONV_TIME(t) ((t) << 3)
-#define INA2XX_CONFIG_BUS_CONV_TIME(t)   ((t) << 6)
-
-#define INA2XX_CONFIG_AVG_1        (0 << 9)
-#define INA2XX_CONFIG_AVG_4        BIT(9)
-#define INA2XX_CONFIG_AVG_16       (2 << 9)
-#define INA2XX_CONFIG_AVG_64       (3 << 9)
-#define INA2XX_CONFIG_AVG_128      (4 << 9)
-#define INA2XX_CONFIG_AVG_256      (5 << 9)
-#define INA2XX_CONFIG_AVG_512      (6 << 9)
-#define INA2XX_CONFIG_AVG_1024     (7 << 9)
-
-#define INA2XX_MASK_EN_LEN         BIT(0)
-#define INA2XX_MASK_EN_APOL        BIT(1)
-#define INA2XX_MASK_EN_OVF         BIT(2)
-#define INA2XX_MASK_EN_CVRF        BIT(3)
-#define INA2XX_MASK_EN_AFF         BIT(4)
-#define INA2XX_MASK_EN_CNVR        BIT(10)
-#define INA2XX_MASK_EN_POL         BIT(11)
-#define INA2XX_MASK_EN_BUL         BIT(12)
-#define INA2XX_MASK_EN_BOL         BIT(13)
-#define INA2XX_MASK_EN_SUL         BIT(14)
-#define INA2XX_MASK_EN_SOL        BIT(15)
-
+#define INA2XX_CONFIG_BUS_CONV_TIME(t) ((t) << 6)
+
+#define INA2XX_CONFIG_AVG_1 (0 << 9)
+#define INA2XX_CONFIG_AVG_4 BIT(9)
+#define INA2XX_CONFIG_AVG_16 (2 << 9)
+#define INA2XX_CONFIG_AVG_64 (3 << 9)
+#define INA2XX_CONFIG_AVG_128 (4 << 9)
+#define INA2XX_CONFIG_AVG_256 (5 << 9)
+#define INA2XX_CONFIG_AVG_512 (6 << 9)
+#define INA2XX_CONFIG_AVG_1024 (7 << 9)
+
+#define INA2XX_MASK_EN_LEN BIT(0)
+#define INA2XX_MASK_EN_APOL BIT(1)
+#define INA2XX_MASK_EN_OVF BIT(2)
+#define INA2XX_MASK_EN_CVRF BIT(3)
+#define INA2XX_MASK_EN_AFF BIT(4)
+#define INA2XX_MASK_EN_CNVR BIT(10)
+#define INA2XX_MASK_EN_POL BIT(11)
+#define INA2XX_MASK_EN_BUL BIT(12)
+#define INA2XX_MASK_EN_BOL BIT(13)
+#define INA2XX_MASK_EN_SUL BIT(14)
+#define INA2XX_MASK_EN_SOL BIT(15)
 
 #if defined(CONFIG_INA231) && defined(CONFIG_INA219)
 #error CONFIG_INA231 and CONFIG_INA219 must not be both defined.
@@ -68,28 +67,27 @@ enum ina2xx_conv_time {
 #ifdef CONFIG_INA231
 
 /* Calibration value to get current LSB = 1mA */
-#define INA2XX_CALIB_1MA(rsense_mohm) (5120/(rsense_mohm))
+#define INA2XX_CALIB_1MA(rsense_mohm) (5120 / (rsense_mohm))
 /* Bus voltage: mV per LSB */
-#define INA2XX_BUS_MV(reg) ((reg) * 125 / 100)
+#define INA2XX_BUS_MV(reg) ((reg)*125 / 100)
 /* Shunt voltage: uV per LSB */
-#define INA2XX_SHUNT_UV(reg) ((reg) * 25 / 10)
+#define INA2XX_SHUNT_UV(reg) ((reg)*25 / 10)
 /* Power LSB: mW per current LSB */
-#define INA2XX_POW_MW(reg) ((reg) * 25 * 1/*Current mA/LSB*/)
+#define INA2XX_POW_MW(reg) ((reg)*25 * 1 /*Current mA/LSB*/)
 
 #else /* CONFIG_INA219 */
 
 /* Calibration value to get current LSB = 1mA */
-#define INA2XX_CALIB_1MA(rsense_mohm) (40960/(rsense_mohm))
+#define INA2XX_CALIB_1MA(rsense_mohm) (40960 / (rsense_mohm))
 /* Bus voltage: mV per LSB */
 #define INA2XX_BUS_MV(reg) ((reg) / 2)
 /* Shunt voltage: uV */
-#define INA2XX_SHUNT_UV(reg) ((reg) * 10)
+#define INA2XX_SHUNT_UV(reg) ((reg)*10)
 /* Power LSB: mW per current LSB */
-#define INA2XX_POW_MW(reg) ((reg) * 20 * 1/*Current mA/LSB*/)
+#define INA2XX_POW_MW(reg) ((reg)*20 * 1 /*Current mA/LSB*/)
 
 #endif
 
-
 /* Read INA2XX register. */
 uint16_t ina2xx_read(uint8_t idx, uint8_t reg);
 
diff --git a/driver/ina3221.c b/driver/ina3221.c
index 5b89f9694e..4659552497 100644
--- a/driver/ina3221.c
+++ b/driver/ina3221.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -14,12 +14,12 @@
 #include "util.h"
 
 /* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
 
 const static uint8_t ina3221_reg_map[INA3221_CHAN_COUNT][INA3221_MAX_REG] = {
-{ 1, 2,  7,  8 }, /* Chan 1 */
-{ 3, 4,  9, 10 }, /* Chan 2 */
-{ 5, 6, 11, 12 }  /* Chan 3 */
+	{ 1, 2, 7, 8 }, /* Chan 1 */
+	{ 3, 4, 9, 10 }, /* Chan 2 */
+	{ 5, 6, 11, 12 } /* Chan 3 */
 };
 
 static uint16_t ina3221_read(unsigned int unit, uint8_t reg)
@@ -27,8 +27,7 @@ static uint16_t ina3221_read(unsigned int unit, uint8_t reg)
 	int res;
 	int val;
 
-	res = i2c_read16(ina3221[unit].port, ina3221[unit].address,
-			 reg, &val);
+	res = i2c_read16(ina3221[unit].port, ina3221[unit].address, reg, &val);
 	if (res) {
 		CPRINTS("INA3221 I2C read failed");
 		return 0x0bad;
@@ -37,7 +36,7 @@ static uint16_t ina3221_read(unsigned int unit, uint8_t reg)
 }
 
 static uint16_t ina3221_chan_read(unsigned int unit, enum ina3221_channel chan,
-			   enum ina3221_register reg)
+				  enum ina3221_register reg)
 {
 	if (chan >= INA3221_CHAN_COUNT || reg >= INA3221_MAX_REG) {
 		CPRINTS("INA3221 Bad channel or register value");
@@ -51,8 +50,8 @@ static int ina3221_write(unsigned int unit, uint8_t reg, uint16_t val)
 	int res;
 	uint16_t be_val = (val >> 8) | ((val & 0xff) << 8);
 
-	res = i2c_write16(ina3221[unit].port, ina3221[unit].address,
-			  reg, be_val);
+	res = i2c_write16(ina3221[unit].port, ina3221[unit].address, reg,
+			  be_val);
 	if (res)
 		CPRINTS("INA3221 I2C write failed");
 	return res;
@@ -93,12 +92,12 @@ static void ina3221_dump(unsigned int unit)
 		if (ina3221[unit].name[chan] != NULL) {
 			sv[chan] = ina3221_chan_read(unit, chan,
 						     INA3221_SHUNT_VOLT);
-			bv[chan] = ina3221_chan_read(unit, chan,
-						     INA3221_BUS_VOLT);
-			crit[chan] = ina3221_chan_read(unit, chan,
-						       INA3221_CRITICAL);
-			warn[chan] = ina3221_chan_read(unit, chan,
-						       INA3221_WARNING);
+			bv[chan] =
+				ina3221_chan_read(unit, chan, INA3221_BUS_VOLT);
+			crit[chan] =
+				ina3221_chan_read(unit, chan, INA3221_CRITICAL);
+			warn[chan] =
+				ina3221_chan_read(unit, chan, INA3221_WARNING);
 		}
 	}
 	mask = ina3221_read(unit, INA3221_REG_MASK);
@@ -109,9 +108,9 @@ static void ina3221_dump(unsigned int unit)
 		if (ina3221[unit].name[chan] != NULL) {
 			ccprintf("%d: %s:\n", chan, ina3221[unit].name[chan]);
 			ccprintf("      Shunt voltage: %04x => %d uV\n",
-				sv[chan], INA3221_SHUNT_UV((int)sv[chan]));
+				 sv[chan], INA3221_SHUNT_UV((int)sv[chan]));
 			ccprintf("      Bus voltage  : %04x => %d mV\n",
-				bv[chan], INA3221_BUS_MV((int)bv[chan]));
+				 bv[chan], INA3221_BUS_MV((int)bv[chan]));
 			ccprintf("      Warning      : %04x\n", warn[chan]);
 			ccprintf("      Critical     : %04x\n", crit[chan]);
 		}
@@ -122,7 +121,7 @@ static void ina3221_dump(unsigned int unit)
 /*****************************************************************************/
 /* Console commands */
 
-static int command_ina(int argc, char **argv)
+static int command_ina(int argc, const char **argv)
 {
 	char *e;
 	unsigned int unit;
@@ -156,7 +155,6 @@ static int command_ina(int argc, char **argv)
 
 	return EC_ERROR_INVAL;
 }
-DECLARE_CONSOLE_COMMAND(ina, command_ina,
-			"<index> [config|mask <val>]",
+DECLARE_CONSOLE_COMMAND(ina, command_ina, "<index> [config|mask <val>]",
 			"INA3221 voltage sensing");
 #endif
diff --git a/driver/ina3221.h b/driver/ina3221.h
index 4d8c8211b4..5d642bba3b 100644
--- a/driver/ina3221.h
+++ b/driver/ina3221.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,8 +8,8 @@
 #ifndef __CROS_EC_INA3221_H
 #define __CROS_EC_INA3221_H
 
-#define INA3221_REG_CONFIG	0x00
-#define INA3221_REG_MASK	0x0F
+#define INA3221_REG_CONFIG 0x00
+#define INA3221_REG_MASK 0x0F
 
 /*
  * Common bits are:
@@ -18,12 +18,12 @@
  * conversion time = 1.1 ms
  * mode = shunt and bus, continuous.
  */
-#define INA3221_CONFIG_BASE	0x8127
+#define INA3221_CONFIG_BASE 0x8127
 
 /* Bus voltage: lower 3 bits clear, LSB = 8 mV */
 #define INA3221_BUS_MV(reg) (reg)
 /* Shunt voltage: lower 3 bits clear, LSB = 40 uV */
-#define INA3221_SHUNT_UV(reg) ((reg) * (40/8))
+#define INA3221_SHUNT_UV(reg) ((reg) * (40 / 8))
 
 enum ina3221_channel {
 	INA3221_CHAN_1 = 0,
@@ -43,9 +43,9 @@ enum ina3221_register {
 
 /* Configuration table - defined in board file. */
 struct ina3221_t {
-	int port;             /* I2C port index */
-	uint8_t address;      /* I2C address */
-	const char *name[INA3221_CHAN_COUNT];  /* Channel names */
+	int port; /* I2C port index */
+	uint8_t address; /* I2C address */
+	const char *name[INA3221_CHAN_COUNT]; /* Channel names */
 };
 
 /* External config in board file */
diff --git a/driver/ioexpander/ccgxxf.c b/driver/ioexpander/ccgxxf.c
index 08dd17c863..a95d17ada3 100644
--- a/driver/ioexpander/ccgxxf.c
+++ b/driver/ioexpander/ccgxxf.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -12,25 +12,25 @@
 /* Add after all include files */
 #include "ccgxxf.h"
 
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
 
 static inline int ccgxxf_read8(int ioex, int reg, int *data)
 {
 	return i2c_read8(ioex_config[ioex].i2c_host_port,
-			ioex_config[ioex].i2c_addr_flags, reg, data);
+			 ioex_config[ioex].i2c_addr_flags, reg, data);
 }
 
 static inline int ccgxxf_update8(int ioex, int reg, uint8_t mask,
-				enum mask_update_action action)
+				 enum mask_update_action action)
 {
 	return i2c_update8(ioex_config[ioex].i2c_host_port,
-			ioex_config[ioex].i2c_addr_flags, reg, mask, action);
+			   ioex_config[ioex].i2c_addr_flags, reg, mask, action);
 }
 
 static inline int ccgxxf_write16(int ioex, uint16_t reg, uint16_t data)
 {
 	return i2c_write16(ioex_config[ioex].i2c_host_port,
-			ioex_config[ioex].i2c_addr_flags, reg, data);
+			   ioex_config[ioex].i2c_addr_flags, reg, data);
 }
 
 static int ccgxxf_get_level(int ioex, int port, int mask, int *val)
@@ -64,9 +64,9 @@ static int ccgxxf_set_flags_by_mask(int ioex, int port, int mask, int flags)
 
 	/* Push-pull output can't be configured for 1.8V level */
 	if ((flags & GPIO_OUTPUT) && (flags & GPIO_SEL_1P8V) &&
-		!(flags & GPIO_OPEN_DRAIN)) {
+	    !(flags & GPIO_OPEN_DRAIN)) {
 		CPRINTS("Invalid flags: ioex=%d, port=%d, mask=%d, flags=0x%x",
-				ioex, port, mask, flags);
+			ioex, port, mask, flags);
 
 		return EC_ERROR_INVAL;
 	}
@@ -99,7 +99,7 @@ static int ccgxxf_set_flags_by_mask(int ioex, int port, int mask, int flags)
 	}
 
 	pin_mode = port | (pin_mode << CCGXXF_GPIO_PIN_MODE_SHIFT) |
-			(mask << CCGXXF_GPIO_PIN_MASK_SHIFT);
+		   (mask << CCGXXF_GPIO_PIN_MASK_SHIFT);
 
 	/* Note: once set the 1.8V level affect whole GPIO port */
 	if (flags & GPIO_SEL_1P8V)
@@ -111,17 +111,17 @@ static int ccgxxf_set_flags_by_mask(int ioex, int port, int mask, int flags)
 	 */
 	if (flags & (GPIO_HIGH | GPIO_LOW)) {
 		rv = ccgxxf_set_level(ioex, port, mask,
-					flags & GPIO_HIGH ? 1 : 0);
+				      flags & GPIO_HIGH ? 1 : 0);
 		if (rv)
 			return rv;
 	}
 
-	return	ccgxxf_write16(ioex, CCGXXF_REG_GPIO_MODE, pin_mode);
+	return ccgxxf_write16(ioex, CCGXXF_REG_GPIO_MODE, pin_mode);
 }
 
 static int ccgxxf_get_flags_by_mask(int ioex, int port, int mask, int *flags)
 {
-	 /* TODO: Add it after implementing in the CCGXXF firmware. */
+	/* TODO: Add it after implementing in the CCGXXF firmware. */
 	return EC_SUCCESS;
 }
 
@@ -131,7 +131,6 @@ static int ccgxxf_enable_interrupt(int ioex, int port, int mask, int enable)
 	return EC_ERROR_UNIMPLEMENTED;
 }
 
-
 #ifdef CONFIG_IO_EXPANDER_SUPPORT_GET_PORT
 static int ccgxxf_get_port(int ioex, int port, int *val)
 {
@@ -146,13 +145,13 @@ int ccgxxf_init(int ioex)
 }
 
 const struct ioexpander_drv ccgxxf_ioexpander_drv = {
-	.init			= &ccgxxf_init,
-	.get_level		= &ccgxxf_get_level,
-	.set_level		= &ccgxxf_set_level,
-	.get_flags_by_mask	= &ccgxxf_get_flags_by_mask,
-	.set_flags_by_mask	= &ccgxxf_set_flags_by_mask,
-	.enable_interrupt	= &ccgxxf_enable_interrupt,
+	.init = &ccgxxf_init,
+	.get_level = &ccgxxf_get_level,
+	.set_level = &ccgxxf_set_level,
+	.get_flags_by_mask = &ccgxxf_get_flags_by_mask,
+	.set_flags_by_mask = &ccgxxf_set_flags_by_mask,
+	.enable_interrupt = &ccgxxf_enable_interrupt,
 #ifdef CONFIG_IO_EXPANDER_SUPPORT_GET_PORT
-	.get_port		= &ccgxxf_get_port,
+	.get_port = &ccgxxf_get_port,
 #endif
 };
diff --git a/driver/ioexpander/ioexpander_nct38xx.c b/driver/ioexpander/ioexpander_nct38xx.c
index 6d30e4ecc3..a97bf06908 100644
--- a/driver/ioexpander/ioexpander_nct38xx.c
+++ b/driver/ioexpander/ioexpander_nct38xx.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,8 +13,8 @@
 #include "nct38xx.h"
 #include "tcpm/tcpci.h"
 
-#define CPRINTF(format, args...) cprintf(CC_GPIO, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_GPIO, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
 
 #ifdef CONFIG_IO_EXPANDER_SUPPORT_GET_PORT
 #error "This driver doesn't support get_port function"
@@ -30,7 +30,7 @@ struct nct38xx_chip_data {
 };
 
 static struct nct38xx_chip_data chip_data[CONFIG_IO_EXPANDER_PORT_COUNT] = {
-	 [0 ... (CONFIG_IO_EXPANDER_PORT_COUNT - 1)] =  { {0, 0}, -1 }
+	[0 ...(CONFIG_IO_EXPANDER_PORT_COUNT - 1)] = { { 0, 0 }, -1 }
 };
 
 static int nct38xx_ioex_check_is_valid(int ioex, int port, int mask)
@@ -41,9 +41,8 @@ static int nct38xx_ioex_check_is_valid(int ioex, int port, int mask)
 			return EC_ERROR_INVAL;
 		}
 		if (mask & ~NCT38XXX_3808_VALID_GPIO_MASK) {
-
 			CPRINTF("GPIO%02d is not support in NCT3808\n",
-							__fls(mask));
+				__fls(mask));
 			return EC_ERROR_INVAL;
 		}
 	}
@@ -62,11 +61,11 @@ static int nct38xx_ioex_init(int ioex)
 	 *  010: NCT3808
 	 */
 	rv = i2c_read8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags,
-			TCPC_REG_BCD_DEV, &val);
+		       TCPC_REG_BCD_DEV, &val);
 
 	if (rv != EC_SUCCESS) {
 		CPRINTF("Failed to read NCT38XX DEV ID for IOexpander %d\n",
-					ioex);
+			ioex);
 		return rv;
 	}
 
@@ -81,9 +80,9 @@ static int nct38xx_ioex_init(int ioex)
 	 * function of IOEX when the NCT38XX TCPCI driver is not included.
 	 */
 	if (!IS_ENABLED(CONFIG_USB_PD_TCPM_NCT38XX)) {
-		rv = i2c_write16(ioex_p->i2c_host_port,
-				ioex_p->i2c_addr_flags, TCPC_REG_ALERT_MASK,
-				TCPC_REG_ALERT_VENDOR_DEF);
+		rv = i2c_write16(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags,
+				 TCPC_REG_ALERT_MASK,
+				 TCPC_REG_ALERT_VENDOR_DEF);
 		if (rv != EC_SUCCESS)
 			return rv;
 	}
@@ -100,7 +99,7 @@ static int nct38xx_ioex_get_level(int ioex, int port, int mask, int *val)
 
 	reg = NCT38XX_REG_GPIO_DATA_IN(port);
 	rv = i2c_read8(ioex_config[ioex].i2c_host_port,
-			ioex_config[ioex].i2c_addr_flags, reg, val);
+		       ioex_config[ioex].i2c_addr_flags, reg, val);
 	if (rv != EC_SUCCESS)
 		return rv;
 
@@ -120,7 +119,7 @@ static int nct38xx_ioex_set_level(int ioex, int port, int mask, int value)
 	reg = NCT38XX_REG_GPIO_DATA_OUT(port);
 
 	rv = i2c_read8(ioex_config[ioex].i2c_host_port,
-			ioex_config[ioex].i2c_addr_flags, reg, &val);
+		       ioex_config[ioex].i2c_addr_flags, reg, &val);
 	if (rv != EC_SUCCESS)
 		return rv;
 
@@ -130,7 +129,7 @@ static int nct38xx_ioex_set_level(int ioex, int port, int mask, int value)
 		val &= ~mask;
 
 	return i2c_write8(ioex_config[ioex].i2c_host_port,
-			ioex_config[ioex].i2c_addr_flags, reg, val);
+			  ioex_config[ioex].i2c_addr_flags, reg, val);
 }
 
 static int nct38xx_ioex_get_flags(int ioex, int port, int mask, int *flags)
@@ -177,7 +176,7 @@ static int nct38xx_ioex_get_flags(int ioex, int port, int mask, int *flags)
 }
 
 static int nct38xx_ioex_sel_int_type(int i2c_port, int i2c_addr, int port,
-					int mask, int flags)
+				     int mask, int flags)
 {
 	int rv;
 	int reg_rising, reg_falling;
@@ -222,7 +221,7 @@ static int nct38xx_ioex_sel_int_type(int i2c_port, int i2c_addr, int port,
 		if (rv != EC_SUCCESS)
 			return rv;
 	} else if ((flags & GPIO_INT_F_RISING) ||
-				(flags & GPIO_INT_F_FALLING)) {
+		   (flags & GPIO_INT_F_FALLING)) {
 		if (flags & GPIO_INT_F_RISING)
 			rising |= mask;
 		else
@@ -242,7 +241,7 @@ static int nct38xx_ioex_sel_int_type(int i2c_port, int i2c_addr, int port,
 }
 
 static int nct38xx_ioex_set_flags_by_mask(int ioex, int port, int mask,
-					int flags)
+					  int flags)
 {
 	int rv, reg, val, i2c_port, i2c_addr;
 	struct ioexpander_config_t *ioex_p = &ioex_config[ioex];
@@ -260,8 +259,8 @@ static int nct38xx_ioex_set_flags_by_mask(int ioex, int port, int mask,
 	 */
 	if (port == 0) {
 		/* GPIO03 in NCT3807 is not muxed with other function. */
-		if (!(chip_data[ioex].chip_id ==
-					NCT38XX_VARIANT_3807 && mask & 0x08)) {
+		if (!(chip_data[ioex].chip_id == NCT38XX_VARIANT_3807 &&
+		      mask & 0x08)) {
 			reg = NCT38XX_REG_MUX_CONTROL;
 			rv = i2c_read8(i2c_port, i2c_addr, reg, &val);
 			if (rv != EC_SUCCESS)
@@ -320,7 +319,7 @@ static int nct38xx_ioex_set_flags_by_mask(int ioex, int port, int mask,
 	else
 		val &= ~mask;
 
-	return  i2c_write8(i2c_port, i2c_addr, reg, val);
+	return i2c_write8(i2c_port, i2c_addr, reg, val);
 }
 
 /*
@@ -341,7 +340,7 @@ static int nct38xx_ioex_set_flags_by_mask(int ioex, int port, int mask,
  *    TCPC.
  */
 static int nct38xx_ioex_enable_interrupt(int ioex, int port, int mask,
-					int enable)
+					 int enable)
 {
 	int rv, reg, val;
 	struct ioexpander_config_t *ioex_p = &ioex_config[ioex];
@@ -352,14 +351,14 @@ static int nct38xx_ioex_enable_interrupt(int ioex, int port, int mask,
 
 	/* Clear the pending bit */
 	reg = NCT38XX_REG_GPIO_ALERT_STAT(port);
-	rv = i2c_read8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags,
-					reg, &val);
+	rv = i2c_read8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, reg,
+		       &val);
 	if (rv != EC_SUCCESS)
 		return rv;
 
 	val |= mask;
-	rv = i2c_write8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags,
-					reg, val);
+	rv = i2c_write8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, reg,
+			val);
 	if (rv != EC_SUCCESS)
 		return rv;
 
@@ -374,8 +373,8 @@ static int nct38xx_ioex_enable_interrupt(int ioex, int port, int mask,
 		val = chip_data[ioex].int_mask[port];
 	}
 
-	return i2c_write8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags,
-					reg, val);
+	return i2c_write8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, reg,
+			  val);
 }
 
 int nct38xx_ioex_event_handler(int ioex)
@@ -386,15 +385,15 @@ int nct38xx_ioex_event_handler(int ioex)
 	struct ioexpander_config_t *ioex_p = &ioex_config[ioex];
 	int rv = 0;
 
-	int_mask = chip_data[ioex].int_mask[0] | (
-				chip_data[ioex].int_mask[1] << 8);
+	int_mask = chip_data[ioex].int_mask[0] |
+		   (chip_data[ioex].int_mask[1] << 8);
 	reg = NCT38XX_REG_GPIO_ALERT_STAT(0);
 	/*
 	 * Read ALERT_STAT_0 and ALERT_STAT_1 register in a single I2C
 	 * transaction to increase efficiency
 	 */
-	rv = i2c_read16(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags,
-					reg, &int_status);
+	rv = i2c_read16(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, reg,
+			&int_status);
 	if (rv != EC_SUCCESS)
 		return rv;
 
@@ -403,15 +402,15 @@ int nct38xx_ioex_event_handler(int ioex)
 	 * Clear the changed status bits in ALERT_STAT_0 and ALERT_STAT_1
 	 * register in a single I2C transaction to increase efficiency
 	 */
-	rv = i2c_write16(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags,
-					reg, int_status);
+	rv = i2c_write16(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, reg,
+			 int_status);
 	if (rv != EC_SUCCESS)
 		return rv;
 
 	/* For NCT3808, only check one port */
 	total_port = (chip_data[ioex].chip_id == NCT38XX_VARIANT_3808) ?
-		NCT38XX_NCT3808_MAX_IO_PORT :
-		NCT38XX_NCT3807_MAX_IO_PORT;
+			     NCT38XX_NCT3808_MAX_IO_PORT :
+			     NCT38XX_NCT3807_MAX_IO_PORT;
 	for (i = 0; i < total_port; i++) {
 		uint8_t pending;
 
@@ -421,15 +420,13 @@ int nct38xx_ioex_event_handler(int ioex)
 			continue;
 
 		for (j = 0, g = ioex_list; j < ioex_ih_count; j++, g++) {
-
 			if (ioex == g->ioex && i == g->port &&
-						(pending & g->mask)) {
+			    (pending & g->mask)) {
 				ioex_irq_handlers[j](j + IOEX_SIGNAL_START);
 				pending &= ~g->mask;
 				if (!pending)
 					break;
 			}
-
 		}
 	}
 
@@ -453,9 +450,8 @@ void nct38xx_ioex_handle_alert(int ioex)
 		CPRINTF("fail to read ALERT register\n");
 
 	if (status & TCPC_REG_ALERT_VENDOR_DEF) {
-		rv = i2c_write16(ioex_p->i2c_host_port,
-				ioex_p->i2c_addr_flags, TCPC_REG_ALERT,
-				TCPC_REG_ALERT_VENDOR_DEF);
+		rv = i2c_write16(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags,
+				 TCPC_REG_ALERT, TCPC_REG_ALERT_VENDOR_DEF);
 		if (rv != EC_SUCCESS) {
 			CPRINTF("Fail to clear Vendor Define mask\n");
 			return;
@@ -465,10 +461,10 @@ void nct38xx_ioex_handle_alert(int ioex)
 }
 
 const struct ioexpander_drv nct38xx_ioexpander_drv = {
-	.init              = &nct38xx_ioex_init,
-	.get_level         = &nct38xx_ioex_get_level,
-	.set_level         = &nct38xx_ioex_set_level,
+	.init = &nct38xx_ioex_init,
+	.get_level = &nct38xx_ioex_get_level,
+	.set_level = &nct38xx_ioex_set_level,
 	.get_flags_by_mask = &nct38xx_ioex_get_flags,
 	.set_flags_by_mask = &nct38xx_ioex_set_flags_by_mask,
-	.enable_interrupt  = &nct38xx_ioex_enable_interrupt,
+	.enable_interrupt = &nct38xx_ioex_enable_interrupt,
 };
diff --git a/driver/ioexpander/it8300.h b/driver/ioexpander/it8300.h
index 2b47e7f3e1..ce1dfc91a8 100644
--- a/driver/ioexpander/it8300.h
+++ b/driver/ioexpander/it8300.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,96 +11,96 @@
 #include "i2c.h"
 
 /* Gather Interrupt Status Register */
-#define IT8300_GISR		0x0
+#define IT8300_GISR 0x0
 
 /* Interrupt Status Registers */
-#define IT8300_ISR_A		0x6
-#define IT8300_ISR_B		0x7
-#define IT8300_ISR_C		0x28
-#define IT8300_ISR_D		0x2E
-#define IT8300_ISR_E		0x2F
+#define IT8300_ISR_A 0x6
+#define IT8300_ISR_B 0x7
+#define IT8300_ISR_C 0x28
+#define IT8300_ISR_D 0x2E
+#define IT8300_ISR_E 0x2F
 
 /* Port Data Register Groups */
-#define IT8300_PDGR_A		0x1
-#define IT8300_PDGR_B		0x2
-#define IT8300_PDGR_C		0x3
-#define IT8300_PDGR_D		0x4
-#define IT8300_PDGR_E		0x5
+#define IT8300_PDGR_A 0x1
+#define IT8300_PDGR_B 0x2
+#define IT8300_PDGR_C 0x3
+#define IT8300_PDGR_D 0x4
+#define IT8300_PDGR_E 0x5
 
 /* GPIO Port Control n Registers */
-#define IT8300_GPCR_A0		0x10
-#define IT8300_GPCR_A1		0x11
-#define IT8300_GPCR_A2		0x12
-#define IT8300_GPCR_A3		0x13
-#define IT8300_GPCR_A4		0x14
-#define IT8300_GPCR_A5		0x15
-#define IT8300_GPCR_A6		0x16
-#define IT8300_GPCR_A7		0x17
-
-#define IT8300_GPCR_B0		0x18
-#define IT8300_GPCR_B1		0x19
-#define IT8300_GPCR_B2		0x1A
-#define IT8300_GPCR_B3		0x1B
-#define IT8300_GPCR_B4		0x1C
-#define IT8300_GPCR_B5		0x1D
-#define IT8300_GPCR_B6		0x1E
-
-#define IT8300_GPCR_C0		0x20
-#define IT8300_GPCR_C1		0x21
-#define IT8300_GPCR_C2		0x22
-#define IT8300_GPCR_C3		0x23
-#define IT8300_GPCR_C4		0x24
-#define IT8300_GPCR_C5		0x25
-#define IT8300_GPCR_C6		0x26
-
-#define IT8300_GPCR_D0		0x08
-#define IT8300_GPCR_D1		0x09
-#define IT8300_GPCR_D2		0x0A
-#define IT8300_GPCR_D3		0x0B
-#define IT8300_GPCR_D4		0x0C
-#define IT8300_GPCR_D5		0x0D
-
-#define IT8300_GPCR_E0		0x32
-
-#define IT8300_GPCR_E2		0x34
-#define IT8300_GPCR_E3		0x35
-#define IT8300_GPCR_E4		0x36
-#define IT8300_GPCR_E5		0x37
-#define IT8300_GPCR_E6		0x38
-
-#define IT8300_GPCR_GPI_MODE	BIT(7)
-#define IT8300_GPCR_GP0_MODE	BIT(6)
-#define IT8300_GPCR_PULL_UP_EN	BIT(2)
-#define IT8300_GPCR_PULL_DN_EN	BIT(1)
+#define IT8300_GPCR_A0 0x10
+#define IT8300_GPCR_A1 0x11
+#define IT8300_GPCR_A2 0x12
+#define IT8300_GPCR_A3 0x13
+#define IT8300_GPCR_A4 0x14
+#define IT8300_GPCR_A5 0x15
+#define IT8300_GPCR_A6 0x16
+#define IT8300_GPCR_A7 0x17
+
+#define IT8300_GPCR_B0 0x18
+#define IT8300_GPCR_B1 0x19
+#define IT8300_GPCR_B2 0x1A
+#define IT8300_GPCR_B3 0x1B
+#define IT8300_GPCR_B4 0x1C
+#define IT8300_GPCR_B5 0x1D
+#define IT8300_GPCR_B6 0x1E
+
+#define IT8300_GPCR_C0 0x20
+#define IT8300_GPCR_C1 0x21
+#define IT8300_GPCR_C2 0x22
+#define IT8300_GPCR_C3 0x23
+#define IT8300_GPCR_C4 0x24
+#define IT8300_GPCR_C5 0x25
+#define IT8300_GPCR_C6 0x26
+
+#define IT8300_GPCR_D0 0x08
+#define IT8300_GPCR_D1 0x09
+#define IT8300_GPCR_D2 0x0A
+#define IT8300_GPCR_D3 0x0B
+#define IT8300_GPCR_D4 0x0C
+#define IT8300_GPCR_D5 0x0D
+
+#define IT8300_GPCR_E0 0x32
+
+#define IT8300_GPCR_E2 0x34
+#define IT8300_GPCR_E3 0x35
+#define IT8300_GPCR_E4 0x36
+#define IT8300_GPCR_E5 0x37
+#define IT8300_GPCR_E6 0x38
+
+#define IT8300_GPCR_GPI_MODE BIT(7)
+#define IT8300_GPCR_GP0_MODE BIT(6)
+#define IT8300_GPCR_PULL_UP_EN BIT(2)
+#define IT8300_GPCR_PULL_DN_EN BIT(1)
 
 /* EXGPIO Clear Alert */
-#define IT8300_ECA		0x30
+#define IT8300_ECA 0x30
 
 /* EXGPIO Alert Enable */
-#define IT8300_EAE		0x31
+#define IT8300_EAE 0x31
 
 /* Port Data Mirror Registers */
-#define IT8300_PDMRA_A		0x29
-#define IT8300_PDMRA_B		0x2A
-#define IT8300_PDMRA_C		0x2B
-#define IT8300_PDMRA_D		0x2C
-#define IT8300_PDMRA_E		0x2D
+#define IT8300_PDMRA_A 0x29
+#define IT8300_PDMRA_B 0x2A
+#define IT8300_PDMRA_C 0x2B
+#define IT8300_PDMRA_D 0x2C
+#define IT8300_PDMRA_E 0x2D
 
 /* Output Open-Drain Enable Registers */
-#define IT8300_OODER_A		0x39
-#define IT8300_OODER_B		0x3A
-#define IT8300_OODER_C		0x3B
-#define IT8300_OODER_D		0x3C
-#define IT8300_OODER_E		0x3D
+#define IT8300_OODER_A 0x39
+#define IT8300_OODER_B 0x3A
+#define IT8300_OODER_C 0x3B
+#define IT8300_OODER_D 0x3C
+#define IT8300_OODER_E 0x3D
 
 /* IT83200 Port GPIOs */
-#define IT8300_GPX_0		BIT(0)
-#define IT8300_GPX_1		BIT(1)
-#define IT8300_GPX_2		BIT(2)
-#define IT8300_GPX_3		BIT(3)
-#define IT8300_GPX_4		BIT(4)
-#define IT8300_GPX_5		BIT(5)
-#define IT8300_GPX_6		BIT(6)
-#define IT8300_GPX_7		BIT(7)
+#define IT8300_GPX_0 BIT(0)
+#define IT8300_GPX_1 BIT(1)
+#define IT8300_GPX_2 BIT(2)
+#define IT8300_GPX_3 BIT(3)
+#define IT8300_GPX_4 BIT(4)
+#define IT8300_GPX_5 BIT(5)
+#define IT8300_GPX_6 BIT(6)
+#define IT8300_GPX_7 BIT(7)
 
 #endif /* __CROS_EC_IOEXPANDER_IT8300_H */
diff --git a/driver/ioexpander/it8801.c b/driver/ioexpander/it8801.c
index dbf13c4da8..256b4c9654 100644
--- a/driver/ioexpander/it8801.c
+++ b/driver/ioexpander/it8801.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,7 +17,7 @@
 #include "util.h"
 #include "keyboard_backlight.h"
 
-#define CPRINTS(format, args...) cprints(CC_KEYSCAN, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_KEYSCAN, format, ##args)
 
 static int it8801_ioex_set_level(int ioex, int port, int mask, int value);
 static void it8801_ioex_event_handler(void);
@@ -25,14 +25,14 @@ DECLARE_DEFERRED(it8801_ioex_event_handler);
 
 static int it8801_read(int reg, int *data)
 {
-	return i2c_read8(I2C_PORT_KB_DISCRETE,
-		KB_DISCRETE_I2C_ADDR_FLAGS, reg, data);
+	return i2c_read8(I2C_PORT_KB_DISCRETE, KB_DISCRETE_I2C_ADDR_FLAGS, reg,
+			 data);
 }
 
 __maybe_unused static int it8801_write(int reg, int data)
 {
-	return i2c_write8(I2C_PORT_KB_DISCRETE,
-		KB_DISCRETE_I2C_ADDR_FLAGS, reg, data);
+	return i2c_write8(I2C_PORT_KB_DISCRETE, KB_DISCRETE_I2C_ADDR_FLAGS, reg,
+			  data);
 }
 
 struct it8801_vendor_id_t {
@@ -41,8 +41,8 @@ struct it8801_vendor_id_t {
 };
 
 static const struct it8801_vendor_id_t it8801_vendor_id_verify[] = {
-	{ 0x12, IT8801_REG_HBVIDR},
-	{ 0x83, IT8801_REG_LBVIDR},
+	{ 0x12, IT8801_REG_HBVIDR },
+	{ 0x83, IT8801_REG_LBVIDR },
 };
 
 static int it8801_check_vendor_id(void)
@@ -133,10 +133,10 @@ void keyboard_raw_task_start(void)
 	keyboard_raw_enable_interrupt(1);
 }
 
-__overridable const uint8_t it8801_kso_mapping[] = {
-	0, 1, 20, 3, 4, 5, 6, 17, 18, 16, 15, 11, 12,
+__overridable const uint8_t it8801_kso_mapping[] = { 0,	 1,  20, 3,  4,	 5,  6,
+						     17, 18, 16, 15, 11, 12,
 #ifdef CONFIG_KEYBOARD_KEYPAD
-	13, 14
+						     13, 14
 #endif
 };
 BUILD_ASSERT(ARRAY_SIZE(it8801_kso_mapping) == KEYBOARD_COLS_MAX);
@@ -179,11 +179,11 @@ test_mockable void keyboard_raw_drive_column(int col)
 			if (col == IT8801_REG_MASK_SELKSO2) {
 				/* Output high(so selected). */
 				it8801_ioex_set_level(0, 2,
-						IT8801_REG_GPIO23SOV, 1);
+						      IT8801_REG_GPIO23SOV, 1);
 			} else {
 				/* Output low(so not selected). */
 				it8801_ioex_set_level(0, 2,
-						IT8801_REG_GPIO23SOV, 0);
+						      IT8801_REG_GPIO23SOV, 0);
 			}
 		}
 	}
@@ -229,25 +229,25 @@ static int it8801_ioex_read(int ioex, int reg, int *data)
 {
 	struct ioexpander_config_t *ioex_p = &ioex_config[ioex];
 
-	return i2c_read8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags,
-			 reg, data);
+	return i2c_read8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, reg,
+			 data);
 }
 
 static int it8801_ioex_write(int ioex, int reg, int data)
 {
 	struct ioexpander_config_t *ioex_p = &ioex_config[ioex];
 
-	return i2c_write8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags,
-			  reg, data);
+	return i2c_write8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, reg,
+			  data);
 }
 
 static int it8801_ioex_update(int ioex, int reg, int data,
-				enum mask_update_action action)
+			      enum mask_update_action action)
 {
 	struct ioexpander_config_t *ioex_p = &ioex_config[ioex];
 
-	return i2c_update8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags,
-			  reg, data, action);
+	return i2c_update8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, reg,
+			   data, action);
 }
 
 static const int it8801_valid_gpio_group[] = {
@@ -340,15 +340,15 @@ static int it8801_ioex_set_level(int ioex, int port, int mask, int value)
 			it8801_gpio_sov[port] &= ~mask;
 
 		rv = it8801_ioex_write(ioex, IT8801_REG_GPIO_SOVR(port),
-						it8801_gpio_sov[port]);
+				       it8801_gpio_sov[port]);
 	}
 	mutex_unlock(&ioex_mutex);
 
 	return rv;
 }
 
-static int it8801_ioex_get_flags_by_mask(int ioex, int port,
-		int mask, int *flags)
+static int it8801_ioex_get_flags_by_mask(int ioex, int port, int mask,
+					 int *flags)
 {
 	int rv, val;
 
@@ -378,8 +378,8 @@ static int it8801_ioex_get_flags_by_mask(int ioex, int port,
 	return EC_SUCCESS;
 }
 
-static int it8801_ioex_set_flags_by_mask(int ioex, int port,
-		int mask, int flags)
+static int it8801_ioex_set_flags_by_mask(int ioex, int port, int mask,
+					 int flags)
 {
 	int rv, val;
 
@@ -388,13 +388,13 @@ static int it8801_ioex_set_flags_by_mask(int ioex, int port,
 
 	if (flags & ~IT8801_SUPPORT_GPIO_FLAGS) {
 		CPRINTS("Flag 0x%08x is not supported at port %d, mask %d",
-					flags, port, mask);
+			flags, port, mask);
 		return EC_ERROR_INVAL;
 	}
 
 	/* GPIO alternate function switching(GPIO[00, 12:15, 20:23]). */
 	rv = it8801_ioex_write(ioex, IT8801_REG_GPIO_CR(port, mask),
-					IT8801_REG_MASK_GPIOAFS_FUNC1);
+			       IT8801_REG_MASK_GPIOAFS_FUNC1);
 	if (rv)
 		return rv;
 
@@ -418,7 +418,7 @@ static int it8801_ioex_set_flags_by_mask(int ioex, int port,
 			it8801_gpio_sov[port] &= ~mask;
 
 		rv = it8801_ioex_write(ioex, IT8801_REG_GPIO_SOVR(port),
-						it8801_gpio_sov[port]);
+				       it8801_gpio_sov[port]);
 		if (rv)
 			goto unlock_mutex;
 
@@ -451,13 +451,13 @@ static int it8801_ioex_enable_interrupt(int ioex, int port, int mask,
 		return EC_ERROR_INVAL;
 
 	/* Clear pending interrupt */
-	rv = it8801_ioex_update(ioex, IT8801_REG_GPIO_ISR(port),
-				mask, MASK_SET);
+	rv = it8801_ioex_update(ioex, IT8801_REG_GPIO_ISR(port), mask,
+				MASK_SET);
 	if (rv)
 		return rv;
 
-	return it8801_ioex_update(ioex, IT8801_REG_GPIO_IER(port),
-				mask, enable ? MASK_SET : MASK_CLR);
+	return it8801_ioex_update(ioex, IT8801_REG_GPIO_IER(port), mask,
+				  enable ? MASK_SET : MASK_CLR);
 }
 
 #ifdef CONFIG_ZEPHYR
@@ -483,7 +483,7 @@ static void it8801_ioex_irq(int ioex, int port)
 
 			/* Clear pending interrupt */
 			it8801_ioex_update(ioex, IT8801_REG_GPIO_ISR(port),
-					g->mask, MASK_SET);
+					   g->mask, MASK_SET);
 
 			if (!data)
 				break;
@@ -502,7 +502,7 @@ static void it8801_ioex_event_handler(void)
 
 	/* Wake the keyboard scan task if KSI interrupts are triggered */
 	if (IS_ENABLED(CONFIG_KEYBOARD_DISCRETE) &&
-		data & IT8801_REG_MASK_GISR_GKSIIS)
+	    data & IT8801_REG_MASK_GISR_GKSIIS)
 		task_wake(TASK_ID_KEYSCAN);
 
 	/*
@@ -535,14 +535,14 @@ static int it8801_ioex_get_port(int ioex, int port, int *val)
 #endif
 
 const struct ioexpander_drv it8801_ioexpander_drv = {
-	.init              = &it8801_ioex_init,
-	.get_level         = &it8801_ioex_get_level,
-	.set_level         = &it8801_ioex_set_level,
+	.init = &it8801_ioex_init,
+	.get_level = &it8801_ioex_get_level,
+	.set_level = &it8801_ioex_set_level,
 	.get_flags_by_mask = &it8801_ioex_get_flags_by_mask,
 	.set_flags_by_mask = &it8801_ioex_set_flags_by_mask,
-	.enable_interrupt  = &it8801_ioex_enable_interrupt,
+	.enable_interrupt = &it8801_ioex_enable_interrupt,
 #ifdef CONFIG_IO_EXPANDER_SUPPORT_GET_PORT
-	.get_port          = &it8801_ioex_get_port,
+	.get_port = &it8801_ioex_get_port,
 #endif
 };
 
@@ -561,7 +561,7 @@ static void dump_register(int reg)
 		ccprintf("ERR (%d)\n", rv);
 }
 
-static int it8801_dump(int argc, char **argv)
+static int it8801_dump(int argc, const char **argv)
 {
 	dump_register(IT8801_REG_KSIIER);
 	dump_register(IT8801_REG_KSIEER);
@@ -582,13 +582,13 @@ struct it8801_pwm_gpio_map {
 };
 
 const static struct it8801_pwm_gpio_map it8801_pwm_gpio_map[] = {
-	[1] = {.port = 1, .mask = BIT(2), .pushpull_en = BIT(0)},
-	[2] = {.port = 1, .mask = BIT(3), .pushpull_en = BIT(1)},
-	[3] = {.port = 1, .mask = BIT(4), .pushpull_en = BIT(2)},
-	[4] = {.port = 1, .mask = BIT(5), .pushpull_en = BIT(3)},
-	[7] = {.port = 2, .mask = BIT(0), .pushpull_en = BIT(4)},
-	[8] = {.port = 2, .mask = BIT(3), .pushpull_en = BIT(5)},
-	[9] = {.port = 2, .mask = BIT(2), .pushpull_en = BIT(6)},
+	[1] = { .port = 1, .mask = BIT(2), .pushpull_en = BIT(0) },
+	[2] = { .port = 1, .mask = BIT(3), .pushpull_en = BIT(1) },
+	[3] = { .port = 1, .mask = BIT(4), .pushpull_en = BIT(2) },
+	[4] = { .port = 1, .mask = BIT(5), .pushpull_en = BIT(3) },
+	[7] = { .port = 2, .mask = BIT(0), .pushpull_en = BIT(4) },
+	[8] = { .port = 2, .mask = BIT(3), .pushpull_en = BIT(5) },
+	[9] = { .port = 2, .mask = BIT(2), .pushpull_en = BIT(6) },
 };
 
 void it8801_pwm_enable(enum pwm_channel ch, int enabled)
@@ -609,10 +609,10 @@ void it8801_pwm_enable(enum pwm_channel ch, int enabled)
 	 */
 	if (it8801_pwm_channels[ch].index <= 7)
 		it8801_write(IT8801_REG_GPIO_CR(port, mask),
-				0x1 << IT8801_GPIOAFS_SHIFT);
+			     0x1 << IT8801_GPIOAFS_SHIFT);
 	else
 		it8801_write(IT8801_REG_GPIO_CR(port, mask),
-				0x2 << IT8801_GPIOAFS_SHIFT);
+			     0x2 << IT8801_GPIOAFS_SHIFT);
 
 	it8801_read(IT8801_REG_PWMMCR(it8801_pwm_channels[ch].index), &val);
 	val &= (~IT8801_PWMMCR_MCR_MASK);
@@ -628,7 +628,6 @@ void it8801_pwm_enable(enum pwm_channel ch, int enabled)
 	if (enabled)
 		val |= it8801_pwm_gpio_map[index].pushpull_en;
 	it8801_write(IT8801_REG_PWMODDSR, val);
-
 }
 
 int it8801_pwm_get_enabled(enum pwm_channel ch)
@@ -706,4 +705,4 @@ const struct kblight_drv kblight_it8801 = {
 	.get_enabled = it8801_kblight_get_enabled,
 };
 #endif
-#endif  /* CONFIG_IO_EXPANDER_IT8801_PWM */
+#endif /* CONFIG_IO_EXPANDER_IT8801_PWM */
diff --git a/driver/ioexpander/it8801.h b/driver/ioexpander/it8801.h
index 05a17acf78..605c88789b 100644
--- a/driver/ioexpander/it8801.h
+++ b/driver/ioexpander/it8801.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -14,79 +14,81 @@
 #define IT8801_I2C_ADDR2 0x39
 
 /* Keyboard Matrix Scan control (KBS) */
-#define IT8801_REG_KSOMCR               0x40
-#define IT8801_REG_MASK_KSOSDIC         BIT(7)
-#define IT8801_REG_MASK_KSE             BIT(6)
-#define IT8801_REG_MASK_AKSOSC          BIT(5)
-#define IT8801_REG_KSIDR                0x41
-#define IT8801_REG_KSIEER               0x42
-#define IT8801_REG_KSIIER               0x43
-#define IT8801_REG_SMBCR                0xfa
-#define IT8801_REG_MASK_ARE             BIT(4)
-#define IT8801_REG_GIECR                0xfb
-#define IT8801_REG_MASK_GKSIIE          BIT(3)
-#define IT8801_REG_GPIO10               0x12
-#define IT8801_REG_GPIO00_KSO19         0x0a
-#define IT8801_REG_GPIO01_KSO18         0x0b
-#define IT8801_REG_GPIO22_KSO21         0x1c
-#define IT8801_REG_GPIO23_KSO20         0x1d
-#define IT8801_REG_MASK_GPIOAFS_PULLUP  BIT(7)
-#define IT8801_REG_MASK_GPIOAFS_FUNC2   BIT(6)
-#define IT8801_REG_MASK_GPIODIR         BIT(5)
-#define IT8801_REG_MASK_GPIOPUE         BIT(0)
-#define IT8801_REG_GPIO23SOV            BIT(3)
-#define IT8801_REG_MASK_SELKSO2         0x02
-#define IT8801_REG_GISR                 0xF9
-#define IT8801_REG_MASK_GISR_GKSIIS     BIT(6)
-#define IT8801_REG_MASK_GISR_GGPIOG2IS  BIT(2)
-#define IT8801_REG_MASK_GISR_GGPIOG1IS  BIT(1)
-#define IT8801_REG_MASK_GISR_GGPIOG0IS  BIT(0)
-#define IT8801_REG_MASK_GISR_GGPIOGXIS  (IT8801_REG_MASK_GISR_GGPIOG2IS | \
-		IT8801_REG_MASK_GISR_GGPIOG1IS | IT8801_REG_MASK_GISR_GGPIOG0IS)
-#define IT8801_REG_LBVIDR               0xFE
-#define IT8801_REG_HBVIDR               0xFF
-#define IT8801_KSO_COUNT                18
+#define IT8801_REG_KSOMCR 0x40
+#define IT8801_REG_MASK_KSOSDIC BIT(7)
+#define IT8801_REG_MASK_KSE BIT(6)
+#define IT8801_REG_MASK_AKSOSC BIT(5)
+#define IT8801_REG_KSIDR 0x41
+#define IT8801_REG_KSIEER 0x42
+#define IT8801_REG_KSIIER 0x43
+#define IT8801_REG_SMBCR 0xfa
+#define IT8801_REG_MASK_ARE BIT(4)
+#define IT8801_REG_GIECR 0xfb
+#define IT8801_REG_MASK_GKSIIE BIT(3)
+#define IT8801_REG_GPIO10 0x12
+#define IT8801_REG_GPIO00_KSO19 0x0a
+#define IT8801_REG_GPIO01_KSO18 0x0b
+#define IT8801_REG_GPIO22_KSO21 0x1c
+#define IT8801_REG_GPIO23_KSO20 0x1d
+#define IT8801_REG_MASK_GPIOAFS_PULLUP BIT(7)
+#define IT8801_REG_MASK_GPIOAFS_FUNC2 BIT(6)
+#define IT8801_REG_MASK_GPIODIR BIT(5)
+#define IT8801_REG_MASK_GPIOPUE BIT(0)
+#define IT8801_REG_GPIO23SOV BIT(3)
+#define IT8801_REG_MASK_SELKSO2 0x02
+#define IT8801_REG_GISR 0xF9
+#define IT8801_REG_MASK_GISR_GKSIIS BIT(6)
+#define IT8801_REG_MASK_GISR_GGPIOG2IS BIT(2)
+#define IT8801_REG_MASK_GISR_GGPIOG1IS BIT(1)
+#define IT8801_REG_MASK_GISR_GGPIOG0IS BIT(0)
+#define IT8801_REG_MASK_GISR_GGPIOGXIS                                     \
+	(IT8801_REG_MASK_GISR_GGPIOG2IS | IT8801_REG_MASK_GISR_GGPIOG1IS | \
+	 IT8801_REG_MASK_GISR_GGPIOG0IS)
+#define IT8801_REG_LBVIDR 0xFE
+#define IT8801_REG_HBVIDR 0xFF
+#define IT8801_KSO_COUNT 18
 
 /* General Purpose I/O Port (GPIO) */
-#define IT8801_SUPPORT_GPIO_FLAGS (GPIO_OPEN_DRAIN | GPIO_INPUT | \
-		GPIO_OUTPUT | GPIO_LOW | GPIO_HIGH | GPIO_INT_ANY)
+#define IT8801_SUPPORT_GPIO_FLAGS                                            \
+	(GPIO_OPEN_DRAIN | GPIO_INPUT | GPIO_OUTPUT | GPIO_LOW | GPIO_HIGH | \
+	 GPIO_INT_ANY)
 
-#define IT8801_REG_MASK_GPIOAFS_FUNC1   (0x00 << 7)
+#define IT8801_REG_MASK_GPIOAFS_FUNC1 (0x00 << 7)
 
 /* IT8801 only supports GPIO 0/1/2 */
-#define IT8801_VALID_GPIO_G0_MASK       0xD9
-#define IT8801_VALID_GPIO_G1_MASK       0x3F
-#define IT8801_VALID_GPIO_G2_MASK       0x0F
+#define IT8801_VALID_GPIO_G0_MASK 0xD9
+#define IT8801_VALID_GPIO_G1_MASK 0x3F
+#define IT8801_VALID_GPIO_G2_MASK 0x0F
 
 extern __override_proto const uint8_t it8801_kso_mapping[];
 extern const struct ioexpander_drv it8801_ioexpander_drv;
 
 /* GPIO Register map */
 /* Input pin status register */
-#define IT8801_REG_GPIO_IPSR(port)      (0x00 + (port))
+#define IT8801_REG_GPIO_IPSR(port) (0x00 + (port))
 /* Set output value register */
-#define IT8801_REG_GPIO_SOVR(port)      (0x05 + (port))
+#define IT8801_REG_GPIO_SOVR(port) (0x05 + (port))
 /* Control register */
-#define IT8801_REG_GPIO_CR(port, mask)  \
-	(0x0A + (port) * 8 + GPIO_MASK_TO_NUM(mask))
+#define IT8801_REG_GPIO_CR(port, mask) \
+	(0x0A + (port)*8 + GPIO_MASK_TO_NUM(mask))
 /* Interrupt status register */
-#define IT8801_REG_GPIO_ISR(port)       (0x32 + (port))
+#define IT8801_REG_GPIO_ISR(port) (0x32 + (port))
 /* Interrupt enable register */
-#define IT8801_REG_GPIO_IER(port)       (0x37 + (port))
+#define IT8801_REG_GPIO_IER(port) (0x37 + (port))
 
 /* Control register values */
-#define IT8801_GPIOAFS_SHIFT            6  /* bit 6~7 */
+#define IT8801_GPIOAFS_SHIFT 6 /* bit 6~7 */
 
-#define IT8801_GPIODIR                  BIT(5)  /* direction, output=1 */
+#define IT8801_GPIODIR BIT(5) /* direction, output=1 */
 /* input pin */
-#define IT8801_GPIOIOT_INT_RISING       BIT(3)
-#define IT8801_GPIOIOT_INT_FALLING      BIT(4)
+#define IT8801_GPIOIOT_INT_RISING BIT(3)
+#define IT8801_GPIOIOT_INT_FALLING BIT(4)
 
-#define IT8801_GPIODIR                  BIT(5)
-#define IT8801_GPIOIOT                  BIT(4)
-#define IT8801_GPIOPOL                  BIT(2)  /* polarity */
-#define IT8801_GPIOPDE                  BIT(1)  /* pull-down enable */
-#define IT8801_GPIOPUE                  BIT(0)  /* pull-up enable */
+#define IT8801_GPIODIR BIT(5)
+#define IT8801_GPIOIOT BIT(4)
+#define IT8801_GPIOPOL BIT(2) /* polarity */
+#define IT8801_GPIOPDE BIT(1) /* pull-down enable */
+#define IT8801_GPIOPUE BIT(0) /* pull-up enable */
 
 /* ISR for IT8801's SMB_INT# */
 void io_expander_it8801_interrupt(enum gpio_signal signal);
@@ -109,18 +111,18 @@ uint16_t it8801_pwm_get_raw_duty(enum pwm_channel ch);
 void it8801_pwm_set_duty(enum pwm_channel ch, int percent);
 int it8801_pwm_get_duty(enum pwm_channel ch);
 
-#define IT8801_REG_PWMODDSR                            0x5F
-#define IT8801_REG_PWMMCR(n)            (0x60 + ((n) - 1) * 8)
-#define IT8801_REG_PWMDCR(n)            (0x64 + ((n) - 1) * 8)
-#define IT8801_REG_PWMPRSL(n)           (0x66 + ((n) - 1) * 8)
-#define IT8801_REG_PWMPRSM(n)           (0x67 + ((n) - 1) * 8)
+#define IT8801_REG_PWMODDSR 0x5F
+#define IT8801_REG_PWMMCR(n) (0x60 + ((n)-1) * 8)
+#define IT8801_REG_PWMDCR(n) (0x64 + ((n)-1) * 8)
+#define IT8801_REG_PWMPRSL(n) (0x66 + ((n)-1) * 8)
+#define IT8801_REG_PWMPRSM(n) (0x67 + ((n)-1) * 8)
 
-#define IT8801_PWMMCR_MCR_MASK          0x3
-#define IT8801_PWMMCR_MCR_OFF           0
-#define IT8801_PWMMCR_MCR_BLINKING      1
-#define IT8801_PWMMCR_MCR_BREATHING     2
-#define IT8801_PWMMCR_MCR_ON            3
+#define IT8801_PWMMCR_MCR_MASK 0x3
+#define IT8801_PWMMCR_MCR_OFF 0
+#define IT8801_PWMMCR_MCR_BLINKING 1
+#define IT8801_PWMMCR_MCR_BREATHING 2
+#define IT8801_PWMMCR_MCR_ON 3
 
-#endif  /* CONFIG_IO_EXPANDER_IT8801_PWM */
+#endif /* CONFIG_IO_EXPANDER_IT8801_PWM */
 
 #endif /* __CROS_EC_KBEXPANDER_IT8801_H */
diff --git a/driver/ioexpander/pca9534.c b/driver/ioexpander/pca9534.c
index d56eb864cb..cd7fc0acf5 100644
--- a/driver/ioexpander/pca9534.c
+++ b/driver/ioexpander/pca9534.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,8 +8,8 @@
 #include "i2c.h"
 #include "pca9534.h"
 
-static int pca9534_pin_read(const int port, const uint16_t addr_flags,
-			    int reg, int pin, int *val)
+static int pca9534_pin_read(const int port, const uint16_t addr_flags, int reg,
+			    int pin, int *val)
 {
 	int ret;
 	ret = i2c_read8(port, addr_flags, reg, val);
@@ -17,8 +17,8 @@ static int pca9534_pin_read(const int port, const uint16_t addr_flags,
 	return ret;
 }
 
-static int pca9534_pin_write(const int port, const uint16_t addr_flags,
-			     int reg, int pin, int val)
+static int pca9534_pin_write(const int port, const uint16_t addr_flags, int reg,
+			     int pin, int val)
 {
 	int ret, v;
 	ret = i2c_read8(port, addr_flags, reg, &v);
@@ -30,23 +30,23 @@ static int pca9534_pin_write(const int port, const uint16_t addr_flags,
 	return i2c_write8(port, addr_flags, reg, v);
 }
 
-int pca9534_get_level(const int port, const uint16_t addr_flags,
-		      int pin, int *level)
+int pca9534_get_level(const int port, const uint16_t addr_flags, int pin,
+		      int *level)
 {
-	return pca9534_pin_read(port, addr_flags,
-				PCA9534_REG_INPUT, pin, level);
+	return pca9534_pin_read(port, addr_flags, PCA9534_REG_INPUT, pin,
+				level);
 }
 
-int pca9534_set_level(const int port, const uint16_t addr_flags,
-		      int pin, int level)
+int pca9534_set_level(const int port, const uint16_t addr_flags, int pin,
+		      int level)
 {
-	return pca9534_pin_write(port, addr_flags,
-				 PCA9534_REG_OUTPUT, pin, level);
+	return pca9534_pin_write(port, addr_flags, PCA9534_REG_OUTPUT, pin,
+				 level);
 }
 
-int pca9534_config_pin(const int port, const uint16_t addr_flags,
-		       int pin, int is_input)
+int pca9534_config_pin(const int port, const uint16_t addr_flags, int pin,
+		       int is_input)
 {
-	return pca9534_pin_write(port, addr_flags,
-				 PCA9534_REG_CONFIG, pin, is_input);
+	return pca9534_pin_write(port, addr_flags, PCA9534_REG_CONFIG, pin,
+				 is_input);
 }
diff --git a/driver/ioexpander/pca9534.h b/driver/ioexpander/pca9534.h
index 0fec577576..67e48191e1 100644
--- a/driver/ioexpander/pca9534.h
+++ b/driver/ioexpander/pca9534.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,12 +8,12 @@
 #ifndef __CROS_EC_IOEXPANDER_PCA9534_H
 #define __CROS_EC_IOEXPANDER_PCA9534_H
 
-#define PCA9534_REG_INPUT  0x0
+#define PCA9534_REG_INPUT 0x0
 #define PCA9534_REG_OUTPUT 0x1
 #define PCA9534_REG_CONFIG 0x3
 
 #define PCA9534_OUTPUT 0
-#define PCA9534_INPUT  1
+#define PCA9534_INPUT 1
 
 /*
  * Get input level. Note that this reflects the actual level on the
@@ -26,8 +26,8 @@
  *
  * @return EC_SUCCESS, or EC_ERROR_* on error.
  */
-int pca9534_get_level(const int port, const uint16_t addr_flags,
-		      int pin, int *level);
+int pca9534_get_level(const int port, const uint16_t addr_flags, int pin,
+		      int *level);
 
 /*
  * Set output level. This function has no effect if the pin is
@@ -40,8 +40,8 @@ int pca9534_get_level(const int port, const uint16_t addr_flags,
  *
  * @return EC_SUCCESS, or EC_ERROR_* on error.
  */
-int pca9534_set_level(const int port, const uint16_t addr_flags,
-		      int pin, int level);
+int pca9534_set_level(const int port, const uint16_t addr_flags, int pin,
+		      int level);
 
 /*
  * Config a pin as input or output.
@@ -53,7 +53,7 @@ int pca9534_set_level(const int port, const uint16_t addr_flags,
  *
  * @return EC_SUCCESS, or EC_ERROR_* on error.
  */
-int pca9534_config_pin(const int port, const uint16_t addr_flags,
-		       int pin, int is_input);
+int pca9534_config_pin(const int port, const uint16_t addr_flags, int pin,
+		       int is_input);
 
-#endif  /* __CROS_EC_IOEXPANDER_PCA9534_H */
+#endif /* __CROS_EC_IOEXPANDER_PCA9534_H */
diff --git a/driver/ioexpander/pca9555.h b/driver/ioexpander/pca9555.h
index 273f898821..ea29c91656 100644
--- a/driver/ioexpander/pca9555.h
+++ b/driver/ioexpander/pca9555.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,33 +10,31 @@
 
 #include "i2c.h"
 
-#define PCA9555_CMD_INPUT_PORT_0		0
-#define PCA9555_CMD_INPUT_PORT_1		1
-#define PCA9555_CMD_OUTPUT_PORT_0		2
-#define PCA9555_CMD_OUTPUT_PORT_1		3
-#define PCA9555_CMD_POLARITY_INVERSION_PORT_0	4
-#define PCA9555_CMD_POLARITY_INVERSION_PORT_1	5
-#define PCA9555_CMD_CONFIGURATION_PORT_0	6
-#define PCA9555_CMD_CONFIGURATION_PORT_1	7
+#define PCA9555_CMD_INPUT_PORT_0 0
+#define PCA9555_CMD_INPUT_PORT_1 1
+#define PCA9555_CMD_OUTPUT_PORT_0 2
+#define PCA9555_CMD_OUTPUT_PORT_1 3
+#define PCA9555_CMD_POLARITY_INVERSION_PORT_0 4
+#define PCA9555_CMD_POLARITY_INVERSION_PORT_1 5
+#define PCA9555_CMD_CONFIGURATION_PORT_0 6
+#define PCA9555_CMD_CONFIGURATION_PORT_1 7
 
-#define PCA9555_IO_0	BIT(0)
-#define PCA9555_IO_1	BIT(1)
-#define PCA9555_IO_2	BIT(2)
-#define PCA9555_IO_3	BIT(3)
-#define PCA9555_IO_4	BIT(4)
-#define PCA9555_IO_5	BIT(5)
-#define PCA9555_IO_6	BIT(6)
-#define PCA9555_IO_7	BIT(7)
+#define PCA9555_IO_0 BIT(0)
+#define PCA9555_IO_1 BIT(1)
+#define PCA9555_IO_2 BIT(2)
+#define PCA9555_IO_3 BIT(3)
+#define PCA9555_IO_4 BIT(4)
+#define PCA9555_IO_5 BIT(5)
+#define PCA9555_IO_6 BIT(6)
+#define PCA9555_IO_7 BIT(7)
 
-static inline int pca9555_read(const int port,
-			       const uint16_t i2c_addr_flags,
+static inline int pca9555_read(const int port, const uint16_t i2c_addr_flags,
 			       int reg, int *data_ptr)
 {
 	return i2c_read8(port, i2c_addr_flags, reg, data_ptr);
 }
 
-static inline int pca9555_write(const int port,
-				const uint16_t i2c_addr_flags,
+static inline int pca9555_write(const int port, const uint16_t i2c_addr_flags,
 				int reg, int data)
 {
 	return i2c_write8(port, i2c_addr_flags, reg, data);
diff --git a/driver/ioexpander/pca9675.c b/driver/ioexpander/pca9675.c
index f9e83b48c5..74faab8722 100644
--- a/driver/ioexpander/pca9675.c
+++ b/driver/ioexpander/pca9675.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -21,8 +21,8 @@ static struct pca9675_ioexpander pca9675_iox[CONFIG_IO_EXPANDER_PORT_COUNT];
 static int pca9675_read16(int ioex, uint16_t *data)
 {
 	return i2c_xfer(ioex_config[ioex].i2c_host_port,
-			ioex_config[ioex].i2c_addr_flags,
-			NULL, 0, (uint8_t *)data, 2);
+			ioex_config[ioex].i2c_addr_flags, NULL, 0,
+			(uint8_t *)data, 2);
 }
 
 static int pca9675_write16(int ioex, uint16_t data)
@@ -35,22 +35,21 @@ static int pca9675_write16(int ioex, uint16_t data)
 	data |= pca9675_iox[ioex].io_direction;
 
 	return i2c_xfer(ioex_config[ioex].i2c_host_port,
-			ioex_config[ioex].i2c_addr_flags,
-			(uint8_t *)&data, 2, NULL, 0);
+			ioex_config[ioex].i2c_addr_flags, (uint8_t *)&data, 2,
+			NULL, 0);
 }
 
 static int pca9675_reset(int ioex)
 {
 	uint8_t reset = PCA9675_RESET_SEQ_DATA;
 
-	return i2c_xfer(ioex_config[ioex].i2c_host_port,
-			0, &reset, 1, NULL, 0);
+	return i2c_xfer(ioex_config[ioex].i2c_host_port, 0, &reset, 1, NULL, 0);
 }
 
 static int pca9675_get_flags_by_mask(int ioex, int port, int mask, int *flags)
 {
-	*flags = mask & pca9675_iox[ioex].io_direction ?
-				GPIO_INPUT : GPIO_OUTPUT;
+	*flags = mask & pca9675_iox[ioex].io_direction ? GPIO_INPUT :
+							 GPIO_OUTPUT;
 
 	return EC_SUCCESS;
 }
@@ -129,13 +128,13 @@ static int pca9675_get_port(int ioex, int port, int *val)
 #endif
 
 const struct ioexpander_drv pca9675_ioexpander_drv = {
-	.init			= &pca9675_init,
-	.get_level		= &pca9675_get_level,
-	.set_level		= &pca9675_set_level,
-	.get_flags_by_mask	= &pca9675_get_flags_by_mask,
-	.set_flags_by_mask	= &pca9675_set_flags_by_mask,
-	.enable_interrupt	= &pca9675_enable_interrupt,
+	.init = &pca9675_init,
+	.get_level = &pca9675_get_level,
+	.set_level = &pca9675_set_level,
+	.get_flags_by_mask = &pca9675_get_flags_by_mask,
+	.set_flags_by_mask = &pca9675_set_flags_by_mask,
+	.enable_interrupt = &pca9675_enable_interrupt,
 #ifdef CONFIG_IO_EXPANDER_SUPPORT_GET_PORT
-	.get_port		= &pca9675_get_port,
+	.get_port = &pca9675_get_port,
 #endif
 };
diff --git a/driver/ioexpander/pca9675.h b/driver/ioexpander/pca9675.h
index 59f36918a4..6b71ffa023 100644
--- a/driver/ioexpander/pca9675.h
+++ b/driver/ioexpander/pca9675.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/driver/ioexpander/pcal6408.c b/driver/ioexpander/pcal6408.c
index 46de96b595..1b746bffc3 100644
--- a/driver/ioexpander/pcal6408.c
+++ b/driver/ioexpander/pcal6408.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -12,8 +12,8 @@
 #include "ioexpander.h"
 #include "pcal6408.h"
 
-#define CPRINTF(format, args...) cprintf(CC_GPIO, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_GPIO, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args)
 
 #ifdef CONFIG_IO_EXPANDER_SUPPORT_GET_PORT
 #error "This driver doesn't support get_port function"
@@ -24,17 +24,16 @@
  * we don't have to read it via i2c transaction every time.
  * Default value of interrupt mask register is 0xff.
  */
-uint8_t pcal6408_int_mask[] = {
-	[0 ... (CONFIG_IO_EXPANDER_PORT_COUNT - 1)] =  0xff };
-
+uint8_t pcal6408_int_mask[] = { [0 ...(CONFIG_IO_EXPANDER_PORT_COUNT - 1)] =
+					0xff };
 
 static int pcal6408_read(int ioex, int reg, int *data)
 {
 	int rv;
 	struct ioexpander_config_t *ioex_p = &ioex_config[ioex];
 
-	rv = i2c_read8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags,
-			reg, data);
+	rv = i2c_read8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, reg,
+		       data);
 
 	return rv;
 }
@@ -44,8 +43,8 @@ static int pcal6408_write(int ioex, int reg, int data)
 	int rv;
 	struct ioexpander_config_t *ioex_p = &ioex_config[ioex];
 
-	rv = i2c_write8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags,
-			reg, data);
+	rv = i2c_write8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, reg,
+			data);
 
 	return rv;
 }
@@ -56,8 +55,7 @@ static int pcal6408_ioex_check_is_valid(int port, int mask)
 		return EC_ERROR_INVAL;
 
 	if (mask & ~PCAL6408_VALID_GPIO_MASK) {
-		CPRINTF("GPIO%02d is not support in PCAL6408\n",
-						__fls(mask));
+		CPRINTF("GPIO%02d is not support in PCAL6408\n", __fls(mask));
 		return EC_ERROR_INVAL;
 	}
 
@@ -110,7 +108,7 @@ static int pcal6408_ioex_set_level(int ioex, int port, int mask, int value)
 }
 
 static int pcal6408_ioex_get_flags_by_mask(int ioex, int port, int mask,
-					int *flags)
+					   int *flags)
 {
 	int rv, val;
 
@@ -171,7 +169,7 @@ static int pcal6408_ioex_get_flags_by_mask(int ioex, int port, int mask,
 }
 
 static int pcal6408_ioex_set_flags_by_mask(int ioex, int port, int mask,
-					int flags)
+					   int flags)
 {
 	int rv, val;
 
@@ -180,14 +178,13 @@ static int pcal6408_ioex_set_flags_by_mask(int ioex, int port, int mask,
 		return rv;
 
 	if (((flags & GPIO_INT_BOTH) == GPIO_INT_RISING) ||
-		((flags & GPIO_INT_BOTH) == GPIO_INT_FALLING)) {
+	    ((flags & GPIO_INT_BOTH) == GPIO_INT_FALLING)) {
 		CPRINTF("PCAL6408 only support GPIO_INT_BOTH.\n");
 		return EC_ERROR_INVAL;
 	}
 
-
 	if ((flags & (GPIO_INT_F_RISING | GPIO_INT_F_FALLING)) &&
-		!(flags & GPIO_INPUT)) {
+	    !(flags & GPIO_INPUT)) {
 		CPRINTF("Interrupt pin must be GPIO_INPUT.\n");
 		return EC_ERROR_INVAL;
 	}
@@ -269,7 +266,7 @@ static int pcal6408_ioex_set_flags_by_mask(int ioex, int port, int mask,
 }
 
 static int pcal6408_ioex_enable_interrupt(int ioex, int port, int mask,
-					int enable)
+					  int enable)
 {
 	int rv, val;
 
@@ -302,7 +299,7 @@ static int pcal6408_ioex_enable_interrupt(int ioex, int port, int mask,
 		pcal6408_int_mask[ioex] |= mask;
 
 	rv = pcal6408_write(ioex, PCAL6408_REG_INT_MASK,
-			pcal6408_int_mask[ioex]);
+			    pcal6408_int_mask[ioex]);
 
 	return rv;
 }
@@ -321,7 +318,7 @@ int pcal6408_ioex_event_handler(int ioex)
 	 * read status register will not.
 	 */
 	rv = i2c_read8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags,
-				PCAL6408_REG_INT_STATUS, &int_status);
+		       PCAL6408_REG_INT_STATUS, &int_status);
 	if (rv != EC_SUCCESS)
 		return rv;
 
@@ -335,9 +332,7 @@ int pcal6408_ioex_event_handler(int ioex)
 		return EC_SUCCESS;
 
 	for (i = 0, g = ioex_list; i < ioex_ih_count; i++, g++) {
-
-		if (ioex == g->ioex && 0 == g->port &&
-					(int_status & g->mask)) {
+		if (ioex == g->ioex && 0 == g->port && (int_status & g->mask)) {
 			ioex_irq_handlers[i](i + IOEX_SIGNAL_START);
 			int_status &= ~g->mask;
 			if (!int_status)
@@ -349,10 +344,10 @@ int pcal6408_ioex_event_handler(int ioex)
 }
 
 const struct ioexpander_drv pcal6408_ioexpander_drv = {
-	.init			= &pcal6408_ioex_init,
-	.get_level		= &pcal6408_ioex_get_level,
-	.set_level		= &pcal6408_ioex_set_level,
-	.get_flags_by_mask	= &pcal6408_ioex_get_flags_by_mask,
-	.set_flags_by_mask	= &pcal6408_ioex_set_flags_by_mask,
-	.enable_interrupt	= &pcal6408_ioex_enable_interrupt,
+	.init = &pcal6408_ioex_init,
+	.get_level = &pcal6408_ioex_get_level,
+	.set_level = &pcal6408_ioex_set_level,
+	.get_flags_by_mask = &pcal6408_ioex_get_flags_by_mask,
+	.set_flags_by_mask = &pcal6408_ioex_set_flags_by_mask,
+	.enable_interrupt = &pcal6408_ioex_enable_interrupt,
 };
diff --git a/driver/ioexpander/pcal6408.h b/driver/ioexpander/pcal6408.h
index fc9969aab1..3bedf5bdc4 100644
--- a/driver/ioexpander/pcal6408.h
+++ b/driver/ioexpander/pcal6408.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,28 +8,28 @@
 #ifndef __CROS_EC_IOEXPANDER_PCAL6408_H
 #define __CROS_EC_IOEXPANDER_PCAL6408_H
 
-#define PCAL6408_I2C_ADDR0		0x20
-#define PCAL6408_I2C_ADDR1		0x21
+#define PCAL6408_I2C_ADDR0 0x20
+#define PCAL6408_I2C_ADDR1 0x21
 
-#define PCAL6408_REG_INPUT		0x00
-#define PCAL6408_REG_OUTPUT		0x01
-#define PCAL6408_REG_POLARITY_INVERSION	0x02
-#define PCAL6408_REG_CONFIG		0x03
-#define PCAL6408_REG_OUT_STRENGTH0	0x40
-#define PCAL6408_REG_OUT_STRENGTH1	0x41
-#define PCAL6408_REG_INPUT_LATCH	0x42
-#define PCAL6408_REG_PULL_ENABLE	0x43
-#define PCAL6408_REG_PULL_UP_DOWN	0x44
-#define PCAL6408_REG_INT_MASK		0x45
-#define PCAL6408_REG_INT_STATUS		0x46
-#define PCAL6408_REG_OUT_CONFIG		0x4f
+#define PCAL6408_REG_INPUT 0x00
+#define PCAL6408_REG_OUTPUT 0x01
+#define PCAL6408_REG_POLARITY_INVERSION 0x02
+#define PCAL6408_REG_CONFIG 0x03
+#define PCAL6408_REG_OUT_STRENGTH0 0x40
+#define PCAL6408_REG_OUT_STRENGTH1 0x41
+#define PCAL6408_REG_INPUT_LATCH 0x42
+#define PCAL6408_REG_PULL_ENABLE 0x43
+#define PCAL6408_REG_PULL_UP_DOWN 0x44
+#define PCAL6408_REG_INT_MASK 0x45
+#define PCAL6408_REG_INT_STATUS 0x46
+#define PCAL6408_REG_OUT_CONFIG 0x4f
 
-#define PCAL6408_VALID_GPIO_MASK	0xff
+#define PCAL6408_VALID_GPIO_MASK 0xff
 
-#define PCAL6408_OUTPUT			0
-#define PCAL6408_INPUT			1
+#define PCAL6408_OUTPUT 0
+#define PCAL6408_INPUT 1
 
-#define PCAL6408_OUT_CONFIG_OPEN_DRAIN	0x01
+#define PCAL6408_OUT_CONFIG_OPEN_DRAIN 0x01
 
 /*
  * Check which IO's interrupt event is triggered. If any, call its
@@ -39,4 +39,4 @@ int pcal6408_ioex_event_handler(int ioex);
 
 extern const struct ioexpander_drv pcal6408_ioexpander_drv;
 
-#endif  /* __CROS_EC_IOEXPANDER_PCAL6408_H */
+#endif /* __CROS_EC_IOEXPANDER_PCAL6408_H */
diff --git a/driver/ioexpander/tca64xxa.c b/driver/ioexpander/tca64xxa.c
index b44dd7a686..b1b0d2dd09 100644
--- a/driver/ioexpander/tca64xxa.c
+++ b/driver/ioexpander/tca64xxa.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,32 +19,33 @@
  * must multiply them by 4. Flags value contains information which version
  * of chip is used.
  */
-#define TCA64XXA_PORT_ID(port, reg, flags) \
-	((((flags) & TCA64XXA_FLAG_VER_MASK) \
-	>> TCA64XXA_FLAG_VER_OFFSET) * (reg) + (port))
+#define TCA64XXA_PORT_ID(port, reg, flags)                                \
+	((((flags)&TCA64XXA_FLAG_VER_MASK) >> TCA64XXA_FLAG_VER_OFFSET) * \
+		 (reg) +                                                  \
+	 (port))
 
 static int tca64xxa_write_byte(int ioex, int port, int reg, uint8_t val)
 {
 	const struct ioexpander_config_t *ioex_p = &ioex_config[ioex];
-	const int reg_addr = TCA64XXA_PORT_ID(port, reg,
-		(ioex_p->flags & IOEX_FLAGS_TCA64XXA_FLAG_VER_TCA6416A) ? 2:4);
+	const int reg_addr = TCA64XXA_PORT_ID(
+		port, reg,
+		(ioex_p->flags & IOEX_FLAGS_TCA64XXA_FLAG_VER_TCA6416A) ? 2 :
+									  4);
 
-	return i2c_write8(ioex_p->i2c_host_port,
-			  ioex_p->i2c_addr_flags,
-			  reg_addr,
-			  val);
+	return i2c_write8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags,
+			  reg_addr, val);
 }
 
 static int tca64xxa_read_byte(int ioex, int port, int reg, int *val)
 {
 	const struct ioexpander_config_t *ioex_p = &ioex_config[ioex];
-	const int reg_addr = TCA64XXA_PORT_ID(port, reg,
-		(ioex_p->flags & IOEX_FLAGS_TCA64XXA_FLAG_VER_TCA6416A) ? 2:4);
+	const int reg_addr = TCA64XXA_PORT_ID(
+		port, reg,
+		(ioex_p->flags & IOEX_FLAGS_TCA64XXA_FLAG_VER_TCA6416A) ? 2 :
+									  4);
 
-	return i2c_read8(ioex_p->i2c_host_port,
-			 ioex_p->i2c_addr_flags,
-			 reg_addr,
-			 val);
+	return i2c_read8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags,
+			 reg_addr, val);
 }
 
 /* Restore default values in registers */
@@ -59,23 +60,17 @@ static int tca64xxa_reset(int ioex, int portsCount)
 	 * This loop sets default values (from specification) to all registers.
 	 */
 	for (port = 0; port < portsCount; port++) {
-		ret = tca64xxa_write_byte(ioex,
-					  port,
-					  TCA64XXA_REG_OUTPUT,
+		ret = tca64xxa_write_byte(ioex, port, TCA64XXA_REG_OUTPUT,
 					  TCA64XXA_DEFAULT_OUTPUT);
 		if (ret)
 			return ret;
 
-		ret = tca64xxa_write_byte(ioex,
-					  port,
-					  TCA64XXA_REG_POLARITY_INV,
+		ret = tca64xxa_write_byte(ioex, port, TCA64XXA_REG_POLARITY_INV,
 					  TCA64XXA_DEFAULT_POLARITY_INV);
 		if (ret)
 			return ret;
 
-		ret = tca64xxa_write_byte(ioex,
-					  port,
-					  TCA64XXA_REG_CONF,
+		ret = tca64xxa_write_byte(ioex, port, TCA64XXA_REG_CONF,
 					  TCA64XXA_DEFAULT_CONF);
 		if (ret)
 			return ret;
@@ -150,7 +145,7 @@ static int tca64xxa_get_flags_by_mask(int ioex, int port, int mask, int *flags)
 		*flags |= GPIO_OUTPUT;
 
 		ret = tca64xxa_read_byte(ioex, port, TCA64XXA_REG_OUTPUT, &v);
-		if(ret)
+		if (ret)
 			return ret;
 
 		if (v & mask)
@@ -188,7 +183,7 @@ static int tca64xxa_set_flags_by_mask(int ioex, int port, int mask, int flags)
 
 	/* Configuration */
 	ret = tca64xxa_read_byte(ioex, port, TCA64XXA_REG_CONF, &v);
-	if(ret)
+	if (ret)
 		return ret;
 
 	if (flags & GPIO_INPUT)
@@ -217,13 +212,13 @@ static int tca64xxa_get_port(int ioex, int port, int *val)
 
 /* Driver structure */
 const struct ioexpander_drv tca64xxa_ioexpander_drv = {
-	.init 			= tca64xxa_init,
-	.get_level 		= tca64xxa_get_level,
-	.set_level 		= tca64xxa_set_level,
-	.get_flags_by_mask 	= tca64xxa_get_flags_by_mask,
-	.set_flags_by_mask 	= tca64xxa_set_flags_by_mask,
-	.enable_interrupt 	= NULL,
+	.init = tca64xxa_init,
+	.get_level = tca64xxa_get_level,
+	.set_level = tca64xxa_set_level,
+	.get_flags_by_mask = tca64xxa_get_flags_by_mask,
+	.set_flags_by_mask = tca64xxa_set_flags_by_mask,
+	.enable_interrupt = NULL,
 #ifdef CONFIG_IO_EXPANDER_SUPPORT_GET_PORT
-	.get_port		= tca64xxa_get_port,
+	.get_port = tca64xxa_get_port,
 #endif
 };
diff --git a/driver/ioexpander/tca64xxa.h b/driver/ioexpander/tca64xxa.h
index 2d2e6e36bc..af095d7ea9 100644
--- a/driver/ioexpander/tca64xxa.h
+++ b/driver/ioexpander/tca64xxa.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,17 +11,17 @@
 /* io-expander driver specific flag bit for tca6424a */
 #define IOEX_FLAGS_TCA64XXA_FLAG_VER_TCA6424A IOEX_FLAGS_CUSTOM_BIT(25)
 
-#define TCA64XXA_FLAG_VER_MASK		GENMASK(2, 1)
-#define TCA64XXA_FLAG_VER_OFFSET	0
+#define TCA64XXA_FLAG_VER_MASK GENMASK(2, 1)
+#define TCA64XXA_FLAG_VER_OFFSET 0
 
-#define TCA64XXA_REG_INPUT		0
-#define TCA64XXA_REG_OUTPUT		1
-#define TCA64XXA_REG_POLARITY_INV	2
-#define TCA64XXA_REG_CONF		3
+#define TCA64XXA_REG_INPUT 0
+#define TCA64XXA_REG_OUTPUT 1
+#define TCA64XXA_REG_POLARITY_INV 2
+#define TCA64XXA_REG_CONF 3
 
-#define TCA64XXA_DEFAULT_OUTPUT		0xFF
-#define TCA64XXA_DEFAULT_POLARITY_INV	0x00
-#define TCA64XXA_DEFAULT_CONF		0xFF
+#define TCA64XXA_DEFAULT_OUTPUT 0xFF
+#define TCA64XXA_DEFAULT_POLARITY_INV 0x00
+#define TCA64XXA_DEFAULT_CONF 0xFF
 
 extern const struct ioexpander_drv tca64xxa_ioexpander_drv;
 
diff --git a/driver/led/aw20198.c b/driver/led/aw20198.c
index 1322c08a09..e2eea69481 100644
--- a/driver/led/aw20198.c
+++ b/driver/led/aw20198.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,12 +16,12 @@
 #define CPRINTF(fmt, args...) cprintf(CC_RGBKBD, "AW20198: " fmt, ##args)
 #define CPRINTS(fmt, args...) cprints(CC_RGBKBD, "AW20198: " fmt, ##args)
 
-#define BUF_SIZE	(SIZE_OF_RGB * AW20198_GRID_SIZE)
+#define BUF_SIZE (SIZE_OF_RGB * AW20198_GRID_SIZE)
 
 static int aw20198_read(struct rgbkbd *ctx, uint8_t addr, uint8_t *value)
 {
-	return i2c_xfer(ctx->cfg->i2c, AW20198_I2C_ADDR_FLAG,
-			&addr, sizeof(addr), value, sizeof(*value));
+	return i2c_xfer(ctx->cfg->i2c, AW20198_I2C_ADDR_FLAG, &addr,
+			sizeof(addr), value, sizeof(*value));
 }
 
 static int aw20198_write(struct rgbkbd *ctx, uint8_t addr, uint8_t value)
@@ -31,8 +31,8 @@ static int aw20198_write(struct rgbkbd *ctx, uint8_t addr, uint8_t value)
 		[1] = value,
 	};
 
-	return i2c_xfer(ctx->cfg->i2c, AW20198_I2C_ADDR_FLAG,
-			buf, sizeof(buf), NULL, 0);
+	return i2c_xfer(ctx->cfg->i2c, AW20198_I2C_ADDR_FLAG, buf, sizeof(buf),
+			NULL, 0);
 }
 
 static int aw20198_set_page(struct rgbkbd *ctx, uint8_t page)
@@ -103,8 +103,8 @@ static int aw20198_set_color(struct rgbkbd *ctx, uint8_t offset,
 		buf[i * SIZE_OF_RGB + 3] = color[i].b;
 	}
 
-	return i2c_xfer(ctx->cfg->i2c, AW20198_I2C_ADDR_FLAG,
-			buf, frame_len, NULL, 0);
+	return i2c_xfer(ctx->cfg->i2c, AW20198_I2C_ADDR_FLAG, buf, frame_len,
+			NULL, 0);
 }
 
 static int aw20198_set_scale(struct rgbkbd *ctx, uint8_t offset,
@@ -131,8 +131,8 @@ static int aw20198_set_scale(struct rgbkbd *ctx, uint8_t offset,
 		buf[i * SIZE_OF_RGB + 3] = scale.b;
 	}
 
-	return i2c_xfer(ctx->cfg->i2c, AW20198_I2C_ADDR_FLAG,
-			buf, frame_len, NULL, 0);
+	return i2c_xfer(ctx->cfg->i2c, AW20198_I2C_ADDR_FLAG, buf, frame_len,
+			NULL, 0);
 }
 
 static int aw20198_set_gcc(struct rgbkbd *ctx, uint8_t level)
@@ -159,7 +159,7 @@ static int aw20198_init(struct rgbkbd *ctx)
 	rv = aw20198_get_config(ctx, AW20198_REG_GCR, &u8);
 	if (rv) {
 		return rv;
-	}  
+	}
 	u8 &= ~AW20198_REG_GCR_SWSEL_MASK;
 	u8 |= ((ctx->cfg->col_len - 1) << AW20198_REG_GCR_SWSEL_SHIFT);
 	rv = aw20198_write(ctx, AW20198_REG_GCR, u8);
diff --git a/driver/led/aw20198.h b/driver/led/aw20198.h
index bbb284cc3a..85ef8c4b9e 100644
--- a/driver/led/aw20198.h
+++ b/driver/led/aw20198.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,38 +7,38 @@
 #define __CROS_EC_DRIVER_LED_AW20198_H
 
 /* This depends on AD0 and AD1. (GRD, GRD) = 0x20. */
-#define AW20198_I2C_ADDR_FLAG	0x20
-
-#define AW20198_ROW_SIZE	6
-#define AW20198_COL_SIZE	11
-#define AW20198_GRID_SIZE	(AW20198_COL_SIZE * AW20198_ROW_SIZE)
-
-#define AW20198_PAGE_FUNC	0xC0
-#define AW20198_PAGE_PWM	0xC1
-#define AW20198_PAGE_SCALE	0xC2
-
-#define AW20198_REG_GCR				0x00
-#define AW20198_REG_GCR_SWSEL_MASK		0xF0
-#define AW20198_REG_GCR_SWSEL_SHIFT		4
-#define AW20198_REG_GCR_SW1_ACTIVE		0
-#define AW20198_REG_GCR_SW1_TO_SW2_ACTIVE	1
-#define AW20198_REG_GCR_SW1_TO_SW3_ACTIVE	2
-#define AW20198_REG_GCR_SW1_TO_SW4_ACTIVE	3
-#define AW20198_REG_GCR_SW1_TO_SW5_ACTIVE	4
-#define AW20198_REG_GCR_SW1_TO_SW6_ACTIVE	5
-#define AW20198_REG_GCR_SW1_TO_SW7_ACTIVE	6
-#define AW20198_REG_GCR_SW1_TO_SW8_ACTIVE	7
-#define AW20198_REG_GCR_SW1_TO_SW9_ACTIVE	8
-#define AW20198_REG_GCR_SW1_TO_SW10_ACTIVE	9
-#define AW20198_REG_GCR_SW1_TO_SW11_ACTIVE	10
-
-#define AW20198_REG_GCC		0x01
-#define AW20198_REG_RSTN	0x2F
-#define AW20198_REG_MIXCR	0x46
-#define AW20198_REG_PAGE	0xF0
-
-#define AW20198_RESET_MAGIC	0xAE
+#define AW20198_I2C_ADDR_FLAG 0x20
+
+#define AW20198_ROW_SIZE 6
+#define AW20198_COL_SIZE 11
+#define AW20198_GRID_SIZE (AW20198_COL_SIZE * AW20198_ROW_SIZE)
+
+#define AW20198_PAGE_FUNC 0xC0
+#define AW20198_PAGE_PWM 0xC1
+#define AW20198_PAGE_SCALE 0xC2
+
+#define AW20198_REG_GCR 0x00
+#define AW20198_REG_GCR_SWSEL_MASK 0xF0
+#define AW20198_REG_GCR_SWSEL_SHIFT 4
+#define AW20198_REG_GCR_SW1_ACTIVE 0
+#define AW20198_REG_GCR_SW1_TO_SW2_ACTIVE 1
+#define AW20198_REG_GCR_SW1_TO_SW3_ACTIVE 2
+#define AW20198_REG_GCR_SW1_TO_SW4_ACTIVE 3
+#define AW20198_REG_GCR_SW1_TO_SW5_ACTIVE 4
+#define AW20198_REG_GCR_SW1_TO_SW6_ACTIVE 5
+#define AW20198_REG_GCR_SW1_TO_SW7_ACTIVE 6
+#define AW20198_REG_GCR_SW1_TO_SW8_ACTIVE 7
+#define AW20198_REG_GCR_SW1_TO_SW9_ACTIVE 8
+#define AW20198_REG_GCR_SW1_TO_SW10_ACTIVE 9
+#define AW20198_REG_GCR_SW1_TO_SW11_ACTIVE 10
+
+#define AW20198_REG_GCC 0x01
+#define AW20198_REG_RSTN 0x2F
+#define AW20198_REG_MIXCR 0x46
+#define AW20198_REG_PAGE 0xF0
+
+#define AW20198_RESET_MAGIC 0xAE
 
 extern const struct rgbkbd_drv aw20198_drv;
 
-#endif  /* __CROS_EC_DRIVER_LED_AW20198_H */
+#endif /* __CROS_EC_DRIVER_LED_AW20198_H */
diff --git a/driver/led/ds2413.c b/driver/led/ds2413.c
index b856d85671..5268e52ac0 100644
--- a/driver/led/ds2413.c
+++ b/driver/led/ds2413.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,12 +19,12 @@ enum led_color {
 	LED_RED,
 	LED_YELLOW,
 	LED_GREEN,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
-static const uint8_t led_masks[LED_COLOR_COUNT] = {0xff, 0xfe, 0xfc, 0xfd};
-static const char * const color_names[LED_COLOR_COUNT] = {
-	"off", "red", "yellow", "green"};
+static const uint8_t led_masks[LED_COLOR_COUNT] = { 0xff, 0xfe, 0xfc, 0xfd };
+static const char *const color_names[LED_COLOR_COUNT] = { "off", "red",
+							  "yellow", "green" };
 
 /**
  * Set the onewire LED GPIO controller outputs
@@ -48,9 +48,9 @@ static int led_set_mask(int mask)
 	/* Write and turn on the LEDs */
 	onewire_write(0x5a);
 	onewire_write(mask);
-	onewire_write(~mask);  /* Repeat inverted */
+	onewire_write(~mask); /* Repeat inverted */
 
-	rv = onewire_read();   /* Confirmation byte */
+	rv = onewire_read(); /* Confirmation byte */
 	if (rv != 0xaa)
 		return EC_ERROR_UNKNOWN;
 
@@ -109,10 +109,10 @@ static void onewire_led_tick(void)
 	/* Translate charge state to LED color */
 	switch (charge_get_state()) {
 	case PWR_STATE_IDLE:
-		if (chflags & CHARGE_FLAG_FORCE_IDLE)
-			new_color = (tick_count & 1) ? LED_GREEN : LED_OFF;
-		else
-			new_color = LED_GREEN;
+		new_color = LED_GREEN;
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		new_color = (tick_count & 1) ? LED_GREEN : LED_OFF;
 		break;
 	case PWR_STATE_CHARGE:
 		new_color = LED_YELLOW;
@@ -149,7 +149,7 @@ DECLARE_HOOK(HOOK_SECOND, onewire_led_tick, HOOK_PRIO_DEFAULT);
 /*****************************************************************************/
 /* Console commands */
 #define CONFIG_CMD_POWERLED
-static int command_powerled(int argc, char **argv)
+static int command_powerled(int argc, const char **argv)
 {
 	int i;
 
@@ -161,6 +161,5 @@ static int command_powerled(int argc, char **argv)
 	return EC_ERROR_PARAM1;
 }
 DECLARE_CONSOLE_COMMAND(powerled, command_powerled,
-			"<off | red | yellow | green>",
-			"Set power LED color");
+			"<off | red | yellow | green>", "Set power LED color");
 #endif
diff --git a/driver/led/is31fl3733b.c b/driver/led/is31fl3733b.c
index 5b1df890f1..33004d1cec 100644
--- a/driver/led/is31fl3733b.c
+++ b/driver/led/is31fl3733b.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,63 +14,62 @@
 #define CPRINTF(fmt, args...) cprintf(CC_RGBKBD, "RGBKBD: " fmt, ##args)
 #define CPRINTS(fmt, args...) cprints(CC_RGBKBD, "RGBKBD: " fmt, ##args)
 
-
 /* This depends on ADDR1 and ADDR2. (GND, GND) = 0x50. */
-#define IS31FL3733B_ADDR_FLAGS		0x50
+#define IS31FL3733B_ADDR_FLAGS 0x50
 
-#define IS31FL3733B_ROW_SIZE	16
-#define IS31FL3733B_COL_SIZE	4
-#define IS31FL3733B_GRID_SIZE	(IS31FL3733B_COL_SIZE * IS31FL3733B_ROW_SIZE)
-#define IS31FL3733B_BUF_SIZE	(SIZE_OF_RGB * IS31FL3733B_GRID_SIZE)
+#define IS31FL3733B_ROW_SIZE 16
+#define IS31FL3733B_COL_SIZE 4
+#define IS31FL3733B_GRID_SIZE (IS31FL3733B_COL_SIZE * IS31FL3733B_ROW_SIZE)
+#define IS31FL3733B_BUF_SIZE (SIZE_OF_RGB * IS31FL3733B_GRID_SIZE)
 
 /* IS31FL3733B registers */
-#define IS31FL3733B_REG_COMMAND			0xFD
-#define IS31FL3733B_REG_COMMAND_WRITE_LOCK	0xFE
-#define IS31FL3733B_REG_INT_MASK		0xF0
-#define IS31FL3733B_REG_INT_STATUS		0xF1
+#define IS31FL3733B_REG_COMMAND 0xFD
+#define IS31FL3733B_REG_COMMAND_WRITE_LOCK 0xFE
+#define IS31FL3733B_REG_INT_MASK 0xF0
+#define IS31FL3733B_REG_INT_STATUS 0xF1
 
-#define IS31FL3733B_PAGE_CTRL			0x00
-#define IS31FL3733B_PAGE_PWM			0x01
-#define IS31FL3733B_PAGE_AUTO			0x02
-#define IS31FL3733B_PAGE_FUNC			0x03
+#define IS31FL3733B_PAGE_CTRL 0x00
+#define IS31FL3733B_PAGE_PWM 0x01
+#define IS31FL3733B_PAGE_AUTO 0x02
+#define IS31FL3733B_PAGE_FUNC 0x03
 
 /* FEh Command Register Write Lock */
-#define IS31FL3733B_WRITE_DISABLE		0x00
-#define IS31FL3733B_WRITE_ENABLE		0xC5
-
-#define IS31FL3733B_INT_MASK_IAC		BIT(3)
-#define IS31FL3733B_INT_MASK_IAB		BIT(2)
-#define IS31FL3733B_INT_MASK_IS			BIT(1)
-#define IS31FL3733B_INT_MASK_IO			BIT(0)
-#define IS31FL3733B_INT_STATUS_ABM3		BIT(4)
-#define IS31FL3733B_INT_STATUS_ABM2		BIT(3)
-#define IS31FL3733B_INT_STATUS_ABM1		BIT(2)
-#define IS31FL3733B_INT_STATUS_SB		BIT(1)
-#define IS31FL3733B_INT_STATUS_OB		BIT(0)
-
-#define IS31FL3733B_FUNC_CFG			0x00
-#define IS31FL3733B_FUNC_GCC			0x01
-#define IS31FL3733B_FUNC_ABM1_1			0x02
-#define IS31FL3733B_FUNC_ABM1_2			0x03
-#define IS31FL3733B_FUNC_ABM1_3			0x04
-#define IS31FL3733B_FUNC_ABM1_4			0x05
-#define IS31FL3733B_FUNC_ABM2_1			0x06
-#define IS31FL3733B_FUNC_ABM2_2			0x07
-#define IS31FL3733B_FUNC_ABM2_3			0x08
-#define IS31FL3733B_FUNC_ABM2_4			0x09
-#define IS31FL3733B_FUNC_ABM3_1			0x0a
-#define IS31FL3733B_FUNC_ABM3_2			0x0b
-#define IS31FL3733B_FUNC_ABM3_3			0x0c
-#define IS31FL3733B_FUNC_ABM3_4			0x0d
-#define IS31FL3733B_FUNC_TUR			0x0e
-#define IS31FL3733B_FUNC_SW_PU			0x0f
-#define IS31FL3733B_FUNC_CS_PD			0x10
-#define IS31FL3733B_FUNC_RST			0x11
+#define IS31FL3733B_WRITE_DISABLE 0x00
+#define IS31FL3733B_WRITE_ENABLE 0xC5
+
+#define IS31FL3733B_INT_MASK_IAC BIT(3)
+#define IS31FL3733B_INT_MASK_IAB BIT(2)
+#define IS31FL3733B_INT_MASK_IS BIT(1)
+#define IS31FL3733B_INT_MASK_IO BIT(0)
+#define IS31FL3733B_INT_STATUS_ABM3 BIT(4)
+#define IS31FL3733B_INT_STATUS_ABM2 BIT(3)
+#define IS31FL3733B_INT_STATUS_ABM1 BIT(2)
+#define IS31FL3733B_INT_STATUS_SB BIT(1)
+#define IS31FL3733B_INT_STATUS_OB BIT(0)
+
+#define IS31FL3733B_FUNC_CFG 0x00
+#define IS31FL3733B_FUNC_GCC 0x01
+#define IS31FL3733B_FUNC_ABM1_1 0x02
+#define IS31FL3733B_FUNC_ABM1_2 0x03
+#define IS31FL3733B_FUNC_ABM1_3 0x04
+#define IS31FL3733B_FUNC_ABM1_4 0x05
+#define IS31FL3733B_FUNC_ABM2_1 0x06
+#define IS31FL3733B_FUNC_ABM2_2 0x07
+#define IS31FL3733B_FUNC_ABM2_3 0x08
+#define IS31FL3733B_FUNC_ABM2_4 0x09
+#define IS31FL3733B_FUNC_ABM3_1 0x0a
+#define IS31FL3733B_FUNC_ABM3_2 0x0b
+#define IS31FL3733B_FUNC_ABM3_3 0x0c
+#define IS31FL3733B_FUNC_ABM3_4 0x0d
+#define IS31FL3733B_FUNC_TUR 0x0e
+#define IS31FL3733B_FUNC_SW_PU 0x0f
+#define IS31FL3733B_FUNC_CS_PD 0x10
+#define IS31FL3733B_FUNC_RST 0x11
 
 static int is31fl3733b_read(struct rgbkbd *ctx, uint8_t addr, uint8_t *value)
 {
-	return i2c_xfer(ctx->cfg->i2c, IS31FL3733B_ADDR_FLAGS,
-			&addr, sizeof(addr), value, sizeof(*value));
+	return i2c_xfer(ctx->cfg->i2c, IS31FL3733B_ADDR_FLAGS, &addr,
+			sizeof(addr), value, sizeof(*value));
 }
 
 static int is31fl3733b_write(struct rgbkbd *ctx, uint8_t addr, uint8_t value)
@@ -80,8 +79,8 @@ static int is31fl3733b_write(struct rgbkbd *ctx, uint8_t addr, uint8_t value)
 		[1] = value,
 	};
 
-	return i2c_xfer(ctx->cfg->i2c, IS31FL3733B_ADDR_FLAGS,
-			buf, sizeof(buf), NULL, 0);
+	return i2c_xfer(ctx->cfg->i2c, IS31FL3733B_ADDR_FLAGS, buf, sizeof(buf),
+			NULL, 0);
 }
 
 static int is31fl3733b_set_page(struct rgbkbd *ctx, uint8_t page)
@@ -90,7 +89,7 @@ static int is31fl3733b_set_page(struct rgbkbd *ctx, uint8_t page)
 
 	/* unlock page select once */
 	rv = is31fl3733b_write(ctx, IS31FL3733B_REG_COMMAND_WRITE_LOCK,
-					IS31FL3733B_WRITE_ENABLE);
+			       IS31FL3733B_WRITE_ENABLE);
 	if (rv) {
 		return rv;
 	}
@@ -99,7 +98,7 @@ static int is31fl3733b_set_page(struct rgbkbd *ctx, uint8_t page)
 }
 
 static int is31fl3733b_get_config(struct rgbkbd *ctx, uint8_t addr,
-							uint8_t *value)
+				  uint8_t *value)
 {
 	int rv;
 
@@ -112,7 +111,7 @@ static int is31fl3733b_get_config(struct rgbkbd *ctx, uint8_t addr,
 }
 
 static int is31fl3733b_set_config(struct rgbkbd *ctx, uint8_t addr,
-							uint8_t value)
+				  uint8_t value)
 {
 	int rv;
 
@@ -150,7 +149,7 @@ static int is31fl3733b_enable(struct rgbkbd *ctx, bool enable)
 }
 
 static int is31fl3733b_set_color(struct rgbkbd *ctx, uint8_t offset,
-			     struct rgb_s *color, uint8_t len)
+				 struct rgb_s *color, uint8_t len)
 {
 	int led_addr, led_addr_row, led_addr_col;
 	int i, rv;
@@ -165,7 +164,7 @@ static int is31fl3733b_set_color(struct rgbkbd *ctx, uint8_t offset,
 		led_addr_col = (offset + i) / ctx->cfg->row_len;
 		led_addr = led_addr_row * 0x30 + led_addr_col;
 
-		rv  = is31fl3733b_write(ctx, led_addr + 0x00, color[i].r);
+		rv = is31fl3733b_write(ctx, led_addr + 0x00, color[i].r);
 		rv |= is31fl3733b_write(ctx, led_addr + 0x10, color[i].g);
 		rv |= is31fl3733b_write(ctx, led_addr + 0x20, color[i].b);
 
@@ -209,16 +208,13 @@ static int is31fl3733b_init(struct rgbkbd *ctx)
 	}
 
 	if (IS_ENABLED(CONFIG_RGB_KEYBOARD_DEBUG)) {
-
 		uint8_t val;
 		int ret;
 
-		ret = is31fl3733b_get_config(ctx,
-					IS31FL3733B_FUNC_SW_PU, &val);
+		ret = is31fl3733b_get_config(ctx, IS31FL3733B_FUNC_SW_PU, &val);
 		CPRINTS("SW_PU: val=0x%02x (rv=%d)", val, ret);
 
-		ret = is31fl3733b_get_config(ctx,
-					IS31FL3733B_FUNC_CS_PD, &val);
+		ret = is31fl3733b_get_config(ctx, IS31FL3733B_FUNC_CS_PD, &val);
 		CPRINTS("CS_PD: val=0x%02x (rv=%d)", val, ret);
 	}
 
diff --git a/driver/led/is31fl3743b.c b/driver/led/is31fl3743b.c
index a07b2f63f8..5eef21c388 100644
--- a/driver/led/is31fl3743b.c
+++ b/driver/led/is31fl3743b.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,30 +17,30 @@
 
 #define SPI(id) (&(spi_devices[id]))
 
-#define IS31FL3743B_ROW_SIZE	6
-#define IS31FL3743B_COL_SIZE	11
-#define IS31FL3743B_GRID_SIZE	(IS31FL3743B_COL_SIZE * IS31FL3743B_ROW_SIZE)
-#define IS31FL3743B_BUF_SIZE	(SIZE_OF_RGB * IS31FL3743B_GRID_SIZE)
+#define IS31FL3743B_ROW_SIZE 6
+#define IS31FL3743B_COL_SIZE 11
+#define IS31FL3743B_GRID_SIZE (IS31FL3743B_COL_SIZE * IS31FL3743B_ROW_SIZE)
+#define IS31FL3743B_BUF_SIZE (SIZE_OF_RGB * IS31FL3743B_GRID_SIZE)
 
-#define IS31FL3743B_CMD_ID	0b101
-#define IS31FL3743B_PAGE_PWM	0
-#define IS31FL3743B_PAGE_SCALE	1
-#define IS31FL3743B_PAGE_FUNC	2
+#define IS31FL3743B_CMD_ID 0b101
+#define IS31FL3743B_PAGE_PWM 0
+#define IS31FL3743B_PAGE_SCALE 1
+#define IS31FL3743B_PAGE_FUNC 2
 
-#define IS31FL3743B_REG_CONFIG		0x00
-#define IS31FL3743B_REG_GCC		0x01
-#define IS31FL3743B_REG_PD_PU		0x02
-#define IS31FL3743B_REG_SPREAD_SPECTRUM	0x25
-#define IS31FL3743B_REG_RSTN		0x2f
+#define IS31FL3743B_REG_CONFIG 0x00
+#define IS31FL3743B_REG_GCC 0x01
+#define IS31FL3743B_REG_PD_PU 0x02
+#define IS31FL3743B_REG_SPREAD_SPECTRUM 0x25
+#define IS31FL3743B_REG_RSTN 0x2f
 
-#define IS31FL3743B_CFG_SWS_1_11	0b0000
+#define IS31FL3743B_CFG_SWS_1_11 0b0000
 #define IS31FL3743B_CONFIG(sws, osde, ssd) \
 	((sws) << 4 | BIT(3) | (osde) << 1 | (ssd) << 0)
 
 struct is31fl3743b_cmd {
-	uint8_t page: 4;
-	uint8_t id: 3;
-	uint8_t read: 1;
+	uint8_t page : 4;
+	uint8_t id : 3;
+	uint8_t read : 1;
 } __packed;
 
 struct is31fl3743b_msg {
@@ -49,8 +49,8 @@ struct is31fl3743b_msg {
 	uint8_t payload[];
 } __packed;
 
-__maybe_unused
-static int is31fl3743b_read(struct rgbkbd *ctx, uint8_t addr, uint8_t *value)
+__maybe_unused static int is31fl3743b_read(struct rgbkbd *ctx, uint8_t addr,
+					   uint8_t *value)
 {
 	uint8_t buf[8];
 	struct is31fl3743b_msg *msg = (void *)buf;
@@ -81,9 +81,9 @@ static int is31fl3743b_write(struct rgbkbd *ctx, uint8_t addr, uint8_t value)
 
 static int is31fl3743b_enable(struct rgbkbd *ctx, bool enable)
 {
-	uint8_t u8 = IS31FL3743B_CONFIG(IS31FL3743B_CFG_SWS_1_11, 0,
-					enable ? 1 : 0);
-	CPRINTS("Setting config register to 0b%pb", BINARY_VALUE(u8, 8));
+	uint8_t u8 =
+		IS31FL3743B_CONFIG(IS31FL3743B_CFG_SWS_1_11, 0, enable ? 1 : 0);
+	CPRINTS("Setting config register to 0x%x", u8);
 	return is31fl3743b_write(ctx, IS31FL3743B_REG_CONFIG, u8);
 }
 
@@ -104,7 +104,7 @@ static int is31fl3743b_set_color(struct rgbkbd *ctx, uint8_t offset,
 		return EC_ERROR_OVERFLOW;
 	}
 
-	msg->addr = frame_offset + 1;	/* Register addr base is 1. */
+	msg->addr = frame_offset + 1; /* Register addr base is 1. */
 	for (i = 0; i < len; i++) {
 		msg->payload[i * SIZE_OF_RGB + 0] = color[i].r;
 		msg->payload[i * SIZE_OF_RGB + 1] = color[i].g;
@@ -131,7 +131,7 @@ static int is31fl3743b_set_scale(struct rgbkbd *ctx, uint8_t offset,
 		return EC_ERROR_OVERFLOW;
 	}
 
-	msg->addr = frame_offset + 1;	/* Address base is 1. */
+	msg->addr = frame_offset + 1; /* Address base is 1. */
 	for (i = 0; i < len; i++) {
 		msg->payload[i * SIZE_OF_RGB + 0] = scale.r;
 		msg->payload[i * SIZE_OF_RGB + 1] = scale.g;
diff --git a/driver/led/lm3509.c b/driver/led/lm3509.c
index fbd783a42e..5df604bac6 100644
--- a/driver/led/lm3509.c
+++ b/driver/led/lm3509.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -12,22 +12,19 @@
 
 static inline int lm3509_write(uint8_t reg, uint8_t val)
 {
-	return i2c_write8(I2C_PORT_KBLIGHT, LM3509_I2C_ADDR_FLAGS,
-			  reg, val);
+	return i2c_write8(I2C_PORT_KBLIGHT, LM3509_I2C_ADDR_FLAGS, reg, val);
 }
 
 static inline int lm3509_read(uint8_t reg, int *val)
 {
-	return i2c_read8(I2C_PORT_KBLIGHT, LM3509_I2C_ADDR_FLAGS,
-			 reg, val);
+	return i2c_read8(I2C_PORT_KBLIGHT, LM3509_I2C_ADDR_FLAGS, reg, val);
 }
 
 /* Brightness level (0.0 to 100.0%) to brightness register conversion table */
 static const uint16_t lm3509_brightness[32] = {
-	  0,   1,   6,  10,  11,  13,  16,  20,
-	 24,  28,  31,  37,  43,  52,  62,  75,
-	 87, 100, 125, 150, 168, 187, 225, 262,
-	312, 375, 437, 525, 612, 700, 875, 1000
+	0,   1,	  6,   10,  11,	 13,  16,  20,	24,  28,  31,
+	37,  43,  52,  62,  75,	 87,  100, 125, 150, 168, 187,
+	225, 262, 312, 375, 437, 525, 612, 700, 875, 1000
 };
 
 static int brightness_to_bmain(int percent)
diff --git a/driver/led/lm3509.h b/driver/led/lm3509.h
index a7defe1fb7..1f2ace46f0 100644
--- a/driver/led/lm3509.h
+++ b/driver/led/lm3509.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,7 +8,7 @@
 #ifndef __CROS_EC_LM3509_H
 #define __CROS_EC_LM3509_H
 
-#define LM3509_I2C_ADDR_FLAGS	0x36
+#define LM3509_I2C_ADDR_FLAGS 0x36
 
 /*
  * General purpose register
@@ -18,7 +18,7 @@
  * [1]= enable secondary current sink.
  * [0]= enable main current sink.
  */
-#define LM3509_REG_GP		0x10
+#define LM3509_REG_GP 0x10
 
 /*
  * Brightness register
@@ -27,10 +27,10 @@
  * 0x1F: 100%
  * Power-on-value: 0% (0xE0)
  */
-#define LM3509_REG_BMAIN	0xA0
-#define LM3509_REG_BSUB		0xB0
+#define LM3509_REG_BMAIN 0xA0
+#define LM3509_REG_BSUB 0xB0
 
-#define LM3509_BMAIN_MASK	0x1F
+#define LM3509_BMAIN_MASK 0x1F
 
 extern const struct kblight_drv kblight_lm3509;
 
diff --git a/driver/led/lm3630a.c b/driver/led/lm3630a.c
index e927c677a4..e3194ede45 100644
--- a/driver/led/lm3630a.c
+++ b/driver/led/lm3630a.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,14 +10,12 @@
 #include "lm3630a.h"
 #include "timer.h"
 
-
 /* I2C address */
 #define LM3630A_I2C_ADDR_FLAGS 0x36
 
 static inline int lm3630a_write(uint8_t reg, uint8_t val)
 {
-	return i2c_write8(I2C_PORT_KBLIGHT, LM3630A_I2C_ADDR_FLAGS,
-			  reg, val);
+	return i2c_write8(I2C_PORT_KBLIGHT, LM3630A_I2C_ADDR_FLAGS, reg, val);
 }
 
 static void deferred_lm3630a_poweron(void)
@@ -46,23 +44,22 @@ int lm3630a_poweron(void)
 
 	/* Enable feedback and PWM for banks A. */
 	ret |= lm3630a_write(LM3630A_REG_CONFIG,
-				LM3630A_CFG_BIT_FB_EN_A |
-				LM3630A_CFG_BIT_PWM_EN_A);
+			     LM3630A_CFG_BIT_FB_EN_A |
+				     LM3630A_CFG_BIT_PWM_EN_A);
 
 	/* 24V, 800mA overcurrent protection, 500kHz boost frequency. */
 	ret |= lm3630a_write(LM3630A_REG_BOOST_CONTROL,
-				LM3630A_BOOST_OVP_24V |
-				LM3630A_BOOST_OCP_800MA |
-				LM3630A_FMODE_500KHZ);
+			     LM3630A_BOOST_OVP_24V | LM3630A_BOOST_OCP_800MA |
+				     LM3630A_FMODE_500KHZ);
 
 	/* Limit current to 24.5mA */
 	ret |= lm3630a_write(LM3630A_REG_A_CURRENT, 0x1a);
 
 	/* Enable bank A, put in linear mode, and connect LED2 to bank A. */
 	ret |= lm3630a_write(LM3630A_REG_CONTROL,
-				LM3630A_CTRL_BIT_LINEAR_A |
-				LM3630A_CTRL_BIT_LED_EN_A |
-				LM3630A_CTRL_BIT_LED2_ON_A);
+			     LM3630A_CTRL_BIT_LINEAR_A |
+				     LM3630A_CTRL_BIT_LED_EN_A |
+				     LM3630A_CTRL_BIT_LED2_ON_A);
 
 	/*
 	 * Only set the brightness after ~100 ms. Without this, LED may blink
diff --git a/driver/led/lm3630a.h b/driver/led/lm3630a.h
index d43304b66e..34a268c370 100644
--- a/driver/led/lm3630a.h
+++ b/driver/led/lm3630a.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,56 +8,56 @@
 #ifndef __CROS_EC_LM3630A_H
 #define __CROS_EC_LM3630A_H
 
-#define LM3630A_REG_CONTROL		0x00
-#define LM3630A_REG_CONFIG		0x01
-#define LM3630A_REG_BOOST_CONTROL	0x02
-#define LM3630A_REG_A_BRIGHTNESS	0x03
-#define LM3630A_REG_B_BRIGHTNESS	0x04
-#define LM3630A_REG_A_CURRENT		0x05
-#define LM3630A_REG_B_CURRENT		0x06
-#define LM3630A_REG_ONOFF_RAMP		0x07
-#define LM3630A_REG_RUN_RAMP		0x08
-#define LM3630A_REG_INT_STATUS		0x09
-#define LM3630A_REG_INT_ENABLE		0x0a
-#define LM3630A_REG_FAULT_STATUS	0x0b
-#define LM3630A_REG_SW_RESET		0x0f
-#define LM3630A_REG_PWM_OUT_LOW		0x12
-#define LM3630A_REG_PWM_OUT_HIGH	0x13
-#define LM3630A_REG_REVISION		0x1f
-#define LM3630A_REG_FILTER_STRENGTH	0x50
+#define LM3630A_REG_CONTROL 0x00
+#define LM3630A_REG_CONFIG 0x01
+#define LM3630A_REG_BOOST_CONTROL 0x02
+#define LM3630A_REG_A_BRIGHTNESS 0x03
+#define LM3630A_REG_B_BRIGHTNESS 0x04
+#define LM3630A_REG_A_CURRENT 0x05
+#define LM3630A_REG_B_CURRENT 0x06
+#define LM3630A_REG_ONOFF_RAMP 0x07
+#define LM3630A_REG_RUN_RAMP 0x08
+#define LM3630A_REG_INT_STATUS 0x09
+#define LM3630A_REG_INT_ENABLE 0x0a
+#define LM3630A_REG_FAULT_STATUS 0x0b
+#define LM3630A_REG_SW_RESET 0x0f
+#define LM3630A_REG_PWM_OUT_LOW 0x12
+#define LM3630A_REG_PWM_OUT_HIGH 0x13
+#define LM3630A_REG_REVISION 0x1f
+#define LM3630A_REG_FILTER_STRENGTH 0x50
 
 /* Control register bits */
-#define LM3630A_CTRL_BIT_SLEEP_CMD	BIT(7)
-#define LM3630A_CTRL_BIT_SLEEP_STAT	BIT(6)
-#define LM3630A_CTRL_BIT_LINEAR_A	BIT(4)
-#define LM3630A_CTRL_BIT_LINEAR_B	BIT(3)
-#define LM3630A_CTRL_BIT_LED_EN_A	BIT(2)
-#define LM3630A_CTRL_BIT_LED_EN_B	BIT(1)
-#define LM3630A_CTRL_BIT_LED2_ON_A	BIT(0)
+#define LM3630A_CTRL_BIT_SLEEP_CMD BIT(7)
+#define LM3630A_CTRL_BIT_SLEEP_STAT BIT(6)
+#define LM3630A_CTRL_BIT_LINEAR_A BIT(4)
+#define LM3630A_CTRL_BIT_LINEAR_B BIT(3)
+#define LM3630A_CTRL_BIT_LED_EN_A BIT(2)
+#define LM3630A_CTRL_BIT_LED_EN_B BIT(1)
+#define LM3630A_CTRL_BIT_LED2_ON_A BIT(0)
 
 /* Config register bits */
-#define LM3630A_CFG_BIT_FB_EN_B		BIT(4)
-#define LM3630A_CFG_BIT_FB_EN_A		BIT(3)
-#define LM3630A_CFG_BIT_PWM_LOW		BIT(2)
-#define LM3630A_CFG_BIT_PWM_EN_B	BIT(1)
-#define LM3630A_CFG_BIT_PWM_EN_A	BIT(0)
+#define LM3630A_CFG_BIT_FB_EN_B BIT(4)
+#define LM3630A_CFG_BIT_FB_EN_A BIT(3)
+#define LM3630A_CFG_BIT_PWM_LOW BIT(2)
+#define LM3630A_CFG_BIT_PWM_EN_B BIT(1)
+#define LM3630A_CFG_BIT_PWM_EN_A BIT(0)
 
 /* Boost control register bits */
-#define LM3630A_BOOST_OVP_16V		(0 << 5)
-#define LM3630A_BOOST_OVP_24V		BIT(5)
-#define LM3630A_BOOST_OVP_32V		(2 << 5)
-#define LM3630A_BOOST_OVP_40V		(3 << 5)
-#define LM3630A_BOOST_OCP_600MA		(0 << 3)
-#define LM3630A_BOOST_OCP_800MA		BIT(3)
-#define LM3630A_BOOST_OCP_1000MA	(2 << 3)
-#define LM3630A_BOOST_OCP_1200MA	(3 << 3)
-#define LM3630A_BOOST_SLOW_START	BIT(2)
-#define LM3630A_SHIFT_500KHZ		(0 << 1)  /* FMODE=0 */
-#define LM3630A_SHIFT_560KHZ		BIT(1)  /* FMODE=0 */
-#define LM3630A_SHIFT_1000KHZ		(0 << 1)  /* FMODE=1 */
-#define LM3630A_SHIFT_1120KHZ		BIT(1)  /* FMODE=1 */
-#define LM3630A_FMODE_500KHZ		(0 << 0)
-#define LM3630A_FMODE_1000KHZ		BIT(0)
+#define LM3630A_BOOST_OVP_16V (0 << 5)
+#define LM3630A_BOOST_OVP_24V BIT(5)
+#define LM3630A_BOOST_OVP_32V (2 << 5)
+#define LM3630A_BOOST_OVP_40V (3 << 5)
+#define LM3630A_BOOST_OCP_600MA (0 << 3)
+#define LM3630A_BOOST_OCP_800MA BIT(3)
+#define LM3630A_BOOST_OCP_1000MA (2 << 3)
+#define LM3630A_BOOST_OCP_1200MA (3 << 3)
+#define LM3630A_BOOST_SLOW_START BIT(2)
+#define LM3630A_SHIFT_500KHZ (0 << 1) /* FMODE=0 */
+#define LM3630A_SHIFT_560KHZ BIT(1) /* FMODE=0 */
+#define LM3630A_SHIFT_1000KHZ (0 << 1) /* FMODE=1 */
+#define LM3630A_SHIFT_1120KHZ BIT(1) /* FMODE=1 */
+#define LM3630A_FMODE_500KHZ (0 << 0)
+#define LM3630A_FMODE_1000KHZ BIT(0)
 
 /* Power on and initialize LM3630A. */
 int lm3630a_poweron(void);
diff --git a/driver/led/lp5562.c b/driver/led/lp5562.c
index e0758a8b91..e1766fd776 100644
--- a/driver/led/lp5562.c
+++ b/driver/led/lp5562.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -123,7 +123,7 @@ int lp5562_set_pc(int engine, int val)
 /*****************************************************************************/
 /* Console commands */
 #ifdef CONFIG_CMD_POWERLED
-static int command_lp5562(int argc, char **argv)
+static int command_lp5562(int argc, const char **argv)
 {
 	if (argc == 4) {
 		char *e;
diff --git a/driver/led/lp5562.h b/driver/led/lp5562.h
index 75e820aab7..81031ee084 100644
--- a/driver/led/lp5562.h
+++ b/driver/led/lp5562.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,40 +8,40 @@
 #ifndef __CROS_EC_LP5562_H
 #define __CROS_EC_LP5562_H
 
-#define LP5562_REG_ENABLE	0x00
-#define LP5562_REG_OP_MODE	0x01
-#define LP5562_REG_B_PWM	0x02
-#define LP5562_REG_G_PWM	0x03
-#define LP5562_REG_R_PWM	0x04
-#define LP5562_REG_B_CURRENT	0x05
-#define LP5562_REG_G_CURRENT	0x06
-#define LP5562_REG_R_CURRENT	0x07
-#define LP5562_REG_CONFIG	0x08
-#define LP5562_REG_ENG1_PC	0x09
-#define LP5562_REG_ENG2_PC	0x0a
-#define LP5562_REG_ENG3_PC	0x0b
-#define LP5562_REG_STATUS	0x0c
-#define LP5562_REG_RESET	0x0d
-#define LP5562_REG_W_PWM	0x0e
-#define LP5562_REG_W_CURRENT	0x0f
-#define LP5562_REG_LED_MAP	0x70
-
-#define LP5562_REG_ENG_PROG(n)	(0x10 + ((n)-1) * 0x20)
+#define LP5562_REG_ENABLE 0x00
+#define LP5562_REG_OP_MODE 0x01
+#define LP5562_REG_B_PWM 0x02
+#define LP5562_REG_G_PWM 0x03
+#define LP5562_REG_R_PWM 0x04
+#define LP5562_REG_B_CURRENT 0x05
+#define LP5562_REG_G_CURRENT 0x06
+#define LP5562_REG_R_CURRENT 0x07
+#define LP5562_REG_CONFIG 0x08
+#define LP5562_REG_ENG1_PC 0x09
+#define LP5562_REG_ENG2_PC 0x0a
+#define LP5562_REG_ENG3_PC 0x0b
+#define LP5562_REG_STATUS 0x0c
+#define LP5562_REG_RESET 0x0d
+#define LP5562_REG_W_PWM 0x0e
+#define LP5562_REG_W_CURRENT 0x0f
+#define LP5562_REG_LED_MAP 0x70
+
+#define LP5562_REG_ENG_PROG(n) (0x10 + ((n)-1) * 0x20)
 
 /* Brightness range: 0x00 - 0xff */
-#define LP5562_COLOR_NONE	0x000000
-#define LP5562_COLOR_RED(b)	(0x010000 * (b))
-#define LP5562_COLOR_GREEN(b)	(0x000100 * (b))
-#define LP5562_COLOR_BLUE(b)	(0x000001 * (b))
-
-#define LP5562_ENG_SEL_NONE	0x0
-#define LP5562_ENG_SEL_1	0x1
-#define LP5562_ENG_SEL_2	0x2
-#define LP5562_ENG_SEL_3	0x3
-
-#define LP5562_ENG_HOLD		0x0
-#define LP5562_ENG_STEP		0x1
-#define LP5562_ENG_RUN		0x2
+#define LP5562_COLOR_NONE 0x000000
+#define LP5562_COLOR_RED(b) (0x010000 * (b))
+#define LP5562_COLOR_GREEN(b) (0x000100 * (b))
+#define LP5562_COLOR_BLUE(b) (0x000001 * (b))
+
+#define LP5562_ENG_SEL_NONE 0x0
+#define LP5562_ENG_SEL_1 0x1
+#define LP5562_ENG_SEL_2 0x2
+#define LP5562_ENG_SEL_3 0x3
+
+#define LP5562_ENG_HOLD 0x0
+#define LP5562_ENG_STEP 0x1
+#define LP5562_ENG_RUN 0x2
 
 /* Power on and initialize LP5562. */
 int lp5562_poweron(void);
diff --git a/driver/led/max695x.c b/driver/led/max695x.c
index c6155f1499..31e0799b11 100644
--- a/driver/led/max695x.c
+++ b/driver/led/max695x.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -13,12 +13,11 @@
 #include "max695x.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 static inline int max695x_i2c_write8(uint8_t offset, uint8_t data)
 {
-	return i2c_write8(I2C_PORT_PORT80, PORT80_I2C_ADDR,
-			   offset, (int)data);
+	return i2c_write8(I2C_PORT_PORT80, PORT80_I2C_ADDR, offset, (int)data);
 }
 
 static inline int max695x_i2c_write(uint8_t offset, uint8_t *data, int len)
@@ -27,8 +26,8 @@ static inline int max695x_i2c_write(uint8_t offset, uint8_t *data, int len)
 	 * The address pointer stored in the MAX695x increments after
 	 * each data byte is written unless the address equals 01111111
 	 */
-	return i2c_write_block(I2C_PORT_PORT80, PORT80_I2C_ADDR,
-			   offset, data, len);
+	return i2c_write_block(I2C_PORT_PORT80, PORT80_I2C_ADDR, offset, data,
+			       len);
 }
 
 int display_7seg_write(enum seven_seg_module_display module, uint16_t data)
@@ -84,12 +83,10 @@ int display_7seg_write(enum seven_seg_module_display module, uint16_t data)
  */
 static void max695x_init(void)
 {
-	uint8_t buf[4] = {
-		[0] = MAX695X_DECODE_MODE_HEX_DECODE,
-		[1] = MAX695X_INTENSITY_MEDIUM,
-		[2] = MAX695X_SCAN_LIMIT_4,
-		[3] = MAX695X_CONFIG_OPR_NORMAL
-	};
+	uint8_t buf[4] = { [0] = MAX695X_DECODE_MODE_HEX_DECODE,
+			   [1] = MAX695X_INTENSITY_MEDIUM,
+			   [2] = MAX695X_SCAN_LIMIT_4,
+			   [3] = MAX695X_CONFIG_OPR_NORMAL };
 	max695x_i2c_write(MAX695X_REG_DECODE_MODE, buf, ARRAY_SIZE(buf));
 }
 DECLARE_HOOK(HOOK_INIT, max695x_init, HOOK_PRIO_DEFAULT);
@@ -97,8 +94,7 @@ DECLARE_HOOK(HOOK_CHIPSET_STARTUP, max695x_init, HOOK_PRIO_DEFAULT);
 
 static void max695x_shutdown(void)
 {
-	max695x_i2c_write8(MAX695X_REG_CONFIG,
-			   MAX695X_CONFIG_OPR_SHUTDOWN);
+	max695x_i2c_write8(MAX695X_REG_CONFIG, MAX695X_CONFIG_OPR_SHUTDOWN);
 }
 DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, max695x_shutdown, HOOK_PRIO_DEFAULT);
 
@@ -118,7 +114,6 @@ static int console_command_max695x_write(int argc, char **argv)
 
 	return display_7seg_write(SEVEN_SEG_CONSOLE_DISPLAY, val);
 }
-DECLARE_CONSOLE_COMMAND(seg, console_command_max695x_write,
-			"<val>",
+DECLARE_CONSOLE_COMMAND(seg, console_command_max695x_write, "<val>",
 			"Write to 7 segment display in hex");
 #endif
diff --git a/driver/led/max695x.h b/driver/led/max695x.h
index 5ed5d91e2f..b792237d57 100644
--- a/driver/led/max695x.h
+++ b/driver/led/max695x.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -9,36 +9,36 @@
 #define __CROS_EC_MAX656X_H
 
 /* I2C interface */
-#define MAX695X_I2C_ADDR1_FLAGS	0x38
-#define MAX695X_I2C_ADDR2_FLAGS	0x39
+#define MAX695X_I2C_ADDR1_FLAGS 0x38
+#define MAX695X_I2C_ADDR2_FLAGS 0x39
 
 /* Decode mode register */
-#define MAX695X_REG_DECODE_MODE		0x01
+#define MAX695X_REG_DECODE_MODE 0x01
 /* Hexadecimal decode for digits 3–0 */
-#define MAX695X_DECODE_MODE_HEX_DECODE	0x0f
+#define MAX695X_DECODE_MODE_HEX_DECODE 0x0f
 
 /* Intensity register */
-#define MAX695X_REG_INTENSITY		0x02
+#define MAX695X_REG_INTENSITY 0x02
 /* Setting meduim intensity */
-#define MAX695X_INTENSITY_MEDIUM	0x20
+#define MAX695X_INTENSITY_MEDIUM 0x20
 
 /* Scan limit register value */
-#define MAX695X_REG_SCAN_LIMIT		0x03
+#define MAX695X_REG_SCAN_LIMIT 0x03
 
 /* Scanning digits 0-3 */
-#define MAX695X_SCAN_LIMIT_4		0x03
+#define MAX695X_SCAN_LIMIT_4 0x03
 
 /* Configuration register */
-#define MAX695X_REG_CONFIG		0x04
+#define MAX695X_REG_CONFIG 0x04
 /* Shutdown seven segment display */
-#define MAX695X_CONFIG_OPR_SHUTDOWN	0x00
+#define MAX695X_CONFIG_OPR_SHUTDOWN 0x00
 /* Start seven segment display */
-#define MAX695X_CONFIG_OPR_NORMAL	0x01
+#define MAX695X_CONFIG_OPR_NORMAL 0x01
 
 /* Digit addresses */
-#define MAX695X_DIGIT0_ADDR	0x20
-#define MAX695X_DIGIT1_ADDR	0x21
-#define MAX695X_DIGIT2_ADDR	0x22
-#define MAX695X_DIGIT3_ADDR	0x23
+#define MAX695X_DIGIT0_ADDR 0x20
+#define MAX695X_DIGIT1_ADDR 0x21
+#define MAX695X_DIGIT2_ADDR 0x22
+#define MAX695X_DIGIT3_ADDR 0x23
 
 #endif /* __CROS_EC_MAX656X_H */
diff --git a/driver/led/mp3385.c b/driver/led/mp3385.c
index 278e333ae1..50ce31341a 100644
--- a/driver/led/mp3385.c
+++ b/driver/led/mp3385.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -13,10 +13,10 @@
 #include "task.h"
 #include "timer.h"
 
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args)
 
-#define I2C_ADDR_MP3385_FLAGS	0x31
+#define I2C_ADDR_MP3385_FLAGS 0x31
 
 struct mp3385_value {
 	uint8_t offset;
@@ -40,36 +40,36 @@ static struct mp3385_value mp3385_conf[] = {
 	 * Frequency selection: 300(KHz)
 	 * Short circuit protection: 8(V)
 	 */
-	{.offset = 1, .data = 0x43},
+	{ .offset = 1, .data = 0x43 },
 	/*
 	 * Register 0x02: LED current Full-Scale Register
 	 * ISET Resistor: 127(Kohm)
 	 * Maximum LED current: 20196/127 = 159(mA)
 	 * Setting LED current: 62(mA)
 	 */
-	{.offset = 2, .data = 0x65},
+	{ .offset = 2, .data = 0x65 },
 
-	 /* Register 0x03: RO - ignored */
+	/* Register 0x03: RO - ignored */
 
 	/*
 	 * Register 0x04: Internal LED Dimming Brightness Register
 	 * SMBus PWM function: None Use
 	 */
-	{.offset = 4, .data = 0x00},
+	{ .offset = 4, .data = 0x00 },
 	/*
 	 * Register 0x05: OVP, OCP Threshold Register
 	 * Over Current Protection: 0.5(V)
 	 * Panel LED Voltage(Max): 47.8(V)
 	 * OVP setting: 54(V)
 	 */
-	{.offset = 5, .data = 0x97},
+	{ .offset = 5, .data = 0x97 },
 	/*
 	 * Register 0x00: Dimming mode Register
 	 * String Selection: 4(Number)
 	 * Interface Selection: 1
 	 * Brightness mode: 3
 	 */
-	{.offset = 0, .data = 0xF2},
+	{ .offset = 0, .data = 0xF2 },
 };
 static const int mp3385_conf_size = ARRAY_SIZE(mp3385_conf);
 
@@ -78,12 +78,12 @@ static void set_mp3385_reg(void)
 	int i;
 
 	for (i = 0; i < mp3385_conf_size; ++i) {
-		int rv = i2c_write8(I2C_PORT_BACKLIGHT,
-				    I2C_ADDR_MP3385_FLAGS,
+		int rv = i2c_write8(I2C_PORT_BACKLIGHT, I2C_ADDR_MP3385_FLAGS,
 				    mp3385_conf[i].offset, mp3385_conf[i].data);
 		if (rv) {
 			CPRINTS("Write MP3385 register %d "
-					"failed rv=%d", i, rv);
+				"failed rv=%d",
+				i, rv);
 			return;
 		}
 	}
@@ -113,7 +113,7 @@ void mp3385_interrupt(enum gpio_signal signal)
 	 *             |-   t2   -| : 1 second is enough
 	 */
 	hook_call_deferred(&mp3385_backlight_enable_deferred_data,
-						MP3385_POWER_BACKLIGHT_DELAY);
+			   MP3385_POWER_BACKLIGHT_DELAY);
 }
 
 int mp3385_set_config(int offset, int data)
diff --git a/driver/led/mp3385.h b/driver/led/mp3385.h
index bdb5dac0ae..733a8f76cd 100644
--- a/driver/led/mp3385.h
+++ b/driver/led/mp3385.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -27,7 +27,7 @@ void mp3385_board_init(void);
 int mp3385_set_config(int offset, int data);
 
 #ifndef MP3385_POWER_BACKLIGHT_DELAY
-#define MP3385_POWER_BACKLIGHT_DELAY (15*MSEC)
+#define MP3385_POWER_BACKLIGHT_DELAY (15 * MSEC)
 #endif
 
 void mp3385_interrupt(enum gpio_signal signal);
diff --git a/driver/led/oz554.c b/driver/led/oz554.c
index 4b661a592c..b2cbff08ba 100644
--- a/driver/led/oz554.c
+++ b/driver/led/oz554.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -13,10 +13,10 @@
 #include "task.h"
 #include "timer.h"
 
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args)
 
-#define I2C_ADDR_OZ554_FLAGS	0x31
+#define I2C_ADDR_OZ554_FLAGS 0x31
 
 struct oz554_value {
 	uint8_t offset;
@@ -40,38 +40,38 @@ static struct oz554_value oz554_conf[] = {
 	 * Frequency selection: 300(KHz)
 	 * Short circuit protection: 8(V)
 	 */
-	{.offset = 1, .data = 0x43},
+	{ .offset = 1, .data = 0x43 },
 	/*
 	 * Reigster 0x02: LED current amplitude control
 	 * ISET Resistor: 10.2(Kohm)
 	 * Maximum LED current: 1636/10.2 = 160.4(mA)
 	 * Setting LED current: 65(mA)
 	 */
-	{.offset = 2, .data = 0x65},
+	{ .offset = 2, .data = 0x65 },
 	/*
 	 * Reigster 0x03: LED backlight Status
 	 * Status function: Read only
 	 */
-	{.offset = 3, .data = 0x00},
+	{ .offset = 3, .data = 0x00 },
 	/*
 	 * Reigster 0x04: LED current control with SMBus
 	 * SMBus PWM function: None Use
 	 */
-	{.offset = 4, .data = 0x00},
+	{ .offset = 4, .data = 0x00 },
 	/*
 	 * Reigster 0x05: OVP, OCP control
 	 * Over Current Protection: 0.5(V)
 	 * Panel LED Voltage(Max): 47.8(V)
 	 * OVP setting: 54(V)
 	 */
-	{.offset = 5, .data = 0x97},
+	{ .offset = 5, .data = 0x97 },
 	/*
 	 * Reigster 0x00: Dimming mode and string ON/OFF control
 	 * String Selection: 4(Number)
 	 * Interface Selection: 1
 	 * Brightness mode: 3
 	 */
-	{.offset = 0, .data = 0xF2},
+	{ .offset = 0, .data = 0xF2 },
 };
 static const int oz554_conf_size = ARRAY_SIZE(oz554_conf);
 
@@ -80,11 +80,10 @@ static void set_oz554_reg(void)
 	int i;
 
 	for (i = 0; i < oz554_conf_size; ++i) {
-		int rv = i2c_write8(I2C_PORT_BACKLIGHT,
-				    I2C_ADDR_OZ554_FLAGS,
+		int rv = i2c_write8(I2C_PORT_BACKLIGHT, I2C_ADDR_OZ554_FLAGS,
 				    oz554_conf[i].offset, oz554_conf[i].data);
 		if (rv) {
-			CPRINTS("Write OZ554 register %d failed rv=%d" , i, rv);
+			CPRINTS("Write OZ554 register %d failed rv=%d", i, rv);
 			return;
 		}
 	}
@@ -114,7 +113,7 @@ void oz554_interrupt(enum gpio_signal signal)
 	 *             |-   t2   -| : 1 second is enough
 	 */
 	hook_call_deferred(&backlight_enable_deferred_data,
-                           OZ554_POWER_BACKLIGHT_DELAY);
+			   OZ554_POWER_BACKLIGHT_DELAY);
 }
 
 int oz554_set_config(int offset, int data)
diff --git a/driver/led/oz554.h b/driver/led/oz554.h
index 1893900b22..c735f9f3b9 100644
--- a/driver/led/oz554.h
+++ b/driver/led/oz554.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/driver/led/tlc59116f.c b/driver/led/tlc59116f.c
index b1c16a921b..3debdb3cfb 100644
--- a/driver/led/tlc59116f.c
+++ b/driver/led/tlc59116f.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The ChromiumOS Authors.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,13 +14,13 @@
 #define CPRINTF(fmt, args...) cprintf(CC_RGBKBD, "TLC59116F: " fmt, ##args)
 #define CPRINTS(fmt, args...) cprints(CC_RGBKBD, "TLC59116F: " fmt, ##args)
 
-#define TLC59116F_BUF_SIZE	(SIZE_OF_RGB * TLC59116F_GRID_SIZE)
-#define TLC59116_MODE_BIT_SLEEP		4
+#define TLC59116F_BUF_SIZE (SIZE_OF_RGB * TLC59116F_GRID_SIZE)
+#define TLC59116_MODE_BIT_SLEEP 4
 
 static int tlc59116f_read(struct rgbkbd *ctx, uint8_t addr, uint8_t *value)
 {
-	return i2c_xfer(ctx->cfg->i2c, TLC59116F_I2C_ADDR_FLAG,
-			&addr, sizeof(addr), value, sizeof(*value));
+	return i2c_xfer(ctx->cfg->i2c, TLC59116F_I2C_ADDR_FLAG, &addr,
+			sizeof(addr), value, sizeof(*value));
 }
 
 static int tlc59116f_write(struct rgbkbd *ctx, uint8_t addr, uint8_t value)
@@ -30,8 +30,8 @@ static int tlc59116f_write(struct rgbkbd *ctx, uint8_t addr, uint8_t value)
 		[1] = value,
 	};
 
-	return i2c_xfer(ctx->cfg->i2c, TLC59116F_I2C_ADDR_FLAG,
-			buf, sizeof(buf), NULL, 0);
+	return i2c_xfer(ctx->cfg->i2c, TLC59116F_I2C_ADDR_FLAG, buf,
+			sizeof(buf), NULL, 0);
 }
 
 static int tlc59116f_reset(struct rgbkbd *ctx)
@@ -75,7 +75,7 @@ static int tlc59116f_enable(struct rgbkbd *ctx, bool enable)
 }
 
 static int tlc59116f_set_color(struct rgbkbd *ctx, uint8_t offset,
-				struct rgb_s *color, uint8_t len)
+			       struct rgb_s *color, uint8_t len)
 {
 	uint8_t buf[sizeof(offset) + TLC59116F_BUF_SIZE];
 	const int frame_len = len * SIZE_OF_RGB + sizeof(offset);
@@ -86,20 +86,19 @@ static int tlc59116f_set_color(struct rgbkbd *ctx, uint8_t offset,
 		return EC_ERROR_OVERFLOW;
 	}
 
-	buf[0] = TLC59116_AI_BRIGHTNESS_ONLY |
-			(frame_offset + TLC59116F_PWM0);
+	buf[0] = TLC59116_AI_BRIGHTNESS_ONLY | (frame_offset + TLC59116F_PWM0);
 	for (i = 0; i < len; i++) {
 		buf[i * SIZE_OF_RGB + 1] = color[i].r;
 		buf[i * SIZE_OF_RGB + 2] = color[i].g;
 		buf[i * SIZE_OF_RGB + 3] = color[i].b;
 	}
 
-	return i2c_xfer(ctx->cfg->i2c, TLC59116F_I2C_ADDR_FLAG,
-			buf, frame_len, NULL, 0);
+	return i2c_xfer(ctx->cfg->i2c, TLC59116F_I2C_ADDR_FLAG, buf, frame_len,
+			NULL, 0);
 }
 
 static int tlc59116f_set_scale(struct rgbkbd *ctx, uint8_t offset,
-				 struct rgb_s scale, uint8_t len)
+			       struct rgb_s scale, uint8_t len)
 {
 	/* tlc59116f not support scale function */
 	return EC_SUCCESS;
diff --git a/driver/led/tlc59116f.h b/driver/led/tlc59116f.h
index 68ce218517..2a0347f568 100644
--- a/driver/led/tlc59116f.h
+++ b/driver/led/tlc59116f.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The ChromiumOS Authors.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,68 +7,68 @@
 #define __CROS_EC_DRIVER_LED_TLC59116F_H
 
 /* TLC59116F secondary address */
-#define TLC59116F_ADDR0_FLAG		0x60
-#define TLC59116F_ADDR1_FLAG		0x61
-#define TLC59116F_ADDR2_FLAG		0x62
-#define TLC59116F_ADDR3_FLAG		0x63
-#define TLC59116F_ADDR4_FLAG		0x64
-#define TLC59116F_ADDR5_FLAG		0x65
-#define TLC59116F_ADDR6_FLAG		0x66
-#define TLC59116F_ADDR7_FLAG		0x67
-#define TLC59116F_ADDR8_FLAG		0x68
-#define TLC59116F_ADDR9_FLAG		0x69
-#define TLC59116F_ADDR10_FLAG		0x6A
-#define TLC59116F_RESET			0x6B
-#define TLC59116F_ADDR12_FLAG		0x6C
-#define TLC59116F_ADDR13_FLAG		0x6D
-#define TLC59116F_ADDR14_FLAG		0x6E
-#define TLC59116F_ADDR15_FLAG		0x6F
+#define TLC59116F_ADDR0_FLAG 0x60
+#define TLC59116F_ADDR1_FLAG 0x61
+#define TLC59116F_ADDR2_FLAG 0x62
+#define TLC59116F_ADDR3_FLAG 0x63
+#define TLC59116F_ADDR4_FLAG 0x64
+#define TLC59116F_ADDR5_FLAG 0x65
+#define TLC59116F_ADDR6_FLAG 0x66
+#define TLC59116F_ADDR7_FLAG 0x67
+#define TLC59116F_ADDR8_FLAG 0x68
+#define TLC59116F_ADDR9_FLAG 0x69
+#define TLC59116F_ADDR10_FLAG 0x6A
+#define TLC59116F_RESET 0x6B
+#define TLC59116F_ADDR12_FLAG 0x6C
+#define TLC59116F_ADDR13_FLAG 0x6D
+#define TLC59116F_ADDR14_FLAG 0x6E
+#define TLC59116F_ADDR15_FLAG 0x6F
 
-#define TLC59116F_ROW_SIZE		1
-#define TLC59116F_COL_SIZE		5
-#define TLC59116F_GRID_SIZE	(TLC59116F_COL_SIZE * TLC59116F_ROW_SIZE)
+#define TLC59116F_ROW_SIZE 1
+#define TLC59116F_COL_SIZE 5
+#define TLC59116F_GRID_SIZE (TLC59116F_COL_SIZE * TLC59116F_ROW_SIZE)
 
 /* TLC59116F registers */
-#define TLC59116F_MODE1			0x00
-#define TLC59116F_MODE2			0x01
-#define TLC59116F_PWM0			0x02
-#define TLC59116F_PWM1			0x03
-#define TLC59116F_PWM2			0x04
-#define TLC59116F_PWM3			0x05
-#define TLC59116F_PWM4			0x06
-#define TLC59116F_PWM5			0x07
-#define TLC59116F_PWM6			0x08
-#define TLC59116F_PWM7			0x09
-#define TLC59116F_PWM8			0x0A
-#define TLC59116F_PWM9			0x0B
-#define TLC59116F_PWM10			0x0C
-#define TLC59116F_PWM11			0x0D
-#define TLC59116F_PWM12			0x0E
-#define TLC59116F_PWM13			0x0F
-#define TLC59116F_PWM14			0x10
-#define TLC59116F_PWM15			0x11
-#define TLC59116F_GRPPWM		0x12
-#define TLC59116F_GRPFREQ		0x13
-#define TLC59116F_LEDOUT0		0x14
-#define TLC59116F_LEDOUT1		0x15
-#define TLC59116F_LEDOUT2		0x16
-#define TLC59116F_LEDOUT3		0x17
-#define TLC59116F_SUBADR1		0x18
-#define TLC59116F_SUBADR2		0x19
-#define TLC59116F_SUBADR3		0x1A
-#define TLC59116F_ALLCALLADR		0x1B
+#define TLC59116F_MODE1 0x00
+#define TLC59116F_MODE2 0x01
+#define TLC59116F_PWM0 0x02
+#define TLC59116F_PWM1 0x03
+#define TLC59116F_PWM2 0x04
+#define TLC59116F_PWM3 0x05
+#define TLC59116F_PWM4 0x06
+#define TLC59116F_PWM5 0x07
+#define TLC59116F_PWM6 0x08
+#define TLC59116F_PWM7 0x09
+#define TLC59116F_PWM8 0x0A
+#define TLC59116F_PWM9 0x0B
+#define TLC59116F_PWM10 0x0C
+#define TLC59116F_PWM11 0x0D
+#define TLC59116F_PWM12 0x0E
+#define TLC59116F_PWM13 0x0F
+#define TLC59116F_PWM14 0x10
+#define TLC59116F_PWM15 0x11
+#define TLC59116F_GRPPWM 0x12
+#define TLC59116F_GRPFREQ 0x13
+#define TLC59116F_LEDOUT0 0x14
+#define TLC59116F_LEDOUT1 0x15
+#define TLC59116F_LEDOUT2 0x16
+#define TLC59116F_LEDOUT3 0x17
+#define TLC59116F_SUBADR1 0x18
+#define TLC59116F_SUBADR2 0x19
+#define TLC59116F_SUBADR3 0x1A
+#define TLC59116F_ALLCALLADR 0x1B
 
-#define TLC59116_LEDOUT_OFF		0x00
-#define TLC59116_LEDOUT_ON		0x55
-#define TLC59116_LEDOUT_PWM		0xAA
-#define TLC59116_LEDOUT_GROUP		0xFF
+#define TLC59116_LEDOUT_OFF 0x00
+#define TLC59116_LEDOUT_ON 0x55
+#define TLC59116_LEDOUT_PWM 0xAA
+#define TLC59116_LEDOUT_GROUP 0xFF
 
 /* Auto Increment flag */
-#define TLC59116_AI_NONE		0
-#define TLC59116_AI_ALL		        BIT(7)
-#define TLC59116_AI_BRIGHTNESS_ONLY	(BIT(7) | BIT(5))
-#define TLC59116_AI_GCR_ONLY		(BIT(7) | BIT(6))
+#define TLC59116_AI_NONE 0
+#define TLC59116_AI_ALL BIT(7)
+#define TLC59116_AI_BRIGHTNESS_ONLY (BIT(7) | BIT(5))
+#define TLC59116_AI_GCR_ONLY (BIT(7) | BIT(6))
 
 extern const struct rgbkbd_drv tlc59116f_drv;
 
-#endif  /* __CROS_EC_DRIVER_LED_TLC59116F_H */
+#endif /* __CROS_EC_DRIVER_LED_TLC59116F_H */
diff --git a/driver/ln9310.c b/driver/ln9310.c
index 4214b3b514..4a56568eb9 100644
--- a/driver/ln9310.c
+++ b/driver/ln9310.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -14,8 +14,8 @@
 #include "timer.h"
 
 #define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
 
 static int power_good;
 static int startup_workaround_required;
@@ -27,19 +27,15 @@ int ln9310_power_good(void)
 
 static inline int raw_read8(int offset, int *value)
 {
-	return i2c_read8(ln9310_config.i2c_port,
-			 ln9310_config.i2c_addr_flags,
-			 offset,
-			 value);
+	return i2c_read8(ln9310_config.i2c_port, ln9310_config.i2c_addr_flags,
+			 offset, value);
 }
 
 static inline int field_update8(int offset, int mask, int value)
 {
 	/* Clear mask and then set value in i2c reg value */
 	return i2c_field_update8(ln9310_config.i2c_port,
-				 ln9310_config.i2c_addr_flags,
-				 offset,
-				 mask,
+				 ln9310_config.i2c_addr_flags, offset, mask,
 				 value);
 }
 
@@ -87,11 +83,12 @@ static int is_battery_gt_10v(bool *out)
 	 * Turn on INFET_OUT_SWITCH_OK comparator;
 	 * configure INFET_OUT_SWITCH_OK to 10V.
 	 */
-	status = field_update8(LN9310_REG_TRACK_CTRL,
-		      LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_MASK |
-				LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG_MASK,
-		      LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_ON |
-				LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG_10V);
+	status =
+		field_update8(LN9310_REG_TRACK_CTRL,
+			      LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_MASK |
+				      LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG_MASK,
+			      LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_ON |
+				      LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG_10V);
 	if (status != EC_SUCCESS)
 		return status;
 
@@ -112,8 +109,8 @@ static int is_battery_gt_10v(bool *out)
 
 	/* Turn off INFET_OUT_SWITCH_OK comparator */
 	status = field_update8(LN9310_REG_TRACK_CTRL,
-		      LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_MASK,
-		      LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_OFF);
+			       LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_MASK,
+			       LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_OFF);
 
 	return status;
 }
@@ -237,11 +234,11 @@ static int ln9310_init_2to1(void)
 
 	/* Enable 2:1 operation mode */
 	rc |= field_update8(LN9310_REG_PWR_CTRL, LN9310_PWR_OP_MODE_MASK,
-			   LN9310_PWR_OP_MODE_SWITCH21);
+			    LN9310_PWR_OP_MODE_SWITCH21);
 
 	/* 2S lower bound delta configurations */
 	rc |= field_update8(LN9310_REG_LB_CTRL, LN9310_LB_DELTA_MASK,
-			   LN9310_LB_DELTA_2S);
+			    LN9310_LB_DELTA_2S);
 
 	/*
 	 * TODO(waihong): The LN9310_REG_SYS_CTR was set to a wrong value
@@ -263,23 +260,24 @@ static int ln9310_update_infet(void)
 
 	/* Update Infet register settings */
 	rc |= field_update8(LN9310_REG_CFG_5, LN9310_CFG_5_INGATE_PD_EN_MASK,
-			   LN9310_CFG_5_INGATE_PD_EN_OFF);
+			    LN9310_CFG_5_INGATE_PD_EN_OFF);
 
 	rc |= field_update8(LN9310_REG_CFG_5,
-			   LN9310_CFG_5_INFET_CP_PD_BIAS_CFG_MASK,
-			   LN9310_CFG_5_INFET_CP_PD_BIAS_CFG_LOWEST);
+			    LN9310_CFG_5_INFET_CP_PD_BIAS_CFG_MASK,
+			    LN9310_CFG_5_INFET_CP_PD_BIAS_CFG_LOWEST);
 
 	/* enable automatic infet control */
-	rc |= field_update8(LN9310_REG_PWR_CTRL, LN9310_PWR_INFET_AUTO_MODE_MASK,
-			   LN9310_PWR_INFET_AUTO_MODE_ON);
+	rc |= field_update8(LN9310_REG_PWR_CTRL,
+			    LN9310_PWR_INFET_AUTO_MODE_MASK,
+			    LN9310_PWR_INFET_AUTO_MODE_ON);
 
 	/* disable LS_HELPER during IDLE by setting MSK bit high  */
 	rc |= field_update8(LN9310_REG_CFG_0,
-			   LN9310_CFG_0_LS_HELPER_IDLE_MSK_MASK,
-			   LN9310_CFG_0_LS_HELPER_IDLE_MSK_ON);
+			    LN9310_CFG_0_LS_HELPER_IDLE_MSK_MASK,
+			    LN9310_CFG_0_LS_HELPER_IDLE_MSK_ON);
 
 	rc |= field_update8(LN9310_REG_LION_CTRL, LN9310_LION_CTRL_MASK,
-			   LN9310_LION_CTRL_LOCK);
+			    LN9310_LION_CTRL_LOCK);
 
 	return rc == EC_SUCCESS ? EC_SUCCESS : EC_ERROR_UNKNOWN;
 }
@@ -290,40 +288,40 @@ static int ln9310_precharge_cfly(uint64_t *precharge_timeout)
 	CPRINTS("LN9310 precharge cfly");
 
 	/* Unlock registers and enable test mode */
-	status |= field_update8(LN9310_REG_LION_CTRL,
-			LN9310_LION_CTRL_MASK,
-			LN9310_LION_CTRL_UNLOCK_AND_EN_TM);
+	status |= field_update8(LN9310_REG_LION_CTRL, LN9310_LION_CTRL_MASK,
+				LN9310_LION_CTRL_UNLOCK_AND_EN_TM);
 
 	/* disable test mode overrides */
 	status |= field_update8(LN9310_REG_FORCE_SC21_CTRL_2,
-			LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_MASK,
-			LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_OFF);
+				LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_MASK,
+				LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_OFF);
 
 	/* Configure test mode target values for precharge ckts.  */
-	status |= field_update8(LN9310_REG_FORCE_SC21_CTRL_1,
-			LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_MASK,
-			LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_ON);
+	status |= field_update8(
+		LN9310_REG_FORCE_SC21_CTRL_1,
+		LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_MASK,
+		LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_ON);
 
 	/* Force SCOUT precharge/predischarge overrides */
-	status |= field_update8(LN9310_REG_TEST_MODE_CTRL,
-			LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_MASK |
+	status |= field_update8(
+		LN9310_REG_TEST_MODE_CTRL,
+		LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_MASK |
 			LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_MASK,
-			LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_ON |
+		LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_ON |
 			LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_ON);
 
 	/* Force enable CFLY precharge overrides */
 	status |= field_update8(LN9310_REG_FORCE_SC21_CTRL_2,
-			LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_MASK,
-			LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_ON);
+				LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_MASK,
+				LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_ON);
 
 	/* delay long enough to ensure CFLY has time to fully precharge */
 	usleep(LN9310_CFLY_PRECHARGE_DELAY);
 
 	/* locking and leaving test mode will stop CFLY precharge */
 	*precharge_timeout = get_time().val + LN9310_CFLY_PRECHARGE_TIMEOUT;
-	status |= field_update8(LN9310_REG_LION_CTRL,
-			LN9310_LION_CTRL_MASK,
-			LN9310_LION_CTRL_LOCK);
+	status |= field_update8(LN9310_REG_LION_CTRL, LN9310_LION_CTRL_MASK,
+				LN9310_LION_CTRL_LOCK);
 
 	return status;
 }
@@ -334,30 +332,30 @@ static int ln9310_precharge_cfly_reset(void)
 	CPRINTS("LN9310 precharge cfly reset");
 
 	/* set known initial state for config bits related to cfly precharge */
-	status |= field_update8(LN9310_REG_LION_CTRL,
-		LN9310_LION_CTRL_MASK,
-		LN9310_LION_CTRL_UNLOCK);
+	status |= field_update8(LN9310_REG_LION_CTRL, LN9310_LION_CTRL_MASK,
+				LN9310_LION_CTRL_UNLOCK);
 
 	/* Force off SCOUT precharge/predischarge overrides */
-	status |= field_update8(LN9310_REG_TEST_MODE_CTRL,
-			LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_MASK |
+	status |= field_update8(
+		LN9310_REG_TEST_MODE_CTRL,
+		LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_MASK |
 			LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_MASK,
-			LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_OFF |
+		LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_OFF |
 			LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_OFF);
 
 	/* disable test mode overrides */
 	status |= field_update8(LN9310_REG_FORCE_SC21_CTRL_2,
-			LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_MASK,
-			LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_OFF);
+				LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_MASK,
+				LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_OFF);
 
 	/* disable CFLY and SC_OUT precharge control  */
-	status |= field_update8(LN9310_REG_FORCE_SC21_CTRL_1,
-			LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_MASK,
-			LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_OFF);
+	status |= field_update8(
+		LN9310_REG_FORCE_SC21_CTRL_1,
+		LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_MASK,
+		LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_OFF);
 
-	status |= field_update8(LN9310_REG_LION_CTRL,
-			LN9310_LION_CTRL_MASK,
-			LN9310_LION_CTRL_LOCK);
+	status |= field_update8(LN9310_REG_LION_CTRL, LN9310_LION_CTRL_MASK,
+				LN9310_LION_CTRL_LOCK);
 
 	return status;
 }
@@ -368,9 +366,7 @@ int ln9310_init(void)
 	enum battery_cell_type batt;
 
 	/* Make sure initial state of LN9310 is STANDBY (i.e. output is off)  */
-	field_update8(LN9310_REG_STARTUP_CTRL,
-				LN9310_STARTUP_STANDBY_EN,
-				1);
+	field_update8(LN9310_REG_STARTUP_CTRL, LN9310_STARTUP_STANDBY_EN, 1);
 
 	/*
 	 * LN9310 software startup is only required for earlier silicon revs.
@@ -383,7 +379,8 @@ int ln9310_init(void)
 		return status;
 	}
 	chip_revision = val & LN9310_BC_STS_C_CHIP_REV_MASK;
-	startup_workaround_required = chip_revision < LN9310_BC_STS_C_CHIP_REV_FIXED;
+	startup_workaround_required = chip_revision <
+				      LN9310_BC_STS_C_CHIP_REV_FIXED;
 
 	/* Update INFET configuration  */
 	status = ln9310_update_infet();
@@ -400,8 +397,7 @@ int ln9310_init(void)
 		      LN9310_PWR_OP_MODE_MANUAL_UPDATE_MASK,
 		      LN9310_PWR_OP_MODE_MANUAL_UPDATE_OFF);
 
-	field_update8(LN9310_REG_TIMER_CTRL,
-		      LN9310_TIMER_OP_SELF_SYNC_EN_MASK,
+	field_update8(LN9310_REG_TIMER_CTRL, LN9310_TIMER_OP_SELF_SYNC_EN_MASK,
 		      LN9310_TIMER_OP_SELF_SYNC_EN_ON);
 
 	/*
@@ -409,16 +405,13 @@ int ln9310_init(void)
 	 * circuit time to settle.
 	 */
 	field_update8(LN9310_REG_STARTUP_CTRL,
-		      LN9310_STARTUP_SELECT_EXT_5V_FOR_VDR,
-		      0);
+		      LN9310_STARTUP_SELECT_EXT_5V_FOR_VDR, 0);
 
-	field_update8(LN9310_REG_LB_CTRL,
-		      LN9310_LB_MIN_FREQ_EN,
+	field_update8(LN9310_REG_LB_CTRL, LN9310_LB_MIN_FREQ_EN,
 		      LN9310_LB_MIN_FREQ_EN);
 
 	/* Set minimum switching frequency to 25 kHz */
-	field_update8(LN9310_REG_SPARE_0,
-		      LN9310_SPARE_0_LB_MIN_FREQ_SEL_MASK,
+	field_update8(LN9310_REG_SPARE_0, LN9310_SPARE_0_LB_MIN_FREQ_SEL_MASK,
 		      LN9310_SPARE_0_LB_MIN_FREQ_SEL_ON);
 
 	usleep(LN9310_CDC_DELAY);
@@ -445,9 +438,7 @@ int ln9310_init(void)
 		return status;
 
 	/* Unmask the MODE change interrupt */
-	field_update8(LN9310_REG_INT1_MSK,
-			LN9310_INT1_MODE,
-			0);
+	field_update8(LN9310_REG_INT1_MSK, LN9310_INT1_MODE, 0);
 	return EC_SUCCESS;
 }
 
@@ -495,20 +486,22 @@ void ln9310_software_enable(int enable)
 	if (startup_workaround_required) {
 		if (enable) {
 			/*
-			* Software modification of LN9310 startup sequence w/ retry
-			* loop.
-			*
-			* (1) Clear interrupts
-			* (2) Precharge Cfly w/ overrides of internal LN9310 signals
-			* (3) disable overrides -> stop precharging Cfly
-			* (4.1) if < 100 ms elapsed since (2) -> trigger LN9310 internal
-			*                                        startup seq. 
-			* (4.2) else -> abort and optionally retry from step 2
-			*/
+			 * Software modification of LN9310 startup sequence w/
+			 * retry loop.
+			 *
+			 * (1) Clear interrupts
+			 * (2) Precharge Cfly w/ overrides of internal LN9310
+			 * signals (3) disable overrides -> stop precharging
+			 * Cfly (4.1) if < 100 ms elapsed since (2) -> trigger
+			 * LN9310 internal startup seq. (4.2) else -> abort and
+			 * optionally retry from step 2
+			 */
 			retry_count = 0;
-			while (!ln9310_init_completed && retry_count < LN9310_INIT_RETRY_COUNT) {
+			while (!ln9310_init_completed &&
+			       retry_count < LN9310_INIT_RETRY_COUNT) {
 				/* Precharge CFLY before starting up */
-				status = ln9310_precharge_cfly(&precharge_timeout);
+				status = ln9310_precharge_cfly(
+					&precharge_timeout);
 				if (status != EC_SUCCESS) {
 					CPRINTS("LN9310 failed to run Cfly precharge sequence");
 					status = ln9310_precharge_cfly_reset();
@@ -517,58 +510,64 @@ void ln9310_software_enable(int enable)
 				}
 
 				/*
-				* Only start the SC if the cfly precharge
-				* hasn't timed out (i.e. ended too long ago)
-				*/
+				 * Only start the SC if the cfly precharge
+				 * hasn't timed out (i.e. ended too long ago)
+				 */
 				if (get_time().val < precharge_timeout) {
-					/* Clear the STANDBY_EN bit to enable the SC */
+					/* Clear the STANDBY_EN bit to enable
+					 * the SC */
 					field_update8(LN9310_REG_STARTUP_CTRL,
-							LN9310_STARTUP_STANDBY_EN,
-							0);
-					if (get_time().val > precharge_timeout ) {
+						      LN9310_STARTUP_STANDBY_EN,
+						      0);
+					if (get_time().val >
+					    precharge_timeout) {
 						/*
-						* if timed out during previous I2C command, abort 
-						* startup attempt
-						*/
-						field_update8(LN9310_REG_STARTUP_CTRL,
+						 * if timed out during previous
+						 * I2C command, abort startup
+						 * attempt
+						 */
+						field_update8(
+							LN9310_REG_STARTUP_CTRL,
 							LN9310_STARTUP_STANDBY_EN,
 							1);
 					} else {
-						/* all other paths should reattempt startup  */
+						/* all other paths should
+						 * reattempt startup  */
 						ln9310_init_completed = true;
 					}
 				}
-				/* Reset to known state for config bits related to cfly precharge */
+				/* Reset to known state for config bits related
+				 * to cfly precharge */
 				ln9310_precharge_cfly_reset();
 				retry_count++;
 			}
 
 			if (!ln9310_init_completed) {
 				CPRINTS("LN9310 failed to start after %d retry attempts",
-						retry_count);
+					retry_count);
 			}
 		} else {
 			/*
-			* Internal LN9310 shutdown sequence is ok as is, so just reset
-			* the state to prepare for subsequent startup sequences.
-			*
-			* (1) set STANDBY_EN=1 to be sure the part turns off even if nEN=0
-			* (2) reset cfly precharge related registers to known initial state
-			*/
+			 * Internal LN9310 shutdown sequence is ok as is, so
+			 * just reset the state to prepare for subsequent
+			 * startup sequences.
+			 *
+			 * (1) set STANDBY_EN=1 to be sure the part turns off
+			 * even if nEN=0 (2) reset cfly precharge related
+			 * registers to known initial state
+			 */
 			field_update8(LN9310_REG_STARTUP_CTRL,
-					LN9310_STARTUP_STANDBY_EN,
-					1);
+				      LN9310_STARTUP_STANDBY_EN, 1);
 
 			ln9310_precharge_cfly_reset();
 		}
 	} else {
 		/*
-		* for newer LN9310 revsisions, the startup workaround is not required
-		* so the STANDBY_EN bit can just be set directly
-		*/
+		 * for newer LN9310 revsisions, the startup workaround is not
+		 * required so the STANDBY_EN bit can just be set directly
+		 */
 		field_update8(LN9310_REG_STARTUP_CTRL,
-					LN9310_STARTUP_STANDBY_EN,
-					!enable);
+			      LN9310_STARTUP_STANDBY_EN, !enable);
 	}
 	return;
 }
diff --git a/driver/mag_bmm150.c b/driver/mag_bmm150.c
index ad1eba7ad0..5088e51c14 100644
--- a/driver/mag_bmm150.c
+++ b/driver/mag_bmm150.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,75 +25,74 @@
 #error "Not implemented"
 #endif
 
-
 #define CPUTS(outstr) cputs(CC_ACCEL, outstr)
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args)
-
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args)
 
 /****************************************************************************
-* Copyright (C) 2011 - 2014 Bosch Sensortec GmbH
-*
-****************************************************************************/
+ * Copyright (C) 2011 - 2014 Bosch Sensortec GmbH
+ *
+ ****************************************************************************/
 /***************************************************************************
-* License:
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions are met:
-*
-*   Redistributions of source code must retain the above copyright
-*   notice, this list of conditions and the following disclaimer.
-*
-*   Redistributions in binary form must reproduce the above copyright
-*   notice, this list of conditions and the following disclaimer in the
-*   documentation and/or other materials provided with the distribution.
-*
-*   Neither the name of the copyright holder nor the names of the
-*   contributors may be used to endorse or promote products derived from
-*   this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
-*
-* The information provided is believed to be accurate and reliable.
-* The copyright holder assumes no responsibility for the consequences of use
-* of such information nor for any infringement of patents or
-* other rights of third parties which may result from its use.
-* No license is granted by implication or otherwise under any patent or
-* patent rights of the copyright holder.
-*/
-
-#define BMI150_READ_16BIT_COM_REG(store_, addr_) do { \
-	int val; \
-	raw_mag_read8(s->port, s->i2c_spi_addr_flags, (addr_), &val); \
-	store_ = val; \
-	raw_mag_read8(s->port, s->i2c_spi_addr_flags, (addr_) + 1, &val); \
-	store_ |= (val << 8); \
-} while (0)
+ * License:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *   Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ *   Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ *
+ *   Neither the name of the copyright holder nor the names of the
+ *   contributors may be used to endorse or promote products derived from
+ *   this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ * The information provided is believed to be accurate and reliable.
+ * The copyright holder assumes no responsibility for the consequences of use
+ * of such information nor for any infringement of patents or
+ * other rights of third parties which may result from its use.
+ * No license is granted by implication or otherwise under any patent or
+ * patent rights of the copyright holder.
+ */
 
+#define BMI150_READ_16BIT_COM_REG(store_, addr_)                              \
+	do {                                                                  \
+		int val;                                                      \
+		raw_mag_read8(s->port, s->i2c_spi_addr_flags, (addr_), &val); \
+		store_ = val;                                                 \
+		raw_mag_read8(s->port, s->i2c_spi_addr_flags, (addr_) + 1,    \
+			      &val);                                          \
+		store_ |= (val << 8);                                         \
+	} while (0)
 
 int bmm150_init(struct motion_sensor_t *s)
 {
 	int ret;
 	int val;
 	struct bmm150_comp_registers *regs = BMM150_COMP_REG(s);
-	struct mag_cal_t             *moc = BMM150_CAL(s);
+	struct mag_cal_t *moc = BMM150_CAL(s);
 
 	/* Set the compass from Suspend to Sleep */
-	ret = raw_mag_write8(s->port, s->i2c_spi_addr_flags,
-			     BMM150_PWR_CTRL, BMM150_PWR_ON);
+	ret = raw_mag_write8(s->port, s->i2c_spi_addr_flags, BMM150_PWR_CTRL,
+			     BMM150_PWR_ON);
 	msleep(4);
 	/* Now we can read the device id */
-	ret = raw_mag_read8(s->port, s->i2c_spi_addr_flags,
-			    BMM150_CHIP_ID, &val);
+	ret = raw_mag_read8(s->port, s->i2c_spi_addr_flags, BMM150_CHIP_ID,
+			    &val);
 	if (ret)
 		return EC_ERROR_UNKNOWN;
 
@@ -101,27 +100,24 @@ int bmm150_init(struct motion_sensor_t *s)
 		return EC_ERROR_ACCESS_DENIED;
 
 	/* Read the private registers for compensation */
-	ret = raw_mag_read8(s->port, s->i2c_spi_addr_flags,
-			    BMM150_REGA_DIG_X1, &val);
+	ret = raw_mag_read8(s->port, s->i2c_spi_addr_flags, BMM150_REGA_DIG_X1,
+			    &val);
 	if (ret)
 		return EC_ERROR_UNKNOWN;
 	regs->dig1[X] = val;
-	raw_mag_read8(s->port, s->i2c_spi_addr_flags,
-		      BMM150_REGA_DIG_Y1, &val);
+	raw_mag_read8(s->port, s->i2c_spi_addr_flags, BMM150_REGA_DIG_Y1, &val);
 	regs->dig1[Y] = val;
-	raw_mag_read8(s->port, s->i2c_spi_addr_flags,
-		      BMM150_REGA_DIG_X2, &val);
+	raw_mag_read8(s->port, s->i2c_spi_addr_flags, BMM150_REGA_DIG_X2, &val);
 	regs->dig2[X] = val;
-	raw_mag_read8(s->port, s->i2c_spi_addr_flags,
-		      BMM150_REGA_DIG_Y2, &val);
+	raw_mag_read8(s->port, s->i2c_spi_addr_flags, BMM150_REGA_DIG_Y2, &val);
 	regs->dig2[Y] = val;
 
-	raw_mag_read8(s->port, s->i2c_spi_addr_flags,
-		      BMM150_REGA_DIG_XY1, &val);
+	raw_mag_read8(s->port, s->i2c_spi_addr_flags, BMM150_REGA_DIG_XY1,
+		      &val);
 	regs->dig_xy1 = val;
 
-	raw_mag_read8(s->port, s->i2c_spi_addr_flags,
-		      BMM150_REGA_DIG_XY2, &val);
+	raw_mag_read8(s->port, s->i2c_spi_addr_flags, BMM150_REGA_DIG_XY2,
+		      &val);
 	regs->dig_xy2 = val;
 
 	BMI150_READ_16BIT_COM_REG(regs->dig_z1, BMM150_REGA_DIG_Z1_LSB);
@@ -130,21 +126,17 @@ int bmm150_init(struct motion_sensor_t *s)
 	BMI150_READ_16BIT_COM_REG(regs->dig_z4, BMM150_REGA_DIG_Z4_LSB);
 	BMI150_READ_16BIT_COM_REG(regs->dig_xyz1, BMM150_REGA_DIG_XYZ1_LSB);
 
-
 	/* Set the repetition in "Regular Preset" */
-	raw_mag_write8(s->port, s->i2c_spi_addr_flags,
-		       BMM150_REPXY, BMM150_REP(SPECIAL, XY));
-	raw_mag_write8(s->port, s->i2c_spi_addr_flags,
-		       BMM150_REPZ, BMM150_REP(SPECIAL, Z));
-	ret = raw_mag_read8(s->port, s->i2c_spi_addr_flags,
-			    BMM150_REPXY, &val);
-	ret = raw_mag_read8(s->port, s->i2c_spi_addr_flags,
-			    BMM150_REPZ, &val);
+	raw_mag_write8(s->port, s->i2c_spi_addr_flags, BMM150_REPXY,
+		       BMM150_REP(SPECIAL, XY));
+	raw_mag_write8(s->port, s->i2c_spi_addr_flags, BMM150_REPZ,
+		       BMM150_REP(SPECIAL, Z));
+	ret = raw_mag_read8(s->port, s->i2c_spi_addr_flags, BMM150_REPXY, &val);
+	ret = raw_mag_read8(s->port, s->i2c_spi_addr_flags, BMM150_REPZ, &val);
 	/*
 	 * Set the compass forced mode, to sleep after each measure.
 	 */
-	ret = raw_mag_write8(s->port, s->i2c_spi_addr_flags,
-			     BMM150_OP_CTRL,
+	ret = raw_mag_write8(s->port, s->i2c_spi_addr_flags, BMM150_OP_CTRL,
 			     BMM150_OP_MODE_FORCED << BMM150_OP_MODE_OFFSET);
 
 	init_mag_cal(moc);
@@ -152,10 +144,8 @@ int bmm150_init(struct motion_sensor_t *s)
 	return ret;
 }
 
-void bmm150_temp_compensate_xy(const struct motion_sensor_t *s,
-			       intv3_t raw,
-			       intv3_t comp,
-			       int r)
+void bmm150_temp_compensate_xy(const struct motion_sensor_t *s, intv3_t raw,
+			       intv3_t comp, int r)
 {
 	int inter, axis;
 	struct bmm150_comp_registers *regs = BMM150_COMP_REG(s);
@@ -191,10 +181,8 @@ void bmm150_temp_compensate_xy(const struct motion_sensor_t *s,
 	}
 }
 
-void bmm150_temp_compensate_z(const struct motion_sensor_t *s,
-			      intv3_t raw,
-			      intv3_t comp,
-			      int r)
+void bmm150_temp_compensate_z(const struct motion_sensor_t *s, intv3_t raw,
+			      intv3_t comp, int r)
 {
 	int dividend, divisor;
 	struct bmm150_comp_registers *regs = BMM150_COMP_REG(s);
@@ -221,9 +209,7 @@ void bmm150_temp_compensate_z(const struct motion_sensor_t *s,
 		comp[Z] = BMM150_OVERFLOW_OUTPUT;
 }
 
-void bmm150_normalize(const struct motion_sensor_t *s,
-		      intv3_t v,
-		      uint8_t *data)
+void bmm150_normalize(const struct motion_sensor_t *s, intv3_t v, uint8_t *data)
 {
 	uint16_t r;
 	intv3_t raw;
@@ -247,8 +233,7 @@ void bmm150_normalize(const struct motion_sensor_t *s,
 	v[Z] += cal->bias[Z];
 }
 
-int bmm150_set_offset(const struct motion_sensor_t *s,
-		      const intv3_t offset)
+int bmm150_set_offset(const struct motion_sensor_t *s, const intv3_t offset)
 {
 	struct mag_cal_t *cal = BMM150_CAL(s);
 	cal->bias[X] = offset[X];
@@ -257,8 +242,7 @@ int bmm150_set_offset(const struct motion_sensor_t *s,
 	return EC_SUCCESS;
 }
 
-int bmm150_get_offset(const struct motion_sensor_t *s,
-		      intv3_t offset)
+int bmm150_get_offset(const struct motion_sensor_t *s, intv3_t offset)
 {
 	struct mag_cal_t *cal = BMM150_CAL(s);
 	offset[X] = cal->bias[X];
diff --git a/driver/mag_lis2mdl.c b/driver/mag_lis2mdl.c
index c0f7dff90d..e8a8cb82ca 100644
--- a/driver/mag_lis2mdl.c
+++ b/driver/mag_lis2mdl.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,11 +24,9 @@
 #endif
 #endif
 
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
 
-void lis2mdl_normalize(const struct motion_sensor_t *s,
-		       intv3_t v,
-		       uint8_t *raw)
+void lis2mdl_normalize(const struct motion_sensor_t *s, intv3_t v, uint8_t *raw)
 {
 	struct mag_cal_t *cal = LIS2MDL_CAL(s);
 	int i;
@@ -82,8 +80,8 @@ static int set_range(struct motion_sensor_t *s, int range, int rnd)
  * @offset: offset vector
  * @temp: Temp
  */
-static int set_offset(const struct motion_sensor_t *s,
-		      const int16_t *offset, int16_t temp)
+static int set_offset(const struct motion_sensor_t *s, const int16_t *offset,
+		      int16_t temp)
 {
 	struct mag_cal_t *cal = LIS2MDL_CAL(s);
 
@@ -100,8 +98,8 @@ static int set_offset(const struct motion_sensor_t *s,
  * @offset: offset vector
  * @temp: Temp
  */
-static int get_offset(const struct motion_sensor_t *s,
-		      int16_t *offset, int16_t *temp)
+static int get_offset(const struct motion_sensor_t *s, int16_t *offset,
+		      int16_t *temp)
 {
 	struct mag_cal_t *cal = LIS2MDL_CAL(s);
 	intv3_t offset_int;
@@ -139,26 +137,24 @@ int lis2mdl_thru_lsm6dsm_init(struct motion_sensor_t *s)
 
 	mutex_lock(s->mutex);
 	/* Magnetometer in cascade mode */
-	ret = sensorhub_check_and_rst(
-			LSM6DSM_MAIN_SENSOR(s),
-			CONFIG_ACCELGYRO_SEC_ADDR_FLAGS,
-			LIS2MDL_WHO_AM_I_REG, LIS2MDL_WHO_AM_I,
-			LIS2MDL_CFG_REG_A_ADDR, LIS2MDL_FLAG_SW_RESET);
+	ret = sensorhub_check_and_rst(LSM6DSM_MAIN_SENSOR(s),
+				      CONFIG_ACCELGYRO_SEC_ADDR_FLAGS,
+				      LIS2MDL_WHO_AM_I_REG, LIS2MDL_WHO_AM_I,
+				      LIS2MDL_CFG_REG_A_ADDR,
+				      LIS2MDL_FLAG_SW_RESET);
 	if (ret != EC_SUCCESS)
 		goto err_unlock;
 
-	ret = sensorhub_config_ext_reg(
-			LSM6DSM_MAIN_SENSOR(s),
-			CONFIG_ACCELGYRO_SEC_ADDR_FLAGS,
-			LIS2MDL_CFG_REG_A_ADDR,
-			LIS2MDL_ODR_50HZ | LIS2MDL_MODE_CONT);
+	ret = sensorhub_config_ext_reg(LSM6DSM_MAIN_SENSOR(s),
+				       CONFIG_ACCELGYRO_SEC_ADDR_FLAGS,
+				       LIS2MDL_CFG_REG_A_ADDR,
+				       LIS2MDL_ODR_50HZ | LIS2MDL_MODE_CONT);
 	if (ret != EC_SUCCESS)
 		goto err_unlock;
 
-	ret = sensorhub_config_slv0_read(
-			LSM6DSM_MAIN_SENSOR(s),
-			CONFIG_ACCELGYRO_SEC_ADDR_FLAGS,
-			LIS2MDL_OUT_REG, OUT_XYZ_SIZE);
+	ret = sensorhub_config_slv0_read(LSM6DSM_MAIN_SENSOR(s),
+					 CONFIG_ACCELGYRO_SEC_ADDR_FLAGS,
+					 LIS2MDL_OUT_REG, OUT_XYZ_SIZE);
 	if (ret != EC_SUCCESS)
 		goto err_unlock;
 
@@ -197,8 +193,8 @@ static int lis2mdl_is_data_ready(const struct motion_sensor_t *s, int *ready)
 {
 	int ret, tmp;
 
-	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags,
-			   LIS2MDL_STATUS_REG, &tmp);
+	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, LIS2MDL_STATUS_REG,
+			   &tmp);
 	if (ret != EC_SUCCESS) {
 		*ready = 0;
 		return ret;
@@ -206,7 +202,6 @@ static int lis2mdl_is_data_ready(const struct motion_sensor_t *s, int *ready)
 
 	*ready = tmp & LIS2MDL_XYZ_DIRTY_MASK;
 	return EC_SUCCESS;
-
 }
 
 /**
@@ -239,8 +234,8 @@ int lis2mdl_read(const struct motion_sensor_t *s, intv3_t v)
 	}
 
 	mutex_lock(s->mutex);
-	ret = st_raw_read_n(s->port, s->i2c_spi_addr_flags,
-			    LIS2MDL_OUT_REG, raw, OUT_XYZ_SIZE);
+	ret = st_raw_read_n(s->port, s->i2c_spi_addr_flags, LIS2MDL_OUT_REG,
+			    raw, OUT_XYZ_SIZE);
 	mutex_unlock(s->mutex);
 	if (ret == EC_SUCCESS) {
 		lis2mdl_normalize(s, v, raw);
@@ -280,8 +275,7 @@ int lis2mdl_init(struct motion_sensor_t *s)
 	mutex_lock(s->mutex);
 
 	/* Reset the sensor */
-	ret = st_raw_write8(s->port, LIS2MDL_ADDR_FLAGS,
-			    LIS2MDL_CFG_REG_A_ADDR,
+	ret = st_raw_write8(s->port, LIS2MDL_ADDR_FLAGS, LIS2MDL_CFG_REG_A_ADDR,
 			    LIS2MDL_FLAG_SW_RESET);
 	if (ret != EC_SUCCESS)
 		goto lis2mdl_init_error;
@@ -330,20 +324,20 @@ int lis2mdl_set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
 	if (rate > 0) {
 		if (rnd)
 			/* Round up */
-			reg_val = rate <= 10000 ? LIS2MDL_ODR_10HZ
-				: rate <= 20000 ? LIS2MDL_ODR_20HZ
-				: LIS2MDL_ODR_50HZ;
+			reg_val = rate <= 10000 ? LIS2MDL_ODR_10HZ :
+				  rate <= 20000 ? LIS2MDL_ODR_20HZ :
+						  LIS2MDL_ODR_50HZ;
 		else
 			/* Round down */
-			reg_val = rate < 20000 ? LIS2MDL_ODR_10HZ
-				: rate < 50000 ? LIS2MDL_ODR_20HZ
-				: LIS2MDL_ODR_50HZ;
+			reg_val = rate < 20000 ? LIS2MDL_ODR_10HZ :
+				  rate < 50000 ? LIS2MDL_ODR_20HZ :
+						 LIS2MDL_ODR_50HZ;
 	}
 
-	normalized_rate = rate <= 0 ? 0
-		: reg_val == LIS2MDL_ODR_10HZ ? 10000
-		: reg_val == LIS2MDL_ODR_20HZ ? 20000
-		: 50000;
+	normalized_rate = rate <= 0 ? 0 :
+			  reg_val == LIS2MDL_ODR_10HZ ? 10000 :
+			  reg_val == LIS2MDL_ODR_20HZ ? 20000 :
+							50000;
 
 	/*
 	 * If no change is needed just bail. Not doing so will require a reset
@@ -356,10 +350,9 @@ int lis2mdl_set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
 		init_mag_cal(cal);
 
 	if (normalized_rate > 0)
-		cal->batch_size = MAX(
-				MAG_CAL_MIN_BATCH_SIZE,
-				(normalized_rate * 1000) /
-					MAG_CAL_MIN_BATCH_WINDOW_US);
+		cal->batch_size = MAX(MAG_CAL_MIN_BATCH_SIZE,
+				      (normalized_rate * 1000) /
+					      MAG_CAL_MIN_BATCH_WINDOW_US);
 	else
 		cal->batch_size = 0;
 
diff --git a/driver/mag_lis2mdl.h b/driver/mag_lis2mdl.h
index bc823628b3..ea28137beb 100644
--- a/driver/mag_lis2mdl.h
+++ b/driver/mag_lis2mdl.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,45 +16,45 @@
  * 8-bit address is 0011110Wb where the last bit represents whether the
  * operation is a read or a write.
  */
-#define LIS2MDL_ADDR_FLAGS		0x1e
+#define LIS2MDL_ADDR_FLAGS 0x1e
 
-#define LIS2MDL_STARTUP_MS		10
+#define LIS2MDL_STARTUP_MS 10
 
 /* Registers */
-#define LIS2MDL_WHO_AM_I_REG		0x4f
-#define LIS2MDL_CFG_REG_A_ADDR		0x60
-#define LIS2MDL_INT_CTRL_REG		0x63
-#define LIS2MDL_STATUS_REG		0x67
-#define LIS2MDL_OUT_REG			0x68
-
-#define LIS2MDL_WHO_AM_I		0x40
-
-#define LIS2MDL_FLAG_TEMP_COMPENSATION	0x80
-#define LIS2MDL_FLAG_REBOOT		0x40
-#define LIS2MDL_FLAG_SW_RESET		0x20
-#define LIS2MDL_FLAG_LOW_POWER		0x10
-#define LIS2MDL_ODR_50HZ		0x08
-#define LIS2MDL_ODR_20HZ		0x04
-#define LIS2MDL_ODR_10HZ		0x00
-#define LIS2MDL_MODE_IDLE		0x03
-#define LIS2MDL_MODE_SINGLE		0x01
-#define LIS2MDL_MODE_CONT		0x00
-#define LIS2MDL_ODR_MODE_MASK		0x8f
-
-#define LIS2MDL_X_DIRTY			0x01
-#define LIS2MDL_Y_DIRTY			0x02
-#define LIS2MDL_Z_DIRTY			0x04
-#define LIS2MDL_XYZ_DIRTY		0x08
-#define LIS2MDL_XYZ_DIRTY_MASK		0x0f
-
-#define	LIS2DSL_RESOLUTION		16
+#define LIS2MDL_WHO_AM_I_REG 0x4f
+#define LIS2MDL_CFG_REG_A_ADDR 0x60
+#define LIS2MDL_INT_CTRL_REG 0x63
+#define LIS2MDL_STATUS_REG 0x67
+#define LIS2MDL_OUT_REG 0x68
+
+#define LIS2MDL_WHO_AM_I 0x40
+
+#define LIS2MDL_FLAG_TEMP_COMPENSATION 0x80
+#define LIS2MDL_FLAG_REBOOT 0x40
+#define LIS2MDL_FLAG_SW_RESET 0x20
+#define LIS2MDL_FLAG_LOW_POWER 0x10
+#define LIS2MDL_ODR_50HZ 0x08
+#define LIS2MDL_ODR_20HZ 0x04
+#define LIS2MDL_ODR_10HZ 0x00
+#define LIS2MDL_MODE_IDLE 0x03
+#define LIS2MDL_MODE_SINGLE 0x01
+#define LIS2MDL_MODE_CONT 0x00
+#define LIS2MDL_ODR_MODE_MASK 0x8f
+
+#define LIS2MDL_X_DIRTY 0x01
+#define LIS2MDL_Y_DIRTY 0x02
+#define LIS2MDL_Z_DIRTY 0x04
+#define LIS2MDL_XYZ_DIRTY 0x08
+#define LIS2MDL_XYZ_DIRTY_MASK 0x0f
+
+#define LIS2DSL_RESOLUTION 16
 /*
  * Maximum sensor data range (milligauss):
  * Spec is 1.5 mguass / LSB, so 0.15 uT / LSB.
  * Calibration code is set to 16LSB/ut, [0.0625 uT/LSB]
  * Apply a multiplier to change the unit
  */
-#define LIS2MDL_RATIO(_in) (((_in) * 24) / 10)
+#define LIS2MDL_RATIO(_in) (((_in)*24) / 10)
 
 struct lis2mdl_private_data {
 	/* lsm6dsm_data union requires cal be first element */
@@ -63,8 +63,8 @@ struct lis2mdl_private_data {
 	struct stprivate_data data;
 #endif
 #ifdef CONFIG_MAG_BMI_LIS2MDL
-	intv3_t          hn;   /* last sample for offset compensation */
-	int              hn_valid;
+	intv3_t hn; /* last sample for offset compensation */
+	int hn_valid;
 #endif
 };
 
@@ -75,15 +75,13 @@ struct lis2mdl_private_data {
 	(&(DOWNCAST(s->drv_data, struct lis2mdl_private_data, data)->cal))
 #endif
 
-
-#define LIS2MDL_ODR_MIN_VAL	10000
-#define LIS2MDL_ODR_MAX_VAL	50000
+#define LIS2MDL_ODR_MIN_VAL 10000
+#define LIS2MDL_ODR_MAX_VAL 50000
 #if (CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ <= LIS2MDL_ODR_MAX_VAL)
 #error "EC too slow for magnetometer"
 #endif
 
-void lis2mdl_normalize(const struct motion_sensor_t *s,
-		       intv3_t v,
+void lis2mdl_normalize(const struct motion_sensor_t *s, intv3_t v,
 		       uint8_t *data);
 
 extern const struct accelgyro_drv lis2mdl_drv;
diff --git a/driver/mcdp28x0.c b/driver/mcdp28x0.c
index bf44a6eaf8..1b56e6d53f 100644
--- a/driver/mcdp28x0.c
+++ b/driver/mcdp28x0.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -16,7 +16,7 @@
 #include "usart-stm32f0.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
 
 static uint8_t mcdp_inbuf[MCDP_INBUF_MAX];
 
@@ -35,27 +35,21 @@ static inline void print_buffer(uint8_t *buf, int cnt)
 	CPRINTF("\n");
 }
 #else
-static inline void print_buffer(uint8_t *buf, int cnt) {}
+static inline void print_buffer(uint8_t *buf, int cnt)
+{
+}
 #endif
 
 static struct usart_config const usart_mcdp;
 
-struct queue const usart_mcdp_rx_queue = QUEUE_DIRECT(MCDP_INBUF_MAX,
-						      uint8_t,
-						      usart_mcdp.producer,
-						      null_consumer);
-struct queue const usart_mcdp_tx_queue = QUEUE_DIRECT(MCDP_OUTBUF_MAX,
-						      uint8_t,
-						      null_producer,
-						      usart_mcdp.consumer);
-
-static struct usart_config const usart_mcdp = USART_CONFIG(CONFIG_MCDP28X0,
-							   usart_rx_interrupt,
-							   usart_tx_interrupt,
-							   115200,
-							   0,
-							   usart_mcdp_rx_queue,
-							   usart_mcdp_tx_queue);
+struct queue const usart_mcdp_rx_queue = QUEUE_DIRECT(
+	MCDP_INBUF_MAX, uint8_t, usart_mcdp.producer, null_consumer);
+struct queue const usart_mcdp_tx_queue = QUEUE_DIRECT(
+	MCDP_OUTBUF_MAX, uint8_t, null_producer, usart_mcdp.consumer);
+
+static struct usart_config const usart_mcdp =
+	USART_CONFIG(CONFIG_MCDP28X0, usart_rx_interrupt, usart_tx_interrupt,
+		     115200, 0, usart_mcdp_rx_queue, usart_mcdp_tx_queue);
 
 /**
  * Compute checksum.
@@ -131,7 +125,7 @@ static int rx_serial(uint8_t *msg, int cnt)
 
 	read = queue_remove_units(&usart_mcdp_rx_queue, msg, cnt);
 	while ((read < cnt) && retry) {
-		usleep(100*MSEC);
+		usleep(100 * MSEC);
 		read += queue_remove_units(&usart_mcdp_rx_queue, msg + read,
 					   cnt - read);
 		retry--;
@@ -143,7 +137,7 @@ static int rx_serial(uint8_t *msg, int cnt)
 	if (cnt > msg[0])
 		cnt = msg[0];
 
-	if (msg[cnt-1] != compute_checksum(0, msg, cnt-1))
+	if (msg[cnt - 1] != compute_checksum(0, msg, cnt - 1))
 		return MCDP_ERROR_CHKSUM;
 
 	if (read != cnt) {
@@ -176,9 +170,9 @@ void mcdp_disable(void)
 	usart_shutdown(&usart_mcdp);
 }
 
-int mcdp_get_info(struct mcdp_info  *info)
+int mcdp_get_info(struct mcdp_info *info)
 {
-	const uint8_t msg[2] = {MCDP_CMD_APPSTEST, 0x28};
+	const uint8_t msg[2] = { MCDP_CMD_APPSTEST, 0x28 };
 	int rv = tx_serial(msg, sizeof(msg));
 
 	if (rv)
@@ -233,8 +227,8 @@ static int mcdp_appstest(uint8_t cmd, int paramc, char **paramv)
 		msg[1] = i + 1;
 		msg[2] = (param >> 24) & 0xff;
 		msg[3] = (param >> 16) & 0xff;
-		msg[4] = (param >>  8) & 0xff;
-		msg[5] = (param >>  0) & 0xff;
+		msg[4] = (param >> 8) & 0xff;
+		msg[5] = (param >> 0) & 0xff;
 		rv = tx_serial(msg, sizeof(msg));
 		if (rv)
 			return rv;
@@ -261,7 +255,7 @@ static int mcdp_appstest(uint8_t cmd, int paramc, char **paramv)
 	return EC_SUCCESS;
 }
 
-int command_mcdp(int argc, char **argv)
+int command_mcdp(int argc, const char **argv)
 {
 	int rv = EC_SUCCESS;
 	char *e;
@@ -277,9 +271,8 @@ int command_mcdp(int argc, char **argv)
 			ccprintf("family:%04x chipid:%04x irom:%d.%d.%d "
 				 "fw:%d.%d.%d\n",
 				 MCDP_FAMILY(info.family),
-				 MCDP_CHIPID(info.chipid),
-				 info.irom.major, info.irom.minor,
-				 info.irom.build,
+				 MCDP_CHIPID(info.chipid), info.irom.major,
+				 info.irom.minor, info.irom.build,
 				 info.fw.major, info.fw.minor, info.fw.build);
 	} else if (!strncasecmp(argv[1], "devid", 4)) {
 		uint8_t dev_id = strtoi(argv[2], &e, 10);
@@ -309,6 +302,5 @@ int command_mcdp(int argc, char **argv)
 	return EC_SUCCESS;
 }
 DECLARE_CONSOLE_COMMAND(mcdp, command_mcdp,
-			"info|devid <id>|appstest <cmd> [<params>]",
-			"USB PD");
+			"info|devid <id>|appstest <cmd> [<params>]", "USB PD");
 #endif /* CONFIG_CMD_MCDP */
diff --git a/driver/mcdp28x0.h b/driver/mcdp28x0.h
index 4352a3899e..a35184600f 100644
--- a/driver/mcdp28x0.h
+++ b/driver/mcdp28x0.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,11 +11,11 @@
 #define MCDP_OUTBUF_MAX 16
 #define MCDP_INBUF_MAX 16
 
-#define MCDP_CMD_GETINFO       0x40
-#define MCDP_CMD_GETDEVID      0x30
-#define MCDP_CMD_APPSTEST      0x12
+#define MCDP_CMD_GETINFO 0x40
+#define MCDP_CMD_GETDEVID 0x30
+#define MCDP_CMD_APPSTEST 0x12
 #define MCDP_CMD_APPSTESTPARAM 0x11
-#define MCDP_CMD_ACK           0x0c
+#define MCDP_CMD_ACK 0x0c
 
 /* packet header (2 bytes: length + cmd) + data + footer (1byte: checksum) */
 #define MCDP_RSP_LEN(len) (len + 3)
@@ -48,6 +48,6 @@ void mcdp_disable(void);
  * @info pointer to mcdp_info structure
  * @return zero if success, error code otherwise.
  */
-int mcdp_get_info(struct mcdp_info  *info);
+int mcdp_get_info(struct mcdp_info *info);
 
 #endif
diff --git a/driver/mp2964.c b/driver/mp2964.c
index 21a23a8f4c..7e08d4f5ba 100644
--- a/driver/mp2964.c
+++ b/driver/mp2964.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,22 +11,18 @@
 #include "timer.h"
 #include "util.h"
 
-#define MP2964_STARTUP_WAIT_US		(50 * MSEC)
-#define MP2964_STORE_WAIT_US		(300 * MSEC)
-#define MP2964_RESTORE_WAIT_US		(2 * MSEC)
+#define MP2964_STARTUP_WAIT_US (50 * MSEC)
+#define MP2964_STORE_WAIT_US (300 * MSEC)
+#define MP2964_RESTORE_WAIT_US (2 * MSEC)
 
-enum reg_page {
-	REG_PAGE_0,
-	REG_PAGE_1,
-	REG_PAGE_COUNT
-};
+enum reg_page { REG_PAGE_0, REG_PAGE_1, REG_PAGE_COUNT };
 
 static int mp2964_write8(uint8_t reg, uint8_t value)
 {
 	const uint8_t tx[2] = { reg, value };
 
-	return i2c_xfer_unlocked(I2C_PORT_MP2964, I2C_ADDR_MP2964_FLAGS,
-				 tx, sizeof(tx), NULL, 0, I2C_XFER_SINGLE);
+	return i2c_xfer_unlocked(I2C_PORT_MP2964, I2C_ADDR_MP2964_FLAGS, tx,
+				 sizeof(tx), NULL, 0, I2C_XFER_SINGLE);
 }
 
 static void mp2964_read16(uint8_t reg, uint16_t *value)
@@ -34,8 +30,8 @@ static void mp2964_read16(uint8_t reg, uint16_t *value)
 	const uint8_t tx[1] = { reg };
 	uint8_t rx[2];
 
-	i2c_xfer_unlocked(I2C_PORT_MP2964, I2C_ADDR_MP2964_FLAGS,
-			  tx, sizeof(tx), rx, sizeof(rx), I2C_XFER_SINGLE);
+	i2c_xfer_unlocked(I2C_PORT_MP2964, I2C_ADDR_MP2964_FLAGS, tx,
+			  sizeof(tx), rx, sizeof(rx), I2C_XFER_SINGLE);
 	*value = (rx[1] << 8) | rx[0];
 }
 
@@ -43,8 +39,8 @@ static void mp2964_write16(uint8_t reg, uint16_t value)
 {
 	const uint8_t tx[3] = { reg, value & 0xff, value >> 8 };
 
-	i2c_xfer_unlocked(I2C_PORT_MP2964, I2C_ADDR_MP2964_FLAGS,
-			  tx, sizeof(tx), NULL, 0, I2C_XFER_SINGLE);
+	i2c_xfer_unlocked(I2C_PORT_MP2964, I2C_ADDR_MP2964_FLAGS, tx,
+			  sizeof(tx), NULL, 0, I2C_XFER_SINGLE);
 }
 
 static int mp2964_select_page(enum reg_page page)
@@ -92,15 +88,15 @@ static int mp2964_store_user_all(void)
 
 	ccprintf("%s: updating persistent settings\n", __func__);
 
-	status = i2c_xfer_unlocked(I2C_PORT_MP2964, I2C_ADDR_MP2964_FLAGS,
-				   &wr, sizeof(wr), NULL, 0, I2C_XFER_SINGLE);
+	status = i2c_xfer_unlocked(I2C_PORT_MP2964, I2C_ADDR_MP2964_FLAGS, &wr,
+				   sizeof(wr), NULL, 0, I2C_XFER_SINGLE);
 	if (status != EC_SUCCESS)
 		return status;
 
 	usleep(MP2964_STORE_WAIT_US);
 
-	status = i2c_xfer_unlocked(I2C_PORT_MP2964, I2C_ADDR_MP2964_FLAGS,
-				   &rd, sizeof(rd), NULL, 0, I2C_XFER_SINGLE);
+	status = i2c_xfer_unlocked(I2C_PORT_MP2964, I2C_ADDR_MP2964_FLAGS, &rd,
+				   sizeof(rd), NULL, 0, I2C_XFER_SINGLE);
 	if (status != EC_SUCCESS)
 		return status;
 
@@ -110,8 +106,7 @@ static int mp2964_store_user_all(void)
 }
 
 static void mp2964_patch_rail(enum reg_page page,
-			      const struct mp2964_reg_val *page_vals,
-			      int count,
+			      const struct mp2964_reg_val *page_vals, int count,
 			      int *delta)
 {
 	if (mp2964_select_page(page) != EC_SUCCESS)
diff --git a/driver/mp2964.h b/driver/mp2964.h
index f424887567..228cae8d5b 100644
--- a/driver/mp2964.h
+++ b/driver/mp2964.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,33 +6,33 @@
 #ifndef __CROS_EC_PMIC_MP2964_H
 #define __CROS_EC_PMIC_MP2964_H
 
-#define MP2964_PAGE			0x00
-#define MP2964_STORE_USER_ALL		0x15
-#define MP2964_RESTORE_USER_ALL		0x16
-#define MP2964_MFR_VOUT_TRIM		0x22
-#define MP2964_MFR_PHASE_NUM		0x29
-#define MP2964_MFR_IMON_SNS_OFFS	0x2c
-#define MP2964_IOUT_CAL_GAIN_SET	0x38
-#define MP2964_MFR_TRANS_FAST		0x3d
-#define MP2964_MFR_ALT_SET		0x3f
-#define MP2964_MFR_CONFIG2		0x48
-#define MP2964_MFR_SLOPE_SR_DCM		0x4e
-#define MP2964_MFR_ICC_MAX_SET		0x53
-#define MP2964_MFR_OCP_OVP_DAC_LIMIT	0x60
-#define MP2964_MFR_OCP_SET		0x62
-#define MP2964_PRODUCT_DATA_CODE	0x93
-#define MP2964_LOT_CODE_VR		0x94
-#define MP2964_MFR_PSI_TRIM4		0xb0
-#define MP2964_MFR_PSI_TRIM1		0xb1
-#define MP2964_MFR_PSI_TRIM3		0xb3
-#define MP2964_MFR_SLOPE_CNT_2P		0xd4
-#define MP2964_MFR_SLOPE_CNT_5P		0xe0
-#define MP2964_MFR_IMON_SVID1		0xe8
-#define MP2964_MFR_IMON_SVID2		0xe9
-#define MP2964_MFR_IMON_SVID3		0xea
-#define MP2964_MFR_IMON_SVID4		0xeb
-#define MP2964_MFR_IMON_SVID5		0xef
-#define MP2964_MFR_IMON_SVID6		0xf0
+#define MP2964_PAGE 0x00
+#define MP2964_STORE_USER_ALL 0x15
+#define MP2964_RESTORE_USER_ALL 0x16
+#define MP2964_MFR_VOUT_TRIM 0x22
+#define MP2964_MFR_PHASE_NUM 0x29
+#define MP2964_MFR_IMON_SNS_OFFS 0x2c
+#define MP2964_IOUT_CAL_GAIN_SET 0x38
+#define MP2964_MFR_TRANS_FAST 0x3d
+#define MP2964_MFR_ALT_SET 0x3f
+#define MP2964_MFR_CONFIG2 0x48
+#define MP2964_MFR_SLOPE_SR_DCM 0x4e
+#define MP2964_MFR_ICC_MAX_SET 0x53
+#define MP2964_MFR_OCP_OVP_DAC_LIMIT 0x60
+#define MP2964_MFR_OCP_SET 0x62
+#define MP2964_PRODUCT_DATA_CODE 0x93
+#define MP2964_LOT_CODE_VR 0x94
+#define MP2964_MFR_PSI_TRIM4 0xb0
+#define MP2964_MFR_PSI_TRIM1 0xb1
+#define MP2964_MFR_PSI_TRIM3 0xb3
+#define MP2964_MFR_SLOPE_CNT_2P 0xd4
+#define MP2964_MFR_SLOPE_CNT_5P 0xe0
+#define MP2964_MFR_IMON_SVID1 0xe8
+#define MP2964_MFR_IMON_SVID2 0xe9
+#define MP2964_MFR_IMON_SVID3 0xea
+#define MP2964_MFR_IMON_SVID4 0xeb
+#define MP2964_MFR_IMON_SVID5 0xef
+#define MP2964_MFR_IMON_SVID6 0xf0
 
 struct mp2964_reg_val {
 	uint8_t reg;
diff --git a/driver/mp4245.c b/driver/mp4245.c
index 60df5affaf..a78cfbd068 100644
--- a/driver/mp4245.c
+++ b/driver/mp4245.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,7 +11,6 @@
 #include "mp4245.h"
 #include "util.h"
 
-
 static int mp4245_reg16_write(int offset, int data)
 {
 	return i2c_write16(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS, offset,
@@ -29,8 +28,8 @@ int mp4245_set_voltage_out(int desired_mv)
 	 *
 	 * VOUT_COMMAND = (Vdes (mV) * 1024 / 1000) / 1024
 	 */
-	vout = (desired_mv * MP4245_VOUT_FROM_MV + (MP4245_VOUT_1V >> 1))
-		/ MP4245_VOUT_1V;
+	vout = (desired_mv * MP4245_VOUT_FROM_MV + (MP4245_VOUT_1V >> 1)) /
+	       MP4245_VOUT_1V;
 
 	return mp4245_reg16_write(MP4245_CMD_VOUT_COMMAND, vout);
 }
@@ -50,7 +49,7 @@ int mp4245_votlage_out_enable(int enable)
 	int cmd_val = enable ? MP4245_CMD_OPERATION_ON : 0;
 
 	return i2c_write8(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS,
-			MP4245_CMD_OPERATION, cmd_val);
+			  MP4245_CMD_OPERATION, cmd_val);
 }
 
 int mp3245_get_vbus(int *mv, int *ma)
@@ -61,9 +60,9 @@ int mp3245_get_vbus(int *mv, int *ma)
 
 	/* Get Vbus/Ibus raw measurements */
 	rv = i2c_read16(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS,
-		   MP4245_CMD_READ_VOUT, &vbus);
+			MP4245_CMD_READ_VOUT, &vbus);
 	rv |= i2c_read16(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS,
-		  MP4245_CMD_READ_IOUT, &ibus);
+			 MP4245_CMD_READ_IOUT, &ibus);
 
 	if (rv == EC_SUCCESS) {
 		/* Convert Vbus/Ibus to mV/mA */
@@ -82,34 +81,21 @@ struct mp4245_info {
 	uint8_t len;
 };
 
-static struct mp4245_info  mp4245_cmds[] = {
-	{MP4245_CMD_OPERATION,          1},
-	{MP4245_CMD_CLEAR_FAULTS,       1},
-	{MP4245_CMD_WRITE_PROTECT,      1},
-	{MP4245_CMD_STORE_USER_ALL,     1},
-	{MP4245_CMD_RESTORE_USER_ALL,   1},
-	{MP4245_CMD_VOUT_MODE,          1},
-	{MP4245_CMD_VOUT_COMMAND,       2},
-	{MP4245_CMD_VOUT_SCALE_LOOP,    2},
-	{MP4245_CMD_STATUS_BYTE,        1},
-	{MP4245_CMD_STATUS_WORD,        2},
-	{MP4245_CMD_STATUS_VOUT,        1},
-	{MP4245_CMD_STATUS_INPUT,       1},
-	{MP4245_CMD_STATUS_TEMP,        1},
-	{MP4245_CMD_STATUS_CML,         1},
-	{MP4245_CMD_READ_VIN,           2},
-	{MP4245_CMD_READ_VOUT,          2},
-	{MP4245_CMD_READ_IOUT,          2},
-	{MP4245_CMD_READ_TEMP,          2},
-	{MP4245_CMD_MFR_MODE_CTRL,      1},
-	{MP4245_CMD_MFR_CURRENT_LIM,    1},
-	{MP4245_CMD_MFR_LINE_DROP,      1},
-	{MP4245_CMD_MFR_OT_FAULT_LIM,   1},
-	{MP4245_CMD_MFR_OT_WARN_LIM,    1},
-	{MP4245_CMD_MFR_CRC_ERROR,      1},
-	{MP4245_CMD_MFF_MTP_CFG_CODE,   1},
-	{MP4245_CMD_MFR_MTP_REV_NUM,    1},
-	{MP4245_CMD_MFR_STATUS_MASK,    1},
+static struct mp4245_info mp4245_cmds[] = {
+	{ MP4245_CMD_OPERATION, 1 },	    { MP4245_CMD_CLEAR_FAULTS, 1 },
+	{ MP4245_CMD_WRITE_PROTECT, 1 },    { MP4245_CMD_STORE_USER_ALL, 1 },
+	{ MP4245_CMD_RESTORE_USER_ALL, 1 }, { MP4245_CMD_VOUT_MODE, 1 },
+	{ MP4245_CMD_VOUT_COMMAND, 2 },	    { MP4245_CMD_VOUT_SCALE_LOOP, 2 },
+	{ MP4245_CMD_STATUS_BYTE, 1 },	    { MP4245_CMD_STATUS_WORD, 2 },
+	{ MP4245_CMD_STATUS_VOUT, 1 },	    { MP4245_CMD_STATUS_INPUT, 1 },
+	{ MP4245_CMD_STATUS_TEMP, 1 },	    { MP4245_CMD_STATUS_CML, 1 },
+	{ MP4245_CMD_READ_VIN, 2 },	    { MP4245_CMD_READ_VOUT, 2 },
+	{ MP4245_CMD_READ_IOUT, 2 },	    { MP4245_CMD_READ_TEMP, 2 },
+	{ MP4245_CMD_MFR_MODE_CTRL, 1 },    { MP4245_CMD_MFR_CURRENT_LIM, 1 },
+	{ MP4245_CMD_MFR_LINE_DROP, 1 },    { MP4245_CMD_MFR_OT_FAULT_LIM, 1 },
+	{ MP4245_CMD_MFR_OT_WARN_LIM, 1 },  { MP4245_CMD_MFR_CRC_ERROR, 1 },
+	{ MP4245_CMD_MFF_MTP_CFG_CODE, 1 }, { MP4245_CMD_MFR_MTP_REV_NUM, 1 },
+	{ MP4245_CMD_MFR_STATUS_MASK, 1 },
 };
 
 static void mp4245_dump_reg(void)
@@ -124,7 +110,7 @@ static void mp4245_dump_reg(void)
 				       mp4245_cmds[i].cmd, &val);
 		} else {
 			rv = i2c_read16(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS,
-				       mp4245_cmds[i].cmd, &val);
+					mp4245_cmds[i].cmd, &val);
 		}
 
 		if (!rv)
@@ -142,23 +128,23 @@ void mp4245_get_status(void)
 	int vout;
 
 	/* Get Operation register */
-	i2c_read8(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS,
-		  MP4245_CMD_OPERATION, &on);
+	i2c_read8(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS, MP4245_CMD_OPERATION,
+		  &on);
 	/* Vbus on/off is bit 7 */
 	on >>= 7;
 
 	/* Get status word */
 	i2c_read16(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS,
-		  MP4245_CMD_STATUS_WORD, &status);
+		   MP4245_CMD_STATUS_WORD, &status);
 
 	/* Get Vbus measurement */
-	i2c_read16(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS,
-		   MP4245_CMD_READ_VOUT, &vbus);
+	i2c_read16(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS, MP4245_CMD_READ_VOUT,
+		   &vbus);
 	vbus = MP4245_VOUT_TO_MV(vbus);
 
 	/* Get Ibus measurement */
-	i2c_read16(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS,
-		  MP4245_CMD_READ_IOUT, &ibus);
+	i2c_read16(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS, MP4245_CMD_READ_IOUT,
+		   &ibus);
 	ibus = MP4245_IOUT_TO_MA(ibus);
 
 	/* Get Vout command (sets Vbus level) */
@@ -168,7 +154,7 @@ void mp4245_get_status(void)
 
 	/* Get Input current limit */
 	i2c_read8(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS,
-		   MP4245_CMD_MFR_CURRENT_LIM, &ilim);
+		  MP4245_CMD_MFR_CURRENT_LIM, &ilim);
 	ilim *= MP4245_ILIM_STEP_MA;
 
 	ccprintf("mp4245 Vbus %s:\n", on ? "On" : "Off");
@@ -177,7 +163,7 @@ void mp4245_get_status(void)
 	ccprintf("\tIlim   = %d mA, Ibus = %d mA\n", ilim, ibus);
 }
 
-static int command_mp4245(int argc, char **argv)
+static int command_mp4245(int argc, const char **argv)
 {
 	char *e;
 	int val;
@@ -208,6 +194,5 @@ static int command_mp4245(int argc, char **argv)
 	}
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(mp4245, command_mp4245,
-			"<info|dump|vbus|ilim>",
+DECLARE_CONSOLE_COMMAND(mp4245, command_mp4245, "<info|dump|vbus|ilim>",
 			"Turn on/off|set vbus.");
diff --git a/driver/mp4245.h b/driver/mp4245.h
index b453ad2076..64fc3e9bc1 100644
--- a/driver/mp4245.h
+++ b/driver/mp4245.h
@@ -1,66 +1,64 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 /* MPS MP4245 Buck-Boost converter driver definitions */
 
 /* I2C addresses */
-#define MP4245_I2C_ADDR_0_FLAGS 0x61  /* R1 -> GND */
-#define MP4245_I2C_ADDR_1_FLAGS 0x62  /* R1 -> 15.0k */
-#define MP4245_I2C_ADDR_2_FLAGS 0x63  /* R1 -> 25.5k */
-#define MP4245_I2C_ADDR_3_FLAGS 0x64  /* R1 -> 35.7k */
-#define MP4245_I2C_ADDR_4_FLAGS 0x65  /* R1 -> 45.3k */
-#define MP4245_I2C_ADDR_5_FLAGS 0x66  /* R1 -> 56.0k */
-#define MP4245_I2C_ADDR_6_FLAGS 0x67  /* R1 -> VCC */
-
+#define MP4245_I2C_ADDR_0_FLAGS 0x61 /* R1 -> GND */
+#define MP4245_I2C_ADDR_1_FLAGS 0x62 /* R1 -> 15.0k */
+#define MP4245_I2C_ADDR_2_FLAGS 0x63 /* R1 -> 25.5k */
+#define MP4245_I2C_ADDR_3_FLAGS 0x64 /* R1 -> 35.7k */
+#define MP4245_I2C_ADDR_4_FLAGS 0x65 /* R1 -> 45.3k */
+#define MP4245_I2C_ADDR_5_FLAGS 0x66 /* R1 -> 56.0k */
+#define MP4245_I2C_ADDR_6_FLAGS 0x67 /* R1 -> VCC */
 
 /* MP4245 CMD Offsets */
-#define MP4245_CMD_OPERATION         0x01
-#define MP4245_CMD_CLEAR_FAULTS      0x03
-#define MP4245_CMD_WRITE_PROTECT     0x10
-#define MP4245_CMD_STORE_USER_ALL    0x15
-#define MP4245_CMD_RESTORE_USER_ALL  0x16
-#define MP4245_CMD_VOUT_MODE         0x20
-#define MP4245_CMD_VOUT_COMMAND      0x21
-#define MP4245_CMD_VOUT_SCALE_LOOP   0x29
-#define MP4245_CMD_STATUS_BYTE       0x78
-#define MP4245_CMD_STATUS_WORD       0x79
-#define MP4245_CMD_STATUS_VOUT       0x7A
-#define MP4245_CMD_STATUS_INPUT      0x7C
-#define MP4245_CMD_STATUS_TEMP       0x7D
-#define MP4245_CMD_STATUS_CML        0x7E
-#define MP4245_CMD_READ_VIN          0x88
-#define MP4245_CMD_READ_VOUT         0x8B
-#define MP4245_CMD_READ_IOUT         0x8C
-#define MP4245_CMD_READ_TEMP         0x8D
-#define MP4245_CMD_MFR_MODE_CTRL     0xD0
-#define MP4245_CMD_MFR_CURRENT_LIM   0xD1
-#define MP4245_CMD_MFR_LINE_DROP     0xD2
-#define MP4245_CMD_MFR_OT_FAULT_LIM  0xD3
-#define MP4245_CMD_MFR_OT_WARN_LIM   0xD4
-#define MP4245_CMD_MFR_CRC_ERROR     0xD5
-#define MP4245_CMD_MFF_MTP_CFG_CODE  0xD6
-#define MP4245_CMD_MFR_MTP_REV_NUM   0xD7
-#define MP4245_CMD_MFR_STATUS_MASK   0xD8
-
-#define MP4245_CMD_OPERATION_ON      BIT(7)
+#define MP4245_CMD_OPERATION 0x01
+#define MP4245_CMD_CLEAR_FAULTS 0x03
+#define MP4245_CMD_WRITE_PROTECT 0x10
+#define MP4245_CMD_STORE_USER_ALL 0x15
+#define MP4245_CMD_RESTORE_USER_ALL 0x16
+#define MP4245_CMD_VOUT_MODE 0x20
+#define MP4245_CMD_VOUT_COMMAND 0x21
+#define MP4245_CMD_VOUT_SCALE_LOOP 0x29
+#define MP4245_CMD_STATUS_BYTE 0x78
+#define MP4245_CMD_STATUS_WORD 0x79
+#define MP4245_CMD_STATUS_VOUT 0x7A
+#define MP4245_CMD_STATUS_INPUT 0x7C
+#define MP4245_CMD_STATUS_TEMP 0x7D
+#define MP4245_CMD_STATUS_CML 0x7E
+#define MP4245_CMD_READ_VIN 0x88
+#define MP4245_CMD_READ_VOUT 0x8B
+#define MP4245_CMD_READ_IOUT 0x8C
+#define MP4245_CMD_READ_TEMP 0x8D
+#define MP4245_CMD_MFR_MODE_CTRL 0xD0
+#define MP4245_CMD_MFR_CURRENT_LIM 0xD1
+#define MP4245_CMD_MFR_LINE_DROP 0xD2
+#define MP4245_CMD_MFR_OT_FAULT_LIM 0xD3
+#define MP4245_CMD_MFR_OT_WARN_LIM 0xD4
+#define MP4245_CMD_MFR_CRC_ERROR 0xD5
+#define MP4245_CMD_MFF_MTP_CFG_CODE 0xD6
+#define MP4245_CMD_MFR_MTP_REV_NUM 0xD7
+#define MP4245_CMD_MFR_STATUS_MASK 0xD8
 
-#define MP4245_VOUT_1V               BIT(10)
-#define MP4245_VOUT_FROM_MV          (MP4245_VOUT_1V * MP4245_VOUT_1V / 1000)
-#define MP4245_VOUT_TO_MV(v)         ((v * 1000) / MP4245_VOUT_1V)
-#define MP4245_IOUT_TO_MA(i)         (((i & 0x7ff) * 1000) / BIT(6))
-#define MP4245_ILIM_STEP_MA          50
-#define MP4245_VOUT_5V_DELAY_MS      10
+#define MP4245_CMD_OPERATION_ON BIT(7)
 
+#define MP4245_VOUT_1V BIT(10)
+#define MP4245_VOUT_FROM_MV (MP4245_VOUT_1V * MP4245_VOUT_1V / 1000)
+#define MP4245_VOUT_TO_MV(v) ((v * 1000) / MP4245_VOUT_1V)
+#define MP4245_IOUT_TO_MA(i) (((i & 0x7ff) * 1000) / BIT(6))
+#define MP4245_ILIM_STEP_MA 50
+#define MP4245_VOUT_5V_DELAY_MS 10
 
-#define MP4245_MFR_STATUS_MASK_VOUT        BIT(7)
-#define MP4245_MFR_STATUS_MASK_IOUT        BIT(6)
-#define MP4245_MFR_STATUS_MASK_INPUT       BIT(5)
-#define MP4245_MFR_STATUS_MASK_TEMP        BIT(4)
-#define MP4245_MFR_STATUS_MASK_PG_STATUS   BIT(3)
+#define MP4245_MFR_STATUS_MASK_VOUT BIT(7)
+#define MP4245_MFR_STATUS_MASK_IOUT BIT(6)
+#define MP4245_MFR_STATUS_MASK_INPUT BIT(5)
+#define MP4245_MFR_STATUS_MASK_TEMP BIT(4)
+#define MP4245_MFR_STATUS_MASK_PG_STATUS BIT(3)
 #define MP4245_MFR_STATUS_MASK_PG_ALT_EDGE BIT(2)
-#define MP4245_MFR_STATUS_MASK_OTHER       BIT(1)
-#define MP4245_MFR_STATUS_MASK_UNKNOWN     BIT(0)
+#define MP4245_MFR_STATUS_MASK_OTHER BIT(1)
+#define MP4245_MFR_STATUS_MASK_UNKNOWN BIT(0)
 
 /**
  * MP4245 set output voltage level
diff --git a/driver/nfc/ctn730.c b/driver/nfc/ctn730.c
index 775149e659..090c140864 100644
--- a/driver/nfc/ctn730.c
+++ b/driver/nfc/ctn730.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,6 +10,7 @@
 #include "gpio.h"
 #include "i2c.h"
 #include "peripheral_charger.h"
+#include "printf.h"
 #include "timer.h"
 #include "util.h"
 #include "watchdog.h"
@@ -31,16 +32,15 @@ static const int _wake_up_delay_ms = 10;
 static const int _detection_interval_ms = 500;
 
 /* Buffer size for i2c read & write */
-#define CTN730_MESSAGE_BUFFER_SIZE	0x20
+#define CTN730_MESSAGE_BUFFER_SIZE 0x20
 
 /* This driver isn't compatible with big endian. */
-BUILD_ASSERT(__BYTE_ORDER__  == __ORDER_LITTLE_ENDIAN__);
+BUILD_ASSERT(__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__);
 
 #define CPRINTS(fmt, args...) cprints(CC_PCHG, "CTN730: " fmt, ##args)
 
 static const char *_text_instruction(uint8_t instruction)
 {
-	/* TODO: For normal build, use %pb and BINARY_VALUE(res->inst, 6) */
 	switch (instruction) {
 	case WLC_HOST_CTRL_RESET:
 		return "RESET";
@@ -158,8 +158,7 @@ static int _i2c_read(int i2c_port, uint8_t *in, int in_len)
 
 static void _print_header(const struct ctn730_msg *msg)
 {
-	CPRINTS("%s_%s",
-		_text_instruction(msg->instruction),
+	CPRINTS("%s_%s", _text_instruction(msg->instruction),
 		_text_message_type(msg->message_type));
 }
 
@@ -206,9 +205,9 @@ static int ctn730_init(struct pchg *ctx)
 	cmd->message_type = CTN730_MESSAGE_TYPE_COMMAND;
 	cmd->instruction = WLC_HOST_CTRL_RESET;
 	cmd->length = WLC_HOST_CTRL_RESET_CMD_SIZE;
-	cmd->payload[0] = ctx->mode == PCHG_MODE_NORMAL
-			? WLC_HOST_CTRL_RESET_CMD_MODE_NORMAL
-			: WLC_HOST_CTRL_RESET_CMD_MODE_DOWNLOAD;
+	cmd->payload[0] = ctx->mode == PCHG_MODE_NORMAL ?
+				  WLC_HOST_CTRL_RESET_CMD_MODE_NORMAL :
+				  WLC_HOST_CTRL_RESET_CMD_MODE_DOWNLOAD;
 
 	/* TODO: Run 1 sec timeout timer. */
 	rv = _send_command(ctx, cmd);
@@ -258,8 +257,13 @@ static int _process_payload_response(struct pchg *ctx, struct ctn730_msg *res)
 		int rv = _i2c_read(ctx->cfg->i2c_port, buf, len);
 		if (rv)
 			return rv;
-		if (IS_ENABLED(CTN730_DEBUG))
-			CPRINTS("Payload: %ph", HEX_BUF(buf, len));
+		if (IS_ENABLED(CTN730_DEBUG)) {
+			char str_buf[hex_str_buf_size(len)];
+
+			snprintf_hex_buffer(str_buf, sizeof(str_buf),
+					    HEX_BUF(buf, len));
+			CPRINTS("Payload: %s", str_buf);
+		}
 	}
 
 	ctx->event = PCHG_EVENT_NONE;
@@ -359,8 +363,13 @@ static int _process_payload_event(struct pchg *ctx, struct ctn730_msg *res)
 		int rv = _i2c_read(ctx->cfg->i2c_port, buf, len);
 		if (rv)
 			return rv;
-		if (IS_ENABLED(CTN730_DEBUG))
-			CPRINTS("Payload: %ph", HEX_BUF(buf, len));
+		if (IS_ENABLED(CTN730_DEBUG)) {
+			char str_buf[hex_str_buf_size(len)];
+
+			snprintf_hex_buffer(str_buf, sizeof(str_buf),
+					    HEX_BUF(buf, len));
+			CPRINTS("Payload: %s", str_buf);
+		}
 	}
 
 	ctx->event = PCHG_EVENT_NONE;
@@ -510,8 +519,8 @@ static int ctn730_get_soc(struct pchg *ctx)
 
 static int ctn730_update_open(struct pchg *ctx)
 {
-	uint8_t buf[sizeof(struct ctn730_msg)
-		    + WLC_HOST_CTRL_DL_OPEN_SESSION_CMD_SIZE];
+	uint8_t buf[sizeof(struct ctn730_msg) +
+		    WLC_HOST_CTRL_DL_OPEN_SESSION_CMD_SIZE];
 	struct ctn730_msg *cmd = (void *)buf;
 	uint32_t version = ctx->update.version;
 	int rv;
@@ -531,16 +540,16 @@ static int ctn730_update_open(struct pchg *ctx)
 
 static int ctn730_update_write(struct pchg *ctx)
 {
-	uint8_t buf[sizeof(struct ctn730_msg)
-		    + WLC_HOST_CTRL_DL_WRITE_FLASH_CMD_SIZE];
+	uint8_t buf[sizeof(struct ctn730_msg) +
+		    WLC_HOST_CTRL_DL_WRITE_FLASH_CMD_SIZE];
 	struct ctn730_msg *cmd = (void *)buf;
 	uint32_t *a = (void *)cmd->payload;
 	uint8_t *d = (void *)&cmd->payload[CTN730_FLASH_ADDR_SIZE];
 	int rv;
 
 	/* Address is 3 bytes. FW size must be a multiple of 128 bytes. */
-	if (ctx->update.addr & GENMASK(31, 24)
-		|| ctx->update.size != WLC_HOST_CTRL_DL_WRITE_FLASH_BLOCK_SIZE)
+	if (ctx->update.addr & GENMASK(31, 24) ||
+	    ctx->update.size != WLC_HOST_CTRL_DL_WRITE_FLASH_BLOCK_SIZE)
 		return EC_ERROR_INVAL;
 
 	cmd->message_type = CTN730_MESSAGE_TYPE_COMMAND;
@@ -563,8 +572,8 @@ static int ctn730_update_write(struct pchg *ctx)
 
 static int ctn730_update_close(struct pchg *ctx)
 {
-	uint8_t buf[sizeof(struct ctn730_msg)
-		    + WLC_HOST_CTRL_DL_COMMIT_SESSION_CMD_SIZE];
+	uint8_t buf[sizeof(struct ctn730_msg) +
+		    WLC_HOST_CTRL_DL_COMMIT_SESSION_CMD_SIZE];
 	struct ctn730_msg *cmd = (void *)buf;
 	uint32_t *crc32 = (void *)cmd->payload;
 	int rv;
@@ -654,7 +663,7 @@ const struct pchg_drv ctn730_drv = {
 	.update_close = ctn730_update_close,
 };
 
-static int cc_ctn730(int argc, char **argv)
+static int cc_ctn730(int argc, const char **argv)
 {
 	int port;
 	char *end;
diff --git a/driver/nfc/ctn730.h b/driver/nfc/ctn730.h
index 0195b36a6d..6911d4fa5e 100644
--- a/driver/nfc/ctn730.h
+++ b/driver/nfc/ctn730.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,109 +6,109 @@
 #ifndef __CROS_EC_CTN730_H
 #define __CROS_EC_CTN730_H
 
-#define CTN730_I2C_ADDR			0x28
+#define CTN730_I2C_ADDR 0x28
 
 /* Size of flash address space in bytes */
-#define CTN730_FLASH_ADDR_SIZE		3
+#define CTN730_FLASH_ADDR_SIZE 3
 
 /* All commands are guaranteed to finish within 1 second. */
-#define CTN730_COMMAND_TIME_OUT		(1 * SECOND)
+#define CTN730_COMMAND_TIME_OUT (1 * SECOND)
 
 /* Message Types */
-#define CTN730_MESSAGE_TYPE_COMMAND	0b00
-#define CTN730_MESSAGE_TYPE_RESPONSE	0b01
-#define CTN730_MESSAGE_TYPE_EVENT	0b10
+#define CTN730_MESSAGE_TYPE_COMMAND 0b00
+#define CTN730_MESSAGE_TYPE_RESPONSE 0b01
+#define CTN730_MESSAGE_TYPE_EVENT 0b10
 
 /* Instruction Codes */
-#define WLC_HOST_CTRL_RESET			0b000000
-#define WLC_HOST_CTRL_DL_OPEN_SESSION		0b000011
-#define WLC_HOST_CTRL_DL_COMMIT_SESSION		0b000100
-#define WLC_HOST_CTRL_DL_WRITE_FLASH		0b000101
-#define WLC_HOST_CTRL_DUMP_STATUS		0b001100
-#define WLC_HOST_CTRL_GENERIC_ERROR		0b001111
-#define WLC_HOST_CTRL_BIST			0b000110
-#define WLC_CHG_CTRL_ENABLE			0b010000
-#define WLC_CHG_CTRL_DISABLE			0b010001
-#define WLC_CHG_CTRL_DEVICE_STATE		0b010010
-#define WLC_CHG_CTRL_CHARGING_STATE		0b010100
-#define WLC_CHG_CTRL_CHARGING_INFO		0b010101
+#define WLC_HOST_CTRL_RESET 0b000000
+#define WLC_HOST_CTRL_DL_OPEN_SESSION 0b000011
+#define WLC_HOST_CTRL_DL_COMMIT_SESSION 0b000100
+#define WLC_HOST_CTRL_DL_WRITE_FLASH 0b000101
+#define WLC_HOST_CTRL_DUMP_STATUS 0b001100
+#define WLC_HOST_CTRL_GENERIC_ERROR 0b001111
+#define WLC_HOST_CTRL_BIST 0b000110
+#define WLC_CHG_CTRL_ENABLE 0b010000
+#define WLC_CHG_CTRL_DISABLE 0b010001
+#define WLC_CHG_CTRL_DEVICE_STATE 0b010010
+#define WLC_CHG_CTRL_CHARGING_STATE 0b010100
+#define WLC_CHG_CTRL_CHARGING_INFO 0b010101
 
 /* WLC_HOST_CTRL_RESET constants */
-#define WLC_HOST_CTRL_RESET_CMD_SIZE			1
-#define WLC_HOST_CTRL_RESET_RSP_SIZE			1
-#define WLC_HOST_CTRL_RESET_EVT_NORMAL_MODE		0x00
-#define WLC_HOST_CTRL_RESET_EVT_NORMAL_MODE_SIZE	3
-#define WLC_HOST_CTRL_RESET_EVT_DOWNLOAD_MODE		0x01
-#define WLC_HOST_CTRL_RESET_EVT_DOWNLOAD_MODE_SIZE	2
-#define WLC_HOST_CTRL_RESET_REASON_INTENDED		0x00
-#define WLC_HOST_CTRL_RESET_REASON_CORRUPTED		0x01
-#define WLC_HOST_CTRL_RESET_REASON_UNRECOVERABLE	0x02
-#define WLC_HOST_CTRL_RESET_CMD_MODE_NORMAL		0x00
-#define WLC_HOST_CTRL_RESET_CMD_MODE_DOWNLOAD		0x01
+#define WLC_HOST_CTRL_RESET_CMD_SIZE 1
+#define WLC_HOST_CTRL_RESET_RSP_SIZE 1
+#define WLC_HOST_CTRL_RESET_EVT_NORMAL_MODE 0x00
+#define WLC_HOST_CTRL_RESET_EVT_NORMAL_MODE_SIZE 3
+#define WLC_HOST_CTRL_RESET_EVT_DOWNLOAD_MODE 0x01
+#define WLC_HOST_CTRL_RESET_EVT_DOWNLOAD_MODE_SIZE 2
+#define WLC_HOST_CTRL_RESET_REASON_INTENDED 0x00
+#define WLC_HOST_CTRL_RESET_REASON_CORRUPTED 0x01
+#define WLC_HOST_CTRL_RESET_REASON_UNRECOVERABLE 0x02
+#define WLC_HOST_CTRL_RESET_CMD_MODE_NORMAL 0x00
+#define WLC_HOST_CTRL_RESET_CMD_MODE_DOWNLOAD 0x01
 #define WLC_HOST_CTRL_RESET_EVT_MIN_SIZE \
 	WLC_HOST_CTRL_RESET_EVT_DOWNLOAD_MODE_SIZE
 
 /* WLC_HOST_CTRL_DL_* constants */
-#define WLC_HOST_CTRL_DL_OPEN_SESSION_CMD_SIZE		2
-#define WLC_HOST_CTRL_DL_OPEN_SESSION_RSP_SIZE		1
-#define WLC_HOST_CTRL_DL_WRITE_FLASH_BLOCK_SIZE		128
-#define WLC_HOST_CTRL_DL_WRITE_FLASH_CMD_SIZE		\
+#define WLC_HOST_CTRL_DL_OPEN_SESSION_CMD_SIZE 2
+#define WLC_HOST_CTRL_DL_OPEN_SESSION_RSP_SIZE 1
+#define WLC_HOST_CTRL_DL_WRITE_FLASH_BLOCK_SIZE 128
+#define WLC_HOST_CTRL_DL_WRITE_FLASH_CMD_SIZE \
 	(CTN730_FLASH_ADDR_SIZE + WLC_HOST_CTRL_DL_WRITE_FLASH_BLOCK_SIZE)
-#define WLC_HOST_CTRL_DL_WRITE_FLASH_RSP_SIZE		1
-#define WLC_HOST_CTRL_DL_COMMIT_SESSION_CMD_SIZE	4
-#define WLC_HOST_CTRL_DL_COMMIT_SESSION_RSP_SIZE	1
+#define WLC_HOST_CTRL_DL_WRITE_FLASH_RSP_SIZE 1
+#define WLC_HOST_CTRL_DL_COMMIT_SESSION_CMD_SIZE 4
+#define WLC_HOST_CTRL_DL_COMMIT_SESSION_RSP_SIZE 1
 
 /* WLC_CHG_CTRL_ENABLE constants */
-#define WLC_CHG_CTRL_ENABLE_CMD_SIZE		2
-#define WLC_CHG_CTRL_ENABLE_RSP_SIZE		1
+#define WLC_CHG_CTRL_ENABLE_CMD_SIZE 2
+#define WLC_CHG_CTRL_ENABLE_RSP_SIZE 1
 
 /* WLC_CHG_CTRL_DISABLE constants */
-#define WLC_CHG_CTRL_DISABLE_CMD_SIZE		0
-#define WLC_CHG_CTRL_DISABLE_RSP_SIZE		1
-#define WLC_CHG_CTRL_DISABLE_EVT_SIZE		1
+#define WLC_CHG_CTRL_DISABLE_CMD_SIZE 0
+#define WLC_CHG_CTRL_DISABLE_RSP_SIZE 1
+#define WLC_CHG_CTRL_DISABLE_EVT_SIZE 1
 
 /* WLC_CHG_CTRL_DEVICE_STATE constants */
-#define WLC_CHG_CTRL_DEVICE_STATE_DEVICE_DETECTED		0x00
-#define WLC_CHG_CTRL_DEVICE_STATE_DEVICE_DEACTIVATED		0x01
-#define WLC_CHG_CTRL_DEVICE_STATE_DEVICE_DEVICE_LOST		0x02
-#define WLC_CHG_CTRL_DEVICE_STATE_DEVICE_DEVICE_BAD_VERSION	0x03
-#define WLC_CHG_CTRL_DEVICE_STATE_DEVICE_DOCKED			0x04
-#define WLC_CHG_CTRL_DEVICE_STATE_DEVICE_UNDOCKED		0x05
-#define WLC_CHG_CTRL_DEVICE_STATE_EVT_SIZE_DETECTED		8
-#define WLC_CHG_CTRL_DEVICE_STATE_EVT_SIZE			1
+#define WLC_CHG_CTRL_DEVICE_STATE_DEVICE_DETECTED 0x00
+#define WLC_CHG_CTRL_DEVICE_STATE_DEVICE_DEACTIVATED 0x01
+#define WLC_CHG_CTRL_DEVICE_STATE_DEVICE_DEVICE_LOST 0x02
+#define WLC_CHG_CTRL_DEVICE_STATE_DEVICE_DEVICE_BAD_VERSION 0x03
+#define WLC_CHG_CTRL_DEVICE_STATE_DEVICE_DOCKED 0x04
+#define WLC_CHG_CTRL_DEVICE_STATE_DEVICE_UNDOCKED 0x05
+#define WLC_CHG_CTRL_DEVICE_STATE_EVT_SIZE_DETECTED 8
+#define WLC_CHG_CTRL_DEVICE_STATE_EVT_SIZE 1
 
 /* WLC_CHG_CTRL_CHARGING_STATE constants */
-#define WLC_CHG_CTRL_CHARGING_STATE_CHARGE_STARTED		0x00
-#define WLC_CHG_CTRL_CHARGING_STATE_CHARGE_ENDED		0x01
-#define WLC_CHG_CTRL_CHARGING_STATE_CHARGE_STOPPED		0x02
-#define WLC_CHG_CTRL_CHARGING_STATE_EVT_SIZE			1
+#define WLC_CHG_CTRL_CHARGING_STATE_CHARGE_STARTED 0x00
+#define WLC_CHG_CTRL_CHARGING_STATE_CHARGE_ENDED 0x01
+#define WLC_CHG_CTRL_CHARGING_STATE_CHARGE_STOPPED 0x02
+#define WLC_CHG_CTRL_CHARGING_STATE_EVT_SIZE 1
 
 /* WLC_HOST_CTRL_DUMP_STATUS constants */
-#define WLC_HOST_CTRL_DUMP_STATUS_CMD_SIZE	1
+#define WLC_HOST_CTRL_DUMP_STATUS_CMD_SIZE 1
 
 /* WLC_CHG_CTRL_CHARGING_INFO constants */
-#define WLC_CHG_CTRL_CHARGING_INFO_CMD_SIZE	0
-#define WLC_CHG_CTRL_CHARGING_INFO_RSP_SIZE	2
-#define WLC_CHG_CTRL_CHARGING_INFO_EVT_SIZE	5
+#define WLC_CHG_CTRL_CHARGING_INFO_CMD_SIZE 0
+#define WLC_CHG_CTRL_CHARGING_INFO_RSP_SIZE 2
+#define WLC_CHG_CTRL_CHARGING_INFO_EVT_SIZE 5
 
 /* Status Codes */
 enum wlc_host_status {
-	WLC_HOST_STATUS_OK				= 0x00,
-	WLC_HOST_STATUS_PARAMETER_ERROR			= 0x01,
-	WLC_HOST_STATUS_STATE_ERROR			= 0x02,
-	WLC_HOST_STATUS_VALUE_ERROR			= 0x03,
-	WLC_HOST_STATUS_REJECTED			= 0x04,
-	WLC_HOST_STATUS_RESOURCE_ERROR			= 0x10,
-	WLC_HOST_STATUS_TXLDO_ERROR			= 0x11,
-	WLC_HOST_STATUS_ANTENNA_SELECTION_ERROR		= 0x12,
-	WLC_HOST_STATUS_BIST_FAILED			= 0x20,
-	WLC_HOST_STATUS_BIST_NO_WLC_CAP			= 0x21,
-	WLC_HOST_STATUS_BIST_TXLDO_CURRENT_OVERFLOW	= 0x22,
-	WLC_HOST_STATUS_BIST_TXLDO_CURRENT_UNDERFLOW	= 0x23,
-	WLC_HOST_STATUS_FW_VERSION_ERROR		= 0x30,
-	WLC_HOST_STATUS_FW_VERIFICATION_ERROR		= 0x31,
-	WLC_HOST_STATUS_NTAG_BLOCK_PARAMETER_ERROR	= 0x32,
-	WLC_HOST_STATUS_NTAG_READ_ERROR			= 0x33,
+	WLC_HOST_STATUS_OK = 0x00,
+	WLC_HOST_STATUS_PARAMETER_ERROR = 0x01,
+	WLC_HOST_STATUS_STATE_ERROR = 0x02,
+	WLC_HOST_STATUS_VALUE_ERROR = 0x03,
+	WLC_HOST_STATUS_REJECTED = 0x04,
+	WLC_HOST_STATUS_RESOURCE_ERROR = 0x10,
+	WLC_HOST_STATUS_TXLDO_ERROR = 0x11,
+	WLC_HOST_STATUS_ANTENNA_SELECTION_ERROR = 0x12,
+	WLC_HOST_STATUS_BIST_FAILED = 0x20,
+	WLC_HOST_STATUS_BIST_NO_WLC_CAP = 0x21,
+	WLC_HOST_STATUS_BIST_TXLDO_CURRENT_OVERFLOW = 0x22,
+	WLC_HOST_STATUS_BIST_TXLDO_CURRENT_UNDERFLOW = 0x23,
+	WLC_HOST_STATUS_FW_VERSION_ERROR = 0x30,
+	WLC_HOST_STATUS_FW_VERIFICATION_ERROR = 0x31,
+	WLC_HOST_STATUS_NTAG_BLOCK_PARAMETER_ERROR = 0x32,
+	WLC_HOST_STATUS_NTAG_READ_ERROR = 0x33,
 };
 
 struct ctn730_msg {
@@ -118,4 +118,4 @@ struct ctn730_msg {
 	uint8_t payload[];
 } __packed;
 
-#endif  /* __CROS_EC_CTN730_H */
+#endif /* __CROS_EC_CTN730_H */
diff --git a/driver/nvidia_gpu.c b/driver/nvidia_gpu.c
new file mode 100644
index 0000000000..e9fbd156ac
--- /dev/null
+++ b/driver/nvidia_gpu.c
@@ -0,0 +1,161 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Nvidia GPU D-Notify driver
+ */
+
+#include <stddef.h>
+
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "nvidia_gpu.h"
+#include "throttle_ap.h"
+#include "timer.h"
+
+#define CPRINTS(fmt, args...) cprints(CC_GPU, "GPU: " fmt, ##args)
+#define CPRINTF(fmt, args...) cprintf(CC_GPU, "GPU: " fmt, ##args)
+
+test_export_static enum d_notify_level d_notify_level = D_NOTIFY_1;
+test_export_static bool policy_initialized = false;
+test_export_static const struct d_notify_policy *d_notify_policy = NULL;
+
+void nvidia_gpu_init_policy(const struct d_notify_policy *policy)
+{
+	if (policy) {
+		d_notify_policy = policy;
+		policy_initialized = true;
+	}
+}
+
+void nvidia_gpu_over_temp(int assert)
+{
+	uint8_t *memmap_gpu = (uint8_t *)host_get_memmap(EC_MEMMAP_GPU);
+
+	if (assert)
+		*memmap_gpu |= EC_MEMMAP_GPU_OVERT_BIT;
+	else
+		*memmap_gpu &= ~EC_MEMMAP_GPU_OVERT_BIT;
+
+	host_set_single_event(EC_HOST_EVENT_GPU);
+}
+
+static void set_d_notify_level(enum d_notify_level level)
+{
+	uint8_t *memmap_gpu = (uint8_t *)host_get_memmap(EC_MEMMAP_GPU);
+
+	if (level == d_notify_level)
+		return;
+
+	d_notify_level = level;
+	*memmap_gpu = (*memmap_gpu & ~EC_MEMMAP_GPU_D_NOTIFY_MASK) |
+		      d_notify_level;
+	host_set_single_event(EC_HOST_EVENT_GPU);
+	CPRINTS("Set D-notify level to D%c", ('1' + (int)d_notify_level));
+}
+
+static void evaluate_d_notify_level(void)
+{
+	enum d_notify_level lvl;
+	const struct d_notify_policy *policy = d_notify_policy;
+
+	/*
+	 * We don't need to care about 'transitioning to S0' because throttling
+	 * is unlikely required when the system is about to start.
+	 */
+	if (!chipset_in_state(CHIPSET_STATE_ON))
+		return;
+
+	if (!policy_initialized) {
+		CPRINTS("WARN: %s called before policies are set.", __func__);
+		return;
+	}
+
+	if (extpower_is_present()) {
+		const int watts = charge_manager_get_power_limit_uw() / 1000000;
+
+		for (lvl = D_NOTIFY_1; lvl <= D_NOTIFY_5; lvl++) {
+			if (policy[lvl].power_source != D_NOTIFY_AC &&
+			    policy[lvl].power_source != D_NOTIFY_AC_DC)
+				continue;
+
+			if (policy[lvl].power_source == D_NOTIFY_AC) {
+				if (watts >= policy[lvl].ac.min_charger_watts) {
+					set_d_notify_level(lvl);
+					break;
+				}
+			} else {
+				set_d_notify_level(lvl);
+				break;
+			}
+		}
+	} else {
+		const int soc = charge_get_percent();
+
+		for (lvl = D_NOTIFY_5; lvl >= D_NOTIFY_1; lvl--) {
+			if (policy[lvl].power_source == D_NOTIFY_DC) {
+				if (soc <= policy[lvl].dc.min_battery_soc) {
+					set_d_notify_level(lvl);
+					break;
+				}
+			} else if (policy[lvl].power_source == D_NOTIFY_AC_DC) {
+				set_d_notify_level(lvl);
+				break;
+			}
+		}
+	}
+}
+
+static void disable_gpu_acoff(void)
+{
+	gpio_set_level(GPIO_NVIDIA_GPU_ACOFF_ODL, 1);
+	evaluate_d_notify_level();
+}
+DECLARE_DEFERRED(disable_gpu_acoff);
+
+static void handle_battery_soc_change(void)
+{
+	evaluate_d_notify_level();
+}
+DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, handle_battery_soc_change,
+	     HOOK_PRIO_DEFAULT);
+
+/*
+ * This function enables and disables both hard and soft throttles. (Thus,
+ * <type> has no meaning.).
+ *
+ * When throttling, it hard-throttles the GPU and sets the D-level to D5. It
+ * also schedules a deferred call to disable the hard throttle. So, it's not
+ * necessary to call it for unthrottling.
+ *
+ * Currently, it's upto each board when this is called. For example, it can be
+ * called from board_set_active_charge_port since board_set_active_charge_port
+ * is called whenever (and prior to) active port or active supplier or both
+ * changes.
+ */
+void throttle_gpu(enum throttle_level level, enum throttle_type type, /* not
+									 used */
+		  enum throttle_sources source)
+{
+	if (level == THROTTLE_ON) {
+		/* Cancel pending deferred call. */
+		hook_call_deferred(&disable_gpu_acoff_data, -1);
+		/* Toggle hardware throttle immediately. */
+		gpio_set_level(GPIO_NVIDIA_GPU_ACOFF_ODL, 0);
+		/*
+		 * Switch to the lowest (D5) first then move up as the situation
+		 * improves.
+		 */
+		set_d_notify_level(D_NOTIFY_5);
+		hook_call_deferred(&disable_gpu_acoff_data,
+				   NVIDIA_GPU_ACOFF_DURATION);
+	} else {
+		disable_gpu_acoff();
+	}
+}
diff --git a/driver/nvidia_gpu.h b/driver/nvidia_gpu.h
new file mode 100644
index 0000000000..bfd1bba287
--- /dev/null
+++ b/driver/nvidia_gpu.h
@@ -0,0 +1,67 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Nvidia GPU D-Notify driver header file
+ */
+
+#ifndef DRIVER_NVIDIA_GPU_H
+#define DRIVER_NVIDIA_GPU_H
+
+#define NVIDIA_GPU_ACOFF_DURATION (100 * MSEC)
+
+enum d_notify_level {
+	D_NOTIFY_1 = 0,
+	D_NOTIFY_2,
+	D_NOTIFY_3,
+	D_NOTIFY_4,
+	D_NOTIFY_5,
+	D_NOTIFY_COUNT,
+};
+
+enum d_notify_policy_type {
+	/* High- or low-power A/C */
+	D_NOTIFY_AC,
+	/* Too low of A/C to still charge or DC with high battery SOC */
+	D_NOTIFY_AC_DC,
+	/* DC with medium or low battery SOC */
+	D_NOTIFY_DC,
+};
+
+struct d_notify_policy {
+	enum d_notify_policy_type power_source;
+	union {
+		struct {
+			unsigned int min_charger_watts;
+		} ac;
+		struct {
+			unsigned int min_battery_soc;
+		} dc;
+	};
+};
+
+#define AC_ATLEAST_W(W)                                                   \
+	{                                                                 \
+		.power_source = D_NOTIFY_AC, .ac.min_charger_watts = (W), \
+	}
+
+#define AC_DC                                   \
+	{                                       \
+		.power_source = D_NOTIFY_AC_DC, \
+	}
+
+#define DC_ATLEAST_SOC(S)                                               \
+	{                                                               \
+		.power_source = D_NOTIFY_DC, .dc.min_battery_soc = (S), \
+	}
+
+void nvidia_gpu_init_policy(const struct d_notify_policy *policies);
+
+/**
+ * Notify the host of assertion or deassertion of GPU over temperature.
+ *
+ * @param assert  True for assert. False for deassert.
+ */
+void nvidia_gpu_over_temp(int assert);
+
+#endif /* DRIVER_NVIDIA_GPU_H */
diff --git a/driver/pmic_bd99992gw.h b/driver/pmic_bd99992gw.h
index e00ea1d252..9229b62f48 100644
--- a/driver/pmic_bd99992gw.h
+++ b/driver/pmic_bd99992gw.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,22 +10,22 @@
 
 #include "temp_sensor/bd99992gw.h"
 
-#define BD99992GW_REG_PWRSRCINT		0x04
-#define BD99992GW_REG_RESETIRQ1		0x08
-#define BD99992GW_REG_PBCONFIG		0x14
-#define BD99992GW_REG_PWRSTAT1		0x16
-#define BD99992GW_REG_PWRSTAT2		0x17
-#define BD99992GW_REG_VCCIOCNT		0x30
-#define BD99992GW_REG_V5ADS3CNT		0x31
-#define BD99992GW_REG_V18ACNT		0x34
-#define BD99992GW_REG_V100ACNT		0x37
-#define BD99992GW_REG_V085ACNT		0x38
-#define BD99992GW_REG_VRMODECTRL	0x3b
-#define BD99992GW_REG_DISCHGCNT1	0x3c
-#define BD99992GW_REG_DISCHGCNT2	0x3d
-#define BD99992GW_REG_DISCHGCNT3	0x3e
-#define BD99992GW_REG_DISCHGCNT4	0x3f
-#define BD99992GW_REG_SDWNCTRL		0x49
-#define BD99992GW_SDWNCTRL_SWDN		BIT(0) /* SWDN mask */
+#define BD99992GW_REG_PWRSRCINT 0x04
+#define BD99992GW_REG_RESETIRQ1 0x08
+#define BD99992GW_REG_PBCONFIG 0x14
+#define BD99992GW_REG_PWRSTAT1 0x16
+#define BD99992GW_REG_PWRSTAT2 0x17
+#define BD99992GW_REG_VCCIOCNT 0x30
+#define BD99992GW_REG_V5ADS3CNT 0x31
+#define BD99992GW_REG_V18ACNT 0x34
+#define BD99992GW_REG_V100ACNT 0x37
+#define BD99992GW_REG_V085ACNT 0x38
+#define BD99992GW_REG_VRMODECTRL 0x3b
+#define BD99992GW_REG_DISCHGCNT1 0x3c
+#define BD99992GW_REG_DISCHGCNT2 0x3d
+#define BD99992GW_REG_DISCHGCNT3 0x3e
+#define BD99992GW_REG_DISCHGCNT4 0x3f
+#define BD99992GW_REG_SDWNCTRL 0x49
+#define BD99992GW_SDWNCTRL_SWDN BIT(0) /* SWDN mask */
 
-#endif  /* __CROS_EC_PMIC_BD99992GW_H */
+#endif /* __CROS_EC_PMIC_BD99992GW_H */
diff --git a/driver/pmic_tps650x30.h b/driver/pmic_tps650x30.h
index f03bef5f05..f346fba380 100644
--- a/driver/pmic_tps650x30.h
+++ b/driver/pmic_tps650x30.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -9,29 +9,29 @@
 #define __CROS_EC_PMIC_TPS650X30_H
 
 /* I2C interface */
-#define TPS650X30_I2C_ADDR1_FLAGS	0x30
-#define TPS650X30_I2C_ADDR2_FLAGS	0x32
-#define TPS650X30_I2C_ADDR3_FLAGS	0x34
+#define TPS650X30_I2C_ADDR1_FLAGS 0x30
+#define TPS650X30_I2C_ADDR2_FLAGS 0x32
+#define TPS650X30_I2C_ADDR3_FLAGS 0x34
 
 /* TPS650X30 registers */
-#define TPS650X30_REG_VENDORID		0x00
-#define TPS650X30_REG_PBCONFIG		0x14
-#define TPS650X30_REG_PGMASK1		0x18
-#define TPS650X30_REG_VCCIOCNT		0x30
-#define TPS650X30_REG_V5ADS3CNT		0x31
-#define TPS650X30_REG_V33ADSWCNT	0x32
-#define TPS650X30_REG_V18ACNT		0x34
-#define TPS650X30_REG_V1P2UCNT		0x36
-#define TPS650X30_REG_V100ACNT		0x37
-#define TPS650X30_REG_VRMODECTRL	0x3B
-#define TPS650X30_REG_DISCHCNT1		0x3C
-#define TPS650X30_REG_DISCHCNT2		0x3D
-#define TPS650X30_REG_DISCHCNT3		0x3E
-#define TPS650X30_REG_DISCHCNT4		0x3F
-#define TPS650X30_REG_PWFAULT_MASK1	0xE5
-#define TPS650X30_REG_PWFAULT_MASK2	0xE6
+#define TPS650X30_REG_VENDORID 0x00
+#define TPS650X30_REG_PBCONFIG 0x14
+#define TPS650X30_REG_PGMASK1 0x18
+#define TPS650X30_REG_VCCIOCNT 0x30
+#define TPS650X30_REG_V5ADS3CNT 0x31
+#define TPS650X30_REG_V33ADSWCNT 0x32
+#define TPS650X30_REG_V18ACNT 0x34
+#define TPS650X30_REG_V1P2UCNT 0x36
+#define TPS650X30_REG_V100ACNT 0x37
+#define TPS650X30_REG_VRMODECTRL 0x3B
+#define TPS650X30_REG_DISCHCNT1 0x3C
+#define TPS650X30_REG_DISCHCNT2 0x3D
+#define TPS650X30_REG_DISCHCNT3 0x3E
+#define TPS650X30_REG_DISCHCNT4 0x3F
+#define TPS650X30_REG_PWFAULT_MASK1 0xE5
+#define TPS650X30_REG_PWFAULT_MASK2 0xE6
 
 /* TPS650X30 register values */
-#define TPS650X30_VENDOR_ID		0x22
+#define TPS650X30_VENDOR_ID 0x22
 
-#endif	/* __CROS_EC_PMIC_TPS650X30_H */
+#endif /* __CROS_EC_PMIC_TPS650X30_H */
diff --git a/driver/ppc/aoz1380.c b/driver/ppc/aoz1380.c
index 726f626caf..27d55cab51 100644
--- a/driver/ppc/aoz1380.c
+++ b/driver/ppc/aoz1380.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,21 +14,21 @@
 #include "atomic.h"
 #include "common.h"
 #include "console.h"
-#include "aoz1380.h"
 #include "hooks.h"
+#include "ppc/aoz1380_public.h"
 #include "system.h"
 #include "tcpm/tcpm.h"
 #include "usb_pd.h"
 #include "usb_pd_tcpc.h"
 #include "usbc_ppc.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 static atomic_t irq_pending; /* Bitmask of ports signaling an interrupt. */
 
-#define AOZ1380_FLAGS_SOURCE_ENABLED    BIT(0)
-#define AOZ1380_FLAGS_SINK_ENABLED      BIT(1)
+#define AOZ1380_FLAGS_SOURCE_ENABLED BIT(0)
+#define AOZ1380_FLAGS_SINK_ENABLED BIT(1)
 #define AOZ1380_FLAGS_INT_ON_DISCONNECT BIT(2)
 static atomic_t flags[CONFIG_USB_PD_PORT_MAX_COUNT];
 
@@ -157,7 +157,6 @@ const struct ppc_drv aoz1380_drv = {
 	.is_sourcing_vbus = &aoz1380_is_sourcing_vbus,
 	.vbus_sink_enable = &aoz1380_vbus_sink_enable,
 	.vbus_source_enable = &aoz1380_vbus_source_enable,
-	.set_vbus_source_current_limit =
-		&aoz1380_set_vbus_source_current_limit,
+	.set_vbus_source_current_limit = &aoz1380_set_vbus_source_current_limit,
 	.interrupt = &aoz1380_interrupt,
 };
diff --git a/driver/ppc/ktu1125.c b/driver/ppc/ktu1125.c
index 9c01cfa358..047d011aac 100644
--- a/driver/ppc/ktu1125.c
+++ b/driver/ppc/ktu1125.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,25 +18,21 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 static atomic_t irq_pending; /* Bitmask of ports signaling an interrupt. */
 
 static int read_reg(uint8_t port, int reg, int *regval)
 {
 	return i2c_read8(ppc_chips[port].i2c_port,
-			 ppc_chips[port].i2c_addr_flags,
-			 reg,
-			 regval);
+			 ppc_chips[port].i2c_addr_flags, reg, regval);
 }
 
 static int write_reg(uint8_t port, int reg, int regval)
 {
 	return i2c_write8(ppc_chips[port].i2c_port,
-			  ppc_chips[port].i2c_addr_flags,
-			  reg,
-			  regval);
+			  ppc_chips[port].i2c_addr_flags, reg, regval);
 }
 
 static int set_flags(const int port, const int addr, const int flags_to_set)
@@ -80,7 +76,6 @@ static int set_field(const int port, const int addr, const int shift,
 	return set_flags(port, addr, val);
 }
 
-
 #ifdef CONFIG_CMD_PPC_DUMP
 static int ktu1125_dump(int port)
 {
@@ -102,15 +97,14 @@ static int ktu1125_dump(int port)
 static int ktu1125_power_path_control(int port, int enable)
 {
 	int status = enable ? set_flags(port, KTU1125_CTRL_SW_CFG,
-					KTU1125_SW_AB_EN)
-			    : clr_flags(port, KTU1125_CTRL_SW_CFG,
-					KTU1125_SW_AB_EN |
-					KTU1125_CC1S_VCONN |
-					KTU1125_CC2S_VCONN);
+					KTU1125_SW_AB_EN) :
+			      clr_flags(port, KTU1125_CTRL_SW_CFG,
+					KTU1125_SW_AB_EN | KTU1125_CC1S_VCONN |
+						KTU1125_CC2S_VCONN);
 
 	if (status) {
-		CPRINTS("ppc p%d: Failed to %s power path",
-			port, enable ? "enable" : "disable");
+		CPRINTS("ppc p%d: Failed to %s power path", port,
+			enable ? "enable" : "disable");
 	}
 
 	return status;
@@ -138,7 +132,6 @@ static int ktu1125_init(int port)
 		return regval;
 	}
 
-
 	/*
 	 * Setting control register CTRL_SW_CFG
 	 */
@@ -230,7 +223,7 @@ static int ktu1125_init(int port)
 	 */
 
 	/* Leave SYSA_OK and FRS masked for SNK group of interrupts */
-	regval =  KTU1125_SNK_MASK_ALL & (KTU1125_SYSA_OK | KTU1125_FR_SWAP);
+	regval = KTU1125_SNK_MASK_ALL & (KTU1125_SYSA_OK | KTU1125_FR_SWAP);
 	status = write_reg(port, KTU1125_INTMASK_SNK, regval);
 	if (status) {
 		ppc_err_prints("Failed to write INTMASK_SNK!", port, status);
@@ -291,8 +284,7 @@ static int ktu1125_set_polarity(int port, int polarity)
 	if (polarity) {
 		/* CC2 active. */
 		clr_flags(port, KTU1125_CTRL_SW_CFG, KTU1125_CC2S_VCONN);
-		return set_flags(port, KTU1125_CTRL_SW_CFG,
-				 KTU1125_CC1S_VCONN);
+		return set_flags(port, KTU1125_CTRL_SW_CFG, KTU1125_CC1S_VCONN);
 	}
 
 	/* else CC1 active. */
@@ -326,9 +318,8 @@ static int ktu1125_set_vbus_src_current_limit(int port, enum tcpc_rp_value rp)
 		break;
 	};
 
-
 	status = set_field(port, KTU1125_SET_SW_CFG, KTU1125_SYSB_CLP_SHIFT,
-			    KTU1125_SYSB_CLP_LEN, regval);
+			   KTU1125_SYSB_CLP_LEN, regval);
 	if (status)
 		ppc_prints("Failed to set KTU1125_SET_SW_CFG!", port);
 
@@ -338,13 +329,13 @@ static int ktu1125_set_vbus_src_current_limit(int port, enum tcpc_rp_value rp)
 static int ktu1125_discharge_vbus(int port, int enable)
 {
 	int status = enable ? set_flags(port, KTU1125_SET_SW2_CFG,
-					KTU1125_VBUS_DIS_EN)
-			    : clr_flags(port, KTU1125_SET_SW2_CFG,
+					KTU1125_VBUS_DIS_EN) :
+			      clr_flags(port, KTU1125_SET_SW2_CFG,
 					KTU1125_VBUS_DIS_EN);
 
 	if (status) {
-		CPRINTS("ppc p%d: Failed to %s vbus discharge",
-			port, enable ? "enable" : "disable");
+		CPRINTS("ppc p%d: Failed to %s vbus discharge", port,
+			enable ? "enable" : "disable");
 		return status;
 	}
 
@@ -355,11 +346,10 @@ static int ktu1125_discharge_vbus(int port, int enable)
 static int ktu1125_set_vconn(int port, int enable)
 {
 	int status = enable ? set_flags(port, KTU1125_CTRL_SW_CFG,
-					KTU1125_VCONN_EN)
-			    : clr_flags(port, KTU1125_CTRL_SW_CFG,
-					KTU1125_VCONN_EN |
-					KTU1125_CC1S_VCONN |
-					KTU1125_CC2S_VCONN);
+					KTU1125_VCONN_EN) :
+			      clr_flags(port, KTU1125_CTRL_SW_CFG,
+					KTU1125_VCONN_EN | KTU1125_CC1S_VCONN |
+						KTU1125_CC2S_VCONN);
 
 	return status;
 }
@@ -369,10 +359,9 @@ static int ktu1125_set_vconn(int port, int enable)
 static int ktu1125_set_frs_enable(int port, int enable)
 {
 	/* Enable/Disable FR_SWAP Interrupt */
-	int status = enable ? clr_flags(port, KTU1125_INTMASK_SNK,
-					KTU1125_FR_SWAP)
-			    : set_flags(port, KTU1125_INTMASK_SNK,
-					KTU1125_FR_SWAP);
+	int status =
+		enable ? clr_flags(port, KTU1125_INTMASK_SNK, KTU1125_FR_SWAP) :
+			 set_flags(port, KTU1125_INTMASK_SNK, KTU1125_FR_SWAP);
 
 	if (status) {
 		ppc_prints("Failed to write KTU1125_INTMASK_SNK!", port);
@@ -380,10 +369,8 @@ static int ktu1125_set_frs_enable(int port, int enable)
 	}
 
 	/* Set the FRS_EN bit */
-	status = enable ? set_flags(port, KTU1125_CTRL_SW_CFG,
-				    KTU1125_FRS_EN)
-			: clr_flags(port, KTU1125_CTRL_SW_CFG,
-				    KTU1125_FRS_EN);
+	status = enable ? set_flags(port, KTU1125_CTRL_SW_CFG, KTU1125_FRS_EN) :
+			  clr_flags(port, KTU1125_CTRL_SW_CFG, KTU1125_FRS_EN);
 
 	return status;
 }
@@ -418,14 +405,14 @@ static int ktu1125_vbus_source_enable(int port, int enable)
 #ifdef CONFIG_USBC_PPC_SBU
 static int ktu1125_set_sbu(int port, int enable)
 {
-	int status = enable ? clr_flags(port, KTU1125_CTRL_SW_CFG,
-					KTU1125_SBU_SHUT)
-			    : set_flags(port, KTU1125_CTRL_SW_CFG,
-					KTU1125_SBU_SHUT);
+	int status =
+		enable ?
+			clr_flags(port, KTU1125_CTRL_SW_CFG, KTU1125_SBU_SHUT) :
+			set_flags(port, KTU1125_CTRL_SW_CFG, KTU1125_SBU_SHUT);
 
 	if (status) {
-		CPRINTS("ppc p%d: Failed to %s sbu",
-			port, enable ? "enable" : "disable");
+		CPRINTS("ppc p%d: Failed to %s sbu", port,
+			enable ? "enable" : "disable");
 	}
 
 	return status;
@@ -452,31 +439,29 @@ static void ktu1125_handle_interrupt(int port)
 		attempt++;
 		if (attempt > 1)
 			ppc_prints("Could not clear interrupts on first "
-				"try, retrying", port);
+				   "try, retrying",
+				   port);
 
 		/* Clear the interrupt by reading all 3 registers */
 		read_reg(port, KTU1125_INT_SNK, &snk);
 		read_reg(port, KTU1125_INT_SRC, &src);
 		read_reg(port, KTU1125_INT_DATA, &data);
 
-		CPRINTS("ppc p%d: INTERRUPT snk=%02X src=%02X data=%02X",
-			port, snk, src, data);
+		CPRINTS("ppc p%d: INTERRUPT snk=%02X src=%02X data=%02X", port,
+			snk, src, data);
 
 		if (snk & KTU1125_FR_SWAP)
 			pd_got_frs_signal(port);
 
-		if (snk & (KTU1125_SYSA_SCP |
-			   KTU1125_SYSA_OCP |
-			   KTU1125_VBUS_OVP)) {
+		if (snk &
+		    (KTU1125_SYSA_SCP | KTU1125_SYSA_OCP | KTU1125_VBUS_OVP)) {
 			/* Log and PD reset */
 			pd_handle_overcurrent(port);
 		}
 
-		if (src & (KTU1125_SYSB_CLP |
-			   KTU1125_SYSB_OCP |
-			   KTU1125_SYSB_SCP |
-			   KTU1125_VCONN_CLP |
-			   KTU1125_VCONN_SCP)) {
+		if (src &
+		    (KTU1125_SYSB_CLP | KTU1125_SYSB_OCP | KTU1125_SYSB_SCP |
+		     KTU1125_VCONN_CLP | KTU1125_VCONN_SCP)) {
 			/* Log and PD reset */
 			pd_handle_overcurrent(port);
 		}
diff --git a/driver/ppc/ktu1125.h b/driver/ppc/ktu1125.h
index 826c6a925e..229c894b8c 100644
--- a/driver/ppc/ktu1125.h
+++ b/driver/ppc/ktu1125.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,114 +12,114 @@
 
 #include "driver/ppc/ktu1125_public.h"
 
-#define KTU1125_ID		0x0
-#define KTU1125_CTRL_SW_CFG	0x1
-#define KTU1125_SET_SW_CFG	0x2
-#define KTU1125_SET_SW2_CFG	0x3
-#define KTU1125_MONITOR_SNK	0x4
-#define KTU1125_MONITOR_SRC	0x5
-#define KTU1125_MONITOR_DATA	0x6
-#define KTU1125_INTMASK_SNK	0x7
-#define KTU1125_INTMASK_SRC	0x8
-#define KTU1125_INTMASK_DATA	0x9
-#define KTU1125_INT_SNK		0xA
-#define KTU1125_INT_SRC		0xB
-#define KTU1125_INT_DATA	0xC
+#define KTU1125_ID 0x0
+#define KTU1125_CTRL_SW_CFG 0x1
+#define KTU1125_SET_SW_CFG 0x2
+#define KTU1125_SET_SW2_CFG 0x3
+#define KTU1125_MONITOR_SNK 0x4
+#define KTU1125_MONITOR_SRC 0x5
+#define KTU1125_MONITOR_DATA 0x6
+#define KTU1125_INTMASK_SNK 0x7
+#define KTU1125_INTMASK_SRC 0x8
+#define KTU1125_INTMASK_DATA 0x9
+#define KTU1125_INT_SNK 0xA
+#define KTU1125_INT_SRC 0xB
+#define KTU1125_INT_DATA 0xC
 
 /* KTU1125_ID default value */
 #define KTU1125_VENDOR_DIE_IDS 0xA5
 
 /* KTU1125_CTRL_SW_CFG bits */
-#define KTU1125_SBU_SHUT	BIT(0)
-#define KTU1125_VCONN_EN	BIT(1)
-#define KTU1125_CC2S_VCONN	BIT(2)
-#define KTU1125_CC1S_VCONN	BIT(3)
-#define KTU1125_POW_MODE	BIT(4)
-#define KTU1125_SW_AB_EN	BIT(5)
-#define KTU1125_FRS_EN		BIT(6)
-#define KTU1125_EN_L		BIT(7)
+#define KTU1125_SBU_SHUT BIT(0)
+#define KTU1125_VCONN_EN BIT(1)
+#define KTU1125_CC2S_VCONN BIT(2)
+#define KTU1125_CC1S_VCONN BIT(3)
+#define KTU1125_POW_MODE BIT(4)
+#define KTU1125_SW_AB_EN BIT(5)
+#define KTU1125_FRS_EN BIT(6)
+#define KTU1125_EN_L BIT(7)
 
 /* KTU1125_SET_SW_CFG bits and fields */
-#define KTU1125_RDB_DIS		BIT(0)
-#define KTU1125_SS_CLP_SNK	BIT(1)
-#define KTU1125_TDON		BIT(2)
-#define KTU1125_VCONN_CLP_SHIFT	3
-#define KTU1125_VCONN_CLP_LEN	2
-#define KTU1125_SYSB_CLP_SHIFT	5
-#define KTU1125_SYSB_CLP_LEN	3
+#define KTU1125_RDB_DIS BIT(0)
+#define KTU1125_SS_CLP_SNK BIT(1)
+#define KTU1125_TDON BIT(2)
+#define KTU1125_VCONN_CLP_SHIFT 3
+#define KTU1125_VCONN_CLP_LEN 2
+#define KTU1125_SYSB_CLP_SHIFT 5
+#define KTU1125_SYSB_CLP_LEN 3
 
 /* VBUS Switch Current Limit Settings - SYSB_CLP */
-#define KTU1125_SYSB_ILIM_0_6	0
-#define KTU1125_SYSB_ILIM_1_05	1
-#define KTU1125_SYSB_ILIM_1_70	2
-#define KTU1125_SYSB_ILIM_3_30	3
-#define KTU1125_SYSB_ILIM_3_60	4
+#define KTU1125_SYSB_ILIM_0_6 0
+#define KTU1125_SYSB_ILIM_1_05 1
+#define KTU1125_SYSB_ILIM_1_70 2
+#define KTU1125_SYSB_ILIM_3_30 3
+#define KTU1125_SYSB_ILIM_3_60 4
 
 /* VCONN Current Limit Settings - VCONN_CLP */
-#define KTU1125_VCONN_ILIM_0_40	0
-#define KTU1125_VCONN_ILIM_0_60	1
-#define KTU1125_VCONN_ILIM_1_00	2
-#define KTU1125_VCONN_ILIM_1_40	3
+#define KTU1125_VCONN_ILIM_0_40 0
+#define KTU1125_VCONN_ILIM_0_60 1
+#define KTU1125_VCONN_ILIM_1_00 2
+#define KTU1125_VCONN_ILIM_1_40 3
 
 /* KTU1125_SET_SW2_CFG bits and fields */
-#define KTU1125_OVP_BUS_SHIFT	0
-#define KTU1125_OVP_BUS_LEN	3
-#define KTU1125_DIS_RES_SHIFT	3
-#define KTU1125_DIS_RES_LEN	2
-#define KTU1125_VBUS_DIS_EN	BIT(5)
-#define KTU1125_T_HIC_SHIFT	6
-#define KTU1125_T_HIC_LEN	2
+#define KTU1125_OVP_BUS_SHIFT 0
+#define KTU1125_OVP_BUS_LEN 3
+#define KTU1125_DIS_RES_SHIFT 3
+#define KTU1125_DIS_RES_LEN 2
+#define KTU1125_VBUS_DIS_EN BIT(5)
+#define KTU1125_T_HIC_SHIFT 6
+#define KTU1125_T_HIC_LEN 2
 
 /* VBUS Over Voltage Protection */
-#define KTU1125_SYSB_VLIM_25_00	0
-#define KTU1125_SYSB_VLIM_17_00	4
-#define KTU1125_SYSB_VLIM_13_75	5
-#define KTU1125_SYSB_VLIM_10_60	6
-#define KTU1125_SYSB_VLIM_6_00	7
+#define KTU1125_SYSB_VLIM_25_00 0
+#define KTU1125_SYSB_VLIM_17_00 4
+#define KTU1125_SYSB_VLIM_13_75 5
+#define KTU1125_SYSB_VLIM_10_60 6
+#define KTU1125_SYSB_VLIM_6_00 7
 
 /* Discharge resistor [ohms] */
-#define KTU1125_DIS_RES_1400	0
-#define KTU1125_DIS_RES_730	1
-#define KTU1125_DIS_RES_570	2
-#define KTU1125_DIS_RES_205	3
+#define KTU1125_DIS_RES_1400 0
+#define KTU1125_DIS_RES_730 1
+#define KTU1125_DIS_RES_570 2
+#define KTU1125_DIS_RES_205 3
 
 /* T _HIC values [ms] */
-#define KTU_T_HIC_MS_17		0
-#define KTU_T_HIC_MS_34		1
-#define KTU_T_HIC_MS_51		2
-#define KTU_T_HIC_MS_68		3
+#define KTU_T_HIC_MS_17 0
+#define KTU_T_HIC_MS_34 1
+#define KTU_T_HIC_MS_51 2
+#define KTU_T_HIC_MS_68 3
 
 /* Bits for MONITOR/INTMASK/INT SNK */
-#define KTU1125_SS_FAIL		BIT(0)
-#define KTU1125_OTP		BIT(1)
-#define KTU1125_FR_SWAP		BIT(2)
-#define KTU1125_SYSA_SCP	BIT(3)
-#define KTU1125_SYSA_OCP	BIT(4)
-#define KTU1125_VBUS_OVP	BIT(5)
-#define KTU1125_VBUS_UVLO	BIT(6)
-#define KTU1125_SYSA_OK		BIT(7)
-#define KTU1125_SNK_MASK_ALL	0xFF
+#define KTU1125_SS_FAIL BIT(0)
+#define KTU1125_OTP BIT(1)
+#define KTU1125_FR_SWAP BIT(2)
+#define KTU1125_SYSA_SCP BIT(3)
+#define KTU1125_SYSA_OCP BIT(4)
+#define KTU1125_VBUS_OVP BIT(5)
+#define KTU1125_VBUS_UVLO BIT(6)
+#define KTU1125_SYSA_OK BIT(7)
+#define KTU1125_SNK_MASK_ALL 0xFF
 
 /* Bits for MONITOR/INTMASK/INT SRC */
-#define KTU1125_VCONN_SCP	BIT(0)
-#define KTU1125_VCONN_CLP	BIT(1)
-#define KTU1125_VCONN_UVLO	BIT(2)
-#define KTU1125_SYSB_SCP	BIT(3)
-#define KTU1125_SYSB_OCP	BIT(4)
-#define KTU1125_SYSB_CLP	BIT(5)
-#define KTU1125_SYSB_UVLO	BIT(6)
-#define KTU1125_VBUS_OK		BIT(7)
-#define KTU1125_SRC_MASK_ALL	0xFF
+#define KTU1125_VCONN_SCP BIT(0)
+#define KTU1125_VCONN_CLP BIT(1)
+#define KTU1125_VCONN_UVLO BIT(2)
+#define KTU1125_SYSB_SCP BIT(3)
+#define KTU1125_SYSB_OCP BIT(4)
+#define KTU1125_SYSB_CLP BIT(5)
+#define KTU1125_SYSB_UVLO BIT(6)
+#define KTU1125_VBUS_OK BIT(7)
+#define KTU1125_SRC_MASK_ALL 0xFF
 
 /* Bits for MONITOR/INTMASK/INT DATA */
-#define KTU1125_SBUB		BIT(0)
-#define KTU1125_SBUA		BIT(1)
-#define KTU1125_SBU2_OVP	BIT(2)
-#define KTU1125_SBU1_OVP	BIT(3)
-#define KTU1125_CC2_OVP		BIT(4)
-#define KTU1125_CC1_OVP		BIT(5)
-#define KTU1125_CC2S_CLAMP	BIT(6)
-#define KTU1125_CC1S_CLAMP	BIT(7)
-#define KTU1125_DATA_MASK_ALL	0xFC
+#define KTU1125_SBUB BIT(0)
+#define KTU1125_SBUA BIT(1)
+#define KTU1125_SBU2_OVP BIT(2)
+#define KTU1125_SBU1_OVP BIT(3)
+#define KTU1125_CC2_OVP BIT(4)
+#define KTU1125_CC1_OVP BIT(5)
+#define KTU1125_CC2S_CLAMP BIT(6)
+#define KTU1125_CC1S_CLAMP BIT(7)
+#define KTU1125_DATA_MASK_ALL 0xFC
 
 #endif /* defined(__CROS_EC_KTU1125_H) */
diff --git a/driver/ppc/nx20p348x.c b/driver/ppc/nx20p348x.c
index e05d7e60a7..d202898a85 100644
--- a/driver/ppc/nx20p348x.c
+++ b/driver/ppc/nx20p348x.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,8 +19,8 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 static atomic_t irq_pending; /* Bitmask of ports signaling an interrupt. */
 
@@ -37,17 +37,13 @@ static uint8_t flags[CONFIG_USB_PD_PORT_MAX_COUNT];
 static int read_reg(uint8_t port, int reg, int *regval)
 {
 	return i2c_read8(ppc_chips[port].i2c_port,
-			 ppc_chips[port].i2c_addr_flags,
-			 reg,
-			 regval);
+			 ppc_chips[port].i2c_addr_flags, reg, regval);
 }
 
 static int write_reg(uint8_t port, int reg, int regval)
 {
 	return i2c_write8(ppc_chips[port].i2c_port,
-			  ppc_chips[port].i2c_addr_flags,
-			  reg,
-			  regval);
+			  ppc_chips[port].i2c_addr_flags, reg, regval);
 }
 
 static int nx20p348x_set_ovp_limit(int port)
@@ -76,7 +72,7 @@ static int nx20p348x_is_sourcing_vbus(int port)
 }
 
 static int nx20p348x_set_vbus_source_current_limit(int port,
-						 enum tcpc_rp_value rp)
+						   enum tcpc_rp_value rp)
 {
 	int regval;
 	int status;
@@ -103,7 +99,6 @@ static int nx20p348x_set_vbus_source_current_limit(int port,
 		break;
 	};
 
-
 	return write_reg(port, NX20P348X_5V_SRC_OCP_THRESHOLD_REG, regval);
 }
 
@@ -166,7 +161,8 @@ __maybe_unused static int nx20p3481_vbus_sink_enable(int port, int enable)
 		return rv;
 
 	return (status & NX20P348X_SWITCH_STATUS_HVSNK) == control ?
-		EC_SUCCESS : EC_ERROR_UNKNOWN;
+		       EC_SUCCESS :
+		       EC_ERROR_UNKNOWN;
 }
 
 __maybe_unused static int nx20p3481_vbus_source_enable(int port, int enable)
@@ -242,7 +238,7 @@ __maybe_unused static int nx20p3483_vbus_sink_enable(int port, int enable)
 			return rv;
 
 		is_sink = (ds & NX20P3483_DEVICE_MODE_MASK) ==
-			NX20P3483_MODE_HV_SNK;
+			  NX20P3483_MODE_HV_SNK;
 		if (enable == is_sink)
 			return EC_SUCCESS;
 
@@ -319,6 +315,10 @@ static int nx20p348x_init(int port)
 		/* Unmask Fast Role Swap detect interrupt */
 		mask &= ~NX20P3481_INT1_FRS_DET;
 	}
+	if (IS_ENABLED(CONFIG_USBC_NX20P348X_RCP_5VSRC_MASK_ENABLE)) {
+		/* Mask RCP 5V SRC */
+		mask |= NX20P348X_INT1_RCP_5VSRC;
+	}
 	rv = write_reg(port, NX20P348X_INTERRUPT1_MASK_REG, mask);
 	if (rv)
 		return rv;
@@ -409,7 +409,7 @@ static void nx20p348x_handle_interrupt(int port)
 		    NX20P348X_DB_EXIT_FAIL_THRESHOLD) {
 			ppc_prints("failed to exit DB mode", port);
 			if (read_reg(port, NX20P348X_INTERRUPT1_MASK_REG,
-				    &mask_reg)) {
+				     &mask_reg)) {
 				mask_reg |= NX20P348X_INT1_DBEXIT_ERR;
 				write_reg(port, NX20P348X_INTERRUPT1_MASK_REG,
 					  mask_reg);
@@ -502,8 +502,8 @@ static int nx20p348x_dump(int port)
 	int rv;
 
 	ccprintf("Port %d NX20P348X registers\n", port);
-	for (reg_addr = NX20P348X_DEVICE_ID_REG; reg_addr <=
-		     NX20P348X_DEVICE_CONTROL_REG; reg_addr++) {
+	for (reg_addr = NX20P348X_DEVICE_ID_REG;
+	     reg_addr <= NX20P348X_DEVICE_CONTROL_REG; reg_addr++) {
 		rv = read_reg(port, reg_addr, &reg);
 		if (rv) {
 			ccprintf("nx20p: Failed to read register 0x%x\n",
diff --git a/driver/ppc/nx20p348x.h b/driver/ppc/nx20p348x.h
index 001a43f489..94e7a8d06e 100644
--- a/driver/ppc/nx20p348x.h
+++ b/driver/ppc/nx20p348x.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,16 +9,7 @@
 #define __CROS_EC_NX20P348X_H
 
 #include "common.h"
-
-#define NX20P3483_ADDR0_FLAGS 0x70
-#define NX20P3483_ADDR1_FLAGS 0x71
-#define NX20P3483_ADDR2_FLAGS 0x72
-#define NX20P3483_ADDR3_FLAGS 0x73
-
-#define NX20P3481_ADDR0_FLAGS 0x74
-#define NX20P3481_ADDR1_FLAGS 0x75
-#define NX20P3481_ADDR2_FLAGS 0x76
-#define NX20P3481_ADDR3_FLAGS 0x77
+#include "ppc/nx20p348x_public.h"
 
 /*
  * This PPC hard-codes the over voltage protect of Vbus at 6.8V in dead-battery
@@ -28,63 +19,63 @@
 #define NX20P348X_SAFE_RESET_VBUS_MV 5000
 
 /* NX20P348x register addresses */
-#define NX20P348X_DEVICE_ID_REG			0x00
-#define NX20P348X_DEVICE_STATUS_REG		0x01
-#define NX20P348X_SWITCH_CONTROL_REG		0x02
-#define NX20P348X_SWITCH_STATUS_REG		0x03
-#define NX20P348X_INTERRUPT1_REG		0x04
-#define NX20P348X_INTERRUPT2_REG		0x05
-#define NX20P348X_INTERRUPT1_MASK_REG		0x06
-#define NX20P348X_INTERRUPT2_MASK_REG		0x07
-#define NX20P348X_OVLO_THRESHOLD_REG		0x08
-#define NX20P348X_HV_SRC_OCP_THRESHOLD_REG	0x09
-#define NX20P348X_5V_SRC_OCP_THRESHOLD_REG	0x0A
-#define NX20P348X_DEVICE_CONTROL_REG		0x0B
+#define NX20P348X_DEVICE_ID_REG 0x00
+#define NX20P348X_DEVICE_STATUS_REG 0x01
+#define NX20P348X_SWITCH_CONTROL_REG 0x02
+#define NX20P348X_SWITCH_STATUS_REG 0x03
+#define NX20P348X_INTERRUPT1_REG 0x04
+#define NX20P348X_INTERRUPT2_REG 0x05
+#define NX20P348X_INTERRUPT1_MASK_REG 0x06
+#define NX20P348X_INTERRUPT2_MASK_REG 0x07
+#define NX20P348X_OVLO_THRESHOLD_REG 0x08
+#define NX20P348X_HV_SRC_OCP_THRESHOLD_REG 0x09
+#define NX20P348X_5V_SRC_OCP_THRESHOLD_REG 0x0A
+#define NX20P348X_DEVICE_CONTROL_REG 0x0B
 
 /* Device Control Register (0x0B) */
-#define NX20P3483_CTRL_FRS_AT		BIT(3)
-#define NX20P348X_CTRL_DB_EXIT		BIT(2)
-#define NX20P348X_CTRL_VBUSDIS_EN	BIT(1)
-#define NX20P348X_CTRL_LDO_SD		BIT(0)
+#define NX20P3483_CTRL_FRS_AT BIT(3)
+#define NX20P348X_CTRL_DB_EXIT BIT(2)
+#define NX20P348X_CTRL_VBUSDIS_EN BIT(1)
+#define NX20P348X_CTRL_LDO_SD BIT(0)
 
 /* Device Status Modes (0x01) */
-#define NX20P3481_DEVICE_MODE_MASK	0x3
-#define NX20P3483_DEVICE_MODE_MASK	0x7
-#define NX20P348X_MODE_DEAD_BATTERY	0
+#define NX20P3481_DEVICE_MODE_MASK 0x3
+#define NX20P3483_DEVICE_MODE_MASK 0x7
+#define NX20P348X_MODE_DEAD_BATTERY 0
 /* After dead battery, mode values are different between 3481 and 3483 */
-#define NX20P3481_MODE_NORMAL		1
-#define NX20P3481_MODE_FRS		2
-#define NX20P3481_MODE_STANDBY		3
+#define NX20P3481_MODE_NORMAL 1
+#define NX20P3481_MODE_FRS 2
+#define NX20P3481_MODE_STANDBY 3
 
-#define NX20P3483_MODE_HV_SNK		1
-#define NX20P3483_MODE_5V_SRC		2
-#define NX20P3483_MODE_HV_SRC		3
-#define NX20P3483_MODE_STANDBY		4
+#define NX20P3483_MODE_HV_SNK 1
+#define NX20P3483_MODE_5V_SRC 2
+#define NX20P3483_MODE_HV_SRC 3
+#define NX20P3483_MODE_STANDBY 4
 
 /* Switch Control Register (0x02) */
-#define NX20P3481_SWITCH_CONTROL_5VSRC	BIT(2)
-#define NX20P3481_SWITCH_CONTROL_HVSRC	BIT(1)
-#define NX20P3481_SWITCH_CONTROL_HVSNK	BIT(0)
+#define NX20P3481_SWITCH_CONTROL_5VSRC BIT(2)
+#define NX20P3481_SWITCH_CONTROL_HVSRC BIT(1)
+#define NX20P3481_SWITCH_CONTROL_HVSNK BIT(0)
 
 /* Switch Status Register (0x03) */
-#define NX20P348X_SWITCH_STATUS_5VSRC	BIT(2)
-#define NX20P348X_SWITCH_STATUS_HVSRC	BIT(1)
-#define NX20P348X_SWITCH_STATUS_HVSNK	BIT(0)
+#define NX20P348X_SWITCH_STATUS_5VSRC BIT(2)
+#define NX20P348X_SWITCH_STATUS_HVSRC BIT(1)
+#define NX20P348X_SWITCH_STATUS_HVSNK BIT(0)
 #define NX20P348X_SWITCH_STATUS_DEBOUNCE_MSEC 25
-#define NX20P348X_SWITCH_STATUS_MASK	0x7
+#define NX20P348X_SWITCH_STATUS_MASK 0x7
 
 /* Internal 5V VBUS Switch Current Limit Settings (min) */
 #define NX20P348X_ILIM_MASK 0xF
-#define NX20P348X_ILIM_0_400  0
-#define NX20P348X_ILIM_0_600  1
-#define NX20P348X_ILIM_0_800  2
-#define NX20P348X_ILIM_1_000  3
-#define NX20P348X_ILIM_1_200  4
-#define NX20P348X_ILIM_1_400  5
-#define NX20P348X_ILIM_1_600  6
-#define NX20P348X_ILIM_1_800  7
-#define NX20P348X_ILIM_2_000  8
-#define NX20P348X_ILIM_2_200  9
+#define NX20P348X_ILIM_0_400 0
+#define NX20P348X_ILIM_0_600 1
+#define NX20P348X_ILIM_0_800 2
+#define NX20P348X_ILIM_1_000 3
+#define NX20P348X_ILIM_1_200 4
+#define NX20P348X_ILIM_1_400 5
+#define NX20P348X_ILIM_1_600 6
+#define NX20P348X_ILIM_1_800 7
+#define NX20P348X_ILIM_2_000 8
+#define NX20P348X_ILIM_2_200 9
 #define NX20P348X_ILIM_2_400 10
 #define NX20P348X_ILIM_2_600 11
 #define NX20P348X_ILIM_2_800 12
@@ -103,33 +94,23 @@
 #define NX20P348X_OVLO_23_0 6
 
 /* Interrupt 1 Register Bits (0x04) */
-#define NX20P348X_INT1_DBEXIT_ERR	BIT(7)
-#define NX20P3481_INT1_FRS_DET		BIT(6)
-#define NX20P348X_INT1_OV_5VSRC		BIT(4)
-#define NX20P348X_INT1_RCP_5VSRC	BIT(3)
-#define NX20P348X_INT1_SC_5VSRC		BIT(2)
-#define NX20P348X_INT1_OC_5VSRC		BIT(1)
-#define NX20P348X_INT1_OTP		BIT(0)
+#define NX20P348X_INT1_DBEXIT_ERR BIT(7)
+#define NX20P3481_INT1_FRS_DET BIT(6)
+#define NX20P348X_INT1_OV_5VSRC BIT(4)
+#define NX20P348X_INT1_RCP_5VSRC BIT(3)
+#define NX20P348X_INT1_SC_5VSRC BIT(2)
+#define NX20P348X_INT1_OC_5VSRC BIT(1)
+#define NX20P348X_INT1_OTP BIT(0)
 
 /* Interrupt 2 Register Bits (0x05) */
-#define NX20P348X_INT2_EN_ERR		BIT(7)
-#define NX20P348X_INT2_RCP_HVSNK	BIT(6)
-#define NX20P348X_INT2_SC_HVSNK		BIT(5)
-#define NX20P348X_INT2_OV_HVSNK		BIT(4)
-#define NX20P348X_INT2_RCP_HVSRC	BIT(3)
-#define NX20P348X_INT2_SC_HVSRC		BIT(2)
-#define NX20P348X_INT2_OC_HVSRC		BIT(1)
-#define NX20P348X_INT2_OV_HVSRC		BIT(0)
-
-struct ppc_drv;
-extern const struct ppc_drv nx20p348x_drv;
-
-/**
- * Interrupt Handler for the NX20P348x.
- *
- * @param port: The Type-C port which triggered the interrupt.
- */
-void nx20p348x_interrupt(int port);
+#define NX20P348X_INT2_EN_ERR BIT(7)
+#define NX20P348X_INT2_RCP_HVSNK BIT(6)
+#define NX20P348X_INT2_SC_HVSNK BIT(5)
+#define NX20P348X_INT2_OV_HVSNK BIT(4)
+#define NX20P348X_INT2_RCP_HVSRC BIT(3)
+#define NX20P348X_INT2_SC_HVSRC BIT(2)
+#define NX20P348X_INT2_OC_HVSRC BIT(1)
+#define NX20P348X_INT2_OV_HVSRC BIT(0)
 
 /**
  * Board override for NX20P348X init.
diff --git a/driver/ppc/rt1718s.c b/driver/ppc/rt1718s.c
index a7a378d934..3accf5d0fa 100644
--- a/driver/ppc/rt1718s.c
+++ b/driver/ppc/rt1718s.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,40 +14,33 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-
 #define RT1718S_FLAGS_SOURCE_ENABLED BIT(0)
 static atomic_t flags[CONFIG_USB_PD_PORT_MAX_COUNT];
 
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static int read_reg(uint8_t port, int reg, int *val)
 {
 	if (reg > 0xFF) {
-		return i2c_read_offset16(
-			ppc_chips[port].i2c_port,
-			ppc_chips[port].i2c_addr_flags,
-			reg, val, 1);
+		return i2c_read_offset16(ppc_chips[port].i2c_port,
+					 ppc_chips[port].i2c_addr_flags, reg,
+					 val, 1);
 	} else {
-		return i2c_read8(
-			ppc_chips[port].i2c_port,
-			ppc_chips[port].i2c_addr_flags,
-			reg, val);
+		return i2c_read8(ppc_chips[port].i2c_port,
+				 ppc_chips[port].i2c_addr_flags, reg, val);
 	}
 }
 
 static int write_reg(uint8_t port, int reg, int val)
 {
 	if (reg > 0xFF) {
-		return i2c_write_offset16(
-			ppc_chips[port].i2c_port,
-			ppc_chips[port].i2c_addr_flags,
-			reg, val, 1);
+		return i2c_write_offset16(ppc_chips[port].i2c_port,
+					  ppc_chips[port].i2c_addr_flags, reg,
+					  val, 1);
 	} else {
-		return i2c_write8(
-			ppc_chips[port].i2c_port,
-			ppc_chips[port].i2c_addr_flags,
-			reg, val);
+		return i2c_write8(ppc_chips[port].i2c_port,
+				  ppc_chips[port].i2c_addr_flags, reg, val);
 	}
 }
 
@@ -72,18 +65,10 @@ static int rt1718s_is_sourcing_vbus(int port)
 
 static int rt1718s_vbus_source_enable(int port, int enable)
 {
-	atomic_t prev_flag;
-
 	if (enable)
-		prev_flag = atomic_or(&flags[port],
-				RT1718S_FLAGS_SOURCE_ENABLED);
+		atomic_or(&flags[port], RT1718S_FLAGS_SOURCE_ENABLED);
 	else
-		prev_flag = atomic_clear_bits(&flags[port],
-				RT1718S_FLAGS_SOURCE_ENABLED);
-
-	/* Return if status doesn't change */
-	if (!!(prev_flag & RT1718S_FLAGS_SOURCE_ENABLED) == !!enable)
-		return EC_SUCCESS;
+		atomic_clear_bits(&flags[port], RT1718S_FLAGS_SOURCE_ENABLED);
 
 	RETURN_ERROR(tcpm_set_src_ctrl(port, enable));
 
@@ -105,10 +90,9 @@ static int rt1718s_vbus_sink_enable(int port, int enable)
 
 static int rt1718s_discharge_vbus(int port, int enable)
 {
-	return update_bits(port,
-		TCPC_REG_POWER_CTRL,
-		TCPC_REG_POWER_CTRL_FORCE_DISCHARGE,
-		enable ? 0xFF : 0x00);
+	return update_bits(port, TCPC_REG_POWER_CTRL,
+			   TCPC_REG_POWER_CTRL_FORCE_DISCHARGE,
+			   enable ? 0xFF : 0x00);
 }
 
 #ifdef CONFIG_CMD_PPC_DUMP
diff --git a/driver/ppc/rt1718s.h b/driver/ppc/rt1718s.h
index 192063d3fc..e3fd8ac74e 100644
--- a/driver/ppc/rt1718s.h
+++ b/driver/ppc/rt1718s.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/driver/ppc/rt1739.c b/driver/ppc/rt1739.c
index 7b08faac83..d89599a7ae 100644
--- a/driver/ppc/rt1739.c
+++ b/driver/ppc/rt1739.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,7 +15,6 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-
 #if defined(CONFIG_USBC_PPC_VCONN) && !defined(CONFIG_USBC_PPC_POLARITY)
 #error "Can't use set_vconn without set_polarity"
 #endif
@@ -24,35 +23,28 @@
 #define RT1739_FLAGS_FRS_ENABLED BIT(1)
 static atomic_t flags[CONFIG_USB_PD_PORT_MAX_COUNT];
 
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
 
 static int read_reg(uint8_t port, int reg, int *val)
 {
-	return i2c_read8(
-		ppc_chips[port].i2c_port,
-		ppc_chips[port].i2c_addr_flags,
-		reg, val);
+	return i2c_read8(ppc_chips[port].i2c_port,
+			 ppc_chips[port].i2c_addr_flags, reg, val);
 }
 
 static int write_reg(uint8_t port, int reg, int val)
 {
-	return i2c_write8(
-		ppc_chips[port].i2c_port,
-		ppc_chips[port].i2c_addr_flags,
-		reg, val);
+	return i2c_write8(ppc_chips[port].i2c_port,
+			  ppc_chips[port].i2c_addr_flags, reg, val);
 }
 
 static int update_reg(int port, int reg, int mask,
 		      enum mask_update_action action)
 {
-	return i2c_update8(
-		ppc_chips[port].i2c_port,
-		ppc_chips[port].i2c_addr_flags,
-		reg, mask, action);
+	return i2c_update8(ppc_chips[port].i2c_port,
+			   ppc_chips[port].i2c_addr_flags, reg, mask, action);
 }
 
-
 static int rt1739_is_sourcing_vbus(int port)
 {
 	return flags[port] & RT1739_FLAGS_SOURCE_ENABLED;
@@ -63,11 +55,11 @@ static int rt1739_vbus_source_enable(int port, int enable)
 	atomic_t prev_flag;
 
 	if (enable)
-		prev_flag = atomic_or(&flags[port],
-				RT1739_FLAGS_SOURCE_ENABLED);
+		prev_flag =
+			atomic_or(&flags[port], RT1739_FLAGS_SOURCE_ENABLED);
 	else
 		prev_flag = atomic_clear_bits(&flags[port],
-				RT1739_FLAGS_SOURCE_ENABLED);
+					      RT1739_FLAGS_SOURCE_ENABLED);
 
 	/* Return if status doesn't change */
 	if (!!(prev_flag & RT1739_FLAGS_SOURCE_ENABLED) == !!enable)
@@ -90,10 +82,8 @@ static int rt1739_vbus_source_enable(int port, int enable)
 
 static int rt1739_vbus_sink_enable(int port, int enable)
 {
-	return update_reg(port, RT1739_REG_VBUS_SWITCH_CTRL,
-			  RT1739_HV_SNK_EN,
+	return update_reg(port, RT1739_REG_VBUS_SWITCH_CTRL, RT1739_HV_SNK_EN,
 			  enable ? MASK_SET : MASK_CLR);
-
 }
 
 #ifdef CONFIG_CMD_PPC_DUMP
@@ -145,8 +135,7 @@ static int rt1739_is_vbus_present(int port)
 #ifdef CONFIG_USBC_PPC_POLARITY
 static int rt1739_set_polarity(int port, int polarity)
 {
-	return update_reg(port, RT1739_REG_VCONN_CTRL1,
-			  RT1739_VCONN_ORIENT,
+	return update_reg(port, RT1739_REG_VCONN_CTRL1, RT1739_VCONN_ORIENT,
 			  polarity ? RT1739_VCONN_ORIENT_CC1 :
 				     RT1739_VCONN_ORIENT_CC2);
 }
@@ -155,9 +144,8 @@ static int rt1739_set_polarity(int port, int polarity)
 #ifdef CONFIG_USBC_PPC_VCONN
 static int rt1739_set_vconn(int port, int enable)
 {
-	return update_reg(port, RT1739_REG_VCONN_CTRL1,
-				RT1739_VCONN_EN,
-				enable ? MASK_SET : MASK_CLR);
+	return update_reg(port, RT1739_REG_VCONN_CTRL1, RT1739_VCONN_EN,
+			  enable ? MASK_SET : MASK_CLR);
 }
 #endif
 
@@ -176,14 +164,13 @@ static int rt1739_workaround(int port)
 	case RT1739_DEVICE_ID_ES1:
 		CPRINTS("RT1739 ES1");
 		RETURN_ERROR(update_reg(port, RT1739_REG_SYS_CTRL1,
-			RT1739_OSC640K_FORCE_EN,
-			MASK_SET));
+					RT1739_OSC640K_FORCE_EN, MASK_SET));
 
 		RETURN_ERROR(write_reg(port, RT1739_VBUS_FAULT_DIS,
 				       RT1739_OVP_DISVBUS_EN |
-				       RT1739_UVLO_DISVBUS_EN |
-				       RT1739_SCP_DISVBUS_EN |
-				       RT1739_OCPS_DISVBUS_EN));
+					       RT1739_UVLO_DISVBUS_EN |
+					       RT1739_SCP_DISVBUS_EN |
+					       RT1739_OCPS_DISVBUS_EN));
 		break;
 
 	case RT1739_DEVICE_ID_ES2:
@@ -208,14 +195,13 @@ static int rt1739_workaround(int port)
 		msleep(5);
 		RETURN_ERROR(write_reg(port, RT1739_REG_VBUS_SWITCH_CTRL, 0));
 		msleep(5);
-		RETURN_ERROR(write_reg(port, RT1739_VBUS_FAULT_DIS,
-				       RT1739_OVP_DISVBUS_EN |
-				       RT1739_UVLO_DISVBUS_EN |
-				       RT1739_RCP_DISVBUS_EN |
-				       RT1739_SCP_DISVBUS_EN));
-		RETURN_ERROR(write_reg(port, RT1739_REG_VBUS_CTRL1,
-				       RT1739_HVLV_SCP_EN |
-				       RT1739_HVLV_OCRC_EN));
+		RETURN_ERROR(write_reg(
+			port, RT1739_VBUS_FAULT_DIS,
+			RT1739_OVP_DISVBUS_EN | RT1739_UVLO_DISVBUS_EN |
+				RT1739_RCP_DISVBUS_EN | RT1739_SCP_DISVBUS_EN));
+		RETURN_ERROR(
+			write_reg(port, RT1739_REG_VBUS_CTRL1,
+				  RT1739_HVLV_SCP_EN | RT1739_HVLV_OCRC_EN));
 		break;
 
 	default:
@@ -229,8 +215,7 @@ static int rt1739_workaround(int port)
 static int rt1739_set_frs_enable(int port, int enable)
 {
 	/* Enable FRS RX detect */
-	RETURN_ERROR(update_reg(port, RT1739_REG_CC_FRS_CTRL1,
-				RT1739_FRS_RX_EN,
+	RETURN_ERROR(update_reg(port, RT1739_REG_CC_FRS_CTRL1, RT1739_FRS_RX_EN,
 				enable ? MASK_SET : MASK_CLR));
 
 	/*
@@ -243,8 +228,7 @@ static int rt1739_set_frs_enable(int port, int enable)
 	RETURN_ERROR(update_reg(port, RT1739_REG_INT_MASK5,
 				RT1739_BC12_SNK_DONE_MASK,
 				enable ? MASK_CLR : MASK_SET));
-	RETURN_ERROR(update_reg(port, RT1739_REG_INT_MASK4,
-				RT1739_FRS_RX_MASK,
+	RETURN_ERROR(update_reg(port, RT1739_REG_INT_MASK4, RT1739_FRS_RX_MASK,
 				enable ? MASK_SET : MASK_CLR));
 	if (enable)
 		atomic_or(&flags[port], RT1739_FLAGS_FRS_ENABLED);
@@ -268,22 +252,19 @@ static int rt1739_init(int port)
 	RETURN_ERROR(rt1739_workaround(port));
 	RETURN_ERROR(rt1739_set_frs_enable(port, false));
 	RETURN_ERROR(update_reg(port, RT1739_REG_VBUS_DET_EN,
-				RT1739_VBUS_PRESENT_EN,
-				MASK_SET));
+				RT1739_VBUS_PRESENT_EN, MASK_SET));
 	RETURN_ERROR(update_reg(port, RT1739_REG_SBU_CTRL_01,
-				RT1739_DM_SWEN | RT1739_DP_SWEN,
-				MASK_SET));
+				RT1739_DM_SWEN | RT1739_DP_SWEN, MASK_SET));
 	RETURN_ERROR(update_reg(port, RT1739_REG_SBU_CTRL_01,
-				RT1739_SBUSW_MUX_SEL,
-				MASK_CLR));
+				RT1739_SBUSW_MUX_SEL, MASK_CLR));
 	RETURN_ERROR(update_reg(port, RT1739_REG_VCONN_CTRL3,
-				RT1739_VCONN_CLIMIT_EN,
-				MASK_SET));
+				RT1739_VCONN_CLIMIT_EN, MASK_SET));
 
 	/* VBUS OVP -> 23V */
-	RETURN_ERROR(write_reg(port, RT1739_REG_VBUS_OV_SETTING,
+	RETURN_ERROR(write_reg(
+		port, RT1739_REG_VBUS_OV_SETTING,
 		(RT1739_OVP_SEL_23_0V << RT1739_VBUS_OVP_SEL_SHIFT) |
-		(RT1739_OVP_SEL_23_0V << RT1739_VIN_HV_OVP_SEL_SHIFT)));
+			(RT1739_OVP_SEL_23_0V << RT1739_VIN_HV_OVP_SEL_SHIFT)));
 	/* VBUS OCP -> 3.3A (or 5.5A for ES2 HV Sink) */
 	RETURN_ERROR(rt1739_get_device_id(port, &device_id));
 	if (device_id == RT1739_DEVICE_ID_ES2)
@@ -317,7 +298,7 @@ static void rt1739_update_charge_manager(int port,
 	if (new_bc12_type != current_bc12_type) {
 		if (current_bc12_type != CHARGE_SUPPLIER_NONE)
 			charge_manager_update_charge(current_bc12_type, port,
-							NULL);
+						     NULL);
 
 		if (new_bc12_type != CHARGE_SUPPLIER_NONE) {
 			struct charge_port_info chg = {
@@ -334,8 +315,8 @@ static void rt1739_update_charge_manager(int port,
 
 static void rt1739_enable_bc12_detection(int port, bool enable)
 {
-	update_reg(port, RT1739_REG_BC12_SNK_FUNC,
-		   RT1739_BC12_SNK_EN, enable ? MASK_SET : MASK_CLR);
+	update_reg(port, RT1739_REG_BC12_SNK_FUNC, RT1739_BC12_SNK_EN,
+		   enable ? MASK_SET : MASK_CLR);
 }
 
 static enum charge_supplier rt1739_bc12_get_device_type(int port)
@@ -370,16 +351,16 @@ static void rt1739_usb_charger_task_init(const int port)
 static void rt1739_usb_charger_task_event(const int port, uint32_t evt)
 {
 	bool is_non_pd_sink = !pd_capable(port) &&
-		!usb_charger_port_is_sourcing_vbus(port) &&
-		pd_check_vbus_level(port, VBUS_PRESENT);
+			      !usb_charger_port_is_sourcing_vbus(port) &&
+			      pd_check_vbus_level(port, VBUS_PRESENT);
 
 	/* vbus change, start bc12 detection */
 	if (evt & USB_CHG_EVENT_VBUS) {
 		if (is_non_pd_sink)
 			rt1739_enable_bc12_detection(port, true);
 		else
-			rt1739_update_charge_manager(
-					port, CHARGE_SUPPLIER_NONE);
+			rt1739_update_charge_manager(port,
+						     CHARGE_SUPPLIER_NONE);
 	}
 
 	/* detection done, update charge_manager and stop detection */
diff --git a/driver/ppc/rt1739.h b/driver/ppc/rt1739.h
index 2f9b196011..d93369094f 100644
--- a/driver/ppc/rt1739.h
+++ b/driver/ppc/rt1739.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,110 +16,110 @@
 #define RT1739_ADDR3_FLAGS 0x72
 #define RT1739_ADDR4_FLAGS 0x73
 
-#define RT1739_REG_DEVICE_ID0		0x02
-#define RT1739_DEVICE_ID_ES1			0x11
-#define RT1739_DEVICE_ID_ES2			0x12
-
-#define RT1739_REG_SW_RESET		0x04
-#define RT1739_SW_RESET				BIT(0)
-
-#define RT1739_REG_INT_MASK4		0x0C
-#define RT1739_FRS_RX_MASK			BIT(4)
-
-#define RT1739_REG_INT_MASK5		0x0D
-#define RT1739_BC12_SNK_DONE_MASK		BIT(0)
-
-#define RT1739_REG_INT_EVENT4		0x14
-
-#define RT1739_REG_INT_EVENT5		0x15
-#define RT1739_BC12_SNK_DONE_INT		BIT(0)
-
-#define RT1739_REG_INT_STS4		0x1C
-#define RT1739_VBUS_VALID			BIT(2)
-#define RT1739_VBUS_PRESENT			BIT(0)
-
-#define RT1739_REG_SYS_CTRL		0x20
-#define RT1739_OT_EN				BIT(4)
-#define RT1739_SHUTDOWN_OFF			BIT(0)
-
-#define RT1739_REG_VBUS_SWITCH_CTRL	0x21
-#define RT1739_LV_SRC_EN			BIT(2)
-#define RT1739_HV_SRC_EN			BIT(1)
-#define RT1739_HV_SNK_EN			BIT(0)
-
-#define RT1739_REG_VBUS_CTRL1		0x23
-#define RT1739_HVLV_SCP_EN			BIT(1)
-#define RT1739_HVLV_OCRC_EN			BIT(0)
-
-#define RT1739_REG_VBUS_OV_SETTING	0x24
-
-#define RT1739_VBUS_OVP_SEL_SHIFT		0
-#define RT1739_VIN_HV_OVP_SEL_SHIFT		4
-#define RT1739_OVP_SEL_6_0V			0
-#define RT1739_OVP_SEL_6_8V			1
-#define RT1739_OVP_SEL_10_0V			2
-#define RT1739_OVP_SEL_11_5V			3
-#define RT1739_OVP_SEL_14_0V			4
-#define RT1739_OVP_SEL_17_0V			5
-#define RT1739_OVP_SEL_23_0V			6
-
-#define RT1739_REG_VBUS_OC_SETTING	0x25
-
-#define RT1739_LV_SRC_OCP_SHIFT			4
-#define RT1739_LV_SRC_OCP_SEL_1_25A		(0 << RT1739_LV_SRC_OCP_SHIFT)
-#define RT1739_LV_SRC_OCP_SEL_1_75A		(1 << RT1739_LV_SRC_OCP_SHIFT)
-#define RT1739_LV_SRC_OCP_SEL_2_25A		(2 << RT1739_LV_SRC_OCP_SHIFT)
-#define RT1739_LV_SRC_OCP_SEL_3_3A		(3 << RT1739_LV_SRC_OCP_SHIFT)
-
-#define RT1739_HV_SINK_OCP_SHIFT		0
-#define RT1739_HV_SINK_OCP_SEL_1_25A		(0 << RT1739_HV_SINK_OCP_SHIFT)
-#define RT1739_HV_SINK_OCP_SEL_1_75A		(1 << RT1739_HV_SINK_OCP_SHIFT)
-#define RT1739_HV_SINK_OCP_SEL_3_3A		(2 << RT1739_HV_SINK_OCP_SHIFT)
-#define RT1739_HV_SINK_OCP_SEL_5_5A		(3 << RT1739_HV_SINK_OCP_SHIFT)
-
-#define RT1739_VBUS_FAULT_DIS		0x26
-#define RT1739_OVP_DISVBUS_EN			BIT(6)
-#define RT1739_UVLO_DISVBUS_EN			BIT(5)
-#define RT1739_SRCP_DISVBUS_EN			BIT(4)
-#define RT1739_RCP_DISVBUS_EN			BIT(3)
-#define RT1739_SCP_DISVBUS_EN			BIT(2)
-#define RT1739_OCPS_DISVBUS_EN			BIT(1)
-#define RT1739_OCP_DISVBUS_EN			BIT(0)
-
-#define RT1739_REG_VBUS_DET_EN		0x27
-#define RT1739_VBUS_SAFE5V_EN			BIT(2)
-#define RT1739_VBUS_SAFE0V_EN			BIT(1)
-#define RT1739_VBUS_PRESENT_EN			BIT(0)
-
-#define RT1739_REG_CC_FRS_CTRL1		0x2D
-#define RT1739_FRS_RX_EN			BIT(1)
-
-#define RT1739_REG_VCONN_CTRL1		0x31
-#define RT1739_VCONN_ORIENT			BIT(1)
-#define RT1739_VCONN_EN				BIT(0)
-
-#define RT1739_VCONN_ORIENT_CC1			MASK_SET
-#define RT1739_VCONN_ORIENT_CC2			MASK_CLR
-
-#define RT1739_REG_VCONN_CTRL3		0x33
-#define RT1739_VCONN_CLIMIT_EN		BIT(0)
-
-#define RT1739_REG_SBU_CTRL_01		0x38
-#define RT1739_SBUSW_MUX_SEL		BIT(4)
-#define RT1739_DM_SWEN				BIT(1)
-#define RT1739_DP_SWEN				BIT(0)
-
-#define RT1739_REG_BC12_SNK_FUNC	0x40
-#define RT1739_BC12_SNK_EN			BIT(7)
-
-#define RT1739_REG_BC12_STAT		0x41
-#define RT1739_PORT_STAT_MASK			0x0F
-#define RT1739_PORT_STAT_SDP			0x0D
-#define RT1739_PORT_STAT_CDP			0x0E
-#define RT1739_PORT_STAT_DCP			0x0F
-
-#define RT1739_REG_SYS_CTRL1		0x60
-#define RT1739_OSC640K_FORCE_EN			BIT(3)
+#define RT1739_REG_DEVICE_ID0 0x02
+#define RT1739_DEVICE_ID_ES1 0x11
+#define RT1739_DEVICE_ID_ES2 0x12
+
+#define RT1739_REG_SW_RESET 0x04
+#define RT1739_SW_RESET BIT(0)
+
+#define RT1739_REG_INT_MASK4 0x0C
+#define RT1739_FRS_RX_MASK BIT(4)
+
+#define RT1739_REG_INT_MASK5 0x0D
+#define RT1739_BC12_SNK_DONE_MASK BIT(0)
+
+#define RT1739_REG_INT_EVENT4 0x14
+
+#define RT1739_REG_INT_EVENT5 0x15
+#define RT1739_BC12_SNK_DONE_INT BIT(0)
+
+#define RT1739_REG_INT_STS4 0x1C
+#define RT1739_VBUS_VALID BIT(2)
+#define RT1739_VBUS_PRESENT BIT(0)
+
+#define RT1739_REG_SYS_CTRL 0x20
+#define RT1739_OT_EN BIT(4)
+#define RT1739_SHUTDOWN_OFF BIT(0)
+
+#define RT1739_REG_VBUS_SWITCH_CTRL 0x21
+#define RT1739_LV_SRC_EN BIT(2)
+#define RT1739_HV_SRC_EN BIT(1)
+#define RT1739_HV_SNK_EN BIT(0)
+
+#define RT1739_REG_VBUS_CTRL1 0x23
+#define RT1739_HVLV_SCP_EN BIT(1)
+#define RT1739_HVLV_OCRC_EN BIT(0)
+
+#define RT1739_REG_VBUS_OV_SETTING 0x24
+
+#define RT1739_VBUS_OVP_SEL_SHIFT 0
+#define RT1739_VIN_HV_OVP_SEL_SHIFT 4
+#define RT1739_OVP_SEL_6_0V 0
+#define RT1739_OVP_SEL_6_8V 1
+#define RT1739_OVP_SEL_10_0V 2
+#define RT1739_OVP_SEL_11_5V 3
+#define RT1739_OVP_SEL_14_0V 4
+#define RT1739_OVP_SEL_17_0V 5
+#define RT1739_OVP_SEL_23_0V 6
+
+#define RT1739_REG_VBUS_OC_SETTING 0x25
+
+#define RT1739_LV_SRC_OCP_SHIFT 4
+#define RT1739_LV_SRC_OCP_SEL_1_25A (0 << RT1739_LV_SRC_OCP_SHIFT)
+#define RT1739_LV_SRC_OCP_SEL_1_75A (1 << RT1739_LV_SRC_OCP_SHIFT)
+#define RT1739_LV_SRC_OCP_SEL_2_25A (2 << RT1739_LV_SRC_OCP_SHIFT)
+#define RT1739_LV_SRC_OCP_SEL_3_3A (3 << RT1739_LV_SRC_OCP_SHIFT)
+
+#define RT1739_HV_SINK_OCP_SHIFT 0
+#define RT1739_HV_SINK_OCP_SEL_1_25A (0 << RT1739_HV_SINK_OCP_SHIFT)
+#define RT1739_HV_SINK_OCP_SEL_1_75A (1 << RT1739_HV_SINK_OCP_SHIFT)
+#define RT1739_HV_SINK_OCP_SEL_3_3A (2 << RT1739_HV_SINK_OCP_SHIFT)
+#define RT1739_HV_SINK_OCP_SEL_5_5A (3 << RT1739_HV_SINK_OCP_SHIFT)
+
+#define RT1739_VBUS_FAULT_DIS 0x26
+#define RT1739_OVP_DISVBUS_EN BIT(6)
+#define RT1739_UVLO_DISVBUS_EN BIT(5)
+#define RT1739_SRCP_DISVBUS_EN BIT(4)
+#define RT1739_RCP_DISVBUS_EN BIT(3)
+#define RT1739_SCP_DISVBUS_EN BIT(2)
+#define RT1739_OCPS_DISVBUS_EN BIT(1)
+#define RT1739_OCP_DISVBUS_EN BIT(0)
+
+#define RT1739_REG_VBUS_DET_EN 0x27
+#define RT1739_VBUS_SAFE5V_EN BIT(2)
+#define RT1739_VBUS_SAFE0V_EN BIT(1)
+#define RT1739_VBUS_PRESENT_EN BIT(0)
+
+#define RT1739_REG_CC_FRS_CTRL1 0x2D
+#define RT1739_FRS_RX_EN BIT(1)
+
+#define RT1739_REG_VCONN_CTRL1 0x31
+#define RT1739_VCONN_ORIENT BIT(1)
+#define RT1739_VCONN_EN BIT(0)
+
+#define RT1739_VCONN_ORIENT_CC1 MASK_SET
+#define RT1739_VCONN_ORIENT_CC2 MASK_CLR
+
+#define RT1739_REG_VCONN_CTRL3 0x33
+#define RT1739_VCONN_CLIMIT_EN BIT(0)
+
+#define RT1739_REG_SBU_CTRL_01 0x38
+#define RT1739_SBUSW_MUX_SEL BIT(4)
+#define RT1739_DM_SWEN BIT(1)
+#define RT1739_DP_SWEN BIT(0)
+
+#define RT1739_REG_BC12_SNK_FUNC 0x40
+#define RT1739_BC12_SNK_EN BIT(7)
+
+#define RT1739_REG_BC12_STAT 0x41
+#define RT1739_PORT_STAT_MASK 0x0F
+#define RT1739_PORT_STAT_SDP 0x0D
+#define RT1739_PORT_STAT_CDP 0x0E
+#define RT1739_PORT_STAT_DCP 0x0F
+
+#define RT1739_REG_SYS_CTRL1 0x60
+#define RT1739_OSC640K_FORCE_EN BIT(3)
 
 extern const struct ppc_drv rt1739_ppc_drv;
 extern const struct bc12_drv rt1739_bc12_drv;
diff --git a/driver/ppc/sn5s330.c b/driver/ppc/sn5s330.c
index 6a157b005e..385f27fe52 100644
--- a/driver/ppc/sn5s330.c
+++ b/driver/ppc/sn5s330.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,8 +23,8 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 static atomic_t irq_pending; /* Bitmask of ports signaling an interrupt. */
 static int source_enabled[CONFIG_USB_PD_PORT_MAX_COUNT];
@@ -32,17 +32,13 @@ static int source_enabled[CONFIG_USB_PD_PORT_MAX_COUNT];
 static int read_reg(uint8_t port, int reg, int *regval)
 {
 	return i2c_read8(ppc_chips[port].i2c_port,
-			 ppc_chips[port].i2c_addr_flags,
-			 reg,
-			 regval);
+			 ppc_chips[port].i2c_addr_flags, reg, regval);
 }
 
 static int write_reg(uint8_t port, int reg, int regval)
 {
 	return i2c_write8(ppc_chips[port].i2c_port,
-			  ppc_chips[port].i2c_addr_flags,
-			  reg,
-			  regval);
+			  ppc_chips[port].i2c_addr_flags, reg, regval);
 }
 
 static int set_flags(const int port, const int addr, const int flags_to_set)
@@ -58,7 +54,6 @@ static int set_flags(const int port, const int addr, const int flags_to_set)
 	return write_reg(port, addr, val);
 }
 
-
 static int clr_flags(const int port, const int addr, const int flags_to_clear)
 {
 	int val, rv;
@@ -85,9 +80,7 @@ static int sn5s330_dump(int port)
 	for (i = SN5S330_FUNC_SET1; i <= SN5S330_FUNC_SET12; i++) {
 		i2c_read8(i2c_port, i2c_addr_flags, i, &data);
 		ccprintf("FUNC_SET%d [%02Xh] = 0x%02x\n",
-			 i - SN5S330_FUNC_SET1 + 1,
-			 i,
-			 data);
+			 i - SN5S330_FUNC_SET1 + 1, i, data);
 	}
 
 	cflush();
@@ -95,9 +88,7 @@ static int sn5s330_dump(int port)
 	for (i = SN5S330_INT_STATUS_REG1; i <= SN5S330_INT_STATUS_REG4; i++) {
 		i2c_read8(i2c_port, i2c_addr_flags, i, &data);
 		ccprintf("INT_STATUS_REG%d [%02Xh] = 0x%02x\n",
-			 i - SN5S330_INT_STATUS_REG1 + 1,
-			 i,
-			 data);
+			 i - SN5S330_INT_STATUS_REG1 + 1, i, data);
 	}
 
 	cflush();
@@ -106,9 +97,7 @@ static int sn5s330_dump(int port)
 	     i++) {
 		i2c_read8(i2c_port, i2c_addr_flags, i, &data);
 		ccprintf("INT_TRIP_RISE_REG%d [%02Xh] = 0x%02x\n",
-			 i - SN5S330_INT_TRIP_RISE_REG1 + 1,
-			 i,
-			 data);
+			 i - SN5S330_INT_TRIP_RISE_REG1 + 1, i, data);
 	}
 
 	cflush();
@@ -117,9 +106,7 @@ static int sn5s330_dump(int port)
 	     i++) {
 		i2c_read8(i2c_port, i2c_addr_flags, i, &data);
 		ccprintf("INT_TRIP_FALL_REG%d [%02Xh] = 0x%02x\n",
-			 i - SN5S330_INT_TRIP_FALL_REG1 + 1,
-			 i,
-			 data);
+			 i - SN5S330_INT_TRIP_FALL_REG1 + 1, i, data);
 	}
 
 	cflush();
@@ -128,9 +115,7 @@ static int sn5s330_dump(int port)
 	     i++) {
 		i2c_read8(i2c_port, i2c_addr_flags, i, &data);
 		ccprintf("INT_MASK_RISE_REG%d [%02Xh] = 0x%02x\n",
-			 i - SN5S330_INT_MASK_RISE_REG1 + 1,
-			 i,
-			 data);
+			 i - SN5S330_INT_MASK_RISE_REG1 + 1, i, data);
 	}
 
 	cflush();
@@ -139,9 +124,7 @@ static int sn5s330_dump(int port)
 	     i++) {
 		i2c_read8(i2c_port, i2c_addr_flags, i, &data);
 		ccprintf("INT_MASK_FALL_REG%d [%02Xh] = 0x%02x\n",
-			 i - SN5S330_INT_MASK_FALL_REG1 + 1,
-			 i,
-			 data);
+			 i - SN5S330_INT_MASK_FALL_REG1 + 1, i, data);
 	}
 
 	cflush();
@@ -165,8 +148,8 @@ static int sn5s330_pp_fet_enable(uint8_t port, enum sn5s330_pp_idx pp,
 		return EC_ERROR_INVAL;
 	/* LCOV_EXCL_STOP */
 
-	status = enable ? set_flags(port, SN5S330_FUNC_SET3, pp_bit)
-			: clr_flags(port, SN5S330_FUNC_SET3, pp_bit);
+	status = enable ? set_flags(port, SN5S330_FUNC_SET3, pp_bit) :
+			  clr_flags(port, SN5S330_FUNC_SET3, pp_bit);
 
 	if (status) {
 		ppc_prints("Failed to set FUNC_SET3!", port);
@@ -185,7 +168,7 @@ static int sn5s330_init(int port)
 	int status;
 	int retries;
 	int reg;
-	const int i2c_port  = ppc_chips[port].i2c_port;
+	const int i2c_port = ppc_chips[port].i2c_port;
 	const uint16_t i2c_addr_flags = ppc_chips[port].i2c_addr_flags;
 
 #ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
@@ -213,11 +196,10 @@ static int sn5s330_init(int port)
 	 */
 	retries = 0;
 	do {
-		status = i2c_write8(i2c_port, i2c_addr_flags,
-				    SN5S330_FUNC_SET1, regval);
+		status = i2c_write8(i2c_port, i2c_addr_flags, SN5S330_FUNC_SET1,
+				    regval);
 		if (status) {
-			ppc_prints("Failed to set FUNC_SET1! Retrying..",
-				port);
+			ppc_prints("Failed to set FUNC_SET1! Retrying..", port);
 			retries++;
 			msleep(1);
 		} else {
@@ -227,24 +209,24 @@ static int sn5s330_init(int port)
 
 	/* Set Vbus OVP threshold to ~22.325V. */
 	regval = 0x37;
-	status = i2c_write8(i2c_port, i2c_addr_flags,
-			    SN5S330_FUNC_SET5, regval);
+	status =
+		i2c_write8(i2c_port, i2c_addr_flags, SN5S330_FUNC_SET5, regval);
 	if (status) {
 		ppc_prints("Failed to set FUNC_SET5!", port);
 		return status;
 	}
 
 	/* Set Vbus UVP threshold to ~2.75V. */
-	status = i2c_read8(i2c_port, i2c_addr_flags,
-			   SN5S330_FUNC_SET6, &regval);
+	status =
+		i2c_read8(i2c_port, i2c_addr_flags, SN5S330_FUNC_SET6, &regval);
 	if (status) {
 		ppc_prints("Failed to read FUNC_SET6!", port);
 		return status;
 	}
 	regval &= ~0x3F;
 	regval |= 1;
-	status = i2c_write8(i2c_port, i2c_addr_flags,
-			    SN5S330_FUNC_SET6, regval);
+	status =
+		i2c_write8(i2c_port, i2c_addr_flags, SN5S330_FUNC_SET6, regval);
 	if (status) {
 		ppc_prints("Failed to write FUNC_SET6!", port);
 		return status;
@@ -252,8 +234,8 @@ static int sn5s330_init(int port)
 
 	/* Enable SBU Fets and set PP2 current limit to ~3A. */
 	regval = SN5S330_SBU_EN | 0x8;
-	status = i2c_write8(i2c_port, i2c_addr_flags,
-			    SN5S330_FUNC_SET2, regval);
+	status =
+		i2c_write8(i2c_port, i2c_addr_flags, SN5S330_FUNC_SET2, regval);
 	if (status) {
 		ppc_prints("Failed to set FUNC_SET2!", port);
 		return status;
@@ -272,8 +254,8 @@ static int sn5s330_init(int port)
 	 * low voltage protection).
 	 */
 	regval = SN5S330_OVP_EN_CC | SN5S330_PP2_CONFIG | SN5S330_CONFIG_UVP;
-	status = i2c_write8(i2c_port, i2c_addr_flags,
-			    SN5S330_FUNC_SET9, regval);
+	status =
+		i2c_write8(i2c_port, i2c_addr_flags, SN5S330_FUNC_SET9, regval);
 	if (status) {
 		ppc_prints("Failed to set FUNC_SET9!", port);
 		return status;
@@ -284,7 +266,7 @@ static int sn5s330_init(int port)
 	 * set 1000 us for PP2 for compatibility.
 	 */
 	regval = (PPX_ILIM_DEGLITCH_0_US_200 << 3) |
-		  PPX_ILIM_DEGLITCH_0_US_1000;
+		 PPX_ILIM_DEGLITCH_0_US_1000;
 	status = i2c_write8(i2c_port, i2c_addr_flags, SN5S330_FUNC_SET11,
 			    regval);
 	if (status) {
@@ -299,16 +281,16 @@ static int sn5s330_init(int port)
 	 * reset default (20 us).
 	 */
 	regval = 0;
-	status = i2c_read8(i2c_port, i2c_addr_flags,
-			   SN5S330_FUNC_SET8, &regval);
+	status =
+		i2c_read8(i2c_port, i2c_addr_flags, SN5S330_FUNC_SET8, &regval);
 	if (status) {
 		ppc_prints("Failed to read FUNC_SET8!", port);
 		return status;
 	}
 	regval &= ~SN5S330_VCONN_DEGLITCH_MASK;
 	regval |= SN5S330_VCONN_DEGLITCH_640_US;
-	status = i2c_write8(i2c_port, i2c_addr_flags,
-			    SN5S330_FUNC_SET8, regval);
+	status =
+		i2c_write8(i2c_port, i2c_addr_flags, SN5S330_FUNC_SET8, regval);
 	if (status) {
 		ppc_prints("Failed to set FUNC_SET8!", port);
 		return status;
@@ -366,8 +348,8 @@ static int sn5s330_init(int port)
 	 * is checked below.
 	 */
 	regval = SN5S330_DIG_RES | SN5S330_VSAFE0V_MASK;
-	status = i2c_write8(i2c_port, i2c_addr_flags,
-			    SN5S330_INT_STATUS_REG4, regval);
+	status = i2c_write8(i2c_port, i2c_addr_flags, SN5S330_INT_STATUS_REG4,
+			    regval);
 	if (status) {
 		ppc_prints("Failed to write INT_STATUS_REG4!", port);
 		return status;
@@ -418,7 +400,7 @@ static int sn5s330_init(int port)
 	regval = ~SN5S330_VBUS_GOOD_MASK;
 #else
 	regval = 0xFF;
-#endif  /* CONFIG_USB_PD_VBUS_DETECT_PPC && CONFIG_USB_CHARGER */
+#endif /* CONFIG_USB_PD_VBUS_DETECT_PPC && CONFIG_USB_CHARGER */
 
 	status = i2c_write8(i2c_port, i2c_addr_flags,
 			    SN5S330_INT_MASK_RISE_REG3, regval);
@@ -436,24 +418,21 @@ static int sn5s330_init(int port)
 
 	/* Now clear any pending interrupts. */
 	for (reg = SN5S330_INT_TRIP_RISE_REG1;
-	     reg <= SN5S330_INT_TRIP_FALL_REG3;
-	     reg++) {
-		status = i2c_write8(i2c_port, i2c_addr_flags,
-				    reg, 0xFF);
+	     reg <= SN5S330_INT_TRIP_FALL_REG3; reg++) {
+		status = i2c_write8(i2c_port, i2c_addr_flags, reg, 0xFF);
 		if (status) {
-			CPRINTS("ppc p%d: Failed to write reg 0x%2x!",
-				port, reg);
+			CPRINTS("ppc p%d: Failed to write reg 0x%2x!", port,
+				reg);
 			return status;
 		}
 	}
 
-
 	/*
 	 * For PP2, check to see if we booted in dead battery mode.  If we
 	 * booted in dead battery mode, the PP2 FET will already be enabled.
 	 */
-	status = i2c_read8(i2c_port, i2c_addr_flags,
-			   SN5S330_INT_STATUS_REG4, &regval);
+	status = i2c_read8(i2c_port, i2c_addr_flags, SN5S330_INT_STATUS_REG4,
+			   &regval);
 	if (status) {
 		ppc_prints("Failed to read INT_STATUS_REG4!", port);
 		return status;
@@ -464,8 +443,8 @@ static int sn5s330_init(int port)
 		 * Clear the bit by writing 1 and keep vSafe0V_MASK
 		 * unchanged.
 		 */
-		i2c_write8(i2c_port, i2c_addr_flags,
-			   SN5S330_INT_STATUS_REG4, regval);
+		i2c_write8(i2c_port, i2c_addr_flags, SN5S330_INT_STATUS_REG4,
+			   regval);
 
 		/*
 		 * Turn on PP2 FET.
@@ -559,13 +538,13 @@ static int sn5s330_set_vbus_source_current_limit(int port,
 static int sn5s330_discharge_vbus(int port, int enable)
 {
 	int status = enable ? set_flags(port, SN5S330_FUNC_SET3,
-					SN5S330_VBUS_DISCH_EN)
-			    : clr_flags(port, SN5S330_FUNC_SET3,
+					SN5S330_VBUS_DISCH_EN) :
+			      clr_flags(port, SN5S330_FUNC_SET3,
 					SN5S330_VBUS_DISCH_EN);
 
 	if (status) {
-		CPRINTS("ppc p%d: Failed to %s vbus discharge",
-			port, enable ? "enable" : "disable");
+		CPRINTS("ppc p%d: Failed to %s vbus discharge", port,
+			enable ? "enable" : "disable");
 		return status;
 	}
 
@@ -681,7 +660,8 @@ static void sn5s330_handle_interrupt(int port)
 
 		if (attempt > 1)
 			ppc_prints("Could not clear interrupts on first "
-				"try, retrying", port);
+				   "try, retrying",
+				   port);
 
 		read_reg(port, SN5S330_INT_TRIP_RISE_REG1, &rise);
 		read_reg(port, SN5S330_INT_TRIP_FALL_REG1, &fall);
@@ -719,16 +699,15 @@ static void sn5s330_handle_interrupt(int port)
 		read_reg(port, SN5S330_INT_TRIP_FALL_REG3, &fall);
 
 		/* Inform other modules about VBUS level */
-		if (rise & SN5S330_VBUS_GOOD_MASK
-		    || fall & SN5S330_VBUS_GOOD_MASK)
+		if (rise & SN5S330_VBUS_GOOD_MASK ||
+		    fall & SN5S330_VBUS_GOOD_MASK)
 			usb_charger_vbus_change(port,
 						sn5s330_is_vbus_present(port));
 
 		/* Clear the interrupt sources. */
 		write_reg(port, SN5S330_INT_TRIP_RISE_REG3, rise);
 		write_reg(port, SN5S330_INT_TRIP_FALL_REG3, fall);
-#endif  /* CONFIG_USB_PD_VBUS_DETECT_PPC && CONFIG_USB_CHARGER */
-
+#endif /* CONFIG_USB_PD_VBUS_DETECT_PPC && CONFIG_USB_CHARGER */
 	}
 }
 
diff --git a/driver/ppc/sn5s330.h b/driver/ppc/sn5s330.h
index 9768906182..70a46920ee 100644
--- a/driver/ppc/sn5s330.h
+++ b/driver/ppc/sn5s330.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,15 +27,15 @@ enum sn5s330_pp_idx {
 	SN5S330_PP_COUNT,
 };
 
-#define SN5S330_FUNC_SET1  0x50
-#define SN5S330_FUNC_SET2  0x51
-#define SN5S330_FUNC_SET3  0x52
-#define SN5S330_FUNC_SET4  0x53
-#define SN5S330_FUNC_SET5  0x54
-#define SN5S330_FUNC_SET6  0x55
-#define SN5S330_FUNC_SET7  0x56
-#define SN5S330_FUNC_SET8  0x57
-#define SN5S330_FUNC_SET9  0x58
+#define SN5S330_FUNC_SET1 0x50
+#define SN5S330_FUNC_SET2 0x51
+#define SN5S330_FUNC_SET3 0x52
+#define SN5S330_FUNC_SET4 0x53
+#define SN5S330_FUNC_SET5 0x54
+#define SN5S330_FUNC_SET6 0x55
+#define SN5S330_FUNC_SET7 0x56
+#define SN5S330_FUNC_SET8 0x57
+#define SN5S330_FUNC_SET9 0x58
 #define SN5S330_FUNC_SET10 0x59
 #define SN5S330_FUNC_SET11 0x5A
 #define SN5S330_FUNC_SET12 0x5B
@@ -62,72 +62,72 @@ enum sn5s330_pp_idx {
 #define SN5S330_INT_MASK_FALL_REG2 0x2A
 #define SN5S330_INT_MASK_FALL_REG3 0x2B
 
-#define PPX_ILIM_DEGLITCH_0_US_20     0x1
-#define PPX_ILIM_DEGLITCH_0_US_50     0x2
-#define PPX_ILIM_DEGLITCH_0_US_100    0x3
-#define PPX_ILIM_DEGLITCH_0_US_200    0x4
-#define PPX_ILIM_DEGLITCH_0_US_1000   0x5
-#define PPX_ILIM_DEGLITCH_0_US_2000   0x6
-#define PPX_ILIM_DEGLITCH_0_US_10000  0x7
+#define PPX_ILIM_DEGLITCH_0_US_20 0x1
+#define PPX_ILIM_DEGLITCH_0_US_50 0x2
+#define PPX_ILIM_DEGLITCH_0_US_100 0x3
+#define PPX_ILIM_DEGLITCH_0_US_200 0x4
+#define PPX_ILIM_DEGLITCH_0_US_1000 0x5
+#define PPX_ILIM_DEGLITCH_0_US_2000 0x6
+#define PPX_ILIM_DEGLITCH_0_US_10000 0x7
 
 /* Internal VBUS Switch Current Limit Settings (min) */
-#define SN5S330_ILIM_0_35  0
-#define SN5S330_ILIM_0_63  1
-#define SN5S330_ILIM_0_90  2
-#define SN5S330_ILIM_1_14  3
-#define SN5S330_ILIM_1_38  4
-#define SN5S330_ILIM_1_62  5
-#define SN5S330_ILIM_1_86  6
-#define SN5S330_ILIM_2_10  7
-#define SN5S330_ILIM_2_34  8
-#define SN5S330_ILIM_2_58  9
-#define SN5S330_ILIM_2_82  10
-#define SN5S330_ILIM_3_06  11
-#define SN5S330_ILIM_3_30  12
+#define SN5S330_ILIM_0_35 0
+#define SN5S330_ILIM_0_63 1
+#define SN5S330_ILIM_0_90 2
+#define SN5S330_ILIM_1_14 3
+#define SN5S330_ILIM_1_38 4
+#define SN5S330_ILIM_1_62 5
+#define SN5S330_ILIM_1_86 6
+#define SN5S330_ILIM_2_10 7
+#define SN5S330_ILIM_2_34 8
+#define SN5S330_ILIM_2_58 9
+#define SN5S330_ILIM_2_82 10
+#define SN5S330_ILIM_3_06 11
+#define SN5S330_ILIM_3_30 12
 
 /* FUNC_SET_2 */
-#define SN5S330_SBU_EN			BIT(4)
+#define SN5S330_SBU_EN BIT(4)
 
 /* FUNC_SET_3 */
-#define SN5S330_PP1_EN			BIT(0)
-#define SN5S330_PP2_EN			BIT(1)
-#define SN5S330_VBUS_DISCH_EN		BIT(2)
-#define SN5S330_SET_RCP_MODE_PP1	BIT(5)
-#define SN5S330_SET_RCP_MODE_PP2	BIT(6)
+#define SN5S330_PP1_EN BIT(0)
+#define SN5S330_PP2_EN BIT(1)
+#define SN5S330_VBUS_DISCH_EN BIT(2)
+#define SN5S330_SET_RCP_MODE_PP1 BIT(5)
+#define SN5S330_SET_RCP_MODE_PP2 BIT(6)
 
 /* FUNC_SET_4 */
-#define SN5S330_VCONN_EN		BIT(0)
-#define SN5S330_CC_POLARITY		BIT(1)
-#define SN5S330_CC_EN			BIT(4)
-#define SN5S330_VCONN_ILIM_SEL		BIT(5)
+#define SN5S330_VCONN_EN BIT(0)
+#define SN5S330_CC_POLARITY BIT(1)
+#define SN5S330_CC_EN BIT(4)
+#define SN5S330_VCONN_ILIM_SEL BIT(5)
 
 /* FUNC_SET_8 */
-#define SN5S330_VCONN_DEGLITCH_MASK	(3 << 6)
-#define SN5S330_VCONN_DEGLITCH_63_US	(0 << 6)
-#define SN5S330_VCONN_DEGLITCH_125_US	BIT(6)
-#define SN5S330_VCONN_DEGLITCH_640_US	(2 << 6)
-#define SN5S330_VCONN_DEGLITCH_1280_US	(3 << 6)
+#define SN5S330_VCONN_DEGLITCH_MASK (3 << 6)
+#define SN5S330_VCONN_DEGLITCH_63_US (0 << 6)
+#define SN5S330_VCONN_DEGLITCH_125_US BIT(6)
+#define SN5S330_VCONN_DEGLITCH_640_US (2 << 6)
+#define SN5S330_VCONN_DEGLITCH_1280_US (3 << 6)
 
 /* FUNC_SET_9 */
-#define SN5S330_FORCE_OVP_EN_SBU	BIT(1)
-#define SN5S330_PP2_CONFIG		BIT(2)
-#define SN5S330_PWR_OVR_VBUS		BIT(3)
-#define SN5S330_OVP_EN_CC		BIT(4)
-#define SN5S330_CONFIG_UVP		BIT(5)
-#define SN5S330_FORCE_ON_VBUS_OVP	BIT(6)
-#define SN5S330_FORCE_ON_VBUS_UVP	BIT(7)
+#define SN5S330_FORCE_OVP_EN_SBU BIT(1)
+#define SN5S330_PP2_CONFIG BIT(2)
+#define SN5S330_PWR_OVR_VBUS BIT(3)
+#define SN5S330_OVP_EN_CC BIT(4)
+#define SN5S330_CONFIG_UVP BIT(5)
+#define SN5S330_FORCE_ON_VBUS_OVP BIT(6)
+#define SN5S330_FORCE_ON_VBUS_UVP BIT(7)
 
 /* INT_STATUS_REG3 */
-#define SN5S330_VBUS_GOOD		BIT(0)
+#define SN5S330_VBUS_GOOD BIT(0)
 
 /* INT_STATUS_REG4 */
-#define SN5S330_DIG_RES			BIT(0)
-#define SN5S330_DB_BOOT			BIT(1)
-#define SN5S330_VSAFE0V_STAT		BIT(2)
-#define SN5S330_VSAFE0V_MASK		BIT(3)
+#define SN5S330_DIG_RES BIT(0)
+#define SN5S330_DB_BOOT BIT(1)
+#define SN5S330_VSAFE0V_STAT BIT(2)
+#define SN5S330_VSAFE0V_MASK BIT(3)
 
 /* FUNC_SET_10 */
-#define SN5S330_PP1_RCP_OFFSET		BIT(4)
+#define SN5S330_PP1_RCP_OFFSET BIT(4)
 
 /*
  * INT_MASK_RISE/FALL_EDGE_1
diff --git a/driver/ppc/syv682x.c b/driver/ppc/syv682x.c
index 22ff51f3d2..88c6443ad0 100644
--- a/driver/ppc/syv682x.c
+++ b/driver/ppc/syv682x.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,16 +21,16 @@
 #include "usb_pd.h"
 #include "util.h"
 
-#define SYV682X_FLAGS_SOURCE_ENABLED	BIT(0)
-#define SYV682X_FLAGS_SINK_ENABLED	BIT(1)
+#define SYV682X_FLAGS_SOURCE_ENABLED BIT(0)
+#define SYV682X_FLAGS_SINK_ENABLED BIT(1)
 /* 0 -> CC1, 1 -> CC2 */
-#define SYV682X_FLAGS_CC_POLARITY	BIT(2)
-#define SYV682X_FLAGS_VBUS_PRESENT	BIT(3)
-#define SYV682X_FLAGS_TSD		BIT(4)
-#define SYV682X_FLAGS_OVP		BIT(5)
-#define SYV682X_FLAGS_5V_OC		BIT(6)
-#define SYV682X_FLAGS_FRS		BIT(7)
-#define SYV682X_FLAGS_VCONN_OCP		BIT(8)
+#define SYV682X_FLAGS_CC_POLARITY BIT(2)
+#define SYV682X_FLAGS_VBUS_PRESENT BIT(3)
+#define SYV682X_FLAGS_TSD BIT(4)
+#define SYV682X_FLAGS_OVP BIT(5)
+#define SYV682X_FLAGS_5V_OC BIT(6)
+#define SYV682X_FLAGS_FRS BIT(7)
+#define SYV682X_FLAGS_VCONN_OCP BIT(8)
 
 static atomic_t irq_pending; /* Bitmask of ports signaling an interrupt. */
 static atomic_t flags[CONFIG_USB_PD_PORT_MAX_COUNT];
@@ -39,7 +39,7 @@ static atomic_t sink_ocp_count[CONFIG_USB_PD_PORT_MAX_COUNT];
 static timestamp_t vbus_oc_timer[CONFIG_USB_PD_PORT_MAX_COUNT];
 static timestamp_t vconn_oc_timer[CONFIG_USB_PD_PORT_MAX_COUNT];
 
-#define SYV682X_VBUS_DET_THRESH_MV		4000
+#define SYV682X_VBUS_DET_THRESH_MV 4000
 /* Longest time that can be programmed in DSG_TIME field */
 #define SYV682X_MAX_VBUS_DISCHARGE_TIME_MS 400
 /*
@@ -68,9 +68,10 @@ static timestamp_t vconn_oc_timer[CONFIG_USB_PD_PORT_MAX_COUNT];
 "instead of the TCPC"
 #endif
 
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
-static int syv682x_vbus_sink_enable(int port, int enable);
+	static int
+	syv682x_vbus_sink_enable(int port, int enable);
 
 static int syv682x_init(int port);
 
@@ -79,9 +80,7 @@ static void syv682x_interrupt_delayed(int port, int delay);
 static int read_reg(uint8_t port, int reg, int *regval)
 {
 	return i2c_read8(ppc_chips[port].i2c_port,
-			 ppc_chips[port].i2c_addr_flags,
-			 reg,
-			 regval);
+			 ppc_chips[port].i2c_addr_flags, reg, regval);
 }
 
 #ifdef CONFIG_USBC_PPC_SYV682C
@@ -107,8 +106,8 @@ static int syv682x_wait_for_ready(int port, int reg)
 		return EC_SUCCESS;
 #endif
 
-	deadline.val = get_time().val
-			+ (SYV682X_MAX_VBUS_DISCHARGE_TIME_MS * MSEC);
+	deadline.val =
+		get_time().val + (SYV682X_MAX_VBUS_DISCHARGE_TIME_MS * MSEC);
 
 	do {
 		rv = read_reg(port, SYV682X_CONTROL_3_REG, &regval);
@@ -138,9 +137,7 @@ static int write_reg(uint8_t port, int reg, int regval)
 		return rv;
 
 	return i2c_write8(ppc_chips[port].i2c_port,
-			  ppc_chips[port].i2c_addr_flags,
-			  reg,
-			  regval);
+			  ppc_chips[port].i2c_addr_flags, reg, regval);
 }
 
 static int syv682x_is_sourcing_vbus(int port)
@@ -186,8 +183,8 @@ static int syv682x_vbus_source_enable(int port, int enable)
 
 	if (enable) {
 		/* Select 5V path and turn on channel */
-		regval &= ~(SYV682X_CONTROL_1_CH_SEL |
-			    SYV682X_CONTROL_1_PWR_ENB);
+		regval &=
+			~(SYV682X_CONTROL_1_CH_SEL | SYV682X_CONTROL_1_PWR_ENB);
 		/* Disable HV Sink path */
 		regval |= SYV682X_CONTROL_1_HV_DR;
 	} else if (flags[port] & SYV682X_FLAGS_SOURCE_ENABLED) {
@@ -416,8 +413,8 @@ static int syv682x_vbus_sink_enable(int port, int enable)
 		/* Select high voltage path */
 		regval |= SYV682X_CONTROL_1_CH_SEL;
 		/* Select Sink mode and turn on the channel */
-		regval &= ~(SYV682X_CONTROL_1_HV_DR |
-			    SYV682X_CONTROL_1_PWR_ENB);
+		regval &=
+			~(SYV682X_CONTROL_1_HV_DR | SYV682X_CONTROL_1_PWR_ENB);
 		/* Set sink current limit to the configured value */
 		regval |= CONFIG_SYV682X_HV_ILIM << SYV682X_HV_ILIM_BIT_SHIFT;
 		atomic_clear_bits(&flags[port], SYV682X_FLAGS_SOURCE_ENABLED);
@@ -567,8 +564,8 @@ static int syv682x_dump(int port)
 			ccprintf("ppc_syv682[p%d]: Failed to read reg 0x%02x\n",
 				 port, reg_addr);
 		else
-			ccprintf("ppc_syv682[p%d]: reg 0x%02x = 0x%02x\n",
-				 port, reg_addr, data);
+			ccprintf("ppc_syv682[p%d]: reg 0x%02x = 0x%02x\n", port,
+				 reg_addr, data);
 	}
 
 	cflush();
@@ -652,10 +649,10 @@ static int syv682x_set_frs_enable(int port, int enable)
 		 * should be set.
 		 */
 		regval &= ~(SYV682X_CONTROL_4_CC1_BPS |
-				SYV682X_CONTROL_4_CC2_BPS);
+			    SYV682X_CONTROL_4_CC2_BPS);
 		regval |= flags[port] & SYV682X_FLAGS_CC_POLARITY ?
-					SYV682X_CONTROL_4_CC2_BPS :
-					SYV682X_CONTROL_4_CC1_BPS;
+				  SYV682X_CONTROL_4_CC2_BPS :
+				  SYV682X_CONTROL_4_CC1_BPS;
 		/* set GPIO after configuring */
 		write_reg(port, SYV682X_CONTROL_4_REG, regval);
 		gpio_or_ioex_set_level(ppc_chips[port].frs_en, 1);
@@ -705,9 +702,9 @@ static bool syv682x_is_sink(uint8_t control_1)
 	 *
 	 * The SYV682 is only a sink when !HV_DR && CH_SEL
 	 */
-	if (!(control_1 & SYV682X_CONTROL_1_PWR_ENB)
-		&& !(control_1 & SYV682X_CONTROL_1_HV_DR)
-		&& (control_1 & SYV682X_CONTROL_1_CH_SEL))
+	if (!(control_1 & SYV682X_CONTROL_1_PWR_ENB) &&
+	    !(control_1 & SYV682X_CONTROL_1_HV_DR) &&
+	    (control_1 & SYV682X_CONTROL_1_CH_SEL))
 		return true;
 
 	return false;
@@ -735,8 +732,7 @@ static int syv682x_init(int port)
 	if (IS_ENABLED(CONFIG_USB_PD_FRS_PPC))
 		gpio_or_ioex_set_level(ppc_chips[port].frs_en, 0);
 
-	if (!syv682x_is_sink(control_1)
-		|| (status & SYV682X_STATUS_VSAFE_0V)) {
+	if (!syv682x_is_sink(control_1) || (status & SYV682X_STATUS_VSAFE_0V)) {
 		/*
 		 * Disable both power paths,
 		 * set HV_ILIM to 3.3A,
@@ -745,9 +741,9 @@ static int syv682x_init(int port)
 		 * select HV channel.
 		 */
 		regval = SYV682X_CONTROL_1_PWR_ENB |
-			(CONFIG_SYV682X_HV_ILIM << SYV682X_HV_ILIM_BIT_SHIFT) |
-			/* !SYV682X_CONTROL_1_HV_DR */
-			SYV682X_CONTROL_1_CH_SEL;
+			 (CONFIG_SYV682X_HV_ILIM << SYV682X_HV_ILIM_BIT_SHIFT) |
+			 /* !SYV682X_CONTROL_1_HV_DR */
+			 SYV682X_CONTROL_1_CH_SEL;
 		rv = write_reg(port, SYV682X_CONTROL_1_REG, regval);
 		if (rv)
 			return rv;
@@ -775,9 +771,9 @@ static int syv682x_init(int port)
 	 * tVconnOff (35ms) timeout.
 	 * On SYV682C, we are allowed to access CONTROL4 while the i2c busy.
 	 */
-	regval = (SYV682X_OC_DELAY_10MS << SYV682X_OC_DELAY_SHIFT)
-		| (SYV682X_DSG_RON_200_OHM << SYV682X_DSG_RON_SHIFT)
-		| (SYV682X_DSG_TIME_50MS << SYV682X_DSG_TIME_SHIFT);
+	regval = (SYV682X_OC_DELAY_10MS << SYV682X_OC_DELAY_SHIFT) |
+		 (SYV682X_DSG_RON_200_OHM << SYV682X_DSG_RON_SHIFT) |
+		 (SYV682X_DSG_TIME_50MS << SYV682X_DSG_TIME_SHIFT);
 
 	if (IS_ENABLED(CONFIG_USBC_PPC_SYV682X_SMART_DISCHARGE))
 		regval |= SYV682X_CONTROL_2_SDSG;
diff --git a/driver/ppc/syv682x.h b/driver/ppc/syv682x.h
index d9416f47f1..f4fa616725 100644
--- a/driver/ppc/syv682x.h
+++ b/driver/ppc/syv682x.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,91 +12,91 @@
 #include "driver/ppc/syv682x_public.h"
 
 /* Source OC deglitch implemented in HW for SYV682B */
-#define SYV682X_HW_OC_DEGLITCH_MS	10
+#define SYV682X_HW_OC_DEGLITCH_MS 10
 
 /* SYV682x register addresses */
-#define SYV682X_STATUS_REG		0x00
-#define SYV682X_CONTROL_1_REG		0x01
-#define SYV682X_CONTROL_2_REG		0x02
-#define SYV682X_CONTROL_3_REG		0x03
-#define SYV682X_CONTROL_4_REG		0x04
+#define SYV682X_STATUS_REG 0x00
+#define SYV682X_CONTROL_1_REG 0x01
+#define SYV682X_CONTROL_2_REG 0x02
+#define SYV682X_CONTROL_3_REG 0x03
+#define SYV682X_CONTROL_4_REG 0x04
 
 /* Status Register */
-#define SYV682X_STATUS_OC_HV		BIT(7)
-#define SYV682X_STATUS_RVS		BIT(6)
-#define SYV682X_STATUS_OC_5V		BIT(5)
-#define SYV682X_STATUS_OVP		BIT(4)
-#define SYV682X_STATUS_FRS		BIT(3)
-#define SYV682X_STATUS_TSD		BIT(2)
-#define SYV682X_STATUS_VSAFE_5V		BIT(1)
-#define SYV682X_STATUS_VSAFE_0V		BIT(0)
-#define SYV682X_STATUS_INT_MASK		0xfc
+#define SYV682X_STATUS_OC_HV BIT(7)
+#define SYV682X_STATUS_RVS BIT(6)
+#define SYV682X_STATUS_OC_5V BIT(5)
+#define SYV682X_STATUS_OVP BIT(4)
+#define SYV682X_STATUS_FRS BIT(3)
+#define SYV682X_STATUS_TSD BIT(2)
+#define SYV682X_STATUS_VSAFE_5V BIT(1)
+#define SYV682X_STATUS_VSAFE_0V BIT(0)
+#define SYV682X_STATUS_INT_MASK 0xfc
 
 /* Control Register 1 */
-#define SYV682X_CONTROL_1_CH_SEL	BIT(1)
-#define SYV682X_CONTROL_1_HV_DR		BIT(2)
-#define SYV682X_CONTROL_1_PWR_ENB	BIT(7)
+#define SYV682X_CONTROL_1_CH_SEL BIT(1)
+#define SYV682X_CONTROL_1_HV_DR BIT(2)
+#define SYV682X_CONTROL_1_PWR_ENB BIT(7)
 
-#define SYV682X_5V_ILIM_MASK		0x18
-#define SYV682X_5V_ILIM_BIT_SHIFT	3
-#define SYV682X_5V_ILIM_1_25		0
-#define SYV682X_5V_ILIM_1_75		1
-#define SYV682X_5V_ILIM_2_25		2
-#define SYV682X_5V_ILIM_3_30		3
+#define SYV682X_5V_ILIM_MASK 0x18
+#define SYV682X_5V_ILIM_BIT_SHIFT 3
+#define SYV682X_5V_ILIM_1_25 0
+#define SYV682X_5V_ILIM_1_75 1
+#define SYV682X_5V_ILIM_2_25 2
+#define SYV682X_5V_ILIM_3_30 3
 
-#define SYV682X_HV_ILIM_MASK		0x60
-#define SYV682X_HV_ILIM_BIT_SHIFT	5
-#define SYV682X_HV_ILIM_1_25		0
-#define SYV682X_HV_ILIM_1_75		1
-#define SYV682X_HV_ILIM_3_30		2
-#define SYV682X_HV_ILIM_5_50		3
+#define SYV682X_HV_ILIM_MASK 0x60
+#define SYV682X_HV_ILIM_BIT_SHIFT 5
+#define SYV682X_HV_ILIM_1_25 0
+#define SYV682X_HV_ILIM_1_75 1
+#define SYV682X_HV_ILIM_3_30 2
+#define SYV682X_HV_ILIM_5_50 3
 
 /* Control Register 2 */
-#define SYV682X_OC_DELAY_MASK		GENMASK(7, 6)
-#define SYV682X_OC_DELAY_SHIFT		6
-#define SYV682X_OC_DELAY_1MS		0
-#define SYV682X_OC_DELAY_10MS		1
-#define SYV682X_OC_DELAY_50MS		2
-#define SYV682X_OC_DELAY_100MS		3
-#define SYV682X_DSG_TIME_MASK		GENMASK(5, 4)
-#define SYV682X_DSG_TIME_SHIFT		4
-#define SYV682X_DSG_TIME_50MS		0
-#define SYV682X_DSG_TIME_100MS		1
-#define SYV682X_DSG_TIME_200MS		2
-#define SYV682X_DSG_TIME_400MS		3
-#define SYV682X_DSG_RON_MASK		GENMASK(3, 2)
-#define SYV682X_DSG_RON_SHIFT		2
-#define SYV682X_DSG_RON_200_OHM		0
-#define SYV682X_DSG_RON_400_OHM		1
-#define SYV682X_DSG_RON_800_OHM		2
-#define SYV682X_DSG_RON_1600_OHM	3
-#define SYV682X_CONTROL_2_SDSG		BIT(1)
-#define SYV682X_CONTROL_2_FDSG		BIT(0)
+#define SYV682X_OC_DELAY_MASK GENMASK(7, 6)
+#define SYV682X_OC_DELAY_SHIFT 6
+#define SYV682X_OC_DELAY_1MS 0
+#define SYV682X_OC_DELAY_10MS 1
+#define SYV682X_OC_DELAY_50MS 2
+#define SYV682X_OC_DELAY_100MS 3
+#define SYV682X_DSG_TIME_MASK GENMASK(5, 4)
+#define SYV682X_DSG_TIME_SHIFT 4
+#define SYV682X_DSG_TIME_50MS 0
+#define SYV682X_DSG_TIME_100MS 1
+#define SYV682X_DSG_TIME_200MS 2
+#define SYV682X_DSG_TIME_400MS 3
+#define SYV682X_DSG_RON_MASK GENMASK(3, 2)
+#define SYV682X_DSG_RON_SHIFT 2
+#define SYV682X_DSG_RON_200_OHM 0
+#define SYV682X_DSG_RON_400_OHM 1
+#define SYV682X_DSG_RON_800_OHM 2
+#define SYV682X_DSG_RON_1600_OHM 3
+#define SYV682X_CONTROL_2_SDSG BIT(1)
+#define SYV682X_CONTROL_2_FDSG BIT(0)
 
 /* Control Register 3 */
-#define SYV682X_BUSY			BIT(7)
-#define SYV682X_RVS_MASK		BIT(3)
-#define SYV682X_RST_REG			BIT(0)
-#define SYV682X_OVP_MASK		0x70
-#define SYV682X_OVP_BIT_SHIFT		4
-#define SYV682X_OVP_06_0		0
-#define SYV682X_OVP_08_0		1
-#define SYV682X_OVP_11_1		2
-#define SYV682X_OVP_12_1		3
-#define SYV682X_OVP_14_2		4
-#define SYV682X_OVP_17_9		5
-#define SYV682X_OVP_21_6		6
-#define SYV682X_OVP_23_7		7
+#define SYV682X_BUSY BIT(7)
+#define SYV682X_RVS_MASK BIT(3)
+#define SYV682X_RST_REG BIT(0)
+#define SYV682X_OVP_MASK 0x70
+#define SYV682X_OVP_BIT_SHIFT 4
+#define SYV682X_OVP_06_0 0
+#define SYV682X_OVP_08_0 1
+#define SYV682X_OVP_11_1 2
+#define SYV682X_OVP_12_1 3
+#define SYV682X_OVP_14_2 4
+#define SYV682X_OVP_17_9 5
+#define SYV682X_OVP_21_6 6
+#define SYV682X_OVP_23_7 7
 
 /* Control Register 4 */
-#define SYV682X_CONTROL_4_CC1_BPS	BIT(7)
-#define SYV682X_CONTROL_4_CC2_BPS	BIT(6)
-#define SYV682X_CONTROL_4_VCONN1	BIT(5)
-#define SYV682X_CONTROL_4_VCONN2	BIT(4)
-#define SYV682X_CONTROL_4_VBAT_OVP	BIT(3)
-#define SYV682X_CONTROL_4_VCONN_OCP	BIT(2)
-#define SYV682X_CONTROL_4_CC_FRS	BIT(1)
-#define SYV682X_CONTROL_4_INT_MASK	0x0c
+#define SYV682X_CONTROL_4_CC1_BPS BIT(7)
+#define SYV682X_CONTROL_4_CC2_BPS BIT(6)
+#define SYV682X_CONTROL_4_VCONN1 BIT(5)
+#define SYV682X_CONTROL_4_VCONN2 BIT(4)
+#define SYV682X_CONTROL_4_VBAT_OVP BIT(3)
+#define SYV682X_CONTROL_4_VCONN_OCP BIT(2)
+#define SYV682X_CONTROL_4_CC_FRS BIT(1)
+#define SYV682X_CONTROL_4_INT_MASK 0x0c
 
 /*
  * syv682x_board_is_syv682c
diff --git a/driver/regulator_ir357x.c b/driver/regulator_ir357x.c
index 4721146367..24e4e26bbe 100644
--- a/driver/regulator_ir357x.c
+++ b/driver/regulator_ir357x.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -14,7 +14,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
-#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ##args)
 
 /* I2C address */
 #define IR357x_I2C_ADDR_FLAGS 0x08
@@ -25,73 +25,72 @@ struct ir_setting {
 };
 
 static struct ir_setting ir3570_settings[] = {
-	{0x10, 0x22}, {0x11, 0x22}, {0x12, 0x88}, {0x13, 0x10},
-	{0x14, 0x0d}, {0x15, 0x21}, {0x16, 0x21}, {0x17, 0x00},
-	{0x18, 0x00}, {0x19, 0x00}, {0x1a, 0x00}, {0x1b, 0x00},
-	{0x1c, 0x00}, {0x1d, 0x00}, {0x1e, 0x00}, {0x1f, 0x00},
-	{0x20, 0x00}, {0x21, 0x00}, {0x22, 0x60}, {0x23, 0x60},
-	{0x24, 0x74}, {0x25, 0x4e}, {0x26, 0xff}, {0x27, 0x80},
-	{0x28, 0x00}, {0x29, 0x20}, {0x2a, 0x15}, {0x2b, 0x26},
-	{0x2c, 0xb6}, {0x2d, 0x21}, {0x2e, 0x11}, {0x2f, 0x20},
-	{0x30, 0xab}, {0x31, 0x14}, {0x32, 0x90}, {0x33, 0x4d},
-	{0x34, 0x75}, {0x35, 0x64}, {0x36, 0x64}, {0x37, 0x09},
-	{0x38, 0xc4}, {0x39, 0x20}, {0x3a, 0x80}, {0x3b, 0x00},
-	{0x3c, 0x00}, {0x3d, 0xaa}, {0x3e, 0x00}, {0x3f, 0x05},
-	{0x40, 0x50}, {0x41, 0x40}, {0x42, 0x00}, {0x43, 0x00},
-	{0x44, 0x00}, {0x45, 0x00}, {0x46, 0x00}, {0x47, 0x00},
-	{0x48, 0x1c}, {0x49, 0x0c}, {0x4a, 0x0f}, {0x4b, 0x40},
-	{0x4c, 0x80}, {0x4d, 0x40}, {0x4e, 0x80},
-	{0x51, 0x00}, {0x52, 0x45}, {0x53, 0x59},
-	{0x54, 0x23}, {0x55, 0xae}, {0x56, 0x68}, {0x57, 0x24},
-	{0x58, 0x62}, {0x59, 0x42}, {0x5a, 0x34}, {0x5b, 0x00},
-	{0x5c, 0x30}, {0x5d, 0x05}, {0x5e, 0x02}, {0x5f, 0x35},
-	{0x60, 0x30}, {0x61, 0x00}, {0x62, 0xd8}, {0x63, 0x00},
-	{0x64, 0x52}, {0x65, 0x28}, {0x66, 0x14}, {0x67, 0x87},
-	{0x68, 0x80}, {0x69, 0x00}, {0x6a, 0x00}, {0x6b, 0x00},
-	{0x6c, 0x00}, {0x6d, 0xff}, {0x6e, 0x06}, {0x6f, 0xff},
-	{0x70, 0xff}, {0x71, 0x20}, {0x72, 0x00}, {0x73, 0x01},
-	{0x74, 0x00}, {0x75, 0x00}, {0x76, 0x00}, {0x77, 0x00},
-	{0x78, 0x00}, {0x79, 0x00}, {0x7a, 0x00}, {0x7b, 0x00},
-	{0x7c, 0x15}, {0x7d, 0x15}, {0x7e, 0x00}, {0x7f, 0x00},
-	{0x80, 0x00}, {0x81, 0x00}, {0x82, 0x00}, {0x83, 0x00},
-	{0x84, 0x00}, {0x85, 0x00}, {0x86, 0x00}, {0x87, 0x00},
-	{0x88, 0x88}, {0x89, 0x88}, {0x8a, 0x01}, {0x8b, 0x42},
-	{0x8d, 0x00}, {0x8e, 0x00}, {0x8f, 0x1f},
-	{0, 0}
+	{ 0x10, 0x22 }, { 0x11, 0x22 }, { 0x12, 0x88 }, { 0x13, 0x10 },
+	{ 0x14, 0x0d }, { 0x15, 0x21 }, { 0x16, 0x21 }, { 0x17, 0x00 },
+	{ 0x18, 0x00 }, { 0x19, 0x00 }, { 0x1a, 0x00 }, { 0x1b, 0x00 },
+	{ 0x1c, 0x00 }, { 0x1d, 0x00 }, { 0x1e, 0x00 }, { 0x1f, 0x00 },
+	{ 0x20, 0x00 }, { 0x21, 0x00 }, { 0x22, 0x60 }, { 0x23, 0x60 },
+	{ 0x24, 0x74 }, { 0x25, 0x4e }, { 0x26, 0xff }, { 0x27, 0x80 },
+	{ 0x28, 0x00 }, { 0x29, 0x20 }, { 0x2a, 0x15 }, { 0x2b, 0x26 },
+	{ 0x2c, 0xb6 }, { 0x2d, 0x21 }, { 0x2e, 0x11 }, { 0x2f, 0x20 },
+	{ 0x30, 0xab }, { 0x31, 0x14 }, { 0x32, 0x90 }, { 0x33, 0x4d },
+	{ 0x34, 0x75 }, { 0x35, 0x64 }, { 0x36, 0x64 }, { 0x37, 0x09 },
+	{ 0x38, 0xc4 }, { 0x39, 0x20 }, { 0x3a, 0x80 }, { 0x3b, 0x00 },
+	{ 0x3c, 0x00 }, { 0x3d, 0xaa }, { 0x3e, 0x00 }, { 0x3f, 0x05 },
+	{ 0x40, 0x50 }, { 0x41, 0x40 }, { 0x42, 0x00 }, { 0x43, 0x00 },
+	{ 0x44, 0x00 }, { 0x45, 0x00 }, { 0x46, 0x00 }, { 0x47, 0x00 },
+	{ 0x48, 0x1c }, { 0x49, 0x0c }, { 0x4a, 0x0f }, { 0x4b, 0x40 },
+	{ 0x4c, 0x80 }, { 0x4d, 0x40 }, { 0x4e, 0x80 }, { 0x51, 0x00 },
+	{ 0x52, 0x45 }, { 0x53, 0x59 }, { 0x54, 0x23 }, { 0x55, 0xae },
+	{ 0x56, 0x68 }, { 0x57, 0x24 }, { 0x58, 0x62 }, { 0x59, 0x42 },
+	{ 0x5a, 0x34 }, { 0x5b, 0x00 }, { 0x5c, 0x30 }, { 0x5d, 0x05 },
+	{ 0x5e, 0x02 }, { 0x5f, 0x35 }, { 0x60, 0x30 }, { 0x61, 0x00 },
+	{ 0x62, 0xd8 }, { 0x63, 0x00 }, { 0x64, 0x52 }, { 0x65, 0x28 },
+	{ 0x66, 0x14 }, { 0x67, 0x87 }, { 0x68, 0x80 }, { 0x69, 0x00 },
+	{ 0x6a, 0x00 }, { 0x6b, 0x00 }, { 0x6c, 0x00 }, { 0x6d, 0xff },
+	{ 0x6e, 0x06 }, { 0x6f, 0xff }, { 0x70, 0xff }, { 0x71, 0x20 },
+	{ 0x72, 0x00 }, { 0x73, 0x01 }, { 0x74, 0x00 }, { 0x75, 0x00 },
+	{ 0x76, 0x00 }, { 0x77, 0x00 }, { 0x78, 0x00 }, { 0x79, 0x00 },
+	{ 0x7a, 0x00 }, { 0x7b, 0x00 }, { 0x7c, 0x15 }, { 0x7d, 0x15 },
+	{ 0x7e, 0x00 }, { 0x7f, 0x00 }, { 0x80, 0x00 }, { 0x81, 0x00 },
+	{ 0x82, 0x00 }, { 0x83, 0x00 }, { 0x84, 0x00 }, { 0x85, 0x00 },
+	{ 0x86, 0x00 }, { 0x87, 0x00 }, { 0x88, 0x88 }, { 0x89, 0x88 },
+	{ 0x8a, 0x01 }, { 0x8b, 0x42 }, { 0x8d, 0x00 }, { 0x8e, 0x00 },
+	{ 0x8f, 0x1f }, { 0, 0 }
 };
 
 static struct ir_setting ir3571_settings[] = {
-	{0x18, 0x22}, {0x19, 0x22}, {0x1a, 0x08}, {0x1b, 0x10},
-	{0x1c, 0x06}, {0x1d, 0x21}, {0x1e, 0x21}, {0x1f, 0x83},
-	{0x20, 0x83}, {0x21, 0x00}, {0x22, 0x00}, {0x23, 0x00},
-	{0x24, 0x00}, {0x25, 0x00}, {0x26, 0x00}, {0x27, 0x34},
-	{0x28, 0x34}, {0x29, 0x74}, {0x2a, 0x4e}, {0x2b, 0xff},
-	{0x2c, 0x00}, {0x2d, 0x1d}, {0x2e, 0x14}, {0x2f, 0x1f},
-	{0x30, 0x88}, {0x31, 0x9a}, {0x32, 0x1e}, {0x33, 0x19},
-	{0x34, 0xe9}, {0x35, 0x40}, {0x36, 0x90}, {0x37, 0x6d},
-	{0x38, 0x75}, {0x39, 0xa0}, {0x3a, 0x84}, {0x3b, 0x08},
-	{0x3c, 0xc5}, {0x3d, 0xa0}, {0x3e, 0x80}, {0x3f, 0xaa},
-	{0x40, 0x50}, {0x41, 0x4b}, {0x42, 0x02}, {0x43, 0x04},
-	{0x44, 0x00}, {0x45, 0x00}, {0x46, 0x00}, {0x47, 0x78},
-	{0x48, 0x56}, {0x49, 0x18}, {0x4a, 0x88}, {0x4b, 0x00},
-	{0x4c, 0x80}, {0x4d, 0x60}, {0x4e, 0x60}, {0x4f, 0xff},
-	{0x50, 0xff}, {0x51, 0x00}, {0x52, 0x9b}, {0x53, 0xaa},
-	{0x54, 0xd8}, {0x55, 0x56}, {0x56, 0x31}, {0x57, 0x1a},
-	{0x58, 0x12}, {0x59, 0x63}, {0x5a, 0x00}, {0x5b, 0x09},
-	{0x5c, 0x02}, {0x5d, 0x00}, {0x5e, 0xea}, {0x5f, 0x00},
-	{0x60, 0xb0}, {0x61, 0x1e}, {0x62, 0x00}, {0x63, 0x56},
-	{0x64, 0x00}, {0x65, 0x00}, {0x66, 0x00}, {0x67, 0x00},
-	{0x68, 0x28}, {0x69, 0x00}, {0x6a, 0x00}, {0x6b, 0x00},
-	{0x6c, 0x00}, {0x6d, 0x00}, {0x6e, 0x00}, {0x6f, 0x00},
-	{0x70, 0x80}, {0x71, 0x00}, {0x72, 0x00}, {0x73, 0x00},
-	{0x74, 0x00}, {0x75, 0xbf}, {0x76, 0x06}, {0x77, 0xff},
-	{0x78, 0xff}, {0x79, 0x04}, {0x7a, 0x00}, {0x7b, 0x1d},
-	{0x7c, 0xa0}, {0x7d, 0x10}, {0x7e, 0x00}, {0x7f, 0x8a},
-	{0x80, 0x1b}, {0x81, 0x11}, {0x82, 0x00}, {0x83, 0x00},
-	{0x84, 0x00}, {0x85, 0x00}, {0x86, 0x00}, {0x87, 0x00},
-	{0x88, 0x00}, {0x89, 0x00}, {0x8a, 0x00}, {0x8b, 0x00},
-	{0x8c, 0x00}, {0x8d, 0x00}, {0x8e, 0x00}, {0x8f, 0x00},
-	{0, 0}
+	{ 0x18, 0x22 }, { 0x19, 0x22 }, { 0x1a, 0x08 }, { 0x1b, 0x10 },
+	{ 0x1c, 0x06 }, { 0x1d, 0x21 }, { 0x1e, 0x21 }, { 0x1f, 0x83 },
+	{ 0x20, 0x83 }, { 0x21, 0x00 }, { 0x22, 0x00 }, { 0x23, 0x00 },
+	{ 0x24, 0x00 }, { 0x25, 0x00 }, { 0x26, 0x00 }, { 0x27, 0x34 },
+	{ 0x28, 0x34 }, { 0x29, 0x74 }, { 0x2a, 0x4e }, { 0x2b, 0xff },
+	{ 0x2c, 0x00 }, { 0x2d, 0x1d }, { 0x2e, 0x14 }, { 0x2f, 0x1f },
+	{ 0x30, 0x88 }, { 0x31, 0x9a }, { 0x32, 0x1e }, { 0x33, 0x19 },
+	{ 0x34, 0xe9 }, { 0x35, 0x40 }, { 0x36, 0x90 }, { 0x37, 0x6d },
+	{ 0x38, 0x75 }, { 0x39, 0xa0 }, { 0x3a, 0x84 }, { 0x3b, 0x08 },
+	{ 0x3c, 0xc5 }, { 0x3d, 0xa0 }, { 0x3e, 0x80 }, { 0x3f, 0xaa },
+	{ 0x40, 0x50 }, { 0x41, 0x4b }, { 0x42, 0x02 }, { 0x43, 0x04 },
+	{ 0x44, 0x00 }, { 0x45, 0x00 }, { 0x46, 0x00 }, { 0x47, 0x78 },
+	{ 0x48, 0x56 }, { 0x49, 0x18 }, { 0x4a, 0x88 }, { 0x4b, 0x00 },
+	{ 0x4c, 0x80 }, { 0x4d, 0x60 }, { 0x4e, 0x60 }, { 0x4f, 0xff },
+	{ 0x50, 0xff }, { 0x51, 0x00 }, { 0x52, 0x9b }, { 0x53, 0xaa },
+	{ 0x54, 0xd8 }, { 0x55, 0x56 }, { 0x56, 0x31 }, { 0x57, 0x1a },
+	{ 0x58, 0x12 }, { 0x59, 0x63 }, { 0x5a, 0x00 }, { 0x5b, 0x09 },
+	{ 0x5c, 0x02 }, { 0x5d, 0x00 }, { 0x5e, 0xea }, { 0x5f, 0x00 },
+	{ 0x60, 0xb0 }, { 0x61, 0x1e }, { 0x62, 0x00 }, { 0x63, 0x56 },
+	{ 0x64, 0x00 }, { 0x65, 0x00 }, { 0x66, 0x00 }, { 0x67, 0x00 },
+	{ 0x68, 0x28 }, { 0x69, 0x00 }, { 0x6a, 0x00 }, { 0x6b, 0x00 },
+	{ 0x6c, 0x00 }, { 0x6d, 0x00 }, { 0x6e, 0x00 }, { 0x6f, 0x00 },
+	{ 0x70, 0x80 }, { 0x71, 0x00 }, { 0x72, 0x00 }, { 0x73, 0x00 },
+	{ 0x74, 0x00 }, { 0x75, 0xbf }, { 0x76, 0x06 }, { 0x77, 0xff },
+	{ 0x78, 0xff }, { 0x79, 0x04 }, { 0x7a, 0x00 }, { 0x7b, 0x1d },
+	{ 0x7c, 0xa0 }, { 0x7d, 0x10 }, { 0x7e, 0x00 }, { 0x7f, 0x8a },
+	{ 0x80, 0x1b }, { 0x81, 0x11 }, { 0x82, 0x00 }, { 0x83, 0x00 },
+	{ 0x84, 0x00 }, { 0x85, 0x00 }, { 0x86, 0x00 }, { 0x87, 0x00 },
+	{ 0x88, 0x00 }, { 0x89, 0x00 }, { 0x8a, 0x00 }, { 0x8b, 0x00 },
+	{ 0x8c, 0x00 }, { 0x8d, 0x00 }, { 0x8e, 0x00 }, { 0x8f, 0x00 },
+	{ 0, 0 }
 };
 
 static uint8_t ir357x_read(uint8_t reg)
@@ -186,8 +185,8 @@ static int ir357x_check(void)
 	for (; settings->reg; settings++) {
 		val = ir357x_read(settings->reg);
 		if (val != settings->value) {
-			ccprintf("DIFF reg 0x%02x %02x->%02x\n",
-				 settings->reg, settings->value, val);
+			ccprintf("DIFF reg 0x%02x %02x->%02x\n", settings->reg,
+				 settings->value, val);
 			cflush();
 			diff++;
 		}
@@ -196,7 +195,7 @@ static int ir357x_check(void)
 }
 
 #ifdef CONFIG_CMD_REGULATOR
-static int command_ir357x(int argc, char **argv)
+static int command_ir357x(int argc, const char **argv)
 {
 	int reg, val;
 	char *rem;
@@ -234,8 +233,7 @@ static int command_ir357x(int argc, char **argv)
 
 	return EC_ERROR_INVAL;
 }
-DECLARE_CONSOLE_COMMAND(ir357x, command_ir357x,
-			"[check|write]",
+DECLARE_CONSOLE_COMMAND(ir357x, command_ir357x, "[check|write]",
 			"IR357x core regulator control");
 #endif
 
diff --git a/driver/retimer/anx7483.c b/driver/retimer/anx7483.c
index 6804fd3de8..2194483e44 100644
--- a/driver/retimer/anx7483.c
+++ b/driver/retimer/anx7483.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,11 +19,11 @@
  * Programming guide specifies it may be as much as 30ms after chip power on
  * before it's ready for i2c
  */
-#define ANX7483_I2C_WAKE_TIMEOUT_MS	30
+#define ANX7483_I2C_WAKE_TIMEOUT_MS 30
 #define ANX7483_I2C_WAKE_RETRY_DELAY_US 5000
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* Tuning defaults */
 struct anx7483_tuning_set {
@@ -32,163 +32,162 @@ struct anx7483_tuning_set {
 };
 
 static struct anx7483_tuning_set anx7483_usb_enabled[] = {
-	{ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF},
-	{ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF},
-	{ANX7483_DRX1_PORT_CFG2_REG, ANX7483_CFG2_DEF},
-	{ANX7483_DRX2_PORT_CFG2_REG, ANX7483_CFG2_DEF},
-
-	{ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF},
-	{ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF},
-	{ANX7483_DRX1_PORT_CFG0_REG, ANX7483_CFG0_DEF},
-	{ANX7483_DRX2_PORT_CFG0_REG, ANX7483_CFG0_DEF},
-
-	{ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE},
-	{ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE},
-	{ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE},
-	{ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE},
-
-	{ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE},
-	{ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE},
-	{ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE},
-	{ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE},
-
-	{ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF},
-	{ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF},
-	{ANX7483_DRX1_PORT_CFG1_REG, ANX7483_CFG1_DEF},
-	{ANX7483_DRX2_PORT_CFG1_REG, ANX7483_CFG1_DEF},
-
-	{ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT},
-	{ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT},
-	{ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT},
-	{ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT},
-
-	{ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN},
-	{ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN},
-	{ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN},
-	{ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN},
+	{ ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+	{ ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+	{ ANX7483_DRX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+	{ ANX7483_DRX2_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+
+	{ ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+	{ ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+	{ ANX7483_DRX1_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+	{ ANX7483_DRX2_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+
+	{ ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE },
+	{ ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE },
+	{ ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE },
+	{ ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE },
+
+	{ ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+	{ ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+	{ ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+	{ ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+
+	{ ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+	{ ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+	{ ANX7483_DRX1_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+	{ ANX7483_DRX2_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+
+	{ ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT },
+	{ ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT },
+	{ ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT },
+	{ ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT },
+
+	{ ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+	{ ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+	{ ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+	{ ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
 };
 
 static struct anx7483_tuning_set anx7483_dp_enabled[] = {
-	{ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF},
-
-	{ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF},
-	{ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF},
-	{ANX7483_UTX1_PORT_CFG2_REG, ANX7483_CFG2_DEF},
-	{ANX7483_UTX2_PORT_CFG2_REG, ANX7483_CFG2_DEF},
-
-	{ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF},
-	{ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF},
-	{ANX7483_UTX1_PORT_CFG0_REG, ANX7483_CFG0_DEF},
-	{ANX7483_UTX2_PORT_CFG0_REG, ANX7483_CFG0_DEF},
-
-	{ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE},
-	{ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE},
-	{ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE},
-	{ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE},
-	{ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE},
-	{ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE},
-	{ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE},
-	{ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE},
-
-	{ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF},
-	{ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF},
-	{ANX7483_UTX1_PORT_CFG1_REG, ANX7483_CFG1_DEF},
-	{ANX7483_UTX2_PORT_CFG1_REG, ANX7483_CFG1_DEF},
-
-	{ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN},
-	{ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN},
-	{ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN},
-	{ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN},
-	{ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN},
-	{ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN},
-	{ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN},
-	{ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN},
+	{ ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF },
+
+	{ ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+	{ ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+	{ ANX7483_UTX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+	{ ANX7483_UTX2_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+
+	{ ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+	{ ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+	{ ANX7483_UTX1_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+	{ ANX7483_UTX2_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+
+	{ ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+	{ ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+	{ ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+	{ ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+	{ ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+	{ ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+	{ ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+	{ ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+
+	{ ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+	{ ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+	{ ANX7483_UTX1_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+	{ ANX7483_UTX2_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+
+	{ ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+	{ ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+	{ ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+	{ ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+	{ ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+	{ ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+	{ ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+	{ ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
 };
 
 static struct anx7483_tuning_set anx7483_dock_noflip[] = {
-	{ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF},
-
-	{ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF},
-	{ANX7483_DRX1_PORT_CFG2_REG, ANX7483_CFG2_DEF},
-	{ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF},
-	{ANX7483_UTX2_PORT_CFG2_REG, ANX7483_CFG2_DEF},
-
-	{ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF},
-	{ANX7483_DRX1_PORT_CFG0_REG, ANX7483_CFG0_DEF},
-	{ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF},
-	{ANX7483_UTX2_PORT_CFG0_REG, ANX7483_CFG0_DEF},
-
-	{ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE},
-	{ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE},
-
-	{ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE},
-	{ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE},
-	{ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE},
-	{ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE},
-	{ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE},
-	{ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE},
-
-	{ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF},
-	{ANX7483_DRX1_PORT_CFG1_REG, ANX7483_CFG1_DEF},
-	{ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF},
-	{ANX7483_UTX2_PORT_CFG1_REG, ANX7483_CFG1_DEF},
-
-	{ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN},
-	{ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN},
-	{ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN},
-	{ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN},
-	{ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN},
-	{ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN},
-	{ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN},
-	{ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN},
+	{ ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF },
+
+	{ ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+	{ ANX7483_DRX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+	{ ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+	{ ANX7483_UTX2_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+
+	{ ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+	{ ANX7483_DRX1_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+	{ ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+	{ ANX7483_UTX2_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+
+	{ ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE },
+	{ ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE },
+
+	{ ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+	{ ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+	{ ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+	{ ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+	{ ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+	{ ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+
+	{ ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+	{ ANX7483_DRX1_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+	{ ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+	{ ANX7483_UTX2_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+
+	{ ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+	{ ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+	{ ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+	{ ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+	{ ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+	{ ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+	{ ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+	{ ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
 };
 
 static struct anx7483_tuning_set anx7483_dock_flip[] = {
-	{ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF},
-
-	{ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF},
-	{ANX7483_DRX2_PORT_CFG2_REG, ANX7483_CFG2_DEF},
-	{ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF},
-	{ANX7483_UTX1_PORT_CFG2_REG, ANX7483_CFG2_DEF},
-
-	{ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF},
-	{ANX7483_DRX2_PORT_CFG0_REG, ANX7483_CFG0_DEF},
-	{ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF},
-	{ANX7483_UTX1_PORT_CFG0_REG, ANX7483_CFG0_DEF},
-
-	{ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE},
-	{ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE},
-
-	{ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE},
-	{ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE},
-	{ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE},
-	{ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE},
-	{ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE},
-	{ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE},
-
-	{ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF},
-	{ANX7483_UTX1_PORT_CFG1_REG, ANX7483_CFG1_DEF},
-	{ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF},
-	{ANX7483_DRX2_PORT_CFG1_REG, ANX7483_CFG1_DEF},
-
-	{ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN},
-	{ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN},
-	{ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN},
-	{ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN},
-	{ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN},
-	{ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN},
-	{ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN},
-	{ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN},
+	{ ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF },
+
+	{ ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+	{ ANX7483_DRX2_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+	{ ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+	{ ANX7483_UTX1_PORT_CFG2_REG, ANX7483_CFG2_DEF },
+
+	{ ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+	{ ANX7483_DRX2_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+	{ ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+	{ ANX7483_UTX1_PORT_CFG0_REG, ANX7483_CFG0_DEF },
+
+	{ ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE },
+	{ ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE },
+
+	{ ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+	{ ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+	{ ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+	{ ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+	{ ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+	{ ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE },
+
+	{ ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+	{ ANX7483_UTX1_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+	{ ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+	{ ANX7483_DRX2_PORT_CFG1_REG, ANX7483_CFG1_DEF },
+
+	{ ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+	{ ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+	{ ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+	{ ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+	{ ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+	{ ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
+	{ ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN },
+	{ ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN },
 };
 
-static inline int anx7483_read(const struct usb_mux *me,
-			       uint8_t reg, int *val)
+static inline int anx7483_read(const struct usb_mux *me, uint8_t reg, int *val)
 {
 	return i2c_read8(me->i2c_port, me->i2c_addr_flags, reg, val);
 }
 
-static inline int anx7483_write(const struct usb_mux *me,
-				uint8_t reg, uint8_t val)
+static inline int anx7483_write(const struct usb_mux *me, uint8_t reg,
+				uint8_t val)
 {
 	return i2c_write8(me->i2c_port, me->i2c_addr_flags, reg, val);
 }
@@ -231,6 +230,10 @@ static int anx7483_set(const struct usb_mux *me, mux_state_t mux_state,
 	/* This driver does not use host command ACKs */
 	*ack_required = false;
 
+	/* This driver treats safe mode as none */
+	if (mux_state == USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
+
 	/*
 	 * Mux is not powered in Z1
 	 */
@@ -287,8 +290,7 @@ static enum ec_error_list anx7483_apply_tuning(const struct usb_mux *me,
 	return EC_SUCCESS;
 }
 
-enum ec_error_list anx7483_set_default_tuning(const struct usb_mux *me,
-					      mux_state_t mux_state)
+int anx7483_set_default_tuning(const struct usb_mux *me, mux_state_t mux_state)
 {
 	bool flipped = mux_state & USB_PD_MUX_POLARITY_INVERTED;
 
@@ -324,7 +326,7 @@ enum ec_error_list anx7483_set_eq(const struct usb_mux *me,
 
 	if (pin == ANX7483_PIN_UTX1)
 		reg = ANX7483_UTX1_PORT_CFG0_REG;
-	else if (pin ==  ANX7483_PIN_UTX2)
+	else if (pin == ANX7483_PIN_UTX2)
 		reg = ANX7483_UTX2_PORT_CFG0_REG;
 	else if (pin == ANX7483_PIN_URX1)
 		reg = ANX7483_URX1_PORT_CFG0_REG;
diff --git a/driver/retimer/anx7483.h b/driver/retimer/anx7483.h
index d5f6723818..d489b3d8e6 100644
--- a/driver/retimer/anx7483.h
+++ b/driver/retimer/anx7483.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -20,12 +20,12 @@
  * 1   DP_EN (0: disable DP mode; 1: Enable DP mode.)
  * 0   USB_EN (1: disable USB mode; 1: enable USB mode.)
  */
-#define ANX7483_ANALOG_STATUS_CTRL_REG	0x07
-#define ANX7483_CTRL_REG_BYPASS_EN	BIT(5)
-#define ANX7483_CTRL_REG_EN		BIT(4)
-#define ANX7483_CTRL_FLIP_EN		BIT(2)
-#define ANX7483_CTRL_DP_EN		BIT(1)
-#define ANX7483_CTRL_USB_EN		BIT(0)
+#define ANX7483_ANALOG_STATUS_CTRL_REG 0x07
+#define ANX7483_CTRL_REG_BYPASS_EN BIT(5)
+#define ANX7483_CTRL_REG_EN BIT(4)
+#define ANX7483_CTRL_FLIP_EN BIT(2)
+#define ANX7483_CTRL_DP_EN BIT(1)
+#define ANX7483_CTRL_USB_EN BIT(0)
 
 /*
  * Register_EQ/FG/SW_EN register
@@ -34,8 +34,8 @@
  * 7:1 Reserved
  * 0   Reg_EQ/FG/SW_EN (0: from pin control; 1: from register control)
  */
-#define ANX7483_ENABLE_EQ_FLAT_SWING_REG	0x15
-#define ANX7483_ENABLE_EQ_FLAT_SWING_EN		BIT(0)
+#define ANX7483_ENABLE_EQ_FLAT_SWING_REG 0x15
+#define ANX7483_ENABLE_EQ_FLAT_SWING_EN BIT(0)
 
 /*
  * EQ Settings Registers
@@ -43,20 +43,20 @@
  * 7:4 Equilation settings when pin is input
  * 3:0 Fine tuning EQ step
  */
-#define ANX7483_UTX1_PORT_CFG0_REG	0x52
-#define ANX7483_UTX2_PORT_CFG0_REG	0x16
-#define ANX7483_URX1_PORT_CFG0_REG	0x3E
-#define ANX7483_URX2_PORT_CFG0_REG	0x2A
-#define ANX7483_DRX1_PORT_CFG0_REG	0x5C
-#define ANX7483_DRX2_PORT_CFG0_REG	0x20
+#define ANX7483_UTX1_PORT_CFG0_REG 0x52
+#define ANX7483_UTX2_PORT_CFG0_REG 0x16
+#define ANX7483_URX1_PORT_CFG0_REG 0x3E
+#define ANX7483_URX2_PORT_CFG0_REG 0x2A
+#define ANX7483_DRX1_PORT_CFG0_REG 0x5C
+#define ANX7483_DRX2_PORT_CFG0_REG 0x20
 
-#define ANX7483_CFG0_EQ_SHIFT		4
-#define ANX7483_CFG0_EQ_MASK		GENMASK(7, 4)
+#define ANX7483_CFG0_EQ_SHIFT 4
+#define ANX7483_CFG0_EQ_MASK GENMASK(7, 4)
 
 /*
  * Default CFG0 value to apply: 9.2 dB with optimized tuning step
  */
-#define ANX7483_CFG0_DEF		0x53
+#define ANX7483_CFG0_DEF 0x53
 
 /*
  * Flat Gain Settings Registers
@@ -65,17 +65,17 @@
  * 5:4 Flat gain settings when pin is input
  * 3:0 Fine tuning EQ
  */
-#define ANX7483_UTX1_PORT_CFG2_REG	0x54
-#define ANX7483_UTX2_PORT_CFG2_REG	0x18
-#define ANX7483_URX1_PORT_CFG2_REG	0x40
-#define ANX7483_URX2_PORT_CFG2_REG	0x2C
-#define ANX7483_DRX1_PORT_CFG2_REG	0x5E
-#define ANX7483_DRX2_PORT_CFG2_REG	0x22
+#define ANX7483_UTX1_PORT_CFG2_REG 0x54
+#define ANX7483_UTX2_PORT_CFG2_REG 0x18
+#define ANX7483_URX1_PORT_CFG2_REG 0x40
+#define ANX7483_URX2_PORT_CFG2_REG 0x2C
+#define ANX7483_DRX1_PORT_CFG2_REG 0x5E
+#define ANX7483_DRX2_PORT_CFG2_REG 0x22
 
 /*
  * Default CFG2 value to apply: 0.3 dB with optimized fine tuning
  */
-#define ANX7483_CFG2_DEF		0xEE
+#define ANX7483_CFG2_DEF 0xEE
 
 /*
  * Swing and 60K Input Termination Registers
@@ -85,20 +85,20 @@
  * 3:2 Vendor internal use
  * 1:0 Swing setting when configured as input port
  */
-#define ANX7483_UTX1_PORT_CFG4_REG	0x56
-#define ANX7483_UTX2_PORT_CFG4_REG	0x1A
-#define ANX7483_URX1_PORT_CFG4_REG	0x42
-#define ANX7483_URX2_PORT_CFG4_REG	0x2E
-#define ANX7483_DRX1_PORT_CFG4_REG	0x60
-#define ANX7483_DRX2_PORT_CFG4_REG	0x24
-#define ANX7483_DTX1_PORT_CFG4_REG	0x4C
-#define ANX7483_DTX2_PORT_CFG4_REG	0x38
+#define ANX7483_UTX1_PORT_CFG4_REG 0x56
+#define ANX7483_UTX2_PORT_CFG4_REG 0x1A
+#define ANX7483_URX1_PORT_CFG4_REG 0x42
+#define ANX7483_URX2_PORT_CFG4_REG 0x2E
+#define ANX7483_DRX1_PORT_CFG4_REG 0x60
+#define ANX7483_DRX2_PORT_CFG4_REG 0x24
+#define ANX7483_DTX1_PORT_CFG4_REG 0x4C
+#define ANX7483_DTX2_PORT_CFG4_REG 0x38
 
 /*
  * Default values: 1300 mV gain with 60k termination either enabled or disabled
  */
-#define ANX7483_CFG4_TERM_DISABLE	0x63
-#define ANX7483_CFG4_TERM_ENABLE	0x73
+#define ANX7483_CFG4_TERM_DISABLE 0x63
+#define ANX7483_CFG4_TERM_ENABLE 0x73
 
 /*
  * Termination Resistance Registers
@@ -108,21 +108,21 @@
  * 1   Enable termination res for UTX2 path. (0:disable 1: enable.)
  * 0   Tune Flat Gain.
  */
-#define ANX7483_UTX1_PORT_CFG3_REG	0x55
-#define ANX7483_UTX2_PORT_CFG3_REG	0x19
-#define ANX7483_URX1_PORT_CFG3_REG	0x41
-#define ANX7483_URX2_PORT_CFG3_REG	0x2D
-#define ANX7483_DTX1_PORT_CFG3_REG	0x4B
-#define ANX7483_DTX2_PORT_CFG3_REG	0x37
-#define ANX7483_DRX1_PORT_CFG3_REG	0x5F
-#define ANX7483_DRX2_PORT_CFG3_REG	0x23
+#define ANX7483_UTX1_PORT_CFG3_REG 0x55
+#define ANX7483_UTX2_PORT_CFG3_REG 0x19
+#define ANX7483_URX1_PORT_CFG3_REG 0x41
+#define ANX7483_URX2_PORT_CFG3_REG 0x2D
+#define ANX7483_DTX1_PORT_CFG3_REG 0x4B
+#define ANX7483_DTX2_PORT_CFG3_REG 0x37
+#define ANX7483_DRX1_PORT_CFG3_REG 0x5F
+#define ANX7483_DRX2_PORT_CFG3_REG 0x23
 
 /*
  * Default values: Either 100Ohm or 90Ohm, input or output
  */
-#define ANX7483_CFG3_100Ohm_IN		0x3A
-#define ANX7483_CFG3_90Ohm_IN		0x7A
-#define ANX7483_CFG3_90Ohm_OUT		0x7E
+#define ANX7483_CFG3_100Ohm_IN 0x3A
+#define ANX7483_CFG3_90Ohm_IN 0x7A
+#define ANX7483_CFG3_90Ohm_OUT 0x7E
 
 /*
  * AUX_Snooping_CTRL register
@@ -131,13 +131,13 @@
  * 2:1 AUX_VTH (00:60mVppd, 01:90mVppd, 10:120mVppd, 11:140mVppd)
  * 0   AUX_Snooping_EN (0: disable; 1: enable.)
  */
-#define ANX7483_AUX_SNOOPING_CTRL_REG	0x13
+#define ANX7483_AUX_SNOOPING_CTRL_REG 0x13
 
 /*
  * Default value: Enable snooping with 90mVppd
  * (register ignored outside DP mode and does not need to be cleared)
  */
-#define ANX7483_AUX_SNOOPING_DEF	0x13
+#define ANX7483_AUX_SNOOPING_DEF 0x13
 
 /*
  * Middle Frequency Compensation
@@ -146,17 +146,17 @@
  * 5:3 UTX1_EQ_MFR CTLE middle-freq resistance when input
  * 2:0 UTX1_EQ_MFC CTLE middle-freq Capacitance
  */
-#define ANX7483_UTX1_PORT_CFG1_REG	0x53
-#define ANX7483_UTX2_PORT_CFG1_REG	0x17
-#define ANX7483_URX1_PORT_CFG1_REG	0x3F
-#define ANX7483_URX2_PORT_CFG1_REG	0x2B
-#define ANX7483_DRX1_PORT_CFG1_REG	0x5D
-#define ANX7483_DRX2_PORT_CFG1_REG	0x21
+#define ANX7483_UTX1_PORT_CFG1_REG 0x53
+#define ANX7483_UTX2_PORT_CFG1_REG 0x17
+#define ANX7483_URX1_PORT_CFG1_REG 0x3F
+#define ANX7483_URX2_PORT_CFG1_REG 0x2B
+#define ANX7483_DRX1_PORT_CFG1_REG 0x5D
+#define ANX7483_DRX2_PORT_CFG1_REG 0x21
 
 /*
  * Default CFG1 setting: current bias max, Middle frequency resistance of 0x5,
  * Middle frequency capacitance of 0x6
  */
-#define ANX7483_CFG1_DEF		0xEE
+#define ANX7483_CFG1_DEF 0xEE
 
 #endif /* __CROS_EC_USB_RETIMER_ANX7483_H */
diff --git a/driver/retimer/anx7491.h b/driver/retimer/anx7491.h
index 045cf9f411..9bf9594ea7 100644
--- a/driver/retimer/anx7491.h
+++ b/driver/retimer/anx7491.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -9,9 +9,9 @@
 #define __CROS_EC_USB_RETIMER_ANX7491_H
 
 /* I2C interface addresses */
-#define ANX7491_I2C_ADDR0_FLAGS		0x10
-#define ANX7491_I2C_ADDR1_FLAGS		0x14
-#define ANX7491_I2C_ADDR2_FLAGS		0x16
-#define ANX7491_I2C_ADDR3_FLAGS		0x11
+#define ANX7491_I2C_ADDR0_FLAGS 0x10
+#define ANX7491_I2C_ADDR1_FLAGS 0x14
+#define ANX7491_I2C_ADDR2_FLAGS 0x16
+#define ANX7491_I2C_ADDR3_FLAGS 0x11
 
 #endif /* __CROS_EC_USB_RETIMER_ANX7491_H */
diff --git a/driver/retimer/bb_retimer.c b/driver/retimer/bb_retimer.c
index c515505900..897541bfc2 100644
--- a/driver/retimer/bb_retimer.c
+++ b/driver/retimer/bb_retimer.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,40 +10,45 @@
 #include "common.h"
 #include "console.h"
 #include "gpio.h"
+#include "hooks.h"
 #include "i2c.h"
 #include "task.h"
 #include "timer.h"
 #include "usb_pd.h"
 #include "util.h"
 
-#define BB_RETIMER_REG_SIZE	4
-#define BB_RETIMER_READ_SIZE	(BB_RETIMER_REG_SIZE + 1)
-#define BB_RETIMER_WRITE_SIZE	(BB_RETIMER_REG_SIZE + 2)
-#define BB_RETIMER_MUX_DATA_PRESENT (USB_PD_MUX_USB_ENABLED \
-				| USB_PD_MUX_DP_ENABLED \
-				| USB_PD_MUX_SAFE_MODE \
-				| USB_PD_MUX_TBT_COMPAT_ENABLED \
-				| USB_PD_MUX_USB4_ENABLED)
+#define BB_RETIMER_REG_SIZE 4
+#define BB_RETIMER_READ_SIZE (BB_RETIMER_REG_SIZE + 1)
+#define BB_RETIMER_WRITE_SIZE (BB_RETIMER_REG_SIZE + 2)
+#define BB_RETIMER_MUX_DATA_PRESENT                             \
+	(USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED |       \
+	 USB_PD_MUX_SAFE_MODE | USB_PD_MUX_TBT_COMPAT_ENABLED | \
+	 USB_PD_MUX_USB4_ENABLED)
 
-#define BB_RETIMER_MUX_USB_ALT_MODE (USB_PD_MUX_USB_ENABLED\
-				| USB_PD_MUX_DP_ENABLED \
-				| USB_PD_MUX_TBT_COMPAT_ENABLED \
-				| USB_PD_MUX_USB4_ENABLED)
+#define BB_RETIMER_MUX_USB_ALT_MODE                       \
+	(USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED | \
+	 USB_PD_MUX_TBT_COMPAT_ENABLED | USB_PD_MUX_USB4_ENABLED)
 
-#define BB_RETIMER_MUX_USB_DP_MODE (USB_PD_MUX_USB_ENABLED \
-				| USB_PD_MUX_DP_ENABLED \
-				| USB_PD_MUX_USB4_ENABLED)
+#define BB_RETIMER_MUX_USB_DP_MODE                        \
+	(USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED | \
+	 USB_PD_MUX_USB4_ENABLED)
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define BB_RETIMER_I2C_RETRY	5
+#define BB_RETIMER_I2C_RETRY 5
+
+/*
+ * Mutex for BB_RETIMER_REG_CONNECTION_STATE register, which can be
+ * accessed from multiple tasks.
+ */
+static mutex_t bb_retimer_lock[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 /**
  * Utility functions
  */
-static int bb_retimer_read(const struct usb_mux *me,
-			   const uint8_t offset, uint32_t *data)
+static int bb_retimer_read(const struct usb_mux *me, const uint8_t offset,
+			   uint32_t *data)
 {
 	int rv, retry = 0;
 	uint8_t buf[BB_RETIMER_READ_SIZE];
@@ -60,15 +65,15 @@ static int bb_retimer_read(const struct usb_mux *me,
 		 * byte[1:4] : Data [LSB -> MSB]
 		 * Stop
 		 */
-		rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags,
-		      &offset, 1, buf, BB_RETIMER_READ_SIZE);
+		rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags, &offset, 1, buf,
+			      BB_RETIMER_READ_SIZE);
 
 		if (rv == EC_SUCCESS)
 			break;
 
 		if (++retry >= BB_RETIMER_I2C_RETRY) {
-			CPRINTS("C%d: Retimer I2C read err=%d",
-				me->usb_port, rv);
+			CPRINTS("C%d: Retimer I2C read err=%d", me->usb_port,
+				rv);
 			return rv;
 		}
 		msleep(10);
@@ -82,8 +87,8 @@ static int bb_retimer_read(const struct usb_mux *me,
 	return EC_SUCCESS;
 }
 
-static int bb_retimer_write(const struct usb_mux *me,
-			    const uint8_t offset, uint32_t data)
+static int bb_retimer_write(const struct usb_mux *me, const uint8_t offset,
+			    uint32_t data)
 {
 	int rv, retry = 0;
 	uint8_t buf[BB_RETIMER_WRITE_SIZE];
@@ -109,14 +114,14 @@ static int bb_retimer_write(const struct usb_mux *me,
 	 */
 	while (1) {
 		rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags, buf,
-			     BB_RETIMER_WRITE_SIZE, NULL, 0);
+			      BB_RETIMER_WRITE_SIZE, NULL, 0);
 
 		if (rv == EC_SUCCESS)
 			break;
 
 		if (++retry >= BB_RETIMER_I2C_RETRY) {
-			CPRINTS("C%d: Retimer I2C write err=%d",
-				me->usb_port, rv);
+			CPRINTS("C%d: Retimer I2C write err=%d", me->usb_port,
+				rv);
 			break;
 		}
 		msleep(10);
@@ -157,7 +162,8 @@ static void retimer_set_state_dfp(int port, mux_state_t mux_state,
 				  uint32_t *set_retimer_con)
 {
 	union tbt_mode_resp_cable cable_resp = {
-		.raw_value = pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME) };
+		.raw_value = pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME)
+	};
 	union tbt_mode_resp_device dev_resp;
 	enum idh_ptype cable_type = get_usb_pd_cable_type(port);
 
@@ -171,7 +177,7 @@ static void retimer_set_state_dfp(int port, mux_state_t mux_state,
 	 *
 	 */
 	if (is_active_cable_element_retimer(port) &&
-	   (mux_state & BB_RETIMER_MUX_USB_DP_MODE))
+	    (mux_state & BB_RETIMER_MUX_USB_DP_MODE))
 		*set_retimer_con |= BB_RETIMER_RE_TIMER_DRIVER;
 
 	/*
@@ -184,7 +190,7 @@ static void retimer_set_state_dfp(int port, mux_state_t mux_state,
 	 */
 	if ((mux_state & BB_RETIMER_MUX_USB_ALT_MODE) &&
 	    ((cable_type == IDH_PTYPE_ACABLE) ||
-	      cable_resp.tbt_active_passive == TBT_CABLE_ACTIVE))
+	     cable_resp.tbt_active_passive == TBT_CABLE_ACTIVE))
 		*set_retimer_con |= BB_RETIMER_ACTIVE_PASSIVE;
 
 	if (mux_state & USB_PD_MUX_TBT_COMPAT_ENABLED ||
@@ -239,7 +245,7 @@ static void retimer_set_state_dfp(int port, mux_state_t mux_state,
 		 */
 		if ((cable_type == IDH_PTYPE_ACABLE ||
 		     cable_resp.tbt_active_passive == TBT_CABLE_ACTIVE) &&
-		     cable_resp.lsrx_comm == UNIDIR_LSRX_COMM)
+		    cable_resp.lsrx_comm == UNIDIR_LSRX_COMM)
 			*set_retimer_con |= BB_RETIMER_TBT_ACTIVE_LINK_TRAINING;
 
 		/*
@@ -251,9 +257,9 @@ static void retimer_set_state_dfp(int port, mux_state_t mux_state,
 		 * 10..11b - Reserved
 		 */
 		*set_retimer_con |= BB_RETIMER_USB4_TBT_CABLE_SPEED_SUPPORT(
-				    mux_state & USB_PD_MUX_TBT_COMPAT_ENABLED ?
-				    get_tbt_cable_speed(port) :
-				    get_usb4_cable_speed(port));
+			mux_state & USB_PD_MUX_TBT_COMPAT_ENABLED ?
+				get_tbt_cable_speed(port) :
+				get_usb4_cable_speed(port));
 
 		/*
 		 * Bits 29-28: TBT_GEN_SUPPORT
@@ -262,8 +268,8 @@ static void retimer_set_state_dfp(int port, mux_state_t mux_state,
 		 *                           20.0625Gb/s, 20.000Gb/s)
 		 * 10..11b - Reserved
 		 */
-		*set_retimer_con |= BB_RETIMER_TBT_CABLE_GENERATION(
-				       cable_resp.tbt_rounded);
+		*set_retimer_con |=
+			BB_RETIMER_TBT_CABLE_GENERATION(cable_resp.tbt_rounded);
 	}
 }
 
@@ -284,7 +290,8 @@ static void retimer_set_state_ufp(int port, mux_state_t mux_state,
 	/* TODO:b/168890624: Set USB4 retimer config for UFP */
 	if (mux_state & USB_PD_MUX_TBT_COMPAT_ENABLED) {
 		union tbt_dev_mode_enter_cmd ufp_tbt_enter_mode = {
-			.raw_value = pd_ufp_get_enter_mode(port)};
+			.raw_value = pd_ufp_get_enter_mode(port)
+		};
 		/*
 		 * Bit 2: RE_TIMER_DRIVER
 		 * 0 - Re-driver
@@ -316,9 +323,9 @@ static void retimer_set_state_ufp(int port, mux_state_t mux_state,
 		 */
 		if ((IS_ENABLED(CONFIG_USBC_RETIMER_INTEL_BB_VPRO_CAPABLE) &&
 		     ufp_tbt_enter_mode.intel_spec_b0 ==
-					VENDOR_SPECIFIC_SUPPORTED) ||
+			     VENDOR_SPECIFIC_SUPPORTED) ||
 		    ufp_tbt_enter_mode.vendor_spec_b1 ==
-					VENDOR_SPECIFIC_SUPPORTED)
+			    VENDOR_SPECIFIC_SUPPORTED)
 			*set_retimer_con |= BB_RETIMER_VPRO_DOCK_DP_OVERDRIVE;
 
 		/*
@@ -352,7 +359,7 @@ static void retimer_set_state_ufp(int port, mux_state_t mux_state,
 		 * Set according to TBT3 Enter Mode bit 18:16
 		 */
 		*set_retimer_con |= BB_RETIMER_USB4_TBT_CABLE_SPEED_SUPPORT(
-					ufp_tbt_enter_mode.tbt_cable_speed);
+			ufp_tbt_enter_mode.tbt_cable_speed);
 		/*
 		 * Bits 29-28: TBT_GEN_SUPPORT
 		 * 00b - 3rd generation TBT (10.3125 and 20.625Gb/s)
@@ -363,7 +370,7 @@ static void retimer_set_state_ufp(int port, mux_state_t mux_state,
 		 * Set according to TBT3 Enter Mode bit 20:19
 		 */
 		*set_retimer_con |= BB_RETIMER_TBT_CABLE_GENERATION(
-				       ufp_tbt_enter_mode.tbt_rounded);
+			ufp_tbt_enter_mode.tbt_rounded);
 	}
 }
 
@@ -376,10 +383,13 @@ static int retimer_set_state(const struct usb_mux *me, mux_state_t mux_state,
 	uint32_t set_retimer_con = 0;
 	uint8_t dp_pin_mode;
 	int port = me->usb_port;
+	int rv = 0;
 
 	/* This driver does not use host command ACKs */
 	*ack_required = false;
 
+	mutex_lock(&bb_retimer_lock[port]);
+
 	/*
 	 * Bit 0: DATA_CONNECTION_PRESENT
 	 * 0 - No connection present
@@ -413,14 +423,7 @@ static int retimer_set_state(const struct usb_mux *me, mux_state_t mux_state,
 			set_retimer_con |= BB_RETIMER_USB_3_SPEED;
 	}
 
-	/*
-	 * Bit 8: DP_CONNECTION
-	 * 0 – No DP connection
-	 * 1 – DP connected
-	 */
 	if (mux_state & USB_PD_MUX_DP_ENABLED) {
-		set_retimer_con |= BB_RETIMER_DP_CONNECTION;
-
 		/*
 		 * Bit 11-10: DP_PIN_ASSIGNMENT (ignored if BIT8 = 0)
 		 * 00 – Pin assignments E/E’
@@ -429,7 +432,7 @@ static int retimer_set_state(const struct usb_mux *me, mux_state_t mux_state,
 		 */
 		dp_pin_mode = get_dp_pin_mode(port);
 		if (dp_pin_mode == MODE_DP_PIN_C ||
-			dp_pin_mode == MODE_DP_PIN_D)
+		    dp_pin_mode == MODE_DP_PIN_D)
 			set_retimer_con |= BB_RETIMER_DP_PIN_ASSIGNMENT;
 
 		/*
@@ -471,22 +474,28 @@ static int retimer_set_state(const struct usb_mux *me, mux_state_t mux_state,
 		retimer_set_state_ufp(port, mux_state, &set_retimer_con);
 
 	/* Writing the register4 */
-	return bb_retimer_write(me, BB_RETIMER_REG_CONNECTION_STATE,
-			set_retimer_con);
+	rv = bb_retimer_write(me, BB_RETIMER_REG_CONNECTION_STATE,
+			      set_retimer_con);
+	mutex_unlock(&bb_retimer_lock[port]);
+	return rv;
 }
 
 void bb_retimer_hpd_update(const struct usb_mux *me, mux_state_t mux_state,
 			   bool *ack_required)
 {
 	uint32_t retimer_con_reg = 0;
+	int port = me->usb_port;
 
 	/* This driver does not use host command ACKs */
 	*ack_required = false;
 
+	mutex_lock(&bb_retimer_lock[port]);
+
 	if (bb_retimer_read(me, BB_RETIMER_REG_CONNECTION_STATE,
-			    &retimer_con_reg) != EC_SUCCESS)
+			    &retimer_con_reg) != EC_SUCCESS) {
+		mutex_unlock(&bb_retimer_lock[port]);
 		return;
-
+	}
 	/*
 	 * Bit 14: IRQ_HPD (ignored if BIT8 = 0)
 	 * 0 - No IRQ_HPD
@@ -498,19 +507,69 @@ void bb_retimer_hpd_update(const struct usb_mux *me, mux_state_t mux_state,
 		retimer_con_reg &= ~BB_RETIMER_IRQ_HPD;
 
 	/*
+	 * Bit 8: DP_CONNECTION
+	 * 0 - No DP connection
+	 * 1 - DP connected
+	 *
 	 * Bit 15: HPD_LVL (ignored if BIT8 = 0)
 	 * 0 - HPD_State Low
 	 * 1 - HPD_State High
+	 *
+	 * HDMI card connect to chromebook the DP_CONNECTION bit
+	 * would be enable.
+	 * It will increase BBR power consumption, so enable the DP bit
+	 * only when the HPD bit is set so that the retimer stays in
+	 * low power mode until the external monitor is connected.
 	 */
 	if (mux_state & USB_PD_MUX_HPD_LVL)
-		retimer_con_reg |= BB_RETIMER_HPD_LVL;
+		retimer_con_reg |=
+			(BB_RETIMER_HPD_LVL | BB_RETIMER_DP_CONNECTION);
 	else
-		retimer_con_reg &= ~BB_RETIMER_HPD_LVL;
+		retimer_con_reg &=
+			~(BB_RETIMER_HPD_LVL | BB_RETIMER_DP_CONNECTION);
 
 	/* Writing the register4 */
 	bb_retimer_write(me, BB_RETIMER_REG_CONNECTION_STATE, retimer_con_reg);
+
+	mutex_unlock(&bb_retimer_lock[port]);
+}
+
+void bb_retimer_set_usb3(const struct usb_mux *me, bool enable)
+{
+	int rv;
+	uint32_t reg_val = 0;
+	int port = me->usb_port;
+
+	mutex_lock(&bb_retimer_lock[port]);
+
+	rv = bb_retimer_read(me, BB_RETIMER_REG_CONNECTION_STATE, &reg_val);
+	if (rv != EC_SUCCESS) {
+		mutex_unlock(&bb_retimer_lock[port]);
+		return;
+	}
+	/* Bit 5: USB_3_CONNECTION */
+	WRITE_BIT(reg_val, 5, enable);
+	rv = bb_retimer_write(me, BB_RETIMER_REG_CONNECTION_STATE, reg_val);
+	if (rv != EC_SUCCESS) {
+		mutex_unlock(&bb_retimer_lock[port]);
+		return;
+	}
+
+	mutex_unlock(&bb_retimer_lock[port]);
 }
 
+#ifdef CONFIG_ZEPHYR
+static void init_retimer_mutexes(void)
+{
+	int port;
+
+	for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++) {
+		k_mutex_init(&bb_retimer_lock[port]);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, init_retimer_mutexes, HOOK_PRIO_FIRST);
+#endif
+
 static int retimer_low_power_mode(const struct usb_mux *me)
 {
 	return bb_retimer_power_enable(me, false);
@@ -538,14 +597,21 @@ static int retimer_init(const struct usb_mux *me)
 		return rv;
 
 	rv = bb_retimer_read(me, BB_RETIMER_REG_VENDOR_ID, &data);
+	/*
+	 * After reset, i2c controller may not be ready, if this fails,
+	 * retry one more time.
+	 * TODO: revisit the delay time after retimer reset.
+	 */
+	if (rv != EC_SUCCESS)
+		rv = bb_retimer_read(me, BB_RETIMER_REG_VENDOR_ID, &data);
 	if (rv != EC_SUCCESS)
 		return rv;
+	CPRINTS("C%d: retimer power enable success", me->usb_port);
 #ifdef CONFIG_USBC_RETIMER_INTEL_HB
 	if (data != BB_RETIMER_DEVICE_ID)
 		return EC_ERROR_INVAL;
 #else
-	if ((data != BB_RETIMER_VENDOR_ID_1) &&
-			data != BB_RETIMER_VENDOR_ID_2)
+	if ((data != BB_RETIMER_VENDOR_ID_1) && data != BB_RETIMER_VENDOR_ID_2)
 		return EC_ERROR_INVAL;
 
 	rv = bb_retimer_read(me, BB_RETIMER_REG_DEVICE_ID, &data);
@@ -566,12 +632,13 @@ const struct usb_mux_driver bb_usb_retimer = {
 };
 
 #ifdef CONFIG_CMD_RETIMER
-static int console_command_bb_retimer(int argc, char **argv)
+static int console_command_bb_retimer(int argc, const char **argv)
 {
 	char rw, *e;
 	int port, reg, data, val = 0;
 	int rv = EC_SUCCESS;
 	const struct usb_mux *mux;
+	const struct usb_mux_chain *mux_chain;
 
 	if (argc < 4)
 		return EC_ERROR_PARAM_COUNT;
@@ -581,14 +648,15 @@ static int console_command_bb_retimer(int argc, char **argv)
 	if (*e || !board_is_usb_pd_port_present(port))
 		return EC_ERROR_PARAM1;
 
-	mux = &usb_muxes[port];
-	while (mux) {
+	mux_chain = &usb_muxes[port];
+	while (mux_chain) {
+		mux = mux_chain->mux;
 		if (mux->driver == &bb_usb_retimer)
 			break;
-		mux = mux->next_mux;
+		mux_chain = mux_chain->next;
 	}
 
-	if (!mux)
+	if (!mux_chain)
 		return EC_ERROR_PARAM1;
 
 	/* Validate r/w selection */
@@ -608,17 +676,17 @@ static int console_command_bb_retimer(int argc, char **argv)
 			return EC_ERROR_PARAM4;
 	}
 
-	for (; mux != NULL; mux = mux->next_mux) {
+	for (; mux_chain != NULL; mux_chain = mux_chain->next) {
+		mux = mux_chain->mux;
 		if (mux->driver == &bb_usb_retimer) {
 			if (rw == 'r')
 				rv = bb_retimer_read(mux, reg, &data);
 			else {
 				rv = bb_retimer_write(mux, reg, val);
 				if (rv == EC_SUCCESS) {
-					rv = bb_retimer_read(
-						mux, reg, &data);
-				if (rv == EC_SUCCESS && data != val)
-					rv = EC_ERROR_UNKNOWN;
+					rv = bb_retimer_read(mux, reg, &data);
+					if (rv == EC_SUCCESS && data != val)
+						rv = EC_ERROR_UNKNOWN;
 				}
 			}
 			if (rv == EC_SUCCESS)
diff --git a/driver/retimer/kb800x.c b/driver/retimer/kb800x.c
index 44bd166c14..35ab5b183d 100644
--- a/driver/retimer/kb800x.c
+++ b/driver/retimer/kb800x.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -79,14 +79,15 @@ static const uint8_t usb_ss_lane_to_eb[] = { [KB800X_TX0] = KB800X_EB4,
 
 /* Assign a phy TX to an elastic buffer */
 static int kb800x_assign_tx_to_eb(const struct usb_mux *me,
-			  enum kb800x_phy_lane phy_lane, enum kb800x_eb eb)
+				  enum kb800x_phy_lane phy_lane,
+				  enum kb800x_eb eb)
 {
 	uint8_t field_value = 0;
 	uint8_t regval;
 	int rv;
 
 	field_value = KB800X_PHY_IS_AB(phy_lane) ? tx_eb_to_field_ab[eb] :
-						    tx_eb_to_field_cd[eb];
+						   tx_eb_to_field_cd[eb];
 
 	/* For lane1 of each PHY, shift by 3 bits */
 	field_value <<= 3 * KB800X_LANE_NUMBER_FROM_PHY(phy_lane);
@@ -95,20 +96,19 @@ static int kb800x_assign_tx_to_eb(const struct usb_mux *me,
 	if (rv)
 		return rv;
 	return kb800x_write(me, KB800X_REG_TXSEL_FROM_PHY(phy_lane),
-		     regval | field_value);
+			    regval | field_value);
 }
 
-
 /* Assign a phy RX to an elastic buffer */
 static int kb800x_assign_rx_to_eb(const struct usb_mux *me,
-			  enum kb800x_phy_lane phy_lane, enum kb800x_eb eb)
+				  enum kb800x_phy_lane phy_lane,
+				  enum kb800x_eb eb)
 {
 	uint16_t address = 0;
 	uint8_t field_value = 0;
 	uint8_t regval = 0;
 	int rv;
 
-
 	field_value = rx_phy_lane_to_field[phy_lane];
 	address = rx_eb_to_address[eb];
 
@@ -246,13 +246,11 @@ static int kb800x_xbar_override(const struct usb_mux *me)
 
 	for (i = KB800X_A0; i < KB800X_PHY_LANE_COUNT; ++i) {
 		rv = kb800x_assign_lane(
-			me, i,
-			kb800x_control[me->usb_port].ss_lanes[i]);
+			me, i, kb800x_control[me->usb_port].ss_lanes[i]);
 		if (rv)
 			return rv;
 	}
-	return kb800x_write(me, KB800X_REG_XBAR_OVR,
-				KB800X_XBAR_OVR_EN);
+	return kb800x_write(me, KB800X_REG_XBAR_OVR, KB800X_XBAR_OVR_EN);
 }
 #endif /* CONFIG_KB800X_CUSTOM_XBAR */
 
@@ -314,8 +312,8 @@ static int kb800x_dp_init(const struct usb_mux *me, mux_state_t mux_state)
 		me, KB800X_REG_ORIENTATION,
 		KB800X_ORIENTATION_DP_DFP |
 			((mux_state & USB_PD_MUX_POLARITY_INVERTED) ?
-				       KB800X_ORIENTATION_POLARITY :
-				       0x0));
+				 KB800X_ORIENTATION_POLARITY :
+				 0x0));
 }
 
 static int kb800x_usb3_init(const struct usb_mux *me, mux_state_t mux_state)
@@ -356,7 +354,7 @@ static int kb800x_cio_init(const struct usb_mux *me, mux_state_t mux_state)
 	if (!(mux_state & USB_PD_MUX_USB4_ENABLED)) {
 		/* Special configuration only for legacy mode */
 		if (cable_type == IDH_PTYPE_ACABLE ||
-		     cable_resp.tbt_active_passive == TBT_CABLE_ACTIVE) {
+		    cable_resp.tbt_active_passive == TBT_CABLE_ACTIVE) {
 			/* Active cable */
 			if (cable_resp.lsrx_comm == UNIDIR_LSRX_COMM) {
 				orientation |=
@@ -391,7 +389,7 @@ static int kb800x_set_state(const struct usb_mux *me, mux_state_t mux_state,
 		return rv;
 	/* Release memory map reset */
 	rv = kb800x_write(me, KB800X_REG_RESET,
-		     KB800X_RESET_MASK & ~KB800X_RESET_MM);
+			  KB800X_RESET_MASK & ~KB800X_RESET_MM);
 	if (rv)
 		return rv;
 
@@ -476,11 +474,12 @@ static int kb800x_enter_low_power_mode(const struct usb_mux *me)
 
 #ifdef CONFIG_CMD_RETIMER
 
-static int console_command_kb800x_xfer(int argc, char **argv)
+static int console_command_kb800x_xfer(int argc, const char **argv)
 {
 	char rw, *e;
 	int rv, port, reg, val;
 	uint8_t data;
+	const struct usb_mux_chain *mux_chain;
 	const struct usb_mux *mux;
 
 	if (argc < 4)
@@ -491,16 +490,18 @@ static int console_command_kb800x_xfer(int argc, char **argv)
 	if (*e || !board_is_usb_pd_port_present(port))
 		return EC_ERROR_PARAM1;
 
-	mux = &usb_muxes[port];
-	while (mux) {
-		if (mux->driver == &kb800x_usb_mux_driver)
+	mux_chain = &usb_muxes[port];
+	while (mux_chain) {
+		if (mux_chain->mux->driver == &kb800x_usb_mux_driver)
 			break;
-		mux = mux->next_mux;
+		mux_chain = mux_chain->next;
 	}
 
-	if (!mux)
+	if (!mux_chain)
 		return EC_ERROR_PARAM1;
 
+	mux = mux_chain->mux;
+
 	/* Validate r/w selection */
 	rw = argv[2][0];
 	if (rw != 'w' && rw != 'r')
diff --git a/driver/retimer/kb800x.h b/driver/retimer/kb800x.h
index 5f8cf2810d..1d041f3e29 100644
--- a/driver/retimer/kb800x.h
+++ b/driver/retimer/kb800x.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -12,54 +12,49 @@
 #include "gpio_signal.h"
 #include "usb_mux.h"
 
-#define KB800X_I2C_ADDR0_FLAGS	0x08
-#define KB800X_I2C_ADDR1_FLAGS	0x0C
+#define KB800X_I2C_ADDR0_FLAGS 0x08
+#define KB800X_I2C_ADDR1_FLAGS 0x0C
 
 extern const struct usb_mux_driver kb800x_usb_mux_driver;
 
 /* Set the protocol */
-#define KB800X_REG_PROTOCOL			0x0001
-#define KB800X_PROTOCOL_USB3			0x0
-#define KB800X_PROTOCOL_DPMF			0x1
-#define KB800X_PROTOCOL_DP			0x2
-#define KB800X_PROTOCOL_CIO			0x3
+#define KB800X_REG_PROTOCOL 0x0001
+#define KB800X_PROTOCOL_USB3 0x0
+#define KB800X_PROTOCOL_DPMF 0x1
+#define KB800X_PROTOCOL_DP 0x2
+#define KB800X_PROTOCOL_CIO 0x3
 
 /* Configure the lane orientaitons */
-#define KB800X_REG_ORIENTATION			0x0002
-#define KB800X_ORIENTATION_POLARITY		0x1
-#define KB800X_ORIENTATION_DP_UFP		0x4
-#define KB800X_ORIENTATION_DP_DFP		0x6
-#define KB800X_ORIENTATION_CIO_LANE_SWAP	0x8
+#define KB800X_REG_ORIENTATION 0x0002
+#define KB800X_ORIENTATION_POLARITY 0x1
+#define KB800X_ORIENTATION_DP_UFP 0x4
+#define KB800X_ORIENTATION_DP_DFP 0x6
+#define KB800X_ORIENTATION_CIO_LANE_SWAP 0x8
 /* Select one, 0x0 for non-legacy */
-#define KB800X_ORIENTATION_CIO_LEGACY_PASSIVE	(0x1 << 4)
-#define KB800X_ORIENTATION_CIO_LEGACY_UNIDIR	(0x2 << 4)
-#define KB800X_ORIENTATION_CIO_LEGACY_BIDIR	(0x3 << 4)
+#define KB800X_ORIENTATION_CIO_LEGACY_PASSIVE (0x1 << 4)
+#define KB800X_ORIENTATION_CIO_LEGACY_UNIDIR (0x2 << 4)
+#define KB800X_ORIENTATION_CIO_LEGACY_BIDIR (0x3 << 4)
 
-#define KB800X_REG_RESET			0x0006
-#define KB800X_RESET_FSM			BIT(0)
-#define KB800X_RESET_MM				BIT(1)
-#define KB800X_RESET_SERDES			BIT(2)
-#define KB800X_RESET_COM			BIT(3)
-#define KB800X_RESET_MASK			GENMASK(3, 0)
+#define KB800X_REG_RESET 0x0006
+#define KB800X_RESET_FSM BIT(0)
+#define KB800X_RESET_MM BIT(1)
+#define KB800X_RESET_SERDES BIT(2)
+#define KB800X_RESET_COM BIT(3)
+#define KB800X_RESET_MASK GENMASK(3, 0)
 
-#define KB800X_REG_XBAR_OVR			0x5040
-#define KB800X_XBAR_OVR_EN			BIT(6)
+#define KB800X_REG_XBAR_OVR 0x5040
+#define KB800X_XBAR_OVR_EN BIT(6)
 
 /* Registers to configure the elastic buffer input connection */
-#define KB800X_REG_XBAR_EB1SEL			0x5044
-#define KB800X_REG_XBAR_EB23SEL			0x5045
-#define KB800X_REG_XBAR_EB4SEL			0x5046
-#define KB800X_REG_XBAR_EB56SEL			0x5047
+#define KB800X_REG_XBAR_EB1SEL 0x5044
+#define KB800X_REG_XBAR_EB23SEL 0x5045
+#define KB800X_REG_XBAR_EB4SEL 0x5046
+#define KB800X_REG_XBAR_EB56SEL 0x5047
 
 /* Registers to configure the elastic buffer output connection (x=0-7) */
-#define KB800X_REG_TXSEL_FROM_PHY(x)		(0x5048+((x)/2))
+#define KB800X_REG_TXSEL_FROM_PHY(x) (0x5048 + ((x) / 2))
 
-enum kb800x_ss_lane {
-	KB800X_TX0 = 0,
-	KB800X_TX1,
-	KB800X_RX0,
-	KB800X_RX1
-};
+enum kb800x_ss_lane { KB800X_TX0 = 0, KB800X_TX1, KB800X_RX0, KB800X_RX1 };
 
 enum kb800x_phy_lane {
 	KB800X_A0 = 0,
@@ -82,8 +77,8 @@ enum kb800x_eb {
 	KB800X_EB6
 };
 
-#define KB800X_FLIP_SS_LANE(x) ((x) + 1 - 2*((x) & 0x1))
-#define KB800X_LANE_NUMBER_FROM_PHY(x) ((x) & 0x1)
+#define KB800X_FLIP_SS_LANE(x) ((x) + 1 - 2 * ((x)&0x1))
+#define KB800X_LANE_NUMBER_FROM_PHY(x) ((x)&0x1)
 #define KB800X_PHY_IS_AB(x) ((x) <= KB800X_B1)
 
 struct kb800x_control_t {
@@ -106,5 +101,4 @@ struct kb800x_control_t {
 
 extern struct kb800x_control_t kb800x_control[];
 
-
 #endif /* __CROS_EC_KB800X_H  */
diff --git a/driver/retimer/nb7v904m.c b/driver/retimer/nb7v904m.c
index 94e96230b2..58c57e5c95 100644
--- a/driver/retimer/nb7v904m.c
+++ b/driver/retimer/nb7v904m.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -12,8 +12,8 @@
 #include "nb7v904m.h"
 #include "usb_mux.h"
 
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USB, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args)
 
 #ifdef CONFIG_NB7V904M_LPM_OVERRIDE
 int nb7v904m_lpm_disable = 0;
@@ -21,18 +21,12 @@ int nb7v904m_lpm_disable = 0;
 
 static int nb7v904m_write(const struct usb_mux *me, int offset, int data)
 {
-	return i2c_write8(me->i2c_port,
-			  me->i2c_addr_flags,
-			  offset, data);
-
+	return i2c_write8(me->i2c_port, me->i2c_addr_flags, offset, data);
 }
 
 static int nb7v904m_read(const struct usb_mux *me, int offset, int *regval)
 {
-	return i2c_read8(me->i2c_port,
-			 me->i2c_addr_flags,
-			 offset, regval);
-
+	return i2c_read8(me->i2c_port, me->i2c_addr_flags, offset, regval);
 }
 
 static int set_low_power_mode(const struct usb_mux *me, bool enable)
@@ -68,7 +62,7 @@ static int nb7v904m_enter_low_power_mode(const struct usb_mux *me)
 
 /* Tune USB Eq All: This must be called on board_init context */
 int nb7v904m_tune_usb_set_eq(const struct usb_mux *me, uint8_t eq_a,
-			uint8_t eq_b, uint8_t eq_c, uint8_t eq_d)
+			     uint8_t eq_b, uint8_t eq_c, uint8_t eq_d)
 {
 	int rv = EC_SUCCESS;
 
@@ -89,7 +83,7 @@ int nb7v904m_tune_usb_set_eq(const struct usb_mux *me, uint8_t eq_a,
 
 /* Tune USB Flat Gain: This must be called on board_init context */
 int nb7v904m_tune_usb_flat_gain(const struct usb_mux *me, uint8_t gain_a,
-			uint8_t gain_b, uint8_t gain_c, uint8_t gain_d)
+				uint8_t gain_b, uint8_t gain_c, uint8_t gain_d)
 {
 	int rv = EC_SUCCESS;
 
@@ -110,7 +104,8 @@ int nb7v904m_tune_usb_flat_gain(const struct usb_mux *me, uint8_t gain_a,
 
 /* Set Loss Profile Matching : This must be called on board_init context */
 int nb7v904m_set_loss_profile_match(const struct usb_mux *me, uint8_t loss_a,
-			uint8_t loss_b, uint8_t loss_c, uint8_t loss_d)
+				    uint8_t loss_b, uint8_t loss_c,
+				    uint8_t loss_d)
 {
 	int rv = EC_SUCCESS;
 
@@ -157,6 +152,10 @@ static int nb7v904m_set_mux(const struct usb_mux *me, mux_state_t mux_state,
 	/* This driver does not use host command ACKs */
 	*ack_required = false;
 
+	/* This driver treats safe mode as none */
+	if (mux_state == USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
+
 	/* Turn off redriver if it's not needed at all. */
 	if (mux_state == USB_PD_MUX_NONE)
 		return nb7v904m_enter_low_power_mode(me);
@@ -168,8 +167,8 @@ static int nb7v904m_set_mux(const struct usb_mux *me, mux_state_t mux_state,
 	/* Clear operation mode field */
 	rv = nb7v904m_read(me, NB7V904M_REG_GEN_DEV_SETTINGS, &regval);
 	if (rv) {
-		CPRINTS("C%d %s: Failed to obtain dev settings!",
-			me->usb_port, __func__);
+		CPRINTS("C%d %s: Failed to obtain dev settings!", me->usb_port,
+			__func__);
 		return rv;
 	}
 	regval &= ~NB7V904M_OP_MODE_MASK;
@@ -193,9 +192,9 @@ static int nb7v904m_set_mux(const struct usb_mux *me, mux_state_t mux_state,
 
 	if (mux_state & USB_PD_MUX_DP_ENABLED) {
 		/* Connect AUX */
-		rv = nb7v904m_write(me, NB7V904M_REG_AUX_CH_CTRL, flipped ?
-				    NB7V904M_AUX_CH_FLIPPED :
-				    NB7V904M_AUX_CH_NORMAL);
+		rv = nb7v904m_write(me, NB7V904M_REG_AUX_CH_CTRL,
+				    flipped ? NB7V904M_AUX_CH_FLIPPED :
+					      NB7V904M_AUX_CH_NORMAL);
 		/* Enable all channels for DP */
 		regval |= NB7V904M_CH_EN_MASK;
 	} else {
diff --git a/driver/retimer/nb7v904m.h b/driver/retimer/nb7v904m.h
index d19602153c..07c3b4d51f 100644
--- a/driver/retimer/nb7v904m.h
+++ b/driver/retimer/nb7v904m.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -16,99 +16,99 @@
 #define NB7V904M_I2C_ADDR2 0x1C
 
 /* Registers */
-#define NB7V904M_REG_GEN_DEV_SETTINGS	0x00
-#define NB7V904M_REG_CH_A_EQ_SETTINGS	0x01
-#define NB7V904M_REG_CH_B_EQ_SETTINGS	0x03
-#define NB7V904M_REG_CH_C_EQ_SETTINGS	0x05
-#define NB7V904M_REG_CH_D_EQ_SETTINGS	0x07
-#define NB7V904M_REG_AUX_CH_CTRL        0x09
-#define NB7V904M_REG_CH_A_FLAT_GAIN		0x18
-#define NB7V904M_REG_CH_A_LOSS_CTRL		0x19
-#define NB7V904M_REG_CH_B_FLAT_GAIN		0x1a
-#define NB7V904M_REG_CH_B_LOSS_CTRL		0x1b
-#define NB7V904M_REG_CH_C_FLAT_GAIN		0x1c
-#define NB7V904M_REG_CH_C_LOSS_CTRL		0x1d
-#define NB7V904M_REG_CH_D_FLAT_GAIN		0x1e
-#define NB7V904M_REG_CH_D_LOSS_CTRL		0x1f
+#define NB7V904M_REG_GEN_DEV_SETTINGS 0x00
+#define NB7V904M_REG_CH_A_EQ_SETTINGS 0x01
+#define NB7V904M_REG_CH_B_EQ_SETTINGS 0x03
+#define NB7V904M_REG_CH_C_EQ_SETTINGS 0x05
+#define NB7V904M_REG_CH_D_EQ_SETTINGS 0x07
+#define NB7V904M_REG_AUX_CH_CTRL 0x09
+#define NB7V904M_REG_CH_A_FLAT_GAIN 0x18
+#define NB7V904M_REG_CH_A_LOSS_CTRL 0x19
+#define NB7V904M_REG_CH_B_FLAT_GAIN 0x1a
+#define NB7V904M_REG_CH_B_LOSS_CTRL 0x1b
+#define NB7V904M_REG_CH_C_FLAT_GAIN 0x1c
+#define NB7V904M_REG_CH_C_LOSS_CTRL 0x1d
+#define NB7V904M_REG_CH_D_FLAT_GAIN 0x1e
+#define NB7V904M_REG_CH_D_LOSS_CTRL 0x1f
 
 /* 0x00 - General Device Settings */
-#define NB7V904M_CHIP_EN        BIT(0)
-#define NB7V904M_USB_DP_NORMAL  BIT(1)
+#define NB7V904M_CHIP_EN BIT(0)
+#define NB7V904M_USB_DP_NORMAL BIT(1)
 #define NB7V904M_USB_DP_FLIPPED 0
-#define NB7V904M_DP_ONLY        BIT(2)
-#define NB7V904M_USB_ONLY       (BIT(3) | BIT(1))
-#define NB7V904M_OP_MODE_MASK   GENMASK(3, 1)
-#define NB7V904M_CH_A_EN        BIT(4)
-#define NB7V904M_CH_B_EN        BIT(5)
-#define NB7V904M_CH_C_EN        BIT(6)
-#define NB7V904M_CH_D_EN        BIT(7)
-#define NB7V904M_CH_EN_MASK     GENMASK(7, 4)
+#define NB7V904M_DP_ONLY BIT(2)
+#define NB7V904M_USB_ONLY (BIT(3) | BIT(1))
+#define NB7V904M_OP_MODE_MASK GENMASK(3, 1)
+#define NB7V904M_CH_A_EN BIT(4)
+#define NB7V904M_CH_B_EN BIT(5)
+#define NB7V904M_CH_C_EN BIT(6)
+#define NB7V904M_CH_D_EN BIT(7)
+#define NB7V904M_CH_EN_MASK GENMASK(7, 4)
 
 /* 0x01 - Channel A Equalization Settings */
-#define NB7V904M_CH_A_EQ_0_DB	0x0a
-#define NB7V904M_CH_A_EQ_2_DB	0x08
-#define NB7V904M_CH_A_EQ_4_DB	0x0e
-#define NB7V904M_CH_A_EQ_6_DB	0x0c
-#define NB7V904M_CH_A_EQ_8_DB	0x02
-#define NB7V904M_CH_A_EQ_10_DB	0x00
+#define NB7V904M_CH_A_EQ_0_DB 0x0a
+#define NB7V904M_CH_A_EQ_2_DB 0x08
+#define NB7V904M_CH_A_EQ_4_DB 0x0e
+#define NB7V904M_CH_A_EQ_6_DB 0x0c
+#define NB7V904M_CH_A_EQ_8_DB 0x02
+#define NB7V904M_CH_A_EQ_10_DB 0x00
 
 /* 0x03 - Channel B Equalization Settings */
-#define NB7V904M_CH_B_EQ_0_DB	0x0e
-#define NB7V904M_CH_B_EQ_2_DB	0x0c
-#define NB7V904M_CH_B_EQ_4_DB	0x0a
-#define NB7V904M_CH_B_EQ_6_DB	0x08
-#define NB7V904M_CH_B_EQ_8_DB	0x06
-#define NB7V904M_CH_B_EQ_10_DB	0x00
+#define NB7V904M_CH_B_EQ_0_DB 0x0e
+#define NB7V904M_CH_B_EQ_2_DB 0x0c
+#define NB7V904M_CH_B_EQ_4_DB 0x0a
+#define NB7V904M_CH_B_EQ_6_DB 0x08
+#define NB7V904M_CH_B_EQ_8_DB 0x06
+#define NB7V904M_CH_B_EQ_10_DB 0x00
 
 /* 0x05 - Channel C Equalization Settings */
-#define NB7V904M_CH_C_EQ_0_DB	0x0e
-#define NB7V904M_CH_C_EQ_2_DB	0x0c
-#define NB7V904M_CH_C_EQ_4_DB	0x0a
-#define NB7V904M_CH_C_EQ_6_DB	0x08
-#define NB7V904M_CH_C_EQ_8_DB	0x06
-#define NB7V904M_CH_C_EQ_10_DB	0x00
+#define NB7V904M_CH_C_EQ_0_DB 0x0e
+#define NB7V904M_CH_C_EQ_2_DB 0x0c
+#define NB7V904M_CH_C_EQ_4_DB 0x0a
+#define NB7V904M_CH_C_EQ_6_DB 0x08
+#define NB7V904M_CH_C_EQ_8_DB 0x06
+#define NB7V904M_CH_C_EQ_10_DB 0x00
 
 /* 0x07 - Channel D Equalization Settings */
-#define NB7V904M_CH_D_EQ_0_DB	0x0a
-#define NB7V904M_CH_D_EQ_2_DB	0x08
-#define NB7V904M_CH_D_EQ_4_DB	0x0e
-#define NB7V904M_CH_D_EQ_6_DB	0x0c
-#define NB7V904M_CH_D_EQ_8_DB	0x02
-#define NB7V904M_CH_D_EQ_10_DB	0x00
+#define NB7V904M_CH_D_EQ_0_DB 0x0a
+#define NB7V904M_CH_D_EQ_2_DB 0x08
+#define NB7V904M_CH_D_EQ_4_DB 0x0e
+#define NB7V904M_CH_D_EQ_6_DB 0x0c
+#define NB7V904M_CH_D_EQ_8_DB 0x02
+#define NB7V904M_CH_D_EQ_10_DB 0x00
 
 /* 0x09 - Auxiliary Channel Control */
-#define NB7V904M_AUX_CH_NORMAL   0
-#define NB7V904M_AUX_CH_FLIPPED  BIT(0)
-#define NB7V904M_AUX_CH_HI_Z     BIT(1)
+#define NB7V904M_AUX_CH_NORMAL 0
+#define NB7V904M_AUX_CH_FLIPPED BIT(0)
+#define NB7V904M_AUX_CH_HI_Z BIT(1)
 
 /* 0x18 - Channel A Flag Gain */
-#define NB7V904M_CH_A_GAIN_0_DB		0x00
-#define NB7V904M_CH_A_GAIN_1P5_DB	0x02
-#define NB7V904M_CH_A_GAIN_3P5_DB	0x03
+#define NB7V904M_CH_A_GAIN_0_DB 0x00
+#define NB7V904M_CH_A_GAIN_1P5_DB 0x02
+#define NB7V904M_CH_A_GAIN_3P5_DB 0x03
 
 /* 0x1a - Channel B Flag Gain */
-#define NB7V904M_CH_B_GAIN_0_DB		0x03
-#define NB7V904M_CH_B_GAIN_1P5_DB	0x01
-#define NB7V904M_CH_B_GAIN_3P5_DB	0x00
+#define NB7V904M_CH_B_GAIN_0_DB 0x03
+#define NB7V904M_CH_B_GAIN_1P5_DB 0x01
+#define NB7V904M_CH_B_GAIN_3P5_DB 0x00
 
 /* 0x1c - Channel C Flag Gain */
-#define NB7V904M_CH_C_GAIN_0_DB		0x03
-#define NB7V904M_CH_C_GAIN_1P5_DB	0x01
-#define NB7V904M_CH_C_GAIN_3P5_DB	0x00
+#define NB7V904M_CH_C_GAIN_0_DB 0x03
+#define NB7V904M_CH_C_GAIN_1P5_DB 0x01
+#define NB7V904M_CH_C_GAIN_3P5_DB 0x00
 
 /* 0x1e - Channel D Flag Gain */
-#define NB7V904M_CH_D_GAIN_0_DB		0x00
-#define NB7V904M_CH_D_GAIN_1P5_DB	0x02
-#define NB7V904M_CH_D_GAIN_3P5_DB	0x03
+#define NB7V904M_CH_D_GAIN_0_DB 0x00
+#define NB7V904M_CH_D_GAIN_1P5_DB 0x02
+#define NB7V904M_CH_D_GAIN_3P5_DB 0x03
 
 /* 0x19 - Channel A Loss Profile Matching Control */
 /* 0x1b - Channel B Loss Profile Matching Control */
 /* 0x1d - Channel C Loss Profile Matching Control */
 /* 0x1f - Channel D Loss Profile Matching Control */
-#define NB7V904M_LOSS_PROFILE_A		0x00
-#define NB7V904M_LOSS_PROFILE_B		0x01
-#define NB7V904M_LOSS_PROFILE_C		0x02
-#define NB7V904M_LOSS_PROFILE_D		0x03
+#define NB7V904M_LOSS_PROFILE_A 0x00
+#define NB7V904M_LOSS_PROFILE_B 0x01
+#define NB7V904M_LOSS_PROFILE_C 0x02
+#define NB7V904M_LOSS_PROFILE_D 0x03
 
 extern const struct usb_mux_driver nb7v904m_usb_redriver_drv;
 #ifdef CONFIG_NB7V904M_LPM_OVERRIDE
@@ -116,18 +116,19 @@ extern int nb7v904m_lpm_disable;
 #endif
 
 /* Use this value if tuning eq wants to be skipped  */
-#define NB7V904M_CH_ALL_SKIP_EQ	0xff
+#define NB7V904M_CH_ALL_SKIP_EQ 0xff
 int nb7v904m_tune_usb_set_eq(const struct usb_mux *me, uint8_t eq_a,
-			uint8_t eq_b, uint8_t eq_c, uint8_t eq_d);
+			     uint8_t eq_b, uint8_t eq_c, uint8_t eq_d);
 /* Use this value if tuning gain wants to be skipped  */
-#define NB7V904M_CH_ALL_SKIP_GAIN	0xff
+#define NB7V904M_CH_ALL_SKIP_GAIN 0xff
 int nb7v904m_tune_usb_flat_gain(const struct usb_mux *me, uint8_t gain_a,
-			uint8_t gain_b, uint8_t gain_c, uint8_t gain_d);
+				uint8_t gain_b, uint8_t gain_c, uint8_t gain_d);
 /* Use this value if loss profile control  wants to be skipped  */
-#define NB7V904M_CH_ALL_SKIP_LOSS	0xff
+#define NB7V904M_CH_ALL_SKIP_LOSS 0xff
 /* Control channel Loss Profile Matching */
 int nb7v904m_set_loss_profile_match(const struct usb_mux *me, uint8_t loss_a,
-			uint8_t loss_b, uint8_t loss_c, uint8_t loss_d);
+				    uint8_t loss_b, uint8_t loss_c,
+				    uint8_t loss_d);
 /* Control mapping between AUX and SBU */
 int nb7v904m_set_aux_ch_switch(const struct usb_mux *me, uint8_t aux_ch);
 #endif /* __CROS_EC_USB_REDRIVER_NB7V904M_H */
diff --git a/driver/retimer/pi3dpx1207.c b/driver/retimer/pi3dpx1207.c
index 8829c508a1..27ea474832 100644
--- a/driver/retimer/pi3dpx1207.c
+++ b/driver/retimer/pi3dpx1207.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -21,8 +21,7 @@ static uint8_t buf[PI3DPX1207_NUM_REGISTERS];
 /**
  * Local utility functions
  */
-static int pi3dpx1207_i2c_write(const struct usb_mux *me,
-				uint8_t offset,
+static int pi3dpx1207_i2c_write(const struct usb_mux *me, uint8_t offset,
 				uint8_t val)
 {
 	int rv = EC_SUCCESS;
@@ -44,8 +43,8 @@ static int pi3dpx1207_i2c_write(const struct usb_mux *me,
 		attempt = 0;
 		do {
 			attempt++;
-			rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags,
-				      NULL, 0, buf, offset);
+			rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags, NULL, 0,
+				      buf, offset);
 		} while ((rv != EC_SUCCESS) && (attempt < I2C_MAX_RETRIES));
 	}
 
@@ -55,8 +54,8 @@ static int pi3dpx1207_i2c_write(const struct usb_mux *me,
 		attempt = 0;
 		do {
 			attempt++;
-			rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags,
-				      buf, offset + 1, NULL, 0);
+			rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags, buf,
+				      offset + 1, NULL, 0);
 		} while ((rv != EC_SUCCESS) && (attempt < I2C_MAX_RETRIES));
 	}
 	return rv;
@@ -102,31 +101,35 @@ static int pi3dpx1207_set_mux(const struct usb_mux *me, mux_state_t mux_state,
 	/* This driver does not use host command ACKs */
 	*ack_required = false;
 
+	/* This driver treats safe mode as none */
+	if (mux_state == USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
+
 	/* USB */
 	if (mux_state & USB_PD_MUX_USB_ENABLED) {
 		gpio_or_ioex_set_level(gpio_enable, 1);
 		/* USB with DP */
 		if (mux_state & USB_PD_MUX_DP_ENABLED) {
 			gpio_or_ioex_set_level(gpio_dp_enable, 1);
-			mode_val |= (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-					? PI3DPX1207_MODE_CONF_USB_DP_FLIP
-					: PI3DPX1207_MODE_CONF_USB_DP;
+			mode_val |= (mux_state & USB_PD_MUX_POLARITY_INVERTED) ?
+					    PI3DPX1207_MODE_CONF_USB_DP_FLIP :
+					    PI3DPX1207_MODE_CONF_USB_DP;
 		}
 		/* USB without DP */
 		else {
 			gpio_or_ioex_set_level(gpio_dp_enable, 0);
-			mode_val |= (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-					? PI3DPX1207_MODE_CONF_USB_FLIP
-					: PI3DPX1207_MODE_CONF_USB;
+			mode_val |= (mux_state & USB_PD_MUX_POLARITY_INVERTED) ?
+					    PI3DPX1207_MODE_CONF_USB_FLIP :
+					    PI3DPX1207_MODE_CONF_USB;
 		}
 	}
 	/* DP without USB */
 	else if (mux_state & USB_PD_MUX_DP_ENABLED) {
 		gpio_or_ioex_set_level(gpio_enable, 1);
 		gpio_or_ioex_set_level(gpio_dp_enable, 1);
-		mode_val |= (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-				? PI3DPX1207_MODE_CONF_DP_FLIP
-				: PI3DPX1207_MODE_CONF_DP;
+		mode_val |= (mux_state & USB_PD_MUX_POLARITY_INVERTED) ?
+				    PI3DPX1207_MODE_CONF_DP_FLIP :
+				    PI3DPX1207_MODE_CONF_DP;
 	}
 	/* Nothing enabled, power down the retimer */
 	else {
diff --git a/driver/retimer/pi3dpx1207.h b/driver/retimer/pi3dpx1207.h
index ec3c9b42bc..b246052f2c 100644
--- a/driver/retimer/pi3dpx1207.h
+++ b/driver/retimer/pi3dpx1207.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -9,35 +9,35 @@
 #ifndef __CROS_EC_USB_RETIMER_PI3PDX1207_H
 #define __CROS_EC_USB_RETIMER_PI3PDX1207_H
 
-#define PI3DPX1207_I2C_ADDR_FLAGS	0x57
-#define PI3DPX1207_NUM_REGISTERS	32
+#define PI3DPX1207_I2C_ADDR_FLAGS 0x57
+#define PI3DPX1207_NUM_REGISTERS 32
 
 /* Register Offset 0 - Revision and Vendor ID */
-#define PI3DPX1207_VID_OFFSET		0
+#define PI3DPX1207_VID_OFFSET 0
 
-#define PI3DPX1207B_VID				0x03
-#define PI3DPX1207C_VID				0x13
+#define PI3DPX1207B_VID 0x03
+#define PI3DPX1207C_VID 0x13
 
 /* Register Offset 1 - Device Type/ID */
-#define PI3DPX1207_DID_OFFSET		1
+#define PI3DPX1207_DID_OFFSET 1
 
-#define PI3DPX1207_DID_ACTIVE_MUX		0x11
+#define PI3DPX1207_DID_ACTIVE_MUX 0x11
 
 /* Register Offset 3 - Mode Control */
-#define PI3DPX1207_MODE_OFFSET		3
+#define PI3DPX1207_MODE_OFFSET 3
 
-#define PI3DPX1207_MODE_WATCHDOG_EN		0x02
+#define PI3DPX1207_MODE_WATCHDOG_EN 0x02
 
-#define PI3DPX1207B_MODE_GEN_APP_EN		0x08
+#define PI3DPX1207B_MODE_GEN_APP_EN 0x08
 
-#define PI3DPX1207_MODE_CONF_SAFE		0x00
-#define PI3DPX1207_MODE_CONF_DP			0x20
-#define PI3DPX1207_MODE_CONF_DP_FLIP		0x30
-#define PI3DPX1207_MODE_CONF_USB		0x40
-#define PI3DPX1207_MODE_CONF_USB_FLIP		0x50
-#define PI3DPX1207_MODE_CONF_USB_DP		0x60
-#define PI3DPX1207_MODE_CONF_USB_DP_FLIP	0x70
-#define PI3DPX1207_MODE_CONF_USB_SUPER		0xC0
+#define PI3DPX1207_MODE_CONF_SAFE 0x00
+#define PI3DPX1207_MODE_CONF_DP 0x20
+#define PI3DPX1207_MODE_CONF_DP_FLIP 0x30
+#define PI3DPX1207_MODE_CONF_USB 0x40
+#define PI3DPX1207_MODE_CONF_USB_FLIP 0x50
+#define PI3DPX1207_MODE_CONF_USB_DP 0x60
+#define PI3DPX1207_MODE_CONF_USB_DP_FLIP 0x70
+#define PI3DPX1207_MODE_CONF_USB_SUPER 0xC0
 
 /* Supported USB retimer drivers */
 extern const struct usb_mux_driver pi3dpx1207_usb_retimer;
diff --git a/driver/retimer/pi3hdx1204.c b/driver/retimer/pi3hdx1204.c
index 0431610059..7cf963c7f9 100644
--- a/driver/retimer/pi3hdx1204.c
+++ b/driver/retimer/pi3hdx1204.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -9,8 +9,7 @@
 #include "i2c.h"
 #include "pi3hdx1204.h"
 
-int pi3hdx1204_enable(const int i2c_port,
-		      const uint16_t i2c_addr_flags,
+int pi3hdx1204_enable(const int i2c_port, const uint16_t i2c_addr_flags,
 		      const int enable)
 {
 	const uint8_t buf[PI3HDX1204_DE_OFFSET + 1] = {
@@ -27,8 +26,7 @@ int pi3hdx1204_enable(const int i2c_port,
 	};
 	int rv;
 
-	rv = i2c_xfer(i2c_port, i2c_addr_flags,
-		      buf, PI3HDX1204_DE_OFFSET + 1,
+	rv = i2c_xfer(i2c_port, i2c_addr_flags, buf, PI3HDX1204_DE_OFFSET + 1,
 		      NULL, 0);
 
 	if (rv)
diff --git a/driver/retimer/pi3hdx1204.h b/driver/retimer/pi3hdx1204.h
index f758149c10..637accaf56 100644
--- a/driver/retimer/pi3hdx1204.h
+++ b/driver/retimer/pi3hdx1204.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,62 +8,61 @@
 #ifndef __CROS_EC_USB_RETIMER_PI3HDX1204_H
 #define __CROS_EC_USB_RETIMER_PI3HDX1204_H
 
-#define PI3HDX1204_I2C_ADDR_FLAGS	0x60
+#define PI3HDX1204_I2C_ADDR_FLAGS 0x60
 
 /* Register Offset 0 - Activity */
-#define PI3HDX1204_ACTIVITY_OFFSET	0
+#define PI3HDX1204_ACTIVITY_OFFSET 0
 
 /* Register Offset 1 - Not Used */
-#define PI3HDX1204_NOT_USED_OFFSET	1
+#define PI3HDX1204_NOT_USED_OFFSET 1
 
 /* Register Offset 2 - Enable */
-#define PI3HDX1204_ENABLE_OFFSET	2
-#define PI3HDX1204_ENABLE_ALL_CHANNELS	0xF0
+#define PI3HDX1204_ENABLE_OFFSET 2
+#define PI3HDX1204_ENABLE_ALL_CHANNELS 0xF0
 
 /* Register Offset 3 - EQ setting BIT7-4:CH1, BIT3-0:CH0 */
-#define PI3HDX1204_EQ_CH0_CH1_OFFSET	3
+#define PI3HDX1204_EQ_CH0_CH1_OFFSET 3
 
 /* Register Offset 4 - EQ setting BIT7-4:CH3, BIT3-0:CH2 */
-#define PI3HDX1204_EQ_CH2_CH3_OFFSET	4
+#define PI3HDX1204_EQ_CH2_CH3_OFFSET 4
 
 /* EQ setting for two channel */
-#define PI3HDX1204_EQ_DB25	0x00
-#define PI3HDX1204_EQ_DB80	0x11
-#define PI3HDX1204_EQ_DB110	0x22
-#define PI3HDX1204_EQ_DB220	0x33
-#define PI3HDX1204_EQ_DB410	0x44
-#define PI3HDX1204_EQ_DB710	0x55
-#define PI3HDX1204_EQ_DB900	0x66
-#define PI3HDX1204_EQ_DB1030	0x77
-#define PI3HDX1204_EQ_DB1180	0x88
-#define PI3HDX1204_EQ_DB1390	0x99
-#define PI3HDX1204_EQ_DB1530	0xAA
-#define PI3HDX1204_EQ_DB1690	0xBB
-#define PI3HDX1204_EQ_DB1790	0xCC
-#define PI3HDX1204_EQ_DB1920	0xDD
-#define PI3HDX1204_EQ_DB2050	0xEE
-#define PI3HDX1204_EQ_DB2220	0xFF
+#define PI3HDX1204_EQ_DB25 0x00
+#define PI3HDX1204_EQ_DB80 0x11
+#define PI3HDX1204_EQ_DB110 0x22
+#define PI3HDX1204_EQ_DB220 0x33
+#define PI3HDX1204_EQ_DB410 0x44
+#define PI3HDX1204_EQ_DB710 0x55
+#define PI3HDX1204_EQ_DB900 0x66
+#define PI3HDX1204_EQ_DB1030 0x77
+#define PI3HDX1204_EQ_DB1180 0x88
+#define PI3HDX1204_EQ_DB1390 0x99
+#define PI3HDX1204_EQ_DB1530 0xAA
+#define PI3HDX1204_EQ_DB1690 0xBB
+#define PI3HDX1204_EQ_DB1790 0xCC
+#define PI3HDX1204_EQ_DB1920 0xDD
+#define PI3HDX1204_EQ_DB2050 0xEE
+#define PI3HDX1204_EQ_DB2220 0xFF
 
 /* Register Offset 5 - Output Voltage Swing Setting */
-#define PI3HDX1204_VOD_OFFSET	5
-#define PI3HDX1204_VOD_80_ALL_CHANNELS	0x00
-#define PI3HDX1204_VOD_95_ALL_CHANNELS	0x55
-#define PI3HDX1204_VOD_115_ALL_CHANNELS	0xAA
-#define PI3HDX1204_VOD_130_ALL_CHANNELS	0xFF
+#define PI3HDX1204_VOD_OFFSET 5
+#define PI3HDX1204_VOD_80_ALL_CHANNELS 0x00
+#define PI3HDX1204_VOD_95_ALL_CHANNELS 0x55
+#define PI3HDX1204_VOD_115_ALL_CHANNELS 0xAA
+#define PI3HDX1204_VOD_130_ALL_CHANNELS 0xFF
 
 /* Register Offset 6 - Output De-emphasis Setting */
-#define PI3HDX1204_DE_OFFSET	6
-#define PI3HDX1204_DE_DB_0		0x00
-#define PI3HDX1204_DE_DB_MINUS5		0x55
-#define PI3HDX1204_DE_DB_MINUS7		0xAA
-#define PI3HDX1204_DE_DB_MINUS10	0xFF
+#define PI3HDX1204_DE_OFFSET 6
+#define PI3HDX1204_DE_DB_0 0x00
+#define PI3HDX1204_DE_DB_MINUS5 0x55
+#define PI3HDX1204_DE_DB_MINUS7 0xAA
+#define PI3HDX1204_DE_DB_MINUS10 0xFF
 
 /* Delay for I2C to be ready after power on. */
 #define PI3HDX1204_POWER_ON_DELAY_MS 13
 
 /* Enable or disable the PI3HDX1204. */
-int pi3hdx1204_enable(const int i2c_port,
-		      const uint16_t i2c_addr_flags,
+int pi3hdx1204_enable(const int i2c_port, const uint16_t i2c_addr_flags,
 		      const int enable);
 
 struct pi3hdx1204_tuning {
diff --git a/driver/retimer/ps8802.c b/driver/retimer/ps8802.c
index 9738123ace..e2d93a25b4 100644
--- a/driver/retimer/ps8802.c
+++ b/driver/retimer/ps8802.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -16,22 +16,19 @@
 #define PS8802_DEBUG 0
 #define PS8802_I2C_WAKE_DELAY 500
 
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USB, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args)
 
 int ps8802_i2c_read(const struct usb_mux *me, int page, int offset, int *data)
 {
 	int rv;
 
-	rv = i2c_read8(me->i2c_port,
-		       me->i2c_addr_flags + page,
-		       offset, data);
+	rv = i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset, data);
 
 	if (PS8802_DEBUG)
 		ccprintf("%s(%d:0x%02X, 0x%02X) =>0x%02X\n", __func__,
-			 me->i2c_port,
-			 me->i2c_addr_flags + page,
-			 offset, *data);
+			 me->i2c_port, me->i2c_addr_flags + page, offset,
+			 *data);
 
 	return rv;
 }
@@ -42,58 +39,43 @@ int ps8802_i2c_write(const struct usb_mux *me, int page, int offset, int data)
 	int pre_val, post_val;
 
 	if (PS8802_DEBUG)
-		i2c_read8(me->i2c_port,
-			me->i2c_addr_flags + page,
-			offset, &pre_val);
+		i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset,
+			  &pre_val);
 
-	rv = i2c_write8(me->i2c_port,
-			me->i2c_addr_flags + page,
-			offset, data);
+	rv = i2c_write8(me->i2c_port, me->i2c_addr_flags + page, offset, data);
 
 	if (PS8802_DEBUG) {
-		i2c_read8(me->i2c_port,
-			me->i2c_addr_flags + page,
-			offset, &post_val);
+		i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset,
+			  &post_val);
 
 		ccprintf("%s(%d:0x%02X, 0x%02X, 0x%02X) "
-			"0x%02X=>0x%02X\n",
-			 __func__,
-			 me->i2c_port,
-			 me->i2c_addr_flags + page,
-			 offset, data,
-			 pre_val, post_val);
+			 "0x%02X=>0x%02X\n",
+			 __func__, me->i2c_port, me->i2c_addr_flags + page,
+			 offset, data, pre_val, post_val);
 	}
 
 	return rv;
 }
 
-int ps8802_i2c_write16(const struct usb_mux *me, int page, int offset,
-		       int data)
+int ps8802_i2c_write16(const struct usb_mux *me, int page, int offset, int data)
 {
 	int rv;
 	int pre_val, post_val;
 
 	if (PS8802_DEBUG)
-		i2c_read16(me->i2c_port,
-			   me->i2c_addr_flags + page,
-			   offset, &pre_val);
+		i2c_read16(me->i2c_port, me->i2c_addr_flags + page, offset,
+			   &pre_val);
 
-	rv = i2c_write16(me->i2c_port,
-			 me->i2c_addr_flags + page,
-			 offset, data);
+	rv = i2c_write16(me->i2c_port, me->i2c_addr_flags + page, offset, data);
 
 	if (PS8802_DEBUG) {
-		i2c_read16(me->i2c_port,
-			   me->i2c_addr_flags + page,
-			   offset, &post_val);
+		i2c_read16(me->i2c_port, me->i2c_addr_flags + page, offset,
+			   &post_val);
 
 		ccprintf("%s(%d:0x%02X, 0x%02X, 0x%04X) "
 			 "0x%04X=>0x%04X\n",
-			 __func__,
-			 me->i2c_port,
-			 me->i2c_addr_flags + page,
-			 offset, data,
-			 pre_val, post_val);
+			 __func__, me->i2c_port, me->i2c_addr_flags + page,
+			 offset, data, pre_val, post_val);
 	}
 
 	return rv;
@@ -106,62 +88,46 @@ int ps8802_i2c_field_update8(const struct usb_mux *me, int page, int offset,
 	int pre_val, post_val;
 
 	if (PS8802_DEBUG)
-		i2c_read8(me->i2c_port,
-			  me->i2c_addr_flags + page,
-			  offset, &pre_val);
+		i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset,
+			  &pre_val);
 
-	rv = i2c_field_update8(me->i2c_port,
-			       me->i2c_addr_flags + page,
-			       offset,
-			       field_mask,
-			       set_value);
+	rv = i2c_field_update8(me->i2c_port, me->i2c_addr_flags + page, offset,
+			       field_mask, set_value);
 
 	if (PS8802_DEBUG) {
-		i2c_read8(me->i2c_port,
-			  me->i2c_addr_flags + page,
-			  offset, &post_val);
+		i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset,
+			  &post_val);
 
 		ccprintf("%s(%d:0x%02X, 0x%02X, 0x%02X, 0x%02X) "
 			 "0x%02X=>0x%02X\n",
-			 __func__,
-			 me->i2c_port,
-			 me->i2c_addr_flags + page,
-			 offset, field_mask, set_value,
-			 pre_val, post_val);
+			 __func__, me->i2c_port, me->i2c_addr_flags + page,
+			 offset, field_mask, set_value, pre_val, post_val);
 	}
 
 	return rv;
 }
 
 int ps8802_i2c_field_update16(const struct usb_mux *me, int page, int offset,
-			     uint16_t field_mask, uint16_t set_value)
+			      uint16_t field_mask, uint16_t set_value)
 {
 	int rv;
 	int pre_val, post_val;
 
 	if (PS8802_DEBUG)
-		i2c_read16(me->i2c_port,
-			   me->i2c_addr_flags + page,
-			   offset, &pre_val);
+		i2c_read16(me->i2c_port, me->i2c_addr_flags + page, offset,
+			   &pre_val);
 
-	rv = i2c_field_update16(me->i2c_port,
-				me->i2c_addr_flags + page,
-				offset,
-				field_mask,
-				set_value);
+	rv = i2c_field_update16(me->i2c_port, me->i2c_addr_flags + page, offset,
+				field_mask, set_value);
 
 	if (PS8802_DEBUG) {
-		i2c_read16(me->i2c_port,
-			   me->i2c_addr_flags + page,
-			   offset, &post_val);
+		i2c_read16(me->i2c_port, me->i2c_addr_flags + page, offset,
+			   &post_val);
 
 		ccprintf("%s(%d:0x%02X, 0x%02X, 0x%02X, 0x%04X) "
 			 "0x%04X=>0x%04X\n",
-			 __func__,
-			 me->i2c_port,
-			 me->i2c_addr_flags + page,
-			 offset, field_mask, set_value,
-			 pre_val, post_val);
+			 __func__, me->i2c_port, me->i2c_addr_flags + page,
+			 offset, field_mask, set_value, pre_val, post_val);
 	}
 
 	return rv;
@@ -179,9 +145,7 @@ int ps8802_i2c_wake(const struct usb_mux *me)
 
 	/* If in standby, first read will fail, second should succeed. */
 	for (int i = 0; i < 2; i++) {
-		rv = ps8802_i2c_read(me,
-				     PS8802_REG_PAGE2,
-				     PS8802_REG2_MODE,
+		rv = ps8802_i2c_read(me, PS8802_REG_PAGE2, PS8802_REG2_MODE,
 				     &data);
 		if (rv == EC_SUCCESS)
 			return rv;
@@ -200,7 +164,7 @@ static int ps8802_enter_low_power_mode(const struct usb_mux *me)
 	int rv;
 
 	rv = ps8802_i2c_write(me, PS8802_REG_PAGE2, PS8802_REG2_MODE,
-		  PS8802_MODE_STANDBY_MODE);
+			      PS8802_MODE_STANDBY_MODE);
 
 	if (rv)
 		CPRINTS("C%d: PS8802: Failed to enter low power mode!",
@@ -224,9 +188,13 @@ static int ps8802_set_mux(const struct usb_mux *me, mux_state_t mux_state,
 	/* This driver does not use host command ACKs */
 	*ack_required = false;
 
+	/* This driver treats safe mode as none */
+	if (mux_state == USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
+
 	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
-		return (mux_state == USB_PD_MUX_NONE) ? EC_SUCCESS
-						      : EC_ERROR_NOT_POWERED;
+		return (mux_state == USB_PD_MUX_NONE) ? EC_SUCCESS :
+							EC_ERROR_NOT_POWERED;
 
 	/* Make sure the PS8802 is awake */
 	rv = ps8802_i2c_wake(me);
@@ -234,18 +202,16 @@ static int ps8802_set_mux(const struct usb_mux *me, mux_state_t mux_state,
 		return rv;
 
 	if (PS8802_DEBUG)
-		ccprintf("%s(%d, 0x%02X) %s %s %s\n",
-			 __func__, me->usb_port, mux_state,
-			 (mux_state & USB_PD_MUX_USB_ENABLED)	? "USB" : "",
-			 (mux_state & USB_PD_MUX_DP_ENABLED)	? "DP" : "",
-			 (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-								? "FLIP" : "");
+		ccprintf("%s(%d, 0x%02X) %s %s %s\n", __func__, me->usb_port,
+			 mux_state,
+			 (mux_state & USB_PD_MUX_USB_ENABLED) ? "USB" : "",
+			 (mux_state & USB_PD_MUX_DP_ENABLED) ? "DP" : "",
+			 (mux_state & USB_PD_MUX_POLARITY_INVERTED) ? "FLIP" :
+								      "");
 
 	/* Set the mode and flip */
-	val = (PS8802_MODE_DP_REG_CONTROL |
-	       PS8802_MODE_USB_REG_CONTROL |
-	       PS8802_MODE_FLIP_REG_CONTROL |
-	       PS8802_MODE_IN_HPD_REG_CONTROL);
+	val = (PS8802_MODE_DP_REG_CONTROL | PS8802_MODE_USB_REG_CONTROL |
+	       PS8802_MODE_FLIP_REG_CONTROL | PS8802_MODE_IN_HPD_REG_CONTROL);
 
 	if (mux_state & USB_PD_MUX_USB_ENABLED)
 		val |= PS8802_MODE_USB_ENABLE;
@@ -254,10 +220,7 @@ static int ps8802_set_mux(const struct usb_mux *me, mux_state_t mux_state,
 	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
 		val |= PS8802_MODE_FLIP_ENABLE;
 
-	rv = ps8802_i2c_write(me,
-			      PS8802_REG_PAGE2,
-			      PS8802_REG2_MODE,
-			      val);
+	rv = ps8802_i2c_write(me, PS8802_REG_PAGE2, PS8802_REG2_MODE, val);
 
 	return rv;
 }
@@ -276,10 +239,7 @@ static int ps8802_get_mux(const struct usb_mux *me, mux_state_t *mux_state)
 	if (rv)
 		return rv;
 
-	rv = ps8802_i2c_read(me,
-			     PS8802_REG_PAGE2,
-			     PS8802_REG2_MODE,
-			     &val);
+	rv = ps8802_i2c_read(me, PS8802_REG_PAGE2, PS8802_REG2_MODE, &val);
 	if (rv)
 		return rv;
 
@@ -309,8 +269,7 @@ int ps8802_chg_i2c_addr(int i2c_port)
 {
 	int rv;
 
-	rv = i2c_write8(i2c_port,
-			PS8802_P1_ADDR, PS8802_ADDR_CFG,
+	rv = i2c_write8(i2c_port, PS8802_P1_ADDR, PS8802_ADDR_CFG,
 			PS8802_I2C_ADDR_FLAGS_ALT);
 
 	return rv;
diff --git a/driver/retimer/ps8802.h b/driver/retimer/ps8802.h
index 5f4b9e4e9c..b8a51de62d 100644
--- a/driver/retimer/ps8802.h
+++ b/driver/retimer/ps8802.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -13,70 +13,70 @@
  * PS8802 uses 7-bit I2C addresses 0x08 to 0x17 (ADDR=L).
  * Page 0 = 0x08, Page 1 = 0x09, Page 2 = 0x0A.
  */
-#define PS8802_I2C_ADDR_FLAGS	0x08
+#define PS8802_I2C_ADDR_FLAGS 0x08
 
 /*
  * PS8802 uses 7-bit I2C addresses 0x28 to 0x37.
  * Page 0 = 0x028, Page 1 = 0x29, Page 2 = 0x2A.
  */
-#define PS8802_I2C_ADDR_FLAGS_CUSTOM	0x28
+#define PS8802_I2C_ADDR_FLAGS_CUSTOM 0x28
 
 /*
  * PAGE 0 Register Definitions
  */
-#define PS8802_REG_PAGE0	0x00
+#define PS8802_REG_PAGE0 0x00
 
-#define PS8802_REG0_TX_STATUS		0x72
-#define PS8802_REG0_RX_STATUS		0x76
-#define PS8802_STATUS_NORMAL_OPERATION		BIT(7)
-#define PS8802_STATUS_10_GBPS			BIT(5)
+#define PS8802_REG0_TX_STATUS 0x72
+#define PS8802_REG0_RX_STATUS 0x76
+#define PS8802_STATUS_NORMAL_OPERATION BIT(7)
+#define PS8802_STATUS_10_GBPS BIT(5)
 
 /*
  * PAGE 1 Register Definitions
  */
-#define PS8802_REG_PAGE1	0x01
-
-#define PS8802_800MV_LEVEL_TUNING	0x8A
-#define PS8802_EXTRA_SWING_LEVEL_P0_DEFAULT	0X00
-#define PS8802_EXTRA_SWING_LEVEL_P0_DOWN_1	0X01
-#define PS8802_EXTRA_SWING_LEVEL_P0_DOWN_2	0X02
-#define PS8802_EXTRA_SWING_LEVEL_P0_DOWN_3	0X03
-#define PS8802_EXTRA_SWING_LEVEL_P0_DOWN_4	0X04
-#define PS8802_EXTRA_SWING_LEVEL_P0_UP_1	0X05
-#define PS8802_EXTRA_SWING_LEVEL_P0_UP_2	0X06
-#define PS8802_EXTRA_SWING_LEVEL_P0_UP_3	0X07
-#define PS8802_EXTRA_SWING_LEVEL_P0_MASK	0X07
-
-#define PS8802_REG_DCIRX		0x4B
-#define PS8802_AUTO_DCI_MODE_DISABLE		BIT(7)
-#define PS8802_FORCE_DCI_MODE			BIT(6)
+#define PS8802_REG_PAGE1 0x01
+
+#define PS8802_800MV_LEVEL_TUNING 0x8A
+#define PS8802_EXTRA_SWING_LEVEL_P0_DEFAULT 0X00
+#define PS8802_EXTRA_SWING_LEVEL_P0_DOWN_1 0X01
+#define PS8802_EXTRA_SWING_LEVEL_P0_DOWN_2 0X02
+#define PS8802_EXTRA_SWING_LEVEL_P0_DOWN_3 0X03
+#define PS8802_EXTRA_SWING_LEVEL_P0_DOWN_4 0X04
+#define PS8802_EXTRA_SWING_LEVEL_P0_UP_1 0X05
+#define PS8802_EXTRA_SWING_LEVEL_P0_UP_2 0X06
+#define PS8802_EXTRA_SWING_LEVEL_P0_UP_3 0X07
+#define PS8802_EXTRA_SWING_LEVEL_P0_MASK 0X07
+
+#define PS8802_REG_DCIRX 0x4B
+#define PS8802_AUTO_DCI_MODE_DISABLE BIT(7)
+#define PS8802_FORCE_DCI_MODE BIT(6)
 
 /*
  * PAGE 2 Register Definitions
  */
-#define PS8802_REG_PAGE2	0x02
-
-#define PS8802_REG2_USB_SSEQ_LEVEL	0x02
-#define PS8802_REG2_USB_CEQ_LEVEL	0x04
-#define PS8802_USBEQ_LEVEL_UP_12DB		(0x0000 | 0x0003)
-#define PS8802_USBEQ_LEVEL_UP_13DB		(0x0400 | 0x0007)
-#define PS8802_USBEQ_LEVEL_UP_16DB		(0x0C00 | 0x000F)
-#define PS8802_USBEQ_LEVEL_UP_17DB		(0x1C00 | 0x001F)
-#define PS8802_USBEQ_LEVEL_UP_18DB		(0x3C00 | 0x003F)
-#define PS8802_USBEQ_LEVEL_UP_19DB		(0x7C00 | 0x007F)
-#define PS8802_USBEQ_LEVEL_UP_20DB		(0xFC00 | 0x00FF)
-#define PS8802_USBEQ_LEVEL_UP_23DB		(0xFD00 | 0x01FF)
-#define PS8802_USBEQ_LEVEL_UP_MASK		0xFDFF
-
-#define PS8802_REG2_MODE		0x06
-#define PS8802_MODE_DP_REG_CONTROL		BIT(7)
-#define PS8802_MODE_DP_ENABLE			BIT(6)
-#define PS8802_MODE_USB_REG_CONTROL		BIT(5)
-#define PS8802_MODE_USB_ENABLE			BIT(4)
-#define PS8802_MODE_FLIP_REG_CONTROL		BIT(3)
-#define PS8802_MODE_FLIP_ENABLE			BIT(2)
-#define PS8802_MODE_IN_HPD_REG_CONTROL		BIT(1)
-#define PS8802_MODE_IN_HPD_ENABLE		BIT(0)
+#define PS8802_REG_PAGE2 0x02
+
+#define PS8802_REG2_USB_SSEQ_LEVEL 0x02
+#define PS8802_REG2_USB_CEQ_LEVEL 0x04
+#define PS8802_USBEQ_LEVEL_UP_12DB (0x0000 | 0x0003)
+#define PS8802_USBEQ_LEVEL_UP_13DB (0x0400 | 0x0007)
+#define PS8802_USBEQ_LEVEL_UP_16DB (0x0C00 | 0x000F)
+#define PS8802_USBEQ_LEVEL_UP_17DB (0x1C00 | 0x001F)
+#define PS8802_USBEQ_LEVEL_UP_18DB (0x3C00 | 0x003F)
+#define PS8802_USBEQ_LEVEL_UP_19DB (0x7C00 | 0x007F)
+#define PS8802_USBEQ_LEVEL_UP_20DB (0xFC00 | 0x00FF)
+#define PS8802_USBEQ_LEVEL_UP_23DB (0xFD00 | 0x01FF)
+#define PS8802_USBEQ_LEVEL_UP_MASK 0xFDFF
+
+#define PS8802_REG2_MODE 0x06
+#define PS8802_MODE_DP_REG_CONTROL BIT(7)
+#define PS8802_MODE_DP_ENABLE BIT(6)
+#define PS8802_MODE_USB_REG_CONTROL BIT(5)
+#define PS8802_MODE_USB_ENABLE BIT(4)
+#define PS8802_MODE_FLIP_REG_CONTROL BIT(3)
+#define PS8802_MODE_FLIP_ENABLE BIT(2)
+#define PS8802_MODE_IN_HPD_REG_CONTROL BIT(1)
+#define PS8802_MODE_IN_HPD_ENABLE BIT(0)
 
 /*
  * Support power saving mode, Bit7 Disable
@@ -84,23 +84,23 @@
  * FLIP pin, Bit1 Display IN_HPD pin, [Bit6 Bit4]
  * 00: I2C standy by mode.
  */
-#define PS8802_MODE_STANDBY_MODE		0xAA
-
-#define PS8802_REG2_DPEQ_LEVEL		0x07
-#define PS8802_DPEQ_LEVEL_UP_9DB		0x00
-#define PS8802_DPEQ_LEVEL_UP_11DB		0x01
-#define PS8802_DPEQ_LEVEL_UP_12DB		0x02
-#define PS8802_DPEQ_LEVEL_UP_14DB		0x03
-#define PS8802_DPEQ_LEVEL_UP_17DB		0x04
-#define PS8802_DPEQ_LEVEL_UP_18DB		0x05
-#define PS8802_DPEQ_LEVEL_UP_19DB		0x06
-#define PS8802_DPEQ_LEVEL_UP_20DB		0x07
-#define PS8802_DPEQ_LEVEL_UP_21DB		0x08
-#define PS8802_DPEQ_LEVEL_UP_MASK		0x0F
-
-#define PS8802_P1_ADDR			0x0A
-#define PS8802_ADDR_CFG			0xB0
-#define PS8802_I2C_ADDR_FLAGS_ALT	0x50
+#define PS8802_MODE_STANDBY_MODE 0xAA
+
+#define PS8802_REG2_DPEQ_LEVEL 0x07
+#define PS8802_DPEQ_LEVEL_UP_9DB 0x00
+#define PS8802_DPEQ_LEVEL_UP_11DB 0x01
+#define PS8802_DPEQ_LEVEL_UP_12DB 0x02
+#define PS8802_DPEQ_LEVEL_UP_14DB 0x03
+#define PS8802_DPEQ_LEVEL_UP_17DB 0x04
+#define PS8802_DPEQ_LEVEL_UP_18DB 0x05
+#define PS8802_DPEQ_LEVEL_UP_19DB 0x06
+#define PS8802_DPEQ_LEVEL_UP_20DB 0x07
+#define PS8802_DPEQ_LEVEL_UP_21DB 0x08
+#define PS8802_DPEQ_LEVEL_UP_MASK 0x0F
+
+#define PS8802_P1_ADDR 0x0A
+#define PS8802_ADDR_CFG 0xB0
+#define PS8802_I2C_ADDR_FLAGS_ALT 0x50
 
 extern const struct usb_mux_driver ps8802_usb_mux_driver;
 
@@ -108,11 +108,11 @@ int ps8802_i2c_wake(const struct usb_mux *me);
 int ps8802_i2c_read(const struct usb_mux *me, int page, int offset, int *data);
 int ps8802_i2c_write(const struct usb_mux *me, int page, int offset, int data);
 int ps8802_i2c_write16(const struct usb_mux *me, int page, int offset,
-			int data);
+		       int data);
 int ps8802_i2c_field_update8(const struct usb_mux *me, int page, int offset,
 			     uint8_t field_mask, uint8_t set_value);
 int ps8802_i2c_field_update16(const struct usb_mux *me, int page, int offset,
-			     uint16_t field_mask, uint16_t set_value);
+			      uint16_t field_mask, uint16_t set_value);
 int ps8802_chg_i2c_addr(int i2c_port);
 
 #endif /* __CROS_EC_USB_RETIMER_PS8802_H */
diff --git a/driver/retimer/ps8811.c b/driver/retimer/ps8811.c
index 6a66248d38..aadcbc9f6c 100644
--- a/driver/retimer/ps8811.c
+++ b/driver/retimer/ps8811.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -15,9 +15,7 @@ int ps8811_i2c_read(const struct usb_mux *me, int page, int offset, int *data)
 {
 	int rv;
 
-	rv = i2c_read8(me->i2c_port,
-		       me->i2c_addr_flags + page,
-		       offset, data);
+	rv = i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset, data);
 
 	return rv;
 }
@@ -26,23 +24,18 @@ int ps8811_i2c_write(const struct usb_mux *me, int page, int offset, int data)
 {
 	int rv;
 
-	rv = i2c_write8(me->i2c_port,
-			me->i2c_addr_flags + page,
-			offset, data);
+	rv = i2c_write8(me->i2c_port, me->i2c_addr_flags + page, offset, data);
 
 	return rv;
 }
 
 int ps8811_i2c_field_update(const struct usb_mux *me, int page, int offset,
-			     uint8_t field_mask, uint8_t set_value)
+			    uint8_t field_mask, uint8_t set_value)
 {
 	int rv;
 
-	rv = i2c_field_update8(me->i2c_port,
-			       me->i2c_addr_flags + page,
-			       offset,
-			       field_mask,
-			       set_value);
+	rv = i2c_field_update8(me->i2c_port, me->i2c_addr_flags + page, offset,
+			       field_mask, set_value);
 
 	return rv;
 }
diff --git a/driver/retimer/ps8811.h b/driver/retimer/ps8811.h
index 5721f31eae..b834635215 100644
--- a/driver/retimer/ps8811.h
+++ b/driver/retimer/ps8811.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -20,172 +20,172 @@
  * PS8811 uses 7-bit I2C addresses 0x72 to 0x73 (ADDR=HH).
  * Page 0 = 0x72, Page 1 = 0x73.
  */
-#define PS8811_I2C_ADDR_FLAGS0	0x28
-#define PS8811_I2C_ADDR_FLAGS1	0x2A
-#define PS8811_I2C_ADDR_FLAGS2	0x70
-#define PS8811_I2C_ADDR_FLAGS3	0x72
+#define PS8811_I2C_ADDR_FLAGS0 0x28
+#define PS8811_I2C_ADDR_FLAGS1 0x2A
+#define PS8811_I2C_ADDR_FLAGS2 0x70
+#define PS8811_I2C_ADDR_FLAGS3 0x72
 
 /*
  * PAGE 1 Register Definitions
  */
-#define PS8811_REG_PAGE1			0x01
-
-#define PS8811_REG1_USB_AEQ_LEVEL		0x01
-#define PS8811_AEQ_PIN_LEVEL_UP_CONFIG_MASK	GENMASK(3, 0)
-#define PS8811_AEQ_PIN_LEVEL_UP_SHIFT		0
-#define PS8811_AEQ_PIN_LEVEL_UP_9DB		0x00
-#define PS8811_AEQ_PIN_LEVEL_UP_10P5DB		0x01
-#define PS8811_AEQ_PIN_LEVEL_UP_12DB		0x02
-#define PS8811_AEQ_PIN_LEVEL_UP_13DB		0x03
-#define PS8811_AEQ_PIN_LEVEL_UP_16DB		0x04
-#define PS8811_AEQ_PIN_LEVEL_UP_17DB		0x05
-#define PS8811_AEQ_PIN_LEVEL_UP_18DB		0x06
-#define PS8811_AEQ_PIN_LEVEL_UP_19DB		0x07
-#define PS8811_AEQ_PIN_LEVEL_UP_20DB		0x08
-#define PS8811_AEQ_PIN_LEVEL_UP_21DB		0x09
-#define PS8811_AEQ_PIN_LEVEL_UP_23DB		0x0A
-#define PS8811_AEQ_I2C_LEVEL_UP_CONFIG_MASK	GENMASK(7, 4)
-#define PS8811_AEQ_I2C_LEVEL_UP_SHIFT		4
-#define PS8811_AEQ_I2C_LEVEL_UP_9DB		0x00
-#define PS8811_AEQ_I2C_LEVEL_UP_10P5DB		0x01
-#define PS8811_AEQ_I2C_LEVEL_UP_12DB		0x02
-#define PS8811_AEQ_I2C_LEVEL_UP_13DB		0x03
-#define PS8811_AEQ_I2C_LEVEL_UP_16DB		0x04
-#define PS8811_AEQ_I2C_LEVEL_UP_17DB		0x05
-#define PS8811_AEQ_I2C_LEVEL_UP_18DB		0x06
-#define PS8811_AEQ_I2C_LEVEL_UP_19DB		0x07
-#define PS8811_AEQ_I2C_LEVEL_UP_20DB		0x08
-#define PS8811_AEQ_I2C_LEVEL_UP_21DB		0x09
-#define PS8811_AEQ_I2C_LEVEL_UP_23DB		0x0A
-
-#define PS8811_REG1_USB_ADE_CONFIG		0x02
-#define PS8811_AEQ_CONFIG_REG_ENABLE		BIT(0)
-#define PS8811_AEQ_ADAPTIVE_REG_ENABLE		BIT(1)
-#define PS8811_ADE_PIN_MID_LEVEL_CONFIG_MASK	GENMASK(7, 5)
-#define PS8811_ADE_PIN_MID_LEVEL_SHIFT		5
-#define PS8811_ADE_PIN_MID_LEVEL_0P5DB		0x00
-#define PS8811_ADE_PIN_MID_LEVEL_1P5DB		0x01
-#define PS8811_ADE_PIN_MID_LEVEL_2DB		0x02
-#define PS8811_ADE_PIN_MID_LEVEL_3DB		0x03
-#define PS8811_ADE_PIN_MID_LEVEL_3P5DB		0x04
-#define PS8811_ADE_PIN_MID_LEVEL_4P5DB		0x05
-#define PS8811_ADE_PIN_MID_LEVEL_6DB		0x06
-#define PS8811_ADE_PIN_MID_LEVEL_7P5DB		0x07
-#define PS8811_ADE_PIN_LOW_LEVEL_CONFIG_MASK	GENMASK(4, 2)
-#define PS8811_ADE_PIN_LOW_LEVEL_SHIFT		2
-#define PS8811_ADE_PIN_LOW_LEVEL_0P5DB		0x00
-#define PS8811_ADE_PIN_LOW_LEVEL_1P5DB		0x01
-#define PS8811_ADE_PIN_LOW_LEVEL_2DB		0x02
-#define PS8811_ADE_PIN_LOW_LEVEL_3DB		0x03
-#define PS8811_ADE_PIN_LOW_LEVEL_3P5DB		0x04
-#define PS8811_ADE_PIN_LOW_LEVEL_4P5DB		0x05
-#define PS8811_ADE_PIN_LOW_LEVEL_6DB		0x06
-#define PS8811_ADE_PIN_LOW_LEVEL_7P5DB		0x07
-
-#define PS8811_REG1_USB_BEQ_LEVEL		0x05
-#define PS8811_BEQ_PIN_LEVEL_UP_CONFIG_MASK	GENMASK(3, 0)
-#define PS8811_BEQ_PIN_LEVEL_UP_SHIFT		0
-#define PS8811_BEQ_PIN_LEVEL_UP_9DB		0x00
-#define PS8811_BEQ_PIN_LEVEL_UP_10P5DB		0x01
-#define PS8811_BEQ_PIN_LEVEL_UP_12DB		0x02
-#define PS8811_BEQ_PIN_LEVEL_UP_13DB		0x03
-#define PS8811_BEQ_PIN_LEVEL_UP_16DB		0x04
-#define PS8811_BEQ_PIN_LEVEL_UP_17DB		0x05
-#define PS8811_BEQ_PIN_LEVEL_UP_18DB		0x06
-#define PS8811_BEQ_PIN_LEVEL_UP_19DB		0x07
-#define PS8811_BEQ_PIN_LEVEL_UP_20DB		0x08
-#define PS8811_BEQ_PIN_LEVEL_UP_21DB		0x09
-#define PS8811_BEQ_PIN_LEVEL_UP_23DB		0x0A
-#define PS8811_BEQ_I2C_LEVEL_UP_CONFIG_MASK	GENMASK(7, 4)
-#define PS8811_BEQ_I2C_LEVEL_UP_SHIFT		4
-#define PS8811_BEQ_I2C_LEVEL_UP_9DB		0x00
-#define PS8811_BEQ_I2C_LEVEL_UP_10P5DB		0x01
-#define PS8811_BEQ_I2C_LEVEL_UP_12DB		0x02
-#define PS8811_BEQ_I2C_LEVEL_UP_13DB		0x03
-#define PS8811_BEQ_I2C_LEVEL_UP_16DB		0x04
-#define PS8811_BEQ_I2C_LEVEL_UP_17DB		0x05
-#define PS8811_BEQ_I2C_LEVEL_UP_18DB		0x06
-#define PS8811_BEQ_I2C_LEVEL_UP_19DB		0x07
-#define PS8811_BEQ_I2C_LEVEL_UP_20DB		0x08
-#define PS8811_BEQ_I2C_LEVEL_UP_21DB		0x09
-#define PS8811_BEQ_I2C_LEVEL_UP_23DB		0x0A
-
-#define PS8811_REG1_USB_BDE_CONFIG		0x06
-#define PS8811_BEQ_CONFIG_REG_ENABLE		BIT(0)
-#define PS8811_BEQ_ADAPTIVE_REG_ENABLE		BIT(1)
-#define PS8811_BDE_PIN_MID_LEVEL_CONFIG_MASK	GENMASK(7, 5)
-#define PS8811_BDE_PIN_MID_LEVEL_SHIFT		5
-#define PS8811_BDE_PIN_MID_LEVEL_0P5DB		0x00
-#define PS8811_BDE_PIN_MID_LEVEL_1P5DB		0x01
-#define PS8811_BDE_PIN_MID_LEVEL_2DB		0x02
-#define PS8811_BDE_PIN_MID_LEVEL_3DB		0x03
-#define PS8811_BDE_PIN_MID_LEVEL_3P5DB		0x04
-#define PS8811_BDE_PIN_MID_LEVEL_4P5DB		0x05
-#define PS8811_BDE_PIN_MID_LEVEL_6DB		0x06
-#define PS8811_BDE_PIN_MID_LEVEL_7P5DB		0x07
-#define PS8811_BDE_PIN_LOW_LEVEL_CONFIG_MASK	GENMASK(4, 2)
-#define PS8811_BDE_PIN_LOW_LEVEL_SHIFT		2
-#define PS8811_BDE_PIN_LOW_LEVEL_0P5DB		0x00
-#define PS8811_BDE_PIN_LOW_LEVEL_1P5DB		0x01
-#define PS8811_BDE_PIN_LOW_LEVEL_2DB		0x02
-#define PS8811_BDE_PIN_LOW_LEVEL_3DB		0x03
-#define PS8811_BDE_PIN_LOW_LEVEL_3P5DB		0x04
-#define PS8811_BDE_PIN_LOW_LEVEL_4P5DB		0x05
-#define PS8811_BDE_PIN_LOW_LEVEL_6DB		0x06
-#define PS8811_BDE_PIN_LOW_LEVEL_7P5DB		0x07
-
-#define PS8811_REG1_USB_CHAN_A_SWING		0x66
-#define PS8811_CHAN_A_SWING_MASK		GENMASK(6, 4)
-#define PS8811_CHAN_A_SWING_SHIFT		4
-
-#define PS8811_REG1_50OHM_ADJUST_CHAN_B	0x73
-#define PS8811_50OHM_ADJUST_CHAN_B_CONFIG_MASK	GENMASK(3, 1)
-#define PS8811_50OHM_ADJUST_CHAN_B_SHIFT		1
-#define PS8811_50OHM_ADJUST_CHAN_B_DEFAULT	0x00
-#define PS8811_50OHM_ADJUST_CHAN_B_MINUS_6PCT	0x01
-#define PS8811_50OHM_ADJUST_CHAN_B_MINUS_9PCT	0x02
-#define PS8811_50OHM_ADJUST_CHAN_B_MINUS_14PCT	0x03
-#define PS8811_50OHM_ADJUST_CHAN_B_PLUS_7PCT	0x04
-#define PS8811_50OHM_ADJUST_CHAN_B_PLUS_11PCT	0x05
-#define PS8811_50OHM_ADJUST_CHAN_B_PLUS_20PCT	0x06
-
-#define PS8811_BDE_PIN_MID_LEVEL_1P5DB		0x01
-#define PS8811_BDE_PIN_MID_LEVEL_2DB		0x02
-#define PS8811_BDE_PIN_MID_LEVEL_3DB		0x03
-#define PS8811_BDE_PIN_MID_LEVEL_3P5DB		0x04
-#define PS8811_BDE_PIN_MID_LEVEL_4P5DB		0x05
-#define PS8811_BDE_PIN_MID_LEVEL_6DB		0x06
-#define PS8811_BDE_PIN_MID_LEVEL_7P5DB		0x07
-
-#define PS8811_REG1_USB_CHAN_B_SWING		0xA4
-#define PS8811_CHAN_B_SWING_MASK		GENMASK(2, 0)
-#define PS8811_CHAN_B_SWING_SHIFT		0
+#define PS8811_REG_PAGE1 0x01
+
+#define PS8811_REG1_USB_AEQ_LEVEL 0x01
+#define PS8811_AEQ_PIN_LEVEL_UP_CONFIG_MASK GENMASK(3, 0)
+#define PS8811_AEQ_PIN_LEVEL_UP_SHIFT 0
+#define PS8811_AEQ_PIN_LEVEL_UP_9DB 0x00
+#define PS8811_AEQ_PIN_LEVEL_UP_10P5DB 0x01
+#define PS8811_AEQ_PIN_LEVEL_UP_12DB 0x02
+#define PS8811_AEQ_PIN_LEVEL_UP_13DB 0x03
+#define PS8811_AEQ_PIN_LEVEL_UP_16DB 0x04
+#define PS8811_AEQ_PIN_LEVEL_UP_17DB 0x05
+#define PS8811_AEQ_PIN_LEVEL_UP_18DB 0x06
+#define PS8811_AEQ_PIN_LEVEL_UP_19DB 0x07
+#define PS8811_AEQ_PIN_LEVEL_UP_20DB 0x08
+#define PS8811_AEQ_PIN_LEVEL_UP_21DB 0x09
+#define PS8811_AEQ_PIN_LEVEL_UP_23DB 0x0A
+#define PS8811_AEQ_I2C_LEVEL_UP_CONFIG_MASK GENMASK(7, 4)
+#define PS8811_AEQ_I2C_LEVEL_UP_SHIFT 4
+#define PS8811_AEQ_I2C_LEVEL_UP_9DB 0x00
+#define PS8811_AEQ_I2C_LEVEL_UP_10P5DB 0x01
+#define PS8811_AEQ_I2C_LEVEL_UP_12DB 0x02
+#define PS8811_AEQ_I2C_LEVEL_UP_13DB 0x03
+#define PS8811_AEQ_I2C_LEVEL_UP_16DB 0x04
+#define PS8811_AEQ_I2C_LEVEL_UP_17DB 0x05
+#define PS8811_AEQ_I2C_LEVEL_UP_18DB 0x06
+#define PS8811_AEQ_I2C_LEVEL_UP_19DB 0x07
+#define PS8811_AEQ_I2C_LEVEL_UP_20DB 0x08
+#define PS8811_AEQ_I2C_LEVEL_UP_21DB 0x09
+#define PS8811_AEQ_I2C_LEVEL_UP_23DB 0x0A
+
+#define PS8811_REG1_USB_ADE_CONFIG 0x02
+#define PS8811_AEQ_CONFIG_REG_ENABLE BIT(0)
+#define PS8811_AEQ_ADAPTIVE_REG_ENABLE BIT(1)
+#define PS8811_ADE_PIN_MID_LEVEL_CONFIG_MASK GENMASK(7, 5)
+#define PS8811_ADE_PIN_MID_LEVEL_SHIFT 5
+#define PS8811_ADE_PIN_MID_LEVEL_0P5DB 0x00
+#define PS8811_ADE_PIN_MID_LEVEL_1P5DB 0x01
+#define PS8811_ADE_PIN_MID_LEVEL_2DB 0x02
+#define PS8811_ADE_PIN_MID_LEVEL_3DB 0x03
+#define PS8811_ADE_PIN_MID_LEVEL_3P5DB 0x04
+#define PS8811_ADE_PIN_MID_LEVEL_4P5DB 0x05
+#define PS8811_ADE_PIN_MID_LEVEL_6DB 0x06
+#define PS8811_ADE_PIN_MID_LEVEL_7P5DB 0x07
+#define PS8811_ADE_PIN_LOW_LEVEL_CONFIG_MASK GENMASK(4, 2)
+#define PS8811_ADE_PIN_LOW_LEVEL_SHIFT 2
+#define PS8811_ADE_PIN_LOW_LEVEL_0P5DB 0x00
+#define PS8811_ADE_PIN_LOW_LEVEL_1P5DB 0x01
+#define PS8811_ADE_PIN_LOW_LEVEL_2DB 0x02
+#define PS8811_ADE_PIN_LOW_LEVEL_3DB 0x03
+#define PS8811_ADE_PIN_LOW_LEVEL_3P5DB 0x04
+#define PS8811_ADE_PIN_LOW_LEVEL_4P5DB 0x05
+#define PS8811_ADE_PIN_LOW_LEVEL_6DB 0x06
+#define PS8811_ADE_PIN_LOW_LEVEL_7P5DB 0x07
+
+#define PS8811_REG1_USB_BEQ_LEVEL 0x05
+#define PS8811_BEQ_PIN_LEVEL_UP_CONFIG_MASK GENMASK(3, 0)
+#define PS8811_BEQ_PIN_LEVEL_UP_SHIFT 0
+#define PS8811_BEQ_PIN_LEVEL_UP_9DB 0x00
+#define PS8811_BEQ_PIN_LEVEL_UP_10P5DB 0x01
+#define PS8811_BEQ_PIN_LEVEL_UP_12DB 0x02
+#define PS8811_BEQ_PIN_LEVEL_UP_13DB 0x03
+#define PS8811_BEQ_PIN_LEVEL_UP_16DB 0x04
+#define PS8811_BEQ_PIN_LEVEL_UP_17DB 0x05
+#define PS8811_BEQ_PIN_LEVEL_UP_18DB 0x06
+#define PS8811_BEQ_PIN_LEVEL_UP_19DB 0x07
+#define PS8811_BEQ_PIN_LEVEL_UP_20DB 0x08
+#define PS8811_BEQ_PIN_LEVEL_UP_21DB 0x09
+#define PS8811_BEQ_PIN_LEVEL_UP_23DB 0x0A
+#define PS8811_BEQ_I2C_LEVEL_UP_CONFIG_MASK GENMASK(7, 4)
+#define PS8811_BEQ_I2C_LEVEL_UP_SHIFT 4
+#define PS8811_BEQ_I2C_LEVEL_UP_9DB 0x00
+#define PS8811_BEQ_I2C_LEVEL_UP_10P5DB 0x01
+#define PS8811_BEQ_I2C_LEVEL_UP_12DB 0x02
+#define PS8811_BEQ_I2C_LEVEL_UP_13DB 0x03
+#define PS8811_BEQ_I2C_LEVEL_UP_16DB 0x04
+#define PS8811_BEQ_I2C_LEVEL_UP_17DB 0x05
+#define PS8811_BEQ_I2C_LEVEL_UP_18DB 0x06
+#define PS8811_BEQ_I2C_LEVEL_UP_19DB 0x07
+#define PS8811_BEQ_I2C_LEVEL_UP_20DB 0x08
+#define PS8811_BEQ_I2C_LEVEL_UP_21DB 0x09
+#define PS8811_BEQ_I2C_LEVEL_UP_23DB 0x0A
+
+#define PS8811_REG1_USB_BDE_CONFIG 0x06
+#define PS8811_BEQ_CONFIG_REG_ENABLE BIT(0)
+#define PS8811_BEQ_ADAPTIVE_REG_ENABLE BIT(1)
+#define PS8811_BDE_PIN_MID_LEVEL_CONFIG_MASK GENMASK(7, 5)
+#define PS8811_BDE_PIN_MID_LEVEL_SHIFT 5
+#define PS8811_BDE_PIN_MID_LEVEL_0P5DB 0x00
+#define PS8811_BDE_PIN_MID_LEVEL_1P5DB 0x01
+#define PS8811_BDE_PIN_MID_LEVEL_2DB 0x02
+#define PS8811_BDE_PIN_MID_LEVEL_3DB 0x03
+#define PS8811_BDE_PIN_MID_LEVEL_3P5DB 0x04
+#define PS8811_BDE_PIN_MID_LEVEL_4P5DB 0x05
+#define PS8811_BDE_PIN_MID_LEVEL_6DB 0x06
+#define PS8811_BDE_PIN_MID_LEVEL_7P5DB 0x07
+#define PS8811_BDE_PIN_LOW_LEVEL_CONFIG_MASK GENMASK(4, 2)
+#define PS8811_BDE_PIN_LOW_LEVEL_SHIFT 2
+#define PS8811_BDE_PIN_LOW_LEVEL_0P5DB 0x00
+#define PS8811_BDE_PIN_LOW_LEVEL_1P5DB 0x01
+#define PS8811_BDE_PIN_LOW_LEVEL_2DB 0x02
+#define PS8811_BDE_PIN_LOW_LEVEL_3DB 0x03
+#define PS8811_BDE_PIN_LOW_LEVEL_3P5DB 0x04
+#define PS8811_BDE_PIN_LOW_LEVEL_4P5DB 0x05
+#define PS8811_BDE_PIN_LOW_LEVEL_6DB 0x06
+#define PS8811_BDE_PIN_LOW_LEVEL_7P5DB 0x07
+
+#define PS8811_REG1_USB_CHAN_A_SWING 0x66
+#define PS8811_CHAN_A_SWING_MASK GENMASK(6, 4)
+#define PS8811_CHAN_A_SWING_SHIFT 4
+
+#define PS8811_REG1_50OHM_ADJUST_CHAN_B 0x73
+#define PS8811_50OHM_ADJUST_CHAN_B_CONFIG_MASK GENMASK(3, 1)
+#define PS8811_50OHM_ADJUST_CHAN_B_SHIFT 1
+#define PS8811_50OHM_ADJUST_CHAN_B_DEFAULT 0x00
+#define PS8811_50OHM_ADJUST_CHAN_B_MINUS_6PCT 0x01
+#define PS8811_50OHM_ADJUST_CHAN_B_MINUS_9PCT 0x02
+#define PS8811_50OHM_ADJUST_CHAN_B_MINUS_14PCT 0x03
+#define PS8811_50OHM_ADJUST_CHAN_B_PLUS_7PCT 0x04
+#define PS8811_50OHM_ADJUST_CHAN_B_PLUS_11PCT 0x05
+#define PS8811_50OHM_ADJUST_CHAN_B_PLUS_20PCT 0x06
+
+#define PS8811_BDE_PIN_MID_LEVEL_1P5DB 0x01
+#define PS8811_BDE_PIN_MID_LEVEL_2DB 0x02
+#define PS8811_BDE_PIN_MID_LEVEL_3DB 0x03
+#define PS8811_BDE_PIN_MID_LEVEL_3P5DB 0x04
+#define PS8811_BDE_PIN_MID_LEVEL_4P5DB 0x05
+#define PS8811_BDE_PIN_MID_LEVEL_6DB 0x06
+#define PS8811_BDE_PIN_MID_LEVEL_7P5DB 0x07
+
+#define PS8811_REG1_USB_CHAN_B_SWING 0xA4
+#define PS8811_CHAN_B_SWING_MASK GENMASK(2, 0)
+#define PS8811_CHAN_B_SWING_SHIFT 0
 
 /* De-emphasis -2.2 dB, Pre-shoot 1.2 dB */
-#define PS8811_CHAN_B_DE_2_2_PS_1_2_LSB		0x1
-#define PS8811_CHAN_B_DE_2_2_PS_1_2_MSB		0x13
+#define PS8811_CHAN_B_DE_2_2_PS_1_2_LSB 0x1
+#define PS8811_CHAN_B_DE_2_2_PS_1_2_MSB 0x13
 
 /* De-emphasis -3.5 dB, Pre-shoot 0 dB */
-#define PS8811_CHAN_B_DE_3_5_PS_0_LSB		0x0
-#define PS8811_CHAN_B_DE_3_5_PS_0_MSB		0x5
+#define PS8811_CHAN_B_DE_3_5_PS_0_LSB 0x0
+#define PS8811_CHAN_B_DE_3_5_PS_0_MSB 0x5
 
 /* De-emphasis -4.5 dB, Pre-shoot 0 dB */
-#define PS8811_CHAN_B_DE_4_5_PS_0_LSB		0x0
-#define PS8811_CHAN_B_DE_4_5_PS_0_MSB		0x6
+#define PS8811_CHAN_B_DE_4_5_PS_0_LSB 0x0
+#define PS8811_CHAN_B_DE_4_5_PS_0_MSB 0x6
 
 /* De-emphasis -6 dB, Pre-shoot 1.5 dB */
-#define PS8811_CHAN_B_DE_6_PS_1_5_LSB		0x2
-#define PS8811_CHAN_B_DE_6_PS_1_5_MSB		0x16
+#define PS8811_CHAN_B_DE_6_PS_1_5_LSB 0x2
+#define PS8811_CHAN_B_DE_6_PS_1_5_MSB 0x16
 
 /* De-emphasis -6 dB, Pre-shoot 3 dB */
-#define PS8811_CHAN_B_DE_6_PS_3_LSB		0x4
-#define PS8811_CHAN_B_DE_6_PS_3_MSB		0x16
+#define PS8811_CHAN_B_DE_6_PS_3_LSB 0x4
+#define PS8811_CHAN_B_DE_6_PS_3_MSB 0x16
 
-#define PS8811_REG1_USB_CHAN_B_DE_PS_LSB	0xA5
-#define PS8811_CHAN_B_DE_PS_LSB_MASK		GENMASK(2, 0)
+#define PS8811_REG1_USB_CHAN_B_DE_PS_LSB 0xA5
+#define PS8811_CHAN_B_DE_PS_LSB_MASK GENMASK(2, 0)
 
-#define PS8811_REG1_USB_CHAN_B_DE_PS_MSB	0xA6
-#define PS8811_CHAN_B_DE_PS_MSB_MASK		GENMASK(5, 0)
+#define PS8811_REG1_USB_CHAN_B_DE_PS_MSB 0xA6
+#define PS8811_CHAN_B_DE_PS_MSB_MASK GENMASK(5, 0)
 
 int ps8811_i2c_read(const struct usb_mux *me, int page, int offset, int *data);
 int ps8811_i2c_write(const struct usb_mux *me, int page, int offset, int data);
diff --git a/driver/retimer/ps8818.c b/driver/retimer/ps8818.c
index 2f8e353099..dff1b33a64 100644
--- a/driver/retimer/ps8818.c
+++ b/driver/retimer/ps8818.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,10 +8,10 @@
 #include "chipset.h"
 #include "common.h"
 #include "console.h"
+#include "driver/retimer/ps8818_public.h"
 #include "gpio.h"
 #include "i2c.h"
 #include "ioexpander.h"
-#include "ps8818.h"
 #include "usb_mux.h"
 
 #define PS8818_DEBUG 0
@@ -20,15 +20,12 @@ int ps8818_i2c_read(const struct usb_mux *me, int page, int offset, int *data)
 {
 	int rv;
 
-	rv = i2c_read8(me->i2c_port,
-		       me->i2c_addr_flags + page,
-		       offset, data);
+	rv = i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset, data);
 
 	if (PS8818_DEBUG)
 		ccprintf("%s(%d:0x%02X, 0x%02X) =>0x%02X\n", __func__,
-			 me->usb_port,
-			 me->i2c_addr_flags + page,
-			 offset, *data);
+			 me->usb_port, me->i2c_addr_flags + page, offset,
+			 *data);
 
 	return rv;
 }
@@ -39,26 +36,19 @@ int ps8818_i2c_write(const struct usb_mux *me, int page, int offset, int data)
 	int pre_val, post_val;
 
 	if (PS8818_DEBUG)
-		i2c_read8(me->i2c_port,
-			me->i2c_addr_flags + page,
-			offset, &pre_val);
+		i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset,
+			  &pre_val);
 
-	rv = i2c_write8(me->i2c_port,
-			me->i2c_addr_flags + page,
-			offset, data);
+	rv = i2c_write8(me->i2c_port, me->i2c_addr_flags + page, offset, data);
 
 	if (PS8818_DEBUG) {
-		i2c_read8(me->i2c_port,
-			me->i2c_addr_flags + page,
-			offset, &post_val);
+		i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset,
+			  &post_val);
 
 		ccprintf("%s(%d:0x%02X, 0x%02X, 0x%02X) "
-			"0x%02X=>0x%02X\n",
-			 __func__,
-			 me->usb_port,
-			 me->i2c_addr_flags + page,
-			 offset, data,
-			 pre_val, post_val);
+			 "0x%02X=>0x%02X\n",
+			 __func__, me->usb_port, me->i2c_addr_flags + page,
+			 offset, data, pre_val, post_val);
 	}
 
 	return rv;
@@ -71,28 +61,20 @@ int ps8818_i2c_field_update8(const struct usb_mux *me, int page, int offset,
 	int pre_val, post_val;
 
 	if (PS8818_DEBUG)
-		i2c_read8(me->i2c_port,
-			me->i2c_addr_flags + page,
-			offset, &pre_val);
+		i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset,
+			  &pre_val);
 
-	rv = i2c_field_update8(me->i2c_port,
-			       me->i2c_addr_flags + page,
-			       offset,
-			       field_mask,
-			       set_value);
+	rv = i2c_field_update8(me->i2c_port, me->i2c_addr_flags + page, offset,
+			       field_mask, set_value);
 
 	if (PS8818_DEBUG) {
-		i2c_read8(me->i2c_port,
-			me->i2c_addr_flags + page,
-			offset, &post_val);
+		i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset,
+			  &post_val);
 
 		ccprintf("%s(%d:0x%02X, 0x%02X, 0x%02X, 0x%02X) "
 			 "0x%02X=>0x%02X\n",
-			 __func__,
-			 me->usb_port,
-			 me->i2c_addr_flags + page,
-			 offset, field_mask, set_value,
-			 pre_val, post_val);
+			 __func__, me->usb_port, me->i2c_addr_flags + page,
+			 offset, field_mask, set_value, pre_val, post_val);
 	}
 
 	return rv;
@@ -107,17 +89,21 @@ static int ps8818_set_mux(const struct usb_mux *me, mux_state_t mux_state,
 	/* This driver does not use host command ACKs */
 	*ack_required = false;
 
+	/* This driver treats safe mode as none */
+	if (mux_state == USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
+
 	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
-		return (mux_state == USB_PD_MUX_NONE) ? EC_SUCCESS
-						      : EC_ERROR_NOT_POWERED;
+		return (mux_state == USB_PD_MUX_NONE) ? EC_SUCCESS :
+							EC_ERROR_NOT_POWERED;
 
 	if (PS8818_DEBUG)
-		ccprintf("%s(%d, 0x%02X) %s %s %s\n",
-			 __func__, me->usb_port, mux_state,
-			 (mux_state & USB_PD_MUX_USB_ENABLED)	? "USB" : "",
-			 (mux_state & USB_PD_MUX_DP_ENABLED)	? "DP" : "",
-			 (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-								? "FLIP" : "");
+		ccprintf("%s(%d, 0x%02X) %s %s %s\n", __func__, me->usb_port,
+			 mux_state,
+			 (mux_state & USB_PD_MUX_USB_ENABLED) ? "USB" : "",
+			 (mux_state & USB_PD_MUX_DP_ENABLED) ? "DP" : "",
+			 (mux_state & USB_PD_MUX_POLARITY_INVERTED) ? "FLIP" :
+								      "");
 
 	/* Set the mode */
 	if (mux_state & USB_PD_MUX_USB_ENABLED)
@@ -125,11 +111,8 @@ static int ps8818_set_mux(const struct usb_mux *me, mux_state_t mux_state,
 	if (mux_state & USB_PD_MUX_DP_ENABLED)
 		val |= PS8818_MODE_DP_ENABLE;
 
-	rv = ps8818_i2c_field_update8(me,
-				PS8818_REG_PAGE0,
-				PS8818_REG0_MODE,
-				PS8818_MODE_NON_RESERVED_MASK,
-				val);
+	rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE0, PS8818_REG0_MODE,
+				      PS8818_MODE_NON_RESERVED_MASK, val);
 	if (rv)
 		return rv;
 
@@ -138,11 +121,8 @@ static int ps8818_set_mux(const struct usb_mux *me, mux_state_t mux_state,
 	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
 		val |= PS8818_FLIP_CONFIG;
 
-	rv = ps8818_i2c_field_update8(me,
-				PS8818_REG_PAGE0,
-				PS8818_REG0_FLIP,
-				PS8818_FLIP_NON_RESERVED_MASK,
-				val);
+	rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE0, PS8818_REG0_FLIP,
+				      PS8818_FLIP_NON_RESERVED_MASK, val);
 	if (rv)
 		return rv;
 
@@ -151,11 +131,9 @@ static int ps8818_set_mux(const struct usb_mux *me, mux_state_t mux_state,
 	if (mux_state & USB_PD_MUX_DP_ENABLED)
 		val |= PS8818_DPHPD_PLUGGED;
 
-	rv = ps8818_i2c_field_update8(me,
-				PS8818_REG_PAGE0,
-				PS8818_REG0_DPHPD_CONFIG,
-				PS8818_DPHPD_NON_RESERVED_MASK,
-				val);
+	rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE0,
+				      PS8818_REG0_DPHPD_CONFIG,
+				      PS8818_DPHPD_NON_RESERVED_MASK, val);
 
 	return rv;
 }
diff --git a/driver/retimer/ps8818.h b/driver/retimer/ps8818.h
deleted file mode 100644
index b56df4b411..0000000000
--- a/driver/retimer/ps8818.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * PS8818 retimer.
- */
-#include "usb_mux.h"
-
-#ifndef __CROS_EC_USB_RETIMER_PS8818_H
-#define __CROS_EC_USB_RETIMER_PS8818_H
-
-#define PS8818_I2C_ADDR_FLAGS	0x28
-
-/*
- * PAGE 0 Register Definitions
- */
-#define PS8818_REG_PAGE0	0x00
-
-#define PS8818_REG0_FLIP		0x00
-#define PS8818_FLIP_CONFIG			BIT(7)
-#define PS8818_FLIP_NON_RESERVED_MASK		0xE0
-
-#define PS8818_REG0_MODE		0x01
-#define PS8818_MODE_DP_ENABLE			BIT(7)
-#define PS8818_MODE_USB_ENABLE			BIT(6)
-#define PS8818_MODE_NON_RESERVED_MASK		0xC0
-
-#define PS8818_REG0_DPHPD_CONFIG	0x02
-#define PS8818_DPHPD_CONFIG_INHPD_DISABLE	BIT(7)
-#define PS8818_DPHPD_PLUGGED			BIT(6)
-#define PS8818_DPHPD_NON_RESERVED_MASK		0xFC
-
-/*
- * PAGE 1 Register Definitions
- */
-#define PS8818_REG_PAGE1	0x01
-
-#define PS8818_REG1_APTX1EQ_10G_LEVEL	0x00
-#define PS8818_REG1_APTX2EQ_10G_LEVEL	0x02
-#define PS8818_REG1_CRX1EQ_10G_LEVEL	0x08
-#define PS8818_REG1_CRX2EQ_10G_LEVEL	0x0A
-#define PS8818_REG1_APRX1_DE_LEVEL	0x0C
-#define PS8818_REG1_APTX1EQ_5G_LEVEL	0x70
-#define PS8818_REG1_APTX2EQ_5G_LEVEL	0x72
-#define PS8818_REG1_CRX1EQ_5G_LEVEL	0x78
-#define PS8818_REG1_CRX2EQ_5G_LEVEL	0x7A
-#define PS8818_EQ_LEVEL_UP_9DB			(0)
-#define PS8818_EQ_LEVEL_UP_10DB			(1)
-#define PS8818_EQ_LEVEL_UP_12DB			(2)
-#define PS8818_EQ_LEVEL_UP_13DB			(3)
-#define PS8818_EQ_LEVEL_UP_16DB			(4)
-#define PS8818_EQ_LEVEL_UP_17DB			(5)
-#define PS8818_EQ_LEVEL_UP_18DB			(6)
-#define PS8818_EQ_LEVEL_UP_19DB			(7)
-#define PS8818_EQ_LEVEL_UP_20DB			(8)
-#define PS8818_EQ_LEVEL_UP_21DB			(9)
-#define PS8818_EQ_LEVEL_UP_MASK			(0x0F)
-
-#define PS8818_REG1_RX_PHY		0x6D
-#define PS8818_RX_INPUT_TERM_112_OHM		(0 << 6)
-#define PS8818_RX_INPUT_TERM_104_OHM		(1 << 6)
-#define PS8818_RX_INPUT_TERM_96_OHM		(2 << 6)
-#define PS8818_RX_INPUT_TERM_85_OHM		(3 << 6)
-#define PS8818_RX_INPUT_TERM_MASK		(3 << 6)
-
-#define PS8818_REG1_DPEQ_LEVEL		0xB6
-#define PS8818_DPEQ_LEVEL_UP_9DB		(0 << 3)
-#define PS8818_DPEQ_LEVEL_UP_10DB		(1 << 3)
-#define PS8818_DPEQ_LEVEL_UP_12DB		(2 << 3)
-#define PS8818_DPEQ_LEVEL_UP_13DB		(3 << 3)
-#define PS8818_DPEQ_LEVEL_UP_16DB		(4 << 3)
-#define PS8818_DPEQ_LEVEL_UP_17DB		(5 << 3)
-#define PS8818_DPEQ_LEVEL_UP_18DB		(6 << 3)
-#define PS8818_DPEQ_LEVEL_UP_19DB		(7 << 3)
-#define PS8818_DPEQ_LEVEL_UP_20DB		(8 << 3)
-#define PS8818_DPEQ_LEVEL_UP_21DB		(9 << 3)
-#define PS8818_DPEQ_LEVEL_UP_MASK		(0x0F << 3)
-
-/*
- * PAGE 2 Register Definitions
- */
-#define PS8818_REG_PAGE2	0x02
-
-#define PS8818_REG2_TX_STATUS		0x42
-#define PS8818_REG2_RX_STATUS		0x46
-#define PS8818_STATUS_NORMAL_OPERATION		BIT(7)
-#define PS8818_STATUS_10_GBPS			BIT(5)
-
-extern const struct usb_mux_driver ps8818_usb_retimer_driver;
-
-int ps8818_i2c_read(const struct usb_mux *me,
-		    int page, int offset, int *data);
-int ps8818_i2c_write(const struct usb_mux *me,
-		     int page, int offset, int data);
-int ps8818_i2c_field_update8(const struct usb_mux *me,
-			     int page, int offset,
-			     uint8_t field_mask, uint8_t set_value);
-
-#endif /* __CROS_EC_USB_RETIMER_PS8818_H */
diff --git a/driver/retimer/tdp142.c b/driver/retimer/tdp142.c
index e1632150d0..fb5149da63 100644
--- a/driver/retimer/tdp142.c
+++ b/driver/retimer/tdp142.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -12,18 +12,12 @@
 
 static enum ec_error_list tdp142_write(int offset, int data)
 {
-	return i2c_write8(TDP142_I2C_PORT,
-			  TDP142_I2C_ADDR,
-			  offset, data);
-
+	return i2c_write8(TDP142_I2C_PORT, TDP142_I2C_ADDR, offset, data);
 }
 
 static enum ec_error_list tdp142_read(int offset, int *regval)
 {
-	return i2c_read8(TDP142_I2C_PORT,
-			 TDP142_I2C_ADDR,
-			 offset, regval);
-
+	return i2c_read8(TDP142_I2C_PORT, TDP142_I2C_ADDR, offset, regval);
 }
 
 enum ec_error_list tdp142_set_ctlsel(enum tdp142_ctlsel selection)
diff --git a/driver/retimer/tdp142.h b/driver/retimer/tdp142.h
index 8346a233a5..abf0e3588c 100644
--- a/driver/retimer/tdp142.h
+++ b/driver/retimer/tdp142.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -20,11 +20,11 @@
 #define TDP142_I2C_ADDR3 0x0F
 
 /* Registers */
-#define TDP142_REG_GENERAL		0x0A
-#define TDP142_GENERAL_CTLSEL		GENMASK(1, 0)
-#define TDP142_GENERAL_HPDIN_OVRRIDE	BIT(3)
-#define TDP142_GENERAL_EQ_OVERRIDE	BIT(4)
-#define TDP142_GENERAL_SWAP_HPDIN	BIT(5)
+#define TDP142_REG_GENERAL 0x0A
+#define TDP142_GENERAL_CTLSEL GENMASK(1, 0)
+#define TDP142_GENERAL_HPDIN_OVRRIDE BIT(3)
+#define TDP142_GENERAL_EQ_OVERRIDE BIT(4)
+#define TDP142_GENERAL_SWAP_HPDIN BIT(5)
 
 enum tdp142_ctlsel {
 	TDP142_CTLSEL_SHUTDOWN,
diff --git a/driver/retimer/tusb544.c b/driver/retimer/tusb544.c
index 9de543fd42..c2d617c3be 100644
--- a/driver/retimer/tusb544.c
+++ b/driver/retimer/tusb544.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,28 +10,21 @@
 
 static int tusb544_write(const struct usb_mux *me, int offset, int data)
 {
-	return i2c_write8(me->i2c_port,
-			  me->i2c_addr_flags,
-			  offset, data);
+	return i2c_write8(me->i2c_port, me->i2c_addr_flags, offset, data);
 }
 
 static int tusb544_read(const struct usb_mux *me, int offset, int *data)
 {
-	return i2c_read8(me->i2c_port,
-			 me->i2c_addr_flags,
-			 offset, data);
+	return i2c_read8(me->i2c_port, me->i2c_addr_flags, offset, data);
 }
 
 int tusb544_i2c_field_update8(const struct usb_mux *me, int offset,
-			     uint8_t field_mask, uint8_t set_value)
+			      uint8_t field_mask, uint8_t set_value)
 {
 	int rv;
 
-	rv = i2c_field_update8(me->i2c_port,
-			       me->i2c_addr_flags,
-			       offset,
-			       field_mask,
-			       set_value);
+	rv = i2c_field_update8(me->i2c_port, me->i2c_addr_flags, offset,
+			       field_mask, set_value);
 
 	return rv;
 }
@@ -67,6 +60,10 @@ static int tusb544_set_mux(const struct usb_mux *me, mux_state_t mux_state,
 	/* This driver does not use host command ACKs */
 	*ack_required = false;
 
+	/* This driver treats safe mode as none */
+	if (mux_state == USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
+
 	if (mux_state == USB_PD_MUX_NONE)
 		return tusb544_enter_low_power_mode(me);
 
diff --git a/driver/retimer/tusb544.h b/driver/retimer/tusb544.h
index e1599c78ca..9fe74c5299 100644
--- a/driver/retimer/tusb544.h
+++ b/driver/retimer/tusb544.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -9,55 +9,54 @@
 #ifndef __CROS_EC_USB_REDRIVER_TUSB544_H
 #define __CROS_EC_USB_REDRIVER_TUSB544_H
 
-
 #define TUSB544_I2C_ADDR_FLAGS0 0x44
 
-#define TUSB544_REG_GENERAL4	0x0A
-#define TUSB544_GEN4_CTL_SEL		GENMASK(1, 0)
-#define TUSB544_GEN4_FLIP_SEL		BIT(2)
-#define TUSB544_GEN4_HPDIN		BIT(3)
-#define TUSB544_GEN4_EQ_OVRD		BIT(4)
-#define TUSB544_GEN4_SWAP_SEL		BIT(5)
+#define TUSB544_REG_GENERAL4 0x0A
+#define TUSB544_GEN4_CTL_SEL GENMASK(1, 0)
+#define TUSB544_GEN4_FLIP_SEL BIT(2)
+#define TUSB544_GEN4_HPDIN BIT(3)
+#define TUSB544_GEN4_EQ_OVRD BIT(4)
+#define TUSB544_GEN4_SWAP_SEL BIT(5)
 
-#define TUSB544_REG_DISPLAYPORT_1	0x10
-#define TUSB544_REG_DISPLAYPORT_2	0x11
-#define TUSB544_REG_USB3_1_1	0x20
-#define TUSB544_REG_USB3_1_2	0x21
-#define TUSB544_EQ_RX_DFP_MINUS14_UFP_MINUS33		(0)
-#define TUSB544_EQ_RX_DFP_04_UFP_MINUS15		(1)
-#define TUSB544_EQ_RX_DFP_17_UFP_0		(2)
-#define TUSB544_EQ_RX_DFP_32_UFP_14		(3)
-#define TUSB544_EQ_RX_DFP_41_UFP_24		(4)
-#define TUSB544_EQ_RX_DFP_52_UFP_35		(5)
-#define TUSB544_EQ_RX_DFP_61_UFP_43		(6)
-#define TUSB544_EQ_RX_DFP_69_UFP_52		(7)
-#define TUSB544_EQ_RX_DFP_77_UFP_60		(8)
-#define TUSB544_EQ_RX_DFP_83_UFP_66		(9)
-#define TUSB544_EQ_RX_DFP_88_UFP_72		(10)
-#define TUSB544_EQ_RX_DFP_94_UFP_77		(11)
-#define TUSB544_EQ_RX_DFP_98_UFP_81		(12)
-#define TUSB544_EQ_RX_DFP_103_UFP_86		(13)
-#define TUSB544_EQ_RX_DFP_106_UFP_90		(14)
-#define TUSB544_EQ_RX_DFP_110_UFP_94		(15)
-#define TUSB544_EQ_RX_MASK		(0x0F)
+#define TUSB544_REG_DISPLAYPORT_1 0x10
+#define TUSB544_REG_DISPLAYPORT_2 0x11
+#define TUSB544_REG_USB3_1_1 0x20
+#define TUSB544_REG_USB3_1_2 0x21
+#define TUSB544_EQ_RX_DFP_MINUS14_UFP_MINUS33 (0)
+#define TUSB544_EQ_RX_DFP_04_UFP_MINUS15 (1)
+#define TUSB544_EQ_RX_DFP_17_UFP_0 (2)
+#define TUSB544_EQ_RX_DFP_32_UFP_14 (3)
+#define TUSB544_EQ_RX_DFP_41_UFP_24 (4)
+#define TUSB544_EQ_RX_DFP_52_UFP_35 (5)
+#define TUSB544_EQ_RX_DFP_61_UFP_43 (6)
+#define TUSB544_EQ_RX_DFP_69_UFP_52 (7)
+#define TUSB544_EQ_RX_DFP_77_UFP_60 (8)
+#define TUSB544_EQ_RX_DFP_83_UFP_66 (9)
+#define TUSB544_EQ_RX_DFP_88_UFP_72 (10)
+#define TUSB544_EQ_RX_DFP_94_UFP_77 (11)
+#define TUSB544_EQ_RX_DFP_98_UFP_81 (12)
+#define TUSB544_EQ_RX_DFP_103_UFP_86 (13)
+#define TUSB544_EQ_RX_DFP_106_UFP_90 (14)
+#define TUSB544_EQ_RX_DFP_110_UFP_94 (15)
+#define TUSB544_EQ_RX_MASK (0x0F)
 
-#define TUSB544_EQ_TX_DFP_MINUS14_UFP_MINUS33		(0 << 4)
-#define TUSB544_EQ_TX_DFP_04_UFP_MINUS15		(1 << 4)
-#define TUSB544_EQ_TX_DFP_17_UFP_0		(2 << 4)
-#define TUSB544_EQ_TX_DFP_32_UFP_14		(3 << 4)
-#define TUSB544_EQ_TX_DFP_41_UFP_24		(4 << 4)
-#define TUSB544_EQ_TX_DFP_52_UFP_35		(5 << 4)
-#define TUSB544_EQ_TX_DFP_61_UFP_43		(6 << 4)
-#define TUSB544_EQ_TX_DFP_69_UFP_52		(7 << 4)
-#define TUSB544_EQ_TX_DFP_77_UFP_60		(8 << 4)
-#define TUSB544_EQ_TX_DFP_83_UFP_66		(9 << 4)
-#define TUSB544_EQ_TX_DFP_88_UFP_72		(10 << 4)
-#define TUSB544_EQ_TX_DFP_94_UFP_77		(11 << 4)
-#define TUSB544_EQ_TX_DFP_98_UFP_81		(12 << 4)
-#define TUSB544_EQ_TX_DFP_103_UFP_86		(13 << 4)
-#define TUSB544_EQ_TX_DFP_106_UFP_90		(14 << 4)
-#define TUSB544_EQ_TX_DFP_110_UFP_94		(15 << 4)
-#define TUSB544_EQ_TX_MASK		(0xF0)
+#define TUSB544_EQ_TX_DFP_MINUS14_UFP_MINUS33 (0 << 4)
+#define TUSB544_EQ_TX_DFP_04_UFP_MINUS15 (1 << 4)
+#define TUSB544_EQ_TX_DFP_17_UFP_0 (2 << 4)
+#define TUSB544_EQ_TX_DFP_32_UFP_14 (3 << 4)
+#define TUSB544_EQ_TX_DFP_41_UFP_24 (4 << 4)
+#define TUSB544_EQ_TX_DFP_52_UFP_35 (5 << 4)
+#define TUSB544_EQ_TX_DFP_61_UFP_43 (6 << 4)
+#define TUSB544_EQ_TX_DFP_69_UFP_52 (7 << 4)
+#define TUSB544_EQ_TX_DFP_77_UFP_60 (8 << 4)
+#define TUSB544_EQ_TX_DFP_83_UFP_66 (9 << 4)
+#define TUSB544_EQ_TX_DFP_88_UFP_72 (10 << 4)
+#define TUSB544_EQ_TX_DFP_94_UFP_77 (11 << 4)
+#define TUSB544_EQ_TX_DFP_98_UFP_81 (12 << 4)
+#define TUSB544_EQ_TX_DFP_103_UFP_86 (13 << 4)
+#define TUSB544_EQ_TX_DFP_106_UFP_90 (14 << 4)
+#define TUSB544_EQ_TX_DFP_110_UFP_94 (15 << 4)
+#define TUSB544_EQ_TX_MASK (0xF0)
 
 enum tusb544_ct_sel {
 	TUSB544_CTL_SEL_DISABLED,
@@ -66,10 +65,10 @@ enum tusb544_ct_sel {
 	TUSB544_CTL_SEL_DP_USB,
 };
 
-#define TUSB544_REG_GENERAL6	0x0C
-#define TUSB544_GEN6_DIR_SEL	GENMASK(1, 0)
-#define TUSB544_VOD_DCGAIN_SEL	GENMASK(5, 2)
-#define TUSB544_VOD_DCGAIN_OVERRIDE  BIT(6)
+#define TUSB544_REG_GENERAL6 0x0C
+#define TUSB544_GEN6_DIR_SEL GENMASK(1, 0)
+#define TUSB544_VOD_DCGAIN_SEL GENMASK(5, 2)
+#define TUSB544_VOD_DCGAIN_OVERRIDE BIT(6)
 
 enum tusb544_dir_sel {
 	TUSB544_DIR_SEL_USB_DP_SRC,
@@ -93,17 +92,17 @@ enum tusb544_vod_dcgain_sel {
  * Note: TUSB544 automatically snoops DP lanes to enable, but may be manually
  * directed which lanes to turn on when snoop is disabled
  */
-#define TUSB544_REG_DP4			0x13
-#define TUSB544_DP4_DP0_DISABLE		BIT(0)
-#define TUSB544_DP4_DP1_DISABLE		BIT(1)
-#define TUSB544_DP4_DP2_DISABLE		BIT(2)
-#define TUSB544_DP4_DP3_DISABLE		BIT(3)
-#define TUSB544_DP4_AUX_SBU_OVR		GENMASK(5, 4)
-#define TUSB544_DP4_AUX_SNOOP_DISABLE	BIT(7)
+#define TUSB544_REG_DP4 0x13
+#define TUSB544_DP4_DP0_DISABLE BIT(0)
+#define TUSB544_DP4_DP1_DISABLE BIT(1)
+#define TUSB544_DP4_DP2_DISABLE BIT(2)
+#define TUSB544_DP4_DP3_DISABLE BIT(3)
+#define TUSB544_DP4_AUX_SBU_OVR GENMASK(5, 4)
+#define TUSB544_DP4_AUX_SNOOP_DISABLE BIT(7)
 
 extern const struct usb_mux_driver tusb544_drv;
 
 int tusb544_i2c_field_update8(const struct usb_mux *me, int offset,
-			     uint8_t field_mask, uint8_t set_value);
+			      uint8_t field_mask, uint8_t set_value);
 
 #endif
diff --git a/driver/sb_rmi.c b/driver/sb_rmi.c
index 49783188e1..420ef672ad 100644
--- a/driver/sb_rmi.c
+++ b/driver/sb_rmi.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,11 +12,12 @@
 #include "sb_rmi.h"
 #include "stdbool.h"
 #include "time.h"
+#include "timer.h"
 #include "util.h"
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_SYSTEM, outstr)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
 #define SB_RMI_MAILBOX_TIMEOUT_MS 200
 #define SB_RMI_MAILBOX_RETRY_DELAY_MS 5
@@ -47,7 +48,6 @@ static int sb_rmi_assert_interrupt(bool assert)
 	return sb_rmi_write(SB_RMI_SW_INTR_REG, assert ? 0x1 : 0x0);
 }
 
-
 /**
  * Execute a SB-RMI mailbox transaction
  *
@@ -60,34 +60,34 @@ static int sb_rmi_assert_interrupt(bool assert)
  */
 int sb_rmi_mailbox_xfer(int cmd, uint32_t msg_in, uint32_t *msg_out_ptr)
 {
-       /**
-	* The sequence is as follows:
-	* 1. The initiator (BMC) indicates that command is to be serviced by
-	*    firmware by writing 0x80 to SBRMI::InBndMsg_inst7 (SBRMI_x3F). This
-	*    register must be set to 0x80 after reset.
-	* 2. The initiator (BMC) writes the command to SBRMI::InBndMsg_inst0
-	*    (SBRMI_x38).
-	* 3. For write operations or read operations which require additional
-	*    addressing information as shown in the table above, the initiator
-	*    (BMC) writes Command Data In[31:0] to SBRMI::InBndMsg_inst[4:1]
-	*    {SBRMI_x3C(MSB):SBRMI_x39(LSB)}.
-	* 4. The initiator (BMC) writes 0x01 to SBRMI::SoftwareInterrupt to
-	*    notify firmware to perform the requested read or write command.
-	* 5. Firmware reads the message and performs the defined action.
-	* 6. Firmware writes the original command to outbound message register
-	*    SBRMI::OutBndMsg_inst0 (SBRMI_x30).
-	* 7. Firmware will write SBRMI::Status[SwAlertSts]=1 to generate an
-	*    ALERT (if enabled) to initiator (BMC) to indicate completion of the
-	*    requested command. Firmware must (if applicable) put the message
-	*    data into the message registers SBRMI::OutBndMsg_inst[4:1]
-	*    {SBRMI_x34(MSB):SBRMI_x31(LSB)}.
-	* 8. For a read operation, the initiator (BMC) reads the firmware
-	*    response Command Data Out[31:0] from SBRMI::OutBndMsg_inst[4:1]
-	*    {SBRMI_x34(MSB):SBRMI_x31(LSB)}.
-	* 9. BMC must write 1'b1 to SBRMI::Status[SwAlertSts] to clear the
-	*     ALERT to initiator (BMC). It is recommended to clear the ALERT
-	*     upon completion of the current mailbox command.
-	*/
+	/**
+	 * The sequence is as follows:
+	 * 1. The initiator (BMC) indicates that command is to be serviced by
+	 *    firmware by writing 0x80 to SBRMI::InBndMsg_inst7 (SBRMI_x3F).
+	 * This register must be set to 0x80 after reset.
+	 * 2. The initiator (BMC) writes the command to SBRMI::InBndMsg_inst0
+	 *    (SBRMI_x38).
+	 * 3. For write operations or read operations which require additional
+	 *    addressing information as shown in the table above, the initiator
+	 *    (BMC) writes Command Data In[31:0] to SBRMI::InBndMsg_inst[4:1]
+	 *    {SBRMI_x3C(MSB):SBRMI_x39(LSB)}.
+	 * 4. The initiator (BMC) writes 0x01 to SBRMI::SoftwareInterrupt to
+	 *    notify firmware to perform the requested read or write command.
+	 * 5. Firmware reads the message and performs the defined action.
+	 * 6. Firmware writes the original command to outbound message register
+	 *    SBRMI::OutBndMsg_inst0 (SBRMI_x30).
+	 * 7. Firmware will write SBRMI::Status[SwAlertSts]=1 to generate an
+	 *    ALERT (if enabled) to initiator (BMC) to indicate completion of
+	 * the requested command. Firmware must (if applicable) put the message
+	 *    data into the message registers SBRMI::OutBndMsg_inst[4:1]
+	 *    {SBRMI_x34(MSB):SBRMI_x31(LSB)}.
+	 * 8. For a read operation, the initiator (BMC) reads the firmware
+	 *    response Command Data Out[31:0] from SBRMI::OutBndMsg_inst[4:1]
+	 *    {SBRMI_x34(MSB):SBRMI_x31(LSB)}.
+	 * 9. BMC must write 1'b1 to SBRMI::Status[SwAlertSts] to clear the
+	 *     ALERT to initiator (BMC). It is recommended to clear the ALERT
+	 *     upon completion of the current mailbox command.
+	 */
 	int val;
 	bool alerted;
 	timestamp_t start;
diff --git a/driver/sb_rmi.h b/driver/sb_rmi.h
index 132af0e70a..d406562f79 100644
--- a/driver/sb_rmi.h
+++ b/driver/sb_rmi.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/driver/sensorhub_lsm6dsm.c b/driver/sensorhub_lsm6dsm.c
index 7957925bf1..d801eb85f3 100644
--- a/driver/sensorhub_lsm6dsm.c
+++ b/driver/sensorhub_lsm6dsm.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,10 +13,10 @@
 #include "driver/sensorhub_lsm6dsm.h"
 #include "driver/stm_mems_common.h"
 
-#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args)
 
-static int set_reg_bit_field(const struct motion_sensor_t *s,
-					uint8_t reg, uint8_t bit_field)
+static int set_reg_bit_field(const struct motion_sensor_t *s, uint8_t reg,
+			     uint8_t bit_field)
 {
 	int tmp;
 	int ret;
@@ -29,8 +29,8 @@ static int set_reg_bit_field(const struct motion_sensor_t *s,
 	return st_raw_write8(s->port, s->i2c_spi_addr_flags, reg, tmp);
 }
 
-static int clear_reg_bit_field(const struct motion_sensor_t *s,
-					uint8_t reg, uint8_t bit_field)
+static int clear_reg_bit_field(const struct motion_sensor_t *s, uint8_t reg,
+			       uint8_t bit_field)
 {
 	int tmp;
 	int ret;
@@ -45,14 +45,13 @@ static int clear_reg_bit_field(const struct motion_sensor_t *s,
 
 static inline int enable_sensorhub_func(const struct motion_sensor_t *s)
 {
-	return set_reg_bit_field(s, LSM6DSM_CTRL10_ADDR,
-						LSM6DSM_EMBED_FUNC_EN);
+	return set_reg_bit_field(s, LSM6DSM_CTRL10_ADDR, LSM6DSM_EMBED_FUNC_EN);
 }
 
 static inline int disable_sensorhub_func(const struct motion_sensor_t *s)
 {
 	return clear_reg_bit_field(s, LSM6DSM_CTRL10_ADDR,
-						LSM6DSM_EMBED_FUNC_EN);
+				   LSM6DSM_EMBED_FUNC_EN);
 }
 
 /*
@@ -65,13 +64,13 @@ static inline int disable_sensorhub_func(const struct motion_sensor_t *s)
 static inline int enable_ereg_bank_acc(const struct motion_sensor_t *s)
 {
 	return set_reg_bit_field(s, LSM6DSM_FUNC_CFG_ACC_ADDR,
-							LSM6DSM_FUNC_CFG_EN);
+				 LSM6DSM_FUNC_CFG_EN);
 }
 
 static inline int disable_ereg_bank_acc(const struct motion_sensor_t *s)
 {
 	return clear_reg_bit_field(s, LSM6DSM_FUNC_CFG_ACC_ADDR,
-							LSM6DSM_FUNC_CFG_EN);
+				   LSM6DSM_FUNC_CFG_EN);
 }
 
 static inline int enable_aux_i2c_controller(const struct motion_sensor_t *s)
@@ -87,22 +86,21 @@ static inline int disable_aux_i2c_controller(const struct motion_sensor_t *s)
 }
 
 static inline int restore_controller_cfg(const struct motion_sensor_t *s,
-								int cache)
+					 int cache)
 {
 	return st_raw_write8(s->port, s->i2c_spi_addr_flags,
 			     LSM6DSM_CONTROLLER_CFG_ADDR, cache);
 }
 
-static int enable_i2c_pass_through(const struct motion_sensor_t *s,
-							int *cache)
+static int enable_i2c_pass_through(const struct motion_sensor_t *s, int *cache)
 {
 	int ret;
 
 	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags,
 			   LSM6DSM_CONTROLLER_CFG_ADDR, cache);
 	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x MCR error ret: %d\n",
-			__func__, s->name, s->type, ret);
+		CPRINTF("%s: %s type:0x%x MCR error ret: %d\n", __func__,
+			s->name, s->type, ret);
 		return ret;
 	}
 
@@ -115,19 +113,18 @@ static int enable_i2c_pass_through(const struct motion_sensor_t *s,
 			    LSM6DSM_CONTROLLER_CFG_ADDR,
 			    *cache | LSM6DSM_EXT_TRIGGER_EN);
 	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x MCETEN error ret: %d\n",
-			__func__, s->name, s->type, ret);
+		CPRINTF("%s: %s type:0x%x MCETEN error ret: %d\n", __func__,
+			s->name, s->type, ret);
 		return ret;
 	}
 	msleep(10);
 
-	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
-			    LSM6DSM_CONTROLLER_CFG_ADDR,
-				 *cache & ~(LSM6DSM_EXT_TRIGGER_EN
-					    | LSM6DSM_I2C_CONTROLLER_ON));
+	ret = st_raw_write8(
+		s->port, s->i2c_spi_addr_flags, LSM6DSM_CONTROLLER_CFG_ADDR,
+		*cache & ~(LSM6DSM_EXT_TRIGGER_EN | LSM6DSM_I2C_CONTROLLER_ON));
 	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x MCC error ret: %d\n",
-			__func__, s->name, s->type, ret);
+		CPRINTF("%s: %s type:0x%x MCC error ret: %d\n", __func__,
+			s->name, s->type, ret);
 		restore_controller_cfg(s, *cache);
 		return ret;
 	}
@@ -137,33 +134,31 @@ static int enable_i2c_pass_through(const struct motion_sensor_t *s,
 			     LSM6DSM_I2C_PASS_THRU_MODE);
 }
 
-static inline int power_down_accel(const struct motion_sensor_t *s,
-						int *cache)
+static inline int power_down_accel(const struct motion_sensor_t *s, int *cache)
 {
 	int ret;
 
-	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags,
-			   LSM6DSM_CTRL1_ADDR, cache);
+	ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, LSM6DSM_CTRL1_ADDR,
+			   cache);
 	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x CTRL1R error ret: %d\n",
-			__func__, s->name, s->type, ret);
+		CPRINTF("%s: %s type:0x%x CTRL1R error ret: %d\n", __func__,
+			s->name, s->type, ret);
 		return ret;
 	}
 
-	return st_raw_write8(s->port, s->i2c_spi_addr_flags,
-			     LSM6DSM_CTRL1_ADDR,
+	return st_raw_write8(s->port, s->i2c_spi_addr_flags, LSM6DSM_CTRL1_ADDR,
 			     *cache & ~LSM6DSM_XL_ODR_MASK);
 }
 
 static inline int restore_ctrl1(const struct motion_sensor_t *s, int cache)
 {
-	return st_raw_write8(s->port, s->i2c_spi_addr_flags,
-			     LSM6DSM_CTRL1_ADDR, cache);
+	return st_raw_write8(s->port, s->i2c_spi_addr_flags, LSM6DSM_CTRL1_ADDR,
+			     cache);
 }
 
 static int config_slv0_read(const struct motion_sensor_t *s,
-			    const uint16_t slv_addr_flags,
-			    uint16_t reg, uint8_t len)
+			    const uint16_t slv_addr_flags, uint16_t reg,
+			    uint8_t len)
 {
 	int ret;
 	uint16_t addr_8bit = I2C_STRIP_FLAGS(slv_addr_flags) << 1;
@@ -172,16 +167,16 @@ static int config_slv0_read(const struct motion_sensor_t *s,
 			    LSM6DSM_SLV0_ADD_ADDR,
 			    (addr_8bit | LSM6DSM_SLV0_RD_BIT));
 	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x SA error ret: %d\n",
-			__func__, s->name, s->type, ret);
+		CPRINTF("%s: %s type:0x%x SA error ret: %d\n", __func__,
+			s->name, s->type, ret);
 		return ret;
 	}
 
 	ret = st_raw_write8(s->port, s->i2c_spi_addr_flags,
 			    LSM6DSM_SLV0_SUBADD_ADDR, reg);
 	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x RA error ret: %d\n",
-			__func__, s->name, s->type, ret);
+		CPRINTF("%s: %s type:0x%x RA error ret: %d\n", __func__,
+			s->name, s->type, ret);
 		return ret;
 	}
 
@@ -193,8 +188,8 @@ static int config_slv0_read(const struct motion_sensor_t *s,
 			    LSM6DSM_SLV0_CONFIG_ADDR,
 			    (len & LSM6DSM_SLV0_NUM_OPS_MASK));
 	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x CFG error ret: %d\n",
-			__func__, s->name, s->type, ret);
+		CPRINTF("%s: %s type:0x%x CFG error ret: %d\n", __func__,
+			s->name, s->type, ret);
 		return ret;
 	}
 
@@ -202,16 +197,16 @@ static int config_slv0_read(const struct motion_sensor_t *s,
 }
 
 int sensorhub_config_ext_reg(const struct motion_sensor_t *s,
-			     const uint16_t slv_addr_flags,
-			     uint8_t reg, uint8_t val)
+			     const uint16_t slv_addr_flags, uint8_t reg,
+			     uint8_t val)
 {
 	int ret;
 	int tmp;
 
 	ret = enable_i2c_pass_through(s, &tmp);
 	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x ENI2C error ret: %d\n",
-			__func__, s->name, s->type, ret);
+		CPRINTF("%s: %s type:0x%x ENI2C error ret: %d\n", __func__,
+			s->name, s->type, ret);
 		return ret;
 	}
 
@@ -227,44 +222,44 @@ int sensorhub_config_slv0_read(const struct motion_sensor_t *s,
 	int ret;
 
 	if (len <= 0 || len > OUT_XYZ_SIZE) {
-		CPRINTF("%s: %s type:0x%x Invalid length: %d\n",
-			__func__, s->name, s->type, len);
+		CPRINTF("%s: %s type:0x%x Invalid length: %d\n", __func__,
+			s->name, s->type, len);
 		return EC_ERROR_INVAL;
 	}
 
 	ret = power_down_accel(s, &tmp_xl_cfg);
 	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x PDXL error ret: %d\n",
-			__func__, s->name, s->type, ret);
+		CPRINTF("%s: %s type:0x%x PDXL error ret: %d\n", __func__,
+			s->name, s->type, ret);
 		return ret;
 	}
 
 	ret = enable_ereg_bank_acc(s);
 	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x ENERB error ret: %d\n",
-			__func__, s->name, s->type, ret);
+		CPRINTF("%s: %s type:0x%x ENERB error ret: %d\n", __func__,
+			s->name, s->type, ret);
 		goto out_restore_ctrl1;
 	}
 
 	ret = config_slv0_read(s, slv_addr_flags, reg, len);
 	disable_ereg_bank_acc(s);
 	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x CS0R error ret: %d\n",
-			__func__, s->name, s->type, ret);
+		CPRINTF("%s: %s type:0x%x CS0R error ret: %d\n", __func__,
+			s->name, s->type, ret);
 		goto out_restore_ctrl1;
 	}
 
 	ret = enable_sensorhub_func(s);
 	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x ENSH error ret: %d\n",
-			__func__, s->name, s->type, ret);
+		CPRINTF("%s: %s type:0x%x ENSH error ret: %d\n", __func__,
+			s->name, s->type, ret);
 		goto out_restore_ctrl1;
 	}
 
 	ret = enable_aux_i2c_controller(s);
 	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x ENI2CM error ret: %d\n",
-			__func__, s->name, s->type, ret);
+		CPRINTF("%s: %s type:0x%x ENI2CM error ret: %d\n", __func__,
+			s->name, s->type, ret);
 		disable_sensorhub_func(s);
 	}
 out_restore_ctrl1:
@@ -282,41 +277,40 @@ int sensorhub_slv0_data_read(const struct motion_sensor_t *s, uint8_t *raw)
 	 * contents of that register.
 	 */
 	ret = st_raw_read_n_noinc(s->port, s->i2c_spi_addr_flags,
-				  LSM6DSM_SENSORHUB1_REG,
-				  raw, OUT_XYZ_SIZE);
+				  LSM6DSM_SENSORHUB1_REG, raw, OUT_XYZ_SIZE);
 	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x SH1R error ret: %d\n",
-			__func__, s->name, s->type, ret);
+		CPRINTF("%s: %s type:0x%x SH1R error ret: %d\n", __func__,
+			s->name, s->type, ret);
 		return ret;
 	}
 	return EC_SUCCESS;
 }
 
 int sensorhub_check_and_rst(const struct motion_sensor_t *s,
-			    const uint16_t slv_addr_flags,
-			    uint8_t whoami_reg, uint8_t whoami_val,
-			    uint8_t rst_reg, uint8_t rst_val)
+			    const uint16_t slv_addr_flags, uint8_t whoami_reg,
+			    uint8_t whoami_val, uint8_t rst_reg,
+			    uint8_t rst_val)
 {
 	int ret, tmp;
 	int tmp_controller_cfg;
 
 	ret = enable_i2c_pass_through(s, &tmp_controller_cfg);
 	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x ENI2C error ret: %d\n",
-			__func__, s->name, s->type, ret);
+		CPRINTF("%s: %s type:0x%x ENI2C error ret: %d\n", __func__,
+			s->name, s->type, ret);
 		return ret;
 	}
 
 	ret = st_raw_read8(s->port, slv_addr_flags, whoami_reg, &tmp);
 	if (ret != EC_SUCCESS) {
-		CPRINTF("%s: %s type:0x%x WAIR error ret: %d\n",
-			__func__, s->name, s->type, ret);
+		CPRINTF("%s: %s type:0x%x WAIR error ret: %d\n", __func__,
+			s->name, s->type, ret);
 		goto err_restore_controller_cfg;
 	}
 
 	if (tmp != whoami_val) {
-		CPRINTF("%s: %s type:0x%x WAIC error ret: %d\n",
-			__func__, s->name, s->type, ret);
+		CPRINTF("%s: %s type:0x%x WAIC error ret: %d\n", __func__,
+			s->name, s->type, ret);
 		ret = EC_ERROR_UNKNOWN;
 		goto err_restore_controller_cfg;
 	}
diff --git a/driver/sensorhub_lsm6dsm.h b/driver/sensorhub_lsm6dsm.h
index 07b19046df..9f1b7671ac 100644
--- a/driver/sensorhub_lsm6dsm.h
+++ b/driver/sensorhub_lsm6dsm.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,8 +25,8 @@
  * @return EC_SUCCESS on success, EC error codes on failure.
  */
 int sensorhub_config_ext_reg(const struct motion_sensor_t *s,
-			     const uint16_t slv_addr_flags,
-			     uint8_t reg, uint8_t val);
+			     const uint16_t slv_addr_flags, uint8_t reg,
+			     uint8_t val);
 
 /**
  * Configure the sensor hub to read data from a specific register of an
@@ -39,8 +39,8 @@ int sensorhub_config_ext_reg(const struct motion_sensor_t *s,
  * @return EC_SUCCESS on success, EC error codes on failure.
  */
 int sensorhub_config_slv0_read(const struct motion_sensor_t *s,
-			       const uint16_t slv_addr_flags,
-			       uint8_t reg, int len);
+			       const uint16_t slv_addr_flags, uint8_t reg,
+			       int len);
 
 /**
  * Reads the data from the register bank that is associated with the slave0
@@ -65,7 +65,7 @@ int sensorhub_slv0_data_read(const struct motion_sensor_t *s, uint8_t *raw);
  * @return EC_SUCCESS on success, EC error codes on failure.
  */
 int sensorhub_check_and_rst(const struct motion_sensor_t *s,
-			    const uint16_t slv_addr_flags,
-			    uint8_t whoami_reg, uint8_t whoami_val,
-			    uint8_t rst_reg, uint8_t rst_val);
+			    const uint16_t slv_addr_flags, uint8_t whoami_reg,
+			    uint8_t whoami_val, uint8_t rst_reg,
+			    uint8_t rst_val);
 #endif /* __CROS_EC_SENSORHUB_LSM6DSM_H */
diff --git a/driver/stm_mems_common.c b/driver/stm_mems_common.c
index d3088521d9..93a0b4dc2f 100644
--- a/driver/stm_mems_common.c
+++ b/driver/stm_mems_common.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,28 +11,24 @@
 /**
  * st_raw_read_n - Read n bytes for read
  */
-int st_raw_read_n(const int port,
-		  const uint16_t i2c_addr_flags,
+int st_raw_read_n(const int port, const uint16_t i2c_addr_flags,
 		  const uint8_t reg, uint8_t *data_ptr, const int len)
 {
 	/* TODO: Implement SPI interface support */
-	return i2c_read_block(port, i2c_addr_flags,
-			      reg | 0x80, data_ptr, len);
+	return i2c_read_block(port, i2c_addr_flags, reg | 0x80, data_ptr, len);
 }
 
 /**
  * st_raw_read_n_noinc - Read n bytes for read (no auto inc address)
  */
-int st_raw_read_n_noinc(const int port,
-			const uint16_t i2c_addr_flags,
+int st_raw_read_n_noinc(const int port, const uint16_t i2c_addr_flags,
 			const uint8_t reg, uint8_t *data_ptr, const int len)
 {
 	/* TODO: Implement SPI interface support */
-	return i2c_read_block(port, i2c_addr_flags,
-			      reg, data_ptr, len);
+	return i2c_read_block(port, i2c_addr_flags, reg, data_ptr, len);
 }
 
- /**
+/**
  * st_write_data_with_mask - Write register with mask
  * @s: Motion sensor pointer
  * @reg: Device register
@@ -40,24 +36,22 @@ int st_raw_read_n_noinc(const int port,
  * @data: Data pointer
  */
 int st_write_data_with_mask(const struct motion_sensor_t *s, int reg,
-			 uint8_t mask, uint8_t data)
+			    uint8_t mask, uint8_t data)
 {
 	int err;
 	int new_data = 0x00, old_data = 0x00;
 
-	err = st_raw_read8(s->port, s->i2c_spi_addr_flags,
-			   reg, &old_data);
+	err = st_raw_read8(s->port, s->i2c_spi_addr_flags, reg, &old_data);
 	if (err != EC_SUCCESS)
 		return err;
 
-	new_data = ((old_data & (~mask)) |
-		    ((data << __builtin_ctz(mask)) & mask));
+	new_data =
+		((old_data & (~mask)) | ((data << __builtin_ctz(mask)) & mask));
 
 	if (new_data == old_data)
 		return EC_SUCCESS;
 
-	return st_raw_write8(s->port, s->i2c_spi_addr_flags,
-			     reg, new_data);
+	return st_raw_write8(s->port, s->i2c_spi_addr_flags, reg, new_data);
 }
 
 /**
@@ -77,8 +71,8 @@ int st_get_resolution(const struct motion_sensor_t *s)
  * @offset: offset vector
  * @temp: Temp
  */
-int st_set_offset(const struct motion_sensor_t *s,
-	       const int16_t *offset, int16_t temp)
+int st_set_offset(const struct motion_sensor_t *s, const int16_t *offset,
+		  int16_t temp)
 {
 	struct stprivate_data *data = s->drv_data;
 
@@ -94,8 +88,8 @@ int st_set_offset(const struct motion_sensor_t *s,
  * @offset: offset vector
  * @temp: Temp
  */
-int st_get_offset(const struct motion_sensor_t *s,
-	       int16_t *offset, int16_t *temp)
+int st_get_offset(const struct motion_sensor_t *s, int16_t *offset,
+		  int16_t *temp)
 {
 	struct stprivate_data *data = s->drv_data;
 
@@ -142,3 +136,20 @@ void st_normalize(const struct motion_sensor_t *s, intv3_t v, uint8_t *data)
 	for (i = X; i <= Z; i++)
 		v[i] += (drvdata->offset[i] << 5) / s->current_range;
 }
+
+#ifdef CONFIG_GESTURE_HOST_DETECTION
+/**
+ * st_list_activities - Apply to LSB data sensitivity and rotation
+ * @s: Motion sensor pointer
+ * @enabled: Activities that are enabled (bitmap)
+ * @disabled: Activities that are disabled (bitmap)
+ */
+int st_list_activities(const struct motion_sensor_t *s, uint32_t *enabled,
+		       uint32_t *disabled)
+{
+	struct stprivate_data *data = s->drv_data;
+	*enabled = data->enabled_activities;
+	*disabled = data->disabled_activities;
+	return EC_RES_SUCCESS;
+}
+#endif /* CONFIG_GESTURE_HOST_DETECTION */
diff --git a/driver/stm_mems_common.h b/driver/stm_mems_common.h
index 1c0afbc9f4..370ce10d9c 100644
--- a/driver/stm_mems_common.h
+++ b/driver/stm_mems_common.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,25 +15,25 @@
 #include "i2c.h"
 
 /* X, Y, Z axis data len */
-#define OUT_XYZ_SIZE			6
+#define OUT_XYZ_SIZE 6
 
-#define ST_NORMALIZE_RATE(_fs)    (1 << __fls(_fs))
+#define ST_NORMALIZE_RATE(_fs) (1 << __fls(_fs))
 
-#define FIFO_BUFFER_NUM_PATTERN		8
+#define FIFO_BUFFER_NUM_PATTERN 8
 /* Define number of data to be read from FIFO each time
  * It must be a multiple of OUT_XYZ_SIZE.
  * In case of LSM6DSM FIFO contains pattern depending ODR
  * of Acc/gyro, be sure that FIFO can contains almost
  * FIFO_BUFFER_NUM_PATTERNpattern
  */
-#define FIFO_READ_LEN			(FIFO_BUFFER_NUM_PATTERN * OUT_XYZ_SIZE)
+#define FIFO_READ_LEN (FIFO_BUFFER_NUM_PATTERN * OUT_XYZ_SIZE)
 
 /**
  * Read single register
  */
 static inline int st_raw_read8(const int port,
-			       const uint16_t i2c_spi_addr_flags,
-			       const int reg, int *data_ptr)
+			       const uint16_t i2c_spi_addr_flags, const int reg,
+			       int *data_ptr)
 {
 	/* TODO: Implement SPI interface support */
 	return i2c_read8(port, i2c_spi_addr_flags, reg, data_ptr);
@@ -53,18 +53,16 @@ static inline int st_raw_write8(const int port,
 /**
  * st_raw_read_n - Read n bytes for read
  */
-int st_raw_read_n(const int port,
-		  const uint16_t i2c_spi_addr_flags,
+int st_raw_read_n(const int port, const uint16_t i2c_spi_addr_flags,
 		  const uint8_t reg, uint8_t *data_ptr, const int len);
 
 /**
  * st_raw_read_n_noinc - Read n bytes for read (no auto inc address)
  */
-int st_raw_read_n_noinc(const int port,
-			const uint16_t i2c_spi_addr_flags,
+int st_raw_read_n_noinc(const int port, const uint16_t i2c_spi_addr_flags,
 			const uint8_t reg, uint8_t *data_ptr, const int len);
 
- /**
+/**
  * st_write_data_with_mask - Write register with mask
  * @s: Motion sensor pointer
  * @reg: Device register
@@ -72,9 +70,9 @@ int st_raw_read_n_noinc(const int port,
  * @data: Data pointer
  */
 int st_write_data_with_mask(const struct motion_sensor_t *s, int reg,
-			 uint8_t mask, uint8_t data);
+			    uint8_t mask, uint8_t data);
 
- /**
+/**
  * st_get_resolution - Get bit resolution
  * @s: Motion sensor pointer
  */
@@ -86,8 +84,8 @@ int st_get_resolution(const struct motion_sensor_t *s);
  * @offset: offset vector
  * @temp: Temp
  */
-int st_set_offset(const struct motion_sensor_t *s,
-		  const int16_t *offset, int16_t temp);
+int st_set_offset(const struct motion_sensor_t *s, const int16_t *offset,
+		  int16_t temp);
 
 /**
  * st_get_offset - Get data offset
@@ -95,8 +93,8 @@ int st_set_offset(const struct motion_sensor_t *s,
  * @offset: offset vector
  * @temp: Temp
  */
-int st_get_offset(const struct motion_sensor_t *s,
-		  int16_t *offset, int16_t *temp);
+int st_get_offset(const struct motion_sensor_t *s, int16_t *offset,
+		  int16_t *temp);
 
 /**
  * st_get_data_rate - Get data rate (ODR)
@@ -112,11 +110,22 @@ int st_get_data_rate(const struct motion_sensor_t *s);
  */
 void st_normalize(const struct motion_sensor_t *s, intv3_t v, uint8_t *data);
 
+/**
+ * st_list_activities - Apply to LSB data sensitivity and rotation
+ * @s: Motion sensor pointer
+ * @enabled: Activities that are enabled (bitmap)
+ * @disabled: Activities that are disabled (bitmap)
+ */
+int st_list_activities(const struct motion_sensor_t *s, uint32_t *enabled,
+		       uint32_t *disabled);
+
 /* Internal data structure for sensors */
 struct stprivate_data {
 	struct accelgyro_saved_data_t base;
-	uint8_t              enabled_activities;
-	uint8_t              disabled_activities;
+#ifdef CONFIG_GESTURE_HOST_DETECTION
+	uint8_t enabled_activities;
+	uint8_t disabled_activities;
+#endif /* CONFIG_GESTURE_HOST_DETECTION */
 	int16_t offset[3];
 	uint8_t resol;
 };
diff --git a/driver/sync.c b/driver/sync.c
index 3dc9c98ece..6c48096a18 100644
--- a/driver/sync.c
+++ b/driver/sync.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -17,8 +17,8 @@
 #include "task.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_MOTION_SENSE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_MOTION_SENSE, format, ##args)
 
 #ifndef CONFIG_ACCEL_FIFO
 #error This driver needs CONFIG_ACCEL_FIFO
@@ -35,7 +35,7 @@ static struct queue const sync_event_queue =
 struct sync_event_t next_event;
 struct ec_response_motion_sensor_data vector = {
 	.flags = MOTIONSENSE_SENSOR_FLAG_BYPASS_FIFO,
-	.data = {0, 0, 0}
+	.data = { 0, 0, 0 }
 };
 
 int sync_enabled;
@@ -51,8 +51,8 @@ static int sync_read(const struct motion_sensor_t *s, intv3_t v)
  * still depends on being able to set this to 0 to disable it, we'll just use
  * non 0 rate values as an enable boolean.
  */
-static int sync_set_data_rate(const struct motion_sensor_t *s,
-				int rate, int roundup)
+static int sync_set_data_rate(const struct motion_sensor_t *s, int rate,
+			      int roundup)
 {
 	sync_enabled = !!rate;
 	CPRINTF("sync event driver enabling=%d\n", sync_enabled);
@@ -88,8 +88,8 @@ static int motion_irq_handler(struct motion_sensor_t *s, uint32_t *event)
 
 	while (queue_remove_unit(&sync_event_queue, &sync_event)) {
 		vector.data[X] = sync_event.counter;
-		motion_sense_fifo_stage_data(
-			&vector, s, 1, sync_event.timestamp);
+		motion_sense_fifo_stage_data(&vector, s, 1,
+					     sync_event.timestamp);
 	}
 	motion_sense_fifo_commit_data();
 
@@ -106,7 +106,7 @@ static int sync_init(struct motion_sensor_t *s)
 }
 
 #ifdef CONFIG_SYNC_COMMAND
-static int command_sync(int argc, char **argv)
+static int command_sync(int argc, const char **argv)
 {
 	int count = 1, i;
 
@@ -118,9 +118,7 @@ static int command_sync(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(sync, command_sync,
-	"[count]",
-	"Simulates sync events");
+DECLARE_CONSOLE_COMMAND(sync, command_sync, "[count]", "Simulates sync events");
 #endif
 
 const struct accelgyro_drv sync_drv = {
diff --git a/driver/sync.h b/driver/sync.h
index bf21987b74..76aa225cc1 100644
--- a/driver/sync.h
+++ b/driver/sync.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -14,4 +14,4 @@ extern const struct accelgyro_drv sync_drv;
 
 void sync_interrupt(enum gpio_signal signal);
 
-#endif	/* __CROS_EC_VSYNC_H */
+#endif /* __CROS_EC_VSYNC_H */
diff --git a/driver/tcpm/anx7447.c b/driver/tcpm/anx7447.c
index 8bd0be36f4..a66e2e30b0 100644
--- a/driver/tcpm/anx7447.c
+++ b/driver/tcpm/anx7447.c
@@ -1,10 +1,11 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* ANX7447 port manager */
 
+#include "builtin/assert.h"
 #include "common.h"
 #include "anx7447.h"
 #include "console.h"
@@ -16,8 +17,8 @@
 #include "usb_pd.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 #define VSAFE5V_MIN 3800
 #define VSAFE0V_MAX 800
@@ -35,6 +36,12 @@ static int anx7447_mux_set(const struct usb_mux *me, mux_state_t mux_state,
 
 static struct anx_state anx[CONFIG_USB_PD_PORT_MAX_COUNT];
 static struct anx_usb_mux mux[CONFIG_USB_PD_PORT_MAX_COUNT];
+static bool anx7447_bist_test_mode[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+#ifdef CONFIG_USB_PD_FRS_TCPC
+/* an array to indicate which port is waiting for FRS disablement. */
+static bool anx_frs_dis[CONFIG_USB_PD_PORT_MAX_COUNT];
+#endif /* CONFIG_USB_PD_FRS_TCPC */
 
 /*
  * ANX7447 has two co-existence I2C addresses, TCPC address and
@@ -48,17 +55,16 @@ static struct anx_usb_mux mux[CONFIG_USB_PD_PORT_MAX_COUNT];
  * ANX7447 SPI address.
  */
 const struct anx7447_i2c_addr anx7447_i2c_addrs_flags[] = {
-	{AN7447_TCPC0_I2C_ADDR_FLAGS, AN7447_SPI0_I2C_ADDR_FLAGS},
-	{AN7447_TCPC1_I2C_ADDR_FLAGS, AN7447_SPI1_I2C_ADDR_FLAGS},
-	{AN7447_TCPC2_I2C_ADDR_FLAGS, AN7447_SPI2_I2C_ADDR_FLAGS},
-	{AN7447_TCPC3_I2C_ADDR_FLAGS, AN7447_SPI3_I2C_ADDR_FLAGS}
+	{ AN7447_TCPC0_I2C_ADDR_FLAGS, AN7447_SPI0_I2C_ADDR_FLAGS },
+	{ AN7447_TCPC1_I2C_ADDR_FLAGS, AN7447_SPI1_I2C_ADDR_FLAGS },
+	{ AN7447_TCPC2_I2C_ADDR_FLAGS, AN7447_SPI2_I2C_ADDR_FLAGS },
+	{ AN7447_TCPC3_I2C_ADDR_FLAGS, AN7447_SPI3_I2C_ADDR_FLAGS }
 };
 
 static inline int anx7447_reg_write(int port, int reg, int val)
 {
 	int rv = i2c_write8(tcpc_config[port].i2c_info.port,
-			    anx[port].i2c_addr_flags,
-			    reg, val);
+			    anx[port].i2c_addr_flags, reg, val);
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
 	pd_device_accessed(port);
 #endif
@@ -68,8 +74,7 @@ static inline int anx7447_reg_write(int port, int reg, int val)
 static inline int anx7447_reg_read(int port, int reg, int *val)
 {
 	int rv = i2c_read8(tcpc_config[port].i2c_info.port,
-			   anx[port].i2c_addr_flags,
-			   reg, val);
+			   anx[port].i2c_addr_flags, reg, val);
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
 	pd_device_accessed(port);
 #endif
@@ -146,7 +151,7 @@ static inline void anx7447_reg_write_or(int port, int reg, int v_or)
 		anx7447_reg_write(port, reg, (val | v_or));
 }
 
-#define ANX7447_FLASH_DONE_TIMEOUT_US	(100 * MSEC)
+#define ANX7447_FLASH_DONE_TIMEOUT_US (100 * MSEC)
 
 static int anx7447_wait_for_flash_done(int port)
 {
@@ -245,7 +250,7 @@ int anx7447_flash_erase(int port)
 }
 
 /* Add console command to erase OCM flash if needed. */
-static int command_anx_ocm(int argc, char **argv)
+static int command_anx_ocm(int argc, const char **argv)
 {
 	char *e = NULL;
 	int port;
@@ -265,24 +270,23 @@ static int command_anx_ocm(int argc, char **argv)
 		rv = anx7447_flash_erase_internal(
 			port, 1 /* write to console if empty */);
 		if (rv)
-			ccprintf("C%d: Failed to erase OCM flash (%d)\n",
-				 port, rv);
+			ccprintf("C%d: Failed to erase OCM flash (%d)\n", port,
+				 rv);
 	}
 
-	ccprintf("C%d: OCM flash is %sempty.\n",
-		port, anx7447_flash_is_empty(port) ? "" : "not ");
+	ccprintf("C%d: OCM flash is %sempty.\n", port,
+		 anx7447_flash_is_empty(port) ? "" : "not ");
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(anx_ocm, command_anx_ocm,
-			"port [erase]",
+DECLARE_CONSOLE_COMMAND(anx_ocm, command_anx_ocm, "port [erase]",
 			"Print OCM status or erases OCM for a given port.");
 #endif
 
 static int anx7447_init(int port)
 {
 	int rv, reg, i;
-	const struct usb_mux *me = &usb_muxes[port];
+	const struct usb_mux_chain *me = &usb_muxes[port];
 	bool unused;
 
 	ASSERT(port < CONFIG_USB_PD_PORT_MAX_COUNT);
@@ -303,21 +307,20 @@ static int anx7447_init(int port)
 		}
 	}
 	if (!I2C_STRIP_FLAGS(anx[port].i2c_addr_flags)) {
-		ccprintf("TCPC I2C addr 0x%x is invalid for ANX7447\n",
-			 I2C_STRIP_FLAGS(tcpc_config[port]
-				      .i2c_info.addr_flags));
+		ccprintf(
+			"TCPC I2C addr 0x%x is invalid for ANX7447\n",
+			I2C_STRIP_FLAGS(tcpc_config[port].i2c_info.addr_flags));
 		return EC_ERROR_UNKNOWN;
 	}
 
-
 	rv = tcpci_tcpm_init(port);
 	if (rv)
 		return rv;
 
 #ifdef CONFIG_USB_PD_TCPM_ANX7447_OCM_ERASE_COMMAND
 	/* Check and print OCM status to console. */
-	CPRINTS("C%d: OCM flash is %sempty",
-		port, anx7447_flash_is_empty(port) ? "" : "not ");
+	CPRINTS("C%d: OCM flash is %sempty", port,
+		anx7447_flash_is_empty(port) ? "" : "not ");
 #endif
 
 	/*
@@ -339,7 +342,8 @@ static int anx7447_init(int port)
 		return rv;
 
 	/* Set VBUS_VOLTAGE_ALARM_HI threshold */
-	RETURN_ERROR(tcpc_write16(port, TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG, 0x3FF));
+	RETURN_ERROR(
+		tcpc_write16(port, TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG, 0x3FF));
 	/* Set VCONN_VOLTAGE_ALARM_HI threshold to 6V */
 	RETURN_ERROR(tcpc_write16(port, VCONN_VOLTAGE_ALARM_HI_CFG, 0xF0));
 
@@ -370,21 +374,25 @@ static int anx7447_init(int port)
 	if (rv)
 		return rv;
 
+	if (IS_ENABLED(CONFIG_USB_PD_FRS_TCPC))
+		/* Unmask FRSWAP signal detect */
+		tcpc_write(port, ANX7447_REG_VD_ALERT_MASK,
+			   ANX7447_FRSWAP_SIGNAL_DETECTED);
+
 #ifdef CONFIG_USB_PD_TCPM_MUX
 	/*
 	 * Run mux_set() here for considering CCD(Case-Closed Debugging) case
 	 * If this TCPC is not also the MUX then don't initialize to NONE
 	 */
-	while ((me != NULL) && (me->driver != &anx7447_usb_mux_driver))
-		me = me->next_mux;
+	while ((me != NULL) && (me->mux->driver != &anx7447_usb_mux_driver))
+		me = me->next;
 
 	/*
 	 * Note that bypassing the usb_mux API is okay for internal driver calls
 	 * since the task calling init already holds this port's mux lock.
 	 */
-	if (me != NULL &&
-	    !(me->flags & USB_MUX_FLAG_NOT_TCPC))
-		rv = anx7447_mux_set(me, USB_PD_MUX_NONE, &unused);
+	if (me != NULL && !(me->mux->flags & USB_MUX_FLAG_NOT_TCPC))
+		rv = anx7447_mux_set(me->mux, USB_PD_MUX_NONE, &unused);
 #endif /* CONFIG_USB_PD_TCPM_MUX */
 
 	return rv;
@@ -460,12 +468,105 @@ int anx7447_board_charging_enable(int port, int enable)
 	return tcpc_write(port, TCPC_REG_COMMAND, enable ? 0x55 : 0x44);
 }
 
+static void anx7447_vendor_defined_alert(int port)
+{
+	int alert;
+
+	tcpc_read(port, ANX7447_REG_VD_ALERT, &alert);
+
+	/* write to clear alerts */
+	tcpc_write(port, ANX7447_REG_VD_ALERT, alert);
+
+	if (IS_ENABLED(CONFIG_USB_PD_FRS_TCPC) &&
+	    alert & ANX7447_FRSWAP_SIGNAL_DETECTED)
+		pd_got_frs_signal(port);
+}
+
 static void anx7447_tcpc_alert(int port)
 {
+	int alert;
+
+	tcpc_read16(port, TCPC_REG_ALERT, &alert);
+	if (alert & TCPC_REG_ALERT_VENDOR_DEF)
+		anx7447_vendor_defined_alert(port);
+
 	/* process and clear alert status */
 	tcpci_tcpc_alert(port);
 }
 
+#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
+static int anx7447_tcpc_enter_low_power_mode(int port)
+{
+	int rv;
+
+	/*
+	 * if anx7447 is in source mode, need to set Rp to default before
+	 * entering the low power mode.
+	 */
+	if (pd_get_dual_role(port) == PD_DRP_FORCE_SOURCE) {
+		rv = tcpc_write(
+			port, TCPC_REG_ROLE_CTRL,
+			TCPC_REG_ROLE_CTRL_SET(TYPEC_NO_DRP, TYPEC_RP_USB,
+					       TYPEC_CC_RP, TYPEC_CC_RP));
+		if (rv) {
+			return rv;
+		}
+	}
+
+	return tcpci_enter_low_power_mode(port);
+}
+#endif
+
+#ifdef CONFIG_USB_PD_FRS_TCPC
+static void anx7447_disable_frs_deferred(void)
+{
+	int i, val;
+
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		if (!anx_frs_dis[i])
+			continue;
+
+		anx_frs_dis[i] = false;
+		anx7447_reg_read(i, ANX7447_REG_ADDR_GPIO_CTRL_1, &val);
+		val &= ~ANX7447_ADDR_GPIO_CTRL_1_FRS_EN_DATA;
+		anx7447_reg_write(i, ANX7447_REG_ADDR_GPIO_CTRL_1, val);
+	}
+}
+DECLARE_DEFERRED(anx7447_disable_frs_deferred);
+
+static int anx7447_set_frs_enable(int port, int enable)
+{
+	int val;
+
+	RETURN_ERROR(tcpc_update8(port, ANX7447_REG_FRSWAP_CTRL,
+				  ANX7447_FRSWAP_DETECT_ENABLE,
+				  enable ? MASK_SET : MASK_CLR));
+
+	if (!enable) {
+		/*
+		 * b/223087277#comment52: delay to disable FRS output to the
+		 * PPC. Some PPCs need the FRS_EN pin to stay asserted until the
+		 * VBUS dropped to a threshold under 5V to successfully source.
+		 * However, on some hubs with a larger cap, the VBUS might take
+		 * more than 10 ms.  This workaround is to delay the FRS_EN
+		 * deassertion to PPC for 30 ms, which should be enough for
+		 * most cases.
+		 */
+		anx_frs_dis[port] = true;
+		hook_call_deferred(&anx7447_disable_frs_deferred_data,
+				   30 * MSEC);
+		return EC_SUCCESS;
+	}
+
+	RETURN_ERROR(
+		anx7447_reg_read(port, ANX7447_REG_ADDR_GPIO_CTRL_1, &val));
+	val |= ANX7447_ADDR_GPIO_CTRL_1_FRS_EN_DATA;
+	RETURN_ERROR(
+		anx7447_reg_write(port, ANX7447_REG_ADDR_GPIO_CTRL_1, val));
+	return EC_SUCCESS;
+}
+#endif /* CONFIG_USB_PD_FRS_TCPC */
+
 /*
  * timestamp of the next possible toggle to ensure the 2-ms spacing
  * between IRQ_HPD.
@@ -473,8 +574,7 @@ static void anx7447_tcpc_alert(int port)
 static uint64_t hpd_deadline[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 void anx7447_tcpc_update_hpd_status(const struct usb_mux *me,
-				    mux_state_t mux_state,
-				    bool *ack_required)
+				    mux_state_t mux_state, bool *ack_required)
 {
 	int reg = 0;
 	int port = me->usb_port;
@@ -528,15 +628,21 @@ static int anx7447_mux_init(const struct usb_mux *me)
 	int port = me->usb_port;
 	int i;
 	bool unused;
+	const uint16_t tcpc_i2c_addr =
+		I2C_STRIP_FLAGS(tcpc_config[me->usb_port].i2c_info.addr_flags);
+	const uint16_t mux_i2c_addr =
+		I2C_STRIP_FLAGS(usb_muxes[port].mux->i2c_addr_flags);
 
 	/*
 	 * find corresponding anx7447 SPI address according to
-	 * specified MUX address
+	 * specified MUX address from mux and tcpc i2c addr config.
 	 */
 	for (i = 0; i < ARRAY_SIZE(anx7447_i2c_addrs_flags); i++) {
-		if (I2C_STRIP_FLAGS(usb_muxes[port].i2c_addr_flags) ==
-		    I2C_STRIP_FLAGS(
-			    anx7447_i2c_addrs_flags[i].tcpc_addr_flags)) {
+		uint16_t i2c_addr_key = I2C_STRIP_FLAGS(
+			anx7447_i2c_addrs_flags[i].tcpc_addr_flags);
+
+		if (i2c_addr_key == tcpc_i2c_addr ||
+		    i2c_addr_key == mux_i2c_addr) {
 			anx[port].i2c_addr_flags =
 				anx7447_i2c_addrs_flags[i].spi_addr_flags;
 			break;
@@ -544,7 +650,7 @@ static int anx7447_mux_init(const struct usb_mux *me)
 	}
 	if (!I2C_STRIP_FLAGS(anx[port].i2c_addr_flags)) {
 		ccprintf("TCPC I2C addr 0x%x is invalid for ANX7447\n",
-			 I2C_STRIP_FLAGS(usb_muxes[port].i2c_addr_flags));
+			 I2C_STRIP_FLAGS(usb_muxes[port].mux->i2c_addr_flags));
 		return EC_ERROR_UNKNOWN;
 	}
 
@@ -578,8 +684,8 @@ static void anx7447_mux_safemode(const struct usb_mux *me, int on_off)
 		reg &= ~(ANX7447_REG_SAFE_MODE);
 
 	mux_write(me, ANX7447_REG_ANALOG_CTRL_9, reg);
-	CPRINTS("C%d set mux to safemode %s, reg = 0x%x",
-		me->usb_port, (on_off) ? "on" : "off", reg);
+	CPRINTS("C%d set mux to safemode %s, reg = 0x%x", me->usb_port,
+		(on_off) ? "on" : "off", reg);
 }
 
 static inline void anx7447_configure_aux_src(const struct usb_mux *me,
@@ -596,8 +702,8 @@ static inline void anx7447_configure_aux_src(const struct usb_mux *me,
 
 	mux_write(me, ANX7447_REG_ANALOG_CTRL_9, reg);
 
-	CPRINTS("C%d set aux_src to %s, reg = 0x%x",
-		me->usb_port, (on_off) ? "on" : "off", reg);
+	CPRINTS("C%d set aux_src to %s, reg = 0x%x", me->usb_port,
+		(on_off) ? "on" : "off", reg);
 }
 #endif
 
@@ -622,10 +728,14 @@ static int anx7447_mux_set(const struct usb_mux *me, mux_state_t mux_state,
 	/* This driver does not use host command ACKs */
 	*ack_required = false;
 
+	/* This driver treats safe mode as none */
+	if (mux_state == USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
+
 	cc_direction = mux_state & USB_PD_MUX_POLARITY_INVERTED;
 	mux_type = mux_state & USB_PD_MUX_DOCK;
-	CPRINTS("C%d mux_state = 0x%x, mux_type = 0x%x",
-		port, mux_state, mux_type);
+	CPRINTS("C%d mux_state = 0x%x, mux_type = 0x%x", port, mux_state,
+		mux_type);
 	if (cc_direction == 0) {
 		/* cc1 connection */
 		if (mux_type == USB_PD_MUX_DOCK) {
@@ -749,14 +859,10 @@ static int anx7447_set_cc(int port, int pull)
 }
 
 /* Override for tcpci_tcpm_set_polarity */
-static int anx7447_set_polarity(int port,
-				enum tcpc_cc_polarity polarity)
+static int anx7447_set_polarity(int port, enum tcpc_cc_polarity polarity)
 {
-	return tcpc_update8(port,
-			    TCPC_REG_TCPC_CTRL,
-			    TCPC_REG_TCPC_CTRL_SET(1),
-			    polarity_rm_dts(polarity)
-					? MASK_SET : MASK_CLR);
+	return tcpc_update8(port, TCPC_REG_TCPC_CTRL, TCPC_REG_TCPC_CTRL_SET(1),
+			    polarity_rm_dts(polarity) ? MASK_SET : MASK_CLR);
 }
 
 #ifdef CONFIG_CMD_TCPC_DUMP
@@ -826,6 +932,14 @@ const struct {
 		.name = "PAD_INTP_CTRL",
 		.addr = ANX7447_REG_PAD_INTP_CTRL,
 	},
+	{
+		.name = "OCM_MAIN_VERSION",
+		.addr = ANX7447_REG_OCM_MAIN_VERSION,
+	},
+	{
+		.name = "OCM_BUILD_VERSION",
+		.addr = ANX7447_REG_OCM_BUILD_VERSION,
+	},
 };
 
 /*
@@ -840,15 +954,15 @@ static void anx7447_dump_registers(int port)
 	for (i = 0; i < ARRAY_SIZE(anx7447_alt_regs); i++) {
 		anx7447_reg_read(port, anx7447_alt_regs[i].addr, &val);
 		ccprintf("  %-26s(ALT/0x%02x) =   0x%02x\n",
-				anx7447_alt_regs[i].name,
-				anx7447_alt_regs[i].addr, (uint8_t)val);
+			 anx7447_alt_regs[i].name, anx7447_alt_regs[i].addr,
+			 (uint8_t)val);
 		cflush();
 	}
 }
 #endif /* defined(CONFIG_CMD_TCPC_DUMP) */
 
 static int anx7447_get_chip_info(int port, int live,
-			struct ec_response_pd_chip_info_v1 *chip_info)
+				 struct ec_response_pd_chip_info_v1 *chip_info)
 {
 	int main_version = 0x0, build_version = 0x0;
 
@@ -892,6 +1006,15 @@ enum ec_error_list anx7447_set_bist_test_mode(const int port, const bool enable)
 	RETURN_ERROR(tcpc_write(port, ANX7447_REG_CC_DEBOUNCE_TIME,
 				enable ? 2 : 10));
 
+	anx7447_bist_test_mode[port] = enable;
+
+	return EC_SUCCESS;
+}
+
+enum ec_error_list anx7447_get_bist_test_mode(const int port, bool *enable)
+{
+	*enable = anx7447_bist_test_mode[port];
+
 	return EC_SUCCESS;
 }
 
@@ -903,40 +1026,44 @@ enum ec_error_list anx7447_set_bist_test_mode(const int port, const bool enable)
  * overrides for set_cc and set_polarity.
  */
 const struct tcpm_drv anx7447_tcpm_drv = {
-	.init			= &anx7447_init,
-	.release		= &anx7447_release,
-	.get_cc			= &tcpci_tcpm_get_cc,
+	.init = &anx7447_init,
+	.release = &anx7447_release,
+	.get_cc = &tcpci_tcpm_get_cc,
 #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	.check_vbus_level	= &tcpci_tcpm_check_vbus_level,
+	.check_vbus_level = &tcpci_tcpm_check_vbus_level,
 #endif
-	.get_vbus_voltage	= &anx7447_get_vbus_voltage,
-	.select_rp_value	= &tcpci_tcpm_select_rp_value,
-	.set_cc			= &anx7447_set_cc,
-	.set_polarity		= &anx7447_set_polarity,
+	.get_vbus_voltage = &anx7447_get_vbus_voltage,
+	.select_rp_value = &tcpci_tcpm_select_rp_value,
+	.set_cc = &anx7447_set_cc,
+	.set_polarity = &anx7447_set_polarity,
 #ifdef CONFIG_USB_PD_DECODE_SOP
-	.sop_prime_enable	= &tcpci_tcpm_sop_prime_enable,
+	.sop_prime_enable = &tcpci_tcpm_sop_prime_enable,
 #endif
-	.set_vconn		= &tcpci_tcpm_set_vconn,
-	.set_msg_header		= &tcpci_tcpm_set_msg_header,
-	.set_rx_enable		= &tcpci_tcpm_set_rx_enable,
-	.get_message_raw	= &tcpci_tcpm_get_message_raw,
-	.transmit		= &tcpci_tcpm_transmit,
-	.tcpc_alert		= &anx7447_tcpc_alert,
+	.set_vconn = &tcpci_tcpm_set_vconn,
+	.set_msg_header = &tcpci_tcpm_set_msg_header,
+	.set_rx_enable = &tcpci_tcpm_set_rx_enable,
+	.get_message_raw = &tcpci_tcpm_get_message_raw,
+	.transmit = &tcpci_tcpm_transmit,
+	.tcpc_alert = &anx7447_tcpc_alert,
 #ifdef CONFIG_USB_PD_DISCHARGE_TCPC
-	.tcpc_discharge_vbus	= &tcpci_tcpc_discharge_vbus,
+	.tcpc_discharge_vbus = &tcpci_tcpc_discharge_vbus,
 #endif
 #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-	.drp_toggle		= anx7447_tcpc_drp_toggle,
+	.drp_toggle = anx7447_tcpc_drp_toggle,
 #endif
-	.get_chip_info		= &anx7447_get_chip_info,
-	.set_snk_ctrl		= &tcpci_tcpm_set_snk_ctrl,
-	.set_src_ctrl		= &tcpci_tcpm_set_src_ctrl,
+	.get_chip_info = &anx7447_get_chip_info,
+	.set_snk_ctrl = &tcpci_tcpm_set_snk_ctrl,
+	.set_src_ctrl = &tcpci_tcpm_set_src_ctrl,
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	.enter_low_power_mode	= &tcpci_enter_low_power_mode,
+	.enter_low_power_mode = &anx7447_tcpc_enter_low_power_mode,
+#endif
+#ifdef CONFIG_USB_PD_FRS_TCPC
+	.set_frs_enable = &anx7447_set_frs_enable,
 #endif
-	.set_bist_test_mode	= &anx7447_set_bist_test_mode,
+	.set_bist_test_mode = &anx7447_set_bist_test_mode,
+	.get_bist_test_mode = &anx7447_get_bist_test_mode,
 #ifdef CONFIG_CMD_TCPC_DUMP
-	.dump_registers		= &anx7447_dump_registers,
+	.dump_registers = &anx7447_dump_registers,
 #endif
 };
 
diff --git a/driver/tcpm/anx7447.h b/driver/tcpm/anx7447.h
index 30396c26b3..42de7502f1 100644
--- a/driver/tcpm/anx7447.h
+++ b/driver/tcpm/anx7447.h
@@ -1,9 +1,10 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "usb_mux.h"
+#include "driver/tcpm/anx7447_public.h"
 
 /* USB Power delivery port management */
 
@@ -11,132 +12,153 @@
 #define __CROS_EC_USB_PD_TCPM_ANX7447_H
 
 /* Registers: TCPC address used */
-#define ANX7447_REG_TCPC_SWITCH_0	0xB4
-#define ANX7447_REG_TCPC_SWITCH_1	0xB5
-#define ANX7447_REG_TCPC_AUX_SWITCH	0xB6
-#define VCONN_VOLTAGE_ALARM_HI_CFG	0xB7
+#define ANX7447_REG_TCPC_SWITCH_0 0xB4
+#define ANX7447_REG_TCPC_SWITCH_1 0xB5
+#define ANX7447_REG_TCPC_AUX_SWITCH 0xB6
+#define VCONN_VOLTAGE_ALARM_HI_CFG 0xB7
 
-#define ANX7447_REG_INTR_ALERT_MASK_0	0xC9
+#define ANX7447_REG_INTR_ALERT_MASK_0 0xC9
 
-#define ANX7447_REG_TCPC_CTRL_2		0xCD
-#define ANX7447_REG_ENABLE_VBUS_PROTECT	0x20
+#define ANX7447_REG_TCPC_CTRL_2 0xCD
+#define ANX7447_REG_ENABLE_VBUS_PROTECT 0x20
 
-#define ANX7447_REG_ADC_CTRL_1		0xBF
-#define ANX7447_REG_ADCFSM_EN		0x20
+#define ANX7447_REG_ADC_CTRL_1 0xBF
+#define ANX7447_REG_ADCFSM_EN 0x20
 
 /* Registers: SPI address used */
-#define ANX7447_REG_INTP_SOURCE_0	0x67
-
-#define ANX7447_REG_HPD_CTRL_0		0x7E
-#define ANX7447_REG_HPD_MODE		0x01
-#define ANX7447_REG_HPD_OUT		0x02
-#define ANX7447_REG_HPD_IRQ0		0x04
-#define ANX7447_REG_HPD_PLUG		0x08
-#define ANX7447_REG_HPD_UNPLUG		0x10
-
-#define ANX7447_REG_HPD_DEGLITCH_H	0x80
-#define ANX7447_REG_HPD_DETECT		0x80
-#define ANX7447_REG_HPD_OEN		0x40
-
-#define ANX7447_REG_PAD_INTP_CTRL	0x85
-
-#define ANX7447_REG_INTP_MASK_0		0x86
-
-#define ANX7447_REG_TCPC_CTRL_1		0x9D
-#define CC_DEBOUNCE_MS			BIT(3)
-#define CC_DEBOUNCE_TIME_HI_BIT		BIT(0)
-#define ANX7447_REG_INTP_CTRL_0		0x9E
-#define ANX7447_REG_CC_DEBOUNCE_TIME	0x9F
-
-#define ANX7447_REG_ANALOG_CTRL_8	0xA8
-#define ANX7447_REG_VCONN_OCP_MASK	0x0C
-#define ANX7447_REG_VCONN_OCP_240mA	0x00
-#define ANX7447_REG_VCONN_OCP_310mA	0x04
-#define ANX7447_REG_VCONN_OCP_370mA	0x08
-#define ANX7447_REG_VCONN_OCP_440mA	0x0C
-
-#define ANX7447_REG_ANALOG_CTRL_10	0xAA
-#define ANX7447_REG_CABLE_DET_DIG	0x40
-
-#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_MASK	0x38
-#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_19US	0x00
-#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_38US	0x08
-#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_76US    0x10
-#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_152US   0x18
-#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_303US   0x20
-#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_607US	0x28
-#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_1210US	0x30
-#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_2430US	0x38
-
-#define ANX7447_REG_ANALOG_CTRL_9	0xA9
-#define ANX7447_REG_SAFE_MODE		0x80
-#define ANX7447_REG_R_AUX_RES_PULL_SRC	0x20
+#define ANX7447_REG_INTP_SOURCE_0 0x67
+
+#define ANX7447_REG_HPD_CTRL_0 0x7E
+#define ANX7447_REG_HPD_MODE 0x01
+#define ANX7447_REG_HPD_OUT 0x02
+#define ANX7447_REG_HPD_IRQ0 0x04
+#define ANX7447_REG_HPD_PLUG 0x08
+#define ANX7447_REG_HPD_UNPLUG 0x10
+
+#define ANX7447_REG_HPD_DEGLITCH_H 0x80
+#define ANX7447_REG_HPD_DETECT 0x80
+#define ANX7447_REG_HPD_OEN 0x40
+
+#define ANX7447_REG_PAD_INTP_CTRL 0x85
+
+#define ANX7447_REG_INTP_MASK_0 0x86
+
+#define ANX7447_REG_ADDR_GPIO_CTRL_1 0x89
+
+#define ANX7447_REG_TCPC_CTRL_1 0x9D
+#define CC_DEBOUNCE_MS BIT(3)
+#define CC_DEBOUNCE_TIME_HI_BIT BIT(0)
+#define ANX7447_REG_INTP_CTRL_0 0x9E
+#define ANX7447_REG_CC_DEBOUNCE_TIME 0x9F
+
+#define ANX7447_REG_ANALOG_CTRL_8 0xA8
+#define ANX7447_REG_VCONN_OCP_MASK 0x0C
+#define ANX7447_REG_VCONN_OCP_240mA 0x00
+#define ANX7447_REG_VCONN_OCP_310mA 0x04
+#define ANX7447_REG_VCONN_OCP_370mA 0x08
+#define ANX7447_REG_VCONN_OCP_440mA 0x0C
+
+#define ANX7447_REG_ANALOG_CTRL_10 0xAA
+#define ANX7447_REG_CABLE_DET_DIG 0x40
+
+#define ANX7447_REG_FRSWAP_CTRL 0xAB
+
+#define ANX7447_REG_T_CHK_VBUS_TIMER 0xBB
+
+#define ANX7447_REG_VD_ALERT_MASK 0xC7
+#define ANX7447_REG_VD_ALERT 0xC8
+
+#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_MASK 0x38
+#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_19US 0x00
+#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_38US 0x08
+#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_76US 0x10
+#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_152US 0x18
+#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_303US 0x20
+#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_607US 0x28
+#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_1210US 0x30
+#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_2430US 0x38
+
+#define ANX7447_REG_ANALOG_CTRL_9 0xA9
+#define ANX7447_REG_SAFE_MODE 0x80
+#define ANX7447_REG_R_AUX_RES_PULL_SRC 0x20
+
+/* FRSWAP_CTRL bit definitions */
+#define ANX7447_FR_SWAP BIT(7)
+#define ANX7447_FR_SWAP_EN BIT(6)
+#define ANX7447_R_FRSWAP_CONTROL_SELECT BIT(3)
+#define ANX7447_R_SIGNAL_FRSWAP BIT(2)
+#define ANX7447_TRANSMIT_FRSWAP_SIGNAL BIT(1)
+#define ANX7447_FRSWAP_DETECT_ENABLE BIT(0)
+
+/* ADDR_GPIO_CTRL_1 bit definitions */
+#define ANX7447_ADDR_GPIO_CTRL_1_FRS_EN_DATA BIT(3)
+#define ANX7447_ADDR_GPIO_CTRL_1_FRS_EN_OEN BIT(2)
+
+/* VD_ALERT and VD_ALERT_MASK  bit definitions */
+#define ANX7447_TIMER_1_DONE BIT(7)
+#define ANX7447_TIMER_0_DONE BIT(6)
+#define ANX7447_SOFT_INTP BIT(5)
+#define ANX7447_VCONN_VOLTAGE_ALARM_LO BIT(4)
+#define ANX7447_VCONN_VOLTAGE_ALARM_HI BIT(3)
+#define ANX7447_VCONN_OCP_OCCURRED BIT(2)
+#define ANX7447_VBUS_OCP_OCCURRED BIT(1)
+#define ANX7447_FRSWAP_SIGNAL_DETECTED BIT(0)
 
 /*
  * This section of defines are only required to support the config option
  * CONFIG_USB_PD_TCPM_ANX7447_OCM_ERASE_COMMAND.
  */
 /* SPI registers used for OCM flash operations */
-#define ANX7447_DELAY_IN_US		(20*1000)
-
-#define ANX7447_REG_R_RAM_CTRL			0x05
-#define ANX7447_REG_R_FLASH_RW_CTRL		0x30
-#define ANX7447_REG_R_FLASH_STATUS_0		0x31
-#define ANX7447_REG_FLASH_INST_TYPE		0x33
-#define ANX7447_REG_FLASH_ERASE_TYPE		0x34
-#define ANX7447_REG_OCM_CTRL_0			0x6E
-#define ANX7447_REG_ADDR_GPIO_CTRL_0		0x88
-#define ANX7447_REG_OCM_MAIN_VERSION		0xB4
-#define ANX7447_REG_OCM_BUILD_VERSION		0xB5
+#define ANX7447_DELAY_IN_US (20 * 1000)
+
+#define ANX7447_REG_R_RAM_CTRL 0x05
+#define ANX7447_REG_R_FLASH_RW_CTRL 0x30
+#define ANX7447_REG_R_FLASH_STATUS_0 0x31
+#define ANX7447_REG_FLASH_INST_TYPE 0x33
+#define ANX7447_REG_FLASH_ERASE_TYPE 0x34
+#define ANX7447_REG_OCM_CTRL_0 0x6E
+#define ANX7447_REG_ADDR_GPIO_CTRL_0 0x88
+#define ANX7447_REG_OCM_MAIN_VERSION 0xB4
+#define ANX7447_REG_OCM_BUILD_VERSION 0xB5
 
 /* R_RAM_CTRL bit definitions */
-#define ANX7447_R_RAM_CTRL_FLASH_DONE			(1<<7)
+#define ANX7447_R_RAM_CTRL_FLASH_DONE (1 << 7)
 
 /* R_FLASH_RW_CTRL bit definitions */
-#define ANX7447_R_FLASH_RW_CTRL_GENERAL_INST_EN		(1<<6)
-#define ANX7447_R_FLASH_RW_CTRL_FLASH_ERASE_EN		(1<<5)
-#define ANX7447_R_FLASH_RW_CTRL_WRITE_STATUS_EN		(1<<2)
-#define ANX7447_R_FLASH_RW_CTRL_FLASH_READ		(1<<1)
-#define ANX7447_R_FLASH_RW_CTRL_FLASH_WRITE		(1<<0)
+#define ANX7447_R_FLASH_RW_CTRL_GENERAL_INST_EN (1 << 6)
+#define ANX7447_R_FLASH_RW_CTRL_FLASH_ERASE_EN (1 << 5)
+#define ANX7447_R_FLASH_RW_CTRL_WRITE_STATUS_EN (1 << 2)
+#define ANX7447_R_FLASH_RW_CTRL_FLASH_READ (1 << 1)
+#define ANX7447_R_FLASH_RW_CTRL_FLASH_WRITE (1 << 0)
 
 /* R_FLASH_STATUS_0 definitions */
-#define ANX7447_FLASH_STATUS_SPI_STATUS_0		0x43
+#define ANX7447_FLASH_STATUS_SPI_STATUS_0 0x43
 
 /* FLASH_ERASE_TYPE bit definitions */
-#define ANX7447_FLASH_INST_TYPE_WRITEENABLE		0x06
-#define ANX7447_FLASH_ERASE_TYPE_CHIPERASE		0x60
+#define ANX7447_FLASH_INST_TYPE_WRITEENABLE 0x06
+#define ANX7447_FLASH_ERASE_TYPE_CHIPERASE 0x60
 
 /* OCM_CTRL_0 bit definitions */
-#define ANX7447_OCM_CTRL_OCM_RESET			(1<<6)
+#define ANX7447_OCM_CTRL_OCM_RESET (1 << 6)
 
 /* ADDR_GPIO_CTRL_0 bit definitions */
-#define ANX7447_ADDR_GPIO_CTRL_0_SPI_WP			(1<<7)
-#define ANX7447_ADDR_GPIO_CTRL_0_SPI_CLK_ENABLE		(1<<6)
+#define ANX7447_ADDR_GPIO_CTRL_0_SPI_WP (1 << 7)
+#define ANX7447_ADDR_GPIO_CTRL_0_SPI_CLK_ENABLE (1 << 6)
 /* End of defines used for CONFIG_USB_PD_TCPM_ANX7447_OCM_ERASE_COMMAND */
 
 struct anx7447_i2c_addr {
-	uint16_t	tcpc_addr_flags;
-	uint16_t	spi_addr_flags;
+	uint16_t tcpc_addr_flags;
+	uint16_t spi_addr_flags;
 };
 
-#define AN7447_TCPC0_I2C_ADDR_FLAGS	0x2C
-#define AN7447_TCPC1_I2C_ADDR_FLAGS	0x2B
-#define AN7447_TCPC2_I2C_ADDR_FLAGS	0x2A
-#define AN7447_TCPC3_I2C_ADDR_FLAGS	0x29
-
-#define AN7447_SPI0_I2C_ADDR_FLAGS	0x3F
-#define AN7447_SPI1_I2C_ADDR_FLAGS	0x37
-#define AN7447_SPI2_I2C_ADDR_FLAGS	0x32
-#define AN7447_SPI3_I2C_ADDR_FLAGS	0x31
-
 /*
  * Time TEST_R must be held high for a reset
  */
-#define ANX74XX_RESET_HOLD_MS	1
+#define ANX74XX_RESET_HOLD_MS 1
 /*
  * Time after TEST_R reset to wait for eFuse loading
  */
-#define ANX74XX_RESET_FINISH_MS	2
+#define ANX74XX_RESET_FINISH_MS 2
 
 int anx7447_set_power_supply_ready(int port);
 int anx7447_power_supply_reset(int port);
@@ -145,12 +167,9 @@ int anx7447_board_charging_enable(int port, int enable);
 void anx7447_hpd_mode_en(int port);
 void anx7447_hpd_output_en(int port);
 
-extern const struct tcpm_drv anx7447_tcpm_drv;
-extern const struct usb_mux_driver anx7447_usb_mux_driver;
 void anx7447_tcpc_clear_hpd_status(int port);
 void anx7447_tcpc_update_hpd_status(const struct usb_mux *me,
-				    mux_state_t mux_state,
-				    bool *ack_required);
+				    mux_state_t mux_state, bool *ack_required);
 
 /**
  * Erase OCM flash if it's not empty
diff --git a/driver/tcpm/anx74xx.c b/driver/tcpm/anx74xx.c
index 1fc813c448..64a9271f1c 100644
--- a/driver/tcpm/anx74xx.c
+++ b/driver/tcpm/anx74xx.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -30,23 +30,24 @@
 #error "Please undefine PD 3.0.  See b/159253723 for details"
 #endif
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 struct anx_state {
-	int	polarity;
-	int	vconn_en;
-	int	mux_state;
+	int polarity;
+	int vconn_en;
+	int mux_state;
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	int	prev_mode;
+	int prev_mode;
 #endif
 };
-#define clear_recvd_msg_int(port) do {\
-		int reg, rv; \
+#define clear_recvd_msg_int(port)                                      \
+	do {                                                           \
+		int reg, rv;                                           \
 		rv = tcpc_read(port, ANX74XX_REG_RECVD_MSG_INT, &reg); \
-		if (!rv) \
-			tcpc_write(port, ANX74XX_REG_RECVD_MSG_INT, \
-			reg | 0x01); \
+		if (!rv)                                               \
+			tcpc_write(port, ANX74XX_REG_RECVD_MSG_INT,    \
+				   reg | 0x01);                        \
 	} while (0)
 
 static struct anx_state anx[CONFIG_USB_PD_PORT_MAX_COUNT];
@@ -233,8 +234,7 @@ static void anx74xx_tcpc_discharge_vbus(int port, int enable)
 static uint64_t hpd_deadline[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 void anx74xx_tcpc_update_hpd_status(const struct usb_mux *me,
-				    mux_state_t mux_state,
-				    bool *ack_required)
+				    mux_state_t mux_state, bool *ack_required)
 {
 	int reg;
 	int port = me->usb_port;
@@ -292,37 +292,35 @@ static int anx74xx_tcpm_mux_init(const struct usb_mux *me)
 static int anx74xx_tcpm_mux_enter_safe_mode(int port)
 {
 	int reg;
-	const struct usb_mux *me = &usb_muxes[port];
+	const struct usb_mux *me = usb_muxes[port].mux;
 
 	if (mux_read(me, ANX74XX_REG_ANALOG_CTRL_2, &reg))
 		return EC_ERROR_UNKNOWN;
-	if (mux_write(me, ANX74XX_REG_ANALOG_CTRL_2, reg |
-		       ANX74XX_REG_MODE_TRANS))
+	if (mux_write(me, ANX74XX_REG_ANALOG_CTRL_2,
+		      reg | ANX74XX_REG_MODE_TRANS))
 		return EC_ERROR_UNKNOWN;
 
-
 	return EC_SUCCESS;
 }
 
 static int anx74xx_tcpm_mux_exit_safe_mode(int port)
 {
 	int reg;
-	const struct usb_mux *me = &usb_muxes[port];
+	const struct usb_mux *me = usb_muxes[port].mux;
 
 	if (mux_read(me, ANX74XX_REG_ANALOG_CTRL_2, &reg))
 		return EC_ERROR_UNKNOWN;
-	if (mux_write(me, ANX74XX_REG_ANALOG_CTRL_2, reg &
-		       ~ANX74XX_REG_MODE_TRANS))
+	if (mux_write(me, ANX74XX_REG_ANALOG_CTRL_2,
+		      reg & ~ANX74XX_REG_MODE_TRANS))
 		return EC_ERROR_UNKNOWN;
 
-
 	return EC_SUCCESS;
 }
 
 static int anx74xx_tcpm_mux_exit(int port)
 {
 	int reg;
-	const struct usb_mux *me = &usb_muxes[port];
+	const struct usb_mux *me = usb_muxes[port].mux;
 
 	/*
 	 * Safe mode must be entered before any changes are made to the mux
@@ -357,13 +355,12 @@ static int anx74xx_tcpm_mux_exit(int port)
 	return EC_SUCCESS;
 }
 
-
 static int anx74xx_mux_aux_to_sbu(int port, int polarity, int enabled)
 {
 	int reg;
 	const int aux_mask = ANX74XX_REG_AUX_SWAP_SET_CC2 |
-		ANX74XX_REG_AUX_SWAP_SET_CC1;
-	const struct usb_mux *me = &usb_muxes[port];
+			     ANX74XX_REG_AUX_SWAP_SET_CC1;
+	const struct usb_mux *me = usb_muxes[port].mux;
 
 	/*
 	 * Get the current value of analog_ctrl_2 register. Note, that safe mode
@@ -391,8 +388,7 @@ static int anx74xx_mux_aux_to_sbu(int port, int polarity, int enabled)
 	return EC_SUCCESS;
 }
 
-static int anx74xx_tcpm_mux_set(const struct usb_mux *me,
-				mux_state_t mux_state,
+static int anx74xx_tcpm_mux_set(const struct usb_mux *me, mux_state_t mux_state,
 				bool *ack_required)
 {
 	int ctrl5;
@@ -403,6 +399,10 @@ static int anx74xx_tcpm_mux_set(const struct usb_mux *me,
 	/* This driver does not use host command ACKs */
 	*ack_required = false;
 
+	/* This driver treats safe mode as none */
+	if (mux_state == USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
+
 	if (!(mux_state & ~USB_PD_MUX_POLARITY_INVERTED)) {
 		anx[port].mux_state = mux_state;
 		return anx74xx_tcpm_mux_exit(port);
@@ -448,7 +448,7 @@ static int anx74xx_tcpm_mux_set(const struct usb_mux *me,
 	} else if (!mux_state) {
 		return anx74xx_tcpm_mux_exit(port);
 	} else {
-		return  EC_ERROR_UNIMPLEMENTED;
+		return EC_ERROR_UNIMPLEMENTED;
 	}
 
 	/*
@@ -504,8 +504,7 @@ static int anx74xx_init_analog(int port)
 	/* Analog settings for chip */
 	rv |= tcpc_write(port, ANX74XX_REG_HPD_CONTROL,
 			 ANX74XX_REG_HPD_OP_MODE);
-	rv |= tcpc_write(port, ANX74XX_REG_HPD_CTRL_0,
-			 ANX74XX_REG_HPD_DEFAULT);
+	rv |= tcpc_write(port, ANX74XX_REG_HPD_CTRL_0, ANX74XX_REG_HPD_DEFAULT);
 	if (rv)
 		return rv;
 	rv = tcpc_read(port, ANX74XX_REG_GPIO_CTRL_4_5, &reg);
@@ -526,9 +525,7 @@ static int anx74xx_init_analog(int port)
 }
 
 static int anx74xx_send_message(int port, uint16_t header,
-				const uint32_t *payload,
-				int type,
-				uint8_t len)
+				const uint32_t *payload, int type, uint8_t len)
 {
 	int reg, rv = EC_SUCCESS;
 	uint8_t *buf = NULL;
@@ -537,12 +534,12 @@ static int anx74xx_send_message(int port, uint16_t header,
 	/* Soft Reset Message type = 1101 and Number of Data Object = 0 */
 	if ((header & 0x700f) == 0x000d) {
 		/*
-		* When sending soft reset,
-		* the Rx buffer of ANX3429 shall be clear
-		*/
+		 * When sending soft reset,
+		 * the Rx buffer of ANX3429 shall be clear
+		 */
 		rv = tcpc_read(port, ANX74XX_REG_CTRL_FW, &reg);
-		rv |= tcpc_write(
-			port, ANX74XX_REG_CTRL_FW, reg | CLEAR_RX_BUFFER);
+		rv |= tcpc_write(port, ANX74XX_REG_CTRL_FW,
+				 reg | CLEAR_RX_BUFFER);
 		if (rv)
 			return EC_ERROR_UNKNOWN;
 		tcpc_write(port, ANX74XX_REG_RECVD_MSG_INT, 0xFF);
@@ -574,7 +571,8 @@ static int anx74xx_send_message(int port, uint16_t header,
 						*buf);
 			else
 				rv = tcpc_write(port,
-					ANX74XX_REG_TX_START_ADDR_1 + i - 18,
+						ANX74XX_REG_TX_START_ADDR_1 +
+							i - 18,
 						*buf);
 			if (rv) {
 				num_retry++;
@@ -607,15 +605,13 @@ static int anx74xx_send_message(int port, uint16_t header,
 	return rv;
 }
 
-static int anx74xx_read_pd_obj(int port,
-				uint8_t *buf,
-				int plen)
+static int anx74xx_read_pd_obj(int port, uint8_t *buf, int plen)
 {
 	int rv = EC_SUCCESS, i;
 	int reg, addr = ANX74XX_REG_PD_RX_DATA_OBJ;
 
 	/* Read PD data objects from ANX */
-	for (i = 0; i < plen ; i++) {
+	for (i = 0; i < plen; i++) {
 		/* Register sequence changes for last two bytes, if
 		 * plen is greater than 26
 		 */
@@ -664,7 +660,7 @@ static int anx74xx_check_cc_type(int cc_reg)
 }
 
 static int anx74xx_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2)
+			       enum tcpc_cc_voltage_status *cc2)
 {
 	int rv = EC_SUCCESS;
 	int reg = 0;
@@ -729,7 +725,6 @@ static int anx74xx_tcpm_select_rp_value(int port, int rp)
 	return EC_SUCCESS;
 }
 
-
 static int anx74xx_cc_software_ctrl(int port, int enable)
 {
 	int rv;
@@ -760,7 +755,7 @@ static int anx74xx_tcpm_set_cc(int port, int pull)
 
 	switch (pull) {
 	case TYPEC_CC_RP:
-	/* Enable Rp */
+		/* Enable Rp */
 		rv |= tcpc_read(port, ANX74XX_REG_ANALOG_STATUS, &reg);
 		if (rv)
 			return EC_ERROR_UNKNOWN;
@@ -768,7 +763,7 @@ static int anx74xx_tcpm_set_cc(int port, int pull)
 		rv |= tcpc_write(port, ANX74XX_REG_ANALOG_STATUS, reg);
 		break;
 	case TYPEC_CC_RD:
-	/* Enable Rd */
+		/* Enable Rd */
 		rv |= tcpc_read(port, ANX74XX_REG_ANALOG_STATUS, &reg);
 		if (rv)
 			return EC_ERROR_UNKNOWN;
@@ -786,7 +781,7 @@ static int anx74xx_tcpm_set_cc(int port, int pull)
 static int anx74xx_tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity)
 {
 	int reg, mux_state, rv = EC_SUCCESS;
-	const struct usb_mux *me = &usb_muxes[port];
+	const struct usb_mux *me = usb_muxes[port].mux;
 	bool unused;
 
 	rv |= tcpc_read(port, ANX74XX_REG_CC_SOFTWARE_CTRL, &reg);
@@ -835,7 +830,7 @@ static int anx74xx_tcpm_set_vconn(int port, int enable)
 	if (reg & ANX74XX_REG_REPLY_SOP_EN) {
 		if (enable) {
 			reg |= ANX74XX_REG_REPLY_SOP_1_EN |
-				ANX74XX_REG_REPLY_SOP_2_EN;
+			       ANX74XX_REG_REPLY_SOP_2_EN;
 		} else {
 			reg &= ~(ANX74XX_REG_REPLY_SOP_1_EN |
 				 ANX74XX_REG_REPLY_SOP_2_EN);
@@ -850,7 +845,8 @@ static int anx74xx_tcpm_set_vconn(int port, int enable)
 static int anx74xx_tcpm_set_msg_header(int port, int power_role, int data_role)
 {
 	return tcpc_write(port, ANX74XX_REG_TX_AUTO_GOODCRC_1,
-		  ANX74XX_REG_AUTO_GOODCRC_SET(!!data_role, !!power_role));
+			  ANX74XX_REG_AUTO_GOODCRC_SET(!!data_role,
+						       !!power_role));
 }
 
 static int anx74xx_tcpm_set_rx_enable(int port, int enable)
@@ -917,8 +913,7 @@ static int anx74xx_tcpm_get_message_raw(int port, uint32_t *payload, int *head)
 }
 
 static int anx74xx_tcpm_transmit(int port, enum tcpci_msg_type type,
-		  uint16_t header,
-		  const uint32_t *data)
+				 uint16_t header, const uint32_t *data)
 {
 	uint8_t len = 0;
 	int ret = 0, reg = 0;
@@ -929,37 +924,36 @@ static int anx74xx_tcpm_transmit(int port, enum tcpci_msg_type type,
 	case TCPCI_MSG_SOP_PRIME:
 	case TCPCI_MSG_SOP_PRIME_PRIME:
 		len = PD_HEADER_CNT(header) * 4 + 2;
-		ret = anx74xx_send_message(port, header,
-						  data, type, len);
+		ret = anx74xx_send_message(port, header, data, type, len);
 		break;
 	case TCPCI_MSG_TX_HARD_RESET:
-	/* Request HARD RESET */
+		/* Request HARD RESET */
 		tcpc_read(port, ANX74XX_REG_TX_CTRL_1, &reg);
 		reg |= ANX74XX_REG_TX_HARD_RESET_REQ;
 		ret = tcpc_write(port, ANX74XX_REG_TX_CTRL_1, reg);
-	/*After Hard Reset, TCPM shall disable goodCRC*/
+		/*After Hard Reset, TCPM shall disable goodCRC*/
 		anx74xx_tcpm_set_auto_good_crc(port, 0);
 		break;
 	case TCPCI_MSG_CABLE_RESET:
-	/* Request CABLE RESET */
+		/* Request CABLE RESET */
 		tcpc_read(port, ANX74XX_REG_TX_CTRL_1, &reg);
 		reg |= ANX74XX_REG_TX_CABLE_RESET_REQ;
 		ret = tcpc_write(port, ANX74XX_REG_TX_CTRL_1, reg);
 		break;
 	case TCPCI_MSG_TX_BIST_MODE_2:
-	/* Request BIST MODE 2 */
-		reg = ANX74XX_REG_TX_BIST_START
-				| ANX74XX_REG_TX_BIXT_FOREVER | (0x02 << 4);
+		/* Request BIST MODE 2 */
+		reg = ANX74XX_REG_TX_BIST_START | ANX74XX_REG_TX_BIXT_FOREVER |
+		      (0x02 << 4);
 		ret = tcpc_write(port, ANX74XX_REG_TX_BIST_CTRL, reg);
 		msleep(1);
 		ret = tcpc_write(port, ANX74XX_REG_TX_BIST_CTRL,
-					reg | ANX74XX_REG_TX_BIST_ENABLE);
+				 reg | ANX74XX_REG_TX_BIST_ENABLE);
 		msleep(30);
 		tcpc_read(port, ANX74XX_REG_TX_BIST_CTRL, &reg);
 		ret = tcpc_write(port, ANX74XX_REG_TX_BIST_CTRL,
-					reg | ANX74XX_REG_TX_BIST_STOP);
+				 reg | ANX74XX_REG_TX_BIST_STOP);
 		ret = tcpc_write(port, ANX74XX_REG_TX_BIST_CTRL,
-					reg & (~ANX74XX_REG_TX_BIST_STOP));
+				 reg & (~ANX74XX_REG_TX_BIST_STOP));
 		ret = tcpc_write(port, ANX74XX_REG_TX_BIST_CTRL, 0);
 		break;
 	default:
@@ -1006,7 +1000,8 @@ void anx74xx_tcpc_alert(int port)
 		/* Ensure we don't loop endlessly */
 		if (failed_attempts >= MAX_ALLOW_FAILED_RX_READS) {
 			CPRINTF("C%d Cannot consume RX buffer after %d failed "
-				"attempts!", port, failed_attempts);
+				"attempts!",
+				port, failed_attempts);
 			/*
 			 * The port is in a bad state, we don't want to consume
 			 * all EC resources so suspend the port for a little
@@ -1084,7 +1079,8 @@ static int anx74xx_tcpm_init(int port)
 
 	/* Initialize interrupt polarity */
 	reg = tcpc_config[port].flags & TCPC_FLAGS_ALERT_ACTIVE_HIGH ?
-		ANX74XX_REG_IRQ_POL_HIGH : ANX74XX_REG_IRQ_POL_LOW;
+		      ANX74XX_REG_IRQ_POL_HIGH :
+		      ANX74XX_REG_IRQ_POL_LOW;
 	rv |= tcpc_write(port, ANX74XX_REG_IRQ_STATUS, reg);
 
 	/* unmask interrupts */
@@ -1131,7 +1127,7 @@ static int anx74xx_tcpm_init(int port)
 }
 
 static int anx74xx_get_chip_info(int port, int live,
-			struct ec_response_pd_chip_info_v1 *chip_info)
+				 struct ec_response_pd_chip_info_v1 *chip_info)
 {
 	int rv = tcpci_get_chip_info(port, live, chip_info);
 	int val;
@@ -1171,34 +1167,34 @@ static int anx74xx_tcpm_release(int port)
 }
 
 const struct tcpm_drv anx74xx_tcpm_drv = {
-	.init			= &anx74xx_tcpm_init,
-	.release		= &anx74xx_tcpm_release,
-	.get_cc			= &anx74xx_tcpm_get_cc,
+	.init = &anx74xx_tcpm_init,
+	.release = &anx74xx_tcpm_release,
+	.get_cc = &anx74xx_tcpm_get_cc,
 #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	.check_vbus_level	= &anx74xx_tcpm_check_vbus_level,
+	.check_vbus_level = &anx74xx_tcpm_check_vbus_level,
 #endif
-	.select_rp_value	= &anx74xx_tcpm_select_rp_value,
-	.set_cc			= &anx74xx_tcpm_set_cc,
-	.set_polarity		= &anx74xx_tcpm_set_polarity,
+	.select_rp_value = &anx74xx_tcpm_select_rp_value,
+	.set_cc = &anx74xx_tcpm_set_cc,
+	.set_polarity = &anx74xx_tcpm_set_polarity,
 #ifdef CONFIG_USB_PD_DECODE_SOP
-	.sop_prime_enable	= &tcpci_tcpm_sop_prime_enable,
+	.sop_prime_enable = &tcpci_tcpm_sop_prime_enable,
 #endif
-	.set_vconn		= &anx74xx_tcpm_set_vconn,
-	.set_msg_header		= &anx74xx_tcpm_set_msg_header,
-	.set_rx_enable		= &anx74xx_tcpm_set_rx_enable,
-	.get_message_raw	= &anx74xx_tcpm_get_message_raw,
-	.transmit		= &anx74xx_tcpm_transmit,
-	.tcpc_alert		= &anx74xx_tcpc_alert,
+	.set_vconn = &anx74xx_tcpm_set_vconn,
+	.set_msg_header = &anx74xx_tcpm_set_msg_header,
+	.set_rx_enable = &anx74xx_tcpm_set_rx_enable,
+	.get_message_raw = &anx74xx_tcpm_get_message_raw,
+	.transmit = &anx74xx_tcpm_transmit,
+	.tcpc_alert = &anx74xx_tcpc_alert,
 #ifdef CONFIG_USB_PD_DISCHARGE_TCPC
-	.tcpc_discharge_vbus	= &anx74xx_tcpc_discharge_vbus,
+	.tcpc_discharge_vbus = &anx74xx_tcpc_discharge_vbus,
 #endif
-	.get_chip_info		= &anx74xx_get_chip_info,
+	.get_chip_info = &anx74xx_get_chip_info,
 #if defined(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE) && \
-		defined(CONFIG_USB_PD_TCPC_LOW_POWER)
-	.drp_toggle		= &anx74xx_tcpc_drp_toggle,
-	.enter_low_power_mode	= &anx74xx_enter_low_power_mode,
+	defined(CONFIG_USB_PD_TCPC_LOW_POWER)
+	.drp_toggle = &anx74xx_tcpc_drp_toggle,
+	.enter_low_power_mode = &anx74xx_enter_low_power_mode,
 #endif
-	.set_bist_test_mode	= &tcpci_set_bist_test_mode,
+	.set_bist_test_mode = &tcpci_set_bist_test_mode,
 };
 
 #ifdef CONFIG_CMD_I2C_STRESS_TEST_TCPC
diff --git a/driver/tcpm/anx74xx.h b/driver/tcpm/anx74xx.h
index 19ac3e304f..e814d85371 100644
--- a/driver/tcpm/anx74xx.h
+++ b/driver/tcpm/anx74xx.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -18,42 +18,42 @@
 #define ANX74XX_I2C_ADDR3_FLAGS 0x3E
 #define ANX74XX_I2C_ADDR4_FLAGS 0x40
 
-#define ANX74XX_REG_IRQ_POL_LOW		0x00
-#define ANX74XX_REG_IRQ_POL_HIGH		0x02
+#define ANX74XX_REG_IRQ_POL_LOW 0x00
+#define ANX74XX_REG_IRQ_POL_HIGH 0x02
 
-#define ANX74XX_REG_VENDOR_ID_L         0x00
-#define ANX74XX_REG_VENDOR_ID_H         0x01
-#define ANX74XX_VENDOR_ID               0xAAAA
+#define ANX74XX_REG_VENDOR_ID_L 0x00
+#define ANX74XX_REG_VENDOR_ID_H 0x01
+#define ANX74XX_VENDOR_ID 0xAAAA
 
 /* ANX F/W version：0x50:0x44 which contains otp firmware version */
-#define ANX74XX_REG_FW_VERSION          0x44
+#define ANX74XX_REG_FW_VERSION 0x44
 
-#define ANX74XX_REG_IRQ_STATUS		0x53
+#define ANX74XX_REG_IRQ_STATUS 0x53
 
-#define ANX74XX_REG_INTP_VCONN_CTRL	0x33
-#define ANX74XX_REG_VCONN_DISABLE		0x0f
-#define ANX74XX_REG_VCONN_1_ENABLE		BIT(4)
-#define ANX74XX_REG_VCONN_2_ENABLE		BIT(5)
-#define ANX74XX_REG_R_INTERRUPT_OPEN_DRAIN	BIT(2)
+#define ANX74XX_REG_INTP_VCONN_CTRL 0x33
+#define ANX74XX_REG_VCONN_DISABLE 0x0f
+#define ANX74XX_REG_VCONN_1_ENABLE BIT(4)
+#define ANX74XX_REG_VCONN_2_ENABLE BIT(5)
+#define ANX74XX_REG_R_INTERRUPT_OPEN_DRAIN BIT(2)
 
-#define ANX74XX_STANDBY_MODE		(0)
-#define ANX74XX_NORMAL_MODE		(1)
+#define ANX74XX_STANDBY_MODE (0)
+#define ANX74XX_NORMAL_MODE (1)
 
-#define ANX74XX_REG_TX_CTRL_1		0x81
-#define ANX74XX_REG_TX_HARD_RESET_REQ	BIT(1)
-#define ANX74XX_REG_TX_CABLE_RESET_REQ	BIT(2)
+#define ANX74XX_REG_TX_CTRL_1 0x81
+#define ANX74XX_REG_TX_HARD_RESET_REQ BIT(1)
+#define ANX74XX_REG_TX_CABLE_RESET_REQ BIT(2)
 
-#define ANX74XX_REG_TX_CTRL_2		0x82
-#define ANX74XX_REG_TX_WR_FIFO		0x83
-#define ANX74XX_REG_TX_FIFO_CTRL		0x9a
-#define ANX74XX_REG_TX_HEADER_L		0x2c
-#define ANX74XX_REG_TX_HEADER_H		0x2d
-#define ANX74XX_REG_TX_START_ADDR_0		0x6d
-#define ANX74XX_REG_TX_START_ADDR_1		0xd0
+#define ANX74XX_REG_TX_CTRL_2 0x82
+#define ANX74XX_REG_TX_WR_FIFO 0x83
+#define ANX74XX_REG_TX_FIFO_CTRL 0x9a
+#define ANX74XX_REG_TX_HEADER_L 0x2c
+#define ANX74XX_REG_TX_HEADER_H 0x2d
+#define ANX74XX_REG_TX_START_ADDR_0 0x6d
+#define ANX74XX_REG_TX_START_ADDR_1 0xd0
 
-#define ANX74XX_REG_CTRL_COMMAND		0xdb
-#define ANX74XX_REG_TX_SEND_DATA_REQ	BIT(0)
-#define ANX74XX_REG_TX_HARD_RST_REQ	BIT(1)
+#define ANX74XX_REG_CTRL_COMMAND 0xdb
+#define ANX74XX_REG_TX_SEND_DATA_REQ BIT(0)
+#define ANX74XX_REG_TX_HARD_RST_REQ BIT(1)
 
 #define ANX74XX_REG_TX_BIST_CTRL 0x9D
 #define ANX74XX_REG_TX_BIST_MODE BIT(4)
@@ -62,166 +62,163 @@
 #define ANX74XX_REG_TX_BIST_ENABLE BIT(1)
 #define ANX74XX_REG_TX_BIST_START BIT(0)
 
-#define ANX74XX_REG_PD_HEADER		0x69
-#define ANX74XX_REG_PD_RX_DATA_OBJ		0x11
-#define ANX74XX_REG_PD_RX_DATA_OBJ_M	0x4d
-
-#define ANX74XX_REG_ANALOG_STATUS		0x40
-#define ANX74XX_REG_VBUS_STATUS		BIT(4)
-#define ANX74XX_REG_CC_PULL_RD		0xfd
-#define ANX74XX_REG_CC_PULL_RP		0x02
-
-
-#define ANX74XX_REG_TX_AUTO_GOODCRC_2	0x94
-#define ANX74XX_REG_REPLY_SOP_EN        BIT(3)
-#define ANX74XX_REG_REPLY_SOP_1_EN      BIT(4)
-#define ANX74XX_REG_REPLY_SOP_2_EN      BIT(5)
-
-#define ANX74XX_REG_TX_AUTO_GOODCRC_1	0x9c
-#define ANX74XX_REG_SPEC_REV_BIT_POS	(3)
-#define ANX74XX_REG_DATA_ROLE_BIT_POS	(2)
-#define ANX74XX_REG_PWR_ROLE_BIT_POS	(1)
-#define ANX74XX_REG_AUTO_GOODCRC_EN	BIT(0)
+#define ANX74XX_REG_PD_HEADER 0x69
+#define ANX74XX_REG_PD_RX_DATA_OBJ 0x11
+#define ANX74XX_REG_PD_RX_DATA_OBJ_M 0x4d
+
+#define ANX74XX_REG_ANALOG_STATUS 0x40
+#define ANX74XX_REG_VBUS_STATUS BIT(4)
+#define ANX74XX_REG_CC_PULL_RD 0xfd
+#define ANX74XX_REG_CC_PULL_RP 0x02
+
+#define ANX74XX_REG_TX_AUTO_GOODCRC_2 0x94
+#define ANX74XX_REG_REPLY_SOP_EN BIT(3)
+#define ANX74XX_REG_REPLY_SOP_1_EN BIT(4)
+#define ANX74XX_REG_REPLY_SOP_2_EN BIT(5)
+
+#define ANX74XX_REG_TX_AUTO_GOODCRC_1 0x9c
+#define ANX74XX_REG_SPEC_REV_BIT_POS (3)
+#define ANX74XX_REG_DATA_ROLE_BIT_POS (2)
+#define ANX74XX_REG_PWR_ROLE_BIT_POS (1)
+#define ANX74XX_REG_AUTO_GOODCRC_EN BIT(0)
 #define ANX74XX_REG_AUTO_GOODCRC_SET(drole, prole)    \
 	((PD_REV20 << ANX74XX_REG_SPEC_REV_BIT_POS) | \
-	((drole) << ANX74XX_REG_DATA_ROLE_BIT_POS)  | \
-	((prole) << ANX74XX_REG_PWR_ROLE_BIT_POS)   | \
-	ANX74XX_REG_AUTO_GOODCRC_EN)
-
-
-#define ANX74XX_REG_ANALOG_CTRL_0		0x41
-#define ANX74XX_REG_R_PIN_CABLE_DET		BIT(7)
-
-#define ANX74XX_REG_ANALOG_CTRL_1		0x42
-#define ANX74XX_REG_ANALOG_CTRL_5		0x46
-#define ANX74XX_REG_ANALOG_CTRL_6		0x47
-#define ANX74XX_REG_CC_PULL_RP_36K	0x00
-#define ANX74XX_REG_CC_PULL_RP_12K	0x01
-#define ANX74XX_REG_CC_PULL_RP_4K	0x02
-
-#define ANX74XX_REG_R_SWITCH_CC_CLR	0x0f
-#define ANX74XX_REG_R_SWITCH_CC2_SET	0x10
-#define ANX74XX_REG_R_SWITCH_CC1_SET	0x20
-#define ANX74XX_REG_AUX_SWAP_SET_CC1	0x30
-#define ANX74XX_REG_AUX_SWAP_SET_CC2	0xc0
-
-#define ANX74XX_REG_ANALOG_CTRL_11		0x4c
-#define ANX74XX_REG_ANALOG_CTRL_12		0x4d
-
-#define ANX74XX_REG_MUX_ML0_RX2		BIT(0)
-#define ANX74XX_REG_MUX_ML0_RX1		BIT(1)
-#define ANX74XX_REG_MUX_ML3_RX2		BIT(2)
-#define ANX74XX_REG_MUX_ML3_RX1		BIT(3)
-#define ANX74XX_REG_MUX_SSRX_RX2	BIT(4)
-#define ANX74XX_REG_MUX_SSRX_RX1	BIT(5)
-#define ANX74XX_REG_MUX_ML1_TX2		BIT(6)
-#define ANX74XX_REG_MUX_ML1_TX1		BIT(7)
-
-#define ANX74XX_REG_MUX_ML2_TX2		BIT(4)
-#define ANX74XX_REG_MUX_ML2_TX1		BIT(5)
-#define ANX74XX_REG_MUX_SSTX_TX2	BIT(6)
-#define ANX74XX_REG_MUX_SSTX_TX1	BIT(7)
-
-#define ANX74XX_REG_CC_SOFTWARE_CTRL	0x4a
-#define ANX74XX_REG_CC_SW_CTRL_ENABLE	0x01
-#define ANX74XX_REG_TX_MODE_ENABLE		0x04
-
-#define ANX74XX_REG_SELECT_CC1		0x02
-
-#define ANX74XX_REG_GPIO_CTRL_4_5		0x3f
-#define ANX74XX_REG_VBUS_OP_ENABLE		0x04
-#define ANX74XX_REG_VBUS_GPIO_MODE		0xfe
-
-#define ANX74XX_REG_IRQ_EXT_MASK_1		0x3b
-#define ANX74XX_REG_IRQ_EXT_MASK_2		0x3c
-#define ANX74XX_REG_IRQ_EXT_SOURCE_1	0x3e
-#define ANX74XX_REG_EXT_SOP                     BIT(6)
-#define ANX74XX_REG_EXT_SOP_PRIME               BIT(7)
-#define ANX74XX_REG_IRQ_EXT_SOURCE_2	0x4e
-#define ANX74XX_REG_EXT_SOP_PRIME_PRIME         BIT(0)
-#define ANX74XX_REG_EXT_HARD_RST		BIT(2)
-#define ANX74XX_REG_IRQ_EXT_SOURCE_3	0x4f
-#define ANX74XX_REG_CLEAR_SOFT_IRQ		BIT(2)
-
-#define ANX74XX_REG_IRQ_SOURCE_RECV_MSG	0x6b
-#define ANX74XX_REG_IRQ_CC_MSG_INT		BIT(0)
-#define ANX74XX_REG_IRQ_CC_STATUS_INT	BIT(1)
-#define ANX74XX_REG_IRQ_GOOD_CRC_INT	BIT(2)
-#define ANX74XX_REG_IRQ_TX_FAIL_INT	BIT(3)
-#define ANX74XX_REG_IRQ_SOURCE_RECV_MSG_MASK	0x6c
-
-#define ANX74XX_REG_CLEAR_SET_BITS		0xff
-#define ANX74XX_REG_ALERT_HARD_RST_RECV		BIT(6)
-#define ANX74XX_REG_ALERT_MSG_RECV		BIT(5)
-#define ANX74XX_REG_ALERT_TX_MSG_ERROR	BIT(4)
-#define ANX74XX_REG_ALERT_TX_ACK_RECV	BIT(3)
-#define ANX74XX_REG_ALERT_TX_CABLE_RESETOK	BIT(2)
-#define ANX74XX_REG_ALERT_TX_HARD_RESETOK	BIT(1)
-#define ANX74XX_REG_ALERT_CC_CHANGE	BIT(0)
-
-#define ANX74XX_REG_ANALOG_CTRL_2		0x43
-#define ANX74XX_REG_MODE_TRANS		0x01
-
-#define ANX74XX_REG_SET_VBUS		0x20
-
-#define ANX74XX_REG_ANALOG_CTRL_7		0x48
-#define ANX74XX_REG_STATUS_CC_RD		0x01
-#define ANX74XX_REG_STATUS_CC_RA		0x03
-#define ANX74XX_REG_STATUS_CC1(reg)	((reg & 0x0C) >> 2)
-#define ANX74XX_REG_STATUS_CC2(reg)	((reg & 0x03) >> 0)
-
-#define ANX74XX_REG_HPD_CONTROL		0xfd
-
-#define ANX74XX_REG_HPD_CTRL_0		0x36
-#define ANX74XX_REG_DISCHARGE_CTRL     0x80
-#define ANX74XX_REG_HPD_OP_MODE		0x08
-#define ANX74XX_REG_HPD_DEFAULT		0x00
-#define ANX74XX_REG_HPD_OUT_DATA		0x10
+	 ((drole) << ANX74XX_REG_DATA_ROLE_BIT_POS) | \
+	 ((prole) << ANX74XX_REG_PWR_ROLE_BIT_POS) |  \
+	 ANX74XX_REG_AUTO_GOODCRC_EN)
+
+#define ANX74XX_REG_ANALOG_CTRL_0 0x41
+#define ANX74XX_REG_R_PIN_CABLE_DET BIT(7)
+
+#define ANX74XX_REG_ANALOG_CTRL_1 0x42
+#define ANX74XX_REG_ANALOG_CTRL_5 0x46
+#define ANX74XX_REG_ANALOG_CTRL_6 0x47
+#define ANX74XX_REG_CC_PULL_RP_36K 0x00
+#define ANX74XX_REG_CC_PULL_RP_12K 0x01
+#define ANX74XX_REG_CC_PULL_RP_4K 0x02
+
+#define ANX74XX_REG_R_SWITCH_CC_CLR 0x0f
+#define ANX74XX_REG_R_SWITCH_CC2_SET 0x10
+#define ANX74XX_REG_R_SWITCH_CC1_SET 0x20
+#define ANX74XX_REG_AUX_SWAP_SET_CC1 0x30
+#define ANX74XX_REG_AUX_SWAP_SET_CC2 0xc0
+
+#define ANX74XX_REG_ANALOG_CTRL_11 0x4c
+#define ANX74XX_REG_ANALOG_CTRL_12 0x4d
+
+#define ANX74XX_REG_MUX_ML0_RX2 BIT(0)
+#define ANX74XX_REG_MUX_ML0_RX1 BIT(1)
+#define ANX74XX_REG_MUX_ML3_RX2 BIT(2)
+#define ANX74XX_REG_MUX_ML3_RX1 BIT(3)
+#define ANX74XX_REG_MUX_SSRX_RX2 BIT(4)
+#define ANX74XX_REG_MUX_SSRX_RX1 BIT(5)
+#define ANX74XX_REG_MUX_ML1_TX2 BIT(6)
+#define ANX74XX_REG_MUX_ML1_TX1 BIT(7)
+
+#define ANX74XX_REG_MUX_ML2_TX2 BIT(4)
+#define ANX74XX_REG_MUX_ML2_TX1 BIT(5)
+#define ANX74XX_REG_MUX_SSTX_TX2 BIT(6)
+#define ANX74XX_REG_MUX_SSTX_TX1 BIT(7)
+
+#define ANX74XX_REG_CC_SOFTWARE_CTRL 0x4a
+#define ANX74XX_REG_CC_SW_CTRL_ENABLE 0x01
+#define ANX74XX_REG_TX_MODE_ENABLE 0x04
+
+#define ANX74XX_REG_SELECT_CC1 0x02
+
+#define ANX74XX_REG_GPIO_CTRL_4_5 0x3f
+#define ANX74XX_REG_VBUS_OP_ENABLE 0x04
+#define ANX74XX_REG_VBUS_GPIO_MODE 0xfe
+
+#define ANX74XX_REG_IRQ_EXT_MASK_1 0x3b
+#define ANX74XX_REG_IRQ_EXT_MASK_2 0x3c
+#define ANX74XX_REG_IRQ_EXT_SOURCE_1 0x3e
+#define ANX74XX_REG_EXT_SOP BIT(6)
+#define ANX74XX_REG_EXT_SOP_PRIME BIT(7)
+#define ANX74XX_REG_IRQ_EXT_SOURCE_2 0x4e
+#define ANX74XX_REG_EXT_SOP_PRIME_PRIME BIT(0)
+#define ANX74XX_REG_EXT_HARD_RST BIT(2)
+#define ANX74XX_REG_IRQ_EXT_SOURCE_3 0x4f
+#define ANX74XX_REG_CLEAR_SOFT_IRQ BIT(2)
+
+#define ANX74XX_REG_IRQ_SOURCE_RECV_MSG 0x6b
+#define ANX74XX_REG_IRQ_CC_MSG_INT BIT(0)
+#define ANX74XX_REG_IRQ_CC_STATUS_INT BIT(1)
+#define ANX74XX_REG_IRQ_GOOD_CRC_INT BIT(2)
+#define ANX74XX_REG_IRQ_TX_FAIL_INT BIT(3)
+#define ANX74XX_REG_IRQ_SOURCE_RECV_MSG_MASK 0x6c
+
+#define ANX74XX_REG_CLEAR_SET_BITS 0xff
+#define ANX74XX_REG_ALERT_HARD_RST_RECV BIT(6)
+#define ANX74XX_REG_ALERT_MSG_RECV BIT(5)
+#define ANX74XX_REG_ALERT_TX_MSG_ERROR BIT(4)
+#define ANX74XX_REG_ALERT_TX_ACK_RECV BIT(3)
+#define ANX74XX_REG_ALERT_TX_CABLE_RESETOK BIT(2)
+#define ANX74XX_REG_ALERT_TX_HARD_RESETOK BIT(1)
+#define ANX74XX_REG_ALERT_CC_CHANGE BIT(0)
+
+#define ANX74XX_REG_ANALOG_CTRL_2 0x43
+#define ANX74XX_REG_MODE_TRANS 0x01
+
+#define ANX74XX_REG_SET_VBUS 0x20
+
+#define ANX74XX_REG_ANALOG_CTRL_7 0x48
+#define ANX74XX_REG_STATUS_CC_RD 0x01
+#define ANX74XX_REG_STATUS_CC_RA 0x03
+#define ANX74XX_REG_STATUS_CC1(reg) ((reg & 0x0C) >> 2)
+#define ANX74XX_REG_STATUS_CC2(reg) ((reg & 0x03) >> 0)
+
+#define ANX74XX_REG_HPD_CONTROL 0xfd
+
+#define ANX74XX_REG_HPD_CTRL_0 0x36
+#define ANX74XX_REG_DISCHARGE_CTRL 0x80
+#define ANX74XX_REG_HPD_OP_MODE 0x08
+#define ANX74XX_REG_HPD_DEFAULT 0x00
+#define ANX74XX_REG_HPD_OUT_DATA 0x10
 
 #define ANX74XX_REG_RECVD_MSG_INT 0x98
-#define ANX74XX_REG_CC_STATUS     0x99
-#define ANX74XX_REG_CTRL_FW  0x2E
+#define ANX74XX_REG_CC_STATUS 0x99
+#define ANX74XX_REG_CTRL_FW 0x2E
 #define CLEAR_RX_BUFFER (1)
-#define ANX74XX_REG_POWER_DOWN_CTRL	0x0d
-#define ANX74XX_REG_STATUS_CC1_VRD_USB	BIT(7)
-#define ANX74XX_REG_STATUS_CC1_VRD_1P5	BIT(6)
-#define ANX74XX_REG_STATUS_CC1_VRD_3P0	BIT(5)
-#define ANX74XX_REG_STATUS_CC2_VRD_USB	BIT(4)
-#define ANX74XX_REG_STATUS_CC2_VRD_1P5	BIT(3)
-#define ANX74XX_REG_STATUS_CC2_VRD_3P0	BIT(2)
+#define ANX74XX_REG_POWER_DOWN_CTRL 0x0d
+#define ANX74XX_REG_STATUS_CC1_VRD_USB BIT(7)
+#define ANX74XX_REG_STATUS_CC1_VRD_1P5 BIT(6)
+#define ANX74XX_REG_STATUS_CC1_VRD_3P0 BIT(5)
+#define ANX74XX_REG_STATUS_CC2_VRD_USB BIT(4)
+#define ANX74XX_REG_STATUS_CC2_VRD_1P5 BIT(3)
+#define ANX74XX_REG_STATUS_CC2_VRD_3P0 BIT(2)
 
 /* defined in the inter-bock Spec: 4.2.10 CC Detect Status */
-#define ANX74XX_REG_CC_STATUS_MASK  0xf
-#define BIT_VALUE_OF_SRC_CC_RD      0x01
-#define BIT_VALUE_OF_SRC_CC_RA      0x02
+#define ANX74XX_REG_CC_STATUS_MASK 0xf
+#define BIT_VALUE_OF_SRC_CC_RD 0x01
+#define BIT_VALUE_OF_SRC_CC_RA 0x02
 #define BIT_VALUE_OF_SNK_CC_DEFAULT 0x04
-#define BIT_VALUE_OF_SNK_CC_1_P_5   0x08
-#define BIT_VALUE_OF_SNK_CC_3_P_0   0x0C
-#define ANX74XX_CC_RA_MASK (BIT_VALUE_OF_SRC_CC_RA | \
-			    (BIT_VALUE_OF_SRC_CC_RA << 4))
-#define ANX74XX_CC_RD_MASK (BIT_VALUE_OF_SRC_CC_RD | \
-			    (BIT_VALUE_OF_SRC_CC_RD << 4))
+#define BIT_VALUE_OF_SNK_CC_1_P_5 0x08
+#define BIT_VALUE_OF_SNK_CC_3_P_0 0x0C
+#define ANX74XX_CC_RA_MASK \
+	(BIT_VALUE_OF_SRC_CC_RA | (BIT_VALUE_OF_SRC_CC_RA << 4))
+#define ANX74XX_CC_RD_MASK \
+	(BIT_VALUE_OF_SRC_CC_RD | (BIT_VALUE_OF_SRC_CC_RD << 4))
 
 /*
  * RESETN low to PWR_EN low delay
  */
-#define ANX74XX_RST_L_PWR_L_DELAY_MS	1
+#define ANX74XX_RST_L_PWR_L_DELAY_MS 1
 /*
  * minimum power off-to-on delay to reset chip
  */
-#define ANX74XX_PWR_L_PWR_H_DELAY_MS	10
+#define ANX74XX_PWR_L_PWR_H_DELAY_MS 10
 /*
  * parameter T4: PWR_EN high to RESETN high delay
  */
-#define ANX74XX_PWR_H_RST_H_DELAY_MS	10
+#define ANX74XX_PWR_H_RST_H_DELAY_MS 10
 
 extern const struct tcpm_drv anx74xx_tcpm_drv;
 extern const struct usb_mux_driver anx74xx_tcpm_usb_mux_driver;
 void anx74xx_tcpc_set_vbus(int port, int enable);
 void anx74xx_tcpc_clear_hpd_status(int port);
 void anx74xx_tcpc_update_hpd_status(const struct usb_mux *me,
-				    mux_state_t mux_state,
-				    bool *ack_required);
+				    mux_state_t mux_state, bool *ack_required);
 
 #ifdef CONFIG_CMD_I2C_STRESS_TEST_TCPC
 extern struct i2c_stress_test_dev anx74xx_i2c_stress_test_dev;
diff --git a/driver/tcpm/anx7688.c b/driver/tcpm/anx7688.c
index 5e37352bc5..6ad8a16ff4 100644
--- a/driver/tcpm/anx7688.c
+++ b/driver/tcpm/anx7688.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,24 +12,24 @@
 #include "usb_mux.h"
 
 #if defined(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE) || \
-	defined(CONFIG_USB_PD_TCPC_LOW_POWER) || \
+	defined(CONFIG_USB_PD_TCPC_LOW_POWER) ||    \
 	defined(CONFIG_USB_PD_DISCHARGE_TCPC)
 #error "Unsupported config options of anx7688 PD driver"
 #endif
 
-#define ANX7688_VENDOR_ALERT    BIT(15)
+#define ANX7688_VENDOR_ALERT BIT(15)
 
-#define ANX7688_REG_STATUS      0x82
+#define ANX7688_REG_STATUS 0x82
 #define ANX7688_REG_STATUS_LINK BIT(0)
 
-#define ANX7688_REG_HPD         0x83
-#define ANX7688_REG_HPD_HIGH    BIT(0)
-#define ANX7688_REG_HPD_IRQ     BIT(1)
-#define ANX7688_REG_HPD_ENABLE  BIT(2)
+#define ANX7688_REG_HPD 0x83
+#define ANX7688_REG_HPD_HIGH BIT(0)
+#define ANX7688_REG_HPD_IRQ BIT(1)
+#define ANX7688_REG_HPD_ENABLE BIT(2)
 
-#define ANX7688_USBC_ADDR_FLAGS		0x28
-#define ANX7688_REG_RAMCTRL		0xe7
-#define ANX7688_REG_RAMCTRL_BOOT_DONE	BIT(6)
+#define ANX7688_USBC_ADDR_FLAGS 0x28
+#define ANX7688_REG_RAMCTRL 0xe7
+#define ANX7688_REG_RAMCTRL_BOOT_DONE BIT(6)
 
 static int anx7688_init(int port)
 {
@@ -85,9 +85,9 @@ static void anx7688_update_hpd_enable(int port)
 	    !(status & ANX7688_REG_STATUS_LINK)) {
 		reg &= ~ANX7688_REG_HPD_IRQ;
 		tcpc_write(port, ANX7688_REG_HPD,
-			   (status & ANX7688_REG_STATUS_LINK)
-			   ? reg | ANX7688_REG_HPD_ENABLE
-			   : reg & ~ANX7688_REG_HPD_ENABLE);
+			   (status & ANX7688_REG_STATUS_LINK) ?
+				   reg | ANX7688_REG_HPD_ENABLE :
+				   reg & ~ANX7688_REG_HPD_ENABLE);
 	}
 }
 
@@ -153,6 +153,10 @@ static int anx7688_mux_set(const struct usb_mux *me, mux_state_t mux_state,
 	/* This driver does not use host command ACKs */
 	*ack_required = false;
 
+	/* This driver treats safe mode as none */
+	if (mux_state == USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
+
 	rv = mux_read(me, TCPC_REG_CONFIG_STD_OUTPUT, &reg);
 	if (rv != EC_SUCCESS)
 		return rv;
@@ -195,25 +199,26 @@ static bool anx7688_tcpm_check_vbus_level(int port, enum vbus_level level)
 
 /* ANX7688 is a TCPCI compatible port controller */
 const struct tcpm_drv anx7688_tcpm_drv = {
-	.init			= &anx7688_init,
-	.release		= &anx7688_release,
-	.get_cc			= &tcpci_tcpm_get_cc,
+	.init = &anx7688_init,
+	.release = &anx7688_release,
+	.get_cc = &tcpci_tcpm_get_cc,
 #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	.check_vbus_level	= &anx7688_tcpm_check_vbus_level,
+	.check_vbus_level = &anx7688_tcpm_check_vbus_level,
 #endif
-	.select_rp_value	= &tcpci_tcpm_select_rp_value,
-	.set_cc			= &tcpci_tcpm_set_cc,
-	.set_polarity		= &tcpci_tcpm_set_polarity,
+	.select_rp_value = &tcpci_tcpm_select_rp_value,
+	.set_cc = &tcpci_tcpm_set_cc,
+	.set_polarity = &tcpci_tcpm_set_polarity,
 #ifdef CONFIG_USB_PD_DECODE_SOP
-	.sop_prime_enable	= &tcpci_tcpm_sop_prime_enable,
+	.sop_prime_enable = &tcpci_tcpm_sop_prime_enable,
 #endif
-	.set_vconn		= &tcpci_tcpm_set_vconn,
-	.set_msg_header		= &tcpci_tcpm_set_msg_header,
-	.set_rx_enable		= &tcpci_tcpm_set_rx_enable,
-	.get_message_raw	= &tcpci_tcpm_get_message_raw,
-	.transmit		= &tcpci_tcpm_transmit,
-	.tcpc_alert		= &anx7688_tcpc_alert,
-	.set_bist_test_mode	= &tcpci_set_bist_test_mode,
+	.set_vconn = &tcpci_tcpm_set_vconn,
+	.set_msg_header = &tcpci_tcpm_set_msg_header,
+	.set_rx_enable = &tcpci_tcpm_set_rx_enable,
+	.get_message_raw = &tcpci_tcpm_get_message_raw,
+	.transmit = &tcpci_tcpm_transmit,
+	.tcpc_alert = &anx7688_tcpc_alert,
+	.set_bist_test_mode = &tcpci_set_bist_test_mode,
+	.get_bist_test_mode = &tcpci_get_bist_test_mode,
 };
 
 #ifdef CONFIG_USB_PD_TCPM_MUX
diff --git a/driver/tcpm/anx7688.h b/driver/tcpm/anx7688.h
index 534e4155b1..8a7d2e1d03 100644
--- a/driver/tcpm/anx7688.h
+++ b/driver/tcpm/anx7688.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/driver/tcpm/ccgxxf.c b/driver/tcpm/ccgxxf.c
index ee1754ce08..34670e12ef 100644
--- a/driver/tcpm/ccgxxf.c
+++ b/driver/tcpm/ccgxxf.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -9,6 +9,50 @@
 #include "console.h"
 #include "tcpm/tcpci.h"
 
+/*
+ * TODO (b/236994474): Once the PD negotiation completes, CCGXXF chip stops
+ * responding over I2C for about 10 seconds. As DRP is enabled, TCPM algorithm
+ * constantly looks for any CC status changes even after negotiation completes.
+ * Hence, cache the CC state and return the cached values in case of I2C
+ * failures. This workaround will be removed once the fix is added in the
+ * physical layer firmware of CCGXXF.
+ */
+
+struct ccgxxf_cc {
+	bool good_cc;
+	enum tcpc_cc_voltage_status cc1;
+	enum tcpc_cc_voltage_status cc2;
+};
+
+static struct ccgxxf_cc ccgxxf_cc_cache[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+static int ccgxxf_tcpci_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
+				    enum tcpc_cc_voltage_status *cc2)
+{
+	int rv = tcpci_tcpm_get_cc(port, cc1, cc2);
+
+	if (rv) {
+		if (!ccgxxf_cc_cache[port].good_cc)
+			return rv;
+
+		*cc1 = ccgxxf_cc_cache[port].cc1;
+		*cc2 = ccgxxf_cc_cache[port].cc2;
+	} else {
+		ccgxxf_cc_cache[port].good_cc = true;
+		ccgxxf_cc_cache[port].cc1 = *cc1;
+		ccgxxf_cc_cache[port].cc2 = *cc2;
+	}
+
+	return EC_SUCCESS;
+}
+
+static int ccgxxf_tcpci_tcpm_init(int port)
+{
+	ccgxxf_cc_cache[port].good_cc = false;
+
+	return tcpci_tcpm_init(port);
+}
+
 #ifdef CONFIG_USB_PD_TCPM_SBU
 static int ccgxxf_tcpc_set_sbu(int port, bool enable)
 {
@@ -25,55 +69,61 @@ static void ccgxxf_dump_registers(int port)
 
 	/* Get the F/W version and build ID */
 	if (!tcpc_read16(port, CCGXXF_REG_FW_VERSION, &fw_ver) &&
-		!tcpc_read16(port, CCGXXF_REG_FW_VERSION_BUILD, &fw_build)) {
+	    !tcpc_read16(port, CCGXXF_REG_FW_VERSION_BUILD, &fw_build)) {
 		ccprintf("  FW_VERSION(build.major.minor)        = %d.%d.%d\n",
-			fw_build & 0xFF, (fw_ver >> 8) & 0xFF, fw_ver & 0xFF);
+			 fw_build & 0xFF, (fw_ver >> 8) & 0xFF, fw_ver & 0xFF);
 	}
 }
 #endif
 
+int ccgxxf_reset(int port)
+{
+	return tcpc_write16(port, CCGXXF_REG_FWU_COMMAND, CCGXXF_FWU_CMD_RESET);
+}
+
 const struct tcpm_drv ccgxxf_tcpm_drv = {
-	.init			= &tcpci_tcpm_init,
-	.release		= &tcpci_tcpm_release,
-	.get_cc			= &tcpci_tcpm_get_cc,
+	.init = &ccgxxf_tcpci_tcpm_init,
+	.release = &tcpci_tcpm_release,
+	.get_cc = &ccgxxf_tcpci_tcpm_get_cc,
 #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	.check_vbus_level	= &tcpci_tcpm_check_vbus_level,
+	.check_vbus_level = &tcpci_tcpm_check_vbus_level,
 #endif
-	.select_rp_value	= &tcpci_tcpm_select_rp_value,
-	.set_cc			= &tcpci_tcpm_set_cc,
-	.set_polarity		= &tcpci_tcpm_set_polarity,
+	.select_rp_value = &tcpci_tcpm_select_rp_value,
+	.set_cc = &tcpci_tcpm_set_cc,
+	.set_polarity = &tcpci_tcpm_set_polarity,
 #ifdef CONFIG_USB_PD_DECODE_SOP
-	.sop_prime_enable	= &tcpci_tcpm_sop_prime_enable,
+	.sop_prime_enable = &tcpci_tcpm_sop_prime_enable,
 #endif
-	.set_vconn		= &tcpci_tcpm_set_vconn,
-	.set_msg_header		= &tcpci_tcpm_set_msg_header,
-	.set_rx_enable		= &tcpci_tcpm_set_rx_enable,
-	.get_message_raw	= &tcpci_tcpm_get_message_raw,
-	.transmit		= &tcpci_tcpm_transmit,
-	.tcpc_alert		= &tcpci_tcpc_alert,
+	.set_vconn = &tcpci_tcpm_set_vconn,
+	.set_msg_header = &tcpci_tcpm_set_msg_header,
+	.set_rx_enable = &tcpci_tcpm_set_rx_enable,
+	.get_message_raw = &tcpci_tcpm_get_message_raw,
+	.transmit = &tcpci_tcpm_transmit,
+	.tcpc_alert = &tcpci_tcpc_alert,
 #ifdef CONFIG_USB_PD_DISCHARGE_TCPC
-	.tcpc_discharge_vbus	= &tcpci_tcpc_discharge_vbus,
+	.tcpc_discharge_vbus = &tcpci_tcpc_discharge_vbus,
 #endif
 	.tcpc_enable_auto_discharge_disconnect =
 		&tcpci_tcpc_enable_auto_discharge_disconnect,
 #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-	.drp_toggle		= &tcpci_tcpc_drp_toggle,
+	.drp_toggle = &tcpci_tcpc_drp_toggle,
 #endif
-	.get_chip_info		= &tcpci_get_chip_info,
+	.get_chip_info = &tcpci_get_chip_info,
 #ifdef CONFIG_USB_PD_PPC
-	.get_snk_ctrl		= &tcpci_tcpm_get_snk_ctrl,
-	.set_snk_ctrl		= &tcpci_tcpm_set_snk_ctrl,
-	.get_src_ctrl		= &tcpci_tcpm_get_src_ctrl,
-	.set_src_ctrl		= &tcpci_tcpm_set_src_ctrl,
+	.get_snk_ctrl = &tcpci_tcpm_get_snk_ctrl,
+	.set_snk_ctrl = &tcpci_tcpm_set_snk_ctrl,
+	.get_src_ctrl = &tcpci_tcpm_get_src_ctrl,
+	.set_src_ctrl = &tcpci_tcpm_set_src_ctrl,
 #endif
 #ifdef CONFIG_USB_PD_TCPM_SBU
-	.set_sbu		= &ccgxxf_tcpc_set_sbu,
+	.set_sbu = &ccgxxf_tcpc_set_sbu,
 #endif
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	.enter_low_power_mode	= &tcpci_enter_low_power_mode,
+	.enter_low_power_mode = &tcpci_enter_low_power_mode,
 #endif
-	.set_bist_test_mode	= &tcpci_set_bist_test_mode,
+	.set_bist_test_mode = &tcpci_set_bist_test_mode,
+	.get_bist_test_mode = &tcpci_get_bist_test_mode,
 #ifdef CONFIG_CMD_TCPC_DUMP
-	.dump_registers		= &ccgxxf_dump_registers,
+	.dump_registers = &ccgxxf_dump_registers,
 #endif
 };
diff --git a/driver/tcpm/ccgxxf.h b/driver/tcpm/ccgxxf.h
index 246a231d04..9342dc9a98 100644
--- a/driver/tcpm/ccgxxf.h
+++ b/driver/tcpm/ccgxxf.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,15 +10,37 @@
 #ifndef __CROS_EC_DRIVER_TCPM_CCGXXF_H
 #define __CROS_EC_DRIVER_TCPM_CCGXXF_H
 
-#define CCGXXF_I2C_ADDR1_FLAGS	0x0B
-#define CCGXXF_I2C_ADDR2_FLAGS	0x1B
+#define CCGXXF_I2C_ADDR1_FLAGS 0x0B
+#define CCGXXF_I2C_ADDR2_FLAGS 0x1B
 
 /* SBU FET control register */
-#define CCGXXF_REG_SBU_MUX_CTL	0xBB
+#define CCGXXF_REG_SBU_MUX_CTL 0xBB
 
 /* F/W info register */
-#define CCGXXF_REG_FW_VERSION		0x94
-#define CCGXXF_REG_FW_VERSION_BUILD	0x96
+#define CCGXXF_REG_FW_VERSION 0x94
+#define CCGXXF_REG_FW_VERSION_BUILD 0x96
+
+/* Firmware update / reset control register */
+#define CCGXXF_REG_FWU_COMMAND 0x92
+#define CCGXXF_FWU_CMD_RESET 0x0077
+
+/**
+ * Reset CCGXXF chip
+ *
+ * CCGXXF's reset line is connected to an internal LDO hence external GPIOs
+ * should not control the reset line as it can prevent it booting from dead
+ * battery, instead a software mechanism can be used to reset the chip.
+ * Care must be taken by board level function in below scenarios;
+ * 1. During dead battery boot from CCGXXF ports, do not reset the chip as
+ *    it will lose the dead battery boot scenario content.
+ * 2. If dual port solution chip is used, resetting one port resets other port
+ *    as well.
+ * 3. Built-in I/O expander also gets reset.
+ *
+ * @param port Type-C port number
+ * @return EC_SUCCESS or error
+ */
+int ccgxxf_reset(int port);
 
 extern const struct tcpm_drv ccgxxf_tcpm_drv;
 
@@ -45,13 +67,13 @@ enum ccgxxf_io_pins {
 	CCGXXF_IO_7
 };
 
-#define CCGXXF_REG_GPIO_CONTROL(port)	((port) + 0x80)
-#define CCGXXF_REG_GPIO_STATUS(port)	((port) + 0x84)
+#define CCGXXF_REG_GPIO_CONTROL(port) ((port) + 0x80)
+#define CCGXXF_REG_GPIO_STATUS(port) ((port) + 0x84)
 
-#define CCGXXF_REG_GPIO_MODE		0x88
-#define CCGXXF_GPIO_PIN_MASK_SHIFT	8
-#define CCGXXF_GPIO_PIN_MODE_SHIFT	2
-#define CCGXXF_GPIO_1P8V_SEL		BIT(7)
+#define CCGXXF_REG_GPIO_MODE 0x88
+#define CCGXXF_GPIO_PIN_MASK_SHIFT 8
+#define CCGXXF_GPIO_PIN_MODE_SHIFT 2
+#define CCGXXF_GPIO_1P8V_SEL BIT(7)
 
 enum ccgxxf_gpio_mode {
 	CCGXXF_GPIO_MODE_HIZ_ANALOG,
diff --git a/driver/tcpm/fusb302.c b/driver/tcpm/fusb302.c
index 8357359012..780e5b2cfe 100644
--- a/driver/tcpm/fusb302.c
+++ b/driver/tcpm/fusb302.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -25,8 +25,8 @@
 #error "Unsupported config options of fusb302 PD driver"
 #endif
 
-#define PACKET_IS_GOOD_CRC(head) (PD_HEADER_TYPE(head) == PD_CTRL_GOOD_CRC && \
-				 PD_HEADER_CNT(head) == 0)
+#define PACKET_IS_GOOD_CRC(head) \
+	(PD_HEADER_TYPE(head) == PD_CTRL_GOOD_CRC && PD_HEADER_CNT(head) == 0)
 
 static struct fusb302_chip_state {
 	int cc_polarity;
@@ -77,7 +77,7 @@ static void fusb302_auto_goodcrc_enable(int port, int enable)
 {
 	int reg;
 
-	tcpc_read(port,	TCPC_REG_SWITCHES1, &reg);
+	tcpc_read(port, TCPC_REG_SWITCHES1, &reg);
 
 	if (enable)
 		reg |= TCPC_REG_SWITCHES1_AUTO_GCRC;
@@ -158,8 +158,8 @@ static int measure_cc_pin_source(int port, int cc_measure)
 		/* Read status register */
 		tcpc_read(port, TCPC_REG_STATUS0, &reg);
 
-		cc_lvl = (reg & TCPC_REG_STATUS0_COMP) ? TYPEC_CC_VOLT_RD
-						       : TYPEC_CC_VOLT_RA;
+		cc_lvl = (reg & TCPC_REG_STATUS0_COMP) ? TYPEC_CC_VOLT_RD :
+							 TYPEC_CC_VOLT_RA;
 	}
 
 	/* Restore SWITCHES0 register to its value prior */
@@ -172,8 +172,8 @@ static int measure_cc_pin_source(int port, int cc_measure)
 
 /* Determine cc pin state for source when in manual detect mode */
 static void detect_cc_pin_source_manual(int port,
-	enum tcpc_cc_voltage_status *cc1_lvl,
-	enum tcpc_cc_voltage_status *cc2_lvl)
+					enum tcpc_cc_voltage_status *cc1_lvl,
+					enum tcpc_cc_voltage_status *cc2_lvl)
 {
 	int cc1_measure = TCPC_REG_SWITCHES0_MEAS_CC1;
 	int cc2_measure = TCPC_REG_SWITCHES0_MEAS_CC2;
@@ -189,12 +189,11 @@ static void detect_cc_pin_source_manual(int port,
 		*cc1_lvl = measure_cc_pin_source(port, cc1_measure);
 		*cc2_lvl = measure_cc_pin_source(port, cc2_measure);
 	}
-
 }
 
 /* Determine cc pin state for sink */
 static void detect_cc_pin_sink(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2)
+			       enum tcpc_cc_voltage_status *cc2)
 {
 	int reg;
 	int orig_meas_cc1;
@@ -220,7 +219,6 @@ static void detect_cc_pin_sink(int port, enum tcpc_cc_voltage_status *cc1,
 	else
 		orig_meas_cc2 = 0;
 
-
 	/* Disable CC2 measurement switch, enable CC1 measurement switch */
 	reg &= ~TCPC_REG_SWITCHES0_MEAS_CC2;
 	reg |= TCPC_REG_SWITCHES0_MEAS_CC1;
@@ -296,7 +294,7 @@ static int get_num_bytes(uint16_t header)
 }
 
 static int fusb302_send_message(int port, uint16_t header, const uint32_t *data,
-				 uint8_t *buf, int buf_pos)
+				uint8_t *buf, int buf_pos)
 {
 	int rv;
 	int reg;
@@ -472,7 +470,7 @@ static int fusb302_tcpm_release(int port)
 }
 
 static int fusb302_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2)
+			       enum tcpc_cc_voltage_status *cc2)
 {
 	if (state[port].pulling_up) {
 		/* Source mode? */
@@ -504,12 +502,12 @@ static int fusb302_tcpm_set_cc(int port, int pull)
 			 TCPC_REG_SWITCHES0_VCONN_CC2);
 
 		reg |= TCPC_REG_SWITCHES0_CC1_PU_EN |
-			TCPC_REG_SWITCHES0_CC2_PU_EN;
+		       TCPC_REG_SWITCHES0_CC2_PU_EN;
 
 		if (state[port].vconn_enabled)
 			reg |= state[port].cc_polarity ?
-			       TCPC_REG_SWITCHES0_VCONN_CC1 :
-			       TCPC_REG_SWITCHES0_VCONN_CC2;
+				       TCPC_REG_SWITCHES0_VCONN_CC1 :
+				       TCPC_REG_SWITCHES0_VCONN_CC2;
 
 		tcpc_write(port, TCPC_REG_SWITCHES0, reg);
 
@@ -609,7 +607,7 @@ static int fusb302_tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity)
 }
 
 __maybe_unused static int fusb302_tcpm_decode_sop_prime_enable(int port,
-								bool enable)
+							       bool enable)
 {
 	int reg;
 
@@ -617,11 +615,9 @@ __maybe_unused static int fusb302_tcpm_decode_sop_prime_enable(int port,
 		return EC_ERROR_UNKNOWN;
 
 	if (enable)
-		reg |= (TCPC_REG_CONTROL1_ENSOP1 |
-				TCPC_REG_CONTROL1_ENSOP2);
+		reg |= (TCPC_REG_CONTROL1_ENSOP1 | TCPC_REG_CONTROL1_ENSOP2);
 	else
-		reg &= ~(TCPC_REG_CONTROL1_ENSOP1 |
-			TCPC_REG_CONTROL1_ENSOP2);
+		reg &= ~(TCPC_REG_CONTROL1_ENSOP1 | TCPC_REG_CONTROL1_ENSOP2);
 
 	return tcpc_write(port, TCPC_REG_CONTROL1, reg);
 }
@@ -648,12 +644,11 @@ static int fusb302_tcpm_set_vconn(int port, int enable)
 		if (IS_ENABLED(CONFIG_USB_PD_DECODE_SOP)) {
 			if (state[port].rx_enable) {
 				if (fusb302_tcpm_decode_sop_prime_enable(port,
-									true))
+									 true))
 					return EC_ERROR_UNKNOWN;
 			}
 		}
 	} else {
-
 		tcpc_read(port, TCPC_REG_SWITCHES0, &reg);
 
 		/* clear VCONN switch bits */
@@ -665,7 +660,7 @@ static int fusb302_tcpm_set_vconn(int port, int enable)
 		if (IS_ENABLED(CONFIG_USB_PD_DECODE_SOP)) {
 			if (state[port].rx_enable) {
 				if (fusb302_tcpm_decode_sop_prime_enable(port,
-									false))
+									 false))
 					return EC_ERROR_UNKNOWN;
 			}
 		}
@@ -731,7 +726,6 @@ static int fusb302_tcpm_set_rx_enable(int port, int enable)
 		/* flush rx fifo in case messages have been coming our way */
 		fusb302_flush_rx_fifo(port);
 
-
 	} else {
 		tcpc_write(port, TCPC_REG_SWITCHES0, reg);
 
@@ -814,7 +808,8 @@ static int fusb302_tcpm_get_message_raw(int port, uint32_t *payload, int *head)
 		 * No START, but do issue a STOP at the end.
 		 * add 4 to len to read CRC out
 		 */
-		rv |= tcpc_xfer_unlocked(port, 0, 0, buf, len+4, I2C_XFER_STOP);
+		rv |= tcpc_xfer_unlocked(port, 0, 0, buf, len + 4,
+					 I2C_XFER_STOP);
 
 		tcpc_lock(port, 0);
 	} while (!rv && PACKET_IS_GOOD_CRC(*head) &&
@@ -988,9 +983,8 @@ void fusb302_tcpc_alert(int port)
 	if (interrupt & TCPC_REG_INTERRUPT_VBUSOK) {
 		/* VBUS crossed threshold */
 #ifdef CONFIG_USB_CHARGER
-		usb_charger_vbus_change(port,
-					fusb302_tcpm_check_vbus_level(port,
-							VBUS_PRESENT));
+		usb_charger_vbus_change(port, fusb302_tcpm_check_vbus_level(
+						      port, VBUS_PRESENT));
 #else
 		if (!fusb302_tcpm_check_vbus_level(port, VBUS_PRESENT))
 			pd_vbus_low(port);
@@ -1040,7 +1034,6 @@ void fusb302_tcpc_alert(int port)
 			fusb302_flush_rx_fifo(port);
 		}
 	}
-
 }
 
 /* For BIST receiving */
@@ -1064,16 +1057,16 @@ static int fusb302_set_toggle_mode(int port, int mode)
 	int reg, rv;
 
 	rv = i2c_read8(tcpc_config[port].i2c_info.port,
-		tcpc_config[port].i2c_info.addr_flags,
-		TCPC_REG_CONTROL2, &reg);
+		       tcpc_config[port].i2c_info.addr_flags, TCPC_REG_CONTROL2,
+		       &reg);
 	if (rv)
 		return rv;
 
 	reg &= ~TCPC_REG_CONTROL2_MODE_MASK;
 	reg |= mode << TCPC_REG_CONTROL2_MODE_POS;
 	return i2c_write8(tcpc_config[port].i2c_info.port,
-		tcpc_config[port].i2c_info.addr_flags,
-		TCPC_REG_CONTROL2, reg);
+			  tcpc_config[port].i2c_info.addr_flags,
+			  TCPC_REG_CONTROL2, reg);
 }
 
 static int fusb302_tcpm_enter_low_power_mode(int port)
@@ -1087,8 +1080,8 @@ static int fusb302_tcpm_enter_low_power_mode(int port)
 	 * - start toggling
 	 */
 	rv = i2c_write8(tcpc_config[port].i2c_info.port,
-			  tcpc_config[port].i2c_info.addr_flags,
-			  TCPC_REG_POWER, TCPC_REG_POWER_PWR_LOW);
+			tcpc_config[port].i2c_info.addr_flags, TCPC_REG_POWER,
+			TCPC_REG_POWER_PWR_LOW);
 	if (rv)
 		return rv;
 
@@ -1101,8 +1094,8 @@ static int fusb302_tcpm_enter_low_power_mode(int port)
 		break;
 	case PD_DRP_FREEZE:
 		mode = pd_get_power_role(port) == PD_ROLE_SINK ?
-			TCPC_REG_CONTROL2_MODE_UFP :
-			TCPC_REG_CONTROL2_MODE_DFP;
+			       TCPC_REG_CONTROL2_MODE_UFP :
+			       TCPC_REG_CONTROL2_MODE_DFP;
 		break;
 	case PD_DRP_FORCE_SINK:
 		mode = TCPC_REG_CONTROL2_MODE_UFP;
@@ -1118,14 +1111,14 @@ static int fusb302_tcpm_enter_low_power_mode(int port)
 	usleep(250);
 
 	rv = i2c_read8(tcpc_config[port].i2c_info.port,
-		tcpc_config[port].i2c_info.addr_flags,
-		TCPC_REG_CONTROL2, &reg);
+		       tcpc_config[port].i2c_info.addr_flags, TCPC_REG_CONTROL2,
+		       &reg);
 	if (rv)
 		return rv;
 	reg |= TCPC_REG_CONTROL2_TOGGLE;
 	return i2c_write8(tcpc_config[port].i2c_info.port,
-		tcpc_config[port].i2c_info.addr_flags,
-		TCPC_REG_CONTROL2, reg);
+			  tcpc_config[port].i2c_info.addr_flags,
+			  TCPC_REG_CONTROL2, reg);
 }
 #endif
 
@@ -1143,7 +1136,7 @@ static int fusb302_compare_mdac(int port, int mdac)
 	tcpc_read(port, TCPC_REG_MEASURE, &orig_reg);
 	/* set reg_measure bit 0~5 to mdac, and bit6 to 1(measure vbus) */
 	tcpc_write(port, TCPC_REG_MEASURE,
-		(mdac & TCPC_REG_MEASURE_MDAC_MASK) | TCPC_REG_MEASURE_VBUS);
+		   (mdac & TCPC_REG_MEASURE_MDAC_MASK) | TCPC_REG_MEASURE_VBUS);
 
 	/* Wait on measurement */
 	usleep(350);
@@ -1181,25 +1174,25 @@ int tcpc_get_vbus_voltage(int port)
 }
 
 const struct tcpm_drv fusb302_tcpm_drv = {
-	.init			= &fusb302_tcpm_init,
-	.release		= &fusb302_tcpm_release,
-	.get_cc			= &fusb302_tcpm_get_cc,
+	.init = &fusb302_tcpm_init,
+	.release = &fusb302_tcpm_release,
+	.get_cc = &fusb302_tcpm_get_cc,
 #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	.check_vbus_level	= &fusb302_tcpm_check_vbus_level,
+	.check_vbus_level = &fusb302_tcpm_check_vbus_level,
 #endif
-	.select_rp_value	= &fusb302_tcpm_select_rp_value,
-	.set_cc			= &fusb302_tcpm_set_cc,
-	.set_polarity		= &fusb302_tcpm_set_polarity,
+	.select_rp_value = &fusb302_tcpm_select_rp_value,
+	.set_cc = &fusb302_tcpm_set_cc,
+	.set_polarity = &fusb302_tcpm_set_polarity,
 #ifdef CONFIG_USB_PD_DECODE_SOP
-	.sop_prime_enable	= &fusb302_tcpm_decode_sop_prime_enable,
+	.sop_prime_enable = &fusb302_tcpm_decode_sop_prime_enable,
 #endif
-	.set_vconn		= &fusb302_tcpm_set_vconn,
-	.set_msg_header		= &fusb302_tcpm_set_msg_header,
-	.set_rx_enable		= &fusb302_tcpm_set_rx_enable,
-	.get_message_raw	= &fusb302_tcpm_get_message_raw,
-	.transmit		= &fusb302_tcpm_transmit,
-	.tcpc_alert		= &fusb302_tcpc_alert,
+	.set_vconn = &fusb302_tcpm_set_vconn,
+	.set_msg_header = &fusb302_tcpm_set_msg_header,
+	.set_rx_enable = &fusb302_tcpm_set_rx_enable,
+	.get_message_raw = &fusb302_tcpm_get_message_raw,
+	.transmit = &fusb302_tcpm_transmit,
+	.tcpc_alert = &fusb302_tcpc_alert,
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	.enter_low_power_mode	= &fusb302_tcpm_enter_low_power_mode,
+	.enter_low_power_mode = &fusb302_tcpm_enter_low_power_mode,
 #endif
 };
diff --git a/driver/tcpm/fusb302.h b/driver/tcpm/fusb302.h
index 717b28df18..ac4fb96e19 100644
--- a/driver/tcpm/fusb302.h
+++ b/driver/tcpm/fusb302.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -24,173 +24,173 @@
 /* FUSB302B11MPX */
 #define FUSB302_I2C_ADDR_B11_FLAGS 0x25
 
-#define TCPC_REG_DEVICE_ID	0x01
-
-#define TCPC_REG_SWITCHES0	0x02
-#define TCPC_REG_SWITCHES0_CC2_PU_EN	(1<<7)
-#define TCPC_REG_SWITCHES0_CC1_PU_EN	(1<<6)
-#define TCPC_REG_SWITCHES0_VCONN_CC2	(1<<5)
-#define TCPC_REG_SWITCHES0_VCONN_CC1	(1<<4)
-#define TCPC_REG_SWITCHES0_MEAS_CC2	(1<<3)
-#define TCPC_REG_SWITCHES0_MEAS_CC1	(1<<2)
-#define TCPC_REG_SWITCHES0_CC2_PD_EN	(1<<1)
-#define TCPC_REG_SWITCHES0_CC1_PD_EN	(1<<0)
-
-#define TCPC_REG_SWITCHES1	0x03
-#define TCPC_REG_SWITCHES1_POWERROLE	(1<<7)
-#define TCPC_REG_SWITCHES1_SPECREV1	(1<<6)
-#define TCPC_REG_SWITCHES1_SPECREV0	(1<<5)
-#define TCPC_REG_SWITCHES1_DATAROLE	(1<<4)
-#define TCPC_REG_SWITCHES1_AUTO_GCRC	(1<<2)
-#define TCPC_REG_SWITCHES1_TXCC2_EN	(1<<1)
-#define TCPC_REG_SWITCHES1_TXCC1_EN	(1<<0)
-
-#define TCPC_REG_MEASURE	0x04
-#define TCPC_REG_MEASURE_MDAC_MASK	0x3F
-#define TCPC_REG_MEASURE_VBUS		(1<<6)
+#define TCPC_REG_DEVICE_ID 0x01
+
+#define TCPC_REG_SWITCHES0 0x02
+#define TCPC_REG_SWITCHES0_CC2_PU_EN (1 << 7)
+#define TCPC_REG_SWITCHES0_CC1_PU_EN (1 << 6)
+#define TCPC_REG_SWITCHES0_VCONN_CC2 (1 << 5)
+#define TCPC_REG_SWITCHES0_VCONN_CC1 (1 << 4)
+#define TCPC_REG_SWITCHES0_MEAS_CC2 (1 << 3)
+#define TCPC_REG_SWITCHES0_MEAS_CC1 (1 << 2)
+#define TCPC_REG_SWITCHES0_CC2_PD_EN (1 << 1)
+#define TCPC_REG_SWITCHES0_CC1_PD_EN (1 << 0)
+
+#define TCPC_REG_SWITCHES1 0x03
+#define TCPC_REG_SWITCHES1_POWERROLE (1 << 7)
+#define TCPC_REG_SWITCHES1_SPECREV1 (1 << 6)
+#define TCPC_REG_SWITCHES1_SPECREV0 (1 << 5)
+#define TCPC_REG_SWITCHES1_DATAROLE (1 << 4)
+#define TCPC_REG_SWITCHES1_AUTO_GCRC (1 << 2)
+#define TCPC_REG_SWITCHES1_TXCC2_EN (1 << 1)
+#define TCPC_REG_SWITCHES1_TXCC1_EN (1 << 0)
+
+#define TCPC_REG_MEASURE 0x04
+#define TCPC_REG_MEASURE_MDAC_MASK 0x3F
+#define TCPC_REG_MEASURE_VBUS (1 << 6)
 /*
  * MDAC reference voltage step size is 42 mV. Round our thresholds to reduce
  * maximum error, which also matches suggested thresholds in datasheet
  * (Table 3. Host Interrupt Summary).
  */
-#define TCPC_REG_MEASURE_MDAC_MV(mv)	(DIV_ROUND_NEAREST((mv), 42) & 0x3f)
-
-#define TCPC_REG_CONTROL0	0x06
-#define TCPC_REG_CONTROL0_TX_FLUSH	(1<<6)
-#define TCPC_REG_CONTROL0_INT_MASK	(1<<5)
-#define TCPC_REG_CONTROL0_HOST_CUR_MASK (3<<2)
-#define TCPC_REG_CONTROL0_HOST_CUR_3A0  (3<<2)
-#define TCPC_REG_CONTROL0_HOST_CUR_1A5  (2<<2)
-#define TCPC_REG_CONTROL0_HOST_CUR_USB  (1<<2)
-#define TCPC_REG_CONTROL0_TX_START	(1<<0)
-
-#define TCPC_REG_CONTROL1	0x07
-#define TCPC_REG_CONTROL1_ENSOP2DB	(1<<6)
-#define TCPC_REG_CONTROL1_ENSOP1DB	(1<<5)
-#define TCPC_REG_CONTROL1_BIST_MODE2	(1<<4)
-#define TCPC_REG_CONTROL1_RX_FLUSH	(1<<2)
-#define TCPC_REG_CONTROL1_ENSOP2	(1<<1)
-#define TCPC_REG_CONTROL1_ENSOP1	(1<<0)
-
-#define TCPC_REG_CONTROL2	0x08
+#define TCPC_REG_MEASURE_MDAC_MV(mv) (DIV_ROUND_NEAREST((mv), 42) & 0x3f)
+
+#define TCPC_REG_CONTROL0 0x06
+#define TCPC_REG_CONTROL0_TX_FLUSH (1 << 6)
+#define TCPC_REG_CONTROL0_INT_MASK (1 << 5)
+#define TCPC_REG_CONTROL0_HOST_CUR_MASK (3 << 2)
+#define TCPC_REG_CONTROL0_HOST_CUR_3A0 (3 << 2)
+#define TCPC_REG_CONTROL0_HOST_CUR_1A5 (2 << 2)
+#define TCPC_REG_CONTROL0_HOST_CUR_USB (1 << 2)
+#define TCPC_REG_CONTROL0_TX_START (1 << 0)
+
+#define TCPC_REG_CONTROL1 0x07
+#define TCPC_REG_CONTROL1_ENSOP2DB (1 << 6)
+#define TCPC_REG_CONTROL1_ENSOP1DB (1 << 5)
+#define TCPC_REG_CONTROL1_BIST_MODE2 (1 << 4)
+#define TCPC_REG_CONTROL1_RX_FLUSH (1 << 2)
+#define TCPC_REG_CONTROL1_ENSOP2 (1 << 1)
+#define TCPC_REG_CONTROL1_ENSOP1 (1 << 0)
+
+#define TCPC_REG_CONTROL2 0x08
 /* two-bit field, valid values below */
-#define TCPC_REG_CONTROL2_MODE_MASK	(0x3<<TCPC_REG_CONTROL2_MODE_POS)
-#define TCPC_REG_CONTROL2_MODE_DFP	(0x3)
-#define TCPC_REG_CONTROL2_MODE_UFP	(0x2)
-#define TCPC_REG_CONTROL2_MODE_DRP	(0x1)
-#define TCPC_REG_CONTROL2_MODE_POS	(1)
-#define TCPC_REG_CONTROL2_TOGGLE	(1<<0)
-
-#define TCPC_REG_CONTROL3	0x09
-#define TCPC_REG_CONTROL3_SEND_HARDRESET	(1<<6)
-#define TCPC_REG_CONTROL3_BIST_TMODE		(1<<5) /* 302B Only */
-#define TCPC_REG_CONTROL3_AUTO_HARDRESET	(1<<4)
-#define TCPC_REG_CONTROL3_AUTO_SOFTRESET	(1<<3)
+#define TCPC_REG_CONTROL2_MODE_MASK (0x3 << TCPC_REG_CONTROL2_MODE_POS)
+#define TCPC_REG_CONTROL2_MODE_DFP (0x3)
+#define TCPC_REG_CONTROL2_MODE_UFP (0x2)
+#define TCPC_REG_CONTROL2_MODE_DRP (0x1)
+#define TCPC_REG_CONTROL2_MODE_POS (1)
+#define TCPC_REG_CONTROL2_TOGGLE (1 << 0)
+
+#define TCPC_REG_CONTROL3 0x09
+#define TCPC_REG_CONTROL3_SEND_HARDRESET (1 << 6)
+#define TCPC_REG_CONTROL3_BIST_TMODE (1 << 5) /* 302B Only */
+#define TCPC_REG_CONTROL3_AUTO_HARDRESET (1 << 4)
+#define TCPC_REG_CONTROL3_AUTO_SOFTRESET (1 << 3)
 /* two-bit field */
-#define TCPC_REG_CONTROL3_N_RETRIES		(1<<1)
-#define TCPC_REG_CONTROL3_N_RETRIES_POS		(1)
-#define TCPC_REG_CONTROL3_N_RETRIES_SIZE	(2)
-#define TCPC_REG_CONTROL3_AUTO_RETRY		(1<<0)
-
-#define TCPC_REG_MASK		0x0A
-#define TCPC_REG_MASK_VBUSOK		(1<<7)
-#define TCPC_REG_MASK_ACTIVITY		(1<<6)
-#define TCPC_REG_MASK_COMP_CHNG		(1<<5)
-#define TCPC_REG_MASK_CRC_CHK		(1<<4)
-#define TCPC_REG_MASK_ALERT		(1<<3)
-#define TCPC_REG_MASK_WAKE		(1<<2)
-#define TCPC_REG_MASK_COLLISION		(1<<1)
-#define TCPC_REG_MASK_BC_LVL		(1<<0)
-
-#define TCPC_REG_POWER		0x0B
-#define TCPC_REG_POWER_PWR		(1<<0)	/* four-bit field */
-#define TCPC_REG_POWER_PWR_LOW		0x1 /* Bandgap + Wake circuitry */
-#define TCPC_REG_POWER_PWR_MEDIUM	0x3 /* LOW + Receiver + Current refs */
-#define TCPC_REG_POWER_PWR_HIGH		0x7 /* MEDIUM + Measure block */
-#define TCPC_REG_POWER_PWR_ALL		0xF /* HIGH + Internal Oscillator */
-
-#define TCPC_REG_RESET		0x0C
-#define TCPC_REG_RESET_PD_RESET		(1<<1)
-#define TCPC_REG_RESET_SW_RESET		(1<<0)
-
-#define TCPC_REG_MASKA		0x0E
-#define TCPC_REG_MASKA_OCP_TEMP		(1<<7)
-#define TCPC_REG_MASKA_TOGDONE		(1<<6)
-#define TCPC_REG_MASKA_SOFTFAIL		(1<<5)
-#define TCPC_REG_MASKA_RETRYFAIL	(1<<4)
-#define TCPC_REG_MASKA_HARDSENT		(1<<3)
-#define TCPC_REG_MASKA_TX_SUCCESS	(1<<2)
-#define TCPC_REG_MASKA_SOFTRESET	(1<<1)
-#define TCPC_REG_MASKA_HARDRESET	(1<<0)
-
-#define TCPC_REG_MASKB		0x0F
-#define TCPC_REG_MASKB_GCRCSENT		(1<<0)
-
-#define TCPC_REG_STATUS0A	0x3C
-#define TCPC_REG_STATUS0A_SOFTFAIL	(1<<5)
-#define TCPC_REG_STATUS0A_RETRYFAIL	(1<<4)
-#define TCPC_REG_STATUS0A_POWER		(1<<2) /* two-bit field */
-#define TCPC_REG_STATUS0A_RX_SOFT_RESET	(1<<1)
-#define TCPC_REG_STATUS0A_RX_HARD_RESEt	(1<<0)
-
-#define TCPC_REG_STATUS1A	0x3D
+#define TCPC_REG_CONTROL3_N_RETRIES (1 << 1)
+#define TCPC_REG_CONTROL3_N_RETRIES_POS (1)
+#define TCPC_REG_CONTROL3_N_RETRIES_SIZE (2)
+#define TCPC_REG_CONTROL3_AUTO_RETRY (1 << 0)
+
+#define TCPC_REG_MASK 0x0A
+#define TCPC_REG_MASK_VBUSOK (1 << 7)
+#define TCPC_REG_MASK_ACTIVITY (1 << 6)
+#define TCPC_REG_MASK_COMP_CHNG (1 << 5)
+#define TCPC_REG_MASK_CRC_CHK (1 << 4)
+#define TCPC_REG_MASK_ALERT (1 << 3)
+#define TCPC_REG_MASK_WAKE (1 << 2)
+#define TCPC_REG_MASK_COLLISION (1 << 1)
+#define TCPC_REG_MASK_BC_LVL (1 << 0)
+
+#define TCPC_REG_POWER 0x0B
+#define TCPC_REG_POWER_PWR (1 << 0) /* four-bit field */
+#define TCPC_REG_POWER_PWR_LOW 0x1 /* Bandgap + Wake circuitry */
+#define TCPC_REG_POWER_PWR_MEDIUM 0x3 /* LOW + Receiver + Current refs */
+#define TCPC_REG_POWER_PWR_HIGH 0x7 /* MEDIUM + Measure block */
+#define TCPC_REG_POWER_PWR_ALL 0xF /* HIGH + Internal Oscillator */
+
+#define TCPC_REG_RESET 0x0C
+#define TCPC_REG_RESET_PD_RESET (1 << 1)
+#define TCPC_REG_RESET_SW_RESET (1 << 0)
+
+#define TCPC_REG_MASKA 0x0E
+#define TCPC_REG_MASKA_OCP_TEMP (1 << 7)
+#define TCPC_REG_MASKA_TOGDONE (1 << 6)
+#define TCPC_REG_MASKA_SOFTFAIL (1 << 5)
+#define TCPC_REG_MASKA_RETRYFAIL (1 << 4)
+#define TCPC_REG_MASKA_HARDSENT (1 << 3)
+#define TCPC_REG_MASKA_TX_SUCCESS (1 << 2)
+#define TCPC_REG_MASKA_SOFTRESET (1 << 1)
+#define TCPC_REG_MASKA_HARDRESET (1 << 0)
+
+#define TCPC_REG_MASKB 0x0F
+#define TCPC_REG_MASKB_GCRCSENT (1 << 0)
+
+#define TCPC_REG_STATUS0A 0x3C
+#define TCPC_REG_STATUS0A_SOFTFAIL (1 << 5)
+#define TCPC_REG_STATUS0A_RETRYFAIL (1 << 4)
+#define TCPC_REG_STATUS0A_POWER (1 << 2) /* two-bit field */
+#define TCPC_REG_STATUS0A_RX_SOFT_RESET (1 << 1)
+#define TCPC_REG_STATUS0A_RX_HARD_RESEt (1 << 0)
+
+#define TCPC_REG_STATUS1A 0x3D
 /* three-bit field, valid values below */
-#define TCPC_REG_STATUS1A_TOGSS		(1<<3)
-#define TCPC_REG_STATUS1A_TOGSS_RUNNING		0x0
-#define TCPC_REG_STATUS1A_TOGSS_SRC1		0x1
-#define TCPC_REG_STATUS1A_TOGSS_SRC2		0x2
-#define TCPC_REG_STATUS1A_TOGSS_SNK1		0x5
-#define TCPC_REG_STATUS1A_TOGSS_SNK2		0x6
-#define TCPC_REG_STATUS1A_TOGSS_AA		0x7
-#define TCPC_REG_STATUS1A_TOGSS_POS		(3)
-#define TCPC_REG_STATUS1A_TOGSS_MASK		(0x7)
-
-#define TCPC_REG_STATUS1A_RXSOP2DB	(1<<2)
-#define TCPC_REG_STATUS1A_RXSOP1DB	(1<<1)
-#define TCPC_REG_STATUS1A_RXSOP		(1<<0)
-
-#define TCPC_REG_INTERRUPTA	0x3E
-#define TCPC_REG_INTERRUPTA_OCP_TEMP	(1<<7)
-#define TCPC_REG_INTERRUPTA_TOGDONE	(1<<6)
-#define TCPC_REG_INTERRUPTA_SOFTFAIL	(1<<5)
-#define TCPC_REG_INTERRUPTA_RETRYFAIL	(1<<4)
-#define TCPC_REG_INTERRUPTA_HARDSENT	(1<<3)
-#define TCPC_REG_INTERRUPTA_TX_SUCCESS	(1<<2)
-#define TCPC_REG_INTERRUPTA_SOFTRESET	(1<<1)
-#define TCPC_REG_INTERRUPTA_HARDRESET	(1<<0)
-
-#define TCPC_REG_INTERRUPTB	0x3F
-#define TCPC_REG_INTERRUPTB_GCRCSENT		(1<<0)
-
-#define TCPC_REG_STATUS0	0x40
-#define TCPC_REG_STATUS0_VBUSOK		(1<<7)
-#define TCPC_REG_STATUS0_ACTIVITY	(1<<6)
-#define TCPC_REG_STATUS0_COMP		(1<<5)
-#define TCPC_REG_STATUS0_CRC_CHK	(1<<4)
-#define TCPC_REG_STATUS0_ALERT		(1<<3)
-#define TCPC_REG_STATUS0_WAKE		(1<<2)
-#define TCPC_REG_STATUS0_BC_LVL1	(1<<1) /* two-bit field */
-#define TCPC_REG_STATUS0_BC_LVL0	(1<<0) /* two-bit field */
-
-#define TCPC_REG_STATUS1	0x41
-#define TCPC_REG_STATUS1_RXSOP2		(1<<7)
-#define TCPC_REG_STATUS1_RXSOP1		(1<<6)
-#define TCPC_REG_STATUS1_RX_EMPTY	(1<<5)
-#define TCPC_REG_STATUS1_RX_FULL	(1<<4)
-#define TCPC_REG_STATUS1_TX_EMPTY	(1<<3)
-#define TCPC_REG_STATUS1_TX_FULL	(1<<2)
-
-#define TCPC_REG_INTERRUPT	0x42
-#define TCPC_REG_INTERRUPT_VBUSOK	(1<<7)
-#define TCPC_REG_INTERRUPT_ACTIVITY	(1<<6)
-#define TCPC_REG_INTERRUPT_COMP_CHNG	(1<<5)
-#define TCPC_REG_INTERRUPT_CRC_CHK	(1<<4)
-#define TCPC_REG_INTERRUPT_ALERT	(1<<3)
-#define TCPC_REG_INTERRUPT_WAKE		(1<<2)
-#define TCPC_REG_INTERRUPT_COLLISION	(1<<1)
-#define TCPC_REG_INTERRUPT_BC_LVL	(1<<0)
-
-#define TCPC_REG_FIFOS		0x43
+#define TCPC_REG_STATUS1A_TOGSS (1 << 3)
+#define TCPC_REG_STATUS1A_TOGSS_RUNNING 0x0
+#define TCPC_REG_STATUS1A_TOGSS_SRC1 0x1
+#define TCPC_REG_STATUS1A_TOGSS_SRC2 0x2
+#define TCPC_REG_STATUS1A_TOGSS_SNK1 0x5
+#define TCPC_REG_STATUS1A_TOGSS_SNK2 0x6
+#define TCPC_REG_STATUS1A_TOGSS_AA 0x7
+#define TCPC_REG_STATUS1A_TOGSS_POS (3)
+#define TCPC_REG_STATUS1A_TOGSS_MASK (0x7)
+
+#define TCPC_REG_STATUS1A_RXSOP2DB (1 << 2)
+#define TCPC_REG_STATUS1A_RXSOP1DB (1 << 1)
+#define TCPC_REG_STATUS1A_RXSOP (1 << 0)
+
+#define TCPC_REG_INTERRUPTA 0x3E
+#define TCPC_REG_INTERRUPTA_OCP_TEMP (1 << 7)
+#define TCPC_REG_INTERRUPTA_TOGDONE (1 << 6)
+#define TCPC_REG_INTERRUPTA_SOFTFAIL (1 << 5)
+#define TCPC_REG_INTERRUPTA_RETRYFAIL (1 << 4)
+#define TCPC_REG_INTERRUPTA_HARDSENT (1 << 3)
+#define TCPC_REG_INTERRUPTA_TX_SUCCESS (1 << 2)
+#define TCPC_REG_INTERRUPTA_SOFTRESET (1 << 1)
+#define TCPC_REG_INTERRUPTA_HARDRESET (1 << 0)
+
+#define TCPC_REG_INTERRUPTB 0x3F
+#define TCPC_REG_INTERRUPTB_GCRCSENT (1 << 0)
+
+#define TCPC_REG_STATUS0 0x40
+#define TCPC_REG_STATUS0_VBUSOK (1 << 7)
+#define TCPC_REG_STATUS0_ACTIVITY (1 << 6)
+#define TCPC_REG_STATUS0_COMP (1 << 5)
+#define TCPC_REG_STATUS0_CRC_CHK (1 << 4)
+#define TCPC_REG_STATUS0_ALERT (1 << 3)
+#define TCPC_REG_STATUS0_WAKE (1 << 2)
+#define TCPC_REG_STATUS0_BC_LVL1 (1 << 1) /* two-bit field */
+#define TCPC_REG_STATUS0_BC_LVL0 (1 << 0) /* two-bit field */
+
+#define TCPC_REG_STATUS1 0x41
+#define TCPC_REG_STATUS1_RXSOP2 (1 << 7)
+#define TCPC_REG_STATUS1_RXSOP1 (1 << 6)
+#define TCPC_REG_STATUS1_RX_EMPTY (1 << 5)
+#define TCPC_REG_STATUS1_RX_FULL (1 << 4)
+#define TCPC_REG_STATUS1_TX_EMPTY (1 << 3)
+#define TCPC_REG_STATUS1_TX_FULL (1 << 2)
+
+#define TCPC_REG_INTERRUPT 0x42
+#define TCPC_REG_INTERRUPT_VBUSOK (1 << 7)
+#define TCPC_REG_INTERRUPT_ACTIVITY (1 << 6)
+#define TCPC_REG_INTERRUPT_COMP_CHNG (1 << 5)
+#define TCPC_REG_INTERRUPT_CRC_CHK (1 << 4)
+#define TCPC_REG_INTERRUPT_ALERT (1 << 3)
+#define TCPC_REG_INTERRUPT_WAKE (1 << 2)
+#define TCPC_REG_INTERRUPT_COLLISION (1 << 1)
+#define TCPC_REG_INTERRUPT_BC_LVL (1 << 0)
+
+#define TCPC_REG_FIFOS 0x43
 
 /* Tokens defined for the FUSB302 TX FIFO */
 enum fusb302_txfifo_tokens {
diff --git a/driver/tcpm/fusb307.c b/driver/tcpm/fusb307.c
index 3569032805..2573e81fb3 100644
--- a/driver/tcpm/fusb307.c
+++ b/driver/tcpm/fusb307.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,8 +14,8 @@
 #include "timer.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 int fusb307_power_supply_reset(int port)
 {
@@ -44,25 +44,29 @@ int fusb307_tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity)
 	tcpm_get_cc(port, &cc1, &cc2);
 	if (cc1) {
 		if (pd_get_power_role(port) == PD_ROLE_SINK) {
-			int role = TCPC_REG_ROLE_CTRL_SET(0,
-			tcpci_get_cached_rp(port), TYPEC_CC_RD, TYPEC_CC_OPEN);
+			int role = TCPC_REG_ROLE_CTRL_SET(
+				0, tcpci_get_cached_rp(port), TYPEC_CC_RD,
+				TYPEC_CC_OPEN);
 
 			tcpc_write(port, TCPC_REG_ROLE_CTRL, role);
 		} else {
-			int role = TCPC_REG_ROLE_CTRL_SET(0,
-			tcpci_get_cached_rp(port), TYPEC_CC_RP, TYPEC_CC_OPEN);
+			int role = TCPC_REG_ROLE_CTRL_SET(
+				0, tcpci_get_cached_rp(port), TYPEC_CC_RP,
+				TYPEC_CC_OPEN);
 
 			tcpc_write(port, TCPC_REG_ROLE_CTRL, role);
 		}
 	} else if (cc2) {
 		if (pd_get_power_role(port) == PD_ROLE_SINK) {
-			int role = TCPC_REG_ROLE_CTRL_SET(0,
-			tcpci_get_cached_rp(port), TYPEC_CC_OPEN, TYPEC_CC_RD);
+			int role = TCPC_REG_ROLE_CTRL_SET(
+				0, tcpci_get_cached_rp(port), TYPEC_CC_OPEN,
+				TYPEC_CC_RD);
 
 			tcpc_write(port, TCPC_REG_ROLE_CTRL, role);
 		} else {
-			int role = TCPC_REG_ROLE_CTRL_SET(0,
-			tcpci_get_cached_rp(port), TYPEC_CC_OPEN, TYPEC_CC_RP);
+			int role = TCPC_REG_ROLE_CTRL_SET(
+				0, tcpci_get_cached_rp(port), TYPEC_CC_OPEN,
+				TYPEC_CC_RP);
 
 			tcpc_write(port, TCPC_REG_ROLE_CTRL, role);
 		}
@@ -77,26 +81,27 @@ int fusb307_tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity)
 }
 
 const struct tcpm_drv fusb307_tcpm_drv = {
-	.init			= &fusb307_tcpm_init,
-	.release		= &tcpci_tcpm_release,
-	.get_cc			= &tcpci_tcpm_get_cc,
+	.init = &fusb307_tcpm_init,
+	.release = &tcpci_tcpm_release,
+	.get_cc = &tcpci_tcpm_get_cc,
 #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	.check_vbus_level	= &tcpci_tcpm_check_vbus_level,
+	.check_vbus_level = &tcpci_tcpm_check_vbus_level,
 #endif
-	.select_rp_value	= &tcpci_tcpm_select_rp_value,
-	.set_cc			= &tcpci_tcpm_set_cc,
-	.set_polarity		= &fusb307_tcpm_set_polarity,
-	.set_vconn		= &tcpci_tcpm_set_vconn,
-	.set_msg_header		= &tcpci_tcpm_set_msg_header,
-	.set_rx_enable		= &tcpci_tcpm_set_rx_enable,
-	.get_message_raw	= &tcpci_tcpm_get_message_raw,
-	.transmit		= &tcpci_tcpm_transmit,
-	.tcpc_alert		= &tcpci_tcpc_alert,
+	.select_rp_value = &tcpci_tcpm_select_rp_value,
+	.set_cc = &tcpci_tcpm_set_cc,
+	.set_polarity = &fusb307_tcpm_set_polarity,
+	.set_vconn = &tcpci_tcpm_set_vconn,
+	.set_msg_header = &tcpci_tcpm_set_msg_header,
+	.set_rx_enable = &tcpci_tcpm_set_rx_enable,
+	.get_message_raw = &tcpci_tcpm_get_message_raw,
+	.transmit = &tcpci_tcpm_transmit,
+	.tcpc_alert = &tcpci_tcpc_alert,
 	.tcpc_enable_auto_discharge_disconnect =
-				  &tcpci_tcpc_enable_auto_discharge_disconnect,
-	.get_chip_info		= &tcpci_get_chip_info,
+		&tcpci_tcpc_enable_auto_discharge_disconnect,
+	.get_chip_info = &tcpci_get_chip_info,
 #if defined(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE)
-	.drp_toggle		= &tcpci_tcpc_drp_toggle,
+	.drp_toggle = &tcpci_tcpc_drp_toggle,
 #endif
-	.set_bist_test_mode	= &tcpci_set_bist_test_mode,
+	.set_bist_test_mode = &tcpci_set_bist_test_mode,
+	.get_bist_test_mode = &tcpci_get_bist_test_mode,
 };
diff --git a/driver/tcpm/fusb307.h b/driver/tcpm/fusb307.h
index 3f1f12901d..38114c8caa 100644
--- a/driver/tcpm/fusb307.h
+++ b/driver/tcpm/fusb307.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,14 +12,14 @@
 
 #define FUSB307_I2C_ADDR_FLAGS 0x50
 
-#define TCPC_REG_RESET		0xA2
-#define TCPC_REG_RESET_PD_RESET	BIT(1)
-#define TCPC_REG_RESET_SW_RESET	BIT(0)
+#define TCPC_REG_RESET 0xA2
+#define TCPC_REG_RESET_PD_RESET BIT(1)
+#define TCPC_REG_RESET_SW_RESET BIT(0)
 
-#define TCPC_REG_GPIO1_CFG		0xA4
-#define TCPC_REG_GPIO1_CFG_GPO1_VAL	BIT(2)
-#define TCPC_REG_GPIO1_CFG_GPI1_EN	BIT(1)
-#define TCPC_REG_GPIO1_CFG_GPO1_EN	BIT(0)
+#define TCPC_REG_GPIO1_CFG 0xA4
+#define TCPC_REG_GPIO1_CFG_GPO1_VAL BIT(2)
+#define TCPC_REG_GPIO1_CFG_GPI1_EN BIT(1)
+#define TCPC_REG_GPIO1_CFG_GPO1_EN BIT(0)
 
 int fusb307_power_supply_reset(int port);
 
diff --git a/driver/tcpm/it83xx.c b/driver/tcpm/it83xx.c
index c809cce153..0b636e2e89 100644
--- a/driver/tcpm/it83xx.c
+++ b/driver/tcpm/it83xx.c
@@ -1,10 +1,11 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* TCPM for MCU also running TCPC */
 
+#include "builtin/assert.h"
 #include "common.h"
 #include "config.h"
 #include "console.h"
@@ -22,8 +23,8 @@
 
 #ifdef CONFIG_USB_PD_TCPMV1
 #if defined(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE) || \
-	defined(CONFIG_USB_PD_VBUS_DETECT_TCPC) || \
-	defined(CONFIG_USB_PD_TCPC_LOW_POWER) || \
+	defined(CONFIG_USB_PD_VBUS_DETECT_TCPC) ||  \
+	defined(CONFIG_USB_PD_TCPC_LOW_POWER) ||    \
 	defined(CONFIG_USB_PD_DISCHARGE_TCPC)
 #error "Unsupported config options of IT83xx PD driver"
 #endif
@@ -38,11 +39,11 @@
 
 int rx_en[IT83XX_USBPD_PHY_PORT_COUNT];
 STATIC_IF(CONFIG_USB_PD_DECODE_SOP)
-	bool sop_prime_en[IT83XX_USBPD_PHY_PORT_COUNT];
+bool sop_prime_en[IT83XX_USBPD_PHY_PORT_COUNT];
 
 const struct usbpd_ctrl_t usbpd_ctrl_regs[] = {
-	{&IT83XX_GPIO_GPCRF4, &IT83XX_GPIO_GPCRF5, IT83XX_IRQ_USBPD0},
-	{&IT83XX_GPIO_GPCRH1, &IT83XX_GPIO_GPCRH2, IT83XX_IRQ_USBPD1},
+	{ &IT83XX_GPIO_GPCRF4, &IT83XX_GPIO_GPCRF5, IT83XX_IRQ_USBPD0 },
+	{ &IT83XX_GPIO_GPCRH1, &IT83XX_GPIO_GPCRH2, IT83XX_IRQ_USBPD1 },
 };
 BUILD_ASSERT(ARRAY_SIZE(usbpd_ctrl_regs) == IT83XX_USBPD_PHY_PORT_COUNT);
 
@@ -58,7 +59,7 @@ void it83xx_Rd_5_1K_only_for_hibernate(int port)
 {
 	/* This only apply to active PD port */
 	if (*usbpd_ctrl_regs[port].cc1 == IT83XX_USBPD_CC_PIN_CONFIG &&
-		*usbpd_ctrl_regs[port].cc2 == IT83XX_USBPD_CC_PIN_CONFIG) {
+	    *usbpd_ctrl_regs[port].cc2 == IT83XX_USBPD_CC_PIN_CONFIG) {
 		/* Disable PD PHY */
 		IT83XX_USBPD_GCR(port) &= ~(BIT(0) | BIT(4));
 		/*
@@ -81,9 +82,8 @@ void it83xx_Rd_5_1K_only_for_hibernate(int port)
 	}
 }
 
-static enum tcpc_cc_voltage_status it83xx_get_cc(
-	enum usbpd_port port,
-	enum usbpd_cc_pin cc_pin)
+static enum tcpc_cc_voltage_status it83xx_get_cc(enum usbpd_port port,
+						 enum usbpd_cc_pin cc_pin)
 {
 	enum usbpd_ufp_volt_status ufp_volt;
 	enum usbpd_dfp_volt_status dfp_volt;
@@ -91,8 +91,8 @@ static enum tcpc_cc_voltage_status it83xx_get_cc(
 	int pull;
 
 	pull = (cc_pin == USBPD_CC_PIN_1) ?
-		USBPD_GET_CC1_PULL_REGISTER_SELECTION(port) :
-		USBPD_GET_CC2_PULL_REGISTER_SELECTION(port);
+		       USBPD_GET_CC1_PULL_REGISTER_SELECTION(port) :
+		       USBPD_GET_CC2_PULL_REGISTER_SELECTION(port);
 
 	/* select Rp */
 	if (pull)
@@ -125,7 +125,7 @@ static enum tcpc_cc_voltage_status it83xx_get_cc(
 			cc_state = TYPEC_CC_VOLT_OPEN;
 			break;
 		}
-	/* source */
+		/* source */
 	} else {
 		if (cc_pin == USBPD_CC_PIN_1)
 			dfp_volt = IT83XX_USBPD_DFPVDR(port) & 0xf;
@@ -177,11 +177,10 @@ static int it83xx_tcpm_get_message_raw(int port, uint32_t *buf, int *head)
 	return EC_SUCCESS;
 }
 
-static enum tcpc_transmit_complete it83xx_tx_data(
-	enum usbpd_port port,
-	enum tcpci_msg_type type,
-	uint16_t header,
-	const uint32_t *buf)
+static enum tcpc_transmit_complete it83xx_tx_data(enum usbpd_port port,
+						  enum tcpci_msg_type type,
+						  uint16_t header,
+						  const uint32_t *buf)
 {
 	int r;
 	uint32_t evt;
@@ -198,8 +197,8 @@ static enum tcpc_transmit_complete it83xx_tx_data(
 	 * on dx version:
 	 * 000b=SOP, 001b=SOP', 010b=SOP", 011b=Debug SOP', 100b=Debug SOP''.
 	 */
-	IT83XX_USBPD_MTSR1(port) =
-		(IT83XX_USBPD_MTSR1(port) & ~0x70) | ((type & 0x7) << 4);
+	IT83XX_USBPD_MTSR1(port) = (IT83XX_USBPD_MTSR1(port) & ~0x70) |
+				   ((type & 0x7) << 4);
 	/* bit7: transmit message is send to cable or not */
 	if (type == TCPCI_MSG_SOP)
 		IT83XX_USBPD_MTSR0(port) &= ~USBPD_REG_MASK_CABLE_ENABLE;
@@ -223,7 +222,7 @@ static enum tcpc_transmit_complete it83xx_tx_data(
 		/* Start TX */
 		USBPD_KICK_TX_START(port);
 		evt = task_wait_event_mask(TASK_EVENT_PHY_TX_DONE,
-					PD_T_TCPC_TX_TIMEOUT);
+					   PD_T_TCPC_TX_TIMEOUT);
 		/* check TX status */
 		if (USBPD_IS_TX_ERR(port) || (evt & TASK_EVENT_TIMER)) {
 			/*
@@ -247,8 +246,8 @@ static enum tcpc_transmit_complete it83xx_tx_data(
 	return TCPC_TX_COMPLETE_SUCCESS;
 }
 
-static enum tcpc_transmit_complete it83xx_send_hw_reset(enum usbpd_port port,
-				enum tcpci_msg_type reset_type)
+static enum tcpc_transmit_complete
+it83xx_send_hw_reset(enum usbpd_port port, enum tcpci_msg_type reset_type)
 {
 	if (reset_type == TCPCI_MSG_CABLE_RESET)
 		IT83XX_USBPD_MTSR0(port) |= USBPD_REG_MASK_CABLE_ENABLE;
@@ -288,21 +287,23 @@ static void it83xx_enable_vconn(enum usbpd_port port, int enabled)
 		/* Disable unused CC to become VCONN */
 		if (cc_pin == USBPD_CC_PIN_1) {
 			IT83XX_USBPD_CCCSR(port) = USBPD_CC2_DISCONNECTED(port);
-			IT83XX_USBPD_CCPSR(port) = (IT83XX_USBPD_CCPSR(port)
-				& ~USBPD_REG_MASK_DISCONNECT_POWER_CC2)
-				| USBPD_REG_MASK_DISCONNECT_POWER_CC1;
+			IT83XX_USBPD_CCPSR(port) =
+				(IT83XX_USBPD_CCPSR(port) &
+				 ~USBPD_REG_MASK_DISCONNECT_POWER_CC2) |
+				USBPD_REG_MASK_DISCONNECT_POWER_CC1;
 		} else {
 			IT83XX_USBPD_CCCSR(port) = USBPD_CC1_DISCONNECTED(port);
-			IT83XX_USBPD_CCPSR(port) = (IT83XX_USBPD_CCPSR(port)
-				& ~USBPD_REG_MASK_DISCONNECT_POWER_CC1)
-				| USBPD_REG_MASK_DISCONNECT_POWER_CC2;
+			IT83XX_USBPD_CCPSR(port) =
+				(IT83XX_USBPD_CCPSR(port) &
+				 ~USBPD_REG_MASK_DISCONNECT_POWER_CC1) |
+				USBPD_REG_MASK_DISCONNECT_POWER_CC2;
 		}
 	} else {
 		/* Enable cc1 and cc2 */
 		IT83XX_USBPD_CCCSR(port) &= ~0xaa;
 		IT83XX_USBPD_CCPSR(port) |=
 			(USBPD_REG_MASK_DISCONNECT_POWER_CC1 |
-			USBPD_REG_MASK_DISCONNECT_POWER_CC2);
+			 USBPD_REG_MASK_DISCONNECT_POWER_CC2);
 	}
 }
 
@@ -359,8 +360,8 @@ static void it83xx_set_power_role(enum usbpd_port port, int power_role)
 static void it83xx_set_data_role(enum usbpd_port port, int pd_role)
 {
 	/* 0: PD_ROLE_UFP 1: PD_ROLE_DFP */
-	IT83XX_USBPD_PDMSR(port) =
-		(IT83XX_USBPD_PDMSR(port) & ~0xc) | ((pd_role & 0x1) << 2);
+	IT83XX_USBPD_PDMSR(port) = (IT83XX_USBPD_PDMSR(port) & ~0xc) |
+				   ((pd_role & 0x1) << 2);
 }
 
 #ifdef CONFIG_USB_PD_FRS_TCPC
@@ -378,15 +379,18 @@ static int it83xx_tcpm_set_frs_enable(int port, int enable)
 		/* W/C status */
 		IT83XX_USBPD_PD30IR(port) = 0x3f;
 		/* Enable FRS detection (cc to GND) interrupt */
-		IT83XX_USBPD_MPD30IR(port) &= ~(USBPD_REG_MASK_PD30_ISR |
-					USBPD_REG_MASK_FAST_SWAP_DETECT_ISR);
+		IT83XX_USBPD_MPD30IR(port) &=
+			~(USBPD_REG_MASK_PD30_ISR |
+			  USBPD_REG_MASK_FAST_SWAP_DETECT_ISR);
 		/* Enable FRS detection (cc to GND) */
-		IT83XX_USBPD_PDQSCR(port) = (IT83XX_USBPD_PDQSCR(port) & ~mask)
-					| USBPD_REG_FAST_SWAP_DETECT_ENABLE;
+		IT83XX_USBPD_PDQSCR(port) =
+			(IT83XX_USBPD_PDQSCR(port) & ~mask) |
+			USBPD_REG_FAST_SWAP_DETECT_ENABLE;
 	} else {
 		/* Disable FRS detection (cc to GND) interrupt */
-		IT83XX_USBPD_MPD30IR(port) |= (USBPD_REG_MASK_PD30_ISR |
-					USBPD_REG_MASK_FAST_SWAP_DETECT_ISR);
+		IT83XX_USBPD_MPD30IR(port) |=
+			(USBPD_REG_MASK_PD30_ISR |
+			 USBPD_REG_MASK_FAST_SWAP_DETECT_ISR);
 		/* Disable FRS detection and requestion */
 		IT83XX_USBPD_PDQSCR(port) &= ~mask;
 	}
@@ -409,7 +413,7 @@ static void it83xx_init(enum usbpd_port port, int role)
 	 * (= retry count + 1)
 	 */
 	IT83XX_USBPD_BMCSR(port) = (IT83XX_USBPD_BMCSR(port) & ~0x70) |
-					((CONFIG_PD_RETRY_COUNT + 1) << 4);
+				   ((CONFIG_PD_RETRY_COUNT + 1) << 4);
 	/* Disable Rx decode */
 	it83xx_tcpm_set_rx_enable(port, 0);
 	if (IS_ENABLED(CONFIG_USB_PD_TCPMV1)) {
@@ -440,7 +444,7 @@ static void it83xx_init(enum usbpd_port port, int role)
 	IT83XX_USBPD_IMR(port) = 0xff;
 	/* enable tx done and reset detect interrupt */
 	IT83XX_USBPD_IMR(port) &= ~(USBPD_REG_MASK_MSG_TX_DONE |
-					USBPD_REG_MASK_HARD_RESET_DETECT);
+				    USBPD_REG_MASK_HARD_RESET_DETECT);
 #ifdef IT83XX_INTC_PLUG_IN_OUT_SUPPORT
 	/*
 	 * when tcpc detect type-c plug in (cc lines voltage change), it will
@@ -473,7 +477,7 @@ static void it83xx_init(enum usbpd_port port, int role)
 }
 
 static void it83xx_select_polarity(enum usbpd_port port,
-					enum usbpd_cc_pin cc_pin)
+				   enum usbpd_cc_pin cc_pin)
 {
 	/* cc1/cc2 selection */
 	if (cc_pin == USBPD_CC_PIN_1)
@@ -519,7 +523,7 @@ static int it83xx_tcpm_release(int port)
 }
 
 static int it83xx_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2)
+			      enum tcpc_cc_voltage_status *cc2)
 {
 	*cc2 = it83xx_get_cc(port, USBPD_CC_PIN_2);
 	*cc1 = it83xx_get_cc(port, USBPD_CC_PIN_1);
@@ -567,7 +571,8 @@ static int it83xx_tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity)
 {
 	enum usbpd_cc_pin cc_pin =
 		(polarity == POLARITY_CC1 || polarity == POLARITY_CC1_DTS) ?
-		USBPD_CC_PIN_1 : USBPD_CC_PIN_2;
+			USBPD_CC_PIN_1 :
+			USBPD_CC_PIN_2;
 
 	it83xx_select_polarity(port, cc_pin);
 
@@ -613,7 +618,8 @@ static int it83xx_tcpm_set_vconn(int port, int enable)
 			/* Turn on Vconn power switch. */
 			board_pd_vconn_ctrl(port,
 					    USBPD_GET_PULL_CC_SELECTION(port) ?
-					    USBPD_CC_PIN_2 : USBPD_CC_PIN_1,
+						    USBPD_CC_PIN_2 :
+						    USBPD_CC_PIN_1,
 					    enable);
 		} else {
 			/*
@@ -685,10 +691,8 @@ static int it83xx_tcpm_set_rx_enable(int port, int enable)
 	return EC_SUCCESS;
 }
 
-static int it83xx_tcpm_transmit(int port,
-			enum tcpci_msg_type type,
-			uint16_t header,
-			const uint32_t *data)
+static int it83xx_tcpm_transmit(int port, enum tcpci_msg_type type,
+				uint16_t header, const uint32_t *data)
 {
 	int status = TCPC_TX_COMPLETE_FAILED;
 
@@ -698,10 +702,7 @@ static int it83xx_tcpm_transmit(int port,
 	case TCPCI_MSG_SOP_PRIME_PRIME:
 	case TCPCI_MSG_SOP_DEBUG_PRIME:
 	case TCPCI_MSG_SOP_DEBUG_PRIME_PRIME:
-		status = it83xx_tx_data(port,
-					type,
-					header,
-					data);
+		status = it83xx_tx_data(port, type, header, data);
 		break;
 	case TCPCI_MSG_TX_BIST_MODE_2:
 		it83xx_send_bist_mode2_pattern(port);
@@ -720,12 +721,13 @@ static int it83xx_tcpm_transmit(int port,
 	return EC_SUCCESS;
 }
 
-static int it83xx_tcpm_get_chip_info(int port, int live,
-			struct ec_response_pd_chip_info_v1 *chip_info)
+static int
+it83xx_tcpm_get_chip_info(int port, int live,
+			  struct ec_response_pd_chip_info_v1 *chip_info)
 {
 	chip_info->vendor_id = USB_VID_ITE;
-	chip_info->product_id = ((IT83XX_GCTRL_CHIPID1 << 8) |
-				 IT83XX_GCTRL_CHIPID2);
+	chip_info->product_id =
+		((IT83XX_GCTRL_CHIPID1 << 8) | IT83XX_GCTRL_CHIPID2);
 	chip_info->device_id = IT83XX_GCTRL_CHIPVER & 0xf;
 	chip_info->fw_version_number = 0xEC;
 
@@ -757,16 +759,18 @@ static void it83xx_tcpm_switch_plug_out_type(int port)
 	if ((cc1 == TYPEC_CC_VOLT_RD && cc2 == TYPEC_CC_VOLT_RD) ||
 	    (cc1 == TYPEC_CC_VOLT_RA && cc2 == TYPEC_CC_VOLT_RA))
 		/* We're source, switch to detect audio/debug plug out. */
-		IT83XX_USBPD_TCDCR(port) = (IT83XX_USBPD_TCDCR(port) &
-				~USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE) |
-				USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT |
-				USBPD_REG_PLUG_OUT_SELECT;
+		IT83XX_USBPD_TCDCR(port) =
+			(IT83XX_USBPD_TCDCR(port) &
+			 ~USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE) |
+			USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT |
+			USBPD_REG_PLUG_OUT_SELECT;
 	else if (cc1 == TYPEC_CC_VOLT_RD || cc2 == TYPEC_CC_VOLT_RD)
 		/* We're source, switch to detect sink plug out. */
-		IT83XX_USBPD_TCDCR(port) = (IT83XX_USBPD_TCDCR(port) &
-				~USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE &
-				~USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT) |
-				USBPD_REG_PLUG_OUT_SELECT;
+		IT83XX_USBPD_TCDCR(port) =
+			(IT83XX_USBPD_TCDCR(port) &
+			 ~USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE &
+			 ~USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT) |
+			USBPD_REG_PLUG_OUT_SELECT;
 	else if (cc1 >= TYPEC_CC_VOLT_RP_DEF || cc2 >= TYPEC_CC_VOLT_RP_DEF)
 		/*
 		 * We're sink, disable detect interrupt, so messages on cc line
@@ -891,8 +895,9 @@ static void it83xx_tcpm_hook_disconnect(void)
 		 * Switch to detect plug in and enable detect plug in interrupt,
 		 * since pd task has detected a type-c physical disconnected.
 		 */
-		IT83XX_USBPD_TCDCR(port) &= ~(USBPD_REG_PLUG_OUT_SELECT |
-			USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE);
+		IT83XX_USBPD_TCDCR(port) &=
+			~(USBPD_REG_PLUG_OUT_SELECT |
+			  USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE);
 
 	/* exit BIST test data mode */
 	USBPD_SW_RESET(port);
@@ -916,28 +921,28 @@ DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, it83xx_tcpm_hook_disconnect,
 	     HOOK_PRIO_DEFAULT);
 
 const struct tcpm_drv it83xx_tcpm_drv = {
-	.init			= &it83xx_tcpm_init,
-	.release		= &it83xx_tcpm_release,
-	.get_cc			= &it83xx_tcpm_get_cc,
-	.select_rp_value	= &it83xx_tcpm_select_rp_value,
-	.set_cc			= &it83xx_tcpm_set_cc,
-	.set_polarity		= &it83xx_tcpm_set_polarity,
+	.init = &it83xx_tcpm_init,
+	.release = &it83xx_tcpm_release,
+	.get_cc = &it83xx_tcpm_get_cc,
+	.select_rp_value = &it83xx_tcpm_select_rp_value,
+	.set_cc = &it83xx_tcpm_set_cc,
+	.set_polarity = &it83xx_tcpm_set_polarity,
 #ifdef CONFIG_USB_PD_DECODE_SOP
-	.sop_prime_enable	= &it83xx_tcpm_decode_sop_prime_enable,
+	.sop_prime_enable = &it83xx_tcpm_decode_sop_prime_enable,
 #endif
-	.set_vconn		= &it83xx_tcpm_set_vconn,
-	.set_msg_header		= &it83xx_tcpm_set_msg_header,
-	.set_rx_enable		= &it83xx_tcpm_set_rx_enable,
-	.get_message_raw	= &it83xx_tcpm_get_message_raw,
-	.transmit		= &it83xx_tcpm_transmit,
+	.set_vconn = &it83xx_tcpm_set_vconn,
+	.set_msg_header = &it83xx_tcpm_set_msg_header,
+	.set_rx_enable = &it83xx_tcpm_set_rx_enable,
+	.get_message_raw = &it83xx_tcpm_get_message_raw,
+	.transmit = &it83xx_tcpm_transmit,
 #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-	.drp_toggle		= NULL,
+	.drp_toggle = NULL,
 #endif
-	.get_chip_info		= &it83xx_tcpm_get_chip_info,
+	.get_chip_info = &it83xx_tcpm_get_chip_info,
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	.enter_low_power_mode	= &it83xx_tcpm_enter_low_power_mode,
+	.enter_low_power_mode = &it83xx_tcpm_enter_low_power_mode,
 #endif
 #ifdef CONFIG_USB_PD_FRS_TCPC
-	.set_frs_enable		= &it83xx_tcpm_set_frs_enable,
+	.set_frs_enable = &it83xx_tcpm_set_frs_enable,
 #endif
 };
diff --git a/driver/tcpm/it83xx_pd.h b/driver/tcpm/it83xx_pd.h
index 9acd530e3d..1ab76e2b79 100644
--- a/driver/tcpm/it83xx_pd.h
+++ b/driver/tcpm/it83xx_pd.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,202 +13,202 @@
 
 /* USBPD Controller */
 #if defined(CONFIG_USB_PD_TCPM_DRIVER_IT83XX)
-#define IT83XX_USBPD_BASE(port)   (0x00F03700 + (0x100 * (port)))
+#define IT83XX_USBPD_BASE(port) (0x00F03700 + (0x100 * (port)))
 
-#define IT83XX_USBPD_GCR(p)       REG8(IT83XX_USBPD_BASE(p)+0x0)
-#define USBPD_REG_MASK_SW_RESET_BIT               BIT(7)
-#define USBPD_REG_MASK_TYPE_C_DETECT_RESET        BIT(6)
-#define USBPD_REG_MASK_BMC_PHY                    BIT(4)
-#define USBPD_REG_MASK_AUTO_SEND_SW_RESET         BIT(3)
-#define USBPD_REG_MASK_AUTO_SEND_HW_RESET         BIT(2)
-#define USBPD_REG_MASK_SNIFFER_MODE               BIT(1)
-#define USBPD_REG_MASK_GLOBAL_ENABLE              BIT(0)
-#define IT83XX_USBPD_PDMSR(p)     REG8(IT83XX_USBPD_BASE(p)+0x01)
-#define USBPD_REG_MASK_SOPPP_ENABLE               BIT(7)
-#define USBPD_REG_MASK_SOPP_ENABLE                BIT(6)
-#define USBPD_REG_MASK_SOP_ENABLE                 BIT(5)
-#define IT83XX_USBPD_CCGCR(p)     REG8(IT83XX_USBPD_BASE(p)+0x04)
-#define USBPD_REG_MASK_DISABLE_CC                 BIT(4)
-#define IT83XX_USBPD_CCCSR(p)     REG8(IT83XX_USBPD_BASE(p)+0x05)
-#define USBPD_REG_MASK_CC2_DISCONNECT             BIT(7)
+#define IT83XX_USBPD_GCR(p) REG8(IT83XX_USBPD_BASE(p) + 0x0)
+#define USBPD_REG_MASK_SW_RESET_BIT BIT(7)
+#define USBPD_REG_MASK_TYPE_C_DETECT_RESET BIT(6)
+#define USBPD_REG_MASK_BMC_PHY BIT(4)
+#define USBPD_REG_MASK_AUTO_SEND_SW_RESET BIT(3)
+#define USBPD_REG_MASK_AUTO_SEND_HW_RESET BIT(2)
+#define USBPD_REG_MASK_SNIFFER_MODE BIT(1)
+#define USBPD_REG_MASK_GLOBAL_ENABLE BIT(0)
+#define IT83XX_USBPD_PDMSR(p) REG8(IT83XX_USBPD_BASE(p) + 0x01)
+#define USBPD_REG_MASK_SOPPP_ENABLE BIT(7)
+#define USBPD_REG_MASK_SOPP_ENABLE BIT(6)
+#define USBPD_REG_MASK_SOP_ENABLE BIT(5)
+#define IT83XX_USBPD_CCGCR(p) REG8(IT83XX_USBPD_BASE(p) + 0x04)
+#define USBPD_REG_MASK_DISABLE_CC BIT(4)
+#define IT83XX_USBPD_CCCSR(p) REG8(IT83XX_USBPD_BASE(p) + 0x05)
+#define USBPD_REG_MASK_CC2_DISCONNECT BIT(7)
 #define USBPD_REG_MASK_CC2_DISCONNECT_5_1K_TO_GND BIT(6)
-#define USBPD_REG_MASK_CC1_DISCONNECT             BIT(3)
+#define USBPD_REG_MASK_CC1_DISCONNECT BIT(3)
 #define USBPD_REG_MASK_CC1_DISCONNECT_5_1K_TO_GND BIT(2)
 #ifdef IT83XX_USBPD_CC_VOLTAGE_DETECTOR_INDEPENDENT
-#define USBPD_REG_MASK_DISABLE_CC_VOL_DETECTOR    (BIT(5) | BIT(1))
+#define USBPD_REG_MASK_DISABLE_CC_VOL_DETECTOR (BIT(5) | BIT(1))
 #else
-#define USBPD_REG_MASK_DISABLE_CC_VOL_DETECTOR    BIT(1)
+#define USBPD_REG_MASK_DISABLE_CC_VOL_DETECTOR BIT(1)
 #endif
-#define IT83XX_USBPD_CCPSR(p)     REG8(IT83XX_USBPD_BASE(p)+0x06)
-#define USBPD_REG_MASK_DISCONNECT_5_1K_CC2_DB     BIT(6)
-#define USBPD_REG_MASK_DISCONNECT_POWER_CC2       BIT(5)
-#define USBPD_REG_MASK_DISCONNECT_5_1K_CC1_DB     BIT(2)
-#define USBPD_REG_MASK_DISCONNECT_POWER_CC1       BIT(1)
-#define IT83XX_USBPD_DFPVDR(p)    REG8(IT83XX_USBPD_BASE(p)+0x08)
-#define IT83XX_USBPD_UFPVDR(p)    REG8(IT83XX_USBPD_BASE(p)+0x09)
-#define IT83XX_USBPD_PDPSR(p)     REG8(IT83XX_USBPD_BASE(p)+0x0B)
-#define USBPD_REG_MASK_AUTO_FRS_DISABLE           BIT(7)
-#define IT83XX_USBPD_CCADCR(p)    REG8(IT83XX_USBPD_BASE(p)+0x0C)
-#define IT83XX_USBPD_ISR(p)       REG8(IT83XX_USBPD_BASE(p)+0x14)
-#define USBPD_REG_MASK_TYPE_C_DETECT              BIT(7)
-#define USBPD_REG_MASK_CABLE_RESET_DETECT         BIT(6)
-#define USBPD_REG_MASK_HARD_RESET_DETECT          BIT(5)
-#define USBPD_REG_MASK_MSG_RX_DONE                BIT(4)
-#define USBPD_REG_MASK_AUTO_SOFT_RESET_TX_DONE    BIT(3)
-#define USBPD_REG_MASK_HARD_CABLE_RESET_TX_DONE   BIT(2)
-#define USBPD_REG_MASK_MSG_TX_DONE                BIT(1)
-#define USBPD_REG_MASK_TIMER_TIMEOUT              BIT(0)
-#define IT83XX_USBPD_IMR(p)       REG8(IT83XX_USBPD_BASE(p)+0x15)
-#define IT83XX_USBPD_MTCR(p)      REG8(IT83XX_USBPD_BASE(p)+0x18)
-#define USBPD_REG_MASK_SW_RESET_TX_STAT           BIT(3)
-#define USBPD_REG_MASK_TX_BUSY_STAT               BIT(2)
-#define USBPD_REG_MASK_TX_DISCARD_STAT            BIT(2)
+#define IT83XX_USBPD_CCPSR(p) REG8(IT83XX_USBPD_BASE(p) + 0x06)
+#define USBPD_REG_MASK_DISCONNECT_5_1K_CC2_DB BIT(6)
+#define USBPD_REG_MASK_DISCONNECT_POWER_CC2 BIT(5)
+#define USBPD_REG_MASK_DISCONNECT_5_1K_CC1_DB BIT(2)
+#define USBPD_REG_MASK_DISCONNECT_POWER_CC1 BIT(1)
+#define IT83XX_USBPD_DFPVDR(p) REG8(IT83XX_USBPD_BASE(p) + 0x08)
+#define IT83XX_USBPD_UFPVDR(p) REG8(IT83XX_USBPD_BASE(p) + 0x09)
+#define IT83XX_USBPD_PDPSR(p) REG8(IT83XX_USBPD_BASE(p) + 0x0B)
+#define USBPD_REG_MASK_AUTO_FRS_DISABLE BIT(7)
+#define IT83XX_USBPD_CCADCR(p) REG8(IT83XX_USBPD_BASE(p) + 0x0C)
+#define IT83XX_USBPD_ISR(p) REG8(IT83XX_USBPD_BASE(p) + 0x14)
+#define USBPD_REG_MASK_TYPE_C_DETECT BIT(7)
+#define USBPD_REG_MASK_CABLE_RESET_DETECT BIT(6)
+#define USBPD_REG_MASK_HARD_RESET_DETECT BIT(5)
+#define USBPD_REG_MASK_MSG_RX_DONE BIT(4)
+#define USBPD_REG_MASK_AUTO_SOFT_RESET_TX_DONE BIT(3)
+#define USBPD_REG_MASK_HARD_CABLE_RESET_TX_DONE BIT(2)
+#define USBPD_REG_MASK_MSG_TX_DONE BIT(1)
+#define USBPD_REG_MASK_TIMER_TIMEOUT BIT(0)
+#define IT83XX_USBPD_IMR(p) REG8(IT83XX_USBPD_BASE(p) + 0x15)
+#define IT83XX_USBPD_MTCR(p) REG8(IT83XX_USBPD_BASE(p) + 0x18)
+#define USBPD_REG_MASK_SW_RESET_TX_STAT BIT(3)
+#define USBPD_REG_MASK_TX_BUSY_STAT BIT(2)
+#define USBPD_REG_MASK_TX_DISCARD_STAT BIT(2)
 #ifdef IT83XX_PD_TX_ERROR_STATUS_BIT5
-#define USBPD_REG_MASK_TX_ERR_STAT                BIT(5)
+#define USBPD_REG_MASK_TX_ERR_STAT BIT(5)
 #else
-#define USBPD_REG_MASK_TX_ERR_STAT                BIT(1)
+#define USBPD_REG_MASK_TX_ERR_STAT BIT(1)
 #endif
-#define USBPD_REG_MASK_TX_START                   BIT(0)
-#define IT83XX_USBPD_MTSR0(p)     REG8(IT83XX_USBPD_BASE(p)+0x19)
-#define USBPD_REG_MASK_CABLE_ENABLE               BIT(7)
-#define USBPD_REG_MASK_SEND_HW_RESET              BIT(6)
-#define USBPD_REG_MASK_SEND_BIST_MODE_2           BIT(5)
-#define IT83XX_USBPD_MTSR1(p)     REG8(IT83XX_USBPD_BASE(p)+0x1A)
-#define IT83XX_USBPD_VDMMCSR(p)   REG8(IT83XX_USBPD_BASE(p)+0x1B)
-#define USBPD_REG_MASK_HARD_RESET_DECODE          BIT(0)
-#define IT83XX_USBPD_MRSR(p)      REG8(IT83XX_USBPD_BASE(p)+0x1C)
-#define USBPD_REG_GET_SOP_TYPE_RX(mrsr)           (((mrsr) >> 4) & 0x7)
-#define USBPD_REG_MASK_RX_MSG_VALID               BIT(0)
-#define IT83XX_USBPD_PEFSMR(p)    REG8(IT83XX_USBPD_BASE(p)+0x1D)
-#define IT83XX_USBPD_PES0R(p)     REG8(IT83XX_USBPD_BASE(p)+0x1E)
-#define IT83XX_USBPD_PES1R(p)     REG8(IT83XX_USBPD_BASE(p)+0x1F)
-#define IT83XX_USBPD_TDO(p)       REG32(IT83XX_USBPD_BASE(p)+0x20)
-#define IT83XX_USBPD_AGTMHLR(p)   REG8(IT83XX_USBPD_BASE(p)+0x3C)
-#define IT83XX_USBPD_AGTMHHR(p)   REG8(IT83XX_USBPD_BASE(p)+0x3D)
-#define IT83XX_USBPD_TMHLR(p)     REG8(IT83XX_USBPD_BASE(p)+0x3E)
-#define IT83XX_USBPD_TMHHR(p)     REG8(IT83XX_USBPD_BASE(p)+0x3F)
-#define IT83XX_USBPD_RDO0(p)      REG32(IT83XX_USBPD_BASE(p)+0x40)
-#define IT83XX_USBPD_RMH(p)       REG16(IT83XX_USBPD_BASE(p)+0x5E)
-#define IT83XX_USBPD_CCPSR0(p)    REG8(IT83XX_USBPD_BASE(p)+0x60)
-#define IT83XX_USBPD_BMCSR(p)     REG8(IT83XX_USBPD_BASE(p)+0x64)
-#define IT83XX_USBPD_PDMHSR(p)    REG8(IT83XX_USBPD_BASE(p)+0x65)
-#define IT83XX_USBPD_TCDCR(p)     REG8(IT83XX_USBPD_BASE(p)+0x67)
-#define USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT     BIT(7)
-#define USBPD_REG_MASK_TYPEC_PLUG_IN_OUT_ISR      BIT(4)
-#define USBPD_REG_PLUG_OUT_SELECT                 BIT(3)
-#define USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE      BIT(1)
-#define USBPD_REG_PLUG_IN_OUT_DETECT_STAT         BIT(0)
-#define IT83XX_USBPD_PDQSCR(p)    REG8(IT83XX_USBPD_BASE(p)+0x70)
-#define USBPD_REG_FAST_SWAP_REQUEST_ENABLE     BIT(1)
-#define USBPD_REG_FAST_SWAP_DETECT_ENABLE      BIT(0)
-#define IT83XX_USBPD_PD30IR(p)    REG8(IT83XX_USBPD_BASE(p)+0x78)
-#define USBPD_REG_FAST_SWAP_DETECT_STAT        BIT(4)
-#define IT83XX_USBPD_MPD30IR(p)   REG8(IT83XX_USBPD_BASE(p)+0x7A)
-#define USBPD_REG_MASK_PD30_ISR                BIT(7)
-#define USBPD_REG_MASK_FAST_SWAP_DETECT_ISR    BIT(4)
+#define USBPD_REG_MASK_TX_START BIT(0)
+#define IT83XX_USBPD_MTSR0(p) REG8(IT83XX_USBPD_BASE(p) + 0x19)
+#define USBPD_REG_MASK_CABLE_ENABLE BIT(7)
+#define USBPD_REG_MASK_SEND_HW_RESET BIT(6)
+#define USBPD_REG_MASK_SEND_BIST_MODE_2 BIT(5)
+#define IT83XX_USBPD_MTSR1(p) REG8(IT83XX_USBPD_BASE(p) + 0x1A)
+#define IT83XX_USBPD_VDMMCSR(p) REG8(IT83XX_USBPD_BASE(p) + 0x1B)
+#define USBPD_REG_MASK_HARD_RESET_DECODE BIT(0)
+#define IT83XX_USBPD_MRSR(p) REG8(IT83XX_USBPD_BASE(p) + 0x1C)
+#define USBPD_REG_GET_SOP_TYPE_RX(mrsr) (((mrsr) >> 4) & 0x7)
+#define USBPD_REG_MASK_RX_MSG_VALID BIT(0)
+#define IT83XX_USBPD_PEFSMR(p) REG8(IT83XX_USBPD_BASE(p) + 0x1D)
+#define IT83XX_USBPD_PES0R(p) REG8(IT83XX_USBPD_BASE(p) + 0x1E)
+#define IT83XX_USBPD_PES1R(p) REG8(IT83XX_USBPD_BASE(p) + 0x1F)
+#define IT83XX_USBPD_TDO(p) REG32(IT83XX_USBPD_BASE(p) + 0x20)
+#define IT83XX_USBPD_AGTMHLR(p) REG8(IT83XX_USBPD_BASE(p) + 0x3C)
+#define IT83XX_USBPD_AGTMHHR(p) REG8(IT83XX_USBPD_BASE(p) + 0x3D)
+#define IT83XX_USBPD_TMHLR(p) REG8(IT83XX_USBPD_BASE(p) + 0x3E)
+#define IT83XX_USBPD_TMHHR(p) REG8(IT83XX_USBPD_BASE(p) + 0x3F)
+#define IT83XX_USBPD_RDO0(p) REG32(IT83XX_USBPD_BASE(p) + 0x40)
+#define IT83XX_USBPD_RMH(p) REG16(IT83XX_USBPD_BASE(p) + 0x5E)
+#define IT83XX_USBPD_CCPSR0(p) REG8(IT83XX_USBPD_BASE(p) + 0x60)
+#define IT83XX_USBPD_BMCSR(p) REG8(IT83XX_USBPD_BASE(p) + 0x64)
+#define IT83XX_USBPD_PDMHSR(p) REG8(IT83XX_USBPD_BASE(p) + 0x65)
+#define IT83XX_USBPD_TCDCR(p) REG8(IT83XX_USBPD_BASE(p) + 0x67)
+#define USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT BIT(7)
+#define USBPD_REG_MASK_TYPEC_PLUG_IN_OUT_ISR BIT(4)
+#define USBPD_REG_PLUG_OUT_SELECT BIT(3)
+#define USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE BIT(1)
+#define USBPD_REG_PLUG_IN_OUT_DETECT_STAT BIT(0)
+#define IT83XX_USBPD_PDQSCR(p) REG8(IT83XX_USBPD_BASE(p) + 0x70)
+#define USBPD_REG_FAST_SWAP_REQUEST_ENABLE BIT(1)
+#define USBPD_REG_FAST_SWAP_DETECT_ENABLE BIT(0)
+#define IT83XX_USBPD_PD30IR(p) REG8(IT83XX_USBPD_BASE(p) + 0x78)
+#define USBPD_REG_FAST_SWAP_DETECT_STAT BIT(4)
+#define IT83XX_USBPD_MPD30IR(p) REG8(IT83XX_USBPD_BASE(p) + 0x7A)
+#define USBPD_REG_MASK_PD30_ISR BIT(7)
+#define USBPD_REG_MASK_FAST_SWAP_DETECT_ISR BIT(4)
 
 #elif defined(CONFIG_USB_PD_TCPM_DRIVER_IT8XXX2)
-#define IT83XX_USBPD_BASE(port)     (0x00F03700 + (0x100 * (port) * (port)))
+#define IT83XX_USBPD_BASE(port) (0x00F03700 + (0x100 * (port) * (port)))
 
-#define IT83XX_USBPD_PDGCR(p)       REG8(IT83XX_USBPD_BASE(p)+0x0)
-#define USBPD_REG_MASK_SW_RESET_BIT               BIT(7)
-#define USBPD_REG_MASK_PROTOCOL_STATE_CLEAR       BIT(6)
-#define USBPD_REG_MASK_BIST_DATA_MODE             BIT(4)
-#define USBPD_REG_MASK_AUTO_BIST_RESPONSE         BIT(3)
-#define USBPD_REG_MASK_TX_MESSAGE_ENABLE          BIT(2)
-#define USBPD_REG_MASK_SNIFFER_MODE               BIT(1)
-#define USBPD_REG_MASK_BMC_PHY                    BIT(0)
-#define IT83XX_USBPD_PDCSR0(p)      REG8(IT83XX_USBPD_BASE(p)+0x01)
-#define IT83XX_USBPD_PDMSR(p)       REG8(IT83XX_USBPD_BASE(p)+0x02)
+#define IT83XX_USBPD_PDGCR(p) REG8(IT83XX_USBPD_BASE(p) + 0x0)
+#define USBPD_REG_MASK_SW_RESET_BIT BIT(7)
+#define USBPD_REG_MASK_PROTOCOL_STATE_CLEAR BIT(6)
+#define USBPD_REG_MASK_BIST_DATA_MODE BIT(4)
+#define USBPD_REG_MASK_AUTO_BIST_RESPONSE BIT(3)
+#define USBPD_REG_MASK_TX_MESSAGE_ENABLE BIT(2)
+#define USBPD_REG_MASK_SNIFFER_MODE BIT(1)
+#define USBPD_REG_MASK_BMC_PHY BIT(0)
+#define IT83XX_USBPD_PDCSR0(p) REG8(IT83XX_USBPD_BASE(p) + 0x01)
+#define IT83XX_USBPD_PDMSR(p) REG8(IT83XX_USBPD_BASE(p) + 0x02)
 #define USBPD_REG_MASK_DISABLE_AUTO_GEN_TX_HEADER BIT(7)
-#define USBPD_REG_MASK_AUTO_FRS_DISABLE           BIT(6)
-#define IT83XX_USBPD_PDCSR1(p)      REG8(IT83XX_USBPD_BASE(p)+0x03)
-#define USBPD_REG_MASK_CABLE_RESET_RX_ENABLE      BIT(6)
-#define USBPD_REG_MASK_HARD_RESET_RX_ENABLE       BIT(5)
-#define USBPD_REG_MASK_SOPPP_RX_ENABLE            BIT(2)
-#define USBPD_REG_MASK_SOPP_RX_ENABLE             BIT(1)
-#define USBPD_REG_MASK_SOP_RX_ENABLE              BIT(0)
-#define IT83XX_USBPD_CCGCR(p)       REG8(IT83XX_USBPD_BASE(p)+0x04)
-#define USBPD_REG_MASK_DISABLE_CC                 BIT(7)
-#define USBPD_REG_MASK_DISABLE_CC_VOL_DETECTOR    BIT(6)
-#define USBPD_REG_MASK_CC_SELECT_RP_RESERVED      (BIT(3) | BIT(2) | BIT(1))
-#define USBPD_REG_MASK_CC_SELECT_RP_DEF           (BIT(3) | BIT(2))
-#define USBPD_REG_MASK_CC_SELECT_RP_1A5           BIT(3)
-#define USBPD_REG_MASK_CC_SELECT_RP_3A0           BIT(2)
-#define USBPD_REG_MASK_CC1_CC2_SELECTION          BIT(0)
-#define IT83XX_USBPD_CCCSR(p)       REG8(IT83XX_USBPD_BASE(p)+0x05)
-#define USBPD_REG_MASK_CC2_DISCONNECT             BIT(7)
+#define USBPD_REG_MASK_AUTO_FRS_DISABLE BIT(6)
+#define IT83XX_USBPD_PDCSR1(p) REG8(IT83XX_USBPD_BASE(p) + 0x03)
+#define USBPD_REG_MASK_CABLE_RESET_RX_ENABLE BIT(6)
+#define USBPD_REG_MASK_HARD_RESET_RX_ENABLE BIT(5)
+#define USBPD_REG_MASK_SOPPP_RX_ENABLE BIT(2)
+#define USBPD_REG_MASK_SOPP_RX_ENABLE BIT(1)
+#define USBPD_REG_MASK_SOP_RX_ENABLE BIT(0)
+#define IT83XX_USBPD_CCGCR(p) REG8(IT83XX_USBPD_BASE(p) + 0x04)
+#define USBPD_REG_MASK_DISABLE_CC BIT(7)
+#define USBPD_REG_MASK_DISABLE_CC_VOL_DETECTOR BIT(6)
+#define USBPD_REG_MASK_CC_SELECT_RP_RESERVED (BIT(3) | BIT(2) | BIT(1))
+#define USBPD_REG_MASK_CC_SELECT_RP_DEF (BIT(3) | BIT(2))
+#define USBPD_REG_MASK_CC_SELECT_RP_1A5 BIT(3)
+#define USBPD_REG_MASK_CC_SELECT_RP_3A0 BIT(2)
+#define USBPD_REG_MASK_CC1_CC2_SELECTION BIT(0)
+#define IT83XX_USBPD_CCCSR(p) REG8(IT83XX_USBPD_BASE(p) + 0x05)
+#define USBPD_REG_MASK_CC2_DISCONNECT BIT(7)
 #define USBPD_REG_MASK_CC2_DISCONNECT_5_1K_TO_GND BIT(6)
-#define USBPD_REG_MASK_CC1_DISCONNECT             BIT(3)
+#define USBPD_REG_MASK_CC1_DISCONNECT BIT(3)
 #define USBPD_REG_MASK_CC1_DISCONNECT_5_1K_TO_GND BIT(2)
 #ifdef IT83XX_USBPD_CC1_CC2_RESISTANCE_SEPARATE
-#define USBPD_REG_MASK_CC1_CC2_RP_RD_SELECT       (BIT(1) | BIT(5))
+#define USBPD_REG_MASK_CC1_CC2_RP_RD_SELECT (BIT(1) | BIT(5))
 #else
-#define USBPD_REG_MASK_CC1_CC2_RP_RD_SELECT       BIT(1)
+#define USBPD_REG_MASK_CC1_CC2_RP_RD_SELECT BIT(1)
 #endif
-#define IT83XX_USBPD_CCPSR(p)       REG8(IT83XX_USBPD_BASE(p)+0x06)
-#define USBPD_REG_MASK_DISCONNECT_5_1K_CC2_DB     BIT(6)
-#define USBPD_REG_MASK_DISCONNECT_POWER_CC2       BIT(5)
-#define USBPD_REG_MASK_DISCONNECT_5_1K_CC1_DB     BIT(2)
-#define USBPD_REG_MASK_DISCONNECT_POWER_CC1       BIT(1)
-#define IT83XX_USBPD_SRCVCRR(p)     REG8(IT83XX_USBPD_BASE(p)+0x08)
-#define USBPD_REG_MASK_SRC_COMPARE_CC2_VOLT_H     BIT(5)
-#define USBPD_REG_MASK_SRC_COMPARE_CC2_VOLT_L     BIT(4)
-#define USBPD_REG_MASK_SRC_COMPARE_CC1_VOLT_H     BIT(1)
-#define USBPD_REG_MASK_SRC_COMPARE_CC1_VOLT_L     BIT(0)
-#define IT83XX_USBPD_SNKVCRR(p)     REG8(IT83XX_USBPD_BASE(p)+0x09)
-#define USBPD_REG_MASK_SNK_COMPARE_CC2_VOLT_H     BIT(6)
-#define USBPD_REG_MASK_SNK_COMPARE_CC2_VOLT_M     BIT(5)
-#define USBPD_REG_MASK_SNK_COMPARE_CC2_VOLT_L     BIT(4)
-#define USBPD_REG_MASK_SNK_COMPARE_CC1_VOLT_H     BIT(2)
-#define USBPD_REG_MASK_SNK_COMPARE_CC1_VOLT_M     BIT(1)
-#define USBPD_REG_MASK_SNK_COMPARE_CC1_VOLT_L     BIT(0)
-#define IT83XX_USBPD_PDFSCR(p)      REG8(IT83XX_USBPD_BASE(p)+0x0C)
-#define USBPD_REG_FAST_SWAP_REQUEST_ENABLE        BIT(1)
-#define USBPD_REG_FAST_SWAP_DETECT_ENABLE         BIT(0)
-#define IT83XX_USBPD_IFS(p)         REG8(IT83XX_USBPD_BASE(p)+0x12)
-#define USBPD_REG_FAST_SWAP_DETECT_STAT           BIT(4)
-#define IT83XX_USBPD_MIFS(p)        REG8(IT83XX_USBPD_BASE(p)+0x13)
-#define USBPD_REG_MASK_FAST_SWAP_ISR              BIT(7)
-#define USBPD_REG_MASK_FAST_SWAP_DETECT_ISR       BIT(4)
-#define IT83XX_USBPD_ISR(p)         REG8(IT83XX_USBPD_BASE(p)+0x14)
-#define USBPD_REG_MASK_CABLE_RESET_DETECT         BIT(6)
-#define USBPD_REG_MASK_HARD_RESET_DETECT          BIT(5)
-#define USBPD_REG_MASK_MSG_RX_DONE                BIT(4)
-#define USBPD_REG_MASK_TX_ERROR_STAT              BIT(3)
-#define USBPD_REG_MASK_CABLE_RESET_TX_DONE        BIT(2)
-#define USBPD_REG_MASK_HARD_RESET_TX_DONE         BIT(1)
-#define USBPD_REG_MASK_MSG_TX_DONE                BIT(0)
-#define IT83XX_USBPD_IMR(p)         REG8(IT83XX_USBPD_BASE(p)+0x15)
-#define IT83XX_USBPD_MTCR(p)        REG8(IT83XX_USBPD_BASE(p)+0x18)
-#define USBPD_REG_MASK_TX_DISCARD_STAT            BIT(7)
-#define USBPD_REG_MASK_TX_NO_RESPONSE_STAT        BIT(6)
-#define USBPD_REG_MASK_TX_NOT_EN_STAT             BIT(5)
-#define USBPD_REG_MASK_CABLE_RESET                BIT(3)
-#define USBPD_REG_MASK_SEND_HW_RESET              BIT(2)
-#define USBPD_REG_MASK_SEND_BIST_MODE_2           BIT(1)
-#define USBPD_REG_MASK_TX_START                   BIT(0)
-#define IT83XX_USBPD_MTSR0(p)       REG8(IT83XX_USBPD_BASE(p)+0x19)
-#define IT83XX_USBPD_MHSR0(p)       REG8(IT83XX_USBPD_BASE(p)+0x1A)
-#define USBPD_REG_MASK_SOP_PORT_DATA_ROLE         BIT(5)
-#define IT83XX_USBPD_MHSR1(p)       REG8(IT83XX_USBPD_BASE(p)+0x1B)
-#define USBPD_REG_MASK_SOP_PORT_POWER_ROLE        BIT(0)
-#define IT83XX_USBPD_TDO(p)         REG32(IT83XX_USBPD_BASE(p)+0x22)
-#define IT83XX_USBPD_RMH(p)         REG16(IT83XX_USBPD_BASE(p)+0x42)
-#define IT83XX_USBPD_RDO(p)         REG32(IT83XX_USBPD_BASE(p)+0x44)
-#define IT83XX_USBPD_BMCDR0(p)      REG8(IT83XX_USBPD_BASE(p)+0x61)
-#define USBPD_REG_MASK_BMC_RX_THRESHOLD_SRC       BIT(5)
-#define USBPD_REG_MASK_BMC_RX_THRESHOLD_SNK       BIT(1)
-#define IT83XX_USBPD_TCDCR(p)       REG8(IT83XX_USBPD_BASE(p)+0x67)
-#define USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT     BIT(7)
-#define USBPD_REG_PLUG_OUT_SELECT                 BIT(6)
-#define USBPD_REG_PD3_0_SNK_TX_OK_DISABLE         BIT(5)
-#define USBPD_REG_PD3_0_SNK_TX_NG_DISABLE         BIT(3)
-#define USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE      BIT(1)
-#define USBPD_REG_PLUG_IN_OUT_DETECT_STAT         BIT(0)
-#define IT83XX_USBPD_CCPSR0(p)      REG8(IT83XX_USBPD_BASE(p)+0x70)
-#define IT83XX_USBPD_CCPSR3_RISE(p) REG8(IT83XX_USBPD_BASE(p)+0x73)
-#define IT83XX_USBPD_CCPSR4_FALL(p) REG8(IT83XX_USBPD_BASE(p)+0x74)
+#define IT83XX_USBPD_CCPSR(p) REG8(IT83XX_USBPD_BASE(p) + 0x06)
+#define USBPD_REG_MASK_DISCONNECT_5_1K_CC2_DB BIT(6)
+#define USBPD_REG_MASK_DISCONNECT_POWER_CC2 BIT(5)
+#define USBPD_REG_MASK_DISCONNECT_5_1K_CC1_DB BIT(2)
+#define USBPD_REG_MASK_DISCONNECT_POWER_CC1 BIT(1)
+#define IT83XX_USBPD_SRCVCRR(p) REG8(IT83XX_USBPD_BASE(p) + 0x08)
+#define USBPD_REG_MASK_SRC_COMPARE_CC2_VOLT_H BIT(5)
+#define USBPD_REG_MASK_SRC_COMPARE_CC2_VOLT_L BIT(4)
+#define USBPD_REG_MASK_SRC_COMPARE_CC1_VOLT_H BIT(1)
+#define USBPD_REG_MASK_SRC_COMPARE_CC1_VOLT_L BIT(0)
+#define IT83XX_USBPD_SNKVCRR(p) REG8(IT83XX_USBPD_BASE(p) + 0x09)
+#define USBPD_REG_MASK_SNK_COMPARE_CC2_VOLT_H BIT(6)
+#define USBPD_REG_MASK_SNK_COMPARE_CC2_VOLT_M BIT(5)
+#define USBPD_REG_MASK_SNK_COMPARE_CC2_VOLT_L BIT(4)
+#define USBPD_REG_MASK_SNK_COMPARE_CC1_VOLT_H BIT(2)
+#define USBPD_REG_MASK_SNK_COMPARE_CC1_VOLT_M BIT(1)
+#define USBPD_REG_MASK_SNK_COMPARE_CC1_VOLT_L BIT(0)
+#define IT83XX_USBPD_PDFSCR(p) REG8(IT83XX_USBPD_BASE(p) + 0x0C)
+#define USBPD_REG_FAST_SWAP_REQUEST_ENABLE BIT(1)
+#define USBPD_REG_FAST_SWAP_DETECT_ENABLE BIT(0)
+#define IT83XX_USBPD_IFS(p) REG8(IT83XX_USBPD_BASE(p) + 0x12)
+#define USBPD_REG_FAST_SWAP_DETECT_STAT BIT(4)
+#define IT83XX_USBPD_MIFS(p) REG8(IT83XX_USBPD_BASE(p) + 0x13)
+#define USBPD_REG_MASK_FAST_SWAP_ISR BIT(7)
+#define USBPD_REG_MASK_FAST_SWAP_DETECT_ISR BIT(4)
+#define IT83XX_USBPD_ISR(p) REG8(IT83XX_USBPD_BASE(p) + 0x14)
+#define USBPD_REG_MASK_CABLE_RESET_DETECT BIT(6)
+#define USBPD_REG_MASK_HARD_RESET_DETECT BIT(5)
+#define USBPD_REG_MASK_MSG_RX_DONE BIT(4)
+#define USBPD_REG_MASK_TX_ERROR_STAT BIT(3)
+#define USBPD_REG_MASK_CABLE_RESET_TX_DONE BIT(2)
+#define USBPD_REG_MASK_HARD_RESET_TX_DONE BIT(1)
+#define USBPD_REG_MASK_MSG_TX_DONE BIT(0)
+#define IT83XX_USBPD_IMR(p) REG8(IT83XX_USBPD_BASE(p) + 0x15)
+#define IT83XX_USBPD_MTCR(p) REG8(IT83XX_USBPD_BASE(p) + 0x18)
+#define USBPD_REG_MASK_TX_DISCARD_STAT BIT(7)
+#define USBPD_REG_MASK_TX_NO_RESPONSE_STAT BIT(6)
+#define USBPD_REG_MASK_TX_NOT_EN_STAT BIT(5)
+#define USBPD_REG_MASK_CABLE_RESET BIT(3)
+#define USBPD_REG_MASK_SEND_HW_RESET BIT(2)
+#define USBPD_REG_MASK_SEND_BIST_MODE_2 BIT(1)
+#define USBPD_REG_MASK_TX_START BIT(0)
+#define IT83XX_USBPD_MTSR0(p) REG8(IT83XX_USBPD_BASE(p) + 0x19)
+#define IT83XX_USBPD_MHSR0(p) REG8(IT83XX_USBPD_BASE(p) + 0x1A)
+#define USBPD_REG_MASK_SOP_PORT_DATA_ROLE BIT(5)
+#define IT83XX_USBPD_MHSR1(p) REG8(IT83XX_USBPD_BASE(p) + 0x1B)
+#define USBPD_REG_MASK_SOP_PORT_POWER_ROLE BIT(0)
+#define IT83XX_USBPD_TDO(p) REG32(IT83XX_USBPD_BASE(p) + 0x22)
+#define IT83XX_USBPD_RMH(p) REG16(IT83XX_USBPD_BASE(p) + 0x42)
+#define IT83XX_USBPD_RDO(p) REG32(IT83XX_USBPD_BASE(p) + 0x44)
+#define IT83XX_USBPD_BMCDR0(p) REG8(IT83XX_USBPD_BASE(p) + 0x61)
+#define USBPD_REG_MASK_BMC_RX_THRESHOLD_SRC BIT(5)
+#define USBPD_REG_MASK_BMC_RX_THRESHOLD_SNK BIT(1)
+#define IT83XX_USBPD_TCDCR(p) REG8(IT83XX_USBPD_BASE(p) + 0x67)
+#define USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT BIT(7)
+#define USBPD_REG_PLUG_OUT_SELECT BIT(6)
+#define USBPD_REG_PD3_0_SNK_TX_OK_DISABLE BIT(5)
+#define USBPD_REG_PD3_0_SNK_TX_NG_DISABLE BIT(3)
+#define USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE BIT(1)
+#define USBPD_REG_PLUG_IN_OUT_DETECT_STAT BIT(0)
+#define IT83XX_USBPD_CCPSR0(p) REG8(IT83XX_USBPD_BASE(p) + 0x70)
+#define IT83XX_USBPD_CCPSR3_RISE(p) REG8(IT83XX_USBPD_BASE(p) + 0x73)
+#define IT83XX_USBPD_CCPSR4_FALL(p) REG8(IT83XX_USBPD_BASE(p) + 0x74)
 #endif /* !defined(CONFIG_USB_PD_TCPM_DRIVER_IT83XX) */
 
 /*
@@ -216,7 +216,7 @@
  * This setting will connect CC pin to internal PD module directly without
  * applying any GPIO/ALT configuration.
  */
-#define IT83XX_USBPD_CC_PIN_CONFIG  0x86
+#define IT83XX_USBPD_CC_PIN_CONFIG 0x86
 #define IT83XX_USBPD_CC_PIN_CONFIG2 0x06
 
 /*
@@ -224,138 +224,117 @@
  * detector is enabled and Vconn is dropped below 3.3v (>500us) to avoid
  * the potential risk of voltage fed back into Vcore.
  */
-#define IT83XX_USBPD_T_VCONN_BELOW_3_3V       500  /* us */
+#define IT83XX_USBPD_T_VCONN_BELOW_3_3V 500 /* us */
 
 #ifndef CONFIG_USB_PD_TCPM_ITE_ON_CHIP
-#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT   0
+#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 0
 #endif
 
 #define TASK_EVENT_PHY_TX_DONE TASK_EVENT_CUSTOM_BIT(PD_EVENT_FIRST_FREE_BIT)
 
-#define SET_MASK(reg, bit_mask)      ((reg) |= (bit_mask))
-#define CLEAR_MASK(reg, bit_mask)    ((reg) &= (~(bit_mask)))
-#define IS_MASK_SET(reg, bit_mask)   (((reg) & (bit_mask)) != 0)
+#define SET_MASK(reg, bit_mask) ((reg) |= (bit_mask))
+#define CLEAR_MASK(reg, bit_mask) ((reg) &= (~(bit_mask)))
+#define IS_MASK_SET(reg, bit_mask) (((reg) & (bit_mask)) != 0)
 #define IS_MASK_CLEAR(reg, bit_mask) (((reg) & (bit_mask)) == 0)
 
 #if defined(CONFIG_USB_PD_TCPM_DRIVER_IT83XX)
 /* macros for set */
-#define USBPD_KICK_TX_START(port)            \
-	SET_MASK(IT83XX_USBPD_MTCR(port),    \
-		USBPD_REG_MASK_TX_START)
-#define USBPD_SEND_HARD_RESET(port)          \
-	SET_MASK(IT83XX_USBPD_MTSR0(port),   \
-		USBPD_REG_MASK_SEND_HW_RESET)
-#define USBPD_SW_RESET(port)                 \
-	SET_MASK(IT83XX_USBPD_GCR(port),     \
-		USBPD_REG_MASK_SW_RESET_BIT)
-#define USBPD_ENABLE_BMC_PHY(port)           \
-	SET_MASK(IT83XX_USBPD_GCR(port),     \
-		USBPD_REG_MASK_BMC_PHY)
-#define USBPD_DISABLE_BMC_PHY(port)          \
-	CLEAR_MASK(IT83XX_USBPD_GCR(port),   \
-		USBPD_REG_MASK_BMC_PHY)
-#define USBPD_START(port)                    \
-	CLEAR_MASK(IT83XX_USBPD_CCGCR(port), \
-		USBPD_REG_MASK_DISABLE_CC)
-#define USBPD_ENABLE_SEND_BIST_MODE_2(port)  \
-	SET_MASK(IT83XX_USBPD_MTSR0(port),   \
-		USBPD_REG_MASK_SEND_BIST_MODE_2)
+#define USBPD_KICK_TX_START(port) \
+	SET_MASK(IT83XX_USBPD_MTCR(port), USBPD_REG_MASK_TX_START)
+#define USBPD_SEND_HARD_RESET(port) \
+	SET_MASK(IT83XX_USBPD_MTSR0(port), USBPD_REG_MASK_SEND_HW_RESET)
+#define USBPD_SW_RESET(port) \
+	SET_MASK(IT83XX_USBPD_GCR(port), USBPD_REG_MASK_SW_RESET_BIT)
+#define USBPD_ENABLE_BMC_PHY(port) \
+	SET_MASK(IT83XX_USBPD_GCR(port), USBPD_REG_MASK_BMC_PHY)
+#define USBPD_DISABLE_BMC_PHY(port) \
+	CLEAR_MASK(IT83XX_USBPD_GCR(port), USBPD_REG_MASK_BMC_PHY)
+#define USBPD_START(port) \
+	CLEAR_MASK(IT83XX_USBPD_CCGCR(port), USBPD_REG_MASK_DISABLE_CC)
+#define USBPD_ENABLE_SEND_BIST_MODE_2(port) \
+	SET_MASK(IT83XX_USBPD_MTSR0(port), USBPD_REG_MASK_SEND_BIST_MODE_2)
 #define USBPD_DISABLE_SEND_BIST_MODE_2(port) \
-	CLEAR_MASK(IT83XX_USBPD_MTSR0(port), \
-		USBPD_REG_MASK_SEND_BIST_MODE_2)
-#define USBPD_CLEAR_FRS_DETECT_STATUS(port)  \
+	CLEAR_MASK(IT83XX_USBPD_MTSR0(port), USBPD_REG_MASK_SEND_BIST_MODE_2)
+#define USBPD_CLEAR_FRS_DETECT_STATUS(port) \
 	(IT83XX_USBPD_PD30IR(port) = USBPD_REG_FAST_SWAP_DETECT_STAT)
-#define USBPD_CC1_DISCONNECTED(p) \
+#define USBPD_CC1_DISCONNECTED(p)                                  \
 	((IT83XX_USBPD_CCCSR(p) | USBPD_REG_MASK_CC1_DISCONNECT) & \
-	~USBPD_REG_MASK_CC2_DISCONNECT)
-#define USBPD_CC2_DISCONNECTED(p) \
+	 ~USBPD_REG_MASK_CC2_DISCONNECT)
+#define USBPD_CC2_DISCONNECTED(p)                                  \
 	((IT83XX_USBPD_CCCSR(p) | USBPD_REG_MASK_CC2_DISCONNECT) & \
-	~USBPD_REG_MASK_CC1_DISCONNECT)
+	 ~USBPD_REG_MASK_CC1_DISCONNECT)
 
 /* macros for get */
-#define USBPD_GET_POWER_ROLE(port)                  \
-	(IT83XX_USBPD_PDMSR(port) & 1)
+#define USBPD_GET_POWER_ROLE(port) (IT83XX_USBPD_PDMSR(port) & 1)
 #define USBPD_GET_CC1_PULL_REGISTER_SELECTION(port) \
 	(IT83XX_USBPD_CCGCR(port) & BIT(1))
 #define USBPD_GET_CC2_PULL_REGISTER_SELECTION(port) \
 	(IT83XX_USBPD_BMCSR(port) & BIT(3))
-#define USBPD_GET_PULL_CC_SELECTION(port)           \
-	(IT83XX_USBPD_CCGCR(port) & 1)
+#define USBPD_GET_PULL_CC_SELECTION(port) (IT83XX_USBPD_CCGCR(port) & 1)
 
 /* macros for check */
-#define USBPD_IS_TX_ERR(port)       \
+#define USBPD_IS_TX_ERR(port) \
 	IS_MASK_SET(IT83XX_USBPD_MTCR(port), USBPD_REG_MASK_TX_ERR_STAT)
-#define USBPD_IS_TX_DISCARD(port)   \
+#define USBPD_IS_TX_DISCARD(port) \
 	IS_MASK_SET(IT83XX_USBPD_MTCR(port), USBPD_REG_MASK_TX_DISCARD_STAT)
 
 #elif defined(CONFIG_USB_PD_TCPM_DRIVER_IT8XXX2)
 /* macros for set */
-#define USBPD_SW_RESET(port)                 \
-	SET_MASK(IT83XX_USBPD_PDGCR(port),   \
-		USBPD_REG_MASK_SW_RESET_BIT)
-#define USBPD_ENABLE_BMC_PHY(port)           \
-	SET_MASK(IT83XX_USBPD_PDGCR(port),   \
-		USBPD_REG_MASK_BMC_PHY)
-#define USBPD_DISABLE_BMC_PHY(port)          \
-	CLEAR_MASK(IT83XX_USBPD_PDGCR(port), \
-		USBPD_REG_MASK_BMC_PHY)
-#define USBPD_START(port)                    \
-	CLEAR_MASK(IT83XX_USBPD_CCGCR(port), \
-		USBPD_REG_MASK_DISABLE_CC)
-#define USBPD_SEND_HARD_RESET(port)          \
-	SET_MASK(IT83XX_USBPD_MTCR(port),    \
-		USBPD_REG_MASK_SEND_HW_RESET)
-#define USBPD_SEND_CABLE_RESET(port)         \
-	SET_MASK(IT83XX_USBPD_MTCR(port),    \
-		USBPD_REG_MASK_CABLE_RESET)
-#define USBPD_ENABLE_SEND_BIST_MODE_2(port)  \
-	SET_MASK(IT83XX_USBPD_MTCR(port),    \
-		USBPD_REG_MASK_SEND_BIST_MODE_2)
+#define USBPD_SW_RESET(port) \
+	SET_MASK(IT83XX_USBPD_PDGCR(port), USBPD_REG_MASK_SW_RESET_BIT)
+#define USBPD_ENABLE_BMC_PHY(port) \
+	SET_MASK(IT83XX_USBPD_PDGCR(port), USBPD_REG_MASK_BMC_PHY)
+#define USBPD_DISABLE_BMC_PHY(port) \
+	CLEAR_MASK(IT83XX_USBPD_PDGCR(port), USBPD_REG_MASK_BMC_PHY)
+#define USBPD_START(port) \
+	CLEAR_MASK(IT83XX_USBPD_CCGCR(port), USBPD_REG_MASK_DISABLE_CC)
+#define USBPD_SEND_HARD_RESET(port) \
+	SET_MASK(IT83XX_USBPD_MTCR(port), USBPD_REG_MASK_SEND_HW_RESET)
+#define USBPD_SEND_CABLE_RESET(port) \
+	SET_MASK(IT83XX_USBPD_MTCR(port), USBPD_REG_MASK_CABLE_RESET)
+#define USBPD_ENABLE_SEND_BIST_MODE_2(port) \
+	SET_MASK(IT83XX_USBPD_MTCR(port), USBPD_REG_MASK_SEND_BIST_MODE_2)
 #define USBPD_DISABLE_SEND_BIST_MODE_2(port) \
-	CLEAR_MASK(IT83XX_USBPD_MTCR(port),  \
-		USBPD_REG_MASK_SEND_BIST_MODE_2)
-#define USBPD_KICK_TX_START(port)            \
-	SET_MASK(IT83XX_USBPD_MTCR(port),    \
-		USBPD_REG_MASK_TX_START)
-#define USBPD_CLEAR_FRS_DETECT_STATUS(port)  \
+	CLEAR_MASK(IT83XX_USBPD_MTCR(port), USBPD_REG_MASK_SEND_BIST_MODE_2)
+#define USBPD_KICK_TX_START(port) \
+	SET_MASK(IT83XX_USBPD_MTCR(port), USBPD_REG_MASK_TX_START)
+#define USBPD_CLEAR_FRS_DETECT_STATUS(port) \
 	(IT83XX_USBPD_IFS(port) = USBPD_REG_FAST_SWAP_DETECT_STAT)
-#define USBPD_CC1_DISCONNECTED(p) \
+#define USBPD_CC1_DISCONNECTED(p)                                  \
 	((IT83XX_USBPD_CCCSR(p) | USBPD_REG_MASK_CC1_DISCONNECT) & \
-	~USBPD_REG_MASK_CC2_DISCONNECT)
-#define USBPD_CC2_DISCONNECTED(p) \
+	 ~USBPD_REG_MASK_CC2_DISCONNECT)
+#define USBPD_CC2_DISCONNECTED(p)                                  \
 	((IT83XX_USBPD_CCCSR(p) | USBPD_REG_MASK_CC2_DISCONNECT) & \
-	~USBPD_REG_MASK_CC1_DISCONNECT)
+	 ~USBPD_REG_MASK_CC1_DISCONNECT)
 
 /* macros for get */
-#define USBPD_GET_POWER_ROLE(port)                  \
-	(IT83XX_USBPD_MHSR1(port) & BIT(0))
+#define USBPD_GET_POWER_ROLE(port) (IT83XX_USBPD_MHSR1(port) & BIT(0))
 #define USBPD_GET_CC1_PULL_REGISTER_SELECTION(port) \
 	(IT83XX_USBPD_CCCSR(port) & BIT(1))
 #define USBPD_GET_CC2_PULL_REGISTER_SELECTION(port) \
 	(IT83XX_USBPD_CCCSR(port) & BIT(1))
-#define USBPD_GET_PULL_CC_SELECTION(port)           \
-	(IT83XX_USBPD_CCGCR(port) & BIT(0))
-#define USBPD_GET_SNK_COMPARE_CC1_VOLT(port)        \
-	(IT83XX_USBPD_SNKVCRR(port) &               \
-		(USBPD_REG_MASK_SNK_COMPARE_CC1_VOLT_L |  \
-		USBPD_REG_MASK_SNK_COMPARE_CC1_VOLT_M |   \
-		USBPD_REG_MASK_SNK_COMPARE_CC1_VOLT_H))
-#define USBPD_GET_SNK_COMPARE_CC2_VOLT(port)        \
-	((IT83XX_USBPD_SNKVCRR(port) &              \
-		(USBPD_REG_MASK_SNK_COMPARE_CC2_VOLT_L |  \
-		USBPD_REG_MASK_SNK_COMPARE_CC2_VOLT_M |   \
-		USBPD_REG_MASK_SNK_COMPARE_CC2_VOLT_H)) >> 4)
-#define USBPD_GET_SRC_COMPARE_CC1_VOLT(port)        \
-	(IT83XX_USBPD_SRCVCRR(port) &               \
-		(USBPD_REG_MASK_SRC_COMPARE_CC1_VOLT_L |  \
-		USBPD_REG_MASK_SRC_COMPARE_CC1_VOLT_H))
-#define USBPD_GET_SRC_COMPARE_CC2_VOLT(port)        \
-	((IT83XX_USBPD_SRCVCRR(port) &              \
-		(USBPD_REG_MASK_SRC_COMPARE_CC2_VOLT_L |  \
-		USBPD_REG_MASK_SRC_COMPARE_CC2_VOLT_H)) >> 4)
+#define USBPD_GET_PULL_CC_SELECTION(port) (IT83XX_USBPD_CCGCR(port) & BIT(0))
+#define USBPD_GET_SNK_COMPARE_CC1_VOLT(port)                                   \
+	(IT83XX_USBPD_SNKVCRR(port) & (USBPD_REG_MASK_SNK_COMPARE_CC1_VOLT_L | \
+				       USBPD_REG_MASK_SNK_COMPARE_CC1_VOLT_M | \
+				       USBPD_REG_MASK_SNK_COMPARE_CC1_VOLT_H))
+#define USBPD_GET_SNK_COMPARE_CC2_VOLT(port)          \
+	((IT83XX_USBPD_SNKVCRR(port) &                \
+	  (USBPD_REG_MASK_SNK_COMPARE_CC2_VOLT_L |    \
+	   USBPD_REG_MASK_SNK_COMPARE_CC2_VOLT_M |    \
+	   USBPD_REG_MASK_SNK_COMPARE_CC2_VOLT_H)) >> \
+	 4)
+#define USBPD_GET_SRC_COMPARE_CC1_VOLT(port)                                   \
+	(IT83XX_USBPD_SRCVCRR(port) & (USBPD_REG_MASK_SRC_COMPARE_CC1_VOLT_L | \
+				       USBPD_REG_MASK_SRC_COMPARE_CC1_VOLT_H))
+#define USBPD_GET_SRC_COMPARE_CC2_VOLT(port)          \
+	((IT83XX_USBPD_SRCVCRR(port) &                \
+	  (USBPD_REG_MASK_SRC_COMPARE_CC2_VOLT_L |    \
+	   USBPD_REG_MASK_SRC_COMPARE_CC2_VOLT_H)) >> \
+	 4)
 
 /* macros for check */
-#define USBPD_IS_TX_ERR(port)           \
+#define USBPD_IS_TX_ERR(port) \
 	IS_MASK_SET(IT83XX_USBPD_ISR(port), USBPD_REG_MASK_TX_ERROR_STAT)
 #endif /* !defined(CONFIG_USB_PD_TCPM_DRIVER_IT83XX) */
 
@@ -364,20 +343,20 @@
 	IS_MASK_SET(IT83XX_USBPD_ISR(port), USBPD_REG_MASK_HARD_RESET_DETECT)
 #define USBPD_IS_HARD_CABLE_RESET_TX_DONE(port) \
 	IS_MASK_SET(IT83XX_USBPD_ISR(port),     \
-		USBPD_REG_MASK_HARD_CABLE_RESET_TX_DONE)
-#define USBPD_IS_TX_DONE(port)           \
+		    USBPD_REG_MASK_HARD_CABLE_RESET_TX_DONE)
+#define USBPD_IS_TX_DONE(port) \
 	IS_MASK_SET(IT83XX_USBPD_ISR(port), USBPD_REG_MASK_MSG_TX_DONE)
-#define USBPD_IS_RX_DONE(port)           \
+#define USBPD_IS_RX_DONE(port) \
 	IS_MASK_SET(IT83XX_USBPD_ISR(port), USBPD_REG_MASK_MSG_RX_DONE)
-#define USBPD_IS_PLUG_IN_OUT_DETECT(port)\
+#define USBPD_IS_PLUG_IN_OUT_DETECT(port) \
 	IS_MASK_SET(IT83XX_USBPD_TCDCR(port), USBPD_REG_PLUG_IN_OUT_DETECT_STAT)
-#define USBPD_IS_PLUG_IN(port)           \
+#define USBPD_IS_PLUG_IN(port) \
 	IS_MASK_CLEAR(IT83XX_USBPD_TCDCR(port), USBPD_REG_PLUG_OUT_SELECT)
 #if defined(CONFIG_USB_PD_TCPM_DRIVER_IT83XX)
-#define USBPD_IS_FAST_SWAP_DETECT(port)  \
+#define USBPD_IS_FAST_SWAP_DETECT(port) \
 	IS_MASK_SET(IT83XX_USBPD_PD30IR(port), USBPD_REG_FAST_SWAP_DETECT_STAT)
 #elif defined(CONFIG_USB_PD_TCPM_DRIVER_IT8XXX2)
-#define USBPD_IS_FAST_SWAP_DETECT(port)  \
+#define USBPD_IS_FAST_SWAP_DETECT(port) \
 	IS_MASK_SET(IT83XX_USBPD_IFS(port), USBPD_REG_FAST_SWAP_DETECT_STAT)
 #endif
 
@@ -385,16 +364,16 @@
 /* Use the Zephyr names here. When upstreaming we can update this */
 #include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
 
-#define IT83XX_GPIO_GPCRF4	GPCRF4
-#define IT83XX_GPIO_GPCRF5	GPCRF5
-#define IT83XX_GPIO_GPCRH1	GPCRH1
-#define IT83XX_GPIO_GPCRH2	GPCRH2
-#define IT83XX_GPIO_GPCRP0	IT8XXX2_GPIO_GPCRP0
-#define IT83XX_GPIO_GPCRP1	IT8XXX2_GPIO_GPCRP1
-#define IT83XX_IRQ_USBPD0	IT8XXX2_IRQ_USBPD0
-#define IT83XX_IRQ_USBPD1	IT8XXX2_IRQ_USBPD1
-#define IT83XX_IRQ_USBPD2	IT8XXX2_IRQ_USBPD2
-#define USB_VID_ITE		0x048d
+#define IT83XX_GPIO_GPCRF4 GPCRF4
+#define IT83XX_GPIO_GPCRF5 GPCRF5
+#define IT83XX_GPIO_GPCRH1 GPCRH1
+#define IT83XX_GPIO_GPCRH2 GPCRH2
+#define IT83XX_GPIO_GPCRP0 IT8XXX2_GPIO_GPCRP0
+#define IT83XX_GPIO_GPCRP1 IT8XXX2_GPIO_GPCRP1
+#define IT83XX_IRQ_USBPD0 IT8XXX2_IRQ_USBPD0
+#define IT83XX_IRQ_USBPD1 IT8XXX2_IRQ_USBPD1
+#define IT83XX_IRQ_USBPD2 IT8XXX2_IRQ_USBPD2
+#define USB_VID_ITE 0x048d
 
 /* ITE chip supports PD features */
 #define IT83XX_INTC_FAST_SWAP_SUPPORT
@@ -409,14 +388,14 @@ enum usbpd_port {
 
 enum usbpd_ufp_volt_status {
 	USBPD_UFP_STATE_SNK_OPEN = 0,
-	USBPD_UFP_STATE_SNK_DEF  = 1,
-	USBPD_UFP_STATE_SNK_1_5  = 3,
-	USBPD_UFP_STATE_SNK_3_0  = 7,
+	USBPD_UFP_STATE_SNK_DEF = 1,
+	USBPD_UFP_STATE_SNK_1_5 = 3,
+	USBPD_UFP_STATE_SNK_3_0 = 7,
 };
 
 enum usbpd_dfp_volt_status {
-	USBPD_DFP_STATE_SRC_RA   = 0,
-	USBPD_DFP_STATE_SRC_RD   = 1,
+	USBPD_DFP_STATE_SRC_RA = 0,
+	USBPD_DFP_STATE_SRC_RD = 1,
 	USBPD_DFP_STATE_SRC_OPEN = 3,
 };
 
diff --git a/driver/tcpm/it8xxx2.c b/driver/tcpm/it8xxx2.c
index e1d4ad5d5c..6782b528e5 100644
--- a/driver/tcpm/it8xxx2.c
+++ b/driver/tcpm/it8xxx2.c
@@ -1,10 +1,11 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* TCPM on ITE chip it8xxx2 with embedded TCPC */
 
+#include "builtin/assert.h"
 #include "common.h"
 #include "config.h"
 #include "console.h"
@@ -22,8 +23,8 @@
 
 #ifdef CONFIG_USB_PD_TCPMV1
 #if defined(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE) || \
-	defined(CONFIG_USB_PD_VBUS_DETECT_TCPC) || \
-	defined(CONFIG_USB_PD_TCPC_LOW_POWER) || \
+	defined(CONFIG_USB_PD_VBUS_DETECT_TCPC) ||  \
+	defined(CONFIG_USB_PD_TCPC_LOW_POWER) ||    \
 	defined(CONFIG_USB_PD_DISCHARGE_TCPC)
 #error "Unsupported config options of IT8xxx2 PD driver"
 #endif
@@ -36,17 +37,17 @@
 #endif
 #endif
 
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 bool rx_en[IT83XX_USBPD_PHY_PORT_COUNT];
 STATIC_IF(CONFIG_USB_PD_DECODE_SOP)
-	bool sop_prime_en[IT83XX_USBPD_PHY_PORT_COUNT];
-static uint8_t tx_error_status[IT83XX_USBPD_PHY_PORT_COUNT] = {0};
+bool sop_prime_en[IT83XX_USBPD_PHY_PORT_COUNT];
+static uint8_t tx_error_status[IT83XX_USBPD_PHY_PORT_COUNT] = { 0 };
 
 const struct usbpd_ctrl_t usbpd_ctrl_regs[] = {
-	{&IT83XX_GPIO_GPCRF4, &IT83XX_GPIO_GPCRF5, IT83XX_IRQ_USBPD0},
-	{&IT83XX_GPIO_GPCRH1, &IT83XX_GPIO_GPCRH2, IT83XX_IRQ_USBPD1},
-	{&IT83XX_GPIO_GPCRP0, &IT83XX_GPIO_GPCRP1, IT83XX_IRQ_USBPD2},
+	{ &IT83XX_GPIO_GPCRF4, &IT83XX_GPIO_GPCRF5, IT83XX_IRQ_USBPD0 },
+	{ &IT83XX_GPIO_GPCRH1, &IT83XX_GPIO_GPCRH2, IT83XX_IRQ_USBPD1 },
+	{ &IT83XX_GPIO_GPCRP0, &IT83XX_GPIO_GPCRP1, IT83XX_IRQ_USBPD2 },
 };
 BUILD_ASSERT(ARRAY_SIZE(usbpd_ctrl_regs) >= IT83XX_USBPD_PHY_PORT_COUNT);
 
@@ -58,8 +59,8 @@ BUILD_ASSERT(ARRAY_SIZE(usbpd_ctrl_regs) >= IT83XX_USBPD_PHY_PORT_COUNT);
 void it83xx_Rd_5_1K_only_for_hibernate(int port)
 {
 	uint8_t cc_config = (port == USBPD_PORT_C ?
-			     IT83XX_USBPD_CC_PIN_CONFIG2 :
-			     IT83XX_USBPD_CC_PIN_CONFIG);
+				     IT83XX_USBPD_CC_PIN_CONFIG2 :
+				     IT83XX_USBPD_CC_PIN_CONFIG);
 
 	/* This only apply to active PD port */
 	if (*usbpd_ctrl_regs[port].cc1 == cc_config &&
@@ -130,7 +131,7 @@ static enum tcpc_cc_voltage_status it8xxx2_get_cc(enum usbpd_port port,
 			cc_state = TYPEC_CC_VOLT_OPEN;
 			break;
 		}
-	/* Source */
+		/* Source */
 	} else {
 		if (cc_pin == USBPD_CC_PIN_1)
 			dfp_volt = USBPD_GET_SRC_COMPARE_CC1_VOLT(port);
@@ -214,12 +215,12 @@ static enum tcpc_transmit_complete it8xxx2_tx_data(enum usbpd_port port,
 	 * Bit[2:0] Tx message type
 	 * 000b=SOP, 001b=SOP', 010b=SOP", 011b=Debug SOP', 100b=Debug SOP''.
 	 */
-	IT83XX_USBPD_MTSR0(port) =
-		(IT83XX_USBPD_MTSR0(port) & ~0x7) | (type & 0x7);
+	IT83XX_USBPD_MTSR0(port) = (IT83XX_USBPD_MTSR0(port) & ~0x7) |
+				   (type & 0x7);
 
 	/* According PD version set HW auto retry count */
 	IT83XX_USBPD_PDCSR0(port) = (IT83XX_USBPD_PDCSR0(port) & ~0xC0) |
-					(retry_count << 6);
+				    (retry_count << 6);
 
 	/* Limited by PD_HEADER_CNT() */
 	ASSERT(length <= 0x7);
@@ -244,7 +245,7 @@ static enum tcpc_transmit_complete it8xxx2_tx_data(enum usbpd_port port,
 		 */
 		if (tx_error_status[port] || (evt & TASK_EVENT_TIMER)) {
 			if (tx_error_status[port] &
-					USBPD_REG_MASK_TX_NOT_EN_STAT) {
+			    USBPD_REG_MASK_TX_NOT_EN_STAT) {
 				CPRINTS("p%d TxErr: Tx EN and resend", port);
 				tx_error_status[port] &=
 					~USBPD_REG_MASK_TX_NOT_EN_STAT;
@@ -252,13 +253,13 @@ static enum tcpc_transmit_complete it8xxx2_tx_data(enum usbpd_port port,
 					USBPD_REG_MASK_TX_MESSAGE_ENABLE;
 				continue;
 			} else if (tx_error_status[port] &
-					USBPD_REG_MASK_TX_DISCARD_STAT) {
+				   USBPD_REG_MASK_TX_DISCARD_STAT) {
 				CPRINTS("p%d TxErr: Discard and resend", port);
 				tx_error_status[port] &=
 					~USBPD_REG_MASK_TX_DISCARD_STAT;
 				continue;
 			} else if (tx_error_status[port] &
-					USBPD_REG_MASK_TX_NO_RESPONSE_STAT) {
+				   USBPD_REG_MASK_TX_NO_RESPONSE_STAT) {
 				/* HW had automatically resent message twice */
 				tx_error_status[port] &=
 					~USBPD_REG_MASK_TX_NO_RESPONSE_STAT;
@@ -290,8 +291,8 @@ static enum tcpc_transmit_complete it8xxx2_send_hw_reset(enum usbpd_port port)
 	return TCPC_TX_COMPLETE_SUCCESS;
 }
 
-static enum tcpc_transmit_complete it8xxx2_send_cable_reset(
-						enum usbpd_port port)
+static enum tcpc_transmit_complete
+it8xxx2_send_cable_reset(enum usbpd_port port)
 {
 	/* Send cable reset */
 	USBPD_SEND_CABLE_RESET(port);
@@ -324,14 +325,16 @@ static void it8xxx2_enable_vconn(enum usbpd_port port, int enabled)
 		/* Disable unused CC to become VCONN */
 		if (cc_pin == USBPD_CC_PIN_1) {
 			IT83XX_USBPD_CCCSR(port) = USBPD_CC2_DISCONNECTED(port);
-			IT83XX_USBPD_CCPSR(port) = (IT83XX_USBPD_CCPSR(port)
-				& ~USBPD_REG_MASK_DISCONNECT_POWER_CC2)
-				| USBPD_REG_MASK_DISCONNECT_POWER_CC1;
+			IT83XX_USBPD_CCPSR(port) =
+				(IT83XX_USBPD_CCPSR(port) &
+				 ~USBPD_REG_MASK_DISCONNECT_POWER_CC2) |
+				USBPD_REG_MASK_DISCONNECT_POWER_CC1;
 		} else {
 			IT83XX_USBPD_CCCSR(port) = USBPD_CC1_DISCONNECTED(port);
-			IT83XX_USBPD_CCPSR(port) = (IT83XX_USBPD_CCPSR(port)
-				& ~USBPD_REG_MASK_DISCONNECT_POWER_CC1)
-				| USBPD_REG_MASK_DISCONNECT_POWER_CC2;
+			IT83XX_USBPD_CCPSR(port) =
+				(IT83XX_USBPD_CCPSR(port) &
+				 ~USBPD_REG_MASK_DISCONNECT_POWER_CC1) |
+				USBPD_REG_MASK_DISCONNECT_POWER_CC2;
 		}
 	} else {
 		/* Connect cc analog module (ex.UP/RD/DET/TX/RX) */
@@ -340,7 +343,7 @@ static void it8xxx2_enable_vconn(enum usbpd_port port, int enabled)
 		/* Disable cc 5v tolerant */
 		IT83XX_USBPD_CCPSR(port) |=
 			(USBPD_REG_MASK_DISCONNECT_POWER_CC1 |
-			USBPD_REG_MASK_DISCONNECT_POWER_CC2);
+			 USBPD_REG_MASK_DISCONNECT_POWER_CC2);
 	}
 }
 
@@ -440,8 +443,7 @@ static int it8xxx2_tcpm_release(int port)
 	return EC_ERROR_UNIMPLEMENTED;
 }
 
-static int it8xxx2_tcpm_get_cc(int port,
-			       enum tcpc_cc_voltage_status *cc1,
+static int it8xxx2_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
 			       enum tcpc_cc_voltage_status *cc2)
 {
 	*cc2 = it8xxx2_get_cc(port, USBPD_CC_PIN_2);
@@ -487,7 +489,8 @@ static int it8xxx2_tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity)
 {
 	enum usbpd_cc_pin cc_pin =
 		(polarity == POLARITY_CC1 || polarity == POLARITY_CC1_DTS) ?
-		USBPD_CC_PIN_1 : USBPD_CC_PIN_2;
+			USBPD_CC_PIN_1 :
+			USBPD_CC_PIN_2;
 
 	it8xxx2_select_polarity(port, cc_pin);
 
@@ -504,13 +507,11 @@ __maybe_unused static int it8xxx2_tcpm_decode_sop_prime_enable(int port,
 		return EC_SUCCESS;
 
 	if (enable)
-		IT83XX_USBPD_PDCSR1(port) |=
-			(USBPD_REG_MASK_SOPP_RX_ENABLE |
-			 USBPD_REG_MASK_SOPPP_RX_ENABLE);
+		IT83XX_USBPD_PDCSR1(port) |= (USBPD_REG_MASK_SOPP_RX_ENABLE |
+					      USBPD_REG_MASK_SOPPP_RX_ENABLE);
 	else
-		IT83XX_USBPD_PDCSR1(port) &=
-			~(USBPD_REG_MASK_SOPP_RX_ENABLE |
-			  USBPD_REG_MASK_SOPPP_RX_ENABLE);
+		IT83XX_USBPD_PDCSR1(port) &= ~(USBPD_REG_MASK_SOPP_RX_ENABLE |
+					       USBPD_REG_MASK_SOPPP_RX_ENABLE);
 
 	return EC_SUCCESS;
 }
@@ -535,7 +536,8 @@ static int it8xxx2_tcpm_set_vconn(int port, int enable)
 			/* Turn on Vconn power switch. */
 			board_pd_vconn_ctrl(port,
 					    USBPD_GET_PULL_CC_SELECTION(port) ?
-					    USBPD_CC_PIN_2 : USBPD_CC_PIN_1,
+						    USBPD_CC_PIN_2 :
+						    USBPD_CC_PIN_1,
 					    enable);
 		} else {
 			/*
@@ -592,26 +594,25 @@ static int it8xxx2_tcpm_set_rx_enable(int port, int enable)
 	if (enable) {
 		IT83XX_USBPD_IMR(port) &= ~USBPD_REG_MASK_MSG_RX_DONE;
 		IT83XX_USBPD_PDCSR1(port) |=
-				(USBPD_REG_MASK_SOP_RX_ENABLE |
-				 USBPD_REG_MASK_HARD_RESET_RX_ENABLE);
+			(USBPD_REG_MASK_SOP_RX_ENABLE |
+			 USBPD_REG_MASK_HARD_RESET_RX_ENABLE);
 		if (IS_ENABLED(CONFIG_USB_PD_DECODE_SOP))
-			it8xxx2_tcpm_decode_sop_prime_enable(port,
-							sop_prime_en[port]);
+			it8xxx2_tcpm_decode_sop_prime_enable(
+				port, sop_prime_en[port]);
 	} else {
 		IT83XX_USBPD_IMR(port) |= USBPD_REG_MASK_MSG_RX_DONE;
-		IT83XX_USBPD_PDCSR1(port) &= ~(USBPD_REG_MASK_SOP_RX_ENABLE |
-					USBPD_REG_MASK_SOPP_RX_ENABLE |
-					USBPD_REG_MASK_SOPPP_RX_ENABLE |
-					USBPD_REG_MASK_HARD_RESET_RX_ENABLE);
+		IT83XX_USBPD_PDCSR1(port) &=
+			~(USBPD_REG_MASK_SOP_RX_ENABLE |
+			  USBPD_REG_MASK_SOPP_RX_ENABLE |
+			  USBPD_REG_MASK_SOPPP_RX_ENABLE |
+			  USBPD_REG_MASK_HARD_RESET_RX_ENABLE);
 	}
 
 	return EC_SUCCESS;
 }
 
-static int it8xxx2_tcpm_transmit(int port,
-				 enum tcpci_msg_type type,
-				 uint16_t header,
-				 const uint32_t *data)
+static int it8xxx2_tcpm_transmit(int port, enum tcpci_msg_type type,
+				 uint16_t header, const uint32_t *data)
 {
 	int status = TCPC_TX_COMPLETE_FAILED;
 
@@ -621,10 +622,7 @@ static int it8xxx2_tcpm_transmit(int port,
 	case TCPCI_MSG_SOP_PRIME_PRIME:
 	case TCPCI_MSG_SOP_DEBUG_PRIME:
 	case TCPCI_MSG_SOP_DEBUG_PRIME_PRIME:
-		status = it8xxx2_tx_data(port,
-					 type,
-					 header,
-					 data);
+		status = it8xxx2_tx_data(port, type, header, data);
 		break;
 	case TCPCI_MSG_TX_BIST_MODE_2:
 		it8xxx2_send_bist_mode2_pattern(port);
@@ -645,12 +643,13 @@ static int it8xxx2_tcpm_transmit(int port,
 	return EC_SUCCESS;
 }
 
-static int it8xxx2_tcpm_get_chip_info(int port, int live,
-			struct ec_response_pd_chip_info_v1 *chip_info)
+static int
+it8xxx2_tcpm_get_chip_info(int port, int live,
+			   struct ec_response_pd_chip_info_v1 *chip_info)
 {
 	chip_info->vendor_id = USB_VID_ITE;
-	chip_info->product_id = ((IT83XX_GCTRL_CHIPID1 << 8) |
-				 IT83XX_GCTRL_CHIPID2);
+	chip_info->product_id =
+		((IT83XX_GCTRL_CHIPID1 << 8) | IT83XX_GCTRL_CHIPID2);
 	chip_info->device_id = IT83XX_GCTRL_CHIPVER & 0xf;
 	chip_info->fw_version_number = 0xEC;
 
@@ -687,11 +686,13 @@ static int it8xxx2_tcpm_set_frs_enable(int port, int enable)
 		/* W/C status */
 		IT83XX_USBPD_IFS(port) = 0x33;
 		/* Enable FRS detection (cc to GND) interrupt */
-		IT83XX_USBPD_MIFS(port) &= ~(USBPD_REG_MASK_FAST_SWAP_ISR |
-					USBPD_REG_MASK_FAST_SWAP_DETECT_ISR);
+		IT83XX_USBPD_MIFS(port) &=
+			~(USBPD_REG_MASK_FAST_SWAP_ISR |
+			  USBPD_REG_MASK_FAST_SWAP_DETECT_ISR);
 		/* Enable FRS detection (cc to GND) */
-		IT83XX_USBPD_PDFSCR(port)  = (IT83XX_USBPD_PDFSCR(port) & ~mask)
-					| USBPD_REG_FAST_SWAP_DETECT_ENABLE;
+		IT83XX_USBPD_PDFSCR(port) =
+			(IT83XX_USBPD_PDFSCR(port) & ~mask) |
+			USBPD_REG_FAST_SWAP_DETECT_ENABLE;
 		/*
 		 * TODO(b/160210457): Enable HW auto trigger
 		 * GPH3(port0)/GPH4(port1) output H/L after we detect FRS cc
@@ -699,8 +700,9 @@ static int it8xxx2_tcpm_set_frs_enable(int port, int enable)
 		 */
 	} else {
 		/* Disable FRS detection (cc to GND) interrupt */
-		IT83XX_USBPD_MIFS(port) |= (USBPD_REG_MASK_FAST_SWAP_ISR |
-					USBPD_REG_MASK_FAST_SWAP_DETECT_ISR);
+		IT83XX_USBPD_MIFS(port) |=
+			(USBPD_REG_MASK_FAST_SWAP_ISR |
+			 USBPD_REG_MASK_FAST_SWAP_DETECT_ISR);
 		/* Disable FRS detection and requestion */
 		IT83XX_USBPD_PDFSCR(port) &= ~mask;
 		/*
@@ -724,16 +726,18 @@ static void it8xxx2_tcpm_switch_plug_out_type(int port)
 	if ((cc1 == TYPEC_CC_VOLT_RD && cc2 == TYPEC_CC_VOLT_RD) ||
 	    (cc1 == TYPEC_CC_VOLT_RA && cc2 == TYPEC_CC_VOLT_RA))
 		/* We're source, switch to detect audio/debug plug out. */
-		IT83XX_USBPD_TCDCR(port) = (IT83XX_USBPD_TCDCR(port) &
-				~USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE) |
-				USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT |
-				USBPD_REG_PLUG_OUT_SELECT;
+		IT83XX_USBPD_TCDCR(port) =
+			(IT83XX_USBPD_TCDCR(port) &
+			 ~USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE) |
+			USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT |
+			USBPD_REG_PLUG_OUT_SELECT;
 	else if (cc1 == TYPEC_CC_VOLT_RD || cc2 == TYPEC_CC_VOLT_RD)
 		/* We're source, switch to detect sink plug out. */
-		IT83XX_USBPD_TCDCR(port) = (IT83XX_USBPD_TCDCR(port) &
-				~USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE &
-				~USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT) |
-				USBPD_REG_PLUG_OUT_SELECT;
+		IT83XX_USBPD_TCDCR(port) =
+			(IT83XX_USBPD_TCDCR(port) &
+			 ~USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE &
+			 ~USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT) |
+			USBPD_REG_PLUG_OUT_SELECT;
 	else if (cc1 >= TYPEC_CC_VOLT_RP_DEF || cc2 >= TYPEC_CC_VOLT_RP_DEF)
 		/*
 		 * We're sink, disable detect interrupt, so messages on cc line
@@ -756,8 +760,8 @@ void switch_plug_out_type(enum usbpd_port port)
 static void it8xxx2_init(enum usbpd_port port, int role)
 {
 	uint8_t cc_config = (port == USBPD_PORT_C ?
-			     IT83XX_USBPD_CC_PIN_CONFIG2 :
-			     IT83XX_USBPD_CC_PIN_CONFIG);
+				     IT83XX_USBPD_CC_PIN_CONFIG2 :
+				     IT83XX_USBPD_CC_PIN_CONFIG);
 
 	if (IS_ENABLED(CONFIG_IT83XX_TUNE_CC_PHY)) {
 		/* Tune cc Tx pre-driving time */
@@ -817,7 +821,7 @@ static void it8xxx2_init(enum usbpd_port port, int role)
 	IT83XX_USBPD_TCDCR(port) = (IT83XX_USBPD_TCDCR(port) &
 				    ~(USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE |
 				      USBPD_REG_PLUG_OUT_SELECT)) |
-				    USBPD_REG_PLUG_IN_OUT_DETECT_STAT;
+				   USBPD_REG_PLUG_IN_OUT_DETECT_STAT;
 #endif
 	/* Set cc1/cc2 pins alternate mode */
 	*usbpd_ctrl_regs[port].cc1 = cc_config;
@@ -825,7 +829,8 @@ static void it8xxx2_init(enum usbpd_port port, int role)
 	task_clear_pending_irq(usbpd_ctrl_regs[port].irq);
 #ifdef CONFIG_ZEPHYR
 	irq_connect_dynamic(usbpd_ctrl_regs[port].irq, 0,
-			(void (*)(const void *))chip_pd_irq, (void *)port, 0);
+			    (void (*)(const void *))chip_pd_irq, (void *)port,
+			    0);
 #endif
 	task_enable_irq(usbpd_ctrl_regs[port].irq);
 	USBPD_START(port);
@@ -951,8 +956,9 @@ static void it8xxx2_tcpm_hook_disconnect(void)
 		 * Switch to detect plug in and enable detect plug in interrupt,
 		 * since pd task has detected a type-c physical disconnected.
 		 */
-		IT83XX_USBPD_TCDCR(port) &= ~(USBPD_REG_PLUG_OUT_SELECT |
-			USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE);
+		IT83XX_USBPD_TCDCR(port) &=
+			~(USBPD_REG_PLUG_OUT_SELECT |
+			  USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE);
 
 	/* Exit BIST test data mode */
 	USBPD_SW_RESET(port);
@@ -976,28 +982,28 @@ DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, it8xxx2_tcpm_hook_disconnect,
 	     HOOK_PRIO_DEFAULT);
 
 const struct tcpm_drv it8xxx2_tcpm_drv = {
-	.init			= &it8xxx2_tcpm_init,
-	.release		= &it8xxx2_tcpm_release,
-	.get_cc			= &it8xxx2_tcpm_get_cc,
-	.select_rp_value	= &it8xxx2_tcpm_select_rp_value,
-	.set_cc			= &it8xxx2_tcpm_set_cc,
-	.set_polarity		= &it8xxx2_tcpm_set_polarity,
+	.init = &it8xxx2_tcpm_init,
+	.release = &it8xxx2_tcpm_release,
+	.get_cc = &it8xxx2_tcpm_get_cc,
+	.select_rp_value = &it8xxx2_tcpm_select_rp_value,
+	.set_cc = &it8xxx2_tcpm_set_cc,
+	.set_polarity = &it8xxx2_tcpm_set_polarity,
 #ifdef CONFIG_USB_PD_DECODE_SOP
-	.sop_prime_enable	= &it8xxx2_tcpm_decode_sop_prime_enable,
+	.sop_prime_enable = &it8xxx2_tcpm_decode_sop_prime_enable,
 #endif
-	.set_vconn		= &it8xxx2_tcpm_set_vconn,
-	.set_msg_header		= &it8xxx2_tcpm_set_msg_header,
-	.set_rx_enable		= &it8xxx2_tcpm_set_rx_enable,
-	.get_message_raw	= &it8xxx2_tcpm_get_message_raw,
-	.transmit		= &it8xxx2_tcpm_transmit,
+	.set_vconn = &it8xxx2_tcpm_set_vconn,
+	.set_msg_header = &it8xxx2_tcpm_set_msg_header,
+	.set_rx_enable = &it8xxx2_tcpm_set_rx_enable,
+	.get_message_raw = &it8xxx2_tcpm_get_message_raw,
+	.transmit = &it8xxx2_tcpm_transmit,
 #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-	.drp_toggle		= NULL,
+	.drp_toggle = NULL,
 #endif
-	.get_chip_info		= &it8xxx2_tcpm_get_chip_info,
+	.get_chip_info = &it8xxx2_tcpm_get_chip_info,
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	.enter_low_power_mode	= &it8xxx2_tcpm_enter_low_power_mode,
+	.enter_low_power_mode = &it8xxx2_tcpm_enter_low_power_mode,
 #endif
 #ifdef CONFIG_USB_PD_FRS_TCPC
-	.set_frs_enable		= &it8xxx2_tcpm_set_frs_enable,
+	.set_frs_enable = &it8xxx2_tcpm_set_frs_enable,
 #endif
 };
diff --git a/driver/tcpm/ite_pd_intc.c b/driver/tcpm/ite_pd_intc.c
index 2b5a391dfe..1b5e090d2f 100644
--- a/driver/tcpm/ite_pd_intc.c
+++ b/driver/tcpm/ite_pd_intc.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,8 +16,8 @@ void chip_pd_irq(enum usbpd_port port)
 
 	/* check status */
 	if (IS_ENABLED(IT83XX_INTC_FAST_SWAP_SUPPORT) &&
-		IS_ENABLED(CONFIG_USB_PD_FRS_TCPC) &&
-		IS_ENABLED(CONFIG_USB_PD_REV30)) {
+	    IS_ENABLED(CONFIG_USB_PD_FRS_TCPC) &&
+	    IS_ENABLED(CONFIG_USB_PD_REV30)) {
 		/*
 		 * FRS detection must handle first, because we need to short
 		 * the interrupt -> board_frs_handler latency-critical time.
diff --git a/driver/tcpm/ite_pd_intc.h b/driver/tcpm/ite_pd_intc.h
index 8123e1a233..55768da446 100644
--- a/driver/tcpm/ite_pd_intc.h
+++ b/driver/tcpm/ite_pd_intc.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/driver/tcpm/mt6370.c b/driver/tcpm/mt6370.c
index 7f4cb5b3d3..881b184fad 100644
--- a/driver/tcpm/mt6370.c
+++ b/driver/tcpm/mt6370.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -16,8 +16,8 @@
 #include "usb_pd.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static int mt6370_polarity;
 
@@ -36,7 +36,6 @@ static int mt6370_init(int port)
 
 	/* Only do soft-reset in shipping mode. (b:122017882) */
 	if (!(val & MT6370_REG_SHIPPING_OFF)) {
-
 		/* Software reset. */
 		rv = tcpc_write(port, MT6370_REG_SWRESET, 1);
 		if (rv)
@@ -91,7 +90,7 @@ static inline int mt6370_init_cc_params(int port, int cc_res)
 }
 
 static int mt6370_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2)
+			 enum tcpc_cc_voltage_status *cc2)
 {
 	int status;
 	int rv;
@@ -186,35 +185,36 @@ int mt6370_vconn_discharge(int port)
 
 /* MT6370 is a TCPCI compatible port controller */
 const struct tcpm_drv mt6370_tcpm_drv = {
-	.init			= &mt6370_init,
-	.release		= &tcpci_tcpm_release,
-	.get_cc			= &mt6370_get_cc,
+	.init = &mt6370_init,
+	.release = &tcpci_tcpm_release,
+	.get_cc = &mt6370_get_cc,
 #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	.check_vbus_level	= &tcpci_tcpm_check_vbus_level,
+	.check_vbus_level = &tcpci_tcpm_check_vbus_level,
 #endif
-	.select_rp_value	= &tcpci_tcpm_select_rp_value,
-	.set_cc			= &mt6370_set_cc,
-	.set_polarity		= &mt6370_set_polarity,
+	.select_rp_value = &tcpci_tcpm_select_rp_value,
+	.set_cc = &mt6370_set_cc,
+	.set_polarity = &mt6370_set_polarity,
 #ifdef CONFIG_USB_PD_DECODE_SOP
-	.sop_prime_enable	= &tcpci_tcpm_sop_prime_enable,
+	.sop_prime_enable = &tcpci_tcpm_sop_prime_enable,
 #endif
-	.set_vconn		= &tcpci_tcpm_set_vconn,
-	.set_msg_header		= &tcpci_tcpm_set_msg_header,
-	.set_rx_enable		= &tcpci_tcpm_set_rx_enable,
-	.get_message_raw	= &tcpci_tcpm_get_message_raw,
-	.transmit		= &tcpci_tcpm_transmit,
-	.tcpc_alert		= &tcpci_tcpc_alert,
+	.set_vconn = &tcpci_tcpm_set_vconn,
+	.set_msg_header = &tcpci_tcpm_set_msg_header,
+	.set_rx_enable = &tcpci_tcpm_set_rx_enable,
+	.get_message_raw = &tcpci_tcpm_get_message_raw,
+	.transmit = &tcpci_tcpm_transmit,
+	.tcpc_alert = &tcpci_tcpc_alert,
 #ifdef CONFIG_USB_PD_DISCHARGE_TCPC
-	.tcpc_discharge_vbus	= &tcpci_tcpc_discharge_vbus,
+	.tcpc_discharge_vbus = &tcpci_tcpc_discharge_vbus,
 #endif
 #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-	.drp_toggle		= &tcpci_tcpc_drp_toggle,
+	.drp_toggle = &tcpci_tcpc_drp_toggle,
 #endif
-	.get_chip_info		= &tcpci_get_chip_info,
-	.set_snk_ctrl		= &tcpci_tcpm_set_snk_ctrl,
-	.set_src_ctrl		= &tcpci_tcpm_set_src_ctrl,
+	.get_chip_info = &tcpci_get_chip_info,
+	.set_snk_ctrl = &tcpci_tcpm_set_snk_ctrl,
+	.set_src_ctrl = &tcpci_tcpm_set_src_ctrl,
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	.enter_low_power_mode	= &mt6370_enter_low_power_mode,
+	.enter_low_power_mode = &mt6370_enter_low_power_mode,
 #endif
-	.set_bist_test_mode	= &tcpci_set_bist_test_mode,
+	.set_bist_test_mode = &tcpci_set_bist_test_mode,
+	.get_bist_test_mode = &tcpci_get_bist_test_mode,
 };
diff --git a/driver/tcpm/mt6370.h b/driver/tcpm/mt6370.h
index cdc3112a3e..cc8e14a378 100644
--- a/driver/tcpm/mt6370.h
+++ b/driver/tcpm/mt6370.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,158 +10,158 @@
 
 /* MT6370 Private RegMap */
 
-#define MT6370_REG_PHY_CTRL1			0x80
-#define MT6370_REG_PHY_CTRL2			0x81
-#define MT6370_REG_PHY_CTRL3			0x82
-#define MT6370_REG_PHY_CTRL6			0x85
-
-#define MT6370_REG_CLK_CTRL2			0x87
-#define MT6370_REG_CLK_CTRL3			0x88
-
-#define MT6370_REG_RUST_STATUS			0x8A
-#define MT6370_REG_RUST_INT_EVENT		0x8B
-#define MT6370_REG_RUST_MASK			0x8C
-#define MT6370_REG_BMC_CTRL			0x90
-#define MT6370_REG_BMCIO_RXDZSEL		0x93
-#define MT6370_REG_VCONN_CLIMITEN		0x95
-
-#define MT6370_REG_OVP_FLAG_SEL			0x96
-
-#define MT6370_REG_RT_STATUS			0x97
-#define MT6370_REG_RT_INT			0x98
-#define MT6370_REG_RT_MASK			0x99
-#define RT5081_REG_BMCIO_RXDZEN			0x9A
-#define MT6370_REG_IDLE_CTRL			0x9B
-#define MT6370_REG_INTRST_CTRL			0x9C
-#define MT6370_REG_WATCHDOG_CTRL		0x9D
-#define MT6370_REG_I2CRST_CTRL			0X9E
-
-#define MT6370_REG_SWRESET			0xA0
-#define MT6370_REG_TTCPC_FILTER			0xA1
-#define MT6370_REG_DRP_TOGGLE_CYCLE		0xA2
-#define MT6370_REG_DRP_DUTY_CTRL		0xA3
-#define MT6370_REG_RUST_DETECTION		0xAD
-#define MT6370_REG_RUST_CONTROL			0xAE
-#define MT6370_REG_BMCIO_RXDZEN			0xAF
-#define MT6370_REG_DRP_RUST			0xB9
-
-#define MT6370_REG_UNLOCK_PW2			0xF0
-#define MT6370_REG_UNLOCK_PW1			0xF1
-
-#define MT6370_TCPC_I2C_ADDR_FLAGS		0x4E
+#define MT6370_REG_PHY_CTRL1 0x80
+#define MT6370_REG_PHY_CTRL2 0x81
+#define MT6370_REG_PHY_CTRL3 0x82
+#define MT6370_REG_PHY_CTRL6 0x85
+
+#define MT6370_REG_CLK_CTRL2 0x87
+#define MT6370_REG_CLK_CTRL3 0x88
+
+#define MT6370_REG_RUST_STATUS 0x8A
+#define MT6370_REG_RUST_INT_EVENT 0x8B
+#define MT6370_REG_RUST_MASK 0x8C
+#define MT6370_REG_BMC_CTRL 0x90
+#define MT6370_REG_BMCIO_RXDZSEL 0x93
+#define MT6370_REG_VCONN_CLIMITEN 0x95
+
+#define MT6370_REG_OVP_FLAG_SEL 0x96
+
+#define MT6370_REG_RT_STATUS 0x97
+#define MT6370_REG_RT_INT 0x98
+#define MT6370_REG_RT_MASK 0x99
+#define RT5081_REG_BMCIO_RXDZEN 0x9A
+#define MT6370_REG_IDLE_CTRL 0x9B
+#define MT6370_REG_INTRST_CTRL 0x9C
+#define MT6370_REG_WATCHDOG_CTRL 0x9D
+#define MT6370_REG_I2CRST_CTRL 0X9E
+
+#define MT6370_REG_SWRESET 0xA0
+#define MT6370_REG_TTCPC_FILTER 0xA1
+#define MT6370_REG_DRP_TOGGLE_CYCLE 0xA2
+#define MT6370_REG_DRP_DUTY_CTRL 0xA3
+#define MT6370_REG_RUST_DETECTION 0xAD
+#define MT6370_REG_RUST_CONTROL 0xAE
+#define MT6370_REG_BMCIO_RXDZEN 0xAF
+#define MT6370_REG_DRP_RUST 0xB9
+
+#define MT6370_REG_UNLOCK_PW2 0xF0
+#define MT6370_REG_UNLOCK_PW1 0xF1
+
+#define MT6370_TCPC_I2C_ADDR_FLAGS 0x4E
 
 /*
  * MT6370_REG_PHY_CTRL1				0x80
  */
 
-#define MT6370_REG_PHY_CTRL1_SET(retry_discard, toggle_cnt, bus_idle_cnt,      \
-				 rx_filter)                                    \
-	((retry_discard << 7) | (toggle_cnt << 4) | (bus_idle_cnt << 2) |      \
+#define MT6370_REG_PHY_CTRL1_SET(retry_discard, toggle_cnt, bus_idle_cnt, \
+				 rx_filter)                               \
+	((retry_discard << 7) | (toggle_cnt << 4) | (bus_idle_cnt << 2) | \
 	 (rx_filter & 0x03))
 
 /*
  * MT6370_REG_CLK_CTRL2				0x87
  */
 
-#define MT6370_REG_CLK_DIV_600K_EN		BIT(7)
-#define MT6370_REG_CLK_BCLK2_EN			BIT(6)
-#define MT6370_REG_CLK_BCLK2_TG_EN		BIT(5)
-#define MT6370_REG_CLK_DIV_300K_EN		BIT(3)
-#define MT6370_REG_CLK_CK_300K_EN		BIT(2)
-#define MT6370_REG_CLK_BCLK_EN			BIT(1)
-#define MT6370_REG_CLK_BCLK_TH_EN		BIT(0)
+#define MT6370_REG_CLK_DIV_600K_EN BIT(7)
+#define MT6370_REG_CLK_BCLK2_EN BIT(6)
+#define MT6370_REG_CLK_BCLK2_TG_EN BIT(5)
+#define MT6370_REG_CLK_DIV_300K_EN BIT(3)
+#define MT6370_REG_CLK_CK_300K_EN BIT(2)
+#define MT6370_REG_CLK_BCLK_EN BIT(1)
+#define MT6370_REG_CLK_BCLK_TH_EN BIT(0)
 
 /*
  * MT6370_REG_CLK_CTRL3				0x88
  */
 
-#define MT6370_REG_CLK_OSCMUX_RG_EN		BIT(7)
-#define MT6370_REG_CLK_CK_24M_EN		BIT(6)
-#define MT6370_REG_CLK_OSC_RG_EN		BIT(5)
-#define MT6370_REG_CLK_DIV_2P4M_EN		BIT(4)
-#define MT6370_REG_CLK_CK_2P4M_EN		BIT(3)
-#define MT6370_REG_CLK_PCLK_EN			BIT(2)
-#define MT6370_REG_CLK_PCLK_RG_EN		BIT(1)
-#define MT6370_REG_CLK_PCLK_TG_EN		BIT(0)
+#define MT6370_REG_CLK_OSCMUX_RG_EN BIT(7)
+#define MT6370_REG_CLK_CK_24M_EN BIT(6)
+#define MT6370_REG_CLK_OSC_RG_EN BIT(5)
+#define MT6370_REG_CLK_DIV_2P4M_EN BIT(4)
+#define MT6370_REG_CLK_CK_2P4M_EN BIT(3)
+#define MT6370_REG_CLK_PCLK_EN BIT(2)
+#define MT6370_REG_CLK_PCLK_RG_EN BIT(1)
+#define MT6370_REG_CLK_PCLK_TG_EN BIT(0)
 
 /*
  * MT6370_REG_RX_TX_DBG				0x8b
  */
 
-#define MT6370_REG_RX_TX_DBG_RX_BUSY		BIT(7)
-#define MT6370_REG_RX_TX_DBG_TX_BUSY		BIT(6)
+#define MT6370_REG_RX_TX_DBG_RX_BUSY BIT(7)
+#define MT6370_REG_RX_TX_DBG_TX_BUSY BIT(6)
 
 /*
  * MT6370_REG_BMC_CTRL				0x90
  */
 
-#define MT6370_REG_IDLE_EN			BIT(6)
-#define MT6370_REG_DISCHARGE_EN			BIT(5)
-#define MT6370_REG_BMCIO_LPRPRD			BIT(4)
-#define MT6370_REG_BMCIO_LPEN			BIT(3)
-#define MT6370_REG_BMCIO_BG_EN			BIT(2)
-#define MT6370_REG_VBUS_DET_EN			BIT(1)
-#define MT6370_REG_BMCIO_OSC_EN			BIT(0)
-#define MT6370_REG_BMC_CTRL_DEFAULT                                            \
-	(MT6370_REG_BMCIO_BG_EN | MT6370_REG_VBUS_DET_EN |                     \
+#define MT6370_REG_IDLE_EN BIT(6)
+#define MT6370_REG_DISCHARGE_EN BIT(5)
+#define MT6370_REG_BMCIO_LPRPRD BIT(4)
+#define MT6370_REG_BMCIO_LPEN BIT(3)
+#define MT6370_REG_BMCIO_BG_EN BIT(2)
+#define MT6370_REG_VBUS_DET_EN BIT(1)
+#define MT6370_REG_BMCIO_OSC_EN BIT(0)
+#define MT6370_REG_BMC_CTRL_DEFAULT                        \
+	(MT6370_REG_BMCIO_BG_EN | MT6370_REG_VBUS_DET_EN | \
 	 MT6370_REG_BMCIO_OSC_EN)
 
 /*
  * MT6370_REG_BMCIO_RXDZSEL			0x93
  */
 
-#define MT6370_MASK_OCCTRL_SEL			0xE0
-#define MT6370_OCCTRL_600MA			0x80
-#define MT6370_MASK_BMCIO_RXDZSEL		BIT(0)
+#define MT6370_MASK_OCCTRL_SEL 0xE0
+#define MT6370_OCCTRL_600MA 0x80
+#define MT6370_MASK_BMCIO_RXDZSEL BIT(0)
 
 /*
  * MT6370_REG_OVP_FLAG_SEL			0x96
  */
 
-#define MT6370_MASK_DISCHARGE_LVL		0x03
-#define MT6370_REG_DISCHARGE_LVL		BIT(0)
+#define MT6370_MASK_DISCHARGE_LVL 0x03
+#define MT6370_REG_DISCHARGE_LVL BIT(0)
 
 /*
  * MT6370_REG_RT_STATUS				0x97
  */
 
-#define MT6370_REG_RA_DETACH			BIT(5)
-#define MT6370_REG_VBUS_80			BIT(1)
+#define MT6370_REG_RA_DETACH BIT(5)
+#define MT6370_REG_VBUS_80 BIT(1)
 
 /*
  * MT6370_REG_RT_INT				0x98
  */
 
-#define MT6370_REG_INT_RA_DETACH		BIT(5)
-#define MT6370_REG_INT_WATCHDOG			BIT(2)
-#define MT6370_REG_INT_VBUS_80			BIT(1)
-#define MT6370_REG_INT_WAKEUP			BIT(0)
+#define MT6370_REG_INT_RA_DETACH BIT(5)
+#define MT6370_REG_INT_WATCHDOG BIT(2)
+#define MT6370_REG_INT_VBUS_80 BIT(1)
+#define MT6370_REG_INT_WAKEUP BIT(0)
 
 /*
  * MT6370_REG_RT_MASK				0x99
  */
 
-#define MT6370_REG_M_RA_DETACH			BIT(5)
-#define MT6370_REG_M_WATCHDOG			BIT(2)
-#define MT6370_REG_M_VBUS_80			BIT(1)
-#define MT6370_REG_M_WAKEUP			BIT(0)
+#define MT6370_REG_M_RA_DETACH BIT(5)
+#define MT6370_REG_M_WATCHDOG BIT(2)
+#define MT6370_REG_M_VBUS_80 BIT(1)
+#define MT6370_REG_M_WAKEUP BIT(0)
 
 /*
  * MT6370_REG_IDLE_CTRL				0x9B
  */
 
-#define MT6370_REG_CK_300K_SEL			BIT(7)
-#define MT6370_REG_SHIPPING_OFF			BIT(5)
-#define MT6370_REG_ENEXTMSG			BIT(4)
-#define MT6370_REG_AUTOIDLE_EN			BIT(3)
+#define MT6370_REG_CK_300K_SEL BIT(7)
+#define MT6370_REG_SHIPPING_OFF BIT(5)
+#define MT6370_REG_ENEXTMSG BIT(4)
+#define MT6370_REG_AUTOIDLE_EN BIT(3)
 
 /* timeout = (tout*2+1) * 6.4ms */
 #ifdef CONFIG_USB_PD_REV30
-#define MT6370_REG_IDLE_SET(ck300, ship_dis, auto_idle, tout)                  \
-	((ck300 << 7) | (ship_dis << 5) | (auto_idle << 3) | (tout & 0x07) |   \
+#define MT6370_REG_IDLE_SET(ck300, ship_dis, auto_idle, tout)                \
+	((ck300 << 7) | (ship_dis << 5) | (auto_idle << 3) | (tout & 0x07) | \
 	 MT6370_REG_ENEXTMSG)
 #else
-#define MT6370_REG_IDLE_SET(ck300, ship_dis, auto_idle, tout)                  \
+#define MT6370_REG_IDLE_SET(ck300, ship_dis, auto_idle, tout) \
 	((ck300 << 7) | (ship_dis << 5) | (auto_idle << 3) | (tout & 0x07))
 #endif
 
@@ -169,28 +169,28 @@
  * MT6370_REG_INTRST_CTRL			0x9C
  */
 
-#define MT6370_REG_INTRST_EN			BIT(7)
+#define MT6370_REG_INTRST_EN BIT(7)
 
 /* timeout = (tout+1) * 0.2sec */
-#define MT6370_REG_INTRST_SET(en, tout)		((en << 7) | (tout & 0x03))
+#define MT6370_REG_INTRST_SET(en, tout) ((en << 7) | (tout & 0x03))
 
 /*
  * MT6370_REG_WATCHDOG_CTRL			0x9D
  */
 
-#define MT6370_REG_WATCHDOG_EN			BIT(7)
+#define MT6370_REG_WATCHDOG_EN BIT(7)
 
 /* timeout = (tout+1) * 0.4sec */
-#define MT6370_REG_WATCHDOG_CTRL_SET(en, tout)	((en << 7) | (tout & 0x07))
+#define MT6370_REG_WATCHDOG_CTRL_SET(en, tout) ((en << 7) | (tout & 0x07))
 
 /*
  * MT6370_REG_I2CRST_CTRL			0x9E
  */
 
-#define MT6370_REG_I2CRST_EN			BIT(7)
+#define MT6370_REG_I2CRST_EN BIT(7)
 
 /* timeout = (tout+1) * 12.5ms */
-#define MT6370_REG_I2CRST_SET(en, tout)		((en << 7) | (tout & 0x0f))
+#define MT6370_REG_I2CRST_SET(en, tout) ((en << 7) | (tout & 0x0f))
 
 extern const struct tcpm_drv mt6370_tcpm_drv;
 
diff --git a/driver/tcpm/nct38xx.c b/driver/tcpm/nct38xx.c
index 8b6690524c..f6184b21e4 100644
--- a/driver/tcpm/nct38xx.c
+++ b/driver/tcpm/nct38xx.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -30,8 +30,8 @@
 #error "Please upgrade your board configuration"
 #endif
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 static enum nct38xx_boot_type boot_type[CONFIG_USB_PD_PORT_MAX_COUNT];
 
@@ -74,9 +74,10 @@ static int nct38xx_init(int port)
 	 * accessory and change this bit (see b/186799392).
 	 */
 	if ((boot_type[port] == NCT38XX_BOOT_DEAD_BATTERY) &&
-				(reg & TCPC_REG_POWER_STATUS_DEBUG_ACC_CON))
+	    (reg & TCPC_REG_POWER_STATUS_DEBUG_ACC_CON))
 		CPRINTS("C%d: Booted in dead battery mode, not changing debug"
-			" control", port);
+			" control",
+			port);
 	else if (tcpc_config[port].flags & TCPC_FLAGS_NO_DEBUG_ACC_CONTROL)
 		CPRINTS("C%d: NO_DEBUG_ACC_CONTROL", port);
 	else
@@ -90,8 +91,7 @@ static int nct38xx_init(int port)
 	 * [2] - SNKEN     : VBUS sink enable output enable
 	 * [0] - SRCEN     : VBUS source voltage enable output enable
 	 */
-	reg = NCT38XX_REG_CTRL_OUT_EN_SRCEN |
-	      NCT38XX_REG_CTRL_OUT_EN_SNKEN |
+	reg = NCT38XX_REG_CTRL_OUT_EN_SRCEN | NCT38XX_REG_CTRL_OUT_EN_SNKEN |
 	      NCT38XX_REG_CTRL_OUT_EN_CONNDIREN;
 
 	rv = tcpc_write(port, NCT38XX_REG_CTRL_OUT_EN, reg);
@@ -99,16 +99,13 @@ static int nct38xx_init(int port)
 		return rv;
 
 	/* Disable OVP */
-	rv = tcpc_update8(port,
-			  TCPC_REG_FAULT_CTRL,
-			  TCPC_REG_FAULT_CTRL_VBUS_OVP_FAULT_DIS,
-			  MASK_SET);
+	rv = tcpc_update8(port, TCPC_REG_FAULT_CTRL,
+			  TCPC_REG_FAULT_CTRL_VBUS_OVP_FAULT_DIS, MASK_SET);
 	if (rv)
 		return rv;
 
 	/* Enable VBus monitor and Disable FRS */
-	rv = tcpc_update8(port,
-			  TCPC_REG_POWER_CTRL,
+	rv = tcpc_update8(port, TCPC_REG_POWER_CTRL,
 			  (TCPC_REG_POWER_CTRL_VBUS_VOL_MONITOR_DIS |
 			   TCPC_REG_POWER_CTRL_FRS_ENABLE),
 			  MASK_CLR);
@@ -159,10 +156,7 @@ static int nct38xx_init(int port)
 		reg |= TCPC_REG_ALERT_VENDOR_DEF;
 	}
 
-	rv = tcpc_update16(port,
-			   TCPC_REG_ALERT_MASK,
-			   reg,
-			   MASK_SET);
+	rv = tcpc_update16(port, TCPC_REG_ALERT_MASK, reg, MASK_SET);
 
 	if (rv)
 		return rv;
@@ -172,10 +166,7 @@ static int nct38xx_init(int port)
 	      NCT38XX_REG_VBC_FAULT_CTL_VC_SCP_EN |
 	      NCT38XX_REG_VBC_FAULT_CTL_FAULT_VC_OFF;
 
-	rv = tcpc_update8(port,
-			  NCT38XX_REG_VBC_FAULT_CTL,
-			  reg,
-			  MASK_SET);
+	rv = tcpc_update8(port, NCT38XX_REG_VBC_FAULT_CTL, reg, MASK_SET);
 
 	return rv;
 }
@@ -218,13 +209,11 @@ static int nct38xx_tcpm_set_cc(int port, int pull)
 	 */
 	int rv;
 	enum mask_update_action action =
-			pull == TYPEC_CC_OPEN && tcpm_get_snk_ctrl(port) ?
-				MASK_CLR : MASK_SET;
+		pull == TYPEC_CC_OPEN && tcpm_get_snk_ctrl(port) ? MASK_CLR :
+								   MASK_SET;
 
-	rv = tcpc_update8(port,
-			  NCT38XX_REG_CTRL_OUT_EN,
-			  NCT38XX_REG_CTRL_OUT_EN_SNKEN,
-			  action);
+	rv = tcpc_update8(port, NCT38XX_REG_CTRL_OUT_EN,
+			  NCT38XX_REG_CTRL_OUT_EN_SNKEN, action);
 	if (rv)
 		return rv;
 
@@ -240,10 +229,8 @@ static int nct38xx_tcpm_set_snk_ctrl(int port, int enable)
 	 * USB_Cx_TCPC_VBSNK_EN_L will be driven high.
 	 */
 	if (!enable) {
-		rv = tcpc_update8(port,
-				  NCT38XX_REG_CTRL_OUT_EN,
-				  NCT38XX_REG_CTRL_OUT_EN_SNKEN,
-				  MASK_SET);
+		rv = tcpc_update8(port, NCT38XX_REG_CTRL_OUT_EN,
+				  NCT38XX_REG_CTRL_OUT_EN_SNKEN, MASK_SET);
 		if (rv)
 			return rv;
 	}
@@ -253,9 +240,9 @@ static int nct38xx_tcpm_set_snk_ctrl(int port, int enable)
 
 static inline int tcpc_read_alert_no_lpm_exit(int port, int *val)
 {
-	return tcpc_addr_read16_no_lpm_exit(port,
-					tcpc_config[port].i2c_info.addr_flags,
-					TCPC_REG_ALERT, val);
+	return tcpc_addr_read16_no_lpm_exit(
+		port, tcpc_config[port].i2c_info.addr_flags, TCPC_REG_ALERT,
+		val);
 }
 
 /* Map Type-C port to IOEX port */
@@ -289,9 +276,9 @@ static void nct38xx_tcpc_alert(int port)
 	 * The nct38xx exits Idle mode when ALERT is signaled, so there
 	 * is no need to run the TCPM LPM exit code to check the ALERT
 	 * register bits (Ref. NCT38n7/8 Datasheet S 2.3.4 "Setting the
-	 * I2C to * Idle"). In fact, running the TCPM LPM exit code
-	 * causes a new CC Status ALERT which has the effect of creating
-	 * a new ALERT as a side-effect of handing an ALERT.
+	 * I2C to Idle"). In fact, running the TCPM LPM exit code causes
+	 * a new CC Status ALERT which has the effect of creating a new
+	 * ALERT as a side-effect of handing an ALERT.
 	 */
 	rv = tcpc_read_alert_no_lpm_exit(port, &alert);
 	if (rv == EC_SUCCESS && alert == TCPC_REG_ALERT_NONE) {
@@ -326,10 +313,10 @@ static int nct3807_handle_fault(int port, int fault)
 		/* We don't use TCPC OVP, so just disable it */
 		if (fault & TCPC_REG_FAULT_STATUS_VBUS_OVER_VOLTAGE) {
 			/* Disable OVP */
-			rv = tcpc_update8(port,
-				  TCPC_REG_FAULT_CTRL,
-				  TCPC_REG_FAULT_CTRL_VBUS_OVP_FAULT_DIS,
-				  MASK_SET);
+			rv = tcpc_update8(
+				port, TCPC_REG_FAULT_CTRL,
+				TCPC_REG_FAULT_CTRL_VBUS_OVP_FAULT_DIS,
+				MASK_SET);
 			if (rv)
 				return rv;
 		}
@@ -354,57 +341,58 @@ __maybe_unused static int nct38xx_set_frs_enable(int port, int enable)
 	 * 2. Enable the FRS interrupt (already done in TCPCI alert init)
 	 * 3. Set POWER_CONTORL.FastRoleSwapEnable to 1
 	 */
-	RETURN_ERROR(tcpc_write16(port,
-				TCPC_REG_VBUS_SINK_DISCONNECT_THRESH,
-				enable ? 0x0000 :
-				TCPC_REG_VBUS_SINK_DISCONNECT_THRESH_DEFAULT));
+	RETURN_ERROR(tcpc_write16(
+		port, TCPC_REG_VBUS_SINK_DISCONNECT_THRESH,
+		enable ? 0x0000 :
+			 TCPC_REG_VBUS_SINK_DISCONNECT_THRESH_DEFAULT));
 
-	return tcpc_update8(port,
-			    TCPC_REG_POWER_CTRL,
+	return tcpc_update8(port, TCPC_REG_POWER_CTRL,
 			    TCPC_REG_POWER_CTRL_FRS_ENABLE,
 			    enable ? MASK_SET : MASK_CLR);
 }
 
 const struct tcpm_drv nct38xx_tcpm_drv = {
-	.init			= &nct38xx_tcpm_init,
-	.release		= &tcpci_tcpm_release,
-	.get_cc			= &tcpci_tcpm_get_cc,
+	.init = &nct38xx_tcpm_init,
+	.release = &tcpci_tcpm_release,
+	.get_cc = &tcpci_tcpm_get_cc,
 #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	.check_vbus_level	= &tcpci_tcpm_check_vbus_level,
+	.check_vbus_level = &tcpci_tcpm_check_vbus_level,
 #endif
-	.select_rp_value	= &tcpci_tcpm_select_rp_value,
-	.set_cc			= &nct38xx_tcpm_set_cc,
-	.set_polarity		= &tcpci_tcpm_set_polarity,
+	.select_rp_value = &tcpci_tcpm_select_rp_value,
+	.set_cc = &nct38xx_tcpm_set_cc,
+	.set_polarity = &tcpci_tcpm_set_polarity,
 #ifdef CONFIG_USB_PD_DECODE_SOP
-	.sop_prime_enable	= &tcpci_tcpm_sop_prime_enable,
+	.sop_prime_enable = &tcpci_tcpm_sop_prime_enable,
 #endif
-	.set_vconn		= &tcpci_tcpm_set_vconn,
-	.set_msg_header		= &tcpci_tcpm_set_msg_header,
-	.set_rx_enable		= &tcpci_tcpm_set_rx_enable,
-	.get_message_raw	= &tcpci_tcpm_get_message_raw,
-	.transmit		= &tcpci_tcpm_transmit,
-	.tcpc_alert		= &nct38xx_tcpc_alert,
+	.set_vconn = &tcpci_tcpm_set_vconn,
+	.set_msg_header = &tcpci_tcpm_set_msg_header,
+	.set_rx_enable = &tcpci_tcpm_set_rx_enable,
+	.get_message_raw = &tcpci_tcpm_get_message_raw,
+	.transmit = &tcpci_tcpm_transmit,
+	.tcpc_alert = &nct38xx_tcpc_alert,
 #ifdef CONFIG_USB_PD_DISCHARGE_TCPC
-	.tcpc_discharge_vbus	= &tcpci_tcpc_discharge_vbus,
+	.tcpc_discharge_vbus = &tcpci_tcpc_discharge_vbus,
 #endif
 	.tcpc_enable_auto_discharge_disconnect =
-				  &tcpci_tcpc_enable_auto_discharge_disconnect,
-	.debug_accessory	= &tcpci_tcpc_debug_accessory,
+		&tcpci_tcpc_enable_auto_discharge_disconnect,
+	.debug_accessory = &tcpci_tcpc_debug_accessory,
 
 #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-	.drp_toggle		= &tcpci_tcpc_drp_toggle,
+	.drp_toggle = &tcpci_tcpc_drp_toggle,
 #endif
-	.get_snk_ctrl		= &tcpci_tcpm_get_snk_ctrl,
-	.set_snk_ctrl		= &nct38xx_tcpm_set_snk_ctrl,
-	.get_src_ctrl		= &tcpci_tcpm_get_src_ctrl,
-	.set_src_ctrl		= &tcpci_tcpm_set_src_ctrl,
-	.get_chip_info		= &tcpci_get_chip_info,
+	.get_snk_ctrl = &tcpci_tcpm_get_snk_ctrl,
+	.set_snk_ctrl = &nct38xx_tcpm_set_snk_ctrl,
+	.get_src_ctrl = &tcpci_tcpm_get_src_ctrl,
+	.set_src_ctrl = &tcpci_tcpm_set_src_ctrl,
+	.get_chip_info = &tcpci_get_chip_info,
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	.enter_low_power_mode	= &tcpci_enter_low_power_mode,
+	.enter_low_power_mode = &tcpci_enter_low_power_mode,
 #endif
-	.set_bist_test_mode	= &tcpci_set_bist_test_mode,
+	.set_bist_test_mode = &tcpci_set_bist_test_mode,
+	.get_bist_test_mode = &tcpci_get_bist_test_mode,
 #ifdef CONFIG_USB_PD_FRS
-	.set_frs_enable         = &nct38xx_set_frs_enable,
+	.set_frs_enable = &nct38xx_set_frs_enable,
 #endif
-	.handle_fault		= &nct3807_handle_fault,
+	.handle_fault = &nct3807_handle_fault,
+	.hard_reset_reinit = &tcpci_hard_reset_reinit,
 };
diff --git a/driver/tcpm/nct38xx.h b/driver/tcpm/nct38xx.h
index a63a9f0808..af0747a0bd 100644
--- a/driver/tcpm/nct38xx.h
+++ b/driver/tcpm/nct38xx.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,71 +10,72 @@
 #define __CROS_EC_USB_PD_TCPM_NCT38XX_H
 
 /* Chip variant ID (Part number)  */
-#define NCT38XX_VARIANT_MASK               0x1C
-#define NCT38XX_VARIANT_3807               0x0
-#define NCT38XX_VARIANT_3808               0x2
+#define NCT38XX_VARIANT_MASK 0x1C
+#define NCT38XX_VARIANT_3807 0x0
+#define NCT38XX_VARIANT_3808 0x2
 
 /* There are two IO ports in NCT3807 */
-#define NCT38XX_NCT3807_MAX_IO_PORT        2
+#define NCT38XX_NCT3807_MAX_IO_PORT 2
 /* There is only one IO port in NCT3808 */
-#define NCT38XX_NCT3808_MAX_IO_PORT        1
+#define NCT38XX_NCT3808_MAX_IO_PORT 1
 
-#define NCT38XX_SUPPORT_GPIO_FLAGS (GPIO_OPEN_DRAIN | GPIO_INPUT | \
-		GPIO_OUTPUT | GPIO_LOW | GPIO_HIGH | GPIO_INT_F_RISING | \
-		GPIO_INT_F_FALLING | GPIO_INT_F_HIGH | GPIO_INT_F_LOW)
+#define NCT38XX_SUPPORT_GPIO_FLAGS                                           \
+	(GPIO_OPEN_DRAIN | GPIO_INPUT | GPIO_OUTPUT | GPIO_LOW | GPIO_HIGH | \
+	 GPIO_INT_F_RISING | GPIO_INT_F_FALLING | GPIO_INT_F_HIGH |          \
+	 GPIO_INT_F_LOW)
 
 /* I2C interface */
-#define NCT38XX_I2C_ADDR1_1_FLAGS          0x70
-#define NCT38XX_I2C_ADDR1_2_FLAGS          0x71
-#define NCT38XX_I2C_ADDR1_3_FLAGS          0x72
-#define NCT38XX_I2C_ADDR1_4_FLAGS          0x73
+#define NCT38XX_I2C_ADDR1_1_FLAGS 0x70
+#define NCT38XX_I2C_ADDR1_2_FLAGS 0x71
+#define NCT38XX_I2C_ADDR1_3_FLAGS 0x72
+#define NCT38XX_I2C_ADDR1_4_FLAGS 0x73
 
-#define NCT38XX_I2C_ADDR2_1_FLAGS          0x74
-#define NCT38XX_I2C_ADDR2_2_FLAGS          0x75
-#define NCT38XX_I2C_ADDR2_3_FLAGS          0x76
-#define NCT38XX_I2C_ADDR2_4_FLAGS          0x77
+#define NCT38XX_I2C_ADDR2_1_FLAGS 0x74
+#define NCT38XX_I2C_ADDR2_2_FLAGS 0x75
+#define NCT38XX_I2C_ADDR2_3_FLAGS 0x76
+#define NCT38XX_I2C_ADDR2_4_FLAGS 0x77
 
-#define NCT38XX_REG_VENDOR_ID_L            0x00
-#define NCT38XX_REG_VENDOR_ID_H            0x01
-#define NCT38XX_VENDOR_ID                  0x0416
+#define NCT38XX_REG_VENDOR_ID_L 0x00
+#define NCT38XX_REG_VENDOR_ID_H 0x01
+#define NCT38XX_VENDOR_ID 0x0416
 
-#define NCT38XX_PRODUCT_ID                 0xC301
+#define NCT38XX_PRODUCT_ID 0xC301
 
 /*
  * Default value from the ROLE_CTRL register on first boot will depend on
  * whether we're coming from a dead battery state.
  */
-#define NCT38XX_ROLE_CTRL_DEAD_BATTERY	   0x0A
-#define NCT39XX_ROLE_CTRL_GOOD_BATTERY	   0x4A
-
-#define NCT38XX_REG_GPIO_DATA_IN(n)       (0xC0 + ((n) * 8))
-#define NCT38XX_REG_GPIO_DATA_OUT(n)      (0xC1 + ((n) * 8))
-#define NCT38XX_REG_GPIO_DIR(n)           (0xC2 + ((n) * 8))
-#define NCT38XX_REG_GPIO_OD_SEL(n)        (0xC3 + ((n) * 8))
-#define NCT38XX_REG_GPIO_ALERT_RISE(n)    (0xC4 + ((n) * 8))
-#define NCT38XX_REG_GPIO_ALERT_FALL(n)    (0xC5 + ((n) * 8))
-#define NCT38XX_REG_GPIO_ALERT_LEVEL(n)   (0xC6 + ((n) * 8))
-#define NCT38XX_REG_GPIO_ALERT_MASK(n)    (0xC7 + ((n) * 8))
-#define NCT38XX_REG_MUX_CONTROL            0xD0
-#define NCT38XX_REG_GPIO_ALERT_STAT(n)    (0xD4 + (n))
+#define NCT38XX_ROLE_CTRL_DEAD_BATTERY 0x0A
+#define NCT39XX_ROLE_CTRL_GOOD_BATTERY 0x4A
+
+#define NCT38XX_REG_GPIO_DATA_IN(n) (0xC0 + ((n)*8))
+#define NCT38XX_REG_GPIO_DATA_OUT(n) (0xC1 + ((n)*8))
+#define NCT38XX_REG_GPIO_DIR(n) (0xC2 + ((n)*8))
+#define NCT38XX_REG_GPIO_OD_SEL(n) (0xC3 + ((n)*8))
+#define NCT38XX_REG_GPIO_ALERT_RISE(n) (0xC4 + ((n)*8))
+#define NCT38XX_REG_GPIO_ALERT_FALL(n) (0xC5 + ((n)*8))
+#define NCT38XX_REG_GPIO_ALERT_LEVEL(n) (0xC6 + ((n)*8))
+#define NCT38XX_REG_GPIO_ALERT_MASK(n) (0xC7 + ((n)*8))
+#define NCT38XX_REG_MUX_CONTROL 0xD0
+#define NCT38XX_REG_GPIO_ALERT_STAT(n) (0xD4 + (n))
 
 /* NCT3808 only supports GPIO 2/3/4/6/7 */
-#define NCT38XXX_3808_VALID_GPIO_MASK            0xDC
+#define NCT38XXX_3808_VALID_GPIO_MASK 0xDC
 
-#define NCT38XX_REG_CTRL_OUT_EN            0xD2
-#define NCT38XX_REG_CTRL_OUT_EN_SRCEN      (1 << 0)
-#define NCT38XX_REG_CTRL_OUT_EN_FASTEN     (1 << 1)
-#define NCT38XX_REG_CTRL_OUT_EN_SNKEN      (1 << 2)
-#define NCT38XX_REG_CTRL_OUT_EN_CONNDIREN  (1 << 6)
+#define NCT38XX_REG_CTRL_OUT_EN 0xD2
+#define NCT38XX_REG_CTRL_OUT_EN_SRCEN (1 << 0)
+#define NCT38XX_REG_CTRL_OUT_EN_FASTEN (1 << 1)
+#define NCT38XX_REG_CTRL_OUT_EN_SNKEN (1 << 2)
+#define NCT38XX_REG_CTRL_OUT_EN_CONNDIREN (1 << 6)
 
-#define NCT38XX_REG_VBC_FAULT_CTL          0xD7
-#define NCT38XX_REG_VBC_FAULT_CTL_VC_OCP_EN	(1 << 0)
-#define NCT38XX_REG_VBC_FAULT_CTL_VC_SCP_EN	(1 << 1)
-#define NCT38XX_REG_VBC_FAULT_CTL_FAULT_VC_OFF	(1 << 3)
-#define NCT38XX_REG_VBC_FAULT_CTL_VB_OCP_OFF	(1 << 4)
-#define NCT38XX_REG_VBC_FAULT_CTL_VC_OVP_OFF	(1 << 5)
+#define NCT38XX_REG_VBC_FAULT_CTL 0xD7
+#define NCT38XX_REG_VBC_FAULT_CTL_VC_OCP_EN (1 << 0)
+#define NCT38XX_REG_VBC_FAULT_CTL_VC_SCP_EN (1 << 1)
+#define NCT38XX_REG_VBC_FAULT_CTL_FAULT_VC_OFF (1 << 3)
+#define NCT38XX_REG_VBC_FAULT_CTL_VB_OCP_OFF (1 << 4)
+#define NCT38XX_REG_VBC_FAULT_CTL_VC_OVP_OFF (1 << 5)
 
-#define NCT38XX_RESET_HOLD_DELAY_MS	1
+#define NCT38XX_RESET_HOLD_DELAY_MS 1
 
 /*
  * From the datasheet (section 4.4.2 Reset Timing) as following:
@@ -85,8 +86,8 @@
  * NCT3808 (dual port)   |   x   |   3ms |
  * ----------------------+-------+-------+
  */
-#define NCT3807_RESET_POST_DELAY_MS	2
-#define NCT3808_RESET_POST_DELAY_MS	3
+#define NCT3807_RESET_POST_DELAY_MS 2
+#define NCT3808_RESET_POST_DELAY_MS 3
 
 extern const struct tcpm_drv nct38xx_tcpm_drv;
 
diff --git a/driver/tcpm/ps8xxx.c b/driver/tcpm/ps8xxx.c
index 212a7f10dd..9eb3b40b2b 100644
--- a/driver/tcpm/ps8xxx.c
+++ b/driver/tcpm/ps8xxx.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,6 +8,7 @@
  *
  * Supported TCPCs:
  * - PS8705
+ * - PS8745
  * - PS8751
  * - PS8755
  * - PS8805
@@ -23,7 +24,8 @@
 #include "usb_mux.h"
 #include "usb_pd.h"
 
-#if !defined(CONFIG_USB_PD_TCPM_PS8705) && \
+#if !defined(CONFIG_USB_PD_TCPM_PS8705) &&     \
+	!defined(CONFIG_USB_PD_TCPM_PS8745) && \
 	!defined(CONFIG_USB_PD_TCPM_PS8751) && \
 	!defined(CONFIG_USB_PD_TCPM_PS8755) && \
 	!defined(CONFIG_USB_PD_TCPM_PS8805) && \
@@ -31,8 +33,7 @@
 #error "Unsupported PS8xxx TCPC."
 #endif
 
-#if !defined(CONFIG_USB_PD_TCPM_TCPCI) || \
-	!defined(CONFIG_USB_PD_TCPM_MUX) || \
+#if !defined(CONFIG_USB_PD_TCPM_TCPCI) || !defined(CONFIG_USB_PD_TCPM_MUX) || \
 	!defined(CONFIG_USBC_SS_MUX)
 
 #error "PS8XXX is using a standard TCPCI interface with integrated mux control"
@@ -55,10 +56,10 @@
 
 #endif /* CONFIG_USB_PD_TCPM_PS8751_CUSTOM_MUX_DRIVER */
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
-#define PS8XXX_I2C_RECOVERY_DELAY_MS	10
+#define PS8XXX_I2C_RECOVERY_DELAY_MS 10
 
 /*
  * The product_id per ports here is expected to be set in callback function -
@@ -94,7 +95,7 @@ static uint64_t hpd_deadline[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 void ps8xxx_wake_from_standby(const struct usb_mux *me);
 
-#if defined(CONFIG_USB_PD_TCPM_PS8705) || \
+#if defined(CONFIG_USB_PD_TCPM_PS8705) ||     \
 	defined(CONFIG_USB_PD_TCPM_PS8751) || \
 	defined(CONFIG_USB_PD_TCPM_PS8755) || \
 	defined(CONFIG_USB_PD_TCPM_PS8805)
@@ -122,7 +123,7 @@ static int ps8xxx_addr_dci_disable(int port, int i2c_addr, int i2c_reg)
 }
 #endif /* CONFIG_USB_PD_TCPM_PS875[15] || CONFIG_USB_PD_TCPM_PS8[78]05 */
 
-#if defined(CONFIG_USB_PD_TCPM_PS8705) || \
+#if defined(CONFIG_USB_PD_TCPM_PS8705) ||     \
 	defined(CONFIG_USB_PD_TCPM_PS8755) || \
 	defined(CONFIG_USB_PD_TCPM_PS8805)
 static int ps8705_dci_disable(int port)
@@ -166,13 +167,13 @@ static int ps8751_dci_disable(int port)
 }
 #endif /* CONFIG_USB_PD_TCPM_PS8751 */
 
-#ifdef CONFIG_USB_PD_TCPM_PS8815
+#if defined(CONFIG_USB_PD_TCPM_PS8815) || defined(CONFIG_USB_PD_TCPM_PS8745)
 static int ps8815_dci_disable(int port)
 {
-	/* DCI is disabled on the ps8815 */
+	/* DCI is disabled on the ps8815 and ps8745 */
 	return EC_SUCCESS;
 }
-#endif /* CONFIG_USB_PD_TCPM_PS8815 */
+#endif /* CONFIG_USB_PD_TCPM_PS8815 || CONFIG_USB_PD_TCPM_PS8745 */
 
 #ifdef CONFIG_USB_PD_TCPM_PS8805
 static int ps8805_gpio_mask[] = {
@@ -191,8 +192,8 @@ int ps8805_gpio_set_level(int port, enum ps8805_gpio signal, int level)
 		return EC_ERROR_INVAL;
 
 	rv = i2c_read8(tcpc_config[port].i2c_info.port,
-		       PS8805_VENDOR_DEFINED_I2C_ADDR,
-		       PS8805_REG_GPIO_CONTROL, &regval);
+		       PS8805_VENDOR_DEFINED_I2C_ADDR, PS8805_REG_GPIO_CONTROL,
+		       &regval);
 	if (rv)
 		return rv;
 
@@ -203,8 +204,8 @@ int ps8805_gpio_set_level(int port, enum ps8805_gpio signal, int level)
 		regval &= ~mask;
 
 	return i2c_write8(tcpc_config[port].i2c_info.port,
-		       PS8805_VENDOR_DEFINED_I2C_ADDR,
-		       PS8805_REG_GPIO_CONTROL, regval);
+			  PS8805_VENDOR_DEFINED_I2C_ADDR,
+			  PS8805_REG_GPIO_CONTROL, regval);
 }
 
 int ps8805_gpio_get_level(int port, enum ps8805_gpio signal, int *level)
@@ -216,8 +217,8 @@ int ps8805_gpio_get_level(int port, enum ps8805_gpio signal, int *level)
 		return EC_ERROR_INVAL;
 
 	rv = i2c_read8(tcpc_config[port].i2c_info.port,
-		       PS8805_VENDOR_DEFINED_I2C_ADDR,
-		       PS8805_REG_GPIO_CONTROL, &regval);
+		       PS8805_VENDOR_DEFINED_I2C_ADDR, PS8805_REG_GPIO_CONTROL,
+		       &regval);
 	if (rv)
 		return rv;
 	*level = !!(regval & ps8805_gpio_mask[signal]);
@@ -245,49 +246,42 @@ struct ps8xxx_variant_map {
  */
 static struct ps8xxx_variant_map variant_map[] = {
 #ifdef CONFIG_USB_PD_TCPM_PS8705
-	{
-		PS8705_PRODUCT_ID,
-		ps8705_dci_disable,
-		{
-		 [REG_FW_VER] = 0x82,
-		}
-	},
+	{ PS8705_PRODUCT_ID,
+	  ps8705_dci_disable,
+	  {
+		  [REG_FW_VER] = 0x82,
+	  } },
+#endif
+#ifdef CONFIG_USB_PD_TCPM_PS8745
+	{ PS8745_PRODUCT_ID, ps8815_dci_disable, { [REG_FW_VER] = 0x82 } },
 #endif
 #ifdef CONFIG_USB_PD_TCPM_PS8751
-	{
-		PS8751_PRODUCT_ID,
-		ps8751_dci_disable,
-		{
-			[REG_FW_VER] = 0x90,
-		}
-	},
+	{ PS8751_PRODUCT_ID,
+	  ps8751_dci_disable,
+	  {
+		  [REG_FW_VER] = 0x90,
+	  } },
 #endif
 #ifdef CONFIG_USB_PD_TCPM_PS8755
-	{
-		PS8755_PRODUCT_ID,
-		ps8705_dci_disable,
-		{
-			[REG_FW_VER] = 0x82,
-		}
-	},
+	{ PS8755_PRODUCT_ID,
+	  ps8705_dci_disable,
+	  {
+		  [REG_FW_VER] = 0x82,
+	  } },
 #endif
 #ifdef CONFIG_USB_PD_TCPM_PS8805
-	{
-		PS8805_PRODUCT_ID,
-		ps8705_dci_disable,
-		{
-			[REG_FW_VER] = 0x82,
-		}
-	},
+	{ PS8805_PRODUCT_ID,
+	  ps8705_dci_disable,
+	  {
+		  [REG_FW_VER] = 0x82,
+	  } },
 #endif
 #ifdef CONFIG_USB_PD_TCPM_PS8815
-	{
-		PS8815_PRODUCT_ID,
-		ps8815_dci_disable,
-		{
-			[REG_FW_VER] = 0x82,
-		}
-	},
+	{ PS8815_PRODUCT_ID,
+	  ps8815_dci_disable,
+	  {
+		  [REG_FW_VER] = 0x82,
+	  } },
 #endif
 };
 
@@ -300,8 +294,7 @@ static int get_reg_by_product(const int port,
 		return INT32_MAX;
 
 	for (i = 0; i < ARRAY_SIZE(variant_map); i++) {
-		if (product_id[port] ==
-		      variant_map[i].product_id) {
+		if (product_id[port] == variant_map[i].product_id) {
 			return variant_map[i].reg_map[reg];
 		}
 	}
@@ -341,8 +334,7 @@ static int dp_set_irq(const struct usb_mux *me, int enable)
 }
 
 /* LCOV_EXCL_START */
-__overridable
-uint16_t board_get_ps8xxx_product_id(int port)
+__overridable uint16_t board_get_ps8xxx_product_id(int port)
 {
 	/* Board supporting multiple chip sources in ps8xxx.c MUST override this
 	 * function to judge the real chip source for this board. For example,
@@ -354,6 +346,8 @@ uint16_t board_get_ps8xxx_product_id(int port)
 		return 0;
 	} else if (IS_ENABLED(CONFIG_USB_PD_TCPM_PS8705)) {
 		return PS8705_PRODUCT_ID;
+	} else if (IS_ENABLED(CONFIG_USB_PD_TCPM_PS8745)) {
+		return PS8745_PRODUCT_ID;
 	} else if (IS_ENABLED(CONFIG_USB_PD_TCPM_PS8751)) {
 		return PS8751_PRODUCT_ID;
 	} else if (IS_ENABLED(CONFIG_USB_PD_TCPM_PS8755)) {
@@ -385,8 +379,7 @@ bool check_ps8755_chip(int port)
 }
 
 void ps8xxx_tcpc_update_hpd_status(const struct usb_mux *me,
-				   mux_state_t mux_state,
-				   bool *ack_required)
+				   mux_state_t mux_state, bool *ack_required)
 {
 	int port = me->usb_port;
 	int hpd_lvl = (mux_state & USB_PD_MUX_HPD_LVL) ? 1 : 0;
@@ -421,12 +414,12 @@ static int ps8xxx_tcpc_bist_mode_2(int port)
 	int rv;
 
 	/* Generate BIST for 50ms. */
-	rv = tcpc_write(port,
-		PS8XXX_REG_BIST_CONT_MODE_BYTE0, PS8751_BIST_COUNTER_BYTE0);
-	rv |= tcpc_write(port,
-		PS8XXX_REG_BIST_CONT_MODE_BYTE1, PS8751_BIST_COUNTER_BYTE1);
-	rv |= tcpc_write(port,
-		PS8XXX_REG_BIST_CONT_MODE_BYTE2, PS8751_BIST_COUNTER_BYTE2);
+	rv = tcpc_write(port, PS8XXX_REG_BIST_CONT_MODE_BYTE0,
+			PS8751_BIST_COUNTER_BYTE0);
+	rv |= tcpc_write(port, PS8XXX_REG_BIST_CONT_MODE_BYTE1,
+			 PS8751_BIST_COUNTER_BYTE1);
+	rv |= tcpc_write(port, PS8XXX_REG_BIST_CONT_MODE_BYTE2,
+			 PS8751_BIST_COUNTER_BYTE2);
 
 	/* Auto stop */
 	rv |= tcpc_write(port, PS8XXX_REG_BIST_CONT_MODE_CTR, 0);
@@ -438,7 +431,7 @@ static int ps8xxx_tcpc_bist_mode_2(int port)
 }
 
 static int ps8xxx_tcpm_transmit(int port, enum tcpci_msg_type type,
-			uint16_t header, const uint32_t *data)
+				uint16_t header, const uint32_t *data)
 {
 	if (type == TCPCI_MSG_TX_BIST_MODE_2)
 		return ps8xxx_tcpc_bist_mode_2(port);
@@ -472,7 +465,7 @@ static void ps8xxx_role_control_delay(int port)
 
 #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
 static int ps8xxx_set_role_ctrl(int port, enum tcpc_drp drp,
-	enum tcpc_rp_value rp, enum tcpc_cc_pull pull)
+				enum tcpc_rp_value rp, enum tcpc_cc_pull pull)
 {
 	int rv;
 
@@ -494,12 +487,13 @@ static int ps8xxx_tcpc_drp_toggle(int port)
 	int opposite_pull;
 
 	/*
-	 * Workaround for PS8805/PS8815, which can't restart Connection
+	 * Workaround for PS8805/PS8815/PS8745, which can't restart Connection
 	 * Detection if the partner already presents pull. Now starts with
 	 * the opposite pull. Check b/149570002.
 	 */
 	if (product_id[port] == PS8805_PRODUCT_ID ||
-	    product_id[port] == PS8815_PRODUCT_ID) {
+	    product_id[port] == PS8815_PRODUCT_ID ||
+	    product_id[port] == PS8745_PRODUCT_ID) {
 		if (ps8815_disable_rp_detect[port]) {
 			CPRINTS("TCPC%d: rearm Rp disable detect on connect",
 				port);
@@ -518,7 +512,7 @@ static int ps8xxx_tcpc_drp_toggle(int port)
 
 		/* Set auto drp toggle, starting with the opposite pull */
 		rv |= ps8xxx_set_role_ctrl(port, TYPEC_DRP, TYPEC_RP_USB,
-			opposite_pull);
+					   opposite_pull);
 
 		/* Set Look4Connection command */
 		rv |= tcpc_write(port, TCPC_REG_COMMAND,
@@ -532,19 +526,26 @@ static int ps8xxx_tcpc_drp_toggle(int port)
 #endif
 
 #ifdef CONFIG_USB_PD_TCPM_PS8805_FORCE_DID
-static int ps8805_make_device_id(int port, int *id)
+static int ps8805_make_device_id(int port, int *id, int live)
 {
+	static int cached_chip_revision[CONFIG_USB_PD_PORT_MAX_COUNT];
+	static bool cache_valid[CONFIG_USB_PD_PORT_MAX_COUNT];
 	int p0_addr;
 	int val;
 	int status;
 
-	p0_addr = PS8751_P3_TO_P0_FLAGS(tcpc_config[port].i2c_info.addr_flags);
+	if (live || !cache_valid[port]) {
+		p0_addr = PS8751_P3_TO_P0_FLAGS(
+			tcpc_config[port].i2c_info.addr_flags);
+		status = tcpc_addr_read(port, p0_addr,
+					PS8805_P0_REG_CHIP_REVISION, &val);
+		if (status != EC_SUCCESS)
+			return status;
+		cached_chip_revision[port] = val;
+		cache_valid[port] = true;
+	}
 
-	status = tcpc_addr_read(port, p0_addr, PS8805_P0_REG_CHIP_REVISION,
-				&val);
-	if (status != EC_SUCCESS)
-		return status;
-	switch (val & 0xF0) {
+	switch (cached_chip_revision[port] & 0xF0) {
 	case 0x00: /* A2 chip */
 		*id = 1;
 		break;
@@ -570,21 +571,27 @@ static int ps8805_make_device_id(int port, int *id)
  * The ps8815 A2 reports device ID 0x0001 instead of 0x0003 when the
  * firmware is bad (mis-programmed).
  */
-static int ps8815_make_device_id(int port, int *id)
+static int ps8815_make_device_id(int port, int *id, int live)
 {
+	static int cached_hw_revision[CONFIG_USB_PD_PORT_MAX_COUNT];
+	static bool cache_valid[CONFIG_USB_PD_PORT_MAX_COUNT];
 	int p1_addr;
 	int val;
 	int status;
 
-	/* P1 registers are always accessible on PS8815 */
-	p1_addr = PS8751_P3_TO_P1_FLAGS(tcpc_config[port].i2c_info.addr_flags);
-
-	status = tcpc_addr_read16(port, p1_addr, PS8815_P1_REG_HW_REVISION,
-				  &val);
-	if (status != EC_SUCCESS)
-		return status;
+	if (live || !cache_valid[port]) {
+		/* P1 registers are always accessible on PS8815 */
+		p1_addr = PS8751_P3_TO_P1_FLAGS(
+			tcpc_config[port].i2c_info.addr_flags);
+		status = tcpc_addr_read16(port, p1_addr,
+					  PS8815_P1_REG_HW_REVISION, &val);
+		if (status != EC_SUCCESS)
+			return status;
+		cached_hw_revision[port] = val;
+		cache_valid[port] = true;
+	}
 
-	switch (val) {
+	switch (cached_hw_revision[port]) {
 	case 0x0a00:
 		*id = 1;
 		break;
@@ -601,6 +608,52 @@ static int ps8815_make_device_id(int port, int *id)
 }
 #endif
 
+#ifdef CONFIG_USB_PD_TCPM_PS8745_FORCE_ID
+/*
+ * Some PS8745 firmwares report the same product/device ID and chip rev as
+ * PS8815-A2. This function probes vendor-specific registers to determine
+ * whether the device is a PS8815 or PS8745 and updates the IDs pointed to by
+ * the parameters to be the correct IDs for the detected chip.
+ *
+ * See b/236761058 and the PS8xxx TCPC Family Chip Revision Guide (v0.2)
+ */
+static int ps8745_make_device_id(int port, uint16_t *pid, uint16_t *did,
+				 int live)
+{
+	static int cached_reg_id[CONFIG_USB_PD_PORT_MAX_COUNT];
+	static bool cache_valid[CONFIG_USB_PD_PORT_MAX_COUNT];
+	int status;
+	int val;
+
+	if (live || !cache_valid[port]) {
+		status = tcpc_addr_read(
+			port,
+			PS8751_P3_TO_P0_FLAGS(
+				tcpc_config[port].i2c_info.addr_flags),
+			PS8815_P0_REG_ID, &val);
+		if (status != EC_SUCCESS)
+			return status;
+		cached_reg_id[port] = val;
+		cache_valid[port] = true;
+	}
+
+	if (*pid == PS8815_PRODUCT_ID && (cached_reg_id[port] & BIT(1)) != 0) {
+		/* PS8815 with this bit set is actually PS8745 */
+		*pid = PS8745_PRODUCT_ID;
+	}
+
+	if (*pid == PS8745_PRODUCT_ID && *did == 0x0003) {
+		/*
+		 * Some versions report the correct product ID but the
+		 * device ID is still for PS8815-A2.
+		 */
+		*did = 0x0006;
+	}
+
+	return EC_SUCCESS;
+}
+#endif
+
 /*
  * The ps8815 can take up to 50ms (FW_INIT_DELAY_MS) to fully wake up
  * from sleep/low power mode - specially when it contains an application
@@ -645,8 +698,10 @@ static int ps8xxx_lpm_recovery_delay(int port)
 }
 
 static int ps8xxx_get_chip_info(int port, int live,
-			struct ec_response_pd_chip_info_v1 *chip_info)
+				struct ec_response_pd_chip_info_v1 *chip_info)
 {
+	static int cached_fw_version[CONFIG_USB_PD_PORT_MAX_COUNT];
+	static bool cache_valid[CONFIG_USB_PD_PORT_MAX_COUNT];
 	int val;
 	int reg;
 	int rv = tcpci_get_chip_info(port, live, chip_info);
@@ -668,10 +723,24 @@ static int ps8xxx_get_chip_info(int port, int live,
 		chip_info->product_id = product_id[port];
 	}
 
+#ifdef CONFIG_USB_PD_TCPM_PS8745_FORCE_ID
+	/* device ID 3 is PS8815 and might be misreported */
+	if (chip_info->product_id == PS8815_PRODUCT_ID ||
+	    chip_info->device_id == 0x0003) {
+		uint16_t pid = chip_info->product_id;
+		uint16_t did = chip_info->device_id;
+
+		rv = ps8745_make_device_id(port, &pid, &did, live);
+		chip_info->product_id = pid;
+		chip_info->device_id = did;
+		if (rv != EC_SUCCESS)
+			return rv;
+	}
+#endif
 #ifdef CONFIG_USB_PD_TCPM_PS8805_FORCE_DID
 	if (chip_info->product_id == PS8805_PRODUCT_ID &&
 	    chip_info->device_id == 0x0001) {
-		rv = ps8805_make_device_id(port, &val);
+		rv = ps8805_make_device_id(port, &val, live);
 		if (rv != EC_SUCCESS)
 			return rv;
 		chip_info->device_id = val;
@@ -680,24 +749,28 @@ static int ps8xxx_get_chip_info(int port, int live,
 #ifdef CONFIG_USB_PD_TCPM_PS8815_FORCE_DID
 	if (chip_info->product_id == PS8815_PRODUCT_ID &&
 	    chip_info->device_id == 0x0001) {
-		rv = ps8815_make_device_id(port, &val);
+		rv = ps8815_make_device_id(port, &val, live);
 		if (rv != EC_SUCCESS)
 			return rv;
 		chip_info->device_id = val;
 	}
 #endif
-	reg = get_reg_by_product(port, REG_FW_VER);
-	rv = tcpc_read(port, reg, &val);
-	if (rv != EC_SUCCESS)
-		return rv;
 
-	chip_info->fw_version_number = val;
+	if (live || !cache_valid[port]) {
+		reg = get_reg_by_product(port, REG_FW_VER);
+		rv = tcpc_read(port, reg, &val);
+		if (rv != EC_SUCCESS)
+			return rv;
+		cached_fw_version[port] = val;
+		cache_valid[port] = true;
+	}
+	chip_info->fw_version_number = cached_fw_version[port];
 
 	/* Treat unexpected values as error (FW not initiated from reset) */
-	if (live && (
-	    chip_info->vendor_id != PS8XXX_VENDOR_ID ||
-	    chip_info->product_id != board_get_ps8xxx_product_id(port) ||
-	    chip_info->fw_version_number == 0))
+	if (live &&
+	    (chip_info->vendor_id != PS8XXX_VENDOR_ID ||
+	     chip_info->product_id != board_get_ps8xxx_product_id(port) ||
+	     chip_info->fw_version_number == 0))
 		return EC_ERROR_UNKNOWN;
 
 #if defined(CONFIG_USB_PD_TCPM_PS8751) && \
@@ -716,12 +789,13 @@ static int ps8xxx_get_chip_info(int port, int live,
 static int ps8xxx_enter_low_power_mode(int port)
 {
 	/*
-	 * PS8751/PS8815 has the auto sleep function that enters
+	 * PS8751/PS8815/PS8745 has the auto sleep function that enters
 	 * low power mode on its own in ~2 seconds. Other chips
 	 * don't have it. Stub it out for PS8751/PS8815.
 	 */
 	if (product_id[port] == PS8751_PRODUCT_ID ||
-		product_id[port] == PS8815_PRODUCT_ID)
+	    product_id[port] == PS8815_PRODUCT_ID ||
+	    product_id[port] == PS8745_PRODUCT_ID)
 		return EC_SUCCESS;
 
 	return tcpci_enter_low_power_mode(port);
@@ -736,8 +810,7 @@ __maybe_unused static int ps8815_tcpc_fast_role_swap_enable(int port,
 	if (!tcpm_tcpc_has_frs_control(port))
 		return EC_SUCCESS;
 
-	status = tcpc_update8(port,
-			      PS8815_REG_RESERVED_F4,
+	status = tcpc_update8(port, PS8815_REG_RESERVED_F4,
 			      PS8815_REG_RESERVED_F4_FRS_EN,
 			      enable ? MASK_SET : MASK_CLR);
 	if (status != EC_SUCCESS)
@@ -816,7 +889,8 @@ __maybe_unused static int ps8815_disable_rp_detect_workaround_check(int port)
 }
 
 __overridable void board_ps8xxx_tcpc_init(int port)
-{}
+{
+}
 
 static int ps8xxx_tcpm_init(int port)
 {
@@ -837,7 +911,10 @@ static int ps8xxx_tcpm_init(int port)
 		status = ps8815_disable_rp_detect_workaround_check(port);
 		if (status != EC_SUCCESS)
 			return status;
+	}
 
+	if (IS_ENABLED(CONFIG_USB_PD_TCPM_PS8745) ||
+	    IS_ENABLED(CONFIG_USB_PD_TCPM_PS8815)) {
 		/*
 		 * NOTE(b/183127346): Enable FRS sequence:
 		 *
@@ -848,8 +925,7 @@ static int ps8xxx_tcpm_init(int port)
 		 *    set reg 0xf4.FRS_EN (drive FRS GPIO to PPC)
 		 */
 		if (tcpm_tcpc_has_frs_control(port)) {
-			status = tcpc_update8(port,
-					      PS8815_REG_RESERVED_D1,
+			status = tcpc_update8(port, PS8815_REG_RESERVED_D1,
 					      PS8815_REG_RESERVED_D1_FRS_EN,
 					      MASK_SET);
 			if (status != EC_SUCCESS)
@@ -884,7 +960,7 @@ static int ps8xxx_tcpm_init(int port)
  * delay will allow the transient to disappear.
  */
 static int ps8751_get_gcc(int port, enum tcpc_cc_voltage_status *cc1,
-			 enum tcpc_cc_voltage_status *cc2)
+			  enum tcpc_cc_voltage_status *cc2)
 {
 	int rv;
 	int status;
@@ -932,7 +1008,7 @@ static int ps8xxx_tcpm_set_cc(int port, int pull)
 }
 
 static int ps8xxx_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-			 enum tcpc_cc_voltage_status *cc2)
+			      enum tcpc_cc_voltage_status *cc2)
 {
 #ifdef CONFIG_USB_PD_TCPM_PS8751
 	if (product_id[port] == PS8751_PRODUCT_ID)
@@ -957,39 +1033,41 @@ static int ps8xxx_tcpm_set_vconn(int port, int enable)
 }
 
 const struct tcpm_drv ps8xxx_tcpm_drv = {
-	.init			= ps8xxx_tcpm_init,
-	.release		= ps8xxx_tcpm_release,
-	.get_cc			= ps8xxx_tcpm_get_cc,
+	.init = ps8xxx_tcpm_init,
+	.release = ps8xxx_tcpm_release,
+	.get_cc = ps8xxx_tcpm_get_cc,
 #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	.check_vbus_level	= tcpci_tcpm_check_vbus_level,
+	.check_vbus_level = tcpci_tcpm_check_vbus_level,
 #endif
-	.select_rp_value	= tcpci_tcpm_select_rp_value,
-	.set_cc			= ps8xxx_tcpm_set_cc,
-	.set_polarity		= tcpci_tcpm_set_polarity,
+	.select_rp_value = tcpci_tcpm_select_rp_value,
+	.set_cc = ps8xxx_tcpm_set_cc,
+	.set_polarity = tcpci_tcpm_set_polarity,
 #ifdef CONFIG_USB_PD_DECODE_SOP
-	.sop_prime_enable	= tcpci_tcpm_sop_prime_enable,
+	.sop_prime_enable = tcpci_tcpm_sop_prime_enable,
 #endif
-	.set_vconn		= ps8xxx_tcpm_set_vconn,
-	.set_msg_header		= tcpci_tcpm_set_msg_header,
-	.set_rx_enable		= tcpci_tcpm_set_rx_enable,
-	.get_message_raw	= tcpci_tcpm_get_message_raw,
-	.transmit		= ps8xxx_tcpm_transmit,
-	.tcpc_alert		= tcpci_tcpc_alert,
+	.set_vconn = ps8xxx_tcpm_set_vconn,
+	.set_msg_header = tcpci_tcpm_set_msg_header,
+	.set_rx_enable = tcpci_tcpm_set_rx_enable,
+	.get_message_raw = tcpci_tcpm_get_message_raw,
+	.transmit = ps8xxx_tcpm_transmit,
+	.tcpc_alert = tcpci_tcpc_alert,
 #ifdef CONFIG_USB_PD_DISCHARGE_TCPC
-	.tcpc_discharge_vbus	= tcpci_tcpc_discharge_vbus,
+	.tcpc_discharge_vbus = tcpci_tcpc_discharge_vbus,
 #endif
 #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-	.drp_toggle		= ps8xxx_tcpc_drp_toggle,
+	.drp_toggle = ps8xxx_tcpc_drp_toggle,
 #endif
-	.get_chip_info		= ps8xxx_get_chip_info,
-	.set_snk_ctrl		= tcpci_tcpm_set_snk_ctrl,
-	.set_src_ctrl		= tcpci_tcpm_set_src_ctrl,
+	.get_chip_info = ps8xxx_get_chip_info,
+	.set_snk_ctrl = tcpci_tcpm_set_snk_ctrl,
+	.set_src_ctrl = tcpci_tcpm_set_src_ctrl,
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	.enter_low_power_mode	= ps8xxx_enter_low_power_mode,
+	.enter_low_power_mode = ps8xxx_enter_low_power_mode,
 #endif
-	.set_bist_test_mode	= tcpci_set_bist_test_mode,
-#if defined(CONFIG_USB_PD_FRS) && defined(CONFIG_USB_PD_TCPM_PS8815)
-	.set_frs_enable         = ps8815_tcpc_fast_role_swap_enable,
+	.set_bist_test_mode = tcpci_set_bist_test_mode,
+	.get_bist_test_mode = &tcpci_get_bist_test_mode,
+#if defined(CONFIG_USB_PD_FRS) && (defined(CONFIG_USB_PD_TCPM_PS8815) || \
+				   defined(CONFIG_USB_PD_TCPM_PS8745))
+	.set_frs_enable = ps8815_tcpc_fast_role_swap_enable,
 #endif
 };
 
@@ -1039,6 +1117,10 @@ void ps8xxx_wake_from_standby(const struct usb_mux *me)
 static int ps8xxx_mux_set(const struct usb_mux *me, mux_state_t mux_state,
 			  bool *ack_required)
 {
+	/* This driver treats safe mode as none */
+	if (mux_state == USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
+
 	if (product_id[me->usb_port] == PS8751_PRODUCT_ID &&
 	    me->flags & USB_MUX_FLAG_NOT_TCPC) {
 		ps8xxx_wake_from_standby(me);
@@ -1049,11 +1131,11 @@ static int ps8xxx_mux_set(const struct usb_mux *me, mux_state_t mux_state,
 		 * setting mux breaks SuperSpeed connection.
 		 */
 		if (mux_state != USB_PD_MUX_NONE)
-			RETURN_ERROR(mux_write(me, TCPC_REG_ROLE_CTRL,
-					TCPC_REG_ROLE_CTRL_SET(TYPEC_NO_DRP,
-							       TYPEC_RP_USB,
-							       TYPEC_CC_RD,
-							       TYPEC_CC_RD)));
+			RETURN_ERROR(
+				mux_write(me, TCPC_REG_ROLE_CTRL,
+					  TCPC_REG_ROLE_CTRL_SET(
+						  TYPEC_NO_DRP, TYPEC_RP_USB,
+						  TYPEC_CC_RD, TYPEC_CC_RD)));
 	}
 
 	return tcpci_tcpm_mux_set(me, mux_state, ack_required);
diff --git a/driver/tcpm/ps8xxx.h b/driver/tcpm/ps8xxx.h
index eeddd22640..7d873abc85 100644
--- a/driver/tcpm/ps8xxx.h
+++ b/driver/tcpm/ps8xxx.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,67 +11,67 @@
 #ifndef __CROS_EC_USB_PD_TCPM_PS8XXX_H
 #define __CROS_EC_USB_PD_TCPM_PS8XXX_H
 
-#define PS8751_P3_TO_P0_FLAGS(p3_flags)	((p3_flags) - 3)
-#define PS8751_P3_TO_P1_FLAGS(p3_flags)	((p3_flags) - 2)
+#define PS8751_P3_TO_P0_FLAGS(p3_flags) ((p3_flags)-3)
+#define PS8751_P3_TO_P1_FLAGS(p3_flags) ((p3_flags)-2)
 
-#define PS8751_BIST_TIMER_FREQ  15000000
-#define PS8751_BIST_DELAY_MS    50
+#define PS8751_BIST_TIMER_FREQ 15000000
+#define PS8751_BIST_DELAY_MS 50
 
-#define PS8751_BIST_COUNTER (PS8751_BIST_TIMER_FREQ / MSEC \
-				* PS8751_BIST_DELAY_MS)
+#define PS8751_BIST_COUNTER \
+	(PS8751_BIST_TIMER_FREQ / MSEC * PS8751_BIST_DELAY_MS)
 
 #define PS8751_BIST_COUNTER_BYTE0 (PS8751_BIST_COUNTER & 0xff)
 #define PS8751_BIST_COUNTER_BYTE1 ((PS8751_BIST_COUNTER >> 8) & 0xff)
 #define PS8751_BIST_COUNTER_BYTE2 ((PS8751_BIST_COUNTER >> 16) & 0xff)
 
-#define PS8XXX_REG_RP_DETECT_CONTROL            0x9B
-#define RP_DETECT_DISABLE			0x30
+#define PS8XXX_REG_RP_DETECT_CONTROL 0x9B
+#define RP_DETECT_DISABLE 0x30
 
-#define PS8XXX_REG_I2C_DEBUGGING_ENABLE         0xA0
-#define PS8XXX_REG_I2C_DEBUGGING_ENABLE_ON      0x30
-#define PS8XXX_REG_I2C_DEBUGGING_ENABLE_OFF     0x31    /* default */
-#define PS8XXX_REG_BIST_CONT_MODE_BYTE0         0xBC
-#define PS8XXX_REG_BIST_CONT_MODE_BYTE1         0xBD
-#define PS8XXX_REG_BIST_CONT_MODE_BYTE2         0xBE
-#define PS8XXX_REG_BIST_CONT_MODE_CTR           0xBF
-#define PS8XXX_REG_DET_CTRL0                    0x08
+#define PS8XXX_REG_I2C_DEBUGGING_ENABLE 0xA0
+#define PS8XXX_REG_I2C_DEBUGGING_ENABLE_ON 0x30
+#define PS8XXX_REG_I2C_DEBUGGING_ENABLE_OFF 0x31 /* default */
+#define PS8XXX_REG_BIST_CONT_MODE_BYTE0 0xBC
+#define PS8XXX_REG_BIST_CONT_MODE_BYTE1 0xBD
+#define PS8XXX_REG_BIST_CONT_MODE_BYTE2 0xBE
+#define PS8XXX_REG_BIST_CONT_MODE_CTR 0xBF
+#define PS8XXX_REG_DET_CTRL0 0x08
 
-#define PS8XXX_REG_MUX_USB_DCI_CFG_MODE_MASK    0xC0
-#define PS8XXX_REG_MUX_USB_DCI_CFG_MODE_OFF     0x80
+#define PS8XXX_REG_MUX_USB_DCI_CFG_MODE_MASK 0xC0
+#define PS8XXX_REG_MUX_USB_DCI_CFG_MODE_OFF 0x80
 
-#define MUX_IN_HPD_ASSERTION_REG                0xD0
-#define IN_HPD  BIT(0)
+#define MUX_IN_HPD_ASSERTION_REG 0xD0
+#define IN_HPD BIT(0)
 #define HPD_IRQ BIT(1)
 
-#define PS8XXX_P1_REG_MUX_USB_DCI_CFG           0x4B
+#define PS8XXX_P1_REG_MUX_USB_DCI_CFG 0x4B
 
-#define PS8755_P0_REG_SM			0x06
-#define PS8755_P0_REG_SM_VALUE			0x80
+#define PS8755_P0_REG_SM 0x06
+#define PS8755_P0_REG_SM_VALUE 0x80
 
 #if defined(CONFIG_USB_PD_TCPM_PS8751)
 /* Vendor defined registers */
-#define PS8XXX_REG_VENDOR_ID_L                  0x00
-#define PS8XXX_REG_VENDOR_ID_H                  0x01
-#define PS8XXX_REG_MUX_DP_EQ_CONFIGURATION      0xD3
-#define PS8XXX_REG_MUX_DP_OUTPUT_CONFIGURATION  0xD4
-#define PS8XXX_REG_MUX_USB_C2SS_EQ              0xE7
-#define PS8XXX_REG_MUX_USB_C2SS_HS_THRESHOLD    0xE8
-#define PS8751_REG_MUX_USB_DCI_CFG              0xED
+#define PS8XXX_REG_VENDOR_ID_L 0x00
+#define PS8XXX_REG_VENDOR_ID_H 0x01
+#define PS8XXX_REG_MUX_DP_EQ_CONFIGURATION 0xD3
+#define PS8XXX_REG_MUX_DP_OUTPUT_CONFIGURATION 0xD4
+#define PS8XXX_REG_MUX_USB_C2SS_EQ 0xE7
+#define PS8XXX_REG_MUX_USB_C2SS_HS_THRESHOLD 0xE8
+#define PS8751_REG_MUX_USB_DCI_CFG 0xED
 #endif
 
 /* Vendor defined registers */
-#define PS8815_P1_REG_HW_REVISION		0xF0
+#define PS8815_P1_REG_HW_REVISION 0xF0
 
 /* Vendor defined registers */
-#define PS8815_REG_APTX_EQ_AT_10G		0x20
-#define PS8815_REG_RX_EQ_AT_10G			0x22
-#define PS8815_REG_APTX_EQ_AT_5G		0x24
-#define PS8815_REG_RX_EQ_AT_5G			0x26
+#define PS8815_REG_APTX_EQ_AT_10G 0x20
+#define PS8815_REG_RX_EQ_AT_10G 0x22
+#define PS8815_REG_APTX_EQ_AT_5G 0x24
+#define PS8815_REG_RX_EQ_AT_5G 0x26
 
-#define PS8815_REG_RESERVED_D1			0xD1
-#define PS8815_REG_RESERVED_D1_FRS_EN		BIT(7)
-#define PS8815_REG_RESERVED_F4			0xF4
-#define PS8815_REG_RESERVED_F4_FRS_EN		BIT(6)
+#define PS8815_REG_RESERVED_D1 0xD1
+#define PS8815_REG_RESERVED_D1_FRS_EN BIT(7)
+#define PS8815_REG_RESERVED_F4 0xF4
+#define PS8815_REG_RESERVED_F4_FRS_EN BIT(6)
 
 /*
  * Below register is defined from Parade PS8815 Register Table,
@@ -79,37 +79,42 @@
  */
 
 /* Displayport related settings */
-#define PS8815_REG_DP_EQ_SETTING		0xF8
-#define PS8815_AUTO_EQ_DISABLE			BIT(7)
-#define PS8815_DPEQ_LOSS_UP_21DB		0x09
-#define PS8815_DPEQ_LOSS_UP_20DB		0x08
-#define PS8815_DPEQ_LOSS_UP_19DB		0x07
-#define PS8815_DPEQ_LOSS_UP_18DB		0x06
-#define PS8815_DPEQ_LOSS_UP_17DB		0x05
-#define PS8815_DPEQ_LOSS_UP_16DB		0x04
-#define PS8815_DPEQ_LOSS_UP_13DB		0x03
-#define PS8815_DPEQ_LOSS_UP_12DB		0x02
-#define PS8815_DPEQ_LOSS_UP_10DB		0x01
-#define PS8815_DPEQ_LOSS_UP_9DB			0x00
-#define PS8815_REG_DP_EQ_COMP_SHIFT		3
-#define PS8815_AUX_INTERCEPTION_DISABLE		BIT(1)
+#define PS8815_REG_DP_EQ_SETTING 0xF8
+#define PS8815_AUTO_EQ_DISABLE BIT(7)
+#define PS8815_DPEQ_LOSS_UP_21DB 0x09
+#define PS8815_DPEQ_LOSS_UP_20DB 0x08
+#define PS8815_DPEQ_LOSS_UP_19DB 0x07
+#define PS8815_DPEQ_LOSS_UP_18DB 0x06
+#define PS8815_DPEQ_LOSS_UP_17DB 0x05
+#define PS8815_DPEQ_LOSS_UP_16DB 0x04
+#define PS8815_DPEQ_LOSS_UP_13DB 0x03
+#define PS8815_DPEQ_LOSS_UP_12DB 0x02
+#define PS8815_DPEQ_LOSS_UP_10DB 0x01
+#define PS8815_DPEQ_LOSS_UP_9DB 0x00
+#define PS8815_REG_DP_EQ_COMP_SHIFT 3
+#define PS8815_AUX_INTERCEPTION_DISABLE BIT(1)
 
 /*
  * PS8805 register to distinguish chip revision
  * bit 7-4: 1010b is A3 chip, 0000b is A2 chip
  */
-#define PS8805_P0_REG_CHIP_REVISION		0x62
+#define PS8805_P0_REG_CHIP_REVISION 0x62
+/*
+ * PS8815 register to differentiate with PS8745: bit 1 = 0 is a PS8815-A2,
+ * 1 is a PS8745-A2.
+ */
+#define PS8815_P0_REG_ID 0x2C
 
 /*
  * PS8805 GPIO control register. Note the device I2C address of 0x1A is
  * independent of the ADDR pin on the chip, and not the same address being used
  * for TCPCI functions.
  */
-#define PS8805_VENDOR_DEFINED_I2C_ADDR		0x1A
-#define PS8805_REG_GPIO_CONTROL		0x21
-#define PS8805_REG_GPIO_0			BIT(7)
-#define PS8805_REG_GPIO_1			BIT(5)
-#define PS8805_REG_GPIO_2			BIT(6)
+#define PS8805_VENDOR_DEFINED_I2C_ADDR 0x1A
+#define PS8805_REG_GPIO_CONTROL 0x21
+#define PS8805_REG_GPIO_0 BIT(7)
+#define PS8805_REG_GPIO_1 BIT(5)
+#define PS8805_REG_GPIO_2 BIT(6)
 
 enum ps8805_gpio {
 	PS8805_GPIO_0,
diff --git a/driver/tcpm/raa489000.c b/driver/tcpm/raa489000.c
index db169f19f1..810ca29550 100644
--- a/driver/tcpm/raa489000.c
+++ b/driver/tcpm/raa489000.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -18,10 +18,10 @@
 
 #define DEFAULT_R_AC 20
 #define R_AC CONFIG_CHARGER_SENSE_RESISTOR_AC
-#define AC_CURRENT_TO_REG(CUR) ((CUR) * R_AC / DEFAULT_R_AC)
+#define AC_CURRENT_TO_REG(CUR) ((CUR)*R_AC / DEFAULT_R_AC)
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 static int dev_id[CONFIG_USB_PD_PORT_MAX_COUNT] = { -1 };
 
@@ -47,14 +47,13 @@ int raa489000_set_output_current(int port, enum tcpc_rp_value rp)
 {
 	int regval;
 	int selected_cur = rp == TYPEC_RP_3A0 ?
-				RAA489000_VBUS_CURRENT_TARGET_3A :
-				RAA489000_VBUS_CURRENT_TARGET_1_5A;
+				   RAA489000_VBUS_CURRENT_TARGET_3A :
+				   RAA489000_VBUS_CURRENT_TARGET_1_5A;
 
 	regval = AC_CURRENT_TO_REG(selected_cur) +
-				selected_cur % (DEFAULT_R_AC/R_AC);
+		 selected_cur % (DEFAULT_R_AC / R_AC);
 
-	return tcpc_write16(port, RAA489000_VBUS_CURRENT_TARGET,
-				regval);
+	return tcpc_write16(port, RAA489000_VBUS_CURRENT_TARGET, regval);
 }
 
 int raa489000_init(int port)
@@ -94,11 +93,11 @@ int raa489000_init(int port)
 	 * can get the correct voltage.
 	 */
 	i2c_port = tcpc_config[port].i2c_info.port;
-	rv = i2c_read16(i2c_port, ISL923X_ADDR_FLAGS,
-			ISL9238_REG_CONTROL3, &regval);
+	rv = i2c_read16(i2c_port, ISL923X_ADDR_FLAGS, ISL9238_REG_CONTROL3,
+			&regval);
 	regval |= RAA489000_ENABLE_ADC;
-	rv |= i2c_write16(i2c_port, ISL923X_ADDR_FLAGS,
-			ISL9238_REG_CONTROL3, regval);
+	rv |= i2c_write16(i2c_port, ISL923X_ADDR_FLAGS, ISL9238_REG_CONTROL3,
+			  regval);
 	if (rv)
 		CPRINTS("c%d: failed to enable ADCs", port);
 
@@ -108,7 +107,6 @@ int raa489000_init(int port)
 	if (rv)
 		CPRINTS("c%d: failed to enable vbus detect cmd", port);
 
-
 	/*
 	 * If VBUS is present, start sinking from it if we haven't already
 	 * chosen a charge port and no battery is connected.  This is
@@ -131,7 +129,7 @@ int raa489000_init(int port)
 				ISL9238_REG_CONTROL3, &regval);
 		regval &= ~RAA489000_ENABLE_ADC;
 		rv |= i2c_write16(i2c_port, ISL923X_ADDR_FLAGS,
-				ISL9238_REG_CONTROL3, regval);
+				  ISL9238_REG_CONTROL3, regval);
 		if (rv)
 			CPRINTS("c%d: failed to disable ADCs", port);
 	}
@@ -172,14 +170,14 @@ int raa489000_init(int port)
 	 */
 	if (device_id <= 1) {
 		rv = tcpc_write16(port, RAA489000_TYPEC_SETTING1,
-			     RAA489000_SETTING1_RDOE |
-			     RAA489000_SETTING1_CC2_CMP3_EN |
-			     RAA489000_SETTING1_CC2_CMP2_EN |
-			     RAA489000_SETTING1_CC2_CMP1_EN |
-			     RAA489000_SETTING1_CC1_CMP3_EN |
-			     RAA489000_SETTING1_CC1_CMP2_EN |
-			     RAA489000_SETTING1_CC1_CMP1_EN |
-			     RAA489000_SETTING1_CC_DB_EN);
+				  RAA489000_SETTING1_RDOE |
+					  RAA489000_SETTING1_CC2_CMP3_EN |
+					  RAA489000_SETTING1_CC2_CMP2_EN |
+					  RAA489000_SETTING1_CC2_CMP1_EN |
+					  RAA489000_SETTING1_CC1_CMP3_EN |
+					  RAA489000_SETTING1_CC1_CMP2_EN |
+					  RAA489000_SETTING1_CC1_CMP1_EN |
+					  RAA489000_SETTING1_CC_DB_EN);
 		if (rv)
 			CPRINTS("c%d: failed to enable CC comparators", port);
 	}
@@ -187,8 +185,8 @@ int raa489000_init(int port)
 	/* Set Rx enable for receiver comparator */
 	rv = tcpc_read16(port, RAA489000_PD_PHYSICAL_SETTING1, &regval);
 	regval |= RAA489000_PD_PHY_SETTING1_RECEIVER_EN |
-		RAA489000_PD_PHY_SETTING1_SQUELCH_EN |
-		RAA489000_PD_PHY_SETTING1_TX_LDO11_EN;
+		  RAA489000_PD_PHY_SETTING1_SQUELCH_EN |
+		  RAA489000_PD_PHY_SETTING1_TX_LDO11_EN;
 	rv |= tcpc_write16(port, RAA489000_PD_PHYSICAL_SETTING1, regval);
 	if (rv)
 		CPRINTS("c%d: failed to set PD PHY setting1", port);
@@ -231,13 +229,13 @@ int raa489000_init(int port)
 	 * Set Vbus OCP UV here, PD tasks will set target current
 	 */
 	rv = tcpc_write16(port, RAA489000_VBUS_OCP_UV_THRESHOLD,
-				RAA489000_OCP_THRESHOLD_VALUE);
+			  RAA489000_OCP_THRESHOLD_VALUE);
 	if (rv)
 		CPRINTS("c%d: failed to set OCP threshold", port);
 
 	/* Set Vbus Target Voltage */
 	rv = tcpc_write16(port, RAA489000_VBUS_VOLTAGE_TARGET,
-				RAA489000_VBUS_VOLTAGE_TARGET_5160MV);
+			  RAA489000_VBUS_VOLTAGE_TARGET_5160MV);
 	if (rv)
 		CPRINTS("c%d: failed to set Vbus Target Voltage", port);
 
@@ -260,6 +258,54 @@ int raa489000_tcpm_set_cc(int port, int pull)
 	return rv;
 }
 
+#ifdef CONFIG_CMD_TCPC_DUMP
+
+static const struct tcpc_reg_dump_map raa489000_regs[] = {
+	{
+		.addr = RAA489000_TCPC_SETTING1,
+		.name = "TCPC_SETTING1",
+		.size = 2,
+	},
+	{
+		.addr = RAA489000_VBUS_VOLTAGE_TARGET,
+		.name = "VBUS_VOLTAGE_TARGET",
+		.size = 2,
+	},
+	{
+		.addr = RAA489000_VBUS_CURRENT_TARGET,
+		.name = "VBUS_CURRENT_TARGET",
+		.size = 2,
+	},
+	{
+		.addr = RAA489000_VBUS_OCP_UV_THRESHOLD,
+		.name = "VBUS_OCP_UV_THRESHOLD",
+		.size = 2,
+	},
+	{
+		.addr = RAA489000_TYPEC_SETTING1,
+		.name = "TYPEC_SETTING1",
+		.size = 2,
+	},
+	{
+		.addr = RAA489000_PD_PHYSICAL_SETTING1,
+		.name = "PD_PHYSICAL_SETTING1",
+		.size = 2,
+	},
+	{
+		.addr = RAA489000_PD_PHYSICAL_PARAMETER1,
+		.name = "PD_PHYSICAL_PARAMETER1",
+		.size = 2,
+	},
+};
+
+void raa489000_dump_registers(int port)
+{
+	tcpc_dump_std_registers(port);
+	tcpc_dump_registers(port, raa489000_regs, ARRAY_SIZE(raa489000_regs));
+}
+
+#endif
+
 int raa489000_debug_detach(int port)
 {
 	int rv;
@@ -278,7 +324,7 @@ int raa489000_debug_detach(int port)
 	RETURN_ERROR(tcpc_read(port, TCPC_REG_POWER_STATUS, &power_status));
 
 	if (!pd_is_battery_capable() &&
-			(power_status & TCPC_REG_POWER_STATUS_SINKING_VBUS))
+	    (power_status & TCPC_REG_POWER_STATUS_SINKING_VBUS))
 		return EC_SUCCESS;
 
 	tcpci_tcpc_enable_auto_discharge_disconnect(port, 1);
@@ -292,37 +338,44 @@ int raa489000_debug_detach(int port)
 
 /* RAA489000 is a TCPCI compatible port controller */
 const struct tcpm_drv raa489000_tcpm_drv = {
-	.init                   = &raa489000_init,
-	.release                = &tcpci_tcpm_release,
-	.get_cc                 = &tcpci_tcpm_get_cc,
+	.init = &raa489000_init,
+	.release = &tcpci_tcpm_release,
+	.get_cc = &tcpci_tcpm_get_cc,
 #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	.check_vbus_level       = &tcpci_tcpm_check_vbus_level,
+	.check_vbus_level = &tcpci_tcpm_check_vbus_level,
 #endif
-	.select_rp_value        = &tcpci_tcpm_select_rp_value,
-	.set_cc                 = &raa489000_tcpm_set_cc,
-	.set_polarity           = &tcpci_tcpm_set_polarity,
+	.select_rp_value = &tcpci_tcpm_select_rp_value,
+	.set_cc = &raa489000_tcpm_set_cc,
+	.set_polarity = &tcpci_tcpm_set_polarity,
 #ifdef CONFIG_USB_PD_DECODE_SOP
-	.sop_prime_enable	= &tcpci_tcpm_sop_prime_enable,
+	.sop_prime_enable = &tcpci_tcpm_sop_prime_enable,
 #endif
-	.set_vconn              = &tcpci_tcpm_set_vconn,
-	.set_msg_header         = &tcpci_tcpm_set_msg_header,
-	.set_rx_enable          = &tcpci_tcpm_set_rx_enable,
-	.get_message_raw        = &tcpci_tcpm_get_message_raw,
-	.transmit               = &tcpci_tcpm_transmit,
-	.tcpc_alert             = &tcpci_tcpc_alert,
+	.set_vconn = &tcpci_tcpm_set_vconn,
+	.set_msg_header = &tcpci_tcpm_set_msg_header,
+	.set_rx_enable = &tcpci_tcpm_set_rx_enable,
+	.get_message_raw = &tcpci_tcpm_get_message_raw,
+	.transmit = &tcpci_tcpm_transmit,
+	.tcpc_alert = &tcpci_tcpc_alert,
 #ifdef CONFIG_USB_PD_DISCHARGE_TCPC
-	.tcpc_discharge_vbus    = &tcpci_tcpc_discharge_vbus,
+	.tcpc_discharge_vbus = &tcpci_tcpc_discharge_vbus,
 #endif
 #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-	.drp_toggle             = &tcpci_tcpc_drp_toggle,
+	.drp_toggle = &tcpci_tcpc_drp_toggle,
 #endif
-	.get_chip_info          = &tcpci_get_chip_info,
+	.get_chip_info = &tcpci_get_chip_info,
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	.enter_low_power_mode   = &raa489000_enter_low_power_mode,
-	.wake_low_power_mode	= &tcpci_wake_low_power_mode,
+	.enter_low_power_mode = &raa489000_enter_low_power_mode,
+	.wake_low_power_mode = &tcpci_wake_low_power_mode,
 #endif
-	.set_bist_test_mode	= &tcpci_set_bist_test_mode,
+	.set_bist_test_mode = &tcpci_set_bist_test_mode,
+	.get_bist_test_mode = &tcpci_get_bist_test_mode,
 	.tcpc_enable_auto_discharge_disconnect =
 		&tcpci_tcpc_enable_auto_discharge_disconnect,
-	.debug_detach		= &raa489000_debug_detach,
+	.debug_detach = &raa489000_debug_detach,
+#ifdef CONFIG_CMD_TCPC_DUMP
+	.dump_registers = &raa489000_dump_registers,
+#endif
+#ifdef CONFIG_USB_PD_FRS
+	.set_frs_enable = &tcpci_tcpc_fast_role_swap_enable,
+#endif
 };
diff --git a/driver/tcpm/raa489000.h b/driver/tcpm/raa489000.h
index 2a4c7c6b3d..41a37f94e7 100644
--- a/driver/tcpm/raa489000.h
+++ b/driver/tcpm/raa489000.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -17,25 +17,25 @@
 #define RAA489000_TCPC3_I2C_FLAGS 0x25
 
 /* Vendor registers */
-#define RAA489000_TCPC_SETTING1			0x80
-#define RAA489000_VBUS_VOLTAGE_TARGET		0x90
-#define RAA489000_VBUS_CURRENT_TARGET		0x92
-#define RAA489000_VBUS_OCP_UV_THRESHOLD		0x94
-#define RAA489000_TYPEC_SETTING1		0xC0
-#define RAA489000_PD_PHYSICAL_SETTING1		0xE0
-#define RAA489000_PD_PHYSICAL_PARAMETER1	0xE8
+#define RAA489000_TCPC_SETTING1 0x80
+#define RAA489000_VBUS_VOLTAGE_TARGET 0x90
+#define RAA489000_VBUS_CURRENT_TARGET 0x92
+#define RAA489000_VBUS_OCP_UV_THRESHOLD 0x94
+#define RAA489000_TYPEC_SETTING1 0xC0
+#define RAA489000_PD_PHYSICAL_SETTING1 0xE0
+#define RAA489000_PD_PHYSICAL_PARAMETER1 0xE8
 
 /* TCPC_SETTING_1 */
-#define RAA489000_TCPCV1_0_EN		BIT(0)
-#define RAA489000_TCPC_PWR_CNTRL	BIT(4)
+#define RAA489000_TCPCV1_0_EN BIT(0)
+#define RAA489000_TCPC_PWR_CNTRL BIT(4)
 
 /* VBUS_CURRENT_TARGET */
-#define RAA489000_VBUS_CURRENT_TARGET_3A	0x66 /* 3.0A + iOvershoot */
-#define RAA489000_VBUS_CURRENT_TARGET_1_5A	0x38 /* 1.5A + iOvershoot */
+#define RAA489000_VBUS_CURRENT_TARGET_3A 0x66 /* 3.0A + iOvershoot */
+#define RAA489000_VBUS_CURRENT_TARGET_1_5A 0x38 /* 1.5A + iOvershoot */
 
 /* VBUS_VOLTAGE_TARGET */
-#define RAA489000_VBUS_VOLTAGE_TARGET_5160MV	0x102 /* 5.16V */
-#define RAA489000_VBUS_VOLTAGE_TARGET_5220MV	0x105 /* 5.22V */
+#define RAA489000_VBUS_VOLTAGE_TARGET_5160MV 0x102 /* 5.16V */
+#define RAA489000_VBUS_VOLTAGE_TARGET_5220MV 0x105 /* 5.22V */
 
 /* VBUS_OCP_UV_THRESHOLD */
 /* Detect voltage level of overcurrent protection during Sourcing VBUS */
@@ -43,26 +43,26 @@
 
 /* TYPEC_SETTING1 - only older silicon */
 /* Enables for reverse current protection */
-#define RAA489000_SETTING1_IP2_EN	BIT(9)
-#define RAA489000_SETTING1_IP1_EN	BIT(8)
+#define RAA489000_SETTING1_IP2_EN BIT(9)
+#define RAA489000_SETTING1_IP1_EN BIT(8)
 
 /* Switches from dead-battery Rd */
-#define RAA489000_SETTING1_RDOE		BIT(7)
+#define RAA489000_SETTING1_RDOE BIT(7)
 
 /* CC comparator enables */
-#define RAA489000_SETTING1_CC2_CMP3_EN	BIT(6)
-#define RAA489000_SETTING1_CC2_CMP2_EN	BIT(5)
-#define RAA489000_SETTING1_CC2_CMP1_EN	BIT(4)
-#define RAA489000_SETTING1_CC1_CMP3_EN	BIT(3)
-#define RAA489000_SETTING1_CC1_CMP2_EN	BIT(2)
-#define RAA489000_SETTING1_CC1_CMP1_EN	BIT(1)
+#define RAA489000_SETTING1_CC2_CMP3_EN BIT(6)
+#define RAA489000_SETTING1_CC2_CMP2_EN BIT(5)
+#define RAA489000_SETTING1_CC2_CMP1_EN BIT(4)
+#define RAA489000_SETTING1_CC1_CMP3_EN BIT(3)
+#define RAA489000_SETTING1_CC1_CMP2_EN BIT(2)
+#define RAA489000_SETTING1_CC1_CMP1_EN BIT(1)
 
 /* CC debounce enable */
-#define RAA489000_SETTING1_CC_DB_EN	BIT(0)
+#define RAA489000_SETTING1_CC_DB_EN BIT(0)
 
 /* PD_PHYSICAL_SETTING_1 */
 #define RAA489000_PD_PHY_SETTING1_RECEIVER_EN BIT(9)
-#define RAA489000_PD_PHY_SETTING1_SQUELCH_EN  BIT(8)
+#define RAA489000_PD_PHY_SETTING1_SQUELCH_EN BIT(8)
 #define RAA489000_PD_PHY_SETTING1_TX_LDO11_EN BIT(0)
 
 /* PD_PHYSICAL_PARMETER_1 */
diff --git a/driver/tcpm/rt1715.c b/driver/tcpm/rt1715.c
index 7985ee95a3..60bb3da068 100644
--- a/driver/tcpm/rt1715.c
+++ b/driver/tcpm/rt1715.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,12 +20,11 @@
 static int rt1715_polarity[CONFIG_USB_PD_PORT_MAX_COUNT];
 static bool rt1715_initialized[CONFIG_USB_PD_PORT_MAX_COUNT];
 
-
 static int rt1715_enable_ext_messages(int port, int enable)
 {
 	return tcpc_update8(port, RT1715_REG_VENDOR_5,
-		  RT1715_REG_VENDOR_5_ENEXTMSG,
-		  enable ? MASK_SET : MASK_CLR);
+			    RT1715_REG_VENDOR_5_ENEXTMSG,
+			    enable ? MASK_SET : MASK_CLR);
 }
 
 static int rt1715_tcpci_tcpm_init(int port)
@@ -40,7 +39,7 @@ static int rt1715_tcpci_tcpm_init(int port)
 	if (!(rt1715_initialized[port])) {
 		/* RT1715 has a vendor-defined register reset */
 		rv = tcpc_update8(port, RT1715_REG_VENDOR_7,
-			RT1715_REG_VENDOR_7_SOFT_RESET, MASK_SET);
+				  RT1715_REG_VENDOR_7_SOFT_RESET, MASK_SET);
 		if (rv)
 			return rv;
 		rt1715_initialized[port] = true;
@@ -48,7 +47,7 @@ static int rt1715_tcpci_tcpm_init(int port)
 	}
 
 	rv = tcpc_update8(port, RT1715_REG_VENDOR_5,
-		  RT1715_REG_VENDOR_5_SHUTDOWN_OFF, MASK_SET);
+			  RT1715_REG_VENDOR_5_SHUTDOWN_OFF, MASK_SET);
 	if (rv)
 		return rv;
 
@@ -56,8 +55,8 @@ static int rt1715_tcpci_tcpm_init(int port)
 		rt1715_enable_ext_messages(port, 1);
 
 	rv = tcpc_write(port, RT1715_REG_I2CRST_CTRL,
-		  (RT1715_REG_I2CRST_CTRL_EN |
-		  RT1715_REG_I2CRST_CTRL_TOUT_200MS));
+			(RT1715_REG_I2CRST_CTRL_EN |
+			 RT1715_REG_I2CRST_CTRL_TOUT_200MS));
 	if (rv)
 		return rv;
 
@@ -71,27 +70,27 @@ static int rt1715_tcpci_tcpm_init(int port)
 	 * (min 250 us, max 500 us).
 	 */
 	rv = tcpc_write(port, RT1715_REG_TTCPC_FILTER,
-		  RT1715_REG_TTCPC_FILTER_400US);
+			RT1715_REG_TTCPC_FILTER_400US);
 	if (rv)
 		return rv;
 
 	rv = tcpc_write(port, RT1715_REG_DRP_TOGGLE_CYCLE,
-		  RT1715_REG_DRP_TOGGLE_CYCLE_76MS);
+			RT1715_REG_DRP_TOGGLE_CYCLE_76MS);
 	if (rv)
 		return rv;
 
 	/* PHY control */
 	/* Set PHY control registers to Richtek recommended values */
 	rv = tcpc_write(port, RT1715_REG_PHY_CTRL1,
-		  (RT1715_REG_PHY_CTRL1_ENRETRY |
-		  RT1715_REG_PHY_CTRL1_TRANSCNT_7 |
-		  RT1715_REG_PHY_CTRL1_TRXFILTER_125NS));
+			(RT1715_REG_PHY_CTRL1_ENRETRY |
+			 RT1715_REG_PHY_CTRL1_TRANSCNT_7 |
+			 RT1715_REG_PHY_CTRL1_TRXFILTER_125NS));
 	if (rv)
 		return rv;
 
 	/* Set PHY control registers to Richtek recommended values */
 	rv = tcpc_write(port, RT1715_REG_PHY_CTRL2,
-		  RT1715_REG_PHY_CTRL2_CDRTHRESH_2_58US);
+			RT1715_REG_PHY_CTRL2_CDRTHRESH_2_58US);
 	if (rv)
 		return rv;
 
@@ -113,14 +112,14 @@ static inline int rt1715_init_cc_params(int port, int cc_level)
 		/* RXCC threshold : 0.55V */
 		en = RT1715_REG_BMCIO_RXDZEN_DISABLE;
 
-		sel = RT1715_REG_BMCIO_RXDZSEL_OCCTRL_600MA
-		  | RT1715_REG_BMCIO_RXDZSEL_SEL;
+		sel = RT1715_REG_BMCIO_RXDZSEL_OCCTRL_600MA |
+		      RT1715_REG_BMCIO_RXDZSEL_SEL;
 	} else {
 		/* RD threshold : 0.35V & RP threshold : 0.75V */
 		en = RT1715_REG_BMCIO_RXDZEN_ENABLE;
 
-		sel = RT1715_REG_BMCIO_RXDZSEL_OCCTRL_600MA
-		  | RT1715_REG_BMCIO_RXDZSEL_SEL;
+		sel = RT1715_REG_BMCIO_RXDZSEL_OCCTRL_600MA |
+		      RT1715_REG_BMCIO_RXDZSEL_SEL;
 	}
 
 	rv = tcpc_write(port, RT1715_REG_BMCIO_RXDZEN, en);
@@ -131,7 +130,7 @@ static inline int rt1715_init_cc_params(int port, int cc_level)
 }
 
 static int rt1715_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2)
+			 enum tcpc_cc_voltage_status *cc2)
 {
 	int rv;
 
@@ -235,7 +234,7 @@ const struct tcpm_drv rt1715_tcpm_drv = {
 	.set_cc = &tcpci_tcpm_set_cc,
 	.set_polarity = &rt1715_set_polarity,
 #ifdef CONFIG_USB_PD_DECODE_SOP
-	.sop_prime_enable   = &tcpci_tcpm_sop_prime_enable,
+	.sop_prime_enable = &tcpci_tcpm_sop_prime_enable,
 #endif
 	.set_vconn = &rt1715_set_vconn,
 	.set_msg_header = &tcpci_tcpm_set_msg_header,
@@ -257,5 +256,6 @@ const struct tcpm_drv rt1715_tcpm_drv = {
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
 	.enter_low_power_mode = &rt1715_enter_low_power_mode,
 #endif
-	.set_bist_test_mode	= &tcpci_set_bist_test_mode,
+	.set_bist_test_mode = &tcpci_set_bist_test_mode,
+	.get_bist_test_mode = &tcpci_get_bist_test_mode,
 };
diff --git a/driver/tcpm/rt1715.h b/driver/tcpm/rt1715.h
index dcf2aa28d4..d489dc73fd 100644
--- a/driver/tcpm/rt1715.h
+++ b/driver/tcpm/rt1715.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,78 +7,77 @@
 #define __CROS_EC_USB_PD_TCPM_RT1715_H
 
 /* I2C interface */
-#define RT1715_I2C_ADDR_FLAGS			0x4E
+#define RT1715_I2C_ADDR_FLAGS 0x4E
 
-#define RT1715_VENDOR_ID			0x29CF
+#define RT1715_VENDOR_ID 0x29CF
 
-#define RT1715_REG_VENDOR_7			0xA0
-#define RT1715_REG_VENDOR_7_SOFT_RESET		BIT(0)
+#define RT1715_REG_VENDOR_7 0xA0
+#define RT1715_REG_VENDOR_7_SOFT_RESET BIT(0)
 
-#define RT1715_REG_PHY_CTRL1			0x80
+#define RT1715_REG_PHY_CTRL1 0x80
 /* Wait for tReceive before retrying transmit in response to a bad GoodCRC */
-#define RT1715_REG_PHY_CTRL1_ENRETRY		BIT(7)
+#define RT1715_REG_PHY_CTRL1_ENRETRY BIT(7)
 /*
  * Bit 6:4 <TRANSCNT>: Consider CC to be idle if there are 7 or fewer BMC
  * transients observed in <46.67us>
  */
-#define RT1715_REG_PHY_CTRL1_TRANSCNT_7		0x70
+#define RT1715_REG_PHY_CTRL1_TRANSCNT_7 0x70
 /*
  * Bit 1:0 <TRXFilter>: RX filter to make sure the stable received PD message.
  * default value is 01b
  * The debounce time is (register value + 2) * 41.67ns
  */
-#define RT1715_REG_PHY_CTRL1_TRXFILTER_125NS	0x01
-#define RT1715_REG_PHY_CTRL2			0x81
+#define RT1715_REG_PHY_CTRL1_TRXFILTER_125NS 0x01
+#define RT1715_REG_PHY_CTRL2 0x81
 /*
  * Decrease the time that the PHY will wait for a second transition to detect
  * a BMC-encoded 1 bit from 2.67 us to 2.25 us.
  * Timeout = register value * .04167 us.
  */
-#define RT1715_REG_PHY_CTRL2_CDRTHRESH_2_25US	54
-#define RT1715_REG_PHY_CTRL2_CDRTHRESH_2_5US	60
-#define RT1715_REG_PHY_CTRL2_CDRTHRESH_2_58US	62
+#define RT1715_REG_PHY_CTRL2_CDRTHRESH_2_25US 54
+#define RT1715_REG_PHY_CTRL2_CDRTHRESH_2_5US 60
+#define RT1715_REG_PHY_CTRL2_CDRTHRESH_2_58US 62
 
-#define RT1715_REG_PWR				0x90
-#define RT1715_REG_PWR_BMCIO_LPEN		BIT(3)
-#define RT1715_REG_PWR_VBUS_DETEN		BIT(1)
-#define RT1715_REG_PWR_BMCIO_OSCEN		BIT(0)
+#define RT1715_REG_PWR 0x90
+#define RT1715_REG_PWR_BMCIO_LPEN BIT(3)
+#define RT1715_REG_PWR_VBUS_DETEN BIT(1)
+#define RT1715_REG_PWR_BMCIO_OSCEN BIT(0)
 
-#define RT1715_REG_BMCIO_RXDZSEL		0x93
-#define RT1715_REG_BMCIO_RXDZSEL_OCCTRL_600MA	BIT(7)
-#define RT1715_REG_BMCIO_RXDZSEL_SEL		BIT(0)
+#define RT1715_REG_BMCIO_RXDZSEL 0x93
+#define RT1715_REG_BMCIO_RXDZSEL_OCCTRL_600MA BIT(7)
+#define RT1715_REG_BMCIO_RXDZSEL_SEL BIT(0)
 
-#define RT1715_REG_RT_INT			0x98
-#define RT1715_REG_RT_INT_WAKEUP		BIT(0)
+#define RT1715_REG_RT_INT 0x98
+#define RT1715_REG_RT_INT_WAKEUP BIT(0)
 
-#define RT1715_REG_RT_MASK			0x99
-#define RT1715_REG_RT_MASK_M_WAKEUP		BIT(0)
+#define RT1715_REG_RT_MASK 0x99
+#define RT1715_REG_RT_MASK_M_WAKEUP BIT(0)
 
-#define RT1715_REG_VENDOR_5			0x9B
-#define RT1715_REG_VENDOR_5_SHUTDOWN_OFF	BIT(5)
-#define RT1715_REG_VENDOR_5_ENEXTMSG		BIT(4)
-#define RT1715_REG_VENDOR_5_AUTOIDLE_EN		BIT(3)
+#define RT1715_REG_VENDOR_5 0x9B
+#define RT1715_REG_VENDOR_5_SHUTDOWN_OFF BIT(5)
+#define RT1715_REG_VENDOR_5_ENEXTMSG BIT(4)
+#define RT1715_REG_VENDOR_5_AUTOIDLE_EN BIT(3)
 
-#define RT1715_REG_I2CRST_CTRL			0x9E
+#define RT1715_REG_I2CRST_CTRL 0x9E
 /* I2C reset : (val + 1) * 12.5ms */
-#define RT1715_REG_I2CRST_CTRL_TOUT_200MS	0x0F
-#define RT1715_REG_I2CRST_CTRL_TOUT_150MS	0x0B
-#define RT1715_REG_I2CRST_CTRL_TOUT_100MS	0x07
-#define RT1715_REG_I2CRST_CTRL_EN		BIT(7)
+#define RT1715_REG_I2CRST_CTRL_TOUT_200MS 0x0F
+#define RT1715_REG_I2CRST_CTRL_TOUT_150MS 0x0B
+#define RT1715_REG_I2CRST_CTRL_TOUT_100MS 0x07
+#define RT1715_REG_I2CRST_CTRL_EN BIT(7)
 
+#define RT1715_REG_TTCPC_FILTER 0xA1
+#define RT1715_REG_TTCPC_FILTER_400US 0x0F
 
-#define RT1715_REG_TTCPC_FILTER			0xA1
-#define RT1715_REG_TTCPC_FILTER_400US		0x0F
-
-#define RT1715_REG_DRP_TOGGLE_CYCLE		0xA2
+#define RT1715_REG_DRP_TOGGLE_CYCLE 0xA2
 /* DRP Duty : (51.2 + 6.4 * val) ms */
-#define RT1715_REG_DRP_TOGGLE_CYCLE_76MS	0x04
+#define RT1715_REG_DRP_TOGGLE_CYCLE_76MS 0x04
 
-#define RT1715_REG_DRP_DUTY_CTRL		0xA3
-#define RT1715_REG_DRP_DUTY_CTRL_40PERCENT	400
+#define RT1715_REG_DRP_DUTY_CTRL 0xA3
+#define RT1715_REG_DRP_DUTY_CTRL_40PERCENT 400
 
-#define RT1715_REG_BMCIO_RXDZEN			0xAF
-#define RT1715_REG_BMCIO_RXDZEN_ENABLE		0x01
-#define RT1715_REG_BMCIO_RXDZEN_DISABLE		0x00
+#define RT1715_REG_BMCIO_RXDZEN 0xAF
+#define RT1715_REG_BMCIO_RXDZEN_ENABLE 0x01
+#define RT1715_REG_BMCIO_RXDZEN_DISABLE 0x00
 
 extern const struct tcpm_drv rt1715_tcpm_drv;
 
diff --git a/driver/tcpm/rt1718s.c b/driver/tcpm/rt1718s.c
index e985419668..a009e33323 100644
--- a/driver/tcpm/rt1718s.c
+++ b/driver/tcpm/rt1718s.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,26 +22,25 @@
 #include "usb_pe_sm.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-#define RT1718S_SW_RESET_DELAY_MS	2
+#define RT1718S_SW_RESET_DELAY_MS 2
 /* Time for delay deasserting EN_FRS after FRS VBUS drop. */
-#define RT1718S_FRS_DIS_DELAY		(5 * MSEC)
+#define RT1718S_FRS_DIS_DELAY (5 * MSEC)
 
-#define FLAG_FRS_ENABLED		BIT(0)
-#define FLAG_FRS_RX_SIGNALLED		BIT(1)
-#define FLAG_FRS_VBUS_VALID_FALL	BIT(2)
+#define FLAG_FRS_ENABLED BIT(0)
+#define FLAG_FRS_RX_SIGNALLED BIT(1)
+#define FLAG_FRS_VBUS_VALID_FALL BIT(2)
 static atomic_t frs_flag[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 /* i2c_write function which won't wake TCPC from low power mode. */
 static int rt1718s_write(int port, int reg, int val, int len)
 {
 	if (reg > 0xFF) {
-		return i2c_write_offset16(
-			tcpc_config[port].i2c_info.port,
-			tcpc_config[port].i2c_info.addr_flags,
-			reg, val, len);
+		return i2c_write_offset16(tcpc_config[port].i2c_info.port,
+					  tcpc_config[port].i2c_info.addr_flags,
+					  reg, val, len);
 	} else if (len == 1) {
 		return tcpc_write(port, reg, val);
 	} else {
@@ -52,10 +51,9 @@ static int rt1718s_write(int port, int reg, int val, int len)
 static int rt1718s_read(int port, int reg, int *val, int len)
 {
 	if (reg > 0xFF) {
-		return i2c_read_offset16(
-			tcpc_config[port].i2c_info.port,
-			tcpc_config[port].i2c_info.addr_flags,
-			reg, val, len);
+		return i2c_read_offset16(tcpc_config[port].i2c_info.port,
+					 tcpc_config[port].i2c_info.addr_flags,
+					 reg, val, len);
 	} else if (len == 1) {
 		return tcpc_read(port, reg, val);
 	} else {
@@ -97,13 +95,12 @@ int rt1718s_read16(int port, int reg, int *val)
 	return rt1718s_read(port, reg, val, 2);
 }
 
-
 int rt1718s_sw_reset(int port)
 {
 	int rv;
 
-	rv = rt1718s_update_bits8(port, RT1718S_SYS_CTRL3,
-		RT1718S_SWRESET_MASK, 0xFF);
+	rv = rt1718s_update_bits8(port, RT1718S_SYS_CTRL3, RT1718S_SWRESET_MASK,
+				  0xFF);
 
 	msleep(RT1718S_SW_RESET_DELAY_MS);
 
@@ -114,44 +111,43 @@ int rt1718s_sw_reset(int port)
 static int rt1718s_enable_bc12_sink(int port, bool en)
 {
 	return rt1718s_update_bits8(port, RT1718S_RT2_BC12_SNK_FUNC,
-			RT1718S_RT2_BC12_SNK_FUNC_BC12_SNK_EN,
-			en ? 0xFF : 0);
+				    RT1718S_RT2_BC12_SNK_FUNC_BC12_SNK_EN,
+				    en ? 0xFF : 0);
 }
 
 static int rt1718s_set_bc12_sink_spec_ta(int port, bool en)
 {
-	return rt1718s_update_bits8(port,
-			RT1718S_RT2_BC12_SNK_FUNC,
-			RT1718S_RT2_BC12_SNK_FUNC_SPEC_TA_EN, en ? 0xFF : 0);
+	return rt1718s_update_bits8(port, RT1718S_RT2_BC12_SNK_FUNC,
+				    RT1718S_RT2_BC12_SNK_FUNC_SPEC_TA_EN,
+				    en ? 0xFF : 0);
 }
 
 static int rt1718s_set_bc12_sink_dcdt_sel(int port, uint8_t dcdt_sel)
 {
-	return rt1718s_update_bits8(port,
-			RT1718S_RT2_BC12_SNK_FUNC,
-			RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_MASK, dcdt_sel);
+	return rt1718s_update_bits8(port, RT1718S_RT2_BC12_SNK_FUNC,
+				    RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_MASK,
+				    dcdt_sel);
 }
 
 static int rt1718s_set_bc12_sink_vlgc_option(int port, bool en)
 {
-	return rt1718s_update_bits8(port,
-			RT1718S_RT2_BC12_SNK_FUNC,
-			RT1718S_RT2_BC12_SNK_FUNC_VLGC_OPT, en ? 0xFF : 0);
+	return rt1718s_update_bits8(port, RT1718S_RT2_BC12_SNK_FUNC,
+				    RT1718S_RT2_BC12_SNK_FUNC_VLGC_OPT,
+				    en ? 0xFF : 0);
 }
 
 static int rt1718s_set_bc12_sink_vport_sel(int port, uint8_t sel)
 {
-	return rt1718s_update_bits8(port,
-			RT1718S_RT2_DPDM_CTR1_DPDM_SET,
-			RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_MASK, sel);
+	return rt1718s_update_bits8(
+		port, RT1718S_RT2_DPDM_CTR1_DPDM_SET,
+		RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_MASK, sel);
 }
 
 static int rt1718s_set_bc12_sink_wait_vbus(int port, bool en)
 {
-	return rt1718s_update_bits8(port,
-			RT1718S_RT2_BC12_SNK_FUNC,
-			RT1718S_RT2_BC12_SNK_FUNC_BC12_WAIT_VBUS,
-			en ? 0xFF : 0);
+	return rt1718s_update_bits8(port, RT1718S_RT2_BC12_SNK_FUNC,
+				    RT1718S_RT2_BC12_SNK_FUNC_BC12_WAIT_VBUS,
+				    en ? 0xFF : 0);
 }
 
 /*
@@ -161,27 +157,27 @@ static int rt1718s_bc12_init(int port)
 {
 	/* Enable vendor defined BC12 function */
 	RETURN_ERROR(rt1718s_write8(port, RT1718S_RT_MASK6,
-			RT1718S_RT_MASK6_M_BC12_SNK_DONE |
-			RT1718S_RT_MASK6_M_BC12_TA_CHG));
+				    RT1718S_RT_MASK6_M_BC12_SNK_DONE |
+					    RT1718S_RT_MASK6_M_BC12_TA_CHG));
 
 	RETURN_ERROR(rt1718s_write8(port, RT1718S_RT2_SBU_CTRL_01,
-			RT1718S_RT2_SBU_CTRL_01_DPDM_VIEN |
-			RT1718S_RT2_SBU_CTRL_01_DM_SWEN |
-			RT1718S_RT2_SBU_CTRL_01_DP_SWEN));
+				    RT1718S_RT2_SBU_CTRL_01_DPDM_VIEN |
+					    RT1718S_RT2_SBU_CTRL_01_DM_SWEN |
+					    RT1718S_RT2_SBU_CTRL_01_DP_SWEN));
 
 	/* Disable 2.7v mode */
 	RETURN_ERROR(rt1718s_set_bc12_sink_spec_ta(port, false));
 
 	/* DCDT select 600ms timeout */
-	RETURN_ERROR(rt1718s_set_bc12_sink_dcdt_sel(port,
-			RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_600MS));
+	RETURN_ERROR(rt1718s_set_bc12_sink_dcdt_sel(
+		port, RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_600MS));
 
 	/* Disable vlgc option */
 	RETURN_ERROR(rt1718s_set_bc12_sink_vlgc_option(port, false));
 
 	/* DPDM voltage selection */
-	RETURN_ERROR(rt1718s_set_bc12_sink_vport_sel(port,
-			RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_0_65V));
+	RETURN_ERROR(rt1718s_set_bc12_sink_vport_sel(
+		port, RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_0_65V));
 
 	/* Disable sink wait vbus */
 	RETURN_ERROR(rt1718s_set_bc12_sink_wait_vbus(port, false));
@@ -197,22 +193,24 @@ static int rt1718s_workaround(int port)
 
 	switch (device_id) {
 	case RT1718S_DEVICE_ID_ES1:
-		RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_VCONN_CONTROL_3,
-					RT1718S_VCONN_CONTROL_3_VCONN_OVP_DEG,
-					0xFF));
+		RETURN_ERROR(rt1718s_update_bits8(
+			port, RT1718S_VCONN_CONTROL_3,
+			RT1718S_VCONN_CONTROL_3_VCONN_OVP_DEG, 0xFF));
 		/* fallthrough */
 	case RT1718S_DEVICE_ID_ES2:
-		RETURN_ERROR(rt1718s_update_bits8(port, TCPC_REG_FAULT_CTRL,
-					TCPC_REG_FAULT_CTRL_VBUS_OCP_FAULT_DIS,
-					0xFF));
-		RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_VCON_CTRL4,
-					RT1718S_VCON_CTRL4_UVP_CP_EN |
-					RT1718S_VCON_CTRL4_OCP_CP_EN,
-					0));
-		RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_VCONN_CONTROL_2,
-					RT1718S_VCONN_CONTROL_2_OVP_EN_CC1 |
-					RT1718S_VCONN_CONTROL_2_OVP_EN_CC2,
-					0xFF));
+		RETURN_ERROR(rt1718s_update_bits8(
+			port, TCPC_REG_FAULT_CTRL,
+			TCPC_REG_FAULT_CTRL_VBUS_OCP_FAULT_DIS, 0xFF));
+		RETURN_ERROR(rt1718s_update_bits8(
+			port, RT1718S_VCON_CTRL4,
+			RT1718S_VCON_CTRL4_UVP_CP_EN |
+				RT1718S_VCON_CTRL4_OCP_CP_EN,
+			0));
+		RETURN_ERROR(rt1718s_update_bits8(
+			port, RT1718S_VCONN_CONTROL_2,
+			RT1718S_VCONN_CONTROL_2_OVP_EN_CC1 |
+				RT1718S_VCONN_CONTROL_2_OVP_EN_CC2,
+			0xFF));
 		break;
 	default:
 		/* do nothing */
@@ -271,12 +269,13 @@ static int rt1718s_init(int port)
 
 	/* Set VBUS_VOL_SEL to 20V */
 	RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_RT2_VBUS_VOL_CTRL,
-				RT1718S_RT2_VBUS_VOL_CTRL_VOL_SEL,
-				RT1718S_VBUS_VOL_TO_REG(20)));
+					  RT1718S_RT2_VBUS_VOL_CTRL_VOL_SEL,
+					  RT1718S_VBUS_VOL_TO_REG(20)));
 
 	/* Set VCONN_OCP_SEL to 400mA */
 	RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_VCONN_CONTROL_3,
-				RT1718S_VCONN_CONTROL_3_VCONN_OCP_SEL, 0x7F));
+					  RT1718S_VCONN_CONTROL_3_VCONN_OCP_SEL,
+					  0x7F));
 
 	/* Increase the Vconn OCP shoot detection from 200ns to 3~5us */
 	RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_VCON_CTRL4,
@@ -287,9 +286,10 @@ static int rt1718s_init(int port)
 
 	/* Tcpc connect invalid disabled. Exit shipping mode */
 	RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_SYS_CTRL1,
-				RT1718S_SYS_CTRL1_TCPC_CONN_INVALID, 0x00));
-	RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_SYS_CTRL1,
-				RT1718S_SYS_CTRL1_SHIPPING_OFF, 0xFF));
+					  RT1718S_SYS_CTRL1_TCPC_CONN_INVALID,
+					  0x00));
+	RETURN_ERROR(rt1718s_update_bits8(
+		port, RT1718S_SYS_CTRL1, RT1718S_SYS_CTRL1_SHIPPING_OFF, 0xFF));
 
 	/* Clear alert and fault */
 	RETURN_ERROR(rt1718s_write8(port, TCPC_REG_FAULT_STATUS, 0xFF));
@@ -303,8 +303,7 @@ static int rt1718s_init(int port)
 	 * tcpci_tcpm_init.
 	 */
 	RETURN_ERROR(tcpc_update16(port, TCPC_REG_ALERT_MASK,
-				TCPC_REG_ALERT_MASK_VENDOR_DEF,
-				MASK_SET));
+				   TCPC_REG_ALERT_MASK_VENDOR_DEF, MASK_SET));
 
 	if (IS_ENABLED(CONFIG_USB_PD_FRS)) {
 		memset(frs_flag, 0,
@@ -368,7 +367,7 @@ static void rt1718s_update_charge_manager(int port,
 	if (new_bc12_type != current_bc12_type) {
 		if (current_bc12_type != CHARGE_SUPPLIER_NONE)
 			charge_manager_update_charge(current_bc12_type, port,
-							NULL);
+						     NULL);
 
 		if (new_bc12_type != CHARGE_SUPPLIER_NONE) {
 			struct charge_port_info chg = {
@@ -391,16 +390,15 @@ static void rt1718s_bc12_usb_charger_task_init(const int port)
 static void rt1718s_bc12_usb_charger_task_event(const int port, uint32_t evt)
 {
 	bool is_non_pd_sink = !pd_capable(port) &&
-		!usb_charger_port_is_sourcing_vbus(port) &&
-		pd_check_vbus_level(port, VBUS_PRESENT);
+			      !usb_charger_port_is_sourcing_vbus(port) &&
+			      pd_check_vbus_level(port, VBUS_PRESENT);
 
 	if (evt & USB_CHG_EVENT_VBUS) {
-
 		if (is_non_pd_sink)
 			rt1718s_enable_bc12_sink(port, true);
 		else
-			rt1718s_update_charge_manager(
-					port, CHARGE_SUPPLIER_NONE);
+			rt1718s_update_charge_manager(port,
+						      CHARGE_SUPPLIER_NONE);
 	}
 
 	/* detection done, update charge_manager and stop detection */
@@ -534,8 +532,7 @@ void rt1718s_vendor_defined_alert(int port)
 		return;
 	/* ES1 workaround: disable Vconn discharge */
 	rv = rt1718s_update_bits8(port, RT1718S_SYS_CTRL2,
-			RT1718S_SYS_CTRL2_VCONN_DISCHARGE_EN,
-			0);
+				  RT1718S_SYS_CTRL2_VCONN_DISCHARGE_EN, 0);
 	if (rv)
 		return;
 
@@ -547,7 +544,6 @@ __overridable int board_rt1718s_set_snk_enable(int port, int enable)
 	return EC_SUCCESS;
 }
 
-
 static int rt1718s_tcpm_set_snk_ctrl(int port, int enable)
 {
 	int rv;
@@ -721,8 +717,7 @@ void rt1718s_gpio_set_flags(int port, enum rt1718s_gpio signal, uint32_t flags)
 void rt1718s_gpio_set_level(int port, enum rt1718s_gpio signal, int value)
 {
 	rt1718s_update_bits8(port, RT1718S_GPIO_CTRL(signal),
-			RT1718S_GPIO_CTRL_O,
-			value ? 0xFF : 0);
+			     RT1718S_GPIO_CTRL_O, value ? 0xFF : 0);
 }
 
 int rt1718s_gpio_get_level(int port, enum rt1718s_gpio signal)
@@ -733,13 +728,12 @@ int rt1718s_gpio_get_level(int port, enum rt1718s_gpio signal)
 	return !!(val & RT1718S_GPIO_CTRL_I);
 }
 
-static int command_rt1718s_gpio(int argc, char **argv)
+static int command_rt1718s_gpio(int argc, const char **argv)
 {
 	int i, j;
 	uint32_t flags;
 
 	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
-
 		if (tcpc_config[i].drv != &rt1718s_tcpm_drv)
 			continue;
 
@@ -751,7 +745,7 @@ static int command_rt1718s_gpio(int argc, char **argv)
 				return EC_ERROR_UNKNOWN;
 
 			ccprintf("C%d GPIO%d OD=%d PU=%d PD=%d OE=%d HL=%d\n",
-				 i, j+1, !(flags & RT1718S_GPIO_CTRL_OD_N),
+				 i, j + 1, !(flags & RT1718S_GPIO_CTRL_OD_N),
 				 !!(flags & RT1718S_GPIO_CTRL_PU),
 				 !!(flags & RT1718S_GPIO_CTRL_PD),
 				 !!(flags & RT1718S_GPIO_CTRL_OE),
@@ -780,42 +774,43 @@ static int rt1718s_set_sbu(int port, bool enable)
 
 /* RT1718S is a TCPCI compatible port controller */
 const struct tcpm_drv rt1718s_tcpm_drv = {
-	.init			= &rt1718s_init,
-	.release		= &tcpci_tcpm_release,
-	.get_cc			= &tcpci_tcpm_get_cc,
+	.init = &rt1718s_init,
+	.release = &tcpci_tcpm_release,
+	.get_cc = &tcpci_tcpm_get_cc,
 #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	.check_vbus_level	= &tcpci_tcpm_check_vbus_level,
+	.check_vbus_level = &tcpci_tcpm_check_vbus_level,
 #endif
-	.select_rp_value	= &tcpci_tcpm_select_rp_value,
-	.set_cc			= &tcpci_tcpm_set_cc,
-	.set_polarity		= &tcpci_tcpm_set_polarity,
+	.select_rp_value = &tcpci_tcpm_select_rp_value,
+	.set_cc = &tcpci_tcpm_set_cc,
+	.set_polarity = &tcpci_tcpm_set_polarity,
 #ifdef CONFIG_USB_PD_DECODE_SOP
-	.sop_prime_enable	= &tcpci_tcpm_sop_prime_enable,
+	.sop_prime_enable = &tcpci_tcpm_sop_prime_enable,
 #endif
-	.set_vconn		= &rt1718s_set_vconn,
-	.set_msg_header		= &tcpci_tcpm_set_msg_header,
-	.set_rx_enable		= &tcpci_tcpm_set_rx_enable,
-	.get_message_raw	= &tcpci_tcpm_get_message_raw,
-	.transmit		= &tcpci_tcpm_transmit,
-	.tcpc_alert		= &rt1718s_alert,
+	.set_vconn = &rt1718s_set_vconn,
+	.set_msg_header = &tcpci_tcpm_set_msg_header,
+	.set_rx_enable = &tcpci_tcpm_set_rx_enable,
+	.get_message_raw = &tcpci_tcpm_get_message_raw,
+	.transmit = &tcpci_tcpm_transmit,
+	.tcpc_alert = &rt1718s_alert,
 #ifdef CONFIG_USB_PD_DISCHARGE_TCPC
-	.tcpc_discharge_vbus	= &tcpci_tcpc_discharge_vbus,
+	.tcpc_discharge_vbus = &tcpci_tcpc_discharge_vbus,
 #endif
 #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-	.drp_toggle		= &tcpci_tcpc_drp_toggle,
+	.drp_toggle = &tcpci_tcpc_drp_toggle,
 #endif
-	.get_chip_info		= &tcpci_get_chip_info,
-	.set_snk_ctrl		= &rt1718s_tcpm_set_snk_ctrl,
-	.set_src_ctrl		= &tcpci_tcpm_set_src_ctrl,
+	.get_chip_info = &tcpci_get_chip_info,
+	.set_snk_ctrl = &rt1718s_tcpm_set_snk_ctrl,
+	.set_src_ctrl = &tcpci_tcpm_set_src_ctrl,
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	.enter_low_power_mode	= &rt1718s_enter_low_power_mode,
+	.enter_low_power_mode = &rt1718s_enter_low_power_mode,
 #endif
 #ifdef CONFIG_USB_PD_FRS_TCPC
-	.set_frs_enable		= &rt1718s_set_frs_enable,
+	.set_frs_enable = &rt1718s_set_frs_enable,
 #endif
-	.set_bist_test_mode	= &tcpci_set_bist_test_mode,
+	.set_bist_test_mode = &tcpci_set_bist_test_mode,
+	.get_bist_test_mode = &tcpci_get_bist_test_mode,
 #ifdef CONFIG_USB_PD_TCPM_SBU
-	.set_sbu		= &rt1718s_set_sbu,
+	.set_sbu = &rt1718s_set_sbu,
 #endif
 };
 
diff --git a/driver/tcpm/rt1718s.h b/driver/tcpm/rt1718s.h
index a4f7545a06..f7c821ba53 100644
--- a/driver/tcpm/rt1718s.h
+++ b/driver/tcpm/rt1718s.h
@@ -1,193 +1,179 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 #ifndef __CROS_EC_USB_PD_TCPM_RT1718S_H
 #define __CROS_EC_USB_PD_TCPM_RT1718S_H
 
+#include "tcpm/rt1718s_public.h"
 #include "util.h"
 #include "usb_charge.h"
 #include "usb_pd_tcpm.h"
 
 /* RT1718S Private RegMap */
-#define RT1718S_I2C_ADDR1_FLAGS				0x43
-#define RT1718S_I2C_ADDR2_FLAGS				0x40
-
-#define RT1718S_VID					0x29CF
-#define RT1718S_PID					0x1718
-
-#define RT1718S_DEVICE_ID				0x04
-#define RT1718S_DEVICE_ID_ES1				0x4511
-#define RT1718S_DEVICE_ID_ES2				0x4513
-
-#define RT1718S_PHYCTRL1				0x80
-#define RT1718S_PHYCTRL2				0x81
-#define RT1718S_PHYCTRL3				0x82
-#define RT1718S_PHYCTRL7				0x86
-#define RT1718S_VCON_CTRL1				0x8A
-#define RT1718S_VCON_CTRL3				0x8C
-#define RT1718S_VCON_LIMIT_MODE				BIT(0)
-#define RT1718S_SYS_CTRL1				0x8F
-#define RT1718S_SYS_CTRL1_TCPC_CONN_INVALID		BIT(6)
-#define RT1718S_SYS_CTRL1_SHIPPING_OFF			BIT(5)
-#define RT1718S_SYS_CTRL2				0x90
-#define RT1718S_SYS_CTRL2_BMCIO_OSC_EN			BIT(0)
-#define RT1718S_SYS_CTRL2_LPWR_EN			BIT(3)
-
-#define RT1718S_VCONN_CONTROL_2				0x8B
-#define RT1718S_VCONN_CONTROL_2_OVP_EN_CC1		BIT(7)
-#define RT1718S_VCONN_CONTROL_2_OVP_EN_CC2		BIT(6)
-#define RT1718S_VCONN_CONTROL_2_RVP_EN                  BIT(3)
-#define RT1718S_VCONN_CONTROL_3				0x8C
-#define RT1718S_VCONN_CONTROL_3_VCONN_OCP_SEL		GENMASK(7, 5)
-#define RT1718S_VCONN_CONTROL_3_VCONN_OVP_DEG		BIT(1)
-
-#define RT1718S_SYS_CTRL2				0x90
-#define RT1718S_SYS_CTRL2_VCONN_DISCHARGE_EN		BIT(5)
-
-#define RT1718S_RT_MASK1				0x91
-#define RT1718S_RT_MASK1_M_VBUS_FRS_LOW			BIT(7)
-#define RT1718S_RT_MASK1_M_RX_FRS			BIT(6)
-#define RT1718S_RT_MASK2				0x92
-#define RT1718S_RT_MASK3				0x93
-#define RT1718S_RT_MASK4				0x94
-#define RT1718S_RT_MASK5				0x95
-#define RT1718S_RT_MASK6				0x96
-#define RT1718S_RT_MASK6_M_BC12_SNK_DONE		BIT(7)
-#define RT1718S_RT_MASK6_M_HVDCP_CHK_DONE		BIT(6)
-#define RT1718S_RT_MASK6_M_BC12_TA_CHG			BIT(5)
-#define RT1718S_RT_MASK7				0x97
-
-#define RT1718S_RT_INT1					0x98
-#define RT1718S_RT_INT1_INT_VBUS_FRS_LOW		BIT(7)
-#define RT1718S_RT_INT1_INT_RX_FRS			BIT(6)
-#define RT1718S_RT_INT2					0x99
-#define RT1718S_RT_INT6					0x9D
-#define RT1718S_RT_INT6_INT_BC12_SNK_DONE		BIT(7)
-#define RT1718S_RT_INT6_INT_HVDCP_CHK_DONE		BIT(6)
-#define RT1718S_RT_INT6_INT_BC12_TA_CHG			BIT(5)
-#define RT1718S_RT_INT6_INT_ADC_DONE			BIT(0)
-
-#define RT1718S_RT_ST6					0xA4
-#define RT1718S_RT_ST6_BC12_SNK_DONE			BIT(7)
-#define RT1718S_RT_ST6_HVDCP_CHK_DONE			BIT(6)
-#define RT1718S_RT_ST6_BC12_TA_CHG			BIT(5)
-
-#define RT1718S_PHYCTRL9				0xAC
-
-#define RT1718S_SYS_CTRL3				0xB0
-#define RT1718S_TCPC_CTRL1				0xB1
-#define RT1718S_TCPC_CTRL2				0xB2
-#define RT1718S_TCPC_CTRL3				0xB3
-#define RT1718S_SWRESET_MASK				BIT(0)
-#define RT1718S_TCPC_CTRL4				0xB4
-#define RT1718S_SYS_CTRL4				0xB8
-#define RT1718S_WATCHDOG_CTRL				0xBE
-#define RT1718S_I2C_RST_CTRL				0xBF
-
-#define RT1718S_HILO_CTRL9				0xC8
-#define RT1718S_SHILED_CTRL1				0xCA
-#define RT1718S_FRS_CTRL1				0xCB
-#define RT1718S_FRS_CTRL1_FRSWAPRX_MASK			0xF0
-#define RT1718S_FRS_CTRL2				0xCC
-#define RT1718S_FRS_CTRL2_RX_FRS_EN			BIT(6)
-#define RT1718S_FRS_CTRL2_FR_VBUS_SELECT		BIT(4)
-#define RT1718S_FRS_CTRL2_VBUS_FRS_EN			BIT(3)
-#define RT1718S_FRS_CTRL3				0xCE
-#define RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO2		BIT(3)
-#define RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO1		BIT(2)
-
-#define RT1718S_DIS_SRC_VBUS_CTRL			0xE0
-#define RT1718S_ENA_SRC_VBUS_CTRL			0xE1
-#define RT1718S_FAULT_OC1_VBUS_CTRL			0xE3
-#define RT1718S_GPIO1_VBUS_CTRL				0xEA
-#define RT1718S_GPIO1_VBUS_CTRL_FRS_RX_VBUS		BIT(6)
-#define RT1718S_GPIO2_VBUS_CTRL				0xEB
-#define RT1718S_GPIO2_VBUS_CTRL_FRS_RX_VBUS		BIT(6)
-#define RT1718S_VBUS_CTRL_EN				0xEC
-#define RT1718S_VBUS_CTRL_EN_GPIO2_VBUS_PATH_EN		BIT(7)
-#define RT1718S_VBUS_CTRL_EN_GPIO1_VBUS_PATH_EN		BIT(6)
-
-#define RT1718S_GPIO_CTRL(n)				(0xED + (n))
-#define RT1718S_GPIO_CTRL_PU				BIT(5)
-#define RT1718S_GPIO_CTRL_PD				BIT(4)
-#define RT1718S_GPIO_CTRL_OD_N				BIT(3)
-#define RT1718S_GPIO_CTRL_OE				BIT(2)
-#define RT1718S_GPIO_CTRL_O				BIT(1)
-#define RT1718S_GPIO_CTRL_I				BIT(0)
-
-#define RT1718S_UNLOCK_PW_2				0xF0
-#define RT1718S_UNLOCK_PW_1				0xF1
-
-#define RT1718S_RT2_SYS_CTRL5				0xF210
-
-#define RT1718S_VBUS_VOL_TO_REG(_vol)			(CLAMP(_vol, 5, 20) - 5)
-#define RT1718S_VBUS_PCT_TO_REG(_pct)			(CLAMP(_pct, 5, 20) \
-							/ 5 - 1)
-#define RT1718S_RT2_VBUS_VOL_CTRL			0xF213
-#define RT1718S_RT2_VBUS_VOL_CTRL_OVP_SEL		(BIT(5) | BIT(4))
-#define RT1718S_RT2_VBUS_VOL_CTRL_VOL_SEL		0x0F
-
-#define RT1718S_VCON_CTRL4				0xF211
-#define RT1718S_VCON_CTRL4_UVP_CP_EN			BIT(5)
-#define RT1718S_VCON_CTRL4_OCP_CP_EN			BIT(4)
-
-#define RT1718S_RT2_VBUS_OCRC_EN			0xF214
-#define RT1718S_RT2_VBUS_OCRC_EN_VBUS_OCP1_EN		BIT(0)
-#define RT1718S_RT2_VBUS_OCP_CTRL1			0xF216
-#define RT1718S_RT2_VBUS_OCP_CTRL4			0xF219
-
-#define RT1718S_RT2_SBU_CTRL_01				0xF23A
-#define RT1718S_RT2_SBU_CTRL_01_SBU_VIEN		BIT(7)
-#define RT1718S_RT2_SBU_CTRL_01_DPDM_VIEN		BIT(6)
-#define RT1718S_RT2_SBU_CTRL_01_SBU2_SWEN		BIT(3)
-#define RT1718S_RT2_SBU_CTRL_01_SBU1_SWEN		BIT(2)
-#define RT1718S_RT2_SBU_CTRL_01_DM_SWEN			BIT(1)
-#define RT1718S_RT2_SBU_CTRL_01_DP_SWEN			BIT(0)
-
-#define RT1718S_RT2_BC12_SNK_FUNC			0xF260
-#define RT1718S_RT2_BC12_SNK_FUNC_BC12_SNK_EN		BIT(7)
-#define RT1718S_RT2_BC12_SNK_FUNC_SPEC_TA_EN		BIT(6)
-#define RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_MASK		0x30
-#define RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_DISABLE	0x00
-#define RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_300MS	0x10
-#define RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_600MS	0x20
-#define RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_WAIT_DATA	0x30
-#define RT1718S_RT2_BC12_SNK_FUNC_VLGC_OPT		BIT(3)
-#define RT1718S_RT2_BC12_SNK_FUNC_VPORT_SEL		BIT(2)
-#define RT1718S_RT2_BC12_SNK_FUNC_BC12_WAIT_VBUS	BIT(1)
-
-#define RT1718S_RT2_BC12_STAT				0xF261
-#define RT1718S_RT2_BC12_STAT_DCDT			BIT(4)
-#define RT1718S_RT2_BC12_STAT_PORT_STATUS_MASK		0x0F
-#define RT1718S_RT2_BC12_STAT_PORT_STATUS_NONE		0x00
-#define RT1718S_RT2_BC12_STAT_PORT_STATUS_SDP		0x0D
-#define RT1718S_RT2_BC12_STAT_PORT_STATUS_CDP		0x0E
-#define RT1718S_RT2_BC12_STAT_PORT_STATUS_DCP		0x0F
-
-
-#define RT1718S_RT2_DPDM_CTR1_DPDM_SET			0xF263
-#define RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_MASK	0x03
-#define RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_0_55V	0x00
-#define RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_0_60V	0x01
-#define RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_0_65V	0x02
-#define RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_0_70V	0x03
-
-#define RT1718S_RT2_BC12_SRC_FUNC			0xF26D
-#define RT1718S_RT2_BC12_SRC_FUNC_BC12_SRC_EN		BIT(7)
-#define RT1718S_RT2_BC12_SRC_FUNC_SRC_MODE_SEL_MASK	0x70
-#define RT1718S_RT2_BC12_SRC_FUNC_SRC_MODE_SEL_BC12_SDP	0x00
-#define RT1718S_RT2_BC12_SRC_FUNC_SRC_MODE_SEL_BC12_CDP	0x10
-#define RT1718S_RT2_BC12_SRC_FUNC_SRC_MODE_SEL_BC12_DCP	0x20
-#define RT1718S_RT2_BC12_SRC_FUNC_WAIT_VBUS_ON		BIT(0)
-
-#define RT1718S_ADC_CTRL_01				0xF2A0
-#define RT1718S_ADC_CTRL_02				0xF2A1
-#define RT1718S_ADC_CHX_VOL_L(ch)			(0xF2A6 + (ch) * 2)
-#define RT1718S_ADC_CHX_VOL_H(ch)			(0xF2A7 + (ch) * 2)
-
-extern const struct tcpm_drv rt1718s_tcpm_drv;
-extern const struct bc12_drv rt1718s_bc12_drv;
+#define RT1718S_PHYCTRL1 0x80
+#define RT1718S_PHYCTRL2 0x81
+#define RT1718S_PHYCTRL3 0x82
+#define RT1718S_PHYCTRL7 0x86
+#define RT1718S_VCON_CTRL1 0x8A
+#define RT1718S_VCON_CTRL3 0x8C
+#define RT1718S_VCON_LIMIT_MODE BIT(0)
+#define RT1718S_SYS_CTRL1 0x8F
+#define RT1718S_SYS_CTRL1_TCPC_CONN_INVALID BIT(6)
+#define RT1718S_SYS_CTRL1_SHIPPING_OFF BIT(5)
+#define RT1718S_SYS_CTRL2 0x90
+#define RT1718S_SYS_CTRL2_BMCIO_OSC_EN BIT(0)
+#define RT1718S_SYS_CTRL2_LPWR_EN BIT(3)
+
+#define RT1718S_VCONN_CONTROL_2 0x8B
+#define RT1718S_VCONN_CONTROL_2_OVP_EN_CC1 BIT(7)
+#define RT1718S_VCONN_CONTROL_2_OVP_EN_CC2 BIT(6)
+#define RT1718S_VCONN_CONTROL_2_RVP_EN BIT(3)
+#define RT1718S_VCONN_CONTROL_3 0x8C
+#define RT1718S_VCONN_CONTROL_3_VCONN_OCP_SEL GENMASK(7, 5)
+#define RT1718S_VCONN_CONTROL_3_VCONN_OVP_DEG BIT(1)
+
+#define RT1718S_SYS_CTRL2 0x90
+#define RT1718S_SYS_CTRL2_VCONN_DISCHARGE_EN BIT(5)
+
+#define RT1718S_RT_MASK1 0x91
+#define RT1718S_RT_MASK1_M_VBUS_FRS_LOW BIT(7)
+#define RT1718S_RT_MASK1_M_RX_FRS BIT(6)
+#define RT1718S_RT_MASK2 0x92
+#define RT1718S_RT_MASK3 0x93
+#define RT1718S_RT_MASK4 0x94
+#define RT1718S_RT_MASK5 0x95
+#define RT1718S_RT_MASK6 0x96
+#define RT1718S_RT_MASK6_M_BC12_SNK_DONE BIT(7)
+#define RT1718S_RT_MASK6_M_HVDCP_CHK_DONE BIT(6)
+#define RT1718S_RT_MASK6_M_BC12_TA_CHG BIT(5)
+#define RT1718S_RT_MASK7 0x97
+
+#define RT1718S_RT_INT1 0x98
+#define RT1718S_RT_INT1_INT_VBUS_FRS_LOW BIT(7)
+#define RT1718S_RT_INT1_INT_RX_FRS BIT(6)
+#define RT1718S_RT_INT2 0x99
+#define RT1718S_RT_INT6 0x9D
+#define RT1718S_RT_INT6_INT_BC12_SNK_DONE BIT(7)
+#define RT1718S_RT_INT6_INT_HVDCP_CHK_DONE BIT(6)
+#define RT1718S_RT_INT6_INT_BC12_TA_CHG BIT(5)
+#define RT1718S_RT_INT6_INT_ADC_DONE BIT(0)
+
+#define RT1718S_RT_ST6 0xA4
+#define RT1718S_RT_ST6_BC12_SNK_DONE BIT(7)
+#define RT1718S_RT_ST6_HVDCP_CHK_DONE BIT(6)
+#define RT1718S_RT_ST6_BC12_TA_CHG BIT(5)
+
+#define RT1718S_PHYCTRL9 0xAC
+
+#define RT1718S_SYS_CTRL3 0xB0
+#define RT1718S_TCPC_CTRL1 0xB1
+#define RT1718S_TCPC_CTRL2 0xB2
+#define RT1718S_TCPC_CTRL3 0xB3
+#define RT1718S_SWRESET_MASK BIT(0)
+#define RT1718S_TCPC_CTRL4 0xB4
+#define RT1718S_SYS_CTRL4 0xB8
+#define RT1718S_WATCHDOG_CTRL 0xBE
+#define RT1718S_I2C_RST_CTRL 0xBF
+
+#define RT1718S_HILO_CTRL9 0xC8
+#define RT1718S_SHILED_CTRL1 0xCA
+#define RT1718S_FRS_CTRL1 0xCB
+#define RT1718S_FRS_CTRL1_FRSWAPRX_MASK 0xF0
+#define RT1718S_FRS_CTRL2 0xCC
+#define RT1718S_FRS_CTRL2_RX_FRS_EN BIT(6)
+#define RT1718S_FRS_CTRL2_FR_VBUS_SELECT BIT(4)
+#define RT1718S_FRS_CTRL2_VBUS_FRS_EN BIT(3)
+#define RT1718S_FRS_CTRL3 0xCE
+#define RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO2 BIT(3)
+#define RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO1 BIT(2)
+
+#define RT1718S_DIS_SRC_VBUS_CTRL 0xE0
+#define RT1718S_ENA_SRC_VBUS_CTRL 0xE1
+#define RT1718S_FAULT_OC1_VBUS_CTRL 0xE3
+#define RT1718S_GPIO1_VBUS_CTRL 0xEA
+#define RT1718S_GPIO1_VBUS_CTRL_FRS_RX_VBUS BIT(6)
+#define RT1718S_GPIO2_VBUS_CTRL 0xEB
+#define RT1718S_GPIO2_VBUS_CTRL_FRS_RX_VBUS BIT(6)
+#define RT1718S_VBUS_CTRL_EN 0xEC
+#define RT1718S_VBUS_CTRL_EN_GPIO2_VBUS_PATH_EN BIT(7)
+#define RT1718S_VBUS_CTRL_EN_GPIO1_VBUS_PATH_EN BIT(6)
+
+#define RT1718S_GPIO_CTRL(n) (0xED + (n))
+#define RT1718S_GPIO_CTRL_PU BIT(5)
+#define RT1718S_GPIO_CTRL_PD BIT(4)
+#define RT1718S_GPIO_CTRL_OD_N BIT(3)
+#define RT1718S_GPIO_CTRL_OE BIT(2)
+#define RT1718S_GPIO_CTRL_O BIT(1)
+#define RT1718S_GPIO_CTRL_I BIT(0)
+
+#define RT1718S_UNLOCK_PW_2 0xF0
+#define RT1718S_UNLOCK_PW_1 0xF1
+
+#define RT1718S_RT2_SYS_CTRL5 0xF210
+
+#define RT1718S_VBUS_VOL_TO_REG(_vol) (CLAMP(_vol, 5, 20) - 5)
+#define RT1718S_VBUS_PCT_TO_REG(_pct) (CLAMP(_pct, 5, 20) / 5 - 1)
+#define RT1718S_RT2_VBUS_VOL_CTRL 0xF213
+#define RT1718S_RT2_VBUS_VOL_CTRL_OVP_SEL (BIT(5) | BIT(4))
+#define RT1718S_RT2_VBUS_VOL_CTRL_VOL_SEL 0x0F
+
+#define RT1718S_VCON_CTRL4 0xF211
+#define RT1718S_VCON_CTRL4_UVP_CP_EN BIT(5)
+#define RT1718S_VCON_CTRL4_OCP_CP_EN BIT(4)
+
+#define RT1718S_RT2_VBUS_OCRC_EN 0xF214
+#define RT1718S_RT2_VBUS_OCRC_EN_VBUS_OCP1_EN BIT(0)
+#define RT1718S_RT2_VBUS_OCP_CTRL1 0xF216
+#define RT1718S_RT2_VBUS_OCP_CTRL4 0xF219
+
+#define RT1718S_RT2_SBU_CTRL_01 0xF23A
+#define RT1718S_RT2_SBU_CTRL_01_SBU_VIEN BIT(7)
+#define RT1718S_RT2_SBU_CTRL_01_DPDM_VIEN BIT(6)
+#define RT1718S_RT2_SBU_CTRL_01_SBU2_SWEN BIT(3)
+#define RT1718S_RT2_SBU_CTRL_01_SBU1_SWEN BIT(2)
+#define RT1718S_RT2_SBU_CTRL_01_DM_SWEN BIT(1)
+#define RT1718S_RT2_SBU_CTRL_01_DP_SWEN BIT(0)
+
+#define RT1718S_RT2_BC12_SNK_FUNC 0xF260
+#define RT1718S_RT2_BC12_SNK_FUNC_BC12_SNK_EN BIT(7)
+#define RT1718S_RT2_BC12_SNK_FUNC_SPEC_TA_EN BIT(6)
+#define RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_MASK 0x30
+#define RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_DISABLE 0x00
+#define RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_300MS 0x10
+#define RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_600MS 0x20
+#define RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_WAIT_DATA 0x30
+#define RT1718S_RT2_BC12_SNK_FUNC_VLGC_OPT BIT(3)
+#define RT1718S_RT2_BC12_SNK_FUNC_VPORT_SEL BIT(2)
+#define RT1718S_RT2_BC12_SNK_FUNC_BC12_WAIT_VBUS BIT(1)
+
+#define RT1718S_RT2_BC12_STAT 0xF261
+#define RT1718S_RT2_BC12_STAT_DCDT BIT(4)
+#define RT1718S_RT2_BC12_STAT_PORT_STATUS_MASK 0x0F
+#define RT1718S_RT2_BC12_STAT_PORT_STATUS_NONE 0x00
+#define RT1718S_RT2_BC12_STAT_PORT_STATUS_SDP 0x0D
+#define RT1718S_RT2_BC12_STAT_PORT_STATUS_CDP 0x0E
+#define RT1718S_RT2_BC12_STAT_PORT_STATUS_DCP 0x0F
+
+#define RT1718S_RT2_DPDM_CTR1_DPDM_SET 0xF263
+#define RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_MASK 0x03
+#define RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_0_55V 0x00
+#define RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_0_60V 0x01
+#define RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_0_65V 0x02
+#define RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_0_70V 0x03
+
+#define RT1718S_RT2_BC12_SRC_FUNC 0xF26D
+#define RT1718S_RT2_BC12_SRC_FUNC_BC12_SRC_EN BIT(7)
+#define RT1718S_RT2_BC12_SRC_FUNC_SRC_MODE_SEL_MASK 0x70
+#define RT1718S_RT2_BC12_SRC_FUNC_SRC_MODE_SEL_BC12_SDP 0x00
+#define RT1718S_RT2_BC12_SRC_FUNC_SRC_MODE_SEL_BC12_CDP 0x10
+#define RT1718S_RT2_BC12_SRC_FUNC_SRC_MODE_SEL_BC12_DCP 0x20
+#define RT1718S_RT2_BC12_SRC_FUNC_WAIT_VBUS_ON BIT(0)
+
+#define RT1718S_ADC_CTRL_01 0xF2A0
+#define RT1718S_ADC_CTRL_02 0xF2A1
+#define RT1718S_ADC_CHX_VOL_L(ch) (0xF2A6 + (ch)*2)
+#define RT1718S_ADC_CHX_VOL_H(ch) (0xF2A7 + (ch)*2)
 
 int rt1718s_write8(int port, int reg, int val);
 int rt1718s_read8(int port, int reg, int *val);
@@ -256,7 +242,6 @@ int rt1718s_gpio_get_level(int port, enum rt1718s_gpio signal);
  */
 int rt1718s_set_frs_enable(int port, int enable);
 
-
 /**
  * Board override for fast role swap.
  *
diff --git a/driver/tcpm/stm32gx.c b/driver/tcpm/stm32gx.c
index 359c7c1108..77a436b2ac 100644
--- a/driver/tcpm/stm32gx.c
+++ b/driver/tcpm/stm32gx.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -30,8 +30,8 @@
 #error "Unsupported config options of Stm32gx PD driver"
 #endif
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 /* Wait time for vconn power switch to turn off. */
 #ifndef PD_STM32GX_VCONN_TURN_OFF_DELAY_US
@@ -40,7 +40,6 @@
 
 static int cached_rp[CONFIG_USB_PD_PORT_MAX_COUNT];
 
-
 static int stm32gx_tcpm_get_message_raw(int port, uint32_t *buf, int *head)
 {
 	return stm32gx_ucpd_get_message_raw(port, buf, head);
@@ -57,7 +56,7 @@ static int stm32gx_tcpm_release(int port)
 }
 
 static int stm32gx_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2)
+			       enum tcpc_cc_voltage_status *cc2)
 {
 	/* Get cc_state value for each CC line */
 	stm32gx_ucpd_get_cc(port, cc1, cc2);
@@ -102,10 +101,8 @@ static int stm32gx_tcpm_set_rx_enable(int port, int enable)
 	return stm32gx_ucpd_set_rx_enable(port, enable);
 }
 
-static int stm32gx_tcpm_transmit(int port,
-			enum tcpci_msg_type type,
-			uint16_t header,
-			const uint32_t *data)
+static int stm32gx_tcpm_transmit(int port, enum tcpci_msg_type type,
+				 uint16_t header, const uint32_t *data)
 {
 	return stm32gx_ucpd_transmit(port, type, header, data);
 }
@@ -115,9 +112,9 @@ static int stm32gx_tcpm_sop_prime_enable(int port, bool enable)
 	return stm32gx_ucpd_sop_prime_enable(port, enable);
 }
 
-
-static int stm32gx_tcpm_get_chip_info(int port, int live,
-			struct ec_response_pd_chip_info_v1 *chip_info)
+static int
+stm32gx_tcpm_get_chip_info(int port, int live,
+			   struct ec_response_pd_chip_info_v1 *chip_info)
 {
 	return stm32gx_ucpd_get_chip_info(port, live, chip_info);
 }
@@ -147,7 +144,7 @@ static int stm32gx_tcpm_reset_bist_type_2(int port)
 }
 
 enum ec_error_list stm32gx_tcpm_set_bist_test_mode(const int port,
-		const bool enable)
+						   const bool enable)
 {
 	return stm32gx_ucpd_set_bist_test_mode(port, enable);
 }
@@ -165,22 +162,22 @@ bool stm32gx_tcpm_check_vbus_level(int port, enum vbus_level level)
 }
 
 const struct tcpm_drv stm32gx_tcpm_drv = {
-	.init			= &stm32gx_tcpm_init,
-	.release		= &stm32gx_tcpm_release,
-	.get_cc			= &stm32gx_tcpm_get_cc,
-	.check_vbus_level	= &stm32gx_tcpm_check_vbus_level,
-	.select_rp_value	= &stm32gx_tcpm_select_rp_value,
-	.set_cc			= &stm32gx_tcpm_set_cc,
-	.set_polarity		= &stm32gx_tcpm_set_polarity,
+	.init = &stm32gx_tcpm_init,
+	.release = &stm32gx_tcpm_release,
+	.get_cc = &stm32gx_tcpm_get_cc,
+	.check_vbus_level = &stm32gx_tcpm_check_vbus_level,
+	.select_rp_value = &stm32gx_tcpm_select_rp_value,
+	.set_cc = &stm32gx_tcpm_set_cc,
+	.set_polarity = &stm32gx_tcpm_set_polarity,
 #ifdef CONFIG_USB_PD_DECODE_SOP
-	.sop_prime_enable      = &stm32gx_tcpm_sop_prime_enable,
+	.sop_prime_enable = &stm32gx_tcpm_sop_prime_enable,
 #endif
-	.set_vconn		= &stm32gx_tcpm_set_vconn,
-	.set_msg_header		= &stm32gx_tcpm_set_msg_header,
-	.set_rx_enable		= &stm32gx_tcpm_set_rx_enable,
-	.get_message_raw	= &stm32gx_tcpm_get_message_raw,
-	.transmit		= &stm32gx_tcpm_transmit,
-	.get_chip_info		= &stm32gx_tcpm_get_chip_info,
-	.reset_bist_type_2	= &stm32gx_tcpm_reset_bist_type_2,
-	.set_bist_test_mode	= &stm32gx_tcpm_set_bist_test_mode,
+	.set_vconn = &stm32gx_tcpm_set_vconn,
+	.set_msg_header = &stm32gx_tcpm_set_msg_header,
+	.set_rx_enable = &stm32gx_tcpm_set_rx_enable,
+	.get_message_raw = &stm32gx_tcpm_get_message_raw,
+	.transmit = &stm32gx_tcpm_transmit,
+	.get_chip_info = &stm32gx_tcpm_get_chip_info,
+	.reset_bist_type_2 = &stm32gx_tcpm_reset_bist_type_2,
+	.set_bist_test_mode = &stm32gx_tcpm_set_bist_test_mode,
 };
diff --git a/driver/tcpm/stm32gx.h b/driver/tcpm/stm32gx.h
index de6a803d52..a8a1e1a1be 100644
--- a/driver/tcpm/stm32gx.h
+++ b/driver/tcpm/stm32gx.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,8 +7,6 @@
 #ifndef __CROS_EC_DRIVER_TCPM_STM32GX_H
 #define __CROS_EC_DRIVER_TCPM_STM32GX_H
 
-
 extern const struct tcpm_drv stm32gx_tcpm_drv;
 
-
 #endif /* __CROS_EC_DRIVER_TCPM_STM32GX_H */
diff --git a/driver/tcpm/stub.c b/driver/tcpm/stub.c
index 863a88c044..b28d436b51 100644
--- a/driver/tcpm/stub.c
+++ b/driver/tcpm/stub.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,8 +22,8 @@ static int init_alert_mask(int port)
 	 * signal the TCPM via the Alert# gpio line.
 	 */
 	mask = TCPC_REG_ALERT_TX_SUCCESS | TCPC_REG_ALERT_TX_FAILED |
-		TCPC_REG_ALERT_TX_DISCARDED | TCPC_REG_ALERT_RX_STATUS |
-		TCPC_REG_ALERT_RX_HARD_RST | TCPC_REG_ALERT_CC_STATUS;
+	       TCPC_REG_ALERT_TX_DISCARDED | TCPC_REG_ALERT_RX_STATUS |
+	       TCPC_REG_ALERT_RX_HARD_RST | TCPC_REG_ALERT_CC_STATUS;
 	/* Set the alert mask in TCPC */
 	rv = tcpc_alert_mask_set(port, mask);
 
@@ -48,7 +48,7 @@ int tcpm_init(int port)
 }
 
 int tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2)
+		enum tcpc_cc_voltage_status *cc2)
 {
 	return tcpc_get_cc(port, cc1, cc2);
 }
@@ -153,7 +153,7 @@ void tcpc_alert(int port)
 	if (status & TCPC_REG_ALERT_TX_COMPLETE) {
 		/* transmit complete */
 		pd_transmit_complete(port, status & TCPC_REG_ALERT_TX_SUCCESS ?
-					   TCPC_TX_COMPLETE_SUCCESS :
-					   TCPC_TX_COMPLETE_FAILED);
+						   TCPC_TX_COMPLETE_SUCCESS :
+						   TCPC_TX_COMPLETE_FAILED);
 	}
 }
diff --git a/driver/tcpm/tcpci.c b/driver/tcpm/tcpci.c
index a55db12e1c..daa289c743 100644
--- a/driver/tcpm/tcpci.c
+++ b/driver/tcpm/tcpci.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,17 +26,17 @@
 #include "usb_pd_tcpm.h"
 #include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
 
 STATIC_IF(CONFIG_USB_PD_DECODE_SOP)
-	bool sop_prime_en[CONFIG_USB_PD_PORT_MAX_COUNT];
+bool sop_prime_en[CONFIG_USB_PD_PORT_MAX_COUNT];
 STATIC_IF(CONFIG_USB_PD_DECODE_SOP)
-	int rx_en[CONFIG_USB_PD_PORT_MAX_COUNT];
+int rx_en[CONFIG_USB_PD_PORT_MAX_COUNT];
 
-#define TCPC_FLAGS_VSAFE0V(_flags) \
+#define TCPC_FLAGS_VSAFE0V(_flags)             \
 	((_flags & TCPC_FLAGS_TCPCI_REV2_0) && \
-		!(_flags & TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V))
+	 !(_flags & TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V))
 
 /****************************************************************************
  * TCPCI DEBUG Helpers
@@ -57,7 +57,7 @@ struct i2c_wrt_op {
 	int mask;
 };
 STATIC_IF(DEBUG_I2C_FAULT_LAST_WRITE_OP)
-	struct i2c_wrt_op last_write_op[CONFIG_USB_PD_PORT_MAX_COUNT];
+struct i2c_wrt_op last_write_op[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 /*
  * AutoDischargeDisconnect has caused a number of issues with the
@@ -90,7 +90,7 @@ struct get_cc_values {
 	int role;
 };
 STATIC_IF(DEBUG_GET_CC)
-	struct get_cc_values last_get_cc[CONFIG_USB_PD_PORT_MAX_COUNT];
+struct get_cc_values last_get_cc[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 /*
  * Seeing RoleCtrl updates can help determine why GetCC is not
@@ -130,13 +130,12 @@ int tcpc_addr_write(int port, int i2c_addr, int reg, int val)
 
 	if (IS_ENABLED(DEBUG_I2C_FAULT_LAST_WRITE_OP)) {
 		last_write_op[port].addr = i2c_addr;
-		last_write_op[port].reg  = reg;
-		last_write_op[port].val  = val & 0xFF;
+		last_write_op[port].reg = reg;
+		last_write_op[port].val = val & 0xFF;
 		last_write_op[port].mask = 0;
 	}
 
-	rv = i2c_write8(tcpc_config[port].i2c_info.port,
-			i2c_addr, reg, val);
+	rv = i2c_write8(tcpc_config[port].i2c_info.port, i2c_addr, reg, val);
 
 	pd_device_accessed(port);
 	return rv;
@@ -150,13 +149,12 @@ int tcpc_addr_write16(int port, int i2c_addr, int reg, int val)
 
 	if (IS_ENABLED(DEBUG_I2C_FAULT_LAST_WRITE_OP)) {
 		last_write_op[port].addr = i2c_addr;
-		last_write_op[port].reg  = reg;
-		last_write_op[port].val  = val & 0xFFFF;
+		last_write_op[port].reg = reg;
+		last_write_op[port].val = val & 0xFFFF;
 		last_write_op[port].mask = 0;
 	}
 
-	rv = i2c_write16(tcpc_config[port].i2c_info.port,
-			 i2c_addr, reg, val);
+	rv = i2c_write16(tcpc_config[port].i2c_info.port, i2c_addr, reg, val);
 
 	pd_device_accessed(port);
 	return rv;
@@ -168,8 +166,7 @@ int tcpc_addr_read(int port, int i2c_addr, int reg, int *val)
 
 	pd_wait_exit_low_power(port);
 
-	rv = i2c_read8(tcpc_config[port].i2c_info.port,
-		       i2c_addr, reg, val);
+	rv = i2c_read8(tcpc_config[port].i2c_info.port, i2c_addr, reg, val);
 
 	pd_device_accessed(port);
 	return rv;
@@ -186,8 +183,7 @@ int tcpc_addr_read16_no_lpm_exit(int port, int i2c_addr, int reg, int *val)
 {
 	int rv;
 
-	rv = i2c_read16(tcpc_config[port].i2c_info.port,
-			i2c_addr, reg, val);
+	rv = i2c_read16(tcpc_config[port].i2c_info.port, i2c_addr, reg, val);
 
 	pd_device_accessed(port);
 	return rv;
@@ -200,8 +196,8 @@ int tcpc_read_block(int port, int reg, uint8_t *in, int size)
 	pd_wait_exit_low_power(port);
 
 	rv = i2c_read_block(tcpc_config[port].i2c_info.port,
-			    tcpc_config[port].i2c_info.addr_flags,
-			    reg, in, size);
+			    tcpc_config[port].i2c_info.addr_flags, reg, in,
+			    size);
 
 	pd_device_accessed(port);
 	return rv;
@@ -214,15 +210,15 @@ int tcpc_write_block(int port, int reg, const uint8_t *out, int size)
 	pd_wait_exit_low_power(port);
 
 	rv = i2c_write_block(tcpc_config[port].i2c_info.port,
-			     tcpc_config[port].i2c_info.addr_flags,
-			     reg, out, size);
+			     tcpc_config[port].i2c_info.addr_flags, reg, out,
+			     size);
 
 	pd_device_accessed(port);
 	return rv;
 }
 
-int tcpc_xfer(int port, const uint8_t *out, int out_size,
-			uint8_t *in, int in_size)
+int tcpc_xfer(int port, const uint8_t *out, int out_size, uint8_t *in,
+	      int in_size)
 {
 	int rv;
 	/* Dispatching to tcpc_xfer_unlocked reduces code size growth. */
@@ -233,23 +229,22 @@ int tcpc_xfer(int port, const uint8_t *out, int out_size,
 	return rv;
 }
 
-int tcpc_xfer_unlocked(int port, const uint8_t *out, int out_size,
-			    uint8_t *in, int in_size, int flags)
+int tcpc_xfer_unlocked(int port, const uint8_t *out, int out_size, uint8_t *in,
+		       int in_size, int flags)
 {
 	int rv;
 
 	pd_wait_exit_low_power(port);
 
 	rv = i2c_xfer_unlocked(tcpc_config[port].i2c_info.port,
-			       tcpc_config[port].i2c_info.addr_flags,
-			       out, out_size, in, in_size, flags);
+			       tcpc_config[port].i2c_info.addr_flags, out,
+			       out_size, in, in_size, flags);
 
 	pd_device_accessed(port);
 	return rv;
 }
 
-int tcpc_update8(int port, int reg,
-		 uint8_t mask,
+int tcpc_update8(int port, int reg, uint8_t mask,
 		 enum mask_update_action action)
 {
 	int rv;
@@ -259,20 +254,19 @@ int tcpc_update8(int port, int reg,
 
 	if (IS_ENABLED(DEBUG_I2C_FAULT_LAST_WRITE_OP)) {
 		last_write_op[port].addr = i2c_addr;
-		last_write_op[port].reg  = reg;
-		last_write_op[port].val  = 0;
+		last_write_op[port].reg = reg;
+		last_write_op[port].val = 0;
 		last_write_op[port].mask = (mask & 0xFF) | (action << 16);
 	}
 
-	rv = i2c_update8(tcpc_config[port].i2c_info.port,
-			 i2c_addr, reg, mask, action);
+	rv = i2c_update8(tcpc_config[port].i2c_info.port, i2c_addr, reg, mask,
+			 action);
 
 	pd_device_accessed(port);
 	return rv;
 }
 
-int tcpc_update16(int port, int reg,
-		  uint16_t mask,
+int tcpc_update16(int port, int reg, uint16_t mask,
 		  enum mask_update_action action)
 {
 	int rv;
@@ -282,13 +276,13 @@ int tcpc_update16(int port, int reg,
 
 	if (IS_ENABLED(DEBUG_I2C_FAULT_LAST_WRITE_OP)) {
 		last_write_op[port].addr = i2c_addr;
-		last_write_op[port].reg  = reg;
-		last_write_op[port].val  = 0;
+		last_write_op[port].reg = reg;
+		last_write_op[port].val = 0;
 		last_write_op[port].mask = (mask & 0xFFFF) | (action << 16);
 	}
 
-	rv = i2c_update16(tcpc_config[port].i2c_info.port,
-			  i2c_addr, reg, mask, action);
+	rv = i2c_update16(tcpc_config[port].i2c_info.port, i2c_addr, reg, mask,
+			  action);
 
 	pd_device_accessed(port);
 	return rv;
@@ -324,17 +318,14 @@ static int init_alert_mask(int port)
 	 */
 	if (get_usb_pd_vbus_detect() == USB_PD_VBUS_DETECT_TCPC) {
 		mask = TCPC_REG_ALERT_TX_SUCCESS | TCPC_REG_ALERT_TX_FAILED |
-			TCPC_REG_ALERT_TX_DISCARDED | TCPC_REG_ALERT_RX_STATUS |
-			TCPC_REG_ALERT_RX_HARD_RST | TCPC_REG_ALERT_CC_STATUS |
-			TCPC_REG_ALERT_FAULT
-			| TCPC_REG_ALERT_POWER_STATUS
-			;
+		       TCPC_REG_ALERT_TX_DISCARDED | TCPC_REG_ALERT_RX_STATUS |
+		       TCPC_REG_ALERT_RX_HARD_RST | TCPC_REG_ALERT_CC_STATUS |
+		       TCPC_REG_ALERT_FAULT | TCPC_REG_ALERT_POWER_STATUS;
 	} else {
 		mask = TCPC_REG_ALERT_TX_SUCCESS | TCPC_REG_ALERT_TX_FAILED |
-			TCPC_REG_ALERT_TX_DISCARDED | TCPC_REG_ALERT_RX_STATUS |
-			TCPC_REG_ALERT_RX_HARD_RST | TCPC_REG_ALERT_CC_STATUS |
-			TCPC_REG_ALERT_FAULT
-			;
+		       TCPC_REG_ALERT_TX_DISCARDED | TCPC_REG_ALERT_RX_STATUS |
+		       TCPC_REG_ALERT_RX_HARD_RST | TCPC_REG_ALERT_CC_STATUS |
+		       TCPC_REG_ALERT_FAULT;
 	}
 
 	/* TCPCI Rev2 includes SAFE0V alerts */
@@ -373,7 +364,7 @@ static int init_power_status_mask(int port)
 	else
 		mask = 0;
 
-	rv = tcpc_write(port, TCPC_REG_POWER_STATUS_MASK , mask);
+	rv = tcpc_write(port, TCPC_REG_POWER_STATUS_MASK, mask);
 
 	return rv;
 }
@@ -399,11 +390,10 @@ int tcpci_tcpm_select_rp_value(int port, int rp)
 void tcpci_tcpc_discharge_vbus(int port, int enable)
 {
 	if (IS_ENABLED(DEBUG_FORCED_DISCHARGE))
-		CPRINTS("C%d: ForceDischarge %sABLED",
-			port, enable ? "EN" : "DIS");
+		CPRINTS("C%d: ForceDischarge %sABLED", port,
+			enable ? "EN" : "DIS");
 
-	tcpc_update8(port,
-		     TCPC_REG_POWER_CTRL,
+	tcpc_update8(port, TCPC_REG_POWER_CTRL,
 		     TCPC_REG_POWER_CTRL_FORCE_DISCHARGE,
 		     (enable) ? MASK_SET : MASK_CLR);
 }
@@ -416,11 +406,10 @@ void tcpci_tcpc_discharge_vbus(int port, int enable)
 void tcpci_tcpc_enable_auto_discharge_disconnect(int port, int enable)
 {
 	if (IS_ENABLED(DEBUG_AUTO_DISCHARGE_DISCONNECT))
-		CPRINTS("C%d: AutoDischargeDisconnect %sABLED",
-			port, enable ? "EN" : "DIS");
+		CPRINTS("C%d: AutoDischargeDisconnect %sABLED", port,
+			enable ? "EN" : "DIS");
 
-	tcpc_update8(port,
-		     TCPC_REG_POWER_CTRL,
+	tcpc_update8(port, TCPC_REG_POWER_CTRL,
 		     TCPC_REG_POWER_CTRL_AUTO_DISCHARGE_DISCONNECT,
 		     (enable) ? MASK_SET : MASK_CLR);
 }
@@ -433,7 +422,7 @@ int tcpci_tcpc_debug_accessory(int port, bool enable)
 }
 
 int tcpci_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2)
+		      enum tcpc_cc_voltage_status *cc2)
 {
 	int role;
 	int status;
@@ -493,13 +482,11 @@ int tcpci_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
 	*cc2 |= cc2_present_rd << 2;
 
 	if (IS_ENABLED(DEBUG_GET_CC) &&
-	    (last_get_cc[port].cc1 != *cc1 ||
-	     last_get_cc[port].cc2 != *cc2 ||
+	    (last_get_cc[port].cc1 != *cc1 || last_get_cc[port].cc2 != *cc2 ||
 	     last_get_cc[port].cc_sts != status ||
 	     last_get_cc[port].role != role)) {
-
-		CPRINTS("C%d: GET_CC cc1=%d cc2=%d cc_sts=0x%X role=0x%X",
-			port, *cc1, *cc2, status, role);
+		CPRINTS("C%d: GET_CC cc1=%d cc2=%d cc_sts=0x%X role=0x%X", port,
+			*cc1, *cc2, status, role);
 
 		last_get_cc[port].cc1 = *cc1;
 		last_get_cc[port].cc2 = *cc2;
@@ -511,9 +498,8 @@ int tcpci_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
 
 int tcpci_tcpm_set_cc(int port, int pull)
 {
-	int role = TCPC_REG_ROLE_CTRL_SET(TYPEC_NO_DRP,
-					  tcpci_get_cached_rp(port),
-					  pull, pull);
+	int role = TCPC_REG_ROLE_CTRL_SET(
+		TYPEC_NO_DRP, tcpci_get_cached_rp(port), pull, pull);
 
 	if (IS_ENABLED(DEBUG_ROLE_CTRL_UPDATES))
 		CPRINTS("C%d: SET_CC pull=%d role=0x%X", port, pull, role);
@@ -523,7 +509,7 @@ int tcpci_tcpm_set_cc(int port, int pull)
 
 #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
 int tcpci_set_role_ctrl(int port, enum tcpc_drp drp, enum tcpc_rp_value rp,
-	enum tcpc_cc_pull pull)
+			enum tcpc_cc_pull pull)
 {
 	int role = TCPC_REG_ROLE_CTRL_SET(drp, rp, pull, pull);
 
@@ -552,16 +538,16 @@ int tcpci_tcpc_drp_toggle(int port)
 	 *
 	 * Set the Rp Value to be the minimal to save power
 	 */
-	pull = (tcpc_config[port].flags & TCPC_FLAGS_TCPCI_REV2_0)
-			? TYPEC_CC_RP : TYPEC_CC_RD;
+	pull = (tcpc_config[port].flags & TCPC_FLAGS_TCPCI_REV2_0) ?
+		       TYPEC_CC_RP :
+		       TYPEC_CC_RD;
 
 	rv = tcpci_set_role_ctrl(port, TYPEC_DRP, TYPEC_RP_USB, pull);
 	if (rv)
 		return rv;
 
 	/* Set up to catch LOOK4CONNECTION alerts */
-	rv = tcpc_update8(port,
-			  TCPC_REG_TCPC_CTRL,
+	rv = tcpc_update8(port, TCPC_REG_TCPC_CTRL,
 			  TCPC_REG_TCPC_CTRL_EN_LOOK4CONNECTION_ALERT,
 			  MASK_SET);
 	if (rv)
@@ -590,18 +576,15 @@ void tcpci_wake_low_power_mode(int port)
 	 * correctly support it
 	 */
 	i2c_write8(tcpc_config[port].i2c_info.port,
-		   tcpc_config[port].i2c_info.addr_flags,
-		   TCPC_REG_COMMAND, TCPC_REG_COMMAND_WAKE_I2C);
+		   tcpc_config[port].i2c_info.addr_flags, TCPC_REG_COMMAND,
+		   TCPC_REG_COMMAND_WAKE_I2C);
 }
 #endif
 
 int tcpci_tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity)
 {
-	return tcpc_update8(port,
-			    TCPC_REG_TCPC_CTRL,
-			    TCPC_REG_TCPC_CTRL_SET(1),
-			    polarity_rm_dts(polarity)
-					? MASK_SET : MASK_CLR);
+	return tcpc_update8(port, TCPC_REG_TCPC_CTRL, TCPC_REG_TCPC_CTRL_SET(1),
+			    polarity_rm_dts(polarity) ? MASK_SET : MASK_CLR);
 }
 
 bool tcpci_tcpm_get_snk_ctrl(int port)
@@ -611,14 +594,13 @@ bool tcpci_tcpm_get_snk_ctrl(int port)
 
 	rv = tcpci_tcpm_get_power_status(port, &pwr_sts);
 
-	return rv == EC_SUCCESS &&
-		pwr_sts & TCPC_REG_POWER_STATUS_SINKING_VBUS;
+	return rv == EC_SUCCESS && pwr_sts & TCPC_REG_POWER_STATUS_SINKING_VBUS;
 }
 
 int tcpci_tcpm_set_snk_ctrl(int port, int enable)
 {
 	int cmd = enable ? TCPC_REG_COMMAND_SNK_CTRL_HIGH :
-		TCPC_REG_COMMAND_SNK_CTRL_LOW;
+			   TCPC_REG_COMMAND_SNK_CTRL_LOW;
 
 	return tcpc_write(port, TCPC_REG_COMMAND, cmd);
 }
@@ -631,13 +613,13 @@ bool tcpci_tcpm_get_src_ctrl(int port)
 	rv = tcpci_tcpm_get_power_status(port, &pwr_sts);
 
 	return rv == EC_SUCCESS &&
-		pwr_sts & TCPC_REG_POWER_STATUS_SOURCING_VBUS;
+	       pwr_sts & TCPC_REG_POWER_STATUS_SOURCING_VBUS;
 }
 
 int tcpci_tcpm_set_src_ctrl(int port, int enable)
 {
 	int cmd = enable ? TCPC_REG_COMMAND_SRC_CTRL_HIGH :
-		TCPC_REG_COMMAND_SRC_CTRL_LOW;
+			   TCPC_REG_COMMAND_SRC_CTRL_LOW;
 
 	return tcpc_write(port, TCPC_REG_COMMAND, cmd);
 }
@@ -708,12 +690,11 @@ int tcpci_tcpm_set_rx_enable(int port, int enable)
 		rx_en[port] = enable;
 	}
 
-
 	if (enable) {
 		detect_sop_en = TCPC_REG_RX_DETECT_SOP_HRST_MASK;
 
 		if (IS_ENABLED(CONFIG_USB_PD_DECODE_SOP) &&
-			sop_prime_en[port]) {
+		    sop_prime_en[port]) {
 			/*
 			 * Only the VCONN Source is allowed to communicate
 			 * with the Cable Plugs.
@@ -730,10 +711,9 @@ int tcpci_tcpm_set_rx_enable(int port, int enable)
 #ifdef CONFIG_USB_PD_FRS
 int tcpci_tcpc_fast_role_swap_enable(int port, int enable)
 {
-	return tcpc_update8(port,
-		     TCPC_REG_POWER_CTRL,
-		     TCPC_REG_POWER_CTRL_FRS_ENABLE,
-		     (enable) ? MASK_SET : MASK_CLR);
+	return tcpc_update8(port, TCPC_REG_POWER_CTRL,
+			    TCPC_REG_POWER_CTRL_FRS_ENABLE,
+			    (enable) ? MASK_SET : MASK_CLR);
 }
 #endif
 
@@ -788,7 +768,7 @@ static int tcpci_rev2_0_tcpm_get_message_raw(int port, uint32_t *payload,
 
 	/* The next two bytes are the header */
 	rv |= tcpc_xfer_unlocked(port, NULL, 0, (uint8_t *)head, 2,
-				cnt ? 0 : I2C_XFER_STOP);
+				 cnt ? 0 : I2C_XFER_STOP);
 
 	/* Encode message address in bits 31 to 28 */
 	*head &= 0x0000ffff;
@@ -953,11 +933,11 @@ void tcpm_clear_pending_messages(int port)
 	q->tail = q->head;
 }
 
-int tcpci_tcpm_transmit(int port, enum tcpci_msg_type type,
-			uint16_t header, const uint32_t *data)
+int tcpci_tcpm_transmit(int port, enum tcpci_msg_type type, uint16_t header,
+			const uint32_t *data)
 {
 	int reg = TCPC_REG_TX_DATA;
-	int rv, cnt = 4*PD_HEADER_CNT(header);
+	int rv, cnt = 4 * PD_HEADER_CNT(header);
 
 	/* If not SOP* transmission, just write to the transmit register */
 	if (type >= NUM_SOP_STAR_TYPES) {
@@ -966,7 +946,7 @@ int tcpci_tcpm_transmit(int port, enum tcpci_msg_type type,
 		 * should ignore retry field for these 3 types).
 		 */
 		return tcpc_write(port, TCPC_REG_TRANSMIT,
-			TCPC_REG_TRANSMIT_SET_WITHOUT_RETRY(type));
+				  TCPC_REG_TRANSMIT_SET_WITHOUT_RETRY(type));
 	}
 
 	if (tcpc_config[port].flags & TCPC_FLAGS_TCPCI_REV2_0) {
@@ -983,13 +963,14 @@ int tcpci_tcpm_transmit(int port, enum tcpci_msg_type type,
 		rv |= tcpc_xfer_unlocked(port, (uint8_t *)&cnt, 1, NULL, 0, 0);
 		if (cnt > sizeof(header)) {
 			rv |= tcpc_xfer_unlocked(port, (uint8_t *)&header,
-					 sizeof(header), NULL, 0, 0);
+						 sizeof(header), NULL, 0, 0);
 			rv |= tcpc_xfer_unlocked(port, (uint8_t *)data,
-					 cnt-sizeof(header), NULL, 0,
-					 I2C_XFER_STOP);
+						 cnt - sizeof(header), NULL, 0,
+						 I2C_XFER_STOP);
 		} else {
 			rv |= tcpc_xfer_unlocked(port, (uint8_t *)&header,
-					sizeof(header), NULL, 0, I2C_XFER_STOP);
+						 sizeof(header), NULL, 0,
+						 I2C_XFER_STOP);
 		}
 		tcpc_lock(port, 0);
 
@@ -1075,15 +1056,13 @@ static int tcpci_handle_fault(int port, int fault)
 	if (IS_ENABLED(DEBUG_I2C_FAULT_LAST_WRITE_OP) &&
 	    fault & TCPC_REG_FAULT_STATUS_I2C_INTERFACE_ERR) {
 		if (last_write_op[port].mask == 0)
-			CPRINTS("C%d I2C WR 0x%02X 0x%02X value=0x%X",
-				port,
+			CPRINTS("C%d I2C WR 0x%02X 0x%02X value=0x%X", port,
 				last_write_op[port].addr,
 				last_write_op[port].reg,
 				last_write_op[port].val);
 		else
 			CPRINTS("C%d I2C UP 0x%02X 0x%02X op=%d mask=0x%X",
-				port,
-				last_write_op[port].addr,
+				port, last_write_op[port].addr,
 				last_write_op[port].reg,
 				last_write_op[port].mask >> 16,
 				last_write_op[port].mask & 0xFFFF);
@@ -1091,8 +1070,8 @@ static int tcpci_handle_fault(int port, int fault)
 
 	/* Report overcurrent to the OCP module if enabled */
 	if ((dev_cap_1[port] & TCPC_REG_DEV_CAP_1_VBUS_OCP_REPORTING) &&
-			IS_ENABLED(CONFIG_USBC_OCP) &&
-			(fault & TCPC_REG_FAULT_STATUS_VBUS_OVER_CURRENT))
+	    IS_ENABLED(CONFIG_USBC_OCP) &&
+	    (fault & TCPC_REG_FAULT_STATUS_VBUS_OVER_CURRENT))
 		pd_handle_overcurrent(port);
 
 	if (tcpc_config[port].drv->handle_fault)
@@ -1101,16 +1080,41 @@ static int tcpci_handle_fault(int port, int fault)
 	return rv;
 }
 
-enum ec_error_list tcpci_set_bist_test_mode(const int port,
-		const bool enable)
+int tcpci_hard_reset_reinit(int port)
+{
+	int rv;
+
+	/* Initialize power_status_mask */
+	rv = init_power_status_mask(port);
+	/* Initialize alert_mask */
+	rv |= init_alert_mask(port);
+
+	CPRINTS("C%d: Hard Reset re-initialize %s", port,
+		rv ? "failed" : "success");
+
+	return rv;
+}
+
+enum ec_error_list tcpci_set_bist_test_mode(const int port, const bool enable)
 {
 	int rv;
 
 	rv = tcpc_update8(port, TCPC_REG_TCPC_CTRL,
-			TCPC_REG_TCPC_CTRL_BIST_TEST_MODE,
-			enable ? MASK_SET : MASK_CLR);
-	rv |= tcpc_update16(port, TCPC_REG_ALERT_MASK,
-			TCPC_REG_ALERT_RX_STATUS, enable ? MASK_CLR : MASK_SET);
+			  TCPC_REG_TCPC_CTRL_BIST_TEST_MODE,
+			  enable ? MASK_SET : MASK_CLR);
+	rv |= tcpc_update16(port, TCPC_REG_ALERT_MASK, TCPC_REG_ALERT_RX_STATUS,
+			    enable ? MASK_CLR : MASK_SET);
+	return rv;
+}
+
+enum ec_error_list tcpci_get_bist_test_mode(const int port, bool *enable)
+{
+	int rv;
+	int val;
+
+	rv = tcpc_read(port, TCPC_REG_TCPC_CTRL, &val);
+	*enable = !!(val & TCPC_REG_TCPC_CTRL_BIST_TEST_MODE);
+
 	return rv;
 }
 
@@ -1166,8 +1170,8 @@ static void tcpci_check_vbus_changed(int port, int alert, uint32_t *pd_event)
 		if ((get_usb_pd_vbus_detect() == USB_PD_VBUS_DETECT_TCPC) &&
 		    IS_ENABLED(CONFIG_USB_CHARGER)) {
 			/* Update charge manager with new VBUS state */
-			usb_charger_vbus_change(port,
-				!!(tcpc_vbus[port] & BIT(VBUS_PRESENT)));
+			usb_charger_vbus_change(port, !!(tcpc_vbus[port] &
+							 BIT(VBUS_PRESENT)));
 
 			if (pd_event)
 				*pd_event |= TASK_EVENT_WAKE;
@@ -1203,8 +1207,7 @@ void tcpci_tcpc_alert(int port)
 	if (alert & TCPC_REG_ALERT_FAULT) {
 		int fault;
 
-		if (tcpci_get_fault(port, &fault) == EC_SUCCESS &&
-		    fault != 0 &&
+		if (tcpci_get_fault(port, &fault) == EC_SUCCESS && fault != 0 &&
 		    tcpci_handle_fault(port, fault) == EC_SUCCESS &&
 		    tcpci_clear_fault(port, fault) == EC_SUCCESS)
 			CPRINTS("C%d FAULT 0x%02X handled", port, fault);
@@ -1217,8 +1220,8 @@ void tcpci_tcpc_alert(int port)
 	 */
 	if (alert & TCPC_REG_ALERT_TX_COMPLETE)
 		pd_transmit_complete(port, alert & TCPC_REG_ALERT_TX_SUCCESS ?
-					   TCPC_TX_COMPLETE_SUCCESS :
-					   TCPC_TX_COMPLETE_FAILED);
+						   TCPC_TX_COMPLETE_SUCCESS :
+						   TCPC_TX_COMPLETE_FAILED);
 
 	/* Pull all RX messages from TCPC into EC memory */
 	failed_attempts = 0;
@@ -1229,7 +1232,6 @@ void tcpci_tcpc_alert(int port)
 		if (tcpm_alert_status(port, &alert))
 			++failed_attempts;
 
-
 		/*
 		 * EC RX FIFO is full. Deassert ALERT# line to exit interrupt
 		 * handler by discarding pending message from TCPC RX FIFO.
@@ -1237,8 +1239,8 @@ void tcpci_tcpc_alert(int port)
 		if (retval == EC_ERROR_OVERFLOW) {
 			CPRINTS("C%d: PD RX OVF!", port);
 			tcpc_write16(port, TCPC_REG_ALERT,
-				TCPC_REG_ALERT_RX_STATUS |
-				TCPC_REG_ALERT_RX_BUF_OVF);
+				     TCPC_REG_ALERT_RX_STATUS |
+					     TCPC_REG_ALERT_RX_BUF_OVF);
 		}
 
 		/* Ensure we don't loop endlessly */
@@ -1294,6 +1296,9 @@ void tcpci_tcpc_alert(int port)
 	if (alert & TCPC_REG_ALERT_RX_HARD_RST) {
 		/* hard reset received */
 		CPRINTS("C%d Hard Reset received", port);
+
+		tcpm_hard_reset_reinit(port);
+
 		pd_event |= PD_EVENT_RX_HARD_RESET;
 	}
 
@@ -1307,8 +1312,8 @@ void tcpci_tcpc_alert(int port)
 	    alert & TCPC_REG_ALERT_TX_FAILED)
 		CPRINTS("C%d Hard Reset sent", port);
 
-	if (tcpm_tcpc_has_frs_control(port)
-	    && (alert_ext & TCPC_REG_ALERT_EXT_SNK_FRS))
+	if (tcpm_tcpc_has_frs_control(port) &&
+	    (alert_ext & TCPC_REG_ALERT_EXT_SNK_FRS))
 		pd_got_frs_signal(port);
 
 	/*
@@ -1365,7 +1370,6 @@ int tcpci_get_chip_info(int port, int live,
 
 	i = &cached_info[port];
 
-
 	/* If already cached && live data is not asked, return cached value */
 	if (i->vendor_id && !live) {
 		/*
@@ -1463,9 +1467,9 @@ int tcpci_tcpm_init(int port)
 	 * Alert assertion when CC_STATUS.Looking4Connection changes state.
 	 */
 	if (tcpc_config[port].flags & TCPC_FLAGS_TCPCI_REV2_0) {
-		error = tcpc_update8(port, TCPC_REG_TCPC_CTRL,
-				TCPC_REG_TCPC_CTRL_EN_LOOK4CONNECTION_ALERT,
-				MASK_SET);
+		error = tcpc_update8(
+			port, TCPC_REG_TCPC_CTRL,
+			TCPC_REG_TCPC_CTRL_EN_LOOK4CONNECTION_ALERT, MASK_SET);
 		if (error)
 			CPRINTS("C%d: Failed to init TCPC_CTRL!", port);
 	}
@@ -1492,10 +1496,10 @@ int tcpci_tcpm_init(int port)
 			tcpc_vbus[port] = 0;
 	} else {
 		/* Initial level, set appropriately */
-		tcpc_vbus[port] = (power_status &
-				   TCPC_REG_POWER_STATUS_VBUS_PRES)
-					? BIT(VBUS_PRESENT)
-					: BIT(VBUS_SAFE0V);
+		tcpc_vbus[port] =
+			(power_status & TCPC_REG_POWER_STATUS_VBUS_PRES) ?
+				BIT(VBUS_PRESENT) :
+				BIT(VBUS_SAFE0V);
 	}
 
 	/* Enable/disable VBUS monitor by the flag */
@@ -1511,8 +1515,8 @@ int tcpci_tcpm_init(int port)
 	 * Force an update to the VBUS status in case the TCPC doesn't send a
 	 * power status changed interrupt later.
 	 */
-	tcpci_check_vbus_changed(port,
-		TCPC_REG_ALERT_POWER_STATUS | TCPC_REG_ALERT_EXT_STATUS,
+	tcpci_check_vbus_changed(
+		port, TCPC_REG_ALERT_POWER_STATUS | TCPC_REG_ALERT_EXT_STATUS,
 		NULL);
 
 	error = init_alert_mask(port);
@@ -1584,6 +1588,10 @@ int tcpci_tcpm_mux_set(const struct usb_mux *me, mux_state_t mux_state,
 	/* This driver does not use host command ACKs */
 	*ack_required = false;
 
+	/* This driver treats safe mode as none */
+	if (mux_state == USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
+
 	/* Parameter is port only */
 	rv = mux_read(me, TCPC_REG_CONFIG_STD_OUTPUT, &reg);
 	if (rv != EC_SUCCESS)
@@ -1686,11 +1694,9 @@ static const struct tcpc_reg_dump_map tcpc_regs[] = {
 		.name = "FAULT_STATUS_MASK",
 		.size = 1,
 	},
-	{
-		.addr = TCPC_REG_EXT_STATUS_MASK,
-		.name = "EXT_STATUS_MASK",
-		.size = 1
-	},
+	{ .addr = TCPC_REG_EXT_STATUS_MASK,
+	  .name = "EXT_STATUS_MASK",
+	  .size = 1 },
 	{
 		.addr = TCPC_REG_ALERT_EXTENDED_MASK,
 		.name = "ALERT_EXTENDED_MASK",
@@ -1833,43 +1839,44 @@ void tcpc_dump_std_registers(int port)
 #endif
 
 const struct tcpm_drv tcpci_tcpm_drv = {
-	.init			= &tcpci_tcpm_init,
-	.release		= &tcpci_tcpm_release,
-	.get_cc			= &tcpci_tcpm_get_cc,
+	.init = &tcpci_tcpm_init,
+	.release = &tcpci_tcpm_release,
+	.get_cc = &tcpci_tcpm_get_cc,
 #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	.check_vbus_level	= &tcpci_tcpm_check_vbus_level,
+	.check_vbus_level = &tcpci_tcpm_check_vbus_level,
 #endif
-	.get_vbus_voltage	= &tcpci_get_vbus_voltage,
-	.select_rp_value	= &tcpci_tcpm_select_rp_value,
-	.set_cc			= &tcpci_tcpm_set_cc,
-	.set_polarity		= &tcpci_tcpm_set_polarity,
+	.get_vbus_voltage = &tcpci_get_vbus_voltage,
+	.select_rp_value = &tcpci_tcpm_select_rp_value,
+	.set_cc = &tcpci_tcpm_set_cc,
+	.set_polarity = &tcpci_tcpm_set_polarity,
 #ifdef CONFIG_USB_PD_DECODE_SOP
-	.sop_prime_enable	= &tcpci_tcpm_sop_prime_enable,
+	.sop_prime_enable = &tcpci_tcpm_sop_prime_enable,
 #endif
-	.set_vconn		= &tcpci_tcpm_set_vconn,
-	.set_msg_header		= &tcpci_tcpm_set_msg_header,
-	.set_rx_enable		= &tcpci_tcpm_set_rx_enable,
-	.get_message_raw	= &tcpci_tcpm_get_message_raw,
-	.transmit		= &tcpci_tcpm_transmit,
-	.tcpc_alert		= &tcpci_tcpc_alert,
+	.set_vconn = &tcpci_tcpm_set_vconn,
+	.set_msg_header = &tcpci_tcpm_set_msg_header,
+	.set_rx_enable = &tcpci_tcpm_set_rx_enable,
+	.get_message_raw = &tcpci_tcpm_get_message_raw,
+	.transmit = &tcpci_tcpm_transmit,
+	.tcpc_alert = &tcpci_tcpc_alert,
 #ifdef CONFIG_USB_PD_DISCHARGE_TCPC
-	.tcpc_discharge_vbus	= &tcpci_tcpc_discharge_vbus,
+	.tcpc_discharge_vbus = &tcpci_tcpc_discharge_vbus,
 #endif
 	.tcpc_enable_auto_discharge_disconnect =
 		&tcpci_tcpc_enable_auto_discharge_disconnect,
 #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-	.drp_toggle		= &tcpci_tcpc_drp_toggle,
+	.drp_toggle = &tcpci_tcpc_drp_toggle,
 #endif
-	.get_chip_info		= &tcpci_get_chip_info,
-	.get_snk_ctrl		= &tcpci_tcpm_get_snk_ctrl,
-	.set_snk_ctrl		= &tcpci_tcpm_set_snk_ctrl,
-	.get_src_ctrl		= &tcpci_tcpm_get_src_ctrl,
-	.set_src_ctrl		= &tcpci_tcpm_set_src_ctrl,
+	.get_chip_info = &tcpci_get_chip_info,
+	.get_snk_ctrl = &tcpci_tcpm_get_snk_ctrl,
+	.set_snk_ctrl = &tcpci_tcpm_set_snk_ctrl,
+	.get_src_ctrl = &tcpci_tcpm_get_src_ctrl,
+	.set_src_ctrl = &tcpci_tcpm_set_src_ctrl,
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	.enter_low_power_mode	= &tcpci_enter_low_power_mode,
+	.enter_low_power_mode = &tcpci_enter_low_power_mode,
 #endif
-	.set_bist_test_mode	= &tcpci_set_bist_test_mode,
+	.set_bist_test_mode = &tcpci_set_bist_test_mode,
+	.get_bist_test_mode = &tcpci_get_bist_test_mode,
 #ifdef CONFIG_CMD_TCPC_DUMP
-	.dump_registers		= &tcpc_dump_std_registers,
+	.dump_registers = &tcpc_dump_std_registers,
 #endif
 };
diff --git a/driver/tcpm/tusb422.c b/driver/tcpm/tusb422.c
index 6e07bce5e1..6d12d1758b 100644
--- a/driver/tcpm/tusb422.c
+++ b/driver/tcpm/tusb422.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -36,7 +36,7 @@ enum tusb422_reg_addr {
 
 enum vbus_and_vconn_control_mask {
 	INT_VCONNDIS_DISABLE = BIT(1),
-	INT_VBUSDIS_DISABLE  = BIT(2),
+	INT_VBUSDIS_DISABLE = BIT(2),
 };
 
 /* The TUSB422 cannot drive an FRS GPIO, but can detect FRS */
@@ -86,7 +86,7 @@ static int tusb422_tcpci_tcpm_init(int port)
 		 * Mode.
 		 */
 		tcpc_write(port, TUSB422_REG_VBUS_AND_VCONN_CONTROL,
-				INT_VBUSDIS_DISABLE);
+			   INT_VBUSDIS_DISABLE);
 	}
 	if (IS_ENABLED(CONFIG_USB_PD_FRS_TCPC)) {
 		/* Disable FRS detection, and enable the FRS detection alert */
@@ -103,7 +103,7 @@ static int tusb422_tcpci_tcpm_init(int port)
 	 */
 	/* Enable VBUS detection */
 	return tcpc_write16(port, TCPC_REG_COMMAND,
-				TCPC_REG_COMMAND_ENABLE_VBUS_DETECT);
+			    TCPC_REG_COMMAND_ENABLE_VBUS_DETECT);
 }
 
 static int tusb422_tcpm_set_cc(int port, int pull)
@@ -154,40 +154,41 @@ static void tusb422_tcpci_tcpc_alert(int port)
 }
 
 const struct tcpm_drv tusb422_tcpm_drv = {
-	.init			= &tusb422_tcpci_tcpm_init,
-	.release		= &tcpci_tcpm_release,
-	.get_cc			= &tcpci_tcpm_get_cc,
+	.init = &tusb422_tcpci_tcpm_init,
+	.release = &tcpci_tcpm_release,
+	.get_cc = &tcpci_tcpm_get_cc,
 #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	.check_vbus_level	= &tcpci_tcpm_check_vbus_level,
+	.check_vbus_level = &tcpci_tcpm_check_vbus_level,
 #endif
-	.select_rp_value	= &tcpci_tcpm_select_rp_value,
-	.set_cc			= &tusb422_tcpm_set_cc,
-	.set_polarity		= &tcpci_tcpm_set_polarity,
+	.select_rp_value = &tcpci_tcpm_select_rp_value,
+	.set_cc = &tusb422_tcpm_set_cc,
+	.set_polarity = &tcpci_tcpm_set_polarity,
 #ifdef CONFIG_USB_PD_DECODE_SOP
-	.sop_prime_enable	= &tcpci_tcpm_sop_prime_enable,
+	.sop_prime_enable = &tcpci_tcpm_sop_prime_enable,
 #endif
-	.set_vconn		= &tcpci_tcpm_set_vconn,
-	.set_msg_header		= &tcpci_tcpm_set_msg_header,
-	.set_rx_enable		= &tcpci_tcpm_set_rx_enable,
-	.get_message_raw	= &tcpci_tcpm_get_message_raw,
-	.transmit		= &tcpci_tcpm_transmit,
-	.tcpc_alert		= &tusb422_tcpci_tcpc_alert,
+	.set_vconn = &tcpci_tcpm_set_vconn,
+	.set_msg_header = &tcpci_tcpm_set_msg_header,
+	.set_rx_enable = &tcpci_tcpm_set_rx_enable,
+	.get_message_raw = &tcpci_tcpm_get_message_raw,
+	.transmit = &tcpci_tcpm_transmit,
+	.tcpc_alert = &tusb422_tcpci_tcpc_alert,
 #ifdef CONFIG_USB_PD_DISCHARGE_TCPC
-	.tcpc_discharge_vbus	= &tcpci_tcpc_discharge_vbus,
+	.tcpc_discharge_vbus = &tcpci_tcpc_discharge_vbus,
 #endif
 	.tcpc_enable_auto_discharge_disconnect =
-				  &tcpci_tcpc_enable_auto_discharge_disconnect,
+		&tcpci_tcpc_enable_auto_discharge_disconnect,
 #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-	.drp_toggle		= &tusb422_tcpc_drp_toggle,
+	.drp_toggle = &tusb422_tcpc_drp_toggle,
 #endif
-	.get_chip_info		= &tcpci_get_chip_info,
-	.set_snk_ctrl		= &tcpci_tcpm_set_snk_ctrl,
-	.set_src_ctrl		= &tcpci_tcpm_set_src_ctrl,
+	.get_chip_info = &tcpci_get_chip_info,
+	.set_snk_ctrl = &tcpci_tcpm_set_snk_ctrl,
+	.set_src_ctrl = &tcpci_tcpm_set_src_ctrl,
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	.enter_low_power_mode	= &tcpci_enter_low_power_mode,
+	.enter_low_power_mode = &tcpci_enter_low_power_mode,
 #endif
-	.set_bist_test_mode	= &tcpci_set_bist_test_mode,
+	.set_bist_test_mode = &tcpci_set_bist_test_mode,
+	.get_bist_test_mode = &tcpci_get_bist_test_mode,
 #ifdef CONFIG_USB_PD_FRS_TCPC
-	.set_frs_enable         = &tusb422_set_frs_enable,
+	.set_frs_enable = &tusb422_set_frs_enable,
 #endif
 };
diff --git a/driver/tcpm/tusb422.h b/driver/tcpm/tusb422.h
index f39939b184..2ce601c866 100644
--- a/driver/tcpm/tusb422.h
+++ b/driver/tcpm/tusb422.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/driver/temp_sensor/adt7481.c b/driver/temp_sensor/adt7481.c
index 738fdb776a..0157d64b2d 100644
--- a/driver/temp_sensor/adt7481.c
+++ b/driver/temp_sensor/adt7481.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -34,14 +34,14 @@ static int has_power(void)
 
 static int raw_read8(const int offset, int *data_ptr)
 {
-	return i2c_read8(I2C_PORT_THERMAL, ADT7481_I2C_ADDR_FLAGS,
-			 offset, data_ptr);
+	return i2c_read8(I2C_PORT_THERMAL, ADT7481_I2C_ADDR_FLAGS, offset,
+			 data_ptr);
 }
 
 static int raw_write8(const int offset, int data)
 {
-	return i2c_write8(I2C_PORT_THERMAL, ADT7481_I2C_ADDR_FLAGS,
-			  offset, data);
+	return i2c_write8(I2C_PORT_THERMAL, ADT7481_I2C_ADDR_FLAGS, offset,
+			  data);
 }
 
 static int get_temp(const int offset, int *temp_ptr)
@@ -145,7 +145,7 @@ int adt7481_set_therm_limit(int channel, int limit_c, int hysteresis)
 		return EC_ERROR_INVAL;
 
 	if (hysteresis > ADT7481_HYSTERESIS_HIGH_LIMIT ||
-		hysteresis < ADT7481_HYSTERESIS_LOW_LIMIT)
+	    hysteresis < ADT7481_HYSTERESIS_LOW_LIMIT)
 		return EC_ERROR_INVAL;
 
 	/* hysteresis must be less than high limit */
@@ -197,12 +197,10 @@ static void adt7481_temp_sensor_poll(void)
 DECLARE_HOOK(HOOK_SECOND, adt7481_temp_sensor_poll, HOOK_PRIO_TEMP_SENSOR);
 
 #ifdef CONFIG_CMD_TEMP_SENSOR
-static void print_temps(
-		const char *name,
-		const int adt7481_temp_reg,
-		const int adt7481_therm_limit_reg,
-		const int adt7481_high_limit_reg,
-		const int adt7481_low_limit_reg)
+static void print_temps(const char *name, const int adt7481_temp_reg,
+			const int adt7481_therm_limit_reg,
+			const int adt7481_high_limit_reg,
+			const int adt7481_low_limit_reg)
 {
 	int value;
 
@@ -230,39 +228,33 @@ static int print_status(void)
 {
 	int value;
 
-	print_temps("Local", ADT7481_LOCAL,
-		    ADT7481_LOCAL_THERM_LIMIT,
-		    ADT7481_LOCAL_HIGH_LIMIT_R,
-		    ADT7481_LOCAL_LOW_LIMIT_R);
+	print_temps("Local", ADT7481_LOCAL, ADT7481_LOCAL_THERM_LIMIT,
+		    ADT7481_LOCAL_HIGH_LIMIT_R, ADT7481_LOCAL_LOW_LIMIT_R);
 
-	print_temps("Remote1", ADT7481_REMOTE1,
-		    ADT7481_REMOTE1_THERM_LIMIT,
-		    ADT7481_REMOTE1_HIGH_LIMIT_R,
-		    ADT7481_REMOTE1_LOW_LIMIT_R);
+	print_temps("Remote1", ADT7481_REMOTE1, ADT7481_REMOTE1_THERM_LIMIT,
+		    ADT7481_REMOTE1_HIGH_LIMIT_R, ADT7481_REMOTE1_LOW_LIMIT_R);
 
-	print_temps("Remote2", ADT7481_REMOTE2,
-		    ADT7481_REMOTE2_THERM_LIMIT,
-		    ADT7481_REMOTE2_HIGH_LIMIT,
-		    ADT7481_REMOTE2_LOW_LIMIT);
+	print_temps("Remote2", ADT7481_REMOTE2, ADT7481_REMOTE2_THERM_LIMIT,
+		    ADT7481_REMOTE2_HIGH_LIMIT, ADT7481_REMOTE2_LOW_LIMIT);
 
 	ccprintf("\n");
 
 	if (raw_read8(ADT7481_STATUS1_R, &value) == EC_SUCCESS)
-		ccprintf("STATUS1:  %pb\n", BINARY_VALUE(value, 8));
+		ccprintf("STATUS1:  0x%x\n", value);
 
 	if (raw_read8(ADT7481_STATUS2_R, &value) == EC_SUCCESS)
-		ccprintf("STATUS2:  %pb\n", BINARY_VALUE(value, 8));
+		ccprintf("STATUS2:  0x%x\n", value);
 
 	if (raw_read8(ADT7481_CONFIGURATION1_R, &value) == EC_SUCCESS)
-		ccprintf("CONFIG1: %pb\n", BINARY_VALUE(value, 8));
+		ccprintf("CONFIG1: 0x%x\n", value);
 
 	if (raw_read8(ADT7481_CONFIGURATION2, &value) == EC_SUCCESS)
-		ccprintf("CONFIG2: %pb\n", BINARY_VALUE(value, 8));
+		ccprintf("CONFIG2: 0x%x\n", value);
 
 	return EC_SUCCESS;
 }
 
-static int command_adt7481(int argc, char **argv)
+static int command_adt7481(int argc, const char **argv)
 {
 	char *command;
 	char *e;
@@ -307,8 +299,7 @@ static int command_adt7481(int argc, char **argv)
 		rv = raw_read8(offset, &data);
 		if (rv < 0)
 			return rv;
-		ccprintf("Byte at offset 0x%02x is %pb\n",
-			 offset, BINARY_VALUE(data, 8));
+		ccprintf("Byte at offset 0x%02x is 0x%x\n", offset, data);
 		return rv;
 	}
 
@@ -331,7 +322,8 @@ static int command_adt7481(int argc, char **argv)
 
 	return rv;
 }
-DECLARE_CONSOLE_COMMAND(adt7481, command_adt7481,
+DECLARE_CONSOLE_COMMAND(
+	adt7481, command_adt7481,
 	"[settemp|setbyte <offset> <value>] or [getbyte <offset>] or"
 	"[power <on|off>]. "
 	"Temps in Celsius.",
diff --git a/driver/temp_sensor/adt7481.h b/driver/temp_sensor/adt7481.h
index 78541a0a3b..af2b676f0d 100644
--- a/driver/temp_sensor/adt7481.h
+++ b/driver/temp_sensor/adt7481.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,120 +8,118 @@
 #ifndef __CROS_EC_ADT7481_H
 #define __CROS_EC_ADT7481_H
 
-#define ADT7481_I2C_ADDR_FLAGS		0x4B
+#define ADT7481_I2C_ADDR_FLAGS 0x4B
 
-#define ADT7481_IDX_LOCAL	0
-#define ADT7481_IDX_REMOTE1	1
-#define ADT7481_IDX_REMOTE2	2
+#define ADT7481_IDX_LOCAL 0
+#define ADT7481_IDX_REMOTE1 1
+#define ADT7481_IDX_REMOTE2 2
 
 /* Chip-specific registers */
-#define ADT7481_LOCAL			0x00
-#define ADT7481_REMOTE1			0x01
-#define ADT7481_STATUS1_R		0x02
-#define ADT7481_CONFIGURATION1_R	0x03
-#define ADT7481_CONVERSION_RATE_R	0x04
-#define ADT7481_LOCAL_HIGH_LIMIT_R	0x05
-#define ADT7481_LOCAL_LOW_LIMIT_R	0x06
-#define ADT7481_REMOTE1_HIGH_LIMIT_R	0x07
-#define ADT7481_REMOTE1_LOW_LIMIT_R	0x08
-#define ADT7481_CONFIGURATION1_W	0x09
-#define ADT7481_CONVERSION_RATE_W	0x0a
-#define ADT7481_LOCAL_HIGH_LIMIT_W	0x0b
-#define ADT7481_LOCAL_LOW_LIMIT_W	0x0c
-#define ADT7481_REMOTE1_HIGH_LIMIT_W	0x0d
-#define ADT7481_REMOTE1_LOW_LIMIT_W	0x0e
-#define ADT7481_ONESHOT_W		0x0f
-#define ADT7481_REMOTE1_EXTD_R		0x10
-#define ADT7481_REMOTE1_OFFSET		0x11
-#define ADT7481_REMOTE1_OFFSET_EXTD	0x12
-#define ADT7481_REMOTE1_HIGH_LIMIT_EXTD	0x13
-#define ADT7481_REMOTE1_LOW_LIMIT_EXTD	0x14
-#define ADT7481_REMOTE1_THERM_LIMIT	0x19
-#define ADT7481_LOCAL_THERM_LIMIT	0x20
-#define ADT7481_THERM_HYSTERESIS	0x21
-#define ADT7481_CONSECUTIVE_ALERT	0x22
-#define ADT7481_STATUS2_R		0x23
-#define ADT7481_CONFIGURATION2		0x24
-#define ADT7481_REMOTE2			0x30
-#define ADT7481_REMOTE2_HIGH_LIMIT	0x31
-#define ADT7481_REMOTE2_LOW_LIMIT	0x32
-#define ADT7481_REMOTE2_EXTD_R		0x33
-#define ADT7481_REMOTE2_OFFSET		0x34
-#define ADT7481_REMOTE2_OFFSET_EXTD	0x35
-#define ADT7481_REMOTE2_HIGH_LIMIT_EXTD	0x36
-#define ADT7481_REMOTE2_LOW_LIMIT_EXTD	0x37
-#define ADT7481_REMOTE2_THERM_LIMIT	0x39
-#define ADT7481_DEVICE_ID		0x3d
-#define ADT7481_MANUFACTURER_ID		0x3e
+#define ADT7481_LOCAL 0x00
+#define ADT7481_REMOTE1 0x01
+#define ADT7481_STATUS1_R 0x02
+#define ADT7481_CONFIGURATION1_R 0x03
+#define ADT7481_CONVERSION_RATE_R 0x04
+#define ADT7481_LOCAL_HIGH_LIMIT_R 0x05
+#define ADT7481_LOCAL_LOW_LIMIT_R 0x06
+#define ADT7481_REMOTE1_HIGH_LIMIT_R 0x07
+#define ADT7481_REMOTE1_LOW_LIMIT_R 0x08
+#define ADT7481_CONFIGURATION1_W 0x09
+#define ADT7481_CONVERSION_RATE_W 0x0a
+#define ADT7481_LOCAL_HIGH_LIMIT_W 0x0b
+#define ADT7481_LOCAL_LOW_LIMIT_W 0x0c
+#define ADT7481_REMOTE1_HIGH_LIMIT_W 0x0d
+#define ADT7481_REMOTE1_LOW_LIMIT_W 0x0e
+#define ADT7481_ONESHOT_W 0x0f
+#define ADT7481_REMOTE1_EXTD_R 0x10
+#define ADT7481_REMOTE1_OFFSET 0x11
+#define ADT7481_REMOTE1_OFFSET_EXTD 0x12
+#define ADT7481_REMOTE1_HIGH_LIMIT_EXTD 0x13
+#define ADT7481_REMOTE1_LOW_LIMIT_EXTD 0x14
+#define ADT7481_REMOTE1_THERM_LIMIT 0x19
+#define ADT7481_LOCAL_THERM_LIMIT 0x20
+#define ADT7481_THERM_HYSTERESIS 0x21
+#define ADT7481_CONSECUTIVE_ALERT 0x22
+#define ADT7481_STATUS2_R 0x23
+#define ADT7481_CONFIGURATION2 0x24
+#define ADT7481_REMOTE2 0x30
+#define ADT7481_REMOTE2_HIGH_LIMIT 0x31
+#define ADT7481_REMOTE2_LOW_LIMIT 0x32
+#define ADT7481_REMOTE2_EXTD_R 0x33
+#define ADT7481_REMOTE2_OFFSET 0x34
+#define ADT7481_REMOTE2_OFFSET_EXTD 0x35
+#define ADT7481_REMOTE2_HIGH_LIMIT_EXTD 0x36
+#define ADT7481_REMOTE2_LOW_LIMIT_EXTD 0x37
+#define ADT7481_REMOTE2_THERM_LIMIT 0x39
+#define ADT7481_DEVICE_ID 0x3d
+#define ADT7481_MANUFACTURER_ID 0x3e
 
 /* Config1 register bits */
-#define ADT7481_CONFIG1_REMOTE1_ALERT_MASK	BIT(0)
-#define ADT7481_CONFIG1_REMOTE2_ALERT_MASK	BIT(1)
-#define ADT7481_CONFIG1_TEMP_RANGE		BIT(2)
-#define ADT7481_CONFIG1_SEL_REMOTE2		BIT(3)
+#define ADT7481_CONFIG1_REMOTE1_ALERT_MASK BIT(0)
+#define ADT7481_CONFIG1_REMOTE2_ALERT_MASK BIT(1)
+#define ADT7481_CONFIG1_TEMP_RANGE BIT(2)
+#define ADT7481_CONFIG1_SEL_REMOTE2 BIT(3)
 /* ADT7481_CONFIG1_MODE bit is use to enable THERM mode */
-#define ADT7481_CONFIG1_MODE			BIT(5)
-#define ADT7481_CONFIG1_RUN_L			BIT(6)
+#define ADT7481_CONFIG1_MODE BIT(5)
+#define ADT7481_CONFIG1_RUN_L BIT(6)
 /* mask all alerts on ALERT# pin */
-#define ADT7481_CONFIG1_ALERT_MASK_L		BIT(7)
+#define ADT7481_CONFIG1_ALERT_MASK_L BIT(7)
 
 /* Config2 register bits */
-#define ADT7481_CONFIG2_LOCK			BIT(7)
+#define ADT7481_CONFIG2_LOCK BIT(7)
 
 /* Conversion Rate/Channel Select Register */
-#define ADT7481_CONV_RATE_MASK		(0x0f)
-#define ADT7481_CONV_RATE_16S		(0x00)
-#define ADT7481_CONV_RATE_8S		(0x01)
-#define ADT7481_CONV_RATE_4S		(0x02)
-#define ADT7481_CONV_RATE_2S		(0x03)
-#define ADT7481_CONV_RATE_1S		(0x04)
-#define ADT7481_CONV_RATE_500MS		(0x05)
-#define ADT7481_CONV_RATE_250MS		(0x06)
-#define ADT7481_CONV_RATE_125MS		(0x07)
-#define ADT7481_CONV_RATE_62500US	(0x08)
-#define ADT7481_CONV_RATE_31250US	(0x09)
-#define ADT7481_CONV_RATE_15500US	(0x0a)
+#define ADT7481_CONV_RATE_MASK (0x0f)
+#define ADT7481_CONV_RATE_16S (0x00)
+#define ADT7481_CONV_RATE_8S (0x01)
+#define ADT7481_CONV_RATE_4S (0x02)
+#define ADT7481_CONV_RATE_2S (0x03)
+#define ADT7481_CONV_RATE_1S (0x04)
+#define ADT7481_CONV_RATE_500MS (0x05)
+#define ADT7481_CONV_RATE_250MS (0x06)
+#define ADT7481_CONV_RATE_125MS (0x07)
+#define ADT7481_CONV_RATE_62500US (0x08)
+#define ADT7481_CONV_RATE_31250US (0x09)
+#define ADT7481_CONV_RATE_15500US (0x0a)
 /* continuous mode 73 ms averaging */
-#define ADT7481_CONV_RATE_73MS_AVE	(0x0b)
-#define ADT7481_CONV_CHAN_SELECT_MASK	(0x30)
-#define ADT7481_CONV_CHAN_SEL_ROUND_ROBIN	(0 << 4)
-#define ADT7481_CONV_CHAN_SEL_LOCAL		BIT(4)
-#define ADT7481_CONV_CHAN_SEL_REMOTE1		(2 << 4)
-#define ADT7481_CONV_CHAN_SEL_REMOTE2		(3 << 4)
-#define ADT7481_CONV_AVERAGING_L	BIT(7)
-
+#define ADT7481_CONV_RATE_73MS_AVE (0x0b)
+#define ADT7481_CONV_CHAN_SELECT_MASK (0x30)
+#define ADT7481_CONV_CHAN_SEL_ROUND_ROBIN (0 << 4)
+#define ADT7481_CONV_CHAN_SEL_LOCAL BIT(4)
+#define ADT7481_CONV_CHAN_SEL_REMOTE1 (2 << 4)
+#define ADT7481_CONV_CHAN_SEL_REMOTE2 (3 << 4)
+#define ADT7481_CONV_AVERAGING_L BIT(7)
 
 /* Status1 register bits */
-#define ADT7481_STATUS1_LOCAL_THERM_ALARM	BIT(0)
-#define ADT7481_STATUS1_REMOTE1_THERM_ALARM	BIT(1)
-#define ADT7481_STATUS1_REMOTE1_OPEN		BIT(2)
-#define ADT7481_STATUS1_REMOTE1_LOW_ALARM	BIT(3)
-#define ADT7481_STATUS1_REMOTE1_HIGH_ALARM	BIT(4)
-#define ADT7481_STATUS1_LOCAL_LOW_ALARM		BIT(5)
-#define ADT7481_STATUS1_LOCAL_HIGH_ALARM	BIT(6)
-#define ADT7481_STATUS1_BUSY			BIT(7)
+#define ADT7481_STATUS1_LOCAL_THERM_ALARM BIT(0)
+#define ADT7481_STATUS1_REMOTE1_THERM_ALARM BIT(1)
+#define ADT7481_STATUS1_REMOTE1_OPEN BIT(2)
+#define ADT7481_STATUS1_REMOTE1_LOW_ALARM BIT(3)
+#define ADT7481_STATUS1_REMOTE1_HIGH_ALARM BIT(4)
+#define ADT7481_STATUS1_LOCAL_LOW_ALARM BIT(5)
+#define ADT7481_STATUS1_LOCAL_HIGH_ALARM BIT(6)
+#define ADT7481_STATUS1_BUSY BIT(7)
 
 /* Status2 register bits */
-#define ADT7481_STATUS2_ALERT			BIT(0)
-#define ADT7481_STATUS2_REMOTE2_THERM_ALARM	BIT(1)
-#define ADT7481_STATUS2_REMOTE2_OPEN		BIT(2)
-#define ADT7481_STATUS2_REMOTE2_LOW_ALARM	BIT(3)
-#define ADT7481_STATUS2_REMOTE2_HIGH_ALARM	BIT(4)
+#define ADT7481_STATUS2_ALERT BIT(0)
+#define ADT7481_STATUS2_REMOTE2_THERM_ALARM BIT(1)
+#define ADT7481_STATUS2_REMOTE2_OPEN BIT(2)
+#define ADT7481_STATUS2_REMOTE2_LOW_ALARM BIT(3)
+#define ADT7481_STATUS2_REMOTE2_HIGH_ALARM BIT(4)
 
 /* Consecutive Alert register */
-#define ADT7481_CONSEC_MASK		(0xf)
-#define ADT7481_CONSEC_1		(0x0)
-#define ADT7481_CONSEC_2		(0x2)
-#define ADT7481_CONSEC_3		(0x6)
-#define ADT7481_CONSEC_4		(0xe)
-#define ADT7481_CONSEC_EN_SCL_TIMEOUT	BIT(5)
-#define ADT7481_CONSEC_EN_SDA_TIMEOUT	BIT(6)
-#define ADT7481_CONSEC_MASK_LOCAL_ALERT	BIT(7)
-
+#define ADT7481_CONSEC_MASK (0xf)
+#define ADT7481_CONSEC_1 (0x0)
+#define ADT7481_CONSEC_2 (0x2)
+#define ADT7481_CONSEC_3 (0x6)
+#define ADT7481_CONSEC_4 (0xe)
+#define ADT7481_CONSEC_EN_SCL_TIMEOUT BIT(5)
+#define ADT7481_CONSEC_EN_SDA_TIMEOUT BIT(6)
+#define ADT7481_CONSEC_MASK_LOCAL_ALERT BIT(7)
 
 /* Limits */
-#define ADT7481_HYSTERESIS_HIGH_LIMIT	255
-#define ADT7481_HYSTERESIS_LOW_LIMIT	0
+#define ADT7481_HYSTERESIS_HIGH_LIMIT 255
+#define ADT7481_HYSTERESIS_LOW_LIMIT 0
 
 enum adt7481_power_state {
 	ADT7481_POWER_OFF = 0,
diff --git a/driver/temp_sensor/amd_r19me4070.c b/driver/temp_sensor/amd_r19me4070.c
index b5f4e66d38..97868b6945 100644
--- a/driver/temp_sensor/amd_r19me4070.c
+++ b/driver/temp_sensor/amd_r19me4070.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,14 +13,14 @@
 #include "amd_r19me4070.h"
 #include "power.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* GPU I2C address */
-#define GPU_ADDR_FLAGS                  0x0041
+#define GPU_ADDR_FLAGS 0x0041
 
-#define GPU_INIT_OFFSET                 0x01
-#define GPU_TEMPERATURE_OFFSET          0x03
+#define GPU_INIT_OFFSET 0x01
+#define GPU_TEMPERATURE_OFFSET 0x03
 
 static int initialized;
 /*
@@ -34,8 +34,8 @@ static void gpu_init_temp_sensor(void)
 {
 	int rv;
 	rv = i2c_write_block(I2C_PORT_GPU, GPU_ADDR_FLAGS, GPU_INIT_OFFSET,
-			  gpu_init_write_value,
-			  ARRAY_SIZE(gpu_init_write_value));
+			     gpu_init_write_value,
+			     ARRAY_SIZE(gpu_init_write_value));
 	if (rv == EC_SUCCESS) {
 		initialized = 1;
 		return;
@@ -64,7 +64,7 @@ int get_temp_R19ME4070(int idx, int *temp_ptr)
 		return EC_ERROR_BUSY;
 	}
 	rv = i2c_read_block(I2C_PORT_GPU, GPU_ADDR_FLAGS,
-			GPU_TEMPERATURE_OFFSET, reg, ARRAY_SIZE(reg));
+			    GPU_TEMPERATURE_OFFSET, reg, ARRAY_SIZE(reg));
 	if (rv) {
 		CPRINTS("read GPU Temperature fail");
 		*temp_ptr = C_TO_K(0);
diff --git a/driver/temp_sensor/amd_r19me4070.h b/driver/temp_sensor/amd_r19me4070.h
index d3c7977ba5..5460dcb1cc 100644
--- a/driver/temp_sensor/amd_r19me4070.h
+++ b/driver/temp_sensor/amd_r19me4070.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,7 +9,7 @@
 #define __CROS_EC_R19ME4070_H
 
 /* GPU features */
-#define R19ME4070_LOCAL                 0
+#define R19ME4070_LOCAL 0
 
 /*
  * get GPU temperature value and move to *tem_ptr
diff --git a/driver/temp_sensor/bd99992gw.c b/driver/temp_sensor/bd99992gw.c
index e66642224c..bd152c0441 100644
--- a/driver/temp_sensor/bd99992gw.c
+++ b/driver/temp_sensor/bd99992gw.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,6 +10,7 @@
  */
 
 #include "bd99992gw.h"
+#include "builtin/assert.h"
 #include "chipset.h"
 #include "common.h"
 #include "console.h"
@@ -23,7 +24,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_THERMAL, outstr)
-#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
 
 /* List of active channels, ordered by pointer register */
 static enum bd99992gw_adc_channel
@@ -39,8 +40,8 @@ static enum bd99992gw_adc_channel
 static int raw_read8(const int offset, int *data_ptr)
 {
 	int ret;
-	ret = i2c_read8(I2C_PORT_THERMAL, BD99992GW_I2C_ADDR_FLAGS,
-			offset, data_ptr);
+	ret = i2c_read8(I2C_PORT_THERMAL, BD99992GW_I2C_ADDR_FLAGS, offset,
+			data_ptr);
 	if (ret != EC_SUCCESS)
 		CPRINTS("bd99992gw read fail %d", ret);
 	return ret;
@@ -49,8 +50,8 @@ static int raw_read8(const int offset, int *data_ptr)
 static int raw_write8(const int offset, int data)
 {
 	int ret;
-	ret = i2c_write8(I2C_PORT_THERMAL, BD99992GW_I2C_ADDR_FLAGS,
-			 offset, data);
+	ret = i2c_write8(I2C_PORT_THERMAL, BD99992GW_I2C_ADDR_FLAGS, offset,
+			 data);
 	if (ret != EC_SUCCESS)
 		CPRINTS("bd99992gw write fail %d", ret);
 	return ret;
@@ -79,9 +80,11 @@ static void bd99992gw_init(void)
 	/* Now write pointer regs with channel to monitor */
 	for (i = 0; i < active_channel_count; ++i)
 		/* Write stop bit on last channel */
-		if (raw_write8(pointer_reg + i, active_channels[i] |
-			  ((i == active_channel_count - 1) ?
-			  BD99992GW_ADC1ADDR_STOP : 0)))
+		if (raw_write8(pointer_reg + i,
+			       active_channels[i] |
+				       ((i == active_channel_count - 1) ?
+						BD99992GW_ADC1ADDR_STOP :
+						0)))
 			return;
 
 	/* Enable ADC interrupts */
@@ -96,7 +99,8 @@ static void bd99992gw_init(void)
 
 	/* Start round-robin conversions at 27ms period */
 	raw_write8(BD99992GW_REG_ADC1CNTL1, ADC_LOOP_PERIOD |
-		   BD99992GW_ADC1CNTL1_ADEN | BD99992GW_ADC1CNTL1_ADSTRT);
+						    BD99992GW_ADC1CNTL1_ADEN |
+						    BD99992GW_ADC1CNTL1_ADSTRT);
 }
 /*
  * Some regs only work in S0, so we must initialize on AP startup in
@@ -130,24 +134,20 @@ int bd99992gw_get_val(int idx, int *temp_ptr)
 	/* Find requested channel */
 	for (i = 0; i < ARRAY_SIZE(active_channels); ++i) {
 		channel = active_channels[i];
-		if (channel == idx ||
-		    channel == BD99992GW_ADC_CHANNEL_NONE)
+		if (channel == idx || channel == BD99992GW_ADC_CHANNEL_NONE)
 			break;
 	}
 
 	/* Make sure we found it */
-	if (i == ARRAY_SIZE(active_channels) ||
-	    active_channels[i] != idx) {
+	if (i == ARRAY_SIZE(active_channels) || active_channels[i] != idx) {
 		CPRINTS("Bad ADC channel %d", idx);
 		return EC_ERROR_INVAL;
 	}
 
 	/* Pause conversions */
-	ret = raw_write8(0x80,
-			 ADC_LOOP_PERIOD |
-			 BD99992GW_ADC1CNTL1_ADEN |
-			 BD99992GW_ADC1CNTL1_ADSTRT |
-			 BD99992GW_ADC1CNTL1_ADPAUSE);
+	ret = raw_write8(0x80, ADC_LOOP_PERIOD | BD99992GW_ADC1CNTL1_ADEN |
+				       BD99992GW_ADC1CNTL1_ADSTRT |
+				       BD99992GW_ADC1CNTL1_ADPAUSE);
 	if (ret)
 		return ret;
 
@@ -173,8 +173,9 @@ int bd99992gw_get_val(int idx, int *temp_ptr)
 		return ret;
 
 	/* Resume conversions */
-	ret = raw_write8(BD99992GW_REG_ADC1CNTL1, ADC_LOOP_PERIOD |
-		   BD99992GW_ADC1CNTL1_ADEN | BD99992GW_ADC1CNTL1_ADSTRT);
+	ret = raw_write8(BD99992GW_REG_ADC1CNTL1,
+			 ADC_LOOP_PERIOD | BD99992GW_ADC1CNTL1_ADEN |
+				 BD99992GW_ADC1CNTL1_ADSTRT);
 	if (ret)
 		return ret;
 
diff --git a/driver/temp_sensor/bd99992gw.h b/driver/temp_sensor/bd99992gw.h
index c461012c45..8ee2c2774c 100644
--- a/driver/temp_sensor/bd99992gw.h
+++ b/driver/temp_sensor/bd99992gw.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,74 +8,74 @@
 #ifndef __CROS_EC_TEMP_SENSOR_BD99992GW_H
 #define __CROS_EC_TEMP_SENSOR_BD99992GW_H
 
-#define BD99992GW_I2C_ADDR_FLAGS	0x30
+#define BD99992GW_I2C_ADDR_FLAGS 0x30
 
 /* ADC channels */
 enum bd99992gw_adc_channel {
-	BD99992GW_ADC_CHANNEL_NONE      = -1,
-	BD99992GW_ADC_CHANNEL_BATTERY   = 0,
-	BD99992GW_ADC_CHANNEL_AC        = 1,
+	BD99992GW_ADC_CHANNEL_NONE = -1,
+	BD99992GW_ADC_CHANNEL_BATTERY = 0,
+	BD99992GW_ADC_CHANNEL_AC = 1,
 	BD99992GW_ADC_CHANNEL_SYSTHERM0 = 2,
 	BD99992GW_ADC_CHANNEL_SYSTHERM1 = 3,
 	BD99992GW_ADC_CHANNEL_SYSTHERM2 = 4,
 	BD99992GW_ADC_CHANNEL_SYSTHERM3 = 5,
-	BD99992GW_ADC_CHANNEL_DIE_TEMP  = 6,
-	BD99992GW_ADC_CHANNEL_VDC       = 7,
-	BD99992GW_ADC_CHANNEL_COUNT     = 8,
+	BD99992GW_ADC_CHANNEL_DIE_TEMP = 6,
+	BD99992GW_ADC_CHANNEL_VDC = 7,
+	BD99992GW_ADC_CHANNEL_COUNT = 8,
 };
 
 /* Registers */
-#define BD99992GW_REG_IRQLVL1		0x02
-#define BD99992GW_IRQLVL1_ADC		 BIT(1) /* ADC IRQ asserted */
+#define BD99992GW_REG_IRQLVL1 0x02
+#define BD99992GW_IRQLVL1_ADC BIT(1) /* ADC IRQ asserted */
 
-#define BD99992GW_REG_ADC1INT		0x03
-#define BD99992GW_ADC1INT_RND		 BIT(0) /* RR cycle completed */
+#define BD99992GW_REG_ADC1INT 0x03
+#define BD99992GW_ADC1INT_RND BIT(0) /* RR cycle completed */
 
-#define BD99992GW_REG_MADC1INT		0x0a
-#define BD99992GW_MADC1INT_RND		 BIT(0) /* RR cycle mask */
+#define BD99992GW_REG_MADC1INT 0x0a
+#define BD99992GW_MADC1INT_RND BIT(0) /* RR cycle mask */
 
-#define BD99992GW_REG_IRQLVL1MSK	0x13
-#define BD99992GW_IRQLVL1MSK_MADC	 BIT(1) /* ADC IRQ mask */
+#define BD99992GW_REG_IRQLVL1MSK 0x13
+#define BD99992GW_IRQLVL1MSK_MADC BIT(1) /* ADC IRQ mask */
 
-#define BD99992GW_REG_ADC1CNTL1		0x80
-#define BD99992GW_ADC1CNTL1_SLP27MS	 (0x6 << 3) /* 27ms between pass */
-#define BD99992GW_ADC1CNTL1_NOLOOP	 (0x7 << 3) /* Single loop pass only */
-#define BD99992GW_ADC1CNTL1_ADPAUSE	 BIT(2)   /* ADC pause */
-#define BD99992GW_ADC1CNTL1_ADSTRT	 BIT(1)   /* ADC start */
-#define BD99992GW_ADC1CNTL1_ADEN	 BIT(0)   /* ADC enable */
+#define BD99992GW_REG_ADC1CNTL1 0x80
+#define BD99992GW_ADC1CNTL1_SLP27MS (0x6 << 3) /* 27ms between pass */
+#define BD99992GW_ADC1CNTL1_NOLOOP (0x7 << 3) /* Single loop pass only */
+#define BD99992GW_ADC1CNTL1_ADPAUSE BIT(2) /* ADC pause */
+#define BD99992GW_ADC1CNTL1_ADSTRT BIT(1) /* ADC start */
+#define BD99992GW_ADC1CNTL1_ADEN BIT(0) /* ADC enable */
 
-#define BD99992GW_REG_ADC1CNTL2		0x81
-#define BD99992GW_ADC1CNTL2_ADCTHERM	 BIT(0) /* Enable ADC sequencing */
+#define BD99992GW_REG_ADC1CNTL2 0x81
+#define BD99992GW_ADC1CNTL2_ADCTHERM BIT(0) /* Enable ADC sequencing */
 
- /* ADC1 Pointer file regs - assign to proper bd99992gw_adc_channel */
-#define BD99992GW_ADC_POINTER_REG_COUNT	8
-#define BD99992GW_REG_ADC1ADDR0		0x82
-#define BD99992GW_REG_ADC1ADDR1		0x83
-#define BD99992GW_REG_ADC1ADDR2		0x84
-#define BD99992GW_REG_ADC1ADDR3		0x85
-#define BD99992GW_REG_ADC1ADDR4		0x86
-#define BD99992GW_REG_ADC1ADDR5		0x87
-#define BD99992GW_REG_ADC1ADDR6		0x88
-#define BD99992GW_REG_ADC1ADDR7		0x89
-#define BD99992GW_ADC1ADDR_STOP		 BIT(3) /* Last conversion channel */
+/* ADC1 Pointer file regs - assign to proper bd99992gw_adc_channel */
+#define BD99992GW_ADC_POINTER_REG_COUNT 8
+#define BD99992GW_REG_ADC1ADDR0 0x82
+#define BD99992GW_REG_ADC1ADDR1 0x83
+#define BD99992GW_REG_ADC1ADDR2 0x84
+#define BD99992GW_REG_ADC1ADDR3 0x85
+#define BD99992GW_REG_ADC1ADDR4 0x86
+#define BD99992GW_REG_ADC1ADDR5 0x87
+#define BD99992GW_REG_ADC1ADDR6 0x88
+#define BD99992GW_REG_ADC1ADDR7 0x89
+#define BD99992GW_ADC1ADDR_STOP BIT(3) /* Last conversion channel */
 
 /* Result registers */
-#define BD99992GW_REG_ADC1DATA0L	0x95
-#define BD99992GW_REG_ADC1DATA0H	0x96
-#define BD99992GW_REG_ADC1DATA1L	0x97
-#define BD99992GW_REG_ADC1DATA1H	0x98
-#define BD99992GW_REG_ADC1DATA2L	0x99
-#define BD99992GW_REG_ADC1DATA2H	0x9a
-#define BD99992GW_REG_ADC1DATA3L	0x9b
-#define BD99992GW_REG_ADC1DATA3H	0x9c
-#define BD99992GW_REG_ADC1DATA4L	0x9d
-#define BD99992GW_REG_ADC1DATA4H	0x9e
-#define BD99992GW_REG_ADC1DATA5L	0x9f
-#define BD99992GW_REG_ADC1DATA5H	0xa0
-#define BD99992GW_REG_ADC1DATA6L	0xa1
-#define BD99992GW_REG_ADC1DATA6H	0xa2
-#define BD99992GW_REG_ADC1DATA7L	0xa3
-#define BD99992GW_REG_ADC1DATA7H	0xa4
+#define BD99992GW_REG_ADC1DATA0L 0x95
+#define BD99992GW_REG_ADC1DATA0H 0x96
+#define BD99992GW_REG_ADC1DATA1L 0x97
+#define BD99992GW_REG_ADC1DATA1H 0x98
+#define BD99992GW_REG_ADC1DATA2L 0x99
+#define BD99992GW_REG_ADC1DATA2H 0x9a
+#define BD99992GW_REG_ADC1DATA3L 0x9b
+#define BD99992GW_REG_ADC1DATA3H 0x9c
+#define BD99992GW_REG_ADC1DATA4L 0x9d
+#define BD99992GW_REG_ADC1DATA4H 0x9e
+#define BD99992GW_REG_ADC1DATA5L 0x9f
+#define BD99992GW_REG_ADC1DATA5H 0xa0
+#define BD99992GW_REG_ADC1DATA6L 0xa1
+#define BD99992GW_REG_ADC1DATA6H 0xa2
+#define BD99992GW_REG_ADC1DATA7L 0xa3
+#define BD99992GW_REG_ADC1DATA7H 0xa4
 
 /**
  * Get the latest value from the sensor.
@@ -87,4 +87,4 @@ enum bd99992gw_adc_channel {
  */
 int bd99992gw_get_val(int idx, int *temp_ptr);
 
-#endif  /* __CROS_EC_TEMP_SENSOR_BD99992GW_H */
+#endif /* __CROS_EC_TEMP_SENSOR_BD99992GW_H */
diff --git a/driver/temp_sensor/ec_adc.c b/driver/temp_sensor/ec_adc.c
index 196d191e47..ca03cd6c6d 100644
--- a/driver/temp_sensor/ec_adc.c
+++ b/driver/temp_sensor/ec_adc.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,15 +23,15 @@ static int get_temp(int idx, int *temp_ptr)
 	if (temp_raw == ADC_READ_ERROR)
 		return EC_ERROR_UNKNOWN;
 
-	/* TODO : Need modification here if the result is not 10-bit */
+		/* TODO : Need modification here if the result is not 10-bit */
 
-	/* If there is no thermistor calculation function.
-	 *  1. Add adjusting function like thermistor_ncp15wb.c
-	 *  2. Place function here with ifdef
-	 *  3. define it on board.h
-	 */
+		/* If there is no thermistor calculation function.
+		 *  1. Add adjusting function like thermistor_ncp15wb.c
+		 *  2. Place function here with ifdef
+		 *  3. define it on board.h
+		 */
 #ifdef CONFIG_THERMISTOR_NCP15WB
-	*temp_ptr = ncp15wb_calculate_temp((uint16_t) temp_raw);
+	*temp_ptr = ncp15wb_calculate_temp((uint16_t)temp_raw);
 #else
 #error "Unknown thermistor for ec_adc"
 	return EC_ERROR_UNKNOWN;
@@ -45,7 +45,7 @@ int ec_adc_get_val(int idx, int *temp_ptr)
 	int ret;
 	int temp_c;
 
-	if(idx < 0 || idx >= ADC_CH_COUNT)
+	if (idx < 0 || idx >= ADC_CH_COUNT)
 		return EC_ERROR_INVAL;
 
 	ret = get_temp(idx, &temp_c);
diff --git a/driver/temp_sensor/ec_adc.h b/driver/temp_sensor/ec_adc.h
index 8ff213e95d..3bea83ffe8 100644
--- a/driver/temp_sensor/ec_adc.h
+++ b/driver/temp_sensor/ec_adc.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,4 +21,4 @@
  */
 int ec_adc_get_val(int idx, int *temp_ptr);
 
-#endif  /* __CROS_EC_TEMP_SENSOR_EC_ADC_H */
+#endif /* __CROS_EC_TEMP_SENSOR_EC_ADC_H */
diff --git a/driver/temp_sensor/f75303.c b/driver/temp_sensor/f75303.c
index 6b8895a252..e686537c31 100644
--- a/driver/temp_sensor/f75303.c
+++ b/driver/temp_sensor/f75303.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,15 +13,14 @@
 #include "console.h"
 
 static int temps[F75303_IDX_COUNT];
-static int8_t fake_temp[F75303_IDX_COUNT] = {-1, -1, -1};
+static int8_t fake_temp[F75303_IDX_COUNT] = { -1, -1, -1 };
 
 /**
  * Read 8 bits register from temp sensor.
  */
 static int raw_read8(const int offset, int *data)
 {
-	return i2c_read8(I2C_PORT_THERMAL, F75303_I2C_ADDR_FLAGS,
-			 offset, data);
+	return i2c_read8(I2C_PORT_THERMAL, F75303_I2C_ADDR_FLAGS, offset, data);
 }
 
 static int get_temp(const int offset, int *temp)
@@ -59,7 +58,7 @@ static void f75303_sensor_poll(void)
 }
 DECLARE_HOOK(HOOK_SECOND, f75303_sensor_poll, HOOK_PRIO_TEMP_SENSOR);
 
-static int f75303_set_fake_temp(int argc, char **argv)
+static int f75303_set_fake_temp(int argc, const char **argv)
 {
 	int index;
 	int value;
@@ -88,6 +87,5 @@ static int f75303_set_fake_temp(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(f75303, f75303_set_fake_temp,
-		"<index> <value>|off",
-		"Set fake temperature of sensor f75303.");
+DECLARE_CONSOLE_COMMAND(f75303, f75303_set_fake_temp, "<index> <value>|off",
+			"Set fake temperature of sensor f75303.");
diff --git a/driver/temp_sensor/f75303.h b/driver/temp_sensor/f75303.h
index bdfd2624f0..f8c85231da 100644
--- a/driver/temp_sensor/f75303.h
+++ b/driver/temp_sensor/f75303.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,9 +9,9 @@
 #define __CROS_EC_F75303_H
 
 #ifdef BOARD_MUSHU
-#define F75303_I2C_ADDR_FLAGS		0x4D
+#define F75303_I2C_ADDR_FLAGS 0x4D
 #else
-#define F75303_I2C_ADDR_FLAGS		0x4C
+#define F75303_I2C_ADDR_FLAGS 0x4C
 #endif
 
 enum f75303_index {
@@ -22,9 +22,9 @@ enum f75303_index {
 };
 
 /* F75303 register */
-#define F75303_TEMP_LOCAL		0x00
-#define F75303_TEMP_REMOTE1		0x01
-#define F75303_TEMP_REMOTE2		0x23
+#define F75303_TEMP_LOCAL 0x00
+#define F75303_TEMP_REMOTE1 0x01
+#define F75303_TEMP_REMOTE2 0x23
 
 /**
  * Get the last polled value of a sensor.
@@ -37,4 +37,4 @@ enum f75303_index {
  */
 int f75303_get_val(int idx, int *temp);
 
-#endif  /* __CROS_EC_F75303_H */
+#endif /* __CROS_EC_F75303_H */
diff --git a/driver/temp_sensor/g753.c b/driver/temp_sensor/g753.c
index e3946e4f43..8d94cac4f8 100644
--- a/driver/temp_sensor/g753.c
+++ b/driver/temp_sensor/g753.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -31,15 +31,14 @@ static int has_power(void)
 
 static int raw_read8(const int offset, int *data_ptr)
 {
-	return i2c_read8(I2C_PORT_THERMAL, G753_I2C_ADDR_FLAGS,
-			 offset, data_ptr);
+	return i2c_read8(I2C_PORT_THERMAL, G753_I2C_ADDR_FLAGS, offset,
+			 data_ptr);
 }
 
 #ifdef CONFIG_CMD_TEMP_SENSOR
 static int raw_write8(const int offset, int data)
 {
-	return i2c_write8(I2C_PORT_THERMAL, G753_I2C_ADDR_FLAGS,
-			  offset, data);
+	return i2c_write8(I2C_PORT_THERMAL, G753_I2C_ADDR_FLAGS, offset, data);
 }
 #endif
 
@@ -93,8 +92,7 @@ static void temp_sensor_poll(void)
 DECLARE_HOOK(HOOK_SECOND, temp_sensor_poll, HOOK_PRIO_TEMP_SENSOR);
 
 #ifdef CONFIG_CMD_TEMP_SENSOR
-static void print_temps(const char *name,
-			const int temp_reg,
+static void print_temps(const char *name, const int temp_reg,
 			const int high_limit_reg)
 {
 	int value;
@@ -106,7 +104,6 @@ static void print_temps(const char *name,
 
 	if (get_temp(high_limit_reg, &value) == EC_SUCCESS)
 		ccprintf("  High Alarm: %3dC\n", value);
-
 }
 
 static int print_status(void)
@@ -118,23 +115,22 @@ static int print_status(void)
 		return EC_ERROR_NOT_POWERED;
 	}
 
-	print_temps("Local", G753_TEMP_LOCAL,
-		    G753_LOCAL_TEMP_HIGH_LIMIT_R);
+	print_temps("Local", G753_TEMP_LOCAL, G753_LOCAL_TEMP_HIGH_LIMIT_R);
 
 	ccprintf("\n");
 
 	if (raw_read8(G753_STATUS, &value) == EC_SUCCESS)
-		ccprintf("STATUS:  %pb\n", BINARY_VALUE(value, 8));
+		ccprintf("STATUS:  0x%x\n", value);
 
 	if (raw_read8(G753_CONFIGURATION_R, &value) == EC_SUCCESS)
-		ccprintf("CONFIG:  %pb\n", BINARY_VALUE(value, 8));
+		ccprintf("CONFIG:  0x%x\n", value);
 
 	return EC_SUCCESS;
 }
 
-static int command_g753(int argc, char **argv)
+static int command_g753(int argc, const char **argv)
 {
-	char *command;
+	const char *command;
 	char *e;
 	int data;
 	int offset;
@@ -161,8 +157,7 @@ static int command_g753(int argc, char **argv)
 		rv = raw_read8(offset, &data);
 		if (rv < 0)
 			return rv;
-		ccprintf("Byte at offset 0x%02x is %pb\n",
-			 offset, BINARY_VALUE(data, 8));
+		ccprintf("Byte at offset 0x%02x is 0x%x\n", offset, data);
 		return rv;
 	}
 
@@ -185,7 +180,8 @@ static int command_g753(int argc, char **argv)
 
 	return rv;
 }
-DECLARE_CONSOLE_COMMAND(g753, command_g753,
+DECLARE_CONSOLE_COMMAND(
+	g753, command_g753,
 	"[settemp|setbyte <offset> <value>] or [getbyte <offset>]. "
 	"Temps in Celsius.",
 	"Print g753 temp sensor status or set parameters.");
diff --git a/driver/temp_sensor/g753.h b/driver/temp_sensor/g753.h
index 04c412bfbb..00f7fec8ac 100644
--- a/driver/temp_sensor/g753.h
+++ b/driver/temp_sensor/g753.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,36 +8,35 @@
 #ifndef __CROS_EC_G753_H
 #define __CROS_EC_G753_H
 
+#define G753_I2C_ADDR_FLAGS 0x48
 
-#define G753_I2C_ADDR_FLAGS			0x48
-
-#define G753_IDX_INTERNAL	0
+#define G753_IDX_INTERNAL 0
 
 /* G753 register */
-#define G753_TEMP_LOCAL				0x00
-#define G753_STATUS				0x02
-#define G753_CONFIGURATION_R			0x03
-#define G753_CONVERSION_RATE_R			0x04
-#define G753_LOCAL_TEMP_HIGH_LIMIT_R		0x05
-#define G753_CONFIGURATION_W			0x09
-#define G753_CONVERSION_RATE_W			0x0A
-#define G753_LOCAL_TEMP_HIGH_LIMIT_W		0x0B
-#define G753_ONESHOT				0x0F
-#define G753_Customer_Data_Log_Register_1	0x2D
-#define G753_Customer_Data_Log_Register_2	0x2E
-#define G753_Customer_Data_Log_Register_3	0x2F
-#define G753_ALERT_MODE				0xBF
-#define G753_CHIP_ID				0xFD
-#define G753_VENDOR_ID				0xFE
-#define G753_DEVICE_ID				0xFF
+#define G753_TEMP_LOCAL 0x00
+#define G753_STATUS 0x02
+#define G753_CONFIGURATION_R 0x03
+#define G753_CONVERSION_RATE_R 0x04
+#define G753_LOCAL_TEMP_HIGH_LIMIT_R 0x05
+#define G753_CONFIGURATION_W 0x09
+#define G753_CONVERSION_RATE_W 0x0A
+#define G753_LOCAL_TEMP_HIGH_LIMIT_W 0x0B
+#define G753_ONESHOT 0x0F
+#define G753_Customer_Data_Log_Register_1 0x2D
+#define G753_Customer_Data_Log_Register_2 0x2E
+#define G753_Customer_Data_Log_Register_3 0x2F
+#define G753_ALERT_MODE 0xBF
+#define G753_CHIP_ID 0xFD
+#define G753_VENDOR_ID 0xFE
+#define G753_DEVICE_ID 0xFF
 
 /* Config register bits */
-#define G753_CONFIGURATION_STANDBY		BIT(6)
-#define G753_CONFIGURATION_ALERT_MASK		BIT(7)
+#define G753_CONFIGURATION_STANDBY BIT(6)
+#define G753_CONFIGURATION_ALERT_MASK BIT(7)
 
 /* Status register bits */
-#define G753_STATUS_LOCAL_TEMP_HIGH_ALARM	BIT(6)
-#define G753_STATUS_BUSY			BIT(7)
+#define G753_STATUS_LOCAL_TEMP_HIGH_ALARM BIT(6)
+#define G753_STATUS_BUSY BIT(7)
 
 /**
  * Get the last polled value of a sensor.
@@ -50,4 +49,4 @@
  */
 int g753_get_val(int idx, int *temp_ptr);
 
-#endif  /* __CROS_EC_G753_H */
+#endif /* __CROS_EC_G753_H */
diff --git a/driver/temp_sensor/g78x.c b/driver/temp_sensor/g78x.c
index c4fd0ff243..82cb2d26e9 100644
--- a/driver/temp_sensor/g78x.c
+++ b/driver/temp_sensor/g78x.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -35,15 +35,14 @@ static int has_power(void)
 
 static int raw_read8(const int offset, int *data_ptr)
 {
-	return i2c_read8(I2C_PORT_THERMAL, G78X_I2C_ADDR_FLAGS,
-			 offset, data_ptr);
+	return i2c_read8(I2C_PORT_THERMAL, G78X_I2C_ADDR_FLAGS, offset,
+			 data_ptr);
 }
 
 #ifdef CONFIG_CMD_TEMP_SENSOR
 static int raw_write8(const int offset, int data)
 {
-	return i2c_write8(I2C_PORT_THERMAL, G78X_I2C_ADDR_FLAGS,
-			  offset, data);
+	return i2c_write8(I2C_PORT_THERMAL, G78X_I2C_ADDR_FLAGS, offset, data);
 }
 #endif
 
@@ -113,10 +112,8 @@ static void temp_sensor_poll(void)
 DECLARE_HOOK(HOOK_SECOND, temp_sensor_poll, HOOK_PRIO_TEMP_SENSOR);
 
 #ifdef CONFIG_CMD_TEMP_SENSOR
-static void print_temps(const char *name,
-			const int temp_reg,
-			const int therm_limit_reg,
-			const int high_limit_reg,
+static void print_temps(const char *name, const int temp_reg,
+			const int therm_limit_reg, const int high_limit_reg,
 			const int low_limit_reg)
 {
 	int value;
@@ -145,19 +142,15 @@ static int print_status(void)
 		return EC_ERROR_NOT_POWERED;
 	}
 
-	print_temps("Local", G78X_TEMP_LOCAL,
-		    G78X_LOCAL_TEMP_THERM_LIMIT,
-		    G78X_LOCAL_TEMP_HIGH_LIMIT_R,
-		    G78X_LOCAL_TEMP_LOW_LIMIT_R);
+	print_temps("Local", G78X_TEMP_LOCAL, G78X_LOCAL_TEMP_THERM_LIMIT,
+		    G78X_LOCAL_TEMP_HIGH_LIMIT_R, G78X_LOCAL_TEMP_LOW_LIMIT_R);
 
-	print_temps("Remote1", G78X_TEMP_REMOTE1,
-		    G78X_REMOTE1_TEMP_THERM_LIMIT,
+	print_temps("Remote1", G78X_TEMP_REMOTE1, G78X_REMOTE1_TEMP_THERM_LIMIT,
 		    G78X_REMOTE1_TEMP_HIGH_LIMIT_R,
 		    G78X_REMOTE1_TEMP_LOW_LIMIT_R);
 
 #ifdef CONFIG_TEMP_SENSOR_G782
-	print_temps("Remote2", G78X_TEMP_REMOTE1,
-		    G78X_REMOTE2_TEMP_THERM_LIMIT,
+	print_temps("Remote2", G78X_TEMP_REMOTE1, G78X_REMOTE2_TEMP_THERM_LIMIT,
 		    G78X_REMOTE2_TEMP_HIGH_LIMIT_R,
 		    G78X_REMOTE2_TEMP_LOW_LIMIT_R);
 #endif
@@ -165,20 +158,20 @@ static int print_status(void)
 	ccprintf("\n");
 
 	if (raw_read8(G78X_STATUS, &value) == EC_SUCCESS)
-		ccprintf("STATUS:  %pb\n", BINARY_VALUE(value, 8));
+		ccprintf("STATUS:  0x%x\n", value);
 
 #ifdef CONFIG_TEMP_SENSOR_G782
 	if (raw_read8(G78X_STATUS1, &value) == EC_SUCCESS)
-		ccprintf("STATUS1: %pb\n", BINARY_VALUE(value, 8));
+		ccprintf("STATUS1: 0x%x\n", value);
 #endif
 
 	if (raw_read8(G78X_CONFIGURATION_R, &value) == EC_SUCCESS)
-		ccprintf("CONFIG:  %pb\n", BINARY_VALUE(value, 8));
+		ccprintf("CONFIG:  0x%x\n", value);
 
 	return EC_SUCCESS;
 }
 
-static int command_g78x(int argc, char **argv)
+static int command_g78x(int argc, const char **argv)
 {
 	char *command;
 	char *e;
@@ -207,8 +200,7 @@ static int command_g78x(int argc, char **argv)
 		rv = raw_read8(offset, &data);
 		if (rv < 0)
 			return rv;
-		ccprintf("Byte at offset 0x%02x is %pb\n",
-			 offset, BINARY_VALUE(data, 8));
+		ccprintf("Byte at offset 0x%02x is 0x%x\n", offset, data);
 		return rv;
 	}
 
@@ -231,7 +223,8 @@ static int command_g78x(int argc, char **argv)
 
 	return rv;
 }
-DECLARE_CONSOLE_COMMAND(g78x, command_g78x,
+DECLARE_CONSOLE_COMMAND(
+	g78x, command_g78x,
 	"[settemp|setbyte <offset> <value>] or [getbyte <offset>]. "
 	"Temps in Celsius.",
 	"Print g781/g782 temp sensor status or set parameters.");
diff --git a/driver/temp_sensor/g78x.h b/driver/temp_sensor/g78x.h
index fdd987fcbd..70abc82a3f 100644
--- a/driver/temp_sensor/g78x.h
+++ b/driver/temp_sensor/g78x.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,118 +12,118 @@
 #error Cannot support both G781 and G782 together!
 #endif
 
-#define G78X_I2C_ADDR_FLAGS		0x4C
+#define G78X_I2C_ADDR_FLAGS 0x4C
 
-#define G78X_IDX_INTERNAL	0
-#define G78X_IDX_EXTERNAL1	1
-#define G78X_IDX_EXTERNAL2	2
+#define G78X_IDX_INTERNAL 0
+#define G78X_IDX_EXTERNAL1 1
+#define G78X_IDX_EXTERNAL2 2
 
 #if defined(CONFIG_TEMP_SENSOR_G781)
 /* G781 register */
-#define G78X_TEMP_LOCAL			0x00
-#define G78X_TEMP_REMOTE1		0x01
-#define G78X_STATUS			0x02
-#define G78X_CONFIGURATION_R		0x03
-#define G78X_CONVERSION_RATE_R		0x04
-#define G78X_LOCAL_TEMP_HIGH_LIMIT_R	0x05
-#define G78X_LOCAL_TEMP_LOW_LIMIT_R	0x06
-#define G78X_REMOTE1_TEMP_HIGH_LIMIT_R	0x07
-#define G78X_REMOTE1_TEMP_LOW_LIMIT_R	0x08
-#define G78X_CONFIGURATION_W		0x09
-#define G78X_CONVERSION_RATE_W		0x0a
-#define G78X_LOCAL_TEMP_HIGH_LIMIT_W	0x0b
-#define G78X_LOCAL_TEMP_LOW_LIMIT_W	0x0c
-#define G78X_REMOTE1_TEMP_HIGH_LIMIT_W	0x0d
-#define G78X_REMOTE1_TEMP_LOW_LIMIT_W	0x0e
-#define G78X_ONESHOT			0x0f
-#define G78X_REMOTE1_TEMP_EXTENDED	0x10
-#define G78X_REMOTE1_TEMP_OFFSET_HIGH	0x11
-#define G78X_REMOTE1_TEMP_OFFSET_EXTD	0x12
-#define G78X_REMOTE1_T_HIGH_LIMIT_EXTD	0x13
-#define G78X_REMOTE1_T_LOW_LIMIT_EXTD	0x14
-#define G78X_REMOTE1_TEMP_THERM_LIMIT	0x19
-#define G78X_LOCAL_TEMP_THERM_LIMIT	0x20
-#define G78X_THERM_HYSTERESIS		0x21
-#define G78X_ALERT_FAULT_QUEUE_CODE	0x22
-#define G78X_MANUFACTURER_ID		0xFE
-#define G78X_DEVICE_ID			0xFF
+#define G78X_TEMP_LOCAL 0x00
+#define G78X_TEMP_REMOTE1 0x01
+#define G78X_STATUS 0x02
+#define G78X_CONFIGURATION_R 0x03
+#define G78X_CONVERSION_RATE_R 0x04
+#define G78X_LOCAL_TEMP_HIGH_LIMIT_R 0x05
+#define G78X_LOCAL_TEMP_LOW_LIMIT_R 0x06
+#define G78X_REMOTE1_TEMP_HIGH_LIMIT_R 0x07
+#define G78X_REMOTE1_TEMP_LOW_LIMIT_R 0x08
+#define G78X_CONFIGURATION_W 0x09
+#define G78X_CONVERSION_RATE_W 0x0a
+#define G78X_LOCAL_TEMP_HIGH_LIMIT_W 0x0b
+#define G78X_LOCAL_TEMP_LOW_LIMIT_W 0x0c
+#define G78X_REMOTE1_TEMP_HIGH_LIMIT_W 0x0d
+#define G78X_REMOTE1_TEMP_LOW_LIMIT_W 0x0e
+#define G78X_ONESHOT 0x0f
+#define G78X_REMOTE1_TEMP_EXTENDED 0x10
+#define G78X_REMOTE1_TEMP_OFFSET_HIGH 0x11
+#define G78X_REMOTE1_TEMP_OFFSET_EXTD 0x12
+#define G78X_REMOTE1_T_HIGH_LIMIT_EXTD 0x13
+#define G78X_REMOTE1_T_LOW_LIMIT_EXTD 0x14
+#define G78X_REMOTE1_TEMP_THERM_LIMIT 0x19
+#define G78X_LOCAL_TEMP_THERM_LIMIT 0x20
+#define G78X_THERM_HYSTERESIS 0x21
+#define G78X_ALERT_FAULT_QUEUE_CODE 0x22
+#define G78X_MANUFACTURER_ID 0xFE
+#define G78X_DEVICE_ID 0xFF
 
 /* Config register bits */
-#define G78X_CONFIGURATION_STANDBY	BIT(6)
-#define G78X_CONFIGURATION_ALERT_MASK	BIT(7)
+#define G78X_CONFIGURATION_STANDBY BIT(6)
+#define G78X_CONFIGURATION_ALERT_MASK BIT(7)
 
 /* Status register bits */
-#define G78X_STATUS_LOCAL_TEMP_THERM_ALARM	BIT(0)
-#define G78X_STATUS_REMOTE1_TEMP_THERM_ALARM	BIT(1)
-#define G78X_STATUS_REMOTE1_TEMP_FAULT		BIT(2)
-#define G78X_STATUS_REMOTE1_TEMP_LOW_ALARM	BIT(3)
-#define G78X_STATUS_REMOTE1_TEMP_HIGH_ALARM	BIT(4)
-#define G78X_STATUS_LOCAL_TEMP_LOW_ALARM	BIT(5)
-#define G78X_STATUS_LOCAL_TEMP_HIGH_ALARM	BIT(6)
-#define G78X_STATUS_BUSY			BIT(7)
+#define G78X_STATUS_LOCAL_TEMP_THERM_ALARM BIT(0)
+#define G78X_STATUS_REMOTE1_TEMP_THERM_ALARM BIT(1)
+#define G78X_STATUS_REMOTE1_TEMP_FAULT BIT(2)
+#define G78X_STATUS_REMOTE1_TEMP_LOW_ALARM BIT(3)
+#define G78X_STATUS_REMOTE1_TEMP_HIGH_ALARM BIT(4)
+#define G78X_STATUS_LOCAL_TEMP_LOW_ALARM BIT(5)
+#define G78X_STATUS_LOCAL_TEMP_HIGH_ALARM BIT(6)
+#define G78X_STATUS_BUSY BIT(7)
 
 #elif defined(CONFIG_TEMP_SENSOR_G782)
 /* G782 register */
-#define G78X_TEMP_LOCAL			0x00
-#define G78X_TEMP_REMOTE1		0x01
-#define G78X_TEMP_REMOTE2		0x02
-#define G78X_STATUS			0x03
-#define G78X_CONFIGURATION_R		0x04
-#define G78X_CONFIGURATION_W		0x04
-#define G78X_CONVERSION_RATE_R		0x05
-#define G78X_CONVERSION_RATE_W		0x05
-#define G78X_LOCAL_TEMP_HIGH_LIMIT_R	0x06
-#define G78X_LOCAL_TEMP_HIGH_LIMIT_W	0x06
-#define G78X_LOCAL_TEMP_LOW_LIMIT_R	0x07
-#define G78X_LOCAL_TEMP_LOW_LIMIT_W	0x07
-#define G78X_REMOTE1_TEMP_HIGH_LIMIT_R	0x08
-#define G78X_REMOTE1_TEMP_HIGH_LIMIT_W	0x08
-#define G78X_REMOTE1_TEMP_LOW_LIMIT_R	0x09
-#define G78X_REMOTE1_TEMP_LOW_LIMIT_W	0x09
-#define G78X_REMOTE2_TEMP_HIGH_LIMIT_R	0x0a
-#define G78X_REMOTE2_TEMP_HIGH_LIMIT_W	0x0a
-#define G78X_REMOTE2_TEMP_LOW_LIMIT_R	0x0b
-#define G78X_REMOTE2_TEMP_LOW_LIMIT_W	0x0b
-#define G78X_ONESHOT			0x0c
-#define G78X_REMOTE1_TEMP_EXTENDED	0x0d
-#define G78X_REMOTE1_TEMP_OFFSET_HIGH	0x0e
-#define G78X_REMOTE1_TEMP_OFFSET_EXTD	0x0f
-#define G78X_REMOTE1_T_HIGH_LIMIT_EXTD	0x10
-#define G78X_REMOTE1_T_LOW_LIMIT_EXTD	0x11
-#define G78X_REMOTE1_TEMP_THERM_LIMIT	0x12
-#define G78X_REMOTE2_TEMP_EXTENDED	0x13
-#define G78X_REMOTE2_TEMP_OFFSET_HIGH	0x14
-#define G78X_REMOTE2_TEMP_OFFSET_EXTD	0x15
-#define G78X_REMOTE2_T_HIGH_LIMIT_EXTD	0x16
-#define G78X_REMOTE2_T_LOW_LIMIT_EXTD	0x17
-#define G78X_REMOTE2_TEMP_THERM_LIMIT	0x18
-#define G78X_STATUS1			0x19
-#define G78X_LOCAL_TEMP_THERM_LIMIT	0x20
-#define G78X_THERM_HYSTERESIS		0x21
-#define G78X_ALERT_FAULT_QUEUE_CODE	0x22
-#define G78X_MANUFACTURER_ID		0xFE
-#define G78X_DEVICE_ID			0xFF
+#define G78X_TEMP_LOCAL 0x00
+#define G78X_TEMP_REMOTE1 0x01
+#define G78X_TEMP_REMOTE2 0x02
+#define G78X_STATUS 0x03
+#define G78X_CONFIGURATION_R 0x04
+#define G78X_CONFIGURATION_W 0x04
+#define G78X_CONVERSION_RATE_R 0x05
+#define G78X_CONVERSION_RATE_W 0x05
+#define G78X_LOCAL_TEMP_HIGH_LIMIT_R 0x06
+#define G78X_LOCAL_TEMP_HIGH_LIMIT_W 0x06
+#define G78X_LOCAL_TEMP_LOW_LIMIT_R 0x07
+#define G78X_LOCAL_TEMP_LOW_LIMIT_W 0x07
+#define G78X_REMOTE1_TEMP_HIGH_LIMIT_R 0x08
+#define G78X_REMOTE1_TEMP_HIGH_LIMIT_W 0x08
+#define G78X_REMOTE1_TEMP_LOW_LIMIT_R 0x09
+#define G78X_REMOTE1_TEMP_LOW_LIMIT_W 0x09
+#define G78X_REMOTE2_TEMP_HIGH_LIMIT_R 0x0a
+#define G78X_REMOTE2_TEMP_HIGH_LIMIT_W 0x0a
+#define G78X_REMOTE2_TEMP_LOW_LIMIT_R 0x0b
+#define G78X_REMOTE2_TEMP_LOW_LIMIT_W 0x0b
+#define G78X_ONESHOT 0x0c
+#define G78X_REMOTE1_TEMP_EXTENDED 0x0d
+#define G78X_REMOTE1_TEMP_OFFSET_HIGH 0x0e
+#define G78X_REMOTE1_TEMP_OFFSET_EXTD 0x0f
+#define G78X_REMOTE1_T_HIGH_LIMIT_EXTD 0x10
+#define G78X_REMOTE1_T_LOW_LIMIT_EXTD 0x11
+#define G78X_REMOTE1_TEMP_THERM_LIMIT 0x12
+#define G78X_REMOTE2_TEMP_EXTENDED 0x13
+#define G78X_REMOTE2_TEMP_OFFSET_HIGH 0x14
+#define G78X_REMOTE2_TEMP_OFFSET_EXTD 0x15
+#define G78X_REMOTE2_T_HIGH_LIMIT_EXTD 0x16
+#define G78X_REMOTE2_T_LOW_LIMIT_EXTD 0x17
+#define G78X_REMOTE2_TEMP_THERM_LIMIT 0x18
+#define G78X_STATUS1 0x19
+#define G78X_LOCAL_TEMP_THERM_LIMIT 0x20
+#define G78X_THERM_HYSTERESIS 0x21
+#define G78X_ALERT_FAULT_QUEUE_CODE 0x22
+#define G78X_MANUFACTURER_ID 0xFE
+#define G78X_DEVICE_ID 0xFF
 
 /* Config register bits */
-#define G78X_CONFIGURATION_REMOTE2_DIS	BIT(5)
-#define G78X_CONFIGURATION_STANDBY	BIT(6)
-#define G78X_CONFIGURATION_ALERT_MASK	BIT(7)
+#define G78X_CONFIGURATION_REMOTE2_DIS BIT(5)
+#define G78X_CONFIGURATION_STANDBY BIT(6)
+#define G78X_CONFIGURATION_ALERT_MASK BIT(7)
 
 /* Status register bits */
-#define G78X_STATUS_LOCAL_TEMP_LOW_ALARM	BIT(0)
-#define G78X_STATUS_LOCAL_TEMP_HIGH_ALARM	BIT(1)
-#define G78X_STATUS_LOCAL_TEMP_THERM_ALARM	BIT(2)
-#define G78X_STATUS_REMOTE2_TEMP_THERM_ALARM	BIT(3)
-#define G78X_STATUS_REMOTE1_TEMP_THERM_ALARM	BIT(4)
-#define G78X_STATUS_REMOTE2_TEMP_FAULT		BIT(5)
-#define G78X_STATUS_REMOTE1_TEMP_FAULT		BIT(6)
-#define G78X_STATUS_BUSY			BIT(7)
+#define G78X_STATUS_LOCAL_TEMP_LOW_ALARM BIT(0)
+#define G78X_STATUS_LOCAL_TEMP_HIGH_ALARM BIT(1)
+#define G78X_STATUS_LOCAL_TEMP_THERM_ALARM BIT(2)
+#define G78X_STATUS_REMOTE2_TEMP_THERM_ALARM BIT(3)
+#define G78X_STATUS_REMOTE1_TEMP_THERM_ALARM BIT(4)
+#define G78X_STATUS_REMOTE2_TEMP_FAULT BIT(5)
+#define G78X_STATUS_REMOTE1_TEMP_FAULT BIT(6)
+#define G78X_STATUS_BUSY BIT(7)
 
 /* Status1 register bits */
-#define G78X_STATUS_REMOTE2_TEMP_LOW_ALARM	BIT(4)
-#define G78X_STATUS_REMOTE2_TEMP_HIGH_ALARM	BIT(5)
-#define G78X_STATUS_REMOTE1_TEMP_LOW_ALARM	BIT(6)
-#define G78X_STATUS_REMOTE1_TEMP_HIGH_ALARM	BIT(7)
+#define G78X_STATUS_REMOTE2_TEMP_LOW_ALARM BIT(4)
+#define G78X_STATUS_REMOTE2_TEMP_HIGH_ALARM BIT(5)
+#define G78X_STATUS_REMOTE1_TEMP_LOW_ALARM BIT(6)
+#define G78X_STATUS_REMOTE1_TEMP_HIGH_ALARM BIT(7)
 #endif
 
 /**
@@ -137,4 +137,4 @@
  */
 int g78x_get_val(int idx, int *temp_ptr);
 
-#endif  /* __CROS_EC_G78X_H */
+#endif /* __CROS_EC_G78X_H */
diff --git a/driver/temp_sensor/oti502.c b/driver/temp_sensor/oti502.c
index b58d1c3e96..2051df89f6 100644
--- a/driver/temp_sensor/oti502.c
+++ b/driver/temp_sensor/oti502.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,13 +12,13 @@
 #include "hooks.h"
 #include "util.h"
 
-static int temp_val_ambient;	/* Ambient is chip temperature*/
-static int temp_val_object;		/* Object is IR temperature */
+static int temp_val_ambient; /* Ambient is chip temperature*/
+static int temp_val_object; /* Object is IR temperature */
 
 static int oti502_read_block(const int offset, uint8_t *data, int len)
 {
-	return i2c_read_block(I2C_PORT_THERMAL, OTI502_I2C_ADDR_FLAGS,
-			 offset, data, len);
+	return i2c_read_block(I2C_PORT_THERMAL, OTI502_I2C_ADDR_FLAGS, offset,
+			      data, len);
 }
 
 int oti502_get_val(int idx, int *temp_ptr)
diff --git a/driver/temp_sensor/oti502.h b/driver/temp_sensor/oti502.h
index 4e846282c1..fd09362589 100644
--- a/driver/temp_sensor/oti502.h
+++ b/driver/temp_sensor/oti502.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,10 +8,10 @@
 #ifndef __CROS_EC_OTI502_H
 #define __CROS_EC_OTI502_H
 
-#define OTI502_I2C_ADDR_FLAGS		0x10
+#define OTI502_I2C_ADDR_FLAGS 0x10
 
-#define OTI502_IDX_AMBIENT	0
-#define OTI502_IDX_OBJECT	1
+#define OTI502_IDX_AMBIENT 0
+#define OTI502_IDX_OBJECT 1
 
 /**
  * Get the last polled value of a sensor.
@@ -24,4 +24,4 @@
  */
 int oti502_get_val(int idx, int *temp_ptr);
 
-#endif  /* __CROS_EC_OTI502_H */
+#endif /* __CROS_EC_OTI502_H */
diff --git a/driver/temp_sensor/pct2075.c b/driver/temp_sensor/pct2075.c
index a5458c72fb..9c7b7190e9 100644
--- a/driver/temp_sensor/pct2075.c
+++ b/driver/temp_sensor/pct2075.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,7 +21,7 @@
 #define PCT2075_SHIFT1 (16 - PCT2075_RESOLUTION)
 #define PCT2075_SHIFT2 (PCT2075_RESOLUTION - 8)
 
-#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
 
 static int temp_mk_local[PCT2075_COUNT];
 
@@ -35,8 +35,8 @@ static int raw_read16(int sensor, const int offset, int *data_ptr)
 		return EC_ERROR_NOT_POWERED;
 #endif
 	return i2c_read16(pct2075_sensors[sensor].i2c_port,
-			  pct2075_sensors[sensor].i2c_addr_flags,
-			  offset, data_ptr);
+			  pct2075_sensors[sensor].i2c_addr_flags, offset,
+			  data_ptr);
 }
 
 static int get_reg_temp(int sensor, int *temp_ptr)
@@ -90,6 +90,6 @@ DECLARE_HOOK(HOOK_SECOND, pct2075_poll, HOOK_PRIO_TEMP_SENSOR);
 
 void pct2075_init(void)
 {
-/* Incase we need to initialize somthing */
+	/* Incase we need to initialize somthing */
 }
 DECLARE_HOOK(HOOK_INIT, pct2075_init, HOOK_PRIO_DEFAULT);
diff --git a/driver/temp_sensor/sb_tsi.c b/driver/temp_sensor/sb_tsi.c
index ffcd924b0e..0c58fb88dc 100644
--- a/driver/temp_sensor/sb_tsi.c
+++ b/driver/temp_sensor/sb_tsi.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,8 +19,8 @@
 
 static int raw_read8(const int offset, int *data_ptr)
 {
-	return i2c_read8(I2C_PORT_THERMAL_AP, SB_TSI_I2C_ADDR_FLAGS,
-			 offset, data_ptr);
+	return i2c_read8(I2C_PORT_THERMAL_AP, SB_TSI_I2C_ADDR_FLAGS, offset,
+			 data_ptr);
 }
 
 int sb_tsi_get_val(int idx, int *temp_ptr)
diff --git a/driver/temp_sensor/thermistor.c b/driver/temp_sensor/thermistor.c
index bef10416b6..25fe0f56e8 100644
--- a/driver/temp_sensor/thermistor.c
+++ b/driver/temp_sensor/thermistor.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,13 +9,14 @@
  */
 
 #include "adc.h"
+#include "builtin/assert.h"
 #include "common.h"
 #include "gpio.h"
 #include "temp_sensor/thermistor.h"
 #include "util.h"
 
 int thermistor_linear_interpolate(uint16_t mv,
-		const struct thermistor_info *info)
+				  const struct thermistor_info *info)
 {
 	const struct thermistor_data_pair *data = info->data;
 	int v_high = 0, v_low = 0, t_low, t_high, num_steps;
@@ -66,7 +67,7 @@ int thermistor_linear_interpolate(uint16_t mv,
 	return t_low + num_steps;
 }
 
-#if defined(CONFIG_STEINHART_HART_3V3_51K1_47K_4050B) || \
+#if defined(CONFIG_STEINHART_HART_3V3_51K1_47K_4050B) ||     \
 	defined(CONFIG_STEINHART_HART_3V3_13K7_47K_4050B) || \
 	defined(CONFIG_STEINHART_HART_6V0_51K1_47K_4050B) || \
 	defined(CONFIG_STEINHART_HART_3V0_22K6_47K_4050B) || \
@@ -103,19 +104,19 @@ int thermistor_get_temperature(int idx_adc, int *temp_ptr,
  */
 #define THERMISTOR_SCALING_FACTOR_51_47 11
 static const struct thermistor_data_pair thermistor_data_51_47[] = {
-	{ 2484 / THERMISTOR_SCALING_FACTOR_51_47, 0   },
-	{ 2142 / THERMISTOR_SCALING_FACTOR_51_47, 10  },
-	{ 1767 / THERMISTOR_SCALING_FACTOR_51_47, 20  },
-	{ 1400 / THERMISTOR_SCALING_FACTOR_51_47, 30  },
-	{ 1072 / THERMISTOR_SCALING_FACTOR_51_47, 40  },
-	{  802 / THERMISTOR_SCALING_FACTOR_51_47, 50  },
-	{  593 / THERMISTOR_SCALING_FACTOR_51_47, 60  },
-	{  436 / THERMISTOR_SCALING_FACTOR_51_47, 70  },
-	{  321 / THERMISTOR_SCALING_FACTOR_51_47, 80  },
-	{  276 / THERMISTOR_SCALING_FACTOR_51_47, 85  },
-	{  237 / THERMISTOR_SCALING_FACTOR_51_47, 90  },
-	{  204 / THERMISTOR_SCALING_FACTOR_51_47, 95  },
-	{  177 / THERMISTOR_SCALING_FACTOR_51_47, 100 },
+	{ 2484 / THERMISTOR_SCALING_FACTOR_51_47, 0 },
+	{ 2142 / THERMISTOR_SCALING_FACTOR_51_47, 10 },
+	{ 1767 / THERMISTOR_SCALING_FACTOR_51_47, 20 },
+	{ 1400 / THERMISTOR_SCALING_FACTOR_51_47, 30 },
+	{ 1072 / THERMISTOR_SCALING_FACTOR_51_47, 40 },
+	{ 802 / THERMISTOR_SCALING_FACTOR_51_47, 50 },
+	{ 593 / THERMISTOR_SCALING_FACTOR_51_47, 60 },
+	{ 436 / THERMISTOR_SCALING_FACTOR_51_47, 70 },
+	{ 321 / THERMISTOR_SCALING_FACTOR_51_47, 80 },
+	{ 276 / THERMISTOR_SCALING_FACTOR_51_47, 85 },
+	{ 237 / THERMISTOR_SCALING_FACTOR_51_47, 90 },
+	{ 204 / THERMISTOR_SCALING_FACTOR_51_47, 95 },
+	{ 177 / THERMISTOR_SCALING_FACTOR_51_47, 100 },
 };
 
 static const struct thermistor_info thermistor_info_51_47 = {
@@ -127,7 +128,7 @@ static const struct thermistor_info thermistor_info_51_47 = {
 int get_temp_3v3_51k1_47k_4050b(int idx_adc, int *temp_ptr)
 {
 	return thermistor_get_temperature(idx_adc, temp_ptr,
-			&thermistor_info_51_47);
+					  &thermistor_info_51_47);
 }
 #endif /* CONFIG_STEINHART_HART_3V3_51K1_47K_4050B */
 
@@ -139,19 +140,19 @@ int get_temp_3v3_51k1_47k_4050b(int idx_adc, int *temp_ptr)
  */
 #define THERMISTOR_SCALING_FACTOR_13_47 13
 static const struct thermistor_data_pair thermistor_data_13_47[] = {
-	{ 3033 / THERMISTOR_SCALING_FACTOR_13_47, 0   },
-	{ 2882 / THERMISTOR_SCALING_FACTOR_13_47, 10  },
-	{ 2677 / THERMISTOR_SCALING_FACTOR_13_47, 20  },
-	{ 2420 / THERMISTOR_SCALING_FACTOR_13_47, 30  },
-	{ 2119 / THERMISTOR_SCALING_FACTOR_13_47, 40  },
-	{ 1799 / THERMISTOR_SCALING_FACTOR_13_47, 50  },
-	{ 1485 / THERMISTOR_SCALING_FACTOR_13_47, 60  },
-	{ 1197 / THERMISTOR_SCALING_FACTOR_13_47, 70  },
-	{  947 / THERMISTOR_SCALING_FACTOR_13_47, 80  },
-	{  839 / THERMISTOR_SCALING_FACTOR_13_47, 85  },
-	{  741 / THERMISTOR_SCALING_FACTOR_13_47, 90  },
-	{  653 / THERMISTOR_SCALING_FACTOR_13_47, 95  },
-	{  576 / THERMISTOR_SCALING_FACTOR_13_47, 100 },
+	{ 3033 / THERMISTOR_SCALING_FACTOR_13_47, 0 },
+	{ 2882 / THERMISTOR_SCALING_FACTOR_13_47, 10 },
+	{ 2677 / THERMISTOR_SCALING_FACTOR_13_47, 20 },
+	{ 2420 / THERMISTOR_SCALING_FACTOR_13_47, 30 },
+	{ 2119 / THERMISTOR_SCALING_FACTOR_13_47, 40 },
+	{ 1799 / THERMISTOR_SCALING_FACTOR_13_47, 50 },
+	{ 1485 / THERMISTOR_SCALING_FACTOR_13_47, 60 },
+	{ 1197 / THERMISTOR_SCALING_FACTOR_13_47, 70 },
+	{ 947 / THERMISTOR_SCALING_FACTOR_13_47, 80 },
+	{ 839 / THERMISTOR_SCALING_FACTOR_13_47, 85 },
+	{ 741 / THERMISTOR_SCALING_FACTOR_13_47, 90 },
+	{ 653 / THERMISTOR_SCALING_FACTOR_13_47, 95 },
+	{ 576 / THERMISTOR_SCALING_FACTOR_13_47, 100 },
 };
 
 static const struct thermistor_info thermistor_info_13_47 = {
@@ -163,7 +164,7 @@ static const struct thermistor_info thermistor_info_13_47 = {
 int get_temp_3v3_13k7_47k_4050b(int idx_adc, int *temp_ptr)
 {
 	return thermistor_get_temperature(idx_adc, temp_ptr,
-			&thermistor_info_13_47);
+					  &thermistor_info_13_47);
 }
 #endif /* CONFIG_STEINHART_HART_3V3_13K7_47K_4050B */
 
@@ -175,19 +176,19 @@ int get_temp_3v3_13k7_47k_4050b(int idx_adc, int *temp_ptr)
  */
 #define THERMISTOR_SCALING_FACTOR_6V0_51_47 18
 static const struct thermistor_data_pair thermistor_data_6v0_51_47[] = {
-	{ 4517 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 0   },
-	{ 3895 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 10  },
-	{ 3214 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 20  },
-	{ 2546 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 30  },
-	{ 1950 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 40  },
-	{ 1459 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 50  },
-	{ 1079 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 60  },
-	{  794 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 70  },
-	{  584 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 80  },
-	{  502 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 85  },
-	{  432 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 90  },
-	{  372 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 95  },
-	{  322 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 100 },
+	{ 4517 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 0 },
+	{ 3895 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 10 },
+	{ 3214 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 20 },
+	{ 2546 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 30 },
+	{ 1950 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 40 },
+	{ 1459 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 50 },
+	{ 1079 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 60 },
+	{ 794 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 70 },
+	{ 584 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 80 },
+	{ 502 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 85 },
+	{ 432 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 90 },
+	{ 372 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 95 },
+	{ 322 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 100 },
 };
 
 static const struct thermistor_info thermistor_info_6v0_51_47 = {
@@ -199,7 +200,7 @@ static const struct thermistor_info thermistor_info_6v0_51_47 = {
 int get_temp_6v0_51k1_47k_4050b(int idx_adc, int *temp_ptr)
 {
 	return thermistor_get_temperature(idx_adc, temp_ptr,
-			&thermistor_info_6v0_51_47);
+					  &thermistor_info_6v0_51_47);
 }
 #endif /* CONFIG_STEINHART_HART_6V0_51K1_47K_4050B */
 
@@ -211,19 +212,19 @@ int get_temp_6v0_51k1_47k_4050b(int idx_adc, int *temp_ptr)
  */
 #define THERMISTOR_SCALING_FACTOR_22_47 11
 static const struct thermistor_data_pair thermistor_data_22_47[] = {
-	{ 2619 / THERMISTOR_SCALING_FACTOR_22_47, 0   },
-	{ 2421 / THERMISTOR_SCALING_FACTOR_22_47, 10  },
-	{ 2168 / THERMISTOR_SCALING_FACTOR_22_47, 20  },
-	{ 1875 / THERMISTOR_SCALING_FACTOR_22_47, 30  },
-	{ 1563 / THERMISTOR_SCALING_FACTOR_22_47, 40  },
-	{ 1262 / THERMISTOR_SCALING_FACTOR_22_47, 50  },
-	{  994 / THERMISTOR_SCALING_FACTOR_22_47, 60  },
-	{  769 / THERMISTOR_SCALING_FACTOR_22_47, 70  },
-	{  588 / THERMISTOR_SCALING_FACTOR_22_47, 80  },
-	{  513 / THERMISTOR_SCALING_FACTOR_22_47, 85  },
-	{  448 / THERMISTOR_SCALING_FACTOR_22_47, 90  },
-	{  390 / THERMISTOR_SCALING_FACTOR_22_47, 95  },
-	{  340 / THERMISTOR_SCALING_FACTOR_22_47, 100 },
+	{ 2619 / THERMISTOR_SCALING_FACTOR_22_47, 0 },
+	{ 2421 / THERMISTOR_SCALING_FACTOR_22_47, 10 },
+	{ 2168 / THERMISTOR_SCALING_FACTOR_22_47, 20 },
+	{ 1875 / THERMISTOR_SCALING_FACTOR_22_47, 30 },
+	{ 1563 / THERMISTOR_SCALING_FACTOR_22_47, 40 },
+	{ 1262 / THERMISTOR_SCALING_FACTOR_22_47, 50 },
+	{ 994 / THERMISTOR_SCALING_FACTOR_22_47, 60 },
+	{ 769 / THERMISTOR_SCALING_FACTOR_22_47, 70 },
+	{ 588 / THERMISTOR_SCALING_FACTOR_22_47, 80 },
+	{ 513 / THERMISTOR_SCALING_FACTOR_22_47, 85 },
+	{ 448 / THERMISTOR_SCALING_FACTOR_22_47, 90 },
+	{ 390 / THERMISTOR_SCALING_FACTOR_22_47, 95 },
+	{ 340 / THERMISTOR_SCALING_FACTOR_22_47, 100 },
 };
 
 static const struct thermistor_info thermistor_info_22_47 = {
@@ -235,7 +236,7 @@ static const struct thermistor_info thermistor_info_22_47 = {
 int get_temp_3v0_22k6_47k_4050b(int idx_adc, int *temp_ptr)
 {
 	return thermistor_get_temperature(idx_adc, temp_ptr,
-			&thermistor_info_22_47);
+					  &thermistor_info_22_47);
 }
 #endif /* CONFIG_STEINHART_HART_3V0_22K6_47K_4050B */
 
@@ -247,16 +248,16 @@ int get_temp_3v0_22k6_47k_4050b(int idx_adc, int *temp_ptr)
  */
 #define THERMISTOR_SCALING_FACTOR_31_47 11
 static const struct thermistor_data_pair thermistor_data_31_47[] = {
-	{ 2753 / THERMISTOR_SCALING_FACTOR_31_47, 0   },
-	{ 2487 / THERMISTOR_SCALING_FACTOR_31_47, 10  },
-	{ 2165 / THERMISTOR_SCALING_FACTOR_31_47, 20  },
-	{ 1813 / THERMISTOR_SCALING_FACTOR_31_47, 30  },
-	{ 1145 / THERMISTOR_SCALING_FACTOR_31_47, 50  },
-	{  878 / THERMISTOR_SCALING_FACTOR_31_47, 60  },
-	{  665 / THERMISTOR_SCALING_FACTOR_31_47, 70  },
-	{  500 / THERMISTOR_SCALING_FACTOR_31_47, 80  },
-	{  375 / THERMISTOR_SCALING_FACTOR_31_47, 90  },
-	{  282 / THERMISTOR_SCALING_FACTOR_31_47, 100 },
+	{ 2753 / THERMISTOR_SCALING_FACTOR_31_47, 0 },
+	{ 2487 / THERMISTOR_SCALING_FACTOR_31_47, 10 },
+	{ 2165 / THERMISTOR_SCALING_FACTOR_31_47, 20 },
+	{ 1813 / THERMISTOR_SCALING_FACTOR_31_47, 30 },
+	{ 1145 / THERMISTOR_SCALING_FACTOR_31_47, 50 },
+	{ 878 / THERMISTOR_SCALING_FACTOR_31_47, 60 },
+	{ 665 / THERMISTOR_SCALING_FACTOR_31_47, 70 },
+	{ 500 / THERMISTOR_SCALING_FACTOR_31_47, 80 },
+	{ 375 / THERMISTOR_SCALING_FACTOR_31_47, 90 },
+	{ 282 / THERMISTOR_SCALING_FACTOR_31_47, 100 },
 };
 
 static const struct thermistor_info thermistor_info_31_47 = {
@@ -268,6 +269,6 @@ static const struct thermistor_info thermistor_info_31_47 = {
 int get_temp_3v3_30k9_47k_4050b(int idx_adc, int *temp_ptr)
 {
 	return thermistor_get_temperature(idx_adc, temp_ptr,
-			&thermistor_info_31_47);
+					  &thermistor_info_31_47);
 }
 #endif /* CONFIG_STEINHART_HART_3V3_30K9_47K_4050B */
diff --git a/driver/temp_sensor/thermistor_ncp15wb.c b/driver/temp_sensor/thermistor_ncp15wb.c
index dba06ee326..93896cfcc2 100644
--- a/driver/temp_sensor/thermistor_ncp15wb.c
+++ b/driver/temp_sensor/thermistor_ncp15wb.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,30 +15,30 @@
  * For 50C through 100C, use linear interpolation from discreet points
  * in table below. For temps < 50C, use a simplified linear function.
  */
-#define ADC_DISCREET_RANGE_START_TEMP	50
+#define ADC_DISCREET_RANGE_START_TEMP 50
 /* 10 bit ADC result corresponding to START_TEMP */
-#define ADC_DISCREET_RANGE_START_RESULT	407
+#define ADC_DISCREET_RANGE_START_RESULT 407
 
-#define ADC_DISCREET_RANGE_LIMIT_TEMP	100
+#define ADC_DISCREET_RANGE_LIMIT_TEMP 100
 /* 10 bit ADC result corresponding to LIMIT_TEMP */
-#define ADC_DISCREET_RANGE_LIMIT_RESULT	107
+#define ADC_DISCREET_RANGE_LIMIT_RESULT 107
 
 /* Table entries in steppings of 5C */
-#define ADC_DISCREET_RANGE_STEP		5
+#define ADC_DISCREET_RANGE_STEP 5
 
 /* Discreet range ADC results (9 bit) per temperature, in 5 degree steps */
 static const uint8_t adc_result[] = {
-	203,	/* 50 C */
-	178,	/* 55 C */
-	157,	/* 60 C */
-	138,	/* 65 C */
-	121,	/* 70 C */
-	106,	/* 75 C */
-	93,	/* 80 C */
-	81,	/* 85 C */
-	70,	/* 90 C */
-	61,	/* 95 C */
-	53,	/* 100 C */
+	203, /* 50 C */
+	178, /* 55 C */
+	157, /* 60 C */
+	138, /* 65 C */
+	121, /* 70 C */
+	106, /* 75 C */
+	93, /* 80 C */
+	81, /* 85 C */
+	70, /* 90 C */
+	61, /* 95 C */
+	53, /* 100 C */
 };
 
 /*
@@ -46,8 +46,9 @@ static const uint8_t adc_result[] = {
  * to 50C, the temperature curve is roughly linear, so we don't need to include
  * data points in our table.
  */
-#define adc_to_temp(result) (ADC_DISCREET_RANGE_START_TEMP - \
-	(((result) - ADC_DISCREET_RANGE_START_RESULT) * 3 + 16) / 32)
+#define adc_to_temp(result)              \
+	(ADC_DISCREET_RANGE_START_TEMP - \
+	 (((result)-ADC_DISCREET_RANGE_START_RESULT) * 3 + 16) / 32)
 
 /* Convert ADC result (10 bit) to temperature in celsius */
 int ncp15wb_calculate_temp(uint16_t adc)
@@ -72,8 +73,7 @@ int ncp15wb_calculate_temp(uint16_t adc)
 		tail = ARRAY_SIZE(adc_result) - 1;
 		while (head != tail) {
 			mid = (head + tail) / 2;
-			if (adc_result[mid] >= adc &&
-			    adc_result[mid+1] < adc)
+			if (adc_result[mid] >= adc && adc_result[mid + 1] < adc)
 				break;
 			if (adc_result[mid] > adc)
 				head = mid + 1;
@@ -85,7 +85,9 @@ int ncp15wb_calculate_temp(uint16_t adc)
 		if (head != tail) {
 			delta = adc_result[mid] - adc_result[mid + 1];
 			step = ((adc_result[mid] - adc) *
-				ADC_DISCREET_RANGE_STEP + delta / 2) / delta;
+					ADC_DISCREET_RANGE_STEP +
+				delta / 2) /
+			       delta;
 		} else {
 			/* Edge case where adc = max */
 			mid = head;
diff --git a/driver/temp_sensor/tmp006.c b/driver/temp_sensor/tmp006.c
index 96922c857c..e3cb62276a 100644
--- a/driver/temp_sensor/tmp006.c
+++ b/driver/temp_sensor/tmp006.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,7 +19,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_THERMAL, outstr)
-#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
 
 /*
  * Alg 0 was what's in the TMP006 User's Guide.  Alg 1 is Alg 0, but with
@@ -30,23 +30,23 @@
 #define ALGORITHM_PARAMS 12
 
 /* Flags for tdata->fail */
-#define FAIL_INIT        BIT(0)  /* Just initialized */
-#define FAIL_POWER       BIT(1)  /* Sensor not powered */
-#define FAIL_I2C         BIT(2)  /* I2C communication error */
-#define FAIL_NOT_READY   BIT(3)  /* Data not ready */
+#define FAIL_INIT BIT(0) /* Just initialized */
+#define FAIL_POWER BIT(1) /* Sensor not powered */
+#define FAIL_I2C BIT(2) /* I2C communication error */
+#define FAIL_NOT_READY BIT(3) /* Data not ready */
 
 /* State and conversion factors to track for each sensor */
 struct tmp006_data_t {
 	/* chip info */
-	int16_t v_raw;		 /* TMP006_REG_VOBJ */
-	int16_t t_raw0;		 /* TMP006_REG_TDIE */
-	int fail;		 /* Fail flags; non-zero if last read failed */
+	int16_t v_raw; /* TMP006_REG_VOBJ */
+	int16_t t_raw0; /* TMP006_REG_TDIE */
+	int fail; /* Fail flags; non-zero if last read failed */
 	/* calibration params */
-	float s0, a1, a2;	 /* Sensitivity factors */
-	float b0, b1, b2;	 /* Self-heating correction */
-	float c2;		 /* Seebeck effect */
-	float d0, d1, ds;	 /* Tdie filter and slope adjustment */
-	float e0, e1;		 /* Tobj output filter */
+	float s0, a1, a2; /* Sensitivity factors */
+	float b0, b1, b2; /* Self-heating correction */
+	float c2; /* Seebeck effect */
+	float d0, d1, ds; /* Tdie filter and slope adjustment */
+	float e0, e1; /* Tobj output filter */
 	/* FIR filter stages */
 	float tdie1, tobj1;
 };
@@ -57,7 +57,7 @@ static const struct tmp006_data_t tmp006_data_default = {
 	.fail = FAIL_INIT,
 
 	/* Alg 0 params from User's Guide */
-	.s0 = 0.0f,				/* zero == "uncalibrated" */
+	.s0 = 0.0f, /* zero == "uncalibrated" */
 	.a1 = 1.75e-3f,
 	.a2 = -1.678e-5f,
 	.b0 = -2.94e-5f,
@@ -104,8 +104,7 @@ static void tmp006_poll_sensor(int sensor_id)
 	 * data ready; otherwise, we read garbage data.
 	 */
 	if (tdata->fail & (FAIL_POWER | FAIL_INIT)) {
-		rv = i2c_read16(TMP006_PORT(addr_flags),
-				TMP006_REG(addr_flags),
+		rv = i2c_read16(TMP006_PORT(addr_flags), TMP006_REG(addr_flags),
 				TMP006_REG_CONFIG, &v);
 		if (rv) {
 			tdata->fail |= FAIL_I2C;
@@ -117,16 +116,14 @@ static void tmp006_poll_sensor(int sensor_id)
 		}
 	}
 
-	rv = i2c_read16(TMP006_PORT(addr_flags),
-			TMP006_REG(addr_flags),
+	rv = i2c_read16(TMP006_PORT(addr_flags), TMP006_REG(addr_flags),
 			TMP006_REG_TDIE, &t);
 	if (rv) {
 		tdata->fail |= FAIL_I2C;
 		return;
 	}
 
-	rv = i2c_read16(TMP006_PORT(addr_flags),
-			TMP006_REG(addr_flags),
+	rv = i2c_read16(TMP006_PORT(addr_flags), TMP006_REG(addr_flags),
 			TMP006_REG_VOBJ, &v);
 	if (rv) {
 		tdata->fail |= FAIL_I2C;
@@ -179,8 +176,7 @@ static int tmp006_read_die_temp_k(const struct tmp006_data_t *tdata,
  * This uses Tdie and Vobj and a bunch of magic parameters to calculate the
  * object temperature, Tobj.
  */
-static int tmp006_read_object_temp_k(struct tmp006_data_t *tdata,
-				     int *temp_ptr)
+static int tmp006_read_object_temp_k(struct tmp006_data_t *tdata, int *temp_ptr)
 {
 	float tdie, vobj;
 	float tx, s, vos, vx, fv, tobj, t4;
@@ -251,7 +247,7 @@ int tmp006_get_val(int idx, int *temp_ptr)
 		 * an I2C error.
 		 */
 		return (tdata->fail & FAIL_I2C) ? EC_ERROR_UNKNOWN :
-			EC_ERROR_NOT_POWERED;
+						  EC_ERROR_NOT_POWERED;
 	}
 
 	/* Check the low bit to determine which temperature to read. */
@@ -277,26 +273,24 @@ static enum ec_status tmp006_get_calibration(struct host_cmd_handler_args *args)
 
 	r1->algorithm = ALGORITHM_NUM;
 	r1->num_params = ALGORITHM_PARAMS;
-	r1->val[0]  = tdata->s0;
-	r1->val[1]  = tdata->a1;
-	r1->val[2]  = tdata->a2;
-	r1->val[3]  = tdata->b0;
-	r1->val[4]  = tdata->b1;
-	r1->val[5]  = tdata->b2;
-	r1->val[6]  = tdata->c2;
-	r1->val[7]  = tdata->d0;
-	r1->val[8]  = tdata->d1;
-	r1->val[9]  = tdata->ds;
+	r1->val[0] = tdata->s0;
+	r1->val[1] = tdata->a1;
+	r1->val[2] = tdata->a2;
+	r1->val[3] = tdata->b0;
+	r1->val[4] = tdata->b1;
+	r1->val[5] = tdata->b2;
+	r1->val[6] = tdata->c2;
+	r1->val[7] = tdata->d0;
+	r1->val[8] = tdata->d1;
+	r1->val[9] = tdata->ds;
 	r1->val[10] = tdata->e0;
 	r1->val[11] = tdata->e1;
 
-	args->response_size = sizeof(*r1) +
-		r1->num_params * sizeof(r1->val[0]);
+	args->response_size = sizeof(*r1) + r1->num_params * sizeof(r1->val[0]);
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_TMP006_GET_CALIBRATION,
-		     tmp006_get_calibration,
+DECLARE_HOST_COMMAND(EC_CMD_TMP006_GET_CALIBRATION, tmp006_get_calibration,
 		     EC_VER_MASK(1));
 
 static enum ec_status tmp006_set_calibration(struct host_cmd_handler_args *args)
@@ -329,8 +323,7 @@ static enum ec_status tmp006_set_calibration(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_TMP006_SET_CALIBRATION,
-		     tmp006_set_calibration,
+DECLARE_HOST_COMMAND(EC_CMD_TMP006_SET_CALIBRATION, tmp006_set_calibration,
 		     EC_VER_MASK(1));
 
 static enum ec_status tmp006_get_raw(struct host_cmd_handler_args *args)
@@ -356,9 +349,7 @@ static enum ec_status tmp006_get_raw(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_TMP006_GET_RAW,
-		     tmp006_get_raw,
-		     EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_TMP006_GET_RAW, tmp006_get_raw, EC_VER_MASK(0));
 
 /*****************************************************************************/
 /* Console commands */
@@ -375,7 +366,6 @@ static int tmp006_print(int idx)
 	int d;
 	int addr_flags = tmp006_sensors[idx].addr_flags;
 
-
 	ccprintf("Debug data from %s:\n", tmp006_sensors[idx].name);
 
 	if (!tmp006_has_power(idx)) {
@@ -383,41 +373,36 @@ static int tmp006_print(int idx)
 		return EC_ERROR_UNKNOWN;
 	}
 
-	rv = i2c_read16(TMP006_PORT(addr_flags),
-			TMP006_REG(addr_flags),
+	rv = i2c_read16(TMP006_PORT(addr_flags), TMP006_REG(addr_flags),
 			TMP006_REG_MANUFACTURER_ID, &d);
 	if (rv)
 		return rv;
 	ccprintf("  Manufacturer ID: 0x%04x\n", d);
 
-	rv = i2c_read16(TMP006_PORT(addr_flags),
-			TMP006_REG(addr_flags),
+	rv = i2c_read16(TMP006_PORT(addr_flags), TMP006_REG(addr_flags),
 			TMP006_REG_DEVICE_ID, &d);
 	ccprintf("  Device ID:       0x%04x\n", d);
 
-	rv = i2c_read16(TMP006_PORT(addr_flags),
-			TMP006_REG(addr_flags),
+	rv = i2c_read16(TMP006_PORT(addr_flags), TMP006_REG(addr_flags),
 			TMP006_REG_CONFIG, &d);
 	ccprintf("  Config:          0x%04x\n", d);
 
-	rv = i2c_read16(TMP006_PORT(addr_flags),
-			TMP006_REG(addr_flags),
+	rv = i2c_read16(TMP006_PORT(addr_flags), TMP006_REG(addr_flags),
 			TMP006_REG_VOBJ, &vraw);
 
 	v = ((int)vraw * 15625) / 100;
 	ccprintf("  Voltage:         0x%04x = %d nV\n", vraw, v);
 
-	rv = i2c_read16(TMP006_PORT(addr_flags),
-			TMP006_REG(addr_flags),
+	rv = i2c_read16(TMP006_PORT(addr_flags), TMP006_REG(addr_flags),
 			TMP006_REG_TDIE, &traw);
 	t = (int)traw;
-	ccprintf("  Temperature:     0x%04x = %d.%02d C\n",
-		 traw, t / 128, t > 0 ? t % 128 : 128 - (t % 128));
+	ccprintf("  Temperature:     0x%04x = %d.%02d C\n", traw, t / 128,
+		 t > 0 ? t % 128 : 128 - (t % 128));
 
 	return EC_SUCCESS;
 }
 
-static int command_sensor_info(int argc, char **argv)
+static int command_sensor_info(int argc, const char **argv)
 {
 	int i;
 	int rv, rv1;
@@ -442,14 +427,13 @@ static int command_sensor_info(int argc, char **argv)
 
 	return rv1;
 }
-DECLARE_CONSOLE_COMMAND(tmp006, command_sensor_info,
-			"[ <index> ]",
+DECLARE_CONSOLE_COMMAND(tmp006, command_sensor_info, "[ <index> ]",
 			"Print TMP006 sensors");
 #endif
 
 /* Disable the t6cal command until/unless we have FP support in printf */
 #if 0
-static int command_t6cal(int argc, char **argv)
+static int command_t6cal(int argc, const char **argv)
 {
 	struct tmp006_data_t *tdata;
 	char *e;
diff --git a/driver/temp_sensor/tmp006.h b/driver/temp_sensor/tmp006.h
index 594dbc711a..c3409dde59 100644
--- a/driver/temp_sensor/tmp006.h
+++ b/driver/temp_sensor/tmp006.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,11 +9,11 @@
 #define __CROS_EC_TMP006_H
 
 /* Registers within the TMP006 chip */
-#define TMP006_REG_VOBJ            0x00
-#define TMP006_REG_TDIE            0x01
-#define TMP006_REG_CONFIG          0x02
+#define TMP006_REG_VOBJ 0x00
+#define TMP006_REG_TDIE 0x01
+#define TMP006_REG_CONFIG 0x02
 #define TMP006_REG_MANUFACTURER_ID 0xfe
-#define TMP006_REG_DEVICE_ID       0xff
+#define TMP006_REG_DEVICE_ID 0xff
 
 /* I2C address components */
 #define TMP006_ADDR(PORT, REG) ((PORT << 16) + REG)
@@ -22,7 +22,7 @@
 
 struct tmp006_t {
 	const char *name;
-	int addr_flags;	/* I2C address formed by TMP006_ADDR macro. */
+	int addr_flags; /* I2C address formed by TMP006_ADDR macro. */
 };
 
 /* Names and addresses of the sensors we have */
@@ -40,4 +40,4 @@ extern const struct tmp006_t tmp006_sensors[];
  */
 int tmp006_get_val(int idx, int *temp_ptr);
 
-#endif  /* __CROS_EC_TMP006_H */
+#endif /* __CROS_EC_TMP006_H */
diff --git a/driver/temp_sensor/tmp112.c b/driver/temp_sensor/tmp112.c
index 6e726a27b9..f7f28159aa 100644
--- a/driver/temp_sensor/tmp112.c
+++ b/driver/temp_sensor/tmp112.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,7 +21,7 @@
 #define TMP112_SHIFT1 (16 - TMP112_RESOLUTION)
 #define TMP112_SHIFT2 (TMP112_RESOLUTION - 8)
 
-#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args)
 
 static int temp_mk_local[TMP112_COUNT];
 
@@ -35,8 +35,8 @@ static int raw_read16(int sensor, const int offset, int *data_ptr)
 		return EC_ERROR_NOT_POWERED;
 #endif
 	return i2c_read16(tmp112_sensors[sensor].i2c_port,
-			  tmp112_sensors[sensor].i2c_addr_flags,
-			  offset, data_ptr);
+			  tmp112_sensors[sensor].i2c_addr_flags, offset,
+			  data_ptr);
 }
 
 static int raw_write16(int sensor, const int offset, int data)
@@ -49,8 +49,7 @@ static int raw_write16(int sensor, const int offset, int data)
 		return EC_ERROR_NOT_POWERED;
 #endif
 	return i2c_write16(tmp112_sensors[sensor].i2c_port,
-			   tmp112_sensors[sensor].i2c_addr_flags,
-			   offset, data);
+			   tmp112_sensors[sensor].i2c_addr_flags, offset, data);
 }
 
 static int get_reg_temp(int sensor, int *temp_ptr)
diff --git a/driver/temp_sensor/tmp411.c b/driver/temp_sensor/tmp411.c
index 8db3f9a8d8..8a14440671 100644
--- a/driver/temp_sensor/tmp411.c
+++ b/driver/temp_sensor/tmp411.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -139,7 +139,7 @@ int tmp411_set_therm_limit(int channel, int limit_c, int hysteresis)
 		return EC_ERROR_INVAL;
 
 	if (hysteresis > TMP411_HYSTERESIS_HIGH_LIMIT ||
-		hysteresis < TMP411_HYSTERESIS_LOW_LIMIT)
+	    hysteresis < TMP411_HYSTERESIS_LOW_LIMIT)
 		return EC_ERROR_INVAL;
 
 	/* hysteresis must be less than high limit */
@@ -181,17 +181,14 @@ static void tmp411_temp_sensor_poll(void)
 
 	if (get_temp(TMP411_REMOTE1, &temp_c) == EC_SUCCESS)
 		temp_val_remote1 = C_TO_K(temp_c);
-
 }
 DECLARE_HOOK(HOOK_SECOND, tmp411_temp_sensor_poll, HOOK_PRIO_TEMP_SENSOR);
 
 #ifdef CONFIG_CMD_TEMP_SENSOR
-static void print_temps(
-		const char *name,
-		const int tmp411_temp_reg,
-		const int tmp411_therm_limit_reg,
-		const int tmp411_high_limit_reg,
-		const int tmp411_low_limit_reg)
+static void print_temps(const char *name, const int tmp411_temp_reg,
+			const int tmp411_therm_limit_reg,
+			const int tmp411_high_limit_reg,
+			const int tmp411_low_limit_reg)
 {
 	int value;
 
@@ -219,28 +216,24 @@ static int print_status(void)
 {
 	int value;
 
-	print_temps("Local", TMP411_LOCAL,
-		    TMP411_LOCAL_THERM_LIMIT,
-		    TMP411_LOCAL_HIGH_LIMIT_R,
-		    TMP411_LOCAL_LOW_LIMIT_R);
+	print_temps("Local", TMP411_LOCAL, TMP411_LOCAL_THERM_LIMIT,
+		    TMP411_LOCAL_HIGH_LIMIT_R, TMP411_LOCAL_LOW_LIMIT_R);
 
-	print_temps("Remote1", TMP411_REMOTE1,
-		    TMP411_REMOTE1_THERM_LIMIT,
-		    TMP411_REMOTE1_HIGH_LIMIT_R,
-		    TMP411_REMOTE1_LOW_LIMIT_R);
+	print_temps("Remote1", TMP411_REMOTE1, TMP411_REMOTE1_THERM_LIMIT,
+		    TMP411_REMOTE1_HIGH_LIMIT_R, TMP411_REMOTE1_LOW_LIMIT_R);
 
 	ccprintf("\n");
 
 	if (raw_read8(TMP411_STATUS_R, &value) == EC_SUCCESS)
-		ccprintf("STATUS:  %pb\n", BINARY_VALUE(value, 8));
+		ccprintf("STATUS:  0x%x\n", value);
 
 	if (raw_read8(TMP411_CONFIGURATION1_R, &value) == EC_SUCCESS)
-		ccprintf("CONFIG1: %pb\n", BINARY_VALUE(value, 8));
+		ccprintf("CONFIG1: 0x%x\n", value);
 
 	return EC_SUCCESS;
 }
 
-static int command_tmp411(int argc, char **argv)
+static int command_tmp411(int argc, const char **argv)
 {
 	char *command;
 	char *e;
@@ -285,8 +278,7 @@ static int command_tmp411(int argc, char **argv)
 		rv = raw_read8(offset, &data);
 		if (rv < 0)
 			return rv;
-		ccprintf("Byte at offset 0x%02x is %pb\n",
-			 offset, BINARY_VALUE(data, 8));
+		ccprintf("Byte at offset 0x%02x is 0x%x\n", offset, data);
 		return rv;
 	}
 
@@ -309,7 +301,8 @@ static int command_tmp411(int argc, char **argv)
 
 	return rv;
 }
-DECLARE_CONSOLE_COMMAND(tmp411, command_tmp411,
+DECLARE_CONSOLE_COMMAND(
+	tmp411, command_tmp411,
 	"[settemp|setbyte <offset> <value>] or [getbyte <offset>] or"
 	"[power <on|off>]. "
 	"Temps in Celsius.",
diff --git a/driver/temp_sensor/tmp411.h b/driver/temp_sensor/tmp411.h
index ef1b23278c..0716a2846d 100644
--- a/driver/temp_sensor/tmp411.h
+++ b/driver/temp_sensor/tmp411.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,83 +8,83 @@
 #ifndef __CROS_EC_TMP411_H
 #define __CROS_EC_TMP411_H
 
-#define TMP411_I2C_ADDR_FLAGS		0x4C
+#define TMP411_I2C_ADDR_FLAGS 0x4C
 
-#define TMP411_IDX_LOCAL	0
-#define TMP411_IDX_REMOTE1	1
-#define TMP411_IDX_REMOTE2	2
+#define TMP411_IDX_LOCAL 0
+#define TMP411_IDX_REMOTE1 1
+#define TMP411_IDX_REMOTE2 2
 
 /* Chip-specific registers */
-#define TMP411_LOCAL			0x00
-#define TMP411_REMOTE1			0x01
-#define TMP411_STATUS_R			0x02
-#define TMP411_CONFIGURATION1_R		0x03
-#define TMP411_CONVERSION_RATE_R	0x04
-#define TMP411_LOCAL_HIGH_LIMIT_R	0x05
-#define TMP411_LOCAL_LOW_LIMIT_R	0x06
-#define TMP411_REMOTE1_HIGH_LIMIT_R	0x07
-#define TMP411_REMOTE1_LOW_LIMIT_R	0x08
-#define TMP411_CONFIGURATION1_W		0x09
-#define TMP411_CONVERSION_RATE_W	0x0a
-#define TMP411_LOCAL_HIGH_LIMIT_W	0x0b
-#define TMP411_LOCAL_LOW_LIMIT_W	0x0c
-#define TMP411_REMOTE1_HIGH_LIMIT_W	0x0d
-#define TMP411_REMOTE1_LOW_LIMIT_W	0x0e
-#define TMP411_ONESHOT			0x0f
-#define TMP411_REMOTE1_EXTD		0x10
-#define TMP411_REMOTE1_HIGH_LIMIT_EXTD	0x13
-#define TMP411_REMOTE1_LOW_LIMIT_EXTD	0x14
-#define TMP411_REMOTE2_HIGH_LIMIT_R	0x15
-#define TMP411_REMOTE2_HIGH_LIMIT_W	0x15
-#define TMP411_REMOTE2_LOW_LIMIT_R	0x16
-#define TMP411_REMOTE2_LOW_LIMIT_W	0x16
-#define TMP411_REMOTE2_HIGH_LIMIT_EXTD	0x17
-#define TMP411_REMOTE2_LOW_LIMIT_EXTD	0x18
-#define TMP411_REMOTE1_THERM_LIMIT	0x19
-#define TMP411_REMOTE2_THERM_LIMIT	0x1a
-#define TMP411_STATUS_FAULT		0x1b
-#define TMP411_CHANNEL_MASK		0x1f
-#define TMP411_LOCAL_THERM_LIMIT	0x20
-#define TMP411_THERM_HYSTERESIS		0x21
-#define TMP411_CONSECUTIVE_ALERT	0x22
-#define TMP411_REMOTE2			0x23
-#define TMP411_REMOTE2_EXTD		0x24
-#define TMP411_BETA_RANGE_CH1		0x25
-#define TMP411_BETA_RANGE_CH2		0x26
-#define TMP411_NFACTOR_REMOTE1		0x27
-#define TMP411_NFACTOR_REMOTE2		0x28
-#define TMP411_LOCAL_EXTD		0x29
-#define TMP411_STATUS_LIMIT_HIGH	0x35
-#define TMP411_STATUS_LIMIT_LOW		0x36
-#define TMP411_STATUS_THERM		0x37
-#define TMP411_RESET_W			0xfc
-#define TMP411_MANUFACTURER_ID		0xfe
-#define TMP411_DEVICE_ID		0xff
+#define TMP411_LOCAL 0x00
+#define TMP411_REMOTE1 0x01
+#define TMP411_STATUS_R 0x02
+#define TMP411_CONFIGURATION1_R 0x03
+#define TMP411_CONVERSION_RATE_R 0x04
+#define TMP411_LOCAL_HIGH_LIMIT_R 0x05
+#define TMP411_LOCAL_LOW_LIMIT_R 0x06
+#define TMP411_REMOTE1_HIGH_LIMIT_R 0x07
+#define TMP411_REMOTE1_LOW_LIMIT_R 0x08
+#define TMP411_CONFIGURATION1_W 0x09
+#define TMP411_CONVERSION_RATE_W 0x0a
+#define TMP411_LOCAL_HIGH_LIMIT_W 0x0b
+#define TMP411_LOCAL_LOW_LIMIT_W 0x0c
+#define TMP411_REMOTE1_HIGH_LIMIT_W 0x0d
+#define TMP411_REMOTE1_LOW_LIMIT_W 0x0e
+#define TMP411_ONESHOT 0x0f
+#define TMP411_REMOTE1_EXTD 0x10
+#define TMP411_REMOTE1_HIGH_LIMIT_EXTD 0x13
+#define TMP411_REMOTE1_LOW_LIMIT_EXTD 0x14
+#define TMP411_REMOTE2_HIGH_LIMIT_R 0x15
+#define TMP411_REMOTE2_HIGH_LIMIT_W 0x15
+#define TMP411_REMOTE2_LOW_LIMIT_R 0x16
+#define TMP411_REMOTE2_LOW_LIMIT_W 0x16
+#define TMP411_REMOTE2_HIGH_LIMIT_EXTD 0x17
+#define TMP411_REMOTE2_LOW_LIMIT_EXTD 0x18
+#define TMP411_REMOTE1_THERM_LIMIT 0x19
+#define TMP411_REMOTE2_THERM_LIMIT 0x1a
+#define TMP411_STATUS_FAULT 0x1b
+#define TMP411_CHANNEL_MASK 0x1f
+#define TMP411_LOCAL_THERM_LIMIT 0x20
+#define TMP411_THERM_HYSTERESIS 0x21
+#define TMP411_CONSECUTIVE_ALERT 0x22
+#define TMP411_REMOTE2 0x23
+#define TMP411_REMOTE2_EXTD 0x24
+#define TMP411_BETA_RANGE_CH1 0x25
+#define TMP411_BETA_RANGE_CH2 0x26
+#define TMP411_NFACTOR_REMOTE1 0x27
+#define TMP411_NFACTOR_REMOTE2 0x28
+#define TMP411_LOCAL_EXTD 0x29
+#define TMP411_STATUS_LIMIT_HIGH 0x35
+#define TMP411_STATUS_LIMIT_LOW 0x36
+#define TMP411_STATUS_THERM 0x37
+#define TMP411_RESET_W 0xfc
+#define TMP411_MANUFACTURER_ID 0xfe
+#define TMP411_DEVICE_ID 0xff
 
-#define TMP411A_DEVICE_ID_VAL		0x12
-#define TMP411B_DEVICE_ID_VAL		0x13
-#define TMP411C_DEVICE_ID_VAL		0x10
-#define TMP411d_DEVICE_ID_VAL		0x12
+#define TMP411A_DEVICE_ID_VAL 0x12
+#define TMP411B_DEVICE_ID_VAL 0x13
+#define TMP411C_DEVICE_ID_VAL 0x10
+#define TMP411d_DEVICE_ID_VAL 0x12
 
 /* Config register bits */
-#define TMP411_CONFIG1_TEMP_RANGE	BIT(2)
+#define TMP411_CONFIG1_TEMP_RANGE BIT(2)
 /* TMP411_CONFIG1_MODE bit is use to enable THERM mode */
-#define TMP411_CONFIG1_MODE		BIT(5)
-#define TMP411_CONFIG1_RUN_L		BIT(6)
-#define TMP411_CONFIG1_ALERT_MASK_L	BIT(7)
+#define TMP411_CONFIG1_MODE BIT(5)
+#define TMP411_CONFIG1_RUN_L BIT(6)
+#define TMP411_CONFIG1_ALERT_MASK_L BIT(7)
 
 /* Status register bits */
-#define TMP411_STATUS_TEMP_THERM_ALARM	BIT(1)
-#define TMP411_STATUS_OPEN		BIT(2)
-#define TMP411_STATUS_TEMP_LOW_ALARM	BIT(3)
-#define TMP411_STATUS_TEMP_HIGH_ALARM	BIT(4)
-#define TMP411_STATUS_LOCAL_TEMP_LOW_ALARM	BIT(5)
-#define TMP411_STATUS_LOCAL_TEMP_HIGH_ALARM	BIT(6)
-#define TMP411_STATUS_BUSY		BIT(7)
+#define TMP411_STATUS_TEMP_THERM_ALARM BIT(1)
+#define TMP411_STATUS_OPEN BIT(2)
+#define TMP411_STATUS_TEMP_LOW_ALARM BIT(3)
+#define TMP411_STATUS_TEMP_HIGH_ALARM BIT(4)
+#define TMP411_STATUS_LOCAL_TEMP_LOW_ALARM BIT(5)
+#define TMP411_STATUS_LOCAL_TEMP_HIGH_ALARM BIT(6)
+#define TMP411_STATUS_BUSY BIT(7)
 
 /* Limits */
-#define TMP411_HYSTERESIS_HIGH_LIMIT	255
-#define TMP411_HYSTERESIS_LOW_LIMIT	0
+#define TMP411_HYSTERESIS_HIGH_LIMIT 255
+#define TMP411_HYSTERESIS_LOW_LIMIT 0
 
 enum tmp411_power_state {
 	TMP411_POWER_OFF = 0,
diff --git a/driver/temp_sensor/tmp432.c b/driver/temp_sensor/tmp432.c
index 8db6a99e19..fde6536536 100644
--- a/driver/temp_sensor/tmp432.c
+++ b/driver/temp_sensor/tmp432.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,7 +19,7 @@ static int temp_val_remote2;
 #ifndef CONFIG_TEMP_SENSOR_POWER
 static uint8_t is_sensor_shutdown;
 #endif
-static int fake_temp[TMP432_IDX_COUNT] = {-1, -1, -1};
+static int fake_temp[TMP432_IDX_COUNT] = { -1, -1, -1 };
 
 /**
  * Determine whether the sensor is powered.
@@ -37,14 +37,14 @@ static int has_power(void)
 
 static int raw_read8(const int offset, int *data_ptr)
 {
-	return i2c_read8(I2C_PORT_THERMAL, TMP432_I2C_ADDR_FLAGS,
-			 offset, data_ptr);
+	return i2c_read8(I2C_PORT_THERMAL, TMP432_I2C_ADDR_FLAGS, offset,
+			 data_ptr);
 }
 
 static int raw_write8(const int offset, int data)
 {
-	return i2c_write8(I2C_PORT_THERMAL, TMP432_I2C_ADDR_FLAGS,
-			  offset, data);
+	return i2c_write8(I2C_PORT_THERMAL, TMP432_I2C_ADDR_FLAGS, offset,
+			  data);
 }
 
 static int get_temp(const int offset, int *temp_ptr)
@@ -150,7 +150,7 @@ int tmp432_set_therm_limit(int channel, int limit_c, int hysteresis)
 		return EC_ERROR_INVAL;
 
 	if (hysteresis > TMP432_HYSTERESIS_HIGH_LIMIT ||
-		hysteresis < TMP432_HYSTERESIS_LOW_LIMIT)
+	    hysteresis < TMP432_HYSTERESIS_LOW_LIMIT)
 		return EC_ERROR_INVAL;
 
 	/* hysteresis must be less than high limit */
@@ -228,12 +228,10 @@ static int tmp432_set_fake_temp(int index, int degree_c)
 	return EC_SUCCESS;
 }
 
-static void print_temps(
-		const char *name,
-		const int tmp432_temp_reg,
-		const int tmp432_therm_limit_reg,
-		const int tmp432_high_limit_reg,
-		const int tmp432_low_limit_reg)
+static void print_temps(const char *name, const int tmp432_temp_reg,
+			const int tmp432_therm_limit_reg,
+			const int tmp432_high_limit_reg,
+			const int tmp432_low_limit_reg)
 {
 	int value;
 
@@ -261,20 +259,14 @@ static int print_status(void)
 {
 	int value, i;
 
-	print_temps("Local", TMP432_LOCAL,
-		    TMP432_LOCAL_THERM_LIMIT,
-		    TMP432_LOCAL_HIGH_LIMIT_R,
-		    TMP432_LOCAL_LOW_LIMIT_R);
+	print_temps("Local", TMP432_LOCAL, TMP432_LOCAL_THERM_LIMIT,
+		    TMP432_LOCAL_HIGH_LIMIT_R, TMP432_LOCAL_LOW_LIMIT_R);
 
-	print_temps("Remote1", TMP432_REMOTE1,
-		    TMP432_REMOTE1_THERM_LIMIT,
-		    TMP432_REMOTE1_HIGH_LIMIT_R,
-		    TMP432_REMOTE1_LOW_LIMIT_R);
+	print_temps("Remote1", TMP432_REMOTE1, TMP432_REMOTE1_THERM_LIMIT,
+		    TMP432_REMOTE1_HIGH_LIMIT_R, TMP432_REMOTE1_LOW_LIMIT_R);
 
-	print_temps("Remote2", TMP432_REMOTE2,
-		    TMP432_REMOTE2_THERM_LIMIT,
-		    TMP432_REMOTE2_HIGH_LIMIT_R,
-		    TMP432_REMOTE2_LOW_LIMIT_R);
+	print_temps("Remote2", TMP432_REMOTE2, TMP432_REMOTE2_THERM_LIMIT,
+		    TMP432_REMOTE2_HIGH_LIMIT_R, TMP432_REMOTE2_LOW_LIMIT_R);
 
 	ccprintf("\n");
 
@@ -294,22 +286,22 @@ static int print_status(void)
 	ccprintf("\n");
 
 	if (raw_read8(TMP432_STATUS, &value) == EC_SUCCESS)
-		ccprintf("STATUS:  %pb\n", BINARY_VALUE(value, 8));
+		ccprintf("STATUS:  0x%x\n", value);
 
 	if (raw_read8(TMP432_CONFIGURATION1_R, &value) == EC_SUCCESS)
-		ccprintf("CONFIG1: %pb\n", BINARY_VALUE(value, 8));
+		ccprintf("CONFIG1: 0x%x\n", value);
 
 	if (raw_read8(TMP432_CONFIGURATION2_R, &value) == EC_SUCCESS)
-		ccprintf("CONFIG2: %pb\n", BINARY_VALUE(value, 8));
+		ccprintf("CONFIG2: 0x%x\n", value);
 
 	return EC_SUCCESS;
 }
 
-static int command_tmp432(int argc, char **argv)
+static int command_tmp432(int argc, const char **argv)
 {
-	char *command;
+	const char *command;
 	char *e;
-	char *power;
+	const char *power;
 	int data;
 	int offset;
 	int rv;
@@ -321,8 +313,7 @@ static int command_tmp432(int argc, char **argv)
 			rv = tmp432_set_power(TMP432_POWER_ON);
 			if (!rv)
 				print_status();
-		}
-		else if (!strncasecmp(power, "off", sizeof("off")))
+		} else if (!strncasecmp(power, "off", sizeof("off")))
 			rv = tmp432_set_power(TMP432_POWER_OFF);
 		else
 			return EC_ERROR_PARAM2;
@@ -351,8 +342,7 @@ static int command_tmp432(int argc, char **argv)
 		rv = raw_read8(offset, &data);
 		if (rv < 0)
 			return rv;
-		ccprintf("Byte at offset 0x%02x is %pb\n",
-			 offset, BINARY_VALUE(data, 8));
+		ccprintf("Byte at offset 0x%02x is 0x%x\n", offset, data);
 		return rv;
 	}
 
@@ -379,7 +369,8 @@ static int command_tmp432(int argc, char **argv)
 
 	return rv;
 }
-DECLARE_CONSOLE_COMMAND(tmp432, command_tmp432,
+DECLARE_CONSOLE_COMMAND(
+	tmp432, command_tmp432,
 	"[settemp|setbyte <offset> <value>] or [getbyte <offset>] or"
 	"[fake <index> <value>] or [power <on|off>]. "
 	"Temps in Celsius.",
diff --git a/driver/temp_sensor/tmp432.h b/driver/temp_sensor/tmp432.h
index e58e39a4a0..d4c99f1129 100644
--- a/driver/temp_sensor/tmp432.h
+++ b/driver/temp_sensor/tmp432.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,85 +8,85 @@
 #ifndef __CROS_EC_TMP432_H
 #define __CROS_EC_TMP432_H
 
-#define TMP432_I2C_ADDR_FLAGS		0x4C
+#define TMP432_I2C_ADDR_FLAGS 0x4C
 
-#define TMP432_IDX_LOCAL	0
-#define TMP432_IDX_REMOTE1	1
-#define TMP432_IDX_REMOTE2	2
-#define TMP432_IDX_COUNT	3
+#define TMP432_IDX_LOCAL 0
+#define TMP432_IDX_REMOTE1 1
+#define TMP432_IDX_REMOTE2 2
+#define TMP432_IDX_COUNT 3
 
 /* Chip-specific registers */
-#define TMP432_LOCAL			0x00
-#define TMP432_REMOTE1			0x01
-#define TMP432_STATUS			0x02
-#define TMP432_CONFIGURATION1_R		0x03
-#define TMP432_CONVERSION_RATE_R	0x04
-#define TMP432_LOCAL_HIGH_LIMIT_R	0x05
-#define TMP432_LOCAL_LOW_LIMIT_R	0x06
-#define TMP432_REMOTE1_HIGH_LIMIT_R	0x07
-#define TMP432_REMOTE1_LOW_LIMIT_R	0x08
-#define TMP432_CONFIGURATION1_W		0x09
-#define TMP432_CONVERSION_RATE_W	0x0a
-#define TMP432_LOCAL_HIGH_LIMIT_W	0x0b
-#define TMP432_LOCAL_LOW_LIMIT_W	0x0c
-#define TMP432_REMOTE1_HIGH_LIMIT_W	0x0d
-#define TMP432_REMOTE1_LOW_LIMIT_W	0x0e
-#define TMP432_ONESHOT			0x0f
-#define TMP432_REMOTE1_EXTD		0x10
-#define TMP432_REMOTE1_HIGH_LIMIT_EXTD	0x13
-#define TMP432_REMOTE1_LOW_LIMIT_EXTD	0x14
-#define TMP432_REMOTE2_HIGH_LIMIT_R	0x15
-#define TMP432_REMOTE2_HIGH_LIMIT_W	0x15
-#define TMP432_REMOTE2_LOW_LIMIT_R	0x16
-#define TMP432_REMOTE2_LOW_LIMIT_W	0x16
-#define TMP432_REMOTE2_HIGH_LIMIT_EXTD	0x17
-#define TMP432_REMOTE2_LOW_LIMIT_EXTD	0x18
-#define TMP432_REMOTE1_THERM_LIMIT	0x19
-#define TMP432_REMOTE2_THERM_LIMIT	0x1a
-#define TMP432_STATUS_FAULT		0x1b
-#define TMP432_CHANNEL_MASK		0x1f
-#define TMP432_LOCAL_THERM_LIMIT	0x20
-#define TMP432_THERM_HYSTERESIS		0x21
-#define TMP432_CONSECUTIVE_ALERT	0x22
-#define TMP432_REMOTE2			0x23
-#define TMP432_REMOTE2_EXTD		0x24
-#define TMP432_BETA_RANGE_CH1		0x25
-#define TMP432_BETA_RANGE_CH2		0x26
-#define TMP432_NFACTOR_REMOTE1		0x27
-#define TMP432_NFACTOR_REMOTE2		0x28
-#define TMP432_LOCAL_EXTD		0x29
-#define TMP432_STATUS_LIMIT_HIGH	0x35
-#define TMP432_STATUS_LIMIT_LOW		0x36
-#define TMP432_STATUS_THERM		0x37
-#define TMP432_LOCAL_HIGH_LIMIT_EXTD	0x3d
-#define TMP432_LOCAL_LOW_LIMIT_EXTD	0x3e
-#define TMP432_CONFIGURATION2_R		0x3f
-#define TMP432_CONFIGURATION2_W		0x3f
-#define TMP432_RESET_W			0xfc
-#define TMP432_DEVICE_ID		0xfd
-#define TMP432_MANUFACTURER_ID		0xfe
+#define TMP432_LOCAL 0x00
+#define TMP432_REMOTE1 0x01
+#define TMP432_STATUS 0x02
+#define TMP432_CONFIGURATION1_R 0x03
+#define TMP432_CONVERSION_RATE_R 0x04
+#define TMP432_LOCAL_HIGH_LIMIT_R 0x05
+#define TMP432_LOCAL_LOW_LIMIT_R 0x06
+#define TMP432_REMOTE1_HIGH_LIMIT_R 0x07
+#define TMP432_REMOTE1_LOW_LIMIT_R 0x08
+#define TMP432_CONFIGURATION1_W 0x09
+#define TMP432_CONVERSION_RATE_W 0x0a
+#define TMP432_LOCAL_HIGH_LIMIT_W 0x0b
+#define TMP432_LOCAL_LOW_LIMIT_W 0x0c
+#define TMP432_REMOTE1_HIGH_LIMIT_W 0x0d
+#define TMP432_REMOTE1_LOW_LIMIT_W 0x0e
+#define TMP432_ONESHOT 0x0f
+#define TMP432_REMOTE1_EXTD 0x10
+#define TMP432_REMOTE1_HIGH_LIMIT_EXTD 0x13
+#define TMP432_REMOTE1_LOW_LIMIT_EXTD 0x14
+#define TMP432_REMOTE2_HIGH_LIMIT_R 0x15
+#define TMP432_REMOTE2_HIGH_LIMIT_W 0x15
+#define TMP432_REMOTE2_LOW_LIMIT_R 0x16
+#define TMP432_REMOTE2_LOW_LIMIT_W 0x16
+#define TMP432_REMOTE2_HIGH_LIMIT_EXTD 0x17
+#define TMP432_REMOTE2_LOW_LIMIT_EXTD 0x18
+#define TMP432_REMOTE1_THERM_LIMIT 0x19
+#define TMP432_REMOTE2_THERM_LIMIT 0x1a
+#define TMP432_STATUS_FAULT 0x1b
+#define TMP432_CHANNEL_MASK 0x1f
+#define TMP432_LOCAL_THERM_LIMIT 0x20
+#define TMP432_THERM_HYSTERESIS 0x21
+#define TMP432_CONSECUTIVE_ALERT 0x22
+#define TMP432_REMOTE2 0x23
+#define TMP432_REMOTE2_EXTD 0x24
+#define TMP432_BETA_RANGE_CH1 0x25
+#define TMP432_BETA_RANGE_CH2 0x26
+#define TMP432_NFACTOR_REMOTE1 0x27
+#define TMP432_NFACTOR_REMOTE2 0x28
+#define TMP432_LOCAL_EXTD 0x29
+#define TMP432_STATUS_LIMIT_HIGH 0x35
+#define TMP432_STATUS_LIMIT_LOW 0x36
+#define TMP432_STATUS_THERM 0x37
+#define TMP432_LOCAL_HIGH_LIMIT_EXTD 0x3d
+#define TMP432_LOCAL_LOW_LIMIT_EXTD 0x3e
+#define TMP432_CONFIGURATION2_R 0x3f
+#define TMP432_CONFIGURATION2_W 0x3f
+#define TMP432_RESET_W 0xfc
+#define TMP432_DEVICE_ID 0xfd
+#define TMP432_MANUFACTURER_ID 0xfe
 
 /* Config register bits */
-#define TMP432_CONFIG1_TEMP_RANGE	BIT(2)
+#define TMP432_CONFIG1_TEMP_RANGE BIT(2)
 /* TMP432_CONFIG1_MODE bit is use to enable THERM mode */
-#define TMP432_CONFIG1_MODE		BIT(5)
-#define TMP432_CONFIG1_RUN_L		BIT(6)
-#define TMP432_CONFIG1_ALERT_MASK_L	BIT(7)
-#define TMP432_CONFIG2_RESISTANCE_CORRECTION	BIT(2)
-#define TMP432_CONFIG2_LOCAL_ENABLE	BIT(3)
-#define TMP432_CONFIG2_REMOTE1_ENABLE	BIT(4)
-#define TMP432_CONFIG2_REMOTE2_ENABLE	BIT(5)
+#define TMP432_CONFIG1_MODE BIT(5)
+#define TMP432_CONFIG1_RUN_L BIT(6)
+#define TMP432_CONFIG1_ALERT_MASK_L BIT(7)
+#define TMP432_CONFIG2_RESISTANCE_CORRECTION BIT(2)
+#define TMP432_CONFIG2_LOCAL_ENABLE BIT(3)
+#define TMP432_CONFIG2_REMOTE1_ENABLE BIT(4)
+#define TMP432_CONFIG2_REMOTE2_ENABLE BIT(5)
 
 /* Status register bits */
-#define TMP432_STATUS_TEMP_THERM_ALARM	BIT(1)
-#define TMP432_STATUS_OPEN		BIT(2)
-#define TMP432_STATUS_TEMP_LOW_ALARM	BIT(3)
-#define TMP432_STATUS_TEMP_HIGH_ALARM	BIT(4)
-#define TMP432_STATUS_BUSY		BIT(7)
+#define TMP432_STATUS_TEMP_THERM_ALARM BIT(1)
+#define TMP432_STATUS_OPEN BIT(2)
+#define TMP432_STATUS_TEMP_LOW_ALARM BIT(3)
+#define TMP432_STATUS_TEMP_HIGH_ALARM BIT(4)
+#define TMP432_STATUS_BUSY BIT(7)
 
 /* Limintaions */
-#define TMP432_HYSTERESIS_HIGH_LIMIT	255
-#define TMP432_HYSTERESIS_LOW_LIMIT	0
+#define TMP432_HYSTERESIS_HIGH_LIMIT 255
+#define TMP432_HYSTERESIS_LOW_LIMIT 0
 
 enum tmp432_power_state {
 	TMP432_POWER_OFF = 0,
diff --git a/driver/temp_sensor/tmp468.c b/driver/temp_sensor/tmp468.c
index 46e77ca696..87eb040460 100644
--- a/driver/temp_sensor/tmp468.c
+++ b/driver/temp_sensor/tmp468.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,9 +15,9 @@
 
 #include "tmp468.h"
 
-
-static int fake_temp[TMP468_CHANNEL_COUNT] = {-1, -1, -1, -1, -1, -1, -1 , -1, -1};
-static int temp_val[TMP468_CHANNEL_COUNT]  = {0, 0, 0, 0, 0, 0, 0 , 0, 0};
+static int fake_temp[TMP468_CHANNEL_COUNT] = { -1, -1, -1, -1, -1,
+					       -1, -1, -1, -1 };
+static int temp_val[TMP468_CHANNEL_COUNT] = { 0, 0, 0, 0, 0, 0, 0, 0, 0 };
 static uint8_t is_sensor_shutdown;
 
 static int has_power(void)
@@ -27,14 +27,14 @@ static int has_power(void)
 
 static int raw_read16(const int offset, int *data_ptr)
 {
-	return i2c_read16(I2C_PORT_THERMAL, TMP468_I2C_ADDR_FLAGS,
-			  offset, data_ptr);
+	return i2c_read16(I2C_PORT_THERMAL, TMP468_I2C_ADDR_FLAGS, offset,
+			  data_ptr);
 }
 
 static int raw_write16(const int offset, int data_ptr)
 {
-	return i2c_write16(I2C_PORT_THERMAL, TMP468_I2C_ADDR_FLAGS,
-			   offset, data_ptr);
+	return i2c_write16(I2C_PORT_THERMAL, TMP468_I2C_ADDR_FLAGS, offset,
+			   data_ptr);
 }
 
 static int tmp468_shutdown(uint8_t want_shutdown)
@@ -64,7 +64,7 @@ static int tmp468_shutdown(uint8_t want_shutdown)
 
 int tmp468_get_val(int idx, int *temp_ptr)
 {
-	if(!has_power())
+	if (!has_power())
 		return EC_ERROR_NOT_POWERED;
 
 	if (idx < TMP468_CHANNEL_COUNT) {
diff --git a/driver/temp_sensor/tmp468.h b/driver/temp_sensor/tmp468.h
index 59fbd20477..3a2c154066 100644
--- a/driver/temp_sensor/tmp468.h
+++ b/driver/temp_sensor/tmp468.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,73 +11,73 @@
 #define TMP468_I2C_ADDR_FLAGS (0x48 | I2C_FLAG_BIG_ENDIAN)
 #define TMP468_SHIFT1 7
 
-#define TMP468_LOCAL			0x00
-#define TMP468_REMOTE1			0x01
-#define TMP468_REMOTE2			0x02
-#define TMP468_REMOTE3			0x03
-#define TMP468_REMOTE4			0x04
-#define TMP468_REMOTE5			0x05
-#define TMP468_REMOTE6			0x06
-#define TMP468_REMOTE7			0x07
-#define TMP468_REMOTE8			0x08
-
-#define TMP468_SRST			0x20
-#define TMP468_THERM			0x21
-#define TMP468_THERM2			0x22
-#define TMP468_ROPEN			0x23
-
-#define TMP468_CONFIGURATION		0x30
-#define TMP468_THERM_HYST		0x38
-
-#define TMP468_LOCAL_LOW_LIMIT		0x39
-#define TMP468_LOCAL_HIGH_LIMT		0x3a
-
-#define TMP468_REMOTE1_OFFSET		0x40
-#define TMP468_REMOTE1_NFACTOR		0x41
-#define TMP468_REMOTE1_LOW_LIMIT	0x41
-#define TMP468_REMOTE1_HIGH_LIMIT	0x42
-
-#define TMP468_REMOTE2_OFFSET		0x48
-#define TMP468_REMOTE2_NFACTOR		0x49
-#define TMP468_REMOTE2_LOW_LIMIT	0x4a
-#define TMP468_REMOTE2_HIGH_LIMIT	0x4b
-
-#define TMP468_REMOTE3_OFFSET		0x50
-#define TMP468_REMOTE3_NFACTOR		0x51
-#define TMP468_REMOTE3_LOW_LIMIT	0x52
-#define TMP468_REMOTE3_HIGH_LIMIT	0x53
-
-#define TMP468_REMOTE4_OFFSET		0x58
-#define TMP468_REMOTE4_NFACTOR		0x59
-#define TMP468_REMOTE4_LOW_LIMIT	0x59
-#define TMP468_REMOTE4_HIGH_LIMIT	0x5a
-
-#define TMP468_REMOTE5_OFFSET		0x60
-#define TMP468_REMOTE5_NFACTOR		0x61
-#define TMP468_REMOTE5_LOW_LIMIT	0x62
-#define TMP468_REMOTE5_HIGH_LIMIT	0x63
-
-#define TMP468_REMOTE6_OFFSET		0x68
-#define TMP468_REMOTE6_NFACTOR		0x69
-#define TMP468_REMOTE6_LOW_LIMIT	0x6a
-#define TMP468_REMOTE6_HIGH_LIMIT	0x6b
-
-#define TMP468_REMOTE7_OFFSET		0x70
-#define TMP468_REMOTE7_NFACTOR		0x71
-#define TMP468_REMOTE7_LOW_LIMIT	0x72
-#define TMP468_REMOTE7_HIGH_LIMIT	0x73
-
-#define TMP468_REMOTE8_OFFSET		0x78
-#define TMP468_REMOTE8_NFACTOR		0x79
-#define TMP468_REMOTE8_LOW_LIMIT	0x7a
-#define TMP468_REMOTE8_HIGH_LIMIT	0x7b
-
-#define TMP468_LOCK			0xc4
-
-#define TMP468_DEVICE_ID		0xfd
-#define TMP468_MANUFACTURER_ID		0xfe
-
-#define TMP468_SHUTDOWN			BIT(5)
+#define TMP468_LOCAL 0x00
+#define TMP468_REMOTE1 0x01
+#define TMP468_REMOTE2 0x02
+#define TMP468_REMOTE3 0x03
+#define TMP468_REMOTE4 0x04
+#define TMP468_REMOTE5 0x05
+#define TMP468_REMOTE6 0x06
+#define TMP468_REMOTE7 0x07
+#define TMP468_REMOTE8 0x08
+
+#define TMP468_SRST 0x20
+#define TMP468_THERM 0x21
+#define TMP468_THERM2 0x22
+#define TMP468_ROPEN 0x23
+
+#define TMP468_CONFIGURATION 0x30
+#define TMP468_THERM_HYST 0x38
+
+#define TMP468_LOCAL_LOW_LIMIT 0x39
+#define TMP468_LOCAL_HIGH_LIMT 0x3a
+
+#define TMP468_REMOTE1_OFFSET 0x40
+#define TMP468_REMOTE1_NFACTOR 0x41
+#define TMP468_REMOTE1_LOW_LIMIT 0x41
+#define TMP468_REMOTE1_HIGH_LIMIT 0x42
+
+#define TMP468_REMOTE2_OFFSET 0x48
+#define TMP468_REMOTE2_NFACTOR 0x49
+#define TMP468_REMOTE2_LOW_LIMIT 0x4a
+#define TMP468_REMOTE2_HIGH_LIMIT 0x4b
+
+#define TMP468_REMOTE3_OFFSET 0x50
+#define TMP468_REMOTE3_NFACTOR 0x51
+#define TMP468_REMOTE3_LOW_LIMIT 0x52
+#define TMP468_REMOTE3_HIGH_LIMIT 0x53
+
+#define TMP468_REMOTE4_OFFSET 0x58
+#define TMP468_REMOTE4_NFACTOR 0x59
+#define TMP468_REMOTE4_LOW_LIMIT 0x59
+#define TMP468_REMOTE4_HIGH_LIMIT 0x5a
+
+#define TMP468_REMOTE5_OFFSET 0x60
+#define TMP468_REMOTE5_NFACTOR 0x61
+#define TMP468_REMOTE5_LOW_LIMIT 0x62
+#define TMP468_REMOTE5_HIGH_LIMIT 0x63
+
+#define TMP468_REMOTE6_OFFSET 0x68
+#define TMP468_REMOTE6_NFACTOR 0x69
+#define TMP468_REMOTE6_LOW_LIMIT 0x6a
+#define TMP468_REMOTE6_HIGH_LIMIT 0x6b
+
+#define TMP468_REMOTE7_OFFSET 0x70
+#define TMP468_REMOTE7_NFACTOR 0x71
+#define TMP468_REMOTE7_LOW_LIMIT 0x72
+#define TMP468_REMOTE7_HIGH_LIMIT 0x73
+
+#define TMP468_REMOTE8_OFFSET 0x78
+#define TMP468_REMOTE8_NFACTOR 0x79
+#define TMP468_REMOTE8_LOW_LIMIT 0x7a
+#define TMP468_REMOTE8_HIGH_LIMIT 0x7b
+
+#define TMP468_LOCK 0xc4
+
+#define TMP468_DEVICE_ID 0xfd
+#define TMP468_MANUFACTURER_ID 0xfe
+
+#define TMP468_SHUTDOWN BIT(5)
 
 enum tmp468_channel_id {
 	TMP468_CHANNEL_LOCAL,
@@ -101,7 +101,6 @@ enum tmp468_power_state {
 	TMP468_POWER_COUNT
 };
 
-
 /**
  * Get the last polled value of a sensor.
  *
diff --git a/driver/touchpad_elan.c b/driver/touchpad_elan.c
index 6df4f0f7de..05c081a84a 100644
--- a/driver/touchpad_elan.c
+++ b/driver/touchpad_elan.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,73 +25,73 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_TOUCHPAD, outstr)
-#define CPRINTF(format, args...) cprintf(CC_TOUCHPAD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_TOUCHPAD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_TOUCHPAD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_TOUCHPAD, format, ##args)
 
-#define TASK_EVENT_POWER  TASK_EVENT_CUSTOM_BIT(0)
+#define TASK_EVENT_POWER TASK_EVENT_CUSTOM_BIT(0)
 
 /******************************************************************************/
 /* How to talk to the controller */
 /******************************************************************************/
 
-#define ELAN_VENDOR_ID			0x04f3
+#define ELAN_VENDOR_ID 0x04f3
 
-#define ETP_I2C_RESET			0x0100
-#define ETP_I2C_WAKE_UP			0x0800
-#define ETP_I2C_SLEEP			0x0801
+#define ETP_I2C_RESET 0x0100
+#define ETP_I2C_WAKE_UP 0x0800
+#define ETP_I2C_SLEEP 0x0801
 
-#define ETP_I2C_STAND_CMD		0x0005
-#define ETP_I2C_UNIQUEID_CMD		0x0101
-#define ETP_I2C_FW_VERSION_CMD		0x0102
-#define ETP_I2C_OSM_VERSION_CMD		0x0103
-#define ETP_I2C_XY_TRACENUM_CMD		0x0105
-#define ETP_I2C_MAX_X_AXIS_CMD		0x0106
-#define ETP_I2C_MAX_Y_AXIS_CMD		0x0107
-#define ETP_I2C_RESOLUTION_CMD		0x0108
-#define ETP_I2C_IAP_VERSION_CMD		0x0110
-#define ETP_I2C_PRESSURE_CMD		0x010A
-#define ETP_I2C_SET_CMD			0x0300
-#define ETP_I2C_IAP_TYPE_CMD		0x0304
-#define ETP_I2C_POWER_CMD		0x0307
-#define ETP_I2C_FW_CHECKSUM_CMD		0x030F
+#define ETP_I2C_STAND_CMD 0x0005
+#define ETP_I2C_UNIQUEID_CMD 0x0101
+#define ETP_I2C_FW_VERSION_CMD 0x0102
+#define ETP_I2C_OSM_VERSION_CMD 0x0103
+#define ETP_I2C_XY_TRACENUM_CMD 0x0105
+#define ETP_I2C_MAX_X_AXIS_CMD 0x0106
+#define ETP_I2C_MAX_Y_AXIS_CMD 0x0107
+#define ETP_I2C_RESOLUTION_CMD 0x0108
+#define ETP_I2C_IAP_VERSION_CMD 0x0110
+#define ETP_I2C_PRESSURE_CMD 0x010A
+#define ETP_I2C_SET_CMD 0x0300
+#define ETP_I2C_IAP_TYPE_CMD 0x0304
+#define ETP_I2C_POWER_CMD 0x0307
+#define ETP_I2C_FW_CHECKSUM_CMD 0x030F
 
-#define ETP_ENABLE_ABS		0x0001
+#define ETP_ENABLE_ABS 0x0001
 
-#define ETP_DISABLE_POWER	0x0001
+#define ETP_DISABLE_POWER 0x0001
 
-#define ETP_I2C_REPORT_LEN	34
+#define ETP_I2C_REPORT_LEN 34
 
-#define ETP_MAX_FINGERS		5
-#define ETP_FINGER_DATA_LEN	5
+#define ETP_MAX_FINGERS 5
+#define ETP_FINGER_DATA_LEN 5
 
-#define ETP_PRESSURE_OFFSET	25
-#define ETP_FWIDTH_REDUCE	90
+#define ETP_PRESSURE_OFFSET 25
+#define ETP_FWIDTH_REDUCE 90
 
-#define ETP_REPORT_ID		0x5D
-#define ETP_REPORT_ID_OFFSET	2
-#define ETP_TOUCH_INFO_OFFSET	3
-#define ETP_FINGER_DATA_OFFSET	4
-#define ETP_HOVER_INFO_OFFSET	30
-#define ETP_MAX_REPORT_LEN	34
+#define ETP_REPORT_ID 0x5D
+#define ETP_REPORT_ID_OFFSET 2
+#define ETP_TOUCH_INFO_OFFSET 3
+#define ETP_FINGER_DATA_OFFSET 4
+#define ETP_HOVER_INFO_OFFSET 30
+#define ETP_MAX_REPORT_LEN 34
 
-#define ETP_IAP_START_ADDR		0x0083
+#define ETP_IAP_START_ADDR 0x0083
 
-#define ETP_I2C_IAP_RESET_CMD		0x0314
-#define ETP_I2C_IAP_RESET		0xF0F0
-#define ETP_I2C_IAP_CTRL_CMD		0x0310
-#define ETP_I2C_MAIN_MODE_ON		BIT(9)
-#define ETP_I2C_IAP_CMD			0x0311
-#define ETP_I2C_IAP_PASSWORD		0x1EA5
+#define ETP_I2C_IAP_RESET_CMD 0x0314
+#define ETP_I2C_IAP_RESET 0xF0F0
+#define ETP_I2C_IAP_CTRL_CMD 0x0310
+#define ETP_I2C_MAIN_MODE_ON BIT(9)
+#define ETP_I2C_IAP_CMD 0x0311
+#define ETP_I2C_IAP_PASSWORD 0x1EA5
 
-#define ETP_I2C_IAP_REG_L		0x01
-#define ETP_I2C_IAP_REG_H		0x06
+#define ETP_I2C_IAP_REG_L 0x01
+#define ETP_I2C_IAP_REG_H 0x06
 
-#define ETP_FW_IAP_PAGE_ERR		BIT(5)
-#define ETP_FW_IAP_INTF_ERR		BIT(4)
+#define ETP_FW_IAP_PAGE_ERR BIT(5)
+#define ETP_FW_IAP_INTF_ERR BIT(4)
 
 #ifdef CONFIG_USB_UPDATE
 /* The actual FW_SIZE depends on IC. */
-#define FW_SIZE			CONFIG_TOUCHPAD_VIRTUAL_SIZE
+#define FW_SIZE CONFIG_TOUCHPAD_VIRTUAL_SIZE
 #endif
 
 struct {
@@ -124,8 +124,8 @@ static int elan_tp_read_cmd(uint16_t reg, uint16_t *val)
 	buf[1] = reg >> 8;
 
 	return i2c_xfer(CONFIG_TOUCHPAD_I2C_PORT,
-			CONFIG_TOUCHPAD_I2C_ADDR_FLAGS,
-			buf, sizeof(buf), (uint8_t *)val, sizeof(*val));
+			CONFIG_TOUCHPAD_I2C_ADDR_FLAGS, buf, sizeof(buf),
+			(uint8_t *)val, sizeof(*val));
 }
 
 static int elan_tp_write_cmd(uint16_t reg, uint16_t val)
@@ -138,8 +138,8 @@ static int elan_tp_write_cmd(uint16_t reg, uint16_t val)
 	buf[3] = val >> 8;
 
 	return i2c_xfer(CONFIG_TOUCHPAD_I2C_PORT,
-			CONFIG_TOUCHPAD_I2C_ADDR_FLAGS,
-			buf, sizeof(buf), NULL, 0);
+			CONFIG_TOUCHPAD_I2C_ADDR_FLAGS, buf, sizeof(buf), NULL,
+			0);
 }
 
 /* Power is on by default. */
@@ -171,7 +171,7 @@ out:
 	return rv;
 }
 
-static int finger_status[ETP_MAX_FINGERS] = {0};
+static int finger_status[ETP_MAX_FINGERS] = { 0 };
 
 /*
  * Timestamp of last interrupt (32 bits are enough as we divide the value by 100
@@ -192,15 +192,14 @@ static int elan_tp_read_report(void)
 	int i, ri;
 	uint8_t touch_info;
 	uint8_t hover_info;
-	uint8_t *finger = tp_buf+ETP_FINGER_DATA_OFFSET;
+	uint8_t *finger = tp_buf + ETP_FINGER_DATA_OFFSET;
 	struct usb_hid_touchpad_report report;
 	uint16_t timestamp;
 
 	/* Compute and save timestamp early in case another interrupt comes. */
 	timestamp = irq_ts / USB_HID_TOUCHPAD_TIMESTAMP_UNIT;
 
-	rv = i2c_xfer(CONFIG_TOUCHPAD_I2C_PORT,
-		      CONFIG_TOUCHPAD_I2C_ADDR_FLAGS,
+	rv = i2c_xfer(CONFIG_TOUCHPAD_I2C_PORT, CONFIG_TOUCHPAD_I2C_ADDR_FLAGS,
 		      NULL, 0, tp_buf, ETP_I2C_REPORT_LEN);
 
 	if (rv) {
@@ -221,14 +220,14 @@ static int elan_tp_read_report(void)
 	hover_info = tp_buf[ETP_HOVER_INFO_OFFSET];
 
 	for (i = 0; i < ETP_MAX_FINGERS; i++) {
-		int valid = touch_info & (1 << (3+i));
+		int valid = touch_info & (1 << (3 + i));
 
 		if (valid) {
 			int width = finger[3] & 0x0f;
 			int height = (finger[3] & 0xf0) >> 4;
 			int pressure = finger[4] + elan_tp_params.pressure_adj;
 			pressure = DIV_ROUND_NEAREST(pressure * pressure_mult,
-						pressure_div);
+						     pressure_div);
 
 			width = MIN(4095, width * elan_tp_params.width_x);
 			height = MIN(4095, height * elan_tp_params.width_y);
@@ -240,8 +239,8 @@ static int elan_tp_read_report(void)
 			report.finger[ri].id = i;
 			report.finger[ri].width = width;
 			report.finger[ri].height = height;
-			report.finger[ri].x =
-				((finger[0] & 0xf0) << 4) | finger[1];
+			report.finger[ri].x = ((finger[0] & 0xf0) << 4) |
+					      finger[1];
 			report.finger[ri].y =
 				elan_tp_params.max_y -
 				(((finger[0] & 0x0f) << 8) | finger[2]);
@@ -331,8 +330,7 @@ static void elan_tp_init(void)
 
 	elan_tp_write_cmd(ETP_I2C_STAND_CMD, ETP_I2C_RESET);
 	msleep(100);
-	rv = i2c_xfer(CONFIG_TOUCHPAD_I2C_PORT,
-		      CONFIG_TOUCHPAD_I2C_ADDR_FLAGS,
+	rv = i2c_xfer(CONFIG_TOUCHPAD_I2C_PORT, CONFIG_TOUCHPAD_I2C_ADDR_FLAGS,
 		      NULL, 0, val, sizeof(val));
 
 	CPRINTS("reset rv %d buf=%04x", rv, *((uint16_t *)val));
@@ -347,7 +345,7 @@ static void elan_tp_init(void)
 		goto out;
 
 	rv = elan_tp_read_cmd(ETP_I2C_IAP_VERSION_CMD,
-			&elan_tp_params.iap_version);
+			      &elan_tp_params.iap_version);
 	CPRINTS("%s: iap_version:%04X.", __func__, elan_tp_params.iap_version);
 	elan_tp_params.iap_version >>= 8;
 	if (rv)
@@ -389,22 +387,22 @@ static void elan_tp_init(void)
 	if (rv)
 		goto out;
 
-	dpi_x = 10*val[0] + 790;
-	dpi_y = 10*val[1] + 790;
+	dpi_x = 10 * val[0] + 790;
+	dpi_y = 10 * val[1] + 790;
 
-	CPRINTS("max=%d/%d width=%d/%d adj=%d dpi=%d/%d",
-		elan_tp_params.max_x, elan_tp_params.max_y,
-		elan_tp_params.width_x, elan_tp_params.width_y,
-		elan_tp_params.pressure_adj, dpi_x, dpi_y);
+	CPRINTS("max=%d/%d width=%d/%d adj=%d dpi=%d/%d", elan_tp_params.max_x,
+		elan_tp_params.max_y, elan_tp_params.width_x,
+		elan_tp_params.width_y, elan_tp_params.pressure_adj, dpi_x,
+		dpi_y);
 
 #ifdef CONFIG_USB_HID_TOUCHPAD
 	/* Validity check dimensions provided at build time. */
 	if (elan_tp_params.max_x != CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X ||
 	    elan_tp_params.max_y != CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y ||
 	    calc_physical_dimension(dpi_x, elan_tp_params.max_x) !=
-			CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X ||
+		    CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X ||
 	    calc_physical_dimension(dpi_y, elan_tp_params.max_y) !=
-			CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y) {
+		    CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y) {
 		CPRINTS("*** TP mismatch!");
 	}
 #endif
@@ -469,7 +467,7 @@ static int elan_read_write_iap_type(void)
 		uint16_t val;
 
 		if (elan_tp_write_cmd(ETP_I2C_IAP_TYPE_CMD,
-					elan_tp_params.page_size / 2))
+				      elan_tp_params.page_size / 2))
 			return EC_ERROR_UNKNOWN;
 
 		if (elan_tp_read_cmd(ETP_I2C_IAP_TYPE_CMD, &val))
@@ -477,7 +475,6 @@ static int elan_read_write_iap_type(void)
 
 		if (val == elan_tp_params.page_size / 2)
 			return EC_SUCCESS;
-
 	}
 	return EC_ERROR_UNKNOWN;
 }
@@ -527,7 +524,7 @@ static int elan_prepare_for_update(void)
 
 static int touchpad_update_page(const uint8_t *data)
 {
-	const uint8_t cmd[2] = {ETP_I2C_IAP_REG_L, ETP_I2C_IAP_REG_H};
+	const uint8_t cmd[2] = { ETP_I2C_IAP_REG_L, ETP_I2C_IAP_REG_H };
 	uint16_t checksum = 0;
 	uint16_t rx_buf;
 	int i, rv;
@@ -539,13 +536,13 @@ static int touchpad_update_page(const uint8_t *data)
 	i2c_lock(CONFIG_TOUCHPAD_I2C_PORT, 1);
 
 	rv = i2c_xfer_unlocked(CONFIG_TOUCHPAD_I2C_PORT,
-			       CONFIG_TOUCHPAD_I2C_ADDR_FLAGS,
-			       cmd, sizeof(cmd), NULL, 0, I2C_XFER_START);
+			       CONFIG_TOUCHPAD_I2C_ADDR_FLAGS, cmd, sizeof(cmd),
+			       NULL, 0, I2C_XFER_START);
 	if (rv)
 		goto fail;
 	rv = i2c_xfer_unlocked(CONFIG_TOUCHPAD_I2C_PORT,
-			       CONFIG_TOUCHPAD_I2C_ADDR_FLAGS,
-			       data, elan_tp_params.page_size, NULL, 0, 0);
+			       CONFIG_TOUCHPAD_I2C_ADDR_FLAGS, data,
+			       elan_tp_params.page_size, NULL, 0, 0);
 	if (rv)
 		goto fail;
 	rv = i2c_xfer_unlocked(CONFIG_TOUCHPAD_I2C_PORT,
@@ -564,8 +561,7 @@ fail:
 	rv = elan_tp_read_cmd(ETP_I2C_IAP_CTRL_CMD, &rx_buf);
 
 	if (rv || (rx_buf & (ETP_FW_IAP_PAGE_ERR | ETP_FW_IAP_INTF_ERR))) {
-		CPRINTS("%s: IAP reports failed write : %x.",
-			__func__, rx_buf);
+		CPRINTS("%s: IAP reports failed write : %x.", __func__, rx_buf);
 		return EC_ERROR_UNKNOWN;
 	}
 	return 0;
@@ -580,8 +576,8 @@ int touchpad_update_write(int offset, int size, const uint8_t *data)
 
 	if (offset == 0) {
 		/* Verify the IC type is aligned with defined firmware size */
-		if (elan_tp_params.page_size * elan_tp_params.page_count
-				!= FW_SIZE) {
+		if (elan_tp_params.page_size * elan_tp_params.page_count !=
+		    FW_SIZE) {
 			CPRINTS("%s: IC(%d*%d) size and FW_SIZE(%d) mismatch",
 				__func__, elan_tp_params.page_count,
 				elan_tp_params.page_size, FW_SIZE);
@@ -599,7 +595,8 @@ int touchpad_update_write(int offset, int size, const uint8_t *data)
 	if (offset <= (ETP_IAP_START_ADDR * 2) &&
 	    (ETP_IAP_START_ADDR * 2) < (offset + size)) {
 		iap_addr = ((data[ETP_IAP_START_ADDR * 2 - offset + 1] << 8) |
-			data[ETP_IAP_START_ADDR * 2 - offset]) << 1;
+			    data[ETP_IAP_START_ADDR * 2 - offset])
+			   << 1;
 		CPRINTS("%s: payload starts from 0x%x.", __func__, iap_addr);
 	}
 
@@ -608,7 +605,7 @@ int touchpad_update_write(int offset, int size, const uint8_t *data)
 		return EC_ERROR_INVAL;
 
 	for (addr = offset; addr < (offset + size);
-			addr += elan_tp_params.page_size) {
+	     addr += elan_tp_params.page_size) {
 		if (iap_addr > addr) /* Skip chunk */
 			continue;
 		rv = touchpad_update_page(data + addr - offset);
@@ -632,21 +629,17 @@ int touchpad_update_write(int offset, int size, const uint8_t *data)
 #define TOUCHPAD_ELAN_DEBUG_CMD_LENGTH 50
 #define TOUCHPAD_ELAN_DEBUG_NUM_CMD 2
 
-static const uint8_t
-allowed_command_hashes[TOUCHPAD_ELAN_DEBUG_NUM_CMD][SHA256_DIGEST_SIZE] = {
-	{
-		0x0a, 0xf6, 0x37, 0x03, 0x93, 0xb2, 0xde, 0x8c,
-		0x56, 0x7b, 0x86, 0xba, 0xa6, 0x79, 0xe3, 0xa3,
-		0x8b, 0xc7, 0x15, 0xf2, 0x53, 0xcf, 0x71, 0x8b,
-		0x3d, 0xe4, 0x81, 0xf9, 0xd9, 0xa8, 0x78, 0x48
-	},
-	{
-		0xac, 0xe5, 0xbf, 0x17, 0x1f, 0xde, 0xce, 0x76,
-		0x0c, 0x0e, 0xf8, 0xa2, 0xe9, 0x67, 0x2d, 0xc9,
-		0x1b, 0xd4, 0xba, 0x34, 0x51, 0xca, 0xf6, 0x6d,
-		0x7b, 0xb2, 0x1f, 0x14, 0x82, 0x1c, 0x0b, 0x74
-	},
-};
+static const uint8_t allowed_command_hashes
+	[TOUCHPAD_ELAN_DEBUG_NUM_CMD][SHA256_DIGEST_SIZE] = {
+		{ 0x0a, 0xf6, 0x37, 0x03, 0x93, 0xb2, 0xde, 0x8c,
+		  0x56, 0x7b, 0x86, 0xba, 0xa6, 0x79, 0xe3, 0xa3,
+		  0x8b, 0xc7, 0x15, 0xf2, 0x53, 0xcf, 0x71, 0x8b,
+		  0x3d, 0xe4, 0x81, 0xf9, 0xd9, 0xa8, 0x78, 0x48 },
+		{ 0xac, 0xe5, 0xbf, 0x17, 0x1f, 0xde, 0xce, 0x76,
+		  0x0c, 0x0e, 0xf8, 0xa2, 0xe9, 0x67, 0x2d, 0xc9,
+		  0x1b, 0xd4, 0xba, 0x34, 0x51, 0xca, 0xf6, 0x6d,
+		  0x7b, 0xb2, 0x1f, 0x14, 0x82, 0x1c, 0x0b, 0x74 },
+	};
 
 /* Debugging commands need to allocate a <=1k buffer. */
 SHARED_MEM_CHECK_SIZE(1024);
@@ -677,8 +670,8 @@ int touchpad_debug(const uint8_t *param, unsigned int param_size,
 		uint8_t *command_hash;
 		unsigned int offset = param[1];
 		unsigned int write_length = param[2];
-		unsigned int read_length =
-			((unsigned int)param[3] << 8) | param[4];
+		unsigned int read_length = ((unsigned int)param[3] << 8) |
+					   param[4];
 		int i;
 		int match;
 		int rv;
@@ -688,13 +681,14 @@ int touchpad_debug(const uint8_t *param, unsigned int param_size,
 			return EC_RES_INVALID_PARAM;
 
 		SHA256_init(&ctx);
-		SHA256_update(&ctx, param+5, TOUCHPAD_ELAN_DEBUG_CMD_LENGTH-5);
+		SHA256_update(&ctx, param + 5,
+			      TOUCHPAD_ELAN_DEBUG_CMD_LENGTH - 5);
 		command_hash = SHA256_final(&ctx);
 
 		match = 0;
 		for (i = 0; i < TOUCHPAD_ELAN_DEBUG_NUM_CMD; i++) {
 			if (!memcmp(command_hash, allowed_command_hashes[i],
-					sizeof(allowed_command_hashes[i]))) {
+				    sizeof(allowed_command_hashes[i]))) {
 				match = 1;
 				break;
 			}
@@ -711,8 +705,8 @@ int touchpad_debug(const uint8_t *param, unsigned int param_size,
 		buffer_size = read_length;
 
 		if (read_length > 0) {
-			if (shared_mem_acquire(buffer_size,
-				    (char **)&buffer) != EC_SUCCESS) {
+			if (shared_mem_acquire(buffer_size, (char **)&buffer) !=
+			    EC_SUCCESS) {
 				buffer = NULL;
 				buffer_size = 0;
 				return EC_RES_BUSY;
@@ -722,9 +716,8 @@ int touchpad_debug(const uint8_t *param, unsigned int param_size,
 		}
 
 		rv = i2c_xfer(CONFIG_TOUCHPAD_I2C_PORT,
-			      CONFIG_TOUCHPAD_I2C_ADDR_FLAGS,
-			      &param[offset], write_length,
-			      buffer, read_length);
+			      CONFIG_TOUCHPAD_I2C_ADDR_FLAGS, &param[offset],
+			      write_length, buffer, read_length);
 
 		if (rv)
 			return EC_RES_BUS_ERROR;
@@ -796,7 +789,7 @@ static void touchpad_power_control(void)
 
 #ifdef CONFIG_USB_SUSPEND
 	enable = enable &&
-		(!usb_is_suspended() || usb_is_remote_wakeup_enabled());
+		 (!usb_is_suspended() || usb_is_remote_wakeup_enabled());
 #endif
 
 #ifdef CONFIG_TABLET_MODE
diff --git a/driver/touchpad_gt7288.c b/driver/touchpad_gt7288.c
index ac05b88323..9d9b31a22b 100644
--- a/driver/touchpad_gt7288.c
+++ b/driver/touchpad_gt7288.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,7 @@
 /* Define this to enable various warning messages during report parsing. */
 #undef DEBUG_CHECKS
 
-#define CPRINTS(format, args...) cprints(CC_TOUCHPAD, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_TOUCHPAD, format, ##args)
 
 #define GT7288_I2C_ADDR_FLAGS 0x14
 
@@ -44,9 +44,8 @@
 static int gt7288_read_desc(uint16_t register_id, uint8_t *data,
 			    size_t max_length)
 {
-	uint8_t reg_bytes[] = {
-		register_id & 0xFF, (register_id & 0xFF00) >> 8
-	};
+	uint8_t reg_bytes[] = { register_id & 0xFF,
+				(register_id & 0xFF00) >> 8 };
 	return i2c_xfer(CONFIG_TOUCHPAD_I2C_PORT, GT7288_I2C_ADDR_FLAGS,
 			reg_bytes, sizeof(reg_bytes), data, max_length);
 }
@@ -88,8 +87,8 @@ static void gt7288_translate_contact(const uint8_t *data,
 
 static int gt7288_read(uint8_t *data, size_t max_length)
 {
-	return i2c_xfer(CONFIG_TOUCHPAD_I2C_PORT, GT7288_I2C_ADDR_FLAGS,
-			NULL, 0, data, max_length);
+	return i2c_xfer(CONFIG_TOUCHPAD_I2C_PORT, GT7288_I2C_ADDR_FLAGS, NULL,
+			0, data, max_length);
 }
 
 int gt7288_read_ptp_report(struct gt7288_ptp_report *report)
@@ -102,8 +101,8 @@ int gt7288_read_ptp_report(struct gt7288_ptp_report *report)
 
 	if (data[10] > GT7288_MAX_CONTACTS) {
 		if (IS_ENABLED(DEBUG_CHECKS))
-			CPRINTS("ERROR: too many contacts (%d > %d).",
-				data[10], GT7288_MAX_CONTACTS);
+			CPRINTS("ERROR: too many contacts (%d > %d).", data[10],
+				GT7288_MAX_CONTACTS);
 		return EC_ERROR_HW_INTERNAL;
 	}
 	report->num_contacts = data[10];
@@ -126,7 +125,7 @@ int gt7288_read_ptp_report(struct gt7288_ptp_report *report)
 }
 
 #ifdef CONFIG_CMD_GT7288
-static int command_gt7288_read_desc(int argc, char **argv)
+static int command_gt7288_read_desc(int argc, const char **argv)
 {
 	uint16_t register_id;
 	long parsed_arg;
@@ -150,11 +149,10 @@ static int command_gt7288_read_desc(int argc, char **argv)
 	ccprintf("\n");
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(gt7288_desc, command_gt7288_read_desc,
-			"register",
+DECLARE_CONSOLE_COMMAND(gt7288_desc, command_gt7288_read_desc, "register",
 			"Read a descriptor on the GT7288");
 
-static int command_gt7288_read_report_descriptor(int argc, char **argv)
+static int command_gt7288_read_report_descriptor(int argc, const char **argv)
 {
 	int i;
 	uint8_t data[64];
@@ -185,7 +183,7 @@ static int command_gt7288_read_report_descriptor(int argc, char **argv)
 DECLARE_CONSOLE_COMMAND(gt7288_repdesc, command_gt7288_read_report_descriptor,
 			"", "Read the report descriptor on the GT7288");
 
-static int command_gt7288_ver(int argc, char **argv)
+static int command_gt7288_ver(int argc, const char **argv)
 {
 	struct gt7288_version_info info;
 
@@ -200,7 +198,7 @@ static int command_gt7288_ver(int argc, char **argv)
 DECLARE_CONSOLE_COMMAND(gt7288_ver, command_gt7288_ver, "",
 			"Read version information from the GT7288");
 
-static int command_gt7288_report(int argc, char **argv)
+static int command_gt7288_report(int argc, const char **argv)
 {
 	int i;
 	struct gt7288_ptp_report report;
diff --git a/driver/touchpad_gt7288.h b/driver/touchpad_gt7288.h
index c89c586784..ad8d43636e 100644
--- a/driver/touchpad_gt7288.h
+++ b/driver/touchpad_gt7288.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/driver/touchpad_st.c b/driver/touchpad_st.c
index 56633bad16..ad10470ed9 100644
--- a/driver/touchpad_st.c
+++ b/driver/touchpad_st.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,6 +11,7 @@
 #include "hwtimer.h"
 #include "hooks.h"
 #include "i2c.h"
+#include "printf.h"
 #include "registers.h"
 #include "spi.h"
 #include "task.h"
@@ -28,11 +29,11 @@
 /* Console output macros */
 #define CC_TOUCHPAD CC_USB
 #define CPUTS(outstr) cputs(CC_TOUCHPAD, outstr)
-#define CPRINTF(format, args...) cprintf(CC_TOUCHPAD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_TOUCHPAD, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_TOUCHPAD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_TOUCHPAD, format, ##args)
 
-#define TASK_EVENT_POWER  TASK_EVENT_CUSTOM_BIT(0)
-#define TASK_EVENT_TP_UPDATED  TASK_EVENT_CUSTOM_BIT(1)
+#define TASK_EVENT_POWER TASK_EVENT_CUSTOM_BIT(0)
+#define TASK_EVENT_TP_UPDATED TASK_EVENT_CUSTOM_BIT(1)
 
 #define SPI (&(spi_devices[SPI_ST_TP_DEVICE_ID]))
 
@@ -55,26 +56,26 @@ static void touchpad_power_control(void);
  */
 static int system_state;
 
-#define SYSTEM_STATE_DEBUG_MODE		BIT(0)
-#define SYSTEM_STATE_ENABLE_HEAT_MAP	BIT(1)
-#define SYSTEM_STATE_ENABLE_DOME_SWITCH	BIT(2)
-#define SYSTEM_STATE_ACTIVE_MODE	BIT(3)
-#define SYSTEM_STATE_DOME_SWITCH_LEVEL	BIT(4)
-#define SYSTEM_STATE_READY		BIT(5)
+#define SYSTEM_STATE_DEBUG_MODE BIT(0)
+#define SYSTEM_STATE_ENABLE_HEAT_MAP BIT(1)
+#define SYSTEM_STATE_ENABLE_DOME_SWITCH BIT(2)
+#define SYSTEM_STATE_ACTIVE_MODE BIT(3)
+#define SYSTEM_STATE_DOME_SWITCH_LEVEL BIT(4)
+#define SYSTEM_STATE_READY BIT(5)
 
 /*
  * Pending action for touchpad.
  */
 static int tp_control;
 
-#define TP_CONTROL_SHALL_HALT		BIT(0)
-#define TP_CONTROL_SHALL_RESET		BIT(1)
-#define TP_CONTROL_SHALL_INIT		BIT(2)
-#define TP_CONTROL_SHALL_INIT_FULL	BIT(3)
-#define TP_CONTROL_SHALL_DUMP_ERROR	BIT(4)
-#define TP_CONTROL_RESETTING		BIT(5)
-#define TP_CONTROL_INIT			BIT(6)
-#define TP_CONTROL_INIT_FULL		BIT(7)
+#define TP_CONTROL_SHALL_HALT BIT(0)
+#define TP_CONTROL_SHALL_RESET BIT(1)
+#define TP_CONTROL_SHALL_INIT BIT(2)
+#define TP_CONTROL_SHALL_INIT_FULL BIT(3)
+#define TP_CONTROL_SHALL_DUMP_ERROR BIT(4)
+#define TP_CONTROL_RESETTING BIT(5)
+#define TP_CONTROL_INIT BIT(6)
+#define TP_CONTROL_INIT_FULL BIT(7)
 
 /*
  * Number of times we have reset the touchpad because of errors.
@@ -115,7 +116,6 @@ static struct {
 	} /* anonymous */;
 } __packed rx_buf;
 
-
 #ifdef CONFIG_USB_ISOCHRONOUS
 #define USB_ISO_PACKET_SIZE 256
 /*
@@ -124,7 +124,7 @@ static struct {
 struct packet_header_t {
 	uint8_t index;
 
-#define HEADER_FLAGS_NEW_FRAME	BIT(0)
+#define HEADER_FLAGS_NEW_FRAME BIT(0)
 	uint8_t flags;
 } __packed;
 BUILD_ASSERT(sizeof(struct packet_header_t) < USB_ISO_PACKET_SIZE);
@@ -133,7 +133,7 @@ static struct packet_header_t packet_header;
 
 /* What will be sent to USB interface. */
 struct st_tp_usb_packet_t {
-#define USB_FRAME_FLAGS_BUTTON	BIT(0)
+#define USB_FRAME_FLAGS_BUTTON BIT(0)
 	/*
 	 * This will be true if user clicked on touchpad.
 	 * TODO(b/70482333): add corresponding code for button signal.
@@ -165,7 +165,6 @@ static void st_tp_interrupt_send(void);
 DECLARE_DEFERRED(st_tp_interrupt_send);
 #endif
 
-
 /* Function implementations */
 
 static void set_bits(int *lvalue, int rvalue, int mask)
@@ -184,8 +183,7 @@ static void set_bits(int *lvalue, int rvalue, int mask)
  * @return array index of next finger (i.e. (i + 1) if a finger is added).
  */
 static int st_tp_parse_finger(struct usb_hid_touchpad_report *report,
-			      struct st_tp_event_t *event,
-			      int i)
+			      struct st_tp_event_t *event, int i)
 {
 	const int id = event->finger.touch_id;
 
@@ -193,9 +191,9 @@ static int st_tp_parse_finger(struct usb_hid_touchpad_report *report,
 	if (event->finger.touch_type == ST_TP_TOUCH_TYPE_INVALID)
 		return i;
 
-	if (event->evt_id ==  ST_TP_EVENT_ID_ENTER_POINTER)
+	if (event->evt_id == ST_TP_EVENT_ID_ENTER_POINTER)
 		touch_slot |= 1 << id;
-	else if (event->evt_id ==  ST_TP_EVENT_ID_LEAVE_POINTER)
+	else if (event->evt_id == ST_TP_EVENT_ID_LEAVE_POINTER)
 		touch_slot &= ~BIT(id);
 
 	/* We cannot report more fingers */
@@ -213,10 +211,10 @@ static int st_tp_parse_finger(struct usb_hid_touchpad_report *report,
 		report->finger[i].inrange = 1;
 		report->finger[i].id = id;
 		report->finger[i].pressure = event->finger.z;
-		report->finger[i].width = (event->finger.minor |
-					   (event->minor_high << 4)) << 5;
-		report->finger[i].height = (event->finger.major |
-					    (event->major_high << 4)) << 5;
+		report->finger[i].width =
+			(event->finger.minor | (event->minor_high << 4)) << 5;
+		report->finger[i].height =
+			(event->finger.major | (event->major_high << 4)) << 5;
 
 		report->finger[i].x = (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X -
 				       event->finger.x);
@@ -253,8 +251,7 @@ static int st_tp_check_domeswitch_state(void)
 	 * Domeswitch level from device is inverted.
 	 * That is, 0 => pressed, 1 => released.
 	 */
-	set_bits(&system_state,
-		 ret ? 0 : SYSTEM_STATE_DOME_SWITCH_LEVEL,
+	set_bits(&system_state, ret ? 0 : SYSTEM_STATE_DOME_SWITCH_LEVEL,
 		 SYSTEM_STATE_DOME_SWITCH_LEVEL);
 	return 0;
 }
@@ -295,7 +292,7 @@ static int st_tp_write_hid_report(void)
 		}
 	}
 
-	if (!num_finger && !domeswitch_changed)  /* nothing changed */
+	if (!num_finger && !domeswitch_changed) /* nothing changed */
 		return 0;
 
 	/* Don't report 0 finger click. */
@@ -343,8 +340,8 @@ static int st_tp_read_host_buffer_header(void)
 	const uint8_t tx_buf[] = { ST_TP_CMD_READ_SPI_HOST_BUFFER, 0x00, 0x00 };
 	int rx_len = ST_TP_EXTRA_BYTE + sizeof(rx_buf.buffer_header);
 
-	return spi_transaction(SPI, tx_buf, sizeof(tx_buf),
-			       (uint8_t *)&rx_buf, rx_len);
+	return spi_transaction(SPI, tx_buf, sizeof(tx_buf), (uint8_t *)&rx_buf,
+			       rx_len);
 }
 
 static int st_tp_send_ack(void)
@@ -368,11 +365,7 @@ static int st_tp_update_system_state(int new_state, int mask)
 
 	mask = SYSTEM_STATE_ENABLE_HEAT_MAP | SYSTEM_STATE_ENABLE_DOME_SWITCH;
 	if ((new_state & mask) != (system_state & mask)) {
-		uint8_t tx_buf[] = {
-			ST_TP_CMD_WRITE_FEATURE_SELECT,
-			0x05,
-			0
-		};
+		uint8_t tx_buf[] = { ST_TP_CMD_WRITE_FEATURE_SELECT, 0x05, 0 };
 		if (new_state & SYSTEM_STATE_ENABLE_HEAT_MAP) {
 			CPRINTS("Heatmap enabled");
 			tx_buf[2] |= BIT(0);
@@ -423,8 +416,8 @@ static int st_tp_update_system_state(int new_state, int mask)
 
 static void st_tp_enable_interrupt(int enable)
 {
-	uint8_t tx_buf[] = {
-		ST_TP_CMD_WRITE_SYSTEM_COMMAND, 0x01, enable ? 1 : 0};
+	uint8_t tx_buf[] = { ST_TP_CMD_WRITE_SYSTEM_COMMAND, 0x01,
+			     enable ? 1 : 0 };
 	if (enable)
 		gpio_enable_interrupt(GPIO_TOUCHPAD_INT);
 	spi_transaction(SPI, tx_buf, sizeof(tx_buf), NULL, 0);
@@ -434,8 +427,8 @@ static void st_tp_enable_interrupt(int enable)
 
 static int st_tp_start_scan(void)
 {
-	int new_state = (SYSTEM_STATE_ACTIVE_MODE |
-			 SYSTEM_STATE_ENABLE_DOME_SWITCH);
+	int new_state =
+		(SYSTEM_STATE_ACTIVE_MODE | SYSTEM_STATE_ENABLE_DOME_SWITCH);
 	int mask = new_state;
 	int ret;
 
@@ -451,9 +444,8 @@ static int st_tp_start_scan(void)
 
 static int st_tp_read_host_data_memory(uint16_t addr, void *rx_buf, int len)
 {
-	uint8_t tx_buf[] = {
-		ST_TP_CMD_READ_HOST_DATA_MEMORY, addr >> 8, addr & 0xFF
-	};
+	uint8_t tx_buf[] = { ST_TP_CMD_READ_HOST_DATA_MEMORY, addr >> 8,
+			     addr & 0xFF };
 
 	return spi_transaction(SPI, tx_buf, sizeof(tx_buf), rx_buf, len);
 }
@@ -473,9 +465,7 @@ static int st_tp_stop_scan(void)
 
 static int st_tp_load_host_data(uint8_t mem_id)
 {
-	uint8_t tx_buf[] = {
-		ST_TP_CMD_WRITE_SYSTEM_COMMAND, 0x06, mem_id
-	};
+	uint8_t tx_buf[] = { ST_TP_CMD_WRITE_SYSTEM_COMMAND, 0x06, mem_id };
 	int retry, ret;
 	uint16_t count;
 	struct st_tp_host_data_header_t *header = &rx_buf.data_header;
@@ -559,24 +549,24 @@ static int st_tp_read_system_info(int reload)
  */
 static void enable_deep_sleep(int enable)
 {
-	uint8_t cmd[] = {0xFA, 0x20, 0x00, 0x00, 0x68, enable ? 0x0B : 0x08};
+	uint8_t cmd[] = { 0xFA, 0x20, 0x00, 0x00, 0x68, enable ? 0x0B : 0x08 };
 
 	spi_transaction(SPI, cmd, sizeof(cmd), NULL, 0);
 }
 
 static void dump_error(void)
 {
-	uint8_t tx_buf[] = {0xFB, 0x20, 0x01, 0xEF, 0x80};
+	uint8_t tx_buf[] = { 0xFB, 0x20, 0x01, 0xEF, 0x80 };
 	int rx_len = sizeof(rx_buf.dump_info) + ST_TP_EXTRA_BYTE;
 	int i;
 
-	spi_transaction(SPI, tx_buf, sizeof(tx_buf),
-			(uint8_t *)&rx_buf, rx_len);
+	spi_transaction(SPI, tx_buf, sizeof(tx_buf), (uint8_t *)&rx_buf,
+			rx_len);
 
 	for (i = 0; i < ARRAY_SIZE(rx_buf.dump_info); i += 4)
-		CPRINTS("%08x %08x %08x %08x",
-			rx_buf.dump_info[i + 0], rx_buf.dump_info[i + 1],
-			rx_buf.dump_info[i + 2], rx_buf.dump_info[i + 3]);
+		CPRINTS("%08x %08x %08x %08x", rx_buf.dump_info[i + 0],
+			rx_buf.dump_info[i + 1], rx_buf.dump_info[i + 2],
+			rx_buf.dump_info[i + 3]);
 	msleep(8);
 }
 
@@ -589,8 +579,8 @@ static void dump_error(void)
 static void dump_memory(void)
 {
 	uint32_t size = 0x10000, rx_len = 512 + ST_TP_EXTRA_BYTE;
-	uint32_t offset, i;
-	uint8_t cmd[] = {0xFB, 0x00, 0x10, 0x00, 0x00};
+	uint32_t offset, i, j;
+	uint8_t cmd[] = { 0xFB, 0x00, 0x10, 0x00, 0x00 };
 
 	if (!dump_memory_on_error)
 		return;
@@ -598,20 +588,20 @@ static void dump_memory(void)
 	for (offset = 0; offset < size; offset += 512) {
 		cmd[3] = (offset >> 8) & 0xFF;
 		cmd[4] = (offset >> 0) & 0xFF;
-		spi_transaction(SPI, cmd, sizeof(cmd),
-				(uint8_t *)&rx_buf, rx_len);
+		spi_transaction(SPI, cmd, sizeof(cmd), (uint8_t *)&rx_buf,
+				rx_len);
 
 		for (i = 0; i < rx_len - ST_TP_EXTRA_BYTE; i += 32) {
-			CPRINTF("%ph %ph %ph %ph "
-				"%ph %ph %ph %ph\n",
-				HEX_BUF(rx_buf.bytes + i + 4 * 0, 4),
-				HEX_BUF(rx_buf.bytes + i + 4 * 1, 4),
-				HEX_BUF(rx_buf.bytes + i + 4 * 2, 4),
-				HEX_BUF(rx_buf.bytes + i + 4 * 3, 4),
-				HEX_BUF(rx_buf.bytes + i + 4 * 4, 4),
-				HEX_BUF(rx_buf.bytes + i + 4 * 5, 4),
-				HEX_BUF(rx_buf.bytes + i + 4 * 6, 4),
-				HEX_BUF(rx_buf.bytes + i + 4 * 7, 4));
+			for (j = 0; j < 8; j++) {
+				char str_buf[hex_str_buf_size(4)];
+
+				snprintf_hex_buffer(
+					str_buf, sizeof(str_buf),
+					HEX_BUF(rx_buf.bytes + i + 4 * j, 4));
+
+				CPRINTF("%s ", str_buf);
+			}
+			CPRINTF("\n");
 			msleep(8);
 		}
 	}
@@ -629,11 +619,8 @@ static void st_tp_handle_error(uint8_t error_type)
 	/*
 	 * Suggest action: memory dump and power cycle.
 	 */
-	if (error_type <= 0x06 ||
-	    error_type == 0xF1 ||
-	    error_type == 0xF2 ||
-	    error_type == 0xF3 ||
-	    (error_type >= 0x47 && error_type <= 0x4E)) {
+	if (error_type <= 0x06 || error_type == 0xF1 || error_type == 0xF2 ||
+	    error_type == 0xF3 || (error_type >= 0x47 && error_type <= 0x4E)) {
 		tp_control |= TP_CONTROL_SHALL_RESET;
 		return;
 	}
@@ -641,8 +628,7 @@ static void st_tp_handle_error(uint8_t error_type)
 	/*
 	 * Suggest action: FW shall halt, consult ST.
 	 */
-	if ((error_type >= 0x20 && error_type <= 0x23) ||
-	    error_type == 0x25 ||
+	if ((error_type >= 0x20 && error_type <= 0x23) || error_type == 0x25 ||
 	    (error_type >= 0x2E && error_type <= 0x46)) {
 		CPRINTS("tp shall halt");
 		tp_control |= TP_CONTROL_SHALL_HALT;
@@ -697,15 +683,13 @@ static void st_tp_handle_error_report(struct st_tp_event_t *e)
 static void st_tp_handle_status_report(struct st_tp_event_t *e)
 {
 	static uint32_t prev_idle_count;
-	uint32_t info = ((e->report.info[0] << 0) |
-			 (e->report.info[1] << 8) |
-			 (e->report.info[2] << 16) |
-			 (e->report.info[3] << 24));
+	uint32_t info = ((e->report.info[0] << 0) | (e->report.info[1] << 8) |
+			 (e->report.info[2] << 16) | (e->report.info[3] << 24));
 
 	if (e->report.report_type == ST_TP_STATUS_FCAL ||
 	    e->report.report_type == ST_TP_STATUS_FRAME_DROP)
-		CPRINTS("TP STATUS REPORT: %02x %08x",
-			e->report.report_type, info);
+		CPRINTS("TP STATUS REPORT: %02x %08x", e->report.report_type,
+			info);
 
 	/*
 	 * Idle count might not change if ST FW is busy (for example, when the
@@ -803,8 +787,8 @@ static int st_tp_reset(void)
 		 * suggest us to reset or halt.
 		 */
 		if (!(tp_control & (TP_CONTROL_INIT | TP_CONTROL_INIT_FULL)) &&
-		    (tp_control & (TP_CONTROL_SHALL_HALT |
-				   TP_CONTROL_SHALL_RESET)))
+		    (tp_control &
+		     (TP_CONTROL_SHALL_HALT | TP_CONTROL_SHALL_RESET)))
 			break;
 
 		for (i = 0; i < num_events; i++) {
@@ -883,14 +867,10 @@ int touchpad_get_info(struct touchpad_info *tp)
 static int write_hwreg_cmd32(uint32_t address, uint32_t data)
 {
 	uint8_t tx_buf[] = {
-		ST_TP_CMD_WRITE_HW_REG,
-		(address >> 24) & 0xFF,
-		(address >> 16) & 0xFF,
-		(address >> 8) & 0xFF,
-		(address >> 0) & 0xFF,
-		(data >> 24) & 0xFF,
-		(data >> 16) & 0xFF,
-		(data >> 8) & 0xFF,
+		ST_TP_CMD_WRITE_HW_REG, (address >> 24) & 0xFF,
+		(address >> 16) & 0xFF, (address >> 8) & 0xFF,
+		(address >> 0) & 0xFF,	(data >> 24) & 0xFF,
+		(data >> 16) & 0xFF,	(data >> 8) & 0xFF,
 		(data >> 0) & 0xFF,
 	};
 
@@ -900,12 +880,9 @@ static int write_hwreg_cmd32(uint32_t address, uint32_t data)
 static int write_hwreg_cmd8(uint32_t address, uint8_t data)
 {
 	uint8_t tx_buf[] = {
-		ST_TP_CMD_WRITE_HW_REG,
-		(address >> 24) & 0xFF,
-		(address >> 16) & 0xFF,
-		(address >> 8) & 0xFF,
-		(address >> 0) & 0xFF,
-		data,
+		ST_TP_CMD_WRITE_HW_REG, (address >> 24) & 0xFF,
+		(address >> 16) & 0xFF, (address >> 8) & 0xFF,
+		(address >> 0) & 0xFF,	data,
 	};
 
 	return spi_transaction(SPI, tx_buf, sizeof(tx_buf), NULL, 0);
@@ -914,8 +891,7 @@ static int write_hwreg_cmd8(uint32_t address, uint8_t data)
 static int wait_for_flash_ready(uint8_t type)
 {
 	uint8_t tx_buf[] = {
-		ST_TP_CMD_READ_HW_REG,
-		0x20, 0x00, 0x00, type,
+		ST_TP_CMD_READ_HW_REG, 0x20, 0x00, 0x00, type,
 	};
 	int ret = EC_SUCCESS, retry = 200;
 
@@ -973,8 +949,8 @@ static int st_tp_start_flash_dma(void)
 	return ret;
 }
 
-static int st_tp_write_one_chunk(const uint8_t *head,
-				 uint32_t addr, uint32_t chunk_size)
+static int st_tp_write_one_chunk(const uint8_t *head, uint32_t addr,
+				 uint32_t chunk_size)
 {
 	uint8_t tx_buf[ST_TP_DMA_CHUNK_SIZE + 5];
 	uint32_t index = 0;
@@ -1000,13 +976,13 @@ static int st_tp_write_one_chunk(const uint8_t *head,
  */
 static int st_tp_write_flash(int offset, int size, const uint8_t *data)
 {
-	uint8_t tx_buf[12] = {0};
+	uint8_t tx_buf[12] = { 0 };
 	const uint8_t *head = data, *tail = data + size;
 	uint32_t addr, index, chunk_size;
 	uint32_t flash_buffer_size;
 	int ret;
 
-	offset >>= 2;  /* offset should be count in words */
+	offset >>= 2; /* offset should be count in words */
 	/*
 	 * To write to flash, the data has to be separated into several chunks.
 	 * Each chunk will be no more than `ST_TP_DMA_CHUNK_SIZE` bytes.
@@ -1039,7 +1015,7 @@ static int st_tp_write_flash(int offset, int size, const uint8_t *data)
 		tx_buf[index++] = 0x20;
 		tx_buf[index++] = 0x00;
 		tx_buf[index++] = 0x00;
-		tx_buf[index++] = 0x72;  /* flash DMA config */
+		tx_buf[index++] = 0x72; /* flash DMA config */
 		tx_buf[index++] = 0x00;
 		tx_buf[index++] = 0x00;
 
@@ -1108,9 +1084,7 @@ static uint8_t get_cx_version(uint8_t tp_version)
  */
 static int st_tp_panel_init(int full)
 {
-	uint8_t tx_buf[] = {
-		ST_TP_CMD_WRITE_SYSTEM_COMMAND, 0x00, 0x02
-	};
+	uint8_t tx_buf[] = { ST_TP_CMD_WRITE_SYSTEM_COMMAND, 0x00, 0x02 };
 	int ret, retry;
 
 	if (tp_control & (TP_CONTROL_INIT | TP_CONTROL_INIT_FULL))
@@ -1149,8 +1123,8 @@ static int st_tp_panel_init(int full)
 			return EC_SUCCESS;
 		} else if (ret == EC_ERROR_BUSY) {
 			CPRINTS("Panel initialization on going...");
-		} else if (tp_control & ~(TP_CONTROL_INIT |
-					  TP_CONTROL_INIT_FULL)) {
+		} else if (tp_control &
+			   ~(TP_CONTROL_INIT | TP_CONTROL_INIT_FULL)) {
 			/* there are other kind of errors. */
 			CPRINTS("Panel initialization failed, tp_control: %x",
 				tp_control);
@@ -1262,21 +1236,25 @@ int touchpad_debug(const uint8_t *param, unsigned int param_size,
 		*data_size = 0;
 		st_tp_stop_scan();
 		return EC_SUCCESS;
-	case ST_TP_DEBUG_CMD_READ_BUF_HEADER:
+	case ST_TP_DEBUG_CMD_READ_BUF_HEADER: {
+		char str_buf[hex_str_buf_size(8)];
 		*data = buf;
 		*data_size = 8;
 		st_tp_read_host_buffer_header();
 		memcpy(buf, rx_buf.bytes, *data_size);
-		CPRINTS("header: %ph", HEX_BUF(buf, *data_size));
+		snprintf_hex_buffer(str_buf, sizeof(str_buf),
+				    HEX_BUF(buf, *data_size));
+		CPRINTS("header: %s", str_buf);
 		return EC_SUCCESS;
+	}
 	case ST_TP_DEBUG_CMD_READ_EVENTS:
 		num_events = st_tp_read_all_events(0);
 		if (num_events) {
 			int i;
 
 			for (i = 0; i < num_events; i++) {
-				CPRINTS("event[%d]: id=%d, type=%d",
-					i, rx_buf.events[i].evt_id,
+				CPRINTS("event[%d]: id=%d, type=%d", i,
+					rx_buf.events[i].evt_id,
 					rx_buf.events[i].report.report_type);
 			}
 		}
@@ -1336,9 +1314,7 @@ static void touchpad_read_idle_count(void)
 	uint32_t count;
 	int ret;
 	int rx_len = 2 + ST_TP_EXTRA_BYTE;
-	uint8_t cmd_read_counter[] = {
-		0xFB, 0x00, 0x10, 0xff, 0xff
-	};
+	uint8_t cmd_read_counter[] = { 0xFB, 0x00, 0x10, 0xff, 0xff };
 
 	/* Find address of idle count. */
 	ret = st_tp_load_host_data(ST_TP_MEM_ID_SYSTEM_INFO);
@@ -1373,13 +1349,9 @@ static void touchpad_read_idle_count(void)
  */
 static void touchpad_collect_error(void)
 {
-	const uint8_t tx_dump_error[] = {
-		0xFB, 0x20, 0x01, 0xEF, 0x80
-	};
+	const uint8_t tx_dump_error[] = { 0xFB, 0x20, 0x01, 0xEF, 0x80 };
 	uint32_t dump_info[2];
-	const uint8_t tx_dump_memory[] = {
-		0xFB, 0x00, 0x10, 0x00, 0x00
-	};
+	const uint8_t tx_dump_memory[] = { 0xFB, 0x00, 0x10, 0x00, 0x00 };
 	uint32_t dump_memory[16];
 	int i;
 
@@ -1398,14 +1370,10 @@ static void touchpad_collect_error(void)
 	CPRINTS("check memory dump:");
 	for (i = 0; i < ARRAY_SIZE(dump_memory); i += 8) {
 		CPRINTF("%08x %08x %08x %08x %08x %08x %08x %08x\n",
-			dump_memory[i + 0],
-			dump_memory[i + 1],
-			dump_memory[i + 2],
-			dump_memory[i + 3],
-			dump_memory[i + 4],
-			dump_memory[i + 5],
-			dump_memory[i + 6],
-			dump_memory[i + 7]);
+			dump_memory[i + 0], dump_memory[i + 1],
+			dump_memory[i + 2], dump_memory[i + 3],
+			dump_memory[i + 4], dump_memory[i + 5],
+			dump_memory[i + 6], dump_memory[i + 7]);
 	}
 
 	for (i = 0; i < 3; i++)
@@ -1522,9 +1490,9 @@ DECLARE_HOOK(HOOK_TABLET_MODE_CHANGE, touchpad_power_change, HOOK_PRIO_DEFAULT);
 #ifdef CONFIG_USB_ISOCHRONOUS
 static void st_tp_enable_heat_map(void)
 {
-	int new_state = (SYSTEM_STATE_ENABLE_HEAT_MAP |
-			 SYSTEM_STATE_ENABLE_DOME_SWITCH |
-			 SYSTEM_STATE_ACTIVE_MODE);
+	int new_state =
+		(SYSTEM_STATE_ENABLE_HEAT_MAP |
+		 SYSTEM_STATE_ENABLE_DOME_SWITCH | SYSTEM_STATE_ACTIVE_MODE);
 	int mask = new_state;
 
 	st_tp_update_system_state(new_state, mask);
@@ -1619,8 +1587,8 @@ static int st_tp_read_frame(void)
 	 * valid, but the data should always be ready when interrupt pin is low.
 	 * Let's skip this check for now.
 	 */
-	ret = spi_transaction(SPI, tx_buf, sizeof(tx_buf),
-			      (uint8_t *)rx_buf, rx_len);
+	ret = spi_transaction(SPI, tx_buf, sizeof(tx_buf), (uint8_t *)rx_buf,
+			      rx_len);
 	if (ret == EC_SUCCESS) {
 		int i;
 		uint8_t *dest = usb_packet[spi_buffer_index & 1].frame;
@@ -1649,16 +1617,12 @@ static int heatmap_send_packet(struct usb_isochronous_config const *config);
 static void st_tp_usb_tx_callback(struct usb_isochronous_config const *config);
 
 /* USB descriptors */
-USB_ISOCHRONOUS_CONFIG_FULL(usb_st_tp_heatmap_config,
-			    USB_IFACE_ST_TOUCHPAD,
-			    USB_CLASS_VENDOR_SPEC,
-			    USB_SUBCLASS_GOOGLE_HEATMAP,
+USB_ISOCHRONOUS_CONFIG_FULL(usb_st_tp_heatmap_config, USB_IFACE_ST_TOUCHPAD,
+			    USB_CLASS_VENDOR_SPEC, USB_SUBCLASS_GOOGLE_HEATMAP,
 			    USB_PROTOCOL_GOOGLE_HEATMAP,
-			    USB_STR_HEATMAP_NAME,  /* interface name */
-			    USB_EP_ST_TOUCHPAD,
-			    USB_ISO_PACKET_SIZE,
-			    st_tp_usb_tx_callback,
-			    st_tp_usb_set_interface,
+			    USB_STR_HEATMAP_NAME, /* interface name */
+			    USB_EP_ST_TOUCHPAD, USB_ISO_PACKET_SIZE,
+			    st_tp_usb_tx_callback, st_tp_usb_set_interface,
 			    1 /* 1 extra EP for interrupts */)
 
 /* ***This function will be executed in interrupt context*** */
@@ -1703,13 +1667,10 @@ static int heatmap_send_packet(struct usb_isochronous_config const *config)
 	if (num_byte_available > 0) {
 		if (transmit_report_offset == 0)
 			packet_header.flags |= HEADER_FLAGS_NEW_FRAME;
-		ret = usb_isochronous_write_buffer(
-				config,
-				(uint8_t *)&packet_header,
-				sizeof(packet_header),
-				offset,
-				&buffer_id,
-				0);
+		ret = usb_isochronous_write_buffer(config,
+						   (uint8_t *)&packet_header,
+						   sizeof(packet_header),
+						   offset, &buffer_id, 0);
 		/*
 		 * Since USB_ISO_PACKET_SIZE > sizeof(packet_header), this must
 		 * be true.
@@ -1721,12 +1682,8 @@ static int heatmap_send_packet(struct usb_isochronous_config const *config)
 		packet_header.index++;
 
 		ret = usb_isochronous_write_buffer(
-				config,
-				(uint8_t *)packet + transmit_report_offset,
-				num_byte_available,
-				offset,
-				&buffer_id,
-				1);
+			config, (uint8_t *)packet + transmit_report_offset,
+			num_byte_available, offset, &buffer_id, 1);
 		if (ret < 0) {
 			/*
 			 * TODO(b/70482333): handle this error, it might be:
@@ -1766,7 +1723,7 @@ static int st_tp_usb_set_interface(usb_uint alternate_setting,
 	} else if (alternate_setting == 0) {
 		hook_call_deferred(&st_tp_disable_heat_map_data, 0);
 		return 0;
-	} else  /* we only have two settings. */
+	} else /* we only have two settings. */
 		return -1;
 }
 
@@ -1785,12 +1742,12 @@ static int get_heat_map_addr(void)
 }
 
 struct st_tp_interrupt_t {
-#define ST_TP_INT_FRAME_AVAILABLE	BIT(0)
+#define ST_TP_INT_FRAME_AVAILABLE BIT(0)
 	uint8_t flags;
 } __packed;
 
-static usb_uint st_tp_usb_int_buffer[
-	DIV_ROUND_UP(sizeof(struct st_tp_interrupt_t), 2)] __usb_ram;
+static usb_uint st_tp_usb_int_buffer[DIV_ROUND_UP(
+	sizeof(struct st_tp_interrupt_t), 2)] __usb_ram;
 
 const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_ST_TOUCHPAD, 81) = {
 	.bLength = USB_DT_ENDPOINT_SIZE,
@@ -1809,8 +1766,8 @@ static void st_tp_interrupt_send(void)
 
 	if (usb_buffer_index < spi_buffer_index)
 		report.flags |= ST_TP_INT_FRAME_AVAILABLE;
-	memcpy_to_usbram((void *)usb_sram_addr(st_tp_usb_int_buffer),
-			 &report, sizeof(report));
+	memcpy_to_usbram((void *)usb_sram_addr(st_tp_usb_int_buffer), &report,
+			 sizeof(report));
 	/* enable TX */
 	STM32_TOGGLE_EP(USB_EP_ST_TOUCHPAD_INT, EP_TX_MASK, EP_TX_VALID, 0);
 	usb_wake();
@@ -1833,10 +1790,8 @@ static void st_tp_interrupt_event(enum usb_ep_event evt)
 		btable_ep[ep].tx_addr = usb_sram_addr(st_tp_usb_int_buffer);
 		btable_ep[ep].tx_count = sizeof(struct st_tp_interrupt_t);
 
-		STM32_USB_EP(ep) = ((ep << 0) |
-				    EP_TX_VALID |
-				    (3 << 9) /* interrupt EP */ |
-				    EP_RX_DISAB);
+		STM32_USB_EP(ep) = ((ep << 0) | EP_TX_VALID |
+				    (3 << 9) /* interrupt EP */ | EP_RX_DISAB);
 	}
 }
 
@@ -1846,7 +1801,7 @@ USB_DECLARE_EP(USB_EP_ST_TOUCHPAD_INT, st_tp_interrupt_tx, st_tp_interrupt_tx,
 #endif
 
 /* Debugging commands */
-static int command_touchpad_st(int argc, char **argv)
+static int command_touchpad_st(int argc, const char **argv)
 {
 	if (argc < 2)
 		return EC_ERROR_PARAM_COUNT;
diff --git a/driver/touchpad_st.h b/driver/touchpad_st.h
index ef0960591b..6ea3f6aeb0 100644
--- a/driver/touchpad_st.h
+++ b/driver/touchpad_st.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,71 +10,69 @@
 
 #include "common.h"
 
-#define ST_VENDOR_ID		0x0483
+#define ST_VENDOR_ID 0x0483
 
-#define ST_TP_EXTRA_BYTE	1
+#define ST_TP_EXTRA_BYTE 1
 
-#define ST_TP_CMD_READ_ALL_EVENTS		0x87
-#define ST_TP_CMD_WRITE_SCAN_MODE_SELECT	0xA0
-#define ST_TP_CMD_WRITE_FEATURE_SELECT		0xA2
-#define ST_TP_CMD_WRITE_SYSTEM_COMMAND		0xA4
-#define ST_TP_CMD_WRITE_HOST_DATA_MEMORY	0xA6
-#define ST_TP_CMD_READ_HOST_DATA_MEMORY		0xA7
-#define ST_TP_CMD_WRITE_FW_CONFIG		0xA8
-#define ST_TP_CMD_READ_FW_CONFIG		0xA9
-#define ST_TP_CMD_SPI_HOST_BUFFER_ACK		0xC0
-#define ST_TP_CMD_READ_SPI_HOST_BUFFER		0xC1
+#define ST_TP_CMD_READ_ALL_EVENTS 0x87
+#define ST_TP_CMD_WRITE_SCAN_MODE_SELECT 0xA0
+#define ST_TP_CMD_WRITE_FEATURE_SELECT 0xA2
+#define ST_TP_CMD_WRITE_SYSTEM_COMMAND 0xA4
+#define ST_TP_CMD_WRITE_HOST_DATA_MEMORY 0xA6
+#define ST_TP_CMD_READ_HOST_DATA_MEMORY 0xA7
+#define ST_TP_CMD_WRITE_FW_CONFIG 0xA8
+#define ST_TP_CMD_READ_FW_CONFIG 0xA9
+#define ST_TP_CMD_SPI_HOST_BUFFER_ACK 0xC0
+#define ST_TP_CMD_READ_SPI_HOST_BUFFER 0xC1
 
-#define ST_TP_CMD_WRITE_HW_REG			0xFA
-#define ST_TP_CMD_READ_HW_REG			0xFB
+#define ST_TP_CMD_WRITE_HW_REG 0xFA
+#define ST_TP_CMD_READ_HW_REG 0xFB
 
 /* Max number of bytes that the DMA can burn on the flash in one shot in FTI */
-#define ST_TP_FLASH_BUFFER_SIZE		(64 * 1024)
+#define ST_TP_FLASH_BUFFER_SIZE (64 * 1024)
 /* Max number of bytes that can be written in I2C to the DMA */
-#define ST_TP_DMA_CHUNK_SIZE		32
+#define ST_TP_DMA_CHUNK_SIZE 32
 
-#define ST_HOST_BUFFER_DATA_VALID	BIT(0)
-#define ST_HOST_BUFFER_MT_READY		BIT(3)
-#define ST_HOST_BUFFER_SF_READY		BIT(4)
-#define ST_HOST_BUFFER_SS_READY		BIT(5)
+#define ST_HOST_BUFFER_DATA_VALID BIT(0)
+#define ST_HOST_BUFFER_MT_READY BIT(3)
+#define ST_HOST_BUFFER_SF_READY BIT(4)
+#define ST_HOST_BUFFER_SS_READY BIT(5)
 
-#define ST_TP_SCAN_MODE_ACTIVE		0x00
-#define ST_TP_SCAN_MODE_LOW_POWER	0x01
-#define ST_TP_SCAN_MODE_TUNING_WIZARD	0x02
-#define ST_TP_SCAN_MODE_LOCKED		0x03
+#define ST_TP_SCAN_MODE_ACTIVE 0x00
+#define ST_TP_SCAN_MODE_LOW_POWER 0x01
+#define ST_TP_SCAN_MODE_TUNING_WIZARD 0x02
+#define ST_TP_SCAN_MODE_LOCKED 0x03
 
-#define ST_TOUCH_ROWS		(18)  /* force len */
-#define ST_TOUCH_COLS		(25)  /* sense len */
+#define ST_TOUCH_ROWS (18) /* force len */
+#define ST_TOUCH_COLS (25) /* sense len */
 
-#define ST_TOUCH_HEADER_SIZE	32
+#define ST_TOUCH_HEADER_SIZE 32
 
-#define BYTES_PER_PIXEL		1
+#define BYTES_PER_PIXEL 1
 /* Number of bits per pixel, this value is decided by experiments. */
-#define BITS_PER_PIXEL		8
+#define BITS_PER_PIXEL 8
 
-#define ST_TOUCH_FRAME_SIZE	(ST_TOUCH_ROWS * ST_TOUCH_COLS * \
-				 BYTES_PER_PIXEL)
-#define ST_TOUCH_FORCE_SIZE	(ST_TOUCH_ROWS * BYTES_PER_PIXEL)
-#define ST_TOUCH_SENSE_SIZE	(ST_TOUCH_COLS * BYTES_PER_PIXEL)
+#define ST_TOUCH_FRAME_SIZE (ST_TOUCH_ROWS * ST_TOUCH_COLS * BYTES_PER_PIXEL)
+#define ST_TOUCH_FORCE_SIZE (ST_TOUCH_ROWS * BYTES_PER_PIXEL)
+#define ST_TOUCH_SENSE_SIZE (ST_TOUCH_COLS * BYTES_PER_PIXEL)
 
-#define ST_TP_MEM_ID_SYSTEM_INFO	0x01
-
-#define ST_TP_FLASH_OFFSET_CODE		(0x0000 << 2)
-#define ST_TP_FLASH_OFFSET_PANEL_CFG	(0x6800 << 2)
-#define ST_TP_FLASH_OFFSET_CX		(0x7000 << 2)
-#define ST_TP_FLASH_OFFSET_CONFIG	(0x7C00 << 2)
+#define ST_TP_MEM_ID_SYSTEM_INFO 0x01
 
+#define ST_TP_FLASH_OFFSET_CODE (0x0000 << 2)
+#define ST_TP_FLASH_OFFSET_PANEL_CFG (0x6800 << 2)
+#define ST_TP_FLASH_OFFSET_CX (0x7000 << 2)
+#define ST_TP_FLASH_OFFSET_CONFIG (0x7C00 << 2)
 
 struct st_tp_host_data_header_t {
-#define ST_TP_HEADER_MAGIC	0xA5
-	uint8_t magic;  /* this should always be ST_TP_HEADER_MAGIC */
+#define ST_TP_HEADER_MAGIC 0xA5
+	uint8_t magic; /* this should always be ST_TP_HEADER_MAGIC */
 	uint8_t host_data_mem_id;
 	uint16_t count;
 } __packed;
 
 /* Compute offset of end of a member in given type */
-#define endof(type, member) (offsetof(type, member) + \
-			     sizeof(((type *)NULL)->member))
+#define endof(type, member) \
+	(offsetof(type, member) + sizeof(((type *)NULL)->member))
 
 struct st_tp_system_info_t {
 	/* Part 1, basic info */
@@ -83,7 +81,7 @@ struct st_tp_system_info_t {
 	uint8_t api_ver_minor;
 	uint8_t api_ver_major;
 	uint16_t chip0_ver;
-	uint8_t chip0_id[2];  /* should be 0x3936 */
+	uint8_t chip0_id[2]; /* should be 0x3936 */
 	uint16_t chip1_ver;
 	uint16_t chip1_id;
 	uint16_t fw_ver;
@@ -101,7 +99,7 @@ struct st_tp_system_info_t {
 	uint32_t fw_crc;
 	uint32_t cfg_crc;
 #define ST_TP_SYSTEM_INFO_PART_1_SIZE endof(struct st_tp_system_info_t, cfg_crc)
-#define ST_TP_SYSTEM_INFO_PART_1_RESERVED	16
+#define ST_TP_SYSTEM_INFO_PART_1_RESERVED 16
 
 	uint16_t scr_res_x;
 	uint16_t scr_res_y;
@@ -109,20 +107,18 @@ struct st_tp_system_info_t {
 	uint8_t scr_rx_len;
 	uint8_t key_len;
 	uint8_t frc_len;
-#define ST_TP_SYSTEM_INFO_PART_2_SIZE (endof(struct st_tp_system_info_t, \
-					     frc_len) - \
-				       offsetof(struct st_tp_system_info_t, \
-						scr_res_x))
-#define ST_TP_SYSTEM_INFO_PART_2_RESERVED	40
+#define ST_TP_SYSTEM_INFO_PART_2_SIZE                 \
+	(endof(struct st_tp_system_info_t, frc_len) - \
+	 offsetof(struct st_tp_system_info_t, scr_res_x))
+#define ST_TP_SYSTEM_INFO_PART_2_RESERVED 40
 
-#if 0  /* the following parts are defined in spec, but not currently used. */
+#if 0 /* the following parts are defined in spec, but not currently used. */
 
 	uint16_t dbg_frame_addr;
-#define ST_TP_SYSTEM_INFO_PART_3_SIZE (endof(struct st_tp_system_info_t, \
-					     dbg_frame_addr) - \
-				       offsetof(struct st_tp_system_info_t, \
-						dbg_frame_addr))
-#define ST_TP_SYSTEM_INFO_PART_3_RESERVED	6
+#define ST_TP_SYSTEM_INFO_PART_3_SIZE                        \
+	(endof(struct st_tp_system_info_t, dbg_frame_addr) - \
+	 offsetof(struct st_tp_system_info_t, dbg_frame_addr))
+#define ST_TP_SYSTEM_INFO_PART_3_RESERVED 6
 
 	uint16_t ms_scr_raw_addr;
 	uint16_t ms_scr_filter_addr;
@@ -160,24 +156,23 @@ struct st_tp_system_info_t {
 	uint16_t ss_prx_rx_filter_addr;
 	uint16_t ss_prx_rx_str_addr;
 	uint16_t ss_prx_rx_bl_addr;
-#define ST_TP_SYSTEM_INFO_PART_4_SIZE (endof(struct st_tp_system_info_t, \
-					     ss_prx_rx_bl_addr) - \
-				       offsetof(struct st_tp_system_info_t, \
-						ms_scr_raw_addr))
-#endif  /* if 0 */
+#define ST_TP_SYSTEM_INFO_PART_4_SIZE                           \
+	(endof(struct st_tp_system_info_t, ss_prx_rx_bl_addr) - \
+	 offsetof(struct st_tp_system_info_t, ms_scr_raw_addr))
+#endif /* if 0 */
 } __packed;
 
-#define ST_TP_SYSTEM_INFO_LEN	(sizeof(struct st_tp_system_info_t) + \
-				 ST_TP_SYSTEM_INFO_PART_1_RESERVED)
+#define ST_TP_SYSTEM_INFO_LEN \
+	(sizeof(struct st_tp_system_info_t) + ST_TP_SYSTEM_INFO_PART_1_RESERVED)
 
 struct st_tp_host_buffer_header_t {
-#define ST_TP_BUFFER_HEADER_DATA_VALID		BIT(0)
-#define ST_TP_BUFFER_HEADER_EVT_FIFO_NOT_EMPTY	BIT(1)
-#define ST_TP_BUFFER_HEADER_SYS_FAULT		BIT(2)
-#define ST_TP_BUFFER_HEADER_HEAT_MAP_MT_RDY	BIT(3)
-#define ST_TP_BUFFER_HEADER_HEAT_MAP_SF_RDY	BIT(4)
-#define ST_TP_BUFFER_HEADER_HEAT_MAP_SS_RDY	BIT(5)
-#define ST_TP_BUFFER_HEADER_DOMESWITCH_LVL	BIT(6)
+#define ST_TP_BUFFER_HEADER_DATA_VALID BIT(0)
+#define ST_TP_BUFFER_HEADER_EVT_FIFO_NOT_EMPTY BIT(1)
+#define ST_TP_BUFFER_HEADER_SYS_FAULT BIT(2)
+#define ST_TP_BUFFER_HEADER_HEAT_MAP_MT_RDY BIT(3)
+#define ST_TP_BUFFER_HEADER_HEAT_MAP_SF_RDY BIT(4)
+#define ST_TP_BUFFER_HEADER_HEAT_MAP_SS_RDY BIT(5)
+#define ST_TP_BUFFER_HEADER_DOMESWITCH_LVL BIT(6)
 	uint8_t flags;
 	uint8_t reserved[3];
 	uint8_t heatmap_miss_count;
@@ -187,56 +182,56 @@ struct st_tp_host_buffer_header_t {
 
 struct st_tp_host_buffer_heat_map_t {
 	uint8_t frame[ST_TOUCH_FRAME_SIZE];
-#if 0  /* we are not using these now */
+#if 0 /* we are not using these now */
 	uint8_t force[ST_TOUCH_FORCE_SIZE];
 	uint8_t sense[ST_TOUCH_SENSE_SIZE];
 #endif
 } __packed;
 
 struct st_tp_event_t {
-#define ST_TP_EVENT_MAGIC		0x3
-	unsigned magic:2;  /* should always be 0x3 */
-	unsigned major_high:2;
-#define ST_TP_EVENT_ID_CONTROLLER_READY	0x0
-#define ST_TP_EVENT_ID_ENTER_POINTER	0x1
-#define ST_TP_EVENT_ID_MOTION_POINTER	0x2
-#define ST_TP_EVENT_ID_LEAVE_POINTER	0x3
-#define ST_TP_EVENT_ID_STATUS_REPORT	0x4
-#define ST_TP_EVENT_ID_USER_REPORT	0x5
-#define ST_TP_EVENT_ID_DEBUG_REPORT	0xe
-#define ST_TP_EVENT_ID_ERROR_REPORT	0xf
-	unsigned evt_id:4;
+#define ST_TP_EVENT_MAGIC 0x3
+	unsigned magic : 2; /* should always be 0x3 */
+	unsigned major_high : 2;
+#define ST_TP_EVENT_ID_CONTROLLER_READY 0x0
+#define ST_TP_EVENT_ID_ENTER_POINTER 0x1
+#define ST_TP_EVENT_ID_MOTION_POINTER 0x2
+#define ST_TP_EVENT_ID_LEAVE_POINTER 0x3
+#define ST_TP_EVENT_ID_STATUS_REPORT 0x4
+#define ST_TP_EVENT_ID_USER_REPORT 0x5
+#define ST_TP_EVENT_ID_DEBUG_REPORT 0xe
+#define ST_TP_EVENT_ID_ERROR_REPORT 0xf
+	unsigned evt_id : 4;
 
 	union {
 		struct {
-#define ST_TP_TOUCH_TYPE_INVALID	0x0
-#define ST_TP_TOUCH_TYPE_FINGER		0x1
-#define ST_TP_TOUCH_TYPE_GLOVE		0x2
-#define ST_TP_TOUCH_TYPE_STYLUS		0x3
-#define ST_TP_TOUCH_TYPE_PALM		0x4
-			unsigned touch_type:4;
-			unsigned touch_id:4;
-			unsigned y:12;
-			unsigned x:12;
+#define ST_TP_TOUCH_TYPE_INVALID 0x0
+#define ST_TP_TOUCH_TYPE_FINGER 0x1
+#define ST_TP_TOUCH_TYPE_GLOVE 0x2
+#define ST_TP_TOUCH_TYPE_STYLUS 0x3
+#define ST_TP_TOUCH_TYPE_PALM 0x4
+			unsigned touch_type : 4;
+			unsigned touch_id : 4;
+			unsigned y : 12;
+			unsigned x : 12;
 			uint8_t z;
-			uint8_t minor:4;  // need to be concat with minor_high
-			uint8_t major:4;  // need to be concat with major_high
+			uint8_t minor : 4; // need to be concat with minor_high
+			uint8_t major : 4; // need to be concat with major_high
 		} __packed finger;
 
 		struct {
-#define ST_TP_STATUS_CMD_ECHO	0x1
-#define ST_TP_STATUS_FRAME_DROP	0x3
-#define ST_TP_STATUS_FCAL	0x5
-#define ST_TP_STATUS_BEACON	0x9
+#define ST_TP_STATUS_CMD_ECHO 0x1
+#define ST_TP_STATUS_FRAME_DROP 0x3
+#define ST_TP_STATUS_FCAL 0x5
+#define ST_TP_STATUS_BEACON 0x9
 			uint8_t report_type;
 			uint8_t info[4];
 			uint8_t reserved;
 		} __packed report;
-	} __packed ; /* anonymous */
+	} __packed; /* anonymous */
 
-	unsigned minor_high:2;
-	unsigned reserved:1;
-	unsigned evt_left:5;
+	unsigned minor_high : 2;
+	unsigned reserved : 1;
+	unsigned evt_left : 5;
 } __packed;
 
 struct st_tp_fw_header_t {
@@ -258,12 +253,12 @@ enum ST_TP_MODE {
 	HEAT_MAP_MODE,
 };
 
-#define ST_TP_DEBUG_CMD_RESET_TOUCHPAD		0x00
-#define ST_TP_DEBUG_CMD_CALIBRATE		0x01
-#define ST_TP_DEBUG_CMD_START_SCAN		0x02
-#define ST_TP_DEBUG_CMD_STOP_SCAN		0x03
-#define ST_TP_DEBUG_CMD_READ_BUF_HEADER		0x04
-#define ST_TP_DEBUG_CMD_READ_EVENTS		0x05
+#define ST_TP_DEBUG_CMD_RESET_TOUCHPAD 0x00
+#define ST_TP_DEBUG_CMD_CALIBRATE 0x01
+#define ST_TP_DEBUG_CMD_START_SCAN 0x02
+#define ST_TP_DEBUG_CMD_STOP_SCAN 0x03
+#define ST_TP_DEBUG_CMD_READ_BUF_HEADER 0x04
+#define ST_TP_DEBUG_CMD_READ_EVENTS 0x05
 
 #define ST_TP_HEAT_MAP_THRESHOLD 10
 
diff --git a/driver/usb_mux/amd_fp5.c b/driver/usb_mux/amd_fp5.c
index c32e6992c2..ca042b0fa0 100644
--- a/driver/usb_mux/amd_fp5.c
+++ b/driver/usb_mux/amd_fp5.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -22,8 +22,7 @@ static inline int amd_fp5_mux_read(const struct usb_mux *me, uint8_t *val)
 	uint8_t buf[3] = { 0 };
 	int rv;
 
-	rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags,
-		      NULL, 0, buf, 3);
+	rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags, NULL, 0, buf, 3);
 	if (rv)
 		return rv;
 
@@ -34,8 +33,7 @@ static inline int amd_fp5_mux_read(const struct usb_mux *me, uint8_t *val)
 
 static inline int amd_fp5_mux_write(const struct usb_mux *me, uint8_t val)
 {
-	return i2c_write8(me->i2c_port, me->i2c_addr_flags,
-			  me->usb_port, val);
+	return i2c_write8(me->i2c_port, me->i2c_addr_flags, me->usb_port, val);
 }
 
 static int amd_fp5_init(const struct usb_mux *me)
@@ -51,6 +49,10 @@ static int amd_fp5_set_mux(const struct usb_mux *me, mux_state_t mux_state,
 	/* This driver does not use host command ACKs */
 	*ack_required = false;
 
+	/* This driver treats safe mode as none */
+	if (mux_state == USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
+
 	saved_mux_state[me->usb_port] = mux_state;
 
 	/*
@@ -60,20 +62,22 @@ static int amd_fp5_set_mux(const struct usb_mux *me, mux_state_t mux_state,
 	 * it because a powered down MUX is off.
 	 */
 	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
-		return (mux_state == USB_PD_MUX_NONE)
-			? EC_SUCCESS
-			: EC_ERROR_NOT_POWERED;
+		return (mux_state == USB_PD_MUX_NONE) ? EC_SUCCESS :
+							EC_ERROR_NOT_POWERED;
 
 	if ((mux_state & USB_PD_MUX_USB_ENABLED) &&
-		(mux_state & USB_PD_MUX_DP_ENABLED))
-		val = (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-			? AMD_FP5_MUX_DOCK_INVERTED : AMD_FP5_MUX_DOCK;
+	    (mux_state & USB_PD_MUX_DP_ENABLED))
+		val = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ?
+			      AMD_FP5_MUX_DOCK_INVERTED :
+			      AMD_FP5_MUX_DOCK;
 	else if (mux_state & USB_PD_MUX_USB_ENABLED)
-		val = (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-			? AMD_FP5_MUX_USB_INVERTED : AMD_FP5_MUX_USB;
+		val = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ?
+			      AMD_FP5_MUX_USB_INVERTED :
+			      AMD_FP5_MUX_USB;
 	else if (mux_state & USB_PD_MUX_DP_ENABLED)
-		val = (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-			? AMD_FP5_MUX_DP_INVERTED : AMD_FP5_MUX_DP;
+		val = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ?
+			      AMD_FP5_MUX_DP_INVERTED :
+			      AMD_FP5_MUX_DP;
 
 	return amd_fp5_mux_write(me, val);
 }
@@ -101,21 +105,21 @@ static int amd_fp5_get_mux(const struct usb_mux *me, mux_state_t *mux_state)
 		break;
 	case AMD_FP5_MUX_USB_INVERTED:
 		*mux_state = USB_PD_MUX_USB_ENABLED |
-				USB_PD_MUX_POLARITY_INVERTED;
+			     USB_PD_MUX_POLARITY_INVERTED;
 		break;
 	case AMD_FP5_MUX_DOCK:
 		*mux_state = USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED;
 		break;
 	case AMD_FP5_MUX_DOCK_INVERTED:
-		*mux_state = USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED
-			     | USB_PD_MUX_POLARITY_INVERTED;
+		*mux_state = USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED |
+			     USB_PD_MUX_POLARITY_INVERTED;
 		break;
 	case AMD_FP5_MUX_DP:
 		*mux_state = USB_PD_MUX_DP_ENABLED;
 		break;
 	case AMD_FP5_MUX_DP_INVERTED:
 		*mux_state = USB_PD_MUX_DP_ENABLED |
-				USB_PD_MUX_POLARITY_INVERTED;
+			     USB_PD_MUX_POLARITY_INVERTED;
 		break;
 	case AMD_FP5_MUX_SAFE:
 	default:
@@ -126,8 +130,8 @@ static int amd_fp5_get_mux(const struct usb_mux *me, mux_state_t *mux_state)
 	return EC_SUCCESS;
 }
 
-static struct queue const chipset_reset_queue
-	= QUEUE_NULL(CONFIG_USB_PD_PORT_MAX_COUNT, struct usb_mux *);
+static struct queue const chipset_reset_queue =
+	QUEUE_NULL(CONFIG_USB_PD_PORT_MAX_COUNT, struct usb_mux *);
 
 static void amd_fp5_chipset_reset_delay(void)
 {
diff --git a/driver/usb_mux/amd_fp5.h b/driver/usb_mux/amd_fp5.h
index 7534ea0d8a..9a23cf57b0 100644
--- a/driver/usb_mux/amd_fp5.h
+++ b/driver/usb_mux/amd_fp5.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,14 +8,14 @@
 #ifndef __CROS_EC_USB_MUX_AMD_FP5_H
 #define __CROS_EC_USB_MUX_AMD_FP5_H
 
-#define AMD_FP5_MUX_I2C_ADDR_FLAGS	0x5C
+#define AMD_FP5_MUX_I2C_ADDR_FLAGS 0x5C
 
-#define AMD_FP5_MUX_SAFE		0x00
-#define AMD_FP5_MUX_USB			0x02
-#define AMD_FP5_MUX_USB_INVERTED	0x11
-#define AMD_FP5_MUX_DOCK		0x06
-#define AMD_FP5_MUX_DOCK_INVERTED	0x19
-#define AMD_FP5_MUX_DP			0x0C
-#define AMD_FP5_MUX_DP_INVERTED		0x1C
+#define AMD_FP5_MUX_SAFE 0x00
+#define AMD_FP5_MUX_USB 0x02
+#define AMD_FP5_MUX_USB_INVERTED 0x11
+#define AMD_FP5_MUX_DOCK 0x06
+#define AMD_FP5_MUX_DOCK_INVERTED 0x19
+#define AMD_FP5_MUX_DP 0x0C
+#define AMD_FP5_MUX_DP_INVERTED 0x1C
 
 #endif /* __CROS_EC_USB_MUX_AMD_FP5_H */
diff --git a/driver/usb_mux/amd_fp6.c b/driver/usb_mux/amd_fp6.c
index 4f31fae186..a776a696f7 100644
--- a/driver/usb_mux/amd_fp6.c
+++ b/driver/usb_mux/amd_fp6.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -15,8 +15,8 @@
 #include "timer.h"
 #include "usb_mux.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /*
  * The recommendation from "3.3.2 Command Timeout" is 250ms,
@@ -50,8 +50,8 @@ static int amd_fp6_mux_port0_read(const struct usb_mux *me, uint8_t *val)
 	 * payload[1]: Port 0 Control/Status
 	 * payload[2]: Port 1 Control/Status (unused on FP6)
 	 */
-	mux_ready = !!((payload[0] >> AMD_FP6_MUX_PD_STATUS_OFFSET)
-						& AMD_FP6_MUX_PD_STATUS_READY);
+	mux_ready = !!((payload[0] >> AMD_FP6_MUX_PD_STATUS_OFFSET) &
+		       AMD_FP6_MUX_PD_STATUS_READY);
 
 	if (!mux_ready)
 		return EC_ERROR_BUSY;
@@ -80,7 +80,6 @@ static int amd_fp6_mux_port0_write(const struct usb_mux *me, uint8_t write_val)
 	 */
 	start = get_time();
 	while (time_since32(start) < WRITE_CMD_TIMEOUT_MS * MSEC) {
-
 		RETURN_ERROR(amd_fp6_mux_port0_read(me, &read_val));
 		port_status = read_val >> AMD_FP6_MUX_PORT_STATUS_OFFSET;
 
@@ -134,7 +133,6 @@ static void amd_fp6_set_mux_retry(void)
 				   CMD_RETRY_INTERVAL_MS * MSEC);
 }
 
-
 static int amd_fp6_set_mux(const struct usb_mux *me, mux_state_t mux_state,
 			   bool *ack_required)
 {
@@ -143,6 +141,10 @@ static int amd_fp6_set_mux(const struct usb_mux *me, mux_state_t mux_state,
 	/* This driver does not use host command ACKs */
 	*ack_required = false;
 
+	/* This driver treats safe mode as none */
+	if (mux_state == USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
+
 	if (mux_state == USB_PD_MUX_NONE)
 		/*
 		 * LOW_POWER must be set when connection mode is
@@ -170,8 +172,8 @@ static int amd_fp6_set_mux(const struct usb_mux *me, mux_state_t mux_state,
 
 	/* Mux is not powered in Z1 */
 	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
-		return (mux_state == USB_PD_MUX_NONE) ? EC_SUCCESS
-						      : EC_ERROR_NOT_POWERED;
+		return (mux_state == USB_PD_MUX_NONE) ? EC_SUCCESS :
+							EC_ERROR_NOT_POWERED;
 
 	saved_mux_state[me->usb_port].write_pending = true;
 	amd_fp6_set_mux_retry();
diff --git a/driver/usb_mux/amd_fp6.h b/driver/usb_mux/amd_fp6.h
index 913903e4c4..ba2b791ba5 100644
--- a/driver/usb_mux/amd_fp6.h
+++ b/driver/usb_mux/amd_fp6.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,24 +8,24 @@
 #ifndef __CROS_EC_USB_MUX_AMD_FP6_H
 #define __CROS_EC_USB_MUX_AMD_FP6_H
 
-#define AMD_FP6_C0_MUX_I2C_ADDR		0x5C
-#define AMD_FP6_C4_MUX_I2C_ADDR		0x52
+#define AMD_FP6_C0_MUX_I2C_ADDR 0x5C
+#define AMD_FP6_C4_MUX_I2C_ADDR 0x52
 
-#define AMD_FP6_MUX_MODE_SAFE		0x0
-#define AMD_FP6_MUX_MODE_USB		0x1
-#define AMD_FP6_MUX_MODE_DP		0x2
-#define AMD_FP6_MUX_MODE_DOCK		0x3
-#define AMD_FP6_MUX_MODE_MASK		GENMASK(1, 0)
+#define AMD_FP6_MUX_MODE_SAFE 0x0
+#define AMD_FP6_MUX_MODE_USB 0x1
+#define AMD_FP6_MUX_MODE_DP 0x2
+#define AMD_FP6_MUX_MODE_DOCK 0x3
+#define AMD_FP6_MUX_MODE_MASK GENMASK(1, 0)
 
-#define AMD_FP6_MUX_ORIENTATION		BIT(4)
-#define AMD_FP6_MUX_LOW_POWER		BIT(5)
+#define AMD_FP6_MUX_ORIENTATION BIT(4)
+#define AMD_FP6_MUX_LOW_POWER BIT(5)
 
-#define AMD_FP6_MUX_PORT_STATUS_OFFSET	6
-#define AMD_FP6_MUX_PORT_CMD_BUSY	0x0
-#define AMD_FP6_MUX_PORT_CMD_COMPLETE	0x1
-#define AMD_FP6_MUX_PORT_CMD_TIMEOUT	0x2
+#define AMD_FP6_MUX_PORT_STATUS_OFFSET 6
+#define AMD_FP6_MUX_PORT_CMD_BUSY 0x0
+#define AMD_FP6_MUX_PORT_CMD_COMPLETE 0x1
+#define AMD_FP6_MUX_PORT_CMD_TIMEOUT 0x2
 
-#define AMD_FP6_MUX_PD_STATUS_READY	BIT(5)
-#define AMD_FP6_MUX_PD_STATUS_OFFSET	1
+#define AMD_FP6_MUX_PD_STATUS_READY BIT(5)
+#define AMD_FP6_MUX_PD_STATUS_OFFSET 1
 
 #endif /* __CROS_EC_USB_MUX_AMD_FP6_H */
diff --git a/driver/usb_mux/anx3443.c b/driver/usb_mux/anx3443.c
index c7158b645c..f3b0b08afd 100644
--- a/driver/usb_mux/anx3443.c
+++ b/driver/usb_mux/anx3443.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -23,22 +23,21 @@
 #define ANX3443_I2C_WAKE_TIMEOUT_MS 20
 #define ANX3443_I2C_WAKE_RETRY_DELAY_US 500
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static struct {
 	mux_state_t mux_state;
 	bool awake;
 } saved_mux_state[CONFIG_USB_PD_PORT_MAX_COUNT];
 
-static inline int anx3443_read(const struct usb_mux *me,
-			       uint8_t reg, int *val)
+static inline int anx3443_read(const struct usb_mux *me, uint8_t reg, int *val)
 {
 	return i2c_read8(me->i2c_port, me->i2c_addr_flags, reg, val);
 }
 
-static inline int anx3443_write(const struct usb_mux *me,
-				uint8_t reg, uint8_t val)
+static inline int anx3443_write(const struct usb_mux *me, uint8_t reg,
+				uint8_t val)
 {
 	return i2c_write8(me->i2c_port, me->i2c_addr_flags, reg, val);
 }
@@ -97,6 +96,10 @@ static int anx3443_set_mux(const struct usb_mux *me, mux_state_t mux_state,
 	/* This driver does not use host command ACKs */
 	*ack_required = false;
 
+	/* This driver treats safe mode as none */
+	if (mux_state == USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
+
 	saved_mux_state[me->usb_port].mux_state = mux_state;
 
 	/* To disable both DP and USB the mux must be powered off. */
@@ -195,7 +198,7 @@ static bool anx3443_port_is_usb2_only(const struct usb_mux *me)
 static void anx3443_suspend(void)
 {
 	for (int i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		const struct usb_mux *mux = &usb_muxes[i];
+		const struct usb_mux *mux = usb_muxes[i].mux;
 
 		if (mux->driver != &anx3443_usb_mux_driver)
 			continue;
@@ -209,14 +212,14 @@ DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, anx3443_suspend, HOOK_PRIO_DEFAULT);
 static void anx3443_resume(void)
 {
 	for (int i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		int port = usb_muxes[i].usb_port;
+		int port = usb_muxes[i].mux->usb_port;
 		bool ack_required;
 
-		if (usb_muxes[i].driver != &anx3443_usb_mux_driver)
+		if (usb_muxes[i].mux->driver != &anx3443_usb_mux_driver)
 			continue;
 
-		anx3443_set_mux(&usb_muxes[i], saved_mux_state[port].mux_state,
-				&ack_required);
+		anx3443_set_mux(usb_muxes[i].mux,
+				saved_mux_state[port].mux_state, &ack_required);
 	}
 }
 DECLARE_HOOK(HOOK_CHIPSET_RESUME, anx3443_resume, HOOK_PRIO_DEFAULT);
diff --git a/driver/usb_mux/anx3443.h b/driver/usb_mux/anx3443.h
index a8e84d5e5e..bd2dc2bf45 100644
--- a/driver/usb_mux/anx3443.h
+++ b/driver/usb_mux/anx3443.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -9,36 +9,36 @@
 #ifndef __CROS_EC_USB_MUX_ANX3443_H
 #define __CROS_EC_USB_MUX_ANX3443_H
 
-#define ANX3443_I2C_READY_DELAY		(30 * MSEC)
+#define ANX3443_I2C_READY_DELAY (30 * MSEC)
 
 /* I2C interface addresses */
-#define ANX3443_I2C_ADDR0_FLAGS		0x10
-#define ANX3443_I2C_ADDR1_FLAGS		0x14
-#define ANX3443_I2C_ADDR2_FLAGS		0x16
-#define ANX3443_I2C_ADDR3_FLAGS		0x11
+#define ANX3443_I2C_ADDR0_FLAGS 0x10
+#define ANX3443_I2C_ADDR1_FLAGS 0x14
+#define ANX3443_I2C_ADDR2_FLAGS 0x16
+#define ANX3443_I2C_ADDR3_FLAGS 0x11
 
 /* This register is not documented in datasheet. */
-#define ANX3443_REG_POWER_CNTRL		0x2B
-#define ANX3443_POWER_CNTRL_OFF		0xFF
+#define ANX3443_REG_POWER_CNTRL 0x2B
+#define ANX3443_POWER_CNTRL_OFF 0xFF
 
-#define ANX3443_REG_USB_STATUS		0xD7
+#define ANX3443_REG_USB_STATUS 0xD7
 /* status of downstream RX term */
-#define ANX3443_DN_EN_RTERM_ST		BIT(7)
+#define ANX3443_DN_EN_RTERM_ST BIT(7)
 /* status of upstream RX term */
-#define ANX3443_UP_EN_RTERM_ST		BIT(6)
+#define ANX3443_UP_EN_RTERM_ST BIT(6)
 
 /* Ultra low power control register  */
-#define ANX3443_REG_ULTRA_LOW_POWER	0xE6
-#define ANX3443_ULTRA_LOW_POWER_EN	0x06
-#define ANX3443_ULTRA_LOW_POWER_DIS	0x00
+#define ANX3443_REG_ULTRA_LOW_POWER 0xE6
+#define ANX3443_ULTRA_LOW_POWER_EN 0x06
+#define ANX3443_ULTRA_LOW_POWER_DIS 0x00
 
 /* Mux control register  */
-#define ANX3443_REG_ULP_CFG_MODE	0xF8
-#define ANX3443_ULP_CFG_MODE_EN		BIT(4)
-#define ANX3443_ULP_CFG_MODE_SWAP	BIT(3)
-#define ANX3443_ULP_CFG_MODE_FLIP	BIT(2)
-#define ANX3443_ULP_CFG_MODE_DP_EN	BIT(1)
-#define ANX3443_ULP_CFG_MODE_USB_EN	BIT(0)
+#define ANX3443_REG_ULP_CFG_MODE 0xF8
+#define ANX3443_ULP_CFG_MODE_EN BIT(4)
+#define ANX3443_ULP_CFG_MODE_SWAP BIT(3)
+#define ANX3443_ULP_CFG_MODE_FLIP BIT(2)
+#define ANX3443_ULP_CFG_MODE_DP_EN BIT(1)
+#define ANX3443_ULP_CFG_MODE_USB_EN BIT(0)
 
 extern const struct usb_mux_driver anx3443_usb_mux_driver;
 
diff --git a/driver/usb_mux/anx7440.c b/driver/usb_mux/anx7440.c
index 89e593217d..456eaaa407 100644
--- a/driver/usb_mux/anx7440.c
+++ b/driver/usb_mux/anx7440.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -13,17 +13,16 @@
 #include "usb_mux.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-static inline int anx7440_read(const struct usb_mux *me,
-			       uint8_t reg, int *val)
+static inline int anx7440_read(const struct usb_mux *me, uint8_t reg, int *val)
 {
 	return i2c_read8(me->i2c_port, me->i2c_addr_flags, reg, val);
 }
 
-static inline int anx7440_write(const struct usb_mux *me,
-				uint8_t reg, uint8_t val)
+static inline int anx7440_write(const struct usb_mux *me, uint8_t reg,
+				uint8_t val)
 {
 	return i2c_write8(me->i2c_port, me->i2c_addr_flags, reg, val);
 }
@@ -69,6 +68,10 @@ static int anx7440_set_mux(const struct usb_mux *me, mux_state_t mux_state,
 	/* This driver does not use host command ACKs */
 	*ack_required = false;
 
+	/* This driver treats safe mode as none */
+	if (mux_state == USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
+
 	res = anx7440_read(me, ANX7440_REG_CHIP_CTRL, &reg);
 	if (res)
 		return res;
diff --git a/driver/usb_mux/anx7440.h b/driver/usb_mux/anx7440.h
index 2147e3146a..3849837cd2 100644
--- a/driver/usb_mux/anx7440.h
+++ b/driver/usb_mux/anx7440.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -16,25 +16,25 @@
 #define I2C_ADDR_USB_MUX1_FLAGS ANX7440_I2C_ADDR2_FLAGS
 
 /* Vendor / Device Id registers and expected fused values */
-#define ANX7440_REG_VENDOR_ID_L    0x00
-#define ANX7440_VENDOR_ID_L        0xaa
-#define ANX7440_REG_VENDOR_ID_H    0x01
-#define ANX7440_VENDOR_ID_H        0xaa
-#define ANX7440_REG_DEVICE_ID_L    0x02
-#define ANX7440_DEVICE_ID_L        0x40
-#define ANX7440_REG_DEVICE_ID_H    0x03
-#define ANX7440_DEVICE_ID_H        0x74
+#define ANX7440_REG_VENDOR_ID_L 0x00
+#define ANX7440_VENDOR_ID_L 0xaa
+#define ANX7440_REG_VENDOR_ID_H 0x01
+#define ANX7440_VENDOR_ID_H 0xaa
+#define ANX7440_REG_DEVICE_ID_L 0x02
+#define ANX7440_DEVICE_ID_L 0x40
+#define ANX7440_REG_DEVICE_ID_H 0x03
+#define ANX7440_DEVICE_ID_H 0x74
 #define ANX7440_REG_DEVICE_VERSION 0x04
-#define ANX7440_DEVICE_VERSION     0xCB
+#define ANX7440_DEVICE_VERSION 0xCB
 
 /* Chip control register for checking mux state */
-#define ANX7440_REG_CHIP_CTRL               0x05
-#define ANX7440_CHIP_CTRL_FINAL_FLIP        BIT(6)
-#define ANX7440_CHIP_CTRL_OP_MODE_FINAL_DP  BIT(5)
+#define ANX7440_REG_CHIP_CTRL 0x05
+#define ANX7440_CHIP_CTRL_FINAL_FLIP BIT(6)
+#define ANX7440_CHIP_CTRL_OP_MODE_FINAL_DP BIT(5)
 #define ANX7440_CHIP_CTRL_OP_MODE_FINAL_USB BIT(4)
-#define ANX7440_CHIP_CTRL_SW_FLIP           BIT(2)
-#define ANX7440_CHIP_CTRL_SW_OP_MODE_DP     BIT(1)
-#define ANX7440_CHIP_CTRL_SW_OP_MODE_USB    BIT(0)
-#define ANX7440_CHIP_CTRL_SW_OP_MODE_CLEAR  0x7
+#define ANX7440_CHIP_CTRL_SW_FLIP BIT(2)
+#define ANX7440_CHIP_CTRL_SW_OP_MODE_DP BIT(1)
+#define ANX7440_CHIP_CTRL_SW_OP_MODE_USB BIT(0)
+#define ANX7440_CHIP_CTRL_SW_OP_MODE_CLEAR 0x7
 
 #endif /* __CROS_EC_USB_MUX_ANX7440_H */
diff --git a/driver/usb_mux/anx7451.c b/driver/usb_mux/anx7451.c
index db56457bb8..b974128740 100644
--- a/driver/usb_mux/anx7451.c
+++ b/driver/usb_mux/anx7451.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -22,17 +22,16 @@
 #define ANX7451_I2C_WAKE_TIMEOUT_MS 20
 #define ANX7451_I2C_WAKE_RETRY_DELAY_US 500
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
-static inline int anx7451_read(const struct usb_mux *me,
-			       uint8_t reg, int *val)
+static inline int anx7451_read(const struct usb_mux *me, uint8_t reg, int *val)
 {
 	return i2c_read8(me->i2c_port, me->i2c_addr_flags, reg, val);
 }
 
-static inline int anx7451_write(const struct usb_mux *me,
-				uint8_t reg, uint8_t val)
+static inline int anx7451_write(const struct usb_mux *me, uint8_t reg,
+				uint8_t val)
 {
 	return i2c_write8(me->i2c_port, me->i2c_addr_flags, reg, val);
 }
@@ -97,6 +96,10 @@ static int anx7451_set_mux(const struct usb_mux *me, mux_state_t mux_state,
 	/* This driver does not use host command ACKs */
 	*ack_required = false;
 
+	/* This driver treats safe mode as none */
+	if (mux_state == USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
+
 	/*
 	 * Mux is not powered in Z1, and will start up in USB mode.  Ensure any
 	 * mux sets when off get run again so we don't leave the retimer on with
diff --git a/driver/usb_mux/anx7451.h b/driver/usb_mux/anx7451.h
index 7eefb6e79e..4b63d513fd 100644
--- a/driver/usb_mux/anx7451.h
+++ b/driver/usb_mux/anx7451.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -12,38 +12,38 @@
 #include "usb_mux.h"
 
 /* I2C interface addresses */
-#define ANX7451_I2C_ADDR0_FLAGS		0x10
-#define ANX7451_I2C_ADDR1_FLAGS		0x14
-#define ANX7451_I2C_ADDR2_FLAGS		0x16
-#define ANX7451_I2C_ADDR3_FLAGS		0x11
+#define ANX7451_I2C_ADDR0_FLAGS 0x10
+#define ANX7451_I2C_ADDR1_FLAGS 0x14
+#define ANX7451_I2C_ADDR2_FLAGS 0x16
+#define ANX7451_I2C_ADDR3_FLAGS 0x11
 
 /* This register is not documented in datasheet. */
-#define ANX7451_REG_POWER_CNTRL		0x2B
-#define ANX7451_POWER_CNTRL_OFF		0xFF
+#define ANX7451_REG_POWER_CNTRL 0x2B
+#define ANX7451_POWER_CNTRL_OFF 0xFF
 
 /*
  * Ultra low power control register.
  * On ANX7451, this register should always be 0 (disabled).
  * See figure 2-2 in family programming guide.
  */
-#define ANX7451_REG_ULTRA_LOW_POWER	0xE6
+#define ANX7451_REG_ULTRA_LOW_POWER 0xE6
 /* #define ANX7451_ULTRA_LOW_POWER_EN	0x06 */
-#define ANX7451_ULTRA_LOW_POWER_DIS	0x00
+#define ANX7451_ULTRA_LOW_POWER_DIS 0x00
 
 /* Mux control register  */
-#define ANX7451_REG_ULP_CFG_MODE	0xF8
-#define ANX7451_ULP_CFG_MODE_EN		BIT(4)
-#define ANX7451_ULP_CFG_MODE_SWAP	BIT(3)
-#define ANX7451_ULP_CFG_MODE_FLIP	BIT(2)
-#define ANX7451_ULP_CFG_MODE_DP_EN	BIT(1)
-#define ANX7451_ULP_CFG_MODE_USB_EN	BIT(0)
+#define ANX7451_REG_ULP_CFG_MODE 0xF8
+#define ANX7451_ULP_CFG_MODE_EN BIT(4)
+#define ANX7451_ULP_CFG_MODE_SWAP BIT(3)
+#define ANX7451_ULP_CFG_MODE_FLIP BIT(2)
+#define ANX7451_ULP_CFG_MODE_DP_EN BIT(1)
+#define ANX7451_ULP_CFG_MODE_USB_EN BIT(0)
 
 /* Register to set USB I2C address, defaults to 0x29 (7-bit) */
-#define ANX7451_REG_USB_I2C_ADDR	0x38
+#define ANX7451_REG_USB_I2C_ADDR 0x38
 
 /* ANX7451 AUX FLIP control */
-#define ANX7451_REG_USB_AUX_FLIP_CTRL	0xA4
-#define ANX7451_USB_AUX_FLIP_EN		0x20
+#define ANX7451_REG_USB_AUX_FLIP_CTRL 0xA4
+#define ANX7451_USB_AUX_FLIP_EN 0x20
 
 extern const struct usb_mux_driver anx7451_usb_mux_driver;
 
diff --git a/driver/usb_mux/it5205.c b/driver/usb_mux/it5205.c
index 0cfecdeda0..de3d950c86 100644
--- a/driver/usb_mux/it5205.c
+++ b/driver/usb_mux/it5205.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -25,15 +25,15 @@ static int it5205_write(const struct usb_mux *me, uint8_t reg, uint8_t val)
 static int it5205h_sbu_update(const struct usb_mux *me, uint8_t reg,
 			      uint8_t mask, enum mask_update_action action)
 {
-	return i2c_update8(me->i2c_port, IT5205H_SBU_I2C_ADDR_FLAGS,
-			   reg, mask, action);
+	return i2c_update8(me->i2c_port, IT5205H_SBU_I2C_ADDR_FLAGS, reg, mask,
+			   action);
 }
 
 static int it5205h_sbu_field_update(const struct usb_mux *me, uint8_t reg,
 				    uint8_t field_mask, uint8_t set_value)
 {
-	return i2c_field_update8(me->i2c_port, IT5205H_SBU_I2C_ADDR_FLAGS,
-				 reg, field_mask, set_value);
+	return i2c_field_update8(me->i2c_port, IT5205H_SBU_I2C_ADDR_FLAGS, reg,
+				 field_mask, set_value);
 }
 
 struct mux_chip_id_t {
@@ -42,10 +42,10 @@ struct mux_chip_id_t {
 };
 
 static const struct mux_chip_id_t mux_chip_id_verify[] = {
-	{ '5', IT5205_REG_CHIP_ID3},
-	{ '2', IT5205_REG_CHIP_ID2},
-	{ '0', IT5205_REG_CHIP_ID1},
-	{ '5', IT5205_REG_CHIP_ID0},
+	{ '5', IT5205_REG_CHIP_ID3 },
+	{ '2', IT5205_REG_CHIP_ID2 },
+	{ '0', IT5205_REG_CHIP_ID1 },
+	{ '5', IT5205_REG_CHIP_ID0 },
 };
 
 static int it5205_init(const struct usb_mux *me)
@@ -67,16 +67,16 @@ static int it5205_init(const struct usb_mux *me)
 	}
 
 	if (IS_ENABLED(CONFIG_USB_MUX_IT5205H_SBU_OVP)) {
-		RETURN_ERROR(it5205h_sbu_field_update(me, IT5205H_REG_VSR,
-				IT5205H_VREF_SELECT_MASK,
-				IT5205H_VREF_SELECT_3_3V));
+		RETURN_ERROR(it5205h_sbu_field_update(
+			me, IT5205H_REG_VSR, IT5205H_VREF_SELECT_MASK,
+			IT5205H_VREF_SELECT_3_3V));
 
 		RETURN_ERROR(it5205h_sbu_field_update(me, IT5205H_REG_CSBUOVPSR,
-				IT5205H_OVP_SELECT_MASK,
-				IT5205H_OVP_3_68V));
+						      IT5205H_OVP_SELECT_MASK,
+						      IT5205H_OVP_3_68V));
 
-		RETURN_ERROR(it5205h_sbu_update(me, IT5205H_REG_ISR,
-				IT5205H_ISR_CSBU_MASK, MASK_CLR));
+		RETURN_ERROR(it5205h_sbu_update(
+			me, IT5205H_REG_ISR, IT5205H_ISR_CSBU_MASK, MASK_CLR));
 
 		RETURN_ERROR(it5205h_enable_csbu_switch(me, true));
 	}
@@ -86,8 +86,8 @@ static int it5205_init(const struct usb_mux *me)
 
 enum ec_error_list it5205h_enable_csbu_switch(const struct usb_mux *me, bool en)
 {
-	return it5205h_sbu_update(me, IT5205H_REG_CSBUSR,
-			IT5205H_CSBUSR_SWITCH, en ? MASK_SET : MASK_CLR);
+	return it5205h_sbu_update(me, IT5205H_REG_CSBUSR, IT5205H_CSBUSR_SWITCH,
+				  en ? MASK_SET : MASK_CLR);
 }
 
 /* Writes control register to set switch mode */
@@ -99,6 +99,10 @@ static int it5205_set_mux(const struct usb_mux *me, mux_state_t mux_state,
 	/* This driver does not use host command ACKs */
 	*ack_required = false;
 
+	/* This driver treats safe mode as none */
+	if (mux_state == USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
+
 	switch (mux_state & MUX_STATE_DP_USB_MASK) {
 	case USB_PD_MUX_USB_ENABLED:
 		reg = IT5205_USB;
diff --git a/driver/usb_mux/it5205.h b/driver/usb_mux/it5205.h
index 0fb9f009f6..6a8fc2bb24 100644
--- a/driver/usb_mux/it5205.h
+++ b/driver/usb_mux/it5205.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,18 +19,17 @@
 #define IT5205_REG_CHIP_ID0 0x7
 
 /* MUX power down register */
-#define IT5205_REG_MUXPDR        0x10
-#define IT5205_MUX_POWER_DOWN    BIT(0)
+#define IT5205_REG_MUXPDR 0x10
+#define IT5205_MUX_POWER_DOWN BIT(0)
 
 /* MUX control register */
-#define IT5205_REG_MUXCR         0x11
+#define IT5205_REG_MUXCR 0x11
 #define IT5205_POLARITY_INVERTED BIT(4)
 
-#define IT5205_DP_USB_CTRL_MASK  0x0f
-#define IT5205_DP                0x0f
-#define IT5205_DP_USB            0x03
-#define IT5205_USB               0x07
-
+#define IT5205_DP_USB_CTRL_MASK 0x0f
+#define IT5205_DP 0x0f
+#define IT5205_DP_USB 0x03
+#define IT5205_USB 0x07
 
 /* IT5205-H SBU module */
 
@@ -38,27 +37,27 @@
 #define IT5205H_SBU_I2C_ADDR_FLAGS 0x6a
 
 /* Vref Select Register */
-#define IT5205H_REG_VSR            0x10
-#define IT5205H_VREF_SELECT_MASK   0x30
-#define IT5205H_VREF_SELECT_3_3V   0x00
-#define IT5205H_VREF_SELECT_OFF    0x20
+#define IT5205H_REG_VSR 0x10
+#define IT5205H_VREF_SELECT_MASK 0x30
+#define IT5205H_VREF_SELECT_3_3V 0x00
+#define IT5205H_VREF_SELECT_OFF 0x20
 
 /* CSBU OVP Select Register */
-#define IT5205H_REG_CSBUOVPSR      0x1e
-#define IT5205H_OVP_SELECT_MASK    0x30
-#define IT5205H_OVP_3_90V          0x00
-#define IT5205H_OVP_3_68V          0x10
-#define IT5205H_OVP_3_62V          0x20
-#define IT5205H_OVP_3_57V          0x30
+#define IT5205H_REG_CSBUOVPSR 0x1e
+#define IT5205H_OVP_SELECT_MASK 0x30
+#define IT5205H_OVP_3_90V 0x00
+#define IT5205H_OVP_3_68V 0x10
+#define IT5205H_OVP_3_62V 0x20
+#define IT5205H_OVP_3_57V 0x30
 
 /* CSBU Switch Register */
-#define IT5205H_REG_CSBUSR         0x22
-#define IT5205H_CSBUSR_SWITCH      BIT(0)
+#define IT5205H_REG_CSBUSR 0x22
+#define IT5205H_CSBUSR_SWITCH BIT(0)
 
 /* Interrupt Switch Register */
-#define IT5205H_REG_ISR            0x25
-#define IT5205H_ISR_CSBU_MASK      BIT(4)
-#define IT5205H_ISR_CSBU_OVP       BIT(0)
+#define IT5205H_REG_ISR 0x25
+#define IT5205H_ISR_CSBU_MASK BIT(4)
+#define IT5205H_ISR_CSBU_OVP BIT(0)
 
 enum ec_error_list it5205h_enable_csbu_switch(const struct usb_mux *me,
 					      bool en);
diff --git a/driver/usb_mux/pi3usb3x532.c b/driver/usb_mux/pi3usb3x532.c
index 2435157967..54eff928b7 100644
--- a/driver/usb_mux/pi3usb3x532.c
+++ b/driver/usb_mux/pi3usb3x532.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,8 +11,7 @@
 #include "usb_mux.h"
 #include "util.h"
 
-static int pi3usb3x532_read(const struct usb_mux *me,
-			    uint8_t reg, uint8_t *val)
+static int pi3usb3x532_read(const struct usb_mux *me, uint8_t reg, uint8_t *val)
 {
 	int read, res;
 
@@ -33,8 +32,7 @@ static int pi3usb3x532_read(const struct usb_mux *me,
 	return EC_SUCCESS;
 }
 
-static int pi3usb3x532_write(const struct usb_mux *me,
-			     uint8_t reg, uint8_t val)
+static int pi3usb3x532_write(const struct usb_mux *me, uint8_t reg, uint8_t val)
 {
 	if (reg != PI3USB3X532_REG_CONTROL)
 		return EC_ERROR_UNKNOWN;
@@ -58,11 +56,10 @@ int pi3usb3x532_check_vendor(const struct usb_mux *me, int *val)
 
 static int pi3usb3x532_reset(const struct usb_mux *me)
 {
-	return pi3usb3x532_write(
-		me,
-		PI3USB3X532_REG_CONTROL,
-		(PI3USB3X532_MODE_POWERDOWN & PI3USB3X532_CTRL_MASK) |
-		PI3USB3X532_CTRL_RSVD);
+	return pi3usb3x532_write(me, PI3USB3X532_REG_CONTROL,
+				 (PI3USB3X532_MODE_POWERDOWN &
+				  PI3USB3X532_CTRL_MASK) |
+					 PI3USB3X532_CTRL_RSVD);
 }
 
 static int pi3usb3x532_init(const struct usb_mux *me)
@@ -83,8 +80,7 @@ static int pi3usb3x532_init(const struct usb_mux *me)
 }
 
 /* Writes control register to set switch mode */
-static int pi3usb3x532_set_mux(const struct usb_mux *me,
-			       mux_state_t mux_state,
+static int pi3usb3x532_set_mux(const struct usb_mux *me, mux_state_t mux_state,
 			       bool *ack_required)
 {
 	uint8_t reg = 0;
@@ -92,6 +88,10 @@ static int pi3usb3x532_set_mux(const struct usb_mux *me,
 	/* This driver does not use host command ACKs */
 	*ack_required = false;
 
+	/* This driver treats safe mode as none */
+	if (mux_state == USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
+
 	if (mux_state & USB_PD_MUX_USB_ENABLED)
 		reg |= PI3USB3X532_MODE_USB;
 	if (mux_state & USB_PD_MUX_DP_ENABLED)
@@ -104,8 +104,7 @@ static int pi3usb3x532_set_mux(const struct usb_mux *me,
 }
 
 /* Reads control register and updates mux_state accordingly */
-static int pi3usb3x532_get_mux(const struct usb_mux *me,
-			       mux_state_t *mux_state)
+static int pi3usb3x532_get_mux(const struct usb_mux *me, mux_state_t *mux_state)
 {
 	uint8_t reg = 0;
 	uint8_t res;
diff --git a/driver/usb_mux/pi3usb3x532.h b/driver/usb_mux/pi3usb3x532.h
index 6b398fdace..9214d349f0 100644
--- a/driver/usb_mux/pi3usb3x532.h
+++ b/driver/usb_mux/pi3usb3x532.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -70,8 +70,8 @@
  * dp0-1 : rx1, tx1
  * hpd+/-: rfu2, rfu1
  */
-#define PI3USB3X532_MODE_DP_USB_SWAP (PI3USB3X532_MODE_DP_USB | \
-				      PI3USB3X532_BIT_SWAP)
+#define PI3USB3X532_MODE_DP_USB_SWAP \
+	(PI3USB3X532_MODE_DP_USB | PI3USB3X532_BIT_SWAP)
 
 /* Get Vendor ID */
 int pi3usb3x532_check_vendor(const struct usb_mux *me, int *val);
diff --git a/driver/usb_mux/ps8740.c b/driver/usb_mux/ps8740.c
index 618c74cd65..557c4f1976 100644
--- a/driver/usb_mux/ps8740.c
+++ b/driver/usb_mux/ps8740.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -14,14 +14,12 @@
 
 int ps8740_read(const struct usb_mux *me, uint8_t reg, int *val)
 {
-	return i2c_read8(me->i2c_port, me->i2c_addr_flags,
-			 reg, val);
+	return i2c_read8(me->i2c_port, me->i2c_addr_flags, reg, val);
 }
 
 int ps8740_write(const struct usb_mux *me, uint8_t reg, uint8_t val)
 {
-	return i2c_write8(me->i2c_port, me->i2c_addr_flags,
-			  reg, val);
+	return i2c_write8(me->i2c_port, me->i2c_addr_flags, reg, val);
 }
 
 static int ps8740_init(const struct usb_mux *me)
@@ -42,7 +40,7 @@ static int ps8740_init(const struct usb_mux *me)
 	if (res)
 		return res;
 
-	res  = ps8740_read(me, PS8740_REG_CHIP_ID2, &id2);
+	res = ps8740_read(me, PS8740_REG_CHIP_ID2, &id2);
 	if (res)
 		return res;
 
@@ -78,6 +76,10 @@ static int ps8740_set_mux(const struct usb_mux *me, mux_state_t mux_state,
 	/* This driver does not use host command ACKs */
 	*ack_required = false;
 
+	/* This driver treats safe mode as none */
+	if (mux_state == USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
+
 	if (mux_state & USB_PD_MUX_USB_ENABLED)
 		reg |= PS8740_MODE_USB_ENABLED;
 	if (mux_state & USB_PD_MUX_DP_ENABLED)
diff --git a/driver/usb_mux/ps8740.h b/driver/usb_mux/ps8740.h
index 3a669b5ad9..0b29a80cf1 100644
--- a/driver/usb_mux/ps8740.h
+++ b/driver/usb_mux/ps8740.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,67 +11,67 @@
 
 #include "usb_mux.h"
 
-#define PS8740_I2C_ADDR0_FLAG    0x10
-#define PS8740_I2C_ADDR1_FLAG    0x11
-#define PS8740_I2C_ADDR2_FLAG    0x19
-#define PS8740_I2C_ADDR3_FLAG    0x1a
+#define PS8740_I2C_ADDR0_FLAG 0x10
+#define PS8740_I2C_ADDR1_FLAG 0x11
+#define PS8740_I2C_ADDR2_FLAG 0x19
+#define PS8740_I2C_ADDR3_FLAG 0x1a
 
 /* Mode register for setting mux */
 #define PS8740_REG_MODE 0x00
 #define PS8740_MODE_POLARITY_INVERTED BIT(4)
-#define PS8740_MODE_USB_ENABLED       BIT(5)
-#define PS8740_MODE_DP_ENABLED        BIT(6)
+#define PS8740_MODE_USB_ENABLED BIT(5)
+#define PS8740_MODE_DP_ENABLED BIT(6)
 #ifdef CONFIG_USB_MUX_PS8740
-	#define PS8740_MODE_POWER_DOWN        BIT(7)
+#define PS8740_MODE_POWER_DOWN BIT(7)
 #elif defined(CONFIG_USB_MUX_PS8742)
-	#define PS8740_MODE_CE_DP_ENABLED     BIT(7)
-	/* To reset the state machine to default */
-	#define PS8740_MODE_POWER_DOWN        0
+#define PS8740_MODE_CE_DP_ENABLED BIT(7)
+/* To reset the state machine to default */
+#define PS8740_MODE_POWER_DOWN 0
 #endif
 
 /* Status register for checking mux state */
 #define PS8740_REG_STATUS 0x09
 #define PS8740_STATUS_POLARITY_INVERTED BIT(2)
-#define PS8740_STATUS_USB_ENABLED       BIT(3)
-#define PS8740_STATUS_DP_ENABLED        BIT(4)
-#define PS8740_STATUS_HPD_ASSERTED      BIT(7)
+#define PS8740_STATUS_USB_ENABLED BIT(3)
+#define PS8740_STATUS_DP_ENABLED BIT(4)
+#define PS8740_STATUS_HPD_ASSERTED BIT(7)
 
 /* Chip ID / revision registers and expected fused values */
 #define PS8740_REG_REVISION_ID1 0xf0
 #define PS8740_REG_REVISION_ID2 0xf1
-#define PS8740_REG_CHIP_ID1     0xf2
-#define PS8740_REG_CHIP_ID2     0xf3
+#define PS8740_REG_CHIP_ID1 0xf2
+#define PS8740_REG_CHIP_ID2 0xf3
 #ifdef CONFIG_USB_MUX_PS8740
-	#define PS8740_REVISION_ID1   0x00
-	#define PS8740_REVISION_ID2_0 0x0a
-	#define PS8740_REVISION_ID2_1 0x0b
-	#define PS8740_CHIP_ID1       0x40
+#define PS8740_REVISION_ID1 0x00
+#define PS8740_REVISION_ID2_0 0x0a
+#define PS8740_REVISION_ID2_1 0x0b
+#define PS8740_CHIP_ID1 0x40
 #elif defined(CONFIG_USB_MUX_PS8742)
-	#define PS8740_REVISION_ID1   0x01
-	#define PS8740_REVISION_ID2_0 0x0a
-	#define PS8740_REVISION_ID2_1 0x0a
-	#define PS8740_CHIP_ID1       0x42
+#define PS8740_REVISION_ID1 0x01
+#define PS8740_REVISION_ID2_0 0x0a
+#define PS8740_REVISION_ID2_1 0x0a
+#define PS8740_CHIP_ID1 0x42
 #endif
-#define PS8740_CHIP_ID2         0x87
+#define PS8740_CHIP_ID2 0x87
 
 /* USB equalization settings for Host to Mux */
-#define PS8740_REG_USB_EQ_TX     0x32
+#define PS8740_REG_USB_EQ_TX 0x32
 #define PS8740_USB_EQ_TX_10_1_DB 0x00
 #define PS8740_USB_EQ_TX_14_3_DB 0x20
-#define PS8740_USB_EQ_TX_8_5_DB  0x40
-#define PS8740_USB_EQ_TX_6_5_DB  0x60
+#define PS8740_USB_EQ_TX_8_5_DB 0x40
+#define PS8740_USB_EQ_TX_6_5_DB 0x60
 #define PS8740_USB_EQ_TX_11_5_DB 0x80
-#define PS8740_USB_EQ_TX_9_5_DB  0xc0
-#define PS8740_USB_EQ_TX_7_5_DB  0xe0
+#define PS8740_USB_EQ_TX_9_5_DB 0xc0
+#define PS8740_USB_EQ_TX_7_5_DB 0xe0
 #define PS8740_USB_EQ_TERM_100_OHM (0 << 2)
-#define PS8740_USB_EQ_TERM_85_OHM  BIT(2)
+#define PS8740_USB_EQ_TERM_85_OHM BIT(2)
 
 /* USB equalization settings for Connector to Mux */
-#define PS8740_REG_USB_EQ_RX     0x3b
-#define PS8740_USB_EQ_RX_4_4_DB  0x00
-#define PS8740_USB_EQ_RX_7_0_DB  0x10
-#define PS8740_USB_EQ_RX_8_2_DB  0x20
-#define PS8740_USB_EQ_RX_9_4_DB  0x30
+#define PS8740_REG_USB_EQ_RX 0x3b
+#define PS8740_USB_EQ_RX_4_4_DB 0x00
+#define PS8740_USB_EQ_RX_7_0_DB 0x10
+#define PS8740_USB_EQ_RX_8_2_DB 0x20
+#define PS8740_USB_EQ_RX_9_4_DB 0x30
 #define PS8740_USB_EQ_RX_10_2_DB 0x40
 #define PS8740_USB_EQ_RX_11_4_DB 0x50
 #define PS8740_USB_EQ_RX_14_3_DB 0x60
diff --git a/driver/usb_mux/ps8743.c b/driver/usb_mux/ps8743.c
index 28ad5e9546..86f0a7f9b2 100644
--- a/driver/usb_mux/ps8743.c
+++ b/driver/usb_mux/ps8743.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -25,24 +25,21 @@ static enum usb_conn_status saved_usb_conn_status[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 int ps8743_read(const struct usb_mux *me, uint8_t reg, int *val)
 {
-	return i2c_read8(me->i2c_port, me->i2c_addr_flags,
-			 reg, val);
+	return i2c_read8(me->i2c_port, me->i2c_addr_flags, reg, val);
 }
 
 int ps8743_write(const struct usb_mux *me, uint8_t reg, uint8_t val)
 {
-	return i2c_write8(me->i2c_port, me->i2c_addr_flags,
-			  reg, val);
+	return i2c_write8(me->i2c_port, me->i2c_addr_flags, reg, val);
 }
 
 int ps8743_field_update(const struct usb_mux *me, uint8_t reg, uint8_t mask,
 			uint8_t val)
 {
-	return i2c_field_update8(me->i2c_port, me->i2c_addr_flags,
-			  reg, mask, val);
+	return i2c_field_update8(me->i2c_port, me->i2c_addr_flags, reg, mask,
+				 val);
 }
 
-
 int ps8743_check_chip_id(const struct usb_mux *me, int *val)
 {
 	int id1;
@@ -56,7 +53,7 @@ int ps8743_check_chip_id(const struct usb_mux *me, int *val)
 	if (res)
 		return res;
 
-	res  = ps8743_read(me, PS8743_REG_CHIP_ID2, &id2);
+	res = ps8743_read(me, PS8743_REG_CHIP_ID2, &id2);
 	if (res)
 		return res;
 
@@ -83,7 +80,7 @@ static int ps8743_init(const struct usb_mux *me)
 	if (res)
 		return res;
 
-	res  = ps8743_read(me, PS8743_REG_CHIP_ID2, &id2);
+	res = ps8743_read(me, PS8743_REG_CHIP_ID2, &id2);
 	if (res)
 		return res;
 
@@ -121,14 +118,17 @@ static int ps8743_set_mux(const struct usb_mux *me, mux_state_t mux_state,
 	 * For CE_DP, CE_USB, and FLIP, disable pin control and enable I2C
 	 * control.
 	 */
-	uint8_t reg = (PS8743_MODE_IN_HPD_CONTROL |
-		       PS8743_MODE_DP_REG_CONTROL |
-		       PS8743_MODE_USB_REG_CONTROL |
-		       PS8743_MODE_FLIP_REG_CONTROL);
+	uint8_t reg =
+		(PS8743_MODE_IN_HPD_CONTROL | PS8743_MODE_DP_REG_CONTROL |
+		 PS8743_MODE_USB_REG_CONTROL | PS8743_MODE_FLIP_REG_CONTROL);
 
 	/* This driver does not use host command ACKs */
 	*ack_required = false;
 
+	/* This driver treats safe mode as none */
+	if (mux_state == USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
+
 	if (mux_state & USB_PD_MUX_USB_ENABLED)
 		reg |= PS8743_MODE_USB_ENABLE;
 	else
@@ -214,7 +214,7 @@ static enum usb_conn_status ps8743_get_usb_conn_status(const struct usb_mux *me)
 static void ps8743_suspend(void)
 {
 	for (int i = 0; i < board_get_usb_pd_port_count(); i++) {
-		const struct usb_mux *mux = &usb_muxes[i];
+		const struct usb_mux *mux = usb_muxes[i].mux;
 
 		if (mux->driver != &ps8743_usb_mux_driver)
 			continue;
@@ -233,7 +233,7 @@ DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, ps8743_suspend, HOOK_PRIO_DEFAULT);
 static void ps8743_resume(void)
 {
 	for (int i = 0; i < board_get_usb_pd_port_count(); i++) {
-		const struct usb_mux *mux = &usb_muxes[i];
+		const struct usb_mux *mux = usb_muxes[i].mux;
 
 		if (mux->driver != &ps8743_usb_mux_driver)
 			continue;
diff --git a/driver/usb_mux/ps8743.h b/driver/usb_mux/ps8743.h
index 8e3a9d9b4c..e34d4f93e4 100644
--- a/driver/usb_mux/ps8743.h
+++ b/driver/usb_mux/ps8743.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -14,30 +14,30 @@
 /* Status register for checking mux state */
 #define PS8743_REG_STATUS 0x09
 #define PS8743_STATUS_POLARITY_INVERTED BIT(2)
-#define PS8743_STATUS_USB_ENABLED       BIT(3)
-#define PS8743_STATUS_DP_ENABLED        BIT(4)
-#define PS8743_STATUS_HPD_ASSERTED      BIT(7)
+#define PS8743_STATUS_USB_ENABLED BIT(3)
+#define PS8743_STATUS_DP_ENABLED BIT(4)
+#define PS8743_STATUS_HPD_ASSERTED BIT(7)
 
 /* Chip ID / revision registers and expected fused values */
 #define PS8743_REG_REVISION_ID1 0xf0
 #define PS8743_REG_REVISION_ID2 0xf1
-#define PS8743_REG_CHIP_ID1     0xf2
-#define PS8743_REG_CHIP_ID2     0xf3
-#define PS8743_REVISION_ID1_0   0x00
-#define PS8743_REVISION_ID1_1   0x01
-#define PS8743_REVISION_ID2     0x0b
-#define PS8743_CHIP_ID1         0x41
-#define PS8743_CHIP_ID2         0x87
+#define PS8743_REG_CHIP_ID1 0xf2
+#define PS8743_REG_CHIP_ID2 0xf3
+#define PS8743_REVISION_ID1_0 0x00
+#define PS8743_REVISION_ID1_1 0x01
+#define PS8743_REVISION_ID2 0x0b
+#define PS8743_CHIP_ID1 0x41
+#define PS8743_CHIP_ID2 0x87
 
 /* Misc register for checking DCI / SS pair mode status */
-#define PS8743_MISC_DCI_SS_MODES          0x42
+#define PS8743_MISC_DCI_SS_MODES 0x42
 #define PS8743_SSTX_NORMAL_OPERATION_MODE BIT(4)
-#define PS8743_SSTX_POWER_SAVING_MODE     BIT(5)
-#define PS8743_SSTX_SUSPEND_MODE          BIT(6)
+#define PS8743_SSTX_POWER_SAVING_MODE BIT(5)
+#define PS8743_SSTX_SUSPEND_MODE BIT(6)
 
 /* Misc resiger for checking HPD / DP / USB / FLIP mode status */
 #define PS8743_MISC_HPD_DP_USB_FLIP 0x09
-#define PS8743_USB_MODE_STATUS      BIT(3)
-#define PS8743_DP_MODE_STATUS       BIT(4)
+#define PS8743_USB_MODE_STATUS BIT(3)
+#define PS8743_DP_MODE_STATUS BIT(4)
 
 #endif /* __CROS_EC_PS8743_H */
diff --git a/driver/usb_mux/ps8822.c b/driver/usb_mux/ps8822.c
index 7f25db37f4..d3ea76965d 100644
--- a/driver/usb_mux/ps8822.c
+++ b/driver/usb_mux/ps8822.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -15,15 +15,13 @@
 static int ps8822_read(const struct usb_mux *me, int page, uint8_t reg,
 		       int *val)
 {
-	return i2c_read8(me->i2c_port, me->i2c_addr_flags + page,
-			 reg, val);
+	return i2c_read8(me->i2c_port, me->i2c_addr_flags + page, reg, val);
 }
 
 static int ps8822_write(const struct usb_mux *me, int page, uint8_t reg,
 			int val)
 {
-	return i2c_write8(me->i2c_port, me->i2c_addr_flags + page,
-			reg, val);
+	return i2c_write8(me->i2c_port, me->i2c_addr_flags + page, reg, val);
 }
 
 int ps8822_set_dp_rx_eq(const struct usb_mux *me, int db)
@@ -32,8 +30,7 @@ int ps8822_set_dp_rx_eq(const struct usb_mux *me, int db)
 	int rv;
 
 	/* Read DP EQ register */
-	rv = ps8822_read(me, PS8822_REG_PAGE1, PS8822_REG_DP_EQ,
-			 &dpeq_reg);
+	rv = ps8822_read(me, PS8822_REG_PAGE1, PS8822_REG_DP_EQ, &dpeq_reg);
 	if (rv)
 		return rv;
 
@@ -44,13 +41,11 @@ int ps8822_set_dp_rx_eq(const struct usb_mux *me, int db)
 	dpeq_reg &= ~PS8822_DP_EQ_AUTO_EN;
 
 	/* Set gain to the requested value */
-	dpeq_reg &= ~(PS8822_DPEQ_LEVEL_UP_MASK <<
-		      PS8822_REG_DP_EQ_SHIFT);
+	dpeq_reg &= ~(PS8822_DPEQ_LEVEL_UP_MASK << PS8822_REG_DP_EQ_SHIFT);
 	dpeq_reg |= (db << PS8822_REG_DP_EQ_SHIFT);
 
 	/* Apply new EQ setting */
-	return ps8822_write(me, PS8822_REG_PAGE1, PS8822_REG_DP_EQ,
-			  dpeq_reg);
+	return ps8822_write(me, PS8822_REG_PAGE1, PS8822_REG_DP_EQ, dpeq_reg);
 }
 
 static int ps8822_init(const struct usb_mux *me)
@@ -88,6 +83,10 @@ static int ps8822_set_mux(const struct usb_mux *me, mux_state_t mux_state,
 	/* This driver does not use host command ACKs */
 	*ack_required = false;
 
+	/* This driver treats safe mode as none */
+	if (mux_state == USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
+
 	rv = ps8822_read(me, PS8822_REG_PAGE0, PS8822_REG_MODE, &reg);
 	if (rv)
 		return rv;
@@ -126,7 +125,6 @@ static int ps8822_get_mux(const struct usb_mux *me, mux_state_t *mux_state)
 	return EC_SUCCESS;
 }
 
-
 const struct usb_mux_driver ps8822_usb_mux_driver = {
 	.init = ps8822_init,
 	.set = ps8822_set_mux,
diff --git a/driver/usb_mux/ps8822.h b/driver/usb_mux/ps8822.h
index 86b911db70..4f7503b21b 100644
--- a/driver/usb_mux/ps8822.h
+++ b/driver/usb_mux/ps8822.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,48 +11,48 @@
 
 #include "usb_mux.h"
 
-#define PS8822_I2C_ADDR0_FLAG    0x10
-#define PS8822_I2C_ADDR1_FLAG    0x18
-#define PS8822_I2C_ADDR2_FLAG    0x58
-#define PS8822_I2C_ADDR3_FLAG    0x60
+#define PS8822_I2C_ADDR0_FLAG 0x10
+#define PS8822_I2C_ADDR1_FLAG 0x18
+#define PS8822_I2C_ADDR2_FLAG 0x58
+#define PS8822_I2C_ADDR3_FLAG 0x60
 
-#define PS8822_REG_PAGE0	0x00
+#define PS8822_REG_PAGE0 0x00
 
 /* Mode register for setting mux */
-#define PS8822_REG_MODE         0x01
-#define PS8822_MODE_ALT_DP_EN   BIT(7)
-#define PS8822_MODE_USB_EN      BIT(6)
-#define PS8822_MODE_FLIP        BIT(5)
-#define PS8822_MODE_PIN_E       BIT(4)
+#define PS8822_REG_MODE 0x01
+#define PS8822_MODE_ALT_DP_EN BIT(7)
+#define PS8822_MODE_USB_EN BIT(6)
+#define PS8822_MODE_FLIP BIT(5)
+#define PS8822_MODE_PIN_E BIT(4)
 
-#define PS8822_REG_CONFIG       0x02
+#define PS8822_REG_CONFIG 0x02
 #define PS8822_CONFIG_HPD_IN_DIS BIT(7)
-#define PS8822_CONFIG_DP_PLUG    BIT(6)
+#define PS8822_CONFIG_DP_PLUG BIT(6)
 
-#define PS8822_REG_DEV_ID1      0x06
-#define PS8822_REG_DEV_ID2      0x07
-#define PS8822_REG_DEV_ID3      0x08
-#define PS8822_REG_DEV_ID4      0x09
-#define PS8822_REG_DEV_ID5      0x0A
-#define PS8822_REG_DEV_ID6      0x0B
+#define PS8822_REG_DEV_ID1 0x06
+#define PS8822_REG_DEV_ID2 0x07
+#define PS8822_REG_DEV_ID3 0x08
+#define PS8822_REG_DEV_ID4 0x09
+#define PS8822_REG_DEV_ID5 0x0A
+#define PS8822_REG_DEV_ID6 0x0B
 
 #define PS8822_ID_LEN 6
 
-#define PS8822_REG_PAGE1        0x01
-#define PS8822_REG_DP_EQ        0xB6
-#define PS8822_DP_EQ_AUTO_EN    BIT(7)
+#define PS8822_REG_PAGE1 0x01
+#define PS8822_REG_DP_EQ 0xB6
+#define PS8822_DP_EQ_AUTO_EN BIT(7)
 
-#define PS8822_DPEQ_LEVEL_UP_9DB    0x00
-#define PS8822_DPEQ_LEVEL_UP_11DB   0x01
-#define PS8822_DPEQ_LEVEL_UP_12DB   0x02
-#define PS8822_DPEQ_LEVEL_UP_14DB   0x03
-#define PS8822_DPEQ_LEVEL_UP_17DB   0x04
-#define PS8822_DPEQ_LEVEL_UP_18DB   0x05
-#define PS8822_DPEQ_LEVEL_UP_19DB   0x06
-#define PS8822_DPEQ_LEVEL_UP_20DB   0x07
-#define PS8822_DPEQ_LEVEL_UP_21DB   0x08
-#define PS8822_DPEQ_LEVEL_UP_MASK   0x0F
-#define PS8822_REG_DP_EQ_SHIFT      3
+#define PS8822_DPEQ_LEVEL_UP_9DB 0x00
+#define PS8822_DPEQ_LEVEL_UP_11DB 0x01
+#define PS8822_DPEQ_LEVEL_UP_12DB 0x02
+#define PS8822_DPEQ_LEVEL_UP_14DB 0x03
+#define PS8822_DPEQ_LEVEL_UP_17DB 0x04
+#define PS8822_DPEQ_LEVEL_UP_18DB 0x05
+#define PS8822_DPEQ_LEVEL_UP_19DB 0x06
+#define PS8822_DPEQ_LEVEL_UP_20DB 0x07
+#define PS8822_DPEQ_LEVEL_UP_21DB 0x08
+#define PS8822_DPEQ_LEVEL_UP_MASK 0x0F
+#define PS8822_REG_DP_EQ_SHIFT 3
 
 /**
  * Set DP Rx Equalization value
diff --git a/driver/usb_mux/tusb1064.c b/driver/usb_mux/tusb1064.c
index 0d48725d40..7fd6cfe561 100644
--- a/driver/usb_mux/tusb1064.c
+++ b/driver/usb_mux/tusb1064.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,27 +7,27 @@
 #include "tusb1064.h"
 #include "usb_mux.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 #if defined(CONFIG_USB_MUX_TUSB1044) + defined(CONFIG_USB_MUX_TUSB1064) + \
-	defined(CONFIG_USB_MUX_TUSB546) != 1
+		defined(CONFIG_USB_MUX_TUSB546) !=                        \
+	1
 #error "Must choose exactly one of CONFIG_USB_MUX_TUSB{546,1044,1064}"
 #endif
 
 static int tusb1064_read(const struct usb_mux *me, uint8_t reg, uint8_t *val)
 {
 	int buffer = 0xee;
-	int res = i2c_read8(me->i2c_port, me->i2c_addr_flags,
-			    (int)reg, &buffer);
+	int res =
+		i2c_read8(me->i2c_port, me->i2c_addr_flags, (int)reg, &buffer);
 	*val = buffer;
 	return res;
 }
 
 static int tusb1064_write(const struct usb_mux *me, uint8_t reg, uint8_t val)
 {
-	return i2c_write8(me->i2c_port, me->i2c_addr_flags,
-			  (int)reg, (int)val);
+	return i2c_write8(me->i2c_port, me->i2c_addr_flags, (int)reg, (int)val);
 }
 
 #if defined(CONFIG_USB_MUX_TUSB1044)
@@ -96,13 +96,17 @@ static int tusb1064_set_mux(const struct usb_mux *me, mux_state_t mux_state,
 	int rv;
 	int mask;
 
+	/* This driver treats safe mode as none */
+	if (mux_state == USB_PD_MUX_SAFE_MODE)
+		mux_state = USB_PD_MUX_NONE;
+
 	rv = tusb1064_read(me, TUSB1064_REG_GENERAL, &reg);
 	if (rv)
 		return rv;
 
 	/* Mask bits that may be set in this function */
 	mask = REG_GENERAL_CTLSEL_USB3 | REG_GENERAL_CTLSEL_ANYDP |
-		REG_GENERAL_FLIPSEL;
+	       REG_GENERAL_FLIPSEL;
 #if defined(CONFIG_USB_MUX_TUSB1044) || defined(CONFIG_USB_MUX_TUSB546)
 	mask |= REG_GENERAL_HPDIN_OVERRIDE;
 #endif
diff --git a/driver/usb_mux/tusb1064.h b/driver/usb_mux/tusb1064.h
index d6eb649532..1a38290174 100644
--- a/driver/usb_mux/tusb1064.h
+++ b/driver/usb_mux/tusb1064.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,43 +17,43 @@
  *    F -> floating
  *    1 -> tied to VCC
  */
-#define TUSB1064_I2C_ADDR0_FLAGS     0x44
-#define TUSB1064_I2C_ADDR1_FLAGS     0x45
-#define TUSB1064_I2C_ADDR2_FLAGS     0x46
-#define TUSB1064_I2C_ADDR3_FLAGS     0x47
-#define TUSB1064_I2C_ADDR4_FLAGS     0x20
-#define TUSB1064_I2C_ADDR5_FLAGS     0x21
-#define TUSB1064_I2C_ADDR6_FLAGS     0x22
-#define TUSB1064_I2C_ADDR7_FLAGS     0x23
-#define TUSB1064_I2C_ADDR8_FLAGS     0x10
-#define TUSB1064_I2C_ADDR9_FLAGS     0x11
-#define TUSB1064_I2C_ADDR10_FLAGS    0x12
-#define TUSB1064_I2C_ADDR11_FLAGS    0x13
-#define TUSB1064_I2C_ADDR12_FLAGS    0x0C
-#define TUSB1064_I2C_ADDR13_FLAGS    0x0D
-#define TUSB1064_I2C_ADDR14_FLAGS    0x0E
-#define TUSB1064_I2C_ADDR15_FLAGS    0x0F
+#define TUSB1064_I2C_ADDR0_FLAGS 0x44
+#define TUSB1064_I2C_ADDR1_FLAGS 0x45
+#define TUSB1064_I2C_ADDR2_FLAGS 0x46
+#define TUSB1064_I2C_ADDR3_FLAGS 0x47
+#define TUSB1064_I2C_ADDR4_FLAGS 0x20
+#define TUSB1064_I2C_ADDR5_FLAGS 0x21
+#define TUSB1064_I2C_ADDR6_FLAGS 0x22
+#define TUSB1064_I2C_ADDR7_FLAGS 0x23
+#define TUSB1064_I2C_ADDR8_FLAGS 0x10
+#define TUSB1064_I2C_ADDR9_FLAGS 0x11
+#define TUSB1064_I2C_ADDR10_FLAGS 0x12
+#define TUSB1064_I2C_ADDR11_FLAGS 0x13
+#define TUSB1064_I2C_ADDR12_FLAGS 0x0C
+#define TUSB1064_I2C_ADDR13_FLAGS 0x0D
+#define TUSB1064_I2C_ADDR14_FLAGS 0x0E
+#define TUSB1064_I2C_ADDR15_FLAGS 0x0F
 
 /* TUSB1064 General Register */
-#define TUSB1064_REG_GENERAL            0x0a
-#define REG_GENERAL_CTLSEL_USB3         BIT(0)
-#define REG_GENERAL_CTLSEL_ANYDP        BIT(1)
-#define REG_GENERAL_FLIPSEL             BIT(2)
+#define TUSB1064_REG_GENERAL 0x0a
+#define REG_GENERAL_CTLSEL_USB3 BIT(0)
+#define REG_GENERAL_CTLSEL_ANYDP BIT(1)
+#define REG_GENERAL_FLIPSEL BIT(2)
 #if defined(CONFIG_USB_MUX_TUSB1044) || defined(CONFIG_USB_MUX_TUSB546)
-#define REG_GENERAL_HPDIN_OVERRIDE      BIT(3)
+#define REG_GENERAL_HPDIN_OVERRIDE BIT(3)
 #else
-#define REG_GENERAL_DP_EN_CTRL          BIT(3)
+#define REG_GENERAL_DP_EN_CTRL BIT(3)
 #endif
-#define REG_GENERAL_EQ_OVERRIDE         BIT(4)
+#define REG_GENERAL_EQ_OVERRIDE BIT(4)
 
 /* AUX and DP Lane Control Register */
-#define TUSB1064_REG_AUXDPCTRL          0x13
+#define TUSB1064_REG_AUXDPCTRL 0x13
 #define TUSB1064_AUXDPCTRL_AUX_SNOOP_DISABLE BIT(7)
-#define TUSB1064_AUXDPCTRL_AUX_SBU_OVR  0x30
-#define TUSB1064_AUXDPCTRL_DP3_DISABLE  BIT(3)
-#define TUSB1064_AUXDPCTRL_DP2_DISABLE  BIT(2)
-#define TUSB1064_AUXDPCTRL_DP1_DISABLE  BIT(1)
-#define TUSB1064_AUXDPCTRL_DP0_DISABLE  BIT(0)
+#define TUSB1064_AUXDPCTRL_AUX_SBU_OVR 0x30
+#define TUSB1064_AUXDPCTRL_DP3_DISABLE BIT(3)
+#define TUSB1064_AUXDPCTRL_DP2_DISABLE BIT(2)
+#define TUSB1064_AUXDPCTRL_DP1_DISABLE BIT(1)
+#define TUSB1064_AUXDPCTRL_DP0_DISABLE BIT(0)
 
 /* Receiver Equalization GPIO Control */
 #define TUSB1064_REG_DP1DP3EQ_SEL 0x10
@@ -78,19 +78,18 @@
 #define TUSB1064_DP_EQ_RX_12_1_DB 0xF
 
 #ifndef TUSB1064_DP1EQ
-#define TUSB1064_DP1EQ(nr)         ((nr) << 4)
+#define TUSB1064_DP1EQ(nr) ((nr) << 4)
 #endif
 #ifndef TUSB1064_DP3EQ
-#define TUSB1064_DP3EQ(nr)         ((nr) << 0)
+#define TUSB1064_DP3EQ(nr) ((nr) << 0)
 #endif
 #ifndef TUSB1064_DP0EQ
-#define TUSB1064_DP0EQ(nr)         ((nr) << 4)
+#define TUSB1064_DP0EQ(nr) ((nr) << 4)
 #endif
 #ifndef TUSB1064_DP2EQ
-#define TUSB1064_DP2EQ(nr)         ((nr) << 0)
+#define TUSB1064_DP2EQ(nr) ((nr) << 0)
 #endif
 
-
 /* TUSB1064 Receiver Equalization GPIO Control */
 #define TUSB1064_REG_SSRX2RX1EQ_SEL 0x20
 #define TUSB1064_REG_SSTXEQ_SEL 0x21
diff --git a/driver/usb_mux/usb_mux.c b/driver/usb_mux/usb_mux.c
index 1dea4b8d29..1edcf25179 100644
--- a/driver/usb_mux/usb_mux.c
+++ b/driver/usb_mux/usb_mux.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,9 +6,11 @@
 /* USB mux high-level driver. */
 
 #include "atomic.h"
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
 #include "chipset.h"
+#include "ec_commands.h"
 #include "hooks.h"
 #include "host_command.h"
 #include "queue.h"
@@ -19,8 +21,8 @@
 #include "util.h"
 
 #ifdef CONFIG_COMMON_RUNTIME
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 #else
 #define CPRINTS(format, args...)
 #define CPRINTF(format, args...)
@@ -35,17 +37,18 @@ static int enable_debug_prints;
 static atomic_t flags[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 /* Device is in low power mode. */
-#define USB_MUX_FLAG_IN_LPM		BIT(0)
+#define USB_MUX_FLAG_IN_LPM BIT(0)
 
 /* Device initialized at least once */
-#define USB_MUX_FLAG_INIT		BIT(1)
+#define USB_MUX_FLAG_INIT BIT(1)
 
 /* Coordinate mux accesses by-port among the tasks */
 static mutex_t mux_lock[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 /* Coordinate which task requires an ACK event */
 static task_id_t ack_task[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[0 ... CONFIG_USB_PD_PORT_MAX_COUNT - 1] = TASK_ID_INVALID };
+	[0 ... CONFIG_USB_PD_PORT_MAX_COUNT - 1] = TASK_ID_INVALID
+};
 
 static void perform_mux_set(int port, int index, mux_state_t mux_mode,
 			    enum usb_switch usb_mode, int polarity);
@@ -60,9 +63,6 @@ enum mux_config_type {
 	USB_MUX_HPD_UPDATE,
 };
 
-/* Set all muxes for this board's port */
-#define USB_MUX_ALL_CHIPS -1
-
 /* Define a USB mux task ID for the purpose of linking */
 #ifndef HAS_TASK_USB_MUX
 #define TASK_ID_USB_MUX TASK_ID_INVALID
@@ -79,7 +79,7 @@ enum mux_config_type {
  * Depth must be a power of 2, which is normally enforced by the queue init
  * code, but must be manually enforced here.
  */
-#define MUX_QUEUE_DEPTH		4
+#define MUX_QUEUE_DEPTH 4
 BUILD_ASSERT(POWER_OF_TWO(MUX_QUEUE_DEPTH));
 
 /* Define in order to enable debug info about how long the queue takes */
@@ -87,10 +87,10 @@ BUILD_ASSERT(POWER_OF_TWO(MUX_QUEUE_DEPTH));
 
 struct mux_queue_entry {
 	enum mux_config_type type;
-	int index;			/* Index to set, or USB_MUX_ALL_CHIPS */
-	mux_state_t mux_mode;		/* For both HPD and mux set */
-	enum usb_switch usb_config;	/* Set only */
-	int polarity;			/* Set only */
+	int index; /* Index to set, or TYPEC_USB_MUX_SET_ALL_CHIPS */
+	mux_state_t mux_mode; /* For both HPD and mux set */
+	enum usb_switch usb_config; /* Set only */
+	int polarity; /* Set only */
 #ifdef DEBUG_MUX_QUEUE_TIME
 	timestamp_t enqueued_time;
 #endif
@@ -108,10 +108,9 @@ struct mux_queue_entry {
  */
 static struct queue mux_queue[CONFIG_USB_PD_PORT_MAX_COUNT];
 __maybe_unused static struct queue_state
-				queue_states[CONFIG_USB_PD_PORT_MAX_COUNT];
+	queue_states[CONFIG_USB_PD_PORT_MAX_COUNT];
 __maybe_unused static struct mux_queue_entry
-				queue_buffers[CONFIG_USB_PD_PORT_MAX_COUNT]
-					     [MUX_QUEUE_DEPTH];
+	queue_buffers[CONFIG_USB_PD_PORT_MAX_COUNT][MUX_QUEUE_DEPTH];
 static mutex_t queue_lock[CONFIG_USB_PD_PORT_MAX_COUNT];
 #else
 extern struct queue const mux_queue[];
@@ -136,11 +135,9 @@ static int init_mux_mutex(const struct device *dev)
 SYS_INIT(init_mux_mutex, POST_KERNEL, 50);
 #endif /* CONFIG_ZEPHYR */
 
-__maybe_unused static void mux_task_enqueue(int port, int index,
-					    enum mux_config_type type,
-					    mux_state_t mux_mode,
-					    enum usb_switch usb_config,
-					    int polarity)
+__maybe_unused static void
+mux_task_enqueue(int port, int index, enum mux_config_type type,
+		 mux_state_t mux_mode, enum usb_switch usb_config, int polarity)
 {
 	struct mux_queue_entry new_entry;
 
@@ -177,7 +174,7 @@ static void init_queue_structs(void)
 		mux_queue[i].buffer_units = MUX_QUEUE_DEPTH;
 		mux_queue[i].buffer_units_mask = MUX_QUEUE_DEPTH - 1;
 		mux_queue[i].unit_bytes = sizeof(struct mux_queue_entry);
-		mux_queue[i].buffer = (uint8_t *) &queue_buffers[i][0];
+		mux_queue[i].buffer = (uint8_t *)&queue_buffers[i][0];
 	}
 }
 DECLARE_HOOK(HOOK_INIT, init_queue_structs, HOOK_PRIO_FIRST);
@@ -227,7 +224,8 @@ __maybe_unused void usb_mux_task(void *u)
 							       next.mux_mode);
 				else
 					CPRINTS("Error: Unknown mux task type:"
-						"%d", next.type);
+						"%d",
+						next.type);
 
 #ifdef DEBUG_MUX_QUEUE_TIME
 				CPRINTS("C%d: Completed mux set queued %d "
@@ -254,16 +252,14 @@ __maybe_unused void usb_mux_task(void *u)
 }
 
 /* Configure the MUX */
-static int configure_mux(int port, int index,
-			 enum mux_config_type config,
+static int configure_mux(int port, int index, enum mux_config_type config,
 			 mux_state_t *mux_state)
 {
 	int rv = EC_SUCCESS;
-	const struct usb_mux *mux_ptr;
+	const struct usb_mux_chain *mux_chain;
 	int chip = 0;
 
-	if (config == USB_MUX_SET_MODE ||
-	    config == USB_MUX_GET_MODE) {
+	if (config == USB_MUX_SET_MODE || config == USB_MUX_GET_MODE) {
 		if (mux_state == NULL)
 			return EC_ERROR_INVAL;
 
@@ -276,14 +272,15 @@ static int configure_mux(int port, int index,
 	 * MUXes.  So when we change one, we traverse the whole list
 	 * to make sure they are all updated appropriately.
 	 */
-	for (mux_ptr = &usb_muxes[port];
-	     rv == EC_SUCCESS && mux_ptr != NULL;
-	     mux_ptr = mux_ptr->next_mux, chip++) {
+	for (mux_chain = &usb_muxes[port];
+	     rv == EC_SUCCESS && mux_chain != NULL && mux_chain->mux != NULL;
+	     mux_chain = mux_chain->next, chip++) {
 		mux_state_t lcl_state;
+		const struct usb_mux *mux_ptr = mux_chain->mux;
 		const struct usb_mux_driver *drv = mux_ptr->driver;
 		bool ack_required = false;
 
-		if (index != USB_MUX_ALL_CHIPS && index != chip)
+		if (index != TYPEC_USB_MUX_SET_ALL_CHIPS && index != chip)
 			continue;
 
 		/* Action time!  Lock this mux */
@@ -321,6 +318,10 @@ static int configure_mux(int port, int index,
 			if (mux_ptr->flags & USB_MUX_FLAG_SET_WITHOUT_FLIP)
 				lcl_state &= ~USB_PD_MUX_POLARITY_INVERTED;
 
+			if ((lcl_state != USB_PD_MUX_NONE) &&
+			    (mux_ptr->flags & USB_MUX_FLAG_POLARITY_INVERTED))
+				lcl_state ^= USB_PD_MUX_POLARITY_INVERTED;
+
 			if (drv && drv->set) {
 				rv = drv->set(mux_ptr, lcl_state,
 					      &ack_required);
@@ -335,10 +336,12 @@ static int configure_mux(int port, int index,
 			/* Inform the AP its selected mux is set */
 			if (IS_ENABLED(CONFIG_USB_MUX_AP_CONTROL)) {
 				if (chip == 0)
-					pd_notify_event(port,
+					pd_notify_event(
+						port,
 						PD_STATUS_EVENT_MUX_0_SET_DONE);
 				else if (chip == 1)
-					pd_notify_event(port,
+					pd_notify_event(
+						port,
 						PD_STATUS_EVENT_MUX_1_SET_DONE);
 			}
 
@@ -363,7 +366,6 @@ static int configure_mux(int port, int index,
 			if (mux_ptr->hpd_update)
 				mux_ptr->hpd_update(mux_ptr, *mux_state,
 						    &ack_required);
-
 		}
 
 		/* Unlock before any host command waits */
@@ -380,10 +382,10 @@ static int configure_mux(int port, int index,
 				assert(task_get_current() == TASK_ID_USB_MUX);
 			} else {
 #if defined(CONFIG_ZEPHYR) && defined(TEST_BUILD)
-				assert(port ==
-				       TASK_ID_TO_PD_PORT(task_get_current()) ||
+				assert(port == TASK_ID_TO_PD_PORT(
+						       task_get_current()) ||
 				       task_get_current() ==
-				       TASK_ID_TEST_RUNNER);
+					       TASK_ID_TEST_RUNNER);
 #else
 				assert(port ==
 				       TASK_ID_TO_PD_PORT(task_get_current()));
@@ -397,7 +399,7 @@ static int configure_mux(int port, int index,
 			 * mux, but could be made configurable for other
 			 * purposes.
 			 */
-			task_wait_event_mask(PD_EVENT_AP_MUX_DONE, 100*MSEC);
+			task_wait_event_mask(PD_EVENT_AP_MUX_DONE, 100 * MSEC);
 			ack_task[port] = TASK_ID_INVALID;
 
 			usleep(12.5 * MSEC);
@@ -405,8 +407,7 @@ static int configure_mux(int port, int index,
 	}
 
 	if (rv)
-		CPRINTS("mux config:%d, port:%d, rv:%d",
-			config, port, rv);
+		CPRINTS("mux config:%d, port:%d, rv:%d", config, port, rv);
 
 	return rv;
 }
@@ -421,7 +422,8 @@ static void enter_low_power_mode(int port)
 	atomic_or(&flags[port], USB_MUX_FLAG_IN_LPM);
 
 	/* Apply any low power customization if present */
-	configure_mux(port, USB_MUX_ALL_CHIPS, USB_MUX_LOW_POWER, NULL);
+	configure_mux(port, TYPEC_USB_MUX_SET_ALL_CHIPS, USB_MUX_LOW_POWER,
+		      NULL);
 }
 
 static int exit_low_power_mode(int port)
@@ -453,7 +455,8 @@ void usb_mux_init(int port)
 		return;
 	}
 
-	rv = configure_mux(port, USB_MUX_ALL_CHIPS, USB_MUX_INIT, NULL);
+	rv = configure_mux(port, TYPEC_USB_MUX_SET_ALL_CHIPS, USB_MUX_INIT,
+			   NULL);
 
 	if (rv == EC_SUCCESS)
 		atomic_or(&flags[port], USB_MUX_FLAG_INIT);
@@ -474,7 +477,7 @@ static void perform_mux_set(int port, int index, mux_state_t mux_mode,
 	mux_state_t mux_state;
 	const int should_enter_low_power_mode =
 		(mux_mode == USB_PD_MUX_NONE &&
-		usb_mode == USB_SWITCH_DISCONNECT);
+		 usb_mode == USB_SWITCH_DISCONNECT);
 
 	/* Perform initialization if not initialized yet */
 	if (!(flags[port] & USB_MUX_FLAG_INIT))
@@ -496,17 +499,16 @@ static void perform_mux_set(int port, int index, mux_state_t mux_mode,
 		return;
 
 	/* Configure superspeed lanes */
-	mux_state = ((mux_mode != USB_PD_MUX_NONE) && polarity)
-			? mux_mode | USB_PD_MUX_POLARITY_INVERTED
-			: mux_mode;
+	mux_state = ((mux_mode != USB_PD_MUX_NONE) && polarity) ?
+			    mux_mode | USB_PD_MUX_POLARITY_INVERTED :
+			    mux_mode;
 
 	if (configure_mux(port, index, USB_MUX_SET_MODE, &mux_state))
 		return;
 
 	if (enable_debug_prints)
-		CPRINTS(
-		     "usb/dp mux: port(%d) typec_mux(%d) usb2(%d) polarity(%d)",
-		     port, mux_mode, usb_mode, polarity);
+		CPRINTS("usb/dp mux: port(%d) typec_mux(%d) usb2(%d) polarity(%d)",
+			port, mux_mode, usb_mode, polarity);
 
 	/*
 	 * If we are completely disconnecting the mux, then we should put it in
@@ -516,20 +518,20 @@ static void perform_mux_set(int port, int index, mux_state_t mux_mode,
 		enter_low_power_mode(port);
 }
 
-void usb_mux_set(int port, mux_state_t mux_mode,
-		 enum usb_switch usb_mode, int polarity)
+void usb_mux_set(int port, mux_state_t mux_mode, enum usb_switch usb_mode,
+		 int polarity)
 {
 	if (port >= board_get_usb_pd_port_count())
 		return;
 
 	/* Block if we have no mux task, but otherwise queue it up and return */
 	if (IS_ENABLED(HAS_TASK_USB_MUX))
-		mux_task_enqueue(port, USB_MUX_ALL_CHIPS,
-				 USB_MUX_SET_MODE, mux_mode,
-				 usb_mode, polarity);
+		mux_task_enqueue(port, TYPEC_USB_MUX_SET_ALL_CHIPS,
+				 USB_MUX_SET_MODE, mux_mode, usb_mode,
+				 polarity);
 	else
-		perform_mux_set(port, USB_MUX_ALL_CHIPS,
-				mux_mode, usb_mode, polarity);
+		perform_mux_set(port, TYPEC_USB_MUX_SET_ALL_CHIPS, mux_mode,
+				usb_mode, polarity);
 }
 
 void usb_mux_set_single(int port, int index, mux_state_t mux_mode,
@@ -540,12 +542,10 @@ void usb_mux_set_single(int port, int index, mux_state_t mux_mode,
 
 	/* Block if we have no mux task, but otherwise queue it up and return */
 	if (IS_ENABLED(HAS_TASK_USB_MUX))
-		mux_task_enqueue(port, index,
-				 USB_MUX_SET_MODE, mux_mode,
+		mux_task_enqueue(port, index, USB_MUX_SET_MODE, mux_mode,
 				 usb_mode, polarity);
 	else
-		perform_mux_set(port, index,
-				mux_mode, usb_mode, polarity);
+		perform_mux_set(port, index, mux_mode, usb_mode, polarity);
 }
 
 bool usb_mux_set_completed(int port)
@@ -561,9 +561,9 @@ bool usb_mux_set_completed(int port)
 	mutex_lock(&queue_lock[port]);
 
 	for (queue_begin(&mux_queue[port], &it); it.ptr != NULL;
-					queue_next(&mux_queue[port], &it)) {
+	     queue_next(&mux_queue[port], &it)) {
 		const struct mux_queue_entry *check =
-					(struct mux_queue_entry *) it.ptr;
+			(struct mux_queue_entry *)it.ptr;
 
 		if (check->type == USB_MUX_SET_MODE) {
 			sets_pending = true;
@@ -590,8 +590,8 @@ static enum ec_error_list try_usb_mux_get(int port, mux_state_t *mux_state)
 		return EC_SUCCESS;
 	}
 
-	return configure_mux(port, USB_MUX_ALL_CHIPS, USB_MUX_GET_MODE,
-			     mux_state);
+	return configure_mux(port, TYPEC_USB_MUX_SET_ALL_CHIPS,
+			     USB_MUX_GET_MODE, mux_state);
 }
 
 mux_state_t usb_mux_get(int port)
@@ -619,7 +619,7 @@ void usb_mux_flip(int port)
 	if (exit_low_power_mode(port) != EC_SUCCESS)
 		return;
 
-	if (configure_mux(port, USB_MUX_ALL_CHIPS, USB_MUX_GET_MODE,
+	if (configure_mux(port, TYPEC_USB_MUX_SET_ALL_CHIPS, USB_MUX_GET_MODE,
 			  &mux_state))
 		return;
 
@@ -628,7 +628,8 @@ void usb_mux_flip(int port)
 	else
 		mux_state |= USB_PD_MUX_POLARITY_INVERTED;
 
-	configure_mux(port, USB_MUX_ALL_CHIPS, USB_MUX_SET_MODE, &mux_state);
+	configure_mux(port, TYPEC_USB_MUX_SET_ALL_CHIPS, USB_MUX_SET_MODE,
+		      &mux_state);
 }
 
 static void perform_mux_hpd_update(int port, int index, mux_state_t hpd_state)
@@ -650,10 +651,11 @@ void usb_mux_hpd_update(int port, mux_state_t hpd_state)
 
 	/* Send to the mux task if present to maintain sequencing with sets */
 	if (IS_ENABLED(HAS_TASK_USB_MUX))
-		mux_task_enqueue(port, USB_MUX_ALL_CHIPS, USB_MUX_HPD_UPDATE,
-				 hpd_state, 0, 0);
+		mux_task_enqueue(port, TYPEC_USB_MUX_SET_ALL_CHIPS,
+				 USB_MUX_HPD_UPDATE, hpd_state, 0, 0);
 	else
-		perform_mux_hpd_update(port, USB_MUX_ALL_CHIPS, hpd_state);
+		perform_mux_hpd_update(port, TYPEC_USB_MUX_SET_ALL_CHIPS,
+				       hpd_state);
 }
 
 int usb_mux_retimer_fw_update_port_info(void)
@@ -661,15 +663,17 @@ int usb_mux_retimer_fw_update_port_info(void)
 	int i;
 	int port_info = 0;
 	const struct usb_mux *mux_ptr;
+	const struct usb_mux_chain *mux_chain;
 
 	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
-		mux_ptr = &usb_muxes[i];
-		while (mux_ptr) {
+		mux_chain = &usb_muxes[i];
+		while (mux_chain && mux_chain->mux) {
+			mux_ptr = mux_chain->mux;
 			if (mux_ptr->driver &&
-				mux_ptr->driver->is_retimer_fw_update_capable &&
-				mux_ptr->driver->is_retimer_fw_update_capable())
+			    mux_ptr->driver->is_retimer_fw_update_capable &&
+			    mux_ptr->driver->is_retimer_fw_update_capable())
 				port_info |= BIT(i);
-			mux_ptr = mux_ptr->next_mux;
+			mux_chain = mux_chain->next;
 		}
 	}
 	return port_info;
@@ -680,8 +684,8 @@ static void mux_chipset_reset(void)
 	int port;
 
 	for (port = 0; port < board_get_usb_pd_port_count(); ++port)
-		configure_mux(port, USB_MUX_ALL_CHIPS, USB_MUX_CHIPSET_RESET,
-			      NULL);
+		configure_mux(port, TYPEC_USB_MUX_SET_ALL_CHIPS,
+			      USB_MUX_CHIPSET_RESET, NULL);
 }
 DECLARE_HOOK(HOOK_CHIPSET_RESET, mux_chipset_reset, HOOK_PRIO_DEFAULT);
 
@@ -693,26 +697,28 @@ static void usb_mux_reset_in_g3(void)
 {
 	int port;
 	const struct usb_mux *mux_ptr;
+	const struct usb_mux_chain *mux_chain;
 
 	for (port = 0; port < board_get_usb_pd_port_count(); port++) {
-		mux_ptr = &usb_muxes[port];
+		mux_chain = &usb_muxes[port];
 
-		while (mux_ptr) {
+		while (mux_chain && mux_chain->mux) {
+			mux_ptr = mux_chain->mux;
 			if (mux_ptr->flags & USB_MUX_FLAG_RESETS_IN_G3) {
 				atomic_clear_bits(&flags[port],
 						  USB_MUX_FLAG_INIT |
-						  USB_MUX_FLAG_IN_LPM);
+							  USB_MUX_FLAG_IN_LPM);
 			}
-			mux_ptr = mux_ptr->next_mux;
+			mux_chain = mux_chain->next;
 		}
 	}
 }
 DECLARE_HOOK(HOOK_CHIPSET_HARD_OFF, usb_mux_reset_in_g3, HOOK_PRIO_DEFAULT);
 
 #ifdef CONFIG_CMD_TYPEC
-static int command_typec(int argc, char **argv)
+static int command_typec(int argc, const char **argv)
 {
-	const char * const mux_name[] = {"none", "usb", "dp", "dock"};
+	const char *const mux_name[] = { "none", "usb", "dp", "dock" };
 	char *e;
 	int port;
 	mux_state_t mux = USB_PD_MUX_NONE;
@@ -735,16 +741,16 @@ static int command_typec(int argc, char **argv)
 
 		mux_state = usb_mux_get(port);
 		ccprintf("Port %d: USB=%d DP=%d POLARITY=%s HPD_IRQ=%d "
-			"HPD_LVL=%d SAFE=%d TBT=%d USB4=%d\n", port,
-			!!(mux_state & USB_PD_MUX_USB_ENABLED),
-			!!(mux_state & USB_PD_MUX_DP_ENABLED),
-			mux_state & USB_PD_MUX_POLARITY_INVERTED ?
-				"INVERTED" : "NORMAL",
-			!!(mux_state & USB_PD_MUX_HPD_IRQ),
-			!!(mux_state & USB_PD_MUX_HPD_LVL),
-			!!(mux_state & USB_PD_MUX_SAFE_MODE),
-			!!(mux_state & USB_PD_MUX_TBT_COMPAT_ENABLED),
-			!!(mux_state & USB_PD_MUX_USB4_ENABLED));
+			 "HPD_LVL=%d SAFE=%d TBT=%d USB4=%d\n",
+			 port, !!(mux_state & USB_PD_MUX_USB_ENABLED),
+			 !!(mux_state & USB_PD_MUX_DP_ENABLED),
+			 mux_state & USB_PD_MUX_POLARITY_INVERTED ? "INVERTED" :
+								    "NORMAL",
+			 !!(mux_state & USB_PD_MUX_HPD_IRQ),
+			 !!(mux_state & USB_PD_MUX_HPD_LVL),
+			 !!(mux_state & USB_PD_MUX_SAFE_MODE),
+			 !!(mux_state & USB_PD_MUX_TBT_COMPAT_ENABLED),
+			 !!(mux_state & USB_PD_MUX_USB4_ENABLED));
 
 		return EC_SUCCESS;
 	}
@@ -752,14 +758,13 @@ static int command_typec(int argc, char **argv)
 	for (i = 0; i < ARRAY_SIZE(mux_name); i++)
 		if (!strcasecmp(argv[2], mux_name[i]))
 			mux = i;
-	usb_mux_set(port, mux, mux == USB_PD_MUX_NONE ?
-				      USB_SWITCH_DISCONNECT :
-				      USB_SWITCH_CONNECT,
-			  polarity_rm_dts(pd_get_polarity(port)));
+	usb_mux_set(port, mux,
+		    mux == USB_PD_MUX_NONE ? USB_SWITCH_DISCONNECT :
+					     USB_SWITCH_CONNECT,
+		    polarity_rm_dts(pd_get_polarity(port)));
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(typec, command_typec,
-			"[port|debug] [none|usb|dp|dock]",
+DECLARE_CONSOLE_COMMAND(typec, command_typec, "[port|debug] [none|usb|dp|dock]",
 			"Control type-C connector muxing");
 #endif
 
@@ -786,8 +791,7 @@ static enum ec_status hc_usb_pd_mux_info(struct host_cmd_handler_args *args)
 	args->response_size = sizeof(*r);
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_USB_PD_MUX_INFO,
-		     hc_usb_pd_mux_info,
+DECLARE_HOST_COMMAND(EC_CMD_USB_PD_MUX_INFO, hc_usb_pd_mux_info,
 		     EC_VER_MASK(0));
 
 static enum ec_status hc_usb_pd_mux_ack(struct host_cmd_handler_args *args)
@@ -802,6 +806,4 @@ static enum ec_status hc_usb_pd_mux_ack(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_USB_PD_MUX_ACK,
-		     hc_usb_pd_mux_ack,
-		     EC_VER_MASK(0));
+DECLARE_HOST_COMMAND(EC_CMD_USB_PD_MUX_ACK, hc_usb_pd_mux_ack, EC_VER_MASK(0));
diff --git a/driver/usb_mux/virtual.c b/driver/usb_mux/virtual.c
index 23987fd676..417a48c577 100644
--- a/driver/usb_mux/virtual.c
+++ b/driver/usb_mux/virtual.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -18,11 +18,11 @@
  * configures the HPD mux state. Both states are independent of each other
  * may differ when the PD role changes when in dock mode.
  */
-#define USB_PD_MUX_HPD_STATE	(USB_PD_MUX_HPD_LVL | USB_PD_MUX_HPD_IRQ)
-#define USB_PD_MUX_USB_DP_STATE	(USB_PD_MUX_USB_ENABLED | \
-			USB_PD_MUX_DP_ENABLED | USB_PD_MUX_POLARITY_INVERTED | \
-			USB_PD_MUX_SAFE_MODE | USB_PD_MUX_TBT_COMPAT_ENABLED | \
-			USB_PD_MUX_USB4_ENABLED)
+#define USB_PD_MUX_HPD_STATE (USB_PD_MUX_HPD_LVL | USB_PD_MUX_HPD_IRQ)
+#define USB_PD_MUX_USB_DP_STATE                                \
+	(USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED |      \
+	 USB_PD_MUX_POLARITY_INVERTED | USB_PD_MUX_SAFE_MODE | \
+	 USB_PD_MUX_TBT_COMPAT_ENABLED | USB_PD_MUX_USB4_ENABLED)
 
 static mux_state_t virtual_mux_state[CONFIG_USB_PD_PORT_MAX_COUNT];
 
@@ -82,7 +82,8 @@ static int virtual_set_mux(const struct usb_mux *me, mux_state_t mux_state,
 	 * is still active.  Otherwise, don't preserve HPD state.
 	 */
 	if (mux_state & USB_PD_MUX_DP_ENABLED)
-		new_mux_state = (mux_state & ~USB_PD_MUX_HPD_STATE) |
+		new_mux_state =
+			(mux_state & ~USB_PD_MUX_HPD_STATE) |
 			(virtual_mux_state[port] & USB_PD_MUX_HPD_STATE);
 	else
 		new_mux_state = mux_state;
@@ -112,8 +113,8 @@ void virtual_hpd_update(const struct usb_mux *me, mux_state_t mux_state,
 	int port = me->usb_port;
 
 	/* Current HPD related mux status + existing USB & DP mux status */
-	mux_state_t new_mux_state = mux_state |
-			(virtual_mux_state[port] & USB_PD_MUX_USB_DP_STATE);
+	mux_state_t new_mux_state =
+		mux_state | (virtual_mux_state[port] & USB_PD_MUX_USB_DP_STATE);
 
 	virtual_mux_update_state(port, new_mux_state, ack_required);
 }
diff --git a/driver/wpc/cps8100.c b/driver/wpc/cps8100.c
index 78aa73fbfd..acfdc06a32 100644
--- a/driver/wpc/cps8100.c
+++ b/driver/wpc/cps8100.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,49 +18,61 @@
 /* Print additional data */
 #define CPS8100_DEBUG
 
-#define CPUTS(outstr)		cputs(CC_PCHG, outstr)
-#define CPRINTS(fmt, args...)	cprints(CC_PCHG, "CPS8100: " fmt, ##args)
-#define CPRINTFP(fmt, args...)	cprintf(CC_PCHG, "CPS8100: " fmt, ##args)
-#define CPRINTF(fmt, args...)	cprintf(CC_PCHG, fmt, ##args)
+#define CPUTS(outstr) cputs(CC_PCHG, outstr)
+#define CPRINTS(fmt, args...) cprints(CC_PCHG, "CPS8100: " fmt, ##args)
+#define CPRINTFP(fmt, args...) cprintf(CC_PCHG, "CPS8100: " fmt, ##args)
+#define CPRINTF(fmt, args...) cprintf(CC_PCHG, fmt, ##args)
 
 /*
  * Configuration
  */
-#define CPS8100_I2C_ADDR_H		0x31
-#define CPS8100_I2C_ADDR_L		0x30
+#define CPS8100_I2C_ADDR_H 0x31
+#define CPS8100_I2C_ADDR_L 0x30
+#define CPS8200_I2C_ADDR 0x30
 
 /* High address registers (commands?) */
-#define CPS8100_REGH_PASSWORD		0xf500
-#define CPS8100_REGH_ACCESS_MODE	0xf505
-#define CPS8100_REGH_ADDRESS		0xf503
+#define CPS8100_REGH_PASSWORD 0xf500
+#define CPS8100_REGH_ACCESS_MODE 0xf505
+#define CPS8100_REGH_ADDRESS 0xf503
 
-#define CPS8100_ACCESS_MODE_8		0x00
-#define CPS8100_ACCESS_MODE_16		0x01
-#define CPS8100_ACCESS_MODE_32		0x02
+#define CPS8100_ACCESS_MODE_8 0x00
+#define CPS8100_ACCESS_MODE_16 0x01
+#define CPS8100_ACCESS_MODE_32 0x02
+#define CPS8100_PASSWORD 0x19e5
+#define CPS8100_CHIPID 0x8100
+#define CPS8200_CHIPID 0x8200
+
+#define CPS8200_I2C_ENABLE 0x0000000E
+#define CPS8200_PASSWORD 0x00001250
 
 /* Registers */
-#define CPS8100_REG_IC_INFO		0x20000000
-#define CPS8100_REG_FW_INFO		0x20000004
-#define CPS8100_REG_FUNC_EN		0x2000003c
-#define CPS8100_REG_ALERT_INFO		0x20000158
-#define CPS8100_REG_INT_ENABLE		0x20000160
-#define CPS8100_REG_INT_FLAG		0x20000164
-
-#define CPS8100_STATUS_PROFILE(r)	(((r) & GENMASK(5, 4)) >> 4)
-#define CPS8100_STATUS_CHARGE(r)	((r) & BIT(6))
-#define CPS8100_STATUS_DEVICE(r)	((r) & BIT(7))
-#define CPS8100_STATUS_BATTERY(r)	(((r) & GENMASK(15, 8)) >> 8)
-#define CPS8100_IRQ_TYPE(r)		(((r) & GENMASK(23, 20)) >> 20)
+#define CPS8100_REG_IC_INFO 0x20000000
+#define CPS8100_REG_FW_INFO 0x20000004
+#define CPS8100_REG_FUNC_EN 0x2000003c
+#define CPS8100_REG_ALERT_INFO 0x20000158
+#define CPS8100_REG_INT_ENABLE 0x20000160
+#define CPS8100_REG_INT_FLAG 0x20000164
+
+#define CPS8200_REG_I2C_ENABLE 0xFFFFFF00
+#define CPS8200_REG_PASSWORD 0x400140FC
+
+#define CPS8100_STATUS_PROFILE(r) (((r)&GENMASK(5, 4)) >> 4)
+#define CPS8100_STATUS_CHARGE(r) ((r)&BIT(6))
+#define CPS8100_STATUS_DEVICE(r) ((r)&BIT(7))
+#define CPS8100_STATUS_BATTERY(r) (((r)&GENMASK(15, 8)) >> 8)
+#define CPS8100_IRQ_TYPE(r) (((r)&GENMASK(23, 20)) >> 20)
 
 /* Status flags in ALERT_INFO register */
-#define CPS8100_STATUS_FOD		BIT(0)
-#define CPS8100_STATUS_OCP		BIT(1)
-#define CPS8100_STATUS_OVP		BIT(2)
-#define CPS8100_STATUS_OTP		BIT(3)
-#define CPS8100_STATUS_UVP		BIT(16)
+#define CPS8100_STATUS_FOD BIT(0)
+#define CPS8100_STATUS_OCP BIT(1)
+#define CPS8100_STATUS_OVP BIT(2)
+#define CPS8100_STATUS_OTP BIT(3)
+#define CPS8100_STATUS_UVP BIT(16)
 
 /* Buffer size for i2c read & write */
-#define CPS8100_MESSAGE_BUFFER_SIZE	0x20
+#define CPS8100_MESSAGE_BUFFER_SIZE 0x20
+
+static uint32_t chip_id;
 
 /* TODO: Check datasheet how to wake up and how long it takes to wake up. */
 static const int cps8100_wake_up_delay_ms = 10;
@@ -81,22 +93,15 @@ struct cps8100_msg {
 	uint8_t data[2];
 } __packed;
 
+static int (*cps8x00_read32)(int port, uint32_t reg, uint32_t *val);
+
 /* This driver isn't compatible with big endian. */
-BUILD_ASSERT(__BYTE_ORDER__  == __ORDER_LITTLE_ENDIAN__);
-
-static const char * const cps8100_func_names[] = {
-	[0] = "DPL",
-	[1] = "OPP",
-	[2] = "OTP",
-	[3] = "OVPK",
-	[4] = "OCP",
-	[5] = "UVP",
-	[6] = "OVP",
-	[7] = "FOD",
-	[8] = "SAMSUNG",
-	[9] = "APPLE",
-	[10] = "EPP",
-	[11] = "HUAWEI",
+BUILD_ASSERT(__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__);
+
+static const char *const cps8100_func_names[] = {
+	[0] = "DPL",	 [1] = "OPP",	[2] = "OTP",  [3] = "OVPK",
+	[4] = "OCP",	 [5] = "UVP",	[6] = "OVP",  [7] = "FOD",
+	[8] = "SAMSUNG", [9] = "APPLE", [10] = "EPP", [11] = "HUAWEI",
 	[12] = "CPS",
 };
 
@@ -114,7 +119,7 @@ enum cps8100_irq_type {
 	CPS8100_IRQ_TYPE_COUNT
 };
 
-static const char * const cps8100_irq_type_names[] = {
+static const char *const cps8100_irq_type_names[] = {
 	[CPS8100_IRQ_TYPE_FOD] = "FOD",
 	[CPS8100_IRQ_TYPE_OCP] = "OCP",
 	[CPS8100_IRQ_TYPE_OVP] = "OVP",
@@ -127,7 +132,7 @@ static const char * const cps8100_irq_type_names[] = {
 	[CPS8100_IRQ_TYPE_RESET] = "RESET",
 };
 
-static const char * const cps8100_profile_names[] = {
+static const char *const cps8100_profile_names[] = {
 	[0] = "NONE",
 	[1] = "BPP",
 	[2] = "EPP",
@@ -211,14 +216,54 @@ static int cps8100_i2c_write(int port, int addr, const uint8_t *buf, size_t len)
 
 static int cps8100_set_unlock(int port)
 {
-	uint8_t buf[4];
+	const uint8_t cps8100_unlock_cmd[] = {
+		/* Password register address */
+		(CPS8100_REGH_PASSWORD >> 8) & 0xff,
+		(CPS8100_REGH_PASSWORD >> 0) & 0xff,
+		/* Password */
+		(CPS8100_PASSWORD >> 0) & 0xff,
+		(CPS8100_PASSWORD >> 8) & 0xff,
+	};
+
+	return cps8100_i2c_write(port, CPS8100_I2C_ADDR_H, cps8100_unlock_cmd,
+				 4);
+}
 
-	buf[0] = 0xf5;
-	buf[1] = 0x00;	/* Password register address */
-	buf[2] = 0xe5;
-	buf[3] = 0x19;	/* Password */
+static int cps8200_set_unlock(int port)
+{
+	const uint8_t cps8200_unlock_cmd[] = {
+		/* Password register addr */
+		(CPS8200_REG_PASSWORD >> 24) & 0xff,
+		(CPS8200_REG_PASSWORD >> 16) & 0xff,
+		(CPS8200_REG_PASSWORD >> 8) & 0xff,
+		(CPS8200_REG_PASSWORD >> 0) & 0xff,
+		/* Password */
+		(CPS8200_PASSWORD >> 0) & 0xff,
+		(CPS8200_PASSWORD >> 8) & 0xff,
+		(CPS8200_PASSWORD >> 16) & 0xff,
+		(CPS8200_PASSWORD >> 24) & 0xff,
+	};
+
+	return cps8100_i2c_write(port, CPS8200_I2C_ADDR, cps8200_unlock_cmd, 8);
+}
 
-	return cps8100_i2c_write(port, CPS8100_I2C_ADDR_H, buf, 4);
+static int cps8200_i2c_enable(int port)
+{
+	const uint8_t cps8200_i2c_enable_cmd[] = {
+		/* addr */
+		(CPS8200_REG_I2C_ENABLE >> 24) & 0xff,
+		(CPS8200_REG_I2C_ENABLE >> 16) & 0xff,
+		(CPS8200_REG_I2C_ENABLE >> 8) & 0xff,
+		(CPS8200_REG_I2C_ENABLE >> 0) & 0xff,
+		/* data */
+		(CPS8200_I2C_ENABLE >> 0) & 0xff,
+		(CPS8200_I2C_ENABLE >> 8) & 0xff,
+		(CPS8200_I2C_ENABLE >> 16) & 0xff,
+		(CPS8200_I2C_ENABLE >> 24) & 0xff,
+	};
+
+	return cps8100_i2c_write(port, CPS8200_I2C_ADDR, cps8200_i2c_enable_cmd,
+				 8);
 }
 
 static int cps8100_set_write_mode(int port, uint8_t mode)
@@ -249,17 +294,44 @@ static int cps8100_read32(int port, uint32_t reg, uint32_t *val)
 {
 	uint8_t buf[CPS8100_MESSAGE_BUFFER_SIZE];
 
-	if (cps8100_set_unlock(port) ||
-	    cps8100_set_write_mode(port, CPS8100_ACCESS_MODE_32) ||
-	    cps8100_set_high_address(port, reg))
+	if (cps8100_set_high_address(port, reg))
 		return EC_ERROR_UNKNOWN;
 
 	/* Set low 16 bits of register address and read a byte. */
 	buf[0] = (reg >> 8) & 0xff;
 	buf[1] = (reg >> 0) & 0xff;
 
-	return i2c_xfer(port, CPS8100_I2C_ADDR_L, buf, 2,
-			(void *)val, sizeof(*val));
+	return i2c_xfer(port, CPS8100_I2C_ADDR_L, buf, 2, (void *)val,
+			sizeof(*val));
+}
+
+static int cps8200_read32(int port, uint32_t reg, uint32_t *val)
+{
+	uint8_t buf[4];
+
+	buf[0] = (reg >> 24) & 0xff;
+	buf[1] = (reg >> 16) & 0xff;
+	buf[2] = (reg >> 8) & 0xff;
+	buf[3] = (reg >> 0) & 0xff;
+
+	return i2c_xfer(port, CPS8200_I2C_ADDR, buf, 4, (void *)val,
+			sizeof(*val));
+}
+
+static int cps8100_unlock(int port)
+{
+	int rv;
+
+	rv = cps8100_set_unlock(port);
+	return rv ? rv : cps8100_set_write_mode(port, CPS8100_ACCESS_MODE_32);
+}
+
+static int cps8200_unlock(int port)
+{
+	int rv;
+
+	rv = cps8200_i2c_enable(port);
+	return rv ? rv : cps8200_set_unlock(port);
 }
 
 static int cps8100_reset(struct pchg *ctx)
@@ -274,19 +346,15 @@ static int cps8100_reset(struct pchg *ctx)
 
 static int cps8100_init(struct pchg *ctx)
 {
-	uint32_t u32;
 	int port = ctx->cfg->i2c_port;
-	int rv;
 
-	rv = cps8100_read32(port, CPS8100_REG_IC_INFO, &u32);
-	if (!rv)
-		CPRINTS("IC=0x%08x", u32);
-
-	rv = cps8100_read32(port, CPS8100_REG_FW_INFO, &u32);
-	if (!rv)
-		CPRINTS("FW=0x%08x", u32);
-
-	return EC_SUCCESS;
+	/* Enable I2C, unlock and set mode */;
+	if (chip_id == CPS8100_CHIPID)
+		return cps8100_unlock(port);
+	else if (chip_id == CPS8200_CHIPID)
+		return cps8200_unlock(port);
+	else
+		return EC_ERROR_UNKNOWN;
 }
 
 static int cps8100_enable(struct pchg *ctx, bool enable)
@@ -298,7 +366,7 @@ static int cps8100_get_alert_info(struct pchg *ctx, uint32_t *reg)
 {
 	int rv;
 
-	rv = cps8100_read32(ctx->cfg->i2c_port, CPS8100_REG_ALERT_INFO, reg);
+	rv = cps8x00_read32(ctx->cfg->i2c_port, CPS8100_REG_ALERT_INFO, reg);
 	if (rv) {
 		CPRINTS("Failed to get alert info (%d)", rv);
 		return rv;
@@ -307,6 +375,63 @@ static int cps8100_get_alert_info(struct pchg *ctx, uint32_t *reg)
 	return EC_SUCCESS;
 }
 
+static int cps8100_get_chip_info(struct pchg *ctx)
+{
+	uint32_t u32;
+	int port = ctx->cfg->i2c_port;
+	int rv = EC_ERROR_UNKNOWN;
+
+	/*
+	 * CPS8100 needs 100~120ms delay, CPS8200 needs 40~50ms delay
+	 * between reset and the first access to I2C register.
+	 */
+	if (chip_id == CPS8100_CHIPID) {
+		/*
+		 * already probed but unlock again in case it's turned
+		 * off.
+		 */
+		msleep(120);
+		return cps8100_unlock(port);
+	} else if (chip_id == CPS8200_CHIPID) {
+		msleep(50);
+		return cps8200_unlock(port);
+	}
+
+	/* not probed yet, need to unlock blindly first. */
+	msleep(120);
+	if (!cps8100_unlock(port))
+		rv = cps8100_read32(port, CPS8100_REG_IC_INFO, &u32);
+	else if (!cps8200_unlock(port))
+		rv = cps8200_read32(port, CPS8100_REG_IC_INFO, &u32);
+
+	if (rv) {
+		CPRINTS("Failed to read IC info!");
+		return rv;
+	}
+
+	/* Probe */;
+	CPRINTS("IC=0x%08x", u32);
+	if ((u32 & 0xffff) == CPS8100_CHIPID) {
+		cps8x00_read32 = cps8100_read32;
+		chip_id = CPS8100_CHIPID;
+	} else if ((u32 & 0xffff) == CPS8200_CHIPID) {
+		cps8x00_read32 = cps8200_read32;
+		chip_id = CPS8200_CHIPID;
+	} else {
+		CPRINTS("Unknown chip!");
+		return EC_ERROR_UNKNOWN;
+	}
+
+	if (!cps8x00_read32(port, CPS8100_REG_FW_INFO, &u32)) {
+		CPRINTS("FW=0x%08x", u32);
+	} else {
+		CPRINTS("Failed to read FW info!");
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
 static void cps8100_print_alert_info(uint32_t reg)
 {
 	cps8100_print_irq_type_names("IRQ_TYPE: ", reg);
@@ -315,7 +440,8 @@ static void cps8100_print_alert_info(uint32_t reg)
 	CPRINTFP("Profile: %s\n",
 		 cps8100_profile_names[CPS8100_STATUS_PROFILE(reg)]);
 	CPRINTFP("%sCharging\n", CPS8100_STATUS_CHARGE(reg) ? "" : "Not ");
-	CPRINTFP("Device %sPresent\n", CPS8100_STATUS_DEVICE(reg) ? "":"Not ");
+	CPRINTFP("Device %sPresent\n",
+		 CPS8100_STATUS_DEVICE(reg) ? "" : "Not ");
 	CPRINTFP("Battery: %d%%\n", CPS8100_STATUS_BATTERY(reg));
 }
 
@@ -386,6 +512,7 @@ const struct pchg_drv cps8100_drv = {
 	.reset = cps8100_reset,
 	.init = cps8100_init,
 	.enable = cps8100_enable,
+	.get_chip_info = cps8100_get_chip_info,
 	.get_event = cps8100_get_event,
 	.get_soc = cps8100_get_soc,
 	.update_open = cps8100_update_open,
@@ -398,7 +525,7 @@ static void cps8100_dump(struct pchg *ctx)
 	uint32_t val;
 	int rv;
 
-	rv = cps8100_read32(ctx->cfg->i2c_port, CPS8100_REG_FUNC_EN, &val);
+	rv = cps8x00_read32(ctx->cfg->i2c_port, CPS8100_REG_FUNC_EN, &val);
 	if (rv == EC_SUCCESS)
 		cps8100_print_func_names("FEATURES: ", val);
 
@@ -407,7 +534,7 @@ static void cps8100_dump(struct pchg *ctx)
 		cps8100_print_alert_info(val);
 }
 
-static int cc_cps8100(int argc, char **argv)
+static int cc_cps8100(int argc, const char **argv)
 {
 	struct pchg *ctx;
 	char *end;
@@ -436,6 +563,5 @@ static int cc_cps8100(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(cps8100, cc_cps8100,
-			"<port> [reset]",
+DECLARE_CONSOLE_COMMAND(cps8100, cc_cps8100, "<port> [reset]",
 			"Print status of or reset CPS8100");
diff --git a/driver/wpc/p9221.c b/driver/wpc/p9221.c
deleted file mode 100644
index 973d991240..0000000000
--- a/driver/wpc/p9221.c
+++ /dev/null
@@ -1,808 +0,0 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * IDT P9221-R7 Wireless Power Receiver driver.
- */
-
-#include "p9221.h"
-#include "charge_manager.h"
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "power.h"
-#include "tcpm/tcpm.h"
-#include "timer.h"
-#include "usb_charge.h"
-#include "usb_pd.h"
-#include "util.h"
-#include <stdbool.h>
-#include "printf.h"
-
-#define CPRINTS(format, args...) cprints(CC_USBPD, "WPC " format, ## args)
-
-#define P9221_TX_TIMEOUT_MS		(20 * 1000*1000)
-#define P9221_DCIN_TIMEOUT_MS		(2 * 1000*1000)
-#define P9221_VRECT_TIMEOUT_MS		(2 * 1000*1000)
-#define P9221_NOTIFIER_DELAY_MS		(80*1000)
-#define P9221R7_ILIM_MAX_UA		(1600 * 1000)
-#define P9221R7_OVER_CHECK_NUM		3
-
-#define OVC_LIMIT			1
-#define OVC_THRESHOLD			1400000
-#define OVC_BACKOFF_LIMIT		900000
-#define OVC_BACKOFF_AMOUNT		100000
-
-/* P9221  parameters */
-static struct wpc_charger_info p9221_charger_info = {
-	.online = false,
-	.i2c_port = I2C_PORT_WPC,
-	.pp_buf_valid = false,
-};
-
-static struct wpc_charger_info *wpc = &p9221_charger_info;
-
-static void p9221_set_offline(void);
-
-static const uint32_t p9221_ov_set_lut[] = {
-	17000000, 20000000, 15000000, 13000000,
-	11000000, 11000000, 11000000, 11000000
-};
-
-static int p9221_reg_is_8_bit(uint16_t reg)
-{
-	switch (reg) {
-	case P9221_CHIP_REVISION_REG:
-	case P9221R7_VOUT_SET_REG:
-	case P9221R7_ILIM_SET_REG:
-	case P9221R7_CHARGE_STAT_REG:
-	case P9221R7_EPT_REG:
-	case P9221R7_SYSTEM_MODE_REG:
-	case P9221R7_COM_CHAN_RESET_REG:
-	case P9221R7_COM_CHAN_SEND_SIZE_REG:
-	case P9221R7_COM_CHAN_SEND_IDX_REG:
-	case P9221R7_COM_CHAN_RECV_SIZE_REG:
-	case P9221R7_COM_CHAN_RECV_IDX_REG:
-	case P9221R7_DEBUG_REG:
-	case P9221R7_EPP_Q_FACTOR_REG:
-	case P9221R7_EPP_TX_GUARANTEED_POWER_REG:
-	case P9221R7_EPP_TX_POTENTIAL_POWER_REG:
-	case P9221R7_EPP_TX_CAPABILITY_FLAGS_REG:
-	case P9221R7_EPP_RENEGOTIATION_REG:
-	case P9221R7_EPP_CUR_RPP_HEADER_REG:
-	case P9221R7_EPP_CUR_NEGOTIATED_POWER_REG:
-	case P9221R7_EPP_CUR_MAXIMUM_POWER_REG:
-	case P9221R7_EPP_CUR_FSK_MODULATION_REG:
-	case P9221R7_EPP_REQ_RPP_HEADER_REG:
-	case P9221R7_EPP_REQ_NEGOTIATED_POWER_REG:
-	case P9221R7_EPP_REQ_MAXIMUM_POWER_REG:
-	case P9221R7_EPP_REQ_FSK_MODULATION_REG:
-	case P9221R7_VRECT_TARGET_REG:
-	case P9221R7_VRECT_KNEE_REG:
-	case P9221R7_FOD_SECTION_REG:
-	case P9221R7_VRECT_ADJ_REG:
-	case P9221R7_ALIGN_X_ADC_REG:
-	case P9221R7_ALIGN_Y_ADC_REG:
-	case P9221R7_ASK_MODULATION_DEPTH_REG:
-	case P9221R7_OVSET_REG:
-	case P9221R7_EPP_TX_SPEC_REV_REG:
-		return true;
-	default:
-		return false;
-	}
-}
-
-static int p9221_read8(uint16_t reg, int *val)
-{
-	return i2c_read_offset16(wpc->i2c_port, P9221_R7_ADDR_FLAGS,
-				 reg, val, 1);
-}
-
-static int p9221_write8(uint16_t reg, int val)
-{
-	return i2c_write_offset16(wpc->i2c_port, P9221_R7_ADDR_FLAGS,
-				  reg, val, 1);
-}
-
-static int p9221_read16(uint16_t reg, int *val)
-{
-	return i2c_read_offset16(wpc->i2c_port, P9221_R7_ADDR_FLAGS,
-				 reg, val, 2);
-}
-
-static int p9221_write16(uint16_t reg, int val)
-{
-	return i2c_write_offset16(wpc->i2c_port, P9221_R7_ADDR_FLAGS,
-				  reg, val, 2);
-}
-
-static int p9221_block_read(uint16_t reg, uint8_t *data, int len)
-{
-	return i2c_read_offset16_block(wpc->i2c_port, P9221_R7_ADDR_FLAGS,
-				       reg, data, len);
-}
-
-static int p9221_block_write(uint16_t reg, uint8_t *data, int len)
-{
-	return i2c_write_offset16_block(wpc->i2c_port, P9221_R7_ADDR_FLAGS,
-					reg, data, len);
-}
-
-static int p9221_set_cmd_reg(uint8_t cmd)
-{
-	int cur_cmd;
-	int retry;
-	int ret;
-
-	for (retry = 0; retry < P9221_COM_CHAN_RETRIES; retry++) {
-		ret = p9221_read8(P9221_COM_REG, &cur_cmd);
-		if (ret == EC_SUCCESS && cur_cmd == 0)
-			break;
-		msleep(25);
-	}
-
-	if (retry >= P9221_COM_CHAN_RETRIES) {
-		CPRINTS("Failed to wait for cmd free %02x", cur_cmd);
-		return EC_ERROR_TIMEOUT;
-	}
-
-	ret = p9221_write8(P9221_COM_REG, cmd);
-	if (ret)
-		CPRINTS("Failed to set cmd reg %02x: %d", cmd, ret);
-
-	return ret;
-}
-
-/* Convert a register value to uV, Hz, or uA */
-static int p9221_convert_reg_r7(uint16_t reg, uint16_t raw_data, uint32_t *val)
-{
-	switch (reg) {
-	case P9221R7_ALIGN_X_ADC_REG:	/* raw */
-	case P9221R7_ALIGN_Y_ADC_REG:	/* raw */
-		*val = raw_data;
-		break;
-	case P9221R7_VOUT_ADC_REG:	/* 12-bit ADC raw */
-	case P9221R7_IOUT_ADC_REG:	/* 12-bit ADC raw */
-	case P9221R7_DIE_TEMP_ADC_REG:	/* 12-bit ADC raw */
-	case P9221R7_EXT_TEMP_REG:
-		*val = raw_data & 0xFFF;
-		break;
-	case P9221R7_VOUT_SET_REG:	/* 0.1V -> uV */
-		*val = raw_data * 100 * 1000;
-		break;
-	case P9221R7_IOUT_REG:		/* mA -> uA */
-	case P9221R7_VRECT_REG:		/* mV -> uV */
-	case P9221R7_VOUT_REG:		/* mV -> uV */
-	case P9221R7_OP_FREQ_REG:	/* kHz -> Hz */
-	case P9221R7_TX_PINGFREQ_REG:	/* kHz -> Hz */
-		*val = raw_data * 1000;
-		break;
-	case P9221R7_ILIM_SET_REG:	/* 100mA -> uA, 200mA offset */
-		*val = ((raw_data * 100) + 200) * 1000;
-		break;
-	case P9221R7_OVSET_REG:		/* uV */
-		raw_data &= P9221R7_OVSET_MASK;
-		*val = p9221_ov_set_lut[raw_data];
-		break;
-	default:
-		return -2;
-	}
-
-	return 0;
-}
-
-static int p9221_reg_read_converted(uint16_t reg, uint32_t *val)
-{
-	int ret;
-	int data;
-
-	if (p9221_reg_is_8_bit(reg))
-		ret = p9221_read8(reg, &data);
-	else
-		ret = p9221_read16(reg, &data);
-
-	if (ret)
-		return ret;
-
-	return p9221_convert_reg_r7(reg, data, val);
-}
-
-static int p9221_is_online(void)
-{
-	int chip_id;
-
-	if (p9221_read16(P9221_CHIP_ID_REG, &chip_id)
-			|| chip_id != P9221_CHIP_ID)
-		return false;
-	else
-		return true;
-}
-
-int wpc_chip_is_online(void)
-{
-	return p9221_is_online();
-}
-
-
-void p9221_interrupt(enum gpio_signal signal)
-{
-	task_wake(TASK_ID_WPC);
-}
-
-static int p9221r7_clear_interrupts(uint16_t mask)
-{
-	int ret;
-
-	ret = p9221_write16(P9221R7_INT_CLEAR_REG, mask);
-	if (ret) {
-		CPRINTS("Failed to clear INT reg: %d", ret);
-		return ret;
-	}
-
-	ret = p9221_set_cmd_reg(P9221_COM_CLEAR_INT_MASK);
-	if (ret)
-		CPRINTS("Failed to reset INT: %d", ret);
-
-	return ret;
-}
-
-/*
- * Enable interrupts on the P9221 R7, note we don't really need to disable
- * interrupts since when the device goes out of field, the P9221 is reset.
- */
-static int p9221_enable_interrupts_r7(void)
-{
-	uint16_t mask = 0;
-	int ret;
-
-	CPRINTS("Enable interrupts");
-
-	mask = P9221R7_STAT_LIMIT_MASK | P9221R7_STAT_CC_MASK
-		| P9221_STAT_VRECT;
-
-	p9221r7_clear_interrupts(mask);
-
-	ret = p9221_write8(P9221_INT_ENABLE_REG, mask);
-	if (ret)
-		CPRINTS("Failed to enable INTs: %d", ret);
-	return ret;
-}
-
-static int p9221_send_csp(uint8_t status)
-{
-	int ret;
-
-	CPRINTS("Send CSP=%d", status);
-	mutex_lock(&wpc->cmd_lock);
-
-	ret = p9221_write8(P9221R7_CHARGE_STAT_REG, status);
-	if (ret == EC_SUCCESS)
-		ret = p9221_set_cmd_reg(P9221R7_COM_SENDCSP);
-
-	mutex_unlock(&wpc->cmd_lock);
-	return ret;
-}
-
-static int p9221_send_eop(uint8_t reason)
-{
-	int rv;
-
-	CPRINTS("Send EOP reason=%d", reason);
-	mutex_lock(&wpc->cmd_lock);
-
-	rv = p9221_write8(P9221R7_EPT_REG, reason);
-	if (rv == EC_SUCCESS)
-		rv = p9221_set_cmd_reg(P9221R7_COM_SENDEPT);
-
-	mutex_unlock(&wpc->cmd_lock);
-	return rv;
-}
-
-static void print_current_samples(uint32_t *iout_val, int count)
-{
-	int i;
-	char temp[P9221R7_OVER_CHECK_NUM * 9 + 1] = { 0 };
-
-	for (i = 0; i < count ; i++)
-		snprintf(temp + i * 9, sizeof(temp) - i * 9,
-			  "%08x ", iout_val[i]);
-	CPRINTS("OVER IOUT_SAMPLES: %s", temp);
-}
-
-
-/*
- * Number of times to poll the status to see if the current limit condition
- * was transient or not.
- */
-static void p9221_limit_handler_r7(uint16_t orign_irq_src)
-{
-	uint8_t reason;
-	int i;
-	int ret;
-	int ovc_count = 0;
-	uint32_t iout_val[P9221R7_OVER_CHECK_NUM] = { 0 };
-	int irq_src = (int)orign_irq_src;
-
-	CPRINTS("OVER INT: %02x", irq_src);
-
-	if (irq_src & P9221R7_STAT_OVV) {
-		reason = P9221_EOP_OVER_VOLT;
-		goto send_eop;
-	}
-
-	if (irq_src & P9221R7_STAT_OVT) {
-		reason = P9221_EOP_OVER_TEMP;
-		goto send_eop;
-	}
-
-	if ((irq_src & P9221R7_STAT_UV) && !(irq_src & P9221R7_STAT_OVC))
-		return;
-
-	reason = P9221_EOP_OVER_CURRENT;
-	for (i = 0; i < P9221R7_OVER_CHECK_NUM; i++) {
-		ret = p9221r7_clear_interrupts(
-				irq_src & P9221R7_STAT_LIMIT_MASK);
-		msleep(50);
-		if (ret)
-			continue;
-
-		ret = p9221_reg_read_converted(P9221R7_IOUT_REG, &iout_val[i]);
-		if (ret) {
-			CPRINTS("Failed to read IOUT[%d]: %d", i, ret);
-			continue;
-		} else if (iout_val[i] > OVC_THRESHOLD) {
-			ovc_count++;
-		}
-
-		ret = p9221_read16(P9221_STATUS_REG, &irq_src);
-		if (ret) {
-			CPRINTS("Failed to read status: %d", ret);
-			continue;
-		}
-
-		if ((irq_src & P9221R7_STAT_OVC) == 0) {
-			print_current_samples(iout_val, i + 1);
-			CPRINTS("OVER condition %04x cleared after %d tries",
-				irq_src, i);
-			return;
-		}
-
-		CPRINTS("OVER status is still %04x, retry", irq_src);
-	}
-
-	if (ovc_count < OVC_LIMIT) {
-		print_current_samples(iout_val, P9221R7_OVER_CHECK_NUM);
-		CPRINTS("ovc_threshold=%d, ovc_count=%d, ovc_limit=%d",
-			OVC_THRESHOLD, ovc_count, OVC_LIMIT);
-		return;
-	}
-
-send_eop:
-	CPRINTS("OVER is %04x, sending EOP %d", irq_src, reason);
-
-	ret = p9221_send_eop(reason);
-	if (ret)
-		CPRINTS("Failed to send EOP %d: %d", reason, ret);
-}
-
-static void p9221_abort_transfers(void)
-{
-	wpc->tx_busy = false;
-	wpc->tx_done = true;
-	wpc->rx_done = true;
-	wpc->rx_len = 0;
-}
-
-/* Handler for r7 and R7 chips */
-static void p9221r7_irq_handler(uint16_t irq_src)
-{
-	int res;
-
-	if (irq_src & P9221R7_STAT_LIMIT_MASK)
-		p9221_limit_handler_r7(irq_src);
-
-	/* Receive complete */
-	if (irq_src & P9221R7_STAT_CCDATARCVD) {
-		int rxlen = 0;
-
-		res = p9221_read8(P9221R7_COM_CHAN_RECV_SIZE_REG, &rxlen);
-		if (res)
-			CPRINTS("Failed to read len: %d", res);
-
-		if (rxlen) {
-			res = p9221_block_read(P9221R7_DATA_RECV_BUF_START,
-					       wpc->rx_buf, rxlen);
-			if (res) {
-				CPRINTS("Failed to read CC data: %d", res);
-				rxlen = 0;
-			}
-
-			wpc->rx_len = rxlen;
-			wpc->rx_done = true;
-		}
-	}
-
-	/* Send complete */
-	if (irq_src & P9221R7_STAT_CCSENDBUSY) {
-		wpc->tx_busy = false;
-		wpc->tx_done = true;
-	}
-
-	/* Proprietary packet */
-	if (irq_src & P9221R7_STAT_PPRCVD) {
-		res = p9221_block_read(P9221R7_DATA_RECV_BUF_START,
-				       wpc->pp_buf, sizeof(wpc->pp_buf));
-		if (res) {
-			CPRINTS("Failed to read PP: %d", res);
-			wpc->pp_buf_valid = false;
-			return;
-		}
-
-		/* We only care about PP which come with 0x4F header */
-		wpc->pp_buf_valid = (wpc->pp_buf[0] == 0x4F);
-
-		hexdump(wpc->pp_buf, sizeof(wpc->pp_buf));
-	}
-
-	/* CC Reset complete */
-	if (irq_src & P9221R7_STAT_CCRESET)
-		p9221_abort_transfers();
-}
-
-static int p9221_is_epp(void)
-{
-	int ret, reg;
-	uint32_t vout_uv;
-
-	if (p9221_read8(P9221R7_SYSTEM_MODE_REG, &reg) == EC_SUCCESS)
-		return reg & P9221R7_SYSTEM_MODE_EXTENDED_MASK;
-
-	/* Check based on power supply voltage */
-	ret = p9221_reg_read_converted(P9221R7_VOUT_ADC_REG, &vout_uv);
-	if (ret) {
-		CPRINTS("Failed to read VOUT_ADC: %d", ret);
-		return false;
-	}
-
-	CPRINTS("Voltage is %duV", vout_uv);
-	if (vout_uv > P9221_EPP_THRESHOLD_UV)
-		return true;
-
-	return false;
-}
-
-static void p9221_config_fod(void)
-{
-
-	int epp;
-	uint8_t *fod;
-	int fod_len;
-	int ret;
-	int retries = 3;
-
-	CPRINTS("Config FOD");
-
-	epp = p9221_is_epp();
-	fod_len = epp ? board_get_epp_fod(&fod) : board_get_fod(&fod);
-	if (!fod_len || !fod) {
-		CPRINTS("FOD data not found");
-		return;
-	}
-
-	while (retries) {
-		uint8_t fod_read[fod_len];
-
-		CPRINTS("Writing %s FOD (n=%d try=%d)",
-			epp ? "EPP" : "BPP", fod_len, retries);
-
-		ret = p9221_block_write(P9221R7_FOD_REG, fod, fod_len);
-		if (ret)
-			goto no_fod;
-
-		/* Verify the FOD has been written properly */
-		ret = p9221_block_read(P9221R7_FOD_REG, fod_read, fod_len);
-		if (ret)
-			goto no_fod;
-
-		if (memcmp(fod, fod_read, fod_len) == 0)
-			return;
-
-		hexdump(fod_read, fod_len);
-
-		retries--;
-		msleep(100);
-	}
-
-no_fod:
-	CPRINTS("Failed to set FOD. retries:%d ret:%d", retries, ret);
-}
-
-static void p9221_set_online(void)
-{
-	int ret;
-
-	CPRINTS("Set online");
-
-	wpc->online = true;
-
-	wpc->tx_busy = false;
-	wpc->tx_done = true;
-	wpc->rx_done = false;
-	wpc->charge_supplier = CHARGE_SUPPLIER_WPC_BPP;
-
-	ret = p9221_enable_interrupts_r7();
-	if (ret)
-		CPRINTS("Failed to enable INT: %d", ret);
-
-	/* NOTE: depends on _is_epp() which is not valid until DC_IN */
-	p9221_config_fod();
-}
-
-static void p9221_vbus_check_timeout(void)
-{
-	CPRINTS("Timeout VBUS, online=%d", wpc->online);
-	if (wpc->online)
-		p9221_set_offline();
-
-}
-DECLARE_DEFERRED(p9221_vbus_check_timeout);
-
-static void p9221_set_offline(void)
-{
-	CPRINTS("Set offline");
-
-	wpc->online = false;
-	/* Reset PP buf so we can get a new serial number next time around */
-	wpc->pp_buf_valid = false;
-
-	p9221_abort_transfers();
-
-	hook_call_deferred(&p9221_vbus_check_timeout_data, -1);
-}
-
-/* P9221_NOTIFIER_DELAY_MS from VRECTON */
-static int p9221_notifier_check_det(void)
-{
-	if (wpc->online)
-		goto done;
-
-	/* send out a FOD but is_epp() is still invalid */
-	p9221_set_online();
-
-	/* Give the vbus 2 seconds to come up. */
-	CPRINTS("Waiting VBUS");
-	hook_call_deferred(&p9221_vbus_check_timeout_data, -1);
-	hook_call_deferred(&p9221_vbus_check_timeout_data,
-			   P9221_DCIN_TIMEOUT_MS);
-
-done:
-	wpc->p9221_check_det = false;
-	return 0;
-}
-
-static int p9221_get_charge_supplier(void)
-{
-	if (!wpc->online)
-		return EC_ERROR_UNKNOWN;
-
-	if (p9221_is_epp()) {
-		uint32_t tx_id;
-		int txmf_id;
-		int ret;
-
-		wpc->charge_supplier = CHARGE_SUPPLIER_WPC_EPP;
-
-		ret = p9221_read16(P9221R7_EPP_TX_MFG_CODE_REG, &txmf_id);
-		if (ret || txmf_id != P9221_GPP_TX_MF_ID)
-			return ret;
-
-		ret = p9221_block_read(P9221R7_PROP_TX_ID_REG,
-				       (uint8_t *) &tx_id,
-				       P9221R7_PROP_TX_ID_SIZE);
-		if (ret)
-			return ret;
-
-		if (tx_id & P9221R7_PROP_TX_ID_GPP_MASK)
-			wpc->charge_supplier = CHARGE_SUPPLIER_WPC_GPP;
-
-		CPRINTS("txmf_id=0x%04x tx_id=0x%08x supplier=%d",
-			txmf_id, tx_id, wpc->charge_supplier);
-	} else {
-		wpc->charge_supplier = CHARGE_SUPPLIER_WPC_BPP;
-		CPRINTS("supplier=%d", wpc->charge_supplier);
-	}
-
-	return EC_SUCCESS;
-}
-
-static int p9221_get_icl(int charge_supplier)
-{
-	switch (charge_supplier) {
-	case CHARGE_SUPPLIER_WPC_EPP:
-	case CHARGE_SUPPLIER_WPC_GPP:
-		return P9221_DC_ICL_EPP_MA;
-	case CHARGE_SUPPLIER_WPC_BPP:
-	default:
-		return P9221_DC_ICL_BPP_MA;
-	}
-}
-
-static int p9221_get_ivl(int charge_supplier)
-{
-	switch (charge_supplier) {
-	case CHARGE_SUPPLIER_WPC_EPP:
-	case CHARGE_SUPPLIER_WPC_GPP:
-		return P9221_DC_IVL_EPP_MV;
-	case CHARGE_SUPPLIER_WPC_BPP:
-	default:
-		return P9221_DC_IVL_BPP_MV;
-	}
-}
-
-static void p9221_update_charger(int type, struct charge_port_info *chg)
-{
-	if (!chg)
-		charge_manager_update_dualrole(0, CAP_UNKNOWN);
-	else
-		charge_manager_update_dualrole(0, CAP_DEDICATED);
-
-	charge_manager_update_charge(type, 0, chg);
-}
-
-static int p9221_reg_write_converted_r7(uint16_t reg, uint32_t val)
-{
-	int ret = 0;
-	uint16_t data;
-	int i;
-	/* Do the appropriate conversion */
-	switch (reg) {
-	case P9221R7_ILIM_SET_REG:
-		/* uA -> 0.1A, offset 0.2A */
-		if ((val < 200000) || (val > 1600000))
-			return -EC_ERROR_INVAL;
-		data = (val / (100 * 1000)) - 2;
-		break;
-	case P9221R7_VOUT_SET_REG:
-		/* uV -> 0.1V */
-		val /= 1000;
-		if (val < 3500 || val > 9000)
-			return -EC_ERROR_INVAL;
-		data = val / 100;
-		break;
-	case P9221R7_OVSET_REG:
-		/* uV */
-		for (i = 0; i < ARRAY_SIZE(p9221_ov_set_lut); i++) {
-			if (val == p9221_ov_set_lut[i])
-				break;
-		}
-		if (i == ARRAY_SIZE(p9221_ov_set_lut))
-			return -EC_ERROR_INVAL;
-		data = i;
-		break;
-	default:
-		return -EC_ERROR_INVAL;
-	}
-	if (p9221_reg_is_8_bit(reg))
-		ret = p9221_write8(reg, data);
-	else
-		ret = p9221_write16(reg, data);
-	return ret;
-}
-
-static int p9221_set_dc_icl(void)
-{
-	/* Increase the IOUT limit */
-	if (p9221_reg_write_converted_r7(P9221R7_ILIM_SET_REG,
-					 P9221R7_ILIM_MAX_UA))
-		CPRINTS("%s set rx_iout limit fail.", __func__);
-
-	return EC_SUCCESS;
-}
-
-
-static void p9221_notifier_check_vbus(void)
-{
-	struct charge_port_info chg;
-
-	wpc->p9221_check_vbus = false;
-
-	CPRINTS("%s online:%d vbus:%d", __func__, wpc->online,
-		wpc->vbus_status);
-
-	/*
-	 * We now have confirmation from DC_IN, kill the timer, p9221_online
-	 * will be set by this function.
-	 */
-	hook_call_deferred(&p9221_vbus_check_timeout_data, -1);
-
-	if (wpc->vbus_status) {
-		/* WPC VBUS on ,Always write FOD, check dc_icl, send CSP */
-		p9221_set_dc_icl();
-		p9221_config_fod();
-
-		p9221_send_csp(1);
-
-		/* when wpc vbus attached after 2s, set wpc online */
-		if (!wpc->online)
-			p9221_set_online();
-
-		/* WPC VBUS on , update charge voltage and current */
-		p9221_get_charge_supplier();
-		chg.voltage = p9221_get_ivl(wpc->charge_supplier);
-		chg.current = p9221_get_icl(wpc->charge_supplier);
-
-		p9221_update_charger(wpc->charge_supplier, &chg);
-	} else {
-		/*
-		 * Vbus detached, set wpc offline and update wpc charge voltage
-		 * and current to zero.
-		 */
-		if (wpc->online) {
-			p9221_set_offline();
-			p9221_update_charger(wpc->charge_supplier, NULL);
-		}
-	}
-
-	CPRINTS("check_vbus changed on:%d vbus:%d", wpc->online,
-		wpc->vbus_status);
-
-}
-
-static void p9221_detect_work(void)
-{
-
-	CPRINTS("%s online:%d check_vbus:%d check_det:%d vbus:%d", __func__,
-		wpc->online, wpc->p9221_check_vbus, wpc->p9221_check_det,
-		wpc->vbus_status);
-
-	/* Step 1 */
-	if (wpc->p9221_check_det)
-		p9221_notifier_check_det();
-
-	/* Step 2 */
-	if (wpc->p9221_check_vbus)
-		p9221_notifier_check_vbus();
-
-}
-DECLARE_DEFERRED(p9221_detect_work);
-
-void p9221_notify_vbus_change(int vbus)
-{
-	wpc->p9221_check_vbus = true;
-	wpc->vbus_status = vbus;
-	hook_call_deferred(&p9221_detect_work_data, P9221_NOTIFIER_DELAY_MS);
-}
-
-void wireless_power_charger_task(void *u)
-{
-	while (1) {
-		int ret, irq_src;
-		task_wait_event(-1);
-
-		ret = p9221_read16(P9221_INT_REG, &irq_src);
-		if (ret) {
-			CPRINTS("Failed to read INT REG");
-			continue;
-		}
-
-		CPRINTS("INT SRC 0x%04x", irq_src);
-
-		if (p9221r7_clear_interrupts(irq_src))
-			continue;
-
-		if (irq_src & P9221_STAT_VRECT) {
-			CPRINTS("VRECTON, online=%d", wpc->online);
-			if (!wpc->online) {
-				wpc->p9221_check_det = true;
-				hook_call_deferred(&p9221_detect_work_data,
-						   P9221_NOTIFIER_DELAY_MS);
-			}
-		}
-
-		p9221r7_irq_handler(irq_src);
-	}
-}
diff --git a/driver/wpc/p9221.h b/driver/wpc/p9221.h
index 0bb0571b38..53dcc57aa7 100644
--- a/driver/wpc/p9221.h
+++ b/driver/wpc/p9221.h
@@ -1,9 +1,8 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-
 /*
  * IDT P9221-R7 Wireless Power Receiver driver definitions.
  */
@@ -16,248 +15,243 @@
 #include "charge_manager.h"
 #include "task.h"
 
-
 /* ========== Variant-specific configuration ============ */
 
-#define P9221_R7_ADDR_FLAGS			0x61
+#define P9221_R7_ADDR_FLAGS 0x61
 
 /*
  * P9221 common registers
  */
-#define P9221_CHIP_ID_REG			0x00
-#define P9221_CHIP_ID				0x9220
-#define P9221_CHIP_REVISION_REG			0x02
-#define P9221_CUSTOMER_ID_REG			0x03
-#define P9221R7_CUSTOMER_ID_VAL			0x05
-#define P9221_OTP_FW_MAJOR_REV_REG		0x04
-#define P9221_OTP_FW_MINOR_REV_REG		0x06
-#define P9221_OTP_FW_DATE_REG			0x08
-#define P9221_OTP_FW_DATE_SIZE			12
-#define P9221_OTP_FW_TIME_REG			0x14
-#define P9221_OTP_FW_TIME_SIZE			8
-#define P9221_SRAM_FW_MAJOR_REV_REG		0x1C
-#define P9221_SRAM_FW_MINOR_REV_REG		0x1E
-#define P9221_SRAM_FW_DATE_REG			0x20
-#define P9221_SRAM_FW_DATE_SIZE			12
-#define P9221_SRAM_FW_TIME_REG			0x2C
-#define P9221_SRAM_FW_TIME_SIZE			8
-#define P9221_STATUS_REG			0x34
-#define P9221_INT_REG				0x36
-#define P9221_INT_MASK				0xF7
-#define P9221_INT_ENABLE_REG			0x38
-#define P9221_GPP_TX_MF_ID			0x0072
+#define P9221_CHIP_ID_REG 0x00
+#define P9221_CHIP_ID 0x9220
+#define P9221_CHIP_REVISION_REG 0x02
+#define P9221_CUSTOMER_ID_REG 0x03
+#define P9221R7_CUSTOMER_ID_VAL 0x05
+#define P9221_OTP_FW_MAJOR_REV_REG 0x04
+#define P9221_OTP_FW_MINOR_REV_REG 0x06
+#define P9221_OTP_FW_DATE_REG 0x08
+#define P9221_OTP_FW_DATE_SIZE 12
+#define P9221_OTP_FW_TIME_REG 0x14
+#define P9221_OTP_FW_TIME_SIZE 8
+#define P9221_SRAM_FW_MAJOR_REV_REG 0x1C
+#define P9221_SRAM_FW_MINOR_REV_REG 0x1E
+#define P9221_SRAM_FW_DATE_REG 0x20
+#define P9221_SRAM_FW_DATE_SIZE 12
+#define P9221_SRAM_FW_TIME_REG 0x2C
+#define P9221_SRAM_FW_TIME_SIZE 8
+#define P9221_STATUS_REG 0x34
+#define P9221_INT_REG 0x36
+#define P9221_INT_MASK 0xF7
+#define P9221_INT_ENABLE_REG 0x38
+#define P9221_GPP_TX_MF_ID 0x0072
 
 /*
  * P9221 Rx registers (x != 5)
  */
-#define P9221_CHARGE_STAT_REG			0x3A
-#define P9221_EPT_REG				0x3B
-#define P9221_VOUT_ADC_REG			0x3C
-#define P9221_VOUT_ADC_MASK			0x0FFF
-#define P9221_VOUT_SET_REG			0x3E
-#define P9221_MAX_VOUT_SET_MV_DEFAULT		9000
-#define P9221_VRECT_ADC_REG			0x40
-#define P9221_VRECT_ADC_MASK			0x0FFF
-#define P9221_OVSET_REG				0x42
-#define P9221_OVSET_MASK			0x70
-#define P9221_OVSET_SHIFT			4
-#define P9221_RX_IOUT_REG			0x44
-#define P9221_DIE_TEMP_ADC_REG			0x46
-#define P9221_DIE_TEMP_ADC_MASK			0x0FFF
-#define P9221_OP_FREQ_REG			0x48
-#define P9221_ILIM_SET_REG			0x4A
-#define P9221_ALIGN_X_ADC_REG			0x4B
-#define P9221_ALIGN_Y_ADC_REG			0x4C
-#define P9221_OP_MODE_REG			0x4D
-#define P9221_COM_REG				0x4E
-#define P9221_FW_SWITCH_KEY_REG			0x4F
-#define P9221_INT_CLEAR_REG			0x56
-#define P9221_RXID_REG				0x5C
-#define P9221_RXID_LEN				6
-#define P9221_MPREQ_REG				0x5C
-#define P9221_MPREQ_LEN				6
-#define P9221_FOD_REG				0x68
-#define P9221_NUM_FOD				16
-#define P9221_RX_RAWIOUT_REG			0x7A
-#define P9221_RX_RAWIOUT_MASK			0xFFF
-#define P9221_PMA_AD_REG			0x7C
-#define P9221_RX_PINGFREQ_REG			0xFC
-#define P9221_RX_PINGFREQ_MASK			0xFFF
-#define P9221_LAST_REG				0xFF
+#define P9221_CHARGE_STAT_REG 0x3A
+#define P9221_EPT_REG 0x3B
+#define P9221_VOUT_ADC_REG 0x3C
+#define P9221_VOUT_ADC_MASK 0x0FFF
+#define P9221_VOUT_SET_REG 0x3E
+#define P9221_MAX_VOUT_SET_MV_DEFAULT 9000
+#define P9221_VRECT_ADC_REG 0x40
+#define P9221_VRECT_ADC_MASK 0x0FFF
+#define P9221_OVSET_REG 0x42
+#define P9221_OVSET_MASK 0x70
+#define P9221_OVSET_SHIFT 4
+#define P9221_RX_IOUT_REG 0x44
+#define P9221_DIE_TEMP_ADC_REG 0x46
+#define P9221_DIE_TEMP_ADC_MASK 0x0FFF
+#define P9221_OP_FREQ_REG 0x48
+#define P9221_ILIM_SET_REG 0x4A
+#define P9221_ALIGN_X_ADC_REG 0x4B
+#define P9221_ALIGN_Y_ADC_REG 0x4C
+#define P9221_OP_MODE_REG 0x4D
+#define P9221_COM_REG 0x4E
+#define P9221_FW_SWITCH_KEY_REG 0x4F
+#define P9221_INT_CLEAR_REG 0x56
+#define P9221_RXID_REG 0x5C
+#define P9221_RXID_LEN 6
+#define P9221_MPREQ_REG 0x5C
+#define P9221_MPREQ_LEN 6
+#define P9221_FOD_REG 0x68
+#define P9221_NUM_FOD 16
+#define P9221_RX_RAWIOUT_REG 0x7A
+#define P9221_RX_RAWIOUT_MASK 0xFFF
+#define P9221_PMA_AD_REG 0x7C
+#define P9221_RX_PINGFREQ_REG 0xFC
+#define P9221_RX_PINGFREQ_MASK 0xFFF
+#define P9221_LAST_REG 0xFF
 
 /*
  * P9221R7 unique registers
  */
-#define P9221R7_INT_CLEAR_REG			0x3A
-#define P9221R7_VOUT_SET_REG			0x3C
-#define P9221R7_ILIM_SET_REG			0x3D
-#define P9221R7_ILIM_SET_MAX			0x0E	/* 0x0E = 1.6A */
-#define P9221R7_CHARGE_STAT_REG			0x3E
-#define P9221R7_EPT_REG				0x3F
-#define P9221R7_VRECT_REG			0x40
-#define P9221R7_VOUT_REG			0x42
-#define P9221R7_IOUT_REG			0x44
-#define P9221R7_OP_FREQ_REG			0x48
-#define P9221R7_SYSTEM_MODE_REG			0x4C
-#define P9221R7_COM_CHAN_RESET_REG		0x50
-#define P9221R7_COM_CHAN_SEND_SIZE_REG		0x58
-#define P9221R7_COM_CHAN_SEND_IDX_REG		0x59
-#define P9221R7_COM_CHAN_RECV_SIZE_REG		0x5A
-#define P9221R7_COM_CHAN_RECV_IDX_REG		0x5B
-#define P9221R7_VRECT_ADC_REG			0x60
-#define P9221R7_VOUT_ADC_REG			0x62
-#define P9221R7_VOUT_ADC_MASK			0xFFF
-#define P9221R7_IOUT_ADC_REG			0x64
-#define P9221R7_IOUT_ADC_MASK			0xFFF
-#define P9221R7_DIE_TEMP_ADC_REG		0x66
-#define P9221R7_DIE_TEMP_ADC_MASK		0xFFF
-#define P9221R7_AC_PERIOD_REG			0x68
-#define P9221R7_TX_PINGFREQ_REG			0x6A
-#define P9221R7_EXT_TEMP_REG			0x6C
-#define P9221R7_EXT_TEMP_MASK			0xFFF
-#define P9221R7_FOD_REG				0x70
-#define P9221R7_NUM_FOD				16
-#define P9221R7_DEBUG_REG			0x80
-#define P9221R7_EPP_Q_FACTOR_REG		0x83
-#define P9221R7_EPP_TX_GUARANTEED_POWER_REG	0x84
-#define P9221R7_EPP_TX_POTENTIAL_POWER_REG	0x85
-#define P9221R7_EPP_TX_CAPABILITY_FLAGS_REG	0x86
-#define P9221R7_EPP_RENEGOTIATION_REG		0x87
-#define P9221R7_EPP_CUR_RPP_HEADER_REG		0x88
-#define P9221R7_EPP_CUR_NEGOTIATED_POWER_REG	0x89
-#define P9221R7_EPP_CUR_MAXIMUM_POWER_REG	0x8A
-#define P9221R7_EPP_CUR_FSK_MODULATION_REG	0x8B
-#define P9221R7_EPP_REQ_RPP_HEADER_REG		0x8C
-#define P9221R7_EPP_REQ_NEGOTIATED_POWER_REG	0x8D
-#define P9221R7_EPP_REQ_MAXIMUM_POWER_REG	0x8E
-#define P9221R7_EPP_REQ_FSK_MODULATION_REG	0x8F
-#define P9221R7_VRECT_TARGET_REG		0x90
-#define P9221R7_VRECT_KNEE_REG			0x92
-#define P9221R7_VRECT_CORRECTION_FACTOR_REG	0x93
-#define P9221R7_VRECT_MAX_CORRECTION_FACTOR_REG	0x94
-#define P9221R7_VRECT_MIN_CORRECTION_FACTOR_REG	0x96
-#define P9221R7_FOD_SECTION_REG			0x99
-#define P9221R7_VRECT_ADJ_REG			0x9E
-#define P9221R7_ALIGN_X_ADC_REG			0xA0
-#define P9221R7_ALIGN_Y_ADC_REG			0xA1
-#define P9221R7_ASK_MODULATION_DEPTH_REG	0xA2
-#define P9221R7_OVSET_REG			0xA3
-#define P9221R7_OVSET_MASK			0x7
-#define P9221R7_EPP_TX_SPEC_REV_REG		0xA9
-#define P9221R7_EPP_TX_MFG_CODE_REG		0xAA
-#define P9221R7_GP0_RESET_VOLT_REG		0xAC
-#define P9221R7_GP1_RESET_VOLT_REG		0xAE
-#define P9221R7_GP2_RESET_VOLT_REG		0xB0
-#define P9221R7_GP3_RESET_VOLT_REG		0xB2
-#define P9221R7_PROP_TX_ID_REG			0xB4
-#define P9221R7_PROP_TX_ID_SIZE			4
-#define P9221R7_DATA_SEND_BUF_START		0x100
-#define P9221R7_DATA_SEND_BUF_SIZE		0x80
-#define P9221R7_DATA_RECV_BUF_START		0x180
-#define P9221R7_DATA_RECV_BUF_SIZE		0x80
-#define P9221R7_MAX_PP_BUF_SIZE			16
-#define P9221R7_LAST_REG			0x1FF
+#define P9221R7_INT_CLEAR_REG 0x3A
+#define P9221R7_VOUT_SET_REG 0x3C
+#define P9221R7_ILIM_SET_REG 0x3D
+#define P9221R7_ILIM_SET_MAX 0x0E /* 0x0E = 1.6A */
+#define P9221R7_CHARGE_STAT_REG 0x3E
+#define P9221R7_EPT_REG 0x3F
+#define P9221R7_VRECT_REG 0x40
+#define P9221R7_VOUT_REG 0x42
+#define P9221R7_IOUT_REG 0x44
+#define P9221R7_OP_FREQ_REG 0x48
+#define P9221R7_SYSTEM_MODE_REG 0x4C
+#define P9221R7_COM_CHAN_RESET_REG 0x50
+#define P9221R7_COM_CHAN_SEND_SIZE_REG 0x58
+#define P9221R7_COM_CHAN_SEND_IDX_REG 0x59
+#define P9221R7_COM_CHAN_RECV_SIZE_REG 0x5A
+#define P9221R7_COM_CHAN_RECV_IDX_REG 0x5B
+#define P9221R7_VRECT_ADC_REG 0x60
+#define P9221R7_VOUT_ADC_REG 0x62
+#define P9221R7_VOUT_ADC_MASK 0xFFF
+#define P9221R7_IOUT_ADC_REG 0x64
+#define P9221R7_IOUT_ADC_MASK 0xFFF
+#define P9221R7_DIE_TEMP_ADC_REG 0x66
+#define P9221R7_DIE_TEMP_ADC_MASK 0xFFF
+#define P9221R7_AC_PERIOD_REG 0x68
+#define P9221R7_TX_PINGFREQ_REG 0x6A
+#define P9221R7_EXT_TEMP_REG 0x6C
+#define P9221R7_EXT_TEMP_MASK 0xFFF
+#define P9221R7_FOD_REG 0x70
+#define P9221R7_NUM_FOD 16
+#define P9221R7_DEBUG_REG 0x80
+#define P9221R7_EPP_Q_FACTOR_REG 0x83
+#define P9221R7_EPP_TX_GUARANTEED_POWER_REG 0x84
+#define P9221R7_EPP_TX_POTENTIAL_POWER_REG 0x85
+#define P9221R7_EPP_TX_CAPABILITY_FLAGS_REG 0x86
+#define P9221R7_EPP_RENEGOTIATION_REG 0x87
+#define P9221R7_EPP_CUR_RPP_HEADER_REG 0x88
+#define P9221R7_EPP_CUR_NEGOTIATED_POWER_REG 0x89
+#define P9221R7_EPP_CUR_MAXIMUM_POWER_REG 0x8A
+#define P9221R7_EPP_CUR_FSK_MODULATION_REG 0x8B
+#define P9221R7_EPP_REQ_RPP_HEADER_REG 0x8C
+#define P9221R7_EPP_REQ_NEGOTIATED_POWER_REG 0x8D
+#define P9221R7_EPP_REQ_MAXIMUM_POWER_REG 0x8E
+#define P9221R7_EPP_REQ_FSK_MODULATION_REG 0x8F
+#define P9221R7_VRECT_TARGET_REG 0x90
+#define P9221R7_VRECT_KNEE_REG 0x92
+#define P9221R7_VRECT_CORRECTION_FACTOR_REG 0x93
+#define P9221R7_VRECT_MAX_CORRECTION_FACTOR_REG 0x94
+#define P9221R7_VRECT_MIN_CORRECTION_FACTOR_REG 0x96
+#define P9221R7_FOD_SECTION_REG 0x99
+#define P9221R7_VRECT_ADJ_REG 0x9E
+#define P9221R7_ALIGN_X_ADC_REG 0xA0
+#define P9221R7_ALIGN_Y_ADC_REG 0xA1
+#define P9221R7_ASK_MODULATION_DEPTH_REG 0xA2
+#define P9221R7_OVSET_REG 0xA3
+#define P9221R7_OVSET_MASK 0x7
+#define P9221R7_EPP_TX_SPEC_REV_REG 0xA9
+#define P9221R7_EPP_TX_MFG_CODE_REG 0xAA
+#define P9221R7_GP0_RESET_VOLT_REG 0xAC
+#define P9221R7_GP1_RESET_VOLT_REG 0xAE
+#define P9221R7_GP2_RESET_VOLT_REG 0xB0
+#define P9221R7_GP3_RESET_VOLT_REG 0xB2
+#define P9221R7_PROP_TX_ID_REG 0xB4
+#define P9221R7_PROP_TX_ID_SIZE 4
+#define P9221R7_DATA_SEND_BUF_START 0x100
+#define P9221R7_DATA_SEND_BUF_SIZE 0x80
+#define P9221R7_DATA_RECV_BUF_START 0x180
+#define P9221R7_DATA_RECV_BUF_SIZE 0x80
+#define P9221R7_MAX_PP_BUF_SIZE 16
+#define P9221R7_LAST_REG 0x1FF
 
 /*
  * System Mode Mask (r7+/0x4C)
  */
-#define P9221R7_SYSTEM_MODE_EXTENDED_MASK	(1 << 3)
+#define P9221R7_SYSTEM_MODE_EXTENDED_MASK (1 << 3)
 
 /*
  * TX ID GPP Mask (r7+/0xB4->0xB7)
  */
-#define P9221R7_PROP_TX_ID_GPP_MASK		(1 << 29)
+#define P9221R7_PROP_TX_ID_GPP_MASK (1 << 29)
 
 /*
  * Com Channel Commands
  */
-#define P9221R7_COM_CHAN_CCRESET		BIT(7)
-#define P9221_COM_CHAN_RETRIES			5
+#define P9221R7_COM_CHAN_CCRESET BIT(7)
+#define P9221_COM_CHAN_RETRIES 5
 
 /*
  * End of Power packet types
  */
-#define P9221_EOP_UNKNOWN			0x00
-#define P9221_EOP_EOC				0x01
-#define P9221_EOP_INTERNAL_FAULT		0x02
-#define P9221_EOP_OVER_TEMP			0x03
-#define P9221_EOP_OVER_VOLT			0x04
-#define P9221_EOP_OVER_CURRENT			0x05
-#define P9221_EOP_BATT_FAIL			0x06
-#define P9221_EOP_RECONFIG			0x07
-#define P9221_EOP_NO_RESPONSE			0x08
-#define P9221_EOP_NEGOTIATION_FAIL		0x0A
-#define P9221_EOP_RESTART_POWER			0x0B
+#define P9221_EOP_UNKNOWN 0x00
+#define P9221_EOP_EOC 0x01
+#define P9221_EOP_INTERNAL_FAULT 0x02
+#define P9221_EOP_OVER_TEMP 0x03
+#define P9221_EOP_OVER_VOLT 0x04
+#define P9221_EOP_OVER_CURRENT 0x05
+#define P9221_EOP_BATT_FAIL 0x06
+#define P9221_EOP_RECONFIG 0x07
+#define P9221_EOP_NO_RESPONSE 0x08
+#define P9221_EOP_NEGOTIATION_FAIL 0x0A
+#define P9221_EOP_RESTART_POWER 0x0B
 
 /*
  * Command flags
  */
-#define P9221R7_COM_RENEGOTIATE			P9221_COM_RENEGOTIATE
-#define P9221R7_COM_SWITCH2RAM			P9221_COM_SWITCH_TO_RAM_MASK
-#define P9221R7_COM_CLRINT			P9221_COM_CLEAR_INT_MASK
-#define P9221R7_COM_SENDCSP			P9221_COM_SEND_CHG_STAT_MASK
-#define P9221R7_COM_SENDEPT			P9221_COM_SEND_EOP_MASK
-#define P9221R7_COM_LDOTGL			P9221_COM_LDO_TOGGLE
-#define P9221R7_COM_CCACTIVATE			BIT(0)
+#define P9221R7_COM_RENEGOTIATE P9221_COM_RENEGOTIATE
+#define P9221R7_COM_SWITCH2RAM P9221_COM_SWITCH_TO_RAM_MASK
+#define P9221R7_COM_CLRINT P9221_COM_CLEAR_INT_MASK
+#define P9221R7_COM_SENDCSP P9221_COM_SEND_CHG_STAT_MASK
+#define P9221R7_COM_SENDEPT P9221_COM_SEND_EOP_MASK
+#define P9221R7_COM_LDOTGL P9221_COM_LDO_TOGGLE
+#define P9221R7_COM_CCACTIVATE BIT(0)
 
-#define P9221_COM_RENEGOTIATE			BIT(7)
-#define P9221_COM_SWITCH_TO_RAM_MASK		BIT(6)
-#define P9221_COM_CLEAR_INT_MASK		BIT(5)
-#define P9221_COM_SEND_CHG_STAT_MASK		BIT(4)
-#define P9221_COM_SEND_EOP_MASK			BIT(3)
-#define P9221_COM_LDO_TOGGLE			BIT(1)
+#define P9221_COM_RENEGOTIATE BIT(7)
+#define P9221_COM_SWITCH_TO_RAM_MASK BIT(6)
+#define P9221_COM_CLEAR_INT_MASK BIT(5)
+#define P9221_COM_SEND_CHG_STAT_MASK BIT(4)
+#define P9221_COM_SEND_EOP_MASK BIT(3)
+#define P9221_COM_LDO_TOGGLE BIT(1)
 
 /*
  * Interrupt/Status flags for P9221
  */
-#define P9221_STAT_VOUT				BIT(7)
-#define P9221_STAT_VRECT			BIT(6)
-#define P9221_STAT_ACMISSING			BIT(5)
-#define P9221_STAT_OV_TEMP			BIT(2)
-#define P9221_STAT_OV_VOLT			BIT(1)
-#define P9221_STAT_OV_CURRENT			BIT(0)
-#define P9221_STAT_LIMIT_MASK			(P9221_STAT_OV_TEMP | \
-						 P9221_STAT_OV_VOLT | \
-						 P9221_STAT_OV_CURRENT)
+#define P9221_STAT_VOUT BIT(7)
+#define P9221_STAT_VRECT BIT(6)
+#define P9221_STAT_ACMISSING BIT(5)
+#define P9221_STAT_OV_TEMP BIT(2)
+#define P9221_STAT_OV_VOLT BIT(1)
+#define P9221_STAT_OV_CURRENT BIT(0)
+#define P9221_STAT_LIMIT_MASK \
+	(P9221_STAT_OV_TEMP | P9221_STAT_OV_VOLT | P9221_STAT_OV_CURRENT)
 /*
  * Interrupt/Status flags for P9221R7
  */
-#define P9221R7_STAT_CCRESET			BIT(12)
-#define P9221R7_STAT_CCERROR			BIT(11)
-#define P9221R7_STAT_PPRCVD			BIT(10)
-#define P9221R7_STAT_CCDATARCVD			BIT(9)
-#define P9221R7_STAT_CCSENDBUSY			BIT(8)
-#define P9221R7_STAT_VOUTCHANGED		BIT(7)
-#define P9221R7_STAT_VRECTON			BIT(6)
-#define P9221R7_STAT_MODECHANGED		BIT(5)
-#define P9221R7_STAT_UV				BIT(3)
-#define P9221R7_STAT_OVT			BIT(2)
-#define P9221R7_STAT_OVV			BIT(1)
-#define P9221R7_STAT_OVC			BIT(0)
-#define P9221R7_STAT_MASK			0x1FFF
-#define P9221R7_STAT_CC_MASK			(P9221R7_STAT_CCRESET | \
-						 P9221R7_STAT_PPRCVD | \
-						 P9221R7_STAT_CCERROR | \
-						 P9221R7_STAT_CCDATARCVD | \
-						 P9221R7_STAT_CCSENDBUSY)
-#define P9221R7_STAT_LIMIT_MASK			(P9221R7_STAT_UV | \
-						 P9221R7_STAT_OVV | \
-						 P9221R7_STAT_OVT | \
-						 P9221R7_STAT_OVC)
+#define P9221R7_STAT_CCRESET BIT(12)
+#define P9221R7_STAT_CCERROR BIT(11)
+#define P9221R7_STAT_PPRCVD BIT(10)
+#define P9221R7_STAT_CCDATARCVD BIT(9)
+#define P9221R7_STAT_CCSENDBUSY BIT(8)
+#define P9221R7_STAT_VOUTCHANGED BIT(7)
+#define P9221R7_STAT_VRECTON BIT(6)
+#define P9221R7_STAT_MODECHANGED BIT(5)
+#define P9221R7_STAT_UV BIT(3)
+#define P9221R7_STAT_OVT BIT(2)
+#define P9221R7_STAT_OVV BIT(1)
+#define P9221R7_STAT_OVC BIT(0)
+#define P9221R7_STAT_MASK 0x1FFF
+#define P9221R7_STAT_CC_MASK                                                 \
+	(P9221R7_STAT_CCRESET | P9221R7_STAT_PPRCVD | P9221R7_STAT_CCERROR | \
+	 P9221R7_STAT_CCDATARCVD | P9221R7_STAT_CCSENDBUSY)
+#define P9221R7_STAT_LIMIT_MASK                                  \
+	(P9221R7_STAT_UV | P9221R7_STAT_OVV | P9221R7_STAT_OVT | \
+	 P9221R7_STAT_OVC)
 
-#define P9221_DC_ICL_BPP_MA			1000
-#define P9221_DC_ICL_EPP_MA			1100
-#define P9221_DC_IVL_BPP_MV			5000
-#define P9221_DC_IVL_EPP_MV			9000
-#define P9221_EPP_THRESHOLD_UV			7000000
+#define P9221_DC_ICL_BPP_MA 1000
+#define P9221_DC_ICL_EPP_MA 1100
+#define P9221_DC_IVL_BPP_MV 5000
+#define P9221_DC_IVL_EPP_MV 9000
+#define P9221_EPP_THRESHOLD_UV 7000000
 
-#define true    1
-#define false   0
+#define true 1
+#define false 0
 
 struct wpc_charger_info {
-	uint8_t online;				 /* wpc is online */
-	uint8_t cust_id;			 /* customer id */
-	uint8_t i2c_port;			 /* i2c port */
+	uint8_t online; /* wpc is online */
+	uint8_t cust_id; /* customer id */
+	uint8_t i2c_port; /* i2c port */
 	/* Proprietary Packets receive buffer, to get Proprietary data from TX*/
 	uint8_t pp_buf[P9221R7_MAX_PP_BUF_SIZE];
 	uint8_t pp_buf_valid;
@@ -267,8 +261,8 @@ struct wpc_charger_info {
 	uint8_t rx_done;
 	/* Message packets send buffer, used when send messages from RX to TX*/
 	uint8_t tx_buf[P9221R7_DATA_SEND_BUF_SIZE];
-	uint8_t tx_id;				/* TX device id */
-	uint8_t tx_len;	 /* The data size need send to TX */
+	uint8_t tx_id; /* TX device id */
+	uint8_t tx_len; /* The data size need send to TX */
 	uint8_t tx_done; /* TX data send has done */
 	uint8_t tx_busy; /* when tx_busy=1, can't transfer data from RX to TX */
 	/* p9221_check_vbus=1 when VBUS has changed, need update charge state */
diff --git a/extra/cr50_rma_open/cr50_rma_open.py b/extra/cr50_rma_open/cr50_rma_open.py
index 42ddbbac2d..dc9c144158 100755
--- a/extra/cr50_rma_open/cr50_rma_open.py
+++ b/extra/cr50_rma_open/cr50_rma_open.py
@@ -1,6 +1,6 @@
 #!/usr/bin/env python3
 # -*- coding: utf-8 -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -50,23 +50,22 @@ import subprocess
 import sys
 import time
 
-import serial
+import serial  # pylint:disable=import-error
 
 SCRIPT_VERSION = 5
 CCD_IS_UNRESTRICTED = 1 << 0
 WP_IS_DISABLED = 1 << 1
 TESTLAB_IS_ENABLED = 1 << 2
 RMA_OPENED = CCD_IS_UNRESTRICTED | WP_IS_DISABLED
-URL = ('https://www.google.com/chromeos/partner/console/cr50reset?'
-       'challenge=%s&hwid=%s')
-RMA_SUPPORT_PROD = '0.3.3'
-RMA_SUPPORT_PREPVT = '0.4.5'
-DEV_MODE_OPEN_PROD = '0.3.9'
-DEV_MODE_OPEN_PREPVT = '0.4.7'
-TESTLAB_PROD = '0.3.10'
-CR50_USB = '18d1:5014'
-CR50_LSUSB_CMD = ['lsusb', '-vd', CR50_USB]
-ERASED_BID = 'ffffffff'
+URL = "https://www.google.com/chromeos/partner/console/cr50reset?challenge=%s&hwid=%s"
+RMA_SUPPORT_PROD = "0.3.3"
+RMA_SUPPORT_PREPVT = "0.4.5"
+DEV_MODE_OPEN_PROD = "0.3.9"
+DEV_MODE_OPEN_PREPVT = "0.4.7"
+TESTLAB_PROD = "0.3.10"
+CR50_USB = "18d1:5014"
+CR50_LSUSB_CMD = ["lsusb", "-vd", CR50_USB]
+ERASED_BID = "ffffffff"
 
 DEBUG_MISSING_USB = """
 Unable to find Cr50 Device 18d1:5014
@@ -128,13 +127,14 @@ DEBUG_DUT_CONTROL_OSERROR = """
 Run from chroot if you are trying to use a /dev/pts ccd servo console
 """
 
+
 class RMAOpen(object):
     """Used to find the cr50 console and run RMA open"""
 
-    ENABLE_TESTLAB_CMD = 'ccd testlab enabled\n'
+    ENABLE_TESTLAB_CMD = "ccd testlab enabled\n"
 
     def __init__(self, device=None, usb_serial=None, servo_port=None, ip=None):
-        self.servo_port = servo_port if servo_port else '9999'
+        self.servo_port = servo_port if servo_port else "9999"
         self.ip = ip
         if device:
             self.set_cr50_device(device)
@@ -142,18 +142,18 @@ class RMAOpen(object):
             self.find_cr50_servo_uart()
         else:
             self.find_cr50_device(usb_serial)
-        logging.info('DEVICE: %s', self.device)
+        logging.info("DEVICE: %s", self.device)
         self.check_version()
         self.print_platform_info()
-        logging.info('Cr50 setup ok')
+        logging.info("Cr50 setup ok")
         self.update_ccd_state()
         self.using_ccd = self.device_is_running_with_servo_ccd()
 
     def _dut_control(self, control):
         """Run dut-control and return the response"""
         try:
-            cmd = ['dut-control', '-p', self.servo_port, control]
-            return subprocess.check_output(cmd, encoding='utf-8').strip()
+            cmd = ["dut-control", "-p", self.servo_port, control]
+            return subprocess.check_output(cmd, encoding="utf-8").strip()
         except OSError:
             logging.warning(DEBUG_DUT_CONTROL_OSERROR)
             raise
@@ -163,8 +163,8 @@ class RMAOpen(object):
 
         Find the console and configure it, so it can be used with this script.
         """
-        self._dut_control('cr50_uart_timestamp:off')
-        self.device = self._dut_control('cr50_uart_pty').split(':')[-1]
+        self._dut_control("cr50_uart_timestamp:off")
+        self.device = self._dut_control("cr50_uart_pty").split(":")[-1]
 
     def set_cr50_device(self, device):
         """Save the device used for the console"""
@@ -183,38 +183,38 @@ class RMAOpen(object):
         try:
             ser = serial.Serial(self.device, timeout=1)
         except OSError:
-            logging.warning('Permission denied %s', self.device)
-            logging.warning('Try running cr50_rma_open with sudo')
+            logging.warning("Permission denied %s", self.device)
+            logging.warning("Try running cr50_rma_open with sudo")
             raise
-        write_cmd = cmd + '\n\n'
-        ser.write(write_cmd.encode('utf-8'))
+        write_cmd = cmd + "\n\n"
+        ser.write(write_cmd.encode("utf-8"))
         if nbytes:
             output = ser.read(nbytes)
         else:
             output = ser.readall()
         ser.close()
 
-        output = output.decode('utf-8').strip() if output else ''
+        output = output.decode("utf-8").strip() if output else ""
         # Return only the command output
-        split_cmd = cmd + '\r'
+        split_cmd = cmd + "\r"
         if cmd and split_cmd in output:
-            return ''.join(output.rpartition(split_cmd)[1::]).split('>')[0]
+            return "".join(output.rpartition(split_cmd)[1::]).split(">")[0]
         return output
 
     def device_is_running_with_servo_ccd(self):
         """Return True if the device is a servod ccd console"""
         # servod uses /dev/pts consoles. Non-servod uses /dev/ttyUSBX
-        if '/dev/pts' not in self.device:
+        if "/dev/pts" not in self.device:
             return False
         # If cr50 doesn't show rdd is connected, cr50 the device must not be
         # a ccd device
-        if 'Rdd:     connected' not in self.send_cmd_get_output('ccdstate'):
+        if "Rdd:     connected" not in self.send_cmd_get_output("ccdstate"):
             return False
         # Check if the servod is running with ccd. This requires the script
         # is run in the chroot, so run it last.
-        if 'ccd_cr50' not in self._dut_control('servo_type'):
+        if "ccd_cr50" not in self._dut_control("servo_type"):
             return False
-        logging.info('running through servod ccd')
+        logging.info("running through servod ccd")
         return True
 
     def get_rma_challenge(self):
@@ -239,14 +239,14 @@ class RMAOpen(object):
         Returns:
             The RMA challenge with all whitespace removed.
         """
-        output = self.send_cmd_get_output('rma_auth').strip()
-        logging.info('rma_auth output:\n%s', output)
+        output = self.send_cmd_get_output("rma_auth").strip()
+        logging.info("rma_auth output:\n%s", output)
         # Extract the challenge from the console output
-        if 'generated challenge:' in output:
-            return output.split('generated challenge:')[-1].strip()
-        challenge = ''.join(re.findall(r' \S{5}' * 4, output))
+        if "generated challenge:" in output:
+            return output.split("generated challenge:")[-1].strip()
+        challenge = "".join(re.findall(r" \S{5}" * 4, output))
         # Remove all whitespace
-        return re.sub(r'\s', '', challenge)
+        return re.sub(r"\s", "", challenge)
 
     def generate_challenge_url(self, hwid):
         """Get the rma_auth challenge
@@ -257,12 +257,14 @@ class RMAOpen(object):
 
         challenge = self.get_rma_challenge()
         self.print_platform_info()
-        logging.info('CHALLENGE: %s', challenge)
-        logging.info('HWID: %s', hwid)
+        logging.info("CHALLENGE: %s", challenge)
+        logging.info("HWID: %s", hwid)
         url = URL % (challenge, hwid)
-        logging.info('GOTO:\n %s', url)
-        logging.info('If the server fails to debug the challenge make sure the '
-                     'RLZ is allowlisted')
+        logging.info("GOTO:\n %s", url)
+        logging.info(
+            "If the server fails to debug the challenge make sure the "
+            "RLZ is allowlisted"
+        )
 
     def try_authcode(self, authcode):
         """Try opening cr50 with the authcode
@@ -272,48 +274,48 @@ class RMAOpen(object):
         """
         # rma_auth may cause the system to reboot. Don't wait to read all that
         # output. Read the first 300 bytes and call it a day.
-        output = self.send_cmd_get_output('rma_auth ' + authcode, nbytes=300)
-        logging.info('CR50 RESPONSE: %s', output)
-        logging.info('waiting for cr50 reboot')
+        output = self.send_cmd_get_output("rma_auth " + authcode, nbytes=300)
+        logging.info("CR50 RESPONSE: %s", output)
+        logging.info("waiting for cr50 reboot")
         # Cr50 may be rebooting. Wait a bit
         time.sleep(5)
         if self.using_ccd:
             # After reboot, reset the ccd endpoints
-            self._dut_control('power_state:ccd_reset')
+            self._dut_control("power_state:ccd_reset")
         # Update the ccd state after the authcode attempt
         self.update_ccd_state()
 
-        authcode_match = 'process_response: success!' in output
+        authcode_match = "process_response: success!" in output
         if not self.check(CCD_IS_UNRESTRICTED):
             if not authcode_match:
                 logging.warning(DEBUG_AUTHCODE_MISMATCH)
-                message = 'Authcode mismatch. Check args and url'
+                message = "Authcode mismatch. Check args and url"
             else:
-                message = 'Could not set all capability privileges to Always'
+                message = "Could not set all capability privileges to Always"
             raise ValueError(message)
 
     def wp_is_force_disabled(self):
         """Returns True if write protect is forced disabled"""
-        output = self.send_cmd_get_output('wp')
-        wp_state = output.split('Flash WP:', 1)[-1].split('\n', 1)[0].strip()
-        logging.info('wp: %s', wp_state)
-        return wp_state == 'forced disabled'
+        output = self.send_cmd_get_output("wp")
+        wp_state = output.split("Flash WP:", 1)[-1].split("\n", 1)[0].strip()
+        logging.info("wp: %s", wp_state)
+        return wp_state == "forced disabled"
 
     def testlab_is_enabled(self):
         """Returns True if testlab mode is enabled"""
-        output = self.send_cmd_get_output('ccd testlab')
-        testlab_state = output.split('mode')[-1].strip().lower()
-        logging.info('testlab: %s', testlab_state)
-        return testlab_state == 'enabled'
+        output = self.send_cmd_get_output("ccd testlab")
+        testlab_state = output.split("mode")[-1].strip().lower()
+        logging.info("testlab: %s", testlab_state)
+        return testlab_state == "enabled"
 
     def ccd_is_restricted(self):
         """Returns True if any of the capabilities are still restricted"""
-        output = self.send_cmd_get_output('ccd')
-        if 'Capabilities' not in output:
-            raise ValueError('Could not get ccd output')
-        logging.debug('CURRENT CCD SETTINGS:\n%s', output)
-        restricted = 'IfOpened' in output or 'IfUnlocked' in output
-        logging.info('ccd: %srestricted', '' if restricted else 'Un')
+        output = self.send_cmd_get_output("ccd")
+        if "Capabilities" not in output:
+            raise ValueError("Could not get ccd output")
+        logging.debug("CURRENT CCD SETTINGS:\n%s", output)
+        restricted = "IfOpened" in output or "IfUnlocked" in output
+        logging.info("ccd: %srestricted", "" if restricted else "Un")
         return restricted
 
     def update_ccd_state(self):
@@ -339,9 +341,10 @@ class RMAOpen(object):
 
     def _capabilities_allow_open_from_console(self):
         """Return True if ccd open is Always allowed from usb"""
-        output = self.send_cmd_get_output('ccd')
-        return (re.search('OpenNoDevMode.*Always', output) and
-                re.search('OpenFromUSB.*Always', output))
+        output = self.send_cmd_get_output("ccd")
+        return re.search("OpenNoDevMode.*Always", output) and re.search(
+            "OpenFromUSB.*Always", output
+        )
 
     def _requires_dev_mode_open(self):
         """Return True if the image requires dev mode to open"""
@@ -354,78 +357,83 @@ class RMAOpen(object):
 
     def _run_on_dut(self, command):
         """Run the command on the DUT."""
-        return subprocess.check_output(['ssh', self.ip, command],
-                                       encoding='utf-8')
+        return subprocess.check_output(
+            ["ssh", self.ip, command], encoding="utf-8"
+        )
 
     def _open_in_dev_mode(self):
         """Open Cr50 when it's in dev mode"""
-        output = self.send_cmd_get_output('ccd')
+        output = self.send_cmd_get_output("ccd")
         # If the device is already open, nothing needs to be done.
-        if 'State: Open' not in output:
+        if "State: Open" not in output:
             # Verify the device is in devmode before trying to run open.
-            if 'dev_mode' not in output:
-                logging.warning('Enter dev mode to open ccd or update to %s',
-                                TESTLAB_PROD)
-                raise ValueError('DUT not in dev mode')
+            if "dev_mode" not in output:
+                logging.warning(
+                    "Enter dev mode to open ccd or update to %s", TESTLAB_PROD
+                )
+                raise ValueError("DUT not in dev mode")
             if not self.ip:
-                logging.warning("If your DUT doesn't have ssh support, run "
-                                "'gsctool -a -o' from the AP")
-                raise ValueError('Cannot run ccd open without dut ip')
-            self._run_on_dut('gsctool -a -o')
+                logging.warning(
+                    "If your DUT doesn't have ssh support, run "
+                    "'gsctool -a -o' from the AP"
+                )
+                raise ValueError("Cannot run ccd open without dut ip")
+            self._run_on_dut("gsctool -a -o")
             # Wait >1 second for cr50 to update ccd state
             time.sleep(3)
-            output = self.send_cmd_get_output('ccd')
-            if 'State: Open' not in output:
-                raise ValueError('Could not open cr50')
-        logging.info('ccd is open')
+            output = self.send_cmd_get_output("ccd")
+            if "State: Open" not in output:
+                raise ValueError("Could not open cr50")
+        logging.info("ccd is open")
 
     def enable_testlab(self):
         """Disable write protect"""
         if not self._has_testlab_support():
-            logging.warning('Testlab mode is not supported in prod iamges')
+            logging.warning("Testlab mode is not supported in prod iamges")
             return
         # Some cr50 images need to be in dev mode before they can be opened.
         if self._requires_dev_mode_open():
             self._open_in_dev_mode()
         else:
-            self.send_cmd_get_output('ccd open')
-        logging.info('Enabling testlab mode reqires pressing the power button.')
-        logging.info('Once the process starts keep tapping the power button '
-                     'for 10 seconds.')
+            self.send_cmd_get_output("ccd open")
+        logging.info("Enabling testlab mode reqires pressing the power button.")
+        logging.info(
+            "Once the process starts keep tapping the power button for 10 seconds."
+        )
         input("Press Enter when you're ready to start...")
         end_time = time.time() + 15
 
         ser = serial.Serial(self.device, timeout=1)
-        printed_lines = ''
-        output = ''
+        printed_lines = ""
+        output = ""
         # start ccd testlab enable
-        ser.write(self.ENABLE_TESTLAB_CMD.encode('utf-8'))
-        logging.info('start pressing the power button\n\n')
+        ser.write(self.ENABLE_TESTLAB_CMD.encode("utf-8"))
+        logging.info("start pressing the power button\n\n")
         # Print all of the cr50 output as we get it, so the user will have more
         # information about pressing the power button. Tapping the power button
         # a couple of times should do it, but this will give us more confidence
         # the process is still running/worked.
         try:
             while time.time() < end_time:
-                output += ser.read(100).decode('utf-8')
-                full_lines = output.rsplit('\n', 1)[0]
+                output += ser.read(100).decode("utf-8")
+                full_lines = output.rsplit("\n", 1)[0]
                 new_lines = full_lines
                 if printed_lines:
                     new_lines = full_lines.split(printed_lines, 1)[-1].strip()
-                logging.info('\n%s', new_lines)
+                logging.info("\n%s", new_lines)
                 printed_lines = full_lines
 
                 # Make sure the process hasn't ended. If it has, print the last
                 # of the output and exit.
                 new_lines = output.split(printed_lines, 1)[-1]
-                if 'CCD test lab mode enabled' in output:
+                if "CCD test lab mode enabled" in output:
                     # print the last of the ou
                     logging.info(new_lines)
                     break
-                elif 'Physical presence check timeout' in output:
+                elif "Physical presence check timeout" in output:
                     logging.info(new_lines)
-                    logging.warning('Did not detect power button press in time')
-                    raise ValueError('Could not enable testlab mode try again')
+                    logging.warning("Did not detect power button press in time")
+                    raise ValueError("Could not enable testlab mode try again")
         finally:
             ser.close()
         # Wait for the ccd hook to update things
@@ -433,44 +441,50 @@ class RMAOpen(object):
         # Update the state after attempting to disable write protect
         self.update_ccd_state()
         if not self.check(TESTLAB_IS_ENABLED):
-            raise ValueError('Could not enable testlab mode try again')
+            raise ValueError("Could not enable testlab mode try again")
 
     def wp_disable(self):
         """Disable write protect"""
-        logging.info('Disabling write protect')
-        self.send_cmd_get_output('wp disable')
+        logging.info("Disabling write protect")
+        self.send_cmd_get_output("wp disable")
         # Update the state after attempting to disable write protect
         self.update_ccd_state()
         if not self.check(WP_IS_DISABLED):
-            raise ValueError('Could not disable write protect')
+            raise ValueError("Could not disable write protect")
 
     def check_version(self):
         """Make sure cr50 is running a version that supports RMA Open"""
-        output = self.send_cmd_get_output('version')
+        output = self.send_cmd_get_output("version")
         if not output.strip():
             logging.warning(DEBUG_DEVICE, self.device)
-            raise ValueError('Could not communicate with %s' % self.device)
+            raise ValueError("Could not communicate with %s" % self.device)
 
-        version = re.search(r'RW.*\* ([\d\.]+)/', output).group(1)
-        logging.info('Running Cr50 Version: %s', version)
-        self.running_ver_fields = [int(field) for field in version.split('.')]
+        version = re.search(r"RW.*\* ([\d\.]+)/", output).group(1)
+        logging.info("Running Cr50 Version: %s", version)
+        self.running_ver_fields = [int(field) for field in version.split(".")]
 
         # prePVT images have even major versions. Prod have odd
         self.is_prepvt = self.running_ver_fields[1] % 2 == 0
         rma_support = RMA_SUPPORT_PREPVT if self.is_prepvt else RMA_SUPPORT_PROD
 
-        logging.info('%s RMA support added in: %s',
-                     'prePVT' if self.is_prepvt else 'prod', rma_support)
+        logging.info(
+            "%s RMA support added in: %s",
+            "prePVT" if self.is_prepvt else "prod",
+            rma_support,
+        )
         if not self.is_prepvt and self._running_version_is_older(TESTLAB_PROD):
-            raise ValueError('Update cr50. No testlab support in old prod '
-                             'images.')
+            raise ValueError(
+                "Update cr50. No testlab support in old prod images."
+            )
         if self._running_version_is_older(rma_support):
-            raise ValueError('%s does not have RMA support. Update to at '
-                             'least %s' % (version, rma_support))
+            raise ValueError(
+                "%s does not have RMA support. Update to at least %s"
+                % (version, rma_support)
+            )
 
     def _running_version_is_older(self, target_ver):
         """Returns True if running version is older than target_ver."""
-        target_ver_fields = [int(field) for field in target_ver.split('.')]
+        target_ver_fields = [int(field) for field in target_ver.split(".")]
         for i, field in enumerate(self.running_ver_fields):
             if field > int(target_ver_fields[i]):
                 return False
@@ -486,11 +500,11 @@ class RMAOpen(object):
             is no output or sysinfo doesn't contain the devid.
         """
         self.set_cr50_device(device)
-        sysinfo = self.send_cmd_get_output('sysinfo')
+        sysinfo = self.send_cmd_get_output("sysinfo")
         # Make sure there is some output, and it shows it's from Cr50
-        if not sysinfo or 'cr50' not in sysinfo:
+        if not sysinfo or "cr50" not in sysinfo:
             return False
-        logging.debug('Sysinfo output: %s', sysinfo)
+        logging.debug("Sysinfo output: %s", sysinfo)
         # The cr50 device id should be in the sysinfo output, if we found
         # the right console. Make sure it is
         return devid in sysinfo
@@ -508,104 +522,150 @@ class RMAOpen(object):
             ValueError if the console can't be found with the given serialname
         """
         usb_serial = self.find_cr50_usb(usb_serial)
-        logging.info('SERIALNAME: %s', usb_serial)
-        devid = '0x' + ' 0x'.join(usb_serial.lower().split('-'))
-        logging.info('DEVID: %s', devid)
+        logging.info("SERIALNAME: %s", usb_serial)
+        devid = "0x" + " 0x".join(usb_serial.lower().split("-"))
+        logging.info("DEVID: %s", devid)
 
         # Get all the usb devices
-        devices = glob.glob('/dev/ttyUSB*')
+        devices = glob.glob("/dev/ttyUSB*")
         # Typically Cr50 has the lowest number. Sort the devices, so we're more
         # likely to try the cr50 console first.
         devices.sort()
 
         # Find the one that is the cr50 console
         for device in devices:
-            logging.info('testing %s', device)
+            logging.info("testing %s", device)
             if self.device_matches_devid(devid, device):
-                logging.info('found device: %s', device)
+                logging.info("found device: %s", device)
                 return
         logging.warning(DEBUG_CONNECTION)
-        raise ValueError('Found USB device, but could not communicate with '
-                         'cr50 console')
+        raise ValueError(
+            "Found USB device, but could not communicate with cr50 console"
+        )
 
     def print_platform_info(self):
         """Print the cr50 BID RLZ code"""
-        bid_output = self.send_cmd_get_output('bid')
-        bid = re.search(r'Board ID: (\S+?)[:,]', bid_output).group(1)
+        bid_output = self.send_cmd_get_output("bid")
+        bid = re.search(r"Board ID: (\S+?)[:,]", bid_output).group(1)
         if bid == ERASED_BID:
             logging.warning(DEBUG_ERASED_BOARD_ID)
-            raise ValueError('Cannot run RMA Open when board id is erased')
+            raise ValueError("Cannot run RMA Open when board id is erased")
         bid = int(bid, 16)
-        chrs = [chr((bid >> (8 * i)) & 0xff) for i in range(4)]
-        logging.info('RLZ: %s', ''.join(chrs[::-1]))
+        chrs = [chr((bid >> (8 * i)) & 0xFF) for i in range(4)]
+        logging.info("RLZ: %s", "".join(chrs[::-1]))
 
     @staticmethod
     def find_cr50_usb(usb_serial):
         """Make sure the Cr50 USB device exists"""
         try:
-            output = subprocess.check_output(CR50_LSUSB_CMD, encoding='utf-8')
+            output = subprocess.check_output(CR50_LSUSB_CMD, encoding="utf-8")
         except:
             logging.warning(DEBUG_MISSING_USB)
-            raise ValueError('Could not find Cr50 USB device')
-        serialnames = re.findall(r'iSerial +\d+ (\S+)\s', output)
+            raise ValueError("Could not find Cr50 USB device")
+        serialnames = re.findall(r"iSerial +\d+ (\S+)\s", output)
         if usb_serial:
             if usb_serial not in serialnames:
                 logging.warning(DEBUG_SERIALNAME)
                 raise ValueError('Could not find usb device "%s"' % usb_serial)
             return usb_serial
         if len(serialnames) > 1:
-            logging.info('Found Cr50 device serialnames %s',
-                         ', '.join(serialnames))
+            logging.info(
+                "Found Cr50 device serialnames %s", ", ".join(serialnames)
+            )
             logging.warning(DEBUG_TOO_MANY_USB_DEVICES)
-            raise ValueError('Too many cr50 usb devices')
+            raise ValueError("Too many cr50 usb devices")
         return serialnames[0]
 
     def print_dut_state(self):
         """Print CCD RMA and testlab mode state."""
         if not self.check(CCD_IS_UNRESTRICTED):
-            logging.info('CCD is still restricted.')
-            logging.info('Run cr50_rma_open.py -g -i $HWID to generate a url')
-            logging.info('Run cr50_rma_open.py -a $AUTHCODE to open cr50 with '
-                         'an authcode')
+            logging.info("CCD is still restricted.")
+            logging.info("Run cr50_rma_open.py -g -i $HWID to generate a url")
+            logging.info(
+                "Run cr50_rma_open.py -a $AUTHCODE to open cr50 with an authcode"
+            )
         elif not self.check(WP_IS_DISABLED):
-            logging.info('WP is still enabled.')
-            logging.info('Run cr50_rma_open.py -w to disable write protect')
+            logging.info("WP is still enabled.")
+            logging.info("Run cr50_rma_open.py -w to disable write protect")
         if self.check(RMA_OPENED):
-            logging.info('RMA Open complete')
+            logging.info("RMA Open complete")
 
         if not self.check(TESTLAB_IS_ENABLED) and self.is_prepvt:
-            logging.info('testlab mode is disabled.')
-            logging.info('If you are prepping a device for the testlab, you '
-                         'should enable testlab mode.')
-            logging.info('Run cr50_rma_open.py -t to enable testlab mode')
+            logging.info("testlab mode is disabled.")
+            logging.info(
+                "If you are prepping a device for the testlab, you "
+                "should enable testlab mode."
+            )
+            logging.info("Run cr50_rma_open.py -t to enable testlab mode")
 
 
 def parse_args(argv):
     """Get cr50_rma_open args."""
     parser = argparse.ArgumentParser(
-        description=__doc__, formatter_class=argparse.RawTextHelpFormatter)
-    parser.add_argument('-g', '--generate_challenge', action='store_true',
-                        help='Generate Cr50 challenge. Must be used with -i')
-    parser.add_argument('-t', '--enable_testlab', action='store_true',
-                        help='enable testlab mode')
-    parser.add_argument('-w', '--wp_disable', action='store_true',
-                        help='Disable write protect')
-    parser.add_argument('-c', '--check_connection', action='store_true',
-                        help='Check cr50 console connection works')
-    parser.add_argument('-s', '--serialname', type=str, default='',
-                        help='The cr50 usb serialname')
-    parser.add_argument('-D', '--debug', action='store_true',
-                        help='print debug messages')
-    parser.add_argument('-d', '--device', type=str, default='',
-                        help='cr50 console device ex /dev/ttyUSB0')
-    parser.add_argument('-i', '--hwid', type=str, default='',
-                        help='The board hwid. Needed to generate a challenge')
-    parser.add_argument('-a', '--authcode', type=str, default='',
-                        help='The authcode string from the challenge url')
-    parser.add_argument('-P', '--servo_port', type=str, default='',
-                        help='the servo port')
-    parser.add_argument('-I', '--ip', type=str, default='',
-                        help='The DUT IP. Necessary to do ccd open')
+        description=__doc__, formatter_class=argparse.RawTextHelpFormatter
+    )
+    parser.add_argument(
+        "-g",
+        "--generate_challenge",
+        action="store_true",
+        help="Generate Cr50 challenge. Must be used with -i",
+    )
+    parser.add_argument(
+        "-t",
+        "--enable_testlab",
+        action="store_true",
+        help="enable testlab mode",
+    )
+    parser.add_argument(
+        "-w", "--wp_disable", action="store_true", help="Disable write protect"
+    )
+    parser.add_argument(
+        "-c",
+        "--check_connection",
+        action="store_true",
+        help="Check cr50 console connection works",
+    )
+    parser.add_argument(
+        "-s",
+        "--serialname",
+        type=str,
+        default="",
+        help="The cr50 usb serialname",
+    )
+    parser.add_argument(
+        "-D", "--debug", action="store_true", help="print debug messages"
+    )
+    parser.add_argument(
+        "-d",
+        "--device",
+        type=str,
+        default="",
+        help="cr50 console device ex /dev/ttyUSB0",
+    )
+    parser.add_argument(
+        "-i",
+        "--hwid",
+        type=str,
+        default="",
+        help="The board hwid. Needed to generate a challenge",
+    )
+    parser.add_argument(
+        "-a",
+        "--authcode",
+        type=str,
+        default="",
+        help="The authcode string from the challenge url",
+    )
+    parser.add_argument(
+        "-P", "--servo_port", type=str, default="", help="the servo port"
+    )
+    parser.add_argument(
+        "-I",
+        "--ip",
+        type=str,
+        default="",
+        help="The DUT IP. Necessary to do ccd open",
+    )
     return parser.parse_args(argv)
 
 
@@ -614,52 +674,59 @@ def main(argv):
     opts = parse_args(argv)
 
     loglevel = logging.INFO
-    log_format = '%(levelname)7s'
+    log_format = "%(levelname)7s"
     if opts.debug:
         loglevel = logging.DEBUG
-        log_format += ' - %(lineno)3d:%(funcName)-15s'
-    log_format += ' - %(message)s'
+        log_format += " - %(lineno)3d:%(funcName)-15s"
+    log_format += " - %(message)s"
     logging.basicConfig(level=loglevel, format=log_format)
 
     tried_authcode = False
-    logging.info('Running cr50_rma_open version %s', SCRIPT_VERSION)
+    logging.info("Running cr50_rma_open version %s", SCRIPT_VERSION)
 
-    cr50_rma_open = RMAOpen(opts.device, opts.serialname, opts.servo_port,
-                            opts.ip)
+    cr50_rma_open = RMAOpen(
+        opts.device, opts.serialname, opts.servo_port, opts.ip
+    )
     if opts.check_connection:
         sys.exit(0)
 
     if not cr50_rma_open.check(CCD_IS_UNRESTRICTED):
         if opts.generate_challenge:
             if not opts.hwid:
-                logging.warning('--hwid necessary to generate challenge url')
+                logging.warning("--hwid necessary to generate challenge url")
                 sys.exit(0)
             cr50_rma_open.generate_challenge_url(opts.hwid)
             sys.exit(0)
         elif opts.authcode:
-            logging.info('Using authcode: %s', opts.authcode)
+            logging.info("Using authcode: %s", opts.authcode)
             cr50_rma_open.try_authcode(opts.authcode)
             tried_authcode = True
 
-    if not cr50_rma_open.check(WP_IS_DISABLED) and (tried_authcode or
-                                                    opts.wp_disable):
+    if not cr50_rma_open.check(WP_IS_DISABLED) and (
+        tried_authcode or opts.wp_disable
+    ):
         if not cr50_rma_open.check(CCD_IS_UNRESTRICTED):
-            raise ValueError("Can't disable write protect unless ccd is "
-                             "open. Run through the rma open process first")
+            raise ValueError(
+                "Can't disable write protect unless ccd is "
+                "open. Run through the rma open process first"
+            )
         if tried_authcode:
-            logging.warning('RMA Open did not disable write protect. File a '
-                            'bug')
-            logging.warning('Trying to disable it manually')
+            logging.warning(
+                "RMA Open did not disable write protect. File a bug"
+            )
+            logging.warning("Trying to disable it manually")
         cr50_rma_open.wp_disable()
 
     if not cr50_rma_open.check(TESTLAB_IS_ENABLED) and opts.enable_testlab:
         if not cr50_rma_open.check(CCD_IS_UNRESTRICTED):
-            raise ValueError("Can't enable testlab mode unless ccd is open."
-                             "Run through the rma open process first")
+            raise ValueError(
+                "Can't enable testlab mode unless ccd is open."
+                "Run through the rma open process first"
+            )
         cr50_rma_open.enable_testlab()
 
     cr50_rma_open.print_dut_state()
 
 
-if __name__ == '__main__':
+if __name__ == "__main__":
     sys.exit(main(sys.argv[1:]))
diff --git a/extra/ftdi_hostcmd/Makefile b/extra/ftdi_hostcmd/Makefile
index d46b4b1c72..10f0e2d390 100644
--- a/extra/ftdi_hostcmd/Makefile
+++ b/extra/ftdi_hostcmd/Makefile
@@ -1,4 +1,4 @@
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/extra/ftdi_hostcmd/test_cmds.c b/extra/ftdi_hostcmd/test_cmds.c
index 4552476d0f..7bd3413032 100644
--- a/extra/ftdi_hostcmd/test_cmds.c
+++ b/extra/ftdi_hostcmd/test_cmds.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,7 +22,7 @@ static struct mpsse_context *mpsse;
 /* enum ec_status meaning */
 static const char *ec_strerr(enum ec_status r)
 {
-	static const char * const strs[] = {
+	static const char *const strs[] = {
 		"SUCCESS",
 		"INVALID_COMMAND",
 		"ERROR",
@@ -47,10 +47,9 @@ static const char *ec_strerr(enum ec_status r)
 	return "<undefined result>";
 };
 
-
-/****************************************************************************
- * Debugging output
- */
+	/****************************************************************************
+	 * Debugging output
+	 */
 
 #define LINELEN 16
 
@@ -64,8 +63,7 @@ static void showline(uint8_t *buf, int len)
 		printf("   ");
 	printf("    ");
 	for (i = 0; i < len; i++)
-		printf("%c",
-		       (buf[i] >= ' ' && buf[i] <= '~') ? buf[i] : '.');
+		printf("%c", (buf[i] >= ' ' && buf[i] <= '~') ? buf[i] : '.');
 	printf("\n");
 }
 
@@ -104,8 +102,8 @@ static uint8_t txbuf[128];
  * Load the output buffer with a proto v3 request (header, then data, with
  * checksum correct in header).
  */
-static size_t prepare_request(int cmd, int version,
-			      const uint8_t *data, size_t data_len)
+static size_t prepare_request(int cmd, int version, const uint8_t *data,
+			      size_t data_len)
 {
 	struct ec_host_request *request;
 	size_t i, total_len;
@@ -113,8 +111,8 @@ static size_t prepare_request(int cmd, int version,
 
 	total_len = sizeof(*request) + data_len;
 	if (total_len > sizeof(txbuf)) {
-		printf("Request too large (%zd > %zd)\n",
-		       total_len, sizeof(txbuf));
+		printf("Request too large (%zd > %zd)\n", total_len,
+		       sizeof(txbuf));
 		return -1;
 	}
 
@@ -153,8 +151,7 @@ static int send_request(uint8_t *txbuf, size_t len)
 	tptr = Transfer(mpsse, txbuf, len);
 
 	if (!tptr) {
-		fprintf(stderr, "Transfer failed: %s\n",
-			ErrorString(mpsse));
+		fprintf(stderr, "Transfer failed: %s\n", ErrorString(mpsse));
 		return -1;
 	}
 
@@ -178,7 +175,6 @@ static int send_request(uint8_t *txbuf, size_t len)
 	return ret;
 }
 
-
 /* Timeout flag, so we don't wait forever */
 static int timedout;
 static void alarm_handler(int sig)
@@ -195,8 +191,8 @@ static void alarm_handler(int sig)
  *   0   = response received (check hdr for EC result and body size)
  *   -1  = problems
  */
-static int get_response(struct ec_host_response *hdr,
-			uint8_t *bodydest, size_t bodylen)
+static int get_response(struct ec_host_response *hdr, uint8_t *bodydest,
+			size_t bodylen)
 {
 	uint8_t *hptr = 0, *bptr = 0;
 	uint8_t sum = 0;
@@ -237,8 +233,7 @@ static int get_response(struct ec_host_response *hdr,
 	/* Now read the response header */
 	hptr = Read(mpsse, sizeof(*hdr));
 	if (!hptr) {
-		fprintf(stderr, "Read failed: %s\n",
-			ErrorString(mpsse));
+		fprintf(stderr, "Read failed: %s\n", ErrorString(mpsse));
 		goto out;
 	}
 	show("Header(%d):\n", hptr, sizeof(*hdr));
@@ -247,14 +242,12 @@ static int get_response(struct ec_host_response *hdr,
 	/* Check the header */
 	if (hdr->struct_version != EC_HOST_RESPONSE_VERSION) {
 		printf("response version %d (should be %d)\n",
-		       hdr->struct_version,
-		       EC_HOST_RESPONSE_VERSION);
+		       hdr->struct_version, EC_HOST_RESPONSE_VERSION);
 		goto out;
 	}
 
 	if (hdr->data_len > bodylen) {
-		printf("response data_len %d is > %zd\n",
-		       hdr->data_len,
+		printf("response data_len %d is > %zd\n", hdr->data_len,
 		       bodylen);
 		goto out;
 	}
@@ -290,19 +283,13 @@ out:
 	return ret;
 }
 
-
 /*
  * Send command, wait for result. Return zero if communication succeeded; check
  * response to see if the EC liked the command.
  */
-static int send_cmd(int cmd, int version,
-		    void *outbuf,
-		    size_t outsize,
-		    struct ec_host_response *resp,
-		    void *inbuf,
-		    size_t insize)
+static int send_cmd(int cmd, int version, void *outbuf, size_t outsize,
+		    struct ec_host_response *resp, void *inbuf, size_t insize)
 {
-
 	size_t len;
 	int ret = -1;
 
@@ -312,8 +299,7 @@ static int send_cmd(int cmd, int version,
 		return -1;
 
 	if (MPSSE_OK != Start(mpsse)) {
-		fprintf(stderr, "Start failed: %s\n",
-			ErrorString(mpsse));
+		fprintf(stderr, "Start failed: %s\n", ErrorString(mpsse));
 		return -1;
 	}
 
@@ -322,15 +308,13 @@ static int send_cmd(int cmd, int version,
 		ret = 0;
 
 	if (MPSSE_OK != Stop(mpsse)) {
-		fprintf(stderr, "Stop failed: %s\n",
-			ErrorString(mpsse));
+		fprintf(stderr, "Stop failed: %s\n", ErrorString(mpsse));
 		return -1;
 	}
 
 	return ret;
 }
 
-
 /****************************************************************************
  * Probe for basic protocol info
  */
@@ -352,10 +336,8 @@ static int probe_v3(void)
 	if (opt_verbose)
 		printf("Trying EC_CMD_GET_PROTOCOL_INFO...\n");
 
-	ret = send_cmd(EC_CMD_GET_PROTOCOL_INFO, 0,
-		       0, 0,
-		       &resp,
-		       &info, sizeof(info));
+	ret = send_cmd(EC_CMD_GET_PROTOCOL_INFO, 0, 0, 0, &resp, &info,
+		       sizeof(info));
 
 	if (ret) {
 		printf("EC_CMD_GET_PROTOCOL_INFO failed\n");
@@ -363,8 +345,8 @@ static int probe_v3(void)
 	}
 
 	if (EC_RES_SUCCESS != resp.result) {
-		printf("EC result is %d: %s\n",
-		       resp.result, ec_strerr(resp.result));
+		printf("EC result is %d: %s\n", resp.result,
+		       ec_strerr(resp.result));
 		return -1;
 	}
 
@@ -378,8 +360,7 @@ static int probe_v3(void)
 	       info.max_request_packet_size);
 	printf("  max_response_packet_size:   %d\n",
 	       info.max_response_packet_size);
-	printf("  flags:                      0x%x\n",
-	       info.flags);
+	printf("  flags:                      0x%x\n", info.flags);
 
 	return 0;
 }
@@ -390,119 +371,118 @@ static int probe_v3(void)
 
 struct lookup {
 	uint16_t cmd;
-	const char * const desc;
+	const char *const desc;
 };
 
 static struct lookup cmd_table[] = {
-	{0x00, "EC_CMD_PROTO_VERSION"},
-	{0x01, "EC_CMD_HELLO"},
-	{0x02, "EC_CMD_GET_VERSION"},
-	{0x03, "EC_CMD_READ_TEST"},
-	{0x04, "EC_CMD_GET_BUILD_INFO"},
-	{0x05, "EC_CMD_GET_CHIP_INFO"},
-	{0x06, "EC_CMD_GET_BOARD_VERSION"},
-	{0x07, "EC_CMD_READ_MEMMAP"},
-	{0x08, "EC_CMD_GET_CMD_VERSIONS"},
-	{0x09, "EC_CMD_GET_COMMS_STATUS"},
-	{0x0a, "EC_CMD_TEST_PROTOCOL"},
-	{0x0b, "EC_CMD_GET_PROTOCOL_INFO"},
-	{0x0c, "EC_CMD_GSV_PAUSE_IN_S5"},
-	{0x0d, "EC_CMD_GET_FEATURES"},
-	{0x10, "EC_CMD_FLASH_INFO"},
-	{0x11, "EC_CMD_FLASH_READ"},
-	{0x12, "EC_CMD_FLASH_WRITE"},
-	{0x13, "EC_CMD_FLASH_ERASE"},
-	{0x15, "EC_CMD_FLASH_PROTECT"},
-	{0x16, "EC_CMD_FLASH_REGION_INFO"},
-	{0x17, "EC_CMD_VBNV_CONTEXT"},
-	{0x20, "EC_CMD_PWM_GET_FAN_TARGET_RPM"},
-	{0x21, "EC_CMD_PWM_SET_FAN_TARGET_RPM"},
-	{0x22, "EC_CMD_PWM_GET_KEYBOARD_BACKLIGHT"},
-	{0x23, "EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT"},
-	{0x24, "EC_CMD_PWM_SET_FAN_DUTY"},
-	{0x28, "EC_CMD_LIGHTBAR_CMD"},
-	{0x29, "EC_CMD_LED_CONTROL"},
-	{0x2a, "EC_CMD_VBOOT_HASH"},
-	{0x2b, "EC_CMD_MOTION_SENSE_CMD"},
-	{0x2c, "EC_CMD_FORCE_LID_OPEN"},
-	{0x30, "EC_CMD_USB_CHARGE_SET_MODE"},
-	{0x40, "EC_CMD_PSTORE_INFO"},
-	{0x41, "EC_CMD_PSTORE_READ"},
-	{0x42, "EC_CMD_PSTORE_WRITE"},
-	{0x44, "EC_CMD_RTC_GET_VALUE"},
-	{0x45, "EC_CMD_RTC_GET_ALARM"},
-	{0x46, "EC_CMD_RTC_SET_VALUE"},
-	{0x47, "EC_CMD_RTC_SET_ALARM"},
-	{0x48, "EC_CMD_PORT80_LAST_BOOT"},
-	{0x48, "EC_CMD_PORT80_READ"},
-	{0x50, "EC_CMD_THERMAL_SET_THRESHOLD"},
-	{0x51, "EC_CMD_THERMAL_GET_THRESHOLD"},
-	{0x52, "EC_CMD_THERMAL_AUTO_FAN_CTRL"},
-	{0x53, "EC_CMD_TMP006_GET_CALIBRATION"},
-	{0x54, "EC_CMD_TMP006_SET_CALIBRATION"},
-	{0x55, "EC_CMD_TMP006_GET_RAW"},
-	{0x60, "EC_CMD_MKBP_STATE"},
-	{0x61, "EC_CMD_MKBP_INFO"},
-	{0x62, "EC_CMD_MKBP_SIMULATE_KEY"},
-	{0x64, "EC_CMD_MKBP_SET_CONFIG"},
-	{0x65, "EC_CMD_MKBP_GET_CONFIG"},
-	{0x66, "EC_CMD_KEYSCAN_SEQ_CTRL"},
-	{0x67, "EC_CMD_GET_NEXT_EVENT"},
-	{0x70, "EC_CMD_TEMP_SENSOR_GET_INFO"},
-	{0x87, "EC_CMD_HOST_EVENT_GET_B"},
-	{0x88, "EC_CMD_HOST_EVENT_GET_SMI_MASK"},
-	{0x89, "EC_CMD_HOST_EVENT_GET_SCI_MASK"},
-	{0x8d, "EC_CMD_HOST_EVENT_GET_WAKE_MASK"},
-	{0x8a, "EC_CMD_HOST_EVENT_SET_SMI_MASK"},
-	{0x8b, "EC_CMD_HOST_EVENT_SET_SCI_MASK"},
-	{0x8c, "EC_CMD_HOST_EVENT_CLEAR"},
-	{0x8e, "EC_CMD_HOST_EVENT_SET_WAKE_MASK"},
-	{0x8f, "EC_CMD_HOST_EVENT_CLEAR_B"},
-	{0x90, "EC_CMD_SWITCH_ENABLE_BKLIGHT"},
-	{0x91, "EC_CMD_SWITCH_ENABLE_WIRELESS"},
-	{0x92, "EC_CMD_GPIO_SET"},
-	{0x93, "EC_CMD_GPIO_GET"},
-	{0x94, "EC_CMD_I2C_READ"},
-	{0x95, "EC_CMD_I2C_WRITE"},
-	{0x96, "EC_CMD_CHARGE_CONTROL"},
-	{0x97, "EC_CMD_CONSOLE_SNAPSHOT"},
-	{0x98, "EC_CMD_CONSOLE_READ"},
-	{0x99, "EC_CMD_BATTERY_CUT_OFF"},
-	{0x9a, "EC_CMD_USB_MUX"},
-	{0x9b, "EC_CMD_LDO_SET"},
-	{0x9c, "EC_CMD_LDO_GET"},
-	{0x9d, "EC_CMD_POWER_INFO"},
-	{0x9e, "EC_CMD_I2C_PASSTHRU"},
-	{0x9f, "EC_CMD_HANG_DETECT"},
-	{0xa0, "EC_CMD_CHARGE_STATE"},
-	{0xa1, "EC_CMD_CHARGE_CURRENT_LIMIT"},
-	{0xa2, "EC_CMD_EXT_POWER_CURRENT_LIMIT"},
-	{0xb0, "EC_CMD_SB_READ_WORD"},
-	{0xb1, "EC_CMD_SB_WRITE_WORD"},
-	{0xb2, "EC_CMD_SB_READ_BLOCK"},
-	{0xb3, "EC_CMD_SB_WRITE_BLOCK"},
-	{0xb4, "EC_CMD_BATTERY_VENDOR_PARAM"},
-	{0xb5, "EC_CMD_SB_FW_UPDATE"},
-	{0xd2, "EC_CMD_REBOOT_EC"},
-	{0xd3, "EC_CMD_GET_PANIC_INFO"},
-	{0xd1, "EC_CMD_REBOOT"},
-	{0xdb, "EC_CMD_RESEND_RESPONSE"},
-	{0xdc, "EC_CMD_VERSION0"},
-	{0x100, "EC_CMD_PD_EXCHANGE_STATUS"},
-	{0x104, "EC_CMD_PD_HOST_EVENT_STATUS"},
-	{0x101, "EC_CMD_USB_PD_CONTROL"},
-	{0x102, "EC_CMD_USB_PD_PORTS"},
-	{0x103, "EC_CMD_USB_PD_POWER_INFO"},
-	{0x110, "EC_CMD_USB_PD_FW_UPDATE"},
-	{0x111, "EC_CMD_USB_PD_RW_HASH_ENTRY"},
-	{0x112, "EC_CMD_USB_PD_DEV_INFO"},
-	{0x113, "EC_CMD_USB_PD_DISCOVERY"},
-	{0x114, "EC_CMD_PD_CHARGE_PORT_OVERRIDE"},
-	{0x115, "EC_CMD_PD_GET_LOG_ENTRY"},
-	{0x116, "EC_CMD_USB_PD_GET_AMODE"},
-	{0x117, "EC_CMD_USB_PD_SET_AMODE"},
-	{0x118, "EC_CMD_PD_WRITE_LOG_ENTRY"},
-	{0x200, "EC_CMD_BLOB"},
+	{ 0x00, "EC_CMD_PROTO_VERSION" },
+	{ 0x01, "EC_CMD_HELLO" },
+	{ 0x02, "EC_CMD_GET_VERSION" },
+	{ 0x03, "EC_CMD_READ_TEST" },
+	{ 0x04, "EC_CMD_GET_BUILD_INFO" },
+	{ 0x05, "EC_CMD_GET_CHIP_INFO" },
+	{ 0x06, "EC_CMD_GET_BOARD_VERSION" },
+	{ 0x07, "EC_CMD_READ_MEMMAP" },
+	{ 0x08, "EC_CMD_GET_CMD_VERSIONS" },
+	{ 0x09, "EC_CMD_GET_COMMS_STATUS" },
+	{ 0x0a, "EC_CMD_TEST_PROTOCOL" },
+	{ 0x0b, "EC_CMD_GET_PROTOCOL_INFO" },
+	{ 0x0c, "EC_CMD_GSV_PAUSE_IN_S5" },
+	{ 0x0d, "EC_CMD_GET_FEATURES" },
+	{ 0x10, "EC_CMD_FLASH_INFO" },
+	{ 0x11, "EC_CMD_FLASH_READ" },
+	{ 0x12, "EC_CMD_FLASH_WRITE" },
+	{ 0x13, "EC_CMD_FLASH_ERASE" },
+	{ 0x15, "EC_CMD_FLASH_PROTECT" },
+	{ 0x16, "EC_CMD_FLASH_REGION_INFO" },
+	{ 0x20, "EC_CMD_PWM_GET_FAN_TARGET_RPM" },
+	{ 0x21, "EC_CMD_PWM_SET_FAN_TARGET_RPM" },
+	{ 0x22, "EC_CMD_PWM_GET_KEYBOARD_BACKLIGHT" },
+	{ 0x23, "EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT" },
+	{ 0x24, "EC_CMD_PWM_SET_FAN_DUTY" },
+	{ 0x28, "EC_CMD_LIGHTBAR_CMD" },
+	{ 0x29, "EC_CMD_LED_CONTROL" },
+	{ 0x2a, "EC_CMD_VBOOT_HASH" },
+	{ 0x2b, "EC_CMD_MOTION_SENSE_CMD" },
+	{ 0x2c, "EC_CMD_FORCE_LID_OPEN" },
+	{ 0x30, "EC_CMD_USB_CHARGE_SET_MODE" },
+	{ 0x40, "EC_CMD_PSTORE_INFO" },
+	{ 0x41, "EC_CMD_PSTORE_READ" },
+	{ 0x42, "EC_CMD_PSTORE_WRITE" },
+	{ 0x44, "EC_CMD_RTC_GET_VALUE" },
+	{ 0x45, "EC_CMD_RTC_GET_ALARM" },
+	{ 0x46, "EC_CMD_RTC_SET_VALUE" },
+	{ 0x47, "EC_CMD_RTC_SET_ALARM" },
+	{ 0x48, "EC_CMD_PORT80_LAST_BOOT" },
+	{ 0x48, "EC_CMD_PORT80_READ" },
+	{ 0x50, "EC_CMD_THERMAL_SET_THRESHOLD" },
+	{ 0x51, "EC_CMD_THERMAL_GET_THRESHOLD" },
+	{ 0x52, "EC_CMD_THERMAL_AUTO_FAN_CTRL" },
+	{ 0x53, "EC_CMD_TMP006_GET_CALIBRATION" },
+	{ 0x54, "EC_CMD_TMP006_SET_CALIBRATION" },
+	{ 0x55, "EC_CMD_TMP006_GET_RAW" },
+	{ 0x60, "EC_CMD_MKBP_STATE" },
+	{ 0x61, "EC_CMD_MKBP_INFO" },
+	{ 0x62, "EC_CMD_MKBP_SIMULATE_KEY" },
+	{ 0x64, "EC_CMD_MKBP_SET_CONFIG" },
+	{ 0x65, "EC_CMD_MKBP_GET_CONFIG" },
+	{ 0x66, "EC_CMD_KEYSCAN_SEQ_CTRL" },
+	{ 0x67, "EC_CMD_GET_NEXT_EVENT" },
+	{ 0x70, "EC_CMD_TEMP_SENSOR_GET_INFO" },
+	{ 0x87, "EC_CMD_HOST_EVENT_GET_B" },
+	{ 0x88, "EC_CMD_HOST_EVENT_GET_SMI_MASK" },
+	{ 0x89, "EC_CMD_HOST_EVENT_GET_SCI_MASK" },
+	{ 0x8d, "EC_CMD_HOST_EVENT_GET_WAKE_MASK" },
+	{ 0x8a, "EC_CMD_HOST_EVENT_SET_SMI_MASK" },
+	{ 0x8b, "EC_CMD_HOST_EVENT_SET_SCI_MASK" },
+	{ 0x8c, "EC_CMD_HOST_EVENT_CLEAR" },
+	{ 0x8e, "EC_CMD_HOST_EVENT_SET_WAKE_MASK" },
+	{ 0x8f, "EC_CMD_HOST_EVENT_CLEAR_B" },
+	{ 0x90, "EC_CMD_SWITCH_ENABLE_BKLIGHT" },
+	{ 0x91, "EC_CMD_SWITCH_ENABLE_WIRELESS" },
+	{ 0x92, "EC_CMD_GPIO_SET" },
+	{ 0x93, "EC_CMD_GPIO_GET" },
+	{ 0x94, "EC_CMD_I2C_READ" },
+	{ 0x95, "EC_CMD_I2C_WRITE" },
+	{ 0x96, "EC_CMD_CHARGE_CONTROL" },
+	{ 0x97, "EC_CMD_CONSOLE_SNAPSHOT" },
+	{ 0x98, "EC_CMD_CONSOLE_READ" },
+	{ 0x99, "EC_CMD_BATTERY_CUT_OFF" },
+	{ 0x9a, "EC_CMD_USB_MUX" },
+	{ 0x9b, "EC_CMD_LDO_SET" },
+	{ 0x9c, "EC_CMD_LDO_GET" },
+	{ 0x9d, "EC_CMD_POWER_INFO" },
+	{ 0x9e, "EC_CMD_I2C_PASSTHRU" },
+	{ 0x9f, "EC_CMD_HANG_DETECT" },
+	{ 0xa0, "EC_CMD_CHARGE_STATE" },
+	{ 0xa1, "EC_CMD_CHARGE_CURRENT_LIMIT" },
+	{ 0xa2, "EC_CMD_EXT_POWER_CURRENT_LIMIT" },
+	{ 0xb0, "EC_CMD_SB_READ_WORD" },
+	{ 0xb1, "EC_CMD_SB_WRITE_WORD" },
+	{ 0xb2, "EC_CMD_SB_READ_BLOCK" },
+	{ 0xb3, "EC_CMD_SB_WRITE_BLOCK" },
+	{ 0xb4, "EC_CMD_BATTERY_VENDOR_PARAM" },
+	{ 0xb5, "EC_CMD_SB_FW_UPDATE" },
+	{ 0xd2, "EC_CMD_REBOOT_EC" },
+	{ 0xd3, "EC_CMD_GET_PANIC_INFO" },
+	{ 0xd1, "EC_CMD_REBOOT" },
+	{ 0xdb, "EC_CMD_RESEND_RESPONSE" },
+	{ 0xdc, "EC_CMD_VERSION0" },
+	{ 0x100, "EC_CMD_PD_EXCHANGE_STATUS" },
+	{ 0x104, "EC_CMD_PD_HOST_EVENT_STATUS" },
+	{ 0x101, "EC_CMD_USB_PD_CONTROL" },
+	{ 0x102, "EC_CMD_USB_PD_PORTS" },
+	{ 0x103, "EC_CMD_USB_PD_POWER_INFO" },
+	{ 0x110, "EC_CMD_USB_PD_FW_UPDATE" },
+	{ 0x111, "EC_CMD_USB_PD_RW_HASH_ENTRY" },
+	{ 0x112, "EC_CMD_USB_PD_DEV_INFO" },
+	{ 0x113, "EC_CMD_USB_PD_DISCOVERY" },
+	{ 0x114, "EC_CMD_PD_CHARGE_PORT_OVERRIDE" },
+	{ 0x115, "EC_CMD_PD_GET_LOG_ENTRY" },
+	{ 0x116, "EC_CMD_USB_PD_GET_AMODE" },
+	{ 0x117, "EC_CMD_USB_PD_SET_AMODE" },
+	{ 0x118, "EC_CMD_PD_WRITE_LOG_ENTRY" },
+	{ 0x200, "EC_CMD_BLOB" },
 };
 
 #define ARRAY_SIZE(A) (sizeof(A) / sizeof(A[0]))
@@ -532,15 +512,13 @@ static void scan_commands(uint16_t start, uint16_t stop)
 
 	printf("Supported host commands:\n");
 	for (i = start; i <= stop; i++) {
-
 		if (opt_verbose)
 			printf("Querying CMD %02x\n", i);
 
 		q_vers.cmd = i;
-		if (0 != send_cmd(EC_CMD_GET_CMD_VERSIONS, 1,
-				  &q_vers, sizeof(q_vers),
-				  &ec_resp,
-				  &r_vers, sizeof(r_vers))) {
+		if (0 != send_cmd(EC_CMD_GET_CMD_VERSIONS, 1, &q_vers,
+				  sizeof(q_vers), &ec_resp, &r_vers,
+				  sizeof(r_vers))) {
 			printf("query failed on cmd %02x - aborting\n", i);
 			return;
 		}
@@ -557,8 +535,7 @@ static void scan_commands(uint16_t start, uint16_t stop)
 			break;
 		default:
 			printf("lookup of cmd %02x returned %d %s\n", i,
-			       ec_resp.result,
-			       ec_strerr(ec_resp.result));
+			       ec_resp.result, ec_strerr(ec_resp.result));
 		}
 	}
 }
diff --git a/extra/i2c_pseudo/Documentation.md b/extra/i2c_pseudo/Documentation.md
new file mode 100644
index 0000000000..ebcef6a01e
--- /dev/null
+++ b/extra/i2c_pseudo/Documentation.md
@@ -0,0 +1,279 @@
+# i2c-pseudo driver
+
+Usually I2C adapters are implemented in a kernel driver.  It is also possible to
+implement an adapter in userspace, through the /dev/i2c-pseudo-controller
+interface.  Load module i2c-pseudo for this.
+
+Use cases for this module include:
+
+* Using local I2C device drivers, particularly i2c-dev, with I2C busses on
+  remote systems.  For example, interacting with a Device Under Test (DUT)
+  connected to a Linux host through a debug interface, or interacting with a
+  remote host over a network.
+
+* Implementing I2C device driver tests that are impractical with the i2c-stub
+  module.  For example, when simulating an I2C device where its driver might
+  issue a sequence of reads and writes without interruption, and the value at a
+  certain address must change during the sequence.
+
+This is not intended to replace kernel drivers for actual I2C busses on the
+local host machine.
+
+## Details
+
+Each time /dev/i2c-pseudo-controller is opened, and the correct initialization
+command is written to it (ADAPTER_START), a new I2C adapter is created.  The
+adapter will live until its file descriptor is closed.  Multiple pseudo adapters
+can co-exist simultaneously, controlled by the same or different userspace
+processes.  When an I2C device driver sends an I2C message to a pseudo adapter,
+the message becomes readable from its file descriptor.  If a reply is written
+before the adapter timeout expires, that reply will be sent back to the I2C
+device driver.
+
+Reads and writes are buffered inside i2c-pseudo such that userspace controllers
+may split them up into arbitrarily small chunks.  Multiple commands, or portions
+of multiple commands, may be read or written together.
+
+Blocking I/O is the default.  Non-blocking I/O is supported as well, enabled by
+O_NONBLOCK.  Polling is supported, with or without non-blocking I/O.  A special
+command (ADAPTER_SHUTDOWN) is available to unblock any pollers or blocked
+reads or writes, as a convenience for a multi-threaded or multi-process program
+that wants to exit.
+
+It is safe to access a single controller fd from multiple threads or processes
+concurrently, though it is up to the controller to ensure proper ordering, and
+to ensure that writes for different commands do not get interleaved.  However,
+it is recommended (not required) that controller implementations have only one
+reader thread and one writer thread, which may or may not be the same thread.
+Avoiding multiple readers and multiple writers greatly simplifies controller
+implementation, and there is likely no performance benefit to be gained from
+concurrent reads or concurrent writes due to how i2c-pseudo serializes them
+internally.  After all, on a real I2C bus only one I2C message can be active at
+a time.
+
+Commands are newline-terminated, both those read from the controller device, and
+those written to it.
+
+## Read Commands
+
+The commands that may be read from a pseudo controller device are:
+
+
+---
+
+Read Command
+
+:   `I2C_ADAPTER_NUM <num>`
+
+Example
+
+:   `"I2C_ADAPTER_NUM 5\\n"`
+
+Details
+
+
+---
+
+Read Command
+
+:   `I2C_PSEUDO_ID <num>`
+
+Example
+
+:   `"I2C_PSEUDO_ID 98\\n"`
+
+Details
+
+
+---
+
+Read Command
+
+:   `I2C_BEGIN_XFER`
+
+Example
+
+:   `"I2C_BEGIN_XFER\\n"`
+
+Details
+
+
+---
+
+Read Command
+
+:   `I2C_XFER_REQ <xfer_id> <msg_id> <addr> <flags> <data_len> [<write_byte>[:...]]`
+
+Example
+
+:   `"I2C_XFER_REQ 3 0 0x0070 0x0000 2 AB:9F\\n"`
+
+Example
+
+:   `"I2C_XFER_REQ 3 1 0x0070 0x0001 4\\n"`
+
+Details
+
+
+---
+
+Read Command
+
+:   `I2C_COMMIT_XFER`
+
+Example
+
+:   `"I2C_COMMIT_XFER\\n"`
+
+Details
+
+## Write Commands
+
+The commands that may be written to a pseudo controller device are:
+
+Write Command
+
+:   `SET_ADAPTER_NAME_SUFFIX <suffix>`
+
+Example
+
+:   `"SET_ADAPTER_NAME_SUFFIX My Adapter\\n"`
+
+Details
+
+
+---
+
+Write Command
+
+:   `SET_ADAPTER_TIMEOUT_MS <ms>`
+
+Example
+
+:   `"SET_ADAPTER_TIMEOUT_MS 2000\\n"`
+
+Details
+
+
+---
+
+Write Command
+
+:   `ADAPTER_START`
+
+Example
+
+:   `"ADAPTER_START\\n"`
+
+Details
+
+
+---
+
+Write Command
+
+:   `GET_ADAPTER_NUM`
+
+Example
+
+:   `"GET_ADAPTER_NUM\\n"`
+
+Details
+
+
+---
+
+Write Command
+
+:   `GET_PSEUDO_ID`
+
+Example
+
+:   `"GET_PSEUDO_ID\\n"`
+
+Details
+
+
+---
+
+Write Command
+
+:   `I2C_XFER_REPLY <xfer_id> <msg_id> <addr> <flags> <errno> [<read_byte>[:...]]`
+
+Example
+
+:   `"I2C_XFER_REPLY 3 0 0x0070 0x0000 0\\n"`
+
+Example
+
+:   `"I2C_XFER_REPLY 3 1 0x0070 0x0001 0 0B:29:02:D9\\n"`
+
+Details
+
+
+---
+
+Write Command
+
+:   `ADAPTER_SHUTDOWN`
+
+Example
+
+:   `"ADAPTER_SHUTDOWN\\n"`
+
+Details
+
+## Example userspace controller code
+
+In C, a simple exchange between i2c-pseudo and userspace might look like the
+example below.  Note that for brevity this lacks any error checking and
+handling, which a real pseudo controller implementation should have.
+
+```
+int fd;
+char buf[1<<12];
+
+fd = open("/dev/i2c-pseudo-controller", O_RDWR);
+/* Create the I2C adapter. */
+dprintf(fd, "ADAPTER_START\n");
+
+/*
+ * Pretend this I2C adapter number is 5, and the first I2C xfer sent to it was
+ * from this command (using its i2c-dev interface):
+ * $ i2cset -y 5 0x70 0xC2
+ *
+ * Then this read would place the following into *buf:
+ * "I2C_BEGIN_XFER\n"
+ * "I2C_XFER_REQ 0 0 0x0070 0x0000 1 C2\n"
+ * "I2C_COMMIT_XFER\n"
+ */
+read(fd, buf, sizeof(buf));
+
+/* This reply would allow the i2cset command above to exit successfully. */
+dprintf(fd, "I2C_XFER_REPLY 0 0 0x0070 0x0000 0\n");
+
+/*
+ * Now pretend the next I2C xfer sent to this adapter was from:
+ * $ i2cget -y 5 0x70 0xAB
+ *
+ * Then this read would place the following into *buf:
+ * "I2C_BEGIN_XFER\n"
+ * "I2C_XFER_REQ 1 0 0x0070 0x0000 1 AB\n"
+ * "I2C_XFER_REQ 1 1 0x0070 0x0001 1\n'"
+ * "I2C_COMMIT_XFER\n"
+ */
+read(fd, buf, sizeof(buf));
+
+/*
+ * These replies would allow the i2cget command above to print the following to
+ * stdout and exit successfully:
+ * 0x0b
+ *
+ * Note that it is also valid to write these together in one write().
+ */
+dprintf(fd, "I2C_XFER_REPLY 1 0 0x0070 0x0000 0\n");
+dprintf(fd, "I2C_XFER_REPLY 1 1 0x0070 0x0001 0 0B\n");
+
+/* Destroy the I2C adapter. */
+close(fd);
+```
diff --git a/extra/i2c_pseudo/Documentation.rst b/extra/i2c_pseudo/Documentation.rst
new file mode 100644
index 0000000000..2527eb5337
--- /dev/null
+++ b/extra/i2c_pseudo/Documentation.rst
@@ -0,0 +1,306 @@
+=================
+i2c-pseudo driver
+=================
+
+Usually I2C adapters are implemented in a kernel driver.  It is also possible to
+implement an adapter in userspace, through the /dev/i2c-pseudo-controller
+interface.  Load module i2c-pseudo for this.
+
+Use cases for this module include:
+
+- Using local I2C device drivers, particularly i2c-dev, with I2C busses on
+  remote systems.  For example, interacting with a Device Under Test (DUT)
+  connected to a Linux host through a debug interface, or interacting with a
+  remote host over a network.
+
+- Implementing I2C device driver tests that are impractical with the i2c-stub
+  module.  For example, when simulating an I2C device where its driver might
+  issue a sequence of reads and writes without interruption, and the value at a
+  certain address must change during the sequence.
+
+This is not intended to replace kernel drivers for actual I2C busses on the
+local host machine.
+
+
+Details
+=======
+
+Each time /dev/i2c-pseudo-controller is opened, and the correct initialization
+command is written to it (ADAPTER_START), a new I2C adapter is created.  The
+adapter will live until its file descriptor is closed.  Multiple pseudo adapters
+can co-exist simultaneously, controlled by the same or different userspace
+processes.  When an I2C device driver sends an I2C message to a pseudo adapter,
+the message becomes readable from its file descriptor.  If a reply is written
+before the adapter timeout expires, that reply will be sent back to the I2C
+device driver.
+
+Reads and writes are buffered inside i2c-pseudo such that userspace controllers
+may split them up into arbitrarily small chunks.  Multiple commands, or portions
+of multiple commands, may be read or written together.
+
+Blocking I/O is the default.  Non-blocking I/O is supported as well, enabled by
+O_NONBLOCK.  Polling is supported, with or without non-blocking I/O.  A special
+command (ADAPTER_SHUTDOWN) is available to unblock any pollers or blocked
+reads or writes, as a convenience for a multi-threaded or multi-process program
+that wants to exit.
+
+It is safe to access a single controller fd from multiple threads or processes
+concurrently, though it is up to the controller to ensure proper ordering, and
+to ensure that writes for different commands do not get interleaved.  However,
+it is recommended (not required) that controller implementations have only one
+reader thread and one writer thread, which may or may not be the same thread.
+Avoiding multiple readers and multiple writers greatly simplifies controller
+implementation, and there is likely no performance benefit to be gained from
+concurrent reads or concurrent writes due to how i2c-pseudo serializes them
+internally.  After all, on a real I2C bus only one I2C message can be active at
+a time.
+
+Commands are newline-terminated, both those read from the controller device, and
+those written to it.
+
+
+Read Commands
+=============
+
+The commands that may be read from a pseudo controller device are:
+
+----
+
+:Read Command: ``I2C_ADAPTER_NUM <num>``
+:Example: ``"I2C_ADAPTER_NUM 5\n"``
+:Details:
+  | This is read in response to the GET_ADAPTER_NUM command being written.
+    The number is the I2C adapter number in decimal.  This can only occur after
+    ADAPTER_START, because before that the number is not known and cannot be
+    predicted reliably.
+
+----
+
+:Read Command: ``I2C_PSEUDO_ID <num>``
+:Example: ``"I2C_PSEUDO_ID 98\n"``
+:Details:
+  | This is read in response to the GET_PSEUDO_ID command being written.
+    The number is the pseudo ID in decimal.
+
+----
+
+:Read Command: ``I2C_BEGIN_XFER``
+:Example: ``"I2C_BEGIN_XFER\n"``
+:Details:
+  | This indicates the start of an I2C transaction request, in other words
+    the start of the I2C messages from a single invocation of the I2C adapter's
+    master_xfer() callback.  This can only occur after ADAPTER_START.
+
+----
+
+:Read Command: ``I2C_XFER_REQ <xfer_id> <msg_id> <addr> <flags> <data_len> [<write_byte>[:...]]``
+:Example: ``"I2C_XFER_REQ 3 0 0x0070 0x0000 2 AB:9F\n"``
+:Example: ``"I2C_XFER_REQ 3 1 0x0070 0x0001 4\n"``
+:Details:
+  | This is a single I2C message that a device driver requested be sent on
+    the bus, in other words a single struct i2c_msg from master_xfer() msgs arg.
+  |
+  | The xfer_id is a number representing the whole I2C transaction, thus all
+    I2C_XFER_REQ between a I2C_BEGIN_XFER + I2C_COMMIT_XFER pair share an
+    xfer_id.  The purpose is to ensure replies from the userspace controller are
+    always properly matched to the intended master_xfer() request.  The first
+    transaction has xfer_id 0, and it increases by 1 with each transaction,
+    however it will eventually wrap back to 0 if enough transactions happen
+    during the lifetime of a pseudo adapter.  It is guaranteed to have a large
+    enough maximum value such that there can never be multiple outstanding
+    transactions with the same ID, due to an internal limit in i2c-pseudo that
+    will block master_xfer() calls when the controller is falling behind in its
+    replies.
+  |
+  | The msg_id is a decimal number representing the index of the I2C message
+    within its transaction, in other words the index in master_xfer() \*msgs
+    array arg.  This starts at 0 after each I2C_BEGIN_XFER.  This is guaranteed
+    to not wrap.
+  |
+  | The addr is the hexadecimal I2C address for this I2C message.  The address
+    is right-aligned without any read/write bit.
+  |
+  | The flags are the same bitmask flags used in struct i2c_msg, in hexadecimal
+    form.  Of particular importance to any pseudo controller is the read bit,
+    which is guaranteed to be 0x1 per Linux I2C documentation.
+  |
+  | The data_len is the decimal number of either how many bytes to write that
+    will follow, or how many bytes to read and reply with if this is a read
+    request.
+  |
+  | If this is a read, data_len will be the final field in this command.  If
+    this is a write, data_len will be followed by the given number of
+    colon-separated hexadecimal byte values, in the format shown in the example
+    above.
+
+----
+
+:Read Command: ``I2C_COMMIT_XFER``
+:Example: ``"I2C_COMMIT_XFER\n"``
+:Details:
+  | This indicates the end of an I2C transaction request, in other words the
+    end of the I2C messages from a single invocation of the I2C adapter's
+    master_xfer() callback.  This should be read exactly once after each
+    I2C_BEGIN_XFER, with a varying number of I2C_XFER_REQ between them.
+
+
+Write Commands
+==============
+
+The commands that may be written to a pseudo controller device are:
+
+
+:Write Command: ``SET_ADAPTER_NAME_SUFFIX <suffix>``
+:Example: ``"SET_ADAPTER_NAME_SUFFIX My Adapter\n"``
+:Details:
+  | Sets a suffix to append to the auto-generated I2C adapter name.  Only
+    valid before ADAPTER_START.  A space or other separator character will be
+    placed between the auto-generated name and the suffix, so there is no need
+    to include a leading separator in the suffix.  If the resulting name is too
+    long for the I2C adapter name field, it will be quietly truncated.
+
+----
+
+:Write Command: ``SET_ADAPTER_TIMEOUT_MS <ms>``
+:Example: ``"SET_ADAPTER_TIMEOUT_MS 2000\n"``
+:Details:
+  | Sets the timeout in milliseconds for each I2C transaction, in other words
+    for each master_xfer() reply.  Only valid before ADAPTER_START.  The I2C
+    subsystem will automatically time out transactions based on this setting.
+    Set to 0 to use the I2C subsystem default timeout.  The default timeout for
+    new pseudo adapters where this command has not been used is configurable at
+    i2c-pseudo module load time, and itself has a default independent from the
+    I2C subsystem default.  (If the i2c-pseudo module level default is set to 0,
+    that has the same meaning as here.)
+
+----
+
+:Write Command: ``ADAPTER_START``
+:Example: ``"ADAPTER_START\n"``
+:Details:
+  | Tells i2c-pseudo to actually create the I2C adapter.  Only valid once per
+    open controller fd.
+
+----
+
+:Write Command: ``GET_ADAPTER_NUM``
+:Example: ``"GET_ADAPTER_NUM\n"``
+:Details:
+  | Asks i2c-pseudo for the number assigned to this I2C adapter by the I2C
+    subsystem.  Only valid after ADAPTER_START, because before that the number
+    is not known and cannot be predicted reliably.
+
+----
+
+:Write Command: ``GET_PSEUDO_ID``
+:Example: ``"GET_PSEUDO_ID\n"``
+:Details:
+  | Asks i2c-pseudo for the pseudo ID of this I2C adapter.  The pseudo ID will
+    not be reused for the lifetime of the i2c-pseudo module, unless an internal
+    counter wraps.  I2C clients can use this to track specific instances of
+    pseudo adapters, even when adapter numbers have been reused.
+
+----
+
+:Write Command: ``I2C_XFER_REPLY <xfer_id> <msg_id> <addr> <flags> <errno> [<read_byte>[:...]]``
+:Example: ``"I2C_XFER_REPLY 3 0 0x0070 0x0000 0\n"``
+:Example: ``"I2C_XFER_REPLY 3 1 0x0070 0x0001 0 0B:29:02:D9\n"``
+:Details:
+  | This is how a pseudo controller can reply to I2C_XFER_REQ.  Only valid
+    after I2C_XFER_REQ.  A pseudo controller should write one of these for each
+    I2C_XFER_REQ it reads, including for failures, so that I2C device drivers
+    need not wait for the adapter timeout upon failure (if failure is known
+    sooner).
+  |
+  | The fields in common with I2C_XFER_REQ have their same meanings, and their
+    values are expected to exactly match what was read in the I2C_XFER_REQ
+    command that this is in reply to.
+  |
+  | The errno field is how the pseudo controller indicates success or failure
+    for this I2C message.  A 0 value indicates success.  A non-zero value
+    indicates a failure.  Pseudo controllers are encouraged to use errno values
+    to encode some meaning in a failure response, but that is not a requirement,
+    and the I2C adapter interface does not provide a way to pass per-message
+    errno values to a device driver anyways.
+  |
+  | Pseudo controllers are encouraged to reply in the same order as messages
+    were received, however i2c-pseudo will properly match up out-of-order
+    replies with their original requests.
+
+----
+
+:Write Command: ``ADAPTER_SHUTDOWN``
+:Example: ``"ADAPTER_SHUTDOWN\n"``
+:Details:
+  | This tells i2c-pseudo that the pseudo controller wants to shutdown and
+    intends to close the controller device fd soon.  Use of this is OPTIONAL, it
+    is perfectly valid to close the controller device fd without ever using this
+    command.
+  |
+  | This commands unblocks any blocked controller I/O (reads, writes, or polls),
+    and that is its main purpose.
+  |
+  | Any I2C transactions attempted by a device driver after this command will
+    fail, and will not be passed on to the userspace controller.
+  |
+  | This DOES NOT delete the I2C adapter.  Only closing the fd will do that.
+    That MAY CHANGE in the future, such that this does delete the I2C adapter.
+    (However this will never be required, it will always be okay to simply close
+    the fd.)
+
+
+Example userspace controller code
+=================================
+
+In C, a simple exchange between i2c-pseudo and userspace might look like the
+example below.  Note that for brevity this lacks any error checking and
+handling, which a real pseudo controller implementation should have.
+
+::
+
+  int fd;
+  char buf[1<<12];
+
+  fd = open("/dev/i2c-pseudo-controller", O_RDWR);
+  /* Create the I2C adapter. */
+  dprintf(fd, "ADAPTER_START\n");
+
+  /*
+   * Pretend this I2C adapter number is 5, and the first I2C xfer sent to it was
+   * from this command (using its i2c-dev interface):
+   * $ i2cset -y 5 0x70 0xC2
+   *
+   * Then this read would place the following into *buf:
+   * "I2C_BEGIN_XFER\n"
+   * "I2C_XFER_REQ 0 0 0x0070 0x0000 1 C2\n"
+   * "I2C_COMMIT_XFER\n"
+   */
+  read(fd, buf, sizeof(buf));
+
+  /* This reply would allow the i2cset command above to exit successfully. */
+  dprintf(fd, "I2C_XFER_REPLY 0 0 0x0070 0x0000 0\n");
+
+  /*
+   * Now pretend the next I2C xfer sent to this adapter was from:
+   * $ i2cget -y 5 0x70 0xAB
+   *
+   * Then this read would place the following into *buf:
+   * "I2C_BEGIN_XFER\n"
+   * "I2C_XFER_REQ 1 0 0x0070 0x0000 1 AB\n"
+   * "I2C_XFER_REQ 1 1 0x0070 0x0001 1\n'"
+   * "I2C_COMMIT_XFER\n"
+   */
+  read(fd, buf, sizeof(buf));
+
+  /*
+   * These replies would allow the i2cget command above to print the following to
+   * stdout and exit successfully:
+   * 0x0b
+   *
+   * Note that it is also valid to write these together in one write().
+   */
+  dprintf(fd, "I2C_XFER_REPLY 1 0 0x0070 0x0000 0\n");
+  dprintf(fd, "I2C_XFER_REPLY 1 1 0x0070 0x0001 0 0B\n");
+
+  /* Destroy the I2C adapter. */
+  close(fd);
diff --git a/extra/i2c_pseudo/Makefile b/extra/i2c_pseudo/Makefile
index f7fda6e2de..b53085a970 100644
--- a/extra/i2c_pseudo/Makefile
+++ b/extra/i2c_pseudo/Makefile
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/extra/i2c_pseudo/README b/extra/i2c_pseudo/README
index 96efa062b1..1d1ef75641 100644
--- a/extra/i2c_pseudo/README
+++ b/extra/i2c_pseudo/README
@@ -2,12 +2,16 @@ This directory contains the i2c-pseudo Linux kernel module.
 
 The i2c-pseudo module was written with the intention of being submitted upstream
 in the Linux kernel.  This copy exists because of as 2019-03 this module is not
-yet in the upstream kernel, and even if/when this is included, it may take years
-before making its way to the prepackaged Linux distribution kernels typically
-used by CrOS developers.
+yet in the upstream kernel, and even if/when this is included, it may take a
+long time to get included in prepackaged Linux distribution kernels, especially
+those based on Linux LTS branches.
 
-See Documentation.txt for more information about the module itself.  That file
-is Documentation/i2c/pseudo-controller-interface in the upstream patch.
+See Documentation.rst or Documentation.md for more information about the module
+itself.  The reStructuredText (.rst) file is
+Documentation/i2c/pseudo-controller-interface.rst in the upstream patch.  The
+Markdown file (.md) is generated using rst2md from
+nb2plots (https://github.com/matthew-brett/nb2plots) which uses
+Sphinx (https://www.sphinx-doc.org/).
 
 When servod starts, if the i2c-pseudo module is loaded servod will automatically
 create an I2C pseudo adapter for the Servo I2C bus.  That I2C adapter may then
diff --git a/extra/i2c_pseudo/check_stream_open.sh b/extra/i2c_pseudo/check_stream_open.sh
index da802cb282..70cffd7c73 100755
--- a/extra/i2c_pseudo/check_stream_open.sh
+++ b/extra/i2c_pseudo/check_stream_open.sh
@@ -1,6 +1,6 @@
 #!/bin/sh
 #
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/extra/i2c_pseudo/i2c-pseudo.c b/extra/i2c_pseudo/i2c-pseudo.c
index 325d140663..7cb2904322 100644
--- a/extra/i2c_pseudo/i2c-pseudo.c
+++ b/extra/i2c_pseudo/i2c-pseudo.c
@@ -30,47 +30,47 @@
 #include <linux/wait.h>
 
 /* Minimum i2cp_limit module parameter value. */
-#define I2CP_ADAPTERS_MIN	0
+#define I2CP_ADAPTERS_MIN 0
 /* Maximum i2cp_limit module parameter value. */
-#define I2CP_ADAPTERS_MAX	256
+#define I2CP_ADAPTERS_MAX 256
 /* Default i2cp_limit module parameter value. */
-#define I2CP_DEFAULT_LIMIT	8
+#define I2CP_DEFAULT_LIMIT 8
 /* Value for alloc_chrdev_region() baseminor arg. */
-#define I2CP_CDEV_BASEMINOR	0
-#define I2CP_TIMEOUT_MS_MIN	0
-#define I2CP_TIMEOUT_MS_MAX	(60 * MSEC_PER_SEC)
-#define I2CP_DEFAULT_TIMEOUT_MS	(3 * MSEC_PER_SEC)
+#define I2CP_CDEV_BASEMINOR 0
+#define I2CP_TIMEOUT_MS_MIN 0
+#define I2CP_TIMEOUT_MS_MAX (60 * MSEC_PER_SEC)
+#define I2CP_DEFAULT_TIMEOUT_MS (3 * MSEC_PER_SEC)
 
 /* Used in struct device.kobj.name field. */
-#define I2CP_DEVICE_NAME	"i2c-pseudo-controller"
+#define I2CP_DEVICE_NAME "i2c-pseudo-controller"
 /* Value for alloc_chrdev_region() name arg. */
-#define I2CP_CHRDEV_NAME	"i2c_pseudo"
+#define I2CP_CHRDEV_NAME "i2c_pseudo"
 /* Value for class_create() name arg. */
-#define I2CP_CLASS_NAME		"i2c-pseudo"
+#define I2CP_CLASS_NAME "i2c-pseudo"
 /* Value for alloc_chrdev_region() count arg.  Should always be 1. */
-#define I2CP_CDEV_COUNT		1
-
-#define I2CP_ADAP_START_CMD		"ADAPTER_START"
-#define I2CP_ADAP_SHUTDOWN_CMD		"ADAPTER_SHUTDOWN"
-#define I2CP_GET_NUMBER_CMD		"GET_ADAPTER_NUM"
-#define I2CP_NUMBER_REPLY_CMD		"I2C_ADAPTER_NUM"
-#define I2CP_GET_PSEUDO_ID_CMD		"GET_PSEUDO_ID"
-#define I2CP_PSEUDO_ID_REPLY_CMD	"I2C_PSEUDO_ID"
-#define I2CP_SET_NAME_SUFFIX_CMD	"SET_ADAPTER_NAME_SUFFIX"
-#define I2CP_SET_TIMEOUT_CMD		"SET_ADAPTER_TIMEOUT_MS"
-#define I2CP_BEGIN_MXFER_REQ_CMD	"I2C_BEGIN_XFER"
-#define I2CP_COMMIT_MXFER_REQ_CMD	"I2C_COMMIT_XFER"
-#define I2CP_MXFER_REQ_CMD		"I2C_XFER_REQ"
-#define I2CP_MXFER_REPLY_CMD		"I2C_XFER_REPLY"
+#define I2CP_CDEV_COUNT 1
+
+#define I2CP_ADAP_START_CMD "ADAPTER_START"
+#define I2CP_ADAP_SHUTDOWN_CMD "ADAPTER_SHUTDOWN"
+#define I2CP_GET_NUMBER_CMD "GET_ADAPTER_NUM"
+#define I2CP_NUMBER_REPLY_CMD "I2C_ADAPTER_NUM"
+#define I2CP_GET_PSEUDO_ID_CMD "GET_PSEUDO_ID"
+#define I2CP_PSEUDO_ID_REPLY_CMD "I2C_PSEUDO_ID"
+#define I2CP_SET_NAME_SUFFIX_CMD "SET_ADAPTER_NAME_SUFFIX"
+#define I2CP_SET_TIMEOUT_CMD "SET_ADAPTER_TIMEOUT_MS"
+#define I2CP_BEGIN_MXFER_REQ_CMD "I2C_BEGIN_XFER"
+#define I2CP_COMMIT_MXFER_REQ_CMD "I2C_COMMIT_XFER"
+#define I2CP_MXFER_REQ_CMD "I2C_XFER_REQ"
+#define I2CP_MXFER_REPLY_CMD "I2C_XFER_REPLY"
 
 /* Maximum size of a controller command. */
-#define I2CP_CTRLR_CMD_LIMIT		255
+#define I2CP_CTRLR_CMD_LIMIT 255
 /* Maximum number of controller read responses to allow enqueued at once. */
-#define I2CP_CTRLR_RSP_QUEUE_LIMIT	256
+#define I2CP_CTRLR_RSP_QUEUE_LIMIT 256
 /* The maximum size of a single controller read response. */
-#define I2CP_MAX_MSG_BUF_SIZE		16384
+#define I2CP_MAX_MSG_BUF_SIZE 16384
 /* Maximum size of a controller read or write. */
-#define I2CP_RW_SIZE_LIMIT		1048576
+#define I2CP_RW_SIZE_LIMIT 1048576
 
 /*
  * Marks the end of a controller command or read response.
@@ -85,11 +85,11 @@
  * because of an assertion that the copy size (1) must match the size of the
  * string literal (2 with its trailing null).
  */
-static const char i2cp_ctrlr_end_char		= '\n';
+static const char i2cp_ctrlr_end_char = '\n';
 /* Separator between I2C message header fields in the controller bytestream. */
-static const char i2cp_ctrlr_header_sep_char	= ' ';
+static const char i2cp_ctrlr_header_sep_char = ' ';
 /* Separator between I2C message data bytes in the controller bytestream. */
-static const char i2cp_ctrlr_data_sep_char	= ':';
+static const char i2cp_ctrlr_data_sep_char = ':';
 
 /*
  * This used instead of strcmp(in_str, other_str) because in_str may have null
@@ -99,10 +99,10 @@ static const char i2cp_ctrlr_data_sep_char	= ':';
 #define STRING_NEQ(in_str, in_size, other_str) \
 	(in_size != strlen(other_str) || memcmp(other_str, in_str, in_size))
 
-#define STR_HELPER(num)		#num
-#define STR(num)		STR_HELPER(num)
+#define STR_HELPER(num) #num
+#define STR(num) STR_HELPER(num)
 
-#define CONST_STRLEN(str)	(sizeof(str) - 1)
+#define CONST_STRLEN(str) (sizeof(str) - 1)
 
 /*
  * The number of pseudo I2C adapters permitted.  This default value can be
@@ -207,8 +207,8 @@ struct i2cp_cmd {
 	 * behavior with duplicate command names is undefined, subject to
 	 * change, and subject to become either a build-time or runtime error.
 	 */
-	char *cmd_string;  /* Must be non-NULL. */
-	size_t cmd_size;  /* Must be non-zero. */
+	char *cmd_string; /* Must be non-NULL. */
+	size_t cmd_size; /* Must be non-zero. */
 
 	/*
 	 * This is called once for each I2C pseudo controller to initialize
@@ -308,7 +308,7 @@ struct i2cp_cmd {
 	 * This callback MUST NOT be NULL.
 	 */
 	int (*header_receiver)(void *data, char *in, size_t in_size,
-		bool non_blocking);
+			       bool non_blocking);
 	/*
 	 * This is called to process write command data, when requested by the
 	 * header_receiver() return value.
@@ -347,7 +347,7 @@ struct i2cp_cmd {
 	 * should be NULL.  Otherwise, this callback MUST NOT be NULL.
 	 */
 	int (*data_receiver)(void *data, char *in, size_t in_size,
-		bool non_blocking);
+			     bool non_blocking);
 	/*
 	 * This is called to complete processing of a command, after it has been
 	 * received in its entirety.
@@ -394,7 +394,7 @@ struct i2cp_cmd {
 	 * This callback may be NULL.
 	 */
 	int (*cmd_completer)(void *data, struct i2cp_controller *pdata,
-		int receive_status, bool non_blocking);
+			     int receive_status, bool non_blocking);
 };
 
 /*
@@ -749,13 +749,13 @@ struct i2cp_rsp_master_xfer {
 	 * Always initialize fields below here to zero.  They are for internal
 	 * use by i2cp_rsp_master_xfer_formatter().
 	 */
-	int num_msgs_done;  /* type of @num field */
+	int num_msgs_done; /* type of @num field */
 	size_t buf_start_plus_one;
 };
 
 /* vanprintf - See anprintf() documentation. */
 static ssize_t vanprintf(char **out, ssize_t max_size, gfp_t gfp,
-	const char *fmt, va_list ap)
+			 const char *fmt, va_list ap)
 {
 	int ret;
 	ssize_t buf_size;
@@ -790,9 +790,9 @@ static ssize_t vanprintf(char **out, ssize_t max_size, gfp_t gfp,
 	*out = buf;
 	return ret;
 
- fail_before_args1:
+fail_before_args1:
 	va_end(args1);
- fail_after_args1:
+fail_after_args1:
 	kfree(buf);
 	if (ret >= 0)
 		ret = -ENOTRECOVERABLE;
@@ -833,7 +833,7 @@ static ssize_t vanprintf(char **out, ssize_t max_size, gfp_t gfp,
  *        a bug.
  */
 static ssize_t anprintf(char **out, ssize_t max_size, gfp_t gfp,
-	const char *fmt, ...)
+			const char *fmt, ...)
 {
 	ssize_t ret;
 	va_list args;
@@ -905,24 +905,26 @@ static ssize_t i2cp_rsp_master_xfer_formatter(void *data, char **out)
 		 * that no bytes were lost in kernel->userspace transmission.
 		 */
 		ret = anprintf(&buf_start, I2CP_MAX_MSG_BUF_SIZE, GFP_KERNEL,
-			"%*s%c%u%c%d%c0x%04X%c0x%04X%c%u",
-			(int)strlen(I2CP_MXFER_REQ_CMD), I2CP_MXFER_REQ_CMD,
-			i2cp_ctrlr_header_sep_char, mxfer_rsp->id,
-			i2cp_ctrlr_header_sep_char, mxfer_rsp->num_msgs_done,
-			i2cp_ctrlr_header_sep_char, i2c_msg->addr,
-			i2cp_ctrlr_header_sep_char, i2c_msg->flags,
-			i2cp_ctrlr_header_sep_char, i2c_msg->len);
+			       "%*s%c%u%c%d%c0x%04X%c0x%04X%c%u",
+			       (int)strlen(I2CP_MXFER_REQ_CMD),
+			       I2CP_MXFER_REQ_CMD, i2cp_ctrlr_header_sep_char,
+			       mxfer_rsp->id, i2cp_ctrlr_header_sep_char,
+			       mxfer_rsp->num_msgs_done,
+			       i2cp_ctrlr_header_sep_char, i2c_msg->addr,
+			       i2cp_ctrlr_header_sep_char, i2c_msg->flags,
+			       i2cp_ctrlr_header_sep_char, i2c_msg->len);
 		if (ret > 0) {
 			*out = buf_start;
 			mxfer_rsp->buf_start_plus_one = 1;
-		/*
-		 * If we have a zero return value, it means the output buffer
-		 * was allocated as size one, containing only a terminating null
-		 * character.  This would be a bug given the requested format
-		 * string above.  Also, formatter functions must not mutate *out
-		 * when returning zero.  So if this matches, free the useless
-		 * buffer and return an error.
-		 */
+			/*
+			 * If we have a zero return value, it means the output
+			 * buffer was allocated as size one, containing only a
+			 * terminating null character.  This would be a bug
+			 * given the requested format string above.  Also,
+			 * formatter functions must not mutate *out when
+			 * returning zero.  So if this matches, free the useless
+			 * buffer and return an error.
+			 */
 		} else if (ret == 0) {
 			ret = -EINVAL;
 			kfree(buf_start);
@@ -932,7 +934,7 @@ static ssize_t i2cp_rsp_master_xfer_formatter(void *data, char **out)
 
 	byte_start = mxfer_rsp->buf_start_plus_one - 1;
 	byte_limit = min_t(size_t, i2c_msg->len - byte_start,
-		I2CP_MAX_MSG_BUF_SIZE / 3);
+			   I2CP_MAX_MSG_BUF_SIZE / 3);
 	/* 3 chars per byte == 2 chars for hex + 1 char for separator */
 	buf_size = byte_limit * 3;
 
@@ -943,34 +945,34 @@ static ssize_t i2cp_rsp_master_xfer_formatter(void *data, char **out)
 	}
 
 	for (buf_pos = buf_start, i = 0; i < byte_limit; ++i) {
-		*buf_pos++ = (i || byte_start) ?
-			i2cp_ctrlr_data_sep_char : i2cp_ctrlr_header_sep_char;
-		buf_pos = hex_byte_pack_upper(
-			buf_pos, i2c_msg->buf[byte_start + i]);
+		*buf_pos++ = (i || byte_start) ? i2cp_ctrlr_data_sep_char :
+						 i2cp_ctrlr_header_sep_char;
+		buf_pos = hex_byte_pack_upper(buf_pos,
+					      i2c_msg->buf[byte_start + i]);
 	}
 	*out = buf_start;
 	ret = buf_size;
 	mxfer_rsp->buf_start_plus_one += i;
 
- maybe_free:
+maybe_free:
 	if (ret <= 0) {
 		if (mxfer_rsp->num_msgs_done >= mxfer_rsp->num) {
 			kfree(mxfer_rsp->msgs);
 			kfree(mxfer_rsp);
-		/*
-		 * If we are returning an error but have not consumed all of
-		 * mxfer_rsp yet, we must not attempt to output any more I2C
-		 * messages from the same mxfer_rsp.  Setting mxfer_rsp->msgs to
-		 * NULL tells the remaining invocations with this mxfer_rsp to
-		 * output nothing.
-		 *
-		 * There can be more invocations with the same mxfer_rsp even
-		 * after returning an error here because
-		 * i2cp_adapter_master_xfer() reuses a single
-		 * struct i2cp_rsp_master_xfer (mxfer_rsp) across multiple
-		 * struct i2cp_rsp (rsp_wrappers), one for each struct i2c_msg
-		 * within the mxfer_rsp.
-		 */
+			/*
+			 * If we are returning an error but have not consumed
+			 * all of mxfer_rsp yet, we must not attempt to output
+			 * any more I2C messages from the same mxfer_rsp.
+			 * Setting mxfer_rsp->msgs to NULL tells the remaining
+			 * invocations with this mxfer_rsp to output nothing.
+			 *
+			 * There can be more invocations with the same mxfer_rsp
+			 * even after returning an error here because
+			 * i2cp_adapter_master_xfer() reuses a single
+			 * struct i2cp_rsp_master_xfer (mxfer_rsp) across
+			 * multiple struct i2cp_rsp (rsp_wrappers), one for each
+			 * struct i2c_msg within the mxfer_rsp.
+			 */
 		} else if (ret < 0) {
 			kfree(mxfer_rsp->msgs);
 			mxfer_rsp->msgs = NULL;
@@ -980,7 +982,7 @@ static ssize_t i2cp_rsp_master_xfer_formatter(void *data, char **out)
 }
 
 static ssize_t i2cp_id_show(struct device *dev, struct device_attribute *attr,
-	char *buf)
+			    char *buf)
 {
 	int ret;
 	struct i2c_adapter *adap;
@@ -1039,9 +1041,10 @@ static void i2cp_cmd_mxfer_reply_data_shutdown(void *data)
 
 	cmd_data = data;
 	mutex_lock(&cmd_data->reply_queue_lock);
-	list_for_each(list_ptr, &cmd_data->reply_queue_head) {
+	list_for_each(list_ptr, &cmd_data->reply_queue_head)
+	{
 		mxfer_reply = list_entry(list_ptr, struct i2cp_cmd_mxfer_reply,
-			reply_queue_item);
+					 reply_queue_item);
 		mutex_lock(&mxfer_reply->lock);
 		complete_all(&mxfer_reply->data_filled);
 		mutex_unlock(&mxfer_reply->lock);
@@ -1059,29 +1062,30 @@ static void i2cp_cmd_mxfer_reply_data_destroyer(void *data)
 	kfree(data);
 }
 
-static inline bool i2cp_mxfer_reply_is_current(
-	struct i2cp_cmd_mxfer_reply_data *cmd_data,
-	struct i2cp_cmd_mxfer_reply *mxfer_reply)
+static inline bool
+i2cp_mxfer_reply_is_current(struct i2cp_cmd_mxfer_reply_data *cmd_data,
+			    struct i2cp_cmd_mxfer_reply *mxfer_reply)
 {
 	int i;
 
 	i = cmd_data->current_msg_idx;
-	return cmd_data->current_id == mxfer_reply->id &&
-		i >= 0 && i < mxfer_reply->num_msgs &&
-		cmd_data->current_addr == mxfer_reply->msgs[i].addr &&
-		cmd_data->current_flags == mxfer_reply->msgs[i].flags;
+	return cmd_data->current_id == mxfer_reply->id && i >= 0 &&
+	       i < mxfer_reply->num_msgs &&
+	       cmd_data->current_addr == mxfer_reply->msgs[i].addr &&
+	       cmd_data->current_flags == mxfer_reply->msgs[i].flags;
 }
 
 /* cmd_data->reply_queue_lock must be held. */
-static inline struct i2cp_cmd_mxfer_reply *i2cp_mxfer_reply_find_current(
-	struct i2cp_cmd_mxfer_reply_data *cmd_data)
+static inline struct i2cp_cmd_mxfer_reply *
+i2cp_mxfer_reply_find_current(struct i2cp_cmd_mxfer_reply_data *cmd_data)
 {
 	struct list_head *list_ptr;
 	struct i2cp_cmd_mxfer_reply *mxfer_reply;
 
-	list_for_each(list_ptr, &cmd_data->reply_queue_head) {
+	list_for_each(list_ptr, &cmd_data->reply_queue_head)
+	{
 		mxfer_reply = list_entry(list_ptr, struct i2cp_cmd_mxfer_reply,
-			reply_queue_item);
+					 reply_queue_item);
 		if (i2cp_mxfer_reply_is_current(cmd_data, mxfer_reply))
 			return mxfer_reply;
 	}
@@ -1089,17 +1093,18 @@ static inline struct i2cp_cmd_mxfer_reply *i2cp_mxfer_reply_find_current(
 }
 
 /* cmd_data->reply_queue_lock must NOT already be held. */
-static inline void i2cp_mxfer_reply_update_current(
-	struct i2cp_cmd_mxfer_reply_data *cmd_data)
+static inline void
+i2cp_mxfer_reply_update_current(struct i2cp_cmd_mxfer_reply_data *cmd_data)
 {
 	mutex_lock(&cmd_data->reply_queue_lock);
-	cmd_data->reply_queue_current_item = i2cp_mxfer_reply_find_current(
-		cmd_data);
+	cmd_data->reply_queue_current_item =
+		i2cp_mxfer_reply_find_current(cmd_data);
 	mutex_unlock(&cmd_data->reply_queue_lock);
 }
 
 static int i2cp_cmd_mxfer_reply_header_receiver(void *data, char *in,
-	size_t in_size, bool non_blocking)
+						size_t in_size,
+						bool non_blocking)
 {
 	int ret, reply_errno = 0;
 	struct i2cp_cmd_mxfer_reply_data *cmd_data;
@@ -1218,10 +1223,10 @@ static int i2cp_cmd_mxfer_reply_header_receiver(void *data, char *in,
 }
 
 static int i2cp_cmd_mxfer_reply_data_receiver(void *data, char *in,
-	size_t in_size, bool non_blocking)
+					      size_t in_size, bool non_blocking)
 {
 	int ret;
-	char u8_hex[3] = {0};
+	char u8_hex[3] = { 0 };
 	struct i2cp_cmd_mxfer_reply_data *cmd_data;
 	struct i2cp_cmd_mxfer_reply *mxfer_reply;
 	struct i2c_msg *i2c_msg;
@@ -1333,7 +1338,7 @@ static int i2cp_cmd_mxfer_reply_data_receiver(void *data, char *in,
 		 * I2C_M_DMA_SAFE bit? Do we ever need to use copy_to_user()?
 		 */
 		ret = kstrtou8(u8_hex, 16,
-			&i2c_msg->buf[cmd_data->current_buf_idx]);
+			       &i2c_msg->buf[cmd_data->current_buf_idx]);
 		if (ret < 0)
 			goto unlock;
 		if (i2c_msg->flags & I2C_M_RECV_LEN)
@@ -1346,13 +1351,15 @@ static int i2cp_cmd_mxfer_reply_data_receiver(void *data, char *in,
 	/* Quietly ignore any bytes beyond the buffer size. */
 	ret = 0;
 
- unlock:
+unlock:
 	mutex_unlock(&mxfer_reply->lock);
 	return ret;
 }
 
 static int i2cp_cmd_mxfer_reply_cmd_completer(void *data,
-	struct i2cp_controller *pdata, int receive_status, bool non_blocking)
+					      struct i2cp_controller *pdata,
+					      int receive_status,
+					      bool non_blocking)
 {
 	int ret;
 	struct i2cp_cmd_mxfer_reply_data *cmd_data;
@@ -1399,7 +1406,7 @@ static int i2cp_cmd_mxfer_reply_cmd_completer(void *data,
 	mutex_unlock(&mxfer_reply->lock);
 	ret = 0;
 
- reset_cmd_data:
+reset_cmd_data:
 	cmd_data->state = I2CP_CMD_MXFER_REPLY_STATE_CMD_NEXT;
 	cmd_data->current_id = 0;
 	cmd_data->current_addr = 0;
@@ -1410,7 +1417,8 @@ static int i2cp_cmd_mxfer_reply_cmd_completer(void *data,
 }
 
 static int i2cp_cmd_adap_start_header_receiver(void *data, char *in,
-	size_t in_size, bool non_blocking)
+					       size_t in_size,
+					       bool non_blocking)
 {
 	/*
 	 * No more header fields or data are expected.  This directs any further
@@ -1421,7 +1429,7 @@ static int i2cp_cmd_adap_start_header_receiver(void *data, char *in,
 }
 
 static int i2cp_cmd_adap_start_data_receiver(void *data, char *in,
-	size_t in_size, bool non_blocking)
+					     size_t in_size, bool non_blocking)
 {
 	/*
 	 * Reaching here means the controller wrote extra data in the command
@@ -1432,7 +1440,9 @@ static int i2cp_cmd_adap_start_data_receiver(void *data, char *in,
 }
 
 static int i2cp_cmd_adap_start_cmd_completer(void *data,
-	struct i2cp_controller *pdata, int receive_status, bool non_blocking)
+					     struct i2cp_controller *pdata,
+					     int receive_status,
+					     bool non_blocking)
 {
 	int ret;
 
@@ -1466,13 +1476,14 @@ static int i2cp_cmd_adap_start_cmd_completer(void *data,
 
 	ret = 0;
 
- unlock:
+unlock:
 	mutex_unlock(&pdata->startstop_lock);
 	return ret;
 }
 
 static int i2cp_cmd_adap_shutdown_header_receiver(void *data, char *in,
-	size_t in_size, bool non_blocking)
+						  size_t in_size,
+						  bool non_blocking)
 {
 	/*
 	 * No more header fields or data are expected.  This directs any further
@@ -1483,7 +1494,8 @@ static int i2cp_cmd_adap_shutdown_header_receiver(void *data, char *in,
 }
 
 static int i2cp_cmd_adap_shutdown_data_receiver(void *data, char *in,
-	size_t in_size, bool non_blocking)
+						size_t in_size,
+						bool non_blocking)
 {
 	/*
 	 * Reaching here means the controller wrote extra data in the command
@@ -1494,7 +1506,9 @@ static int i2cp_cmd_adap_shutdown_data_receiver(void *data, char *in,
 }
 
 static int i2cp_cmd_adap_shutdown_cmd_completer(void *data,
-	struct i2cp_controller *pdata, int receive_status, bool non_blocking)
+						struct i2cp_controller *pdata,
+						int receive_status,
+						bool non_blocking)
 {
 	/* Refuse to shutdown if there were errors processing this command. */
 	if (receive_status)
@@ -1512,7 +1526,8 @@ static int i2cp_cmd_adap_shutdown_cmd_completer(void *data,
 }
 
 static int i2cp_cmd_get_number_header_receiver(void *data, char *in,
-	size_t in_size, bool non_blocking)
+					       size_t in_size,
+					       bool non_blocking)
 {
 	/*
 	 * No more header fields or data are expected.  This directs any further
@@ -1523,7 +1538,7 @@ static int i2cp_cmd_get_number_header_receiver(void *data, char *in,
 }
 
 static int i2cp_cmd_get_number_data_receiver(void *data, char *in,
-	size_t in_size, bool non_blocking)
+					     size_t in_size, bool non_blocking)
 {
 	/*
 	 * Reaching here means the controller wrote extra data in the command
@@ -1534,7 +1549,9 @@ static int i2cp_cmd_get_number_data_receiver(void *data, char *in,
 }
 
 static int i2cp_cmd_get_number_cmd_completer(void *data,
-	struct i2cp_controller *pdata, int receive_status, bool non_blocking)
+					     struct i2cp_controller *pdata,
+					     int receive_status,
+					     bool non_blocking)
 {
 	ssize_t ret;
 	int i2c_adap_nr;
@@ -1572,9 +1589,9 @@ static int i2cp_cmd_get_number_cmd_completer(void *data,
 	}
 
 	ret = anprintf(&rsp_buf->buf, I2CP_MAX_MSG_BUF_SIZE, GFP_KERNEL,
-		"%*s%c%d",
-		(int)strlen(I2CP_NUMBER_REPLY_CMD), I2CP_NUMBER_REPLY_CMD,
-		i2cp_ctrlr_header_sep_char, i2c_adap_nr);
+		       "%*s%c%d", (int)strlen(I2CP_NUMBER_REPLY_CMD),
+		       I2CP_NUMBER_REPLY_CMD, i2cp_ctrlr_header_sep_char,
+		       i2c_adap_nr);
 	if (ret < 0) {
 		goto fail_after_rsp_buf_alloc;
 	} else if (ret == 0) {
@@ -1600,17 +1617,18 @@ static int i2cp_cmd_get_number_cmd_completer(void *data,
 	mutex_unlock(&pdata->read_rsp_queue_lock);
 	return 0;
 
- fail_after_buf_alloc:
+fail_after_buf_alloc:
 	kfree(rsp_buf->buf);
- fail_after_rsp_buf_alloc:
+fail_after_rsp_buf_alloc:
 	kfree(rsp_buf);
- fail_after_rsp_wrapper_alloc:
+fail_after_rsp_wrapper_alloc:
 	kfree(rsp_wrapper);
 	return ret;
 }
 
 static int i2cp_cmd_get_pseudo_id_header_receiver(void *data, char *in,
-	size_t in_size, bool non_blocking)
+						  size_t in_size,
+						  bool non_blocking)
 {
 	/*
 	 * No more header fields or data are expected.  This directs any further
@@ -1621,7 +1639,8 @@ static int i2cp_cmd_get_pseudo_id_header_receiver(void *data, char *in,
 }
 
 static int i2cp_cmd_get_pseudo_id_data_receiver(void *data, char *in,
-	size_t in_size, bool non_blocking)
+						size_t in_size,
+						bool non_blocking)
 {
 	/*
 	 * Reaching here means the controller wrote extra data in the command
@@ -1632,7 +1651,9 @@ static int i2cp_cmd_get_pseudo_id_data_receiver(void *data, char *in,
 }
 
 static int i2cp_cmd_get_pseudo_id_cmd_completer(void *data,
-	struct i2cp_controller *pdata, int receive_status, bool non_blocking)
+						struct i2cp_controller *pdata,
+						int receive_status,
+						bool non_blocking)
 {
 	ssize_t ret;
 	struct i2cp_rsp_buffer *rsp_buf;
@@ -1653,9 +1674,9 @@ static int i2cp_cmd_get_pseudo_id_cmd_completer(void *data,
 	}
 
 	ret = anprintf(&rsp_buf->buf, I2CP_MAX_MSG_BUF_SIZE, GFP_KERNEL,
-		"%*s%c%u",
-		(int)strlen(I2CP_PSEUDO_ID_REPLY_CMD), I2CP_PSEUDO_ID_REPLY_CMD,
-		i2cp_ctrlr_header_sep_char, pdata->id);
+		       "%*s%c%u", (int)strlen(I2CP_PSEUDO_ID_REPLY_CMD),
+		       I2CP_PSEUDO_ID_REPLY_CMD, i2cp_ctrlr_header_sep_char,
+		       pdata->id);
 	if (ret < 0) {
 		goto fail_after_rsp_buf_alloc;
 	} else if (ret == 0) {
@@ -1681,11 +1702,11 @@ static int i2cp_cmd_get_pseudo_id_cmd_completer(void *data,
 	mutex_unlock(&pdata->read_rsp_queue_lock);
 	return 0;
 
- fail_after_buf_alloc:
+fail_after_buf_alloc:
 	kfree(rsp_buf->buf);
- fail_after_rsp_buf_alloc:
+fail_after_rsp_buf_alloc:
 	kfree(rsp_buf);
- fail_after_rsp_wrapper_alloc:
+fail_after_rsp_wrapper_alloc:
 	kfree(rsp_wrapper);
 	return ret;
 }
@@ -1707,13 +1728,15 @@ static void i2cp_cmd_set_name_suffix_data_destroyer(void *data)
 }
 
 static int i2cp_cmd_set_name_suffix_header_receiver(void *data, char *in,
-	size_t in_size, bool non_blocking)
+						    size_t in_size,
+						    bool non_blocking)
 {
 	return 1;
 }
 
 static int i2cp_cmd_set_name_suffix_data_receiver(void *data, char *in,
-	size_t in_size, bool non_blocking)
+						  size_t in_size,
+						  bool non_blocking)
 {
 	size_t remaining;
 	struct i2cp_cmd_set_name_suffix_data *cmd_data;
@@ -1730,7 +1753,9 @@ static int i2cp_cmd_set_name_suffix_data_receiver(void *data, char *in,
 }
 
 static int i2cp_cmd_set_name_suffix_cmd_completer(void *data,
-	struct i2cp_controller *pdata, int receive_status, bool non_blocking)
+						  struct i2cp_controller *pdata,
+						  int receive_status,
+						  bool non_blocking)
 {
 	int ret;
 	struct i2cp_cmd_set_name_suffix_data *cmd_data;
@@ -1753,14 +1778,14 @@ static int i2cp_cmd_set_name_suffix_cmd_completer(void *data,
 
 	cmd_data = data;
 	ret = snprintf(pdata->i2c_adapter.name, sizeof(pdata->i2c_adapter.name),
-		"I2C pseudo ID %u %*s", pdata->id,
-		(int)cmd_data->name_suffix_len, cmd_data->name_suffix);
+		       "I2C pseudo ID %u %*s", pdata->id,
+		       (int)cmd_data->name_suffix_len, cmd_data->name_suffix);
 	if (ret < 0)
 		goto unlock;
 
 	ret = 0;
 
- unlock:
+unlock:
 	mutex_unlock(&pdata->startstop_lock);
 	return ret;
 }
@@ -1782,7 +1807,8 @@ static void i2cp_cmd_set_timeout_data_destroyer(void *data)
 }
 
 static int i2cp_cmd_set_timeout_header_receiver(void *data, char *in,
-	size_t in_size, bool non_blocking)
+						size_t in_size,
+						bool non_blocking)
 {
 	int ret;
 	struct i2cp_cmd_set_timeout_data *cmd_data;
@@ -1802,7 +1828,7 @@ static int i2cp_cmd_set_timeout_header_receiver(void *data, char *in,
 }
 
 static int i2cp_cmd_set_timeout_data_receiver(void *data, char *in,
-	size_t in_size, bool non_blocking)
+					      size_t in_size, bool non_blocking)
 {
 	/*
 	 * Reaching here means the controller wrote extra data in the command
@@ -1812,7 +1838,9 @@ static int i2cp_cmd_set_timeout_data_receiver(void *data, char *in,
 }
 
 static int i2cp_cmd_set_timeout_cmd_completer(void *data,
-	struct i2cp_controller *pdata, int receive_status, bool non_blocking)
+					      struct i2cp_controller *pdata,
+					      int receive_status,
+					      bool non_blocking)
 {
 	int ret;
 	struct i2cp_cmd_set_timeout_data *cmd_data;
@@ -1835,7 +1863,7 @@ static int i2cp_cmd_set_timeout_cmd_completer(void *data,
 
 	cmd_data = data;
 	if (cmd_data->timeout_ms < I2CP_TIMEOUT_MS_MIN ||
-		cmd_data->timeout_ms > I2CP_TIMEOUT_MS_MAX) {
+	    cmd_data->timeout_ms > I2CP_TIMEOUT_MS_MAX) {
 		ret = -ERANGE;
 		goto unlock;
 	}
@@ -1843,7 +1871,7 @@ static int i2cp_cmd_set_timeout_cmd_completer(void *data,
 	pdata->i2c_adapter.timeout = msecs_to_jiffies(cmd_data->timeout_ms);
 	ret = 0;
 
- unlock:
+unlock:
 	mutex_unlock(&pdata->startstop_lock);
 	return ret;
 }
@@ -1914,11 +1942,12 @@ static const struct i2cp_cmd i2cp_cmds[] = {
 static inline bool i2cp_poll_in(struct i2cp_controller *pdata)
 {
 	return pdata->rsp_invalidated || pdata->rsp_buf_remaining != 0 ||
-		!list_empty(&pdata->read_rsp_queue_head);
+	       !list_empty(&pdata->read_rsp_queue_head);
 }
 
 static inline int i2cp_fill_rsp_buf(struct i2cp_rsp *rsp_wrapper,
-	struct i2cp_rsp_buffer *rsp_buf, char *contents, size_t size)
+				    struct i2cp_rsp_buffer *rsp_buf,
+				    char *contents, size_t size)
 {
 	rsp_buf->buf = kmemdup(contents, size, GFP_KERNEL);
 	if (!rsp_buf->buf)
@@ -1929,19 +1958,19 @@ static inline int i2cp_fill_rsp_buf(struct i2cp_rsp *rsp_wrapper,
 	return 0;
 }
 
-#define I2CP_FILL_RSP_BUF_WITH_LITERAL(rsp_wrapper, rsp_buf, str_literal)\
-	i2cp_fill_rsp_buf(\
-		rsp_wrapper, rsp_buf, str_literal, strlen(str_literal))
+#define I2CP_FILL_RSP_BUF_WITH_LITERAL(rsp_wrapper, rsp_buf, str_literal) \
+	i2cp_fill_rsp_buf(rsp_wrapper, rsp_buf, str_literal,              \
+			  strlen(str_literal))
 
 static int i2cp_adapter_master_xfer(struct i2c_adapter *adap,
-	struct i2c_msg *msgs, int num)
+				    struct i2c_msg *msgs, int num)
 {
 	int i, ret = 0;
 	long wait_ret;
 	size_t wrappers_length, wrapper_idx = 0, rsp_bufs_idx = 0;
 	struct i2cp_controller *pdata;
 	struct i2cp_rsp **rsp_wrappers;
-	struct i2cp_rsp_buffer *rsp_bufs[2] = {0};
+	struct i2cp_rsp_buffer *rsp_bufs[2] = { 0 };
 	struct i2cp_rsp_master_xfer *mxfer_rsp;
 	struct i2cp_cmd_mxfer_reply_data *cmd_data;
 	struct i2cp_cmd_mxfer_reply *mxfer_reply;
@@ -1966,8 +1995,8 @@ static int i2cp_adapter_master_xfer(struct i2c_adapter *adap,
 	}
 
 	wrappers_length = (size_t)num + ARRAY_SIZE(rsp_bufs);
-	rsp_wrappers = kcalloc(wrappers_length, sizeof(*rsp_wrappers),
-		GFP_KERNEL);
+	rsp_wrappers =
+		kcalloc(wrappers_length, sizeof(*rsp_wrappers), GFP_KERNEL);
 	if (!rsp_wrappers)
 		return -ENOMEM;
 
@@ -1981,15 +2010,15 @@ static int i2cp_adapter_master_xfer(struct i2c_adapter *adap,
 	init_completion(&mxfer_reply->data_filled);
 	mutex_init(&mxfer_reply->lock);
 
-	mxfer_reply->msgs = kcalloc(num, sizeof(*mxfer_reply->msgs),
-		GFP_KERNEL);
+	mxfer_reply->msgs =
+		kcalloc(num, sizeof(*mxfer_reply->msgs), GFP_KERNEL);
 	if (!mxfer_reply->msgs) {
 		ret = -ENOMEM;
 		goto return_after_mxfer_reply_alloc;
 	}
 
-	mxfer_reply->completed = kcalloc(num, sizeof(*mxfer_reply->completed),
-		GFP_KERNEL);
+	mxfer_reply->completed =
+		kcalloc(num, sizeof(*mxfer_reply->completed), GFP_KERNEL);
 	if (!mxfer_reply->completed) {
 		ret = -ENOMEM;
 		goto return_after_reply_msgs_alloc;
@@ -2034,8 +2063,8 @@ static int i2cp_adapter_master_xfer(struct i2c_adapter *adap,
 		if (msgs[i].flags & I2C_M_RD)
 			continue;
 		/* Copy the data, not the address. */
-		mxfer_rsp->msgs[i].buf = kmemdup(msgs[i].buf, msgs[i].len,
-			GFP_KERNEL);
+		mxfer_rsp->msgs[i].buf =
+			kmemdup(msgs[i].buf, msgs[i].len, GFP_KERNEL);
 		if (!mxfer_rsp->msgs[i].buf) {
 			ret = -ENOMEM;
 			goto fail_after_rsp_msgs_alloc;
@@ -2051,7 +2080,8 @@ static int i2cp_adapter_master_xfer(struct i2c_adapter *adap,
 	}
 
 	ret = I2CP_FILL_RSP_BUF_WITH_LITERAL(rsp_wrappers[wrapper_idx++],
-		rsp_bufs[rsp_bufs_idx++], I2CP_BEGIN_MXFER_REQ_CMD);
+					     rsp_bufs[rsp_bufs_idx++],
+					     I2CP_BEGIN_MXFER_REQ_CMD);
 	if (ret < 0)
 		goto fail_after_individual_rsp_wrappers_alloc;
 
@@ -2062,7 +2092,8 @@ static int i2cp_adapter_master_xfer(struct i2c_adapter *adap,
 	}
 
 	ret = I2CP_FILL_RSP_BUF_WITH_LITERAL(rsp_wrappers[wrapper_idx++],
-		rsp_bufs[rsp_bufs_idx++], I2CP_COMMIT_MXFER_REQ_CMD);
+					     rsp_bufs[rsp_bufs_idx++],
+					     I2CP_COMMIT_MXFER_REQ_CMD);
 	if (ret < 0)
 		goto fail_after_individual_rsp_wrappers_alloc;
 
@@ -2082,12 +2113,12 @@ static int i2cp_adapter_master_xfer(struct i2c_adapter *adap,
 
 	mxfer_reply->id = mxfer_rsp->id;
 	list_add_tail(&mxfer_reply->reply_queue_item,
-		&cmd_data->reply_queue_head);
+		      &cmd_data->reply_queue_head);
 	++cmd_data->reply_queue_length;
 
 	for (i = 0; i < wrappers_length; ++i) {
 		list_add_tail(&rsp_wrappers[i]->queue,
-			&pdata->read_rsp_queue_head);
+			      &pdata->read_rsp_queue_head);
 		complete(&pdata->read_rsp_queued);
 	}
 	pdata->read_rsp_queue_length += wrappers_length;
@@ -2132,31 +2163,31 @@ static int i2cp_adapter_master_xfer(struct i2c_adapter *adap,
 	mutex_unlock(&cmd_data->reply_queue_lock);
 	goto return_after_reply_msgs_alloc;
 
- fail_with_reply_queue_lock:
+fail_with_reply_queue_lock:
 	mutex_unlock(&cmd_data->reply_queue_lock);
- fail_with_read_rsp_queue_lock:
+fail_with_read_rsp_queue_lock:
 	mutex_unlock(&pdata->read_rsp_queue_lock);
- fail_after_individual_rsp_wrappers_alloc:
+fail_after_individual_rsp_wrappers_alloc:
 	for (i = 0; i < wrappers_length; ++i)
 		kfree(rsp_wrappers[i]);
- fail_after_rsp_msgs_alloc:
+fail_after_rsp_msgs_alloc:
 	for (i = 0; i < num; ++i)
 		kfree(mxfer_rsp->msgs[i].buf);
 	kfree(mxfer_rsp->msgs);
- fail_after_mxfer_rsp_alloc:
+fail_after_mxfer_rsp_alloc:
 	kfree(mxfer_rsp);
- fail_after_individual_rsp_bufs_alloc:
+fail_after_individual_rsp_bufs_alloc:
 	for (i = 0; i < ARRAY_SIZE(rsp_bufs); ++i) {
 		kfree(rsp_bufs[i]->buf);
 		kfree(rsp_bufs[i]);
 	}
- return_after_reply_completed_alloc:
+return_after_reply_completed_alloc:
 	kfree(mxfer_reply->completed);
- return_after_reply_msgs_alloc:
+return_after_reply_msgs_alloc:
 	kfree(mxfer_reply->msgs);
- return_after_mxfer_reply_alloc:
+return_after_mxfer_reply_alloc:
 	kfree(mxfer_reply);
- return_after_rsp_wrappers_ptrs_alloc:
+return_after_rsp_wrappers_ptrs_alloc:
 	kfree(rsp_wrappers);
 	return ret;
 }
@@ -2183,9 +2214,8 @@ static const struct i2c_algorithm i2cp_algorithm = {
 
 /* this_pseudo->counters.lock must _not_ be held when calling this. */
 static void i2cp_remove_from_counters(struct i2cp_controller *pdata,
-	struct i2cp_device *this_pseudo)
+				      struct i2cp_device *this_pseudo)
 {
-
 	mutex_lock(&this_pseudo->counters.lock);
 	this_pseudo->counters.all_controllers[pdata->index] = NULL;
 	--this_pseudo->counters.count;
@@ -2290,7 +2320,7 @@ static int i2cp_cdev_open(struct inode *inodep, struct file *filep)
 	pdata->i2c_adapter.timeout = msecs_to_jiffies(i2cp_default_timeout_ms);
 	pdata->i2c_adapter.dev.parent = &this_pseudo->device;
 	ret = snprintf(pdata->i2c_adapter.name, sizeof(pdata->i2c_adapter.name),
-		"I2C pseudo ID %u", pdata->id);
+		       "I2C pseudo ID %u", pdata->id);
 	if (ret < 0)
 		goto fail_after_counters_update;
 
@@ -2298,9 +2328,9 @@ static int i2cp_cdev_open(struct inode *inodep, struct file *filep)
 	filep->private_data = pdata;
 	return 0;
 
- fail_after_counters_update:
+fail_after_counters_update:
 	i2cp_remove_from_counters(pdata, this_pseudo);
- fail_after_cmd_data_created:
+fail_after_cmd_data_created:
 	for (i = 0; i < num_cmd_data_created; ++i)
 		if (i2cp_cmds[i].data_destroyer)
 			i2cp_cmds[i].data_destroyer(pdata->cmd_data[i]);
@@ -2317,7 +2347,7 @@ static int i2cp_cdev_release(struct inode *inodep, struct file *filep)
 
 	pdata = filep->private_data;
 	this_pseudo = container_of(pdata->i2c_adapter.dev.parent,
-		struct i2cp_device, device);
+				   struct i2cp_device, device);
 
 	/*
 	 * The select(2) man page makes it clear that the behavior of pending
@@ -2378,7 +2408,8 @@ static int i2cp_cdev_release(struct inode *inodep, struct file *filep)
 /* The caller must hold pdata->rsp_lock. */
 /* Return value is whether or not to continue in calling loop. */
 static bool i2cp_cdev_read_iteration(char __user **buf, size_t *count,
-	ssize_t *ret, bool non_blocking, struct i2cp_controller *pdata)
+				     ssize_t *ret, bool non_blocking,
+				     struct i2cp_controller *pdata)
 {
 	long wait_ret;
 	ssize_t copy_size;
@@ -2450,9 +2481,9 @@ static bool i2cp_cdev_read_iteration(char __user **buf, size_t *count,
 
 		mutex_lock(&pdata->read_rsp_queue_lock);
 		if (!list_empty(&pdata->read_rsp_queue_head))
-			rsp_wrapper = list_first_entry(
-				&pdata->read_rsp_queue_head,
-				struct i2cp_rsp, queue);
+			rsp_wrapper =
+				list_first_entry(&pdata->read_rsp_queue_head,
+						 struct i2cp_rsp, queue);
 		/*
 		 * Avoid holding pdata->read_rsp_queue_lock while
 		 * executing a formatter, allocating memory, or doing
@@ -2543,7 +2574,7 @@ static bool i2cp_cdev_read_iteration(char __user **buf, size_t *count,
 			return false;
 		}
 
- write_end_char:
+	write_end_char:
 		copy_size = sizeof(i2cp_ctrlr_end_char);
 		/*
 		 * This assertion is just in case someone changes
@@ -2554,8 +2585,7 @@ static bool i2cp_cdev_read_iteration(char __user **buf, size_t *count,
 		 * block, we already know it's greater than zero.
 		 */
 		BUILD_BUG_ON(copy_size != 1);
-		copy_ret = copy_to_user(*buf, &i2cp_ctrlr_end_char,
-			copy_size);
+		copy_ret = copy_to_user(*buf, &i2cp_ctrlr_end_char, copy_size);
 		copy_size -= copy_ret;
 		/*
 		 * After writing to the userspace buffer, we need to
@@ -2571,7 +2601,7 @@ static bool i2cp_cdev_read_iteration(char __user **buf, size_t *count,
 	}
 
 	copy_size = max_t(ssize_t, 0,
-		min_t(ssize_t, *count, pdata->rsp_buf_remaining));
+			  min_t(ssize_t, *count, pdata->rsp_buf_remaining));
 	copy_ret = copy_to_user(*buf, pdata->rsp_buf_pos, copy_size);
 	copy_size -= copy_ret;
 	pdata->rsp_buf_remaining -= copy_size;
@@ -2584,14 +2614,14 @@ static bool i2cp_cdev_read_iteration(char __user **buf, size_t *count,
 		pdata->rsp_buf_pos = NULL;
 	}
 
- /*
-  * When jumping here, the following variables should be set:
-  *   copy_ret: Return value from copy_to_user() (bytes not copied).
-  *   copy_size: The number of bytes successfully copied by copy_to_user().  In
-  *       other words, this should be the size arg to copy_to_user() minus its
-  *       return value (bytes not copied).
-  */
- after_copy_to_user:
+/*
+ * When jumping here, the following variables should be set:
+ *   copy_ret: Return value from copy_to_user() (bytes not copied).
+ *   copy_size: The number of bytes successfully copied by copy_to_user().  In
+ *       other words, this should be the size arg to copy_to_user() minus its
+ *       return value (bytes not copied).
+ */
+after_copy_to_user:
 	*ret += copy_size;
 	*count -= copy_size;
 	*buf += copy_size;
@@ -2600,7 +2630,7 @@ static bool i2cp_cdev_read_iteration(char __user **buf, size_t *count,
 }
 
 static ssize_t i2cp_cdev_read(struct file *filep, char __user *buf,
-		size_t count, loff_t *f_ps)
+			      size_t count, loff_t *f_ps)
 {
 	ssize_t ret = 0;
 	bool non_blocking;
@@ -2638,20 +2668,20 @@ static ssize_t i2cp_cdev_read(struct file *filep, char __user *buf,
 		goto unlock;
 	}
 
-	while (count > 0 && i2cp_cdev_read_iteration(
-		&buf, &count, &ret, non_blocking, pdata))
+	while (count > 0 && i2cp_cdev_read_iteration(&buf, &count, &ret,
+						     non_blocking, pdata))
 		;
 
- unlock:
+unlock:
 	mutex_unlock(&pdata->rsp_lock);
 	return ret;
 }
 
 /* Must be called with pdata->cmd_lock held. */
 /* Must never consume past first i2cp_ctrlr_end_char in @start. */
-static ssize_t i2cp_receive_ctrlr_cmd_header(
-	struct i2cp_controller *pdata, char *start, size_t remaining,
-	bool non_blocking)
+static ssize_t i2cp_receive_ctrlr_cmd_header(struct i2cp_controller *pdata,
+					     char *start, size_t remaining,
+					     bool non_blocking)
 {
 	int found_deliminator_char = 0;
 	int i, cmd_idx;
@@ -2665,7 +2695,7 @@ static ssize_t i2cp_receive_ctrlr_cmd_header(
 		    start[i] == i2cp_ctrlr_header_sep_char) {
 			found_deliminator_char = 1;
 			break;
-	}
+		}
 
 	if (i <= buf_remaining) {
 		copy_size = i;
@@ -2695,7 +2725,7 @@ static ssize_t i2cp_receive_ctrlr_cmd_header(
 		for (i = 0; i < ARRAY_SIZE(i2cp_cmds); ++i)
 			if (i2cp_cmds[i].cmd_size == pdata->cmd_size &&
 			    !memcmp(i2cp_cmds[i].cmd_string, pdata->cmd_buf,
-					pdata->cmd_size))
+				    pdata->cmd_size))
 				break;
 		if (i >= ARRAY_SIZE(i2cp_cmds)) {
 			/* unrecognized command */
@@ -2725,7 +2755,7 @@ static ssize_t i2cp_receive_ctrlr_cmd_header(
 		}
 	}
 
- clear_buffer:
+clear_buffer:
 	pdata->cmd_size = 0;
 	/*
 	 * Ensure a trailing null character for the next header_receiver() or
@@ -2745,7 +2775,8 @@ static ssize_t i2cp_receive_ctrlr_cmd_header(
 /* Must be called with pdata->cmd_lock held. */
 /* Must never consume past first i2cp_ctrlr_end_char in @start. */
 static ssize_t i2cp_receive_ctrlr_cmd_data(struct i2cp_controller *pdata,
-	char *start, size_t remaining, bool non_blocking)
+					   char *start, size_t remaining,
+					   bool non_blocking)
 {
 	ssize_t i, ret, size_holder;
 	int cmd_idx;
@@ -2755,13 +2786,14 @@ static ssize_t i2cp_receive_ctrlr_cmd_data(struct i2cp_controller *pdata,
 	if (cmd_idx < 0)
 		return -EINVAL;
 
-	size_holder = min_t(size_t,
+	size_holder = min_t(
+		size_t,
 		(I2CP_CTRLR_CMD_LIMIT -
 		 (I2CP_CTRLR_CMD_LIMIT % pdata->cmd_data_increment)) -
-		pdata->cmd_size,
-		(((pdata->cmd_size + remaining) /
-		  pdata->cmd_data_increment) *
-		 pdata->cmd_data_increment) - pdata->cmd_size);
+			pdata->cmd_size,
+		(((pdata->cmd_size + remaining) / pdata->cmd_data_increment) *
+		 pdata->cmd_data_increment) -
+			pdata->cmd_size);
 
 	/* Size of current buffer plus all remaining write bytes. */
 	size_holder = pdata->cmd_size + remaining;
@@ -2791,8 +2823,10 @@ static ssize_t i2cp_receive_ctrlr_cmd_data(struct i2cp_controller *pdata,
 	 * buffer to end up with if there were unlimited write bytes
 	 * remaining (computed in-line below).
 	 */
-	size_holder = min_t(ssize_t, size_holder, (I2CP_CTRLR_CMD_LIMIT - (
-		I2CP_CTRLR_CMD_LIMIT % pdata->cmd_data_increment)));
+	size_holder =
+		min_t(ssize_t, size_holder,
+		      (I2CP_CTRLR_CMD_LIMIT -
+		       (I2CP_CTRLR_CMD_LIMIT % pdata->cmd_data_increment)));
 	/*
 	 * Subtract the existing buffer size to get the number of bytes we
 	 * actually want to copy from the remaining write bytes in this loop
@@ -2843,7 +2877,7 @@ static ssize_t i2cp_receive_ctrlr_cmd_data(struct i2cp_controller *pdata,
 
 /* Must be called with pdata->cmd_lock held. */
 static int i2cp_receive_ctrlr_cmd_complete(struct i2cp_controller *pdata,
-	bool non_blocking)
+					   bool non_blocking)
 {
 	int ret = 0, cmd_idx;
 
@@ -2851,8 +2885,9 @@ static int i2cp_receive_ctrlr_cmd_complete(struct i2cp_controller *pdata,
 	cmd_idx = pdata->cmd_idx_plus_one - 1;
 
 	if (cmd_idx >= 0 && i2cp_cmds[cmd_idx].cmd_completer) {
-		ret = i2cp_cmds[cmd_idx].cmd_completer(pdata->cmd_data[cmd_idx],
-			pdata, pdata->cmd_receive_status, non_blocking);
+		ret = i2cp_cmds[cmd_idx].cmd_completer(
+			pdata->cmd_data[cmd_idx], pdata,
+			pdata->cmd_receive_status, non_blocking);
 		if (ret > 0)
 			ret = 0;
 	}
@@ -2872,7 +2907,7 @@ static int i2cp_receive_ctrlr_cmd_complete(struct i2cp_controller *pdata,
 }
 
 static ssize_t i2cp_cdev_write(struct file *filep, const char __user *buf,
-		size_t count, loff_t *f_ps)
+			       size_t count, loff_t *f_ps)
 {
 	ssize_t ret = 0;
 	bool non_blocking;
@@ -2949,8 +2984,8 @@ static ssize_t i2cp_cdev_write(struct file *filep, const char __user *buf,
 		start += ret;
 
 		if (ret > 0 && start[-1] == i2cp_ctrlr_end_char) {
-			ret = i2cp_receive_ctrlr_cmd_complete(
-				pdata, non_blocking);
+			ret = i2cp_receive_ctrlr_cmd_complete(pdata,
+							      non_blocking);
 			if (ret < 0)
 				break;
 		}
@@ -2963,7 +2998,7 @@ static ssize_t i2cp_cdev_write(struct file *filep, const char __user *buf,
 		/* If successful the whole write is always consumed. */
 		ret = count;
 
- free_kbuf:
+free_kbuf:
 	kfree(kbuf);
 	return ret;
 }
@@ -3056,7 +3091,7 @@ static const struct file_operations i2cp_fileops = {
 };
 
 static ssize_t i2cp_limit_show(struct device *dev,
-	struct device_attribute *attr, char *buf)
+			       struct device_attribute *attr, char *buf)
 {
 	int ret;
 
@@ -3075,7 +3110,7 @@ static struct device_attribute i2cp_limit_dev_attr = {
 };
 
 static ssize_t i2cp_count_show(struct device *dev,
-	struct device_attribute *attr, char *buf)
+			       struct device_attribute *attr, char *buf)
 {
 	int count, ret;
 	struct i2cp_device *this_pseudo;
@@ -3138,9 +3173,9 @@ static int __init i2cp_init(void)
 	int ret = -1;
 
 	if (i2cp_limit < I2CP_ADAPTERS_MIN || i2cp_limit > I2CP_ADAPTERS_MAX) {
-		pr_err("%s: i2cp_limit=%u, must be in range ["
-			STR(I2CP_ADAPTERS_MIN) ", " STR(I2CP_ADAPTERS_MAX)
-			"]\n", __func__, i2cp_limit);
+		pr_err("%s: i2cp_limit=%u, must be in range [" STR(
+			       I2CP_ADAPTERS_MIN) ", " STR(I2CP_ADAPTERS_MAX) "]\n",
+		       __func__, i2cp_limit);
 		return -EINVAL;
 	}
 
@@ -3151,7 +3186,7 @@ static int __init i2cp_init(void)
 	i2cp_class->dev_groups = i2cp_device_sysfs_groups;
 
 	ret = alloc_chrdev_region(&i2cp_dev_num, I2CP_CDEV_BASEMINOR,
-		I2CP_CDEV_COUNT, I2CP_CHRDEV_NAME);
+				  I2CP_CDEV_COUNT, I2CP_CHRDEV_NAME);
 	if (ret < 0)
 		goto fail_after_class_create;
 
@@ -3171,8 +3206,9 @@ static int __init i2cp_init(void)
 		goto fail_after_device_init;
 
 	mutex_init(&i2cp_device->counters.lock);
-	i2cp_device->counters.all_controllers = kcalloc(i2cp_limit,
-		sizeof(*i2cp_device->counters.all_controllers), GFP_KERNEL);
+	i2cp_device->counters.all_controllers = kcalloc(
+		i2cp_limit, sizeof(*i2cp_device->counters.all_controllers),
+		GFP_KERNEL);
 	if (!i2cp_device->counters.all_controllers) {
 		ret = -ENOMEM;
 		goto fail_after_device_init;
@@ -3187,11 +3223,11 @@ static int __init i2cp_init(void)
 
 	return 0;
 
- fail_after_device_init:
+fail_after_device_init:
 	put_device(&i2cp_device->device);
- fail_after_chrdev_register:
+fail_after_chrdev_register:
 	unregister_chrdev_region(i2cp_dev_num, I2CP_CDEV_COUNT);
- fail_after_class_create:
+fail_after_class_create:
 	i2c_p_class_destroy();
 	return ret;
 }
diff --git a/extra/lightbar/Makefile b/extra/lightbar/Makefile
index ce84428869..628f19ab81 100644
--- a/extra/lightbar/Makefile
+++ b/extra/lightbar/Makefile
@@ -1,4 +1,4 @@
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
+# Copyright 2014 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/extra/lightbar/input.c b/extra/lightbar/input.c
index e6c5485e39..5b605600ea 100644
--- a/extra/lightbar/input.c
+++ b/extra/lightbar/input.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
+ * Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -32,7 +32,7 @@ char *get_input(const char *prompt)
 	return line;
 }
 
-#else  /* no readline */
+#else /* no readline */
 
 char *get_input(const char *prompt)
 {
diff --git a/extra/lightbar/main.c b/extra/lightbar/main.c
index ef011d35f1..321c0c73d2 100644
--- a/extra/lightbar/main.c
+++ b/extra/lightbar/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
+ * Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -55,7 +55,7 @@ void *entry_lightbar(void *ptr)
 /* timespec uses nanoseconds */
 #define TS_USEC 1000L
 #define TS_MSEC 1000000L
-#define TS_SEC  1000000000L
+#define TS_SEC 1000000000L
 
 static void timespec_incr(struct timespec *v, time_t secs, long nsecs)
 {
@@ -66,7 +66,6 @@ static void timespec_incr(struct timespec *v, time_t secs, long nsecs)
 	v->tv_nsec %= TS_SEC;
 }
 
-
 static pthread_mutex_t task_mutex = PTHREAD_MUTEX_INITIALIZER;
 static pthread_cond_t task_cond = PTHREAD_COND_INITIALIZER;
 static uint32_t task_event;
@@ -82,8 +81,8 @@ uint32_t task_wait_event(int timeout_us)
 		clock_gettime(CLOCK_REALTIME, &t);
 		timespec_incr(&t, timeout_us / SECOND, timeout_us * TS_USEC);
 
-		if (ETIMEDOUT == pthread_cond_timedwait(&task_cond,
-							&task_mutex, &t))
+		if (ETIMEDOUT ==
+		    pthread_cond_timedwait(&task_cond, &task_mutex, &t))
 			task_event |= TASK_EVENT_TIMER;
 	} else {
 		pthread_cond_wait(&task_cond, &task_mutex);
@@ -96,7 +95,7 @@ uint32_t task_wait_event(int timeout_us)
 }
 
 void task_set_event(task_id_t tskid, /* always LIGHTBAR */
-			uint32_t event)
+		    uint32_t event)
 {
 	pthread_mutex_lock(&task_mutex);
 	task_event = event;
@@ -104,8 +103,6 @@ void task_set_event(task_id_t tskid, /* always LIGHTBAR */
 	pthread_mutex_unlock(&task_mutex);
 }
 
-
-
 /* Stubbed functions */
 
 void cprintf(int zero, const char *fmt, ...)
@@ -146,7 +143,7 @@ timestamp_t get_time(void)
 		clock_gettime(CLOCK_REALTIME, &t_start);
 	clock_gettime(CLOCK_REALTIME, &t);
 	ret.val = (t.tv_sec - t_start.tv_sec) * SECOND +
-		(t.tv_nsec - t_start.tv_nsec) / TS_USEC;
+		  (t.tv_nsec - t_start.tv_nsec) / TS_USEC;
 	return ret;
 }
 
@@ -162,8 +159,7 @@ uint8_t *system_get_jump_tag(uint16_t tag, int *version, int *size)
 }
 
 /* Copied from util/ectool.c */
-int lb_read_params_from_file(const char *filename,
-			     struct lightbar_params_v1 *p)
+int lb_read_params_from_file(const char *filename, struct lightbar_params_v1 *p)
 {
 	FILE *fp;
 	char buf[80];
@@ -175,46 +171,65 @@ int lb_read_params_from_file(const char *filename,
 
 	fp = fopen(filename, "rb");
 	if (!fp) {
-		fprintf(stderr, "Can't open %s: %s\n",
-			filename, strerror(errno));
+		fprintf(stderr, "Can't open %s: %s\n", filename,
+			strerror(errno));
 		return 1;
 	}
 
 	/* We must read the correct number of params from each line */
-#define READ(N) do {							\
-		line++;							\
-		want = (N);						\
-		got = -1;						\
-		if (!fgets(buf, sizeof(buf), fp))			\
-			goto done;					\
-		got = sscanf(buf, "%i %i %i %i",			\
-			     &val[0], &val[1], &val[2], &val[3]);	\
-		if (want != got)					\
-			goto done;					\
+#define READ(N)                                                             \
+	do {                                                                \
+		line++;                                                     \
+		want = (N);                                                 \
+		got = -1;                                                   \
+		if (!fgets(buf, sizeof(buf), fp))                           \
+			goto done;                                          \
+		got = sscanf(buf, "%i %i %i %i", &val[0], &val[1], &val[2], \
+			     &val[3]);                                      \
+		if (want != got)                                            \
+			goto done;                                          \
 	} while (0)
 
-
 	/* Do it */
-	READ(1); p->google_ramp_up = val[0];
-	READ(1); p->google_ramp_down = val[0];
-	READ(1); p->s3s0_ramp_up = val[0];
-	READ(1); p->s0_tick_delay[0] = val[0];
-	READ(1); p->s0_tick_delay[1] = val[0];
-	READ(1); p->s0a_tick_delay[0] = val[0];
-	READ(1); p->s0a_tick_delay[1] = val[0];
-	READ(1); p->s0s3_ramp_down = val[0];
-	READ(1); p->s3_sleep_for = val[0];
-	READ(1); p->s3_ramp_up = val[0];
-	READ(1); p->s3_ramp_down = val[0];
-	READ(1); p->tap_tick_delay = val[0];
-	READ(1); p->tap_gate_delay = val[0];
-	READ(1); p->tap_display_time = val[0];
-
-	READ(1); p->tap_pct_red = val[0];
-	READ(1); p->tap_pct_green = val[0];
-	READ(1); p->tap_seg_min_on = val[0];
-	READ(1); p->tap_seg_max_on = val[0];
-	READ(1); p->tap_seg_osc = val[0];
+	READ(1);
+	p->google_ramp_up = val[0];
+	READ(1);
+	p->google_ramp_down = val[0];
+	READ(1);
+	p->s3s0_ramp_up = val[0];
+	READ(1);
+	p->s0_tick_delay[0] = val[0];
+	READ(1);
+	p->s0_tick_delay[1] = val[0];
+	READ(1);
+	p->s0a_tick_delay[0] = val[0];
+	READ(1);
+	p->s0a_tick_delay[1] = val[0];
+	READ(1);
+	p->s0s3_ramp_down = val[0];
+	READ(1);
+	p->s3_sleep_for = val[0];
+	READ(1);
+	p->s3_ramp_up = val[0];
+	READ(1);
+	p->s3_ramp_down = val[0];
+	READ(1);
+	p->tap_tick_delay = val[0];
+	READ(1);
+	p->tap_gate_delay = val[0];
+	READ(1);
+	p->tap_display_time = val[0];
+
+	READ(1);
+	p->tap_pct_red = val[0];
+	READ(1);
+	p->tap_pct_green = val[0];
+	READ(1);
+	p->tap_seg_min_on = val[0];
+	READ(1);
+	p->tap_seg_max_on = val[0];
+	READ(1);
+	p->tap_seg_osc = val[0];
 	READ(3);
 	p->tap_idx[0] = val[0];
 	p->tap_idx[1] = val[1];
@@ -298,19 +313,18 @@ int lb_load_program(const char *filename, struct lightbar_program *prog)
 
 	fp = fopen(filename, "rb");
 	if (!fp) {
-		fprintf(stderr, "Can't open %s: %s\n",
-			filename, strerror(errno));
+		fprintf(stderr, "Can't open %s: %s\n", filename,
+			strerror(errno));
 		return 1;
 	}
 
 	rc = fseek(fp, 0, SEEK_END);
 	if (rc) {
-		fprintf(stderr, "Couldn't find end of file %s",
-				filename);
+		fprintf(stderr, "Couldn't find end of file %s", filename);
 		fclose(fp);
 		return 1;
 	}
-	rc = (int) ftell(fp);
+	rc = (int)ftell(fp);
 	if (rc > EC_LB_PROG_LEN) {
 		fprintf(stderr, "File %s is too long, aborting\n", filename);
 		fclose(fp);
diff --git a/extra/lightbar/simulation.h b/extra/lightbar/simulation.h
index edbe5f340e..c77583e6c9 100644
--- a/extra/lightbar/simulation.h
+++ b/extra/lightbar/simulation.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
+ * Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -38,13 +38,12 @@ int fake_consolecmd_lightbar(int argc, char *argv[]);
 #define CONFIG_LIGHTBAR_POWER_RAILS
 #endif
 
-
 /* Stuff that's too interleaved with the rest of the EC to just include */
 
 /* Test an important condition at compile time, not run time */
-#define _BA1_(cond, line) \
-	extern int __build_assertion_ ## line[1 - 2*!(cond)]	\
-	__attribute__ ((unused))
+#define _BA1_(cond, line)                                    \
+	extern int __build_assertion_##line[1 - 2 * !(cond)] \
+		__attribute__((unused))
 #define _BA0_(c, x) _BA1_(c, x)
 #define BUILD_ASSERT(cond) _BA0_(cond, __LINE__)
 
@@ -61,14 +60,14 @@ void cprints(int zero, const char *fmt, ...);
 
 /* Task events */
 #define TASK_EVENT_CUSTOM_BIT(x) BUILD_CHECK_INLINE(BIT(x), BIT(x) & 0x0fffffff)
-#define TASK_EVENT_I2C_IDLE      0x10000000
-#define TASK_EVENT_WAKE          0x20000000
-#define TASK_EVENT_MUTEX         0x40000000
-#define TASK_EVENT_TIMER         0x80000000
+#define TASK_EVENT_I2C_IDLE 0x10000000
+#define TASK_EVENT_WAKE 0x20000000
+#define TASK_EVENT_MUTEX 0x40000000
+#define TASK_EVENT_TIMER 0x80000000
 
 /* Time units in usecs */
-#define MSEC         1000
-#define SECOND    1000000
+#define MSEC 1000
+#define SECOND 1000000
 
 #define TASK_ID_LIGHTBAR 0
 #define CC_LIGHTBAR 0
@@ -103,15 +102,22 @@ int system_add_jump_tag(uint16_t tag, int version, int size, const void *data);
 uint8_t *system_get_jump_tag(uint16_t tag, int *version, int *size);
 
 /* Export unused static functions to avoid compiler warnings. */
-#define DECLARE_HOOK(X, fn, Y) \
-	void fake_hook_##fn(void) { fn(); }
+#define DECLARE_HOOK(X, fn, Y)    \
+	void fake_hook_##fn(void) \
+	{                         \
+		fn();             \
+	}
 
-#define DECLARE_HOST_COMMAND(X, fn, Y) \
+#define DECLARE_HOST_COMMAND(X, fn, Y)                                       \
 	enum ec_status fake_hostcmd_##fn(struct host_cmd_handler_args *args) \
-	{ return fn(args); }
+	{                                                                    \
+		return fn(args);                                             \
+	}
 
-#define DECLARE_CONSOLE_COMMAND(X, fn, Y...) \
+#define DECLARE_CONSOLE_COMMAND(X, fn, Y...)            \
 	int fake_consolecmd_##X(int argc, char *argv[]) \
-	{ return fn(argc, argv); }
+	{                                               \
+		return fn(argc, argv);                  \
+	}
 
-#endif	/* __EXTRA_SIMULATION_H */
+#endif /* __EXTRA_SIMULATION_H */
diff --git a/extra/lightbar/windows.c b/extra/lightbar/windows.c
index 115074363c..e0b14fae42 100644
--- a/extra/lightbar/windows.c
+++ b/extra/lightbar/windows.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
+ * Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -42,8 +42,8 @@ void init_windows(void)
 
 	/* Get a colormap */
 	colormap_id = xcb_generate_id(c);
-	xcb_create_colormap(c, XCB_COLORMAP_ALLOC_NONE,
-			    colormap_id, screen->root, screen->root_visual);
+	xcb_create_colormap(c, XCB_COLORMAP_ALLOC_NONE, colormap_id,
+			    screen->root, screen->root_visual);
 
 	/* Create foreground GC */
 	foreground = xcb_generate_id(c);
@@ -57,16 +57,16 @@ void init_windows(void)
 	mask = XCB_CW_BACK_PIXEL | XCB_CW_EVENT_MASK;
 	values[0] = screen->black_pixel;
 	values[1] = XCB_EVENT_MASK_EXPOSURE | XCB_EVENT_MASK_BUTTON_PRESS;
-	xcb_create_window(c,				 /* Connection */
-			  XCB_COPY_FROM_PARENT,		 /* depth */
-			  win,				 /* window Id */
-			  screen->root,			 /* parent window */
-			  0, 0,				 /* x, y */
-			  win_w, win_h,			 /* width, height */
-			  10,				 /* border_width */
+	xcb_create_window(c, /* Connection */
+			  XCB_COPY_FROM_PARENT, /* depth */
+			  win, /* window Id */
+			  screen->root, /* parent window */
+			  0, 0, /* x, y */
+			  win_w, win_h, /* width, height */
+			  10, /* border_width */
 			  XCB_WINDOW_CLASS_INPUT_OUTPUT, /* class */
-			  screen->root_visual,		 /* visual */
-			  mask, values);		 /* masks */
+			  screen->root_visual, /* visual */
+			  mask, values); /* masks */
 
 	/* Map the window on the screen */
 	xcb_map_window(c, win);
@@ -88,10 +88,10 @@ void cleanup(void)
 
 /* xcb likes 16-bit colors */
 uint16_t leds[NUM_LEDS][3] = {
-	{0xffff, 0x0000, 0x0000},
-	{0x0000, 0xffff, 0x0000},
-	{0x0000, 0x0000, 0xffff},
-	{0xffff, 0xffff, 0x0000},
+	{ 0xffff, 0x0000, 0x0000 },
+	{ 0x0000, 0xffff, 0x0000 },
+	{ 0x0000, 0x0000, 0xffff },
+	{ 0xffff, 0xffff, 0x0000 },
 };
 pthread_mutex_t leds_mutex = PTHREAD_MUTEX_INITIALIZER;
 
@@ -101,10 +101,8 @@ void change_gc_color(uint16_t red, uint16_t green, uint16_t blue)
 	uint32_t values[2];
 	xcb_alloc_color_reply_t *reply;
 
-	reply = xcb_alloc_color_reply(c,
-				      xcb_alloc_color(c, colormap_id,
-						      red, green, blue),
-				      NULL);
+	reply = xcb_alloc_color_reply(
+		c, xcb_alloc_color(c, colormap_id, red, green, blue), NULL);
 	assert(reply);
 
 	mask = XCB_GC_FOREGROUND;
@@ -116,8 +114,8 @@ void change_gc_color(uint16_t red, uint16_t green, uint16_t blue)
 void update_window(void)
 {
 	xcb_segment_t segments[] = {
-		{0, 0, win_w, win_h},
-		{0, win_h, win_w, 0},
+		{ 0, 0, win_w, win_h },
+		{ 0, win_h, win_w, 0 },
 	};
 	xcb_rectangle_t rect;
 	int w = win_w / NUM_LEDS;
@@ -135,8 +133,7 @@ void update_window(void)
 			rect.width = w;
 			rect.height = win_h;
 
-			change_gc_color(copyleds[i][0],
-					copyleds[i][1],
+			change_gc_color(copyleds[i][0], copyleds[i][1],
 					copyleds[i][2]);
 
 			xcb_poly_fill_rectangle(c, win, foreground, 1, &rect);
@@ -184,8 +181,6 @@ void setrgb(int led, int red, int green, int blue)
 /*****************************************************************************/
 /* lb_common stubs */
 
-
-
 /* Brightness serves no purpose here. It's automatic on the Chromebook. */
 static int brightness = 0xc0;
 void lb_set_brightness(unsigned int newval)
@@ -238,14 +233,13 @@ void lb_hc_cmd_dump(struct ec_response_lightbar *out)
 	printf("lightbar is %s\n", fake_power ? "on" : "off");
 	memset(out, fake_power, sizeof(*out));
 };
-void lb_hc_cmd_reg(const struct ec_params_lightbar *in) { };
+void lb_hc_cmd_reg(const struct ec_params_lightbar *in){};
 
 int lb_power(int enabled)
 {
 	return fake_power;
 }
 
-
 /*****************************************************************************/
 /* Event handling stuff */
 
@@ -257,7 +251,6 @@ void *entry_windows(void *ptr)
 	int chg = 1;
 
 	while ((e = xcb_wait_for_event(c))) {
-
 		switch (e->response_type & ~0x80) {
 		case XCB_EXPOSE:
 			ev = (xcb_expose_event_t *)e;
diff --git a/extra/rma_reset/Makefile b/extra/rma_reset/Makefile
index 4a640c5b4c..d4644e91c8 100644
--- a/extra/rma_reset/Makefile
+++ b/extra/rma_reset/Makefile
@@ -1,4 +1,4 @@
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -19,7 +19,7 @@ CFLAGS  := -std=gnu99 \
         -Wredundant-decls \
         -Wmissing-declarations
 
-ifeq ($(DEBUG),1)
+ifneq ($(DEBUG),)
 CFLAGS += -g -O0
 else
 CFLAGS += -O3
diff --git a/extra/rma_reset/board.h b/extra/rma_reset/board.h
index f969ad0c56..38e3e7b382 100644
--- a/extra/rma_reset/board.h
+++ b/extra/rma_reset/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/extra/rma_reset/rma_reset.c b/extra/rma_reset/rma_reset.c
index fe1eb5e909..d437b63f1a 100644
--- a/extra/rma_reset/rma_reset.c
+++ b/extra/rma_reset/rma_reset.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,24 +27,22 @@
 #define EC_COORDINATE_SZ 32
 #define EC_PRIV_KEY_SZ 32
 #define EC_P256_UNCOMPRESSED_PUB_KEY_SZ (EC_COORDINATE_SZ * 2 + 1)
-#define EC_P256_COMPRESSED_PUB_KEY_SZ (EC_COORDINATE_SZ  + 1)
+#define EC_P256_COMPRESSED_PUB_KEY_SZ (EC_COORDINATE_SZ + 1)
 
 #define SERVER_ADDRESS \
 	"https://www.google.com/chromeos/partner/console/cr50reset/request"
 
 /* Test server keys for x25519 and p256 curves. */
 static const uint8_t rma_test_server_x25519_public_key[] = {
-	0x03, 0xae, 0x2d, 0x2c, 0x06, 0x23, 0xe0, 0x73,
-	0x0d, 0xd3, 0xb7, 0x92, 0xac, 0x54, 0xc5, 0xfd,
-	0x7e, 0x9c, 0xf0, 0xa8, 0xeb, 0x7e, 0x2a, 0xb5,
-	0xdb, 0xf4, 0x79, 0x5f, 0x8a, 0x0f, 0x28, 0x3f
+	0x03, 0xae, 0x2d, 0x2c, 0x06, 0x23, 0xe0, 0x73, 0x0d, 0xd3, 0xb7,
+	0x92, 0xac, 0x54, 0xc5, 0xfd, 0x7e, 0x9c, 0xf0, 0xa8, 0xeb, 0x7e,
+	0x2a, 0xb5, 0xdb, 0xf4, 0x79, 0x5f, 0x8a, 0x0f, 0x28, 0x3f
 };
 
 static const uint8_t rma_test_server_x25519_private_key[] = {
-	0x47, 0x3b, 0xa5, 0xdb, 0xc4, 0xbb, 0xd6, 0x77,
-	0x20, 0xbd, 0xd8, 0xbd, 0xc8, 0x7a, 0xbb, 0x07,
-	0x03, 0x79, 0xba, 0x7b, 0x52, 0x8c, 0xec, 0xb3,
-	0x4d, 0xaa, 0x69, 0xf5, 0x65, 0xb4, 0x31, 0xad
+	0x47, 0x3b, 0xa5, 0xdb, 0xc4, 0xbb, 0xd6, 0x77, 0x20, 0xbd, 0xd8,
+	0xbd, 0xc8, 0x7a, 0xbb, 0x07, 0x03, 0x79, 0xba, 0x7b, 0x52, 0x8c,
+	0xec, 0xb3, 0x4d, 0xaa, 0x69, 0xf5, 0x65, 0xb4, 0x31, 0xad
 };
 
 #define RMA_TEST_SERVER_X25519_KEY_ID 0x10
@@ -57,10 +55,9 @@ static const uint8_t rma_test_server_x25519_private_key[] = {
  * openssl ec -in key.pem -text -noout
  */
 static const uint8_t rma_test_server_p256_private_key[] = {
-	0x54, 0xb0, 0x82, 0x92, 0x54, 0x92, 0xfc, 0x4a,
-	0xa7, 0x6b, 0xea, 0x8f, 0x30, 0xcc, 0xf7, 0x3d,
-	0xa2, 0xf6, 0xa7, 0xad, 0xf0, 0xec, 0x7d, 0xe9,
-	0x26, 0x75, 0xd1, 0xec, 0xde, 0x20, 0x8f, 0x81
+	0x54, 0xb0, 0x82, 0x92, 0x54, 0x92, 0xfc, 0x4a, 0xa7, 0x6b, 0xea,
+	0x8f, 0x30, 0xcc, 0xf7, 0x3d, 0xa2, 0xf6, 0xa7, 0xad, 0xf0, 0xec,
+	0x7d, 0xe9, 0x26, 0x75, 0xd1, 0xec, 0xde, 0x20, 0x8f, 0x81
 };
 
 /*
@@ -68,15 +65,12 @@ static const uint8_t rma_test_server_p256_private_key[] = {
  * prefix, 65 bytes total.
  */
 static const uint8_t rma_test_server_p256_public_key[] = {
-	0x04, 0xe7, 0xbe, 0x37, 0xaa, 0x68, 0xca, 0xcc,
-	0x68, 0xf4, 0x8c, 0x56, 0x65, 0x5a, 0xcb, 0xf8,
-	0xf4, 0x65, 0x3c, 0xd3, 0xc6, 0x1b, 0xae, 0xd6,
-	0x51, 0x7a, 0xcc, 0x00, 0x8d, 0x59, 0x6d, 0x1b,
-	0x0a, 0x66, 0xe8, 0x68, 0x5e, 0x6a, 0x82, 0x19,
-	0x81, 0x76, 0x84, 0x92, 0x7f, 0x8d, 0xb2, 0xbe,
-	0xf5, 0x39, 0x50, 0xd5, 0xfe, 0xee, 0x00, 0x67,
-	0xcf, 0x40, 0x5f, 0x68, 0x12, 0x83, 0x4f, 0xa4,
-	0x35
+	0x04, 0xe7, 0xbe, 0x37, 0xaa, 0x68, 0xca, 0xcc, 0x68, 0xf4, 0x8c,
+	0x56, 0x65, 0x5a, 0xcb, 0xf8, 0xf4, 0x65, 0x3c, 0xd3, 0xc6, 0x1b,
+	0xae, 0xd6, 0x51, 0x7a, 0xcc, 0x00, 0x8d, 0x59, 0x6d, 0x1b, 0x0a,
+	0x66, 0xe8, 0x68, 0x5e, 0x6a, 0x82, 0x19, 0x81, 0x76, 0x84, 0x92,
+	0x7f, 0x8d, 0xb2, 0xbe, 0xf5, 0x39, 0x50, 0xd5, 0xfe, 0xee, 0x00,
+	0x67, 0xcf, 0x40, 0x5f, 0x68, 0x12, 0x83, 0x4f, 0xa4, 0x35
 };
 
 #define RMA_TEST_SERVER_P256_KEY_ID 0x20
@@ -84,8 +78,8 @@ static const uint8_t rma_test_server_p256_public_key[] = {
 
 /* Default values which can change based on command line arguments. */
 static uint8_t server_key_id = RMA_TEST_SERVER_X25519_KEY_ID;
-static uint8_t board_id[4] = {'Z', 'Z', 'C', 'R'};
-static uint8_t device_id[8] = {'T', 'H', 'X', 1, 1, 3, 8, 0xfe};
+static uint8_t board_id[4] = { 'Z', 'Z', 'C', 'R' };
+static uint8_t device_id[8] = { 'T', 'H', 'X', 1, 1, 3, 8, 0xfe };
 static uint8_t hw_id[20] = "TESTSAMUS1234";
 
 static char challenge[RMA_CHALLENGE_BUF_SIZE];
@@ -95,20 +89,15 @@ static char *progname;
 static char *short_opts = "a:b:c:d:hpk:tw:";
 static const struct option long_opts[] = {
 	/* name    hasarg *flag val */
-	{"auth_code",  1,   NULL, 'a'},
-	{"board_id",   1,   NULL, 'b'},
-	{"challenge",  1,   NULL, 'c'},
-	{"device_id",  1,   NULL, 'd'},
-	{"help",       0,   NULL, 'h'},
-	{"hw_id",      1,   NULL, 'w'},
-	{"key_id",     1,   NULL, 'k'},
-	{"p256",       0,   NULL, 'p'},
-	{"test",       0,   NULL, 't'},
-	{},
+	{ "auth_code", 1, NULL, 'a' }, { "board_id", 1, NULL, 'b' },
+	{ "challenge", 1, NULL, 'c' }, { "device_id", 1, NULL, 'd' },
+	{ "help", 0, NULL, 'h' },      { "hw_id", 1, NULL, 'w' },
+	{ "key_id", 1, NULL, 'k' },    { "p256", 0, NULL, 'p' },
+	{ "test", 0, NULL, 't' },      {},
 };
 
 void panic_assert_fail(const char *fname, int linenum);
-void rand_bytes(void *buffer, size_t len);
+void trng_rand_bytes(void *buffer, size_t len);
 int safe_memcmp(const void *s1, const void *s2, size_t size);
 
 void panic_assert_fail(const char *fname, int linenum)
@@ -131,7 +120,7 @@ int safe_memcmp(const void *s1, const void *s2, size_t size)
 	return result != 0;
 }
 
-void rand_bytes(void *buffer, size_t len)
+void trng_rand_bytes(void *buffer, size_t len)
 {
 	RAND_bytes(buffer, len);
 }
@@ -173,8 +162,8 @@ static void p256_key_and_secret_seed(uint8_t pub_key[32],
 
 		/* Extract public key into an octal array. */
 		EC_POINT_point2oct(group, EC_KEY_get0_public_key(key),
-				   POINT_CONVERSION_UNCOMPRESSED,
-				   buf, sizeof(buf), NULL);
+				   POINT_CONVERSION_UNCOMPRESSED, buf,
+				   sizeof(buf), NULL);
 
 		/* If Y coordinate is an odd value, we are done. */
 	} while (!(buf[sizeof(buf) - 1] & 1));
@@ -195,8 +184,8 @@ static void p256_key_and_secret_seed(uint8_t pub_key[32],
 	secret_point = EC_POINT_new(group);
 
 	/* Multiply server public key by our private key. */
-	EC_POINT_mul(group, secret_point, 0, pub,
-		     EC_KEY_get0_private_key(key), 0);
+	EC_POINT_mul(group, secret_point, 0, pub, EC_KEY_get0_private_key(key),
+		     0);
 
 	/* Pull the result back into the octal buffer. */
 	EC_POINT_point2oct(group, secret_point, POINT_CONVERSION_UNCOMPRESSED,
@@ -252,9 +241,8 @@ static void p256_calculate_secret(uint8_t secret[32],
 	secret_point = EC_POINT_new(group);
 
 	/* Multiply client's point by our private key. */
-	EC_POINT_mul(group, secret_point, 0,
-		     EC_KEY_get0_public_key(key),
-		     priv, 0);
+	EC_POINT_mul(group, secret_point, 0, EC_KEY_get0_public_key(key), priv,
+		     0);
 
 	/* Pull the result back into the octal buffer. */
 	EC_POINT_point2oct(group, secret_point, POINT_CONVERSION_UNCOMPRESSED,
@@ -274,7 +262,7 @@ static int rma_server_side(const char *generated_challenge)
 
 	/* Convert the challenge back into binary */
 	if (base32_decode(cptr, 8 * sizeof(c), generated_challenge, 9) !=
-		8 * sizeof(c)) {
+	    8 * sizeof(c)) {
 		printf("Error decoding challenge\n");
 		return -1;
 	}
@@ -311,8 +299,8 @@ static int rma_server_side(const char *generated_challenge)
 	 * and DeviceID.
 	 */
 	hmac_SHA256(hmac, secret, sizeof(secret), cptr + 1, sizeof(c) - 1);
-	if (base32_encode(authcode, RMA_AUTHCODE_BUF_SIZE,
-			  hmac, RMA_AUTHCODE_CHARS * 5, 0)) {
+	if (base32_encode(authcode, RMA_AUTHCODE_BUF_SIZE, hmac,
+			  RMA_AUTHCODE_CHARS * 5, 0)) {
 		printf("Error encoding auth code\n");
 		return -1;
 	}
@@ -323,7 +311,7 @@ static int rma_server_side(const char *generated_challenge)
 
 static int rma_create_test_challenge(int p256_mode)
 {
-	uint8_t temp[32];   /* Private key or HMAC */
+	uint8_t temp[32]; /* Private key or HMAC */
 	uint8_t secret_seed[32];
 	struct rma_challenge c;
 	uint8_t *cptr = (uint8_t *)&c;
@@ -334,8 +322,8 @@ static int rma_create_test_challenge(int p256_mode)
 	memset(authcode, 0, sizeof(authcode));
 
 	memset(&c, 0, sizeof(c));
-	c.version_key_id = RMA_CHALLENGE_VKID_BYTE(
-		RMA_CHALLENGE_VERSION, server_key_id);
+	c.version_key_id =
+		RMA_CHALLENGE_VKID_BYTE(RMA_CHALLENGE_VERSION, server_key_id);
 
 	memcpy(&bid, board_id, sizeof(bid));
 	bid = be32toh(bid);
@@ -361,8 +349,8 @@ static int rma_create_test_challenge(int p256_mode)
 	 * and DeviceID.  Those are all in the right order in the challenge
 	 * struct, after the version/key id byte.
 	 */
-	hmac_SHA256(temp, secret_seed, sizeof(secret_seed),
-		    cptr + 1, sizeof(c) - 1);
+	hmac_SHA256(temp, secret_seed, sizeof(secret_seed), cptr + 1,
+		    sizeof(c) - 1);
 	if (base32_encode(authcode, sizeof(authcode), temp,
 			  RMA_AUTHCODE_CHARS * 5, 0))
 		return 1;
@@ -382,7 +370,8 @@ static void dump_key(const char *title, const uint8_t *key, size_t key_size)
 
 	printf("\n\n\%s\n", title);
 	for (i = 0; i < key_size; i++)
-		printf("%02x%c", key[i], ((i + 1) % bytes_per_line) ? ' ':'\n');
+		printf("%02x%c", key[i],
+		       ((i + 1) % bytes_per_line) ? ' ' : '\n');
 
 	if (i % bytes_per_line)
 		printf("\n");
@@ -453,25 +442,26 @@ static void usage(void)
 	       "--device_id <arg> --hw_id <arg> |\n"
 	       "                           --auth_code <arg> |\n"
 	       "                           --challenge <arg>\n"
-		"\n"
-		"This is used to generate the cr50 or server responses for rma "
-		"open.\n"
-		"The cr50 side can be used to generate a challenge response "
-		"and sends authoriztion code to reset device.\n"
-		"The server side can generate an authcode from cr50's "
-		"rma challenge.\n"
-		"\n"
-		"  -c,--challenge    The challenge generated by cr50\n"
-		"  -k,--key_id       Index of the server private key\n"
-		"  -b,--board_id     BoardID type field\n"
-		"  -d,--device_id    Device-unique identifier\n"
-		"  -a,--auth_code    Reset authorization code\n"
-		"  -w,--hw_id        Hardware id\n"
-		"  -h,--help         Show this message\n"
-		"  -p,--p256         Use prime256v1 curve instead of x25519\n"
-		"  -t,--test         "
-			"Generate challenge using default test inputs\n"
-	       "\n", progname);
+	       "\n"
+	       "This is used to generate the cr50 or server responses for rma "
+	       "open.\n"
+	       "The cr50 side can be used to generate a challenge response "
+	       "and sends authoriztion code to reset device.\n"
+	       "The server side can generate an authcode from cr50's "
+	       "rma challenge.\n"
+	       "\n"
+	       "  -c,--challenge    The challenge generated by cr50\n"
+	       "  -k,--key_id       Index of the server private key\n"
+	       "  -b,--board_id     BoardID type field\n"
+	       "  -d,--device_id    Device-unique identifier\n"
+	       "  -a,--auth_code    Reset authorization code\n"
+	       "  -w,--hw_id        Hardware id\n"
+	       "  -h,--help         Show this message\n"
+	       "  -p,--p256         Use prime256v1 curve instead of x25519\n"
+	       "  -t,--test         "
+	       "Generate challenge using default test inputs\n"
+	       "\n",
+	       progname);
 }
 
 static int atoh(char *v)
@@ -498,7 +488,7 @@ static int set_server_key_id(char *id)
 		return 1;
 
 	/* verify digits */
-	if (!isxdigit(*id) || !isxdigit(*(id+1)))
+	if (!isxdigit(*id) || !isxdigit(*(id + 1)))
 		return 1;
 
 	server_key_id = atoh(id);
@@ -520,7 +510,7 @@ static int set_board_id(char *id)
 			return 1;
 
 	for (i = 0; i < 4; i++)
-		board_id[i] = atoh((id + (i*2)));
+		board_id[i] = atoh((id + (i * 2)));
 
 	return 0;
 }
@@ -538,7 +528,7 @@ static int set_device_id(char *id)
 			return 1;
 
 	for (i = 0; i < 8; i++)
-		device_id[i] = atoh((id + (i*2)));
+		device_id[i] = atoh((id + (i * 2)));
 
 	return 0;
 }
@@ -635,14 +625,14 @@ int main(int argc, char **argv)
 		case 'h':
 			usage();
 			return 0;
-		case 0:                         /* auto-handled option */
+		case 0: /* auto-handled option */
 			break;
 		case '?':
 			if (optopt)
 				printf("Unrecognized option: -%c\n", optopt);
 			else
 				printf("Unrecognized option: %s\n",
-							argv[optind - 1]);
+				       argv[optind - 1]);
 			break;
 		case ':':
 			printf("Missing argument to %s\n", argv[optind - 1]);
@@ -683,7 +673,7 @@ int main(int argc, char **argv)
 			if (!k_flag || !b_flag || !d_flag || !w_flag) {
 				printf("server-side: Flag -c is mandatory\n");
 				printf("cr50-side: Flags -k, -b, -d, and -w "
-					"are mandatory\n");
+				       "are mandatory\n");
 				return 1;
 			}
 		}
diff --git a/extra/sps_errs/Makefile b/extra/sps_errs/Makefile
index 12224ad803..b25eecbdab 100644
--- a/extra/sps_errs/Makefile
+++ b/extra/sps_errs/Makefile
@@ -1,4 +1,4 @@
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/extra/sps_errs/prog.c b/extra/sps_errs/prog.c
index b649199068..bf44dd182c 100644
--- a/extra/sps_errs/prog.c
+++ b/extra/sps_errs/prog.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,7 +23,7 @@ static struct mpsse_context *mpsse;
 /* enum ec_status meaning */
 static const char *ec_strerr(enum ec_status r)
 {
-	static const char * const strs[] = {
+	static const char *const strs[] = {
 		"SUCCESS",
 		"INVALID_COMMAND",
 		"ERROR",
@@ -48,10 +48,9 @@ static const char *ec_strerr(enum ec_status r)
 	return "<undefined result>";
 };
 
-
-/****************************************************************************
- * Debugging output
- */
+	/****************************************************************************
+	 * Debugging output
+	 */
 
 #define LINELEN 16
 
@@ -65,8 +64,7 @@ static void showline(uint8_t *buf, int len)
 		printf("   ");
 	printf("    ");
 	for (i = 0; i < len; i++)
-		printf("%c",
-		       (buf[i] >= ' ' && buf[i] <= '~') ? buf[i] : '.');
+		printf("%c", (buf[i] >= ' ' && buf[i] <= '~') ? buf[i] : '.');
 	printf("\n");
 }
 
@@ -105,8 +103,8 @@ static uint8_t txbuf[128];
  * Load the output buffer with a proto v3 request (header, then data, with
  * checksum correct in header).
  */
-static size_t prepare_request(int cmd, int version,
-			      const uint8_t *data, size_t data_len)
+static size_t prepare_request(int cmd, int version, const uint8_t *data,
+			      size_t data_len)
 {
 	struct ec_host_request *request;
 	size_t i, total_len;
@@ -114,8 +112,8 @@ static size_t prepare_request(int cmd, int version,
 
 	total_len = sizeof(*request) + data_len;
 	if (total_len > sizeof(txbuf)) {
-		printf("Request too large (%zd > %zd)\n",
-		       total_len, sizeof(txbuf));
+		printf("Request too large (%zd > %zd)\n", total_len,
+		       sizeof(txbuf));
 		return -1;
 	}
 
@@ -139,7 +137,6 @@ static size_t prepare_request(int cmd, int version,
 	return total_len;
 }
 
-
 /* Timeout flag, so we don't wait forever */
 static int timedout;
 static void alarm_handler(int sig)
@@ -151,11 +148,8 @@ static void alarm_handler(int sig)
  * Send command, wait for result. Return zero if communication succeeded; check
  * response to see if the EC liked the command.
  */
-static int send_cmd(int cmd, int version,
-		    void *outbuf,
-		    size_t outsize,
-		    struct ec_host_response *hdr,
-		    void *bodydest,
+static int send_cmd(int cmd, int version, void *outbuf, size_t outsize,
+		    struct ec_host_response *hdr, void *bodydest,
 		    size_t bodylen)
 {
 	uint8_t *tptr, *hptr = 0, *bptr = 0;
@@ -166,15 +160,13 @@ static int send_cmd(int cmd, int version,
 	size_t bytes_left = stop_after;
 	size_t bytes_sent = 0;
 
-
 	/* Load up the txbuf with the stuff to send */
 	len = prepare_request(cmd, version, outbuf, outsize);
 	if (len < 0)
 		return -1;
 
 	if (MPSSE_OK != Start(mpsse)) {
-		fprintf(stderr, "Start failed: %s\n",
-			ErrorString(mpsse));
+		fprintf(stderr, "Start failed: %s\n", ErrorString(mpsse));
 		return -1;
 	}
 
@@ -189,8 +181,7 @@ static int send_cmd(int cmd, int version,
 	bytes_left -= len;
 	bytes_sent += len;
 	if (!tptr) {
-		fprintf(stderr, "Transfer failed: %s\n",
-			ErrorString(mpsse));
+		fprintf(stderr, "Transfer failed: %s\n", ErrorString(mpsse));
 		goto out;
 	}
 
@@ -278,8 +269,7 @@ static int send_cmd(int cmd, int version,
 	bytes_left -= len;
 	bytes_sent += len;
 	if (!hptr) {
-		fprintf(stderr, "Read failed: %s\n",
-			ErrorString(mpsse));
+		fprintf(stderr, "Read failed: %s\n", ErrorString(mpsse));
 		goto out;
 	}
 	show("Header(%d):\n", hptr, sizeof(*hdr));
@@ -288,14 +278,12 @@ static int send_cmd(int cmd, int version,
 	/* Check the header */
 	if (hdr->struct_version != EC_HOST_RESPONSE_VERSION) {
 		printf("HEY: response version %d (should be %d)\n",
-		       hdr->struct_version,
-		       EC_HOST_RESPONSE_VERSION);
+		       hdr->struct_version, EC_HOST_RESPONSE_VERSION);
 		goto out;
 	}
 
 	if (hdr->data_len > bodylen) {
-		printf("HEY: response data_len %d is > %zd\n",
-		       hdr->data_len,
+		printf("HEY: response data_len %d is > %zd\n", hdr->data_len,
 		       bodylen);
 		goto out;
 	}
@@ -341,15 +329,13 @@ out:
 		free(bptr);
 
 	if (MPSSE_OK != Stop(mpsse)) {
-		fprintf(stderr, "Stop failed: %s\n",
-			ErrorString(mpsse));
+		fprintf(stderr, "Stop failed: %s\n", ErrorString(mpsse));
 		return -1;
 	}
 
 	return 0;
 }
 
-
 /****************************************************************************/
 
 /**
@@ -372,10 +358,7 @@ static int hello(void)
 	p.in_data = 0xa5a5a5a5;
 	expected = p.in_data + 0x01020304;
 
-	retval = send_cmd(EC_CMD_HELLO, 0,
-			  &p, sizeof(p),
-			  &resp,
-			  &r, sizeof(r));
+	retval = send_cmd(EC_CMD_HELLO, 0, &p, sizeof(p), &resp, &r, sizeof(r));
 
 	if (retval) {
 		printf("Transmission error\n");
@@ -383,14 +366,13 @@ static int hello(void)
 	}
 
 	if (EC_RES_SUCCESS != resp.result) {
-		printf("EC result is %d: %s\n",
-		       resp.result, ec_strerr(resp.result));
+		printf("EC result is %d: %s\n", resp.result,
+		       ec_strerr(resp.result));
 		return -1;
 	}
 
-	printf("sent %08x, expected %08x, got %08x => %s\n",
-	       p.in_data, expected, r.out_data,
-	       expected == r.out_data ? "yay" : "boo");
+	printf("sent %08x, expected %08x, got %08x => %s\n", p.in_data,
+	       expected, r.out_data, expected == r.out_data ? "yay" : "boo");
 
 	return !(expected == r.out_data);
 }
diff --git a/extra/stack_analyzer/run_tests.sh b/extra/stack_analyzer/run_tests.sh
index 5662f60b8b..d5e65045c3 100755
--- a/extra/stack_analyzer/run_tests.sh
+++ b/extra/stack_analyzer/run_tests.sh
@@ -1,6 +1,6 @@
 #!/bin/bash
 #
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/extra/stack_analyzer/stack_analyzer.py b/extra/stack_analyzer/stack_analyzer.py
index 77d16d5450..2431545c6a 100755
--- a/extra/stack_analyzer/stack_analyzer.py
+++ b/extra/stack_analyzer/stack_analyzer.py
@@ -1,11 +1,7 @@
 #!/usr/bin/env python3
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
 
 """Statically analyze stack usage of EC firmware.
 
@@ -25,1848 +21,2090 @@ import ctypes
 import os
 import re
 import subprocess
-import yaml
 
+import yaml  # pylint:disable=import-error
 
-SECTION_RO = 'RO'
-SECTION_RW = 'RW'
+SECTION_RO = "RO"
+SECTION_RW = "RW"
 # Default size of extra stack frame needed by exception context switch.
 # This value is for cortex-m with FPU enabled.
 DEFAULT_EXCEPTION_FRAME_SIZE = 224
 
 
 class StackAnalyzerError(Exception):
-  """Exception class for stack analyzer utility."""
+    """Exception class for stack analyzer utility."""
 
 
 class TaskInfo(ctypes.Structure):
-  """Taskinfo ctypes structure.
-
-  The structure definition is corresponding to the "struct taskinfo"
-  in "util/export_taskinfo.so.c".
-  """
-  _fields_ = [('name', ctypes.c_char_p),
-              ('routine', ctypes.c_char_p),
-              ('stack_size', ctypes.c_uint32)]
+    """Taskinfo ctypes structure.
 
+    The structure definition is corresponding to the "struct taskinfo"
+    in "util/export_taskinfo.so.c".
+    """
 
-class Task(object):
-  """Task information.
+    _fields_ = [
+        ("name", ctypes.c_char_p),
+        ("routine", ctypes.c_char_p),
+        ("stack_size", ctypes.c_uint32),
+    ]
 
-  Attributes:
-    name: Task name.
-    routine_name: Routine function name.
-    stack_max_size: Max stack size.
-    routine_address: Resolved routine address. None if it hasn't been resolved.
-  """
 
-  def __init__(self, name, routine_name, stack_max_size, routine_address=None):
-    """Constructor.
+class Task(object):
+    """Task information.
 
-    Args:
+    Attributes:
       name: Task name.
       routine_name: Routine function name.
       stack_max_size: Max stack size.
-      routine_address: Resolved routine address.
-    """
-    self.name = name
-    self.routine_name = routine_name
-    self.stack_max_size = stack_max_size
-    self.routine_address = routine_address
-
-  def __eq__(self, other):
-    """Task equality.
-
-    Args:
-      other: The compared object.
-
-    Returns:
-      True if equal, False if not.
+      routine_address: Resolved routine address. None if it hasn't been resolved.
     """
-    if not isinstance(other, Task):
-      return False
 
-    return (self.name == other.name and
-            self.routine_name == other.routine_name and
-            self.stack_max_size == other.stack_max_size and
-            self.routine_address == other.routine_address)
+    def __init__(
+        self, name, routine_name, stack_max_size, routine_address=None
+    ):
+        """Constructor.
+
+        Args:
+          name: Task name.
+          routine_name: Routine function name.
+          stack_max_size: Max stack size.
+          routine_address: Resolved routine address.
+        """
+        self.name = name
+        self.routine_name = routine_name
+        self.stack_max_size = stack_max_size
+        self.routine_address = routine_address
+
+    def __eq__(self, other):
+        """Task equality.
+
+        Args:
+          other: The compared object.
+
+        Returns:
+          True if equal, False if not.
+        """
+        if not isinstance(other, Task):
+            return False
+
+        return (
+            self.name == other.name
+            and self.routine_name == other.routine_name
+            and self.stack_max_size == other.stack_max_size
+            and self.routine_address == other.routine_address
+        )
 
 
 class Symbol(object):
-  """Symbol information.
+    """Symbol information.
 
-  Attributes:
-    address: Symbol address.
-    symtype: Symbol type, 'O' (data, object) or 'F' (function).
-    size: Symbol size.
-    name: Symbol name.
-  """
-
-  def __init__(self, address, symtype, size, name):
-    """Constructor.
-
-    Args:
+    Attributes:
       address: Symbol address.
-      symtype: Symbol type.
+      symtype: Symbol type, 'O' (data, object) or 'F' (function).
       size: Symbol size.
       name: Symbol name.
     """
-    assert symtype in ['O', 'F']
-    self.address = address
-    self.symtype = symtype
-    self.size = size
-    self.name = name
 
-  def __eq__(self, other):
-    """Symbol equality.
-
-    Args:
-      other: The compared object.
-
-    Returns:
-      True if equal, False if not.
-    """
-    if not isinstance(other, Symbol):
-      return False
-
-    return (self.address == other.address and
-            self.symtype == other.symtype and
-            self.size == other.size and
-            self.name == other.name)
+    def __init__(self, address, symtype, size, name):
+        """Constructor.
+
+        Args:
+          address: Symbol address.
+          symtype: Symbol type.
+          size: Symbol size.
+          name: Symbol name.
+        """
+        assert symtype in ["O", "F"]
+        self.address = address
+        self.symtype = symtype
+        self.size = size
+        self.name = name
+
+    def __eq__(self, other):
+        """Symbol equality.
+
+        Args:
+          other: The compared object.
+
+        Returns:
+          True if equal, False if not.
+        """
+        if not isinstance(other, Symbol):
+            return False
+
+        return (
+            self.address == other.address
+            and self.symtype == other.symtype
+            and self.size == other.size
+            and self.name == other.name
+        )
 
 
 class Callsite(object):
-  """Function callsite.
-
-  Attributes:
-    address: Address of callsite location. None if it is unknown.
-    target: Callee address. None if it is unknown.
-    is_tail: A bool indicates that it is a tailing call.
-    callee: Resolved callee function. None if it hasn't been resolved.
-  """
+    """Function callsite.
 
-  def __init__(self, address, target, is_tail, callee=None):
-    """Constructor.
-
-    Args:
+    Attributes:
       address: Address of callsite location. None if it is unknown.
       target: Callee address. None if it is unknown.
-      is_tail: A bool indicates that it is a tailing call. (function jump to
-               another function without restoring the stack frame)
-      callee: Resolved callee function.
+      is_tail: A bool indicates that it is a tailing call.
+      callee: Resolved callee function. None if it hasn't been resolved.
     """
-    # It makes no sense that both address and target are unknown.
-    assert not (address is None and target is None)
-    self.address = address
-    self.target = target
-    self.is_tail = is_tail
-    self.callee = callee
-
-  def __eq__(self, other):
-    """Callsite equality.
 
-    Args:
-      other: The compared object.
-
-    Returns:
-      True if equal, False if not.
-    """
-    if not isinstance(other, Callsite):
-      return False
-
-    if not (self.address == other.address and
-            self.target == other.target and
-            self.is_tail == other.is_tail):
-      return False
-
-    if self.callee is None:
-      return other.callee is None
-    elif other.callee is None:
-      return False
-
-    # Assume the addresses of functions are unique.
-    return self.callee.address == other.callee.address
+    def __init__(self, address, target, is_tail, callee=None):
+        """Constructor.
+
+        Args:
+          address: Address of callsite location. None if it is unknown.
+          target: Callee address. None if it is unknown.
+          is_tail: A bool indicates that it is a tailing call. (function jump to
+                   another function without restoring the stack frame)
+          callee: Resolved callee function.
+        """
+        # It makes no sense that both address and target are unknown.
+        assert not (address is None and target is None)
+        self.address = address
+        self.target = target
+        self.is_tail = is_tail
+        self.callee = callee
+
+    def __eq__(self, other):
+        """Callsite equality.
+
+        Args:
+          other: The compared object.
+
+        Returns:
+          True if equal, False if not.
+        """
+        if not isinstance(other, Callsite):
+            return False
+
+        if not (
+            self.address == other.address
+            and self.target == other.target
+            and self.is_tail == other.is_tail
+        ):
+            return False
+
+        if self.callee is None:
+            return other.callee is None
+        elif other.callee is None:
+            return False
+
+        # Assume the addresses of functions are unique.
+        return self.callee.address == other.callee.address
 
 
 class Function(object):
-  """Function.
+    """Function.
 
-  Attributes:
-    address: Address of function.
-    name: Name of function from its symbol.
-    stack_frame: Size of stack frame.
-    callsites: Callsite list.
-    stack_max_usage: Max stack usage. None if it hasn't been analyzed.
-    stack_max_path: Max stack usage path. None if it hasn't been analyzed.
-  """
-
-  def __init__(self, address, name, stack_frame, callsites):
-    """Constructor.
-
-    Args:
+    Attributes:
       address: Address of function.
       name: Name of function from its symbol.
       stack_frame: Size of stack frame.
       callsites: Callsite list.
+      stack_max_usage: Max stack usage. None if it hasn't been analyzed.
+      stack_max_path: Max stack usage path. None if it hasn't been analyzed.
     """
-    self.address = address
-    self.name = name
-    self.stack_frame = stack_frame
-    self.callsites = callsites
-    self.stack_max_usage = None
-    self.stack_max_path = None
-
-  def __eq__(self, other):
-    """Function equality.
-
-    Args:
-      other: The compared object.
-
-    Returns:
-      True if equal, False if not.
-    """
-    if not isinstance(other, Function):
-      return False
 
-    if not (self.address == other.address and
-            self.name == other.name and
-            self.stack_frame == other.stack_frame and
-            self.callsites == other.callsites and
-            self.stack_max_usage == other.stack_max_usage):
-      return False
+    def __init__(self, address, name, stack_frame, callsites):
+        """Constructor.
+
+        Args:
+          address: Address of function.
+          name: Name of function from its symbol.
+          stack_frame: Size of stack frame.
+          callsites: Callsite list.
+        """
+        self.address = address
+        self.name = name
+        self.stack_frame = stack_frame
+        self.callsites = callsites
+        self.stack_max_usage = None
+        self.stack_max_path = None
+
+    def __eq__(self, other):
+        """Function equality.
+
+        Args:
+          other: The compared object.
+
+        Returns:
+          True if equal, False if not.
+        """
+        if not isinstance(other, Function):
+            return False
+
+        if not (
+            self.address == other.address
+            and self.name == other.name
+            and self.stack_frame == other.stack_frame
+            and self.callsites == other.callsites
+            and self.stack_max_usage == other.stack_max_usage
+        ):
+            return False
+
+        if self.stack_max_path is None:
+            return other.stack_max_path is None
+        elif other.stack_max_path is None:
+            return False
+
+        if len(self.stack_max_path) != len(other.stack_max_path):
+            return False
+
+        for self_func, other_func in zip(
+            self.stack_max_path, other.stack_max_path
+        ):
+            # Assume the addresses of functions are unique.
+            if self_func.address != other_func.address:
+                return False
+
+        return True
+
+    def __hash__(self):
+        return id(self)
 
-    if self.stack_max_path is None:
-      return other.stack_max_path is None
-    elif other.stack_max_path is None:
-      return False
-
-    if len(self.stack_max_path) != len(other.stack_max_path):
-      return False
-
-    for self_func, other_func in zip(self.stack_max_path, other.stack_max_path):
-      # Assume the addresses of functions are unique.
-      if self_func.address != other_func.address:
-        return False
-
-    return True
-
-  def __hash__(self):
-    return id(self)
 
 class AndesAnalyzer(object):
-  """Disassembly analyzer for Andes architecture.
-
-  Public Methods:
-    AnalyzeFunction: Analyze stack frame and callsites of the function.
-  """
-
-  GENERAL_PURPOSE_REGISTER_SIZE = 4
-
-  # Possible condition code suffixes.
-  CONDITION_CODES = [ 'eq', 'eqz', 'gez', 'gtz', 'lez', 'ltz', 'ne', 'nez',
-                      'eqc', 'nec', 'nezs', 'nes', 'eqs']
-  CONDITION_CODES_RE = '({})'.format('|'.join(CONDITION_CODES))
-
-  IMM_ADDRESS_RE = r'([0-9A-Fa-f]+)\s+<([^>]+)>'
-  # Branch instructions.
-  JUMP_OPCODE_RE = re.compile(r'^(b{0}|j|jr|jr.|jrnez)(\d?|\d\d)$' \
-                  .format(CONDITION_CODES_RE))
-  # Call instructions.
-  CALL_OPCODE_RE = re.compile \
-                  (r'^(jal|jral|jral.|jralnez|beqzal|bltzal|bgezal)(\d)?$')
-  CALL_OPERAND_RE = re.compile(r'^{}$'.format(IMM_ADDRESS_RE))
-  # Ignore lp register because it's for return.
-  INDIRECT_CALL_OPERAND_RE = re.compile \
-                  (r'^\$r\d{1,}$|\$fp$|\$gp$|\$ta$|\$sp$|\$pc$')
-  # TODO: Handle other kinds of store instructions.
-  PUSH_OPCODE_RE = re.compile(r'^push(\d{1,})$')
-  PUSH_OPERAND_RE = re.compile(r'^\$r\d{1,}, \#\d{1,}    \! \{([^\]]+)\}')
-  SMW_OPCODE_RE = re.compile(r'^smw(\.\w\w|\.\w\w\w)$')
-  SMW_OPERAND_RE = re.compile(r'^(\$r\d{1,}|\$\wp), \[\$\wp\], '
-                   r'(\$r\d{1,}|\$\wp), \#\d\w\d    \! \{([^\]]+)\}')
-  OPERANDGROUP_RE = re.compile(r'^\$r\d{1,}\~\$r\d{1,}')
-
-  LWI_OPCODE_RE = re.compile(r'^lwi(\.\w\w)$')
-  LWI_PC_OPERAND_RE = re.compile(r'^\$pc, \[([^\]]+)\]')
-  # Example: "34280:  3f c8 0f ec   addi.gp $fp, #0xfec"
-  # Assume there is always a "\t" after the hex data.
-  DISASM_REGEX_RE = re.compile(r'^(?P<address>[0-9A-Fa-f]+):\s+'
-                    r'(?P<words>[0-9A-Fa-f ]+)'
-                    r'\t\s*(?P<opcode>\S+)(\s+(?P<operand>[^;]*))?')
-
-  def ParseInstruction(self, line, function_end):
-    """Parse the line of instruction.
+    """Disassembly analyzer for Andes architecture.
 
-    Args:
-      line: Text of disassembly.
-      function_end: End address of the current function. None if unknown.
-
-    Returns:
-      (address, words, opcode, operand_text): The instruction address, words,
-                                        opcode, and the text of operands.
-                                        None if it isn't an instruction line.
+    Public Methods:
+      AnalyzeFunction: Analyze stack frame and callsites of the function.
     """
-    result = self.DISASM_REGEX_RE.match(line)
-    if result is None:
-      return None
-
-    address = int(result.group('address'), 16)
-    # Check if it's out of bound.
-    if function_end is not None and address >= function_end:
-      return None
-
-    opcode = result.group('opcode').strip()
-    operand_text = result.group('operand')
-    words = result.group('words')
-    if operand_text is None:
-      operand_text = ''
-    else:
-      operand_text = operand_text.strip()
-
-    return (address, words, opcode, operand_text)
-
-  def AnalyzeFunction(self, function_symbol, instructions):
-
-    stack_frame = 0
-    callsites = []
-    for address, words, opcode, operand_text in instructions:
-      is_jump_opcode = self.JUMP_OPCODE_RE.match(opcode) is not None
-      is_call_opcode = self.CALL_OPCODE_RE.match(opcode) is not None
-
-      if is_jump_opcode or is_call_opcode:
-        is_tail = is_jump_opcode
-
-        result = self.CALL_OPERAND_RE.match(operand_text)
 
+    GENERAL_PURPOSE_REGISTER_SIZE = 4
+
+    # Possible condition code suffixes.
+    CONDITION_CODES = [
+        "eq",
+        "eqz",
+        "gez",
+        "gtz",
+        "lez",
+        "ltz",
+        "ne",
+        "nez",
+        "eqc",
+        "nec",
+        "nezs",
+        "nes",
+        "eqs",
+    ]
+    CONDITION_CODES_RE = "({})".format("|".join(CONDITION_CODES))
+
+    IMM_ADDRESS_RE = r"([0-9A-Fa-f]+)\s+<([^>]+)>"
+    # Branch instructions.
+    JUMP_OPCODE_RE = re.compile(
+        r"^(b{0}|j|jr|jr.|jrnez)(\d?|\d\d)$".format(CONDITION_CODES_RE)
+    )
+    # Call instructions.
+    CALL_OPCODE_RE = re.compile(
+        r"^(jal|jral|jral.|jralnez|beqzal|bltzal|bgezal)(\d)?$"
+    )
+    CALL_OPERAND_RE = re.compile(r"^{}$".format(IMM_ADDRESS_RE))
+    # Ignore lp register because it's for return.
+    INDIRECT_CALL_OPERAND_RE = re.compile(
+        r"^\$r\d{1,}$|\$fp$|\$gp$|\$ta$|\$sp$|\$pc$"
+    )
+    # TODO: Handle other kinds of store instructions.
+    PUSH_OPCODE_RE = re.compile(r"^push(\d{1,})$")
+    PUSH_OPERAND_RE = re.compile(r"^\$r\d{1,}, \#\d{1,}    \! \{([^\]]+)\}")
+    SMW_OPCODE_RE = re.compile(r"^smw(\.\w\w|\.\w\w\w)$")
+    SMW_OPERAND_RE = re.compile(
+        r"^(\$r\d{1,}|\$\wp), \[\$\wp\], "
+        r"(\$r\d{1,}|\$\wp), \#\d\w\d    \! \{([^\]]+)\}"
+    )
+    OPERANDGROUP_RE = re.compile(r"^\$r\d{1,}\~\$r\d{1,}")
+
+    LWI_OPCODE_RE = re.compile(r"^lwi(\.\w\w)$")
+    LWI_PC_OPERAND_RE = re.compile(r"^\$pc, \[([^\]]+)\]")
+    # Example: "34280:  3f c8 0f ec   addi.gp $fp, #0xfec"
+    # Assume there is always a "\t" after the hex data.
+    DISASM_REGEX_RE = re.compile(
+        r"^(?P<address>[0-9A-Fa-f]+):\s+"
+        r"(?P<words>[0-9A-Fa-f ]+)"
+        r"\t\s*(?P<opcode>\S+)(\s+(?P<operand>[^;]*))?"
+    )
+
+    def ParseInstruction(self, line, function_end):
+        """Parse the line of instruction.
+
+        Args:
+          line: Text of disassembly.
+          function_end: End address of the current function. None if unknown.
+
+        Returns:
+          (address, words, opcode, operand_text): The instruction address, words,
+                                            opcode, and the text of operands.
+                                            None if it isn't an instruction line.
+        """
+        result = self.DISASM_REGEX_RE.match(line)
         if result is None:
-          if (self.INDIRECT_CALL_OPERAND_RE.match(operand_text) is not None):
-            # Found an indirect call.
-            callsites.append(Callsite(address, None, is_tail))
-
+            return None
+
+        address = int(result.group("address"), 16)
+        # Check if it's out of bound.
+        if function_end is not None and address >= function_end:
+            return None
+
+        opcode = result.group("opcode").strip()
+        operand_text = result.group("operand")
+        words = result.group("words")
+        if operand_text is None:
+            operand_text = ""
         else:
-          target_address = int(result.group(1), 16)
-          # Filter out the in-function target (branches and in-function calls,
-          # which are actually branches).
-          if not (function_symbol.size > 0 and
-                  function_symbol.address < target_address <
-                  (function_symbol.address + function_symbol.size)):
-            # Maybe it is a callsite.
-            callsites.append(Callsite(address, target_address, is_tail))
-
-      elif self.LWI_OPCODE_RE.match(opcode) is not None:
-        result = self.LWI_PC_OPERAND_RE.match(operand_text)
-        if result is not None:
-          # Ignore "lwi $pc, [$sp], xx" because it's usually a return.
-          if result.group(1) != '$sp':
-            # Found an indirect call.
-            callsites.append(Callsite(address, None, True))
-
-      elif self.PUSH_OPCODE_RE.match(opcode) is not None:
-        # Example: fc 20    push25 $r8, #0    ! {$r6~$r8, $fp, $gp, $lp}
-        if self.PUSH_OPERAND_RE.match(operand_text) is not None:
-          # capture fc 20
-          imm5u = int(words.split(' ')[1], 16)
-          # sp = sp - (imm5u << 3)
-          imm8u = (imm5u<<3) & 0xff
-          stack_frame += imm8u
-
-          result = self.PUSH_OPERAND_RE.match(operand_text)
-          operandgroup_text = result.group(1)
-          # capture $rx~$ry
-          if self.OPERANDGROUP_RE.match(operandgroup_text) is not None:
-            # capture number & transfer string to integer
-            oprandgrouphead = operandgroup_text.split(',')[0]
-            rx=int(''.join(filter(str.isdigit, oprandgrouphead.split('~')[0])))
-            ry=int(''.join(filter(str.isdigit, oprandgrouphead.split('~')[1])))
-
-            stack_frame += ((len(operandgroup_text.split(','))+ry-rx) *
-                          self.GENERAL_PURPOSE_REGISTER_SIZE)
-          else:
-            stack_frame += (len(operandgroup_text.split(',')) *
-                          self.GENERAL_PURPOSE_REGISTER_SIZE)
-
-      elif self.SMW_OPCODE_RE.match(opcode) is not None:
-        # Example: smw.adm $r6, [$sp], $r10, #0x2    ! {$r6~$r10, $lp}
-        if self.SMW_OPERAND_RE.match(operand_text) is not None:
-          result = self.SMW_OPERAND_RE.match(operand_text)
-          operandgroup_text = result.group(3)
-          # capture $rx~$ry
-          if self.OPERANDGROUP_RE.match(operandgroup_text) is not None:
-            # capture number & transfer string to integer
-            oprandgrouphead = operandgroup_text.split(',')[0]
-            rx=int(''.join(filter(str.isdigit, oprandgrouphead.split('~')[0])))
-            ry=int(''.join(filter(str.isdigit, oprandgrouphead.split('~')[1])))
-
-            stack_frame += ((len(operandgroup_text.split(','))+ry-rx) *
-                          self.GENERAL_PURPOSE_REGISTER_SIZE)
-          else:
-            stack_frame += (len(operandgroup_text.split(',')) *
-                          self.GENERAL_PURPOSE_REGISTER_SIZE)
-
-    return (stack_frame, callsites)
+            operand_text = operand_text.strip()
+
+        return (address, words, opcode, operand_text)
+
+    def AnalyzeFunction(self, function_symbol, instructions):
+
+        stack_frame = 0
+        callsites = []
+        for address, words, opcode, operand_text in instructions:
+            is_jump_opcode = self.JUMP_OPCODE_RE.match(opcode) is not None
+            is_call_opcode = self.CALL_OPCODE_RE.match(opcode) is not None
+
+            if is_jump_opcode or is_call_opcode:
+                is_tail = is_jump_opcode
+
+                result = self.CALL_OPERAND_RE.match(operand_text)
+
+                if result is None:
+                    if (
+                        self.INDIRECT_CALL_OPERAND_RE.match(operand_text)
+                        is not None
+                    ):
+                        # Found an indirect call.
+                        callsites.append(Callsite(address, None, is_tail))
+
+                else:
+                    target_address = int(result.group(1), 16)
+                    # Filter out the in-function target (branches and in-function calls,
+                    # which are actually branches).
+                    if not (
+                        function_symbol.size > 0
+                        and function_symbol.address
+                        < target_address
+                        < (function_symbol.address + function_symbol.size)
+                    ):
+                        # Maybe it is a callsite.
+                        callsites.append(
+                            Callsite(address, target_address, is_tail)
+                        )
+
+            elif self.LWI_OPCODE_RE.match(opcode) is not None:
+                result = self.LWI_PC_OPERAND_RE.match(operand_text)
+                if result is not None:
+                    # Ignore "lwi $pc, [$sp], xx" because it's usually a return.
+                    if result.group(1) != "$sp":
+                        # Found an indirect call.
+                        callsites.append(Callsite(address, None, True))
+
+            elif self.PUSH_OPCODE_RE.match(opcode) is not None:
+                # Example: fc 20    push25 $r8, #0    ! {$r6~$r8, $fp, $gp, $lp}
+                if self.PUSH_OPERAND_RE.match(operand_text) is not None:
+                    # capture fc 20
+                    imm5u = int(words.split(" ")[1], 16)
+                    # sp = sp - (imm5u << 3)
+                    imm8u = (imm5u << 3) & 0xFF
+                    stack_frame += imm8u
+
+                    result = self.PUSH_OPERAND_RE.match(operand_text)
+                    operandgroup_text = result.group(1)
+                    # capture $rx~$ry
+                    if (
+                        self.OPERANDGROUP_RE.match(operandgroup_text)
+                        is not None
+                    ):
+                        # capture number & transfer string to integer
+                        oprandgrouphead = operandgroup_text.split(",")[0]
+                        rx = int(
+                            "".join(
+                                filter(
+                                    str.isdigit, oprandgrouphead.split("~")[0]
+                                )
+                            )
+                        )
+                        ry = int(
+                            "".join(
+                                filter(
+                                    str.isdigit, oprandgrouphead.split("~")[1]
+                                )
+                            )
+                        )
+
+                        stack_frame += (
+                            len(operandgroup_text.split(",")) + ry - rx
+                        ) * self.GENERAL_PURPOSE_REGISTER_SIZE
+                    else:
+                        stack_frame += (
+                            len(operandgroup_text.split(","))
+                            * self.GENERAL_PURPOSE_REGISTER_SIZE
+                        )
+
+            elif self.SMW_OPCODE_RE.match(opcode) is not None:
+                # Example: smw.adm $r6, [$sp], $r10, #0x2    ! {$r6~$r10, $lp}
+                if self.SMW_OPERAND_RE.match(operand_text) is not None:
+                    result = self.SMW_OPERAND_RE.match(operand_text)
+                    operandgroup_text = result.group(3)
+                    # capture $rx~$ry
+                    if (
+                        self.OPERANDGROUP_RE.match(operandgroup_text)
+                        is not None
+                    ):
+                        # capture number & transfer string to integer
+                        oprandgrouphead = operandgroup_text.split(",")[0]
+                        rx = int(
+                            "".join(
+                                filter(
+                                    str.isdigit, oprandgrouphead.split("~")[0]
+                                )
+                            )
+                        )
+                        ry = int(
+                            "".join(
+                                filter(
+                                    str.isdigit, oprandgrouphead.split("~")[1]
+                                )
+                            )
+                        )
+
+                        stack_frame += (
+                            len(operandgroup_text.split(",")) + ry - rx
+                        ) * self.GENERAL_PURPOSE_REGISTER_SIZE
+                    else:
+                        stack_frame += (
+                            len(operandgroup_text.split(","))
+                            * self.GENERAL_PURPOSE_REGISTER_SIZE
+                        )
+
+        return (stack_frame, callsites)
 
-class ArmAnalyzer(object):
-  """Disassembly analyzer for ARM architecture.
-
-  Public Methods:
-    AnalyzeFunction: Analyze stack frame and callsites of the function.
-  """
-
-  GENERAL_PURPOSE_REGISTER_SIZE = 4
-
-  # Possible condition code suffixes.
-  CONDITION_CODES = ['', 'eq', 'ne', 'cs', 'hs', 'cc', 'lo', 'mi', 'pl', 'vs',
-                     'vc', 'hi', 'ls', 'ge', 'lt', 'gt', 'le']
-  CONDITION_CODES_RE = '({})'.format('|'.join(CONDITION_CODES))
-  # Assume there is no function name containing ">".
-  IMM_ADDRESS_RE = r'([0-9A-Fa-f]+)\s+<([^>]+)>'
-
-  # Fuzzy regular expressions for instruction and operand parsing.
-  # Branch instructions.
-  JUMP_OPCODE_RE = re.compile(
-      r'^(b{0}|bx{0})(\.\w)?$'.format(CONDITION_CODES_RE))
-  # Call instructions.
-  CALL_OPCODE_RE = re.compile(
-      r'^(bl{0}|blx{0})(\.\w)?$'.format(CONDITION_CODES_RE))
-  CALL_OPERAND_RE = re.compile(r'^{}$'.format(IMM_ADDRESS_RE))
-  CBZ_CBNZ_OPCODE_RE = re.compile(r'^(cbz|cbnz)(\.\w)?$')
-  # Example: "r0, 1009bcbe <host_cmd_motion_sense+0x1d2>"
-  CBZ_CBNZ_OPERAND_RE = re.compile(r'^[^,]+,\s+{}$'.format(IMM_ADDRESS_RE))
-  # Ignore lr register because it's for return.
-  INDIRECT_CALL_OPERAND_RE = re.compile(r'^r\d+|sb|sl|fp|ip|sp|pc$')
-  # TODO(cheyuw): Handle conditional versions of following
-  #               instructions.
-  # TODO(cheyuw): Handle other kinds of pc modifying instructions (e.g. mov pc).
-  LDR_OPCODE_RE = re.compile(r'^ldr(\.\w)?$')
-  # Example: "pc, [sp], #4"
-  LDR_PC_OPERAND_RE = re.compile(r'^pc, \[([^\]]+)\]')
-  # TODO(cheyuw): Handle other kinds of stm instructions.
-  PUSH_OPCODE_RE = re.compile(r'^push$')
-  STM_OPCODE_RE = re.compile(r'^stmdb$')
-  # Stack subtraction instructions.
-  SUB_OPCODE_RE = re.compile(r'^sub(s|w)?(\.\w)?$')
-  SUB_OPERAND_RE = re.compile(r'^sp[^#]+#(\d+)')
-  # Example: "44d94:  f893 0068   ldrb.w  r0, [r3, #104]  ; 0x68"
-  # Assume there is always a "\t" after the hex data.
-  DISASM_REGEX_RE = re.compile(r'^(?P<address>[0-9A-Fa-f]+):\s+[0-9A-Fa-f ]+'
-                               r'\t\s*(?P<opcode>\S+)(\s+(?P<operand>[^;]*))?')
-
-  def ParseInstruction(self, line, function_end):
-    """Parse the line of instruction.
 
-    Args:
-      line: Text of disassembly.
-      function_end: End address of the current function. None if unknown.
+class ArmAnalyzer(object):
+    """Disassembly analyzer for ARM architecture.
 
-    Returns:
-      (address, opcode, operand_text): The instruction address, opcode,
-                                       and the text of operands. None if it
-                                       isn't an instruction line.
+    Public Methods:
+      AnalyzeFunction: Analyze stack frame and callsites of the function.
     """
-    result = self.DISASM_REGEX_RE.match(line)
-    if result is None:
-      return None
-
-    address = int(result.group('address'), 16)
-    # Check if it's out of bound.
-    if function_end is not None and address >= function_end:
-      return None
-
-    opcode = result.group('opcode').strip()
-    operand_text = result.group('operand')
-    if operand_text is None:
-      operand_text = ''
-    else:
-      operand_text = operand_text.strip()
-
-    return (address, opcode, operand_text)
-
-  def AnalyzeFunction(self, function_symbol, instructions):
-    """Analyze function, resolve the size of stack frame and callsites.
-
-    Args:
-      function_symbol: Function symbol.
-      instructions: Instruction list.
-
-    Returns:
-      (stack_frame, callsites): Size of stack frame, callsite list.
-    """
-    stack_frame = 0
-    callsites = []
-    for address, opcode, operand_text in instructions:
-      is_jump_opcode = self.JUMP_OPCODE_RE.match(opcode) is not None
-      is_call_opcode = self.CALL_OPCODE_RE.match(opcode) is not None
-      is_cbz_cbnz_opcode = self.CBZ_CBNZ_OPCODE_RE.match(opcode) is not None
-      if is_jump_opcode or is_call_opcode or is_cbz_cbnz_opcode:
-        is_tail = is_jump_opcode or is_cbz_cbnz_opcode
-
-        if is_cbz_cbnz_opcode:
-          result = self.CBZ_CBNZ_OPERAND_RE.match(operand_text)
-        else:
-          result = self.CALL_OPERAND_RE.match(operand_text)
 
+    GENERAL_PURPOSE_REGISTER_SIZE = 4
+
+    # Possible condition code suffixes.
+    CONDITION_CODES = [
+        "",
+        "eq",
+        "ne",
+        "cs",
+        "hs",
+        "cc",
+        "lo",
+        "mi",
+        "pl",
+        "vs",
+        "vc",
+        "hi",
+        "ls",
+        "ge",
+        "lt",
+        "gt",
+        "le",
+    ]
+    CONDITION_CODES_RE = "({})".format("|".join(CONDITION_CODES))
+    # Assume there is no function name containing ">".
+    IMM_ADDRESS_RE = r"([0-9A-Fa-f]+)\s+<([^>]+)>"
+
+    # Fuzzy regular expressions for instruction and operand parsing.
+    # Branch instructions.
+    JUMP_OPCODE_RE = re.compile(
+        r"^(b{0}|bx{0})(\.\w)?$".format(CONDITION_CODES_RE)
+    )
+    # Call instructions.
+    CALL_OPCODE_RE = re.compile(
+        r"^(bl{0}|blx{0})(\.\w)?$".format(CONDITION_CODES_RE)
+    )
+    CALL_OPERAND_RE = re.compile(r"^{}$".format(IMM_ADDRESS_RE))
+    CBZ_CBNZ_OPCODE_RE = re.compile(r"^(cbz|cbnz)(\.\w)?$")
+    # Example: "r0, 1009bcbe <host_cmd_motion_sense+0x1d2>"
+    CBZ_CBNZ_OPERAND_RE = re.compile(r"^[^,]+,\s+{}$".format(IMM_ADDRESS_RE))
+    # Ignore lr register because it's for return.
+    INDIRECT_CALL_OPERAND_RE = re.compile(r"^r\d+|sb|sl|fp|ip|sp|pc$")
+    # TODO(cheyuw): Handle conditional versions of following
+    #               instructions.
+    # TODO(cheyuw): Handle other kinds of pc modifying instructions (e.g. mov pc).
+    LDR_OPCODE_RE = re.compile(r"^ldr(\.\w)?$")
+    # Example: "pc, [sp], #4"
+    LDR_PC_OPERAND_RE = re.compile(r"^pc, \[([^\]]+)\]")
+    # TODO(cheyuw): Handle other kinds of stm instructions.
+    PUSH_OPCODE_RE = re.compile(r"^push$")
+    STM_OPCODE_RE = re.compile(r"^stmdb$")
+    # Stack subtraction instructions.
+    SUB_OPCODE_RE = re.compile(r"^sub(s|w)?(\.\w)?$")
+    SUB_OPERAND_RE = re.compile(r"^sp[^#]+#(\d+)")
+    # Example: "44d94:  f893 0068   ldrb.w  r0, [r3, #104]  ; 0x68"
+    # Assume there is always a "\t" after the hex data.
+    DISASM_REGEX_RE = re.compile(
+        r"^(?P<address>[0-9A-Fa-f]+):\s+[0-9A-Fa-f ]+"
+        r"\t\s*(?P<opcode>\S+)(\s+(?P<operand>[^;]*))?"
+    )
+
+    def ParseInstruction(self, line, function_end):
+        """Parse the line of instruction.
+
+        Args:
+          line: Text of disassembly.
+          function_end: End address of the current function. None if unknown.
+
+        Returns:
+          (address, opcode, operand_text): The instruction address, opcode,
+                                           and the text of operands. None if it
+                                           isn't an instruction line.
+        """
+        result = self.DISASM_REGEX_RE.match(line)
         if result is None:
-          # Failed to match immediate address, maybe it is an indirect call.
-          # CBZ and CBNZ can't be indirect calls.
-          if (not is_cbz_cbnz_opcode and
-              self.INDIRECT_CALL_OPERAND_RE.match(operand_text) is not None):
-            # Found an indirect call.
-            callsites.append(Callsite(address, None, is_tail))
+            return None
 
-        else:
-          target_address = int(result.group(1), 16)
-          # Filter out the in-function target (branches and in-function calls,
-          # which are actually branches).
-          if not (function_symbol.size > 0 and
-                  function_symbol.address < target_address <
-                  (function_symbol.address + function_symbol.size)):
-            # Maybe it is a callsite.
-            callsites.append(Callsite(address, target_address, is_tail))
-
-      elif self.LDR_OPCODE_RE.match(opcode) is not None:
-        result = self.LDR_PC_OPERAND_RE.match(operand_text)
-        if result is not None:
-          # Ignore "ldr pc, [sp], xx" because it's usually a return.
-          if result.group(1) != 'sp':
-            # Found an indirect call.
-            callsites.append(Callsite(address, None, True))
-
-      elif self.PUSH_OPCODE_RE.match(opcode) is not None:
-        # Example: "{r4, r5, r6, r7, lr}"
-        stack_frame += (len(operand_text.split(',')) *
-                        self.GENERAL_PURPOSE_REGISTER_SIZE)
-      elif self.SUB_OPCODE_RE.match(opcode) is not None:
-        result = self.SUB_OPERAND_RE.match(operand_text)
-        if result is not None:
-          stack_frame += int(result.group(1))
-        else:
-          # Unhandled stack register subtraction.
-          assert not operand_text.startswith('sp')
+        address = int(result.group("address"), 16)
+        # Check if it's out of bound.
+        if function_end is not None and address >= function_end:
+            return None
 
-      elif self.STM_OPCODE_RE.match(opcode) is not None:
-        if operand_text.startswith('sp!'):
-          # Subtract and writeback to stack register.
-          # Example: "sp!, {r4, r5, r6, r7, r8, r9, lr}"
-          # Get the text of pushed register list.
-          unused_sp, unused_sep, parameter_text = operand_text.partition(',')
-          stack_frame += (len(parameter_text.split(',')) *
-                          self.GENERAL_PURPOSE_REGISTER_SIZE)
+        opcode = result.group("opcode").strip()
+        operand_text = result.group("operand")
+        if operand_text is None:
+            operand_text = ""
+        else:
+            operand_text = operand_text.strip()
+
+        return (address, opcode, operand_text)
+
+    def AnalyzeFunction(self, function_symbol, instructions):
+        """Analyze function, resolve the size of stack frame and callsites.
+
+        Args:
+          function_symbol: Function symbol.
+          instructions: Instruction list.
+
+        Returns:
+          (stack_frame, callsites): Size of stack frame, callsite list.
+        """
+        stack_frame = 0
+        callsites = []
+        for address, opcode, operand_text in instructions:
+            is_jump_opcode = self.JUMP_OPCODE_RE.match(opcode) is not None
+            is_call_opcode = self.CALL_OPCODE_RE.match(opcode) is not None
+            is_cbz_cbnz_opcode = (
+                self.CBZ_CBNZ_OPCODE_RE.match(opcode) is not None
+            )
+            if is_jump_opcode or is_call_opcode or is_cbz_cbnz_opcode:
+                is_tail = is_jump_opcode or is_cbz_cbnz_opcode
+
+                if is_cbz_cbnz_opcode:
+                    result = self.CBZ_CBNZ_OPERAND_RE.match(operand_text)
+                else:
+                    result = self.CALL_OPERAND_RE.match(operand_text)
+
+                if result is None:
+                    # Failed to match immediate address, maybe it is an indirect call.
+                    # CBZ and CBNZ can't be indirect calls.
+                    if (
+                        not is_cbz_cbnz_opcode
+                        and self.INDIRECT_CALL_OPERAND_RE.match(operand_text)
+                        is not None
+                    ):
+                        # Found an indirect call.
+                        callsites.append(Callsite(address, None, is_tail))
+
+                else:
+                    target_address = int(result.group(1), 16)
+                    # Filter out the in-function target (branches and in-function calls,
+                    # which are actually branches).
+                    if not (
+                        function_symbol.size > 0
+                        and function_symbol.address
+                        < target_address
+                        < (function_symbol.address + function_symbol.size)
+                    ):
+                        # Maybe it is a callsite.
+                        callsites.append(
+                            Callsite(address, target_address, is_tail)
+                        )
+
+            elif self.LDR_OPCODE_RE.match(opcode) is not None:
+                result = self.LDR_PC_OPERAND_RE.match(operand_text)
+                if result is not None:
+                    # Ignore "ldr pc, [sp], xx" because it's usually a return.
+                    if result.group(1) != "sp":
+                        # Found an indirect call.
+                        callsites.append(Callsite(address, None, True))
+
+            elif self.PUSH_OPCODE_RE.match(opcode) is not None:
+                # Example: "{r4, r5, r6, r7, lr}"
+                stack_frame += (
+                    len(operand_text.split(","))
+                    * self.GENERAL_PURPOSE_REGISTER_SIZE
+                )
+            elif self.SUB_OPCODE_RE.match(opcode) is not None:
+                result = self.SUB_OPERAND_RE.match(operand_text)
+                if result is not None:
+                    stack_frame += int(result.group(1))
+                else:
+                    # Unhandled stack register subtraction.
+                    assert not operand_text.startswith("sp")
+
+            elif self.STM_OPCODE_RE.match(opcode) is not None:
+                if operand_text.startswith("sp!"):
+                    # Subtract and writeback to stack register.
+                    # Example: "sp!, {r4, r5, r6, r7, r8, r9, lr}"
+                    # Get the text of pushed register list.
+                    (
+                        unused_sp,
+                        unused_sep,
+                        parameter_text,
+                    ) = operand_text.partition(",")
+                    stack_frame += (
+                        len(parameter_text.split(","))
+                        * self.GENERAL_PURPOSE_REGISTER_SIZE
+                    )
+
+        return (stack_frame, callsites)
 
-    return (stack_frame, callsites)
 
 class RiscvAnalyzer(object):
-  """Disassembly analyzer for RISC-V architecture.
-
-  Public Methods:
-    AnalyzeFunction: Analyze stack frame and callsites of the function.
-  """
-
-  # Possible condition code suffixes.
-  CONDITION_CODES = [ 'eqz', 'nez', 'lez', 'gez', 'ltz', 'gtz', 'gt', 'le',
-                      'gtu', 'leu', 'eq', 'ne', 'ge', 'lt', 'ltu', 'geu']
-  CONDITION_CODES_RE = '({})'.format('|'.join(CONDITION_CODES))
-  # Branch instructions.
-  JUMP_OPCODE_RE = re.compile(r'^(b{0}|j|jr)$'.format(CONDITION_CODES_RE))
-  # Call instructions.
-  CALL_OPCODE_RE = re.compile(r'^(jal|jalr)$')
-  # Example: "j		8009b318 <set_state_prl_hr>" or
-  #          "jal	ra,800a4394 <power_get_signals>" or
-  #          "bltu	t0,t1,80080300 <data_loop>"
-  JUMP_ADDRESS_RE = r'((\w(\w|\d\d),){0,2})([0-9A-Fa-f]+)\s+<([^>]+)>'
-  CALL_OPERAND_RE = re.compile(r'^{}$'.format(JUMP_ADDRESS_RE))
-  # Capture address, Example:  800a4394
-  CAPTURE_ADDRESS = re.compile(r'[0-9A-Fa-f]{8}')
-  # Indirect jump, Example: jalr	a5
-  INDIRECT_CALL_OPERAND_RE = re.compile(r'^t\d+|s\d+|a\d+$')
-  # Example:  addi
-  ADDI_OPCODE_RE = re.compile(r'^addi$')
-  # Allocate stack instructions.
-  ADDI_OPERAND_RE = re.compile(r'^(sp,sp,-\d+)$')
-  # Example: "800804b6:	1101                	addi	sp,sp,-32"
-  DISASM_REGEX_RE = re.compile(r'^(?P<address>[0-9A-Fa-f]+):\s+[0-9A-Fa-f ]+'
-                               r'\t\s*(?P<opcode>\S+)(\s+(?P<operand>[^;]*))?')
-
-  def ParseInstruction(self, line, function_end):
-    """Parse the line of instruction.
+    """Disassembly analyzer for RISC-V architecture.
 
-    Args:
-      line: Text of disassembly.
-      function_end: End address of the current function. None if unknown.
-
-    Returns:
-      (address, opcode, operand_text):  The instruction address, opcode,
-                                        and the text of operands. None if it
-                                        isn't an instruction line.
+    Public Methods:
+      AnalyzeFunction: Analyze stack frame and callsites of the function.
     """
-    result = self.DISASM_REGEX_RE.match(line)
-    if result is None:
-      return None
-
-    address = int(result.group('address'), 16)
-    # Check if it's out of bound.
-    if function_end is not None and address >= function_end:
-      return None
-
-    opcode = result.group('opcode').strip()
-    operand_text = result.group('operand')
-    if operand_text is None:
-      operand_text = ''
-    else:
-      operand_text = operand_text.strip()
-
-    return (address, opcode, operand_text)
-
-  def AnalyzeFunction(self, function_symbol, instructions):
-
-    stack_frame = 0
-    callsites = []
-    for address, opcode, operand_text in instructions:
-      is_jump_opcode = self.JUMP_OPCODE_RE.match(opcode) is not None
-      is_call_opcode = self.CALL_OPCODE_RE.match(opcode) is not None
 
-      if is_jump_opcode or is_call_opcode:
-        is_tail = is_jump_opcode
-
-        result = self.CALL_OPERAND_RE.match(operand_text)
+    # Possible condition code suffixes.
+    CONDITION_CODES = [
+        "eqz",
+        "nez",
+        "lez",
+        "gez",
+        "ltz",
+        "gtz",
+        "gt",
+        "le",
+        "gtu",
+        "leu",
+        "eq",
+        "ne",
+        "ge",
+        "lt",
+        "ltu",
+        "geu",
+    ]
+    CONDITION_CODES_RE = "({})".format("|".join(CONDITION_CODES))
+    # Branch instructions.
+    JUMP_OPCODE_RE = re.compile(r"^(b{0}|j|jr)$".format(CONDITION_CODES_RE))
+    # Call instructions.
+    CALL_OPCODE_RE = re.compile(r"^(jal|jalr)$")
+    # Example: "j		8009b318 <set_state_prl_hr>" or
+    #          "jal	ra,800a4394 <power_get_signals>" or
+    #          "bltu	t0,t1,80080300 <data_loop>"
+    JUMP_ADDRESS_RE = r"((\w(\w|\d\d),){0,2})([0-9A-Fa-f]+)\s+<([^>]+)>"
+    CALL_OPERAND_RE = re.compile(r"^{}$".format(JUMP_ADDRESS_RE))
+    # Capture address, Example:  800a4394
+    CAPTURE_ADDRESS = re.compile(r"[0-9A-Fa-f]{8}")
+    # Indirect jump, Example: jalr	a5
+    INDIRECT_CALL_OPERAND_RE = re.compile(r"^t\d+|s\d+|a\d+$")
+    # Example:  addi
+    ADDI_OPCODE_RE = re.compile(r"^addi$")
+    # Allocate stack instructions.
+    ADDI_OPERAND_RE = re.compile(r"^(sp,sp,-\d+)$")
+    # Example: "800804b6:	1101                	addi	sp,sp,-32"
+    DISASM_REGEX_RE = re.compile(
+        r"^(?P<address>[0-9A-Fa-f]+):\s+[0-9A-Fa-f ]+"
+        r"\t\s*(?P<opcode>\S+)(\s+(?P<operand>[^;]*))?"
+    )
+
+    def ParseInstruction(self, line, function_end):
+        """Parse the line of instruction.
+
+        Args:
+          line: Text of disassembly.
+          function_end: End address of the current function. None if unknown.
+
+        Returns:
+          (address, opcode, operand_text):  The instruction address, opcode,
+                                            and the text of operands. None if it
+                                            isn't an instruction line.
+        """
+        result = self.DISASM_REGEX_RE.match(line)
         if result is None:
-          if (self.INDIRECT_CALL_OPERAND_RE.match(operand_text) is not None):
-            # Found an indirect call.
-            callsites.append(Callsite(address, None, is_tail))
-
-        else:
-          # Capture address form operand_text and then convert to string
-          address_str = "".join(self.CAPTURE_ADDRESS.findall(operand_text))
-          # String to integer
-          target_address = int(address_str, 16)
-          # Filter out the in-function target (branches and in-function calls,
-          # which are actually branches).
-          if not (function_symbol.size > 0 and
-                  function_symbol.address < target_address <
-                  (function_symbol.address + function_symbol.size)):
-            # Maybe it is a callsite.
-            callsites.append(Callsite(address, target_address, is_tail))
-
-      elif self.ADDI_OPCODE_RE.match(opcode) is not None:
-      	# Example: sp,sp,-32
-        if self.ADDI_OPERAND_RE.match(operand_text) is not None:
-            stack_frame += abs(int(operand_text.split(",")[2]))
-
-    return (stack_frame, callsites)
-
-class StackAnalyzer(object):
-  """Class to analyze stack usage.
-
-  Public Methods:
-    Analyze: Run the stack analysis.
-  """
-
-  C_FUNCTION_NAME = r'_A-Za-z0-9'
-
-  # Assume there is no ":" in the path.
-  # Example: "driver/accel_kionix.c:321 (discriminator 3)"
-  ADDRTOLINE_RE = re.compile(
-      r'^(?P<path>[^:]+):(?P<linenum>\d+)(\s+\(discriminator\s+\d+\))?$')
-  # To eliminate the suffix appended by compilers, try to extract the
-  # C function name from the prefix of symbol name.
-  # Example: "SHA256_transform.constprop.28"
-  FUNCTION_PREFIX_NAME_RE = re.compile(
-      r'^(?P<name>[{0}]+)([^{0}].*)?$'.format(C_FUNCTION_NAME))
-
-  # Errors of annotation resolving.
-  ANNOTATION_ERROR_INVALID = 'invalid signature'
-  ANNOTATION_ERROR_NOTFOUND = 'function is not found'
-  ANNOTATION_ERROR_AMBIGUOUS = 'signature is ambiguous'
-
-  def __init__(self, options, symbols, rodata, tasklist, annotation):
-    """Constructor.
-
-    Args:
-      options: Namespace from argparse.parse_args().
-      symbols: Symbol list.
-      rodata: Content of .rodata section (offset, data)
-      tasklist: Task list.
-      annotation: Annotation config.
-    """
-    self.options = options
-    self.symbols = symbols
-    self.rodata_offset = rodata[0]
-    self.rodata = rodata[1]
-    self.tasklist = tasklist
-    self.annotation = annotation
-    self.address_to_line_cache = {}
-
-  def AddressToLine(self, address, resolve_inline=False):
-    """Convert address to line.
+            return None
 
-    Args:
-      address: Target address.
-      resolve_inline: Output the stack of inlining.
-
-    Returns:
-      lines: List of the corresponding lines.
-
-    Raises:
-      StackAnalyzerError: If addr2line is failed.
-    """
-    cache_key = (address, resolve_inline)
-    if cache_key in self.address_to_line_cache:
-      return self.address_to_line_cache[cache_key]
-
-    try:
-      args = [self.options.addr2line,
-              '-f',
-              '-e',
-              self.options.elf_path,
-              '{:x}'.format(address)]
-      if resolve_inline:
-        args.append('-i')
-
-      line_text = subprocess.check_output(args, encoding='utf-8')
-    except subprocess.CalledProcessError:
-      raise StackAnalyzerError('addr2line failed to resolve lines.')
-    except OSError:
-      raise StackAnalyzerError('Failed to run addr2line.')
-
-    lines = [line.strip() for line in line_text.splitlines()]
-    # Assume the output has at least one pair like "function\nlocation\n", and
-    # they always show up in pairs.
-    # Example: "handle_request\n
-    #           common/usb_pd_protocol.c:1191\n"
-    assert len(lines) >= 2 and len(lines) % 2 == 0
-
-    line_infos = []
-    for index in range(0, len(lines), 2):
-      (function_name, line_text) = lines[index:index + 2]
-      if line_text in ['??:0', ':?']:
-        line_infos.append(None)
-      else:
-        result = self.ADDRTOLINE_RE.match(line_text)
-        # Assume the output is always well-formed.
-        assert result is not None
-        line_infos.append((function_name.strip(),
-                           os.path.realpath(result.group('path').strip()),
-                           int(result.group('linenum'))))
-
-    self.address_to_line_cache[cache_key] = line_infos
-    return line_infos
-
-  def AnalyzeDisassembly(self, disasm_text):
-    """Parse the disassembly text, analyze, and build a map of all functions.
-
-    Args:
-      disasm_text: Disassembly text.
+        address = int(result.group("address"), 16)
+        # Check if it's out of bound.
+        if function_end is not None and address >= function_end:
+            return None
 
-    Returns:
-      function_map: Dict of functions.
-    """
-    disasm_lines = [line.strip() for line in disasm_text.splitlines()]
-
-    if 'nds' in disasm_lines[1]:
-      analyzer = AndesAnalyzer()
-    elif 'arm' in disasm_lines[1]:
-      analyzer = ArmAnalyzer()
-    elif 'riscv' in disasm_lines[1]:
-      analyzer = RiscvAnalyzer()
-    else:
-      raise StackAnalyzerError('Unsupported architecture.')
-
-    # Example: "08028c8c <motion_lid_calc>:"
-    function_signature_regex = re.compile(
-        r'^(?P<address>[0-9A-Fa-f]+)\s+<(?P<name>[^>]+)>:$')
-
-    def DetectFunctionHead(line):
-      """Check if the line is a function head.
-
-      Args:
-        line: Text of disassembly.
-
-      Returns:
-        symbol: Function symbol. None if it isn't a function head.
-      """
-      result = function_signature_regex.match(line)
-      if result is None:
-        return None
-
-      address = int(result.group('address'), 16)
-      symbol = symbol_map.get(address)
-
-      # Check if the function exists and matches.
-      if symbol is None or symbol.symtype != 'F':
-        return None
-
-      return symbol
-
-    # Build symbol map, indexed by symbol address.
-    symbol_map = {}
-    for symbol in self.symbols:
-      # If there are multiple symbols with same address, keeping any of them is
-      # good enough.
-      symbol_map[symbol.address] = symbol
-
-    # Parse the disassembly text. We update the variable "line" to next line
-    # when needed. There are two steps of parser:
-    #
-    # Step 1: Searching for the function head. Once reach the function head,
-    # move to the next line, which is the first line of function body.
-    #
-    # Step 2: Parsing each instruction line of function body. Once reach a
-    # non-instruction line, stop parsing and analyze the parsed instructions.
-    #
-    # Finally turn back to the step 1 without updating the line, because the
-    # current non-instruction line can be another function head.
-    function_map = {}
-    # The following three variables are the states of the parsing processing.
-    # They will be initialized properly during the state changes.
-    function_symbol = None
-    function_end = None
-    instructions = []
-
-    # Remove heading and tailing spaces for each line.
-    line_index = 0
-    while line_index < len(disasm_lines):
-      # Get the current line.
-      line = disasm_lines[line_index]
-
-      if function_symbol is None:
-        # Step 1: Search for the function head.
-
-        function_symbol = DetectFunctionHead(line)
-        if function_symbol is not None:
-          # Assume there is no empty function. If the function head is followed
-          # by EOF, it is an empty function.
-          assert line_index + 1 < len(disasm_lines)
-
-          # Found the function head, initialize and turn to the step 2.
-          instructions = []
-          # If symbol size exists, use it as a hint of function size.
-          if function_symbol.size > 0:
-            function_end = function_symbol.address + function_symbol.size
-          else:
-            function_end = None
-
-      else:
-        # Step 2: Parse the function body.
-
-        instruction = analyzer.ParseInstruction(line, function_end)
-        if instruction is not None:
-          instructions.append(instruction)
-
-        if instruction is None or line_index + 1 == len(disasm_lines):
-          # Either the invalid instruction or EOF indicates the end of the
-          # function, finalize the function analysis.
-
-          # Assume there is no empty function.
-          assert len(instructions) > 0
-
-          (stack_frame, callsites) = analyzer.AnalyzeFunction(function_symbol,
-                                                              instructions)
-          # Assume the function addresses are unique in the disassembly.
-          assert function_symbol.address not in function_map
-          function_map[function_symbol.address] = Function(
-              function_symbol.address,
-              function_symbol.name,
-              stack_frame,
-              callsites)
-
-          # Initialize and turn back to the step 1.
-          function_symbol = None
-
-          # If the current line isn't an instruction, it can be another function
-          # head, skip moving to the next line.
-          if instruction is None:
-            continue
-
-      # Move to the next line.
-      line_index += 1
-
-    # Resolve callees of functions.
-    for function in function_map.values():
-      for callsite in function.callsites:
-        if callsite.target is not None:
-          # Remain the callee as None if we can't resolve it.
-          callsite.callee = function_map.get(callsite.target)
-
-    return function_map
+        opcode = result.group("opcode").strip()
+        operand_text = result.group("operand")
+        if operand_text is None:
+            operand_text = ""
+        else:
+            operand_text = operand_text.strip()
+
+        return (address, opcode, operand_text)
+
+    def AnalyzeFunction(self, function_symbol, instructions):
+
+        stack_frame = 0
+        callsites = []
+        for address, opcode, operand_text in instructions:
+            is_jump_opcode = self.JUMP_OPCODE_RE.match(opcode) is not None
+            is_call_opcode = self.CALL_OPCODE_RE.match(opcode) is not None
+
+            if is_jump_opcode or is_call_opcode:
+                is_tail = is_jump_opcode
+
+                result = self.CALL_OPERAND_RE.match(operand_text)
+                if result is None:
+                    if (
+                        self.INDIRECT_CALL_OPERAND_RE.match(operand_text)
+                        is not None
+                    ):
+                        # Found an indirect call.
+                        callsites.append(Callsite(address, None, is_tail))
+
+                else:
+                    # Capture address form operand_text and then convert to string
+                    address_str = "".join(
+                        self.CAPTURE_ADDRESS.findall(operand_text)
+                    )
+                    # String to integer
+                    target_address = int(address_str, 16)
+                    # Filter out the in-function target (branches and in-function calls,
+                    # which are actually branches).
+                    if not (
+                        function_symbol.size > 0
+                        and function_symbol.address
+                        < target_address
+                        < (function_symbol.address + function_symbol.size)
+                    ):
+                        # Maybe it is a callsite.
+                        callsites.append(
+                            Callsite(address, target_address, is_tail)
+                        )
+
+            elif self.ADDI_OPCODE_RE.match(opcode) is not None:
+                # Example: sp,sp,-32
+                if self.ADDI_OPERAND_RE.match(operand_text) is not None:
+                    stack_frame += abs(int(operand_text.split(",")[2]))
+
+        return (stack_frame, callsites)
 
-  def MapAnnotation(self, function_map, signature_set):
-    """Map annotation signatures to functions.
 
-    Args:
-      function_map: Function map.
-      signature_set: Set of annotation signatures.
+class StackAnalyzer(object):
+    """Class to analyze stack usage.
 
-    Returns:
-      Map of signatures to functions, map of signatures which can't be resolved.
+    Public Methods:
+      Analyze: Run the stack analysis.
     """
-    # Build the symbol map indexed by symbol name. If there are multiple symbols
-    # with the same name, add them into a set. (e.g. symbols of static function
-    # with the same name)
-    symbol_map = collections.defaultdict(set)
-    for symbol in self.symbols:
-      if symbol.symtype == 'F':
-        # Function symbol.
-        result = self.FUNCTION_PREFIX_NAME_RE.match(symbol.name)
-        if result is not None:
-          function = function_map.get(symbol.address)
-          # Ignore the symbol not in disassembly.
-          if function is not None:
-            # If there are multiple symbol with the same name and point to the
-            # same function, the set will deduplicate them.
-            symbol_map[result.group('name').strip()].add(function)
-
-    # Build the signature map indexed by annotation signature.
-    signature_map = {}
-    sig_error_map = {}
-    symbol_path_map = {}
-    for sig in signature_set:
-      (name, path, _) = sig
-
-      functions = symbol_map.get(name)
-      if functions is None:
-        sig_error_map[sig] = self.ANNOTATION_ERROR_NOTFOUND
-        continue
-
-      if name not in symbol_path_map:
-        # Lazy symbol path resolving. Since the addr2line isn't fast, only
-        # resolve needed symbol paths.
-        group_map = collections.defaultdict(list)
-        for function in functions:
-          line_info = self.AddressToLine(function.address)[0]
-          if line_info is None:
-            continue
 
-          (_, symbol_path, _) = line_info
+    C_FUNCTION_NAME = r"_A-Za-z0-9"
 
-          # Group the functions with the same symbol signature (symbol name +
-          # symbol path). Assume they are the same copies and do the same
-          # annotation operations of them because we don't know which copy is
-          # indicated by the users.
-          group_map[symbol_path].append(function)
+    # Assume there is no ":" in the path.
+    # Example: "driver/accel_kionix.c:321 (discriminator 3)"
+    ADDRTOLINE_RE = re.compile(
+        r"^(?P<path>[^:]+):(?P<linenum>\d+)(\s+\(discriminator\s+\d+\))?$"
+    )
+    # To eliminate the suffix appended by compilers, try to extract the
+    # C function name from the prefix of symbol name.
+    # Example: "SHA256_transform.constprop.28"
+    FUNCTION_PREFIX_NAME_RE = re.compile(
+        r"^(?P<name>[{0}]+)([^{0}].*)?$".format(C_FUNCTION_NAME)
+    )
+
+    # Errors of annotation resolving.
+    ANNOTATION_ERROR_INVALID = "invalid signature"
+    ANNOTATION_ERROR_NOTFOUND = "function is not found"
+    ANNOTATION_ERROR_AMBIGUOUS = "signature is ambiguous"
+
+    def __init__(self, options, symbols, rodata, tasklist, annotation):
+        """Constructor.
+
+        Args:
+          options: Namespace from argparse.parse_args().
+          symbols: Symbol list.
+          rodata: Content of .rodata section (offset, data)
+          tasklist: Task list.
+          annotation: Annotation config.
+        """
+        self.options = options
+        self.symbols = symbols
+        self.rodata_offset = rodata[0]
+        self.rodata = rodata[1]
+        self.tasklist = tasklist
+        self.annotation = annotation
+        self.address_to_line_cache = {}
+
+    def AddressToLine(self, address, resolve_inline=False):
+        """Convert address to line.
+
+        Args:
+          address: Target address.
+          resolve_inline: Output the stack of inlining.
+
+        Returns:
+          lines: List of the corresponding lines.
+
+        Raises:
+          StackAnalyzerError: If addr2line is failed.
+        """
+        cache_key = (address, resolve_inline)
+        if cache_key in self.address_to_line_cache:
+            return self.address_to_line_cache[cache_key]
+
+        try:
+            args = [
+                self.options.addr2line,
+                "-f",
+                "-e",
+                self.options.elf_path,
+                "{:x}".format(address),
+            ]
+            if resolve_inline:
+                args.append("-i")
+
+            line_text = subprocess.check_output(args, encoding="utf-8")
+        except subprocess.CalledProcessError:
+            raise StackAnalyzerError("addr2line failed to resolve lines.")
+        except OSError:
+            raise StackAnalyzerError("Failed to run addr2line.")
+
+        lines = [line.strip() for line in line_text.splitlines()]
+        # Assume the output has at least one pair like "function\nlocation\n", and
+        # they always show up in pairs.
+        # Example: "handle_request\n
+        #           common/usb_pd_protocol.c:1191\n"
+        assert len(lines) >= 2 and len(lines) % 2 == 0
+
+        line_infos = []
+        for index in range(0, len(lines), 2):
+            (function_name, line_text) = lines[index : index + 2]
+            if line_text in ["??:0", ":?"]:
+                line_infos.append(None)
+            else:
+                result = self.ADDRTOLINE_RE.match(line_text)
+                # Assume the output is always well-formed.
+                assert result is not None
+                line_infos.append(
+                    (
+                        function_name.strip(),
+                        os.path.realpath(result.group("path").strip()),
+                        int(result.group("linenum")),
+                    )
+                )
+
+        self.address_to_line_cache[cache_key] = line_infos
+        return line_infos
+
+    def AnalyzeDisassembly(self, disasm_text):
+        """Parse the disassembly text, analyze, and build a map of all functions.
+
+        Args:
+          disasm_text: Disassembly text.
+
+        Returns:
+          function_map: Dict of functions.
+        """
+        disasm_lines = [line.strip() for line in disasm_text.splitlines()]
+
+        if "nds" in disasm_lines[1]:
+            analyzer = AndesAnalyzer()
+        elif "arm" in disasm_lines[1]:
+            analyzer = ArmAnalyzer()
+        elif "riscv" in disasm_lines[1]:
+            analyzer = RiscvAnalyzer()
+        else:
+            raise StackAnalyzerError("Unsupported architecture.")
 
-        symbol_path_map[name] = group_map
+        # Example: "08028c8c <motion_lid_calc>:"
+        function_signature_regex = re.compile(
+            r"^(?P<address>[0-9A-Fa-f]+)\s+<(?P<name>[^>]+)>:$"
+        )
 
-      # Symbol matching.
-      function_group = None
-      group_map = symbol_path_map[name]
-      if len(group_map) > 0:
-        if path is None:
-          if len(group_map) > 1:
-            # There is ambiguity but the path isn't specified.
-            sig_error_map[sig] = self.ANNOTATION_ERROR_AMBIGUOUS
-            continue
+        def DetectFunctionHead(line):
+            """Check if the line is a function head.
 
-          # No path signature but all symbol signatures of functions are same.
-          # Assume they are the same functions, so there is no ambiguity.
-          (function_group,) = group_map.values()
-        else:
-          function_group = group_map.get(path)
+            Args:
+              line: Text of disassembly.
 
-      if function_group is None:
-        sig_error_map[sig] = self.ANNOTATION_ERROR_NOTFOUND
-        continue
+            Returns:
+              symbol: Function symbol. None if it isn't a function head.
+            """
+            result = function_signature_regex.match(line)
+            if result is None:
+                return None
 
-      # The function_group is a list of all the same functions (according to
-      # our assumption) which should be annotated together.
-      signature_map[sig] = function_group
+            address = int(result.group("address"), 16)
+            symbol = symbol_map.get(address)
 
-    return (signature_map, sig_error_map)
+            # Check if the function exists and matches.
+            if symbol is None or symbol.symtype != "F":
+                return None
 
-  def LoadAnnotation(self):
-    """Load annotation rules.
+            return symbol
 
-    Returns:
-      Map of add rules, set of remove rules, set of text signatures which can't
-      be parsed.
-    """
-    # Assume there is no ":" in the path.
-    # Example: "get_range.lto.2501[driver/accel_kionix.c:327]"
-    annotation_signature_regex = re.compile(
-        r'^(?P<name>[^\[]+)(\[(?P<path>[^:]+)(:(?P<linenum>\d+))?\])?$')
-
-    def NormalizeSignature(signature_text):
-      """Parse and normalize the annotation signature.
-
-      Args:
-        signature_text: Text of the annotation signature.
-
-      Returns:
-        (function name, path, line number) of the signature. The path and line
-        number can be None if not exist. None if failed to parse.
-      """
-      result = annotation_signature_regex.match(signature_text.strip())
-      if result is None:
-        return None
-
-      name_result = self.FUNCTION_PREFIX_NAME_RE.match(
-          result.group('name').strip())
-      if name_result is None:
-        return None
-
-      path = result.group('path')
-      if path is not None:
-        path = os.path.realpath(path.strip())
-
-      linenum = result.group('linenum')
-      if linenum is not None:
-        linenum = int(linenum.strip())
-
-      return (name_result.group('name').strip(), path, linenum)
-
-    def ExpandArray(dic):
-      """Parse and expand a symbol array
-
-      Args:
-        dic: Dictionary for the array annotation
-
-      Returns:
-        array of (symbol name, None, None).
-      """
-      # TODO(drinkcat): This function is quite inefficient, as it goes through
-      # the symbol table multiple times.
-
-      begin_name = dic['name']
-      end_name = dic['name'] + "_end"
-      offset = dic['offset'] if 'offset' in dic else 0
-      stride = dic['stride']
-
-      begin_address = None
-      end_address = None
-
-      for symbol in self.symbols:
-        if (symbol.name == begin_name):
-          begin_address = symbol.address
-        if (symbol.name == end_name):
-          end_address = symbol.address
-
-      if (not begin_address or not end_address):
-        return None
-
-      output = []
-      # TODO(drinkcat): This is inefficient as we go from address to symbol
-      # object then to symbol name, and later on we'll go back from symbol name
-      # to symbol object.
-      for addr in range(begin_address+offset, end_address, stride):
-        # TODO(drinkcat): Not all architectures need to drop the first bit.
-        val = self.rodata[(addr-self.rodata_offset) // 4] & 0xfffffffe
-        name = None
+        # Build symbol map, indexed by symbol address.
+        symbol_map = {}
         for symbol in self.symbols:
-          if (symbol.address == val):
-            result = self.FUNCTION_PREFIX_NAME_RE.match(symbol.name)
-            name = result.group('name')
-            break
-
-        if not name:
-          raise StackAnalyzerError('Cannot find function for address %s.',
-                                   hex(val))
-
-        output.append((name, None, None))
-
-      return output
-
-    add_rules = collections.defaultdict(set)
-    remove_rules = list()
-    invalid_sigtxts = set()
-
-    if 'add' in self.annotation and self.annotation['add'] is not None:
-      for src_sigtxt, dst_sigtxts in self.annotation['add'].items():
-        src_sig = NormalizeSignature(src_sigtxt)
-        if src_sig is None:
-          invalid_sigtxts.add(src_sigtxt)
-          continue
-
-        for dst_sigtxt in dst_sigtxts:
-          if isinstance(dst_sigtxt, dict):
-            dst_sig = ExpandArray(dst_sigtxt)
-            if dst_sig is None:
-              invalid_sigtxts.add(str(dst_sigtxt))
+            # If there are multiple symbols with same address, keeping any of them is
+            # good enough.
+            symbol_map[symbol.address] = symbol
+
+        # Parse the disassembly text. We update the variable "line" to next line
+        # when needed. There are two steps of parser:
+        #
+        # Step 1: Searching for the function head. Once reach the function head,
+        # move to the next line, which is the first line of function body.
+        #
+        # Step 2: Parsing each instruction line of function body. Once reach a
+        # non-instruction line, stop parsing and analyze the parsed instructions.
+        #
+        # Finally turn back to the step 1 without updating the line, because the
+        # current non-instruction line can be another function head.
+        function_map = {}
+        # The following three variables are the states of the parsing processing.
+        # They will be initialized properly during the state changes.
+        function_symbol = None
+        function_end = None
+        instructions = []
+
+        # Remove heading and tailing spaces for each line.
+        line_index = 0
+        while line_index < len(disasm_lines):
+            # Get the current line.
+            line = disasm_lines[line_index]
+
+            if function_symbol is None:
+                # Step 1: Search for the function head.
+
+                function_symbol = DetectFunctionHead(line)
+                if function_symbol is not None:
+                    # Assume there is no empty function. If the function head is followed
+                    # by EOF, it is an empty function.
+                    assert line_index + 1 < len(disasm_lines)
+
+                    # Found the function head, initialize and turn to the step 2.
+                    instructions = []
+                    # If symbol size exists, use it as a hint of function size.
+                    if function_symbol.size > 0:
+                        function_end = (
+                            function_symbol.address + function_symbol.size
+                        )
+                    else:
+                        function_end = None
+
             else:
-              add_rules[src_sig].update(dst_sig)
-          else:
-            dst_sig = NormalizeSignature(dst_sigtxt)
-            if dst_sig is None:
-              invalid_sigtxts.add(dst_sigtxt)
+                # Step 2: Parse the function body.
+
+                instruction = analyzer.ParseInstruction(line, function_end)
+                if instruction is not None:
+                    instructions.append(instruction)
+
+                if instruction is None or line_index + 1 == len(disasm_lines):
+                    # Either the invalid instruction or EOF indicates the end of the
+                    # function, finalize the function analysis.
+
+                    # Assume there is no empty function.
+                    assert len(instructions) > 0
+
+                    (stack_frame, callsites) = analyzer.AnalyzeFunction(
+                        function_symbol, instructions
+                    )
+                    # Assume the function addresses are unique in the disassembly.
+                    assert function_symbol.address not in function_map
+                    function_map[function_symbol.address] = Function(
+                        function_symbol.address,
+                        function_symbol.name,
+                        stack_frame,
+                        callsites,
+                    )
+
+                    # Initialize and turn back to the step 1.
+                    function_symbol = None
+
+                    # If the current line isn't an instruction, it can be another function
+                    # head, skip moving to the next line.
+                    if instruction is None:
+                        continue
+
+            # Move to the next line.
+            line_index += 1
+
+        # Resolve callees of functions.
+        for function in function_map.values():
+            for callsite in function.callsites:
+                if callsite.target is not None:
+                    # Remain the callee as None if we can't resolve it.
+                    callsite.callee = function_map.get(callsite.target)
+
+        return function_map
+
+    def MapAnnotation(self, function_map, signature_set):
+        """Map annotation signatures to functions.
+
+        Args:
+          function_map: Function map.
+          signature_set: Set of annotation signatures.
+
+        Returns:
+          Map of signatures to functions, map of signatures which can't be resolved.
+        """
+        # Build the symbol map indexed by symbol name. If there are multiple symbols
+        # with the same name, add them into a set. (e.g. symbols of static function
+        # with the same name)
+        symbol_map = collections.defaultdict(set)
+        for symbol in self.symbols:
+            if symbol.symtype == "F":
+                # Function symbol.
+                result = self.FUNCTION_PREFIX_NAME_RE.match(symbol.name)
+                if result is not None:
+                    function = function_map.get(symbol.address)
+                    # Ignore the symbol not in disassembly.
+                    if function is not None:
+                        # If there are multiple symbol with the same name and point to the
+                        # same function, the set will deduplicate them.
+                        symbol_map[result.group("name").strip()].add(function)
+
+        # Build the signature map indexed by annotation signature.
+        signature_map = {}
+        sig_error_map = {}
+        symbol_path_map = {}
+        for sig in signature_set:
+            (name, path, _) = sig
+
+            functions = symbol_map.get(name)
+            if functions is None:
+                sig_error_map[sig] = self.ANNOTATION_ERROR_NOTFOUND
+                continue
+
+            if name not in symbol_path_map:
+                # Lazy symbol path resolving. Since the addr2line isn't fast, only
+                # resolve needed symbol paths.
+                group_map = collections.defaultdict(list)
+                for function in functions:
+                    line_info = self.AddressToLine(function.address)[0]
+                    if line_info is None:
+                        continue
+
+                    (_, symbol_path, _) = line_info
+
+                    # Group the functions with the same symbol signature (symbol name +
+                    # symbol path). Assume they are the same copies and do the same
+                    # annotation operations of them because we don't know which copy is
+                    # indicated by the users.
+                    group_map[symbol_path].append(function)
+
+                symbol_path_map[name] = group_map
+
+            # Symbol matching.
+            function_group = None
+            group_map = symbol_path_map[name]
+            if len(group_map) > 0:
+                if path is None:
+                    if len(group_map) > 1:
+                        # There is ambiguity but the path isn't specified.
+                        sig_error_map[sig] = self.ANNOTATION_ERROR_AMBIGUOUS
+                        continue
+
+                    # No path signature but all symbol signatures of functions are same.
+                    # Assume they are the same functions, so there is no ambiguity.
+                    (function_group,) = group_map.values()
+                else:
+                    function_group = group_map.get(path)
+
+            if function_group is None:
+                sig_error_map[sig] = self.ANNOTATION_ERROR_NOTFOUND
+                continue
+
+            # The function_group is a list of all the same functions (according to
+            # our assumption) which should be annotated together.
+            signature_map[sig] = function_group
+
+        return (signature_map, sig_error_map)
+
+    def LoadAnnotation(self):
+        """Load annotation rules.
+
+        Returns:
+          Map of add rules, set of remove rules, set of text signatures which can't
+          be parsed.
+        """
+        # Assume there is no ":" in the path.
+        # Example: "get_range.lto.2501[driver/accel_kionix.c:327]"
+        annotation_signature_regex = re.compile(
+            r"^(?P<name>[^\[]+)(\[(?P<path>[^:]+)(:(?P<linenum>\d+))?\])?$"
+        )
+
+        def NormalizeSignature(signature_text):
+            """Parse and normalize the annotation signature.
+
+            Args:
+              signature_text: Text of the annotation signature.
+
+            Returns:
+              (function name, path, line number) of the signature. The path and line
+              number can be None if not exist. None if failed to parse.
+            """
+            result = annotation_signature_regex.match(signature_text.strip())
+            if result is None:
+                return None
+
+            name_result = self.FUNCTION_PREFIX_NAME_RE.match(
+                result.group("name").strip()
+            )
+            if name_result is None:
+                return None
+
+            path = result.group("path")
+            if path is not None:
+                path = os.path.realpath(path.strip())
+
+            linenum = result.group("linenum")
+            if linenum is not None:
+                linenum = int(linenum.strip())
+
+            return (name_result.group("name").strip(), path, linenum)
+
+        def ExpandArray(dic):
+            """Parse and expand a symbol array
+
+            Args:
+              dic: Dictionary for the array annotation
+
+            Returns:
+              array of (symbol name, None, None).
+            """
+            # TODO(drinkcat): This function is quite inefficient, as it goes through
+            # the symbol table multiple times.
+
+            begin_name = dic["name"]
+            end_name = dic["name"] + "_end"
+            offset = dic["offset"] if "offset" in dic else 0
+            stride = dic["stride"]
+
+            begin_address = None
+            end_address = None
+
+            for symbol in self.symbols:
+                if symbol.name == begin_name:
+                    begin_address = symbol.address
+                if symbol.name == end_name:
+                    end_address = symbol.address
+
+            if not begin_address or not end_address:
+                return None
+
+            output = []
+            # TODO(drinkcat): This is inefficient as we go from address to symbol
+            # object then to symbol name, and later on we'll go back from symbol name
+            # to symbol object.
+            for addr in range(begin_address + offset, end_address, stride):
+                # TODO(drinkcat): Not all architectures need to drop the first bit.
+                val = self.rodata[(addr - self.rodata_offset) // 4] & 0xFFFFFFFE
+                name = None
+                for symbol in self.symbols:
+                    if symbol.address == val:
+                        result = self.FUNCTION_PREFIX_NAME_RE.match(symbol.name)
+                        name = result.group("name")
+                        break
+
+                if not name:
+                    raise StackAnalyzerError(
+                        "Cannot find function for address %s." % hex(val)
+                    )
+
+                output.append((name, None, None))
+
+            return output
+
+        add_rules = collections.defaultdict(set)
+        remove_rules = list()
+        invalid_sigtxts = set()
+
+        if "add" in self.annotation and self.annotation["add"] is not None:
+            for src_sigtxt, dst_sigtxts in self.annotation["add"].items():
+                src_sig = NormalizeSignature(src_sigtxt)
+                if src_sig is None:
+                    invalid_sigtxts.add(src_sigtxt)
+                    continue
+
+                for dst_sigtxt in dst_sigtxts:
+                    if isinstance(dst_sigtxt, dict):
+                        dst_sig = ExpandArray(dst_sigtxt)
+                        if dst_sig is None:
+                            invalid_sigtxts.add(str(dst_sigtxt))
+                        else:
+                            add_rules[src_sig].update(dst_sig)
+                    else:
+                        dst_sig = NormalizeSignature(dst_sigtxt)
+                        if dst_sig is None:
+                            invalid_sigtxts.add(dst_sigtxt)
+                        else:
+                            add_rules[src_sig].add(dst_sig)
+
+        if (
+            "remove" in self.annotation
+            and self.annotation["remove"] is not None
+        ):
+            for sigtxt_path in self.annotation["remove"]:
+                if isinstance(sigtxt_path, str):
+                    # The path has only one vertex.
+                    sigtxt_path = [sigtxt_path]
+
+                if len(sigtxt_path) == 0:
+                    continue
+
+                # Generate multiple remove paths from all the combinations of the
+                # signatures of each vertex.
+                sig_paths = [[]]
+                broken_flag = False
+                for sigtxt_node in sigtxt_path:
+                    if isinstance(sigtxt_node, str):
+                        # The vertex has only one signature.
+                        sigtxt_set = {sigtxt_node}
+                    elif isinstance(sigtxt_node, list):
+                        # The vertex has multiple signatures.
+                        sigtxt_set = set(sigtxt_node)
+                    else:
+                        # Assume the format of annotation is verified. There should be no
+                        # invalid case.
+                        assert False
+
+                    sig_set = set()
+                    for sigtxt in sigtxt_set:
+                        sig = NormalizeSignature(sigtxt)
+                        if sig is None:
+                            invalid_sigtxts.add(sigtxt)
+                            broken_flag = True
+                        elif not broken_flag:
+                            sig_set.add(sig)
+
+                    if broken_flag:
+                        continue
+
+                    # Append each signature of the current node to the all previous
+                    # remove paths.
+                    sig_paths = [
+                        path + [sig] for path in sig_paths for sig in sig_set
+                    ]
+
+                if not broken_flag:
+                    # All signatures are normalized. The remove path has no error.
+                    remove_rules.extend(sig_paths)
+
+        return (add_rules, remove_rules, invalid_sigtxts)
+
+    def ResolveAnnotation(self, function_map):
+        """Resolve annotation.
+
+        Args:
+          function_map: Function map.
+
+        Returns:
+          Set of added call edges, list of remove paths, set of eliminated
+          callsite addresses, set of annotation signatures which can't be resolved.
+        """
+
+        def StringifySignature(signature):
+            """Stringify the tupled signature.
+
+            Args:
+              signature: Tupled signature.
+
+            Returns:
+              Signature string.
+            """
+            (name, path, linenum) = signature
+            bracket_text = ""
+            if path is not None:
+                path = os.path.relpath(path)
+                if linenum is None:
+                    bracket_text = "[{}]".format(path)
+                else:
+                    bracket_text = "[{}:{}]".format(path, linenum)
+
+            return name + bracket_text
+
+        (add_rules, remove_rules, invalid_sigtxts) = self.LoadAnnotation()
+
+        signature_set = set()
+        for src_sig, dst_sigs in add_rules.items():
+            signature_set.add(src_sig)
+            signature_set.update(dst_sigs)
+
+        for remove_sigs in remove_rules:
+            signature_set.update(remove_sigs)
+
+        # Map signatures to functions.
+        (signature_map, sig_error_map) = self.MapAnnotation(
+            function_map, signature_set
+        )
+
+        # Build the indirect callsite map indexed by callsite signature.
+        indirect_map = collections.defaultdict(set)
+        for function in function_map.values():
+            for callsite in function.callsites:
+                if callsite.target is not None:
+                    continue
+
+                # Found an indirect callsite.
+                line_info = self.AddressToLine(callsite.address)[0]
+                if line_info is None:
+                    continue
+
+                (name, path, linenum) = line_info
+                result = self.FUNCTION_PREFIX_NAME_RE.match(name)
+                if result is None:
+                    continue
+
+                indirect_map[(result.group("name").strip(), path, linenum)].add(
+                    (function, callsite.address)
+                )
+
+        # Generate the annotation sets.
+        add_set = set()
+        remove_list = list()
+        eliminated_addrs = set()
+
+        for src_sig, dst_sigs in add_rules.items():
+            src_funcs = set(signature_map.get(src_sig, []))
+            # Try to match the source signature to the indirect callsites. Even if it
+            # can't be found in disassembly.
+            indirect_calls = indirect_map.get(src_sig)
+            if indirect_calls is not None:
+                for function, callsite_address in indirect_calls:
+                    # Add the caller of the indirect callsite to the source functions.
+                    src_funcs.add(function)
+                    # Assume each callsite can be represented by a unique address.
+                    eliminated_addrs.add(callsite_address)
+
+                if src_sig in sig_error_map:
+                    # Assume the error is always the not found error. Since the signature
+                    # found in indirect callsite map must be a full signature, it can't
+                    # happen the ambiguous error.
+                    assert (
+                        sig_error_map[src_sig] == self.ANNOTATION_ERROR_NOTFOUND
+                    )
+                    # Found in inline stack, remove the not found error.
+                    del sig_error_map[src_sig]
+
+            for dst_sig in dst_sigs:
+                dst_funcs = signature_map.get(dst_sig)
+                if dst_funcs is None:
+                    continue
+
+                # Duplicate the call edge for all the same source and destination
+                # functions.
+                for src_func in src_funcs:
+                    for dst_func in dst_funcs:
+                        add_set.add((src_func, dst_func))
+
+        for remove_sigs in remove_rules:
+            # Since each signature can be mapped to multiple functions, generate
+            # multiple remove paths from all the combinations of these functions.
+            remove_paths = [[]]
+            skip_flag = False
+            for remove_sig in remove_sigs:
+                # Transform each signature to the corresponding functions.
+                remove_funcs = signature_map.get(remove_sig)
+                if remove_funcs is None:
+                    # There is an unresolved signature in the remove path. Ignore the
+                    # whole broken remove path.
+                    skip_flag = True
+                    break
+                else:
+                    # Append each function of the current signature to the all previous
+                    # remove paths.
+                    remove_paths = [
+                        p + [f] for p in remove_paths for f in remove_funcs
+                    ]
+
+            if skip_flag:
+                # Ignore the broken remove path.
+                continue
+
+            for remove_path in remove_paths:
+                # Deduplicate the remove paths.
+                if remove_path not in remove_list:
+                    remove_list.append(remove_path)
+
+        # Format the error messages.
+        failed_sigtxts = set()
+        for sigtxt in invalid_sigtxts:
+            failed_sigtxts.add((sigtxt, self.ANNOTATION_ERROR_INVALID))
+
+        for sig, error in sig_error_map.items():
+            failed_sigtxts.add((StringifySignature(sig), error))
+
+        return (add_set, remove_list, eliminated_addrs, failed_sigtxts)
+
+    def PreprocessAnnotation(
+        self, function_map, add_set, remove_list, eliminated_addrs
+    ):
+        """Preprocess the annotation and callgraph.
+
+        Add the missing call edges, and delete simple remove paths (the paths have
+        one or two vertices) from the function_map.
+
+        Eliminate the annotated indirect callsites.
+
+        Return the remaining remove list.
+
+        Args:
+          function_map: Function map.
+          add_set: Set of missing call edges.
+          remove_list: List of remove paths.
+          eliminated_addrs: Set of eliminated callsite addresses.
+
+        Returns:
+          List of remaining remove paths.
+        """
+
+        def CheckEdge(path):
+            """Check if all edges of the path are on the callgraph.
+
+            Args:
+              path: Path.
+
+            Returns:
+              True or False.
+            """
+            for index in range(len(path) - 1):
+                if (path[index], path[index + 1]) not in edge_set:
+                    return False
+
+            return True
+
+        for src_func, dst_func in add_set:
+            # TODO(cheyuw): Support tailing call annotation.
+            src_func.callsites.append(
+                Callsite(None, dst_func.address, False, dst_func)
+            )
+
+        # Delete simple remove paths.
+        remove_simple = set(tuple(p) for p in remove_list if len(p) <= 2)
+        edge_set = set()
+        for function in function_map.values():
+            cleaned_callsites = []
+            for callsite in function.callsites:
+                if (callsite.callee,) in remove_simple or (
+                    function,
+                    callsite.callee,
+                ) in remove_simple:
+                    continue
+
+                if (
+                    callsite.target is None
+                    and callsite.address in eliminated_addrs
+                ):
+                    continue
+
+                cleaned_callsites.append(callsite)
+                if callsite.callee is not None:
+                    edge_set.add((function, callsite.callee))
+
+            function.callsites = cleaned_callsites
+
+        return [p for p in remove_list if len(p) >= 3 and CheckEdge(p)]
+
+    def AnalyzeCallGraph(self, function_map, remove_list):
+        """Analyze callgraph.
+
+        It will update the max stack size and path for each function.
+
+        Args:
+          function_map: Function map.
+          remove_list: List of remove paths.
+
+        Returns:
+          List of function cycles.
+        """
+
+        def Traverse(curr_state):
+            """Traverse the callgraph and calculate the max stack usages of functions.
+
+            Args:
+              curr_state: Current state.
+
+            Returns:
+              SCC lowest link.
+            """
+            scc_index = scc_index_counter[0]
+            scc_index_counter[0] += 1
+            scc_index_map[curr_state] = scc_index
+            scc_lowlink = scc_index
+            scc_stack.append(curr_state)
+            # Push the current state in the stack. We can use a set to maintain this
+            # because the stacked states are unique; otherwise we will find a cycle
+            # first.
+            stacked_states.add(curr_state)
+
+            (curr_address, curr_positions) = curr_state
+            curr_func = function_map[curr_address]
+
+            invalid_flag = False
+            new_positions = list(curr_positions)
+            for index, position in enumerate(curr_positions):
+                remove_path = remove_list[index]
+
+                # The position of each remove path in the state is the length of the
+                # longest matching path between the prefix of the remove path and the
+                # suffix of the current traversing path. We maintain this length when
+                # appending the next callee to the traversing path. And it can be used
+                # to check if the remove path appears in the traversing path.
+
+                # TODO(cheyuw): Implement KMP algorithm to match remove paths
+                #               efficiently.
+                if remove_path[position] is curr_func:
+                    # Matches the current function, extend the length.
+                    new_positions[index] = position + 1
+                    if new_positions[index] == len(remove_path):
+                        # The length of the longest matching path is equal to the length of
+                        # the remove path, which means the suffix of the current traversing
+                        # path matches the remove path.
+                        invalid_flag = True
+                        break
+
+                else:
+                    # We can't get the new longest matching path by extending the previous
+                    # one directly. Fallback to search the new longest matching path.
+
+                    # If we can't find any matching path in the following search, reset
+                    # the matching length to 0.
+                    new_positions[index] = 0
+
+                    # We want to find the new longest matching prefix of remove path with
+                    # the suffix of the current traversing path. Because the new longest
+                    # matching path won't be longer than the prevous one now, and part of
+                    # the suffix matches the prefix of remove path, we can get the needed
+                    # suffix from the previous matching prefix of the invalid path.
+                    suffix = remove_path[:position] + [curr_func]
+                    for offset in range(1, len(suffix)):
+                        length = position - offset
+                        if remove_path[:length] == suffix[offset:]:
+                            new_positions[index] = length
+                            break
+
+            new_positions = tuple(new_positions)
+
+            # If the current suffix is invalid, set the max stack usage to 0.
+            max_stack_usage = 0
+            max_callee_state = None
+            self_loop = False
+
+            if not invalid_flag:
+                # Max stack usage is at least equal to the stack frame.
+                max_stack_usage = curr_func.stack_frame
+                for callsite in curr_func.callsites:
+                    callee = callsite.callee
+                    if callee is None:
+                        continue
+
+                    callee_state = (callee.address, new_positions)
+                    if callee_state not in scc_index_map:
+                        # Unvisited state.
+                        scc_lowlink = min(scc_lowlink, Traverse(callee_state))
+                    elif callee_state in stacked_states:
+                        # The state is shown in the stack. There is a cycle.
+                        sub_stack_usage = 0
+                        scc_lowlink = min(
+                            scc_lowlink, scc_index_map[callee_state]
+                        )
+                        if callee_state == curr_state:
+                            self_loop = True
+
+                    done_result = done_states.get(callee_state)
+                    if done_result is not None:
+                        # Already done this state and use its result. If the state reaches a
+                        # cycle, reusing the result will cause inaccuracy (the stack usage
+                        # of cycle depends on where the entrance is). But it's fine since we
+                        # can't get accurate stack usage under this situation, and we rely
+                        # on user-provided annotations to break the cycle, after which the
+                        # result will be accurate again.
+                        (sub_stack_usage, _) = done_result
+
+                        if callsite.is_tail:
+                            # For tailing call, since the callee reuses the stack frame of the
+                            # caller, choose the larger one directly.
+                            stack_usage = max(
+                                curr_func.stack_frame, sub_stack_usage
+                            )
+                        else:
+                            stack_usage = (
+                                curr_func.stack_frame + sub_stack_usage
+                            )
+
+                        if stack_usage > max_stack_usage:
+                            max_stack_usage = stack_usage
+                            max_callee_state = callee_state
+
+            if scc_lowlink == scc_index:
+                group = []
+                while scc_stack[-1] != curr_state:
+                    scc_state = scc_stack.pop()
+                    stacked_states.remove(scc_state)
+                    group.append(scc_state)
+
+                scc_stack.pop()
+                stacked_states.remove(curr_state)
+
+                # If the cycle is not empty, record it.
+                if len(group) > 0 or self_loop:
+                    group.append(curr_state)
+                    cycle_groups.append(group)
+
+            # Store the done result.
+            done_states[curr_state] = (max_stack_usage, max_callee_state)
+
+            if curr_positions == initial_positions:
+                # If the current state is initial state, we traversed the callgraph by
+                # using the current function as start point. Update the stack usage of
+                # the function.
+                # If the function matches a single vertex remove path, this will set its
+                # max stack usage to 0, which is not expected (we still calculate its
+                # max stack usage, but prevent any function from calling it). However,
+                # all the single vertex remove paths have been preprocessed and removed.
+                curr_func.stack_max_usage = max_stack_usage
+
+                # Reconstruct the max stack path by traversing the state transitions.
+                max_stack_path = [curr_func]
+                callee_state = max_callee_state
+                while callee_state is not None:
+                    # The first element of state tuple is function address.
+                    max_stack_path.append(function_map[callee_state[0]])
+                    done_result = done_states.get(callee_state)
+                    # All of the descendants should be done.
+                    assert done_result is not None
+                    (_, callee_state) = done_result
+
+                curr_func.stack_max_path = max_stack_path
+
+            return scc_lowlink
+
+        # The state is the concatenation of the current function address and the
+        # state of matching position.
+        initial_positions = (0,) * len(remove_list)
+        done_states = {}
+        stacked_states = set()
+        scc_index_counter = [0]
+        scc_index_map = {}
+        scc_stack = []
+        cycle_groups = []
+        for function in function_map.values():
+            if function.stack_max_usage is None:
+                Traverse((function.address, initial_positions))
+
+        cycle_functions = []
+        for group in cycle_groups:
+            cycle = set(function_map[state[0]] for state in group)
+            if cycle not in cycle_functions:
+                cycle_functions.append(cycle)
+
+        return cycle_functions
+
+    def Analyze(self):
+        """Run the stack analysis.
+
+        Raises:
+          StackAnalyzerError: If disassembly fails.
+        """
+
+        def OutputInlineStack(address, prefix=""):
+            """Output beautiful inline stack.
+
+            Args:
+              address: Address.
+              prefix: Prefix of each line.
+
+            Returns:
+              Key for sorting, output text
+            """
+            line_infos = self.AddressToLine(address, True)
+
+            if line_infos[0] is None:
+                order_key = (None, None)
             else:
-              add_rules[src_sig].add(dst_sig)
-
-    if 'remove' in self.annotation and self.annotation['remove'] is not None:
-      for sigtxt_path in self.annotation['remove']:
-        if isinstance(sigtxt_path, str):
-          # The path has only one vertex.
-          sigtxt_path = [sigtxt_path]
-
-        if len(sigtxt_path) == 0:
-          continue
-
-        # Generate multiple remove paths from all the combinations of the
-        # signatures of each vertex.
-        sig_paths = [[]]
-        broken_flag = False
-        for sigtxt_node in sigtxt_path:
-          if isinstance(sigtxt_node, str):
-            # The vertex has only one signature.
-            sigtxt_set = {sigtxt_node}
-          elif isinstance(sigtxt_node, list):
-            # The vertex has multiple signatures.
-            sigtxt_set = set(sigtxt_node)
-          else:
-            # Assume the format of annotation is verified. There should be no
-            # invalid case.
-            assert False
-
-          sig_set = set()
-          for sigtxt in sigtxt_set:
-            sig = NormalizeSignature(sigtxt)
-            if sig is None:
-              invalid_sigtxts.add(sigtxt)
-              broken_flag = True
-            elif not broken_flag:
-              sig_set.add(sig)
-
-          if broken_flag:
-            continue
-
-          # Append each signature of the current node to the all previous
-          # remove paths.
-          sig_paths = [path + [sig] for path in sig_paths for sig in sig_set]
-
-        if not broken_flag:
-          # All signatures are normalized. The remove path has no error.
-          remove_rules.extend(sig_paths)
-
-    return (add_rules, remove_rules, invalid_sigtxts)
+                (_, path, linenum) = line_infos[0]
+                order_key = (linenum, path)
+
+            line_texts = []
+            for line_info in reversed(line_infos):
+                if line_info is None:
+                    (function_name, path, linenum) = ("??", "??", 0)
+                else:
+                    (function_name, path, linenum) = line_info
+
+                line_texts.append(
+                    "{}[{}:{}]".format(
+                        function_name, os.path.relpath(path), linenum
+                    )
+                )
+
+            output = "{}-> {} {:x}\n".format(prefix, line_texts[0], address)
+            for depth, line_text in enumerate(line_texts[1:]):
+                output += "{}   {}- {}\n".format(
+                    prefix, "  " * depth, line_text
+                )
+
+            # Remove the last newline character.
+            return (order_key, output.rstrip("\n"))
+
+        # Analyze disassembly.
+        try:
+            disasm_text = subprocess.check_output(
+                [self.options.objdump, "-d", self.options.elf_path],
+                encoding="utf-8",
+            )
+        except subprocess.CalledProcessError:
+            raise StackAnalyzerError("objdump failed to disassemble.")
+        except OSError:
+            raise StackAnalyzerError("Failed to run objdump.")
+
+        function_map = self.AnalyzeDisassembly(disasm_text)
+        result = self.ResolveAnnotation(function_map)
+        (add_set, remove_list, eliminated_addrs, failed_sigtxts) = result
+        remove_list = self.PreprocessAnnotation(
+            function_map, add_set, remove_list, eliminated_addrs
+        )
+        cycle_functions = self.AnalyzeCallGraph(function_map, remove_list)
+
+        # Print the results of task-aware stack analysis.
+        extra_stack_frame = self.annotation.get(
+            "exception_frame_size", DEFAULT_EXCEPTION_FRAME_SIZE
+        )
+        for task in self.tasklist:
+            routine_func = function_map[task.routine_address]
+            print(
+                "Task: {}, Max size: {} ({} + {}), Allocated size: {}".format(
+                    task.name,
+                    routine_func.stack_max_usage + extra_stack_frame,
+                    routine_func.stack_max_usage,
+                    extra_stack_frame,
+                    task.stack_max_size,
+                )
+            )
+
+            print("Call Trace:")
+            max_stack_path = routine_func.stack_max_path
+            # Assume the routine function is resolved.
+            assert max_stack_path is not None
+            for depth, curr_func in enumerate(max_stack_path):
+                line_info = self.AddressToLine(curr_func.address)[0]
+                if line_info is None:
+                    (path, linenum) = ("??", 0)
+                else:
+                    (_, path, linenum) = line_info
+
+                print(
+                    "    {} ({}) [{}:{}] {:x}".format(
+                        curr_func.name,
+                        curr_func.stack_frame,
+                        os.path.relpath(path),
+                        linenum,
+                        curr_func.address,
+                    )
+                )
+
+                if depth + 1 < len(max_stack_path):
+                    succ_func = max_stack_path[depth + 1]
+                    text_list = []
+                    for callsite in curr_func.callsites:
+                        if callsite.callee is succ_func:
+                            indent_prefix = "        "
+                            if callsite.address is None:
+                                order_text = (
+                                    None,
+                                    "{}-> [annotation]".format(indent_prefix),
+                                )
+                            else:
+                                order_text = OutputInlineStack(
+                                    callsite.address, indent_prefix
+                                )
+
+                            text_list.append(order_text)
+
+                    for _, text in sorted(text_list, key=lambda item: item[0]):
+                        print(text)
+
+        print("Unresolved indirect callsites:")
+        for function in function_map.values():
+            indirect_callsites = []
+            for callsite in function.callsites:
+                if callsite.target is None:
+                    indirect_callsites.append(callsite.address)
+
+            if len(indirect_callsites) > 0:
+                print("    In function {}:".format(function.name))
+                text_list = []
+                for address in indirect_callsites:
+                    text_list.append(OutputInlineStack(address, "        "))
+
+                for _, text in sorted(text_list, key=lambda item: item[0]):
+                    print(text)
+
+        print("Unresolved annotation signatures:")
+        for sigtxt, error in failed_sigtxts:
+            print("    {}: {}".format(sigtxt, error))
+
+        if len(cycle_functions) > 0:
+            print("There are cycles in the following function sets:")
+            for functions in cycle_functions:
+                print(
+                    "[{}]".format(
+                        ", ".join(function.name for function in functions)
+                    )
+                )
 
-  def ResolveAnnotation(self, function_map):
-    """Resolve annotation.
 
-    Args:
-      function_map: Function map.
+def ParseArgs():
+    """Parse commandline arguments.
 
     Returns:
-      Set of added call edges, list of remove paths, set of eliminated
-      callsite addresses, set of annotation signatures which can't be resolved.
+      options: Namespace from argparse.parse_args().
     """
-    def StringifySignature(signature):
-      """Stringify the tupled signature.
-
-      Args:
-        signature: Tupled signature.
-
-      Returns:
-        Signature string.
-      """
-      (name, path, linenum) = signature
-      bracket_text = ''
-      if path is not None:
-        path = os.path.relpath(path)
-        if linenum is None:
-          bracket_text = '[{}]'.format(path)
-        else:
-          bracket_text = '[{}:{}]'.format(path, linenum)
-
-      return name + bracket_text
-
-    (add_rules, remove_rules, invalid_sigtxts) = self.LoadAnnotation()
-
-    signature_set = set()
-    for src_sig, dst_sigs in add_rules.items():
-      signature_set.add(src_sig)
-      signature_set.update(dst_sigs)
-
-    for remove_sigs in remove_rules:
-      signature_set.update(remove_sigs)
-
-    # Map signatures to functions.
-    (signature_map, sig_error_map) = self.MapAnnotation(function_map,
-                                                        signature_set)
-
-    # Build the indirect callsite map indexed by callsite signature.
-    indirect_map = collections.defaultdict(set)
-    for function in function_map.values():
-      for callsite in function.callsites:
-        if callsite.target is not None:
-          continue
-
-        # Found an indirect callsite.
-        line_info = self.AddressToLine(callsite.address)[0]
-        if line_info is None:
-          continue
-
-        (name, path, linenum) = line_info
-        result = self.FUNCTION_PREFIX_NAME_RE.match(name)
-        if result is None:
-          continue
-
-        indirect_map[(result.group('name').strip(), path, linenum)].add(
-            (function, callsite.address))
-
-    # Generate the annotation sets.
-    add_set = set()
-    remove_list = list()
-    eliminated_addrs = set()
-
-    for src_sig, dst_sigs in add_rules.items():
-      src_funcs = set(signature_map.get(src_sig, []))
-      # Try to match the source signature to the indirect callsites. Even if it
-      # can't be found in disassembly.
-      indirect_calls = indirect_map.get(src_sig)
-      if indirect_calls is not None:
-        for function, callsite_address in indirect_calls:
-          # Add the caller of the indirect callsite to the source functions.
-          src_funcs.add(function)
-          # Assume each callsite can be represented by a unique address.
-          eliminated_addrs.add(callsite_address)
-
-        if src_sig in sig_error_map:
-          # Assume the error is always the not found error. Since the signature
-          # found in indirect callsite map must be a full signature, it can't
-          # happen the ambiguous error.
-          assert sig_error_map[src_sig] == self.ANNOTATION_ERROR_NOTFOUND
-          # Found in inline stack, remove the not found error.
-          del sig_error_map[src_sig]
-
-      for dst_sig in dst_sigs:
-        dst_funcs = signature_map.get(dst_sig)
-        if dst_funcs is None:
-          continue
-
-        # Duplicate the call edge for all the same source and destination
-        # functions.
-        for src_func in src_funcs:
-          for dst_func in dst_funcs:
-            add_set.add((src_func, dst_func))
-
-    for remove_sigs in remove_rules:
-      # Since each signature can be mapped to multiple functions, generate
-      # multiple remove paths from all the combinations of these functions.
-      remove_paths = [[]]
-      skip_flag = False
-      for remove_sig in remove_sigs:
-        # Transform each signature to the corresponding functions.
-        remove_funcs = signature_map.get(remove_sig)
-        if remove_funcs is None:
-          # There is an unresolved signature in the remove path. Ignore the
-          # whole broken remove path.
-          skip_flag = True
-          break
-        else:
-          # Append each function of the current signature to the all previous
-          # remove paths.
-          remove_paths = [p + [f] for p in remove_paths for f in remove_funcs]
-
-      if skip_flag:
-        # Ignore the broken remove path.
-        continue
-
-      for remove_path in remove_paths:
-        # Deduplicate the remove paths.
-        if remove_path not in remove_list:
-          remove_list.append(remove_path)
-
-    # Format the error messages.
-    failed_sigtxts = set()
-    for sigtxt in invalid_sigtxts:
-      failed_sigtxts.add((sigtxt, self.ANNOTATION_ERROR_INVALID))
-
-    for sig, error in sig_error_map.items():
-      failed_sigtxts.add((StringifySignature(sig), error))
-
-    return (add_set, remove_list, eliminated_addrs, failed_sigtxts)
-
-  def PreprocessAnnotation(self, function_map, add_set, remove_list,
-                           eliminated_addrs):
-    """Preprocess the annotation and callgraph.
+    parser = argparse.ArgumentParser(description="EC firmware stack analyzer.")
+    parser.add_argument("elf_path", help="the path of EC firmware ELF")
+    parser.add_argument(
+        "--export_taskinfo",
+        required=True,
+        help="the path of export_taskinfo.so utility",
+    )
+    parser.add_argument(
+        "--section",
+        required=True,
+        help="the section.",
+        choices=[SECTION_RO, SECTION_RW],
+    )
+    parser.add_argument(
+        "--objdump", default="objdump", help="the path of objdump"
+    )
+    parser.add_argument(
+        "--addr2line", default="addr2line", help="the path of addr2line"
+    )
+    parser.add_argument(
+        "--annotation", default=None, help="the path of annotation file"
+    )
+
+    # TODO(cheyuw): Add an option for dumping stack usage of all functions.
+
+    return parser.parse_args()
 
-    Add the missing call edges, and delete simple remove paths (the paths have
-    one or two vertices) from the function_map.
 
-    Eliminate the annotated indirect callsites.
-
-    Return the remaining remove list.
+def ParseSymbolText(symbol_text):
+    """Parse the content of the symbol text.
 
     Args:
-      function_map: Function map.
-      add_set: Set of missing call edges.
-      remove_list: List of remove paths.
-      eliminated_addrs: Set of eliminated callsite addresses.
+      symbol_text: Text of the symbols.
 
     Returns:
-      List of remaining remove paths.
+      symbols: Symbol list.
     """
-    def CheckEdge(path):
-      """Check if all edges of the path are on the callgraph.
-
-      Args:
-        path: Path.
-
-      Returns:
-        True or False.
-      """
-      for index in range(len(path) - 1):
-        if (path[index], path[index + 1]) not in edge_set:
-          return False
-
-      return True
-
-    for src_func, dst_func in add_set:
-      # TODO(cheyuw): Support tailing call annotation.
-      src_func.callsites.append(
-          Callsite(None, dst_func.address, False, dst_func))
-
-    # Delete simple remove paths.
-    remove_simple = set(tuple(p) for p in remove_list if len(p) <= 2)
-    edge_set = set()
-    for function in function_map.values():
-      cleaned_callsites = []
-      for callsite in function.callsites:
-        if ((callsite.callee,) in remove_simple or
-            (function, callsite.callee) in remove_simple):
-          continue
-
-        if callsite.target is None and callsite.address in eliminated_addrs:
-          continue
-
-        cleaned_callsites.append(callsite)
-        if callsite.callee is not None:
-          edge_set.add((function, callsite.callee))
+    # Example: "10093064 g     F .text  0000015c .hidden hook_task"
+    symbol_regex = re.compile(
+        r"^(?P<address>[0-9A-Fa-f]+)\s+[lwg]\s+"
+        r"((?P<type>[OF])\s+)?\S+\s+"
+        r"(?P<size>[0-9A-Fa-f]+)\s+"
+        r"(\S+\s+)?(?P<name>\S+)$"
+    )
+
+    symbols = []
+    for line in symbol_text.splitlines():
+        line = line.strip()
+        result = symbol_regex.match(line)
+        if result is not None:
+            address = int(result.group("address"), 16)
+            symtype = result.group("type")
+            if symtype is None:
+                symtype = "O"
 
-      function.callsites = cleaned_callsites
+            size = int(result.group("size"), 16)
+            name = result.group("name")
+            symbols.append(Symbol(address, symtype, size, name))
 
-    return [p for p in remove_list if len(p) >= 3 and CheckEdge(p)]
+    return symbols
 
-  def AnalyzeCallGraph(self, function_map, remove_list):
-    """Analyze callgraph.
 
-    It will update the max stack size and path for each function.
+def ParseRoDataText(rodata_text):
+    """Parse the content of rodata
 
     Args:
-      function_map: Function map.
-      remove_list: List of remove paths.
+      symbol_text: Text of the rodata dump.
 
     Returns:
-      List of function cycles.
+      symbols: Symbol list.
     """
-    def Traverse(curr_state):
-      """Traverse the callgraph and calculate the max stack usages of functions.
-
-      Args:
-        curr_state: Current state.
-
-      Returns:
-        SCC lowest link.
-      """
-      scc_index = scc_index_counter[0]
-      scc_index_counter[0] += 1
-      scc_index_map[curr_state] = scc_index
-      scc_lowlink = scc_index
-      scc_stack.append(curr_state)
-      # Push the current state in the stack. We can use a set to maintain this
-      # because the stacked states are unique; otherwise we will find a cycle
-      # first.
-      stacked_states.add(curr_state)
-
-      (curr_address, curr_positions) = curr_state
-      curr_func = function_map[curr_address]
-
-      invalid_flag = False
-      new_positions = list(curr_positions)
-      for index, position in enumerate(curr_positions):
-        remove_path = remove_list[index]
-
-        # The position of each remove path in the state is the length of the
-        # longest matching path between the prefix of the remove path and the
-        # suffix of the current traversing path. We maintain this length when
-        # appending the next callee to the traversing path. And it can be used
-        # to check if the remove path appears in the traversing path.
-
-        # TODO(cheyuw): Implement KMP algorithm to match remove paths
-        #               efficiently.
-        if remove_path[position] is curr_func:
-          # Matches the current function, extend the length.
-          new_positions[index] = position + 1
-          if new_positions[index] == len(remove_path):
-            # The length of the longest matching path is equal to the length of
-            # the remove path, which means the suffix of the current traversing
-            # path matches the remove path.
-            invalid_flag = True
-            break
-
-        else:
-          # We can't get the new longest matching path by extending the previous
-          # one directly. Fallback to search the new longest matching path.
-
-          # If we can't find any matching path in the following search, reset
-          # the matching length to 0.
-          new_positions[index] = 0
-
-          # We want to find the new longest matching prefix of remove path with
-          # the suffix of the current traversing path. Because the new longest
-          # matching path won't be longer than the prevous one now, and part of
-          # the suffix matches the prefix of remove path, we can get the needed
-          # suffix from the previous matching prefix of the invalid path.
-          suffix = remove_path[:position] + [curr_func]
-          for offset in range(1, len(suffix)):
-            length = position - offset
-            if remove_path[:length] == suffix[offset:]:
-              new_positions[index] = length
-              break
-
-      new_positions = tuple(new_positions)
-
-      # If the current suffix is invalid, set the max stack usage to 0.
-      max_stack_usage = 0
-      max_callee_state = None
-      self_loop = False
-
-      if not invalid_flag:
-        # Max stack usage is at least equal to the stack frame.
-        max_stack_usage = curr_func.stack_frame
-        for callsite in curr_func.callsites:
-          callee = callsite.callee
-          if callee is None:
+    # Examples: 8018ab0 00040048 00010000 10020000 4b8e0108  ...H........K...
+    #           100a7294 00000000 00000000 01000000           ............
+
+    base_offset = None
+    offset = None
+    rodata = []
+    for line in rodata_text.splitlines():
+        line = line.strip()
+        space = line.find(" ")
+        if space < 0:
+            continue
+        try:
+            address = int(line[0:space], 16)
+        except ValueError:
             continue
 
-          callee_state = (callee.address, new_positions)
-          if callee_state not in scc_index_map:
-            # Unvisited state.
-            scc_lowlink = min(scc_lowlink, Traverse(callee_state))
-          elif callee_state in stacked_states:
-            # The state is shown in the stack. There is a cycle.
-            sub_stack_usage = 0
-            scc_lowlink = min(scc_lowlink, scc_index_map[callee_state])
-            if callee_state == curr_state:
-              self_loop = True
-
-          done_result = done_states.get(callee_state)
-          if done_result is not None:
-            # Already done this state and use its result. If the state reaches a
-            # cycle, reusing the result will cause inaccuracy (the stack usage
-            # of cycle depends on where the entrance is). But it's fine since we
-            # can't get accurate stack usage under this situation, and we rely
-            # on user-provided annotations to break the cycle, after which the
-            # result will be accurate again.
-            (sub_stack_usage, _) = done_result
-
-            if callsite.is_tail:
-              # For tailing call, since the callee reuses the stack frame of the
-              # caller, choose the larger one directly.
-              stack_usage = max(curr_func.stack_frame, sub_stack_usage)
-            else:
-              stack_usage = curr_func.stack_frame + sub_stack_usage
-
-            if stack_usage > max_stack_usage:
-              max_stack_usage = stack_usage
-              max_callee_state = callee_state
-
-      if scc_lowlink == scc_index:
-        group = []
-        while scc_stack[-1] != curr_state:
-          scc_state = scc_stack.pop()
-          stacked_states.remove(scc_state)
-          group.append(scc_state)
-
-        scc_stack.pop()
-        stacked_states.remove(curr_state)
-
-        # If the cycle is not empty, record it.
-        if len(group) > 0 or self_loop:
-          group.append(curr_state)
-          cycle_groups.append(group)
-
-      # Store the done result.
-      done_states[curr_state] = (max_stack_usage, max_callee_state)
-
-      if curr_positions == initial_positions:
-        # If the current state is initial state, we traversed the callgraph by
-        # using the current function as start point. Update the stack usage of
-        # the function.
-        # If the function matches a single vertex remove path, this will set its
-        # max stack usage to 0, which is not expected (we still calculate its
-        # max stack usage, but prevent any function from calling it). However,
-        # all the single vertex remove paths have been preprocessed and removed.
-        curr_func.stack_max_usage = max_stack_usage
-
-        # Reconstruct the max stack path by traversing the state transitions.
-        max_stack_path = [curr_func]
-        callee_state = max_callee_state
-        while callee_state is not None:
-          # The first element of state tuple is function address.
-          max_stack_path.append(function_map[callee_state[0]])
-          done_result = done_states.get(callee_state)
-          # All of the descendants should be done.
-          assert done_result is not None
-          (_, callee_state) = done_result
-
-        curr_func.stack_max_path = max_stack_path
-
-      return scc_lowlink
-
-    # The state is the concatenation of the current function address and the
-    # state of matching position.
-    initial_positions = (0,) * len(remove_list)
-    done_states = {}
-    stacked_states = set()
-    scc_index_counter = [0]
-    scc_index_map = {}
-    scc_stack = []
-    cycle_groups = []
-    for function in function_map.values():
-      if function.stack_max_usage is None:
-        Traverse((function.address, initial_positions))
-
-    cycle_functions = []
-    for group in cycle_groups:
-      cycle = set(function_map[state[0]] for state in group)
-      if cycle not in cycle_functions:
-        cycle_functions.append(cycle)
-
-    return cycle_functions
-
-  def Analyze(self):
-    """Run the stack analysis.
-
-    Raises:
-      StackAnalyzerError: If disassembly fails.
-    """
-    def OutputInlineStack(address, prefix=''):
-      """Output beautiful inline stack.
-
-      Args:
-        address: Address.
-        prefix: Prefix of each line.
-
-      Returns:
-        Key for sorting, output text
-      """
-      line_infos = self.AddressToLine(address, True)
-
-      if line_infos[0] is None:
-        order_key = (None, None)
-      else:
-        (_, path, linenum) = line_infos[0]
-        order_key = (linenum, path)
-
-      line_texts = []
-      for line_info in reversed(line_infos):
-        if line_info is None:
-          (function_name, path, linenum) = ('??', '??', 0)
-        else:
-          (function_name, path, linenum) = line_info
-
-        line_texts.append('{}[{}:{}]'.format(function_name,
-                                             os.path.relpath(path),
-                                             linenum))
-
-      output = '{}-> {} {:x}\n'.format(prefix, line_texts[0], address)
-      for depth, line_text in enumerate(line_texts[1:]):
-        output += '{}   {}- {}\n'.format(prefix, '  ' * depth, line_text)
-
-      # Remove the last newline character.
-      return (order_key, output.rstrip('\n'))
-
-    # Analyze disassembly.
-    try:
-      disasm_text = subprocess.check_output([self.options.objdump,
-                                             '-d',
-                                             self.options.elf_path],
-                                            encoding='utf-8')
-    except subprocess.CalledProcessError:
-      raise StackAnalyzerError('objdump failed to disassemble.')
-    except OSError:
-      raise StackAnalyzerError('Failed to run objdump.')
-
-    function_map = self.AnalyzeDisassembly(disasm_text)
-    result = self.ResolveAnnotation(function_map)
-    (add_set, remove_list, eliminated_addrs, failed_sigtxts) = result
-    remove_list = self.PreprocessAnnotation(function_map,
-                                            add_set,
-                                            remove_list,
-                                            eliminated_addrs)
-    cycle_functions = self.AnalyzeCallGraph(function_map, remove_list)
-
-    # Print the results of task-aware stack analysis.
-    extra_stack_frame = self.annotation.get('exception_frame_size',
-                                            DEFAULT_EXCEPTION_FRAME_SIZE)
-    for task in self.tasklist:
-      routine_func = function_map[task.routine_address]
-      print('Task: {}, Max size: {} ({} + {}), Allocated size: {}'.format(
-          task.name,
-          routine_func.stack_max_usage + extra_stack_frame,
-          routine_func.stack_max_usage,
-          extra_stack_frame,
-          task.stack_max_size))
-
-      print('Call Trace:')
-      max_stack_path = routine_func.stack_max_path
-      # Assume the routine function is resolved.
-      assert max_stack_path is not None
-      for depth, curr_func in enumerate(max_stack_path):
-        line_info = self.AddressToLine(curr_func.address)[0]
-        if line_info is None:
-          (path, linenum) = ('??', 0)
-        else:
-          (_, path, linenum) = line_info
-
-        print('    {} ({}) [{}:{}] {:x}'.format(curr_func.name,
-                                                curr_func.stack_frame,
-                                                os.path.relpath(path),
-                                                linenum,
-                                                curr_func.address))
-
-        if depth + 1 < len(max_stack_path):
-          succ_func = max_stack_path[depth + 1]
-          text_list = []
-          for callsite in curr_func.callsites:
-            if callsite.callee is succ_func:
-              indent_prefix = '        '
-              if callsite.address is None:
-                order_text = (None, '{}-> [annotation]'.format(indent_prefix))
-              else:
-                order_text = OutputInlineStack(callsite.address, indent_prefix)
-
-              text_list.append(order_text)
-
-          for _, text in sorted(text_list, key=lambda item: item[0]):
-            print(text)
-
-    print('Unresolved indirect callsites:')
-    for function in function_map.values():
-      indirect_callsites = []
-      for callsite in function.callsites:
-        if callsite.target is None:
-          indirect_callsites.append(callsite.address)
-
-      if len(indirect_callsites) > 0:
-        print('    In function {}:'.format(function.name))
-        text_list = []
-        for address in indirect_callsites:
-          text_list.append(OutputInlineStack(address, '        '))
-
-        for _, text in sorted(text_list, key=lambda item: item[0]):
-          print(text)
-
-    print('Unresolved annotation signatures:')
-    for sigtxt, error in failed_sigtxts:
-      print('    {}: {}'.format(sigtxt, error))
-
-    if len(cycle_functions) > 0:
-      print('There are cycles in the following function sets:')
-      for functions in cycle_functions:
-        print('[{}]'.format(', '.join(function.name for function in functions)))
-
-
-def ParseArgs():
-  """Parse commandline arguments.
-
-  Returns:
-    options: Namespace from argparse.parse_args().
-  """
-  parser = argparse.ArgumentParser(description="EC firmware stack analyzer.")
-  parser.add_argument('elf_path', help="the path of EC firmware ELF")
-  parser.add_argument('--export_taskinfo', required=True,
-                      help="the path of export_taskinfo.so utility")
-  parser.add_argument('--section', required=True, help='the section.',
-                      choices=[SECTION_RO, SECTION_RW])
-  parser.add_argument('--objdump', default='objdump',
-                      help='the path of objdump')
-  parser.add_argument('--addr2line', default='addr2line',
-                      help='the path of addr2line')
-  parser.add_argument('--annotation', default=None,
-                      help='the path of annotation file')
-
-  # TODO(cheyuw): Add an option for dumping stack usage of all functions.
-
-  return parser.parse_args()
-
-
-def ParseSymbolText(symbol_text):
-  """Parse the content of the symbol text.
-
-  Args:
-    symbol_text: Text of the symbols.
-
-  Returns:
-    symbols: Symbol list.
-  """
-  # Example: "10093064 g     F .text  0000015c .hidden hook_task"
-  symbol_regex = re.compile(r'^(?P<address>[0-9A-Fa-f]+)\s+[lwg]\s+'
-                            r'((?P<type>[OF])\s+)?\S+\s+'
-                            r'(?P<size>[0-9A-Fa-f]+)\s+'
-                            r'(\S+\s+)?(?P<name>\S+)$')
-
-  symbols = []
-  for line in symbol_text.splitlines():
-    line = line.strip()
-    result = symbol_regex.match(line)
-    if result is not None:
-      address = int(result.group('address'), 16)
-      symtype = result.group('type')
-      if symtype is None:
-        symtype = 'O'
-
-      size = int(result.group('size'), 16)
-      name = result.group('name')
-      symbols.append(Symbol(address, symtype, size, name))
-
-  return symbols
-
-
-def ParseRoDataText(rodata_text):
-  """Parse the content of rodata
-
-  Args:
-    symbol_text: Text of the rodata dump.
-
-  Returns:
-    symbols: Symbol list.
-  """
-  # Examples: 8018ab0 00040048 00010000 10020000 4b8e0108  ...H........K...
-  #           100a7294 00000000 00000000 01000000           ............
-
-  base_offset = None
-  offset = None
-  rodata = []
-  for line in rodata_text.splitlines():
-    line = line.strip()
-    space = line.find(' ')
-    if space < 0:
-        continue
-    try:
-      address = int(line[0:space], 16)
-    except ValueError:
-      continue
-
-    if not base_offset:
-      base_offset = address
-      offset = address
-    elif address != offset:
-      raise StackAnalyzerError('objdump of rodata not contiguous.')
+        if not base_offset:
+            base_offset = address
+            offset = address
+        elif address != offset:
+            raise StackAnalyzerError("objdump of rodata not contiguous.")
 
-    for i in range(0, 4):
-      num = line[(space + 1 + i*9):(space + 9 + i*9)]
-      if len(num.strip()) > 0:
-        val = int(num, 16)
-      else:
-        val = 0
-      # TODO(drinkcat): Not all platforms are necessarily big-endian
-      rodata.append((val & 0x000000ff) << 24 |
-                    (val & 0x0000ff00) << 8 |
-                    (val & 0x00ff0000) >> 8 |
-                    (val & 0xff000000) >> 24)
+        for i in range(0, 4):
+            num = line[(space + 1 + i * 9) : (space + 9 + i * 9)]
+            if len(num.strip()) > 0:
+                val = int(num, 16)
+            else:
+                val = 0
+            # TODO(drinkcat): Not all platforms are necessarily big-endian
+            rodata.append(
+                (val & 0x000000FF) << 24
+                | (val & 0x0000FF00) << 8
+                | (val & 0x00FF0000) >> 8
+                | (val & 0xFF000000) >> 24
+            )
 
-    offset = offset + 4*4
+        offset = offset + 4 * 4
 
-  return (base_offset, rodata)
+    return (base_offset, rodata)
 
 
 def LoadTasklist(section, export_taskinfo, symbols):
-  """Load the task information.
+    """Load the task information.
 
-  Args:
-    section: Section (RO | RW).
-    export_taskinfo: Handle of export_taskinfo.so.
-    symbols: Symbol list.
+    Args:
+      section: Section (RO | RW).
+      export_taskinfo: Handle of export_taskinfo.so.
+      symbols: Symbol list.
 
-  Returns:
-    tasklist: Task list.
-  """
+    Returns:
+      tasklist: Task list.
+    """
 
-  TaskInfoPointer = ctypes.POINTER(TaskInfo)
-  taskinfos = TaskInfoPointer()
-  if section == SECTION_RO:
-    get_taskinfos_func = export_taskinfo.get_ro_taskinfos
-  else:
-    get_taskinfos_func = export_taskinfo.get_rw_taskinfos
+    TaskInfoPointer = ctypes.POINTER(TaskInfo)
+    taskinfos = TaskInfoPointer()
+    if section == SECTION_RO:
+        get_taskinfos_func = export_taskinfo.get_ro_taskinfos
+    else:
+        get_taskinfos_func = export_taskinfo.get_rw_taskinfos
 
-  taskinfo_num = get_taskinfos_func(ctypes.pointer(taskinfos))
+    taskinfo_num = get_taskinfos_func(ctypes.pointer(taskinfos))
 
-  tasklist = []
-  for index in range(taskinfo_num):
-    taskinfo = taskinfos[index]
-    tasklist.append(Task(taskinfo.name.decode('utf-8'),
-                         taskinfo.routine.decode('utf-8'),
-                         taskinfo.stack_size))
+    tasklist = []
+    for index in range(taskinfo_num):
+        taskinfo = taskinfos[index]
+        tasklist.append(
+            Task(
+                taskinfo.name.decode("utf-8"),
+                taskinfo.routine.decode("utf-8"),
+                taskinfo.stack_size,
+            )
+        )
 
-  # Resolve routine address for each task. It's more efficient to resolve all
-  # routine addresses of tasks together.
-  routine_map = dict((task.routine_name, None) for task in tasklist)
+    # Resolve routine address for each task. It's more efficient to resolve all
+    # routine addresses of tasks together.
+    routine_map = dict((task.routine_name, None) for task in tasklist)
 
-  for symbol in symbols:
-    # Resolve task routine address.
-    if symbol.name in routine_map:
-      # Assume the symbol of routine is unique.
-      assert routine_map[symbol.name] is None
-      routine_map[symbol.name] = symbol.address
+    for symbol in symbols:
+        # Resolve task routine address.
+        if symbol.name in routine_map:
+            # Assume the symbol of routine is unique.
+            assert routine_map[symbol.name] is None
+            routine_map[symbol.name] = symbol.address
 
-  for task in tasklist:
-    address = routine_map[task.routine_name]
-    # Assume we have resolved all routine addresses.
-    assert address is not None
-    task.routine_address = address
+    for task in tasklist:
+        address = routine_map[task.routine_name]
+        # Assume we have resolved all routine addresses.
+        assert address is not None
+        task.routine_address = address
 
-  return tasklist
+    return tasklist
 
 
 def main():
-  """Main function."""
-  try:
-    options = ParseArgs()
-
-    # Load annotation config.
-    if options.annotation is None:
-      annotation = {}
-    elif not os.path.exists(options.annotation):
-      print('Warning: Annotation file {} does not exist.'
-            .format(options.annotation))
-      annotation = {}
-    else:
-      try:
-        with open(options.annotation, 'r') as annotation_file:
-          annotation = yaml.safe_load(annotation_file)
-
-      except yaml.YAMLError:
-        raise StackAnalyzerError('Failed to parse annotation file {}.'
-                                 .format(options.annotation))
-      except IOError:
-        raise StackAnalyzerError('Failed to open annotation file {}.'
-                                 .format(options.annotation))
-
-      # TODO(cheyuw): Do complete annotation format verification.
-      if not isinstance(annotation, dict):
-        raise StackAnalyzerError('Invalid annotation file {}.'
-                                 .format(options.annotation))
-
-    # Generate and parse the symbols.
+    """Main function."""
     try:
-      symbol_text = subprocess.check_output([options.objdump,
-                                             '-t',
-                                             options.elf_path],
-                                            encoding='utf-8')
-      rodata_text = subprocess.check_output([options.objdump,
-                                             '-s',
-                                             '-j', '.rodata',
-                                             options.elf_path],
-                                            encoding='utf-8')
-    except subprocess.CalledProcessError:
-      raise StackAnalyzerError('objdump failed to dump symbol table or rodata.')
-    except OSError:
-      raise StackAnalyzerError('Failed to run objdump.')
-
-    symbols = ParseSymbolText(symbol_text)
-    rodata = ParseRoDataText(rodata_text)
-
-    # Load the tasklist.
-    try:
-      export_taskinfo = ctypes.CDLL(options.export_taskinfo)
-    except OSError:
-      raise StackAnalyzerError('Failed to load export_taskinfo.')
-
-    tasklist = LoadTasklist(options.section, export_taskinfo, symbols)
-
-    analyzer = StackAnalyzer(options, symbols, rodata, tasklist, annotation)
-    analyzer.Analyze()
-  except StackAnalyzerError as e:
-    print('Error: {}'.format(e))
-
-
-if __name__ == '__main__':
-  main()
+        options = ParseArgs()
+
+        # Load annotation config.
+        if options.annotation is None:
+            annotation = {}
+        elif not os.path.exists(options.annotation):
+            print(
+                "Warning: Annotation file {} does not exist.".format(
+                    options.annotation
+                )
+            )
+            annotation = {}
+        else:
+            try:
+                with open(options.annotation, "r") as annotation_file:
+                    annotation = yaml.safe_load(annotation_file)
+
+            except yaml.YAMLError:
+                raise StackAnalyzerError(
+                    "Failed to parse annotation file {}.".format(
+                        options.annotation
+                    )
+                )
+            except IOError:
+                raise StackAnalyzerError(
+                    "Failed to open annotation file {}.".format(
+                        options.annotation
+                    )
+                )
+
+            # TODO(cheyuw): Do complete annotation format verification.
+            if not isinstance(annotation, dict):
+                raise StackAnalyzerError(
+                    "Invalid annotation file {}.".format(options.annotation)
+                )
+
+        # Generate and parse the symbols.
+        try:
+            symbol_text = subprocess.check_output(
+                [options.objdump, "-t", options.elf_path], encoding="utf-8"
+            )
+            rodata_text = subprocess.check_output(
+                [options.objdump, "-s", "-j", ".rodata", options.elf_path],
+                encoding="utf-8",
+            )
+        except subprocess.CalledProcessError:
+            raise StackAnalyzerError(
+                "objdump failed to dump symbol table or rodata."
+            )
+        except OSError:
+            raise StackAnalyzerError("Failed to run objdump.")
+
+        symbols = ParseSymbolText(symbol_text)
+        rodata = ParseRoDataText(rodata_text)
+
+        # Load the tasklist.
+        try:
+            export_taskinfo = ctypes.CDLL(options.export_taskinfo)
+        except OSError:
+            raise StackAnalyzerError("Failed to load export_taskinfo.")
+
+        tasklist = LoadTasklist(options.section, export_taskinfo, symbols)
+
+        analyzer = StackAnalyzer(options, symbols, rodata, tasklist, annotation)
+        analyzer.Analyze()
+    except StackAnalyzerError as e:
+        print("Error: {}".format(e))
+
+
+if __name__ == "__main__":
+    main()
diff --git a/extra/stack_analyzer/stack_analyzer_unittest.py b/extra/stack_analyzer/stack_analyzer_unittest.py
index c36fa9da45..23a8fb93ea 100755
--- a/extra/stack_analyzer/stack_analyzer_unittest.py
+++ b/extra/stack_analyzer/stack_analyzer_unittest.py
@@ -1,830 +1,993 @@
 #!/usr/bin/env python3
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
 
 """Tests for Stack Analyzer classes and functions."""
 
 from __future__ import print_function
 
-import mock
 import os
 import subprocess
 import unittest
 
+import mock  # pylint:disable=import-error
 import stack_analyzer as sa
 
 
 class ObjectTest(unittest.TestCase):
-  """Tests for classes of basic objects."""
-
-  def testTask(self):
-    task_a = sa.Task('a', 'a_task', 1234)
-    task_b = sa.Task('b', 'b_task', 5678, 0x1000)
-    self.assertEqual(task_a, task_a)
-    self.assertNotEqual(task_a, task_b)
-    self.assertNotEqual(task_a, None)
-
-  def testSymbol(self):
-    symbol_a = sa.Symbol(0x1234, 'F', 32, 'a')
-    symbol_b = sa.Symbol(0x234, 'O', 42, 'b')
-    self.assertEqual(symbol_a, symbol_a)
-    self.assertNotEqual(symbol_a, symbol_b)
-    self.assertNotEqual(symbol_a, None)
-
-  def testCallsite(self):
-    callsite_a = sa.Callsite(0x1002, 0x3000, False)
-    callsite_b = sa.Callsite(0x1002, 0x3000, True)
-    self.assertEqual(callsite_a, callsite_a)
-    self.assertNotEqual(callsite_a, callsite_b)
-    self.assertNotEqual(callsite_a, None)
-
-  def testFunction(self):
-    func_a = sa.Function(0x100, 'a', 0, [])
-    func_b = sa.Function(0x200, 'b', 0, [])
-    self.assertEqual(func_a, func_a)
-    self.assertNotEqual(func_a, func_b)
-    self.assertNotEqual(func_a, None)
+    """Tests for classes of basic objects."""
+
+    def testTask(self):
+        task_a = sa.Task("a", "a_task", 1234)
+        task_b = sa.Task("b", "b_task", 5678, 0x1000)
+        self.assertEqual(task_a, task_a)
+        self.assertNotEqual(task_a, task_b)
+        self.assertNotEqual(task_a, None)
+
+    def testSymbol(self):
+        symbol_a = sa.Symbol(0x1234, "F", 32, "a")
+        symbol_b = sa.Symbol(0x234, "O", 42, "b")
+        self.assertEqual(symbol_a, symbol_a)
+        self.assertNotEqual(symbol_a, symbol_b)
+        self.assertNotEqual(symbol_a, None)
+
+    def testCallsite(self):
+        callsite_a = sa.Callsite(0x1002, 0x3000, False)
+        callsite_b = sa.Callsite(0x1002, 0x3000, True)
+        self.assertEqual(callsite_a, callsite_a)
+        self.assertNotEqual(callsite_a, callsite_b)
+        self.assertNotEqual(callsite_a, None)
+
+    def testFunction(self):
+        func_a = sa.Function(0x100, "a", 0, [])
+        func_b = sa.Function(0x200, "b", 0, [])
+        self.assertEqual(func_a, func_a)
+        self.assertNotEqual(func_a, func_b)
+        self.assertNotEqual(func_a, None)
 
 
 class ArmAnalyzerTest(unittest.TestCase):
-  """Tests for class ArmAnalyzer."""
-
-  def AppendConditionCode(self, opcodes):
-    rets = []
-    for opcode in opcodes:
-      rets.extend(opcode + cc for cc in sa.ArmAnalyzer.CONDITION_CODES)
-
-    return rets
-
-  def testInstructionMatching(self):
-    jump_list = self.AppendConditionCode(['b', 'bx'])
-    jump_list += (list(opcode + '.n' for opcode in jump_list) +
-                  list(opcode + '.w' for opcode in jump_list))
-    for opcode in jump_list:
-      self.assertIsNotNone(sa.ArmAnalyzer.JUMP_OPCODE_RE.match(opcode))
-
-    self.assertIsNone(sa.ArmAnalyzer.JUMP_OPCODE_RE.match('bl'))
-    self.assertIsNone(sa.ArmAnalyzer.JUMP_OPCODE_RE.match('blx'))
-
-    cbz_list = ['cbz', 'cbnz', 'cbz.n', 'cbnz.n', 'cbz.w', 'cbnz.w']
-    for opcode in cbz_list:
-      self.assertIsNotNone(sa.ArmAnalyzer.CBZ_CBNZ_OPCODE_RE.match(opcode))
-
-    self.assertIsNone(sa.ArmAnalyzer.CBZ_CBNZ_OPCODE_RE.match('cbn'))
-
-    call_list = self.AppendConditionCode(['bl', 'blx'])
-    call_list += list(opcode + '.n' for opcode in call_list)
-    for opcode in call_list:
-      self.assertIsNotNone(sa.ArmAnalyzer.CALL_OPCODE_RE.match(opcode))
-
-    self.assertIsNone(sa.ArmAnalyzer.CALL_OPCODE_RE.match('ble'))
-
-    result = sa.ArmAnalyzer.CALL_OPERAND_RE.match('53f90 <get_time+0x18>')
-    self.assertIsNotNone(result)
-    self.assertEqual(result.group(1), '53f90')
-    self.assertEqual(result.group(2), 'get_time+0x18')
-
-    result = sa.ArmAnalyzer.CBZ_CBNZ_OPERAND_RE.match('r6, 53f90 <get+0x0>')
-    self.assertIsNotNone(result)
-    self.assertEqual(result.group(1), '53f90')
-    self.assertEqual(result.group(2), 'get+0x0')
-
-    self.assertIsNotNone(sa.ArmAnalyzer.PUSH_OPCODE_RE.match('push'))
-    self.assertIsNone(sa.ArmAnalyzer.PUSH_OPCODE_RE.match('pushal'))
-    self.assertIsNotNone(sa.ArmAnalyzer.STM_OPCODE_RE.match('stmdb'))
-    self.assertIsNone(sa.ArmAnalyzer.STM_OPCODE_RE.match('lstm'))
-    self.assertIsNotNone(sa.ArmAnalyzer.SUB_OPCODE_RE.match('sub'))
-    self.assertIsNotNone(sa.ArmAnalyzer.SUB_OPCODE_RE.match('subs'))
-    self.assertIsNotNone(sa.ArmAnalyzer.SUB_OPCODE_RE.match('subw'))
-    self.assertIsNotNone(sa.ArmAnalyzer.SUB_OPCODE_RE.match('sub.w'))
-    self.assertIsNotNone(sa.ArmAnalyzer.SUB_OPCODE_RE.match('subs.w'))
-
-    result = sa.ArmAnalyzer.SUB_OPERAND_RE.match('sp, sp, #1668   ; 0x684')
-    self.assertIsNotNone(result)
-    self.assertEqual(result.group(1), '1668')
-    result = sa.ArmAnalyzer.SUB_OPERAND_RE.match('sp, #1668')
-    self.assertIsNotNone(result)
-    self.assertEqual(result.group(1), '1668')
-    self.assertIsNone(sa.ArmAnalyzer.SUB_OPERAND_RE.match('sl, #1668'))
-
-  def testAnalyzeFunction(self):
-    analyzer = sa.ArmAnalyzer()
-    symbol = sa.Symbol(0x10, 'F', 0x100, 'foo')
-    instructions = [
-        (0x10, 'push', '{r4, r5, r6, r7, lr}'),
-        (0x12, 'subw', 'sp, sp, #16	; 0x10'),
-        (0x16, 'movs', 'lr, r1'),
-        (0x18, 'beq.n', '26 <foo+0x26>'),
-        (0x1a, 'bl', '30 <foo+0x30>'),
-        (0x1e, 'bl', 'deadbeef <bar>'),
-        (0x22, 'blx', '0 <woo>'),
-        (0x26, 'push', '{r1}'),
-        (0x28, 'stmdb', 'sp!, {r4, r5, r6, r7, r8, r9, lr}'),
-        (0x2c, 'stmdb', 'sp!, {r4}'),
-        (0x30, 'stmdb', 'sp, {r4}'),
-        (0x34, 'bx.n', '10 <foo>'),
-        (0x36, 'bx.n', 'r3'),
-        (0x38, 'ldr', 'pc, [r10]'),
-    ]
-    (size, callsites) = analyzer.AnalyzeFunction(symbol, instructions)
-    self.assertEqual(size, 72)
-    expect_callsites = [sa.Callsite(0x1e, 0xdeadbeef, False),
-                        sa.Callsite(0x22, 0x0, False),
-                        sa.Callsite(0x34, 0x10, True),
-                        sa.Callsite(0x36, None, True),
-                        sa.Callsite(0x38, None, True)]
-    self.assertEqual(callsites, expect_callsites)
+    """Tests for class ArmAnalyzer."""
+
+    def AppendConditionCode(self, opcodes):
+        rets = []
+        for opcode in opcodes:
+            rets.extend(opcode + cc for cc in sa.ArmAnalyzer.CONDITION_CODES)
+
+        return rets
+
+    def testInstructionMatching(self):
+        jump_list = self.AppendConditionCode(["b", "bx"])
+        jump_list += list(opcode + ".n" for opcode in jump_list) + list(
+            opcode + ".w" for opcode in jump_list
+        )
+        for opcode in jump_list:
+            self.assertIsNotNone(sa.ArmAnalyzer.JUMP_OPCODE_RE.match(opcode))
+
+        self.assertIsNone(sa.ArmAnalyzer.JUMP_OPCODE_RE.match("bl"))
+        self.assertIsNone(sa.ArmAnalyzer.JUMP_OPCODE_RE.match("blx"))
+
+        cbz_list = ["cbz", "cbnz", "cbz.n", "cbnz.n", "cbz.w", "cbnz.w"]
+        for opcode in cbz_list:
+            self.assertIsNotNone(
+                sa.ArmAnalyzer.CBZ_CBNZ_OPCODE_RE.match(opcode)
+            )
+
+        self.assertIsNone(sa.ArmAnalyzer.CBZ_CBNZ_OPCODE_RE.match("cbn"))
+
+        call_list = self.AppendConditionCode(["bl", "blx"])
+        call_list += list(opcode + ".n" for opcode in call_list)
+        for opcode in call_list:
+            self.assertIsNotNone(sa.ArmAnalyzer.CALL_OPCODE_RE.match(opcode))
+
+        self.assertIsNone(sa.ArmAnalyzer.CALL_OPCODE_RE.match("ble"))
+
+        result = sa.ArmAnalyzer.CALL_OPERAND_RE.match("53f90 <get_time+0x18>")
+        self.assertIsNotNone(result)
+        self.assertEqual(result.group(1), "53f90")
+        self.assertEqual(result.group(2), "get_time+0x18")
+
+        result = sa.ArmAnalyzer.CBZ_CBNZ_OPERAND_RE.match("r6, 53f90 <get+0x0>")
+        self.assertIsNotNone(result)
+        self.assertEqual(result.group(1), "53f90")
+        self.assertEqual(result.group(2), "get+0x0")
+
+        self.assertIsNotNone(sa.ArmAnalyzer.PUSH_OPCODE_RE.match("push"))
+        self.assertIsNone(sa.ArmAnalyzer.PUSH_OPCODE_RE.match("pushal"))
+        self.assertIsNotNone(sa.ArmAnalyzer.STM_OPCODE_RE.match("stmdb"))
+        self.assertIsNone(sa.ArmAnalyzer.STM_OPCODE_RE.match("lstm"))
+        self.assertIsNotNone(sa.ArmAnalyzer.SUB_OPCODE_RE.match("sub"))
+        self.assertIsNotNone(sa.ArmAnalyzer.SUB_OPCODE_RE.match("subs"))
+        self.assertIsNotNone(sa.ArmAnalyzer.SUB_OPCODE_RE.match("subw"))
+        self.assertIsNotNone(sa.ArmAnalyzer.SUB_OPCODE_RE.match("sub.w"))
+        self.assertIsNotNone(sa.ArmAnalyzer.SUB_OPCODE_RE.match("subs.w"))
+
+        result = sa.ArmAnalyzer.SUB_OPERAND_RE.match("sp, sp, #1668   ; 0x684")
+        self.assertIsNotNone(result)
+        self.assertEqual(result.group(1), "1668")
+        result = sa.ArmAnalyzer.SUB_OPERAND_RE.match("sp, #1668")
+        self.assertIsNotNone(result)
+        self.assertEqual(result.group(1), "1668")
+        self.assertIsNone(sa.ArmAnalyzer.SUB_OPERAND_RE.match("sl, #1668"))
+
+    def testAnalyzeFunction(self):
+        analyzer = sa.ArmAnalyzer()
+        symbol = sa.Symbol(0x10, "F", 0x100, "foo")
+        instructions = [
+            (0x10, "push", "{r4, r5, r6, r7, lr}"),
+            (0x12, "subw", "sp, sp, #16	; 0x10"),
+            (0x16, "movs", "lr, r1"),
+            (0x18, "beq.n", "26 <foo+0x26>"),
+            (0x1A, "bl", "30 <foo+0x30>"),
+            (0x1E, "bl", "deadbeef <bar>"),
+            (0x22, "blx", "0 <woo>"),
+            (0x26, "push", "{r1}"),
+            (0x28, "stmdb", "sp!, {r4, r5, r6, r7, r8, r9, lr}"),
+            (0x2C, "stmdb", "sp!, {r4}"),
+            (0x30, "stmdb", "sp, {r4}"),
+            (0x34, "bx.n", "10 <foo>"),
+            (0x36, "bx.n", "r3"),
+            (0x38, "ldr", "pc, [r10]"),
+        ]
+        (size, callsites) = analyzer.AnalyzeFunction(symbol, instructions)
+        self.assertEqual(size, 72)
+        expect_callsites = [
+            sa.Callsite(0x1E, 0xDEADBEEF, False),
+            sa.Callsite(0x22, 0x0, False),
+            sa.Callsite(0x34, 0x10, True),
+            sa.Callsite(0x36, None, True),
+            sa.Callsite(0x38, None, True),
+        ]
+        self.assertEqual(callsites, expect_callsites)
 
 
 class StackAnalyzerTest(unittest.TestCase):
-  """Tests for class StackAnalyzer."""
-
-  def setUp(self):
-    symbols = [sa.Symbol(0x1000, 'F', 0x15C, 'hook_task'),
-               sa.Symbol(0x2000, 'F', 0x51C, 'console_task'),
-               sa.Symbol(0x3200, 'O', 0x124, '__just_data'),
-               sa.Symbol(0x4000, 'F', 0x11C, 'touchpad_calc'),
-               sa.Symbol(0x5000, 'F', 0x12C, 'touchpad_calc.constprop.42'),
-               sa.Symbol(0x12000, 'F', 0x13C, 'trackpad_range'),
-               sa.Symbol(0x13000, 'F', 0x200, 'inlined_mul'),
-               sa.Symbol(0x13100, 'F', 0x200, 'inlined_mul'),
-               sa.Symbol(0x13100, 'F', 0x200, 'inlined_mul_alias'),
-               sa.Symbol(0x20000, 'O', 0x0, '__array'),
-               sa.Symbol(0x20010, 'O', 0x0, '__array_end'),
-    ]
-    tasklist = [sa.Task('HOOKS', 'hook_task', 2048, 0x1000),
-                sa.Task('CONSOLE', 'console_task', 460, 0x2000)]
-    # Array at 0x20000 that contains pointers to hook_task and console_task,
-    # with stride=8, offset=4
-    rodata = (0x20000, [ 0xDEAD1000, 0x00001000, 0xDEAD2000, 0x00002000 ])
-    options = mock.MagicMock(elf_path='./ec.RW.elf',
-                             export_taskinfo='fake',
-                             section='RW',
-                             objdump='objdump',
-                             addr2line='addr2line',
-                             annotation=None)
-    self.analyzer = sa.StackAnalyzer(options, symbols, rodata, tasklist, {})
-
-  def testParseSymbolText(self):
-    symbol_text = (
-        '0 g     F .text  e8 Foo\n'
-        '0000dead  w    F .text  000000e8 .hidden Bar\n'
-        'deadbeef l     O .bss   00000004 .hidden Woooo\n'
-        'deadbee g     O .rodata        00000008 __Hooo_ooo\n'
-        'deadbee g       .rodata        00000000 __foo_doo_coo_end\n'
-    )
-    symbols = sa.ParseSymbolText(symbol_text)
-    expect_symbols = [sa.Symbol(0x0, 'F', 0xe8, 'Foo'),
-                      sa.Symbol(0xdead, 'F', 0xe8, 'Bar'),
-                      sa.Symbol(0xdeadbeef, 'O', 0x4, 'Woooo'),
-                      sa.Symbol(0xdeadbee, 'O', 0x8, '__Hooo_ooo'),
-                      sa.Symbol(0xdeadbee, 'O', 0x0, '__foo_doo_coo_end')]
-    self.assertEqual(symbols, expect_symbols)
-
-  def testParseRoData(self):
-    rodata_text = (
-        '\n'
-        'Contents of section .rodata:\n'
-        ' 20000 dead1000 00100000 dead2000 00200000  He..f.He..s.\n'
-    )
-    rodata = sa.ParseRoDataText(rodata_text)
-    expect_rodata = (0x20000,
-                     [ 0x0010adde, 0x00001000, 0x0020adde, 0x00002000 ])
-    self.assertEqual(rodata, expect_rodata)
-
-  def testLoadTasklist(self):
-    def tasklist_to_taskinfos(pointer, tasklist):
-      taskinfos = []
-      for task in tasklist:
-        taskinfos.append(sa.TaskInfo(name=task.name.encode('utf-8'),
-                                     routine=task.routine_name.encode('utf-8'),
-                                     stack_size=task.stack_max_size))
-
-      TaskInfoArray = sa.TaskInfo * len(taskinfos)
-      pointer.contents.contents = TaskInfoArray(*taskinfos)
-      return len(taskinfos)
-
-    def ro_taskinfos(pointer):
-      return tasklist_to_taskinfos(pointer, expect_ro_tasklist)
-
-    def rw_taskinfos(pointer):
-      return tasklist_to_taskinfos(pointer, expect_rw_tasklist)
-
-    expect_ro_tasklist = [
-        sa.Task('HOOKS', 'hook_task', 2048, 0x1000),
-    ]
-
-    expect_rw_tasklist = [
-        sa.Task('HOOKS', 'hook_task', 2048, 0x1000),
-        sa.Task('WOOKS', 'hook_task', 4096, 0x1000),
-        sa.Task('CONSOLE', 'console_task', 460, 0x2000),
-    ]
-
-    export_taskinfo = mock.MagicMock(
-        get_ro_taskinfos=mock.MagicMock(side_effect=ro_taskinfos),
-        get_rw_taskinfos=mock.MagicMock(side_effect=rw_taskinfos))
-
-    tasklist = sa.LoadTasklist('RO', export_taskinfo, self.analyzer.symbols)
-    self.assertEqual(tasklist, expect_ro_tasklist)
-    tasklist = sa.LoadTasklist('RW', export_taskinfo, self.analyzer.symbols)
-    self.assertEqual(tasklist, expect_rw_tasklist)
-
-  def testResolveAnnotation(self):
-    self.analyzer.annotation = {}
-    (add_rules, remove_rules, invalid_sigtxts) = self.analyzer.LoadAnnotation()
-    self.assertEqual(add_rules, {})
-    self.assertEqual(remove_rules, [])
-    self.assertEqual(invalid_sigtxts, set())
-
-    self.analyzer.annotation = {'add': None, 'remove': None}
-    (add_rules, remove_rules, invalid_sigtxts) = self.analyzer.LoadAnnotation()
-    self.assertEqual(add_rules, {})
-    self.assertEqual(remove_rules, [])
-    self.assertEqual(invalid_sigtxts, set())
-
-    self.analyzer.annotation = {
-        'add': None,
-        'remove': [
-            [['a', 'b'], ['0', '[', '2'], 'x'],
-            [['a', 'b[x:3]'], ['0', '1', '2'], 'x'],
-        ],
-    }
-    (add_rules, remove_rules, invalid_sigtxts) = self.analyzer.LoadAnnotation()
-    self.assertEqual(add_rules, {})
-    self.assertEqual(list.sort(remove_rules), list.sort([
-        [('a', None, None), ('1', None, None), ('x', None, None)],
-        [('a', None, None), ('0', None, None), ('x', None, None)],
-        [('a', None, None), ('2', None, None), ('x', None, None)],
-        [('b', os.path.abspath('x'), 3), ('1', None, None), ('x', None, None)],
-        [('b', os.path.abspath('x'), 3), ('0', None, None), ('x', None, None)],
-        [('b', os.path.abspath('x'), 3), ('2', None, None), ('x', None, None)],
-    ]))
-    self.assertEqual(invalid_sigtxts, {'['})
-
-    self.analyzer.annotation = {
-        'add': {
-          'touchpad_calc': [ dict(name='__array', stride=8, offset=4) ],
+    """Tests for class StackAnalyzer."""
+
+    def setUp(self):
+        symbols = [
+            sa.Symbol(0x1000, "F", 0x15C, "hook_task"),
+            sa.Symbol(0x2000, "F", 0x51C, "console_task"),
+            sa.Symbol(0x3200, "O", 0x124, "__just_data"),
+            sa.Symbol(0x4000, "F", 0x11C, "touchpad_calc"),
+            sa.Symbol(0x5000, "F", 0x12C, "touchpad_calc.constprop.42"),
+            sa.Symbol(0x12000, "F", 0x13C, "trackpad_range"),
+            sa.Symbol(0x13000, "F", 0x200, "inlined_mul"),
+            sa.Symbol(0x13100, "F", 0x200, "inlined_mul"),
+            sa.Symbol(0x13100, "F", 0x200, "inlined_mul_alias"),
+            sa.Symbol(0x20000, "O", 0x0, "__array"),
+            sa.Symbol(0x20010, "O", 0x0, "__array_end"),
+        ]
+        tasklist = [
+            sa.Task("HOOKS", "hook_task", 2048, 0x1000),
+            sa.Task("CONSOLE", "console_task", 460, 0x2000),
+        ]
+        # Array at 0x20000 that contains pointers to hook_task and console_task,
+        # with stride=8, offset=4
+        rodata = (0x20000, [0xDEAD1000, 0x00001000, 0xDEAD2000, 0x00002000])
+        options = mock.MagicMock(
+            elf_path="./ec.RW.elf",
+            export_taskinfo="fake",
+            section="RW",
+            objdump="objdump",
+            addr2line="addr2line",
+            annotation=None,
+        )
+        self.analyzer = sa.StackAnalyzer(options, symbols, rodata, tasklist, {})
+
+    def testParseSymbolText(self):
+        symbol_text = (
+            "0 g     F .text  e8 Foo\n"
+            "0000dead  w    F .text  000000e8 .hidden Bar\n"
+            "deadbeef l     O .bss   00000004 .hidden Woooo\n"
+            "deadbee g     O .rodata        00000008 __Hooo_ooo\n"
+            "deadbee g       .rodata        00000000 __foo_doo_coo_end\n"
+        )
+        symbols = sa.ParseSymbolText(symbol_text)
+        expect_symbols = [
+            sa.Symbol(0x0, "F", 0xE8, "Foo"),
+            sa.Symbol(0xDEAD, "F", 0xE8, "Bar"),
+            sa.Symbol(0xDEADBEEF, "O", 0x4, "Woooo"),
+            sa.Symbol(0xDEADBEE, "O", 0x8, "__Hooo_ooo"),
+            sa.Symbol(0xDEADBEE, "O", 0x0, "__foo_doo_coo_end"),
+        ]
+        self.assertEqual(symbols, expect_symbols)
+
+    def testParseRoData(self):
+        rodata_text = (
+            "\n"
+            "Contents of section .rodata:\n"
+            " 20000 dead1000 00100000 dead2000 00200000  He..f.He..s.\n"
+        )
+        rodata = sa.ParseRoDataText(rodata_text)
+        expect_rodata = (
+            0x20000,
+            [0x0010ADDE, 0x00001000, 0x0020ADDE, 0x00002000],
+        )
+        self.assertEqual(rodata, expect_rodata)
+
+    def testLoadTasklist(self):
+        def tasklist_to_taskinfos(pointer, tasklist):
+            taskinfos = []
+            for task in tasklist:
+                taskinfos.append(
+                    sa.TaskInfo(
+                        name=task.name.encode("utf-8"),
+                        routine=task.routine_name.encode("utf-8"),
+                        stack_size=task.stack_max_size,
+                    )
+                )
+
+            TaskInfoArray = sa.TaskInfo * len(taskinfos)
+            pointer.contents.contents = TaskInfoArray(*taskinfos)
+            return len(taskinfos)
+
+        def ro_taskinfos(pointer):
+            return tasklist_to_taskinfos(pointer, expect_ro_tasklist)
+
+        def rw_taskinfos(pointer):
+            return tasklist_to_taskinfos(pointer, expect_rw_tasklist)
+
+        expect_ro_tasklist = [
+            sa.Task("HOOKS", "hook_task", 2048, 0x1000),
+        ]
+
+        expect_rw_tasklist = [
+            sa.Task("HOOKS", "hook_task", 2048, 0x1000),
+            sa.Task("WOOKS", "hook_task", 4096, 0x1000),
+            sa.Task("CONSOLE", "console_task", 460, 0x2000),
+        ]
+
+        export_taskinfo = mock.MagicMock(
+            get_ro_taskinfos=mock.MagicMock(side_effect=ro_taskinfos),
+            get_rw_taskinfos=mock.MagicMock(side_effect=rw_taskinfos),
+        )
+
+        tasklist = sa.LoadTasklist("RO", export_taskinfo, self.analyzer.symbols)
+        self.assertEqual(tasklist, expect_ro_tasklist)
+        tasklist = sa.LoadTasklist("RW", export_taskinfo, self.analyzer.symbols)
+        self.assertEqual(tasklist, expect_rw_tasklist)
+
+    def testResolveAnnotation(self):
+        self.analyzer.annotation = {}
+        (
+            add_rules,
+            remove_rules,
+            invalid_sigtxts,
+        ) = self.analyzer.LoadAnnotation()
+        self.assertEqual(add_rules, {})
+        self.assertEqual(remove_rules, [])
+        self.assertEqual(invalid_sigtxts, set())
+
+        self.analyzer.annotation = {"add": None, "remove": None}
+        (
+            add_rules,
+            remove_rules,
+            invalid_sigtxts,
+        ) = self.analyzer.LoadAnnotation()
+        self.assertEqual(add_rules, {})
+        self.assertEqual(remove_rules, [])
+        self.assertEqual(invalid_sigtxts, set())
+
+        self.analyzer.annotation = {
+            "add": None,
+            "remove": [
+                [["a", "b"], ["0", "[", "2"], "x"],
+                [["a", "b[x:3]"], ["0", "1", "2"], "x"],
+            ],
         }
-    }
-    (add_rules, remove_rules, invalid_sigtxts) = self.analyzer.LoadAnnotation()
-    self.assertEqual(add_rules, {
-      ('touchpad_calc', None, None):
-        set([('console_task', None, None), ('hook_task', None, None)])})
-
-    funcs = {
-        0x1000: sa.Function(0x1000, 'hook_task', 0, []),
-        0x2000: sa.Function(0x2000, 'console_task', 0, []),
-        0x4000: sa.Function(0x4000, 'touchpad_calc', 0, []),
-        0x5000: sa.Function(0x5000, 'touchpad_calc.constprop.42', 0, []),
-        0x13000: sa.Function(0x13000, 'inlined_mul', 0, []),
-        0x13100: sa.Function(0x13100, 'inlined_mul', 0, []),
-    }
-    funcs[0x1000].callsites = [
-        sa.Callsite(0x1002, None, False, None)]
-    # Set address_to_line_cache to fake the results of addr2line.
-    self.analyzer.address_to_line_cache = {
-        (0x1000, False): [('hook_task', os.path.abspath('a.c'), 10)],
-        (0x1002, False): [('toot_calc', os.path.abspath('t.c'), 1234)],
-        (0x2000, False): [('console_task', os.path.abspath('b.c'), 20)],
-        (0x4000, False): [('toudhpad_calc', os.path.abspath('a.c'), 20)],
-        (0x5000, False): [
-            ('touchpad_calc.constprop.42', os.path.abspath('b.c'), 40)],
-        (0x12000, False): [('trackpad_range', os.path.abspath('t.c'), 10)],
-        (0x13000, False): [('inlined_mul', os.path.abspath('x.c'), 12)],
-        (0x13100, False): [('inlined_mul', os.path.abspath('x.c'), 12)],
-    }
-    self.analyzer.annotation = {
-        'add': {
-            'hook_task.lto.573': ['touchpad_calc.lto.2501[a.c]'],
-            'console_task': ['touchpad_calc[b.c]', 'inlined_mul_alias'],
-            'hook_task[q.c]': ['hook_task'],
-            'inlined_mul[x.c]': ['inlined_mul'],
-            'toot_calc[t.c:1234]': ['hook_task'],
-        },
-        'remove': [
-            ['touchpad?calc['],
-            'touchpad_calc',
-            ['touchpad_calc[a.c]'],
-            ['task_unk[a.c]'],
-            ['touchpad_calc[x/a.c]'],
-            ['trackpad_range'],
-            ['inlined_mul'],
-            ['inlined_mul', 'console_task', 'touchpad_calc[a.c]'],
-            ['inlined_mul', 'inlined_mul_alias', 'console_task'],
-            ['inlined_mul', 'inlined_mul_alias', 'console_task'],
-        ],
-    }
-    (add_rules, remove_rules, invalid_sigtxts) = self.analyzer.LoadAnnotation()
-    self.assertEqual(invalid_sigtxts, {'touchpad?calc['})
-
-    signature_set = set()
-    for src_sig, dst_sigs in add_rules.items():
-      signature_set.add(src_sig)
-      signature_set.update(dst_sigs)
-
-    for remove_sigs in remove_rules:
-      signature_set.update(remove_sigs)
-
-    (signature_map, failed_sigs) = self.analyzer.MapAnnotation(funcs,
-                                                               signature_set)
-    result = self.analyzer.ResolveAnnotation(funcs)
-    (add_set, remove_list, eliminated_addrs, failed_sigs) = result
-
-    expect_signature_map = {
-        ('hook_task', None, None): {funcs[0x1000]},
-        ('touchpad_calc', os.path.abspath('a.c'), None): {funcs[0x4000]},
-        ('touchpad_calc', os.path.abspath('b.c'), None): {funcs[0x5000]},
-        ('console_task', None, None): {funcs[0x2000]},
-        ('inlined_mul_alias', None, None): {funcs[0x13100]},
-        ('inlined_mul', os.path.abspath('x.c'), None): {funcs[0x13000],
-                                                        funcs[0x13100]},
-        ('inlined_mul', None, None): {funcs[0x13000], funcs[0x13100]},
-    }
-    self.assertEqual(len(signature_map), len(expect_signature_map))
-    for sig, funclist in signature_map.items():
-      self.assertEqual(set(funclist), expect_signature_map[sig])
-
-    self.assertEqual(add_set, {
-        (funcs[0x1000], funcs[0x4000]),
-        (funcs[0x1000], funcs[0x1000]),
-        (funcs[0x2000], funcs[0x5000]),
-        (funcs[0x2000], funcs[0x13100]),
-        (funcs[0x13000], funcs[0x13000]),
-        (funcs[0x13000], funcs[0x13100]),
-        (funcs[0x13100], funcs[0x13000]),
-        (funcs[0x13100], funcs[0x13100]),
-    })
-    expect_remove_list = [
-        [funcs[0x4000]],
-        [funcs[0x13000]],
-        [funcs[0x13100]],
-        [funcs[0x13000], funcs[0x2000], funcs[0x4000]],
-        [funcs[0x13100], funcs[0x2000], funcs[0x4000]],
-        [funcs[0x13000], funcs[0x13100], funcs[0x2000]],
-        [funcs[0x13100], funcs[0x13100], funcs[0x2000]],
-    ]
-    self.assertEqual(len(remove_list), len(expect_remove_list))
-    for remove_path in remove_list:
-      self.assertTrue(remove_path in expect_remove_list)
-
-    self.assertEqual(eliminated_addrs, {0x1002})
-    self.assertEqual(failed_sigs, {
-        ('touchpad?calc[', sa.StackAnalyzer.ANNOTATION_ERROR_INVALID),
-        ('touchpad_calc', sa.StackAnalyzer.ANNOTATION_ERROR_AMBIGUOUS),
-        ('hook_task[q.c]', sa.StackAnalyzer.ANNOTATION_ERROR_NOTFOUND),
-        ('task_unk[a.c]', sa.StackAnalyzer.ANNOTATION_ERROR_NOTFOUND),
-        ('touchpad_calc[x/a.c]', sa.StackAnalyzer.ANNOTATION_ERROR_NOTFOUND),
-        ('trackpad_range', sa.StackAnalyzer.ANNOTATION_ERROR_NOTFOUND),
-    })
-
-  def testPreprocessAnnotation(self):
-    funcs = {
-        0x1000: sa.Function(0x1000, 'hook_task', 0, []),
-        0x2000: sa.Function(0x2000, 'console_task', 0, []),
-        0x4000: sa.Function(0x4000, 'touchpad_calc', 0, []),
-    }
-    funcs[0x1000].callsites = [
-        sa.Callsite(0x1002, 0x1000, False, funcs[0x1000])]
-    funcs[0x2000].callsites = [
-        sa.Callsite(0x2002, 0x1000, False, funcs[0x1000]),
-        sa.Callsite(0x2006, None, True, None),
-    ]
-    add_set = {
-        (funcs[0x2000], funcs[0x2000]),
-        (funcs[0x2000], funcs[0x4000]),
-        (funcs[0x4000], funcs[0x1000]),
-        (funcs[0x4000], funcs[0x2000]),
-    }
-    remove_list = [
-        [funcs[0x1000]],
-        [funcs[0x2000], funcs[0x2000]],
-        [funcs[0x4000], funcs[0x1000]],
-        [funcs[0x2000], funcs[0x4000], funcs[0x2000]],
-        [funcs[0x4000], funcs[0x1000], funcs[0x4000]],
-    ]
-    eliminated_addrs = {0x2006}
-
-    remaining_remove_list = self.analyzer.PreprocessAnnotation(funcs,
-                                                               add_set,
-                                                               remove_list,
-                                                               eliminated_addrs)
-
-    expect_funcs = {
-        0x1000: sa.Function(0x1000, 'hook_task', 0, []),
-        0x2000: sa.Function(0x2000, 'console_task', 0, []),
-        0x4000: sa.Function(0x4000, 'touchpad_calc', 0, []),
-    }
-    expect_funcs[0x2000].callsites = [
-        sa.Callsite(None, 0x4000, False, expect_funcs[0x4000])]
-    expect_funcs[0x4000].callsites = [
-        sa.Callsite(None, 0x2000, False, expect_funcs[0x2000])]
-    self.assertEqual(funcs, expect_funcs)
-    self.assertEqual(remaining_remove_list, [
-        [funcs[0x2000], funcs[0x4000], funcs[0x2000]],
-    ])
-
-  def testAndesAnalyzeDisassembly(self):
-    disasm_text = (
-        '\n'
-        'build/{BOARD}/RW/ec.RW.elf:     file format elf32-nds32le'
-        '\n'
-        'Disassembly of section .text:\n'
-        '\n'
-        '00000900 <wook_task>:\n'
-        '   ...\n'
-        '00001000 <hook_task>:\n'
-        '   1000:   fc 42\tpush25 $r10, #16    ! {$r6~$r10, $fp, $gp, $lp}\n'
-        '   1004:   47 70\t\tmovi55 $r0, #1\n'
-        '   1006:   b1 13\tbnezs8 100929de <flash_command_write>\n'
-        '   1008:   00 01 5c fc\tbne    $r6, $r0, 2af6a\n'
-        '00002000 <console_task>:\n'
-        '   2000:   fc 00\t\tpush25 $r6, #0    ! {$r6, $fp, $gp, $lp} \n'
-        '   2002:   f0 0e fc c5\tjal   1000 <hook_task>\n'
-        '   2006:   f0 0e bd 3b\tj  53968 <get_program_memory_addr>\n'
-        '   200a:   de ad be ef\tswi.gp $r0, [ + #-11036]\n'
-        '00004000 <touchpad_calc>:\n'
-        '   4000:   47 70\t\tmovi55 $r0, #1\n'
-        '00010000 <look_task>:'
-    )
-    function_map = self.analyzer.AnalyzeDisassembly(disasm_text)
-    func_hook_task = sa.Function(0x1000, 'hook_task', 48, [
-        sa.Callsite(0x1006, 0x100929de, True, None)])
-    expect_funcmap = {
-        0x1000: func_hook_task,
-        0x2000: sa.Function(0x2000, 'console_task', 16,
-                            [sa.Callsite(0x2002, 0x1000, False, func_hook_task),
-                             sa.Callsite(0x2006, 0x53968, True, None)]),
-        0x4000: sa.Function(0x4000, 'touchpad_calc', 0, []),
-    }
-    self.assertEqual(function_map, expect_funcmap)
-
-  def testArmAnalyzeDisassembly(self):
-    disasm_text = (
-        '\n'
-        'build/{BOARD}/RW/ec.RW.elf:     file format elf32-littlearm'
-        '\n'
-        'Disassembly of section .text:\n'
-        '\n'
-        '00000900 <wook_task>:\n'
-        '	...\n'
-        '00001000 <hook_task>:\n'
-        '   1000:	dead beef\tfake\n'
-        '   1004:	4770\t\tbx	lr\n'
-        '   1006:	b113\tcbz	r3, 100929de <flash_command_write>\n'
-        '   1008:	00015cfc\t.word	0x00015cfc\n'
-        '00002000 <console_task>:\n'
-        '   2000:	b508\t\tpush	{r3, lr} ; malformed comments,; r0, r1 \n'
-        '   2002:	f00e fcc5\tbl	1000 <hook_task>\n'
-        '   2006:	f00e bd3b\tb.w	53968 <get_program_memory_addr>\n'
-        '   200a:	dead beef\tfake\n'
-        '00004000 <touchpad_calc>:\n'
-        '   4000:	4770\t\tbx	lr\n'
-        '00010000 <look_task>:'
-    )
-    function_map = self.analyzer.AnalyzeDisassembly(disasm_text)
-    func_hook_task = sa.Function(0x1000, 'hook_task', 0, [
-        sa.Callsite(0x1006, 0x100929de, True, None)])
-    expect_funcmap = {
-        0x1000: func_hook_task,
-        0x2000: sa.Function(0x2000, 'console_task', 8,
-                            [sa.Callsite(0x2002, 0x1000, False, func_hook_task),
-                             sa.Callsite(0x2006, 0x53968, True, None)]),
-        0x4000: sa.Function(0x4000, 'touchpad_calc', 0, []),
-    }
-    self.assertEqual(function_map, expect_funcmap)
-
-  def testAnalyzeCallGraph(self):
-    funcs = {
-        0x1000: sa.Function(0x1000, 'hook_task', 0, []),
-        0x2000: sa.Function(0x2000, 'console_task', 8, []),
-        0x3000: sa.Function(0x3000, 'task_a', 12, []),
-        0x4000: sa.Function(0x4000, 'task_b', 96, []),
-        0x5000: sa.Function(0x5000, 'task_c', 32, []),
-        0x6000: sa.Function(0x6000, 'task_d', 100, []),
-        0x7000: sa.Function(0x7000, 'task_e', 24, []),
-        0x8000: sa.Function(0x8000, 'task_f', 20, []),
-        0x9000: sa.Function(0x9000, 'task_g', 20, []),
-        0x10000: sa.Function(0x10000, 'task_x', 16, []),
-    }
-    funcs[0x1000].callsites = [
-        sa.Callsite(0x1002, 0x3000, False, funcs[0x3000]),
-        sa.Callsite(0x1006, 0x4000, False, funcs[0x4000])]
-    funcs[0x2000].callsites = [
-        sa.Callsite(0x2002, 0x5000, False, funcs[0x5000]),
-        sa.Callsite(0x2006, 0x2000, False, funcs[0x2000]),
-        sa.Callsite(0x200a, 0x10000, False, funcs[0x10000])]
-    funcs[0x3000].callsites = [
-        sa.Callsite(0x3002, 0x4000, False, funcs[0x4000]),
-        sa.Callsite(0x3006, 0x1000, False, funcs[0x1000])]
-    funcs[0x4000].callsites = [
-        sa.Callsite(0x4002, 0x6000, True, funcs[0x6000]),
-        sa.Callsite(0x4006, 0x7000, False, funcs[0x7000]),
-        sa.Callsite(0x400a, 0x8000, False, funcs[0x8000])]
-    funcs[0x5000].callsites = [
-        sa.Callsite(0x5002, 0x4000, False, funcs[0x4000])]
-    funcs[0x7000].callsites = [
-        sa.Callsite(0x7002, 0x7000, False, funcs[0x7000])]
-    funcs[0x8000].callsites = [
-        sa.Callsite(0x8002, 0x9000, False, funcs[0x9000])]
-    funcs[0x9000].callsites = [
-        sa.Callsite(0x9002, 0x4000, False, funcs[0x4000])]
-    funcs[0x10000].callsites = [
-        sa.Callsite(0x10002, 0x2000, False, funcs[0x2000])]
-
-    cycles = self.analyzer.AnalyzeCallGraph(funcs, [
-        [funcs[0x2000]] * 2,
-        [funcs[0x10000], funcs[0x2000]] * 3,
-        [funcs[0x1000], funcs[0x3000], funcs[0x1000]]
-    ])
-
-    expect_func_stack = {
-        0x1000: (268, [funcs[0x1000],
-                       funcs[0x3000],
-                       funcs[0x4000],
-                       funcs[0x8000],
-                       funcs[0x9000],
-                       funcs[0x4000],
-                       funcs[0x7000]]),
-        0x2000: (208, [funcs[0x2000],
-                       funcs[0x10000],
-                       funcs[0x2000],
-                       funcs[0x10000],
-                       funcs[0x2000],
-                       funcs[0x5000],
-                       funcs[0x4000],
-                       funcs[0x7000]]),
-        0x3000: (280, [funcs[0x3000],
-                       funcs[0x1000],
-                       funcs[0x3000],
-                       funcs[0x4000],
-                       funcs[0x8000],
-                       funcs[0x9000],
-                       funcs[0x4000],
-                       funcs[0x7000]]),
-        0x4000: (120, [funcs[0x4000], funcs[0x7000]]),
-        0x5000: (152, [funcs[0x5000], funcs[0x4000], funcs[0x7000]]),
-        0x6000: (100, [funcs[0x6000]]),
-        0x7000: (24, [funcs[0x7000]]),
-        0x8000: (160, [funcs[0x8000],
-                       funcs[0x9000],
-                       funcs[0x4000],
-                       funcs[0x7000]]),
-        0x9000: (140, [funcs[0x9000], funcs[0x4000], funcs[0x7000]]),
-        0x10000: (200, [funcs[0x10000],
-                        funcs[0x2000],
-                        funcs[0x10000],
-                        funcs[0x2000],
-                        funcs[0x5000],
-                        funcs[0x4000],
-                        funcs[0x7000]]),
-    }
-    expect_cycles = [
-        {funcs[0x4000], funcs[0x8000], funcs[0x9000]},
-        {funcs[0x7000]},
-    ]
-    for func in funcs.values():
-      (stack_max_usage, stack_max_path) = expect_func_stack[func.address]
-      self.assertEqual(func.stack_max_usage, stack_max_usage)
-      self.assertEqual(func.stack_max_path, stack_max_path)
-
-    self.assertEqual(len(cycles), len(expect_cycles))
-    for cycle in cycles:
-      self.assertTrue(cycle in expect_cycles)
-
-  @mock.patch('subprocess.check_output')
-  def testAddressToLine(self, checkoutput_mock):
-    checkoutput_mock.return_value = 'fake_func\n/test.c:1'
-    self.assertEqual(self.analyzer.AddressToLine(0x1234),
-                     [('fake_func', '/test.c', 1)])
-    checkoutput_mock.assert_called_once_with(
-        ['addr2line', '-f', '-e', './ec.RW.elf', '1234'], encoding='utf-8')
-    checkoutput_mock.reset_mock()
-
-    checkoutput_mock.return_value = 'fake_func\n/a.c:1\nbake_func\n/b.c:2\n'
-    self.assertEqual(self.analyzer.AddressToLine(0x1234, True),
-                     [('fake_func', '/a.c', 1), ('bake_func', '/b.c', 2)])
-    checkoutput_mock.assert_called_once_with(
-        ['addr2line', '-f', '-e', './ec.RW.elf', '1234', '-i'],
-        encoding='utf-8')
-    checkoutput_mock.reset_mock()
-
-    checkoutput_mock.return_value = 'fake_func\n/test.c:1 (discriminator 128)'
-    self.assertEqual(self.analyzer.AddressToLine(0x12345),
-                     [('fake_func', '/test.c', 1)])
-    checkoutput_mock.assert_called_once_with(
-        ['addr2line', '-f', '-e', './ec.RW.elf', '12345'], encoding='utf-8')
-    checkoutput_mock.reset_mock()
-
-    checkoutput_mock.return_value = '??\n:?\nbake_func\n/b.c:2\n'
-    self.assertEqual(self.analyzer.AddressToLine(0x123456),
-                     [None, ('bake_func', '/b.c', 2)])
-    checkoutput_mock.assert_called_once_with(
-        ['addr2line', '-f', '-e', './ec.RW.elf', '123456'], encoding='utf-8')
-    checkoutput_mock.reset_mock()
-
-    with self.assertRaisesRegexp(sa.StackAnalyzerError,
-                                 'addr2line failed to resolve lines.'):
-      checkoutput_mock.side_effect = subprocess.CalledProcessError(1, '')
-      self.analyzer.AddressToLine(0x5678)
-
-    with self.assertRaisesRegexp(sa.StackAnalyzerError,
-                                 'Failed to run addr2line.'):
-      checkoutput_mock.side_effect = OSError()
-      self.analyzer.AddressToLine(0x9012)
-
-  @mock.patch('subprocess.check_output')
-  @mock.patch('stack_analyzer.StackAnalyzer.AddressToLine')
-  def testAndesAnalyze(self, addrtoline_mock, checkoutput_mock):
-    disasm_text = (
-        '\n'
-        'build/{BOARD}/RW/ec.RW.elf:     file format elf32-nds32le'
-        '\n'
-        'Disassembly of section .text:\n'
-        '\n'
-        '00000900 <wook_task>:\n'
-        '   ...\n'
-        '00001000 <hook_task>:\n'
-        '   1000:   fc 00\t\tpush25 $r10, #16    ! {$r6~$r10, $fp, $gp, $lp}\n'
-        '   1002:   47 70\t\tmovi55 $r0, #1\n'
-        '   1006:   00 01 5c fc\tbne    $r6, $r0, 2af6a\n'
-        '00002000 <console_task>:\n'
-        '   2000:   fc 00\t\tpush25 $r6, #0    ! {$r6, $fp, $gp, $lp} \n'
-        '   2002:   f0 0e fc c5\tjal   1000 <hook_task>\n'
-        '   2006:   f0 0e bd 3b\tj  53968 <get_program_memory_addr>\n'
-        '   200a:   12 34 56 78\tjral5 $r0\n'
-    )
-
-    addrtoline_mock.return_value = [('??', '??', 0)]
-    self.analyzer.annotation = {
-        'exception_frame_size': 64,
-        'remove': [['fake_func']],
-    }
-
-    with mock.patch('builtins.print') as print_mock:
-      checkoutput_mock.return_value = disasm_text
-      self.analyzer.Analyze()
-      print_mock.assert_has_calls([
-          mock.call(
-              'Task: HOOKS, Max size: 96 (32 + 64), Allocated size: 2048'),
-          mock.call('Call Trace:'),
-          mock.call('    hook_task (32) [??:0] 1000'),
-          mock.call(
-              'Task: CONSOLE, Max size: 112 (48 + 64), Allocated size: 460'),
-          mock.call('Call Trace:'),
-          mock.call('    console_task (16) [??:0] 2000'),
-          mock.call('        -> ??[??:0] 2002'),
-          mock.call('    hook_task (32) [??:0] 1000'),
-          mock.call('Unresolved indirect callsites:'),
-          mock.call('    In function console_task:'),
-          mock.call('        -> ??[??:0] 200a'),
-          mock.call('Unresolved annotation signatures:'),
-          mock.call('    fake_func: function is not found'),
-      ])
-
-    with self.assertRaisesRegexp(sa.StackAnalyzerError,
-                                 'Failed to run objdump.'):
-      checkoutput_mock.side_effect = OSError()
-      self.analyzer.Analyze()
-
-    with self.assertRaisesRegexp(sa.StackAnalyzerError,
-                                 'objdump failed to disassemble.'):
-      checkoutput_mock.side_effect = subprocess.CalledProcessError(1, '')
-      self.analyzer.Analyze()
-
-  @mock.patch('subprocess.check_output')
-  @mock.patch('stack_analyzer.StackAnalyzer.AddressToLine')
-  def testArmAnalyze(self, addrtoline_mock, checkoutput_mock):
-    disasm_text = (
-        '\n'
-        'build/{BOARD}/RW/ec.RW.elf:     file format elf32-littlearm'
-        '\n'
-        'Disassembly of section .text:\n'
-        '\n'
-        '00000900 <wook_task>:\n'
-        '	...\n'
-        '00001000 <hook_task>:\n'
-        '   1000:	b508\t\tpush	{r3, lr}\n'
-        '   1002:	4770\t\tbx	lr\n'
-        '   1006:	00015cfc\t.word	0x00015cfc\n'
-        '00002000 <console_task>:\n'
-        '   2000:	b508\t\tpush	{r3, lr}\n'
-        '   2002:	f00e fcc5\tbl	1000 <hook_task>\n'
-        '   2006:	f00e bd3b\tb.w	53968 <get_program_memory_addr>\n'
-        '   200a:	1234 5678\tb.w  sl\n'
-    )
-
-    addrtoline_mock.return_value = [('??', '??', 0)]
-    self.analyzer.annotation = {
-        'exception_frame_size': 64,
-        'remove': [['fake_func']],
-    }
-
-    with mock.patch('builtins.print') as print_mock:
-      checkoutput_mock.return_value = disasm_text
-      self.analyzer.Analyze()
-      print_mock.assert_has_calls([
-          mock.call(
-              'Task: HOOKS, Max size: 72 (8 + 64), Allocated size: 2048'),
-          mock.call('Call Trace:'),
-          mock.call('    hook_task (8) [??:0] 1000'),
-          mock.call(
-              'Task: CONSOLE, Max size: 80 (16 + 64), Allocated size: 460'),
-          mock.call('Call Trace:'),
-          mock.call('    console_task (8) [??:0] 2000'),
-          mock.call('        -> ??[??:0] 2002'),
-          mock.call('    hook_task (8) [??:0] 1000'),
-          mock.call('Unresolved indirect callsites:'),
-          mock.call('    In function console_task:'),
-          mock.call('        -> ??[??:0] 200a'),
-          mock.call('Unresolved annotation signatures:'),
-          mock.call('    fake_func: function is not found'),
-      ])
-
-    with self.assertRaisesRegexp(sa.StackAnalyzerError,
-                                 'Failed to run objdump.'):
-      checkoutput_mock.side_effect = OSError()
-      self.analyzer.Analyze()
-
-    with self.assertRaisesRegexp(sa.StackAnalyzerError,
-                                 'objdump failed to disassemble.'):
-      checkoutput_mock.side_effect = subprocess.CalledProcessError(1, '')
-      self.analyzer.Analyze()
-
-  @mock.patch('subprocess.check_output')
-  @mock.patch('stack_analyzer.ParseArgs')
-  def testMain(self, parseargs_mock, checkoutput_mock):
-    symbol_text = ('1000 g     F .text  0000015c .hidden hook_task\n'
-                   '2000 g     F .text  0000051c .hidden console_task\n')
-    rodata_text = (
-        '\n'
-        'Contents of section .rodata:\n'
-        ' 20000 dead1000 00100000 dead2000 00200000  He..f.He..s.\n'
-    )
-
-    args = mock.MagicMock(elf_path='./ec.RW.elf',
-                          export_taskinfo='fake',
-                          section='RW',
-                          objdump='objdump',
-                          addr2line='addr2line',
-                          annotation='fake')
-    parseargs_mock.return_value = args
-
-    with mock.patch('os.path.exists') as path_mock:
-      path_mock.return_value = False
-      with mock.patch('builtins.print') as print_mock:
-        with mock.patch('builtins.open', mock.mock_open()) as open_mock:
-          sa.main()
-          print_mock.assert_any_call(
-              'Warning: Annotation file fake does not exist.')
-
-    with mock.patch('os.path.exists') as path_mock:
-      path_mock.return_value = True
-      with mock.patch('builtins.print') as print_mock:
-        with mock.patch('builtins.open', mock.mock_open()) as open_mock:
-          open_mock.side_effect = IOError()
-          sa.main()
-          print_mock.assert_called_once_with(
-              'Error: Failed to open annotation file fake.')
-
-      with mock.patch('builtins.print') as print_mock:
-        with mock.patch('builtins.open', mock.mock_open()) as open_mock:
-          open_mock.return_value.read.side_effect = ['{', '']
-          sa.main()
-          open_mock.assert_called_once_with('fake', 'r')
-          print_mock.assert_called_once_with(
-              'Error: Failed to parse annotation file fake.')
-
-      with mock.patch('builtins.print') as print_mock:
-        with mock.patch('builtins.open',
-                        mock.mock_open(read_data='')) as open_mock:
-          sa.main()
-          print_mock.assert_called_once_with(
-              'Error: Invalid annotation file fake.')
-
-    args.annotation = None
-
-    with mock.patch('builtins.print') as print_mock:
-      checkoutput_mock.side_effect = [symbol_text, rodata_text]
-      sa.main()
-      print_mock.assert_called_once_with(
-          'Error: Failed to load export_taskinfo.')
-
-    with mock.patch('builtins.print') as print_mock:
-      checkoutput_mock.side_effect = subprocess.CalledProcessError(1, '')
-      sa.main()
-      print_mock.assert_called_once_with(
-          'Error: objdump failed to dump symbol table or rodata.')
-
-    with mock.patch('builtins.print') as print_mock:
-      checkoutput_mock.side_effect = OSError()
-      sa.main()
-      print_mock.assert_called_once_with('Error: Failed to run objdump.')
-
-
-if __name__ == '__main__':
-  unittest.main()
+        (
+            add_rules,
+            remove_rules,
+            invalid_sigtxts,
+        ) = self.analyzer.LoadAnnotation()
+        self.assertEqual(add_rules, {})
+        self.assertEqual(
+            list.sort(remove_rules),
+            list.sort(
+                [
+                    [("a", None, None), ("1", None, None), ("x", None, None)],
+                    [("a", None, None), ("0", None, None), ("x", None, None)],
+                    [("a", None, None), ("2", None, None), ("x", None, None)],
+                    [
+                        ("b", os.path.abspath("x"), 3),
+                        ("1", None, None),
+                        ("x", None, None),
+                    ],
+                    [
+                        ("b", os.path.abspath("x"), 3),
+                        ("0", None, None),
+                        ("x", None, None),
+                    ],
+                    [
+                        ("b", os.path.abspath("x"), 3),
+                        ("2", None, None),
+                        ("x", None, None),
+                    ],
+                ]
+            ),
+        )
+        self.assertEqual(invalid_sigtxts, {"["})
+
+        self.analyzer.annotation = {
+            "add": {
+                "touchpad_calc": [dict(name="__array", stride=8, offset=4)],
+            }
+        }
+        (
+            add_rules,
+            remove_rules,
+            invalid_sigtxts,
+        ) = self.analyzer.LoadAnnotation()
+        self.assertEqual(
+            add_rules,
+            {
+                ("touchpad_calc", None, None): set(
+                    [("console_task", None, None), ("hook_task", None, None)]
+                )
+            },
+        )
+
+        funcs = {
+            0x1000: sa.Function(0x1000, "hook_task", 0, []),
+            0x2000: sa.Function(0x2000, "console_task", 0, []),
+            0x4000: sa.Function(0x4000, "touchpad_calc", 0, []),
+            0x5000: sa.Function(0x5000, "touchpad_calc.constprop.42", 0, []),
+            0x13000: sa.Function(0x13000, "inlined_mul", 0, []),
+            0x13100: sa.Function(0x13100, "inlined_mul", 0, []),
+        }
+        funcs[0x1000].callsites = [sa.Callsite(0x1002, None, False, None)]
+        # Set address_to_line_cache to fake the results of addr2line.
+        self.analyzer.address_to_line_cache = {
+            (0x1000, False): [("hook_task", os.path.abspath("a.c"), 10)],
+            (0x1002, False): [("toot_calc", os.path.abspath("t.c"), 1234)],
+            (0x2000, False): [("console_task", os.path.abspath("b.c"), 20)],
+            (0x4000, False): [("toudhpad_calc", os.path.abspath("a.c"), 20)],
+            (0x5000, False): [
+                ("touchpad_calc.constprop.42", os.path.abspath("b.c"), 40)
+            ],
+            (0x12000, False): [("trackpad_range", os.path.abspath("t.c"), 10)],
+            (0x13000, False): [("inlined_mul", os.path.abspath("x.c"), 12)],
+            (0x13100, False): [("inlined_mul", os.path.abspath("x.c"), 12)],
+        }
+        self.analyzer.annotation = {
+            "add": {
+                "hook_task.lto.573": ["touchpad_calc.lto.2501[a.c]"],
+                "console_task": ["touchpad_calc[b.c]", "inlined_mul_alias"],
+                "hook_task[q.c]": ["hook_task"],
+                "inlined_mul[x.c]": ["inlined_mul"],
+                "toot_calc[t.c:1234]": ["hook_task"],
+            },
+            "remove": [
+                ["touchpad?calc["],
+                "touchpad_calc",
+                ["touchpad_calc[a.c]"],
+                ["task_unk[a.c]"],
+                ["touchpad_calc[x/a.c]"],
+                ["trackpad_range"],
+                ["inlined_mul"],
+                ["inlined_mul", "console_task", "touchpad_calc[a.c]"],
+                ["inlined_mul", "inlined_mul_alias", "console_task"],
+                ["inlined_mul", "inlined_mul_alias", "console_task"],
+            ],
+        }
+        (
+            add_rules,
+            remove_rules,
+            invalid_sigtxts,
+        ) = self.analyzer.LoadAnnotation()
+        self.assertEqual(invalid_sigtxts, {"touchpad?calc["})
+
+        signature_set = set()
+        for src_sig, dst_sigs in add_rules.items():
+            signature_set.add(src_sig)
+            signature_set.update(dst_sigs)
+
+        for remove_sigs in remove_rules:
+            signature_set.update(remove_sigs)
+
+        (signature_map, failed_sigs) = self.analyzer.MapAnnotation(
+            funcs, signature_set
+        )
+        result = self.analyzer.ResolveAnnotation(funcs)
+        (add_set, remove_list, eliminated_addrs, failed_sigs) = result
+
+        expect_signature_map = {
+            ("hook_task", None, None): {funcs[0x1000]},
+            ("touchpad_calc", os.path.abspath("a.c"), None): {funcs[0x4000]},
+            ("touchpad_calc", os.path.abspath("b.c"), None): {funcs[0x5000]},
+            ("console_task", None, None): {funcs[0x2000]},
+            ("inlined_mul_alias", None, None): {funcs[0x13100]},
+            ("inlined_mul", os.path.abspath("x.c"), None): {
+                funcs[0x13000],
+                funcs[0x13100],
+            },
+            ("inlined_mul", None, None): {funcs[0x13000], funcs[0x13100]},
+        }
+        self.assertEqual(len(signature_map), len(expect_signature_map))
+        for sig, funclist in signature_map.items():
+            self.assertEqual(set(funclist), expect_signature_map[sig])
+
+        self.assertEqual(
+            add_set,
+            {
+                (funcs[0x1000], funcs[0x4000]),
+                (funcs[0x1000], funcs[0x1000]),
+                (funcs[0x2000], funcs[0x5000]),
+                (funcs[0x2000], funcs[0x13100]),
+                (funcs[0x13000], funcs[0x13000]),
+                (funcs[0x13000], funcs[0x13100]),
+                (funcs[0x13100], funcs[0x13000]),
+                (funcs[0x13100], funcs[0x13100]),
+            },
+        )
+        expect_remove_list = [
+            [funcs[0x4000]],
+            [funcs[0x13000]],
+            [funcs[0x13100]],
+            [funcs[0x13000], funcs[0x2000], funcs[0x4000]],
+            [funcs[0x13100], funcs[0x2000], funcs[0x4000]],
+            [funcs[0x13000], funcs[0x13100], funcs[0x2000]],
+            [funcs[0x13100], funcs[0x13100], funcs[0x2000]],
+        ]
+        self.assertEqual(len(remove_list), len(expect_remove_list))
+        for remove_path in remove_list:
+            self.assertTrue(remove_path in expect_remove_list)
+
+        self.assertEqual(eliminated_addrs, {0x1002})
+        self.assertEqual(
+            failed_sigs,
+            {
+                ("touchpad?calc[", sa.StackAnalyzer.ANNOTATION_ERROR_INVALID),
+                ("touchpad_calc", sa.StackAnalyzer.ANNOTATION_ERROR_AMBIGUOUS),
+                ("hook_task[q.c]", sa.StackAnalyzer.ANNOTATION_ERROR_NOTFOUND),
+                ("task_unk[a.c]", sa.StackAnalyzer.ANNOTATION_ERROR_NOTFOUND),
+                (
+                    "touchpad_calc[x/a.c]",
+                    sa.StackAnalyzer.ANNOTATION_ERROR_NOTFOUND,
+                ),
+                ("trackpad_range", sa.StackAnalyzer.ANNOTATION_ERROR_NOTFOUND),
+            },
+        )
+
+    def testPreprocessAnnotation(self):
+        funcs = {
+            0x1000: sa.Function(0x1000, "hook_task", 0, []),
+            0x2000: sa.Function(0x2000, "console_task", 0, []),
+            0x4000: sa.Function(0x4000, "touchpad_calc", 0, []),
+        }
+        funcs[0x1000].callsites = [
+            sa.Callsite(0x1002, 0x1000, False, funcs[0x1000])
+        ]
+        funcs[0x2000].callsites = [
+            sa.Callsite(0x2002, 0x1000, False, funcs[0x1000]),
+            sa.Callsite(0x2006, None, True, None),
+        ]
+        add_set = {
+            (funcs[0x2000], funcs[0x2000]),
+            (funcs[0x2000], funcs[0x4000]),
+            (funcs[0x4000], funcs[0x1000]),
+            (funcs[0x4000], funcs[0x2000]),
+        }
+        remove_list = [
+            [funcs[0x1000]],
+            [funcs[0x2000], funcs[0x2000]],
+            [funcs[0x4000], funcs[0x1000]],
+            [funcs[0x2000], funcs[0x4000], funcs[0x2000]],
+            [funcs[0x4000], funcs[0x1000], funcs[0x4000]],
+        ]
+        eliminated_addrs = {0x2006}
+
+        remaining_remove_list = self.analyzer.PreprocessAnnotation(
+            funcs, add_set, remove_list, eliminated_addrs
+        )
+
+        expect_funcs = {
+            0x1000: sa.Function(0x1000, "hook_task", 0, []),
+            0x2000: sa.Function(0x2000, "console_task", 0, []),
+            0x4000: sa.Function(0x4000, "touchpad_calc", 0, []),
+        }
+        expect_funcs[0x2000].callsites = [
+            sa.Callsite(None, 0x4000, False, expect_funcs[0x4000])
+        ]
+        expect_funcs[0x4000].callsites = [
+            sa.Callsite(None, 0x2000, False, expect_funcs[0x2000])
+        ]
+        self.assertEqual(funcs, expect_funcs)
+        self.assertEqual(
+            remaining_remove_list,
+            [
+                [funcs[0x2000], funcs[0x4000], funcs[0x2000]],
+            ],
+        )
+
+    def testAndesAnalyzeDisassembly(self):
+        disasm_text = (
+            "\n"
+            "build/{BOARD}/RW/ec.RW.elf:     file format elf32-nds32le"
+            "\n"
+            "Disassembly of section .text:\n"
+            "\n"
+            "00000900 <wook_task>:\n"
+            "   ...\n"
+            "00001000 <hook_task>:\n"
+            "   1000:   fc 42\tpush25 $r10, #16    ! {$r6~$r10, $fp, $gp, $lp}\n"
+            "   1004:   47 70\t\tmovi55 $r0, #1\n"
+            "   1006:   b1 13\tbnezs8 100929de <flash_command_write>\n"
+            "   1008:   00 01 5c fc\tbne    $r6, $r0, 2af6a\n"
+            "00002000 <console_task>:\n"
+            "   2000:   fc 00\t\tpush25 $r6, #0    ! {$r6, $fp, $gp, $lp} \n"
+            "   2002:   f0 0e fc c5\tjal   1000 <hook_task>\n"
+            "   2006:   f0 0e bd 3b\tj  53968 <get_program_memory_addr>\n"
+            "   200a:   de ad be ef\tswi.gp $r0, [ + #-11036]\n"
+            "00004000 <touchpad_calc>:\n"
+            "   4000:   47 70\t\tmovi55 $r0, #1\n"
+            "00010000 <look_task>:"
+        )
+        function_map = self.analyzer.AnalyzeDisassembly(disasm_text)
+        func_hook_task = sa.Function(
+            0x1000,
+            "hook_task",
+            48,
+            [sa.Callsite(0x1006, 0x100929DE, True, None)],
+        )
+        expect_funcmap = {
+            0x1000: func_hook_task,
+            0x2000: sa.Function(
+                0x2000,
+                "console_task",
+                16,
+                [
+                    sa.Callsite(0x2002, 0x1000, False, func_hook_task),
+                    sa.Callsite(0x2006, 0x53968, True, None),
+                ],
+            ),
+            0x4000: sa.Function(0x4000, "touchpad_calc", 0, []),
+        }
+        self.assertEqual(function_map, expect_funcmap)
+
+    def testArmAnalyzeDisassembly(self):
+        disasm_text = (
+            "\n"
+            "build/{BOARD}/RW/ec.RW.elf:     file format elf32-littlearm"
+            "\n"
+            "Disassembly of section .text:\n"
+            "\n"
+            "00000900 <wook_task>:\n"
+            "	...\n"
+            "00001000 <hook_task>:\n"
+            "   1000:	dead beef\tfake\n"
+            "   1004:	4770\t\tbx	lr\n"
+            "   1006:	b113\tcbz	r3, 100929de <flash_command_write>\n"
+            "   1008:	00015cfc\t.word	0x00015cfc\n"
+            "00002000 <console_task>:\n"
+            "   2000:	b508\t\tpush	{r3, lr} ; malformed comments,; r0, r1 \n"
+            "   2002:	f00e fcc5\tbl	1000 <hook_task>\n"
+            "   2006:	f00e bd3b\tb.w	53968 <get_program_memory_addr>\n"
+            "   200a:	dead beef\tfake\n"
+            "00004000 <touchpad_calc>:\n"
+            "   4000:	4770\t\tbx	lr\n"
+            "00010000 <look_task>:"
+        )
+        function_map = self.analyzer.AnalyzeDisassembly(disasm_text)
+        func_hook_task = sa.Function(
+            0x1000,
+            "hook_task",
+            0,
+            [sa.Callsite(0x1006, 0x100929DE, True, None)],
+        )
+        expect_funcmap = {
+            0x1000: func_hook_task,
+            0x2000: sa.Function(
+                0x2000,
+                "console_task",
+                8,
+                [
+                    sa.Callsite(0x2002, 0x1000, False, func_hook_task),
+                    sa.Callsite(0x2006, 0x53968, True, None),
+                ],
+            ),
+            0x4000: sa.Function(0x4000, "touchpad_calc", 0, []),
+        }
+        self.assertEqual(function_map, expect_funcmap)
+
+    def testAnalyzeCallGraph(self):
+        funcs = {
+            0x1000: sa.Function(0x1000, "hook_task", 0, []),
+            0x2000: sa.Function(0x2000, "console_task", 8, []),
+            0x3000: sa.Function(0x3000, "task_a", 12, []),
+            0x4000: sa.Function(0x4000, "task_b", 96, []),
+            0x5000: sa.Function(0x5000, "task_c", 32, []),
+            0x6000: sa.Function(0x6000, "task_d", 100, []),
+            0x7000: sa.Function(0x7000, "task_e", 24, []),
+            0x8000: sa.Function(0x8000, "task_f", 20, []),
+            0x9000: sa.Function(0x9000, "task_g", 20, []),
+            0x10000: sa.Function(0x10000, "task_x", 16, []),
+        }
+        funcs[0x1000].callsites = [
+            sa.Callsite(0x1002, 0x3000, False, funcs[0x3000]),
+            sa.Callsite(0x1006, 0x4000, False, funcs[0x4000]),
+        ]
+        funcs[0x2000].callsites = [
+            sa.Callsite(0x2002, 0x5000, False, funcs[0x5000]),
+            sa.Callsite(0x2006, 0x2000, False, funcs[0x2000]),
+            sa.Callsite(0x200A, 0x10000, False, funcs[0x10000]),
+        ]
+        funcs[0x3000].callsites = [
+            sa.Callsite(0x3002, 0x4000, False, funcs[0x4000]),
+            sa.Callsite(0x3006, 0x1000, False, funcs[0x1000]),
+        ]
+        funcs[0x4000].callsites = [
+            sa.Callsite(0x4002, 0x6000, True, funcs[0x6000]),
+            sa.Callsite(0x4006, 0x7000, False, funcs[0x7000]),
+            sa.Callsite(0x400A, 0x8000, False, funcs[0x8000]),
+        ]
+        funcs[0x5000].callsites = [
+            sa.Callsite(0x5002, 0x4000, False, funcs[0x4000])
+        ]
+        funcs[0x7000].callsites = [
+            sa.Callsite(0x7002, 0x7000, False, funcs[0x7000])
+        ]
+        funcs[0x8000].callsites = [
+            sa.Callsite(0x8002, 0x9000, False, funcs[0x9000])
+        ]
+        funcs[0x9000].callsites = [
+            sa.Callsite(0x9002, 0x4000, False, funcs[0x4000])
+        ]
+        funcs[0x10000].callsites = [
+            sa.Callsite(0x10002, 0x2000, False, funcs[0x2000])
+        ]
+
+        cycles = self.analyzer.AnalyzeCallGraph(
+            funcs,
+            [
+                [funcs[0x2000]] * 2,
+                [funcs[0x10000], funcs[0x2000]] * 3,
+                [funcs[0x1000], funcs[0x3000], funcs[0x1000]],
+            ],
+        )
+
+        expect_func_stack = {
+            0x1000: (
+                268,
+                [
+                    funcs[0x1000],
+                    funcs[0x3000],
+                    funcs[0x4000],
+                    funcs[0x8000],
+                    funcs[0x9000],
+                    funcs[0x4000],
+                    funcs[0x7000],
+                ],
+            ),
+            0x2000: (
+                208,
+                [
+                    funcs[0x2000],
+                    funcs[0x10000],
+                    funcs[0x2000],
+                    funcs[0x10000],
+                    funcs[0x2000],
+                    funcs[0x5000],
+                    funcs[0x4000],
+                    funcs[0x7000],
+                ],
+            ),
+            0x3000: (
+                280,
+                [
+                    funcs[0x3000],
+                    funcs[0x1000],
+                    funcs[0x3000],
+                    funcs[0x4000],
+                    funcs[0x8000],
+                    funcs[0x9000],
+                    funcs[0x4000],
+                    funcs[0x7000],
+                ],
+            ),
+            0x4000: (120, [funcs[0x4000], funcs[0x7000]]),
+            0x5000: (152, [funcs[0x5000], funcs[0x4000], funcs[0x7000]]),
+            0x6000: (100, [funcs[0x6000]]),
+            0x7000: (24, [funcs[0x7000]]),
+            0x8000: (
+                160,
+                [funcs[0x8000], funcs[0x9000], funcs[0x4000], funcs[0x7000]],
+            ),
+            0x9000: (140, [funcs[0x9000], funcs[0x4000], funcs[0x7000]]),
+            0x10000: (
+                200,
+                [
+                    funcs[0x10000],
+                    funcs[0x2000],
+                    funcs[0x10000],
+                    funcs[0x2000],
+                    funcs[0x5000],
+                    funcs[0x4000],
+                    funcs[0x7000],
+                ],
+            ),
+        }
+        expect_cycles = [
+            {funcs[0x4000], funcs[0x8000], funcs[0x9000]},
+            {funcs[0x7000]},
+        ]
+        for func in funcs.values():
+            (stack_max_usage, stack_max_path) = expect_func_stack[func.address]
+            self.assertEqual(func.stack_max_usage, stack_max_usage)
+            self.assertEqual(func.stack_max_path, stack_max_path)
+
+        self.assertEqual(len(cycles), len(expect_cycles))
+        for cycle in cycles:
+            self.assertTrue(cycle in expect_cycles)
+
+    @mock.patch("subprocess.check_output")
+    def testAddressToLine(self, checkoutput_mock):
+        checkoutput_mock.return_value = "fake_func\n/test.c:1"
+        self.assertEqual(
+            self.analyzer.AddressToLine(0x1234), [("fake_func", "/test.c", 1)]
+        )
+        checkoutput_mock.assert_called_once_with(
+            ["addr2line", "-f", "-e", "./ec.RW.elf", "1234"], encoding="utf-8"
+        )
+        checkoutput_mock.reset_mock()
+
+        checkoutput_mock.return_value = "fake_func\n/a.c:1\nbake_func\n/b.c:2\n"
+        self.assertEqual(
+            self.analyzer.AddressToLine(0x1234, True),
+            [("fake_func", "/a.c", 1), ("bake_func", "/b.c", 2)],
+        )
+        checkoutput_mock.assert_called_once_with(
+            ["addr2line", "-f", "-e", "./ec.RW.elf", "1234", "-i"],
+            encoding="utf-8",
+        )
+        checkoutput_mock.reset_mock()
+
+        checkoutput_mock.return_value = (
+            "fake_func\n/test.c:1 (discriminator 128)"
+        )
+        self.assertEqual(
+            self.analyzer.AddressToLine(0x12345), [("fake_func", "/test.c", 1)]
+        )
+        checkoutput_mock.assert_called_once_with(
+            ["addr2line", "-f", "-e", "./ec.RW.elf", "12345"], encoding="utf-8"
+        )
+        checkoutput_mock.reset_mock()
+
+        checkoutput_mock.return_value = "??\n:?\nbake_func\n/b.c:2\n"
+        self.assertEqual(
+            self.analyzer.AddressToLine(0x123456),
+            [None, ("bake_func", "/b.c", 2)],
+        )
+        checkoutput_mock.assert_called_once_with(
+            ["addr2line", "-f", "-e", "./ec.RW.elf", "123456"], encoding="utf-8"
+        )
+        checkoutput_mock.reset_mock()
+
+        with self.assertRaisesRegexp(
+            sa.StackAnalyzerError, "addr2line failed to resolve lines."
+        ):
+            checkoutput_mock.side_effect = subprocess.CalledProcessError(1, "")
+            self.analyzer.AddressToLine(0x5678)
+
+        with self.assertRaisesRegexp(
+            sa.StackAnalyzerError, "Failed to run addr2line."
+        ):
+            checkoutput_mock.side_effect = OSError()
+            self.analyzer.AddressToLine(0x9012)
+
+    @mock.patch("subprocess.check_output")
+    @mock.patch("stack_analyzer.StackAnalyzer.AddressToLine")
+    def testAndesAnalyze(self, addrtoline_mock, checkoutput_mock):
+        disasm_text = (
+            "\n"
+            "build/{BOARD}/RW/ec.RW.elf:     file format elf32-nds32le"
+            "\n"
+            "Disassembly of section .text:\n"
+            "\n"
+            "00000900 <wook_task>:\n"
+            "   ...\n"
+            "00001000 <hook_task>:\n"
+            "   1000:   fc 00\t\tpush25 $r10, #16    ! {$r6~$r10, $fp, $gp, $lp}\n"
+            "   1002:   47 70\t\tmovi55 $r0, #1\n"
+            "   1006:   00 01 5c fc\tbne    $r6, $r0, 2af6a\n"
+            "00002000 <console_task>:\n"
+            "   2000:   fc 00\t\tpush25 $r6, #0    ! {$r6, $fp, $gp, $lp} \n"
+            "   2002:   f0 0e fc c5\tjal   1000 <hook_task>\n"
+            "   2006:   f0 0e bd 3b\tj  53968 <get_program_memory_addr>\n"
+            "   200a:   12 34 56 78\tjral5 $r0\n"
+        )
+
+        addrtoline_mock.return_value = [("??", "??", 0)]
+        self.analyzer.annotation = {
+            "exception_frame_size": 64,
+            "remove": [["fake_func"]],
+        }
+
+        with mock.patch("builtins.print") as print_mock:
+            checkoutput_mock.return_value = disasm_text
+            self.analyzer.Analyze()
+            print_mock.assert_has_calls(
+                [
+                    mock.call(
+                        "Task: HOOKS, Max size: 96 (32 + 64), Allocated size: 2048"
+                    ),
+                    mock.call("Call Trace:"),
+                    mock.call("    hook_task (32) [??:0] 1000"),
+                    mock.call(
+                        "Task: CONSOLE, Max size: 112 (48 + 64), Allocated size: 460"
+                    ),
+                    mock.call("Call Trace:"),
+                    mock.call("    console_task (16) [??:0] 2000"),
+                    mock.call("        -> ??[??:0] 2002"),
+                    mock.call("    hook_task (32) [??:0] 1000"),
+                    mock.call("Unresolved indirect callsites:"),
+                    mock.call("    In function console_task:"),
+                    mock.call("        -> ??[??:0] 200a"),
+                    mock.call("Unresolved annotation signatures:"),
+                    mock.call("    fake_func: function is not found"),
+                ]
+            )
+
+        with self.assertRaisesRegexp(
+            sa.StackAnalyzerError, "Failed to run objdump."
+        ):
+            checkoutput_mock.side_effect = OSError()
+            self.analyzer.Analyze()
+
+        with self.assertRaisesRegexp(
+            sa.StackAnalyzerError, "objdump failed to disassemble."
+        ):
+            checkoutput_mock.side_effect = subprocess.CalledProcessError(1, "")
+            self.analyzer.Analyze()
+
+    @mock.patch("subprocess.check_output")
+    @mock.patch("stack_analyzer.StackAnalyzer.AddressToLine")
+    def testArmAnalyze(self, addrtoline_mock, checkoutput_mock):
+        disasm_text = (
+            "\n"
+            "build/{BOARD}/RW/ec.RW.elf:     file format elf32-littlearm"
+            "\n"
+            "Disassembly of section .text:\n"
+            "\n"
+            "00000900 <wook_task>:\n"
+            "	...\n"
+            "00001000 <hook_task>:\n"
+            "   1000:	b508\t\tpush	{r3, lr}\n"
+            "   1002:	4770\t\tbx	lr\n"
+            "   1006:	00015cfc\t.word	0x00015cfc\n"
+            "00002000 <console_task>:\n"
+            "   2000:	b508\t\tpush	{r3, lr}\n"
+            "   2002:	f00e fcc5\tbl	1000 <hook_task>\n"
+            "   2006:	f00e bd3b\tb.w	53968 <get_program_memory_addr>\n"
+            "   200a:	1234 5678\tb.w  sl\n"
+        )
+
+        addrtoline_mock.return_value = [("??", "??", 0)]
+        self.analyzer.annotation = {
+            "exception_frame_size": 64,
+            "remove": [["fake_func"]],
+        }
+
+        with mock.patch("builtins.print") as print_mock:
+            checkoutput_mock.return_value = disasm_text
+            self.analyzer.Analyze()
+            print_mock.assert_has_calls(
+                [
+                    mock.call(
+                        "Task: HOOKS, Max size: 72 (8 + 64), Allocated size: 2048"
+                    ),
+                    mock.call("Call Trace:"),
+                    mock.call("    hook_task (8) [??:0] 1000"),
+                    mock.call(
+                        "Task: CONSOLE, Max size: 80 (16 + 64), Allocated size: 460"
+                    ),
+                    mock.call("Call Trace:"),
+                    mock.call("    console_task (8) [??:0] 2000"),
+                    mock.call("        -> ??[??:0] 2002"),
+                    mock.call("    hook_task (8) [??:0] 1000"),
+                    mock.call("Unresolved indirect callsites:"),
+                    mock.call("    In function console_task:"),
+                    mock.call("        -> ??[??:0] 200a"),
+                    mock.call("Unresolved annotation signatures:"),
+                    mock.call("    fake_func: function is not found"),
+                ]
+            )
+
+        with self.assertRaisesRegexp(
+            sa.StackAnalyzerError, "Failed to run objdump."
+        ):
+            checkoutput_mock.side_effect = OSError()
+            self.analyzer.Analyze()
+
+        with self.assertRaisesRegexp(
+            sa.StackAnalyzerError, "objdump failed to disassemble."
+        ):
+            checkoutput_mock.side_effect = subprocess.CalledProcessError(1, "")
+            self.analyzer.Analyze()
+
+    @mock.patch("subprocess.check_output")
+    @mock.patch("stack_analyzer.ParseArgs")
+    def testMain(self, parseargs_mock, checkoutput_mock):
+        symbol_text = (
+            "1000 g     F .text  0000015c .hidden hook_task\n"
+            "2000 g     F .text  0000051c .hidden console_task\n"
+        )
+        rodata_text = (
+            "\n"
+            "Contents of section .rodata:\n"
+            " 20000 dead1000 00100000 dead2000 00200000  He..f.He..s.\n"
+        )
+
+        args = mock.MagicMock(
+            elf_path="./ec.RW.elf",
+            export_taskinfo="fake",
+            section="RW",
+            objdump="objdump",
+            addr2line="addr2line",
+            annotation="fake",
+        )
+        parseargs_mock.return_value = args
+
+        with mock.patch("os.path.exists") as path_mock:
+            path_mock.return_value = False
+            with mock.patch("builtins.print") as print_mock:
+                with mock.patch("builtins.open", mock.mock_open()) as open_mock:
+                    sa.main()
+                    print_mock.assert_any_call(
+                        "Warning: Annotation file fake does not exist."
+                    )
+
+        with mock.patch("os.path.exists") as path_mock:
+            path_mock.return_value = True
+            with mock.patch("builtins.print") as print_mock:
+                with mock.patch("builtins.open", mock.mock_open()) as open_mock:
+                    open_mock.side_effect = IOError()
+                    sa.main()
+                    print_mock.assert_called_once_with(
+                        "Error: Failed to open annotation file fake."
+                    )
+
+            with mock.patch("builtins.print") as print_mock:
+                with mock.patch("builtins.open", mock.mock_open()) as open_mock:
+                    open_mock.return_value.read.side_effect = ["{", ""]
+                    sa.main()
+                    open_mock.assert_called_once_with("fake", "r")
+                    print_mock.assert_called_once_with(
+                        "Error: Failed to parse annotation file fake."
+                    )
+
+            with mock.patch("builtins.print") as print_mock:
+                with mock.patch(
+                    "builtins.open", mock.mock_open(read_data="")
+                ) as open_mock:
+                    sa.main()
+                    print_mock.assert_called_once_with(
+                        "Error: Invalid annotation file fake."
+                    )
+
+        args.annotation = None
+
+        with mock.patch("builtins.print") as print_mock:
+            checkoutput_mock.side_effect = [symbol_text, rodata_text]
+            sa.main()
+            print_mock.assert_called_once_with(
+                "Error: Failed to load export_taskinfo."
+            )
+
+        with mock.patch("builtins.print") as print_mock:
+            checkoutput_mock.side_effect = subprocess.CalledProcessError(1, "")
+            sa.main()
+            print_mock.assert_called_once_with(
+                "Error: objdump failed to dump symbol table or rodata."
+            )
+
+        with mock.patch("builtins.print") as print_mock:
+            checkoutput_mock.side_effect = OSError()
+            sa.main()
+            print_mock.assert_called_once_with("Error: Failed to run objdump.")
+
+
+if __name__ == "__main__":
+    unittest.main()
diff --git a/extra/tigertool/ecusb/__init__.py b/extra/tigertool/ecusb/__init__.py
index fe4dbc6749..9451551f37 100644
--- a/extra/tigertool/ecusb/__init__.py
+++ b/extra/tigertool/ecusb/__init__.py
@@ -1,9 +1,5 @@
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
 
-__all__ = ['tiny_servo_common', 'stm32usb', 'stm32uart', 'pty_driver']
+__all__ = ["tiny_servo_common", "stm32usb", "stm32uart", "pty_driver"]
diff --git a/extra/tigertool/ecusb/pty_driver.py b/extra/tigertool/ecusb/pty_driver.py
index 09ef8c42e4..723bf41b57 100644
--- a/extra/tigertool/ecusb/pty_driver.py
+++ b/extra/tigertool/ecusb/pty_driver.py
@@ -1,10 +1,6 @@
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
 
 """ptyDriver class
 
@@ -17,9 +13,10 @@ import ast
 import errno
 import fcntl
 import os
-import pexpect
 import time
-from pexpect import fdpexpect
+
+import pexpect  # pylint:disable=import-error
+from pexpect import fdpexpect  # pylint:disable=import-error
 
 # Expecting a result in 3 seconds is plenty even for slow platforms.
 DEFAULT_UART_TIMEOUT = 3
@@ -27,281 +24,291 @@ FLUSH_UART_TIMEOUT = 1
 
 
 class ptyError(Exception):
-  """Exception class for pty errors."""
+    """Exception class for pty errors."""
 
 
 UART_PARAMS = {
-    'uart_cmd': None,
-    'uart_multicmd': None,
-    'uart_regexp': None,
-    'uart_timeout': DEFAULT_UART_TIMEOUT,
+    "uart_cmd": None,
+    "uart_multicmd": None,
+    "uart_regexp": None,
+    "uart_timeout": DEFAULT_UART_TIMEOUT,
 }
 
 
 class ptyDriver(object):
-  """Automate interactive commands on a pty interface."""
-  def __init__(self, interface, params, fast=False):
-    """Init class variables."""
-    self._child = None
-    self._fd = None
-    self._interface = interface
-    self._pty_path = self._interface.get_pty()
-    self._dict = UART_PARAMS.copy()
-    self._fast = fast
-
-  def __del__(self):
-    self.close()
-
-  def close(self):
-    """Close any open files and interfaces."""
-    if self._fd:
-      self._close()
-    self._interface.close()
-
-  def _open(self):
-    """Connect to serial device and create pexpect interface."""
-    assert self._fd is None
-    self._fd = os.open(self._pty_path, os.O_RDWR | os.O_NONBLOCK)
-    # Don't allow forked processes to access.
-    fcntl.fcntl(self._fd, fcntl.F_SETFD,
-                fcntl.fcntl(self._fd, fcntl.F_GETFD) | fcntl.FD_CLOEXEC)
-    self._child = fdpexpect.fdspawn(self._fd)
-    # pexpect defaults to a 100ms delay before sending characters, to
-    # work around race conditions in ssh. We don't need this feature
-    # so we'll change delaybeforesend from 0.1 to 0.001 to speed things up.
-    if self._fast:
-      self._child.delaybeforesend = 0.001
-
-  def _close(self):
-    """Close serial device connection."""
-    os.close(self._fd)
-    self._fd = None
-    self._child = None
-
-  def _flush(self):
-    """Flush device output to prevent previous messages interfering."""
-    if self._child.sendline('') != 1:
-      raise ptyError('Failed to send newline.')
-    # Have a maximum timeout for the flush operation. We should have cleared
-    # all data from the buffer, but if data is regularly being generated, we
-    # can't guarantee it will ever stop.
-    flush_end_time = time.time() + FLUSH_UART_TIMEOUT
-    while time.time() <= flush_end_time:
-      try:
-        self._child.expect('.', timeout=0.01)
-      except (pexpect.TIMEOUT, pexpect.EOF):
-        break
-      except OSError as e:
-        # EAGAIN indicates no data available, maybe we didn't wait long enough.
-        if e.errno != errno.EAGAIN:
-          raise
-        break
-
-  def _send(self, cmds):
-    """Send command to EC.
-
-    This function always flushes serial device before sending, and is used as
-    a wrapper function to make sure the channel is always flushed before
-    sending commands.
-
-    Args:
-      cmds: The commands to send to the device, either a list or a string.
-
-    Raises:
-      ptyError: Raised when writing to the device fails.
-    """
-    self._flush()
-    if not isinstance(cmds, list):
-      cmds = [cmds]
-    for cmd in cmds:
-      if self._child.sendline(cmd) != len(cmd) + 1:
-        raise ptyError('Failed to send command.')
-
-  def _issue_cmd(self, cmds):
-    """Send command to the device and do not wait for response.
-
-    Args:
-      cmds: The commands to send to the device, either a list or a string.
-    """
-    self._issue_cmd_get_results(cmds, [])
-
-  def _issue_cmd_get_results(self, cmds,
-                             regex_list, timeout=DEFAULT_UART_TIMEOUT):
-    """Send command to the device and wait for response.
-
-    This function waits for response message matching a regular
-    expressions.
-
-    Args:
-      cmds: The commands issued, either a list or a string.
-      regex_list: List of Regular expressions used to match response message.
-        Note1, list must be ordered.
-        Note2, empty list sends and returns.
-      timeout: time to wait for matching results before failing.
-
-    Returns:
-      List of tuples, each of which contains the entire matched string and
-      all the subgroups of the match. None if not matched.
-      For example:
-        response of the given command:
-          High temp: 37.2
-          Low temp: 36.4
-        regex_list:
-          ['High temp: (\d+)\.(\d+)', 'Low temp: (\d+)\.(\d+)']
-        returns:
-          [('High temp: 37.2', '37', '2'), ('Low temp: 36.4', '36', '4')]
-
-    Raises:
-      ptyError: If timed out waiting for a response
-    """
-    result_list = []
-    self._open()
-    try:
-      self._send(cmds)
-      for regex in regex_list:
-        self._child.expect(regex, timeout)
-        match = self._child.match
-        lastindex = match.lastindex if match and match.lastindex else 0
-        # Create a tuple which contains the entire matched string and all
-        # the subgroups of the match.
-        result = match.group(*range(lastindex + 1)) if match else None
-        if result:
-          result = tuple(res.decode('utf-8') for res in result)
-        result_list.append(result)
-    except pexpect.TIMEOUT:
-      raise ptyError('Timeout waiting for response.')
-    finally:
-      if not regex_list:
-        # Must be longer than delaybeforesend
-        time.sleep(0.1)
-      self._close()
-    return result_list
-
-  def _issue_cmd_get_multi_results(self, cmd, regex):
-    """Send command to the device and wait for multiple response.
-
-    This function waits for arbitrary number of response message
-    matching a regular expression.
-
-    Args:
-      cmd: The command issued.
-      regex: Regular expression used to match response message.
-
-    Returns:
-      List of tuples, each of which contains the entire matched string and
-      all the subgroups of the match. None if not matched.
-    """
-    result_list = []
-    self._open()
-    try:
-      self._send(cmd)
-      while True:
+    """Automate interactive commands on a pty interface."""
+
+    def __init__(self, interface, params, fast=False):
+        """Init class variables."""
+        self._child = None
+        self._fd = None
+        self._interface = interface
+        self._pty_path = self._interface.get_pty()
+        self._dict = UART_PARAMS.copy()
+        self._fast = fast
+
+    def __del__(self):
+        self.close()
+
+    def close(self):
+        """Close any open files and interfaces."""
+        if self._fd:
+            self._close()
+        self._interface.close()
+
+    def _open(self):
+        """Connect to serial device and create pexpect interface."""
+        assert self._fd is None
+        self._fd = os.open(self._pty_path, os.O_RDWR | os.O_NONBLOCK)
+        # Don't allow forked processes to access.
+        fcntl.fcntl(
+            self._fd,
+            fcntl.F_SETFD,
+            fcntl.fcntl(self._fd, fcntl.F_GETFD) | fcntl.FD_CLOEXEC,
+        )
+        self._child = fdpexpect.fdspawn(self._fd)
+        # pexpect defaults to a 100ms delay before sending characters, to
+        # work around race conditions in ssh. We don't need this feature
+        # so we'll change delaybeforesend from 0.1 to 0.001 to speed things up.
+        if self._fast:
+            self._child.delaybeforesend = 0.001
+
+    def _close(self):
+        """Close serial device connection."""
+        os.close(self._fd)
+        self._fd = None
+        self._child = None
+
+    def _flush(self):
+        """Flush device output to prevent previous messages interfering."""
+        if self._child.sendline("") != 1:
+            raise ptyError("Failed to send newline.")
+        # Have a maximum timeout for the flush operation. We should have cleared
+        # all data from the buffer, but if data is regularly being generated, we
+        # can't guarantee it will ever stop.
+        flush_end_time = time.time() + FLUSH_UART_TIMEOUT
+        while time.time() <= flush_end_time:
+            try:
+                self._child.expect(".", timeout=0.01)
+            except (pexpect.TIMEOUT, pexpect.EOF):
+                break
+            except OSError as e:
+                # EAGAIN indicates no data available, maybe we didn't wait long enough.
+                if e.errno != errno.EAGAIN:
+                    raise
+                break
+
+    def _send(self, cmds):
+        """Send command to EC.
+
+        This function always flushes serial device before sending, and is used as
+        a wrapper function to make sure the channel is always flushed before
+        sending commands.
+
+        Args:
+          cmds: The commands to send to the device, either a list or a string.
+
+        Raises:
+          ptyError: Raised when writing to the device fails.
+        """
+        self._flush()
+        if not isinstance(cmds, list):
+            cmds = [cmds]
+        for cmd in cmds:
+            if self._child.sendline(cmd) != len(cmd) + 1:
+                raise ptyError("Failed to send command.")
+
+    def _issue_cmd(self, cmds):
+        """Send command to the device and do not wait for response.
+
+        Args:
+          cmds: The commands to send to the device, either a list or a string.
+        """
+        self._issue_cmd_get_results(cmds, [])
+
+    def _issue_cmd_get_results(
+        self, cmds, regex_list, timeout=DEFAULT_UART_TIMEOUT
+    ):
+        """Send command to the device and wait for response.
+
+        This function waits for response message matching a regular
+        expressions.
+
+        Args:
+          cmds: The commands issued, either a list or a string.
+          regex_list: List of Regular expressions used to match response message.
+            Note1, list must be ordered.
+            Note2, empty list sends and returns.
+          timeout: time to wait for matching results before failing.
+
+        Returns:
+          List of tuples, each of which contains the entire matched string and
+          all the subgroups of the match. None if not matched.
+          For example:
+            response of the given command:
+              High temp: 37.2
+              Low temp: 36.4
+            regex_list:
+              ['High temp: (\d+)\.(\d+)', 'Low temp: (\d+)\.(\d+)']
+            returns:
+              [('High temp: 37.2', '37', '2'), ('Low temp: 36.4', '36', '4')]
+
+        Raises:
+          ptyError: If timed out waiting for a response
+        """
+        result_list = []
+        self._open()
         try:
-          self._child.expect(regex, timeout=0.1)
-          match = self._child.match
-          lastindex = match.lastindex if match and match.lastindex else 0
-          # Create a tuple which contains the entire matched string and all
-          # the subgroups of the match.
-          result = match.group(*range(lastindex + 1)) if match else None
-          if result:
-            result = tuple(res.decode('utf-8') for res in result)
-          result_list.append(result)
+            self._send(cmds)
+            for regex in regex_list:
+                self._child.expect(regex, timeout)
+                match = self._child.match
+                lastindex = match.lastindex if match and match.lastindex else 0
+                # Create a tuple which contains the entire matched string and all
+                # the subgroups of the match.
+                result = match.group(*range(lastindex + 1)) if match else None
+                if result:
+                    result = tuple(res.decode("utf-8") for res in result)
+                result_list.append(result)
         except pexpect.TIMEOUT:
-          break
-    finally:
-      self._close()
-    return result_list
-
-  def _Set_uart_timeout(self, timeout):
-    """Set timeout value for waiting for the device response.
-
-    Args:
-      timeout: Timeout value in second.
-    """
-    self._dict['uart_timeout'] = timeout
-
-  def _Get_uart_timeout(self):
-    """Get timeout value for waiting for the device response.
-
-    Returns:
-      Timeout value in second.
-    """
-    return self._dict['uart_timeout']
-
-  def _Set_uart_regexp(self, regexp):
-    """Set the list of regular expressions which matches the command response.
-
-    Args:
-      regexp: A string which contains a list of regular expressions.
-    """
-    if not isinstance(regexp, str):
-      raise ptyError('The argument regexp should be a string.')
-    self._dict['uart_regexp'] = ast.literal_eval(regexp)
-
-  def _Get_uart_regexp(self):
-    """Get the list of regular expressions which matches the command response.
-
-    Returns:
-      A string which contains a list of regular expressions.
-    """
-    return str(self._dict['uart_regexp'])
-
-  def _Set_uart_cmd(self, cmd):
-    """Set the UART command and send it to the device.
-
-    If ec_uart_regexp is 'None', the command is just sent and it doesn't care
-    about its response.
-
-    If ec_uart_regexp is not 'None', the command is send and its response,
-    which matches the regular expression of ec_uart_regexp, will be kept.
-    Use its getter to obtain this result. If no match after ec_uart_timeout
-    seconds, a timeout error will be raised.
-
-    Args:
-      cmd: A string of UART command.
-    """
-    if self._dict['uart_regexp']:
-      self._dict['uart_cmd'] = self._issue_cmd_get_results(
-          cmd, self._dict['uart_regexp'], self._dict['uart_timeout'])
-    else:
-      self._dict['uart_cmd'] = None
-      self._issue_cmd(cmd)
-
-  def _Set_uart_multicmd(self, cmds):
-    """Set multiple UART commands and send them to the device.
-
-    Note that ec_uart_regexp is not supported to match the results.
-
-    Args:
-      cmds: A semicolon-separated string of UART commands.
-    """
-    self._issue_cmd(cmds.split(';'))
-
-  def _Get_uart_cmd(self):
-    """Get the result of the latest UART command.
-
-    Returns:
-      A string which contains a list of tuples, each of which contains the
-      entire matched string and all the subgroups of the match. 'None' if
-      the ec_uart_regexp is 'None'.
-    """
-    return str(self._dict['uart_cmd'])
-
-  def _Set_uart_capture(self, cmd):
-    """Set UART capture mode (on or off).
-
-    Once capture is enabled, UART output could be collected periodically by
-    invoking _Get_uart_stream() below.
-
-    Args:
-      cmd: True for on, False for off
-    """
-    self._interface.set_capture_active(cmd)
-
-  def _Get_uart_capture(self):
-    """Get the UART capture mode (on or off)."""
-    return self._interface.get_capture_active()
-
-  def _Get_uart_stream(self):
-    """Get uart stream generated since last time."""
-    return self._interface.get_stream()
+            raise ptyError("Timeout waiting for response.")
+        finally:
+            if not regex_list:
+                # Must be longer than delaybeforesend
+                time.sleep(0.1)
+            self._close()
+        return result_list
+
+    def _issue_cmd_get_multi_results(self, cmd, regex):
+        """Send command to the device and wait for multiple response.
+
+        This function waits for arbitrary number of response message
+        matching a regular expression.
+
+        Args:
+          cmd: The command issued.
+          regex: Regular expression used to match response message.
+
+        Returns:
+          List of tuples, each of which contains the entire matched string and
+          all the subgroups of the match. None if not matched.
+        """
+        result_list = []
+        self._open()
+        try:
+            self._send(cmd)
+            while True:
+                try:
+                    self._child.expect(regex, timeout=0.1)
+                    match = self._child.match
+                    lastindex = (
+                        match.lastindex if match and match.lastindex else 0
+                    )
+                    # Create a tuple which contains the entire matched string and all
+                    # the subgroups of the match.
+                    result = (
+                        match.group(*range(lastindex + 1)) if match else None
+                    )
+                    if result:
+                        result = tuple(res.decode("utf-8") for res in result)
+                    result_list.append(result)
+                except pexpect.TIMEOUT:
+                    break
+        finally:
+            self._close()
+        return result_list
+
+    def _Set_uart_timeout(self, timeout):
+        """Set timeout value for waiting for the device response.
+
+        Args:
+          timeout: Timeout value in second.
+        """
+        self._dict["uart_timeout"] = timeout
+
+    def _Get_uart_timeout(self):
+        """Get timeout value for waiting for the device response.
+
+        Returns:
+          Timeout value in second.
+        """
+        return self._dict["uart_timeout"]
+
+    def _Set_uart_regexp(self, regexp):
+        """Set the list of regular expressions which matches the command response.
+
+        Args:
+          regexp: A string which contains a list of regular expressions.
+        """
+        if not isinstance(regexp, str):
+            raise ptyError("The argument regexp should be a string.")
+        self._dict["uart_regexp"] = ast.literal_eval(regexp)
+
+    def _Get_uart_regexp(self):
+        """Get the list of regular expressions which matches the command response.
+
+        Returns:
+          A string which contains a list of regular expressions.
+        """
+        return str(self._dict["uart_regexp"])
+
+    def _Set_uart_cmd(self, cmd):
+        """Set the UART command and send it to the device.
+
+        If ec_uart_regexp is 'None', the command is just sent and it doesn't care
+        about its response.
+
+        If ec_uart_regexp is not 'None', the command is send and its response,
+        which matches the regular expression of ec_uart_regexp, will be kept.
+        Use its getter to obtain this result. If no match after ec_uart_timeout
+        seconds, a timeout error will be raised.
+
+        Args:
+          cmd: A string of UART command.
+        """
+        if self._dict["uart_regexp"]:
+            self._dict["uart_cmd"] = self._issue_cmd_get_results(
+                cmd, self._dict["uart_regexp"], self._dict["uart_timeout"]
+            )
+        else:
+            self._dict["uart_cmd"] = None
+            self._issue_cmd(cmd)
+
+    def _Set_uart_multicmd(self, cmds):
+        """Set multiple UART commands and send them to the device.
+
+        Note that ec_uart_regexp is not supported to match the results.
+
+        Args:
+          cmds: A semicolon-separated string of UART commands.
+        """
+        self._issue_cmd(cmds.split(";"))
+
+    def _Get_uart_cmd(self):
+        """Get the result of the latest UART command.
+
+        Returns:
+          A string which contains a list of tuples, each of which contains the
+          entire matched string and all the subgroups of the match. 'None' if
+          the ec_uart_regexp is 'None'.
+        """
+        return str(self._dict["uart_cmd"])
+
+    def _Set_uart_capture(self, cmd):
+        """Set UART capture mode (on or off).
+
+        Once capture is enabled, UART output could be collected periodically by
+        invoking _Get_uart_stream() below.
+
+        Args:
+          cmd: True for on, False for off
+        """
+        self._interface.set_capture_active(cmd)
+
+    def _Get_uart_capture(self):
+        """Get the UART capture mode (on or off)."""
+        return self._interface.get_capture_active()
+
+    def _Get_uart_stream(self):
+        """Get uart stream generated since last time."""
+        return self._interface.get_stream()
diff --git a/extra/tigertool/ecusb/stm32uart.py b/extra/tigertool/ecusb/stm32uart.py
index 95219455a9..64d0234f06 100644
--- a/extra/tigertool/ecusb/stm32uart.py
+++ b/extra/tigertool/ecusb/stm32uart.py
@@ -1,10 +1,6 @@
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
 
 """Allow creation of uart/console interface via stm32 usb endpoint."""
 
@@ -17,232 +13,247 @@ import termios
 import threading
 import time
 import tty
-import usb
+
+import usb  # pylint:disable=import-error
 
 from . import stm32usb
 
 
 class SuartError(Exception):
-  """Class for exceptions of Suart."""
-  def __init__(self, msg, value=0):
-    """SuartError constructor.
+    """Class for exceptions of Suart."""
 
-    Args:
-      msg: string, message describing error in detail
-      value: integer, value of error when non-zero status returned.  Default=0
-    """
-    super(SuartError, self).__init__(msg, value)
-    self.msg = msg
-    self.value = value
+    def __init__(self, msg, value=0):
+        """SuartError constructor.
 
+        Args:
+          msg: string, message describing error in detail
+          value: integer, value of error when non-zero status returned.  Default=0
+        """
+        super(SuartError, self).__init__(msg, value)
+        self.msg = msg
+        self.value = value
 
-class Suart(object):
-  """Provide interface to stm32 serial usb endpoint."""
-  def __init__(self, vendor=0x18d1, product=0x501a, interface=0,
-               serialname=None, debuglog=False):
-    """Suart contstructor.
-
-    Initializes stm32 USB stream interface.
-
-    Args:
-      vendor: usb vendor id of stm32 device
-      product: usb product id of stm32 device
-      interface: interface number of stm32 device to use
-      serialname: serial name to target. Defaults to None.
-      debuglog: chatty output. Defaults to False.
-
-    Raises:
-      SuartError: If init fails
-    """
-    self._ptym = None
-    self._ptys = None
-    self._ptyname = None
-    self._rx_thread = None
-    self._tx_thread = None
-    self._debuglog = debuglog
-    self._susb = stm32usb.Susb(vendor=vendor, product=product,
-                               interface=interface, serialname=serialname)
-    self._running = False
-
-  def __del__(self):
-    """Suart destructor."""
-    self.close()
-
-  def close(self):
-    """Stop all running threads."""
-    self._running = False
-    if self._rx_thread:
-      self._rx_thread.join(2)
-      self._rx_thread = None
-    if self._tx_thread:
-      self._tx_thread.join(2)
-      self._tx_thread = None
-    self._susb.close()
-
-  def run_rx_thread(self):
-    """Background loop to pass data from USB to pty."""
-    ep = select.epoll()
-    ep.register(self._ptym, select.EPOLLHUP)
-    try:
-      while self._running:
-        events = ep.poll(0)
-        # Check if the pty is connected to anything, or hungup.
-        if not events:
-          try:
-            r = self._susb._read_ep.read(64, self._susb.TIMEOUT_MS)
-            if r:
-              if self._debuglog:
-                print(''.join([chr(x) for x in r]), end='')
-              os.write(self._ptym, r)
-
-          # If we miss some characters on pty disconnect, that's fine.
-          # ep.read() also throws USBError on timeout, which we discard.
-          except OSError:
-            pass
-          except usb.core.USBError:
-            pass
-        else:
-          time.sleep(.1)
-    except Exception as e:
-      raise e
-
-  def run_tx_thread(self):
-    """Background loop to pass data from pty to USB."""
-    ep = select.epoll()
-    ep.register(self._ptym, select.EPOLLHUP)
-    try:
-      while self._running:
-        events = ep.poll(0)
-        # Check if the pty is connected to anything, or hungup.
-        if not events:
-          try:
-            r = os.read(self._ptym, 64)
-            # TODO(crosbug.com/936182): Remove when the servo v4/micro console
-            # issues are fixed.
-            time.sleep(0.001)
-            if r:
-              self._susb._write_ep.write(r, self._susb.TIMEOUT_MS)
-
-          except OSError:
-            pass
-          except usb.core.USBError:
-            pass
-        else:
-          time.sleep(.1)
-    except Exception as e:
-      raise e
-
-  def run(self):
-    """Creates pthreads to poll stm32 & PTY for data."""
-    m, s = os.openpty()
-    self._ptyname = os.ttyname(s)
-
-    self._ptym = m
-    self._ptys = s
-
-    os.fchmod(s, 0o660)
-
-    # Change the owner and group of the PTY to the user who started servod.
-    try:
-      uid = int(os.environ.get('SUDO_UID', -1))
-    except TypeError:
-      uid = -1
 
-    try:
-      gid = int(os.environ.get('SUDO_GID', -1))
-    except TypeError:
-      gid = -1
-    os.fchown(s, uid, gid)
-
-    tty.setraw(self._ptym, termios.TCSADRAIN)
-
-    # Generate a HUP flag on pty slave fd.
-    os.fdopen(s).close()
-
-    self._running = True
-
-    self._rx_thread = threading.Thread(target=self.run_rx_thread, args=[])
-    self._rx_thread.daemon = True
-    self._rx_thread.start()
-
-    self._tx_thread = threading.Thread(target=self.run_tx_thread, args=[])
-    self._tx_thread.daemon = True
-    self._tx_thread.start()
-
-  def get_uart_props(self):
-    """Get the uart's properties.
-
-    Returns:
-      dict where:
-        baudrate: integer of uarts baudrate
-        bits: integer, number of bits of data Can be 5|6|7|8 inclusive
-        parity: integer, parity of 0-2 inclusive where:
-          0: no parity
-          1: odd parity
-          2: even parity
-        sbits: integer, number of stop bits.  Can be 0|1|2 inclusive where:
-          0: 1 stop bit
-          1: 1.5 stop bits
-          2: 2 stop bits
-    """
-    return {
-        'baudrate': 115200,
-        'bits': 8,
-        'parity': 0,
-        'sbits': 1,
-    }
-
-  def set_uart_props(self, line_props):
-    """Set the uart's properties.
-
-    Note that Suart cannot set properties
-    and will fail if the properties are not the default 115200,8n1.
-
-    Args:
-      line_props: dict where:
-        baudrate: integer of uarts baudrate
-        bits: integer, number of bits of data ( prior to stop bit)
-        parity: integer, parity of 0-2 inclusive where
-          0: no parity
-          1: odd parity
-          2: even parity
-        sbits: integer, number of stop bits.  Can be 0|1|2 inclusive where:
-          0: 1 stop bit
-          1: 1.5 stop bits
-          2: 2 stop bits
-
-    Raises:
-      SuartError: If requested line properties are not the default.
-    """
-    curr_props = self.get_uart_props()
-    for prop in line_props:
-      if line_props[prop] != curr_props[prop]:
-        raise SuartError('Line property %s cannot be set from %s to %s' % (
-            prop, curr_props[prop], line_props[prop]))
-    return True
-
-  def get_pty(self):
-    """Gets path to pty for communication to/from uart.
-
-    Returns:
-      String path to the pty connected to the uart
-    """
-    return self._ptyname
+class Suart(object):
+    """Provide interface to stm32 serial usb endpoint."""
+
+    def __init__(
+        self,
+        vendor=0x18D1,
+        product=0x501A,
+        interface=0,
+        serialname=None,
+        debuglog=False,
+    ):
+        """Suart contstructor.
+
+        Initializes stm32 USB stream interface.
+
+        Args:
+          vendor: usb vendor id of stm32 device
+          product: usb product id of stm32 device
+          interface: interface number of stm32 device to use
+          serialname: serial name to target. Defaults to None.
+          debuglog: chatty output. Defaults to False.
+
+        Raises:
+          SuartError: If init fails
+        """
+        self._ptym = None
+        self._ptys = None
+        self._ptyname = None
+        self._rx_thread = None
+        self._tx_thread = None
+        self._debuglog = debuglog
+        self._susb = stm32usb.Susb(
+            vendor=vendor,
+            product=product,
+            interface=interface,
+            serialname=serialname,
+        )
+        self._running = False
+
+    def __del__(self):
+        """Suart destructor."""
+        self.close()
+
+    def close(self):
+        """Stop all running threads."""
+        self._running = False
+        if self._rx_thread:
+            self._rx_thread.join(2)
+            self._rx_thread = None
+        if self._tx_thread:
+            self._tx_thread.join(2)
+            self._tx_thread = None
+        self._susb.close()
+
+    def run_rx_thread(self):
+        """Background loop to pass data from USB to pty."""
+        ep = select.epoll()
+        ep.register(self._ptym, select.EPOLLHUP)
+        try:
+            while self._running:
+                events = ep.poll(0)
+                # Check if the pty is connected to anything, or hungup.
+                if not events:
+                    try:
+                        r = self._susb._read_ep.read(64, self._susb.TIMEOUT_MS)
+                        if r:
+                            if self._debuglog:
+                                print("".join([chr(x) for x in r]), end="")
+                            os.write(self._ptym, r)
+
+                    # If we miss some characters on pty disconnect, that's fine.
+                    # ep.read() also throws USBError on timeout, which we discard.
+                    except OSError:
+                        pass
+                    except usb.core.USBError:
+                        pass
+                else:
+                    time.sleep(0.1)
+        except Exception as e:
+            raise e
+
+    def run_tx_thread(self):
+        """Background loop to pass data from pty to USB."""
+        ep = select.epoll()
+        ep.register(self._ptym, select.EPOLLHUP)
+        try:
+            while self._running:
+                events = ep.poll(0)
+                # Check if the pty is connected to anything, or hungup.
+                if not events:
+                    try:
+                        r = os.read(self._ptym, 64)
+                        # TODO(crosbug.com/936182): Remove when the servo v4/micro console
+                        # issues are fixed.
+                        time.sleep(0.001)
+                        if r:
+                            self._susb._write_ep.write(r, self._susb.TIMEOUT_MS)
+
+                    except OSError:
+                        pass
+                    except usb.core.USBError:
+                        pass
+                else:
+                    time.sleep(0.1)
+        except Exception as e:
+            raise e
+
+    def run(self):
+        """Creates pthreads to poll stm32 & PTY for data."""
+        m, s = os.openpty()
+        self._ptyname = os.ttyname(s)
+
+        self._ptym = m
+        self._ptys = s
+
+        os.fchmod(s, 0o660)
+
+        # Change the owner and group of the PTY to the user who started servod.
+        try:
+            uid = int(os.environ.get("SUDO_UID", -1))
+        except TypeError:
+            uid = -1
+
+        try:
+            gid = int(os.environ.get("SUDO_GID", -1))
+        except TypeError:
+            gid = -1
+        os.fchown(s, uid, gid)
+
+        tty.setraw(self._ptym, termios.TCSADRAIN)
+
+        # Generate a HUP flag on pty slave fd.
+        os.fdopen(s).close()
+
+        self._running = True
+
+        self._rx_thread = threading.Thread(target=self.run_rx_thread, args=[])
+        self._rx_thread.daemon = True
+        self._rx_thread.start()
+
+        self._tx_thread = threading.Thread(target=self.run_tx_thread, args=[])
+        self._tx_thread.daemon = True
+        self._tx_thread.start()
+
+    def get_uart_props(self):
+        """Get the uart's properties.
+
+        Returns:
+          dict where:
+            baudrate: integer of uarts baudrate
+            bits: integer, number of bits of data Can be 5|6|7|8 inclusive
+            parity: integer, parity of 0-2 inclusive where:
+              0: no parity
+              1: odd parity
+              2: even parity
+            sbits: integer, number of stop bits.  Can be 0|1|2 inclusive where:
+              0: 1 stop bit
+              1: 1.5 stop bits
+              2: 2 stop bits
+        """
+        return {
+            "baudrate": 115200,
+            "bits": 8,
+            "parity": 0,
+            "sbits": 1,
+        }
+
+    def set_uart_props(self, line_props):
+        """Set the uart's properties.
+
+        Note that Suart cannot set properties
+        and will fail if the properties are not the default 115200,8n1.
+
+        Args:
+          line_props: dict where:
+            baudrate: integer of uarts baudrate
+            bits: integer, number of bits of data ( prior to stop bit)
+            parity: integer, parity of 0-2 inclusive where
+              0: no parity
+              1: odd parity
+              2: even parity
+            sbits: integer, number of stop bits.  Can be 0|1|2 inclusive where:
+              0: 1 stop bit
+              1: 1.5 stop bits
+              2: 2 stop bits
+
+        Raises:
+          SuartError: If requested line properties are not the default.
+        """
+        curr_props = self.get_uart_props()
+        for prop in line_props:
+            if line_props[prop] != curr_props[prop]:
+                raise SuartError(
+                    "Line property %s cannot be set from %s to %s"
+                    % (prop, curr_props[prop], line_props[prop])
+                )
+        return True
+
+    def get_pty(self):
+        """Gets path to pty for communication to/from uart.
+
+        Returns:
+          String path to the pty connected to the uart
+        """
+        return self._ptyname
 
 
 def main():
-  """Run a suart test with the default parameters."""
-  try:
-    sobj = Suart()
-    sobj.run()
+    """Run a suart test with the default parameters."""
+    try:
+        sobj = Suart()
+        sobj.run()
 
-    # run() is a thread so just busy wait to mimic server.
-    while True:
-      # Ours sleeps to eleven!
-      time.sleep(11)
-  except KeyboardInterrupt:
-    sys.exit(0)
+        # run() is a thread so just busy wait to mimic server.
+        while True:
+            # Ours sleeps to eleven!
+            time.sleep(11)
+    except KeyboardInterrupt:
+        sys.exit(0)
 
 
-if __name__ == '__main__':
-  main()
+if __name__ == "__main__":
+    main()
diff --git a/extra/tigertool/ecusb/stm32usb.py b/extra/tigertool/ecusb/stm32usb.py
index bfd5fbb1fb..f9c700466a 100644
--- a/extra/tigertool/ecusb/stm32usb.py
+++ b/extra/tigertool/ecusb/stm32usb.py
@@ -1,119 +1,132 @@
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
 
 """Allows creation of an interface via stm32 usb."""
 
-import usb
+import usb  # pylint:disable=import-error
 
 
 class SusbError(Exception):
-  """Class for exceptions of Susb."""
-  def __init__(self, msg, value=0):
-    """SusbError constructor.
+    """Class for exceptions of Susb."""
 
-    Args:
-      msg: string, message describing error in detail
-      value: integer, value of error when non-zero status returned.  Default=0
-    """
-    super(SusbError, self).__init__(msg, value)
-    self.msg = msg
-    self.value = value
+    def __init__(self, msg, value=0):
+        """SusbError constructor.
+
+        Args:
+          msg: string, message describing error in detail
+          value: integer, value of error when non-zero status returned.  Default=0
+        """
+        super(SusbError, self).__init__(msg, value)
+        self.msg = msg
+        self.value = value
 
 
 class Susb(object):
-  """Provide stm32 USB functionality.
-
-  Instance Variables:
-    _read_ep: pyUSB read endpoint for this interface
-    _write_ep: pyUSB write endpoint for this interface
-  """
-  READ_ENDPOINT = 0x81
-  WRITE_ENDPOINT = 0x1
-  TIMEOUT_MS = 100
-
-  def __init__(self, vendor=0x18d1,
-               product=0x5027, interface=1, serialname=None, logger=None):
-    """Susb constructor.
-
-    Discovers and connects to stm32 USB endpoints.
-
-    Args:
-      vendor: usb vendor id of stm32 device.
-      product: usb product id of stm32 device.
-      interface: interface number ( 1 - 4 ) of stm32 device to use.
-      serialname: string of device serialname.
-      logger: none
-
-    Raises:
-      SusbError: An error accessing Susb object
+    """Provide stm32 USB functionality.
+
+    Instance Variables:
+      _read_ep: pyUSB read endpoint for this interface
+      _write_ep: pyUSB write endpoint for this interface
     """
-    self._vendor = vendor
-    self._product = product
-    self._interface = interface
-    self._serialname = serialname
-    self._find_device()
-
-  def _find_device(self):
-    """Set up the usb endpoint"""
-    # Find the stm32.
-    dev_g = usb.core.find(idVendor=self._vendor, idProduct=self._product,
-                             find_all=True)
-    dev_list = list(dev_g)
-
-    if not dev_list:
-      raise SusbError('USB device not found')
-
-    # Check if we have multiple stm32s and we've specified the serial.
-    dev = None
-    if self._serialname:
-      for d in dev_list:
-        dev_serial = usb.util.get_string(d, d.iSerialNumber)
-        if dev_serial == self._serialname:
-          dev = d
-          break
-      if dev is None:
-        raise SusbError('USB device(%s) not found' % self._serialname)
-    else:
-      try:
-        dev = dev_list[0]
-      except StopIteration:
-        raise SusbError('USB device %04x:%04x not found' % (
-            self._vendor, self._product))
-
-    # If we can't set configuration, it's already been set.
-    try:
-      dev.set_configuration()
-    except usb.core.USBError:
-      pass
-
-    self._dev = dev
-
-    # Get an endpoint instance.
-    cfg = dev.get_active_configuration()
-    intf = usb.util.find_descriptor(cfg, bInterfaceNumber=self._interface)
-    self._intf = intf
-    if not intf:
-      raise SusbError('Interface %04x:%04x - 0x%x not found' % (
-          self._vendor, self._product, self._interface))
-
-    # Detach raiden.ko if it is loaded. CCD endpoints support either a kernel
-    # module driver that produces a ttyUSB, or direct endpoint access, but
-    # can't do both at the same time.
-    if dev.is_kernel_driver_active(intf.bInterfaceNumber) is True:
-      dev.detach_kernel_driver(intf.bInterfaceNumber)
-
-    read_ep_number = intf.bInterfaceNumber + self.READ_ENDPOINT
-    read_ep = usb.util.find_descriptor(intf, bEndpointAddress=read_ep_number)
-    self._read_ep = read_ep
-
-    write_ep_number = intf.bInterfaceNumber + self.WRITE_ENDPOINT
-    write_ep = usb.util.find_descriptor(intf, bEndpointAddress=write_ep_number)
-    self._write_ep = write_ep
-
-  def close(self):
-    usb.util.dispose_resources(self._dev)
+
+    READ_ENDPOINT = 0x81
+    WRITE_ENDPOINT = 0x1
+    TIMEOUT_MS = 100
+
+    def __init__(
+        self,
+        vendor=0x18D1,
+        product=0x5027,
+        interface=1,
+        serialname=None,
+        logger=None,
+    ):
+        """Susb constructor.
+
+        Discovers and connects to stm32 USB endpoints.
+
+        Args:
+          vendor: usb vendor id of stm32 device.
+          product: usb product id of stm32 device.
+          interface: interface number ( 1 - 4 ) of stm32 device to use.
+          serialname: string of device serialname.
+          logger: none
+
+        Raises:
+          SusbError: An error accessing Susb object
+        """
+        self._vendor = vendor
+        self._product = product
+        self._interface = interface
+        self._serialname = serialname
+        self._find_device()
+
+    def _find_device(self):
+        """Set up the usb endpoint"""
+        # Find the stm32.
+        dev_g = usb.core.find(
+            idVendor=self._vendor, idProduct=self._product, find_all=True
+        )
+        dev_list = list(dev_g)
+
+        if not dev_list:
+            raise SusbError("USB device not found")
+
+        # Check if we have multiple stm32s and we've specified the serial.
+        dev = None
+        if self._serialname:
+            for d in dev_list:
+                dev_serial = usb.util.get_string(d, d.iSerialNumber)
+                if dev_serial == self._serialname:
+                    dev = d
+                    break
+            if dev is None:
+                raise SusbError("USB device(%s) not found" % self._serialname)
+        else:
+            try:
+                dev = dev_list[0]
+            except StopIteration:
+                raise SusbError(
+                    "USB device %04x:%04x not found"
+                    % (self._vendor, self._product)
+                )
+
+        # If we can't set configuration, it's already been set.
+        try:
+            dev.set_configuration()
+        except usb.core.USBError:
+            pass
+
+        self._dev = dev
+
+        # Get an endpoint instance.
+        cfg = dev.get_active_configuration()
+        intf = usb.util.find_descriptor(cfg, bInterfaceNumber=self._interface)
+        self._intf = intf
+        if not intf:
+            raise SusbError(
+                "Interface %04x:%04x - 0x%x not found"
+                % (self._vendor, self._product, self._interface)
+            )
+
+        # Detach raiden.ko if it is loaded. CCD endpoints support either a kernel
+        # module driver that produces a ttyUSB, or direct endpoint access, but
+        # can't do both at the same time.
+        if dev.is_kernel_driver_active(intf.bInterfaceNumber) is True:
+            dev.detach_kernel_driver(intf.bInterfaceNumber)
+
+        read_ep_number = intf.bInterfaceNumber + self.READ_ENDPOINT
+        read_ep = usb.util.find_descriptor(
+            intf, bEndpointAddress=read_ep_number
+        )
+        self._read_ep = read_ep
+
+        write_ep_number = intf.bInterfaceNumber + self.WRITE_ENDPOINT
+        write_ep = usb.util.find_descriptor(
+            intf, bEndpointAddress=write_ep_number
+        )
+        self._write_ep = write_ep
+
+    def close(self):
+        usb.util.dispose_resources(self._dev)
diff --git a/extra/tigertool/ecusb/tiny_servo_common.py b/extra/tigertool/ecusb/tiny_servo_common.py
index e27736a9dc..fc028104ed 100644
--- a/extra/tigertool/ecusb/tiny_servo_common.py
+++ b/extra/tigertool/ecusb/tiny_servo_common.py
@@ -1,238 +1,241 @@
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
 
 """Utilities for using lightweight console functions."""
 
 # Note: This is a py2/3 compatible file.
 
 import datetime
-import errno
-import os
-import re
-import subprocess
 import sys
 import time
-import usb
 
 import six
+import usb  # pylint:disable=import-error
 
-from . import pty_driver
-from . import stm32uart
+from . import pty_driver, stm32uart
 
 
 def get_subprocess_args():
-  if six.PY3:
-    return {'encoding': 'utf-8'}
-  return {}
+    if six.PY3:
+        return {"encoding": "utf-8"}
+    return {}
 
 
 class TinyServoError(Exception):
-  """Exceptions."""
+    """Exceptions."""
 
 
 def log(output):
-  """Print output to console, logfiles can be added here.
+    """Print output to console, logfiles can be added here.
+
+    Args:
+      output: string to output.
+    """
+    sys.stdout.write(output)
+    sys.stdout.write("\n")
+    sys.stdout.flush()
 
-  Args:
-    output: string to output.
-  """
-  sys.stdout.write(output)
-  sys.stdout.write('\n')
-  sys.stdout.flush()
 
 def check_usb(vidpid, serialname=None):
-  """Check if |vidpid| is present on the system's USB.
+    """Check if |vidpid| is present on the system's USB.
 
-  Args:
-    vidpid: string representation of the usb vid:pid, eg. '18d1:2001'
-    serialname: serialname if specified.
+    Args:
+      vidpid: string representation of the usb vid:pid, eg. '18d1:2001'
+      serialname: serialname if specified.
 
-  Returns: True if found, False, otherwise.
-  """
-  if serialname:
-    output = subprocess.check_output(['lsusb', '-v', '-d', vidpid],
-                                     **get_subprocess_args())
-    m = re.search(r'^\s*iSerial\s+\d+\s+%s$' % serialname, output, flags=re.M)
-    if m:
-      return True
+    Returns:
+      True if found, False, otherwise.
+    """
+    if get_usb_dev(vidpid, serialname):
+        return True
 
     return False
-  else:
-    if subprocess.call(['lsusb', '-d', vidpid], stdout=open('/dev/null', 'w')):
-      return False
-  return True
-
-def check_usb_sn(vidpid):
-  """Return the serial number
-
-  Return the serial number of the first USB device with VID:PID vidpid,
-  or None if no device is found. This will not work well with two of
-  the same device attached.
 
-  Args:
-    vidpid: string representation of the usb vid:pid, eg. '18d1:2001'
 
-  Returns: string serial number if found, None otherwise.
-  """
-  output = subprocess.check_output(['lsusb', '-v', '-d', vidpid],
-                                   **get_subprocess_args())
-  m = re.search(r'^\s*iSerial\s+(.*)$', output, flags=re.M)
-  if m:
-    return m.group(1)
+def check_usb_sn(vidpid):
+    """Return the serial number
 
-  return None
+    Return the serial number of the first USB device with VID:PID vidpid,
+    or None if no device is found. This will not work well with two of
+    the same device attached.
 
-def get_usb_dev(vidpid, serialname=None):
-  """Return the USB pyusb devie struct
+    Args:
+      vidpid: string representation of the usb vid:pid, eg. '18d1:2001'
 
-  Return the dev struct of the first USB device with VID:PID vidpid,
-  or None if no device is found. If more than one device check serial
-  if supplied.
+    Returns:
+      string serial number if found, None otherwise.
+    """
+    dev = get_usb_dev(vidpid)
 
-  Args:
-    vidpid: string representation of the usb vid:pid, eg. '18d1:2001'
-    serialname: serialname if specified.
+    if dev:
+        dev_serial = usb.util.get_string(dev, dev.iSerialNumber)
 
-  Returns: pyusb device if found, None otherwise.
-  """
-  vidpidst = vidpid.split(':')
-  vid = int(vidpidst[0], 16)
-  pid = int(vidpidst[1], 16)
+        return dev_serial
 
+    return None
 
-  dev_g = usb.core.find(idVendor=vid, idProduct=pid, find_all=True)
-  dev_list = list(dev_g)
 
-  if not dev_list:
-    return None
+def get_usb_dev(vidpid, serialname=None):
+    """Return the USB pyusb devie struct
+
+    Return the dev struct of the first USB device with VID:PID vidpid,
+    or None if no device is found. If more than one device check serial
+    if supplied.
+
+    Args:
+      vidpid: string representation of the usb vid:pid, eg. '18d1:2001'
+      serialname: serialname if specified.
+
+    Returns:
+      pyusb device if found, None otherwise.
+    """
+    vidpidst = vidpid.split(":")
+    vid = int(vidpidst[0], 16)
+    pid = int(vidpidst[1], 16)
+
+    dev_g = usb.core.find(idVendor=vid, idProduct=pid, find_all=True)
+    dev_list = list(dev_g)
+
+    if not dev_list:
+        return None
+
+    # Check if we have multiple devices and we've specified the serial.
+    dev = None
+    if serialname:
+        for d in dev_list:
+            dev_serial = usb.util.get_string(d, d.iSerialNumber)
+            if dev_serial == serialname:
+                dev = d
+                break
+        if dev is None:
+            return None
+    else:
+        try:
+            dev = dev_list[0]
+        except StopIteration:
+            return None
+
+    return dev
 
-  # Check if we have multiple devices and we've specified the serial.
-  dev = None
-  if serialname:
-    for d in dev_list:
-      dev_serial = usb.util.get_string(d, d.iSerialNumber)
-      if dev_serial == serialname:
-        dev = d
-        break
-    if dev is None:
-      return None
-  else:
-    try:
-      dev = dev_list[0]
-    except StopIteration:
-      return None
-
-  return dev
 
 def check_usb_dev(vidpid, serialname=None):
-  """Return the USB dev number
+    """Return the USB dev number
 
-  Return the dev number of the first USB device with VID:PID vidpid,
-  or None if no device is found. If more than one device check serial
-  if supplied.
+    Return the dev number of the first USB device with VID:PID vidpid,
+    or None if no device is found. If more than one device check serial
+    if supplied.
 
-  Args:
-    vidpid: string representation of the usb vid:pid, eg. '18d1:2001'
-    serialname: serialname if specified.
+    Args:
+      vidpid: string representation of the usb vid:pid, eg. '18d1:2001'
+      serialname: serialname if specified.
 
-  Returns: usb device number if found, None otherwise.
-  """
-  dev = get_usb_dev(vidpid, serialname=serialname)
+    Returns:
+      usb device number if found, None otherwise.
+    """
+    dev = get_usb_dev(vidpid, serialname=serialname)
 
-  if dev:
-    return dev.address
+    if dev:
+        return dev.address
 
-  return None
+    return None
 
 
 def wait_for_usb_remove(vidpid, serialname=None, timeout=None):
-  """Wait for USB device with vidpid to be removed.
+    """Wait for USB device with vidpid to be removed.
+
+    Wrapper for wait_for_usb below
+    """
+    wait_for_usb(
+        vidpid, serialname=serialname, timeout=timeout, desiredpresence=False
+    )
 
-  Wrapper for wait_for_usb below
-  """
-  wait_for_usb(vidpid, serialname=serialname,
-               timeout=timeout, desiredpresence=False)
 
 def wait_for_usb(vidpid, serialname=None, timeout=None, desiredpresence=True):
-  """Wait for usb device with vidpid to be present/absent.
-
-  Args:
-    vidpid: string representation of the usb vid:pid, eg. '18d1:2001'
-    serialname: serialname if specificed.
-    timeout: timeout in seconds, None for no timeout.
-    desiredpresence: True for present, False for not present.
-
-  Raises:
-    TinyServoError: on timeout.
-  """
-  if timeout:
-    finish = datetime.datetime.now() + datetime.timedelta(seconds=timeout)
-  while check_usb(vidpid, serialname) != desiredpresence:
-    time.sleep(.01)
+    """Wait for usb device with vidpid to be present/absent.
+
+    Args:
+      vidpid: string representation of the usb vid:pid, eg. '18d1:2001'
+      serialname: serialname if specificed.
+      timeout: timeout in seconds, None for no timeout.
+      desiredpresence: True for present, False for not present.
+
+    Raises:
+      TinyServoError: on timeout.
+    """
     if timeout:
-      if datetime.datetime.now() > finish:
-        raise TinyServoError('Timeout', 'Timeout waiting for USB %s' % vidpid)
+        finish = datetime.datetime.now() + datetime.timedelta(seconds=timeout)
+    while check_usb(vidpid, serialname) != desiredpresence:
+        time.sleep(0.1)
+        if timeout:
+            if datetime.datetime.now() > finish:
+                raise TinyServoError(
+                    "Timeout", "Timeout waiting for USB %s" % vidpid
+                )
+
 
 def do_serialno(serialno, pty):
-  """Set serialnumber 'serialno' via ec console 'pty'.
-
-  Commands are:
-  # > serialno set 1234
-  # Saving serial number
-  # Serial number: 1234
-
-  Args:
-    serialno: string serial number to set.
-    pty: tinyservo console to send commands.
-
-  Raises:
-    TinyServoError: on failure to set.
-    ptyError: on command interface error.
-  """
-  cmd = 'serialno set %s' % serialno
-  regex = 'Serial number:\s+(\S+)'
-
-  results = pty._issue_cmd_get_results(cmd, [regex])[0]
-  sn = results[1].strip().strip('\n\r')
-
-  if sn == serialno:
-    log('Success !')
-    log('Serial set to %s' % sn)
-  else:
-    log('Serial number set to %s but saved as %s.' % (serialno, sn))
-    raise TinyServoError(
-        'Serial Number',
-        'Serial number set to %s but saved as %s.' % (serialno, sn))
+    """Set serialnumber 'serialno' via ec console 'pty'.
+
+    Commands are:
+    # > serialno set 1234
+    # Saving serial number
+    # Serial number: 1234
+
+    Args:
+      serialno: string serial number to set.
+      pty: tinyservo console to send commands.
+
+    Raises:
+      TinyServoError: on failure to set.
+      ptyError: on command interface error.
+    """
+    cmd = r"serialno set %s" % serialno
+    regex = r"Serial number:\s+(\S+)"
+
+    results = pty._issue_cmd_get_results(cmd, [regex])[0]
+    sn = results[1].strip().strip("\n\r")
+
+    if sn == serialno:
+        log("Success !")
+        log("Serial set to %s" % sn)
+    else:
+        log("Serial number set to %s but saved as %s." % (serialno, sn))
+        raise TinyServoError(
+            "Serial Number",
+            "Serial number set to %s but saved as %s." % (serialno, sn),
+        )
+
 
 def setup_tinyservod(vidpid, interface, serialname=None, debuglog=False):
-  """Set up a pty
-
-  Set up a pty to the ec console in order
-  to send commands. Returns a pty_driver object.
-
-  Args:
-    vidpid: string vidpid of device to access.
-    interface: not used.
-    serialname: string serial name of device requested, optional.
-    debuglog: chatty printout (boolean)
-
-  Returns: pty object
-
-  Raises:
-    UsbError, SusbError: on device not found
-  """
-  vidstr, pidstr = vidpid.split(':')
-  vid = int(vidstr, 16)
-  pid = int(pidstr, 16)
-  suart = stm32uart.Suart(vendor=vid, product=pid,
-                          interface=interface, serialname=serialname,
-                          debuglog=debuglog)
-  suart.run()
-  pty = pty_driver.ptyDriver(suart, [])
-
-  return pty
+    """Set up a pty
+
+    Set up a pty to the ec console in order
+    to send commands. Returns a pty_driver object.
+
+    Args:
+      vidpid: string vidpid of device to access.
+      interface: not used.
+      serialname: string serial name of device requested, optional.
+      debuglog: chatty printout (boolean)
+
+    Returns:
+      pty object
+
+    Raises:
+      UsbError, SusbError: on device not found
+    """
+    vidstr, pidstr = vidpid.split(":")
+    vid = int(vidstr, 16)
+    pid = int(pidstr, 16)
+    suart = stm32uart.Suart(
+        vendor=vid,
+        product=pid,
+        interface=interface,
+        serialname=serialname,
+        debuglog=debuglog,
+    )
+    suart.run()
+    pty = pty_driver.ptyDriver(suart, [])
+
+    return pty
diff --git a/extra/tigertool/ecusb/tiny_servod.py b/extra/tigertool/ecusb/tiny_servod.py
index 632d9c3a20..f8d61b5305 100644
--- a/extra/tigertool/ecusb/tiny_servod.py
+++ b/extra/tigertool/ecusb/tiny_servod.py
@@ -1,54 +1,51 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
 
 """Helper class to facilitate communication to servo ec console."""
 
-from ecusb import pty_driver
-from ecusb import stm32uart
+from ecusb import pty_driver, stm32uart
 
 
 class TinyServod(object):
-  """Helper class to wrap a pty_driver with interface."""
-
-  def __init__(self, vid, pid, interface, serialname=None, debug=False):
-    """Build the driver and interface.
-
-    Args:
-      vid: servo device vid
-      pid: servo device pid
-      interface: which usb interface the servo console is on
-      serialname: the servo device serial (if available)
-    """
-    self._vid = vid
-    self._pid = pid
-    self._interface = interface
-    self._serial = serialname
-    self._debug = debug
-    self._init()
-
-  def _init(self):
-    self.suart = stm32uart.Suart(vendor=self._vid,
-                                 product=self._pid,
-                                 interface=self._interface,
-                                 serialname=self._serial,
-                                 debuglog=self._debug)
-    self.suart.run()
-    self.pty = pty_driver.ptyDriver(self.suart, [])
-
-  def reinitialize(self):
-    """Reinitialize the connect after a reset/disconnect/etc."""
-    self.close()
-    self._init()
-
-  def close(self):
-    """Close out the connection and release resources.
-
-    Note: if another TinyServod process or servod itself needs the same device
-          it's necessary to call this to ensure the usb device is available.
-    """
-    self.suart.close()
+    """Helper class to wrap a pty_driver with interface."""
+
+    def __init__(self, vid, pid, interface, serialname=None, debug=False):
+        """Build the driver and interface.
+
+        Args:
+          vid: servo device vid
+          pid: servo device pid
+          interface: which usb interface the servo console is on
+          serialname: the servo device serial (if available)
+        """
+        self._vid = vid
+        self._pid = pid
+        self._interface = interface
+        self._serial = serialname
+        self._debug = debug
+        self._init()
+
+    def _init(self):
+        self.suart = stm32uart.Suart(
+            vendor=self._vid,
+            product=self._pid,
+            interface=self._interface,
+            serialname=self._serial,
+            debuglog=self._debug,
+        )
+        self.suart.run()
+        self.pty = pty_driver.ptyDriver(self.suart, [])
+
+    def reinitialize(self):
+        """Reinitialize the connect after a reset/disconnect/etc."""
+        self.close()
+        self._init()
+
+    def close(self):
+        """Close out the connection and release resources.
+
+        Note: if another TinyServod process or servod itself needs the same device
+              it's necessary to call this to ensure the usb device is available.
+        """
+        self.suart.close()
diff --git a/extra/tigertool/flash_dfu.sh b/extra/tigertool/flash_dfu.sh
index 7aa6c24f09..9578ef626e 100755
--- a/extra/tigertool/flash_dfu.sh
+++ b/extra/tigertool/flash_dfu.sh
@@ -1,5 +1,5 @@
 #!/bin/bash
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/extra/tigertool/make_pkg.sh b/extra/tigertool/make_pkg.sh
index 5a63862242..ae0ae95cfe 100755
--- a/extra/tigertool/make_pkg.sh
+++ b/extra/tigertool/make_pkg.sh
@@ -1,8 +1,10 @@
 #!/bin/bash
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
+set -e
+
 # Make sure we are in the correct dir.
 cd "$( dirname "${BASH_SOURCE[0]}" )" || exit
 
@@ -21,10 +23,11 @@ cp tigertest.py "${DEST}"
 cp README.md "${DEST}"
 
 cp -r ecusb "${DEST}"
-cp -r ../../../../../chroot/usr/lib64/python2.7/site-packages/usb "${DEST}"
+# Not compatible with glinux as of 4/28/2022.
+# cp -r ../../../../../chroot/usr/lib64/python3.6/site-packages/usb "${DEST}"
 find "${DEST}" -name "*.py[co]" -delete
 cp -r ../usb_serial "${DEST}"
 
-(cd build; tar -czf tigertool_${DATE}.tgz tigertool)
+(cd build && tar -czf tigertool_"${DATE}".tgz tigertool)
 
 echo "Done packaging tigertool_${DATE}.tgz"
diff --git a/extra/tigertool/tigertest.py b/extra/tigertool/tigertest.py
index 0cd31c8cce..b1186cca77 100755
--- a/extra/tigertool/tigertest.py
+++ b/extra/tigertool/tigertest.py
@@ -1,11 +1,7 @@
 #!/usr/bin/env python3
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
 
 """Smoke test of tigertool binary."""
 
@@ -13,7 +9,6 @@ import argparse
 import subprocess
 import sys
 
-
 # Script to control tigertail USB-C Mux board.
 #
 # optional arguments:
@@ -35,58 +30,62 @@ import sys
 
 
 def testCmd(cmd, expected_results):
-  """Run command on console, check for success.
-
-  Args:
-    cmd: shell command to run.
-    expected_results: a list object of strings expected in the result.
-
-  Raises:
-    Exception on fail.
-  """
-  print('run: ' + cmd)
-  try:
-    p = subprocess.run(cmd, shell=True, check=False, capture_output=True)
-    output = p.stdout.decode('utf-8')
-    error = p.stderr.decode('utf-8')
-    assert p.returncode == 0
-    for result in expected_results:
-      output.index(result)
-  except Exception as e:
-    print('FAIL')
-    print('cmd: ' + cmd)
-    print('error: ' + str(e))
-    print('stdout:\n' + output)
-    print('stderr:\n' + error)
-    print('expected: ' + str(expected_results))
-    print('RC: ' + str(p.returncode))
-    raise e
+    """Run command on console, check for success.
+
+    Args:
+      cmd: shell command to run.
+      expected_results: a list object of strings expected in the result.
+
+    Raises:
+      Exception on fail.
+    """
+    print("run: " + cmd)
+    try:
+        p = subprocess.run(cmd, shell=True, check=False, capture_output=True)
+        output = p.stdout.decode("utf-8")
+        error = p.stderr.decode("utf-8")
+        assert p.returncode == 0
+        for result in expected_results:
+            output.index(result)
+    except Exception as e:
+        print("FAIL")
+        print("cmd: " + cmd)
+        print("error: " + str(e))
+        print("stdout:\n" + output)
+        print("stderr:\n" + error)
+        print("expected: " + str(expected_results))
+        print("RC: " + str(p.returncode))
+        raise e
+
 
 def test_sequence():
-  testCmd('./tigertool.py --reboot', ['PASS'])
-  testCmd('./tigertool.py --setserialno test', ['PASS'])
-  testCmd('./tigertool.py --check_serial', ['test', 'PASS'])
-  testCmd('./tigertool.py -s test --check_serial', ['test', 'PASS'])
-  testCmd('./tigertool.py -m A', ['Mux set to A', 'PASS'])
-  testCmd('./tigertool.py -m B', ['Mux set to B', 'PASS'])
-  testCmd('./tigertool.py -m off', ['Mux set to off', 'PASS'])
-  testCmd('./tigertool.py -p', ['PASS'])
-  testCmd('./tigertool.py -r rw', ['PASS'])
-  testCmd('./tigertool.py -r ro', ['PASS'])
-  testCmd('./tigertool.py --check_version', ['RW', 'RO', 'PASS'])
-
-  print('PASS')
+    testCmd("./tigertool.py --reboot", ["PASS"])
+    testCmd("./tigertool.py --setserialno test", ["PASS"])
+    testCmd("./tigertool.py --check_serial", ["test", "PASS"])
+    testCmd("./tigertool.py -s test --check_serial", ["test", "PASS"])
+    testCmd("./tigertool.py -m A", ["Mux set to A", "PASS"])
+    testCmd("./tigertool.py -m B", ["Mux set to B", "PASS"])
+    testCmd("./tigertool.py -m off", ["Mux set to off", "PASS"])
+    testCmd("./tigertool.py -p", ["PASS"])
+    testCmd("./tigertool.py -r rw", ["PASS"])
+    testCmd("./tigertool.py -r ro", ["PASS"])
+    testCmd("./tigertool.py --check_version", ["RW", "RO", "PASS"])
+
+    print("PASS")
+
 
 def main(argv):
-  parser = argparse.ArgumentParser(description=__doc__)
-  parser.add_argument('-c', '--count', type=int, default=1,
-                      help='loops to run')
+    parser = argparse.ArgumentParser(description=__doc__)
+    parser.add_argument(
+        "-c", "--count", type=int, default=1, help="loops to run"
+    )
+
+    opts = parser.parse_args(argv)
 
-  opts = parser.parse_args(argv)
+    for i in range(1, opts.count + 1):
+        print("Iteration: %d" % i)
+        test_sequence()
 
-  for i in range(1, opts.count + 1):
-    print('Iteration: %d' % i)
-    test_sequence()
 
-if __name__ == '__main__':
+if __name__ == "__main__":
     main(sys.argv[1:])
diff --git a/extra/tigertool/tigertool.py b/extra/tigertool/tigertool.py
index 6baae8abdf..69303aa02a 100755
--- a/extra/tigertool/tigertool.py
+++ b/extra/tigertool/tigertool.py
@@ -1,11 +1,7 @@
 #!/usr/bin/env python3
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
 
 """Script to control tigertail USB-C Mux board."""
 
@@ -17,287 +13,318 @@ import time
 
 import ecusb.tiny_servo_common as c
 
-STM_VIDPID = '18d1:5027'
-serialno = 'Uninitialized'
+STM_VIDPID = "18d1:5027"
+serialno = "Uninitialized"
+
 
 def do_mux(mux, pty):
-  """Set mux via ec console 'pty'.
+    """Set mux via ec console 'pty'.
+
+    Args:
+      mux: mux to connect to DUT, 'A', 'B', or 'off'
+      pty: a pty object connected to tigertail
 
-  Args:
-    mux: mux to connect to DUT, 'A', 'B', or 'off'
-    pty: a pty object connected to tigertail
+    Commands are:
+    # > mux A
+    # TYPE-C mux is A
+    """
+    validmux = ["A", "B", "off"]
+    if mux not in validmux:
+        c.log("Mux setting %s invalid, try one of %s" % (mux, validmux))
+        return False
 
-  Commands are:
-  # > mux A
-  # TYPE-C mux is A
-  """
-  validmux = ['A', 'B', 'off']
-  if mux not in validmux:
-    c.log('Mux setting %s invalid, try one of %s' % (mux, validmux))
-    return False
+    cmd = "mux %s" % mux
+    regex = "TYPE\-C mux is ([^\s\r\n]*)\r"
 
-  cmd = 'mux %s' % mux
-  regex = 'TYPE\-C mux is ([^\s\r\n]*)\r'
+    results = pty._issue_cmd_get_results(cmd, [regex])[0]
+    result = results[1].strip().strip("\n\r")
 
-  results = pty._issue_cmd_get_results(cmd, [regex])[0]
-  result = results[1].strip().strip('\n\r')
+    if result != mux:
+        c.log("Mux set to %s but saved as %s." % (mux, result))
+        return False
+    c.log("Mux set to %s" % result)
+    return True
 
-  if result != mux:
-    c.log('Mux set to %s but saved as %s.' % (mux, result))
-    return False
-  c.log('Mux set to %s' % result)
-  return True
 
 def do_version(pty):
-  """Check version via ec console 'pty'.
-
-  Args:
-    pty: a pty object connected to tigertail
-
-  Commands are:
-  # > version
-  # Chip:    stm stm32f07x
-  # Board:   0
-  # RO:      tigertail_v1.1.6749-74d1a312e
-  # RW:      tigertail_v1.1.6749-74d1a312e
-  # Build:   tigertail_v1.1.6749-74d1a312e
-  #          2017-07-25 20:08:34 nsanders@meatball.mtv.corp.google.com
-  """
-  cmd = 'version'
-  regex = r'RO:\s+(\S+)\s+RW:\s+(\S+)\s+Build:\s+(\S+)\s+' \
-          r'(\d\d\d\d-\d\d-\d\d \d\d:\d\d:\d\d) (\S+)'
-
-  results = pty._issue_cmd_get_results(cmd, [regex])[0]
-  c.log('Version is %s' % results[3])
-  c.log('RO:    %s' % results[1])
-  c.log('RW:    %s' % results[2])
-  c.log('Date:  %s' % results[4])
-  c.log('Src:   %s' % results[5])
-
-  return True
+    """Check version via ec console 'pty'.
+
+    Args:
+      pty: a pty object connected to tigertail
+
+    Commands are:
+    # > version
+    # Chip:    stm stm32f07x
+    # Board:   0
+    # RO:      tigertail_v1.1.6749-74d1a312e
+    # RW:      tigertail_v1.1.6749-74d1a312e
+    # Build:   tigertail_v1.1.6749-74d1a312e
+    #          2017-07-25 20:08:34 nsanders@meatball.mtv.corp.google.com
+    """
+    cmd = "version"
+    regex = (
+        r"RO:\s+(\S+)\s+RW:\s+(\S+)\s+Build:\s+(\S+)\s+"
+        r"(\d\d\d\d-\d\d-\d\d \d\d:\d\d:\d\d) (\S+)"
+    )
+
+    results = pty._issue_cmd_get_results(cmd, [regex])[0]
+    c.log("Version is %s" % results[3])
+    c.log("RO:    %s" % results[1])
+    c.log("RW:    %s" % results[2])
+    c.log("Date:  %s" % results[4])
+    c.log("Src:   %s" % results[5])
+
+    return True
+
 
 def do_check_serial(pty):
-  """Check serial via ec console 'pty'.
+    """Check serial via ec console 'pty'.
 
-  Args:
-    pty: a pty object connected to tigertail
+    Args:
+      pty: a pty object connected to tigertail
 
-  Commands are:
-  # > serialno
-  # Serial number: number
-  """
-  cmd = 'serialno'
-  regex = r'Serial number: ([^\n\r]+)'
+    Commands are:
+    # > serialno
+    # Serial number: number
+    """
+    cmd = "serialno"
+    regex = r"Serial number: ([^\n\r]+)"
 
-  results = pty._issue_cmd_get_results(cmd, [regex])[0]
-  c.log('Serial is %s' % results[1])
+    results = pty._issue_cmd_get_results(cmd, [regex])[0]
+    c.log("Serial is %s" % results[1])
 
-  return True
+    return True
 
 
 def do_power(count, bus, pty):
-  """Check power usage via ec console 'pty'.
-
-  Args:
-    count: number of samples to capture
-    bus: rail to monitor, 'vbus', 'cc1', or 'cc2'
-    pty: a pty object connected to tigertail
-
-  Commands are:
-  # > ina 0
-  # Configuration: 4127
-  # Shunt voltage: 02c4 => 1770 uV
-  # Bus voltage  : 1008 => 5130 mV
-  # Power        : 0019 => 625 mW
-  # Current      : 0082 => 130 mA
-  # Calibration  : 0155
-  # Mask/Enable  : 0008
-  # Alert limit  : 0000
-  """
-  if bus == 'vbus':
-    ina = 0
-  if bus == 'cc1':
-    ina = 4
-  if bus == 'cc2':
-    ina = 1
-
-  start = time.time()
-
-  c.log('time,\tmV,\tmW,\tmA')
-
-  cmd = 'ina %s' % ina
-  regex = r'Bus voltage  : \S+ \S+ (\d+) mV\s+' \
-          r'Power        : \S+ \S+ (\d+) mW\s+' \
-          r'Current      : \S+ \S+ (\d+) mA'
-
-  for i in range(0, count):
-    results = pty._issue_cmd_get_results(cmd, [regex])[0]
-    c.log('%.2f,\t%s,\t%s\t%s' % (
-        time.time() - start,
-        results[1], results[2], results[3]))
+    """Check power usage via ec console 'pty'.
+
+    Args:
+      count: number of samples to capture
+      bus: rail to monitor, 'vbus', 'cc1', or 'cc2'
+      pty: a pty object connected to tigertail
+
+    Commands are:
+    # > ina 0
+    # Configuration: 4127
+    # Shunt voltage: 02c4 => 1770 uV
+    # Bus voltage  : 1008 => 5130 mV
+    # Power        : 0019 => 625 mW
+    # Current      : 0082 => 130 mA
+    # Calibration  : 0155
+    # Mask/Enable  : 0008
+    # Alert limit  : 0000
+    """
+    if bus == "vbus":
+        ina = 0
+    if bus == "cc1":
+        ina = 4
+    if bus == "cc2":
+        ina = 1
+
+    start = time.time()
+
+    c.log("time,\tmV,\tmW,\tmA")
+
+    cmd = "ina %s" % ina
+    regex = (
+        r"Bus voltage  : \S+ \S+ (\d+) mV\s+"
+        r"Power        : \S+ \S+ (\d+) mW\s+"
+        r"Current      : \S+ \S+ (\d+) mA"
+    )
+
+    for i in range(0, count):
+        results = pty._issue_cmd_get_results(cmd, [regex])[0]
+        c.log(
+            "%.2f,\t%s,\t%s\t%s"
+            % (time.time() - start, results[1], results[2], results[3])
+        )
+
+    return True
 
-  return True
 
 def do_reboot(pty, serialname):
-  """Reboot via ec console pty
-
-  Args:
-    pty: a pty object connected to tigertail
-    serialname: serial name, can be None.
-
-  Command is: reboot.
-  """
-  cmd = 'reboot'
-
-  # Check usb dev number on current instance.
-  devno = c.check_usb_dev(STM_VIDPID, serialname=serialname)
-  if not devno:
-    c.log('Device not found')
-    return False
-
-  try:
-    pty._issue_cmd(cmd)
-  except Exception as e:
-    c.log('Failed to send command: ' + str(e))
-    return False
-
-  try:
-    c.wait_for_usb_remove(STM_VIDPID, timeout=3., serialname=serialname)
-  except Exception as e:
-    # Polling for reboot isn't reliable but if it hasn't happened in 3 seconds
-    # it's not going to. This step just goes faster if it's detected.
-    pass
-
-  try:
-    c.wait_for_usb(STM_VIDPID, timeout=3., serialname=serialname)
-  except Exception as e:
-    c.log('Failed to return from reboot: ' + str(e))
-    return False
-
-  # Check that the device had a new device number, i.e. it's
-  # disconnected and reconnected.
-  newdevno = c.check_usb_dev(STM_VIDPID, serialname=serialname)
-  if newdevno == devno:
-    c.log("Device didn't reboot")
-    return False
-
-  return True
+    """Reboot via ec console pty
+
+    Args:
+      pty: a pty object connected to tigertail
+      serialname: serial name, can be None.
+
+    Command is: reboot.
+    """
+    cmd = "reboot"
+
+    # Check usb dev number on current instance.
+    devno = c.check_usb_dev(STM_VIDPID, serialname=serialname)
+    if not devno:
+        c.log("Device not found")
+        return False
+
+    try:
+        pty._issue_cmd(cmd)
+    except Exception as e:
+        c.log("Failed to send command: " + str(e))
+        return False
+
+    try:
+        c.wait_for_usb_remove(STM_VIDPID, timeout=3.0, serialname=serialname)
+    except Exception as e:
+        # Polling for reboot isn't reliable but if it hasn't happened in 3 seconds
+        # it's not going to. This step just goes faster if it's detected.
+        pass
+
+    try:
+        c.wait_for_usb(STM_VIDPID, timeout=3.0, serialname=serialname)
+    except Exception as e:
+        c.log("Failed to return from reboot: " + str(e))
+        return False
+
+    # Check that the device had a new device number, i.e. it's
+    # disconnected and reconnected.
+    newdevno = c.check_usb_dev(STM_VIDPID, serialname=serialname)
+    if newdevno == devno:
+        c.log("Device didn't reboot")
+        return False
+
+    return True
+
 
 def do_sysjump(region, pty, serialname):
-  """Set region via ec console 'pty'.
-
-  Args:
-    region: ec code region to execute, 'ro' or 'rw'
-    pty: a pty object connected to tigertail
-    serialname: serial name, can be None.
-
-  Commands are:
-  # > sysjump rw
-  """
-  validregion = ['ro', 'rw']
-  if region not in validregion:
-    c.log('Region setting %s invalid, try one of %s' % (
-        region, validregion))
-    return False
-
-  cmd = 'sysjump %s' % region
-  try:
-    pty._issue_cmd(cmd)
-  except Exception as e:
-    c.log('Exception: ' + str(e))
-    return False
-
-  try:
-    c.wait_for_usb_remove(STM_VIDPID, timeout=3., serialname=serialname)
-  except Exception as e:
-    # Polling for reboot isn't reliable but if it hasn't happened in 3 seconds
-    # it's not going to. This step just goes faster if it's detected.
-    pass
-
-  try:
-    c.wait_for_usb(STM_VIDPID, timeout=3., serialname=serialname)
-  except Exception as e:
-    c.log('Failed to return from restart: ' + str(e))
-    return False
-
-  c.log('Region requested %s' % region)
-  return True
+    """Set region via ec console 'pty'.
+
+    Args:
+      region: ec code region to execute, 'ro' or 'rw'
+      pty: a pty object connected to tigertail
+      serialname: serial name, can be None.
+
+    Commands are:
+    # > sysjump rw
+    """
+    validregion = ["ro", "rw"]
+    if region not in validregion:
+        c.log(
+            "Region setting %s invalid, try one of %s" % (region, validregion)
+        )
+        return False
+
+    cmd = "sysjump %s" % region
+    try:
+        pty._issue_cmd(cmd)
+    except Exception as e:
+        c.log("Exception: " + str(e))
+        return False
+
+    try:
+        c.wait_for_usb_remove(STM_VIDPID, timeout=3.0, serialname=serialname)
+    except Exception as e:
+        # Polling for reboot isn't reliable but if it hasn't happened in 3 seconds
+        # it's not going to. This step just goes faster if it's detected.
+        pass
+
+    try:
+        c.wait_for_usb(STM_VIDPID, timeout=3.0, serialname=serialname)
+    except Exception as e:
+        c.log("Failed to return from restart: " + str(e))
+        return False
+
+    c.log("Region requested %s" % region)
+    return True
+
 
 def get_parser():
-  parser = argparse.ArgumentParser(
-      description=__doc__)
-  parser.add_argument('-s', '--serialno', type=str, default=None,
-                      help='serial number of board to use')
-  parser.add_argument('-b', '--bus', type=str, default='vbus',
-                      help='Which rail to log: [vbus|cc1|cc2]')
-  group = parser.add_mutually_exclusive_group()
-  group.add_argument('--setserialno', type=str, default=None,
-                     help='serial number to set on the board.')
-  group.add_argument('--check_serial', action='store_true',
-                     help='check serial number set on the board.')
-  group.add_argument('-m', '--mux', type=str, default=None,
-                     help='mux selection')
-  group.add_argument('-p', '--power', action='store_true',
-                     help='check VBUS')
-  group.add_argument('-l', '--powerlog', type=int, default=None,
-                     help='log VBUS')
-  group.add_argument('-r', '--sysjump', type=str, default=None,
-                     help='region selection')
-  group.add_argument('--reboot', action='store_true',
-                     help='reboot tigertail')
-  group.add_argument('--check_version', action='store_true',
-                     help='check tigertail version')
-  return parser
+    parser = argparse.ArgumentParser(description=__doc__)
+    parser.add_argument(
+        "-s",
+        "--serialno",
+        type=str,
+        default=None,
+        help="serial number of board to use",
+    )
+    parser.add_argument(
+        "-b",
+        "--bus",
+        type=str,
+        default="vbus",
+        help="Which rail to log: [vbus|cc1|cc2]",
+    )
+    group = parser.add_mutually_exclusive_group()
+    group.add_argument(
+        "--setserialno",
+        type=str,
+        default=None,
+        help="serial number to set on the board.",
+    )
+    group.add_argument(
+        "--check_serial",
+        action="store_true",
+        help="check serial number set on the board.",
+    )
+    group.add_argument(
+        "-m", "--mux", type=str, default=None, help="mux selection"
+    )
+    group.add_argument("-p", "--power", action="store_true", help="check VBUS")
+    group.add_argument(
+        "-l", "--powerlog", type=int, default=None, help="log VBUS"
+    )
+    group.add_argument(
+        "-r", "--sysjump", type=str, default=None, help="region selection"
+    )
+    group.add_argument("--reboot", action="store_true", help="reboot tigertail")
+    group.add_argument(
+        "--check_version", action="store_true", help="check tigertail version"
+    )
+    return parser
+
 
 def main(argv):
-  parser = get_parser()
-  opts = parser.parse_args(argv)
+    parser = get_parser()
+    opts = parser.parse_args(argv)
 
-  result = True
+    result = True
 
-  # Let's make sure there's a tigertail
-  # If nothing found in 5 seconds, fail.
-  c.wait_for_usb(STM_VIDPID, timeout=5., serialname=opts.serialno)
+    # Let's make sure there's a tigertail
+    # If nothing found in 5 seconds, fail.
+    c.wait_for_usb(STM_VIDPID, timeout=5.0, serialname=opts.serialno)
 
-  pty = c.setup_tinyservod(STM_VIDPID, 0, serialname=opts.serialno)
+    pty = c.setup_tinyservod(STM_VIDPID, 0, serialname=opts.serialno)
 
-  if opts.bus not in ('vbus', 'cc1', 'cc2'):
-    c.log('Try --bus [vbus|cc1|cc2]')
-    result = False
+    if opts.bus not in ("vbus", "cc1", "cc2"):
+        c.log("Try --bus [vbus|cc1|cc2]")
+        result = False
 
-  elif opts.setserialno:
-    try:
-      c.do_serialno(opts.setserialno, pty)
-    except Exception:
-      result = False
+    elif opts.setserialno:
+        try:
+            c.do_serialno(opts.setserialno, pty)
+        except Exception:
+            result = False
 
-  elif opts.mux:
-    result &= do_mux(opts.mux, pty)
+    elif opts.mux:
+        result &= do_mux(opts.mux, pty)
 
-  elif opts.sysjump:
-    result &= do_sysjump(opts.sysjump, pty, serialname=opts.serialno)
+    elif opts.sysjump:
+        result &= do_sysjump(opts.sysjump, pty, serialname=opts.serialno)
 
-  elif opts.reboot:
-    result &= do_reboot(pty, serialname=opts.serialno)
+    elif opts.reboot:
+        result &= do_reboot(pty, serialname=opts.serialno)
 
-  elif opts.check_version:
-    result &= do_version(pty)
+    elif opts.check_version:
+        result &= do_version(pty)
 
-  elif opts.check_serial:
-    result &= do_check_serial(pty)
+    elif opts.check_serial:
+        result &= do_check_serial(pty)
 
-  elif opts.power:
-    result &= do_power(1, opts.bus, pty)
+    elif opts.power:
+        result &= do_power(1, opts.bus, pty)
 
-  elif opts.powerlog:
-    result &= do_power(opts.powerlog, opts.bus, pty)
+    elif opts.powerlog:
+        result &= do_power(opts.powerlog, opts.bus, pty)
 
-  if result:
-    c.log('PASS')
-  else:
-    c.log('FAIL')
-    sys.exit(-1)
+    if result:
+        c.log("PASS")
+    else:
+        c.log("FAIL")
+        sys.exit(-1)
 
 
-if __name__ == '__main__':
-  sys.exit(main(sys.argv[1:]))
+if __name__ == "__main__":
+    sys.exit(main(sys.argv[1:]))
diff --git a/extra/touchpad_updater/Makefile b/extra/touchpad_updater/Makefile
index ebf9c3212d..df824e8757 100644
--- a/extra/touchpad_updater/Makefile
+++ b/extra/touchpad_updater/Makefile
@@ -1,4 +1,4 @@
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/extra/touchpad_updater/touchpad_updater.c b/extra/touchpad_updater/touchpad_updater.c
index 716ded00f5..fee898ca06 100644
--- a/extra/touchpad_updater/touchpad_updater.c
+++ b/extra/touchpad_updater/touchpad_updater.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,16 +18,16 @@
 #include <libusb.h>
 
 /* Command line options */
-static uint16_t vid = 0x18d1;			/* Google */
-static uint16_t pid = 0x5022;			/* Hammer */
-static uint8_t ep_num = 4;			/* console endpoint */
-static uint8_t extended_i2c_exercise;		/* non-zero to exercise */
-static char *firmware_binary = "144.0_2.0.bin";	/* firmware blob */
+static uint16_t vid = 0x18d1; /* Google */
+static uint16_t pid = 0x5022; /* Hammer */
+static uint8_t ep_num = 4; /* console endpoint */
+static uint8_t extended_i2c_exercise; /* non-zero to exercise */
+static char *firmware_binary = "144.0_2.0.bin"; /* firmware blob */
 
 /* Firmware binary blob related */
-#define MAX_FW_PAGE_SIZE	512
-#define MAX_FW_PAGE_COUNT	1024
-#define MAX_FW_SIZE		(128 * 1024)
+#define MAX_FW_PAGE_SIZE 512
+#define MAX_FW_PAGE_COUNT 1024
+#define MAX_FW_SIZE (128 * 1024)
 
 static uint8_t fw_data[MAX_FW_SIZE];
 int fw_page_count;
@@ -47,13 +47,10 @@ static char *progname;
 static char *short_opts = ":f:v:p:e:hd";
 static const struct option long_opts[] = {
 	/* name    hasarg *flag val */
-	{"file",     1,   NULL, 'f'},
-	{"vid",      1,   NULL, 'v'},
-	{"pid",      1,   NULL, 'p'},
-	{"ep",       1,   NULL, 'e'},
-	{"help",     0,   NULL, 'h'},
-	{"debug",    0,   NULL, 'd'},
-	{NULL,       0,   NULL, 0},
+	{ "file", 1, NULL, 'f' }, { "vid", 1, NULL, 'v' },
+	{ "pid", 1, NULL, 'p' },  { "ep", 1, NULL, 'e' },
+	{ "help", 0, NULL, 'h' }, { "debug", 0, NULL, 'd' },
+	{ NULL, 0, NULL, 0 },
 };
 
 static void usage(int errs)
@@ -71,7 +68,8 @@ static void usage(int errs)
 	       "  -d,--debug              Exercise extended read I2C over USB\n"
 	       "                          and print verbose debug messages.\n"
 	       "  -h,--help               Show this message\n"
-	       "\n", progname, firmware_binary, vid, pid, ep_num);
+	       "\n",
+	       progname, firmware_binary, vid, pid, ep_num);
 
 	exit(!!errs);
 }
@@ -87,28 +85,28 @@ static void parse_cmdline(int argc, char *argv[])
 	else
 		progname = argv[0];
 
-	opterr = 0;				/* quiet, you */
+	opterr = 0; /* quiet, you */
 	while ((i = getopt_long(argc, argv, short_opts, long_opts, 0)) != -1) {
 		switch (i) {
 		case 'f':
 			firmware_binary = optarg;
 			break;
 		case 'p':
-			pid = (uint16_t) strtoull(optarg, &e, 16);
+			pid = (uint16_t)strtoull(optarg, &e, 16);
 			if (!*optarg || (e && *e)) {
 				printf("Invalid argument: \"%s\"\n", optarg);
 				errorcnt++;
 			}
 			break;
 		case 'v':
-			vid = (uint16_t) strtoull(optarg, &e, 16);
+			vid = (uint16_t)strtoull(optarg, &e, 16);
 			if (!*optarg || (e && *e)) {
 				printf("Invalid argument: \"%s\"\n", optarg);
 				errorcnt++;
 			}
 			break;
 		case 'e':
-			ep_num = (uint8_t) strtoull(optarg, &e, 0);
+			ep_num = (uint8_t)strtoull(optarg, &e, 0);
 			if (!*optarg || (e && *e)) {
 				printf("Invalid argument: \"%s\"\n", optarg);
 				errorcnt++;
@@ -120,7 +118,7 @@ static void parse_cmdline(int argc, char *argv[])
 		case 'h':
 			usage(errorcnt);
 			break;
-		case 0:				/* auto-handled option */
+		case 0: /* auto-handled option */
 			break;
 		case '?':
 			if (optopt)
@@ -142,7 +140,6 @@ static void parse_cmdline(int argc, char *argv[])
 
 	if (errorcnt)
 		usage(errorcnt);
-
 }
 
 /* USB transfer related */
@@ -163,7 +160,7 @@ static void request_exit(const char *format, ...)
 	va_start(ap, format);
 	vfprintf(stderr, format, ap);
 	va_end(ap);
-	do_exit++;    /* Why need this ? */
+	do_exit++; /* Why need this ? */
 
 	if (tx_transfer)
 		libusb_free_transfer(tx_transfer);
@@ -178,9 +175,8 @@ static void request_exit(const char *format, ...)
 	exit(1);
 }
 
-#define DIE(msg, r)							\
-	request_exit("%s: line %d, %s\n", msg, __LINE__,		\
-		     libusb_error_name(r))
+#define DIE(msg, r) \
+	request_exit("%s: line %d, %s\n", msg, __LINE__, libusb_error_name(r))
 
 static void sighandler(int signum)
 {
@@ -259,8 +255,8 @@ static void register_sigaction(void)
 }
 
 /* Transfer over libusb */
-#define I2C_PORT_ON_HAMMER		0x00
-#define I2C_ADDRESS_ON_HAMMER		0x15
+#define I2C_PORT_ON_HAMMER 0x00
+#define I2C_ADDRESS_ON_HAMMER 0x15
 
 static int check_read_status(int r, int expected, int actual)
 {
@@ -291,12 +287,12 @@ static int check_read_status(int r, int expected, int actual)
 	return r;
 }
 
-#define MAX_USB_PACKET_SIZE		64
-#define PRIMITIVE_READING_SIZE		60
+#define MAX_USB_PACKET_SIZE 64
+#define PRIMITIVE_READING_SIZE 60
 
-static int libusb_single_write_and_read(
-		const uint8_t *to_write, uint16_t write_length,
-		uint8_t *to_read, uint16_t read_length)
+static int libusb_single_write_and_read(const uint8_t *to_write,
+					uint16_t write_length, uint8_t *to_read,
+					uint16_t read_length)
 {
 	int r;
 	int tx_ready;
@@ -315,10 +311,10 @@ static int libusb_single_write_and_read(
 		tx_buf[4] = read_length >> 7;
 		if (extended_i2c_exercise) {
 			printf("Triggering extended reading."
-				"rc:%0x, rc1:%0x\n",
-				tx_buf[3], tx_buf[4]);
+			       "rc:%0x, rc1:%0x\n",
+			       tx_buf[3], tx_buf[4]);
 			printf("Expecting %d Bytes.\n",
-				(tx_buf[3] & 0x7f) | (tx_buf[4] << 7));
+			       (tx_buf[3] & 0x7f) | (tx_buf[4] << 7));
 		}
 	} else {
 		tx_buf[3] = read_length;
@@ -331,19 +327,18 @@ static int libusb_single_write_and_read(
 	while (sent_bytes < (offset + write_length)) {
 		tx_ready = remains = (offset + write_length) - sent_bytes;
 
-		r = libusb_bulk_transfer(devh,
-				(ep_num | LIBUSB_ENDPOINT_OUT),
-				tx_buf + sent_bytes, tx_ready,
-				&actual_length, 5000);
+		r = libusb_bulk_transfer(devh, (ep_num | LIBUSB_ENDPOINT_OUT),
+					 tx_buf + sent_bytes, tx_ready,
+					 &actual_length, 5000);
 		if (r == 0 && actual_length == tx_ready) {
 			r = libusb_bulk_transfer(devh,
-					(ep_num | LIBUSB_ENDPOINT_IN),
-					rx_buf, sizeof(rx_buf),
-					&actual_length, 5000);
+						 (ep_num | LIBUSB_ENDPOINT_IN),
+						 rx_buf, sizeof(rx_buf),
+						 &actual_length, 5000);
 		}
-		r = check_read_status(
-				r, (remains == tx_ready) ? read_length : 0,
-				actual_length);
+		r = check_read_status(r,
+				      (remains == tx_ready) ? read_length : 0,
+				      actual_length);
 		if (r)
 			break;
 		sent_bytes += tx_ready;
@@ -352,21 +347,19 @@ static int libusb_single_write_and_read(
 }
 
 /* Control Elan trackpad I2C over USB */
-#define ETP_I2C_INF_LENGTH		2
+#define ETP_I2C_INF_LENGTH 2
 
-static int elan_write_and_read(
-		int reg, uint8_t *buf, int read_length,
-		int with_cmd, int cmd)
+static int elan_write_and_read(int reg, uint8_t *buf, int read_length,
+			       int with_cmd, int cmd)
 {
-
 	tx_buf[0] = (reg >> 0) & 0xff;
 	tx_buf[1] = (reg >> 8) & 0xff;
 	if (with_cmd) {
 		tx_buf[2] = (cmd >> 0) & 0xff;
 		tx_buf[3] = (cmd >> 8) & 0xff;
 	}
-	return libusb_single_write_and_read(
-			tx_buf, with_cmd ? 4 : 2, rx_buf, read_length);
+	return libusb_single_write_and_read(tx_buf, with_cmd ? 4 : 2, rx_buf,
+					    read_length);
 }
 
 static int elan_read_block(int reg, uint8_t *buf, int read_length)
@@ -385,16 +378,16 @@ static int elan_write_cmd(int reg, int cmd)
 }
 
 /* Elan trackpad firmware information related */
-#define ETP_I2C_IAP_VERSION_CMD		0x0110
-#define ETP_I2C_FW_VERSION_CMD		0x0102
-#define ETP_I2C_IAP_CHECKSUM_CMD	0x0315
-#define ETP_I2C_FW_CHECKSUM_CMD		0x030F
-#define ETP_I2C_OSM_VERSION_CMD		0x0103
+#define ETP_I2C_IAP_VERSION_CMD 0x0110
+#define ETP_I2C_FW_VERSION_CMD 0x0102
+#define ETP_I2C_IAP_CHECKSUM_CMD 0x0315
+#define ETP_I2C_FW_CHECKSUM_CMD 0x030F
+#define ETP_I2C_OSM_VERSION_CMD 0x0103
 
 static int elan_get_version(int is_iap)
 {
-	elan_read_cmd(
-		is_iap ? ETP_I2C_IAP_VERSION_CMD : ETP_I2C_FW_VERSION_CMD);
+	elan_read_cmd(is_iap ? ETP_I2C_IAP_VERSION_CMD :
+			       ETP_I2C_FW_VERSION_CMD);
 	return le_bytes_to_int(rx_buf + 4);
 }
 
@@ -435,8 +428,8 @@ static void elan_get_ic_page_count(void)
 
 static int elan_get_checksum(int is_iap)
 {
-	elan_read_cmd(
-		is_iap ? ETP_I2C_IAP_CHECKSUM_CMD : ETP_I2C_FW_CHECKSUM_CMD);
+	elan_read_cmd(is_iap ? ETP_I2C_IAP_CHECKSUM_CMD :
+			       ETP_I2C_FW_CHECKSUM_CMD);
 	return le_bytes_to_int(rx_buf + 4);
 }
 
@@ -451,21 +444,21 @@ static uint16_t elan_get_fw_info(void)
 	iap_checksum = elan_get_checksum(1);
 	fw_version = elan_get_version(0);
 	iap_version = elan_get_version(1);
-	printf("IAP  version: %4x, FW  version: %4x\n",
-			iap_version, fw_version);
-	printf("IAP checksum: %4x, FW checksum: %4x\n",
-			iap_checksum, fw_checksum);
+	printf("IAP  version: %4x, FW  version: %4x\n", iap_version,
+	       fw_version);
+	printf("IAP checksum: %4x, FW checksum: %4x\n", iap_checksum,
+	       fw_checksum);
 	return fw_checksum;
 }
 
 /* Update preparation */
-#define ETP_I2C_IAP_RESET_CMD		0x0314
-#define ETP_I2C_IAP_RESET		0xF0F0
-#define ETP_I2C_IAP_CTRL_CMD		0x0310
-#define ETP_I2C_MAIN_MODE_ON		(1 << 9)
-#define ETP_I2C_IAP_CMD			0x0311
-#define ETP_I2C_IAP_PASSWORD		0x1EA5
-#define ETP_I2C_IAP_TYPE_CMD		0x0304
+#define ETP_I2C_IAP_RESET_CMD 0x0314
+#define ETP_I2C_IAP_RESET 0xF0F0
+#define ETP_I2C_IAP_CTRL_CMD 0x0310
+#define ETP_I2C_MAIN_MODE_ON (1 << 9)
+#define ETP_I2C_IAP_CMD 0x0311
+#define ETP_I2C_IAP_PASSWORD 0x1EA5
+#define ETP_I2C_IAP_TYPE_CMD 0x0304
 
 static int elan_in_main_mode(void)
 {
@@ -478,8 +471,7 @@ static int elan_read_write_iap_type(void)
 	for (int retry = 0; retry < 3; ++retry) {
 		uint16_t val;
 
-		if (elan_write_cmd(ETP_I2C_IAP_TYPE_CMD,
-				   fw_page_size / 2))
+		if (elan_write_cmd(ETP_I2C_IAP_TYPE_CMD, fw_page_size / 2))
 			return -1;
 
 		if (elan_read_cmd(ETP_I2C_IAP_TYPE_CMD))
@@ -490,7 +482,6 @@ static int elan_read_write_iap_type(void)
 			printf("%s: OK\n", __func__);
 			return 0;
 		}
-
 	}
 	return -1;
 }
@@ -528,17 +519,17 @@ static void elan_prepare_for_update(void)
 		request_exit("cannot read iap password.\n");
 	if (le_bytes_to_int(rx_buf + 4) != ETP_I2C_IAP_PASSWORD)
 		request_exit("Got an unexpected IAP password %4x\n",
-			le_bytes_to_int(rx_buf + 4));
+			     le_bytes_to_int(rx_buf + 4));
 }
 
 /* Firmware block update */
-#define ETP_IAP_START_ADDR		0x0083
+#define ETP_IAP_START_ADDR 0x0083
 
 static uint16_t elan_calc_checksum(uint8_t *data, int length)
 {
 	uint16_t checksum = 0;
 	for (int i = 0; i < length; i += 2)
-		checksum += ((uint16_t)(data[i+1]) << 8) | (data[i]);
+		checksum += ((uint16_t)(data[i + 1]) << 8) | (data[i]);
 	return checksum;
 }
 
@@ -547,11 +538,11 @@ static int elan_get_iap_addr(void)
 	return le_bytes_to_int(fw_data + ETP_IAP_START_ADDR * 2) * 2;
 }
 
-#define ETP_I2C_IAP_REG_L		0x01
-#define ETP_I2C_IAP_REG_H		0x06
+#define ETP_I2C_IAP_REG_L 0x01
+#define ETP_I2C_IAP_REG_H 0x06
 
-#define ETP_FW_IAP_PAGE_ERR		(1 << 5)
-#define ETP_FW_IAP_INTF_ERR		(1 << 4)
+#define ETP_FW_IAP_PAGE_ERR (1 << 5)
+#define ETP_FW_IAP_INTF_ERR (1 << 4)
 
 static int elan_write_fw_block(uint8_t *raw_data, uint16_t checksum)
 {
@@ -564,8 +555,8 @@ static int elan_write_fw_block(uint8_t *raw_data, uint16_t checksum)
 	page_store[fw_page_size + 2 + 0] = (checksum >> 0) & 0xff;
 	page_store[fw_page_size + 2 + 1] = (checksum >> 8) & 0xff;
 
-	rv = libusb_single_write_and_read(
-			page_store, fw_page_size + 4, rx_buf, 0);
+	rv = libusb_single_write_and_read(page_store, fw_page_size + 4, rx_buf,
+					  0);
 	if (rv)
 		return rv;
 	usleep((fw_page_size >= 512 ? 50 : 35) * 1000);
@@ -578,7 +569,6 @@ static int elan_write_fw_block(uint8_t *raw_data, uint16_t checksum)
 	return 0;
 }
 
-
 static uint16_t elan_update_firmware(void)
 {
 	uint16_t checksum = 0, block_checksum;
@@ -661,7 +651,7 @@ int main(int argc, char *argv[])
 	remote_checksum = elan_get_checksum(1);
 	if (remote_checksum != local_checksum)
 		printf("checksum diff local=[%04X], remote=[%04X]\n",
-				local_checksum, remote_checksum);
+		       local_checksum, remote_checksum);
 
 	/* Print the updated firmware information */
 	elan_get_fw_info();
diff --git a/extra/usb_console/Makefile b/extra/usb_console/Makefile
index bddca1d0a2..bc4c5909a2 100644
--- a/extra/usb_console/Makefile
+++ b/extra/usb_console/Makefile
@@ -1,4 +1,4 @@
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/extra/usb_console/usb_console.c b/extra/usb_console/usb_console.c
index e4f8ea504f..aea9eb8293 100644
--- a/extra/usb_console/usb_console.c
+++ b/extra/usb_console/usb_console.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,12 +18,12 @@
 #include <libusb.h>
 
 /* Options */
-static uint16_t vid = 0x18d1;			/* Google */
-static uint16_t pid = 0x500f;			/* discovery-stm32f072 */
-static uint8_t ep_num = 4;			/* console endpoint */
+static uint16_t vid = 0x18d1; /* Google */
+static uint16_t pid = 0x500f; /* discovery-stm32f072 */
+static uint8_t ep_num = 4; /* console endpoint */
 
-static unsigned char rx_buf[1024];		/* much too big */
-static unsigned char tx_buf[1024];		/* much too big */
+static unsigned char rx_buf[1024]; /* much too big */
+static unsigned char tx_buf[1024]; /* much too big */
 static const struct libusb_pollfd **usb_fds;
 static struct libusb_device_handle *devh;
 static struct libusb_transfer *rx_transfer;
@@ -40,9 +40,8 @@ static void request_exit(const char *format, ...)
 	do_exit++;
 }
 
-#define BOO(msg, r)							\
-	request_exit("%s: line %d, %s\n", msg, __LINE__,		\
-		     libusb_error_name(r))
+#define BOO(msg, r) \
+	request_exit("%s: line %d, %s\n", msg, __LINE__, libusb_error_name(r))
 
 static void sighandler(int signum)
 {
@@ -105,8 +104,8 @@ static void send_tx(int len)
 {
 	int r;
 
-	libusb_fill_bulk_transfer(tx_transfer, devh,
-				  ep_num, tx_buf, len, cb_tx, NULL, 0);
+	libusb_fill_bulk_transfer(tx_transfer, devh, ep_num, tx_buf, len, cb_tx,
+				  NULL, 0);
 
 	r = libusb_submit_transfer(tx_transfer);
 	if (r < 0)
@@ -185,7 +184,7 @@ static int wait_for_stuff_to_happen(void)
 		return -1;
 	}
 
-	if (r == 0)				/* timed out */
+	if (r == 0) /* timed out */
 		return 0;
 
 	/* Ignore stdin until we've finished sending the current line */
@@ -235,11 +234,9 @@ static char *progname;
 static char *short_opts = ":v:p:e:h";
 static const struct option long_opts[] = {
 	/* name    hasarg *flag val */
-	{"vid",      1,   NULL, 'v'},
-	{"pid",      1,   NULL, 'p'},
-	{"ep",       1,   NULL, 'e'},
-	{"help",     0,   NULL, 'h'},
-	{NULL,       0,   NULL, 0},
+	{ "vid", 1, NULL, 'v' }, { "pid", 1, NULL, 'p' },
+	{ "ep", 1, NULL, 'e' },	 { "help", 0, NULL, 'h' },
+	{ NULL, 0, NULL, 0 },
 };
 
 static void usage(int errs)
@@ -254,7 +251,8 @@ static void usage(int errs)
 	       "  -p,--pid    HEXVAL      Product ID (default %04x)\n"
 	       "  -e,--ep     NUM         Endpoint (default %d)\n"
 	       "  -h,--help               Show this message\n"
-	       "\n", progname, vid, pid, ep_num);
+	       "\n",
+	       progname, vid, pid, ep_num);
 
 	exit(!!errs);
 }
@@ -275,25 +273,25 @@ int main(int argc, char *argv[])
 	else
 		progname = argv[0];
 
-	opterr = 0;				/* quiet, you */
+	opterr = 0; /* quiet, you */
 	while ((i = getopt_long(argc, argv, short_opts, long_opts, 0)) != -1) {
 		switch (i) {
 		case 'p':
-			pid = (uint16_t) strtoull(optarg, &e, 16);
+			pid = (uint16_t)strtoull(optarg, &e, 16);
 			if (!*optarg || (e && *e)) {
 				printf("Invalid argument: \"%s\"\n", optarg);
 				errorcnt++;
 			}
 			break;
 		case 'v':
-			vid = (uint16_t) strtoull(optarg, &e, 16);
+			vid = (uint16_t)strtoull(optarg, &e, 16);
 			if (!*optarg || (e && *e)) {
 				printf("Invalid argument: \"%s\"\n", optarg);
 				errorcnt++;
 			}
 			break;
 		case 'e':
-			ep_num = (uint8_t) strtoull(optarg, &e, 0);
+			ep_num = (uint8_t)strtoull(optarg, &e, 0);
 			if (!*optarg || (e && *e)) {
 				printf("Invalid argument: \"%s\"\n", optarg);
 				errorcnt++;
@@ -302,7 +300,7 @@ int main(int argc, char *argv[])
 		case 'h':
 			usage(errorcnt);
 			break;
-		case 0:				/* auto-handled option */
+		case 0: /* auto-handled option */
 			break;
 		case '?':
 			if (optopt)
@@ -368,9 +366,8 @@ int main(int argc, char *argv[])
 		printf("can't alloc rx_transfer");
 		goto out;
 	}
-	libusb_fill_bulk_transfer(rx_transfer, devh,
-				  0x80 | ep_num,
-				  rx_buf, sizeof(rx_buf), cb_rx, NULL, 0);
+	libusb_fill_bulk_transfer(rx_transfer, devh, 0x80 | ep_num, rx_buf,
+				  sizeof(rx_buf), cb_rx, NULL, 0);
 
 	tx_transfer = libusb_alloc_transfer(0);
 	if (!tx_transfer) {
@@ -396,14 +393,14 @@ int main(int argc, char *argv[])
 	while (!do_exit) {
 		r = wait_for_stuff_to_happen();
 		switch (r) {
-		case 0:	/* timed out */
+		case 0: /* timed out */
 			/* printf("."); */
 			/* fflush(stdout); */
 			break;
-		case 1:	/* stdin ready */
+		case 1: /* stdin ready */
 			handle_stdin();
 			break;
-		case 2:	/* libusb ready */
+		case 2: /* libusb ready */
 			handle_libusb();
 			break;
 		}
@@ -440,7 +437,7 @@ int main(int argc, char *argv[])
 
 	printf("bye\n");
 	r = 0;
- out:
+out:
 	if (tx_transfer)
 		libusb_free_transfer(tx_transfer);
 	if (rx_transfer)
diff --git a/extra/usb_gpio/Makefile b/extra/usb_gpio/Makefile
index 644e3ee70f..84a27ccc12 100644
--- a/extra/usb_gpio/Makefile
+++ b/extra/usb_gpio/Makefile
@@ -1,4 +1,4 @@
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
+# Copyright 2014 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/extra/usb_gpio/usb_gpio.c b/extra/usb_gpio/usb_gpio.c
index 8973f3d304..7f2121d2b0 100644
--- a/extra/usb_gpio/usb_gpio.c
+++ b/extra/usb_gpio/usb_gpio.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
+ * Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,54 +11,46 @@
 #include <string.h>
 #include <unistd.h>
 
-#define CHECK(expression)					\
-	({							\
-		int error__ = (expression);			\
-								\
-		if (error__ != 0) {				\
-			fprintf(stderr,				\
-				"libusb error: %s:%d %s\n",	\
-				__FILE__,			\
-				__LINE__,			\
-				libusb_error_name(error__));	\
-			return error__;				\
-		}						\
-								\
-		error__;					\
+#define CHECK(expression)                                                     \
+	({                                                                    \
+		int error__ = (expression);                                   \
+                                                                              \
+		if (error__ != 0) {                                           \
+			fprintf(stderr, "libusb error: %s:%d %s\n", __FILE__, \
+				__LINE__, libusb_error_name(error__));        \
+			return error__;                                       \
+		}                                                             \
+                                                                              \
+		error__;                                                      \
 	})
 
 #define TRANSFER_TIMEOUT_MS 100
 
-static int gpio_write(libusb_device_handle *device,
-		      uint32_t set_mask,
+static int gpio_write(libusb_device_handle *device, uint32_t set_mask,
 		      uint32_t clear_mask)
 {
 	uint8_t command[8];
-	int     transferred;
+	int transferred;
 
-	command[0] = (set_mask >>  0) & 0xff;
-	command[1] = (set_mask >>  8) & 0xff;
+	command[0] = (set_mask >> 0) & 0xff;
+	command[1] = (set_mask >> 8) & 0xff;
 	command[2] = (set_mask >> 16) & 0xff;
 	command[3] = (set_mask >> 24) & 0xff;
 
-	command[4] = (clear_mask >>  0) & 0xff;
-	command[5] = (clear_mask >>  8) & 0xff;
+	command[4] = (clear_mask >> 0) & 0xff;
+	command[5] = (clear_mask >> 8) & 0xff;
 	command[6] = (clear_mask >> 16) & 0xff;
 	command[7] = (clear_mask >> 24) & 0xff;
 
-	CHECK(libusb_bulk_transfer(device,
-				   LIBUSB_ENDPOINT_OUT | 2,
-				   command,
-				   sizeof(command),
-				   &transferred,
+	CHECK(libusb_bulk_transfer(device, LIBUSB_ENDPOINT_OUT | 2, command,
+				   sizeof(command), &transferred,
 				   TRANSFER_TIMEOUT_MS));
 
 	if (transferred != sizeof(command)) {
 		fprintf(stderr,
 			"Failed to transfer full command "
 			"(sent %d of %d bytes)\n",
-			transferred,
-			(int)sizeof(command));
+			transferred, (int)sizeof(command));
 		return LIBUSB_ERROR_OTHER;
 	}
 
@@ -68,38 +60,29 @@ static int gpio_write(libusb_device_handle *device,
 static int gpio_read(libusb_device_handle *device, uint32_t *mask)
 {
 	uint8_t response[4];
-	int     transferred;
+	int transferred;
 
 	/*
 	 * The first query does triggers the sampling of the GPIO values, the
 	 * second query reads them back.
 	 */
-	CHECK(libusb_bulk_transfer(device,
-				   LIBUSB_ENDPOINT_IN | 2,
-				   response,
-				   sizeof(response),
-				   &transferred,
+	CHECK(libusb_bulk_transfer(device, LIBUSB_ENDPOINT_IN | 2, response,
+				   sizeof(response), &transferred,
 				   TRANSFER_TIMEOUT_MS));
 
-	CHECK(libusb_bulk_transfer(device,
-				   LIBUSB_ENDPOINT_IN | 2,
-				   response,
-				   sizeof(response),
-				   &transferred,
+	CHECK(libusb_bulk_transfer(device, LIBUSB_ENDPOINT_IN | 2, response,
+				   sizeof(response), &transferred,
 				   TRANSFER_TIMEOUT_MS));
 
 	if (transferred != sizeof(response)) {
 		fprintf(stderr,
 			"Failed to transfer full response "
 			"(read %d of %d bytes)\n",
-			transferred,
-			(int)sizeof(response));
+			transferred, (int)sizeof(response));
 		return LIBUSB_ERROR_OTHER;
 	}
 
-	*mask = (response[0] <<  0 |
-		 response[1] <<  8 |
-		 response[2] << 16 |
+	*mask = (response[0] << 0 | response[1] << 8 | response[2] << 16 |
 		 response[3] << 24);
 
 	return 0;
@@ -107,13 +90,13 @@ static int gpio_read(libusb_device_handle *device, uint32_t *mask)
 
 int main(int argc, char **argv)
 {
-	libusb_context       *context;
+	libusb_context *context;
 	libusb_device_handle *device;
-	uint16_t              vendor_id  = 0x18d1; /* Google */
-	uint16_t              product_id = 0x500f; /* discovery-stm32f072 */
-	int                   interface = 1;	   /* gpio interface */
+	uint16_t vendor_id = 0x18d1; /* Google */
+	uint16_t product_id = 0x500f; /* discovery-stm32f072 */
+	int interface = 1; /* gpio interface */
 
-	if (!(argc == 2 && strcmp(argv[1], "read")  == 0) &&
+	if (!(argc == 2 && strcmp(argv[1], "read") == 0) &&
 	    !(argc == 4 && strcmp(argv[1], "write") == 0)) {
 		puts("Usage: usb_gpio read\n"
 		     "       usb_gpio write <set_mask> <clear_mask>\n");
@@ -122,15 +105,12 @@ int main(int argc, char **argv)
 
 	CHECK(libusb_init(&context));
 
-	device = libusb_open_device_with_vid_pid(context,
-						 vendor_id,
-						 product_id);
+	device =
+		libusb_open_device_with_vid_pid(context, vendor_id, product_id);
 
 	if (device == NULL) {
-		fprintf(stderr,
-			"Unable to find device 0x%04x:0x%04x\n",
-			vendor_id,
-			product_id);
+		fprintf(stderr, "Unable to find device 0x%04x:0x%04x\n",
+			vendor_id, product_id);
 		return 1;
 	}
 
@@ -146,7 +126,7 @@ int main(int argc, char **argv)
 	}
 
 	if (argc == 4 && strcmp(argv[1], "write") == 0) {
-		uint32_t set_mask   = strtol(argv[2], NULL, 0);
+		uint32_t set_mask = strtol(argv[2], NULL, 0);
 		uint32_t clear_mask = strtol(argv[3], NULL, 0);
 
 		CHECK(gpio_write(device, set_mask, clear_mask));
diff --git a/extra/usb_power/convert_power_log_board.py b/extra/usb_power/convert_power_log_board.py
index 8aab77ee4c..f5fb7e925d 100644
--- a/extra/usb_power/convert_power_log_board.py
+++ b/extra/usb_power/convert_power_log_board.py
@@ -1,11 +1,7 @@
 #!/usr/bin/env python
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
 
 """
 Program to convert sweetberry config to servod config template.
@@ -14,11 +10,12 @@ Program to convert sweetberry config to servod config template.
 # Note: This is a py2/3 compatible file.
 
 from __future__ import print_function
+
 import json
 import os
 import sys
 
-from powerlog import Spower
+from powerlog import Spower  # pylint:disable=import-error
 
 
 def fetch_records(board_file):
@@ -48,21 +45,29 @@ def write_to_file(file, sweetberry, inas):
       inas: list of inas read from board file.
     """
 
-    with open(file, 'w') as pyfile:
+    with open(file, "w") as pyfile:
 
-        pyfile.write('inas = [\n')
+        pyfile.write("inas = [\n")
 
         for rec in inas:
-            if rec['sweetberry'] != sweetberry:
+            if rec["sweetberry"] != sweetberry:
                 continue
 
             # EX : ('sweetberry', 0x40, 'SB_FW_CAM_2P8', 5.0, 1.000, 3, False),
-            channel, i2c_addr = Spower.CHMAP[rec['channel']]
-            record = ("    ('sweetberry', 0x%02x, '%s', 5.0, %f, %d, 'True')"
-                      ",\n" % (i2c_addr, rec['name'], rec['rs'], channel))
+            channel, i2c_addr = Spower.CHMAP[rec["channel"]]
+            record = (
+                "    ('sweetberry', 0x%02x, '%s', 5.0, %f, %d, 'True')"
+                ",\n"
+                % (
+                    i2c_addr,
+                    rec["name"],
+                    rec["rs"],
+                    channel,
+                )
+            )
             pyfile.write(record)
 
-        pyfile.write(']\n')
+        pyfile.write("]\n")
 
 
 def main(argv):
@@ -76,16 +81,18 @@ def main(argv):
 
     inas = fetch_records(inputf)
 
-    sweetberry = set(rec['sweetberry'] for rec in inas)
+    sweetberry = set(rec["sweetberry"] for rec in inas)
 
     if len(sweetberry) == 2:
-        print("Converting %s to %s and %s" % (inputf, basename + '_a.py',
-                                              basename + '_b.py'))
-        write_to_file(basename + '_a.py', 'A', inas)
-        write_to_file(basename + '_b.py', 'B', inas)
+        print(
+            "Converting %s to %s and %s"
+            % (inputf, basename + "_a.py", basename + "_b.py")
+        )
+        write_to_file(basename + "_a.py", "A", inas)
+        write_to_file(basename + "_b.py", "B", inas)
     else:
-        print("Converting %s to %s" % (inputf, basename + '.py'))
-        write_to_file(basename + '.py', sweetberry.pop(), inas)
+        print("Converting %s to %s" % (inputf, basename + ".py"))
+        write_to_file(basename + ".py", sweetberry.pop(), inas)
 
 
 if __name__ == "__main__":
diff --git a/extra/usb_power/convert_servo_ina.py b/extra/usb_power/convert_servo_ina.py
index 1c70f31aeb..1deb75cda4 100755
--- a/extra/usb_power/convert_servo_ina.py
+++ b/extra/usb_power/convert_servo_ina.py
@@ -1,11 +1,7 @@
 #!/usr/bin/env python
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
 
 """Program to convert power logging config from a servo_ina device
    to a sweetberry config.
@@ -14,67 +10,74 @@
 # Note: This is a py2/3 compatible file.
 
 from __future__ import print_function
+
 import os
 import sys
 
 
 def fetch_records(basename):
-  """Import records from servo_ina file.
+    """Import records from servo_ina file.
 
-  servo_ina files are python imports, and have a list of tuples with
-  the INA data.
-  (inatype, i2caddr, rail name, bus voltage, shunt ohms, mux, True)
+    servo_ina files are python imports, and have a list of tuples with
+    the INA data.
+    (inatype, i2caddr, rail name, bus voltage, shunt ohms, mux, True)
 
-  Args:
-    basename: python import name (filename -.py)
+    Args:
+      basename: python import name (filename -.py)
 
-  Returns:
-    list of tuples as described above.
-  """
-  ina_desc = __import__(basename)
-  return ina_desc.inas
+    Returns:
+      list of tuples as described above.
+    """
+    ina_desc = __import__(basename)
+    return ina_desc.inas
 
 
 def main(argv):
-  if len(argv) != 2:
-    print("usage:")
-    print(" %s input.py" % argv[0])
-    return
+    if len(argv) != 2:
+        print("usage:")
+        print(" %s input.py" % argv[0])
+        return
 
-  inputf = argv[1]
-  basename = os.path.splitext(inputf)[0]
-  outputf = basename + '.board'
-  outputs = basename + '.scenario'
+    inputf = argv[1]
+    basename = os.path.splitext(inputf)[0]
+    outputf = basename + ".board"
+    outputs = basename + ".scenario"
 
-  print("Converting %s to %s, %s" % (inputf, outputf, outputs))
+    print("Converting %s to %s, %s" % (inputf, outputf, outputs))
 
-  inas = fetch_records(basename)
+    inas = fetch_records(basename)
 
+    boardfile = open(outputf, "w")
+    scenario = open(outputs, "w")
 
-  boardfile = open(outputf, 'w')
-  scenario = open(outputs, 'w')
+    boardfile.write("[\n")
+    scenario.write("[\n")
+    start = True
 
-  boardfile.write('[\n')
-  scenario.write('[\n')
-  start = True
+    for rec in inas:
+        if start:
+            start = False
+        else:
+            boardfile.write(",\n")
+            scenario.write(",\n")
 
-  for rec in inas:
-    if start:
-      start = False
-    else:
-      boardfile.write(',\n')
-      scenario.write(',\n')
+        record = (
+            '  {"name": "%s", "rs": %f, "sweetberry": "A", "channel": %d}'
+            % (
+                rec[2],
+                rec[4],
+                rec[1] - 64,
+            )
+        )
+        boardfile.write(record)
+        scenario.write('"%s"' % rec[2])
 
-    record = '  {"name": "%s", "rs": %f, "sweetberry": "A", "channel": %d}' % (
-             rec[2], rec[4], rec[1] - 64)
-    boardfile.write(record)
-    scenario.write('"%s"' % rec[2])
+    boardfile.write("\n")
+    boardfile.write("]")
 
-  boardfile.write('\n')
-  boardfile.write(']')
+    scenario.write("\n")
+    scenario.write("]")
 
-  scenario.write('\n')
-  scenario.write(']')
 
 if __name__ == "__main__":
-  main(sys.argv)
+    main(sys.argv)
diff --git a/extra/usb_power/powerlog.py b/extra/usb_power/powerlog.py
index 82cce3daed..13e41bd23a 100755
--- a/extra/usb_power/powerlog.py
+++ b/extra/usb_power/powerlog.py
@@ -1,11 +1,7 @@
 #!/usr/bin/env python
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
 
 """Program to fetch power logging data from a sweetberry device
    or other usb device that exports a USB power logging interface.
@@ -14,9 +10,9 @@
 # Note: This is a py2/3 compatible file.
 
 from __future__ import print_function
+
 import argparse
 import array
-from distutils import sysconfig
 import json
 import logging
 import os
@@ -25,884 +21,1041 @@ import struct
 import sys
 import time
 import traceback
+from distutils import sysconfig
 
-import usb
-
-from stats_manager import StatsManager
+import usb  # pylint:disable=import-error
+from stats_manager import StatsManager  # pylint:disable=import-error
 
 # Directory where hdctools installs configuration files into.
-LIB_DIR = os.path.join(sysconfig.get_python_lib(standard_lib=False), 'servo',
-                       'data')
+LIB_DIR = os.path.join(
+    sysconfig.get_python_lib(standard_lib=False), "servo", "data"
+)
 
 # Potential config file locations: current working directory, the same directory
 # as powerlog.py file or LIB_DIR.
-CONFIG_LOCATIONS = [os.getcwd(), os.path.dirname(os.path.realpath(__file__)),
-                    LIB_DIR]
-
-def logoutput(msg):
-  print(msg)
-  sys.stdout.flush()
-
-def process_filename(filename):
-  """Find the file path from the filename.
-
-  If filename is already the complete path, return that directly. If filename is
-  just the short name, look for the file in the current working directory, in
-  the directory of the current .py file, and then in the directory installed by
-  hdctools. If the file is found, return the complete path of the file.
-
-  Args:
-      filename: complete file path or short file name.
-
-  Returns:
-      a complete file path.
-
-  Raises:
-      IOError if filename does not exist.
-  """
-  # Check if filename is absolute path.
-  if os.path.isabs(filename) and os.path.isfile(filename):
-    return filename
-  # Check if filename is relative to a known config location.
-  for dirname in CONFIG_LOCATIONS:
-    file_at_dir = os.path.join(dirname, filename)
-    if os.path.isfile(file_at_dir):
-      return file_at_dir
-  raise IOError('No such file or directory: \'%s\'' % filename)
-
-
-class Spower(object):
-  """Power class to access devices on the bus.
-
-  Usage:
-    bus = Spower()
-
-  Instance Variables:
-    _dev: pyUSB device object
-    _read_ep: pyUSB read endpoint for this interface
-    _write_ep: pyUSB write endpoint for this interface
-  """
-
-  # INA interface type.
-  INA_POWER     = 1
-  INA_BUSV      = 2
-  INA_CURRENT   = 3
-  INA_SHUNTV    = 4
-  # INA_SUFFIX is used to differentiate multiple ina types for the same power
-  # rail. No suffix for when ina type is 0 (non-existent) and when ina type is 1
-  # (power, no suffix for backward compatibility).
-  INA_SUFFIX      = ['', '', '_busv', '_cur', '_shuntv']
-
-  # usb power commands
-  CMD_RESET   = 0x0000
-  CMD_STOP    = 0x0001
-  CMD_ADDINA  = 0x0002
-  CMD_START   = 0x0003
-  CMD_NEXT    = 0x0004
-  CMD_SETTIME = 0x0005
-
-  # Map between header channel number (0-47)
-  # and INA I2C bus/addr on sweetberry.
-  CHMAP = {
-	0: (3, 0x40),
-	1: (1, 0x40),
-	2: (2, 0x40),
-	3: (0, 0x40),
-	4: (3, 0x41),
-	5: (1, 0x41),
-	6: (2, 0x41),
-	7: (0, 0x41),
-	8: (3, 0x42),
-	9: (1, 0x42),
-	10: (2, 0x42),
-	11: (0, 0x42),
-	12: (3, 0x43),
-	13: (1, 0x43),
-	14: (2, 0x43),
-	15: (0, 0x43),
-	16: (3, 0x44),
-	17: (1, 0x44),
-	18: (2, 0x44),
-	19: (0, 0x44),
-	20: (3, 0x45),
-	21: (1, 0x45),
-	22: (2, 0x45),
-	23: (0, 0x45),
-	24: (3, 0x46),
-	25: (1, 0x46),
-	26: (2, 0x46),
-	27: (0, 0x46),
-	28: (3, 0x47),
-	29: (1, 0x47),
-	30: (2, 0x47),
-	31: (0, 0x47),
-	32: (3, 0x48),
-	33: (1, 0x48),
-	34: (2, 0x48),
-	35: (0, 0x48),
-	36: (3, 0x49),
-	37: (1, 0x49),
-	38: (2, 0x49),
-	39: (0, 0x49),
-	40: (3, 0x4a),
-	41: (1, 0x4a),
-	42: (2, 0x4a),
-	43: (0, 0x4a),
-	44: (3, 0x4b),
-	45: (1, 0x4b),
-	46: (2, 0x4b),
-	47: (0, 0x4b),
-  }
-
-  def __init__(self, board, vendor=0x18d1,
-               product=0x5020, interface=1, serialname=None):
-    self._logger = logging.getLogger(__name__)
-    self._board = board
-
-    # Find the stm32.
-    dev_g = usb.core.find(idVendor=vendor, idProduct=product, find_all=True)
-    dev_list = list(dev_g)
-    if dev_list is None:
-      raise Exception("Power", "USB device not found")
-
-    # Check if we have multiple stm32s and we've specified the serial.
-    dev = None
-    if serialname:
-      for d in dev_list:
-        dev_serial = "PyUSB dioesn't have a stable interface"
-        try:
-          dev_serial = usb.util.get_string(d, 256, d.iSerialNumber)
-        except ValueError:
-          # Incompatible pyUsb version.
-          dev_serial = usb.util.get_string(d, d.iSerialNumber)
-        if dev_serial == serialname:
-          dev = d
-          break
-      if dev is None:
-        raise Exception("Power", "USB device(%s) not found" % serialname)
-    else:
-      try:
-        dev = dev_list[0]
-      except TypeError:
-        # Incompatible pyUsb version.
-        dev = dev_list.next()
-
-    self._logger.debug("Found USB device: %04x:%04x", vendor, product)
-    self._dev = dev
-
-    # Get an endpoint instance.
-    try:
-      dev.set_configuration()
-    except usb.USBError:
-      pass
-    cfg = dev.get_active_configuration()
-
-    intf = usb.util.find_descriptor(cfg, custom_match=lambda i: \
-        i.bInterfaceClass==255 and i.bInterfaceSubClass==0x54)
-
-    self._intf = intf
-    self._logger.debug("InterfaceNumber: %s", intf.bInterfaceNumber)
-
-    read_ep = usb.util.find_descriptor(
-      intf,
-      # match the first IN endpoint
-      custom_match = \
-      lambda e: \
-          usb.util.endpoint_direction(e.bEndpointAddress) == \
-          usb.util.ENDPOINT_IN
-    )
-
-    self._read_ep = read_ep
-    self._logger.debug("Reader endpoint: 0x%x", read_ep.bEndpointAddress)
-
-    write_ep = usb.util.find_descriptor(
-      intf,
-      # match the first OUT endpoint
-      custom_match = \
-      lambda e: \
-          usb.util.endpoint_direction(e.bEndpointAddress) == \
-          usb.util.ENDPOINT_OUT
-    )
-
-    self._write_ep = write_ep
-    self._logger.debug("Writer endpoint: 0x%x", write_ep.bEndpointAddress)
-
-    self.clear_ina_struct()
-
-    self._logger.debug("Found power logging USB endpoint.")
-
-  def clear_ina_struct(self):
-    """ Clear INA description struct."""
-    self._inas = []
+CONFIG_LOCATIONS = [
+    os.getcwd(),
+    os.path.dirname(os.path.realpath(__file__)),
+    LIB_DIR,
+]
 
-  def append_ina_struct(self, name, rs, port, addr,
-                        data=None, ina_type=INA_POWER):
-    """Add an INA descriptor into the list of active INAs.
 
-    Args:
-      name:	Readable name of this channel.
-      rs:	Sense resistor value in ohms, floating point.
-      port:	I2C channel this INA is connected to.
-      addr: 	I2C addr of this INA.
-      data:	Misc data for special handling, board specific.
-      ina_type: INA function to use, power, voltage, etc.
-    """
-    ina = {}
-    ina['name'] = name
-    ina['rs'] = rs
-    ina['port'] = port
-    ina['addr'] = addr
-    ina['type'] = ina_type
-    # Calculate INA231 Calibration register
-    # (see INA231 spec p.15)
-    # CurrentLSB = uA per div = 80mV / (Rsh * 2^15)
-    # CurrentLSB uA = 80000000nV / (Rsh mOhm * 0x8000)
-    ina['uAscale'] = 80000000. / (rs * 0x8000);
-    ina['uWscale'] = 25. * ina['uAscale'];
-    ina['mVscale'] = 1.25
-    ina['uVscale'] = 2.5
-    ina['data'] = data
-    self._inas.append(ina)
-
-  def wr_command(self, write_list, read_count=1, wtimeout=100, rtimeout=1000):
-    """Write command to logger logic.
-
-    This function writes byte command values list to stm, then reads
-    byte status.
-
-    Args:
-      write_list: list of command byte values [0~255].
-      read_count: number of status byte values to read.
-
-    Interface:
-      write: [command, data ... ]
-      read: [status ]
-
-    Returns:
-      bytes read, or None on failure.
-    """
-    self._logger.debug("Spower.wr_command(write_list=[%s] (%d), read_count=%s)",
-                       list(bytearray(write_list)), len(write_list), read_count)
-
-    # Clean up args from python style to correct types.
-    write_length = 0
-    if write_list:
-      write_length = len(write_list)
-    if not read_count:
-      read_count = 0
-
-    # Send command to stm32.
-    if write_list:
-      cmd = write_list
-      ret = self._write_ep.write(cmd, wtimeout)
-
-    self._logger.debug("RET: %s ", ret)
-
-    # Read back response if necessary.
-    if read_count:
-      bytesread = self._read_ep.read(512, rtimeout)
-      self._logger.debug("BYTES: [%s]", bytesread)
-
-      if len(bytesread) != read_count:
-        pass
-
-      self._logger.debug("STATUS: 0x%02x", int(bytesread[0]))
-      if read_count == 1:
-        return bytesread[0]
-      else:
-        return bytesread
-
-    return None
-
-  def clear(self):
-    """Clear pending reads on the stm32"""
-    try:
-      while True:
-        ret = self.wr_command(b"", read_count=512, rtimeout=100, wtimeout=50)
-        self._logger.debug("Try Clear: read %s",
-                           "success" if ret == 0 else "failure")
-    except:
-      pass
-
-  def send_reset(self):
-    """Reset the power interface on the stm32"""
-    cmd = struct.pack("<H", self.CMD_RESET)
-    ret = self.wr_command(cmd, rtimeout=50, wtimeout=50)
-    self._logger.debug("Command RESET: %s",
-                       "success" if ret == 0 else "failure")
-
-  def reset(self):
-    """Try resetting the USB interface until success.
-
-    Use linear back off strategy when encounter the error with 10ms increment.
-
-    Raises:
-      Exception on failure.
-    """
-    max_reset_retry = 100
-    for count in range(1, max_reset_retry + 1):
-      self.clear()
-      try:
-        self.send_reset()
-        return
-      except Exception as e:
-        self.clear()
-        self.clear()
-        self._logger.debug("TRY %d of %d: %s", count, max_reset_retry, e)
-        time.sleep(count * 0.01)
-    raise Exception("Power", "Failed to reset")
-
-  def stop(self):
-    """Stop any active data acquisition."""
-    cmd = struct.pack("<H", self.CMD_STOP)
-    ret = self.wr_command(cmd)
-    self._logger.debug("Command STOP: %s",
-                       "success" if ret == 0 else "failure")
-
-  def start(self, integration_us):
-    """Start data acquisition.
-
-    Args:
-      integration_us: int, how many us between samples, and
-                      how often the data block must be read.
+def logoutput(msg):
+    print(msg)
+    sys.stdout.flush()
 
-    Returns:
-      actual sampling interval in ms.
-    """
-    cmd = struct.pack("<HI", self.CMD_START, integration_us)
-    read = self.wr_command(cmd, read_count=5)
-    actual_us = 0
-    if len(read) == 5:
-      ret, actual_us = struct.unpack("<BI", read)
-      self._logger.debug("Command START: %s %dus",
-               "success" if ret == 0 else "failure", actual_us)
-    else:
-      self._logger.debug("Command START: FAIL")
 
-    return actual_us
+def process_filename(filename):
+    """Find the file path from the filename.
 
-  def add_ina_name(self, name_tuple):
-    """Add INA from board config.
+    If filename is already the complete path, return that directly. If filename is
+    just the short name, look for the file in the current working directory, in
+    the directory of the current .py file, and then in the directory installed by
+    hdctools. If the file is found, return the complete path of the file.
 
     Args:
-      name_tuple:	name and type of power rail in board config.
+        filename: complete file path or short file name.
 
     Returns:
-      True if INA added, False if the INA is not on this board.
+        a complete file path.
 
     Raises:
-      Exception on unexpected failure.
+        IOError if filename does not exist.
     """
-    name, ina_type = name_tuple
-
-    for datum in self._brdcfg:
-      if datum["name"] == name:
-        rs = int(float(datum["rs"]) * 1000.)
-        board = datum["sweetberry"]
-
-        if board == self._board:
-          if 'port' in datum and 'addr' in datum:
-            port = datum['port']
-            addr = datum['addr']
-          else:
-            channel = int(datum["channel"])
-            port, addr = self.CHMAP[channel]
-          self.add_ina(port, ina_type, addr, 0, rs, data=datum)
-          return True
-        else:
-          return False
-    raise Exception("Power", "Failed to find INA %s" % name)
+    # Check if filename is absolute path.
+    if os.path.isabs(filename) and os.path.isfile(filename):
+        return filename
+    # Check if filename is relative to a known config location.
+    for dirname in CONFIG_LOCATIONS:
+        file_at_dir = os.path.join(dirname, filename)
+        if os.path.isfile(file_at_dir):
+            return file_at_dir
+    raise IOError("No such file or directory: '%s'" % filename)
 
-  def set_time(self, timestamp_us):
-    """Set sweetberry time to match host time.
 
-    Args:
-      timestamp_us: host timestmap in us.
-    """
-    # 0x0005 , 8 byte timestamp
-    cmd = struct.pack("<HQ", self.CMD_SETTIME, timestamp_us)
-    ret = self.wr_command(cmd)
-
-    self._logger.debug("Command SETTIME: %s",
-                       "success" if ret == 0 else "failure")
+class Spower(object):
+    """Power class to access devices on the bus.
 
-  def add_ina(self, bus, ina_type, addr, extra, resistance, data=None):
-    """Add an INA to the data acquisition list.
+    Usage:
+      bus = Spower()
 
-    Args:
-      bus: which i2c bus the INA is on. Same ordering as Si2c.
-      ina_type: Ina interface: INA_POWER/BUSV/etc.
-      addr: 7 bit i2c addr of this INA
-      extra: extra data for nonstandard configs.
-      resistance: int, shunt resistance in mOhm
+    Instance Variables:
+      _dev: pyUSB device object
+      _read_ep: pyUSB read endpoint for this interface
+      _write_ep: pyUSB write endpoint for this interface
     """
-    # 0x0002, 1B: bus, 1B:INA type, 1B: INA addr, 1B: extra, 4B: Rs
-    cmd = struct.pack("<HBBBBI", self.CMD_ADDINA,
-                      bus, ina_type, addr, extra, resistance)
-    ret = self.wr_command(cmd)
-    if ret == 0:
-      if data:
-        name = data['name']
-      else:
-        name = "ina%d_%02x" % (bus, addr)
-      self.append_ina_struct(name, resistance, bus, addr,
-                             data=data, ina_type=ina_type)
-    self._logger.debug("Command ADD_INA: %s",
-                       "success" if ret == 0 else "failure")
-
-  def report_header_size(self):
-    """Helper function to calculate power record header size."""
-    result = 2
-    timestamp = 8
-    return result + timestamp
-
-  def report_size(self, ina_count):
-    """Helper function to calculate full power record size."""
-    record = 2
-
-    datasize = self.report_header_size() + ina_count * record
-    # Round to multiple of 4 bytes.
-    datasize = int(((datasize + 3) // 4) * 4)
-
-    return datasize
-
-  def read_line(self):
-    """Read a line of data from the setup INAs
 
-    Returns:
-      list of dicts of the values read by ina/type tuple, otherwise None.
-      [{ts:100, (vbat, power):450}, {ts:200, (vbat, power):440}]
-    """
-    try:
-      expected_bytes = self.report_size(len(self._inas))
-      cmd = struct.pack("<H", self.CMD_NEXT)
-      bytesread = self.wr_command(cmd, read_count=expected_bytes)
-    except usb.core.USBError as e:
-      self._logger.error("READ LINE FAILED %s", e)
-      return None
-
-    if len(bytesread) == 1:
-      if bytesread[0] != 0x6:
-        self._logger.debug("READ LINE FAILED bytes: %d ret: %02x",
-                           len(bytesread), bytesread[0])
-      return None
-
-    if len(bytesread) % expected_bytes != 0:
-      self._logger.debug("READ LINE WARNING: expected %d, got %d",
-          expected_bytes, len(bytesread))
-
-    packet_count = len(bytesread) // expected_bytes
-
-    values = []
-    for i in range(0, packet_count):
-      start = i * expected_bytes
-      end = (i + 1) * expected_bytes
-      record = self.interpret_line(bytesread[start:end])
-      values.append(record)
-
-    return values
-
-  def interpret_line(self, data):
-    """Interpret a power record from INAs
+    # INA interface type.
+    INA_POWER = 1
+    INA_BUSV = 2
+    INA_CURRENT = 3
+    INA_SHUNTV = 4
+    # INA_SUFFIX is used to differentiate multiple ina types for the same power
+    # rail. No suffix for when ina type is 0 (non-existent) and when ina type is 1
+    # (power, no suffix for backward compatibility).
+    INA_SUFFIX = ["", "", "_busv", "_cur", "_shuntv"]
+
+    # usb power commands
+    CMD_RESET = 0x0000
+    CMD_STOP = 0x0001
+    CMD_ADDINA = 0x0002
+    CMD_START = 0x0003
+    CMD_NEXT = 0x0004
+    CMD_SETTIME = 0x0005
+
+    # Map between header channel number (0-47)
+    # and INA I2C bus/addr on sweetberry.
+    CHMAP = {
+        0: (3, 0x40),
+        1: (1, 0x40),
+        2: (2, 0x40),
+        3: (0, 0x40),
+        4: (3, 0x41),
+        5: (1, 0x41),
+        6: (2, 0x41),
+        7: (0, 0x41),
+        8: (3, 0x42),
+        9: (1, 0x42),
+        10: (2, 0x42),
+        11: (0, 0x42),
+        12: (3, 0x43),
+        13: (1, 0x43),
+        14: (2, 0x43),
+        15: (0, 0x43),
+        16: (3, 0x44),
+        17: (1, 0x44),
+        18: (2, 0x44),
+        19: (0, 0x44),
+        20: (3, 0x45),
+        21: (1, 0x45),
+        22: (2, 0x45),
+        23: (0, 0x45),
+        24: (3, 0x46),
+        25: (1, 0x46),
+        26: (2, 0x46),
+        27: (0, 0x46),
+        28: (3, 0x47),
+        29: (1, 0x47),
+        30: (2, 0x47),
+        31: (0, 0x47),
+        32: (3, 0x48),
+        33: (1, 0x48),
+        34: (2, 0x48),
+        35: (0, 0x48),
+        36: (3, 0x49),
+        37: (1, 0x49),
+        38: (2, 0x49),
+        39: (0, 0x49),
+        40: (3, 0x4A),
+        41: (1, 0x4A),
+        42: (2, 0x4A),
+        43: (0, 0x4A),
+        44: (3, 0x4B),
+        45: (1, 0x4B),
+        46: (2, 0x4B),
+        47: (0, 0x4B),
+    }
+
+    def __init__(
+        self, board, vendor=0x18D1, product=0x5020, interface=1, serialname=None
+    ):
+        self._logger = logging.getLogger(__name__)
+        self._board = board
+
+        # Find the stm32.
+        dev_g = usb.core.find(idVendor=vendor, idProduct=product, find_all=True)
+        dev_list = list(dev_g)
+        if dev_list is None:
+            raise Exception("Power", "USB device not found")
+
+        # Check if we have multiple stm32s and we've specified the serial.
+        dev = None
+        if serialname:
+            for d in dev_list:
+                dev_serial = "PyUSB dioesn't have a stable interface"
+                try:
+                    dev_serial = usb.util.get_string(d, 256, d.iSerialNumber)
+                except ValueError:
+                    # Incompatible pyUsb version.
+                    dev_serial = usb.util.get_string(d, d.iSerialNumber)
+                if dev_serial == serialname:
+                    dev = d
+                    break
+            if dev is None:
+                raise Exception(
+                    "Power", "USB device(%s) not found" % serialname
+                )
+        else:
+            dev = dev_list[0]
 
-    Args:
-      data: one single record of bytes.
+        self._logger.debug("Found USB device: %04x:%04x", vendor, product)
+        self._dev = dev
 
-    Output:
-      stdout of the record in csv format.
+        # Get an endpoint instance.
+        try:
+            dev.set_configuration()
+        except usb.USBError:
+            pass
+        cfg = dev.get_active_configuration()
+
+        intf = usb.util.find_descriptor(
+            cfg,
+            custom_match=lambda i: i.bInterfaceClass == 255
+            and i.bInterfaceSubClass == 0x54,
+        )
+
+        self._intf = intf
+        self._logger.debug("InterfaceNumber: %s", intf.bInterfaceNumber)
+
+        read_ep = usb.util.find_descriptor(
+            intf,
+            # match the first IN endpoint
+            custom_match=lambda e: usb.util.endpoint_direction(
+                e.bEndpointAddress
+            )
+            == usb.util.ENDPOINT_IN,
+        )
+
+        self._read_ep = read_ep
+        self._logger.debug("Reader endpoint: 0x%x", read_ep.bEndpointAddress)
+
+        write_ep = usb.util.find_descriptor(
+            intf,
+            # match the first OUT endpoint
+            custom_match=lambda e: usb.util.endpoint_direction(
+                e.bEndpointAddress
+            )
+            == usb.util.ENDPOINT_OUT,
+        )
+
+        self._write_ep = write_ep
+        self._logger.debug("Writer endpoint: 0x%x", write_ep.bEndpointAddress)
+
+        self.clear_ina_struct()
+
+        self._logger.debug("Found power logging USB endpoint.")
+
+    def clear_ina_struct(self):
+        """Clear INA description struct."""
+        self._inas = []
+
+    def append_ina_struct(
+        self, name, rs, port, addr, data=None, ina_type=INA_POWER
+    ):
+        """Add an INA descriptor into the list of active INAs.
+
+        Args:
+          name:	Readable name of this channel.
+          rs:	Sense resistor value in ohms, floating point.
+          port:	I2C channel this INA is connected to.
+          addr: 	I2C addr of this INA.
+          data:	Misc data for special handling, board specific.
+          ina_type: INA function to use, power, voltage, etc.
+        """
+        ina = {}
+        ina["name"] = name
+        ina["rs"] = rs
+        ina["port"] = port
+        ina["addr"] = addr
+        ina["type"] = ina_type
+        # Calculate INA231 Calibration register
+        # (see INA231 spec p.15)
+        # CurrentLSB = uA per div = 80mV / (Rsh * 2^15)
+        # CurrentLSB uA = 80000000nV / (Rsh mOhm * 0x8000)
+        ina["uAscale"] = 80000000.0 / (rs * 0x8000)
+        ina["uWscale"] = 25.0 * ina["uAscale"]
+        ina["mVscale"] = 1.25
+        ina["uVscale"] = 2.5
+        ina["data"] = data
+        self._inas.append(ina)
+
+    def wr_command(self, write_list, read_count=1, wtimeout=100, rtimeout=1000):
+        """Write command to logger logic.
+
+        This function writes byte command values list to stm, then reads
+        byte status.
+
+        Args:
+          write_list: list of command byte values [0~255].
+          read_count: number of status byte values to read.
+
+        Interface:
+          write: [command, data ... ]
+          read: [status ]
+
+        Returns:
+          bytes read, or None on failure.
+        """
+        self._logger.debug(
+            "Spower.wr_command(write_list=[%s] (%d), read_count=%s)",
+            list(bytearray(write_list)),
+            len(write_list),
+            read_count,
+        )
+
+        # Clean up args from python style to correct types.
+        write_length = 0
+        if write_list:
+            write_length = len(write_list)
+        if not read_count:
+            read_count = 0
+
+        # Send command to stm32.
+        if write_list:
+            cmd = write_list
+            ret = self._write_ep.write(cmd, wtimeout)
+
+        self._logger.debug("RET: %s ", ret)
+
+        # Read back response if necessary.
+        if read_count:
+            bytesread = self._read_ep.read(512, rtimeout)
+            self._logger.debug("BYTES: [%s]", bytesread)
+
+            if len(bytesread) != read_count:
+                pass
+
+            self._logger.debug("STATUS: 0x%02x", int(bytesread[0]))
+            if read_count == 1:
+                return bytesread[0]
+            else:
+                return bytesread
+
+        return None
+
+    def clear(self):
+        """Clear pending reads on the stm32"""
+        try:
+            while True:
+                ret = self.wr_command(
+                    b"", read_count=512, rtimeout=100, wtimeout=50
+                )
+                self._logger.debug(
+                    "Try Clear: read %s", "success" if ret == 0 else "failure"
+                )
+        except:
+            pass
+
+    def send_reset(self):
+        """Reset the power interface on the stm32"""
+        cmd = struct.pack("<H", self.CMD_RESET)
+        ret = self.wr_command(cmd, rtimeout=50, wtimeout=50)
+        self._logger.debug(
+            "Command RESET: %s", "success" if ret == 0 else "failure"
+        )
+
+    def reset(self):
+        """Try resetting the USB interface until success.
+
+        Use linear back off strategy when encounter the error with 10ms increment.
+
+        Raises:
+          Exception on failure.
+        """
+        max_reset_retry = 100
+        for count in range(1, max_reset_retry + 1):
+            self.clear()
+            try:
+                self.send_reset()
+                return
+            except Exception as e:
+                self.clear()
+                self.clear()
+                self._logger.debug(
+                    "TRY %d of %d: %s", count, max_reset_retry, e
+                )
+                time.sleep(count * 0.01)
+        raise Exception("Power", "Failed to reset")
+
+    def stop(self):
+        """Stop any active data acquisition."""
+        cmd = struct.pack("<H", self.CMD_STOP)
+        ret = self.wr_command(cmd)
+        self._logger.debug(
+            "Command STOP: %s", "success" if ret == 0 else "failure"
+        )
+
+    def start(self, integration_us):
+        """Start data acquisition.
+
+        Args:
+          integration_us: int, how many us between samples, and
+                          how often the data block must be read.
+
+        Returns:
+          actual sampling interval in ms.
+        """
+        cmd = struct.pack("<HI", self.CMD_START, integration_us)
+        read = self.wr_command(cmd, read_count=5)
+        actual_us = 0
+        if len(read) == 5:
+            ret, actual_us = struct.unpack("<BI", read)
+            self._logger.debug(
+                "Command START: %s %dus",
+                "success" if ret == 0 else "failure",
+                actual_us,
+            )
+        else:
+            self._logger.debug("Command START: FAIL")
+
+        return actual_us
+
+    def add_ina_name(self, name_tuple):
+        """Add INA from board config.
+
+        Args:
+          name_tuple:	name and type of power rail in board config.
+
+        Returns:
+          True if INA added, False if the INA is not on this board.
+
+        Raises:
+          Exception on unexpected failure.
+        """
+        name, ina_type = name_tuple
+
+        for datum in self._brdcfg:
+            if datum["name"] == name:
+                rs = int(float(datum["rs"]) * 1000.0)
+                board = datum["sweetberry"]
+
+                if board == self._board:
+                    if "port" in datum and "addr" in datum:
+                        port = datum["port"]
+                        addr = datum["addr"]
+                    else:
+                        channel = int(datum["channel"])
+                        port, addr = self.CHMAP[channel]
+                    self.add_ina(port, ina_type, addr, 0, rs, data=datum)
+                    return True
+                else:
+                    return False
+        raise Exception("Power", "Failed to find INA %s" % name)
+
+    def set_time(self, timestamp_us):
+        """Set sweetberry time to match host time.
+
+        Args:
+          timestamp_us: host timestmap in us.
+        """
+        # 0x0005 , 8 byte timestamp
+        cmd = struct.pack("<HQ", self.CMD_SETTIME, timestamp_us)
+        ret = self.wr_command(cmd)
+
+        self._logger.debug(
+            "Command SETTIME: %s", "success" if ret == 0 else "failure"
+        )
+
+    def add_ina(self, bus, ina_type, addr, extra, resistance, data=None):
+        """Add an INA to the data acquisition list.
+
+        Args:
+          bus: which i2c bus the INA is on. Same ordering as Si2c.
+          ina_type: Ina interface: INA_POWER/BUSV/etc.
+          addr: 7 bit i2c addr of this INA
+          extra: extra data for nonstandard configs.
+          resistance: int, shunt resistance in mOhm
+        """
+        # 0x0002, 1B: bus, 1B:INA type, 1B: INA addr, 1B: extra, 4B: Rs
+        cmd = struct.pack(
+            "<HBBBBI", self.CMD_ADDINA, bus, ina_type, addr, extra, resistance
+        )
+        ret = self.wr_command(cmd)
+        if ret == 0:
+            if data:
+                name = data["name"]
+            else:
+                name = "ina%d_%02x" % (bus, addr)
+            self.append_ina_struct(
+                name, resistance, bus, addr, data=data, ina_type=ina_type
+            )
+        self._logger.debug(
+            "Command ADD_INA: %s", "success" if ret == 0 else "failure"
+        )
+
+    def report_header_size(self):
+        """Helper function to calculate power record header size."""
+        result = 2
+        timestamp = 8
+        return result + timestamp
+
+    def report_size(self, ina_count):
+        """Helper function to calculate full power record size."""
+        record = 2
+
+        datasize = self.report_header_size() + ina_count * record
+        # Round to multiple of 4 bytes.
+        datasize = int(((datasize + 3) // 4) * 4)
+
+        return datasize
+
+    def read_line(self):
+        """Read a line of data from the setup INAs
+
+        Returns:
+          list of dicts of the values read by ina/type tuple, otherwise None.
+          [{ts:100, (vbat, power):450}, {ts:200, (vbat, power):440}]
+        """
+        try:
+            expected_bytes = self.report_size(len(self._inas))
+            cmd = struct.pack("<H", self.CMD_NEXT)
+            bytesread = self.wr_command(cmd, read_count=expected_bytes)
+        except usb.core.USBError as e:
+            self._logger.error("READ LINE FAILED %s", e)
+            return None
+
+        if len(bytesread) == 1:
+            if bytesread[0] != 0x6:
+                self._logger.debug(
+                    "READ LINE FAILED bytes: %d ret: %02x",
+                    len(bytesread),
+                    bytesread[0],
+                )
+            return None
+
+        if len(bytesread) % expected_bytes != 0:
+            self._logger.debug(
+                "READ LINE WARNING: expected %d, got %d",
+                expected_bytes,
+                len(bytesread),
+            )
+
+        packet_count = len(bytesread) // expected_bytes
+
+        values = []
+        for i in range(0, packet_count):
+            start = i * expected_bytes
+            end = (i + 1) * expected_bytes
+            record = self.interpret_line(bytesread[start:end])
+            values.append(record)
+
+        return values
+
+    def interpret_line(self, data):
+        """Interpret a power record from INAs
+
+        Args:
+          data: one single record of bytes.
+
+        Output:
+          stdout of the record in csv format.
+
+        Returns:
+          dict containing name, value of recorded data.
+        """
+        status, size = struct.unpack("<BB", data[0:2])
+        if len(data) != self.report_size(size):
+            self._logger.error(
+                "READ LINE FAILED st:%d size:%d expected:%d len:%d",
+                status,
+                size,
+                self.report_size(size),
+                len(data),
+            )
+        else:
+            pass
 
-    Returns:
-      dict containing name, value of recorded data.
-    """
-    status, size = struct.unpack("<BB", data[0:2])
-    if len(data) != self.report_size(size):
-      self._logger.error("READ LINE FAILED st:%d size:%d expected:%d len:%d",
-                         status, size, self.report_size(size), len(data))
-    else:
-      pass
+        timestamp = struct.unpack("<Q", data[2:10])[0]
+        self._logger.debug(
+            "READ LINE: st:%d size:%d time:%dus", status, size, timestamp
+        )
+        ftimestamp = float(timestamp) / 1000000.0
 
-    timestamp = struct.unpack("<Q", data[2:10])[0]
-    self._logger.debug("READ LINE: st:%d size:%d time:%dus", status, size,
-                       timestamp)
-    ftimestamp = float(timestamp) / 1000000.
+        record = {"ts": ftimestamp, "status": status, "berry": self._board}
 
-    record = {"ts": ftimestamp, "status": status, "berry":self._board}
+        for i in range(0, size):
+            idx = self.report_header_size() + 2 * i
+            name = self._inas[i]["name"]
+            name_tuple = (self._inas[i]["name"], self._inas[i]["type"])
 
-    for i in range(0, size):
-      idx = self.report_header_size() + 2*i
-      name = self._inas[i]['name']
-      name_tuple = (self._inas[i]['name'], self._inas[i]['type'])
+            raw_val = struct.unpack("<h", data[idx : idx + 2])[0]
 
-      raw_val = struct.unpack("<h", data[idx:idx+2])[0]
+            if self._inas[i]["type"] == Spower.INA_POWER:
+                val = raw_val * self._inas[i]["uWscale"]
+            elif self._inas[i]["type"] == Spower.INA_BUSV:
+                val = raw_val * self._inas[i]["mVscale"]
+            elif self._inas[i]["type"] == Spower.INA_CURRENT:
+                val = raw_val * self._inas[i]["uAscale"]
+            elif self._inas[i]["type"] == Spower.INA_SHUNTV:
+                val = raw_val * self._inas[i]["uVscale"]
 
-      if self._inas[i]['type'] == Spower.INA_POWER:
-        val = raw_val * self._inas[i]['uWscale']
-      elif self._inas[i]['type'] == Spower.INA_BUSV:
-        val = raw_val * self._inas[i]['mVscale']
-      elif self._inas[i]['type'] == Spower.INA_CURRENT:
-        val = raw_val * self._inas[i]['uAscale']
-      elif self._inas[i]['type'] == Spower.INA_SHUNTV:
-        val = raw_val * self._inas[i]['uVscale']
+            self._logger.debug(
+                "READ %d %s: %fs: 0x%04x %f", i, name, ftimestamp, raw_val, val
+            )
+            record[name_tuple] = val
 
-      self._logger.debug("READ %d %s: %fs: 0x%04x %f", i, name, ftimestamp,
-                         raw_val, val)
-      record[name_tuple] = val
+        return record
 
-    return record
+    def load_board(self, brdfile):
+        """Load a board config.
 
-  def load_board(self, brdfile):
-    """Load a board config.
+        Args:
+          brdfile:	Filename of a json file decribing the INA wiring of this board.
+        """
+        with open(process_filename(brdfile)) as data_file:
+            data = json.load(data_file)
 
-    Args:
-      brdfile:	Filename of a json file decribing the INA wiring of this board.
-    """
-    with open(process_filename(brdfile)) as data_file:
-        data = json.load(data_file)
-
-    #TODO: validate this.
-    self._brdcfg = data;
-    self._logger.debug(pprint.pformat(data))
+        # TODO: validate this.
+        self._brdcfg = data
+        self._logger.debug(pprint.pformat(data))
 
 
 class powerlog(object):
-  """Power class to log aggregated power.
-
-  Usage:
-    obj = powerlog()
-
-  Instance Variables:
-    _data: a StatsManager object that records sweetberry readings and calculates
-           statistics.
-    _pwr[]: Spower objects for individual sweetberries.
-  """
+    """Power class to log aggregated power.
 
-  def __init__(self, brdfile, cfgfile, serial_a=None, serial_b=None,
-               sync_date=False, use_ms=False, use_mW=False, print_stats=False,
-               stats_dir=None, stats_json_dir=None, print_raw_data=True,
-               raw_data_dir=None):
-    """Init the powerlog class and set the variables.
-
-    Args:
-      brdfile: string name of json file containing board layout.
-      cfgfile: string name of json containing list of rails to read.
-      serial_a: serial number of sweetberry A.
-      serial_b: serial number of sweetberry B.
-      sync_date: report timestamps synced with host datetime.
-      use_ms: report timestamps in ms rather than us.
-      use_mW: report power as milliwatts, otherwise default to microwatts.
-      print_stats: print statistics for sweetberry readings at the end.
-      stats_dir: directory to save sweetberry readings statistics; if None then
-                 do not save the statistics.
-      stats_json_dir: directory to save means of sweetberry readings in json
-                      format; if None then do not save the statistics.
-      print_raw_data: print sweetberry readings raw data in real time, default
-                      is to print.
-      raw_data_dir: directory to save sweetberry readings raw data; if None then
-                    do not save the raw data.
-    """
-    self._logger = logging.getLogger(__name__)
-    self._data = StatsManager()
-    self._pwr = {}
-    self._use_ms = use_ms
-    self._use_mW = use_mW
-    self._print_stats = print_stats
-    self._stats_dir = stats_dir
-    self._stats_json_dir = stats_json_dir
-    self._print_raw_data = print_raw_data
-    self._raw_data_dir = raw_data_dir
-
-    if not serial_a and not serial_b:
-      self._pwr['A'] = Spower('A')
-    if serial_a:
-      self._pwr['A'] = Spower('A', serialname=serial_a)
-    if serial_b:
-      self._pwr['B'] = Spower('B', serialname=serial_b)
-
-    with open(process_filename(cfgfile)) as data_file:
-      names = json.load(data_file)
-    self._names = self.process_scenario(names)
-
-    for key in self._pwr:
-      self._pwr[key].load_board(brdfile)
-      self._pwr[key].reset()
-
-    # Allocate the rails to the appropriate boards.
-    used_boards = []
-    for name in self._names:
-      success = False
-      for key in self._pwr.keys():
-        if self._pwr[key].add_ina_name(name):
-          success = True
-          if key not in used_boards:
-            used_boards.append(key)
-      if not success:
-        raise Exception("Failed to add %s (maybe missing "
-                        "sweetberry, or bad board file?)" % name)
-
-    # Evict unused boards.
-    for key in list(self._pwr.keys()):
-      if key not in used_boards:
-        self._pwr.pop(key)
-
-    for key in self._pwr.keys():
-      if sync_date:
-        self._pwr[key].set_time(time.time() * 1000000)
-      else:
-        self._pwr[key].set_time(0)
-
-  def process_scenario(self, name_list):
-    """Return list of tuples indicating name and type.
+    Usage:
+      obj = powerlog()
 
-    Args:
-      json originated list of names, or [name, type]
-    Returns:
-      list of tuples of (name, type) defaulting to type "POWER"
-    Raises: exception, invalid INA type.
+    Instance Variables:
+      _data: a StatsManager object that records sweetberry readings and calculates
+             statistics.
+      _pwr[]: Spower objects for individual sweetberries.
     """
-    names = []
-    for entry in name_list:
-      if isinstance(entry, list):
-        name = entry[0]
-        if entry[1] == "POWER":
-          type = Spower.INA_POWER
-        elif entry[1] == "BUSV":
-          type = Spower.INA_BUSV
-        elif entry[1] == "CURRENT":
-          type = Spower.INA_CURRENT
-        elif entry[1] == "SHUNTV":
-          type = Spower.INA_SHUNTV
-        else:
-          raise Exception("Invalid INA type", "Type of %s [%s] not recognized,"
-                    " try one of POWER, BUSV, CURRENT" % (entry[0], entry[1]))
-      else:
-        name = entry
-        type = Spower.INA_POWER
 
-      names.append((name, type))
-    return names
+    def __init__(
+        self,
+        brdfile,
+        cfgfile,
+        serial_a=None,
+        serial_b=None,
+        sync_date=False,
+        use_ms=False,
+        use_mW=False,
+        print_stats=False,
+        stats_dir=None,
+        stats_json_dir=None,
+        print_raw_data=True,
+        raw_data_dir=None,
+    ):
+        """Init the powerlog class and set the variables.
+
+        Args:
+          brdfile: string name of json file containing board layout.
+          cfgfile: string name of json containing list of rails to read.
+          serial_a: serial number of sweetberry A.
+          serial_b: serial number of sweetberry B.
+          sync_date: report timestamps synced with host datetime.
+          use_ms: report timestamps in ms rather than us.
+          use_mW: report power as milliwatts, otherwise default to microwatts.
+          print_stats: print statistics for sweetberry readings at the end.
+          stats_dir: directory to save sweetberry readings statistics; if None then
+                     do not save the statistics.
+          stats_json_dir: directory to save means of sweetberry readings in json
+                          format; if None then do not save the statistics.
+          print_raw_data: print sweetberry readings raw data in real time, default
+                          is to print.
+          raw_data_dir: directory to save sweetberry readings raw data; if None then
+                        do not save the raw data.
+        """
+        self._logger = logging.getLogger(__name__)
+        self._data = StatsManager()
+        self._pwr = {}
+        self._use_ms = use_ms
+        self._use_mW = use_mW
+        self._print_stats = print_stats
+        self._stats_dir = stats_dir
+        self._stats_json_dir = stats_json_dir
+        self._print_raw_data = print_raw_data
+        self._raw_data_dir = raw_data_dir
+
+        if not serial_a and not serial_b:
+            self._pwr["A"] = Spower("A")
+        if serial_a:
+            self._pwr["A"] = Spower("A", serialname=serial_a)
+        if serial_b:
+            self._pwr["B"] = Spower("B", serialname=serial_b)
+
+        with open(process_filename(cfgfile)) as data_file:
+            names = json.load(data_file)
+        self._names = self.process_scenario(names)
 
-  def start(self, integration_us_request, seconds, sync_speed=.8):
-    """Starts sampling.
-
-    Args:
-      integration_us_request: requested interval between sample values.
-      seconds: time until exit, or None to run until cancel.
-      sync_speed: A usb request is sent every [.8] * integration_us.
-    """
-    # We will get back the actual integration us.
-    # It should be the same for all devices.
-    integration_us = None
-    for key in self._pwr:
-      integration_us_new = self._pwr[key].start(integration_us_request)
-      if integration_us:
-        if integration_us != integration_us_new:
-          raise Exception("FAIL",
-              "Integration on A: %dus != integration on B %dus" % (
-              integration_us, integration_us_new))
-      integration_us = integration_us_new
-
-    # CSV header
-    title = "ts:%dus" % integration_us
-    for name_tuple in self._names:
-      name, ina_type = name_tuple
-
-      if ina_type == Spower.INA_POWER:
-        unit = "mW" if self._use_mW else "uW"
-      elif ina_type == Spower.INA_BUSV:
-        unit = "mV"
-      elif ina_type == Spower.INA_CURRENT:
-        unit = "uA"
-      elif ina_type == Spower.INA_SHUNTV:
-        unit = "uV"
-
-      title += ", %s %s" % (name, unit)
-      name_type = name + Spower.INA_SUFFIX[ina_type]
-      self._data.SetUnit(name_type, unit)
-    title += ", status"
-    if self._print_raw_data:
-      logoutput(title)
-
-    forever = False
-    if not seconds:
-      forever = True
-    end_time = time.time() + seconds
-    try:
-      pending_records = []
-      while forever or end_time > time.time():
-        if (integration_us > 5000):
-          time.sleep((integration_us / 1000000.) * sync_speed)
         for key in self._pwr:
-          records = self._pwr[key].read_line()
-          if not records:
-            continue
-
-          for record in records:
-            pending_records.append(record)
-
-        pending_records.sort(key=lambda r: r['ts'])
-
-        aggregate_record = {"boards": set()}
-        for record in pending_records:
-          if record["berry"] not in aggregate_record["boards"]:
-            for rkey in record.keys():
-              aggregate_record[rkey] = record[rkey]
-            aggregate_record["boards"].add(record["berry"])
-          else:
-            self._logger.info("break %s, %s", record["berry"],
-                              aggregate_record["boards"])
-            break
-
-          if aggregate_record["boards"] == set(self._pwr.keys()):
-            csv = "%f" % aggregate_record["ts"]
-            for name in self._names:
-              if name in aggregate_record:
-                multiplier = 0.001 if (self._use_mW and
-                    name[1]==Spower.INA_POWER) else 1
-                value = aggregate_record[name] * multiplier
-                csv += ", %.2f" % value
-                name_type = name[0] + Spower.INA_SUFFIX[name[1]]
-                self._data.AddSample(name_type, value)
-              else:
-                csv += ", "
-            csv += ", %d" % aggregate_record["status"]
-            if self._print_raw_data:
-              logoutput(csv)
-
-            aggregate_record = {"boards": set()}
-            for r in range(0, len(self._pwr)):
-              pending_records.pop(0)
-
-    except KeyboardInterrupt:
-      self._logger.info('\nCTRL+C caught.')
-
-    finally:
-      for key in self._pwr:
-        self._pwr[key].stop()
-      self._data.CalculateStats()
-      if self._print_stats:
-        print(self._data.SummaryToString())
-      save_dir = 'sweetberry%s' % time.time()
-      if self._stats_dir:
-        stats_dir = os.path.join(self._stats_dir, save_dir)
-        self._data.SaveSummary(stats_dir)
-      if self._stats_json_dir:
-        stats_json_dir = os.path.join(self._stats_json_dir, save_dir)
-        self._data.SaveSummaryJSON(stats_json_dir)
-      if self._raw_data_dir:
-        raw_data_dir = os.path.join(self._raw_data_dir, save_dir)
-        self._data.SaveRawData(raw_data_dir)
+            self._pwr[key].load_board(brdfile)
+            self._pwr[key].reset()
+
+        # Allocate the rails to the appropriate boards.
+        used_boards = []
+        for name in self._names:
+            success = False
+            for key in self._pwr.keys():
+                if self._pwr[key].add_ina_name(name):
+                    success = True
+                    if key not in used_boards:
+                        used_boards.append(key)
+            if not success:
+                raise Exception(
+                    "Failed to add %s (maybe missing "
+                    "sweetberry, or bad board file?)" % name
+                )
+
+        # Evict unused boards.
+        for key in list(self._pwr.keys()):
+            if key not in used_boards:
+                self._pwr.pop(key)
+
+        for key in self._pwr.keys():
+            if sync_date:
+                self._pwr[key].set_time(time.time() * 1000000)
+            else:
+                self._pwr[key].set_time(0)
+
+    def process_scenario(self, name_list):
+        """Return list of tuples indicating name and type.
+
+        Args:
+          json originated list of names, or [name, type]
+        Returns:
+          list of tuples of (name, type) defaulting to type "POWER"
+        Raises: exception, invalid INA type.
+        """
+        names = []
+        for entry in name_list:
+            if isinstance(entry, list):
+                name = entry[0]
+                if entry[1] == "POWER":
+                    type = Spower.INA_POWER
+                elif entry[1] == "BUSV":
+                    type = Spower.INA_BUSV
+                elif entry[1] == "CURRENT":
+                    type = Spower.INA_CURRENT
+                elif entry[1] == "SHUNTV":
+                    type = Spower.INA_SHUNTV
+                else:
+                    raise Exception(
+                        "Invalid INA type",
+                        "Type of %s [%s] not recognized,"
+                        " try one of POWER, BUSV, CURRENT"
+                        % (entry[0], entry[1]),
+                    )
+            else:
+                name = entry
+                type = Spower.INA_POWER
+
+            names.append((name, type))
+        return names
+
+    def start(self, integration_us_request, seconds, sync_speed=0.8):
+        """Starts sampling.
+
+        Args:
+          integration_us_request: requested interval between sample values.
+          seconds: time until exit, or None to run until cancel.
+          sync_speed: A usb request is sent every [.8] * integration_us.
+        """
+        # We will get back the actual integration us.
+        # It should be the same for all devices.
+        integration_us = None
+        for key in self._pwr:
+            integration_us_new = self._pwr[key].start(integration_us_request)
+            if integration_us:
+                if integration_us != integration_us_new:
+                    raise Exception(
+                        "FAIL",
+                        # pylint:disable=bad-string-format-type
+                        "Integration on A: %dus != integration on B %dus"
+                        % (integration_us, integration_us_new),
+                    )
+            integration_us = integration_us_new
+
+        # CSV header
+        title = "ts:%dus" % integration_us
+        for name_tuple in self._names:
+            name, ina_type = name_tuple
+
+            if ina_type == Spower.INA_POWER:
+                unit = "mW" if self._use_mW else "uW"
+            elif ina_type == Spower.INA_BUSV:
+                unit = "mV"
+            elif ina_type == Spower.INA_CURRENT:
+                unit = "uA"
+            elif ina_type == Spower.INA_SHUNTV:
+                unit = "uV"
+
+            title += ", %s %s" % (name, unit)
+            name_type = name + Spower.INA_SUFFIX[ina_type]
+            self._data.SetUnit(name_type, unit)
+        title += ", status"
+        if self._print_raw_data:
+            logoutput(title)
+
+        forever = False
+        if not seconds:
+            forever = True
+        end_time = time.time() + seconds
+        try:
+            pending_records = []
+            while forever or end_time > time.time():
+                if integration_us > 5000:
+                    time.sleep((integration_us / 1000000.0) * sync_speed)
+                for key in self._pwr:
+                    records = self._pwr[key].read_line()
+                    if not records:
+                        continue
+
+                    for record in records:
+                        pending_records.append(record)
+
+                pending_records.sort(key=lambda r: r["ts"])
+
+                aggregate_record = {"boards": set()}
+                for record in pending_records:
+                    if record["berry"] not in aggregate_record["boards"]:
+                        for rkey in record.keys():
+                            aggregate_record[rkey] = record[rkey]
+                        aggregate_record["boards"].add(record["berry"])
+                    else:
+                        self._logger.info(
+                            "break %s, %s",
+                            record["berry"],
+                            aggregate_record["boards"],
+                        )
+                        break
+
+                    if aggregate_record["boards"] == set(self._pwr.keys()):
+                        csv = "%f" % aggregate_record["ts"]
+                        for name in self._names:
+                            if name in aggregate_record:
+                                multiplier = (
+                                    0.001
+                                    if (
+                                        self._use_mW
+                                        and name[1] == Spower.INA_POWER
+                                    )
+                                    else 1
+                                )
+                                value = aggregate_record[name] * multiplier
+                                csv += ", %.2f" % value
+                                name_type = name[0] + Spower.INA_SUFFIX[name[1]]
+                                self._data.AddSample(name_type, value)
+                            else:
+                                csv += ", "
+                        csv += ", %d" % aggregate_record["status"]
+                        if self._print_raw_data:
+                            logoutput(csv)
+
+                        aggregate_record = {"boards": set()}
+                        for r in range(0, len(self._pwr)):
+                            pending_records.pop(0)
+
+        except KeyboardInterrupt:
+            self._logger.info("\nCTRL+C caught.")
+
+        finally:
+            for key in self._pwr:
+                self._pwr[key].stop()
+            self._data.CalculateStats()
+            if self._print_stats:
+                print(self._data.SummaryToString())
+            save_dir = "sweetberry%s" % time.time()
+            if self._stats_dir:
+                stats_dir = os.path.join(self._stats_dir, save_dir)
+                self._data.SaveSummary(stats_dir)
+            if self._stats_json_dir:
+                stats_json_dir = os.path.join(self._stats_json_dir, save_dir)
+                self._data.SaveSummaryJSON(stats_json_dir)
+            if self._raw_data_dir:
+                raw_data_dir = os.path.join(self._raw_data_dir, save_dir)
+                self._data.SaveRawData(raw_data_dir)
 
 
 def main(argv=None):
-  if argv is None:
-    argv = sys.argv[1:]
-  # Command line argument description.
-  parser = argparse.ArgumentParser(
-      description="Gather CSV data from sweetberry")
-  parser.add_argument('-b', '--board', type=str,
-      help="Board configuration file, eg. my.board", default="")
-  parser.add_argument('-c', '--config', type=str,
-      help="Rail config to monitor, eg my.scenario", default="")
-  parser.add_argument('-A', '--serial', type=str,
-      help="Serial number of sweetberry A", default="")
-  parser.add_argument('-B', '--serial_b', type=str,
-      help="Serial number of sweetberry B", default="")
-  parser.add_argument('-t', '--integration_us', type=int,
-      help="Target integration time for samples", default=100000)
-  parser.add_argument('-s', '--seconds', type=float,
-      help="Seconds to run capture", default=0.)
-  parser.add_argument('--date', default=False,
-      help="Sync logged timestamp to host date", action="store_true")
-  parser.add_argument('--ms', default=False,
-      help="Print timestamp as milliseconds", action="store_true")
-  parser.add_argument('--mW', default=False,
-      help="Print power as milliwatts, otherwise default to microwatts",
-      action="store_true")
-  parser.add_argument('--slow', default=False,
-      help="Intentionally overflow", action="store_true")
-  parser.add_argument('--print_stats', default=False, action="store_true",
-      help="Print statistics for sweetberry readings at the end")
-  parser.add_argument('--save_stats', type=str, nargs='?',
-      dest='stats_dir', metavar='STATS_DIR',
-      const=os.path.dirname(os.path.abspath(__file__)), default=None,
-      help="Save statistics for sweetberry readings to %(metavar)s if "
-           "%(metavar)s is specified, %(metavar)s will be created if it does "
-           "not exist; if %(metavar)s is not specified but the flag is set, "
-           "stats will be saved to where %(prog)s is located; if this flag is "
-           "not set, then do not save stats")
-  parser.add_argument('--save_stats_json', type=str, nargs='?',
-      dest='stats_json_dir', metavar='STATS_JSON_DIR',
-      const=os.path.dirname(os.path.abspath(__file__)), default=None,
-      help="Save means for sweetberry readings in json to %(metavar)s if "
-           "%(metavar)s is specified, %(metavar)s will be created if it does "
-           "not exist; if %(metavar)s is not specified but the flag is set, "
-           "stats will be saved to where %(prog)s is located; if this flag is "
-           "not set, then do not save stats")
-  parser.add_argument('--no_print_raw_data',
-      dest='print_raw_data', default=True, action="store_false",
-      help="Not print raw sweetberry readings at real time, default is to "
-           "print")
-  parser.add_argument('--save_raw_data', type=str, nargs='?',
-      dest='raw_data_dir', metavar='RAW_DATA_DIR',
-      const=os.path.dirname(os.path.abspath(__file__)), default=None,
-      help="Save raw data for sweetberry readings to %(metavar)s if "
-           "%(metavar)s is specified, %(metavar)s will be created if it does "
-           "not exist; if %(metavar)s is not specified but the flag is set, "
-           "raw data will be saved to where %(prog)s is located; if this flag "
-           "is not set, then do not save raw data")
-  parser.add_argument('-v', '--verbose', default=False,
-      help="Very chatty printout", action="store_true")
-
-  args = parser.parse_args(argv)
-
-  root_logger = logging.getLogger(__name__)
-  if args.verbose:
-    root_logger.setLevel(logging.DEBUG)
-  else:
-    root_logger.setLevel(logging.INFO)
-
-  # if powerlog is used through main, log to sys.stdout
-  if __name__ == "__main__":
-    stdout_handler = logging.StreamHandler(sys.stdout)
-    stdout_handler.setFormatter(logging.Formatter('%(levelname)s: %(message)s'))
-    root_logger.addHandler(stdout_handler)
-
-  integration_us_request = args.integration_us
-  if not args.board:
-    raise Exception("Power", "No board file selected, see board.README")
-  if not args.config:
-    raise Exception("Power", "No config file selected, see board.README")
-
-  brdfile = args.board
-  cfgfile = args.config
-  seconds = args.seconds
-  serial_a = args.serial
-  serial_b = args.serial_b
-  sync_date = args.date
-  use_ms = args.ms
-  use_mW = args.mW
-  print_stats = args.print_stats
-  stats_dir = args.stats_dir
-  stats_json_dir = args.stats_json_dir
-  print_raw_data = args.print_raw_data
-  raw_data_dir = args.raw_data_dir
-
-  boards = []
-
-  sync_speed = .8
-  if args.slow:
-    sync_speed = 1.2
-
-  # Set up logging interface.
-  powerlogger = powerlog(brdfile, cfgfile, serial_a=serial_a, serial_b=serial_b,
-      sync_date=sync_date, use_ms=use_ms, use_mW=use_mW,
-      print_stats=print_stats, stats_dir=stats_dir,
-      stats_json_dir=stats_json_dir,
-      print_raw_data=print_raw_data,raw_data_dir=raw_data_dir)
-
-  # Start logging.
-  powerlogger.start(integration_us_request, seconds, sync_speed=sync_speed)
+    if argv is None:
+        argv = sys.argv[1:]
+    # Command line argument description.
+    parser = argparse.ArgumentParser(
+        description="Gather CSV data from sweetberry"
+    )
+    parser.add_argument(
+        "-b",
+        "--board",
+        type=str,
+        help="Board configuration file, eg. my.board",
+        default="",
+    )
+    parser.add_argument(
+        "-c",
+        "--config",
+        type=str,
+        help="Rail config to monitor, eg my.scenario",
+        default="",
+    )
+    parser.add_argument(
+        "-A",
+        "--serial",
+        type=str,
+        help="Serial number of sweetberry A",
+        default="",
+    )
+    parser.add_argument(
+        "-B",
+        "--serial_b",
+        type=str,
+        help="Serial number of sweetberry B",
+        default="",
+    )
+    parser.add_argument(
+        "-t",
+        "--integration_us",
+        type=int,
+        help="Target integration time for samples",
+        default=100000,
+    )
+    parser.add_argument(
+        "-s",
+        "--seconds",
+        type=float,
+        help="Seconds to run capture",
+        default=0.0,
+    )
+    parser.add_argument(
+        "--date",
+        default=False,
+        help="Sync logged timestamp to host date",
+        action="store_true",
+    )
+    parser.add_argument(
+        "--ms",
+        default=False,
+        help="Print timestamp as milliseconds",
+        action="store_true",
+    )
+    parser.add_argument(
+        "--mW",
+        default=False,
+        help="Print power as milliwatts, otherwise default to microwatts",
+        action="store_true",
+    )
+    parser.add_argument(
+        "--slow",
+        default=False,
+        help="Intentionally overflow",
+        action="store_true",
+    )
+    parser.add_argument(
+        "--print_stats",
+        default=False,
+        action="store_true",
+        help="Print statistics for sweetberry readings at the end",
+    )
+    parser.add_argument(
+        "--save_stats",
+        type=str,
+        nargs="?",
+        dest="stats_dir",
+        metavar="STATS_DIR",
+        const=os.path.dirname(os.path.abspath(__file__)),
+        default=None,
+        help="Save statistics for sweetberry readings to %(metavar)s if "
+        "%(metavar)s is specified, %(metavar)s will be created if it does "
+        "not exist; if %(metavar)s is not specified but the flag is set, "
+        "stats will be saved to where %(prog)s is located; if this flag is "
+        "not set, then do not save stats",
+    )
+    parser.add_argument(
+        "--save_stats_json",
+        type=str,
+        nargs="?",
+        dest="stats_json_dir",
+        metavar="STATS_JSON_DIR",
+        const=os.path.dirname(os.path.abspath(__file__)),
+        default=None,
+        help="Save means for sweetberry readings in json to %(metavar)s if "
+        "%(metavar)s is specified, %(metavar)s will be created if it does "
+        "not exist; if %(metavar)s is not specified but the flag is set, "
+        "stats will be saved to where %(prog)s is located; if this flag is "
+        "not set, then do not save stats",
+    )
+    parser.add_argument(
+        "--no_print_raw_data",
+        dest="print_raw_data",
+        default=True,
+        action="store_false",
+        help="Not print raw sweetberry readings at real time, default is to "
+        "print",
+    )
+    parser.add_argument(
+        "--save_raw_data",
+        type=str,
+        nargs="?",
+        dest="raw_data_dir",
+        metavar="RAW_DATA_DIR",
+        const=os.path.dirname(os.path.abspath(__file__)),
+        default=None,
+        help="Save raw data for sweetberry readings to %(metavar)s if "
+        "%(metavar)s is specified, %(metavar)s will be created if it does "
+        "not exist; if %(metavar)s is not specified but the flag is set, "
+        "raw data will be saved to where %(prog)s is located; if this flag "
+        "is not set, then do not save raw data",
+    )
+    parser.add_argument(
+        "-v",
+        "--verbose",
+        default=False,
+        help="Very chatty printout",
+        action="store_true",
+    )
+
+    args = parser.parse_args(argv)
+
+    root_logger = logging.getLogger(__name__)
+    if args.verbose:
+        root_logger.setLevel(logging.DEBUG)
+    else:
+        root_logger.setLevel(logging.INFO)
+
+    # if powerlog is used through main, log to sys.stdout
+    if __name__ == "__main__":
+        stdout_handler = logging.StreamHandler(sys.stdout)
+        stdout_handler.setFormatter(
+            logging.Formatter("%(levelname)s: %(message)s")
+        )
+        root_logger.addHandler(stdout_handler)
+
+    integration_us_request = args.integration_us
+    if not args.board:
+        raise Exception("Power", "No board file selected, see board.README")
+    if not args.config:
+        raise Exception("Power", "No config file selected, see board.README")
+
+    brdfile = args.board
+    cfgfile = args.config
+    seconds = args.seconds
+    serial_a = args.serial
+    serial_b = args.serial_b
+    sync_date = args.date
+    use_ms = args.ms
+    use_mW = args.mW
+    print_stats = args.print_stats
+    stats_dir = args.stats_dir
+    stats_json_dir = args.stats_json_dir
+    print_raw_data = args.print_raw_data
+    raw_data_dir = args.raw_data_dir
+
+    boards = []
+
+    sync_speed = 0.8
+    if args.slow:
+        sync_speed = 1.2
+
+    # Set up logging interface.
+    powerlogger = powerlog(
+        brdfile,
+        cfgfile,
+        serial_a=serial_a,
+        serial_b=serial_b,
+        sync_date=sync_date,
+        use_ms=use_ms,
+        use_mW=use_mW,
+        print_stats=print_stats,
+        stats_dir=stats_dir,
+        stats_json_dir=stats_json_dir,
+        print_raw_data=print_raw_data,
+        raw_data_dir=raw_data_dir,
+    )
+
+    # Start logging.
+    powerlogger.start(integration_us_request, seconds, sync_speed=sync_speed)
 
 
 if __name__ == "__main__":
-  main()
+    main()
diff --git a/extra/usb_power/powerlog_unittest.py b/extra/usb_power/powerlog_unittest.py
index 1d0718530e..62667e35b8 100644
--- a/extra/usb_power/powerlog_unittest.py
+++ b/extra/usb_power/powerlog_unittest.py
@@ -1,10 +1,6 @@
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
 
 """Unit tests for powerlog."""
 
@@ -13,42 +9,44 @@ import shutil
 import tempfile
 import unittest
 
-import powerlog
+from usb_power import powerlog
+
 
 class TestPowerlog(unittest.TestCase):
-  """Test to verify powerlog util methods work as expected."""
-
-  def setUp(self):
-    """Set up data and create a temporary directory to save data and stats."""
-    self.tempdir = tempfile.mkdtemp()
-    self.filename = 'testfile'
-    self.filepath = os.path.join(self.tempdir, self.filename)
-    with open(self.filepath, 'w') as f:
-      f.write('')
-
-  def tearDown(self):
-    """Delete the temporary directory and its content."""
-    shutil.rmtree(self.tempdir)
-
-  def test_ProcessFilenameAbsoluteFilePath(self):
-    """Absolute file path is returned unchanged."""
-    processed_fname = powerlog.process_filename(self.filepath)
-    self.assertEqual(self.filepath, processed_fname)
-
-  def test_ProcessFilenameRelativeFilePath(self):
-    """Finds relative file path inside a known config location."""
-    original = powerlog.CONFIG_LOCATIONS
-    powerlog.CONFIG_LOCATIONS = [self.tempdir]
-    processed_fname = powerlog.process_filename(self.filename)
-    try:
-      self.assertEqual(self.filepath, processed_fname)
-    finally:
-      powerlog.CONFIG_LOCATIONS = original
-
-  def test_ProcessFilenameInvalid(self):
-    """IOError is raised when file cannot be found by any of the four ways."""
-    with self.assertRaises(IOError):
-      powerlog.process_filename(self.filename)
-
-if __name__ == '__main__':
-  unittest.main()
+    """Test to verify powerlog util methods work as expected."""
+
+    def setUp(self):
+        """Set up data and create a temporary directory to save data and stats."""
+        self.tempdir = tempfile.mkdtemp()
+        self.filename = "testfile"
+        self.filepath = os.path.join(self.tempdir, self.filename)
+        with open(self.filepath, "w") as f:
+            f.write("")
+
+    def tearDown(self):
+        """Delete the temporary directory and its content."""
+        shutil.rmtree(self.tempdir)
+
+    def test_ProcessFilenameAbsoluteFilePath(self):
+        """Absolute file path is returned unchanged."""
+        processed_fname = powerlog.process_filename(self.filepath)
+        self.assertEqual(self.filepath, processed_fname)
+
+    def test_ProcessFilenameRelativeFilePath(self):
+        """Finds relative file path inside a known config location."""
+        original = powerlog.CONFIG_LOCATIONS
+        powerlog.CONFIG_LOCATIONS = [self.tempdir]
+        processed_fname = powerlog.process_filename(self.filename)
+        try:
+            self.assertEqual(self.filepath, processed_fname)
+        finally:
+            powerlog.CONFIG_LOCATIONS = original
+
+    def test_ProcessFilenameInvalid(self):
+        """IOError is raised when file cannot be found by any of the four ways."""
+        with self.assertRaises(IOError):
+            powerlog.process_filename(self.filename)
+
+
+if __name__ == "__main__":
+    unittest.main()
diff --git a/extra/usb_power/stats_manager.py b/extra/usb_power/stats_manager.py
index 0f8c3fcb15..2035138731 100644
--- a/extra/usb_power/stats_manager.py
+++ b/extra/usb_power/stats_manager.py
@@ -1,10 +1,6 @@
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
 
 """Calculates statistics for lists of data and pretty print them."""
 
@@ -18,384 +14,409 @@ import logging
 import math
 import os
 
-import numpy
+import numpy  # pylint:disable=import-error
 
-STATS_PREFIX = '@@'
-NAN_TAG = '*'
-NAN_DESCRIPTION = '%s domains contain NaN samples' % NAN_TAG
+STATS_PREFIX = "@@"
+NAN_TAG = "*"
+NAN_DESCRIPTION = "%s domains contain NaN samples" % NAN_TAG
 
 LONG_UNIT = {
-    '': 'N/A',
-    'mW': 'milliwatt',
-    'uW': 'microwatt',
-    'mV': 'millivolt',
-    'uA': 'microamp',
-    'uV': 'microvolt'
+    "": "N/A",
+    "mW": "milliwatt",
+    "uW": "microwatt",
+    "mV": "millivolt",
+    "uA": "microamp",
+    "uV": "microvolt",
 }
 
 
 class StatsManagerError(Exception):
-  """Errors in StatsManager class."""
-  pass
+    """Errors in StatsManager class."""
 
+    pass
 
-class StatsManager(object):
-  """Calculates statistics for several lists of data(float).
-
-  Example usage:
-
-    >>> stats = StatsManager(title='Title Banner')
-    >>> stats.AddSample(TIME_KEY, 50.0)
-    >>> stats.AddSample(TIME_KEY, 25.0)
-    >>> stats.AddSample(TIME_KEY, 40.0)
-    >>> stats.AddSample(TIME_KEY, 10.0)
-    >>> stats.AddSample(TIME_KEY, 10.0)
-    >>> stats.AddSample('frobnicate', 11.5)
-    >>> stats.AddSample('frobnicate', 9.0)
-    >>> stats.AddSample('foobar', 11111.0)
-    >>> stats.AddSample('foobar', 22222.0)
-    >>> stats.CalculateStats()
-    >>> print(stats.SummaryToString())
-  ` @@--------------------------------------------------------------
-  ` @@                        Title Banner
-    @@--------------------------------------------------------------
-    @@            NAME  COUNT      MEAN   STDDEV       MAX       MIN
-    @@   sample_msecs      4     31.25    15.16     50.00     10.00
-    @@         foobar      2  16666.50  5555.50  22222.00  11111.00
-    @@     frobnicate      2     10.25     1.25     11.50      9.00
-  ` @@--------------------------------------------------------------
-
-  Attributes:
-    _data: dict of list of readings for each domain(key)
-    _unit: dict of unit for each domain(key)
-    _smid: id supplied to differentiate data output to other StatsManager
-           instances that potentially save to the same directory
-           if smid all output files will be named |smid|_|fname|
-    _title: title to add as banner to formatted summary. If no title,
-            no banner gets added
-    _order: list of formatting order for domains. Domains not listed are
-            displayed in sorted order
-    _hide_domains: collection of domains to hide when formatting summary string
-    _accept_nan: flag to indicate if NaN samples are acceptable
-    _nan_domains: set to keep track of which domains contain NaN samples
-    _summary: dict of stats per domain (key): min, max, count, mean, stddev
-    _logger = StatsManager logger
-
-  Note:
-    _summary is empty until CalculateStats() is called, and is updated when
-    CalculateStats() is called.
-  """
-
-  # pylint: disable=W0102
-  def __init__(self, smid='', title='', order=[], hide_domains=[],
-               accept_nan=True):
-    """Initialize infrastructure for data and their statistics."""
-    self._title = title
-    self._data = collections.defaultdict(list)
-    self._unit = collections.defaultdict(str)
-    self._smid = smid
-    self._order = order
-    self._hide_domains = hide_domains
-    self._accept_nan = accept_nan
-    self._nan_domains = set()
-    self._summary = {}
-    self._logger = logging.getLogger(type(self).__name__)
-
-  def AddSample(self, domain, sample):
-    """Add one sample for a domain.
-
-    Args:
-      domain: the domain name for the sample.
-      sample: one time sample for domain, expect type float.
-
-    Raises:
-      StatsManagerError: if trying to add NaN and |_accept_nan| is false
-    """
-    try:
-      sample = float(sample)
-    except ValueError:
-      # if we don't accept nan this will be caught below
-      self._logger.debug('sample %s for domain %s is not a number. Making NaN',
-                         sample, domain)
-      sample = float('NaN')
-    if not self._accept_nan and math.isnan(sample):
-      raise StatsManagerError('accept_nan is false. Cannot add NaN sample.')
-    self._data[domain].append(sample)
-    if math.isnan(sample):
-      self._nan_domains.add(domain)
-
-  def SetUnit(self, domain, unit):
-    """Set the unit for a domain.
-
-    There can be only one unit for each domain. Setting unit twice will
-    overwrite the original unit.
-
-    Args:
-      domain: the domain name.
-      unit: unit of the domain.
-    """
-    if domain in self._unit:
-      self._logger.warning('overwriting the unit of %s, old unit is %s, new '
-                           'unit is %s.', domain, self._unit[domain], unit)
-    self._unit[domain] = unit
 
-  def CalculateStats(self):
-    """Calculate stats for all domain-data pairs.
-
-    First erases all previous stats, then calculate stats for all data.
-    """
-    self._summary = {}
-    for domain, data in self._data.items():
-      data_np = numpy.array(data)
-      self._summary[domain] = {
-          'mean': numpy.nanmean(data_np),
-          'min': numpy.nanmin(data_np),
-          'max': numpy.nanmax(data_np),
-          'stddev': numpy.nanstd(data_np),
-          'count': data_np.size,
-      }
-
-  @property
-  def DomainsToDisplay(self):
-    """List of domains that the manager will output in summaries."""
-    return set(self._summary.keys()) - set(self._hide_domains)
-
-  @property
-  def NanInOutput(self):
-    """Return whether any of the domains to display have NaN values."""
-    return bool(len(set(self._nan_domains) & self.DomainsToDisplay))
-
-  def _SummaryTable(self):
-    """Generate the matrix to output as a summary.
-
-    Returns:
-      A 2d matrix of headers and their data for each domain
-      e.g.
-      [[NAME, COUNT, MEAN, STDDEV, MAX, MIN],
-       [pp5000_mw, 10, 50, 0, 50, 50]]
-    """
-    headers = ('NAME', 'COUNT', 'MEAN', 'STDDEV', 'MAX', 'MIN')
-    table = [headers]
-    # determine what domains to display & and the order
-    domains_to_display = self.DomainsToDisplay
-    display_order = [key for key in self._order if key in domains_to_display]
-    domains_to_display -= set(display_order)
-    display_order.extend(sorted(domains_to_display))
-    for domain in display_order:
-      stats = self._summary[domain]
-      if not domain.endswith(self._unit[domain]):
-        domain = '%s_%s' % (domain, self._unit[domain])
-      if domain in self._nan_domains:
-        domain = '%s%s' % (domain, NAN_TAG)
-      row = [domain]
-      row.append(str(stats['count']))
-      for entry in headers[2:]:
-        row.append('%.2f' % stats[entry.lower()])
-      table.append(row)
-    return table
-
-  def SummaryToMarkdownString(self):
-    """Format the summary into a b/ compatible markdown table string.
-
-    This requires this sort of output format
-
-    | header1   | header2   | header3   | ...
-    | --------- | --------- | --------- | ...
-    | sample1h1 | sample1h2 | sample1h3 | ...
-    .
-    .
-    .
-
-    Returns:
-      formatted summary string.
-    """
-    # All we need to do before processing is insert a row of '-' between
-    # the headers, and the data
-    table = self._SummaryTable()
-    columns = len(table[0])
-    # Using '-:' to allow the numbers to be right aligned
-    sep_row = ['-'] + ['-:'] * (columns - 1)
-    table.insert(1, sep_row)
-    text_rows = ['|'.join(r) for r in table]
-    body = '\n'.join(['|%s|' % r for r in text_rows])
-    if self._title:
-      title_section = '**%s**  \n\n' % self._title
-      body = title_section + body
-    # Make sure that the body is terminated with a newline.
-    return body + '\n'
-
-  def SummaryToString(self, prefix=STATS_PREFIX):
-    """Format summary into a string, ready for pretty print.
-
-    See class description for format example.
-
-    Args:
-      prefix: start every row in summary string with prefix, for easier reading.
-
-    Returns:
-      formatted summary string.
-    """
-    table = self._SummaryTable()
-    max_col_width = []
-    for col_idx in range(len(table[0])):
-      col_item_widths = [len(row[col_idx]) for row in table]
-      max_col_width.append(max(col_item_widths))
-
-    formatted_lines = []
-    for row in table:
-      formatted_row = prefix + ' '
-      for i in range(len(row)):
-        formatted_row += row[i].rjust(max_col_width[i] + 2)
-      formatted_lines.append(formatted_row)
-    if self.NanInOutput:
-      formatted_lines.append('%s %s' % (prefix, NAN_DESCRIPTION))
-
-    if self._title:
-      line_length = len(formatted_lines[0])
-      dec_length = len(prefix)
-      # trim title to be at most as long as the longest line without the prefix
-      title = self._title[:(line_length - dec_length)]
-      # line is a seperator line consisting of -----
-      line = '%s%s' % (prefix, '-' * (line_length - dec_length))
-      # prepend the prefix to the centered title
-      padded_title = '%s%s' % (prefix, title.center(line_length)[dec_length:])
-      formatted_lines = [line, padded_title, line] + formatted_lines + [line]
-    formatted_output = '\n'.join(formatted_lines)
-    return formatted_output
-
-  def GetSummary(self):
-    """Getter for summary."""
-    return self._summary
-
-  def _MakeUniqueFName(self, fname):
-    """prepend |_smid| to fname & rotate fname to ensure uniqueness.
-
-    Before saving a file through the StatsManager, make sure that the filename
-    is unique, first by prepending the smid if any and otherwise by appending
-    increasing integer suffixes until the filename is unique.
-
-    If |smid| is defined /path/to/example/file.txt becomes
-    /path/to/example/{smid}_file.txt.
-
-    The rotation works by changing /path/to/example/somename.txt to
-    /path/to/example/somename1.txt if the first one already exists on the
-    system.
-
-    Note: this is not thread-safe. While it makes sense to use StatsManager
-    in a threaded data-collection, the data retrieval should happen in a
-    single threaded environment to ensure files don't get potentially clobbered.
-
-    Args:
-      fname: filename to ensure uniqueness.
-
-    Returns:
-      {smid_}fname{tag}.[b].ext
-      the smid portion gets prepended if |smid| is defined
-      the tag portion gets appended if necessary to ensure unique fname
-    """
-    fdir = os.path.dirname(fname)
-    base, ext = os.path.splitext(os.path.basename(fname))
-    if self._smid:
-      base = '%s_%s' % (self._smid, base)
-    unique_fname = os.path.join(fdir, '%s%s' % (base, ext))
-    tag = 0
-    while os.path.exists(unique_fname):
-      old_fname = unique_fname
-      unique_fname = os.path.join(fdir, '%s%d%s' % (base, tag, ext))
-      self._logger.warning('Attempted to store stats information at %s, but '
-                           'file already exists. Attempting to store at %s '
-                           'now.', old_fname, unique_fname)
-      tag += 1
-    return unique_fname
-
-  def SaveSummary(self, directory, fname='summary.txt', prefix=STATS_PREFIX):
-    """Save summary to file.
-
-    Args:
-      directory: directory to save the summary in.
-      fname: filename to save summary under.
-      prefix: start every row in summary string with prefix, for easier reading.
-
-    Returns:
-      full path of summary save location
-    """
-    summary_str = self.SummaryToString(prefix=prefix) + '\n'
-    return self._SaveSummary(summary_str, directory, fname)
-
-  def SaveSummaryJSON(self, directory, fname='summary.json'):
-    """Save summary (only MEAN) into a JSON file.
-
-    Args:
-      directory: directory to save the JSON summary in.
-      fname: filename to save summary under.
-
-    Returns:
-      full path of summary save location
-    """
-    data = {}
-    for domain in self._summary:
-      unit = LONG_UNIT.get(self._unit[domain], self._unit[domain])
-      data_entry = {'mean': self._summary[domain]['mean'], 'unit': unit}
-      data[domain] = data_entry
-    summary_str = json.dumps(data, indent=2)
-    return self._SaveSummary(summary_str, directory, fname)
-
-  def SaveSummaryMD(self, directory, fname='summary.md'):
-    """Save summary into a MD file to paste into b/.
-
-    Args:
-      directory: directory to save the MD summary in.
-      fname: filename to save summary under.
-
-    Returns:
-      full path of summary save location
+class StatsManager(object):
+    """Calculates statistics for several lists of data(float).
+
+    Example usage:
+
+      >>> stats = StatsManager(title='Title Banner')
+      >>> stats.AddSample(TIME_KEY, 50.0)
+      >>> stats.AddSample(TIME_KEY, 25.0)
+      >>> stats.AddSample(TIME_KEY, 40.0)
+      >>> stats.AddSample(TIME_KEY, 10.0)
+      >>> stats.AddSample(TIME_KEY, 10.0)
+      >>> stats.AddSample('frobnicate', 11.5)
+      >>> stats.AddSample('frobnicate', 9.0)
+      >>> stats.AddSample('foobar', 11111.0)
+      >>> stats.AddSample('foobar', 22222.0)
+      >>> stats.CalculateStats()
+      >>> print(stats.SummaryToString())
+    ` @@--------------------------------------------------------------
+    ` @@                        Title Banner
+      @@--------------------------------------------------------------
+      @@            NAME  COUNT      MEAN   STDDEV       MAX       MIN
+      @@   sample_msecs      4     31.25    15.16     50.00     10.00
+      @@         foobar      2  16666.50  5555.50  22222.00  11111.00
+      @@     frobnicate      2     10.25     1.25     11.50      9.00
+    ` @@--------------------------------------------------------------
+
+    Attributes:
+      _data: dict of list of readings for each domain(key)
+      _unit: dict of unit for each domain(key)
+      _smid: id supplied to differentiate data output to other StatsManager
+             instances that potentially save to the same directory
+             if smid all output files will be named |smid|_|fname|
+      _title: title to add as banner to formatted summary. If no title,
+              no banner gets added
+      _order: list of formatting order for domains. Domains not listed are
+              displayed in sorted order
+      _hide_domains: collection of domains to hide when formatting summary string
+      _accept_nan: flag to indicate if NaN samples are acceptable
+      _nan_domains: set to keep track of which domains contain NaN samples
+      _summary: dict of stats per domain (key): min, max, count, mean, stddev
+      _logger = StatsManager logger
+
+    Note:
+      _summary is empty until CalculateStats() is called, and is updated when
+      CalculateStats() is called.
     """
-    summary_str = self.SummaryToMarkdownString()
-    return self._SaveSummary(summary_str, directory, fname)
 
-  def _SaveSummary(self, output_str, directory, fname):
-    """Wrote |output_str| to |fname|.
-
-    Args:
-      output_str: formatted output string
-      directory: directory to save the summary in.
-      fname: filename to save summary under.
-
-    Returns:
-      full path of summary save location
-    """
-    if not os.path.exists(directory):
-      os.makedirs(directory)
-    fname = self._MakeUniqueFName(os.path.join(directory, fname))
-    with open(fname, 'w') as f:
-      f.write(output_str)
-    return fname
-
-  def GetRawData(self):
-    """Getter for all raw_data."""
-    return self._data
-
-  def SaveRawData(self, directory, dirname='raw_data'):
-    """Save raw data to file.
-
-    Args:
-      directory: directory to create the raw data folder in.
-      dirname: folder in which raw data live.
-
-    Returns:
-      list of full path of each domain's raw data save location
-    """
-    if not os.path.exists(directory):
-      os.makedirs(directory)
-    dirname = os.path.join(directory, dirname)
-    if not os.path.exists(dirname):
-      os.makedirs(dirname)
-    fnames = []
-    for domain, data in self._data.items():
-      if not domain.endswith(self._unit[domain]):
-        domain = '%s_%s' % (domain, self._unit[domain])
-      fname = self._MakeUniqueFName(os.path.join(dirname, '%s.txt' % domain))
-      with open(fname, 'w') as f:
-        f.write('\n'.join('%.2f' % sample for sample in data) + '\n')
-      fnames.append(fname)
-    return fnames
+    # pylint: disable=W0102
+    def __init__(
+        self, smid="", title="", order=[], hide_domains=[], accept_nan=True
+    ):
+        """Initialize infrastructure for data and their statistics."""
+        self._title = title
+        self._data = collections.defaultdict(list)
+        self._unit = collections.defaultdict(str)
+        self._smid = smid
+        self._order = order
+        self._hide_domains = hide_domains
+        self._accept_nan = accept_nan
+        self._nan_domains = set()
+        self._summary = {}
+        self._logger = logging.getLogger(type(self).__name__)
+
+    def AddSample(self, domain, sample):
+        """Add one sample for a domain.
+
+        Args:
+          domain: the domain name for the sample.
+          sample: one time sample for domain, expect type float.
+
+        Raises:
+          StatsManagerError: if trying to add NaN and |_accept_nan| is false
+        """
+        try:
+            sample = float(sample)
+        except ValueError:
+            # if we don't accept nan this will be caught below
+            self._logger.debug(
+                "sample %s for domain %s is not a number. Making NaN",
+                sample,
+                domain,
+            )
+            sample = float("NaN")
+        if not self._accept_nan and math.isnan(sample):
+            raise StatsManagerError(
+                "accept_nan is false. Cannot add NaN sample."
+            )
+        self._data[domain].append(sample)
+        if math.isnan(sample):
+            self._nan_domains.add(domain)
+
+    def SetUnit(self, domain, unit):
+        """Set the unit for a domain.
+
+        There can be only one unit for each domain. Setting unit twice will
+        overwrite the original unit.
+
+        Args:
+          domain: the domain name.
+          unit: unit of the domain.
+        """
+        if domain in self._unit:
+            self._logger.warning(
+                "overwriting the unit of %s, old unit is %s, new "
+                "unit is %s.",
+                domain,
+                self._unit[domain],
+                unit,
+            )
+        self._unit[domain] = unit
+
+    def CalculateStats(self):
+        """Calculate stats for all domain-data pairs.
+
+        First erases all previous stats, then calculate stats for all data.
+        """
+        self._summary = {}
+        for domain, data in self._data.items():
+            data_np = numpy.array(data)
+            self._summary[domain] = {
+                "mean": numpy.nanmean(data_np),
+                "min": numpy.nanmin(data_np),
+                "max": numpy.nanmax(data_np),
+                "stddev": numpy.nanstd(data_np),
+                "count": data_np.size,
+            }
+
+    @property
+    def DomainsToDisplay(self):
+        """List of domains that the manager will output in summaries."""
+        return set(self._summary.keys()) - set(self._hide_domains)
+
+    @property
+    def NanInOutput(self):
+        """Return whether any of the domains to display have NaN values."""
+        return bool(len(set(self._nan_domains) & self.DomainsToDisplay))
+
+    def _SummaryTable(self):
+        """Generate the matrix to output as a summary.
+
+        Returns:
+          A 2d matrix of headers and their data for each domain
+          e.g.
+          [[NAME, COUNT, MEAN, STDDEV, MAX, MIN],
+           [pp5000_mw, 10, 50, 0, 50, 50]]
+        """
+        headers = ("NAME", "COUNT", "MEAN", "STDDEV", "MAX", "MIN")
+        table = [headers]
+        # determine what domains to display & and the order
+        domains_to_display = self.DomainsToDisplay
+        display_order = [
+            key for key in self._order if key in domains_to_display
+        ]
+        domains_to_display -= set(display_order)
+        display_order.extend(sorted(domains_to_display))
+        for domain in display_order:
+            stats = self._summary[domain]
+            if not domain.endswith(self._unit[domain]):
+                domain = "%s_%s" % (domain, self._unit[domain])
+            if domain in self._nan_domains:
+                domain = "%s%s" % (domain, NAN_TAG)
+            row = [domain]
+            row.append(str(stats["count"]))
+            for entry in headers[2:]:
+                row.append("%.2f" % stats[entry.lower()])
+            table.append(row)
+        return table
+
+    def SummaryToMarkdownString(self):
+        """Format the summary into a b/ compatible markdown table string.
+
+        This requires this sort of output format
+
+        | header1   | header2   | header3   | ...
+        | --------- | --------- | --------- | ...
+        | sample1h1 | sample1h2 | sample1h3 | ...
+        .
+        .
+        .
+
+        Returns:
+          formatted summary string.
+        """
+        # All we need to do before processing is insert a row of '-' between
+        # the headers, and the data
+        table = self._SummaryTable()
+        columns = len(table[0])
+        # Using '-:' to allow the numbers to be right aligned
+        sep_row = ["-"] + ["-:"] * (columns - 1)
+        table.insert(1, sep_row)
+        text_rows = ["|".join(r) for r in table]
+        body = "\n".join(["|%s|" % r for r in text_rows])
+        if self._title:
+            title_section = "**%s**  \n\n" % self._title
+            body = title_section + body
+        # Make sure that the body is terminated with a newline.
+        return body + "\n"
+
+    def SummaryToString(self, prefix=STATS_PREFIX):
+        """Format summary into a string, ready for pretty print.
+
+        See class description for format example.
+
+        Args:
+          prefix: start every row in summary string with prefix, for easier reading.
+
+        Returns:
+          formatted summary string.
+        """
+        table = self._SummaryTable()
+        max_col_width = []
+        for col_idx in range(len(table[0])):
+            col_item_widths = [len(row[col_idx]) for row in table]
+            max_col_width.append(max(col_item_widths))
+
+        formatted_lines = []
+        for row in table:
+            formatted_row = prefix + " "
+            for i in range(len(row)):
+                formatted_row += row[i].rjust(max_col_width[i] + 2)
+            formatted_lines.append(formatted_row)
+        if self.NanInOutput:
+            formatted_lines.append("%s %s" % (prefix, NAN_DESCRIPTION))
+
+        if self._title:
+            line_length = len(formatted_lines[0])
+            dec_length = len(prefix)
+            # trim title to be at most as long as the longest line without the prefix
+            title = self._title[: (line_length - dec_length)]
+            # line is a seperator line consisting of -----
+            line = "%s%s" % (prefix, "-" * (line_length - dec_length))
+            # prepend the prefix to the centered title
+            padded_title = "%s%s" % (
+                prefix,
+                title.center(line_length)[dec_length:],
+            )
+            formatted_lines = (
+                [line, padded_title, line] + formatted_lines + [line]
+            )
+        formatted_output = "\n".join(formatted_lines)
+        return formatted_output
+
+    def GetSummary(self):
+        """Getter for summary."""
+        return self._summary
+
+    def _MakeUniqueFName(self, fname):
+        """prepend |_smid| to fname & rotate fname to ensure uniqueness.
+
+        Before saving a file through the StatsManager, make sure that the filename
+        is unique, first by prepending the smid if any and otherwise by appending
+        increasing integer suffixes until the filename is unique.
+
+        If |smid| is defined /path/to/example/file.txt becomes
+        /path/to/example/{smid}_file.txt.
+
+        The rotation works by changing /path/to/example/somename.txt to
+        /path/to/example/somename1.txt if the first one already exists on the
+        system.
+
+        Note: this is not thread-safe. While it makes sense to use StatsManager
+        in a threaded data-collection, the data retrieval should happen in a
+        single threaded environment to ensure files don't get potentially clobbered.
+
+        Args:
+          fname: filename to ensure uniqueness.
+
+        Returns:
+          {smid_}fname{tag}.[b].ext
+          the smid portion gets prepended if |smid| is defined
+          the tag portion gets appended if necessary to ensure unique fname
+        """
+        fdir = os.path.dirname(fname)
+        base, ext = os.path.splitext(os.path.basename(fname))
+        if self._smid:
+            base = "%s_%s" % (self._smid, base)
+        unique_fname = os.path.join(fdir, "%s%s" % (base, ext))
+        tag = 0
+        while os.path.exists(unique_fname):
+            old_fname = unique_fname
+            unique_fname = os.path.join(fdir, "%s%d%s" % (base, tag, ext))
+            self._logger.warning(
+                "Attempted to store stats information at %s, but "
+                "file already exists. Attempting to store at %s "
+                "now.",
+                old_fname,
+                unique_fname,
+            )
+            tag += 1
+        return unique_fname
+
+    def SaveSummary(self, directory, fname="summary.txt", prefix=STATS_PREFIX):
+        """Save summary to file.
+
+        Args:
+          directory: directory to save the summary in.
+          fname: filename to save summary under.
+          prefix: start every row in summary string with prefix, for easier reading.
+
+        Returns:
+          full path of summary save location
+        """
+        summary_str = self.SummaryToString(prefix=prefix) + "\n"
+        return self._SaveSummary(summary_str, directory, fname)
+
+    def SaveSummaryJSON(self, directory, fname="summary.json"):
+        """Save summary (only MEAN) into a JSON file.
+
+        Args:
+          directory: directory to save the JSON summary in.
+          fname: filename to save summary under.
+
+        Returns:
+          full path of summary save location
+        """
+        data = {}
+        for domain in self._summary:
+            unit = LONG_UNIT.get(self._unit[domain], self._unit[domain])
+            data_entry = {"mean": self._summary[domain]["mean"], "unit": unit}
+            data[domain] = data_entry
+        summary_str = json.dumps(data, indent=2)
+        return self._SaveSummary(summary_str, directory, fname)
+
+    def SaveSummaryMD(self, directory, fname="summary.md"):
+        """Save summary into a MD file to paste into b/.
+
+        Args:
+          directory: directory to save the MD summary in.
+          fname: filename to save summary under.
+
+        Returns:
+          full path of summary save location
+        """
+        summary_str = self.SummaryToMarkdownString()
+        return self._SaveSummary(summary_str, directory, fname)
+
+    def _SaveSummary(self, output_str, directory, fname):
+        """Wrote |output_str| to |fname|.
+
+        Args:
+          output_str: formatted output string
+          directory: directory to save the summary in.
+          fname: filename to save summary under.
+
+        Returns:
+          full path of summary save location
+        """
+        if not os.path.exists(directory):
+            os.makedirs(directory)
+        fname = self._MakeUniqueFName(os.path.join(directory, fname))
+        with open(fname, "w") as f:
+            f.write(output_str)
+        return fname
+
+    def GetRawData(self):
+        """Getter for all raw_data."""
+        return self._data
+
+    def SaveRawData(self, directory, dirname="raw_data"):
+        """Save raw data to file.
+
+        Args:
+          directory: directory to create the raw data folder in.
+          dirname: folder in which raw data live.
+
+        Returns:
+          list of full path of each domain's raw data save location
+        """
+        if not os.path.exists(directory):
+            os.makedirs(directory)
+        dirname = os.path.join(directory, dirname)
+        if not os.path.exists(dirname):
+            os.makedirs(dirname)
+        fnames = []
+        for domain, data in self._data.items():
+            if not domain.endswith(self._unit[domain]):
+                domain = "%s_%s" % (domain, self._unit[domain])
+            fname = self._MakeUniqueFName(
+                os.path.join(dirname, "%s.txt" % domain)
+            )
+            with open(fname, "w") as f:
+                f.write("\n".join("%.2f" % sample for sample in data) + "\n")
+            fnames.append(fname)
+        return fnames
diff --git a/extra/usb_power/stats_manager_unittest.py b/extra/usb_power/stats_manager_unittest.py
index beb9984b93..2bfaa5c83d 100644
--- a/extra/usb_power/stats_manager_unittest.py
+++ b/extra/usb_power/stats_manager_unittest.py
@@ -1,14 +1,11 @@
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
 
 """Unit tests for StatsManager."""
 
 from __future__ import print_function
+
 import json
 import os
 import re
@@ -16,300 +13,314 @@ import shutil
 import tempfile
 import unittest
 
-import stats_manager
+import stats_manager  # pylint:disable=import-error
 
 
 class TestStatsManager(unittest.TestCase):
-  """Test to verify StatsManager methods work as expected.
-
-  StatsManager should collect raw data, calculate their statistics, and save
-  them in expected format.
-  """
-
-  def _populate_mock_stats(self):
-    """Create a populated & processed StatsManager to test data retrieval."""
-    self.data.AddSample('A', 99999.5)
-    self.data.AddSample('A', 100000.5)
-    self.data.SetUnit('A', 'uW')
-    self.data.SetUnit('A', 'mW')
-    self.data.AddSample('B', 1.5)
-    self.data.AddSample('B', 2.5)
-    self.data.AddSample('B', 3.5)
-    self.data.SetUnit('B', 'mV')
-    self.data.CalculateStats()
-
-  def _populate_mock_stats_no_unit(self):
-    self.data.AddSample('B', 1000)
-    self.data.AddSample('A', 200)
-    self.data.SetUnit('A', 'blue')
-
-  def setUp(self):
-    """Set up StatsManager and create a temporary directory for test."""
-    self.tempdir = tempfile.mkdtemp()
-    self.data = stats_manager.StatsManager()
-
-  def tearDown(self):
-    """Delete the temporary directory and its content."""
-    shutil.rmtree(self.tempdir)
-
-  def test_AddSample(self):
-    """Adding a sample successfully adds a sample."""
-    self.data.AddSample('Test', 1000)
-    self.data.SetUnit('Test', 'test')
-    self.data.CalculateStats()
-    summary = self.data.GetSummary()
-    self.assertEqual(1, summary['Test']['count'])
-
-  def test_AddSampleNoFloatAcceptNaN(self):
-    """Adding a non-number adds 'NaN' and doesn't raise an exception."""
-    self.data.AddSample('Test', 10)
-    self.data.AddSample('Test', 20)
-    # adding a fake NaN: one that gets converted into NaN internally
-    self.data.AddSample('Test', 'fiesta')
-    # adding a real NaN
-    self.data.AddSample('Test', float('NaN'))
-    self.data.SetUnit('Test', 'test')
-    self.data.CalculateStats()
-    summary = self.data.GetSummary()
-    # assert that 'NaN' as added.
-    self.assertEqual(4, summary['Test']['count'])
-    # assert that mean, min, and max calculatings ignore the 'NaN'
-    self.assertEqual(10, summary['Test']['min'])
-    self.assertEqual(20, summary['Test']['max'])
-    self.assertEqual(15, summary['Test']['mean'])
-
-  def test_AddSampleNoFloatNotAcceptNaN(self):
-    """Adding a non-number raises a StatsManagerError if accept_nan is False."""
-    self.data = stats_manager.StatsManager(accept_nan=False)
-    with self.assertRaisesRegexp(stats_manager.StatsManagerError,
-                                 'accept_nan is false. Cannot add NaN sample.'):
-      # adding a fake NaN: one that gets converted into NaN internally
-      self.data.AddSample('Test', 'fiesta')
-    with self.assertRaisesRegexp(stats_manager.StatsManagerError,
-                                 'accept_nan is false. Cannot add NaN sample.'):
-      # adding a real NaN
-      self.data.AddSample('Test', float('NaN'))
-
-  def test_AddSampleNoUnit(self):
-    """Not adding a unit does not cause an exception on CalculateStats()."""
-    self.data.AddSample('Test', 17)
-    self.data.CalculateStats()
-    summary = self.data.GetSummary()
-    self.assertEqual(1, summary['Test']['count'])
-
-  def test_UnitSuffix(self):
-    """Unit gets appended as a suffix in the displayed summary."""
-    self.data.AddSample('test', 250)
-    self.data.SetUnit('test', 'mw')
-    self.data.CalculateStats()
-    summary_str = self.data.SummaryToString()
-    self.assertIn('test_mw', summary_str)
-
-  def test_DoubleUnitSuffix(self):
-    """If domain already ends in unit, verify that unit doesn't get appended."""
-    self.data.AddSample('test_mw', 250)
-    self.data.SetUnit('test_mw', 'mw')
-    self.data.CalculateStats()
-    summary_str = self.data.SummaryToString()
-    self.assertIn('test_mw', summary_str)
-    self.assertNotIn('test_mw_mw', summary_str)
-
-  def test_GetRawData(self):
-    """GetRawData returns exact same data as fed in."""
-    self._populate_mock_stats()
-    raw_data = self.data.GetRawData()
-    self.assertListEqual([99999.5, 100000.5], raw_data['A'])
-    self.assertListEqual([1.5, 2.5, 3.5], raw_data['B'])
-
-  def test_GetSummary(self):
-    """GetSummary returns expected stats about the data fed in."""
-    self._populate_mock_stats()
-    summary = self.data.GetSummary()
-    self.assertEqual(2, summary['A']['count'])
-    self.assertAlmostEqual(100000.5, summary['A']['max'])
-    self.assertAlmostEqual(99999.5, summary['A']['min'])
-    self.assertAlmostEqual(0.5, summary['A']['stddev'])
-    self.assertAlmostEqual(100000.0, summary['A']['mean'])
-    self.assertEqual(3, summary['B']['count'])
-    self.assertAlmostEqual(3.5, summary['B']['max'])
-    self.assertAlmostEqual(1.5, summary['B']['min'])
-    self.assertAlmostEqual(0.81649658092773, summary['B']['stddev'])
-    self.assertAlmostEqual(2.5, summary['B']['mean'])
-
-  def test_SaveRawData(self):
-    """SaveRawData stores same data as fed in."""
-    self._populate_mock_stats()
-    dirname = 'unittest_raw_data'
-    expected_files = set(['A_mW.txt', 'B_mV.txt'])
-    fnames = self.data.SaveRawData(self.tempdir, dirname)
-    files_returned = set([os.path.basename(f) for f in fnames])
-    # Assert that only the expected files got returned.
-    self.assertEqual(expected_files, files_returned)
-    # Assert that only the returned files are in the outdir.
-    self.assertEqual(set(os.listdir(os.path.join(self.tempdir, dirname))),
-                     files_returned)
-    for fname in fnames:
-      with open(fname, 'r') as f:
-        if 'A_mW' in fname:
-          self.assertEqual('99999.50', f.readline().strip())
-          self.assertEqual('100000.50', f.readline().strip())
-        if 'B_mV' in fname:
-          self.assertEqual('1.50', f.readline().strip())
-          self.assertEqual('2.50', f.readline().strip())
-          self.assertEqual('3.50', f.readline().strip())
-
-  def test_SaveRawDataNoUnit(self):
-    """SaveRawData appends no unit suffix if the unit is not specified."""
-    self._populate_mock_stats_no_unit()
-    self.data.CalculateStats()
-    outdir = 'unittest_raw_data'
-    files = self.data.SaveRawData(self.tempdir, outdir)
-    files = [os.path.basename(f) for f in files]
-    # Verify nothing gets appended to domain for filename if no unit exists.
-    self.assertIn('B.txt', files)
-
-  def test_SaveRawDataSMID(self):
-    """SaveRawData uses the smid when creating output filename."""
-    identifier = 'ec'
-    self.data = stats_manager.StatsManager(smid=identifier)
-    self._populate_mock_stats()
-    files = self.data.SaveRawData(self.tempdir)
-    for fname in files:
-      self.assertTrue(os.path.basename(fname).startswith(identifier))
-
-  def test_SummaryToStringNaNHelp(self):
-    """NaN containing row gets tagged with *, help banner gets added."""
-    help_banner_exp = '%s %s' % (stats_manager.STATS_PREFIX,
-                                 stats_manager.NAN_DESCRIPTION)
-    nan_domain = 'A-domain'
-    nan_domain_exp = '%s%s' % (nan_domain, stats_manager.NAN_TAG)
-    # NaN helper banner is added when a NaN domain is found & domain gets tagged
-    data = stats_manager.StatsManager()
-    data.AddSample(nan_domain, float('NaN'))
-    data.AddSample(nan_domain, 17)
-    data.AddSample('B-domain', 17)
-    data.CalculateStats()
-    summarystr = data.SummaryToString()
-    self.assertIn(help_banner_exp, summarystr)
-    self.assertIn(nan_domain_exp, summarystr)
-    # NaN helper banner is not added when no NaN domain output, no tagging
-    data = stats_manager.StatsManager()
-    # nan_domain in this scenario does not contain any NaN
-    data.AddSample(nan_domain, 19)
-    data.AddSample('B-domain', 17)
-    data.CalculateStats()
-    summarystr = data.SummaryToString()
-    self.assertNotIn(help_banner_exp, summarystr)
-    self.assertNotIn(nan_domain_exp, summarystr)
-
-  def test_SummaryToStringTitle(self):
-    """Title shows up in SummaryToString if title specified."""
-    title = 'titulo'
-    data = stats_manager.StatsManager(title=title)
-    self._populate_mock_stats()
-    summary_str = data.SummaryToString()
-    self.assertIn(title, summary_str)
-
-  def test_SummaryToStringHideDomains(self):
-    """Keys indicated in hide_domains are not printed in the summary."""
-    data = stats_manager.StatsManager(hide_domains=['A-domain'])
-    data.AddSample('A-domain', 17)
-    data.AddSample('B-domain', 17)
-    data.CalculateStats()
-    summary_str = data.SummaryToString()
-    self.assertIn('B-domain', summary_str)
-    self.assertNotIn('A-domain', summary_str)
-
-  def test_SummaryToStringOrder(self):
-    """Order passed into StatsManager is honoured when formatting summary."""
-    # StatsManager that should print D & B first, and the subsequent elements
-    # are sorted.
-    d_b_a_c_regexp = re.compile('D-domain.*B-domain.*A-domain.*C-domain',
-                                re.DOTALL)
-    data = stats_manager.StatsManager(order=['D-domain', 'B-domain'])
-    data.AddSample('A-domain', 17)
-    data.AddSample('B-domain', 17)
-    data.AddSample('C-domain', 17)
-    data.AddSample('D-domain', 17)
-    data.CalculateStats()
-    summary_str = data.SummaryToString()
-    self.assertRegexpMatches(summary_str, d_b_a_c_regexp)
-
-  def test_MakeUniqueFName(self):
-    data = stats_manager.StatsManager()
-    testfile = os.path.join(self.tempdir, 'testfile.txt')
-    with open(testfile, 'w') as f:
-      f.write('')
-    expected_fname = os.path.join(self.tempdir, 'testfile0.txt')
-    self.assertEqual(expected_fname, data._MakeUniqueFName(testfile))
-
-  def test_SaveSummary(self):
-    """SaveSummary properly dumps the summary into a file."""
-    self._populate_mock_stats()
-    fname = 'unittest_summary.txt'
-    expected_fname = os.path.join(self.tempdir, fname)
-    fname = self.data.SaveSummary(self.tempdir, fname)
-    # Assert the reported fname is the same as the expected fname
-    self.assertEqual(expected_fname, fname)
-    # Assert only the reported fname is output (in the tempdir)
-    self.assertEqual(set([os.path.basename(fname)]),
-                     set(os.listdir(self.tempdir)))
-    with open(fname, 'r') as f:
-      self.assertEqual(
-          '@@   NAME  COUNT       MEAN  STDDEV        MAX       MIN\n',
-          f.readline())
-      self.assertEqual(
-          '@@   A_mW      2  100000.00    0.50  100000.50  99999.50\n',
-          f.readline())
-      self.assertEqual(
-          '@@   B_mV      3       2.50    0.82       3.50      1.50\n',
-          f.readline())
-
-  def test_SaveSummarySMID(self):
-    """SaveSummary uses the smid when creating output filename."""
-    identifier = 'ec'
-    self.data = stats_manager.StatsManager(smid=identifier)
-    self._populate_mock_stats()
-    fname = os.path.basename(self.data.SaveSummary(self.tempdir))
-    self.assertTrue(fname.startswith(identifier))
-
-  def test_SaveSummaryJSON(self):
-    """SaveSummaryJSON saves the added data properly in JSON format."""
-    self._populate_mock_stats()
-    fname = 'unittest_summary.json'
-    expected_fname = os.path.join(self.tempdir, fname)
-    fname = self.data.SaveSummaryJSON(self.tempdir, fname)
-    # Assert the reported fname is the same as the expected fname
-    self.assertEqual(expected_fname, fname)
-    # Assert only the reported fname is output (in the tempdir)
-    self.assertEqual(set([os.path.basename(fname)]),
-                     set(os.listdir(self.tempdir)))
-    with open(fname, 'r') as f:
-      summary = json.load(f)
-      self.assertAlmostEqual(100000.0, summary['A']['mean'])
-      self.assertEqual('milliwatt', summary['A']['unit'])
-      self.assertAlmostEqual(2.5, summary['B']['mean'])
-      self.assertEqual('millivolt', summary['B']['unit'])
-
-  def test_SaveSummaryJSONSMID(self):
-    """SaveSummaryJSON uses the smid when creating output filename."""
-    identifier = 'ec'
-    self.data = stats_manager.StatsManager(smid=identifier)
-    self._populate_mock_stats()
-    fname = os.path.basename(self.data.SaveSummaryJSON(self.tempdir))
-    self.assertTrue(fname.startswith(identifier))
-
-  def test_SaveSummaryJSONNoUnit(self):
-    """SaveSummaryJSON marks unknown units properly as N/A."""
-    self._populate_mock_stats_no_unit()
-    self.data.CalculateStats()
-    fname = 'unittest_summary.json'
-    fname = self.data.SaveSummaryJSON(self.tempdir, fname)
-    with open(fname, 'r') as f:
-      summary = json.load(f)
-      self.assertEqual('blue', summary['A']['unit'])
-      # if no unit is specified, JSON should save 'N/A' as the unit.
-      self.assertEqual('N/A', summary['B']['unit'])
-
-if __name__ == '__main__':
-  unittest.main()
+    """Test to verify StatsManager methods work as expected.
+
+    StatsManager should collect raw data, calculate their statistics, and save
+    them in expected format.
+    """
+
+    def _populate_mock_stats(self):
+        """Create a populated & processed StatsManager to test data retrieval."""
+        self.data.AddSample("A", 99999.5)
+        self.data.AddSample("A", 100000.5)
+        self.data.SetUnit("A", "uW")
+        self.data.SetUnit("A", "mW")
+        self.data.AddSample("B", 1.5)
+        self.data.AddSample("B", 2.5)
+        self.data.AddSample("B", 3.5)
+        self.data.SetUnit("B", "mV")
+        self.data.CalculateStats()
+
+    def _populate_mock_stats_no_unit(self):
+        self.data.AddSample("B", 1000)
+        self.data.AddSample("A", 200)
+        self.data.SetUnit("A", "blue")
+
+    def setUp(self):
+        """Set up StatsManager and create a temporary directory for test."""
+        self.tempdir = tempfile.mkdtemp()
+        self.data = stats_manager.StatsManager()
+
+    def tearDown(self):
+        """Delete the temporary directory and its content."""
+        shutil.rmtree(self.tempdir)
+
+    def test_AddSample(self):
+        """Adding a sample successfully adds a sample."""
+        self.data.AddSample("Test", 1000)
+        self.data.SetUnit("Test", "test")
+        self.data.CalculateStats()
+        summary = self.data.GetSummary()
+        self.assertEqual(1, summary["Test"]["count"])
+
+    def test_AddSampleNoFloatAcceptNaN(self):
+        """Adding a non-number adds 'NaN' and doesn't raise an exception."""
+        self.data.AddSample("Test", 10)
+        self.data.AddSample("Test", 20)
+        # adding a fake NaN: one that gets converted into NaN internally
+        self.data.AddSample("Test", "fiesta")
+        # adding a real NaN
+        self.data.AddSample("Test", float("NaN"))
+        self.data.SetUnit("Test", "test")
+        self.data.CalculateStats()
+        summary = self.data.GetSummary()
+        # assert that 'NaN' as added.
+        self.assertEqual(4, summary["Test"]["count"])
+        # assert that mean, min, and max calculatings ignore the 'NaN'
+        self.assertEqual(10, summary["Test"]["min"])
+        self.assertEqual(20, summary["Test"]["max"])
+        self.assertEqual(15, summary["Test"]["mean"])
+
+    def test_AddSampleNoFloatNotAcceptNaN(self):
+        """Adding a non-number raises a StatsManagerError if accept_nan is False."""
+        self.data = stats_manager.StatsManager(accept_nan=False)
+        with self.assertRaisesRegexp(
+            stats_manager.StatsManagerError,
+            "accept_nan is false. Cannot add NaN sample.",
+        ):
+            # adding a fake NaN: one that gets converted into NaN internally
+            self.data.AddSample("Test", "fiesta")
+        with self.assertRaisesRegexp(
+            stats_manager.StatsManagerError,
+            "accept_nan is false. Cannot add NaN sample.",
+        ):
+            # adding a real NaN
+            self.data.AddSample("Test", float("NaN"))
+
+    def test_AddSampleNoUnit(self):
+        """Not adding a unit does not cause an exception on CalculateStats()."""
+        self.data.AddSample("Test", 17)
+        self.data.CalculateStats()
+        summary = self.data.GetSummary()
+        self.assertEqual(1, summary["Test"]["count"])
+
+    def test_UnitSuffix(self):
+        """Unit gets appended as a suffix in the displayed summary."""
+        self.data.AddSample("test", 250)
+        self.data.SetUnit("test", "mw")
+        self.data.CalculateStats()
+        summary_str = self.data.SummaryToString()
+        self.assertIn("test_mw", summary_str)
+
+    def test_DoubleUnitSuffix(self):
+        """If domain already ends in unit, verify that unit doesn't get appended."""
+        self.data.AddSample("test_mw", 250)
+        self.data.SetUnit("test_mw", "mw")
+        self.data.CalculateStats()
+        summary_str = self.data.SummaryToString()
+        self.assertIn("test_mw", summary_str)
+        self.assertNotIn("test_mw_mw", summary_str)
+
+    def test_GetRawData(self):
+        """GetRawData returns exact same data as fed in."""
+        self._populate_mock_stats()
+        raw_data = self.data.GetRawData()
+        self.assertListEqual([99999.5, 100000.5], raw_data["A"])
+        self.assertListEqual([1.5, 2.5, 3.5], raw_data["B"])
+
+    def test_GetSummary(self):
+        """GetSummary returns expected stats about the data fed in."""
+        self._populate_mock_stats()
+        summary = self.data.GetSummary()
+        self.assertEqual(2, summary["A"]["count"])
+        self.assertAlmostEqual(100000.5, summary["A"]["max"])
+        self.assertAlmostEqual(99999.5, summary["A"]["min"])
+        self.assertAlmostEqual(0.5, summary["A"]["stddev"])
+        self.assertAlmostEqual(100000.0, summary["A"]["mean"])
+        self.assertEqual(3, summary["B"]["count"])
+        self.assertAlmostEqual(3.5, summary["B"]["max"])
+        self.assertAlmostEqual(1.5, summary["B"]["min"])
+        self.assertAlmostEqual(0.81649658092773, summary["B"]["stddev"])
+        self.assertAlmostEqual(2.5, summary["B"]["mean"])
+
+    def test_SaveRawData(self):
+        """SaveRawData stores same data as fed in."""
+        self._populate_mock_stats()
+        dirname = "unittest_raw_data"
+        expected_files = set(["A_mW.txt", "B_mV.txt"])
+        fnames = self.data.SaveRawData(self.tempdir, dirname)
+        files_returned = set([os.path.basename(f) for f in fnames])
+        # Assert that only the expected files got returned.
+        self.assertEqual(expected_files, files_returned)
+        # Assert that only the returned files are in the outdir.
+        self.assertEqual(
+            set(os.listdir(os.path.join(self.tempdir, dirname))), files_returned
+        )
+        for fname in fnames:
+            with open(fname, "r") as f:
+                if "A_mW" in fname:
+                    self.assertEqual("99999.50", f.readline().strip())
+                    self.assertEqual("100000.50", f.readline().strip())
+                if "B_mV" in fname:
+                    self.assertEqual("1.50", f.readline().strip())
+                    self.assertEqual("2.50", f.readline().strip())
+                    self.assertEqual("3.50", f.readline().strip())
+
+    def test_SaveRawDataNoUnit(self):
+        """SaveRawData appends no unit suffix if the unit is not specified."""
+        self._populate_mock_stats_no_unit()
+        self.data.CalculateStats()
+        outdir = "unittest_raw_data"
+        files = self.data.SaveRawData(self.tempdir, outdir)
+        files = [os.path.basename(f) for f in files]
+        # Verify nothing gets appended to domain for filename if no unit exists.
+        self.assertIn("B.txt", files)
+
+    def test_SaveRawDataSMID(self):
+        """SaveRawData uses the smid when creating output filename."""
+        identifier = "ec"
+        self.data = stats_manager.StatsManager(smid=identifier)
+        self._populate_mock_stats()
+        files = self.data.SaveRawData(self.tempdir)
+        for fname in files:
+            self.assertTrue(os.path.basename(fname).startswith(identifier))
+
+    def test_SummaryToStringNaNHelp(self):
+        """NaN containing row gets tagged with *, help banner gets added."""
+        help_banner_exp = "%s %s" % (
+            stats_manager.STATS_PREFIX,
+            stats_manager.NAN_DESCRIPTION,
+        )
+        nan_domain = "A-domain"
+        nan_domain_exp = "%s%s" % (nan_domain, stats_manager.NAN_TAG)
+        # NaN helper banner is added when a NaN domain is found & domain gets tagged
+        data = stats_manager.StatsManager()
+        data.AddSample(nan_domain, float("NaN"))
+        data.AddSample(nan_domain, 17)
+        data.AddSample("B-domain", 17)
+        data.CalculateStats()
+        summarystr = data.SummaryToString()
+        self.assertIn(help_banner_exp, summarystr)
+        self.assertIn(nan_domain_exp, summarystr)
+        # NaN helper banner is not added when no NaN domain output, no tagging
+        data = stats_manager.StatsManager()
+        # nan_domain in this scenario does not contain any NaN
+        data.AddSample(nan_domain, 19)
+        data.AddSample("B-domain", 17)
+        data.CalculateStats()
+        summarystr = data.SummaryToString()
+        self.assertNotIn(help_banner_exp, summarystr)
+        self.assertNotIn(nan_domain_exp, summarystr)
+
+    def test_SummaryToStringTitle(self):
+        """Title shows up in SummaryToString if title specified."""
+        title = "titulo"
+        data = stats_manager.StatsManager(title=title)
+        self._populate_mock_stats()
+        summary_str = data.SummaryToString()
+        self.assertIn(title, summary_str)
+
+    def test_SummaryToStringHideDomains(self):
+        """Keys indicated in hide_domains are not printed in the summary."""
+        data = stats_manager.StatsManager(hide_domains=["A-domain"])
+        data.AddSample("A-domain", 17)
+        data.AddSample("B-domain", 17)
+        data.CalculateStats()
+        summary_str = data.SummaryToString()
+        self.assertIn("B-domain", summary_str)
+        self.assertNotIn("A-domain", summary_str)
+
+    def test_SummaryToStringOrder(self):
+        """Order passed into StatsManager is honoured when formatting summary."""
+        # StatsManager that should print D & B first, and the subsequent elements
+        # are sorted.
+        d_b_a_c_regexp = re.compile(
+            "D-domain.*B-domain.*A-domain.*C-domain", re.DOTALL
+        )
+        data = stats_manager.StatsManager(order=["D-domain", "B-domain"])
+        data.AddSample("A-domain", 17)
+        data.AddSample("B-domain", 17)
+        data.AddSample("C-domain", 17)
+        data.AddSample("D-domain", 17)
+        data.CalculateStats()
+        summary_str = data.SummaryToString()
+        self.assertRegexpMatches(summary_str, d_b_a_c_regexp)
+
+    def test_MakeUniqueFName(self):
+        data = stats_manager.StatsManager()
+        testfile = os.path.join(self.tempdir, "testfile.txt")
+        with open(testfile, "w") as f:
+            f.write("")
+        expected_fname = os.path.join(self.tempdir, "testfile0.txt")
+        self.assertEqual(expected_fname, data._MakeUniqueFName(testfile))
+
+    def test_SaveSummary(self):
+        """SaveSummary properly dumps the summary into a file."""
+        self._populate_mock_stats()
+        fname = "unittest_summary.txt"
+        expected_fname = os.path.join(self.tempdir, fname)
+        fname = self.data.SaveSummary(self.tempdir, fname)
+        # Assert the reported fname is the same as the expected fname
+        self.assertEqual(expected_fname, fname)
+        # Assert only the reported fname is output (in the tempdir)
+        self.assertEqual(
+            set([os.path.basename(fname)]), set(os.listdir(self.tempdir))
+        )
+        with open(fname, "r") as f:
+            self.assertEqual(
+                "@@   NAME  COUNT       MEAN  STDDEV        MAX       MIN\n",
+                f.readline(),
+            )
+            self.assertEqual(
+                "@@   A_mW      2  100000.00    0.50  100000.50  99999.50\n",
+                f.readline(),
+            )
+            self.assertEqual(
+                "@@   B_mV      3       2.50    0.82       3.50      1.50\n",
+                f.readline(),
+            )
+
+    def test_SaveSummarySMID(self):
+        """SaveSummary uses the smid when creating output filename."""
+        identifier = "ec"
+        self.data = stats_manager.StatsManager(smid=identifier)
+        self._populate_mock_stats()
+        fname = os.path.basename(self.data.SaveSummary(self.tempdir))
+        self.assertTrue(fname.startswith(identifier))
+
+    def test_SaveSummaryJSON(self):
+        """SaveSummaryJSON saves the added data properly in JSON format."""
+        self._populate_mock_stats()
+        fname = "unittest_summary.json"
+        expected_fname = os.path.join(self.tempdir, fname)
+        fname = self.data.SaveSummaryJSON(self.tempdir, fname)
+        # Assert the reported fname is the same as the expected fname
+        self.assertEqual(expected_fname, fname)
+        # Assert only the reported fname is output (in the tempdir)
+        self.assertEqual(
+            set([os.path.basename(fname)]), set(os.listdir(self.tempdir))
+        )
+        with open(fname, "r") as f:
+            summary = json.load(f)
+            self.assertAlmostEqual(100000.0, summary["A"]["mean"])
+            self.assertEqual("milliwatt", summary["A"]["unit"])
+            self.assertAlmostEqual(2.5, summary["B"]["mean"])
+            self.assertEqual("millivolt", summary["B"]["unit"])
+
+    def test_SaveSummaryJSONSMID(self):
+        """SaveSummaryJSON uses the smid when creating output filename."""
+        identifier = "ec"
+        self.data = stats_manager.StatsManager(smid=identifier)
+        self._populate_mock_stats()
+        fname = os.path.basename(self.data.SaveSummaryJSON(self.tempdir))
+        self.assertTrue(fname.startswith(identifier))
+
+    def test_SaveSummaryJSONNoUnit(self):
+        """SaveSummaryJSON marks unknown units properly as N/A."""
+        self._populate_mock_stats_no_unit()
+        self.data.CalculateStats()
+        fname = "unittest_summary.json"
+        fname = self.data.SaveSummaryJSON(self.tempdir, fname)
+        with open(fname, "r") as f:
+            summary = json.load(f)
+            self.assertEqual("blue", summary["A"]["unit"])
+            # if no unit is specified, JSON should save 'N/A' as the unit.
+            self.assertEqual("N/A", summary["B"]["unit"])
+
+
+if __name__ == "__main__":
+    unittest.main()
diff --git a/extra/usb_serial/add_usb_serial_id b/extra/usb_serial/add_usb_serial_id
index ef8336afdc..12e0055e0b 100755
--- a/extra/usb_serial/add_usb_serial_id
+++ b/extra/usb_serial/add_usb_serial_id
@@ -1,6 +1,6 @@
 #!/bin/sh -e
 #
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/extra/usb_serial/console.py b/extra/usb_serial/console.py
index d06b33ce23..2b0ecd5f13 100755
--- a/extra/usb_serial/console.py
+++ b/extra/usb_serial/console.py
@@ -1,17 +1,14 @@
-#!/usr/bin/env python
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+#!/usr/bin/env python3
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
 
 """Allow creation of uart/console interface via usb google serial endpoint."""
 
 # Note: This is a py2/3 compatible file.
 
 from __future__ import print_function
+
 import argparse
 import array
 import os
@@ -19,25 +16,25 @@ import sys
 import termios
 import threading
 import time
-import traceback
 import tty
+
 try:
-  import usb
-except:
-  print("import usb failed")
-  print("try running these commands:")
-  print(" sudo apt-get install python-pip")
-  print(" sudo pip install --pre pyusb")
-  print()
-  sys.exit(-1)
+    import usb  # pylint:disable=import-error
+except ModuleNotFoundError:
+    print("import usb failed")
+    print("try running these commands:")
+    print(" sudo apt-get install python-pip")
+    print(" sudo pip install --pre pyusb")
+    print()
+    sys.exit(-1)
 
 import six
 
 
 def GetBuffer(stream):
-  if six.PY3:
-    return stream.buffer
-  return stream
+    if six.PY3:
+        return stream.buffer
+    return stream
 
 
 """Class Susb covers USB device discovery and initialization.
@@ -46,99 +43,103 @@ def GetBuffer(stream):
   and interface number.
 """
 
+
 class SusbError(Exception):
-  """Class for exceptions of Susb."""
-  def __init__(self, msg, value=0):
-    """SusbError constructor.
+    """Class for exceptions of Susb."""
 
-    Args:
-      msg: string, message describing error in detail
-      value: integer, value of error when non-zero status returned.  Default=0
-    """
-    super(SusbError, self).__init__(msg, value)
-    self.msg = msg
-    self.value = value
-
-class Susb():
-  """Provide USB functionality.
-
-  Instance Variables:
-  _read_ep: pyUSB read endpoint for this interface
-  _write_ep: pyUSB write endpoint for this interface
-  """
-  READ_ENDPOINT = 0x81
-  WRITE_ENDPOINT = 0x1
-  TIMEOUT_MS = 100
-
-  def __init__(self, vendor=0x18d1,
-               product=0x500f, interface=1, serialname=None):
-    """Susb constructor.
-
-    Discovers and connects to USB endpoints.
-
-    Args:
-      vendor    : usb vendor id of device
-      product   : usb product id of device
-      interface : interface number ( 1 - 8 ) of device to use
-      serialname: string of device serialnumber.
-
-    Raises:
-      SusbError: An error accessing Susb object
+    def __init__(self, msg, value=0):
+        """SusbError constructor.
+
+        Args:
+          msg: string, message describing error in detail
+          value: integer, value of error when non-zero status returned.  Default=0
+        """
+        super(SusbError, self).__init__(msg, value)
+        self.msg = msg
+        self.value = value
+
+
+class Susb:
+    """Provide USB functionality.
+
+    Instance Variables:
+    _read_ep: pyUSB read endpoint for this interface
+    _write_ep: pyUSB write endpoint for this interface
     """
-    # Find the device.
-    dev_g = usb.core.find(idVendor=vendor, idProduct=product, find_all=True)
-    dev_list = list(dev_g)
-    if dev_list is None:
-      raise SusbError("USB device not found")
-
-    # Check if we have multiple devices.
-    dev = None
-    if serialname:
-      for d in dev_list:
-        dev_serial = "PyUSB doesn't have a stable interface"
-        try:
-          dev_serial = usb.util.get_string(d, 256, d.iSerialNumber)
-        except:
-          dev_serial = usb.util.get_string(d, d.iSerialNumber)
-        if dev_serial == serialname:
-          dev = d
-          break
-      if dev is None:
-        raise SusbError("USB device(%s) not found" % (serialname,))
-    else:
-      try:
-        dev = dev_list[0]
-      except:
-        try:
-          dev = dev_list.next()
-        except:
-          raise SusbError("USB device %04x:%04x not found" % (vendor, product))
 
-    # If we can't set configuration, it's already been set.
-    try:
-      dev.set_configuration()
-    except usb.core.USBError:
-      pass
+    READ_ENDPOINT = 0x81
+    WRITE_ENDPOINT = 0x1
+    TIMEOUT_MS = 100
+
+    def __init__(
+        self, vendor=0x18D1, product=0x500F, interface=1, serialname=None
+    ):
+        """Susb constructor.
+
+        Discovers and connects to USB endpoints.
+
+        Args:
+          vendor: usb vendor id of device
+          product: usb product id of device
+          interface: interface number ( 1 - 8 ) of device to use
+          serialname: string of device serialnumber.
+
+        Raises:
+          SusbError: An error accessing Susb object
+        """
+        # Find the device.
+        dev_g = usb.core.find(idVendor=vendor, idProduct=product, find_all=True)
+        dev_list = list(dev_g)
+        if dev_list is None:
+            raise SusbError("USB device not found")
+
+        # Check if we have multiple devices.
+        dev = None
+        if serialname:
+            for d in dev_list:
+                dev_serial = usb.util.get_string(d, d.iSerialNumber)
+                if dev_serial == serialname:
+                    dev = d
+                    break
+            if dev is None:
+                raise SusbError("USB device(%s) not found" % (serialname,))
+        else:
+            try:
+                dev = dev_list[0]
+            except IndexError:
+                raise SusbError(
+                    "USB device %04x:%04x not found" % (vendor, product)
+                )
+
+        # If we can't set configuration, it's already been set.
+        try:
+            dev.set_configuration()
+        except usb.core.USBError:
+            pass
 
-    # Get an endpoint instance.
-    cfg = dev.get_active_configuration()
-    intf = usb.util.find_descriptor(cfg, bInterfaceNumber=interface)
-    self._intf = intf
+        # Get an endpoint instance.
+        cfg = dev.get_active_configuration()
+        intf = usb.util.find_descriptor(cfg, bInterfaceNumber=interface)
+        self._intf = intf
 
-    if not intf:
-      raise SusbError("Interface not found")
+        if not intf:
+            raise SusbError("Interface not found")
 
-    # Detach raiden.ko if it is loaded.
-    if dev.is_kernel_driver_active(intf.bInterfaceNumber) is True:
+        # Detach raiden.ko if it is loaded.
+        if dev.is_kernel_driver_active(intf.bInterfaceNumber) is True:
             dev.detach_kernel_driver(intf.bInterfaceNumber)
 
-    read_ep_number = intf.bInterfaceNumber + self.READ_ENDPOINT
-    read_ep = usb.util.find_descriptor(intf, bEndpointAddress=read_ep_number)
-    self._read_ep = read_ep
+        read_ep_number = intf.bInterfaceNumber + self.READ_ENDPOINT
+        read_ep = usb.util.find_descriptor(
+            intf, bEndpointAddress=read_ep_number
+        )
+        self._read_ep = read_ep
 
-    write_ep_number = intf.bInterfaceNumber + self.WRITE_ENDPOINT
-    write_ep = usb.util.find_descriptor(intf, bEndpointAddress=write_ep_number)
-    self._write_ep = write_ep
+        write_ep_number = intf.bInterfaceNumber + self.WRITE_ENDPOINT
+        write_ep = usb.util.find_descriptor(
+            intf, bEndpointAddress=write_ep_number
+        )
+        self._write_ep = write_ep
 
 
 """Suart class implements a stream interface, to access Google's USB class.
@@ -147,90 +148,96 @@ class Susb():
   and forwards them across. This particular class is hardcoded to stdin/out.
 """
 
-class SuartError(Exception):
-  """Class for exceptions of Suart."""
-  def __init__(self, msg, value=0):
-    """SuartError constructor.
-
-    Args:
-      msg: string, message describing error in detail
-      value: integer, value of error when non-zero status returned.  Default=0
-    """
-    super(SuartError, self).__init__(msg, value)
-    self.msg = msg
-    self.value = value
-
-
-class Suart():
-  """Provide interface to serial usb endpoint."""
-
-  def __init__(self, vendor=0x18d1, product=0x501c, interface=0,
-               serialname=None):
-    """Suart contstructor.
-
-    Initializes USB stream interface.
-
-    Args:
-      vendor: usb vendor id of device
-      product: usb product id of device
-      interface: interface number of device to use
-      serialname: Defaults to None.
-
-    Raises:
-      SuartError: If init fails
-    """
-    self._done = threading.Event()
-    self._susb = Susb(vendor=vendor, product=product,
-        interface=interface, serialname=serialname)
-
-  def wait_until_done(self, timeout=None):
-    return self._done.wait(timeout=timeout)
-
-  def run_rx_thread(self):
-    try:
-      while True:
-          try:
-            r = self._susb._read_ep.read(64, self._susb.TIMEOUT_MS)
-            if r:
-              GetBuffer(sys.stdout).write(r.tobytes())
-              GetBuffer(sys.stdout).flush()
-
-          except Exception as e:
-            # If we miss some characters on pty disconnect, that's fine.
-            # ep.read() also throws USBError on timeout, which we discard.
-            if not isinstance(e, (OSError, usb.core.USBError)):
-              print("rx %s" % e)
-    finally:
-      self._done.set()
-
-  def run_tx_thread(self):
-    try:
-      while True:
-          try:
-            r = GetBuffer(sys.stdin).read(1)
-            if not r or r == b"\x03":
-              break
-            if r:
-              self._susb._write_ep.write(array.array('B', r),
-                                         self._susb.TIMEOUT_MS)
-          except Exception as e:
-            print("tx %s" % e)
-    finally:
-      self._done.set()
-
-  def run(self):
-    """Creates pthreads to poll USB & PTY for data.
-    """
-    self._exit = False
-
-    self._rx_thread = threading.Thread(target=self.run_rx_thread)
-    self._rx_thread.daemon = True
-    self._rx_thread.start()
-
-    self._tx_thread = threading.Thread(target=self.run_tx_thread)
-    self._tx_thread.daemon = True
-    self._tx_thread.start()
 
+class SuartError(Exception):
+    """Class for exceptions of Suart."""
+
+    def __init__(self, msg, value=0):
+        """SuartError constructor.
+
+        Args:
+          msg: string, message describing error in detail
+          value: integer, value of error when non-zero status returned.  Default=0
+        """
+        super(SuartError, self).__init__(msg, value)
+        self.msg = msg
+        self.value = value
+
+
+class Suart:
+    """Provide interface to serial usb endpoint."""
+
+    def __init__(
+        self, vendor=0x18D1, product=0x501C, interface=0, serialname=None
+    ):
+        """Suart contstructor.
+
+        Initializes USB stream interface.
+
+        Args:
+          vendor: usb vendor id of device
+          product: usb product id of device
+          interface: interface number of device to use
+          serialname: Defaults to None.
+
+        Raises:
+          SuartError: If init fails
+        """
+        self._done = threading.Event()
+        self._susb = Susb(
+            vendor=vendor,
+            product=product,
+            interface=interface,
+            serialname=serialname,
+        )
+
+    def wait_until_done(self, timeout=None):
+        return self._done.wait(timeout=timeout)
+
+    def run_rx_thread(self):
+        try:
+            while True:
+                try:
+                    r = self._susb._read_ep.read(64, self._susb.TIMEOUT_MS)
+                    if r:
+                        GetBuffer(sys.stdout).write(r.tobytes())
+                        GetBuffer(sys.stdout).flush()
+
+                except Exception as e:
+                    # If we miss some characters on pty disconnect, that's fine.
+                    # ep.read() also throws USBError on timeout, which we discard.
+                    if not isinstance(e, (OSError, usb.core.USBError)):
+                        print("rx %s" % e)
+        finally:
+            self._done.set()
+
+    def run_tx_thread(self):
+        try:
+            while True:
+                try:
+                    r = GetBuffer(sys.stdin).read(1)
+                    if not r or r == b"\x03":
+                        break
+                    if r:
+                        self._susb._write_ep.write(
+                            array.array("B", r), self._susb.TIMEOUT_MS
+                        )
+                except Exception as e:
+                    print("tx %s" % e)
+        finally:
+            self._done.set()
+
+    def run(self):
+        """Creates pthreads to poll USB & PTY for data."""
+        self._exit = False
+
+        self._rx_thread = threading.Thread(target=self.run_rx_thread)
+        self._rx_thread.daemon = True
+        self._rx_thread.start()
+
+        self._tx_thread = threading.Thread(target=self.run_tx_thread)
+        self._tx_thread.daemon = True
+        self._tx_thread.start()
 
 
 """Command line functionality
@@ -239,60 +246,76 @@ class Suart():
   Ctrl-C exits.
 """
 
-parser = argparse.ArgumentParser(description="Open a console to a USB device")
-parser.add_argument('-d', '--device', type=str,
-    help="vid:pid of target device", default="18d1:501c")
-parser.add_argument('-i', '--interface', type=int,
-    help="interface number of console", default=0)
-parser.add_argument('-s', '--serialno', type=str,
-    help="serial number of device", default="")
-parser.add_argument('-S', '--notty-exit-sleep', type=float, default=0.2,
-    help="When stdin is *not* a TTY, wait this many seconds after EOF from "
-    "stdin before exiting, to give time for receiving a reply from the USB "
-    "device.")
+parser = argparse.ArgumentParser(
+    description="Open a console to a USB device",
+    formatter_class=argparse.ArgumentDefaultsHelpFormatter,
+)
+parser.add_argument(
+    "-d",
+    "--device",
+    type=str,
+    help="vid:pid of target device",
+    default="18d1:501c",
+)
+parser.add_argument(
+    "-i", "--interface", type=int, help="interface number of console", default=0
+)
+parser.add_argument(
+    "-s", "--serialno", type=str, help="serial number of device", default=""
+)
+parser.add_argument(
+    "-S",
+    "--notty-exit-sleep",
+    type=float,
+    default=0.2,
+    help="When stdin is *not* a TTY, wait this many seconds "
+    "after EOF from stdin before exiting, to give time for "
+    "receiving a reply from the USB device.",
+)
 
 
 def runconsole():
-  """Run the usb console code
+    """Run the usb console code
 
-  Starts the pty thread, and idles until a ^C is caught.
-  """
-  args = parser.parse_args()
+    Starts the pty thread, and idles until a ^C is caught.
+    """
+    args = parser.parse_args()
 
-  vidstr, pidstr = args.device.split(':')
-  vid = int(vidstr, 16)
-  pid = int(pidstr, 16)
+    vidstr, pidstr = args.device.split(":")
+    vid = int(vidstr, 16)
+    pid = int(pidstr, 16)
 
-  serialno = args.serialno
-  interface = args.interface
+    serialno = args.serialno
+    interface = args.interface
 
-  sobj = Suart(vendor=vid, product=pid, interface=interface,
-               serialname=serialno)
-  if sys.stdin.isatty():
-    tty.setraw(sys.stdin.fileno())
-  sobj.run()
-  sobj.wait_until_done()
-  if not sys.stdin.isatty() and args.notty_exit_sleep > 0:
-    time.sleep(args.notty_exit_sleep)
+    sobj = Suart(
+        vendor=vid, product=pid, interface=interface, serialname=serialno
+    )
+    if sys.stdin.isatty():
+        tty.setraw(sys.stdin.fileno())
+    sobj.run()
+    sobj.wait_until_done()
+    if not sys.stdin.isatty() and args.notty_exit_sleep > 0:
+        time.sleep(args.notty_exit_sleep)
 
 
 def main():
-  stdin_isatty = sys.stdin.isatty()
-  if stdin_isatty:
-    fd = sys.stdin.fileno()
-    os.system("stty -echo")
-    old_settings = termios.tcgetattr(fd)
-
-  try:
-    runconsole()
-  finally:
+    stdin_isatty = sys.stdin.isatty()
     if stdin_isatty:
-      termios.tcsetattr(fd, termios.TCSADRAIN, old_settings)
-      os.system("stty echo")
-    # Avoid having the user's shell prompt start mid-line after the final output
-    # from this program.
-    print()
+        fd = sys.stdin.fileno()
+        os.system("stty -echo")
+        old_settings = termios.tcgetattr(fd)
+
+    try:
+        runconsole()
+    finally:
+        if stdin_isatty:
+            termios.tcsetattr(fd, termios.TCSADRAIN, old_settings)
+            os.system("stty echo")
+        # Avoid having the user's shell prompt start mid-line after the final output
+        # from this program.
+        print()
 
 
-if __name__ == '__main__':
-  main()
+if __name__ == "__main__":
+    main()
diff --git a/extra/usb_serial/install b/extra/usb_serial/install
index eba1d2ac83..b49ad990e1 100755
--- a/extra/usb_serial/install
+++ b/extra/usb_serial/install
@@ -1,6 +1,6 @@
 #!/bin/sh -e
 #
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/extra/usb_serial/raiden.c b/extra/usb_serial/raiden.c
index e4720b4357..131cddb00f 100644
--- a/extra/usb_serial/raiden.c
+++ b/extra/usb_serial/raiden.c
@@ -2,7 +2,7 @@
  * USB Serial module for Raiden USB debug serial console forwarding.
  * SubClass and Protocol allocated in go/usb-ids
  *
- * Copyright 2014 The Chromium OS Authors <chromium-os-dev@chromium.org>
+ * Copyright 2014 The ChromiumOS Authors <chromium-os-dev@chromium.org>
  * Author: Anton Staaf <robotboy@chromium.org>
  *
  * This program is free software; you can redistribute it and/or modify
@@ -19,28 +19,25 @@
 
 MODULE_LICENSE("GPL");
 
-#define USB_VENDOR_ID_GOOGLE		0x18d1
-#define USB_SUBCLASS_GOOGLE_SERIAL	0x50
-#define USB_PROTOCOL_GOOGLE_SERIAL	0x01
+#define USB_VENDOR_ID_GOOGLE 0x18d1
+#define USB_SUBCLASS_GOOGLE_SERIAL 0x50
+#define USB_PROTOCOL_GOOGLE_SERIAL 0x01
 
 static struct usb_device_id const ids[] = {
-	{ USB_VENDOR_AND_INTERFACE_INFO(USB_VENDOR_ID_GOOGLE,
-					USB_CLASS_VENDOR_SPEC,
-					USB_SUBCLASS_GOOGLE_SERIAL,
-					USB_PROTOCOL_GOOGLE_SERIAL) },
-        { 0 }
+	{ USB_VENDOR_AND_INTERFACE_INFO(
+		USB_VENDOR_ID_GOOGLE, USB_CLASS_VENDOR_SPEC,
+		USB_SUBCLASS_GOOGLE_SERIAL, USB_PROTOCOL_GOOGLE_SERIAL) },
+	{ 0 }
 };
 
 MODULE_DEVICE_TABLE(usb, ids);
 
-static struct usb_serial_driver device =
-{
-	.driver    = { .owner = THIS_MODULE,
-		       .name  = "Google" },
-	.id_table  = ids,
+static struct usb_serial_driver device = {
+	.driver = { .owner = THIS_MODULE, .name = "Google" },
+	.id_table = ids,
 	.num_ports = 1,
 };
 
-static struct usb_serial_driver * const drivers[] = { &device, NULL };
+static struct usb_serial_driver *const drivers[] = { &device, NULL };
 
 module_usb_serial_driver(drivers, ids);
diff --git a/extra/usb_updater/Makefile b/extra/usb_updater/Makefile
index 1dfbc55645..5a8dc82c28 100644
--- a/extra/usb_updater/Makefile
+++ b/extra/usb_updater/Makefile
@@ -1,4 +1,4 @@
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -19,10 +19,10 @@ CFLAGS  := -std=gnu99 \
         -Wredundant-decls \
         -Wmissing-declarations
 
-ifeq (DEBUG,)
-CFLAGS += -O3
-else
+ifneq ($(DEBUG),)
 CFLAGS += -O0
+else
+CFLAGS += -O3
 endif
 
 #
@@ -52,4 +52,3 @@ clean:
 
 parser_debug: desc_parser.c
 	gcc -g -O0  -DTEST_PARSER desc_parser.c -o dp
-
diff --git a/extra/usb_updater/desc_parser.c b/extra/usb_updater/desc_parser.c
index 5bd996bdda..7e9f583902 100644
--- a/extra/usb_updater/desc_parser.c
+++ b/extra/usb_updater/desc_parser.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -75,8 +75,7 @@ static int get_next_token(char *input, size_t expected_size, char **output)
 	next_colon = strchr(input, ':');
 	if (next_colon)
 		*next_colon = '\0';
-	if (!next_colon || (expected_size &&
-			    strlen(input) != expected_size)) {
+	if (!next_colon || (expected_size && strlen(input) != expected_size)) {
 		fprintf(stderr, "Invalid entry in section %d\n",
 			section_count_);
 		return -EINVAL;
@@ -98,16 +97,15 @@ static int get_hex_value(char *input, char **output)
 
 	value = strtol(input, &e, 16);
 	if ((e && *e) || (strlen(input) > 8)) {
-		fprintf(stderr, "Invalid hex value %s in section %d\n",
-			input, section_count_);
+		fprintf(stderr, "Invalid hex value %s in section %d\n", input,
+			section_count_);
 		return -EINVAL;
 	}
 
 	return value;
 }
 
-static int parse_range(char *next_line,
-		       size_t line_len,
+static int parse_range(char *next_line, size_t line_len,
 		       struct addr_range *parsed_range)
 {
 	char *line_cursor;
@@ -299,7 +297,6 @@ int parser_get_next_range(struct addr_range **range)
 
 	*range = new_range;
 	return 0;
-
 }
 
 int parser_find_board(const char *hash_file_name, const char *board_id)
diff --git a/extra/usb_updater/desc_parser.h b/extra/usb_updater/desc_parser.h
index faa80d1a63..e459927b57 100644
--- a/extra/usb_updater/desc_parser.h
+++ b/extra/usb_updater/desc_parser.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/extra/usb_updater/fw_update.py b/extra/usb_updater/fw_update.py
index 0d7a570fc3..a77de94a7c 100755
--- a/extra/usb_updater/fw_update.py
+++ b/extra/usb_updater/fw_update.py
@@ -1,11 +1,7 @@
 #!/usr/bin/env python
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
 
 # Upload firmware over USB
 # Note: This is a py2/3 compatible file.
@@ -20,407 +16,436 @@ import struct
 import sys
 import time
 from pprint import pprint
-import usb
 
+import usb  # pylint:disable=import-error
+from ecusb.stm32usb import SusbError
 
 debug = False
-def debuglog(msg):
-  if debug:
-    print(msg)
-
-def log(msg):
-  print(msg)
-  sys.stdout.flush()
-
-
-"""Sends firmware update to CROS EC usb endpoint."""
-
-class Supdate(object):
-  """Class to access firmware update endpoints.
-
-  Usage:
-    d = Supdate()
-
-  Instance Variables:
-    _dev: pyUSB device object
-    _read_ep: pyUSB read endpoint for this interface
-    _write_ep: pyUSB write endpoint for this interface
-  """
-  USB_SUBCLASS_GOOGLE_UPDATE = 0x53
-  USB_CLASS_VENDOR = 0xFF
 
-  def __init__(self):
-    pass
 
+def debuglog(msg):
+    if debug:
+        print(msg)
 
-  def connect_usb(self, serialname=None):
-    """Initial discovery and connection to USB endpoint.
-
-    This searches for a USB device matching the VID:PID specified
-    in the config file, optionally matching a specified serialname.
-
-    Args:
-      serialname: Find the device with this serial, in case multiple
-          devices are attached.
-
-    Returns:
-      True on success.
-    Raises:
-      Exception on error.
-    """
-    # Find the stm32.
-    vendor = self._brdcfg['vid']
-    product = self._brdcfg['pid']
-
-    dev_g = usb.core.find(idVendor=vendor, idProduct=product, find_all=True)
-    dev_list = list(dev_g)
-    if dev_list is None:
-      raise Exception("Update", "USB device not found")
-
-    # Check if we have multiple stm32s and we've specified the serial.
-    dev = None
-    if serialname:
-      for d in dev_list:
-        if usb.util.get_string(d, d.iSerialNumber) == serialname:
-          dev = d
-          break
-      if dev is None:
-        raise SusbError("USB device(%s) not found" % serialname)
-    else:
-      try:
-        dev = dev_list[0]
-      except:
-        dev = dev_list.next()
-
-    debuglog("Found stm32: %04x:%04x" % (vendor, product))
-    self._dev = dev
-
-    # Get an endpoint instance.
-    try:
-      dev.set_configuration()
-    except:
-      pass
-    cfg = dev.get_active_configuration()
-
-    intf = usb.util.find_descriptor(cfg, custom_match=lambda i: \
-        i.bInterfaceClass==self.USB_CLASS_VENDOR and \
-        i.bInterfaceSubClass==self.USB_SUBCLASS_GOOGLE_UPDATE)
-
-    self._intf = intf
-    debuglog("Interface: %s" % intf)
-    debuglog("InterfaceNumber: %s" % intf.bInterfaceNumber)
-
-    read_ep = usb.util.find_descriptor(
-      intf,
-      # match the first IN endpoint
-      custom_match = \
-      lambda e: \
-          usb.util.endpoint_direction(e.bEndpointAddress) == \
-          usb.util.ENDPOINT_IN
-    )
-
-    self._read_ep = read_ep
-    debuglog("Reader endpoint: 0x%x" % read_ep.bEndpointAddress)
-
-    write_ep = usb.util.find_descriptor(
-      intf,
-      # match the first OUT endpoint
-      custom_match = \
-      lambda e: \
-          usb.util.endpoint_direction(e.bEndpointAddress) == \
-          usb.util.ENDPOINT_OUT
-    )
-
-    self._write_ep = write_ep
-    debuglog("Writer endpoint: 0x%x" % write_ep.bEndpointAddress)
-
-    return True
-
-
-  def wr_command(self, write_list, read_count=1, wtimeout=100, rtimeout=2000):
-    """Write command to logger logic..
-
-    This function writes byte command values list to stm, then reads
-    byte status.
-
-    Args:
-      write_list: list of command byte values [0~255].
-      read_count: number of status byte values to read.
-      wtimeout: mS to wait for write success
-      rtimeout: mS to wait for read success
-
-    Returns:
-      status byte, if one byte is read,
-      byte list, if multiple bytes are read,
-      None, if no bytes are read.
-
-    Interface:
-      write: [command, data ... ]
-      read: [status ]
-    """
-    debuglog("wr_command(write_list=[%s] (%d), read_count=%s)" % (
-          list(bytearray(write_list)), len(write_list), read_count))
-
-    # Clean up args from python style to correct types.
-    write_length = 0
-    if write_list:
-      write_length = len(write_list)
-    if not read_count:
-      read_count = 0
-
-    # Send command to stm32.
-    if write_list:
-      cmd = write_list
-      ret = self._write_ep.write(cmd, wtimeout)
-      debuglog("RET: %s " % ret)
-
-    # Read back response if necessary.
-    if read_count:
-      bytesread = self._read_ep.read(512, rtimeout)
-      debuglog("BYTES: [%s]" % bytesread)
-
-      if len(bytesread) != read_count:
-        debuglog("Unexpected bytes read: %d, expected: %d" % (len(bytesread), read_count))
-        pass
-
-      debuglog("STATUS: 0x%02x" % int(bytesread[0]))
-      if read_count == 1:
-        return bytesread[0]
-      else:
-        return bytesread
-
-    return None
-
-  def stop(self):
-    """Finalize system flash and exit."""
-    cmd = struct.pack(">I", 0xB007AB1E)
-    read = self.wr_command(cmd, read_count=4)
 
-    if len(read) == 4:
-      log("Finished flashing")
-      return
+def log(msg):
+    print(msg)
+    sys.stdout.flush()
 
-    raise Exception("Update", "Stop failed [%s]" % read)
 
+"""Sends firmware update to CROS EC usb endpoint."""
 
-  def write_file(self):
-    """Write the update region packet by packet to USB
 
-    This sends write packets of size 128B out, in 32B chunks.
-    Overall, this will write all data in the inactive code region.
+class Supdate(object):
+    """Class to access firmware update endpoints.
 
-    Raises:
-      Exception if write failed or address out of bounds.
-    """
-    region = self._region
-    flash_base = self._brdcfg["flash"]
-    offset = self._base - flash_base
-    if offset != self._brdcfg['regions'][region][0]:
-      raise Exception("Update", "Region %s offset 0x%x != available offset 0x%x" % (
-          region, self._brdcfg['regions'][region][0], offset))
-
-    length = self._brdcfg['regions'][region][1]
-    log("Sending")
-
-    # Go to the correct region in the ec.bin file.
-    self._binfile.seek(offset)
-
-    # Send 32 bytes at a time. Must be less than the endpoint's max packet size.
-    maxpacket = 32
-
-    # While data is left, create update packets.
-    while length > 0:
-      # Update packets are 128B. We can use any number
-      # but the micro must malloc this memory.
-      pagesize = min(length, 128)
-
-      # Packet is:
-      #  packet size: page bytes transferred plus 3 x 32b values header.
-      #  cmd: n/a
-      #  base: flash address to write this packet.
-      #  data: 128B of data to write into flash_base
-      cmd = struct.pack(">III", pagesize + 12, 0, offset + flash_base)
-      read = self.wr_command(cmd, read_count=0)
-
-      # Push 'todo' bytes out the pipe.
-      todo = pagesize
-      while todo > 0:
-        packetsize = min(maxpacket, todo)
-        data = self._binfile.read(packetsize)
-        if len(data) != packetsize:
-          raise Exception("Update", "No more data from file")
-        for i in range(0, 10):
-          try:
-            self.wr_command(data, read_count=0)
-            break
-          except:
-            log("Timeout fail")
-        todo -= packetsize
-      # Done with this packet, move to the next one.
-      length -= pagesize
-      offset += pagesize
-
-      # Validate that the micro thinks it successfully wrote the data.
-      read = self.wr_command(''.encode(), read_count=4)
-      result = struct.unpack("<I", read)
-      result = result[0]
-      if result != 0:
-        raise Exception("Update", "Upload failed with rc: 0x%x" % result)
-
-
-  def start(self):
-    """Start a transaction and erase currently inactive region.
-
-    This function sends a start command, and receives the base of the
-    preferred inactive region. This could be RW, RW_B,
-    or RO (if there's no RW_B)
-
-    Note that the region is erased here, so you'd better program the RO if
-    you just erased it. TODO(nsanders): Modify the protocol to allow active
-    region select or query before erase.
-    """
+    Usage:
+      d = Supdate()
 
-    # Size is 3 uint32 fields
-    # packet: [packetsize, cmd, base]
-    size = 4 + 4 + 4
-    # Return value is [status, base_addr]
-    expected = 4 + 4
-
-    cmd = struct.pack("<III", size, 0, 0)
-    read = self.wr_command(cmd, read_count=expected)
-
-    if len(read) == 4:
-      raise Exception("Update", "Protocol version 0 not supported")
-    elif len(read) == expected:
-      base, version = struct.unpack(">II", read)
-      log("Update protocol v. %d" % version)
-      log("Available flash region base: %x" % base)
-    else:
-      raise Exception("Update", "Start command returned %d bytes" % len(read))
-
-    if base < 256:
-      raise Exception("Update", "Start returned error code 0x%x" % base)
-
-    self._base = base
-    flash_base = self._brdcfg["flash"]
-    self._offset = self._base - flash_base
-
-    # Find our active region.
-    for region in self._brdcfg['regions']:
-      if (self._offset >= self._brdcfg['regions'][region][0]) and \
-         (self._offset < (self._brdcfg['regions'][region][0] + \
-          self._brdcfg['regions'][region][1])):
-        log("Active region: %s" % region)
-        self._region = region
-
-
-  def load_board(self, brdfile):
-    """Load firmware layout file.
-
-    example as follows:
-    {
-      "board": "servo micro",
-      "vid": 6353,
-      "pid": 20506,
-      "flash": 134217728,
-      "regions": {
-        "RW": [65536, 65536],
-        "PSTATE": [61440, 4096],
-        "RO": [0, 61440]
-      }
-    }
-
-    Args:
-      brdfile: path to board description file.
+    Instance Variables:
+      _dev: pyUSB device object
+      _read_ep: pyUSB read endpoint for this interface
+      _write_ep: pyUSB write endpoint for this interface
     """
-    with open(brdfile) as data_file:
-        data = json.load(data_file)
-
-    # TODO(nsanders): validate this data before moving on.
-    self._brdcfg = data;
-    if debug:
-      pprint(data)
-
-    log("Board is %s" % self._brdcfg['board'])
-    # Cast hex strings to int.
-    self._brdcfg['flash'] = int(self._brdcfg['flash'], 0)
-    self._brdcfg['vid'] = int(self._brdcfg['vid'], 0)
-    self._brdcfg['pid'] = int(self._brdcfg['pid'], 0)
-
-    log("Flash Base is %x" % self._brdcfg['flash'])
-    self._flashsize = 0
-    for region in self._brdcfg['regions']:
-      base = int(self._brdcfg['regions'][region][0], 0)
-      length = int(self._brdcfg['regions'][region][1], 0)
-      log("region %s\tbase:0x%08x size:0x%08x" % (
-          region, base, length))
-      self._flashsize += length
 
-      # Convert these to int because json doesn't support hex.
-      self._brdcfg['regions'][region][0] = base
-      self._brdcfg['regions'][region][1] = length
+    USB_SUBCLASS_GOOGLE_UPDATE = 0x53
+    USB_CLASS_VENDOR = 0xFF
 
-    log("Flash Size: 0x%x" % self._flashsize)
-
-  def load_file(self, binfile):
-    """Open and verify size of the target ec.bin file.
-
-    Args:
-      binfile: path to ec.bin
-
-    Raises:
-      Exception on file not found or filesize not matching.
-    """
-    self._filesize = os.path.getsize(binfile)
-    self._binfile = open(binfile, 'rb')
-
-    if self._filesize != self._flashsize:
-      raise Exception("Update", "Flash size 0x%x != file size 0x%x" % (self._flashsize, self._filesize))
+    def __init__(self):
+        pass
 
+    def connect_usb(self, serialname=None):
+        """Initial discovery and connection to USB endpoint.
+
+        This searches for a USB device matching the VID:PID specified
+        in the config file, optionally matching a specified serialname.
+
+        Args:
+          serialname: Find the device with this serial, in case multiple
+              devices are attached.
+
+        Returns:
+          True on success.
+        Raises:
+          Exception on error.
+        """
+        # Find the stm32.
+        vendor = self._brdcfg["vid"]
+        product = self._brdcfg["pid"]
+
+        dev_g = usb.core.find(idVendor=vendor, idProduct=product, find_all=True)
+        dev_list = list(dev_g)
+        if dev_list is None:
+            raise Exception("Update", "USB device not found")
+
+        # Check if we have multiple stm32s and we've specified the serial.
+        dev = None
+        if serialname:
+            for d in dev_list:
+                if usb.util.get_string(d, d.iSerialNumber) == serialname:
+                    dev = d
+                    break
+            if dev is None:
+                raise SusbError("USB device(%s) not found" % serialname)
+        else:
+            dev = dev_list[0]
+
+        debuglog("Found stm32: %04x:%04x" % (vendor, product))
+        self._dev = dev
+
+        # Get an endpoint instance.
+        try:
+            dev.set_configuration()
+        except:
+            pass
+        cfg = dev.get_active_configuration()
+
+        intf = usb.util.find_descriptor(
+            cfg,
+            custom_match=lambda i: i.bInterfaceClass == self.USB_CLASS_VENDOR
+            and i.bInterfaceSubClass == self.USB_SUBCLASS_GOOGLE_UPDATE,
+        )
+
+        self._intf = intf
+        debuglog("Interface: %s" % intf)
+        debuglog("InterfaceNumber: %s" % intf.bInterfaceNumber)
+
+        read_ep = usb.util.find_descriptor(
+            intf,
+            # match the first IN endpoint
+            custom_match=lambda e: usb.util.endpoint_direction(
+                e.bEndpointAddress
+            )
+            == usb.util.ENDPOINT_IN,
+        )
+
+        self._read_ep = read_ep
+        debuglog("Reader endpoint: 0x%x" % read_ep.bEndpointAddress)
+
+        write_ep = usb.util.find_descriptor(
+            intf,
+            # match the first OUT endpoint
+            custom_match=lambda e: usb.util.endpoint_direction(
+                e.bEndpointAddress
+            )
+            == usb.util.ENDPOINT_OUT,
+        )
+
+        self._write_ep = write_ep
+        debuglog("Writer endpoint: 0x%x" % write_ep.bEndpointAddress)
+
+        return True
+
+    def wr_command(self, write_list, read_count=1, wtimeout=100, rtimeout=2000):
+        """Write command to logger logic..
+
+        This function writes byte command values list to stm, then reads
+        byte status.
+
+        Args:
+          write_list: list of command byte values [0~255].
+          read_count: number of status byte values to read.
+          wtimeout: mS to wait for write success
+          rtimeout: mS to wait for read success
+
+        Returns:
+          status byte, if one byte is read,
+          byte list, if multiple bytes are read,
+          None, if no bytes are read.
+
+        Interface:
+          write: [command, data ... ]
+          read: [status ]
+        """
+        debuglog(
+            "wr_command(write_list=[%s] (%d), read_count=%s)"
+            % (list(bytearray(write_list)), len(write_list), read_count)
+        )
+
+        # Clean up args from python style to correct types.
+        write_length = 0
+        if write_list:
+            write_length = len(write_list)
+        if not read_count:
+            read_count = 0
+
+        # Send command to stm32.
+        if write_list:
+            cmd = write_list
+            ret = self._write_ep.write(cmd, wtimeout)
+            debuglog("RET: %s " % ret)
+
+        # Read back response if necessary.
+        if read_count:
+            bytesread = self._read_ep.read(512, rtimeout)
+            debuglog("BYTES: [%s]" % bytesread)
+
+            if len(bytesread) != read_count:
+                debuglog(
+                    "Unexpected bytes read: %d, expected: %d"
+                    % (len(bytesread), read_count)
+                )
+                pass
+
+            debuglog("STATUS: 0x%02x" % int(bytesread[0]))
+            if read_count == 1:
+                return bytesread[0]
+            else:
+                return bytesread
+
+        return None
+
+    def stop(self):
+        """Finalize system flash and exit."""
+        cmd = struct.pack(">I", 0xB007AB1E)
+        read = self.wr_command(cmd, read_count=4)
+
+        if len(read) == 4:
+            log("Finished flashing")
+            return
+
+        raise Exception("Update", "Stop failed [%s]" % read)
+
+    def write_file(self):
+        """Write the update region packet by packet to USB
+
+        This sends write packets of size 128B out, in 32B chunks.
+        Overall, this will write all data in the inactive code region.
+
+        Raises:
+          Exception if write failed or address out of bounds.
+        """
+        region = self._region
+        flash_base = self._brdcfg["flash"]
+        offset = self._base - flash_base
+        if offset != self._brdcfg["regions"][region][0]:
+            raise Exception(
+                "Update",
+                "Region %s offset 0x%x != available offset 0x%x"
+                % (region, self._brdcfg["regions"][region][0], offset),
+            )
+
+        length = self._brdcfg["regions"][region][1]
+        log("Sending")
+
+        # Go to the correct region in the ec.bin file.
+        self._binfile.seek(offset)
+
+        # Send 32 bytes at a time. Must be less than the endpoint's max packet size.
+        maxpacket = 32
+
+        # While data is left, create update packets.
+        while length > 0:
+            # Update packets are 128B. We can use any number
+            # but the micro must malloc this memory.
+            pagesize = min(length, 128)
+
+            # Packet is:
+            #  packet size: page bytes transferred plus 3 x 32b values header.
+            #  cmd: n/a
+            #  base: flash address to write this packet.
+            #  data: 128B of data to write into flash_base
+            cmd = struct.pack(">III", pagesize + 12, 0, offset + flash_base)
+            read = self.wr_command(cmd, read_count=0)
+
+            # Push 'todo' bytes out the pipe.
+            todo = pagesize
+            while todo > 0:
+                packetsize = min(maxpacket, todo)
+                data = self._binfile.read(packetsize)
+                if len(data) != packetsize:
+                    raise Exception("Update", "No more data from file")
+                for i in range(0, 10):
+                    try:
+                        self.wr_command(data, read_count=0)
+                        break
+                    except:
+                        log("Timeout fail")
+                todo -= packetsize
+            # Done with this packet, move to the next one.
+            length -= pagesize
+            offset += pagesize
+
+            # Validate that the micro thinks it successfully wrote the data.
+            read = self.wr_command("".encode(), read_count=4)
+            result = struct.unpack("<I", read)
+            result = result[0]
+            if result != 0:
+                raise Exception(
+                    "Update", "Upload failed with rc: 0x%x" % result
+                )
+
+    def start(self):
+        """Start a transaction and erase currently inactive region.
+
+        This function sends a start command, and receives the base of the
+        preferred inactive region. This could be RW, RW_B,
+        or RO (if there's no RW_B)
+
+        Note that the region is erased here, so you'd better program the RO if
+        you just erased it. TODO(nsanders): Modify the protocol to allow active
+        region select or query before erase.
+        """
+
+        # Size is 3 uint32 fields
+        # packet: [packetsize, cmd, base]
+        size = 4 + 4 + 4
+        # Return value is [status, base_addr]
+        expected = 4 + 4
+
+        cmd = struct.pack("<III", size, 0, 0)
+        read = self.wr_command(cmd, read_count=expected)
+
+        if len(read) == 4:
+            raise Exception("Update", "Protocol version 0 not supported")
+        elif len(read) == expected:
+            base, version = struct.unpack(">II", read)
+            log("Update protocol v. %d" % version)
+            log("Available flash region base: %x" % base)
+        else:
+            raise Exception(
+                "Update", "Start command returned %d bytes" % len(read)
+            )
+
+        if base < 256:
+            raise Exception("Update", "Start returned error code 0x%x" % base)
+
+        self._base = base
+        flash_base = self._brdcfg["flash"]
+        self._offset = self._base - flash_base
+
+        # Find our active region.
+        for region in self._brdcfg["regions"]:
+            if (self._offset >= self._brdcfg["regions"][region][0]) and (
+                self._offset
+                < (
+                    self._brdcfg["regions"][region][0]
+                    + self._brdcfg["regions"][region][1]
+                )
+            ):
+                log("Active region: %s" % region)
+                self._region = region
+
+    def load_board(self, brdfile):
+        """Load firmware layout file.
+
+        example as follows:
+        {
+          "board": "servo micro",
+          "vid": 6353,
+          "pid": 20506,
+          "flash": 134217728,
+          "regions": {
+            "RW": [65536, 65536],
+            "PSTATE": [61440, 4096],
+            "RO": [0, 61440]
+          }
+        }
+
+        Args:
+          brdfile: path to board description file.
+        """
+        with open(brdfile) as data_file:
+            data = json.load(data_file)
+
+        # TODO(nsanders): validate this data before moving on.
+        self._brdcfg = data
+        if debug:
+            pprint(data)
+
+        log("Board is %s" % self._brdcfg["board"])
+        # Cast hex strings to int.
+        self._brdcfg["flash"] = int(self._brdcfg["flash"], 0)
+        self._brdcfg["vid"] = int(self._brdcfg["vid"], 0)
+        self._brdcfg["pid"] = int(self._brdcfg["pid"], 0)
+
+        log("Flash Base is %x" % self._brdcfg["flash"])
+        self._flashsize = 0
+        for region in self._brdcfg["regions"]:
+            base = int(self._brdcfg["regions"][region][0], 0)
+            length = int(self._brdcfg["regions"][region][1], 0)
+            log("region %s\tbase:0x%08x size:0x%08x" % (region, base, length))
+            self._flashsize += length
+
+            # Convert these to int because json doesn't support hex.
+            self._brdcfg["regions"][region][0] = base
+            self._brdcfg["regions"][region][1] = length
+
+        log("Flash Size: 0x%x" % self._flashsize)
+
+    def load_file(self, binfile):
+        """Open and verify size of the target ec.bin file.
+
+        Args:
+          binfile: path to ec.bin
+
+        Raises:
+          Exception on file not found or filesize not matching.
+        """
+        self._filesize = os.path.getsize(binfile)
+        self._binfile = open(binfile, "rb")
+
+        if self._filesize != self._flashsize:
+            raise Exception(
+                "Update",
+                "Flash size 0x%x != file size 0x%x"
+                % (self._flashsize, self._filesize),
+            )
 
 
 # Generate command line arguments
 parser = argparse.ArgumentParser(description="Update firmware over usb")
-parser.add_argument('-b', '--board', type=str, help="Board configuration json file", default="board.json")
-parser.add_argument('-f', '--file', type=str, help="Complete ec.bin file", default="ec.bin")
-parser.add_argument('-s', '--serial', type=str, help="Serial number", default="")
-parser.add_argument('-l', '--list', action="store_true", help="List regions")
-parser.add_argument('-v', '--verbose', action="store_true", help="Chatty output")
+parser.add_argument(
+    "-b",
+    "--board",
+    type=str,
+    help="Board configuration json file",
+    default="board.json",
+)
+parser.add_argument(
+    "-f", "--file", type=str, help="Complete ec.bin file", default="ec.bin"
+)
+parser.add_argument(
+    "-s", "--serial", type=str, help="Serial number", default=""
+)
+parser.add_argument("-l", "--list", action="store_true", help="List regions")
+parser.add_argument(
+    "-v", "--verbose", action="store_true", help="Chatty output"
+)
+
 
 def main():
-  global debug
-  args = parser.parse_args()
+    global debug
+    args = parser.parse_args()
 
+    brdfile = args.board
+    serial = args.serial
+    binfile = args.file
+    if args.verbose:
+        debug = True
 
-  brdfile = args.board
-  serial = args.serial
-  binfile = args.file
-  if args.verbose:
-    debug = True
+    with open(brdfile) as data_file:
+        names = json.load(data_file)
 
-  with open(brdfile) as data_file:
-    names = json.load(data_file)
+    p = Supdate()
+    p.load_board(brdfile)
+    p.connect_usb(serialname=serial)
+    p.load_file(binfile)
 
-  p = Supdate()
-  p.load_board(brdfile)
-  p.connect_usb(serialname=serial)
-  p.load_file(binfile)
+    # List solely prints the config.
+    if args.list:
+        return
 
-  # List solely prints the config.
-  if (args.list):
-    return
+    # Start transfer and erase.
+    p.start()
+    # Upload the bin file
+    log("Uploading %s" % binfile)
+    p.write_file()
 
-  # Start transfer and erase.
-  p.start()
-  # Upload the bin file
-  log("Uploading %s" % binfile)
-  p.write_file()
+    # Finalize
+    log("Done. Finalizing.")
+    p.stop()
 
-  # Finalize
-  log("Done. Finalizing.")
-  p.stop()
 
 if __name__ == "__main__":
-  main()
-
-
+    main()
diff --git a/extra/usb_updater/sample_descriptor b/extra/usb_updater/sample_descriptor
index 1566e9e2e1..3be408b642 100644
--- a/extra/usb_updater/sample_descriptor
+++ b/extra/usb_updater/sample_descriptor
@@ -1,4 +1,4 @@
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/extra/usb_updater/servo_updater.py b/extra/usb_updater/servo_updater.py
index fa0d21670c..c0be11fdde 100755
--- a/extra/usb_updater/servo_updater.py
+++ b/extra/usb_updater/servo_updater.py
@@ -1,53 +1,55 @@
 #!/usr/bin/env python
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
 
 # Note: This is a py2/3 compatible file.
 
+"""USB updater tool for servo and similar boards."""
+
 from __future__ import print_function
 
 import argparse
-import errno
+import json
 import os
 import re
 import subprocess
 import time
-import tempfile
-
-import json
 
-import fw_update
 import ecusb.tiny_servo_common as c
+import fw_update
 from ecusb import tiny_servod
 
+
 class ServoUpdaterException(Exception):
-  """Raised on exceptions generated by servo_updater."""
+    """Raised on exceptions generated by servo_updater."""
 
-BOARD_C2D2 = 'c2d2'
-BOARD_SERVO_MICRO = 'servo_micro'
-BOARD_SERVO_V4 = 'servo_v4'
-BOARD_SERVO_V4P1 = 'servo_v4p1'
-BOARD_SWEETBERRY = 'sweetberry'
+
+BOARD_C2D2 = "c2d2"
+BOARD_SERVO_MICRO = "servo_micro"
+BOARD_SERVO_V4 = "servo_v4"
+BOARD_SERVO_V4P1 = "servo_v4p1"
+BOARD_SWEETBERRY = "sweetberry"
 
 DEFAULT_BOARD = BOARD_SERVO_V4
 
 # These lists are to facilitate exposing choices in the command-line tool
 # below.
-BOARDS = [BOARD_C2D2, BOARD_SERVO_MICRO, BOARD_SERVO_V4, BOARD_SERVO_V4P1,
-          BOARD_SWEETBERRY]
+BOARDS = [
+    BOARD_C2D2,
+    BOARD_SERVO_MICRO,
+    BOARD_SERVO_V4,
+    BOARD_SERVO_V4P1,
+    BOARD_SWEETBERRY,
+]
 
 # Servo firmware bundles four channels of firmware. We need to make sure the
 # user does not request a non-existing channel, so keep the lists around to
 # guard on command-line usage.
 
-DEFAULT_CHANNEL = STABLE_CHANNEL = 'stable'
+DEFAULT_CHANNEL = STABLE_CHANNEL = "stable"
 
-PREV_CHANNEL = 'prev'
+PREV_CHANNEL = "prev"
 
 # The ordering here matters. From left to right it's the channel that the user
 # is most likely to be running. This is used to inform and warn the user if
@@ -55,12 +57,12 @@ PREV_CHANNEL = 'prev'
 # user know they are running the 'stable' version before letting them know they
 # are running 'dev' or even 'alpah' which (while true) might cause confusion.
 
-CHANNELS = [DEFAULT_CHANNEL, PREV_CHANNEL, 'dev', 'alpha']
+CHANNELS = [DEFAULT_CHANNEL, PREV_CHANNEL, "dev", "alpha"]
 
-DEFAULT_BASE_PATH = '/usr/'
-TEST_IMAGE_BASE_PATH = '/usr/local/'
+DEFAULT_BASE_PATH = "/usr/"
+TEST_IMAGE_BASE_PATH = "/usr/local/"
 
-COMMON_PATH = 'share/servo_updater'
+COMMON_PATH = "share/servo_updater"
 
 FIRMWARE_DIR = "firmware/"
 CONFIGS_DIR = "configs/"
@@ -68,389 +70,444 @@ CONFIGS_DIR = "configs/"
 RETRIES_COUNT = 10
 RETRIES_DELAY = 1
 
+
 def do_with_retries(func, *args):
-  """
-  Call function passed as argument and check if no error happened.
-  If exception was raised by function,
-  it will be retried up to RETRIES_COUNT times.
-
-  Args:
-    func: function that will be called
-    args: arguments passed to 'func'
-
-  Returns:
-    If call to function was successful, its result will be returned.
-    If retries count was exceeded, exception will be raised.
-  """
-
-  retry = 0
-  while retry < RETRIES_COUNT:
-    try:
-      return func(*args)
-    except Exception as e:
-      print("Retrying function %s: %s" % (func.__name__, e))
-      retry = retry + 1
-      time.sleep(RETRIES_DELAY)
-      continue
-
-  raise Exception("'{}' failed after {} retries".format(func.__name__, RETRIES_COUNT))
+    """Try a function several times
+
+    Call function passed as argument and check if no error happened.
+    If exception was raised by function,
+    it will be retried up to RETRIES_COUNT times.
+
+    Args:
+      func: function that will be called
+      args: arguments passed to 'func'
+
+    Returns:
+      If call to function was successful, its result will be returned.
+      If retries count was exceeded, exception will be raised.
+    """
+
+    retry = 0
+    while retry < RETRIES_COUNT:
+        try:
+            return func(*args)
+        except Exception as e:
+            print("Retrying function %s: %s" % (func.__name__, e))
+            retry = retry + 1
+            time.sleep(RETRIES_DELAY)
+            continue
+
+    raise Exception(
+        "'{}' failed after {} retries".format(func.__name__, RETRIES_COUNT)
+    )
+
 
 def flash(brdfile, serialno, binfile):
-  """
-  Call fw_update to upload to updater USB endpoint.
-
-  Args:
-    brdfile:  path to board configuration file
-    serialno: device serial number
-    binfile:  firmware file
-  """
-
-  p = fw_update.Supdate()
-  p.load_board(brdfile)
-  p.connect_usb(serialname=serialno)
-  p.load_file(binfile)
-
-  # Start transfer and erase.
-  p.start()
-  # Upload the bin file
-  print("Uploading %s" % binfile)
-  p.write_file()
-
-  # Finalize
-  print("Done. Finalizing.")
-  p.stop()
+    """Call fw_update to upload to updater USB endpoint.
+
+    Args:
+      brdfile: path to board configuration file
+      serialno: device serial number
+      binfile: firmware file
+    """
+
+    p = fw_update.Supdate()
+    p.load_board(brdfile)
+    p.connect_usb(serialname=serialno)
+    p.load_file(binfile)
+
+    # Start transfer and erase.
+    p.start()
+    # Upload the bin file
+    print("Uploading %s" % binfile)
+    p.write_file()
+
+    # Finalize
+    print("Done. Finalizing.")
+    p.stop()
+
 
 def flash2(vidpid, serialno, binfile):
-  """
-  Call fw update via usb_updater2 commandline.
-
-  Args:
-    vidpid:   vendor id and product id of device
-    serialno: device serial number (optional)
-    binfile:  firmware file
-  """
-
-  tool = 'usb_updater2'
-  cmd = "%s -d %s" % (tool, vidpid)
-  if serialno:
-    cmd += " -S %s" % serialno
-  cmd += " -n"
-  cmd += " %s" % binfile
-
-  print(cmd)
-  help_cmd = '%s --help' % tool
-  with open('/dev/null') as devnull:
-    valid_check = subprocess.call(help_cmd.split(), stdout=devnull,
-                                  stderr=devnull)
-  if valid_check:
-    raise ServoUpdaterException('%s exit with res = %d. Make sure the tool '
-                                'is available on the device.' % (help_cmd,
-                                                                 valid_check))
-  res = subprocess.call(cmd.split())
-
-  if res in (0, 1, 2):
-    return res
-  else:
-    raise ServoUpdaterException("%s exit with res = %d" % (cmd, res))
+    """Call fw update via usb_updater2 commandline.
+
+    Args:
+      vidpid: vendor id and product id of device
+      serialno: device serial number (optional)
+      binfile: firmware file
+    """
+
+    tool = "usb_updater2"
+    cmd = "%s -d %s" % (tool, vidpid)
+    if serialno:
+        cmd += " -S %s" % serialno
+    cmd += " -n"
+    cmd += " %s" % binfile
+
+    print(cmd)
+    help_cmd = "%s --help" % tool
+    with open("/dev/null") as devnull:
+        valid_check = subprocess.call(
+            help_cmd.split(), stdout=devnull, stderr=devnull
+        )
+    if valid_check:
+        raise ServoUpdaterException(
+            "%s exit with res = %d. Make sure the tool "
+            "is available on the device." % (help_cmd, valid_check)
+        )
+    res = subprocess.call(cmd.split())
+
+    if res in (0, 1, 2):
+        return res
+    else:
+        raise ServoUpdaterException("%s exit with res = %d" % (cmd, res))
+
 
 def select(tinys, region):
-  """
-  Ensure the servo is in the expected ro/rw region.
-  This function jumps to the required region and verify if jump was
-  successful by executing 'sysinfo' command and reading current region.
-  If response was not received or region is invalid, exception is raised.
+    """Jump to specified boot region
 
-  Args:
-    tinys:  TinyServod object
-    region: region to jump to, only "rw" and "ro" is allowed
-  """
+    Ensure the servo is in the expected ro/rw region.
+    This function jumps to the required region and verify if jump was
+    successful by executing 'sysinfo' command and reading current region.
+    If response was not received or region is invalid, exception is raised.
 
-  if region not in ["rw", "ro"]:
-    raise Exception("Region must be ro or rw")
+    Args:
+      tinys: TinyServod object
+      region: region to jump to, only "rw" and "ro" is allowed
+    """
+
+    if region not in ["rw", "ro"]:
+        raise Exception("Region must be ro or rw")
+
+    if region == "ro":
+        cmd = "reboot"
+    else:
+        cmd = "sysjump %s" % region
 
-  if region is "ro":
-    cmd = "reboot"
-  else:
-    cmd = "sysjump %s" % region
+    tinys.pty._issue_cmd(cmd)
 
-  tinys.pty._issue_cmd(cmd)
+    tinys.close()
+    time.sleep(2)
+    tinys.reinitialize()
 
-  tinys.close()
-  time.sleep(2)
-  tinys.reinitialize()
+    res = tinys.pty._issue_cmd_get_results("sysinfo", [r"Copy:[\s]+(RO|RW)"])
+    current_region = res[0][1].lower()
+    if current_region != region:
+        raise Exception("Invalid region: %s/%s" % (current_region, region))
 
-  res = tinys.pty._issue_cmd_get_results("sysinfo", ["Copy:[\s]+(RO|RW)"])
-  current_region = res[0][1].lower()
-  if current_region != region:
-    raise Exception("Invalid region: %s/%s" % (current_region, region))
 
 def do_version(tinys):
-  """Check version via ec console 'pty'.
+    """Check version via ec console 'pty'.
 
-  Args:
-    tinys: TinyServod object
+    Args:
+      tinys: TinyServod object
 
-  Returns:
-    detected version number
+    Returns:
+      detected version number
 
-  Commands are:
-  # > version
-  # ...
-  # Build:   tigertail_v1.1.6749-74d1a312e
-  """
-  cmd = '\r\nversion\r\n'
-  regex = 'Build:\s+(\S+)[\r\n]+'
+    Commands are:
+    # > version
+    # ...
+    # Build:   tigertail_v1.1.6749-74d1a312e
+    """
+    cmd = "version"
+    regex = r"Build:\s+(\S+)[\r\n]+"
 
-  results = tinys.pty._issue_cmd_get_results(cmd, [regex])[0]
+    results = tinys.pty._issue_cmd_get_results(cmd, [regex])[0]
+
+    return results[1].strip(" \t\r\n\0")
 
-  return results[1].strip(' \t\r\n\0')
 
 def do_updater_version(tinys):
-  """Check whether this uses python updater or c++ updater
-
-  Args:
-    tinys: TinyServod object
-
-  Returns:
-    updater version number. 2 or 6.
-  """
-  vers = do_version(tinys)
-
-  # Servo versions below 58 are from servo-9040.B. Versions starting with _v2
-  # are newer than anything _v1, no need to check the exact number. Updater
-  # version is not directly queryable.
-  if re.search('_v[2-9]\.\d', vers):
-    return 6
-  m = re.search('_v1\.1\.(\d\d\d\d)', vers)
-  if m:
-    version_number = int(m.group(1))
-    if version_number < 5800:
-      return 2
-    else:
-      return 6
-  raise ServoUpdaterException(
-      "Can't determine updater target from vers: [%s]" % vers)
+    """Check whether this uses python updater or c++ updater
 
-def _extract_version(boardname, binfile):
-  """Find the version string from |binfile|.
+    Args:
+      tinys: TinyServod object
 
-  Args:
-    boardname: the name of the board, eg. "servo_micro"
-    binfile: path to the binary to search
+    Returns:
+      updater version number. 2 or 6.
+    """
+    vers = do_version(tinys)
 
-  Returns:
-    the version string.
-  """
-  if boardname is None:
-    # cannot extract the version if the name is None
-    return None
-  rawstrings = subprocess.check_output(
-      ['cbfstool', binfile, 'read', '-r', 'RO_FRID', '-f', '/dev/stdout'],
-      **c.get_subprocess_args())
-  m = re.match(r'%s_v\S+' % boardname, rawstrings)
-  if m:
-    newvers = m.group(0).strip(' \t\r\n\0')
-  else:
-    raise ServoUpdaterException("Can't find version from file: %s." % binfile)
+    # Servo versions below 58 are from servo-9040.B. Versions starting with _v2
+    # are newer than anything _v1, no need to check the exact number. Updater
+    # version is not directly queryable.
+    if re.search(r"_v[2-9]\.\d", vers):
+        return 6
+    m = re.search(r"_v1\.1\.(\d\d\d\d)", vers)
+    if m:
+        version_number = int(m.group(1))
+        if version_number < 5800:
+            return 2
+        else:
+            return 6
+    raise ServoUpdaterException(
+        "Can't determine updater target from vers: [%s]" % vers
+    )
+
+
+def _extract_version(boardname, binfile):
+    """Find the version string from |binfile|.
+
+    Args:
+      boardname: the name of the board, eg. "servo_micro"
+      binfile: path to the binary to search
+
+    Returns:
+      the version string.
+    """
+    if boardname is None:
+        # cannot extract the version if the name is None
+        return None
+    rawstrings = subprocess.check_output(
+        ["cbfstool", binfile, "read", "-r", "RO_FRID", "-f", "/dev/stdout"],
+        **c.get_subprocess_args()
+    )
+    m = re.match(r"%s_v\S+" % boardname, rawstrings)
+    if m:
+        newvers = m.group(0).strip(" \t\r\n\0")
+    else:
+        raise ServoUpdaterException(
+            "Can't find version from file: %s." % binfile
+        )
+
+    return newvers
 
-  return newvers
 
 def get_firmware_channel(bname, version):
-  """Find out which channel |version| for |bname| came from.
-
-  Args:
-    bname: board name
-    version: current version string
-
-  Returns:
-    one of the channel names if |version| came from one of those, or None
-  """
-  for channel in CHANNELS:
-    # Pass |bname| as cname to find the board specific file, and pass None as
-    # fname to ensure the default directory is searched
-    _, _, vers = get_files_and_version(bname, None, channel=channel)
-    if version == vers:
-      return channel
-  # None of the channels matched. This firmware is currently unknown.
-  return None
+    """Find out which channel |version| for |bname| came from.
+
+    Args:
+      bname: board name
+      version: current version string
+
+    Returns:
+      one of the channel names if |version| came from one of those, or None
+    """
+    for channel in CHANNELS:
+        # Pass |bname| as cname to find the board specific file, and pass None as
+        # fname to ensure the default directory is searched
+        _, _, vers = get_files_and_version(bname, None, channel=channel)
+        if version == vers:
+            return channel
+    # None of the channels matched. This firmware is currently unknown.
+    return None
+
 
 def get_files_and_version(cname, fname=None, channel=DEFAULT_CHANNEL):
-  """Select config and firmware binary files.
-
-  This checks default file names and paths.
-  In: /usr/share/servo_updater/[firmware|configs]
-  check for board.json, board.bin
-
-  Args:
-    cname: board name, or config name. eg. "servo_v4" or "servo_v4.json"
-    fname: firmware binary name. Can be None to try default.
-    channel: the channel requested for servo firmware. See |CHANNELS| above.
-
-  Returns:
-    cname, fname, version: validated filenames selected from the path.
-  """
-  for p in (DEFAULT_BASE_PATH, TEST_IMAGE_BASE_PATH):
-    updater_path = os.path.join(p, COMMON_PATH)
-    if os.path.exists(updater_path):
-      break
-  else:
-    raise ServoUpdaterException('servo_updater/ dir not found in known spots.')
-
-  firmware_path = os.path.join(updater_path, FIRMWARE_DIR)
-  configs_path = os.path.join(updater_path, CONFIGS_DIR)
-
-  for p in (firmware_path, configs_path):
-    if not os.path.exists(p):
-      raise ServoUpdaterException('Could not find required path %r' % p)
-
-  if not os.path.isfile(cname):
-    # If not an existing file, try checking on the default path.
-    newname = os.path.join(configs_path, cname)
-    if os.path.isfile(newname):
-      cname = newname
+    """Select config and firmware binary files.
+
+    This checks default file names and paths.
+    In: /usr/share/servo_updater/[firmware|configs]
+    check for board.json, board.bin
+
+    Args:
+      cname: board name, or config name. eg. "servo_v4" or "servo_v4.json"
+      fname: firmware binary name. Can be None to try default.
+      channel: the channel requested for servo firmware. See |CHANNELS| above.
+
+    Returns:
+      cname, fname, version: validated filenames selected from the path.
+    """
+    for p in (DEFAULT_BASE_PATH, TEST_IMAGE_BASE_PATH):
+        updater_path = os.path.join(p, COMMON_PATH)
+        if os.path.exists(updater_path):
+            break
     else:
-      # Try appending ".json" to convert board name to config file.
-      cname = newname + ".json"
+        raise ServoUpdaterException(
+            "servo_updater/ dir not found in known spots."
+        )
+
+    firmware_path = os.path.join(updater_path, FIRMWARE_DIR)
+    configs_path = os.path.join(updater_path, CONFIGS_DIR)
+
+    for p in (firmware_path, configs_path):
+        if not os.path.exists(p):
+            raise ServoUpdaterException("Could not find required path %r" % p)
+
     if not os.path.isfile(cname):
-      raise ServoUpdaterException("Can't find config file: %s." % cname)
-
-  # Always retrieve the boardname
-  with open(cname) as data_file:
-    data = json.load(data_file)
-  boardname = data['board']
-
-  if not fname:
-    # If no |fname| supplied, look for the default locations with the board
-    # and channel requested.
-    binary_file = '%s.%s.bin' % (boardname, channel)
-    newname = os.path.join(firmware_path, binary_file)
-    if os.path.isfile(newname):
-      fname = newname
-    else:
-      raise ServoUpdaterException("Can't find firmware binary: %s." %
-                                  binary_file)
-  elif not os.path.isfile(fname):
-    # If a name is specified but not found, try the default path.
-    newname = os.path.join(firmware_path, fname)
-    if os.path.isfile(newname):
-      fname = newname
+        # If not an existing file, try checking on the default path.
+        newname = os.path.join(configs_path, cname)
+        if os.path.isfile(newname):
+            cname = newname
+        else:
+            # Try appending ".json" to convert board name to config file.
+            cname = newname + ".json"
+        if not os.path.isfile(cname):
+            raise ServoUpdaterException("Can't find config file: %s." % cname)
+
+    # Always retrieve the boardname
+    with open(cname) as data_file:
+        data = json.load(data_file)
+    boardname = data["board"]
+
+    if not fname:
+        # If no |fname| supplied, look for the default locations with the board
+        # and channel requested.
+        binary_file = "%s.%s.bin" % (boardname, channel)
+        newname = os.path.join(firmware_path, binary_file)
+        if os.path.isfile(newname):
+            fname = newname
+        else:
+            raise ServoUpdaterException(
+                "Can't find firmware binary: %s." % binary_file
+            )
+    elif not os.path.isfile(fname):
+        # If a name is specified but not found, try the default path.
+        newname = os.path.join(firmware_path, fname)
+        if os.path.isfile(newname):
+            fname = newname
+        else:
+            raise ServoUpdaterException("Can't find file: %s." % fname)
+
+    # Lastly, retrieve the version as well for decision making, debug, and
+    # informational purposes.
+    binvers = _extract_version(boardname, fname)
+
+    return cname, fname, binvers
+
+
+def main():
+    parser = argparse.ArgumentParser(description="Image a servo device")
+    parser.add_argument(
+        "-p",
+        "--print",
+        dest="print_only",
+        action="store_true",
+        default=False,
+        help="only print available firmware for board/channel",
+    )
+    parser.add_argument(
+        "-s",
+        "--serialno",
+        type=str,
+        help="serial number to program",
+        default=None,
+    )
+    parser.add_argument(
+        "-b",
+        "--board",
+        type=str,
+        help="Board configuration json file",
+        default=DEFAULT_BOARD,
+        choices=BOARDS,
+    )
+    parser.add_argument(
+        "-c",
+        "--channel",
+        type=str,
+        help="Firmware channel to use",
+        default=DEFAULT_CHANNEL,
+        choices=CHANNELS,
+    )
+    parser.add_argument(
+        "-f", "--file", type=str, help="Complete ec.bin file", default=None
+    )
+    parser.add_argument(
+        "--force",
+        action="store_true",
+        help="Update even if version match",
+        default=False,
+    )
+    parser.add_argument(
+        "-v", "--verbose", action="store_true", help="Chatty output"
+    )
+    parser.add_argument(
+        "-r",
+        "--reboot",
+        action="store_true",
+        help="Always reboot, even after probe.",
+    )
+
+    args = parser.parse_args()
+
+    brdfile, binfile, newvers = get_files_and_version(
+        args.board, args.file, args.channel
+    )
+
+    # If the user only cares about the information then just print it here,
+    # and exit.
+    if args.print_only:
+        output = ("board: %s\nchannel: %s\nfirmware: %s") % (
+            args.board,
+            args.channel,
+            newvers,
+        )
+        print(output)
+        return
+
+    serialno = args.serialno
+
+    with open(brdfile) as data_file:
+        data = json.load(data_file)
+    vid, pid = int(data["vid"], 0), int(data["pid"], 0)
+    vidpid = "%04x:%04x" % (vid, pid)
+    iface = int(data["console"], 0)
+    boardname = data["board"]
+
+    # Make sure device is up.
+    print("===== Waiting for USB device =====")
+    c.wait_for_usb(vidpid, serialname=serialno)
+    # We need a tiny_servod to query some information. Set it up first.
+    tinys = tiny_servod.TinyServod(vid, pid, iface, serialno, args.verbose)
+
+    if not args.force:
+        vers = do_version(tinys)
+        print("Current %s version is   %s" % (boardname, vers))
+        print("Available %s version is %s" % (boardname, newvers))
+
+        if newvers == vers:
+            print("No version update needed")
+            if args.reboot:
+                select(tinys, "ro")
+            return
+        else:
+            print("Updating to recommended version.")
+
+    # Make sure the servo MCU is in RO
+    print("===== Jumping to RO =====")
+    do_with_retries(select, tinys, "ro")
+
+    print("===== Flashing RW =====")
+    vers = do_with_retries(do_updater_version, tinys)
+    # To make sure that the tiny_servod here does not interfere with other
+    # processes, close it out.
+    tinys.close()
+
+    if vers == 2:
+        flash(brdfile, serialno, binfile)
+    elif vers == 6:
+        do_with_retries(flash2, vidpid, serialno, binfile)
     else:
-      raise ServoUpdaterException("Can't find file: %s." % fname)
+        raise ServoUpdaterException("Can't detect updater version")
 
-  # Lastly, retrieve the version as well for decision making, debug, and
-  # informational purposes.
-  binvers = _extract_version(boardname, fname)
+    # Make sure device is up.
+    c.wait_for_usb(vidpid, serialname=serialno)
+    # After we have made sure that it's back/available, reconnect the tiny servod.
+    tinys.reinitialize()
 
-  return cname, fname, binvers
+    # Make sure the servo MCU is in RW
+    print("===== Jumping to RW =====")
+    do_with_retries(select, tinys, "rw")
 
-def main():
-  parser = argparse.ArgumentParser(description="Image a servo device")
-  parser.add_argument('-p', '--print', dest='print_only', action='store_true',
-                      default=False,
-                      help='only print available firmware for board/channel')
-  parser.add_argument('-s', '--serialno', type=str,
-                      help="serial number to program", default=None)
-  parser.add_argument('-b', '--board', type=str,
-                      help="Board configuration json file",
-                      default=DEFAULT_BOARD, choices=BOARDS)
-  parser.add_argument('-c', '--channel', type=str,
-                      help="Firmware channel to use",
-                      default=DEFAULT_CHANNEL, choices=CHANNELS)
-  parser.add_argument('-f', '--file', type=str,
-                      help="Complete ec.bin file", default=None)
-  parser.add_argument('--force', action="store_true",
-                      help="Update even if version match", default=False)
-  parser.add_argument('-v', '--verbose', action="store_true",
-                      help="Chatty output")
-  parser.add_argument('-r', '--reboot', action="store_true",
-                      help="Always reboot, even after probe.")
-
-  args = parser.parse_args()
-
-  brdfile, binfile, newvers = get_files_and_version(args.board, args.file,
-                                                    args.channel)
-
-  # If the user only cares about the information then just print it here,
-  # and exit.
-  if args.print_only:
-    output = ('board: %s\n'
-              'channel: %s\n'
-              'firmware: %s') % (args.board, args.channel, newvers)
-    print(output)
-    return
-
-  serialno = args.serialno
-
-  with open(brdfile) as data_file:
-      data = json.load(data_file)
-  vid, pid = int(data['vid'], 0), int(data['pid'], 0)
-  vidpid = "%04x:%04x" % (vid, pid)
-  iface = int(data['console'], 0)
-  boardname = data['board']
-
-  # Make sure device is up.
-  print("===== Waiting for USB device =====")
-  c.wait_for_usb(vidpid, serialname=serialno)
-  # We need a tiny_servod to query some information. Set it up first.
-  tinys = tiny_servod.TinyServod(vid, pid, iface, serialno, args.verbose)
-
-  if not args.force:
-    vers = do_version(tinys)
-    print("Current %s version is   %s" % (boardname, vers))
-    print("Available %s version is %s" % (boardname, newvers))
-
-    if newvers == vers:
-      print("No version update needed")
-      if args.reboot:
-        select(tinys, 'ro')
-      return
+    print("===== Flashing RO =====")
+    vers = do_with_retries(do_updater_version, tinys)
+
+    if vers == 2:
+        flash(brdfile, serialno, binfile)
+    elif vers == 6:
+        do_with_retries(flash2, vidpid, serialno, binfile)
     else:
-      print("Updating to recommended version.")
-
-  # Make sure the servo MCU is in RO
-  print("===== Jumping to RO =====")
-  do_with_retries(select, tinys, 'ro')
-
-  print("===== Flashing RW =====")
-  vers = do_with_retries(do_updater_version, tinys)
-  # To make sure that the tiny_servod here does not interfere with other
-  # processes, close it out.
-  tinys.close()
-
-  if vers == 2:
-    flash(brdfile, serialno, binfile)
-  elif vers == 6:
-    do_with_retries(flash2, vidpid, serialno, binfile)
-  else:
-    raise ServoUpdaterException("Can't detect updater version")
-
-  # Make sure device is up.
-  c.wait_for_usb(vidpid, serialname=serialno)
-  # After we have made sure that it's back/available, reconnect the tiny servod.
-  tinys.reinitialize()
-
-  # Make sure the servo MCU is in RW
-  print("===== Jumping to RW =====")
-  do_with_retries(select, tinys, 'rw')
-
-  print("===== Flashing RO =====")
-  vers = do_with_retries(do_updater_version, tinys)
-
-  if vers == 2:
-    flash(brdfile, serialno, binfile)
-  elif vers == 6:
-    do_with_retries(flash2, vidpid, serialno, binfile)
-  else:
-    raise ServoUpdaterException("Can't detect updater version")
-
-  # Make sure the servo MCU is in RO
-  print("===== Rebooting =====")
-  do_with_retries(select, tinys, 'ro')
-  # Perform additional reboot to free USB/UART resources, taken by tiny servod.
-  # See https://issuetracker.google.com/196021317 for background.
-  tinys.pty._issue_cmd("reboot")
-
-  print("===== Finished =====")
+        raise ServoUpdaterException("Can't detect updater version")
+
+    # Make sure the servo MCU is in RO
+    print("===== Rebooting =====")
+    do_with_retries(select, tinys, "ro")
+    # Perform additional reboot to free USB/UART resources, taken by tiny servod.
+    # See https://issuetracker.google.com/196021317 for background.
+    tinys.pty._issue_cmd("reboot")
+
+    print("===== Finished =====")
+
 
 if __name__ == "__main__":
-  main()
+    main()
diff --git a/extra/usb_updater/usb_updater2.c b/extra/usb_updater/usb_updater2.c
index 81cf48a680..d591811a2b 100644
--- a/extra/usb_updater/usb_updater2.c
+++ b/extra/usb_updater/usb_updater2.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -46,16 +46,16 @@
 #define PROTOCOL USB_PROTOCOL_GOOGLE_UPDATE
 
 enum exit_values {
-	noop = 0,	  /* All up to date, no update needed. */
-	all_updated = 1,  /* Update completed, reboot required. */
-	rw_updated  = 2,  /* RO was not updated, reboot required. */
-	update_error = 3  /* Something went wrong. */
+	noop = 0, /* All up to date, no update needed. */
+	all_updated = 1, /* Update completed, reboot required. */
+	rw_updated = 2, /* RO was not updated, reboot required. */
+	update_error = 3 /* Something went wrong. */
 };
 
 struct usb_endpoint {
 	struct libusb_device_handle *devh;
 	uint8_t ep_num;
-	int     chunk_len;
+	int chunk_len;
 };
 
 struct transfer_descriptor {
@@ -76,22 +76,22 @@ static char *progname;
 static char *short_opts = "bd:efg:hjlnp:rsS:tuw";
 static const struct option long_opts[] = {
 	/* name    hasarg *flag val */
-	{"binvers",	1,   NULL, 'b'},
-	{"device",	1,   NULL, 'd'},
-	{"entropy",	0,   NULL, 'e'},
-	{"fwver",	0,   NULL, 'f'},
-	{"tp_debug",	1,   NULL, 'g'},
-	{"help",	0,   NULL, 'h'},
-	{"jump_to_rw",	0,   NULL, 'j'},
-	{"follow_log",	0,   NULL, 'l'},
-	{"no_reset",	0,   NULL, 'n'},
-	{"tp_update",	1,   NULL, 'p'},
-	{"reboot",	0,   NULL, 'r'},
-	{"stay_in_ro",	0,   NULL, 's'},
-	{"serial",	1,   NULL, 'S'},
-	{"tp_info",	0,   NULL, 't'},
-	{"unlock_rollback",	0,   NULL, 'u'},
-	{"unlock_rw",	0,   NULL, 'w'},
+	{ "binvers", 1, NULL, 'b' },
+	{ "device", 1, NULL, 'd' },
+	{ "entropy", 0, NULL, 'e' },
+	{ "fwver", 0, NULL, 'f' },
+	{ "tp_debug", 1, NULL, 'g' },
+	{ "help", 0, NULL, 'h' },
+	{ "jump_to_rw", 0, NULL, 'j' },
+	{ "follow_log", 0, NULL, 'l' },
+	{ "no_reset", 0, NULL, 'n' },
+	{ "tp_update", 1, NULL, 'p' },
+	{ "reboot", 0, NULL, 'r' },
+	{ "stay_in_ro", 0, NULL, 's' },
+	{ "serial", 1, NULL, 'S' },
+	{ "tp_info", 0, NULL, 't' },
+	{ "unlock_rollback", 0, NULL, 'u' },
+	{ "unlock_rw", 0, NULL, 'w' },
 	{},
 };
 
@@ -113,7 +113,7 @@ static void usage(int errs)
 	       "Options:\n"
 	       "\n"
 	       "  -b,--binvers             Report versions of image's "
-				"RW and RO, do not update\n"
+	       "RW and RO, do not update\n"
 	       "  -d,--device  VID:PID     USB device (default %04x:%04x)\n"
 	       "  -e,--entropy             Add entropy to device secret\n"
 	       "  -f,--fwver               Report running firmware versions.\n"
@@ -128,7 +128,8 @@ static void usage(int errs)
 	       "  -t,--tp_info             Get touchpad information\n"
 	       "  -u,--unlock_rollback     Tell EC to unlock the rollback region\n"
 	       "  -w,--unlock_rw           Tell EC to unlock the RW region\n"
-	       "\n", progname, VID, PID);
+	       "\n",
+	       progname, VID, PID);
 
 	exit(errs ? update_error : noop);
 }
@@ -138,7 +139,7 @@ static void str2hex(const char *str, uint8_t *data, int *len)
 	int i;
 	int slen = strlen(str);
 
-	if (slen/2 > *len) {
+	if (slen / 2 > *len) {
 		fprintf(stderr, "Hex string too long.\n");
 		exit(update_error);
 	}
@@ -153,7 +154,7 @@ static void str2hex(const char *str, uint8_t *data, int *len)
 		char tmp[3];
 
 		tmp[0] = str[i];
-		tmp[1] = str[i+1];
+		tmp[1] = str[i + 1];
 		tmp[2] = 0;
 
 		data[*len] = strtol(tmp, &end, 16);
@@ -250,9 +251,9 @@ static uint8_t *get_file_or_die(const char *filename, size_t *len_ptr)
 	return data;
 }
 
-#define USB_ERROR(m, r) \
-	fprintf(stderr, "%s:%d, %s returned %d (%s)\n", __FILE__, __LINE__, \
-		m, r, libusb_strerror(r))
+#define USB_ERROR(m, r)                                                        \
+	fprintf(stderr, "%s:%d, %s returned %d (%s)\n", __FILE__, __LINE__, m, \
+		r, libusb_strerror(r))
 
 /*
  * Actual USB transfer function, the 'allow_less' flag indicates that the
@@ -261,17 +262,14 @@ static uint8_t *get_file_or_die(const char *filename, size_t *len_ptr)
  * bytes were received.
  */
 static void do_xfer(struct usb_endpoint *uep, void *outbuf, int outlen,
-		    void *inbuf, int inlen, int allow_less,
-		    size_t *rxed_count)
+		    void *inbuf, int inlen, int allow_less, size_t *rxed_count)
 {
-
 	int r, actual;
 
 	/* Send data out */
 	if (outbuf && outlen) {
 		actual = 0;
-		r = libusb_bulk_transfer(uep->devh, uep->ep_num,
-					 outbuf, outlen,
+		r = libusb_bulk_transfer(uep->devh, uep->ep_num, outbuf, outlen,
 					 &actual, 2000);
 		if (r < 0) {
 			USB_ERROR("libusb_bulk_transfer", r);
@@ -286,11 +284,9 @@ static void do_xfer(struct usb_endpoint *uep, void *outbuf, int outlen,
 
 	/* Read reply back */
 	if (inbuf && inlen) {
-
 		actual = 0;
-		r = libusb_bulk_transfer(uep->devh, uep->ep_num | 0x80,
-					 inbuf, inlen,
-					 &actual, 5000);
+		r = libusb_bulk_transfer(uep->devh, uep->ep_num | 0x80, inbuf,
+					 inlen, &actual, 5000);
 		if (r < 0) {
 			USB_ERROR("libusb_bulk_transfer", r);
 			exit(update_error);
@@ -307,8 +303,8 @@ static void do_xfer(struct usb_endpoint *uep, void *outbuf, int outlen,
 	}
 }
 
-static void xfer(struct usb_endpoint *uep, void *outbuf,
-		 size_t outlen, void *inbuf, size_t inlen, int allow_less)
+static void xfer(struct usb_endpoint *uep, void *outbuf, size_t outlen,
+		 void *inbuf, size_t inlen, int allow_less)
 {
 	do_xfer(uep, outbuf, outlen, inbuf, inlen, allow_less, NULL);
 }
@@ -321,8 +317,7 @@ static int find_endpoint(const struct libusb_interface_descriptor *iface,
 
 	if (iface->bInterfaceClass == 255 &&
 	    iface->bInterfaceSubClass == SUBCLASS &&
-	    iface->bInterfaceProtocol == PROTOCOL &&
-	    iface->bNumEndpoints) {
+	    iface->bInterfaceProtocol == PROTOCOL && iface->bNumEndpoints) {
 		ep = &iface->endpoint[0];
 		uep->ep_num = ep->bEndpointAddress & 0x7f;
 		uep->chunk_len = ep->wMaxPacketSize;
@@ -377,19 +372,19 @@ static int parse_vidpid(const char *input, uint16_t *vid_ptr, uint16_t *pid_ptr)
 		return 0;
 	*s++ = '\0';
 
-	*vid_ptr = (uint16_t) strtoull(copy, &e, 16);
+	*vid_ptr = (uint16_t)strtoull(copy, &e, 16);
 	if (!*optarg || (e && *e))
 		return 0;
 
-	*pid_ptr = (uint16_t) strtoull(s, &e, 16);
+	*pid_ptr = (uint16_t)strtoull(s, &e, 16);
 	if (!*optarg || (e && *e))
 		return 0;
 
 	return 1;
 }
 
-static libusb_device_handle *check_device(libusb_device *dev,
-	uint16_t vid, uint16_t pid, char *serialno)
+static libusb_device_handle *check_device(libusb_device *dev, uint16_t vid,
+					  uint16_t pid, char *serialno)
 {
 	struct libusb_device_descriptor desc;
 	libusb_device_handle *handle = NULL;
@@ -409,7 +404,9 @@ static libusb_device_handle *check_device(libusb_device *dev,
 
 	if (desc.iSerialNumber) {
 		ret = libusb_get_string_descriptor_ascii(handle,
-			desc.iSerialNumber, (unsigned char *)sn, sizeof(sn));
+							 desc.iSerialNumber,
+							 (unsigned char *)sn,
+							 sizeof(sn));
 		if (ret > 0)
 			snvalid = 1;
 	}
@@ -428,8 +425,8 @@ static libusb_device_handle *check_device(libusb_device *dev,
 	return NULL;
 }
 
-static void usb_findit(uint16_t vid, uint16_t pid,
-		char *serialno, struct usb_endpoint *uep)
+static void usb_findit(uint16_t vid, uint16_t pid, char *serialno,
+		       struct usb_endpoint *uep)
 {
 	int iface_num, r, i;
 	libusb_device **devs;
@@ -475,8 +472,8 @@ static void usb_findit(uint16_t vid, uint16_t pid,
 		shut_down(uep);
 	}
 
-	printf("found interface %d endpoint %d, chunk_len %d\n",
-	       iface_num, uep->ep_num, uep->chunk_len);
+	printf("found interface %d endpoint %d, chunk_len %d\n", iface_num,
+	       uep->ep_num, uep->chunk_len);
 
 	libusb_set_auto_detach_kernel_driver(uep->devh, 1);
 	r = libusb_claim_interface(uep->devh, iface_num);
@@ -511,9 +508,8 @@ static int transfer_block(struct usb_endpoint *uep,
 	}
 
 	/* Now get the reply. */
-	r = libusb_bulk_transfer(uep->devh, uep->ep_num | 0x80,
-				 (void *) &reply, sizeof(reply),
-				 &actual, 5000);
+	r = libusb_bulk_transfer(uep->devh, uep->ep_num | 0x80, (void *)&reply,
+				 sizeof(reply), &actual, 5000);
 	if (r) {
 		if (r == -7) {
 			fprintf(stderr, "Timeout!\n");
@@ -541,10 +537,8 @@ static int transfer_block(struct usb_endpoint *uep,
  * data_len     - section size
  * smart_update - non-zero to enable the smart trailing of 0xff.
  */
-static void transfer_section(struct transfer_descriptor *td,
-			     uint8_t *data_ptr,
-			     uint32_t section_addr,
-			     size_t data_len,
+static void transfer_section(struct transfer_descriptor *td, uint8_t *data_ptr,
+			     uint32_t section_addr, size_t data_len,
 			     uint8_t smart_update)
 {
 	/*
@@ -571,17 +565,16 @@ static void transfer_section(struct transfer_descriptor *td,
 		struct update_frame_header ufh;
 
 		ufh.block_size = htobe32(payload_size +
-					sizeof(struct update_frame_header));
+					 sizeof(struct update_frame_header));
 		ufh.cmd.block_base = block_base;
 		ufh.cmd.block_digest = 0;
 		for (max_retries = 10; max_retries; max_retries--)
-			if (!transfer_block(&td->uep, &ufh,
-						data_ptr, payload_size))
+			if (!transfer_block(&td->uep, &ufh, data_ptr,
+					    payload_size))
 				break;
 
 		if (!max_retries) {
-			fprintf(stderr,
-				"Failed to transfer block, %zd to go\n",
+			fprintf(stderr, "Failed to transfer block, %zd to go\n",
 				data_len);
 			exit(update_error);
 		}
@@ -596,30 +589,27 @@ static void transfer_section(struct transfer_descriptor *td,
  * states.
  */
 enum upgrade_status {
-	not_needed = 0,  /* Version below or equal that on the target. */
-	not_possible,    /*
-			  * RO is newer, but can't be transferred due to
-			  * target RW shortcomings.
-			  */
-	needed            /*
-			   * This section needs to be transferred to the
-			   * target.
-			   */
+	not_needed = 0, /* Version below or equal that on the target. */
+	not_possible, /*
+		       * RO is newer, but can't be transferred due to
+		       * target RW shortcomings.
+		       */
+	needed /*
+		* This section needs to be transferred to the
+		* target.
+		*/
 };
 
 /* This array describes all sections of the new image. */
 static struct {
 	const char *name;
-	uint32_t    offset;
-	uint32_t    size;
-	enum upgrade_status  ustatus;
+	uint32_t offset;
+	uint32_t size;
+	enum upgrade_status ustatus;
 	char version[32];
 	int32_t rollback;
 	uint32_t key_version;
-} sections[] = {
-	{"RO"},
-	{"RW"}
-};
+} sections[] = { { "RO" }, { "RW" } };
 
 static const struct fmap_area *fmap_find_area_or_die(const struct fmap *fmap,
 						     const char *name)
@@ -650,7 +640,7 @@ static void fetch_header_versions(const uint8_t *image, size_t len)
 		fprintf(stderr, "Cannot find FMAP in image\n");
 		exit(update_error);
 	}
-	fmap = (const struct fmap *)(image+offset);
+	fmap = (const struct fmap *)(image + offset);
 
 	/* FIXME: validate fmap struct more than this? */
 	if (fmap->size != len) {
@@ -693,15 +683,15 @@ static void fetch_header_versions(const uint8_t *image, size_t len)
 			fprintf(stderr, "Invalid fwid size\n");
 			exit(update_error);
 		}
-		memcpy(sections[i].version, image+fmaparea->offset,
-			fmaparea->size);
+		memcpy(sections[i].version, image + fmaparea->offset,
+		       fmaparea->size);
 
 		sections[i].rollback = -1;
 		if (fmap_rollback_name) {
 			fmaparea = fmap_find_area(fmap, fmap_rollback_name);
 			if (fmaparea)
 				memcpy(&sections[i].rollback,
-				       image+fmaparea->offset,
+				       image + fmaparea->offset,
 				       sizeof(sections[i].rollback));
 		}
 
@@ -710,7 +700,8 @@ static void fetch_header_versions(const uint8_t *image, size_t len)
 			fmaparea = fmap_find_area(fmap, fmap_key_name);
 			if (fmaparea) {
 				const struct vb21_packed_key *key =
-					(const void *)(image+fmaparea->offset);
+					(const void *)(image +
+						       fmaparea->offset);
 				sections[i].key_version = key->key_version;
 			}
 		}
@@ -723,9 +714,9 @@ static int show_headers_versions(const void *image)
 
 	for (i = 0; i < ARRAY_SIZE(sections); i++) {
 		printf("%s off=%08x/%08x v=%.32s rb=%d kv=%d\n",
-			sections[i].name, sections[i].offset, sections[i].size,
-			sections[i].version, sections[i].rollback,
-			sections[i].key_version);
+		       sections[i].name, sections[i].offset, sections[i].size,
+		       sections[i].version, sections[i].rollback,
+		       sections[i].key_version);
 	}
 	return 0;
 }
@@ -772,17 +763,16 @@ static void setup_connection(struct transfer_descriptor *td)
 	int actual = 0;
 
 	/* Flush all data from endpoint to recover in case of error. */
-	while (!libusb_bulk_transfer(td->uep.devh,
-					td->uep.ep_num | 0x80,
-					(void *)&inbuf, td->uep.chunk_len,
-					&actual, 10)) {
+	while (!libusb_bulk_transfer(td->uep.devh, td->uep.ep_num | 0x80,
+				     (void *)&inbuf, td->uep.chunk_len, &actual,
+				     10)) {
 		printf("flush\n");
 	}
 
 	memset(&ufh, 0, sizeof(ufh));
 	ufh.block_size = htobe32(sizeof(ufh));
-	do_xfer(&td->uep, &ufh, sizeof(ufh), &start_resp,
-		sizeof(start_resp), 1, &rxed_size);
+	do_xfer(&td->uep, &ufh, sizeof(ufh), &start_resp, sizeof(start_resp), 1,
+		&rxed_size);
 
 	/* We got something. Check for errors in response */
 	if (rxed_size < 8) {
@@ -803,10 +793,9 @@ static void setup_connection(struct transfer_descriptor *td)
 	header_type = be16toh(start_resp.rpdu.header_type);
 
 	printf("target running protocol version %d (type %d)\n",
-		protocol_version, header_type);
+	       protocol_version, header_type);
 	if (header_type != UPDATE_HEADER_TYPE_COMMON) {
-		fprintf(stderr, "Unsupported header type %d\n",
-			header_type);
+		fprintf(stderr, "Unsupported header type %d\n", header_type);
 		exit(update_error);
 	}
 
@@ -820,7 +809,7 @@ static void setup_connection(struct transfer_descriptor *td)
 
 	td->offset = be32toh(start_resp.rpdu.common.offset);
 	memcpy(targ.common.version, start_resp.rpdu.common.version,
-		sizeof(start_resp.rpdu.common.version));
+	       sizeof(start_resp.rpdu.common.version));
 	targ.common.maximum_pdu_size =
 		be32toh(start_resp.rpdu.common.maximum_pdu_size);
 	targ.common.flash_protection =
@@ -845,21 +834,20 @@ static void setup_connection(struct transfer_descriptor *td)
  * if it is - of what maximum size.
  */
 static int ext_cmd_over_usb(struct usb_endpoint *uep, uint16_t subcommand,
-			    void *cmd_body, size_t body_size,
-			    void *resp, size_t *resp_size,
-			    int allow_less)
+			    void *cmd_body, size_t body_size, void *resp,
+			    size_t *resp_size, int allow_less)
 {
 	struct update_frame_header *ufh;
 	uint16_t *frame_ptr;
 	size_t usb_msg_size;
 
-	usb_msg_size = sizeof(struct update_frame_header) +
-		sizeof(subcommand) + body_size;
+	usb_msg_size = sizeof(struct update_frame_header) + sizeof(subcommand) +
+		       body_size;
 
 	ufh = malloc(usb_msg_size);
 	if (!ufh) {
-		printf("%s: failed to allocate %zd bytes\n",
-		       __func__, usb_msg_size);
+		printf("%s: failed to allocate %zd bytes\n", __func__,
+		       usb_msg_size);
 		return -1;
 	}
 
@@ -895,30 +883,28 @@ static void send_done(struct usb_endpoint *uep)
 }
 
 static void send_subcommand(struct transfer_descriptor *td, uint16_t subcommand,
-			    void *cmd_body, size_t body_size,
-			    uint8_t *response, size_t response_size)
+			    void *cmd_body, size_t body_size, uint8_t *response,
+			    size_t response_size)
 {
 	send_done(&td->uep);
 
-	ext_cmd_over_usb(&td->uep, subcommand,
-			cmd_body, body_size,
-			response, &response_size, 0);
+	ext_cmd_over_usb(&td->uep, subcommand, cmd_body, body_size, response,
+			 &response_size, 0);
 	printf("sent command %x, resp %x\n", subcommand, response[0]);
 }
 
 /* Returns number of successfully transmitted image sections. */
-static int transfer_image(struct transfer_descriptor *td,
-			       uint8_t *data, size_t data_len)
+static int transfer_image(struct transfer_descriptor *td, uint8_t *data,
+			  size_t data_len)
 {
 	size_t i;
 	int num_txed_sections = 0;
 
 	for (i = 0; i < ARRAY_SIZE(sections); i++)
 		if (sections[i].ustatus == needed) {
-			transfer_section(td,
-					 data + sections[i].offset,
-					 sections[i].offset,
-					 sections[i].size, 1);
+			transfer_section(td, data + sections[i].offset,
+					 sections[i].offset, sections[i].size,
+					 1);
 			num_txed_sections++;
 		}
 
@@ -968,9 +954,8 @@ static void generate_reset_request(struct transfer_descriptor *td)
 	command_body_size = 0;
 	response_size = 1;
 	subcommand = UPDATE_EXTRA_CMD_IMMEDIATE_RESET;
-	ext_cmd_over_usb(&td->uep, subcommand,
-			command_body, command_body_size,
-			&response, &response_size, 0);
+	ext_cmd_over_usb(&td->uep, subcommand, command_body, command_body_size,
+			 &response, &response_size, 0);
 
 	printf("reboot not triggered\n");
 }
@@ -987,7 +972,7 @@ static void get_random(uint8_t *data, int len)
 	}
 
 	while (i < len) {
-		int ret = fread(data+i, len-i, 1, fp);
+		int ret = fread(data + i, len - i, 1, fp);
 
 		if (ret < 0) {
 			perror("fread");
@@ -1005,7 +990,8 @@ static void read_console(struct transfer_descriptor *td)
 	uint8_t payload[] = { 0x1 };
 	uint8_t response[64];
 	size_t response_size = 64;
-	struct timespec sleep_duration = {  /* 100 ms */
+	struct timespec sleep_duration = {
+		/* 100 ms */
 		.tv_sec = 0,
 		.tv_nsec = 100l * 1000l * 1000l,
 	};
@@ -1015,17 +1001,15 @@ static void read_console(struct transfer_descriptor *td)
 	printf("\n");
 	while (1) {
 		response_size = 1;
-		ext_cmd_over_usb(&td->uep,
-				 UPDATE_EXTRA_CMD_CONSOLE_READ_INIT,
-				 NULL, 0,
-				 response, &response_size, 0);
+		ext_cmd_over_usb(&td->uep, UPDATE_EXTRA_CMD_CONSOLE_READ_INIT,
+				 NULL, 0, response, &response_size, 0);
 
 		while (1) {
 			response_size = 64;
 			ext_cmd_over_usb(&td->uep,
 					 UPDATE_EXTRA_CMD_CONSOLE_READ_NEXT,
-					 payload, sizeof(payload),
-					 response, &response_size, 1);
+					 payload, sizeof(payload), response,
+					 &response_size, 1);
 			if (response[0] == 0)
 				break;
 			/* make sure it's null-terminated. */
@@ -1067,7 +1051,7 @@ int main(int argc, char *argv[])
 	memset(&td, 0, sizeof(td));
 
 	errorcnt = 0;
-	opterr = 0;				/* quiet, you */
+	opterr = 0; /* quiet, you */
 	while ((i = getopt_long(argc, argv, short_opts, long_opts, 0)) != -1) {
 		switch (i) {
 		case 'b':
@@ -1091,8 +1075,8 @@ int main(int argc, char *argv[])
 			extra_command = UPDATE_EXTRA_CMD_TOUCHPAD_DEBUG;
 			/* Maximum length. */
 			extra_command_data_len = 50;
-			str2hex(optarg,
-				extra_command_data, &extra_command_data_len);
+			str2hex(optarg, extra_command_data,
+				&extra_command_data_len);
 			hexdump(extra_command_data, extra_command_data_len);
 			extra_command_answer_len = 64;
 			break;
@@ -1112,8 +1096,8 @@ int main(int argc, char *argv[])
 			touchpad_update = 1;
 
 			data = get_file_or_die(optarg, &data_len);
-			printf("read %zd(%#zx) bytes from %s\n",
-				data_len, data_len, argv[optind - 1]);
+			printf("read %zd(%#zx) bytes from %s\n", data_len,
+			       data_len, argv[optind - 1]);
 
 			break;
 		case 'r':
@@ -1127,8 +1111,7 @@ int main(int argc, char *argv[])
 			break;
 		case 't':
 			extra_command = UPDATE_EXTRA_CMD_TOUCHPAD_INFO;
-			extra_command_answer_len =
-				sizeof(struct touchpad_info);
+			extra_command_answer_len = sizeof(struct touchpad_info);
 			break;
 		case 'u':
 			extra_command = UPDATE_EXTRA_CMD_UNLOCK_ROLLBACK;
@@ -1136,7 +1119,7 @@ int main(int argc, char *argv[])
 		case 'w':
 			extra_command = UPDATE_EXTRA_CMD_UNLOCK_RW;
 			break;
-		case 0:				/* auto-handled option */
+		case 0: /* auto-handled option */
 			break;
 		case '?':
 			if (optopt)
@@ -1167,8 +1150,8 @@ int main(int argc, char *argv[])
 		}
 
 		data = get_file_or_die(argv[optind], &data_len);
-		printf("read %zd(%#zx) bytes from %s\n",
-		       data_len, data_len, argv[optind]);
+		printf("read %zd(%#zx) bytes from %s\n", data_len, data_len,
+		       argv[optind]);
 
 		fetch_header_versions(data, data_len);
 
@@ -1190,16 +1173,13 @@ int main(int argc, char *argv[])
 
 	if (data) {
 		if (touchpad_update) {
-			transfer_section(&td,
-					data,
-					0x80000000,
-					data_len, 0);
+			transfer_section(&td, data, 0x80000000, data_len, 0);
 			free(data);
 
 			send_done(&td.uep);
 		} else {
-			transferred_sections = transfer_image(&td,
-							data, data_len);
+			transferred_sections =
+				transfer_image(&td, data, data_len);
 			free(data);
 
 			if (transferred_sections && !no_reset_request)
@@ -1208,16 +1188,16 @@ int main(int argc, char *argv[])
 	} else if (extra_command == UPDATE_EXTRA_CMD_CONSOLE_READ_INIT) {
 		read_console(&td);
 	} else if (extra_command > -1) {
-		send_subcommand(&td, extra_command,
-				extra_command_data, extra_command_data_len,
-				extra_command_answer, extra_command_answer_len);
+		send_subcommand(&td, extra_command, extra_command_data,
+				extra_command_data_len, extra_command_answer,
+				extra_command_answer_len);
 
 		switch (extra_command) {
 		case UPDATE_EXTRA_CMD_TOUCHPAD_INFO:
 			dump_touchpad_info(extra_command_answer,
 					   extra_command_answer_len);
 			break;
-		case  UPDATE_EXTRA_CMD_TOUCHPAD_DEBUG:
+		case UPDATE_EXTRA_CMD_TOUCHPAD_DEBUG:
 			hexdump(extra_command_answer, extra_command_answer_len);
 			break;
 		}
diff --git a/firmware_builder.py b/firmware_builder.py
index 6b5d094edf..afd3d815c5 100755
--- a/firmware_builder.py
+++ b/firmware_builder.py
@@ -1,6 +1,6 @@
 #!/usr/bin/env python3
 # -*- coding: utf-8 -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 """Build, bundle, or test all of the EC boards.
@@ -16,21 +16,20 @@ import pathlib
 import subprocess
 import sys
 
-# pylint: disable=import-error
-from google.protobuf import json_format
-
 from chromite.api.gen_sdk.chromite.api import firmware_pb2
 
+# pylint: disable=import-error
+from google.protobuf import json_format
 
-DEFAULT_BUNDLE_DIRECTORY = '/tmp/artifact_bundles'
-DEFAULT_BUNDLE_METADATA_FILE = '/tmp/artifact_bundle_metadata'
+DEFAULT_BUNDLE_DIRECTORY = "/tmp/artifact_bundles"
+DEFAULT_BUNDLE_METADATA_FILE = "/tmp/artifact_bundle_metadata"
 
 # The the list of boards whose on-device unit tests we will verify compilation.
 # TODO(b/172501728) On-device unit tests should build for all boards, but
 # they've bit rotted, so we only build the ones that compile.
 BOARDS_UNIT_TEST = [
-    'bloonchipper',
-    'dartmonkey',
+    "bloonchipper",
+    "dartmonkey",
 ]
 
 
@@ -46,67 +45,87 @@ def build(opts):
     """
     metric_list = firmware_pb2.FwBuildMetricList()
 
+    # Run formatting checks on all python files.
+    subprocess.run(
+        ["black", "--check", "."], cwd=os.path.dirname(__file__), check=True
+    )
+    subprocess.run(
+        [
+            "isort",
+            "--settings-file=.isort.cfg",
+            "--check",
+            "--gitignore",
+            "--dont-follow-links",
+            ".",
+        ],
+        cwd=os.path.dirname(__file__),
+        check=True,
+    )
+
     if opts.code_coverage:
         print(
             "When --code-coverage is selected, 'build' is a no-op. "
             "Run 'test' with --code-coverage instead."
         )
-        with open(opts.metrics, 'w') as f:
-            f.write(json_format.MessageToJson(metric_list))
+        with open(opts.metrics, "w") as file:
+            file.write(json_format.MessageToJson(metric_list))
         return
 
-    cmd = ['make', 'buildall_only', f'-j{opts.cpus}']
+    ec_dir = pathlib.Path(__file__).parent
+    subprocess.run([ec_dir / "util" / "check_clang_format.py"], check=True)
+
+    cmd = ["make", "buildall_only", f"-j{opts.cpus}"]
     print(f"# Running {' '.join(cmd)}.")
     subprocess.run(cmd, cwd=os.path.dirname(__file__), check=True)
     ec_dir = os.path.dirname(__file__)
-    build_dir = os.path.join(ec_dir, 'build')
+    build_dir = os.path.join(ec_dir, "build")
     for build_target in sorted(os.listdir(build_dir)):
         metric = metric_list.value.add()
         metric.target_name = build_target
-        metric.platform_name = 'ec'
-        for variant in ['RO', 'RW']:
+        metric.platform_name = "ec"
+        for variant in ["RO", "RW"]:
             memsize_file = (
                 pathlib.Path(build_dir)
                 / build_target
                 / variant
-                / f'ec.{variant}.elf.memsize.txt'
+                / f"ec.{variant}.elf.memsize.txt"
             )
             if memsize_file.exists():
                 parse_memsize(memsize_file, metric, variant)
-    with open(opts.metrics, 'w') as f:
-        f.write(json_format.MessageToJson(metric_list))
+    with open(opts.metrics, "w") as file:
+        file.write(json_format.MessageToJson(metric_list))
 
     # Ensure that there are no regressions for boards that build successfully
     # with clang: b/172020503.
-    cmd = ['./util/build_with_clang.py']
+    cmd = ["./util/build_with_clang.py"]
     print(f'# Running {" ".join(cmd)}.')
-    subprocess.run(cmd,
-                   cwd=os.path.dirname(__file__),
-                   check=True)
+    subprocess.run(cmd, cwd=os.path.dirname(__file__), check=True)
 
 
 UNITS = {
-    'B': 1,
-    'KB': 1024,
-    'MB': 1024 * 1024,
-    'GB': 1024 * 1024 * 1024,
+    "B": 1,
+    "KB": 1024,
+    "MB": 1024 * 1024,
+    "GB": 1024 * 1024 * 1024,
 }
 
 
 def parse_memsize(filename, metric, variant):
-    with open(filename, 'r') as infile:
+    """Parse the output of the build to extract the image size."""
+    with open(filename, "r") as infile:
         # Skip header line
         infile.readline()
         for line in infile.readlines():
             parts = line.split()
             fw_section = metric.fw_section.add()
-            fw_section.region = variant + '_' + parts[0][:-1]
+            fw_section.region = variant + "_" + parts[0][:-1]
             fw_section.used = int(parts[1]) * UNITS[parts[2]]
             fw_section.total = int(parts[3]) * UNITS[parts[4]]
             fw_section.track_on_gerrit = False
 
 
 def bundle(opts):
+    """Bundle the artifacts."""
     if opts.code_coverage:
         bundle_coverage(opts)
     else:
@@ -132,8 +151,8 @@ def write_metadata(opts, info):
     bundle_metadata_file = (
         opts.metadata if opts.metadata else DEFAULT_BUNDLE_METADATA_FILE
     )
-    with open(bundle_metadata_file, 'w') as f:
-        f.write(json_format.MessageToJson(info))
+    with open(bundle_metadata_file, "w") as file:
+        file.write(json_format.MessageToJson(info))
 
 
 def bundle_coverage(opts):
@@ -142,10 +161,10 @@ def bundle_coverage(opts):
     info.bcs_version_info.version_string = opts.bcs_version
     bundle_dir = get_bundle_dir(opts)
     ec_dir = os.path.dirname(__file__)
-    tarball_name = 'coverage.tbz2'
+    tarball_name = "coverage.tbz2"
     tarball_path = os.path.join(bundle_dir, tarball_name)
-    cmd = ['tar', 'cvfj', tarball_path, 'lcov.info']
-    subprocess.run(cmd, cwd=os.path.join(ec_dir, 'build/coverage'), check=True)
+    cmd = ["tar", "cvfj", tarball_path, "lcov.info"]
+    subprocess.run(cmd, cwd=os.path.join(ec_dir, "build/coverage"), check=True)
     meta = info.objects.add()
     meta.file_name = tarball_name
     meta.lcov_info.type = (
@@ -161,16 +180,20 @@ def bundle_firmware(opts):
     info.bcs_version_info.version_string = opts.bcs_version
     bundle_dir = get_bundle_dir(opts)
     ec_dir = os.path.dirname(__file__)
-    for build_target in sorted(os.listdir(os.path.join(ec_dir, 'build'))):
-        tarball_name = ''.join([build_target, '.firmware.tbz2'])
+    for build_target in sorted(os.listdir(os.path.join(ec_dir, "build"))):
+        tarball_name = "".join([build_target, ".firmware.tbz2"])
         tarball_path = os.path.join(bundle_dir, tarball_name)
         cmd = [
-            'tar', 'cvfj', tarball_path,
-            '--exclude=*.o.d', '--exclude=*.o', '.',
+            "tar",
+            "cvfj",
+            tarball_path,
+            "--exclude=*.o.d",
+            "--exclude=*.o",
+            ".",
         ]
         subprocess.run(
             cmd,
-            cwd=os.path.join(ec_dir, 'build', build_target),
+            cwd=os.path.join(ec_dir, "build", build_target),
             check=True,
         )
         meta = info.objects.add()
@@ -188,8 +211,21 @@ def test(opts):
     """Runs all of the unit tests for EC firmware"""
     # TODO(b/169178847): Add appropriate metric information
     metrics = firmware_pb2.FwTestMetricList()
-    with open(opts.metrics, 'w') as f:
-        f.write(json_format.MessageToJson(metrics))
+    with open(opts.metrics, "w") as file:
+        file.write(json_format.MessageToJson(metrics))
+
+    # Run python unit tests.
+    subprocess.run(
+        ["util/ec3po/run_tests.sh"], cwd=os.path.dirname(__file__), check=True
+    )
+    subprocess.run(
+        ["extra/stack_analyzer/run_tests.sh"],
+        cwd=os.path.dirname(__file__),
+        check=True,
+    )
+    subprocess.run(
+        ["util/run_tests.sh"], cwd=os.path.dirname(__file__), check=True
+    )
 
     # If building for code coverage, build the 'coverage' target, which
     # builds the posix-based unit tests for code coverage and assembles
@@ -197,8 +233,8 @@ def test(opts):
     #
     # Otherwise, build the 'runtests' target, which verifies all
     # posix-based unit tests build and pass.
-    target = 'coverage' if opts.code_coverage else 'runtests'
-    cmd = ['make', target, f'-j{opts.cpus}']
+    target = "coverage" if opts.code_coverage else "runtests"
+    cmd = ["make", target, f"-j{opts.cpus}"]
     print(f"# Running {' '.join(cmd)}.")
     subprocess.run(cmd, cwd=os.path.dirname(__file__), check=True)
 
@@ -206,13 +242,13 @@ def test(opts):
         # Verify compilation of the on-device unit test binaries.
         # TODO(b/172501728) These should build  for all boards, but they've bit
         # rotted, so we only build the ones that compile.
-        cmd = ['make', f'-j{opts.cpus}']
-        cmd.extend(['tests-' + b for b in BOARDS_UNIT_TEST])
+        cmd = ["make", f"-j{opts.cpus}"]
+        cmd.extend(["tests-" + b for b in BOARDS_UNIT_TEST])
         print(f"# Running {' '.join(cmd)}.")
         subprocess.run(cmd, cwd=os.path.dirname(__file__), check=True)
 
         # Verify the tests pass with ASan also
-        cmd = ['make', 'TEST_ASAN=y', target, f'-j{opts.cpus}']
+        cmd = ["make", "TEST_ASAN=y", target, f"-j{opts.cpus}"]
         print(f"# Running {' '.join(cmd)}.")
         subprocess.run(cmd, cwd=os.path.dirname(__file__), check=True)
 
@@ -224,8 +260,8 @@ def main(args):
     """
     opts = parse_args(args)
 
-    if not hasattr(opts, 'func'):
-        print('Must select a valid sub command!')
+    if not hasattr(opts, "func"):
+        print("Must select a valid sub command!")
         return -1
 
     # Run selected sub command function
@@ -238,69 +274,67 @@ def main(args):
 
 
 def parse_args(args):
+    """Parse all command line args and return opts dict."""
     parser = argparse.ArgumentParser(description=__doc__)
 
     parser.add_argument(
-        '--cpus',
+        "--cpus",
         default=multiprocessing.cpu_count(),
-        help='The number of cores to use.',
+        help="The number of cores to use.",
     )
 
     parser.add_argument(
-        '--metrics',
-        dest='metrics',
+        "--metrics",
+        dest="metrics",
         required=True,
-        help='File to write the json-encoded MetricsList proto message.',
+        help="File to write the json-encoded MetricsList proto message.",
     )
 
     parser.add_argument(
-        '--metadata',
+        "--metadata",
         required=False,
-        help='Full pathname for the file in which to write build artifact '
-        'metadata.',
+        help="Full pathname for the file in which to write build artifact metadata.",
     )
 
     parser.add_argument(
-        '--output-dir',
+        "--output-dir",
         required=False,
-        help='Full pathanme for the directory in which to bundle build '
-        'artifacts.',
+        help="Full pathanme for the directory in which to bundle build artifacts.",
     )
 
     parser.add_argument(
-        '--code-coverage',
+        "--code-coverage",
         required=False,
-        action='store_true',
-        help='Build host-based unit tests for code coverage.',
+        action="store_true",
+        help="Build host-based unit tests for code coverage.",
     )
 
     parser.add_argument(
-        '--bcs-version',
-        dest='bcs_version',
-        default='',
+        "--bcs-version",
+        dest="bcs_version",
+        default="",
         required=False,
         # TODO(b/180008931): make this required=True.
-        help='BCS version to include in metadata.',
+        help="BCS version to include in metadata.",
     )
 
     # Would make this required=True, but not available until 3.7
     sub_cmds = parser.add_subparsers()
 
-    build_cmd = sub_cmds.add_parser('build', help='Builds all firmware targets')
+    build_cmd = sub_cmds.add_parser("build", help="Builds all firmware targets")
     build_cmd.set_defaults(func=build)
 
     build_cmd = sub_cmds.add_parser(
-        'bundle',
-        help='Creates a tarball containing build '
-        'artifacts from all firmware targets',
+        "bundle",
+        help="Creates a tarball containing build artifacts from all firmware targets",
     )
     build_cmd.set_defaults(func=bundle)
 
-    test_cmd = sub_cmds.add_parser('test', help='Runs all firmware unit tests')
+    test_cmd = sub_cmds.add_parser("test", help="Runs all firmware unit tests")
     test_cmd.set_defaults(func=test)
 
     return parser.parse_args(args)
 
 
-if __name__ == '__main__':
+if __name__ == "__main__":
     sys.exit(main(sys.argv[1:]))
diff --git a/fuzz/build.mk b/fuzz/build.mk
index ebb5a3a839..bc79df71e6 100644
--- a/fuzz/build.mk
+++ b/fuzz/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/fuzz/fuzz_config.h b/fuzz/fuzz_config.h
index fb974ea727..006919d314 100644
--- a/fuzz/fuzz_config.h
+++ b/fuzz/fuzz_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -90,11 +90,11 @@
 #define CONFIG_MKBP_EVENT
 #define CONFIG_MKBP_USE_GPIO
 #define CONFIG_PERIPHERAL_CHARGER
-#define I2C_PORT_WLC		0
-#define GPIO_WLC_IRQ_CONN	1
-#define GPIO_WLC_NRST_CONN	2
+#define I2C_PORT_WLC 0
+#define GPIO_WLC_IRQ_CONN 1
+#define GPIO_WLC_NRST_CONN 2
 #define GPIO_PCHG_P0 GPIO_WLC_IRQ_CONN
-#endif  /* TEST_PCHG_FUZZ */
+#endif /* TEST_PCHG_FUZZ */
 
-#endif  /* TEST_FUZZ */
-#endif  /* __FUZZ_FUZZ_CONFIG_H */
+#endif /* TEST_FUZZ */
+#endif /* __FUZZ_FUZZ_CONFIG_H */
diff --git a/fuzz/host_command_fuzz.c b/fuzz/host_command_fuzz.c
index 4e30a5e8c1..0a648f602c 100644
--- a/fuzz/host_command_fuzz.c
+++ b/fuzz/host_command_fuzz.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,10 +8,12 @@
 #include <pthread.h>
 #include <sys/time.h>
 
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
 #include "host_command.h"
 #include "host_test.h"
+#include "printf.h"
 #include "task.h"
 #include "test_util.h"
 #include "timer.h"
@@ -75,7 +77,7 @@ static int hostcmd_fill(const uint8_t *data, size_t size)
 	chunks[2].start = chunks[1].start + chunks[1].size + data_len_size;
 	chunks[2].size = sizeof(req_buf) - chunks[2].start;
 #else
-	struct chunk chunks[1] = { {0, sizeof(req_buf)} };
+	struct chunk chunks[1] = { { 0, sizeof(req_buf) } };
 #endif
 
 	/*
@@ -89,7 +91,7 @@ static int hostcmd_fill(const uint8_t *data, size_t size)
 	 * over checksum and data_len.
 	 */
 	for (i = 0; i < ARRAY_SIZE(chunks) && ipos < size; i++) {
-		int cp_size = MIN(chunks[i].size, size-ipos);
+		int cp_size = MIN(chunks[i].size, size - ipos);
 
 		memcpy(req_buf + chunks[i].start, data + ipos, cp_size);
 
@@ -112,8 +114,11 @@ static int hostcmd_fill(const uint8_t *data, size_t size)
 	 * issues.
 	 */
 	if (first) {
-		ccprintf("Request: cmd=%04x data=%ph\n",
-			req->command, HEX_BUF(req_buf, req_size));
+		char str_buf[hex_str_buf_size(req_size)];
+
+		snprintf_hex_buffer(str_buf, sizeof(str_buf),
+				    HEX_BUF(req_buf, req_size));
+		ccprintf("Request: cmd=%04x data=%s\n", req->command, str_buf);
 		first = 0;
 	}
 
@@ -130,7 +135,7 @@ static int hostcmd_fill(const uint8_t *data, size_t size)
 static pthread_cond_t done_cond;
 static pthread_mutex_t lock;
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	ccprints("Fuzzing task started");
 	wait_for_task_started();
diff --git a/fuzz/host_command_fuzz.mocklist b/fuzz/host_command_fuzz.mocklist
index 4ffc786b32..3b7d03ee0e 100644
--- a/fuzz/host_command_fuzz.mocklist
+++ b/fuzz/host_command_fuzz.mocklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/fuzz/host_command_fuzz.tasklist b/fuzz/host_command_fuzz.tasklist
index 2ff8a94d98..1edc0ce0cb 100644
--- a/fuzz/host_command_fuzz.tasklist
+++ b/fuzz/host_command_fuzz.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/fuzz/pchg_fuzz.c b/fuzz/pchg_fuzz.c
index 97dbca74c4..4ef5f28b74 100644
--- a/fuzz/pchg_fuzz.c
+++ b/fuzz/pchg_fuzz.c
@@ -1,11 +1,10 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Test peripheral device charger module.
  */
 
-#define HIDE_EC_STDLIB
 #include "common.h"
 #include "compile_time_macros.h"
 #include "driver/nfc/ctn730.h"
@@ -40,15 +39,15 @@ static pthread_cond_t done_cond;
 static pthread_mutex_t lock;
 
 #define MAX_MESSAGES 8
-#define MAX_MESSAGE_SIZE (sizeof(struct ctn730_msg) \
-			  + member_size(struct ctn730_msg, length) * 256)
+#define MAX_MESSAGE_SIZE             \
+	(sizeof(struct ctn730_msg) + \
+	 member_size(struct ctn730_msg, length) * 256)
 static uint8_t input[MAX_MESSAGE_SIZE * MAX_MESSAGES];
 static uint8_t *head, *tail;
 static bool data_available;
 
-int pchg_i2c_xfer(int port, uint16_t addr_flags,
-		  const uint8_t *out, int out_size,
-		  uint8_t *in, int in_size, int flags)
+int pchg_i2c_xfer(int port, uint16_t addr_flags, const uint8_t *out,
+		  int out_size, uint8_t *in, int in_size, int flags)
 {
 	if (port != I2C_PORT_WLC || addr_flags != CTN730_I2C_ADDR)
 		return EC_ERROR_INVAL;
@@ -92,10 +91,9 @@ void irq_task(int argc, char **argv)
 		pthread_cond_signal(&done_cond);
 		pthread_mutex_unlock(&lock);
 	}
-
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	ccprints("Fuzzing task started");
 	task_wait_event(-1);
diff --git a/fuzz/pchg_fuzz.tasklist b/fuzz/pchg_fuzz.tasklist
index 5b30e09245..7c57f19854 100644
--- a/fuzz/pchg_fuzz.tasklist
+++ b/fuzz/pchg_fuzz.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/fuzz/span.h b/fuzz/span.h
index 531df832a3..9cb08f9461 100644
--- a/fuzz/span.h
+++ b/fuzz/span.h
@@ -1,4 +1,4 @@
-// Copyright 2018 The Chromium OS Authors. All rights reserved.
+// Copyright 2018 The ChromiumOS Authors
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
@@ -9,48 +9,76 @@
 
 #include <algorithm>
 
-namespace fuzz {
+namespace fuzz
+{
 
-template <typename T>
-class span {
- public:
-  typedef T value_type;
+template <typename T> class span {
+    public:
+	typedef T value_type;
 
-  constexpr span() : span<T>(nullptr, nullptr) {}
-  constexpr span(T* begin, size_t size) : begin_(begin), end_(begin + size) {}
-  constexpr span(T* begin, T* end) : begin_(begin), end_(end) {}
+	constexpr span()
+		: span<T>(nullptr, nullptr)
+	{
+	}
+	constexpr span(T *begin, size_t size)
+		: begin_(begin)
+		, end_(begin + size)
+	{
+	}
+	constexpr span(T *begin, T *end)
+		: begin_(begin)
+		, end_(end)
+	{
+	}
 
-  template <class Container>
-  constexpr span(Container& container)
-      : begin_(container.begin()), end_(container.end()){};
+	template <class Container>
+	constexpr span(Container &container)
+		: begin_(container.begin())
+		, end_(container.end()){};
 
-  constexpr T* begin() const { return begin_; }
-  constexpr T* end() const { return end_; }
+	constexpr T *begin() const
+	{
+		return begin_;
+	}
+	constexpr T *end() const
+	{
+		return end_;
+	}
 
-  constexpr T* data() const { return begin_; }
+	constexpr T *data() const
+	{
+		return begin_;
+	}
 
-  constexpr bool empty() const { return begin_ == end_; }
-  constexpr size_t size() const { return end_ - begin_; }
+	constexpr bool empty() const
+	{
+		return begin_ == end_;
+	}
+	constexpr size_t size() const
+	{
+		return end_ - begin_;
+	}
 
- private:
-  T* begin_;
-  T* end_;
+    private:
+	T *begin_;
+	T *end_;
 };
 
 template <typename Source, typename Destination>
-size_t CopyWithPadding(Source source,
-                       Destination destination,
-                       typename Destination::value_type fill_value) {
-  if (source.size() >= destination.size()) {
-    std::copy(source.begin(), source.begin() + destination.size(),
-              destination.begin());
-    return destination.size();
-  }
-  std::copy(source.begin(), source.end(), destination.begin());
-  std::fill(destination.begin() + source.size(), destination.end(), fill_value);
-  return source.size();
+size_t CopyWithPadding(Source source, Destination destination,
+		       typename Destination::value_type fill_value)
+{
+	if (source.size() >= destination.size()) {
+		std::copy(source.begin(), source.begin() + destination.size(),
+			  destination.begin());
+		return destination.size();
+	}
+	std::copy(source.begin(), source.end(), destination.begin());
+	std::fill(destination.begin() + source.size(), destination.end(),
+		  fill_value);
+	return source.size();
 }
 
-}  // namespace fuzz
+} // namespace fuzz
 
-#endif  // __FUZZ_SPAN_H
+#endif // __FUZZ_SPAN_H
diff --git a/fuzz/usb_pd_fuzz.c b/fuzz/usb_pd_fuzz.c
index 64eb0913a6..bb462b9e61 100644
--- a/fuzz/usb_pd_fuzz.c
+++ b/fuzz/usb_pd_fuzz.c
@@ -1,10 +1,9 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Test USB PD module.
  */
-#define HIDE_EC_STDLIB
 #include "common.h"
 #include "task.h"
 #include "tcpm/tcpm.h"
@@ -20,17 +19,26 @@
 
 #define TASK_EVENT_FUZZ TASK_EVENT_CUSTOM_BIT(0)
 
-#define PORT0	0
+#define PORT0 0
 
-static int mock_tcpm_init(int port) { return EC_SUCCESS; }
-static int mock_tcpm_release(int port) { return EC_SUCCESS; }
+static int mock_tcpm_init(int port)
+{
+	return EC_SUCCESS;
+}
+static int mock_tcpm_release(int port)
+{
+	return EC_SUCCESS;
+}
 
 static int mock_tcpm_select_rp_value(int port, int rp)
 {
 	return EC_SUCCESS;
 }
 
-static int mock_tcpm_set_cc(int port, int pull) { return EC_SUCCESS; }
+static int mock_tcpm_set_cc(int port, int pull)
+{
+	return EC_SUCCESS;
+}
 static int mock_tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity)
 {
 	return EC_SUCCESS;
@@ -41,16 +49,28 @@ static __maybe_unused int mock_tcpm_sop_prime_enable(int port, bool enable)
 	return EC_SUCCESS;
 }
 
-static int mock_tcpm_set_vconn(int port, int enable) { return EC_SUCCESS; }
-static int mock_tcpm_set_msg_header(int port,
-			int power_role, int data_role) { return EC_SUCCESS; }
-static int mock_tcpm_set_rx_enable(int port, int enable) { return EC_SUCCESS; }
+static int mock_tcpm_set_vconn(int port, int enable)
+{
+	return EC_SUCCESS;
+}
+static int mock_tcpm_set_msg_header(int port, int power_role, int data_role)
+{
+	return EC_SUCCESS;
+}
+static int mock_tcpm_set_rx_enable(int port, int enable)
+{
+	return EC_SUCCESS;
+}
 static int mock_tcpm_transmit(int port, enum tcpci_msg_type type,
-		uint16_t header, const uint32_t *data)
-{ return EC_SUCCESS; }
-static void mock_tcpc_alert(int port) {}
+			      uint16_t header, const uint32_t *data)
+{
+	return EC_SUCCESS;
+}
+static void mock_tcpc_alert(int port)
+{
+}
 static int mock_tcpci_get_chip_info(int port, int live,
-		struct ec_response_pd_chip_info_v1 *info)
+				    struct ec_response_pd_chip_info_v1 *info)
 {
 	return EC_ERROR_UNIMPLEMENTED;
 }
@@ -76,7 +96,7 @@ struct tcpc_state {
 static struct tcpc_state mock_tcpc_state[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 static int mock_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2)
+			    enum tcpc_cc_voltage_status *cc2)
 {
 	*cc1 = mock_tcpc_state[port].cc1;
 	*cc2 = mock_tcpc_state[port].cc2;
@@ -125,31 +145,33 @@ int tcpm_enqueue_message(const int port)
 	return EC_SUCCESS;
 }
 
-void tcpm_clear_pending_messages(int port) {}
+void tcpm_clear_pending_messages(int port)
+{
+}
 
 static const struct tcpm_drv mock_tcpm_drv = {
-	.init                   = &mock_tcpm_init,
-	.release                = &mock_tcpm_release,
-	.get_cc                 = &mock_tcpm_get_cc,
+	.init = &mock_tcpm_init,
+	.release = &mock_tcpm_release,
+	.get_cc = &mock_tcpm_get_cc,
 #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC
-	.check_vbus_level       = &mock_tcpm_check_vbus_level,
+	.check_vbus_level = &mock_tcpm_check_vbus_level,
 #endif
-	.select_rp_value        = &mock_tcpm_select_rp_value,
-	.set_cc                 = &mock_tcpm_set_cc,
-	.set_polarity           = &mock_tcpm_set_polarity,
+	.select_rp_value = &mock_tcpm_select_rp_value,
+	.set_cc = &mock_tcpm_set_cc,
+	.set_polarity = &mock_tcpm_set_polarity,
 #ifdef CONFIG_USB_PD_DECODE_SOP
-	.sop_prime_enable		= &mock_tcpm_sop_prime_enable,
+	.sop_prime_enable = &mock_tcpm_sop_prime_enable,
 #endif
-	.set_vconn              = &mock_tcpm_set_vconn,
-	.set_msg_header         = &mock_tcpm_set_msg_header,
-	.set_rx_enable          = &mock_tcpm_set_rx_enable,
+	.set_vconn = &mock_tcpm_set_vconn,
+	.set_msg_header = &mock_tcpm_set_msg_header,
+	.set_rx_enable = &mock_tcpm_set_rx_enable,
 	/* The core calls tcpm_dequeue_message. */
-	.get_message_raw        = NULL,
-	.transmit               = &mock_tcpm_transmit,
-	.tcpc_alert             = &mock_tcpc_alert,
-	.get_chip_info          = &mock_tcpci_get_chip_info,
+	.get_message_raw = NULL,
+	.transmit = &mock_tcpm_transmit,
+	.tcpc_alert = &mock_tcpc_alert,
+	.get_chip_info = &mock_tcpci_get_chip_info,
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-	.enter_low_power_mode   = &mock_enter_low_power_mode,
+	.enter_low_power_mode = &mock_enter_low_power_mode,
 #endif
 };
 
@@ -170,7 +192,7 @@ enum tcpc_cc_voltage_status next_cc1, next_cc2;
 #define MAX_MESSAGES 8
 static struct message messages[MAX_MESSAGES];
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	uint8_t port = PORT0;
 	int i;
@@ -181,8 +203,8 @@ void run_test(int argc, char **argv)
 	while (1) {
 		task_wait_event_mask(TASK_EVENT_FUZZ, -1);
 
-		memset(&mock_tcpc_state[port],
-			0, sizeof(mock_tcpc_state[port]));
+		memset(&mock_tcpc_state[port], 0,
+		       sizeof(mock_tcpc_state[port]));
 
 		task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_TCPC_RESET);
 		task_wait_event(250 * MSEC);
@@ -196,7 +218,7 @@ void run_test(int argc, char **argv)
 		/* Fake RX messages, one by one. */
 		for (i = 0; i < MAX_MESSAGES && messages[i].cnt; i++) {
 			memcpy(&mock_tcpc_state[port].message, &messages[i],
-				sizeof(messages[i]));
+			       sizeof(messages[i]));
 
 			tcpm_enqueue_message(port);
 			task_wait_event(50 * MSEC);
@@ -220,21 +242,23 @@ int test_fuzz_one_input(const uint8_t *data, unsigned int size)
 
 	next_cc1 = data[0] & 0x0f;
 	next_cc2 = (data[0] & 0xf0) >> 4;
-	data++; size--;
+	data++;
+	size--;
 
 	memset(messages, 0, sizeof(messages));
 
 	for (i = 0; i < MAX_MESSAGES && size > 0; i++) {
 		int cnt = data[0];
 
-		if (cnt < 3 || cnt > MAX_TCPC_PAYLOAD+3 || cnt > size) {
+		if (cnt < 3 || cnt > MAX_TCPC_PAYLOAD + 3 || cnt > size) {
 			/* Invalid count, or out of bounds. */
 			return 0;
 		}
 
 		memcpy(&messages[i], data, cnt);
 
-		data += cnt; size -= cnt;
+		data += cnt;
+		size -= cnt;
 	}
 
 	if (size != 0) {
diff --git a/fuzz/usb_pd_fuzz.tasklist b/fuzz/usb_pd_fuzz.tasklist
index 6edeac2f98..c006f00784 100644
--- a/fuzz/usb_pd_fuzz.tasklist
+++ b/fuzz/usb_pd_fuzz.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/fuzz/usb_tcpm_v2_rev20_fuzz.c b/fuzz/usb_tcpm_v2_rev20_fuzz.c
index 2f0129464a..c4f57432ad 100644
--- a/fuzz/usb_tcpm_v2_rev20_fuzz.c
+++ b/fuzz/usb_tcpm_v2_rev20_fuzz.c
@@ -1,11 +1,10 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Stubs needed for fuzz testing the USB TCPMv2 state machines.
  */
 
-#define HIDE_EC_STDLIB
 #include "charge_manager.h"
 #include "mock/usb_mux_mock.h"
 #include "usb_pd.h"
@@ -17,12 +16,18 @@ const struct svdm_response svdm_rsp = {
 };
 
 /* USB mux configuration */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.driver = &mock_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.driver = &mock_usb_mux_driver,
+			},
 	},
 	{
-		.driver = &mock_usb_mux_driver,
+		.mux =
+			&(const struct usb_mux){
+				.driver = &mock_usb_mux_driver,
+			},
 	}
 };
 
diff --git a/fuzz/usb_tcpm_v2_rev20_fuzz.mocklist b/fuzz/usb_tcpm_v2_rev20_fuzz.mocklist
index 1b2c615371..fe2a3f8f38 100644
--- a/fuzz/usb_tcpm_v2_rev20_fuzz.mocklist
+++ b/fuzz/usb_tcpm_v2_rev20_fuzz.mocklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/fuzz/usb_tcpm_v2_rev20_fuzz.tasklist b/fuzz/usb_tcpm_v2_rev20_fuzz.tasklist
index e3ad19e719..d20bba1365 100644
--- a/fuzz/usb_tcpm_v2_rev20_fuzz.tasklist
+++ b/fuzz/usb_tcpm_v2_rev20_fuzz.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/2id.h b/include/2id.h
index 8daa4d27db..8d05f96e56 100644
--- a/include/2id.h
+++ b/include/2id.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -25,8 +25,23 @@ struct vb2_id {
 #define EXPECTED_ID_SIZE VB2_ID_NUM_BYTES
 
 /* IDs to use for "keys" with sig_alg==VB2_SIG_NONE */
-#define VB2_ID_NONE_SHA1   {{0x00, 0x01,}}
-#define VB2_ID_NONE_SHA256 {{0x02, 0x56,}}
-#define VB2_ID_NONE_SHA512 {{0x05, 0x12,}}
+#define VB2_ID_NONE_SHA1            \
+	{                           \
+		{                   \
+			0x00, 0x01, \
+		}                   \
+	}
+#define VB2_ID_NONE_SHA256          \
+	{                           \
+		{                   \
+			0x02, 0x56, \
+		}                   \
+	}
+#define VB2_ID_NONE_SHA512          \
+	{                           \
+		{                   \
+			0x05, 0x12, \
+		}                   \
+	}
 
-#endif  /* VBOOT_REFERENCE_VBOOT_2ID_H_ */
+#endif /* VBOOT_REFERENCE_VBOOT_2ID_H_ */
diff --git a/include/accel_cal.h b/include/accel_cal.h
index 80f0161a04..2f7b5d6bbf 100644
--- a/include/accel_cal.h
+++ b/include/accel_cal.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/accelgyro.h b/include/accelgyro.h
index be6b8061c3..74824b2611 100644
--- a/include/accelgyro.h
+++ b/include/accelgyro.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -60,9 +60,7 @@ struct accelgyro_drv {
 	 *
 	 * @return EC_SUCCESS if successful, non-zero if error.
 	 */
-	int (*set_range)(struct motion_sensor_t *s,
-			int range,
-			int rnd);
+	int (*set_range)(struct motion_sensor_t *s, int range, int rnd);
 
 	/**
 	 * Setter and getter methods for the sensor resolution.
@@ -72,9 +70,8 @@ struct accelgyro_drv {
 	 * value. Otherwise, it rounds down.
 	 * @return EC_SUCCESS if successful, non-zero if error.
 	 */
-	int (*set_resolution)(const struct motion_sensor_t *s,
-				int res,
-				int rnd);
+	int (*set_resolution)(const struct motion_sensor_t *s, int res,
+			      int rnd);
 	int (*get_resolution)(const struct motion_sensor_t *s);
 
 	/**
@@ -86,12 +83,10 @@ struct accelgyro_drv {
 	 * value. Otherwise, it rounds down.
 	 * @return EC_SUCCESS if successful, non-zero if error.
 	 */
-	int (*set_data_rate)(const struct motion_sensor_t *s,
-				int rate,
-				int rnd);
+	int (*set_data_rate)(const struct motion_sensor_t *s, int rate,
+			     int rnd);
 	int (*get_data_rate)(const struct motion_sensor_t *s);
 
-
 	/**
 	 * Setter and getter methods for the sensor offset.
 	 * @s Pointer to sensor data.
@@ -100,11 +95,9 @@ struct accelgyro_drv {
 	 * @return EC_SUCCESS if successful, non-zero if error.
 	 */
 	int (*set_offset)(const struct motion_sensor_t *s,
-				const int16_t    *offset,
-				int16_t    temp);
-	int (*get_offset)(const struct motion_sensor_t *s,
-				int16_t    *offset,
-				int16_t    *temp);
+			  const int16_t *offset, int16_t temp);
+	int (*get_offset)(const struct motion_sensor_t *s, int16_t *offset,
+			  int16_t *temp);
 	/**
 	 * Setter and getter methods for the sensor scale.
 	 * @s Pointer to sensor data.
@@ -112,19 +105,16 @@ struct accelgyro_drv {
 	 * @temp: temperature when calibration was done.
 	 * @return EC_SUCCESS if successful, non-zero if error.
 	 */
-	int (*set_scale)(const struct motion_sensor_t *s,
-				const uint16_t    *scale,
-				int16_t    temp);
-	int (*get_scale)(const struct motion_sensor_t *s,
-				uint16_t   *scale,
-				int16_t    *temp);
+	int (*set_scale)(const struct motion_sensor_t *s, const uint16_t *scale,
+			 int16_t temp);
+	int (*get_scale)(const struct motion_sensor_t *s, uint16_t *scale,
+			 int16_t *temp);
 	/**
 	 * Request performing/entering calibration.
 	 * Either a one shot mode (enable is not used),
 	 * or enter/exit a calibration state.
 	 */
-	int (*perform_calib)(struct motion_sensor_t *s,
-				int        enable);
+	int (*perform_calib)(struct motion_sensor_t *s, int enable);
 
 	/**
 	 * Function that probes if supported chip is present.
@@ -161,8 +151,7 @@ struct accelgyro_drv {
 	 * @data additional data if needed, activity dependent.
 	 */
 	int (*manage_activity)(const struct motion_sensor_t *s,
-			       enum motionsensor_activity activity,
-			       int enable,
+			       enum motionsensor_activity activity, int enable,
 			       const struct ec_motion_sense_activity *data);
 	/**
 	 * List activities managed by the sensors.
@@ -171,8 +160,7 @@ struct accelgyro_drv {
 	 * @disabled bit mask of activities currently disabled.
 	 */
 	int (*list_activities)(const struct motion_sensor_t *s,
-			       uint32_t *enabled,
-			       uint32_t *disabled);
+			       uint32_t *enabled, uint32_t *disabled);
 
 	/**
 	 * Get the root mean square of current noise (ug/mdps) in the sensor.
@@ -248,9 +236,9 @@ struct rgb_calibration_t {
 
 /* als driver data */
 struct als_drv_data_t {
-	int rate;          /* holds current sensor rate */
-	int last_value;    /* holds last als clear channel value */
-	struct als_calibration_t als_cal;    /* calibration data */
+	int rate; /* holds current sensor rate */
+	int last_value; /* holds last als clear channel value */
+	struct als_calibration_t als_cal; /* calibration data */
 };
 
 #define SENSOR_APPLY_DIV_SCALE(_input, _scale) \
@@ -260,6 +248,6 @@ struct als_drv_data_t {
 	(((_input) * (uint64_t)(_scale)) / MOTION_SENSE_DEFAULT_SCALE)
 
 /* Individual channel scale value between 0 and 2 represented in 16 bits */
-#define ALS_CHANNEL_SCALE(_x) ((_x) * MOTION_SENSE_DEFAULT_SCALE)
+#define ALS_CHANNEL_SCALE(_x) ((_x)*MOTION_SENSE_DEFAULT_SCALE)
 
 #endif /* __CROS_EC_ACCELGYRO_H */
diff --git a/include/acpi.h b/include/acpi.h
index 56930c4b2d..b99fe9a235 100644
--- a/include/acpi.h
+++ b/include/acpi.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -74,4 +74,4 @@ int acpi_dptf_set_profile_num(int n);
  */
 int acpi_dptf_get_profile_num(void);
 
-#endif	/* __CROS_EC_ACPI_H */
+#endif /* __CROS_EC_ACPI_H */
diff --git a/include/adc.h b/include/adc.h
index 890b6662d4..ddb6c8246e 100644
--- a/include/adc.h
+++ b/include/adc.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,7 +11,7 @@
 #include "adc_chip.h"
 #include "common.h"
 
-#define ADC_READ_ERROR -1  /* Value returned by adc_read_channel() on error */
+#define ADC_READ_ERROR -1 /* Value returned by adc_read_channel() on error */
 
 #ifdef CONFIG_ZEPHYR
 #include <zephyr_adc.h>
@@ -80,4 +80,4 @@ int adc_disable_watchdog(void);
  */
 int adc_set_watchdog_delay(int delay_ms);
 
-#endif  /* __CROS_EC_ADC_H */
+#endif /* __CROS_EC_ADC_H */
diff --git a/include/als.h b/include/als.h
index 4ff3fcdb4f..21c373c9b6 100644
--- a/include/als.h
+++ b/include/als.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -34,4 +34,4 @@ extern struct als_t als[];
  */
 int als_read(enum als_id id, int *lux);
 
-#endif  /* __CROS_EC_ALS_H */
+#endif /* __CROS_EC_ALS_H */
diff --git a/include/ap_hang_detect.h b/include/ap_hang_detect.h
index 9526bb0a84..8dfcce6d74 100644
--- a/include/ap_hang_detect.h
+++ b/include/ap_hang_detect.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,4 +17,4 @@
  */
 void hang_detect_stop_on_host_command(void);
 
-#endif  /* __CROS_EC_AP_HANG_DETECT_H */
+#endif /* __CROS_EC_AP_HANG_DETECT_H */
diff --git a/include/atkbd_protocol.h b/include/atkbd_protocol.h
new file mode 100644
index 0000000000..a33e6e455e
--- /dev/null
+++ b/include/atkbd_protocol.h
@@ -0,0 +1,45 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * ATKBD keyboard protocol constants.
+ *
+ * See the IBL PC AT Technical Reference Manual Section 4.
+ * i.e., 6183355_PC_AT_Technical_Reference_Mar86.pdf
+ *
+ * https://archive.org/details/bitsavers_ibmpcat618ferenceMar86_25829277/page/n151/mode/2up
+ */
+
+#ifndef __CROS_EC_ATKBD_PROTOCOL_H
+#define __CROS_EC_ATKBD_PROTOCOL_H
+
+#define ATKBD_CMD_OK_GETID 0xe8
+#define ATKBD_CMD_EX_ENABLE 0xea
+#define ATKBD_CMD_EX_SETLEDS 0xeb
+#define ATKBD_CMD_SETLEDS 0xed
+#define ATKBD_CMD_DIAG_ECHO 0xee
+#define ATKBD_CMD_GSCANSET 0xf0
+#define ATKBD_CMD_SSCANSET 0xf0
+#define ATKBD_CMD_GETID 0xf2
+#define ATKBD_CMD_SETREP 0xf3
+#define ATKBD_CMD_ENABLE 0xf4
+#define ATKBD_CMD_RESET_DIS 0xf5
+#define ATKBD_CMD_RESET_DEF 0xf6
+#define ATKBD_CMD_ALL_TYPEM 0xf7
+#define ATKBD_CMD_SETALL_MB 0xf8
+#define ATKBD_CMD_SETALL_MBR 0xfa
+#define ATKBD_CMD_SET_A_KEY_T 0xfb
+#define ATKBD_CMD_SET_A_KEY_MR 0xfc
+#define ATKBD_CMD_SET_A_KEY_M 0xfd
+#define ATKBD_CMD_RESEND 0xfe
+#define ATKBD_CMD_RESET 0xff
+
+#define ATKBD_RET_OVERFLOW 0x00
+#define ATKBD_RET_TEST_SUCCESS 0xaa
+#define ATKBD_RET_ECHO 0xee
+#define ATKBD_RET_ACK 0xfa
+#define ATKBD_RET_TEST_FAIL 0xfc
+#define ATKBD_RET_INTERNAL_FAIL 0xfd
+#define ATKBD_RET_RESEND 0xfe
+
+#endif /* __CROS_EC_ATKBD_PROTOCOL_H */
diff --git a/include/atomic_bit.h b/include/atomic_bit.h
index 3aeaa6c5b6..34416a2f89 100644
--- a/include/atomic_bit.h
+++ b/include/atomic_bit.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/atomic_t.h b/include/atomic_t.h
index d7c1a99147..7f95665f46 100644
--- a/include/atomic_t.h
+++ b/include/atomic_t.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,4 +19,4 @@ typedef atomic_t atomic_val_t;
 #include <zephyr/sys/atomic.h>
 #endif
 
-#endif  /* __CROS_EC_ATOMIC_T_H */
+#endif /* __CROS_EC_ATOMIC_T_H */
diff --git a/include/audio_codec.h b/include/audio_codec.h
index b80d1c0f57..431f776247 100644
--- a/include/audio_codec.h
+++ b/include/audio_codec.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -41,8 +41,8 @@ int audio_codec_capable(uint8_t cap);
  *   EC_ERROR_INVAL if invalid cap.
  *   EC_ERROR_BUSY if the shm_id has been registered.
  */
-int audio_codec_register_shm(uint8_t shm_id, uint8_t cap,
-		uintptr_t *addr, uint32_t len, uint8_t type);
+int audio_codec_register_shm(uint8_t shm_id, uint8_t cap, uintptr_t *addr,
+			     uint32_t len, uint8_t type);
 
 /*
  * Translates the physical address from AP to EC's memory space.  Required if
@@ -63,7 +63,6 @@ int audio_codec_memmap_ap_to_ec(uintptr_t ap_addr, uintptr_t *ec_addr);
  */
 int16_t audio_codec_s16_scale_and_clip(int16_t orig, uint8_t scalar);
 
-
 /*
  * DMIC abstract layer
  */
@@ -120,7 +119,6 @@ int audio_codec_dmic_set_gain_idx(uint8_t channel, uint8_t gain);
  */
 int audio_codec_dmic_get_gain_idx(uint8_t channel, uint8_t *gain);
 
-
 /*
  * I2S RX abstract layer
  */
@@ -181,7 +179,6 @@ int audio_codec_i2s_rx_set_daifmt(uint8_t daifmt);
  */
 int audio_codec_i2s_rx_set_bclk(uint32_t bclk);
 
-
 /*
  * WoV abstract layer
  */
diff --git a/include/backlight.h b/include/backlight.h
index 1bfafbdd2c..4d37af01c0 100644
--- a/include/backlight.h
+++ b/include/backlight.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,7 +19,9 @@
 #ifdef CONFIG_BACKLIGHT_REQ_GPIO
 void backlight_interrupt(enum gpio_signal signal);
 #else
-static inline void backlight_interrupt(enum gpio_signal signal) { }
+static inline void backlight_interrupt(enum gpio_signal signal)
+{
+}
 #endif /* !CONFIG_BACKLIGHT_REQ_GPIO */
 
 /**
@@ -27,4 +29,4 @@ static inline void backlight_interrupt(enum gpio_signal signal) { }
  */
 void enable_backlight(int enabled);
 
-#endif  /* __CROS_EC_BACKLIGHT_H */
+#endif /* __CROS_EC_BACKLIGHT_H */
diff --git a/include/base32.h b/include/base32.h
index ac04ce9c70..a1816afb60 100644
--- a/include/base32.h
+++ b/include/base32.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -41,9 +41,8 @@ uint8_t crc5_sym(uint8_t sym, uint8_t previous_crc);
  *				must be a multiple of add_crc_every.
  * @return EC_SUCCESS, or non-zero error code.
  */
-int base32_encode(char *dest, int destlen_chars,
-		  const void *srcbits, int srclen_bits,
-		  int add_crc_every);
+int base32_encode(char *dest, int destlen_chars, const void *srcbits,
+		  int srclen_bits, int add_crc_every);
 
 /**
  * base32-decode data from a null-terminated string
diff --git a/include/base_state.h b/include/base_state.h
index d8c72e5663..60b499ecd0 100644
--- a/include/base_state.h
+++ b/include/base_state.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/battery.h b/include/battery.h
index 9daf1ce981..51fcd68696 100644
--- a/include/battery.h
+++ b/include/battery.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -23,38 +23,41 @@
 #else /* !CONFIG_ZEPHYR */
 
 /* Stop charge when charging and battery level >= this percentage */
-#define BATTERY_LEVEL_FULL		100
+#define BATTERY_LEVEL_FULL 100
 
 /* Tell host we're charged when battery level >= this percentage */
 #ifdef CONFIG_BATTERY_LEVEL_NEAR_FULL
-#define BATTERY_LEVEL_NEAR_FULL		 CONFIG_BATTERY_LEVEL_NEAR_FULL
+#define BATTERY_LEVEL_NEAR_FULL CONFIG_BATTERY_LEVEL_NEAR_FULL
 #else
-#define BATTERY_LEVEL_NEAR_FULL		 97
+#define BATTERY_LEVEL_NEAR_FULL 97
 #endif
 
 /*
  * Send battery-low host event when discharging and battery level <= this level
  */
-#define BATTERY_LEVEL_LOW		 10
+#define BATTERY_LEVEL_LOW 10
 
 /*
  * Send battery-critical host event when discharging and battery level <= this
  * level.
  */
-#define BATTERY_LEVEL_CRITICAL		  5
+#define BATTERY_LEVEL_CRITICAL 5
 
 /*
  * Shut down main processor and/or hibernate EC when discharging and battery
  * level < this level. Setting this too low makes the battery discharge too
  * deeply, which isn't good for the battery health.
  */
-#define BATTERY_LEVEL_SHUTDOWN		  3
+#define BATTERY_LEVEL_SHUTDOWN 3
 
 #endif /* CONFIG_ZEPHYR */
 
 /* Full-capacity change reqd for host event */
 #define LFCC_EVENT_THRESH 5
 
+/* Max string size in the SB spec is 31. */
+#define SB_MAX_STR_SIZE 31
+
 /* Battery index, only used with CONFIG_BATTERY_V2. */
 enum battery_index {
 	BATT_IDX_INVALID = -1,
@@ -66,7 +69,7 @@ enum battery_index {
  * Sometimes we have hardware to detect battery present, sometimes we have to
  * wait until we've been able to talk to the battery.
  */
-FORWARD_DECLARE_ENUM(battery_present) {
+FORWARD_DECLARE_ENUM(battery_present){
 	BP_NOT_INIT = -1,
 	BP_NO = 0,
 	BP_YES = 1,
@@ -96,13 +99,12 @@ struct battery_static_info {
 	 * char device_name[32];
 	 * char chemistry[32];
 	 */
-	/* Max string size in the SB spec is 31. */
-	char manufacturer_ext[32];	/* SB_MANUFACTURER_NAME */
-	char model_ext[32];		/* SB_DEVICE_NAME */
-	char serial_ext[32];		/* SB_SERIAL_NUMBER */
-	char type_ext[32];		/* SB_DEVICE_CHEMISTRY */
+	char manufacturer_ext[SB_MAX_STR_SIZE + 1]; /* SB_MANUFACTURER_NAME */
+	char model_ext[SB_MAX_STR_SIZE + 1]; /* SB_DEVICE_NAME */
+	char serial_ext[SB_MAX_STR_SIZE + 1]; /* SB_SERIAL_NUMBER */
+	char type_ext[SB_MAX_STR_SIZE + 1]; /* SB_DEVICE_CHEMISTRY */
 #ifdef CONFIG_BATTERY_VENDOR_PARAM
-	uint8_t vendor_param[32];
+	uint8_t vendor_param[SB_MAX_STR_SIZE + 1];
 #endif
 };
 
@@ -111,18 +113,18 @@ extern struct ec_response_battery_dynamic_info battery_dynamic[];
 
 /* Battery parameters */
 struct batt_params {
-	int temperature;      /* Temperature in 0.1 K */
-	int state_of_charge;  /* State of charge (percent, 0-100) */
-	int voltage;          /* Battery voltage (mV) */
-	int current;          /* Battery current (mA); negative=discharging */
-	int desired_voltage;  /* Charging voltage desired by battery (mV) */
-	int desired_current;  /* Charging current desired by battery (mA) */
-	int remaining_capacity;  /* Remaining capacity in mAh */
-	int full_capacity;    /* Capacity in mAh (might change occasionally) */
-	int display_charge;   /* Display charge in 10ths of a % (1000=100.0%) */
-	int status;	      /* Battery status */
+	int temperature; /* Temperature in 0.1 K */
+	int state_of_charge; /* State of charge (percent, 0-100) */
+	int voltage; /* Battery voltage (mV) */
+	int current; /* Battery current (mA); negative=discharging */
+	int desired_voltage; /* Charging voltage desired by battery (mV) */
+	int desired_current; /* Charging current desired by battery (mA) */
+	int remaining_capacity; /* Remaining capacity in mAh */
+	int full_capacity; /* Capacity in mAh (might change occasionally) */
+	int display_charge; /* Display charge in 10ths of a % (1000=100.0%) */
+	int status; /* Battery status */
 	enum battery_present is_present; /* Is the battery physically present */
-	int flags;            /* Flags */
+	int flags; /* Flags */
 };
 
 /*
@@ -138,25 +140,25 @@ int battery_get_avg_voltage(void); /* in mV */
 /* Flags for batt_params */
 
 /* Battery wants to be charged */
-#define BATT_FLAG_WANT_CHARGE			0x00000001
+#define BATT_FLAG_WANT_CHARGE 0x00000001
 
 /* Battery is responsive (talking to us via I2C) */
-#define BATT_FLAG_RESPONSIVE			0x00000002
+#define BATT_FLAG_RESPONSIVE 0x00000002
 
 /* Bits to indicate which parameter(s) could not be read */
-#define BATT_FLAG_BAD_TEMPERATURE		0x00000004
-#define BATT_FLAG_BAD_STATE_OF_CHARGE		0x00000008
-#define BATT_FLAG_BAD_VOLTAGE			0x00000010
-#define BATT_FLAG_BAD_CURRENT			0x00000020
-#define BATT_FLAG_BAD_DESIRED_VOLTAGE		0x00000040
-#define BATT_FLAG_BAD_DESIRED_CURRENT		0x00000080
-#define BATT_FLAG_BAD_REMAINING_CAPACITY	0x00000100
-#define BATT_FLAG_BAD_FULL_CAPACITY		0x00000200
-#define BATT_FLAG_BAD_STATUS			0x00000400
-#define BATT_FLAG_IMBALANCED_CELL		0x00000800
-#define BATT_FLAG_BAD_AVERAGE_CURRENT		0x00001000
+#define BATT_FLAG_BAD_TEMPERATURE 0x00000004
+#define BATT_FLAG_BAD_STATE_OF_CHARGE 0x00000008
+#define BATT_FLAG_BAD_VOLTAGE 0x00000010
+#define BATT_FLAG_BAD_CURRENT 0x00000020
+#define BATT_FLAG_BAD_DESIRED_VOLTAGE 0x00000040
+#define BATT_FLAG_BAD_DESIRED_CURRENT 0x00000080
+#define BATT_FLAG_BAD_REMAINING_CAPACITY 0x00000100
+#define BATT_FLAG_BAD_FULL_CAPACITY 0x00000200
+#define BATT_FLAG_BAD_STATUS 0x00000400
+#define BATT_FLAG_IMBALANCED_CELL 0x00000800
+#define BATT_FLAG_BAD_AVERAGE_CURRENT 0x00001000
 /* All of the above BATT_FLAG_BAD_* bits */
-#define BATT_FLAG_BAD_ANY			0x000017fc
+#define BATT_FLAG_BAD_ANY 0x000017fc
 
 /* Battery constants */
 struct battery_info {
diff --git a/include/battery_bq27621_g1.h b/include/battery_bq27621_g1.h
index ff7e546f3a..019a9d2fe4 100644
--- a/include/battery_bq27621_g1.h
+++ b/include/battery_bq27621_g1.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/include/battery_fuel_gauge.h b/include/battery_fuel_gauge.h
index 7589a68190..b3fbb035e7 100644
--- a/include/battery_fuel_gauge.h
+++ b/include/battery_fuel_gauge.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -67,7 +67,6 @@ struct board_batt_params {
 extern const struct board_batt_params board_battery_info[];
 extern const enum battery_type DEFAULT_BATTERY_TYPE;
 
-
 #ifdef CONFIG_BATTERY_MEASURE_IMBALANCE
 /**
  * Report the absolute difference between the highest and lowest cell voltage in
diff --git a/include/battery_smart.h b/include/battery_smart.h
index c37b7c692c..f07b967861 100644
--- a/include/battery_smart.h
+++ b/include/battery_smart.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,167 +11,168 @@
 #include "common.h"
 
 /* Smart battery and charger I2C address */
-#define BATTERY_ADDR_FLAGS	0x0B
-#define CHARGER_ADDR_FLAGS	0x09
+#define BATTERY_ADDR_FLAGS 0x0B
+#define CHARGER_ADDR_FLAGS 0x09
 
 /* Charger functions */
-#define SB_CHARGER_SPEC_INFO            0x11
-#define SB_CHARGE_MODE                  0x12
-#define SB_CHARGER_STATUS               0x13
-#define SB_CHARGING_CURRENT             0x14
-#define SB_CHARGING_VOLTAGE             0x15
-#define SB_ALARM_WARNING                0x16
+#define SB_CHARGER_SPEC_INFO 0x11
+#define SB_CHARGE_MODE 0x12
+#define SB_CHARGER_STATUS 0x13
+#define SB_CHARGING_CURRENT 0x14
+#define SB_CHARGING_VOLTAGE 0x15
+#define SB_ALARM_WARNING 0x16
 
 /* Battery functions */
-#define SB_MANUFACTURER_ACCESS          0x00
-#define SB_REMAINING_CAPACITY_ALARM     0x01
-#define SB_REMAINING_TIME_ALARM         0x02
-#define SB_BATTERY_MODE                 0x03
-#define SB_AT_RATE                      0x04
-#define SB_AT_RATE_TIME_TO_FULL         0x05
-#define SB_AT_RATE_TIME_TO_EMPTY        0x06
-#define SB_AT_RATE_OK                   0x07
-#define SB_TEMPERATURE                  0x08
-#define SB_VOLTAGE                      0x09
-#define SB_CURRENT                      0x0a
-#define SB_AVERAGE_CURRENT              0x0b
-#define SB_MAX_ERROR                    0x0c
-#define SB_RELATIVE_STATE_OF_CHARGE     0x0d
-#define SB_ABSOLUTE_STATE_OF_CHARGE     0x0e
-#define SB_REMAINING_CAPACITY           0x0f
-#define SB_FULL_CHARGE_CAPACITY         0x10
-#define SB_RUN_TIME_TO_EMPTY            0x11
-#define SB_AVERAGE_TIME_TO_EMPTY        0x12
-#define SB_AVERAGE_TIME_TO_FULL         0x13
-#define SB_CHARGING_CURRENT             0x14
-#define SB_CHARGING_VOLTAGE             0x15
-#define SB_BATTERY_STATUS               0x16
-#define SB_CYCLE_COUNT                  0x17
-#define SB_DESIGN_CAPACITY              0x18
-#define SB_DESIGN_VOLTAGE               0x19
-#define SB_SPECIFICATION_INFO           0x1a
-#define SB_MANUFACTURE_DATE             0x1b
-#define SB_SERIAL_NUMBER                0x1c
-#define SB_MANUFACTURER_NAME            0x20
-#define SB_DEVICE_NAME                  0x21
-#define SB_DEVICE_CHEMISTRY             0x22
-#define SB_MANUFACTURER_DATA            0x23
-#define SB_OPTIONAL_MFG_FUNC1		0x3C
-#define SB_OPTIONAL_MFG_FUNC2		0x3D
-#define SB_OPTIONAL_MFG_FUNC3		0x3E
-#define SB_OPTIONAL_MFG_FUNC4		0x3F
+#define SB_MANUFACTURER_ACCESS 0x00
+#define SB_REMAINING_CAPACITY_ALARM 0x01
+#define SB_REMAINING_TIME_ALARM 0x02
+#define SB_BATTERY_MODE 0x03
+#define SB_AT_RATE 0x04
+#define SB_AT_RATE_TIME_TO_FULL 0x05
+#define SB_AT_RATE_TIME_TO_EMPTY 0x06
+#define SB_AT_RATE_OK 0x07
+#define SB_TEMPERATURE 0x08
+#define SB_VOLTAGE 0x09
+#define SB_CURRENT 0x0a
+#define SB_AVERAGE_CURRENT 0x0b
+#define SB_MAX_ERROR 0x0c
+#define SB_RELATIVE_STATE_OF_CHARGE 0x0d
+#define SB_ABSOLUTE_STATE_OF_CHARGE 0x0e
+#define SB_REMAINING_CAPACITY 0x0f
+#define SB_FULL_CHARGE_CAPACITY 0x10
+#define SB_RUN_TIME_TO_EMPTY 0x11
+#define SB_AVERAGE_TIME_TO_EMPTY 0x12
+#define SB_AVERAGE_TIME_TO_FULL 0x13
+#define SB_CHARGING_CURRENT 0x14
+#define SB_CHARGING_VOLTAGE 0x15
+#define SB_BATTERY_STATUS 0x16
+#define SB_CYCLE_COUNT 0x17
+#define SB_DESIGN_CAPACITY 0x18
+#define SB_DESIGN_VOLTAGE 0x19
+#define SB_SPECIFICATION_INFO 0x1a
+#define SB_MANUFACTURE_DATE 0x1b
+#define SB_SERIAL_NUMBER 0x1c
+#define SB_MANUFACTURER_NAME 0x20
+#define SB_DEVICE_NAME 0x21
+#define SB_DEVICE_CHEMISTRY 0x22
+#define SB_MANUFACTURER_DATA 0x23
+#define SB_OPTIONAL_MFG_FUNC1 0x3C
+#define SB_OPTIONAL_MFG_FUNC2 0x3D
+#define SB_OPTIONAL_MFG_FUNC3 0x3E
+#define SB_OPTIONAL_MFG_FUNC4 0x3F
 /* Extension of smart battery spec, may not be supported on all platforms */
-#define SB_PACK_STATUS                  0x43
-#define SB_ALT_MANUFACTURER_ACCESS      0x44
-#define SB_MANUFACTURE_INFO		0x70
+#define SB_PACK_STATUS 0x43
+#define SB_ALT_MANUFACTURER_ACCESS 0x44
+#define SB_MANUFACTURE_INFO 0x70
 
 /* Battery mode */
 #define MODE_INTERNAL_CHARGE_CONTROLLER BIT(0)
-#define MODE_PRIMARY_BATTERY_SUPPORT    BIT(1)
-#define MODE_CONDITION_CYCLE            BIT(7)
-#define MODE_CHARGE_CONTROLLER_ENABLED  BIT(8)
-#define MODE_PRIMARY_BATTERY            BIT(9)
-#define MODE_ALARM                      BIT(13)
-#define MODE_CHARGER                    BIT(14)
-#define MODE_CAPACITY                   BIT(15)
+#define MODE_PRIMARY_BATTERY_SUPPORT BIT(1)
+#define MODE_CONDITION_CYCLE BIT(7)
+#define MODE_CHARGE_CONTROLLER_ENABLED BIT(8)
+#define MODE_PRIMARY_BATTERY BIT(9)
+#define MODE_ALARM BIT(13)
+#define MODE_CHARGER BIT(14)
+#define MODE_CAPACITY BIT(15)
 
 /* Battery status */
-#define STATUS_ERR_CODE_MASK            0xf
-#define STATUS_CODE_OK                  0
-#define STATUS_CODE_BUSY                1
-#define STATUS_CODE_RESERVED            2
-#define STATUS_CODE_UNSUPPORTED         3
-#define STATUS_CODE_ACCESS_DENIED       4
-#define STATUS_CODE_OVERUNDERFLOW       5
-#define STATUS_CODE_BADSIZE             6
-#define STATUS_CODE_UNKNOWN_ERROR       7
-#define STATUS_FULLY_DISCHARGED         BIT(4)
-#define STATUS_FULLY_CHARGED            BIT(5)
-#define STATUS_DISCHARGING              BIT(6)
-#define STATUS_INITIALIZED              BIT(7)
-#define STATUS_REMAINING_TIME_ALARM     BIT(8)
+#define STATUS_ERR_CODE_MASK 0xf
+#define STATUS_CODE_OK 0
+#define STATUS_CODE_BUSY 1
+#define STATUS_CODE_RESERVED 2
+#define STATUS_CODE_UNSUPPORTED 3
+#define STATUS_CODE_ACCESS_DENIED 4
+#define STATUS_CODE_OVERUNDERFLOW 5
+#define STATUS_CODE_BADSIZE 6
+#define STATUS_CODE_UNKNOWN_ERROR 7
+#define STATUS_FULLY_DISCHARGED BIT(4)
+#define STATUS_FULLY_CHARGED BIT(5)
+#define STATUS_DISCHARGING BIT(6)
+#define STATUS_INITIALIZED BIT(7)
+#define STATUS_REMAINING_TIME_ALARM BIT(8)
 #define STATUS_REMAINING_CAPACITY_ALARM BIT(9)
 #define STATUS_TERMINATE_DISCHARGE_ALARM BIT(11)
-#define STATUS_OVERTEMP_ALARM           BIT(12)
-#define STATUS_TERMINATE_CHARGE_ALARM   BIT(14)
-#define STATUS_OVERCHARGED_ALARM        BIT(15)
+#define STATUS_OVERTEMP_ALARM BIT(12)
+#define STATUS_TERMINATE_CHARGE_ALARM BIT(14)
+#define STATUS_OVERCHARGED_ALARM BIT(15)
 
 /* Battery Spec Info */
-#define BATTERY_SPEC_REVISION_MASK	0x000F
-#define BATTERY_SPEC_REVISION_SHIFT	0
-#define BATTERY_SPEC_VERSION_MASK	0x00F0
-#define BATTERY_SPEC_VERSION_SHIFT	4
-#define BATTERY_SPEC_VSCALE_MASK	0x0F00
-#define BATTERY_SPEC_VSCALE_SHIFT	8
-#define BATTERY_SPEC_IPSCALE_MASK	0xF000
-#define BATTERY_SPEC_IPSCALE_SHIFT	12
-
-#define BATTERY_SPEC_VERSION(INFO)      ((INFO & BATTERY_SPEC_VERSION_MASK) >> \
-					 BATTERY_SPEC_VERSION_SHIFT)
+#define BATTERY_SPEC_REVISION_MASK 0x000F
+#define BATTERY_SPEC_REVISION_SHIFT 0
+#define BATTERY_SPEC_VERSION_MASK 0x00F0
+#define BATTERY_SPEC_VERSION_SHIFT 4
+#define BATTERY_SPEC_VSCALE_MASK 0x0F00
+#define BATTERY_SPEC_VSCALE_SHIFT 8
+#define BATTERY_SPEC_IPSCALE_MASK 0xF000
+#define BATTERY_SPEC_IPSCALE_SHIFT 12
+
+#define BATTERY_SPEC_VERSION(INFO) \
+	((INFO & BATTERY_SPEC_VERSION_MASK) >> BATTERY_SPEC_VERSION_SHIFT)
 /* Smart battery version info */
-#define BATTERY_SPEC_VER_1_0            1
-#define BATTERY_SPEC_VER_1_1            2
-#define BATTERY_SPEC_VER_1_1_WITH_PEC   3
+#define BATTERY_SPEC_VER_1_0 1
+#define BATTERY_SPEC_VER_1_1 2
+#define BATTERY_SPEC_VER_1_1_WITH_PEC 3
 /* Smart battery revision info */
-#define BATTERY_SPEC_REVISION_1		1
+#define BATTERY_SPEC_REVISION_1 1
 
 /* Charger alarm warning */
-#define ALARM_OVER_CHARGED              0x8000
-#define ALARM_TERMINATE_CHARGE          0x4000
-#define ALARM_RESERVED_2000             0x2000
-#define ALARM_OVER_TEMP                 0x1000
-#define ALARM_TERMINATE_DISCHARGE       0x0800
-#define ALARM_RESERVED_0400             0x0400
-#define ALARM_REMAINING_CAPACITY        0x0200
-#define ALARM_REMAINING_TIME            0x0100
-#define ALARM_STATUS_INITIALIZE         0x0080
-#define ALARM_STATUS_DISCHARGING        0x0040
-#define ALARM_STATUS_FULLY_CHARGED      0x0020
-#define ALARM_STATUS_FULLY_DISCHARGED   0x0010
+#define ALARM_OVER_CHARGED 0x8000
+#define ALARM_TERMINATE_CHARGE 0x4000
+#define ALARM_RESERVED_2000 0x2000
+#define ALARM_OVER_TEMP 0x1000
+#define ALARM_TERMINATE_DISCHARGE 0x0800
+#define ALARM_RESERVED_0400 0x0400
+#define ALARM_REMAINING_CAPACITY 0x0200
+#define ALARM_REMAINING_TIME 0x0100
+#define ALARM_STATUS_INITIALIZE 0x0080
+#define ALARM_STATUS_DISCHARGING 0x0040
+#define ALARM_STATUS_FULLY_CHARGED 0x0020
+#define ALARM_STATUS_FULLY_DISCHARGED 0x0010
 /* Charge mode */
-#define CHARGE_FLAG_INHIBIT_CHARGE      BIT(0)
-#define CHARGE_FLAG_ENABLE_POLLING      BIT(1)
-#define CHARGE_FLAG_POR_RESET           BIT(2)
-#define CHARGE_FLAG_RESET_TO_ZERO       BIT(3)
+#define CHARGE_FLAG_INHIBIT_CHARGE BIT(0)
+#define CHARGE_FLAG_ENABLE_POLLING BIT(1)
+#define CHARGE_FLAG_POR_RESET BIT(2)
+#define CHARGE_FLAG_RESET_TO_ZERO BIT(3)
 /* Charger status */
-#define CHARGER_CHARGE_INHIBITED        BIT(0)
-#define CHARGER_POLLING_ENABLED         BIT(1)
-#define CHARGER_VOLTAGE_NOTREG          BIT(2)
-#define CHARGER_CURRENT_NOTREG          BIT(3)
-#define CHARGER_LEVEL_2                 BIT(4)
-#define CHARGER_LEVEL_3                 BIT(5)
-#define CHARGER_CURRENT_OR              BIT(6)
-#define CHARGER_VOLTAGE_OR              BIT(7)
-#define CHARGER_RES_OR                  BIT(8)
-#define CHARGER_RES_COLD                BIT(9)
-#define CHARGER_RES_HOT                 BIT(10)
-#define CHARGER_RES_UR                  BIT(11)
-#define CHARGER_ALARM_INHIBITED         BIT(12)
-#define CHARGER_POWER_FAIL              BIT(13)
-#define CHARGER_BATTERY_PRESENT         BIT(14)
-#define CHARGER_AC_PRESENT              BIT(15)
+#define CHARGER_CHARGE_INHIBITED BIT(0)
+#define CHARGER_POLLING_ENABLED BIT(1)
+#define CHARGER_VOLTAGE_NOTREG BIT(2)
+#define CHARGER_CURRENT_NOTREG BIT(3)
+#define CHARGER_LEVEL_2 BIT(4)
+#define CHARGER_LEVEL_3 BIT(5)
+#define CHARGER_CURRENT_OR BIT(6)
+#define CHARGER_VOLTAGE_OR BIT(7)
+#define CHARGER_RES_OR BIT(8)
+#define CHARGER_RES_COLD BIT(9)
+#define CHARGER_RES_HOT BIT(10)
+#define CHARGER_RES_UR BIT(11)
+#define CHARGER_ALARM_INHIBITED BIT(12)
+#define CHARGER_POWER_FAIL BIT(13)
+#define CHARGER_BATTERY_PRESENT BIT(14)
+#define CHARGER_AC_PRESENT BIT(15)
+#define CHARGER_BYPASS_MODE BIT(16)
 /* Charger specification info */
-#define INFO_CHARGER_SPEC(INFO)         ((INFO) & 0xf)
-#define INFO_SELECTOR_SUPPORT(INFO)     (((INFO) >> 4) & 1)
+#define INFO_CHARGER_SPEC(INFO) ((INFO)&0xf)
+#define INFO_SELECTOR_SUPPORT(INFO) (((INFO) >> 4) & 1)
 
 /* Manufacturer Access parameters */
-#define PARAM_SAFETY_STATUS             0x51
-#define PARAM_OPERATION_STATUS          0x54
-#define PARAM_FIRMWARE_RUNTIME          0x62
+#define PARAM_SAFETY_STATUS 0x51
+#define PARAM_OPERATION_STATUS 0x54
+#define PARAM_FIRMWARE_RUNTIME 0x62
 /* Operation status masks -- 6 byte reply */
 /* reply[3] */
-#define BATTERY_DISCHARGING_DISABLED    0x20
-#define BATTERY_CHARGING_DISABLED       0x40
+#define BATTERY_DISCHARGING_DISABLED 0x20
+#define BATTERY_CHARGING_DISABLED 0x40
 
 /* Battery manufacture date */
-#define MANUFACTURE_DATE_DAY_MASK	0x001F
-#define MANUFACTURE_DATE_DAY_SHIFT	0
-#define MANUFACTURE_DATE_MONTH_MASK	0x01E0
-#define MANUFACTURE_DATE_MONTH_SHIFT	5
-#define MANUFACTURE_DATE_YEAR_MASK	0xFE00
-#define MANUFACTURE_DATE_YEAR_SHIFT	9
-#define MANUFACTURE_DATE_YEAR_OFFSET	1980
-#define MANUFACTURE_RUNTIME_SIZE	4
+#define MANUFACTURE_DATE_DAY_MASK 0x001F
+#define MANUFACTURE_DATE_DAY_SHIFT 0
+#define MANUFACTURE_DATE_MONTH_MASK 0x01E0
+#define MANUFACTURE_DATE_MONTH_SHIFT 5
+#define MANUFACTURE_DATE_YEAR_MASK 0xFE00
+#define MANUFACTURE_DATE_YEAR_SHIFT 9
+#define MANUFACTURE_DATE_YEAR_OFFSET 1980
+#define MANUFACTURE_RUNTIME_SIZE 4
 
 /* Read from battery */
 int sb_read(int cmd, int *param);
diff --git a/include/bluetooth_le.h b/include/bluetooth_le.h
index 286653dda6..e65b3d448b 100644
--- a/include/bluetooth_le.h
+++ b/include/bluetooth_le.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,69 +23,67 @@
 #include "common.h"
 #include "util.h"
 
-#define BLUETOOTH_ADDR_OCTETS                   6
+#define BLUETOOTH_ADDR_OCTETS 6
 
 /*
  * GAP assigned numbers
  * https://www.bluetooth.org/en-us/specification/
  * assigned-numbers/generic-access-profile
  */
-#define GAP_FLAGS                               0x01
-#define GAP_INCOMP_16_BIT_UUID                  0x02
-#define GAP_COMP_16_BIT_UUID                    0x03
-#define GAP_INCOMP_32_BIT_UUID                  0x04
-#define GAP_COMP_32_BIT_UUID                    0x05
-#define GAP_INCOMP_128_BIT_UUID                 0x06
-#define GAP_COMP_128_BIT_UUID                   0x07
-#define GAP_SHORT_NAME                          0x08
-#define GAP_COMPLETE_NAME                       0x09
-#define GAP_TX_POWER_LEVEL                      0x0A
-#define GAP_CLASS_OF_DEVICE                     0x0D
-#define GAP_SIMPLE_PAIRING_HASH                 0x0E
-#define GAP_SIMPLE_PAIRING_HASH_192             0x0E
-#define GAP_SIMPLE_PAIRING_RAND                 0x0F
-#define GAP_SIMPLE_PAIRING_RAND_192             0x0F
-#define GAP_DEVICE_ID                           0x10
-#define GAP_SECURITY_MANAGER_TK                 0x10
-#define GAP_SECURITY_MANAGER_OOB_FLAGS          0x11
-#define GAP_SLAVE_CONNECTION_INTERVAL_RANGE     0x12
-#define GAP_SERVICE_SOLICITATION_UUID_16        0x14
-#define GAP_SERVICE_SOLICITATION_UUID_32        0x1F
-#define GAP_SERVICE_SOLICITATION_UUID_128       0x15
-#define GAP_SERVICE_DATA                        0x16
-#define GAP_SERVICE_DATA_UUID_16                0x16
-#define GAP_SERVICE_DATA_UUID_32                0x20
-#define GAP_SERVICE_DATA_UUID_128               0x21
-#define GAP_LE_SECURE_CONNECTIONS_CONFIRMATION  0x22
-#define GAP_LE_SECURE_CONNECTIONS_RAND          0x23
-#define GAP_PUBLIC_TARGET_ADDRESS               0x17
-#define GAP_RANDOM_TARGET_ADDRESS               0x18
-#define GAP_APPEARANCE                          0x19
-#define GAP_ADVERTISING_INTERVAL                0x1A
-#define GAP_LE_BLUETOOTH_DEVICE_ADDRESS         0x1B
-#define GAP_LE_ROLE                             0x1C
-#define GAP_SIMPLE_PAIRING_HASH_256             0x1D
-#define GAP_SIMPLE_PAIRING_RAND_256             0x1E
-#define GAP_3D_INFORMATION_DATA                 0x3D
-#define GAP_MANUFACTURER_SPECIFIC_DATA          0xFF
-
+#define GAP_FLAGS 0x01
+#define GAP_INCOMP_16_BIT_UUID 0x02
+#define GAP_COMP_16_BIT_UUID 0x03
+#define GAP_INCOMP_32_BIT_UUID 0x04
+#define GAP_COMP_32_BIT_UUID 0x05
+#define GAP_INCOMP_128_BIT_UUID 0x06
+#define GAP_COMP_128_BIT_UUID 0x07
+#define GAP_SHORT_NAME 0x08
+#define GAP_COMPLETE_NAME 0x09
+#define GAP_TX_POWER_LEVEL 0x0A
+#define GAP_CLASS_OF_DEVICE 0x0D
+#define GAP_SIMPLE_PAIRING_HASH 0x0E
+#define GAP_SIMPLE_PAIRING_HASH_192 0x0E
+#define GAP_SIMPLE_PAIRING_RAND 0x0F
+#define GAP_SIMPLE_PAIRING_RAND_192 0x0F
+#define GAP_DEVICE_ID 0x10
+#define GAP_SECURITY_MANAGER_TK 0x10
+#define GAP_SECURITY_MANAGER_OOB_FLAGS 0x11
+#define GAP_SLAVE_CONNECTION_INTERVAL_RANGE 0x12
+#define GAP_SERVICE_SOLICITATION_UUID_16 0x14
+#define GAP_SERVICE_SOLICITATION_UUID_32 0x1F
+#define GAP_SERVICE_SOLICITATION_UUID_128 0x15
+#define GAP_SERVICE_DATA 0x16
+#define GAP_SERVICE_DATA_UUID_16 0x16
+#define GAP_SERVICE_DATA_UUID_32 0x20
+#define GAP_SERVICE_DATA_UUID_128 0x21
+#define GAP_LE_SECURE_CONNECTIONS_CONFIRMATION 0x22
+#define GAP_LE_SECURE_CONNECTIONS_RAND 0x23
+#define GAP_PUBLIC_TARGET_ADDRESS 0x17
+#define GAP_RANDOM_TARGET_ADDRESS 0x18
+#define GAP_APPEARANCE 0x19
+#define GAP_ADVERTISING_INTERVAL 0x1A
+#define GAP_LE_BLUETOOTH_DEVICE_ADDRESS 0x1B
+#define GAP_LE_ROLE 0x1C
+#define GAP_SIMPLE_PAIRING_HASH_256 0x1D
+#define GAP_SIMPLE_PAIRING_RAND_256 0x1E
+#define GAP_3D_INFORMATION_DATA 0x3D
+#define GAP_MANUFACTURER_SPECIFIC_DATA 0xFF
 
 /* org.bluetooth.characteristic.gap.appearance.xml */
-#define GAP_APPEARANCE_HID_KEYBOARD             961
+#define GAP_APPEARANCE_HID_KEYBOARD 961
 
 /* org.bluetooth.service.human_interface_device.xml */
-#define GATT_SERVICE_HID_UUID                   0x1812
+#define GATT_SERVICE_HID_UUID 0x1812
 
 /* Bluetooth Core Supplement v5 */
 
 /* Bluetooth Core Supplement v5 1.3 */
-#define GAP_FLAGS_LE_LIM_DISC   0x01
-#define GAP_FLAGS_LE_GEN_DISC   0x02
-#define GAP_FLAGS_LE_NO_BR_EDR  0x04
+#define GAP_FLAGS_LE_LIM_DISC 0x01
+#define GAP_FLAGS_LE_GEN_DISC 0x02
+#define GAP_FLAGS_LE_NO_BR_EDR 0x04
 
 /* Bluetooth Core Supplement v5 1.3 */
 
-
 /* BLE 4.1 Vol 6 section 2.3 pg 38+ */
 
 /* Advertising PDU Header
@@ -103,49 +101,48 @@ struct ble_adv_header {
 	uint8_t length;
 };
 
-#define BLE_ADV_HEADER_PDU_TYPE_SHIFT    0
-#define BLE_ADV_HEADER_TXADD_SHIFT       6
-#define BLE_ADV_HEADER_RXADD_SHIFT       7
-#define BLE_ADV_HEADER_LENGTH_SHIFT      8
+#define BLE_ADV_HEADER_PDU_TYPE_SHIFT 0
+#define BLE_ADV_HEADER_TXADD_SHIFT 6
+#define BLE_ADV_HEADER_RXADD_SHIFT 7
+#define BLE_ADV_HEADER_LENGTH_SHIFT 8
 
-#define BLE_ADV_HEADER(type, tx, rx, length) \
-		((uint16_t) \
-		((((length) & 0x3f) << BLE_ADV_HEADER_LENGTH_SHIFT) | \
-		 (((rx) & 0x1) << BLE_ADV_HEADER_RXADD_SHIFT) | \
-		 (((tx) & 0x1) << BLE_ADV_HEADER_TXADD_SHIFT) | \
-		 (((type) & 0xf) << BLE_ADV_HEADER_PDU_TYPE_SHIFT)))
+#define BLE_ADV_HEADER(type, tx, rx, length)                           \
+	((uint16_t)((((length)&0x3f) << BLE_ADV_HEADER_LENGTH_SHIFT) | \
+		    (((rx)&0x1) << BLE_ADV_HEADER_RXADD_SHIFT) |       \
+		    (((tx)&0x1) << BLE_ADV_HEADER_TXADD_SHIFT) |       \
+		    (((type)&0xf) << BLE_ADV_HEADER_PDU_TYPE_SHIFT)))
 
-#define BLE_ADV_HEADER_PDU_TYPE_ADV_IND         0
-#define BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND  1
+#define BLE_ADV_HEADER_PDU_TYPE_ADV_IND 0
+#define BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND 1
 #define BLE_ADV_HEADER_PDU_TYPE_ADV_NONCONN_IND 2
-#define BLE_ADV_HEADER_PDU_TYPE_SCAN_REQ        3
-#define BLE_ADV_HEADER_PDU_TYPE_SCAN_RSP        4
-#define BLE_ADV_HEADER_PDU_TYPE_CONNECT_REQ     5
-#define BLE_ADV_HEADER_PDU_TYPE_ADV_SCAN_IND    6
+#define BLE_ADV_HEADER_PDU_TYPE_SCAN_REQ 3
+#define BLE_ADV_HEADER_PDU_TYPE_SCAN_RSP 4
+#define BLE_ADV_HEADER_PDU_TYPE_CONNECT_REQ 5
+#define BLE_ADV_HEADER_PDU_TYPE_ADV_SCAN_IND 6
 
-#define BLE_ADV_HEADER_PUBLIC_ADDR    0
-#define BLE_ADV_HEADER_RANDOM_ADDR    1
+#define BLE_ADV_HEADER_PUBLIC_ADDR 0
+#define BLE_ADV_HEADER_RANDOM_ADDR 1
 
 /* BLE 4.1 Vol 3 Part C 10.8 */
-#define BLE_RANDOM_ADDR_MSBS_PRIVATE             0x00
-#define BLE_RANDOM_ADDR_MSBS_RESOLVABLE_PRIVATE  0x40
-#define BLE_RANDOM_ADDR_MSBS_RFU                 0x80
-#define BLE_RANDOM_ADDR_MSBS_STATIC              0xC0
+#define BLE_RANDOM_ADDR_MSBS_PRIVATE 0x00
+#define BLE_RANDOM_ADDR_MSBS_RESOLVABLE_PRIVATE 0x40
+#define BLE_RANDOM_ADDR_MSBS_RFU 0x80
+#define BLE_RANDOM_ADDR_MSBS_STATIC 0xC0
 
 #define BLE_ADV_ACCESS_ADDRESS 0x8E89BED6
 #define BLE_ADV_CRCINIT 0x555555
 
-#define BLE_MAX_ADV_PAYLOAD_OCTETS       37
+#define BLE_MAX_ADV_PAYLOAD_OCTETS 37
 
 /* LL SCA Values.  They are shifted left 5 bits for Hop values */
-#define BLE_LL_SCA_251_PPM_TO_500_PPM    (0 << 5)
-#define BLE_LL_SCA_151_PPM_TO_250_PPM    BIT(5)
-#define BLE_LL_SCA_101_PPM_TO_150_PPM    (2 << 5)
-#define BLE_LL_SCA_076_PPM_TO_100_PPM    (3 << 5)
-#define BLE_LL_SCA_051_PPM_TO_075_PPM    (4 << 5)
-#define BLE_LL_SCA_031_PPM_TO_050_PPM    (5 << 5)
-#define BLE_LL_SCA_021_PPM_TO_030_PPM    (6 << 5)
-#define BLE_LL_SCA_000_PPM_TO_020_PPM    (7 << 5)
+#define BLE_LL_SCA_251_PPM_TO_500_PPM (0 << 5)
+#define BLE_LL_SCA_151_PPM_TO_250_PPM BIT(5)
+#define BLE_LL_SCA_101_PPM_TO_150_PPM (2 << 5)
+#define BLE_LL_SCA_076_PPM_TO_100_PPM (3 << 5)
+#define BLE_LL_SCA_051_PPM_TO_075_PPM (4 << 5)
+#define BLE_LL_SCA_031_PPM_TO_050_PPM (5 << 5)
+#define BLE_LL_SCA_021_PPM_TO_030_PPM (6 << 5)
+#define BLE_LL_SCA_000_PPM_TO_020_PPM (7 << 5)
 
 /* BLE 4.1 Vol 6 section 2.4 pg 45 */
 
@@ -169,26 +166,25 @@ struct ble_data_header {
 	uint8_t length;
 };
 
-#define BLE_DATA_HEADER_LLID_SHIFT       0
-#define BLE_DATA_HEADER_NESN_SHIFT       2
-#define BLE_DATA_HEADER_SN_SHIFT         3
-#define BLE_DATA_HEADER_MD_SHIFT         4
-#define BLE_DATA_HEADER_LENGTH_SHIFT     8
+#define BLE_DATA_HEADER_LLID_SHIFT 0
+#define BLE_DATA_HEADER_NESN_SHIFT 2
+#define BLE_DATA_HEADER_SN_SHIFT 3
+#define BLE_DATA_HEADER_MD_SHIFT 4
+#define BLE_DATA_HEADER_LENGTH_SHIFT 8
 
 #define BLE_DATA_HEADER_LLID_DATANOSTART 1
-#define BLE_DATA_HEADER_LLID_DATASTART   2
-#define BLE_DATA_HEADER_LLID_CONTROL     3
+#define BLE_DATA_HEADER_LLID_DATASTART 2
+#define BLE_DATA_HEADER_LLID_CONTROL 3
 
-#define BLE_DATA_HEADER(llid, nesn, sn, md, length) \
-		((uint16_t) \
-		((((length) & 0x1f) << BLE_DATA_HEADER_LENGTH_SHIFT) | \
-		 (((MD) & 0x1) << BLE_DATA_HEADER_MD_SHIFT) | \
-		 (((SN) & 0x1) << BLE_DATA_HEADER_SN_SHIFT) | \
-		 (((NESN) & 0x1) << BLE_DATA_HEADER_NESN_SHIFT) | \
-		 (((llid) & 0x3) << BLE_DATA_HEADER_LLID_SHIFT)))
+#define BLE_DATA_HEADER(llid, nesn, sn, md, length)                     \
+	((uint16_t)((((length)&0x1f) << BLE_DATA_HEADER_LENGTH_SHIFT) | \
+		    (((MD)&0x1) << BLE_DATA_HEADER_MD_SHIFT) |          \
+		    (((SN)&0x1) << BLE_DATA_HEADER_SN_SHIFT) |          \
+		    (((NESN)&0x1) << BLE_DATA_HEADER_NESN_SHIFT) |      \
+		    (((llid)&0x3) << BLE_DATA_HEADER_LLID_SHIFT)))
 
-#define BLE_MAX_DATA_PAYLOAD_OCTETS      31
-#define BLE_MAX_PAYLOAD_OCTETS           BLE_MAX_ADV_PAYLOAD_OCTETS
+#define BLE_MAX_DATA_PAYLOAD_OCTETS 31
+#define BLE_MAX_PAYLOAD_OCTETS BLE_MAX_ADV_PAYLOAD_OCTETS
 
 union ble_header {
 	struct ble_adv_header adv;
@@ -210,34 +206,34 @@ struct ble_packet {
 };
 
 /* LL Control PDU Opcodes BLE 4.1 Vol 6 2.4.2 */
-#define BLE_LL_CONNECTION_UPDATE_REQ     0x00
-#define BLE_LL_CHANNEL_MAP_REQ           0x01
-#define BLE_LL_TERMINATE_IND             0x02
-#define BLE_LL_ENC_REQ                   0x03
-#define BLE_LL_ENC_RSP                   0x04
-#define BLE_LL_START_ENC_REQ             0x05
-#define BLE_LL_START_ENC_RSP             0x06
-#define BLE_LL_UNKNOWN_RSP               0x07
-#define BLE_LL_FEATURE_REQ               0x08
-#define BLE_LL_FEATURE_RSP               0x09
-#define BLE_LL_PAUSE_ENC_REQ             0x0A
-#define BLE_LL_PAUSE_ENC_RSP             0x0B
-#define BLE_LL_VERSION_IND               0x0C
-#define BLE_LL_REJECT_IND                0x0D
-#define BLE_LL_SLAVE_FEATURE_REQ         0x0E
-#define BLE_LL_CONNECTION_PARAM_REQ      0x0F
-#define BLE_LL_CONNECTION_PARAM_RSP      0x10
-#define BLE_LL_REJECT_IND_EXT            0x11
-#define BLE_LL_PING_REQ                  0x12
-#define BLE_LL_PING_RSP                  0x13
-#define BLE_LL_RFU                       0x14
+#define BLE_LL_CONNECTION_UPDATE_REQ 0x00
+#define BLE_LL_CHANNEL_MAP_REQ 0x01
+#define BLE_LL_TERMINATE_IND 0x02
+#define BLE_LL_ENC_REQ 0x03
+#define BLE_LL_ENC_RSP 0x04
+#define BLE_LL_START_ENC_REQ 0x05
+#define BLE_LL_START_ENC_RSP 0x06
+#define BLE_LL_UNKNOWN_RSP 0x07
+#define BLE_LL_FEATURE_REQ 0x08
+#define BLE_LL_FEATURE_RSP 0x09
+#define BLE_LL_PAUSE_ENC_REQ 0x0A
+#define BLE_LL_PAUSE_ENC_RSP 0x0B
+#define BLE_LL_VERSION_IND 0x0C
+#define BLE_LL_REJECT_IND 0x0D
+#define BLE_LL_SLAVE_FEATURE_REQ 0x0E
+#define BLE_LL_CONNECTION_PARAM_REQ 0x0F
+#define BLE_LL_CONNECTION_PARAM_RSP 0x10
+#define BLE_LL_REJECT_IND_EXT 0x11
+#define BLE_LL_PING_REQ 0x12
+#define BLE_LL_PING_RSP 0x13
+#define BLE_LL_RFU 0x14
 
 /* BLE 4.1 Vol 6 4.6 Table 4.3 */
-#define BLE_LL_FEATURE_LE_ENCRYPTION     0x00
-#define BLE_LL_FEATURE_CONN_PARAMS_REQ   0x01
-#define BLE_LL_FEATURE_EXT_REJ_IND       0x02
-#define BLE_LL_FEATURE_SLAVE_FEAT_EXCHG  0x03
-#define BLE_LL_FEATURE_LE_PING           0x04
+#define BLE_LL_FEATURE_LE_ENCRYPTION 0x00
+#define BLE_LL_FEATURE_CONN_PARAMS_REQ 0x01
+#define BLE_LL_FEATURE_EXT_REJ_IND 0x02
+#define BLE_LL_FEATURE_SLAVE_FEAT_EXCHG 0x03
+#define BLE_LL_FEATURE_LE_PING 0x04
 
 struct ble_ll_connection_update_req {
 	uint8_t win_size;
@@ -285,8 +281,8 @@ struct ble_ll_feature_rsp {
 
 /* ble_ll_pause_enc_rsp has no CtrData field */
 
-#define BLE_LL_VERS_NR_4_0     6
-#define BLE_LL_VERS_NR_4_1     7
+#define BLE_LL_VERS_NR_4_0 6
+#define BLE_LL_VERS_NR_4_1 7
 
 struct ble_ll_version_ind {
 	uint8_t vers_nr; /* Version Number */
@@ -348,7 +344,7 @@ int chan2freq(int channel);
 
 /* BLE 4.1 Vol 6 2.3.3.1 */
 void fill_remapping_table(struct remapping_table *rt, uint8_t map[5],
-	int hop_increment);
+			  int hop_increment);
 
 void ble_tx(struct ble_pdu *pdu);
 
@@ -376,7 +372,7 @@ uint8_t *pack_adv_int(uint8_t *dest, int length, int type, int data);
 uint8_t *pack_adv_addr(uint8_t *dest, uint64_t addr);
 
 const uint8_t *unpack_adv(const uint8_t *src, int *length, int *type,
-		    const uint8_t **data);
+			  const uint8_t **data);
 
 void dump_ble_addr(uint8_t *mem, char *name);
 
diff --git a/include/bluetooth_le_ll.h b/include/bluetooth_le_ll.h
index 9f540102da..d17aec8a57 100644
--- a/include/bluetooth_le_ll.h
+++ b/include/bluetooth_le_ll.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,33 +17,30 @@ enum ll_state_t {
 	TEST_TX,
 };
 
-#define LL_ADV_INTERVAL_UNIT_US       625
-#define LL_ADV_TIMEOUT_UNIT_US        1000000
+#define LL_ADV_INTERVAL_UNIT_US 625
+#define LL_ADV_TIMEOUT_UNIT_US 1000000
 
-#define LL_ADV_DIRECT_INTERVAL_US     3750    /* 3.75 ms */
-#define LL_ADV_DIRECT_TIMEOUT_US      1280000 /* 1.28 s */
+#define LL_ADV_DIRECT_INTERVAL_US 3750 /* 3.75 ms */
+#define LL_ADV_DIRECT_TIMEOUT_US 1280000 /* 1.28 s */
 
-#define LL_MAX_DATA_PACKET_LENGTH     27
-#define LL_MAX_DATA_PACKETS           4
+#define LL_MAX_DATA_PACKET_LENGTH 27
+#define LL_MAX_DATA_PACKETS 4
 
 /* BTLE Spec 4.0: Vol 6, Part B, Section 4.5.3 */
-#define TRANSMIT_WINDOW_OFFSET_CONSTANT	1250
+#define TRANSMIT_WINDOW_OFFSET_CONSTANT 1250
 
-#define LL_MAX_BUFFER_SIZE  (LL_MAX_DATA_PACKET_LENGTH * LL_MAX_DATA_PACKETS)
+#define LL_MAX_BUFFER_SIZE (LL_MAX_DATA_PACKET_LENGTH * LL_MAX_DATA_PACKETS)
 
-#define LL_SUPPORTED_FEATURES (HCI_LE_FTR_ENCRYPTION | \
-	HCI_LE_FTR_CONNECTION_PARAMETERS_REQUEST | \
-	HCI_LE_FTR_EXTENDED_REJECT_INDICATION | \
-	HCI_LE_FTR_SLAVE_INITIATED_FEATURES_EXCHANGE)
+#define LL_SUPPORTED_FEATURES                                               \
+	(HCI_LE_FTR_ENCRYPTION | HCI_LE_FTR_CONNECTION_PARAMETERS_REQUEST | \
+	 HCI_LE_FTR_EXTENDED_REJECT_INDICATION |                            \
+	 HCI_LE_FTR_SLAVE_INITIATED_FEATURES_EXCHANGE)
 
-#define LL_SUPPORTED_STATES (HCI_LE_STATE_NONCON_ADV | \
-	HCI_LE_STATE_SCANNABLE_ADV | \
-	HCI_LE_STATE_CONNECTABLE_ADV | \
-	HCI_LE_STATE_DIRECT_ADV | \
-	HCI_LE_STATE_PASSIVE_SCAN | \
-	HCI_LE_STATE_ACTIVE_SCAN | \
-	HCI_LE_STATE_INITIATE | \
-	HCI_LE_STATE_SLAVE)
+#define LL_SUPPORTED_STATES                                       \
+	(HCI_LE_STATE_NONCON_ADV | HCI_LE_STATE_SCANNABLE_ADV |   \
+	 HCI_LE_STATE_CONNECTABLE_ADV | HCI_LE_STATE_DIRECT_ADV | \
+	 HCI_LE_STATE_PASSIVE_SCAN | HCI_LE_STATE_ACTIVE_SCAN |   \
+	 HCI_LE_STATE_INITIATE | HCI_LE_STATE_SLAVE)
 
 /*
  * 4.6.1 LE Encryption
@@ -60,64 +57,63 @@ enum ll_state_t {
  */
 
 /*Link Layer Control PDU Opcodes */
-#define LL_CONNECTION_UPDATE_REQ  0x00
-#define LL_CHANNEL_MAP_REQ        0x01
-#define LL_TERMINATE_IND          0x02
-#define LL_ENC_REQ                0x03
-#define LL_ENC_RSP                0x04
-#define LL_START_ENC_REQ          0x05
-#define LL_START_ENC_RSP          0x06
-#define LL_UNKNOWN_RSP            0x07
-#define LL_FEATURE_REQ            0x08
-#define LL_FEATURE_RSP            0x09
-#define LL_PAUSE_ENC_REQ          0x0A
-#define LL_PAUSE_ENC_RSP          0x0B
-#define LL_VERSION_IND            0x0C
-#define LL_REJECT_IND             0x0D
-#define LL_SLAVE_FEATURE_REQ      0x0E
-#define LL_CONNECTION_PARAM_REQ   0x0F
-#define LL_CONNECTION_PARAM_RSP   0x10
-#define LL_REJECT_IND_EXT         0x11
-#define LL_PING_REQ               0x12
-#define LL_PING_RSP               0x13
+#define LL_CONNECTION_UPDATE_REQ 0x00
+#define LL_CHANNEL_MAP_REQ 0x01
+#define LL_TERMINATE_IND 0x02
+#define LL_ENC_REQ 0x03
+#define LL_ENC_RSP 0x04
+#define LL_START_ENC_REQ 0x05
+#define LL_START_ENC_RSP 0x06
+#define LL_UNKNOWN_RSP 0x07
+#define LL_FEATURE_REQ 0x08
+#define LL_FEATURE_RSP 0x09
+#define LL_PAUSE_ENC_REQ 0x0A
+#define LL_PAUSE_ENC_RSP 0x0B
+#define LL_VERSION_IND 0x0C
+#define LL_REJECT_IND 0x0D
+#define LL_SLAVE_FEATURE_REQ 0x0E
+#define LL_CONNECTION_PARAM_REQ 0x0F
+#define LL_CONNECTION_PARAM_RSP 0x10
+#define LL_REJECT_IND_EXT 0x11
+#define LL_PING_REQ 0x12
+#define LL_PING_RSP 0x13
 
 /* BLE 4.1 Vol 6 2.3.3.1 Connection information */
-#define CONNECT_REQ_INITA_LEN					6
-#define CONNECT_REQ_ADVA_LEN					6
-#define CONNECT_REQ_ACCESS_ADDR_LEN				4
-#define CONNECT_REQ_CRC_INIT_VAL_LEN				3
-#define CONNECT_REQ_WIN_SIZE_LEN				1
-#define CONNECT_REQ_WIN_OFFSET_LEN				2
-#define CONNECT_REQ_INTERVAL_LEN				2
-#define CONNECT_REQ_LATENCY_LEN					2
-#define CONNECT_REQ_TIMEOUT_LEN					2
-#define CONNECT_REQ_CHANNEL_MAP_LEN				5
-#define CONNECT_REQ_HOP_INCREMENT_AND_SCA_LEN			1
+#define CONNECT_REQ_INITA_LEN 6
+#define CONNECT_REQ_ADVA_LEN 6
+#define CONNECT_REQ_ACCESS_ADDR_LEN 4
+#define CONNECT_REQ_CRC_INIT_VAL_LEN 3
+#define CONNECT_REQ_WIN_SIZE_LEN 1
+#define CONNECT_REQ_WIN_OFFSET_LEN 2
+#define CONNECT_REQ_INTERVAL_LEN 2
+#define CONNECT_REQ_LATENCY_LEN 2
+#define CONNECT_REQ_TIMEOUT_LEN 2
+#define CONNECT_REQ_CHANNEL_MAP_LEN 5
+#define CONNECT_REQ_HOP_INCREMENT_AND_SCA_LEN 1
 struct ble_connection_params {
-	uint8_t		init_a[CONNECT_REQ_INITA_LEN];
-	uint8_t		adv_a[CONNECT_REQ_ADVA_LEN];
-	uint32_t	access_addr;
-	uint32_t	crc_init_val;
-	uint8_t		win_size;
-	uint16_t	win_offset;
-	uint16_t	interval;
-	uint16_t	latency;
-	uint16_t	timeout;
-	uint64_t	channel_map;
-	uint8_t		hop_increment;
-	uint8_t		sleep_clock_accuracy;
-	uint32_t	transmitWindowOffset;
-	uint32_t	transmitWindowSize;
-	uint32_t	connInterval;
-	uint16_t	connLatency;
-	uint32_t	connSupervisionTimeout;
+	uint8_t init_a[CONNECT_REQ_INITA_LEN];
+	uint8_t adv_a[CONNECT_REQ_ADVA_LEN];
+	uint32_t access_addr;
+	uint32_t crc_init_val;
+	uint8_t win_size;
+	uint16_t win_offset;
+	uint16_t interval;
+	uint16_t latency;
+	uint16_t timeout;
+	uint64_t channel_map;
+	uint8_t hop_increment;
+	uint8_t sleep_clock_accuracy;
+	uint32_t transmitWindowOffset;
+	uint32_t transmitWindowSize;
+	uint32_t connInterval;
+	uint16_t connLatency;
+	uint32_t connSupervisionTimeout;
 };
 
 uint8_t ll_reset(void);
 
 uint8_t ll_set_tx_power(uint8_t *params);
 
-
 /* LE Information */
 uint8_t ll_read_buffer_size(uint8_t *return_params);
 uint8_t ll_read_local_supported_features(uint8_t *return_params);
diff --git a/include/board_config.h b/include/board_config.h
index 5b21be8236..b20f1fe46c 100644
--- a/include/board_config.h
+++ b/include/board_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/include/body_detection.h b/include/body_detection.h
index 59af6580c6..8fea5d84e1 100644
--- a/include/body_detection.h
+++ b/include/body_detection.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,10 +9,7 @@
 #include <stdint.h>
 #include <stdbool.h>
 
-enum body_detect_states {
-	BODY_DETECTION_OFF_BODY,
-	BODY_DETECTION_ON_BODY
-};
+enum body_detect_states { BODY_DETECTION_OFF_BODY, BODY_DETECTION_ON_BODY };
 
 /* get/set the state of body detection */
 enum body_detect_states body_detect_get_state(void);
diff --git a/include/btle_hci2.h b/include/btle_hci2.h
index 193df3391b..dc59b72277 100644
--- a/include/btle_hci2.h
+++ b/include/btle_hci2.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,40 +14,39 @@ struct hciCmdHdr {
 	uint16_t opcode;
 	uint8_t paramLen;
 } __packed;
-#define CMD_MAKE_OPCODE(ogf, ocf) ((((uint16_t)((ogf) & 0x3f)) << 10) | ((ocf) & 0x03ff))
-#define CMD_GET_OGF(opcode)       (((opcode) >> 10) & 0x3f)
-#define CMD_GET_OCF(opcode)       ((opcode) & 0x03ff)
-
+#define CMD_MAKE_OPCODE(ogf, ocf) \
+	((((uint16_t)((ogf)&0x3f)) << 10) | ((ocf)&0x03ff))
+#define CMD_GET_OGF(opcode) (((opcode) >> 10) & 0x3f)
+#define CMD_GET_OCF(opcode) ((opcode)&0x03ff)
 
 struct hciAclHdr {
 	uint16_t hdr;
 	uint16_t len;
 } __packed;
-#define ACL_HDR_MASK_CONN_ID      0x0FFF
-#define ACL_HDR_MASK_PB           0x3000
-#define ACL_HDR_MASK_BC           0xC000
-#define ACL_HDR_PB_FIRST_NONAUTO  0x0000
-#define ACL_HDR_PB_CONTINUED      0x1000
-#define ACL_HDR_PB_FIRST_AUTO     0x2000
-#define ACL_HDR_PB_COMPLETE       0x3000
+#define ACL_HDR_MASK_CONN_ID 0x0FFF
+#define ACL_HDR_MASK_PB 0x3000
+#define ACL_HDR_MASK_BC 0xC000
+#define ACL_HDR_PB_FIRST_NONAUTO 0x0000
+#define ACL_HDR_PB_CONTINUED 0x1000
+#define ACL_HDR_PB_FIRST_AUTO 0x2000
+#define ACL_HDR_PB_COMPLETE 0x3000
 
 struct hciScoHdr {
 	uint16_t hdr;
 	uint8_t len;
 } __packed;
-#define SCO_HDR_MASK_CONN_ID      0x0FFF
-#define SCO_HDR_MASK_STATUS       0x3000
-#define SCO_STATUS_ALL_OK         0x0000
-#define SCO_STATUS_UNKNOWN        0x1000
-#define SCO_STATUS_NO_DATA        0x2000
-#define SCO_STATUS_SOME_DATA      0x3000
+#define SCO_HDR_MASK_CONN_ID 0x0FFF
+#define SCO_HDR_MASK_STATUS 0x3000
+#define SCO_STATUS_ALL_OK 0x0000
+#define SCO_STATUS_UNKNOWN 0x1000
+#define SCO_STATUS_NO_DATA 0x2000
+#define SCO_STATUS_SOME_DATA 0x3000
 
 struct hciEvtHdr {
 	uint8_t code;
 	uint8_t len;
 } __packed;
 
-
 void hci_cmd(uint8_t *hciCmdbuf);
 void hci_acl_to_host(uint8_t *data, uint16_t hdr, uint16_t len);
 void hci_acl_from_host(uint8_t *hciAclbuf);
diff --git a/include/btle_hci_int.h b/include/btle_hci_int.h
index 83fffee69f..ce3fd6ef41 100644
--- a/include/btle_hci_int.h
+++ b/include/btle_hci_int.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,377 +8,479 @@
  * original author.
  */
 
-
 #ifndef _HCI_INT_H_
 #define _HCI_INT_H_
 
 #include "util.h"
-#define HCI_DEV_NAME_LEN        248
-
-#define HCI_INQUIRY_LENGTH_UNIT                                  1280 /* msec */
-#define HCI_INQUIRY_LENGTH_MAX                                   48 /* units */
-
-#define HCI_LAP_Unlimited_Inquiry                                0x9E8B33
-#define HCI_LAP_Limited_Inquiry                                  0x9E8B00
-
-#define HCI_CLOCK_OFST_VALID                                     0x8000
-
-#define HCI_PKT_TYP_NO_2_DH1                                     0x0002 /* BT 2.1+ */
-#define HCI_PKT_TYP_NO_3_DH1                                     0x0004 /* BT 2.1+ */
-#define HCI_PKT_TYP_DM1                                          0x0008 /* BT 1.1+ */
-#define HCI_PKT_TYP_DH1                                          0x0010 /* BT 1.1+ */
-#define HCI_PKT_TYP_NO_2_DH3                                     0x0100 /* BT 2.1+ */
-#define HCI_PKT_TYP_NO_3_DH3                                     0x0200 /* BT 2.1+ */
-#define HCI_PKT_TYP_DM3                                          0x0400 /* BT 1.1+ */
-#define HCI_PKT_TYP_DH3                                          0x0800 /* BT 1.1+ */
-#define HCI_PKT_TYP_NO_2_DH5                                     0x1000 /* BT 2.1+ */
-#define HCI_PKT_TYP_NO_3_DH5                                     0x1000 /* BT 2.1+ */
-#define HCI_PKT_TYP_DM5                                          0x4000 /* BT 1.1+ */
-#define HCI_PKT_TYP_DH5                                          0x8000 /* BT 1.1+ */
-#define HCI_PKT_TYP_DEFAULT                                      0xCC18
-
-#define HCI_PKT_TYP_SCO_HV1                                      0x0001 /* BT 1.1+ */
-#define HCI_PKT_TYP_SCO_HV2                                      0x0002 /* BT 1.1+ */
-#define HCI_PKT_TYP_SCO_HV3                                      0x0004 /* BT 1.1+ */
-#define HCI_PKT_TYP_SCO_EV3                                      0x0008 /* BT 1.2+ */
-#define HCI_PKT_TYP_SCO_EV4                                      0x0010 /* BT 1.2+ */
-#define HCI_PKT_TYP_SCO_EV5                                      0x0020 /* BT 1.2+ */
-#define HCI_PKT_TYP_SCO_NO_2_EV3                                 0x0040 /* BT 2.1+ */
-#define HCI_PKT_TYP_SCO_NO_3_EV3                                 0x0080 /* BT 2.1+ */
-#define HCI_PKT_TYP_SCO_NO_2_EV5                                 0x0100 /* BT 2.1+ */
-#define HCI_PKT_TYP_SCO_NO_3_EV5                                 0x0200 /* BT 2.1+ */
-
-#define HCI_LINK_POLICY_DISABLE_ALL_LM_MODES                     0x0000
-#define HCI_LINK_POLICY_ENABLE_ROLESWITCH                        0x0001
-#define HCI_LINK_POLICY_ENABLE_HOLD_MODE                         0x0002
-#define HCI_LINK_POLICY_ENABLE_SNIFF_MODE                        0x0004
-#define HCI_LINK_POLICY_ENABLE_PARK_MODE                         0x0008
-
-#define HCI_FILTER_TYPE_CLEAR_ALL                                0x00 /* no subtypes, no data */
-#define HCI_FILTER_INQUIRY_RESULT                                0x01 /* below subtypes */
-#define HCI_FILTER_COND_TYPE_RETURN_ALL_DEVS                     0x00 /* no data */
-#define HCI_FILTER_COND_TYPE_SPECIFIC_DEV_CLS                    0x01 /* uint24_t wanted_class, uint24_t wanted_mask (only set bits are compared to wanted_class) */
-#define HCI_FILTER_COND_TYPE_SPECIFIC_ADDR                       0x02 /* uint8_t mac[6] */
-#define HCI_FILTER_CONNECTION_SETUP                              0x02 /* below subtypes */
-#define HCI_FILTER_COND_TYPE_ALLOW_CONNS_FROM_ALL_DEVS           0x00 /* uint8_t auto_accept_type: 1 - no, 2 - yes w/ no roleswitch, 3 - yes w/ roleswitch */
-#define HCI_FILTER_COND_TYPE_ALLOW_CONNS_FROM_SPECIFIC_DEV_CLS   0x01 /* uint24_t wanted_class, uint24_t wanted_mask (only set bits are compared to wanted_class), auto_accept flag same as above */
-#define HCI_FILTER_COND_TYPE_ALLOW_CONNS_FROM_SPECIFIC_ADDR      0x02 /* uint8_t mac[6], auto_accept flag same as above */
-
-#define HCI_SCAN_ENABLE_INQUIRY                                  0x01 /* discoverable */
-#define HCI_SCAN_ENABLE_PAGE                                     0x02 /* connectable */
-
-#define HCI_HOLD_MODE_SUSPEND_PAGE_SCAN                          0x01
-#define HCI_HOLD_MODE_SUSPEND_INQUIRY_SCAN                       0x02
-#define HCI_HOLD_MODE_SUSPEND_PERIODIC_INQUIRIES                 0x04
-
-#define HCI_TO_HOST_FLOW_CTRL_ACL                                0x01
-#define HCI_TO_HOST_FLOW_CTRL_SCO                                0x02
-
-#define HCI_INQ_MODE_STD                                         0 /* normal mode @ BT 1.1+ */
-#define HCI_INQ_MODE_RSSI                                        1 /* with RSSI   @ BT 1.2+ */
-#define HCI_INQ_MODE_EIR                                         2 /* with EIR    @ BT 2.1+ */
-
-#define HCI_SSP_KEY_ENTRY_STARTED                                0
-#define HCI_SSP_KEY_ENTRY_DIGIT_ENTERED                          1
-#define HCI_SSP_KEY_ENTRY_DIGIT_ERASED                           2
-#define HCI_SSP_KEY_ENTRY_CLEARED                                3
-#define HCI_SSP_KEY_ENTRY_COMPLETED                              4
-
-#define HCI_LOCATION_DOMAIN_OPTION_NONE                          0x20 /* ' ' */
-#define HCI_LOCATION_DOMAIN_OPTION_OUTDOORS_ONLY                 0x4F /* 'O' */
-#define HCI_LOCATION_DOMAIN_OPTION_INDOORS_ONLY                  0x49 /* 'I' */
-#define HCI_LOCATION_DOMAIN_OPTION_NON_COUNTRY_ENTITY            0x58 /* 'X' */
-
-#define HCI_PERIOD_TYPE_DOWNLINK                                 0x00
-#define HCI_PERIOD_TYPE_UPLINK                                   0x01
-#define HCI_PERIOD_TYPE_BIDIRECTIONAL                            0x02
-#define HCI_PERIOD_TYPE_GUARD_PERIOD                             0x03
-
-#define HCI_MWS_INTERVAL_TYPE_NO_RX_NO_TX                        0x00
-#define HCI_MWS_INTERVAL_TYPE_TX_ALLOWED                         0x01
-#define HCI_MWS_INTERVAL_TYPE_RX_ALLOWED                         0x02
-#define HCI_MWS_INTERVAL_TYPE_TX_RX_ALLOWED                      0x03
-#define HCI_MWS_INTERVAL_TYPE_FRAME                              0x04 /* type defined by Set External Frame Configuration command */
-
-#define HCI_CONNLESS_FRAG_TYPE_CONT                              0x00 /* continuation fragment */
-#define HCI_CONNLESS_FRAG_TYPE_START                             0x01 /* first fragment */
-#define HCI_CONNLESS_FRAG_TYPE_END                               0x02 /* last fragment */
-#define HCI_CONNLESS_FRAG_TYPE_COMPLETE                          0x03 /* complete fragment - no fragmentation */
-
-#define HCI_CUR_MODE_ACTIVE                                      0x00
-#define HCI_CUR_MODE_HOLD                                        0x01
-#define HCI_CUR_MODE_SNIFF                                       0x02
-#define HCI_CUR_MODE_PARK                                        0x03
-
-#define HCI_SCO_LINK_TYPE_SCO                                    0x00
-#define HCI_SCO_LINK_TYPE_ESCO                                   0x02
-
-#define HCI_SCO_AIR_MODE_MULAW                                   0x00
-#define HCI_SCO_AIR_MODE_ALAW                                    0x01
-#define HCI_SCO_AIR_MODE_CVSD                                    0x02
-#define HCI_SCO_AIR_MODE_TRANSPARENT                             0x03
-
-#define HCI_MCA_500_PPM                                          0x00
-#define HCI_MCA_250_PPM                                          0x01
-#define HCI_MCA_150_PPM                                          0x02
-#define HCI_MCA_100_PPM                                          0x03
-#define HCI_MCA_75_PPM                                           0x04
-#define HCI_MCA_50_PPM                                           0x05
-#define HCI_MCA_30_PPM                                           0x06
-#define HCI_MCA_20_PPM                                           0x07
-
-#define HCI_EDR_LINK_KEY_COMBO                                   0x00
-#define HCI_EDR_LINK_KEY_LOCAL                                   0x01
-#define HCI_EDR_LINK_KEY_REMOTE                                  0x02
-#define HCI_EDR_LINK_KEY_DEBUG                                   0x03
-#define HCI_EDR_LINK_KEY_UNAUTH_COMBO                            0x04
-#define HCI_EDR_LINK_KEY_AUTH_COMBO                              0x05
-#define HCI_EDR_LINK_KEY_CHANGED                                 0x06
-
-#define HCI_VERSION_1_0_B                                         0 /* BT 1.0b */
-#define HCI_VERSION_1_1                                           1 /* BT 1.1  */
-#define HCI_VERSION_1_2                                           2 /* BT 1.2  */
-#define HCI_VERSION_2_0                                           4 /* BT 2.0  */
-#define HCI_VERSION_2_1                                           3 /* BT 2.1  */
-#define HCI_VERSION_3_0                                           4 /* BT 3.0  */
-#define HCI_VERSION_4_0                                           6 /* BT 4.0  */
-#define HCI_VERSION_4_1                                           7 /* BT 4.1  */
-
-#define HCI_LE_STATE_NONCON_ADV                                  0x0000000000000001ULL /* BT 4.0+ */
-#define HCI_LE_STATE_SCANNABLE_ADV                               0x0000000000000002ULL /* BT 4.0+ */
-#define HCI_LE_STATE_CONNECTABLE_ADV                             0x0000000000000004ULL /* BT 4.0+ */
-#define HCI_LE_STATE_DIRECT_ADV                                  0x0000000000000008ULL /* BT 4.0+ */
-#define HCI_LE_STATE_PASSIVE_SCAN                                0x0000000000000010ULL /* BT 4.0+ */
-#define HCI_LE_STATE_ACTIVE_SCAN                                 0x0000000000000020ULL /* BT 4.0+ */
-#define HCI_LE_STATE_INITIATE                                    0x0000000000000040ULL /* BT 4.0+ */
-#define HCI_LE_STATE_SLAVE                                       0x0000000000000080ULL /* BT 4.0+ */
-#define HCI_LE_STATE_NONCON_ADV_w_PASSIVE_SCAN                   0x0000000000000100ULL /* BT 4.0+ */
-#define HCI_LE_STATE_SCANNABLE_ADV_w_PASSIVE_SCAN                0x0000000000000200ULL /* BT 4.0+ */
-#define HCI_LE_STATE_CONNECTABLE_ADV_w_PASSIVE_SCAN              0x0000000000000400ULL /* BT 4.0+ */
-#define HCI_LE_STATE_DIRECT_ADV_w_PASSIVE_SCAN                   0x0000000000000800ULL /* BT 4.0+ */
-#define HCI_LE_STATE_NONCON_ADV_w_ACTIVE_SCAN                    0x0000000000001000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_SCANNABLE_ADV_w_ACTIVE_SCAN                 0x0000000000002000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_CONNECTABLE_ADV_w_ACTIVE_SCAN               0x0000000000004000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_DIRECT_ADV_w_ACTIVE_SCAN                    0x0000000000008000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_NONCON_ADV_w_INITIATING                     0x0000000000010000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_SCANNABLE_ADV_w_INITIATING                  0x0000000000020000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_NONCON_ADV_w_MASTER                         0x0000000000040000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_SCANNABLE_ADV_w_MASTER                      0x0000000000080000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_NONCON_ADV_w_SLAVE                          0x0000000000100000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_SCANNABLE_ADV_w_SLAVE                       0x0000000000200000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_PASSIVE_SCAN_w_INITIATING                   0x0000000000400000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_ACTIVE_SCAN_w_INITIATING                    0x0000000000800000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_PASSIVE_SCAN_w_MASTER                       0x0000000001000000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_ACTIVE_SCAN_w_MASTER                        0x0000000002000000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_PASSIVE_SCAN_w_SLAVE                        0x0000000004000000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_ACTIVE_SCAN_w_SLAVE                         0x0000000008000000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_INTIATING_w_MASTER                          0x0000000010000000ULL /* BT 4.0+ */
-#define HCI_LE_STATE_LOW_DUTY_CYCLE_DIRECT_ADV                   0x0000000020000000ULL /* BT 4.1+ */
-#define HCI_LE_STATE_PASSIVE_SCAN_w_LOW_DUTY_CYCLE_DIRECT_ADV    0x0000000040000000ULL /* BT 4.1+ */
-#define HCI_LE_STATE_ACTIVE_SCAN_w_LOW_DUTY_CYCLE_DIRECT_ADV     0x0000000080000000ULL /* BT 4.1+ */
-#define HCI_LE_STATE_CONNECTABLE_ADV_w_INITIATING                0x0000000100000000ULL /* BT 4.1+ */
-#define HCI_LE_STATE_DIRECT_ADV_w_INITIATING                     0x0000000200000000ULL /* BT 4.1+ */
-#define HCI_LE_STATE_LOW_DUTY_CYCLE_DIRECT_ADV_w_INITIATING      0x0000000400000000ULL /* BT 4.1+ */
-#define HCI_LE_STATE_CONNECTABLE_ADV_w_MASTER                    0x0000000800000000ULL /* BT 4.1+ */
-#define HCI_LE_STATE_DIRECT_ADV_w_MASTER                         0x0000001000000000ULL /* BT 4.1+ */
-#define HCI_LE_STATE_LOW_DUTY_CYCLE_DIRECT_ADV_w_MASTER          0x0000002000000000ULL /* BT 4.1+ */
-#define HCI_LE_STATE_CONNECTABLE_ADV_w_SLAVE                     0x0000004000000000ULL /* BT 4.1+ */
-#define HCI_LE_STATE_DIRECT_ADV_w_SLAVE                          0x0000008000000000ULL /* BT 4.1+ */
-#define HCI_LE_STATE_LOW_DUTY_CYCLE_DIRECT_ADV_w_SLAVE           0x0000010000000000ULL /* BT 4.1+ */
-#define HCI_LE_STATE_INITIATING_w_SLAVE                          0x0000020000000000ULL /* BT 4.1+ */
-
-#define HCI_LMP_FTR_3_SLOT_PACKETS                               0x0000000000000001ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_5_SLOT_PACKETS                               0x0000000000000002ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_ENCRYPTION                                   0x0000000000000004ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_SLOT_OFFSET                                  0x0000000000000008ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_TIMING_ACCURACY                              0x0000000000000010ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_SWITCH                                       0x0000000000000020ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_HOLD_MODE                                    0x0000000000000040ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_SNIFF_MODE                                   0x0000000000000080ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_PARK_MODE                                    0x0000000000000100ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_RSSI                                         0x0000000000000200ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_CHANNEL_QUALITY_DRIVEN_DATA_RATE             0x0000000000000400ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_SCO_LINKS                                    0x0000000000000800ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_HV2_PACKETS                                  0x0000000000001000ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_HV3_PACKETS                                  0x0000000000002000ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_MU_LAW                                       0x0000000000004000ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_A_LAW                                        0x0000000000008000ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_CVSD                                         0x0000000000010000ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_PAGING_SCHEME                                0x0000000000020000ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_POWER_CONTROL                                0x0000000000040000ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_TRANSPARENT_SCO_DATA                         0x0000000000080000ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_FLOW_CONTROL_LAG_B0                          0x0000000000100000ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_FLOW_CONTROL_LAG_B1                          0x0000000000200000ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_FLOW_CONTROL_LAG_B2                          0x0000000000400000ULL /* BT 1.1+ */
-#define HCI_LMP_FTR_BROADCAST_ENCRYPTION                         0x0000000000800000ULL /* BT 1.2+ */
-#define HCI_LMP_FTR_ACL_2MBPS                                    0x0000000002000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_ACL_3MBPS                                    0x0000000004000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_ENHANCED_INQUIRY_SCAN                        0x0000000008000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_INTERLACED_INQUIRY_SCAN                      0x0000000010000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_INTERLACED_PAGE_SCAN                         0x0000000020000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_RSSI_WITH_INQUIRY_RESULTS                    0x0000000040000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_EXTENDED_SCO_LINK                            0x0000000080000000ULL /* BT 2.1+ */ /* EV3 packets */
-#define HCI_LMP_FTR_EV4_PACKETS                                  0x0000000100000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_EV5_PACKETS                                  0x0000000200000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_AFH_CAPABLE_SLAVE                            0x0000000800000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_AFH_CLASSIFICATION_SLAVE                     0x0000001000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_BR_EDR_NOT_SUPPORTED                         0x0000002000000000ULL /* BT 4.0+ */
-#define HCI_LMP_FTR_LE_SUPPORTED_CONTROLLER                      0x0000004000000000ULL /* BT 4.0+ */
-#define HCI_LMP_FTR_3_SLOT_ACL_PACKETS                           0x0000008000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_5_SLOT_ACL_PACKETS                           0x0000010000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_SNIFF_SUBRATING                              0x0000020000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_PAUSE_ENCRYPTION                             0x0000040000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_AFH_CAPABLE_MASTER                           0x0000080000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_AFH_CLASSIFICATION_MASTER                    0x0000100000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_ESCO_2MBPS                                   0x0000200000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_ESCO_3MBPS                                   0x0000400000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_3_SLOT_ESCO                                  0x0000800000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_EXTENDED_INQUIRY_RESPONSE                    0x0001000000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_SSP                                          0x0008000000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_ENCAPSULATED_PDU                             0x0010000000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_ERRONEOUS_DATA_REPORTING                     0x0020000000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_NON_FLUSHABLE_PACKET_BOUNDARY_FLAG           0x0040000000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_LINK_SUPERVISION_TIMEOUT_CHANGED_EVENT       0x0100000000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_INQUIRY_RESPONSE_TX_POWER_LEVEL              0x0200000000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_EXTENDED_FEATURES                            0x8000000000000000ULL /* BT 2.1+ */
-#define HCI_LMP_FTR_ENHANCED_POWER_CONTROL                       0x0400000000000000ULL /* BT 3.0+ */
-#define HCI_LMP_FTR_SIMUL_LE_EDR_CAPABLE_CONTROLLER              0x0002000000000000ULL /* BT 4.0+ */
-
-#define HCI_LMP_EXT_FTR_P1_SSP_HOST_SUPPORT                      0x0000000000000001ULL /* BT 2.1+ */
-#define HCI_LMP_EXT_FTR_P1_LE_HOST_SUPPORT                       0x0000000000000002ULL /* BT 4.0+ */
-#define HCI_LMP_EXT_FTR_P1_SIMUL_LE_EDR_HOST_SUPPORT             0x0000000000000004ULL /* BT 4.0+ */
-#define HCI_LMP_EXT_FTR_P1_SECURE_CONNECTIONS_HOST_SUPPORT       0x0000000000000008ULL /* BT 4.1+ */
-
-#define HCI_LMP_EXT_FTR_P2_CONNLESS_SLAVE_BROADCAST_MASTER       0x0000000000000001ULL /* BT 4.1+ */
-#define HCI_LMP_EXT_FTR_P2_CONNLESS_SLAVE_BROADCAST_SLAVE        0x0000000000000002ULL /* BT 4.1+ */
-#define HCI_LMP_EXT_FTR_P2_SYNCHRONIZATION_TRAIN                 0x0000000000000004ULL /* BT 4.1+ */
-#define HCI_LMP_EXT_FTR_P2_SYNCHRONIZATION_SCAN                  0x0000000000000008ULL /* BT 4.1+ */
-#define HCI_LMP_EXT_FTR_P2_INQUIRY_RESPONSE_NOTIFICATION_EVT     0x0000000000000010ULL /* BT 4.1+ */
-#define HCI_LMP_EXT_FTR_P2_GENERALIZED_INTERLACED_SCAN           0x0000000000000020ULL /* BT 4.1+ */
-#define HCI_LMP_EXT_FTR_P2_COARSE_CLOCK_ADJUSTMENT               0x0000000000000040ULL /* BT 4.1+ */
-#define HCI_LMP_EXT_FTR_P2_SECURE_CONNECTIONS_CAPABLE_CONTROLLER 0x0000000000000100ULL /* BT 4.1+ */
-#define HCI_LMP_EXT_FTR_P2_PING                                  0x0000000000000200ULL /* BT 4.1+ */
-#define HCI_LMP_EXT_FTR_P2_TRAIN_NUDGING                         0x0000000000000800ULL /* BT 4.1+ */
-
-#define HCI_EVENT_INQUIRY_COMPLETE                               0x0000000000000001ULL /* BT 1.1+ */
-#define HCI_EVENT_INQUIRY_RESULT                                 0x0000000000000002ULL /* BT 1.1+ */
-#define HCI_EVENT_CONN_COMPLETE                                  0x0000000000000004ULL /* BT 1.1+ */
-#define HCI_EVENT_CONN_REQUEST                                   0x0000000000000008ULL /* BT 1.1+ */
-#define HCI_EVENT_DISCONNECTION_COMPLETE                         0x0000000000000010ULL /* BT 1.1+ */
-#define HCI_EVENT_AUTH_COMPLETE                                  0x0000000000000020ULL /* BT 1.1+ */
-#define HCI_EVENT_REMOTE_NAME_REQUEST_COMPLETE                   0x0000000000000040ULL /* BT 1.1+ */
-#define HCI_EVENT_ENCR_CHANGE                                    0x0000000000000080ULL /* BT 1.1+ */
-#define HCI_EVENT_CHANGE_CONN_LINK_KEY_COMPLETE                  0x0000000000000100ULL /* BT 1.1+ */
-#define HCI_EVENT_MASTER_LINK_KEY_COMPLETE                       0x0000000000000200ULL /* BT 1.1+ */
-#define HCI_EVENT_READ_REMOTE_SUPPORTED_FEATURES_COMPLETE        0x0000000000000400ULL /* BT 1.1+ */
-#define HCI_EVENT_READ_REMOTE_VERSION_INFO_COMPLETE              0x0000000000000800ULL /* BT 1.1+ */
-#define HCI_EVENT_QOS_SETUP_COMPLETE                             0x0000000000001000ULL /* BT 1.1+ */
-#define HCI_EVENT_HARDWARE_ERROR                                 0x0000000000008000ULL /* BT 1.1+ */
-#define HCI_EVENT_FLUSH_OCCURRED                                 0x0000000000010000ULL /* BT 1.1+ */
-#define HCI_EVENT_ROLE_CHANGE                                    0x0000000000020000ULL /* BT 1.1+ */
-#define HCI_EVENT_MODE_CHANGE                                    0x0000000000080000ULL /* BT 1.1+ */
-#define HCI_EVENT_RETURN_LINK_KEYS                               0x0000000000100000ULL /* BT 1.1+ */
-#define HCI_EVENT_PIN_CODE_REQUEST                               0x0000000000200000ULL /* BT 1.1+ */
-#define HCI_EVENT_LINK_KEY_REQUEST                               0x0000000000400000ULL /* BT 1.1+ */
-#define HCI_EVENT_LINK_KEY_NOTIFICATION                          0x0000000000800000ULL /* BT 1.1+ */
-#define HCI_EVENT_LOOPBACK_COMMAND                               0x0000000001000000ULL /* BT 1.1+ */
-#define HCI_EVENT_DATA_BUFFER_OVERFLOW                           0x0000000002000000ULL /* BT 1.1+ */
-#define HCI_EVENT_MAX_SLOTS_CHANGE                               0x0000000004000000ULL /* BT 1.1+ */
-#define HCI_EVENT_READ_CLOCK_OFFSET_COMPLETE                     0x0000000008000000ULL /* BT 1.1+ */
-#define HCI_EVENT_CONN_PACKET_TYPE_CHANGED                       0x0000000010000000ULL /* BT 1.1+ */
-#define HCI_EVENT_QOS_VIOLATION                                  0x0000000020000000ULL /* BT 1.1+ */
-#define HCI_EVENT_PAGE_SCAN_MODE_CHANGE                          0x0000000040000000ULL /* BT 1.1+, obsolete @ BT1.2+ */
-#define HCI_EVENT_PAGE_SCAN_REPETITION_MODE_CHANGE               0x0000000080000000ULL /* BT 1.1+ */
-#define HCI_EVENT_ALL_BT_1_1                                     0x00000000FFFFFFFFULL /* also the default for BT 1.1 */
-#define HCI_EVENT_FLOW_SPEC_COMPLETE                             0x0000000100000000ULL /* BT 1.2+ */
-#define HCI_EVENT_INQUIRY_RESULT_WITH_RSSI                       0x0000000200000000ULL /* BT 1.2+ */
-#define HCI_EVENT_READ_REMOTE_EXTENDED_FEATURES_COMPLETE         0x0000000400000000ULL /* BT 1.2+ */
-#define HCI_EVENT_SYNC_CONN_COMPLETE                             0x0000080000000000ULL /* BT 1.2+ */
-#define HCI_EVENT_SYNC_CONN_CHANGED                              0x0000100000000000ULL /* BT 1.2+ */
-#define HCI_EVENT_ALL_BT_1_2                                     0x00001FFFFFFFFFFFULL /* also the default for BT 1.2+ */
-#define HCI_EVENT_SNIFF_SUBRATING                                0x0000200000000000ULL /* BT 2.1+ */
-#define HCI_EVENT_EXTENDED_INQUIRY_RESULT                        0x0000400000000000ULL /* BT 2.1+ */
-#define HCI_EVENT_ENCR_KEY_REFRESH_COMPLETE                      0x0000800000000000ULL /* BT 2.1+ */
-#define HCI_EVENT_IO_CAPABILITY_REQUEST                          0x0001000000000000ULL /* BT 2.1+ */
-#define HCI_EVENT_IO_CAPABILITY_REQUEST_REPLY                    0x0002000000000000ULL /* BT 2.1+ */
-#define HCI_EVENT_USER_CONFIRMATION_REQUEST                      0x0004000000000000ULL /* BT 2.1+ */
-#define HCI_EVENT_USER_PASSKEY_REQUEST                           0x0008000000000000ULL /* BT 2.1+ */
-#define HCI_EVENT_REMOTE_OOB_DATA_REQUEST                        0x0010000000000000ULL /* BT 2.1+ */
-#define HCI_EVENT_SIMPLE_PAIRING_COMPLETE                        0x0020000000000000ULL /* BT 2.1+ */
-#define HCI_EVENT_LINK_SUPERVISION_TIMOUT_CHANGED                0x0080000000000000ULL /* BT 2.1+ */
-#define HCI_EVENT_ENHANCED_FLUSH_COMPLETE                        0x0100000000000000ULL /* BT 2.1+ */
-#define HCI_EVENT_USER_PASSKEY_NOTIFICATION                      0x0400000000000000ULL /* BT 2.1+ */
-#define HCI_EVENT_KEYPRESS_NOTIFICATION                          0x0800000000000000ULL /* BT 2.1+ */
-#define HCI_EVENT_REMOTE_HOST_SUPPORTED_FEATURES                 0x1000000000000000ULL /* BT 2.1+ */
-#define HCI_EVENT_ALL_BT_2_1                                     0x1DBFFFFFFFFFFFFFULL
-#define HCI_EVENT_ALL_BT_3_0                                     0x1DBFFFFFFFFFFFFFULL
-#define HCI_EVENT_LE_META                                        0x2000000000000000ULL /* BT 4.0+ */
-#define HCI_EVENT_ALL_BT_4_0                                     0x3DBFFFFFFFFFFFFFULL
-#define HCI_EVENT_ALL_BT_4_1                                     0x3DBFFFFFFFFFFFFFULL
-
-#define HCI_EVENT_P2_PHYS_LINK_COMPLETE                          0x0000000000000001ULL /* BT 3.0+ */
-#define HCI_EVENT_P2_CHANNEL_SELECTED                            0x0000000000000002ULL /* BT 3.0+ */
-#define HCI_EVENT_P2_DISCONNECTION_PHYSICAL_LINK                 0x0000000000000004ULL /* BT 3.0+ */
-#define HCI_EVENT_P2_PHYSICAL_LINK_LOSS_EARLY_WARNING            0x0000000000000008ULL /* BT 3.0+ */
-#define HCI_EVENT_P2_PHYSICAL_LINK_RECOVERY                      0x0000000000000010ULL /* BT 3.0+ */
-#define HCI_EVENT_P2_LOGICAL_LINK_COMPLETE                       0x0000000000000020ULL /* BT 3.0+ */
-#define HCI_EVENT_P2_DISCONNECTION_LOGICAL_LINK_COMPLETE         0x0000000000000040ULL /* BT 3.0+ */
-#define HCI_EVENT_P2_FLOW_SPEC_MODIFY_COMPLETE                   0x0000000000000080ULL /* BT 3.0+ */
-#define HCI_EVENT_P2_NUMBER_OF_COMPLETED_DATA_BLOCKS             0x0000000000000100ULL /* BT 3.0+ */
-#define HCI_EVENT_P2_AMP_START_TEST                              0x0000000000000200ULL /* BT 3.0+ */
-#define HCI_EVENT_P2_AMP_TEST_END                                0x0000000000000400ULL /* BT 3.0+ */
-#define HCI_EVENT_P2_AMP_RECEIVER_REPORT                         0x0000000000000800ULL /* BT 3.0+ */
-#define HCI_EVENT_P2_SHORT_RANGE_MODE_CHANGE_COMPLETE            0x0000000000001000ULL /* BT 3.0+ */
-#define HCI_EVENT_P2_AMP_STATUS_CHANGE                           0x0000000000002000ULL /* BT 3.0+ */
-#define HCI_EVENT_P2_ALL_BT_3_0                                  0x0000000000003FFFULL
-#define HCI_EVENT_P2_ALL_BT_4_0                                  0x0000000000003FFFULL
-#define HCI_EVENT_P2_TRIGGERED_CLOCK_CAPTURE                     0x0000000000004000ULL /* BT 4.1+ */
-#define HCI_EVENT_P2_SYNCH_TRAIN_COMPLETE                        0x0000000000008000ULL /* BT 4.1+ */
-#define HCI_EVENT_P2_SYNCH_TRAIN_RECEIVED                        0x0000000000010000ULL /* BT 4.1+ */
-#define HCI_EVENT_P2_CONNLESS_SLAVE_BROADCAST_RXED               0x0000000000020000ULL /* BT 4.1+ */
-#define HCI_EVENT_P2_CONNLESS_SLAVE_BROADCAST_TIMEOUT            0x0000000000040000ULL /* BT 4.1+ */
-#define HCI_EVENT_P2_TRUNCATED_PAGE_COMPLETE                     0x0000000000080000ULL /* BT 4.1+ */
-#define HCI_EVENT_P2_SLAVE_PAGE_RESPONSE_TIMEOUT                 0x0000000000100000ULL /* BT 4.1+ */
-#define HCI_EVENT_P2_CONNLESS_SLAVE_BROADCAST_CHANNEL_MAP_CHANGE 0x0000000000200000ULL /* BT 4.1+ */
-#define HCI_EVENT_P2_INQUIRY_RESPONSE_NOTIFICATION               0x0000000000400000ULL /* BT 4.1+ */
-#define HCI_EVENT_P2_AUTHENTICATED_PAYLOAD_TIMEOUT_EXPIRED       0x0000000000800000ULL /* BT 4.1+ */
-#define HCI_EVENT_P2_ALL_BT_4_1                                  0x0000000000FFFFFFULL
-
-#define HCI_LE_EVENT_CONN_COMPLETE                               0x0000000000000001ULL /* BT 4.0+ */
-#define HCI_LE_EVENT_ADV_REPORT                                  0x0000000000000002ULL /* BT 4.0+ */
-#define HCI_LE_EVENT_CONN_UPDATE_COMPLETE                        0x0000000000000004ULL /* BT 4.0+ */
-#define HCI_LE_EVENT_READ_REMOTE_USED_FEATURES_CMPLETE           0x0000000000000008ULL /* BT 4.0+ */
-#define HCI_LE_EVENT_LTK_REQUEST                                 0x0000000000000010ULL /* BT 4.0+ */
-#define HCI_LE_EVENT_REMOTE_CONNECTION_PARAMETER_REQUEST         0x0000000000000020ULL /* BT 4.1+ */
-
-#define HCI_LE_FTR_ENCRYPTION                                    0x0000000000000001ULL /* BT 4.0+ */
-#define HCI_LE_FTR_CONNECTION_PARAMETERS_REQUEST                 0x0000000000000002ULL /* BT 4.1+ */
-#define HCI_LE_FTR_EXTENDED_REJECT_INDICATION                    0x0000000000000004ULL /* BT 4.1+ */
-#define HCI_LE_FTR_SLAVE_INITIATED_FEATURES_EXCHANGE             0x0000000000000008ULL /* BT 4.1+ */
-#define HCI_LE_FTR_LE_PING                                       0x0000000000000010ULL /* BT 4.1+ */
-
-
-
-
-
-#define HCI_OGF_Link_Control                                     1
-
+#define HCI_DEV_NAME_LEN 248
+
+#define HCI_INQUIRY_LENGTH_UNIT 1280 /* msec */
+#define HCI_INQUIRY_LENGTH_MAX 48 /* units */
+
+#define HCI_LAP_Unlimited_Inquiry 0x9E8B33
+#define HCI_LAP_Limited_Inquiry 0x9E8B00
+
+#define HCI_CLOCK_OFST_VALID 0x8000
+
+#define HCI_PKT_TYP_NO_2_DH1 0x0002 /* BT 2.1+ */
+#define HCI_PKT_TYP_NO_3_DH1 0x0004 /* BT 2.1+ */
+#define HCI_PKT_TYP_DM1 0x0008 /* BT 1.1+ */
+#define HCI_PKT_TYP_DH1 0x0010 /* BT 1.1+ */
+#define HCI_PKT_TYP_NO_2_DH3 0x0100 /* BT 2.1+ */
+#define HCI_PKT_TYP_NO_3_DH3 0x0200 /* BT 2.1+ */
+#define HCI_PKT_TYP_DM3 0x0400 /* BT 1.1+ */
+#define HCI_PKT_TYP_DH3 0x0800 /* BT 1.1+ */
+#define HCI_PKT_TYP_NO_2_DH5 0x1000 /* BT 2.1+ */
+#define HCI_PKT_TYP_NO_3_DH5 0x1000 /* BT 2.1+ */
+#define HCI_PKT_TYP_DM5 0x4000 /* BT 1.1+ */
+#define HCI_PKT_TYP_DH5 0x8000 /* BT 1.1+ */
+#define HCI_PKT_TYP_DEFAULT 0xCC18
+
+#define HCI_PKT_TYP_SCO_HV1 0x0001 /* BT 1.1+ */
+#define HCI_PKT_TYP_SCO_HV2 0x0002 /* BT 1.1+ */
+#define HCI_PKT_TYP_SCO_HV3 0x0004 /* BT 1.1+ */
+#define HCI_PKT_TYP_SCO_EV3 0x0008 /* BT 1.2+ */
+#define HCI_PKT_TYP_SCO_EV4 0x0010 /* BT 1.2+ */
+#define HCI_PKT_TYP_SCO_EV5 0x0020 /* BT 1.2+ */
+#define HCI_PKT_TYP_SCO_NO_2_EV3 0x0040 /* BT 2.1+ */
+#define HCI_PKT_TYP_SCO_NO_3_EV3 0x0080 /* BT 2.1+ */
+#define HCI_PKT_TYP_SCO_NO_2_EV5 0x0100 /* BT 2.1+ */
+#define HCI_PKT_TYP_SCO_NO_3_EV5 0x0200 /* BT 2.1+ */
+
+#define HCI_LINK_POLICY_DISABLE_ALL_LM_MODES 0x0000
+#define HCI_LINK_POLICY_ENABLE_ROLESWITCH 0x0001
+#define HCI_LINK_POLICY_ENABLE_HOLD_MODE 0x0002
+#define HCI_LINK_POLICY_ENABLE_SNIFF_MODE 0x0004
+#define HCI_LINK_POLICY_ENABLE_PARK_MODE 0x0008
+
+#define HCI_FILTER_TYPE_CLEAR_ALL 0x00 /* no subtypes, no data */
+#define HCI_FILTER_INQUIRY_RESULT 0x01 /* below subtypes */
+#define HCI_FILTER_COND_TYPE_RETURN_ALL_DEVS 0x00 /* no data */
+#define HCI_FILTER_COND_TYPE_SPECIFIC_DEV_CLS                                  \
+	0x01 /* uint24_t wanted_class, uint24_t wanted_mask (only set bits are \
+		compared to wanted_class) */
+#define HCI_FILTER_COND_TYPE_SPECIFIC_ADDR 0x02 /* uint8_t mac[6] */
+#define HCI_FILTER_CONNECTION_SETUP 0x02 /* below subtypes */
+#define HCI_FILTER_COND_TYPE_ALLOW_CONNS_FROM_ALL_DEVS                        \
+	0x00 /* uint8_t auto_accept_type: 1 - no, 2 - yes w/ no roleswitch, 3 \
+		- yes w/ roleswitch */
+#define HCI_FILTER_COND_TYPE_ALLOW_CONNS_FROM_SPECIFIC_DEV_CLS                 \
+	0x01 /* uint24_t wanted_class, uint24_t wanted_mask (only set bits are \
+		compared to wanted_class), auto_accept flag same as above */
+#define HCI_FILTER_COND_TYPE_ALLOW_CONNS_FROM_SPECIFIC_ADDR \
+	0x02 /* uint8_t mac[6], auto_accept flag same as above */
+
+#define HCI_SCAN_ENABLE_INQUIRY 0x01 /* discoverable */
+#define HCI_SCAN_ENABLE_PAGE 0x02 /* connectable */
+
+#define HCI_HOLD_MODE_SUSPEND_PAGE_SCAN 0x01
+#define HCI_HOLD_MODE_SUSPEND_INQUIRY_SCAN 0x02
+#define HCI_HOLD_MODE_SUSPEND_PERIODIC_INQUIRIES 0x04
+
+#define HCI_TO_HOST_FLOW_CTRL_ACL 0x01
+#define HCI_TO_HOST_FLOW_CTRL_SCO 0x02
+
+#define HCI_INQ_MODE_STD 0 /* normal mode @ BT 1.1+ */
+#define HCI_INQ_MODE_RSSI 1 /* with RSSI   @ BT 1.2+ */
+#define HCI_INQ_MODE_EIR 2 /* with EIR    @ BT 2.1+ */
+
+#define HCI_SSP_KEY_ENTRY_STARTED 0
+#define HCI_SSP_KEY_ENTRY_DIGIT_ENTERED 1
+#define HCI_SSP_KEY_ENTRY_DIGIT_ERASED 2
+#define HCI_SSP_KEY_ENTRY_CLEARED 3
+#define HCI_SSP_KEY_ENTRY_COMPLETED 4
+
+#define HCI_LOCATION_DOMAIN_OPTION_NONE 0x20 /* ' ' */
+#define HCI_LOCATION_DOMAIN_OPTION_OUTDOORS_ONLY 0x4F /* 'O' */
+#define HCI_LOCATION_DOMAIN_OPTION_INDOORS_ONLY 0x49 /* 'I' */
+#define HCI_LOCATION_DOMAIN_OPTION_NON_COUNTRY_ENTITY 0x58 /* 'X' */
+
+#define HCI_PERIOD_TYPE_DOWNLINK 0x00
+#define HCI_PERIOD_TYPE_UPLINK 0x01
+#define HCI_PERIOD_TYPE_BIDIRECTIONAL 0x02
+#define HCI_PERIOD_TYPE_GUARD_PERIOD 0x03
+
+#define HCI_MWS_INTERVAL_TYPE_NO_RX_NO_TX 0x00
+#define HCI_MWS_INTERVAL_TYPE_TX_ALLOWED 0x01
+#define HCI_MWS_INTERVAL_TYPE_RX_ALLOWED 0x02
+#define HCI_MWS_INTERVAL_TYPE_TX_RX_ALLOWED 0x03
+#define HCI_MWS_INTERVAL_TYPE_FRAME \
+	0x04 /* type defined by Set External Frame Configuration command */
+
+#define HCI_CONNLESS_FRAG_TYPE_CONT 0x00 /* continuation fragment */
+#define HCI_CONNLESS_FRAG_TYPE_START 0x01 /* first fragment */
+#define HCI_CONNLESS_FRAG_TYPE_END 0x02 /* last fragment */
+#define HCI_CONNLESS_FRAG_TYPE_COMPLETE \
+	0x03 /* complete fragment - no fragmentation */
+
+#define HCI_CUR_MODE_ACTIVE 0x00
+#define HCI_CUR_MODE_HOLD 0x01
+#define HCI_CUR_MODE_SNIFF 0x02
+#define HCI_CUR_MODE_PARK 0x03
+
+#define HCI_SCO_LINK_TYPE_SCO 0x00
+#define HCI_SCO_LINK_TYPE_ESCO 0x02
+
+#define HCI_SCO_AIR_MODE_MULAW 0x00
+#define HCI_SCO_AIR_MODE_ALAW 0x01
+#define HCI_SCO_AIR_MODE_CVSD 0x02
+#define HCI_SCO_AIR_MODE_TRANSPARENT 0x03
+
+#define HCI_MCA_500_PPM 0x00
+#define HCI_MCA_250_PPM 0x01
+#define HCI_MCA_150_PPM 0x02
+#define HCI_MCA_100_PPM 0x03
+#define HCI_MCA_75_PPM 0x04
+#define HCI_MCA_50_PPM 0x05
+#define HCI_MCA_30_PPM 0x06
+#define HCI_MCA_20_PPM 0x07
+
+#define HCI_EDR_LINK_KEY_COMBO 0x00
+#define HCI_EDR_LINK_KEY_LOCAL 0x01
+#define HCI_EDR_LINK_KEY_REMOTE 0x02
+#define HCI_EDR_LINK_KEY_DEBUG 0x03
+#define HCI_EDR_LINK_KEY_UNAUTH_COMBO 0x04
+#define HCI_EDR_LINK_KEY_AUTH_COMBO 0x05
+#define HCI_EDR_LINK_KEY_CHANGED 0x06
+
+#define HCI_VERSION_1_0_B 0 /* BT 1.0b */
+#define HCI_VERSION_1_1 1 /* BT 1.1  */
+#define HCI_VERSION_1_2 2 /* BT 1.2  */
+#define HCI_VERSION_2_0 4 /* BT 2.0  */
+#define HCI_VERSION_2_1 3 /* BT 2.1  */
+#define HCI_VERSION_3_0 4 /* BT 3.0  */
+#define HCI_VERSION_4_0 6 /* BT 4.0  */
+#define HCI_VERSION_4_1 7 /* BT 4.1  */
+
+#define HCI_LE_STATE_NONCON_ADV 0x0000000000000001ULL /* BT 4.0+ */
+#define HCI_LE_STATE_SCANNABLE_ADV 0x0000000000000002ULL /* BT 4.0+ */
+#define HCI_LE_STATE_CONNECTABLE_ADV 0x0000000000000004ULL /* BT 4.0+ */
+#define HCI_LE_STATE_DIRECT_ADV 0x0000000000000008ULL /* BT 4.0+ */
+#define HCI_LE_STATE_PASSIVE_SCAN 0x0000000000000010ULL /* BT 4.0+ */
+#define HCI_LE_STATE_ACTIVE_SCAN 0x0000000000000020ULL /* BT 4.0+ */
+#define HCI_LE_STATE_INITIATE 0x0000000000000040ULL /* BT 4.0+ */
+#define HCI_LE_STATE_SLAVE 0x0000000000000080ULL /* BT 4.0+ */
+#define HCI_LE_STATE_NONCON_ADV_w_PASSIVE_SCAN \
+	0x0000000000000100ULL /* BT 4.0+ */
+#define HCI_LE_STATE_SCANNABLE_ADV_w_PASSIVE_SCAN \
+	0x0000000000000200ULL /* BT 4.0+ */
+#define HCI_LE_STATE_CONNECTABLE_ADV_w_PASSIVE_SCAN \
+	0x0000000000000400ULL /* BT 4.0+ */
+#define HCI_LE_STATE_DIRECT_ADV_w_PASSIVE_SCAN \
+	0x0000000000000800ULL /* BT 4.0+ */
+#define HCI_LE_STATE_NONCON_ADV_w_ACTIVE_SCAN \
+	0x0000000000001000ULL /* BT 4.0+ */
+#define HCI_LE_STATE_SCANNABLE_ADV_w_ACTIVE_SCAN \
+	0x0000000000002000ULL /* BT 4.0+ */
+#define HCI_LE_STATE_CONNECTABLE_ADV_w_ACTIVE_SCAN \
+	0x0000000000004000ULL /* BT 4.0+ */
+#define HCI_LE_STATE_DIRECT_ADV_w_ACTIVE_SCAN \
+	0x0000000000008000ULL /* BT 4.0+ */
+#define HCI_LE_STATE_NONCON_ADV_w_INITIATING \
+	0x0000000000010000ULL /* BT 4.0+     \
+			       */
+#define HCI_LE_STATE_SCANNABLE_ADV_w_INITIATING \
+	0x0000000000020000ULL /* BT 4.0+ */
+#define HCI_LE_STATE_NONCON_ADV_w_MASTER 0x0000000000040000ULL /* BT 4.0+ */
+#define HCI_LE_STATE_SCANNABLE_ADV_w_MASTER \
+	0x0000000000080000ULL /* BT 4.0+    \
+			       */
+#define HCI_LE_STATE_NONCON_ADV_w_SLAVE 0x0000000000100000ULL /* BT 4.0+ */
+#define HCI_LE_STATE_SCANNABLE_ADV_w_SLAVE 0x0000000000200000ULL /* BT 4.0+ */
+#define HCI_LE_STATE_PASSIVE_SCAN_w_INITIATING \
+	0x0000000000400000ULL /* BT 4.0+ */
+#define HCI_LE_STATE_ACTIVE_SCAN_w_INITIATING \
+	0x0000000000800000ULL /* BT 4.0+ */
+#define HCI_LE_STATE_PASSIVE_SCAN_w_MASTER 0x0000000001000000ULL /* BT 4.0+ */
+#define HCI_LE_STATE_ACTIVE_SCAN_w_MASTER 0x0000000002000000ULL /* BT 4.0+ */
+#define HCI_LE_STATE_PASSIVE_SCAN_w_SLAVE 0x0000000004000000ULL /* BT 4.0+ */
+#define HCI_LE_STATE_ACTIVE_SCAN_w_SLAVE 0x0000000008000000ULL /* BT 4.0+ */
+#define HCI_LE_STATE_INTIATING_w_MASTER 0x0000000010000000ULL /* BT 4.0+ */
+#define HCI_LE_STATE_LOW_DUTY_CYCLE_DIRECT_ADV \
+	0x0000000020000000ULL /* BT 4.1+ */
+#define HCI_LE_STATE_PASSIVE_SCAN_w_LOW_DUTY_CYCLE_DIRECT_ADV \
+	0x0000000040000000ULL /* BT 4.1+ */
+#define HCI_LE_STATE_ACTIVE_SCAN_w_LOW_DUTY_CYCLE_DIRECT_ADV \
+	0x0000000080000000ULL /* BT 4.1+ */
+#define HCI_LE_STATE_CONNECTABLE_ADV_w_INITIATING \
+	0x0000000100000000ULL /* BT 4.1+ */
+#define HCI_LE_STATE_DIRECT_ADV_w_INITIATING \
+	0x0000000200000000ULL /* BT 4.1+     \
+			       */
+#define HCI_LE_STATE_LOW_DUTY_CYCLE_DIRECT_ADV_w_INITIATING \
+	0x0000000400000000ULL /* BT 4.1+ */
+#define HCI_LE_STATE_CONNECTABLE_ADV_w_MASTER \
+	0x0000000800000000ULL /* BT 4.1+ */
+#define HCI_LE_STATE_DIRECT_ADV_w_MASTER 0x0000001000000000ULL /* BT 4.1+ */
+#define HCI_LE_STATE_LOW_DUTY_CYCLE_DIRECT_ADV_w_MASTER \
+	0x0000002000000000ULL /* BT 4.1+ */
+#define HCI_LE_STATE_CONNECTABLE_ADV_w_SLAVE \
+	0x0000004000000000ULL /* BT 4.1+     \
+			       */
+#define HCI_LE_STATE_DIRECT_ADV_w_SLAVE 0x0000008000000000ULL /* BT 4.1+ */
+#define HCI_LE_STATE_LOW_DUTY_CYCLE_DIRECT_ADV_w_SLAVE \
+	0x0000010000000000ULL /* BT 4.1+ */
+#define HCI_LE_STATE_INITIATING_w_SLAVE 0x0000020000000000ULL /* BT 4.1+ */
+
+#define HCI_LMP_FTR_3_SLOT_PACKETS 0x0000000000000001ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_5_SLOT_PACKETS 0x0000000000000002ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_ENCRYPTION 0x0000000000000004ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_SLOT_OFFSET 0x0000000000000008ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_TIMING_ACCURACY 0x0000000000000010ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_SWITCH 0x0000000000000020ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_HOLD_MODE 0x0000000000000040ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_SNIFF_MODE 0x0000000000000080ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_PARK_MODE 0x0000000000000100ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_RSSI 0x0000000000000200ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_CHANNEL_QUALITY_DRIVEN_DATA_RATE \
+	0x0000000000000400ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_SCO_LINKS 0x0000000000000800ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_HV2_PACKETS 0x0000000000001000ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_HV3_PACKETS 0x0000000000002000ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_MU_LAW 0x0000000000004000ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_A_LAW 0x0000000000008000ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_CVSD 0x0000000000010000ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_PAGING_SCHEME 0x0000000000020000ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_POWER_CONTROL 0x0000000000040000ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_TRANSPARENT_SCO_DATA 0x0000000000080000ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_FLOW_CONTROL_LAG_B0 0x0000000000100000ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_FLOW_CONTROL_LAG_B1 0x0000000000200000ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_FLOW_CONTROL_LAG_B2 0x0000000000400000ULL /* BT 1.1+ */
+#define HCI_LMP_FTR_BROADCAST_ENCRYPTION 0x0000000000800000ULL /* BT 1.2+ */
+#define HCI_LMP_FTR_ACL_2MBPS 0x0000000002000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_ACL_3MBPS 0x0000000004000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_ENHANCED_INQUIRY_SCAN 0x0000000008000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_INTERLACED_INQUIRY_SCAN \
+	0x0000000010000000ULL /* BT 2.1+    \
+			       */
+#define HCI_LMP_FTR_INTERLACED_PAGE_SCAN 0x0000000020000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_RSSI_WITH_INQUIRY_RESULTS \
+	0x0000000040000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_EXTENDED_SCO_LINK \
+	0x0000000080000000ULL /* BT 2.1+ */ /* EV3 packets */
+#define HCI_LMP_FTR_EV4_PACKETS 0x0000000100000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_EV5_PACKETS 0x0000000200000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_AFH_CAPABLE_SLAVE 0x0000000800000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_AFH_CLASSIFICATION_SLAVE \
+	0x0000001000000000ULL /* BT 2.1+     \
+			       */
+#define HCI_LMP_FTR_BR_EDR_NOT_SUPPORTED 0x0000002000000000ULL /* BT 4.0+ */
+#define HCI_LMP_FTR_LE_SUPPORTED_CONTROLLER \
+	0x0000004000000000ULL /* BT 4.0+    \
+			       */
+#define HCI_LMP_FTR_3_SLOT_ACL_PACKETS 0x0000008000000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_5_SLOT_ACL_PACKETS 0x0000010000000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_SNIFF_SUBRATING 0x0000020000000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_PAUSE_ENCRYPTION 0x0000040000000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_AFH_CAPABLE_MASTER 0x0000080000000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_AFH_CLASSIFICATION_MASTER \
+	0x0000100000000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_ESCO_2MBPS 0x0000200000000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_ESCO_3MBPS 0x0000400000000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_3_SLOT_ESCO 0x0000800000000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_EXTENDED_INQUIRY_RESPONSE \
+	0x0001000000000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_SSP 0x0008000000000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_ENCAPSULATED_PDU 0x0010000000000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_ERRONEOUS_DATA_REPORTING \
+	0x0020000000000000ULL /* BT 2.1+     \
+			       */
+#define HCI_LMP_FTR_NON_FLUSHABLE_PACKET_BOUNDARY_FLAG \
+	0x0040000000000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_LINK_SUPERVISION_TIMEOUT_CHANGED_EVENT \
+	0x0100000000000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_INQUIRY_RESPONSE_TX_POWER_LEVEL \
+	0x0200000000000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_EXTENDED_FEATURES 0x8000000000000000ULL /* BT 2.1+ */
+#define HCI_LMP_FTR_ENHANCED_POWER_CONTROL 0x0400000000000000ULL /* BT 3.0+ */
+#define HCI_LMP_FTR_SIMUL_LE_EDR_CAPABLE_CONTROLLER \
+	0x0002000000000000ULL /* BT 4.0+ */
+
+#define HCI_LMP_EXT_FTR_P1_SSP_HOST_SUPPORT \
+	0x0000000000000001ULL /* BT 2.1+    \
+			       */
+#define HCI_LMP_EXT_FTR_P1_LE_HOST_SUPPORT 0x0000000000000002ULL /* BT 4.0+ */
+#define HCI_LMP_EXT_FTR_P1_SIMUL_LE_EDR_HOST_SUPPORT \
+	0x0000000000000004ULL /* BT 4.0+ */
+#define HCI_LMP_EXT_FTR_P1_SECURE_CONNECTIONS_HOST_SUPPORT \
+	0x0000000000000008ULL /* BT 4.1+ */
+
+#define HCI_LMP_EXT_FTR_P2_CONNLESS_SLAVE_BROADCAST_MASTER \
+	0x0000000000000001ULL /* BT 4.1+ */
+#define HCI_LMP_EXT_FTR_P2_CONNLESS_SLAVE_BROADCAST_SLAVE \
+	0x0000000000000002ULL /* BT 4.1+ */
+#define HCI_LMP_EXT_FTR_P2_SYNCHRONIZATION_TRAIN \
+	0x0000000000000004ULL /* BT 4.1+ */
+#define HCI_LMP_EXT_FTR_P2_SYNCHRONIZATION_SCAN \
+	0x0000000000000008ULL /* BT 4.1+ */
+#define HCI_LMP_EXT_FTR_P2_INQUIRY_RESPONSE_NOTIFICATION_EVT \
+	0x0000000000000010ULL /* BT 4.1+ */
+#define HCI_LMP_EXT_FTR_P2_GENERALIZED_INTERLACED_SCAN \
+	0x0000000000000020ULL /* BT 4.1+ */
+#define HCI_LMP_EXT_FTR_P2_COARSE_CLOCK_ADJUSTMENT \
+	0x0000000000000040ULL /* BT 4.1+ */
+#define HCI_LMP_EXT_FTR_P2_SECURE_CONNECTIONS_CAPABLE_CONTROLLER \
+	0x0000000000000100ULL /* BT 4.1+ */
+#define HCI_LMP_EXT_FTR_P2_PING 0x0000000000000200ULL /* BT 4.1+ */
+#define HCI_LMP_EXT_FTR_P2_TRAIN_NUDGING 0x0000000000000800ULL /* BT 4.1+ */
+
+#define HCI_EVENT_INQUIRY_COMPLETE 0x0000000000000001ULL /* BT 1.1+ */
+#define HCI_EVENT_INQUIRY_RESULT 0x0000000000000002ULL /* BT 1.1+ */
+#define HCI_EVENT_CONN_COMPLETE 0x0000000000000004ULL /* BT 1.1+ */
+#define HCI_EVENT_CONN_REQUEST 0x0000000000000008ULL /* BT 1.1+ */
+#define HCI_EVENT_DISCONNECTION_COMPLETE 0x0000000000000010ULL /* BT 1.1+ */
+#define HCI_EVENT_AUTH_COMPLETE 0x0000000000000020ULL /* BT 1.1+ */
+#define HCI_EVENT_REMOTE_NAME_REQUEST_COMPLETE \
+	0x0000000000000040ULL /* BT 1.1+ */
+#define HCI_EVENT_ENCR_CHANGE 0x0000000000000080ULL /* BT 1.1+ */
+#define HCI_EVENT_CHANGE_CONN_LINK_KEY_COMPLETE \
+	0x0000000000000100ULL /* BT 1.1+ */
+#define HCI_EVENT_MASTER_LINK_KEY_COMPLETE 0x0000000000000200ULL /* BT 1.1+ */
+#define HCI_EVENT_READ_REMOTE_SUPPORTED_FEATURES_COMPLETE \
+	0x0000000000000400ULL /* BT 1.1+ */
+#define HCI_EVENT_READ_REMOTE_VERSION_INFO_COMPLETE \
+	0x0000000000000800ULL /* BT 1.1+ */
+#define HCI_EVENT_QOS_SETUP_COMPLETE 0x0000000000001000ULL /* BT 1.1+ */
+#define HCI_EVENT_HARDWARE_ERROR 0x0000000000008000ULL /* BT 1.1+ */
+#define HCI_EVENT_FLUSH_OCCURRED 0x0000000000010000ULL /* BT 1.1+ */
+#define HCI_EVENT_ROLE_CHANGE 0x0000000000020000ULL /* BT 1.1+ */
+#define HCI_EVENT_MODE_CHANGE 0x0000000000080000ULL /* BT 1.1+ */
+#define HCI_EVENT_RETURN_LINK_KEYS 0x0000000000100000ULL /* BT 1.1+ */
+#define HCI_EVENT_PIN_CODE_REQUEST 0x0000000000200000ULL /* BT 1.1+ */
+#define HCI_EVENT_LINK_KEY_REQUEST 0x0000000000400000ULL /* BT 1.1+ */
+#define HCI_EVENT_LINK_KEY_NOTIFICATION 0x0000000000800000ULL /* BT 1.1+ */
+#define HCI_EVENT_LOOPBACK_COMMAND 0x0000000001000000ULL /* BT 1.1+ */
+#define HCI_EVENT_DATA_BUFFER_OVERFLOW 0x0000000002000000ULL /* BT 1.1+ */
+#define HCI_EVENT_MAX_SLOTS_CHANGE 0x0000000004000000ULL /* BT 1.1+ */
+#define HCI_EVENT_READ_CLOCK_OFFSET_COMPLETE \
+	0x0000000008000000ULL /* BT 1.1+     \
+			       */
+#define HCI_EVENT_CONN_PACKET_TYPE_CHANGED 0x0000000010000000ULL /* BT 1.1+ */
+#define HCI_EVENT_QOS_VIOLATION 0x0000000020000000ULL /* BT 1.1+ */
+#define HCI_EVENT_PAGE_SCAN_MODE_CHANGE \
+	0x0000000040000000ULL /* BT 1.1+, obsolete @ BT1.2+ */
+#define HCI_EVENT_PAGE_SCAN_REPETITION_MODE_CHANGE \
+	0x0000000080000000ULL /* BT 1.1+ */
+#define HCI_EVENT_ALL_BT_1_1 \
+	0x00000000FFFFFFFFULL /* also the default for BT 1.1 */
+#define HCI_EVENT_FLOW_SPEC_COMPLETE 0x0000000100000000ULL /* BT 1.2+ */
+#define HCI_EVENT_INQUIRY_RESULT_WITH_RSSI 0x0000000200000000ULL /* BT 1.2+ */
+#define HCI_EVENT_READ_REMOTE_EXTENDED_FEATURES_COMPLETE \
+	0x0000000400000000ULL /* BT 1.2+ */
+#define HCI_EVENT_SYNC_CONN_COMPLETE 0x0000080000000000ULL /* BT 1.2+ */
+#define HCI_EVENT_SYNC_CONN_CHANGED 0x0000100000000000ULL /* BT 1.2+ */
+#define HCI_EVENT_ALL_BT_1_2 \
+	0x00001FFFFFFFFFFFULL /* also the default for BT 1.2+ */
+#define HCI_EVENT_SNIFF_SUBRATING 0x0000200000000000ULL /* BT 2.1+ */
+#define HCI_EVENT_EXTENDED_INQUIRY_RESULT 0x0000400000000000ULL /* BT 2.1+ */
+#define HCI_EVENT_ENCR_KEY_REFRESH_COMPLETE \
+	0x0000800000000000ULL /* BT 2.1+    \
+			       */
+#define HCI_EVENT_IO_CAPABILITY_REQUEST 0x0001000000000000ULL /* BT 2.1+ */
+#define HCI_EVENT_IO_CAPABILITY_REQUEST_REPLY \
+	0x0002000000000000ULL /* BT 2.1+ */
+#define HCI_EVENT_USER_CONFIRMATION_REQUEST \
+	0x0004000000000000ULL /* BT 2.1+    \
+			       */
+#define HCI_EVENT_USER_PASSKEY_REQUEST 0x0008000000000000ULL /* BT 2.1+ */
+#define HCI_EVENT_REMOTE_OOB_DATA_REQUEST 0x0010000000000000ULL /* BT 2.1+ */
+#define HCI_EVENT_SIMPLE_PAIRING_COMPLETE 0x0020000000000000ULL /* BT 2.1+ */
+#define HCI_EVENT_LINK_SUPERVISION_TIMOUT_CHANGED \
+	0x0080000000000000ULL /* BT 2.1+ */
+#define HCI_EVENT_ENHANCED_FLUSH_COMPLETE 0x0100000000000000ULL /* BT 2.1+ */
+#define HCI_EVENT_USER_PASSKEY_NOTIFICATION \
+	0x0400000000000000ULL /* BT 2.1+    \
+			       */
+#define HCI_EVENT_KEYPRESS_NOTIFICATION 0x0800000000000000ULL /* BT 2.1+ */
+#define HCI_EVENT_REMOTE_HOST_SUPPORTED_FEATURES \
+	0x1000000000000000ULL /* BT 2.1+ */
+#define HCI_EVENT_ALL_BT_2_1 0x1DBFFFFFFFFFFFFFULL
+#define HCI_EVENT_ALL_BT_3_0 0x1DBFFFFFFFFFFFFFULL
+#define HCI_EVENT_LE_META 0x2000000000000000ULL /* BT 4.0+ */
+#define HCI_EVENT_ALL_BT_4_0 0x3DBFFFFFFFFFFFFFULL
+#define HCI_EVENT_ALL_BT_4_1 0x3DBFFFFFFFFFFFFFULL
+
+#define HCI_EVENT_P2_PHYS_LINK_COMPLETE 0x0000000000000001ULL /* BT 3.0+ */
+#define HCI_EVENT_P2_CHANNEL_SELECTED 0x0000000000000002ULL /* BT 3.0+ */
+#define HCI_EVENT_P2_DISCONNECTION_PHYSICAL_LINK \
+	0x0000000000000004ULL /* BT 3.0+ */
+#define HCI_EVENT_P2_PHYSICAL_LINK_LOSS_EARLY_WARNING \
+	0x0000000000000008ULL /* BT 3.0+ */
+#define HCI_EVENT_P2_PHYSICAL_LINK_RECOVERY \
+	0x0000000000000010ULL /* BT 3.0+    \
+			       */
+#define HCI_EVENT_P2_LOGICAL_LINK_COMPLETE 0x0000000000000020ULL /* BT 3.0+ */
+#define HCI_EVENT_P2_DISCONNECTION_LOGICAL_LINK_COMPLETE \
+	0x0000000000000040ULL /* BT 3.0+ */
+#define HCI_EVENT_P2_FLOW_SPEC_MODIFY_COMPLETE \
+	0x0000000000000080ULL /* BT 3.0+ */
+#define HCI_EVENT_P2_NUMBER_OF_COMPLETED_DATA_BLOCKS \
+	0x0000000000000100ULL /* BT 3.0+ */
+#define HCI_EVENT_P2_AMP_START_TEST 0x0000000000000200ULL /* BT 3.0+ */
+#define HCI_EVENT_P2_AMP_TEST_END 0x0000000000000400ULL /* BT 3.0+ */
+#define HCI_EVENT_P2_AMP_RECEIVER_REPORT 0x0000000000000800ULL /* BT 3.0+ */
+#define HCI_EVENT_P2_SHORT_RANGE_MODE_CHANGE_COMPLETE \
+	0x0000000000001000ULL /* BT 3.0+ */
+#define HCI_EVENT_P2_AMP_STATUS_CHANGE 0x0000000000002000ULL /* BT 3.0+ */
+#define HCI_EVENT_P2_ALL_BT_3_0 0x0000000000003FFFULL
+#define HCI_EVENT_P2_ALL_BT_4_0 0x0000000000003FFFULL
+#define HCI_EVENT_P2_TRIGGERED_CLOCK_CAPTURE \
+	0x0000000000004000ULL /* BT 4.1+     \
+			       */
+#define HCI_EVENT_P2_SYNCH_TRAIN_COMPLETE 0x0000000000008000ULL /* BT 4.1+ */
+#define HCI_EVENT_P2_SYNCH_TRAIN_RECEIVED 0x0000000000010000ULL /* BT 4.1+ */
+#define HCI_EVENT_P2_CONNLESS_SLAVE_BROADCAST_RXED \
+	0x0000000000020000ULL /* BT 4.1+ */
+#define HCI_EVENT_P2_CONNLESS_SLAVE_BROADCAST_TIMEOUT \
+	0x0000000000040000ULL /* BT 4.1+ */
+#define HCI_EVENT_P2_TRUNCATED_PAGE_COMPLETE \
+	0x0000000000080000ULL /* BT 4.1+     \
+			       */
+#define HCI_EVENT_P2_SLAVE_PAGE_RESPONSE_TIMEOUT \
+	0x0000000000100000ULL /* BT 4.1+ */
+#define HCI_EVENT_P2_CONNLESS_SLAVE_BROADCAST_CHANNEL_MAP_CHANGE \
+	0x0000000000200000ULL /* BT 4.1+ */
+#define HCI_EVENT_P2_INQUIRY_RESPONSE_NOTIFICATION \
+	0x0000000000400000ULL /* BT 4.1+ */
+#define HCI_EVENT_P2_AUTHENTICATED_PAYLOAD_TIMEOUT_EXPIRED \
+	0x0000000000800000ULL /* BT 4.1+ */
+#define HCI_EVENT_P2_ALL_BT_4_1 0x0000000000FFFFFFULL
+
+#define HCI_LE_EVENT_CONN_COMPLETE 0x0000000000000001ULL /* BT 4.0+ */
+#define HCI_LE_EVENT_ADV_REPORT 0x0000000000000002ULL /* BT 4.0+ */
+#define HCI_LE_EVENT_CONN_UPDATE_COMPLETE 0x0000000000000004ULL /* BT 4.0+ */
+#define HCI_LE_EVENT_READ_REMOTE_USED_FEATURES_CMPLETE \
+	0x0000000000000008ULL /* BT 4.0+ */
+#define HCI_LE_EVENT_LTK_REQUEST 0x0000000000000010ULL /* BT 4.0+ */
+#define HCI_LE_EVENT_REMOTE_CONNECTION_PARAMETER_REQUEST \
+	0x0000000000000020ULL /* BT 4.1+ */
+
+#define HCI_LE_FTR_ENCRYPTION 0x0000000000000001ULL /* BT 4.0+ */
+#define HCI_LE_FTR_CONNECTION_PARAMETERS_REQUEST \
+	0x0000000000000002ULL /* BT 4.1+ */
+#define HCI_LE_FTR_EXTENDED_REJECT_INDICATION \
+	0x0000000000000004ULL /* BT 4.1+ */
+#define HCI_LE_FTR_SLAVE_INITIATED_FEATURES_EXCHANGE \
+	0x0000000000000008ULL /* BT 4.1+ */
+#define HCI_LE_FTR_LE_PING 0x0000000000000010ULL /* BT 4.1+ */
+
+#define HCI_OGF_Link_Control 1
 
 /* ==== BT 1.1 ==== */
 
-#define HCI_CMD_Inquiry                                          0x0001 /* status */
+#define HCI_CMD_Inquiry 0x0001 /* status */
 struct hciInquiry {
 	uint8_t lap[3];
 	uint8_t inqLen;
 	uint8_t numResp;
 } __packed;
 
-#define HCI_CMD_Inquiry_Cancel                                   0x0002 /* complete */
+#define HCI_CMD_Inquiry_Cancel 0x0002 /* complete */
 struct hciCmplInquiryCancel {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Periodic_Inquiry_Mode                            0x0003 /* complete */
+#define HCI_CMD_Periodic_Inquiry_Mode 0x0003 /* complete */
 struct hciPeriodicInquiryMode {
 	uint16_t maxPeriodLen;
 	uint16_t minPeriodLen;
@@ -390,10 +492,9 @@ struct hciCmplPeriodicInquiryMode {
 	uint8_t status;
 } __packed;
 
+#define HCI_CMD_Exit_Periodic_Inquiry_Mode 0x0004 /* complete */
 
-#define HCI_CMD_Exit_Periodic_Inquiry_Mode                       0x0004 /* complete */
-
-#define HCI_CMD_Create_Connection                                0x0005 /* status */
+#define HCI_CMD_Create_Connection 0x0005 /* status */
 struct hciCreateConnection {
 	uint8_t mac[6];
 	uint16_t allowedPackets; /* HCI_PKT_TYP_* */
@@ -402,19 +503,20 @@ struct hciCreateConnection {
 	uint8_t allowRoleSwitch;
 } __packed;
 
-#define HCI_CMD_Disconnect                                       0x0006 /* status */
+#define HCI_CMD_Disconnect 0x0006 /* status */
 struct hciDisconnect {
 	uint16_t conn;
 	uint8_t reason;
 } __packed;
 
-#define HCI_CMD_Add_SCO_Connection                               0x0007 /* status */ /* deprecated in BT 1.2+ */
+#define HCI_CMD_Add_SCO_Connection \
+	0x0007 /* status */ /* deprecated in BT 1.2+ */
 struct hciAddScoConnection {
 	uint16_t conn;
 	uint16_t packetTypes; /* HCI_PKT_TYP_SCO_* */
 } __packed;
 
-#define HCI_CMD_Create_Connection_Cancel                         0x0008 /* complete */
+#define HCI_CMD_Create_Connection_Cancel 0x0008 /* complete */
 struct hciCreateConnectionCancel {
 	uint8_t mac[6];
 } __packed;
@@ -423,19 +525,19 @@ struct hciCmplCreateConnectionCancel {
 	uint8_t mac[6];
 } __packed;
 
-#define HCI_CMD_Accept_Connection_Request                        0x0009 /* status */
+#define HCI_CMD_Accept_Connection_Request 0x0009 /* status */
 struct hciAcceptConnection {
 	uint8_t mac[6];
 	uint8_t remainSlave;
 } __packed;
 
-#define HCI_CMD_Reject_Connection_Request                        0x000A /* status */
+#define HCI_CMD_Reject_Connection_Request 0x000A /* status */
 struct hciRejectConnection {
 	uint8_t mac[6];
 	uint8_t reason;
 } __packed;
 
-#define HCI_CMD_Link_Key_Request_Reply                           0x000B /* complete */
+#define HCI_CMD_Link_Key_Request_Reply 0x000B /* complete */
 struct hciLinkKeyRequestReply {
 	uint8_t mac[6];
 	uint8_t key[16];
@@ -445,7 +547,7 @@ struct hciCmplLinkKeyRequestReply {
 	uint8_t mac[6];
 } __packed;
 
-#define HCI_CMD_Link_Key_Request_Negative_Reply                  0x000C /* complete */
+#define HCI_CMD_Link_Key_Request_Negative_Reply 0x000C /* complete */
 struct hciLinkKeyRequestNegativeReply {
 	uint8_t mac[6];
 } __packed;
@@ -454,7 +556,7 @@ struct hciCmplLinkKeyRequestNegativeReply {
 	uint8_t mac[6];
 } __packed;
 
-#define HCI_CMD_PIN_Code_Request_Reply                           0x000D /* complete */
+#define HCI_CMD_PIN_Code_Request_Reply 0x000D /* complete */
 struct hciPinCodeRequestReply {
 	uint8_t mac[6];
 	uint8_t pinCodeLen;
@@ -465,7 +567,7 @@ struct hciCmplPinCodeRequestReply {
 	uint8_t mac[6];
 } __packed;
 
-#define HCI_CMD_PIN_Code_Request_Negative_Reply                  0x000E /* complete */
+#define HCI_CMD_PIN_Code_Request_Negative_Reply 0x000E /* complete */
 struct hciPinCodeRequestNegativeReply {
 	uint8_t mac[6];
 } __packed;
@@ -474,34 +576,34 @@ struct hciCmplPinCodeRequestNegativeReply {
 	uint8_t mac[6];
 } __packed;
 
-#define HCI_CMD_Change_Connection_Packet_Type                    0x000F /* status */
+#define HCI_CMD_Change_Connection_Packet_Type 0x000F /* status */
 struct hciChangeConnectionPacketType {
 	uint16_t conn;
 	uint16_t allowedPackets; /* HCI_PKT_TYP_* */
 } __packed;
 
-#define HCI_CMD_Authentication_Requested                         0x0011 /* status */
+#define HCI_CMD_Authentication_Requested 0x0011 /* status */
 struct hciAuthRequested {
 	uint16_t conn;
 } __packed;
 
-#define HCI_CMD_Set_Connection_Encryption                        0x0013 /* status */
+#define HCI_CMD_Set_Connection_Encryption 0x0013 /* status */
 struct hciSetConnectionEncryption {
 	uint16_t conn;
 	uint8_t encrOn;
 } __packed;
 
-#define HCI_CMD_Change_Connection_Link_Key                       0x0015 /* status */
+#define HCI_CMD_Change_Connection_Link_Key 0x0015 /* status */
 struct hciChangeConnLinkKey {
 	uint16_t conn;
 } __packed;
 
-#define HCI_CMD_Master_Link_Key                                  0x0017 /* status */
+#define HCI_CMD_Master_Link_Key 0x0017 /* status */
 struct hciMasterLinkKey {
 	uint8_t useTempKey;
 } __packed;
 
-#define HCI_CMD_Remote_Name_Request                              0x0019 /* status */
+#define HCI_CMD_Remote_Name_Request 0x0019 /* status */
 struct hciRemoteNameRequest {
 	uint8_t mac[6];
 	uint8_t PSRM;
@@ -509,7 +611,7 @@ struct hciRemoteNameRequest {
 	uint16_t clockOffset; /* possibly | HCI_CLOCK_OFST_VALID */
 } __packed;
 
-#define HCI_CMD_Remote_Name_Request_Cancel                       0x001A /* complete */
+#define HCI_CMD_Remote_Name_Request_Cancel 0x001A /* complete */
 struct hciRemoteNameRequestCancel {
 	uint8_t mac[6];
 } __packed;
@@ -518,31 +620,30 @@ struct hciCmplRemoteNameRequestCancel {
 	uint8_t mac[6];
 } __packed;
 
-#define HCI_CMD_Read_Remote_Supported_Features                   0x001B /* status */
+#define HCI_CMD_Read_Remote_Supported_Features 0x001B /* status */
 struct hciReadRemoteSupportedFeatures {
 	uint16_t conn;
 } __packed;
 
-#define HCI_CMD_Read_Remote_Version_Information                  0x001D /* status */
+#define HCI_CMD_Read_Remote_Version_Information 0x001D /* status */
 struct hciReadRemoteVersionInfo {
 	uint16_t conn;
 } __packed;
 
-#define HCI_CMD_Read_Clock_Offset                                0x001F /* status */
+#define HCI_CMD_Read_Clock_Offset 0x001F /* status */
 struct hciReadClockOffset {
 	uint16_t conn;
 } __packed;
 
-
 /* ==== BT 1.2 ==== */
 
-#define HCI_CMD_Read_Remote_Extended_Features                    0x001C /* status */
+#define HCI_CMD_Read_Remote_Extended_Features 0x001C /* status */
 struct hciReadRemoteExtendedFeatures {
 	uint16_t conn;
 	uint8_t page; /* BT1.2 max: 0 */
 } __packed;
 
-#define HCI_CMD_Read_Lmp_Handle                                  0x0020 /* complete */
+#define HCI_CMD_Read_Lmp_Handle 0x0020 /* complete */
 struct hciReadLmpHandle {
 	uint16_t handle;
 } __packed;
@@ -553,7 +654,7 @@ struct hciCmplReadLmpHandle {
 	uint32_t reserved;
 } __packed;
 
-#define HCI_CMD_Setup_Synchronous_Connection                     0x0028 /* status */
+#define HCI_CMD_Setup_Synchronous_Connection 0x0028 /* status */
 struct hciSetupSyncConn {
 	uint16_t conn;
 	uint32_t txBandwidth;
@@ -564,7 +665,7 @@ struct hciSetupSyncConn {
 	uint16_t allowedPacketsSco; /* HCI_PKT_TYP_SCO_* */
 } __packed;
 
-#define HCI_CMD_Accept_Synchronous_Connection_Request            0x0029 /* status */
+#define HCI_CMD_Accept_Synchronous_Connection_Request 0x0029 /* status */
 struct hciAcceptSyncConn {
 	uint8_t mac[6];
 	uint32_t txBandwidth;
@@ -575,16 +676,15 @@ struct hciAcceptSyncConn {
 	uint16_t allowedPacketsSco; /* HCI_PKT_TYP_SCO_* */
 } __packed;
 
-#define HCI_CMD_Reject_Synchronous_Connection_Request            0x002A /* status */
+#define HCI_CMD_Reject_Synchronous_Connection_Request 0x002A /* status */
 struct hciRejectSyncConn {
 	uint8_t mac[6];
 	uint8_t reason;
 } __packed;
 
-
 /* ==== BR 2.1 ==== */
 
-#define HCI_CMD_IO_Capability_Request_Reply                      0x002B /* complete */
+#define HCI_CMD_IO_Capability_Request_Reply 0x002B /* complete */
 struct hciIoCapabilityRequestReply {
 	uint8_t mac[6];
 	uint8_t cap; /* HCI_DISPLAY_CAP_* */
@@ -596,7 +696,7 @@ struct hciCmplIoCapabilityRequestReply {
 	uint8_t mac[6];
 } __packed;
 
-#define HCI_CMD_User_Confirmation_Request_Reply                  0x002C /* complete */
+#define HCI_CMD_User_Confirmation_Request_Reply 0x002C /* complete */
 struct hciUserConfRequestReply {
 	uint8_t mac[6];
 } __packed;
@@ -605,7 +705,7 @@ struct hciCmplUserConfRequestReply {
 	uint8_t mac[6];
 } __packed;
 
-#define HCI_CMD_User_Confirmation_Request_Negative_Reply         0x002D /* complete */
+#define HCI_CMD_User_Confirmation_Request_Negative_Reply 0x002D /* complete */
 struct hciUserConfRequestNegativeReply {
 	uint8_t mac[6];
 } __packed;
@@ -614,7 +714,7 @@ struct hciCmplUserConfRequestNegativeReply {
 	uint8_t mac[6];
 } __packed;
 
-#define HCI_CMD_User_Passkey_Request_Reply                       0x002E /* complete */
+#define HCI_CMD_User_Passkey_Request_Reply 0x002E /* complete */
 struct hciUserPasskeyRequestReply {
 	uint8_t mac[6];
 	uint32_t num;
@@ -624,7 +724,7 @@ struct hciCmplUserPasskeyRequestReply {
 	uint8_t mac[6];
 } __packed;
 
-#define HCI_CMD_User_Passkey_Request_Negative_Reply              0x002F /* complete */
+#define HCI_CMD_User_Passkey_Request_Negative_Reply 0x002F /* complete */
 struct hciUserPasskeyRequestNegativeReply {
 	uint8_t mac[6];
 } __packed;
@@ -633,7 +733,7 @@ struct hciCmplUserPasskeyRequestNegativeReply {
 	uint8_t mac[6];
 } __packed;
 
-#define HCI_CMD_Remote_OOB_Data_Request_Reply                    0x0030 /* complete */
+#define HCI_CMD_Remote_OOB_Data_Request_Reply 0x0030 /* complete */
 struct hciRemoteOobDataRequestReply {
 	uint8_t mac[6];
 	uint8_t C[16];
@@ -644,7 +744,7 @@ struct hciCmplRemoteOobDataRequestReply {
 	uint8_t mac[6];
 } __packed;
 
-#define HCI_CMD_Remote_OOB_Data_Request_Negative_Reply           0x0033 /* complete */
+#define HCI_CMD_Remote_OOB_Data_Request_Negative_Reply 0x0033 /* complete */
 struct hciRemoteOobDataRequestNegativeReply {
 	uint8_t mac[6];
 } __packed;
@@ -653,7 +753,7 @@ struct hciCmplRemoteOobDataRequestNegativeReply {
 	uint8_t mac[6];
 } __packed;
 
-#define HCI_CMD_IO_Capability_Request_Negative_Reply             0x0034 /* complete */
+#define HCI_CMD_IO_Capability_Request_Negative_Reply 0x0034 /* complete */
 struct hciIoCapabilityRequestNegativeReply {
 	uint8_t mac[6];
 	uint8_t reason;
@@ -663,10 +763,9 @@ struct hciCmplIoCapabilityRequestNegativeReply {
 	uint8_t mac[6];
 } __packed;
 
-
 /* ==== BT 3.0 ==== */
 
-#define HCI_CMD_Create_Physical_link                             0x0035 /* status */
+#define HCI_CMD_Create_Physical_link 0x0035 /* status */
 struct hciCreatePhysicalLink {
 	uint8_t physLinkHandle;
 	uint8_t dedicatedAmpKeyLength;
@@ -674,7 +773,7 @@ struct hciCreatePhysicalLink {
 	uint8_t dedicatedAmpKey;
 } __packed;
 
-#define HCI_CMD_Accept_Physical_link                             0x0036 /* status */
+#define HCI_CMD_Accept_Physical_link 0x0036 /* status */
 struct hciAcceptPhysicalLink {
 	uint8_t physLinkHandle;
 	uint8_t dedicatedAmpKeyLength;
@@ -682,32 +781,32 @@ struct hciAcceptPhysicalLink {
 	uint8_t dedicatedAmpKey;
 } __packed;
 
-#define HCI_CMD_Disconnect_Physical_link                         0x0037 /* status */
+#define HCI_CMD_Disconnect_Physical_link 0x0037 /* status */
 struct hciDisconnectPhysicalLink {
 	uint8_t physLinkHandle;
 	uint8_t reason;
 } __packed;
 
-#define HCI_CMD_Create_Logical_link                              0x0038 /* status */
+#define HCI_CMD_Create_Logical_link 0x0038 /* status */
 struct hciCreateLogicalLink {
 	uint8_t physLinkHandle;
 	uint8_t txFlowSpec[16];
 	uint8_t rxFlowSpec[16];
 } __packed;
 
-#define HCI_CMD_Accept_Logical_Link                              0x0039 /* status */
+#define HCI_CMD_Accept_Logical_Link 0x0039 /* status */
 struct hciAcceptLogicalLink {
 	uint8_t physLinkHandle;
 	uint8_t txFlowSpec[16];
 	uint8_t rxFlowSpec[16];
 } __packed;
 
-#define HCI_CMD_Disconnect_Logical_link                          0x003A /* status */
+#define HCI_CMD_Disconnect_Logical_link 0x003A /* status */
 struct hciDisconnectLogicalLink {
 	uint8_t physLinkHandle;
 } __packed;
 
-#define HCI_CMD_Logical_Link_Cancel                              0x003B /* complete */
+#define HCI_CMD_Logical_Link_Cancel 0x003B /* complete */
 struct hciLogicalLinkCancel {
 	uint8_t physLinkHandle;
 	uint8_t txFlowSpecID;
@@ -718,17 +817,16 @@ struct hciCmplLogicalLinkCancel {
 	uint8_t txFlowSpecID;
 } __packed;
 
-#define HCI_CMD_Flow_Spec_Modify                                 0x003C /* status */
+#define HCI_CMD_Flow_Spec_Modify 0x003C /* status */
 struct hciFlowSpecModify {
 	uint16_t handle;
 	uint8_t txFlowSpec[16];
 	uint8_t rxFlowSpec[16];
 } __packed;
 
-
 /* ==== BT 4.1 ==== */
 
-#define HCI_CMD_Enhanced_Setup_Synchronous_Connection            0x003D /* status */
+#define HCI_CMD_Enhanced_Setup_Synchronous_Connection 0x003D /* status */
 struct hciEnhSetupSyncConn {
 	uint16_t conn;
 	uint32_t txBandwidth;
@@ -756,7 +854,7 @@ struct hciEnhSetupSyncConn {
 	uint8_t retransmissionEffort;
 } __packed;
 
-#define HCI_CMD_Enhanced_Accept_Synchronous_Connection           0x003E /* status */
+#define HCI_CMD_Enhanced_Accept_Synchronous_Connection 0x003E /* status */
 struct hciEnhAcceptSyncConn {
 	uint8_t mac[6];
 	uint32_t txBandwidth;
@@ -784,14 +882,14 @@ struct hciEnhAcceptSyncConn {
 	uint8_t retransmissionEffort;
 } __packed;
 
-#define HCI_CMD_Truncated_Page                                   0x003F /* status */
+#define HCI_CMD_Truncated_Page 0x003F /* status */
 struct hciTruncatedPage {
 	uint8_t mac[6];
 	uint8_t PSRM;
 	uint16_t clockOffset; /* possibly | HCI_CLOCK_OFST_VALID */
 } __packed;
 
-#define HCI_CMD_Truncated_Page_Cancel                            0x0040 /* complete */
+#define HCI_CMD_Truncated_Page_Cancel 0x0040 /* complete */
 struct hciTruncatedPageCancel {
 	uint8_t mac[6];
 } __packed;
@@ -800,7 +898,7 @@ struct hciCmplTruncatedPageCancel {
 	uint8_t mac[6];
 } __packed;
 
-#define HCI_CMD_Set_Connectionless_Slave_Broadcast               0x0041 /* complete */
+#define HCI_CMD_Set_Connectionless_Slave_Broadcast 0x0041 /* complete */
 struct hciSetConnectionlessSlaveBroadcast {
 	uint8_t enabled;
 	uint8_t ltAddr; /* 1..7 */
@@ -816,7 +914,9 @@ struct hciCmplSetConnectionlessSlaveBroadcast {
 	uint16_t interval;
 } __packed;
 
-#define HCI_CMD_Set_Connectionless_Slave_Broadcast_Receive       0x0042 /* complete */
+#define HCI_CMD_Set_Connectionless_Slave_Broadcast_Receive \
+	0x0042 /* complete                                 \
+		*/
 struct hciSetConnectionlessSlaveBroadcastReceive {
 	uint8_t enabled;
 	uint8_t mac[6]; /* add rof tranmitter */
@@ -836,9 +936,9 @@ struct hciCmplSetConnectionlessSlaveBroadcastReceive {
 	uint8_t ltAddr; /* 1..7 */
 } __packed;
 
-#define HCI_CMD_Start_Synchronisation_Train                      0x0043 /* status */
+#define HCI_CMD_Start_Synchronisation_Train 0x0043 /* status */
 
-#define HCI_CMD_Receive_Synchronisation_Train                    0x0044 /* status */
+#define HCI_CMD_Receive_Synchronisation_Train 0x0044 /* status */
 struct hciReceiveSyncTrain {
 	uint8_t mac[6];
 	uint16_t syncScanTimeout;
@@ -846,7 +946,7 @@ struct hciReceiveSyncTrain {
 	uint16_t syncScanInterval;
 } __packed;
 
-#define HCI_CMD_Remote_OOB_Extended_Data_Request_Reply           0x0045 /* complete */
+#define HCI_CMD_Remote_OOB_Extended_Data_Request_Reply 0x0045 /* complete */
 struct hciRemoteOobExtendedDataRequestReply {
 	uint8_t mac[6];
 	uint8_t C_192[16];
@@ -859,23 +959,18 @@ struct hciCmplRemoteOobExtendedDataRequestReply {
 	uint8_t mac[6];
 } __packed;
 
-
-
-
-
-#define HCI_OGF_Link_Policy                                      2
-
+#define HCI_OGF_Link_Policy 2
 
 /* ==== BT 1.1 ==== */
 
-#define HCI_CMD_Hold_Mode                                        0x0001 /* status */
+#define HCI_CMD_Hold_Mode 0x0001 /* status */
 struct hciHoldMode {
 	uint16_t conn;
 	uint16_t holdModeMaxInt;
 	uint16_t holdModeMinInt;
 } __packed;
 
-#define HCI_CMD_Sniff_Mode                                       0x0003 /* status */
+#define HCI_CMD_Sniff_Mode 0x0003 /* status */
 struct hciSniffMode {
 	uint16_t conn;
 	uint16_t sniffMaxInt;
@@ -884,24 +979,24 @@ struct hciSniffMode {
 	uint16_t sniffTimeout;
 } __packed;
 
-#define HCI_CMD_Exit_Sniff_Mode                                  0x0004 /* status */
+#define HCI_CMD_Exit_Sniff_Mode 0x0004 /* status */
 struct hciExitSniffMode {
 	uint16_t conn;
 } __packed;
 
-#define HCI_CMD_Park_State                                       0x0005 /* status */
+#define HCI_CMD_Park_State 0x0005 /* status */
 struct hciParkState {
 	uint16_t conn;
 	uint16_t beaconMaxInt;
 	uint16_t beaconMinInt;
 } __packed;
 
-#define HCI_CMD_Exit_Park_State                                  0x0006 /* status */
+#define HCI_CMD_Exit_Park_State 0x0006 /* status */
 struct hciExitParkState {
 	uint16_t conn;
 } __packed;
 
-#define HCI_CMD_QoS_Setup                                        0x0007 /* status */
+#define HCI_CMD_QoS_Setup 0x0007 /* status */
 struct hisQosSetup {
 	uint16_t conn;
 	uint8_t flags;
@@ -912,7 +1007,7 @@ struct hisQosSetup {
 	uint32_t delayVariation;
 } __packed;
 
-#define HCI_CMD_Role_Discovery                                   0x0009 /* complete */
+#define HCI_CMD_Role_Discovery 0x0009 /* complete */
 struct hciRoleDiscovery {
 	uint16_t conn;
 } __packed;
@@ -920,13 +1015,13 @@ struct hciCmplRoleDiscovery {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Switch_Role                                      0x000B /* status */
+#define HCI_CMD_Switch_Role 0x000B /* status */
 struct hciSwitchRole {
 	uint8_t mac[6];
 	uint8_t becomeSlave;
 } __packed;
 
-#define HCI_CMD_Read_Link_Policy_Settings                        0x000C /* complete */
+#define HCI_CMD_Read_Link_Policy_Settings 0x000C /* complete */
 struct hciReadLinkPolicySettings {
 	uint16_t conn;
 } __packed;
@@ -936,7 +1031,7 @@ struct hciCmplReadLinkPolicySettings {
 	uint16_t policy; /* HCI_LINK_POLICY_* */
 } __packed;
 
-#define HCI_CMD_Write_Link_Policy_Settings                       0x000D /* complete */
+#define HCI_CMD_Write_Link_Policy_Settings 0x000D /* complete */
 struct hciWriteLinkPolicySettings {
 	uint16_t conn;
 	uint16_t policy; /* HCI_LINK_POLICY_* */
@@ -946,16 +1041,15 @@ struct hciCmplWriteLinkPolicySettings {
 	uint16_t conn;
 } __packed;
 
-
 /* ==== BT 1.2 ==== */
 
-#define HCI_CMD_Read_Default_Link_Policy_Settings                0x000E /* complete */
+#define HCI_CMD_Read_Default_Link_Policy_Settings 0x000E /* complete */
 struct hciCmplReadDefaultLinkPolicySettings {
 	uint8_t status;
 	uint16_t policy; /* HCI_LINK_POLICY_* */
 } __packed;
 
-#define HCI_CMD_Write_Default_Link_Policy_Settings               0x000F /* complete */
+#define HCI_CMD_Write_Default_Link_Policy_Settings 0x000F /* complete */
 struct hciWriteDefaultLinkPolicySettings {
 	uint16_t policy; /* HCI_LINK_POLICY_* */
 } __packed;
@@ -963,7 +1057,7 @@ struct hciCmplWriteDefaultLinkPolicySettings {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Flow_Specification                               0x0010 /* status */
+#define HCI_CMD_Flow_Specification 0x0010 /* status */
 struct hisFlowSpecification {
 	uint16_t conn;
 	uint8_t flags;
@@ -975,10 +1069,9 @@ struct hisFlowSpecification {
 	uint32_t accessLatency;
 } __packed;
 
-
 /* ==== BT 2.1 ==== */
 
-#define HCI_CMD_Sniff_Subrating                                  0x0011 /* complete */
+#define HCI_CMD_Sniff_Subrating 0x0011 /* complete */
 struct hciSniffSubrating {
 	uint16_t conn;
 	uint16_t maxLatency;
@@ -990,16 +1083,11 @@ struct hciCmplSniffSubrating {
 	uint16_t conn;
 } __packed;
 
-
-
-
-
-#define HCI_OGF_Controller_and_Baseband                          3
-
+#define HCI_OGF_Controller_and_Baseband 3
 
 /* ==== BT 1.1 ==== */
 
-#define HCI_CMD_Set_Event_Mask                                   0x0001 /* complete */
+#define HCI_CMD_Set_Event_Mask 0x0001 /* complete */
 struct hciSetEventMask {
 	uint64_t mask; /* bitmask of HCI_EVENT_* */
 } __packed;
@@ -1007,12 +1095,12 @@ struct hciCmplSetEventMask {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Reset                                            0x0003 /* complete */
+#define HCI_CMD_Reset 0x0003 /* complete */
 struct hciCmplReset {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Set_Event_Filter                                 0x0005 /* complete */
+#define HCI_CMD_Set_Event_Filter 0x0005 /* complete */
 struct hciSetEventFilter {
 	uint8_t filterType; /* HCI_FILTER_TYPE_* */
 	/* more things are optional here */
@@ -1021,7 +1109,7 @@ struct hciCmplSetEventFiler {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Flush                                            0x0008 /* complete */
+#define HCI_CMD_Flush 0x0008 /* complete */
 struct hciFlush {
 	uint16_t conn;
 } __packed;
@@ -1030,13 +1118,13 @@ struct hciCmplFlush {
 	uint16_t conn;
 } __packed;
 
-#define HCI_CMD_Read_PIN_Type                                    0x0009 /* complete */
+#define HCI_CMD_Read_PIN_Type 0x0009 /* complete */
 struct hciCmplReadPinType {
 	uint8_t status;
 	uint8_t isFixed;
 } __packed;
 
-#define HCI_CMD_Write_PIN_Type                                   0x000A /* complete */
+#define HCI_CMD_Write_PIN_Type 0x000A /* complete */
 struct hciWritePinType {
 	uint8_t isFixed;
 } __packed;
@@ -1044,12 +1132,12 @@ struct hciCmplWritePinType {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Create_New_Unit_Key                              0x000B /* complete */
+#define HCI_CMD_Create_New_Unit_Key 0x000B /* complete */
 struct hciCmplCreateNewUnitKey {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Stored_Link_Key                             0x000D /* complete */
+#define HCI_CMD_Read_Stored_Link_Key 0x000D /* complete */
 struct hciReadStoredLinkKey {
 	uint8_t mac[6];
 	uint8_t readAll;
@@ -1060,7 +1148,7 @@ struct hciCmplReadStoredLinkKey {
 	uint16_t numKeysRead;
 } __packed;
 
-#define HCI_CMD_Write_Stored_Link_Key                            0x0011 /* complete */
+#define HCI_CMD_Write_Stored_Link_Key 0x0011 /* complete */
 struct hciWriteStoredLinkKeyItem {
 	uint8_t mac[6];
 	uint8_t key[16];
@@ -1074,7 +1162,7 @@ struct hciCmplWriteStoredLinkKey {
 	uint8_t numKeysWritten;
 } __packed;
 
-#define HCI_CMD_Delete_Stored_Link_Key                           0x0012 /* complete */
+#define HCI_CMD_Delete_Stored_Link_Key 0x0012 /* complete */
 struct hciDeleteStoredLinkKey {
 	uint8_t mac[6];
 	uint8_t deleteAll;
@@ -1084,7 +1172,7 @@ struct hciCmplDeleteStoredLinkKey {
 	uint8_t numKeysDeleted;
 } __packed;
 
-#define HCI_CMD_Write_Local_Name                                 0x0013 /* complete */
+#define HCI_CMD_Write_Local_Name 0x0013 /* complete */
 struct hciWriteLocalName {
 	char name[HCI_DEV_NAME_LEN];
 } __packed;
@@ -1092,19 +1180,19 @@ struct hciCmplWriteLocalName {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Local_Name                                  0x0014 /* complete */
+#define HCI_CMD_Read_Local_Name 0x0014 /* complete */
 struct hciCmplReadLocalName {
 	uint8_t status;
 	char name[HCI_DEV_NAME_LEN];
 } __packed;
 
-#define HCI_CMD_Read_Connection_Accept_Timeout                   0x0015 /* complete */
+#define HCI_CMD_Read_Connection_Accept_Timeout 0x0015 /* complete */
 struct hciCmplReadConnAcceptTimeout {
 	uint8_t status;
 	uint16_t timeout; /* in units of 0.625ms 1..0xB540 */
 } __packed;
 
-#define HCI_CMD_Write_Connection_Accept_Timeout                  0x0016 /* complete */
+#define HCI_CMD_Write_Connection_Accept_Timeout 0x0016 /* complete */
 struct hciWriteConnAcceptTimeout {
 	uint16_t timeout; /* in units of 0.625ms 1..0xB540 */
 } __packed;
@@ -1112,13 +1200,13 @@ struct hciCmplWriteConnAcceptTimeout {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Page_Timeout                                0x0017 /* complete */
+#define HCI_CMD_Read_Page_Timeout 0x0017 /* complete */
 struct hciCmplReadPageTimeout {
 	uint8_t status;
 	uint16_t timeout;
 } __packed;
 
-#define HCI_CMD_Write_Page_Timeout                               0x0018 /* complete */
+#define HCI_CMD_Write_Page_Timeout 0x0018 /* complete */
 struct hciWritePageTimeout {
 	uint16_t timeout;
 } __packed;
@@ -1126,13 +1214,13 @@ struct hciCmplWritePageTimeout {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Scan_Enable                                 0x0019 /* complete */
+#define HCI_CMD_Read_Scan_Enable 0x0019 /* complete */
 struct hciCmplReadScanEnable {
 	uint8_t status;
 	uint8_t state; /* bitmask of HCI_SCAN_ENABLE_* */
 } __packed;
 
-#define HCI_CMD_Write_Scan_Enable                                0x001A /* complete */
+#define HCI_CMD_Write_Scan_Enable 0x001A /* complete */
 struct hciWriteScanEnable {
 	uint8_t state; /* bitmask of HCI_SCAN_ENABLE_* */
 } __packed;
@@ -1140,14 +1228,14 @@ struct hciCmplWriteScanEnable {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Page_Scan_Activity                          0x001B /* complete */
+#define HCI_CMD_Read_Page_Scan_Activity 0x001B /* complete */
 struct hciCmplReadPageScanActivity {
 	uint8_t status;
 	uint16_t scanInterval;
 	uint16_t scanWindow;
 } __packed;
 
-#define HCI_CMD_Write_Page_Scan_Activity                         0x001C /* complete */
+#define HCI_CMD_Write_Page_Scan_Activity 0x001C /* complete */
 struct hciWritePageScanActivity {
 	uint16_t scanInterval;
 	uint16_t scanWindow;
@@ -1156,14 +1244,14 @@ struct hciCmplWritePageScanActivity {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Inquiry_Scan_Activity                       0x001D /* complete */
+#define HCI_CMD_Read_Inquiry_Scan_Activity 0x001D /* complete */
 struct hciCmplReadInquiryScanActivity {
 	uint8_t status;
 	uint16_t scanInterval;
 	uint16_t scanWindow;
 } __packed;
 
-#define HCI_CMD_Write_Inquiry_Scan_Activity                      0x001E /* complete */
+#define HCI_CMD_Write_Inquiry_Scan_Activity 0x001E /* complete */
 struct hciWriteInquiryScanActivity {
 	uint16_t scanInterval;
 	uint16_t scanWindow;
@@ -1172,13 +1260,13 @@ struct hciCmplWriteInquiryScanActivity {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Authentication_Enable                       0x001F /* complete */
+#define HCI_CMD_Read_Authentication_Enable 0x001F /* complete */
 struct hciCmplReadAuthEnable {
 	uint8_t status;
 	uint8_t authRequired;
 } __packed;
 
-#define HCI_CMD_Write_Authentication_Enable                      0x0020 /* complete */
+#define HCI_CMD_Write_Authentication_Enable 0x0020 /* complete */
 struct hciWriteAuthEnable {
 	uint8_t authRequired;
 } __packed;
@@ -1186,13 +1274,15 @@ struct hciCmplWriteAuthEnable {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Encryption_Mode                             0x0021 /* complete *//* deprecated in BT 2.1+ */
+#define HCI_CMD_Read_Encryption_Mode \
+	0x0021 /* complete */ /* deprecated in BT 2.1+ */
 struct hciCmplReadEncryptionMode {
 	uint8_t status;
 	uint8_t encrRequired;
 } __packed;
 
-#define HCI_CMD_Write_Encryption_Mode                            0x0022 /* complete *//* deprecated in BT 2.1+ */
+#define HCI_CMD_Write_Encryption_Mode \
+	0x0022 /* complete */ /* deprecated in BT 2.1+ */
 struct hciWriteEncryptionMode {
 	uint8_t encrRequired;
 } __packed;
@@ -1200,13 +1290,13 @@ struct hciCmplWriteEncryptionMode {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Class_Of_Device                             0x0023 /* complete */
+#define HCI_CMD_Read_Class_Of_Device 0x0023 /* complete */
 struct hciCmplReadClassOfDevice {
 	uint8_t status;
 	uint8_t cls[3];
 } __packed;
 
-#define HCI_CMD_Write_Class_Of_Device                            0x0024 /* complete */
+#define HCI_CMD_Write_Class_Of_Device 0x0024 /* complete */
 struct hciWriteClassOfDevice {
 	uint8_t cls[3];
 } __packed;
@@ -1214,13 +1304,13 @@ struct hciCmplWriteClassOfDevice {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Voice_Setting                               0x0025 /* complete */
+#define HCI_CMD_Read_Voice_Setting 0x0025 /* complete */
 struct hciCmplReadVoiceSetting {
 	uint8_t status;
 	uint16_t voiceSetting;
 } __packed;
 
-#define HCI_CMD_Write_Voice_Setting                              0x0026 /* complete */
+#define HCI_CMD_Write_Voice_Setting 0x0026 /* complete */
 struct hciWriteVoiceSetting {
 	uint16_t voiceSetting;
 } __packed;
@@ -1228,7 +1318,7 @@ struct hciCmplWriteVoiceSetting {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Automatic_Flush_Timeout                     0x0027 /* complete */
+#define HCI_CMD_Read_Automatic_Flush_Timeout 0x0027 /* complete */
 struct hciReadAutoFlushTimeout {
 	uint16_t conn;
 } __packed;
@@ -1238,7 +1328,7 @@ struct hciCmplReadAutoFlushTimeout {
 	uint16_t timeout;
 } __packed;
 
-#define HCI_CMD_Write_Automatic_Flush_Timeout                    0x0028 /* complete */
+#define HCI_CMD_Write_Automatic_Flush_Timeout 0x0028 /* complete */
 struct hciWriteAutoFlushTimeout {
 	uint16_t conn;
 	uint16_t timeout;
@@ -1248,13 +1338,13 @@ struct hciCmplWriteAutoFlushTimeout {
 	uint16_t conn;
 } __packed;
 
-#define HCI_CMD_Read_Num_Broadcast_Retransmissions               0x0029 /* complete */
+#define HCI_CMD_Read_Num_Broadcast_Retransmissions 0x0029 /* complete */
 struct hciCmplReadNumBroadcastRetransmissions {
 	uint8_t status;
 	uint8_t numRetransmissions; /* 0 .. 0xFE => 1 .. 255 TXes */
 } __packed;
 
-#define HCI_CMD_Write_Num_Broadcast_Retransmissions              0x002A /* complete */
+#define HCI_CMD_Write_Num_Broadcast_Retransmissions 0x002A /* complete */
 struct hciWriteNumBroadcastRetransmissions {
 	uint8_t numRetransmissions; /* 0 .. 0xFE => 1 .. 255 TXes */
 } __packed;
@@ -1262,13 +1352,13 @@ struct hciCmplWriteNumBroadcastRetransmissions {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Hold_Mode_Activity                          0x002B /* complete */
+#define HCI_CMD_Read_Hold_Mode_Activity 0x002B /* complete */
 struct hciCmplReadHoldModeActivity {
 	uint8_t status;
 	uint8_t holdModeActivity; /* bitfield if HCI_HOLD_MODE_SUSPEND_* */
 } __packed;
 
-#define HCI_CMD_Write_Hold_Mode_Activity                         0x002C /* complete */
+#define HCI_CMD_Write_Hold_Mode_Activity 0x002C /* complete */
 struct hciWriteHoldModeActivity {
 	uint8_t holdModeActivity; /* bitfield if HCI_HOLD_MODE_SUSPEND_* */
 } __packed;
@@ -1276,7 +1366,7 @@ struct hciCmplWriteHoldModeActivity {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Transmit_Power_Level                        0x002D /* complete */
+#define HCI_CMD_Read_Transmit_Power_Level 0x002D /* complete */
 struct hciReadTransmitPowerLevel {
 	uint16_t conn;
 	uint8_t max; /* else current */
@@ -1287,13 +1377,13 @@ struct hciCmplReadTransmitPowerLevel {
 	uint8_t txPower; /* actually an int8_t */
 } __packed;
 
-#define HCI_CMD_Read_SCO_Flow_Control_Enable                     0x002E /* complete */
+#define HCI_CMD_Read_SCO_Flow_Control_Enable 0x002E /* complete */
 struct hciCmplReadSyncFlowCtrl {
 	uint8_t status;
 	uint8_t syncFlowCtrlOn;
 } __packed;
 
-#define HCI_CMD_Write_SCO_Flow_Control_Enable                    0x002F /* complete */
+#define HCI_CMD_Write_SCO_Flow_Control_Enable 0x002F /* complete */
 struct hciWriteSyncFlowCtrlEnable {
 	uint8_t syncFlowCtrlOn;
 } __packed;
@@ -1301,7 +1391,7 @@ struct hciCmplWriteSyncFlowCtrlEnable {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Set_Controller_To_Host_Flow_Control              0x0031 /* complete */
+#define HCI_CMD_Set_Controller_To_Host_Flow_Control 0x0031 /* complete */
 struct hciSetControllerToHostFlowControl {
 	uint8_t chipToHostFlowCtrl; /* bitmask of HCI_TO_HOST_FLOW_CTRL_* */
 } __packed;
@@ -1309,7 +1399,7 @@ struct hciCmplSetControllerToHostFlowControl {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Host_Buffer_Size                                 0x0033 /* complete */
+#define HCI_CMD_Host_Buffer_Size 0x0033 /* complete */
 struct hciHostBufferSize {
 	uint16_t maxAclPacket;
 	uint8_t maxScoPacket;
@@ -1320,7 +1410,9 @@ struct hciCmplHostBufferSize {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Host_Number_Of_Completed_Packets                 0x0035 /* special: can be sent anytime (not subj to cmd flow control), does not generate events unless error */
+#define HCI_CMD_Host_Number_Of_Completed_Packets                               \
+	0x0035 /* special: can be sent anytime (not subj to cmd flow control), \
+		  does not generate events unless error */
 struct hciHostNumberOfCompletedPacketsItem {
 	uint16_t conn;
 	uint16_t numCompletedPackets;
@@ -1330,33 +1422,35 @@ struct hciHostNumberOfCompletedPackets {
 	struct hciHostNumberOfCompletedPacketsItem items[];
 } __packed;
 
-#define HCI_CMD_Read_Link_Supervision_Timeout                    0x0036 /* complete */
+#define HCI_CMD_Read_Link_Supervision_Timeout 0x0036 /* complete */
 struct hciReadLinkSupervisionTimeout {
 	uint16_t conn;
 } __packed;
 struct hciCmplReadLinkSupervisionTimeout {
 	uint8_t status;
 	uint16_t conn;
-	uint16_t timeout; /* in units of 0.625ms allowed: 1..0xffff, required support 0x0190 - 0xffff */
+	uint16_t timeout; /* in units of 0.625ms allowed: 1..0xffff, required
+			     support 0x0190 - 0xffff */
 } __packed;
 
-#define HCI_CMD_Write_Link_Supervision_Timeout                   0x0037 /* complete */
+#define HCI_CMD_Write_Link_Supervision_Timeout 0x0037 /* complete */
 struct hciWriteLinkSupervisionTimeout {
 	uint16_t conn;
-	uint16_t timeout; /* in units of 0.625ms allowed: 1..0xffff, required support 0x0190 - 0xffff */
+	uint16_t timeout; /* in units of 0.625ms allowed: 1..0xffff, required
+			     support 0x0190 - 0xffff */
 } __packed;
 struct hciCmplWriteLinkSupervisionTimeout {
 	uint8_t status;
 	uint16_t conn;
 } __packed;
 
-#define HCI_CMD_Read_Number_Of_Supported_IAC                     0x0038 /* complete */
+#define HCI_CMD_Read_Number_Of_Supported_IAC 0x0038 /* complete */
 struct hciCmplReadNumberOfSupportedIac {
 	uint8_t status;
 	uint8_t numSupportedIac;
 } __packed;
 
-#define HCI_CMD_Read_Current_IAC_LAP                             0x0039 /* complete */
+#define HCI_CMD_Read_Current_IAC_LAP 0x0039 /* complete */
 struct hciCmplReadCurrentIacItem {
 	uint8_t iac_lap[3];
 } __packed;
@@ -1366,7 +1460,7 @@ struct hciCmplReadCurrentIac {
 	struct hciCmplReadCurrentIacItem items[];
 } __packed;
 
-#define HCI_CMD_Write_Current_IAC_LAP                            0x003A /* complete */
+#define HCI_CMD_Write_Current_IAC_LAP 0x003A /* complete */
 struct hciWriteCurrentIacLapItem {
 	uint8_t iacLap[3];
 } __packed;
@@ -1378,13 +1472,13 @@ struct hciCmplWriteCurrentIacLap {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Page_Scan_Period_Mode                       0x003B /* complete */
+#define HCI_CMD_Read_Page_Scan_Period_Mode 0x003B /* complete */
 struct hciCmplReadPageScanPeriodMode {
 	uint8_t status;
 	uint8_t mode;
 } __packed;
 
-#define HCI_CMD_Write_Page_Scan_Period_Mode                      0x003C /* complete */
+#define HCI_CMD_Write_Page_Scan_Period_Mode 0x003C /* complete */
 struct hciWritePageScanPeriodMode {
 	uint8_t mode;
 } __packed;
@@ -1392,13 +1486,15 @@ struct hciCmplWritePageScanPeriodMode {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Page_Scan_Mode                              0x003D  /* complete *//* deprecated in BT 1.2+ */
+#define HCI_CMD_Read_Page_Scan_Mode \
+	0x003D /* complete */ /* deprecated in BT 1.2+ */
 struct hciCmplReadPageScanMode {
 	uint8_t status;
 	uint8_t pageScanMode; /* nonzero modes are optional */
 } __packed;
 
-#define HCI_CMD_Write_Page_Scan_Mode                             0x003E  /* complete *//* deprecated in BT 1.2+ */
+#define HCI_CMD_Write_Page_Scan_Mode \
+	0x003E /* complete */ /* deprecated in BT 1.2+ */
 struct hciWritePageScanMode {
 	uint8_t pageScanMode; /* nonzero modes are optional */
 } __packed;
@@ -1406,10 +1502,9 @@ struct hciCmplWritePageScanMode {
 	uint8_t status;
 } __packed;
 
-
 /* ==== BT 1.2 ==== */
 
-#define HCI_CMD_Set_AFH_Host_Channel_Classification              0x003F /* complete */
+#define HCI_CMD_Set_AFH_Host_Channel_Classification 0x003F /* complete */
 struct hciSetAfhHostChannelClassification {
 	uint8_t channels[10];
 } __packed;
@@ -1417,13 +1512,13 @@ struct hciCmplSetAfhHostChannelClassification {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Inquiry_Scan_Type                           0x0042 /* complete */
+#define HCI_CMD_Read_Inquiry_Scan_Type 0x0042 /* complete */
 struct hciCmplReadInquiryScanType {
 	uint8_t status;
 	uint8_t interlaced; /* optional */
 } __packed;
 
-#define HCI_CMD_Write_Inquiry_Scan_Type                          0x0043 /* complete */
+#define HCI_CMD_Write_Inquiry_Scan_Type 0x0043 /* complete */
 struct hciWriteInquiryScanType {
 	uint8_t interlaced; /* optional */
 } __packed;
@@ -1431,13 +1526,13 @@ struct hciCmplWriteInquiryScanType {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Inquiry_Mode                                0x0044 /* complete */
+#define HCI_CMD_Read_Inquiry_Mode 0x0044 /* complete */
 struct hciCmplReadInquryMode {
 	uint8_t status;
 	uint8_t inqMode; /* HCI_INQ_MODE_* */
 } __packed;
 
-#define HCI_CMD_Write_Inquiry_Mode                               0x0045 /* complete */
+#define HCI_CMD_Write_Inquiry_Mode 0x0045 /* complete */
 struct hciWriteInquiryMode {
 	uint8_t inqMode; /* HCI_INQ_MODE_* */
 } __packed;
@@ -1445,13 +1540,13 @@ struct hciCmplWriteInquiryMode {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Page_Scan_Type                              0x0046 /* complete */
+#define HCI_CMD_Read_Page_Scan_Type 0x0046 /* complete */
 struct hciCmplReadPageScanType {
 	uint8_t status;
 	uint8_t interlaced; /* optional */
 } __packed;
 
-#define HCI_CMD_Write_Page_Scan_Type                             0x0047 /* complete */
+#define HCI_CMD_Write_Page_Scan_Type 0x0047 /* complete */
 struct hciWritePageScanType {
 	uint8_t interlaced; /* optional */
 } __packed;
@@ -1459,13 +1554,13 @@ struct hciCmplWritePageScanType {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_AFH_Channel_Assessment_Mode                 0x0048 /* complete */
+#define HCI_CMD_Read_AFH_Channel_Assessment_Mode 0x0048 /* complete */
 struct hciCmplReadAfhChannelAssessment {
 	uint8_t status;
 	uint8_t channelAssessmentEnabled;
 } __packed;
 
-#define HCI_CMD_Write_AFH_Channel_Assessment_Mode                0x0049 /* complete */
+#define HCI_CMD_Write_AFH_Channel_Assessment_Mode 0x0049 /* complete */
 struct hciWriteAfhChannelAssessment {
 	uint8_t channelAssessmentEnabled;
 } __packed;
@@ -1473,17 +1568,16 @@ struct hciCmplWriteAfhChannelAssessment {
 	uint8_t status;
 } __packed;
 
-
 /* ==== BT 2.1 ==== */
 
-#define HCI_CMD_Read_Extended_Inquiry_Response                   0x0051 /* complete */
+#define HCI_CMD_Read_Extended_Inquiry_Response 0x0051 /* complete */
 struct hciCmplReadEIR {
 	uint8_t status;
 	uint8_t useFec;
 	uint8_t data[240];
 } __packed;
 
-#define HCI_CMD_Write_Extended_Inquiry_Response                  0x0052 /* complete */
+#define HCI_CMD_Write_Extended_Inquiry_Response 0x0052 /* complete */
 struct hciWriteEIR {
 	uint8_t useFec;
 	uint8_t data[240];
@@ -1492,18 +1586,18 @@ struct hciCmplWriteEIR {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Refresh_Encryption_Key                           0x0052 /* status */
+#define HCI_CMD_Refresh_Encryption_Key 0x0052 /* status */
 struct hciRefreshEncryptionKey {
 	uint16_t conn;
 } __packed;
 
-#define HCI_CMD_Read_Simple_Pairing_Mode                         0x0055 /* complete */
+#define HCI_CMD_Read_Simple_Pairing_Mode 0x0055 /* complete */
 struct hciCmplReadSimplePairingMore {
 	uint8_t status;
 	uint8_t useSsp;
 } __packed;
 
-#define HCI_CMD_Write_Simple_Pairing_Mode                        0x0056 /* complete */
+#define HCI_CMD_Write_Simple_Pairing_Mode 0x0056 /* complete */
 struct hciWriteSimplePairingMode {
 	uint8_t useSsp;
 } __packed;
@@ -1511,20 +1605,22 @@ struct hciCmplWriteSimplePairingMode {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Local_OOB_Data                              0x0057 /* complete */
+#define HCI_CMD_Read_Local_OOB_Data 0x0057 /* complete */
 struct hciCmplReadLocalOobData {
 	uint8_t status;
 	uint8_t C[16];
 	uint8_t R[16];
 } __packed;
 
-#define HCI_CMD_Read_Inquiry_Response_Transmit_Power_Level       0x0058 /* complete */
+#define HCI_CMD_Read_Inquiry_Response_Transmit_Power_Level \
+	0x0058 /* complete                                 \
+		*/
 struct hciCmplReadInquiryTransmitPowerLevel {
 	uint8_t status;
 	uint8_t power; /* actually an int8_t */
 } __packed;
 
-#define HCI_CMD_Write_Inquiry_Transmit_Power_Level               0x0059 /* complete */
+#define HCI_CMD_Write_Inquiry_Transmit_Power_Level 0x0059 /* complete */
 struct hciWriteInquiryTransmitPowerLevel {
 	uint8_t power; /* actually an int8_t */
 } __packed;
@@ -1532,13 +1628,13 @@ struct hciCmplWriteInquiryTransmitPowerLevel {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Default_Erroneous_Data_Reporting            0x005A /* complete */
+#define HCI_CMD_Read_Default_Erroneous_Data_Reporting 0x005A /* complete */
 struct hciCmplReadErroneousDataReporting {
 	uint8_t status;
 	uint8_t reportingEnabled;
 } __packed;
 
-#define HCI_CMD_Write_Default_Erroneous_Data_Reporting           0x005B /* complete */
+#define HCI_CMD_Write_Default_Erroneous_Data_Reporting 0x005B /* complete */
 struct hciWriteErroneousDataReporting {
 	uint8_t reportingEnabled;
 } __packed;
@@ -1546,13 +1642,14 @@ struct hciCmplWriteErroneousDataReporting {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Enhanced_Flush                                   0x005F /* status */
+#define HCI_CMD_Enhanced_Flush 0x005F /* status */
 struct hciEnhancedFlush {
 	uint16_t conn;
-	uint8_t which; /* 0 is the only value - flush auto-flushable packets only */
+	uint8_t which; /* 0 is the only value - flush auto-flushable packets
+			  only */
 } __packed;
 
-#define HCI_CMD_Send_Keypress_Notification                       0x0060 /* complete */
+#define HCI_CMD_Send_Keypress_Notification 0x0060 /* complete */
 struct hciSendKeypressNotification {
 	uint8_t mac[6];
 	uint8_t notifType; /* HCI_SSP_KEY_ENTRY_* */
@@ -1562,24 +1659,25 @@ struct hciCmplSendKeypressNotification {
 	uint8_t mac[6];
 } __packed;
 
-
 /* ==== BT 3.0 ==== */
 
-#define HCI_CMD_Read_Logical_Link_Accept_Timeout                 0x0061 /* complete */
+#define HCI_CMD_Read_Logical_Link_Accept_Timeout 0x0061 /* complete */
 struct hciCmplReadLogicalLinkTimeout {
 	uint8_t status;
-	uint16_t timeout; /* in units of 0.625ms 1..0xB540. Required support 0x00A0..0xB540 */
+	uint16_t timeout; /* in units of 0.625ms 1..0xB540. Required support
+			     0x00A0..0xB540 */
 } __packed;
 
-#define HCI_CMD_Write_Logical_Link_Accept_Timeout                0x0062 /* complete */
+#define HCI_CMD_Write_Logical_Link_Accept_Timeout 0x0062 /* complete */
 struct hciWriteLogicalLinkTimeout {
-	uint16_t timeout; /* in units of 0.625ms 1..0xB540. Required support 0x00A0..0xB540 */
+	uint16_t timeout; /* in units of 0.625ms 1..0xB540. Required support
+			     0x00A0..0xB540 */
 } __packed;
 struct hciCmplWriteLogicalLinkTimeout {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Set_Event_Mask_Page_2                            0x0063 /* complete */
+#define HCI_CMD_Set_Event_Mask_Page_2 0x0063 /* complete */
 struct hciSetEventMaskPage2 {
 	uint64_t mask; /* bitmask of HCI_EVENT_P2_* */
 } __packed;
@@ -1587,7 +1685,7 @@ struct hciCmplSetEventMaskPage2 {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Location_Data                               0x0064 /* complete */
+#define HCI_CMD_Read_Location_Data 0x0064 /* complete */
 struct hciCmplReadLocationData {
 	uint8_t status;
 	uint8_t regulatoryDomainKnown;
@@ -1596,7 +1694,7 @@ struct hciCmplReadLocationData {
 	uint8_t mainsPowered;
 } __packed;
 
-#define HCI_CMD_Write_Location_Data                              0x0065 /* complete */
+#define HCI_CMD_Write_Location_Data 0x0065 /* complete */
 struct hciWriteLocationData {
 	uint8_t regulatoryDomainKnown;
 	uint16_t domain; /* ISO3166-1 code if known, else 0x5858 'XX' */
@@ -1607,21 +1705,23 @@ struct hciCmplWriteLocationData {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Flow_Control_Mode                           0x0066 /* complete */
+#define HCI_CMD_Read_Flow_Control_Mode 0x0066 /* complete */
 struct hciCmplReadFlowControlMode {
 	uint8_t status;
-	uint8_t blockBased; /* block based is for amp, packed-based is for BR/EDR */
+	uint8_t blockBased; /* block based is for amp, packed-based is for
+			       BR/EDR */
 } __packed;
 
-#define HCI_CMD_Write_Flow_Control_mode                          0x0067 /* complete */
+#define HCI_CMD_Write_Flow_Control_mode 0x0067 /* complete */
 struct hciWriteFlowControlMode {
-	uint8_t blockBased; /* block based is for amp, packed-based is for BR/EDR */
+	uint8_t blockBased; /* block based is for amp, packed-based is for
+			       BR/EDR */
 } __packed;
 struct hciCmplWriteFlowcontrolMode {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Enhanced_Transmit_Power_Level               0x0068 /* complete */
+#define HCI_CMD_Read_Enhanced_Transmit_Power_Level 0x0068 /* complete */
 struct hciReadEnhancedTransmitPowerLevel {
 	uint16_t conn;
 	uint8_t max; /* else currurent is read */
@@ -1634,7 +1734,7 @@ struct hciCmplReadEnhancedTransmitPowerLevel {
 	uint8_t txLevel8DPSK; /* actually an int8_t */
 } __packed;
 
-#define HCI_CMD_Read_Best_Effort_Flush_Timeout                   0x0069 /* complete */
+#define HCI_CMD_Read_Best_Effort_Flush_Timeout 0x0069 /* complete */
 struct hciReadBestEffortFlushTimeout {
 	uint16_t logicalLinkHandle;
 } __packed;
@@ -1643,7 +1743,7 @@ struct hciCmplReadBestEffortFlushTimeout {
 	uint32_t bestEffortFlushTimeout; /* in microseconds */
 } __packed;
 
-#define HCI_CMD_Write_Best_Effort_Flush_Timeout                  0x006A /* complete */
+#define HCI_CMD_Write_Best_Effort_Flush_Timeout 0x006A /* complete */
 struct hciWriteBestEffortFlushTimeout {
 	uint16_t logicalLinkHandle;
 	uint32_t bestEffortFlushTimeout; /* in microseconds */
@@ -1652,23 +1752,22 @@ struct hciCmplWriteBestEffortFlushTimeout {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Short_Range_Mode                                 0x006B /* status */
+#define HCI_CMD_Short_Range_Mode 0x006B /* status */
 struct hciShortRangeMode {
 	uint8_t physicalLinkHandle;
 	uint8_t shortRangeModeEnabled;
 } __packed;
 
-
 /* ==== BT 4.0 ==== */
 
-#define HCI_CMD_Read_LE_Host_Supported                           0x006C /* complete */
+#define HCI_CMD_Read_LE_Host_Supported 0x006C /* complete */
 struct hciCmplReadLeHostSupported {
 	uint8_t status;
 	uint8_t leSupportedHost;
 	uint8_t simultaneousLeHost;
 } __packed;
 
-#define HCI_CMD_Write_LE_Host_Supported                          0x006D /* complete */
+#define HCI_CMD_Write_LE_Host_Supported 0x006D /* complete */
 struct hciWriteLeHostSupported {
 	uint8_t leSupportedHost;
 	uint8_t simultaneousLeHost;
@@ -1677,10 +1776,9 @@ struct hciCmplWriteLeHostSupported {
 	uint8_t status;
 } __packed;
 
-
 /* ==== BT 4.1 ==== */
 
-#define HCI_CMD_Set_MWS_Channel_Parameters                       0x006E /* complete */
+#define HCI_CMD_Set_MWS_Channel_Parameters 0x006E /* complete */
 struct hciSetMwsChannelParams {
 	uint8_t mwsEnabled;
 	uint16_t mwsChannelRxCenterFreq; /* in MHz */
@@ -1693,7 +1791,7 @@ struct hciCmplSetMwsChannelParams {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Set_External_Frame_Configuration                 0x006F /* complete */
+#define HCI_CMD_Set_External_Frame_Configuration 0x006F /* complete */
 struct hciSetExternalFrameConfigItem {
 	uint16_t periodDuration; /* in microseconds */
 	uint8_t periodType; /* HCI_PERIOD_TYPE_* */
@@ -1709,7 +1807,7 @@ struct hciCmplSetExternalFrameConfig {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Set_MWS_Signalling                               0x0070 /* complete */
+#define HCI_CMD_Set_MWS_Signalling 0x0070 /* complete */
 struct hciSetMwsSignalling {
 	uint16_t mwsRxAssertOffset; /* all of these are in microseconds */
 	uint16_t mwsRxAssertJitter;
@@ -1747,7 +1845,7 @@ struct hciCmplSetMwsSignalling {
 	uint16_t _802TxOnDeassertJitter;
 } __packed;
 
-#define HCI_CMD_Set_MWS_Transport_Layer                          0x0071 /* complete */
+#define HCI_CMD_Set_MWS_Transport_Layer 0x0071 /* complete */
 struct hciSetMwsTransportLayer {
 	uint8_t transportLayer;
 	uint32_t toMwsBaudRate; /* in byte/sec */
@@ -1757,7 +1855,7 @@ struct hciCmplSetMwsTransportLayer {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Set_MWS_Scan_Frequency_Table                     0x0072 /* complete */
+#define HCI_CMD_Set_MWS_Scan_Frequency_Table 0x0072 /* complete */
 struct hciSetMwsScanFrequencyTableItem {
 	uint16_t scanFreqLow; /*in MHz */
 	uint16_t scanFreqHigh; /*in MHz */
@@ -1770,7 +1868,7 @@ struct hciCmplSetMwsScanFrequencyTable {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Set_MWS_PATTERN_Configuration                    0x0073 /* complete */
+#define HCI_CMD_Set_MWS_PATTERN_Configuration 0x0073 /* complete */
 struct hciSetMwsPatternConfigItem {
 	uint16_t intervalDuration; /* in microseconds */
 	uint8_t intervalType; /* HCI_MWS_INTERVAL_TYPE_* */
@@ -1784,7 +1882,7 @@ struct hciCmplSetMwsPatternConfig {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Set_Reserved_LT_ADDR                             0x0074 /* complete */
+#define HCI_CMD_Set_Reserved_LT_ADDR 0x0074 /* complete */
 struct hciSetReservedLtAddr {
 	uint8_t ltAddr;
 } __packed;
@@ -1793,7 +1891,7 @@ struct hciCmplSetReservedLtAddr {
 	uint8_t ltAddr;
 } __packed;
 
-#define HCI_CMD_Delete_Reserved_LT_ADDR                          0x0075 /* complete */
+#define HCI_CMD_Delete_Reserved_LT_ADDR 0x0075 /* complete */
 struct hciDeleteReservedLtAddr {
 	uint8_t ltAddr;
 } __packed;
@@ -1802,7 +1900,7 @@ struct hciCmplDeleteReservedLtAddr {
 	uint8_t ltAddr;
 } __packed;
 
-#define HCI_CMD_Set_Connectionless_Slave_Broadcast_Data          0x0076 /* complete */
+#define HCI_CMD_Set_Connectionless_Slave_Broadcast_Data 0x0076 /* complete */
 struct hciSetConnlessSlaveBroadcastData {
 	uint8_t ltAddr;
 	uint8_t fragment; /* HCI_CONNLESS_FRAG_TYPE_* */
@@ -1814,7 +1912,7 @@ struct hciCmplSetConnlessSlaveBroadcastData {
 	uint8_t ltAddr;
 } __packed;
 
-#define HCI_CMD_Read_Synchronisation_Train_Parameters            0x0077 /* complete */
+#define HCI_CMD_Read_Synchronisation_Train_Parameters 0x0077 /* complete */
 struct hciCmplReadSyncTrainParams {
 	uint8_t status;
 	uint16_t interval;
@@ -1822,7 +1920,7 @@ struct hciCmplReadSyncTrainParams {
 	uint8_t serviceData;
 } __packed;
 
-#define HCI_CMD_Write_Synchronisation_Train_Parameters           0x0078 /* complete */
+#define HCI_CMD_Write_Synchronisation_Train_Parameters 0x0078 /* complete */
 struct hciWriteSyncTrainParams {
 	uint16_t intMin;
 	uint16_t intMax;
@@ -1834,13 +1932,13 @@ struct hciCmplWriteSyncTrainParams {
 	uint16_t interval;
 } __packed;
 
-#define HCI_CMD_Read_Secure_Connections_Host_Support             0x0079 /* complete */
+#define HCI_CMD_Read_Secure_Connections_Host_Support 0x0079 /* complete */
 struct hciCmplReadSecureConnectionsHostSupport {
 	uint8_t status;
 	uint8_t secureConnectionsSupported;
 } __packed;
 
-#define HCI_CMD_Write_Secure_Connections_Host_Support            0x007A /* complete */
+#define HCI_CMD_Write_Secure_Connections_Host_Support 0x007A /* complete */
 struct hciWriteSecureConnectionsHostSupport {
 	uint8_t secureConnectionsSupported;
 } __packed;
@@ -1848,7 +1946,7 @@ struct hciCmplWriteSecureConnectionsHostSupport {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Authenticated_Payload_Timeout               0x007B /* complete */
+#define HCI_CMD_Read_Authenticated_Payload_Timeout 0x007B /* complete */
 struct hciReadAuthedPayloadTimeout {
 	uint16_t conn;
 } __packed;
@@ -1858,7 +1956,7 @@ struct hciCmplReadAuthedPayloadTimeout {
 	uint16_t timeout; /* in units of 10ms, 1 .. 0xffff */
 } __packed;
 
-#define HCI_CMD_Write_Authenticated_Payload_Timeout              0x007C /* complete */
+#define HCI_CMD_Write_Authenticated_Payload_Timeout 0x007C /* complete */
 struct hciWriteAuthedPayloadTimeout {
 	uint16_t conn;
 	uint16_t timeout; /* in units of 10ms, 1 .. 0xffff */
@@ -1868,7 +1966,7 @@ struct hciCmplWriteAuthedPayloadTimeout {
 	uint16_t conn;
 } __packed;
 
-#define HCI_CMD_Read_Local_OOB_Extended_Data                     0x007D /* complete */
+#define HCI_CMD_Read_Local_OOB_Extended_Data 0x007D /* complete */
 struct hciCmplReadLocalOobExtendedData {
 	uint8_t status;
 	uint8_t C_192[16];
@@ -1877,13 +1975,13 @@ struct hciCmplReadLocalOobExtendedData {
 	uint8_t R_256[16];
 } __packed;
 
-#define HCI_CMD_Read_Extended_Page_Timeout                       0x007E /* complete */
+#define HCI_CMD_Read_Extended_Page_Timeout 0x007E /* complete */
 struct hciCmplReadExtendedPageTimeout {
 	uint8_t status;
 	uint16_t timeout; /* in units of 0.625ms 0..0xffff */
 } __packed;
 
-#define HCI_CMD_Write_Extended_Page_Timeout                      0x007F /* complete */
+#define HCI_CMD_Write_Extended_Page_Timeout 0x007F /* complete */
 struct hciWriteExtendedPageTimeout {
 	uint16_t timeout; /* in units of 0.625ms 0..0xffff */
 } __packed;
@@ -1891,13 +1989,13 @@ struct hciCmplWriteExtendedPageTimeout {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_Read_Extended_Inquiry_Length                     0x0080 /* complete */
+#define HCI_CMD_Read_Extended_Inquiry_Length 0x0080 /* complete */
 struct hciCmplReadExtendedInquiryLength {
 	uint8_t status;
 	uint16_t timeout; /* in units of 0.625ms 0..0xffff */
 } __packed;
 
-#define HCI_CMD_Write_Extended_Inquiry_Length                    0x0081 /* complete */
+#define HCI_CMD_Write_Extended_Inquiry_Length 0x0081 /* complete */
 struct hciWriteExtendedInquiryLength {
 	uint16_t timeout; /* in units of 0.625ms 0..0xffff */
 } __packed;
@@ -1905,16 +2003,11 @@ struct hciCmplWriteExtendedInquiryLength {
 	uint8_t status;
 } __packed;
 
-
-
-
-
-#define HCI_OGF_Informational                                    4
-
+#define HCI_OGF_Informational 4
 
 /* ==== BT 1.1 ==== */
 
-#define HCI_CMD_Read_Local_Version_Information                   0x0001 /* complete */
+#define HCI_CMD_Read_Local_Version_Information 0x0001 /* complete */
 struct hciCmplReadLocalVersion {
 	uint8_t status;
 	uint8_t hciVersion; /* HCI_VERSION_* */
@@ -1924,19 +2017,19 @@ struct hciCmplReadLocalVersion {
 	uint16_t lmpSubversion;
 } __packed;
 
-#define HCI_CMD_Read_Local_Supported_Commands                    0x0002 /* complete */
+#define HCI_CMD_Read_Local_Supported_Commands 0x0002 /* complete */
 struct hciCmplReadLocalSupportedCommands {
 	uint8_t status;
 	uint64_t bitfield;
 } __packed;
 
-#define HCI_CMD_Read_Local_Supported_Features                    0x0003 /* complete */
+#define HCI_CMD_Read_Local_Supported_Features 0x0003 /* complete */
 struct hciCmplReadLocalSupportedFeatures {
 	uint8_t status;
-	uint64_t features;  /* bitmask of HCI_LMP_FTR_* */
+	uint64_t features; /* bitmask of HCI_LMP_FTR_* */
 } __packed;
 
-#define HCI_CMD_Read_Local_Extended_Features                     0x0004 /* complete */
+#define HCI_CMD_Read_Local_Extended_Features 0x0004 /* complete */
 struct hciReadLocalExtendedFeatures {
 	uint8_t page;
 } __packed;
@@ -1947,7 +2040,7 @@ struct hciCmplReadLocalExtendedFeatures {
 	uint64_t features; /* bitmask of HCI_LMP_EXT_FTR_P* */
 } __packed;
 
-#define HCI_CMD_Read_Buffer_Size                                 0x0005 /* complete */
+#define HCI_CMD_Read_Buffer_Size 0x0005 /* complete */
 struct hciCmplReadBufferSize {
 	uint8_t status;
 	uint16_t aclBufferLen;
@@ -1956,16 +2049,15 @@ struct hciCmplReadBufferSize {
 	uint16_t numScoBuffers;
 } __packed;
 
-#define HCI_CMD_Read_BD_ADDR                                     0x0009 /* complete */
+#define HCI_CMD_Read_BD_ADDR 0x0009 /* complete */
 struct hciCmplReadBdAddr {
 	uint8_t status;
 	uint8_t mac[6];
 } __packed;
 
-
 /* ==== BT 3.0 ==== */
 
-#define HCI_CMD_Read_Data_Block_Size                             0x000A /* complete */
+#define HCI_CMD_Read_Data_Block_Size 0x000A /* complete */
 struct hciCmplReadDataBlockSize {
 	uint8_t status;
 	uint16_t maxAclDataPacketLen;
@@ -1973,30 +2065,24 @@ struct hciCmplReadDataBlockSize {
 	uint16_t totalNumDataBlocks;
 } __packed;
 
-
 /* ==== BT 4.1 ==== */
 
-#define HCI_CMD_Read_Local_Supported_Codecs                      0x000B /* complete */
+#define HCI_CMD_Read_Local_Supported_Codecs 0x000B /* complete */
 struct hciCmplReadLocalSupportedCodecs {
 	uint8_t status;
 	uint8_t numSupportedCodecs;
 	uint8_t codecs[];
-/* these follow, but due to var array cannot be declared here:
-	uint8_t numVendorCodecs;
-	uint32_t vendorCodecs[];
-*/
+	/* these follow, but due to var array cannot be declared here:
+		uint8_t numVendorCodecs;
+		uint32_t vendorCodecs[];
+	*/
 } __packed;
 
-
-
-
-
-#define HCI_OGF_Status                                           5
-
+#define HCI_OGF_Status 5
 
 /* == BT 1.1 == */
 
-#define HCI_CMD_Read_Failed_Contact_Counter                      0x0001 /* complete */
+#define HCI_CMD_Read_Failed_Contact_Counter 0x0001 /* complete */
 struct hciReadFailedContactCounter {
 	uint16_t conn;
 } __packed;
@@ -2006,7 +2092,7 @@ struct hciCmplReadFailedContactCounter {
 	uint16_t counter;
 } __packed;
 
-#define HCI_CMD_Reset_Failed_Contact_Counter                     0x0002 /* complete */
+#define HCI_CMD_Reset_Failed_Contact_Counter 0x0002 /* complete */
 struct hciResetFailedContactCounter {
 	uint16_t conn;
 } __packed;
@@ -2015,7 +2101,7 @@ struct hciCmplResetFailedContactCounter {
 	uint16_t conn;
 } __packed;
 
-#define HCI_CMD_Read_Link_Quality                                0x0003 /* complete */
+#define HCI_CMD_Read_Link_Quality 0x0003 /* complete */
 struct hciReadLinkQuality {
 	uint16_t conn;
 } __packed;
@@ -2025,7 +2111,7 @@ struct hciCmplReadLinkQuality {
 	uint8_t quality;
 } __packed;
 
-#define HCI_CMD_Read_RSSI                                        0x0005 /* complete */
+#define HCI_CMD_Read_RSSI 0x0005 /* complete */
 struct hciReadRssi {
 	uint16_t conn;
 } __packed;
@@ -2035,10 +2121,9 @@ struct hciCmplReadRssi {
 	uint8_t RSSI; /* actually an int8_t */
 } __packed;
 
-
 /* ==== BT 1.2 ==== */
 
-#define HCI_CMD_Read_AFH_Channel_Map                             0x0006 /* complete */
+#define HCI_CMD_Read_AFH_Channel_Map 0x0006 /* complete */
 struct hciReadAfhChannelMap {
 	uint16_t conn;
 } __packed;
@@ -2048,7 +2133,7 @@ struct hciCmplReadAfhChannelMap {
 	uint8_t map[10];
 } __packed;
 
-#define HCI_CMD_Read_Clock                                       0x0007 /* complete */
+#define HCI_CMD_Read_Clock 0x0007 /* complete */
 struct hciReadClock {
 	uint16_t conn;
 	uint8_t readRemote; /* else reads local and ignores conn */
@@ -2060,10 +2145,9 @@ struct hciCmplReadClock {
 	uint16_t accuracy;
 } __packed;
 
-
 /* ==== BT 3.0 ==== */
 
-#define HCI_CMD_Read_Encryption_Key_Size                         0x0008 /* complete */
+#define HCI_CMD_Read_Encryption_Key_Size 0x0008 /* complete */
 struct hciReadEncrKeySize {
 	uint16_t conn;
 } __packed;
@@ -2073,7 +2157,7 @@ struct hciCmplReadEncrKeySize {
 	uint8_t keySize;
 } __packed;
 
-#define HCI_CMD_Read_Local_AMP_Info                              0x0009 /* complete */
+#define HCI_CMD_Read_Local_AMP_Info 0x0009 /* complete */
 struct hciCmplReadLocalAmpInfo {
 	uint8_t status;
 	uint8_t ampStatus;
@@ -2088,7 +2172,7 @@ struct hciCmplReadLocalAmpInfo {
 	uint32_t bestEffortFlushTimeout;
 } __packed;
 
-#define HCI_CMD_Read_Local_AMP_ASSOC                             0x000A /* complete */
+#define HCI_CMD_Read_Local_AMP_ASSOC 0x000A /* complete */
 struct hciReadLocalAmpAssoc {
 	uint8_t physicalLinkHandle;
 	uint16_t lengthSoFar;
@@ -2101,7 +2185,7 @@ struct hciCmplReadLocalAmpAssoc {
 	uint8_t ampAssocFragment[]; /* 1.. 248 byutes */
 } __packed;
 
-#define HCI_CMD_Write_Remote_AMP_ASSOC                           0x000B /* complete */
+#define HCI_CMD_Write_Remote_AMP_ASSOC 0x000B /* complete */
 struct hciWriteRemoteAmpAssoc {
 	uint8_t physicalLinkHandle;
 	uint16_t lengthSoFar;
@@ -2115,7 +2199,7 @@ struct hciCmplWriteRemoteAmpAssoc {
 
 /* ==== BT 4.1 ==== */
 
-#define HCI_CMD_Get_MWS_Transport_Layer_Configuration            0x000C /* complete */
+#define HCI_CMD_Get_MWS_Transport_Layer_Configuration 0x000C /* complete */
 struct hciCmplGetMwsTransportLayerConfigItem {
 	uint8_t transportLayer;
 	uint8_t numBaudRates;
@@ -2127,13 +2211,15 @@ struct hciCmplGetMwsTransportLayerConfigBandwidthItem {
 struct hciCmplGetMwsTransportLayerConfig {
 	uint8_t status;
 	uint8_t numTransports;
-	struct hciCmplGetMwsTransportLayerConfigItem items[]; /* numTransports items */
-/* this follows:
-	struct hciCmplGetMwsTransportLayerConfigBandwidthItem items[] // sum(items[].numbaudRates) items
-*/
+	struct hciCmplGetMwsTransportLayerConfigItem items[]; /* numTransports
+								 items */
+	/* this follows:
+		struct hciCmplGetMwsTransportLayerConfigBandwidthItem items[] //
+	   sum(items[].numbaudRates) items
+	*/
 } __packed;
 
-#define HCI_CMD_Set_Triggered_Clock_Capture                      0x000D /* complete */
+#define HCI_CMD_Set_Triggered_Clock_Capture 0x000D /* complete */
 struct hciSetTriggeredClockCapture {
 	uint16_t conn;
 	uint8_t enable;
@@ -2145,16 +2231,11 @@ struct hciCmplSetTriggeredClockCapture {
 	uint8_t status;
 } __packed;
 
-
-
-
-
-#define HCI_OGF_LE                                               8
-
+#define HCI_OGF_LE 8
 
 /* ==== BT 4.0 ==== */
 
-#define HCI_CMD_LE_Set_Event_Mask                                0x0001 /* complete */
+#define HCI_CMD_LE_Set_Event_Mask 0x0001 /* complete */
 struct hciLeSetEventMask {
 	uint64_t events; /* bitmask of HCI_LE_EVENT_* */
 } __packed;
@@ -2162,28 +2243,28 @@ struct hciCmplLeSetEventMask {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_LE_Read_Buffer_Size                              0x0002 /* complete */
+#define HCI_CMD_LE_Read_Buffer_Size 0x0002 /* complete */
 struct hciCmplLeReadBufferSize {
 	uint8_t status;
 	uint16_t leBufferSize;
 	uint8_t leNumBuffers;
 } __packed;
 
-#define HCI_CMD_LE_Read_Local_Supported_Features                 0x0003 /* complete */
+#define HCI_CMD_LE_Read_Local_Supported_Features 0x0003 /* complete */
 struct hciCmplLeReadLocalSupportedFeatures {
 	uint8_t status;
 	uint64_t leFeatures; /* bitmask of HCI_LE_FTR_* */
 } __packed;
 
-#define HCI_CMD_LE_Set_Random_Address                            0x0005 /* complete */
-struct hciLeSetRandomAddress{
+#define HCI_CMD_LE_Set_Random_Address 0x0005 /* complete */
+struct hciLeSetRandomAddress {
 	uint8_t mac[6];
 } __packed;
-struct hciCmplLeSetRandomAddress{
+struct hciCmplLeSetRandomAddress {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_LE_Set_Adv_Params                                0x0006 /* complete */
+#define HCI_CMD_LE_Set_Adv_Params 0x0006 /* complete */
 struct hciLeSetAdvParams {
 	uint16_t advIntervalMin;
 	uint16_t advIntervalMax;
@@ -2198,13 +2279,13 @@ struct hciCmplLeSetAdvParams {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_LE_Read_Adv_Channel_TX_Power                     0x0007 /* complete */
+#define HCI_CMD_LE_Read_Adv_Channel_TX_Power 0x0007 /* complete */
 struct hciCmplLeReadAdvChannelTxPower {
 	uint8_t status;
 	uint8_t txPower; /* actually an int8_t */
 } __packed;
 
-#define HCI_CMD_LE_Set_Advertising_Data                          0x0008 /* complete */
+#define HCI_CMD_LE_Set_Advertising_Data 0x0008 /* complete */
 struct hciLeSetAdvData {
 	uint8_t advDataLen;
 	uint8_t advData[31];
@@ -2213,7 +2294,7 @@ struct hciCmplLeSetAdvData {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_LE_Set_Scan_Response_Data                        0x0009 /* complete */
+#define HCI_CMD_LE_Set_Scan_Response_Data 0x0009 /* complete */
 struct hciSetScanResponseData {
 	uint8_t scanRspDataLen;
 	uint8_t scanRspData[31];
@@ -2222,7 +2303,7 @@ struct hciCmplSetScanResponseData {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_LE_Set_Advertise_Enable                          0x000A /* complete */
+#define HCI_CMD_LE_Set_Advertise_Enable 0x000A /* complete */
 struct hciLeSetAdvEnable {
 	uint8_t advOn;
 } __packed;
@@ -2230,7 +2311,7 @@ struct hciCmplLeSetAdvEnable {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_LE_Set_Scan_Parameters                           0x000B /* complete */
+#define HCI_CMD_LE_Set_Scan_Parameters 0x000B /* complete */
 struct hciLeSetScanParams {
 	uint8_t activeScan;
 	uint16_t scanInterval; /* in units of 0.625ms, 4..0x4000 */
@@ -2242,7 +2323,7 @@ struct hciCmplLeSetScanParams {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_LE_Set_Scan_Enable                               0x000C /* complete */
+#define HCI_CMD_LE_Set_Scan_Enable 0x000C /* complete */
 struct hciLeSetScanEnable {
 	uint8_t scanOn;
 	uint8_t filterDuplicates;
@@ -2251,7 +2332,7 @@ struct hciCmplLeSetScanEnable {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_LE_Create_Connection                             0x000D /* status */
+#define HCI_CMD_LE_Create_Connection 0x000D /* status */
 struct hciLeCreateConnection {
 	uint16_t scanInterval; /* in units of 0.625ms, 4..0x4000 */
 	uint16_t scanWindow; /* in units of 0.625ms, 4..0x4000 */
@@ -2263,27 +2344,29 @@ struct hciLeCreateConnection {
 	uint16_t connIntervalMax; /* in units of 1.25ms, 6..0x0C80 */
 	uint16_t connLatency; /* 0..0x1F4 */
 	uint16_t supervisionTimeout; /* in units of 10ms, 0xA...0x0C80 */
-	uint16_t minConnLen; /* minimum conn len needed in units of 0.625ms 0..0xfff */
-	uint16_t maxConnLen; /* minimum conn len needed in units of 0.625ms 0..0xfff */
+	uint16_t minConnLen; /* minimum conn len needed in units of 0.625ms
+				0..0xfff */
+	uint16_t maxConnLen; /* minimum conn len needed in units of 0.625ms
+				0..0xfff */
 } __packed;
 
-#define HCI_CMD_LE_Create_Connection_Cancel                      0x000E /* complete */
+#define HCI_CMD_LE_Create_Connection_Cancel 0x000E /* complete */
 struct hciCmplLeCreateConnectionCancel {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_LE_Read_Allow_List_Size                          0x000F /* complete */
+#define HCI_CMD_LE_Read_Allow_List_Size 0x000F /* complete */
 struct hciCmplLeReadAllowListSize {
 	uint8_t status;
 	uint8_t allowlistSize;
 } __packed;
 
-#define HCI_CMD_LE_Clear_Allow_List                              0x0010 /* complete */
+#define HCI_CMD_LE_Clear_Allow_List 0x0010 /* complete */
 struct hciCmplLeClearAllowList {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_LE_Add_Device_To_Allow_List                      0x0011 /* complete */
+#define HCI_CMD_LE_Add_Device_To_Allow_List 0x0011 /* complete */
 struct hciLeAddDeviceToAllowList {
 	uint8_t randomAddr;
 	uint8_t mac[6];
@@ -2292,7 +2375,7 @@ struct hciCmplLeAddDeviceToAllowList {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_LE_Remove_Device_From_Allow_List                 0x0012 /* complete */
+#define HCI_CMD_LE_Remove_Device_From_Allow_List 0x0012 /* complete */
 struct hciLeRemoveDeviceFromAllowList {
 	uint8_t randomAddr;
 	uint8_t mac[6];
@@ -2301,18 +2384,20 @@ struct hciCmplLeRemoveDeviceFromAllowList {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_LE_Connection_Update                             0x0013 /* status */
+#define HCI_CMD_LE_Connection_Update 0x0013 /* status */
 struct hciLeConnectionUpdate {
 	uint16_t conn;
 	uint16_t connIntervalMin; /* in units of 1.25ms, 6..0x0C80 */
 	uint16_t connIntervalMax; /* in units of 1.25ms, 6..0x0C80 */
 	uint16_t connLatency; /* 0..0x1F4 */
 	uint16_t supervisionTimeout; /* in units of 10ms, 0xA...0x0C80 */
-	uint16_t minConnLen; /* minimum conn len needed in units of 0.625ms 0..0xfff */
-	uint16_t maxConnLen; /* minimum conn len needed in units of 0.625ms 0..0xfff */
+	uint16_t minConnLen; /* minimum conn len needed in units of 0.625ms
+				0..0xfff */
+	uint16_t maxConnLen; /* minimum conn len needed in units of 0.625ms
+				0..0xfff */
 } __packed;
 
-#define HCI_CMD_LE_Set_Host_Channel_Classification               0x0014 /* complete */
+#define HCI_CMD_LE_Set_Host_Channel_Classification 0x0014 /* complete */
 struct hciLeSetHostChannelClassification {
 	uint8_t chMap[5];
 } __packed;
@@ -2320,7 +2405,7 @@ struct hciCmplLeSetHostChannelClassification {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_LE_Read_Channel_Map                              0x0015 /* complete */
+#define HCI_CMD_LE_Read_Channel_Map 0x0015 /* complete */
 struct hciLeReadChannelMap {
 	uint16_t conn;
 } __packed;
@@ -2330,12 +2415,12 @@ struct hciCmplLeReadChannelMap {
 	uint8_t chMap[5];
 } __packed;
 
-#define HCI_CMD_LE_Read_Remote_Used_Features                     0x0016 /* status */
+#define HCI_CMD_LE_Read_Remote_Used_Features 0x0016 /* status */
 struct hciLeReadRemoteUsedFeatures {
 	uint16_t conn;
 } __packed;
 
-#define HCI_CMD_LE_Encrypt                                       0x0017 /* complete */
+#define HCI_CMD_LE_Encrypt 0x0017 /* complete */
 struct hciLeEncrypt {
 	uint8_t key[16];
 	uint8_t plaintext[16];
@@ -2345,13 +2430,13 @@ struct hciCmplLeEncrypt {
 	uint8_t encryptedData[16];
 } __packed;
 
-#define HCI_CMD_LE_Rand                                          0x0018 /* complete */
+#define HCI_CMD_LE_Rand 0x0018 /* complete */
 struct hciCmplLeRand {
 	uint8_t status;
 	uint64_t rand;
 } __packed;
 
-#define HCI_CMD_LE_Start_Encryption                              0x0019 /* status */
+#define HCI_CMD_LE_Start_Encryption 0x0019 /* status */
 struct hciLeStartEncryption {
 	uint16_t conn;
 	uint64_t rand;
@@ -2359,7 +2444,7 @@ struct hciLeStartEncryption {
 	uint8_t LTK[16];
 } __packed;
 
-#define HCI_CMD_LE_LTK_Request_Reply                             0x001A /* complete */
+#define HCI_CMD_LE_LTK_Request_Reply 0x001A /* complete */
 struct hciLeLtkRequestReply {
 	uint16_t conn;
 	uint8_t LTK[16];
@@ -2369,7 +2454,7 @@ struct hciCmplLeLtkRequestReply {
 	uint16_t conn;
 } __packed;
 
-#define HCI_CMD_LE_LTK_Request_Negative_Reply                    0x001B /* complete */
+#define HCI_CMD_LE_LTK_Request_Negative_Reply 0x001B /* complete */
 struct hciLeLtkRequestNegativeReply {
 	uint16_t conn;
 } __packed;
@@ -2378,13 +2463,13 @@ struct hciCmplLeLtkRequestNegativeReply {
 	uint16_t conn;
 } __packed;
 
-#define HCI_CMD_LE_Read_Supported_States                         0x001C /* complete */
+#define HCI_CMD_LE_Read_Supported_States 0x001C /* complete */
 struct hciCmplLeReadSupportedStates {
 	uint8_t status;
 	uint64_t states; /* bitmask of HCI_LE_STATE_* */
 } __packed;
 
-#define HCI_CMD_LE_Receiver_Test                                 0x001D /* complete */
+#define HCI_CMD_LE_Receiver_Test 0x001D /* complete */
 struct hciLeReceiverTest {
 	uint8_t radioChannelNum; /* 2402 + radioChannelNum * 2 MHz */
 } __packed;
@@ -2392,7 +2477,7 @@ struct hciCmplLeReceiverTest {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_LE_Transmitter_Test                              0x001E /* complete */
+#define HCI_CMD_LE_Transmitter_Test 0x001E /* complete */
 struct hciLeTransmitterTest {
 	uint8_t radioChannelNum; /* 2402 + radioChannelNum * 2 MHz */
 	uint8_t lengthOfTestData;
@@ -2402,31 +2487,33 @@ struct hciCmplLeTransmitterTest {
 	uint8_t status;
 } __packed;
 
-#define HCI_CMD_LE_Test_End                                      0x001F /* complete */
+#define HCI_CMD_LE_Test_End 0x001F /* complete */
 struct hciCmplLeTestEnd {
 	uint8_t status;
 	uint16_t numPackets;
 } __packed;
 
-
 /* ==== BT 4.1 ==== */
 
-#define HCI_CMD_LE_Remote_Conn_Param_Request_Reply               0x0020 /* complete */
+#define HCI_CMD_LE_Remote_Conn_Param_Request_Reply 0x0020 /* complete */
 struct hciLeRemoteConnParamRequestReply {
 	uint16_t conn;
 	uint16_t connIntervalMin; /* in units of 1.25ms, 6..0x0C80 */
 	uint16_t connIntervalMax; /* in units of 1.25ms, 6..0x0C80 */
 	uint16_t connLatency; /* 0..0x1F4 */
 	uint16_t supervisionTimeout; /* in units of 10ms, 0xA...0x0C80 */
-	uint16_t minConnLen; /* minimum conn len needed in units of 0.625ms 0..0xfff */
-	uint16_t maxConnLen; /* minimum conn len needed in units of 0.625ms 0..0xfff */
+	uint16_t minConnLen; /* minimum conn len needed in units of 0.625ms
+				0..0xfff */
+	uint16_t maxConnLen; /* minimum conn len needed in units of 0.625ms
+				0..0xfff */
 } __packed;
 struct hciCmplLeRemoteConnParamRequestReply {
 	uint8_t status;
 	uint16_t conn;
 } __packed;
 
-#define HCI_CMD_LE_Remote_Conn_Param_Request_Negative_Reply      0x0021 /* complete */
+#define HCI_CMD_LE_Remote_Conn_Param_Request_Negative_Reply \
+	0x0021 /* complete */
 struct hciRemoteConnParamRequestNegativeReply {
 	uint16_t conn;
 	uint8_t reason;
@@ -2436,19 +2523,16 @@ struct hciCmplLeRemoteConnParamRequestNegativeReply {
 	uint16_t conn;
 } __packed;
 
-
-
 /* EVENTS */
 
-
 /* ==== BT 1.1 ==== */
 
-#define HCI_EVT_Inquiry_Complete                                 0x01
+#define HCI_EVT_Inquiry_Complete 0x01
 struct hciEvtInquiryComplete {
 	uint8_t status;
 } __packed;
 
-#define HCI_EVT_Inquiry_Result                                   0x02
+#define HCI_EVT_Inquiry_Result 0x02
 struct hciEvtInquiryResultItem {
 	uint8_t mac[6];
 	uint8_t PSRM;
@@ -2462,7 +2546,7 @@ struct hciEvtInquiryResult {
 	struct hciEvtInquiryResultItem items[];
 } __packed;
 
-#define HCI_EVT_Connection_Complete                              0x03
+#define HCI_EVT_Connection_Complete 0x03
 struct hciEvtConnComplete {
 	uint8_t status;
 	uint16_t conn;
@@ -2471,61 +2555,61 @@ struct hciEvtConnComplete {
 	uint8_t encrypted;
 } __packed;
 
-#define HCI_EVT_Connection_Request                               0x04
+#define HCI_EVT_Connection_Request 0x04
 struct hciEvtConnRequest {
 	uint8_t mac[6];
 	uint8_t deviceClass[3];
 	uint8_t isAclLink;
 } __packed;
 
-#define HCI_EVT_Disconnection_Complete                           0x05
+#define HCI_EVT_Disconnection_Complete 0x05
 struct hciEvtDiscComplete {
 	uint8_t status;
 	uint16_t conn;
 	uint8_t reason;
 } __packed;
 
-#define HCI_EVT_Authentication_Complete                          0x06
+#define HCI_EVT_Authentication_Complete 0x06
 struct hciEvtAuthComplete {
 	uint8_t status;
 	uint16_t handle;
 } __packed;
 
-#define HCI_EVT_Remote_Name_Request_Complete                     0x07
+#define HCI_EVT_Remote_Name_Request_Complete 0x07
 struct hciEvtRemoteNameReqComplete {
 	uint8_t status;
 	uint8_t mac[6];
 	char name[HCI_DEV_NAME_LEN];
 } __packed;
 
-#define HCI_EVT_Encryption_Change                                0x08
+#define HCI_EVT_Encryption_Change 0x08
 struct hciEvtEncrChange {
 	uint8_t status;
 	uint16_t conn;
 	uint8_t encrOn;
 } __packed;
 
-#define HCI_EVT_Change_Connection_Link_Key_Complete              0x09
+#define HCI_EVT_Change_Connection_Link_Key_Complete 0x09
 struct hciEvtChangeConnLinkKeyComplete {
 	uint8_t status;
 	uint16_t handle;
 } __packed;
 
-#define HCI_EVT_Master_Link_Key_Complete                         0x0A
+#define HCI_EVT_Master_Link_Key_Complete 0x0A
 struct hciEvtMasterLinkKeyComplete {
 	uint8_t status;
 	uint16_t conn;
 	uint8_t usingTempKey; /* else using semi-permanent key */
 } __packed;
 
-#define HCI_EVT_Read_Remote_Supported_Features_Complete          0x0B
+#define HCI_EVT_Read_Remote_Supported_Features_Complete 0x0B
 struct hciEvtReadRemoteSupportedFeaturesComplete {
 	uint8_t status;
 	uint16_t conn;
 	uint64_t lmpFeatures; /* bitmask of HCI_LMP_FTR_* */
 } __packed;
 
-#define HCI_EVT_Read_Remote_Version_Complete                     0x0C
+#define HCI_EVT_Read_Remote_Version_Complete 0x0C
 struct hciEvtReadRemoteVersionComplete {
 	uint8_t status;
 	uint16_t conn;
@@ -2534,7 +2618,7 @@ struct hciEvtReadRemoteVersionComplete {
 	uint16_t lmpSubversion;
 } __packed;
 
-#define HCI_EVT_QOS_Setup_Complete                               0x0D
+#define HCI_EVT_QOS_Setup_Complete 0x0D
 struct hciEvtQosSetupComplete {
 	uint8_t status;
 	uint16_t conn;
@@ -2546,37 +2630,37 @@ struct hciEvtQosSetupComplete {
 	uint32_t delayVariation;
 } __packed;
 
-#define HCI_EVT_Command_Complete                                 0x0E
+#define HCI_EVT_Command_Complete 0x0E
 struct hciEvtCmdComplete {
 	uint8_t numCmdCredits;
 	uint16_t opcode;
 } __packed;
 
-#define HCI_EVT_Command_Status                                   0x0F
+#define HCI_EVT_Command_Status 0x0F
 struct hciEvtCmdStatus {
 	uint8_t status;
 	uint8_t numCmdCredits;
 	uint16_t opcode;
 } __packed;
 
-#define HCI_EVT_Hardware_Error                                   0x10
+#define HCI_EVT_Hardware_Error 0x10
 struct hciEvtHwError {
 	uint8_t errCode;
 } __packed;
 
-#define HCI_EVT_Flush_Occurred                                   0x11
+#define HCI_EVT_Flush_Occurred 0x11
 struct hciEvtFlushOccurred {
 	uint16_t conn;
 } __packed;
 
-#define HCI_EVT_Role_Change                                      0x12
+#define HCI_EVT_Role_Change 0x12
 struct hciEvtRoleChange {
 	uint8_t status;
 	uint8_t mac[6];
 	uint8_t amSlave;
 } __packed;
 
-#define HCI_EVT_Number_Of_Completed_Packets                      0x13
+#define HCI_EVT_Number_Of_Completed_Packets 0x13
 struct hciEvtNumCompletedPacketsItem {
 	uint16_t conn;
 	uint16_t numPackets;
@@ -2586,7 +2670,7 @@ struct hciEvtNumCompletedPackets {
 	struct hciEvtNumCompletedPacketsItem items[];
 } __packed;
 
-#define HCI_EVT_Mode_Change                                      0x14
+#define HCI_EVT_Mode_Change 0x14
 struct hciEvtModeChange {
 	uint8_t status;
 	uint16_t conn;
@@ -2594,7 +2678,7 @@ struct hciEvtModeChange {
 	uint16_t interval; /* in units of 0.625ms 0..0xffff */
 } __packed;
 
-#define HCI_EVT_Return_Link_Keys                                 0x15
+#define HCI_EVT_Return_Link_Keys 0x15
 struct hciEvtReturnLinkKeysItem {
 	uint8_t mac[6];
 	uint8_t key[16];
@@ -2604,72 +2688,71 @@ struct hciEvtReturnLinkKeys {
 	struct hciEvtReturnLinkKeysItem items[];
 } __packed;
 
-#define HCI_EVT_PIN_Code_Request                                 0x16
+#define HCI_EVT_PIN_Code_Request 0x16
 struct hciEvtPinCodeReq {
 	uint8_t mac[6];
 } __packed;
 
-#define HCI_EVT_Link_Key_Request                                 0x17
+#define HCI_EVT_Link_Key_Request 0x17
 struct hciEvtLinkKeyReq {
 	uint8_t mac[6];
 } __packed;
 
-#define HCI_EVT_Link_Key_Notification                            0x18
+#define HCI_EVT_Link_Key_Notification 0x18
 struct hciEvtLinkKeyNotif {
 	uint8_t mac[6];
 	uint8_t key[16];
 	uint8_t keyType; /* HCI_KEY_TYPE_ */
 } __packed;
 
-#define HCI_EVT_Loopback_Command                                 0x19
+#define HCI_EVT_Loopback_Command 0x19
 /* data is the sent command, up to 252 bytes of it */
 
-#define HCI_EVT_Data_Buffer_Overflow                             0x1A
+#define HCI_EVT_Data_Buffer_Overflow 0x1A
 struct hciEvtDataBufferOverflow {
 	uint8_t aclLink;
 } __packed;
 
-#define HCI_EVT_Max_Slots_Change                                 0x1B
+#define HCI_EVT_Max_Slots_Change 0x1B
 struct hciEvtMaxSlotsChange {
 	uint16_t conn;
 	uint8_t lmpMaxSlots;
 } __packed;
 
-#define HCI_EVT_Read_Clock_Offset_Complete                       0x1C
+#define HCI_EVT_Read_Clock_Offset_Complete 0x1C
 struct hciEvtReadClockOffsetComplete {
 	uint8_t status;
 	uint16_t conn;
 	uint16_t clockOffset;
 } __packed;
 
-#define HCI_EVT_Connection_Packet_Type_Changed                   0x1D
+#define HCI_EVT_Connection_Packet_Type_Changed 0x1D
 struct hciEvtConnPacketTypeChanged {
 	uint8_t status;
 	uint16_t conn;
 	uint16_t packetsAllowed; /* HCI_PKT_TYP_* */
 } __packed;
 
-#define HCI_EVT_QoS_Violation                                    0x1E
+#define HCI_EVT_QoS_Violation 0x1E
 struct hciEvtQosViolation {
 	uint16_t conn;
 } __packed;
 
-#define HCI_EVT_Page_Scan_Mode_Change                            0x1F /* deprecated in BT 1.2+ */
+#define HCI_EVT_Page_Scan_Mode_Change 0x1F /* deprecated in BT 1.2+ */
 struct hciEvtPsmChange {
 	uint8_t mac[6];
 	uint8_t PSM;
 } __packed;
 
-#define HCI_EVT_Page_Scan_Repetition_Mode_Change                 0x20
+#define HCI_EVT_Page_Scan_Repetition_Mode_Change 0x20
 struct hciEvtPrsmChange {
 	uint8_t mac[6];
 	uint8_t PSRM;
 } __packed;
 
-
 /* ==== BT 1.2 ==== */
 
-#define HCI_EVT_Flow_Specification_Complete                      0x21
+#define HCI_EVT_Flow_Specification_Complete 0x21
 struct hciEvtFlowSpecComplete {
 	uint8_t status;
 	uint16_t conn;
@@ -2681,7 +2764,7 @@ struct hciEvtFlowSpecComplete {
 	uint32_t latency;
 } __packed;
 
-#define HCI_EVT_Inquiry_Result_With_RSSI                         0x22
+#define HCI_EVT_Inquiry_Result_With_RSSI 0x22
 struct hciEvtInquiryResultWithRssiItem {
 	uint8_t mac[6];
 	uint8_t PSRM;
@@ -2695,7 +2778,7 @@ struct hciEvtInquiryResultWithRssi {
 	struct hciEvtInquiryResultWithRssiItem items[];
 } __packed;
 
-#define HCI_EVT_Read_Remote_Extended_Features_Complete           0x23
+#define HCI_EVT_Read_Remote_Extended_Features_Complete 0x23
 struct hciEvtReadRemoteExtFeturesComplete {
 	uint8_t status;
 	uint16_t conn;
@@ -2704,7 +2787,7 @@ struct hciEvtReadRemoteExtFeturesComplete {
 	uint64_t extLmpFeatures; /* HCI_LMP_EXT_FTR_P* & HCI_LMP_FTR_* */
 } __packed;
 
-#define HCI_EVT_Synchronous_Connection_Complete                  0x2C
+#define HCI_EVT_Synchronous_Connection_Complete 0x2C
 struct hciEvtSyncConnComplete {
 	uint8_t status;
 	uint16_t conn;
@@ -2717,7 +2800,7 @@ struct hciEvtSyncConnComplete {
 	uint8_t airMode; /* HCI_SCO_AIR_MODE_* */
 } __packed;
 
-#define HCI_EVT_Synchronous_Connection_Changed                   0x2D
+#define HCI_EVT_Synchronous_Connection_Changed 0x2D
 struct hciEvtSyncConnChanged {
 	uint8_t status;
 	uint16_t conn;
@@ -2727,10 +2810,9 @@ struct hciEvtSyncConnChanged {
 	uint16_t txPacketLen;
 } __packed;
 
-
 /* ==== BT 2.1 ==== */
 
-#define HCI_EVT_Sniff_Subrating                                  0x2E
+#define HCI_EVT_Sniff_Subrating 0x2E
 struct hciEvtSniffSubrating {
 	uint8_t status;
 	uint16_t conn;
@@ -2740,7 +2822,7 @@ struct hciEvtSniffSubrating {
 	uint16_t minLocalTimeout;
 } __packed;
 
-#define HCI_EVT_Extended_Inquiry_Result                          0x2F
+#define HCI_EVT_Extended_Inquiry_Result 0x2F
 struct hciEvtExtendedInquiryResult {
 	uint8_t numResponses; /* must be 1 */
 	uint8_t mac[6];
@@ -2752,18 +2834,18 @@ struct hciEvtExtendedInquiryResult {
 	uint8_t EIR[240];
 } __packed;
 
-#define HCI_EVT_Encryption_Key_Refresh_Complete                  0x30
+#define HCI_EVT_Encryption_Key_Refresh_Complete 0x30
 struct hciEvtEncrKeyRefreshComplete {
 	uint8_t status;
 	uint16_t conn;
 } __packed;
 
-#define HCI_EVT_IO_Capability_Request                            0x31
+#define HCI_EVT_IO_Capability_Request 0x31
 struct hciEvtIoCapRequest {
 	uint8_t mac[6];
 } __packed;
 
-#define HCI_EVT_IO_Capability_Response                           0x32
+#define HCI_EVT_IO_Capability_Response 0x32
 struct hciEvtIoCapResponse {
 	uint8_t mac[6];
 	uint8_t ioCapability; /* HCI_DISPLAY_CAP_* */
@@ -2771,90 +2853,89 @@ struct hciEvtIoCapResponse {
 	uint8_t authReqments; /* HCI_AUTH_REQMENT_ */
 } __packed;
 
-#define HCI_EVT_User_Confirmation_Request                        0x33
+#define HCI_EVT_User_Confirmation_Request 0x33
 struct hciEvtUserConfRequest {
 	uint8_t mac[6];
 	uint32_t numericValue;
 } __packed;
 
-#define HCI_EVT_User_Passkey_Request                             0x34
+#define HCI_EVT_User_Passkey_Request 0x34
 struct hciEvtUserPasskeyRequest {
 	uint8_t mac[6];
 } __packed;
 
-#define HCI_EVT_Remote_OOB_Data_Request                          0x35
+#define HCI_EVT_Remote_OOB_Data_Request 0x35
 struct hciEvtRemoteOobRequest {
 	uint8_t mac[6];
 } __packed;
 
-#define HCI_EVT_Simple_Pairing_Complete                          0x36
+#define HCI_EVT_Simple_Pairing_Complete 0x36
 struct hciEvtSimplePairingComplete {
 	uint8_t status;
 	uint8_t mac[6];
 } __packed;
 
-#define HCI_EVT_Link_Supervision_Timeout_Changed                 0x38
+#define HCI_EVT_Link_Supervision_Timeout_Changed 0x38
 struct hciEvtLinkSupervisionTimeoutChanged {
 	uint16_t conn;
 	uint16_t timeout; /* in units of 0.625 ms 1..0xffff */
 } __packed;
 
-#define HCI_EVT_Enhanced_Flush_Complete                          0x39
+#define HCI_EVT_Enhanced_Flush_Complete 0x39
 struct hciEvtEnahncedFlushComplete {
 	uint16_t conn;
 } __packed;
 
-#define HCI_EVT_User_Passkey_Notification                        0x3B
+#define HCI_EVT_User_Passkey_Notification 0x3B
 struct hciEvtUserPasskeyNotif {
 	uint8_t mac[6];
 	uint32_t passkey;
 } __packed;
 
-#define HCI_EVT_Keypress_Notification                            0x3C
+#define HCI_EVT_Keypress_Notification 0x3C
 struct hciEvtKeypressNotification {
 	uint8_t mac[6];
 	uint8_t notifType; /* HCI_SSP_KEY_ENTRY_* */
 } __packed;
 
-#define HCI_EVT_Remote_Host_Supported_Features_Notification      0x3D
+#define HCI_EVT_Remote_Host_Supported_Features_Notification 0x3D
 struct hciEvtRemoteHostSupportedFeatures {
 	uint8_t mac[6];
 	uint64_t hostSupportedFeatures; /* HCI_LMP_FTR_* */
 } __packed;
 
-
 /* ==== BT 3.0 ==== */
 
-#define HCI_EVT_Physical_Link_Complete                           0x40
+#define HCI_EVT_Physical_Link_Complete 0x40
 struct hciEvtPhysLinkComplete {
 	uint8_t status;
 	uint8_t physLinkHandle;
 } __packed;
 
-#define HIC_EVT_Channel_Selected                                 0x41
+#define HIC_EVT_Channel_Selected 0x41
 struct hciEvtChannelSelected {
 	uint8_t physLinkHandle;
 } __packed;
 
-#define HCI_EVT_Disconnection_Physical_Link_Complete             0x42
+#define HCI_EVT_Disconnection_Physical_Link_Complete 0x42
 struct hciEvtDiscPhysLinkComplete {
 	uint8_t status;
 	uint8_t physLinkHandle;
 	uint8_t reason;
 } __packed;
 
-#define HCI_EVT_Physical_Link_Loss_Early_Warning                 0x43
+#define HCI_EVT_Physical_Link_Loss_Early_Warning 0x43
 struct hciEvtDiscPhysLinkLossEralyWarning {
 	uint8_t physLinkHandle;
 	uint8_t lossReason;
 } __packed;
 
-#define HCI_EVT_Physical_Link_Recovery                           0x44
+#define HCI_EVT_Physical_Link_Recovery 0x44
 struct hciEvtDiscPhysLinkRecovery {
 	uint8_t physLinkHandle;
 } __packed;
 
-#define HCI_EVT_Logical_Link_Complete                            0x45
+#define HCI_EVT_Logical_Link_Complete 0x45
 struct hciEvtLogicalLinkComplete {
 	uint8_t status;
 	uint16_t logicalLinkHandle;
@@ -2862,20 +2943,20 @@ struct hciEvtLogicalLinkComplete {
 	uint8_t txFlowSpecID;
 } __packed;
 
-#define HCI_EVT_Disconnection_Logical_Link_Complete              0x46
+#define HCI_EVT_Disconnection_Logical_Link_Complete 0x46
 struct hciEvtDiscLogicalLinkComplete {
 	uint8_t status;
 	uint16_t logicalLinkHandle;
 	uint8_t reason;
 } __packed;
 
-#define HCI_EVT_Flow_Spec_Modify_Complete                        0x47
+#define HCI_EVT_Flow_Spec_Modify_Complete 0x47
 struct hciEvtFlowSpecModifyComplete {
 	uint8_t status;
 	uint16_t conn;
 } __packed;
 
-#define HCI_EVT_Number_Of_Completed_Data_Blocks                  0x48
+#define HCI_EVT_Number_Of_Completed_Data_Blocks 0x48
 struct hciEvtNumCompletedDataBlocksItem {
 	uint16_t conn;
 	uint16_t numPackets;
@@ -2886,19 +2967,19 @@ struct hciEvtNumCompletedDataBlocks {
 	struct hciEvtNumCompletedDataBlocksItem items[];
 } __packed;
 
-#define HCI_EVT_AMP_Start_Test                                   0x49
+#define HCI_EVT_AMP_Start_Test 0x49
 struct hciEvtAmpStartTest {
 	uint8_t status;
 	uint8_t scenario;
 } __packed;
 
-#define HCI_EVT_AMP_Test_End                                     0x4A
+#define HCI_EVT_AMP_Test_End 0x4A
 struct hciEvtAmpTestEnd {
 	uint8_t status;
 	uint8_t scenario;
 } __packed;
 
-#define HCI_EVT_AMP_Receiver_Report                              0x4B
+#define HCI_EVT_AMP_Receiver_Report 0x4B
 struct hciEvtampReceiverReport {
 	uint8_t controllerType;
 	uint8_t reason;
@@ -2909,28 +2990,27 @@ struct hciEvtampReceiverReport {
 	uint32_t numberOfErrorBits;
 } __packed;
 
-#define HCI_EVT_Short_Range_Mode_Change_Complete                 0x4C
+#define HCI_EVT_Short_Range_Mode_Change_Complete 0x4C
 struct hciEvtshortRangeModeChangeComplete {
 	uint8_t status;
 	uint8_t physLinkHandle;
 	uint8_t shortRangeModeOn;
 } __packed;
 
-#define HCI_EVT_AMP_Status_Change                                0x4D
+#define HCI_EVT_AMP_Status_Change 0x4D
 struct hciEvtAmpStatusChange {
 	uint8_t status;
 	uint8_t ampStatus;
 } __packed;
 
-
 /* ==== BT 4.0 ==== */
 
-#define HCI_EVT_LE_Meta                                          0x3E
+#define HCI_EVT_LE_Meta 0x3E
 struct hciEvtLeMeta {
 	uint8_t subevent;
 } __packed;
 
-#define HCI_EVTLE_Connection_Complete                            0x01
+#define HCI_EVTLE_Connection_Complete 0x01
 struct hciEvtLeConnectionComplete {
 	uint8_t status;
 	uint16_t conn;
@@ -2943,21 +3023,23 @@ struct hciEvtLeConnectionComplete {
 	uint8_t masterClockAccuracy; /* HCI_MCA_* */
 } __packed;
 
-#define HCI_EVTLE_Advertising_Report                             0x02
+#define HCI_EVTLE_Advertising_Report 0x02
 struct hciEvtLeAdvReportItem {
 	uint8_t advType; /* HCI_ADV_TYPE_* */
 	uint8_t randomAddr;
 	uint8_t mac[6];
 	uint8_t dataLen;
 	uint8_t data[];
-/*  int8_t RSSI <-- this cannot be here due to variable data len, but in reality it is there */
+	/*  int8_t RSSI <-- this cannot be here due to variable data len, but in
+	 * reality it is there */
 } __packed;
 struct hciEvtLeAdvReport {
 	uint8_t numReports;
-	/* struct hciEvtLeAdvReportItem items[]; <- this cannot be here since data length is variable */
+	/* struct hciEvtLeAdvReportItem items[]; <- this cannot be here since
+	 * data length is variable */
 } __packed;
 
-#define HCI_EVTLE_Connection_Update_Complete                     0x03
+#define HCI_EVTLE_Connection_Update_Complete 0x03
 struct hciEvtLeConnectionUpdateComplete {
 	uint8_t status;
 	uint16_t conn;
@@ -2966,24 +3048,23 @@ struct hciEvtLeConnectionUpdateComplete {
 	uint16_t supervisionTimeout; /* inunit sof 10ms, 0xA..0x0C80 */
 } __packed;
 
-#define HCI_EVTLE_Read_Remote_Used_Features_Complete             0x04
+#define HCI_EVTLE_Read_Remote_Used_Features_Complete 0x04
 struct hciEvtLeReadRemoteFeaturesComplete {
 	uint8_t status;
 	uint16_t conn;
 	uint64_t leFeatures; /* bitmask of HCI_LE_FTR_* */
 } __packed;
 
-#define HCI_EVTLE_LTK_Request                                    0x05
+#define HCI_EVTLE_LTK_Request 0x05
 struct hciEvtLeLtkRequest {
 	uint16_t conn;
 	uint64_t randomNum;
 	uint16_t diversifier;
 } __packed;
 
-
 /* ==== BT 4.1 ==== */
 
-#define HCI_EVTLE_Read_Remote_Connection_Parameter_Request       0x06
+#define HCI_EVTLE_Read_Remote_Connection_Parameter_Request 0x06
 struct hciEvtLeReadRemoteConnParamRequest {
 	uint16_t conn;
 	uint16_t connIntervalMin; /* in units of 1.25 ms 6..0x0C80 */
@@ -2992,7 +3073,7 @@ struct hciEvtLeReadRemoteConnParamRequest {
 	uint16_t supervisionTimeout; /* inunit sof 10ms, 0xA..0x0C80 */
 } __packed;
 
-#define HCI_EVT_Triggered_Clock_Capture                          0x4E
+#define HCI_EVT_Triggered_Clock_Capture 0x4E
 struct hciEvtTriggeredClockCapture {
 	uint16_t conn;
 	uint8_t piconetClock;
@@ -3000,12 +3081,12 @@ struct hciEvtTriggeredClockCapture {
 	uint16_t slotOffset;
 } __packed;
 
-#define HCI_EVT_Synchronization_Train_Complete                   0x4F
+#define HCI_EVT_Synchronization_Train_Complete 0x4F
 struct hciEvtSyncTrainComplete {
 	uint8_t status;
 } __packed;
 
-#define HCI_EVT_Synchronization_Train_Received                   0x50
+#define HCI_EVT_Synchronization_Train_Received 0x50
 struct hciEvtSyncTrainReceived {
 	uint8_t status;
 	uint8_t mac[6];
@@ -3017,7 +3098,7 @@ struct hciEvtSyncTrainReceived {
 	uint8_t serviceData;
 } __packed;
 
-#define HCI_EVT_Connectionless_Slave_Broadcast_Receive           0x51
+#define HCI_EVT_Connectionless_Slave_Broadcast_Receive 0x51
 struct hciEvtConnectionlessSlaveBroadcastReceive {
 	uint8_t mac[6];
 	uint8_t ltAddr;
@@ -3029,127 +3110,116 @@ struct hciEvtConnectionlessSlaveBroadcastReceive {
 	/* data */
 } __packed;
 
-#define HCI_EVT_Connectionless_Slave_Broadcast_Timeout           0x52
+#define HCI_EVT_Connectionless_Slave_Broadcast_Timeout 0x52
 struct hciEvtConnectionlessSlaveBroadcastTimeout {
 	uint8_t mac[6];
 	uint8_t ltAddr;
 } __packed;
 
-#define HCI_EVT_Truncated_Page_Complete                          0x53
+#define HCI_EVT_Truncated_Page_Complete 0x53
 struct hciEvtTruncatedPageComplete {
 	uint8_t status;
 	uint8_t mac[6];
 } __packed;
 
-#define HCI_EVT_Slave_Page_Response_Timeout                      0x54
+#define HCI_EVT_Slave_Page_Response_Timeout 0x54
 
-#define HCI_EVT_Connless_Slave_Broadcast_Channel_Map_Change      0x55
+#define HCI_EVT_Connless_Slave_Broadcast_Channel_Map_Change 0x55
 struct hciEvtConnlessSlaveBroadcastChannelMapChange {
 	uint8_t map[10];
 } __packed;
 
-#define HCI_EVT_Inquiry_Response_Notification                    0x56
+#define HCI_EVT_Inquiry_Response_Notification 0x56
 struct hciEvtInquiryResponseNotif {
 	uint8_t lap[3];
 	uint8_t RSSI; /* actually an int8_t */
 } __packed;
 
-#define HCI_EVT_Authenticated_Payload_Timeout_Expired            0x57
+#define HCI_EVT_Authenticated_Payload_Timeout_Expired 0x57
 struct hciEvtAuthedPayloadTimeoutExpired {
 	uint16_t conn;
 } __packed;
 
-
-
-
-
 /* ERROR CODES */
 
 /* ==== BT 1.1 ==== */
 
-#define HCI_SUCCESS                                              0x00
-#define HCI_ERR_Unknown_HCI_Command                              0x01
-#define HCI_ERR_No_Connection                                    0x02
-#define HCI_ERR_Hardware_Failure                                 0x03
-#define HCI_ERR_Page_Timeout                                     0x04
-#define HCI_ERR_Authentication_Failure                           0x05
-#define HCI_ERR_Key_Missing                                      0x06
-#define HCI_ERR_Memory_Full                                      0x07
-#define HCI_ERR_Connection_Timeout                               0x08
-#define HCI_ERR_Max_Number_Of_Connections                        0x09
-#define HCI_ERR_Max_Number_Of_SCO_Connections_To_A_Device        0x0A
-#define HCI_ERR_ACL_Connection_Already_Exists                    0x0B
-#define HCI_ERR_Command_Disallowed                               0x0C
-#define HCI_ERR_Host_Rejected_Due_To_Limited_Resources           0x0D
-#define HCI_ERR_Host_Rejected_Due_To_Security_Reasons            0x0E
-#define HCI_ERR_Host_Rejected_Remote_Device_Personal_Device      0x0F
-#define HCI_ERR_Host_Timeout                                     0x10
-#define HCI_ERR_Unsupported_Feature_Or_Parameter_Value           0x11
-#define HCI_ERR_Invalid_HCI_Command_Parameters                   0x12
-#define HCI_ERR_Other_End_Terminated_Connection_User_Requested   0x13
-#define HCI_ERR_Other_End_Terminated_Connection_Low_Resources    0x14
-#define HCI_ERR_Other_End_Terminated_Connection_Soon_Power_Off   0x15
-#define HCI_ERR_Connection_Terminated_By_Local_Host              0x16
-#define HCI_ERR_Repeated_Attempts                                0x17
-#define HCI_ERR_Pairing_Not_Allowed                              0x18
-#define HCI_ERR_Unknown_LMP_PDU                                  0x19
-#define HCI_ERR_Unsupported_Remote_Feature                       0x1A
-#define HCI_ERR_SCO_Offset_Rejected                              0x1B
-#define HCI_ERR_SCO_Interval_Rejected                            0x1C
-#define HCI_ERR_SCO_Air_Mode_Rejected                            0x1D
-#define HCI_ERR_Invalid_LMP_Parameters                           0x1E
-#define HCI_ERR_Unspecified_Error                                0x1F
-#define HCI_ERR_Unsupported_LMP_Parameter                        0x20
-#define HCI_ERR_Role_Change_Not_Allowed                          0x21
-#define HCI_ERR_LMP_Response_Timeout                             0x22
-#define HCI_ERR_LMP_Error_Transaction_Collision                  0x23
-#define HCI_ERR_LMP_PDU_Not_Allowed                              0x24
-#define HCI_ERR_Encryption_Mode_Not_Acceptable                   0x25
-#define HCI_ERR_Unit_Key_Used                                    0x26
-#define HCI_ERR_QoS_Not_Supported                                0x27
-#define HCI_ERR_Instant_Passed                                   0x28
-#define HCI_ERR_Pairing_With_Unit_Key_Not_Supported              0x29
-
+#define HCI_SUCCESS 0x00
+#define HCI_ERR_Unknown_HCI_Command 0x01
+#define HCI_ERR_No_Connection 0x02
+#define HCI_ERR_Hardware_Failure 0x03
+#define HCI_ERR_Page_Timeout 0x04
+#define HCI_ERR_Authentication_Failure 0x05
+#define HCI_ERR_Key_Missing 0x06
+#define HCI_ERR_Memory_Full 0x07
+#define HCI_ERR_Connection_Timeout 0x08
+#define HCI_ERR_Max_Number_Of_Connections 0x09
+#define HCI_ERR_Max_Number_Of_SCO_Connections_To_A_Device 0x0A
+#define HCI_ERR_ACL_Connection_Already_Exists 0x0B
+#define HCI_ERR_Command_Disallowed 0x0C
+#define HCI_ERR_Host_Rejected_Due_To_Limited_Resources 0x0D
+#define HCI_ERR_Host_Rejected_Due_To_Security_Reasons 0x0E
+#define HCI_ERR_Host_Rejected_Remote_Device_Personal_Device 0x0F
+#define HCI_ERR_Host_Timeout 0x10
+#define HCI_ERR_Unsupported_Feature_Or_Parameter_Value 0x11
+#define HCI_ERR_Invalid_HCI_Command_Parameters 0x12
+#define HCI_ERR_Other_End_Terminated_Connection_User_Requested 0x13
+#define HCI_ERR_Other_End_Terminated_Connection_Low_Resources 0x14
+#define HCI_ERR_Other_End_Terminated_Connection_Soon_Power_Off 0x15
+#define HCI_ERR_Connection_Terminated_By_Local_Host 0x16
+#define HCI_ERR_Repeated_Attempts 0x17
+#define HCI_ERR_Pairing_Not_Allowed 0x18
+#define HCI_ERR_Unknown_LMP_PDU 0x19
+#define HCI_ERR_Unsupported_Remote_Feature 0x1A
+#define HCI_ERR_SCO_Offset_Rejected 0x1B
+#define HCI_ERR_SCO_Interval_Rejected 0x1C
+#define HCI_ERR_SCO_Air_Mode_Rejected 0x1D
+#define HCI_ERR_Invalid_LMP_Parameters 0x1E
+#define HCI_ERR_Unspecified_Error 0x1F
+#define HCI_ERR_Unsupported_LMP_Parameter 0x20
+#define HCI_ERR_Role_Change_Not_Allowed 0x21
+#define HCI_ERR_LMP_Response_Timeout 0x22
+#define HCI_ERR_LMP_Error_Transaction_Collision 0x23
+#define HCI_ERR_LMP_PDU_Not_Allowed 0x24
+#define HCI_ERR_Encryption_Mode_Not_Acceptable 0x25
+#define HCI_ERR_Unit_Key_Used 0x26
+#define HCI_ERR_QoS_Not_Supported 0x27
+#define HCI_ERR_Instant_Passed 0x28
+#define HCI_ERR_Pairing_With_Unit_Key_Not_Supported 0x29
 
 /* ==== BT 1.2 ==== */
 
-#define HCI_ERR_Different_Transaction_Collision                  0x2A
-#define HCI_ERR_QoS_Unacceptable_Parameter                       0x2C
-#define HCI_ERR_QoS_Rejected                                     0x2D
-#define HCI_ERR_Channel_Classification_Not_Supported             0x2E
-#define HCI_ERR_Insufficient_Security                            0x2F
-#define HCI_ERR_Parameter_Out_Of_Mandatory_Range                 0x30
-#define HCI_ERR_Role_Switch_Pending                              0x33
-#define HCI_ERR_Reserved_Slot_Violation                          0x34
-#define HIC_ERR_Role_Switch_Failed                               0x35
-
+#define HCI_ERR_Different_Transaction_Collision 0x2A
+#define HCI_ERR_QoS_Unacceptable_Parameter 0x2C
+#define HCI_ERR_QoS_Rejected 0x2D
+#define HCI_ERR_Channel_Classification_Not_Supported 0x2E
+#define HCI_ERR_Insufficient_Security 0x2F
+#define HCI_ERR_Parameter_Out_Of_Mandatory_Range 0x30
+#define HCI_ERR_Role_Switch_Pending 0x33
+#define HCI_ERR_Reserved_Slot_Violation 0x34
+#define HIC_ERR_Role_Switch_Failed 0x35
 
 /* ==== BT 2.1 ==== */
 
-#define HCI_ERR_EIR_Too_Large                                    0x36
-#define HCI_ERR_SSP_Not_Supported_By_Host                        0x37
-#define HCI_ERR_Host_Busy_Pairing                                0x38
-
+#define HCI_ERR_EIR_Too_Large 0x36
+#define HCI_ERR_SSP_Not_Supported_By_Host 0x37
+#define HCI_ERR_Host_Busy_Pairing 0x38
 
 /* ==== BT 3.0 ==== */
 
-#define HCI_ERR_Connection_Rejected_No_Suitable_Channel_Found    0x39
-#define HCI_ERR_Controller_Busy                                  0x3A
-
+#define HCI_ERR_Connection_Rejected_No_Suitable_Channel_Found 0x39
+#define HCI_ERR_Controller_Busy 0x3A
 
 /* ==== BT 4.0 ==== */
 
-#define HCI_ERR_Unacceptable_Connection_Interval                 0x3B
-#define HCI_ERR_Directed_Advertising_Timeout                     0x3C
-#define HCI_ERR_Connection_Terminated_Due_To_MIC_Failure         0x3D
-#define HCI_ERR_Connection_Failed_To_To_Established              0x3E
-#define HCI_ERR_MAC_Connection_Failed                            0x3F
-
+#define HCI_ERR_Unacceptable_Connection_Interval 0x3B
+#define HCI_ERR_Directed_Advertising_Timeout 0x3C
+#define HCI_ERR_Connection_Terminated_Due_To_MIC_Failure 0x3D
+#define HCI_ERR_Connection_Failed_To_To_Established 0x3E
+#define HCI_ERR_MAC_Connection_Failed 0x3F
 
 /* ==== BT 4.1 ==== */
 
-#define HCI_ERR_CoarseClock_AdjFailed_Will_Try_clock_Dragging    0x40
-
-
+#define HCI_ERR_CoarseClock_AdjFailed_Will_Try_clock_Dragging 0x40
 
 #endif
diff --git a/include/button.h b/include/button.h
index 30d2969e8c..937b280876 100644
--- a/include/button.h
+++ b/include/button.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,9 +13,8 @@
 #include "gpio_signal.h"
 #include "ec_commands.h"
 
-#define BUTTON_FLAG_ACTIVE_HIGH  BIT(0)
-#define BUTTON_FLAG_DISABLED     BIT(1)   /* Button disabled */
-
+#define BUTTON_FLAG_ACTIVE_HIGH BIT(0)
+#define BUTTON_FLAG_DISABLED BIT(1) /* Button disabled */
 
 #define BUTTON_DEBOUNCE_US (30 * MSEC)
 
@@ -103,4 +102,4 @@ int button_is_adc_detected(enum gpio_signal gpio);
  */
 int adc_to_physical_value(enum gpio_signal gpio);
 
-#endif  /* __CROS_EC_BUTTON_H */
+#endif /* __CROS_EC_BUTTON_H */
diff --git a/include/byteorder.h b/include/byteorder.h
index 8cfd810e54..7a47cbde65 100644
--- a/include/byteorder.h
+++ b/include/byteorder.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,4 +8,4 @@
 
 #include <endian.h>
 
-#endif  /* __EC_INCLUDE_BYTEORDER_H */
+#endif /* __EC_INCLUDE_BYTEORDER_H */
diff --git a/include/capsense.h b/include/capsense.h
index 2c0734aa4d..cb967c595e 100644
--- a/include/capsense.h
+++ b/include/capsense.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,4 +11,4 @@
 
 void capsense_interrupt(enum gpio_signal signal);
 
-#endif  /* __CROS_EC_CAPSENSE_H */
+#endif /* __CROS_EC_CAPSENSE_H */
diff --git a/include/case_closed_debug.h b/include/case_closed_debug.h
index 53c8b1ed17..ebca79fdc0 100644
--- a/include/case_closed_debug.h
+++ b/include/case_closed_debug.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/include/cec.h b/include/cec.h
index b1ac6dbbb0..006eeffe6a 100644
--- a/include/cec.h
+++ b/include/cec.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/charge_manager.h b/include/charge_manager.h
index b6d3c235bf..ccef9d8814 100644
--- a/include/charge_manager.h
+++ b/include/charge_manager.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,7 +19,7 @@
 
 /* Only track BC1.2 charge current if we support BC1.2 charging */
 #if defined(HAS_TASK_USB_CHG) || defined(HAS_TASK_USB_CHG_P0) || \
-	defined(CONFIG_PLATFORM_EC_USB_CHARGER_SINGLE_TASK) || \
+	defined(CONFIG_PLATFORM_EC_USB_CHARGER_SINGLE_TASK) ||   \
 	defined(TEST_BUILD)
 #define CHARGE_MANAGER_BC12
 #endif
@@ -28,9 +28,12 @@
  * Time to delay for detecting the charger type (must be long enough for BC1.2
  * driver to get supplier information and notify charge manager).
  */
-#define CHARGE_DETECT_DELAY (2*SECOND)
+#define CHARGE_DETECT_DELAY (2 * SECOND)
 
-/* Commonly-used charge suppliers listed in no particular order */
+/*
+ * Commonly-used charge suppliers listed in no particular order.
+ * Don't forget to update CHARGE_SUPPLIER_NAME and supplier_priority.
+ */
 enum charge_supplier {
 	CHARGE_SUPPLIER_NONE = -1,
 	CHARGE_SUPPLIER_PD,
@@ -48,14 +51,34 @@ enum charge_supplier {
 #if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
 	CHARGE_SUPPLIER_DEDICATED,
 #endif
-#ifdef CONFIG_WIRELESS_CHARGER_P9221_R7
-	CHARGE_SUPPLIER_WPC_BPP,
-	CHARGE_SUPPLIER_WPC_EPP,
-	CHARGE_SUPPLIER_WPC_GPP,
-#endif
 	CHARGE_SUPPLIER_COUNT
 };
 
+#ifdef CHARGE_MANAGER_BC12
+#define CHARGE_SUPPLIER_NAME_BC12                          \
+	[CHARGE_SUPPLIER_BC12_DCP] = "BC12_DCP",           \
+	[CHARGE_SUPPLIER_BC12_CDP] = "BC12_CDP",           \
+	[CHARGE_SUPPLIER_BC12_SDP] = "BC12_SDP",           \
+	[CHARGE_SUPPLIER_PROPRIETARY] = "BC12_PROP",       \
+	[CHARGE_SUPPLIER_TYPEC_UNDER_1_5A] = "USBC_U1_5A", \
+	[CHARGE_SUPPLIER_OTHER] = "BC12_OTHER", [CHARGE_SUPPLIER_VBUS] = "VBUS",
+#else
+#define CHARGE_SUPPLIER_NAME_BC12
+#endif
+#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
+#define CHARGE_SUPPLIER_NAME_DEDICATED \
+	[CHARGE_SUPPLIER_DEDICATED] = "DEDICATED",
+#else
+#define CHARGE_SUPPLIER_NAME_DEDICATED
+#endif
+#define CHARGE_SUPPLIER_NAME_QI
+
+#define CHARGE_SUPPLIER_NAME                                           \
+	[CHARGE_SUPPLIER_PD] = "PD", [CHARGE_SUPPLIER_TYPEC] = "USBC", \
+	[CHARGE_SUPPLIER_TYPEC_DTS] = "USBC_DTS",                      \
+	CHARGE_SUPPLIER_NAME_BC12 CHARGE_SUPPLIER_NAME_DEDICATED       \
+		CHARGE_SUPPLIER_NAME_QI
+
 /*
  * Charge supplier priority: lower number indicates higher priority.
  * Default priority is in charge_manager.c. It can be overridden by boards.
@@ -76,8 +99,7 @@ struct charge_port_info {
  * @param charge	Charge port current / voltage. If NULL, current = 0
  * 			voltage = 0 will be used.
  */
-void charge_manager_update_charge(int supplier,
-				  int port,
+void charge_manager_update_charge(int supplier, int port,
 				  const struct charge_port_info *charge);
 
 /* Partner port dualrole capabilities */
@@ -114,8 +136,8 @@ enum ceil_requestor {
 	CEIL_REQUESTOR_COUNT,
 };
 
-#define CHARGE_PORT_COUNT (CONFIG_USB_PD_PORT_MAX_COUNT + \
-			   CONFIG_DEDICATED_CHARGE_PORT_COUNT)
+#define CHARGE_PORT_COUNT \
+	(CONFIG_USB_PD_PORT_MAX_COUNT + CONFIG_DEDICATED_CHARGE_PORT_COUNT)
 #if (CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0)
 
 /**
@@ -201,7 +223,7 @@ int charge_manager_get_selected_charge_port(void);
  *
  * @return	Power limit (uW).
  */
-int charge_manager_get_power_limit_uw(void);
+test_mockable int charge_manager_get_power_limit_uw(void);
 
 /**
  * Get the charger current (mA) value.
@@ -284,8 +306,8 @@ int board_set_active_charge_port(int charge_port);
  * @param max_ma Maximum charge current limit, >= charge_ma.
  * @param charge_mv Negotiated charge voltage (mV).
  */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv);
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv);
 
 /**
  * Get whether the port is sourcing power on VBUS.
@@ -329,9 +351,8 @@ __override_proto int board_charge_port_is_connected(int port);
  * @param port	Dedicated charge port.
  * @param r	USB PD power info to be updated.
  */
-__override_proto
-void board_fill_source_power_info(int port,
-				  struct ec_response_usb_pd_power_info *r);
+__override_proto void
+board_fill_source_power_info(int port, struct ec_response_usb_pd_power_info *r);
 
 /**
  * Board specific callback to get vbus voltage.
@@ -339,4 +360,7 @@ void board_fill_source_power_info(int port,
  * @param port  Dedicated charge port.
  */
 __override_proto int board_get_vbus_voltage(int port);
+
+int is_pd_port(int port);
+
 #endif /* __CROS_EC_CHARGE_MANAGER_H */
diff --git a/include/charge_ramp.h b/include/charge_ramp.h
index 0745f5ef98..be456a64ec 100644
--- a/include/charge_ramp.h
+++ b/include/charge_ramp.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,10 +11,7 @@
 #include "timer.h"
 
 /* Charge ramp state used for checking VBUS */
-enum chg_ramp_vbus_state {
-	CHG_RAMP_VBUS_RAMPING,
-	CHG_RAMP_VBUS_STABLE
-};
+enum chg_ramp_vbus_state { CHG_RAMP_VBUS_RAMPING, CHG_RAMP_VBUS_STABLE };
 
 /**
  * Check if VBUS is too low
@@ -81,11 +78,15 @@ int chg_ramp_is_detected(void);
  * @voltage Negotiated charge voltage.
  */
 void chg_ramp_charge_supplier_change(int port, int supplier, int current,
-			     timestamp_t registration_time, int voltage);
+				     timestamp_t registration_time,
+				     int voltage);
 
 #else
-static inline void chg_ramp_charge_supplier_change(
-		int port, int supplier, timestamp_t registration_time) { }
+static inline void
+chg_ramp_charge_supplier_change(int port, int supplier,
+				timestamp_t registration_time)
+{
+}
 #endif
 
 #endif /* __CROS_EC_CHARGE_RAMP_H */
diff --git a/include/charge_state.h b/include/charge_state.h
index ed777c1a64..221947b9d1 100644
--- a/include/charge_state.h
+++ b/include/charge_state.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,6 +7,7 @@
 
 #include "common.h"
 #include "timer.h"
+#include "stdbool.h"
 
 /* Stuff that's common to all charger implementations can go here. */
 
@@ -14,14 +15,14 @@
 #define PRECHARGE_TIMEOUT CONFIG_BATTERY_PRECHARGE_TIMEOUT
 
 /* Power state task polling periods in usec */
-#define CHARGE_POLL_PERIOD_VERY_LONG   MINUTE
-#define CHARGE_POLL_PERIOD_LONG        (MSEC * 500)
-#define CHARGE_POLL_PERIOD_CHARGE      (MSEC * 250)
-#define CHARGE_POLL_PERIOD_SHORT       (MSEC * 100)
-#define CHARGE_MIN_SLEEP_USEC          (MSEC * 50)
+#define CHARGE_POLL_PERIOD_VERY_LONG MINUTE
+#define CHARGE_POLL_PERIOD_LONG (MSEC * 500)
+#define CHARGE_POLL_PERIOD_CHARGE (MSEC * 250)
+#define CHARGE_POLL_PERIOD_SHORT (MSEC * 100)
+#define CHARGE_MIN_SLEEP_USEC (MSEC * 50)
 /* If a board hasn't provided a max sleep, use 1 minute as default */
 #ifndef CHARGE_MAX_SLEEP_USEC
-#define CHARGE_MAX_SLEEP_USEC          MINUTE
+#define CHARGE_MAX_SLEEP_USEC MINUTE
 #endif
 
 /* Power states */
@@ -36,6 +37,8 @@ enum charge_state {
 	PWR_STATE_IDLE0,
 	/* Idle; AC present */
 	PWR_STATE_IDLE,
+	/* Forced Idle */
+	PWR_STATE_FORCED_IDLE,
 	/* Discharging */
 	PWR_STATE_DISCHARGE,
 	/* Discharging and fully charged */
@@ -61,20 +64,13 @@ enum charge_state {
 /* Debugging constants, in the same order as enum charge_state. This string
  * table was moved here to sync with enum above.
  */
-#define CHARGE_STATE_NAME_TABLE { \
-		"unchange",	\
-		"init",		\
-		"reinit",	\
-		"idle0",	\
-		"idle",		\
-		"discharge",	\
-		"discharge_full",	\
-		"charge",	\
-		"charge_near_full",      \
-		"error"		\
+#define CHARGE_STATE_NAME_TABLE                                             \
+	{                                                                   \
+		"unchange", "init", "reinit", "idle0", "idle", "discharge", \
+			"discharge_full", "charge", "charge_near_full",     \
+			"error"                                             \
 	}
-	/* End of CHARGE_STATE_NAME_TABLE macro */
-
+/* End of CHARGE_STATE_NAME_TABLE macro */
 
 /**
  * Return current charge state.
@@ -99,7 +95,14 @@ uint32_t charge_get_flags(void);
 /**
  * Return current battery charge percentage.
  */
+#if defined(CONFIG_BATTERY) || defined(TEST_BUILD)
 int charge_get_percent(void);
+#else
+static inline int charge_get_percent(void)
+{
+	return 0;
+}
+#endif
 
 /**
  * Return current battery charge if not using charge manager sub-system.
@@ -124,7 +127,7 @@ __override_proto int charge_is_consuming_full_input_current(void);
 /**
  * Return non-zero if discharging and battery so low we should shut down.
  */
-#ifdef CONFIG_CHARGER
+#if defined(CONFIG_CHARGER) && defined(CONFIG_BATTERY)
 int charge_want_shutdown(void);
 #else
 static inline int charge_want_shutdown(void)
@@ -134,13 +137,41 @@ static inline int charge_want_shutdown(void)
 #endif
 
 /**
+ * Return true if battery level is below threshold, false otherwise,
+ * or if SoC can't be determined.
+ *
+ * @param transitioned	True to check if SoC is previously above threshold
+ */
+enum batt_threshold_type {
+	BATT_THRESHOLD_TYPE_LOW = 0,
+	BATT_THRESHOLD_TYPE_SHUTDOWN
+};
+#if defined(CONFIG_CHARGER) && defined(CONFIG_BATTERY)
+int battery_is_below_threshold(enum batt_threshold_type type,
+			       bool transitioned);
+#else
+static inline int battery_is_below_threshold(enum batt_threshold_type type,
+					     bool transitioned)
+{
+	return 0;
+}
+#endif
+
+/**
  * Return non-zero if the battery level is too low to allow power on, even if
  * a charger is attached.
  *
  * @param power_button_pressed	True if the power-up attempt is caused by a
  *				power button press.
  */
+#ifdef CONFIG_BATTERY
 int charge_prevent_power_on(int power_button_pressed);
+#else
+static inline int charge_prevent_power_on(int power_button_pressed)
+{
+	return 0;
+}
+#endif
 
 /**
  * Get the last polled battery/charger temperature.
@@ -159,8 +190,7 @@ int charge_get_battery_temp(int idx, int *temp_ptr);
  */
 const struct batt_params *charger_current_battery_params(void);
 
-
 /* Config Charger */
 #include "charge_state_v2.h"
 
-#endif	/* __CROS_EC_CHARGE_STATE_H */
+#endif /* __CROS_EC_CHARGE_STATE_H */
diff --git a/include/charge_state_v1.h b/include/charge_state_v1.h
index f5d464b655..302fc0acf8 100644
--- a/include/charge_state_v1.h
+++ b/include/charge_state_v1.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,24 +13,22 @@
 #define CHARGER_UPDATE_PERIOD (SECOND * 10)
 
 /* Power state error flags */
-#define F_CHARGER_INIT        BIT(0) /* Charger initialization */
-#define F_CHARGER_VOLTAGE     BIT(1) /* Charger maximum output voltage */
-#define F_CHARGER_CURRENT     BIT(2) /* Charger maximum output current */
-#define F_BATTERY_VOLTAGE     BIT(3) /* Battery voltage */
-#define F_BATTERY_MODE        BIT(8) /* Battery mode */
-#define F_BATTERY_CAPACITY    BIT(9) /* Battery capacity */
+#define F_CHARGER_INIT BIT(0) /* Charger initialization */
+#define F_CHARGER_VOLTAGE BIT(1) /* Charger maximum output voltage */
+#define F_CHARGER_CURRENT BIT(2) /* Charger maximum output current */
+#define F_BATTERY_VOLTAGE BIT(3) /* Battery voltage */
+#define F_BATTERY_MODE BIT(8) /* Battery mode */
+#define F_BATTERY_CAPACITY BIT(9) /* Battery capacity */
 #define F_BATTERY_STATE_OF_CHARGE BIT(10) /* State of charge, percentage */
-#define F_BATTERY_UNRESPONSIVE    BIT(11) /* Battery not responding */
-#define F_BATTERY_NOT_CONNECTED   BIT(12) /* Battery not connected */
-#define F_BATTERY_GET_PARAMS  BIT(13) /* Any battery parameter bad */
+#define F_BATTERY_UNRESPONSIVE BIT(11) /* Battery not responding */
+#define F_BATTERY_NOT_CONNECTED BIT(12) /* Battery not connected */
+#define F_BATTERY_GET_PARAMS BIT(13) /* Any battery parameter bad */
 
-#define F_BATTERY_MASK (F_BATTERY_VOLTAGE | \
-			F_BATTERY_MODE | \
-			F_BATTERY_CAPACITY | F_BATTERY_STATE_OF_CHARGE | \
-			F_BATTERY_UNRESPONSIVE | F_BATTERY_NOT_CONNECTED | \
-			F_BATTERY_GET_PARAMS)
-#define F_CHARGER_MASK (F_CHARGER_VOLTAGE | F_CHARGER_CURRENT | \
-			F_CHARGER_INIT)
+#define F_BATTERY_MASK                                             \
+	(F_BATTERY_VOLTAGE | F_BATTERY_MODE | F_BATTERY_CAPACITY | \
+	 F_BATTERY_STATE_OF_CHARGE | F_BATTERY_UNRESPONSIVE |      \
+	 F_BATTERY_NOT_CONNECTED | F_BATTERY_GET_PARAMS)
+#define F_CHARGER_MASK (F_CHARGER_VOLTAGE | F_CHARGER_CURRENT | F_CHARGER_INIT)
 
 /* Power state data
  * Status collection of charging state machine.
diff --git a/include/charge_state_v2.h b/include/charge_state_v2.h
index 547dc6c63d..0817204774 100644
--- a/include/charge_state_v2.h
+++ b/include/charge_state_v2.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -117,8 +117,8 @@ void board_base_reset(void);
  * @param curr Pointer to struct charge_state_data
  * @return Action to take.
  */
-enum critical_shutdown board_critical_shutdown_check(
-		struct charge_state_data *curr);
+enum critical_shutdown
+board_critical_shutdown_check(struct charge_state_data *curr);
 
 /**
  * Callback to set battery level for shutdown
@@ -223,4 +223,11 @@ __test_only void reset_prev_disp_charge(void);
  */
 __test_only bool charging_progress_displayed(void);
 
+/**
+ * Callback for boards to request charger to enable bypass mode on/off.
+ *
+ * @return True for requesting bypass on. False for requesting bypass off.
+ */
+int board_should_charger_bypass(void);
+
 #endif /* __CROS_EC_CHARGE_STATE_V2_H */
diff --git a/include/charger.h b/include/charger.h
index 66130ce3a5..046ed3acc2 100644
--- a/include/charger.h
+++ b/include/charger.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -50,7 +50,7 @@ struct charger_drv {
 	enum ec_error_list (*post_init)(int chgnum);
 
 	/* Get charger information */
-	const struct charger_info * (*get_info)(int chgnum);
+	const struct charger_info *(*get_info)(int chgnum);
 
 	/* Get smart battery charger status. Supported flags may vary. */
 	enum ec_error_list (*get_status)(int chgnum, int *status);
@@ -85,12 +85,10 @@ struct charger_drv {
 	enum ec_error_list (*get_voltage)(int chgnum, int *voltage);
 	enum ec_error_list (*set_voltage)(int chgnum, int voltage);
 
-
 	/* Get the measured charge current and voltage in mA/mV */
 	enum ec_error_list (*get_actual_current)(int chgnum, int *current);
 	enum ec_error_list (*get_actual_voltage)(int chgnum, int *voltage);
 
-
 	/* Discharge battery when on AC power. */
 	enum ec_error_list (*discharge_on_ac)(int chgnum, int enable);
 
@@ -98,6 +96,10 @@ struct charger_drv {
 	enum ec_error_list (*get_vbus_voltage)(int chgnum, int port,
 					       int *voltage);
 
+	/* Get the Vsys voltage (mV) from the charger */
+	enum ec_error_list (*get_vsys_voltage)(int chgnum, int port,
+					       int *voltage);
+
 	/* Set desired input current value */
 	enum ec_error_list (*set_input_current_limit)(int chgnum,
 						      int input_current);
@@ -180,13 +182,13 @@ enum chg_id {
 void charger_get_params(struct charger_params *chg);
 
 /* Bits to indicate which fields of struct charger_params could not be read */
-#define CHG_FLAG_BAD_CURRENT		0x00000001
-#define CHG_FLAG_BAD_VOLTAGE		0x00000002
-#define CHG_FLAG_BAD_INPUT_CURRENT	0x00000004
-#define CHG_FLAG_BAD_STATUS		0x00000008
-#define CHG_FLAG_BAD_OPTION		0x00000010
+#define CHG_FLAG_BAD_CURRENT 0x00000001
+#define CHG_FLAG_BAD_VOLTAGE 0x00000002
+#define CHG_FLAG_BAD_INPUT_CURRENT 0x00000004
+#define CHG_FLAG_BAD_STATUS 0x00000008
+#define CHG_FLAG_BAD_OPTION 0x00000010
 /* All of the above CHG_FLAG_BAD_* bits */
-#define CHG_FLAG_BAD_ANY                0x0000001f
+#define CHG_FLAG_BAD_ANY 0x0000001f
 
 /**
  * Return the closest match the charger can supply to the requested current.
@@ -277,6 +279,9 @@ enum ec_error_list charger_discharge_on_ac(int enable);
 /* Get the VBUS voltage (mV) from the charger */
 enum ec_error_list charger_get_vbus_voltage(int port, int *voltage);
 
+/* Get the Vsys voltage (mV) from the charger */
+enum ec_error_list charger_get_vsys_voltage(int port, int *voltage);
+
 /* Custom board function to discharge battery when on AC power */
 int board_discharge_on_ac(int enable);
 
@@ -384,10 +389,15 @@ enum ec_error_list charger_enable_linear_charge(int chgnum, bool enable);
  */
 enum ec_error_list charger_enable_bypass_mode(int chgnum, int enable);
 
-/*
+/**
  * Print all charger info for debugging purposes
  * @param chgnum: charger IC index.
  */
 void print_charger_debug(int chgnum);
 
+/**
+ * Get the value of CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON
+ */
+int charger_get_min_bat_pct_for_power_on(void);
+
 #endif /* __CROS_EC_CHARGER_H */
diff --git a/include/charger_detect.h b/include/charger_detect.h
index ae2001e418..7371583cd8 100644
--- a/include/charger_detect.h
+++ b/include/charger_detect.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/charger_profile_override.h b/include/charger_profile_override.h
index 091eb11946..24606d3c3d 100644
--- a/include/charger_profile_override.h
+++ b/include/charger_profile_override.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,7 +10,7 @@
 
 #include "charge_state_v2.h"
 
-#define TEMPC_TENTHS_OF_DEG(c) ((c) * 10)
+#define TEMPC_TENTHS_OF_DEG(c) ((c)*10)
 
 #define CHARGER_PROF_TEMP_C_LAST_RANGE 0xFFFF
 
@@ -69,10 +69,11 @@ int charger_profile_override(struct charge_state_data *curr);
  *  <0     An error occurred. The poll time will be shorter than usual.
  *         Too many errors in a row may trigger some corrective action.
  */
-int charger_profile_override_common(struct charge_state_data *curr,
-			const struct fast_charge_params *fast_chg_params,
-			const struct fast_charge_profile **prev_chg_prof_info,
-			int batt_vtg_max);
+int charger_profile_override_common(
+	struct charge_state_data *curr,
+	const struct fast_charge_params *fast_chg_params,
+	const struct fast_charge_profile **prev_chg_prof_info,
+	int batt_vtg_max);
 
 /*
  * Access to custom profile params through host commands.
diff --git a/include/chipset.h b/include/chipset.h
index 840db3aa60..1a5c5a0d2f 100644
--- a/include/chipset.h
+++ b/include/chipset.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -29,17 +29,18 @@
  * I'll compare it myself with the state(s) I want."
  */
 enum chipset_state_mask {
-	CHIPSET_STATE_HARD_OFF = 0x01,   /* Hard off (G3) */
-	CHIPSET_STATE_SOFT_OFF = 0x02,   /* Soft off (S5, S4) */
-	CHIPSET_STATE_SUSPEND  = 0x04,   /* Suspend (S3) */
-	CHIPSET_STATE_ON       = 0x08,   /* On (S0) */
-	CHIPSET_STATE_STANDBY  = 0x10,   /* Standby (S0ix) */
+	CHIPSET_STATE_HARD_OFF = 0x01, /* Hard off (G3) */
+	CHIPSET_STATE_SOFT_OFF = 0x02, /* Soft off (S5, S4) */
+	CHIPSET_STATE_SUSPEND = 0x04, /* Suspend (S3) */
+	CHIPSET_STATE_ON = 0x08, /* On (S0) */
+	CHIPSET_STATE_STANDBY = 0x10, /* Standby (S0ix) */
 	/* Common combinations */
-	CHIPSET_STATE_ANY_OFF = (CHIPSET_STATE_HARD_OFF |
-				 CHIPSET_STATE_SOFT_OFF),  /* Any off state */
+	CHIPSET_STATE_ANY_OFF =
+		(CHIPSET_STATE_HARD_OFF | CHIPSET_STATE_SOFT_OFF), /* Any off
+								      state */
 	/* This combination covers any kind of suspend i.e. S3 or S0ix. */
-	CHIPSET_STATE_ANY_SUSPEND = (CHIPSET_STATE_SUSPEND |
-				     CHIPSET_STATE_STANDBY),
+	CHIPSET_STATE_ANY_SUSPEND =
+		(CHIPSET_STATE_SUSPEND | CHIPSET_STATE_STANDBY),
 };
 
 enum critical_shutdown {
@@ -138,23 +139,47 @@ static inline int chipset_in_or_transitioning_to_state(int state_mask)
 	return state_mask & CHIPSET_STATE_ANY_OFF;
 }
 
-static inline void chipset_exit_hard_off(void) { }
-static inline void chipset_throttle_cpu(int throttle) { }
+static inline void chipset_exit_hard_off(void)
+{
+}
+static inline void chipset_throttle_cpu(int throttle)
+{
+}
 static inline void chipset_force_shutdown(enum chipset_shutdown_reason reason)
 {
 }
 
-static inline void chipset_reset(enum chipset_shutdown_reason reason) { }
-static inline void power_interrupt(enum gpio_signal signal) { }
-static inline void chipset_handle_espi_reset_assert(void) { }
-static inline void chipset_handle_reboot(void) { }
-static inline void chipset_reset_request_interrupt(enum gpio_signal signal) { }
-static inline void chipset_warm_reset_interrupt(enum gpio_signal signal) { }
-static inline void chipset_ap_rst_interrupt(enum gpio_signal signal) { }
-static inline void chipset_power_good_interrupt(enum gpio_signal signal) { }
-static inline void chipset_watchdog_interrupt(enum gpio_signal signal) { }
+static inline void chipset_reset(enum chipset_shutdown_reason reason)
+{
+}
+static inline void power_interrupt(enum gpio_signal signal)
+{
+}
+static inline void chipset_handle_espi_reset_assert(void)
+{
+}
+static inline void chipset_handle_reboot(void)
+{
+}
+static inline void chipset_reset_request_interrupt(enum gpio_signal signal)
+{
+}
+static inline void chipset_warm_reset_interrupt(enum gpio_signal signal)
+{
+}
+static inline void chipset_ap_rst_interrupt(enum gpio_signal signal)
+{
+}
+static inline void chipset_power_good_interrupt(enum gpio_signal signal)
+{
+}
+static inline void chipset_watchdog_interrupt(enum gpio_signal signal)
+{
+}
 
-static inline void init_reset_log(void) { }
+static inline void init_reset_log(void)
+{
+}
 
 #endif /* !CONFIG_AP_POWER_CONTROL */
 
@@ -215,8 +240,9 @@ void chipset_watchdog_interrupt(enum gpio_signal signal);
  * @param now                Current time
  * @return Action to take
  */
-__override_proto enum critical_shutdown board_system_is_idle(
-		uint64_t last_shutdown_time, uint64_t *target, uint64_t now);
+__override_proto enum critical_shutdown
+board_system_is_idle(uint64_t last_shutdown_time, uint64_t *target,
+		     uint64_t now);
 
 #ifdef CONFIG_CMD_AP_RESET_LOG
 
@@ -237,9 +263,19 @@ get_ap_reset_stats(struct ap_reset_log_entry *reset_log_entries,
 		   size_t num_reset_log_entries,
 		   uint32_t *resets_since_ec_boot);
 
+/**
+ * Check the reason given in the last call to report_ap_reset() .
+ *
+ * @return Reason argument that was passed to the last call to
+ * report_ap_reset(). Zero if report_ap_reset() has not been called.
+ */
+enum chipset_shutdown_reason chipset_get_shutdown_reason(void);
+
 #else
 
-static inline void report_ap_reset(enum chipset_shutdown_reason reason) { }
+static inline void report_ap_reset(enum chipset_shutdown_reason reason)
+{
+}
 
 test_mockable_static_inline enum ec_error_list
 get_ap_reset_stats(struct ap_reset_log_entry *reset_log_entries,
@@ -248,6 +284,11 @@ get_ap_reset_stats(struct ap_reset_log_entry *reset_log_entries,
 	return EC_SUCCESS;
 }
 
+static inline enum chipset_shutdown_reason chipset_get_shutdown_reason(void)
+{
+	return CHIPSET_RESET_UNKNOWN;
+}
+
 #endif /* !CONFIG_CMD_AP_RESET_LOG */
 
-#endif  /* __CROS_EC_CHIPSET_H */
+#endif /* __CROS_EC_CHIPSET_H */
diff --git a/include/clock.h b/include/clock.h
index c64cfe4db5..600649f891 100644
--- a/include/clock.h
+++ b/include/clock.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -78,10 +78,10 @@ enum bus_type {
 void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles);
 
 /* Clock gate control modes for clock_enable_peripheral() */
-#define CGC_MODE_RUN    BIT(0)
-#define CGC_MODE_SLEEP  BIT(1)
+#define CGC_MODE_RUN BIT(0)
+#define CGC_MODE_SLEEP BIT(1)
 #define CGC_MODE_DSLEEP BIT(2)
-#define CGC_MODE_ALL    (CGC_MODE_RUN | CGC_MODE_SLEEP | CGC_MODE_DSLEEP)
+#define CGC_MODE_ALL (CGC_MODE_RUN | CGC_MODE_SLEEP | CGC_MODE_DSLEEP)
 
 /**
  * Enable clock to peripheral by setting the CGC register pertaining
@@ -108,4 +108,4 @@ void clock_disable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode);
  */
 void clock_refresh_console_in_use(void);
 
-#endif  /* __CROS_EC_CLOCK_H */
+#endif /* __CROS_EC_CLOCK_H */
diff --git a/include/common.h b/include/common.h
index 02989c692b..7334fe3aed 100644
--- a/include/common.h
+++ b/include/common.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -46,7 +46,7 @@
  *     #define BAZ CONCAT2(BAR, FOO)
  * Will evaluate to BAR1, which then evaluates to 42.
  */
-#define CONCAT_STAGE_1(w, x, y, z) w ## x ## y ## z
+#define CONCAT_STAGE_1(w, x, y, z) w##x##y##z
 #define CONCAT2(w, x) CONCAT_STAGE_1(w, x, , )
 #define CONCAT3(w, x, y) CONCAT_STAGE_1(w, x, y, )
 #define CONCAT4(w, x, y, z) CONCAT_STAGE_1(w, x, y, z)
@@ -58,20 +58,20 @@
  * is safe with regards to using nested macros and defined arguments.
  */
 #ifndef CONFIG_ZEPHYR
-#define STRINGIFY0(name)  #name
-#define STRINGIFY(name)  STRINGIFY0(name)
-#endif   /* CONFIG_ZEPHYR */
+#define STRINGIFY0(name) #name
+#define STRINGIFY(name) STRINGIFY0(name)
+#endif /* CONFIG_ZEPHYR */
 
 /* Macros to access registers */
 #define REG64_ADDR(addr) ((volatile uint64_t *)(addr))
 #define REG32_ADDR(addr) ((volatile uint32_t *)(addr))
 #define REG16_ADDR(addr) ((volatile uint16_t *)(addr))
-#define REG8_ADDR(addr)  ((volatile uint8_t  *)(addr))
+#define REG8_ADDR(addr) ((volatile uint8_t *)(addr))
 
 #define REG64(addr) (*REG64_ADDR(addr))
 #define REG32(addr) (*REG32_ADDR(addr))
 #define REG16(addr) (*REG16_ADDR(addr))
-#define REG8(addr)  (*REG8_ADDR(addr))
+#define REG8(addr) (*REG8_ADDR(addr))
 
 /*
  * Define __aligned(n) and __packed if someone hasn't beat us to it.  Linux
@@ -184,7 +184,13 @@
  */
 #define __override_proto
 #define __override
-#define __overridable	__attribute__((weak))
+#define __overridable __attribute__((weak))
+
+/*
+ * Attribute that will generate a compiler warning if the return value is not
+ * used.
+ */
+#define __warn_unused_result __attribute__((warn_unused_result))
 
 /*
  * Macros for combining bytes into larger integers. _LE and _BE signify little
@@ -198,30 +204,29 @@
 
 #define UINT32_FROM_BYTES(lsb, byte1, byte2, msb) \
 	((lsb) | (byte1) << 8 | (byte2) << 16 | (msb) << 24)
-#define UINT32_FROM_BYTE_ARRAY_LE(data, lsb_index) \
+#define UINT32_FROM_BYTE_ARRAY_LE(data, lsb_index)                      \
 	UINT32_FROM_BYTES((data)[(lsb_index)], (data)[(lsb_index) + 1], \
 			  (data)[(lsb_index) + 2], (data)[(lsb_index) + 3])
-#define UINT32_FROM_BYTE_ARRAY_BE(data, msb_index) \
+#define UINT32_FROM_BYTE_ARRAY_BE(data, msb_index)                          \
 	UINT32_FROM_BYTES((data)[(msb_index) + 3], (data)[(msb_index) + 2], \
 			  (data)[(msb_index) + 1], (data)[(msb_index)])
 
 /* There isn't really a better place for this */
 #define C_TO_K(temp_c) ((temp_c) + 273)
-#define K_TO_C(temp_c) ((temp_c) - 273)
+#define K_TO_C(temp_c) ((temp_c)-273)
 /*
  * round_divide is part of math_utils, so you may need to import math_utils.h
  * and link math_utils.o if you use the following macros.
  */
 #define CELSIUS_TO_DECI_KELVIN(temp_c) \
 	(round_divide(CELSIUS_TO_MILLI_KELVIN(temp_c), 100))
-#define DECI_KELVIN_TO_CELSIUS(temp_dk) \
-	(MILLI_KELVIN_TO_CELSIUS((temp_dk) * 100))
-#define MILLI_KELVIN_TO_MILLI_CELSIUS(temp_mk) ((temp_mk) - 273150)
+#define DECI_KELVIN_TO_CELSIUS(temp_dk) (MILLI_KELVIN_TO_CELSIUS((temp_dk)*100))
+#define MILLI_KELVIN_TO_MILLI_CELSIUS(temp_mk) ((temp_mk)-273150)
 #define MILLI_CELSIUS_TO_MILLI_KELVIN(temp_mc) ((temp_mc) + 273150)
 #define MILLI_KELVIN_TO_KELVIN(temp_mk) (round_divide((temp_mk), 1000))
-#define KELVIN_TO_MILLI_KELVIN(temp_k) ((temp_k) * 1000)
+#define KELVIN_TO_MILLI_KELVIN(temp_k) ((temp_k)*1000)
 #define CELSIUS_TO_MILLI_KELVIN(temp_c) \
-	(MILLI_CELSIUS_TO_MILLI_KELVIN((temp_c) * 1000))
+	(MILLI_CELSIUS_TO_MILLI_KELVIN((temp_c)*1000))
 #define MILLI_KELVIN_TO_CELSIUS(temp_mk) \
 	(round_divide(MILLI_KELVIN_TO_MILLI_CELSIUS(temp_mk), 1000))
 
@@ -229,14 +234,15 @@
  * TARGET_WITH_MARGIN(X, 5) returns X' where X' * 100.5% is almost equal to
  * but does not exceed X. */
 #define TARGET_WITH_MARGIN(target, tenths_percent) \
-	(((target) * 1000) / (1000 + (tenths_percent)))
+	(((target)*1000) / (1000 + (tenths_percent)))
 
 /* Call a function, and return the error value unless it returns EC_SUCCESS. */
-#define RETURN_ERROR(fn) do { \
-	int error = (fn); \
-	if (error != EC_SUCCESS) \
-		return error; \
-} while (0)
+#define RETURN_ERROR(fn)                 \
+	do {                             \
+		int error = (fn);        \
+		if (error != EC_SUCCESS) \
+			return error;    \
+	} while (0)
 
 /*
  * Define test_mockable and test_mockable_static for mocking
@@ -246,11 +252,15 @@
 #define test_mockable __attribute__((weak))
 #define test_mockable_static __attribute__((weak))
 #define test_mockable_static_inline __attribute__((weak))
+#define test_mockable_noreturn __attribute__((weak))
+#define test_mockable_static_noreturn __attribute__((weak))
 #define test_export_static
 #else
 #define test_mockable
 #define test_mockable_static static
 #define test_mockable_static_inline static inline
+#define test_mockable_noreturn noreturn
+#define test_mockable_static_noreturn static noreturn
 #define test_export_static static
 #endif
 
@@ -366,8 +376,7 @@ enum ec_error_list {
 
 /*
  * Mark functions that collide with stdlib so they can be hidden when linking
- * against libraries that require stdlib. HIDE_EC_STDLIB should be defined
- * before including common.h from code that links to cstdlib.
+ * against libraries that require stdlib.
  */
 #ifdef TEST_FUZZ
 #define __stdlib_compat __attribute__((visibility("hidden")))
@@ -391,12 +400,12 @@ enum ec_error_list {
  * undefined, rather than defined to something else. This usually
  * involves tricks with __builtin_strcmp.
  */
-#define __cfg_select(cfg, empty, otherwise)     \
+#define __cfg_select(cfg, empty, otherwise) \
 	__cfg_select_1(cfg, empty, otherwise)
 #define __cfg_select_placeholder_ _,
-#define __cfg_select_1(value, empty, otherwise)			  \
+#define __cfg_select_1(value, empty, otherwise) \
 	__cfg_select_2(__cfg_select_placeholder_##value, empty, otherwise)
-#define __cfg_select_2(arg1_or_junk, empty, otherwise)		\
+#define __cfg_select_2(arg1_or_junk, empty, otherwise) \
 	__cfg_select_3(arg1_or_junk _, empty, otherwise)
 #define __cfg_select_3(_ignore1, _ignore2, select, ...) select
 
@@ -405,13 +414,10 @@ enum ec_error_list {
  * handling the __builtin_strcmp trickery where a BUILD_ASSERT is
  * appropriate in the context.
  */
-#define __cfg_select_build_assert(cfg, value, empty, undef)	\
-	__cfg_select(						\
-		value,						\
-		empty,						\
-		BUILD_ASSERT(					\
-			__builtin_strcmp(cfg, #value) == 0);	\
-		undef)
+#define __cfg_select_build_assert(cfg, value, empty, undef)            \
+	__cfg_select(value, empty,                                     \
+		     BUILD_ASSERT(__builtin_strcmp(cfg, #value) == 0); \
+		     undef)
 
 /*
  * Attribute for generating an error if a function is used.
@@ -436,16 +442,16 @@ enum ec_error_list {
  * technique requires that the optimizer be enabled so it can remove
  * the undefined function call.
  */
-#define __config_enabled(cfg, value)					      \
-	__cfg_select(							      \
-		value, 1, ({						      \
-			int __undefined = __builtin_strcmp(cfg, #value) == 0; \
-			extern int IS_ENABLED_BAD_ARGS(void) __error(	      \
-				cfg " must be <blank>, or not defined.");     \
-			if (!__undefined)				      \
-				IS_ENABLED_BAD_ARGS();			      \
-			0;						      \
-		}))
+#define __config_enabled(cfg, value)                                           \
+	__cfg_select(value, 1, ({                                              \
+			     int __undefined =                                 \
+				     __builtin_strcmp(cfg, #value) == 0;       \
+			     extern int IS_ENABLED_BAD_ARGS(void) __error(     \
+				     cfg " must be <blank>, or not defined."); \
+			     if (!__undefined)                                 \
+				     IS_ENABLED_BAD_ARGS();                    \
+			     0;                                                \
+		     }))
 
 /**
  * Checks if a config option is enabled or disabled
@@ -478,7 +484,7 @@ enum ec_error_list {
  * if the config option is enabled by Zephyr's definition.
  */
 #define IS_ENABLED(option) __cfg_select(option, 1, Z_IS_ENABLED1(option))
-#endif  /* CONFIG_ZEPHYR */
+#endif /* CONFIG_ZEPHYR */
 
 /**
  * Makes a global variable static when a config option is enabled,
@@ -490,7 +496,7 @@ enum ec_error_list {
  * should be defined to nothing or undefined.
  */
 #ifndef CONFIG_ZEPHYR
-#define STATIC_IF(option)						\
+#define STATIC_IF(option) \
 	__cfg_select_build_assert(#option, option, static, extern)
 #else
 /*
@@ -511,7 +517,7 @@ enum ec_error_list {
  * config option.
  */
 #ifndef CONFIG_ZEPHYR
-#define STATIC_IF_NOT(option)						\
+#define STATIC_IF_NOT(option) \
 	__cfg_select_build_assert(#option, option, extern, static)
 #else
 /*
@@ -522,4 +528,4 @@ enum ec_error_list {
 	__cfg_select(option, extern, COND_CODE_1(option, (extern), (static)))
 #endif /* CONFIG_ZEPHYR */
 
-#endif  /* __CROS_EC_COMMON_H */
+#endif /* __CROS_EC_COMMON_H */
diff --git a/include/compile_time_macros.h b/include/compile_time_macros.h
index 0151f1a391..8330ea5840 100644
--- a/include/compile_time_macros.h
+++ b/include/compile_time_macros.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -69,7 +69,7 @@
 
 /* Just in case - http://gcc.gnu.org/onlinedocs/gcc/Offsetof.html */
 #ifndef offsetof
-#define offsetof(type, member)  __builtin_offsetof(type, member)
+#define offsetof(type, member) __builtin_offsetof(type, member)
 #endif
 
 #define member_size(type, member) sizeof(((type *)0)->member)
@@ -78,7 +78,7 @@
  * Bit operation macros.
  */
 #ifndef CONFIG_ZEPHYR
-#define BIT(nr)			(1U << (nr))
+#define BIT(nr) (1U << (nr))
 /*
  * Set or clear <bit> of <var> depending on <set>.
  * It also supports setting and clearing (e.g. SET_BIT, CLR_BIT) macros.
@@ -86,7 +86,7 @@
 #define WRITE_BIT(var, bit, set) \
 	((var) = (set) ? ((var) | BIT(bit)) : ((var) & ~BIT(bit)))
 #endif
-#define BIT_ULL(nr)		(1ULL << (nr))
+#define BIT_ULL(nr) (1ULL << (nr))
 
 /*
  * Create a bit mask from least significant bit |l|
@@ -102,8 +102,8 @@
  * warnings for BIT(31+1).
  */
 #ifndef CONFIG_ZEPHYR
-#define GENMASK(h, l)     (((BIT(h)<<1)     - 1) ^ (BIT(l)     - 1))
-#define GENMASK_ULL(h, l) (((BIT_ULL(h)<<1) - 1) ^ (BIT_ULL(l) - 1))
+#define GENMASK(h, l) (((BIT(h) << 1) - 1) ^ (BIT(l) - 1))
+#define GENMASK_ULL(h, l) (((BIT_ULL(h) << 1) - 1) ^ (BIT_ULL(l) - 1))
 #endif
 
 #endif /* __CROS_EC_COMPILE_TIME_MACROS_H */
diff --git a/include/compiler.h b/include/compiler.h
index b3d99e26af..d684308c95 100644
--- a/include/compiler.h
+++ b/include/compiler.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,7 +21,7 @@
  * macro.
  */
 #ifndef typeof
-#define typeof(x)	__typeof__(x)
+#define typeof(x) __typeof__(x)
 #endif
 
 /**
diff --git a/include/config.h b/include/config.h
index 523d94a8a8..8ca7973093 100644
--- a/include/config.h
+++ b/include/config.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -623,7 +623,7 @@
  * are supplied and charging will be disabled after
  * CONFIG_BATTERY_LOW_VOLTAGE_TIMEOUT seconds.
  */
-#define CONFIG_BATTERY_LOW_VOLTAGE_TIMEOUT  (30*60*SECOND)
+#define CONFIG_BATTERY_LOW_VOLTAGE_TIMEOUT (30 * 60 * SECOND)
 
 /*
  * Specify the battery percentage at which the host is told it is full.
@@ -695,7 +695,7 @@
  * - If system fails to shutdown for some reason and battery further discharges
  *   to 2%, EC will trigger shutdown.
  */
-#define CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE	4  /* shutdown if soc <= 4% */
+#define CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE 4 /* shutdown if soc <= 4% */
 
 /*
  * Powerd's full_factor. The value comes from:
@@ -703,7 +703,7 @@
  *
  * This value is used by the host to calculate the ETA for full charge.
  */
-#define CONFIG_BATT_HOST_FULL_FACTOR		97
+#define CONFIG_BATT_HOST_FULL_FACTOR 97
 
 /*
  * Smart battery pass-through host commands.
@@ -943,7 +943,6 @@
 #undef CONFIG_CHARGER_SM5803
 #undef CONFIG_CHARGER_SY21612
 
-
 /* Allow run-time completion of the charger driver structure */
 #undef CONFIG_CHARGER_RUNTIME_CONFIG
 
@@ -1120,7 +1119,6 @@
  */
 #undef CONFIG_CHARGER_BQ25710_CMP_POL_EXTERNAL
 
-
 /* Enable if CONFIG_CHARGER_BQ25710_PKPWR_TOVLD_DEG should be applied */
 #undef CONFIG_CHARGER_BQ25710_PKPWR_TOVLD_DEG_CUSTOM
 
@@ -1234,8 +1232,8 @@
  * analog signaling.  If the AP requires greater than 15W to boot, then see
  * CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW.
  */
-#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 2  /* Don't boot if soc < 2% */
-#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC	1
+#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 2 /* Don't boot if soc < 2% */
+#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC 1
 /* Default: 15000 */
 #undef CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
 /* Default: Disabled */
@@ -1335,7 +1333,6 @@
 #undef CONFIG_TRICKLE_CHARGING
 
 /* Wireless chargers */
-#undef CONFIG_WIRELESS_CHARGER_P9221_R7
 #undef CONFIG_CPS8100
 
 /*****************************************************************************/
@@ -1395,39 +1392,38 @@
 /* Chipset config */
 
 /* AP chipset support; pick at most one */
-#undef CONFIG_CHIPSET_ALDERLAKE		/* Intel Alderlake (x86) */
-#undef CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540	/* Intel Alderlake (x86)
-						 * with power sequencer
-						 * chip
-						 */
-#undef CONFIG_CHIPSET_APOLLOLAKE	/* Intel Apollolake (x86) */
-#undef CONFIG_CHIPSET_BRASWELL		/* Intel Braswell (x86) */
-#undef CONFIG_CHIPSET_CANNONLAKE	/* Intel Cannonlake (x86) */
-#undef CONFIG_CHIPSET_COMETLAKE		/* Intel Cometlake (x86) */
-#undef CONFIG_CHIPSET_COMETLAKE_DISCRETE	/* Intel Cometlake (x86),
-						 * discrete EC control
-						 */
-#undef CONFIG_CHIPSET_ECDRIVEN		/* Mock power module */
-#undef CONFIG_CHIPSET_FALCONLITE	/* Falcon-lite*/
-#undef CONFIG_CHIPSET_GEMINILAKE	/* Intel Geminilake (x86) */
-#undef CONFIG_CHIPSET_ICELAKE		/* Intel Icelake (x86) */
-#undef CONFIG_CHIPSET_JASPERLAKE	/* Intel Jasperlake (x86) */
-#undef CONFIG_CHIPSET_METEORLAKE	/* Intel Meteorlake (x86) */
-#undef CONFIG_CHIPSET_MT817X		/* MediaTek MT817x */
-#undef CONFIG_CHIPSET_MT8183		/* MediaTek MT8183 */
-#undef CONFIG_CHIPSET_MT8192		/* MediaTek MT8192 */
-#undef CONFIG_CHIPSET_CEZANNE		/* AMD Cezanne (x86) */
-#undef CONFIG_CHIPSET_RK3288		/* Rockchip rk3288 */
-#undef CONFIG_CHIPSET_RK3399		/* Rockchip rk3399 */
-#undef CONFIG_CHIPSET_SKYLAKE		/* Intel Skylake (x86) */
-#undef CONFIG_CHIPSET_SC7180            /* Qualcomm SC7180 */
-#undef CONFIG_CHIPSET_SC7280            /* Qualcomm SC7280 */
-#undef CONFIG_CHIPSET_SDM845            /* Qualcomm SDM845 */
-#undef CONFIG_CHIPSET_STONEY		/* AMD Stoney (x86)*/
-#undef CONFIG_CHIPSET_TIGERLAKE		/* Intel Tigerlake (x86) */
+#undef CONFIG_CHIPSET_ALDERLAKE /* Intel Alderlake (x86) */
+#undef CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540 /* Intel Alderlake (x86) \
+					     * with power sequencer  \
+					     * chip                  \
+					     */
+#undef CONFIG_CHIPSET_APOLLOLAKE /* Intel Apollolake (x86) */
+#undef CONFIG_CHIPSET_CANNONLAKE /* Intel Cannonlake (x86) */
+#undef CONFIG_CHIPSET_COMETLAKE /* Intel Cometlake (x86) */
+#undef CONFIG_CHIPSET_COMETLAKE_DISCRETE /* Intel Cometlake (x86), \
+					  * discrete EC control    \
+					  */
+#undef CONFIG_CHIPSET_ECDRIVEN /* Mock power module */
+#undef CONFIG_CHIPSET_FALCONLITE /* Falcon-lite*/
+#undef CONFIG_CHIPSET_GEMINILAKE /* Intel Geminilake (x86) */
+#undef CONFIG_CHIPSET_ICELAKE /* Intel Icelake (x86) */
+#undef CONFIG_CHIPSET_JASPERLAKE /* Intel Jasperlake (x86) */
+#undef CONFIG_CHIPSET_METEORLAKE /* Intel Meteorlake (x86) */
+#undef CONFIG_CHIPSET_MT817X /* MediaTek MT817x */
+#undef CONFIG_CHIPSET_MT8183 /* MediaTek MT8183 */
+#undef CONFIG_CHIPSET_MT8192 /* MediaTek MT8192 */
+#undef CONFIG_CHIPSET_CEZANNE /* AMD Cezanne (x86) */
+#undef CONFIG_CHIPSET_RK3288 /* Rockchip rk3288 */
+#undef CONFIG_CHIPSET_RK3399 /* Rockchip rk3399 */
+#undef CONFIG_CHIPSET_SKYLAKE /* Intel Skylake (x86) */
+#undef CONFIG_CHIPSET_SC7180 /* Qualcomm SC7180 */
+#undef CONFIG_CHIPSET_SC7280 /* Qualcomm SC7280 */
+#undef CONFIG_CHIPSET_SDM845 /* Qualcomm SDM845 */
+#undef CONFIG_CHIPSET_STONEY /* AMD Stoney (x86)*/
+#undef CONFIG_CHIPSET_TIGERLAKE /* Intel Tigerlake (x86) */
 
 /* Shared chipset support; automatically gets defined below. */
-#undef CONFIG_CHIPSET_APL_GLK		/* Apollolake & Geminilake */
+#undef CONFIG_CHIPSET_APL_GLK /* Apollolake & Geminilake */
 
 /* Support chipset throttling */
 #undef CONFIG_CHIPSET_CAN_THROTTLE
@@ -1539,8 +1535,8 @@
  * Required Configuration:
  * - CONFIG_BLINK_LEDS        --> List of LEDs (gpio enum names) to use as bits
  */
-#undef  CONFIG_BLINK
-#undef  CONFIG_BLINK_LEDS                     /* Ex: GPIO_LED1, GPIO_LED2 */
+#undef CONFIG_BLINK
+#undef CONFIG_BLINK_LEDS /* Ex: GPIO_LED1, GPIO_LED2 */
 
 /*****************************************************************************/
 /*
@@ -1550,20 +1546,20 @@
  * console.
  */
 
-#undef  CONFIG_CMD_ACCELS
-#undef  CONFIG_CMD_ACCEL_FIFO
-#undef  CONFIG_CMD_ACCEL_INFO
+#undef CONFIG_CMD_ACCELS
+#undef CONFIG_CMD_ACCEL_FIFO
+#undef CONFIG_CMD_ACCEL_INFO
 #define CONFIG_CMD_ACCELSPOOF
 #define CONFIG_CMD_ADC
-#undef  CONFIG_CMD_ALS
+#undef CONFIG_CMD_ALS
 #define CONFIG_CMD_APTHROTTLE
-#undef  CONFIG_CMD_BATDEBUG
+#undef CONFIG_CMD_BATDEBUG
 #define CONFIG_CMD_BATTFAKE
-#undef  CONFIG_CMD_BATT_MFG_ACCESS
-#undef  CONFIG_CMD_BUTTON
+#undef CONFIG_CMD_BATT_MFG_ACCESS
+#undef CONFIG_CMD_BUTTON
 #define CONFIG_CMD_CBI
-#undef  CONFIG_CMD_PD_SRCCAPS_REDUCED_SIZE
-#undef  CONFIG_CMD_VBUS
+#undef CONFIG_CMD_PD_SRCCAPS_REDUCED_SIZE
+#undef CONFIG_CMD_VBUS
 
 /*
  * HAS_TASK_CHIPSET implies the GSC presence.
@@ -1576,97 +1572,97 @@
 #undef CONFIG_CMD_CHARGEN
 #endif
 #define CONFIG_CMD_CHARGER
-#undef  CONFIG_CMD_CHARGER_ADC_AMON_BMON
-#undef  CONFIG_CMD_CHARGER_DUMP
-#undef  CONFIG_CMD_CHARGER_PROFILE_OVERRIDE
-#undef  CONFIG_CMD_CHARGER_PROFILE_OVERRIDE_TEST
+#undef CONFIG_CMD_CHARGER_ADC_AMON_BMON
+#undef CONFIG_CMD_CHARGER_DUMP
+#undef CONFIG_CMD_CHARGER_PROFILE_OVERRIDE
+#undef CONFIG_CMD_CHARGER_PROFILE_OVERRIDE_TEST
 #define CONFIG_CMD_CHARGE_SUPPLIER_INFO
-#undef  CONFIG_CMD_CHGRAMP
-#undef  CONFIG_CMD_CLOCKGATES
-#undef  CONFIG_CMD_COMXTEST
+#undef CONFIG_CMD_CHGRAMP
+#undef CONFIG_CMD_CLOCKGATES
+#undef CONFIG_CMD_COMXTEST
 #define CONFIG_CMD_CRASH
 #define CONFIG_CMD_DEVICE_EVENT
-#undef  CONFIG_CMD_DLOG
-#undef  CONFIG_CMD_ECTEMP
+#undef CONFIG_CMD_DLOG
+#undef CONFIG_CMD_ECTEMP
 #define CONFIG_CMD_FASTCHARGE
-#undef  CONFIG_CMD_FLASH
+#undef CONFIG_CMD_FLASH
 #define CONFIG_CMD_FLASHINFO
-#undef  CONFIG_CMD_FLASH_TRISTATE
-#undef  CONFIG_CMD_FORCETIME
-#undef  CONFIG_CMD_FPSENSOR_DEBUG
+#undef CONFIG_CMD_FLASH_TRISTATE
+#undef CONFIG_CMD_FORCETIME
+#undef CONFIG_CMD_FPSENSOR_DEBUG
 #define CONFIG_CMD_GETTIME
-#undef  CONFIG_CMD_GL3590
-#undef  CONFIG_CMD_GPIO_EXTENDED
-#undef  CONFIG_CMD_GT7288
+#undef CONFIG_CMD_GL3590
+#undef CONFIG_CMD_GPIO_EXTENDED
+#undef CONFIG_CMD_GT7288
 #define CONFIG_CMD_HASH
 #define CONFIG_CMD_HCDEBUG
-#undef  CONFIG_CMD_HOSTCMD
-#undef  CONFIG_CMD_I2CWEDGE
-#undef  CONFIG_CMD_I2C_PROTECT
+#undef CONFIG_CMD_HOSTCMD
+#undef CONFIG_CMD_I2CWEDGE
+#undef CONFIG_CMD_I2C_PROTECT
 #define CONFIG_CMD_I2C_SCAN
-#undef  CONFIG_CMD_I2C_SPEED
-#undef  CONFIG_CMD_I2C_STRESS_TEST
-#undef  CONFIG_CMD_I2C_STRESS_TEST_ACCEL
-#undef  CONFIG_CMD_I2C_STRESS_TEST_ALS
-#undef  CONFIG_CMD_I2C_STRESS_TEST_BATTERY
-#undef  CONFIG_CMD_I2C_STRESS_TEST_CHARGER
-#undef  CONFIG_CMD_I2C_STRESS_TEST_TCPC
+#undef CONFIG_CMD_I2C_SPEED
+#undef CONFIG_CMD_I2C_STRESS_TEST
+#undef CONFIG_CMD_I2C_STRESS_TEST_ACCEL
+#undef CONFIG_CMD_I2C_STRESS_TEST_ALS
+#undef CONFIG_CMD_I2C_STRESS_TEST_BATTERY
+#undef CONFIG_CMD_I2C_STRESS_TEST_CHARGER
+#undef CONFIG_CMD_I2C_STRESS_TEST_TCPC
 #define CONFIG_CMD_I2C_XFER
-#undef  CONFIG_CMD_I2C_XFER_RAW
+#undef CONFIG_CMD_I2C_XFER_RAW
 #define CONFIG_CMD_IDLE_STATS
 #define CONFIG_CMD_INA
-#undef  CONFIG_CMD_JUMPTAGS
+#undef CONFIG_CMD_JUMPTAGS
 #define CONFIG_CMD_KEYBOARD
-#undef  CONFIG_CMD_LEDTEST
-#undef  CONFIG_CMD_MCDP
+#undef CONFIG_CMD_LEDTEST
+#undef CONFIG_CMD_MCDP
 #define CONFIG_CMD_MD
 #define CONFIG_CMD_MEM
 #define CONFIG_CMD_MFALLOW
 #define CONFIG_CMD_MMAPINFO
 #define CONFIG_CMD_PD
-#undef  CONFIG_CMD_PD_DEV_DUMP_INFO
-#undef  CONFIG_CMD_PD_FLASH
-#undef  CONFIG_CMD_PD_TIMER
+#undef CONFIG_CMD_PD_DEV_DUMP_INFO
+#undef CONFIG_CMD_PD_FLASH
+#undef CONFIG_CMD_PD_TIMER
 #define CONFIG_CMD_PECI
-#undef  CONFIG_CMD_PLL
+#undef CONFIG_CMD_PLL
 #define CONFIG_CMD_POWERINDEBUG
-#undef  CONFIG_CMD_POWERLED
+#undef CONFIG_CMD_POWERLED
 #define CONFIG_CMD_PWR_AVG
 #define CONFIG_CMD_POWER_AP
-#undef  CONFIG_CMD_PPC_DUMP
-#undef  CONFIG_CMD_PS2
-#undef  CONFIG_CMD_RAND
+#undef CONFIG_CMD_PPC_DUMP
+#undef CONFIG_CMD_PS2
+#undef CONFIG_CMD_RAND
 #define CONFIG_CMD_REGULATOR
-#undef  CONFIG_CMD_RESET_FLAGS
+#undef CONFIG_CMD_RESET_FLAGS
 #define CONFIG_CMD_RETIMER
-#undef  CONFIG_CMD_RTC
-#undef  CONFIG_CMD_RTC_ALARM
+#undef CONFIG_CMD_RTC
+#undef CONFIG_CMD_RTC_ALARM
 #define CONFIG_CMD_RW
-#undef	CONFIG_CMD_S5_TIMEOUT
-#undef  CONFIG_CMD_SCRATCHPAD
-#undef	CONFIG_CMD_SEVEN_SEG_DISPLAY
+#undef CONFIG_CMD_S5_TIMEOUT
+#undef CONFIG_CMD_SCRATCHPAD
+#undef CONFIG_CMD_SEVEN_SEG_DISPLAY
 #define CONFIG_CMD_SHMEM
-#undef  CONFIG_CMD_SLEEP
+#undef CONFIG_CMD_SLEEP
 #define CONFIG_CMD_SLEEPMASK
 #define CONFIG_CMD_SLEEPMASK_SET
-#undef  CONFIG_CMD_SPI_FLASH
-#undef  CONFIG_CMD_SPI_NOR
-#undef  CONFIG_CMD_SPI_XFER
-#undef  CONFIG_CMD_STACKOVERFLOW
+#undef CONFIG_CMD_SPI_FLASH
+#undef CONFIG_CMD_SPI_NOR
+#undef CONFIG_CMD_SPI_XFER
+#undef CONFIG_CMD_STACKOVERFLOW
 #define CONFIG_CMD_SYSINFO
 #define CONFIG_CMD_SYSJUMP
 #define CONFIG_CMD_SYSLOCK
-#undef  CONFIG_CMD_TASK_RESET
-#undef  CONFIG_CMD_TASKREADY
-#undef  CONFIG_CMD_TCPC_DUMP
+#undef CONFIG_CMD_TASK_RESET
+#undef CONFIG_CMD_TASKREADY
+#undef CONFIG_CMD_TCPC_DUMP
 #define CONFIG_CMD_TEMP_SENSOR
 #define CONFIG_CMD_TIMERINFO
 #define CONFIG_CMD_TYPEC
-#undef  CONFIG_CMD_USART_INFO
-#undef  CONFIG_CMD_USB_PD_CABLE
-#undef  CONFIG_CMD_USB_PD_PE
+#undef CONFIG_CMD_USART_INFO
+#undef CONFIG_CMD_USB_PD_CABLE
+#undef CONFIG_CMD_USB_PD_PE
 #define CONFIG_CMD_WAITMS
-#undef  CONFIG_CMD_AP_RESET_LOG
+#undef CONFIG_CMD_AP_RESET_LOG
 
 /*****************************************************************************/
 
@@ -2003,6 +1999,15 @@
  */
 #undef CONFIG_FAN_UPDATE_PERIOD
 
+/*
+ * Enable fan slow response control mechanism.
+ * A specific type of fan needs a longer time to output the TACH
+ * signal to EC after EC outputs the PWM signal to the fan.
+ * During this period, the driver will read two consecutive RPM = 0.
+ * In this case, don't step the PWM duty too aggressively
+ */
+#undef CONFIG_FAN_BYPASS_SLOW_RESPONSE
+
 /*****************************************************************************/
 /* Flash configuration */
 
@@ -2240,7 +2245,6 @@
 /* If defined, protect rollback region readback using MPU. */
 #undef CONFIG_ROLLBACK_MPU_PROTECT
 
-
 /*
  * If defined, inject some locally generated entropy when secret is updated,
  * using board_get_entropy function.
@@ -2342,6 +2346,11 @@
 /* Support getting gpio flags. */
 #undef CONFIG_GPIO_GET_EXTENDED
 
+/*
+ * GPU Drivers
+ */
+#undef CONFIG_GPU_NVIDIA
+
 /* Do we want to detect the lid angle? */
 #undef CONFIG_LID_ANGLE
 
@@ -2438,7 +2447,7 @@
 #ifdef HAS_TASK_HOSTCMD
 #define CONFIG_HOSTCMD_EVENTS
 #else
-#undef  CONFIG_HOSTCMD_EVENTS
+#undef CONFIG_HOSTCMD_EVENTS
 #endif
 
 /*
@@ -2468,9 +2477,9 @@
  * recess period of CONFIG_HOSTCMD_RATE_LIMITING_RECESS will be
  * enforced.
  */
-#define CONFIG_HOSTCMD_RATE_LIMITING_PERIOD   (500 * MSEC)
-#define CONFIG_HOSTCMD_RATE_LIMITING_MIN_REST (3   * MSEC)
-#define CONFIG_HOSTCMD_RATE_LIMITING_RECESS   (20  * MSEC)
+#define CONFIG_HOSTCMD_RATE_LIMITING_PERIOD (500 * MSEC)
+#define CONFIG_HOSTCMD_RATE_LIMITING_MIN_REST (3 * MSEC)
+#define CONFIG_HOSTCMD_RATE_LIMITING_RECESS (20 * MSEC)
 
 /* PD MCU supports host commands */
 #undef CONFIG_HOSTCMD_PD
@@ -2515,10 +2524,8 @@
 /* Set entry in PD MCU's device rw_hash table */
 #define CONFIG_HOSTCMD_RWHASHPD
 
-#if !defined(TEST_BUILD) && !defined(TEST_FUZZ)
 /* Enable EC_CMD_LOCATE_CHIP */
 #define CONFIG_HOSTCMD_LOCATE_CHIP
-#endif
 
 /* Command to get the EC uptime (and optionally AP reset stats) */
 #define CONFIG_HOSTCMD_GET_UPTIME_INFO
@@ -2530,11 +2537,11 @@
  * List of host commands whose debug output will be suppressed
  * By default remove periodic commands and commands called often (SENSE).
  */
-#define CONFIG_SUPPRESSED_HOST_COMMANDS \
+#define CONFIG_SUPPRESSED_HOST_COMMANDS                                        \
 	EC_CMD_CONSOLE_SNAPSHOT, EC_CMD_CONSOLE_READ, EC_CMD_USB_PD_DISCOVERY, \
-	EC_CMD_USB_PD_POWER_INFO, EC_CMD_PD_GET_LOG_ENTRY, \
-	EC_CMD_MOTION_SENSE_CMD, EC_CMD_GET_NEXT_EVENT, EC_CMD_GET_UPTIME_INFO
-
+		EC_CMD_USB_PD_POWER_INFO, EC_CMD_PD_GET_LOG_ENTRY,             \
+		EC_CMD_MOTION_SENSE_CMD, EC_CMD_GET_NEXT_EVENT,                \
+		EC_CMD_GET_UPTIME_INFO
 
 /*****************************************************************************/
 
@@ -2776,7 +2783,6 @@
 #undef CONFIG_INA231
 #undef CONFIG_INA3221
 
-
 /*****************************************************************************/
 /* Inductive charging */
 
@@ -3011,6 +3017,11 @@
 #undef CONFIG_KEYBOARD_CUSTOMIZATION
 
 /*
+ * Allow support multiple keyboard matrix for speical key.
+ */
+#undef CONFIG_KEYBOARD_MULTIPLE
+
+/*
  * Allow board-specific 8042 keyboard callback when a key state is changed.
  */
 #undef CONFIG_KEYBOARD_SCANCODE_CALLBACK
@@ -3153,16 +3164,16 @@
 #undef CONFIG_LED_POWER_ACTIVE_LOW
 
 /* Support for LED driver chip(s) */
-#undef CONFIG_LED_DRIVER_DS2413  /* Maxim DS2413, on one-wire interface */
-#undef CONFIG_LED_DRIVER_LM3509  /* LM3509, on I2C interface */
+#undef CONFIG_LED_DRIVER_DS2413 /* Maxim DS2413, on one-wire interface */
+#undef CONFIG_LED_DRIVER_LM3509 /* LM3509, on I2C interface */
 #undef CONFIG_LED_DRIVER_LM3630A /* LM3630A, on I2C interface */
-#undef CONFIG_LED_DRIVER_LP5562  /* LP5562, on I2C interface */
-#undef CONFIG_LED_DRIVER_MP3385   /* MPS MP3385, on I2C */
-#undef CONFIG_LED_DRIVER_OZ554   /* O2Micro OZ554, on I2C */
+#undef CONFIG_LED_DRIVER_LP5562 /* LP5562, on I2C interface */
+#undef CONFIG_LED_DRIVER_MP3385 /* MPS MP3385, on I2C */
+#undef CONFIG_LED_DRIVER_OZ554 /* O2Micro OZ554, on I2C */
 #undef CONFIG_LED_DRIVER_IS31FL3733B /* Lumissil IS31FL3733B on I2C */
 #undef CONFIG_LED_DRIVER_IS31FL3743B /* Lumissil IS31FL3743B on SPI */
-#undef CONFIG_LED_DRIVER_AW20198     /* Awinic AW20198 on I2C */
-#undef CONFIG_LED_DRIVER_TLC59116F   /* TLC59116F on I2C */
+#undef CONFIG_LED_DRIVER_AW20198 /* Awinic AW20198 on I2C */
+#undef CONFIG_LED_DRIVER_TLC59116F /* TLC59116F on I2C */
 
 /* Enable late init for is31fl3743b. Work around b:232443638. */
 #undef CONFIG_IS31FL3743B_LATE_INIT
@@ -3266,15 +3277,15 @@
  * SLP signals (SLP_S3, SLP_S4, and SLP_S5) use virtual wires instead of
  * physical pins with eSPI interface.
  */
-#undef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#undef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-#undef CONFIG_HOSTCMD_ESPI_VW_SLP_S5
+#undef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+#undef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
+#undef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S5
 
 /* MCHP next two items are EC eSPI slave configuration */
 /* Maximum clock frequence eSPI EC slave advertises
  * Values in MHz are 20, 25, 33, 50, and 66
  */
-#undef CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ
+#undef CONFIG_HOST_INTERFACE_ESPI_EC_MAX_FREQ
 
 /* EC eSPI slave advertises IO lanes
  * 0 = Single
@@ -3282,7 +3293,7 @@
  * 2 = Single and Quad
  * 3 = Single, Dual, and Quad
  */
-#undef CONFIG_HOSTCMD_ESPI_EC_MODE
+#undef CONFIG_HOST_INTERFACE_ESPI_EC_MODE
 
 /* Bit map of eSPI channels EC advertises
  * bit[0] = 1 Peripheral channel
@@ -3290,7 +3301,7 @@
  * bit[2] = 1 OOB channel
  * bit[3] = 1 Flash channel
  */
-#undef CONFIG_HOSTCMD_ESPI_EC_CHAN_BITMAP
+#undef CONFIG_HOST_INTERFACE_ESPI_EC_CHAN_BITMAP
 
 /*
  * Background information (from Intel eSPI Compatibility Specification):
@@ -3321,7 +3332,7 @@
  * Don't enable this config if the platform implements the Deep-Sx entry as EC
  * needs to maintain these pins' states per request.
  */
-#undef CONFIG_HOSTCMD_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST
+#undef CONFIG_HOST_INTERFACE_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST
 
 /* Base address of low power RAM. */
 #undef CONFIG_LPRAM_BASE
@@ -3403,9 +3414,6 @@
  */
 #undef CONFIG_MCDP28X0
 
-/* Define clock input to MFT module. */
-#undef CONFIG_MFT_INPUT_LFCLK
-
 /* Minute-IA watchdog timer vector number. */
 #define CONFIG_MIA_WDT_VEC 0xFF
 
@@ -3577,7 +3585,7 @@
 #undef CONFIG_POWER_BUTTON_INIT_IDLE
 
 /* Timeout before power button task gives up starting system */
-#define CONFIG_POWER_BUTTON_INIT_TIMEOUT	1
+#define CONFIG_POWER_BUTTON_INIT_TIMEOUT 1
 
 /*
  * Enable delay between DSW_PWROK and PWRBTN assertion.
@@ -3634,10 +3642,12 @@
 #undef CONFIG_POWER_TRACK_HOST_SLEEP_STATE
 
 /*
- * Implement the '%li' printf format as a *32-bit* integer format,
- * as it might be expected by non-EC code.
+ * Allow the use of the "long" printf length modifier ('l') to be in 32-bit
+ * systems along with any supported conversion specifiers. Note that this also
+ * reenables support for the 'i' printf format. This config will only take
+ * effect if sizeof(long) == sizeof(uint32_t).
  */
-#undef CONFIG_PRINTF_LEGACY_LI_FORMAT
+#undef CONFIG_PRINTF_LONG_IS_32BITS
 
 /*
  * On x86 systems, define this option if the CPU_PROCHOT signal is active low.
@@ -4147,28 +4157,28 @@
 #undef CONFIG_TEMP_SENSOR
 
 /* Support particular temperature sensor chips */
-#undef CONFIG_TEMP_SENSOR_ADT7481	/* ADT 7481 sensor, on I2C bus */
-#undef CONFIG_TEMP_SENSOR_BD99992GW	/* BD99992GW PMIC, on I2C bus */
-#undef CONFIG_TEMP_SENSOR_EC_ADC        /* Thermistors on EC's own ADC */
-#undef CONFIG_TEMP_SENSOR_G753		/* G753 sensor, on I2C bus */
-#undef CONFIG_TEMP_SENSOR_G781		/* G781 sensor, on I2C bus */
-#undef CONFIG_TEMP_SENSOR_G782		/* G782 sensor, on I2C bus */
-#undef CONFIG_TEMP_SENSOR_OTI502	/* OTI502 sensor, on I2C bus */
-#undef CONFIG_TEMP_SENSOR_PCT2075	/* PCT2075 sensor, on I2C bus */
-#undef CONFIG_TEMP_SENSOR_SB_TSI	/* SB_TSI sensor, on I2C bus */
-#undef CONFIG_TEMP_SENSOR_TMP006	/* TI TMP006 sensor, on I2C bus */
-#undef CONFIG_TEMP_SENSOR_TMP112	/* TI TMP112 sensor, on I2C bus */
-#undef CONFIG_TEMP_SENSOR_TMP411	/* TI TMP411 sensor, on I2C bus */
-#undef CONFIG_TEMP_SENSOR_TMP432	/* TI TMP432 sensor, on I2C bus */
-#undef CONFIG_TEMP_SENSOR_TMP468	/* TI TMP468 sensor, on I2C bus */
-#undef CONFIG_TEMP_SENSOR_F75303	/* Fintek  F75303 sensor, on I2C bus */
-#undef CONFIG_TEMP_SENSOR_AMD_R19ME4070	/* AMD_R19ME4070 sensor, on I2C bus */
+#undef CONFIG_TEMP_SENSOR_ADT7481 /* ADT 7481 sensor, on I2C bus */
+#undef CONFIG_TEMP_SENSOR_BD99992GW /* BD99992GW PMIC, on I2C bus */
+#undef CONFIG_TEMP_SENSOR_EC_ADC /* Thermistors on EC's own ADC */
+#undef CONFIG_TEMP_SENSOR_G753 /* G753 sensor, on I2C bus */
+#undef CONFIG_TEMP_SENSOR_G781 /* G781 sensor, on I2C bus */
+#undef CONFIG_TEMP_SENSOR_G782 /* G782 sensor, on I2C bus */
+#undef CONFIG_TEMP_SENSOR_OTI502 /* OTI502 sensor, on I2C bus */
+#undef CONFIG_TEMP_SENSOR_PCT2075 /* PCT2075 sensor, on I2C bus */
+#undef CONFIG_TEMP_SENSOR_SB_TSI /* SB_TSI sensor, on I2C bus */
+#undef CONFIG_TEMP_SENSOR_TMP006 /* TI TMP006 sensor, on I2C bus */
+#undef CONFIG_TEMP_SENSOR_TMP112 /* TI TMP112 sensor, on I2C bus */
+#undef CONFIG_TEMP_SENSOR_TMP411 /* TI TMP411 sensor, on I2C bus */
+#undef CONFIG_TEMP_SENSOR_TMP432 /* TI TMP432 sensor, on I2C bus */
+#undef CONFIG_TEMP_SENSOR_TMP468 /* TI TMP468 sensor, on I2C bus */
+#undef CONFIG_TEMP_SENSOR_F75303 /* Fintek  F75303 sensor, on I2C bus */
+#undef CONFIG_TEMP_SENSOR_AMD_R19ME4070 /* AMD_R19ME4070 sensor, on I2C bus */
 
 /* Compile common code for thermistor support */
 #undef CONFIG_THERMISTOR
 
 /* Support particular thermistors */
-#undef CONFIG_THERMISTOR_NCP15WB	/* NCP15WB thermistor */
+#undef CONFIG_THERMISTOR_NCP15WB /* NCP15WB thermistor */
 
 /*
  * If defined, image includes lookup tables and helper functions that convert
@@ -4680,7 +4690,7 @@
  * Some TCPCs need additional time following a VBUS change to internally
  * debounce the CC line status and updating the CC_STATUS register.
  */
-#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE	(25*MSEC)
+#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (25 * MSEC)
 
 /* Define EC and TCPC modules are in one integrated chip */
 #undef CONFIG_USB_PD_TCPC_ON_CHIP
@@ -4805,6 +4815,7 @@
  * to provide the product id per port.
  */
 #undef CONFIG_USB_PD_TCPM_MULTI_PS8XXX
+#undef CONFIG_USB_PD_TCPM_PS8745
 #undef CONFIG_USB_PD_TCPM_PS8751
 #undef CONFIG_USB_PD_TCPM_PS8755
 #undef CONFIG_USB_PD_TCPM_PS8705
@@ -4969,6 +4980,15 @@
 #define CONFIG_USB_PD_TEMP_SENSOR 0
 
 /*
+ * Time limit in ms for a USB PD power button press to be considered a short
+ * press
+ */
+#define CONFIG_USB_PD_SHORT_PRESS_MAX_MS 4000
+
+/* Time limit in ms for a USB PD power button press to be considered valid. */
+#define CONFIG_USB_PD_LONG_PRESS_MAX_MS 8000
+
+/*
  * Set the minimum battery percentage to allow a PD port to send resets as a
  * sink (and risk a hard reset, losing Vbus).  Note this may cause a high-power
  * charger to appear as only a low-power 15W charger until a reset is sent to
@@ -5044,6 +5064,12 @@
 #undef CONFIG_USBC_PPC_SYV682X
 
 /*
+ * NX20P348x 5V SRC RCP trigger level at 10mV. Define to enable 5V SRC RCP
+ * mask for can't trigger interrupt signal.
+ */
+#undef CONFIG_USBC_NX20P348X_RCP_5VSRC_MASK_ENABLE
+
+/*
  * SYV682x PPC high voltage power path current limit.  Default limit is
  * 3.3A.  See the syv682x header file for permissible values.
  */
@@ -5064,6 +5090,9 @@
 /* PPC has level interrupts and has a dedicated interrupt pin to check */
 #undef CONFIG_USBC_PPC_DEDICATED_INT
 
+/* Enable logging related to the PPC. Undefine to reduce EC image size */
+#define CONFIG_USBC_PPC_LOGGING
+
 /* Support for USB type-c superspeed mux */
 #undef CONFIG_USBC_SS_MUX
 
@@ -5116,6 +5145,9 @@
 /* Common USB / BC1.2 charger detection routines */
 #undef CONFIG_USB_CHARGER
 
+/* Only allow PI3USB9201 to advertise itself as BC1.2 client */
+#undef CONFIG_BC12_CLIENT_MODE_ONLY_PI3USB9201
+
 /*
  * Used for bc1.2 chips that need to be triggered from data role swaps instead
  * of just VBUS changes.
@@ -5141,7 +5173,6 @@
 /* The delay in ms from power off to power on for MAX14637 */
 #define CONFIG_BC12_MAX14637_DELAY_FROM_OFF_TO_ON_MS 1
 
-
 /* Enable USB serial console module. */
 #undef CONFIG_USB_CONSOLE
 
@@ -5416,7 +5447,6 @@
  */
 #undef CONFIG_STREAM_SIGNATURE
 
-
 /*****************************************************************************/
 
 /*
@@ -5664,7 +5694,7 @@
  * Used to include files for unit and other builds tests.
  */
 
- /* Define to enable Policy Engine State Machine. */
+/* Define to enable Policy Engine State Machine. */
 #undef CONFIG_TEST_USB_PE_SM
 
 /* Define to enable USB State Machine framework. */
@@ -5691,13 +5721,13 @@
 /*
  * The USB port used for CCD. Defaults to 0/C0.
  */
-#define CONFIG_CCD_USBC_PORT_NUMBER	0
+#define CONFIG_CCD_USBC_PORT_NUMBER 0
 
 /*
  * The historical default SCI pulse width to the host is 65 microseconds, but
  * some chipsets may require different widths.
  */
-#define CONFIG_ESPI_DEFAULT_VW_WIDTH_US	65
+#define CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US 65
 
 /*****************************************************************************/
 /*
@@ -5723,9 +5753,9 @@
  * Define CONFIG_HOST_ESPI_VW_POWER_SIGNAL if any power signals from the host
  * are configured as virtual wires.
  */
-#if defined(CONFIG_HOSTCMD_ESPI_VW_SLP_S3) || \
-	defined(CONFIG_HOSTCMD_ESPI_VW_SLP_S4) || \
-	defined(CONFIG_HOSTCMD_ESPI_VW_SLP_S5)
+#if defined(CONFIG_HOSTCMD_ESPI_VW_SLP_S3) ||            \
+	defined(CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4) || \
+	defined(CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S5)
 #define CONFIG_HOST_ESPI_VW_POWER_SIGNAL
 #endif
 
@@ -5737,7 +5767,7 @@
  * with Key Locker support (TGL+).
  */
 #if defined(CONFIG_POWER_S4_RESIDENCY) && \
-	!defined(CONFIG_HOSTCMD_ESPI_VW_SLP_S5)
+	!defined(CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S5)
 #error "S4_RESIDENCY needs eSPI support or SLP_S5 routed"
 #endif
 
@@ -5746,7 +5776,7 @@
  * without using eSPI for host commands.
  */
 #if (!defined(CONFIG_ZEPHYR) && defined(CONFIG_HOST_ESPI_VW_POWER_SIGNAL) && \
-	!defined(CONFIG_HOST_INTERFACE_ESPI))
+     !defined(CONFIG_HOST_INTERFACE_ESPI))
 #error Must enable eSPI to enable virtual wires.
 #endif
 
@@ -5777,7 +5807,7 @@
 #if !defined(CONFIG_USBC_SS_MUX)
 #error CONFIG_USBC_SS_MUX must be enabled for USB4 mode support
 #endif
-# if !defined(CONFIG_USB_PD_ALT_MODE_DFP)
+#if !defined(CONFIG_USB_PD_ALT_MODE_DFP)
 #error CONFIG_USB_PD_ALT_MODE_DFP must be enabled for USB4 mode support
 #endif
 #endif
@@ -5824,9 +5854,9 @@
  * Ensure that CONFIG_USB_PD_TCPMV2 is being used with exactly one device type
  */
 #ifdef CONFIG_USB_PD_TCPMV2
-#if defined(CONFIG_USB_VPD) + \
-	defined(CONFIG_USB_CTVPD) + \
-	defined(CONFIG_USB_DRP_ACC_TRYSRC) != 1
+#if defined(CONFIG_USB_VPD) + defined(CONFIG_USB_CTVPD) + \
+		defined(CONFIG_USB_DRP_ACC_TRYSRC) !=     \
+	1
 #error Must define exactly one CONFIG_USB_ device type.
 #endif
 #endif
@@ -5847,7 +5877,7 @@
 #error Define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT is limited to TCPMv1
 #endif
 #ifndef CONFIG_USB_PD_3A_PORTS
-#define CONFIG_USB_PD_3A_PORTS	1
+#define CONFIG_USB_PD_3A_PORTS 1
 #endif
 /* USB4 support requires at least one port providing 3.0 A */
 #if defined(CONFIG_USB_PD_USB4) && CONFIG_USB_PD_3A_PORTS == 0
@@ -5855,14 +5885,13 @@
 #endif
 #endif
 
-
 /******************************************************************************/
 /*
  * Ensure CONFIG_USB_PD_TCPMV2 and CONFIG_USBC_SS_MUX both are defined. USBC
  * retimer firmware update feature requires both.
  */
 #if (defined(CONFIG_USBC_RETIMER_FW_UPDATE) && \
-	(!(defined(CONFIG_USB_PD_TCPMV2) && defined(CONFIG_USBC_SS_MUX))))
+     (!(defined(CONFIG_USB_PD_TCPMV2) && defined(CONFIG_USBC_SS_MUX))))
 #error Retimer firmware update requires TCPMv2 and USBC_SS_MUX
 #endif
 
@@ -5879,8 +5908,7 @@
 #error Must select only one type of host communication bus.
 #endif
 
-#if defined(CONFIG_HOSTCMD_X86) && \
-	!defined(CONFIG_HOST_INTERFACE_LPC) && \
+#if defined(CONFIG_HOSTCMD_X86) && !defined(CONFIG_HOST_INTERFACE_LPC) && \
 	!defined(CONFIG_HOST_INTERFACE_ESPI)
 #error Must select one type of host communication bus.
 #endif
@@ -5904,11 +5932,11 @@
 /* Automatic configuration of RAM banks **************************************/
 /* Assume one RAM bank if not specified, auto-compute number of banks        */
 #ifndef CONFIG_RAM_BANK_SIZE
-#define CONFIG_RAM_BANK_SIZE	CONFIG_RAM_SIZE
+#define CONFIG_RAM_BANK_SIZE CONFIG_RAM_SIZE
 #endif
 
 #ifndef CONFIG_RAM_BANKS
-#define CONFIG_RAM_BANKS	(CONFIG_RAM_SIZE / CONFIG_RAM_BANK_SIZE)
+#define CONFIG_RAM_BANKS (CONFIG_RAM_SIZE / CONFIG_RAM_BANK_SIZE)
 #endif
 
 /******************************************************************************/
@@ -5919,13 +5947,12 @@
  * the beginning of RAM.
  */
 #ifndef CONFIG_PANIC_DATA_SIZE
-#define CONFIG_PANIC_DATA_SIZE	sizeof(struct panic_data)
+#define CONFIG_PANIC_DATA_SIZE sizeof(struct panic_data)
 #endif
 
 #ifndef CONFIG_PANIC_DATA_BASE
-#define CONFIG_PANIC_DATA_BASE (CONFIG_RAM_BASE			\
-				+ CONFIG_RAM_SIZE			\
-				- CONFIG_PANIC_DATA_SIZE)
+#define CONFIG_PANIC_DATA_BASE \
+	(CONFIG_RAM_BASE + CONFIG_RAM_SIZE - CONFIG_PANIC_DATA_SIZE)
 #endif
 
 /******************************************************************************/
@@ -5957,7 +5984,6 @@
 #endif
 #endif /* !CONFIG_SHAREDMEM_MINIMUM_SIZE */
 
-
 /******************************************************************************/
 /*
  * Disable the built-in console history if using the experimental console.
@@ -5970,7 +5996,6 @@
 #define CONFIG_CRC8
 #endif /* defined(CONFIG_EXPERIMENTAL_CONSOLE) */
 
-
 /******************************************************************************/
 /*
  * Thermal throttling AP must have temperature sensor enabled to get
@@ -5989,7 +6014,6 @@
 #define CONFIG_TEMP_SENSOR
 #endif
 
-
 /******************************************************************************/
 /* The Matrix Keyboard Protocol depends on MKBP input devices and events. */
 #ifdef CONFIG_KEYBOARD_PROTOCOL_MKBP
@@ -6003,18 +6027,18 @@
 /******************************************************************************/
 /* MKBP events delivery methods. */
 #ifdef CONFIG_MKBP_EVENT
-#if !defined(CONFIG_MKBP_USE_CUSTOM) && \
-	!defined(CONFIG_MKBP_USE_HOST_EVENT) && \
-	!defined(CONFIG_MKBP_USE_GPIO) && \
+#if !defined(CONFIG_MKBP_USE_CUSTOM) &&                  \
+	!defined(CONFIG_MKBP_USE_HOST_EVENT) &&          \
+	!defined(CONFIG_MKBP_USE_GPIO) &&                \
 	!defined(CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT) && \
 	!defined(CONFIG_MKBP_USE_HECI)
 #error Please define one of CONFIG_MKBP_USE_* macro.
 #endif
 
-#if defined(CONFIG_MKBP_USE_CUSTOM) + \
-	defined(CONFIG_MKBP_USE_GPIO) + \
-	defined(CONFIG_MKBP_USE_HOST_EVENT) + \
-	defined(CONFIG_MKBP_USE_HOST_HECI) > 1
+#if defined(CONFIG_MKBP_USE_CUSTOM) + defined(CONFIG_MKBP_USE_GPIO) + \
+		defined(CONFIG_MKBP_USE_HOST_EVENT) +                 \
+		defined(CONFIG_MKBP_USE_HOST_HECI) >                  \
+	1
 #error Must select only one type of MKBP event delivery method.
 #endif
 #endif /* CONFIG_MKBP_EVENT */
@@ -6031,27 +6055,22 @@
 
 /*****************************************************************************/
 /* Define CONFIG_BATTERY if board has a battery. */
-#if defined(CONFIG_BATTERY_BQ20Z453) || \
-	defined(CONFIG_BATTERY_BQ27541) || \
-	defined(CONFIG_BATTERY_BQ27621) || \
-	defined(CONFIG_BATTERY_BQ4050) || \
-	defined(CONFIG_BATTERY_MAX17055) || \
-	defined(CONFIG_BATTERY_MM8013) || \
+#if defined(CONFIG_BATTERY_BQ20Z453) || defined(CONFIG_BATTERY_BQ27541) ||    \
+	defined(CONFIG_BATTERY_BQ27621) || defined(CONFIG_BATTERY_BQ4050) ||  \
+	defined(CONFIG_BATTERY_MAX17055) || defined(CONFIG_BATTERY_MM8013) || \
 	defined(CONFIG_BATTERY_SMART)
 #define CONFIG_BATTERY
 #endif
 
 /*****************************************************************************/
 /* Define CONFIG_USBC_PPC if board has a USB Type-C Power Path Controller. */
-#if defined(CONFIG_USBC_PPC_AOZ1380) || \
-	defined(CONFIG_USBC_PPC_NX20P3483) || \
+#if defined(CONFIG_USBC_PPC_AOZ1380) || defined(CONFIG_USBC_PPC_NX20P3483) || \
 	defined(CONFIG_USBC_PPC_SN5S330)
 #define CONFIG_USBC_PPC
 #endif /* "has a PPC" */
 
 /* Following chips use Power Path Control information from TCPC chip */
-#if defined(CONFIG_USBC_PPC_AOZ1380) || \
-	defined(CONFIG_USBC_PPC_NX20P3481) || \
+#if defined(CONFIG_USBC_PPC_AOZ1380) || defined(CONFIG_USBC_PPC_NX20P3481) || \
 	defined(CONFIG_USBC_PPC_NX20P3483)
 #define CONFIG_USB_PD_PPC
 #endif
@@ -6063,7 +6082,6 @@
 #define CONFIG_USBC_PPC_VCONN
 #endif
 
-
 /*****************************************************************************/
 /* PPC SYV682C is a subset of SYV682X. */
 #if defined(CONFIG_USBC_PPC_SYV682C)
@@ -6100,13 +6118,11 @@
 
 /*****************************************************************************/
 /* Define CONFIG_USBC_OCP if a component can detect overcurrent */
-#if defined(CONFIG_USBC_PPC_AOZ1380) || \
-	defined(CONFIG_USBC_PPC_KTU1125) || \
-	defined(CONFIG_USBC_PPC_NX20P3481) || \
-	defined(CONFIG_USBC_PPC_NX20P3483) || \
-	defined(CONFIG_USBC_PPC_SN5S330) || \
-	defined(CONFIG_USBC_PPC_SYV682X)  || \
-	defined(CONFIG_CHARGER_SM5803) || \
+#if defined(CONFIG_USBC_PPC_AOZ1380) || defined(CONFIG_USBC_PPC_KTU1125) ||   \
+	defined(CONFIG_USBC_PPC_NX20P3481) ||                                 \
+	defined(CONFIG_USBC_PPC_NX20P3483) ||                                 \
+	defined(CONFIG_USBC_PPC_SN5S330) ||                                   \
+	defined(CONFIG_USBC_PPC_SYV682X) || defined(CONFIG_CHARGER_SM5803) || \
 	defined(CONFIG_USB_PD_TCPM_TCPCI)
 #define CONFIG_USBC_OCP
 #endif
@@ -6116,14 +6132,10 @@
  * Define CONFIG_USB_PD_VBUS_MEASURE_CHARGER if the charger on the board
  * supports VBUS measurement.
  */
-#if defined(CONFIG_CHARGER_BD9995X) || \
-	defined(CONFIG_CHARGER_RT9466) || \
-	defined(CONFIG_CHARGER_RT9467) || \
-	defined(CONFIG_CHARGER_RT9490) || \
-	defined(CONFIG_CHARGER_MT6370) || \
-	defined(CONFIG_CHARGER_BQ25710) || \
-	defined(CONFIG_CHARGER_BQ25720) || \
-	defined(CONFIG_CHARGER_ISL9241)
+#if defined(CONFIG_CHARGER_BD9995X) || defined(CONFIG_CHARGER_RT9466) ||     \
+	defined(CONFIG_CHARGER_RT9467) || defined(CONFIG_CHARGER_RT9490) ||  \
+	defined(CONFIG_CHARGER_MT6370) || defined(CONFIG_CHARGER_BQ25710) || \
+	defined(CONFIG_CHARGER_BQ25720) || defined(CONFIG_CHARGER_ISL9241)
 #define CONFIG_USB_PD_VBUS_MEASURE_CHARGER
 
 #ifdef CONFIG_USB_PD_VBUS_MEASURE_NOT_PRESENT
@@ -6162,7 +6174,7 @@
  * Define CONFIG_CHARGER_NARROW_VDC for chargers that use a Narrow VDC power
  * architecture.
  */
-#if defined(CONFIG_CHARGER_ISL9237) || defined(CONFIG_CHARGER_ISL9238) || \
+#if defined(CONFIG_CHARGER_ISL9237) || defined(CONFIG_CHARGER_ISL9238) ||      \
 	defined(CONFIG_CHARGER_ISL9238C) || defined(CONFIG_CHARGER_ISL9241) || \
 	defined(CONFIG_CHARGER_RAA489000) || defined(CONFIG_CHARGER_SM5803) || \
 	defined(CONFIG_CHARGER_BQ25710) || defined(CONFIG_CHARGER_BQ25720)
@@ -6178,7 +6190,6 @@
 #define CONFIG_BUTTON_TRIGGERED_RECOVERY
 #endif /* defined(CONFIG_DEDICATED_RECOVERY_BUTTON) */
 
-
 #ifdef CONFIG_LED_PWM_COUNT
 #define CONFIG_LED_PWM
 #endif /* defined(CONFIG_LED_PWM_COUNT) */
@@ -6213,7 +6224,7 @@
 
 /*****************************************************************************/
 /* Define derived USB PD Discharge common path */
-#if defined(CONFIG_USB_PD_DISCHARGE_GPIO) || \
+#if defined(CONFIG_USB_PD_DISCHARGE_GPIO) ||     \
 	defined(CONFIG_USB_PD_DISCHARGE_TCPC) || \
 	defined(CONFIG_USB_PD_DISCHARGE_PPC)
 #define CONFIG_USB_PD_DISCHARGE
@@ -6235,6 +6246,7 @@
 /* Define derived config options for BC1.2 detection */
 #ifdef CONFIG_BC12_DETECT_PI3USB9201
 #define CONFIG_BC12_DETECT_DATA_ROLE_TRIGGER
+#undef CONFIG_BC12_CLIENT_MODE_ONLY_PI3USB9201
 #endif
 
 /*****************************************************************************/
@@ -6258,7 +6270,6 @@
 #undef CONFIG_CHIPSET_ALDERLAKE
 #undef CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540
 #undef CONFIG_CHIPSET_APOLLOLAKE
-#undef CONFIG_CHIPSET_BRASWELL
 #undef CONFIG_CHIPSET_CANNONLAKE
 #undef CONFIG_CHIPSET_COMETLAKE
 #undef CONFIG_CHIPSET_GEMINILAKE
@@ -6286,7 +6297,7 @@
 #ifndef CONFIG_AP_POWER_CONTROL
 #ifdef HAS_TASK_CHIPSET
 #define CONFIG_AP_POWER_CONTROL
-#endif	/* HAS_TASK_CHIPSET */
+#endif /* HAS_TASK_CHIPSET */
 #endif /* CONFIG_AP_POWER_CONTROL */
 
 /*
@@ -6307,12 +6318,11 @@
 #endif /* !defined(CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON) */
 #endif /* defined(HAS_TASK_CHIPSET) */
 
-
 #ifdef CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW
-# ifndef CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT
-#  define CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT \
+#ifndef CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT
+#define CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT \
 	(CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON)
-# endif
+#endif
 #endif
 
 #ifndef CONFIG_CHARGER_MIN_BAT_PCT_IMBALANCED_POWER_ON
@@ -6381,13 +6391,11 @@
 
 /*****************************************************************************/
 /* Define derived Chipset configs */
-#if defined(CONFIG_CHIPSET_APOLLOLAKE) || \
-	defined(CONFIG_CHIPSET_GEMINILAKE)
+#if defined(CONFIG_CHIPSET_APOLLOLAKE) || defined(CONFIG_CHIPSET_GEMINILAKE)
 #define CONFIG_CHIPSET_APL_GLK
 #endif
 
-#if defined(CONFIG_CHIPSET_JASPERLAKE) || \
-	defined(CONFIG_CHIPSET_TIGERLAKE) || \
+#if defined(CONFIG_CHIPSET_JASPERLAKE) || defined(CONFIG_CHIPSET_TIGERLAKE) || \
 	defined(CONFIG_CHIPSET_ALDERLAKE)
 #define CONFIG_CHIPSET_ICELAKE
 #endif
@@ -6397,28 +6405,25 @@
 #define CONFIG_CHIPSET_X86_RSMRST_AFTER_S5
 #endif
 
-#if defined(CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540) || \
-	defined(CONFIG_CHIPSET_APOLLOLAKE) || \
-	defined(CONFIG_CHIPSET_BRASWELL) || \
-	defined(CONFIG_CHIPSET_CANNONLAKE) || \
-	defined(CONFIG_CHIPSET_COMETLAKE) || \
+#if defined(CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540) ||  \
+	defined(CONFIG_CHIPSET_APOLLOLAKE) ||         \
+	defined(CONFIG_CHIPSET_CANNONLAKE) ||         \
+	defined(CONFIG_CHIPSET_COMETLAKE) ||          \
 	defined(CONFIG_CHIPSET_COMETLAKE_DISCRETE) || \
-	defined(CONFIG_CHIPSET_GEMINILAKE) || \
-	defined(CONFIG_CHIPSET_ICELAKE) || \
-	defined(CONFIG_CHIPSET_METEORLAKE) || \
-	defined(CONFIG_CHIPSET_SKYLAKE)
+	defined(CONFIG_CHIPSET_GEMINILAKE) ||         \
+	defined(CONFIG_CHIPSET_ICELAKE) ||            \
+	defined(CONFIG_CHIPSET_METEORLAKE) || defined(CONFIG_CHIPSET_SKYLAKE)
 #define CONFIG_POWER_COMMON
 #endif
 
 #if defined(CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540) || \
-	defined(CONFIG_CHIPSET_CANNONLAKE) || \
-	defined(CONFIG_CHIPSET_ICELAKE) || \
-	defined(CONFIG_CHIPSET_METEORLAKE) || \
-	defined(CONFIG_CHIPSET_SKYLAKE)
+	defined(CONFIG_CHIPSET_CANNONLAKE) ||        \
+	defined(CONFIG_CHIPSET_ICELAKE) ||           \
+	defined(CONFIG_CHIPSET_METEORLAKE) || defined(CONFIG_CHIPSET_SKYLAKE)
 #define CONFIG_CHIPSET_X86_RSMRST_DELAY
 #endif
 
-#if defined(CONFIG_HOSTCMD_ESPI_VW_SLP_S3) && \
+#if defined(CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3) && \
 	defined(CONFIG_CHIPSET_SLP_S3_L_OVERRIDE)
 #error "Cannot use CONFIG_CHIPSET_SLP_S3_L_OVERRIDE if SLP_S3 is a virtual wire"
 #endif
@@ -6443,8 +6448,7 @@
 /*
  * Automatically define CONFIG_ACCEL_LIS2D_COMMON if a child option is defined.
  */
-#if defined(CONFIG_ACCEL_LIS2DH) || \
-	defined(CONFIG_ACCEL_LIS2DE) || \
+#if defined(CONFIG_ACCEL_LIS2DH) || defined(CONFIG_ACCEL_LIS2DE) || \
 	defined(CONFIG_ACCEL_LNG2DM)
 #define CONFIG_ACCEL_LIS2D_COMMON
 #endif
@@ -6452,8 +6456,7 @@
 /*
  * Automatically define CONFIG_ACCEL_LIS2DW_COMMON if a child option is defined.
  */
-#if defined(CONFIG_ACCEL_LIS2DW12) || \
-	defined(CONFIG_ACCEL_LIS2DWL)
+#if defined(CONFIG_ACCEL_LIS2DW12) || defined(CONFIG_ACCEL_LIS2DWL)
 #define CONFIG_ACCEL_LIS2DW_COMMON
 #endif
 
@@ -6461,8 +6464,7 @@
  * CONFIG_ACCEL_LIS2DW12 and CONFIG_ACCEL_LIS2DWL can't be defined at the same
  * time.
  */
-#if defined(CONFIG_ACCEL_LIS2DW12) && \
-	defined(CONFIG_ACCEL_LIS2DWL)
+#if defined(CONFIG_ACCEL_LIS2DW12) && defined(CONFIG_ACCEL_LIS2DWL)
 #error "Define only one of CONFIG_ACCEL_LIS2DW12 and CONFIG_ACCEL_LIS2DWL"
 #endif
 
@@ -6500,7 +6502,6 @@
 #error CONFIG_CHIP_INIT_ROM_REGION requires CONFIG_RW_ROM_RESIDENT_SIZE
 #endif
 
-
 #if (CONFIG_RO_ROM_RESIDENT_SIZE == 0)
 #error CONFIG_RO_ROM_RESIDENT_SIZE is 0 with CONFIG_CHIP_INIT_ROM_REGION defined
 #endif
@@ -6520,11 +6521,13 @@
 
 /*
  * By default, enable a request for an ACK from AP, on setting the mux, if the
- * board supports Burnside Bridge retimer.
+ * board supports Intel retimer.
  */
-#if defined(CONFIG_USBC_RETIMER_INTEL_BB) && defined(CONFIG_USB_MUX_VIRTUAL)
+#if (defined(CONFIG_USBC_RETIMER_INTEL_BB) ||  \
+     defined(CONFIG_USBC_RETIMER_INTEL_HB)) && \
+	defined(CONFIG_USB_MUX_VIRTUAL)
 #define CONFIG_USB_MUX_AP_ACK_REQUEST
-#endif /* CONFIG_USBC_RETIMER_INTEL_BB  */
+#endif /* CONFIG_USBC_RETIMER_INTEL_BB || CONFIG_USBC_RETIMER_INTEL_HB */
 
 /*****************************************************************************/
 
@@ -6546,7 +6549,7 @@
  * period.
  */
 #ifdef CONFIG_WATCHDOG
-#if (CONFIG_AUX_TIMER_PERIOD_MS) < ((HOOK_TICK_INTERVAL_MS) * 2)
+#if (CONFIG_AUX_TIMER_PERIOD_MS) < ((HOOK_TICK_INTERVAL_MS)*2)
 #error "CONFIG_AUX_TIMER_PERIOD_MS must be at least 2x HOOK_TICK_INTERVAL_MS"
 #endif
 #endif
@@ -6565,20 +6568,17 @@
 #endif
 
 /* Enable BMI secondary port if needed. */
-#if defined(CONFIG_MAG_BMI_BMM150) || \
-	defined(CONFIG_MAG_BMI_LIS2MDL)
+#if defined(CONFIG_MAG_BMI_BMM150) || defined(CONFIG_MAG_BMI_LIS2MDL)
 #define CONFIG_BMI_SEC_I2C
 #endif
 
 /* Enable LSM2MDL secondary port if needed. */
-#if defined(CONFIG_MAG_LSM6DSM_BMM150) || \
-	defined(CONFIG_MAG_LSM6DSM_LIS2MDL)
+#if defined(CONFIG_MAG_LSM6DSM_BMM150) || defined(CONFIG_MAG_LSM6DSM_LIS2MDL)
 #define CONFIG_LSM6DSM_SEC_I2C
 #endif
 
 /* Load LIS2MDL driver if needed */
-#if defined(CONFIG_MAG_BMI_LIS2MDL) || \
-	defined(CONFIG_MAG_LSM6DSM_LIS2MDL)
+#if defined(CONFIG_MAG_BMI_LIS2MDL) || defined(CONFIG_MAG_LSM6DSM_LIS2MDL)
 #define CONFIG_MAG_LIS2MDL
 #ifndef CONFIG_ACCELGYRO_SEC_ADDR_FLAGS
 #error "The i2c address of the magnetometer is not set."
@@ -6586,8 +6586,7 @@
 #endif
 
 /* Load BMM150 driver if needed */
-#if defined(CONFIG_MAG_BMI_BMM150) || \
-	defined(CONFIG_MAG_LSM6DSM_BMM150)
+#if defined(CONFIG_MAG_BMI_BMM150) || defined(CONFIG_MAG_LSM6DSM_BMM150)
 #define CONFIG_MAG_BMM150
 #ifndef CONFIG_ACCELGYRO_SEC_ADDR_FLAGS
 #error "The i2c address of the magnetometer is not set."
@@ -6620,7 +6619,7 @@
 #endif
 #endif /* CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE */
 
-#if defined(CONFIG_USB_PD_TCPM_ANX3429) || \
+#if defined(CONFIG_USB_PD_TCPM_ANX3429) ||     \
 	defined(CONFIG_USB_PD_TCPM_ANX740X) || \
 	defined(CONFIG_USB_PD_TCPM_ANX7471)
 /* Note: ANX7447 is handled by its own driver, not ANX74XX. */
@@ -6646,10 +6645,8 @@
 
 /*****************************************************************************/
 /* ISH power management related definitions */
-#if defined(CONFIG_ISH_PM_D0I2) || \
-	defined(CONFIG_ISH_PM_D0I3) || \
-	defined(CONFIG_ISH_PM_D3) || \
-	defined(CONFIG_ISH_PM_RESET_PREP)
+#if defined(CONFIG_ISH_PM_D0I2) || defined(CONFIG_ISH_PM_D0I3) || \
+	defined(CONFIG_ISH_PM_D3) || defined(CONFIG_ISH_PM_RESET_PREP)
 
 #ifndef CONFIG_LOW_POWER_IDLE
 #error "Must define CONFIG_LOW_POWER_IDLE if enable ISH low power states"
@@ -6682,7 +6679,6 @@
 
 #endif /* CONFIG_ACCEL_FIFO */
 
-
 /*
  * If USB PD Discharge is enabled, verify that CONFIG_USB_PD_DISCHARGE_GPIO
  * and CONFIG_USB_PD_PORT_MAX_COUNT, CONFIG_USB_PD_DISCHARGE_TCPC, or
@@ -6753,21 +6749,21 @@
 #endif
 
 #if defined(CONFIG_USB_PD_TCPM_MULTI_PS8XXX)
-#if defined(CONFIG_USB_PD_TCPM_PS8705) + \
-	defined(CONFIG_USB_PD_TCPM_PS8751) + \
-	defined(CONFIG_USB_PD_TCPM_PS8755) + \
-	defined(CONFIG_USB_PD_TCPM_PS8805) + \
-	defined(CONFIG_USB_PD_TCPM_PS8815) < 2
+#if defined(CONFIG_USB_PD_TCPM_PS8705) + defined(CONFIG_USB_PD_TCPM_PS8751) + \
+		defined(CONFIG_USB_PD_TCPM_PS8755) +                          \
+		defined(CONFIG_USB_PD_TCPM_PS8805) +                          \
+		defined(CONFIG_USB_PD_TCPM_PS8815) <                          \
+	2
 #error "Must select 2 CONFIG_USB_PD_TCPM_PS8* or above if " \
 	"CONFIG_USB_PD_TCPM_MULTI_PS8XXX is defined."
 #endif
 #endif /* CONFIG_USB_PD_TCPM_MULTI_PS8XXX  */
 
-#if defined(CONFIG_USB_PD_TCPM_PS8705) + \
-	defined(CONFIG_USB_PD_TCPM_PS8751) + \
-	defined(CONFIG_USB_PD_TCPM_PS8755) + \
-	defined(CONFIG_USB_PD_TCPM_PS8805) + \
-	defined(CONFIG_USB_PD_TCPM_PS8815) > 1
+#if defined(CONFIG_USB_PD_TCPM_PS8705) + defined(CONFIG_USB_PD_TCPM_PS8751) + \
+		defined(CONFIG_USB_PD_TCPM_PS8755) +                          \
+		defined(CONFIG_USB_PD_TCPM_PS8805) +                          \
+		defined(CONFIG_USB_PD_TCPM_PS8815) >                          \
+	1
 #if !defined(CONFIG_USB_PD_TCPM_MULTI_PS8XXX)
 #error "CONFIG_USB_PD_TCPM_MULTI_PS8XXX MUST be defined if more than one " \
 	"CONFIG_USB_PD_TCPM_PS8* are intended to support in a board."
@@ -6782,25 +6778,25 @@
 #endif /* ifndef(CONFIG_BODY_DETECTION_SENSOR) */
 
 #ifndef CONFIG_BODY_DETECTION_MAX_WINDOW_SIZE
-#define CONFIG_BODY_DETECTION_MAX_WINDOW_SIZE     250 /* max sensor odr (Hz) */
+#define CONFIG_BODY_DETECTION_MAX_WINDOW_SIZE 250 /* max sensor odr (Hz) */
 #endif
 #ifndef CONFIG_BODY_DETECTION_VAR_THRESHOLD
-#define CONFIG_BODY_DETECTION_VAR_THRESHOLD       550 /* (mm/s^2)^2 */
+#define CONFIG_BODY_DETECTION_VAR_THRESHOLD 550 /* (mm/s^2)^2 */
 #endif
 #ifndef CONFIG_BODY_DETECTION_CONFIDENCE_DELTA
-#define CONFIG_BODY_DETECTION_CONFIDENCE_DELTA    525 /* (mm/s^2)^2 */
+#define CONFIG_BODY_DETECTION_CONFIDENCE_DELTA 525 /* (mm/s^2)^2 */
 #endif
 #ifndef CONFIG_BODY_DETECTION_VAR_NOISE_FACTOR
-#define CONFIG_BODY_DETECTION_VAR_NOISE_FACTOR    120 /* % */
+#define CONFIG_BODY_DETECTION_VAR_NOISE_FACTOR 120 /* % */
 #endif
 #ifndef CONFIG_BODY_DETECTION_ON_BODY_CON
-#define CONFIG_BODY_DETECTION_ON_BODY_CON         50  /* % */
+#define CONFIG_BODY_DETECTION_ON_BODY_CON 50 /* % */
 #endif
 #ifndef CONFIG_BODY_DETECTION_OFF_BODY_CON
-#define CONFIG_BODY_DETECTION_OFF_BODY_CON        10  /* % */
+#define CONFIG_BODY_DETECTION_OFF_BODY_CON 10 /* % */
 #endif
 #ifndef CONFIG_BODY_DETECTION_STATIONARY_DURATION
-#define CONFIG_BODY_DETECTION_STATIONARY_DURATION 15  /* second */
+#define CONFIG_BODY_DETECTION_STATIONARY_DURATION 15 /* second */
 #endif
 
 #else /* CONFIG_BODY_DETECTION */
@@ -6844,7 +6840,6 @@
 #define ALS_COUNT 0
 #endif /* CONFIG_ALS */
 
-
 /*
  * If the EC has exclusive control over CBI EEPROM WP, don't consult the main
  * flash WP.
@@ -6879,9 +6874,9 @@
 #else
 #define CONFIG_ACCELGYRO_ICM_COMM_SPI
 #endif
-#endif	/* !CONFIG_ZEPHYR && !CONFIG_ACCELGYRO_ICM_COMM_SPI &&
-	 * !CONFIG_ACCELGYRO_ICM_COMM_I2C
-	 */
+#endif /* !CONFIG_ZEPHYR && !CONFIG_ACCELGYRO_ICM_COMM_SPI && \
+	* !CONFIG_ACCELGYRO_ICM_COMM_I2C                      \
+	*/
 
 #if !defined(CONFIG_ZEPHYR) && !defined(CONFIG_ACCELGYRO_BMI_COMM_SPI) && \
 	!defined(CONFIG_ACCELGYRO_BMI_COMM_I2C)
@@ -6890,9 +6885,9 @@
 #else
 #define CONFIG_ACCELGYRO_BMI_COMM_SPI
 #endif
-#endif	/* !CONFIG_ZEPHYR && !CONFIG_ACCELGYRO_BMI_SPI && \
-	 * !CONFIG_ACCELGYRO_BMI_I2C
-	 */
+#endif /* !CONFIG_ZEPHYR && !CONFIG_ACCELGYRO_BMI_SPI && \
+	* !CONFIG_ACCELGYRO_BMI_I2C                      \
+	*/
 
 /* AMD STT requires AMD SB-RMI to be enabled */
 #if defined(CONFIG_AMD_STT) && !defined(CONFIG_AMD_SB_RMI)
@@ -6907,4 +6902,9 @@
 #define CONFIG_S5_EXIT_WAIT 4
 #endif
 
-#endif  /* __CROS_EC_CONFIG_H */
+/* HAS_GPU_DRIVER enables D-Notify and throttling. */
+#if defined(CONFIG_GPU_NVIDIA)
+#define HAS_GPU_DRIVER
+#endif
+
+#endif /* __CROS_EC_CONFIG_H */
diff --git a/include/config_std_internal_flash.h b/include/config_std_internal_flash.h
index d272f5136c..5da01a4d16 100644
--- a/include/config_std_internal_flash.h
+++ b/include/config_std_internal_flash.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -37,42 +37,38 @@
  * This is NOT a globally defined config, and is only used in this file
  * for convenience.
  */
-#define _IMAGE_SIZE		((CONFIG_FLASH_SIZE_BYTES - \
-				  CONFIG_SHAREDLIB_SIZE) / 2)
+#define _IMAGE_SIZE ((CONFIG_FLASH_SIZE_BYTES - CONFIG_SHAREDLIB_SIZE) / 2)
 
 /*
  * The EC uses the one bank of flash to emulate a SPI-like write protect
  * register with persistent state.
  */
 #define CONFIG_FLASH_PSTATE
-#define CONFIG_FW_PSTATE_SIZE	CONFIG_FLASH_BANK_SIZE
-#define CONFIG_FW_PSTATE_OFF	(_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
+#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE
+#define CONFIG_FW_PSTATE_OFF (_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
 
 /*
  * By default, there is no shared objects library.  However, if configured, the
  * shared objects library will be placed after the RO image.
  */
-#define CONFIG_SHAREDLIB_MEM_OFF	(CONFIG_RO_MEM_OFF + \
-					 _IMAGE_SIZE)
-#define CONFIG_SHAREDLIB_STORAGE_OFF	(CONFIG_RO_STORAGE_OFF + \
-					 _IMAGE_SIZE)
-#define CONFIG_SHAREDLIB_SIZE	0
+#define CONFIG_SHAREDLIB_MEM_OFF (CONFIG_RO_MEM_OFF + _IMAGE_SIZE)
+#define CONFIG_SHAREDLIB_STORAGE_OFF (CONFIG_RO_STORAGE_OFF + _IMAGE_SIZE)
+#define CONFIG_SHAREDLIB_SIZE 0
 
-#define CONFIG_RO_MEM_OFF	0
-#define CONFIG_RO_STORAGE_OFF	0
-#define CONFIG_RO_SIZE		(_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
-#define CONFIG_RW_MEM_OFF	(CONFIG_SHAREDLIB_MEM_OFF + \
-				 CONFIG_SHAREDLIB_SIZE)
-#define CONFIG_RW_STORAGE_OFF	0
-#define CONFIG_RW_SIZE		_IMAGE_SIZE
+#define CONFIG_RO_MEM_OFF 0
+#define CONFIG_RO_STORAGE_OFF 0
+#define CONFIG_RO_SIZE (_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
+#define CONFIG_RW_MEM_OFF (CONFIG_SHAREDLIB_MEM_OFF + CONFIG_SHAREDLIB_SIZE)
+#define CONFIG_RW_STORAGE_OFF 0
+#define CONFIG_RW_SIZE _IMAGE_SIZE
 
-#define CONFIG_EC_PROTECTED_STORAGE_OFF		0
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE	CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_OFF		CONFIG_RW_MEM_OFF
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE		(CONFIG_FLASH_SIZE_BYTES - \
-						 CONFIG_EC_WRITABLE_STORAGE_OFF)
+#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
+#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE \
+	(CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF)
 
-#define CONFIG_WP_STORAGE_OFF		CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE		CONFIG_EC_PROTECTED_STORAGE_SIZE
+#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
+#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
 
 #endif /* __CROS_EC_CONFIG_STD_INTERNAL_FLASH_H */
diff --git a/include/console.h b/include/console.h
index 457d24cc95..4e40eddac8 100644
--- a/include/console.h
+++ b/include/console.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,6 +16,10 @@
 #include "zephyr_console_shim.h"
 #endif
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /*
  * Define uart_shell_stop() and uart_shell_start() functions to start/stop the
  * running shell. To avoid having a guard on the build type, non-Zephyr builds
@@ -54,25 +58,9 @@ struct hex_buffer_params {
 	uint16_t size;
 };
 
-#define HEX_BUF(_buffer, _size) (&(const struct hex_buffer_params){ \
-	.buffer = (_buffer), \
-	.size = (_size) \
-})
-
-/*
- * Define parameters to printing in binary: the value to print, and the number
- * of digits to print.
- */
-
-struct binary_print_params {
-	unsigned int value;
-	uint8_t count;
-};
-
-#define BINARY_VALUE(_value, _count) (&(const struct binary_print_params){ \
-	.value = (_value), \
-	.count = (_count) \
-})
+#define HEX_BUF(_buffer, _size)                                  \
+	(&(const struct hex_buffer_params){ .buffer = (_buffer), \
+					    .size = (_size) })
 
 #define PRINTF_TIMESTAMP_NOW NULL
 
@@ -81,7 +69,7 @@ struct console_command {
 	/* Command name.  Case-insensitive. */
 	const char *name;
 	/* Handler for the command.  argv[0] will be the command name. */
-	int (*handler)(int argc, char **argv);
+	int (*handler)(int argc, const char **argv);
 #ifdef CONFIG_CONSOLE_CMDHELP
 	/* Description of args */
 	const char *argdesc;
@@ -94,7 +82,7 @@ struct console_command {
 };
 
 /* Flag bits for when CONFIG_CONSOLE_COMMAND_FLAGS is enabled */
-#define CMD_FLAG_RESTRICTED  0x00000001
+#define CMD_FLAG_RESTRICTED 0x00000001
 
 /* The default .flags value can be overridden in board.h */
 #ifndef CONFIG_CONSOLE_COMMAND_FLAGS_DEFAULT
@@ -116,19 +104,19 @@ static inline int console_is_restricted(void)
 
 /* Console channels */
 enum console_channel {
-	#define CONSOLE_CHANNEL(enumeration, string) enumeration,
-	#include "console_channel.inc"
-	#undef CONSOLE_CHANNEL
+#define CONSOLE_CHANNEL(enumeration, string) enumeration,
+#include "console_channel.inc"
+#undef CONSOLE_CHANNEL
 
 	/* Channel count; not itself a channel */
 	CC_CHANNEL_COUNT
 };
 
 /* Mask in channel_mask for a particular channel */
-#define CC_MASK(channel)	(1U << (channel))
+#define CC_MASK(channel) (1U << (channel))
 
 /* Mask to use to enable all channels */
-#define CC_ALL			0xffffffffU
+#define CC_ALL 0xffffffffU
 
 /**
  * Enable a console channel by name
@@ -178,20 +166,20 @@ int cputs(enum console_channel channel, const char *outstr);
  *
  * @return non-zero if output was truncated.
  */
-__attribute__((__format__(__printf__, 2, 3)))
-int cprintf(enum console_channel channel, const char *format, ...);
+__attribute__((__format__(__printf__, 2, 3))) int
+cprintf(enum console_channel channel, const char *format, ...);
 
 /**
  * Print formatted output with timestamp. This is like:
- *   cprintf(channel, "[%pT " + format + "]\n", PRINTF_TIMESTAMP_NOW, ...)
+ *   cprintf(channel, "[<TIMESTAMP> " + format + "]\n", ...)
  *
  * @param channel	Output channel
  * @param format	Format string; see printf.h for valid formatting codes
  *
  * @return non-zero if output was truncated.
  */
-__attribute__((__format__(__printf__, 2, 3)))
-int cprints(enum console_channel channel, const char *format, ...);
+__attribute__((__format__(__printf__, 2, 3))) int
+cprints(enum console_channel channel, const char *format, ...);
 
 /**
  * Flush the console output for all channels.
@@ -205,8 +193,8 @@ void cflush(void);
 #define ccputs(outstr) cputs(CC_COMMAND, outstr)
 /* gcc allows variable arg lists in macros; see
  * http://gcc.gnu.org/onlinedocs/gcc/Variadic-Macros.html */
-#define ccprintf(format, args...) cprintf(CC_COMMAND, format, ## args)
-#define ccprints(format, args...) cprints(CC_COMMAND, format, ## args)
+#define ccprintf(format, args...) cprintf(CC_COMMAND, format, ##args)
+#define ccprints(format, args...) cprints(CC_COMMAND, format, ##args)
 
 /**
  * Called by UART when a line of input is pending.
@@ -221,51 +209,47 @@ void console_has_input(void);
  *                      long (excluding null terminator).  Note this is NOT in
  *                      quotes so it can be concatenated to form a struct name.
  * @param routine       Command handling routine, of the form
- *                      int handler(int argc, char **argv)
+ *                      int handler(int argc, const char **argv)
  * @param argdesc       String describing arguments to command; NULL if none.
  * @param help          String with one-line description of command, or NULL.
  * @param flags         Per-command flags, if needed.
  */
 #if !defined(HAS_TASK_CONSOLE) && !defined(CONFIG_ZEPHYR)
-#define DECLARE_CONSOLE_COMMAND(NAME, ROUTINE, ARGDESC, HELP)		\
-	static int (ROUTINE)(int argc, char **argv) __attribute__((unused))
-#define DECLARE_SAFE_CONSOLE_COMMAND(NAME, ROUTINE, ARGDESC, HELP)	\
-	static int (ROUTINE)(int argc, char **argv) __attribute__((unused))
+#define DECLARE_CONSOLE_COMMAND(NAME, ROUTINE, ARGDESC, HELP) \
+	static int(ROUTINE)(int argc, const char **argv) __attribute__((unused))
+#define DECLARE_SAFE_CONSOLE_COMMAND(NAME, ROUTINE, ARGDESC, HELP) \
+	static int(ROUTINE)(int argc, const char **argv) __attribute__((unused))
 #define DECLARE_CONSOLE_COMMAND_FLAGS(NAME, ROUTINE, ARGDESC, HELP, FLAGS) \
-	static int (ROUTINE)(int argc, char **argv) __attribute__((unused))
+	static int(ROUTINE)(int argc, const char **argv) __attribute__((unused))
 #elif defined(HAS_TASK_CONSOLE)
 
 /* We always provde help args, but we may discard them to save space. */
 #if defined(CONFIG_CONSOLE_CMDHELP)
-#define _HELP_ARGS(A, H)						\
-	.argdesc = A,							\
-	.help = H,
+#define _HELP_ARGS(A, H) .argdesc = A, .help = H,
 #else
 #define _HELP_ARGS(A, H)
 #endif
 
 /* We may or may not have a .flags field */
 #ifdef CONFIG_CONSOLE_COMMAND_FLAGS
-#define _FLAG_ARGS(F)							\
-	.flags = F,
+#define _FLAG_ARGS(F) .flags = F,
 #else
 #define _FLAG_ARGS(F)
 #endif
 
 /* This macro takes all possible args and discards the ones we don't use */
-#define _DCL_CON_CMD_ALL(NAME, ROUTINE, ARGDESC, HELP, FLAGS)		\
-	static int (ROUTINE)(int argc, char **argv);			\
-	static const char __con_cmd_label_##NAME[] = #NAME;		\
-	_STATIC_ASSERT(sizeof(__con_cmd_label_##NAME) < 16,		\
-		       "command name '" #NAME "' is too long");		\
-	const struct console_command __keep __no_sanitize_address	\
-	__con_cmd_##NAME						\
-	__attribute__((section(".rodata.cmds." #NAME))) =		\
-	{ .name = __con_cmd_label_##NAME,				\
-	  .handler = ROUTINE,						\
-	  _HELP_ARGS(ARGDESC, HELP)					\
-	  _FLAG_ARGS(FLAGS)						\
-	}
+#define _DCL_CON_CMD_ALL(NAME, ROUTINE, ARGDESC, HELP, FLAGS)       \
+	static int(ROUTINE)(int argc, const char **argv);           \
+	static const char __con_cmd_label_##NAME[] = #NAME;         \
+	_STATIC_ASSERT(sizeof(__con_cmd_label_##NAME) < 16,         \
+		       "command name '" #NAME "' is too long");     \
+	const struct console_command __keep __no_sanitize_address   \
+		__con_cmd_##NAME                                    \
+		__attribute__((section(".rodata.cmds." #NAME))) = { \
+			.name = __con_cmd_label_##NAME,             \
+			.handler = ROUTINE,                         \
+			_HELP_ARGS(ARGDESC, HELP) _FLAG_ARGS(FLAGS) \
+		}
 
 /*
  * If the .flags field exists, we can use this to specify its value. If not,
@@ -275,8 +259,8 @@ void console_has_input(void);
 	_DCL_CON_CMD_ALL(NAME, ROUTINE, ARGDESC, HELP, FLAGS)
 
 /* This works as before, for the same reason. */
-#define DECLARE_CONSOLE_COMMAND(NAME, ROUTINE, ARGDESC, HELP)	\
-	_DCL_CON_CMD_ALL(NAME, ROUTINE, ARGDESC, HELP,		\
+#define DECLARE_CONSOLE_COMMAND(NAME, ROUTINE, ARGDESC, HELP) \
+	_DCL_CON_CMD_ALL(NAME, ROUTINE, ARGDESC, HELP,        \
 			 CONFIG_CONSOLE_COMMAND_FLAGS_DEFAULT)
 
 /*
@@ -284,11 +268,15 @@ void console_has_input(void);
  * the command is never restricted. BE CAREFUL! You should only use this for
  * commands that either do nothing or that do only safe things.
  */
-#define DECLARE_SAFE_CONSOLE_COMMAND(NAME, ROUTINE, ARGDESC, HELP)	\
-	_DCL_CON_CMD_ALL(NAME, ROUTINE, ARGDESC, HELP,			\
-			 (CONFIG_CONSOLE_COMMAND_FLAGS_DEFAULT &	\
+#define DECLARE_SAFE_CONSOLE_COMMAND(NAME, ROUTINE, ARGDESC, HELP) \
+	_DCL_CON_CMD_ALL(NAME, ROUTINE, ARGDESC, HELP,             \
+			 (CONFIG_CONSOLE_COMMAND_FLAGS_DEFAULT &   \
 			  ~CMD_FLAG_RESTRICTED))
 
-#endif	/* HAS_TASK_CONSOLE */
+#endif /* HAS_TASK_CONSOLE */
+
+#ifdef __cplusplus
+}
+#endif
 
-#endif  /* __CROS_EC_CONSOLE_H */
+#endif /* __CROS_EC_CONSOLE_H */
diff --git a/include/console_channel.inc b/include/console_channel.inc
index 96691c21c3..47f065e268 100644
--- a/include/console_channel.inc
+++ b/include/console_channel.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -110,3 +110,6 @@ CONSOLE_CHANNEL(CC_USBPD,        "usbpd")
 #endif
 CONSOLE_CHANNEL(CC_VBOOT,        "vboot")
 CONSOLE_CHANNEL(CC_HOOK,         "hook")
+#ifdef HAS_GPU_DRIVER
+CONSOLE_CHANNEL(CC_GPU,          "gpu")
+#endif
diff --git a/include/consumer.h b/include/consumer.h
index f6d164649e..a331e83a93 100644
--- a/include/consumer.h
+++ b/include/consumer.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/include/crc.h b/include/crc.h
index 04a82313d8..85d389e506 100644
--- a/include/crc.h
+++ b/include/crc.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/crc8.h b/include/crc8.h
index 45b2322b44..c20314311e 100644
--- a/include/crc8.h
+++ b/include/crc8.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/include/cros_board_info.h b/include/cros_board_info.h
index 9ed5e1777b..992192e910 100644
--- a/include/cros_board_info.h
+++ b/include/cros_board_info.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,21 +10,22 @@
 #include "common.h"
 #include "ec_commands.h"
 
-#define CBI_VERSION_MAJOR	0
-#define CBI_VERSION_MINOR	0
+#define CBI_VERSION_MAJOR 0
+#define CBI_VERSION_MINOR 0
 
 #ifdef CONFIG_CBI_GPIO
 /*
  * if CBI is sourced from GPIO, the CBI cache only needs to accomondate
  * BOARD_VERSION and SKU_ID
  */
-#define CBI_IMAGE_SIZE		(sizeof(struct cbi_header) +  (2 * \
-				(sizeof(struct cbi_data) + sizeof(uint32_t))))
+#define CBI_IMAGE_SIZE               \
+	(sizeof(struct cbi_header) + \
+	 (2 * (sizeof(struct cbi_data) + sizeof(uint32_t))))
 #else
-#define CBI_IMAGE_SIZE		256
+#define CBI_IMAGE_SIZE 256
 #endif
 
-static const uint8_t cbi_magic[] = { 0x43, 0x42, 0x49 };  /* 'C' 'B' 'I' */
+static const uint8_t cbi_magic[] = { 0x43, 0x42, 0x49 }; /* 'C' 'B' 'I' */
 
 struct cbi_header {
 	uint8_t magic[3];
@@ -47,9 +48,9 @@ struct cbi_header {
 } __attribute__((packed));
 
 struct cbi_data {
-	uint8_t tag;		/* enum cbi_data_tag */
-	uint8_t size;		/* size of value[] */
-	uint8_t value[];	/* data value */
+	uint8_t tag; /* enum cbi_data_tag */
+	uint8_t size; /* size of value[] */
+	uint8_t value[]; /* data value */
 } __attribute__((packed));
 
 enum cbi_cache_status {
@@ -98,6 +99,7 @@ int cbi_get_fw_config(uint32_t *fw_config);
 int cbi_get_pcb_supplier(uint32_t *pcb_supplier);
 int cbi_get_ssfc(uint32_t *ssfc);
 int cbi_get_rework_id(uint64_t *id);
+int cbi_get_factory_calibration_data(uint32_t *calibration_data);
 
 /**
  * Get data from CBI store
@@ -143,8 +145,8 @@ uint8_t cbi_crc8(const struct cbi_header *h);
  * @return	Address of the byte following the stored data in the
  * 		destination buffer
  */
-uint8_t *cbi_set_data(uint8_t *p, enum cbi_data_tag tag,
-		      const void *buf, int size);
+uint8_t *cbi_set_data(uint8_t *p, enum cbi_data_tag tag, const void *buf,
+		      int size);
 
 /**
  * Store string data in memory in CBI data format.
diff --git a/include/cros_version.h b/include/cros_version.h
index 47fa8d1774..8e3429773a 100644
--- a/include/cros_version.h
+++ b/include/cros_version.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,8 +14,8 @@
 #define CROS_EC_IMAGE_DATA_COOKIE1 0xce778899
 #define CROS_EC_IMAGE_DATA_COOKIE2 0xceaabbdd
 #define CROS_EC_IMAGE_DATA_COOKIE3 0xceeeff00
-#define CROS_EC_IMAGE_DATA_COOKIE3_MASK		GENMASK(31, 8)
-#define CROS_EC_IMAGE_DATA_COOKIE3_VERSION	GENMASK(7, 0)
+#define CROS_EC_IMAGE_DATA_COOKIE3_MASK GENMASK(31, 8)
+#define CROS_EC_IMAGE_DATA_COOKIE3_VERSION GENMASK(7, 0)
 
 #define CROS_FWID_MISSING_STR "CROS_FWID_MISSING"
 
@@ -40,4 +40,4 @@ extern const void *__image_size;
  * @return Number of commits in integer or 0 on error
  */
 int ver_get_num_commits(enum ec_image copy);
-#endif  /* __CROS_EC_VERSION_H */
+#endif /* __CROS_EC_VERSION_H */
diff --git a/include/crypto_api.h b/include/crypto_api.h
index 8a8ccacf99..c6374ebee4 100644
--- a/include/crypto_api.h
+++ b/include/crypto_api.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,8 +26,8 @@ extern "C" {
  *		    value exceeds SHA1 size (20 bytes), the rest of the
  *		    hash is filled up with zeros.
  */
-void app_compute_hash(uint8_t *p_buf, size_t num_bytes,
-		      uint8_t *p_hash, size_t hash_len);
+void app_compute_hash(uint8_t *p_buf, size_t num_bytes, uint8_t *p_hash,
+		      size_t hash_len);
 
 #define CIPHER_SALT_SIZE 16
 
diff --git a/include/device_event.h b/include/device_event.h
index 7a6403e51d..7a9992b0df 100644
--- a/include/device_event.h
+++ b/include/device_event.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -50,4 +50,4 @@ static inline void device_set_single_event(int event)
  */
 void device_enable_event(enum ec_device_event event);
 
-#endif  /* __CROS_EC_DEVICE_EVENT_H */
+#endif /* __CROS_EC_DEVICE_EVENT_H */
diff --git a/include/device_state.h b/include/device_state.h
index e7894ba998..7df80b374d 100644
--- a/include/device_state.h
+++ b/include/device_state.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -84,4 +84,4 @@ int device_set_state(enum device_type device, enum device_state state);
  */
 void board_update_device_state(enum device_type device);
 
-#endif  /* __CROS_DEVICE_STATE_H */
+#endif /* __CROS_DEVICE_STATE_H */
diff --git a/include/display_7seg.h b/include/display_7seg.h
index 4369502672..976d496ccb 100644
--- a/include/display_7seg.h
+++ b/include/display_7seg.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,9 +9,9 @@
 #define __CROS_EC_DISPLAY_7SEG_H
 
 enum seven_seg_module_display {
-	SEVEN_SEG_CONSOLE_DISPLAY,	/* Console data */
-	SEVEN_SEG_EC_DISPLAY,		/* power state */
-	SEVEN_SEG_PORT80_DISPLAY,	/* port80 data */
+	SEVEN_SEG_CONSOLE_DISPLAY, /* Console data */
+	SEVEN_SEG_EC_DISPLAY, /* power state */
+	SEVEN_SEG_PORT80_DISPLAY, /* port80 data */
 };
 
 /**
@@ -23,4 +23,4 @@ enum seven_seg_module_display {
  */
 int display_7seg_write(enum seven_seg_module_display module, uint16_t data);
 
-#endif  /* __CROS_EC_DISPLAY_7SEG_H */
+#endif /* __CROS_EC_DISPLAY_7SEG_H */
diff --git a/include/dma.h b/include/dma.h
index 1687b5f899..f35826a132 100644
--- a/include/dma.h
+++ b/include/dma.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -17,14 +17,14 @@
 
 /* DMA channel options */
 struct dma_option {
-	enum dma_channel channel;	/* DMA channel */
-	void *periph;		/* Pointer to peripheral data register */
-	unsigned flags;		/* DMA flags for the control register. Normally
-				   used to select memory size. */
+	enum dma_channel channel; /* DMA channel */
+	void *periph; /* Pointer to peripheral data register */
+	unsigned flags; /* DMA flags for the control register. Normally
+			   used to select memory size. */
 };
 
-#define DMA_POLLING_INTERVAL_US	100	/* us */
-#define DMA_TRANSFER_TIMEOUT_US	(100 * MSEC) /* us */
+#define DMA_POLLING_INTERVAL_US 100 /* us */
+#define DMA_TRANSFER_TIMEOUT_US (100 * MSEC) /* us */
 
 /**
  * Get a pointer to a DMA channel.
@@ -117,7 +117,7 @@ void dma_dump(enum dma_channel channel);
  * Testing: Test that DMA works correctly for memory to memory transfers
  */
 void dma_test(enum dma_channel channel);
-#endif  /* CONFIG_DMA_HELP */
+#endif /* CONFIG_DMA_HELP */
 
 /**
  * Clear the DMA interrupt/event flags for a given channel
diff --git a/include/dps.h b/include/dps.h
index 151c6b3f09..0cb2a9455b 100644
--- a/include/dps.h
+++ b/include/dps.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -68,4 +68,14 @@ bool dps_is_enabled(void);
  */
 void dps_update_stabilized_time(int port);
 
+#ifdef TEST_BUILD
+__test_only void dps_enable(bool en);
+__test_only int dps_init(void);
+__test_only struct dps_config_t *dps_get_config(void);
+__test_only bool dps_is_fake_enabled(void);
+__test_only int dps_get_fake_mv(void);
+__test_only int dps_get_fake_ma(void);
+__test_only int *dps_get_debug_level(void);
+#endif
+
 #endif /* __CROS_EC_DPS__H */
diff --git a/include/dptf.h b/include/dptf.h
index c34e8ea47a..b71b4cf5c0 100644
--- a/include/dptf.h
+++ b/include/dptf.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,10 +27,10 @@ int dptf_get_fan_duty_target(void);
 /**
  * Set/enable the thresholds.
  */
-void dptf_set_temp_threshold(int sensor_id,	/* zero-based sensor index */
-			     int temp,		/* in degrees K */
-			     int idx,		/* which threshold (0 or 1) */
-			     int enable);	/* true = on, false = off */
+void dptf_set_temp_threshold(int sensor_id, /* zero-based sensor index */
+			     int temp, /* in degrees K */
+			     int idx, /* which threshold (0 or 1) */
+			     int enable); /* true = on, false = off */
 
 /**
  * Return the ID of a temp sensor that has crossed its threshold since the last
@@ -48,4 +48,4 @@ void dptf_set_charging_current_limit(int ma);
  */
 int dptf_get_charging_current_limit(void);
 
-#endif	/* __CROS_EC_DPTF_H */
+#endif /* __CROS_EC_DPTF_H */
diff --git a/include/driver/accel_bma2x2.h b/include/driver/accel_bma2x2.h
index 3a46c7c050..c6be3b0c87 100644
--- a/include/driver/accel_bma2x2.h
+++ b/include/driver/accel_bma2x2.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,144 +12,143 @@
 
 /*** Chip-specific registers ***/
 /* REGISTER ADDRESS DEFINITIONS */
-#define BMA2x2_EEP_OFFSET			0x16
-#define BMA2x2_IMAGE_BASE			0x38
-#define BMA2x2_IMAGE_LEN			22
-#define BMA2x2_CHIP_ID_ADDR			0x00
-#define BMA255_CHIP_ID_MAJOR			0xfa
+#define BMA2x2_EEP_OFFSET 0x16
+#define BMA2x2_IMAGE_BASE 0x38
+#define BMA2x2_IMAGE_LEN 22
+#define BMA2x2_CHIP_ID_ADDR 0x00
+#define BMA255_CHIP_ID_MAJOR 0xfa
 
 /* DATA ADDRESS DEFINITIONS */
-#define BMA2x2_X_AXIS_LSB_ADDR			0x02
-#define BMA2x2_X_AXIS_MSB_ADDR			0x03
-#define BMA2x2_Y_AXIS_LSB_ADDR			0x04
-#define BMA2x2_Y_AXIS_MSB_ADDR			0x05
-#define BMA2x2_Z_AXIS_LSB_ADDR			0x06
-#define BMA2x2_Z_AXIS_MSB_ADDR			0x07
-#define BMA2x2_TEMP_ADDR			0x08
+#define BMA2x2_X_AXIS_LSB_ADDR 0x02
+#define BMA2x2_X_AXIS_MSB_ADDR 0x03
+#define BMA2x2_Y_AXIS_LSB_ADDR 0x04
+#define BMA2x2_Y_AXIS_MSB_ADDR 0x05
+#define BMA2x2_Z_AXIS_LSB_ADDR 0x06
+#define BMA2x2_Z_AXIS_MSB_ADDR 0x07
+#define BMA2x2_TEMP_ADDR 0x08
 
-#define BMA2x2_AXIS_LSB_NEW_DATA		0x01
+#define BMA2x2_AXIS_LSB_NEW_DATA 0x01
 
 /* STATUS ADDRESS DEFINITIONS */
-#define BMA2x2_STAT1_ADDR			0x09
-#define BMA2x2_STAT2_ADDR			0x0A
-#define BMA2x2_STAT_TAP_SLOPE_ADDR		0x0B
-#define BMA2x2_STAT_ORIENT_HIGH_ADDR		0x0C
-#define BMA2x2_STAT_FIFO_ADDR			0x0E
-#define BMA2x2_RANGE_SELECT_ADDR		0x0F
-#define BMA2x2_RANGE_SELECT_MSK			0x0F
-#define BMA2x2_RANGE_2G				3
-#define BMA2x2_RANGE_4G				5
-#define BMA2x2_RANGE_8G				8
-#define BMA2x2_RANGE_16G			12
-
-#define BMA2x2_RANGE_TO_REG(_range) \
+#define BMA2x2_STAT1_ADDR 0x09
+#define BMA2x2_STAT2_ADDR 0x0A
+#define BMA2x2_STAT_TAP_SLOPE_ADDR 0x0B
+#define BMA2x2_STAT_ORIENT_HIGH_ADDR 0x0C
+#define BMA2x2_STAT_FIFO_ADDR 0x0E
+#define BMA2x2_RANGE_SELECT_ADDR 0x0F
+#define BMA2x2_RANGE_SELECT_MSK 0x0F
+#define BMA2x2_RANGE_2G 3
+#define BMA2x2_RANGE_4G 5
+#define BMA2x2_RANGE_8G 8
+#define BMA2x2_RANGE_16G 12
+
+#define BMA2x2_RANGE_TO_REG(_range)                            \
 	((_range) < 8 ? BMA2x2_RANGE_2G + ((_range) / 4) * 2 : \
 			BMA2x2_RANGE_8G + ((_range) / 16) * 4)
 
-#define BMA2x2_REG_TO_RANGE(_reg) \
-	((_reg) < BMA2x2_RANGE_8G ? 2 + (_reg) - BMA2x2_RANGE_2G : \
-				    8 + ((_reg) - BMA2x2_RANGE_8G) * 2)
-
-#define BMA2x2_BW_SELECT_ADDR			0x10
-#define BMA2x2_BW_MSK				0x1F
-#define BMA2x2_BW_7_81HZ			0x08 /* LowPass   7.8125HZ */
-#define BMA2x2_BW_15_63HZ			0x09 /* LowPass  15.625HZ */
-#define BMA2x2_BW_31_25HZ			0x0A /* LowPass  31.25HZ */
-#define BMA2x2_BW_62_50HZ			0x0B /* LowPass  62.50HZ */
-#define BMA2x2_BW_125HZ				0x0C /* LowPass 125HZ */
-#define BMA2x2_BW_250HZ				0x0D /* LowPass 250HZ */
-#define BMA2x2_BW_500HZ				0x0E /* LowPass 500HZ */
-#define BMA2x2_BW_1000HZ			0x0F /* LowPass 1000HZ */
+#define BMA2x2_REG_TO_RANGE(_reg)                                \
+	((_reg) < BMA2x2_RANGE_8G ? 2 + (_reg)-BMA2x2_RANGE_2G : \
+				    8 + ((_reg)-BMA2x2_RANGE_8G) * 2)
+
+#define BMA2x2_BW_SELECT_ADDR 0x10
+#define BMA2x2_BW_MSK 0x1F
+#define BMA2x2_BW_7_81HZ 0x08 /* LowPass   7.8125HZ */
+#define BMA2x2_BW_15_63HZ 0x09 /* LowPass  15.625HZ */
+#define BMA2x2_BW_31_25HZ 0x0A /* LowPass  31.25HZ */
+#define BMA2x2_BW_62_50HZ 0x0B /* LowPass  62.50HZ */
+#define BMA2x2_BW_125HZ 0x0C /* LowPass 125HZ */
+#define BMA2x2_BW_250HZ 0x0D /* LowPass 250HZ */
+#define BMA2x2_BW_500HZ 0x0E /* LowPass 500HZ */
+#define BMA2x2_BW_1000HZ 0x0F /* LowPass 1000HZ */
 
 /* Do not use BW lower than 7813, because __fls cannot be call for 0 */
-#define BMA2x2_BW_TO_REG(_bw) \
-	((_bw) < 125000 ? \
-	 BMA2x2_BW_7_81HZ + __fls(((_bw) * 10) / 78125) : \
-	 BMA2x2_BW_125HZ + __fls((_bw) / 125000))
-
-#define  BMA2x2_REG_TO_BW(_reg) \
-	((_reg) < BMA2x2_BW_125HZ ? \
-	 (78125 << ((_reg) - BMA2x2_BW_7_81HZ)) / 10 : \
-	 125000 << ((_reg) - BMA2x2_BW_125HZ))
-
-#define BMA2x2_MODE_CTRL_ADDR			0x11
-#define BMA2x2_LOW_NOISE_CTRL_ADDR		0x12
-#define BMA2x2_DATA_CTRL_ADDR			0x13
-#define BMA2x2_DATA_HIGH_BW			0x80
-#define BMA2x2_DATA_SHADOW_DIS			0x40
-#define BMA2x2_RST_ADDR				0x14
-#define BMA2x2_CMD_SOFT_RESET			0xb6
+#define BMA2x2_BW_TO_REG(_bw)                                            \
+	((_bw) < 125000 ? BMA2x2_BW_7_81HZ + __fls(((_bw)*10) / 78125) : \
+			  BMA2x2_BW_125HZ + __fls((_bw) / 125000))
+
+#define BMA2x2_REG_TO_BW(_reg)                               \
+	((_reg) < BMA2x2_BW_125HZ ?                          \
+		 (78125 << ((_reg)-BMA2x2_BW_7_81HZ)) / 10 : \
+		 125000 << ((_reg)-BMA2x2_BW_125HZ))
+
+#define BMA2x2_MODE_CTRL_ADDR 0x11
+#define BMA2x2_LOW_NOISE_CTRL_ADDR 0x12
+#define BMA2x2_DATA_CTRL_ADDR 0x13
+#define BMA2x2_DATA_HIGH_BW 0x80
+#define BMA2x2_DATA_SHADOW_DIS 0x40
+#define BMA2x2_RST_ADDR 0x14
+#define BMA2x2_CMD_SOFT_RESET 0xb6
 
 /* INTERRUPT ADDRESS DEFINITIONS */
-#define BMA2x2_INTR_ENABLE1_ADDR		0x16
-#define BMA2x2_INTR_ENABLE2_ADDR		0x17
-#define BMA2x2_INTR_SLOW_NO_MOTION_ADDR		0x18
-#define BMA2x2_INTR1_PAD_SELECT_ADDR		0x19
-#define BMA2x2_INTR_DATA_SELECT_ADDR		0x1A
-#define BMA2x2_INTR2_PAD_SELECT_ADDR		0x1B
-#define BMA2x2_INTR_SOURCE_ADDR			0x1E
-#define BMA2x2_INTR_SET_ADDR			0x20
-#define BMA2x2_INTR_CTRL_ADDR			0x21
-#define BMA2x2_INTR_CTRL_RST_INT		0x80
+#define BMA2x2_INTR_ENABLE1_ADDR 0x16
+#define BMA2x2_INTR_ENABLE2_ADDR 0x17
+#define BMA2x2_INTR_SLOW_NO_MOTION_ADDR 0x18
+#define BMA2x2_INTR1_PAD_SELECT_ADDR 0x19
+#define BMA2x2_INTR_DATA_SELECT_ADDR 0x1A
+#define BMA2x2_INTR2_PAD_SELECT_ADDR 0x1B
+#define BMA2x2_INTR_SOURCE_ADDR 0x1E
+#define BMA2x2_INTR_SET_ADDR 0x20
+#define BMA2x2_INTR_CTRL_ADDR 0x21
+#define BMA2x2_INTR_CTRL_RST_INT 0x80
 
 /* FEATURE ADDRESS DEFINITIONS */
-#define BMA2x2_LOW_DURN_ADDR			0x22
-#define BMA2x2_LOW_THRES_ADDR			0x23
-#define BMA2x2_LOW_HIGH_HYST_ADDR		0x24
-#define BMA2x2_HIGH_DURN_ADDR			0x25
-#define BMA2x2_HIGH_THRES_ADDR			0x26
-#define BMA2x2_SLOPE_DURN_ADDR			0x27
-#define BMA2x2_SLOPE_THRES_ADDR			0x28
-#define BMA2x2_SLOW_NO_MOTION_THRES_ADDR	0x29
-#define BMA2x2_TAP_PARAM_ADDR			0x2A
-#define BMA2x2_TAP_THRES_ADDR			0x2B
-#define BMA2x2_ORIENT_PARAM_ADDR		0x2C
-#define BMA2x2_THETA_BLOCK_ADDR			0x2D
-#define BMA2x2_THETA_FLAT_ADDR			0x2E
-#define BMA2x2_FLAT_HOLD_TIME_ADDR		0x2F
-#define BMA2x2_SELFTEST_ADDR			0x32
-#define BMA2x2_EEPROM_CTRL_ADDR			0x33
-#define BMA2x2_EEPROM_REMAIN_OFF		4
-#define BMA2x2_EEPROM_REMAIN_MSK		0xF0
-#define BMA2x2_EEPROM_LOAD			0x08
-#define BMA2x2_EEPROM_RDY			0x04
-#define BMA2x2_EEPROM_PROG			0x02
-#define BMA2x2_EEPROM_PROG_EN			0x01
-#define BMA2x2_SERIAL_CTRL_ADDR			0x34
+#define BMA2x2_LOW_DURN_ADDR 0x22
+#define BMA2x2_LOW_THRES_ADDR 0x23
+#define BMA2x2_LOW_HIGH_HYST_ADDR 0x24
+#define BMA2x2_HIGH_DURN_ADDR 0x25
+#define BMA2x2_HIGH_THRES_ADDR 0x26
+#define BMA2x2_SLOPE_DURN_ADDR 0x27
+#define BMA2x2_SLOPE_THRES_ADDR 0x28
+#define BMA2x2_SLOW_NO_MOTION_THRES_ADDR 0x29
+#define BMA2x2_TAP_PARAM_ADDR 0x2A
+#define BMA2x2_TAP_THRES_ADDR 0x2B
+#define BMA2x2_ORIENT_PARAM_ADDR 0x2C
+#define BMA2x2_THETA_BLOCK_ADDR 0x2D
+#define BMA2x2_THETA_FLAT_ADDR 0x2E
+#define BMA2x2_FLAT_HOLD_TIME_ADDR 0x2F
+#define BMA2x2_SELFTEST_ADDR 0x32
+#define BMA2x2_EEPROM_CTRL_ADDR 0x33
+#define BMA2x2_EEPROM_REMAIN_OFF 4
+#define BMA2x2_EEPROM_REMAIN_MSK 0xF0
+#define BMA2x2_EEPROM_LOAD 0x08
+#define BMA2x2_EEPROM_RDY 0x04
+#define BMA2x2_EEPROM_PROG 0x02
+#define BMA2x2_EEPROM_PROG_EN 0x01
+#define BMA2x2_SERIAL_CTRL_ADDR 0x34
 
 /* OFFSET ADDRESS DEFINITIONS */
-#define BMA2x2_OFFSET_CTRL_ADDR			0x36
-#define BMA2x2_OFFSET_RESET			0x80
-#define BMA2x2_OFFSET_TRIGGER_OFF		5
-#define BMA2x2_OFFSET_TRIGGER_MASK	(0x3 << BMA2x2_OFFSET_TRIGGER_OFF)
-#define BMA2x2_OFFSET_CAL_READY			0x10
-#define BMA2x2_OFFSET_CAL_SLOW_X		0x04
-#define BMA2x2_OFFSET_CAL_SLOW_Y		0x02
-#define BMA2x2_OFFSET_CAL_SLOW_Z		0x01
-
-#define BMA2x2_OFC_SETTING_ADDR			0x37
-#define BMA2x2_OFC_TARGET_AXIS_OFF		1
-#define BMA2x2_OFC_TARGET_AXIS_LEN		2
+#define BMA2x2_OFFSET_CTRL_ADDR 0x36
+#define BMA2x2_OFFSET_RESET 0x80
+#define BMA2x2_OFFSET_TRIGGER_OFF 5
+#define BMA2x2_OFFSET_TRIGGER_MASK (0x3 << BMA2x2_OFFSET_TRIGGER_OFF)
+#define BMA2x2_OFFSET_CAL_READY 0x10
+#define BMA2x2_OFFSET_CAL_SLOW_X 0x04
+#define BMA2x2_OFFSET_CAL_SLOW_Y 0x02
+#define BMA2x2_OFFSET_CAL_SLOW_Z 0x01
+
+#define BMA2x2_OFC_SETTING_ADDR 0x37
+#define BMA2x2_OFC_TARGET_AXIS_OFF 1
+#define BMA2x2_OFC_TARGET_AXIS_LEN 2
 #define BMA2x2_OFC_TARGET_AXIS(_axis) \
 	(BMA2x2_OFC_TARGET_AXIS_LEN * (_axis) + BMA2x2_OFC_TARGET_AXIS_OFF)
-#define BMA2x2_OFC_TARGET_0G			0
-#define BMA2x2_OFC_TARGET_PLUS_1G		1
-#define BMA2x2_OFC_TARGET_MINUS_1G		2
+#define BMA2x2_OFC_TARGET_0G 0
+#define BMA2x2_OFC_TARGET_PLUS_1G 1
+#define BMA2x2_OFC_TARGET_MINUS_1G 2
 
-#define BMA2x2_OFFSET_X_AXIS_ADDR		0x38
-#define BMA2x2_OFFSET_Y_AXIS_ADDR		0x39
-#define BMA2x2_OFFSET_Z_AXIS_ADDR		0x3A
+#define BMA2x2_OFFSET_X_AXIS_ADDR 0x38
+#define BMA2x2_OFFSET_Y_AXIS_ADDR 0x39
+#define BMA2x2_OFFSET_Z_AXIS_ADDR 0x3A
 
 /* GP ADDRESS DEFINITIONS */
-#define BMA2x2_GP0_ADDR				0x3B
-#define BMA2x2_GP1_ADDR				0x3C
+#define BMA2x2_GP0_ADDR 0x3B
+#define BMA2x2_GP1_ADDR 0x3C
 
 /* FIFO ADDRESS DEFINITIONS */
-#define BMA2x2_FIFO_MODE_ADDR			0x3E
-#define BMA2x2_FIFO_DATA_OUTPUT_ADDR		0x3F
-#define BMA2x2_FIFO_WML_TRIG			0x30
+#define BMA2x2_FIFO_MODE_ADDR 0x3E
+#define BMA2x2_FIFO_DATA_OUTPUT_ADDR 0x3F
+#define BMA2x2_FIFO_WML_TRIG 0x30
 
 /* Sensor resolution in number of bits. This sensor has fixed resolution. */
-#define BMA2x2_RESOLUTION			12
+#define BMA2x2_RESOLUTION 12
 
 #endif /* __CROS_EC_ACCEL_BMA2x2_H */
diff --git a/include/driver/accel_bma2x2_public.h b/include/driver/accel_bma2x2_public.h
index 731fcebbc9..04d7a33e4c 100644
--- a/include/driver/accel_bma2x2_public.h
+++ b/include/driver/accel_bma2x2_public.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,27 +14,27 @@ extern const struct accelgyro_drv bma2x2_accel_drv;
 
 /* I2C ADDRESS DEFINITIONS    */
 /* The following definition of I2C address is used for the following sensors
-* BMA253
-* BMA255
-* BMA355
-* BMA280
-* BMA282
-* BMA223
-* BMA254
-* BMA284
-* BMA250E
-* BMA222E
-*/
-#define BMA2x2_I2C_ADDR1_FLAGS              0x18
-#define BMA2x2_I2C_ADDR2_FLAGS              0x19
+ * BMA253
+ * BMA255
+ * BMA355
+ * BMA280
+ * BMA282
+ * BMA223
+ * BMA254
+ * BMA284
+ * BMA250E
+ * BMA222E
+ */
+#define BMA2x2_I2C_ADDR1_FLAGS 0x18
+#define BMA2x2_I2C_ADDR2_FLAGS 0x19
 
 /* The following definition of I2C address is used for the following sensors
-* BMC150
-* BMC056
-* BMC156
-*/
-#define BMA2x2_I2C_ADDR3_FLAGS              0x10
-#define BMA2x2_I2C_ADDR4_FLAGS              0x11
+ * BMC150
+ * BMC056
+ * BMC156
+ */
+#define BMA2x2_I2C_ADDR3_FLAGS 0x10
+#define BMA2x2_I2C_ADDR4_FLAGS 0x11
 
 /*
  * Min and Max sampling frequency in mHz.
@@ -43,8 +43,7 @@ extern const struct accelgyro_drv bma2x2_accel_drv;
  * (see CONFIG_MOTION_MIN_SENSE_WAIT_TIME), we may read too early when
  * other sensors are active.
  */
-#define BMA255_ACCEL_MIN_FREQ           7810
-#define BMA255_ACCEL_MAX_FREQ \
-	MOTION_MAX_SENSOR_FREQUENCY(125000, 15625)
+#define BMA255_ACCEL_MIN_FREQ 7810
+#define BMA255_ACCEL_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(125000, 15625)
 
 #endif /* CROS_EC_DRIVER_ACCEL_BMA2x2_PUBLIC_H */
diff --git a/include/driver/accel_lis2dw12_public.h b/include/driver/accel_lis2dw12_public.h
index 751df15f86..5596e6ba6a 100644
--- a/include/driver/accel_lis2dw12_public.h
+++ b/include/driver/accel_lis2dw12_public.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,18 +17,18 @@ extern const struct accelgyro_drv lis2dw12_drv;
  * 7-bit address is 011000Xb. Where 'X' is determined
  * by the voltage on the ADDR pin.
  */
-#define LIS2DW12_ADDR0			0x18
-#define LIS2DW12_ADDR1			0x19
+#define LIS2DW12_ADDR0 0x18
+#define LIS2DW12_ADDR1 0x19
 
-#define LIS2DWL_ADDR0_FLAGS		0x18
-#define LIS2DWL_ADDR1_FLAGS		0x19
+#define LIS2DWL_ADDR0_FLAGS 0x18
+#define LIS2DWL_ADDR1_FLAGS 0x19
 
-#define LIS2DW12_EN_BIT			0x01
-#define LIS2DW12_DIS_BIT		0x00
+#define LIS2DW12_EN_BIT 0x01
+#define LIS2DW12_DIS_BIT 0x00
 
 /* Absolute Acc rate. */
-#define LIS2DW12_ODR_MIN_VAL		12500
-#define LIS2DW12_ODR_MAX_VAL		\
+#define LIS2DW12_ODR_MIN_VAL 12500
+#define LIS2DW12_ODR_MAX_VAL \
 	MOTION_MAX_SENSOR_FREQUENCY(1600000, LIS2DW12_ODR_MIN_VAL)
 
 void lis2dw12_interrupt(enum gpio_signal signal);
diff --git a/include/driver/accelgyro_bmi160.h b/include/driver/accelgyro_bmi160.h
index bd5637c2ba..8c6310e65b 100644
--- a/include/driver/accelgyro_bmi160.h
+++ b/include/driver/accelgyro_bmi160.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,253 +12,251 @@
 #include "driver/accelgyro_bmi160_public.h"
 #include "mag_bmm150.h"
 
-#define BMI160_CHIP_ID           0x00
-#define BMI160_CHIP_ID_MAJOR     0xd1
-#define BMI168_CHIP_ID_MAJOR     0xd2
+#define BMI160_CHIP_ID 0x00
+#define BMI160_CHIP_ID_MAJOR 0xd1
+#define BMI168_CHIP_ID_MAJOR 0xd2
 
-#define BMI160_SPEC_ACC_STARTUP_TIME_MS     10
-#define BMI160_SPEC_GYR_STARTUP_TIME_MS     80
-#define BMI160_SPEC_MAG_STARTUP_TIME_MS     60
+#define BMI160_SPEC_ACC_STARTUP_TIME_MS 10
+#define BMI160_SPEC_GYR_STARTUP_TIME_MS 80
+#define BMI160_SPEC_MAG_STARTUP_TIME_MS 60
 
-
-#define BMI160_ERR_REG         0x02
-#define BMI160_PMU_STATUS      0x03
-#define BMI160_PMU_MAG_OFFSET               0
-#define BMI160_PMU_GYR_OFFSET               2
-#define BMI160_PMU_ACC_OFFSET               4
+#define BMI160_ERR_REG 0x02
+#define BMI160_PMU_STATUS 0x03
+#define BMI160_PMU_MAG_OFFSET 0
+#define BMI160_PMU_GYR_OFFSET 2
+#define BMI160_PMU_ACC_OFFSET 4
 #define BMI160_PMU_SENSOR_STATUS(_sensor_type, _val) \
 	(((_val) >> (4 - 2 * (_sensor_type))) & 0x3)
-#define BMI160_PMU_SUSPEND                  0
-#define BMI160_PMU_NORMAL                   1
-#define BMI160_PMU_LOW_POWER                2
-#define BMI160_PMU_FAST_STARTUP             3
-
-#define BMI160_MAG_X_L_G       0x04
-#define BMI160_MAG_X_H_G       0x05
-#define BMI160_MAG_Y_L_G       0x06
-#define BMI160_MAG_Y_H_G       0x07
-#define BMI160_MAG_Z_L_G       0x08
-#define BMI160_MAG_Z_H_G       0x09
-#define BMI160_RHALL_L_G       0x0a
-#define BMI160_RHALL_H_G       0x0b
-#define BMI160_GYR_X_L_G       0x0c
-#define BMI160_GYR_X_H_G       0x0d
-#define BMI160_GYR_Y_L_G       0x0e
-#define BMI160_GYR_Y_H_G       0x0f
-#define BMI160_GYR_Z_L_G       0x10
-#define BMI160_GYR_Z_H_G       0x11
-#define BMI160_ACC_X_L_G       0x12
-#define BMI160_ACC_X_H_G       0x13
-#define BMI160_ACC_Y_L_G       0x14
-#define BMI160_ACC_Y_H_G       0x15
-#define BMI160_ACC_Z_L_G       0x16
-#define BMI160_ACC_Z_H_G       0x17
-
-#define BMI160_SENSORTIME_0    0x18
-#define BMI160_SENSORTIME_1    0x19
-#define BMI160_SENSORTIME_2    0x1a
-
-#define BMI160_STATUS          0x1b
-#define BMI160_POR_DETECTED        BIT(0)
-#define BMI160_GYR_SLF_TST         BIT(1)
-#define BMI160_MAG_MAN_OP          BIT(2)
-#define BMI160_FOC_RDY             BIT(3)
-#define BMI160_NVM_RDY             BIT(4)
-#define BMI160_DRDY_MAG            BIT(5)
-#define BMI160_DRDY_GYR            BIT(6)
-#define BMI160_DRDY_ACC            BIT(7)
-#define BMI160_DRDY_OFF(_sensor)   (7 - (_sensor))
-#define BMI160_DRDY_MASK(_sensor)  (1 << BMI160_DRDY_OFF(_sensor))
+#define BMI160_PMU_SUSPEND 0
+#define BMI160_PMU_NORMAL 1
+#define BMI160_PMU_LOW_POWER 2
+#define BMI160_PMU_FAST_STARTUP 3
+
+#define BMI160_MAG_X_L_G 0x04
+#define BMI160_MAG_X_H_G 0x05
+#define BMI160_MAG_Y_L_G 0x06
+#define BMI160_MAG_Y_H_G 0x07
+#define BMI160_MAG_Z_L_G 0x08
+#define BMI160_MAG_Z_H_G 0x09
+#define BMI160_RHALL_L_G 0x0a
+#define BMI160_RHALL_H_G 0x0b
+#define BMI160_GYR_X_L_G 0x0c
+#define BMI160_GYR_X_H_G 0x0d
+#define BMI160_GYR_Y_L_G 0x0e
+#define BMI160_GYR_Y_H_G 0x0f
+#define BMI160_GYR_Z_L_G 0x10
+#define BMI160_GYR_Z_H_G 0x11
+#define BMI160_ACC_X_L_G 0x12
+#define BMI160_ACC_X_H_G 0x13
+#define BMI160_ACC_Y_L_G 0x14
+#define BMI160_ACC_Y_H_G 0x15
+#define BMI160_ACC_Z_L_G 0x16
+#define BMI160_ACC_Z_H_G 0x17
+
+#define BMI160_SENSORTIME_0 0x18
+#define BMI160_SENSORTIME_1 0x19
+#define BMI160_SENSORTIME_2 0x1a
+
+#define BMI160_STATUS 0x1b
+#define BMI160_POR_DETECTED BIT(0)
+#define BMI160_GYR_SLF_TST BIT(1)
+#define BMI160_MAG_MAN_OP BIT(2)
+#define BMI160_FOC_RDY BIT(3)
+#define BMI160_NVM_RDY BIT(4)
+#define BMI160_DRDY_MAG BIT(5)
+#define BMI160_DRDY_GYR BIT(6)
+#define BMI160_DRDY_ACC BIT(7)
+#define BMI160_DRDY_OFF(_sensor) (7 - (_sensor))
+#define BMI160_DRDY_MASK(_sensor) (1 << BMI160_DRDY_OFF(_sensor))
 
 /* first 2 bytes are the interrupt reasons, next 2 some qualifier */
-#define BMI160_INT_STATUS_0    0x1c
-#define BMI160_STEP_INT            BIT(0)
-#define BMI160_SIGMOT_INT          BIT(1)
-#define BMI160_ANYM_INT            BIT(2)
-#define BMI160_PMU_TRIGGER_INT     BIT(3)
-#define BMI160_D_TAP_INT           BIT(4)
-#define BMI160_S_TAP_INT           BIT(5)
-#define BMI160_ORIENT_INT          BIT(6)
-#define BMI160_FLAT_INT            BIT(7)
-#define BMI160_ORIENT_XY_MASK	   0x30
-#define BMI160_ORIENT_PORTRAIT		(0 << 4)
-#define BMI160_ORIENT_PORTRAIT_INVERT	BIT(4)
-#define BMI160_ORIENT_LANDSCAPE		(2 << 4)
-#define BMI160_ORIENT_LANDSCAPE_INVERT	(3 << 4)
-
-
-#define BMI160_INT_STATUS_1    0x1d
-#define BMI160_HIGHG_INT           (1 << (2 + 8))
-#define BMI160_LOWG_INT            (1 << (3 + 8))
-#define BMI160_DRDY_INT            (1 << (4 + 8))
-#define BMI160_FFULL_INT           (1 << (5 + 8))
-#define BMI160_FWM_INT             (1 << (6 + 8))
-#define BMI160_NOMO_INT            (1 << (7 + 8))
-
-#define BMI160_INT_MASK            0xFFFF
-
-#define BMI160_INT_STATUS_2    0x1e
-#define BMI160_INT_STATUS_3    0x1f
-#define BMI160_FIRST_X             (1 << (0 + 16))
-#define BMI160_FIRST_Y             (1 << (1 + 16))
-#define BMI160_FIRST_Z             (1 << (2 + 16))
-#define BMI160_SIGN                (1 << (3 + 16))
-#define BMI160_ANYM_OFFSET         0
-#define BMI160_TAP_OFFSET          4
-#define BMI160_HIGH_OFFSET         8
+#define BMI160_INT_STATUS_0 0x1c
+#define BMI160_STEP_INT BIT(0)
+#define BMI160_SIGMOT_INT BIT(1)
+#define BMI160_ANYM_INT BIT(2)
+#define BMI160_PMU_TRIGGER_INT BIT(3)
+#define BMI160_D_TAP_INT BIT(4)
+#define BMI160_S_TAP_INT BIT(5)
+#define BMI160_ORIENT_INT BIT(6)
+#define BMI160_FLAT_INT BIT(7)
+#define BMI160_ORIENT_XY_MASK 0x30
+#define BMI160_ORIENT_PORTRAIT (0 << 4)
+#define BMI160_ORIENT_PORTRAIT_INVERT BIT(4)
+#define BMI160_ORIENT_LANDSCAPE (2 << 4)
+#define BMI160_ORIENT_LANDSCAPE_INVERT (3 << 4)
+
+#define BMI160_INT_STATUS_1 0x1d
+#define BMI160_HIGHG_INT (1 << (2 + 8))
+#define BMI160_LOWG_INT (1 << (3 + 8))
+#define BMI160_DRDY_INT (1 << (4 + 8))
+#define BMI160_FFULL_INT (1 << (5 + 8))
+#define BMI160_FWM_INT (1 << (6 + 8))
+#define BMI160_NOMO_INT (1 << (7 + 8))
+
+#define BMI160_INT_MASK 0xFFFF
+
+#define BMI160_INT_STATUS_2 0x1e
+#define BMI160_INT_STATUS_3 0x1f
+#define BMI160_FIRST_X (1 << (0 + 16))
+#define BMI160_FIRST_Y (1 << (1 + 16))
+#define BMI160_FIRST_Z (1 << (2 + 16))
+#define BMI160_SIGN (1 << (3 + 16))
+#define BMI160_ANYM_OFFSET 0
+#define BMI160_TAP_OFFSET 4
+#define BMI160_HIGH_OFFSET 8
 #define BMI160_INT_INFO(_type, _data) \
-(CONCAT2(BMI160_, _data) << CONCAT3(BMI160_, _type, _OFFSET))
-
-#define BMI160_ORIENT_Z            (1 << (6 + 24))
-#define BMI160_FLAT                (1 << (7 + 24))
-
-#define BMI160_TEMPERATURE_0   0x20
-#define BMI160_TEMPERATURE_1   0x21
-
-
-#define BMI160_FIFO_LENGTH_0   0x22
-#define BMI160_FIFO_LENGTH_1   0x23
-#define BMI160_FIFO_LENGTH_MASK    (BIT(11) - 1)
-#define BMI160_FIFO_DATA       0x24
-
-#define BMI160_ACC_CONF        0x40
-#define BMI160_ACC_BW_OFFSET            4
-#define BMI160_ACC_BW_MASK     (0x7 << BMI160_ACC_BW_OFFSET)
-
-#define BMI160_ACC_RANGE       0x41
-#define BMI160_GSEL_2G         0x03
-#define BMI160_GSEL_4G         0x05
-#define BMI160_GSEL_8G         0x08
-#define BMI160_GSEL_16G        0x0c
-
-#define BMI160_GYR_CONF        0x42
-#define BMI160_GYR_BW_OFFSET   4
-#define BMI160_GYR_BW_MASK     (0x3 << BMI160_GYR_BW_OFFSET)
-
-#define BMI160_GYR_RANGE       0x43
-#define BMI160_DPS_SEL_2000    0x00
-#define BMI160_DPS_SEL_1000    0x01
-#define BMI160_DPS_SEL_500     0x02
-#define BMI160_DPS_SEL_250     0x03
-#define BMI160_DPS_SEL_125     0x04
-
-#define BMI160_MAG_CONF        0x44
-
-#define BMI160_FIFO_DOWNS      0x45
-#define BMI160_FIFO_CONFIG_0   0x46
-#define BMI160_FIFO_CONFIG_1   0x47
-#define BMI160_FIFO_TAG_TIME_EN    BIT(1)
-#define BMI160_FIFO_TAG_INT2_EN    BIT(2)
-#define BMI160_FIFO_TAG_INT1_EN    BIT(3)
-#define BMI160_FIFO_HEADER_EN      BIT(4)
-#define BMI160_FIFO_MAG_EN         BIT(5)
-#define BMI160_FIFO_ACC_EN         BIT(6)
-#define BMI160_FIFO_GYR_EN         BIT(7)
-#define BMI160_FIFO_TARG_INT(_i)  CONCAT3(BMI160_FIFO_TAG_INT, _i, _EN)
-#define BMI160_FIFO_SENSOR_EN(_sensor) \
-	((_sensor) == MOTIONSENSE_TYPE_ACCEL ? BMI160_FIFO_ACC_EN : \
-	  ((_sensor) == MOTIONSENSE_TYPE_GYRO ? BMI160_FIFO_GYR_EN : \
-	   BMI160_FIFO_MAG_EN))
-
-#define BMI160_MAG_IF_0        0x4b
+	(CONCAT2(BMI160_, _data) << CONCAT3(BMI160_, _type, _OFFSET))
+
+#define BMI160_ORIENT_Z (1 << (6 + 24))
+#define BMI160_FLAT (1 << (7 + 24))
+
+#define BMI160_TEMPERATURE_0 0x20
+#define BMI160_TEMPERATURE_1 0x21
+
+#define BMI160_FIFO_LENGTH_0 0x22
+#define BMI160_FIFO_LENGTH_1 0x23
+#define BMI160_FIFO_LENGTH_MASK (BIT(11) - 1)
+#define BMI160_FIFO_DATA 0x24
+
+#define BMI160_ACC_CONF 0x40
+#define BMI160_ACC_BW_OFFSET 4
+#define BMI160_ACC_BW_MASK (0x7 << BMI160_ACC_BW_OFFSET)
+
+#define BMI160_ACC_RANGE 0x41
+#define BMI160_GSEL_2G 0x03
+#define BMI160_GSEL_4G 0x05
+#define BMI160_GSEL_8G 0x08
+#define BMI160_GSEL_16G 0x0c
+
+#define BMI160_GYR_CONF 0x42
+#define BMI160_GYR_BW_OFFSET 4
+#define BMI160_GYR_BW_MASK (0x3 << BMI160_GYR_BW_OFFSET)
+
+#define BMI160_GYR_RANGE 0x43
+#define BMI160_DPS_SEL_2000 0x00
+#define BMI160_DPS_SEL_1000 0x01
+#define BMI160_DPS_SEL_500 0x02
+#define BMI160_DPS_SEL_250 0x03
+#define BMI160_DPS_SEL_125 0x04
+
+#define BMI160_MAG_CONF 0x44
+
+#define BMI160_FIFO_DOWNS 0x45
+#define BMI160_FIFO_CONFIG_0 0x46
+#define BMI160_FIFO_CONFIG_1 0x47
+#define BMI160_FIFO_TAG_TIME_EN BIT(1)
+#define BMI160_FIFO_TAG_INT2_EN BIT(2)
+#define BMI160_FIFO_TAG_INT1_EN BIT(3)
+#define BMI160_FIFO_HEADER_EN BIT(4)
+#define BMI160_FIFO_MAG_EN BIT(5)
+#define BMI160_FIFO_ACC_EN BIT(6)
+#define BMI160_FIFO_GYR_EN BIT(7)
+#define BMI160_FIFO_TARG_INT(_i) CONCAT3(BMI160_FIFO_TAG_INT, _i, _EN)
+#define BMI160_FIFO_SENSOR_EN(_sensor)                                      \
+	((_sensor) == MOTIONSENSE_TYPE_ACCEL ?                              \
+		 BMI160_FIFO_ACC_EN :                                       \
+		 ((_sensor) == MOTIONSENSE_TYPE_GYRO ? BMI160_FIFO_GYR_EN : \
+						       BMI160_FIFO_MAG_EN))
+
+#define BMI160_MAG_IF_0 0x4b
 #define BMI160_MAG_I2C_ADDRESS BMI160_MAG_IF_0
-#define BMI160_MAG_IF_1        0x4c
+#define BMI160_MAG_IF_1 0x4c
 #define BMI160_MAG_I2C_CONTROL BMI160_MAG_IF_1
 #define BMI160_MAG_READ_BURST_MASK 3
-#define BMI160_MAG_READ_BURST_1    0
-#define BMI160_MAG_READ_BURST_2    1
-#define BMI160_MAG_READ_BURST_6    2
-#define BMI160_MAG_READ_BURST_8    3
-#define BMI160_MAG_OFFSET_OFF      3
-#define BMI160_MAG_OFFSET_MASK     (0xf << BMI160_MAG_OFFSET_OFF)
-#define BMI160_MAG_MANUAL_EN       BIT(7)
-
-#define BMI160_MAG_IF_2        0x4d
-#define BMI160_MAG_I2C_READ_ADDR    BMI160_MAG_IF_2
-#define BMI160_MAG_IF_3        0x4e
-#define BMI160_MAG_I2C_WRITE_ADDR   BMI160_MAG_IF_3
-#define BMI160_MAG_IF_4        0x4f
-#define BMI160_MAG_I2C_WRITE_DATA   BMI160_MAG_IF_4
-#define BMI160_MAG_I2C_READ_DATA    BMI160_MAG_X_L_G
-
-#define BMI160_INT_EN_0        0x50
-#define BMI160_INT_ANYMO_X_EN      BIT(0)
-#define BMI160_INT_ANYMO_Y_EN      BIT(1)
-#define BMI160_INT_ANYMO_Z_EN      BIT(2)
-#define BMI160_INT_D_TAP_EN        BIT(4)
-#define BMI160_INT_S_TAP_EN        BIT(5)
-#define BMI160_INT_ORIENT_EN       BIT(6)
-#define BMI160_INT_FLAT_EN         BIT(7)
-#define BMI160_INT_EN_1        0x51
-#define BMI160_INT_HIGHG_X_EN      BIT(0)
-#define BMI160_INT_HIGHG_Y_EN      BIT(1)
-#define BMI160_INT_HIGHG_Z_EN      BIT(2)
-#define BMI160_INT_LOW_EN          BIT(3)
-#define BMI160_INT_DRDY_EN         BIT(4)
-#define BMI160_INT_FFUL_EN         BIT(5)
-#define BMI160_INT_FWM_EN          BIT(6)
-#define BMI160_INT_EN_2        0x52
-#define BMI160_INT_NOMOX_EN        BIT(0)
-#define BMI160_INT_NOMOY_EN        BIT(1)
-#define BMI160_INT_NOMOZ_EN        BIT(2)
-#define BMI160_INT_STEP_DET_EN     BIT(3)
-
-#define BMI160_INT_OUT_CTRL    0x53
-#define BMI160_INT_EDGE_CTRL       BIT(0)
-#define BMI160_INT_LVL_CTRL        BIT(1)
-#define BMI160_INT_OD              BIT(2)
-#define BMI160_INT_OUTPUT_EN       BIT(3)
-#define BMI160_INT1_CTRL_OFFSET     0
-#define BMI160_INT2_CTRL_OFFSET     4
+#define BMI160_MAG_READ_BURST_1 0
+#define BMI160_MAG_READ_BURST_2 1
+#define BMI160_MAG_READ_BURST_6 2
+#define BMI160_MAG_READ_BURST_8 3
+#define BMI160_MAG_OFFSET_OFF 3
+#define BMI160_MAG_OFFSET_MASK (0xf << BMI160_MAG_OFFSET_OFF)
+#define BMI160_MAG_MANUAL_EN BIT(7)
+
+#define BMI160_MAG_IF_2 0x4d
+#define BMI160_MAG_I2C_READ_ADDR BMI160_MAG_IF_2
+#define BMI160_MAG_IF_3 0x4e
+#define BMI160_MAG_I2C_WRITE_ADDR BMI160_MAG_IF_3
+#define BMI160_MAG_IF_4 0x4f
+#define BMI160_MAG_I2C_WRITE_DATA BMI160_MAG_IF_4
+#define BMI160_MAG_I2C_READ_DATA BMI160_MAG_X_L_G
+
+#define BMI160_INT_EN_0 0x50
+#define BMI160_INT_ANYMO_X_EN BIT(0)
+#define BMI160_INT_ANYMO_Y_EN BIT(1)
+#define BMI160_INT_ANYMO_Z_EN BIT(2)
+#define BMI160_INT_D_TAP_EN BIT(4)
+#define BMI160_INT_S_TAP_EN BIT(5)
+#define BMI160_INT_ORIENT_EN BIT(6)
+#define BMI160_INT_FLAT_EN BIT(7)
+#define BMI160_INT_EN_1 0x51
+#define BMI160_INT_HIGHG_X_EN BIT(0)
+#define BMI160_INT_HIGHG_Y_EN BIT(1)
+#define BMI160_INT_HIGHG_Z_EN BIT(2)
+#define BMI160_INT_LOW_EN BIT(3)
+#define BMI160_INT_DRDY_EN BIT(4)
+#define BMI160_INT_FFUL_EN BIT(5)
+#define BMI160_INT_FWM_EN BIT(6)
+#define BMI160_INT_EN_2 0x52
+#define BMI160_INT_NOMOX_EN BIT(0)
+#define BMI160_INT_NOMOY_EN BIT(1)
+#define BMI160_INT_NOMOZ_EN BIT(2)
+#define BMI160_INT_STEP_DET_EN BIT(3)
+
+#define BMI160_INT_OUT_CTRL 0x53
+#define BMI160_INT_EDGE_CTRL BIT(0)
+#define BMI160_INT_LVL_CTRL BIT(1)
+#define BMI160_INT_OD BIT(2)
+#define BMI160_INT_OUTPUT_EN BIT(3)
+#define BMI160_INT1_CTRL_OFFSET 0
+#define BMI160_INT2_CTRL_OFFSET 4
 #define BMI160_INT_CTRL(_i, _bit) \
-(CONCAT2(BMI160_INT_, _bit) << CONCAT3(BMI160_INT, _i, _CTRL_OFFSET))
-
-#define BMI160_INT_LATCH       0x54
-#define BMI160_INT1_INPUT_EN       BIT(4)
-#define BMI160_INT2_INPUT_EN       BIT(5)
-#define BMI160_LATCH_MASK          0xf
-#define BMI160_LATCH_NONE          0
-#define BMI160_LATCH_5MS           5
-#define BMI160_LATCH_FOREVER       0xf
-
-#define BMI160_INT_MAP_0       0x55
-#define BMI160_INT_LOWG_STEP       BIT(0)
-#define BMI160_INT_HIGHG           BIT(1)
-#define BMI160_INT_ANYMOTION       BIT(2)
-#define BMI160_INT_NOMOTION        BIT(3)
-#define BMI160_INT_D_TAP           BIT(4)
-#define BMI160_INT_S_TAP           BIT(5)
-#define BMI160_INT_ORIENT          BIT(6)
-#define BMI160_INT_FLAT            BIT(7)
-
-#define BMI160_INT_MAP_1       0x56
-#define BMI160_INT_PMU_TRIG        BIT(0)
-#define BMI160_INT_FFULL           BIT(1)
-#define BMI160_INT_FWM             BIT(2)
-#define BMI160_INT_DRDY            BIT(3)
-#define BMI160_INT1_MAP_OFFSET      4
-#define BMI160_INT2_MAP_OFFSET      0
+	(CONCAT2(BMI160_INT_, _bit) << CONCAT3(BMI160_INT, _i, _CTRL_OFFSET))
+
+#define BMI160_INT_LATCH 0x54
+#define BMI160_INT1_INPUT_EN BIT(4)
+#define BMI160_INT2_INPUT_EN BIT(5)
+#define BMI160_LATCH_MASK 0xf
+#define BMI160_LATCH_NONE 0
+#define BMI160_LATCH_5MS 5
+#define BMI160_LATCH_FOREVER 0xf
+
+#define BMI160_INT_MAP_0 0x55
+#define BMI160_INT_LOWG_STEP BIT(0)
+#define BMI160_INT_HIGHG BIT(1)
+#define BMI160_INT_ANYMOTION BIT(2)
+#define BMI160_INT_NOMOTION BIT(3)
+#define BMI160_INT_D_TAP BIT(4)
+#define BMI160_INT_S_TAP BIT(5)
+#define BMI160_INT_ORIENT BIT(6)
+#define BMI160_INT_FLAT BIT(7)
+
+#define BMI160_INT_MAP_1 0x56
+#define BMI160_INT_PMU_TRIG BIT(0)
+#define BMI160_INT_FFULL BIT(1)
+#define BMI160_INT_FWM BIT(2)
+#define BMI160_INT_DRDY BIT(3)
+#define BMI160_INT1_MAP_OFFSET 4
+#define BMI160_INT2_MAP_OFFSET 0
 #define BMI160_INT_MAP(_i, _bit) \
-(CONCAT2(BMI160_INT_, _bit) << CONCAT3(BMI160_INT, _i, _MAP_OFFSET))
-#define BMI160_INT_FIFO_MAP    BMI160_INT_MAP_1
+	(CONCAT2(BMI160_INT_, _bit) << CONCAT3(BMI160_INT, _i, _MAP_OFFSET))
+#define BMI160_INT_FIFO_MAP BMI160_INT_MAP_1
 
-#define BMI160_INT_MAP_2       0x57
+#define BMI160_INT_MAP_2 0x57
 
-#define BMI160_INT_MAP_INT_1   BMI160_INT_MAP_0
-#define BMI160_INT_MAP_INT_2   BMI160_INT_MAP_2
-#define BMI160_INT_MAP_REG(_i)  CONCAT2(BMI160_INT_MAP_INT_, _i)
+#define BMI160_INT_MAP_INT_1 BMI160_INT_MAP_0
+#define BMI160_INT_MAP_INT_2 BMI160_INT_MAP_2
+#define BMI160_INT_MAP_REG(_i) CONCAT2(BMI160_INT_MAP_INT_, _i)
 
-#define BMI160_INT_DATA_0      0x58
-#define BMI160_INT_DATA_1      0x59
+#define BMI160_INT_DATA_0 0x58
+#define BMI160_INT_DATA_1 0x59
 
-#define BMI160_INT_LOW_HIGH_0  0x5a
-#define BMI160_INT_LOW_HIGH_1  0x5b
-#define BMI160_INT_LOW_HIGH_2  0x5c
-#define BMI160_INT_LOW_HIGH_3  0x5d
-#define BMI160_INT_LOW_HIGH_4  0x5e
+#define BMI160_INT_LOW_HIGH_0 0x5a
+#define BMI160_INT_LOW_HIGH_1 0x5b
+#define BMI160_INT_LOW_HIGH_2 0x5c
+#define BMI160_INT_LOW_HIGH_3 0x5d
+#define BMI160_INT_LOW_HIGH_4 0x5e
 
-#define BMI160_INT_MOTION_0    0x5f
-#define BMI160_INT_MOTION_1    0x60
+#define BMI160_INT_MOTION_0 0x5f
+#define BMI160_INT_MOTION_1 0x60
 /*
  * The formula is defined in 2.11.25 (any motion interrupt [1]).
  *
@@ -268,11 +266,11 @@
  * x = a * 1000 / range * 1953
  */
 #define BMI160_MOTION_TH(_s, _mg) \
-	 (MIN(((_mg) * 1000) / ((_s)->current_range * 1953), 0xff))
-#define BMI160_INT_MOTION_2    0x61
-#define BMI160_INT_MOTION_3    0x62
-#define BMI160_MOTION_NO_MOT_SEL   BIT(0)
-#define BMI160_MOTION_SIG_MOT_SEL  BIT(1)
+	(MIN(((_mg)*1000) / ((_s)->current_range * 1953), 0xff))
+#define BMI160_INT_MOTION_2 0x61
+#define BMI160_INT_MOTION_3 0x62
+#define BMI160_MOTION_NO_MOT_SEL BIT(0)
+#define BMI160_MOTION_SIG_MOT_SEL BIT(1)
 #define BMI160_MOTION_SKIP_OFF 2
 #define BMI160_MOTION_SKIP_MASK 0x3
 #define BMI160_MOTION_SKIP_TIME(_ms) \
@@ -282,74 +280,75 @@
 #define BMI160_MOTION_PROOF_TIME(_ms) \
 	(MIN(__fls((_ms) / 250), BMI160_MOTION_PROOF_MASK))
 
-#define BMI160_INT_TAP_0       0x63
-#define BMI160_TAP_DUR(_s, _ms) \
+#define BMI160_INT_TAP_0 0x63
+#define BMI160_TAP_DUR(_s, _ms)                   \
 	((_ms) <= 250 ? MAX((_ms), 50) / 50 - 1 : \
-	 (_ms) <= 500 ? 4 + ((_ms) - 250) / 125 : \
-	 (_ms) < 700 ? 6 : 7)
+	 (_ms) <= 500 ? 4 + ((_ms)-250) / 125 :   \
+	 (_ms) < 700  ? 6 :                       \
+			7)
 
-#define BMI160_INT_TAP_1       0x64
+#define BMI160_INT_TAP_1 0x64
 #define BMI160_TAP_TH(_s, _mg) \
-	 (MIN(((_mg) * 1000) / ((_s)->current_range * 31250), 0x1f))
+	(MIN(((_mg)*1000) / ((_s)->current_range * 31250), 0x1f))
 
-#define BMI160_INT_ORIENT_0				0x65
+#define BMI160_INT_ORIENT_0 0x65
 
 /* No hysterisis, theta block, int on slope > 0.2 or axis > 1.5, symmetrical */
-#define BMI160_INT_ORIENT_0_INIT_VAL			0x48
+#define BMI160_INT_ORIENT_0_INIT_VAL 0x48
 
-#define BMI160_INT_ORIENT_1				0x66
+#define BMI160_INT_ORIENT_1 0x66
 
 /* no axes remap, no int on up/down, no blocking angle */
-#define BMI160_INT_ORIENT_1_INIT_VAL			0x00
-
-#define BMI160_INT_FLAT_0      0x67
-#define BMI160_INT_FLAT_1      0x68
-
-#define BMI160_FOC_CONF        0x69
-#define BMI160_FOC_GYRO_EN              BIT(6)
-#define BMI160_FOC_ACC_PLUS_1G          1
-#define BMI160_FOC_ACC_MINUS_1G         2
-#define BMI160_FOC_ACC_0G               3
-#define BMI160_FOC_ACC_Z_OFFSET         0
-#define BMI160_FOC_ACC_Y_OFFSET         2
-#define BMI160_FOC_ACC_X_OFFSET         4
-
-#define BMI160_CONF            0x6a
-#define BMI160_IF_CONF         0x6b
-#define BMI160_IF_MODE_OFF     4
-#define BMI160_IF_MODE_MASK    3
+#define BMI160_INT_ORIENT_1_INIT_VAL 0x00
+
+#define BMI160_INT_FLAT_0 0x67
+#define BMI160_INT_FLAT_1 0x68
+
+#define BMI160_FOC_CONF 0x69
+#define BMI160_FOC_GYRO_EN BIT(6)
+#define BMI160_FOC_ACC_PLUS_1G 1
+#define BMI160_FOC_ACC_MINUS_1G 2
+#define BMI160_FOC_ACC_0G 3
+#define BMI160_FOC_ACC_Z_OFFSET 0
+#define BMI160_FOC_ACC_Y_OFFSET 2
+#define BMI160_FOC_ACC_X_OFFSET 4
+
+#define BMI160_CONF 0x6a
+#define BMI160_IF_CONF 0x6b
+#define BMI160_IF_MODE_OFF 4
+#define BMI160_IF_MODE_MASK 3
 #define BMI160_IF_MODE_AUTO_OFF 0
-#define BMI160_IF_MODE_I2C_IOS  1
+#define BMI160_IF_MODE_I2C_IOS 1
 #define BMI160_IF_MODE_AUTO_I2C 2
 
-#define BMI160_PMU_TRIGGER     0x6c
-#define BMI160_SELF_TEST       0x6d
+#define BMI160_PMU_TRIGGER 0x6c
+#define BMI160_SELF_TEST 0x6d
 
-#define BMI160_NV_CONF         0x70
+#define BMI160_NV_CONF 0x70
 
-#define BMI160_OFFSET_ACC70        0x71
-#define BMI160_OFFSET_GYR70        0x74
-#define BMI160_OFFSET_EN_GYR98     0x77
-#define BMI160_OFFSET_ACC_EN            BIT(6)
-#define BMI160_OFFSET_GYRO_EN           BIT(7)
+#define BMI160_OFFSET_ACC70 0x71
+#define BMI160_OFFSET_GYR70 0x74
+#define BMI160_OFFSET_EN_GYR98 0x77
+#define BMI160_OFFSET_ACC_EN BIT(6)
+#define BMI160_OFFSET_GYRO_EN BIT(7)
 
-#define BMI160_STEP_CNT_0          0x78
-#define BMI160_STEP_CNT_1          0x79
-#define BMI160_STEP_CONF_0         0x7a
-#define BMI160_STEP_CONF_1         0x7b
+#define BMI160_STEP_CNT_0 0x78
+#define BMI160_STEP_CNT_1 0x79
+#define BMI160_STEP_CONF_0 0x7a
+#define BMI160_STEP_CONF_1 0x7b
 
-#define BMI160_CMD_REG             0x7e
-#define BMI160_CMD_SOFT_RESET      0xb6
-#define BMI160_CMD_NOOP            0x00
-#define BMI160_CMD_START_FOC       0x03
+#define BMI160_CMD_REG 0x7e
+#define BMI160_CMD_SOFT_RESET 0xb6
+#define BMI160_CMD_NOOP 0x00
+#define BMI160_CMD_START_FOC 0x03
 #define BMI160_CMD_ACC_MODE_OFFSET 0x10
-#define BMI160_CMD_ACC_MODE_SUSP   0x10
+#define BMI160_CMD_ACC_MODE_SUSP 0x10
 #define BMI160_CMD_ACC_MODE_NORMAL 0x11
 #define BMI160_CMD_ACC_MODE_LOWPOWER 0x12
-#define BMI160_CMD_GYR_MODE_SUSP   0x14
+#define BMI160_CMD_GYR_MODE_SUSP 0x14
 #define BMI160_CMD_GYR_MODE_NORMAL 0x15
 #define BMI160_CMD_GYR_MODE_FAST_STARTUP 0x17
-#define BMI160_CMD_MAG_MODE_SUSP   0x18
+#define BMI160_CMD_MAG_MODE_SUSP 0x18
 #define BMI160_CMD_MAG_MODE_NORMAL 0x19
 #define BMI160_CMD_MAG_MODE_LOWPOWER 0x1a
 #define BMI160_CMD_MODE_SUSPEND(_sensor_type) \
@@ -357,31 +356,31 @@
 #define BMI160_CMD_MODE_NORMAL(_sensor_type) \
 	(BMI160_CMD_ACC_MODE_OFFSET | (_sensor_type) << 2 | BMI160_PMU_NORMAL)
 
-#define BMI160_CMD_FIFO_FLUSH      0xb0
-#define BMI160_CMD_INT_RESET       0xb1
-#define BMI160_CMD_SOFT_RESET      0xb6
-#define BMI160_CMD_EXT_MODE_EN_B0  0x37
-#define BMI160_CMD_EXT_MODE_EN_B1  0x9a
-#define BMI160_CMD_EXT_MODE_EN_B2  0xc0
+#define BMI160_CMD_FIFO_FLUSH 0xb0
+#define BMI160_CMD_INT_RESET 0xb1
+#define BMI160_CMD_SOFT_RESET 0xb6
+#define BMI160_CMD_EXT_MODE_EN_B0 0x37
+#define BMI160_CMD_EXT_MODE_EN_B1 0x9a
+#define BMI160_CMD_EXT_MODE_EN_B2 0xc0
 
-#define BMI160_CMD_EXT_MODE_ADDR   0x7f
-#define BMI160_CMD_PAGING_EN           BIT(7)
-#define BMI160_CMD_TARGET_PAGE         BIT(4)
+#define BMI160_CMD_EXT_MODE_ADDR 0x7f
+#define BMI160_CMD_PAGING_EN BIT(7)
+#define BMI160_CMD_TARGET_PAGE BIT(4)
 #define BMI160_COM_C_TRIM_ADDR 0x85
-#define BMI160_COM_C_TRIM              (3 << 4)
+#define BMI160_COM_C_TRIM (3 << 4)
 
-#define BMI160_CMD_TGT_PAGE    0
-#define BMI160_CMD_TGT_PAGE_COM    1
-#define BMI160_CMD_TGT_PAGE_ACC    2
-#define BMI160_CMD_TGT_PAGE_GYR    3
+#define BMI160_CMD_TGT_PAGE 0
+#define BMI160_CMD_TGT_PAGE_COM 1
+#define BMI160_CMD_TGT_PAGE_ACC 2
+#define BMI160_CMD_TGT_PAGE_GYR 3
 
-#define BMI160_FF_FRAME_LEN_TS          4
-#define BMI160_FF_DATA_LEN_ACC          6
-#define BMI160_FF_DATA_LEN_GYR          6
-#define BMI160_FF_DATA_LEN_MAG          8
+#define BMI160_FF_FRAME_LEN_TS 4
+#define BMI160_FF_DATA_LEN_ACC 6
+#define BMI160_FF_DATA_LEN_GYR 6
+#define BMI160_FF_DATA_LEN_MAG 8
 
 /* Root mean square noise of 100 Hz accelerometer, units: ug */
-#define BMI160_ACCEL_RMS_NOISE_100HZ    1300
+#define BMI160_ACCEL_RMS_NOISE_100HZ 1300
 
 /* Functions to access the secondary device through the accel/gyro. */
 int bmi160_sec_raw_read8(const int port, const uint16_t addr_flags,
@@ -404,6 +403,6 @@ int bmi160_sec_raw_write8(const int port, const uint16_t addr_flags,
 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(SENSOR_ID(DT_ALIAS(bmi160_int)))
 #endif
-#endif  /* CONFIG_ZEPHYR */
+#endif /* CONFIG_ZEPHYR */
 
 #endif /* __CROS_EC_ACCELGYRO_BMI160_H */
diff --git a/include/driver/accelgyro_bmi160_public.h b/include/driver/accelgyro_bmi160_public.h
index 6a6890eb84..551e351fea 100644
--- a/include/driver/accelgyro_bmi160_public.h
+++ b/include/driver/accelgyro_bmi160_public.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,7 +18,7 @@
  */
 
 /* I2C addresses */
-#define BMI160_ADDR0_FLAGS      0x68
+#define BMI160_ADDR0_FLAGS 0x68
 
 extern const struct accelgyro_drv bmi160_drv;
 
diff --git a/include/driver/accelgyro_bmi260.h b/include/driver/accelgyro_bmi260.h
index fb5db82afb..5d55a85acc 100644
--- a/include/driver/accelgyro_bmi260.h
+++ b/include/driver/accelgyro_bmi260.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,320 +13,320 @@
 #include "mag_bmm150.h"
 #include "driver/accelgyro_bmi260_public.h"
 
-#define BMI260_CHIP_ID      0x00
+#define BMI260_CHIP_ID 0x00
 /* BMI260 chip identifier */
-#define BMI260_CHIP_ID_MAJOR    0x27
+#define BMI260_CHIP_ID_MAJOR 0x27
 /* BMI220 chip identifier */
-#define BMI220_CHIP_ID_MAJOR    0x26
-
-#define BMI260_ERR_REG          0x02
-
-#define BMI260_STATUS           0x03
-#define BMI260_AUX_BUSY             BIT(2)
-#define BMI260_CMD_RDY              BIT(4)
-#define BMI260_DRDY_AUX             BIT(5)
-#define BMI260_DRDY_GYR             BIT(6)
-#define BMI260_DRDY_ACC             BIT(7)
-#define BMI260_DRDY_OFF(_sensor)    (7 - (_sensor))
-#define BMI260_DRDY_MASK(_sensor)   (1 << BMI260_DRDY_OFF(_sensor))
-
-#define BMI260_AUX_X_L_G           0x04
-#define BMI260_AUX_X_H_G           0x05
-#define BMI260_AUX_Y_L_G           0x06
-#define BMI260_AUX_Y_H_G           0x07
-#define BMI260_AUX_Z_L_G           0x08
-#define BMI260_AUX_Z_H_G           0x09
-#define BMI260_AUX_R_L_G           0x0a
-#define BMI260_AUX_R_H_G           0x0b
-#define BMI260_ACC_X_L_G           0x0c
-#define BMI260_ACC_X_H_G           0x0d
-#define BMI260_ACC_Y_L_G           0x0e
-#define BMI260_ACC_Y_H_G           0x0f
-#define BMI260_ACC_Z_L_G           0x10
-#define BMI260_ACC_Z_H_G           0x11
-#define BMI260_GYR_X_L_G           0x12
-#define BMI260_GYR_X_H_G           0x13
-#define BMI260_GYR_Y_L_G           0x14
-#define BMI260_GYR_Y_H_G           0x15
-#define BMI260_GYR_Z_L_G           0x16
-#define BMI260_GYR_Z_H_G           0x17
-
-#define BMI260_SENSORTIME_0     0x18
-#define BMI260_SENSORTIME_1     0x19
-#define BMI260_SENSORTIME_2     0x1a
-
-#define BMI260_EVENT            0x1b
+#define BMI220_CHIP_ID_MAJOR 0x26
+
+#define BMI260_ERR_REG 0x02
+
+#define BMI260_STATUS 0x03
+#define BMI260_AUX_BUSY BIT(2)
+#define BMI260_CMD_RDY BIT(4)
+#define BMI260_DRDY_AUX BIT(5)
+#define BMI260_DRDY_GYR BIT(6)
+#define BMI260_DRDY_ACC BIT(7)
+#define BMI260_DRDY_OFF(_sensor) (7 - (_sensor))
+#define BMI260_DRDY_MASK(_sensor) (1 << BMI260_DRDY_OFF(_sensor))
+
+#define BMI260_AUX_X_L_G 0x04
+#define BMI260_AUX_X_H_G 0x05
+#define BMI260_AUX_Y_L_G 0x06
+#define BMI260_AUX_Y_H_G 0x07
+#define BMI260_AUX_Z_L_G 0x08
+#define BMI260_AUX_Z_H_G 0x09
+#define BMI260_AUX_R_L_G 0x0a
+#define BMI260_AUX_R_H_G 0x0b
+#define BMI260_ACC_X_L_G 0x0c
+#define BMI260_ACC_X_H_G 0x0d
+#define BMI260_ACC_Y_L_G 0x0e
+#define BMI260_ACC_Y_H_G 0x0f
+#define BMI260_ACC_Z_L_G 0x10
+#define BMI260_ACC_Z_H_G 0x11
+#define BMI260_GYR_X_L_G 0x12
+#define BMI260_GYR_X_H_G 0x13
+#define BMI260_GYR_Y_L_G 0x14
+#define BMI260_GYR_Y_H_G 0x15
+#define BMI260_GYR_Z_L_G 0x16
+#define BMI260_GYR_Z_H_G 0x17
+
+#define BMI260_SENSORTIME_0 0x18
+#define BMI260_SENSORTIME_1 0x19
+#define BMI260_SENSORTIME_2 0x1a
+
+#define BMI260_EVENT 0x1b
 
 /* 2 bytes interrupt reasons*/
-#define BMI260_INT_STATUS_0     0x1c
-#define BMI260_SIG_MOTION_OUT       BIT(0)
-#define BMI260_STEP_COUNTER_OUT     BIT(1)
-#define BMI260_HIGH_LOW_G_OUT       BIT(2)
-#define BMI260_TAP_OUT              BIT(3)
-#define BMI260_FLAT_OUT             BIT(4)
-#define BMI260_NO_MOTION_OUT        BIT(5)
-#define BMI260_ANY_MOTION_OUT       BIT(6)
-#define BMI260_ORIENTATION_OUT      BIT(7)
-
-#define BMI260_INT_STATUS_1     0x1d
-#define BMI260_FFULL_INT            BIT(0 + 8)
-#define BMI260_FWM_INT              BIT(1 + 8)
-#define BMI260_ERR_INT              BIT(2 + 8)
-#define BMI260_AUX_DRDY_INT         BIT(5 + 8)
-#define BMI260_GYR_DRDY_INT         BIT(6 + 8)
-#define BMI260_ACC_DRDY_INT         BIT(7 + 8)
-
-#define BMI260_INT_MASK             0xFFFF
-
-#define BMI260_SC_OUT_0         0x1e
-#define BMI260_SC_OUT_1         0x1f
-
-#define BMI260_ORIENT_ACT       0x20
-
-#define BMI260_INTERNAL_STATUS  0X21
-#define BMI260_MESSAGE_MASK         0xf
-#define BMI260_NOT_INIT             0x00
-#define BMI260_INIT_OK              0x01
-#define BMI260_INIT_ERR             0x02
-#define BMI260_DRV_ERR              0x03
-#define BMI260_SNS_STOP             0x04
-#define BMI260_NVM_ERROR            0x05
-#define BMI260_START_UP_ERROR       0x06
-#define BMI260_COMPAT_ERROR         0x07
-
-#define BMI260_TEMPERATURE_0    0x22
-#define BMI260_TEMPERATURE_1    0x23
-
-#define BMI260_FIFO_LENGTH_0    0x24
-#define BMI260_FIFO_LENGTH_1    0x25
-#define BMI260_FIFO_LENGTH_MASK     (BIT(14) - 1)
-#define BMI260_FIFO_DATA        0x26
-
-#define BMI260_FEAT_PAGE        0x2f
+#define BMI260_INT_STATUS_0 0x1c
+#define BMI260_SIG_MOTION_OUT BIT(0)
+#define BMI260_STEP_COUNTER_OUT BIT(1)
+#define BMI260_HIGH_LOW_G_OUT BIT(2)
+#define BMI260_TAP_OUT BIT(3)
+#define BMI260_FLAT_OUT BIT(4)
+#define BMI260_NO_MOTION_OUT BIT(5)
+#define BMI260_ANY_MOTION_OUT BIT(6)
+#define BMI260_ORIENTATION_OUT BIT(7)
+
+#define BMI260_INT_STATUS_1 0x1d
+#define BMI260_FFULL_INT BIT(0 + 8)
+#define BMI260_FWM_INT BIT(1 + 8)
+#define BMI260_ERR_INT BIT(2 + 8)
+#define BMI260_AUX_DRDY_INT BIT(5 + 8)
+#define BMI260_GYR_DRDY_INT BIT(6 + 8)
+#define BMI260_ACC_DRDY_INT BIT(7 + 8)
+
+#define BMI260_INT_MASK 0xFFFF
+
+#define BMI260_SC_OUT_0 0x1e
+#define BMI260_SC_OUT_1 0x1f
+
+#define BMI260_ORIENT_ACT 0x20
+
+#define BMI260_INTERNAL_STATUS 0X21
+#define BMI260_MESSAGE_MASK 0xf
+#define BMI260_NOT_INIT 0x00
+#define BMI260_INIT_OK 0x01
+#define BMI260_INIT_ERR 0x02
+#define BMI260_DRV_ERR 0x03
+#define BMI260_SNS_STOP 0x04
+#define BMI260_NVM_ERROR 0x05
+#define BMI260_START_UP_ERROR 0x06
+#define BMI260_COMPAT_ERROR 0x07
+
+#define BMI260_TEMPERATURE_0 0x22
+#define BMI260_TEMPERATURE_1 0x23
+
+#define BMI260_FIFO_LENGTH_0 0x24
+#define BMI260_FIFO_LENGTH_1 0x25
+#define BMI260_FIFO_LENGTH_MASK (BIT(14) - 1)
+#define BMI260_FIFO_DATA 0x26
+
+#define BMI260_FEAT_PAGE 0x2f
 /*
  * The register of feature page should be read/write as 16-bit register
  * Otherwise, there can be invalid data
  */
 /* Features page 0 */
-#define BMI260_ORIENT_OUT       0x36
-#define BMI260_ORIENT_OUT_PORTRAIT_LANDSCAPE_MASK   3
-#define BMI260_ORIENT_PORTRAIT                      0x0
-#define BMI260_ORIENT_LANDSCAPE                     0x1
-#define BMI260_ORIENT_PORTRAIT_INVERT               0x2
-#define BMI260_ORIENT_LANDSCAPE_INVERT              0x3
+#define BMI260_ORIENT_OUT 0x36
+#define BMI260_ORIENT_OUT_PORTRAIT_LANDSCAPE_MASK 3
+#define BMI260_ORIENT_PORTRAIT 0x0
+#define BMI260_ORIENT_LANDSCAPE 0x1
+#define BMI260_ORIENT_PORTRAIT_INVERT 0x2
+#define BMI260_ORIENT_LANDSCAPE_INVERT 0x3
 
 /* Features page 1 */
-#define BMI260_GEN_SET_1        0x34
-#define BMI260_GYR_SELF_OFF         BIT(9)
+#define BMI260_GEN_SET_1 0x34
+#define BMI260_GYR_SELF_OFF BIT(9)
 
-#define BMI260_TAP_1            0x3e
-#define BMI260_TAP_1_EN                     BIT(0)
-#define BMI260_TAP_1_SENSITIVITY_OFFSET     1
-#define BMI260_TAP_1_SENSITIVITY_MASK       \
-	(0x7 << BMI260_TAP_1_SENSITIVITY_OFFSET)
+#define BMI260_TAP_1 0x3e
+#define BMI260_TAP_1_EN BIT(0)
+#define BMI260_TAP_1_SENSITIVITY_OFFSET 1
+#define BMI260_TAP_1_SENSITIVITY_MASK (0x7 << BMI260_TAP_1_SENSITIVITY_OFFSET)
 
 /* Features page 2 */
-#define BMI260_ORIENT_1         0x30
-#define BMI260_ORIENT_1_EN          BIT(0)
-#define BMI260_ORIENT_1_UD_EN       BIT(1)
+#define BMI260_ORIENT_1 0x30
+#define BMI260_ORIENT_1_EN BIT(0)
+#define BMI260_ORIENT_1_UD_EN BIT(1)
 #define BMI260_ORIENT_1_MODE_OFFSET 2
-#define BMI260_ORIENT_1_MODE_MASK   (0x3 << BMI260_ORIENT_1_MODE_OFFSET)
-#define BMI260_ORIENT_1_BLOCK_OFFSET    4
-#define BMI260_ORIENT_1_BLOCK_MASK      (0x3 << BMI260_ORIENT_1_BLOCK_OFFSET)
-#define BMI260_ORIENT_1_THETA_OFFSET     6
-#define BMI260_ORIENT_1_THETA_MASK      \
+#define BMI260_ORIENT_1_MODE_MASK (0x3 << BMI260_ORIENT_1_MODE_OFFSET)
+#define BMI260_ORIENT_1_BLOCK_OFFSET 4
+#define BMI260_ORIENT_1_BLOCK_MASK (0x3 << BMI260_ORIENT_1_BLOCK_OFFSET)
+#define BMI260_ORIENT_1_THETA_OFFSET 6
+#define BMI260_ORIENT_1_THETA_MASK \
 	((BIT(6) - 1) << BMI260_ORIENT_1_THETA_OFFSET)
 
-#define BMI260_ORIENT_2         0x32
+#define BMI260_ORIENT_2 0x32
 /* hysteresis(10...0) range is 0~1g, default is 128 (0.0625g) */
-#define BMI260_ORIENT_2_HYSTERESIS_MASK     (BIT(11) - 1)
+#define BMI260_ORIENT_2_HYSTERESIS_MASK (BIT(11) - 1)
 
-#define BMI260_ACC_CONF         0x40
-#define BMI260_ACC_BW_OFFSET        4
-#define BMI260_ACC_BW_MASK          (0x7 << BMI260_ACC_BW_OFFSET)
-#define BMI260_FILTER_PERF          BIT(7)
-#define BMI260_ULP                  0x0
-#define BMI260_HP                   0x1
+#define BMI260_ACC_CONF 0x40
+#define BMI260_ACC_BW_OFFSET 4
+#define BMI260_ACC_BW_MASK (0x7 << BMI260_ACC_BW_OFFSET)
+#define BMI260_FILTER_PERF BIT(7)
+#define BMI260_ULP 0x0
+#define BMI260_HP 0x1
 
-#define BMI260_ACC_RANGE        0x41
-#define BMI260_GSEL_2G              0x00
-#define BMI260_GSEL_4G              0x01
-#define BMI260_GSEL_8G              0x02
-#define BMI260_GSEL_16G             0x03
+#define BMI260_ACC_RANGE 0x41
+#define BMI260_GSEL_2G 0x00
+#define BMI260_GSEL_4G 0x01
+#define BMI260_GSEL_8G 0x02
+#define BMI260_GSEL_16G 0x03
 
 /* The max positvie value of accel data is 0x7FFF, equal to range(g) */
 /* So, in order to get +1g, divide the 0x7FFF by range */
 #define BMI260_ACC_DATA_PLUS_1G(range) (0x7FFF / (range))
 #define BMI260_ACC_DATA_MINUS_1G(range) (-BMI260_ACC_DATA_PLUS_1G(range))
 
-#define BMI260_GYR_CONF         0x42
-#define BMI260_GYR_BW_OFFSET        4
-#define BMI260_GYR_BW_MASK          (0x3 << BMI260_GYR_BW_OFFSET)
-#define BMI260_GYR_NOISE_PERF       BIT(6)
-
-#define BMI260_GYR_RANGE        0x43
-#define BMI260_DPS_SEL_2000         0x00
-#define BMI260_DPS_SEL_1000         0x01
-#define BMI260_DPS_SEL_500          0x02
-#define BMI260_DPS_SEL_250          0x03
-#define BMI260_DPS_SEL_125          0x04
-
-#define BMI260_AUX_CONF         0x44
-
-#define BMI260_FIFO_DOWNS       0x45
-
-#define BMI260_FIFO_WTM_0       0x46
-#define BMI260_FIFO_WTM_1       0x47
-
-#define BMI260_FIFO_CONFIG_0    0x48
-#define BMI260_FIFO_STOP_ON_FULL    BIT(0)
-#define BMI260_FIFO_TIME_EN     BIT(1)
-
-#define BMI260_FIFO_CONFIG_1    0x49
-#define BMI260_FIFO_TAG_INT1_EN_OFFSET  0
-#define BMI260_FIFO_TAG_INT1_EN_MASK    (0x3 << BMI260_FIFO_TAG_INT1_EN_OFFSET)
-#define BMI260_FIFO_TAG_INT2_EN_OFFSET  2
-#define BMI260_FIFO_TAG_INT2_EN_MASK    (0x3 << BMI260_FIFO_TAG_INT2_EN_OFFSET)
-#define BMI260_FIFO_TAG_INT_EDGE        0x0
-#define BMI260_FIFO_TAG_INT_LEVEL       0x1
-#define BMI260_FIFO_TAG_ACC_SAT         0x2
-#define BMI260_FIFO_TAG_GYR_SAT         0x3
-#define BMI260_FIFO_HEADER_EN           BIT(4)
-#define BMI260_FIFO_AUX_EN              BIT(5)
-#define BMI260_FIFO_ACC_EN              BIT(6)
-#define BMI260_FIFO_GYR_EN              BIT(7)
-#define BMI260_FIFO_SENSOR_EN(_sensor) \
-	((_sensor) == MOTIONSENSE_TYPE_ACCEL ? BMI260_FIFO_ACC_EN : \
-	  ((_sensor) == MOTIONSENSE_TYPE_GYRO ? BMI260_FIFO_GYR_EN : \
-	   BMI260_FIFO_AUX_EN))
-
-#define BMI260_SATURATION       0x4a
-
-#define BMI260_AUX_DEV_ID       0x4b
-#define BMI260_AUX_I2C_ADDRESS          BMI260_AUX_DEV_ID
-
-#define BMI260_AUX_IF_CONF      0x4c
-#define BMI260_AUX_I2C_CONTROL          BMI260_AUX_IF_CONF
-#define BMI260_AUX_READ_BURST_MASK      3
-#define BMI260_AUX_MAN_READ_BURST_OFF   2
-#define BMI260_AUX_MAN_READ_BURST_MASK  (0x3 << BMI280_AUX_MAN_READ_BURST_OFF)
-#define BMI260_AUX_READ_BURST_1         0
-#define BMI260_AUX_READ_BURST_2         1
-#define BMI260_AUX_READ_BURST_6         2
-#define BMI260_AUX_READ_BURST_8         3
-#define BMI260_AUX_FCU_WRITE_EN         BIT(6)
-#define BMI260_AUX_MANUAL_EN            BIT(7)
-
-#define BMI260_AUX_RD_ADDR      0x4d
-#define BMI260_AUX_I2C_READ_ADDR    BMI260_AUX_RD_ADDR
-#define BMI260_AUX_WR_ADDR      0x4e
-#define BMI260_AUX_I2C_WRITE_ADDR   BMI260_AUX_WR_ADDR
-#define BMI260_AUX_WR_DATA      0x4f
-#define BMI260_AUX_I2C_WRITE_DATA   BMI260_AUX_WR_DATA
-#define BMI260_AUX_I2C_READ_DATA    BMI260_AUX_X_L_G
-
-#define BMI260_ERR_REG_MSK      0x52
-#define BMI260_FATAL_ERR            BIT(0)
-#define BMI260_INTERNAL_ERR_OFF     1
-#define BMI260_INTERNAL_ERR_MASK    (0xf << BMI260_INTERNAL_ERR_OFF)
-#define BMI260_FIFO_ERR             BIT(6)
-#define BMI260_AUX_ERR              BIT(7)
-
-#define BMI260_INT1_IO_CTRL     0x53
-#define BMI260_INT1_LVL             BIT(1)
-#define BMI260_INT1_OD              BIT(2)
-#define BMI260_INT1_OUTPUT_EN       BIT(3)
-#define BMI260_INT1_INPUT_EN        BIT(4)
-
-#define BMI260_INT2_IO_CTRL     0x54
-#define BMI260_INT2_LVL             BIT(1)
-#define BMI260_INT2_OD              BIT(2)
-#define BMI260_INT2_OUTPUT_EN       BIT(3)
-#define BMI260_INT2_INPUT_EN        BIT(4)
-
-#define BMI260_INT_LATCH        0x55
-#define BMI260_INT_LATCH_EN         BIT(0)
-
-#define BMI260_INT1_MAP_FEAT    0x56
-#define BMI260_INT2_MAP_FEAT    0x57
-#define BMI260_MAP_SIG_MOTION_OUT   BIT(0)
+#define BMI260_GYR_CONF 0x42
+#define BMI260_GYR_BW_OFFSET 4
+#define BMI260_GYR_BW_MASK (0x3 << BMI260_GYR_BW_OFFSET)
+#define BMI260_GYR_NOISE_PERF BIT(6)
+
+#define BMI260_GYR_RANGE 0x43
+#define BMI260_DPS_SEL_2000 0x00
+#define BMI260_DPS_SEL_1000 0x01
+#define BMI260_DPS_SEL_500 0x02
+#define BMI260_DPS_SEL_250 0x03
+#define BMI260_DPS_SEL_125 0x04
+
+#define BMI260_AUX_CONF 0x44
+
+#define BMI260_FIFO_DOWNS 0x45
+
+#define BMI260_FIFO_WTM_0 0x46
+#define BMI260_FIFO_WTM_1 0x47
+
+#define BMI260_FIFO_CONFIG_0 0x48
+#define BMI260_FIFO_STOP_ON_FULL BIT(0)
+#define BMI260_FIFO_TIME_EN BIT(1)
+
+#define BMI260_FIFO_CONFIG_1 0x49
+#define BMI260_FIFO_TAG_INT1_EN_OFFSET 0
+#define BMI260_FIFO_TAG_INT1_EN_MASK (0x3 << BMI260_FIFO_TAG_INT1_EN_OFFSET)
+#define BMI260_FIFO_TAG_INT2_EN_OFFSET 2
+#define BMI260_FIFO_TAG_INT2_EN_MASK (0x3 << BMI260_FIFO_TAG_INT2_EN_OFFSET)
+#define BMI260_FIFO_TAG_INT_EDGE 0x0
+#define BMI260_FIFO_TAG_INT_LEVEL 0x1
+#define BMI260_FIFO_TAG_ACC_SAT 0x2
+#define BMI260_FIFO_TAG_GYR_SAT 0x3
+#define BMI260_FIFO_HEADER_EN BIT(4)
+#define BMI260_FIFO_AUX_EN BIT(5)
+#define BMI260_FIFO_ACC_EN BIT(6)
+#define BMI260_FIFO_GYR_EN BIT(7)
+#define BMI260_FIFO_SENSOR_EN(_sensor)                                      \
+	((_sensor) == MOTIONSENSE_TYPE_ACCEL ?                              \
+		 BMI260_FIFO_ACC_EN :                                       \
+		 ((_sensor) == MOTIONSENSE_TYPE_GYRO ? BMI260_FIFO_GYR_EN : \
+						       BMI260_FIFO_AUX_EN))
+
+#define BMI260_SATURATION 0x4a
+
+#define BMI260_AUX_DEV_ID 0x4b
+#define BMI260_AUX_I2C_ADDRESS BMI260_AUX_DEV_ID
+
+#define BMI260_AUX_IF_CONF 0x4c
+#define BMI260_AUX_I2C_CONTROL BMI260_AUX_IF_CONF
+#define BMI260_AUX_READ_BURST_MASK 3
+#define BMI260_AUX_MAN_READ_BURST_OFF 2
+#define BMI260_AUX_MAN_READ_BURST_MASK (0x3 << BMI280_AUX_MAN_READ_BURST_OFF)
+#define BMI260_AUX_READ_BURST_1 0
+#define BMI260_AUX_READ_BURST_2 1
+#define BMI260_AUX_READ_BURST_6 2
+#define BMI260_AUX_READ_BURST_8 3
+#define BMI260_AUX_FCU_WRITE_EN BIT(6)
+#define BMI260_AUX_MANUAL_EN BIT(7)
+
+#define BMI260_AUX_RD_ADDR 0x4d
+#define BMI260_AUX_I2C_READ_ADDR BMI260_AUX_RD_ADDR
+#define BMI260_AUX_WR_ADDR 0x4e
+#define BMI260_AUX_I2C_WRITE_ADDR BMI260_AUX_WR_ADDR
+#define BMI260_AUX_WR_DATA 0x4f
+#define BMI260_AUX_I2C_WRITE_DATA BMI260_AUX_WR_DATA
+#define BMI260_AUX_I2C_READ_DATA BMI260_AUX_X_L_G
+
+#define BMI260_ERR_REG_MSK 0x52
+#define BMI260_FATAL_ERR BIT(0)
+#define BMI260_INTERNAL_ERR_OFF 1
+#define BMI260_INTERNAL_ERR_MASK (0xf << BMI260_INTERNAL_ERR_OFF)
+#define BMI260_FIFO_ERR BIT(6)
+#define BMI260_AUX_ERR BIT(7)
+
+#define BMI260_INT1_IO_CTRL 0x53
+#define BMI260_INT1_LVL BIT(1)
+#define BMI260_INT1_OD BIT(2)
+#define BMI260_INT1_OUTPUT_EN BIT(3)
+#define BMI260_INT1_INPUT_EN BIT(4)
+
+#define BMI260_INT2_IO_CTRL 0x54
+#define BMI260_INT2_LVL BIT(1)
+#define BMI260_INT2_OD BIT(2)
+#define BMI260_INT2_OUTPUT_EN BIT(3)
+#define BMI260_INT2_INPUT_EN BIT(4)
+
+#define BMI260_INT_LATCH 0x55
+#define BMI260_INT_LATCH_EN BIT(0)
+
+#define BMI260_INT1_MAP_FEAT 0x56
+#define BMI260_INT2_MAP_FEAT 0x57
+#define BMI260_MAP_SIG_MOTION_OUT BIT(0)
 #define BMI260_MAP_STEP_COUNTER_OUT BIT(1)
-#define BMI260_MAP_HIGH_LOW_G_OUT   BIT(2)
-#define BMI260_MAP_TAP_OUT          BIT(3)
-#define BMI260_MAP_FLAT_OUT         BIT(4)
-#define BMI260_MAP_NO_MOTION_OUT    BIT(5)
-#define BMI260_MAP_ANY_MOTION_OUT   BIT(6)
-#define BMI260_MAP_ORIENTAION_OUT   BIT(7)
-
-#define BMI260_INT_MAP_DATA     0x58
-#define BMI260_MAP_FFULL_INT        BIT(0)
-#define BMI260_MAP_FWM_INT          BIT(1)
-#define BMI260_MAP_DRDY_INT         BIT(2)
-#define BMI260_MAP_ERR_INT          BIT(3)
-#define BMI260_INT_MAP_DATA_INT1_OFFSET     0
-#define BMI260_INT_MAP_DATA_INT2_OFFSET     4
+#define BMI260_MAP_HIGH_LOW_G_OUT BIT(2)
+#define BMI260_MAP_TAP_OUT BIT(3)
+#define BMI260_MAP_FLAT_OUT BIT(4)
+#define BMI260_MAP_NO_MOTION_OUT BIT(5)
+#define BMI260_MAP_ANY_MOTION_OUT BIT(6)
+#define BMI260_MAP_ORIENTAION_OUT BIT(7)
+
+#define BMI260_INT_MAP_DATA 0x58
+#define BMI260_MAP_FFULL_INT BIT(0)
+#define BMI260_MAP_FWM_INT BIT(1)
+#define BMI260_MAP_DRDY_INT BIT(2)
+#define BMI260_MAP_ERR_INT BIT(3)
+#define BMI260_INT_MAP_DATA_INT1_OFFSET 0
+#define BMI260_INT_MAP_DATA_INT2_OFFSET 4
 #define BMI260_INT_MAP_DATA_REG(_i, _bit) \
-	(CONCAT3(BMI260_MAP_, _bit, _INT) << \
-	CONCAT3(BMI260_INT_MAP_DATA_INT, _i, _OFFSET))
+	(CONCAT3(BMI260_MAP_, _bit, _INT) \
+	 << CONCAT3(BMI260_INT_MAP_DATA_INT, _i, _OFFSET))
 
-#define BMI260_INIT_CTRL        0x59
-#define BMI260_INIT_ADDR_0      0x5b
-#define BMI260_INIT_ADDR_1      0x5c
-#define BMI260_INIT_DATA        0x5e
-#define BMI260_INTERNAL_ERROR   0x5f
-#define BMI260_INT_ERR_1            BIT(1)
-#define BMI260_INT_ERR_2            BIT(2)
-#define BMI260_FEAT_ENG_DISABLED    BIT(4)
+#define BMI260_INIT_CTRL 0x59
+#define BMI260_INIT_ADDR_0 0x5b
+#define BMI260_INIT_ADDR_1 0x5c
+#define BMI260_INIT_DATA 0x5e
+#define BMI260_INTERNAL_ERROR 0x5f
+#define BMI260_INT_ERR_1 BIT(1)
+#define BMI260_INT_ERR_2 BIT(2)
+#define BMI260_FEAT_ENG_DISABLED BIT(4)
 
-#define BMI260_AUX_IF_TRIM      0x68
-#define BMI260_GYR_CRT_CONF     0x69
+#define BMI260_AUX_IF_TRIM 0x68
+#define BMI260_GYR_CRT_CONF 0x69
 
-#define BMI260_NVM_CONF         0x6a
-#define BMI260_NVM_PROG_EN          BIT(1)
+#define BMI260_NVM_CONF 0x6a
+#define BMI260_NVM_PROG_EN BIT(1)
 
-#define BMI260_IF_CONF          0x6b
-#define BMI260_IF_SPI3              BIT(0)
-#define BMI260_IF_SPI3_OIS          BIT(1)
-#define BMI260_IF_OIS_EN            BIT(4)
-#define BMI260_IF_AUX_EN            BIT(5)
+#define BMI260_IF_CONF 0x6b
+#define BMI260_IF_SPI3 BIT(0)
+#define BMI260_IF_SPI3_OIS BIT(1)
+#define BMI260_IF_OIS_EN BIT(4)
+#define BMI260_IF_AUX_EN BIT(5)
 
-#define BMI260_DRV              0x6c
-#define BMI260_ACC_SELF_TEST    0x6d
+#define BMI260_DRV 0x6c
+#define BMI260_ACC_SELF_TEST 0x6d
 
 #define BMI260_GYR_SELF_TEST_AXES 0x6e
 
-#define BMI260_NV_CONF          0x70
-#define BMI260_ACC_OFFSET_EN        BIT(3)
+#define BMI260_NV_CONF 0x70
+#define BMI260_ACC_OFFSET_EN BIT(3)
 
-#define BMI260_OFFSET_ACC70     0x71
-#define BMI260_OFFSET_GYR70     0x74
-#define BMI260_OFFSET_EN_GYR98  0x77
-#define BMI260_OFFSET_GYRO_EN       BIT(6)
-#define BMI260_GYR_GAIN_EN          BIT(7)
+#define BMI260_OFFSET_ACC70 0x71
+#define BMI260_OFFSET_GYR70 0x74
+#define BMI260_OFFSET_EN_GYR98 0x77
+#define BMI260_OFFSET_GYRO_EN BIT(6)
+#define BMI260_GYR_GAIN_EN BIT(7)
 
-#define BMI260_PWR_CONF         0x7c
-#define BMI260_ADV_POWER_SAVE       BIT(0)
-#define BMI260_FIFO_SELF_WAKE_UP    BIT(1)
-#define BMI260_FUP_EN               BIT(2)
+#define BMI260_PWR_CONF 0x7c
+#define BMI260_ADV_POWER_SAVE BIT(0)
+#define BMI260_FIFO_SELF_WAKE_UP BIT(1)
+#define BMI260_FUP_EN BIT(2)
 
-#define BMI260_PWR_CTRL         0x7d
-#define BMI260_AUX_EN               BIT(0)
-#define BMI260_GYR_EN               BIT(1)
-#define BMI260_ACC_EN               BIT(2)
+#define BMI260_PWR_CTRL 0x7d
+#define BMI260_AUX_EN BIT(0)
+#define BMI260_GYR_EN BIT(1)
+#define BMI260_ACC_EN BIT(2)
 #define BMI260_PWR_EN(_sensor_type) BIT(2 - _sensor_type)
-#define BMI260_TEMP_EN              BIT(3)
+#define BMI260_TEMP_EN BIT(3)
 
-#define BMI260_CMD_REG          0x7e
-#define BMI260_CMD_FIFO_FLUSH       0xb0
-#define BMI260_CMD_SOFT_RESET       0xb6
+#define BMI260_CMD_REG 0x7e
+#define BMI260_CMD_FIFO_FLUSH 0xb0
+#define BMI260_CMD_SOFT_RESET 0xb6
 
-#define BMI260_FF_FRAME_LEN_TS          4
-#define BMI260_FF_DATA_LEN_ACC          6
-#define BMI260_FF_DATA_LEN_GYR          6
-#define BMI260_FF_DATA_LEN_MAG          8
+#define BMI260_FF_FRAME_LEN_TS 4
+#define BMI260_FF_DATA_LEN_ACC 6
+#define BMI260_FF_DATA_LEN_GYR 6
+#define BMI260_FF_DATA_LEN_MAG 8
 
 /* Root mean square noise of 100Hz accelerometer, units: ug */
-#define BMI260_ACCEL_RMS_NOISE_100HZ    1060
+#define BMI260_ACCEL_RMS_NOISE_100HZ 1060
 
 #if defined(CONFIG_ZEPHYR)
 #if DT_NODE_EXISTS(DT_ALIAS(bmi260_int))
@@ -343,9 +343,9 @@
  *     bmi260-int = &base_accel;
  * };
  */
-#define CONFIG_ACCELGYRO_BMI260_INT_EVENT	\
+#define CONFIG_ACCELGYRO_BMI260_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(SENSOR_ID(DT_ALIAS(bmi260_int)))
 #endif
-#endif  /* CONFIG_ZEPHYR */
+#endif /* CONFIG_ZEPHYR */
 
 #endif /* __CROS_EC_ACCELGYRO_BMI260_H */
diff --git a/include/driver/accelgyro_bmi260_public.h b/include/driver/accelgyro_bmi260_public.h
index 9b93ef65ae..33fc55300d 100644
--- a/include/driver/accelgyro_bmi260_public.h
+++ b/include/driver/accelgyro_bmi260_public.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,7 +18,7 @@
  */
 
 /* I2C addresses */
-#define BMI260_ADDR0_FLAGS	0x68
+#define BMI260_ADDR0_FLAGS 0x68
 
 extern const struct accelgyro_drv bmi260_drv;
 
diff --git a/include/driver/accelgyro_bmi_common.h b/include/driver/accelgyro_bmi_common.h
index 6e1ed122b3..371d3d97ce 100644
--- a/include/driver/accelgyro_bmi_common.h
+++ b/include/driver/accelgyro_bmi_common.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,18 +18,18 @@
 #error "BMI must use either SPI or I2C communication"
 #endif
 
-#define BMI_CONF_REG(_sensor)      (0x40 + 2 * (_sensor))
-#define BMI_RANGE_REG(_sensor)     (0x41 + 2 * (_sensor))
+#define BMI_CONF_REG(_sensor) (0x40 + 2 * (_sensor))
+#define BMI_RANGE_REG(_sensor) (0x41 + 2 * (_sensor))
 
-#define BMI_ODR_MASK         0x0F
+#define BMI_ODR_MASK 0x0F
 /* odr = 100 / (1 << (8 - reg)) , within limit */
-#define BMI_ODR_0_78HZ       0x01
-#define BMI_ODR_100HZ        0x08
+#define BMI_ODR_0_78HZ 0x01
+#define BMI_ODR_100HZ 0x08
 
-#define BMI_REG_TO_ODR(_regval) \
+#define BMI_REG_TO_ODR(_regval)                                        \
 	((_regval) < BMI_ODR_100HZ ? 100000 / (1 << (8 - (_regval))) : \
-					100000 * (1 << ((_regval) - 8)))
-#define BMI_ODR_TO_REG(_odr) \
+				     100000 * (1 << ((_regval)-8)))
+#define BMI_ODR_TO_REG(_odr)                                             \
 	((_odr) < 100000 ? (__builtin_clz(100000 / ((_odr) + 1)) - 24) : \
 			   (39 - __builtin_clz((_odr) / 100000)))
 
@@ -40,92 +40,97 @@ enum fifo_header {
 	BMI_FH_CONFIG = 0x48
 };
 
-#define BMI_FH_MODE_MASK     0xc0
-#define BMI_FH_PARM_OFFSET       2
-#define BMI_FH_PARM_MASK         (0x7 << BMI_FH_PARM_OFFSET)
-#define BMI_FH_EXT_MASK      0x03
+#define BMI_FH_MODE_MASK 0xc0
+#define BMI_FH_PARM_OFFSET 2
+#define BMI_FH_PARM_MASK (0x7 << BMI_FH_PARM_OFFSET)
+#define BMI_FH_EXT_MASK 0x03
 
 /* Sensor resolution in number of bits. This sensor has fixed resolution. */
-#define BMI_RESOLUTION      16
+#define BMI_RESOLUTION 16
 /* Min and Max sampling frequency in mHz */
 #define BMI_ACCEL_MIN_FREQ 12500
 #define BMI_ACCEL_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(1600000, 100000)
-#define BMI_GYRO_MIN_FREQ  25000
+#define BMI_GYRO_MIN_FREQ 25000
 #define BMI_GYRO_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(3200000, 100000)
 
 enum bmi_running_mode {
-	STANDARD_UI_9DOF_FIFO          = 0,
-	STANDARD_UI_IMU_FIFO           = 1,
-	STANDARD_UI_IMU                = 2,
-	STANDARD_UI_ADVANCEPOWERSAVE   = 3,
-	ACCEL_PEDOMETER                = 4,
-	APPLICATION_HEAD_TRACKING      = 5,
-	APPLICATION_NAVIGATION         = 6,
-	APPLICATION_REMOTE_CONTROL     = 7,
-	APPLICATION_INDOOR_NAVIGATION  = 8,
+	STANDARD_UI_9DOF_FIFO = 0,
+	STANDARD_UI_IMU_FIFO = 1,
+	STANDARD_UI_IMU = 2,
+	STANDARD_UI_ADVANCEPOWERSAVE = 3,
+	ACCEL_PEDOMETER = 4,
+	APPLICATION_HEAD_TRACKING = 5,
+	APPLICATION_NAVIGATION = 6,
+	APPLICATION_REMOTE_CONTROL = 7,
+	APPLICATION_INDOOR_NAVIGATION = 8,
 };
 
-#define BMI_FLAG_SEC_I2C_ENABLED    BIT(0)
-#define BMI_FIFO_FLAG_OFFSET        4
-#define BMI_FIFO_ALL_MASK           7
-
-#define BMI_GET_DATA(_s) \
-	((struct bmi_drv_data_t *)(_s)->drv_data)
-#define BMI_GET_SAVED_DATA(_s) \
-	(&BMI_GET_DATA(_s)->saved_data[(_s)->type])
-
-#define BMI_ACC_DATA(v) (BMI160_ACC_X_L_G + \
-	(v) * (BMI260_ACC_X_L_G - BMI160_ACC_X_L_G))
-#define BMI_GYR_DATA(v) (BMI160_GYR_X_L_G + \
-	(v) * (BMI260_GYR_X_L_G - BMI160_GYR_X_L_G))
-#define BMI_AUX_DATA(v) (BMI160_MAG_X_L_G + \
-	(v) * (BMI260_AUX_X_L_G - BMI160_MAG_X_L_G))
-
-#define BMI_FIFO_CONFIG_0(v) (BMI160_FIFO_CONFIG_0 + \
-	(v) * (BMI260_FIFO_CONFIG_0 - BMI160_FIFO_CONFIG_0))
-#define BMI_FIFO_CONFIG_1(v) (BMI160_FIFO_CONFIG_1 + \
-	(v) * (BMI260_FIFO_CONFIG_1 - BMI160_FIFO_CONFIG_1))
-#define BMI_FIFO_SENSOR_EN(v, _sensor) (BMI160_FIFO_SENSOR_EN(_sensor) + \
-	(v) * (BMI260_FIFO_SENSOR_EN(_sensor) - BMI160_FIFO_SENSOR_EN(_sensor)))
-
-#define BMI_TEMPERATURE_0(v) (BMI160_TEMPERATURE_0 + \
-	(v) * (BMI260_TEMPERATURE_0 - BMI160_TEMPERATURE_0))
-#define BMI_INVALID_TEMP     0x8000
-
-#define BMI_STATUS(v) (BMI160_STATUS + \
-	(v) * (BMI260_STATUS - BMI160_STATUS))
-#define BMI_DRDY_OFF(_sensor)   (7 - (_sensor))
-#define BMI_DRDY_MASK(_sensor)  (1 << BMI160_DRDY_OFF(_sensor))
-
-#define BMI_OFFSET_ACC70(v) (BMI160_OFFSET_ACC70 + \
-	(v) * (BMI260_OFFSET_ACC70 - BMI160_OFFSET_ACC70))
-#define BMI_OFFSET_GYR70(v) (BMI160_OFFSET_GYR70 + \
-	(v) * (BMI260_OFFSET_GYR70 - BMI160_OFFSET_GYR70))
+#define BMI_FLAG_SEC_I2C_ENABLED BIT(0)
+#define BMI_FIFO_FLAG_OFFSET 4
+#define BMI_FIFO_ALL_MASK 7
+
+#define BMI_GET_DATA(_s) ((struct bmi_drv_data_t *)(_s)->drv_data)
+#define BMI_GET_SAVED_DATA(_s) (&BMI_GET_DATA(_s)->saved_data[(_s)->type])
+
+#define BMI_ACC_DATA(v) \
+	(BMI160_ACC_X_L_G + (v) * (BMI260_ACC_X_L_G - BMI160_ACC_X_L_G))
+#define BMI_GYR_DATA(v) \
+	(BMI160_GYR_X_L_G + (v) * (BMI260_GYR_X_L_G - BMI160_GYR_X_L_G))
+#define BMI_AUX_DATA(v) \
+	(BMI160_MAG_X_L_G + (v) * (BMI260_AUX_X_L_G - BMI160_MAG_X_L_G))
+
+#define BMI_FIFO_CONFIG_0(v)    \
+	(BMI160_FIFO_CONFIG_0 + \
+	 (v) * (BMI260_FIFO_CONFIG_0 - BMI160_FIFO_CONFIG_0))
+#define BMI_FIFO_CONFIG_1(v)    \
+	(BMI160_FIFO_CONFIG_1 + \
+	 (v) * (BMI260_FIFO_CONFIG_1 - BMI160_FIFO_CONFIG_1))
+#define BMI_FIFO_SENSOR_EN(v, _sensor)           \
+	(BMI160_FIFO_SENSOR_EN(_sensor) +        \
+	 (v) * (BMI260_FIFO_SENSOR_EN(_sensor) - \
+		BMI160_FIFO_SENSOR_EN(_sensor)))
+
+#define BMI_TEMPERATURE_0(v)    \
+	(BMI160_TEMPERATURE_0 + \
+	 (v) * (BMI260_TEMPERATURE_0 - BMI160_TEMPERATURE_0))
+#define BMI_INVALID_TEMP 0x8000
+
+#define BMI_STATUS(v) (BMI160_STATUS + (v) * (BMI260_STATUS - BMI160_STATUS))
+#define BMI_DRDY_OFF(_sensor) (7 - (_sensor))
+#define BMI_DRDY_MASK(_sensor) (1 << BMI160_DRDY_OFF(_sensor))
+
+#define BMI_OFFSET_ACC70(v)    \
+	(BMI160_OFFSET_ACC70 + \
+	 (v) * (BMI260_OFFSET_ACC70 - BMI160_OFFSET_ACC70))
+#define BMI_OFFSET_GYR70(v)    \
+	(BMI160_OFFSET_GYR70 + \
+	 (v) * (BMI260_OFFSET_GYR70 - BMI160_OFFSET_GYR70))
 /*
  * There is some bits in this register that differ between BMI160 and BMI260
  * Only use this macro for gyro offset 9:8 (BMI_OFFSET_EN_GYR98 5:0).
  */
-#define BMI_OFFSET_EN_GYR98(v) (BMI160_OFFSET_EN_GYR98 + \
-	(v) * (BMI260_OFFSET_EN_GYR98 - BMI160_OFFSET_EN_GYR98))
-#define BMI_OFFSET_GYR98_MASK     (BIT(6) - 1)
-#define BMI_OFFSET_ACC_MULTI_MG   (3900 * 1024)
-#define BMI_OFFSET_ACC_DIV_MG     1000000
+#define BMI_OFFSET_EN_GYR98(v)    \
+	(BMI160_OFFSET_EN_GYR98 + \
+	 (v) * (BMI260_OFFSET_EN_GYR98 - BMI160_OFFSET_EN_GYR98))
+#define BMI_OFFSET_GYR98_MASK (BIT(6) - 1)
+#define BMI_OFFSET_ACC_MULTI_MG (3900 * 1024)
+#define BMI_OFFSET_ACC_DIV_MG 1000000
 #define BMI_OFFSET_GYRO_MULTI_MDS (61 * 1024)
-#define BMI_OFFSET_GYRO_DIV_MDS   1000
-
-#define BMI_FIFO_LENGTH_0(v) (BMI160_FIFO_LENGTH_0 + \
-	(v) * (BMI260_FIFO_LENGTH_0 - BMI160_FIFO_LENGTH_0))
-#define BMI_FIFO_LENGTH_MASK(v) (BMI160_FIFO_LENGTH_MASK + \
-	(v) * (BMI260_FIFO_LENGTH_MASK - BMI160_FIFO_LENGTH_MASK))
-#define BMI_FIFO_DATA(v) (BMI160_FIFO_DATA + \
-	(v) * (BMI260_FIFO_DATA - BMI160_FIFO_DATA))
-
-#define BMI_CMD_REG(v) (BMI160_CMD_REG + \
-	(v) * (BMI260_CMD_REG - BMI160_CMD_REG))
+#define BMI_OFFSET_GYRO_DIV_MDS 1000
+
+#define BMI_FIFO_LENGTH_0(v)    \
+	(BMI160_FIFO_LENGTH_0 + \
+	 (v) * (BMI260_FIFO_LENGTH_0 - BMI160_FIFO_LENGTH_0))
+#define BMI_FIFO_LENGTH_MASK(v)    \
+	(BMI160_FIFO_LENGTH_MASK + \
+	 (v) * (BMI260_FIFO_LENGTH_MASK - BMI160_FIFO_LENGTH_MASK))
+#define BMI_FIFO_DATA(v) \
+	(BMI160_FIFO_DATA + (v) * (BMI260_FIFO_DATA - BMI160_FIFO_DATA))
+
+#define BMI_CMD_REG(v) \
+	(BMI160_CMD_REG + (v) * (BMI260_CMD_REG - BMI160_CMD_REG))
 #define BMI_CMD_FIFO_FLUSH 0xb0
 
-#define BMI_ACCEL_RMS_NOISE_100HZ(v) (BMI160_ACCEL_RMS_NOISE_100HZ + \
-	(v) * (BMI260_ACCEL_RMS_NOISE_100HZ - BMI160_ACCEL_RMS_NOISE_100HZ))
 #define BMI_ACCEL_100HZ 100
 
 /*
@@ -145,8 +150,8 @@ int bmi_get_xyz_reg(const struct motion_sensor_t *s);
  *
  * @return       Range table of the type.
  */
-const struct bmi_accel_param_pair *bmi_get_range_table(
-		const struct motion_sensor_t *s, int *psize);
+const struct bmi_accel_param_pair *
+bmi_get_range_table(const struct motion_sensor_t *s, int *psize);
 
 /**
  * @return reg value that matches the given engineering value passed in.
@@ -155,8 +160,7 @@ const struct bmi_accel_param_pair *bmi_get_range_table(
  * outside the range of values, it returns the closest valid reg value.
  */
 int bmi_get_reg_val(const int eng_val, const int round_up,
-		    const struct bmi_accel_param_pair *pairs,
-		    const int size);
+		    const struct bmi_accel_param_pair *pairs, const int size);
 
 /**
  * @return engineering value that matches the given reg val
@@ -168,14 +172,14 @@ int bmi_get_engineering_val(const int reg_val,
 /**
  * Read 8bit register from accelerometer.
  */
-int bmi_read8(const int port, const uint16_t i2c_spi_addr_flags,
-	      const int reg, int *data_ptr);
+int bmi_read8(const int port, const uint16_t i2c_spi_addr_flags, const int reg,
+	      int *data_ptr);
 
 /**
  * Write 8bit register from accelerometer.
  */
-int bmi_write8(const int port, const uint16_t i2c_spi_addr_flags,
-	       const int reg, int data);
+int bmi_write8(const int port, const uint16_t i2c_spi_addr_flags, const int reg,
+	       int data);
 
 /**
  * Read 16bit register from accelerometer.
@@ -210,14 +214,14 @@ int bmi_write_n(const int port, const uint16_t i2c_spi_addr_flags,
 /*
  * Enable/Disable specific bit set of a 8-bit reg.
  */
-int bmi_enable_reg8(const struct motion_sensor_t *s,
-		    int reg, uint8_t bits, int enable);
+int bmi_enable_reg8(const struct motion_sensor_t *s, int reg, uint8_t bits,
+		    int enable);
 
 /*
  * Set specific bit set to certain value of a 8-bit reg.
  */
-int bmi_set_reg8(const struct motion_sensor_t *s, int reg,
-		 uint8_t bits, int mask);
+int bmi_set_reg8(const struct motion_sensor_t *s, int reg, uint8_t bits,
+		 int mask);
 
 /*
  * @s: base sensor.
@@ -237,9 +241,8 @@ void bmi_normalize(const struct motion_sensor_t *s, intv3_t v, uint8_t *input);
  * @bp: current pointer in the buffer, updated when processing the header.
  * @ep: pointer to the end of the valid data in the buffer.
  */
-int bmi_decode_header(struct motion_sensor_t *accel,
-		      enum fifo_header hdr, uint32_t last_ts,
-		      uint8_t **bp, uint8_t *ep);
+int bmi_decode_header(struct motion_sensor_t *accel, enum fifo_header hdr,
+		      uint32_t last_ts, uint8_t **bp, uint8_t *ep);
 /**
  * Retrieve hardware FIFO from sensor,
  * - put data in Sensor Hub fifo.
@@ -261,21 +264,19 @@ int bmi_set_range(struct motion_sensor_t *s, int range, int rnd);
 
 int bmi_get_data_rate(const struct motion_sensor_t *s);
 
-
-int bmi_get_offset(const struct motion_sensor_t *s,
-		   int16_t *offset, int16_t *temp);
+int bmi_get_offset(const struct motion_sensor_t *s, int16_t *offset,
+		   int16_t *temp);
 
 int bmi_get_resolution(const struct motion_sensor_t *s);
 
-#ifdef CONFIG_BODY_DETECTION
-int bmi_get_rms_noise(const struct motion_sensor_t *s);
-#endif
+int bmi_get_rms_noise(const struct motion_sensor_t *accel,
+		      int rms_noise_100hz_mg);
 
-int bmi_set_scale(const struct motion_sensor_t *s,
-		  const uint16_t *scale, int16_t temp);
+int bmi_set_scale(const struct motion_sensor_t *s, const uint16_t *scale,
+		  int16_t temp);
 
-int bmi_get_scale(const struct motion_sensor_t *s,
-		  uint16_t *scale, int16_t *temp);
+int bmi_get_scale(const struct motion_sensor_t *s, uint16_t *scale,
+		  int16_t *temp);
 
 /* Start/Stop the FIFO collecting events */
 int bmi_enable_fifo(const struct motion_sensor_t *s, int enable);
@@ -311,9 +312,8 @@ int bmi_set_accel_offset(const struct motion_sensor_t *accel, intv3_t v);
 
 /* Set the gyroscope offset */
 int bmi_set_gyro_offset(const struct motion_sensor_t *gyro, intv3_t v,
-			 int *val98_ptr);
+			int *val98_ptr);
 
-int bmi_list_activities(const struct motion_sensor_t *s,
-			uint32_t *enabled,
+int bmi_list_activities(const struct motion_sensor_t *s, uint32_t *enabled,
 			uint32_t *disabled);
 #endif /* __CROS_EC_ACCELGYRO_BMI_COMMON_H */
diff --git a/include/driver/accelgyro_bmi_common_public.h b/include/driver/accelgyro_bmi_common_public.h
index 52814c71bf..b3965d4dc5 100644
--- a/include/driver/accelgyro_bmi_common_public.h
+++ b/include/driver/accelgyro_bmi_common_public.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,14 +10,14 @@
 /* Min and Max sampling frequency in mHz */
 #define BMI_ACCEL_MIN_FREQ 12500
 #define BMI_ACCEL_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(1600000, 100000)
-#define BMI_GYRO_MIN_FREQ  25000
+#define BMI_GYRO_MIN_FREQ 25000
 #define BMI_GYRO_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(3200000, 100000)
 
 struct bmi_drv_data_t {
 	struct accelgyro_saved_data_t saved_data[3];
-	uint8_t              flags;
-	uint8_t              enabled_activities;
-	uint8_t              disabled_activities;
+	uint8_t flags;
+	uint8_t enabled_activities;
+	uint8_t disabled_activities;
 #ifdef CONFIG_MAG_BMI_BMM150
 	struct bmm150_private_data compass;
 #endif
@@ -26,7 +26,6 @@ struct bmi_drv_data_t {
 	enum motionsensor_orientation orientation;
 	enum motionsensor_orientation last_orientation;
 #endif
-
 };
 
 #endif /* __CROS_EC_DRIVER_ACCELGYRO_BMI_COMMON_PUBLIC_H */
diff --git a/include/driver/accelgyro_lsm6dso_public.h b/include/driver/accelgyro_lsm6dso_public.h
index 65e98bccec..f2c1b2bc4e 100644
--- a/include/driver/accelgyro_lsm6dso_public.h
+++ b/include/driver/accelgyro_lsm6dso_public.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,12 +14,11 @@
  * 7-bit address is 110101xb. Where 'x' is determined
  * by the voltage on the ADDR pin
  */
-#define LSM6DSO_ADDR0_FLAGS		0x6a
-#define LSM6DSO_ADDR1_FLAGS		0x6b
+#define LSM6DSO_ADDR0_FLAGS 0x6a
+#define LSM6DSO_ADDR1_FLAGS 0x6b
 
 /* Absolute maximum rate for Acc and Gyro sensors */
-#define LSM6DSO_ODR_MIN_VAL		13000
-#define LSM6DSO_ODR_MAX_VAL \
-	MOTION_MAX_SENSOR_FREQUENCY(416000, 13000)
+#define LSM6DSO_ODR_MIN_VAL 13000
+#define LSM6DSO_ODR_MAX_VAL MOTION_MAX_SENSOR_FREQUENCY(416000, 13000)
 
 #endif /* __CROS_EC_ACCELGYRO_LSM6DSO_PUBLIC_H */
diff --git a/include/driver/als_tcs3400.h b/include/driver/als_tcs3400.h
index 0748befa71..ab28d7e7d5 100644
--- a/include/driver/als_tcs3400.h
+++ b/include/driver/als_tcs3400.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,70 +11,69 @@
 #include "driver/als_tcs3400_public.h"
 
 /* ID for TCS34001 and TCS34005 */
-#define TCS340015_DEVICE_ID	0x90
+#define TCS340015_DEVICE_ID 0x90
 
 /* ID for TCS34003 and TCS34007 */
-#define TCS340037_DEVICE_ID	0x93
+#define TCS340037_DEVICE_ID 0x93
 
 /* Register Map */
-#define TCS_I2C_ENABLE    0x80    /* R/W Enables states and interrupts */
-#define TCS_I2C_ATIME     0x81    /* R/W RGBC integration time */
-#define TCS_I2C_WTIME     0x83    /* R/W Wait time */
-#define TCS_I2C_AILTL     0x84    /* R/W Clear irq low threshold low byte */
-#define TCS_I2C_AILTH     0x85    /* R/W Clear irq low threshold high byte */
-#define TCS_I2C_AIHTL     0x86    /* R/W Clear irq high threshold low byte */
-#define TCS_I2C_AIHTH     0x87    /* R/W Clear irq high threshold high byte */
-#define TCS_I2C_PERS      0x8C    /* R/W Interrupt persistence filter */
-#define TCS_I2C_CONFIG    0x8D    /* R/W Configuration */
-#define TCS_I2C_CONTROL   0x8F    /* R/W Gain control register */
-#define TCS_I2C_AUX       0x90    /* R/W Auxiliary control register */
-#define TCS_I2C_REVID     0x91    /* R Revision ID */
-#define TCS_I2C_ID        0x92    /* R Device ID */
-#define TCS_I2C_STATUS    0x93    /* R Device status */
-#define TCS_I2C_CDATAL    0x94    /* R Clear / IR channel low data register */
-#define TCS_I2C_CDATAH    0x95    /* R Clear / IR channel high data register */
-#define TCS_I2C_RDATAL    0x96    /* R Red ADC low data register */
-#define TCS_I2C_RDATAH    0x97    /* R Red ADC high data register */
-#define TCS_I2C_GDATAL    0x98    /* R Green ADC low data register */
-#define TCS_I2C_GDATAH    0x99    /* R Green ADC high data register */
-#define TCS_I2C_BDATAL    0x9A    /* R Blue ADC low data register */
-#define TCS_I2C_BDATAH    0x9B    /* R Blue ADC high data register */
-#define TCS_I2C_IR        0xC0    /* R/W Access IR Channel */
-#define TCS_I2C_IFORCE    0xE4    /* W Force Interrupt */
-#define TCS_I2C_CICLEAR   0xE6    /* W Clear channel interrupt clear */
-#define TCS_I2C_AICLEAR   0xE7    /* W Clear all interrupts */
-
-#define TCS_I2C_ENABLE_POWER_ON             BIT(0)
-#define TCS_I2C_ENABLE_ADC_ENABLE           BIT(1)
-#define TCS_I2C_ENABLE_WAIT_ENABLE          BIT(3)
-#define TCS_I2C_ENABLE_INT_ENABLE           BIT(4)
-#define TCS_I2C_ENABLE_SLEEP_AFTER_INT      BIT(6)
-#define TCS_I2C_ENABLE_MASK                 (TCS_I2C_ENABLE_POWER_ON |    \
-					     TCS_I2C_ENABLE_ADC_ENABLE |  \
-					     TCS_I2C_ENABLE_WAIT_ENABLE | \
-					     TCS_I2C_ENABLE_INT_ENABLE |  \
-					     TCS_I2C_ENABLE_SLEEP_AFTER_INT)
+#define TCS_I2C_ENABLE 0x80 /* R/W Enables states and interrupts */
+#define TCS_I2C_ATIME 0x81 /* R/W RGBC integration time */
+#define TCS_I2C_WTIME 0x83 /* R/W Wait time */
+#define TCS_I2C_AILTL 0x84 /* R/W Clear irq low threshold low byte */
+#define TCS_I2C_AILTH 0x85 /* R/W Clear irq low threshold high byte */
+#define TCS_I2C_AIHTL 0x86 /* R/W Clear irq high threshold low byte */
+#define TCS_I2C_AIHTH 0x87 /* R/W Clear irq high threshold high byte */
+#define TCS_I2C_PERS 0x8C /* R/W Interrupt persistence filter */
+#define TCS_I2C_CONFIG 0x8D /* R/W Configuration */
+#define TCS_I2C_CONTROL 0x8F /* R/W Gain control register */
+#define TCS_I2C_AUX 0x90 /* R/W Auxiliary control register */
+#define TCS_I2C_REVID 0x91 /* R Revision ID */
+#define TCS_I2C_ID 0x92 /* R Device ID */
+#define TCS_I2C_STATUS 0x93 /* R Device status */
+#define TCS_I2C_CDATAL 0x94 /* R Clear / IR channel low data register */
+#define TCS_I2C_CDATAH 0x95 /* R Clear / IR channel high data register */
+#define TCS_I2C_RDATAL 0x96 /* R Red ADC low data register */
+#define TCS_I2C_RDATAH 0x97 /* R Red ADC high data register */
+#define TCS_I2C_GDATAL 0x98 /* R Green ADC low data register */
+#define TCS_I2C_GDATAH 0x99 /* R Green ADC high data register */
+#define TCS_I2C_BDATAL 0x9A /* R Blue ADC low data register */
+#define TCS_I2C_BDATAH 0x9B /* R Blue ADC high data register */
+#define TCS_I2C_IR 0xC0 /* R/W Access IR Channel */
+#define TCS_I2C_IFORCE 0xE4 /* W Force Interrupt */
+#define TCS_I2C_CICLEAR 0xE6 /* W Clear channel interrupt clear */
+#define TCS_I2C_AICLEAR 0xE7 /* W Clear all interrupts */
+
+#define TCS_I2C_ENABLE_POWER_ON BIT(0)
+#define TCS_I2C_ENABLE_ADC_ENABLE BIT(1)
+#define TCS_I2C_ENABLE_WAIT_ENABLE BIT(3)
+#define TCS_I2C_ENABLE_INT_ENABLE BIT(4)
+#define TCS_I2C_ENABLE_SLEEP_AFTER_INT BIT(6)
+#define TCS_I2C_ENABLE_MASK                                       \
+	(TCS_I2C_ENABLE_POWER_ON | TCS_I2C_ENABLE_ADC_ENABLE |    \
+	 TCS_I2C_ENABLE_WAIT_ENABLE | TCS_I2C_ENABLE_INT_ENABLE | \
+	 TCS_I2C_ENABLE_SLEEP_AFTER_INT)
 
 enum tcs3400_mode {
 	TCS3400_MODE_SUSPEND = 0,
-	TCS3400_MODE_IDLE =       (TCS_I2C_ENABLE_POWER_ON |
-				   TCS_I2C_ENABLE_ADC_ENABLE),
-	TCS3400_MODE_COLLECTING = (TCS_I2C_ENABLE_POWER_ON |
-				   TCS_I2C_ENABLE_ADC_ENABLE |
-				   TCS_I2C_ENABLE_INT_ENABLE),
+	TCS3400_MODE_IDLE =
+		(TCS_I2C_ENABLE_POWER_ON | TCS_I2C_ENABLE_ADC_ENABLE),
+	TCS3400_MODE_COLLECTING =
+		(TCS_I2C_ENABLE_POWER_ON | TCS_I2C_ENABLE_ADC_ENABLE |
+		 TCS_I2C_ENABLE_INT_ENABLE),
 };
 
-#define TCS_I2C_CONTROL_MASK                0x03
-#define TCS_I2C_STATUS_RGBC_VALID           BIT(0)
-#define TCS_I2C_STATUS_ALS_IRQ              BIT(4)
-#define TCS_I2C_STATUS_ALS_SATURATED        BIT(7)
+#define TCS_I2C_CONTROL_MASK 0x03
+#define TCS_I2C_STATUS_RGBC_VALID BIT(0)
+#define TCS_I2C_STATUS_ALS_IRQ BIT(4)
+#define TCS_I2C_STATUS_ALS_SATURATED BIT(7)
 
-#define TCS_I2C_AUX_ASL_INT_ENABLE          BIT(5)
+#define TCS_I2C_AUX_ASL_INT_ENABLE BIT(5)
 
 /* Light data resides at 0x94 thru 0x98 */
-#define TCS_DATA_START_LOCATION             TCS_I2C_CDATAL
-#define TCS_CLEAR_DATA_SIZE                 2
-#define TCS_RGBC_DATA_SIZE                  8
+#define TCS_DATA_START_LOCATION TCS_I2C_CDATAL
+#define TCS_CLEAR_DATA_SIZE 2
+#define TCS_RGBC_DATA_SIZE 8
 
 #define TCS3400_DRV_DATA(_s) ((struct als_drv_data_t *)(_s)->drv_data)
 #define TCS3400_RGB_DRV_DATA(_s) \
@@ -96,20 +95,20 @@ enum tcs3400_mode {
  * To avoid this, we require value to be <= 20% of saturation level
  * (TCS_GAIN_SAT_LEVEL) before allowing gain to be increased.
  */
-#define TCS_GAIN_ADJUST_FACTOR   5
-#define TCS_GAIN_SAT_LEVEL       (TCS_SATURATION_LEVEL / TCS_GAIN_ADJUST_FACTOR)
-#define TCS_UPSHIFT_FACTOR_N     25 /* upshift factor = 2.5 */
-#define TCS_UPSHIFT_FACTOR_D     10
-#define TCS_GAIN_UPSHIFT_LEVEL   (TCS_SATURATION_LEVEL * TCS_UPSHIFT_FACTOR_D \
-							/ TCS_UPSHIFT_FACTOR_N)
+#define TCS_GAIN_ADJUST_FACTOR 5
+#define TCS_GAIN_SAT_LEVEL (TCS_SATURATION_LEVEL / TCS_GAIN_ADJUST_FACTOR)
+#define TCS_UPSHIFT_FACTOR_N 25 /* upshift factor = 2.5 */
+#define TCS_UPSHIFT_FACTOR_D 10
+#define TCS_GAIN_UPSHIFT_LEVEL \
+	(TCS_SATURATION_LEVEL * TCS_UPSHIFT_FACTOR_D / TCS_UPSHIFT_FACTOR_N)
 
 /*
  * Percentage of saturation level that the auto-adjusting anti-saturation
  * method will drive towards.
  */
 #define TSC_SATURATION_LOW_BAND_PERCENT 90
-#define TSC_SATURATION_LOW_BAND_LEVEL   (TCS_SATURATION_LEVEL * \
-					 TSC_SATURATION_LOW_BAND_PERCENT / 100)
+#define TSC_SATURATION_LOW_BAND_LEVEL \
+	(TCS_SATURATION_LEVEL * TSC_SATURATION_LOW_BAND_PERCENT / 100)
 
 enum crbg_index {
 	CLEAR_CRGB_IDX = 0,
@@ -134,9 +133,9 @@ enum crbg_index {
  *     tcs3400-int = &als_clear;
  * };
  */
-#define CONFIG_ALS_TCS3400_INT_EVENT	\
+#define CONFIG_ALS_TCS3400_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(SENSOR_ID(DT_ALIAS(tcs3400_int)))
 #endif
-#endif  /* CONFIG_ZEPHYR */
+#endif /* CONFIG_ZEPHYR */
 
 #endif /* __CROS_EC_ALS_TCS3400_H */
diff --git a/include/driver/als_tcs3400_public.h b/include/driver/als_tcs3400_public.h
index 812aeda8d3..2cf9aed45f 100644
--- a/include/driver/als_tcs3400_public.h
+++ b/include/driver/als_tcs3400_public.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,34 +11,34 @@
 #include "accelgyro.h"
 
 /* I2C Interface */
-#define TCS3400_I2C_ADDR_FLAGS	0x39
+#define TCS3400_I2C_ADDR_FLAGS 0x39
 
 /* NOTE: The higher the ATIME value in reg, the shorter the accumulation time */
-#define TCS_MIN_ATIME           0x00            /* 712 ms */
-#define TCS_MAX_ATIME           0x70            /* 400 ms */
-#define TCS_ATIME_GRANULARITY   256             /* 256 atime settings */
-#define TCS_SATURATION_LEVEL    0xffff          /* for 0 < atime < 0x70 */
-#define TCS_DEFAULT_ATIME       TCS_MIN_ATIME   /* 712 ms */
-#define TCS_CALIBRATION_ATIME   TCS_MIN_ATIME
-#define TCS_GAIN_UPSHIFT_ATIME  TCS_MAX_ATIME
+#define TCS_MIN_ATIME 0x00 /* 712 ms */
+#define TCS_MAX_ATIME 0x70 /* 400 ms */
+#define TCS_ATIME_GRANULARITY 256 /* 256 atime settings */
+#define TCS_SATURATION_LEVEL 0xffff /* for 0 < atime < 0x70 */
+#define TCS_DEFAULT_ATIME TCS_MIN_ATIME /* 712 ms */
+#define TCS_CALIBRATION_ATIME TCS_MIN_ATIME
+#define TCS_GAIN_UPSHIFT_ATIME TCS_MAX_ATIME
 
 /* Number of different ranges supported for atime adjustment support */
-#define TCS_MAX_ATIME_RANGES    13
-#define TCS_GAIN_TABLE_MAX_LUX  12999
-#define TCS_ATIME_GAIN_FACTOR   100     /* table values are 100x actual value */
+#define TCS_MAX_ATIME_RANGES 13
+#define TCS_GAIN_TABLE_MAX_LUX 12999
+#define TCS_ATIME_GAIN_FACTOR 100 /* table values are 100x actual value */
 
-#define TCS_MIN_AGAIN           0x00            /* 1x gain */
-#define TCS_MAX_AGAIN           0x03            /* 64x gain */
-#define TCS_CALIBRATION_AGAIN   0x02            /* 16x gain */
-#define TCS_DEFAULT_AGAIN       TCS_CALIBRATION_AGAIN
+#define TCS_MIN_AGAIN 0x00 /* 1x gain */
+#define TCS_MAX_AGAIN 0x03 /* 64x gain */
+#define TCS_CALIBRATION_AGAIN 0x02 /* 16x gain */
+#define TCS_DEFAULT_AGAIN TCS_CALIBRATION_AGAIN
 
 #define TCS_MAX_INTEGRATION_TIME 2780 /* 2780us */
-#define TCS_ATIME_DEC_STEP      5
-#define TCS_ATIME_INC_STEP      TCS_GAIN_UPSHIFT_ATIME
+#define TCS_ATIME_DEC_STEP 5
+#define TCS_ATIME_INC_STEP TCS_GAIN_UPSHIFT_ATIME
 
 /* Min and Max sampling frequency in mHz */
-#define TCS3400_LIGHT_MIN_FREQ              149
-#define TCS3400_LIGHT_MAX_FREQ              1000
+#define TCS3400_LIGHT_MIN_FREQ 149
+#define TCS3400_LIGHT_MAX_FREQ 1000
 #if (CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ <= TCS3400_LIGHT_MAX_FREQ)
 #error "EC too slow for light sensor"
 #endif
@@ -55,15 +55,16 @@ struct tcs_saturation_t {
 	uint8_t again;
 
 	/* Acquisition Time, controlled by the ATIME register */
-	uint8_t atime;             /* ATIME register setting */
+	uint8_t atime; /* ATIME register setting */
 };
 
 /* tcs3400 rgb als driver data */
 struct tcs3400_rgb_drv_data_t {
-	uint8_t calibration_mode;/* 0 = normal run mode, 1 = calibration mode */
+	uint8_t calibration_mode; /* 0 = normal run mode, 1 = calibration mode
+				   */
 
 	struct rgb_calibration_t calibration;
-	struct tcs_saturation_t saturation;  /* saturation adjustment */
+	struct tcs_saturation_t saturation; /* saturation adjustment */
 };
 
 extern const struct accelgyro_drv tcs3400_drv;
diff --git a/include/driver/amd_stt.h b/include/driver/amd_stt.h
index 3d382a6c0a..124b13fb00 100644
--- a/include/driver/amd_stt.h
+++ b/include/driver/amd_stt.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/driver/bc12/mt6360_public.h b/include/driver/bc12/mt6360_public.h
index d2b8499e1f..fbceb74dd6 100644
--- a/include/driver/bc12/mt6360_public.h
+++ b/include/driver/bc12/mt6360_public.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/driver/bc12/pi3usb9201_public.h b/include/driver/bc12/pi3usb9201_public.h
index 643952ab4a..20788aa5e3 100644
--- a/include/driver/bc12/pi3usb9201_public.h
+++ b/include/driver/bc12/pi3usb9201_public.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/driver/charger/isl923x_public.h b/include/driver/charger/isl923x_public.h
index 2ee5f62cdb..c5d38f75c7 100644
--- a/include/driver/charger/isl923x_public.h
+++ b/include/driver/charger/isl923x_public.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,7 +11,7 @@
 #include "common.h"
 #include "stdbool.h"
 
-#define ISL923X_ADDR_FLAGS	(0x09)
+#define ISL923X_ADDR_FLAGS (0x09)
 
 extern const struct charger_drv isl923x_drv;
 
diff --git a/include/driver/charger/isl9241_public.h b/include/driver/charger/isl9241_public.h
index 342f627bd3..be586f39c3 100644
--- a/include/driver/charger/isl9241_public.h
+++ b/include/driver/charger/isl9241_public.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,10 +8,10 @@
 #ifndef __CROS_EC_DRIVER_CHARGER_ISL9241_PUBLIC_H
 #define __CROS_EC_DRIVER_CHARGER_ISL9241_PUBLIC_H
 
-#define ISL9241_ADDR_FLAGS	0x09
+#define ISL9241_ADDR_FLAGS 0x09
 
 /* Default minimum VIN voltage controlled by ISL9241_REG_VIN_VOLTAGE */
-#define ISL9241_BC12_MIN_VOLTAGE	4096
+#define ISL9241_BC12_MIN_VOLTAGE 4096
 
 extern const struct charger_drv isl9241_drv;
 
@@ -33,9 +33,9 @@ int isl9241_set_ac_prochot(int chgnum, int ma);
  */
 int isl9241_set_dc_prochot(int chgnum, int ma);
 
-#define ISL9241_AC_PROCHOT_CURRENT_MIN  128     /* mA */
-#define ISL9241_AC_PROCHOT_CURRENT_MAX  6400    /* mA */
-#define ISL9241_DC_PROCHOT_CURRENT_MIN  256     /* mA */
-#define ISL9241_DC_PROCHOT_CURRENT_MAX  12800   /* mA */
+#define ISL9241_AC_PROCHOT_CURRENT_MIN 128 /* mA */
+#define ISL9241_AC_PROCHOT_CURRENT_MAX 6400 /* mA */
+#define ISL9241_DC_PROCHOT_CURRENT_MIN 256 /* mA */
+#define ISL9241_DC_PROCHOT_CURRENT_MAX 12800 /* mA */
 
 #endif /* __CROS_EC_DRIVER_CHARGER_ISL9241_PUBLIC_H */
diff --git a/include/driver/ln9310.h b/include/driver/ln9310.h
index a5d3cf8922..dacdf95a91 100644
--- a/include/driver/ln9310.h
+++ b/include/driver/ln9310.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -12,192 +12,192 @@
 #include "gpio_signal.h"
 
 /* I2C address */
-#define LN9310_I2C_ADDR_0_FLAGS		0x72
-#define LN9310_I2C_ADDR_1_FLAGS		0x73
-#define LN9310_I2C_ADDR_2_FLAGS		0x53
-#define LN9310_I2C_ADDR_3_FLAGS		0x54
+#define LN9310_I2C_ADDR_0_FLAGS 0x72
+#define LN9310_I2C_ADDR_1_FLAGS 0x73
+#define LN9310_I2C_ADDR_2_FLAGS 0x53
+#define LN9310_I2C_ADDR_3_FLAGS 0x54
 
 /* Registers */
-#define LN9310_REG_CHIP_ID		0x00
-#define LN9310_CHIP_ID			0x44
-#define LN9310_REG_INT1			0x01
-#define LN9310_REG_INT1_MSK		0x02
-#define LN9310_INT1_TIMER		BIT(0)
-#define LN9310_INT1_INFET		BIT(1)
-#define LN9310_INT1_TEMP		BIT(2)
-#define LN9310_INT1_REV_CURR		BIT(3)
-#define LN9310_INT1_MODE		BIT(4)
-#define LN9310_INT1_ALARM		BIT(5)
-#define LN9310_INT1_OK			BIT(6)
-#define LN9310_INT1_FAULT		BIT(7)
-
-#define LN9310_REG_SYSGPIO_MSK		0x03
-
-#define LN9310_REG_SYS_STS		0x04
-#define LN9310_SYS_STANDBY		BIT(0)
-#define LN9310_SYS_SWITCHING21_ACTIVE	BIT(1)
-#define LN9310_SYS_SWITCHING31_ACTIVE	BIT(2)
-#define LN9310_SYS_BYPASS_ACTIVE	BIT(3)
-#define LN9310_SYS_INFET_OK		BIT(4)
-#define LN9310_SYS_SC_OUT_SWITCH_OK	BIT(5)
-#define LN9310_SYS_INFET_OUT_SWITCH_OK	BIT(6)
-
-#define LN9310_REG_SAFETY_STS		0x05
-#define LN9310_REG_FAULT1_STS		0x06
-#define LN9310_REG_FAULT2_STS		0x07
-
-#define LN9310_REG_PWR_CTRL		0x1d
-#define LN9310_PWR_OP_MODE0		BIT(0)
-#define LN9310_PWR_OP_MODE1		BIT(1)
-#define LN9310_PWR_INFET_EN		BIT(2)
-#define LN9310_PWR_INFET_AUTO_MODE	BIT(3)
-#define LN9310_PWR_REVERSE_MODE		BIT(4)
-#define LN9310_PWR_VIN_OV_IGNORE	BIT(5)
-#define LN9310_PWR_OP_MANUAL_UPDATE	BIT(6)
-#define LN9310_PWR_FORCE_INSNS_EN	BIT(7)
-#define LN9310_PWR_OP_MODE_MASK		0x03
-#define LN9310_PWR_OP_MODE_DISABLED	0x00
-#define LN9310_PWR_OP_MODE_BYPASS	0x01
-#define LN9310_PWR_OP_MODE_SWITCH21	0x02
-#define LN9310_PWR_OP_MODE_SWITCH31	0x03
-#define LN9310_PWR_OP_MODE_MANUAL_UPDATE_MASK	0x40
-#define LN9310_PWR_OP_MODE_MANUAL_UPDATE_OFF	0x00
-#define LN9310_PWR_INFET_AUTO_MODE_MASK		0x08
-#define LN9310_PWR_INFET_AUTO_MODE_ON		0x08
-#define LN9310_PWR_INFET_AUTO_MODE_OFF		0x00
-
-#define LN9310_REG_SYS_CTRL		0x1e
-
-#define LN9310_REG_STARTUP_CTRL			0x1f
-#define LN9310_STARTUP_STANDBY_EN				BIT(0)
-#define LN9310_STARTUP_SELECT_EXT_5V_FOR_VDR	BIT(3)
-
-#define LN9310_REG_IIN_CTRL		0x20
-#define LN9310_REG_VIN_CTRL		0x21
-
-#define LN9310_REG_TRACK_CTRL		0x22
-#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN			BIT(7)
-#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG2		BIT(6)
-#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG1		BIT(5)
-#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG0		BIT(4)
-#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_MASK	0x80
-#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_ON		0x80
-#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_OFF		0x00
-#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG_MASK	0x70
-#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG_10V	0x10
-
-#define LN9310_REG_OCP_CTRL		0x23
-
-#define LN9310_REG_TIMER_CTRL		0x24
-#define LN9310_TIMER_OP_SELF_SYNC_EN		BIT(3)
-#define LN9310_TIMER_OP_SELF_SYNC_EN_MASK	0x08
-#define LN9310_TIMER_OP_SELF_SYNC_EN_ON		0x08
-
-#define LN9310_REG_RECOVERY_CTRL	0x25
-
-#define LN9310_REG_LB_CTRL		0x26
-#define LN9310_LB_MIN_FREQ_EN	BIT(2)
-#define LN9310_LB_DELTA_MASK	0x38
-#define LN9310_LB_DELTA_2S		0x20
-#define LN9310_LB_DELTA_3S		0x20
-
-#define LN9310_REG_SC_OUT_OV_CTRL	0x29
-#define LN9310_REG_STS_CTRL		0x2d
-
-#define LN9310_REG_MODE_CHANGE_CFG	0x2e
-#define LN9310_MODE_TM_VIN_OV_CFG0		BIT(0)
-#define LN9310_MODE_TM_VIN_OV_CFG1		BIT(1)
-#define LN9310_MODE_TM_VIN_OV_CFG2		BIT(2)
-#define LN9310_MODE_TM_SC_OUT_PRECHG_CFG0	BIT(3)
-#define LN9310_MODE_TM_SC_OUT_PRECHG_CFG1	BIT(4)
-#define LN9310_MODE_TM_TRACK_CFG0		BIT(5)
-#define LN9310_MODE_TM_TRACK_CFG1		BIT(6)
-#define LN9310_MODE_FORCE_MODE_CFG		BIT(7)
-#define LN9310_MODE_TM_TRACK_MASK		0x60
-#define LN9310_MODE_TM_TRACK_BYPASS		0x00
-#define LN9310_MODE_TM_TRACK_SWITCH21		0x20
-#define LN9310_MODE_TM_TRACK_SWITCH31		0x60
-#define LN9310_MODE_TM_SC_OUT_PRECHG_MASK	0x18
-#define LN9310_MODE_TM_SC_OUT_PRECHG_BYPASS	0x0
-#define LN9310_MODE_TM_SC_OUT_PRECHG_SWITCH21	0x08
-#define LN9310_MODE_TM_SC_OUT_PRECHG_SWITCH31	0x18
-#define LN9310_MODE_TM_VIN_OV_CFG_MASK		0x07
-#define LN9310_MODE_TM_VIN_OV_CFG_2S		0x0  /* 14V */
-#define LN9310_MODE_TM_VIN_OV_CFG_3S		0x2  /* 20V */
-
-#define LN9310_REG_SPARE_0	0x2A
-#define LN9310_SPARE_0_SW4_BEFORE_BSTH_BSTL_EN_CFG_MASK	0x40
-#define LN9310_SPARE_0_SW4_BEFORE_BSTH_BSTL_EN_CFG_ON	0x40
-#define LN9310_SPARE_0_LB_MIN_FREQ_SEL_MASK	0x10
-#define LN9310_SPARE_0_LB_MIN_FREQ_SEL_ON	0x10
-
-#define LN9310_REG_SC_DITHER_CTRL	0x2f
-
-#define LN9310_REG_LION_CTRL				0x30
-#define LN9310_LION_CTRL_MASK				0xFF
-#define LN9310_LION_CTRL_UNLOCK_AND_EN_TM	0xAA
-#define LN9310_LION_CTRL_UNLOCK				0x5B
+#define LN9310_REG_CHIP_ID 0x00
+#define LN9310_CHIP_ID 0x44
+#define LN9310_REG_INT1 0x01
+#define LN9310_REG_INT1_MSK 0x02
+#define LN9310_INT1_TIMER BIT(0)
+#define LN9310_INT1_INFET BIT(1)
+#define LN9310_INT1_TEMP BIT(2)
+#define LN9310_INT1_REV_CURR BIT(3)
+#define LN9310_INT1_MODE BIT(4)
+#define LN9310_INT1_ALARM BIT(5)
+#define LN9310_INT1_OK BIT(6)
+#define LN9310_INT1_FAULT BIT(7)
+
+#define LN9310_REG_SYSGPIO_MSK 0x03
+
+#define LN9310_REG_SYS_STS 0x04
+#define LN9310_SYS_STANDBY BIT(0)
+#define LN9310_SYS_SWITCHING21_ACTIVE BIT(1)
+#define LN9310_SYS_SWITCHING31_ACTIVE BIT(2)
+#define LN9310_SYS_BYPASS_ACTIVE BIT(3)
+#define LN9310_SYS_INFET_OK BIT(4)
+#define LN9310_SYS_SC_OUT_SWITCH_OK BIT(5)
+#define LN9310_SYS_INFET_OUT_SWITCH_OK BIT(6)
+
+#define LN9310_REG_SAFETY_STS 0x05
+#define LN9310_REG_FAULT1_STS 0x06
+#define LN9310_REG_FAULT2_STS 0x07
+
+#define LN9310_REG_PWR_CTRL 0x1d
+#define LN9310_PWR_OP_MODE0 BIT(0)
+#define LN9310_PWR_OP_MODE1 BIT(1)
+#define LN9310_PWR_INFET_EN BIT(2)
+#define LN9310_PWR_INFET_AUTO_MODE BIT(3)
+#define LN9310_PWR_REVERSE_MODE BIT(4)
+#define LN9310_PWR_VIN_OV_IGNORE BIT(5)
+#define LN9310_PWR_OP_MANUAL_UPDATE BIT(6)
+#define LN9310_PWR_FORCE_INSNS_EN BIT(7)
+#define LN9310_PWR_OP_MODE_MASK 0x03
+#define LN9310_PWR_OP_MODE_DISABLED 0x00
+#define LN9310_PWR_OP_MODE_BYPASS 0x01
+#define LN9310_PWR_OP_MODE_SWITCH21 0x02
+#define LN9310_PWR_OP_MODE_SWITCH31 0x03
+#define LN9310_PWR_OP_MODE_MANUAL_UPDATE_MASK 0x40
+#define LN9310_PWR_OP_MODE_MANUAL_UPDATE_OFF 0x00
+#define LN9310_PWR_INFET_AUTO_MODE_MASK 0x08
+#define LN9310_PWR_INFET_AUTO_MODE_ON 0x08
+#define LN9310_PWR_INFET_AUTO_MODE_OFF 0x00
+
+#define LN9310_REG_SYS_CTRL 0x1e
+
+#define LN9310_REG_STARTUP_CTRL 0x1f
+#define LN9310_STARTUP_STANDBY_EN BIT(0)
+#define LN9310_STARTUP_SELECT_EXT_5V_FOR_VDR BIT(3)
+
+#define LN9310_REG_IIN_CTRL 0x20
+#define LN9310_REG_VIN_CTRL 0x21
+
+#define LN9310_REG_TRACK_CTRL 0x22
+#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN BIT(7)
+#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG2 BIT(6)
+#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG1 BIT(5)
+#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG0 BIT(4)
+#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_MASK 0x80
+#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_ON 0x80
+#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_OFF 0x00
+#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG_MASK 0x70
+#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG_10V 0x10
+
+#define LN9310_REG_OCP_CTRL 0x23
+
+#define LN9310_REG_TIMER_CTRL 0x24
+#define LN9310_TIMER_OP_SELF_SYNC_EN BIT(3)
+#define LN9310_TIMER_OP_SELF_SYNC_EN_MASK 0x08
+#define LN9310_TIMER_OP_SELF_SYNC_EN_ON 0x08
+
+#define LN9310_REG_RECOVERY_CTRL 0x25
+
+#define LN9310_REG_LB_CTRL 0x26
+#define LN9310_LB_MIN_FREQ_EN BIT(2)
+#define LN9310_LB_DELTA_MASK 0x38
+#define LN9310_LB_DELTA_2S 0x20
+#define LN9310_LB_DELTA_3S 0x20
+
+#define LN9310_REG_SC_OUT_OV_CTRL 0x29
+#define LN9310_REG_STS_CTRL 0x2d
+
+#define LN9310_REG_MODE_CHANGE_CFG 0x2e
+#define LN9310_MODE_TM_VIN_OV_CFG0 BIT(0)
+#define LN9310_MODE_TM_VIN_OV_CFG1 BIT(1)
+#define LN9310_MODE_TM_VIN_OV_CFG2 BIT(2)
+#define LN9310_MODE_TM_SC_OUT_PRECHG_CFG0 BIT(3)
+#define LN9310_MODE_TM_SC_OUT_PRECHG_CFG1 BIT(4)
+#define LN9310_MODE_TM_TRACK_CFG0 BIT(5)
+#define LN9310_MODE_TM_TRACK_CFG1 BIT(6)
+#define LN9310_MODE_FORCE_MODE_CFG BIT(7)
+#define LN9310_MODE_TM_TRACK_MASK 0x60
+#define LN9310_MODE_TM_TRACK_BYPASS 0x00
+#define LN9310_MODE_TM_TRACK_SWITCH21 0x20
+#define LN9310_MODE_TM_TRACK_SWITCH31 0x60
+#define LN9310_MODE_TM_SC_OUT_PRECHG_MASK 0x18
+#define LN9310_MODE_TM_SC_OUT_PRECHG_BYPASS 0x0
+#define LN9310_MODE_TM_SC_OUT_PRECHG_SWITCH21 0x08
+#define LN9310_MODE_TM_SC_OUT_PRECHG_SWITCH31 0x18
+#define LN9310_MODE_TM_VIN_OV_CFG_MASK 0x07
+#define LN9310_MODE_TM_VIN_OV_CFG_2S 0x0 /* 14V */
+#define LN9310_MODE_TM_VIN_OV_CFG_3S 0x2 /* 20V */
+
+#define LN9310_REG_SPARE_0 0x2A
+#define LN9310_SPARE_0_SW4_BEFORE_BSTH_BSTL_EN_CFG_MASK 0x40
+#define LN9310_SPARE_0_SW4_BEFORE_BSTH_BSTL_EN_CFG_ON 0x40
+#define LN9310_SPARE_0_LB_MIN_FREQ_SEL_MASK 0x10
+#define LN9310_SPARE_0_LB_MIN_FREQ_SEL_ON 0x10
+
+#define LN9310_REG_SC_DITHER_CTRL 0x2f
+
+#define LN9310_REG_LION_CTRL 0x30
+#define LN9310_LION_CTRL_MASK 0xFF
+#define LN9310_LION_CTRL_UNLOCK_AND_EN_TM 0xAA
+#define LN9310_LION_CTRL_UNLOCK 0x5B
 /*
  * value changed to 0x22 to distinguish from reset value of 0x00
  * 0x22 and 0x00 are functionally equivalent within LN9310
  */
-#define LN9310_LION_CTRL_LOCK				0x22
-
-#define LN9310_REG_CFG_0	0x3C
-#define LN9310_CFG_0_LS_HELPER_IDLE_MSK_MASK	0x20
-#define LN9310_CFG_0_LS_HELPER_IDLE_MSK_ON		0x20
-
-#define LN9310_REG_CFG_4	0x40
-#define LN9310_CFG_4_SC_OUT_PRECHARGE_EN_TIME_CFG		BIT(2)
-#define LN9310_CFG_4_SW1_VGS_SHORT_EN_MSK				BIT(3)
-#define LN9310_CFG_4_SC_OUT_PRECHARGE_EN_TIME_CFG_MASK 	0x04
-#define LN9310_CFG_4_SW1_VGS_SHORT_EN_MSK_MASK			0x08
-#define LN9310_CFG_4_BSTH_BSTL_HIGH_ROUT_CFG_MASK		0xC0
-#define LN9310_CFG_4_SC_OUT_PRECHARGE_EN_TIME_CFG_ON 	0x04
-#define LN9310_CFG_4_SW1_VGS_SHORT_EN_MSK_OFF			0x00
-#define LN9310_CFG_4_BSTH_BSTL_HIGH_ROUT_CFG_LOWEST		0x00
-
-#define LN9310_REG_CFG_5	0x41
-#define LN9310_CFG_5_INGATE_PD_EN_MASK		0xC0
-#define LN9310_CFG_5_INGATE_PD_EN_OFF		0x00
-#define LN9310_CFG_5_INFET_CP_PD_BIAS_CFG_MASK		0x30
-#define LN9310_CFG_5_INFET_CP_PD_BIAS_CFG_LOWEST	0x00
-
-#define LN9310_REG_TEST_MODE_CTRL	0x46
-#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_MASK		0x40
-#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_ON			0x40
-#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_OFF		0x00
-#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_MASK	0x20
-#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_ON		0x20
-#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_OFF		0x00
-
-#define LN9310_REG_FORCE_SC21_CTRL_1	0x49
-#define LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_MASK	0xFF
-#define LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_ON	0x59
-#define LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_OFF	0x40
-
-#define LN9310_REG_FORCE_SC21_CTRL_2	0x4A
-#define LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_MASK		0x80
-#define LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_ON		0x80
-#define LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_OFF		0x00
-
-#define LN9310_REG_SWAP_CTRL_0	0x58
-#define LN9310_REG_SWAP_CTRL_1	0x59
-#define LN9310_REG_SWAP_CTRL_2	0x5A
-#define LN9310_REG_SWAP_CTRL_3	0x5B
-
-#define LN9310_REG_BC_STS_B		0x51
-#define LN9310_BC_STS_B_INFET_OUT_SWITCH_OK		BIT(5)
-#define LN9310_BC_STS_B_INFET_OUT_SWITCH_OK_MASK	0x20
-
-#define LN9310_REG_BC_STS_C				0x52
-#define LN9310_BC_STS_C_CHIP_REV_MASK	0xF0
-#define LN9310_BC_STS_C_CHIP_REV_FIXED	0x40
+#define LN9310_LION_CTRL_LOCK 0x22
+
+#define LN9310_REG_CFG_0 0x3C
+#define LN9310_CFG_0_LS_HELPER_IDLE_MSK_MASK 0x20
+#define LN9310_CFG_0_LS_HELPER_IDLE_MSK_ON 0x20
+
+#define LN9310_REG_CFG_4 0x40
+#define LN9310_CFG_4_SC_OUT_PRECHARGE_EN_TIME_CFG BIT(2)
+#define LN9310_CFG_4_SW1_VGS_SHORT_EN_MSK BIT(3)
+#define LN9310_CFG_4_SC_OUT_PRECHARGE_EN_TIME_CFG_MASK 0x04
+#define LN9310_CFG_4_SW1_VGS_SHORT_EN_MSK_MASK 0x08
+#define LN9310_CFG_4_BSTH_BSTL_HIGH_ROUT_CFG_MASK 0xC0
+#define LN9310_CFG_4_SC_OUT_PRECHARGE_EN_TIME_CFG_ON 0x04
+#define LN9310_CFG_4_SW1_VGS_SHORT_EN_MSK_OFF 0x00
+#define LN9310_CFG_4_BSTH_BSTL_HIGH_ROUT_CFG_LOWEST 0x00
+
+#define LN9310_REG_CFG_5 0x41
+#define LN9310_CFG_5_INGATE_PD_EN_MASK 0xC0
+#define LN9310_CFG_5_INGATE_PD_EN_OFF 0x00
+#define LN9310_CFG_5_INFET_CP_PD_BIAS_CFG_MASK 0x30
+#define LN9310_CFG_5_INFET_CP_PD_BIAS_CFG_LOWEST 0x00
+
+#define LN9310_REG_TEST_MODE_CTRL 0x46
+#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_MASK 0x40
+#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_ON 0x40
+#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_OFF 0x00
+#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_MASK 0x20
+#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_ON 0x20
+#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_OFF 0x00
+
+#define LN9310_REG_FORCE_SC21_CTRL_1 0x49
+#define LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_MASK 0xFF
+#define LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_ON 0x59
+#define LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_OFF 0x40
+
+#define LN9310_REG_FORCE_SC21_CTRL_2 0x4A
+#define LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_MASK 0x80
+#define LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_ON 0x80
+#define LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_OFF 0x00
+
+#define LN9310_REG_SWAP_CTRL_0 0x58
+#define LN9310_REG_SWAP_CTRL_1 0x59
+#define LN9310_REG_SWAP_CTRL_2 0x5A
+#define LN9310_REG_SWAP_CTRL_3 0x5B
+
+#define LN9310_REG_BC_STS_B 0x51
+#define LN9310_BC_STS_B_INFET_OUT_SWITCH_OK BIT(5)
+#define LN9310_BC_STS_B_INFET_OUT_SWITCH_OK_MASK 0x20
+
+#define LN9310_REG_BC_STS_C 0x52
+#define LN9310_BC_STS_C_CHIP_REV_MASK 0xF0
+#define LN9310_BC_STS_C_CHIP_REV_FIXED 0x40
 
 /* LN9310 Timing definition */
-#define LN9310_CDC_DELAY 				120	/* 120us */
-#define LN9310_CFLY_PRECHARGE_DELAY 	(12*MSEC)
-#define LN9310_CFLY_PRECHARGE_TIMEOUT	(100*MSEC)
+#define LN9310_CDC_DELAY 120 /* 120us */
+#define LN9310_CFLY_PRECHARGE_DELAY (12 * MSEC)
+#define LN9310_CFLY_PRECHARGE_TIMEOUT (100 * MSEC)
 
 /* LN9310 Driver Configuration */
 #define LN9310_INIT_RETRY_COUNT 3
diff --git a/include/driver/mag_bmm150.h b/include/driver/mag_bmm150.h
index 9f517f8097..0325e6c5fc 100644
--- a/include/driver/mag_bmm150.h
+++ b/include/driver/mag_bmm150.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,68 +11,68 @@
 #include "accelgyro.h"
 #include "mag_cal.h"
 
-#define BMM150_ADDR0_FLAGS       0x10
-#define BMM150_ADDR1_FLAGS       0x11
-#define BMM150_ADDR2_FLAGS       0x12
-#define BMM150_ADDR3_FLAGS       0x13
-
-#define BMM150_CHIP_ID           0x40
-#define BMM150_CHIP_ID_MAJOR     0x32
-
-#define BMM150_BASE_DATA         0x42
-
-#define BMM150_INT_STATUS        0x4a
-#define BMM150_PWR_CTRL          0x4b
-#define BMM150_SRST                  (BIT(7) | BIT(1))
-#define BMM150_PWR_ON                BIT(0)
-
-#define BMM150_OP_CTRL           0x4c
-#define BMM150_OP_MODE_OFFSET    1
-#define BMM150_OP_MODE_MASK      3
-#define BMM150_OP_MODE_NORMAL    0x00
-#define BMM150_OP_MODE_FORCED    0x01
-#define BMM150_OP_MODE_SLEEP     0x03
-
-#define BMM150_INT_CTRL          0x4d
-
-#define BMM150_REPXY             0x51
-#define BMM150_LOW_POWER_nXY         3
-#define BMM150_REGULAR_nXY           9
-#define BMM150_ENHANCED_nXY         15
-#define BMM150_HIGH_ACCURACY_nXY    47
-#define BMM150_SPECIAL_nXY          75
-#define BMM150_REPZ              0x52
-#define BMM150_LOW_POWER_nZ          3
-#define BMM150_REGULAR_nZ           15
-#define BMM150_ENHANCED_nZ          27
-#define BMM150_HIGH_ACCURACY_nZ     83
-#define BMM150_SPECIAL_nZ           27
+#define BMM150_ADDR0_FLAGS 0x10
+#define BMM150_ADDR1_FLAGS 0x11
+#define BMM150_ADDR2_FLAGS 0x12
+#define BMM150_ADDR3_FLAGS 0x13
+
+#define BMM150_CHIP_ID 0x40
+#define BMM150_CHIP_ID_MAJOR 0x32
+
+#define BMM150_BASE_DATA 0x42
+
+#define BMM150_INT_STATUS 0x4a
+#define BMM150_PWR_CTRL 0x4b
+#define BMM150_SRST (BIT(7) | BIT(1))
+#define BMM150_PWR_ON BIT(0)
+
+#define BMM150_OP_CTRL 0x4c
+#define BMM150_OP_MODE_OFFSET 1
+#define BMM150_OP_MODE_MASK 3
+#define BMM150_OP_MODE_NORMAL 0x00
+#define BMM150_OP_MODE_FORCED 0x01
+#define BMM150_OP_MODE_SLEEP 0x03
+
+#define BMM150_INT_CTRL 0x4d
+
+#define BMM150_REPXY 0x51
+#define BMM150_LOW_POWER_nXY 3
+#define BMM150_REGULAR_nXY 9
+#define BMM150_ENHANCED_nXY 15
+#define BMM150_HIGH_ACCURACY_nXY 47
+#define BMM150_SPECIAL_nXY 75
+#define BMM150_REPZ 0x52
+#define BMM150_LOW_POWER_nZ 3
+#define BMM150_REGULAR_nZ 15
+#define BMM150_ENHANCED_nZ 27
+#define BMM150_HIGH_ACCURACY_nZ 83
+#define BMM150_SPECIAL_nZ 27
 
 #define BMM150_REP(_preset, _axis) CONCAT4(BMM150_, _preset, _n, _axis)
 
 /* Hidden registers for RHALL calculation */
-#define BMM150_REGA_DIG_X1       0x5d
-#define BMM150_REGA_DIG_Y1       0x5e
-#define BMM150_REGA_DIG_Z4_LSB   0x62
-#define BMM150_REGA_DIG_Z4_MSB   0x63
-#define BMM150_REGA_DIG_X2       0x64
-#define BMM150_REGA_DIG_Y2       0x65
-#define BMM150_REGA_DIG_Z2_LSB   0x68
-#define BMM150_REGA_DIG_Z2_MSB   0x69
-#define BMM150_REGA_DIG_Z1_LSB   0x6a
-#define BMM150_REGA_DIG_Z1_MSB   0x6b
+#define BMM150_REGA_DIG_X1 0x5d
+#define BMM150_REGA_DIG_Y1 0x5e
+#define BMM150_REGA_DIG_Z4_LSB 0x62
+#define BMM150_REGA_DIG_Z4_MSB 0x63
+#define BMM150_REGA_DIG_X2 0x64
+#define BMM150_REGA_DIG_Y2 0x65
+#define BMM150_REGA_DIG_Z2_LSB 0x68
+#define BMM150_REGA_DIG_Z2_MSB 0x69
+#define BMM150_REGA_DIG_Z1_LSB 0x6a
+#define BMM150_REGA_DIG_Z1_MSB 0x6b
 #define BMM150_REGA_DIG_XYZ1_LSB 0x6c
 #define BMM150_REGA_DIG_XYZ1_MSB 0x6d
-#define BMM150_REGA_DIG_Z3_LSB   0x6e
-#define BMM150_REGA_DIG_Z3_MSB   0x6f
-#define BMM150_REGA_DIG_XY2      0x70
-#define BMM150_REGA_DIG_XY1      0x71
+#define BMM150_REGA_DIG_Z3_LSB 0x6e
+#define BMM150_REGA_DIG_Z3_MSB 0x6f
+#define BMM150_REGA_DIG_XY2 0x70
+#define BMM150_REGA_DIG_XY1 0x71
 
 /* Overflow */
 
-#define BMM150_FLIP_OVERFLOW_ADCVAL             (-4096)
-#define BMM150_HALL_OVERFLOW_ADCVAL             (-16384)
-#define BMM150_OVERFLOW_OUTPUT                  (0x8000)
+#define BMM150_FLIP_OVERFLOW_ADCVAL (-4096)
+#define BMM150_HALL_OVERFLOW_ADCVAL (-16384)
+#define BMM150_OVERFLOW_OUTPUT (0x8000)
 
 /* Min and Max sampling frequency in mHz */
 #define BMM150_MAG_MIN_FREQ 781
@@ -84,8 +84,9 @@
  *
  *  To be safe, declare only 75% of the value.
  */
-#define __BMM150_MAG_MAX_FREQ(_preset) (750000000 / \
-	(145 * BMM150_REP(_preset, XY) + 500 *  BMM150_REP(_preset, Z) + 980))
+#define __BMM150_MAG_MAX_FREQ(_preset) \
+	(750000000 /                   \
+	 (145 * BMM150_REP(_preset, XY) + 500 * BMM150_REP(_preset, Z) + 980))
 
 #if (__BMM150_MAG_MAX_FREQ(SPECIAL) > CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ)
 #error "EC too slow for magnetometer"
@@ -93,34 +94,32 @@
 
 struct bmm150_comp_registers {
 	/* Local copy of the compensation registers. */
-	int8_t       dig1[2];
-	int8_t       dig2[2];
+	int8_t dig1[2];
+	int8_t dig2[2];
 
-	uint16_t     dig_z1;
-	int16_t      dig_z2;
-	int16_t      dig_z3;
-	int16_t      dig_z4;
+	uint16_t dig_z1;
+	int16_t dig_z2;
+	int16_t dig_z3;
+	int16_t dig_z4;
 
-	uint8_t      dig_xy1;
-	int8_t       dig_xy2;
+	uint8_t dig_xy1;
+	int8_t dig_xy2;
 
-	uint16_t     dig_xyz1;
+	uint16_t dig_xyz1;
 };
 
 struct bmm150_private_data {
 	/* lsm6dsm_data union requires cal be first element */
-	struct mag_cal_t             cal;
+	struct mag_cal_t cal;
 	struct bmm150_comp_registers comp;
 };
 
 #ifdef CONFIG_MAG_BMI_BMM150
 #include "accelgyro_bmi_common.h"
 
-#define BMM150_COMP_REG(_s) \
-	(&BMI_GET_DATA(_s)->compass.comp)
+#define BMM150_COMP_REG(_s) (&BMI_GET_DATA(_s)->compass.comp)
 
-#define BMM150_CAL(_s) \
-	(&BMI_GET_DATA(_s)->compass.cal)
+#define BMM150_CAL(_s) (&BMI_GET_DATA(_s)->compass.cal)
 /*
  * Behind a BMI, the BMM150 is in forced mode. Be sure to choose a frequency
  * compatible with BMI.
@@ -137,14 +136,11 @@ struct bmm150_private_data {
 int bmm150_init(struct motion_sensor_t *s);
 
 /* Command to normalize and apply temperature compensation */
-void bmm150_normalize(const struct motion_sensor_t *s,
-		      intv3_t v,
+void bmm150_normalize(const struct motion_sensor_t *s, intv3_t v,
 		      uint8_t *data);
 
-int bmm150_set_offset(const struct motion_sensor_t *s,
-		      const intv3_t offset);
+int bmm150_set_offset(const struct motion_sensor_t *s, const intv3_t offset);
 
-int bmm150_get_offset(const struct motion_sensor_t *s,
-		      intv3_t   offset);
+int bmm150_get_offset(const struct motion_sensor_t *s, intv3_t offset);
 
 #endif /* __CROS_EC_MAG_BMM150_H */
diff --git a/driver/ppc/aoz1380.h b/include/driver/ppc/aoz1380_public.h
index 94f2b804b7..aa617054fe 100644
--- a/driver/ppc/aoz1380.h
+++ b/include/driver/ppc/aoz1380_public.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,8 @@
  * controlled PPC chips that are similar to the AOZ1380
  */
 
-#ifndef __CROS_EC_AOZ1380_H
-#define __CROS_EC_AOZ1380_H
+#ifndef __CROS_EC_AOZ1380_PUBLIC_H
+#define __CROS_EC_AOZ1380_PUBLIC_H
 
 #include "usb_pd_tcpm.h"
 
@@ -33,7 +33,6 @@ extern const struct ppc_drv aoz1380_drv;
 int board_aoz1380_set_vbus_source_current_limit(int port,
 						enum tcpc_rp_value rp);
 
-
 /**
  * Interrupt Handler for the AOZ1380.
  *
diff --git a/include/driver/ppc/ktu1125_public.h b/include/driver/ppc/ktu1125_public.h
index 276f8c9a99..28ecfc7c23 100644
--- a/include/driver/ppc/ktu1125_public.h
+++ b/include/driver/ppc/ktu1125_public.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/driver/ppc/nx20p348x_public.h b/include/driver/ppc/nx20p348x_public.h
new file mode 100644
index 0000000000..145896aca1
--- /dev/null
+++ b/include/driver/ppc/nx20p348x_public.h
@@ -0,0 +1,32 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* TI NX20P348X USB-C Power Path Controller */
+
+#ifndef __CROS_EC_DRIVER_PPC_NX20P348X_PUBLIC_H
+#define __CROS_EC_DRIVER_PPC_NX20P348X_PUBLIC_H
+
+#include "usbc_ppc.h"
+
+#define NX20P3483_ADDR0_FLAGS 0x70
+#define NX20P3483_ADDR1_FLAGS 0x71
+#define NX20P3483_ADDR2_FLAGS 0x72
+#define NX20P3483_ADDR3_FLAGS 0x73
+
+#define NX20P3481_ADDR0_FLAGS 0x74
+#define NX20P3481_ADDR1_FLAGS 0x75
+#define NX20P3481_ADDR2_FLAGS 0x76
+#define NX20P3481_ADDR3_FLAGS 0x77
+
+extern const struct ppc_drv nx20p348x_drv;
+
+/**
+ * Interrupt Handler for the NX20P348x.
+ *
+ * @param port: The Type-C port which triggered the interrupt.
+ */
+void nx20p348x_interrupt(int port);
+
+#endif /* __CROS_EC_DRIVER_PPC_NX20P348X_PUBLIC_H */
diff --git a/include/driver/ppc/sn5s330_public.h b/include/driver/ppc/sn5s330_public.h
index fdd60e54cb..62652d99b2 100644
--- a/include/driver/ppc/sn5s330_public.h
+++ b/include/driver/ppc/sn5s330_public.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/driver/ppc/syv682x_public.h b/include/driver/ppc/syv682x_public.h
index 92c841f811..a97d412478 100644
--- a/include/driver/ppc/syv682x_public.h
+++ b/include/driver/ppc/syv682x_public.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,10 +9,10 @@
 #define __CROS_EC_DRIVER_PPC_SYV682X_PUBLIC_H
 
 /* I2C addresses */
-#define SYV682X_ADDR0_FLAGS		0x40
-#define SYV682X_ADDR1_FLAGS		0x41
-#define SYV682X_ADDR2_FLAGS		0x42
-#define SYV682X_ADDR3_FLAGS		0x43
+#define SYV682X_ADDR0_FLAGS 0x40
+#define SYV682X_ADDR1_FLAGS 0x41
+#define SYV682X_ADDR2_FLAGS 0x42
+#define SYV682X_ADDR3_FLAGS 0x43
 
 extern const struct ppc_drv syv682x_drv;
 
diff --git a/include/driver/retimer/anx7483_public.h b/include/driver/retimer/anx7483_public.h
index 8c3b9eaf60..83ad32508e 100644
--- a/include/driver/retimer/anx7483_public.h
+++ b/include/driver/retimer/anx7483_public.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -13,10 +13,10 @@
 #include "usb_mux.h"
 
 /* I2C interface addresses */
-#define ANX7483_I2C_ADDR0_FLAGS		0x3E
-#define ANX7483_I2C_ADDR1_FLAGS		0x38
-#define ANX7483_I2C_ADDR2_FLAGS		0x40
-#define ANX7483_I2C_ADDR3_FLAGS		0x44
+#define ANX7483_I2C_ADDR0_FLAGS 0x3E
+#define ANX7483_I2C_ADDR1_FLAGS 0x38
+#define ANX7483_I2C_ADDR2_FLAGS 0x40
+#define ANX7483_I2C_ADDR3_FLAGS 0x44
 
 /* Equalization tuning */
 enum anx7483_eq_setting {
@@ -52,9 +52,11 @@ enum ec_error_list anx7483_set_eq(const struct usb_mux *me,
 				  enum anx7483_tune_pin pin,
 				  enum anx7483_eq_setting eq);
 
-/* Configure datasheet defaults for tuning registers at this mux setting */
-enum ec_error_list anx7483_set_default_tuning(const struct usb_mux *me,
-					      mux_state_t mux_state);
+/*
+ * Configure datasheet defaults for tuning registers at this mux setting.
+ * Return int so function can be used directly for board_set.
+ */
+int anx7483_set_default_tuning(const struct usb_mux *me, mux_state_t mux_state);
 
 extern const struct usb_mux_driver anx7483_usb_retimer_driver;
 #endif /* __CROS_EC_USB_RETIMER_ANX7483_PUBLIC_H */
diff --git a/include/driver/retimer/bb_retimer.h b/include/driver/retimer/bb_retimer.h
index 6a311bd2ca..460156803e 100644
--- a/include/driver/retimer/bb_retimer.h
+++ b/include/driver/retimer/bb_retimer.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -12,44 +12,44 @@
 #include "driver/retimer/bb_retimer_public.h"
 
 /* Burnside Bridge I2C Configuration Space */
-#define BB_RETIMER_REG_VENDOR_ID	0
-#define BB_RETIMER_VENDOR_ID_1          0x8086
-#define BB_RETIMER_VENDOR_ID_2          0x8087
+#define BB_RETIMER_REG_VENDOR_ID 0
+#define BB_RETIMER_VENDOR_ID_1 0x8086
+#define BB_RETIMER_VENDOR_ID_2 0x8087
 
-#define BB_RETIMER_REG_DEVICE_ID	1
-#ifdef  CONFIG_USBC_RETIMER_INTEL_HB
+#define BB_RETIMER_REG_DEVICE_ID 1
+#ifdef CONFIG_USBC_RETIMER_INTEL_HB
 /* HB has no Device ID field instead it is combined with Vendor ID */
-#define BB_RETIMER_DEVICE_ID		0x0D9C8087
+#define BB_RETIMER_DEVICE_ID 0x0D9C8087
 #else
-#define BB_RETIMER_DEVICE_ID		0x15EE
+#define BB_RETIMER_DEVICE_ID 0x15EE
 #endif
 
 /* Connection State Register Attributes */
-#define BB_RETIMER_REG_CONNECTION_STATE		4
-#define BB_RETIMER_DATA_CONNECTION_PRESENT	BIT(0)
-#define BB_RETIMER_CONNECTION_ORIENTATION	BIT(1)
-#define BB_RETIMER_RE_TIMER_DRIVER		BIT(2)
-#define BB_RETIMER_USB_2_CONNECTION		BIT(4)
-#define BB_RETIMER_USB_3_CONNECTION		BIT(5)
-#define BB_RETIMER_USB_3_SPEED			BIT(6)
-#define BB_RETIMER_USB_DATA_ROLE		BIT(7)
-#define BB_RETIMER_DP_CONNECTION		BIT(8)
-#define BB_RETIMER_DP_PIN_ASSIGNMENT		BIT(10)
-#define BB_RETIMER_IRQ_HPD			BIT(14)
-#define BB_RETIMER_HPD_LVL			BIT(15)
-#define BB_RETIMER_TBT_CONNECTION		BIT(16)
-#define BB_RETIMER_TBT_TYPE			BIT(17)
-#define BB_RETIMER_TBT_CABLE_TYPE		BIT(18)
-#define BB_RETIMER_VPRO_DOCK_DP_OVERDRIVE	BIT(19)
-#define BB_RETIMER_TBT_ACTIVE_LINK_TRAINING	BIT(20)
-#define BB_RETIMER_ACTIVE_PASSIVE		BIT(22)
-#define BB_RETIMER_USB4_ENABLED			BIT(23)
-#define BB_RETIMER_USB4_TBT_CABLE_SPEED_SUPPORT(x)	(((x) & 0x7) << 25)
-#define BB_RETIMER_TBT_CABLE_GENERATION(x)		(((x) & 0x3) << 28)
-
-#define BB_RETIMER_REG_TBT_CONTROL		5
-#define BB_RETIMER_REG_EXT_CONNECTION_MODE	6
-
-#define BB_RETIMER_REG_COUNT			7
+#define BB_RETIMER_REG_CONNECTION_STATE 4
+#define BB_RETIMER_DATA_CONNECTION_PRESENT BIT(0)
+#define BB_RETIMER_CONNECTION_ORIENTATION BIT(1)
+#define BB_RETIMER_RE_TIMER_DRIVER BIT(2)
+#define BB_RETIMER_USB_2_CONNECTION BIT(4)
+#define BB_RETIMER_USB_3_CONNECTION BIT(5)
+#define BB_RETIMER_USB_3_SPEED BIT(6)
+#define BB_RETIMER_USB_DATA_ROLE BIT(7)
+#define BB_RETIMER_DP_CONNECTION BIT(8)
+#define BB_RETIMER_DP_PIN_ASSIGNMENT BIT(10)
+#define BB_RETIMER_IRQ_HPD BIT(14)
+#define BB_RETIMER_HPD_LVL BIT(15)
+#define BB_RETIMER_TBT_CONNECTION BIT(16)
+#define BB_RETIMER_TBT_TYPE BIT(17)
+#define BB_RETIMER_TBT_CABLE_TYPE BIT(18)
+#define BB_RETIMER_VPRO_DOCK_DP_OVERDRIVE BIT(19)
+#define BB_RETIMER_TBT_ACTIVE_LINK_TRAINING BIT(20)
+#define BB_RETIMER_ACTIVE_PASSIVE BIT(22)
+#define BB_RETIMER_USB4_ENABLED BIT(23)
+#define BB_RETIMER_USB4_TBT_CABLE_SPEED_SUPPORT(x) (((x)&0x7) << 25)
+#define BB_RETIMER_TBT_CABLE_GENERATION(x) (((x)&0x3) << 28)
+
+#define BB_RETIMER_REG_TBT_CONTROL 5
+#define BB_RETIMER_REG_EXT_CONNECTION_MODE 7
+
+#define BB_RETIMER_REG_COUNT 8
 
 #endif /* __CROS_EC_BB_RETIMER_H */
diff --git a/include/driver/retimer/bb_retimer_public.h b/include/driver/retimer/bb_retimer_public.h
index d79b051504..2d2893fb49 100644
--- a/include/driver/retimer/bb_retimer_public.h
+++ b/include/driver/retimer/bb_retimer_public.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -56,4 +56,12 @@ __override_proto int bb_retimer_power_enable(const struct usb_mux *me,
 void bb_retimer_hpd_update(const struct usb_mux *me, mux_state_t mux_state,
 			   bool *ack_required);
 
+/**
+ * Enable/disable the USB3 state of BB retimer
+ *
+ * @param me     Pointer to USB mux
+ * @param enable BB retimer USB3 state to be changed
+ */
+void bb_retimer_set_usb3(const struct usb_mux *me, bool enable);
+
 #endif /* __CROS_EC_DRIVER_RETIMER_BB_RETIMER_PUBLIC_H */
diff --git a/include/driver/retimer/ps8818_public.h b/include/driver/retimer/ps8818_public.h
new file mode 100644
index 0000000000..3f0aba963b
--- /dev/null
+++ b/include/driver/retimer/ps8818_public.h
@@ -0,0 +1,96 @@
+/* Copyright 2019 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * PS8818 retimer.
+ */
+#include "usb_mux.h"
+
+#ifndef __CROS_EC_USB_RETIMER_PS8818_H
+#define __CROS_EC_USB_RETIMER_PS8818_H
+
+#define PS8818_I2C_ADDR_FLAGS 0x28
+
+/*
+ * PAGE 0 Register Definitions
+ */
+#define PS8818_REG_PAGE0 0x00
+
+#define PS8818_REG0_FLIP 0x00
+#define PS8818_FLIP_CONFIG BIT(7)
+#define PS8818_FLIP_NON_RESERVED_MASK 0xE0
+
+#define PS8818_REG0_MODE 0x01
+#define PS8818_MODE_DP_ENABLE BIT(7)
+#define PS8818_MODE_USB_ENABLE BIT(6)
+#define PS8818_MODE_NON_RESERVED_MASK 0xC0
+
+#define PS8818_REG0_DPHPD_CONFIG 0x02
+#define PS8818_DPHPD_CONFIG_INHPD_DISABLE BIT(7)
+#define PS8818_DPHPD_PLUGGED BIT(6)
+#define PS8818_DPHPD_NON_RESERVED_MASK 0xFC
+
+/*
+ * PAGE 1 Register Definitions
+ */
+#define PS8818_REG_PAGE1 0x01
+
+#define PS8818_REG1_APTX1EQ_10G_LEVEL 0x00
+#define PS8818_REG1_APTX2EQ_10G_LEVEL 0x02
+#define PS8818_REG1_CRX1EQ_10G_LEVEL 0x08
+#define PS8818_REG1_CRX2EQ_10G_LEVEL 0x0A
+#define PS8818_REG1_APRX1_DE_LEVEL 0x0C
+#define PS8818_REG1_APTX1EQ_5G_LEVEL 0x70
+#define PS8818_REG1_APTX2EQ_5G_LEVEL 0x72
+#define PS8818_REG1_CRX1EQ_5G_LEVEL 0x78
+#define PS8818_REG1_CRX2EQ_5G_LEVEL 0x7A
+#define PS8818_EQ_LEVEL_UP_9DB (0)
+#define PS8818_EQ_LEVEL_UP_10DB (1)
+#define PS8818_EQ_LEVEL_UP_12DB (2)
+#define PS8818_EQ_LEVEL_UP_13DB (3)
+#define PS8818_EQ_LEVEL_UP_16DB (4)
+#define PS8818_EQ_LEVEL_UP_17DB (5)
+#define PS8818_EQ_LEVEL_UP_18DB (6)
+#define PS8818_EQ_LEVEL_UP_19DB (7)
+#define PS8818_EQ_LEVEL_UP_20DB (8)
+#define PS8818_EQ_LEVEL_UP_21DB (9)
+#define PS8818_EQ_LEVEL_UP_MASK (0x0F)
+
+#define PS8818_REG1_RX_PHY 0x6D
+#define PS8818_RX_INPUT_TERM_112_OHM (0 << 6)
+#define PS8818_RX_INPUT_TERM_104_OHM (1 << 6)
+#define PS8818_RX_INPUT_TERM_96_OHM (2 << 6)
+#define PS8818_RX_INPUT_TERM_85_OHM (3 << 6)
+#define PS8818_RX_INPUT_TERM_MASK (3 << 6)
+
+#define PS8818_REG1_DPEQ_LEVEL 0xB6
+#define PS8818_DPEQ_LEVEL_UP_9DB (0 << 3)
+#define PS8818_DPEQ_LEVEL_UP_10DB (1 << 3)
+#define PS8818_DPEQ_LEVEL_UP_12DB (2 << 3)
+#define PS8818_DPEQ_LEVEL_UP_13DB (3 << 3)
+#define PS8818_DPEQ_LEVEL_UP_16DB (4 << 3)
+#define PS8818_DPEQ_LEVEL_UP_17DB (5 << 3)
+#define PS8818_DPEQ_LEVEL_UP_18DB (6 << 3)
+#define PS8818_DPEQ_LEVEL_UP_19DB (7 << 3)
+#define PS8818_DPEQ_LEVEL_UP_20DB (8 << 3)
+#define PS8818_DPEQ_LEVEL_UP_21DB (9 << 3)
+#define PS8818_DPEQ_LEVEL_UP_MASK (0x0F << 3)
+
+/*
+ * PAGE 2 Register Definitions
+ */
+#define PS8818_REG_PAGE2 0x02
+
+#define PS8818_REG2_TX_STATUS 0x42
+#define PS8818_REG2_RX_STATUS 0x46
+#define PS8818_STATUS_NORMAL_OPERATION BIT(7)
+#define PS8818_STATUS_10_GBPS BIT(5)
+
+extern const struct usb_mux_driver ps8818_usb_retimer_driver;
+
+int ps8818_i2c_read(const struct usb_mux *me, int page, int offset, int *data);
+int ps8818_i2c_write(const struct usb_mux *me, int page, int offset, int data);
+int ps8818_i2c_field_update8(const struct usb_mux *me, int page, int offset,
+			     uint8_t field_mask, uint8_t set_value);
+
+#endif /* __CROS_EC_USB_RETIMER_PS8818_H */
diff --git a/include/driver/tcpm/anx7447_public.h b/include/driver/tcpm/anx7447_public.h
new file mode 100644
index 0000000000..5ea1eebd35
--- /dev/null
+++ b/include/driver/tcpm/anx7447_public.h
@@ -0,0 +1,28 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Analogix Type-C port controller */
+
+#ifndef __CROS_EC_DRIVER_TCPM_ANX7447_PUBLIC_H
+#define __CROS_EC_DRIVER_TCPM_ANX7447_PUBLIC_H
+
+#include "usb_mux.h"
+
+#define AN7447_TCPC0_I2C_ADDR_FLAGS 0x2C
+#define AN7447_TCPC1_I2C_ADDR_FLAGS 0x2B
+#define AN7447_TCPC2_I2C_ADDR_FLAGS 0x2A
+#define AN7447_TCPC3_I2C_ADDR_FLAGS 0x29
+
+#define AN7447_SPI0_I2C_ADDR_FLAGS 0x3F
+#define AN7447_SPI1_I2C_ADDR_FLAGS 0x37
+#define AN7447_SPI2_I2C_ADDR_FLAGS 0x32
+#define AN7447_SPI3_I2C_ADDR_FLAGS 0x31
+
+extern const struct tcpm_drv anx7447_tcpm_drv;
+extern const struct usb_mux_driver anx7447_usb_mux_driver;
+
+void anx7447_tcpc_update_hpd_status(const struct usb_mux *me,
+				    mux_state_t mux_state, bool *ack_required);
+#endif /* __CROS_EC_DRIVER_TCPM_ANX7447_PUBLIC_H */
diff --git a/include/driver/tcpm/it8xxx2_pd_public.h b/include/driver/tcpm/it8xxx2_pd_public.h
index 6ad11a9555..0c28127cdb 100644
--- a/include/driver/tcpm/it8xxx2_pd_public.h
+++ b/include/driver/tcpm/it8xxx2_pd_public.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/driver/tcpm/ps8xxx_public.h b/include/driver/tcpm/ps8xxx_public.h
index ad84f93ced..d327dee2a3 100644
--- a/include/driver/tcpm/ps8xxx_public.h
+++ b/include/driver/tcpm/ps8xxx_public.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,12 +15,12 @@ struct usb_mux;
 /* I2C interface */
 #define PS8XXX_I2C_ADDR1_P1_FLAGS 0x09
 #define PS8XXX_I2C_ADDR1_P2_FLAGS 0x0A
-#define PS8XXX_I2C_ADDR1_FLAGS    0x0B	/* P3 */
-#define PS8XXX_I2C_ADDR2_FLAGS    0x1B
-#define PS8XXX_I2C_ADDR3_FLAGS    0x2B
-#define PS8XXX_I2C_ADDR4_FLAGS    0x4B
+#define PS8XXX_I2C_ADDR1_FLAGS 0x0B /* P3 */
+#define PS8XXX_I2C_ADDR2_FLAGS 0x1B
+#define PS8XXX_I2C_ADDR3_FLAGS 0x2B
+#define PS8XXX_I2C_ADDR4_FLAGS 0x4B
 
-#define PS8XXX_VENDOR_ID  0x1DA0
+#define PS8XXX_VENDOR_ID 0x1DA0
 
 /* Minimum Delay for reset assertion */
 #define PS8XXX_RESET_DELAY_MS 1
@@ -56,6 +56,7 @@ struct usb_mux;
  * 8705, 8755 and 8805.
  */
 #define PS8705_PRODUCT_ID 0x8705
+#define PS8745_PRODUCT_ID 0x8745
 #define PS8751_PRODUCT_ID 0x8751
 #define PS8755_PRODUCT_ID 0x8755
 #define PS8805_PRODUCT_ID 0x8805
@@ -75,12 +76,10 @@ extern const struct tcpm_drv ps8xxx_tcpm_drv;
  *
  * @param port	TCPC port number.
  */
-__override_proto
-uint16_t board_get_ps8xxx_product_id(int port);
+__override_proto uint16_t board_get_ps8xxx_product_id(int port);
 
 void ps8xxx_tcpc_update_hpd_status(const struct usb_mux *me,
-				   mux_state_t mux_state,
-				   bool *ack_required);
+				   mux_state_t mux_state, bool *ack_required);
 
 #ifdef CONFIG_CMD_I2C_STRESS_TEST_TCPC
 extern struct i2c_stress_test_dev ps8xxx_i2c_stress_test_dev;
diff --git a/include/driver/tcpm/rt1715_public.h b/include/driver/tcpm/rt1715_public.h
index 14fa9495e8..2f3af95443 100644
--- a/include/driver/tcpm/rt1715_public.h
+++ b/include/driver/tcpm/rt1715_public.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/driver/tcpm/rt1718s_public.h b/include/driver/tcpm/rt1718s_public.h
new file mode 100644
index 0000000000..62bade6ab9
--- /dev/null
+++ b/include/driver/tcpm/rt1718s_public.h
@@ -0,0 +1,24 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Richtek Type-C port controller */
+
+#ifndef __CROS_EC_DRIVER_TCPM_RT1718S_PUBLIC_H
+#define __CROS_EC_DRIVER_TCPM_RT1718S_PUBLIC_H
+
+#define RT1718S_I2C_ADDR1_FLAGS 0x43
+#define RT1718S_I2C_ADDR2_FLAGS 0x40
+
+#define RT1718S_VID 0x29CF
+#define RT1718S_PID 0x1718
+
+#define RT1718S_DEVICE_ID 0x04
+#define RT1718S_DEVICE_ID_ES1 0x4511
+#define RT1718S_DEVICE_ID_ES2 0x4513
+
+extern const struct tcpm_drv rt1718s_tcpm_drv;
+extern const struct bc12_drv rt1718s_bc12_drv;
+
+#endif /* __CROS_EC_DRIVER_TCPM_RT1718S_PUBLIC_H */
diff --git a/include/driver/tcpm/tcpci.h b/include/driver/tcpm/tcpci.h
index 559b75a14f..4879f7dad1 100644
--- a/include/driver/tcpm/tcpci.h
+++ b/include/driver/tcpm/tcpci.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,259 +14,250 @@
 #include "usb_mux.h"
 #include "usb_pd_tcpm.h"
 
-#define TCPC_REG_VENDOR_ID         0x0
-#define TCPC_REG_PRODUCT_ID        0x2
-#define TCPC_REG_BCD_DEV           0x4
-#define TCPC_REG_TC_REV            0x6
-#define TCPC_REG_PD_REV            0x8
-#define TCPC_REG_PD_INT_REV        0xa
-
-#define TCPC_REG_PD_INT_REV_REV_MASK  0xff00
-#define TCPC_REG_PD_INT_REV_REV_1_0   0x10
-#define TCPC_REG_PD_INT_REV_REV_2_0   0x20
-#define TCPC_REG_PD_INT_REV_VER_MASK  0x00ff
-#define TCPC_REG_PD_INT_REV_VER_1_0   0x10
-#define TCPC_REG_PD_INT_REV_VER_1_1   0x11
-#define TCPC_REG_PD_INT_REV_REV(reg) \
-		((reg & TCOC_REG_PD_INT_REV_REV_MASK) >> 8)
-#define TCPC_REG_PD_INT_REV_VER(reg) \
-		(reg & TCOC_REG_PD_INT_REV_VER_MASK)
-
-#define TCPC_REG_ALERT             0x10
-#define TCPC_REG_ALERT_NONE         0x0000
-#define TCPC_REG_ALERT_MASK_ALL     0xffff
-#define TCPC_REG_ALERT_VENDOR_DEF   BIT(15)
-#define TCPC_REG_ALERT_ALERT_EXT    BIT(14)
-#define TCPC_REG_ALERT_EXT_STATUS   BIT(13)
+#define TCPC_REG_VENDOR_ID 0x0
+#define TCPC_REG_PRODUCT_ID 0x2
+#define TCPC_REG_BCD_DEV 0x4
+#define TCPC_REG_TC_REV 0x6
+#define TCPC_REG_PD_REV 0x8
+#define TCPC_REG_PD_INT_REV 0xa
+
+#define TCPC_REG_PD_INT_REV_REV_MASK 0xff00
+#define TCPC_REG_PD_INT_REV_REV_1_0 0x10
+#define TCPC_REG_PD_INT_REV_REV_2_0 0x20
+#define TCPC_REG_PD_INT_REV_VER_MASK 0x00ff
+#define TCPC_REG_PD_INT_REV_VER_1_0 0x10
+#define TCPC_REG_PD_INT_REV_VER_1_1 0x11
+#define TCPC_REG_PD_INT_REV_REV(reg) ((reg & TCOC_REG_PD_INT_REV_REV_MASK) >> 8)
+#define TCPC_REG_PD_INT_REV_VER(reg) (reg & TCOC_REG_PD_INT_REV_VER_MASK)
+
+#define TCPC_REG_ALERT 0x10
+#define TCPC_REG_ALERT_NONE 0x0000
+#define TCPC_REG_ALERT_MASK_ALL 0xffff
+#define TCPC_REG_ALERT_VENDOR_DEF BIT(15)
+#define TCPC_REG_ALERT_ALERT_EXT BIT(14)
+#define TCPC_REG_ALERT_EXT_STATUS BIT(13)
 #define TCPC_REG_ALERT_RX_BEGINNING BIT(12)
 #define TCPC_REG_ALERT_VBUS_DISCNCT BIT(11)
-#define TCPC_REG_ALERT_RX_BUF_OVF   BIT(10)
-#define TCPC_REG_ALERT_FAULT        BIT(9)
-#define TCPC_REG_ALERT_V_ALARM_LO   BIT(8)
-#define TCPC_REG_ALERT_V_ALARM_HI   BIT(7)
-#define TCPC_REG_ALERT_TX_SUCCESS   BIT(6)
+#define TCPC_REG_ALERT_RX_BUF_OVF BIT(10)
+#define TCPC_REG_ALERT_FAULT BIT(9)
+#define TCPC_REG_ALERT_V_ALARM_LO BIT(8)
+#define TCPC_REG_ALERT_V_ALARM_HI BIT(7)
+#define TCPC_REG_ALERT_TX_SUCCESS BIT(6)
 #define TCPC_REG_ALERT_TX_DISCARDED BIT(5)
-#define TCPC_REG_ALERT_TX_FAILED    BIT(4)
-#define TCPC_REG_ALERT_RX_HARD_RST  BIT(3)
-#define TCPC_REG_ALERT_RX_STATUS    BIT(2)
+#define TCPC_REG_ALERT_TX_FAILED BIT(4)
+#define TCPC_REG_ALERT_RX_HARD_RST BIT(3)
+#define TCPC_REG_ALERT_RX_STATUS BIT(2)
 #define TCPC_REG_ALERT_POWER_STATUS BIT(1)
-#define TCPC_REG_ALERT_CC_STATUS    BIT(0)
-#define TCPC_REG_ALERT_TX_COMPLETE  (TCPC_REG_ALERT_TX_SUCCESS | \
-				      TCPC_REG_ALERT_TX_DISCARDED | \
-				      TCPC_REG_ALERT_TX_FAILED)
+#define TCPC_REG_ALERT_CC_STATUS BIT(0)
+#define TCPC_REG_ALERT_TX_COMPLETE                                 \
+	(TCPC_REG_ALERT_TX_SUCCESS | TCPC_REG_ALERT_TX_DISCARDED | \
+	 TCPC_REG_ALERT_TX_FAILED)
 
-#define TCPC_REG_ALERT_MASK        0x12
-#define TCPC_REG_ALERT_MASK_VENDOR_DEF   BIT(15)
+#define TCPC_REG_ALERT_MASK 0x12
+#define TCPC_REG_ALERT_MASK_VENDOR_DEF BIT(15)
 
 #define TCPC_REG_POWER_STATUS_MASK 0x14
 #define TCPC_REG_FAULT_STATUS_MASK 0x15
-#define TCPC_REG_EXT_STATUS_MASK   0x16
+#define TCPC_REG_EXT_STATUS_MASK 0x16
 #define TCPC_REG_ALERT_EXTENDED_MASK 0x17
 
 #define TCPC_REG_CONFIG_STD_OUTPUT 0x18
-#define TCPC_REG_CONFIG_STD_OUTPUT_DBG_ACC_CONN_N    BIT(6)
-#define TCPC_REG_CONFIG_STD_OUTPUT_AUDIO_CONN_N      BIT(5)
-#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_MASK          (3 << 2)
-#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_NONE          (0 << 2)
-#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_USB           BIT(2)
-#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_DP            (2 << 2)
+#define TCPC_REG_CONFIG_STD_OUTPUT_DBG_ACC_CONN_N BIT(6)
+#define TCPC_REG_CONFIG_STD_OUTPUT_AUDIO_CONN_N BIT(5)
+#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_MASK (3 << 2)
+#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_NONE (0 << 2)
+#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_USB BIT(2)
+#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_DP (2 << 2)
 #define TCPC_REG_CONFIG_STD_OUTPUT_CONNECTOR_FLIPPED BIT(0)
 
-#define TCPC_REG_TCPC_CTRL         0x19
+#define TCPC_REG_TCPC_CTRL 0x19
 #define TCPC_REG_TCPC_CTRL_SET(polarity) (polarity)
-#define TCPC_REG_TCPC_CTRL_POLARITY(reg) ((reg) & 0x1)
+#define TCPC_REG_TCPC_CTRL_POLARITY(reg) ((reg)&0x1)
 /*
  * In TCPCI Rev 2.0, this bit must be set this to generate CC status alerts when
  * a connection is found.
  */
-#define TCPC_REG_TCPC_CTRL_EN_LOOK4CONNECTION_ALERT  BIT(6)
-#define TCPC_REG_TCPC_CTRL_DEBUG_ACC_CONTROL         BIT(4)
-#define TCPC_REG_TCPC_CTRL_BIST_TEST_MODE            BIT(1)
-
-#define TCPC_REG_ROLE_CTRL         0x1a
-#define TCPC_REG_ROLE_CTRL_DRP_MASK                    BIT(6)
-#define TCPC_REG_ROLE_CTRL_RP_MASK                     (BIT(5)|BIT(4))
-#define TCPC_REG_ROLE_CTRL_CC2_MASK                    (BIT(3)|BIT(2))
-#define TCPC_REG_ROLE_CTRL_CC1_MASK                    (BIT(1)|BIT(0))
-#define TCPC_REG_ROLE_CTRL_SET(drp, rp, cc1, cc2) \
-		((((drp) << 6) & TCPC_REG_ROLE_CTRL_DRP_MASK) | \
-		(((rp) << 4) & TCPC_REG_ROLE_CTRL_RP_MASK) | \
-		(((cc2) << 2) & TCPC_REG_ROLE_CTRL_CC2_MASK) | \
-		((cc1) & TCPC_REG_ROLE_CTRL_CC1_MASK))
-#define TCPC_REG_ROLE_CTRL_DRP(reg) \
-		(((reg) & TCPC_REG_ROLE_CTRL_DRP_MASK) >> 6)
-#define TCPC_REG_ROLE_CTRL_RP(reg) \
-		(((reg) & TCPC_REG_ROLE_CTRL_RP_MASK) >> 4)
-#define TCPC_REG_ROLE_CTRL_CC2(reg) \
-		(((reg) & TCPC_REG_ROLE_CTRL_CC2_MASK) >> 2)
-#define TCPC_REG_ROLE_CTRL_CC1(reg) \
-		((reg) & TCPC_REG_ROLE_CTRL_CC1_MASK)
-
-#define TCPC_REG_FAULT_CTRL        0x1b
-#define TCPC_REG_FAULT_CTRL_VBUS_OVP_FAULT_DIS         BIT(1)
-#define TCPC_REG_FAULT_CTRL_VBUS_OCP_FAULT_DIS         BIT(0)
-
-#define TCPC_REG_POWER_CTRL        0x1c
-#define TCPC_REG_POWER_CTRL_FRS_ENABLE                 BIT(7)
-#define TCPC_REG_POWER_CTRL_VBUS_VOL_MONITOR_DIS       BIT(6)
-#define TCPC_REG_POWER_CTRL_VOLT_ALARM_DIS             BIT(5)
-#define TCPC_REG_POWER_CTRL_AUTO_DISCHARGE_DISCONNECT  BIT(4)
-#define TCPC_REG_POWER_CTRL_FORCE_DISCHARGE            BIT(2)
+#define TCPC_REG_TCPC_CTRL_EN_LOOK4CONNECTION_ALERT BIT(6)
+#define TCPC_REG_TCPC_CTRL_DEBUG_ACC_CONTROL BIT(4)
+#define TCPC_REG_TCPC_CTRL_BIST_TEST_MODE BIT(1)
+
+#define TCPC_REG_ROLE_CTRL 0x1a
+#define TCPC_REG_ROLE_CTRL_DRP_MASK BIT(6)
+#define TCPC_REG_ROLE_CTRL_RP_MASK (BIT(5) | BIT(4))
+#define TCPC_REG_ROLE_CTRL_CC2_MASK (BIT(3) | BIT(2))
+#define TCPC_REG_ROLE_CTRL_CC1_MASK (BIT(1) | BIT(0))
+#define TCPC_REG_ROLE_CTRL_SET(drp, rp, cc1, cc2)       \
+	((((drp) << 6) & TCPC_REG_ROLE_CTRL_DRP_MASK) | \
+	 (((rp) << 4) & TCPC_REG_ROLE_CTRL_RP_MASK) |   \
+	 (((cc2) << 2) & TCPC_REG_ROLE_CTRL_CC2_MASK) | \
+	 ((cc1)&TCPC_REG_ROLE_CTRL_CC1_MASK))
+#define TCPC_REG_ROLE_CTRL_DRP(reg) (((reg)&TCPC_REG_ROLE_CTRL_DRP_MASK) >> 6)
+#define TCPC_REG_ROLE_CTRL_RP(reg) (((reg)&TCPC_REG_ROLE_CTRL_RP_MASK) >> 4)
+#define TCPC_REG_ROLE_CTRL_CC2(reg) (((reg)&TCPC_REG_ROLE_CTRL_CC2_MASK) >> 2)
+#define TCPC_REG_ROLE_CTRL_CC1(reg) ((reg)&TCPC_REG_ROLE_CTRL_CC1_MASK)
+
+#define TCPC_REG_FAULT_CTRL 0x1b
+#define TCPC_REG_FAULT_CTRL_VBUS_OVP_FAULT_DIS BIT(1)
+#define TCPC_REG_FAULT_CTRL_VBUS_OCP_FAULT_DIS BIT(0)
+
+#define TCPC_REG_POWER_CTRL 0x1c
+#define TCPC_REG_POWER_CTRL_FRS_ENABLE BIT(7)
+#define TCPC_REG_POWER_CTRL_VBUS_VOL_MONITOR_DIS BIT(6)
+#define TCPC_REG_POWER_CTRL_VOLT_ALARM_DIS BIT(5)
+#define TCPC_REG_POWER_CTRL_AUTO_DISCHARGE_DISCONNECT BIT(4)
+#define TCPC_REG_POWER_CTRL_FORCE_DISCHARGE BIT(2)
 #define TCPC_REG_POWER_CTRL_SET(vconn) (vconn)
-#define TCPC_REG_POWER_CTRL_VCONN(reg)    ((reg) & 0x1)
+#define TCPC_REG_POWER_CTRL_VCONN(reg) ((reg)&0x1)
 
-#define TCPC_REG_CC_STATUS         0x1d
-#define TCPC_REG_CC_STATUS_LOOK4CONNECTION_MASK        BIT(5)
-#define TCPC_REG_CC_STATUS_CONNECT_RESULT_MASK         BIT(4)
-#define TCPC_REG_CC_STATUS_CC2_STATE_MASK              (BIT(3)|BIT(2))
-#define TCPC_REG_CC_STATUS_CC1_STATE_MASK              (BIT(1)|BIT(0))
+#define TCPC_REG_CC_STATUS 0x1d
+#define TCPC_REG_CC_STATUS_LOOK4CONNECTION_MASK BIT(5)
+#define TCPC_REG_CC_STATUS_CONNECT_RESULT_MASK BIT(4)
+#define TCPC_REG_CC_STATUS_CC2_STATE_MASK (BIT(3) | BIT(2))
+#define TCPC_REG_CC_STATUS_CC1_STATE_MASK (BIT(1) | BIT(0))
 #define TCPC_REG_CC_STATUS_SET(term, cc1, cc2) \
-		((term) << 4 | ((cc2) & 0x3) << 2 | ((cc1) & 0x3))
+	((term) << 4 | ((cc2)&0x3) << 2 | ((cc1)&0x3))
 #define TCPC_REG_CC_STATUS_LOOK4CONNECTION(reg) \
-		((reg & TCPC_REG_CC_STATUS_LOOK4CONNECTION_MASK) >> 5)
+	((reg & TCPC_REG_CC_STATUS_LOOK4CONNECTION_MASK) >> 5)
 #define TCPC_REG_CC_STATUS_TERM(reg) \
-		(((reg) & TCPC_REG_CC_STATUS_CONNECT_RESULT_MASK) >> 4)
+	(((reg)&TCPC_REG_CC_STATUS_CONNECT_RESULT_MASK) >> 4)
 #define TCPC_REG_CC_STATUS_CC2(reg) \
-		(((reg) & TCPC_REG_CC_STATUS_CC2_STATE_MASK) >> 2)
-#define TCPC_REG_CC_STATUS_CC1(reg) \
-		((reg) & TCPC_REG_CC_STATUS_CC1_STATE_MASK)
+	(((reg)&TCPC_REG_CC_STATUS_CC2_STATE_MASK) >> 2)
+#define TCPC_REG_CC_STATUS_CC1(reg) ((reg)&TCPC_REG_CC_STATUS_CC1_STATE_MASK)
 
-#define TCPC_REG_POWER_STATUS      0x1e
-#define TCPC_REG_POWER_STATUS_MASK_ALL  0xff
+#define TCPC_REG_POWER_STATUS 0x1e
+#define TCPC_REG_POWER_STATUS_MASK_ALL 0xff
 #define TCPC_REG_POWER_STATUS_DEBUG_ACC_CON BIT(7)
-#define TCPC_REG_POWER_STATUS_UNINIT    BIT(6)
+#define TCPC_REG_POWER_STATUS_UNINIT BIT(6)
 #define TCPC_REG_POWER_STATUS_SOURCING_VBUS BIT(4)
-#define TCPC_REG_POWER_STATUS_VBUS_DET  BIT(3)
+#define TCPC_REG_POWER_STATUS_VBUS_DET BIT(3)
 #define TCPC_REG_POWER_STATUS_VBUS_PRES BIT(2)
 #define TCPC_REG_POWER_STATUS_SINKING_VBUS BIT(0)
 
-#define TCPC_REG_FAULT_STATUS      0x1f
-#define TCPC_REG_FAULT_STATUS_ALL_REGS_RESET            BIT(7)
-#define TCPC_REG_FAULT_STATUS_FORCE_OFF_VBUS            BIT(6)
-#define TCPC_REG_FAULT_STATUS_AUTO_DISCHARGE_FAIL       BIT(5)
-#define TCPC_REG_FAULT_STATUS_FORCE_DISCHARGE_FAIL      BIT(4)
-#define TCPC_REG_FAULT_STATUS_VBUS_OVER_CURRENT         BIT(3)
-#define TCPC_REG_FAULT_STATUS_VBUS_OVER_VOLTAGE         BIT(2)
-#define TCPC_REG_FAULT_STATUS_VCONN_OVER_CURRENT        BIT(1)
-#define TCPC_REG_FAULT_STATUS_I2C_INTERFACE_ERR         BIT(0)
-
-#define TCPC_REG_EXT_STATUS        0x20
-#define TCPC_REG_EXT_STATUS_SAFE0V   BIT(0)
-
-#define TCPC_REG_ALERT_EXT         0x21
-#define TCPC_REG_ALERT_EXT_TIMER_EXPIRED        BIT(2)
-#define TCPC_REG_ALERT_EXT_SRC_FRS              BIT(1)
-#define TCPC_REG_ALERT_EXT_SNK_FRS              BIT(0)
-
-#define TCPC_REG_COMMAND           0x23
-#define TCPC_REG_COMMAND_WAKE_I2C		 0x11
-#define TCPC_REG_COMMAND_ENABLE_VBUS_DETECT      0x33
-#define TCPC_REG_COMMAND_SNK_CTRL_LOW            0x44
-#define TCPC_REG_COMMAND_SNK_CTRL_HIGH           0x55
-#define TCPC_REG_COMMAND_SRC_CTRL_LOW            0x66
-#define TCPC_REG_COMMAND_SRC_CTRL_HIGH           0x77
-#define TCPC_REG_COMMAND_LOOK4CONNECTION         0x99
-#define TCPC_REG_COMMAND_RESET_TRANSMIT_BUF      0xDD
-#define TCPC_REG_COMMAND_RESET_RECEIVE_BUF       0xEE
-#define TCPC_REG_COMMAND_I2CIDLE                 0xFF
-
-#define TCPC_REG_DEV_CAP_1         0x24
-#define TCPC_REG_DEV_CAP_1_VBUS_NONDEFAULT_TARGET	BIT(15)
-#define TCPC_REG_DEV_CAP_1_VBUS_OCP_REPORTING		BIT(14)
-#define TCPC_REG_DEV_CAP_1_VBUS_OVP_REPORTING		BIT(13)
-#define TCPC_REG_DEV_CAP_1_BLEED_DISCHARGE		BIT(12)
-#define TCPC_REG_DEV_CAP_1_FORCE_DISCHARGE		BIT(11)
-#define TCPC_REG_DEV_CAP_1_VBUS_MEASURE_ALARM_CAPABLE	BIT(10)
-#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_MASK		(BIT(8)|BIT(9))
-#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_DEF		(0 << 8)
-#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_1P5_DEF	(1 << 8)
-#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_3P0_1P5_DEF	(2 << 8)
-#define TCPC_REG_DEV_CAP_1_PWRROLE_MASK			(BIT(5)|BIT(6)|BIT(7))
-#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC_OR_SNK		(0 << 5)
-#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC			(1 << 5)
-#define TCPC_REG_DEV_CAP_1_PWRROLE_SNK			(2 << 5)
-#define TCPC_REG_DEV_CAP_1_PWRROLE_SNK_ACC		(3 << 5)
-#define TCPC_REG_DEV_CAP_1_PWRROLE_DRP			(4 << 5)
-#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP_ADPT_CBL	(5 << 5)
-#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP		(6 << 5)
-#define TCPC_REG_DEV_CAP_1_ALL_SOP_STAR_MSGS_SUPPORTED	BIT(4)
-#define TCPC_REG_DEV_CAP_1_SOURCE_VCONN			BIT(3)
-#define TCPC_REG_DEV_CAP_1_SINK_VBUS			BIT(2)
-#define TCPC_REG_DEV_CAP_1_SOURCE_NONDEFAULT_VBUS	BIT(1)
-#define TCPC_REG_DEV_CAP_1_SOURCE_VBUS			BIT(0)
-
-#define TCPC_REG_DEV_CAP_2         0x26
-#define TCPC_REG_DEV_CAP_2_LONG_MSG		BIT(12)
-#define TCPC_REG_DEV_CAP_2_SNK_FR_SWAP		BIT(9)
-
-#define TCPC_REG_STD_INPUT_CAP     0x28
-#define TCPC_REG_STD_INPUT_CAP_SRC_FR_SWAP	(BIT(4)|BIT(3))
-#define TCPC_REG_STD_INPUT_CAP_EXT_OVR_V_F	BIT(2)
-#define TCPC_REG_STD_INPUT_CAP_EXT_OVR_C_F	BIT(1)
-#define TCPC_REG_STD_INPUT_CAP_FORCE_OFF_VBUS	BIT(0)
-
-#define TCPC_REG_STD_OUTPUT_CAP    0x29
-#define TCPC_REG_STD_OUTPUT_CAP_SNK_DISC_DET		BIT(7)
-#define TCPC_REG_STD_OUTPUT_CAP_DBG_ACCESSORY		BIT(6)
-#define TCPC_REG_STD_OUTPUT_CAP_VBUS_PRESENT_MON	BIT(5)
-#define TCPC_REG_STD_OUTPUT_CAP_AUDIO_ACCESSORY		BIT(4)
-#define TCPC_REG_STD_OUTPUT_CAP_ACTIVE_CABLE		BIT(3)
-#define TCPC_REG_STD_OUTPUT_CAP_MUX_CONF_CTRL		BIT(2)
-#define TCPC_REG_STD_OUTPUT_CAP_CONN_PRESENT		BIT(1)
-#define TCPC_REG_STD_OUTPUT_CAP_CONN_ORIENTATION	BIT(0)
-
-#define TCPC_REG_CONFIG_EXT_1      0x2A
-#define TCPC_REG_CONFIG_EXT_1_FR_SWAP_SNK_DIR	BIT(1)
-
-#define TCPC_REG_GENERIC_TIMER     0x2c
-
-#define TCPC_REG_MSG_HDR_INFO      0x2e
+#define TCPC_REG_FAULT_STATUS 0x1f
+#define TCPC_REG_FAULT_STATUS_ALL_REGS_RESET BIT(7)
+#define TCPC_REG_FAULT_STATUS_FORCE_OFF_VBUS BIT(6)
+#define TCPC_REG_FAULT_STATUS_AUTO_DISCHARGE_FAIL BIT(5)
+#define TCPC_REG_FAULT_STATUS_FORCE_DISCHARGE_FAIL BIT(4)
+#define TCPC_REG_FAULT_STATUS_VBUS_OVER_CURRENT BIT(3)
+#define TCPC_REG_FAULT_STATUS_VBUS_OVER_VOLTAGE BIT(2)
+#define TCPC_REG_FAULT_STATUS_VCONN_OVER_CURRENT BIT(1)
+#define TCPC_REG_FAULT_STATUS_I2C_INTERFACE_ERR BIT(0)
+
+#define TCPC_REG_EXT_STATUS 0x20
+#define TCPC_REG_EXT_STATUS_SAFE0V BIT(0)
+
+#define TCPC_REG_ALERT_EXT 0x21
+#define TCPC_REG_ALERT_EXT_TIMER_EXPIRED BIT(2)
+#define TCPC_REG_ALERT_EXT_SRC_FRS BIT(1)
+#define TCPC_REG_ALERT_EXT_SNK_FRS BIT(0)
+
+#define TCPC_REG_COMMAND 0x23
+#define TCPC_REG_COMMAND_WAKE_I2C 0x11
+#define TCPC_REG_COMMAND_ENABLE_VBUS_DETECT 0x33
+#define TCPC_REG_COMMAND_SNK_CTRL_LOW 0x44
+#define TCPC_REG_COMMAND_SNK_CTRL_HIGH 0x55
+#define TCPC_REG_COMMAND_SRC_CTRL_LOW 0x66
+#define TCPC_REG_COMMAND_SRC_CTRL_HIGH 0x77
+#define TCPC_REG_COMMAND_LOOK4CONNECTION 0x99
+#define TCPC_REG_COMMAND_RESET_TRANSMIT_BUF 0xDD
+#define TCPC_REG_COMMAND_RESET_RECEIVE_BUF 0xEE
+#define TCPC_REG_COMMAND_I2CIDLE 0xFF
+
+#define TCPC_REG_DEV_CAP_1 0x24
+#define TCPC_REG_DEV_CAP_1_VBUS_NONDEFAULT_TARGET BIT(15)
+#define TCPC_REG_DEV_CAP_1_VBUS_OCP_REPORTING BIT(14)
+#define TCPC_REG_DEV_CAP_1_VBUS_OVP_REPORTING BIT(13)
+#define TCPC_REG_DEV_CAP_1_BLEED_DISCHARGE BIT(12)
+#define TCPC_REG_DEV_CAP_1_FORCE_DISCHARGE BIT(11)
+#define TCPC_REG_DEV_CAP_1_VBUS_MEASURE_ALARM_CAPABLE BIT(10)
+#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_MASK (BIT(8) | BIT(9))
+#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_DEF (0 << 8)
+#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_1P5_DEF (1 << 8)
+#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_3P0_1P5_DEF (2 << 8)
+#define TCPC_REG_DEV_CAP_1_PWRROLE_MASK (BIT(5) | BIT(6) | BIT(7))
+#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC_OR_SNK (0 << 5)
+#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC (1 << 5)
+#define TCPC_REG_DEV_CAP_1_PWRROLE_SNK (2 << 5)
+#define TCPC_REG_DEV_CAP_1_PWRROLE_SNK_ACC (3 << 5)
+#define TCPC_REG_DEV_CAP_1_PWRROLE_DRP (4 << 5)
+#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP_ADPT_CBL (5 << 5)
+#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP (6 << 5)
+#define TCPC_REG_DEV_CAP_1_ALL_SOP_STAR_MSGS_SUPPORTED BIT(4)
+#define TCPC_REG_DEV_CAP_1_SOURCE_VCONN BIT(3)
+#define TCPC_REG_DEV_CAP_1_SINK_VBUS BIT(2)
+#define TCPC_REG_DEV_CAP_1_SOURCE_NONDEFAULT_VBUS BIT(1)
+#define TCPC_REG_DEV_CAP_1_SOURCE_VBUS BIT(0)
+
+#define TCPC_REG_DEV_CAP_2 0x26
+#define TCPC_REG_DEV_CAP_2_LONG_MSG BIT(12)
+#define TCPC_REG_DEV_CAP_2_SNK_FR_SWAP BIT(9)
+
+#define TCPC_REG_STD_INPUT_CAP 0x28
+#define TCPC_REG_STD_INPUT_CAP_SRC_FR_SWAP (BIT(4) | BIT(3))
+#define TCPC_REG_STD_INPUT_CAP_EXT_OVR_V_F BIT(2)
+#define TCPC_REG_STD_INPUT_CAP_EXT_OVR_C_F BIT(1)
+#define TCPC_REG_STD_INPUT_CAP_FORCE_OFF_VBUS BIT(0)
+
+#define TCPC_REG_STD_OUTPUT_CAP 0x29
+#define TCPC_REG_STD_OUTPUT_CAP_SNK_DISC_DET BIT(7)
+#define TCPC_REG_STD_OUTPUT_CAP_DBG_ACCESSORY BIT(6)
+#define TCPC_REG_STD_OUTPUT_CAP_VBUS_PRESENT_MON BIT(5)
+#define TCPC_REG_STD_OUTPUT_CAP_AUDIO_ACCESSORY BIT(4)
+#define TCPC_REG_STD_OUTPUT_CAP_ACTIVE_CABLE BIT(3)
+#define TCPC_REG_STD_OUTPUT_CAP_MUX_CONF_CTRL BIT(2)
+#define TCPC_REG_STD_OUTPUT_CAP_CONN_PRESENT BIT(1)
+#define TCPC_REG_STD_OUTPUT_CAP_CONN_ORIENTATION BIT(0)
+
+#define TCPC_REG_CONFIG_EXT_1 0x2A
+#define TCPC_REG_CONFIG_EXT_1_FR_SWAP_SNK_DIR BIT(1)
+
+#define TCPC_REG_GENERIC_TIMER 0x2c
+
+#define TCPC_REG_MSG_HDR_INFO 0x2e
 #define TCPC_REG_MSG_HDR_INFO_SET(drole, prole) \
-		((drole) << 3 | (PD_REV20 << 1) | (prole))
-#define TCPC_REG_MSG_HDR_INFO_DROLE(reg) (((reg) & 0x8) >> 3)
-#define TCPC_REG_MSG_HDR_INFO_PROLE(reg) ((reg) & 0x1)
-
-#define TCPC_REG_RX_DETECT         0x2f
-#define TCPC_REG_RX_DETECT_MSG_DISABLE_DISCONNECT	BIT(7)
-#define TCPC_REG_RX_DETECT_CABLE_RST			BIT(6)
-#define TCPC_REG_RX_DETECT_HRST				BIT(5)
-#define TCPC_REG_RX_DETECT_SOPPP_DBG			BIT(4)
-#define TCPC_REG_RX_DETECT_SOPP_DBG			BIT(3)
-#define TCPC_REG_RX_DETECT_SOPPP			BIT(2)
-#define TCPC_REG_RX_DETECT_SOPP				BIT(1)
-#define TCPC_REG_RX_DETECT_SOP				BIT(0)
-#define TCPC_REG_RX_DETECT_SOP_HRST_MASK (TCPC_REG_RX_DETECT_SOP | \
-					  TCPC_REG_RX_DETECT_HRST)
-#define TCPC_REG_RX_DETECT_SOP_SOPP_SOPPP_HRST_MASK		\
-					(TCPC_REG_RX_DETECT_SOP | \
-					 TCPC_REG_RX_DETECT_SOPP | \
-					 TCPC_REG_RX_DETECT_SOPPP | \
-					 TCPC_REG_RX_DETECT_HRST)
+	((drole) << 3 | (PD_REV20 << 1) | (prole))
+#define TCPC_REG_MSG_HDR_INFO_DROLE(reg) (((reg)&0x8) >> 3)
+#define TCPC_REG_MSG_HDR_INFO_PROLE(reg) ((reg)&0x1)
+
+#define TCPC_REG_RX_DETECT 0x2f
+#define TCPC_REG_RX_DETECT_MSG_DISABLE_DISCONNECT BIT(7)
+#define TCPC_REG_RX_DETECT_CABLE_RST BIT(6)
+#define TCPC_REG_RX_DETECT_HRST BIT(5)
+#define TCPC_REG_RX_DETECT_SOPPP_DBG BIT(4)
+#define TCPC_REG_RX_DETECT_SOPP_DBG BIT(3)
+#define TCPC_REG_RX_DETECT_SOPPP BIT(2)
+#define TCPC_REG_RX_DETECT_SOPP BIT(1)
+#define TCPC_REG_RX_DETECT_SOP BIT(0)
+#define TCPC_REG_RX_DETECT_SOP_HRST_MASK \
+	(TCPC_REG_RX_DETECT_SOP | TCPC_REG_RX_DETECT_HRST)
+#define TCPC_REG_RX_DETECT_SOP_SOPP_SOPPP_HRST_MASK         \
+	(TCPC_REG_RX_DETECT_SOP | TCPC_REG_RX_DETECT_SOPP | \
+	 TCPC_REG_RX_DETECT_SOPPP | TCPC_REG_RX_DETECT_HRST)
 
 /* TCPCI Rev 1.0 receive registers */
-#define TCPC_REG_RX_BYTE_CNT       0x30
+#define TCPC_REG_RX_BYTE_CNT 0x30
 #define TCPC_REG_RX_BUF_FRAME_TYPE 0x31
-#define TCPC_REG_RX_HDR            0x32
-#define TCPC_REG_RX_DATA           0x34 /* through 0x4f */
+#define TCPC_REG_RX_HDR 0x32
+#define TCPC_REG_RX_DATA 0x34 /* through 0x4f */
 
 /*
  * In TCPCI Rev 2.0, the RECEIVE_BUFFER is comprised of three sets of registers:
  * READABLE_BYTE_COUNT, RX_BUF_FRAME_TYPE and RX_BUF_BYTE_x. These registers can
  * only be accessed by reading at a common register address 30h.
  */
-#define TCPC_REG_RX_BUFFER         0x30
+#define TCPC_REG_RX_BUFFER 0x30
 
-#define TCPC_REG_TRANSMIT          0x50
+#define TCPC_REG_TRANSMIT 0x50
 #define TCPC_REG_TRANSMIT_SET_WITH_RETRY(retries, type) \
-		((retries) << 4 | (type))
+	((retries) << 4 | (type))
 #define TCPC_REG_TRANSMIT_SET_WITHOUT_RETRY(type) (type)
-#define TCPC_REG_TRANSMIT_RETRY(reg) (((reg) & 0x30) >> 4)
-#define TCPC_REG_TRANSMIT_TYPE(reg)  ((reg) & 0x7)
+#define TCPC_REG_TRANSMIT_RETRY(reg) (((reg)&0x30) >> 4)
+#define TCPC_REG_TRANSMIT_TYPE(reg) ((reg)&0x7)
 
 /* TCPCI Rev 1.0 transmit registers */
-#define TCPC_REG_TX_BYTE_CNT       0x51
-#define TCPC_REG_TX_HDR            0x52
-#define TCPC_REG_TX_DATA           0x54 /* through 0x6f */
+#define TCPC_REG_TX_BYTE_CNT 0x51
+#define TCPC_REG_TX_HDR 0x52
+#define TCPC_REG_TX_DATA 0x54 /* through 0x6f */
 
 /*
  * In TCPCI Rev 2.0, the TRANSMIT_BUFFER holds the I2C_WRITE_BYTE_COUNT and the
@@ -274,12 +265,12 @@
  * data bytes) most recently written by the TCPM in TX_BUF_BYTE_x. TX_BUF_BYTE_x
  * is “hidden” and can only be accessed by writing to register address 51h
  */
-#define TCPC_REG_TX_BUFFER         0x51
+#define TCPC_REG_TX_BUFFER 0x51
 
-#define TCPC_REG_VBUS_VOLTAGE                0x70
-#define TCPC_REG_VBUS_VOLTAGE_MEASUREMENT    GENMASK(9, 0)
-#define TCPC_REG_VBUS_VOLTAGE_SCALE_FACTOR   GENMASK(11, 10)
-#define TCPC_REG_VBUS_VOLTAGE_LSB            25
+#define TCPC_REG_VBUS_VOLTAGE 0x70
+#define TCPC_REG_VBUS_VOLTAGE_MEASUREMENT GENMASK(9, 0)
+#define TCPC_REG_VBUS_VOLTAGE_SCALE_FACTOR GENMASK(11, 10)
+#define TCPC_REG_VBUS_VOLTAGE_LSB 25
 
 /*
  * 00: the measurement is not scaled
@@ -287,22 +278,21 @@
  * 10: the measurement is divided by 4
  * 11: reserved
  */
-#define TCPC_REG_VBUS_VOLTAGE_SCALE(x)                                         \
-	(1 << (((x) & TCPC_REG_VBUS_VOLTAGE_SCALE_FACTOR) >> 9))
-#define TCPC_REG_VBUS_VOLTAGE_MEASURE(x)                                       \
-	((x) & TCPC_REG_VBUS_VOLTAGE_MEASUREMENT)
-#define TCPC_REG_VBUS_VOLTAGE_VBUS(x)                                          \
-	(TCPC_REG_VBUS_VOLTAGE_SCALE(x) * TCPC_REG_VBUS_VOLTAGE_MEASURE(x) *   \
+#define TCPC_REG_VBUS_VOLTAGE_SCALE(x) \
+	(1 << (((x)&TCPC_REG_VBUS_VOLTAGE_SCALE_FACTOR) >> 9))
+#define TCPC_REG_VBUS_VOLTAGE_MEASURE(x) ((x)&TCPC_REG_VBUS_VOLTAGE_MEASUREMENT)
+#define TCPC_REG_VBUS_VOLTAGE_VBUS(x)                                        \
+	(TCPC_REG_VBUS_VOLTAGE_SCALE(x) * TCPC_REG_VBUS_VOLTAGE_MEASURE(x) * \
 	 TCPC_REG_VBUS_VOLTAGE_LSB)
 
 #define TCPC_REG_VBUS_SINK_DISCONNECT_THRESH 0x72
 #define TCPC_REG_VBUS_SINK_DISCONNECT_THRESH_DEFAULT 0x008C /* 3.5 V */
 
-#define TCPC_REG_VBUS_STOP_DISCHARGE_THRESH  0x74
-#define TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG   0x76
-#define TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG   0x78
+#define TCPC_REG_VBUS_STOP_DISCHARGE_THRESH 0x74
+#define TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG 0x76
+#define TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG 0x78
 
-#define TCPC_REG_VBUS_NONDEFAULT_TARGET      0x7a
+#define TCPC_REG_VBUS_NONDEFAULT_TARGET 0x7a
 
 extern const struct tcpm_drv tcpci_tcpm_drv;
 extern const struct usb_mux_driver tcpci_tcpm_usb_mux_driver;
@@ -315,7 +305,7 @@ enum tcpc_cc_pull tcpci_get_cached_pull(int port);
 void tcpci_tcpc_alert(int port);
 int tcpci_tcpm_init(int port);
 int tcpci_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2);
+		      enum tcpc_cc_voltage_status *cc2);
 bool tcpci_tcpm_check_vbus_level(int port, enum vbus_level level);
 int tcpci_tcpm_select_rp_value(int port, int rp);
 int tcpci_tcpm_set_cc(int port, int pull);
@@ -325,20 +315,22 @@ int tcpci_tcpm_set_vconn(int port, int enable);
 int tcpci_tcpm_set_msg_header(int port, int power_role, int data_role);
 int tcpci_tcpm_set_rx_enable(int port, int enable);
 int tcpci_tcpm_get_message_raw(int port, uint32_t *payload, int *head);
-int tcpci_tcpm_transmit(int port, enum tcpci_msg_type type,
-			uint16_t header, const uint32_t *data);
+int tcpci_tcpm_transmit(int port, enum tcpci_msg_type type, uint16_t header,
+			const uint32_t *data);
 int tcpci_tcpm_release(int port);
 #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
 int tcpci_set_role_ctrl(int port, enum tcpc_drp drp, enum tcpc_rp_value rp,
-	enum tcpc_cc_pull pull);
+			enum tcpc_cc_pull pull);
 int tcpci_tcpc_drp_toggle(int port);
 #endif
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
 int tcpci_enter_low_power_mode(int port);
 void tcpci_wake_low_power_mode(int port);
 #endif
-enum ec_error_list tcpci_set_bist_test_mode(const int port,
-		const bool enable);
+int tcpci_hard_reset_reinit(int port);
+
+enum ec_error_list tcpci_set_bist_test_mode(const int port, const bool enable);
+enum ec_error_list tcpci_get_bist_test_mode(const int port, bool *enable);
 void tcpci_tcpc_discharge_vbus(int port, int enable);
 void tcpci_tcpc_enable_auto_discharge_disconnect(int port, int enable);
 int tcpci_tcpc_debug_accessory(int port, bool enable);
diff --git a/include/driver/tcpm/tcpm.h b/include/driver/tcpm/tcpm.h
index ef47a3b1e2..8352423d9d 100644
--- a/include/driver/tcpm/tcpm.h
+++ b/include/driver/tcpm/tcpm.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,26 +26,22 @@
 #ifndef CONFIG_USB_PD_TCPC_LOW_POWER
 static inline int tcpc_addr_write(int port, int i2c_addr, int reg, int val)
 {
-	return i2c_write8(tcpc_config[port].i2c_info.port,
-			  i2c_addr, reg, val);
+	return i2c_write8(tcpc_config[port].i2c_info.port, i2c_addr, reg, val);
 }
 
 static inline int tcpc_addr_write16(int port, int i2c_addr, int reg, int val)
 {
-	return i2c_write16(tcpc_config[port].i2c_info.port,
-			   i2c_addr, reg, val);
+	return i2c_write16(tcpc_config[port].i2c_info.port, i2c_addr, reg, val);
 }
 
 static inline int tcpc_addr_read(int port, int i2c_addr, int reg, int *val)
 {
-	return i2c_read8(tcpc_config[port].i2c_info.port,
-			 i2c_addr, reg, val);
+	return i2c_read8(tcpc_config[port].i2c_info.port, i2c_addr, reg, val);
 }
 
 static inline int tcpc_addr_read16(int port, int i2c_addr, int reg, int *val)
 {
-	return i2c_read16(tcpc_config[port].i2c_info.port,
-			  i2c_addr, reg, val);
+	return i2c_read16(tcpc_config[port].i2c_info.port, i2c_addr, reg, val);
 }
 
 /*
@@ -65,8 +61,8 @@ static inline int tcpc_addr_read16(int port, int i2c_addr, int reg, int *val)
  *    need an explicit by the caller.
  */
 
-static inline int tcpc_addr_read16_no_lpm_exit(int port, int i2c_addr,
-					       int reg, int *val)
+static inline int tcpc_addr_read16_no_lpm_exit(int port, int i2c_addr, int reg,
+					       int *val)
 {
 	return tcpc_addr_read16(port, i2c_addr, reg, val);
 }
@@ -75,49 +71,47 @@ static inline int tcpc_xfer(int port, const uint8_t *out, int out_size,
 			    uint8_t *in, int in_size)
 {
 	return i2c_xfer(tcpc_config[port].i2c_info.port,
-			tcpc_config[port].i2c_info.addr_flags,
-			out, out_size, in, in_size);
+			tcpc_config[port].i2c_info.addr_flags, out, out_size,
+			in, in_size);
 }
 
 static inline int tcpc_xfer_unlocked(int port, const uint8_t *out, int out_size,
-			    uint8_t *in, int in_size, int flags)
+				     uint8_t *in, int in_size, int flags)
 {
 	return i2c_xfer_unlocked(tcpc_config[port].i2c_info.port,
-				 tcpc_config[port].i2c_info.addr_flags,
-				 out, out_size, in, in_size, flags);
+				 tcpc_config[port].i2c_info.addr_flags, out,
+				 out_size, in, in_size, flags);
 }
 
 static inline int tcpc_read_block(int port, int reg, uint8_t *in, int size)
 {
 	return i2c_read_block(tcpc_config[port].i2c_info.port,
-			      tcpc_config[port].i2c_info.addr_flags,
-			      reg, in, size);
+			      tcpc_config[port].i2c_info.addr_flags, reg, in,
+			      size);
 }
 
-static inline int tcpc_write_block(int port, int reg,
-		const uint8_t *out, int size)
+static inline int tcpc_write_block(int port, int reg, const uint8_t *out,
+				   int size)
 {
 	return i2c_write_block(tcpc_config[port].i2c_info.port,
-			       tcpc_config[port].i2c_info.addr_flags,
-			       reg, out, size);
+			       tcpc_config[port].i2c_info.addr_flags, reg, out,
+			       size);
 }
 
-static inline int tcpc_update8(int port, int reg,
-			       uint8_t mask,
+static inline int tcpc_update8(int port, int reg, uint8_t mask,
 			       enum mask_update_action action)
 {
 	return i2c_update8(tcpc_config[port].i2c_info.port,
-			   tcpc_config[port].i2c_info.addr_flags,
-			   reg, mask, action);
+			   tcpc_config[port].i2c_info.addr_flags, reg, mask,
+			   action);
 }
 
-static inline int tcpc_update16(int port, int reg,
-				uint16_t mask,
+static inline int tcpc_update16(int port, int reg, uint16_t mask,
 				enum mask_update_action action)
 {
 	return i2c_update16(tcpc_config[port].i2c_info.port,
-			    tcpc_config[port].i2c_info.addr_flags,
-			    reg, mask, action);
+			    tcpc_config[port].i2c_info.addr_flags, reg, mask,
+			    action);
 }
 
 #else /* !CONFIG_USB_PD_TCPC_LOW_POWER */
@@ -128,40 +122,40 @@ int tcpc_addr_read16(int port, int i2c_addr, int reg, int *val);
 int tcpc_addr_read16_no_lpm_exit(int port, int i2c_addr, int reg, int *val);
 int tcpc_read_block(int port, int reg, uint8_t *in, int size);
 int tcpc_write_block(int port, int reg, const uint8_t *out, int size);
-int tcpc_xfer(int port, const uint8_t *out, int out_size,
-		uint8_t *in, int in_size);
-int tcpc_xfer_unlocked(int port, const uint8_t *out, int out_size,
-		uint8_t *in, int in_size, int flags);
+int tcpc_xfer(int port, const uint8_t *out, int out_size, uint8_t *in,
+	      int in_size);
+int tcpc_xfer_unlocked(int port, const uint8_t *out, int out_size, uint8_t *in,
+		       int in_size, int flags);
 
-int tcpc_update8(int port, int reg,
-		 uint8_t mask, enum mask_update_action action);
-int tcpc_update16(int port, int reg,
-		  uint16_t mask, enum mask_update_action action);
+int tcpc_update8(int port, int reg, uint8_t mask,
+		 enum mask_update_action action);
+int tcpc_update16(int port, int reg, uint16_t mask,
+		  enum mask_update_action action);
 
 #endif /* CONFIG_USB_PD_TCPC_LOW_POWER */
 
 static inline int tcpc_write(int port, int reg, int val)
 {
-	return tcpc_addr_write(port,
-			       tcpc_config[port].i2c_info.addr_flags, reg, val);
+	return tcpc_addr_write(port, tcpc_config[port].i2c_info.addr_flags, reg,
+			       val);
 }
 
 static inline int tcpc_write16(int port, int reg, int val)
 {
-	return tcpc_addr_write16(port,
-			tcpc_config[port].i2c_info.addr_flags, reg, val);
+	return tcpc_addr_write16(port, tcpc_config[port].i2c_info.addr_flags,
+				 reg, val);
 }
 
 static inline int tcpc_read(int port, int reg, int *val)
 {
-	return tcpc_addr_read(port,
-			      tcpc_config[port].i2c_info.addr_flags, reg, val);
+	return tcpc_addr_read(port, tcpc_config[port].i2c_info.addr_flags, reg,
+			      val);
 }
 
 static inline int tcpc_read16(int port, int reg, int *val)
 {
-	return tcpc_addr_read16(port,
-			tcpc_config[port].i2c_info.addr_flags, reg, val);
+	return tcpc_addr_read16(port, tcpc_config[port].i2c_info.addr_flags,
+				reg, val);
 }
 
 static inline void tcpc_lock(int port, int lock)
@@ -191,7 +185,7 @@ static inline int tcpm_release(int port)
 }
 
 static inline int tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2)
+			      enum tcpc_cc_voltage_status *cc2)
 {
 	return tcpc_config[port].drv->get_cc(port, cc1, cc2);
 }
@@ -281,7 +275,8 @@ static inline int tcpm_transmit(int port, enum tcpci_msg_type type,
 static inline bool tcpm_get_snk_ctrl(int port)
 {
 	return tcpc_config[port].drv->get_snk_ctrl ?
-		tcpc_config[port].drv->get_snk_ctrl(port) : false;
+		       tcpc_config[port].drv->get_snk_ctrl(port) :
+		       false;
 }
 static inline int tcpm_set_snk_ctrl(int port, int enable)
 {
@@ -293,9 +288,9 @@ static inline int tcpm_set_snk_ctrl(int port, int enable)
 
 static inline bool tcpm_get_src_ctrl(int port)
 {
-
 	return tcpc_config[port].drv->get_src_ctrl ?
-		tcpc_config[port].drv->get_src_ctrl(port) : false;
+		       tcpc_config[port].drv->get_src_ctrl(port) :
+		       false;
 }
 static inline int tcpm_set_src_ctrl(int port, int enable)
 {
@@ -387,6 +382,13 @@ static inline int tcpm_get_chip_info(int port, int live,
 	return EC_ERROR_UNIMPLEMENTED;
 }
 
+static inline int tcpm_hard_reset_reinit(int port)
+{
+	if (tcpc_config[port].drv->hard_reset_reinit)
+		return tcpc_config[port].drv->hard_reset_reinit(port);
+	return EC_ERROR_UNIMPLEMENTED;
+}
+
 static inline enum ec_error_list tcpc_set_bist_test_mode(int port, bool enable)
 {
 	const struct tcpm_drv *tcpc;
@@ -398,6 +400,19 @@ static inline enum ec_error_list tcpc_set_bist_test_mode(int port, bool enable)
 	return rv;
 }
 
+static inline enum ec_error_list tcpc_get_bist_test_mode(int port, bool *enable)
+{
+	const struct tcpm_drv *tcpc;
+
+	tcpc = tcpc_config[port].drv;
+	if (tcpc->get_bist_test_mode)
+		return tcpc->get_bist_test_mode(port, enable);
+
+	*enable = false;
+
+	return EC_ERROR_UNIMPLEMENTED;
+}
+
 /*
  * Returns true if the port controls FRS using the TCPC.
  */
@@ -444,8 +459,8 @@ static inline int tcpm_set_frs_enable(int port, int enable)
 static inline int tcpc_set_sbu(int port, bool enable)
 {
 	return tcpc_config[port].drv->set_sbu ?
-		tcpc_config[port].drv->set_sbu(port, enable) :
-		EC_SUCCESS;
+		       tcpc_config[port].drv->set_sbu(port, enable) :
+		       EC_SUCCESS;
 }
 #endif /* CONFIG_USB_PD_TCPM_SBU */
 
@@ -470,7 +485,7 @@ int tcpm_init(int port);
  * @return EC_SUCCESS or error
  */
 int tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2);
+		enum tcpc_cc_voltage_status *cc2);
 
 /**
  * Check VBUS level
diff --git a/include/driver/tcpm/tusb422_public.h b/include/driver/tcpm/tusb422_public.h
index 8756d9b362..004abdd5c9 100644
--- a/include/driver/tcpm/tusb422_public.h
+++ b/include/driver/tcpm/tusb422_public.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/driver/temp_sensor/pct2075.h b/include/driver/temp_sensor/pct2075.h
index c09d0e383c..e79ac0e97a 100644
--- a/include/driver/temp_sensor/pct2075.h
+++ b/include/driver/temp_sensor/pct2075.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,10 +17,10 @@
 #define PCT2075_I2C_ADDR_FLAGS6 (0x4E | I2C_FLAG_BIG_ENDIAN)
 #define PCT2075_I2C_ADDR_FLAGS7 (0x4F | I2C_FLAG_BIG_ENDIAN)
 
-#define PCT2075_REG_TEMP	0x00
-#define PCT2075_REG_CONF	0x01
-#define PCT2075_REG_THYST	0x02
-#define PCT2075_REG_TOS		0x03
+#define PCT2075_REG_TEMP 0x00
+#define PCT2075_REG_CONF 0x01
+#define PCT2075_REG_THYST 0x02
+#define PCT2075_REG_TOS 0x03
 
 /*
  * I2C port and address information for all the board PCT2075 sensors should be
diff --git a/include/driver/temp_sensor/sb_tsi.h b/include/driver/temp_sensor/sb_tsi.h
index b7113dbc70..d8b015d200 100644
--- a/include/driver/temp_sensor/sb_tsi.h
+++ b/include/driver/temp_sensor/sb_tsi.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,27 +11,27 @@
 #ifndef __CROS_EC_SB_TSI_H
 #define __CROS_EC_SB_TSI_H
 
-#define SB_TSI_I2C_ADDR_FLAGS		0x4C
+#define SB_TSI_I2C_ADDR_FLAGS 0x4C
 
 /* G781 register */
-#define SB_TSI_TEMP_H			0x01
-#define SB_TSI_STATUS			0x02
-#define SB_TSI_CONFIG_1			0x03
-#define SB_TSI_UPDATE_RATE		0x04
-#define SB_TSI_HIGH_TEMP_THRESHOLD_H	0x07
-#define SB_TSI_LOW_TEMP_THRESHOLD_H	0x08
-#define SB_TSI_CONFIG_2			0x09
-#define SB_TSI_TEMP_L			0x10
-#define SB_TSI_TEMP_OFFSET_H		0x11
-#define SB_TSI_TEMP_OFFSET_L		0x12
-#define SB_TSI_HIGH_TEMP_THRESHOLD_L	0x13
-#define SB_TSI_LOW_TEMP_THRESHOLD_L	0x14
-#define SB_TSI_TIMEOUT_CONFIG		0x22
-#define SB_TSI_PSTATE_LIMIT_CONFIG	0x2F
-#define SB_TSI_ALERT_THRESHOLD		0x32
-#define SB_TSI_ALERT_CONFIG		0xBF
-#define SB_TSI_MANUFACTURE_ID		0xFE
-#define SB_TSI_REVISION			0xFF
+#define SB_TSI_TEMP_H 0x01
+#define SB_TSI_STATUS 0x02
+#define SB_TSI_CONFIG_1 0x03
+#define SB_TSI_UPDATE_RATE 0x04
+#define SB_TSI_HIGH_TEMP_THRESHOLD_H 0x07
+#define SB_TSI_LOW_TEMP_THRESHOLD_H 0x08
+#define SB_TSI_CONFIG_2 0x09
+#define SB_TSI_TEMP_L 0x10
+#define SB_TSI_TEMP_OFFSET_H 0x11
+#define SB_TSI_TEMP_OFFSET_L 0x12
+#define SB_TSI_HIGH_TEMP_THRESHOLD_L 0x13
+#define SB_TSI_LOW_TEMP_THRESHOLD_L 0x14
+#define SB_TSI_TIMEOUT_CONFIG 0x22
+#define SB_TSI_PSTATE_LIMIT_CONFIG 0x2F
+#define SB_TSI_ALERT_THRESHOLD 0x32
+#define SB_TSI_ALERT_CONFIG 0xBF
+#define SB_TSI_MANUFACTURE_ID 0xFE
+#define SB_TSI_REVISION 0xFF
 
 /**
  * Get the value of a sensor in K.
@@ -43,4 +43,4 @@
  */
 int sb_tsi_get_val(int idx, int *temp_ptr);
 
-#endif  /* __CROS_EC_SB_TSI_H */
+#endif /* __CROS_EC_SB_TSI_H */
diff --git a/include/driver/temp_sensor/thermistor.h b/include/driver/temp_sensor/thermistor.h
index adcd5c5be4..46b7763747 100644
--- a/include/driver/temp_sensor/thermistor.h
+++ b/include/driver/temp_sensor/thermistor.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,13 +9,13 @@
 #define __CROS_EC_TEMP_SENSOR_THERMISTOR_H
 
 struct thermistor_data_pair {
-	uint8_t mv;	/* Scaled voltage level at ADC (in mV) */
-	uint8_t temp;	/* Temperature in Celsius */
+	uint8_t mv; /* Scaled voltage level at ADC (in mV) */
+	uint8_t temp; /* Temperature in Celsius */
 };
 
 struct thermistor_info {
-	uint8_t scaling_factor;	/* Scaling factor for voltage in data pair. */
-	uint8_t num_pairs;	/* Number of data pairs. */
+	uint8_t scaling_factor; /* Scaling factor for voltage in data pair. */
+	uint8_t num_pairs; /* Number of data pairs. */
 
 	/*
 	 * Values between given data pairs will be calculated as points on
diff --git a/include/driver/temp_sensor/tmp112.h b/include/driver/temp_sensor/tmp112.h
index d1b97b138c..56d55d9133 100644
--- a/include/driver/temp_sensor/tmp112.h
+++ b/include/driver/temp_sensor/tmp112.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,10 +13,10 @@
 #define TMP112_I2C_ADDR_FLAGS2 (0x4A | I2C_FLAG_BIG_ENDIAN)
 #define TMP112_I2C_ADDR_FLAGS3 (0x4B | I2C_FLAG_BIG_ENDIAN)
 
-#define TMP112_REG_TEMP	0x00
-#define TMP112_REG_CONF	0x01
-#define TMP112_REG_HYST	0x02
-#define TMP112_REG_MAX	0x03
+#define TMP112_REG_TEMP 0x00
+#define TMP112_REG_CONF 0x01
+#define TMP112_REG_HYST 0x02
+#define TMP112_REG_MAX 0x03
 
 /*
  * I2C port and address information for all the board TMP112 sensors should be
diff --git a/include/driver/usb_mux/it5205_public.h b/include/driver/usb_mux/it5205_public.h
index 81dc326049..40590194c4 100644
--- a/include/driver/usb_mux/it5205_public.h
+++ b/include/driver/usb_mux/it5205_public.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/include/driver/usb_mux/ps8743_public.h b/include/driver/usb_mux/ps8743_public.h
index c20b948d07..64ba2d0cd7 100644
--- a/include/driver/usb_mux/ps8743_public.h
+++ b/include/driver/usb_mux/ps8743_public.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,69 +10,69 @@
 
 #include <inttypes.h>
 
-#define PS8743_I2C_ADDR0_FLAG    0x10
-#define PS8743_I2C_ADDR1_FLAG    0x11
-#define PS8743_I2C_ADDR2_FLAG    0x19
-#define PS8743_I2C_ADDR3_FLAG    0x1a
+#define PS8743_I2C_ADDR0_FLAG 0x10
+#define PS8743_I2C_ADDR1_FLAG 0x11
+#define PS8743_I2C_ADDR2_FLAG 0x19
+#define PS8743_I2C_ADDR3_FLAG 0x1a
 
 /* Mode register for setting mux */
 #define PS8743_REG_MODE 0x00
-#define PS8743_MODE_IN_HPD_ASSERT    BIT(0)
-#define PS8743_MODE_IN_HPD_CONTROL   BIT(1)
-#define PS8743_MODE_FLIP_ENABLE      BIT(2)
+#define PS8743_MODE_IN_HPD_ASSERT BIT(0)
+#define PS8743_MODE_IN_HPD_CONTROL BIT(1)
+#define PS8743_MODE_FLIP_ENABLE BIT(2)
 #define PS8743_MODE_FLIP_REG_CONTROL BIT(3)
-#define PS8743_MODE_USB_ENABLE       BIT(4)
-#define PS8743_MODE_USB_REG_CONTROL  BIT(5)
-#define PS8743_MODE_DP_ENABLE        BIT(6)
-#define PS8743_MODE_DP_REG_CONTROL   BIT(7)
+#define PS8743_MODE_USB_ENABLE BIT(4)
+#define PS8743_MODE_USB_REG_CONTROL BIT(5)
+#define PS8743_MODE_DP_ENABLE BIT(6)
+#define PS8743_MODE_DP_REG_CONTROL BIT(7)
 /* To reset the state machine to default */
-#define PS8743_MODE_POWER_DOWN (PS8743_MODE_USB_REG_CONTROL |  \
-				PS8743_MODE_DP_REG_CONTROL)
+#define PS8743_MODE_POWER_DOWN \
+	(PS8743_MODE_USB_REG_CONTROL | PS8743_MODE_DP_REG_CONTROL)
 /* DP output setting */
-#define PS8743_REG_DP_SETTING    0x07
-#define PS8743_DP_SWG_ADJ_DFLT   0x00
-#define PS8743_DP_SWG_ADJ_N20P   0x40
-#define PS8743_DP_SWG_ADJ_N15P   0x80
-#define PS8743_DP_SWG_ADJ_P15P   0xc0
-#define PS8743_DP_OUT_SWG_400    0x00
-#define PS8743_DP_OUT_SWG_600    0x10
-#define PS8743_DP_OUT_SWG_800    0x20
-#define PS8743_DP_OUT_SWG_1000   0x30
-#define PS8743_DP_OUT_PRE_EM_0_DB   0x00
+#define PS8743_REG_DP_SETTING 0x07
+#define PS8743_DP_SWG_ADJ_DFLT 0x00
+#define PS8743_DP_SWG_ADJ_N20P 0x40
+#define PS8743_DP_SWG_ADJ_N15P 0x80
+#define PS8743_DP_SWG_ADJ_P15P 0xc0
+#define PS8743_DP_OUT_SWG_400 0x00
+#define PS8743_DP_OUT_SWG_600 0x10
+#define PS8743_DP_OUT_SWG_800 0x20
+#define PS8743_DP_OUT_SWG_1000 0x30
+#define PS8743_DP_OUT_PRE_EM_0_DB 0x00
 #define PS8743_DP_OUT_PRE_EM_3_5_DB 0x04
 #define PS8743_DP_OUT_PRE_EM_6_0_DB 0x08
 #define PS8743_DP_OUT_PRE_EM_9_5_DB 0x0c
-#define PS8743_DP_POST_CUR2_0_DB       0x00
+#define PS8743_DP_POST_CUR2_0_DB 0x00
 #define PS8743_DP_POST_CUR2_NEG_0_9_DB 0x01
 #define PS8743_DP_POST_CUR2_NEG_1_9_DB 0x02
 #define PS8743_DP_POST_CUR2_NEG_3_1_DB 0x03
 
 /* USB equalization settings for Host to Mux */
-#define PS8743_REG_USB_EQ_TX     0x32
+#define PS8743_REG_USB_EQ_TX 0x32
 #define PS8743_USB_EQ_TX_12_8_DB 0x00
-#define PS8743_USB_EQ_TX_17_DB   0x20
-#define PS8743_USB_EQ_TX_7_7_DB  0x40
-#define PS8743_USB_EQ_TX_3_6_DB  0x60
-#define PS8743_USB_EQ_TX_15_DB   0x80
+#define PS8743_USB_EQ_TX_17_DB 0x20
+#define PS8743_USB_EQ_TX_7_7_DB 0x40
+#define PS8743_USB_EQ_TX_3_6_DB 0x60
+#define PS8743_USB_EQ_TX_15_DB 0x80
 #define PS8743_USB_EQ_TX_10_9_DB 0xc0
-#define PS8743_USB_EQ_TX_4_5_DB  0xe0
+#define PS8743_USB_EQ_TX_4_5_DB 0xe0
 
 /* USB swing adjust for Mux to Type-C connector */
-#define PS8743_REG_USB_SWING     0x36
-#define PS8743_OUT_SWG_DEFAULT   0x00
-#define PS8743_OUT_SWG_NEG_20    0x40
-#define PS8743_OUT_SWG_NEG_15    0x80
-#define PS8743_OUT_SWG_POS_15    0xc0
-#define PS8743_LFPS_SWG_DEFAULT  0x00
-#define PS8743_LFPS_SWG_TD       0x08
+#define PS8743_REG_USB_SWING 0x36
+#define PS8743_OUT_SWG_DEFAULT 0x00
+#define PS8743_OUT_SWG_NEG_20 0x40
+#define PS8743_OUT_SWG_NEG_15 0x80
+#define PS8743_OUT_SWG_POS_15 0xc0
+#define PS8743_LFPS_SWG_DEFAULT 0x00
+#define PS8743_LFPS_SWG_TD 0x08
 
 /* USB equalization settings for Connector to Mux */
-#define PS8743_REG_USB_EQ_RX     0x3b
-#define PS8743_USB_EQ_RX_2_4_DB  0x00
-#define PS8743_USB_EQ_RX_5_DB    0x10
-#define PS8743_USB_EQ_RX_6_5_DB  0x20
-#define PS8743_USB_EQ_RX_7_4_DB  0x30
-#define PS8743_USB_EQ_RX_8_7_DB  0x40
+#define PS8743_REG_USB_EQ_RX 0x3b
+#define PS8743_USB_EQ_RX_2_4_DB 0x00
+#define PS8743_USB_EQ_RX_5_DB 0x10
+#define PS8743_USB_EQ_RX_6_5_DB 0x20
+#define PS8743_USB_EQ_RX_7_4_DB 0x30
+#define PS8743_USB_EQ_RX_8_7_DB 0x40
 #define PS8743_USB_EQ_RX_10_9_DB 0x50
 #define PS8743_USB_EQ_RX_12_8_DB 0x60
 #define PS8743_USB_EQ_RX_13_8_DB 0x70
@@ -85,21 +85,21 @@
 #define PS8743_USB_EQ_RX_22_2_DB 0xe0
 
 /* USB High Speed Signal Detector thershold adjustment */
-#define PS8743_REG_HS_DET_THRESHOLD  0x3c
+#define PS8743_REG_HS_DET_THRESHOLD 0x3c
 #define PS8743_USB_HS_THRESH_DEFAULT 0x00
-#define PS8743_USB_HS_THRESH_POS_10  0x20
-#define PS8743_USB_HS_THRESH_POS_33  0x40
-#define PS8743_USB_HS_THRESH_NEG_10  0x60
-#define PS8743_USB_HS_THRESH_NEG_25  0x80
-#define PS8743_USB_HS_THRESH_POS_25  0xa0
-#define PS8743_USB_HS_THRESH_NEG_45  0xc0
-#define PS8743_USB_HS_THRESH_NEG_35  0xe0
+#define PS8743_USB_HS_THRESH_POS_10 0x20
+#define PS8743_USB_HS_THRESH_POS_33 0x40
+#define PS8743_USB_HS_THRESH_NEG_10 0x60
+#define PS8743_USB_HS_THRESH_NEG_25 0x80
+#define PS8743_USB_HS_THRESH_POS_25 0xa0
+#define PS8743_USB_HS_THRESH_NEG_45 0xc0
+#define PS8743_USB_HS_THRESH_NEG_35 0xe0
 
 /* DCI config: 0x45~0x4D */
-#define PS8743_REG_DCI_CONFIG_2        0x47
-#define PS8743_AUTO_DCI_MODE_SHIFT     6
-#define PS8743_AUTO_DCI_MODE_MASK      (3 << PS8743_AUTO_DCI_MODE_SHIFT)
-#define PS8743_AUTO_DCI_MODE_ENABLE    (0 << PS8743_AUTO_DCI_MODE_SHIFT)
+#define PS8743_REG_DCI_CONFIG_2 0x47
+#define PS8743_AUTO_DCI_MODE_SHIFT 6
+#define PS8743_AUTO_DCI_MODE_MASK (3 << PS8743_AUTO_DCI_MODE_SHIFT)
+#define PS8743_AUTO_DCI_MODE_ENABLE (0 << PS8743_AUTO_DCI_MODE_SHIFT)
 #define PS8743_AUTO_DCI_MODE_FORCE_USB (2 << PS8743_AUTO_DCI_MODE_SHIFT)
 #define PS8743_AUTO_DCI_MODE_FORCE_DCI (3 << PS8743_AUTO_DCI_MODE_SHIFT)
 
diff --git a/include/ec_commands.h b/include/ec_commands.h
index b11b34b5fd..a4ec6a00ed 100644
--- a/include/ec_commands.h
+++ b/include/ec_commands.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -32,7 +32,7 @@
 #ifndef BUILD_ASSERT
 #define BUILD_ASSERT(_cond)
 #endif /* !BUILD_ASSERT */
-#endif  /* CHROMIUM_EC */
+#endif /* CHROMIUM_EC */
 
 #ifdef __KERNEL__
 #include <linux/limits.h>
@@ -45,11 +45,11 @@
  */
 
 #ifndef BIT
-#define BIT(nr)         (1UL << (nr))
+#define BIT(nr) (1UL << (nr))
 #endif
 
 #ifndef BIT_ULL
-#define BIT_ULL(nr)     (1ULL << (nr))
+#define BIT_ULL(nr) (1ULL << (nr))
 #endif
 
 /*
@@ -67,12 +67,26 @@
 #endif
 #endif
 
-#endif  /* __KERNEL__ */
+#endif /* __KERNEL__ */
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+/**
+ * Constant for creation of flexible array members that work in both C and
+ * C++. Flexible array members were added in C99 and are not part of the C++
+ * standard. However, clang++ supports them for C++.
+ * When compiling with gcc, flexible array members are not allowed to appear
+ * in an otherwise empty struct, so we use the GCC zero-length array
+ * extension that works with both clang/gcc/g++.
+ */
+#if defined(__cplusplus) && defined(__clang__)
+#define FLEXIBLE_ARRAY_MEMBER_SIZE
+#else
+#define FLEXIBLE_ARRAY_MEMBER_SIZE 0
+#endif
+
 /*
  * Current version of this protocol
  *
@@ -80,28 +94,28 @@ extern "C" {
  * determined in other ways.  Remove this once the kernel code no longer
  * depends on it.
  */
-#define EC_PROTO_VERSION          0x00000002
+#define EC_PROTO_VERSION 0x00000002
 
 /* Command version mask */
 #define EC_VER_MASK(version) BIT(version)
 
 /* I/O addresses for ACPI commands */
-#define EC_LPC_ADDR_ACPI_DATA  0x62
-#define EC_LPC_ADDR_ACPI_CMD   0x66
+#define EC_LPC_ADDR_ACPI_DATA 0x62
+#define EC_LPC_ADDR_ACPI_CMD 0x66
 
 /* I/O addresses for host command */
-#define EC_LPC_ADDR_HOST_DATA  0x200
-#define EC_LPC_ADDR_HOST_CMD   0x204
+#define EC_LPC_ADDR_HOST_DATA 0x200
+#define EC_LPC_ADDR_HOST_CMD 0x204
 
 /* I/O addresses for host command args and params */
 /* Protocol version 2 */
-#define EC_LPC_ADDR_HOST_ARGS    0x800  /* And 0x801, 0x802, 0x803 */
-#define EC_LPC_ADDR_HOST_PARAM   0x804  /* For version 2 params; size is
-					 * EC_PROTO2_MAX_PARAM_SIZE
-					 */
+#define EC_LPC_ADDR_HOST_ARGS 0x800 /* And 0x801, 0x802, 0x803 */
+/* For version 2 params; size is EC_PROTO2_MAX_PARAM_SIZE */
+#define EC_LPC_ADDR_HOST_PARAM 0x804
+
 /* Protocol version 3 */
-#define EC_LPC_ADDR_HOST_PACKET  0x800  /* Offset of version 3 packet */
-#define EC_LPC_HOST_PACKET_SIZE  0x100  /* Max size of version 3 packet */
+#define EC_LPC_ADDR_HOST_PACKET 0x800 /* Offset of version 3 packet */
+#define EC_LPC_HOST_PACKET_SIZE 0x100 /* Max size of version 3 packet */
 
 /*
  * The actual block is 0x800-0x8ff, but some BIOSes think it's 0x880-0x8ff
@@ -110,66 +124,79 @@ extern "C" {
  * Other BIOSes report only the I/O port region spanned by the Microchip
  * MEC series EC; an attempt to address a larger region may fail.
  */
-#define EC_HOST_CMD_REGION0       0x800
-#define EC_HOST_CMD_REGION1       0x880
-#define EC_HOST_CMD_REGION_SIZE    0x80
+#define EC_HOST_CMD_REGION0 0x800
+#define EC_HOST_CMD_REGION1 0x880
+#define EC_HOST_CMD_REGION_SIZE 0x80
 #define EC_HOST_CMD_MEC_REGION_SIZE 0x8
 
 /* EC command register bit functions */
-#define EC_LPC_CMDR_DATA	BIT(0)  /* Data ready for host to read */
-#define EC_LPC_CMDR_PENDING	BIT(1)  /* Write pending to EC */
-#define EC_LPC_CMDR_BUSY	BIT(2)  /* EC is busy processing a command */
-#define EC_LPC_CMDR_CMD		BIT(3)  /* Last host write was a command */
-#define EC_LPC_CMDR_ACPI_BRST	BIT(4)  /* Burst mode (not used) */
-#define EC_LPC_CMDR_SCI		BIT(5)  /* SCI event is pending */
-#define EC_LPC_CMDR_SMI		BIT(6)  /* SMI event is pending */
-
-#define EC_LPC_ADDR_MEMMAP       0x900
-#define EC_MEMMAP_SIZE         255 /* ACPI IO buffer max is 255 bytes */
-#define EC_MEMMAP_TEXT_MAX     8   /* Size of a string in the memory map */
+#define EC_LPC_CMDR_DATA BIT(0) /* Data ready for host to read */
+#define EC_LPC_CMDR_PENDING BIT(1) /* Write pending to EC */
+#define EC_LPC_CMDR_BUSY BIT(2) /* EC is busy processing a command */
+#define EC_LPC_CMDR_CMD BIT(3) /* Last host write was a command */
+#define EC_LPC_CMDR_ACPI_BRST BIT(4) /* Burst mode (not used) */
+#define EC_LPC_CMDR_SCI BIT(5) /* SCI event is pending */
+#define EC_LPC_CMDR_SMI BIT(6) /* SMI event is pending */
+
+#define EC_LPC_ADDR_MEMMAP 0x900
+#define EC_MEMMAP_SIZE 255 /* ACPI IO buffer max is 255 bytes */
+#define EC_MEMMAP_TEXT_MAX 8 /* Size of a string in the memory map */
 
 /* The offset address of each type of data in mapped memory. */
-#define EC_MEMMAP_TEMP_SENSOR      0x00 /* Temp sensors 0x00 - 0x0f */
-#define EC_MEMMAP_FAN              0x10 /* Fan speeds 0x10 - 0x17 */
-#define EC_MEMMAP_TEMP_SENSOR_B    0x18 /* More temp sensors 0x18 - 0x1f */
-#define EC_MEMMAP_ID               0x20 /* 0x20 == 'E', 0x21 == 'C' */
-#define EC_MEMMAP_ID_VERSION       0x22 /* Version of data in 0x20 - 0x2f */
-#define EC_MEMMAP_THERMAL_VERSION  0x23 /* Version of data in 0x00 - 0x1f */
-#define EC_MEMMAP_BATTERY_VERSION  0x24 /* Version of data in 0x40 - 0x7f */
+#define EC_MEMMAP_TEMP_SENSOR 0x00 /* Temp sensors 0x00 - 0x0f */
+#define EC_MEMMAP_FAN 0x10 /* Fan speeds 0x10 - 0x17 */
+#define EC_MEMMAP_TEMP_SENSOR_B 0x18 /* More temp sensors 0x18 - 0x1f */
+#define EC_MEMMAP_ID 0x20 /* 0x20 == 'E', 0x21 == 'C' */
+#define EC_MEMMAP_ID_VERSION 0x22 /* Version of data in 0x20 - 0x2f */
+#define EC_MEMMAP_THERMAL_VERSION 0x23 /* Version of data in 0x00 - 0x1f */
+#define EC_MEMMAP_BATTERY_VERSION 0x24 /* Version of data in 0x40 - 0x7f */
 #define EC_MEMMAP_SWITCHES_VERSION 0x25 /* Version of data in 0x30 - 0x33 */
-#define EC_MEMMAP_EVENTS_VERSION   0x26 /* Version of data in 0x34 - 0x3f */
-#define EC_MEMMAP_HOST_CMD_FLAGS   0x27 /* Host cmd interface flags (8 bits) */
+#define EC_MEMMAP_EVENTS_VERSION 0x26 /* Version of data in 0x34 - 0x3f */
+#define EC_MEMMAP_HOST_CMD_FLAGS 0x27 /* Host cmd interface flags (8 bits) */
 /* Unused 0x28 - 0x2f */
-#define EC_MEMMAP_SWITCHES         0x30	/* 8 bits */
+#define EC_MEMMAP_SWITCHES 0x30 /* 8 bits */
 /* Unused 0x31 - 0x33 */
-#define EC_MEMMAP_HOST_EVENTS      0x34 /* 64 bits */
+#define EC_MEMMAP_HOST_EVENTS 0x34 /* 64 bits */
 /* Battery values are all 32 bits, unless otherwise noted. */
-#define EC_MEMMAP_BATT_VOLT        0x40 /* Battery Present Voltage */
-#define EC_MEMMAP_BATT_RATE        0x44 /* Battery Present Rate */
-#define EC_MEMMAP_BATT_CAP         0x48 /* Battery Remaining Capacity */
-#define EC_MEMMAP_BATT_FLAG        0x4c /* Battery State, see below (8-bit) */
-#define EC_MEMMAP_BATT_COUNT       0x4d /* Battery Count (8-bit) */
-#define EC_MEMMAP_BATT_INDEX       0x4e /* Current Battery Data Index (8-bit) */
+#define EC_MEMMAP_BATT_VOLT 0x40 /* Battery Present Voltage */
+#define EC_MEMMAP_BATT_RATE 0x44 /* Battery Present Rate */
+#define EC_MEMMAP_BATT_CAP 0x48 /* Battery Remaining Capacity */
+#define EC_MEMMAP_BATT_FLAG 0x4c /* Battery State, see below (8-bit) */
+#define EC_MEMMAP_BATT_COUNT 0x4d /* Battery Count (8-bit) */
+#define EC_MEMMAP_BATT_INDEX 0x4e /* Current Battery Data Index (8-bit) */
 /* Unused 0x4f */
-#define EC_MEMMAP_BATT_DCAP        0x50 /* Battery Design Capacity */
-#define EC_MEMMAP_BATT_DVLT        0x54 /* Battery Design Voltage */
-#define EC_MEMMAP_BATT_LFCC        0x58 /* Battery Last Full Charge Capacity */
-#define EC_MEMMAP_BATT_CCNT        0x5c /* Battery Cycle Count */
+#define EC_MEMMAP_BATT_DCAP 0x50 /* Battery Design Capacity */
+#define EC_MEMMAP_BATT_DVLT 0x54 /* Battery Design Voltage */
+#define EC_MEMMAP_BATT_LFCC 0x58 /* Battery Last Full Charge Capacity */
+#define EC_MEMMAP_BATT_CCNT 0x5c /* Battery Cycle Count */
 /* Strings are all 8 bytes (EC_MEMMAP_TEXT_MAX) */
-#define EC_MEMMAP_BATT_MFGR        0x60 /* Battery Manufacturer String */
-#define EC_MEMMAP_BATT_MODEL       0x68 /* Battery Model Number String */
-#define EC_MEMMAP_BATT_SERIAL      0x70 /* Battery Serial Number String */
-#define EC_MEMMAP_BATT_TYPE        0x78 /* Battery Type String */
-#define EC_MEMMAP_ALS              0x80 /* ALS readings in lux (2 X 16 bits) */
+#define EC_MEMMAP_BATT_MFGR 0x60 /* Battery Manufacturer String */
+#define EC_MEMMAP_BATT_MODEL 0x68 /* Battery Model Number String */
+#define EC_MEMMAP_BATT_SERIAL 0x70 /* Battery Serial Number String */
+#define EC_MEMMAP_BATT_TYPE 0x78 /* Battery Type String */
+#define EC_MEMMAP_ALS 0x80 /* ALS readings in lux (2 X 16 bits) */
 /* Unused 0x84 - 0x8f */
-#define EC_MEMMAP_ACC_STATUS       0x90 /* Accelerometer status (8 bits )*/
+#define EC_MEMMAP_ACC_STATUS 0x90 /* Accelerometer status (8 bits )*/
 /* Unused 0x91 */
-#define EC_MEMMAP_ACC_DATA         0x92 /* Accelerometers data 0x92 - 0x9f */
+#define EC_MEMMAP_ACC_DATA 0x92 /* Accelerometers data 0x92 - 0x9f */
 /* 0x92: Lid Angle if available, LID_ANGLE_UNRELIABLE otherwise */
 /* 0x94 - 0x99: 1st Accelerometer */
 /* 0x9a - 0x9f: 2nd Accelerometer */
-#define EC_MEMMAP_GYRO_DATA        0xa0 /* Gyroscope data 0xa0 - 0xa5 */
-/* Unused 0xa6 - 0xdf */
+
+#define EC_MEMMAP_GYRO_DATA 0xa0 /* Gyroscope data 0xa0 - 0xa5 */
+#define EC_MEMMAP_GPU 0xa6 /* GPU-specific, 8 bits */
+
+/*
+ * Bit fields for EC_MEMMAP_GPU
+ * 0:2: D-Notify level (0:D1, ... 4:D5)
+ * 3: Over temperature
+ */
+#define EC_MEMMAP_GPU_D_NOTIFY_MASK GENMASK(2, 0)
+#define EC_MEMMAP_GPU_OVERT_BIT BIT(3)
+
+/* Power Participant related components */
+#define EC_MEMMAP_PWR_SRC 0xa7 /* Power source (8-bit) */
+/* Unused 0xa8 - 0xdf */
 
 /*
  * ACPI is unable to access memory mapped data at or above this offset due to
@@ -179,82 +206,83 @@ extern "C" {
 #define EC_MEMMAP_NO_ACPI 0xe0
 
 /* Define the format of the accelerometer mapped memory status byte. */
-#define EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK  0x0f
-#define EC_MEMMAP_ACC_STATUS_BUSY_BIT        BIT(4)
-#define EC_MEMMAP_ACC_STATUS_PRESENCE_BIT    BIT(7)
+#define EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK 0x0f
+#define EC_MEMMAP_ACC_STATUS_BUSY_BIT BIT(4)
+#define EC_MEMMAP_ACC_STATUS_PRESENCE_BIT BIT(7)
 
 /* Number of temp sensors at EC_MEMMAP_TEMP_SENSOR */
-#define EC_TEMP_SENSOR_ENTRIES        16
+#define EC_TEMP_SENSOR_ENTRIES 16
 /*
  * Number of temp sensors at EC_MEMMAP_TEMP_SENSOR_B.
  *
  * Valid only if EC_MEMMAP_THERMAL_VERSION returns >= 2.
  */
-#define EC_TEMP_SENSOR_B_ENTRIES      8
+#define EC_TEMP_SENSOR_B_ENTRIES 8
 
 /* Max temp sensor entries for host commands */
-#define EC_MAX_TEMP_SENSOR_ENTRIES    (EC_TEMP_SENSOR_ENTRIES + \
-				       EC_TEMP_SENSOR_B_ENTRIES)
+#define EC_MAX_TEMP_SENSOR_ENTRIES \
+	(EC_TEMP_SENSOR_ENTRIES + EC_TEMP_SENSOR_B_ENTRIES)
 
 /* Special values for mapped temperature sensors */
-#define EC_TEMP_SENSOR_NOT_PRESENT    0xff
-#define EC_TEMP_SENSOR_ERROR          0xfe
-#define EC_TEMP_SENSOR_NOT_POWERED    0xfd
+#define EC_TEMP_SENSOR_NOT_PRESENT 0xff
+#define EC_TEMP_SENSOR_ERROR 0xfe
+#define EC_TEMP_SENSOR_NOT_POWERED 0xfd
 #define EC_TEMP_SENSOR_NOT_CALIBRATED 0xfc
 /*
  * The offset of temperature value stored in mapped memory.  This allows
  * reporting a temperature range of 200K to 454K = -73C to 181C.
  */
-#define EC_TEMP_SENSOR_OFFSET      200
+#define EC_TEMP_SENSOR_OFFSET 200
 
 /*
  * Number of ALS readings at EC_MEMMAP_ALS
  */
-#define EC_ALS_ENTRIES             2
+#define EC_ALS_ENTRIES 2
 
 /*
  * The default value a temperature sensor will return when it is present but
  * has not been read this boot.  This is a reasonable number to avoid
  * triggering alarms on the host.
  */
-#define EC_TEMP_SENSOR_DEFAULT     (296 - EC_TEMP_SENSOR_OFFSET)
+#define EC_TEMP_SENSOR_DEFAULT (296 - EC_TEMP_SENSOR_OFFSET)
 
-#define EC_FAN_SPEED_ENTRIES       4       /* Number of fans at EC_MEMMAP_FAN */
-#define EC_FAN_SPEED_NOT_PRESENT   0xffff  /* Entry not present */
-#define EC_FAN_SPEED_STALLED       0xfffe  /* Fan stalled */
+#define EC_FAN_SPEED_ENTRIES 4 /* Number of fans at EC_MEMMAP_FAN */
+#define EC_FAN_SPEED_NOT_PRESENT 0xffff /* Entry not present */
+#define EC_FAN_SPEED_STALLED 0xfffe /* Fan stalled */
 
 /* Battery bit flags at EC_MEMMAP_BATT_FLAG. */
-#define EC_BATT_FLAG_AC_PRESENT   0x01
+#define EC_BATT_FLAG_AC_PRESENT 0x01
 #define EC_BATT_FLAG_BATT_PRESENT 0x02
-#define EC_BATT_FLAG_DISCHARGING  0x04
-#define EC_BATT_FLAG_CHARGING     0x08
+#define EC_BATT_FLAG_DISCHARGING 0x04
+#define EC_BATT_FLAG_CHARGING 0x08
 #define EC_BATT_FLAG_LEVEL_CRITICAL 0x10
 /* Set if some of the static/dynamic data is invalid (or outdated). */
 #define EC_BATT_FLAG_INVALID_DATA 0x20
+#define EC_BATT_FLAG_CUT_OFF 0x40
 
 /* Switch flags at EC_MEMMAP_SWITCHES */
-#define EC_SWITCH_LID_OPEN               0x01
-#define EC_SWITCH_POWER_BUTTON_PRESSED   0x02
+#define EC_SWITCH_LID_OPEN 0x01
+#define EC_SWITCH_POWER_BUTTON_PRESSED 0x02
 #define EC_SWITCH_WRITE_PROTECT_DISABLED 0x04
 /* Was recovery requested via keyboard; now unused. */
-#define EC_SWITCH_IGNORE1		 0x08
+#define EC_SWITCH_IGNORE1 0x08
 /* Recovery requested via dedicated signal (from servo board) */
-#define EC_SWITCH_DEDICATED_RECOVERY     0x10
+#define EC_SWITCH_DEDICATED_RECOVERY 0x10
 /* Was fake developer mode switch; now unused.  Remove in next refactor. */
-#define EC_SWITCH_IGNORE0                0x20
+#define EC_SWITCH_IGNORE0 0x20
 
 /* Host command interface flags */
 /* Host command interface supports LPC args (LPC interface only) */
-#define EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED  0x01
+#define EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED 0x01
 /* Host command interface supports version 3 protocol */
-#define EC_HOST_CMD_FLAG_VERSION_3   0x02
+#define EC_HOST_CMD_FLAG_VERSION_3 0x02
 
 /* Wireless switch flags */
-#define EC_WIRELESS_SWITCH_ALL       ~0x00  /* All flags */
-#define EC_WIRELESS_SWITCH_WLAN       0x01  /* WLAN radio */
-#define EC_WIRELESS_SWITCH_BLUETOOTH  0x02  /* Bluetooth radio */
-#define EC_WIRELESS_SWITCH_WWAN       0x04  /* WWAN power */
-#define EC_WIRELESS_SWITCH_WLAN_POWER 0x08  /* WLAN power */
+#define EC_WIRELESS_SWITCH_ALL ~0x00 /* All flags */
+#define EC_WIRELESS_SWITCH_WLAN 0x01 /* WLAN radio */
+#define EC_WIRELESS_SWITCH_BLUETOOTH 0x02 /* Bluetooth radio */
+#define EC_WIRELESS_SWITCH_WWAN 0x04 /* WWAN power */
+#define EC_WIRELESS_SWITCH_WLAN_POWER 0x08 /* WLAN power */
 
 /*****************************************************************************/
 /*
@@ -322,19 +350,19 @@ extern "C" {
 /* Valid addresses in ACPI memory space, for read/write commands */
 
 /* Memory space version; set to EC_ACPI_MEM_VERSION_CURRENT */
-#define EC_ACPI_MEM_VERSION            0x00
+#define EC_ACPI_MEM_VERSION 0x00
 /*
  * Test location; writing value here updates test compliment byte to (0xff -
  * value).
  */
-#define EC_ACPI_MEM_TEST               0x01
+#define EC_ACPI_MEM_TEST 0x01
 /* Test compliment; writes here are ignored. */
-#define EC_ACPI_MEM_TEST_COMPLIMENT    0x02
+#define EC_ACPI_MEM_TEST_COMPLIMENT 0x02
 
 /* Keyboard backlight brightness percent (0 - 100) */
 #define EC_ACPI_MEM_KEYBOARD_BACKLIGHT 0x03
 /* DPTF Target Fan Duty (0-100, 0xff for auto/none) */
-#define EC_ACPI_MEM_FAN_DUTY           0x04
+#define EC_ACPI_MEM_FAN_DUTY 0x04
 
 /*
  * DPTF temp thresholds. Any of the EC's temp sensors can have up to two
@@ -351,9 +379,9 @@ extern "C" {
  * have tripped". Setting or enabling the thresholds for a sensor will clear
  * the unread event count for that sensor.
  */
-#define EC_ACPI_MEM_TEMP_ID            0x05
-#define EC_ACPI_MEM_TEMP_THRESHOLD     0x06
-#define EC_ACPI_MEM_TEMP_COMMIT        0x07
+#define EC_ACPI_MEM_TEMP_ID 0x05
+#define EC_ACPI_MEM_TEMP_THRESHOLD 0x06
+#define EC_ACPI_MEM_TEMP_COMMIT 0x07
 /*
  * Here are the bits for the COMMIT register:
  *   bit 0 selects the threshold index for the chosen sensor (0/1)
@@ -378,12 +406,12 @@ extern "C" {
  */
 
 /* DPTF battery charging current limit */
-#define EC_ACPI_MEM_CHARGING_LIMIT     0x08
+#define EC_ACPI_MEM_CHARGING_LIMIT 0x08
 
 /* Charging limit is specified in 64 mA steps */
-#define EC_ACPI_MEM_CHARGING_LIMIT_STEP_MA   64
+#define EC_ACPI_MEM_CHARGING_LIMIT_STEP_MA 64
 /* Value to disable DPTF battery charging limit */
-#define EC_ACPI_MEM_CHARGING_LIMIT_DISABLED  0xff
+#define EC_ACPI_MEM_CHARGING_LIMIT_DISABLED 0xff
 
 /*
  * Report device orientation
@@ -396,10 +424,10 @@ extern "C" {
  *   0         Tablet Mode Device Indicator (TBMD)
  */
 #define EC_ACPI_MEM_DEVICE_ORIENTATION 0x09
-#define EC_ACPI_MEM_TBMD_SHIFT         0
-#define EC_ACPI_MEM_TBMD_MASK          0x1
-#define EC_ACPI_MEM_DDPN_SHIFT         1
-#define EC_ACPI_MEM_DDPN_MASK          0x7
+#define EC_ACPI_MEM_TBMD_SHIFT 0
+#define EC_ACPI_MEM_TBMD_MASK 0x1
+#define EC_ACPI_MEM_DDPN_SHIFT 1
+#define EC_ACPI_MEM_DDPN_MASK 0x7
 
 /*
  * Report device features. Uses the same format as the host command, except:
@@ -422,7 +450,7 @@ extern "C" {
 #define EC_ACPI_MEM_DEVICE_FEATURES6 0x10
 #define EC_ACPI_MEM_DEVICE_FEATURES7 0x11
 
-#define EC_ACPI_MEM_BATTERY_INDEX    0x12
+#define EC_ACPI_MEM_BATTERY_INDEX 0x12
 
 /*
  * USB Port Power. Each bit indicates whether the corresponding USB ports' power
@@ -461,40 +489,38 @@ extern "C" {
 #define EC_ACPI_MEM_USB_RETIMER_FW_UPDATE 0x14
 
 #define USB_RETIMER_FW_UPDATE_OP_SHIFT 4
-#define USB_RETIMER_FW_UPDATE_ERR         0xfe
+#define USB_RETIMER_FW_UPDATE_ERR 0xfe
 #define USB_RETIMER_FW_UPDATE_INVALID_MUX 0xff
 /* Mask to clear unused MUX bits in retimer firmware update  */
-#define USB_RETIMER_FW_UPDATE_MUX_MASK	(USB_PD_MUX_USB_ENABLED       | \
-					USB_PD_MUX_DP_ENABLED         | \
-					USB_PD_MUX_SAFE_MODE          | \
-					USB_PD_MUX_TBT_COMPAT_ENABLED | \
-					USB_PD_MUX_USB4_ENABLED)
+#define USB_RETIMER_FW_UPDATE_MUX_MASK                          \
+	(USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED |       \
+	 USB_PD_MUX_SAFE_MODE | USB_PD_MUX_TBT_COMPAT_ENABLED | \
+	 USB_PD_MUX_USB4_ENABLED)
 
 /* Retimer firmware update operations */
 #define USB_RETIMER_FW_UPDATE_QUERY_PORT 0 /* Which ports has retimer */
 #define USB_RETIMER_FW_UPDATE_SUSPEND_PD 1 /* Suspend PD port */
-#define USB_RETIMER_FW_UPDATE_RESUME_PD  2 /* Resume PD port  */
-#define USB_RETIMER_FW_UPDATE_GET_MUX    3 /* Read current USB MUX  */
-#define USB_RETIMER_FW_UPDATE_SET_USB    4 /* Set MUX to USB mode   */
-#define USB_RETIMER_FW_UPDATE_SET_SAFE   5 /* Set MUX to Safe mode  */
-#define USB_RETIMER_FW_UPDATE_SET_TBT    6 /* Set MUX to TBT mode   */
+#define USB_RETIMER_FW_UPDATE_RESUME_PD 2 /* Resume PD port  */
+#define USB_RETIMER_FW_UPDATE_GET_MUX 3 /* Read current USB MUX  */
+#define USB_RETIMER_FW_UPDATE_SET_USB 4 /* Set MUX to USB mode   */
+#define USB_RETIMER_FW_UPDATE_SET_SAFE 5 /* Set MUX to Safe mode  */
+#define USB_RETIMER_FW_UPDATE_SET_TBT 6 /* Set MUX to TBT mode   */
 #define USB_RETIMER_FW_UPDATE_DISCONNECT 7 /* Set MUX to disconnect */
 
-#define EC_ACPI_MEM_USB_RETIMER_PORT(x)   ((x) & 0x0f)
+#define EC_ACPI_MEM_USB_RETIMER_PORT(x) ((x)&0x0f)
 #define EC_ACPI_MEM_USB_RETIMER_OP(x) \
-	(((x) & 0xf0) >> USB_RETIMER_FW_UPDATE_OP_SHIFT)
+	(((x)&0xf0) >> USB_RETIMER_FW_UPDATE_OP_SHIFT)
 
 /*
  * ACPI addresses 0x20 - 0xff map to EC_MEMMAP offset 0x00 - 0xdf.  This data
  * is read-only from the AP.  Added in EC_ACPI_MEM_VERSION 2.
  */
-#define EC_ACPI_MEM_MAPPED_BEGIN   0x20
-#define EC_ACPI_MEM_MAPPED_SIZE    0xe0
+#define EC_ACPI_MEM_MAPPED_BEGIN 0x20
+#define EC_ACPI_MEM_MAPPED_SIZE 0xe0
 
 /* Current version of ACPI memory address space */
 #define EC_ACPI_MEM_VERSION_CURRENT 2
 
-
 /*
  * This header file is used in coreboot both in C and ACPI code.  The ACPI code
  * is pre-processed to handle constants but the ASL compiler is unable to
@@ -514,7 +540,7 @@ extern "C" {
 #ifndef __aligned
 #define __aligned(x) __attribute__((aligned(x)))
 #endif
-#endif  /* __KERNEL__ */
+#endif /* __KERNEL__ */
 
 /*
  * Attributes for EC request and response packets.  Just defining __packed
@@ -581,7 +607,7 @@ extern "C" {
 #define __ec_todo_packed __packed
 #define __ec_todo_unpacked
 
-#else  /* !CONFIG_HOSTCMD_ALIGNED */
+#else /* !CONFIG_HOSTCMD_ALIGNED */
 
 /*
  * Packed structures make no assumption about alignment, so they do inefficient
@@ -596,25 +622,25 @@ extern "C" {
 #define __ec_todo_packed __packed
 #define __ec_todo_unpacked
 
-#endif  /* !CONFIG_HOSTCMD_ALIGNED */
+#endif /* !CONFIG_HOSTCMD_ALIGNED */
 
 /* LPC command status byte masks */
 /* EC has written a byte in the data register and host hasn't read it yet */
-#define EC_LPC_STATUS_TO_HOST     0x01
+#define EC_LPC_STATUS_TO_HOST 0x01
 /* Host has written a command/data byte and the EC hasn't read it yet */
-#define EC_LPC_STATUS_FROM_HOST   0x02
+#define EC_LPC_STATUS_FROM_HOST 0x02
 /* EC is processing a command */
-#define EC_LPC_STATUS_PROCESSING  0x04
+#define EC_LPC_STATUS_PROCESSING 0x04
 /* Last write to EC was a command, not data */
-#define EC_LPC_STATUS_LAST_CMD    0x08
+#define EC_LPC_STATUS_LAST_CMD 0x08
 /* EC is in burst mode */
-#define EC_LPC_STATUS_BURST_MODE  0x10
+#define EC_LPC_STATUS_BURST_MODE 0x10
 /* SCI event is pending (requesting SCI query) */
 #define EC_LPC_STATUS_SCI_PENDING 0x20
 /* SMI event is pending (requesting SMI query) */
 #define EC_LPC_STATUS_SMI_PENDING 0x40
 /* (reserved) */
-#define EC_LPC_STATUS_RESERVED    0x80
+#define EC_LPC_STATUS_RESERVED 0x80
 
 /*
  * EC is busy.  This covers both the EC processing a command, and the host has
@@ -635,21 +661,21 @@ enum ec_status {
 	EC_RES_INVALID_RESPONSE = 5,
 	EC_RES_INVALID_VERSION = 6,
 	EC_RES_INVALID_CHECKSUM = 7,
-	EC_RES_IN_PROGRESS = 8,		/* Accepted, command in progress */
-	EC_RES_UNAVAILABLE = 9,		/* No response available */
-	EC_RES_TIMEOUT = 10,		/* We got a timeout */
-	EC_RES_OVERFLOW = 11,		/* Table / data overflow */
-	EC_RES_INVALID_HEADER = 12,     /* Header contains invalid data */
-	EC_RES_REQUEST_TRUNCATED = 13,  /* Didn't get the entire request */
-	EC_RES_RESPONSE_TOO_BIG = 14,   /* Response was too big to handle */
-	EC_RES_BUS_ERROR = 15,		/* Communications bus error */
-	EC_RES_BUSY = 16,		/* Up but too busy.  Should retry */
-	EC_RES_INVALID_HEADER_VERSION = 17,  /* Header version invalid */
-	EC_RES_INVALID_HEADER_CRC = 18,      /* Header CRC invalid */
-	EC_RES_INVALID_DATA_CRC = 19,        /* Data CRC invalid */
-	EC_RES_DUP_UNAVAILABLE = 20,         /* Can't resend response */
-
-	EC_RES_MAX = UINT16_MAX		/**< Force enum to be 16 bits */
+	EC_RES_IN_PROGRESS = 8, /* Accepted, command in progress */
+	EC_RES_UNAVAILABLE = 9, /* No response available */
+	EC_RES_TIMEOUT = 10, /* We got a timeout */
+	EC_RES_OVERFLOW = 11, /* Table / data overflow */
+	EC_RES_INVALID_HEADER = 12, /* Header contains invalid data */
+	EC_RES_REQUEST_TRUNCATED = 13, /* Didn't get the entire request */
+	EC_RES_RESPONSE_TOO_BIG = 14, /* Response was too big to handle */
+	EC_RES_BUS_ERROR = 15, /* Communications bus error */
+	EC_RES_BUSY = 16, /* Up but too busy.  Should retry */
+	EC_RES_INVALID_HEADER_VERSION = 17, /* Header version invalid */
+	EC_RES_INVALID_HEADER_CRC = 18, /* Header CRC invalid */
+	EC_RES_INVALID_DATA_CRC = 19, /* Data CRC invalid */
+	EC_RES_DUP_UNAVAILABLE = 20, /* Can't resend response */
+
+	EC_RES_MAX = UINT16_MAX, /**< Force enum to be 16 bits */
 } __packed;
 BUILD_ASSERT(sizeof(enum ec_status) == sizeof(uint16_t));
 
@@ -673,7 +699,8 @@ enum host_event_code {
 	/* Event generated by a device attached to the EC */
 	EC_HOST_EVENT_DEVICE = 10,
 	EC_HOST_EVENT_THERMAL = 11,
-	EC_HOST_EVENT_USB_CHARGER = 12,
+	/* GPU related event. Formerly named EC_HOST_EVENT_USB_CHARGER. */
+	EC_HOST_EVENT_GPU = 12,
 	EC_HOST_EVENT_KEY_PRESSED = 13,
 	/*
 	 * EC has finished initializing the host interface.  The host can check
@@ -741,10 +768,50 @@ enum host_event_code {
 	 * raw event status via EC_MEMMAP_HOST_EVENTS but the LPC interface is
 	 * not initialized on the EC, or improperly configured on the host.
 	 */
-	EC_HOST_EVENT_INVALID = 32
+	EC_HOST_EVENT_INVALID = 32,
 };
 /* Host event mask */
-#define EC_HOST_EVENT_MASK(event_code) BIT_ULL((event_code) - 1)
+#define EC_HOST_EVENT_MASK(event_code) BIT_ULL((event_code)-1)
+
+/* clang-format off */
+#define HOST_EVENT_TEXT                                                        \
+	{                                                                      \
+		[EC_HOST_EVENT_NONE] = "NONE",                                 \
+		[EC_HOST_EVENT_LID_CLOSED] = "LID_CLOSED",                     \
+		[EC_HOST_EVENT_LID_OPEN] = "LID_OPEN",                         \
+		[EC_HOST_EVENT_POWER_BUTTON] = "POWER_BUTTON",                 \
+		[EC_HOST_EVENT_AC_CONNECTED] = "AC_CONNECTED",                 \
+		[EC_HOST_EVENT_AC_DISCONNECTED] = "AC_DISCONNECTED",           \
+		[EC_HOST_EVENT_BATTERY_LOW] = "BATTERY_LOW",                   \
+		[EC_HOST_EVENT_BATTERY_CRITICAL] = "BATTERY_CRITICAL",         \
+		[EC_HOST_EVENT_BATTERY] = "BATTERY",                           \
+		[EC_HOST_EVENT_THERMAL_THRESHOLD] = "THERMAL_THRESHOLD",       \
+		[EC_HOST_EVENT_DEVICE] = "DEVICE",                             \
+		[EC_HOST_EVENT_THERMAL] = "THERMAL",                           \
+		[EC_HOST_EVENT_GPU] = "GPU",                                   \
+		[EC_HOST_EVENT_KEY_PRESSED] = "KEY_PRESSED",                   \
+		[EC_HOST_EVENT_INTERFACE_READY] = "INTERFACE_READY",           \
+		[EC_HOST_EVENT_KEYBOARD_RECOVERY] = "KEYBOARD_RECOVERY",       \
+		[EC_HOST_EVENT_THERMAL_SHUTDOWN] = "THERMAL_SHUTDOWN",         \
+		[EC_HOST_EVENT_BATTERY_SHUTDOWN] = "BATTERY_SHUTDOWN",         \
+		[EC_HOST_EVENT_THROTTLE_START] = "THROTTLE_START",             \
+		[EC_HOST_EVENT_THROTTLE_STOP] = "THROTTLE_STOP",               \
+		[EC_HOST_EVENT_HANG_DETECT] = "HANG_DETECT",                   \
+		[EC_HOST_EVENT_HANG_REBOOT] = "HANG_REBOOT",                   \
+		[EC_HOST_EVENT_PD_MCU] = "PD_MCU",                             \
+		[EC_HOST_EVENT_BATTERY_STATUS] = "BATTERY_STATUS",             \
+		[EC_HOST_EVENT_PANIC] = "PANIC",                               \
+		[EC_HOST_EVENT_KEYBOARD_FASTBOOT] = "KEYBOARD_FASTBOOT",       \
+		[EC_HOST_EVENT_RTC] = "RTC",                                   \
+		[EC_HOST_EVENT_MKBP] = "MKBP",                                 \
+		[EC_HOST_EVENT_USB_MUX] = "USB_MUX",                           \
+		[EC_HOST_EVENT_MODE_CHANGE] = "MODE_CHANGE",                   \
+		[EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT] =                  \
+			"KEYBOARD_RECOVERY_HW_REINIT",                         \
+		[EC_HOST_EVENT_WOV] = "WOV",                                   \
+		[EC_HOST_EVENT_INVALID] = "INVALID",                           \
+	}
+/* clang-format on */
 
 /**
  * struct ec_lpc_host_args - Arguments at EC_LPC_ADDR_HOST_ARGS
@@ -779,7 +846,7 @@ struct ec_lpc_host_args {
  * response.  Command version is 0 and response data from EC is at
  * EC_LPC_ADDR_OLD_PARAM with unknown length.
  */
-#define EC_HOST_ARGS_FLAG_TO_HOST   0x02
+#define EC_HOST_ARGS_FLAG_TO_HOST 0x02
 
 /*****************************************************************************/
 /*
@@ -821,12 +888,12 @@ struct ec_lpc_host_args {
  * request, the AP will clock in bytes until it sees the framing byte, then
  * clock in the response packet.
  */
-#define EC_SPI_FRAME_START    0xec
+#define EC_SPI_FRAME_START 0xec
 
 /*
  * Padding bytes which are clocked out after the end of a response packet.
  */
-#define EC_SPI_PAST_END       0xed
+#define EC_SPI_PAST_END 0xed
 
 /*
  * EC is ready to receive, and has ignored the byte sent by the AP. EC expects
@@ -837,36 +904,36 @@ struct ec_lpc_host_args {
  *	 CS goes low. This macro has the Most Significant Bit set to zero,
  *	 so SDO will not be driven high when CS goes low.
  */
-#define EC_SPI_RX_READY       0x78
+#define EC_SPI_RX_READY 0x78
 
 /*
  * EC has started receiving the request from the AP, but hasn't started
  * processing it yet.
  */
-#define EC_SPI_RECEIVING      0xf9
+#define EC_SPI_RECEIVING 0xf9
 
 /* EC has received the entire request from the AP and is processing it. */
-#define EC_SPI_PROCESSING     0xfa
+#define EC_SPI_PROCESSING 0xfa
 
 /*
  * EC received bad data from the AP, such as a packet header with an invalid
  * length.  EC will ignore all data until chip select deasserts.
  */
-#define EC_SPI_RX_BAD_DATA    0xfb
+#define EC_SPI_RX_BAD_DATA 0xfb
 
 /*
  * EC received data from the AP before it was ready.  That is, the AP asserted
  * chip select and started clocking data before the EC was ready to receive it.
  * EC will ignore all data until chip select deasserts.
  */
-#define EC_SPI_NOT_READY      0xfc
+#define EC_SPI_NOT_READY 0xfc
 
 /*
  * EC was ready to receive a request from the AP.  EC has treated the byte sent
  * by the AP as part of a request packet, or (for old-style ECs) is processing
  * a fully received packet but is not ready to respond yet.
  */
-#define EC_SPI_OLD_READY      0xfd
+#define EC_SPI_OLD_READY 0xfd
 
 /*****************************************************************************/
 
@@ -888,22 +955,22 @@ struct ec_lpc_host_args {
  */
 #define EC_PROTO2_REQUEST_HEADER_BYTES 3
 #define EC_PROTO2_REQUEST_TRAILER_BYTES 1
-#define EC_PROTO2_REQUEST_OVERHEAD (EC_PROTO2_REQUEST_HEADER_BYTES +	\
-				    EC_PROTO2_REQUEST_TRAILER_BYTES)
+#define EC_PROTO2_REQUEST_OVERHEAD \
+	(EC_PROTO2_REQUEST_HEADER_BYTES + EC_PROTO2_REQUEST_TRAILER_BYTES)
 
 #define EC_PROTO2_RESPONSE_HEADER_BYTES 2
 #define EC_PROTO2_RESPONSE_TRAILER_BYTES 1
-#define EC_PROTO2_RESPONSE_OVERHEAD (EC_PROTO2_RESPONSE_HEADER_BYTES +	\
-				     EC_PROTO2_RESPONSE_TRAILER_BYTES)
+#define EC_PROTO2_RESPONSE_OVERHEAD \
+	(EC_PROTO2_RESPONSE_HEADER_BYTES + EC_PROTO2_RESPONSE_TRAILER_BYTES)
 
 /* Parameter length was limited by the LPC interface */
 #define EC_PROTO2_MAX_PARAM_SIZE 0xfc
 
 /* Maximum request and response packet sizes for protocol version 2 */
-#define EC_PROTO2_MAX_REQUEST_SIZE (EC_PROTO2_REQUEST_OVERHEAD +	\
-				    EC_PROTO2_MAX_PARAM_SIZE)
-#define EC_PROTO2_MAX_RESPONSE_SIZE (EC_PROTO2_RESPONSE_OVERHEAD +	\
-				     EC_PROTO2_MAX_PARAM_SIZE)
+#define EC_PROTO2_MAX_REQUEST_SIZE \
+	(EC_PROTO2_REQUEST_OVERHEAD + EC_PROTO2_MAX_PARAM_SIZE)
+#define EC_PROTO2_MAX_RESPONSE_SIZE \
+	(EC_PROTO2_RESPONSE_OVERHEAD + EC_PROTO2_MAX_PARAM_SIZE)
 
 /*****************************************************************************/
 
@@ -1075,15 +1142,15 @@ struct ec_host_response4 {
 } __ec_align4;
 
 /* Fields in fields0 byte */
-#define EC_PACKET4_0_STRUCT_VERSION_MASK	0x0f
-#define EC_PACKET4_0_IS_RESPONSE_MASK		0x10
-#define EC_PACKET4_0_SEQ_NUM_SHIFT		5
-#define EC_PACKET4_0_SEQ_NUM_MASK		0x60
-#define EC_PACKET4_0_SEQ_DUP_MASK		0x80
+#define EC_PACKET4_0_STRUCT_VERSION_MASK 0x0f
+#define EC_PACKET4_0_IS_RESPONSE_MASK 0x10
+#define EC_PACKET4_0_SEQ_NUM_SHIFT 5
+#define EC_PACKET4_0_SEQ_NUM_MASK 0x60
+#define EC_PACKET4_0_SEQ_DUP_MASK 0x80
 
 /* Fields in fields1 byte */
-#define EC_PACKET4_1_COMMAND_VERSION_MASK	0x1f  /* (request only) */
-#define EC_PACKET4_1_DATA_CRC_PRESENT_MASK	0x80
+#define EC_PACKET4_1_COMMAND_VERSION_MASK 0x1f /* (request only) */
+#define EC_PACKET4_1_DATA_CRC_PRESENT_MASK 0x80
 
 /*****************************************************************************/
 /*
@@ -1157,7 +1224,7 @@ enum ec_image {
 	EC_IMAGE_RW,
 	EC_IMAGE_RW_A = EC_IMAGE_RW,
 	EC_IMAGE_RO_B,
-	EC_IMAGE_RW_B
+	EC_IMAGE_RW_B,
 };
 
 /**
@@ -1170,7 +1237,7 @@ enum ec_image {
 struct ec_response_get_version {
 	char version_string_ro[32];
 	char version_string_rw[32];
-	char reserved[32];  /* Changed to cros_fwid_ro in version 1 */
+	char reserved[32]; /* Changed to cros_fwid_ro in version 1 */
 	uint32_t current_image;
 } __ec_align4;
 
@@ -1190,9 +1257,9 @@ struct ec_response_get_version {
 struct ec_response_get_version_v1 {
 	char version_string_ro[32];
 	char version_string_rw[32];
-	char cros_fwid_ro[32];  /* Added in version 1 (Used to be reserved) */
+	char cros_fwid_ro[32]; /* Added in version 1 (Used to be reserved) */
 	uint32_t current_image;
-	char cros_fwid_rw[32];  /* Added in version 1 */
+	char cros_fwid_rw[32]; /* Added in version 1 */
 } __ec_align4;
 
 /* Read test */
@@ -1305,11 +1372,11 @@ struct ec_response_get_cmd_versions {
  * lpc must read the status from the command register. Attempting this on
  * lpc will overwrite the args/parameter space and corrupt its data.
  */
-#define EC_CMD_GET_COMMS_STATUS		0x0009
+#define EC_CMD_GET_COMMS_STATUS 0x0009
 
 /* Avoid using ec_status which is for return values */
 enum ec_comms_status {
-	EC_COMMS_STATUS_PROCESSING	= BIT(0),	/* Processing cmd */
+	EC_COMMS_STATUS_PROCESSING = BIT(0), /* Processing cmd */
 };
 
 /**
@@ -1318,11 +1385,11 @@ enum ec_comms_status {
  * @flags: Mask of enum ec_comms_status.
  */
 struct ec_response_get_comms_status {
-	uint32_t flags;		/* Mask of enum ec_comms_status */
+	uint32_t flags; /* Mask of enum ec_comms_status */
 } __ec_align4;
 
 /* Fake a variety of responses, purely for testing purposes. */
-#define EC_CMD_TEST_PROTOCOL		0x000A
+#define EC_CMD_TEST_PROTOCOL 0x000A
 
 /* Tell the EC what to send back to us. */
 struct ec_params_test_protocol {
@@ -1337,7 +1404,7 @@ struct ec_response_test_protocol {
 } __ec_align4;
 
 /* Get protocol information */
-#define EC_CMD_GET_PROTOCOL_INFO	0x000B
+#define EC_CMD_GET_PROTOCOL_INFO 0x000B
 
 /* Flags for ec_response_get_protocol_info.flags */
 /* EC_RES_IN_PROGRESS may be returned if a command is slow */
@@ -1359,12 +1426,11 @@ struct ec_response_get_protocol_info {
 	uint32_t flags;
 } __ec_align4;
 
-
 /*****************************************************************************/
 /* Get/Set miscellaneous values */
 
 /* The upper byte of .flags tells what to do (nothing means "get") */
-#define EC_GSV_SET        0x80000000
+#define EC_GSV_SET 0x80000000
 
 /*
  * The lower three bytes of .flags identifies the parameter, if that has
@@ -1383,11 +1449,11 @@ struct ec_response_get_set_value {
 } __ec_align4;
 
 /* More than one command can use these structs to get/set parameters. */
-#define EC_CMD_GSV_PAUSE_IN_S5	0x000C
+#define EC_CMD_GSV_PAUSE_IN_S5 0x000C
 
 /*****************************************************************************/
 /* List the features supported by the firmware */
-#define EC_CMD_GET_FEATURES  0x000D
+#define EC_CMD_GET_FEATURES 0x000D
 
 /* Supported features */
 enum ec_feature_code {
@@ -1518,6 +1584,10 @@ enum ec_feature_code {
 	 * The EC supports entering and residing in S4.
 	 */
 	EC_FEATURE_S4_RESIDENCY = 44,
+	/*
+	 * The EC supports the AP directing mux sets for the board.
+	 */
+	EC_FEATURE_TYPEC_AP_MUX_SET = 45,
 };
 
 #define EC_FEATURE_MASK_0(event_code) BIT(event_code % 32)
@@ -1688,8 +1758,15 @@ struct ec_params_flash_read {
 struct ec_params_flash_write {
 	uint32_t offset;
 	uint32_t size;
-	/* Followed by data to write */
+	/* Followed by data to write. This union allows accessing an
+	 * underlying buffer as uint32s or uint8s for convenience.
+	 */
+	union {
+		uint32_t words32[FLEXIBLE_ARRAY_MEMBER_SIZE];
+		uint8_t bytes[FLEXIBLE_ARRAY_MEMBER_SIZE];
+	} data;
 } __ec_align4;
+BUILD_ASSERT(member_size(struct ec_params_flash_write, data) == 0);
 
 /* Erase flash */
 #define EC_CMD_FLASH_ERASE 0x0013
@@ -1722,9 +1799,9 @@ struct ec_params_flash_erase {
  * permitted while erasing. (For instance, STM32F4).
  */
 enum ec_flash_erase_cmd {
-	FLASH_ERASE_SECTOR,     /* Erase and wait for result */
-	FLASH_ERASE_SECTOR_ASYNC,  /* Erase and return immediately. */
-	FLASH_ERASE_GET_RESULT,  /* Ask for last erase result */
+	FLASH_ERASE_SECTOR, /* Erase and wait for result */
+	FLASH_ERASE_SECTOR_ASYNC, /* Erase and return immediately. */
+	FLASH_ERASE_GET_RESULT, /* Ask for last erase result */
 };
 
 /**
@@ -1735,8 +1812,8 @@ enum ec_flash_erase_cmd {
  * @params: Same as v0 parameters.
  */
 struct ec_params_flash_erase_v1 {
-	uint8_t  cmd;
-	uint8_t  reserved;
+	uint8_t cmd;
+	uint8_t reserved;
 	uint16_t flag;
 	struct ec_params_flash_erase params;
 } __ec_align4;
@@ -1752,22 +1829,22 @@ struct ec_params_flash_erase_v1 {
  * If mask=0, simply returns the current flags state.
  */
 #define EC_CMD_FLASH_PROTECT 0x0015
-#define EC_VER_FLASH_PROTECT 1  /* Command version 1 */
+#define EC_VER_FLASH_PROTECT 1 /* Command version 1 */
 
 /* Flags for flash protection */
 /* RO flash code protected when the EC boots */
-#define EC_FLASH_PROTECT_RO_AT_BOOT         BIT(0)
+#define EC_FLASH_PROTECT_RO_AT_BOOT BIT(0)
 /*
  * RO flash code protected now.  If this bit is set, at-boot status cannot
  * be changed.
  */
-#define EC_FLASH_PROTECT_RO_NOW             BIT(1)
+#define EC_FLASH_PROTECT_RO_NOW BIT(1)
 /* Entire flash code protected now, until reboot. */
-#define EC_FLASH_PROTECT_ALL_NOW            BIT(2)
+#define EC_FLASH_PROTECT_ALL_NOW BIT(2)
 /* Flash write protect GPIO is asserted now */
-#define EC_FLASH_PROTECT_GPIO_ASSERTED      BIT(3)
+#define EC_FLASH_PROTECT_GPIO_ASSERTED BIT(3)
 /* Error - at least one bank of flash is stuck locked, and cannot be unlocked */
-#define EC_FLASH_PROTECT_ERROR_STUCK        BIT(4)
+#define EC_FLASH_PROTECT_ERROR_STUCK BIT(4)
 /*
  * Error - flash protection is in inconsistent state.  At least one bank of
  * flash which should be protected is not protected.  Usually fixed by
@@ -1775,18 +1852,17 @@ struct ec_params_flash_erase_v1 {
  */
 #define EC_FLASH_PROTECT_ERROR_INCONSISTENT BIT(5)
 /* Entire flash code protected when the EC boots */
-#define EC_FLASH_PROTECT_ALL_AT_BOOT        BIT(6)
+#define EC_FLASH_PROTECT_ALL_AT_BOOT BIT(6)
 /* RW flash code protected when the EC boots */
-#define EC_FLASH_PROTECT_RW_AT_BOOT         BIT(7)
+#define EC_FLASH_PROTECT_RW_AT_BOOT BIT(7)
 /* RW flash code protected now. */
-#define EC_FLASH_PROTECT_RW_NOW             BIT(8)
+#define EC_FLASH_PROTECT_RW_NOW BIT(8)
 /* Rollback information flash region protected when the EC boots */
-#define EC_FLASH_PROTECT_ROLLBACK_AT_BOOT   BIT(9)
+#define EC_FLASH_PROTECT_ROLLBACK_AT_BOOT BIT(9)
 /* Rollback information flash region protected now */
-#define EC_FLASH_PROTECT_ROLLBACK_NOW       BIT(10)
+#define EC_FLASH_PROTECT_ROLLBACK_NOW BIT(10)
 /* Error - Unknown error */
-#define EC_FLASH_PROTECT_ERROR_UNKNOWN      BIT(11)
-
+#define EC_FLASH_PROTECT_ERROR_UNKNOWN BIT(11)
 
 /**
  * struct ec_params_flash_protect - Parameters for the flash protect command.
@@ -1865,34 +1941,6 @@ struct ec_response_flash_region_info {
 	uint32_t size;
 } __ec_align4;
 
-/*
- * Read/write VbNvContext
- *
- * Deprecated as of February 2021.  No current devices use VBNV in EC
- * BBRAM anymore, so this is guaranteed to fail.
- *
- * TODO(b/178689388): remove from this header once no external
- * dependencies reference these constants.
- */
-#define EC_CMD_VBNV_CONTEXT 0x0017
-#define EC_VER_VBNV_CONTEXT 1
-#define EC_VBNV_BLOCK_SIZE 16
-
-enum ec_vbnvcontext_op {
-	EC_VBNV_CONTEXT_OP_READ,
-	EC_VBNV_CONTEXT_OP_WRITE,
-};
-
-struct ec_params_vbnvcontext {
-	uint32_t op;
-	uint8_t block[EC_VBNV_BLOCK_SIZE];
-} __ec_align4;
-
-struct ec_response_vbnvcontext {
-	uint8_t block[EC_VBNV_BLOCK_SIZE];
-} __ec_align4;
-
-
 /* Get SPI flash information */
 #define EC_CMD_FLASH_SPI_INFO 0x0018
 
@@ -1910,7 +1958,6 @@ struct ec_response_flash_spi_info {
 	uint8_t sr1, sr2;
 } __ec_align1;
 
-
 /* Select flash during flash operations */
 #define EC_CMD_FLASH_SELECT 0x0019
 
@@ -1922,24 +1969,26 @@ struct ec_params_flash_select {
 	uint8_t select;
 } __ec_align4;
 
-
 /**
  * Request random numbers to be generated and returned.
  * Can be used to test the random number generator is truly random.
  * See https://csrc.nist.gov/publications/detail/sp/800-22/rev-1a/final and
  * https://webhome.phy.duke.edu/~rgb/General/dieharder.php.
  */
-#define EC_CMD_RAND_NUM	0x001A
+#define EC_CMD_RAND_NUM 0x001A
 #define EC_VER_RAND_NUM 0
 
 struct ec_params_rand_num {
-	uint16_t num_rand_bytes;	/**< num random bytes to generate */
+	uint16_t num_rand_bytes; /**< num random bytes to generate */
 } __ec_align4;
 
 struct ec_response_rand_num {
-	uint8_t rand[0];		/**< generated random numbers */
-} __ec_align4;
-
+	/**
+	 * generated random numbers in the range of 1 to EC_MAX_INSIZE. The true
+	 * size of rand is determined by ec_params_rand_num's num_rand_bytes.
+	 */
+	uint8_t rand[FLEXIBLE_ARRAY_MEMBER_SIZE];
+} __ec_align1;
 BUILD_ASSERT(sizeof(struct ec_response_rand_num) == 0);
 
 /**
@@ -2005,9 +2054,9 @@ enum sysinfo_flags {
 };
 
 struct ec_response_sysinfo {
-	uint32_t reset_flags;		/**< EC_RESET_FLAG_* flags */
-	uint32_t current_image;		/**< enum ec_current_image */
-	uint32_t flags;			/**< enum sysinfo_flags */
+	uint32_t reset_flags; /**< EC_RESET_FLAG_* flags */
+	uint32_t current_image; /**< enum ec_current_image */
+	uint32_t flags; /**< enum sysinfo_flags */
 } __ec_align4;
 
 /*****************************************************************************/
@@ -2080,20 +2129,20 @@ enum ec_pwm_type {
 };
 
 struct ec_params_pwm_set_duty {
-	uint16_t duty;     /* Duty cycle, EC_PWM_MAX_DUTY = 100% */
-	uint8_t pwm_type;  /* ec_pwm_type */
-	uint8_t index;     /* Type-specific index, or 0 if unique */
+	uint16_t duty; /* Duty cycle, EC_PWM_MAX_DUTY = 100% */
+	uint8_t pwm_type; /* ec_pwm_type */
+	uint8_t index; /* Type-specific index, or 0 if unique */
 } __ec_align4;
 
 #define EC_CMD_PWM_GET_DUTY 0x0026
 
 struct ec_params_pwm_get_duty {
-	uint8_t pwm_type;  /* ec_pwm_type */
-	uint8_t index;     /* Type-specific index, or 0 if unique */
+	uint8_t pwm_type; /* ec_pwm_type */
+	uint8_t index; /* Type-specific index, or 0 if unique */
 } __ec_align1;
 
 struct ec_response_pwm_get_duty {
-	uint16_t duty;     /* Duty cycle, EC_PWM_MAX_DUTY = 100% */
+	uint16_t duty; /* Duty cycle, EC_PWM_MAX_DUTY = 100% */
 } __ec_align2;
 
 /*****************************************************************************/
@@ -2120,8 +2169,8 @@ struct lightbar_params_v0 {
 	int32_t google_ramp_up;
 	int32_t google_ramp_down;
 	int32_t s3s0_ramp_up;
-	int32_t s0_tick_delay[2];		/* AC=0/1 */
-	int32_t s0a_tick_delay[2];		/* AC=0/1 */
+	int32_t s0_tick_delay[2]; /* AC=0/1 */
+	int32_t s0a_tick_delay[2]; /* AC=0/1 */
 	int32_t s0s3_ramp_down;
 	int32_t s3_sleep_for;
 	int32_t s3_ramp_up;
@@ -2129,24 +2178,24 @@ struct lightbar_params_v0 {
 
 	/* Oscillation */
 	uint8_t new_s0;
-	uint8_t osc_min[2];			/* AC=0/1 */
-	uint8_t osc_max[2];			/* AC=0/1 */
-	uint8_t w_ofs[2];			/* AC=0/1 */
+	uint8_t osc_min[2]; /* AC=0/1 */
+	uint8_t osc_max[2]; /* AC=0/1 */
+	uint8_t w_ofs[2]; /* AC=0/1 */
 
 	/* Brightness limits based on the backlight and AC. */
-	uint8_t bright_bl_off_fixed[2];		/* AC=0/1 */
-	uint8_t bright_bl_on_min[2];		/* AC=0/1 */
-	uint8_t bright_bl_on_max[2];		/* AC=0/1 */
+	uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */
+	uint8_t bright_bl_on_min[2]; /* AC=0/1 */
+	uint8_t bright_bl_on_max[2]; /* AC=0/1 */
 
 	/* Battery level thresholds */
 	uint8_t battery_threshold[LB_BATTERY_LEVELS - 1];
 
 	/* Map [AC][battery_level] to color index */
-	uint8_t s0_idx[2][LB_BATTERY_LEVELS];	/* AP is running */
-	uint8_t s3_idx[2][LB_BATTERY_LEVELS];	/* AP is sleeping */
+	uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */
+	uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */
 
 	/* Color palette */
-	struct rgb_s color[8];			/* 0-3 are Google colors */
+	struct rgb_s color[8]; /* 0-3 are Google colors */
 } __ec_todo_packed;
 
 struct lightbar_params_v1 {
@@ -2154,8 +2203,8 @@ struct lightbar_params_v1 {
 	int32_t google_ramp_up;
 	int32_t google_ramp_down;
 	int32_t s3s0_ramp_up;
-	int32_t s0_tick_delay[2];		/* AC=0/1 */
-	int32_t s0a_tick_delay[2];		/* AC=0/1 */
+	int32_t s0_tick_delay[2]; /* AC=0/1 */
+	int32_t s0a_tick_delay[2]; /* AC=0/1 */
 	int32_t s0s3_ramp_down;
 	int32_t s3_sleep_for;
 	int32_t s3_ramp_up;
@@ -2175,27 +2224,27 @@ struct lightbar_params_v1 {
 	uint8_t tap_idx[3];
 
 	/* Oscillation */
-	uint8_t osc_min[2];			/* AC=0/1 */
-	uint8_t osc_max[2];			/* AC=0/1 */
-	uint8_t w_ofs[2];			/* AC=0/1 */
+	uint8_t osc_min[2]; /* AC=0/1 */
+	uint8_t osc_max[2]; /* AC=0/1 */
+	uint8_t w_ofs[2]; /* AC=0/1 */
 
 	/* Brightness limits based on the backlight and AC. */
-	uint8_t bright_bl_off_fixed[2];		/* AC=0/1 */
-	uint8_t bright_bl_on_min[2];		/* AC=0/1 */
-	uint8_t bright_bl_on_max[2];		/* AC=0/1 */
+	uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */
+	uint8_t bright_bl_on_min[2]; /* AC=0/1 */
+	uint8_t bright_bl_on_max[2]; /* AC=0/1 */
 
 	/* Battery level thresholds */
 	uint8_t battery_threshold[LB_BATTERY_LEVELS - 1];
 
 	/* Map [AC][battery_level] to color index */
-	uint8_t s0_idx[2][LB_BATTERY_LEVELS];	/* AP is running */
-	uint8_t s3_idx[2][LB_BATTERY_LEVELS];	/* AP is sleeping */
+	uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */
+	uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */
 
 	/* s5: single color pulse on inhibited power-up */
 	uint8_t s5_idx;
 
 	/* Color palette */
-	struct rgb_s color[8];			/* 0-3 are Google colors */
+	struct rgb_s color[8]; /* 0-3 are Google colors */
 } __ec_todo_packed;
 
 /* Lightbar command params v2
@@ -2212,8 +2261,8 @@ struct lightbar_params_v2_timing {
 	int32_t google_ramp_up;
 	int32_t google_ramp_down;
 	int32_t s3s0_ramp_up;
-	int32_t s0_tick_delay[2];		/* AC=0/1 */
-	int32_t s0a_tick_delay[2];		/* AC=0/1 */
+	int32_t s0_tick_delay[2]; /* AC=0/1 */
+	int32_t s0a_tick_delay[2]; /* AC=0/1 */
 	int32_t s0s3_ramp_down;
 	int32_t s3_sleep_for;
 	int32_t s3_ramp_up;
@@ -2237,16 +2286,16 @@ struct lightbar_params_v2_tap {
 
 struct lightbar_params_v2_oscillation {
 	/* Oscillation */
-	uint8_t osc_min[2];			/* AC=0/1 */
-	uint8_t osc_max[2];			/* AC=0/1 */
-	uint8_t w_ofs[2];			/* AC=0/1 */
+	uint8_t osc_min[2]; /* AC=0/1 */
+	uint8_t osc_max[2]; /* AC=0/1 */
+	uint8_t w_ofs[2]; /* AC=0/1 */
 } __ec_todo_packed;
 
 struct lightbar_params_v2_brightness {
 	/* Brightness limits based on the backlight and AC. */
-	uint8_t bright_bl_off_fixed[2];		/* AC=0/1 */
-	uint8_t bright_bl_on_min[2];		/* AC=0/1 */
-	uint8_t bright_bl_on_max[2];		/* AC=0/1 */
+	uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */
+	uint8_t bright_bl_on_min[2]; /* AC=0/1 */
+	uint8_t bright_bl_on_max[2]; /* AC=0/1 */
 } __ec_todo_packed;
 
 struct lightbar_params_v2_thresholds {
@@ -2256,14 +2305,14 @@ struct lightbar_params_v2_thresholds {
 
 struct lightbar_params_v2_colors {
 	/* Map [AC][battery_level] to color index */
-	uint8_t s0_idx[2][LB_BATTERY_LEVELS];	/* AP is running */
-	uint8_t s3_idx[2][LB_BATTERY_LEVELS];	/* AP is sleeping */
+	uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */
+	uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */
 
 	/* s5: single color pulse on inhibited power-up */
 	uint8_t s5_idx;
 
 	/* Color palette */
-	struct rgb_s color[8];			/* 0-3 are Google colors */
+	struct rgb_s color[8]; /* 0-3 are Google colors */
 } __ec_todo_packed;
 
 /* Lightbar program. */
@@ -2274,7 +2323,7 @@ struct lightbar_program {
 } __ec_todo_unpacked;
 
 struct ec_params_lightbar {
-	uint8_t cmd;		      /* Command (see enum lightbar_command) */
+	uint8_t cmd; /* Command (see enum lightbar_command) */
 	union {
 		/*
 		 * The following commands have no args:
@@ -2339,7 +2388,6 @@ struct ec_response_lightbar {
 		struct lightbar_params_v0 get_params_v0;
 		struct lightbar_params_v1 get_params_v1;
 
-
 		struct lightbar_params_v2_timing get_params_v2_timing;
 		struct lightbar_params_v2_tap get_params_v2_tap;
 		struct lightbar_params_v2_oscillation get_params_v2_osc;
@@ -2404,7 +2452,7 @@ enum lightbar_command {
 	LIGHTBAR_CMD_SET_PARAMS_V2_THRESHOLDS = 31,
 	LIGHTBAR_CMD_GET_PARAMS_V2_COLORS = 32,
 	LIGHTBAR_CMD_SET_PARAMS_V2_COLORS = 33,
-	LIGHTBAR_NUM_CMDS
+	LIGHTBAR_NUM_CMDS,
 };
 
 /*****************************************************************************/
@@ -2431,12 +2479,12 @@ enum ec_led_id {
 	/* LED to indicate sysrq debug mode. */
 	EC_LED_ID_SYSRQ_DEBUG_LED,
 
-	EC_LED_ID_COUNT
+	EC_LED_ID_COUNT,
 };
 
 /* LED control flags */
 #define EC_LED_FLAGS_QUERY BIT(0) /* Query LED capability only */
-#define EC_LED_FLAGS_AUTO  BIT(1) /* Switch LED back to automatic control */
+#define EC_LED_FLAGS_AUTO BIT(1) /* Switch LED back to automatic control */
 
 enum ec_led_colors {
 	EC_LED_COLOR_RED = 0,
@@ -2446,12 +2494,12 @@ enum ec_led_colors {
 	EC_LED_COLOR_WHITE,
 	EC_LED_COLOR_AMBER,
 
-	EC_LED_COLOR_COUNT
+	EC_LED_COLOR_COUNT,
 };
 
 struct ec_params_led_control {
-	uint8_t led_id;     /* Which LED to control */
-	uint8_t flags;      /* Control flags */
+	uint8_t led_id; /* Which LED to control */
+	uint8_t flags; /* Control flags */
 
 	uint8_t brightness[EC_LED_COLOR_COUNT];
 } __ec_align1;
@@ -2479,30 +2527,30 @@ struct ec_response_led_control {
 #define EC_CMD_VBOOT_HASH 0x002A
 
 struct ec_params_vboot_hash {
-	uint8_t cmd;             /* enum ec_vboot_hash_cmd */
-	uint8_t hash_type;       /* enum ec_vboot_hash_type */
-	uint8_t nonce_size;      /* Nonce size; may be 0 */
-	uint8_t reserved0;       /* Reserved; set 0 */
-	uint32_t offset;         /* Offset in flash to hash */
-	uint32_t size;           /* Number of bytes to hash */
-	uint8_t nonce_data[64];  /* Nonce data; ignored if nonce_size=0 */
+	uint8_t cmd; /* enum ec_vboot_hash_cmd */
+	uint8_t hash_type; /* enum ec_vboot_hash_type */
+	uint8_t nonce_size; /* Nonce size; may be 0 */
+	uint8_t reserved0; /* Reserved; set 0 */
+	uint32_t offset; /* Offset in flash to hash */
+	uint32_t size; /* Number of bytes to hash */
+	uint8_t nonce_data[64]; /* Nonce data; ignored if nonce_size=0 */
 } __ec_align4;
 
 struct ec_response_vboot_hash {
-	uint8_t status;          /* enum ec_vboot_hash_status */
-	uint8_t hash_type;       /* enum ec_vboot_hash_type */
-	uint8_t digest_size;     /* Size of hash digest in bytes */
-	uint8_t reserved0;       /* Ignore; will be 0 */
-	uint32_t offset;         /* Offset in flash which was hashed */
-	uint32_t size;           /* Number of bytes hashed */
+	uint8_t status; /* enum ec_vboot_hash_status */
+	uint8_t hash_type; /* enum ec_vboot_hash_type */
+	uint8_t digest_size; /* Size of hash digest in bytes */
+	uint8_t reserved0; /* Ignore; will be 0 */
+	uint32_t offset; /* Offset in flash which was hashed */
+	uint32_t size; /* Number of bytes hashed */
 	uint8_t hash_digest[64]; /* Hash digest data */
 } __ec_align4;
 
 enum ec_vboot_hash_cmd {
-	EC_VBOOT_HASH_GET = 0,       /* Get current hash status */
-	EC_VBOOT_HASH_ABORT = 1,     /* Abort calculating current hash */
-	EC_VBOOT_HASH_START = 2,     /* Start computing a new hash */
-	EC_VBOOT_HASH_RECALC = 3,    /* Synchronously compute a new hash */
+	EC_VBOOT_HASH_GET = 0, /* Get current hash status */
+	EC_VBOOT_HASH_ABORT = 1, /* Abort calculating current hash */
+	EC_VBOOT_HASH_START = 2, /* Start computing a new hash */
+	EC_VBOOT_HASH_RECALC = 3, /* Synchronously compute a new hash */
 };
 
 enum ec_vboot_hash_type {
@@ -2520,9 +2568,9 @@ enum ec_vboot_hash_status {
  * If one of these is specified, the EC will automatically update offset and
  * size to the correct values for the specified image (RO or RW).
  */
-#define EC_VBOOT_HASH_OFFSET_RO		0xfffffffe
-#define EC_VBOOT_HASH_OFFSET_ACTIVE	0xfffffffd
-#define EC_VBOOT_HASH_OFFSET_UPDATE	0xfffffffc
+#define EC_VBOOT_HASH_OFFSET_RO 0xfffffffe
+#define EC_VBOOT_HASH_OFFSET_ACTIVE 0xfffffffd
+#define EC_VBOOT_HASH_OFFSET_UPDATE 0xfffffffc
 
 /*
  * 'RW' is vague if there are multiple RW images; we mean the active one,
@@ -2671,7 +2719,7 @@ enum motionsense_command {
 	MOTIONSENSE_CMD_GET_ACTIVITY = 20,
 
 	/* Number of motionsense sub-commands. */
-	MOTIONSENSE_NUM_CMDS
+	MOTIONSENSE_NUM_CMDS,
 };
 
 /* List of motion sensor types. */
@@ -2753,16 +2801,16 @@ struct ec_response_motion_sensor_data {
 	uint8_t sensor_num;
 	/* Each sensor is up to 3-axis. */
 	union {
-		int16_t                                  data[3];
+		int16_t data[3];
 		/* for sensors using unsigned data */
-		uint16_t                                 udata[3];
+		uint16_t udata[3];
 		struct __ec_todo_packed {
-			uint16_t                         reserved;
-			uint32_t                         timestamp;
+			uint16_t reserved;
+			uint32_t timestamp;
 		};
 		struct __ec_todo_unpacked {
 			struct ec_response_activity_data activity_data;
-			int16_t                          add_info[2];
+			int16_t add_info[2];
 		};
 	};
 } __ec_todo_packed;
@@ -2806,7 +2854,7 @@ enum motionsensor_activity {
 struct ec_motion_sense_activity {
 	uint8_t sensor_num;
 	uint8_t activity; /* one of enum motionsensor_activity */
-	uint8_t enable;   /* 1: enable, 0: disable */
+	uint8_t enable; /* 1: enable, 0: disable */
 	uint8_t reserved;
 	uint16_t parameters[3]; /* activity dependent parameters */
 } __ec_todo_unpacked;
@@ -2974,7 +3022,6 @@ struct ec_params_motion_sense {
 			uint16_t scale[3];
 		} sensor_scale;
 
-
 		/* Used for MOTIONSENSE_CMD_FIFO_INFO */
 		/* (no params) */
 
@@ -3058,7 +3105,7 @@ struct ec_params_motion_sense {
 		 */
 		struct __ec_todo_unpacked {
 			uint8_t sensor_num;
-			uint8_t activity;  /* enum motionsensor_activity */
+			uint8_t activity; /* enum motionsensor_activity */
 		} get_activity;
 	};
 } __ec_todo_packed;
@@ -3159,19 +3206,19 @@ struct ec_response_motion_sense {
 			/* Current value of the parameter queried. */
 			int32_t ret;
 		} ec_rate, sensor_odr, sensor_range, kb_wake_angle,
-		  fifo_int_enable, spoof;
+			fifo_int_enable, spoof;
 
 		/*
 		 * Used for MOTIONSENSE_CMD_SENSOR_OFFSET,
 		 * PERFORM_CALIB.
 		 */
-		struct __ec_todo_unpacked  {
+		struct __ec_todo_unpacked {
 			int16_t temp;
 			int16_t offset[3];
 		} sensor_offset, perform_calib;
 
 		/* Used for MOTIONSENSE_CMD_SENSOR_SCALE */
-		struct __ec_todo_unpacked  {
+		struct __ec_todo_unpacked {
 			int16_t temp;
 			uint16_t scale[3];
 		} sensor_scale;
@@ -3262,20 +3309,20 @@ enum usb_charge_mode {
 	/* Set USB port to CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE. */
 	USB_CHARGE_MODE_DEFAULT,
 
-	USB_CHARGE_MODE_COUNT
+	USB_CHARGE_MODE_COUNT,
 };
 
 enum usb_suspend_charge {
 	/* Enable charging in suspend */
 	USB_ALLOW_SUSPEND_CHARGE,
 	/* Disable charging in suspend */
-	USB_DISALLOW_SUSPEND_CHARGE
+	USB_DISALLOW_SUSPEND_CHARGE,
 };
 
 struct ec_params_usb_charge_set_mode {
 	uint8_t usb_port_id;
-	uint8_t mode:7;              /* enum usb_charge_mode */
-	uint8_t inhibit_charge:1;    /* enum usb_suspend_charge */
+	uint8_t mode : 7; /* enum usb_charge_mode */
+	uint8_t inhibit_charge : 1; /* enum usb_suspend_charge */
 } __ec_align1;
 
 /*****************************************************************************/
@@ -3302,16 +3349,16 @@ struct ec_response_pstore_info {
 #define EC_CMD_PSTORE_READ 0x0041
 
 struct ec_params_pstore_read {
-	uint32_t offset;   /* Byte offset to read */
-	uint32_t size;     /* Size to read in bytes */
+	uint32_t offset; /* Byte offset to read */
+	uint32_t size; /* Size to read in bytes */
 } __ec_align4;
 
 /* Write persistent storage */
 #define EC_CMD_PSTORE_WRITE 0x0042
 
 struct ec_params_pstore_write {
-	uint32_t offset;   /* Byte offset to write */
-	uint32_t size;     /* Size to write in bytes */
+	uint32_t offset; /* Byte offset to write */
+	uint32_t size; /* Size to write in bytes */
 	uint8_t data[EC_PSTORE_SIZE_MAX];
 } __ec_align4;
 
@@ -3454,14 +3501,13 @@ struct ec_response_thermal_get_threshold {
 	uint16_t value;
 } __ec_align2;
 
-
 /* The version 1 structs are visible. */
 enum ec_temp_thresholds {
 	EC_TEMP_THRESH_WARN = 0,
 	EC_TEMP_THRESH_HIGH,
 	EC_TEMP_THRESH_HALT,
 
-	EC_TEMP_THRESH_COUNT
+	EC_TEMP_THRESH_COUNT,
 };
 
 /*
@@ -3489,8 +3535,8 @@ enum ec_temp_thresholds {
 struct ec_thermal_config {
 	uint32_t temp_host[EC_TEMP_THRESH_COUNT]; /* levels of hotness */
 	uint32_t temp_host_release[EC_TEMP_THRESH_COUNT]; /* release levels */
-	uint32_t temp_fan_off;		/* no active cooling needed */
-	uint32_t temp_fan_max;		/* max active cooling needed */
+	uint32_t temp_fan_off; /* no active cooling needed */
+	uint32_t temp_fan_max; /* max active cooling needed */
 } __ec_align4;
 
 /* Version 1 - get config for one sensor. */
@@ -3570,7 +3616,6 @@ struct ec_params_tmp006_set_calibration_v1 {
 	float val[0];
 } __ec_align4;
 
-
 /* Read raw TMP006 data */
 #define EC_CMD_TMP006_GET_RAW 0x0055
 
@@ -3579,8 +3624,8 @@ struct ec_params_tmp006_get_raw {
 } __ec_align1;
 
 struct ec_response_tmp006_get_raw {
-	int32_t t;  /* In 1/100 K */
-	int32_t v;  /* In nV */
+	int32_t t; /* In 1/100 K */
+	int32_t v; /* In nV */
 } __ec_align4;
 
 /*****************************************************************************/
@@ -3680,17 +3725,17 @@ enum keyboard_id {
 
 /* flags */
 enum mkbp_config_flags {
-	EC_MKBP_FLAGS_ENABLE = 1,	/* Enable keyboard scanning */
+	EC_MKBP_FLAGS_ENABLE = 1, /* Enable keyboard scanning */
 };
 
 enum mkbp_config_valid {
-	EC_MKBP_VALID_SCAN_PERIOD		= BIT(0),
-	EC_MKBP_VALID_POLL_TIMEOUT		= BIT(1),
-	EC_MKBP_VALID_MIN_POST_SCAN_DELAY	= BIT(3),
-	EC_MKBP_VALID_OUTPUT_SETTLE		= BIT(4),
-	EC_MKBP_VALID_DEBOUNCE_DOWN		= BIT(5),
-	EC_MKBP_VALID_DEBOUNCE_UP		= BIT(6),
-	EC_MKBP_VALID_FIFO_MAX_DEPTH		= BIT(7),
+	EC_MKBP_VALID_SCAN_PERIOD = BIT(0),
+	EC_MKBP_VALID_POLL_TIMEOUT = BIT(1),
+	EC_MKBP_VALID_MIN_POST_SCAN_DELAY = BIT(3),
+	EC_MKBP_VALID_OUTPUT_SETTLE = BIT(4),
+	EC_MKBP_VALID_DEBOUNCE_DOWN = BIT(5),
+	EC_MKBP_VALID_DEBOUNCE_UP = BIT(6),
+	EC_MKBP_VALID_FIFO_MAX_DEPTH = BIT(7),
 };
 
 /*
@@ -3700,10 +3745,10 @@ enum mkbp_config_valid {
  * ec_{params/response}_mkbp_get_config.
  */
 struct ec_mkbp_config {
-	uint32_t valid_mask;		/* valid fields */
-	uint8_t flags;		/* some flags (enum mkbp_config_flags) */
-	uint8_t valid_flags;		/* which flags are valid */
-	uint16_t scan_period_us;	/* period between start of scans */
+	uint32_t valid_mask; /* valid fields */
+	uint8_t flags; /* some flags (enum mkbp_config_flags) */
+	uint8_t valid_flags; /* which flags are valid */
+	uint16_t scan_period_us; /* period between start of scans */
 	/* revert to interrupt mode after no activity for this long */
 	uint32_t poll_timeout_us;
 	/*
@@ -3714,8 +3759,8 @@ struct ec_mkbp_config {
 	uint16_t min_post_scan_delay_us;
 	/* delay between setting up output and waiting for it to settle */
 	uint16_t output_settle_us;
-	uint16_t debounce_down_us;	/* time for debounce on key down */
-	uint16_t debounce_up_us;	/* time for debounce on key up */
+	uint16_t debounce_down_us; /* time for debounce on key down */
+	uint16_t debounce_up_us; /* time for debounce on key up */
 	/* maximum depth to allow for fifo (0 = no keyscan output) */
 	uint8_t fifo_max_depth;
 } __ec_align_size1;
@@ -3732,11 +3777,11 @@ struct ec_response_mkbp_get_config {
 #define EC_CMD_KEYSCAN_SEQ_CTRL 0x0066
 
 enum ec_keyscan_seq_cmd {
-	EC_KEYSCAN_SEQ_STATUS = 0,	/* Get status information */
-	EC_KEYSCAN_SEQ_CLEAR = 1,	/* Clear sequence */
-	EC_KEYSCAN_SEQ_ADD = 2,		/* Add item to sequence */
-	EC_KEYSCAN_SEQ_START = 3,	/* Start running sequence */
-	EC_KEYSCAN_SEQ_COLLECT = 4,	/* Collect sequence summary data */
+	EC_KEYSCAN_SEQ_STATUS = 0, /* Get status information */
+	EC_KEYSCAN_SEQ_CLEAR = 1, /* Clear sequence */
+	EC_KEYSCAN_SEQ_ADD = 2, /* Add item to sequence */
+	EC_KEYSCAN_SEQ_START = 3, /* Start running sequence */
+	EC_KEYSCAN_SEQ_COLLECT = 4, /* Collect sequence summary data */
 };
 
 enum ec_collect_flags {
@@ -3744,19 +3789,19 @@ enum ec_collect_flags {
 	 * Indicates this scan was processed by the EC. Due to timing, some
 	 * scans may be skipped.
 	 */
-	EC_KEYSCAN_SEQ_FLAG_DONE	= BIT(0),
+	EC_KEYSCAN_SEQ_FLAG_DONE = BIT(0),
 };
 
 struct ec_collect_item {
-	uint8_t flags;		/* some flags (enum ec_collect_flags) */
+	uint8_t flags; /* some flags (enum ec_collect_flags) */
 } __ec_align1;
 
 struct ec_params_keyscan_seq_ctrl {
-	uint8_t cmd;	/* Command to send (enum ec_keyscan_seq_cmd) */
+	uint8_t cmd; /* Command to send (enum ec_keyscan_seq_cmd) */
 	union {
 		struct __ec_align1 {
-			uint8_t active;		/* still active */
-			uint8_t num_items;	/* number of items */
+			uint8_t active; /* still active */
+			uint8_t num_items; /* number of items */
 			/* Current item being presented */
 			uint8_t cur_item;
 		} status;
@@ -3766,11 +3811,11 @@ struct ec_params_keyscan_seq_ctrl {
 			 * start of the sequence.
 			 */
 			uint32_t time_us;
-			uint8_t scan[0];	/* keyscan data */
+			uint8_t scan[0]; /* keyscan data */
 		} add;
 		struct __ec_align1 {
-			uint8_t start_item;	/* First item to return */
-			uint8_t num_items;	/* Number of items to return */
+			uint8_t start_item; /* First item to return */
+			uint8_t num_items; /* Number of items to return */
 		} collect;
 	};
 } __ec_todo_packed;
@@ -3778,7 +3823,7 @@ struct ec_params_keyscan_seq_ctrl {
 struct ec_result_keyscan_seq_ctrl {
 	union {
 		struct __ec_todo_unpacked {
-			uint8_t num_items;	/* Number of items */
+			uint8_t num_items; /* Number of items */
 			/* Data for each item */
 			struct ec_collect_item item[0];
 		} collect;
@@ -3854,6 +3899,25 @@ enum ec_mkbp_event {
 };
 BUILD_ASSERT(EC_MKBP_EVENT_COUNT <= EC_MKBP_EVENT_TYPE_MASK);
 
+/* clang-format off */
+#define EC_MKBP_EVENT_TEXT                                                     \
+	{                                                                      \
+		[EC_MKBP_EVENT_KEY_MATRIX] = "KEY_MATRIX",                     \
+		[EC_MKBP_EVENT_HOST_EVENT] = "HOST_EVENT",                     \
+		[EC_MKBP_EVENT_SENSOR_FIFO] = "SENSOR_FIFO",                   \
+		[EC_MKBP_EVENT_BUTTON] = "BUTTON",                             \
+		[EC_MKBP_EVENT_SWITCH] = "SWITCH",                             \
+		[EC_MKBP_EVENT_FINGERPRINT] = "FINGERPRINT",                   \
+		[EC_MKBP_EVENT_SYSRQ] = "SYSRQ",                               \
+		[EC_MKBP_EVENT_HOST_EVENT64] = "HOST_EVENT64",                 \
+		[EC_MKBP_EVENT_CEC_EVENT] = "CEC_EVENT",                       \
+		[EC_MKBP_EVENT_CEC_MESSAGE] = "CEC_MESSAGE",                   \
+		[EC_MKBP_EVENT_DP_ALT_MODE_ENTERED] = "DP_ALT_MODE_ENTERED",   \
+		[EC_MKBP_EVENT_ONLINE_CALIBRATION] = "ONLINE_CALIBRATION",     \
+		[EC_MKBP_EVENT_PCHG] = "PCHG",                                 \
+	}
+/* clang-format on */
+
 union __ec_align_offset1 ec_response_get_next_data {
 	uint8_t key_matrix[13];
 
@@ -3921,58 +3985,57 @@ struct ec_response_get_next_event_v1 {
 
 /* Bit indices for buttons and switches.*/
 /* Buttons */
-#define EC_MKBP_POWER_BUTTON	0
-#define EC_MKBP_VOL_UP		1
-#define EC_MKBP_VOL_DOWN	2
-#define EC_MKBP_RECOVERY	3
+#define EC_MKBP_POWER_BUTTON 0
+#define EC_MKBP_VOL_UP 1
+#define EC_MKBP_VOL_DOWN 2
+#define EC_MKBP_RECOVERY 3
 
 /* Switches */
-#define EC_MKBP_LID_OPEN	0
-#define EC_MKBP_TABLET_MODE	1
-#define EC_MKBP_BASE_ATTACHED	2
-#define EC_MKBP_FRONT_PROXIMITY	3
+#define EC_MKBP_LID_OPEN 0
+#define EC_MKBP_TABLET_MODE 1
+#define EC_MKBP_BASE_ATTACHED 2
+#define EC_MKBP_FRONT_PROXIMITY 3
 
 /* Run keyboard factory test scanning */
 #define EC_CMD_KEYBOARD_FACTORY_TEST 0x0068
 
 struct ec_response_keyboard_factory_test {
-	uint16_t shorted;	/* Keyboard pins are shorted */
+	uint16_t shorted; /* Keyboard pins are shorted */
 } __ec_align2;
 
 /* Fingerprint events in 'fp_events' for EC_MKBP_EVENT_FINGERPRINT */
-#define EC_MKBP_FP_RAW_EVENT(fp_events) ((fp_events) & 0x00FFFFFF)
-#define EC_MKBP_FP_ERRCODE(fp_events)   ((fp_events) & 0x0000000F)
+#define EC_MKBP_FP_RAW_EVENT(fp_events) ((fp_events)&0x00FFFFFF)
+#define EC_MKBP_FP_ERRCODE(fp_events) ((fp_events)&0x0000000F)
 #define EC_MKBP_FP_ENROLL_PROGRESS_OFFSET 4
-#define EC_MKBP_FP_ENROLL_PROGRESS(fpe) (((fpe) & 0x00000FF0) \
-					 >> EC_MKBP_FP_ENROLL_PROGRESS_OFFSET)
+#define EC_MKBP_FP_ENROLL_PROGRESS(fpe) \
+	(((fpe)&0x00000FF0) >> EC_MKBP_FP_ENROLL_PROGRESS_OFFSET)
 #define EC_MKBP_FP_MATCH_IDX_OFFSET 12
 #define EC_MKBP_FP_MATCH_IDX_MASK 0x0000F000
-#define EC_MKBP_FP_MATCH_IDX(fpe) (((fpe) & EC_MKBP_FP_MATCH_IDX_MASK) \
-					 >> EC_MKBP_FP_MATCH_IDX_OFFSET)
-#define EC_MKBP_FP_ENROLL               BIT(27)
-#define EC_MKBP_FP_MATCH                BIT(28)
-#define EC_MKBP_FP_FINGER_DOWN          BIT(29)
-#define EC_MKBP_FP_FINGER_UP            BIT(30)
-#define EC_MKBP_FP_IMAGE_READY          BIT(31)
+#define EC_MKBP_FP_MATCH_IDX(fpe) \
+	(((fpe)&EC_MKBP_FP_MATCH_IDX_MASK) >> EC_MKBP_FP_MATCH_IDX_OFFSET)
+#define EC_MKBP_FP_ENROLL BIT(27)
+#define EC_MKBP_FP_MATCH BIT(28)
+#define EC_MKBP_FP_FINGER_DOWN BIT(29)
+#define EC_MKBP_FP_FINGER_UP BIT(30)
+#define EC_MKBP_FP_IMAGE_READY BIT(31)
 /* code given by EC_MKBP_FP_ERRCODE() when EC_MKBP_FP_ENROLL is set */
-#define EC_MKBP_FP_ERR_ENROLL_OK               0
-#define EC_MKBP_FP_ERR_ENROLL_LOW_QUALITY      1
-#define EC_MKBP_FP_ERR_ENROLL_IMMOBILE         2
-#define EC_MKBP_FP_ERR_ENROLL_LOW_COVERAGE     3
-#define EC_MKBP_FP_ERR_ENROLL_INTERNAL         5
+#define EC_MKBP_FP_ERR_ENROLL_OK 0
+#define EC_MKBP_FP_ERR_ENROLL_LOW_QUALITY 1
+#define EC_MKBP_FP_ERR_ENROLL_IMMOBILE 2
+#define EC_MKBP_FP_ERR_ENROLL_LOW_COVERAGE 3
+#define EC_MKBP_FP_ERR_ENROLL_INTERNAL 5
 /* Can be used to detect if image was usable for enrollment or not. */
-#define EC_MKBP_FP_ERR_ENROLL_PROBLEM_MASK     1
+#define EC_MKBP_FP_ERR_ENROLL_PROBLEM_MASK 1
 /* code given by EC_MKBP_FP_ERRCODE() when EC_MKBP_FP_MATCH is set */
-#define EC_MKBP_FP_ERR_MATCH_NO                0
-#define EC_MKBP_FP_ERR_MATCH_NO_INTERNAL       6
-#define EC_MKBP_FP_ERR_MATCH_NO_TEMPLATES      7
-#define EC_MKBP_FP_ERR_MATCH_NO_LOW_QUALITY    2
-#define EC_MKBP_FP_ERR_MATCH_NO_LOW_COVERAGE   4
-#define EC_MKBP_FP_ERR_MATCH_YES               1
-#define EC_MKBP_FP_ERR_MATCH_YES_UPDATED       3
+#define EC_MKBP_FP_ERR_MATCH_NO 0
+#define EC_MKBP_FP_ERR_MATCH_NO_INTERNAL 6
+#define EC_MKBP_FP_ERR_MATCH_NO_TEMPLATES 7
+#define EC_MKBP_FP_ERR_MATCH_NO_LOW_QUALITY 2
+#define EC_MKBP_FP_ERR_MATCH_NO_LOW_COVERAGE 4
+#define EC_MKBP_FP_ERR_MATCH_YES 1
+#define EC_MKBP_FP_ERR_MATCH_YES_UPDATED 3
 #define EC_MKBP_FP_ERR_MATCH_YES_UPDATE_FAILED 5
 
-
 #define EC_CMD_MKBP_WAKE_MASK 0x0069
 enum ec_mkbp_event_mask_action {
 	/* Retrieve the value of a wake mask. */
@@ -4050,7 +4113,6 @@ struct ec_response_temp_sensor_get_info {
 /*****************************************************************************/
 /* Host event commands */
 
-
 /* Obsolete. New implementation should use EC_CMD_HOST_EVENT instead */
 /*
  * Host event mask params and response structures, shared by all of the host
@@ -4065,17 +4127,17 @@ struct ec_response_host_event_mask {
 } __ec_align4;
 
 /* These all use ec_response_host_event_mask */
-#define EC_CMD_HOST_EVENT_GET_B         0x0087
-#define EC_CMD_HOST_EVENT_GET_SMI_MASK  0x0088
-#define EC_CMD_HOST_EVENT_GET_SCI_MASK  0x0089
+#define EC_CMD_HOST_EVENT_GET_B 0x0087
+#define EC_CMD_HOST_EVENT_GET_SMI_MASK 0x0088
+#define EC_CMD_HOST_EVENT_GET_SCI_MASK 0x0089
 #define EC_CMD_HOST_EVENT_GET_WAKE_MASK 0x008D
 
 /* These all use ec_params_host_event_mask */
-#define EC_CMD_HOST_EVENT_SET_SMI_MASK  0x008A
-#define EC_CMD_HOST_EVENT_SET_SCI_MASK  0x008B
-#define EC_CMD_HOST_EVENT_CLEAR         0x008C
+#define EC_CMD_HOST_EVENT_SET_SMI_MASK 0x008A
+#define EC_CMD_HOST_EVENT_SET_SCI_MASK 0x008B
+#define EC_CMD_HOST_EVENT_CLEAR 0x008C
 #define EC_CMD_HOST_EVENT_SET_WAKE_MASK 0x008E
-#define EC_CMD_HOST_EVENT_CLEAR_B       0x008F
+#define EC_CMD_HOST_EVENT_CLEAR_B 0x008F
 
 /*
  * Unified host event programming interface - Should be used by newer versions
@@ -4087,7 +4149,6 @@ struct ec_response_host_event_mask {
  */
 
 struct ec_params_host_event {
-
 	/* Action requested by host - one of enum ec_host_event_action. */
 	uint8_t action;
 
@@ -4110,7 +4171,6 @@ struct ec_params_host_event {
  */
 
 struct ec_response_host_event {
-
 	/* Mask value in case of get operation */
 	uint64_t value;
 } __ec_align4;
@@ -4159,7 +4219,7 @@ enum ec_host_event_mask_type {
 	EC_HOST_EVENT_LAZY_WAKE_MASK_S5,
 };
 
-#define EC_CMD_HOST_EVENT       0x00A4
+#define EC_CMD_HOST_EVENT 0x00A4
 
 /*****************************************************************************/
 /* Switch commands */
@@ -4315,10 +4375,11 @@ enum ec_charge_control_mode {
 	CHARGE_CONTROL_COUNT,
 };
 
-#define EC_CHARGE_MODE_TEXT { \
-	[CHARGE_CONTROL_NORMAL] = "NORMAL", \
-	[CHARGE_CONTROL_IDLE] = "IDLE", \
-	[CHARGE_CONTROL_DISCHARGE] = "DISCHARGE", \
+#define EC_CHARGE_MODE_TEXT                               \
+	{                                                 \
+		[CHARGE_CONTROL_NORMAL] = "NORMAL",       \
+		[CHARGE_CONTROL_IDLE] = "IDLE",           \
+		[CHARGE_CONTROL_DISCHARGE] = "DISCHARGE", \
 	}
 
 enum ec_charge_control_cmd {
@@ -4327,10 +4388,10 @@ enum ec_charge_control_cmd {
 };
 
 struct ec_params_charge_control {
-	uint32_t mode;  /* enum charge_control_mode */
+	uint32_t mode; /* enum charge_control_mode */
 
 	/* Below are the fields added in V2. */
-	uint8_t cmd;    /* enum ec_charge_control_cmd. */
+	uint8_t cmd; /* enum ec_charge_control_cmd. */
 	uint8_t reserved;
 	/*
 	 * Lower and upper thresholds for battery sustainer. This struct isn't
@@ -4341,15 +4402,15 @@ struct ec_params_charge_control {
 	 * lower=-1, upper=-1.
 	 */
 	struct {
-		int8_t lower;	/* Display SoC in percentage. */
-		int8_t upper;	/* Display SoC in percentage. */
+		int8_t lower; /* Display SoC in percentage. */
+		int8_t upper; /* Display SoC in percentage. */
 	} sustain_soc;
 } __ec_align4;
 
 /* Added in v2 */
 struct ec_response_charge_control {
-	uint32_t mode;  /* enum charge_control_mode */
-	struct {        /* Battery sustainer thresholds */
+	uint32_t mode; /* enum charge_control_mode */
+	struct { /* Battery sustainer thresholds */
 		int8_t lower;
 		int8_t upper;
 	} sustain_soc;
@@ -4377,7 +4438,7 @@ struct ec_response_charge_control {
 
 enum ec_console_read_subcmd {
 	CONSOLE_READ_NEXT = 0,
-	CONSOLE_READ_RECENT
+	CONSOLE_READ_RECENT,
 };
 
 struct ec_params_console_read_v1 {
@@ -4395,7 +4456,7 @@ struct ec_params_console_read_v1 {
  */
 #define EC_CMD_BATTERY_CUT_OFF 0x0099
 
-#define EC_BATTERY_CUTOFF_FLAG_AT_SHUTDOWN	BIT(0)
+#define EC_BATTERY_CUTOFF_FLAG_AT_SHUTDOWN BIT(0)
 
 struct ec_params_battery_cutoff {
 	uint8_t flags;
@@ -4417,8 +4478,8 @@ struct ec_params_usb_mux {
 /* LDOs / FETs control. */
 
 enum ec_ldo_state {
-	EC_LDO_STATE_OFF = 0,	/* the LDO / FET is shut down */
-	EC_LDO_STATE_ON = 1,	/* the LDO / FET is ON / providing power */
+	EC_LDO_STATE_OFF = 0, /* the LDO / FET is shut down */
+	EC_LDO_STATE_ON = 1, /* the LDO / FET is ON / providing power */
 };
 
 /*
@@ -4519,33 +4580,33 @@ struct ec_response_power_info_v1 {
 #define EC_CMD_I2C_PASSTHRU 0x009E
 
 /* Read data; if not present, message is a write */
-#define EC_I2C_FLAG_READ	BIT(15)
+#define EC_I2C_FLAG_READ BIT(15)
 
 /* Mask for address */
-#define EC_I2C_ADDR_MASK	0x3ff
+#define EC_I2C_ADDR_MASK 0x3ff
 
-#define EC_I2C_STATUS_NAK	BIT(0) /* Transfer was not acknowledged */
-#define EC_I2C_STATUS_TIMEOUT	BIT(1) /* Timeout during transfer */
+#define EC_I2C_STATUS_NAK BIT(0) /* Transfer was not acknowledged */
+#define EC_I2C_STATUS_TIMEOUT BIT(1) /* Timeout during transfer */
 
 /* Any error */
-#define EC_I2C_STATUS_ERROR	(EC_I2C_STATUS_NAK | EC_I2C_STATUS_TIMEOUT)
+#define EC_I2C_STATUS_ERROR (EC_I2C_STATUS_NAK | EC_I2C_STATUS_TIMEOUT)
 
 struct ec_params_i2c_passthru_msg {
-	uint16_t addr_flags;	/* I2C peripheral address and flags */
-	uint16_t len;		/* Number of bytes to read or write */
+	uint16_t addr_flags; /* I2C peripheral address and flags */
+	uint16_t len; /* Number of bytes to read or write */
 } __ec_align2;
 
 struct ec_params_i2c_passthru {
-	uint8_t port;		/* I2C port number */
-	uint8_t num_msgs;	/* Number of messages */
+	uint8_t port; /* I2C port number */
+	uint8_t num_msgs; /* Number of messages */
 	struct ec_params_i2c_passthru_msg msg[];
 	/* Data to write for all messages is concatenated here */
 } __ec_align2;
 
 struct ec_response_i2c_passthru {
-	uint8_t i2c_status;	/* Status flags (EC_I2C_STATUS_...) */
-	uint8_t num_msgs;	/* Number of messages processed */
-	uint8_t data[];		/* Data read by messages concatenated here */
+	uint8_t i2c_status; /* Status flags (EC_I2C_STATUS_...) */
+	uint8_t num_msgs; /* Number of messages processed */
+	uint8_t data[]; /* Data read by messages concatenated here */
 } __ec_align1;
 
 /*****************************************************************************/
@@ -4555,16 +4616,16 @@ struct ec_response_i2c_passthru {
 
 /* Reasons to start hang detection timer */
 /* Power button pressed */
-#define EC_HANG_START_ON_POWER_PRESS  BIT(0)
+#define EC_HANG_START_ON_POWER_PRESS BIT(0)
 
 /* Lid closed */
-#define EC_HANG_START_ON_LID_CLOSE    BIT(1)
+#define EC_HANG_START_ON_LID_CLOSE BIT(1)
 
- /* Lid opened */
-#define EC_HANG_START_ON_LID_OPEN     BIT(2)
+/* Lid opened */
+#define EC_HANG_START_ON_LID_OPEN BIT(2)
 
 /* Start of AP S3->S0 transition (booting or resuming from suspend) */
-#define EC_HANG_START_ON_RESUME       BIT(3)
+#define EC_HANG_START_ON_RESUME BIT(3)
 
 /* Reasons to cancel hang detection */
 
@@ -4572,10 +4633,10 @@ struct ec_response_i2c_passthru {
 #define EC_HANG_STOP_ON_POWER_RELEASE BIT(8)
 
 /* Any host command from AP received */
-#define EC_HANG_STOP_ON_HOST_COMMAND  BIT(9)
+#define EC_HANG_STOP_ON_HOST_COMMAND BIT(9)
 
 /* Stop on end of AP S0->S3 transition (suspending or shutting down) */
-#define EC_HANG_STOP_ON_SUSPEND       BIT(10)
+#define EC_HANG_STOP_ON_SUSPEND BIT(10)
 
 /*
  * If this flag is set, all the other fields are ignored, and the hang detect
@@ -4583,14 +4644,14 @@ struct ec_response_i2c_passthru {
  * without reconfiguring any of the other hang detect settings.  Note that
  * you must previously have configured the timeouts.
  */
-#define EC_HANG_START_NOW             BIT(30)
+#define EC_HANG_START_NOW BIT(30)
 
 /*
  * If this flag is set, all the other fields are ignored (including
  * EC_HANG_START_NOW).  This provides the AP a way to stop the hang timer
  * without reconfiguring any of the other hang detect settings.
  */
-#define EC_HANG_STOP_NOW              BIT(31)
+#define EC_HANG_STOP_NOW BIT(31)
 
 struct ec_params_hang_detect {
 	/* Flags; see EC_HANG_* */
@@ -4617,7 +4678,7 @@ enum charge_state_command {
 	CHARGE_STATE_CMD_GET_STATE,
 	CHARGE_STATE_CMD_GET_PARAM,
 	CHARGE_STATE_CMD_SET_PARAM,
-	CHARGE_STATE_NUM_CMDS
+	CHARGE_STATE_NUM_CMDS,
 };
 
 /*
@@ -4625,16 +4686,27 @@ enum charge_state_command {
  * params, which are handled by the particular implementations.
  */
 enum charge_state_params {
-	CS_PARAM_CHG_VOLTAGE,	      /* charger voltage limit */
-	CS_PARAM_CHG_CURRENT,	      /* charger current limit */
-	CS_PARAM_CHG_INPUT_CURRENT,   /* charger input current limit */
-	CS_PARAM_CHG_STATUS,	      /* charger-specific status */
-	CS_PARAM_CHG_OPTION,	      /* charger-specific options */
-	CS_PARAM_LIMIT_POWER,	      /*
-				       * Check if power is limited due to
-				       * low battery and / or a weak external
-				       * charger. READ ONLY.
-				       */
+	/* charger voltage limit */
+	CS_PARAM_CHG_VOLTAGE,
+
+	/* charger current limit */
+	CS_PARAM_CHG_CURRENT,
+
+	/* charger input current limit */
+	CS_PARAM_CHG_INPUT_CURRENT,
+
+	/* charger-specific status */
+	CS_PARAM_CHG_STATUS,
+
+	/* charger-specific options */
+	CS_PARAM_CHG_OPTION,
+
+	/*
+	 * Check if power is limited due to low battery and / or a
+	 * weak external charger. READ ONLY.
+	 */
+	CS_PARAM_LIMIT_POWER,
+
 	/* How many so far? */
 	CS_NUM_BASE_PARAMS,
 
@@ -4657,20 +4729,20 @@ enum charge_state_params {
 };
 
 struct ec_params_charge_state {
-	uint8_t cmd;				/* enum charge_state_command */
+	uint8_t cmd; /* enum charge_state_command */
 	union {
 		/* get_state has no args */
 
 		struct __ec_todo_unpacked {
-			uint32_t param;		/* enum charge_state_param */
+			uint32_t param; /* enum charge_state_param */
 		} get_param;
 
 		struct __ec_todo_unpacked {
-			uint32_t param;		/* param to set */
-			uint32_t value;		/* value to set */
+			uint32_t param; /* param to set */
+			uint32_t value; /* value to set */
 		} set_param;
 	};
-	uint8_t chgnum;				/* Version 1 supports chgnum */
+	uint8_t chgnum; /* Version 1 supports chgnum */
 } __ec_todo_packed;
 
 struct ec_response_charge_state {
@@ -4691,7 +4763,6 @@ struct ec_response_charge_state {
 	};
 } __ec_align4;
 
-
 /*
  * Set maximum battery charging current.
  */
@@ -4795,10 +4866,10 @@ struct ec_response_hibernation_delay {
 #define EC_CMD_HOST_SLEEP_EVENT 0x00A9
 
 enum host_sleep_event {
-	HOST_SLEEP_EVENT_S3_SUSPEND   = 1,
-	HOST_SLEEP_EVENT_S3_RESUME    = 2,
+	HOST_SLEEP_EVENT_S3_SUSPEND = 1,
+	HOST_SLEEP_EVENT_S3_RESUME = 2,
 	HOST_SLEEP_EVENT_S0IX_SUSPEND = 3,
-	HOST_SLEEP_EVENT_S0IX_RESUME  = 4,
+	HOST_SLEEP_EVENT_S0IX_RESUME = 4,
 	/* S3 suspend with additional enabled wake sources */
 	HOST_SLEEP_EVENT_S3_WAKEABLE_SUSPEND = 5,
 };
@@ -4899,13 +4970,13 @@ struct ec_response_device_event {
 /* Smart battery pass-through */
 
 /* Get / Set 16-bit smart battery registers */
-#define EC_CMD_SB_READ_WORD   0x00B0
-#define EC_CMD_SB_WRITE_WORD  0x00B1
+#define EC_CMD_SB_READ_WORD 0x00B0
+#define EC_CMD_SB_WRITE_WORD 0x00B1
 
 /* Get / Set string smart battery parameters
  * formatted as SMBUS "block".
  */
-#define EC_CMD_SB_READ_BLOCK  0x00B2
+#define EC_CMD_SB_READ_BLOCK 0x00B2
 #define EC_CMD_SB_WRITE_BLOCK 0x00B3
 
 struct ec_params_sb_rd {
@@ -4963,14 +5034,14 @@ struct ec_response_battery_vendor_param {
 #define EC_CMD_SB_FW_UPDATE 0x00B5
 
 enum ec_sb_fw_update_subcmd {
-	EC_SB_FW_UPDATE_PREPARE  = 0x0,
-	EC_SB_FW_UPDATE_INFO     = 0x1, /*query sb info */
-	EC_SB_FW_UPDATE_BEGIN    = 0x2, /*check if protected */
-	EC_SB_FW_UPDATE_WRITE    = 0x3, /*check if protected */
-	EC_SB_FW_UPDATE_END      = 0x4,
-	EC_SB_FW_UPDATE_STATUS   = 0x5,
-	EC_SB_FW_UPDATE_PROTECT  = 0x6,
-	EC_SB_FW_UPDATE_MAX      = 0x7,
+	EC_SB_FW_UPDATE_PREPARE = 0x0,
+	EC_SB_FW_UPDATE_INFO = 0x1, /*query sb info */
+	EC_SB_FW_UPDATE_BEGIN = 0x2, /*check if protected */
+	EC_SB_FW_UPDATE_WRITE = 0x3, /*check if protected */
+	EC_SB_FW_UPDATE_END = 0x4,
+	EC_SB_FW_UPDATE_STATUS = 0x5,
+	EC_SB_FW_UPDATE_PROTECT = 0x6,
+	EC_SB_FW_UPDATE_MAX = 0x7,
 };
 
 #define SB_FW_UPDATE_CMD_WRITE_BLOCK_SIZE 32
@@ -4978,8 +5049,8 @@ enum ec_sb_fw_update_subcmd {
 #define SB_FW_UPDATE_CMD_INFO_SIZE 8
 
 struct ec_sb_fw_update_header {
-	uint16_t subcmd;  /* enum ec_sb_fw_update_subcmd */
-	uint16_t fw_id;   /* firmware id */
+	uint16_t subcmd; /* enum ec_sb_fw_update_subcmd */
+	uint16_t fw_id; /* firmware id */
 } __ec_align4;
 
 struct ec_params_sb_fw_update {
@@ -4995,7 +5066,7 @@ struct ec_params_sb_fw_update {
 
 		/* EC_SB_FW_UPDATE_WRITE    = 0x3 */
 		struct __ec_align4 {
-			uint8_t  data[SB_FW_UPDATE_CMD_WRITE_BLOCK_SIZE];
+			uint8_t data[SB_FW_UPDATE_CMD_WRITE_BLOCK_SIZE];
 		} write;
 	};
 } __ec_align4;
@@ -5028,9 +5099,9 @@ struct ec_params_entering_mode {
 	int vboot_mode;
 } __ec_align4;
 
-#define VBOOT_MODE_NORMAL    0
+#define VBOOT_MODE_NORMAL 0
 #define VBOOT_MODE_DEVELOPER 1
-#define VBOOT_MODE_RECOVERY  2
+#define VBOOT_MODE_RECOVERY 2
 
 /*****************************************************************************/
 /*
@@ -5047,14 +5118,13 @@ enum ec_i2c_passthru_protect_subcmd {
 
 struct ec_params_i2c_passthru_protect {
 	uint8_t subcmd;
-	uint8_t port;		/* I2C port number */
+	uint8_t port; /* I2C port number */
 } __ec_align1;
 
 struct ec_response_i2c_passthru_protect {
-	uint8_t status;		/* Status flags (0: unlocked, 1: locked) */
+	uint8_t status; /* Status flags (0: unlocked, 1: locked) */
 } __ec_align1;
 
-
 /*****************************************************************************/
 /*
  * HDMI CEC commands
@@ -5124,9 +5194,9 @@ enum cec_command {
 /* Events from CEC to AP */
 enum mkbp_cec_event {
 	/* Outgoing message was acknowledged by a follower */
-	EC_MKBP_CEC_SEND_OK			= BIT(0),
+	EC_MKBP_CEC_SEND_OK = BIT(0),
 	/* Outgoing message was not acknowledged */
-	EC_MKBP_CEC_SEND_FAILED			= BIT(1),
+	EC_MKBP_CEC_SEND_FAILED = BIT(1),
 };
 
 /*****************************************************************************/
@@ -5175,10 +5245,8 @@ struct __ec_align4 ec_param_ec_codec {
 	uint8_t reserved[3];
 
 	union {
-		struct ec_param_ec_codec_get_shm_addr
-				get_shm_addr_param;
-		struct ec_param_ec_codec_set_shm_addr
-				set_shm_addr_param;
+		struct ec_param_ec_codec_get_shm_addr get_shm_addr_param;
+		struct ec_param_ec_codec_set_shm_addr set_shm_addr_param;
 	};
 };
 
@@ -5233,10 +5301,8 @@ struct __ec_align4 ec_param_ec_codec_dmic {
 	uint8_t reserved[3];
 
 	union {
-		struct ec_param_ec_codec_dmic_set_gain_idx
-				set_gain_idx_param;
-		struct ec_param_ec_codec_dmic_get_gain_idx
-				get_gain_idx_param;
+		struct ec_param_ec_codec_dmic_set_gain_idx set_gain_idx_param;
+		struct ec_param_ec_codec_dmic_get_gain_idx get_gain_idx_param;
 	};
 };
 
@@ -5303,11 +5369,9 @@ struct __ec_align4 ec_param_ec_codec_i2s_rx {
 
 	union {
 		struct ec_param_ec_codec_i2s_rx_set_sample_depth
-				set_sample_depth_param;
-		struct ec_param_ec_codec_i2s_rx_set_daifmt
-				set_daifmt_param;
-		struct ec_param_ec_codec_i2s_rx_set_bclk
-				set_bclk_param;
+			set_sample_depth_param;
+		struct ec_param_ec_codec_i2s_rx_set_daifmt set_daifmt_param;
+		struct ec_param_ec_codec_i2s_rx_set_bclk set_bclk_param;
 	};
 };
 
@@ -5352,10 +5416,8 @@ struct __ec_align4 ec_param_ec_codec_wov {
 	uint8_t reserved[3];
 
 	union {
-		struct ec_param_ec_codec_wov_set_lang
-				set_lang_param;
-		struct ec_param_ec_codec_wov_set_lang_shm
-				set_lang_shm_param;
+		struct ec_param_ec_codec_wov_set_lang set_lang_param;
+		struct ec_param_ec_codec_wov_set_lang_shm set_lang_shm_param;
 	};
 };
 
@@ -5386,8 +5448,8 @@ enum ec_pse_subcmd {
 };
 
 struct __ec_align1 ec_params_pse {
-	uint8_t cmd;	/* enum ec_pse_subcmd */
-	uint8_t port;	/* PSE port */
+	uint8_t cmd; /* enum ec_pse_subcmd */
+	uint8_t port; /* PSE port */
 };
 
 enum ec_pse_status {
@@ -5397,7 +5459,7 @@ enum ec_pse_status {
 };
 
 struct __ec_align1 ec_response_pse_status {
-	uint8_t status;	/* enum ec_pse_status */
+	uint8_t status; /* enum ec_pse_status */
 };
 
 /*****************************************************************************/
@@ -5411,25 +5473,25 @@ struct __ec_align1 ec_response_pse_status {
 
 /* Command */
 enum ec_reboot_cmd {
-	EC_REBOOT_CANCEL = 0,        /* Cancel a pending reboot */
-	EC_REBOOT_JUMP_RO = 1,       /* Jump to RO without rebooting */
-	EC_REBOOT_JUMP_RW = 2,       /* Jump to active RW without rebooting */
+	EC_REBOOT_CANCEL = 0, /* Cancel a pending reboot */
+	EC_REBOOT_JUMP_RO = 1, /* Jump to RO without rebooting */
+	EC_REBOOT_JUMP_RW = 2, /* Jump to active RW without rebooting */
 	/* (command 3 was jump to RW-B) */
-	EC_REBOOT_COLD = 4,          /* Cold-reboot */
-	EC_REBOOT_DISABLE_JUMP = 5,  /* Disable jump until next reboot */
-	EC_REBOOT_HIBERNATE = 6,     /* Hibernate EC */
+	EC_REBOOT_COLD = 4, /* Cold-reboot */
+	EC_REBOOT_DISABLE_JUMP = 5, /* Disable jump until next reboot */
+	EC_REBOOT_HIBERNATE = 6, /* Hibernate EC */
 	EC_REBOOT_HIBERNATE_CLEAR_AP_OFF = 7, /* and clears AP_IDLE flag */
-	EC_REBOOT_COLD_AP_OFF = 8,   /* Cold-reboot and don't boot AP */
+	EC_REBOOT_COLD_AP_OFF = 8, /* Cold-reboot and don't boot AP */
 };
 
 /* Flags for ec_params_reboot_ec.reboot_flags */
-#define EC_REBOOT_FLAG_RESERVED0      BIT(0)  /* Was recovery request */
-#define EC_REBOOT_FLAG_ON_AP_SHUTDOWN BIT(1)  /* Reboot after AP shutdown */
-#define EC_REBOOT_FLAG_SWITCH_RW_SLOT BIT(2)  /* Switch RW slot */
+#define EC_REBOOT_FLAG_RESERVED0 BIT(0) /* Was recovery request */
+#define EC_REBOOT_FLAG_ON_AP_SHUTDOWN BIT(1) /* Reboot after AP shutdown */
+#define EC_REBOOT_FLAG_SWITCH_RW_SLOT BIT(2) /* Switch RW slot */
 
 struct ec_params_reboot_ec {
-	uint8_t cmd;           /* enum ec_reboot_cmd */
-	uint8_t flags;         /* See EC_REBOOT_FLAG_* */
+	uint8_t cmd; /* enum ec_reboot_cmd */
+	uint8_t flags; /* See EC_REBOOT_FLAG_* */
 } __ec_align1;
 
 /*
@@ -5457,7 +5519,7 @@ struct ec_params_reboot_ec {
  *
  * Use EC_CMD_REBOOT_EC to reboot the EC more politely.
  */
-#define EC_CMD_REBOOT 0x00D1  /* Think "die" */
+#define EC_CMD_REBOOT 0x00D1 /* Think "die" */
 
 /*
  * Resend last response (not supported on LPC).
@@ -5492,50 +5554,66 @@ struct ec_params_reboot_ec {
 #define EC_VER_PD_EXCHANGE_STATUS 2
 
 enum pd_charge_state {
-	PD_CHARGE_NO_CHANGE = 0, /* Don't change charge state */
-	PD_CHARGE_NONE,          /* No charging allowed */
-	PD_CHARGE_5V,            /* 5V charging only */
-	PD_CHARGE_MAX            /* Charge at max voltage */
+	/* Don't change charge state */
+	PD_CHARGE_NO_CHANGE = 0,
+
+	/* No charging allowed */
+	PD_CHARGE_NONE,
+
+	/* 5V charging only */
+	PD_CHARGE_5V,
+
+	/* Charge at max voltage */
+	PD_CHARGE_MAX,
 };
 
 /* Status of EC being sent to PD */
-#define EC_STATUS_HIBERNATING	BIT(0)
+#define EC_STATUS_HIBERNATING BIT(0)
 
 struct ec_params_pd_status {
-	uint8_t status;       /* EC status */
-	int8_t batt_soc;      /* battery state of charge */
-	uint8_t charge_state; /* charging state (from enum pd_charge_state) */
+	/* EC status */
+	uint8_t status;
+
+	/* battery state of charge */
+	int8_t batt_soc;
+
+	/* charging state (from enum pd_charge_state) */
+	uint8_t charge_state;
 } __ec_align1;
 
 /* Status of PD being sent back to EC */
-#define PD_STATUS_HOST_EVENT      BIT(0) /* Forward host event to AP */
-#define PD_STATUS_IN_RW           BIT(1) /* Running RW image */
+#define PD_STATUS_HOST_EVENT BIT(0) /* Forward host event to AP */
+#define PD_STATUS_IN_RW BIT(1) /* Running RW image */
 #define PD_STATUS_JUMPED_TO_IMAGE BIT(2) /* Current image was jumped to */
-#define PD_STATUS_TCPC_ALERT_0    BIT(3) /* Alert active in port 0 TCPC */
-#define PD_STATUS_TCPC_ALERT_1    BIT(4) /* Alert active in port 1 TCPC */
-#define PD_STATUS_TCPC_ALERT_2    BIT(5) /* Alert active in port 2 TCPC */
-#define PD_STATUS_TCPC_ALERT_3    BIT(6) /* Alert active in port 3 TCPC */
-#define PD_STATUS_EC_INT_ACTIVE  (PD_STATUS_TCPC_ALERT_0 | \
-				      PD_STATUS_TCPC_ALERT_1 | \
-				      PD_STATUS_HOST_EVENT)
+#define PD_STATUS_TCPC_ALERT_0 BIT(3) /* Alert active in port 0 TCPC */
+#define PD_STATUS_TCPC_ALERT_1 BIT(4) /* Alert active in port 1 TCPC */
+#define PD_STATUS_TCPC_ALERT_2 BIT(5) /* Alert active in port 2 TCPC */
+#define PD_STATUS_TCPC_ALERT_3 BIT(6) /* Alert active in port 3 TCPC */
+#define PD_STATUS_EC_INT_ACTIVE \
+	(PD_STATUS_TCPC_ALERT_0 | PD_STATUS_TCPC_ALERT_1 | PD_STATUS_HOST_EVENT)
 struct ec_response_pd_status {
-	uint32_t curr_lim_ma;       /* input current limit */
-	uint16_t status;            /* PD MCU status */
-	int8_t active_charge_port;  /* active charging port */
+	/* input current limit */
+	uint32_t curr_lim_ma;
+
+	/* PD MCU status */
+	uint16_t status;
+
+	/* active charging port */
+	int8_t active_charge_port;
 } __ec_align_size1;
 
 /* AP to PD MCU host event status command, cleared on read */
 #define EC_CMD_PD_HOST_EVENT_STATUS 0x0104
 
 /* PD MCU host event status bits */
-#define PD_EVENT_UPDATE_DEVICE		BIT(0)
-#define PD_EVENT_POWER_CHANGE		BIT(1)
-#define PD_EVENT_IDENTITY_RECEIVED	BIT(2)
-#define PD_EVENT_DATA_SWAP		BIT(3)
-#define PD_EVENT_TYPEC			BIT(4)
+#define PD_EVENT_UPDATE_DEVICE BIT(0)
+#define PD_EVENT_POWER_CHANGE BIT(1)
+#define PD_EVENT_IDENTITY_RECEIVED BIT(2)
+#define PD_EVENT_DATA_SWAP BIT(3)
+#define PD_EVENT_TYPEC BIT(4)
 
 struct ec_response_host_event_status {
-	uint32_t status;      /* PD MCU host event status */
+	uint32_t status; /* PD MCU host event status */
 } __ec_align4;
 
 /*
@@ -5554,7 +5632,7 @@ enum usb_pd_control_role {
 	USB_PD_CTRL_ROLE_FORCE_SINK = 3,
 	USB_PD_CTRL_ROLE_FORCE_SOURCE = 4,
 	USB_PD_CTRL_ROLE_FREEZE = 5,
-	USB_PD_CTRL_ROLE_COUNT
+	USB_PD_CTRL_ROLE_COUNT,
 };
 
 enum usb_pd_control_mux {
@@ -5564,7 +5642,7 @@ enum usb_pd_control_mux {
 	USB_PD_CTRL_MUX_DP = 3,
 	USB_PD_CTRL_MUX_DOCK = 4,
 	USB_PD_CTRL_MUX_AUTO = 5,
-	USB_PD_CTRL_MUX_COUNT
+	USB_PD_CTRL_MUX_COUNT,
 };
 
 enum usb_pd_control_swap {
@@ -5572,7 +5650,7 @@ enum usb_pd_control_swap {
 	USB_PD_CTRL_SWAP_DATA = 1,
 	USB_PD_CTRL_SWAP_POWER = 2,
 	USB_PD_CTRL_SWAP_VCONN = 3,
-	USB_PD_CTRL_SWAP_COUNT
+	USB_PD_CTRL_SWAP_COUNT,
 };
 
 struct ec_params_usb_pd_control {
@@ -5582,17 +5660,18 @@ struct ec_params_usb_pd_control {
 	uint8_t swap;
 } __ec_align1;
 
-#define PD_CTRL_RESP_ENABLED_COMMS      BIT(0) /* Communication enabled */
-#define PD_CTRL_RESP_ENABLED_CONNECTED  BIT(1) /* Device connected */
+#define PD_CTRL_RESP_ENABLED_COMMS BIT(0) /* Communication enabled */
+#define PD_CTRL_RESP_ENABLED_CONNECTED BIT(1) /* Device connected */
 #define PD_CTRL_RESP_ENABLED_PD_CAPABLE BIT(2) /* Partner is PD capable */
 
-#define PD_CTRL_RESP_ROLE_POWER         BIT(0) /* 0=SNK/1=SRC */
-#define PD_CTRL_RESP_ROLE_DATA          BIT(1) /* 0=UFP/1=DFP */
-#define PD_CTRL_RESP_ROLE_VCONN         BIT(2) /* Vconn status */
-#define PD_CTRL_RESP_ROLE_DR_POWER      BIT(3) /* Partner is dualrole power */
-#define PD_CTRL_RESP_ROLE_DR_DATA       BIT(4) /* Partner is dualrole data */
-#define PD_CTRL_RESP_ROLE_USB_COMM      BIT(5) /* Partner USB comm capable */
-#define PD_CTRL_RESP_ROLE_UNCONSTRAINED BIT(6) /* Partner unconstrained power */
+#define PD_CTRL_RESP_ROLE_POWER BIT(0) /* 0=SNK/1=SRC */
+#define PD_CTRL_RESP_ROLE_DATA BIT(1) /* 0=UFP/1=DFP */
+#define PD_CTRL_RESP_ROLE_VCONN BIT(2) /* Vconn status */
+#define PD_CTRL_RESP_ROLE_DR_POWER BIT(3) /* Partner is dualrole power */
+#define PD_CTRL_RESP_ROLE_DR_DATA BIT(4) /* Partner is dualrole data */
+#define PD_CTRL_RESP_ROLE_USB_COMM BIT(5) /* Partner USB comm capable */
+/* Partner unconstrained power */
+#define PD_CTRL_RESP_ROLE_UNCONSTRAINED BIT(6)
 
 struct ec_response_usb_pd_control {
 	uint8_t enabled;
@@ -5610,39 +5689,39 @@ struct ec_response_usb_pd_control_v1 {
 
 /* Possible port partner connections based on CC line states */
 enum pd_cc_states {
-	PD_CC_NONE = 0,			/* No port partner attached */
+	PD_CC_NONE = 0, /* No port partner attached */
 
 	/* From DFP perspective */
-	PD_CC_UFP_NONE = 1,		/* No UFP accessory connected */
-	PD_CC_UFP_AUDIO_ACC = 2,	/* UFP Audio accessory connected */
-	PD_CC_UFP_DEBUG_ACC = 3,	/* UFP Debug accessory connected */
-	PD_CC_UFP_ATTACHED = 4,		/* Plain UFP attached */
+	PD_CC_UFP_NONE = 1, /* No UFP accessory connected */
+	PD_CC_UFP_AUDIO_ACC = 2, /* UFP Audio accessory connected */
+	PD_CC_UFP_DEBUG_ACC = 3, /* UFP Debug accessory connected */
+	PD_CC_UFP_ATTACHED = 4, /* Plain UFP attached */
 
 	/* From UFP perspective */
-	PD_CC_DFP_ATTACHED = 5,		/* Plain DFP attached */
-	PD_CC_DFP_DEBUG_ACC = 6,	/* DFP debug accessory connected */
+	PD_CC_DFP_ATTACHED = 5, /* Plain DFP attached */
+	PD_CC_DFP_DEBUG_ACC = 6, /* DFP debug accessory connected */
 };
 
 /* Active/Passive Cable */
-#define USB_PD_CTRL_ACTIVE_CABLE        BIT(0)
+#define USB_PD_CTRL_ACTIVE_CABLE BIT(0)
 /* Optical/Non-optical cable */
-#define USB_PD_CTRL_OPTICAL_CABLE       BIT(1)
+#define USB_PD_CTRL_OPTICAL_CABLE BIT(1)
 /* 3rd Gen TBT device (or AMA)/2nd gen tbt Adapter */
-#define USB_PD_CTRL_TBT_LEGACY_ADAPTER  BIT(2)
+#define USB_PD_CTRL_TBT_LEGACY_ADAPTER BIT(2)
 /* Active Link Uni-Direction */
-#define USB_PD_CTRL_ACTIVE_LINK_UNIDIR  BIT(3)
+#define USB_PD_CTRL_ACTIVE_LINK_UNIDIR BIT(3)
 
 struct ec_response_usb_pd_control_v2 {
 	uint8_t enabled;
 	uint8_t role;
 	uint8_t polarity;
 	char state[32];
-	uint8_t cc_state;	/* enum pd_cc_states representing cc state */
-	uint8_t dp_mode;	/* Current DP pin mode (MODE_DP_PIN_[A-E]) */
-	uint8_t reserved;	/* Reserved for future use */
-	uint8_t control_flags;	/* USB_PD_CTRL_*flags */
-	uint8_t cable_speed;	/* TBT_SS_* cable speed */
-	uint8_t cable_gen;	/* TBT_GEN3_* cable rounded support */
+	uint8_t cc_state; /* enum pd_cc_states representing cc state */
+	uint8_t dp_mode; /* Current DP pin mode (MODE_DP_PIN_[A-E]) */
+	uint8_t reserved; /* Reserved for future use */
+	uint8_t control_flags; /* USB_PD_CTRL_*flags */
+	uint8_t cable_speed; /* TBT_SS_* cable speed */
+	uint8_t cable_gen; /* TBT_GEN3_* cable rounded support */
 } __ec_align1;
 
 #define EC_CMD_USB_PD_PORTS 0x0102
@@ -5697,7 +5776,6 @@ struct ec_response_usb_pd_power_info {
 	uint32_t max_power;
 } __ec_align4;
 
-
 /*
  * This command will return the number of USB PD charge port + the number
  * of dedicated port present.
@@ -5731,7 +5809,10 @@ struct ec_params_usb_pd_fw_update {
 	uint16_t dev_id;
 	uint8_t cmd;
 	uint8_t port;
-	uint32_t size;     /* Size to write in bytes */
+
+	/* Size to write in bytes */
+	uint32_t size;
+
 	/* Followed by data to write */
 } __ec_align4;
 
@@ -5742,12 +5823,16 @@ struct ec_params_usb_pd_fw_update {
 struct ec_params_usb_pd_rw_hash_entry {
 	uint16_t dev_id;
 	uint8_t dev_rw_hash[PD_RW_HASH_SIZE];
-	uint8_t reserved;        /*
-				  * For alignment of current_image
-				  * TODO(rspangler) but it's not aligned!
-				  * Should have been reserved[2].
-				  */
-	uint32_t current_image;  /* One of ec_image */
+
+	/*
+	 * Reserved for alignment of current_image
+	 * TODO(rspangler) but it's not aligned!
+	 * Should have been reserved[2].
+	 */
+	uint8_t reserved;
+
+	/* One of ec_image */
+	uint32_t current_image;
 } __ec_align1;
 
 /* Read USB-PD Accessory info */
@@ -5760,8 +5845,8 @@ struct ec_params_usb_pd_info_request {
 /* Read USB-PD Device discovery info */
 #define EC_CMD_USB_PD_DISCOVERY 0x0113
 struct ec_params_usb_pd_discovery_entry {
-	uint16_t vid;  /* USB-IF VID */
-	uint16_t pid;  /* USB-IF PID */
+	uint16_t vid; /* USB-IF VID */
+	uint16_t pid; /* USB-IF PID */
 	uint8_t ptype; /* product type (hub,periph,cable,ama) */
 } __ec_align_size1;
 
@@ -5788,43 +5873,43 @@ struct ec_params_charge_port_override {
 
 struct ec_response_pd_log {
 	uint32_t timestamp; /* relative timestamp in milliseconds */
-	uint8_t type;       /* event type : see PD_EVENT_xx below */
-	uint8_t size_port;  /* [7:5] port number [4:0] payload size in bytes */
-	uint16_t data;      /* type-defined data payload */
+	uint8_t type; /* event type : see PD_EVENT_xx below */
+	uint8_t size_port; /* [7:5] port number [4:0] payload size in bytes */
+	uint16_t data; /* type-defined data payload */
 	uint8_t payload[0]; /* optional additional data payload: 0..16 bytes */
 } __ec_align4;
 
 /* The timestamp is the microsecond counter shifted to get about a ms. */
 #define PD_LOG_TIMESTAMP_SHIFT 10 /* 1 LSB = 1024us */
 
-#define PD_LOG_SIZE_MASK  0x1f
-#define PD_LOG_PORT_MASK  0xe0
-#define PD_LOG_PORT_SHIFT    5
-#define PD_LOG_PORT_SIZE(port, size) (((port) << PD_LOG_PORT_SHIFT) | \
-				      ((size) & PD_LOG_SIZE_MASK))
+#define PD_LOG_SIZE_MASK 0x1f
+#define PD_LOG_PORT_MASK 0xe0
+#define PD_LOG_PORT_SHIFT 5
+#define PD_LOG_PORT_SIZE(port, size) \
+	(((port) << PD_LOG_PORT_SHIFT) | ((size)&PD_LOG_SIZE_MASK))
 #define PD_LOG_PORT(size_port) ((size_port) >> PD_LOG_PORT_SHIFT)
-#define PD_LOG_SIZE(size_port) ((size_port) & PD_LOG_SIZE_MASK)
+#define PD_LOG_SIZE(size_port) ((size_port)&PD_LOG_SIZE_MASK)
 
 /* PD event log : entry types */
 /* PD MCU events */
-#define PD_EVENT_MCU_BASE       0x00
-#define PD_EVENT_MCU_CHARGE             (PD_EVENT_MCU_BASE+0)
-#define PD_EVENT_MCU_CONNECT            (PD_EVENT_MCU_BASE+1)
+#define PD_EVENT_MCU_BASE 0x00
+#define PD_EVENT_MCU_CHARGE (PD_EVENT_MCU_BASE + 0)
+#define PD_EVENT_MCU_CONNECT (PD_EVENT_MCU_BASE + 1)
 /* Reserved for custom board event */
-#define PD_EVENT_MCU_BOARD_CUSTOM       (PD_EVENT_MCU_BASE+2)
+#define PD_EVENT_MCU_BOARD_CUSTOM (PD_EVENT_MCU_BASE + 2)
 /* PD generic accessory events */
-#define PD_EVENT_ACC_BASE       0x20
-#define PD_EVENT_ACC_RW_FAIL   (PD_EVENT_ACC_BASE+0)
-#define PD_EVENT_ACC_RW_ERASE  (PD_EVENT_ACC_BASE+1)
+#define PD_EVENT_ACC_BASE 0x20
+#define PD_EVENT_ACC_RW_FAIL (PD_EVENT_ACC_BASE + 0)
+#define PD_EVENT_ACC_RW_ERASE (PD_EVENT_ACC_BASE + 1)
 /* PD power supply events */
-#define PD_EVENT_PS_BASE        0x40
-#define PD_EVENT_PS_FAULT      (PD_EVENT_PS_BASE+0)
+#define PD_EVENT_PS_BASE 0x40
+#define PD_EVENT_PS_FAULT (PD_EVENT_PS_BASE + 0)
 /* PD video dongles events */
-#define PD_EVENT_VIDEO_BASE     0x60
-#define PD_EVENT_VIDEO_DP_MODE (PD_EVENT_VIDEO_BASE+0)
-#define PD_EVENT_VIDEO_CODEC   (PD_EVENT_VIDEO_BASE+1)
+#define PD_EVENT_VIDEO_BASE 0x60
+#define PD_EVENT_VIDEO_DP_MODE (PD_EVENT_VIDEO_BASE + 0)
+#define PD_EVENT_VIDEO_CODEC (PD_EVENT_VIDEO_BASE + 1)
 /* Returned in the "type" field, when there is no entry available */
-#define PD_EVENT_NO_ENTRY       0xff
+#define PD_EVENT_NO_ENTRY 0xff
 
 /*
  * PD_EVENT_MCU_CHARGE event definition :
@@ -5832,24 +5917,24 @@ struct ec_response_pd_log {
  * the data field contains the port state flags as defined below :
  */
 /* Port partner is a dual role device */
-#define CHARGE_FLAGS_DUAL_ROLE         BIT(15)
+#define CHARGE_FLAGS_DUAL_ROLE BIT(15)
 /* Port is the pending override port */
-#define CHARGE_FLAGS_DELAYED_OVERRIDE  BIT(14)
+#define CHARGE_FLAGS_DELAYED_OVERRIDE BIT(14)
 /* Port is the override port */
-#define CHARGE_FLAGS_OVERRIDE          BIT(13)
+#define CHARGE_FLAGS_OVERRIDE BIT(13)
 /* Charger type */
-#define CHARGE_FLAGS_TYPE_SHIFT               3
-#define CHARGE_FLAGS_TYPE_MASK       (0xf << CHARGE_FLAGS_TYPE_SHIFT)
+#define CHARGE_FLAGS_TYPE_SHIFT 3
+#define CHARGE_FLAGS_TYPE_MASK (0xf << CHARGE_FLAGS_TYPE_SHIFT)
 /* Power delivery role */
-#define CHARGE_FLAGS_ROLE_MASK         (7 <<  0)
+#define CHARGE_FLAGS_ROLE_MASK (7 << 0)
 
 /*
  * PD_EVENT_PS_FAULT data field flags definition :
  */
-#define PS_FAULT_OCP                          1
-#define PS_FAULT_FAST_OCP                     2
-#define PS_FAULT_OVP                          3
-#define PS_FAULT_DISCH                        4
+#define PS_FAULT_OCP 1
+#define PS_FAULT_FAST_OCP 2
+#define PS_FAULT_OVP 3
+#define PS_FAULT_DISCH 4
 
 /*
  * PD_EVENT_VIDEO_CODEC payload is "struct mcdp_info".
@@ -5875,12 +5960,12 @@ struct mcdp_info {
 #define EC_CMD_USB_PD_GET_AMODE 0x0116
 struct ec_params_usb_pd_get_mode_request {
 	uint16_t svid_idx; /* SVID index to get */
-	uint8_t port;      /* port */
+	uint8_t port; /* port */
 } __ec_align_size1;
 
 struct ec_params_usb_pd_get_mode_response {
-	uint16_t svid;   /* SVID */
-	uint16_t opos;    /* Object Position */
+	uint16_t svid; /* SVID */
+	uint16_t opos; /* Object Position */
 	uint32_t vdo[6]; /* Mode VDOs */
 } __ec_align4;
 
@@ -5894,10 +5979,10 @@ enum pd_mode_cmd {
 };
 
 struct ec_params_usb_pd_set_mode_request {
-	uint32_t cmd;  /* enum pd_mode_cmd */
+	uint32_t cmd; /* enum pd_mode_cmd */
 	uint16_t svid; /* SVID to set */
-	uint8_t opos;  /* Object Position */
-	uint8_t port;  /* port */
+	uint8_t opos; /* Object Position */
+	uint8_t port; /* port */
 } __ec_align4;
 
 /* Ask the PD MCU to record a log of a requested type */
@@ -5908,20 +5993,19 @@ struct ec_params_pd_write_log_entry {
 	uint8_t port; /* port#, or 0 for events unrelated to a given port */
 } __ec_align1;
 
-
 /* Control USB-PD chip */
 #define EC_CMD_PD_CONTROL 0x0119
 
 enum ec_pd_control_cmd {
-	PD_SUSPEND = 0,      /* Suspend the PD chip (EC: stop talking to PD) */
-	PD_RESUME,           /* Resume the PD chip (EC: start talking to PD) */
-	PD_RESET,            /* Force reset the PD chip */
-	PD_CONTROL_DISABLE,  /* Disable further calls to this command */
-	PD_CHIP_ON,          /* Power on the PD chip */
+	PD_SUSPEND = 0, /* Suspend the PD chip (EC: stop talking to PD) */
+	PD_RESUME, /* Resume the PD chip (EC: start talking to PD) */
+	PD_RESET, /* Force reset the PD chip */
+	PD_CONTROL_DISABLE, /* Disable further calls to this command */
+	PD_CHIP_ON, /* Power on the PD chip */
 };
 
 struct ec_params_pd_control {
-	uint8_t chip;         /* chip id */
+	uint8_t chip; /* chip id */
 	uint8_t subcmd;
 } __ec_align1;
 
@@ -5933,29 +6017,29 @@ struct ec_params_usb_pd_mux_info {
 } __ec_align1;
 
 /* Flags representing mux state */
-#define USB_PD_MUX_NONE               0      /* Open switch */
-#define USB_PD_MUX_USB_ENABLED        BIT(0) /* USB connected */
-#define USB_PD_MUX_DP_ENABLED         BIT(1) /* DP connected */
-#define USB_PD_MUX_POLARITY_INVERTED  BIT(2) /* CC line Polarity inverted */
-#define USB_PD_MUX_HPD_IRQ            BIT(3) /* HPD IRQ is asserted */
-#define USB_PD_MUX_HPD_IRQ_DEASSERTED 0      /* HPD IRQ is deasserted */
-#define USB_PD_MUX_HPD_LVL            BIT(4) /* HPD level is asserted */
-#define USB_PD_MUX_HPD_LVL_DEASSERTED 0      /* HPD level is deasserted */
-#define USB_PD_MUX_SAFE_MODE          BIT(5) /* DP is in safe mode */
+#define USB_PD_MUX_NONE 0 /* Open switch */
+#define USB_PD_MUX_USB_ENABLED BIT(0) /* USB connected */
+#define USB_PD_MUX_DP_ENABLED BIT(1) /* DP connected */
+#define USB_PD_MUX_POLARITY_INVERTED BIT(2) /* CC line Polarity inverted */
+#define USB_PD_MUX_HPD_IRQ BIT(3) /* HPD IRQ is asserted */
+#define USB_PD_MUX_HPD_IRQ_DEASSERTED 0 /* HPD IRQ is deasserted */
+#define USB_PD_MUX_HPD_LVL BIT(4) /* HPD level is asserted */
+#define USB_PD_MUX_HPD_LVL_DEASSERTED 0 /* HPD level is deasserted */
+#define USB_PD_MUX_SAFE_MODE BIT(5) /* DP is in safe mode */
 #define USB_PD_MUX_TBT_COMPAT_ENABLED BIT(6) /* TBT compat enabled */
-#define USB_PD_MUX_USB4_ENABLED       BIT(7) /* USB4 enabled */
+#define USB_PD_MUX_USB4_ENABLED BIT(7) /* USB4 enabled */
 
 /* USB-C Dock connected */
-#define USB_PD_MUX_DOCK		(USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED)
+#define USB_PD_MUX_DOCK (USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED)
 
 struct ec_response_usb_pd_mux_info {
 	uint8_t flags; /* USB_PD_MUX_*-encoded USB mux state */
 } __ec_align1;
 
-#define EC_CMD_PD_CHIP_INFO		0x011B
+#define EC_CMD_PD_CHIP_INFO 0x011B
 
 struct ec_params_pd_chip_info {
-	uint8_t port;	/* USB-C port number */
+	uint8_t port; /* USB-C port number */
 	/*
 	 * Fetch the live chip info or hard-coded + cached chip info
 	 * 0: hardcoded value for VID/PID, cached value for FW version
@@ -5989,18 +6073,18 @@ struct ec_response_pd_chip_info_v1 {
 } __ec_align2;
 
 /* Run RW signature verification and get status */
-#define EC_CMD_RWSIG_CHECK_STATUS	0x011C
+#define EC_CMD_RWSIG_CHECK_STATUS 0x011C
 
 struct ec_response_rwsig_check_status {
 	uint32_t status;
 } __ec_align4;
 
 /* For controlling RWSIG task */
-#define EC_CMD_RWSIG_ACTION	0x011D
+#define EC_CMD_RWSIG_ACTION 0x011D
 
 enum rwsig_action {
-	RWSIG_ACTION_ABORT = 0,		/* Abort RWSIG and prevent jumping */
-	RWSIG_ACTION_CONTINUE = 1,	/* Jump to RW immediately */
+	RWSIG_ACTION_ABORT = 0, /* Abort RWSIG and prevent jumping */
+	RWSIG_ACTION_CONTINUE = 1, /* Jump to RW immediately */
 };
 
 struct ec_params_rwsig_action {
@@ -6008,10 +6092,10 @@ struct ec_params_rwsig_action {
 } __ec_align4;
 
 /* Run verification on a slot */
-#define EC_CMD_EFS_VERIFY	0x011E
+#define EC_CMD_EFS_VERIFY 0x011E
 
 struct ec_params_efs_verify {
-	uint8_t region;		/* enum ec_flash_region */
+	uint8_t region; /* enum ec_flash_region */
 } __ec_align1;
 
 /*
@@ -6019,25 +6103,26 @@ struct ec_params_efs_verify {
  * type. Integers return a uint32. Strings return a string, using the response
  * size to determine how big it is.
  */
-#define EC_CMD_GET_CROS_BOARD_INFO	0x011F
+#define EC_CMD_GET_CROS_BOARD_INFO 0x011F
 /*
  * Write info into Cros Board Info on EEPROM. Write fails if the board has
  * hardware write-protect enabled.
  */
-#define EC_CMD_SET_CROS_BOARD_INFO	0x0120
+#define EC_CMD_SET_CROS_BOARD_INFO 0x0120
 
 enum cbi_data_tag {
 	CBI_TAG_BOARD_VERSION = 0, /* uint32_t or smaller */
-	CBI_TAG_OEM_ID = 1,        /* uint32_t or smaller */
-	CBI_TAG_SKU_ID = 2,        /* uint32_t or smaller */
+	CBI_TAG_OEM_ID = 1, /* uint32_t or smaller */
+	CBI_TAG_SKU_ID = 2, /* uint32_t or smaller */
 	CBI_TAG_DRAM_PART_NUM = 3, /* variable length ascii, nul terminated. */
-	CBI_TAG_OEM_NAME = 4,      /* variable length ascii, nul terminated. */
-	CBI_TAG_MODEL_ID = 5,      /* uint32_t or smaller */
-	CBI_TAG_FW_CONFIG = 6,     /* uint32_t bit field */
-	CBI_TAG_PCB_SUPPLIER = 7,  /* uint32_t or smaller */
+	CBI_TAG_OEM_NAME = 4, /* variable length ascii, nul terminated. */
+	CBI_TAG_MODEL_ID = 5, /* uint32_t or smaller */
+	CBI_TAG_FW_CONFIG = 6, /* uint32_t bit field */
+	CBI_TAG_PCB_SUPPLIER = 7, /* uint32_t or smaller */
 	/* Second Source Factory Cache */
-	CBI_TAG_SSFC = 8,          /* uint32_t bit field */
-	CBI_TAG_REWORK_ID = 9,     /* uint64_t or smaller */
+	CBI_TAG_SSFC = 8, /* uint32_t bit field */
+	CBI_TAG_REWORK_ID = 9, /* uint64_t or smaller */
+	CBI_TAG_FACTORY_CALIBRATION_DATA = 10, /* uint32_t bit field */
 	CBI_TAG_COUNT,
 };
 
@@ -6047,11 +6132,11 @@ enum cbi_data_tag {
  * RELOAD:  Invalidate cache and read data from EEPROM. Useful to verify
  *          write was successful without reboot.
  */
-#define CBI_GET_RELOAD		BIT(0)
+#define CBI_GET_RELOAD BIT(0)
 
 struct ec_params_get_cbi {
-	uint32_t tag;		/* enum cbi_data_tag */
-	uint32_t flag;		/* CBI_GET_* */
+	uint32_t tag; /* enum cbi_data_tag */
+	uint32_t flag; /* CBI_GET_* */
 } __ec_align4;
 
 /*
@@ -6062,14 +6147,14 @@ struct ec_params_get_cbi {
  * INIT:    Need to be set when creating a new CBI from scratch. All fields
  *          will be initialized to zero first.
  */
-#define CBI_SET_NO_SYNC		BIT(0)
-#define CBI_SET_INIT		BIT(1)
+#define CBI_SET_NO_SYNC BIT(0)
+#define CBI_SET_INIT BIT(1)
 
 struct ec_params_set_cbi {
-	uint32_t tag;		/* enum cbi_data_tag */
-	uint32_t flag;		/* CBI_SET_* */
-	uint32_t size;		/* Data size */
-	uint8_t data[];		/* For string and raw data */
+	uint32_t tag; /* enum cbi_data_tag */
+	uint32_t flag; /* CBI_SET_* */
+	uint32_t size; /* Data size */
+	uint8_t data[]; /* For string and raw data */
 } __ec_align1;
 
 /*
@@ -6078,33 +6163,32 @@ struct ec_params_set_cbi {
 #define EC_CMD_GET_UPTIME_INFO 0x0121
 
 /* EC reset causes */
-#define EC_RESET_FLAG_OTHER       BIT(0)   /* Other known reason */
-#define EC_RESET_FLAG_RESET_PIN   BIT(1)   /* Reset pin asserted */
-#define EC_RESET_FLAG_BROWNOUT    BIT(2)   /* Brownout */
-#define EC_RESET_FLAG_POWER_ON    BIT(3)   /* Power-on reset */
-#define EC_RESET_FLAG_WATCHDOG    BIT(4)   /* Watchdog timer reset */
-#define EC_RESET_FLAG_SOFT        BIT(5)   /* Soft reset trigger by core */
-#define EC_RESET_FLAG_HIBERNATE   BIT(6)   /* Wake from hibernate */
-#define EC_RESET_FLAG_RTC_ALARM   BIT(7)   /* RTC alarm wake */
-#define EC_RESET_FLAG_WAKE_PIN    BIT(8)   /* Wake pin triggered wake */
-#define EC_RESET_FLAG_LOW_BATTERY BIT(9)   /* Low battery triggered wake */
-#define EC_RESET_FLAG_SYSJUMP     BIT(10)  /* Jumped directly to this image */
-#define EC_RESET_FLAG_HARD        BIT(11)  /* Hard reset from software */
-#define EC_RESET_FLAG_AP_OFF      BIT(12)  /* Do not power on AP */
-#define EC_RESET_FLAG_PRESERVED   BIT(13)  /* Some reset flags preserved from
-					    * previous boot
-					    */
-#define EC_RESET_FLAG_USB_RESUME  BIT(14)  /* USB resume triggered wake */
-#define EC_RESET_FLAG_RDD         BIT(15)  /* USB Type-C debug cable */
-#define EC_RESET_FLAG_RBOX        BIT(16)  /* Fixed Reset Functionality */
-#define EC_RESET_FLAG_SECURITY    BIT(17)  /* Security threat */
-#define EC_RESET_FLAG_AP_WATCHDOG BIT(18)  /* AP experienced a watchdog reset */
-#define EC_RESET_FLAG_STAY_IN_RO  BIT(19)  /* Do not select RW in EFS. This
-					    * enables PD in RO for Chromebox.
-					    */
-#define EC_RESET_FLAG_EFS         BIT(20)  /* Jumped to this image by EFS */
-#define EC_RESET_FLAG_AP_IDLE     BIT(21)  /* Leave alone AP */
-#define EC_RESET_FLAG_INITIAL_PWR BIT(22)  /* EC had power, then was reset */
+#define EC_RESET_FLAG_OTHER BIT(0) /* Other known reason */
+#define EC_RESET_FLAG_RESET_PIN BIT(1) /* Reset pin asserted */
+#define EC_RESET_FLAG_BROWNOUT BIT(2) /* Brownout */
+#define EC_RESET_FLAG_POWER_ON BIT(3) /* Power-on reset */
+#define EC_RESET_FLAG_WATCHDOG BIT(4) /* Watchdog timer reset */
+#define EC_RESET_FLAG_SOFT BIT(5) /* Soft reset trigger by core */
+#define EC_RESET_FLAG_HIBERNATE BIT(6) /* Wake from hibernate */
+#define EC_RESET_FLAG_RTC_ALARM BIT(7) /* RTC alarm wake */
+#define EC_RESET_FLAG_WAKE_PIN BIT(8) /* Wake pin triggered wake */
+#define EC_RESET_FLAG_LOW_BATTERY BIT(9) /* Low battery triggered wake */
+#define EC_RESET_FLAG_SYSJUMP BIT(10) /* Jumped directly to this image */
+#define EC_RESET_FLAG_HARD BIT(11) /* Hard reset from software */
+#define EC_RESET_FLAG_AP_OFF BIT(12) /* Do not power on AP */
+/* Some reset flags preserved from previous boot */
+#define EC_RESET_FLAG_PRESERVED BIT(13)
+#define EC_RESET_FLAG_USB_RESUME BIT(14) /* USB resume triggered wake */
+#define EC_RESET_FLAG_RDD BIT(15) /* USB Type-C debug cable */
+#define EC_RESET_FLAG_RBOX BIT(16) /* Fixed Reset Functionality */
+#define EC_RESET_FLAG_SECURITY BIT(17) /* Security threat */
+/* AP experienced a watchdog reset */
+#define EC_RESET_FLAG_AP_WATCHDOG BIT(18)
+/* Do not select RW in EFS. This enables PD in RO for Chromebox. */
+#define EC_RESET_FLAG_STAY_IN_RO BIT(19)
+#define EC_RESET_FLAG_EFS BIT(20) /* Jumped to this image by EFS */
+#define EC_RESET_FLAG_AP_IDLE BIT(21) /* Leave alone AP */
+#define EC_RESET_FLAG_INITIAL_PWR BIT(22) /* EC had power, then was reset */
 
 /*
  * Reason codes used by the AP after a shutdown to figure out why it was reset
@@ -6172,7 +6256,6 @@ enum chipset_shutdown_reason {
 	CHIPSET_SHUTDOWN_COUNT, /* End of shutdown reasons. */
 };
 
-
 struct ec_response_uptime_info {
 	/*
 	 * Number of milliseconds since the last EC boot. Sysjump resets
@@ -6221,7 +6304,7 @@ struct ec_response_uptime_info {
  * Depending on the chip, the operation may take a long time (e.g. to erase
  * flash), so the commands are asynchronous.
  */
-#define EC_CMD_ADD_ENTROPY	0x0122
+#define EC_CMD_ADD_ENTROPY 0x0122
 
 enum add_entropy_action {
 	/* Add entropy to the current secret. */
@@ -6243,7 +6326,7 @@ struct ec_params_rollback_add_entropy {
 /*
  * Perform a single read of a given ADC channel.
  */
-#define EC_CMD_ADC_READ		0x0123
+#define EC_CMD_ADC_READ 0x0123
 
 struct ec_params_adc_read {
 	uint8_t adc_channel;
@@ -6256,7 +6339,7 @@ struct ec_response_adc_read {
 /*
  * Read back rollback info
  */
-#define EC_CMD_ROLLBACK_INFO		0x0124
+#define EC_CMD_ROLLBACK_INFO 0x0124
 
 struct ec_response_rollback_info {
 	int32_t id; /* Incrementing number to indicate which region to use. */
@@ -6264,7 +6347,6 @@ struct ec_response_rollback_info {
 	int32_t rw_rollback_version;
 } __ec_align4;
 
-
 /* Issue AP reset */
 #define EC_CMD_AP_RESET 0x0125
 
@@ -6293,23 +6375,22 @@ enum ec_bus_type {
 };
 
 struct ec_i2c_info {
-	uint16_t port;		/* Physical port for device */
-	uint16_t addr_flags;	/* 7-bit (or 10-bit) address */
+	uint16_t port; /* Physical port for device */
+	uint16_t addr_flags; /* 7-bit (or 10-bit) address */
 };
 
 struct ec_params_locate_chip {
-	uint8_t type;		/* enum ec_chip_type */
-	uint8_t index;		/* Specifies one instance of chip type */
+	uint8_t type; /* enum ec_chip_type */
+	uint8_t index; /* Specifies one instance of chip type */
 	/* Used for type specific parameters in future */
 	union {
 		uint16_t reserved;
 	};
 } __ec_align2;
 
-
 struct ec_response_locate_chip {
-	uint8_t bus_type;	/* enum ec_bus_type */
-	uint8_t reserved;	/* Aligning the following union to 2 bytes */
+	uint8_t bus_type; /* enum ec_bus_type */
+	uint8_t reserved; /* Aligning the following union to 2 bytes */
 	union {
 		struct ec_i2c_info i2c_info;
 	};
@@ -6380,27 +6461,27 @@ enum ec_pd_port_location {
 	 * left side, while BACK_LEFT means the leftmost port on the back of the
 	 * device.
 	 */
-	EC_PD_PORT_LOCATION_LEFT        = 1,
-	EC_PD_PORT_LOCATION_RIGHT       = 2,
-	EC_PD_PORT_LOCATION_BACK        = 3,
-	EC_PD_PORT_LOCATION_FRONT       = 4,
-	EC_PD_PORT_LOCATION_LEFT_FRONT  = 5,
-	EC_PD_PORT_LOCATION_LEFT_BACK   = 6,
+	EC_PD_PORT_LOCATION_LEFT = 1,
+	EC_PD_PORT_LOCATION_RIGHT = 2,
+	EC_PD_PORT_LOCATION_BACK = 3,
+	EC_PD_PORT_LOCATION_FRONT = 4,
+	EC_PD_PORT_LOCATION_LEFT_FRONT = 5,
+	EC_PD_PORT_LOCATION_LEFT_BACK = 6,
 	EC_PD_PORT_LOCATION_RIGHT_FRONT = 7,
-	EC_PD_PORT_LOCATION_RIGHT_BACK  = 8,
-	EC_PD_PORT_LOCATION_BACK_LEFT   = 9,
-	EC_PD_PORT_LOCATION_BACK_RIGHT  = 10,
+	EC_PD_PORT_LOCATION_RIGHT_BACK = 8,
+	EC_PD_PORT_LOCATION_BACK_LEFT = 9,
+	EC_PD_PORT_LOCATION_BACK_RIGHT = 10,
 };
 
 struct ec_params_get_pd_port_caps {
-	uint8_t port;		/* Which port to interrogate */
+	uint8_t port; /* Which port to interrogate */
 } __ec_align1;
 
 struct ec_response_get_pd_port_caps {
-	uint8_t pd_power_role_cap;	/* enum ec_pd_power_role_caps */
-	uint8_t pd_try_power_role_cap;	/* enum ec_pd_try_power_role_caps */
-	uint8_t pd_data_role_cap;	/* enum ec_pd_data_role_caps */
-	uint8_t pd_port_location;	/* enum ec_pd_port_location */
+	uint8_t pd_power_role_cap; /* enum ec_pd_power_role_caps */
+	uint8_t pd_try_power_role_cap; /* enum ec_pd_try_power_role_caps */
+	uint8_t pd_data_role_cap; /* enum ec_pd_data_role_caps */
+	uint8_t pd_port_location; /* enum ec_pd_port_location */
 } __ec_align1;
 
 /*****************************************************************************/
@@ -6417,27 +6498,27 @@ struct ec_response_get_pd_port_caps {
 
 struct ec_params_button {
 	/* Button mask aligned to enum keyboard_button_type */
-	uint32_t  btn_mask;
+	uint32_t btn_mask;
 
 	/* Duration in milliseconds button needs to be pressed */
-	uint32_t  press_ms;
+	uint32_t press_ms;
 } __ec_align1;
 
 enum keyboard_button_type {
-	KEYBOARD_BUTTON_POWER       = 0,
+	KEYBOARD_BUTTON_POWER = 0,
 	KEYBOARD_BUTTON_VOLUME_DOWN = 1,
-	KEYBOARD_BUTTON_VOLUME_UP   = 2,
-	KEYBOARD_BUTTON_RECOVERY    = 3,
-	KEYBOARD_BUTTON_CAPSENSE_1  = 4,
-	KEYBOARD_BUTTON_CAPSENSE_2  = 5,
-	KEYBOARD_BUTTON_CAPSENSE_3  = 6,
-	KEYBOARD_BUTTON_CAPSENSE_4  = 7,
-	KEYBOARD_BUTTON_CAPSENSE_5  = 8,
-	KEYBOARD_BUTTON_CAPSENSE_6  = 9,
-	KEYBOARD_BUTTON_CAPSENSE_7  = 10,
-	KEYBOARD_BUTTON_CAPSENSE_8  = 11,
+	KEYBOARD_BUTTON_VOLUME_UP = 2,
+	KEYBOARD_BUTTON_RECOVERY = 3,
+	KEYBOARD_BUTTON_CAPSENSE_1 = 4,
+	KEYBOARD_BUTTON_CAPSENSE_2 = 5,
+	KEYBOARD_BUTTON_CAPSENSE_3 = 6,
+	KEYBOARD_BUTTON_CAPSENSE_4 = 7,
+	KEYBOARD_BUTTON_CAPSENSE_5 = 8,
+	KEYBOARD_BUTTON_CAPSENSE_6 = 9,
+	KEYBOARD_BUTTON_CAPSENSE_7 = 10,
+	KEYBOARD_BUTTON_CAPSENSE_8 = 11,
 
-	KEYBOARD_BUTTON_COUNT
+	KEYBOARD_BUTTON_COUNT,
 };
 
 /*****************************************************************************/
@@ -6491,15 +6572,15 @@ enum action_key {
  * action keys. This is possible for e.g. if the keyboard has a
  * dedicated Fn key.
  */
-#define KEYBD_CAP_FUNCTION_KEYS		BIT(0)
+#define KEYBD_CAP_FUNCTION_KEYS BIT(0)
 /*
  * Whether the keyboard has a dedicated numeric keyboard.
  */
-#define KEYBD_CAP_NUMERIC_KEYPAD	BIT(1)
+#define KEYBD_CAP_NUMERIC_KEYPAD BIT(1)
 /*
  * Whether the keyboard has a screenlock key.
  */
-#define KEYBD_CAP_SCRNLOCK_KEY		BIT(2)
+#define KEYBD_CAP_SCRNLOCK_KEY BIT(2)
 
 struct ec_response_keybd_config {
 	/*
@@ -6526,12 +6607,12 @@ struct ec_response_keybd_config {
  */
 #define EC_CMD_SMART_DISCHARGE 0x012B
 
-#define EC_SMART_DISCHARGE_FLAGS_SET	BIT(0)
+#define EC_SMART_DISCHARGE_FLAGS_SET BIT(0)
 
 /* Discharge rates when the system is in cutoff or hibernation. */
 struct discharge_rate {
-	uint16_t cutoff;  /* Discharge rate (uA) in cutoff */
-	uint16_t hibern;  /* Discharge rate (uA) in hibernation */
+	uint16_t cutoff; /* Discharge rate (uA) in cutoff */
+	uint16_t hibern; /* Discharge rate (uA) in hibernation */
 };
 
 struct smart_discharge_zone {
@@ -6542,7 +6623,7 @@ struct smart_discharge_zone {
 };
 
 struct ec_params_smart_discharge {
-	uint8_t flags;  /* EC_SMART_DISCHARGE_FLAGS_* */
+	uint8_t flags; /* EC_SMART_DISCHARGE_FLAGS_* */
 	/*
 	 * Desired hours for the battery to survive before reaching 0%. Set to
 	 * zero to disable smart discharging. That is, the system hibernates as
@@ -6667,13 +6748,13 @@ struct ec_params_typec_discovery {
 
 struct svid_mode_info {
 	uint16_t svid;
-	uint16_t mode_count;  /* Number of modes partner sent */
+	uint16_t mode_count; /* Number of modes partner sent */
 	uint32_t mode_vdo[6]; /* Max VDOs allowed after VDM header is 6 */
 };
 
 struct ec_response_typec_discovery {
-	uint8_t identity_count;    /* Number of identity VDOs partner sent */
-	uint8_t svid_count;	   /* Number of SVIDs partner sent */
+	uint8_t identity_count; /* Number of identity VDOs partner sent */
+	uint8_t svid_count; /* Number of SVIDs partner sent */
 	uint16_t reserved;
 	uint32_t discovery_vdo[6]; /* Max VDOs allowed after VDM header is 6 */
 	struct svid_mode_info svids[0];
@@ -6703,14 +6784,19 @@ enum typec_tbt_ufp_reply {
 	TYPEC_TBT_UFP_REPLY_ACK,
 };
 
+#define TYPEC_USB_MUX_SET_ALL_CHIPS 0xFF
+
 struct typec_usb_mux_set {
-	uint8_t mux_index;	/* Index of the mux to set in the chain */
-	uint8_t mux_flags;	/* USB_PD_MUX_*-encoded USB mux state to set */
+	/* Index of the mux to set in the chain */
+	uint8_t mux_index;
+
+	/* USB_PD_MUX_*-encoded USB mux state to set */
+	uint8_t mux_flags;
 } __ec_align1;
 
 struct ec_params_typec_control {
 	uint8_t port;
-	uint8_t command;	/* enum typec_control_command */
+	uint8_t command; /* enum typec_control_command */
 	uint16_t reserved;
 
 	/*
@@ -6752,7 +6838,7 @@ struct ec_params_typec_control {
  */
 enum pd_power_role {
 	PD_ROLE_SINK = 0,
-	PD_ROLE_SOURCE = 1
+	PD_ROLE_SOURCE = 1,
 };
 
 /*
@@ -6799,23 +6885,23 @@ enum tcpc_cc_polarity {
 	 * that this will give a hint that other places need to be
 	 * adjusted.
 	 */
-	POLARITY_COUNT
+	POLARITY_COUNT,
 };
 
-#define MODE_DP_PIN_A	BIT(0)
-#define MODE_DP_PIN_B	BIT(1)
-#define MODE_DP_PIN_C	BIT(2)
-#define MODE_DP_PIN_D	BIT(3)
-#define MODE_DP_PIN_E	BIT(4)
-#define MODE_DP_PIN_F	BIT(5)
-#define MODE_DP_PIN_ALL	GENMASK(5, 0)
+#define MODE_DP_PIN_A BIT(0)
+#define MODE_DP_PIN_B BIT(1)
+#define MODE_DP_PIN_C BIT(2)
+#define MODE_DP_PIN_D BIT(3)
+#define MODE_DP_PIN_E BIT(4)
+#define MODE_DP_PIN_F BIT(5)
+#define MODE_DP_PIN_ALL GENMASK(5, 0)
 
-#define PD_STATUS_EVENT_SOP_DISC_DONE		BIT(0)
-#define PD_STATUS_EVENT_SOP_PRIME_DISC_DONE	BIT(1)
-#define PD_STATUS_EVENT_HARD_RESET		BIT(2)
-#define PD_STATUS_EVENT_DISCONNECTED		BIT(3)
-#define PD_STATUS_EVENT_MUX_0_SET_DONE		BIT(4)
-#define PD_STATUS_EVENT_MUX_1_SET_DONE		BIT(5)
+#define PD_STATUS_EVENT_SOP_DISC_DONE BIT(0)
+#define PD_STATUS_EVENT_SOP_PRIME_DISC_DONE BIT(1)
+#define PD_STATUS_EVENT_HARD_RESET BIT(2)
+#define PD_STATUS_EVENT_DISCONNECTED BIT(3)
+#define PD_STATUS_EVENT_MUX_0_SET_DONE BIT(4)
+#define PD_STATUS_EVENT_MUX_1_SET_DONE BIT(5)
 
 /*
  * Encode and decode for BCD revision response
@@ -6824,9 +6910,9 @@ enum tcpc_cc_polarity {
  * Specification Revision from the PD header, which currently only maps to PD
  * 1.0-3.0 with the major revision being one greater than the binary value.
  */
-#define PD_STATUS_REV_SET_MAJOR(r)	((r + 1) << 12)
-#define PD_STATUS_REV_GET_MAJOR(r)	((r >> 12) & 0xF)
-#define PD_STATUS_REV_GET_MINOR(r)	((r >> 8)  & 0xF)
+#define PD_STATUS_REV_SET_MAJOR(r) ((r + 1) << 12)
+#define PD_STATUS_REV_GET_MAJOR(r) ((r >> 12) & 0xF)
+#define PD_STATUS_REV_GET_MINOR(r) ((r >> 8) & 0xF)
 
 /*
  * Decode helpers for Source and Sink Capability PDOs
@@ -6834,11 +6920,11 @@ enum tcpc_cc_polarity {
  * Note: The Power Delivery Specification should be considered the ultimate
  * source of truth on the decoding of these PDOs
  */
-#define PDO_TYPE_FIXED     (0 << 30)
-#define PDO_TYPE_BATTERY   (1 << 30)
-#define PDO_TYPE_VARIABLE  (2 << 30)
+#define PDO_TYPE_FIXED (0 << 30)
+#define PDO_TYPE_BATTERY (1 << 30)
+#define PDO_TYPE_VARIABLE (2 << 30)
 #define PDO_TYPE_AUGMENTED (3 << 30)
-#define PDO_TYPE_MASK      (3 << 30)
+#define PDO_TYPE_MASK (3 << 30)
 
 /*
  * From Table 6-9 and Table 6-14 PD Rev 3.0 Ver 2.0
@@ -6853,13 +6939,13 @@ enum tcpc_cc_polarity {
  * <19:10> : Voltage in 50mV Units
  * <9:0>   : Maximum Current in 10mA units
  */
-#define PDO_FIXED_DUAL_ROLE	BIT(29)
-#define PDO_FIXED_UNCONSTRAINED	BIT(27)
-#define PDO_FIXED_COMM_CAP	BIT(26)
-#define PDO_FIXED_DATA_SWAP	BIT(25)
+#define PDO_FIXED_DUAL_ROLE BIT(29)
+#define PDO_FIXED_UNCONSTRAINED BIT(27)
+#define PDO_FIXED_COMM_CAP BIT(26)
+#define PDO_FIXED_DATA_SWAP BIT(25)
 #define PDO_FIXED_FRS_CURR_MASK GENMASK(24, 23) /* Sink Cap only */
-#define PDO_FIXED_VOLTAGE(p)	((p >> 10 & 0x3FF) * 50)
-#define PDO_FIXED_CURRENT(p)	((p & 0x3FF) * 10)
+#define PDO_FIXED_VOLTAGE(p) ((p >> 10 & 0x3FF) * 50)
+#define PDO_FIXED_CURRENT(p) ((p & 0x3FF) * 10)
 
 /*
  * From Table 6-12 and Table 6-16 PD Rev 3.0 Ver 2.0
@@ -6869,9 +6955,9 @@ enum tcpc_cc_polarity {
  * <19:10> : Minimum Voltage in 50mV units
  * <9:0>   : Maximum Allowable Power in 250mW units
  */
-#define PDO_BATT_MAX_VOLTAGE(p)	((p >> 20 & 0x3FF) * 50)
-#define PDO_BATT_MIN_VOLTAGE(p)	((p >> 10 & 0x3FF) * 50)
-#define PDO_BATT_MAX_POWER(p)	((p & 0x3FF) * 250)
+#define PDO_BATT_MAX_VOLTAGE(p) ((p >> 20 & 0x3FF) * 50)
+#define PDO_BATT_MIN_VOLTAGE(p) ((p >> 10 & 0x3FF) * 50)
+#define PDO_BATT_MAX_POWER(p) ((p & 0x3FF) * 250)
 
 /*
  * From Table 6-11 and Table 6-15 PD Rev 3.0 Ver 2.0
@@ -6881,9 +6967,9 @@ enum tcpc_cc_polarity {
  * <19:10> : Minimum Voltage in 50mV units
  * <9:0>   : Operational Current in 10mA units
  */
-#define PDO_VAR_MAX_VOLTAGE(p)	((p >> 20 & 0x3FF) * 50)
-#define PDO_VAR_MIN_VOLTAGE(p)	((p >> 10 & 0x3FF) * 50)
-#define PDO_VAR_MAX_CURRENT(p)	((p & 0x3FF) * 10)
+#define PDO_VAR_MAX_VOLTAGE(p) ((p >> 20 & 0x3FF) * 50)
+#define PDO_VAR_MIN_VOLTAGE(p) ((p >> 10 & 0x3FF) * 50)
+#define PDO_VAR_MAX_CURRENT(p) ((p & 0x3FF) * 10)
 
 /*
  * From Table 6-13 and Table 6-17 PD Rev 3.0 Ver 2.0
@@ -6901,33 +6987,33 @@ enum tcpc_cc_polarity {
  * <7>     : Reserved
  * <6:0>   : Maximum Current in 50mA increments
  */
-#define PDO_AUG_MAX_VOLTAGE(p)	((p >> 17 & 0xFF) * 100)
-#define PDO_AUG_MIN_VOLTAGE(p)	((p >> 8 & 0xFF) * 100)
-#define PDO_AUG_MAX_CURRENT(p)	((p & 0x7F) * 50)
+#define PDO_AUG_MAX_VOLTAGE(p) ((p >> 17 & 0xFF) * 100)
+#define PDO_AUG_MIN_VOLTAGE(p) ((p >> 8 & 0xFF) * 100)
+#define PDO_AUG_MAX_CURRENT(p) ((p & 0x7F) * 50)
 
 struct ec_params_typec_status {
 	uint8_t port;
 } __ec_align1;
 
 struct ec_response_typec_status {
-	uint8_t pd_enabled;		/* PD communication enabled - bool */
-	uint8_t dev_connected;		/* Device connected - bool */
-	uint8_t sop_connected;		/* Device is SOP PD capable - bool */
-	uint8_t source_cap_count;	/* Number of Source Cap PDOs */
+	uint8_t pd_enabled; /* PD communication enabled - bool */
+	uint8_t dev_connected; /* Device connected - bool */
+	uint8_t sop_connected; /* Device is SOP PD capable - bool */
+	uint8_t source_cap_count; /* Number of Source Cap PDOs */
 
-	uint8_t power_role;		/* enum pd_power_role */
-	uint8_t data_role;		/* enum pd_data_role */
-	uint8_t vconn_role;		/* enum pd_vconn_role */
-	uint8_t sink_cap_count;		/* Number of Sink Cap PDOs */
+	uint8_t power_role; /* enum pd_power_role */
+	uint8_t data_role; /* enum pd_data_role */
+	uint8_t vconn_role; /* enum pd_vconn_role */
+	uint8_t sink_cap_count; /* Number of Sink Cap PDOs */
 
-	uint8_t polarity;		/* enum tcpc_cc_polarity */
-	uint8_t cc_state;		/* enum pd_cc_states */
-	uint8_t dp_pin;			/* DP pin mode (MODE_DP_IN_[A-E]) */
-	uint8_t mux_state;		/* USB_PD_MUX* - encoded mux state */
+	uint8_t polarity; /* enum tcpc_cc_polarity */
+	uint8_t cc_state; /* enum pd_cc_states */
+	uint8_t dp_pin; /* DP pin mode (MODE_DP_IN_[A-E]) */
+	uint8_t mux_state; /* USB_PD_MUX* - encoded mux state */
 
-	char tc_state[32];		/* TC state name */
+	char tc_state[32]; /* TC state name */
 
-	uint32_t events;		/* PD_STATUS_EVENT bitmask */
+	uint32_t events; /* PD_STATUS_EVENT bitmask */
 
 	/*
 	 * BCD PD revisions for partners
@@ -6942,9 +7028,9 @@ struct ec_response_typec_status {
 	uint16_t sop_revision;
 	uint16_t sop_prime_revision;
 
-	uint32_t source_cap_pdos[7];	/* Max 7 PDOs can be present */
+	uint32_t source_cap_pdos[7]; /* Max 7 PDOs can be present */
 
-	uint32_t sink_cap_pdos[7];	/* Max 7 PDOs can be present */
+	uint32_t sink_cap_pdos[7]; /* Max 7 PDOs can be present */
 } __ec_align1;
 
 /**
@@ -6968,8 +7054,8 @@ struct ec_params_pchg {
 } __ec_align1;
 
 struct ec_response_pchg {
-	uint32_t error;			/* enum pchg_error */
-	uint8_t state;			/* enum pchg_state state */
+	uint32_t error; /* enum pchg_error */
+	uint8_t state; /* enum pchg_state state */
 	uint8_t battery_percentage;
 	uint8_t unused0;
 	uint8_t unused1;
@@ -6979,8 +7065,8 @@ struct ec_response_pchg {
 } __ec_align4;
 
 struct ec_response_pchg_v2 {
-	uint32_t error;			/* enum pchg_error */
-	uint8_t state;			/* enum pchg_state state */
+	uint32_t error; /* enum pchg_error */
+	uint8_t state; /* enum pchg_state state */
 	uint8_t battery_percentage;
 	uint8_t unused0;
 	uint8_t unused1;
@@ -7014,17 +7100,20 @@ enum pchg_state {
 	PCHG_STATE_COUNT,
 };
 
-#define EC_PCHG_STATE_TEXT { \
-	[PCHG_STATE_RESET] = "RESET", \
-	[PCHG_STATE_INITIALIZED] = "INITIALIZED", \
-	[PCHG_STATE_ENABLED] = "ENABLED", \
-	[PCHG_STATE_DETECTED] = "DETECTED", \
-	[PCHG_STATE_CHARGING] = "CHARGING", \
-	[PCHG_STATE_FULL] = "FULL", \
-	[PCHG_STATE_DOWNLOAD] = "DOWNLOAD", \
-	[PCHG_STATE_DOWNLOADING] = "DOWNLOADING", \
-	[PCHG_STATE_CONNECTED] = "CONNECTED", \
+/* clang-format off */
+#define EC_PCHG_STATE_TEXT                                \
+	{                                                 \
+		[PCHG_STATE_RESET] = "RESET",             \
+		[PCHG_STATE_INITIALIZED] = "INITIALIZED", \
+		[PCHG_STATE_ENABLED] = "ENABLED",         \
+		[PCHG_STATE_DETECTED] = "DETECTED",       \
+		[PCHG_STATE_CHARGING] = "CHARGING",       \
+		[PCHG_STATE_FULL] = "FULL",               \
+		[PCHG_STATE_DOWNLOAD] = "DOWNLOAD",       \
+		[PCHG_STATE_DOWNLOADING] = "DOWNLOADING", \
+		[PCHG_STATE_CONNECTED] = "CONNECTED",     \
 	}
+/* clang-format on */
 
 /**
  * Update firmware of peripheral chip
@@ -7032,19 +7121,18 @@ enum pchg_state {
 #define EC_CMD_PCHG_UPDATE 0x0136
 
 /* Port number is encoded in bit[28:31]. */
-#define EC_MKBP_PCHG_PORT_SHIFT		28
+#define EC_MKBP_PCHG_PORT_SHIFT 28
 /* Utility macros for converting MKBP event <-> port number. */
-#define EC_MKBP_PCHG_EVENT_TO_PORT(e)	(((e) >> EC_MKBP_PCHG_PORT_SHIFT) & 0xf)
-#define EC_MKBP_PCHG_PORT_TO_EVENT(p)	((p) << EC_MKBP_PCHG_PORT_SHIFT)
+#define EC_MKBP_PCHG_EVENT_TO_PORT(e) (((e) >> EC_MKBP_PCHG_PORT_SHIFT) & 0xf)
+#define EC_MKBP_PCHG_PORT_TO_EVENT(p) ((p) << EC_MKBP_PCHG_PORT_SHIFT)
 /* Utility macro for extracting event bits. */
-#define EC_MKBP_PCHG_EVENT_MASK(e)	((e) \
-					& GENMASK(EC_MKBP_PCHG_PORT_SHIFT-1, 0))
+#define EC_MKBP_PCHG_EVENT_MASK(e) ((e)&GENMASK(EC_MKBP_PCHG_PORT_SHIFT - 1, 0))
 
-#define EC_MKBP_PCHG_UPDATE_OPENED	BIT(0)
-#define EC_MKBP_PCHG_WRITE_COMPLETE	BIT(1)
-#define EC_MKBP_PCHG_UPDATE_CLOSED	BIT(2)
-#define EC_MKBP_PCHG_UPDATE_ERROR	BIT(3)
-#define EC_MKBP_PCHG_DEVICE_EVENT	BIT(4)
+#define EC_MKBP_PCHG_UPDATE_OPENED BIT(0)
+#define EC_MKBP_PCHG_WRITE_COMPLETE BIT(1)
+#define EC_MKBP_PCHG_UPDATE_CLOSED BIT(2)
+#define EC_MKBP_PCHG_UPDATE_ERROR BIT(3)
+#define EC_MKBP_PCHG_DEVICE_EVENT BIT(4)
 
 enum ec_pchg_update_cmd {
 	/* Reset chip to normal mode. */
@@ -7079,28 +7167,29 @@ struct ec_params_pchg_update {
 	uint8_t data[];
 } __ec_align4;
 
-BUILD_ASSERT(EC_PCHG_UPDATE_CMD_COUNT
-	     < BIT(sizeof(((struct ec_params_pchg_update *)0)->cmd)*8));
+BUILD_ASSERT(EC_PCHG_UPDATE_CMD_COUNT <
+	     BIT(sizeof(((struct ec_params_pchg_update *)0)->cmd) * 8));
 
 struct ec_response_pchg_update {
 	/* Block size */
 	uint32_t block_size;
 } __ec_align4;
 
-
 #define EC_CMD_DISPLAY_SOC 0x0137
 
 struct ec_response_display_soc {
-	int16_t display_soc;  /* Display charge in 10ths of a % (1000=100.0%) */
-	int16_t full_factor;  /* Full factor in 10ths of a % (1000=100.0%) */
-	int16_t shutdown_soc; /* Shutdown SoC in 10ths of a % (1000=100.0%) */
+	/* Display charge in 10ths of a % (1000=100.0%) */
+	int16_t display_soc;
+	/* Full factor in 10ths of a % (1000=100.0%) */
+	int16_t full_factor;
+	/* Shutdown SoC in 10ths of a % (1000=100.0%) */
+	int16_t shutdown_soc;
 } __ec_align2;
 
-
 #define EC_CMD_SET_BASE_STATE 0x0138
 
 struct ec_params_set_base_state {
-	uint8_t cmd;  /* enum ec_set_base_state_cmd */
+	uint8_t cmd; /* enum ec_set_base_state_cmd */
 } __ec_align1;
 
 enum ec_set_base_state_cmd {
@@ -7121,8 +7210,8 @@ enum ec_i2c_control_command {
 #define EC_I2C_CONTROL_SPEED_UNKNOWN 0
 
 struct ec_params_i2c_control {
-	uint8_t port;		/* I2C port number */
-	uint8_t cmd;		/* enum ec_i2c_control_command */
+	uint8_t port; /* I2C port number */
+	uint8_t cmd; /* enum ec_i2c_control_command */
 	union {
 		uint16_t speed_khz;
 	} cmd_params;
@@ -7134,12 +7223,12 @@ struct ec_response_i2c_control {
 	} cmd_response;
 } __ec_align_size1;
 
-#define EC_CMD_RGBKBD_SET_COLOR	0x013A
-#define EC_CMD_RGBKBD		0x013B
+#define EC_CMD_RGBKBD_SET_COLOR 0x013A
+#define EC_CMD_RGBKBD 0x013B
 
-#define EC_RGBKBD_MAX_KEY_COUNT		128
-#define EC_RGBKBD_MAX_RGB_COLOR		0xFFFFFF
-#define EC_RGBKBD_MAX_SCALE		0xFF
+#define EC_RGBKBD_MAX_KEY_COUNT 128
+#define EC_RGBKBD_MAX_RGB_COLOR 0xFFFFFF
+#define EC_RGBKBD_MAX_SCALE 0xFF
 
 enum rgbkbd_state {
 	/* RGB keyboard is reset and not initialized. */
@@ -7159,6 +7248,7 @@ enum ec_rgbkbd_subcmd {
 	EC_RGBKBD_SUBCMD_CLEAR = 1,
 	EC_RGBKBD_SUBCMD_DEMO = 2,
 	EC_RGBKBD_SUBCMD_SET_SCALE = 3,
+	EC_RGBKBD_SUBCMD_GET_CONFIG = 4,
 	EC_RGBKBD_SUBCMD_COUNT
 };
 
@@ -7171,20 +7261,37 @@ enum ec_rgbkbd_demo {
 
 BUILD_ASSERT(EC_RGBKBD_DEMO_COUNT <= 255);
 
+enum ec_rgbkbd_type {
+	EC_RGBKBD_TYPE_UNKNOWN = 0,
+	EC_RGBKBD_TYPE_PER_KEY = 1, /* e.g. Vell */
+	EC_RGBKBD_TYPE_FOUR_ZONES_40_LEDS = 2, /* e.g. Taniks */
+	EC_RGBKBD_TYPE_FOUR_ZONES_12_LEDS = 3, /* e.g. Osiris */
+	EC_RGBKBD_TYPE_FOUR_ZONES_4_LEDS = 4, /* e.g. Mithrax */
+	EC_RGBKBD_TYPE_COUNT,
+};
+
 struct ec_rgbkbd_set_scale {
 	uint8_t key;
 	struct rgb_s scale;
 };
 
 struct ec_params_rgbkbd {
-	uint8_t subcmd;         /* Sub-command (enum ec_rgbkbd_subcmd) */
+	uint8_t subcmd; /* Sub-command (enum ec_rgbkbd_subcmd) */
 	union {
-		struct rgb_s color;	/* EC_RGBKBD_SUBCMD_CLEAR */
-		uint8_t demo;		/* EC_RGBKBD_SUBCMD_DEMO */
+		struct rgb_s color; /* EC_RGBKBD_SUBCMD_CLEAR */
+		uint8_t demo; /* EC_RGBKBD_SUBCMD_DEMO */
 		struct ec_rgbkbd_set_scale set_scale;
 	};
 } __ec_align1;
 
+struct ec_response_rgbkbd {
+	/*
+	 * RGBKBD type supported by the device.
+	 */
+
+	uint8_t rgbkbd_type; /* enum ec_rgbkbd_type */
+} __ec_align1;
+
 struct ec_params_rgbkbd_set_color {
 	/* Specifies the starting key ID whose color is being changed. */
 	uint8_t start_key;
@@ -7213,49 +7320,44 @@ struct ec_params_rgbkbd_set_color {
 #define EC_FP_FLAG_NOT_COMPLETE 0x1
 
 struct ec_params_fp_passthru {
-	uint16_t len;		/* Number of bytes to write then read */
-	uint16_t flags;		/* EC_FP_FLAG_xxx */
-	uint8_t data[];		/* Data to send */
+	uint16_t len; /* Number of bytes to write then read */
+	uint16_t flags; /* EC_FP_FLAG_xxx */
+	uint8_t data[]; /* Data to send */
 } __ec_align2;
 
 /* Configure the Fingerprint MCU behavior */
 #define EC_CMD_FP_MODE 0x0402
 
 /* Put the sensor in its lowest power mode */
-#define FP_MODE_DEEPSLEEP      BIT(0)
+#define FP_MODE_DEEPSLEEP BIT(0)
 /* Wait to see a finger on the sensor */
-#define FP_MODE_FINGER_DOWN    BIT(1)
+#define FP_MODE_FINGER_DOWN BIT(1)
 /* Poll until the finger has left the sensor */
-#define FP_MODE_FINGER_UP      BIT(2)
+#define FP_MODE_FINGER_UP BIT(2)
 /* Capture the current finger image */
-#define FP_MODE_CAPTURE        BIT(3)
+#define FP_MODE_CAPTURE BIT(3)
 /* Finger enrollment session on-going */
 #define FP_MODE_ENROLL_SESSION BIT(4)
 /* Enroll the current finger image */
-#define FP_MODE_ENROLL_IMAGE   BIT(5)
+#define FP_MODE_ENROLL_IMAGE BIT(5)
 /* Try to match the current finger image */
-#define FP_MODE_MATCH          BIT(6)
+#define FP_MODE_MATCH BIT(6)
 /* Reset and re-initialize the sensor. */
-#define FP_MODE_RESET_SENSOR   BIT(7)
+#define FP_MODE_RESET_SENSOR BIT(7)
 /* Sensor maintenance for dead pixels. */
 #define FP_MODE_SENSOR_MAINTENANCE BIT(8)
 /* special value: don't change anything just read back current mode */
-#define FP_MODE_DONT_CHANGE    BIT(31)
-
-#define FP_VALID_MODES (FP_MODE_DEEPSLEEP      | \
-			FP_MODE_FINGER_DOWN    | \
-			FP_MODE_FINGER_UP      | \
-			FP_MODE_CAPTURE        | \
-			FP_MODE_ENROLL_SESSION | \
-			FP_MODE_ENROLL_IMAGE   | \
-			FP_MODE_MATCH          | \
-			FP_MODE_RESET_SENSOR   | \
-			FP_MODE_SENSOR_MAINTENANCE | \
-			FP_MODE_DONT_CHANGE)
+#define FP_MODE_DONT_CHANGE BIT(31)
+
+#define FP_VALID_MODES                                                       \
+	(FP_MODE_DEEPSLEEP | FP_MODE_FINGER_DOWN | FP_MODE_FINGER_UP |       \
+	 FP_MODE_CAPTURE | FP_MODE_ENROLL_SESSION | FP_MODE_ENROLL_IMAGE |   \
+	 FP_MODE_MATCH | FP_MODE_RESET_SENSOR | FP_MODE_SENSOR_MAINTENANCE | \
+	 FP_MODE_DONT_CHANGE)
 
 /* Capture types defined in bits [30..28] */
 #define FP_MODE_CAPTURE_TYPE_SHIFT 28
-#define FP_MODE_CAPTURE_TYPE_MASK  (0x7 << FP_MODE_CAPTURE_TYPE_SHIFT)
+#define FP_MODE_CAPTURE_TYPE_MASK (0x7 << FP_MODE_CAPTURE_TYPE_SHIFT)
 /**
  * enum fp_capture_type - Specifies the "mode" when capturing images.
  *
@@ -7282,8 +7384,8 @@ enum fp_capture_type {
 	FP_CAPTURE_TYPE_MAX,
 };
 /* Extracts the capture type from the sensor 'mode' word */
-#define FP_CAPTURE_TYPE(mode) (((mode) & FP_MODE_CAPTURE_TYPE_MASK) \
-				       >> FP_MODE_CAPTURE_TYPE_SHIFT)
+#define FP_CAPTURE_TYPE(mode) \
+	(((mode)&FP_MODE_CAPTURE_TYPE_MASK) >> FP_MODE_CAPTURE_TYPE_SHIFT)
 
 struct ec_params_fp_mode {
 	uint32_t mode; /* as defined by FP_MODE_ constants */
@@ -7297,15 +7399,15 @@ struct ec_response_fp_mode {
 #define EC_CMD_FP_INFO 0x0403
 
 /* Number of dead pixels detected on the last maintenance */
-#define FP_ERROR_DEAD_PIXELS(errors) ((errors) & 0x3FF)
+#define FP_ERROR_DEAD_PIXELS(errors) ((errors)&0x3FF)
 /* Unknown number of dead pixels detected on the last maintenance */
 #define FP_ERROR_DEAD_PIXELS_UNKNOWN (0x3FF)
 /* No interrupt from the sensor */
-#define FP_ERROR_NO_IRQ    BIT(12)
+#define FP_ERROR_NO_IRQ BIT(12)
 /* SPI communication error */
-#define FP_ERROR_SPI_COMM  BIT(13)
+#define FP_ERROR_SPI_COMM BIT(13)
 /* Invalid sensor Hardware ID */
-#define FP_ERROR_BAD_HWID  BIT(14)
+#define FP_ERROR_BAD_HWID BIT(14)
 /* Sensor initialization failed */
 #define FP_ERROR_INIT_FAIL BIT(15)
 
@@ -7338,8 +7440,8 @@ struct ec_response_fp_info {
 	uint16_t bpp;
 	uint16_t errors; /* see FP_ERROR_ flags above */
 	/* Template/finger current information */
-	uint32_t template_size;  /* max template size in bytes */
-	uint16_t template_max;   /* maximum number of fingers/templates */
+	uint32_t template_size; /* max template size in bytes */
+	uint16_t template_max; /* maximum number of fingers/templates */
 	uint16_t template_valid; /* number of valid fingers/templates */
 	uint32_t template_dirty; /* bitmap of templates with MCU side changes */
 	uint32_t template_version; /* version of the template format */
@@ -7349,13 +7451,13 @@ struct ec_response_fp_info {
 #define EC_CMD_FP_FRAME 0x0404
 
 /* constants defining the 'offset' field which also contains the frame index */
-#define FP_FRAME_INDEX_SHIFT       28
+#define FP_FRAME_INDEX_SHIFT 28
 /* Frame buffer where the captured image is stored */
-#define FP_FRAME_INDEX_RAW_IMAGE    0
+#define FP_FRAME_INDEX_RAW_IMAGE 0
 /* First frame buffer holding a template */
-#define FP_FRAME_INDEX_TEMPLATE     1
+#define FP_FRAME_INDEX_TEMPLATE 1
 #define FP_FRAME_GET_BUFFER_INDEX(offset) ((offset) >> FP_FRAME_INDEX_SHIFT)
-#define FP_FRAME_OFFSET_MASK       0x0FFFFFFF
+#define FP_FRAME_OFFSET_MASK 0x0FFFFFFF
 
 /* Version of the format of the encrypted templates. */
 #define FP_TEMPLATE_FORMAT_VERSION 4
@@ -7422,14 +7524,14 @@ enum fp_context_action {
 
 /* Version 1 of the command is "asynchronous". */
 struct ec_params_fp_context_v1 {
-	uint8_t action;		/**< enum fp_context_action */
-	uint8_t reserved[3];    /**< padding for alignment */
+	uint8_t action; /**< enum fp_context_action */
+	uint8_t reserved[3]; /**< padding for alignment */
 	uint32_t userid[FP_CONTEXT_USERID_WORDS];
 } __ec_align4;
 
 #define EC_CMD_FP_STATS 0x0407
 
-#define FPSTATS_CAPTURE_INV  BIT(0)
+#define FPSTATS_CAPTURE_INV BIT(0)
 #define FPSTATS_MATCHING_INV BIT(1)
 
 struct ec_response_fp_stats {
@@ -7699,14 +7801,14 @@ struct ec_params_usb_pd_mux_ack {
  * switch to the new names soon, as the old names may not be carried forward
  * forever.
  */
-#define EC_HOST_PARAM_SIZE      EC_PROTO2_MAX_PARAM_SIZE
-#define EC_LPC_ADDR_OLD_PARAM   EC_HOST_CMD_REGION1
-#define EC_OLD_PARAM_SIZE       EC_HOST_CMD_REGION_SIZE
+#define EC_HOST_PARAM_SIZE EC_PROTO2_MAX_PARAM_SIZE
+#define EC_LPC_ADDR_OLD_PARAM EC_HOST_CMD_REGION1
+#define EC_OLD_PARAM_SIZE EC_HOST_CMD_REGION_SIZE
 
-#endif  /* !__ACPI__ */
+#endif /* !__ACPI__ */
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif  /* __CROS_EC_EC_COMMANDS_H */
+#endif /* __CROS_EC_EC_COMMANDS_H */
diff --git a/include/ec_ec_comm_client.h b/include/ec_ec_comm_client.h
index 9a60daffe4..9b506dd402 100644
--- a/include/ec_ec_comm_client.h
+++ b/include/ec_ec_comm_client.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -42,8 +42,7 @@ int ec_ec_client_base_get_static_info(void);
  * @return EC_RES_SUCCESS on success, EC_RES_ERROR on communication error,
  * else forwards the error code from the server.
  */
-int ec_ec_client_base_charge_control(int max_current,
-				     int otg_voltage,
+int ec_ec_client_base_charge_control(int max_current, int otg_voltage,
 				     int allow_charging);
 
 /**
diff --git a/include/ec_ec_comm_server.h b/include/ec_ec_comm_server.h
index 1ed5588666..0eb094fea3 100644
--- a/include/ec_ec_comm_server.h
+++ b/include/ec_ec_comm_server.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/include/eeprom.h b/include/eeprom.h
index 368491c959..41e464c1f5 100644
--- a/include/eeprom.h
+++ b/include/eeprom.h
@@ -1,4 +1,4 @@
-/* Copyright 2011 The Chromium OS Authors. All rights reserved.
+/* Copyright 2011 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -52,4 +52,4 @@ int eeprom_write(int block, int offset, int size, const char *data);
  */
 int eeprom_hide(int block);
 
-#endif  /* __CROS_EC_EEPROM_H */
+#endif /* __CROS_EC_EEPROM_H */
diff --git a/include/espi.h b/include/espi.h
index a717e7e414..4768d8f12f 100644
--- a/include/espi.h
+++ b/include/espi.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,29 +14,29 @@
 enum espi_vw_signal {
 	/* The first valid VW signal is 0x2000 */
 	VW_SIGNAL_START = IOEX_LIMIT + 1,
-	VW_SLP_S3_L = VW_SIGNAL_START,	/* index 02h (In)  */
+	VW_SLP_S3_L = VW_SIGNAL_START, /* index 02h (In)  */
 	VW_SLP_S4_L,
 	VW_SLP_S5_L,
-	VW_SUS_STAT_L,			/* index 03h (In)  */
+	VW_SUS_STAT_L, /* index 03h (In)  */
 	VW_PLTRST_L,
 	VW_OOB_RST_WARN,
-	VW_OOB_RST_ACK,			/* index 04h (Out) */
+	VW_OOB_RST_ACK, /* index 04h (Out) */
 	VW_WAKE_L,
 	VW_PME_L,
-	VW_ERROR_FATAL,			/* index 05h (Out) */
+	VW_ERROR_FATAL, /* index 05h (Out) */
 	VW_ERROR_NON_FATAL,
 	/* Merge bit 3/0 into one signal. Need to set them simultaneously */
 	VW_PERIPHERAL_BTLD_STATUS_DONE,
-	VW_SCI_L,			/* index 06h (Out) */
+	VW_SCI_L, /* index 06h (Out) */
 	VW_SMI_L,
 	VW_RCIN_L,
 	VW_HOST_RST_ACK,
-	VW_HOST_RST_WARN,		/* index 07h (In)  */
-	VW_SUS_ACK,			/* index 40h (Out) */
-	VW_SUS_WARN_L,			/* index 41h (In)  */
+	VW_HOST_RST_WARN, /* index 07h (In)  */
+	VW_SUS_ACK, /* index 40h (Out) */
+	VW_SUS_WARN_L, /* index 41h (In)  */
 	VW_SUS_PWRDN_ACK_L,
 	VW_SLP_A_L,
-	VW_SLP_LAN,                     /* index 42h (In)  */
+	VW_SLP_LAN, /* index 42h (In)  */
 	VW_SLP_WLAN,
 	VW_SIGNAL_END,
 	VW_LIMIT = 0x2FFF
@@ -99,6 +99,6 @@ int espi_signal_is_vw(int signal);
  * @param timeout max time in microseconds to poll.
  */
 void espi_wait_vw_not_dirty(enum espi_vw_signal signal,
-	unsigned int timeout_us);
+			    unsigned int timeout_us);
 
-#endif  /* __CROS_EC_ESPI_H */
+#endif /* __CROS_EC_ESPI_H */
diff --git a/include/event_log.h b/include/event_log.h
index 45b10a3a2d..bd3b88510b 100644
--- a/include/event_log.h
+++ b/include/event_log.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,14 +8,14 @@
 
 struct event_log_entry {
 	uint32_t timestamp; /* relative timestamp in milliseconds */
-	uint8_t type;       /* event type, caller-defined */
-	uint8_t size;       /* [7:5] caller-def'd [4:0] payload size in bytes */
-	uint16_t data;      /* type-defined data payload */
+	uint8_t type; /* event type, caller-defined */
+	uint8_t size; /* [7:5] caller-def'd [4:0] payload size in bytes */
+	uint16_t data; /* type-defined data payload */
 	uint8_t payload[0]; /* optional additional data payload: 0..16 bytes */
 } __packed;
 
-#define EVENT_LOG_SIZE_MASK  0x1f
-#define EVENT_LOG_SIZE(size) ((size) & EVENT_LOG_SIZE_MASK)
+#define EVENT_LOG_SIZE_MASK 0x1f
+#define EVENT_LOG_SIZE(size) ((size)&EVENT_LOG_SIZE_MASK)
 
 /* The timestamp is the microsecond counter shifted to get about a ms. */
 #define EVENT_LOG_TIMESTAMP_SHIFT 10 /* 1 LSB = 1024us */
@@ -23,8 +23,8 @@ struct event_log_entry {
 #define EVENT_LOG_NO_ENTRY 0xff
 
 /* Add an entry to the event log. */
-void log_add_event(uint8_t type, uint8_t size, uint16_t data,
-		   void *payload, uint32_t timestamp);
+void log_add_event(uint8_t type, uint8_t size, uint16_t data, void *payload,
+		   uint32_t timestamp);
 
 /*
  * Remove and return an entry from the event log, if available.
diff --git a/include/extpower.h b/include/extpower.h
index 1e9f7976e6..08bec3f0bc 100644
--- a/include/extpower.h
+++ b/include/extpower.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,7 +10,7 @@
 
 #include "common.h"
 
-enum gpio_signal;	/* from gpio_signal.h */
+enum gpio_signal; /* from gpio_signal.h */
 
 /**
  * Run board specific code to update extpower status.  The default
@@ -21,7 +21,7 @@ __override_proto void board_check_extpower(void);
 /**
  * Return non-zero if external power is present.
  */
-int extpower_is_present(void);
+test_mockable int extpower_is_present(void);
 
 /**
  * Interrupt handler for external power GPIOs.
@@ -37,4 +37,4 @@ void extpower_interrupt(enum gpio_signal signal);
  */
 void extpower_handle_update(int is_present);
 
-#endif  /* __CROS_EC_EXTPOWER_H */
+#endif /* __CROS_EC_EXTPOWER_H */
diff --git a/include/fan.h b/include/fan.h
index 87c8f4b7a6..946d0607c9 100644
--- a/include/fan.h
+++ b/include/fan.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,7 +17,7 @@ enum fan_channel {
 #if DT_NODE_EXISTS(DT_INST(0, cros_ec_fans))
 	DT_FOREACH_CHILD(DT_INST(0, cros_ec_fans), NODE_ID_AND_COMMA)
 #endif /* cros_ec_fans */
-	FAN_CH_COUNT
+		FAN_CH_COUNT
 };
 
 BUILD_ASSERT(FAN_CH_COUNT == CONFIG_PLATFORM_EC_NUM_FANS);
@@ -50,7 +50,7 @@ struct fan_t {
 
 /* Values for .flags field */
 /*   Enable automatic RPM control using tach input */
-#define FAN_USE_RPM_MODE   BIT(0)
+#define FAN_USE_RPM_MODE BIT(0)
 /*   Require a higher duty cycle to start up than to keep running */
 #define FAN_USE_FAST_START BIT(1)
 
@@ -62,7 +62,7 @@ extern const struct fan_t fans[];
 #endif
 
 /* For convenience */
-#define FAN_CH(fan)	fans[fan].conf->ch
+#define FAN_CH(fan) fans[fan].conf->ch
 
 /**
  * Set the amount of active cooling needed. The thermal control task will call
@@ -84,7 +84,6 @@ void fan_set_percent_needed(int fan, int pct);
  */
 int fan_percent_to_rpm(int fan, int pct);
 
-
 /**
  * These functions require chip-specific implementations.
  */
@@ -143,4 +142,4 @@ void fan_set_count(int count);
 
 int is_thermal_control_enabled(int idx);
 
-#endif  /* __CROS_EC_FAN_H */
+#endif /* __CROS_EC_FAN_H */
diff --git a/include/flash.h b/include/flash.h
index 240ab0369b..5df6afdb09 100644
--- a/include/flash.h
+++ b/include/flash.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,11 +9,11 @@
 #define __CROS_EC_FLASH_H
 
 #include "common.h"
-#include "ec_commands.h"  /* For EC_FLASH_PROTECT_* flags */
+#include "ec_commands.h" /* For EC_FLASH_PROTECT_* flags */
 
 #ifdef CONFIG_FLASH_MULTIPLE_REGION
-extern struct ec_flash_bank const flash_bank_array[
-	CONFIG_FLASH_REGION_TYPE_COUNT];
+extern struct ec_flash_bank const
+	flash_bank_array[CONFIG_FLASH_REGION_TYPE_COUNT];
 
 /*
  * Return the bank the offset is in.
@@ -51,25 +51,25 @@ int crec_flash_bank_start_offset(int bank);
 int crec_flash_bank_erase_size(int bank);
 
 /* Number of physical flash banks */
-#define PHYSICAL_BANKS  CONFIG_FLASH_MULTIPLE_REGION
+#define PHYSICAL_BANKS CONFIG_FLASH_MULTIPLE_REGION
 
 /* WP region offset and size in units of flash banks */
-#define WP_BANK_OFFSET	crec_flash_bank_index(CONFIG_WP_STORAGE_OFF)
+#define WP_BANK_OFFSET crec_flash_bank_index(CONFIG_WP_STORAGE_OFF)
 #define WP_BANK_COUNT \
 	(crec_flash_bank_count(CONFIG_WP_STORAGE_OFF, CONFIG_WP_STORAGE_SIZE))
 
-#else  /* CONFIG_FLASH_MULTIPLE_REGION */
+#else /* CONFIG_FLASH_MULTIPLE_REGION */
 /* Number of physical flash banks */
 #ifndef PHYSICAL_BANKS
 #define PHYSICAL_BANKS (CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE)
 #endif
 
 /* WP region offset and size in units of flash banks */
-#define WP_BANK_OFFSET	(CONFIG_WP_STORAGE_OFF / CONFIG_FLASH_BANK_SIZE)
+#define WP_BANK_OFFSET (CONFIG_WP_STORAGE_OFF / CONFIG_FLASH_BANK_SIZE)
 #ifndef WP_BANK_COUNT
-#define WP_BANK_COUNT	(CONFIG_WP_STORAGE_SIZE / CONFIG_FLASH_BANK_SIZE)
+#define WP_BANK_COUNT (CONFIG_WP_STORAGE_SIZE / CONFIG_FLASH_BANK_SIZE)
 #endif
-#endif  /* CONFIG_FLASH_MULTIPLE_REGION */
+#endif /* CONFIG_FLASH_MULTIPLE_REGION */
 
 /* Persistent protection state flash offset / size / bank */
 #if defined(CONFIG_FLASH_PSTATE) && defined(CONFIG_FLASH_PSTATE_BANK)
@@ -82,33 +82,33 @@ int crec_flash_bank_erase_size(int bank);
  * When there is a dedicated flash bank used to store persistent state,
  * ensure the RO flash region excludes the PSTATE bank.
  */
-#define EC_FLASH_REGION_RO_SIZE		CONFIG_RO_SIZE
+#define EC_FLASH_REGION_RO_SIZE CONFIG_RO_SIZE
 
 #ifndef PSTATE_BANK
-#define PSTATE_BANK	    (CONFIG_FW_PSTATE_OFF / CONFIG_FLASH_BANK_SIZE)
+#define PSTATE_BANK (CONFIG_FW_PSTATE_OFF / CONFIG_FLASH_BANK_SIZE)
 #endif
 #ifndef PSTATE_BANK_COUNT
-#define PSTATE_BANK_COUNT   (CONFIG_FW_PSTATE_SIZE / CONFIG_FLASH_BANK_SIZE)
+#define PSTATE_BANK_COUNT (CONFIG_FW_PSTATE_SIZE / CONFIG_FLASH_BANK_SIZE)
 #endif
-#else   /* CONFIG_FLASH_PSTATE && CONFIG_FLASH_PSTATE_BANK */
+#else /* CONFIG_FLASH_PSTATE && CONFIG_FLASH_PSTATE_BANK */
 /* Allow flashrom to program the entire write protected area */
-#define EC_FLASH_REGION_RO_SIZE		CONFIG_WP_STORAGE_SIZE
-#define PSTATE_BANK_COUNT		0
-#endif  /* CONFIG_FLASH_PSTATE && CONFIG_FLASH_PSTATE_BANK */
+#define EC_FLASH_REGION_RO_SIZE CONFIG_WP_STORAGE_SIZE
+#define PSTATE_BANK_COUNT 0
+#endif /* CONFIG_FLASH_PSTATE && CONFIG_FLASH_PSTATE_BANK */
 
 #ifdef CONFIG_ROLLBACK
 /*
  * ROLLBACK region offset and size in units of flash banks.
  */
 #ifdef CONFIG_FLASH_MULTIPLE_REGION
-#define ROLLBACK_BANK_OFFSET	crec_flash_bank_index(CONFIG_ROLLBACK_OFF)
-#define ROLLBACK_BANK_COUNT	\
+#define ROLLBACK_BANK_OFFSET crec_flash_bank_index(CONFIG_ROLLBACK_OFF)
+#define ROLLBACK_BANK_COUNT \
 	crec_flash_bank_count(CONFIG_ROLLBACK_OFF, CONFIG_ROLLBACK_SIZE)
 #else
-#define ROLLBACK_BANK_OFFSET	(CONFIG_ROLLBACK_OFF / CONFIG_FLASH_BANK_SIZE)
-#define ROLLBACK_BANK_COUNT	(CONFIG_ROLLBACK_SIZE / CONFIG_FLASH_BANK_SIZE)
-#endif	/* CONFIG_FLASH_MULTIPLE_REGION */
-#endif	/* CONFIG_ROLLBACK */
+#define ROLLBACK_BANK_OFFSET (CONFIG_ROLLBACK_OFF / CONFIG_FLASH_BANK_SIZE)
+#define ROLLBACK_BANK_COUNT (CONFIG_ROLLBACK_SIZE / CONFIG_FLASH_BANK_SIZE)
+#endif /* CONFIG_FLASH_MULTIPLE_REGION */
+#endif /* CONFIG_ROLLBACK */
 
 /* This enum is useful to identify different regions during verification. */
 enum flash_region {
@@ -378,7 +378,7 @@ int crec_flash_write_pstate_mac_addr(const char *mac_addr);
 #ifdef CONFIG_EXTERNAL_STORAGE
 void crec_flash_lock_mapped_storage(int lock);
 #else
-static inline void crec_flash_lock_mapped_storage(int lock) { };
+static inline void crec_flash_lock_mapped_storage(int lock){};
 #endif /* CONFIG_EXTERNAL_STORAGE */
 
 /**
@@ -390,4 +390,4 @@ static inline void crec_flash_lock_mapped_storage(int lock) { };
  */
 int crec_board_flash_select(int select);
 
-#endif  /* __CROS_EC_FLASH_H */
+#endif /* __CROS_EC_FLASH_H */
diff --git a/include/flash_log.h b/include/flash_log.h
index e504df6ee7..7141a8b67a 100644
--- a/include/flash_log.h
+++ b/include/flash_log.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,10 +16,10 @@ enum flash_event_type {
 	FE_LOG_CORRUPTED = 1,
 	FE_TPM_I2C_ERROR = 2,
 	FE_LOG_OVERFLOWS = 3, /* A single byte, overflow counter. */
-	FE_LOG_LOCKS = 4,     /* A single byte, lock failures counter. */
-	FE_LOG_NVMEM = 5,     /* NVMEM failure, variable structure. */
-	FE_LOG_TPM_WIPE_ERROR = 6,     /* Failed to wipe the TPM */
-	FE_LOG_TRNG_STALL = 7,     /* Stall while retrieving a random number. */
+	FE_LOG_LOCKS = 4, /* A single byte, lock failures counter. */
+	FE_LOG_NVMEM = 5, /* NVMEM failure, variable structure. */
+	FE_LOG_TPM_WIPE_ERROR = 6, /* Failed to wipe the TPM */
+	FE_LOG_TRNG_STALL = 7, /* Stall while retrieving a random number. */
 	FE_LOG_DCRYPTO_FAILURE = 8, /* Dcrypto had to be reset. */
 
 	/*
@@ -92,9 +92,9 @@ struct nvmem_failure_payload {
 
 #define FLASH_LOG_PAYLOAD_SIZE(size) ((size)&FLASH_LOG_PAYLOAD_SIZE_MASK)
 /* Size of log entry for a specific payload size. */
-#define FLASH_LOG_ENTRY_SIZE(payload_sz)                                       \
-	((FLASH_LOG_PAYLOAD_SIZE(payload_sz) +                                 \
-	  sizeof(struct flash_log_entry) + CONFIG_FLASH_WRITE_SIZE - 1) &      \
+#define FLASH_LOG_ENTRY_SIZE(payload_sz)                                  \
+	((FLASH_LOG_PAYLOAD_SIZE(payload_sz) +                            \
+	  sizeof(struct flash_log_entry) + CONFIG_FLASH_WRITE_SIZE - 1) & \
 	 ~(CONFIG_FLASH_WRITE_SIZE - 1))
 
 /*
diff --git a/include/fpsensor.h b/include/fpsensor.h
index 8efc4a7006..3963df86a7 100644
--- a/include/fpsensor.h
+++ b/include/fpsensor.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,8 +17,9 @@
 #endif
 
 /*  Four-character-code */
-#define FOURCC(a, b, c, d) ((uint32_t)(a) | ((uint32_t)(b) << 8) | \
-			   ((uint32_t)(c) << 16) | ((uint32_t)(d) << 24))
+#define FOURCC(a, b, c, d)                                              \
+	((uint32_t)(a) | ((uint32_t)(b) << 8) | ((uint32_t)(c) << 16) | \
+	 ((uint32_t)(d) << 24))
 
 /* 8-bit greyscale pixel format as defined by V4L2 headers */
 #define V4L2_PIX_FMT_GREY FOURCC('G', 'R', 'E', 'Y')
diff --git a/include/fpsensor_crypto.h b/include/fpsensor_crypto.h
index b6252b3fd2..7dff9238fa 100644
--- a/include/fpsensor_crypto.h
+++ b/include/fpsensor_crypto.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -67,11 +67,9 @@ int derive_positive_match_secret(uint8_t *output,
  * @param tag_size the size of |tag|.
  * @return EC_SUCCESS on success and error code otherwise.
  */
-int aes_gcm_encrypt(const uint8_t *key, int key_size,
-		    const uint8_t *plaintext,
-		    uint8_t *ciphertext, int text_size,
-		    const uint8_t *nonce, int nonce_size,
-		    uint8_t *tag, int tag_size);
+int aes_gcm_encrypt(const uint8_t *key, int key_size, const uint8_t *plaintext,
+		    uint8_t *ciphertext, int text_size, const uint8_t *nonce,
+		    int nonce_size, uint8_t *tag, int tag_size);
 
 /**
  * Decrypt |plaintext| using AES-GCM128.
@@ -89,7 +87,7 @@ int aes_gcm_encrypt(const uint8_t *key, int key_size,
  */
 int aes_gcm_decrypt(const uint8_t *key, int key_size, uint8_t *plaintext,
 		    const uint8_t *ciphertext, int text_size,
-		    const uint8_t *nonce, int nonce_size,
-		    const uint8_t *tag, int tag_size);
+		    const uint8_t *nonce, int nonce_size, const uint8_t *tag,
+		    int tag_size);
 
 #endif /* __CROS_EC_FPSENSOR_CRYPTO_H */
diff --git a/include/fpsensor_detect.h b/include/fpsensor_detect.h
index 56e04d4ae6..e542223954 100644
--- a/include/fpsensor_detect.h
+++ b/include/fpsensor_detect.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/fpsensor_state.h b/include/fpsensor_state.h
index 98d5b63783..ce454233fa 100644
--- a/include/fpsensor_state.h
+++ b/include/fpsensor_state.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -28,14 +28,13 @@
 #endif
 
 #define SBP_ENC_KEY_LEN 16
-#define FP_ALGORITHM_ENCRYPTED_TEMPLATE_SIZE \
-	(FP_ALGORITHM_TEMPLATE_SIZE + \
-		FP_POSITIVE_MATCH_SALT_BYTES + \
-		sizeof(struct ec_fp_template_encryption_metadata))
+#define FP_ALGORITHM_ENCRYPTED_TEMPLATE_SIZE                         \
+	(FP_ALGORITHM_TEMPLATE_SIZE + FP_POSITIVE_MATCH_SALT_BYTES + \
+	 sizeof(struct ec_fp_template_encryption_metadata))
 
 /* Events for the FPSENSOR task */
-#define TASK_EVENT_SENSOR_IRQ     TASK_EVENT_CUSTOM_BIT(0)
-#define TASK_EVENT_UPDATE_CONFIG  TASK_EVENT_CUSTOM_BIT(1)
+#define TASK_EVENT_SENSOR_IRQ TASK_EVENT_CUSTOM_BIT(0)
+#define TASK_EVENT_UPDATE_CONFIG TASK_EVENT_CUSTOM_BIT(1)
 
 #define FP_NO_SUCH_TEMPLATE -1
 
@@ -53,8 +52,8 @@ extern uint8_t fp_template[FP_MAX_FINGER_COUNT][FP_ALGORITHM_TEMPLATE_SIZE];
  */
 extern uint8_t fp_enc_buffer[FP_ALGORITHM_ENCRYPTED_TEMPLATE_SIZE];
 /* Salt used in derivation of positive match secret. */
-extern uint8_t fp_positive_match_salt
-	[FP_MAX_FINGER_COUNT][FP_POSITIVE_MATCH_SALT_BYTES];
+extern uint8_t fp_positive_match_salt[FP_MAX_FINGER_COUNT]
+				     [FP_POSITIVE_MATCH_SALT_BYTES];
 /* Index of the last enrolled but not retrieved template. */
 extern int8_t template_newly_enrolled;
 /* Number of used templates */
@@ -118,7 +117,7 @@ int fp_tpm_seed_is_set(void);
  * @param mode_output   resulting mode
  * @return EC_RES_SUCCESS on success. Error code on failure.
  */
-int fp_set_sensor_mode(uint32_t mode, uint32_t *mode_output);
+enum ec_status fp_set_sensor_mode(uint32_t mode, uint32_t *mode_output);
 
 /**
  * Allow reading positive match secret for |fgr| in the next 5 seconds.
@@ -128,14 +127,13 @@ int fp_set_sensor_mode(uint32_t mode, uint32_t *mode_output);
  * @return EC_SUCCESS if the request is valid, error code otherwise.
  */
 int fp_enable_positive_match_secret(uint32_t fgr,
-	struct positive_match_secret_state *state);
+				    struct positive_match_secret_state *state);
 
 /**
  * Disallow positive match secret for any finger to be read.
  *
  * @param state the state of positive match secret, e.g. readable or not.
  */
-void fp_disable_positive_match_secret(
-	struct positive_match_secret_state *state);
+void fp_disable_positive_match_secret(struct positive_match_secret_state *state);
 
 #endif /* __CROS_EC_FPSENSOR_STATE_H */
diff --git a/include/gesture.h b/include/gesture.h
index bc0186887c..8744f3efcd 100644
--- a/include/gesture.h
+++ b/include/gesture.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/gpio.h b/include/gpio.h
index 4d827eb3cc..54464d1bfb 100644
--- a/include/gpio.h
+++ b/include/gpio.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -57,14 +57,14 @@
  * Map the legacy EC GPIO flags to the Zephyr equivalent.
  * Refer to the descriptions below.
  */
-#define GPIO_FLAG_NONE     GPIO_DISCONNECTED
+#define GPIO_FLAG_NONE GPIO_DISCONNECTED
 /* GPIO_ANALOG	           not supported by Zephyr */
 /* GPIO_OPEN_DRAIN         already defined by Zephyr */
 /* GPIO_DEFAULT            not supported by Zephyr */
 /* GPIO_PULL_UP            already defined by Zephyr */
 /* GPIO_PULL_DOWN          already defined by Zephyr */
-#define GPIO_LOW           GPIO_OUTPUT_INIT_LOW
-#define GPIO_HIGH          GPIO_OUTPUT_INIT_HIGH
+#define GPIO_LOW GPIO_OUTPUT_INIT_LOW
+#define GPIO_HIGH GPIO_OUTPUT_INIT_HIGH
 /* GPIO_INPUT              already defined by Zephyr */
 /* GPIO_OUTPUT             already defined by Zephyr */
 
@@ -72,14 +72,14 @@
  * One to one mapping of interrupt flags isn't possible. So map these
  * flags to not conflict with any Zephyr flags.
  */
-#define GPIO_INT_F_RISING  BIT(28)
+#define GPIO_INT_F_RISING BIT(28)
 #define GPIO_INT_F_FALLING BIT(29)
-#define GPIO_INT_F_LOW     BIT(30)
-#define GPIO_INT_F_HIGH    BIT(31)
+#define GPIO_INT_F_LOW BIT(30)
+#define GPIO_INT_F_HIGH BIT(31)
 /* GPIO_INT_DSLEEP         not supported by Zephyr */
 /* GPIO_INT_SHARED         not supported by Zephyr */
 
-#define GPIO_SEL_1P8V      GPIO_VOLTAGE_1P8
+#define GPIO_SEL_1P8V GPIO_VOLTAGE_1P8
 /* GPIO_ALTERNATE          not supported by Zephyr */
 /* GPIO_LOCKED             not supported by Zephyr */
 /* GPIO_HIB_WAKE_HIGH      not supported by Zephyr */
@@ -98,51 +98,52 @@
  *   GPIO_PULL_DOWN
  *   GPIO_PULL_ANALOG
  */
-#define GPIO_FLAG_NONE     0       /* No flag needed, default setting */
-#define GPIO_ANALOG        BIT(0)  /* Set pin to analog-mode */
-#define GPIO_OPEN_DRAIN    (BIT(1) | BIT(2))  /* Output type is open-drain  */
-#define GPIO_DEFAULT       BIT(3)  /* Don't set up on boot */
-#define GPIO_PULL_UP       BIT(4)  /* Enable on-chip pullup */
-#define GPIO_PULL_DOWN     BIT(5)  /* Enable on-chip pulldown */
-#define GPIO_LOW           BIT(6)  /* If GPIO_OUTPUT, set level low */
-#define GPIO_HIGH          BIT(7)  /* If GPIO_OUTPUT, set level high */
-#define GPIO_INPUT         BIT(8)  /* Input */
-#define GPIO_OUTPUT        BIT(9)  /* Output */
-#define GPIO_INT_F_RISING  BIT(10) /* Interrupt on rising edge */
+#define GPIO_FLAG_NONE 0 /* No flag needed, default setting */
+#define GPIO_ANALOG BIT(0) /* Set pin to analog-mode */
+#define GPIO_OPEN_DRAIN (BIT(1) | BIT(2)) /* Output type is open-drain  */
+#define GPIO_DEFAULT BIT(3) /* Don't set up on boot */
+#define GPIO_PULL_UP BIT(4) /* Enable on-chip pullup */
+#define GPIO_PULL_DOWN BIT(5) /* Enable on-chip pulldown */
+#define GPIO_LOW BIT(6) /* If GPIO_OUTPUT, set level low */
+#define GPIO_HIGH BIT(7) /* If GPIO_OUTPUT, set level high */
+#define GPIO_INPUT BIT(8) /* Input */
+#define GPIO_OUTPUT BIT(9) /* Output */
+#define GPIO_INT_F_RISING BIT(10) /* Interrupt on rising edge */
 #define GPIO_INT_F_FALLING BIT(11) /* Interrupt on falling edge */
-#define GPIO_INT_F_LOW     BIT(12) /* Interrupt on low level */
-#define GPIO_INT_F_HIGH    BIT(13) /* Interrupt on high level */
-#define GPIO_INT_DSLEEP    BIT(14) /* Interrupt in deep sleep */
-#define GPIO_INT_SHARED    BIT(15) /* Shared among multiple pins */
-#define GPIO_SEL_1P8V      BIT(16) /* Support 1.8v */
-#define GPIO_ALTERNATE     BIT(17) /* GPIO used for alternate function. */
-#define GPIO_LOCKED        BIT(18) /* Lock GPIO output and configuration */
-#define GPIO_HIB_WAKE_HIGH    BIT(19) /* Hibernate wake on high level */
-#define GPIO_HIB_WAKE_LOW     BIT(20) /* Hibernate wake on low level */
-#define GPIO_HIB_WAKE_RISING  BIT(21) /* Hibernate wake on rising edge */
+#define GPIO_INT_F_LOW BIT(12) /* Interrupt on low level */
+#define GPIO_INT_F_HIGH BIT(13) /* Interrupt on high level */
+#define GPIO_INT_DSLEEP BIT(14) /* Interrupt in deep sleep */
+#define GPIO_INT_SHARED BIT(15) /* Shared among multiple pins */
+#define GPIO_SEL_1P8V BIT(16) /* Support 1.8v */
+#define GPIO_ALTERNATE BIT(17) /* GPIO used for alternate function. */
+#define GPIO_LOCKED BIT(18) /* Lock GPIO output and configuration */
+#define GPIO_HIB_WAKE_HIGH BIT(19) /* Hibernate wake on high level */
+#define GPIO_HIB_WAKE_LOW BIT(20) /* Hibernate wake on low level */
+#define GPIO_HIB_WAKE_RISING BIT(21) /* Hibernate wake on rising edge */
 #define GPIO_HIB_WAKE_FALLING BIT(22) /* Hibernate wake on falling edge */
 #ifdef CONFIG_GPIO_POWER_DOWN
-#define GPIO_POWER_DOWN    BIT(23) /* Pin and pad is powered off */
+#define GPIO_POWER_DOWN BIT(23) /* Pin and pad is powered off */
 #endif
 
 #endif /* CONFIG_ZEPHYR */
 
 /* Common flag combinations */
-#define GPIO_OUT_LOW        (GPIO_OUTPUT | GPIO_LOW)
-#define GPIO_OUT_HIGH       (GPIO_OUTPUT | GPIO_HIGH)
-#define GPIO_ODR_HIGH       (GPIO_OUTPUT | GPIO_OPEN_DRAIN | GPIO_HIGH)
-#define GPIO_ODR_LOW        (GPIO_OUTPUT | GPIO_OPEN_DRAIN | GPIO_LOW)
-#define GPIO_INT_RISING     (GPIO_INPUT | GPIO_INT_F_RISING)
-#define GPIO_INT_FALLING    (GPIO_INPUT | GPIO_INT_F_FALLING)
+#define GPIO_OUT_LOW (GPIO_OUTPUT | GPIO_LOW)
+#define GPIO_OUT_HIGH (GPIO_OUTPUT | GPIO_HIGH)
+#define GPIO_ODR_HIGH (GPIO_OUTPUT | GPIO_OPEN_DRAIN | GPIO_HIGH)
+#define GPIO_ODR_LOW (GPIO_OUTPUT | GPIO_OPEN_DRAIN | GPIO_LOW)
+#define GPIO_INT_RISING (GPIO_INPUT | GPIO_INT_F_RISING)
+#define GPIO_INT_FALLING (GPIO_INPUT | GPIO_INT_F_FALLING)
 /* TODO(crosbug.com/p/24204): "EDGE" would have been clearer than "BOTH". */
-#define GPIO_INT_BOTH       (GPIO_INT_RISING | GPIO_INT_FALLING)
-#define GPIO_INT_LOW        (GPIO_INPUT | GPIO_INT_F_LOW)
-#define GPIO_INT_HIGH       (GPIO_INPUT | GPIO_INT_F_HIGH)
-#define GPIO_INT_LEVEL      (GPIO_INT_LOW | GPIO_INT_HIGH)
-#define GPIO_INT_ANY        (GPIO_INT_BOTH | GPIO_INT_LEVEL)
+#define GPIO_INT_BOTH (GPIO_INT_RISING | GPIO_INT_FALLING)
+#define GPIO_INT_LOW (GPIO_INPUT | GPIO_INT_F_LOW)
+#define GPIO_INT_HIGH (GPIO_INPUT | GPIO_INT_F_HIGH)
+#define GPIO_INT_LEVEL (GPIO_INT_LOW | GPIO_INT_HIGH)
+#define GPIO_INT_ANY (GPIO_INT_BOTH | GPIO_INT_LEVEL)
 #define GPIO_INT_BOTH_DSLEEP (GPIO_INT_BOTH | GPIO_INT_DSLEEP)
-#define GPIO_HIB_WAKE_MASK   (GPIO_HIB_WAKE_HIGH | GPIO_HIB_WAKE_LOW | \
-			      GPIO_HIB_WAKE_RISING|GPIO_HIB_WAKE_FALLING)
+#define GPIO_HIB_WAKE_MASK                                               \
+	(GPIO_HIB_WAKE_HIGH | GPIO_HIB_WAKE_LOW | GPIO_HIB_WAKE_RISING | \
+	 GPIO_HIB_WAKE_FALLING)
 
 /* Convert GPIO mask to GPIO number / index. */
 #define GPIO_MASK_TO_NUM(mask) (__fls(mask))
@@ -151,9 +152,7 @@
  * some boards and unit tests don't have a gpio_signal enum defined, so we
  * define an emtpy one here.*/
 #ifndef __CROS_EC_GPIO_SIGNAL_H
-enum gpio_signal {
-	GPIO_COUNT
-};
+enum gpio_signal { GPIO_COUNT };
 #endif /* __CROS_EC_GPIO_SIGNAL_H */
 
 /* Alternate functions for GPIOs */
@@ -207,7 +206,7 @@ extern const int unused_pin_count;
  * If the signal's interrupt is enabled, this will be called in the
  * context of the GPIO interrupt handler.
  */
-extern void (* const gpio_irq_handlers[])(enum gpio_signal signal);
+extern void (*const gpio_irq_handlers[])(enum gpio_signal signal);
 extern const int gpio_ih_count;
 #define GPIO_IH_COUNT gpio_ih_count
 
@@ -440,7 +439,6 @@ int gpio_clear_pending_interrupt(enum gpio_signal signal);
  */
 void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags);
 
-
 /**
  * Set alternate function for GPIO(s).
  *
@@ -454,7 +452,7 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags);
  *                      the specified GPIOs for normal GPIO operation.
  */
 void gpio_set_alternate_function(uint32_t port, uint32_t mask,
-				enum gpio_alternate_func func);
+				 enum gpio_alternate_func func);
 
 #ifdef CONFIG_GPIO_POWER_DOWN
 /**
@@ -486,4 +484,4 @@ int signal_is_gpio(int signal);
  */
 void gpio_set_wakepin(enum gpio_signal signal, uint32_t flags);
 
-#endif  /* __CROS_EC_GPIO_H */
+#endif /* __CROS_EC_GPIO_H */
diff --git a/include/gpio.wrap b/include/gpio.wrap
index d03f8a9588..84055d3ba3 100644
--- a/include/gpio.wrap
+++ b/include/gpio.wrap
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
+ * Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/gpio_list.h b/include/gpio_list.h
index 6bd43187d9..17fc0d3b09 100644
--- a/include/gpio_list.h
+++ b/include/gpio_list.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,35 +8,35 @@
 #include "gpio_signal.h"
 
 #ifdef CONFIG_COMMON_GPIO_SHORTNAMES
-#define GPIO(name, pin, flags) {GPIO_NAME_BY_##pin, GPIO_##pin, flags},
+#define GPIO(name, pin, flags) { GPIO_NAME_BY_##pin, GPIO_##pin, flags },
 #define GPIO_INT(name, pin, flags, signal) \
-		{GPIO_NAME_BY_##pin, GPIO_##pin, flags},
+	{ GPIO_NAME_BY_##pin, GPIO_##pin, flags },
 #else
-#define GPIO(name, pin, flags) {#name, GPIO_##pin, flags},
-#define GPIO_INT(name, pin, flags, signal) {#name, GPIO_##pin, flags},
+#define GPIO(name, pin, flags) { #name, GPIO_##pin, flags },
+#define GPIO_INT(name, pin, flags, signal) { #name, GPIO_##pin, flags },
 #endif
 
-#define UNIMPLEMENTED(name) {#name, UNIMPLEMENTED_GPIO_BANK, 0, GPIO_DEFAULT},
+#define UNIMPLEMENTED(name) { #name, UNIMPLEMENTED_GPIO_BANK, 0, GPIO_DEFAULT },
 
 /* GPIO signal list. */
 __const_data const struct gpio_info gpio_list[] = {
-	#include "gpio.wrap"
+#include "gpio.wrap"
 };
 
 BUILD_ASSERT(ARRAY_SIZE(gpio_list) == GPIO_COUNT);
 
-#define UNUSED(pin) {GPIO_##pin},
+#define UNUSED(pin) { GPIO_##pin },
 /* Unconnected pin list. */
 __const_data const struct unused_pin_info unused_pin_list[] = {
-	#include "gpio.wrap"
+#include "gpio.wrap"
 };
 
 const int unused_pin_count = ARRAY_SIZE(unused_pin_list);
 
 /* GPIO Interrupt Handlers */
 #define GPIO_INT(name, pin, flags, signal) signal,
-void (* const gpio_irq_handlers[])(enum gpio_signal signal) = {
-	#include "gpio.wrap"
+void (*const gpio_irq_handlers[])(enum gpio_signal signal) = {
+#include "gpio.wrap"
 };
 const int gpio_ih_count = ARRAY_SIZE(gpio_irq_handlers);
 
@@ -47,7 +47,7 @@ const int gpio_ih_count = ARRAY_SIZE(gpio_irq_handlers);
  *
  * This constraint is handled within gpio.wrap.
  */
-#define GPIO_INT(name, pin, flags, signal)	\
+#define GPIO_INT(name, pin, flags, signal) \
 	BUILD_ASSERT(GPIO_##name < ARRAY_SIZE(gpio_irq_handlers));
 #include "gpio.wrap"
 
@@ -64,8 +64,9 @@ const int gpio_ih_count = ARRAY_SIZE(gpio_irq_handlers);
  * The compiler will complain if we use the same name twice. The linker ignores
  * anything that gets by.
  */
-#define PIN(a, b...) static const int _pin_ ## a ## _ ## b \
-	__attribute__((unused, section(".unused"))) = __LINE__;
+#define PIN(a, b...)                    \
+	static const int _pin_##a##_##b \
+		__attribute__((unused, section(".unused"))) = __LINE__;
 #include "gpio.wrap"
 
 #include "ioexpander.h"
@@ -83,7 +84,7 @@ const int gpio_ih_count = ARRAY_SIZE(gpio_irq_handlers);
  *      - flags: the same as the flags of GPIO.
  *
  */
-#define IOEX(name, expin, flags) {#name, IOEX_##expin, flags},
+#define IOEX(name, expin, flags) { #name, IOEX_##expin, flags },
 /*
  *  Define the IO expander IO which supports interrupt in gpio.inc by
  *  the format:
@@ -97,18 +98,18 @@ const int gpio_ih_count = ARRAY_SIZE(gpio_irq_handlers);
  *      - flags: the same as the flags of GPIO.
  *      - handler: the IOEX IO's interrupt handler.
  */
-#define IOEX_INT(name, expin, flags, handler) {#name, IOEX_##expin, flags},
+#define IOEX_INT(name, expin, flags, handler) { #name, IOEX_##expin, flags },
 
 /* IO expander signal list. */
 const struct ioex_info ioex_list[] = {
-	#include "gpio.wrap"
+#include "gpio.wrap"
 };
 BUILD_ASSERT(ARRAY_SIZE(ioex_list) == IOEX_COUNT);
 
 /* IO Expander Interrupt Handlers */
 #define IOEX_INT(name, expin, flags, handler) handler,
-void (* const ioex_irq_handlers[])(enum ioex_signal signal) = {
-	#include "gpio.wrap"
+void (*const ioex_irq_handlers[])(enum ioex_signal signal) = {
+#include "gpio.wrap"
 };
 const int ioex_ih_count = ARRAY_SIZE(ioex_irq_handlers);
 /*
@@ -116,9 +117,9 @@ const int ioex_ih_count = ARRAY_SIZE(ioex_irq_handlers);
  * IOEX's declaration in the gpio.inc
  * file.
  */
-#define IOEX_INT(name, expin, flags, handler)		\
-	BUILD_ASSERT(IOEX_##name - IOEX_SIGNAL_START	\
-		     < ARRAY_SIZE(ioex_irq_handlers));
+#define IOEX_INT(name, expin, flags, handler)          \
+	BUILD_ASSERT(IOEX_##name - IOEX_SIGNAL_START < \
+		     ARRAY_SIZE(ioex_irq_handlers));
 #include "gpio.wrap"
 
 #define IOEX(name, expin, flags) expin
@@ -128,9 +129,9 @@ const int ioex_ih_count = ARRAY_SIZE(ioex_irq_handlers);
  * number declared is greater or equal to CONFIG_IO_EXPANDER_PORT_COUNT.
  * The linker ignores anything that gets by.
  */
-#define EXPIN(a, b, c...) \
-	static const int _expin_ ## a ## _ ## b ## _ ## c \
-	__attribute__((unused, section(".unused"))) = __LINE__; \
+#define EXPIN(a, b, c...)                                               \
+	static const int _expin_##a##_##b##_##c                         \
+		__attribute__((unused, section(".unused"))) = __LINE__; \
 	BUILD_ASSERT(a < CONFIG_IO_EXPANDER_PORT_COUNT);
 
 #include "gpio.wrap"
diff --git a/include/gpio_signal.h b/include/gpio_signal.h
index 86fd5d7822..a499108b40 100644
--- a/include/gpio_signal.h
+++ b/include/gpio_signal.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,7 +27,7 @@
 #define GPIO_SIGNAL_START 0 /* The first valid GPIO signal is 0 */
 
 enum gpio_signal {
-	#include "gpio.wrap"
+#include "gpio.wrap"
 	GPIO_COUNT,
 	/* Ensure that sizeof gpio_signal is large enough for ioex_signal */
 	GPIO_LIMIT = 0x0FFF
@@ -42,7 +42,7 @@ enum ioex_signal {
 	IOEX_SIGNAL_START = GPIO_LIMIT + 1,
 	/* Used to ensure that the first IOEX signal is same as start */
 	__IOEX_PLACEHOLDER = GPIO_LIMIT,
-	#include "gpio.wrap"
+#include "gpio.wrap"
 	IOEX_SIGNAL_END,
 	IOEX_LIMIT = 0x1FFF
 };
diff --git a/include/gyro_cal.h b/include/gyro_cal.h
index fb69464aec..fe48d71360 100644
--- a/include/gyro_cal.h
+++ b/include/gyro_cal.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/gyro_still_det.h b/include/gyro_still_det.h
index a776da7ae7..a0332d598a 100644
--- a/include/gyro_still_det.h
+++ b/include/gyro_still_det.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/hooks.h b/include/hooks.h
index e629ffbd9b..1002c7c93d 100644
--- a/include/hooks.h
+++ b/include/hooks.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,12 +12,12 @@
 
 enum hook_priority {
 	/* Generic values across all hooks */
-	HOOK_PRIO_FIRST = 1,       /* Highest priority */
+	HOOK_PRIO_FIRST = 1, /* Highest priority */
 	HOOK_PRIO_POST_FIRST = HOOK_PRIO_FIRST + 1,
-	HOOK_PRIO_DEFAULT = 5000,  /* Default priority */
+	HOOK_PRIO_DEFAULT = 5000, /* Default priority */
 	HOOK_PRIO_PRE_DEFAULT = HOOK_PRIO_DEFAULT - 1,
 	HOOK_PRIO_POST_DEFAULT = HOOK_PRIO_DEFAULT + 1,
-	HOOK_PRIO_LAST = 9999,     /* Lowest priority */
+	HOOK_PRIO_LAST = 9999, /* Lowest priority */
 
 	/* Specific hook vales for HOOK_INIT */
 	/* DMA inits before ADC, I2C, SPI */
@@ -253,6 +253,11 @@ enum hook_type {
 	 */
 	HOOK_USB_PD_CONNECT,
 
+	/*
+	 * Power supply change event.
+	 */
+	HOOK_POWER_SUPPLY_CHANGE,
+
 #ifdef TEST_BUILD
 	/*
 	 * Special hook types to be used by unit tests of the hooks
@@ -261,7 +266,7 @@ enum hook_type {
 	HOOK_TEST_1,
 	HOOK_TEST_2,
 	HOOK_TEST_3,
-#endif  /* TEST_BUILD */
+#endif /* TEST_BUILD */
 
 	/*
 	 * Not a hook type (instead the number of hooks). This should
@@ -346,11 +351,12 @@ int hook_call_deferred(const struct deferred_data *data, int us);
  *			unless there's a compelling reason to care about the
  *			order in which hooks are called.
  */
-#define DECLARE_HOOK(hooktype, routine, priority)			\
-	const struct hook_data __keep __no_sanitize_address		\
-	CONCAT4(__hook_, hooktype, _, routine)				\
-	__attribute__((section(".rodata." STRINGIFY(hooktype))))	\
-	     = {routine, priority}
+#define DECLARE_HOOK(hooktype, routine, priority)                            \
+	const struct hook_data __keep __no_sanitize_address CONCAT4(         \
+		__hook_, hooktype, _, routine)                               \
+		__attribute__((section(".rodata." STRINGIFY(hooktype)))) = { \
+			routine, priority                                    \
+		}
 
 /**
  * Register a deferred function call.
@@ -371,21 +377,26 @@ int hook_call_deferred(const struct deferred_data *data, int us);
  *
  * @param routine	Function pointer, with prototype void routine(void)
  */
-#define DECLARE_DEFERRED(routine)					\
-	const struct deferred_data __keep __no_sanitize_address		\
-	CONCAT2(routine, _data)						\
-	__attribute__((section(".rodata.deferred")))			\
-	     = {routine}
+#define DECLARE_DEFERRED(routine)                                        \
+	const struct deferred_data __keep __no_sanitize_address CONCAT2( \
+		routine, _data)                                          \
+		__attribute__((section(".rodata.deferred"))) = { routine }
 #else
 /*
  * Stub implementation in case hooks are disabled (neither
  * CONFIG_COMMON_RUNTIME nor CONFIG_PLATFORM_EC_HOOKS is defined)
  */
 #define hook_call_deferred(unused1, unused2) -1
-#define DECLARE_HOOK(t, func, p)				\
-	void CONCAT2(unused_hook_, func)(void) { func(); }
-#define DECLARE_DEFERRED(func)					\
-	void CONCAT2(unused_deferred_, func)(void) { func(); }
+#define DECLARE_HOOK(t, func, p)               \
+	void CONCAT2(unused_hook_, func)(void) \
+	{                                      \
+		func();                        \
+	}
+#define DECLARE_DEFERRED(func)                     \
+	void CONCAT2(unused_deferred_, func)(void) \
+	{                                          \
+		func();                            \
+	}
 #endif
 
-#endif  /* __CROS_EC_HOOKS_H */
+#endif /* __CROS_EC_HOOKS_H */
diff --git a/include/host_command.h b/include/host_command.h
index 3ab3d54351..59389107c7 100644
--- a/include/host_command.h
+++ b/include/host_command.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,6 +12,10 @@
 #include "common.h"
 #include "ec_commands.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /* Args for host command handler */
 struct host_cmd_handler_args {
 	/*
@@ -20,11 +24,11 @@ struct host_cmd_handler_args {
 	 * send the response back to the host.
 	 */
 	void (*send_response)(struct host_cmd_handler_args *args);
-	uint16_t command;      /* Command (e.g., EC_CMD_FLASH_GET_INFO) */
-	uint8_t version;       /* Version of command (0-31) */
+	uint16_t command; /* Command (e.g., EC_CMD_FLASH_GET_INFO) */
+	uint8_t version; /* Version of command (0-31) */
 
 	const void *params; /* Input parameters */
-	uint16_t params_size;  /* Size of input parameters in bytes */
+	uint16_t params_size; /* Size of input parameters in bytes */
 
 	/*
 	 * Pointer to output response data buffer.  On input to the handler,
@@ -130,14 +134,13 @@ struct host_command {
 
 #ifdef CONFIG_HOST_EVENT64
 typedef uint64_t host_event_t;
-#define HOST_EVENT_CPRINTS(str, e)	CPRINTS("%s 0x%016" PRIx64, str, e)
-#define HOST_EVENT_CCPRINTF(str, e) \
-	ccprintf("%s 0x%016" PRIx64 "\n", str, e)
+#define HOST_EVENT_CPRINTS(str, e) CPRINTS("%s 0x%016" PRIx64, str, e)
+#define HOST_EVENT_CCPRINTF(str, e) ccprintf("%s 0x%016" PRIx64 "\n", str, e)
 
 #else
 typedef uint32_t host_event_t;
-#define HOST_EVENT_CPRINTS(str, e)	CPRINTS("%s 0x%08x", str, e)
-#define HOST_EVENT_CCPRINTF(str, e)	ccprintf("%s 0x%08x\n", str, e)
+#define HOST_EVENT_CPRINTS(str, e) CPRINTS("%s 0x%08x", str, e)
+#define HOST_EVENT_CCPRINTF(str, e) ccprintf("%s 0x%08x\n", str, e)
 #endif
 
 /**
@@ -256,44 +259,46 @@ void host_packet_receive(struct host_packet *pkt);
 #ifndef CONFIG_ZEPHYR
 __error("This function should only be called from Zephyr OS code")
 #endif
-struct host_command *zephyr_find_host_command(int command);
+	struct host_command *zephyr_find_host_command(int command);
 
 #if defined(CONFIG_ZEPHYR)
 #include "zephyr_host_command.h"
 #elif defined(HAS_TASK_HOSTCMD)
 #define EXPAND(off, cmd) __host_cmd_(off, cmd)
 #define __host_cmd_(off, cmd) __host_cmd_##off##cmd
-#define EXPANDSTR(off, cmd) "__host_cmd_"#off#cmd
+#define EXPANDSTR(off, cmd) "__host_cmd_" #off #cmd
 
 /*
  * Register a host command handler with
  * commands starting at offset 0x0000
  */
-#define DECLARE_HOST_COMMAND(command, routine, version_mask)		\
-	static enum ec_status(routine)(struct host_cmd_handler_args *args); \
-	const struct host_command __keep __no_sanitize_address		\
-	EXPAND(0x0000, command)						\
-	__attribute__((section(".rodata.hcmds." EXPANDSTR(0x0000, command)))) \
-		= {routine, command, version_mask}
+#define DECLARE_HOST_COMMAND(command, routine, version_mask)                   \
+	static enum ec_status(routine)(struct host_cmd_handler_args * args);   \
+	const struct host_command __keep __no_sanitize_address EXPAND(0x0000,  \
+								      command) \
+		__attribute__((section(".rodata.hcmds." EXPANDSTR(             \
+			0x0000, command)))) = { routine, command,              \
+						version_mask }
 
 /*
  * Register a private host command handler with
  * commands starting at offset EC_CMD_BOARD_SPECIFIC_BASE,
  */
-#define DECLARE_PRIVATE_HOST_COMMAND(command, routine, version_mask) \
-	static enum ec_status(routine)(struct host_cmd_handler_args *args); \
-	const struct host_command __keep __no_sanitize_address	     \
-	EXPAND(EC_CMD_BOARD_SPECIFIC_BASE, command) \
-	__attribute__((section(".rodata.hcmds."\
-	EXPANDSTR(EC_CMD_BOARD_SPECIFIC_BASE, command)))) \
-		= {routine, EC_PRIVATE_HOST_COMMAND_VALUE(command), \
-		   version_mask}
+#define DECLARE_PRIVATE_HOST_COMMAND(command, routine, version_mask)         \
+	static enum ec_status(routine)(struct host_cmd_handler_args * args); \
+	const struct host_command __keep __no_sanitize_address EXPAND(       \
+		EC_CMD_BOARD_SPECIFIC_BASE, command)                         \
+		__attribute__((section(".rodata.hcmds." EXPANDSTR(           \
+			EC_CMD_BOARD_SPECIFIC_BASE, command)))) = {          \
+			routine, EC_PRIVATE_HOST_COMMAND_VALUE(command),     \
+			version_mask                                         \
+		}
 #else /* !CONFIG_ZEPHYR && !HAS_TASK_HOSTCMD */
-#define DECLARE_HOST_COMMAND(command, routine, version_mask)    \
-	static enum ec_status (routine)(struct host_cmd_handler_args *args) \
+#define DECLARE_HOST_COMMAND(command, routine, version_mask)                \
+	static enum ec_status(routine)(struct host_cmd_handler_args * args) \
 		__attribute__((unused))
 
-#define DECLARE_PRIVATE_HOST_COMMAND(command, routine, version_mask)	\
+#define DECLARE_PRIVATE_HOST_COMMAND(command, routine, version_mask) \
 	DECLARE_HOST_COMMAND(command, routine, version_mask)
 #endif /* CONFIG_ZEPHYR */
 
@@ -304,7 +309,6 @@ struct host_command *zephyr_find_host_command(int command);
  */
 void host_throttle_cpu(int throttle);
 
-
 /**
  * Signal host command task to send status to PD MCU.
  *
@@ -335,8 +339,7 @@ int pd_get_active_charge_port(void);
  * @param indata Pointer to buffer to store response
  * @param insize Size of buffer to store response
  */
-int pd_host_command(int command, int version,
-		    const void *outdata, int outsize,
+int pd_host_command(int command, int version, const void *outdata, int outsize,
 		    void *indata, int insize);
 
 /*
@@ -358,29 +361,33 @@ stub_send_response_callback(struct host_cmd_handler_args *args)
 	ARG_UNUSED(args);
 }
 
-#define BUILD_HOST_COMMAND(CMD, VERSION, RESPONSE, PARAMS)		\
-	{								\
-		.command = (CMD), .version = (VERSION),			\
-		.send_response = stub_send_response_callback,		\
-		.response_size = 0,					\
-		COND_CODE_0(IS_EMPTY(RESPONSE),				\
-		    (.response = &(RESPONSE),				\
-		     .response_max = sizeof(RESPONSE)),			\
-		    (.response = NULL, .response_max = 0)),		\
-		COND_CODE_0(IS_EMPTY(PARAMS),				\
-		    (.params = &(PARAMS),				\
-		     .params_size = sizeof(PARAMS)),			\
-		    (.params = NULL, .params_size = 0))			\
+#define BUILD_HOST_COMMAND(CMD, VERSION, RESPONSE, PARAMS)          \
+	{                                                           \
+		.send_response = stub_send_response_callback,       \
+		.command = (CMD), .version = (VERSION),             \
+		COND_CODE_0(IS_EMPTY(PARAMS),                       \
+			    (.params = &(PARAMS),                   \
+			     .params_size = sizeof(PARAMS)),        \
+			    (.params = NULL, .params_size = 0)),    \
+		COND_CODE_0(IS_EMPTY(RESPONSE),                     \
+			    (.response = &(RESPONSE),               \
+			     .response_max = sizeof(RESPONSE)),     \
+			    (.response = NULL, .response_max = 0)), \
+		.response_size = 0,                                 \
 	}
 
-#define BUILD_HOST_COMMAND_RESPONSE(CMD, VERSION, RESPONSE)		\
+#define BUILD_HOST_COMMAND_RESPONSE(CMD, VERSION, RESPONSE) \
 	BUILD_HOST_COMMAND(CMD, VERSION, RESPONSE, EMPTY)
 
-#define BUILD_HOST_COMMAND_PARAMS(CMD, VERSION, PARAMS)			\
+#define BUILD_HOST_COMMAND_PARAMS(CMD, VERSION, PARAMS) \
 	BUILD_HOST_COMMAND(CMD, VERSION, EMPTY, PARAMS)
 
-#define BUILD_HOST_COMMAND_SIMPLE(CMD, VERSION)				\
+#define BUILD_HOST_COMMAND_SIMPLE(CMD, VERSION) \
 	BUILD_HOST_COMMAND(CMD, VERSION, EMPTY, EMPTY)
 #endif /* CONFIG_ZTEST */
 
-#endif  /* __CROS_EC_HOST_COMMAND_H */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CROS_EC_HOST_COMMAND_H */
diff --git a/include/host_command_heci.h b/include/host_command_heci.h
index 1dcb054ff6..5595724b59 100644
--- a/include/host_command_heci.h
+++ b/include/host_command_heci.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/hotword_dsp_api.h b/include/hotword_dsp_api.h
index 369af00ede..311add6675 100644
--- a/include/hotword_dsp_api.h
+++ b/include/hotword_dsp_api.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -44,4 +44,4 @@ int GoogleHotwordDspGetMaximumAudioPreambleMs(void);
 /* Returns an internal version number that this library was built at. */
 extern int GoogleHotwordVersion(void);
 
-#endif  /* SPEECH_MICRO_API_HOTWORD_DSP_API_H_ */
+#endif /* SPEECH_MICRO_API_HOTWORD_DSP_API_H_ */
diff --git a/include/hwtimer.h b/include/hwtimer.h
index 3c0e9aaf8a..093a44cad1 100644
--- a/include/hwtimer.h
+++ b/include/hwtimer.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -34,7 +34,8 @@ void __hw_clock_event_clear(void);
 #ifdef CONFIG_HWTIMER_64BIT
 __override_proto
 #endif
-uint32_t __hw_clock_source_read(void);
+	uint32_t
+	__hw_clock_source_read(void);
 
 /**
  * Override the lower 32-bits of the hardware counter
@@ -115,4 +116,4 @@ void hwtimer_setup_watchdog(void);
 /* Reset the watchdog timer, to avoid the watchdog warning */
 void hwtimer_reset_watchdog(void);
 
-#endif  /* __CROS_EC_HWTIMER_H */
+#endif /* __CROS_EC_HWTIMER_H */
diff --git a/include/i2c.h b/include/i2c.h
index c799b9599d..4da9306abb 100644
--- a/include/i2c.h
+++ b/include/i2c.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -34,15 +34,15 @@
  * used here and in motion_sense to give specific meaning to the
  * address that is pertinent to its use.
  */
-#define I2C_ADDR_MASK		0x03FF
-#define I2C_FLAG_PEC		BIT(13)
-#define I2C_FLAG_BIG_ENDIAN	BIT(14)
+#define I2C_ADDR_MASK 0x03FF
+#define I2C_FLAG_PEC BIT(13)
+#define I2C_FLAG_BIG_ENDIAN BIT(14)
 /* BIT(15) SPI_FLAG - used in motion_sense to overload address */
-#define I2C_FLAG_ADDR_IS_SPI	BIT(15)
+#define I2C_FLAG_ADDR_IS_SPI BIT(15)
 
-#define I2C_STRIP_FLAGS(addr_flags)	((addr_flags) & I2C_ADDR_MASK)
-#define I2C_USE_PEC(addr_flags)		((addr_flags) & I2C_FLAG_PEC)
-#define I2C_IS_BIG_ENDIAN(addr_flags)	((addr_flags) & I2C_FLAG_BIG_ENDIAN)
+#define I2C_STRIP_FLAGS(addr_flags) ((addr_flags)&I2C_ADDR_MASK)
+#define I2C_USE_PEC(addr_flags) ((addr_flags)&I2C_FLAG_PEC)
+#define I2C_IS_BIG_ENDIAN(addr_flags) ((addr_flags)&I2C_FLAG_BIG_ENDIAN)
 
 /*
  * All 7-bit addresses in the following formats
@@ -51,8 +51,8 @@
  * are reserved for various purposes. Valid 7-bit client adderesses start at
  * 0x08 and end at 0x77 inclusive.
  */
-#define I2C_FIRST_VALID_ADDR	0x08
-#define I2C_LAST_VALID_ADDR	0x77
+#define I2C_FIRST_VALID_ADDR 0x08
+#define I2C_LAST_VALID_ADDR 0x77
 
 /*
  * Max data size for a version 3 request/response packet. This is
@@ -67,7 +67,7 @@
 #define I2C_RESPONSE_HEADER_SIZE 2
 
 /* This port allows changing speed at runtime */
-#define I2C_PORT_FLAG_DYNAMIC_SPEED	BIT(0)
+#define I2C_PORT_FLAG_DYNAMIC_SPEED BIT(0)
 
 /*
  * Supported I2C CLK frequencies.
@@ -85,13 +85,10 @@ enum i2c_freq {
  *      MASK_SET will OR the mask into the old value
  *      MASK_CLR will AND the ~mask from the old value
  */
-enum mask_update_action {
-	MASK_CLR,
-	MASK_SET
-};
+enum mask_update_action { MASK_CLR, MASK_SET };
 
 struct i2c_info_t {
-	uint16_t port;	/* Physical port for device */
+	uint16_t port; /* Physical port for device */
 	uint16_t addr_flags;
 };
 
@@ -99,17 +96,16 @@ struct i2c_port_t; /* forward declaration */
 
 struct i2c_drv {
 	int (*xfer)(const struct i2c_port_t *i2c_port,
-		    const uint16_t addr_flags,
-		    const uint8_t *out, int out_size,
+		    const uint16_t addr_flags, const uint8_t *out, int out_size,
 		    uint8_t *in, int in_size, int flags);
 };
 
 /* Data structure to define I2C port configuration. */
 struct i2c_port_t {
-	int port;             /* Port */
+	int port; /* Port */
 #ifndef CONFIG_ZEPHYR
-	const char *name;     /* Port name */
-	int kbps;             /* Speed in kbps */
+	const char *name; /* Port name */
+	int kbps; /* Speed in kbps */
 	enum gpio_signal scl; /* Port SCL GPIO line */
 	enum gpio_signal sda; /* Port SDA GPIO line */
 #endif /* CONFIG_ZEPHYR */
@@ -118,7 +114,7 @@ struct i2c_port_t {
 	int (*passthru_allowed)(const struct i2c_port_t *port,
 				uint16_t addr_flags);
 	const struct i2c_drv *drv;
-	uint16_t flags;       /* I2C_PORT_FLAG_* flags */
+	uint16_t flags; /* I2C_PORT_FLAG_* flags */
 };
 
 extern const struct i2c_port_t i2c_ports[];
@@ -126,27 +122,25 @@ extern const unsigned int i2c_ports_used;
 
 #ifdef CONFIG_CMD_I2C_STRESS_TEST
 struct i2c_test_reg_info {
-	int read_reg;      /* Read register (WHO_AM_I, DEV_ID, MAN_ID) */
-	int read_val;      /* Expected val (WHO_AM_I, DEV_ID, MAN_ID) */
-	int write_reg;     /* Read/Write reg which doesn't impact the system */
+	int read_reg; /* Read register (WHO_AM_I, DEV_ID, MAN_ID) */
+	int read_val; /* Expected val (WHO_AM_I, DEV_ID, MAN_ID) */
+	int write_reg; /* Read/Write reg which doesn't impact the system */
 };
 
 struct i2c_test_results {
-	int read_success;  /* Successful read count */
-	int read_fail;     /* Read fail count */
+	int read_success; /* Successful read count */
+	int read_fail; /* Read fail count */
 	int write_success; /* Successful write count */
-	int write_fail;    /* Write fail count */
+	int write_fail; /* Write fail count */
 };
 
 /* Data structure to define I2C test configuration. */
 struct i2c_stress_test_dev {
 	struct i2c_test_reg_info reg_info;
 	struct i2c_test_results test_results;
-	int (*i2c_read)(const int port,
-			const uint16_t addr_flags,
+	int (*i2c_read)(const int port, const uint16_t addr_flags,
 			const int reg, int *data);
-	int (*i2c_write)(const int port,
-			 const uint16_t addr_flags,
+	int (*i2c_write)(const int port, const uint16_t addr_flags,
 			 const int reg, int data);
 	int (*i2c_read_dev)(const int reg, int *data);
 	int (*i2c_write_dev)(const int reg, int data);
@@ -166,15 +160,15 @@ extern const int i2c_test_dev_used;
  * Data structure to define I2C Parameters for a command
  */
 struct i2c_cmd_desc_t {
-	uint8_t port;		/* I2C port */
-	uint16_t addr_flags;	/* Peripheral address and flags */
-	uint8_t cmd;		/* command, only valid on write operations */
+	uint8_t port; /* I2C port */
+	uint16_t addr_flags; /* Peripheral address and flags */
+	uint8_t cmd; /* command, only valid on write operations */
 };
 
 /* Flags for i2c_xfer_unlocked() */
-#define I2C_XFER_START BIT(0)  /* Start smbus session from idle state */
-#define I2C_XFER_STOP BIT(1)  /* Terminate smbus session with stop bit */
-#define I2C_XFER_SINGLE (I2C_XFER_START | I2C_XFER_STOP)  /* One transaction */
+#define I2C_XFER_START BIT(0) /* Start smbus session from idle state */
+#define I2C_XFER_STOP BIT(1) /* Terminate smbus session with stop bit */
+#define I2C_XFER_SINGLE (I2C_XFER_START | I2C_XFER_STOP) /* One transaction */
 
 /**
  * Transmit one block of raw data, then receive one block of raw data. However,
@@ -190,10 +184,8 @@ struct i2c_cmd_desc_t {
  * @param in_size	Number of bytes to receive
  * @return EC_SUCCESS, or non-zero if error.
  */
-int i2c_xfer(const int port,
-	     const uint16_t addr_flags,
-	     const uint8_t *out, int out_size,
-	     uint8_t *in, int in_size);
+int i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out,
+	     int out_size, uint8_t *in, int in_size);
 
 /**
  * Same as i2c_xfer, but the bus is not implicitly locked.  It must be called
@@ -201,10 +193,9 @@ int i2c_xfer(const int port,
  *
  * @param flags		Flags (see I2C_XFER_* above)
  */
-int i2c_xfer_unlocked(const int port,
-		      const uint16_t addr_flags,
-		      const uint8_t *out, int out_size,
-		      uint8_t *in, int in_size, int flags);
+int i2c_xfer_unlocked(const int port, const uint16_t addr_flags,
+		      const uint8_t *out, int out_size, uint8_t *in,
+		      int in_size, int flags);
 
 #define I2C_LINE_SCL_HIGH BIT(0)
 #define I2C_LINE_SDA_HIGH BIT(1)
@@ -305,54 +296,46 @@ void i2c_set_timeout(int port, uint32_t timeout);
  * <addr_flags>, at the specified 8-bit <offset> in the peripheral's address
  * space.
  */
-int i2c_read32(const int port,
-	       const uint16_t addr_flags,
-	       int offset, int *data);
+int i2c_read32(const int port, const uint16_t addr_flags, int offset,
+	       int *data);
 
 /**
  * Write a 32-bit register to the peripheral at 7-bit peripheral address
  * <addr_flags>, at the specified 8-bit <offset> in the peripheral's address
  * space.
  */
-int i2c_write32(const int port,
-		const uint16_t addr_flags,
-		int offset, int data);
+int i2c_write32(const int port, const uint16_t addr_flags, int offset,
+		int data);
 
 /**
  * Read a 16-bit register from the peripheral at 7-bit peripheral address
  * <addr_flags>, at the specified 8-bit <offset> in the peripheral's address
  * space.
  */
-int i2c_read16(const int port,
-	       const uint16_t addr_flags,
-	       int offset, int *data);
+int i2c_read16(const int port, const uint16_t addr_flags, int offset,
+	       int *data);
 
 /**
  * Write a 16-bit register to the peripheral at 7-bit peripheral address
  * <addr_flags>, at the specified 8-bit <offset> in the peripheral's address
  * space.
  */
-int i2c_write16(const int port,
-		const uint16_t addr_flags,
-		int offset, int data);
+int i2c_write16(const int port, const uint16_t addr_flags, int offset,
+		int data);
 
 /**
  * Read an 8-bit register from the peripheral at 7-bit peripheral address
  * <addr_flags>, at the specified 8-bit <offset> in the peripheral's address
  * space.
  */
-int i2c_read8(const int port,
-	      const uint16_t addr_flags,
-	      int offset, int *data);
+int i2c_read8(const int port, const uint16_t addr_flags, int offset, int *data);
 
 /**
  * Write an 8-bit register to the peripheral at 7-bit peripheral address
  * <addr_flags>, at the specified 8-bit <offset> in the peripheral's address
  * space.
  */
-int i2c_write8(const int port,
-	       const uint16_t addr_flags,
-	       int offset, int data);
+int i2c_write8(const int port, const uint16_t addr_flags, int offset, int data);
 
 /**
  * Read, modify, write an i2c register to the peripheral at 7-bit peripheral
@@ -362,17 +345,11 @@ int i2c_write8(const int port,
  * is the same as the original value of the register, the write will not be
  * performed.
  */
-int i2c_update8(const int port,
-		const uint16_t addr_flags,
-		const int offset,
-		const uint8_t mask,
-		const enum mask_update_action action);
+int i2c_update8(const int port, const uint16_t addr_flags, const int offset,
+		const uint8_t mask, const enum mask_update_action action);
 
-int i2c_update16(const int port,
-		 const uint16_t addr_flags,
-		 const int offset,
-		 const uint16_t mask,
-		 const enum mask_update_action action);
+int i2c_update16(const int port, const uint16_t addr_flags, const int offset,
+		 const uint16_t mask, const enum mask_update_action action);
 
 /**
  * Read, modify, write field of an i2c register to the peripheral at 7-bit
@@ -383,48 +360,40 @@ int i2c_update16(const int port,
  * new value is not the same as the original value, the new value will be
  * written back out to the device, otherwise no write will be performed.
  */
-int i2c_field_update8(const int port,
-		      const uint16_t addr_flags,
-		      const int offset,
-		      const uint8_t field_mask,
+int i2c_field_update8(const int port, const uint16_t addr_flags,
+		      const int offset, const uint8_t field_mask,
 		      const uint8_t set_value);
 
-int i2c_field_update16(const int port,
-		       const uint16_t addr_flags,
-		       const int offset,
-		       const uint16_t field_mask,
+int i2c_field_update16(const int port, const uint16_t addr_flags,
+		       const int offset, const uint16_t field_mask,
 		       const uint16_t set_value);
 
 /**
  * Read one or two bytes data from the peripheral at 7-bit peripheral address
  * <addr_flags>, at 16-bit <offset> in the peripheral's address space.
  */
-int i2c_read_offset16(const int port,
-		      const uint16_t addr_flags,
+int i2c_read_offset16(const int port, const uint16_t addr_flags,
 		      uint16_t offset, int *data, int len);
 
 /**
  * Write one or two bytes data to the peripheral at 7-bit peripheral address
  * <addr_flags>, at 16-bit <offset> in the peripheral's address space.
  */
-int i2c_write_offset16(const int port,
-		       const uint16_t addr_flags,
+int i2c_write_offset16(const int port, const uint16_t addr_flags,
 		       uint16_t offset, int data, int len);
 
 /**
  * Read <len> bytes block data from the peripheral at 7-bit peripheral address
  * * <addr_flags>, at 16-bit <offset> in the peripheral's address space.
  */
-int i2c_read_offset16_block(const int port,
-			    const uint16_t addr_flags,
+int i2c_read_offset16_block(const int port, const uint16_t addr_flags,
 			    uint16_t offset, uint8_t *data, int len);
 
 /**
  * Write <len> bytes block data to the peripheral at 7-bit peripheral address
  * <addr_flags>, at 16-bit <offset> in the peripheral's address space.
  */
-int i2c_write_offset16_block(const int port,
-			     const uint16_t addr_flags,
+int i2c_write_offset16_block(const int port, const uint16_t addr_flags,
 			     uint16_t offset, const uint8_t *data, int len);
 
 /**
@@ -448,9 +417,8 @@ int i2c_unwedge(int port);
  *
  * <len>      : the max length of receiving buffer
  */
-int i2c_read_sized_block(const int port,
-			 const uint16_t addr_flags,
-			 int offset, uint8_t *data, int max_len, int *read_len);
+int i2c_read_sized_block(const int port, const uint16_t addr_flags, int offset,
+			 uint8_t *data, int max_len, int *read_len);
 
 /**
  * Read ascii string using smbus read block protocol.
@@ -462,27 +430,24 @@ int i2c_read_sized_block(const int port,
  *              terminating 0.  Similar to strlcpy, the terminating null is
  *              always written into the output buffer.
  */
-int i2c_read_string(const int port,
-		    const uint16_t addr_flags,
-		    int offset, uint8_t *data, int len);
+int i2c_read_string(const int port, const uint16_t addr_flags, int offset,
+		    uint8_t *data, int len);
 
 /**
  * Read a data block of <len> 8-bit transfers from the peripheral at 7-bit
  * peripheral address <addr_flags>, at the specified 8-bit <offset> in the
  * peripheral's address space.
  */
-int i2c_read_block(const int port,
-		   const uint16_t addr_flags,
-		   int offset, uint8_t *data, int len);
+int i2c_read_block(const int port, const uint16_t addr_flags, int offset,
+		   uint8_t *data, int len);
 
 /**
  * Write a data block of <len> 8-bit transfers to the peripheral at 7-bit
  * peripheral address <addr_flags>, at the specified 8-bit <offset> in the
  * peripheral's address space.
  */
-int i2c_write_block(const int port,
-		    const uint16_t addr_flags,
-		    int offset, const uint8_t *data, int len);
+int i2c_write_block(const int port, const uint16_t addr_flags, int offset,
+		    const uint8_t *data, int len);
 
 /**
  * Convert port number to controller number, for multi-port controllers.
@@ -548,8 +513,7 @@ int board_is_i2c_port_powered(int port);
  * @param addr_flags: Peripheral device address
  *
  */
-void i2c_start_xfer_notify(const int port,
-			   const uint16_t addr_flags);
+void i2c_start_xfer_notify(const int port, const uint16_t addr_flags);
 
 /**
  * Function to allow board to take any action after an i2c transaction on a
@@ -560,8 +524,7 @@ void i2c_start_xfer_notify(const int port,
  * @param addr_flags: Peripheral device address
  *
  */
-void i2c_end_xfer_notify(const int port,
-			 const uint16_t addr_flags);
+void i2c_end_xfer_notify(const int port, const uint16_t addr_flags);
 
 /**
  * Defined in common/i2c_trace.c, used by i2c controller to notify tracing
@@ -575,9 +538,9 @@ void i2c_end_xfer_notify(const int port,
  * @param in_size: size of data read
  * @param ret: return of i2c transaction (EC_SUCCESS or otherwise on failure)
  */
-void i2c_trace_notify(int port, uint16_t addr_flags,
-		      const uint8_t *out_data, size_t out_size,
-		      const uint8_t *in_data, size_t in_size, int ret);
+void i2c_trace_notify(int port, uint16_t addr_flags, const uint8_t *out_data,
+		      size_t out_size, const uint8_t *in_data, size_t in_size,
+		      int ret);
 
 /**
  * Convert an enum i2c_freq constant to numeric frequency in kHz.
@@ -622,18 +585,10 @@ enum i2c_freq i2c_get_freq(int port);
 /* Find the matching port in i2c_ports[] table. */
 const struct i2c_port_t *get_i2c_port(const int port);
 
-/**
- * @brief Get soc's i2c port number where i2c device is connected to.
- *
- * This function translate a i2c port enum value (enum-name property listed in
- * named-i2c-ports) to soc's i2c port. Devices which are connected to the
- * same port of soc should have the same number.
- *
- * @param enum_port i2c port enum value.
- * @return i2c port of soc used in mutex_lock().
- *         -1 if physical port is not defined or i2c port number is out of
- *         port_mutex space.
- */
-int i2c_get_physical_port(int enum_port);
+#ifdef CONFIG_ZTEST
+int i2c_port_is_locked(int port);
+#endif
+
+__test_only void i2c_passthru_protect_reset(void);
 
-#endif  /* __CROS_EC_I2C_H */
+#endif /* __CROS_EC_I2C_H */
diff --git a/include/i2c_bitbang.h b/include/i2c_bitbang.h
index 12486b7ee6..cc9b5cbc11 100644
--- a/include/i2c_bitbang.h
+++ b/include/i2c_bitbang.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/i2c_hid.h b/include/i2c_hid.h
index 8568b42837..03b216d3c5 100644
--- a/include/i2c_hid.h
+++ b/include/i2c_hid.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,25 +26,25 @@
  * I2C_HID_HID_DESC_REGISTER is defined in the ACPI table so please make sure
  * you have put in the same value there.
  */
-#define I2C_HID_HID_DESC_REGISTER	0x0001
-#define I2C_HID_REPORT_DESC_REGISTER	0x1000
-#define I2C_HID_INPUT_REPORT_REGISTER	0x2000
-#define I2C_HID_COMMAND_REGISTER	0x3000
-#define I2C_HID_DATA_REGISTER		0x3000
+#define I2C_HID_HID_DESC_REGISTER 0x0001
+#define I2C_HID_REPORT_DESC_REGISTER 0x1000
+#define I2C_HID_INPUT_REPORT_REGISTER 0x2000
+#define I2C_HID_COMMAND_REGISTER 0x3000
+#define I2C_HID_DATA_REGISTER 0x3000
 
 /* I2C-HID commands */
-#define I2C_HID_CMD_RESET		0x01
-#define I2C_HID_CMD_GET_REPORT		0x02
-#define I2C_HID_CMD_SET_REPORT		0x03
-#define I2C_HID_CMD_GET_IDLE		0x04
-#define I2C_HID_CMD_SET_IDLE		0x05
-#define I2C_HID_CMD_GET_PROTOCOL	0x06
-#define I2C_HID_CMD_SET_PROTOCOL	0x07
-#define I2C_HID_CMD_SET_POWER		0x08
+#define I2C_HID_CMD_RESET 0x01
+#define I2C_HID_CMD_GET_REPORT 0x02
+#define I2C_HID_CMD_SET_REPORT 0x03
+#define I2C_HID_CMD_GET_IDLE 0x04
+#define I2C_HID_CMD_SET_IDLE 0x05
+#define I2C_HID_CMD_GET_PROTOCOL 0x06
+#define I2C_HID_CMD_SET_PROTOCOL 0x07
+#define I2C_HID_CMD_SET_POWER 0x08
 
 /* Common HID fields */
-#define I2C_HID_DESC_LENGTH		sizeof(struct i2c_hid_descriptor)
-#define I2C_HID_BCD_VERSION		0x0100
+#define I2C_HID_DESC_LENGTH sizeof(struct i2c_hid_descriptor)
+#define I2C_HID_BCD_VERSION 0x0100
 
 /* I2C-HID HID descriptor */
 struct __packed i2c_hid_descriptor {
diff --git a/include/i2c_hid_touchpad.h b/include/i2c_hid_touchpad.h
index d5d728a488..d425650c40 100644
--- a/include/i2c_hid_touchpad.h
+++ b/include/i2c_hid_touchpad.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,7 +13,7 @@
 #include "stdint.h"
 
 /* Max fingers to support */
-#define I2C_HID_TOUCHPAD_MAX_FINGERS	5
+#define I2C_HID_TOUCHPAD_MAX_FINGERS 5
 
 /*
  * Struct holding a touchpad event
diff --git a/include/i2c_ite_flash_support.h b/include/i2c_ite_flash_support.h
index f70bec877a..241524f4b9 100644
--- a/include/i2c_ite_flash_support.h
+++ b/include/i2c_ite_flash_support.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/i2c_peripheral.h b/include/i2c_peripheral.h
index 488e886b0e..dd4e4b0c7b 100644
--- a/include/i2c_peripheral.h
+++ b/include/i2c_peripheral.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,9 +10,9 @@
 
 /* Data structure to define I2C peripheral port configuration. */
 struct i2c_periph_port_t {
-	const char *name;     /* Port name */
-	int port;             /* Port */
-	uint8_t addr;         /* address(7-bit without R/W) */
+	const char *name; /* Port name */
+	int port; /* Port */
+	uint8_t addr; /* address(7-bit without R/W) */
 };
 
 extern const struct i2c_periph_port_t i2c_periph_ports[];
diff --git a/include/i2c_private.h b/include/i2c_private.h
index 0759f86ef2..269b6810bd 100644
--- a/include/i2c_private.h
+++ b/include/i2c_private.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -29,10 +29,8 @@
  * @param flags		Flags (see I2C_XFER_* above)
  * @return EC_SUCCESS, or non-zero if error.
  */
-int chip_i2c_xfer(const int port,
-		  const uint16_t addr_flags,
-		  const uint8_t *out, int out_size,
-		  uint8_t *in, int in_size, int flags);
+int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out,
+		  int out_size, uint8_t *in, int in_size, int flags);
 
 /**
  * Chip level function to set bus speed.
diff --git a/include/i8042_protocol.h b/include/i8042_protocol.h
index 7e554fc03e..23f500da17 100644
--- a/include/i8042_protocol.h
+++ b/include/i8042_protocol.h
@@ -1,8 +1,12 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
- * i8042 keyboard protocol constants
+ * i8042 keyboard protocol constants.
+ *
+ * See the IBM PS/2 Hardware Interface Technical Reference Manual
+ *
+ * https://archive.org/details/ps-2-hardware-interface-technical-reference-ocr/PS2HardwareInterfaceTechnicalReference-OCR/page/n371/mode/1up
  */
 
 #ifndef __CROS_EC_I8042_PROTOCOL_H
@@ -10,83 +14,52 @@
 
 /* Some commands appear more than once.  Why? */
 
-/* port 0x60 */
-#define I8042_CMD_MOUSE_1_1     0xe6
-#define I8042_CMD_MOUSE_2_1     0xe7
-#define I8042_CMD_MOUSE_RES     0xe8
-#define I8042_CMD_OK_GETID      0xe8
-#define I8042_CMD_GET_MOUSE     0xe9
-#define I8042_CMD_EX_ENABLE     0xea
-#define I8042_CMD_EX_SETLEDS    0xeb
-#define I8042_CMD_SETLEDS       0xed
-#define I8042_CMD_DIAG_ECHO     0xee
-#define I8042_CMD_GSCANSET      0xf0
-#define I8042_CMD_SSCANSET      0xf0
-#define I8042_CMD_GETID         0xf2
-#define I8042_CMD_SETREP        0xf3
-#define I8042_CMD_ENABLE        0xf4
-#define I8042_CMD_RESET_DIS     0xf5
-#define I8042_CMD_RESET_DEF     0xf6
-#define I8042_CMD_ALL_TYPEM     0xf7
-#define I8042_CMD_SETALL_MB     0xf8
-#define I8042_CMD_SETALL_MBR    0xfa
-#define I8042_CMD_SET_A_KEY_T   0xfb
-#define I8042_CMD_SET_A_KEY_MR  0xfc
-#define I8042_CMD_SET_A_KEY_M   0xfd
-#define I8042_CMD_RESET         0xff
-#define I8042_CMD_RESEND        0xfe
-
 /* port 0x64 */
-#define I8042_READ_CMD_BYTE     0x20
-#define I8042_READ_CTL_RAM      0x21
-#define I8042_READ_CTL_RAM_END  0x3f
-#define I8042_WRITE_CMD_BYTE    0x60  /* expect a byte on port 0x60 */
-#define I8042_WRITE_CTL_RAM     0x61
+#define I8042_READ_CMD_BYTE 0x20
+#define I8042_READ_CTL_RAM 0x21
+#define I8042_READ_CTL_RAM_END 0x3f
+#define I8042_WRITE_CMD_BYTE 0x60 /* expect a byte on port 0x60 */
+#define I8042_WRITE_CTL_RAM 0x61
 #define I8042_WRITE_CTL_RAM_END 0x7f
-#define I8042_ROUTE_AUX0        0x90
-#define I8042_ROUTE_AUX1        0x91
-#define I8042_ROUTE_AUX2        0x92
-#define I8042_ROUTE_AUX3        0x93
-#define I8042_ENA_PASSWORD      0xa6
-#define I8042_DIS_MOUSE         0xa7
-#define I8042_ENA_MOUSE         0xa8
-#define I8042_TEST_MOUSE        0xa9
-#define I8042_RESET_SELF_TEST   0xaa
-#define I8042_TEST_KB_PORT      0xab
-#define I8042_DIS_KB            0xad
-#define I8042_ENA_KB            0xae
-#define I8042_READ_OUTPUT_PORT  0xd0
+#define I8042_ROUTE_AUX0 0x90
+#define I8042_ROUTE_AUX1 0x91
+#define I8042_ROUTE_AUX2 0x92
+#define I8042_ROUTE_AUX3 0x93
+#define I8042_ENA_PASSWORD 0xa6
+#define I8042_DIS_MOUSE 0xa7
+#define I8042_ENA_MOUSE 0xa8
+#define I8042_TEST_MOUSE 0xa9
+#define I8042_TEST_MOUSE_NO_ERROR 0x00
+#define I8042_TEST_MOUSE_CLK_STUCK_LOW 0x01
+#define I8042_TEST_MOUSE_CLK_STUCK_HIGH 0x02
+#define I8042_TEST_MOUSE_DATA_STUCK_LOW 0x03
+#define I8042_TEST_MOUSE_DATA_STUCK_HIGH 0x04
+#define I8042_RESET_SELF_TEST 0xaa
+#define I8042_TEST_KB_PORT 0xab
+#define I8042_DIS_KB 0xad
+#define I8042_ENA_KB 0xae
+#define I8042_READ_OUTPUT_PORT 0xd0
 #define I8042_WRITE_OUTPUT_PORT 0xd1
-#define I8042_ECHO_MOUSE        0xd3  /* expect a byte on port 0x60 */
-#define I8042_SEND_TO_MOUSE     0xd4  /* expect a byte on port 0x60 */
-#define I8042_DISABLE_A20       0xdd
-#define I8042_ENABLE_A20        0xdf
-#define I8042_PULSE_START       0xf0
-#define I8042_SYSTEM_RESET      0xfe
-#define I8042_PULSE_END         0xff
+#define I8042_ECHO_MOUSE 0xd3 /* expect a byte on port 0x60 */
+#define I8042_SEND_TO_MOUSE 0xd4 /* expect a byte on port 0x60 */
+#define I8042_DISABLE_A20 0xdd
+#define I8042_ENABLE_A20 0xdf
+#define I8042_PULSE_START 0xf0
+#define I8042_SYSTEM_RESET 0xfe
+#define I8042_PULSE_END 0xff
 
 /* port 0x60 return value */
-#define I8042_RET_EMUL0         0xe0
-#define I8042_RET_EMUL1         0xe1
-#define I8042_RET_ECHO          0xee
-#define I8042_RET_RELEASE       0xf0
-#define I8042_RET_HANJA         0xf1
-#define I8042_RET_HANGEUL       0xf2
-#define I8042_RET_ACK           0xfa
-#define I8042_RET_TEST_FAIL     0xfc
-#define I8042_RET_INTERNAL_FAIL 0xfd
-#define I8042_RET_NAK           0xfe
-#define I8042_RET_ERR           0xff
+#define I8042_RET_NAK 0xfe
 
 /* port 64 - command byte bits */
-#define I8042_XLATE             BIT(6)
-#define I8042_AUX_DIS           BIT(5)
-#define I8042_KBD_DIS           BIT(4)
-#define I8042_SYS_FLAG          BIT(2)
-#define I8042_ENIRQ12           BIT(1)
-#define I8042_ENIRQ1            BIT(0)
+#define I8042_XLATE BIT(6)
+#define I8042_AUX_DIS BIT(5)
+#define I8042_KBD_DIS BIT(4)
+#define I8042_SYS_FLAG BIT(2)
+#define I8042_ENIRQ12 BIT(1)
+#define I8042_ENIRQ1 BIT(0)
 
 /* Status Flags */
-#define I8042_AUX_DATA		BIT(5)
+#define I8042_AUX_DATA BIT(5)
 
 #endif /* __CROS_EC_I8042_PROTOCOL_H */
diff --git a/include/inductive_charging.h b/include/inductive_charging.h
index 5c44e410aa..d4d1dd4d71 100644
--- a/include/inductive_charging.h
+++ b/include/inductive_charging.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/init_rom.h b/include/init_rom.h
index 84fe53d4ff..79a683752b 100644
--- a/include/init_rom.h
+++ b/include/init_rom.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/ioexpander.h b/include/ioexpander.h
index 21d7034303..9aff67dfaf 100644
--- a/include/ioexpander.h
+++ b/include/ioexpander.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,7 +11,7 @@
 #define ioex_signal gpio_signal
 #include "gpio.h"
 #else
-enum ioex_signal;	/* from gpio_signal.h */
+enum ioex_signal; /* from gpio_signal.h */
 #endif
 
 /* IO expander signal definition structure */
@@ -34,11 +34,11 @@ struct ioex_info {
 
 /* Signal information from board.c.  Must match order from enum ioex_signal. */
 extern const struct ioex_info ioex_list[];
-extern void (* const ioex_irq_handlers[])(enum ioex_signal signal);
+extern void (*const ioex_irq_handlers[])(enum ioex_signal signal);
 extern const int ioex_ih_count;
 
 /* Get ioex_info structure for specified signal */
-#define IOEX_GET_INFO(signal) (ioex_list + (signal) - IOEX_SIGNAL_START)
+#define IOEX_GET_INFO(signal) (ioex_list + (signal)-IOEX_SIGNAL_START)
 
 struct ioexpander_drv {
 	/* Initialize IO expander chip/driver */
@@ -60,9 +60,9 @@ struct ioexpander_drv {
 };
 
 /* IO expander default init disabled. No I2C communication will be attempted. */
-#define IOEX_FLAGS_DEFAULT_INIT_DISABLED	BIT(0)
+#define IOEX_FLAGS_DEFAULT_INIT_DISABLED BIT(0)
 /* IO Expander has been initialized */
-#define IOEX_FLAGS_INITIALIZED	BIT(1)
+#define IOEX_FLAGS_INITIALIZED BIT(1)
 
 /*
  * BITS 24 to 31 are used by io-expander drivers that need to control multiple
diff --git a/include/kasa.h b/include/kasa.h
index 6157b5632d..06e5c29dbe 100644
--- a/include/kasa.h
+++ b/include/kasa.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/keyboard_8042.h b/include/keyboard_8042.h
index 6826eb98ac..34c98c2a38 100644
--- a/include/keyboard_8042.h
+++ b/include/keyboard_8042.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -59,4 +59,4 @@ void send_aux_data_to_host_interrupt(uint8_t data);
  */
 void send_aux_data_to_device(uint8_t data);
 
-#endif  /* __CROS_EC_KEYBOARD_8042_H */
+#endif /* __CROS_EC_KEYBOARD_8042_H */
diff --git a/include/keyboard_8042_sharedlib.h b/include/keyboard_8042_sharedlib.h
index e4a2e9a77f..bd7a7b5ec7 100644
--- a/include/keyboard_8042_sharedlib.h
+++ b/include/keyboard_8042_sharedlib.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -47,42 +47,42 @@ extern const uint8_t scancode_translate_table[];
 extern uint8_t scancode_translate_set2_to_1(uint8_t code);
 
 #ifdef CONFIG_KEYBOARD_DEBUG
-#define KEYCAP_LONG_LABEL_BIT   (0x80)
-#define KEYCAP_LONG_LABEL_INDEX_BITMASK		(~KEYCAP_LONG_LABEL_BIT)
+#define KEYCAP_LONG_LABEL_BIT (0x80)
+#define KEYCAP_LONG_LABEL_INDEX_BITMASK (~KEYCAP_LONG_LABEL_BIT)
 
 enum keycap_long_label_idx {
-	KLLI_UNKNO = 0x80,		/* UNKNOWN */
-	KLLI_F1    = 0x81,		/* F1 or PREVIOUS */
-	KLLI_F2    = 0x82,		/* F2 or NEXT */
-	KLLI_F3    = 0x83,		/* F3 or REFRESH */
-	KLLI_F4    = 0x84,		/* F4 or FULL_SCREEN */
-	KLLI_F5    = 0x85,		/* F5 or OVERVIEW */
-	KLLI_F6    = 0x86,		/* F6 or DIM */
-	KLLI_F7    = 0x87,		/* F7 or BRIGHT */
-	KLLI_F8    = 0x88,		/* F8 or MUTE */
-	KLLI_F9    = 0x89,		/* F9 or VOLUME DOWN */
-	KLLI_F10   = 0x8A,		/* F10 or VOLUME UP */
-	KLLI_F11   = 0x8B,		/* F11 or POWER */
-	KLLI_F12   = 0x8C,		/* F12 or DEV TOOLS */
-	KLLI_F13   = 0x8D,		/* F13 or GOOGLE ASSISTANT */
-	KLLI_F14   = 0x8E,		/* F14 */
-	KLLI_F15   = 0x8F,		/* F15 */
-	KLLI_L_ALT = 0x90,		/* LEFT ALT */
-	KLLI_R_ALT = 0x91,		/* RIGHT ALT */
-	KLLI_L_CTR = 0x92,		/* LEFT CONTROL */
-	KLLI_R_CTR = 0x93,		/* RIGHT CONTROL */
-	KLLI_L_SHT = 0x94,		/* LEFT SHIFT */
-	KLLI_R_SHT = 0x95,		/* RIGHT SHIFT */
-	KLLI_ENTER = 0x96,		/* ENTER */
-	KLLI_SPACE = 0x97,		/* SPACE */
-	KLLI_B_SPC = 0x98,		/* BACk SPACE*/
-	KLLI_TAB   = 0x99,		/* TAB */
-	KLLI_SEARC = 0x9A,		/* SEARCH */
-	KLLI_LEFT  = 0x9B,		/* LEFT ARROW */
-	KLLI_RIGHT = 0x9C,		/* RIGHT ARROW */
-	KLLI_DOWN  = 0x9D,		/* DOWN ARROW */
-	KLLI_UP    = 0x9E,		/* UP ARROW */
-	KLLI_ESC   = 0x9F,		/* ESCAPE */
+	KLLI_UNKNO = 0x80, /* UNKNOWN */
+	KLLI_F1 = 0x81, /* F1 or PREVIOUS */
+	KLLI_F2 = 0x82, /* F2 or NEXT */
+	KLLI_F3 = 0x83, /* F3 or REFRESH */
+	KLLI_F4 = 0x84, /* F4 or FULL_SCREEN */
+	KLLI_F5 = 0x85, /* F5 or OVERVIEW */
+	KLLI_F6 = 0x86, /* F6 or DIM */
+	KLLI_F7 = 0x87, /* F7 or BRIGHT */
+	KLLI_F8 = 0x88, /* F8 or MUTE */
+	KLLI_F9 = 0x89, /* F9 or VOLUME DOWN */
+	KLLI_F10 = 0x8A, /* F10 or VOLUME UP */
+	KLLI_F11 = 0x8B, /* F11 or POWER */
+	KLLI_F12 = 0x8C, /* F12 or DEV TOOLS */
+	KLLI_F13 = 0x8D, /* F13 or GOOGLE ASSISTANT */
+	KLLI_F14 = 0x8E, /* F14 */
+	KLLI_F15 = 0x8F, /* F15 */
+	KLLI_L_ALT = 0x90, /* LEFT ALT */
+	KLLI_R_ALT = 0x91, /* RIGHT ALT */
+	KLLI_L_CTR = 0x92, /* LEFT CONTROL */
+	KLLI_R_CTR = 0x93, /* RIGHT CONTROL */
+	KLLI_L_SHT = 0x94, /* LEFT SHIFT */
+	KLLI_R_SHT = 0x95, /* RIGHT SHIFT */
+	KLLI_ENTER = 0x96, /* ENTER */
+	KLLI_SPACE = 0x97, /* SPACE */
+	KLLI_B_SPC = 0x98, /* BACk SPACE*/
+	KLLI_TAB = 0x99, /* TAB */
+	KLLI_SEARC = 0x9A, /* SEARCH */
+	KLLI_LEFT = 0x9B, /* LEFT ARROW */
+	KLLI_RIGHT = 0x9C, /* RIGHT ARROW */
+	KLLI_DOWN = 0x9D, /* DOWN ARROW */
+	KLLI_UP = 0x9E, /* UP ARROW */
+	KLLI_ESC = 0x9F, /* ESCAPE */
 	KLLI_MAX
 };
 
@@ -127,41 +127,41 @@ enum scancode_values {
 	SCANCODE_B = 0x0032,
 	SCANCODE_T = 0x002c,
 
-	SCANCODE_F1 = 0x0005,	/* Translates to 3b in codeset 1 */
-	SCANCODE_F2 = 0x0006,	/* Translates to 3c in codeset 1 */
-	SCANCODE_F3 = 0x0004,	/* Translates to 3d in codeset 1 */
-	SCANCODE_F4 = 0x000c,	/* Translates to 3e in codeset 1 */
-	SCANCODE_F5 = 0x0003,	/* Translates to 3f in codeset 1 */
-	SCANCODE_F6 = 0x000b,	/* Translates to 40 in codeset 1 */
-	SCANCODE_F7 = 0x0083,	/* Translates to 41 in codeset 1 */
-	SCANCODE_F8 = 0x000a,	/* Translates to 42 in codeset 1 */
-	SCANCODE_F9 = 0x0001,	/* Translates to 43 in codeset 1 */
-	SCANCODE_F10 = 0x0009,	/* Translates to 44 in codeset 1 */
-	SCANCODE_F11 = 0x0078,	/* Translates to 57 in codeset 1 */
-	SCANCODE_F12 = 0x0007,	/* Translates to 58 in codeset 1 */
-	SCANCODE_F13 = 0x000f,	/* Translates to 59 in codeset 1 */
-	SCANCODE_F14 = 0x0017,	/* Translates to 5a in codeset 1 */
-	SCANCODE_F15 = 0x001f,	/* Translates to 5b in codeset 1 */
-
-	SCANCODE_BACK =	0xe038,			/* e06a in codeset 1 */
-	SCANCODE_REFRESH = 0xe020,		/* e067 in codeset 1 */
-	SCANCODE_FORWARD = 0xe030,		/* e069 in codeset 1 */
-	SCANCODE_FULLSCREEN = 0xe01d,		/* e011 in codeset 1 */
-	SCANCODE_OVERVIEW = 0xe024,		/* e012 in codeset 1 */
-	SCANCODE_SNAPSHOT = 0xe02d,		/* e013 in codeset 1 */
-	SCANCODE_BRIGHTNESS_DOWN = 0xe02c,	/* e014 in codeset 1 */
-	SCANCODE_BRIGHTNESS_UP = 0xe035,	/* e015 in codeset 1 */
-	SCANCODE_PRIVACY_SCRN_TOGGLE = 0xe03c,	/* e016 in codeset 1 */
-	SCANCODE_VOLUME_MUTE = 0xe023,		/* e020 in codeset 1 */
-	SCANCODE_VOLUME_DOWN = 0xe021,		/* e02e in codeset 1 */
-	SCANCODE_VOLUME_UP = 0xe032,		/* e030 in codeset 1 */
-	SCANCODE_KBD_BKLIGHT_DOWN = 0xe043,	/* e017 in codeset 1 */
-	SCANCODE_KBD_BKLIGHT_UP = 0xe044,	/* e018 in codeset 1 */
-	SCANCODE_KBD_BKLIGHT_TOGGLE = 0xe01c,	/* e01e in codeset 1 */
-	SCANCODE_NEXT_TRACK = 0xe04d,		/* e019 in codeset 1 */
-	SCANCODE_PREV_TRACK = 0xe015,		/* e010 in codeset 1 */
-	SCANCODE_PLAY_PAUSE = 0xe054,		/* e01a in codeset 1 */
-	SCANCODE_MICMUTE = 0xe05b,		/* e01b in codeset 1 */
+	SCANCODE_F1 = 0x0005, /* Translates to 3b in codeset 1 */
+	SCANCODE_F2 = 0x0006, /* Translates to 3c in codeset 1 */
+	SCANCODE_F3 = 0x0004, /* Translates to 3d in codeset 1 */
+	SCANCODE_F4 = 0x000c, /* Translates to 3e in codeset 1 */
+	SCANCODE_F5 = 0x0003, /* Translates to 3f in codeset 1 */
+	SCANCODE_F6 = 0x000b, /* Translates to 40 in codeset 1 */
+	SCANCODE_F7 = 0x0083, /* Translates to 41 in codeset 1 */
+	SCANCODE_F8 = 0x000a, /* Translates to 42 in codeset 1 */
+	SCANCODE_F9 = 0x0001, /* Translates to 43 in codeset 1 */
+	SCANCODE_F10 = 0x0009, /* Translates to 44 in codeset 1 */
+	SCANCODE_F11 = 0x0078, /* Translates to 57 in codeset 1 */
+	SCANCODE_F12 = 0x0007, /* Translates to 58 in codeset 1 */
+	SCANCODE_F13 = 0x000f, /* Translates to 59 in codeset 1 */
+	SCANCODE_F14 = 0x0017, /* Translates to 5a in codeset 1 */
+	SCANCODE_F15 = 0x001f, /* Translates to 5b in codeset 1 */
+
+	SCANCODE_BACK = 0xe038, /* e06a in codeset 1 */
+	SCANCODE_REFRESH = 0xe020, /* e067 in codeset 1 */
+	SCANCODE_FORWARD = 0xe030, /* e069 in codeset 1 */
+	SCANCODE_FULLSCREEN = 0xe01d, /* e011 in codeset 1 */
+	SCANCODE_OVERVIEW = 0xe024, /* e012 in codeset 1 */
+	SCANCODE_SNAPSHOT = 0xe02d, /* e013 in codeset 1 */
+	SCANCODE_BRIGHTNESS_DOWN = 0xe02c, /* e014 in codeset 1 */
+	SCANCODE_BRIGHTNESS_UP = 0xe035, /* e015 in codeset 1 */
+	SCANCODE_PRIVACY_SCRN_TOGGLE = 0xe03c, /* e016 in codeset 1 */
+	SCANCODE_VOLUME_MUTE = 0xe023, /* e020 in codeset 1 */
+	SCANCODE_VOLUME_DOWN = 0xe021, /* e02e in codeset 1 */
+	SCANCODE_VOLUME_UP = 0xe032, /* e030 in codeset 1 */
+	SCANCODE_KBD_BKLIGHT_DOWN = 0xe043, /* e017 in codeset 1 */
+	SCANCODE_KBD_BKLIGHT_UP = 0xe044, /* e018 in codeset 1 */
+	SCANCODE_KBD_BKLIGHT_TOGGLE = 0xe01c, /* e01e in codeset 1 */
+	SCANCODE_NEXT_TRACK = 0xe04d, /* e019 in codeset 1 */
+	SCANCODE_PREV_TRACK = 0xe015, /* e010 in codeset 1 */
+	SCANCODE_PLAY_PAUSE = 0xe054, /* e01a in codeset 1 */
+	SCANCODE_MICMUTE = 0xe05b, /* e01b in codeset 1 */
 
 	SCANCODE_UP = 0xe075,
 	SCANCODE_DOWN = 0xe072,
@@ -173,7 +173,7 @@ enum scancode_values {
 	SCANCODE_LEFT_ALT = 0x0011,
 	SCANCODE_RIGHT_ALT = 0xe011,
 
-	SCANCODE_LEFT_WIN = 0xe01f,  /* Also known as GUI or Super key. */
+	SCANCODE_LEFT_WIN = 0xe01f, /* Also known as GUI or Super key. */
 	SCANCODE_RIGHT_WIN = 0xe027,
 	SCANCODE_MENU = 0xe02f,
 
diff --git a/include/keyboard_backlight.h b/include/keyboard_backlight.h
index 194bec66f4..cf68805235 100644
--- a/include/keyboard_backlight.h
+++ b/include/keyboard_backlight.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -94,4 +94,16 @@ int kblight_register(const struct kblight_drv *drv);
 
 extern const struct kblight_drv kblight_pwm;
 
+#ifdef TEST_BUILD
+/**
+ * @brief Get internal backlight enabled state. The value reported by
+ *        kblight_get_enabled() can be outdated due to a deferred function call
+ *        being required to update it. Using this function in tests improves
+ *        reliability and reduces the need to sleep.
+ *
+ * @return uint8_t 0 if disabled, 1 otherwise.
+ */
+uint8_t kblight_get_current_enable(void);
+#endif /* TEST_BUILD */
+
 #endif /* __CROS_EC_KEYBOARD_BACKLIGHT_H */
diff --git a/include/keyboard_config.h b/include/keyboard_config.h
index 2e6a6eb80d..afb69bf141 100644
--- a/include/keyboard_config.h
+++ b/include/keyboard_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,8 +20,8 @@
 #endif
 
 /* Keyboard matrix is 13 (or 15 with keypad) output columns x 8 input rows */
-#define KEYBOARD_COLS_WITH_KEYPAD	15
-#define KEYBOARD_COLS_NO_KEYPAD		13
+#define KEYBOARD_COLS_WITH_KEYPAD 15
+#define KEYBOARD_COLS_NO_KEYPAD 13
 
 /*
  * KEYBOARD_COLS_MAX has the build time column size. It's used to allocate
@@ -44,59 +44,59 @@ extern uint8_t keyboard_cols;
 #define KEYBOARD_ROW_TO_MASK(r) (1 << (r))
 
 /* Columns and masks for keys we particularly care about */
-#define KEYBOARD_COL_DOWN	11
-#define KEYBOARD_ROW_DOWN	6
-#define KEYBOARD_MASK_DOWN	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_DOWN)
-#define KEYBOARD_COL_ESC	1
-#define KEYBOARD_ROW_ESC	1
-#define KEYBOARD_MASK_ESC	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_ESC)
-#define KEYBOARD_COL_KEY_H	6
-#define KEYBOARD_ROW_KEY_H	1
-#define KEYBOARD_MASK_KEY_H	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_H)
-#define KEYBOARD_COL_KEY_R	3
-#define KEYBOARD_ROW_KEY_R	7
-#define KEYBOARD_MASK_KEY_R	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_R)
-#define KEYBOARD_COL_LEFT_ALT	10
-#define KEYBOARD_ROW_LEFT_ALT	6
-#define KEYBOARD_MASK_LEFT_ALT	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_ALT)
-#define KEYBOARD_COL_REFRESH	2
+#define KEYBOARD_COL_DOWN 11
+#define KEYBOARD_ROW_DOWN 6
+#define KEYBOARD_MASK_DOWN KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_DOWN)
+#define KEYBOARD_COL_ESC 1
+#define KEYBOARD_ROW_ESC 1
+#define KEYBOARD_MASK_ESC KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_ESC)
+#define KEYBOARD_COL_KEY_H 6
+#define KEYBOARD_ROW_KEY_H 1
+#define KEYBOARD_MASK_KEY_H KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_H)
+#define KEYBOARD_COL_KEY_R 3
+#define KEYBOARD_ROW_KEY_R 7
+#define KEYBOARD_MASK_KEY_R KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_R)
+#define KEYBOARD_COL_LEFT_ALT 10
+#define KEYBOARD_ROW_LEFT_ALT 6
+#define KEYBOARD_MASK_LEFT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_ALT)
+#define KEYBOARD_COL_REFRESH 2
 #ifdef CONFIG_KEYBOARD_REFRESH_ROW3
-#define KEYBOARD_ROW_REFRESH	3
+#define KEYBOARD_ROW_REFRESH 3
 #else
-#define KEYBOARD_ROW_REFRESH	2
+#define KEYBOARD_ROW_REFRESH 2
 #endif
-#define KEYBOARD_MASK_REFRESH	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_REFRESH)
-#define KEYBOARD_COL_RIGHT_ALT	10
-#define KEYBOARD_ROW_RIGHT_ALT	0
-#define KEYBOARD_MASK_RIGHT_ALT	KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_ALT)
-#define KEYBOARD_DEFAULT_COL_VOL_UP	4
-#define KEYBOARD_DEFAULT_ROW_VOL_UP	0
-#define KEYBOARD_COL_LEFT_CTRL  0
-#define KEYBOARD_ROW_LEFT_CTRL  2
+#define KEYBOARD_MASK_REFRESH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_REFRESH)
+#define KEYBOARD_COL_RIGHT_ALT 10
+#define KEYBOARD_ROW_RIGHT_ALT 0
+#define KEYBOARD_MASK_RIGHT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_ALT)
+#define KEYBOARD_DEFAULT_COL_VOL_UP 4
+#define KEYBOARD_DEFAULT_ROW_VOL_UP 0
+#define KEYBOARD_COL_LEFT_CTRL 0
+#define KEYBOARD_ROW_LEFT_CTRL 2
 #define KEYBOARD_MASK_LEFT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_CTRL)
 #define KEYBOARD_COL_RIGHT_CTRL 0
 #define KEYBOARD_ROW_RIGHT_CTRL 4
 #define KEYBOARD_MASK_RIGHT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_CTRL)
-#define KEYBOARD_COL_SEARCH     1
-#define KEYBOARD_ROW_SEARCH     0
-#define KEYBOARD_MASK_SEARCH    KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_SEARCH)
-#define KEYBOARD_COL_KEY_0      8
-#define KEYBOARD_ROW_KEY_0      6
-#define KEYBOARD_MASK_KEY_0     KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_0)
-#define KEYBOARD_COL_KEY_1      1
-#define KEYBOARD_ROW_KEY_1      6
-#define KEYBOARD_MASK_KEY_1     KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_1)
-#define KEYBOARD_COL_KEY_2      4
-#define KEYBOARD_ROW_KEY_2      6
-#define KEYBOARD_MASK_KEY_2     KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_2)
+#define KEYBOARD_COL_SEARCH 1
+#define KEYBOARD_ROW_SEARCH 0
+#define KEYBOARD_MASK_SEARCH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_SEARCH)
+#define KEYBOARD_COL_KEY_0 8
+#define KEYBOARD_ROW_KEY_0 6
+#define KEYBOARD_MASK_KEY_0 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_0)
+#define KEYBOARD_COL_KEY_1 1
+#define KEYBOARD_ROW_KEY_1 6
+#define KEYBOARD_MASK_KEY_1 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_1)
+#define KEYBOARD_COL_KEY_2 4
+#define KEYBOARD_ROW_KEY_2 6
+#define KEYBOARD_MASK_KEY_2 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_2)
 #define KEYBOARD_COL_LEFT_SHIFT 7
 #define KEYBOARD_ROW_LEFT_SHIFT 5
 #define KEYBOARD_MASK_LEFT_SHIFT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_SHIFT)
 #ifdef CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2
-#define KEYBOARD_MASK_PWRBTN	KEYBOARD_ROW_TO_MASK(2)
+#define KEYBOARD_MASK_PWRBTN KEYBOARD_ROW_TO_MASK(2)
 #elif defined(CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI3)
-#define KEYBOARD_MASK_PWRBTN	KEYBOARD_ROW_TO_MASK(3)
+#define KEYBOARD_MASK_PWRBTN KEYBOARD_ROW_TO_MASK(3)
 #endif
 
 #endif /* CONFIG_KEYBOARD_CUSTOMIZATION */
-#endif  /* __CROS_EC_KEYBOARD_CONFIG_H */
+#endif /* __CROS_EC_KEYBOARD_CONFIG_H */
diff --git a/include/keyboard_mkbp.h b/include/keyboard_mkbp.h
index 03e84550a7..ff2344937b 100644
--- a/include/keyboard_mkbp.h
+++ b/include/keyboard_mkbp.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -9,6 +9,7 @@
 #define __CROS_EC_KEYBOARD_MKBP_H
 
 #include "common.h"
+#include "ec_commands.h"
 #include "keyboard_config.h"
 
 /**
@@ -18,4 +19,8 @@
  */
 int mkbp_keyboard_add(const uint8_t *buffp);
 
-#endif  /* __CROS_EC_KEYBOARD_MKBP_H */
+#ifdef TEST_BUILD
+void get_keyscan_config(struct ec_mkbp_config *dst);
+#endif
+
+#endif /* __CROS_EC_KEYBOARD_MKBP_H */
diff --git a/include/keyboard_protocol.h b/include/keyboard_protocol.h
index 362364ced4..7b9006fcc0 100644
--- a/include/keyboard_protocol.h
+++ b/include/keyboard_protocol.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -39,7 +39,9 @@ void keyboard_update_button(enum keyboard_button_type button, int is_pressed);
 /* MKBP protocol takes the whole keyboard matrix, and does not care about
  * individual key presses.
  */
-static inline void keyboard_state_changed(int row, int col, int is_pressed) {}
+static inline void keyboard_state_changed(int row, int col, int is_pressed)
+{
+}
 #else
 /**
  * Called by keyboard scan code once any key state change (after de-bounce),
@@ -60,7 +62,7 @@ int board_has_keyboard_backlight(void);
  * to change KEYBOARD_ROW_REFRESH accordingly so that recovery mode can work on
  * the EC side of things (also see related CONFIG_KEYBOARD_REFRESH_ROW3)
  */
-__override_proto
-const struct ec_response_keybd_config *board_vivaldi_keybd_config(void);
+__override_proto const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void);
 
-#endif  /* __CROS_EC_KEYBOARD_PROTOCOL_H */
+#endif /* __CROS_EC_KEYBOARD_PROTOCOL_H */
diff --git a/include/keyboard_raw.h b/include/keyboard_raw.h
index 6989ae36a7..dca7b3c79a 100644
--- a/include/keyboard_raw.h
+++ b/include/keyboard_raw.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,14 +11,14 @@
 #ifndef __CROS_EC_KEYBOARD_RAW_H
 #define __CROS_EC_KEYBOARD_RAW_H
 
-#include "assert.h"
+#include "builtin/assert.h"
 #include "common.h"
 #include "gpio_signal.h"
 #include "keyboard_config.h"
 
 /* Column values for keyboard_raw_drive_column() */
 enum keyboard_column_index {
-	KEYBOARD_COLUMN_ALL = -2,  /* Drive all columns */
+	KEYBOARD_COLUMN_ALL = -2, /* Drive all columns */
 	KEYBOARD_COLUMN_NONE = -1, /* Drive no columns (tri-state all) */
 	/* 0 ~ KEYBOARD_COLS_MAX-1 for the corresponding column */
 };
@@ -70,7 +70,9 @@ void keyboard_raw_enable_interrupt(int enable);
 void keyboard_raw_gpio_interrupt(enum gpio_signal signal);
 
 #else
-static inline void keyboard_raw_gpio_interrupt(enum gpio_signal signal) { }
+static inline void keyboard_raw_gpio_interrupt(enum gpio_signal signal)
+{
+}
 #endif /* !HAS_TASK_KEYSCAN */
 
 /**
@@ -89,11 +91,13 @@ int keyboard_factory_test_scan(void);
  */
 int keyboard_raw_is_input_low(int port, int id);
 
-static inline int keyboard_raw_get_cols(void) {
+static inline int keyboard_raw_get_cols(void)
+{
 	return keyboard_cols;
 }
 
-static inline void keyboard_raw_set_cols(int cols) {
+static inline void keyboard_raw_set_cols(int cols)
+{
 #ifdef CONFIG_KEYBOARD_LANGUAGE_ID
 	/* Keyboard ID is probably encoded right after the last column. Scanner
 	 * would read keyboard ID if the column size is decreased. */
@@ -118,4 +122,4 @@ static inline void keyboard_raw_set_cols(int cols) {
 void board_keyboard_drive_col(int col);
 #endif
 
-#endif  /* __CROS_EC_KEYBOARD_RAW_H */
+#endif /* __CROS_EC_KEYBOARD_RAW_H */
diff --git a/include/keyboard_scan.h b/include/keyboard_scan.h
index 1e164bca37..e235a47c1c 100644
--- a/include/keyboard_scan.h
+++ b/include/keyboard_scan.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -38,6 +38,12 @@ struct keyboard_scan_config {
 #endif
 };
 
+/* Boot key list.  Must be in same order as enum boot_key. */
+struct boot_key_entry {
+	uint8_t col;
+	uint8_t row;
+};
+
 /**
  * Initializes the module.
  */
@@ -89,10 +95,10 @@ const uint8_t *keyboard_scan_get_state(void);
 
 enum kb_scan_disable_masks {
 	/* Reasons why keyboard scanning should be disabled */
-	KB_SCAN_DISABLE_LID_CLOSED   = (1<<0),
-	KB_SCAN_DISABLE_POWER_BUTTON = (1<<1),
-	KB_SCAN_DISABLE_LID_ANGLE    = (1<<2),
-	KB_SCAN_DISABLE_USB_SUSPENDED = (1<<3),
+	KB_SCAN_DISABLE_LID_CLOSED = (1 << 0),
+	KB_SCAN_DISABLE_POWER_BUTTON = (1 << 1),
+	KB_SCAN_DISABLE_LID_ANGLE = (1 << 2),
+	KB_SCAN_DISABLE_USB_SUSPENDED = (1 << 3),
 };
 
 #ifdef HAS_TASK_KEYSCAN
@@ -111,7 +117,9 @@ void keyboard_scan_enable(int enable, enum kb_scan_disable_masks mask);
 void clear_typematic_key(void);
 #else
 static inline void keyboard_scan_enable(int enable,
-		enum kb_scan_disable_masks mask) { }
+					enum kb_scan_disable_masks mask)
+{
+}
 #endif
 
 #ifdef CONFIG_KEYBOARD_SUPPRESS_NOISE
@@ -136,7 +144,9 @@ int keyboard_get_keyboard_id(void);
 #ifdef CONFIG_KEYBOARD_RUNTIME_KEYS
 void set_vol_up_key(uint8_t row, uint8_t col);
 #else
-static inline void set_vol_up_key(uint8_t row, uint8_t col) {}
+static inline void set_vol_up_key(uint8_t row, uint8_t col)
+{
+}
 #endif
 
 #ifdef CONFIG_KEYBOARD_FACTORY_TEST
@@ -148,5 +158,52 @@ extern const int keyboard_factory_scan_pins[][2];
 extern const int keyboard_factory_scan_pins_used;
 #endif
 
+#ifdef CONFIG_KEYBOARD_MULTIPLE
+extern struct boot_key_entry boot_key_list[3];
+
+struct keyboard_type {
+	int col_esc;
+	int row_esc;
+	int col_down;
+	int row_down;
+	int col_left_shift;
+	int row_left_shift;
+	int col_refresh;
+	int row_refresh;
+	int col_right_alt;
+	int row_right_alt;
+	int col_left_alt;
+	int row_left_alt;
+	int col_key_r;
+	int row_key_r;
+	int col_key_h;
+	int row_key_h;
+};
+
+extern struct keyboard_type key_typ;
+#endif
+
+#ifdef TEST_BUILD
+/**
+ * @brief Get the value of print_state_changes
+ *
+ * @return non-zero if state change printing is enabled, zero if not.
+ */
+__test_only int keyboard_scan_get_print_state_changes(void);
+
+/**
+ * @brief Forcibly set the value of print_state_changes
+ *
+ * @param val Value to set
+ */
+__test_only void keyboard_scan_set_print_state_changes(int val);
+
+/**
+ * @brief Checks if keyboard scanning is currently enabled.
+ *
+ * @return int non-zero if enabled, zero otherwise.
+ */
+int keyboard_scan_is_enabled(void);
+#endif /* TEST_BUILD */
 
-#endif  /* __CROS_EC_KEYBOARD_SCAN_H */
+#endif /* __CROS_EC_KEYBOARD_SCAN_H */
diff --git a/include/keyboard_test.h b/include/keyboard_test.h
index 142cff5e53..be12f08372 100644
--- a/include/keyboard_test.h
+++ b/include/keyboard_test.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2013 The Chromium OS Authors. All rights reserved.
+ * Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,9 +16,9 @@
  * logic.
  */
 struct keyscan_item {
-	timestamp_t abs_time;	/* absolute timestamp to present this item */
-	uint32_t time_us;	/* time for this item relative to test start */
-	uint8_t done;		/* 1 if we managed to present this */
+	timestamp_t abs_time; /* absolute timestamp to present this item */
+	uint32_t time_us; /* time for this item relative to test start */
+	uint8_t done; /* 1 if we managed to present this */
 	uint8_t scan[KEYBOARD_COLS_MAX];
 };
 
diff --git a/include/lb_common.h b/include/lb_common.h
index 327c810cad..29f666d33b 100644
--- a/include/lb_common.h
+++ b/include/lb_common.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
+ * Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -38,4 +38,4 @@ void lb_hc_cmd_reg(const struct ec_params_lightbar *in);
  */
 int lb_power(int enabled);
 
-#endif  /* __CROS_EC_LB_COMMON_H */
+#endif /* __CROS_EC_LB_COMMON_H */
diff --git a/include/led_common.h b/include/led_common.h
index 8e9f1441f3..71c8211fec 100644
--- a/include/led_common.h
+++ b/include/led_common.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -79,8 +79,8 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness);
 void led_enable(int enable);
 
 enum ec_led_state {
-	LED_STATE_OFF   = 0,
-	LED_STATE_ON    = 1,
+	LED_STATE_OFF = 0,
+	LED_STATE_ON = 1,
 	LED_STATE_RESET = 2,
 };
 
diff --git a/include/led_onoff_states.h b/include/led_onoff_states.h
index 63955e590a..bfad06aabc 100644
--- a/include/led_onoff_states.h
+++ b/include/led_onoff_states.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,19 +10,15 @@
 
 #include "ec_commands.h"
 
-#define LED_INDEFINITE	UINT8_MAX
-#define LED_ONE_SEC	(1000 / HOOK_TICK_INTERVAL_MS)
-#define LED_OFF         EC_LED_COLOR_COUNT
+#define LED_INDEFINITE UINT8_MAX
+#define LED_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS)
+#define LED_OFF EC_LED_COLOR_COUNT
 
 /*
  * All LED states should have one phase defined,
  * and an additional phase can be defined for blinking
  */
-enum led_phase {
-	LED_PHASE_0,
-	LED_PHASE_1,
-	LED_NUM_PHASES
-};
+enum led_phase { LED_PHASE_0, LED_PHASE_1, LED_NUM_PHASES };
 
 /*
  * STATE_CHARGING_LVL_1 is when 0 <= charge_percentage < led_charge_level_1
diff --git a/include/led_pwm.h b/include/led_pwm.h
index 26a44913b8..1c8cec9ff4 100644
--- a/include/led_pwm.h
+++ b/include/led_pwm.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,20 +15,12 @@
 #ifdef CONFIG_ZEPHYR
 #define PWM_LED_NO_CHANNEL NULL
 
-/* This could really be pwm_dt_spec. */
-struct pwm_led_dt_channel {
-	const struct device *dev;
-	uint32_t channel;
-	pwm_flags_t flags;
-	uint32_t period_ns;
-};
-
 struct pwm_led {
-	const struct pwm_led_dt_channel *ch0;
-	const struct pwm_led_dt_channel *ch1;
-	const struct pwm_led_dt_channel *ch2;
+	const struct pwm_dt_spec *ch0;
+	const struct pwm_dt_spec *ch1;
+	const struct pwm_dt_spec *ch2;
 
-	void (*set_duty)(const struct pwm_led_dt_channel *ch, int percent);
+	void (*set_duty)(const struct pwm_dt_spec *pwm, int percent);
 };
 #else
 #define PWM_LED_NO_CHANNEL ((enum pwm_channel)(-1))
diff --git a/include/libsharedobjs.h b/include/libsharedobjs.h
index 3801ccaca0..ee767ff127 100644
--- a/include/libsharedobjs.h
+++ b/include/libsharedobjs.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -17,7 +17,7 @@
  * NOTE: I know that this doesn't cover all possible cases, but it will catch
  *       an obvious case.
  */
-#if (CONFIG_RO_MEM_OFF ==  CONFIG_RW_MEM_OFF)
+#if (CONFIG_RO_MEM_OFF == CONFIG_RW_MEM_OFF)
 #error "The shared library is NOT compatible with this EC."
 #endif
 
@@ -28,12 +28,12 @@
  */
 #undef SHAREDLIB
 #ifdef SHAREDLIB_IMAGE
-#define SHAREDLIB(...) __attribute__ ((section(".roshared"))) __VA_ARGS__
+#define SHAREDLIB(...) __attribute__((section(".roshared"))) __VA_ARGS__
 #else /* !defined(SHAREDLIB_IMAGE) */
 #define SHAREDLIB(...)
 #endif /* defined(SHAREDLIB_IMAGE) */
 #define SHAREDLIB_FUNC(...) \
-	extern __VA_ARGS__ __attribute__ ((section(".roshared.text")))
+	extern __VA_ARGS__ __attribute__((section(".roshared.text")))
 
 #else /* !defined(CONFIG_SHAREDLIB) */
 
diff --git a/include/lid_angle.h b/include/lid_angle.h
index 24275db313..8836c91238 100644
--- a/include/lid_angle.h
+++ b/include/lid_angle.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -32,4 +32,4 @@ void lid_angle_set_wake_angle(int ang);
  */
 __override_proto void lid_angle_peripheral_enable(int enable);
 
-#endif  /* __CROS_EC_LID_ANGLE_H */
+#endif /* __CROS_EC_LID_ANGLE_H */
diff --git a/include/lid_switch.h b/include/lid_switch.h
index 93d093a21f..3d639b5782 100644
--- a/include/lid_switch.h
+++ b/include/lid_switch.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,7 +14,7 @@
 /**
  * Debounce time for lid switch
  */
-#define LID_DEBOUNCE_US    (30 * MSEC)
+#define LID_DEBOUNCE_US (30 * MSEC)
 
 /**
  * Return non-zero if lid is open.
@@ -37,4 +37,4 @@ void lid_interrupt(enum gpio_signal signal);
  */
 void enable_lid_detect(bool enable);
 
-#endif  /* __CROS_EC_LID_SWITCH_H */
+#endif /* __CROS_EC_LID_SWITCH_H */
diff --git a/include/lightbar.h b/include/lightbar.h
index 2c8c143922..aff5e6fc68 100644
--- a/include/lightbar.h
+++ b/include/lightbar.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,26 +13,13 @@
 /* Define the types of sequences */
 #define LBMSG(state) LIGHTBAR_##state
 #include "lightbar_msg_list.h"
-enum lightbar_sequence {
-	LIGHTBAR_MSG_LIST
-	LIGHTBAR_NUM_SEQUENCES
-};
+enum lightbar_sequence { LIGHTBAR_MSG_LIST LIGHTBAR_NUM_SEQUENCES };
 #undef LBMSG
 
 /* Bytecode field constants */
-enum lb_color {
-	LB_COL_RED,
-	LB_COL_GREEN,
-	LB_COL_BLUE,
-	LB_COL_ALL
-};
+enum lb_color { LB_COL_RED, LB_COL_GREEN, LB_COL_BLUE, LB_COL_ALL };
 
-enum lb_control {
-	LB_CONT_COLOR0,
-	LB_CONT_COLOR1,
-	LB_CONT_PHASE,
-	LB_CONT_MAX
-};
+enum lb_control { LB_CONT_COLOR0, LB_CONT_COLOR1, LB_CONT_PHASE, LB_CONT_MAX };
 
 #ifdef CONFIG_ALS_LIGHTBAR_DIMMING
 /*
@@ -67,4 +54,4 @@ extern void demo_battery_level(int inc);
 extern void demo_is_charging(int ischarge);
 extern void demo_brightness(int inc);
 extern void demo_tap(void);
-#endif  /* __CROS_EC_LIGHTBAR_H */
+#endif /* __CROS_EC_LIGHTBAR_H */
diff --git a/include/lightbar_msg_list.h b/include/lightbar_msg_list.h
index 15c7d14bf6..be87913c83 100644
--- a/include/lightbar_msg_list.h
+++ b/include/lightbar_msg_list.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -6,17 +6,17 @@
  * we can automatically derive the correct constants, functions, and message
  * types.
  */
-#define LIGHTBAR_MSG_LIST                       \
-	LBMSG(ERROR),		/* 0 */		\
-	LBMSG(S5),		/* 1 */		\
-	LBMSG(S3),		/* 2 */		\
-	LBMSG(S0),		/* 3 */		\
-	LBMSG(S5S3),		/* 4 */		\
-	LBMSG(S3S0),		/* 5 */		\
-	LBMSG(S0S3),		/* 6 */		\
-	LBMSG(S3S5),		/* 7 */		\
-	LBMSG(STOP),		/* 8 */		\
-	LBMSG(RUN),		/* 9 */		\
-	LBMSG(KONAMI),		/* A */         \
-	LBMSG(TAP),		/* B */		\
-	LBMSG(PROGRAM),		/* C */
+#define LIGHTBAR_MSG_LIST              \
+	LBMSG(ERROR), /* 0 */          \
+		LBMSG(S5), /* 1 */     \
+		LBMSG(S3), /* 2 */     \
+		LBMSG(S0), /* 3 */     \
+		LBMSG(S5S3), /* 4 */   \
+		LBMSG(S3S0), /* 5 */   \
+		LBMSG(S0S3), /* 6 */   \
+		LBMSG(S3S5), /* 7 */   \
+		LBMSG(STOP), /* 8 */   \
+		LBMSG(RUN), /* 9 */    \
+		LBMSG(KONAMI), /* A */ \
+		LBMSG(TAP), /* B */    \
+		LBMSG(PROGRAM), /* C */
diff --git a/include/lightbar_opcode_list.h b/include/lightbar_opcode_list.h
index 5d75feb459..c8feae682f 100644
--- a/include/lightbar_opcode_list.h
+++ b/include/lightbar_opcode_list.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -6,21 +6,21 @@
  */
 
 /* 	   NAME			OPERAND BYTES	MNEMONIC*/
-#define LIGHTBAR_OPCODE_TABLE					\
-	OP(ON,			0,		"on"		)\
-	OP(OFF,			0,		"off"		)\
-	OP(JUMP,		1,		"jump"		)\
-	OP(JUMP_BATTERY,	2,		"jbat"		)\
-	OP(JUMP_IF_CHARGING,	1,		"jcharge"	)\
-	OP(SET_WAIT_DELAY,	4,		"delay.w"	)\
-	OP(SET_RAMP_DELAY,	4,		"delay.r"	)\
-	OP(WAIT,		0,		"wait"		)\
-	OP(SET_BRIGHTNESS,	1,		"bright"	)\
-	OP(SET_COLOR_SINGLE,	2,		"set.1"		)\
-	OP(SET_COLOR_RGB,	4,		"set.rgb"	)\
-	OP(GET_COLORS,		0,		"get"		)\
-	OP(SWAP_COLORS,		0,		"swap"		)\
-	OP(RAMP_ONCE,		0,		"ramp.1"	)\
-	OP(CYCLE_ONCE,		0,		"cycle.1"	)\
-	OP(CYCLE,		0,		"cycle"		)\
-	OP(HALT,		0,		"halt"		)
+#define LIGHTBAR_OPCODE_TABLE              \
+	OP(ON, 0, "on")                    \
+	OP(OFF, 0, "off")                  \
+	OP(JUMP, 1, "jump")                \
+	OP(JUMP_BATTERY, 2, "jbat")        \
+	OP(JUMP_IF_CHARGING, 1, "jcharge") \
+	OP(SET_WAIT_DELAY, 4, "delay.w")   \
+	OP(SET_RAMP_DELAY, 4, "delay.r")   \
+	OP(WAIT, 0, "wait")                \
+	OP(SET_BRIGHTNESS, 1, "bright")    \
+	OP(SET_COLOR_SINGLE, 2, "set.1")   \
+	OP(SET_COLOR_RGB, 4, "set.rgb")    \
+	OP(GET_COLORS, 0, "get")           \
+	OP(SWAP_COLORS, 0, "swap")         \
+	OP(RAMP_ONCE, 0, "ramp.1")         \
+	OP(CYCLE_ONCE, 0, "cycle.1")       \
+	OP(CYCLE, 0, "cycle")              \
+	OP(HALT, 0, "halt")
diff --git a/include/link_defs.h b/include/link_defs.h
index 79b1a99159..ed7e9d1cfe 100644
--- a/include/link_defs.h
+++ b/include/link_defs.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -82,6 +82,8 @@ extern const struct hook_data __hooks_usb_pd_disconnect[];
 extern const struct hook_data __hooks_usb_pd_disconnect_end[];
 extern const struct hook_data __hooks_usb_pd_connect[];
 extern const struct hook_data __hooks_usb_pd_connect_end[];
+extern const struct hook_data __hooks_power_supply_change[];
+extern const struct hook_data __hooks_power_supply_change_end[];
 
 /* Deferrable functions and firing times*/
 extern const struct deferred_data __deferred_funcs[];
@@ -131,7 +133,7 @@ extern void *__dram_bss_end;
 /* Helper for special chip-specific memory sections */
 #if defined(CONFIG_CHIP_MEMORY_REGIONS) || defined(CONFIG_DRAM_BASE)
 #define __SECTION(name) __attribute__((section("." STRINGIFY(name) ".50_auto")))
-#define __SECTION_KEEP(name)                                                   \
+#define __SECTION_KEEP(name) \
 	__keep __attribute__((section("." STRINGIFY(name) ".keep.50_auto")))
 #else
 #define __SECTION(name)
@@ -146,7 +148,7 @@ extern void *__dram_bss_end;
 #endif /* __CROS_EC_LINK_DEFS_H */
 
 #ifdef CONFIG_PRESERVE_LOGS
-#define __preserved_logs(name)                                                 \
+#define __preserved_logs(name) \
 	__attribute__((section(".preserved_logs." STRINGIFY(name))))
 /* preserved_logs section. */
 extern const char __preserved_logs_start[];
diff --git a/include/lpc.h b/include/lpc.h
index 2a69cbced8..2e0a2eea74 100644
--- a/include/lpc.h
+++ b/include/lpc.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -89,6 +89,13 @@ enum lpc_host_event_type {
  */
 host_event_t lpc_get_host_events(void);
 
+#ifdef TEST_BUILD
+/**
+ * Set host events.
+ */
+void lpc_set_host_event_state(host_event_t events);
+#endif
+
 /**
  * Get host events that are set based on the type provided.
  *
@@ -162,4 +169,4 @@ void lpc_init_mask(void);
  */
 void lpc_s3_resume_clear_masks(void);
 
-#endif  /* __CROS_EC_LPC_H */
+#endif /* __CROS_EC_LPC_H */
diff --git a/include/mag_cal.h b/include/mag_cal.h
index 61b24c7da9..66281bba4e 100644
--- a/include/mag_cal.h
+++ b/include/mag_cal.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,8 +14,8 @@
 #include "kasa.h"
 
 #define MAG_CAL_MAX_SAMPLES 0xffff
-#define MAG_CAL_MIN_BATCH_WINDOW_US    (2 * SECOND)
-#define MAG_CAL_MIN_BATCH_SIZE      50      /* samples */
+#define MAG_CAL_MIN_BATCH_WINDOW_US (2 * SECOND)
+#define MAG_CAL_MIN_BATCH_SIZE 50 /* samples */
 
 struct mag_cal_t {
 	struct kasa_fit kasa_fit;
@@ -38,4 +38,4 @@ void init_mag_cal(struct mag_cal_t *moc);
  * @return    1 if a new calibration value is available, 0 otherwise.
  */
 int mag_cal_update(struct mag_cal_t *moc, const intv3_t v);
-#endif  /* __CROS_EC_MAG_CAL_H */
+#endif /* __CROS_EC_MAG_CAL_H */
diff --git a/include/mat33.h b/include/mat33.h
index fdd7e954ac..43826af1b1 100644
--- a/include/mat33.h
+++ b/include/mat33.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,6 +26,6 @@ void mat33_fp_get_eigenbasis(mat33_fp_t S, fpv3_t eigenvals,
 
 size_t mat33_fp_maxind(mat33_fp_t A, size_t k);
 
-void mat33_fp_rotate(mat33_fp_t A, fp_t c, fp_t s,
-		     size_t k, size_t l, size_t i, size_t j);
-#endif  /* __CROS_EC_MAT_33_H */
+void mat33_fp_rotate(mat33_fp_t A, fp_t c, fp_t s, size_t k, size_t l, size_t i,
+		     size_t j);
+#endif /* __CROS_EC_MAT_33_H */
diff --git a/include/mat44.h b/include/mat44.h
index 2faa093c8e..909c6e0ee7 100644
--- a/include/mat44.h
+++ b/include/mat44.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,4 +22,4 @@ void mat44_fp_swap_rows(mat44_fp_t A, const size_t i, const size_t j);
 
 void mat44_fp_solve(mat44_fp_t A, fpv4_t x, const fpv4_t b,
 		    const sizev4_t pivot);
-#endif  /* __CROS_EC_MAT_44_H */
+#endif /* __CROS_EC_MAT_44_H */
diff --git a/include/math_util.h b/include/math_util.h
index 9ee075839e..51065d2bce 100644
--- a/include/math_util.h
+++ b/include/math_util.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -40,9 +40,9 @@ typedef int64_t fp_inter_t;
 #define INT_TO_FP(x) ((fp_t)(x) << FP_BITS)
 #define FP_TO_INT(x) ((int32_t)((x) >> FP_BITS))
 /* Float to fixed-point, only for compile-time constants and unit tests */
-#define FLOAT_TO_FP(x) ((fp_t)((x) * (float)(1<<FP_BITS)))
+#define FLOAT_TO_FP(x) ((fp_t)((x) * (float)(1 << FP_BITS)))
 /* Fixed-point to float, for unit tests */
-#define FP_TO_FLOAT(x) ((float)(x) / (float)(1<<FP_BITS))
+#define FP_TO_FLOAT(x) ((float)(x) / (float)(1 << FP_BITS))
 
 #define FLT_MAX INT32_MAX
 #define FLT_MIN INT32_MIN
@@ -158,9 +158,7 @@ typedef fp_t mat33_fp_t[3][3];
 typedef int intv3_t[3];
 
 /* For vectors, define which coordinates are in which location. */
-enum {
-	X, Y, Z, W
-};
+enum { X, Y, Z, W };
 /*
  * Return absolute value of x.  Note that as a macro expansion, this may have
  * side effects if x includes function calls, which is why inline functions
@@ -194,7 +192,6 @@ void cross_product(const intv3_t v1, const intv3_t v2, intv3_t v);
  */
 void vector_scale(intv3_t v, fp_t s);
 
-
 /**
  * Find the cosine of the angle between two vectors.
  *
diff --git a/include/memory_commands.h b/include/memory_commands.h
index 91020d8920..666a6ef508 100644
--- a/include/memory_commands.h
+++ b/include/memory_commands.h
@@ -1,4 +1,4 @@
-/* Copyright 2011 The Chromium OS Authors. All rights reserved.
+/* Copyright 2011 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,4 +13,4 @@
 /* Initializes the module. */
 int memory_commands_init(void);
 
-#endif  /* __CROS_EC_MEMORY_COMMANDS_H */
+#endif /* __CROS_EC_MEMORY_COMMANDS_H */
diff --git a/include/mkbp_event.h b/include/mkbp_event.h
index d9237dd33b..d31bd82cb2 100644
--- a/include/mkbp_event.h
+++ b/include/mkbp_event.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -51,11 +51,22 @@ struct mkbp_event_source {
 #ifdef CONFIG_PLATFORM_EC_MKBP_EVENT
 #include "zephyr_mkbp_event.h"
 #else
-#define DECLARE_EVENT_SOURCE(type, func)                       \
-	const struct mkbp_event_source __keep		       \
-	__no_sanitize_address _evt_src_##type		       \
-	__attribute__((section(".rodata.evtsrcs")))            \
-		 = {type, func}
+#define DECLARE_EVENT_SOURCE(type, func)                            \
+	const struct mkbp_event_source __keep __no_sanitize_address \
+		_evt_src_##type                                     \
+		__attribute__((section(".rodata.evtsrcs"))) = { type, func }
 #endif
 
-#endif  /* __CROS_EC_MKBP_EVENT_H */
+#ifdef TEST_BUILD
+/* Allow directly raising events in unit tests */
+void activate_mkbp_with_events(uint32_t events_to_add);
+
+/**
+ * @brief Force the event bits to zero, causing the event handling code to
+ *        believe there are no pending events to service. This has no effect on
+ *        any event sources' internal queues or logic.
+ */
+__test_only void mkbp_event_clear_all(void);
+#endif /* TEST_BUILD */
+
+#endif /* __CROS_EC_MKBP_EVENT_H */
diff --git a/include/mkbp_fifo.h b/include/mkbp_fifo.h
index 347f94e2a7..408980a10b 100644
--- a/include/mkbp_fifo.h
+++ b/include/mkbp_fifo.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,10 +11,8 @@
 #include "common.h"
 #include "ec_commands.h"
 
-
 #define FIFO_DEPTH 16
 
-
 /**
  * Update the "soft" FIFO depth (size). The new depth should be less or
  * equal FIFO_DEPTH
diff --git a/include/mkbp_info.h b/include/mkbp_info.h
index 64daa52dce..61378f9c22 100644
--- a/include/mkbp_info.h
+++ b/include/mkbp_info.h
@@ -19,4 +19,9 @@
  */
 __override_proto int mkbp_support_volume_buttons(void);
 
+#ifdef TEST_BUILD
+uint32_t get_supported_buttons(void);
+uint32_t get_supported_switches(void);
+#endif /* TEST_BUILD */
+
 #endif /* __CROS_EC_MKBP_INFO_H */
diff --git a/include/mkbp_input_devices.h b/include/mkbp_input_devices.h
index 2557aab3f2..920f944fdf 100644
--- a/include/mkbp_input_devices.h
+++ b/include/mkbp_input_devices.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/mock/charge_manager_mock.h b/include/mock/charge_manager_mock.h
index 8a791f6121..afae5a19a2 100644
--- a/include/mock/charge_manager_mock.h
+++ b/include/mock/charge_manager_mock.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,7 +16,7 @@ struct mock_ctrl_charge_manager {
 };
 
 #define MOCK_CTRL_DEFAULT_CHARGE_MANAGER    \
-	((struct mock_ctrl_charge_manager) { \
+	((struct mock_ctrl_charge_manager){ \
 		.vbus_voltage_mv = 0,       \
 	})
 
diff --git a/include/mock/dp_alt_mode_mock.h b/include/mock/dp_alt_mode_mock.h
index 27811140c7..152d5d8b37 100644
--- a/include/mock/dp_alt_mode_mock.h
+++ b/include/mock/dp_alt_mode_mock.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/mock/fp_sensor_mock.h b/include/mock/fp_sensor_mock.h
index 432802348c..338a03b7e9 100644
--- a/include/mock/fp_sensor_mock.h
+++ b/include/mock/fp_sensor_mock.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -28,20 +28,21 @@ struct mock_ctrl_fp_sensor {
 	int fp_maintenance_return;
 };
 
-#define MOCK_CTRL_DEFAULT_FP_SENSOR                                    \
-(struct mock_ctrl_fp_sensor) {                                         \
-	.fp_sensor_init_return                       = EC_SUCCESS,     \
-	.fp_sensor_deinit_return                     = EC_SUCCESS,     \
-	.fp_sensor_get_info_return                   = EC_SUCCESS,     \
-	.fp_sensor_finger_status_return              = FINGER_NONE,    \
-	.fp_sensor_acquire_image_return              = 0,              \
-	.fp_sensor_acquire_image_with_mode_return    = 0,              \
-	.fp_finger_match_return    = EC_MKBP_FP_ERR_MATCH_YES_UPDATED, \
-	.fp_enrollment_begin_return                  = 0,              \
-	.fp_enrollment_finish_return                 = 0,              \
-	.fp_finger_enroll_return   = EC_MKBP_FP_ERR_ENROLL_OK,         \
-	.fp_maintenance_return			     = EC_SUCCESS      \
-}
+#define MOCK_CTRL_DEFAULT_FP_SENSOR                                         \
+	(struct mock_ctrl_fp_sensor)                                        \
+	{                                                                   \
+		.fp_sensor_init_return = EC_SUCCESS,                        \
+		.fp_sensor_deinit_return = EC_SUCCESS,                      \
+		.fp_sensor_get_info_return = EC_SUCCESS,                    \
+		.fp_sensor_finger_status_return = FINGER_NONE,              \
+		.fp_sensor_acquire_image_return = 0,                        \
+		.fp_sensor_acquire_image_with_mode_return = 0,              \
+		.fp_finger_match_return = EC_MKBP_FP_ERR_MATCH_YES_UPDATED, \
+		.fp_enrollment_begin_return = 0,                            \
+		.fp_enrollment_finish_return = 0,                           \
+		.fp_finger_enroll_return = EC_MKBP_FP_ERR_ENROLL_OK,        \
+		.fp_maintenance_return = EC_SUCCESS                         \
+	}
 
 extern struct mock_ctrl_fp_sensor mock_ctrl_fp_sensor;
 
diff --git a/include/mock/fpsensor_crypto_mock.h b/include/mock/fpsensor_crypto_mock.h
new file mode 100644
index 0000000000..8462dc1baf
--- /dev/null
+++ b/include/mock/fpsensor_crypto_mock.h
@@ -0,0 +1,30 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file fpsensor_crypto_mock.h
+ * @brief Controls for the mock fpsensor_crypto library
+ */
+
+#ifndef __MOCK_FPSENSOR_CRYPTO_MOCK_H
+#define __MOCK_FPSENSOR_CRYPTO_MOCK_H
+
+enum mock_ctrl_fpsensor_crypto_sha256_type {
+	MOCK_CTRL_FPSENSOR_CRYPTO_SHA256_TYPE_REAL,
+	MOCK_CTRL_FPSENSOR_CRYPTO_SHA256_TYPE_ZEROS,
+	MOCK_CTRL_FPSENSOR_CRYPTO_SHA256_TYPE_FF,
+};
+
+struct mock_ctrl_fpsensor_crypto {
+	enum mock_ctrl_fpsensor_crypto_sha256_type output_type;
+};
+
+#define MOCK_CTRL_DEFAULT_FPSENSOR_CRYPTO    \
+	((struct mock_ctrl_fpsensor_crypto){ \
+		.output_type = MOCK_CTRL_FPSENSOR_CRYPTO_SHA256_TYPE_REAL })
+
+extern struct mock_ctrl_fpsensor_crypto mock_ctrl_fpsensor_crypto;
+
+#endif /* __MOCK_FPSENSOR_CRYPTO_MOCK_H */
diff --git a/include/mock/fpsensor_detect_mock.h b/include/mock/fpsensor_detect_mock.h
index da23dded96..b8594ebdd9 100644
--- a/include/mock/fpsensor_detect_mock.h
+++ b/include/mock/fpsensor_detect_mock.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/mock/fpsensor_state_mock.h b/include/mock/fpsensor_state_mock.h
index eafe01851c..32450e3cc0 100644
--- a/include/mock/fpsensor_state_mock.h
+++ b/include/mock/fpsensor_state_mock.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,11 +8,19 @@
 
 #include <stdbool.h>
 #include <stdint.h>
+
+#include "driver/fingerprint/fpsensor.h"
 #include "ec_commands.h"
 
 extern const uint8_t default_fake_tpm_seed[FP_CONTEXT_TPM_BYTES];
+extern const uint8_t
+	default_fake_fp_positive_match_salt[FP_MAX_FINGER_COUNT]
+					   [FP_POSITIVE_MATCH_SALT_BYTES];
+extern const uint8_t
+	trivial_fp_positive_match_salt[FP_MAX_FINGER_COUNT]
+				      [FP_POSITIVE_MATCH_SALT_BYTES];
 
 int fpsensor_state_mock_set_tpm_seed(
 	const uint8_t tpm_seed[FP_CONTEXT_TPM_BYTES]);
 
-#endif  /* __MOCK_FPSENSOR_STATE_MOCK_H */
+#endif /* __MOCK_FPSENSOR_STATE_MOCK_H */
diff --git a/include/mock/mkbp_events_mock.h b/include/mock/mkbp_events_mock.h
index 3d686e3618..22600e4f96 100644
--- a/include/mock/mkbp_events_mock.h
+++ b/include/mock/mkbp_events_mock.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,10 +15,11 @@ struct mock_ctrl_mkbp_events {
 	int mkbp_send_event_return;
 };
 
-#define MOCK_CTRL_DEFAULT_MKBP_EVENTS          \
-(struct mock_ctrl_mkbp_events) {               \
-	.mkbp_send_event_return = 1,           \
-}
+#define MOCK_CTRL_DEFAULT_MKBP_EVENTS        \
+	(struct mock_ctrl_mkbp_events)       \
+	{                                    \
+		.mkbp_send_event_return = 1, \
+	}
 
 extern struct mock_ctrl_mkbp_events mock_ctrl_mkbp_events;
 
diff --git a/include/mock/rollback_mock.h b/include/mock/rollback_mock.h
index 576f87e6b9..890e2539a7 100644
--- a/include/mock/rollback_mock.h
+++ b/include/mock/rollback_mock.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,11 +17,12 @@ struct mock_ctrl_rollback {
 	bool get_secret_fail;
 };
 
-#define MOCK_CTRL_DEFAULT_ROLLBACK             \
-(struct mock_ctrl_rollback) {                  \
-	.get_secret_fail = false,              \
-}
+#define MOCK_CTRL_DEFAULT_ROLLBACK        \
+	(struct mock_ctrl_rollback)       \
+	{                                 \
+		.get_secret_fail = false, \
+	}
 
 extern struct mock_ctrl_rollback mock_ctrl_rollback;
 
-#endif  /* __MOCK_ROLLBACK_MOCK_H */
+#endif /* __MOCK_ROLLBACK_MOCK_H */
diff --git a/include/mock/tcpc_mock.h b/include/mock/tcpc_mock.h
index f4db14efb7..2f3a78c69a 100644
--- a/include/mock/tcpc_mock.h
+++ b/include/mock/tcpc_mock.h
@@ -1,8 +1,8 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
- /* Mock for the TCPC interface */
+/* Mock for the TCPC interface */
 
 #include "usb_pd_tcpm.h"
 #include "usb_pd.h"
@@ -28,7 +28,6 @@ struct mock_tcpc_ctrl {
 		enum tcpc_rp_value rp;
 		enum tcpc_cc_polarity polarity;
 	} last;
-
 };
 
 /* Reset this TCPC mock */
diff --git a/include/mock/tcpci_i2c_mock.h b/include/mock/tcpci_i2c_mock.h
index 1d4a986ebe..ae86a8c50b 100644
--- a/include/mock/tcpci_i2c_mock.h
+++ b/include/mock/tcpci_i2c_mock.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -28,15 +28,11 @@ int verify_tcpci_tx_retry_count(enum tcpci_msg_type tx_type,
 
 int verify_tcpci_tx_timeout(enum tcpci_msg_type tx_type,
 			    enum pd_ctrl_msg_type ctrl_msg,
-			    enum pd_data_msg_type data_msg,
-			    int timeout);
+			    enum pd_data_msg_type data_msg, int timeout);
 
 int verify_tcpci_tx_with_data(enum tcpci_msg_type tx_type,
-			      enum pd_data_msg_type data_msg,
-			      uint8_t *data,
-			      int data_bytes,
-			      int *msg_len,
-			      int timeout);
+			      enum pd_data_msg_type data_msg, uint8_t *data,
+			      int data_bytes, int *msg_len, int timeout);
 
 struct possible_tx {
 	enum tcpci_msg_type tx_type;
@@ -44,13 +40,9 @@ struct possible_tx {
 	enum pd_data_msg_type data_msg;
 };
 
-int verify_tcpci_possible_tx(struct possible_tx possible[],
-			     int possible_cnt,
-			     int *found_index,
-			     uint8_t *data,
-			     int data_bytes,
-			     int *msg_len,
-			     int timeout);
+int verify_tcpci_possible_tx(struct possible_tx possible[], int possible_cnt,
+			     int *found_index, uint8_t *data, int data_bytes,
+			     int *msg_len, int timeout);
 
 void mock_tcpci_receive(enum tcpci_msg_type sop, uint16_t header,
 			uint32_t *payload);
diff --git a/include/mock/tcpm_mock.h b/include/mock/tcpm_mock.h
index 7fd89919f5..2733863b62 100644
--- a/include/mock/tcpm_mock.h
+++ b/include/mock/tcpm_mock.h
@@ -1,8 +1,8 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
- /* Mock for the TCPM interface */
+/* Mock for the TCPM interface */
 
 #include "common.h"
 #include "tcpm/tcpm.h"
diff --git a/include/mock/timer_mock.h b/include/mock/timer_mock.h
index 04dc01e9ab..cc294521cc 100644
--- a/include/mock/timer_mock.h
+++ b/include/mock/timer_mock.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,4 +12,4 @@ void set_time(timestamp_t now_);
 
 timestamp_t get_time(void);
 
-#endif  /* __MOCK_TIMER_MOCK_H */
+#endif /* __MOCK_TIMER_MOCK_H */
diff --git a/include/mock/usb_mux_mock.h b/include/mock/usb_mux_mock.h
index 128286796b..c2d154ad72 100644
--- a/include/mock/usb_mux_mock.h
+++ b/include/mock/usb_mux_mock.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/mock/usb_pd_dpm_mock.h b/include/mock/usb_pd_dpm_mock.h
index c61594fd2b..8f91cfb390 100644
--- a/include/mock/usb_pd_dpm_mock.h
+++ b/include/mock/usb_pd_dpm_mock.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/mock/usb_pe_sm_mock.h b/include/mock/usb_pe_sm_mock.h
index fcd6e268a0..819f086c5a 100644
--- a/include/mock/usb_pe_sm_mock.h
+++ b/include/mock/usb_pe_sm_mock.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/mock/usb_prl_mock.h b/include/mock/usb_prl_mock.h
index ee37d6e6e2..eef1d8de63 100644
--- a/include/mock/usb_prl_mock.h
+++ b/include/mock/usb_prl_mock.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,17 +13,14 @@
 
 void mock_prl_reset(void);
 
-int mock_prl_wait_for_tx_msg(int port,
-			     enum tcpci_msg_type tx_type,
+int mock_prl_wait_for_tx_msg(int port, enum tcpci_msg_type tx_type,
 			     enum pd_ctrl_msg_type ctrl_msg,
-			     enum pd_data_msg_type data_msg,
-			     int timeout);
+			     enum pd_data_msg_type data_msg, int timeout);
 
 enum pd_ctrl_msg_type mock_prl_get_last_sent_ctrl_msg(int port);
 
 enum pd_data_msg_type mock_prl_get_last_sent_data_msg(int port);
 
-
 void mock_prl_clear_last_sent_msg(int port);
 
 void mock_prl_message_sent(int port);
diff --git a/include/mock/usb_tc_sm_mock.h b/include/mock/usb_tc_sm_mock.h
index ca16fb4d98..532f2bfb54 100644
--- a/include/mock/usb_tc_sm_mock.h
+++ b/include/mock/usb_tc_sm_mock.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/mock_filter.h b/include/mock_filter.h
index 113c227a3b..83beead6c7 100644
--- a/include/mock_filter.h
+++ b/include/mock_filter.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,5 +18,4 @@
 CONFIG_TEST_MOCK_LIST
 #endif
 
-
 #endif /*  __CROS_EC_MOCK_FILTER_H */
diff --git a/include/module_id.h b/include/module_id.h
index 8872bdd45c..bfc780e70f 100644
--- a/include/module_id.h
+++ b/include/module_id.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/motion_lid.h b/include/motion_lid.h
index 28ddcaec24..917a545ab6 100644
--- a/include/motion_lid.h
+++ b/include/motion_lid.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -34,4 +34,4 @@ enum ec_status host_cmd_motion_lid(struct host_cmd_handler_args *args);
 
 void motion_lid_calc(void);
 
-#endif  /* __CROS_EC_MOTION_LID_H */
+#endif /* __CROS_EC_MOTION_LID_H */
diff --git a/include/motion_orientation.h b/include/motion_orientation.h
index 641f97a799..4b1daaa58c 100644
--- a/include/motion_orientation.h
+++ b/include/motion_orientation.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,13 +12,13 @@
 #include "ec_commands.h"
 #include "motion_sense.h"
 
-enum motionsensor_orientation motion_orientation_remap(
-		const struct motion_sensor_t *s,
-		enum motionsensor_orientation orientation);
+enum motionsensor_orientation
+motion_orientation_remap(const struct motion_sensor_t *s,
+			 enum motionsensor_orientation orientation);
 
 bool motion_orientation_changed(const struct motion_sensor_t *s);
-enum motionsensor_orientation *motion_orientation_ptr(
-		const struct motion_sensor_t *s);
+enum motionsensor_orientation *
+motion_orientation_ptr(const struct motion_sensor_t *s);
 void motion_orientation_update(const struct motion_sensor_t *s);
 
-#endif   /* __CROS_EC_MOTION_ORIENTATION_H */
+#endif /* __CROS_EC_MOTION_ORIENTATION_H */
diff --git a/include/motion_sense.h b/include/motion_sense.h
index 1f2e912ce5..6033d52ff9 100644
--- a/include/motion_sense.h
+++ b/include/motion_sense.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -39,7 +39,6 @@ enum sensor_config {
 #define SENSOR_ACTIVE_S0_S3 (SENSOR_ACTIVE_S3 | SENSOR_ACTIVE_S0)
 #define SENSOR_ACTIVE_S0_S3_S5 (SENSOR_ACTIVE_S0_S3 | SENSOR_ACTIVE_S5)
 
-
 /*
  * Events layout:
  * 0                       8              10
@@ -49,29 +48,27 @@ enum sensor_config {
  */
 
 /* First 8 events for sensor interrupt lines */
-#define TASK_EVENT_MOTION_INTERRUPT_NUM      8
+#define TASK_EVENT_MOTION_INTERRUPT_NUM 8
 #define TASK_EVENT_MOTION_INTERRUPT_MASK \
 	((1 << TASK_EVENT_MOTION_INTERRUPT_NUM) - 1)
-#define TASK_EVENT_MOTION_SENSOR_INTERRUPT(_sensor_id) \
-	BUILD_CHECK_INLINE( \
-		TASK_EVENT_CUSTOM_BIT(_sensor_id), \
-		_sensor_id < TASK_EVENT_MOTION_INTERRUPT_NUM)
+#define TASK_EVENT_MOTION_SENSOR_INTERRUPT(_sensor_id)        \
+	BUILD_CHECK_INLINE(TASK_EVENT_CUSTOM_BIT(_sensor_id), \
+			   _sensor_id < TASK_EVENT_MOTION_INTERRUPT_NUM)
 
 /* Internal events to motion sense task.*/
 #define TASK_EVENT_MOTION_FIRST_INTERNAL_EVENT TASK_EVENT_MOTION_INTERRUPT_NUM
-#define TASK_EVENT_MOTION_INTERNAL_EVENT_NUM    2
+#define TASK_EVENT_MOTION_INTERNAL_EVENT_NUM 2
 #define TASK_EVENT_MOTION_FLUSH_PENDING \
 	TASK_EVENT_CUSTOM_BIT(TASK_EVENT_MOTION_FIRST_INTERNAL_EVENT)
 #define TASK_EVENT_MOTION_ODR_CHANGE \
 	TASK_EVENT_CUSTOM_BIT(TASK_EVENT_MOTION_FIRST_INTERNAL_EVENT + 1)
 
 /* Activity events */
-#define TASK_EVENT_MOTION_FIRST_SW_EVENT   \
+#define TASK_EVENT_MOTION_FIRST_SW_EVENT \
 	(TASK_EVENT_MOTION_INTERRUPT_NUM + TASK_EVENT_MOTION_INTERNAL_EVENT_NUM)
-#define TASK_EVENT_MOTION_ACTIVITY_INTERRUPT(_activity_id) \
-	(TASK_EVENT_CUSTOM_BIT( \
-		TASK_EVENT_MOTION_FIRST_SW_EVENT + (_activity_id)))
-
+#define TASK_EVENT_MOTION_ACTIVITY_INTERRUPT(_activity_id)        \
+	(TASK_EVENT_CUSTOM_BIT(TASK_EVENT_MOTION_FIRST_SW_EVENT + \
+			       (_activity_id)))
 
 #define ROUND_UP_FLAG ((uint32_t)BIT(31))
 #define BASE_ODR(_odr) ((_odr) & ~ROUND_UP_FLAG)
@@ -87,13 +84,13 @@ enum sensor_config {
  *   use peripheral addressing, it is up to the driver to use this
  *   field as it sees fit
  */
-#define ACCEL_MK_I2C_ADDR_FLAGS(addr)	(addr)
-#define ACCEL_MK_SPI_ADDR_FLAGS(addr)	((addr) | I2C_FLAG_ADDR_IS_SPI)
+#define ACCEL_MK_I2C_ADDR_FLAGS(addr) (addr)
+#define ACCEL_MK_SPI_ADDR_FLAGS(addr) ((addr) | I2C_FLAG_ADDR_IS_SPI)
 
-#define ACCEL_GET_I2C_ADDR(addr_flags)	(I2C_STRIP_FLAGS(addr_flags))
-#define ACCEL_GET_SPI_ADDR(addr_flags)	((addr_flags) & I2C_ADDR_MASK)
+#define ACCEL_GET_I2C_ADDR(addr_flags) (I2C_STRIP_FLAGS(addr_flags))
+#define ACCEL_GET_SPI_ADDR(addr_flags) ((addr_flags)&I2C_ADDR_MASK)
 
-#define ACCEL_ADDR_IS_SPI(addr_flags)	((addr_flags) & I2C_FLAG_ADDR_IS_SPI)
+#define ACCEL_ADDR_IS_SPI(addr_flags) ((addr_flags)&I2C_FLAG_ADDR_IS_SPI)
 
 /*
  * Define the frequency to use in max_frequency based on the maximal frequency
@@ -101,9 +98,10 @@ enum sensor_config {
  * Return a frequency the sensor supports.
  * Trigger a compilation error when the EC way to slow for the sensor.
  */
-#define MOTION_MAX_SENSOR_FREQUENCY(_max, _step) GENERIC_MIN( \
-	(_max) / (CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ >= (_step)), \
-	(_step) << __fls(CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ / (_step)))
+#define MOTION_MAX_SENSOR_FREQUENCY(_max, _step)                         \
+	GENERIC_MIN(                                                     \
+		(_max) / (CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ >= (_step)), \
+		(_step) << __fls(CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ / (_step)))
 
 struct motion_data_t {
 	/*
@@ -126,7 +124,7 @@ struct motion_data_t {
  * When set, spoof mode will allow the EC to report arbitrary values for any of
  * the components.
  */
-#define MOTIONSENSE_FLAG_IN_SPOOF_MODE		BIT(1)
+#define MOTIONSENSE_FLAG_IN_SPOOF_MODE BIT(1)
 
 struct online_calib_data {
 	/**
@@ -222,12 +220,6 @@ struct motion_sensor_t {
 	uint16_t oversampling_ratio;
 
 	/*
-	 * How many vector events are lost in the FIFO since last time
-	 * FIFO info has been transmitted.
-	 */
-	uint16_t lost;
-
-	/*
 	 * For sensors in forced mode the ideal time to collect the next
 	 * measurement.
 	 *
@@ -353,8 +345,9 @@ static inline void ec_motion_sensor_clamp_i16s(int16_t *arr, const int32_t *v)
 }
 
 /* direct assignment */
-static inline void ec_motion_sensor_fill_values(
-		struct ec_response_motion_sensor_data *dst, const int32_t *v)
+static inline void
+ec_motion_sensor_fill_values(struct ec_response_motion_sensor_data *dst,
+			     const int32_t *v)
 {
 	dst->data[0] = v[0];
 	dst->data[1] = v[1];
diff --git a/include/motion_sense_fifo.h b/include/motion_sense_fifo.h
index 90d3f78879..e4012e2372 100644
--- a/include/motion_sense_fifo.h
+++ b/include/motion_sense_fifo.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,8 +12,8 @@
 enum motion_sense_async_event {
 	ASYNC_EVENT_FLUSH = MOTIONSENSE_SENSOR_FLAG_FLUSH |
 			    MOTIONSENSE_SENSOR_FLAG_TIMESTAMP,
-	ASYNC_EVENT_ODR =   MOTIONSENSE_SENSOR_FLAG_ODR |
-			    MOTIONSENSE_SENSOR_FLAG_TIMESTAMP,
+	ASYNC_EVENT_ODR = MOTIONSENSE_SENSOR_FLAG_ODR |
+			  MOTIONSENSE_SENSOR_FLAG_TIMESTAMP,
 };
 
 /**
@@ -22,6 +22,15 @@ enum motion_sense_async_event {
 void motion_sense_fifo_init(void);
 
 /**
+ * Set the expected period between samples. Must be call under
+ * g_mutex_lock each time the sensor ODR changes.
+ *
+ * @param sensor_num Affected sensor
+ * @param data_period expected milliseconds between samples.
+ */
+void motion_sense_set_data_period(int sensor_num, uint32_t data_period);
+
+/**
  * Whether or not we need to bypass the FIFO to send an important message.
  *
  * @return Non zero when a bypass is needed.
@@ -48,9 +57,8 @@ void motion_sense_fifo_reset_needed_flags(void);
  * @param sensor The sensor that generated the async event.
  * @param event The event to insert.
  */
-void motion_sense_fifo_insert_async_event(
-	struct motion_sensor_t *sensor,
-	enum motion_sense_async_event event);
+void motion_sense_fifo_insert_async_event(struct motion_sensor_t *sensor,
+					  enum motion_sense_async_event event);
 
 /**
  * Insert a timestamp into the fifo.
@@ -69,11 +77,9 @@ void motion_sense_fifo_add_timestamp(uint32_t timestamp);
  * @param time accurate time (ideally measured in an interrupt) the sample
  *             was taken at
  */
-void motion_sense_fifo_stage_data(
-	struct ec_response_motion_sensor_data *data,
-	struct motion_sensor_t *sensor,
-	int valid_data,
-	uint32_t time);
+void motion_sense_fifo_stage_data(struct ec_response_motion_sensor_data *data,
+				  struct motion_sensor_t *sensor,
+				  int valid_data, uint32_t time);
 
 /**
  * Commit all the currently staged data to the fifo. Doing so makes it readable
@@ -85,12 +91,12 @@ void motion_sense_fifo_commit_data(void);
  * Get information about the fifo.
  *
  * @param fifo_info The struct to modify with the current information about the
- *	  fifo.
+ *	  fifo. WARNING: This must point to a buffer big enough for the struct
+ *	  and also sizeof(uint16_t) * MAX_MOTION_SENSORS of extra space.
  * @param reset Whether or not to reset statistics after reading them.
  */
 void motion_sense_fifo_get_info(
-	struct ec_response_motion_sense_fifo_info *fifo_info,
-	int reset);
+	struct ec_response_motion_sense_fifo_info *fifo_info, int reset);
 
 /**
  * Check whether or not the fifo has gone over its threshold.
diff --git a/include/newton_fit.h b/include/newton_fit.h
index b4db64c814..2fb1994083 100644
--- a/include/newton_fit.h
+++ b/include/newton_fit.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/ocpc.h b/include/ocpc.h
index 3f7b08827f..da1c6907d4 100644
--- a/include/ocpc.h
+++ b/include/ocpc.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,7 +17,7 @@ struct ocpc_data {
 	int active_chg_chip;
 
 	int combined_rsys_rbatt_mo; /* System resistance b/w output and Vbatt */
-	int rsys_mo;  /* System resistance b/w output and VSYS node */
+	int rsys_mo; /* System resistance b/w output and VSYS node */
 	int rbatt_mo; /* Resistance between VSYS node and battery */
 
 	/* ADC values */
@@ -38,7 +38,7 @@ struct ocpc_data {
 #endif /* HAS_TASK_PD_C1 */
 };
 
-#define OCPC_NO_ISYS_MEAS_CAP	BIT(0)
+#define OCPC_NO_ISYS_MEAS_CAP BIT(0)
 
 /** Set the VSYS target for the secondary charger IC.
  *
@@ -49,8 +49,8 @@ struct ocpc_data {
  * @return EC_SUCCESS on success, error otherwise.
  */
 int ocpc_config_secondary_charger(int *desired_input_current,
-				  struct ocpc_data *ocpc,
-				  int voltage_mv, int current_ma);
+				  struct ocpc_data *ocpc, int voltage_mv,
+				  int current_ma);
 
 /** Get the runtime data from the various ADCs.
  *
@@ -59,9 +59,8 @@ int ocpc_config_secondary_charger(int *desired_input_current,
 void ocpc_get_adcs(struct ocpc_data *ocpc);
 
 /* Set the PID constants for the charging loop */
-__overridable void ocpc_get_pid_constants(int *kp, int *kp_div,
-					  int *ki, int *ki_div,
-					  int *kd, int *kd_div);
+__overridable void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki,
+					  int *ki_div, int *kd, int *kd_div);
 
 /*
  ** Set up some initial values for the OCPC data structure.  This will call off
diff --git a/include/onewire.h b/include/onewire.h
index 58899360a4..0b328ceedc 100644
--- a/include/onewire.h
+++ b/include/onewire.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -40,4 +40,4 @@ int onewire_read(void);
  */
 void onewire_write(int data);
 
-#endif  /* __CROS_EC_ONEWIRE_H */
+#endif /* __CROS_EC_ONEWIRE_H */
diff --git a/include/online_calibration.h b/include/online_calibration.h
index e3b259e14d..abeb192b75 100644
--- a/include/online_calibration.h
+++ b/include/online_calibration.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,10 +22,9 @@ void online_calibration_init(void);
  * @param timestamp The time associated with the sample
  * @return EC_SUCCESS when successful.
  */
-int online_calibration_process_data(
-	struct ec_response_motion_sensor_data *data,
-	struct motion_sensor_t *sensor,
-	uint32_t timestamp);
+int online_calibration_process_data(struct ec_response_motion_sensor_data *data,
+				    struct motion_sensor_t *sensor,
+				    uint32_t timestamp);
 
 /**
  * Check if new calibration values are available since the last read.
diff --git a/include/otp.h b/include/otp.h
index 7851411202..2047a2e19f 100644
--- a/include/otp.h
+++ b/include/otp.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -29,4 +29,4 @@ int otp_write_serial(const char *serialno);
  */
 const char *otp_read_serial(void);
 
-#endif  /* __CROS_EC_OTP_H */
+#endif /* __CROS_EC_OTP_H */
diff --git a/include/overflow.h b/include/overflow.h
index 42eab6a094..884eec884a 100644
--- a/include/overflow.h
+++ b/include/overflow.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,7 +26,7 @@
 	__has_builtin(__builtin_mul_overflow)
 #define COMPILER_HAS_GENERIC_BUILTIN_OVERFLOW 1
 #endif
-#endif  /* __clang__ */
+#endif /* __clang__ */
 
 #include "third_party/linux/overflow.h"
 
diff --git a/include/panic.h b/include/panic.h
index 6e4f17fcb9..9a1a78844e 100644
--- a/include/panic.h
+++ b/include/panic.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -15,6 +15,19 @@
 
 #include "software_panic.h"
 
+/*
+ * Define these helpers if needed. While normally they would be derived from
+ * common.h, we cannot include that header here because this file is also used
+ * in the ectool and the build breaks.
+ */
+#ifndef test_mockable_noreturn
+#if defined(TEST_BUILD) || defined(CONFIG_ZTEST)
+#define test_mockable_noreturn __attribute__((weak))
+#else
+#define test_mockable_noreturn noreturn
+#endif
+#endif /* test_mockable_noreturn */
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -66,21 +79,21 @@ struct cortex_panic_data {
 /* NDS32 N8 registers saved on panic */
 struct nds32_n8_panic_data {
 	uint32_t itype;
-	uint32_t regs[16];        /* r0-r10, r15, fp, gp, lp, sp */
+	uint32_t regs[16]; /* r0-r10, r15, fp, gp, lp, sp */
 	uint32_t ipc;
 	uint32_t ipsw;
 };
 
 /* RISC-V RV32I registers saved on panic */
 struct rv32i_panic_data {
-	uint32_t regs[31];        /* sp, ra, gp, tp, a0-a7, t0-t6, s0-s11 */
-	uint32_t mepc;            /* mepc */
-	uint32_t mcause;          /* mcause */
+	uint32_t regs[31]; /* sp, ra, gp, tp, a0-a7, t0-t6, s0-s11 */
+	uint32_t mepc; /* mepc */
+	uint32_t mcause; /* mcause */
 };
 
 /* x86 registers saved on panic */
 struct x86_panic_data {
-	uint32_t vector;          /* Exception vector number */
+	uint32_t vector; /* Exception vector number */
 
 	/* Data pushed when exception handler called */
 	uint32_t error_code;
@@ -102,18 +115,18 @@ struct x86_panic_data {
 
 /* Data saved across reboots */
 struct panic_data {
-	uint8_t arch;             /* Architecture (PANIC_ARCH_*) */
-	uint8_t struct_version;   /* Structure version (currently 2) */
-	uint8_t flags;            /* Flags (PANIC_DATA_FLAG_*) */
-	uint8_t reserved;         /* Reserved; set 0 */
+	uint8_t arch; /* Architecture (PANIC_ARCH_*) */
+	uint8_t struct_version; /* Structure version (currently 2) */
+	uint8_t flags; /* Flags (PANIC_DATA_FLAG_*) */
+	uint8_t reserved; /* Reserved; set 0 */
 
 	/* core specific panic data */
 	union {
-		struct cortex_panic_data cm;       /* Cortex-Mx registers */
+		struct cortex_panic_data cm; /* Cortex-Mx registers */
 		struct nds32_n8_panic_data nds_n8; /* NDS32 N8 registers */
-		struct x86_panic_data x86;         /* Intel x86 */
+		struct x86_panic_data x86; /* Intel x86 */
 #ifndef CONFIG_DO_NOT_INCLUDE_RV32I_PANIC_DATA
-		struct rv32i_panic_data riscv;     /* RISC-V RV32I */
+		struct rv32i_panic_data riscv; /* RISC-V RV32I */
 #endif
 	};
 
@@ -121,21 +134,21 @@ struct panic_data {
 	 * These fields go at the END of the struct so we can find it at the
 	 * end of memory.
 	 */
-	uint32_t struct_size;     /* Size of this struct */
-	uint32_t magic;           /* PANIC_SAVE_MAGIC if valid */
+	uint32_t struct_size; /* Size of this struct */
+	uint32_t magic; /* PANIC_SAVE_MAGIC if valid */
 };
 
 #ifdef CONFIG_RO_PANIC_DATA_SIZE
 BUILD_ASSERT(sizeof(struct panic_data) == CONFIG_RO_PANIC_DATA_SIZE);
 #endif
 
-#define PANIC_DATA_MAGIC 0x21636e50  /* "Pnc!" */
+#define PANIC_DATA_MAGIC 0x21636e50 /* "Pnc!" */
 enum panic_arch {
-	PANIC_ARCH_CORTEX_M = 1,     /* Cortex-M architecture */
-	PANIC_ARCH_NDS32_N8 = 2,     /* NDS32 N8 architecture */
-	PANIC_ARCH_X86 = 3,          /* Intel x86 */
+	PANIC_ARCH_CORTEX_M = 1, /* Cortex-M architecture */
+	PANIC_ARCH_NDS32_N8 = 2, /* NDS32 N8 architecture */
+	PANIC_ARCH_X86 = 3, /* Intel x86 */
 #ifndef CONFIG_DO_NOT_INCLUDE_RV32I_PANIC_DATA
-	PANIC_ARCH_RISCV_RV32I = 4,  /* RISC-V RV32I */
+	PANIC_ARCH_RISCV_RV32I = 4, /* RISC-V RV32I */
 #endif
 };
 
@@ -144,13 +157,13 @@ enum panic_arch {
 
 /* Flags for panic_data.flags */
 /* panic_data.frame is valid */
-#define PANIC_DATA_FLAG_FRAME_VALID    BIT(0)
+#define PANIC_DATA_FLAG_FRAME_VALID BIT(0)
 /* Already printed at console */
-#define PANIC_DATA_FLAG_OLD_CONSOLE    BIT(1)
+#define PANIC_DATA_FLAG_OLD_CONSOLE BIT(1)
 /* Already returned via host command */
-#define PANIC_DATA_FLAG_OLD_HOSTCMD    BIT(2)
+#define PANIC_DATA_FLAG_OLD_HOSTCMD BIT(2)
 /* Already reported via host event */
-#define PANIC_DATA_FLAG_OLD_HOSTEVENT  BIT(3)
+#define PANIC_DATA_FLAG_OLD_HOSTEVENT BIT(3)
 
 /**
  * Write a string to the panic reporting device
@@ -170,8 +183,8 @@ void panic_puts(const char *s);
  * @param format	printf-style format string
  * @param ...		Arguments to process
  */
-__attribute__((__format__(__printf__, 1, 2)))
-void panic_printf(const char *format, ...);
+__attribute__((__format__(__printf__, 1, 2))) void
+panic_printf(const char *format, ...);
 
 /*
  * Print saved panic information
@@ -197,10 +210,10 @@ void panic_data_ccprint(const struct panic_data *pdata);
  * @param linenum	Line number where assertion happened
  */
 #ifdef CONFIG_DEBUG_ASSERT_BRIEF
-noreturn void panic_assert_fail(const char *fname, int linenum);
+test_mockable_noreturn void panic_assert_fail(const char *fname, int linenum);
 #else
-noreturn void panic_assert_fail(const char *msg, const char *func,
-				const char *fname, int linenum);
+test_mockable_noreturn void panic_assert_fail(const char *msg, const char *func,
+					      const char *fname, int linenum);
 #endif
 
 /**
@@ -208,19 +221,27 @@ noreturn void panic_assert_fail(const char *msg, const char *func,
  *
  * @param msg	Panic message
  */
-noreturn void panic(const char *msg);
+#if !(defined(TEST_FUZZ) || defined(CONFIG_ZTEST))
+noreturn
+#endif
+	void
+	panic(const char *msg);
 
 /**
  * Display a default message and reset
  */
-noreturn void panic_reboot(void);
+#if !(defined(TEST_FUZZ) || defined(CONFIG_ZTEST))
+noreturn
+#endif
+	void
+	panic_reboot(void);
 
 #ifdef CONFIG_SOFTWARE_PANIC
 /**
  * Store a panic log and halt the system for a software-related reason, such as
  * stack overflow or assertion failure.
  */
-noreturn void software_panic(uint32_t reason, uint32_t info);
+test_mockable_noreturn void software_panic(uint32_t reason, uint32_t info);
 
 /**
  * Log a panic in the panic log, but don't halt the system. Normally
@@ -254,8 +275,8 @@ void ignore_bus_fault(int ignored);
  * Return a pointer to the saved data from a previous panic that can be
  * safely interpreted
  *
- * @param pointer to the valid panic data, or NULL if none available (for example,
- * the last reboot was not caused by a panic).
+ * @param pointer to the valid panic data, or NULL if none available (for
+ * example, the last reboot was not caused by a panic).
  */
 struct panic_data *panic_get_data(void);
 
@@ -294,4 +315,4 @@ void chip_panic_data_backup(void);
 }
 #endif
 
-#endif  /* __CROS_EC_PANIC_H */
+#endif /* __CROS_EC_PANIC_H */
diff --git a/include/peci.h b/include/peci.h
index 993e7d637d..401e3f999f 100644
--- a/include/peci.h
+++ b/include/peci.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,37 +10,37 @@
 
 #include "common.h"
 
-#define PECI_TARGET_ADDRESS         0x30
-#define PECI_WRITE_DATA_FIFO_SIZE   15
-#define PECI_READ_DATA_FIFO_SIZE    16
+#define PECI_TARGET_ADDRESS 0x30
+#define PECI_WRITE_DATA_FIFO_SIZE 15
+#define PECI_READ_DATA_FIFO_SIZE 16
 
-#define PECI_GET_TEMP_READ_LENGTH   2
-#define PECI_GET_TEMP_WRITE_LENGTH  0
-#define PECI_GET_TEMP_TIMEOUT_US    200
+#define PECI_GET_TEMP_READ_LENGTH 2
+#define PECI_GET_TEMP_WRITE_LENGTH 0
+#define PECI_GET_TEMP_TIMEOUT_US 200
 
 /* PECI Command Code */
 enum peci_command_code {
-	PECI_CMD_PING             = 0x00,
-	PECI_CMD_GET_DIB          = 0xF7,
-	PECI_CMD_GET_TEMP         = 0x01,
-	PECI_CMD_RD_PKG_CFG       = 0xA1,
-	PECI_CMD_WR_PKG_CFG       = 0xA5,
-	PECI_CMD_RD_IAMSR         = 0xB1,
-	PECI_CMD_WR_IAMSR         = 0xB5,
-	PECI_CMD_RD_PCI_CFG       = 0x61,
-	PECI_CMD_WR_PCI_CFG       = 0x65,
+	PECI_CMD_PING = 0x00,
+	PECI_CMD_GET_DIB = 0xF7,
+	PECI_CMD_GET_TEMP = 0x01,
+	PECI_CMD_RD_PKG_CFG = 0xA1,
+	PECI_CMD_WR_PKG_CFG = 0xA5,
+	PECI_CMD_RD_IAMSR = 0xB1,
+	PECI_CMD_WR_IAMSR = 0xB5,
+	PECI_CMD_RD_PCI_CFG = 0x61,
+	PECI_CMD_WR_PCI_CFG = 0x65,
 	PECI_CMD_RD_PCI_CFG_LOCAL = 0xE1,
 	PECI_CMD_WR_PCI_CFG_LOCAL = 0xE5,
 };
 
 struct peci_data {
 	enum peci_command_code cmd_code; /* command code */
-	uint8_t addr;	/* client address */
-	uint8_t w_len;	/* write length */
-	uint8_t r_len;	/* read length */
-	uint8_t *w_buf;	/* buffer pointer of write data */
-	uint8_t *r_buf;	/* buffer pointer of read data */
-	int timeout_us;	/* transaction timeout unit:us */
+	uint8_t addr; /* client address */
+	uint8_t w_len; /* write length */
+	uint8_t r_len; /* read length */
+	uint8_t *w_buf; /* buffer pointer of write data */
+	uint8_t *r_buf; /* buffer pointer of read data */
+	int timeout_us; /* transaction timeout unit:us */
 };
 
 /**
@@ -62,4 +62,4 @@ int peci_temp_sensor_get_val(int idx, int *temp_ptr);
  */
 int peci_transaction(struct peci_data *peci);
 
-#endif  /* __CROS_EC_PECI_H */
+#endif /* __CROS_EC_PECI_H */
diff --git a/include/peripheral_charger.h b/include/peripheral_charger.h
index 0479b5e7bd..ac193ba2da 100644
--- a/include/peripheral_charger.h
+++ b/include/peripheral_charger.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -87,7 +87,7 @@
  */
 
 /* Size of event queue. Use it to initialize struct pchg.events. */
-#define PCHG_EVENT_QUEUE_SIZE	8
+#define PCHG_EVENT_QUEUE_SIZE 8
 
 enum pchg_event {
 	/* No event */
@@ -143,7 +143,7 @@ enum pchg_error {
 	PCHG_ERROR_OTHER,
 };
 
-#define PCHG_ERROR_MASK(e)	BIT(e)
+#define PCHG_ERROR_MASK(e) BIT(e)
 
 enum pchg_mode {
 	PCHG_MODE_NORMAL = 0,
@@ -189,7 +189,7 @@ struct pchg_update {
  */
 struct pchg {
 	/* Static configuration */
-	const struct pchg_config * const cfg;
+	const struct pchg_config *const cfg;
 	/* Current state of the port */
 	enum pchg_state state;
 	/* Event queue */
@@ -220,12 +220,23 @@ struct pchg {
  * Peripheral charger driver
  */
 struct pchg_drv {
-	/* Reset charger chip. */
+	/*
+	 * Reset charger chip. External reset (e.g by GPIO). No
+	 * communication or data access is expected (e.g. no I2C access).
+	 */
 	int (*reset)(struct pchg *ctx);
-	/* Initialize the charger. */
+	/*
+	 * Initialize the charger. Run setup needed only once per reset
+	 * (e.g. enable I2C, unlock I2C).
+	 */
 	int (*init)(struct pchg *ctx);
 	/* Enable/disable the charger. */
 	int (*enable)(struct pchg *ctx, bool enable);
+	/*
+	 * Get chip info, identify chip and setup function pointers
+	 * (e.g. I2C read function). It needs to work without IRQ.
+	 */
+	int (*get_chip_info)(struct pchg *ctx);
 	/* Get event info. */
 	int (*get_event)(struct pchg *ctx);
 	/* Get battery level. */
@@ -246,7 +257,7 @@ extern struct pchg pchgs[];
 extern const int pchg_count;
 
 /* Utility macro converting port config to port number. */
-#define PCHG_CTX_TO_PORT(ctx)	((ctx) - &pchgs[0])
+#define PCHG_CTX_TO_PORT(ctx) ((ctx) - &pchgs[0])
 
 /**
  * Interrupt handler for a peripheral charger.
diff --git a/include/physical_presence.h b/include/physical_presence.h
index 0acbc65691..4f93eaea62 100644
--- a/include/physical_presence.h
+++ b/include/physical_presence.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/include/port80.h b/include/port80.h
index e6212ab593..7521788ea1 100644
--- a/include/port80.h
+++ b/include/port80.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,9 +11,9 @@
 #include "common.h"
 
 enum port_80_event {
-	PORT_80_EVENT_RESUME = 0x1001,  /* S3->S0 transition */
-	PORT_80_EVENT_RESET = 0x1002,   /* RESET transition */
-	PORT_80_IGNORE = 0xffff,	/* Invalid POST CODE */
+	PORT_80_EVENT_RESUME = 0x1001, /* S3->S0 transition */
+	PORT_80_EVENT_RESET = 0x1002, /* RESET transition */
+	PORT_80_IGNORE = 0xffff, /* Invalid POST CODE */
 };
 
 /**
@@ -31,4 +31,4 @@ void port_80_write(int data);
  */
 int port_80_read(void);
 
-#endif  /* __CROS_EC_PORT80_H */
+#endif /* __CROS_EC_PORT80_H */
diff --git a/include/power.h b/include/power.h
index 6200392b95..c32b2714e5 100644
--- a/include/power.h
+++ b/include/power.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,33 +14,33 @@
 #include "gpio_signal.h"
 #include "task_id.h"
 
-FORWARD_DECLARE_ENUM(power_state) {
+FORWARD_DECLARE_ENUM(power_state){
 	/* Steady states */
-	POWER_G3 = 0,	/*
-			 * System is off (not technically all the way into G3,
-			 * which means totally unpowered...)
-			 */
-	POWER_S5,		/* System is soft-off */
-	POWER_S4,		/* System is suspended to disk */
-	POWER_S3,		/* Suspend; RAM on, processor is asleep */
-	POWER_S0,		/* System is on */
+	POWER_G3 = 0, /*
+		       * System is off (not technically all the way into G3,
+		       * which means totally unpowered...)
+		       */
+	POWER_S5, /* System is soft-off */
+	POWER_S4, /* System is suspended to disk */
+	POWER_S3, /* Suspend; RAM on, processor is asleep */
+	POWER_S0, /* System is on */
 #ifdef CONFIG_POWER_S0IX
 	POWER_S0ix,
 #endif
 	/* Transitions */
-	POWER_G3S5,	/* G3 -> S5 (at system init time) */
-	POWER_S5S3,	/* S5 -> S3 (skips S4 on non-Intel systems) */
-	POWER_S3S0,	/* S3 -> S0 */
-	POWER_S0S3,	/* S0 -> S3 */
-	POWER_S3S5,	/* S3 -> S5 (skips S4 on non-Intel systems) */
-	POWER_S5G3,	/* S5 -> G3 */
-	POWER_S3S4,	/* S3 -> S4 */
-	POWER_S4S3,	/* S4 -> S3 */
-	POWER_S4S5,	/* S4 -> S5 */
-	POWER_S5S4,	/* S5 -> S4 */
+	POWER_G3S5, /* G3 -> S5 (at system init time) */
+	POWER_S5S3, /* S5 -> S3 (skips S4 on non-Intel systems) */
+	POWER_S3S0, /* S3 -> S0 */
+	POWER_S0S3, /* S0 -> S3 */
+	POWER_S3S5, /* S3 -> S5 (skips S4 on non-Intel systems) */
+	POWER_S5G3, /* S5 -> G3 */
+	POWER_S3S4, /* S3 -> S4 */
+	POWER_S4S3, /* S4 -> S3 */
+	POWER_S4S5, /* S4 -> S5 */
+	POWER_S5S4, /* S5 -> S4 */
 #ifdef CONFIG_POWER_S0IX
-	POWER_S0ixS0,   /* S0ix -> S0 */
-	POWER_S0S0ix,   /* S0 -> S0ix */
+	POWER_S0ixS0, /* S0ix -> S0 */
+	POWER_S0S0ix, /* S0 -> S0ix */
 #endif
 };
 
@@ -58,18 +58,18 @@ FORWARD_DECLARE_ENUM(power_state) {
  * +-----------------+------------------------------------+
  */
 
-#define POWER_SIGNAL_ACTIVE_STATE	BIT(0)
-#define POWER_SIGNAL_ACTIVE_LOW	(0 << 0)
-#define POWER_SIGNAL_ACTIVE_HIGH	BIT(0)
+#define POWER_SIGNAL_ACTIVE_STATE BIT(0)
+#define POWER_SIGNAL_ACTIVE_LOW (0 << 0)
+#define POWER_SIGNAL_ACTIVE_HIGH BIT(0)
 
-#define POWER_SIGNAL_INTR_STATE	BIT(1)
-#define POWER_SIGNAL_DISABLE_AT_BOOT	BIT(1)
+#define POWER_SIGNAL_INTR_STATE BIT(1)
+#define POWER_SIGNAL_DISABLE_AT_BOOT BIT(1)
 
 /* Information on an power signal */
 struct power_signal_info {
-	enum gpio_signal gpio;	/* GPIO for signal */
-	uint32_t flags;		/* See POWER_SIGNAL_* macros */
-	const char *name;	/* Name of signal */
+	enum gpio_signal gpio; /* GPIO for signal */
+	uint32_t flags; /* See POWER_SIGNAL_* macros */
+	const char *name; /* Name of signal */
 };
 
 /*
@@ -161,7 +161,6 @@ int power_wait_signals_timeout(uint32_t want, int timeout);
  */
 int power_wait_mask_signals_timeout(uint32_t want, uint32_t mask, int timeout);
 
-
 /**
  * Set the low-level power chipset state.
  *
@@ -177,7 +176,8 @@ void power_set_state(enum power_state new_state);
 #ifdef CONFIG_AP_POWER_CONTROL
 enum power_state power_get_state(void);
 #else
-static inline enum power_state power_get_state(void) {
+static inline enum power_state power_get_state(void)
+{
 	return POWER_G3;
 }
 #endif
@@ -208,7 +208,9 @@ enum power_state power_handle_state(enum power_state state);
 #ifdef CONFIG_AP_POWER_CONTROL
 void power_signal_interrupt(enum gpio_signal signal);
 #else
-static inline void power_signal_interrupt(enum gpio_signal signal) { }
+static inline void power_signal_interrupt(enum gpio_signal signal)
+{
+}
 #endif /* !CONFIG_AP_POWER_CONTROL */
 
 /**
@@ -254,7 +256,7 @@ void power_set_host_sleep_state(enum host_sleep_event state);
 /* Context to pass to a host sleep command handler. */
 struct host_sleep_event_context {
 	uint32_t sleep_transitions; /* Number of sleep transitions observed */
-	uint16_t sleep_timeout_ms;  /* Timeout in milliseconds */
+	uint16_t sleep_timeout_ms; /* Timeout in milliseconds */
 };
 
 /**
@@ -264,9 +266,9 @@ struct host_sleep_event_context {
  * @param state Current host sleep state updated by the host.
  * @param ctx Possible sleep parameters and return values, depending on state.
  */
-__override_proto void power_chipset_handle_host_sleep_event(
-		enum host_sleep_event state,
-		struct host_sleep_event_context *ctx);
+__override_proto void
+power_chipset_handle_host_sleep_event(enum host_sleep_event state,
+				      struct host_sleep_event_context *ctx);
 
 /**
  * Provide callback to allow board to take any action on host sleep event
@@ -274,8 +276,8 @@ __override_proto void power_chipset_handle_host_sleep_event(
  *
  * @param state Current host sleep state updated by the host.
  */
-__override_proto void power_board_handle_host_sleep_event(
-		enum host_sleep_event state);
+__override_proto void
+power_board_handle_host_sleep_event(enum host_sleep_event state);
 
 /*
  * This is the default state of host sleep event. Calls to
@@ -283,7 +285,7 @@ __override_proto void power_board_handle_host_sleep_event(
  * value. EC components listening to host sleep event updates can check for this
  * special value to know if the state was reset.
  */
-#define HOST_SLEEP_EVENT_DEFAULT_RESET		0
+#define HOST_SLEEP_EVENT_DEFAULT_RESET 0
 
 enum sleep_notify_type {
 	SLEEP_NOTIFY_NONE,
@@ -337,8 +339,8 @@ enum sleep_hang_type {
  *
  * @param hang_type Host sleep hang type detected.
  */
-__override_proto void power_chipset_handle_sleep_hang(
-			enum sleep_hang_type hang_type);
+__override_proto void
+power_chipset_handle_sleep_hang(enum sleep_hang_type hang_type);
 
 /**
  * Provide callback to allow board to take action on host sleep hang
@@ -349,8 +351,8 @@ __override_proto void power_chipset_handle_sleep_hang(
  *
  * @param hang_type Host sleep hang type detected.
  */
-__override_proto void power_board_handle_sleep_hang(
-			enum sleep_hang_type hang_type);
+__override_proto void
+power_board_handle_sleep_hang(enum sleep_hang_type hang_type);
 
 /**
  * Start the suspend process.
@@ -422,7 +424,6 @@ void power_5v_enable(task_id_t tid, int enable);
 void test_power_common_state(void);
 #endif
 
-
 #ifdef CONFIG_POWERSEQ_FAKE_CONTROL
 /**
  * Enable a fake S0 state
@@ -442,4 +443,4 @@ void power_fake_s0(void);
 void power_fake_disable(void);
 #endif /* defined(CONFIG_POWER_FAKE_CONTROL) */
 
-#endif  /* __CROS_EC_POWER_H */
+#endif /* __CROS_EC_POWER_H */
diff --git a/include/power/alderlake_slg4bd44540.h b/include/power/alderlake_slg4bd44540.h
index 387a583240..20a85053fd 100644
--- a/include/power/alderlake_slg4bd44540.h
+++ b/include/power/alderlake_slg4bd44540.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,13 +12,13 @@
 #define __CROS_EC_ALDERLAKE_SLG4BD44540_H
 
 /* Input state flags. */
-#define IN_PCH_SLP_S3_DEASSERTED  POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
-#define IN_PCH_SLP_S4_DEASSERTED  POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED)
+#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
+#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED)
 #define IN_PCH_SLP_SUS_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_SUS_DEASSERTED)
 
-#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3_DEASSERTED | \
-				  IN_PCH_SLP_S4_DEASSERTED | \
-				  IN_PCH_SLP_SUS_DEASSERTED)
+#define IN_ALL_PM_SLP_DEASSERTED                               \
+	(IN_PCH_SLP_S3_DEASSERTED | IN_PCH_SLP_S4_DEASSERTED | \
+	 IN_PCH_SLP_SUS_DEASSERTED)
 
 #define IN_PGOOD_ALL_CORE POWER_SIGNAL_MASK(X86_DSW_DPWROK)
 
diff --git a/zephyr/projects/skyrim/include/gpio_map.h b/include/power/amd_x86.h
index ca1272a9ed..57011d97df 100644
--- a/zephyr/projects/skyrim/include/gpio_map.h
+++ b/include/power/amd_x86.h
@@ -1,13 +1,16 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#ifndef __ZEPHYR_GPIO_MAP_H
-#define __ZEPHYR_GPIO_MAP_H
+#ifndef __CROS_EC_POWER_AMD_X86_H_
+#define __CROS_EC_POWER_AMD_X86_H_
 
-#include <zephyr/devicetree.h>
-#include <gpio_signal.h>
+/*
+ * In legacy EC-OS, the power signals are defined as part of
+ * the board include headers, but with Zephyr, this is common.
+ */
+#if defined(CONFIG_ZEPHYR) && defined(CONFIG_AP_X86_AMD)
 
 /* Power input signals */
 enum power_signal {
@@ -21,8 +24,6 @@ enum power_signal {
 	POWER_SIGNAL_COUNT,
 };
 
-#define GPIO_ENTERING_RW	GPIO_UNIMPLEMENTED
-#define GPIO_PCH_SYS_PWROK	GPIO_UNIMPLEMENTED
-#define GPIO_PCH_SLP_S0_L	GPIO_PCH_SLP_S3_L
+#endif
 
-#endif /* __ZEPHYR_GPIO_MAP_H */
+#endif /* __CROS_EC_POWER_AMD_X86_H_ */
diff --git a/include/power/apollolake.h b/include/power/apollolake.h
index cc864f26c3..d0931a6b84 100644
--- a/include/power/apollolake.h
+++ b/include/power/apollolake.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,16 +12,15 @@
  * Input state flags.
  * TODO: Normalize the power signal masks from board defines to SoC headers.
  */
-#define IN_RSMRST_N	POWER_SIGNAL_MASK(X86_RSMRST_N)
-#define IN_ALL_SYS_PG	POWER_SIGNAL_MASK(X86_ALL_SYS_PG)
-#define IN_SLP_S3_N	POWER_SIGNAL_MASK(X86_SLP_S3_N)
-#define IN_SLP_S4_N	POWER_SIGNAL_MASK(X86_SLP_S4_N)
+#define IN_RSMRST_N POWER_SIGNAL_MASK(X86_RSMRST_N)
+#define IN_ALL_SYS_PG POWER_SIGNAL_MASK(X86_ALL_SYS_PG)
+#define IN_SLP_S3_N POWER_SIGNAL_MASK(X86_SLP_S3_N)
+#define IN_SLP_S4_N POWER_SIGNAL_MASK(X86_SLP_S4_N)
 #define IN_PCH_SLP_S4_DEASSERTED IN_SLP_S4_N
-#define IN_SUSPWRDNACK	POWER_SIGNAL_MASK(X86_SUSPWRDNACK)
-#define IN_SUS_STAT_N	POWER_SIGNAL_MASK(X86_SUS_STAT_N)
+#define IN_SUSPWRDNACK POWER_SIGNAL_MASK(X86_SUSPWRDNACK)
+#define IN_SUS_STAT_N POWER_SIGNAL_MASK(X86_SUS_STAT_N)
 
-#define IN_ALL_PM_SLP_DEASSERTED (IN_SLP_S3_N | \
-				  IN_SLP_S4_N)
+#define IN_ALL_PM_SLP_DEASSERTED (IN_SLP_S3_N | IN_SLP_S4_N)
 
 #define IN_PGOOD_ALL_CORE (IN_RSMRST_N)
 
@@ -34,16 +33,16 @@
 
 enum power_signal {
 #ifdef CONFIG_POWER_S0IX
-	X86_SLP_S0_N,		/* PCH  -> SLP_S0_L */
+	X86_SLP_S0_N, /* PCH  -> SLP_S0_L */
 #endif
-	X86_SLP_S3_N,		/* PCH  -> SLP_S3_L */
-	X86_SLP_S4_N,		/* PCH  -> SLP_S4_L */
-	X86_SUSPWRDNACK,	/* PCH  -> SUSPWRDNACK */
-
-	X86_ALL_SYS_PG,		/* PMIC -> PMIC_EC_PWROK_OD */
-	X86_RSMRST_N,		/* PMIC -> PMIC_EC_RSMRST_ODL */
-	X86_PGOOD_PP3300,	/* PMIC -> PP3300_PG_OD */
-	X86_PGOOD_PP5000,	/* PMIC -> PP5000_PG_OD */
+	X86_SLP_S3_N, /* PCH  -> SLP_S3_L */
+	X86_SLP_S4_N, /* PCH  -> SLP_S4_L */
+	X86_SUSPWRDNACK, /* PCH  -> SUSPWRDNACK */
+
+	X86_ALL_SYS_PG, /* PMIC -> PMIC_EC_PWROK_OD */
+	X86_RSMRST_N, /* PMIC -> PMIC_EC_RSMRST_ODL */
+	X86_PGOOD_PP3300, /* PMIC -> PP3300_PG_OD */
+	X86_PGOOD_PP5000, /* PMIC -> PP5000_PG_OD */
 
 	/* Number of X86 signals */
 	POWER_SIGNAL_COUNT
diff --git a/include/power/cannonlake.h b/include/power/cannonlake.h
index a056a96ec8..53e9ba2325 100644
--- a/include/power/cannonlake.h
+++ b/include/power/cannonlake.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,18 +9,19 @@
 #define __CROS_EC_CANNONLAKE_H
 
 /* Input state flags. */
-#define IN_PCH_SLP_S3_DEASSERTED  POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
-#define IN_PCH_SLP_S4_DEASSERTED  POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED)
+#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
+#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED)
 #define IN_PCH_SLP_SUS_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_SUS_DEASSERTED)
 
-#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3_DEASSERTED | \
-				  IN_PCH_SLP_S4_DEASSERTED | \
-				  IN_PCH_SLP_SUS_DEASSERTED)
+#define IN_ALL_PM_SLP_DEASSERTED                               \
+	(IN_PCH_SLP_S3_DEASSERTED | IN_PCH_SLP_S4_DEASSERTED | \
+	 IN_PCH_SLP_SUS_DEASSERTED)
 
 #define IN_PGOOD_ALL_CORE POWER_SIGNAL_MASK(X86_PMIC_DPWROK)
 
-#define IN_ALL_S0 (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED | \
-		   PP5000_PGOOD_POWER_SIGNAL_MASK)
+#define IN_ALL_S0                                       \
+	(IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED | \
+	 PP5000_PGOOD_POWER_SIGNAL_MASK)
 
 #define CHIPSET_G3S5_POWERUP_SIGNAL IN_PCH_SLP_SUS_DEASSERTED
 
diff --git a/include/power/cometlake-discrete.h b/include/power/cometlake-discrete.h
index ae1d51c32b..430cb02dce 100644
--- a/include/power/cometlake-discrete.h
+++ b/include/power/cometlake-discrete.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/power/cometlake.h b/include/power/cometlake.h
index 0f48346c9e..405fe7f0d7 100644
--- a/include/power/cometlake.h
+++ b/include/power/cometlake.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,19 +9,21 @@
 #define __CROS_EC_COMETLAKE_H
 
 /* Input state flags. */
-#define IN_PCH_SLP_S3_DEASSERTED  POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
-#define IN_PCH_SLP_S4_DEASSERTED  POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED)
+#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
+#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED)
 
-#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3_DEASSERTED | \
-				  IN_PCH_SLP_S4_DEASSERTED)
+#define IN_ALL_PM_SLP_DEASSERTED \
+	(IN_PCH_SLP_S3_DEASSERTED | IN_PCH_SLP_S4_DEASSERTED)
 
 #define IN_PGOOD_ALL_CORE POWER_SIGNAL_MASK(X86_RSMRST_L_PGOOD)
 
-#define IN_ALL_S0 (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED | \
-		   PP5000_PGOOD_POWER_SIGNAL_MASK)
+#define IN_ALL_S0                                       \
+	(IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED | \
+	 PP5000_PGOOD_POWER_SIGNAL_MASK)
 
-#define CHIPSET_G3S5_POWERUP_SIGNAL (POWER_SIGNAL_MASK(X86_RSMRST_L_PGOOD) | \
-	POWER_SIGNAL_MASK(X86_PP5000_A_PGOOD))
+#define CHIPSET_G3S5_POWERUP_SIGNAL              \
+	(POWER_SIGNAL_MASK(X86_RSMRST_L_PGOOD) | \
+	 POWER_SIGNAL_MASK(X86_PP5000_A_PGOOD))
 
 #define CHARGER_INITIALIZED_DELAY_MS 100
 #define CHARGER_INITIALIZED_TRIES 40
diff --git a/include/power/falconlite.h b/include/power/falconlite.h
index 3c0baeff66..6afbbfbb94 100644
--- a/include/power/falconlite.h
+++ b/include/power/falconlite.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/power/icelake.h b/include/power/icelake.h
index 95460ae80d..6a08efbb42 100644
--- a/include/power/icelake.h
+++ b/include/power/icelake.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,13 +11,13 @@
 #include "stdbool.h"
 
 /* Input state flags. */
-#define IN_PCH_SLP_S3_DEASSERTED  POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
-#define IN_PCH_SLP_S4_DEASSERTED  POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED)
+#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
+#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED)
 #define IN_PCH_SLP_SUS_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_SUS_DEASSERTED)
 
-#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3_DEASSERTED | \
-				  IN_PCH_SLP_S4_DEASSERTED | \
-				  IN_PCH_SLP_SUS_DEASSERTED)
+#define IN_ALL_PM_SLP_DEASSERTED                               \
+	(IN_PCH_SLP_S3_DEASSERTED | IN_PCH_SLP_S4_DEASSERTED | \
+	 IN_PCH_SLP_SUS_DEASSERTED)
 
 #define IN_PGOOD_ALL_CORE POWER_SIGNAL_MASK(X86_DSW_DPWROK)
 
diff --git a/include/power/intel_x86.h b/include/power/intel_x86.h
index 45f4a67786..9001cf8d49 100644
--- a/include/power/intel_x86.h
+++ b/include/power/intel_x86.h
@@ -1,11 +1,10 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Intel X86 chipset power control module for Chrome EC */
 
-
 #ifndef __CROS_EC_INTEL_X86_H
 #define __CROS_EC_INTEL_X86_H
 
@@ -33,12 +32,12 @@
 #endif
 
 /* GPIO for power signal */
-#ifdef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#ifdef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 #define SLP_S3_SIGNAL_L VW_SLP_S3_L
 #else
 #define SLP_S3_SIGNAL_L GPIO_PCH_SLP_S3_L
 #endif
-#ifdef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#ifdef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 #define SLP_S4_SIGNAL_L VW_SLP_S4_L
 #else
 #define SLP_S4_SIGNAL_L GPIO_PCH_SLP_S4_L
@@ -49,7 +48,7 @@
  * use SLP_S4's GPIO as a proxy for SLP_S5. This matches old behavior and
  * effectively prevents S4 residency.
  */
-#ifdef CONFIG_HOSTCMD_ESPI_VW_SLP_S5
+#ifdef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S5
 #define SLP_S5_SIGNAL_L VW_SLP_S5_L
 #else
 #define SLP_S5_SIGNAL_L SLP_S4_SIGNAL_L
diff --git a/include/power/meteorlake.h b/include/power/meteorlake.h
index 2e8792de20..aedf9824fc 100644
--- a/include/power/meteorlake.h
+++ b/include/power/meteorlake.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,11 +11,11 @@
 #include "stdbool.h"
 
 /* Input state flags. */
-#define IN_PCH_SLP_S3_DEASSERTED  POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
-#define IN_PCH_SLP_S4_DEASSERTED  POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED)
+#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
+#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED)
 
-#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3_DEASSERTED | \
-				  IN_PCH_SLP_S4_DEASSERTED)
+#define IN_ALL_PM_SLP_DEASSERTED \
+	(IN_PCH_SLP_S3_DEASSERTED | IN_PCH_SLP_S4_DEASSERTED)
 
 #define IN_PGOOD_ALL_CORE POWER_SIGNAL_MASK(X86_RSMRST_L_PGOOD)
 
diff --git a/include/power/mt8186.h b/include/power/mt8186.h
index a2ad5648ed..92eb42eff2 100644
--- a/include/power/mt8186.h
+++ b/include/power/mt8186.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/power/mt8192.h b/include/power/mt8192.h
index 7a992001ab..19f5ce081d 100644
--- a/include/power/mt8192.h
+++ b/include/power/mt8192.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/power/qcom.h b/include/power/qcom.h
index 5f5247fa87..ccf61ab4a5 100644
--- a/include/power/qcom.h
+++ b/include/power/qcom.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/power/skylake.h b/include/power/skylake.h
index c8a656c6c5..4da8ae9ea3 100644
--- a/include/power/skylake.h
+++ b/include/power/skylake.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,13 +12,13 @@
  * Input state flags.
  * TODO: Normalize the power signal masks from board defines to SoC headers.
  */
-#define IN_PCH_SLP_S3_DEASSERTED  POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
-#define IN_PCH_SLP_S4_DEASSERTED  POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED)
+#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
+#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED)
 #define IN_PCH_SLP_SUS_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_SUS_DEASSERTED)
 
-#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3_DEASSERTED | \
-				  IN_PCH_SLP_S4_DEASSERTED | \
-				  IN_PCH_SLP_SUS_DEASSERTED)
+#define IN_ALL_PM_SLP_DEASSERTED                               \
+	(IN_PCH_SLP_S3_DEASSERTED | IN_PCH_SLP_S4_DEASSERTED | \
+	 IN_PCH_SLP_SUS_DEASSERTED)
 
 /*
  * DPWROK is NC / stuffing option on initial boards.
diff --git a/include/power_button.h b/include/power_button.h
index 167ca21e2b..9ff85abe7f 100644
--- a/include/power_button.h
+++ b/include/power_button.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -69,4 +69,11 @@ int64_t get_time_dsw_pwrok(void);
  */
 void board_pwrbtn_to_pch(int level);
 
-#endif  /* __CROS_EC_POWER_BUTTON_H */
+/**
+ * Simulates a power button press.
+ *
+ * @param duration	Simulated power button press duration in ms.
+ */
+void power_button_simulate_press(unsigned int duration);
+
+#endif /* __CROS_EC_POWER_BUTTON_H */
diff --git a/include/power_led.h b/include/power_led.h
index 05ea7ead3c..d488406cac 100644
--- a/include/power_led.h
+++ b/include/power_led.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -28,7 +28,9 @@ void powerled_set_state(enum powerled_state state);
 
 #else
 
-static inline void powerled_set_state(enum powerled_state state) {}
+static inline void powerled_set_state(enum powerled_state state)
+{
+}
 
 #endif
 
diff --git a/include/printf.h b/include/printf.h
index 37c0cc3949..f797ca593e 100644
--- a/include/printf.h
+++ b/include/printf.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,16 +8,17 @@
 #ifndef __CROS_EC_PRINTF_H
 #define __CROS_EC_PRINTF_H
 
-#include <stdarg.h>  /* For va_list */
-#include <stddef.h>  /* For size_t */
+#include <stdarg.h> /* For va_list */
+#include <stdbool.h>
+#include <stddef.h> /* For size_t */
+#include "console.h"
+#include <stdio.h>
 #include "common.h"
 
-/* The declaration of snprintf is changed to crec_snprintf for Zephyr,
- * so include stdio.h from Zephyr.
+/**
+ * Buffer size in bytes large enough to hold the largest possible timestamp.
  */
-#ifdef CONFIG_ZEPHYR
-#include <stdio.h>
-#endif
+#define PRINTF_TIMESTAMP_BUF_SIZE 22
 
 /*
  * Printf formatting: % [flags] [width] [.precision] [length] [type]
@@ -51,23 +52,14 @@
  *   - 'c' - character
  *   - 's' - null-terminated ASCII string
  *   - 'd' - signed integer
- *   - 'i' - signed integer if CONFIG_PRINTF_LEGACY_LI_FORMAT is set (ignore l)
+ *   - 'i' - signed integer (if CONFIG_PRINTF_LONG_IS_32BITS is enabled)
  *   - 'u' - unsigned integer
  *   - 'x' - unsigned integer, print as lower-case hexadecimal
  *   - 'X' - unsigned integer, print as upper-case hexadecimal
  *   - 'b' - unsigned integer, print as binary
- *
- * Special format codes:
- *   - '%ph' - binary data, print as hex; Use HEX_BUF(buffer, size) to encode
- *             parameters.
- *   - '%pP' - raw pointer.
- *   - "%pT" - current time in seconds - interpreted as "%.6T" for precision.
- *           Supply PRINTF_TIMESTAMP_NOW to use the current time, or supply a
- *           pointer to a 64-bit timestamp to print.
+ *   - 'p' - pointer
  */
 
-#ifndef HIDE_EC_STDLIB
-
 /**
  * Print formatted output to a function, like vfprintf()
  *
@@ -84,40 +76,78 @@
 __stdlib_compat int vfnprintf(int (*addchar)(void *context, int c),
 			      void *context, const char *format, va_list args);
 
-#ifndef CONFIG_ZEPHYR
-#define snprintf crec_snprintf
-#define vsnprintf crec_vsnprintf
-#endif
+#ifdef TEST_BUILD
+/**
+ * Converts @val to a string written in @buf. The value is converted from
+ * least-significant digit to most-significant digit, so the pointer returned
+ * does not necessarily point to the start of @buf.
+ *
+ * This function shouldn't be used directly; it's a helper function for other
+ * printf functions and only exposed for testing.
+ *
+ * @param[out] buf Destination buffer
+ * @param[in] buf_len Length of @buf in bytes
+ * @param[in] val Value to convert
+ * @param[in] precision Fixed point precision; -1 disables fixed point
+ * @param[in] base Base
+ * @param[in] uppercase true to print hex characters uppercase
+ * @return pointer to start of string on success (not necessarily the start of
+ * @buf).
+ * @return NULL on error
+ */
+char *uint64_to_str(char *buf, int buf_len, uint64_t val, int precision,
+		    int base, bool uppercase);
+#endif /* TEST_BUILD */
+
+/**
+ * Print timestamp as string to the provided buffer.
+ *
+ * Guarantees NUL-termination if size != 0.
+ *
+ * @param[out] str Destination string
+ * @param[in] size Size of @str in bytes
+ * @param[in] timestamp Timestamp
+ * @return Length of string written to @str, not including terminating NUL.
+ * @return -EC_ERROR_OVERFLOW when @str buffer is not large enough. @str[0]
+ * is set to '\0'.
+ * @return -EC_ERROR_INVAL when @size is 0.
+ */
+int snprintf_timestamp(char *str, size_t size, uint64_t timestamp);
 
 /**
- * Print formatted outut to a string.
+ * Print the current time as a string to the provided buffer.
  *
- * Guarantees null-termination if size!=0.
+ * Guarantees NUL-termination if size != 0.
  *
- * @param str		Destination string
- * @param size		Size of destination in bytes
- * @param format	Format string
- * @return EC_SUCCESS, or EC_ERROR_OVERFLOW if the output was truncated.
+ * @param[out] str Destination string
+ * @param[in] size Size of @str in bytes
+ * @return Length of string written to @str, not including terminating NUL.
+ * @return -EC_ERROR_OVERFLOW when @str buffer is not large enough. @str[0]
+ * is set to '\0'.
+ * @return -EC_ERROR_INVAL when @size is 0.
  */
-__attribute__((__format__(__printf__, 3, 4)))
-__stdlib_compat int crec_snprintf(char *str, size_t size, const char *format,
-				  ...);
+int snprintf_timestamp_now(char *str, size_t size);
 
 /**
- * Print formatted output to a string.
+ * Prints bytes as a hex string in the provided buffer.
  *
- * Guarantees null-termination if size!=0.
+ * Guarantees NUL-termination if size != 0.
  *
- * @param str		Destination string
- * @param size		Size of destination in bytes
- * @param format	Format string
- * @param args		Parameters
- * @return The string length written to str, or a negative value on error.
- *         The negative values can be -EC_ERROR_INVAL or -EC_ERROR_OVERFLOW.
+ * @param[out] str Destination string
+ * @param[in] size Size of @str in bytes
+ * @param[in] params Data to print
+ * @return Length of string written to @str, not including terminating NUL.
+ * @return -EC_ERROR_OVERFLOW when @str buffer is not large enough.
+ * @return -EC_ERROR_INVAL when @size is 0.
  */
-__stdlib_compat int crec_vsnprintf(char *str, size_t size, const char *format,
-				   va_list args);
+int snprintf_hex_buffer(char *str, size_t size,
+			const struct hex_buffer_params *params);
 
-#endif  /* !HIDE_EC_STDLIB */
+/**
+ * @param[in] num_bytes
+ * @return number of bytes needed to store @num_bytes as a string (including
+ * terminating '\0').
+ */
+size_t hex_str_buf_size(size_t num_bytes);
 
-#endif  /* __CROS_EC_PRINTF_H */
+#endif /* __CROS_EC_PRINTF_H */
diff --git a/include/producer.h b/include/producer.h
index b6a04883d6..81ef93ecf9 100644
--- a/include/producer.h
+++ b/include/producer.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/include/pwm.h b/include/pwm.h
index 401d3dc0ec..2ac46b3812 100644
--- a/include/pwm.h
+++ b/include/pwm.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -39,34 +39,33 @@ void pwm_set_duty(enum pwm_channel ch, int percent);
  */
 int pwm_get_duty(enum pwm_channel ch);
 
-
 /* Flags for PWM config table */
 
 /**
  * PWM output signal is inverted, so 100% duty means always low
  */
-#define PWM_CONFIG_ACTIVE_LOW		BIT(0)
+#define PWM_CONFIG_ACTIVE_LOW BIT(0)
 /**
  * PWM channel has a fan controller with a tach input and can auto-adjust
  * its duty cycle to produce a given fan RPM.
  */
-#define PWM_CONFIG_HAS_RPM_MODE		BIT(1)
+#define PWM_CONFIG_HAS_RPM_MODE BIT(1)
 /**
  * PWM clock select alternate source.  The actual clock and alternate
  * source are chip dependent.
  */
-#define PWM_CONFIG_ALT_CLOCK		BIT(2)
+#define PWM_CONFIG_ALT_CLOCK BIT(2)
 /**
  * PWM channel has a complementary output signal which should be enabled in
  * addition to the primary output.
  */
-#define PWM_CONFIG_COMPLEMENTARY_OUTPUT	BIT(3)
+#define PWM_CONFIG_COMPLEMENTARY_OUTPUT BIT(3)
 /**
  * PWM channel must stay active in low-power idle, if enabled.
  */
-#define PWM_CONFIG_DSLEEP		BIT(4)
+#define PWM_CONFIG_DSLEEP BIT(4)
 /**
  * PWM channel's IO type is open-drain, if enabled. (default IO is push-pull.)
  */
-#define PWM_CONFIG_OPEN_DRAIN		BIT(5)
-#endif  /* __CROS_EC_PWM_H */
+#define PWM_CONFIG_OPEN_DRAIN BIT(5)
+#endif /* __CROS_EC_PWM_H */
diff --git a/include/pwr_defs.h b/include/pwr_defs.h
index c01e602397..499a5b00e4 100644
--- a/include/pwr_defs.h
+++ b/include/pwr_defs.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/queue.h b/include/queue.h
index 6cf72563cb..6e7d4abbf8 100644
--- a/include/queue.h
+++ b/include/queue.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -75,9 +75,9 @@ struct queue {
 
 	struct queue_policy const *policy;
 
-	size_t  buffer_units; /* size of buffer (in units) */
-	size_t  buffer_units_mask; /* size of buffer (in units) - 1*/
-	size_t  unit_bytes;   /* size of unit   (in byte) */
+	size_t buffer_units; /* size of buffer (in units) */
+	size_t buffer_units_mask; /* size of buffer (in units) - 1*/
+	size_t unit_bytes; /* size of unit   (in byte) */
 	uint8_t *buffer;
 };
 
@@ -86,14 +86,14 @@ struct queue {
  * and state structure.  This macro creates a compound literal that can be used
  * to statically initialize a queue.
  */
-#define QUEUE(SIZE, TYPE, POLICY)				\
-	((struct queue) {					\
-		.state        = &((struct queue_state){}),	\
-		.policy       = &POLICY,			\
+#define QUEUE(SIZE, TYPE, POLICY)                                             \
+	((struct queue){                                                      \
+		.state = &((struct queue_state){}),                           \
+		.policy = &POLICY,                                            \
 		.buffer_units = BUILD_CHECK_INLINE(SIZE, POWER_OF_TWO(SIZE)), \
-		.buffer_units_mask = SIZE - 1,			\
-		.unit_bytes   = sizeof(TYPE),			\
-		.buffer       = (uint8_t *) &((TYPE[SIZE]){}),	\
+		.buffer_units_mask = SIZE - 1,                                \
+		.unit_bytes = sizeof(TYPE),                                   \
+		.buffer = (uint8_t *)&((TYPE[SIZE]){}),                       \
 	})
 
 /* Initialize the queue to empty state. */
@@ -143,7 +143,7 @@ void queue_next(struct queue const *q, struct queue_iterator *it);
  * buffer units.
  */
 struct queue_chunk {
-	size_t  count;
+	size_t count;
 	void *buffer;
 };
 
@@ -206,12 +206,8 @@ size_t queue_add_unit(struct queue const *q, const void *src);
 size_t queue_add_units(struct queue const *q, const void *src, size_t count);
 
 /* Add multiple units to queue using supplied memcpy. */
-size_t queue_add_memcpy(struct queue const *q,
-			const void *src,
-			size_t count,
-			void *(*memcpy)(void *dest,
-					const void *src,
-					size_t n));
+size_t queue_add_memcpy(struct queue const *q, const void *src, size_t count,
+			void *(*memcpy)(void *dest, const void *src, size_t n));
 
 /* Remove one unit from the begin of the queue. */
 size_t queue_remove_unit(struct queue const *q, void *dest);
@@ -220,27 +216,18 @@ size_t queue_remove_unit(struct queue const *q, void *dest);
 size_t queue_remove_units(struct queue const *q, void *dest, size_t count);
 
 /* Remove multiple units from the begin of the queue using supplied memcpy. */
-size_t queue_remove_memcpy(struct queue const *q,
-			   void *dest,
-			   size_t count,
-			   void *(*memcpy)(void *dest,
-					   const void *src,
+size_t queue_remove_memcpy(struct queue const *q, void *dest, size_t count,
+			   void *(*memcpy)(void *dest, const void *src,
 					   size_t n));
 
 /* Peek (return but don't remove) the count elements starting with the i'th. */
-size_t queue_peek_units(struct queue const *q,
-			void *dest,
-			size_t i,
+size_t queue_peek_units(struct queue const *q, void *dest, size_t i,
 			size_t count);
 
 /* Peek (return but don't remove) the count elements starting with the i'th. */
-size_t queue_peek_memcpy(struct queue const *q,
-			 void *dest,
-			 size_t i,
-			 size_t count,
-			 void *(*memcpy)(void *dest,
-				const void *src,
-				size_t n));
+size_t
+queue_peek_memcpy(struct queue const *q, void *dest, size_t i, size_t count,
+		  void *(*memcpy)(void *dest, const void *src, size_t n));
 
 /*
  * These macros will statically select the queue functions based on the number
@@ -248,28 +235,28 @@ size_t queue_peek_memcpy(struct queue const *q,
  * and remove functions are much faster than calling the equivalent generic
  * version with a count of one.
  */
-#define QUEUE_ADD_UNITS(q, src, count)					\
-	({								\
-		size_t result;						\
-									\
-		if (count == 1)						\
-			result = queue_add_unit(q, src);		\
-		else							\
-			result = queue_add_units(q, src, count);	\
-									\
-		result;							\
+#define QUEUE_ADD_UNITS(q, src, count)                           \
+	({                                                       \
+		size_t result;                                   \
+                                                                 \
+		if (count == 1)                                  \
+			result = queue_add_unit(q, src);         \
+		else                                             \
+			result = queue_add_units(q, src, count); \
+                                                                 \
+		result;                                          \
 	})
 
-#define QUEUE_REMOVE_UNITS(q, dest, count)				\
-	({								\
-		size_t result;						\
-									\
-		if (count == 1)						\
-			result = queue_remove_unit(q, dest);		\
-		else							\
-			result = queue_remove_units(q, dest, count);	\
-									\
-		result;							\
+#define QUEUE_REMOVE_UNITS(q, dest, count)                           \
+	({                                                           \
+		size_t result;                                       \
+                                                                     \
+		if (count == 1)                                      \
+			result = queue_remove_unit(q, dest);         \
+		else                                                 \
+			result = queue_remove_units(q, dest, count); \
+                                                                     \
+		result;                                              \
 	})
 
 #endif /* __CROS_EC_QUEUE_H */
diff --git a/include/queue_policies.h b/include/queue_policies.h
index b9d698072f..aceb477ef6 100644
--- a/include/queue_policies.h
+++ b/include/queue_policies.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -27,7 +27,7 @@ struct queue_policy_direct {
 void queue_add_direct(struct queue_policy const *policy, size_t count);
 void queue_remove_direct(struct queue_policy const *policy, size_t count);
 
-#define QUEUE_POLICY_DIRECT(PRODUCER, CONSUMER)			\
+#define QUEUE_POLICY_DIRECT(PRODUCER, CONSUMER) \
 	((struct queue_policy_direct const) {			\
 		.policy = {					\
 			.add    = queue_add_direct,		\
@@ -37,7 +37,7 @@ void queue_remove_direct(struct queue_policy const *policy, size_t count);
 		.consumer = &CONSUMER,				\
 	})
 
-#define QUEUE_DIRECT(SIZE, TYPE, PRODUCER, CONSUMER)			\
+#define QUEUE_DIRECT(SIZE, TYPE, PRODUCER, CONSUMER) \
 	QUEUE(SIZE, TYPE, QUEUE_POLICY_DIRECT(PRODUCER, CONSUMER).policy)
 
 /*
diff --git a/include/regulator.h b/include/regulator.h
index 9dae7233c1..680239593e 100644
--- a/include/regulator.h
+++ b/include/regulator.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/reset_flag_desc.inc b/include/reset_flag_desc.inc
index ed3ce69a0d..a29f8d8d83 100644
--- a/include/reset_flag_desc.inc
+++ b/include/reset_flag_desc.inc
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/rgb_keyboard.h b/include/rgb_keyboard.h
index e795389225..56a3e09a91 100644
--- a/include/rgb_keyboard.h
+++ b/include/rgb_keyboard.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,16 +10,16 @@
 #include "stddef.h"
 
 /* Use this instead of '3' for readability where applicable. */
-#define SIZE_OF_RGB		sizeof(struct rgb_s)
+#define SIZE_OF_RGB sizeof(struct rgb_s)
 
-#define RGBKBD_MAX_GCC_LEVEL	0xff
-#define RGBKBD_MAX_SCALE	0xff
+#define RGBKBD_MAX_GCC_LEVEL 0xff
+#define RGBKBD_MAX_SCALE 0xff
 
-#define RGBKBD_CTX_TO_GRID(ctx)	((ctx) - &rgbkbds[0])
+#define RGBKBD_CTX_TO_GRID(ctx) ((ctx) - &rgbkbds[0])
 
 struct rgbkbd_cfg {
 	/* Driver for LED IC */
-	const struct rgbkbd_drv * const drv;
+	const struct rgbkbd_drv *const drv;
 	/* SPI/I2C port (i.e. index of spi_devices[], i2c_ports[]) */
 	union {
 		const uint8_t i2c;
@@ -50,7 +50,7 @@ void rgbkbd_register_init_setting(const struct rgbkbd_init *setting);
 
 struct rgbkbd {
 	/* Static configuration */
-	const struct rgbkbd_cfg * const cfg;
+	const struct rgbkbd_cfg *const cfg;
 	/* Current state of the port */
 	enum rgbkbd_state state;
 	/* Buffer containing color info for each dot. */
@@ -85,8 +85,8 @@ struct rgbkbd_drv {
 	 * @param len    Length of LEDs to be set.
 	 * @return enum ec_error_list
 	 */
-	int (*set_scale)(struct rgbkbd *ctx, uint8_t offset,
-			 struct rgb_s scale, uint8_t len);
+	int (*set_scale)(struct rgbkbd *ctx, uint8_t offset, struct rgb_s scale,
+			 uint8_t len);
 	/**
 	 * Set global current control.
 	 *
@@ -98,24 +98,24 @@ struct rgbkbd_drv {
 
 /* Represents a position of an LED in RGB matrix. */
 struct rgbkbd_coord {
-	uint8_t y: 3;
-	uint8_t x: 5;
+	uint8_t y : 3;
+	uint8_t x : 5;
 };
 
- /*
-  * For optimization, LED coordinates are encoded in LED IDs. This saves us one
-  * translation.
-  */
+/*
+ * For optimization, LED coordinates are encoded in LED IDs. This saves us one
+ * translation.
+ */
 union rgbkbd_coord_u8 {
 	uint8_t u8;
 	struct rgbkbd_coord coord;
 };
 
-#define RGBKBD_COORD(x,y)	((x) << 3 | (y))
+#define RGBKBD_COORD(x, y) ((x) << 3 | (y))
 /* Delimiter for rgbkbd_map data */
-#define RGBKBD_DELM		0xff
+#define RGBKBD_DELM 0xff
 /* Non-existent entry indicator for rgbkbd_table */
-#define RGBKBD_NONE		0x00
+#define RGBKBD_NONE 0x00
 
 /*
  * The matrix consists of multiple grids:
@@ -154,6 +154,12 @@ extern const uint8_t rgbkbd_hsize;
 extern const uint8_t rgbkbd_vsize;
 
 /*
+ * rgbkbd_type describes the rgb kb type supported.
+ * i.e. Number of zones and number of LEDs
+ */
+extern enum ec_rgbkbd_type rgbkbd_type;
+
+/*
  * rgbkbd_map describes a mapping from key IDs to LED IDs.
  *
  * Multiple keys can be mapped to one LED and one key can be mapped to multiple
diff --git a/include/rma_auth.h b/include/rma_auth.h
index 0a4d7c7e71..2ad9299fed 100644
--- a/include/rma_auth.h
+++ b/include/rma_auth.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,16 +10,16 @@
 
 #include <stdint.h>
 
-#include "common.h"  /* For __packed. */
+#include "common.h" /* For __packed. */
 
 /* Current challenge protocol version */
 #define RMA_CHALLENGE_VERSION 0
 
 /* Getters and setters for version_key_id byte */
 #define RMA_CHALLENGE_VKID_BYTE(version, keyid) \
-	(((version) << 6) | ((keyid) & 0x3f))
+	(((version) << 6) | ((keyid)&0x3f))
 #define RMA_CHALLENGE_GET_VERSION(vkidbyte) ((vkidbyte) >> 6)
-#define RMA_CHALLENGE_GET_KEY_ID(vkidbyte) ((vkidbyte) & 0x3f)
+#define RMA_CHALLENGE_GET_KEY_ID(vkidbyte) ((vkidbyte)&0x3f)
 
 #define RMA_DEVICE_ID_SIZE 8
 
diff --git a/include/rollback.h b/include/rollback.h
index 8e439eaac3..55cff3a534 100644
--- a/include/rollback.h
+++ b/include/rollback.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -71,4 +71,4 @@ int board_get_entropy(void *buffer, int len);
 
 #endif
 
-#endif  /* __CROS_EC_ROLLBACK_H */
+#endif /* __CROS_EC_ROLLBACK_H */
diff --git a/include/rsa.h b/include/rsa.h
index 60d56711ca..bbc3795c68 100644
--- a/include/rsa.h
+++ b/include/rsa.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -45,23 +45,21 @@
 /* RSA public key definition, VBoot2 packing */
 struct rsa_public_key {
 	uint32_t size;
-	uint32_t n0inv;           /* -1 / n[0] mod 2^32 */
-	uint32_t n[RSANUMWORDS];  /* modulus as little endian array */
+	uint32_t n0inv; /* -1 / n[0] mod 2^32 */
+	uint32_t n[RSANUMWORDS]; /* modulus as little endian array */
 	uint32_t rr[RSANUMWORDS]; /* R^2 as little endian array */
 };
 #else
 /* RSA public key definition */
 struct rsa_public_key {
-	uint32_t n[RSANUMWORDS];  /* modulus as little endian array */
+	uint32_t n[RSANUMWORDS]; /* modulus as little endian array */
 	uint32_t rr[RSANUMWORDS]; /* R^2 as little endian array */
-	uint32_t n0inv;           /* -1 / n[0] mod 2^32 */
+	uint32_t n0inv; /* -1 / n[0] mod 2^32 */
 };
 #endif
 
-int rsa_verify(const struct rsa_public_key *key,
-	       const uint8_t *signature,
-	       const uint8_t *sha,
-	       uint32_t *workbuf32);
+int rsa_verify(const struct rsa_public_key *key, const uint8_t *signature,
+	       const uint8_t *sha, uint32_t *workbuf32);
 
 #endif /* !__ASSEMBLER__ */
 
diff --git a/include/rtc.h b/include/rtc.h
index cff1ee0f64..0225801e71 100644
--- a/include/rtc.h
+++ b/include/rtc.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,14 +10,14 @@
 
 #include "common.h"
 
-#define SECS_PER_MINUTE     60
-#define SECS_PER_HOUR       (60 * SECS_PER_MINUTE)
-#define SECS_PER_DAY        (24 * SECS_PER_HOUR)
-#define SECS_PER_WEEK       (7 * SECS_PER_DAY)
-#define SECS_PER_YEAR       (365 * SECS_PER_DAY)
+#define SECS_PER_MINUTE 60
+#define SECS_PER_HOUR (60 * SECS_PER_MINUTE)
+#define SECS_PER_DAY (24 * SECS_PER_HOUR)
+#define SECS_PER_WEEK (7 * SECS_PER_DAY)
+#define SECS_PER_YEAR (365 * SECS_PER_DAY)
 /* The seconds elapsed from 01-01-1970 to 01-01-2000 */
-#define SECS_TILL_YEAR_2K   (946684800)
-#define IS_LEAP_YEAR(x)     \
+#define SECS_TILL_YEAR_2K (946684800)
+#define IS_LEAP_YEAR(x) \
 	(((x) % 4 == 0) && (((x) % 100 != 0) || ((x) % 400 == 0)))
 
 struct calendar_date {
diff --git a/include/rwsig.h b/include/rwsig.h
index 425618490b..4abecfddd0 100644
--- a/include/rwsig.h
+++ b/include/rwsig.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -77,22 +77,21 @@ void rwsig_jump_now(void);
 #endif /* ! CONFIG_RO_PUBKEY_SIZE */
 #ifndef CONFIG_RO_PUBKEY_ADDR
 #ifdef CONFIG_RWSIG_TYPE_RWSIG
-#define CONFIG_RO_PUBKEY_STORAGE_OFF (CONFIG_RO_STORAGE_OFF		\
-				      + CONFIG_RO_SIZE			\
-				      - CONFIG_RO_PUBKEY_SIZE)
+#define CONFIG_RO_PUBKEY_STORAGE_OFF \
+	(CONFIG_RO_STORAGE_OFF + CONFIG_RO_SIZE - CONFIG_RO_PUBKEY_SIZE)
 
 /* The pubkey resides at the end of the RO image */
-#define CONFIG_RO_PUBKEY_ADDR (CONFIG_PROGRAM_MEMORY_BASE		\
-			       + CONFIG_EC_PROTECTED_STORAGE_OFF	\
-			       + CONFIG_RO_PUBKEY_STORAGE_OFF)
+#define CONFIG_RO_PUBKEY_ADDR                                           \
+	(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_EC_PROTECTED_STORAGE_OFF + \
+	 CONFIG_RO_PUBKEY_STORAGE_OFF)
 #else
 /*
  * usbpd1 type assumes pubkey location at the end of first half of flash,
  * which might actually be in the PSTATE region.
  */
-#define CONFIG_RO_PUBKEY_ADDR (CONFIG_PROGRAM_MEMORY_BASE	\
-			       + (CONFIG_FLASH_SIZE_BYTES / 2)	\
-			       - CONFIG_RO_PUBKEY_SIZE)
+#define CONFIG_RO_PUBKEY_ADDR                                         \
+	(CONFIG_PROGRAM_MEMORY_BASE + (CONFIG_FLASH_SIZE_BYTES / 2) - \
+	 CONFIG_RO_PUBKEY_SIZE)
 #endif
 #endif /* CONFIG_RO_PUBKEY_ADDR */
 
@@ -108,19 +107,19 @@ void rwsig_jump_now(void);
 #endif
 #endif /* ! CONFIG_RW_SIG_SIZE */
 /* The signature resides at the end of each RW copy */
-#define RW_SIG_OFFSET		(CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE)
-#define RW_A_ADDR		(CONFIG_PROGRAM_MEMORY_BASE +		\
-				 CONFIG_EC_WRITABLE_STORAGE_OFF +	\
-				 CONFIG_RW_STORAGE_OFF)
+#define RW_SIG_OFFSET (CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE)
+#define RW_A_ADDR                                                      \
+	(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_EC_WRITABLE_STORAGE_OFF + \
+	 CONFIG_RW_STORAGE_OFF)
 /* Assume the layout is same as RW_A and it sits right after RW_A */
-#define RW_B_ADDR		(CONFIG_PROGRAM_MEMORY_BASE + \
-				 CONFIG_EC_WRITABLE_STORAGE_OFF + \
-				 CONFIG_RW_B_STORAGE_OFF)
+#define RW_B_ADDR                                                      \
+	(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_EC_WRITABLE_STORAGE_OFF + \
+	 CONFIG_RW_B_STORAGE_OFF)
 #ifndef CONFIG_RW_SIG_ADDR
-#define CONFIG_RW_SIG_ADDR	(RW_A_ADDR + RW_SIG_OFFSET)
+#define CONFIG_RW_SIG_ADDR (RW_A_ADDR + RW_SIG_OFFSET)
 #endif
 #ifndef CONFIG_RW_B_SIG_ADDR
-#define CONFIG_RW_B_SIG_ADDR	(RW_B_ADDR + RW_SIG_OFFSET)
+#define CONFIG_RW_B_SIG_ADDR (RW_B_ADDR + RW_SIG_OFFSET)
 #endif
 
 #endif /* __CROS_EC_RWSIG_H */
diff --git a/include/sfdp.h b/include/sfdp.h
index 087708d799..e1cd6372f2 100644
--- a/include/sfdp.h
+++ b/include/sfdp.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,22 +12,20 @@
  * Helper macros to declare and access SFDP defined bitfields at a JEDEC SFDP
  * defined double word (32b) granularity.
  */
-#define SFDP_DEFINE_BITMASK_32(name, hi, lo)                              \
-	static const uint32_t name = (((1ULL << ((hi) - (lo) + 1)) - 1UL) \
-				      << (lo));
-#define SFDP_DEFINE_SHIFT_32(name, hi, lo) \
-	static const size_t name = (lo);
-#define SFDP_DEFINE_BITFIELD(name, hi, lo)            \
-	SFDP_DEFINE_BITMASK_32(name ## _MASK, hi, lo) \
-	SFDP_DEFINE_SHIFT_32(name ## _SHIFT, hi, lo)
-#define SFDP_GET_BITFIELD(name, dw) \
-	(((dw) & name ## _MASK) >> name ## _SHIFT)
+#define SFDP_DEFINE_BITMASK_32(name, hi, lo) \
+	static const uint32_t name =         \
+		(((1ULL << ((hi) - (lo) + 1)) - 1UL) << (lo));
+#define SFDP_DEFINE_SHIFT_32(name, hi, lo) static const size_t name = (lo);
+#define SFDP_DEFINE_BITFIELD(name, hi, lo)          \
+	SFDP_DEFINE_BITMASK_32(name##_MASK, hi, lo) \
+	SFDP_DEFINE_SHIFT_32(name##_SHIFT, hi, lo)
+#define SFDP_GET_BITFIELD(name, dw) (((dw)&name##_MASK) >> name##_SHIFT)
 
 /**
  * Helper macros to construct SFDP defined double words (32b). Note reserved or
  * unused fields must always be set to all 1's.
  */
-#define SFDP_BITFIELD(name, value) (((value) << name ## _SHIFT) & name ## _MASK)
+#define SFDP_BITFIELD(name, value) (((value) << name##_SHIFT) & name##_MASK)
 #define SFDP_UNUSED(hi, lo) (((1ULL << ((hi) - (lo) + 1)) - 1UL) << (lo))
 
 /******************************************************************************/
@@ -85,10 +83,9 @@ SFDP_DEFINE_BITFIELD(SFDP_HEADER_DW1_S, 7, 0);
 SFDP_DEFINE_BITFIELD(SFDP_HEADER_DW2_NPH, 23, 16);
 SFDP_DEFINE_BITFIELD(SFDP_HEADER_DW2_SFDP_MAJOR, 15, 8);
 SFDP_DEFINE_BITFIELD(SFDP_HEADER_DW2_SFDP_MINOR, 7, 0);
-#define SFDP_HEADER_DWORD_2(nph, major, minor)              \
-	(SFDP_UNUSED(31, 24) |                              \
-	 SFDP_BITFIELD(SFDP_HEADER_DW2_NPH, nph) |          \
-	 SFDP_BITFIELD(SFDP_HEADER_DW2_SFDP_MAJOR, major) | \
+#define SFDP_HEADER_DWORD_2(nph, major, minor)                           \
+	(SFDP_UNUSED(31, 24) | SFDP_BITFIELD(SFDP_HEADER_DW2_NPH, nph) | \
+	 SFDP_BITFIELD(SFDP_HEADER_DW2_SFDP_MAJOR, major) |              \
 	 SFDP_BITFIELD(SFDP_HEADER_DW2_SFDP_MINOR, minor))
 
 /******************************************************************************/
@@ -98,7 +95,7 @@ SFDP_DEFINE_BITFIELD(SFDP_HEADER_DW2_SFDP_MINOR, 7, 0);
 /* In SFDP v1.0, the only reserved ID was the Basic Flash Parameter Table ID of
  * 0x00. Otherwise this field must be set to the vendor's manufacturer ID. Note,
  * the spec does not call out how to report the manufacturer bank number. */
- #define BASIC_FLASH_PARAMETER_TABLE_1_0_ID 0x00
+#define BASIC_FLASH_PARAMETER_TABLE_1_0_ID 0x00
 
 /*
  * SFDP v1.0: Parameter Header 1st DWORD
@@ -178,8 +175,8 @@ SFDP_DEFINE_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW1_ID_LSB, 7, 0);
  */
 SFDP_DEFINE_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW2_ID_MSB, 31, 24);
 SFDP_DEFINE_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW2_PTP, 23, 0);
-#define SFDP_1_5_PARAMETER_HEADER_DWORD_2(idmsb, ptp)                     \
-	(SFDP_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW2_ID_MSB, idmsb) |     \
+#define SFDP_1_5_PARAMETER_HEADER_DWORD_2(idmsb, ptp)                 \
+	(SFDP_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW2_ID_MSB, idmsb) | \
 	 SFDP_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW2_PTP, ptp))
 
 /******************************************************************************/
@@ -226,20 +223,20 @@ SFDP_DEFINE_BITFIELD(BFPT_1_0_DW1_WREN_OPCODE_SELECT, 4, 4);
 SFDP_DEFINE_BITFIELD(BFPT_1_0_DW1_WREN_REQ, 3, 3);
 SFDP_DEFINE_BITFIELD(BFPT_1_0_DW1_WRITE_GRANULARITY, 2, 2);
 SFDP_DEFINE_BITFIELD(BFPT_1_0_DW1_4KIB_AVAILABILITY, 1, 0);
-#define BFPT_1_0_DWORD_1(fr114, fr144, fr122, dtr, addr, fr112,              \
-				    rm4kb, wrenop, wrenrq, wrgr,  ergr)      \
-	(SFDP_UNUSED(31, 23) |                                               \
-	 SFDP_BITFIELD(BFPT_1_0_DW1_1_1_4_SUPPORTED, fr114) |                \
-	 SFDP_BITFIELD(BFPT_1_0_DW1_1_4_4_SUPPORTED, fr144) |                \
-	 SFDP_BITFIELD(BFPT_1_0_DW1_1_2_2_SUPPORTED, fr122) |                \
-	 SFDP_BITFIELD(BFPT_1_0_DW1_DTR_SUPPORTED, dtr) |                    \
-	 SFDP_BITFIELD(BFPT_1_0_DW1_ADDR_BYTES, addr) |                      \
-	 SFDP_BITFIELD(BFPT_1_0_DW1_1_1_2_SUPPORTED, fr112) |                \
-	 SFDP_BITFIELD(BFPT_1_0_DW1_4KIB_ERASE_OPCODE, rm4kb) |              \
-	 SFDP_UNUSED(7, 5) |                                                 \
-	 SFDP_BITFIELD(BFPT_1_0_DW1_WREN_OPCODE_SELECT, wrenop) |            \
-	 SFDP_BITFIELD(BFPT_1_0_DW1_WREN_REQ, wrenrq) |                      \
-	 SFDP_BITFIELD(BFPT_1_0_DW1_WRITE_GRANULARITY, wrgr) |               \
+#define BFPT_1_0_DWORD_1(fr114, fr144, fr122, dtr, addr, fr112, rm4kb, wrenop, \
+			 wrenrq, wrgr, ergr)                                   \
+	(SFDP_UNUSED(31, 23) |                                                 \
+	 SFDP_BITFIELD(BFPT_1_0_DW1_1_1_4_SUPPORTED, fr114) |                  \
+	 SFDP_BITFIELD(BFPT_1_0_DW1_1_4_4_SUPPORTED, fr144) |                  \
+	 SFDP_BITFIELD(BFPT_1_0_DW1_1_2_2_SUPPORTED, fr122) |                  \
+	 SFDP_BITFIELD(BFPT_1_0_DW1_DTR_SUPPORTED, dtr) |                      \
+	 SFDP_BITFIELD(BFPT_1_0_DW1_ADDR_BYTES, addr) |                        \
+	 SFDP_BITFIELD(BFPT_1_0_DW1_1_1_2_SUPPORTED, fr112) |                  \
+	 SFDP_BITFIELD(BFPT_1_0_DW1_4KIB_ERASE_OPCODE, rm4kb) |                \
+	 SFDP_UNUSED(7, 5) |                                                   \
+	 SFDP_BITFIELD(BFPT_1_0_DW1_WREN_OPCODE_SELECT, wrenop) |              \
+	 SFDP_BITFIELD(BFPT_1_0_DW1_WREN_REQ, wrenrq) |                        \
+	 SFDP_BITFIELD(BFPT_1_0_DW1_WRITE_GRANULARITY, wrgr) |                 \
 	 SFDP_BITFIELD(BFPT_1_0_DW1_4KIB_AVAILABILITY, ergr))
 
 /* Basic Flash Parameter Table v1.0 2nd DWORD
@@ -270,13 +267,12 @@ SFDP_DEFINE_BITFIELD(BFPT_1_0_DW3_1_1_4_WAIT_STATE_CLOCKS, 20, 16);
 SFDP_DEFINE_BITFIELD(BFPT_1_0_DW3_1_4_4_OPCODE, 15, 8);
 SFDP_DEFINE_BITFIELD(BFPT_1_0_DW3_1_4_4_MODE_BITS, 7, 5);
 SFDP_DEFINE_BITFIELD(BFPT_1_0_DW3_1_4_4_WAIT_STATE_CLOCKS, 4, 0);
-#define BFPT_1_0_DWORD_3(fr114op, fr114mb, fr114dc,                \
-				    fr144op, fr144mb, fr144dc)     \
-	(SFDP_BITFIELD(BFPT_1_0_DW3_1_1_4_OPCODE, fr114op) |       \
-	 SFDP_BITFIELD(BFPT_1_0_DW3_1_1_4_MODE_BITS, fr114mb) |    \
-	 SFDP_BITFIELD(BFPT_1_0_DW3_1_1_4_WAIT_STATE_CLOCKS, fr114dc) | \
-	 SFDP_BITFIELD(BFPT_1_0_DW3_1_4_4_OPCODE, fr144op) |       \
-	 SFDP_BITFIELD(BFPT_1_0_DW3_1_4_4_MODE_BITS, fr144mb) |    \
+#define BFPT_1_0_DWORD_3(fr114op, fr114mb, fr114dc, fr144op, fr144mb, fr144dc) \
+	(SFDP_BITFIELD(BFPT_1_0_DW3_1_1_4_OPCODE, fr114op) |                   \
+	 SFDP_BITFIELD(BFPT_1_0_DW3_1_1_4_MODE_BITS, fr114mb) |                \
+	 SFDP_BITFIELD(BFPT_1_0_DW3_1_1_4_WAIT_STATE_CLOCKS, fr114dc) |        \
+	 SFDP_BITFIELD(BFPT_1_0_DW3_1_4_4_OPCODE, fr144op) |                   \
+	 SFDP_BITFIELD(BFPT_1_0_DW3_1_4_4_MODE_BITS, fr144mb) |                \
 	 SFDP_BITFIELD(BFPT_1_0_DW3_1_4_4_WAIT_STATE_CLOCKS, fr144dc))
 
 /* Basic Flash Parameter Table v1.0 4th DWORD
@@ -294,13 +290,12 @@ SFDP_DEFINE_BITFIELD(BFPT_1_0_DW4_1_2_2_WAIT_STATE_CLOCKS, 20, 16);
 SFDP_DEFINE_BITFIELD(BFPT_1_0_DW4_1_1_2_OPCODE, 15, 8);
 SFDP_DEFINE_BITFIELD(BFPT_1_0_DW4_1_1_2_MODE_BITS, 7, 5);
 SFDP_DEFINE_BITFIELD(BFPT_1_0_DW4_1_1_2_WAIT_STATE_CLOCKS, 4, 0);
-#define BFPT_1_0_DWORD_4(fr122op, fr122mb, fr122dc,                \
-				    fr112op, fr112mb, fr112dc)     \
-	(SFDP_BITFIELD(BFPT_1_0_DW4_1_2_2_OPCODE, fr122op) |       \
-	 SFDP_BITFIELD(BFPT_1_0_DW4_1_2_2_MODE_BITS, fr122mb) |    \
-	 SFDP_BITFIELD(BFPT_1_0_DW4_1_2_2_WAIT_STATE_CLOCKS, fr122dc) | \
-	 SFDP_BITFIELD(BFPT_1_0_DW4_1_1_2_OPCODE, fr112op) |       \
-	 SFDP_BITFIELD(BFPT_1_0_DW4_1_1_2_MODE_BITS, fr112mb) |    \
+#define BFPT_1_0_DWORD_4(fr122op, fr122mb, fr122dc, fr112op, fr112mb, fr112dc) \
+	(SFDP_BITFIELD(BFPT_1_0_DW4_1_2_2_OPCODE, fr122op) |                   \
+	 SFDP_BITFIELD(BFPT_1_0_DW4_1_2_2_MODE_BITS, fr122mb) |                \
+	 SFDP_BITFIELD(BFPT_1_0_DW4_1_2_2_WAIT_STATE_CLOCKS, fr122dc) |        \
+	 SFDP_BITFIELD(BFPT_1_0_DW4_1_1_2_OPCODE, fr112op) |                   \
+	 SFDP_BITFIELD(BFPT_1_0_DW4_1_1_2_MODE_BITS, fr112mb) |                \
 	 SFDP_BITFIELD(BFPT_1_0_DW4_1_1_2_WAIT_STATE_CLOCKS, fr112dc))
 
 /* Basic Flash Parameter Table v1.0 5th DWORD
@@ -328,9 +323,9 @@ SFDP_DEFINE_BITFIELD(BFPT_1_0_DW5_2_2_2_SUPPORTED, 0, 0);
 SFDP_DEFINE_BITFIELD(BFPT_1_0_DW6_2_2_2_OPCODE, 31, 24);
 SFDP_DEFINE_BITFIELD(BFPT_1_0_DW6_2_2_2_MODE_BITS, 23, 21);
 SFDP_DEFINE_BITFIELD(BFPT_1_0_DW6_2_2_2_WAIT_STATE_CLOCKS, 20, 16);
-#define BFPT_1_0_DWORD_6(fr222op, fr222mb, fr222dc)                \
-	(SFDP_BITFIELD(BFPT_1_0_DW6_2_2_2_OPCODE, fr222op) |       \
-	 SFDP_BITFIELD(BFPT_1_0_DW6_2_2_2_MODE_BITS, fr222mb) |    \
+#define BFPT_1_0_DWORD_6(fr222op, fr222mb, fr222dc)                     \
+	(SFDP_BITFIELD(BFPT_1_0_DW6_2_2_2_OPCODE, fr222op) |            \
+	 SFDP_BITFIELD(BFPT_1_0_DW6_2_2_2_MODE_BITS, fr222mb) |         \
 	 SFDP_BITFIELD(BFPT_1_0_DW6_2_2_2_WAIT_STATE_CLOCKS, fr222dc) | \
 	 SFDP_UNUSED(15, 0))
 
@@ -344,9 +339,9 @@ SFDP_DEFINE_BITFIELD(BFPT_1_0_DW6_2_2_2_WAIT_STATE_CLOCKS, 20, 16);
 SFDP_DEFINE_BITFIELD(BFPT_1_0_DW7_4_4_4_OPCODE, 31, 24);
 SFDP_DEFINE_BITFIELD(BFPT_1_0_DW7_4_4_4_MODE_BITS, 23, 21);
 SFDP_DEFINE_BITFIELD(BFPT_1_0_DW7_4_4_4_WAIT_STATE_CLOCKS, 20, 16);
-#define BFPT_1_0_DWORD_7(fr444op, fr444mb, fr444dc)                \
-	(SFDP_BITFIELD(BFPT_1_0_DW7_4_4_4_OPCODE, fr444op) |       \
-	 SFDP_BITFIELD(BFPT_1_0_DW7_4_4_4_MODE_BITS, fr444mb) |    \
+#define BFPT_1_0_DWORD_7(fr444op, fr444mb, fr444dc)                     \
+	(SFDP_BITFIELD(BFPT_1_0_DW7_4_4_4_OPCODE, fr444op) |            \
+	 SFDP_BITFIELD(BFPT_1_0_DW7_4_4_4_MODE_BITS, fr444mb) |         \
 	 SFDP_BITFIELD(BFPT_1_0_DW7_4_4_4_WAIT_STATE_CLOCKS, fr444dc) | \
 	 SFDP_UNUSED(15, 0))
 
@@ -419,17 +414,16 @@ SFDP_DEFINE_BITFIELD(BFPT_1_5_DW10_ERASE_2_TIME_CNT, 15, 11);
 SFDP_DEFINE_BITFIELD(BFPT_1_5_DW10_ERASE_1_TIME_UNIT, 10, 9);
 SFDP_DEFINE_BITFIELD(BFPT_1_5_DW10_ERASE_1_TIME_CNT, 8, 4);
 SFDP_DEFINE_BITFIELD(BFPT_1_5_DW10_ERASE_TIME_MAX_MULT, 3, 0);
-#define BFPT_1_5_DWORD_10(rm4unit, rm4count, rm3unit,               \
-			  rm3count, rm2unit, rm2count,              \
-			  rm1unit, rm1count, maxmult)               \
-	(SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_4_TIME_UNIT, rm4unit) |  \
-	 SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_4_TIME_CNT, rm4count) |  \
-	 SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_3_TIME_UNIT, rm3unit) |  \
-	 SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_3_TIME_CNT, rm3count) |  \
-	 SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_2_TIME_UNIT, rm2unit) |  \
-	 SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_2_TIME_CNT, rm2count) |  \
-	 SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_1_TIME_UNIT, rm1unit) |  \
-	 SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_1_TIME_CNT, rm1count) |  \
+#define BFPT_1_5_DWORD_10(rm4unit, rm4count, rm3unit, rm3count, rm2unit, \
+			  rm2count, rm1unit, rm1count, maxmult)          \
+	(SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_4_TIME_UNIT, rm4unit) |       \
+	 SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_4_TIME_CNT, rm4count) |       \
+	 SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_3_TIME_UNIT, rm3unit) |       \
+	 SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_3_TIME_CNT, rm3count) |       \
+	 SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_2_TIME_UNIT, rm2unit) |       \
+	 SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_2_TIME_CNT, rm2count) |       \
+	 SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_1_TIME_UNIT, rm1unit) |       \
+	 SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_1_TIME_CNT, rm1count) |       \
 	 SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_TIME_MAX_MULT, maxmult))
 
 /* Basic Flash Parameter Table v1.5 11th DWORD
@@ -464,18 +458,12 @@ SFDP_DEFINE_BITFIELD(BFPT_1_5_DW11_WR_TIME_MAX_MULT, 3, 0);
 #define BFPT_1_5_DWORD_11(crmunit, crmcount, mrbunit, mrbcount, initunit,  \
 			  initcount, pgwrunit, pgwrcount, pagesz, maxmult) \
 	(SFDP_UNUSED(31, 31) |                                             \
-	 SFDP_BITFIELD(BFPT_1_5_DW11_CHIP_ERASE_TIME_UNIT,                 \
-		       crmunit) |                                          \
-	 SFDP_BITFIELD(BFPT_1_5_DW11_CHIP_ERASE_TIME_CNT,                  \
-		       crmcount) |                                         \
-	 SFDP_BITFIELD(BFPT_1_5_DW11_MORE_BYTE_WR_TIME_UNIT,               \
-		       mrbunit) |                                          \
-	 SFDP_BITFIELD(BFPT_1_5_DW11_MORE_BYTE_WR_TIME_CNT,                \
-		       mrbcount) |                                         \
-	 SFDP_BITFIELD(BFPT_1_5_DW11_INIT_BYTE_WR_TIME_UNIT,               \
-		       initunit) |                                         \
-	 SFDP_BITFIELD(BFPT_1_5_DW11_INIT_BYTE_WR_TIME_CNT,                \
-		       initcount) |                                        \
+	 SFDP_BITFIELD(BFPT_1_5_DW11_CHIP_ERASE_TIME_UNIT, crmunit) |      \
+	 SFDP_BITFIELD(BFPT_1_5_DW11_CHIP_ERASE_TIME_CNT, crmcount) |      \
+	 SFDP_BITFIELD(BFPT_1_5_DW11_MORE_BYTE_WR_TIME_UNIT, mrbunit) |    \
+	 SFDP_BITFIELD(BFPT_1_5_DW11_MORE_BYTE_WR_TIME_CNT, mrbcount) |    \
+	 SFDP_BITFIELD(BFPT_1_5_DW11_INIT_BYTE_WR_TIME_UNIT, initunit) |   \
+	 SFDP_BITFIELD(BFPT_1_5_DW11_INIT_BYTE_WR_TIME_CNT, initcount) |   \
 	 SFDP_BITFIELD(BFPT_1_5_DW11_PAGE_WR_TIME_UNIT, pgwrunit) |        \
 	 SFDP_BITFIELD(BFPT_1_5_DW11_PAGE_WR_TIME_CNT, pgwrcount) |        \
 	 SFDP_BITFIELD(BFPT_1_5_DW11_PAGE_SIZE, pagesz) |                  \
@@ -532,26 +520,21 @@ SFDP_DEFINE_BITFIELD(BFPT_1_5_DW12_SUSP_WR_MAX_LAT_CNT, 17, 13);
 SFDP_DEFINE_BITFIELD(BFPT_1_5_DW12_WR_RES_TO_SUSP_LAT_CNT, 12, 9);
 SFDP_DEFINE_BITFIELD(BFPT_1_5_DW12_PROHIB_OPS_DURING_RM_SUSP, 7, 4);
 SFDP_DEFINE_BITFIELD(BFPT_1_5_DW12_PROHIB_OPS_DURING_WR_SUSP, 3, 0);
-#define BFPT_1_5_DWORD_12(unsup, susprmlatun, susprmlatcnt, rmressusplatcnt, \
-			  suspwrmaxlatunit, suspwrmaxlatcnt, wrressuspcnt,   \
-			  prohibopsrmsusp, prohibopswrsusp)                  \
-	(SFDP_BITFIELD(BFPT_1_5_DW12_SUSPEND_UNSUPPORTED, unsup) |           \
-	 SFDP_BITFIELD(BFPT_1_5_DW12_SUSP_RM_MAX_LAT_UNIT,                   \
-		       susprmlatun) |                                        \
-	 SFDP_BITFIELD(BFPT_1_5_DW12_SUSP_RM_MAX_LAT_CNT,                    \
-		       susprmlatcnt) |                                       \
-	 SFDP_BITFIELD(BFPT_1_5_DW12_RM_RES_TO_SUSP_LAT_CNT,                 \
-		       rmressusplatcnt) |                                    \
-	 SFDP_BITFIELD(BFPT_1_5_DW12_SUSP_WR_MAX_LAT_UNIT,                   \
-		       suspwrmaxlatunit) |                                   \
-	 SFDP_BITFIELD(BFPT_1_5_DW12_SUSP_WR_MAX_LAT_CNT,                    \
-		       suspwrmaxlatcnt) |                                    \
-	 SFDP_BITFIELD(BFPT_1_5_DW12_WR_RES_TO_SUSP_LAT_CNT,                 \
-		       wrressuspcnt) |                                       \
-	 SFDP_UNUSED(8, 8) |                                                 \
-	 SFDP_BITFIELD(BFPT_1_5_DW12_PROHIB_OPS_DURING_RM_SUSP,              \
-		       prohibopsrmsusp) |                                    \
-	 SFDP_BITFIELD(BFPT_1_5_DW12_PROHIB_OPS_DURING_WR_SUSP,              \
+#define BFPT_1_5_DWORD_12(unsup, susprmlatun, susprmlatcnt, rmressusplatcnt,   \
+			  suspwrmaxlatunit, suspwrmaxlatcnt, wrressuspcnt,     \
+			  prohibopsrmsusp, prohibopswrsusp)                    \
+	(SFDP_BITFIELD(BFPT_1_5_DW12_SUSPEND_UNSUPPORTED, unsup) |             \
+	 SFDP_BITFIELD(BFPT_1_5_DW12_SUSP_RM_MAX_LAT_UNIT, susprmlatun) |      \
+	 SFDP_BITFIELD(BFPT_1_5_DW12_SUSP_RM_MAX_LAT_CNT, susprmlatcnt) |      \
+	 SFDP_BITFIELD(BFPT_1_5_DW12_RM_RES_TO_SUSP_LAT_CNT,                   \
+		       rmressusplatcnt) |                                      \
+	 SFDP_BITFIELD(BFPT_1_5_DW12_SUSP_WR_MAX_LAT_UNIT, suspwrmaxlatunit) | \
+	 SFDP_BITFIELD(BFPT_1_5_DW12_SUSP_WR_MAX_LAT_CNT, suspwrmaxlatcnt) |   \
+	 SFDP_BITFIELD(BFPT_1_5_DW12_WR_RES_TO_SUSP_LAT_CNT, wrressuspcnt) |   \
+	 SFDP_UNUSED(8, 8) |                                                   \
+	 SFDP_BITFIELD(BFPT_1_5_DW12_PROHIB_OPS_DURING_RM_SUSP,                \
+		       prohibopsrmsusp) |                                      \
+	 SFDP_BITFIELD(BFPT_1_5_DW12_PROHIB_OPS_DURING_WR_SUSP,                \
 		       prohibopswrsusp))
 
 /* Basic Flash Parameter Table v1.5 13th DWORD
@@ -600,12 +583,10 @@ SFDP_DEFINE_BITFIELD(BFPT_1_5_DW14_POWER_UP_TIME_CNT, 12, 8);
 SFDP_DEFINE_BITFIELD(BFPT_1_5_DW14_BUSY_FLAGS, 7, 2);
 #define BFPT_1_5_DWORD_14(pwrdwnunsup, pwrdwnop, pwrupop, pwrupunit, pwrupcnt, \
 			  busypollflags)                                       \
-	(SFDP_BITFIELD(BFPT_1_5_DW14_POWER_DOWN_UNSUPPORTED,                   \
-			pwrdwnunsup) |                                         \
+	(SFDP_BITFIELD(BFPT_1_5_DW14_POWER_DOWN_UNSUPPORTED, pwrdwnunsup) |    \
 	 SFDP_BITFIELD(BFPT_1_5_DW14_POWER_DOWN_OPCODE, pwrdwnop) |            \
 	 SFDP_BITFIELD(BFPT_1_5_DW14_POWER_UP_OPCODE, pwrupop) |               \
-	 SFDP_BITFIELD(BFPT_1_5_DW14_POWER_UP_TIME_UNIT,                       \
-		       pwrupunit) |                                            \
+	 SFDP_BITFIELD(BFPT_1_5_DW14_POWER_UP_TIME_UNIT, pwrupunit) |          \
 	 SFDP_BITFIELD(BFPT_1_5_DW14_POWER_UP_TIME_CNT, pwrupcnt) |            \
 	 SFDP_BITFIELD(BFPT_1_5_DW14_BUSY_FLAGS, busypollflags) |              \
 	 SFDP_UNUSED(1, 0))
@@ -702,7 +683,6 @@ SFDP_DEFINE_BITFIELD(BFPT_1_5_DW15_4_4_4_EXIT, 3, 0);
 	 SFDP_BITFIELD(BFPT_1_5_DW15_4_4_4_ENTRY, fr444entry) |              \
 	 SFDP_BITFIELD(BFPT_1_5_DW15_4_4_4_EXIT, fr444exit))
 
-
 /* Basic Flash Parameter Table v1.5 16th DWORD
  * -------------------------------------------
  * <31:24> : Enter 4-Byte Addressing, where
@@ -804,4 +784,4 @@ SFDP_DEFINE_BITFIELD(BFPT_1_5_DW16_STATUS_REG_1, 6, 0);
 	 SFDP_UNUSED(7, 7) |                                  \
 	 SFDP_BITFIELD(BFPT_1_5_DW16_STATUS_REG_1, statusreg1))
 
-#endif  /* __CROS_EC_SFDP_H */
+#endif /* __CROS_EC_SFDP_H */
diff --git a/include/sha1.h b/include/sha1.h
index 42c0f2612f..12d277d1ac 100644
--- a/include/sha1.h
+++ b/include/sha1.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,7 +11,7 @@
 #include "common.h"
 #ifdef HOST_TOOLS_BUILD
 #include <string.h>
-#define DIV_ROUND_UP(x, y) (((x) + ((y) - 1)) / (y))
+#define DIV_ROUND_UP(x, y) (((x) + ((y)-1)) / (y))
 #else
 #include "util.h"
 #endif
@@ -33,4 +33,4 @@ void sha1_init(struct sha1_ctx *ctx);
 void sha1_update(struct sha1_ctx *ctx, const uint8_t *data, uint32_t len);
 uint8_t *sha1_final(struct sha1_ctx *ctx);
 
-#endif  /* __CROS_EC_SHA1_H */
+#endif /* __CROS_EC_SHA1_H */
diff --git a/include/sha256.h b/include/sha256.h
index 130a666788..d1193c2661 100644
--- a/include/sha256.h
+++ b/include/sha256.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,7 +26,7 @@ struct sha256_ctx {
 	uint32_t tot_len;
 	uint32_t len;
 	uint8_t block[2 * SHA256_BLOCK_SIZE];
-	uint8_t buf[SHA256_DIGEST_SIZE];  /* Used to store the final digest. */
+	uint8_t buf[SHA256_DIGEST_SIZE]; /* Used to store the final digest. */
 };
 #endif
 
@@ -37,4 +37,4 @@ uint8_t *SHA256_final(struct sha256_ctx *ctx);
 void hmac_SHA256(uint8_t *output, const uint8_t *key, const int key_len,
 		 const uint8_t *message, const int message_len);
 
-#endif  /* __CROS_EC_SHA256_H */
+#endif /* __CROS_EC_SHA256_H */
diff --git a/include/shared_mem.h b/include/shared_mem.h
index eadac22a48..307ce9f5e5 100644
--- a/include/shared_mem.h
+++ b/include/shared_mem.h
@@ -1,4 +1,4 @@
-/* Copyright 2011 The Chromium OS Authors. All rights reserved.
+/* Copyright 2011 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -46,10 +46,10 @@ int shared_mem_size(void);
  */
 int shared_mem_acquire(int size, char **dest_ptr);
 
-#define SHARED_MEM_ACQUIRE_CHECK(size, dest_ptr) \
-	({ \
-		SHARED_MEM_CHECK_SIZE(size);				\
-		shared_mem_acquire((size), (dest_ptr));			\
+#define SHARED_MEM_ACQUIRE_CHECK(size, dest_ptr)        \
+	({                                              \
+		SHARED_MEM_CHECK_SIZE(size);            \
+		shared_mem_acquire((size), (dest_ptr)); \
 	})
 
 /**
@@ -85,4 +85,4 @@ extern struct shm_buffer *free_buf_chain;
 extern struct shm_buffer *allocced_buf_chain;
 #endif
 
-#endif  /* __CROS_EC_SHARED_MEM_H */
+#endif /* __CROS_EC_SHARED_MEM_H */
diff --git a/include/software_panic.h b/include/software_panic.h
index 2702c6dc92..d5eb8685b3 100644
--- a/include/software_panic.h
+++ b/include/software_panic.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,23 +9,23 @@
 #define __CROS_EC_SOFTWARE_PANIC_H
 
 /* Holds software panic reason PANIC_SW_* */
-#define SOFTWARE_PANIC_REASON_REG	r4
-#define SOFTWARE_PANIC_INFO_REG		r5
+#define SOFTWARE_PANIC_REASON_REG r4
+#define SOFTWARE_PANIC_INFO_REG r5
 
-#define PANIC_SW_BASE		0xDEAD6660
+#define PANIC_SW_BASE 0xDEAD6660
 
 /* Software panic reasons */
-#define PANIC_SW_DIV_ZERO		(PANIC_SW_BASE + 0)
-#define PANIC_SW_STACK_OVERFLOW		(PANIC_SW_BASE + 1)
-#define PANIC_SW_PD_CRASH		(PANIC_SW_BASE + 2)
-#define PANIC_SW_ASSERT			(PANIC_SW_BASE + 3)
-#define PANIC_SW_WATCHDOG		(PANIC_SW_BASE + 4)
-#define PANIC_SW_BAD_RNG		(PANIC_SW_BASE + 5)
-#define PANIC_SW_PMIC_FAULT		(PANIC_SW_BASE + 6)
+#define PANIC_SW_DIV_ZERO (PANIC_SW_BASE + 0)
+#define PANIC_SW_STACK_OVERFLOW (PANIC_SW_BASE + 1)
+#define PANIC_SW_PD_CRASH (PANIC_SW_BASE + 2)
+#define PANIC_SW_ASSERT (PANIC_SW_BASE + 3)
+#define PANIC_SW_WATCHDOG (PANIC_SW_BASE + 4)
+#define PANIC_SW_BAD_RNG (PANIC_SW_BASE + 5)
+#define PANIC_SW_PMIC_FAULT (PANIC_SW_BASE + 6)
 
 #ifndef __ASSEMBLER__
-extern const char * const panic_sw_reasons[];
+extern const char *const panic_sw_reasons[];
 extern int panic_sw_reason_is_valid(uint32_t vec);
 #endif
 
-#endif  /* __CROS_EC_SOFTWARE_PANIC_H */
+#endif /* __CROS_EC_SOFTWARE_PANIC_H */
diff --git a/include/spi.h b/include/spi.h
index 28fc166f73..965f941fa3 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -89,8 +89,8 @@ int spi_enable(const struct spi_device_t *spi_device, int enable);
  * @param rxlen  number of bytes in rxdata or SPI_READBACK_ALL.
  */
 int spi_transaction(const struct spi_device_t *spi_device,
-		    const uint8_t *txdata, int txlen,
-		    uint8_t *rxdata, int rxlen);
+		    const uint8_t *txdata, int txlen, uint8_t *rxdata,
+		    int rxlen);
 
 /*
  * Similar to spi_transaction(), but hands over to DMA for reading response.
@@ -100,8 +100,8 @@ int spi_transaction(const struct spi_device_t *spi_device,
  * SPI port, it's up to the caller to ensure proper mutual exclusion if needed.
  */
 int spi_transaction_async(const struct spi_device_t *spi_device,
-			  const uint8_t *txdata, int txlen,
-			  uint8_t *rxdata, int rxlen);
+			  const uint8_t *txdata, int txlen, uint8_t *rxdata,
+			  int rxlen);
 
 /* Wait for async response received */
 int spi_transaction_flush(const struct spi_device_t *spi_device);
@@ -131,4 +131,4 @@ static inline void spi_event(enum gpio_signal signal)
 
 #endif
 
-#endif  /* __CROS_EC_SPI_H */
+#endif /* __CROS_EC_SPI_H */
diff --git a/include/spi_flash.h b/include/spi_flash.h
index ca3e796fd3..05fe8c098b 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,40 +12,40 @@
 #define SPI_FLASH_SIZE(x) (1 << (x))
 
 /* SPI flash instructions */
-#define SPI_FLASH_WRITE_ENABLE		0x06
-#define SPI_FLASH_WRITE_DISABLE		0x04
-#define SPI_FLASH_READ_SR1		0x05
-#define SPI_FLASH_READ_SR2		0x35
-#define SPI_FLASH_WRITE_SR		0x01
-#define SPI_FLASH_ERASE_4KB		0x20
-#define SPI_FLASH_ERASE_32KB		0x52
-#define SPI_FLASH_ERASE_64KB		0xD8
-#define SPI_FLASH_ERASE_CHIP		0xC7
-#define SPI_FLASH_READ			0x03
-#define SPI_FLASH_PAGE_PRGRM		0x02
-#define SPI_FLASH_REL_PWRDWN		0xAB
-#define SPI_FLASH_MFR_DEV_ID		0x90
-#define SPI_FLASH_JEDEC_ID		0x9F
-#define SPI_FLASH_UNIQUE_ID		0x4B
-#define SPI_FLASH_SFDP			0x44
-#define SPI_FLASH_ERASE_SEC_REG		0x44
-#define SPI_FLASH_PRGRM_SEC_REG		0x42
-#define SPI_FLASH_READ_SEC_REG		0x48
-#define SPI_FLASH_ENABLE_RESET		0x66
-#define SPI_FLASH_RESET			0x99
+#define SPI_FLASH_WRITE_ENABLE 0x06
+#define SPI_FLASH_WRITE_DISABLE 0x04
+#define SPI_FLASH_READ_SR1 0x05
+#define SPI_FLASH_READ_SR2 0x35
+#define SPI_FLASH_WRITE_SR 0x01
+#define SPI_FLASH_ERASE_4KB 0x20
+#define SPI_FLASH_ERASE_32KB 0x52
+#define SPI_FLASH_ERASE_64KB 0xD8
+#define SPI_FLASH_ERASE_CHIP 0xC7
+#define SPI_FLASH_READ 0x03
+#define SPI_FLASH_PAGE_PRGRM 0x02
+#define SPI_FLASH_REL_PWRDWN 0xAB
+#define SPI_FLASH_MFR_DEV_ID 0x90
+#define SPI_FLASH_JEDEC_ID 0x9F
+#define SPI_FLASH_UNIQUE_ID 0x4B
+#define SPI_FLASH_SFDP 0x44
+#define SPI_FLASH_ERASE_SEC_REG 0x44
+#define SPI_FLASH_PRGRM_SEC_REG 0x42
+#define SPI_FLASH_READ_SEC_REG 0x48
+#define SPI_FLASH_ENABLE_RESET 0x66
+#define SPI_FLASH_RESET 0x99
 
 /* Maximum single write size (in bytes) for the W25Q64FV SPI flash */
-#define SPI_FLASH_MAX_WRITE_SIZE	256
+#define SPI_FLASH_MAX_WRITE_SIZE 256
 
 /*
  * Maximum message size (in bytes) for the W25Q64FV SPI flash
  * Instruction (1) + Address (3) + Data (256) = 260
  * Limited by chip maximum input length of write instruction
  */
-#define SPI_FLASH_MAX_MESSAGE_SIZE	(SPI_FLASH_MAX_WRITE_SIZE + 4)
+#define SPI_FLASH_MAX_MESSAGE_SIZE (SPI_FLASH_MAX_WRITE_SIZE + 4)
 
 /* Maximum single read size in bytes. Limited by size of the message buffer */
-#define SPI_FLASH_MAX_READ_SIZE		(SPI_FLASH_MAX_MESSAGE_SIZE - 4)
+#define SPI_FLASH_MAX_READ_SIZE (SPI_FLASH_MAX_MESSAGE_SIZE - 4)
 
 /* Status register write protect structure */
 enum spi_flash_wp {
@@ -120,7 +120,7 @@ int spi_flash_erase(unsigned int offset, unsigned int bytes);
  * @return EC_SUCCESS, or non-zero if any error.
  */
 int spi_flash_write(unsigned int offset, unsigned int bytes,
-	const uint8_t *data);
+		    const uint8_t *data);
 
 /**
  * Gets the SPI flash JEDEC ID (manufacturer ID, memory type, and capacity)
@@ -185,4 +185,4 @@ int spi_flash_check_protect(unsigned int offset, unsigned int bytes);
  */
 int spi_flash_set_protect(unsigned int offset, unsigned int bytes);
 
-#endif  /* __CROS_EC_SPI_FLASH_H */
+#endif /* __CROS_EC_SPI_FLASH_H */
diff --git a/include/spi_flash_reg.h b/include/spi_flash_reg.h
index a0ffefc721..0d70d6982d 100644
--- a/include/spi_flash_reg.h
+++ b/include/spi_flash_reg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -15,21 +15,21 @@
  * Common register bits for SPI flash. All registers / bits may not be valid
  * for all parts.
  */
-#define SPI_FLASH_SR2_SUS               BIT(7)
-#define SPI_FLASH_SR2_CMP               BIT(6)
-#define SPI_FLASH_SR2_LB3               BIT(5)
-#define SPI_FLASH_SR2_LB2               BIT(4)
-#define SPI_FLASH_SR2_LB1               BIT(3)
-#define SPI_FLASH_SR2_QE                BIT(1)
-#define SPI_FLASH_SR2_SRP1              BIT(0)
-#define SPI_FLASH_SR1_SRP0              BIT(7)
-#define SPI_FLASH_SR1_SEC               BIT(6)
-#define SPI_FLASH_SR1_TB                BIT(5)
-#define SPI_FLASH_SR1_BP2               BIT(4)
-#define SPI_FLASH_SR1_BP1               BIT(3)
-#define SPI_FLASH_SR1_BP0               BIT(2)
-#define SPI_FLASH_SR1_WEL               BIT(1)
-#define SPI_FLASH_SR1_BUSY              BIT(0)
+#define SPI_FLASH_SR2_SUS BIT(7)
+#define SPI_FLASH_SR2_CMP BIT(6)
+#define SPI_FLASH_SR2_LB3 BIT(5)
+#define SPI_FLASH_SR2_LB2 BIT(4)
+#define SPI_FLASH_SR2_LB1 BIT(3)
+#define SPI_FLASH_SR2_QE BIT(1)
+#define SPI_FLASH_SR2_SRP1 BIT(0)
+#define SPI_FLASH_SR1_SRP0 BIT(7)
+#define SPI_FLASH_SR1_SEC BIT(6)
+#define SPI_FLASH_SR1_TB BIT(5)
+#define SPI_FLASH_SR1_BP2 BIT(4)
+#define SPI_FLASH_SR1_BP1 BIT(3)
+#define SPI_FLASH_SR1_BP0 BIT(2)
+#define SPI_FLASH_SR1_WEL BIT(1)
+#define SPI_FLASH_SR1_BUSY BIT(0)
 
 /* SR2 register existence based upon chip */
 #ifdef CONFIG_SPI_FLASH_W25X40
@@ -70,4 +70,4 @@ int spi_flash_reg_to_protect(uint8_t sr1, uint8_t sr2, unsigned int *start,
 int spi_flash_protect_to_reg(unsigned int start, unsigned int len, uint8_t *sr1,
 			     uint8_t *sr2);
 
-#endif  /* __CROS_EC_SPI_FLASH_REG_H */
+#endif /* __CROS_EC_SPI_FLASH_REG_H */
diff --git a/include/spi_nor.h b/include/spi_nor.h
index f0c379cd43..9ffe3ebac9 100644
--- a/include/spi_nor.h
+++ b/include/spi_nor.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -63,32 +63,32 @@ extern const unsigned int spi_nor_devices_used;
 
 /* Industry standard Serial NOR Flash opcodes. All other opcodes are part
  * specific and require SFDP discovery. */
-#define SPI_NOR_OPCODE_WRITE_STATUS  0x01 /* Write Status Register (1 Byte) */
-#define SPI_NOR_OPCODE_PAGE_PROGRAM  0x02 /* Page program */
-#define SPI_NOR_OPCODE_SLOW_READ     0x03 /* Read data (low frequency) */
+#define SPI_NOR_OPCODE_WRITE_STATUS 0x01 /* Write Status Register (1 Byte) */
+#define SPI_NOR_OPCODE_PAGE_PROGRAM 0x02 /* Page program */
+#define SPI_NOR_OPCODE_SLOW_READ 0x03 /* Read data (low frequency) */
 #define SPI_NOR_OPCODE_WRITE_DISABLE 0x04
-#define SPI_NOR_OPCODE_READ_STATUS   0x05 /* Read Status Register */
-#define SPI_NOR_OPCODE_WRITE_ENABLE  0x06
-#define SPI_NOR_OPCODE_FAST_READ     0x0b /* Read data (high frequency) */
-#define SPI_NOR_OPCODE_SFDP          0x5a /* Read JEDEC SFDP */
-#define SPI_NOR_OPCODE_JEDEC_ID      0x9f /* Read JEDEC ID */
-#define SPI_NOR_OPCODE_WREAR         0xc5 /* Write extended address register */
-#define SPI_NOR_OPCODE_CHIP_ERASE    0xc7 /* Erase whole flash chip */
-#define SPI_NOR_OPCODE_RDEAR         0xc8 /* Read extended address register */
+#define SPI_NOR_OPCODE_READ_STATUS 0x05 /* Read Status Register */
+#define SPI_NOR_OPCODE_WRITE_ENABLE 0x06
+#define SPI_NOR_OPCODE_FAST_READ 0x0b /* Read data (high frequency) */
+#define SPI_NOR_OPCODE_SFDP 0x5a /* Read JEDEC SFDP */
+#define SPI_NOR_OPCODE_JEDEC_ID 0x9f /* Read JEDEC ID */
+#define SPI_NOR_OPCODE_WREAR 0xc5 /* Write extended address register */
+#define SPI_NOR_OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */
+#define SPI_NOR_OPCODE_RDEAR 0xc8 /* Read extended address register */
 
 /* Flags for SPI_NOR_OPCODE_READ_STATUS */
-#define SPI_NOR_STATUS_REGISTER_WIP BIT(0)  /* Write in progres */
-#define SPI_NOR_STATUS_REGISTER_WEL BIT(1)  /* Write enabled latch */
+#define SPI_NOR_STATUS_REGISTER_WIP BIT(0) /* Write in progres */
+#define SPI_NOR_STATUS_REGISTER_WEL BIT(1) /* Write enabled latch */
 
 /* If needed in the future this driver can be extended to discover SFDP
  * advertised erase sizes and opcodes for SFDP v1.0+. */
-#define SPI_NOR_DRIVER_SPECIFIED_OPCODE_4KIB_ERASE  0x20
+#define SPI_NOR_DRIVER_SPECIFIED_OPCODE_4KIB_ERASE 0x20
 #define SPI_NOR_DRIVER_SPECIFIED_OPCODE_64KIB_ERASE 0xd8
 
 /* If needed in the future this driver can be extended to discover 4B entry and
  * exit methods for SFDP v1.5+. */
 #define SPI_NOR_DRIVER_SPECIFIED_OPCODE_ENTER_4B 0xb7
-#define SPI_NOR_DRIVER_SPECIFIED_OPCODE_EXIT_4B  0xe9
+#define SPI_NOR_DRIVER_SPECIFIED_OPCODE_EXIT_4B 0xe9
 
 /* JEDEC JEP106AR specifies 9 Manufacturer ID banks, read 12 to be sure. */
 #define SPI_NOR_JEDEC_ID_BANKS 12
@@ -144,8 +144,8 @@ int spi_nor_read_jedec_id(const struct spi_nor_device_t *spi_nor_device,
  * @param data Destination buffer for data.
  * @return ec_error_list (non-zero on error and timeout).
  */
-int spi_nor_read(const struct spi_nor_device_t *spi_nor_device,
-		 uint32_t offset, size_t size, uint8_t *data);
+int spi_nor_read(const struct spi_nor_device_t *spi_nor_device, uint32_t offset,
+		 size_t size, uint8_t *data);
 
 /**
  * Erase flash on the Serial Flash Device.
@@ -181,5 +181,4 @@ int spi_nor_write(const struct spi_nor_device_t *spi_nor_device,
 int spi_nor_write_ear(const struct spi_nor_device_t *spi_nor_device,
 		      const uint8_t value);
 
-
-#endif  /* __CROS_EC_SPI_NOR_H */
+#endif /* __CROS_EC_SPI_NOR_H */
diff --git a/include/stack_trace.h b/include/stack_trace.h
index 52ebe3619f..90d20519b9 100644
--- a/include/stack_trace.h
+++ b/include/stack_trace.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,8 +18,12 @@ void task_register_tracedump(void);
 /* Dump current stack trace */
 void task_dump_trace(void);
 #else
-static inline void task_register_tracedump(void) { }
-static inline void task_dump_trace(void) { }
+static inline void task_register_tracedump(void)
+{
+}
+static inline void task_dump_trace(void)
+{
+}
 #endif
 
-#endif  /* __CROS_EC_STACK_TRACE_H */
+#endif /* __CROS_EC_STACK_TRACE_H */
diff --git a/include/stillness_detector.h b/include/stillness_detector.h
index 65598d4d5c..79de2de79f 100644
--- a/include/stillness_detector.h
+++ b/include/stillness_detector.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/switch.h b/include/switch.h
index e026408af9..97d428e356 100644
--- a/include/switch.h
+++ b/include/switch.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,7 +19,9 @@
  */
 void switch_interrupt(enum gpio_signal signal);
 #else
-static inline void switch_interrupt(enum gpio_signal signal) { }
-#endif  /* !CONFIG_SWITCH */
+static inline void switch_interrupt(enum gpio_signal signal)
+{
+}
+#endif /* !CONFIG_SWITCH */
 
-#endif  /* __CROS_EC_SWITCH_H */
+#endif /* __CROS_EC_SWITCH_H */
diff --git a/include/sysjump.h b/include/sysjump.h
index f5bf5f5a09..7d86df2e61 100644
--- a/include/sysjump.h
+++ b/include/sysjump.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,10 +16,10 @@
  * images.
  */
 
-#define JUMP_DATA_MAGIC 0x706d754a  /* "Jump" */
+#define JUMP_DATA_MAGIC 0x706d754a /* "Jump" */
 #define JUMP_DATA_VERSION 3
-#define JUMP_DATA_SIZE_V1 12  /* Size of version 1 jump data struct */
-#define JUMP_DATA_SIZE_V2 16  /* Size of version 2 jump data struct */
+#define JUMP_DATA_SIZE_V1 12 /* Size of version 1 jump data struct */
+#define JUMP_DATA_SIZE_V2 16 /* Size of version 2 jump data struct */
 
 struct jump_data {
 	/*
@@ -29,19 +29,19 @@ struct jump_data {
 	 */
 
 	/* Fields from version 3 */
-	uint8_t reserved0;    /* (used in proto1 to signal recovery mode) */
-	int struct_size;      /* Size of struct jump_data */
+	uint8_t reserved0; /* (used in proto1 to signal recovery mode) */
+	int struct_size; /* Size of struct jump_data */
 
 	/* Fields from version 2 */
-	int jump_tag_total;   /* Total size of all jump tags */
+	int jump_tag_total; /* Total size of all jump tags */
 
 	/* Fields from version 1 */
 	uint32_t reset_flags; /* Reset flags from the previous boot */
-	int version;          /* Version (JUMP_DATA_VERSION) */
-	int magic;            /* Magic number (JUMP_DATA_MAGIC).  If this
-			       * doesn't match at pre-init time, assume no valid
-			       * data from the previous image.
-			       */
+	int version; /* Version (JUMP_DATA_VERSION) */
+	int magic; /* Magic number (JUMP_DATA_MAGIC).  If this
+		    * doesn't match at pre-init time, assume no valid
+		    * data from the previous image.
+		    */
 };
 
 /**
@@ -49,4 +49,4 @@ struct jump_data {
  */
 struct jump_data *get_jump_data(void);
 
-#endif  /* __CROS_EC_SYSJUMP_IMPL_H */
+#endif /* __CROS_EC_SYSJUMP_IMPL_H */
diff --git a/include/system.h b/include/system.h
index 0fc0206bb3..f55e091e90 100644
--- a/include/system.h
+++ b/include/system.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -89,6 +89,12 @@ void system_enter_hibernate(uint32_t seconds, uint32_t microseconds);
 __test_only void system_common_reset_state(void);
 
 /**
+ * Return the value of reboot_at_shutdown and reset its value, useful for
+ * testing.
+ */
+__test_only enum ec_reboot_cmd system_common_get_reset_reboot_at_shutdown(void);
+
+/**
  * @brief Allow tests to manually set the jump data address.
  *
  * This function allows an override of the location of the jump data (which is
@@ -328,17 +334,17 @@ const char *system_get_build_info(void);
  * Hard reset.  Cuts power to the entire system.  If not present, does a soft
  * reset which just resets the core and on-chip peripherals.
  */
-#define SYSTEM_RESET_HARD               BIT(0)
+#define SYSTEM_RESET_HARD BIT(0)
 /*
  * Preserve existing reset flags.  Used by flash pre-init when it discovers it
  * needs to do a hard reset to clear write protect registers.
  */
-#define SYSTEM_RESET_PRESERVE_FLAGS     BIT(1)
+#define SYSTEM_RESET_PRESERVE_FLAGS BIT(1)
 /*
  * Leave AP off on next reboot, instead of powering it on to do EC software
  * sync.
  */
-#define SYSTEM_RESET_LEAVE_AP_OFF       BIT(2)
+#define SYSTEM_RESET_LEAVE_AP_OFF BIT(2)
 /*
  * Indicate that this was a manually triggered reset.
  */
@@ -346,30 +352,33 @@ const char *system_get_build_info(void);
 /*
  * Wait for reset pin to be driven, rather that resetting ourselves.
  */
-#define SYSTEM_RESET_WAIT_EXT           BIT(4)
+#define SYSTEM_RESET_WAIT_EXT BIT(4)
 /*
  * Indicate that this reset was triggered by an AP watchdog
  */
-#define SYSTEM_RESET_AP_WATCHDOG        BIT(5)
+#define SYSTEM_RESET_AP_WATCHDOG BIT(5)
 /*
  * Stay in RO next reboot, instead of potentially selecting RW during EFS.
  */
-#define SYSTEM_RESET_STAY_IN_RO         BIT(6)
+#define SYSTEM_RESET_STAY_IN_RO BIT(6)
 /*
  * Hibernate reset. Reset EC when wake up from hibernate mode
  * (the most power saving mode).
  */
-#define SYSTEM_RESET_HIBERNATE          BIT(7)
+#define SYSTEM_RESET_HIBERNATE BIT(7)
 
 /**
  * Reset the system.
  *
  * @param flags		Reset flags; see SYSTEM_RESET_* above.
  */
-#ifndef TEST_FUZZ
+#if (defined(TEST_FUZZ) || defined(CONFIG_ZTEST))
+test_mockable
+#else
 noreturn
 #endif
-void system_reset(int flags);
+	void
+	system_reset(int flags);
 
 /**
  * Set a scratchpad register to the specified value.
@@ -440,7 +449,6 @@ __override_proto const char *board_read_serial(void);
  */
 __override_proto int board_write_serial(const char *serial);
 
-
 /**
  * Optional board-level callback functions to read a unique MAC address per
  * chip. Default implementation reads from flash.
@@ -525,7 +533,9 @@ timestamp_t system_get_rtc(void);
 #ifdef CONFIG_RTC
 void print_system_rtc(enum console_channel channel);
 #else
-static inline void print_system_rtc(enum console_channel channel) { }
+static inline void print_system_rtc(enum console_channel channel)
+{
+}
 #endif /* !defined(CONFIG_RTC) */
 
 /**
@@ -538,32 +548,31 @@ enum {
 	/*
 	 * Sleep masks to prevent going in to deep sleep.
 	 */
-	SLEEP_MASK_AP_RUN     = BIT(0), /* the main CPU is running */
-	SLEEP_MASK_UART       = BIT(1), /* UART communication ongoing */
+	SLEEP_MASK_AP_RUN = BIT(0), /* the main CPU is running */
+	SLEEP_MASK_UART = BIT(1), /* UART communication ongoing */
 	SLEEP_MASK_I2C_CONTROLLER = BIT(2), /* I2C controller comms ongoing */
-	SLEEP_MASK_CHARGING   = BIT(3), /* Charging loop ongoing */
-	SLEEP_MASK_USB_PWR    = BIT(4), /* USB power loop ongoing */
-	SLEEP_MASK_USB_PD     = BIT(5), /* USB PD device connected */
-	SLEEP_MASK_SPI        = BIT(6), /* SPI communications ongoing */
+	SLEEP_MASK_CHARGING = BIT(3), /* Charging loop ongoing */
+	SLEEP_MASK_USB_PWR = BIT(4), /* USB power loop ongoing */
+	SLEEP_MASK_USB_PD = BIT(5), /* USB PD device connected */
+	SLEEP_MASK_SPI = BIT(6), /* SPI communications ongoing */
 	SLEEP_MASK_I2C_PERIPHERAL = BIT(7), /* I2C peripheral comms ongoing */
-	SLEEP_MASK_FAN        = BIT(8), /* Fan control loop ongoing */
+	SLEEP_MASK_FAN = BIT(8), /* Fan control loop ongoing */
 	SLEEP_MASK_USB_DEVICE = BIT(9), /* Generic USB device in use */
-	SLEEP_MASK_PWM        = BIT(10), /* PWM output is enabled */
-	SLEEP_MASK_PHYSICAL_PRESENCE  = BIT(11), /* Physical presence
-						    * detection ongoing */
-	SLEEP_MASK_PLL        = BIT(12), /* High-speed PLL in-use */
-	SLEEP_MASK_ADC        = BIT(13), /* ADC conversion ongoing */
-	SLEEP_MASK_EMMC       = BIT(14), /* eMMC emulation ongoing */
-	SLEEP_MASK_FORCE_NO_DSLEEP    = BIT(15), /* Force disable. */
-
+	SLEEP_MASK_PWM = BIT(10), /* PWM output is enabled */
+	SLEEP_MASK_PHYSICAL_PRESENCE = BIT(11), /* Physical presence
+						 * detection ongoing */
+	SLEEP_MASK_PLL = BIT(12), /* High-speed PLL in-use */
+	SLEEP_MASK_ADC = BIT(13), /* ADC conversion ongoing */
+	SLEEP_MASK_EMMC = BIT(14), /* eMMC emulation ongoing */
+	SLEEP_MASK_FORCE_NO_DSLEEP = BIT(15), /* Force disable. */
 
 	/*
 	 * Sleep masks to prevent using slow speed clock in deep sleep.
 	 */
-	SLEEP_MASK_JTAG     = BIT(16), /* JTAG is in use. */
-	SLEEP_MASK_CONSOLE  = BIT(17), /* Console is in use. */
+	SLEEP_MASK_JTAG = BIT(16), /* JTAG is in use. */
+	SLEEP_MASK_CONSOLE = BIT(17), /* Console is in use. */
 
-	SLEEP_MASK_FORCE_NO_LOW_SPEED = BIT(31)  /* Force disable. */
+	SLEEP_MASK_FORCE_NO_LOW_SPEED = BIT(31) /* Force disable. */
 };
 
 /*
@@ -578,10 +587,9 @@ extern atomic_t sleep_mask;
  */
 
 #ifndef CONFIG_LOW_POWER_S0
-#define DEEP_SLEEP_ALLOWED           (!(sleep_mask & 0x0000ffff))
+#define DEEP_SLEEP_ALLOWED (!(sleep_mask & 0x0000ffff))
 #else
-#define DEEP_SLEEP_ALLOWED           (!(sleep_mask & 0x0000ffff & \
-				       (~SLEEP_MASK_AP_RUN)))
+#define DEEP_SLEEP_ALLOWED (!(sleep_mask & 0x0000ffff & (~SLEEP_MASK_AP_RUN)))
 #endif
 #define LOW_SPEED_DEEP_SLEEP_ALLOWED (!(sleep_mask & 0xffff0000))
 
@@ -650,6 +658,13 @@ void disable_deep_sleep(void);
 void enable_deep_sleep(void);
 
 /**
+ * This function is made visible for tests only, it allows overriding the RTC.
+ *
+ * @param seconds
+ */
+void system_set_rtc(uint32_t seconds);
+
+/**
  * Use hibernate module to set up an RTC interrupt at a given
  * time from now
  *
@@ -761,4 +776,4 @@ uint32_t flash_get_rw_offset(enum ec_image copy);
  */
 void system_compensate_rtc(void);
 
-#endif  /* __CROS_EC_SYSTEM_H */
+#endif /* __CROS_EC_SYSTEM_H */
diff --git a/include/tablet_mode.h b/include/tablet_mode.h
index 6ad565628c..e257fedc04 100644
--- a/include/tablet_mode.h
+++ b/include/tablet_mode.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,8 +14,8 @@
 int tablet_get_mode(void);
 
 /* Bit mask of tablet mode trigger */
-#define TABLET_TRIGGER_LID	BIT(0)
-#define TABLET_TRIGGER_BASE	BIT(1)
+#define TABLET_TRIGGER_LID BIT(0)
+#define TABLET_TRIGGER_BASE BIT(1)
 
 /**
  * Set tablet mode state
@@ -56,4 +56,7 @@ void gmr_tablet_switch_disable(void);
  */
 int board_sensor_at_360(void);
 
-#endif  /* __CROS_EC_TABLET_MODE_H */
+/** Reset internal tablet mode state, used for testing. */
+__test_only void tablet_reset(void);
+
+#endif /* __CROS_EC_TABLET_MODE_H */
diff --git a/include/task.h b/include/task.h
index 0343644437..5010900e59 100644
--- a/include/task.h
+++ b/include/task.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,48 +22,47 @@
 #define TASK_EVENT_SYSJUMP_READY BIT(16)
 
 /* Used to signal that IPC layer is available for sending new data */
-#define TASK_EVENT_IPC_READY	BIT(17)
+#define TASK_EVENT_IPC_READY BIT(17)
 
-#define TASK_EVENT_PD_AWAKE	BIT(18)
+#define TASK_EVENT_PD_AWAKE BIT(18)
 
 /* npcx peci event */
-#define TASK_EVENT_PECI_DONE	BIT(19)
+#define TASK_EVENT_PECI_DONE BIT(19)
 
 /* I2C tx/rx interrupt handler completion event. */
 #ifdef CHIP_STM32
-#define TASK_EVENT_I2C_COMPLETION(port) \
-				(1 << ((port) + 20))
-#define TASK_EVENT_I2C_IDLE	(TASK_EVENT_I2C_COMPLETION(0))
-#define TASK_EVENT_MAX_I2C	6
+#define TASK_EVENT_I2C_COMPLETION(port) (1 << ((port) + 20))
+#define TASK_EVENT_I2C_IDLE (TASK_EVENT_I2C_COMPLETION(0))
+#define TASK_EVENT_MAX_I2C 6
 #ifdef I2C_PORT_COUNT
 #if (I2C_PORT_COUNT > TASK_EVENT_MAX_I2C)
 #error "Too many i2c ports for i2c events"
 #endif
 #endif
 #else
-#define TASK_EVENT_I2C_IDLE	BIT(20)
-#define TASK_EVENT_PS2_DONE	BIT(21)
+#define TASK_EVENT_I2C_IDLE BIT(20)
+#define TASK_EVENT_PS2_DONE BIT(21)
 #endif
 
 /* DMA transmit complete event */
-#define TASK_EVENT_DMA_TC       BIT(26)
+#define TASK_EVENT_DMA_TC BIT(26)
 /* ADC interrupt handler event */
-#define TASK_EVENT_ADC_DONE	BIT(27)
+#define TASK_EVENT_ADC_DONE BIT(27)
 /*
  * task_reset() that was requested has been completed
  *
  * For test-only builds, may be used by some tasks to restart themselves.
  */
-#define TASK_EVENT_RESET_DONE   BIT(28)
+#define TASK_EVENT_RESET_DONE BIT(28)
 /* task_wake() called on task */
-#define TASK_EVENT_WAKE		BIT(29)
+#define TASK_EVENT_WAKE BIT(29)
 /* Mutex unlocking */
-#define TASK_EVENT_MUTEX	BIT(30)
+#define TASK_EVENT_MUTEX BIT(30)
 /*
  * Timer expired.  For example, task_wait_event() timed out before receiving
  * another event.
  */
-#define TASK_EVENT_TIMER	(1U << 31)
+#define TASK_EVENT_TIMER (1U << 31)
 
 /* Maximum time for task_wait_event() */
 #define TASK_MAX_WAIT_US 0x7fffffff
@@ -402,7 +401,7 @@ typedef struct mutex mutex_t;
  * initialize it.  We provide the same macro for CrOS EC OS so that we
  * can use it in shared code.
  */
-#define K_MUTEX_DEFINE(name) static mutex_t name = { }
+#define K_MUTEX_DEFINE(name) static mutex_t name = {}
 
 /**
  * Lock a mutex.
@@ -456,8 +455,8 @@ struct irq_def {
 #define IRQ_HANDLER(irqname) CONCAT3(irq_, irqname, _handler)
 #define IRQ_HANDLER_OPT(irqname) CONCAT3(irq_, irqname, _handler_optional)
 #define DECLARE_IRQ(irq, routine, priority) DECLARE_IRQ_(irq, routine, priority)
-#define DECLARE_IRQ_(irq, routine, priority)             \
-	static void __keep routine(void); 		 \
+#define DECLARE_IRQ_(irq, routine, priority) \
+	static void __keep routine(void);    \
 	void IRQ_HANDLER_OPT(irq)(void) __attribute__((alias(#routine)))
 
 /* Include ec.irqlist here for compilation dependency */
@@ -468,4 +467,4 @@ struct irq_def {
 #endif /* CONFIG_COMMON_RUNTIME */
 #endif /* !CONFIG_ZEPHYR */
 
-#endif  /* __CROS_EC_TASK_H */
+#endif /* __CROS_EC_TASK_H */
diff --git a/include/task_filter.h b/include/task_filter.h
index 2cd5e8bbf8..50fc46ce7f 100644
--- a/include/task_filter.h
+++ b/include/task_filter.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -50,5 +50,4 @@
 CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST CONFIG_CTS_TASK_LIST
 #endif
 
-
 #endif /*  __CROS_EC_TASK_FILTER_H */
diff --git a/include/task_id.h b/include/task_id.h
index 2ea10c9595..e617d820b5 100644
--- a/include/task_id.h
+++ b/include/task_id.h
@@ -1,4 +1,4 @@
-/* Copyright 2011 The Chromium OS Authors. All rights reserved.
+/* Copyright 2011 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,8 +17,8 @@
 #include "task_filter.h"
 
 /* define the name of the header containing the list of tasks */
-#define STRINGIFY0(name)  #name
-#define STRINGIFY(name)  STRINGIFY0(name)
+#define STRINGIFY0(name) #name
+#define STRINGIFY(name) STRINGIFY0(name)
 #define CTS_TASK_LIST STRINGIFY(CTS_TASKFILE)
 #define TEST_TASK_LIST STRINGIFY(TEST_TASKFILE)
 #define BOARD_TASK_LIST STRINGIFY(BOARD_TASKFILE)
@@ -46,16 +46,17 @@ enum {
 	TASK_ID_IDLE,
 	/* CONFIG_TASK_LIST is a macro coming from the BOARD_TASK_LIST file */
 	CONFIG_TASK_LIST
-	/* CONFIG_TEST_TASK_LIST is a macro from the TEST_TASK_LIST file */
-	CONFIG_TEST_TASK_LIST
-	/* For CTS tasks */
-	CONFIG_CTS_TASK_LIST
+		/* CONFIG_TEST_TASK_LIST is a macro from the TEST_TASK_LIST file
+		 */
+		CONFIG_TEST_TASK_LIST
+			/* For CTS tasks */
+			CONFIG_CTS_TASK_LIST
 #ifdef EMU_BUILD
-	TASK_ID_TEST_RUNNER,
+				TASK_ID_TEST_RUNNER,
 #endif
 	/* Number of tasks */
 	TASK_ID_COUNT,
-	/* Special task identifiers */
+/* Special task identifiers */
 #ifdef EMU_BUILD
 	TASK_ID_INT_GEN = 0xfe, /* interrupt generator */
 #endif
diff --git a/include/temp_sensor.h b/include/temp_sensor.h
index f8b6f64508..469d4d4764 100644
--- a/include/temp_sensor.h
+++ b/include/temp_sensor.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -38,7 +38,7 @@ struct temp_sensor_t {
 	 * to all use OO style sensor argument to get adc idx.
 	 */
 #ifdef CONFIG_ZEPHYR
-	struct zephyr_temp_sensor *zephyr_info;
+	const struct zephyr_temp_sensor *zephyr_info;
 #else
 	/* Read sensor value in K into temp_ptr; return non-zero if error. */
 	int (*read)(int idx, int *temp_ptr);
@@ -72,4 +72,4 @@ int temp_sensor_read(enum temp_sensor_id id, int *temp_ptr);
  */
 int print_temps(void);
 
-#endif  /* __CROS_EC_TEMP_SENSOR_H */
+#endif /* __CROS_EC_TEMP_SENSOR_H */
diff --git a/include/temp_sensor_chip.h b/include/temp_sensor_chip.h
index 4f9ddf0bc0..de9cb45452 100644
--- a/include/temp_sensor_chip.h
+++ b/include/temp_sensor_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/test_util.h b/include/test_util.h
index 9dcb31297f..8a7f29643d 100644
--- a/include/test_util.h
+++ b/include/test_util.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,60 +8,66 @@
 #ifndef __CROS_EC_TEST_UTIL_H
 #define __CROS_EC_TEST_UTIL_H
 
+#include "compile_time_macros.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 #include "common.h"
 #include "console.h"
 #include "stack_trace.h"
 
 #ifdef CONFIG_ZTEST
-#include <ztest.h>
+#include <zephyr/ztest.h>
 #include "ec_tasks.h"
 #endif /* CONFIG_ZTEST */
 
 /* This allows tests to be easily commented out in run_test for debugging */
 #define test_static static __attribute__((unused))
 
-#define RUN_TEST(n) \
-	do { \
+#define RUN_TEST(n)                              \
+	do {                                     \
 		ccprintf("Running %s...\n", #n); \
-		cflush(); \
-		before_test(); \
-		if (n() == EC_SUCCESS) { \
-			ccputs("OK\n"); \
-		} else { \
-			ccputs("Fail\n"); \
-			__test_error_count++; \
-		} \
-		after_test(); \
+		cflush();                        \
+		before_test();                   \
+		if (n() == EC_SUCCESS) {         \
+			ccputs("OK\n");          \
+		} else {                         \
+			ccputs("Fail\n");        \
+			__test_error_count++;    \
+		}                                \
+		after_test();                    \
 	} while (0)
 
-#define TEST_ASSERT(n) \
-	do { \
-		if (!(n)) { \
-			ccprintf("%s:%d: ASSERTION failed: %s\n", \
-				 __FILE__, __LINE__, #n); \
-			task_dump_trace(); \
-			return EC_ERROR_UNKNOWN; \
-		} \
+#define TEST_ASSERT(n)                                                      \
+	do {                                                                \
+		if (!(n)) {                                                 \
+			ccprintf("%s:%d: ASSERTION failed: %s\n", __FILE__, \
+				 __LINE__, #n);                             \
+			task_dump_trace();                                  \
+			return EC_ERROR_UNKNOWN;                            \
+		}                                                           \
 	} while (0)
 
 #if defined(__cplusplus) && !defined(__auto_type)
 #define __auto_type auto
 #endif
 
-#define TEST_OPERATOR(a, b, op, fmt) \
-	do { \
-		__auto_type _a = (a);                                       \
-		__auto_type _b = (b);                                       \
-		if (!(_a op _b)) {                                          \
-			ccprintf("%s:%d: ASSERTION failed: %s " #op " %s\n",   \
-				 __FILE__, __LINE__, #a, #b);               \
-			ccprintf("\t\tEVAL: " fmt " " #op " " fmt "\n",     \
-				 _a, _b);                                   \
-			task_dump_trace();                                  \
-			return EC_ERROR_UNKNOWN;                            \
-		} else  {                                                   \
-			ccprintf("Pass: %s " #op " %s\n", #a, #b);        \
-		}                                                           \
+#define TEST_OPERATOR(a, b, op, fmt)                                         \
+	do {                                                                 \
+		__auto_type _a = (a);                                        \
+		__auto_type _b = (b);                                        \
+		if (!(_a op _b)) {                                           \
+			ccprintf("%s:%d: ASSERTION failed: %s " #op " %s\n", \
+				 __FILE__, __LINE__, #a, #b);                \
+			ccprintf("\t\tEVAL: " fmt " " #op " " fmt "\n", _a,  \
+				 _b);                                        \
+			task_dump_trace();                                   \
+			return EC_ERROR_UNKNOWN;                             \
+		} else {                                                     \
+			ccprintf("Pass: %s " #op " %s\n", #a, #b);           \
+		}                                                            \
 	} while (0)
 
 #define TEST_EQ(a, b, fmt) TEST_OPERATOR(a, b, ==, fmt)
@@ -70,8 +76,8 @@
 #define TEST_LE(a, b, fmt) TEST_OPERATOR(a, b, <=, fmt)
 #define TEST_GT(a, b, fmt) TEST_OPERATOR(a, b, >, fmt)
 #define TEST_GE(a, b, fmt) TEST_OPERATOR(a, b, >=, fmt)
-#define TEST_BITS_SET(a, bits) TEST_OPERATOR(a & (int)bits, (int)bits, ==, "%u")
-#define TEST_BITS_CLEARED(a, bits) TEST_OPERATOR(a & (int)bits, 0, ==, "%u")
+#define TEST_BITS_SET(a, bits) TEST_OPERATOR(a &(int)bits, (int)bits, ==, "%u")
+#define TEST_BITS_CLEARED(a, bits) TEST_OPERATOR(a &(int)bits, 0, ==, "%u")
 #define TEST_NEAR(a, b, epsilon, fmt) \
 	TEST_OPERATOR(ABS((a) - (b)), epsilon, <, fmt)
 
@@ -79,40 +85,32 @@
 
 #define TEST_ASSERT_ABS_LESS(n, t) TEST_OPERATOR(__ABS(n), t, <, "%d")
 
-#define TEST_ASSERT_ARRAY_EQ(s, d, n) \
-	do { \
-		int __i; \
-		for (__i = 0; __i < n; ++__i) \
-			if ((s)[__i] != (d)[__i]) { \
+#define TEST_ASSERT_ARRAY_EQ(s, d, n)                                        \
+	do {                                                                 \
+		int __i;                                                     \
+		for (__i = 0; __i < n; ++__i)                                \
+			if ((s)[__i] != (d)[__i]) {                          \
 				ccprintf("%s:%d: ASSERT_ARRAY_EQ failed at " \
-					 "index=%d: %d != %d\n", \
-					 __FILE__,  __LINE__, \
-					 __i, (int)(s)[__i], (int)(d)[__i]); \
-				task_dump_trace(); \
-				return EC_ERROR_UNKNOWN; \
-			} \
+					 "index=%d: %d != %d\n",             \
+					 __FILE__, __LINE__, __i,            \
+					 (int)(s)[__i], (int)(d)[__i]);      \
+				task_dump_trace();                           \
+				return EC_ERROR_UNKNOWN;                     \
+			}                                                    \
 	} while (0)
 
-#define TEST_ASSERT_MEMSET(d, c, n) \
-	do { \
-		int __i; \
-		for (__i = 0; __i < n; ++__i) \
-			if ((d)[__i] != (c)) { \
+#define TEST_ASSERT_MEMSET(d, c, n)                                        \
+	do {                                                               \
+		int __i;                                                   \
+		for (__i = 0; __i < n; ++__i)                              \
+			if ((d)[__i] != (c)) {                             \
 				ccprintf("%s:%d: ASSERT_MEMSET failed at " \
-					 "index=%d: %d != %d\n", \
-					 __FILE__, __LINE__, \
-					 __i, (int)(d)[__i], (c)); \
-				task_dump_trace(); \
-				return EC_ERROR_UNKNOWN; \
-			} \
-	} while (0)
-
-#define TEST_CHECK(n) \
-	do { \
-		if (n) \
-			return EC_SUCCESS; \
-		else \
-			return EC_ERROR_UNKNOWN; \
+					 "index=%d: %d != %d\n",           \
+					 __FILE__, __LINE__, __i,          \
+					 (int)(d)[__i], (c));              \
+				task_dump_trace();                         \
+				return EC_ERROR_UNKNOWN;                   \
+			}                                                  \
 	} while (0)
 
 /* Mutlistep test states */
@@ -147,7 +145,7 @@ void before_test(void);
 void after_test(void);
 
 /* Test entry point */
-void run_test(int argc, char **argv);
+void run_test(int argc, const char **argv);
 
 /* Test entry point for fuzzing tests. */
 int test_fuzz_one_input(const uint8_t *data, unsigned int size);
@@ -195,8 +193,12 @@ void interrupt_generator_udelay(unsigned us);
 void wait_for_task_started(void);
 void wait_for_task_started_nosleep(void);
 #else
-static inline void wait_for_task_started(void) { }
-static inline void wait_for_task_started_nosleep(void) { }
+static inline void wait_for_task_started(void)
+{
+}
+static inline void wait_for_task_started_nosleep(void)
+{
+}
 #endif
 
 uint32_t prng(uint32_t seed);
@@ -271,8 +273,8 @@ struct test_i2c_read_string_dev {
 struct test_i2c_xfer {
 	/* I2C xfer handler */
 	int (*routine)(const int port, const uint16_t i2c_addr_flags,
-		       const uint8_t *out, int out_size,
-		       uint8_t *in, int in_size, int flags);
+		       const uint8_t *out, int out_size, uint8_t *in,
+		       int in_size, int flags);
 };
 
 struct test_i2c_write_dev {
@@ -290,11 +292,10 @@ struct test_i2c_write_dev {
  *
  * @param routine     Function pointer, with the same prototype as i2c_xfer()
  */
-#define DECLARE_TEST_I2C_XFER(routine)					\
-	const struct test_i2c_xfer __no_sanitize_address		\
-	__test_i2c_xfer_##routine					\
-	__attribute__((section(".rodata.test_i2c.xfer")))		\
-		= {routine}
+#define DECLARE_TEST_I2C_XFER(routine)                    \
+	const struct test_i2c_xfer __no_sanitize_address  \
+		__test_i2c_xfer_##routine __attribute__(( \
+			section(".rodata.test_i2c.xfer"))) = { routine }
 
 /*
  * Detach an I2C device. Once detached, any read/write command regarding the
@@ -377,14 +378,14 @@ int test_attach_i2c(const int port, const uint16_t addr_flags);
 #define TEST_MAIN() void test_main(void)
 #define TEST_SUITE(name) void name(void)
 #else
-#define TEST_MAIN()                          \
-	void test_main(void);                \
-	void run_test(int argc, char **argv) \
-	{                                    \
-		test_reset();                \
-		test_main();                 \
-		test_print_result();         \
-	}                                    \
+#define TEST_MAIN()                                \
+	void test_main(void);                      \
+	void run_test(int argc, const char **argv) \
+	{                                          \
+		test_reset();                      \
+		test_main();                       \
+		test_print_result();               \
+	}                                          \
 	void test_main(void)
 #define TEST_SUITE(name) TEST_MAIN()
 #endif
@@ -413,7 +414,7 @@ struct unit_test {
  */
 #define ztest_unit_test_setup_teardown(fn, setup, teardown) \
 	{                                                   \
-		#fn, fn, setup, teardown                    \
+#fn, fn, setup, teardown                    \
 	}
 
 /**
@@ -477,7 +478,7 @@ void z_ztest_run_test_suite(const char *name, struct unit_test *suite);
 #define zassert_unreachable(msg, ...) TEST_ASSERT(0)
 #define zassert_true(cond, msg, ...) TEST_ASSERT(cond)
 #define zassert_false(cond, msg, ...) TEST_ASSERT(!(cond))
-#define zassert_ok(cond, msg, ...) TEST_ASSERT(cond)
+#define zassert_ok(cond, msg, ...) TEST_ASSERT(!(cond))
 #define zassert_is_null(ptr, msg, ...) TEST_ASSERT((ptr) == NULL)
 #define zassert_not_null(ptr, msg, ...) TEST_ASSERT((ptr) != NULL)
 #define zassert_equal(a, b, msg, ...) TEST_EQ((a), (b), "0x%x")
@@ -489,4 +490,8 @@ void z_ztest_run_test_suite(const char *name, struct unit_test *suite);
 	TEST_ASSERT_ARRAY_EQ(buf, exp, size)
 #endif /* CONFIG_ZEPHYR */
 
+#ifdef __cplusplus
+}
+#endif
+
 #endif /* __CROS_EC_TEST_UTIL_H */
diff --git a/include/tests/enum_strings.h b/include/tests/enum_strings.h
index ece2df362f..2ad0725f8f 100644
--- a/include/tests/enum_strings.h
+++ b/include/tests/enum_strings.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/thermal.h b/include/thermal.h
index 29d8073ca0..33d0e27f51 100644
--- a/include/thermal.h
+++ b/include/thermal.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,4 +27,4 @@ int thermal_fan_percent(int low, int high, int cur);
  */
 void board_override_fan_control(int fan, int *tmp);
 
-#endif  /* __CROS_EC_THERMAL_H */
+#endif /* __CROS_EC_THERMAL_H */
diff --git a/include/throttle_ap.h b/include/throttle_ap.h
index 09669d70b1..43a5f48e2c 100644
--- a/include/throttle_ap.h
+++ b/include/throttle_ap.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,8 +20,8 @@ enum throttle_level {
  * Types of throttling desired. These are independent.
  */
 enum throttle_type {
-	THROTTLE_SOFT = 0,			/* for example, host events */
-	THROTTLE_HARD,				/* for example, PROCHOT */
+	THROTTLE_SOFT = 0, /* for example, host events */
+	THROTTLE_HARD, /* for example, PROCHOT */
 	NUM_THROTTLE_TYPES
 };
 
@@ -32,6 +32,7 @@ enum throttle_sources {
 	THROTTLE_SRC_THERMAL = 0,
 	THROTTLE_SRC_BAT_DISCHG_CURRENT,
 	THROTTLE_SRC_BAT_VOLTAGE,
+	THROTTLE_SRC_AC,
 };
 
 /**
@@ -57,12 +58,11 @@ struct prochot_cfg {
  * @param type          Type of throttling desired
  * @param source        Which task is requesting throttling
  */
-#if defined(CONFIG_THROTTLE_AP) || \
+#if defined(CONFIG_THROTTLE_AP) ||                           \
 	defined(CONFIG_THROTTLE_AP_ON_BAT_DISCHG_CURRENT) || \
 	defined(CONFIG_THROTTLE_AP_ON_BAT_VOLTAGE)
 
-void throttle_ap(enum throttle_level level,
-		 enum throttle_type type,
+void throttle_ap(enum throttle_level level, enum throttle_type type,
 		 enum throttle_sources source);
 
 /**
@@ -102,7 +102,11 @@ void throttle_ap_c10_input_interrupt(enum gpio_signal signal);
 static inline void throttle_ap(enum throttle_level level,
 			       enum throttle_type type,
 			       enum throttle_sources source)
-{}
+{
+}
 #endif
 
-#endif	/* __CROS_EC_THROTTLE_AP_H */
+void throttle_gpu(enum throttle_level level, enum throttle_type type,
+		  enum throttle_sources source);
+
+#endif /* __CROS_EC_THROTTLE_AP_H */
diff --git a/include/timer.h b/include/timer.h
index 6f9b4ea7b0..7170a35056 100644
--- a/include/timer.h
+++ b/include/timer.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,11 +19,11 @@ typedef long clock_t;
 #include "task_id.h"
 
 /* Time units in microseconds */
-#define MSEC         1000
-#define SECOND    1000000
-#define SEC_UL    1000000ul
-#define MINUTE   60000000
-#define HOUR   3600000000ull  /* Too big to fit in a signed int */
+#define MSEC 1000
+#define SECOND 1000000
+#define SEC_UL 1000000ul
+#define MINUTE 60000000
+#define HOUR 3600000000ull /* Too big to fit in a signed int */
 
 /* Microsecond timestamp. */
 typedef union {
@@ -34,7 +34,6 @@ typedef union {
 	} le /* little endian words */;
 } timestamp_t;
 
-
 /**
  * Initialize the timer module.
  */
@@ -195,4 +194,4 @@ static inline int time_after(uint32_t a, uint32_t b)
 extern timestamp_t *get_time_mock;
 #endif /* CONFIG_ZTEST */
 
-#endif  /* __CROS_EC_TIMER_H */
+#endif /* __CROS_EC_TIMER_H */
diff --git a/include/touchpad.h b/include/touchpad.h
index 4e746d8dc1..8ae985318e 100644
--- a/include/touchpad.h
+++ b/include/touchpad.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/trng.h b/include/trng.h
index cea4555b41..cf8326e5bf 100644
--- a/include/trng.h
+++ b/include/trng.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,32 +14,30 @@
  *
  * Not supported by all platforms.
  **/
-void init_trng(void);
+void trng_init(void);
 
 /**
  * Shutdown the true random number generator.
  *
- * The opposite operation of init_trng(), disable the hardware resources
+ * The opposite operation of trng_init(), disable the hardware resources
  * used by the TRNG to save power.
  *
  * Not supported by all platforms.
  **/
-void exit_trng(void);
+void trng_exit(void);
 
 /**
  * Retrieve a 32 bit random value.
  *
  * Not supported on all platforms.
  **/
-#ifndef HIDE_EC_STDLIB
-uint32_t rand(void);
-#endif
+uint32_t trng_rand(void);
 
 /**
  * Output len random bytes into buffer.
  *
  * Not supported on all platforms.
  **/
-void rand_bytes(void *buffer, size_t len);
+void trng_rand_bytes(void *buffer, size_t len);
 
 #endif /* __EC_INCLUDE_TRNG_H */
diff --git a/include/typec_control.h b/include/typec_control.h
index b162467663..849a661490 100644
--- a/include/typec_control.h
+++ b/include/typec_control.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -33,7 +33,7 @@ void typec_set_sbu(int port, bool enable);
  * @param rp Pull-up values to be aplied as a SRC to advertise current limits
  */
 __override_proto void typec_set_source_current_limit(int port,
-						enum tcpc_rp_value rp);
+						     enum tcpc_rp_value rp);
 
 /**
  * Turn on/off the VCONN FET
diff --git a/include/uart.h b/include/uart.h
index 3789ce127c..851b331fd2 100644
--- a/include/uart.h
+++ b/include/uart.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,7 +8,7 @@
 #ifndef __CROS_EC_UART_H
 #define __CROS_EC_UART_H
 
-#include <stdarg.h>  /* For va_list */
+#include <stdarg.h> /* For va_list */
 #include "common.h"
 #include "gpio_signal.h"
 
@@ -72,8 +72,8 @@ int uart_put_raw(const char *out, int len);
  *
  * @return EC_SUCCESS, or non-zero if output was truncated.
  */
-__attribute__((__format__(__printf__, 1, 2)))
-int uart_printf(const char *format, ...);
+__attribute__((__format__(__printf__, 1, 2))) int
+uart_printf(const char *format, ...);
 
 /**
  * Print formatted output to the UART, like vprintf().
@@ -258,7 +258,9 @@ void uart_exit_dsleep(void);
  */
 void uart_deepsleep_interrupt(enum gpio_signal signal);
 #else
-static inline void uart_deepsleep_interrupt(enum gpio_signal signal) { }
+static inline void uart_deepsleep_interrupt(enum gpio_signal signal)
+{
+}
 #endif /* !CONFIG_LOW_POWER_IDLE */
 
 #if defined(HAS_TASK_CONSOLE) && defined(CONFIG_FORCE_CONSOLE_RESUME)
@@ -269,7 +271,9 @@ static inline void uart_deepsleep_interrupt(enum gpio_signal signal) { }
  */
 void uart_enable_wakeup(int enable);
 #elif !defined(CHIP_FAMILY_NPCX5)
-static inline void uart_enable_wakeup(int enable) {}
+static inline void uart_enable_wakeup(int enable)
+{
+}
 #endif
 
 #ifdef CONFIG_UART_INPUT_FILTER
@@ -335,7 +339,7 @@ void uart_reset_default_pad_panic(void);
  *           time specified in timeout_us.
  */
 int uart_alt_pad_write_read(uint8_t *tx, int tx_len, uint8_t *rx, int rx_len,
-			int timeout_us);
+			    int timeout_us);
 
 /**
  * Interrupt handler for default UART RX pin transition when UART is switched
@@ -372,9 +376,7 @@ enum ec_status uart_console_read_buffer_init(void);
  *
  * @return result status (EC_RES_*)
  */
-int uart_console_read_buffer(uint8_t type,
-			     char *dest,
-			     uint16_t dest_size,
+int uart_console_read_buffer(uint8_t type, char *dest, uint16_t dest_size,
 			     uint16_t *write_count);
 
 /**
@@ -382,4 +384,4 @@ int uart_console_read_buffer(uint8_t type,
  */
 void uart_init_buffer(void);
 
-#endif  /* __CROS_EC_UART_H */
+#endif /* __CROS_EC_UART_H */
diff --git a/include/update_fw.h b/include/update_fw.h
index d345c4f667..dc520c2eb9 100644
--- a/include/update_fw.h
+++ b/include/update_fw.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -43,8 +43,8 @@
  * block_base:   offset of this PDU into the flash SPI.
  */
 struct update_command {
-	uint32_t  block_digest;
-	uint32_t  block_base;
+	uint32_t block_digest;
+	uint32_t block_base;
 	/* The actual payload goes here. */
 } __packed;
 
@@ -112,8 +112,8 @@ struct first_response_pdu {
 		/* cr50 (header_type = UPDATE_HEADER_TYPE_CR50) */
 		struct {
 			/* The below fields are present in versions 3 and up. */
-			uint32_t  backup_ro_offset;
-			uint32_t  backup_rw_offset;
+			uint32_t backup_ro_offset;
+			uint32_t backup_rw_offset;
 
 			/* The below fields are present in versions 4 and up. */
 			/*
@@ -154,8 +154,8 @@ enum first_response_pdu_header_type {
 };
 
 /* TODO: Handle this in update_fw.c, not usb_update.c */
-#define UPDATE_DONE          0xB007AB1E
-#define UPDATE_EXTRA_CMD     0xB007AB1F
+#define UPDATE_DONE 0xB007AB1E
+#define UPDATE_EXTRA_CMD 0xB007AB1F
 
 enum update_extra_command {
 	UPDATE_EXTRA_CMD_IMMEDIATE_RESET = 0,
@@ -235,8 +235,7 @@ struct touchpad_info {
  */
 BUILD_ASSERT(sizeof(struct touchpad_info) <= 50);
 
-void fw_update_command_handler(void *body,
-			       size_t cmd_size,
+void fw_update_command_handler(void *body, size_t cmd_size,
 			       size_t *response_size);
 
 /* Used to tell fw update the update ran successfully and is finished */
@@ -286,4 +285,4 @@ int touchpad_debug(const uint8_t *param, unsigned int param_size,
 /* SHA256 hash of the touchpad firmware expected by this image. */
 extern const uint8_t touchpad_fw_full_hash[32];
 
-#endif  /* ! __CROS_EC_UPDATE_FW_H */
+#endif /* ! __CROS_EC_UPDATE_FW_H */
diff --git a/include/usb_api.h b/include/usb_api.h
index 79ee9406e9..85e82d11e0 100644
--- a/include/usb_api.h
+++ b/include/usb_api.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -76,7 +76,9 @@ void usb_restore_suspended_state(void);
 #ifdef CONFIG_USB_REMOTE_WAKEUP
 void usb_wake(void);
 #else
-static inline void usb_wake(void) {}
+static inline void usb_wake(void)
+{
+}
 #endif
 
 /* Board-specific USB wake, for side-band wake, called by usb_wake above. */
diff --git a/include/usb_bb.h b/include/usb_bb.h
index e2303f13e6..d28d4be441 100644
--- a/include/usb_bb.h
+++ b/include/usb_bb.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -17,7 +17,6 @@
 #define USB_BB_EP0_PACKET_SIZE 8
 #define USB_BB_CAP_DESC_TYPE 0x0d
 
-
 #define USB_BB_CAPS_SVID_SIZE 4
 struct usb_bb_caps_svid_descriptor {
 	uint16_t wSVID;
@@ -38,16 +37,14 @@ struct usb_bb_caps_base_descriptor {
 	uint32_t bReserved; /* SBZ */
 } __packed;
 
-
-#define USB_BB_VCONN_PWRON(x)    (x << 15)
-#define USB_BB_VCONN_PWR_1W      0
-#define USB_BB_VCONN_PWR_1p5W    1
-#define USB_BB_VCONN_PWR_2W      2
-#define USB_BB_VCONN_PWR_3W      3
-#define USB_BB_VCONN_PWR_4W      4
-#define USB_BB_VCONN_PWR_5W      5
-#define USB_BB_VCONN_PWR_6W      6
+#define USB_BB_VCONN_PWRON(x) (x << 15)
+#define USB_BB_VCONN_PWR_1W 0
+#define USB_BB_VCONN_PWR_1p5W 1
+#define USB_BB_VCONN_PWR_2W 2
+#define USB_BB_VCONN_PWR_3W 3
+#define USB_BB_VCONN_PWR_4W 4
+#define USB_BB_VCONN_PWR_5W 5
+#define USB_BB_VCONN_PWR_6W 6
 /* Note, 7W (111b) is reserved */
 
-
 #endif /* __CROS_EC_USB_BB_H */
diff --git a/include/usb_charge.h b/include/usb_charge.h
index 135258c7cf..cd022d5f51 100644
--- a/include/usb_charge.h
+++ b/include/usb_charge.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,7 +14,7 @@
 #include "task.h"
 
 /* USB charger voltage */
-#define USB_CHARGER_VOLTAGE_MV  5000
+#define USB_CHARGER_VOLTAGE_MV 5000
 /* USB charger minimum current */
 #define USB_CHARGER_MIN_CURR_MA 500
 /*
@@ -65,13 +65,13 @@ int usb_charge_set_mode(int usb_port_id, enum usb_charge_mode mode,
 #define USB_CHARGER_EVENT_BIT(x) TASK_EVENT_CUSTOM_BIT(x)
 #endif
 
-#define USB_CHG_EVENT_BC12	USB_CHARGER_EVENT_BIT(0)
-#define USB_CHG_EVENT_VBUS	USB_CHARGER_EVENT_BIT(1)
-#define USB_CHG_EVENT_INTR	USB_CHARGER_EVENT_BIT(2)
-#define USB_CHG_EVENT_DR_UFP	USB_CHARGER_EVENT_BIT(3)
-#define USB_CHG_EVENT_DR_DFP	USB_CHARGER_EVENT_BIT(4)
-#define USB_CHG_EVENT_CC_OPEN	USB_CHARGER_EVENT_BIT(5)
-#define USB_CHG_EVENT_MUX	USB_CHARGER_EVENT_BIT(6)
+#define USB_CHG_EVENT_BC12 USB_CHARGER_EVENT_BIT(0)
+#define USB_CHG_EVENT_VBUS USB_CHARGER_EVENT_BIT(1)
+#define USB_CHG_EVENT_INTR USB_CHARGER_EVENT_BIT(2)
+#define USB_CHG_EVENT_DR_UFP USB_CHARGER_EVENT_BIT(3)
+#define USB_CHG_EVENT_DR_DFP USB_CHARGER_EVENT_BIT(4)
+#define USB_CHG_EVENT_CC_OPEN USB_CHARGER_EVENT_BIT(5)
+#define USB_CHG_EVENT_MUX USB_CHARGER_EVENT_BIT(6)
 
 /*
  * Define USB_CHG_PORT_TO_TASK_ID() and TASK_ID_TO_USB_CHG_PORT() macros to
@@ -80,11 +80,11 @@ int usb_charge_set_mode(int usb_port_id, enum usb_charge_mode mode,
  */
 #ifdef HAS_TASK_USB_CHG_P0
 #define USB_CHG_PORT_TO_TASK_ID(port) (TASK_ID_USB_CHG_P0 + (port))
-#define TASK_ID_TO_USB_CHG_PORT(id) ((id) - TASK_ID_USB_CHG_P0)
+#define TASK_ID_TO_USB_CHG_PORT(id) ((id)-TASK_ID_USB_CHG_P0)
 #else
 #define USB_CHG_PORT_TO_TASK_ID(port) -1 /* stub task ID */
 #define TASK_ID_TO_USB_CHG_PORT(id) 0
-#endif  /* HAS_TASK_USB_CHG_P0 */
+#endif /* HAS_TASK_USB_CHG_P0 */
 
 /**
  * Returns true if the passed port is a power source.
@@ -214,4 +214,4 @@ int board_is_sourcing_vbus(int port);
  */
 int board_vbus_sink_enable(int port, int enable);
 
-#endif  /* __CROS_EC_USB_CHARGE_H */
+#endif /* __CROS_EC_USB_CHARGE_H */
diff --git a/include/usb_common.h b/include/usb_common.h
index bd779780ee..1e1d210f8c 100644
--- a/include/usb_common.h
+++ b/include/usb_common.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -33,10 +33,10 @@ enum pd_drp_next_states {
  *			us of a connection.
  *
  */
-enum pd_drp_next_states drp_auto_toggle_next_state(uint64_t *drp_sink_time,
-	enum pd_power_role power_role, enum pd_dual_role_states drp_state,
-	enum tcpc_cc_voltage_status cc1, enum tcpc_cc_voltage_status cc2,
-	bool auto_toggle_supported);
+enum pd_drp_next_states drp_auto_toggle_next_state(
+	uint64_t *drp_sink_time, enum pd_power_role power_role,
+	enum pd_dual_role_states drp_state, enum tcpc_cc_voltage_status cc1,
+	enum tcpc_cc_voltage_status cc2, bool auto_toggle_supported);
 
 enum pd_pref_type {
 	/* prefer voltage larger than or equal to pd_pref_config.mv */
@@ -105,7 +105,8 @@ int usb_get_battery_soc(void);
  * @return current limit (mA) with DTS flag set if appropriate
  */
 typec_current_t usb_get_typec_current_limit(enum tcpc_cc_polarity polarity,
-	enum tcpc_cc_voltage_status cc1, enum tcpc_cc_voltage_status cc2);
+					    enum tcpc_cc_voltage_status cc1,
+					    enum tcpc_cc_voltage_status cc2);
 
 /**
  * Returns the polarity of a Sink.
@@ -115,7 +116,7 @@ typec_current_t usb_get_typec_current_limit(enum tcpc_cc_polarity polarity,
  * @return polarity
  */
 enum tcpc_cc_polarity get_snk_polarity(enum tcpc_cc_voltage_status cc1,
-	enum tcpc_cc_voltage_status cc2);
+				       enum tcpc_cc_voltage_status cc2);
 
 /**
  * Returns the polarity of a Source.
@@ -125,7 +126,7 @@ enum tcpc_cc_polarity get_snk_polarity(enum tcpc_cc_voltage_status cc1,
  * @return polarity
  */
 enum tcpc_cc_polarity get_src_polarity(enum tcpc_cc_voltage_status cc1,
-	enum tcpc_cc_voltage_status cc2);
+				       enum tcpc_cc_voltage_status cc2);
 
 /**
  * Find PDO index that offers the most amount of power and stays within
@@ -137,8 +138,8 @@ enum tcpc_cc_polarity get_src_polarity(enum tcpc_cc_voltage_status cc1,
  * @param pdo raw pdo corresponding to index, or index 0 on error (output)
  * @return index of PDO within source cap packet
  */
-int pd_find_pdo_index(uint32_t src_cap_cnt, const uint32_t * const src_caps,
-	int max_mv, uint32_t *selected_pdo);
+int pd_find_pdo_index(uint32_t src_cap_cnt, const uint32_t *const src_caps,
+		      int max_mv, uint32_t *selected_pdo);
 
 /**
  * Extract power information out of a Power Data Object (PDO)
@@ -161,7 +162,7 @@ void pd_extract_pdo_power(uint32_t pdo, uint32_t *ma, uint32_t *max_mv,
  * @param port USB-C port number
  */
 void pd_build_request(int32_t vpd_vdo, uint32_t *rdo, uint32_t *ma,
-			uint32_t *mv, int port);
+		      uint32_t *mv, int port);
 
 /**
  * Notifies a task that is waiting on a system jump, that it's complete.
diff --git a/include/usb_console.h b/include/usb_console.h
index 2e0aa7dfa6..cbc322ce6c 100644
--- a/include/usb_console.h
+++ b/include/usb_console.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -80,7 +80,7 @@ int usb_console_tx_blocked(void);
 #define usb_getc(x) (-1)
 #define usb_va_start(x, y)
 #define usb_va_end(x)
-#define usb_console_tx_blocked()	(0)
+#define usb_console_tx_blocked() (0)
 #endif
 
 #endif /* __CROS_EC_USB_CONSOLE_H */
diff --git a/include/usb_descriptor.h b/include/usb_descriptor.h
index 47f6e8805e..a40b858876 100644
--- a/include/usb_descriptor.h
+++ b/include/usb_descriptor.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -15,17 +15,17 @@
 /* USB 2.0 chapter 9 definitions */
 
 /* Descriptor types */
-#define USB_DT_DEVICE                     0x01
-#define USB_DT_CONFIGURATION              0x02
-#define USB_DT_STRING                     0x03
-#define USB_DT_INTERFACE                  0x04
-#define USB_DT_ENDPOINT                   0x05
-#define USB_DT_DEVICE_QUALIFIER           0x06
-#define USB_DT_OTHER_SPEED_CONFIG         0x07
-#define USB_DT_INTERFACE_POWER            0x08
-#define USB_DT_DEBUG                      0x0a
-#define USB_DT_BOS                        0x0f
-#define USB_DT_DEVICE_CAPABILITY          0x10
+#define USB_DT_DEVICE 0x01
+#define USB_DT_CONFIGURATION 0x02
+#define USB_DT_STRING 0x03
+#define USB_DT_INTERFACE 0x04
+#define USB_DT_ENDPOINT 0x05
+#define USB_DT_DEVICE_QUALIFIER 0x06
+#define USB_DT_OTHER_SPEED_CONFIG 0x07
+#define USB_DT_INTERFACE_POWER 0x08
+#define USB_DT_DEBUG 0x0a
+#define USB_DT_BOS 0x0f
+#define USB_DT_DEVICE_CAPABILITY 0x10
 
 /* USB Device Descriptor */
 struct usb_device_descriptor {
@@ -44,7 +44,7 @@ struct usb_device_descriptor {
 	uint8_t iSerialNumber;
 	uint8_t bNumConfigurations;
 } __packed;
-#define USB_DT_DEVICE_SIZE                18
+#define USB_DT_DEVICE_SIZE 18
 
 /* BOS Descriptor ( USB3.1 rev1 Section 9.6.2 ) */
 struct bos_context {
@@ -55,158 +55,160 @@ struct bos_context {
 struct usb_bos_hdr_descriptor {
 	uint8_t bLength;
 	uint8_t bDescriptorType; /* USB_DT_BOS */
-	uint16_t wTotalLength;   /* Total length of of hdr + all dev caps */
-	uint8_t bNumDeviceCaps;  /* Container ID Descriptor + others */
+	uint16_t wTotalLength; /* Total length of of hdr + all dev caps */
+	uint8_t bNumDeviceCaps; /* Container ID Descriptor + others */
 } __packed;
 #define USB_DT_BOS_SIZE 5
 
 /* Container ID Descriptor */
 struct usb_contid_caps_descriptor {
-	uint8_t  bLength;
-	uint8_t  bDescriptorType;     /* USB_DT_DEVICE_CAPABILITY */
-	uint8_t  bDevCapabilityType;  /* USB_DC_DTYPE_xxx */
-	uint8_t  bReserved;           /* SBZ */
-	uint8_t  ContainerID[16];     /* UUID */
+	uint8_t bLength;
+	uint8_t bDescriptorType; /* USB_DT_DEVICE_CAPABILITY */
+	uint8_t bDevCapabilityType; /* USB_DC_DTYPE_xxx */
+	uint8_t bReserved; /* SBZ */
+	uint8_t ContainerID[16]; /* UUID */
 } __packed;
-#define USB_DT_CONTID_SIZE         20
+#define USB_DT_CONTID_SIZE 20
 
 /* Device Cap Type Codes ( offset 2 of Device Capability Descriptor */
-#define USB_DC_DTYPE_WIRELESS  0x01
-#define USB_DC_DTYPE_USB20EXT  0x02
-#define USB_DC_DTYPE_USBSS     0x03
-#define USB_DC_DTYPE_CONTID    0x04
-#define USB_DC_DTYPE_PLATFORM  0x05
-#define USB_DC_DTYPE_PD        0x06
-#define USB_DC_DTYPE_BATTINFO  0x07
-#define USB_DC_DTYPE_CONSUMER  0x08
-#define USB_DC_DTYPE_PRODUCER  0x09
-#define USB_DC_DTYPE_USBSSP    0x0a
-#define USB_DC_DTYPE_PCSTIME   0x0b
-#define USB_DC_DTYPE_WUSBEXT   0x0c
+#define USB_DC_DTYPE_WIRELESS 0x01
+#define USB_DC_DTYPE_USB20EXT 0x02
+#define USB_DC_DTYPE_USBSS 0x03
+#define USB_DC_DTYPE_CONTID 0x04
+#define USB_DC_DTYPE_PLATFORM 0x05
+#define USB_DC_DTYPE_PD 0x06
+#define USB_DC_DTYPE_BATTINFO 0x07
+#define USB_DC_DTYPE_CONSUMER 0x08
+#define USB_DC_DTYPE_PRODUCER 0x09
+#define USB_DC_DTYPE_USBSSP 0x0a
+#define USB_DC_DTYPE_PCSTIME 0x0b
+#define USB_DC_DTYPE_WUSBEXT 0x0c
 #define USB_DC_DTYPE_BILLBOARD 0x0d
 /* RESERVED 0x00, 0xOe - 0xff */
 
 /* Platform descriptor */
 struct usb_platform_descriptor {
-	uint8_t  bLength;
-	uint8_t  bDescriptorType;     /* USB_DT_DEVICE_CAPABILITY */
-	uint8_t  bDevCapabilityType;  /* USB_DC_DTYPE_PLATFORM */
-	uint8_t  bReserved;           /* SBZ */
-	uint8_t  PlatformCapUUID[16]; /* USB_PLAT_CAP_xxx */
-	uint16_t bcdVersion;          /* 0x0100 */
-	uint8_t  bVendorCode;
-	uint8_t  iLandingPage;
+	uint8_t bLength;
+	uint8_t bDescriptorType; /* USB_DT_DEVICE_CAPABILITY */
+	uint8_t bDevCapabilityType; /* USB_DC_DTYPE_PLATFORM */
+	uint8_t bReserved; /* SBZ */
+	uint8_t PlatformCapUUID[16]; /* USB_PLAT_CAP_xxx */
+	uint16_t bcdVersion; /* 0x0100 */
+	uint8_t bVendorCode;
+	uint8_t iLandingPage;
 } __packed;
-#define USB_DT_PLATFORM_SIZE   24
+#define USB_DT_PLATFORM_SIZE 24
 
 /* Platform Capability UUIDs */
-#define USB_PLAT_CAP_WEBUSB /*{3408b638-09a9-47a0-8bfd-a0768815b665}*/ \
-	{0x38, 0xB6, 0x08, 0x34, 0xA9, 0x09, 0xA0, 0x47,               \
-	 0x8B, 0xFD, 0xA0, 0x76, 0x88, 0x15, 0xB6, 0x65}
+#define USB_PLAT_CAP_WEBUSB /*{3408b638-09a9-47a0-8bfd-a0768815b665}*/      \
+	{                                                                   \
+		0x38, 0xB6, 0x08, 0x34, 0xA9, 0x09, 0xA0, 0x47, 0x8B, 0xFD, \
+			0xA0, 0x76, 0x88, 0x15, 0xB6, 0x65                  \
+	}
 
 /* Qualifier Descriptor */
 struct usb_qualifier_descriptor {
-	uint8_t  bLength;
-	uint8_t  bDescriptorType;
+	uint8_t bLength;
+	uint8_t bDescriptorType;
 	uint16_t bcdUSB;
-	uint8_t  bDeviceClass;
-	uint8_t  bDeviceSubClass;
-	uint8_t  bDeviceProtocol;
-	uint8_t  bMaxPacketSize0;
-	uint8_t  bNumConfigurations;
-	uint8_t  bReserved;
+	uint8_t bDeviceClass;
+	uint8_t bDeviceSubClass;
+	uint8_t bDeviceProtocol;
+	uint8_t bMaxPacketSize0;
+	uint8_t bNumConfigurations;
+	uint8_t bReserved;
 } __packed;
-#define USB_DT_QUALIFIER_SIZE		10
+#define USB_DT_QUALIFIER_SIZE 10
 
 /* Configuration Descriptor */
 struct usb_config_descriptor {
-	uint8_t  bLength;
-	uint8_t  bDescriptorType;
+	uint8_t bLength;
+	uint8_t bDescriptorType;
 	uint16_t wTotalLength;
-	uint8_t  bNumInterfaces;
-	uint8_t  bConfigurationValue;
-	uint8_t  iConfiguration;
-	uint8_t  bmAttributes;
-	uint8_t  bMaxPower;
+	uint8_t bNumInterfaces;
+	uint8_t bConfigurationValue;
+	uint8_t iConfiguration;
+	uint8_t bmAttributes;
+	uint8_t bMaxPower;
 } __packed;
-#define USB_DT_CONFIG_SIZE                9
+#define USB_DT_CONFIG_SIZE 9
 
 /* String Descriptor */
 struct usb_string_descriptor {
-	uint8_t  bLength;
-	uint8_t  bDescriptorType;
+	uint8_t bLength;
+	uint8_t bDescriptorType;
 	uint16_t wData[1];
 } __packed;
 
 /* Interface Descriptor */
 struct usb_interface_descriptor {
-	uint8_t  bLength;
-	uint8_t  bDescriptorType;
-	uint8_t  bInterfaceNumber;
-	uint8_t  bAlternateSetting;
-	uint8_t  bNumEndpoints;
-	uint8_t  bInterfaceClass;
-	uint8_t  bInterfaceSubClass;
-	uint8_t  bInterfaceProtocol;
-	uint8_t  iInterface;
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	uint8_t bInterfaceNumber;
+	uint8_t bAlternateSetting;
+	uint8_t bNumEndpoints;
+	uint8_t bInterfaceClass;
+	uint8_t bInterfaceSubClass;
+	uint8_t bInterfaceProtocol;
+	uint8_t iInterface;
 } __packed;
-#define USB_DT_INTERFACE_SIZE           9
+#define USB_DT_INTERFACE_SIZE 9
 
 /* Endpoint Descriptor */
 struct usb_endpoint_descriptor {
-	uint8_t  bLength;
-	uint8_t  bDescriptorType;
-	uint8_t  bEndpointAddress;
-	uint8_t  bmAttributes;
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	uint8_t bEndpointAddress;
+	uint8_t bmAttributes;
 	uint16_t wMaxPacketSize;
-	uint8_t  bInterval;
+	uint8_t bInterval;
 } __packed;
-#define USB_DT_ENDPOINT_SIZE            7
+#define USB_DT_ENDPOINT_SIZE 7
 
 /* USB Class codes */
-#define USB_CLASS_PER_INTERFACE           0x00
-#define USB_CLASS_AUDIO                   0x01
-#define USB_CLASS_COMM                    0x02
-#define USB_CLASS_HID                     0x03
-#define USB_CLASS_PHYSICAL                0x05
-#define USB_CLASS_STILL_IMAGE             0x06
-#define USB_CLASS_PRINTER                 0x07
-#define USB_CLASS_MASS_STORAGE            0x08
-#define USB_CLASS_HUB                     0x09
-#define USB_CLASS_CDC_DATA                0x0a
-#define USB_CLASS_CSCID                   0x0b
-#define USB_CLASS_CONTENT_SEC             0x0d
-#define USB_CLASS_VIDEO                   0x0e
-#define USB_CLASS_BILLBOARD               0x11
-#define USB_CLASS_WIRELESS_CONTROLLER     0xe0
-#define USB_CLASS_MISC                    0xef
-#define USB_CLASS_APP_SPEC                0xfe
-#define USB_CLASS_VENDOR_SPEC             0xff
-
-/* USB Vendor ID assigned to Google Inc. */
+#define USB_CLASS_PER_INTERFACE 0x00
+#define USB_CLASS_AUDIO 0x01
+#define USB_CLASS_COMM 0x02
+#define USB_CLASS_HID 0x03
+#define USB_CLASS_PHYSICAL 0x05
+#define USB_CLASS_STILL_IMAGE 0x06
+#define USB_CLASS_PRINTER 0x07
+#define USB_CLASS_MASS_STORAGE 0x08
+#define USB_CLASS_HUB 0x09
+#define USB_CLASS_CDC_DATA 0x0a
+#define USB_CLASS_CSCID 0x0b
+#define USB_CLASS_CONTENT_SEC 0x0d
+#define USB_CLASS_VIDEO 0x0e
+#define USB_CLASS_BILLBOARD 0x11
+#define USB_CLASS_WIRELESS_CONTROLLER 0xe0
+#define USB_CLASS_MISC 0xef
+#define USB_CLASS_APP_SPEC 0xfe
+#define USB_CLASS_VENDOR_SPEC 0xff
+
+/* USB Vendor ID assigned to Google LLC */
 #define USB_VID_GOOGLE 0x18d1
 
 /* Google specific SubClass/Protocol assignments */
 #define USB_SUBCLASS_GOOGLE_SERIAL 0x50
 #define USB_PROTOCOL_GOOGLE_SERIAL 0x01
 
-#define USB_SUBCLASS_GOOGLE_SPI    0x51
-#define USB_PROTOCOL_GOOGLE_SPI    0x02
+#define USB_SUBCLASS_GOOGLE_SPI 0x51
+#define USB_PROTOCOL_GOOGLE_SPI 0x02
 
-#define USB_SUBCLASS_GOOGLE_I2C    0x52
-#define USB_PROTOCOL_GOOGLE_I2C    0x01
+#define USB_SUBCLASS_GOOGLE_I2C 0x52
+#define USB_PROTOCOL_GOOGLE_I2C 0x01
 
 #define USB_SUBCLASS_GOOGLE_UPDATE 0x53
 #define USB_PROTOCOL_GOOGLE_UPDATE 0xff
 
 /* Double define for cr50 code freeze.
  * TODO(vbendeb): dedupe this. */
-#define USB_SUBCLASS_GOOGLE_CR50   0x53
+#define USB_SUBCLASS_GOOGLE_CR50 0x53
 /* We can use any protocol we want */
 #define USB_PROTOCOL_GOOGLE_CR50_NON_HC_FW_UPDATE 0xff
 
-#define USB_SUBCLASS_GOOGLE_POWER  0x54
-#define USB_PROTOCOL_GOOGLE_POWER  0x01
+#define USB_SUBCLASS_GOOGLE_POWER 0x54
+#define USB_PROTOCOL_GOOGLE_POWER 0x01
 
 #define USB_SUBCLASS_GOOGLE_HEATMAP 0x55
 #define USB_PROTOCOL_GOOGLE_HEATMAP 0x01
@@ -218,72 +220,71 @@ struct usb_endpoint_descriptor {
 
 /* bRequestType fields */
 /* direction field */
-#define USB_DIR_OUT                0    /* from host to uC */
-#define USB_DIR_IN                 0x80 /* from uC to host */
+#define USB_DIR_OUT 0 /* from host to uC */
+#define USB_DIR_IN 0x80 /* from uC to host */
 /* type field */
-#define USB_TYPE_MASK              (0x03 << 5)
-#define USB_TYPE_STANDARD          (0x00 << 5)
-#define USB_TYPE_CLASS             (0x01 << 5)
-#define USB_TYPE_VENDOR            (0x02 << 5)
-#define USB_TYPE_RESERVED          (0x03 << 5)
+#define USB_TYPE_MASK (0x03 << 5)
+#define USB_TYPE_STANDARD (0x00 << 5)
+#define USB_TYPE_CLASS (0x01 << 5)
+#define USB_TYPE_VENDOR (0x02 << 5)
+#define USB_TYPE_RESERVED (0x03 << 5)
 /* recipient field */
-#define USB_RECIP_MASK             0x1f
-#define USB_RECIP_DEVICE           0x00
-#define USB_RECIP_INTERFACE        0x01
-#define USB_RECIP_ENDPOINT         0x02
-#define USB_RECIP_OTHER            0x03
+#define USB_RECIP_MASK 0x1f
+#define USB_RECIP_DEVICE 0x00
+#define USB_RECIP_INTERFACE 0x01
+#define USB_RECIP_ENDPOINT 0x02
+#define USB_RECIP_OTHER 0x03
 
 /* Standard requests for bRequest field in a SETUP packet. */
-#define USB_REQ_GET_STATUS         0x00
-#define USB_REQ_GET_STATUS_SELF_POWERED  BIT(0)
+#define USB_REQ_GET_STATUS 0x00
+#define USB_REQ_GET_STATUS_SELF_POWERED BIT(0)
 #define USB_REQ_GET_STATUS_REMOTE_WAKEUP BIT(1)
-#define USB_REQ_CLEAR_FEATURE      0x01
-#define USB_REQ_SET_FEATURE        0x03
-#define USB_REQ_FEATURE_ENDPOINT_HALT        0x0000
+#define USB_REQ_CLEAR_FEATURE 0x01
+#define USB_REQ_SET_FEATURE 0x03
+#define USB_REQ_FEATURE_ENDPOINT_HALT 0x0000
 #define USB_REQ_FEATURE_DEVICE_REMOTE_WAKEUP 0x0001
-#define USB_REQ_FEATURE_TEST_MODE            0x0002
-#define USB_REQ_SET_ADDRESS        0x05
-#define USB_REQ_GET_DESCRIPTOR     0x06
-#define USB_REQ_SET_DESCRIPTOR     0x07
-#define USB_REQ_GET_CONFIGURATION  0x08
-#define USB_REQ_SET_CONFIGURATION  0x09
-#define USB_REQ_GET_INTERFACE      0x0A
-#define USB_REQ_SET_INTERFACE      0x0B
-#define USB_REQ_SYNCH_FRAME        0x0C
+#define USB_REQ_FEATURE_TEST_MODE 0x0002
+#define USB_REQ_SET_ADDRESS 0x05
+#define USB_REQ_GET_DESCRIPTOR 0x06
+#define USB_REQ_SET_DESCRIPTOR 0x07
+#define USB_REQ_GET_CONFIGURATION 0x08
+#define USB_REQ_SET_CONFIGURATION 0x09
+#define USB_REQ_GET_INTERFACE 0x0A
+#define USB_REQ_SET_INTERFACE 0x0B
+#define USB_REQ_SYNCH_FRAME 0x0C
 
 /* WebUSB URL descriptors */
-#define WEBUSB_REQ_GET_URL         0x02
-#define USB_DT_WEBUSB_URL          0x03
+#define WEBUSB_REQ_GET_URL 0x02
+#define USB_DT_WEBUSB_URL 0x03
 
-#define USB_URL_SCHEME_HTTP       0x00
-#define USB_URL_SCHEME_HTTPS      0x01
-#define USB_URL_SCHEME_NONE       0xff
+#define USB_URL_SCHEME_HTTP 0x00
+#define USB_URL_SCHEME_HTTPS 0x01
+#define USB_URL_SCHEME_NONE 0xff
 
 /*
  * URL descriptor helper.
  * (similar to string descriptor but UTF-8 instead of UTF-16)
  */
-#define USB_URL_DESC(scheme, str) \
-	(const void *)&(const struct { \
-		uint8_t _len; \
-		uint8_t _type; \
-		uint8_t _scheme; \
-		char _data[sizeof(str)]; \
-	}) { \
-		/* Total size of the descriptor is : \
+#define USB_URL_DESC(scheme, str)                                  \
+	(const void *)&(const struct {                             \
+		uint8_t _len;                                      \
+		uint8_t _type;                                     \
+		uint8_t _scheme;                                   \
+		char _data[sizeof(str)];                           \
+	})                                                         \
+	{                                                          \
+		/* Total size of the descriptor is :               \
 		 * size of the UTF-8 text plus the len/type fields \
-		 * minus the string 0-termination \
-		 */ \
-		sizeof(str) + 3 - 1, \
-		USB_DT_WEBUSB_URL, \
-		USB_URL_SCHEME_##scheme, \
-		str \
+		 * minus the string 0-termination                  \
+		 */                                                \
+		sizeof(str) + 3 - 1, USB_DT_WEBUSB_URL,            \
+			USB_URL_SCHEME_##scheme, str               \
 	}
 
 /* Setup Packet */
 struct usb_setup_packet {
-	uint8_t  bmRequestType;
-	uint8_t  bRequest;
+	uint8_t bmRequestType;
+	uint8_t bRequest;
 	uint16_t wValue;
 	uint16_t wIndex;
 	uint16_t wLength;
@@ -326,19 +327,18 @@ struct usb_ms_ext_compat_id_desc {
 #define WIDESTR(quote) WIDESTR2(quote)
 #define WIDESTR2(quote) L##quote
 
-#define USB_STRING_DESC(str) \
-	(const void *)&(const struct { \
-		uint8_t _len; \
-		uint8_t _type; \
-		wchar_t _data[sizeof(str)]; \
-	}) { \
-		/* Total size of the descriptor is : \
-		 * size of the UTF-16 text plus the len/type fields \
-                 * minus the string 0-termination \
-                 */ \
-		sizeof(WIDESTR(str)) + 2 - 2, \
-		USB_DT_STRING, \
-		WIDESTR(str) \
+#define USB_STRING_DESC(str)                                              \
+	(const void *)&(const struct {                                    \
+		uint8_t _len;                                             \
+		uint8_t _type;                                            \
+		wchar_t _data[sizeof(str)];                               \
+	})                                                                \
+	{                                                                 \
+		/* Total size of the descriptor is :                      \
+		 * size of the UTF-16 text plus the len/type fields       \
+		 * minus the string 0-termination                         \
+		 */                                                       \
+		sizeof(WIDESTR(str)) + 2 - 2, USB_DT_STRING, WIDESTR(str) \
 	}
 
 /*
@@ -346,21 +346,21 @@ struct usb_ms_ext_compat_id_desc {
  * windows to request a MS Compatible ID Descriptor and then enables Windows OS
  * to load the correct driver for a USB-EP
  */
-#define USB_MS_STRING_DESC(str) \
-	((const void *)&(const struct { \
-		uint8_t _len; \
-		uint8_t _type; \
-		wchar_t _data[sizeof(str) - 1]; \
-		uint16_t _vendor; \
-	}) { \
-		/* Total size of the descriptor is : \
-		 * size of the UTF-16 text plus the len/type fields \
+#define USB_MS_STRING_DESC(str)                                                \
+	((const void *)&(const struct {                                        \
+		uint8_t _len;                                                  \
+		uint8_t _type;                                                 \
+		wchar_t _data[sizeof(str) - 1];                                \
+		uint16_t _vendor;                                              \
+	}){                                                                    \
+		/* Total size of the descriptor is :                           \
+		 * size of the UTF-16 text plus the len/type fields            \
 		 * plus 2 bytes for vendor code minus the string 0-termination \
-		 */ \
-		sizeof(WIDESTR(str)) + 2 - 2 + 2, \
-		USB_DT_STRING, \
-		WIDESTR(str), \
-		USB_MS_STRING_DESC_VENDOR_CODE,    \
+		 */                                                            \
+		sizeof(WIDESTR(str)) + 2 - 2 + 2,                              \
+		USB_DT_STRING,                                                 \
+		WIDESTR(str),                                                  \
+		USB_MS_STRING_DESC_VENDOR_CODE,                                \
 	})
 
 #ifdef CONFIG_USB_SERIALNO
@@ -370,22 +370,20 @@ struct usb_string_desc {
 	uint8_t _type;
 	wchar_t _data[CONFIG_SERIALNO_LEN];
 };
-#define USB_WR_STRING_DESC(str) \
-	(&(struct usb_string_desc) { \
+#define USB_WR_STRING_DESC(str)                                         \
+	(&(struct usb_string_desc){                                     \
 		/* As above, two bytes metadata, no null terminator. */ \
-		sizeof(WIDESTR(str)) + 2 - 2, \
-		USB_DT_STRING, \
-		WIDESTR(str) \
-})
+		sizeof(WIDESTR(str)) + 2 - 2, USB_DT_STRING, WIDESTR(str) })
 extern struct usb_string_desc *usb_serialno_desc;
 #endif
 
 /* Use these macros for declaring descriptors, to order them properly */
-#define USB_CONF_DESC_VAR(name, varname) varname		\
-	__keep __attribute__((section(".rodata.usb_desc_" STRINGIFY(name))))
+#define USB_CONF_DESC_VAR(name, varname) \
+	varname __keep                   \
+		__attribute__((section(".rodata.usb_desc_" STRINGIFY(name))))
 #define USB_CONF_DESC(name) USB_CONF_DESC_VAR(name, CONCAT2(usb_desc_, name))
 #define USB_IFACE_DESC(num) USB_CONF_DESC(CONCAT3(iface, num, _0iface))
-#define USB_CUSTOM_DESC_VAR(i, name, varname)			\
+#define USB_CUSTOM_DESC_VAR(i, name, varname) \
 	USB_CONF_DESC_VAR(CONCAT4(iface, i, _1, name), varname)
 #define USB_CUSTOM_DESC(i, name) USB_CONF_DESC(CONCAT4(iface, i, _1, name))
 #define USB_EP_DESC(i, num) USB_CONF_DESC(CONCAT4(iface, i, _2ep, num))
@@ -396,10 +394,10 @@ extern const uint8_t __usb_desc_end[];
 #define USB_DESC_SIZE (__usb_desc_end - __usb_desc)
 
 /* These descriptors defined in board code */
-extern const void * const usb_strings[];
+extern const void *const usb_strings[];
 extern const uint8_t usb_string_desc[];
 /* USB string descriptor with the firmware version */
-extern const void * const usb_fw_version;
+extern const void *const usb_fw_version;
 extern const struct bos_context bos_ctx;
 extern const void *webusb_url;
 
diff --git a/include/usb_dp_alt_mode.h b/include/usb_dp_alt_mode.h
index 40b7c321dd..83dc35b085 100644
--- a/include/usb_dp_alt_mode.h
+++ b/include/usb_dp_alt_mode.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -34,6 +34,17 @@ void dp_init(int port);
 bool dp_is_active(int port);
 
 /*
+ * Returns True if DisplayPort mode entry has not started, or mode exit has
+ * already finished.
+ * TODO(b/235984702): Consolidate the DP state API
+ *
+ * @param port      USB-C port number
+ * @return          True if DisplayPort mode is in inactive state
+ *                  False otherwise.
+ */
+bool dp_is_idle(int port);
+
+/*
  * Checks whether the mode entry sequence for DisplayPort alternate mode is done
  * for a port.
  *
@@ -52,7 +63,7 @@ bool dp_entry_is_done(int port);
  * @param vdm       VDM from ACK
  */
 void dp_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count,
-		uint32_t *vdm);
+		  uint32_t *vdm);
 
 /*
  * Handles NAKed (or Not Supported or timed out) DisplayPort VDM requests.
@@ -77,4 +88,4 @@ void dp_vdm_naked(int port, enum tcpci_msg_type type, uint8_t vdm_cmd);
 enum dpm_msg_setup_status dp_setup_next_vdm(int port, int *vdo_count,
 					    uint32_t *vdm);
 
-#endif  /* __CROS_EC_USB_DP_ALT_MODE_H */
+#endif /* __CROS_EC_USB_DP_ALT_MODE_H */
diff --git a/include/usb_emsg.h b/include/usb_emsg.h
index 7b418cefdc..181065156c 100644
--- a/include/usb_emsg.h
+++ b/include/usb_emsg.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/usb_hid.h b/include/usb_hid.h
index e7b1cfe74b..0d49a9b38e 100644
--- a/include/usb_hid.h
+++ b/include/usb_hid.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,39 +8,39 @@
 #ifndef __CROS_EC_USB_HID_H
 #define __CROS_EC_USB_HID_H
 
-#define USB_HID_SUBCLASS_BOOT     1
+#define USB_HID_SUBCLASS_BOOT 1
 #define USB_HID_PROTOCOL_KEYBOARD 1
-#define USB_HID_PROTOCOL_MOUSE    2
+#define USB_HID_PROTOCOL_MOUSE 2
 
 /* USB HID Class requests */
-#define USB_HID_REQ_GET_REPORT    0x01
-#define USB_HID_REQ_GET_IDLE      0x02
-#define USB_HID_REQ_GET_PROTOCOL  0x03
-#define USB_HID_REQ_SET_REPORT    0x09
-#define USB_HID_REQ_SET_IDLE      0x0A
-#define USB_HID_REQ_SET_PROTOCOL  0x0B
+#define USB_HID_REQ_GET_REPORT 0x01
+#define USB_HID_REQ_GET_IDLE 0x02
+#define USB_HID_REQ_GET_PROTOCOL 0x03
+#define USB_HID_REQ_SET_REPORT 0x09
+#define USB_HID_REQ_SET_IDLE 0x0A
+#define USB_HID_REQ_SET_PROTOCOL 0x0B
 
 /* USB HID class descriptor types */
-#define USB_HID_DT_HID            (USB_TYPE_CLASS | 0x01)
-#define USB_HID_DT_REPORT         (USB_TYPE_CLASS | 0x02)
-#define USB_HID_DT_PHYSICAL       (USB_TYPE_CLASS | 0x03)
+#define USB_HID_DT_HID (USB_TYPE_CLASS | 0x01)
+#define USB_HID_DT_REPORT (USB_TYPE_CLASS | 0x02)
+#define USB_HID_DT_PHYSICAL (USB_TYPE_CLASS | 0x03)
 
 /* Pre-defined report types */
-#define REPORT_TYPE_INPUT         0x01
-#define REPORT_TYPE_OUTPUT        0x02
-#define REPORT_TYPE_FEATURE       0x03
+#define REPORT_TYPE_INPUT 0x01
+#define REPORT_TYPE_OUTPUT 0x02
+#define REPORT_TYPE_FEATURE 0x03
 
 struct usb_hid_class_descriptor {
-	uint8_t  bDescriptorType;
+	uint8_t bDescriptorType;
 	uint16_t wDescriptorLength;
 } __packed;
 
 struct usb_hid_descriptor {
-	uint8_t  bLength;
-	uint8_t  bDescriptorType;
+	uint8_t bLength;
+	uint8_t bDescriptorType;
 	uint16_t bcdHID;
-	uint8_t  bCountryCode;
-	uint8_t  bNumDescriptors;
+	uint8_t bCountryCode;
+	uint8_t bNumDescriptors;
 	struct usb_hid_class_descriptor desc[1];
 } __packed;
 
diff --git a/include/usb_hid_touchpad.h b/include/usb_hid_touchpad.h
index 1e6d4cf832..23c16a0201 100644
--- a/include/usb_hid_touchpad.h
+++ b/include/usb_hid_touchpad.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,27 +10,27 @@
 
 #define USB_HID_TOUCHPAD_TIMESTAMP_UNIT 100 /* usec */
 
-#define REPORT_ID_TOUCHPAD		0x01
-#define REPORT_ID_DEVICE_CAPS		0x0A
-#define REPORT_ID_DEVICE_CERT		0x0B
+#define REPORT_ID_TOUCHPAD 0x01
+#define REPORT_ID_DEVICE_CAPS 0x0A
+#define REPORT_ID_DEVICE_CERT 0x0B
 
-#define MAX_FINGERS			5
+#define MAX_FINGERS 5
 
 struct usb_hid_touchpad_report {
 	uint8_t id; /* 0x01 */
 	struct {
-		uint16_t confidence:1;
-		uint16_t tip:1;
-		uint16_t inrange:1;
-		uint16_t id:4;
-		uint16_t pressure:9;
-		uint16_t width:12;
-		uint16_t height:12;
-		uint16_t x:12;
-		uint16_t y:12;
+		uint16_t confidence : 1;
+		uint16_t tip : 1;
+		uint16_t inrange : 1;
+		uint16_t id : 4;
+		uint16_t pressure : 9;
+		uint16_t width : 12;
+		uint16_t height : 12;
+		uint16_t x : 12;
+		uint16_t y : 12;
 	} __packed finger[MAX_FINGERS];
-	uint8_t count:7;
-	uint8_t button:1;
+	uint8_t count : 7;
+	uint8_t button : 1;
 	uint16_t timestamp;
 } __packed;
 
diff --git a/include/usb_i2c.h b/include/usb_i2c.h
index fd79293014..5c8bf8c874 100644
--- a/include/usb_i2c.h
+++ b/include/usb_i2c.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -99,28 +99,28 @@
  */
 
 enum usb_i2c_error {
-	USB_I2C_SUCCESS             = 0x0000,
-	USB_I2C_TIMEOUT             = 0x0001,
-	USB_I2C_BUSY                = 0x0002,
+	USB_I2C_SUCCESS = 0x0000,
+	USB_I2C_TIMEOUT = 0x0001,
+	USB_I2C_BUSY = 0x0002,
 	USB_I2C_WRITE_COUNT_INVALID = 0x0003,
-	USB_I2C_READ_COUNT_INVALID  = 0x0004,
-	USB_I2C_PORT_INVALID        = 0x0005,
-	USB_I2C_DISABLED            = 0x0006,
-	USB_I2C_MISSING_HANDLER     = 0x0007,
+	USB_I2C_READ_COUNT_INVALID = 0x0004,
+	USB_I2C_PORT_INVALID = 0x0005,
+	USB_I2C_DISABLED = 0x0006,
+	USB_I2C_MISSING_HANDLER = 0x0007,
 	USB_I2C_UNSUPPORTED_COMMAND = 0x0008,
-	USB_I2C_UNKNOWN_ERROR       = 0x8000,
+	USB_I2C_UNKNOWN_ERROR = 0x8000,
 };
 
-
 #define USB_I2C_WRITE_BUFFER (CONFIG_USB_I2C_MAX_WRITE_COUNT + 4)
 /* If read payload is larger or equal to 128 bytes, header contains rc1 */
-#define USB_I2C_READ_BUFFER  ((CONFIG_USB_I2C_MAX_READ_COUNT < 128) ?	\
-	(CONFIG_USB_I2C_MAX_READ_COUNT + 4) :				\
-	(CONFIG_USB_I2C_MAX_READ_COUNT + 6))
+#define USB_I2C_READ_BUFFER                            \
+	((CONFIG_USB_I2C_MAX_READ_COUNT < 128) ?       \
+		 (CONFIG_USB_I2C_MAX_READ_COUNT + 4) : \
+		 (CONFIG_USB_I2C_MAX_READ_COUNT + 6))
 
-#define USB_I2C_BUFFER_SIZE					\
-	(USB_I2C_READ_BUFFER > USB_I2C_WRITE_BUFFER ?	\
-		USB_I2C_READ_BUFFER : USB_I2C_WRITE_BUFFER)
+#define USB_I2C_BUFFER_SIZE                                                 \
+	(USB_I2C_READ_BUFFER > USB_I2C_WRITE_BUFFER ? USB_I2C_READ_BUFFER : \
+						      USB_I2C_WRITE_BUFFER)
 
 BUILD_ASSERT(POWER_OF_TWO(USB_I2C_READ_BUFFER));
 BUILD_ASSERT(POWER_OF_TWO(USB_I2C_WRITE_BUFFER));
@@ -156,28 +156,18 @@ extern struct consumer_ops const usb_i2c_consumer_ops;
  * ENDPOINT is the index of the USB bulk endpoint used for receiving and
  * transmitting bytes.
  */
-#define USB_I2C_CONFIG(NAME,						\
-		       INTERFACE,					\
-		       INTERFACE_NAME,					\
-		       ENDPOINT)					\
-	static uint16_t							\
-		CONCAT2(NAME, _buffer_)					\
-			[USB_I2C_BUFFER_SIZE / 2];			\
-	static void CONCAT2(NAME, _deferred_)(void);			\
-	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_));			\
-	static struct queue const CONCAT2(NAME, _to_usb_);		\
-	static struct queue const CONCAT3(usb_to_, NAME, _);		\
-	USB_STREAM_CONFIG_FULL(CONCAT2(NAME, _usb_),			\
-			       INTERFACE,				\
-			       USB_CLASS_VENDOR_SPEC,			\
-			       USB_SUBCLASS_GOOGLE_I2C,			\
-			       USB_PROTOCOL_GOOGLE_I2C,			\
-			       INTERFACE_NAME,				\
-			       ENDPOINT,				\
-			       USB_MAX_PACKET_SIZE,			\
-			       USB_MAX_PACKET_SIZE,			\
-			       CONCAT3(usb_to_, NAME, _),		\
-			       CONCAT2(NAME, _to_usb_))			\
+#define USB_I2C_CONFIG(NAME, INTERFACE, INTERFACE_NAME, ENDPOINT)              \
+	static uint16_t CONCAT2(NAME, _buffer_)[USB_I2C_BUFFER_SIZE / 2];      \
+	static void CONCAT2(NAME, _deferred_)(void);                           \
+	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_));                           \
+	static struct queue const CONCAT2(NAME, _to_usb_);                     \
+	static struct queue const CONCAT3(usb_to_, NAME, _);                   \
+	USB_STREAM_CONFIG_FULL(CONCAT2(NAME, _usb_), INTERFACE,                \
+			       USB_CLASS_VENDOR_SPEC, USB_SUBCLASS_GOOGLE_I2C, \
+			       USB_PROTOCOL_GOOGLE_I2C, INTERFACE_NAME,        \
+			       ENDPOINT, USB_MAX_PACKET_SIZE,                  \
+			       USB_MAX_PACKET_SIZE, CONCAT3(usb_to_, NAME, _), \
+			       CONCAT2(NAME, _to_usb_))                        \
 	struct usb_i2c_config const NAME = {				\
 		.buffer    = CONCAT2(NAME, _buffer_),			\
 		.deferred  = &CONCAT2(NAME, _deferred__data),		\
@@ -186,15 +176,17 @@ extern struct consumer_ops const usb_i2c_consumer_ops;
 			.ops   = &usb_i2c_consumer_ops,			\
 		},							\
 		.tx_queue = &CONCAT2(NAME, _to_usb_),			\
-	};								\
-	static struct queue const CONCAT2(NAME, _to_usb_) =		\
-		QUEUE_DIRECT(USB_I2C_READ_BUFFER, uint8_t,	\
-		null_producer, CONCAT2(NAME, _usb_).consumer);		\
-	static struct queue const CONCAT3(usb_to_, NAME, _) =		\
-		QUEUE_DIRECT(USB_I2C_WRITE_BUFFER, uint8_t,	\
-		CONCAT2(NAME, _usb_).producer, NAME.consumer);		\
-	static void CONCAT2(NAME, _deferred_)(void)			\
-	{ usb_i2c_deferred(&NAME); }
+	};                              \
+	static struct queue const CONCAT2(NAME, _to_usb_) =                    \
+		QUEUE_DIRECT(USB_I2C_READ_BUFFER, uint8_t, null_producer,      \
+			     CONCAT2(NAME, _usb_).consumer);                   \
+	static struct queue const CONCAT3(usb_to_, NAME, _) =                  \
+		QUEUE_DIRECT(USB_I2C_WRITE_BUFFER, uint8_t,                    \
+			     CONCAT2(NAME, _usb_).producer, NAME.consumer);    \
+	static void CONCAT2(NAME, _deferred_)(void)                            \
+	{                                                                      \
+		usb_i2c_deferred(&NAME);                                       \
+	}
 
 /*
  * Handle I2C request in a deferred callback.
@@ -224,11 +216,7 @@ int usb_i2c_board_is_enabled(void);
  * Function to call to register a handler for commands sent to the special i2c
  * address above.
  */
-int usb_i2c_register_cros_cmd_handler(int (*cmd_handler)
-				      (void *data_in,
-				       size_t in_size,
-				       void *data_out,
-				       size_t out_size));
-
+int usb_i2c_register_cros_cmd_handler(int (*cmd_handler)(
+	void *data_in, size_t in_size, void *data_out, size_t out_size));
 
-#endif  /* __CROS_USB_I2C_H */
+#endif /* __CROS_USB_I2C_H */
diff --git a/include/usb_mode.h b/include/usb_mode.h
index 4333cc851e..4cf7710960 100644
--- a/include/usb_mode.h
+++ b/include/usb_mode.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/usb_mux.h b/include/usb_mux.h
index 0d43257994..d510a347d4 100644
--- a/include/usb_mux.h
+++ b/include/usb_mux.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -28,6 +28,7 @@
 #define USB_MUX_FLAG_NOT_TCPC BIT(0) /* TCPC/MUX device used only as MUX */
 #define USB_MUX_FLAG_SET_WITHOUT_FLIP BIT(1) /* SET should not flip */
 #define USB_MUX_FLAG_RESETS_IN_G3 BIT(2) /* Mux chip will reset in G3 */
+#define USB_MUX_FLAG_POLARITY_INVERTED BIT(3) /* Mux polarity is inverted */
 
 #endif /* CONFIG_ZEPHYR */
 
@@ -127,9 +128,6 @@ struct usb_mux {
 	/* Mux driver */
 	const struct usb_mux_driver *driver;
 
-	/* Linked list chain of secondary MUXes. NULL terminated */
-	const struct usb_mux *next_mux;
-
 	/**
 	 * Optional method for tuning for USB mux during mux->driver->init().
 	 *
@@ -157,11 +155,19 @@ struct usb_mux {
 	 * @param[out] ack_required: indication of whether this function
 	 *	       requires a wait for an AP ACK after
 	 */
-	void (*hpd_update)(const struct usb_mux *me,
-			   mux_state_t mux_state,
+	void (*hpd_update)(const struct usb_mux *me, mux_state_t mux_state,
 			   bool *ack_required);
 };
 
+/* Linked list chain of secondary MUXes. NULL terminated */
+struct usb_mux_chain {
+	/* Structure describing USB mux */
+	const struct usb_mux *mux;
+
+	/* Pointer to next mux */
+	const struct usb_mux_chain *next;
+};
+
 /* Supported USB mux drivers */
 extern const struct usb_mux_driver amd_fp5_usb_mux_driver;
 extern const struct usb_mux_driver amd_fp6_usb_mux_driver;
@@ -177,9 +183,9 @@ extern const struct usb_mux_driver virtual_usb_mux_driver;
 
 /* USB muxes present in system, ordered by PD port #, defined at board-level */
 #ifdef CONFIG_USB_MUX_RUNTIME_CONFIG
-extern struct usb_mux usb_muxes[];
+extern struct usb_mux_chain usb_muxes[];
 #else
-extern const struct usb_mux usb_muxes[];
+extern const struct usb_mux_chain usb_muxes[];
 #endif
 
 /* Supported hpd_update functions */
@@ -193,30 +199,30 @@ void virtual_hpd_update(const struct usb_mux *me, mux_state_t mux_state,
 #ifdef CONFIG_USB_PD_TCPM_MUX
 static inline int mux_write(const struct usb_mux *me, int reg, int val)
 {
-	return me->flags & USB_MUX_FLAG_NOT_TCPC
-		? i2c_write8(me->i2c_port, me->i2c_addr_flags, reg, val)
-		: tcpc_write(me->usb_port, reg, val);
+	return me->flags & USB_MUX_FLAG_NOT_TCPC ?
+		       i2c_write8(me->i2c_port, me->i2c_addr_flags, reg, val) :
+		       tcpc_write(me->usb_port, reg, val);
 }
 
 static inline int mux_read(const struct usb_mux *me, int reg, int *val)
 {
-	return me->flags & USB_MUX_FLAG_NOT_TCPC
-		? i2c_read8(me->i2c_port, me->i2c_addr_flags, reg, val)
-		: tcpc_read(me->usb_port, reg, val);
+	return me->flags & USB_MUX_FLAG_NOT_TCPC ?
+		       i2c_read8(me->i2c_port, me->i2c_addr_flags, reg, val) :
+		       tcpc_read(me->usb_port, reg, val);
 }
 
 static inline int mux_write16(const struct usb_mux *me, int reg, int val)
 {
-	return me->flags & USB_MUX_FLAG_NOT_TCPC
-		? i2c_write16(me->i2c_port, me->i2c_addr_flags, reg, val)
-		: tcpc_write16(me->usb_port, reg, val);
+	return me->flags & USB_MUX_FLAG_NOT_TCPC ?
+		       i2c_write16(me->i2c_port, me->i2c_addr_flags, reg, val) :
+		       tcpc_write16(me->usb_port, reg, val);
 }
 
 static inline int mux_read16(const struct usb_mux *me, int reg, int *val)
 {
-	return me->flags & USB_MUX_FLAG_NOT_TCPC
-		? i2c_read16(me->i2c_port, me->i2c_addr_flags, reg, val)
-		: tcpc_read16(me->usb_port, reg, val);
+	return me->flags & USB_MUX_FLAG_NOT_TCPC ?
+		       i2c_read16(me->i2c_port, me->i2c_addr_flags, reg, val) :
+		       tcpc_read16(me->usb_port, reg, val);
 }
 #endif /* CONFIG_USB_PD_TCPM_MUX */
 
@@ -235,8 +241,8 @@ void usb_mux_init(int port);
  * @param usb_config usb2.0 selected function.
  * @param polarity plug polarity (0=CC1, 1=CC2).
  */
-void usb_mux_set(int port, mux_state_t mux_mode,
-		 enum usb_switch usb_config, int polarity);
+void usb_mux_set(int port, mux_state_t mux_mode, enum usb_switch usb_config,
+		 int polarity);
 
 /**
  * Configure superspeed muxes on type-C port for only one index in the mux
diff --git a/include/usb_pd.h b/include/usb_pd.h
index d5b6412d69..6254feb963 100644
--- a/include/usb_pd.h
+++ b/include/usb_pd.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,58 +26,56 @@
  */
 #if defined(HAS_TASK_PD_C0) && defined(CONFIG_USB_PD_PORT_MAX_COUNT)
 #define PD_PORT_TO_TASK_ID(port) (TASK_ID_PD_C0 + (port))
-#define TASK_ID_TO_PD_PORT(id) ((id) - TASK_ID_PD_C0)
+#define TASK_ID_TO_PD_PORT(id) ((id)-TASK_ID_PD_C0)
 #else
 #define PD_PORT_TO_TASK_ID(port) -1 /* stub task ID */
 #define TASK_ID_TO_PD_PORT(id) 0
 #endif /* CONFIG_USB_PD_PORT_MAX_COUNT && HAS_TASK_PD_C0 */
 
 enum pd_rx_errors {
-	PD_RX_ERR_INVAL = -1,           /* Invalid packet */
-	PD_RX_ERR_HARD_RESET = -2,      /* Got a Hard-Reset packet */
-	PD_RX_ERR_CRC = -3,             /* CRC mismatch */
-	PD_RX_ERR_ID = -4,              /* Invalid ID number */
+	PD_RX_ERR_INVAL = -1, /* Invalid packet */
+	PD_RX_ERR_HARD_RESET = -2, /* Got a Hard-Reset packet */
+	PD_RX_ERR_CRC = -3, /* CRC mismatch */
+	PD_RX_ERR_ID = -4, /* Invalid ID number */
 	PD_RX_ERR_UNSUPPORTED_SOP = -5, /* Unsupported SOP */
-	PD_RX_ERR_CABLE_RESET = -6      /* Got a Cable-Reset packet */
+	PD_RX_ERR_CABLE_RESET = -6 /* Got a Cable-Reset packet */
 };
 
 /* Events for USB PD task */
 
 /* Outgoing packet event */
-#define PD_EVENT_TX			TASK_EVENT_CUSTOM_BIT(3)
+#define PD_EVENT_TX TASK_EVENT_CUSTOM_BIT(3)
 /* CC line change event */
-#define PD_EVENT_CC			TASK_EVENT_CUSTOM_BIT(4)
+#define PD_EVENT_CC TASK_EVENT_CUSTOM_BIT(4)
 /* TCPC has reset */
-#define PD_EVENT_TCPC_RESET		TASK_EVENT_CUSTOM_BIT(5)
+#define PD_EVENT_TCPC_RESET TASK_EVENT_CUSTOM_BIT(5)
 /* DRP state has changed */
-#define PD_EVENT_UPDATE_DUAL_ROLE	TASK_EVENT_CUSTOM_BIT(6)
+#define PD_EVENT_UPDATE_DUAL_ROLE TASK_EVENT_CUSTOM_BIT(6)
 /*
  * A task, other than the task owning the PD port, accessed the TCPC. The task
  * that owns the port does not send itself this event.
  */
-#define PD_EVENT_DEVICE_ACCESSED	TASK_EVENT_CUSTOM_BIT(7)
+#define PD_EVENT_DEVICE_ACCESSED TASK_EVENT_CUSTOM_BIT(7)
 /* Chipset power state changed */
-#define PD_EVENT_POWER_STATE_CHANGE	TASK_EVENT_CUSTOM_BIT(8)
+#define PD_EVENT_POWER_STATE_CHANGE TASK_EVENT_CUSTOM_BIT(8)
 /* Issue a Hard Reset. */
-#define PD_EVENT_SEND_HARD_RESET	TASK_EVENT_CUSTOM_BIT(9)
+#define PD_EVENT_SEND_HARD_RESET TASK_EVENT_CUSTOM_BIT(9)
 /* Prepare for sysjump */
-#define PD_EVENT_SYSJUMP		TASK_EVENT_CUSTOM_BIT(10)
+#define PD_EVENT_SYSJUMP TASK_EVENT_CUSTOM_BIT(10)
 /* Receive a Hard Reset. */
-#define PD_EVENT_RX_HARD_RESET		TASK_EVENT_CUSTOM_BIT(11)
+#define PD_EVENT_RX_HARD_RESET TASK_EVENT_CUSTOM_BIT(11)
 /* MUX configured notification event */
-#define PD_EVENT_AP_MUX_DONE		TASK_EVENT_CUSTOM_BIT(12)
+#define PD_EVENT_AP_MUX_DONE TASK_EVENT_CUSTOM_BIT(12)
 /* First free event on PD task */
-#define PD_EVENT_FIRST_FREE_BIT		13
+#define PD_EVENT_FIRST_FREE_BIT 13
 
 /* Ensure TCPC is out of low power mode before handling these events. */
-#define PD_EXIT_LOW_POWER_EVENT_MASK \
-	(PD_EVENT_CC | \
-	 PD_EVENT_UPDATE_DUAL_ROLE | \
-	 PD_EVENT_POWER_STATE_CHANGE | \
-	 PD_EVENT_TCPC_RESET)
+#define PD_EXIT_LOW_POWER_EVENT_MASK               \
+	(PD_EVENT_CC | PD_EVENT_UPDATE_DUAL_ROLE | \
+	 PD_EVENT_POWER_STATE_CHANGE | PD_EVENT_TCPC_RESET)
 
 /* --- PD data message helpers --- */
-#define PDO_MAX_OBJECTS   7
+#define PDO_MAX_OBJECTS 7
 #define PDO_MODES (PDO_MAX_OBJECTS - 1)
 
 /* PDO : Power Data Object */
@@ -94,108 +92,105 @@ enum pd_rx_errors {
  *
  * Note: Some bits and decode macros are defined in ec_commands.h
  */
-#define PDO_FIXED_SUSPEND	BIT(28) /* USB Suspend supported */
+#define PDO_FIXED_SUSPEND BIT(28) /* USB Suspend supported */
 /* Higher capability in vSafe5V sink PDO */
-#define PDO_FIXED_SNK_HIGHER_CAP          BIT(28)
-#define PDO_FIXED_FRS_CURR_NOT_SUPPORTED  (0 << 23)
+#define PDO_FIXED_SNK_HIGHER_CAP BIT(28)
+#define PDO_FIXED_FRS_CURR_NOT_SUPPORTED (0 << 23)
 #define PDO_FIXED_FRS_CURR_DFLT_USB_POWER (1 << 23)
-#define PDO_FIXED_FRS_CURR_1A5_AT_5V      (2 << 23)
-#define PDO_FIXED_FRS_CURR_3A0_AT_5V      (3 << 23)
+#define PDO_FIXED_FRS_CURR_1A5_AT_5V (2 << 23)
+#define PDO_FIXED_FRS_CURR_3A0_AT_5V (3 << 23)
 #define PDO_FIXED_PEAK_CURR () /* [21..20] Peak current */
-#define PDO_FIXED_VOLT(mv)  (((mv)/50) << 10) /* Voltage in 50mV units */
-#define PDO_FIXED_CURR(ma)  (((ma)/10) << 0)  /* Max current in 10mA units */
+#define PDO_FIXED_VOLT(mv) (((mv) / 50) << 10) /* Voltage in 50mV units */
+#define PDO_FIXED_CURR(ma) (((ma) / 10) << 0) /* Max current in 10mA units */
 #define PDO_FIXED_GET_VOLT(pdo) (((pdo >> 10) & 0x3FF) * 50)
 #define PDO_FIXED_GET_CURR(pdo) ((pdo & 0x3FF) * 10)
 
-#define PDO_FIXED(mv, ma, flags) (PDO_FIXED_VOLT(mv) |\
-				  PDO_FIXED_CURR(ma) | (flags))
+#define PDO_FIXED(mv, ma, flags) \
+	(PDO_FIXED_VOLT(mv) | PDO_FIXED_CURR(ma) | (flags))
 
 #define PDO_VAR_MAX_VOLT(mv) ((((mv) / 50) & 0x3FF) << 20)
 #define PDO_VAR_MIN_VOLT(mv) ((((mv) / 50) & 0x3FF) << 10)
-#define PDO_VAR_OP_CURR(ma)  ((((ma) / 10) & 0x3FF) << 0)
+#define PDO_VAR_OP_CURR(ma) ((((ma) / 10) & 0x3FF) << 0)
 
-#define PDO_VAR(min_mv, max_mv, op_ma) \
-				(PDO_VAR_MIN_VOLT(min_mv) | \
-				 PDO_VAR_MAX_VOLT(max_mv) | \
-				 PDO_VAR_OP_CURR(op_ma)   | \
-				 PDO_TYPE_VARIABLE)
+#define PDO_VAR(min_mv, max_mv, op_ma)                         \
+	(PDO_VAR_MIN_VOLT(min_mv) | PDO_VAR_MAX_VOLT(max_mv) | \
+	 PDO_VAR_OP_CURR(op_ma) | PDO_TYPE_VARIABLE)
 
 #define PDO_BATT_MAX_VOLT(mv) ((((mv) / 50) & 0x3FF) << 20)
 #define PDO_BATT_MIN_VOLT(mv) ((((mv) / 50) & 0x3FF) << 10)
 #define PDO_BATT_OP_POWER(mw) ((((mw) / 250) & 0x3FF) << 0)
 
-#define PDO_BATT(min_mv, max_mv, op_mw) \
-				(PDO_BATT_MIN_VOLT(min_mv) | \
-				 PDO_BATT_MAX_VOLT(max_mv) | \
-				 PDO_BATT_OP_POWER(op_mw) | \
-				 PDO_TYPE_BATTERY)
+#define PDO_BATT(min_mv, max_mv, op_mw)                          \
+	(PDO_BATT_MIN_VOLT(min_mv) | PDO_BATT_MAX_VOLT(max_mv) | \
+	 PDO_BATT_OP_POWER(op_mw) | PDO_TYPE_BATTERY)
 
 /* RDO : Request Data Object */
-#define RDO_OBJ_POS(n)             (((n) & 0x7) << 28)
-#define RDO_POS(rdo)               (((rdo) >> 28) & 0x7)
-#define RDO_GIVE_BACK              BIT(27)
-#define RDO_CAP_MISMATCH           BIT(26)
-#define RDO_COMM_CAP               BIT(25)
-#define RDO_NO_SUSPEND             BIT(24)
-#define RDO_FIXED_VAR_OP_CURR(ma)  ((((ma) / 10) & 0x3FF) << 10)
+#define RDO_OBJ_POS(n) (((n)&0x7) << 28)
+#define RDO_POS(rdo) (((rdo) >> 28) & 0x7)
+#define RDO_GIVE_BACK BIT(27)
+#define RDO_CAP_MISMATCH BIT(26)
+#define RDO_COMM_CAP BIT(25)
+#define RDO_NO_SUSPEND BIT(24)
+#define RDO_FIXED_VAR_OP_CURR(ma) ((((ma) / 10) & 0x3FF) << 10)
 #define RDO_FIXED_VAR_MAX_CURR(ma) ((((ma) / 10) & 0x3FF) << 0)
 
-#define RDO_BATT_OP_POWER(mw)      ((((mw) / 250) & 0x3FF) << 10)
-#define RDO_BATT_MAX_POWER(mw)     ((((mw) / 250) & 0x3FF) << 0)
+#define RDO_BATT_OP_POWER(mw) ((((mw) / 250) & 0x3FF) << 10)
+#define RDO_BATT_MAX_POWER(mw) ((((mw) / 250) & 0x3FF) << 0)
 
-#define RDO_FIXED(n, op_ma, max_ma, flags) \
-				(RDO_OBJ_POS(n) | (flags) | \
-				RDO_FIXED_VAR_OP_CURR(op_ma) | \
-				RDO_FIXED_VAR_MAX_CURR(max_ma))
+#define RDO_FIXED(n, op_ma, max_ma, flags)                         \
+	(RDO_OBJ_POS(n) | (flags) | RDO_FIXED_VAR_OP_CURR(op_ma) | \
+	 RDO_FIXED_VAR_MAX_CURR(max_ma))
 
-
-#define RDO_BATT(n, op_mw, max_mw, flags) \
-				(RDO_OBJ_POS(n) | (flags) | \
-				RDO_BATT_OP_POWER(op_mw) | \
-				RDO_BATT_MAX_POWER(max_mw))
+#define RDO_BATT(n, op_mw, max_mw, flags)                      \
+	(RDO_OBJ_POS(n) | (flags) | RDO_BATT_OP_POWER(op_mw) | \
+	 RDO_BATT_MAX_POWER(max_mw))
 
 /* BDO : BIST Data Object
  * 31:28 BIST Mode
  *       In PD 3.0, all but Carrier Mode 2 (as Carrier Mode) and Test Data are
- *       reserved.
+ *       reserved, with a new BIST shared mode added
  * 27:16 Reserved
  * 15:0  Returned error counters (reserved in PD 3.0)
  */
-#define BDO_MODE_RECV       (0 << 28)
-#define BDO_MODE_TRANSMIT   BIT(28)
-#define BDO_MODE_COUNTERS   (2 << 28)
-#define BDO_MODE_CARRIER0   (3 << 28)
-#define BDO_MODE_CARRIER1   (4 << 28)
-#define BDO_MODE_CARRIER2   (5 << 28)
-#define BDO_MODE_CARRIER3   (6 << 28)
-#define BDO_MODE_EYE        (7 << 28)
-#define BDO_MODE_TEST_DATA  (8 << 28)
-
-#define BDO(mode, cnt)      ((mode) | ((cnt) & 0xFFFF))
-
-#define BIST_MODE(n)          ((n) >> 28)
-#define BIST_ERROR_COUNTER(n) ((n) & 0xffff)
-#define BIST_RECEIVER_MODE    0
-#define BIST_TRANSMIT_MODE    1
+#define BDO_MODE_RECV (BIST_RECEIVER_MODE << 28)
+#define BDO_MODE_TRANSMIT (BIST_TRANSMIT_MODE << 28)
+#define BDO_MODE_COUNTERS (BIST_RETURNED_COUNTER << 28)
+#define BDO_MODE_CARRIER0 (BIST_CARRIER_MODE_0 << 28)
+#define BDO_MODE_CARRIER1 (BIST_CARRIER_MODE_1 << 28)
+#define BDO_MODE_CARRIER2 (BIST_CARRIER_MODE_2 << 28)
+#define BDO_MODE_CARRIER3 (BIST_CARRIER_MODE_3 << 28)
+#define BDO_MODE_EYE (BIST_EYE_PATTERN << 28)
+#define BDO_MODE_TEST_DATA (BIST_TEST_DATA << 28)
+#define BDO_MODE_SHARED_ENTER (BIST_SHARED_MODE_ENTER << 28)
+#define BDO_MODE_SHARED_EXIT (BIST_SHARED_MODE_EXIT << 28)
+
+#define BDO(mode, cnt) ((mode) | ((cnt)&0xFFFF))
+
+#define BIST_MODE(n) ((n) >> 28)
+#define BIST_ERROR_COUNTER(n) ((n)&0xffff)
+#define BIST_RECEIVER_MODE 0
+#define BIST_TRANSMIT_MODE 1
 #define BIST_RETURNED_COUNTER 2
-#define BIST_CARRIER_MODE_0   3
-#define BIST_CARRIER_MODE_1   4
-#define BIST_CARRIER_MODE_2   5
-#define BIST_CARRIER_MODE_3   6
-#define BIST_EYE_PATTERN      7
-#define BIST_TEST_DATA        8
+#define BIST_CARRIER_MODE_0 3
+#define BIST_CARRIER_MODE_1 4
+#define BIST_CARRIER_MODE_2 5
+#define BIST_CARRIER_MODE_3 6
+#define BIST_EYE_PATTERN 7
+#define BIST_TEST_DATA 8
+#define BIST_SHARED_MODE_ENTER 9
+#define BIST_SHARED_MODE_EXIT 10
 
 #define SVID_DISCOVERY_MAX 16
 
 /* Timers */
-#define PD_T_SINK_TX                (18*MSEC) /* between 16ms and 20 */
-#define PD_T_CHUNKING_NOT_SUPPORTED (45*MSEC) /* between 40ms and 50ms */
-#define PD_T_HARD_RESET_COMPLETE     (5*MSEC) /* between 4ms and 5ms*/
-#define PD_T_HARD_RESET_RETRY        (1*MSEC) /* 1ms */
-#define PD_T_SEND_SOURCE_CAP       (100*MSEC) /* between 100ms and 200ms */
-#define PD_T_SINK_WAIT_CAP         (575*MSEC) /* between 310ms and 620ms */
-#define PD_T_SINK_TRANSITION        (35*MSEC) /* between 20ms and 35ms */
-#define PD_T_SOURCE_ACTIVITY        (45*MSEC) /* between 40ms and 50ms */
+#define PD_T_SINK_TX (18 * MSEC) /* between 16ms and 20 */
+#define PD_T_CHUNKING_NOT_SUPPORTED (45 * MSEC) /* between 40ms and 50ms */
+#define PD_T_HARD_RESET_COMPLETE (5 * MSEC) /* between 4ms and 5ms*/
+#define PD_T_HARD_RESET_RETRY (1 * MSEC) /* 1ms */
+#define PD_T_SEND_SOURCE_CAP (100 * MSEC) /* between 100ms and 200ms */
+#define PD_T_SINK_WAIT_CAP (575 * MSEC) /* between 310ms and 620ms */
+#define PD_T_SINK_TRANSITION (35 * MSEC) /* between 20ms and 35ms */
+#define PD_T_SOURCE_ACTIVITY (45 * MSEC) /* between 40ms and 50ms */
 /*
  * Adjusting for TCPMv2 PD2 Compliance. In tests like TD.PD.SRC.E5 this
  * value is the duration before the Hard Reset can be sent. Setting the
@@ -207,92 +202,99 @@ enum pd_rx_errors {
  * usb_pd unit test.
  */
 #ifndef CONFIG_USB_PD_TCPMV2
-#define PD_T_SENDER_RESPONSE        (30*MSEC) /* between 24ms and 30ms */
+#define PD_T_SENDER_RESPONSE (30 * MSEC) /* between 24ms and 30ms */
 #else
-#define PD_T_SENDER_RESPONSE        (24*MSEC) /* between 24ms and 30ms */
+/*
+ * In USB Power Delivery Specification Revision 3.1, Version 1.5,
+ * the tSenderResponse have changed to min 26/ max 32 ms.
+ */
+#define PD_T_SENDER_RESPONSE (26 * MSEC) /* between 26ms and 32ms */
 #endif
-#define PD_T_PS_TRANSITION         (500*MSEC) /* between 450ms and 550ms */
-#define PD_T_PS_SOURCE_ON          (480*MSEC) /* between 390ms and 480ms */
-#define PD_T_PS_SOURCE_OFF         (835*MSEC) /* between 750ms and 920ms */
-#define PD_T_PS_HARD_RESET          (25*MSEC) /* between 25ms and 35ms */
-#define PD_T_ERROR_RECOVERY        (240*MSEC) /* min 240ms if sourcing VConn */
-#define PD_T_CC_DEBOUNCE           (100*MSEC) /* between 100ms and 200ms */
+#define PD_T_PS_TRANSITION (500 * MSEC) /* between 450ms and 550ms */
+/*
+ * This is adjusted for PD3.1 Compliance test TEST.PD.PROT.SRC.10.
+ */
+#define PD_T_PS_SOURCE_ON (435 * MSEC) /* between 390ms and 480ms */
+#define PD_T_PS_SOURCE_OFF (835 * MSEC) /* between 750ms and 920ms */
+#define PD_T_PS_HARD_RESET (25 * MSEC) /* between 25ms and 35ms */
+#define PD_T_ERROR_RECOVERY (240 * MSEC) /* min 240ms if sourcing VConn */
+#define PD_T_CC_DEBOUNCE (100 * MSEC) /* between 100ms and 200ms */
 /* DRP_SNK + DRP_SRC must be between 50ms and 100ms with 30%-70% duty cycle */
-#define PD_T_DRP_SNK                (40*MSEC) /* toggle time for sink DRP */
-#define PD_T_DRP_SRC                (30*MSEC) /* toggle time for source DRP */
-#define PD_T_DEBOUNCE               (15*MSEC) /* between 10ms and 20ms */
-#define PD_T_TRY_CC_DEBOUNCE        (15*MSEC) /* between 10ms and 20ms */
-#define PD_T_SINK_ADJ               (55*MSEC) /* between tPDDebounce and 60ms */
-#define PD_T_SRC_RECOVER           (760*MSEC) /* between 660ms and 1000ms */
-#define PD_T_SRC_RECOVER_MAX      (1000*MSEC) /* 1000ms */
-#define PD_T_SRC_TURN_ON           (275*MSEC) /* 275ms */
-#define PD_T_SAFE_0V               (650*MSEC) /* 650ms */
-#define PD_T_NO_RESPONSE          (5500*MSEC) /* between 4.5s and 5.5s */
-#define PD_T_BIST_TRANSMIT          (50*MSEC) /* 50ms (for task_wait arg) */
-#define PD_T_BIST_RECEIVE           (60*MSEC) /* 60ms (time to process bist) */
-#define PD_T_BIST_CONT_MODE         (55*MSEC) /* 30ms to 60ms */
-#define PD_T_VCONN_SOURCE_ON       (100*MSEC) /* 100ms */
-#define PD_T_DRP_TRY               (125*MSEC) /* between 75ms and 150ms */
-#define PD_T_TRY_TIMEOUT           (550*MSEC) /* between 550ms and 1100ms */
-#define PD_T_TRY_WAIT              (600*MSEC) /* Wait time for TryWait.SNK */
-#define PD_T_SINK_REQUEST          (100*MSEC) /* 100ms before next request */
-#define PD_T_PD_DEBOUNCE            (15*MSEC) /* between 10ms and 20ms */
-#define PD_T_CHUNK_SENDER_RESPONSE  (25*MSEC) /* 25ms */
-#define PD_T_CHUNK_SENDER_REQUEST   (25*MSEC) /* 25ms */
-#define PD_T_SWAP_SOURCE_START      (25*MSEC) /* Min of 20ms */
-#define PD_T_RP_VALUE_CHANGE        (20*MSEC) /* 20ms */
-#define PD_T_SRC_DISCONNECT         (15*MSEC) /* 15ms */
-#define PD_T_SRC_TRANSITION         (25*MSEC) /* 25ms to 35 ms */
-#define PD_T_VCONN_STABLE           (50*MSEC) /* 50ms */
-#define PD_T_DISCOVER_IDENTITY      (45*MSEC) /* between 40ms and 50ms */
-#define PD_T_SYSJUMP              (1000*MSEC) /* 1s */
-#define PD_T_PR_SWAP_WAIT          (100*MSEC) /* tPRSwapWait 100ms */
-#define PD_T_DATA_RESET            (225*MSEC) /* between 200ms and 250ms */
-#define PD_T_DATA_RESET_FAIL       (300*MSEC) /* 300ms */
-#define PD_T_VCONN_REAPPLIED        (10*MSEC) /* between 10ms and 20ms */
-#define PD_T_VCONN_DISCHARGE       (240*MSEC) /* between 160ms and 240ms */
+#define PD_T_DRP_SNK (40 * MSEC) /* toggle time for sink DRP */
+#define PD_T_DRP_SRC (30 * MSEC) /* toggle time for source DRP */
+#define PD_T_DEBOUNCE (15 * MSEC) /* between 10ms and 20ms */
+#define PD_T_TRY_CC_DEBOUNCE (15 * MSEC) /* between 10ms and 20ms */
+#define PD_T_SINK_ADJ (55 * MSEC) /* between tPDDebounce and 60ms */
+#define PD_T_SRC_RECOVER (760 * MSEC) /* between 660ms and 1000ms */
+#define PD_T_SRC_RECOVER_MAX (1000 * MSEC) /* 1000ms */
+#define PD_T_SRC_TURN_ON (275 * MSEC) /* 275ms */
+#define PD_T_SAFE_0V (650 * MSEC) /* 650ms */
+#define PD_T_NO_RESPONSE (5500 * MSEC) /* between 4.5s and 5.5s */
+#define PD_T_BIST_TRANSMIT (50 * MSEC) /* 50ms (for task_wait arg) */
+#define PD_T_BIST_RECEIVE (60 * MSEC) /* 60ms (time to process bist) */
+#define PD_T_BIST_CONT_MODE (55 * MSEC) /* 30ms to 60ms */
+#define PD_T_VCONN_SOURCE_ON (100 * MSEC) /* 100ms */
+#define PD_T_DRP_TRY (125 * MSEC) /* between 75ms and 150ms */
+#define PD_T_TRY_TIMEOUT (550 * MSEC) /* between 550ms and 1100ms */
+#define PD_T_TRY_WAIT (600 * MSEC) /* Wait time for TryWait.SNK */
+#define PD_T_SINK_REQUEST (100 * MSEC) /* 100ms before next request */
+#define PD_T_PD_DEBOUNCE (15 * MSEC) /* between 10ms and 20ms */
+#define PD_T_CHUNK_SENDER_RESPONSE (25 * MSEC) /* 25ms */
+#define PD_T_CHUNK_SENDER_REQUEST (25 * MSEC) /* 25ms */
+#define PD_T_SWAP_SOURCE_START (25 * MSEC) /* Min of 20ms */
+#define PD_T_RP_VALUE_CHANGE (20 * MSEC) /* 20ms */
+#define PD_T_SRC_DISCONNECT (15 * MSEC) /* 15ms */
+#define PD_T_SRC_TRANSITION (25 * MSEC) /* 25ms to 35 ms */
+#define PD_T_VCONN_STABLE (50 * MSEC) /* 50ms */
+#define PD_T_DISCOVER_IDENTITY (45 * MSEC) /* between 40ms and 50ms */
+#define PD_T_SYSJUMP (1000 * MSEC) /* 1s */
+#define PD_T_PR_SWAP_WAIT (100 * MSEC) /* tPRSwapWait 100ms */
+#define PD_T_DATA_RESET (225 * MSEC) /* between 200ms and 250ms */
+#define PD_T_DATA_RESET_FAIL (300 * MSEC) /* 300ms */
+#define PD_T_VCONN_REAPPLIED (10 * MSEC) /* between 10ms and 20ms */
+#define PD_T_VCONN_DISCHARGE (240 * MSEC) /* between 160ms and 240ms */
 
 /*
  * Non-spec timer to prevent going Unattached if Vbus drops before a partner FRS
  * signal comes through.  This timer should be shorter than tSinkDisconnect
  * (40ms) to ensure we still transition out of Attached.SNK in time.
  */
-#define PD_T_FRS_VBUS_DEBOUNCE	     (5*MSEC)
+#define PD_T_FRS_VBUS_DEBOUNCE (5 * MSEC)
 
 /* number of edges and time window to detect CC line is not idle */
-#define PD_RX_TRANSITION_COUNT  3
+#define PD_RX_TRANSITION_COUNT 3
 #define PD_RX_TRANSITION_WINDOW 20 /* between 12us and 20us */
 
 /* from USB Type-C Specification Table 5-1 */
-#define PD_T_AME (1*SECOND) /* timeout from UFP attach to Alt Mode Entry */
+#define PD_T_AME (1 * SECOND) /* timeout from UFP attach to Alt Mode Entry */
 
 /* VDM Timers ( USB PD Spec Rev2.0 Table 6-30 )*/
-#define PD_T_VDM_BUSY           (50*MSEC) /* at least 50ms */
-#define PD_T_VDM_E_MODE         (25*MSEC) /* enter/exit the same max */
-#define PD_T_VDM_RCVR_RSP       (15*MSEC) /* max of 15ms */
-#define PD_T_VDM_SNDR_RSP       (30*MSEC) /* max of 30ms */
-#define PD_T_VDM_WAIT_MODE_E   (100*MSEC) /* enter/exit the same max */
+#define PD_T_VDM_BUSY (50 * MSEC) /* at least 50ms */
+#define PD_T_VDM_E_MODE (25 * MSEC) /* enter/exit the same max */
+#define PD_T_VDM_RCVR_RSP (15 * MSEC) /* max of 15ms */
+#define PD_T_VDM_SNDR_RSP (30 * MSEC) /* max of 30ms */
+#define PD_T_VDM_WAIT_MODE_E (100 * MSEC) /* enter/exit the same max */
 
 /* CTVPD Timers ( USB Type-C ECN Table 4-27 ) */
-#define PD_T_VPDDETACH        (20*MSEC) /* max of 20*MSEC */
-#define PD_T_VPDCTDD           (4*MSEC) /* max of 4ms */
-#define PD_T_VPDDISABLE       (25*MSEC) /* min of 25ms */
+#define PD_T_VPDDETACH (20 * MSEC) /* max of 20*MSEC */
+#define PD_T_VPDCTDD (4 * MSEC) /* max of 4ms */
+#define PD_T_VPDDISABLE (25 * MSEC) /* min of 25ms */
 
 /* Voltage thresholds in mV (Table 7-24, PD 3.0 Version 2.0 Spec) */
-#define PD_V_SAFE0V_MAX		800
-#define PD_V_SAFE5V_MIN		4750
-#define PD_V_SAFE5V_NOM		5000
-#define PD_V_SAFE5V_MAX		5500
+#define PD_V_SAFE0V_MAX 800
+#define PD_V_SAFE5V_MIN 4750
+#define PD_V_SAFE5V_NOM 5000
+#define PD_V_SAFE5V_MAX 5500
 
 /* USB Type-C voltages in mV (Table 4-3, USB Type-C Release 2.0 Spec) */
 #define PD_V_SINK_DISCONNECT_MAX 3670
 /* TODO(b/149530538): Add equation for vSinkDisconnectPD */
 
 /* Maximum voltage in mV offered by PD 3.0 Version 2.0 Spec */
-#define PD_REV3_MAX_VOLTAGE	20000
+#define PD_REV3_MAX_VOLTAGE 20000
 
 /* Power in mW at which we will automatically charge from a DRP partner */
-#define PD_DRP_CHARGE_POWER_MIN	27000
+#define PD_DRP_CHARGE_POWER_MIN 27000
 
 /* function table for entered mode */
 struct amode_fx {
@@ -325,9 +327,9 @@ struct svdm_response {
  * value after resetting connection information via memset.
  */
 enum pd_discovery_state {
-	PD_DISC_NEEDED = 0,	/* Cable or partner still needs to be probed */
-	PD_DISC_COMPLETE,	/* Successfully probed, valid to read VDO */
-	PD_DISC_FAIL,		/* Cable did not respond, or Discover* NAK */
+	PD_DISC_NEEDED = 0, /* Cable or partner still needs to be probed */
+	PD_DISC_COMPLETE, /* Successfully probed, valid to read VDO */
+	PD_DISC_FAIL, /* Cable did not respond, or Discover* NAK */
 };
 
 /* Mode discovery state for a particular SVID with a particular transmit type */
@@ -391,8 +393,8 @@ enum hpd_event {
 };
 
 /* DisplayPort flags */
-#define DP_FLAGS_DP_ON              BIT(0) /* Display port mode is on */
-#define DP_FLAGS_HPD_HI_PENDING     BIT(1) /* Pending HPD_HI */
+#define DP_FLAGS_DP_ON BIT(0) /* Display port mode is on */
+#define DP_FLAGS_HPD_HI_PENDING BIT(1) /* Pending HPD_HI */
 
 /* Discover Identity ACK contents after headers */
 union disc_ident_ack {
@@ -408,7 +410,7 @@ union disc_ident_ack {
 	uint32_t raw_value[PDO_MAX_OBJECTS - 1];
 };
 BUILD_ASSERT(sizeof(union disc_ident_ack) ==
-				sizeof(uint32_t) * (PDO_MAX_OBJECTS - 1));
+	     sizeof(uint32_t) * (PDO_MAX_OBJECTS - 1));
 
 /* Discover Identity data - ACK plus discovery state */
 struct identity_data {
@@ -428,10 +430,10 @@ enum pd_alternate_modes {
 /* Discover and possibly enter modes for all SOP* communications when enabled */
 #ifdef CONFIG_USB_PD_DECODE_SOP
 #define DISCOVERY_TYPE_COUNT (TCPCI_MSG_SOP_PRIME + 1)
-#define AMODE_TYPE_COUNT     (TCPCI_MSG_SOP_PRIME_PRIME + 1)
+#define AMODE_TYPE_COUNT (TCPCI_MSG_SOP_PRIME_PRIME + 1)
 #else
 #define DISCOVERY_TYPE_COUNT (TCPCI_MSG_SOP + 1)
-#define AMODE_TYPE_COUNT     (TCPCI_MSG_SOP + 1)
+#define AMODE_TYPE_COUNT (TCPCI_MSG_SOP + 1)
 #endif
 
 /* Discovery results for a port partner (SOP) or cable plug (SOP') */
@@ -485,56 +487,53 @@ struct partner_active_modes {
  * <4:0>    :: command
  */
 #define VDO(vid, type, custom) \
-	(((vid) << 16) |       \
-	((type) << 15) |       \
-	((custom) & 0x7FFF))
-
-#define VDO_SVDM_TYPE     BIT(15)
-#define VDO_SVDM_VERS(x)  (x << 13)
-#define VDO_OPOS(x)       (x << 8)
-#define VDO_CMDT(x)       (x << 6)
-#define VDO_OPOS_MASK     VDO_OPOS(0x7)
-#define VDO_CMDT_MASK     VDO_CMDT(0x3)
-
-#define CMDT_INIT     0
-#define CMDT_RSP_ACK  1
-#define CMDT_RSP_NAK  2
+	(((vid) << 16) | ((type) << 15) | ((custom)&0x7FFF))
+
+#define VDO_SVDM_TYPE BIT(15)
+#define VDO_SVDM_VERS(x) (x << 13)
+#define VDO_OPOS(x) (x << 8)
+#define VDO_CMDT(x) (x << 6)
+#define VDO_OPOS_MASK VDO_OPOS(0x7)
+#define VDO_CMDT_MASK VDO_CMDT(0x3)
+
+#define CMDT_INIT 0
+#define CMDT_RSP_ACK 1
+#define CMDT_RSP_NAK 2
 #define CMDT_RSP_BUSY 3
 
-
 /* reserved for SVDM ... for Google UVDM */
 #define VDO_SRC_INITIATOR (0 << 5)
 #define VDO_SRC_RESPONDER BIT(5)
 
-#define CMD_DISCOVER_IDENT  1
-#define CMD_DISCOVER_SVID   2
-#define CMD_DISCOVER_MODES  3
-#define CMD_ENTER_MODE      4
-#define CMD_EXIT_MODE       5
-#define CMD_ATTENTION       6
-#define CMD_DP_STATUS      16
-#define CMD_DP_CONFIG      17
+#define CMD_DISCOVER_IDENT 1
+#define CMD_DISCOVER_SVID 2
+#define CMD_DISCOVER_MODES 3
+#define CMD_ENTER_MODE 4
+#define CMD_EXIT_MODE 5
+#define CMD_ATTENTION 6
+#define CMD_DP_STATUS 16
+#define CMD_DP_CONFIG 17
 
-#define VDO_CMD_VENDOR(x)    (((10 + (x)) & 0x1f))
+#define VDO_CMD_VENDOR(x) (((10 + (x)) & 0x1f))
 
 /* ChromeOS specific commands */
-#define VDO_CMD_VERSION      VDO_CMD_VENDOR(0)
-#define VDO_CMD_SEND_INFO    VDO_CMD_VENDOR(1)
-#define VDO_CMD_READ_INFO    VDO_CMD_VENDOR(2)
-#define VDO_CMD_REBOOT       VDO_CMD_VENDOR(5)
-#define VDO_CMD_FLASH_ERASE  VDO_CMD_VENDOR(6)
-#define VDO_CMD_FLASH_WRITE  VDO_CMD_VENDOR(7)
-#define VDO_CMD_ERASE_SIG    VDO_CMD_VENDOR(8)
-#define VDO_CMD_PING_ENABLE  VDO_CMD_VENDOR(10)
-#define VDO_CMD_CURRENT      VDO_CMD_VENDOR(11)
-#define VDO_CMD_FLIP         VDO_CMD_VENDOR(12)
-#define VDO_CMD_GET_LOG      VDO_CMD_VENDOR(13)
-#define VDO_CMD_CCD_EN       VDO_CMD_VENDOR(14)
-
-#define PD_VDO_VID(vdo)  ((vdo) >> 16)
+#define VDO_CMD_VERSION VDO_CMD_VENDOR(0)
+#define VDO_CMD_SEND_INFO VDO_CMD_VENDOR(1)
+#define VDO_CMD_READ_INFO VDO_CMD_VENDOR(2)
+#define VDO_CMD_REBOOT VDO_CMD_VENDOR(5)
+#define VDO_CMD_FLASH_ERASE VDO_CMD_VENDOR(6)
+#define VDO_CMD_FLASH_WRITE VDO_CMD_VENDOR(7)
+#define VDO_CMD_ERASE_SIG VDO_CMD_VENDOR(8)
+#define VDO_CMD_PING_ENABLE VDO_CMD_VENDOR(10)
+#define VDO_CMD_CURRENT VDO_CMD_VENDOR(11)
+#define VDO_CMD_FLIP VDO_CMD_VENDOR(12)
+#define VDO_CMD_GET_LOG VDO_CMD_VENDOR(13)
+#define VDO_CMD_CCD_EN VDO_CMD_VENDOR(14)
+
+#define PD_VDO_VID(vdo) ((vdo) >> 16)
 #define PD_VDO_SVDM(vdo) (((vdo) >> 15) & 1)
 #define PD_VDO_OPOS(vdo) (((vdo) >> 8) & 0x7)
-#define PD_VDO_CMD(vdo)  ((vdo) & 0x1f)
+#define PD_VDO_CMD(vdo) ((vdo)&0x1f)
 #define PD_VDO_CMDT(vdo) (((vdo) >> 6) & 0x3)
 
 /*
@@ -556,51 +555,51 @@ struct partner_active_modes {
  * [6] :: Product type DFP VDO
  *
  */
-#define VDO_INDEX_HDR            0
-#define VDO_INDEX_IDH            1
-#define VDO_INDEX_CSTAT          2
-#define VDO_INDEX_CABLE          3
-#define VDO_INDEX_PRODUCT        3
-#define VDO_INDEX_AMA            4
+#define VDO_INDEX_HDR 0
+#define VDO_INDEX_IDH 1
+#define VDO_INDEX_CSTAT 2
+#define VDO_INDEX_CABLE 3
+#define VDO_INDEX_PRODUCT 3
+#define VDO_INDEX_AMA 4
 #define VDO_INDEX_PTYPE_UFP1_VDO 4
-#define VDO_INDEX_PTYPE_CABLE1   4
+#define VDO_INDEX_PTYPE_CABLE1 4
 #define VDO_INDEX_PTYPE_UFP2_VDO 5
-#define VDO_INDEX_PTYPE_CABLE2   5
-#define VDO_INDEX_PTYPE_DFP_VDO  6
+#define VDO_INDEX_PTYPE_CABLE2 5
+#define VDO_INDEX_PTYPE_DFP_VDO 6
 #define VDO_I(name) VDO_INDEX_##name
 
 /* PD Rev 2.0 ID Header VDO */
-#define VDO_IDH(usbh, usbd, ptype, is_modal, vid)		\
-	((usbh) << 31 | (usbd) << 30 | ((ptype) & 0x7) << 27	\
-	 | (is_modal) << 26 | ((vid) & 0xffff))
+#define VDO_IDH(usbh, usbd, ptype, is_modal, vid)            \
+	((usbh) << 31 | (usbd) << 30 | ((ptype)&0x7) << 27 | \
+	 (is_modal) << 26 | ((vid)&0xffff))
 
 /* PD Rev 3.0 ID Header VDO */
-#define VDO_IDH_REV30(usbh, usbd, ptype_u, is_modal, ptype_d, ctype, vid) \
-	(VDO_IDH(usbh, usbd, ptype_u, is_modal, vid)			\
-	| ((ptype_d) & 0x7) << 23 | ((ctype) & 0x3) << 21)
+#define VDO_IDH_REV30(usbh, usbd, ptype_u, is_modal, ptype_d, ctype, vid)      \
+	(VDO_IDH(usbh, usbd, ptype_u, is_modal, vid) | ((ptype_d)&0x7) << 23 | \
+	 ((ctype)&0x3) << 21)
 
-#define PD_IDH_PTYPE(vdo)    (((vdo) >> 27) & 0x7)
+#define PD_IDH_PTYPE(vdo) (((vdo) >> 27) & 0x7)
 #define PD_IDH_IS_MODAL(vdo) (((vdo) >> 26) & 0x1)
-#define PD_IDH_VID(vdo)      ((vdo) & 0xffff)
+#define PD_IDH_VID(vdo) ((vdo)&0xffff)
 
-#define VDO_CSTAT(tid)    ((tid) & 0xfffff)
-#define PD_CSTAT_TID(vdo) ((vdo) & 0xfffff)
+#define VDO_CSTAT(tid) ((tid)&0xfffff)
+#define PD_CSTAT_TID(vdo) ((vdo)&0xfffff)
 
-#define VDO_PRODUCT(pid, bcd) (((pid) & 0xffff) << 16 | ((bcd) & 0xffff))
+#define VDO_PRODUCT(pid, bcd) (((pid)&0xffff) << 16 | ((bcd)&0xffff))
 #define PD_PRODUCT_PID(vdo) (((vdo) >> 16) & 0xffff)
 
-/*
- * PD Rev 3.1 Revision Message Data Object (RMDO)
- * Only bits 16-31 have data. A uint_16t is used to hold RMDOs upper 16 bits.
- */
+/* PD Rev 3.1 Revision Message Data Object (RMDO) */
 struct rmdo {
-	int reserved : 16;
-	int minor_ver : 4;
-	int major_ver : 4;
-	int minor_rev : 4;
-	int major_rev : 4;
+	uint32_t reserved : 16;
+	uint32_t minor_ver : 4;
+	uint32_t major_ver : 4;
+	uint32_t minor_rev : 4;
+	uint32_t major_rev : 4;
 };
 
+/* Confirm RMDO is 32 bits. */
+BUILD_ASSERT(sizeof(struct rmdo) == 4);
+
 /*
  * Message id starts from 0 to 7. If last_msg_id is initialized to 0,
  * it will lead to repetitive message id with first received packet,
@@ -622,9 +621,9 @@ enum pd_rev_type {
 };
 
 #ifdef CONFIG_USB_PD_REV30
-#define PD_REVISION     PD_REV30
+#define PD_REVISION PD_REV30
 #else
-#define PD_REVISION     PD_REV20
+#define PD_REVISION PD_REV20
 #endif
 
 #if defined(CONFIG_USB_PD_TCPMV1)
@@ -649,18 +648,17 @@ struct pd_cable {
 
 	/* Cable revision */
 	enum pd_rev_type rev;
-
 };
 
 /* Note: These flags are only used for TCPMv1 */
 /* Check if Thunderbolt-compatible mode enabled */
-#define CABLE_FLAGS_TBT_COMPAT_ENABLE	   BIT(0)
+#define CABLE_FLAGS_TBT_COMPAT_ENABLE BIT(0)
 /* Flag to limit speed to TBT Gen 2 passive cable */
 #define CABLE_FLAGS_TBT_COMPAT_LIMIT_SPEED BIT(1)
 /* Flag for checking if device is USB4.0 capable */
-#define CABLE_FLAGS_USB4_CAPABLE           BIT(2)
+#define CABLE_FLAGS_USB4_CAPABLE BIT(2)
 /* Flag for entering ENTER_USB mode */
-#define CABLE_FLAGS_ENTER_USB_MODE         BIT(3)
+#define CABLE_FLAGS_ENTER_USB_MODE BIT(3)
 
 /*
  * SVDM Discover SVIDs request -> response
@@ -670,9 +668,9 @@ struct pd_cable {
  * mark the end of SVIDs.  If more than 12 SVIDs are supported command SHOULD be
  * repeated.
  */
-#define VDO_SVID(svid0, svid1) (((svid0) & 0xffff) << 16 | ((svid1) & 0xffff))
+#define VDO_SVID(svid0, svid1) (((svid0)&0xffff) << 16 | ((svid1)&0xffff))
 #define PD_VDO_SVID_SVID0(vdo) ((vdo) >> 16)
-#define PD_VDO_SVID_SVID1(vdo) ((vdo) & 0xffff)
+#define PD_VDO_SVID_SVID1(vdo) ((vdo)&0xffff)
 
 /*
  * Google modes capabilities
@@ -702,10 +700,9 @@ struct pd_cable {
  *           Other bits are reserved.
  * <1:0>   : signal direction ( 00b=rsv, 01b=sink, 10b=src 11b=both )
  */
-#define VDO_MODE_DP(snkp, srcp, usb, gdr, sign, sdir)			\
-	(((snkp) & 0xff) << 16 | ((srcp) & 0xff) << 8			\
-	 | ((usb) & 1) << 7 | ((gdr) & 1) << 6 | ((sign) & 0xF) << 2	\
-	 | ((sdir) & 0x3))
+#define VDO_MODE_DP(snkp, srcp, usb, gdr, sign, sdir)                \
+	(((snkp)&0xff) << 16 | ((srcp)&0xff) << 8 | ((usb)&1) << 7 | \
+	 ((gdr)&1) << 6 | ((sign)&0xF) << 2 | ((sdir)&0x3))
 
 #define MODE_DP_DFP_PIN_SHIFT 8
 #define MODE_DP_UFP_PIN_SHIFT 16
@@ -719,11 +716,11 @@ struct pd_cable {
 /* Pin configs A/B/C/D/E/F */
 #define MODE_DP_PIN_CAPS_MASK 0x3f
 
-#define MODE_DP_V13  0x1
+#define MODE_DP_V13 0x1
 #define MODE_DP_GEN2 0x2
 
-#define MODE_DP_SNK  0x1
-#define MODE_DP_SRC  0x2
+#define MODE_DP_SNK 0x1
+#define MODE_DP_SRC 0x2
 #define MODE_DP_BOTH 0x3
 
 #define MODE_DP_CABLE_SHIFT 6
@@ -740,9 +737,10 @@ struct pd_cable {
  * or UFP_D (if receptacle==1)
  * Also refer to DisplayPort Alt Mode Capabilities Clarification (4/30/2015)
  */
-#define PD_DP_PIN_CAPS(x) ((((x) >> MODE_DP_CABLE_SHIFT) & 0x1) \
-	? (((x) >> MODE_DP_UFP_PIN_SHIFT) & MODE_DP_PIN_CAPS_MASK) \
-	: (((x) >> MODE_DP_DFP_PIN_SHIFT) & MODE_DP_PIN_CAPS_MASK))
+#define PD_DP_PIN_CAPS(x)                                                   \
+	((((x) >> MODE_DP_CABLE_SHIFT) & 0x1) ?                             \
+		 (((x) >> MODE_DP_UFP_PIN_SHIFT) & MODE_DP_PIN_CAPS_MASK) : \
+		 (((x) >> MODE_DP_DFP_PIN_SHIFT) & MODE_DP_PIN_CAPS_MASK))
 
 /*
  * DisplayPort Status VDO
@@ -758,10 +756,10 @@ struct pd_cable {
  * <1:0>  : connect status : 00b ==  no (DFP|UFP)_D is connected or disabled.
  *          01b == DFP_D connected, 10b == UFP_D connected, 11b == both.
  */
-#define VDO_DP_STATUS(irq, lvl, amode, usbc, mf, en, lp, conn)		\
-	(((irq) & 1) << 8 | ((lvl) & 1) << 7 | ((amode) & 1) << 6	\
-	 | ((usbc) & 1) << 5 | ((mf) & 1) << 4 | ((en) & 1) << 3	\
-	 | ((lp) & 1) << 2 | ((conn & 0x3) << 0))
+#define VDO_DP_STATUS(irq, lvl, amode, usbc, mf, en, lp, conn)             \
+	(((irq)&1) << 8 | ((lvl)&1) << 7 | ((amode)&1) << 6 |              \
+	 ((usbc)&1) << 5 | ((mf)&1) << 4 | ((en)&1) << 3 | ((lp)&1) << 2 | \
+	 ((conn & 0x3) << 0))
 
 #define PD_VDO_DPSTS_MF_MASK BIT(4)
 
@@ -770,9 +768,9 @@ struct pd_cable {
 #define PD_VDO_DPSTS_MF_PREF(x) (((x) >> 4) & 1)
 
 /* Per DisplayPort Spec v1.3 Section 3.3 */
-#define HPD_USTREAM_DEBOUNCE_LVL (2*MSEC)
+#define HPD_USTREAM_DEBOUNCE_LVL (2 * MSEC)
 #define HPD_USTREAM_DEBOUNCE_IRQ (250)
-#define HPD_DSTREAM_DEBOUNCE_IRQ (500)  /* between 500-1000us */
+#define HPD_DSTREAM_DEBOUNCE_IRQ (500) /* between 500-1000us */
 
 /*
  * DisplayPort Configure VDO
@@ -786,7 +784,7 @@ struct pd_cable {
  * <1:0>   : cfg : 00 == USB, 01 == DFP_D, 10 == UFP_D, 11 == reserved
  */
 #define VDO_DP_CFG(pin, sig, cfg) \
-	(((pin) & 0xff) << 8 | ((sig) & 0xf) << 2 | ((cfg) & 0x3))
+	(((pin)&0xff) << 8 | ((sig)&0xf) << 2 | ((cfg)&0x3))
 
 #define PD_DP_CFG_DPON(x) (((x & 0x3) == 1) || ((x & 0x3) == 2))
 /*
@@ -794,18 +792,18 @@ struct pd_cable {
  * for backward compatibility, if it is null,
  * get the former sink pin assignment we used to be in <23:16>.
  */
-#define PD_DP_CFG_PIN(x) ((((x) >> 8) & 0xff) ? (((x) >> 8) & 0xff) \
-					      : (((x) >> 16) & 0xff))
+#define PD_DP_CFG_PIN(x) \
+	((((x) >> 8) & 0xff) ? (((x) >> 8) & 0xff) : (((x) >> 16) & 0xff))
 /*
  * ChromeOS specific PD device Hardware IDs. Used to identify unique
  * products and used in VDO_INFO. Note this field is 10 bits.
  */
-#define USB_PD_HW_DEV_ID_RESERVED    0
-#define USB_PD_HW_DEV_ID_ZINGER      1
-#define USB_PD_HW_DEV_ID_MINIMUFFIN  2
-#define USB_PD_HW_DEV_ID_DINGDONG    3
-#define USB_PD_HW_DEV_ID_HOHO        4
-#define USB_PD_HW_DEV_ID_HONEYBUNS   5
+#define USB_PD_HW_DEV_ID_RESERVED 0
+#define USB_PD_HW_DEV_ID_ZINGER 1
+#define USB_PD_HW_DEV_ID_MINIMUFFIN 2
+#define USB_PD_HW_DEV_ID_DINGDONG 3
+#define USB_PD_HW_DEV_ID_HOHO 4
+#define USB_PD_HW_DEV_ID_HONEYBUNS 5
 
 /*
  * ChromeOS specific VDO_CMD_READ_INFO responds with device info including:
@@ -815,86 +813,87 @@ struct pd_cable {
  * SW Debug Version: Software version useful for debugging (15 bits)
  * IS RW: True if currently in RW, False otherwise (1 bit)
  */
-#define VDO_INFO(id, id_minor, ver, is_rw) ((id_minor) << 26 \
-				  | ((id) & 0x3ff) << 16 \
-				  | ((ver) & 0x7fff) << 1 \
-				  | ((is_rw) & 1))
-#define VDO_INFO_HW_DEV_ID(x)    ((x) >> 16)
-#define VDO_INFO_SW_DBG_VER(x)   (((x) >> 1) & 0x7fff)
-#define VDO_INFO_IS_RW(x)        ((x) & 1)
+#define VDO_INFO(id, id_minor, ver, is_rw)                             \
+	((id_minor) << 26 | ((id)&0x3ff) << 16 | ((ver)&0x7fff) << 1 | \
+	 ((is_rw)&1))
+#define VDO_INFO_HW_DEV_ID(x) ((x) >> 16)
+#define VDO_INFO_SW_DBG_VER(x) (((x) >> 1) & 0x7fff)
+#define VDO_INFO_IS_RW(x) ((x)&1)
 
 #define HW_DEV_ID_MAJ(x) (x & 0x3ff)
 #define HW_DEV_ID_MIN(x) ((x) >> 10)
 
 /* USB-IF SIDs */
-#define USB_SID_PD          0xff00 /* power delivery */
+#define USB_SID_PD 0xff00 /* power delivery */
 #define USB_SID_DISPLAYPORT 0xff01
 
 #define USB_GOOGLE_TYPEC_URL "http://www.google.com/chrome/devices/typec"
-/* USB Vendor ID assigned to Google Inc. */
+/* USB Vendor ID assigned to Google LLC */
 #define USB_VID_GOOGLE 0x18d1
 
 /* Other Vendor IDs */
-#define USB_VID_APPLE  0x05ac
+#define USB_VID_APPLE 0x05ac
 #define USB_PID1_APPLE 0x1012
 #define USB_PID2_APPLE 0x1013
 
-#define USB_VID_HP     0x03F0
-#define USB_PID_HP_USB_C_DOCK_G5	0x036B
-#define USB_PID_HP_USB_C_A_UNIV_DOCK_G2	0x096B
-#define USB_PID_HP_E24D_DOCK_MONITOR	0x0467
-#define USB_PID_HP_ELITE_E233_MONITOR	0x1747
-#define USB_PID_HP_E244D_DOCK_MONITOR	0x056D
-#define USB_PID_HP_E274D_DOCK_MONITOR	0x016E
+#define USB_VID_HP 0x03F0
+#define USB_PID_HP_USB_C_DOCK_G5 0x036B
+#define USB_PID_HP_USB_C_A_UNIV_DOCK_G2 0x096B
+#define USB_PID_HP_E24D_DOCK_MONITOR 0x0467
+#define USB_PID_HP_ELITE_E233_MONITOR 0x1747
+#define USB_PID_HP_E244D_DOCK_MONITOR 0x056D
+#define USB_PID_HP_E274D_DOCK_MONITOR 0x016E
 
-#define USB_VID_INTEL  0x8087
+#define USB_VID_INTEL 0x8087
 
 /* Timeout for message receive in microseconds */
 #define USB_PD_RX_TMOUT_US 1800
 
+/* Power button press length triggered by USB PD short button press */
+#define USB_PD_SHORT_BUTTON_PRESS_MS 500
+
 /* --- Protocol layer functions --- */
 
 enum pd_states {
-	PD_STATE_DISABLED,			/* C0  */
-	PD_STATE_SUSPENDED,			/* C1  */
-	PD_STATE_SNK_DISCONNECTED,		/* C2  */
-	PD_STATE_SNK_DISCONNECTED_DEBOUNCE,	/* C3  */
-	PD_STATE_SNK_HARD_RESET_RECOVER,	/* C4  */
-	PD_STATE_SNK_DISCOVERY,			/* C5  */
-	PD_STATE_SNK_REQUESTED,			/* C6  */
-	PD_STATE_SNK_TRANSITION,		/* C7  */
-	PD_STATE_SNK_READY,			/* C8  */
-	PD_STATE_SNK_SWAP_INIT,			/* C9  */
-	PD_STATE_SNK_SWAP_SNK_DISABLE,		/* C10 */
-	PD_STATE_SNK_SWAP_SRC_DISABLE,		/* C11 */
-	PD_STATE_SNK_SWAP_STANDBY,		/* C12 */
-	PD_STATE_SNK_SWAP_COMPLETE,		/* C13 */
-	PD_STATE_SRC_DISCONNECTED,		/* C14 */
-	PD_STATE_SRC_DISCONNECTED_DEBOUNCE,	/* C15 */
-	PD_STATE_SRC_HARD_RESET_RECOVER,	/* C16 */
-	PD_STATE_SRC_STARTUP,			/* C17 */
-	PD_STATE_SRC_DISCOVERY,			/* C18 */
-	PD_STATE_SRC_NEGOCIATE,			/* C19 */
-	PD_STATE_SRC_ACCEPTED,			/* C20 */
-	PD_STATE_SRC_POWERED,			/* C21 */
-	PD_STATE_SRC_TRANSITION,		/* C22 */
-	PD_STATE_SRC_READY,			/* C23 */
-	PD_STATE_SRC_GET_SINK_CAP,		/* C24 */
-	PD_STATE_DR_SWAP,			/* C25 */
-	PD_STATE_SRC_SWAP_INIT,			/* C26 */
-	PD_STATE_SRC_SWAP_SNK_DISABLE,		/* C27 */
-	PD_STATE_SRC_SWAP_SRC_DISABLE,		/* C28 */
-	PD_STATE_SRC_SWAP_STANDBY,		/* C29 */
-	PD_STATE_VCONN_SWAP_SEND,		/* C30 */
-	PD_STATE_VCONN_SWAP_INIT,		/* C31 */
-	PD_STATE_VCONN_SWAP_READY,		/* C32 */
-	PD_STATE_SOFT_RESET,			/* C33 */
-	PD_STATE_HARD_RESET_SEND,		/* C34 */
-	PD_STATE_HARD_RESET_EXECUTE,		/* C35 */
-	PD_STATE_BIST_RX,			/* C36 */
-	PD_STATE_BIST_TX,			/* C37 */
-	PD_STATE_DRP_AUTO_TOGGLE,		/* C38 */
-	PD_STATE_ENTER_USB,			/* C39 */
+	PD_STATE_DISABLED, /* C0  */
+	PD_STATE_SUSPENDED, /* C1  */
+	PD_STATE_SNK_DISCONNECTED, /* C2  */
+	PD_STATE_SNK_DISCONNECTED_DEBOUNCE, /* C3  */
+	PD_STATE_SNK_HARD_RESET_RECOVER, /* C4  */
+	PD_STATE_SNK_DISCOVERY, /* C5  */
+	PD_STATE_SNK_REQUESTED, /* C6  */
+	PD_STATE_SNK_TRANSITION, /* C7  */
+	PD_STATE_SNK_READY, /* C8  */
+	PD_STATE_SNK_SWAP_INIT, /* C9  */
+	PD_STATE_SNK_SWAP_SNK_DISABLE, /* C10 */
+	PD_STATE_SNK_SWAP_SRC_DISABLE, /* C11 */
+	PD_STATE_SNK_SWAP_STANDBY, /* C12 */
+	PD_STATE_SNK_SWAP_COMPLETE, /* C13 */
+	PD_STATE_SRC_DISCONNECTED, /* C14 */
+	PD_STATE_SRC_DISCONNECTED_DEBOUNCE, /* C15 */
+	PD_STATE_SRC_HARD_RESET_RECOVER, /* C16 */
+	PD_STATE_SRC_STARTUP, /* C17 */
+	PD_STATE_SRC_DISCOVERY, /* C18 */
+	PD_STATE_SRC_NEGOCIATE, /* C19 */
+	PD_STATE_SRC_ACCEPTED, /* C20 */
+	PD_STATE_SRC_POWERED, /* C21 */
+	PD_STATE_SRC_TRANSITION, /* C22 */
+	PD_STATE_SRC_READY, /* C23 */
+	PD_STATE_SRC_GET_SINK_CAP, /* C24 */
+	PD_STATE_DR_SWAP, /* C25 */
+	PD_STATE_SRC_SWAP_INIT, /* C26 */
+	PD_STATE_SRC_SWAP_SNK_DISABLE, /* C27 */
+	PD_STATE_SRC_SWAP_SRC_DISABLE, /* C28 */
+	PD_STATE_SRC_SWAP_STANDBY, /* C29 */
+	PD_STATE_VCONN_SWAP_SEND, /* C30 */
+	PD_STATE_VCONN_SWAP_INIT, /* C31 */
+	PD_STATE_VCONN_SWAP_READY, /* C32 */
+	PD_STATE_SOFT_RESET, /* C33 */
+	PD_STATE_HARD_RESET_SEND, /* C34 */
+	PD_STATE_HARD_RESET_EXECUTE, /* C35 */
+	PD_STATE_BIST_RX, /* C36 */
+	PD_STATE_BIST_TX, /* C37 */
+	PD_STATE_DRP_AUTO_TOGGLE, /* C38 */
 	/* Number of states. Not an actual state. */
 	PD_STATE_COUNT,
 };
@@ -939,23 +938,23 @@ enum pd_states {
 
 #ifdef CONFIG_USB_PD_TCPMV1
 /* Flags used for TCPMv1 */
-#define PD_FLAGS_PING_ENABLED      BIT(0) /* SRC_READY pings enabled */
-#define PD_FLAGS_PARTNER_DR_POWER  BIT(1) /* port partner is dualrole power */
-#define PD_FLAGS_PARTNER_DR_DATA   BIT(2) /* port partner is dualrole data */
-#define PD_FLAGS_CHECK_IDENTITY    BIT(3) /* discover identity in READY */
-#define PD_FLAGS_SNK_CAP_RECVD     BIT(4) /* sink capabilities received */
-#define PD_FLAGS_TCPC_DRP_TOGGLE   BIT(5) /* TCPC-controlled DRP toggling */
+#define PD_FLAGS_PING_ENABLED BIT(0) /* SRC_READY pings enabled */
+#define PD_FLAGS_PARTNER_DR_POWER BIT(1) /* port partner is dualrole power */
+#define PD_FLAGS_PARTNER_DR_DATA BIT(2) /* port partner is dualrole data */
+#define PD_FLAGS_CHECK_IDENTITY BIT(3) /* discover identity in READY */
+#define PD_FLAGS_SNK_CAP_RECVD BIT(4) /* sink capabilities received */
+#define PD_FLAGS_TCPC_DRP_TOGGLE BIT(5) /* TCPC-controlled DRP toggling */
 #define PD_FLAGS_EXPLICIT_CONTRACT BIT(6) /* explicit pwr contract in place */
-#define PD_FLAGS_VBUS_NEVER_LOW    BIT(7) /* VBUS input has never been low */
-#define PD_FLAGS_PREVIOUS_PD_CONN  BIT(8) /* previously PD connected */
-#define PD_FLAGS_CHECK_PR_ROLE     BIT(9) /* check power role in READY */
-#define PD_FLAGS_CHECK_DR_ROLE     BIT(10)/* check data role in READY */
-#define PD_FLAGS_PARTNER_UNCONSTR  BIT(11)/* port partner unconstrained pwr */
-#define PD_FLAGS_VCONN_ON          BIT(12)/* vconn is being sourced */
-#define PD_FLAGS_TRY_SRC           BIT(13)/* Try.SRC states are active */
-#define PD_FLAGS_PARTNER_USB_COMM  BIT(14)/* port partner is USB comms */
-#define PD_FLAGS_UPDATE_SRC_CAPS   BIT(15)/* send new source capabilities */
-#define PD_FLAGS_TS_DTS_PARTNER    BIT(16)/* partner has rp/rp or rd/rd */
+#define PD_FLAGS_VBUS_NEVER_LOW BIT(7) /* VBUS input has never been low */
+#define PD_FLAGS_PREVIOUS_PD_CONN BIT(8) /* previously PD connected */
+#define PD_FLAGS_CHECK_PR_ROLE BIT(9) /* check power role in READY */
+#define PD_FLAGS_CHECK_DR_ROLE BIT(10) /* check data role in READY */
+#define PD_FLAGS_PARTNER_UNCONSTR BIT(11) /* port partner unconstrained pwr */
+#define PD_FLAGS_VCONN_ON BIT(12) /* vconn is being sourced */
+#define PD_FLAGS_TRY_SRC BIT(13) /* Try.SRC states are active */
+#define PD_FLAGS_PARTNER_USB_COMM BIT(14) /* port partner is USB comms */
+#define PD_FLAGS_UPDATE_SRC_CAPS BIT(15) /* send new source capabilities */
+#define PD_FLAGS_TS_DTS_PARTNER BIT(16) /* partner has rp/rp or rd/rd */
 /*
  * These PD_FLAGS_LPM* flags track the software state (PD_LPM_FLAGS_REQUESTED)
  * and hardware state (PD_LPM_FLAGS_ENGAGED) of the TCPC low power mode.
@@ -963,26 +962,26 @@ enum pd_states {
  * low power (when PD_LPM_FLAGS_ENGAGED is changing).
  */
 #ifdef CONFIG_USB_PD_TCPC_LOW_POWER
-#define PD_FLAGS_LPM_REQUESTED     BIT(17)/* Tracks SW LPM state */
-#define PD_FLAGS_LPM_ENGAGED       BIT(18)/* Tracks HW LPM state */
-#define PD_FLAGS_LPM_TRANSITION    BIT(19)/* Tracks HW LPM transition */
-#define PD_FLAGS_LPM_EXIT          BIT(19)/* Tracks HW LPM exit */
+#define PD_FLAGS_LPM_REQUESTED BIT(17) /* Tracks SW LPM state */
+#define PD_FLAGS_LPM_ENGAGED BIT(18) /* Tracks HW LPM state */
+#define PD_FLAGS_LPM_TRANSITION BIT(19) /* Tracks HW LPM transition */
+#define PD_FLAGS_LPM_EXIT BIT(19) /* Tracks HW LPM exit */
 #endif
 /*
  * Tracks whether port negotiation may have stalled due to not starting reset
  * timers in SNK_DISCOVERY
  */
-#define PD_FLAGS_SNK_WAITING_BATT  BIT(21)
+#define PD_FLAGS_SNK_WAITING_BATT BIT(21)
 /* Check vconn state in READY */
 #define PD_FLAGS_CHECK_VCONN_STATE BIT(22)
 #endif /* CONFIG_USB_PD_TCPMV1 */
 
 /* Per-port battery backed RAM flags */
 #define PD_BBRMFLG_EXPLICIT_CONTRACT BIT(0)
-#define PD_BBRMFLG_POWER_ROLE        BIT(1)
-#define PD_BBRMFLG_DATA_ROLE         BIT(2)
-#define PD_BBRMFLG_VCONN_ROLE        BIT(3)
-#define PD_BBRMFLG_DBGACC_ROLE       BIT(4)
+#define PD_BBRMFLG_POWER_ROLE BIT(1)
+#define PD_BBRMFLG_DATA_ROLE BIT(2)
+#define PD_BBRMFLG_VCONN_ROLE BIT(3)
+#define PD_BBRMFLG_DBGACC_ROLE BIT(4)
 
 /* Initial value for CC debounce variable */
 #define PD_CC_UNSET -1
@@ -1005,31 +1004,31 @@ enum pd_dual_role_states {
  * NOTE: These are usually set by host commands from the AP.
  */
 enum pd_dpm_request {
-	DPM_REQUEST_DR_SWAP                     = BIT(0),
-	DPM_REQUEST_PR_SWAP                     = BIT(1),
-	DPM_REQUEST_VCONN_SWAP                  = BIT(2),
-	DPM_REQUEST_GOTO_MIN                    = BIT(3),
-	DPM_REQUEST_SRC_CAP_CHANGE              = BIT(4),
-	DPM_REQUEST_GET_SNK_CAPS                = BIT(5),
-	DPM_REQUEST_SEND_PING                   = BIT(6),
-	DPM_REQUEST_SOURCE_CAP                  = BIT(7),
-	DPM_REQUEST_NEW_POWER_LEVEL             = BIT(8),
-	DPM_REQUEST_VDM                         = BIT(9),
-	DPM_REQUEST_BIST_TX                     = BIT(10),
-	DPM_REQUEST_SNK_STARTUP                 = BIT(11),
-	DPM_REQUEST_SRC_STARTUP                 = BIT(12),
-	DPM_REQUEST_HARD_RESET_SEND             = BIT(13),
-	DPM_REQUEST_SOFT_RESET_SEND             = BIT(14),
-	DPM_REQUEST_PORT_DISCOVERY              = BIT(15),
-	DPM_REQUEST_SEND_ALERT                  = BIT(16),
-	DPM_REQUEST_ENTER_USB                   = BIT(17),
-	DPM_REQUEST_GET_SRC_CAPS                = BIT(18),
-	DPM_REQUEST_EXIT_MODES                  = BIT(19),
-	DPM_REQUEST_SOP_PRIME_SOFT_RESET_SEND   = BIT(20),
-	DPM_REQUEST_FRS_DET_ENABLE		= BIT(21),
-	DPM_REQUEST_FRS_DET_DISABLE		= BIT(22),
-	DPM_REQUEST_DATA_RESET                  = BIT(23),
-	DPM_REQUEST_GET_REVISION                = BIT(24),
+	DPM_REQUEST_DR_SWAP = BIT(0),
+	DPM_REQUEST_PR_SWAP = BIT(1),
+	DPM_REQUEST_VCONN_SWAP = BIT(2),
+	DPM_REQUEST_GOTO_MIN = BIT(3),
+	DPM_REQUEST_SRC_CAP_CHANGE = BIT(4),
+	DPM_REQUEST_GET_SNK_CAPS = BIT(5),
+	DPM_REQUEST_SEND_PING = BIT(6),
+	DPM_REQUEST_SOURCE_CAP = BIT(7),
+	DPM_REQUEST_NEW_POWER_LEVEL = BIT(8),
+	DPM_REQUEST_VDM = BIT(9),
+	DPM_REQUEST_BIST_TX = BIT(10),
+	DPM_REQUEST_SNK_STARTUP = BIT(11),
+	DPM_REQUEST_SRC_STARTUP = BIT(12),
+	DPM_REQUEST_HARD_RESET_SEND = BIT(13),
+	DPM_REQUEST_SOFT_RESET_SEND = BIT(14),
+	DPM_REQUEST_PORT_DISCOVERY = BIT(15),
+	DPM_REQUEST_SEND_ALERT = BIT(16),
+	DPM_REQUEST_ENTER_USB = BIT(17),
+	DPM_REQUEST_GET_SRC_CAPS = BIT(18),
+	DPM_REQUEST_EXIT_MODES = BIT(19),
+	DPM_REQUEST_SOP_PRIME_SOFT_RESET_SEND = BIT(20),
+	DPM_REQUEST_FRS_DET_ENABLE = BIT(21),
+	DPM_REQUEST_FRS_DET_DISABLE = BIT(22),
+	DPM_REQUEST_DATA_RESET = BIT(23),
+	DPM_REQUEST_GET_REVISION = BIT(24),
 };
 
 /**
@@ -1140,9 +1139,9 @@ bool pd_get_partner_unconstr_power(int port);
  */
 void pd_resume_check_pr_swap_needed(int port);
 
-/* Control Message type */
+/* Control Message type - USB-PD Spec Rev 3.0, Ver 1.1, Table 6-5 */
 enum pd_ctrl_msg_type {
-	PD_CTRL_INVALID  = 0, /* 0 Reserved - DO NOT PUT IN MESSAGES */
+	PD_CTRL_INVALID = 0, /* 0 Reserved - DO NOT PUT IN MESSAGES */
 	PD_CTRL_GOOD_CRC = 1,
 	PD_CTRL_GOTO_MIN = 2,
 	PD_CTRL_ACCEPT = 3,
@@ -1173,45 +1172,68 @@ enum pd_ctrl_msg_type {
 };
 
 /* Control message types which always mark the start of an AMS */
-#define PD_CTRL_AMS_START_MASK ((1 << PD_CTRL_GOTO_MIN) | \
-				(1 << PD_CTRL_GET_SOURCE_CAP) | \
-				(1 << PD_CTRL_GET_SINK_CAP) | \
-				(1 << PD_CTRL_DR_SWAP) | \
-				(1 << PD_CTRL_PR_SWAP) | \
-				(1 << PD_CTRL_VCONN_SWAP) | \
-				(1 << PD_CTRL_GET_SOURCE_CAP_EXT) | \
-				(1 << PD_CTRL_GET_STATUS) | \
-				(1 << PD_CTRL_FR_SWAP) | \
-				(1 << PD_CTRL_GET_PPS_STATUS) | \
-				(1 << PD_CTRL_GET_COUNTRY_CODES))
-
+#define PD_CTRL_AMS_START_MASK                                           \
+	((1 << PD_CTRL_GOTO_MIN) | (1 << PD_CTRL_GET_SOURCE_CAP) |       \
+	 (1 << PD_CTRL_GET_SINK_CAP) | (1 << PD_CTRL_DR_SWAP) |          \
+	 (1 << PD_CTRL_PR_SWAP) | (1 << PD_CTRL_VCONN_SWAP) |            \
+	 (1 << PD_CTRL_GET_SOURCE_CAP_EXT) | (1 << PD_CTRL_GET_STATUS) | \
+	 (1 << PD_CTRL_FR_SWAP) | (1 << PD_CTRL_GET_PPS_STATUS) |        \
+	 (1 << PD_CTRL_GET_COUNTRY_CODES))
 
 /* Battery Status Data Object fields for REV 3.0 */
 #define BSDO_CAP_UNKNOWN 0xffff
-#define BSDO_CAP(n)      (((n) & 0xffff) << 16)
-#define BSDO_INVALID     BIT(8)
-#define BSDO_PRESENT     BIT(9)
+#define BSDO_CAP(n) (((n)&0xffff) << 16)
+#define BSDO_INVALID BIT(8)
+#define BSDO_PRESENT BIT(9)
 #define BSDO_DISCHARGING BIT(10)
-#define BSDO_IDLE        BIT(11)
+#define BSDO_IDLE BIT(11)
 
 /* Battery Capability offsets for 16-bit array indexes */
-#define BCDB_VID	0
-#define BCDB_PID	1
-#define BCDB_DESIGN_CAP	2
-#define BCDB_FULL_CAP	3
-#define BCDB_BATT_TYPE	4
+#define BCDB_VID 0
+#define BCDB_PID 1
+#define BCDB_DESIGN_CAP 2
+#define BCDB_FULL_CAP 3
+#define BCDB_BATT_TYPE 4
+
+/* Battery Capability Data Block (BCDB) in struct format.
+ * See USB-PD spec Rev 3.1, V 1.3 section 6.5.5
+ */
+struct pd_bcdb {
+	/* Vendor ID*/
+	uint16_t vid;
+	/* Product ID */
+	uint16_t pid;
+	/* Battery’s design capacity in 0.1 Wh (0 = no batt, 0xFFFF = unknown)
+	 */
+	uint16_t design_cap;
+	/* Battery’s last full charge capacity in 0.1 Wh (0 = no batt,
+	 * 0xFFFF = unknown)
+	 */
+	uint16_t last_full_charge_cap;
+	/* Bit 0 indicates if the request was invalid. Other bits reserved. */
+	uint8_t battery_type;
+} __packed;
+
+/* Maximum number of different batteries that can be queried through Get Battery
+ * Status and Get Battery Capability requests. Indices 0 to 3 are fixed
+ * batteries and indices 4 to 7 are hot-swappable batteries. Not all are
+ * necessarily present.
+ *
+ * See USB-PD spec Rev 3.1, V 1.3 sections 6.5.4 - .5
+ */
+#define PD_BATT_MAX (8)
 
 /*
  * Get Battery Cap Message fields for REV 3.0 (assumes extended header is
  * present in first two bytes)
  */
-#define BATT_CAP_REF(n)  (((n) >> 16) & 0xff)
+#define BATT_CAP_REF(n) (((n) >> 16) & 0xff)
 
 /* SOP SDB fields for PD Rev 3.0 Section 6.5.2.1 */
 enum pd_sdb_temperature_status {
-	PD_SDB_TEMPERATURE_STATUS_NOT_SUPPORTED    = 0,
-	PD_SDB_TEMPERATURE_STATUS_NORMAL           = 2,
-	PD_SDB_TEMPERATURE_STATUS_WARNING          = 4,
+	PD_SDB_TEMPERATURE_STATUS_NOT_SUPPORTED = 0,
+	PD_SDB_TEMPERATURE_STATUS_NORMAL = 2,
+	PD_SDB_TEMPERATURE_STATUS_WARNING = 4,
 	PD_SDB_TEMPERATURE_STATUS_OVER_TEMPERATURE = 6,
 } __packed;
 BUILD_ASSERT(sizeof(enum pd_sdb_temperature_status) == 1);
@@ -1245,7 +1267,7 @@ enum pd_sdb_power_indicator {
 	PD_SDB_POWER_INDICATOR_BREATHING = (3 << 3),
 };
 
-/* Extended message type for REV 3.0 */
+/* Extended message type for REV 3.0 - USB-PD Spec 3.0, Ver 1.1, Table 6-42 */
 enum pd_ext_msg_type {
 	/* 0 Reserved */
 	PD_EXT_SOURCE_CAP = 1,
@@ -1273,16 +1295,17 @@ enum pd_ext_msg_type {
 };
 
 /* Alert Data Object fields for REV 3.1 */
-#define ADO_EXTENDED_ALERT_EVENT        (BIT(24) << 7)
+#define ADO_EXTENDED_ALERT_EVENT (BIT(24) << 7)
+#define ADO_EXTENDED_ALERT_EVENT_TYPE 0xf
 /* Alert Data Object fields for REV 3.0 */
-#define ADO_OVP_EVENT                   (BIT(24) << 6)
-#define ADO_SOURCE_INPUT_CHANGE         (BIT(24) << 5)
-#define ADO_OPERATING_CONDITION_CHANGE  (BIT(24) << 4)
-#define ADO_OTP_EVENT                   (BIT(24) << 3)
-#define ADO_OCP_EVENT                   (BIT(24) << 2)
-#define ADO_BATTERY_STATUS_CHANGE       (BIT(24) << 1)
-#define ADO_FIXED_BATTERIES(n)          ((n & 0xf) << 20)
-#define ADO_HOT_SWAPPABLE_BATTERIES(n)  ((n & 0xf) << 16)
+#define ADO_OVP_EVENT (BIT(24) << 6)
+#define ADO_SOURCE_INPUT_CHANGE (BIT(24) << 5)
+#define ADO_OPERATING_CONDITION_CHANGE (BIT(24) << 4)
+#define ADO_OTP_EVENT (BIT(24) << 3)
+#define ADO_OCP_EVENT (BIT(24) << 2)
+#define ADO_BATTERY_STATUS_CHANGE (BIT(24) << 1)
+#define ADO_FIXED_BATTERIES(n) ((n & 0xf) << 20)
+#define ADO_HOT_SWAPPABLE_BATTERIES(n) ((n & 0xf) << 16)
 
 /* Extended alert event types for REV 3.1 */
 enum ado_extended_alert_event_type {
@@ -1292,7 +1315,7 @@ enum ado_extended_alert_event_type {
 	ADO_CONTROLLER_INITIATED_WAKE = 0x4,
 };
 
-/* Data message type */
+/* Data message type - USB-PD Spec Rev 3.0, Ver 1.1, Table 6-6 */
 enum pd_data_msg_type {
 	/* 0 Reserved */
 	PD_DATA_SOURCE_CAP = 1,
@@ -1314,15 +1337,11 @@ enum pd_data_msg_type {
 	/* 16-31 Reserved */
 };
 
-
 /*
  * Cable plug. See 6.2.1.1.7 Cable Plug. Only applies to SOP' and SOP".
  * Replaced by pd_power_role for SOP packets.
  */
-enum pd_cable_plug {
-	PD_PLUG_FROM_DFP_UFP = 0,
-	PD_PLUG_FROM_CABLE = 1
-};
+enum pd_cable_plug { PD_PLUG_FROM_DFP_UFP = 0, PD_PLUG_FROM_CABLE = 1 };
 
 enum cable_outlet {
 	CABLE_PLUG = 0,
@@ -1331,11 +1350,11 @@ enum cable_outlet {
 
 /* Vconn role */
 #define PD_ROLE_VCONN_OFF 0
-#define PD_ROLE_VCONN_ON  1
+#define PD_ROLE_VCONN_ON 1
 
 /* chunk is a request or response in REV 3.0 */
 #define CHUNK_RESPONSE 0
-#define CHUNK_REQUEST  1
+#define CHUNK_REQUEST 1
 
 /* collision avoidance Rp values in REV 3.0 */
 #define SINK_TX_OK TYPEC_RP_3A0
@@ -1352,36 +1371,37 @@ enum cable_outlet {
 
 /* Port default state at startup */
 #ifdef CONFIG_USB_PD_DUAL_ROLE
-#define PD_DEFAULT_STATE(port) ((PD_ROLE_DEFAULT(port) == PD_ROLE_SOURCE) ? \
-				PD_STATE_SRC_DISCONNECTED :	      \
-				PD_STATE_SNK_DISCONNECTED)
+#define PD_DEFAULT_STATE(port)                       \
+	((PD_ROLE_DEFAULT(port) == PD_ROLE_SOURCE) ? \
+		 PD_STATE_SRC_DISCONNECTED :         \
+		 PD_STATE_SNK_DISCONNECTED)
 #else
 #define PD_DEFAULT_STATE(port) PD_STATE_SRC_DISCONNECTED
 #endif
 
-/* build extended message header */
-/* All extended messages are chunked, so set bit 15 */
+/* Build extended message header with chunking */
 #define PD_EXT_HEADER(cnum, rchk, dsize) \
-	 (BIT(15) | ((cnum) << 11) | \
-	 ((rchk) << 10) | (dsize))
+	(BIT(15) | ((cnum) << 11) | ((rchk) << 10) | (dsize))
+
+/* Build extended message header without chunking */
+#define PD_EXT_HEADER_UNCHUNKED(dsize) (dsize)
 
 /* build message header */
-#define PD_HEADER(type, prole, drole, id, cnt, rev, ext) \
-	((type) | ((rev) << 6) | \
-	((drole) << 5) | ((prole) << 8) | \
-	((id) << 9) | ((cnt) << 12) | ((ext) << 15))
+#define PD_HEADER(type, prole, drole, id, cnt, rev, ext)           \
+	((type) | ((rev) << 6) | ((drole) << 5) | ((prole) << 8) | \
+	 ((id) << 9) | ((cnt) << 12) | ((ext) << 15))
 
 /* Used for processing pd header */
-#define PD_HEADER_EXT(header)   (((header) >> 15) & 1)
-#define PD_HEADER_CNT(header)   (((header) >> 12) & 7)
+#define PD_HEADER_EXT(header) (((header) >> 15) & 1)
+#define PD_HEADER_CNT(header) (((header) >> 12) & 7)
 /*
  * NOTE: bit 4 was added in PD 3.0, and should be reserved and set to 0 in PD
  * 2.0 messages
  */
-#define PD_HEADER_TYPE(header)  ((header) & 0x1F)
-#define PD_HEADER_ID(header)    (((header) >> 9) & 7)
+#define PD_HEADER_TYPE(header) ((header)&0x1F)
+#define PD_HEADER_ID(header) (((header) >> 9) & 7)
 #define PD_HEADER_PROLE(header) (((header) >> 8) & 1)
-#define PD_HEADER_REV(header)   (((header) >> 6) & 3)
+#define PD_HEADER_REV(header) (((header) >> 6) & 3)
 #define PD_HEADER_DROLE(header) (((header) >> 5) & 1)
 
 /*
@@ -1390,47 +1410,47 @@ enum cable_outlet {
  * NOTE: This is not part of the PD spec.
  */
 #define PD_HEADER_GET_SOP(header) (((header) >> 28) & 0xf)
-#define PD_HEADER_SOP(sop) (((sop) & 0xf) << 28)
+#define PD_HEADER_SOP(sop) (((sop)&0xf) << 28)
 
 /* Used for processing pd extended header */
-#define PD_EXT_HEADER_CHUNKED(header)   (((header) >> 15) & 1)
+#define PD_EXT_HEADER_CHUNKED(header) (((header) >> 15) & 1)
 #define PD_EXT_HEADER_CHUNK_NUM(header) (((header) >> 11) & 0xf)
 #define PD_EXT_HEADER_REQ_CHUNK(header) (((header) >> 10) & 1)
-#define PD_EXT_HEADER_DATA_SIZE(header) ((header) & 0x1ff)
+#define PD_EXT_HEADER_DATA_SIZE(header) ((header)&0x1ff)
 
 /* Used to get extended header from the first 32-bit word of the message */
 #define GET_EXT_HEADER(msg) (msg & 0xffff)
 
 /* Extended message constants (PD 3.0, Rev. 2.0, section 6.13) */
-#define PD_MAX_EXTENDED_MSG_LEN       260
-#define PD_MAX_EXTENDED_MSG_CHUNK_LEN  26
+#define PD_MAX_EXTENDED_MSG_LEN 260
+#define PD_MAX_EXTENDED_MSG_CHUNK_LEN 26
 
 /* K-codes for special symbols */
 #define PD_SYNC1 0x18
 #define PD_SYNC2 0x11
 #define PD_SYNC3 0x06
-#define PD_RST1  0x07
-#define PD_RST2  0x19
-#define PD_EOP   0x0D
+#define PD_RST1 0x07
+#define PD_RST2 0x19
+#define PD_EOP 0x0D
 
 /* Minimum PD supply current  (mA) */
-#define PD_MIN_MA	500
+#define PD_MIN_MA 500
 
 /* Minimum PD voltage (mV) */
-#define PD_MIN_MV	5000
+#define PD_MIN_MV 5000
 
 /* No connect voltage threshold for sources based on Rp */
-#define PD_SRC_DEF_VNC_MV        1600
-#define PD_SRC_1_5_VNC_MV        1600
-#define PD_SRC_3_0_VNC_MV        2600
+#define PD_SRC_DEF_VNC_MV 1600
+#define PD_SRC_1_5_VNC_MV 1600
+#define PD_SRC_3_0_VNC_MV 2600
 
 /* Rd voltage threshold for sources based on Rp */
-#define PD_SRC_DEF_RD_THRESH_MV  200
-#define PD_SRC_1_5_RD_THRESH_MV  400
-#define PD_SRC_3_0_RD_THRESH_MV  800
+#define PD_SRC_DEF_RD_THRESH_MV 200
+#define PD_SRC_1_5_RD_THRESH_MV 400
+#define PD_SRC_3_0_RD_THRESH_MV 800
 
 /* Voltage threshold to detect connection when presenting Rd */
-#define PD_SNK_VA_MV             250
+#define PD_SNK_VA_MV 250
 
 /* --- Policy layer functions --- */
 
@@ -1523,7 +1543,7 @@ void pd_process_source_cap(int port, int cnt, uint32_t *src_caps);
  * @param ma reduce current to minimum value.
  * @param mv reduce voltage to minimum value.
  */
-void pd_snk_give_back(int port, uint32_t * const ma, uint32_t * const mv);
+void pd_snk_give_back(int port, uint32_t *const ma, uint32_t *const mv);
 
 /**
  * Put a cap on the max voltage requested as a sink.
@@ -1631,7 +1651,6 @@ void pd_set_external_voltage_limit(int port, int mv);
 void pd_set_input_current_limit(int port, uint32_t max_ma,
 				uint32_t supply_voltage);
 
-
 /**
  * Update the power contract if it exists.
  *
@@ -1703,8 +1722,7 @@ __override_proto bool pd_can_charge_from_device(int port, const int pdo_cnt,
  * @param data_role current data role
  * @return True if data swap is allowed, False otherwise
  */
-__override_proto int pd_check_data_swap(int port,
-				enum pd_data_role data_role);
+__override_proto int pd_check_data_swap(int port, enum pd_data_role data_role);
 
 /**
  * Check if vconn swap is allowed.
@@ -1722,9 +1740,8 @@ int pd_check_vconn_swap(int port);
  * @param pr_role Our power role
  * @param flags PD flags
  */
-__override_proto void pd_check_pr_role(int port,
-				enum pd_power_role pr_role,
-				int flags);
+__override_proto void pd_check_pr_role(int port, enum pd_power_role pr_role,
+				       int flags);
 
 /**
  * Check current data role for potential data swap
@@ -1733,9 +1750,8 @@ __override_proto void pd_check_pr_role(int port,
  * @param dr_role Our data role
  * @param flags PD flags
  */
-__override_proto void pd_check_dr_role(int port,
-				enum pd_data_role dr_role,
-				int flags);
+__override_proto void pd_check_dr_role(int port, enum pd_data_role dr_role,
+				       int flags);
 
 /**
  * Check for a potential Vconn swap if the port isn't
@@ -1753,7 +1769,7 @@ __override_proto void pd_try_execute_vconn_swap(int port, int flags);
  * @param data_role new data role
  */
 __override_proto void pd_execute_data_swap(int port,
-				enum pd_data_role data_role);
+					   enum pd_data_role data_role);
 
 /**
  * Get desired dual role state when chipset is suspended.
@@ -1802,7 +1818,7 @@ __override_proto int pd_custom_vdm(int port, int cnt, uint32_t *payload,
  * @return if >0, number of VDOs to send back.
  */
 int pd_svdm(int port, int cnt, uint32_t *payload, uint32_t **rpayload,
-		uint32_t head, enum tcpci_msg_type *rtype);
+	    uint32_t head, enum tcpci_msg_type *rtype);
 
 /**
  * Handle Custom VDMs for flashing.
@@ -1823,8 +1839,8 @@ int pd_custom_flash_vdm(int port, int cnt, uint32_t *payload);
  * @param opos object position of mode to exit.
  * @return vdm for UFP to be sent to enter mode or zero if not.
  */
-uint32_t pd_dfp_enter_mode(int port, enum tcpci_msg_type type,
-		uint16_t svid, int opos);
+uint32_t pd_dfp_enter_mode(int port, enum tcpci_msg_type type, uint16_t svid,
+			   int opos);
 
 /**
  * Save the Enter mode command data received from the port partner for setting
@@ -1862,7 +1878,7 @@ int pd_dfp_dp_get_pin_mode(int port, uint32_t status);
  * @return 1 if UFP should be sent exit mode VDM.
  */
 int pd_dfp_exit_mode(int port, enum tcpci_msg_type type, uint16_t svid,
-		int opos);
+		     int opos);
 
 /**
  * Consume the SVDM attention data
@@ -1881,7 +1897,7 @@ void dfp_consume_attention(int port, uint32_t *payload);
  * @param payload payload data.
  */
 void dfp_consume_identity(int port, enum tcpci_msg_type type, int cnt,
-		uint32_t *payload);
+			  uint32_t *payload);
 
 /**
  * Consume the SVIDs
@@ -1892,7 +1908,7 @@ void dfp_consume_identity(int port, enum tcpci_msg_type type, int cnt,
  * @param payload payload data.
  */
 void dfp_consume_svids(int port, enum tcpci_msg_type type, int cnt,
-		uint32_t *payload);
+		       uint32_t *payload);
 
 /**
  * Consume the alternate modes
@@ -1903,7 +1919,7 @@ void dfp_consume_svids(int port, enum tcpci_msg_type type, int cnt,
  * @param payload payload data.
  */
 void dfp_consume_modes(int port, enum tcpci_msg_type type, int cnt,
-		uint32_t *payload);
+		       uint32_t *payload);
 
 /**
  * Returns true if connected VPD supports Charge Through
@@ -1914,68 +1930,6 @@ void dfp_consume_modes(int port, enum tcpci_msg_type type, int cnt,
 bool is_vpd_ct_supported(int port);
 
 /**
- * Returns CTVPD ground impedance
- *
- * @param port     USB-C port number
- * @return         Ground impedance through the VPD in 1 mOhm increments, else
- *                 0 if Charge Through isn't supported
- */
-uint8_t get_vpd_ct_gnd_impedance(int port);
-
-/**
- * Returns CTVPD VBUS impedance
- *
- * @param port     USB-C port number
- * @return         VBUS impedance through the VPD in 2 mOhm increments, else
- *                 0 if Charge Through isn't supported
- */
-uint8_t get_vpd_ct_vbus_impedance(int port);
-
-/**
- * Returns CTVPD Current support
- *
- * @param port     USB-C port number
- * @return         0 - 3A capable or
- *                 1 - 5A capable
- */
-uint8_t get_vpd_ct_current_support(int port);
-
-/**
- * Returns CTVPD Maximum VBUS Voltage
- *
- * @param port     USB-C port number
- * @return         0 - 20V
- *                 1 - 30V
- *                 2 - 40V
- *                 3 - 50V
- */
-uint8_t get_vpd_ct_max_vbus_voltage(int port);
-
-/**
- * Returns VPD VDO Version
- *
- * @param port     USB-C port number
- * @return         0 for Version 1.0
- */
-uint8_t get_vpd_ct_vdo_version(int port);
-
-/**
- * Returns VPD Firmware Version
- *
- * @param port     USB-C port number
- * @return         Firmware version assigned by the VID owner
- */
-uint8_t get_vpd_ct_firmware_verion(int port);
-
-/**
- * Returns HW Firmware Version
- *
- * @param port     USB-C port number
- * @return         HW version assigned by the VID owner
- */
-uint8_t get_vpd_ct_hw_version(int port);
-
-/**
  * Initialize alternate mode discovery info for DFP
  *
  * @param port     USB-C port number
@@ -2007,7 +1961,7 @@ void pd_set_identity_discovery(int port, enum tcpci_msg_type type,
  * @return      Current discovery state (failed or complete)
  */
 enum pd_discovery_state pd_get_identity_discovery(int port,
-						enum tcpci_msg_type type);
+						  enum tcpci_msg_type type);
 
 /**
  * Set SVID discovery state for this type and port.
@@ -2017,7 +1971,7 @@ enum pd_discovery_state pd_get_identity_discovery(int port,
  * @param disc Discovery state to set (failed or complete)
  */
 void pd_set_svids_discovery(int port, enum tcpci_msg_type type,
-		enum pd_discovery_state disc);
+			    enum pd_discovery_state disc);
 
 /**
  * Get SVID discovery state for this type and port
@@ -2027,7 +1981,7 @@ void pd_set_svids_discovery(int port, enum tcpci_msg_type type,
  * @return     Current discovery state (failed or complete)
  */
 enum pd_discovery_state pd_get_svids_discovery(int port,
-		enum tcpci_msg_type type);
+					       enum tcpci_msg_type type);
 
 /**
  * Set Modes discovery state for this port, SOP* type, and SVID.
@@ -2037,8 +1991,8 @@ enum pd_discovery_state pd_get_svids_discovery(int port,
  * @param svid SVID to set mode discovery state for
  * @param disc Discovery state to set (failed or complete)
  */
-void pd_set_modes_discovery(int port, enum tcpci_msg_type type,
-		uint16_t svid, enum pd_discovery_state disc);
+void pd_set_modes_discovery(int port, enum tcpci_msg_type type, uint16_t svid,
+			    enum pd_discovery_state disc);
 
 /**
  * Get Modes discovery state for this port and SOP* type. Modes discover is
@@ -2054,7 +2008,7 @@ void pd_set_modes_discovery(int port, enum tcpci_msg_type type,
  *                                       PD_DISC_FAIL)
  */
 enum pd_discovery_state pd_get_modes_discovery(int port,
-		enum tcpci_msg_type type);
+					       enum tcpci_msg_type type);
 
 /**
  * Returns the mode vdo count of the specified SVID and sets
@@ -2068,8 +2022,8 @@ enum pd_discovery_state pd_get_modes_discovery(int port,
  * @return         Mode VDO cnt of specified SVID if is discovered,
  *                 0 otherwise
  */
-int pd_get_mode_vdo_for_svid(int port, enum tcpci_msg_type type,
-		uint16_t svid, uint32_t *vdo_out);
+int pd_get_mode_vdo_for_svid(int port, enum tcpci_msg_type type, uint16_t svid,
+			     uint32_t *vdo_out);
 
 /**
  * Get a pointer to mode data for the next SVID that needs to be discovered.
@@ -2085,7 +2039,7 @@ int pd_get_mode_vdo_for_svid(int port, enum tcpci_msg_type type,
  *             NULL, otherwise
  */
 const struct svid_mode_data *pd_get_next_mode(int port,
-		enum tcpci_msg_type type);
+					      enum tcpci_msg_type type);
 
 /**
  * Return a pointer to the discover identity response structure for this SOP*
@@ -2096,7 +2050,7 @@ const struct svid_mode_data *pd_get_next_mode(int port,
  * @return      pointer to response structure, which the caller may not alter
  */
 const union disc_ident_ack *pd_get_identity_response(int port,
-					       enum tcpci_msg_type type);
+						     enum tcpci_msg_type type);
 
 /**
  * Return the VID of the USB PD accessory connected to a specified port
@@ -2152,7 +2106,7 @@ uint16_t pd_get_svid(int port, uint16_t svid_idx, enum tcpci_msg_type type);
  * @return         Pointer to modes of VDO
  */
 const uint32_t *pd_get_mode_vdo(int port, uint16_t svid_idx,
-		enum tcpci_msg_type type);
+				enum tcpci_msg_type type);
 
 /*
  * Looks for a discovered mode VDO for the specified SVID.
@@ -2163,7 +2117,7 @@ const uint32_t *pd_get_mode_vdo(int port, uint16_t svid_idx,
  * @return     Whether a mode was discovered for the SVID
  */
 bool pd_is_mode_discovered_for_svid(int port, enum tcpci_msg_type type,
-		uint16_t svid);
+				    uint16_t svid);
 
 /**
  * Return the alternate mode entry and exit data
@@ -2173,8 +2127,8 @@ bool pd_is_mode_discovered_for_svid(int port, enum tcpci_msg_type type,
  * @param svid  SVID
  * @return      pointer to SVDM mode data
  */
-struct svdm_amode_data *pd_get_amode_data(int port,
-		enum tcpci_msg_type type, uint16_t svid);
+struct svdm_amode_data *pd_get_amode_data(int port, enum tcpci_msg_type type,
+					  uint16_t svid);
 
 /*
  * Returns cable revision
@@ -2242,8 +2196,8 @@ bool pd_discovery_access_validate(int port, enum tcpci_msg_type type);
  * @param type Transmit type (SOP, SOP') for discovered information
  * @return     pointer to PD alternate mode discovery results
  */
-struct pd_discovery *pd_get_am_discovery_and_notify_access(int port,
-		enum tcpci_msg_type type);
+struct pd_discovery *
+pd_get_am_discovery_and_notify_access(int port, enum tcpci_msg_type type);
 
 /*
  * Returns the constant pointer to PD alternate mode discovery results
@@ -2254,7 +2208,7 @@ struct pd_discovery *pd_get_am_discovery_and_notify_access(int port,
  * @return     pointer to PD alternate mode discovery results
  */
 const struct pd_discovery *pd_get_am_discovery(int port,
-		enum tcpci_msg_type type);
+					       enum tcpci_msg_type type);
 
 /*
  * Returns the pointer to PD active alternate modes.
@@ -2264,8 +2218,8 @@ const struct pd_discovery *pd_get_am_discovery(int port,
  * @param type Transmit type (SOP, SOP', SOP'') for active modes
  * @return     Pointer to PD active alternate modes.
  */
-struct partner_active_modes *pd_get_partner_active_modes(int port,
-		enum tcpci_msg_type type);
+struct partner_active_modes *
+pd_get_partner_active_modes(int port, enum tcpci_msg_type type);
 
 /*
  * Sets the current object position for DP alt-mode
@@ -2440,8 +2394,7 @@ enum tbt_compat_cable_speed get_tbt_cable_speed(int port);
  * @param payload   payload data
  * @return          Number of object filled
  */
-int enter_tbt_compat_mode(int port, enum tcpci_msg_type sop,
-			uint32_t *payload);
+int enter_tbt_compat_mode(int port, enum tcpci_msg_type sop, uint32_t *payload);
 
 /**
  * Return maximum speed supported by the port to enter into Thunderbolt mode
@@ -2476,8 +2429,7 @@ __override_proto enum tbt_compat_cable_speed board_get_max_tbt_speed(int port);
  *	   EC_RES_UNAVAILABLE if board does not support this feature
  */
 __override_proto enum ec_status
-			board_set_tbt_ufp_reply(int port,
-						enum typec_tbt_ufp_reply reply);
+board_set_tbt_ufp_reply(int port, enum typec_tbt_ufp_reply reply);
 
 /**
  * Return true if the board's port supports TBT or USB4
@@ -2584,8 +2536,8 @@ void pd_dpm_request(int port, enum pd_dpm_request req);
  *                must be 1 - 7 inclusive.
  * @return        True if the setup was successful
  */
-bool pd_setup_vdm_request(int port, enum tcpci_msg_type tx_type,
-		uint32_t *vdm, uint32_t vdo_cnt);
+bool pd_setup_vdm_request(int port, enum tcpci_msg_type tx_type, uint32_t *vdm,
+			  uint32_t vdo_cnt);
 
 /* Power Data Objects for the source and the sink */
 __override_proto extern const uint32_t pd_src_pdo[];
@@ -2596,6 +2548,15 @@ extern const uint32_t pd_snk_pdo[];
 extern const int pd_snk_pdo_cnt;
 
 /**
+ * TEST ONLY: Set PD_CONTROL command to enabled on this port
+ *
+ * @param port USB-C port number
+ */
+#ifdef TEST_BUILD
+void pd_control_port_enable(int port);
+#endif
+
+/**
  * Request that a host event be sent to notify the AP of a PD power event.
  *
  * Note: per-port events should be retrieved through pd_get_events(), but this
@@ -2607,7 +2568,9 @@ extern const int pd_snk_pdo_cnt;
 #if defined(HAS_TASK_HOSTCMD) && !defined(TEST_BUILD)
 void pd_send_host_event(int mask);
 #else
-static inline void pd_send_host_event(int mask) { }
+static inline void pd_send_host_event(int mask)
+{
+}
 #endif
 
 /**
@@ -2682,7 +2645,6 @@ int pd_write_preamble(int port);
  */
 int pd_write_sym(int port, int bit_off, uint32_t val10);
 
-
 /**
  * Ensure that we have an edge after EOP and we end up at level 0,
  * also fill the last byte.
@@ -2943,7 +2905,7 @@ void pd_clear_events(int port, uint32_t clear_mask);
  * @return EC_RES_SUCCESS if a VDM message is scheduled.
  */
 enum ec_status pd_request_vdm_attention(int port, const uint32_t *data,
-				       int vdo_count);
+					int vdo_count);
 
 /*
  * Requests that the port enter the specified mode. A successful result just
@@ -3058,7 +3020,7 @@ bool pd_waiting_on_partner_src_caps(int port);
  *
  * @param port USB-C port number
  */
-const uint32_t * const pd_get_src_caps(int port);
+const uint32_t *const pd_get_src_caps(int port);
 
 /**
  * Returns the number of source caps
@@ -3082,7 +3044,7 @@ void pd_set_src_caps(int port, int cnt, uint32_t *src_caps);
  *
  * @param port USB-C port number
  */
-const uint32_t * const pd_get_snk_caps(int port);
+const uint32_t *const pd_get_snk_caps(int port);
 
 /**
  * Returns the number of sink caps
@@ -3231,8 +3193,8 @@ __override_proto void pd_notify_dp_alt_mode_entry(int port);
  * Determines the PD state of the port partner according to Table 4-10 in USB PD
  * specification.
  */
-enum pd_cc_states pd_get_cc_state(
-	enum tcpc_cc_voltage_status cc1, enum tcpc_cc_voltage_status cc2);
+enum pd_cc_states pd_get_cc_state(enum tcpc_cc_voltage_status cc1,
+				  enum tcpc_cc_voltage_status cc2);
 
 /*
  * Optional, get the board-specific SRC DTS polarity.
@@ -3255,8 +3217,8 @@ __override_proto uint8_t board_get_src_dts_polarity(int port);
  * @param data type-defined information
  * @param payload pointer to the optional payload (0..16 bytes)
  */
-void pd_log_event(uint8_t type, uint8_t size_port,
-		  uint16_t data, void *payload);
+void pd_log_event(uint8_t type, uint8_t size_port, uint16_t data,
+		  void *payload);
 
 /**
  * Retrieve one logged event and prepare a VDM with it.
@@ -3267,10 +3229,15 @@ void pd_log_event(uint8_t type, uint8_t size_port,
  * @return number of 32-bit words in the VDM payload.
  */
 int pd_vdm_get_log_entry(uint32_t *payload);
-#else  /* CONFIG_USB_PD_LOGGING */
-static inline void pd_log_event(uint8_t type, uint8_t size_port,
-				uint16_t data, void *payload) {}
-static inline int pd_vdm_get_log_entry(uint32_t *payload) { return 0; }
+#else /* CONFIG_USB_PD_LOGGING */
+static inline void pd_log_event(uint8_t type, uint8_t size_port, uint16_t data,
+				void *payload)
+{
+}
+static inline int pd_vdm_get_log_entry(uint32_t *payload)
+{
+	return 0;
+}
 #endif /* CONFIG_USB_PD_LOGGING */
 
 /**
@@ -3527,9 +3494,9 @@ int typec_update_cc(int port);
  * @param pd_sdb_power_state enum defining the New Power State field of the SDB
  * @return pd_sdb_power_indicator enum for the SDB
  */
-__override_proto enum pd_sdb_power_indicator board_get_pd_sdb_power_indicator(
-enum pd_sdb_power_state power_state);
+__override_proto enum pd_sdb_power_indicator
+board_get_pd_sdb_power_indicator(enum pd_sdb_power_state power_state);
 
 /****************************************************************************/
 
-#endif  /* __CROS_EC_USB_PD_H */
+#endif /* __CROS_EC_USB_PD_H */
diff --git a/include/usb_pd_dp_ufp.h b/include/usb_pd_dp_ufp.h
index 64728d948e..663f4f1d83 100644
--- a/include/usb_pd_dp_ufp.h
+++ b/include/usb_pd_dp_ufp.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -32,4 +32,4 @@ void usb_pd_hpd_edge_event(int signal);
  */
 void usb_pd_hpd_converter_enable(int enable);
 
-#endif  /* __CROS_EC_USB_PD_DP_UFP_H */
+#endif /* __CROS_EC_USB_PD_DP_UFP_H */
diff --git a/include/usb_pd_dpm.h b/include/usb_pd_dpm.h
index 391e7ed246..083ef216b6 100644
--- a/include/usb_pd_dpm.h
+++ b/include/usb_pd_dpm.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -51,7 +51,7 @@ void dpm_data_reset_complete(int port);
  * @param vdm       The VDM payload of the ACK
  */
 void dpm_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count,
-		uint32_t *vdm);
+		   uint32_t *vdm);
 
 /*
  * Informs the DPM that a VDM NAK was received. Also applies when a VDM request
@@ -63,7 +63,7 @@ void dpm_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count,
  * @param vdm_cmd The VDM command of the request
  */
 void dpm_vdm_naked(int port, enum tcpci_msg_type type, uint16_t svid,
-		uint8_t vdm_cmd);
+		   uint8_t vdm_cmd);
 
 /*
  * Drives the Policy Engine through entry/exit mode process
@@ -131,6 +131,20 @@ int dpm_get_source_pdo(const uint32_t **src_pdo, const int port);
 int dpm_get_source_current(const int port);
 
 /*
+ * Report we've been asked to enter BIST Shared Test Mode
+ *
+ * @param port		USB-C port number
+ */
+void dpm_bist_shared_mode_enter(int port);
+
+/*
+ * Report we've been asked to exit BIST Shared Test Mode
+ *
+ * @param port		USB-C port number
+ */
+void dpm_bist_shared_mode_exit(int port);
+
+/*
  * Build SOP Status Data Block (SDB)
  *
  * @param port		USB-C port number
@@ -139,6 +153,14 @@ int dpm_get_source_current(const int port);
  */
 int dpm_get_status_msg(int port, uint8_t *msg, uint32_t *len);
 
+/*
+ * DPM function to handle a received alert message
+ *
+ * @param port		USB-C port number
+ * @param ado		Alert Data Object (ado) received from partner
+ */
+void dpm_handle_alert(int port, uint32_t ado);
+
 /* Enum for modules to describe to the DPM their setup status */
 enum dpm_msg_setup_status {
 	MSG_SETUP_SUCCESS,
@@ -147,4 +169,9 @@ enum dpm_msg_setup_status {
 	MSG_SETUP_MUX_WAIT,
 };
 
-#endif  /* __CROS_EC_USB_DPM_H */
+/* Enum to describe current state of connected USB PD buttons */
+enum dpm_pd_button_state {
+	DPM_PD_BUTTON_IDLE,
+	DPM_PD_BUTTON_PRESSED,
+};
+#endif /* __CROS_EC_USB_DPM_H */
diff --git a/include/usb_pd_flags.h b/include/usb_pd_flags.h
index 8e029bcb35..70e80379a6 100644
--- a/include/usb_pd_flags.h
+++ b/include/usb_pd_flags.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/usb_pd_pdo.h b/include/usb_pd_pdo.h
index 4219c05183..9e75555b63 100644
--- a/include/usb_pd_pdo.h
+++ b/include/usb_pd_pdo.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/usb_pd_policy.h b/include/usb_pd_policy.h
index 04a7a68e7d..a5675ded4e 100644
--- a/include/usb_pd_policy.h
+++ b/include/usb_pd_policy.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,8 +21,9 @@
  * @param dr_swap_flag   Data Role Swap Flag bit
  * @param return True if state machine should perform a DR swap, elsf False
  */
-__override_proto  bool port_discovery_dr_swap_policy(int port,
-		enum pd_data_role dr, bool dr_swap_flag);
+__override_proto bool port_discovery_dr_swap_policy(int port,
+						    enum pd_data_role dr,
+						    bool dr_swap_flag);
 
 /**
  * Port Discovery VCONN Swap Policy
@@ -35,6 +36,6 @@ __override_proto  bool port_discovery_dr_swap_policy(int port,
  * @param return True if state machine should perform a VCONN swap, elsf False
  */
 __override_proto bool port_discovery_vconn_swap_policy(int port,
-		bool vconn_swap_flag);
+						       bool vconn_swap_flag);
 
 #endif /* __CROS_EC_USB_PD_POLICY_H */
diff --git a/include/usb_pd_tbt.h b/include/usb_pd_tbt.h
index e052052813..315fccb619 100644
--- a/include/usb_pd_tbt.h
+++ b/include/usb_pd_tbt.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -106,7 +106,7 @@ enum vendor_specific_support {
 
 /* TBT Alternate Mode */
 #define TBT_ALTERNATE_MODE 0x0001
-#define PD_VDO_RESP_MODE_INTEL_TBT(x)	(((x) & 0xff) == TBT_ALTERNATE_MODE)
+#define PD_VDO_RESP_MODE_INTEL_TBT(x) (((x)&0xff) == TBT_ALTERNATE_MODE)
 
 union tbt_mode_resp_device {
 	struct {
diff --git a/include/usb_pd_tcpc.h b/include/usb_pd_tcpc.h
index 0a10f97e0e..a89030cdb7 100644
--- a/include/usb_pd_tcpc.h
+++ b/include/usb_pd_tcpc.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,11 +18,11 @@
 
 #ifdef TCPCI_I2C_PERIPHERAL
 /* Convert TCPC address to type-C port number */
-#define TCPC_ADDR_TO_PORT(addr) ((addr) \
-			- I2C_STRIP_FLAGS(CONFIG_TCPC_I2C_BASE_ADDR_FLAGS))
+#define TCPC_ADDR_TO_PORT(addr) \
+	((addr)-I2C_STRIP_FLAGS(CONFIG_TCPC_I2C_BASE_ADDR_FLAGS))
 /* Check if the i2c address belongs to TCPC */
-#define ADDR_IS_TCPC(addr)      (((addr) & 0x7E) \
-			== I2C_STRIP_FLAGS(CONFIG_TCPC_I2C_BASE_ADDR_FLAGS))
+#define ADDR_IS_TCPC(addr) \
+	(((addr)&0x7E) == I2C_STRIP_FLAGS(CONFIG_TCPC_I2C_BASE_ADDR_FLAGS))
 #endif
 
 /**
@@ -52,7 +52,7 @@ int tcpc_alert_status(int port, int *alert);
 int tcpc_alert_status_clear(int port, uint16_t mask);
 int tcpc_alert_mask_set(int port, uint16_t mask);
 int tcpc_get_cc(int port, enum tcpc_cc_voltage_status *cc1,
-	enum tcpc_cc_voltage_status *cc2);
+		enum tcpc_cc_voltage_status *cc2);
 int tcpc_select_rp_value(int port, int rp);
 int tcpc_set_cc(int port, int pull);
 int tcpc_set_polarity(int port, int polarity);
diff --git a/include/usb_pd_tcpm.h b/include/usb_pd_tcpm.h
index e34329eb18..9a78754a0d 100644
--- a/include/usb_pd_tcpm.h
+++ b/include/usb_pd_tcpm.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,7 +15,7 @@
 #include "i2c.h"
 
 /* Time to wait for TCPC to complete transmit */
-#define PD_T_TCPC_TX_TIMEOUT  (100*MSEC)
+#define PD_T_TCPC_TX_TIMEOUT (100 * MSEC)
 
 enum usbpd_cc_pin {
 	USBPD_CC_PIN_1,
@@ -25,8 +25,8 @@ enum usbpd_cc_pin {
 /* Detected resistor values of port partner */
 enum tcpc_cc_voltage_status {
 	TYPEC_CC_VOLT_OPEN = 0,
-	TYPEC_CC_VOLT_RA = 1,	  /* Port partner is applying Ra */
-	TYPEC_CC_VOLT_RD = 2,	  /* Port partner is applying Rd */
+	TYPEC_CC_VOLT_RA = 1, /* Port partner is applying Ra */
+	TYPEC_CC_VOLT_RD = 2, /* Port partner is applying Rd */
 	TYPEC_CC_VOLT_RP_DEF = 5, /* Port partner is applying Rp (0.5A) */
 	TYPEC_CC_VOLT_RP_1_5 = 6, /* Port partner is applying Rp (1.5A) */
 	TYPEC_CC_VOLT_RP_3_0 = 7, /* Port partner is applying Rp (3.0A) */
@@ -42,7 +42,7 @@ enum tcpc_cc_pull {
 };
 
 /* Pull-up values we apply as a SRC to advertise different current limits */
-FORWARD_DECLARE_ENUM(tcpc_rp_value) {
+FORWARD_DECLARE_ENUM(tcpc_rp_value){
 	TYPEC_RP_USB = 0,
 	TYPEC_RP_1A5 = 1,
 	TYPEC_RP_3A0 = 2,
@@ -58,8 +58,8 @@ enum tcpc_drp {
 /**
  * Returns whether the polarity without the DTS extension
  */
-static inline enum tcpc_cc_polarity polarity_rm_dts(
-	enum tcpc_cc_polarity polarity)
+static inline enum tcpc_cc_polarity
+polarity_rm_dts(enum tcpc_cc_polarity polarity)
 {
 	BUILD_ASSERT(POLARITY_COUNT == 4);
 	return (enum tcpc_cc_polarity)(polarity & BIT(0));
@@ -91,9 +91,9 @@ enum tcpci_msg_type {
 enum tcpc_transmit_complete {
 	TCPC_TX_UNSET = -1,
 	TCPC_TX_WAIT = 0,
-	TCPC_TX_COMPLETE_SUCCESS =   1,
+	TCPC_TX_COMPLETE_SUCCESS = 1,
 	TCPC_TX_COMPLETE_DISCARDED = 2,
-	TCPC_TX_COMPLETE_FAILED =    3,
+	TCPC_TX_COMPLETE_FAILED = 3,
 };
 
 /*
@@ -102,9 +102,9 @@ enum tcpc_transmit_complete {
  * Return true on Vbus check if Vbus is...
  */
 enum vbus_level {
-	VBUS_SAFE0V,	/* less than vSafe0V max */
-	VBUS_PRESENT,	/* at least vSafe5V min */
-	VBUS_REMOVED,	/* less than vSinkDisconnect max */
+	VBUS_SAFE0V, /* less than vSafe0V max */
+	VBUS_PRESENT, /* at least vSafe5V min */
+	VBUS_REMOVED, /* less than vSinkDisconnect max */
 };
 
 /**
@@ -120,7 +120,7 @@ static inline int cc_is_rp(enum tcpc_cc_voltage_status cc)
  * Returns true if both CC lines are completely open.
  */
 static inline int cc_is_open(enum tcpc_cc_voltage_status cc1,
-	enum tcpc_cc_voltage_status cc2)
+			     enum tcpc_cc_voltage_status cc2)
 {
 	return cc1 == TYPEC_CC_VOLT_OPEN && cc2 == TYPEC_CC_VOLT_OPEN;
 }
@@ -129,7 +129,7 @@ static inline int cc_is_open(enum tcpc_cc_voltage_status cc1,
  * Returns true if we detect the port partner is a snk debug accessory.
  */
 static inline int cc_is_snk_dbg_acc(enum tcpc_cc_voltage_status cc1,
-	enum tcpc_cc_voltage_status cc2)
+				    enum tcpc_cc_voltage_status cc2)
 {
 	return cc1 == TYPEC_CC_VOLT_RD && cc2 == TYPEC_CC_VOLT_RD;
 }
@@ -138,7 +138,7 @@ static inline int cc_is_snk_dbg_acc(enum tcpc_cc_voltage_status cc1,
  * Returns true if we detect the port partner is a src debug accessory.
  */
 static inline int cc_is_src_dbg_acc(enum tcpc_cc_voltage_status cc1,
-	enum tcpc_cc_voltage_status cc2)
+				    enum tcpc_cc_voltage_status cc2)
 {
 	return cc_is_rp(cc1) && cc_is_rp(cc2);
 }
@@ -147,7 +147,7 @@ static inline int cc_is_src_dbg_acc(enum tcpc_cc_voltage_status cc1,
  * Returns true if the port partner is an audio accessory.
  */
 static inline int cc_is_audio_acc(enum tcpc_cc_voltage_status cc1,
-	enum tcpc_cc_voltage_status cc2)
+				  enum tcpc_cc_voltage_status cc2)
 {
 	return cc1 == TYPEC_CC_VOLT_RA && cc2 == TYPEC_CC_VOLT_RA;
 }
@@ -156,7 +156,7 @@ static inline int cc_is_audio_acc(enum tcpc_cc_voltage_status cc1,
  * Returns true if the port partner is presenting at least one Rd
  */
 static inline int cc_is_at_least_one_rd(enum tcpc_cc_voltage_status cc1,
-	enum tcpc_cc_voltage_status cc2)
+					enum tcpc_cc_voltage_status cc2)
 {
 	return cc1 == TYPEC_CC_VOLT_RD || cc2 == TYPEC_CC_VOLT_RD;
 }
@@ -165,7 +165,7 @@ static inline int cc_is_at_least_one_rd(enum tcpc_cc_voltage_status cc1,
  * Returns true if the port partner is presenting Rd on only one CC line.
  */
 static inline int cc_is_only_one_rd(enum tcpc_cc_voltage_status cc1,
-	enum tcpc_cc_voltage_status cc2)
+				    enum tcpc_cc_voltage_status cc2)
 {
 	return cc_is_at_least_one_rd(cc1, cc2) && cc1 != cc2;
 }
@@ -200,7 +200,7 @@ struct tcpm_drv {
 	 * @return EC_SUCCESS or error
 	 */
 	int (*get_cc)(int port, enum tcpc_cc_voltage_status *cc1,
-		enum tcpc_cc_voltage_status *cc2);
+		      enum tcpc_cc_voltage_status *cc2);
 
 	/**
 	 * Check VBUS level
@@ -233,7 +233,8 @@ struct tcpm_drv {
 	int (*select_rp_value)(int port, int rp);
 
 	/**
-	 * Set the CC pull resistor. This sets our role as either source or sink.
+	 * Set the CC pull resistor. This sets our role as either source or
+	 * sink.
 	 *
 	 * @param port Type-C port number
 	 * @param pull One of enum tcpc_cc_pull
@@ -321,7 +322,7 @@ struct tcpm_drv {
 	 * @return EC_SUCCESS or error
 	 */
 	int (*transmit)(int port, enum tcpci_msg_type type, uint16_t header,
-					const uint32_t *data);
+			const uint32_t *data);
 
 	/**
 	 * TCPC is asserting alert
@@ -344,8 +345,7 @@ struct tcpm_drv {
 	 * @param port Type-C port number
 	 * @param enable Auto Discharge enable or disable
 	 */
-	void (*tcpc_enable_auto_discharge_disconnect)(int port,
-						      int enable);
+	void (*tcpc_enable_auto_discharge_disconnect)(int port, int enable);
 
 	/**
 	 * Manual control of TCPC DebugAccessory enable
@@ -384,7 +384,7 @@ struct tcpm_drv {
 	 * @return EC_SUCCESS or error
 	 */
 	int (*get_chip_info)(int port, int live,
-			struct ec_response_pd_chip_info_v1 *info);
+			     struct ec_response_pd_chip_info_v1 *info);
 
 	/**
 	 * Request current sinking state of the TCPC
@@ -478,7 +478,7 @@ struct tcpm_drv {
 	 *
 	 * @return EC_SUCCESS or error
 	 */
-	 int (*set_frs_enable)(int port, int enable);
+	int (*set_frs_enable)(int port, int enable);
 #endif
 
 	/**
@@ -489,7 +489,20 @@ struct tcpm_drv {
 	 *
 	 * @return EC_SUCCESS or error
 	 */
-	 int (*handle_fault)(int port, int fault);
+	int (*handle_fault)(int port, int fault);
+
+	/**
+	 * Re-initialize registers during hard reset
+	 *
+	 * NOTE: If the function alters the alert mask and power status mask,
+	 * this indicates the chip does not require a full TCPCI re-init after
+	 * a hard reset.
+	 *
+	 * @param port Type-C port number
+	 *
+	 * @return EC_SUCCESS or error
+	 */
+	int (*hard_reset_reinit)(int port);
 
 	/**
 	 * Controls BIST Test Mode (or analogous functionality) in the TCPC and
@@ -500,15 +513,25 @@ struct tcpm_drv {
 	 * @param enable true to enter BIST Test Mode; false to exit
 	 * @return EC_SUCCESS or error code
 	 */
-	 enum ec_error_list (*set_bist_test_mode)(int port, bool enable);
+	enum ec_error_list (*set_bist_test_mode)(int port, bool enable);
 
+	/**
+	 * Get control of BIST Test Mode (or analogous functionality) in the
+	 * TCPC.
+	 *
+	 * @param port   USB-C port number
+	 * @param enable true for BIST Test Mode enabled; false for error
+	 *               occurred or BIST Test Mode disabled.
+	 * @return EC_SUCCESS or error code
+	 */
+	enum ec_error_list (*get_bist_test_mode)(int port, bool *enable);
 #ifdef CONFIG_CMD_TCPC_DUMP
 	/**
 	 * Dump TCPC registers
 	 *
 	 * @param port Type-C port number
 	 */
-	 void (*dump_registers)(int port);
+	void (*dump_registers)(int port);
 #endif /* defined(CONFIG_CMD_TCPC_DUMP) */
 
 	int (*reset_bist_type_2)(int port);
@@ -534,20 +557,20 @@ struct tcpm_drv {
  * Bit 7 --> TCPC controls FRS (even when CONFIG_USB_PD_FRS_TCPC is off)
  * Bit 8 --> TCPC enable VBUS monitoring
  */
-#define TCPC_FLAGS_ALERT_ACTIVE_HIGH	BIT(0)
-#define TCPC_FLAGS_ALERT_OD		BIT(1)
-#define TCPC_FLAGS_RESET_ACTIVE_HIGH	BIT(2)
-#define TCPC_FLAGS_TCPCI_REV2_0		BIT(3)
-#define TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V	BIT(4)
-#define TCPC_FLAGS_NO_DEBUG_ACC_CONTROL	BIT(5)
-#define TCPC_FLAGS_CONTROL_VCONN	BIT(6)
-#define TCPC_FLAGS_CONTROL_FRS		BIT(7)
-#define TCPC_FLAGS_VBUS_MONITOR		BIT(8)
+#define TCPC_FLAGS_ALERT_ACTIVE_HIGH BIT(0)
+#define TCPC_FLAGS_ALERT_OD BIT(1)
+#define TCPC_FLAGS_RESET_ACTIVE_HIGH BIT(2)
+#define TCPC_FLAGS_TCPCI_REV2_0 BIT(3)
+#define TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V BIT(4)
+#define TCPC_FLAGS_NO_DEBUG_ACC_CONTROL BIT(5)
+#define TCPC_FLAGS_CONTROL_VCONN BIT(6)
+#define TCPC_FLAGS_CONTROL_FRS BIT(7)
+#define TCPC_FLAGS_VBUS_MONITOR BIT(8)
 
 #endif /* !CONFIG_ZEPHYR */
 
 struct tcpc_config_t {
-	enum ec_bus_type bus_type;	/* enum ec_bus_type */
+	enum ec_bus_type bus_type; /* enum ec_bus_type */
 	union {
 		struct i2c_info_t i2c_info;
 	};
@@ -632,9 +655,9 @@ int tcpc_get_vbus_voltage(int port);
 
 #ifdef CONFIG_CMD_TCPC_DUMP
 struct tcpc_reg_dump_map {
-	uint8_t		addr;
-	uint8_t		size;
-	const char	*name;
+	uint8_t addr;
+	uint8_t size;
+	const char *name;
 };
 
 /**
@@ -654,6 +677,6 @@ void tcpc_dump_std_registers(int port);
  *
  */
 void tcpc_dump_registers(int port, const struct tcpc_reg_dump_map *reg,
-			  int count);
+			 int count);
 #endif
 #endif /* __CROS_EC_USB_PD_TCPM_H */
diff --git a/include/usb_pd_timer.h b/include/usb_pd_timer.h
index 3a3f388b22..439b30513d 100644
--- a/include/usb_pd_timer.h
+++ b/include/usb_pd_timer.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,6 +18,18 @@
  */
 enum pd_task_timer {
 	/*
+	 * Timer to check if a USB PD power button press exceeds the long press
+	 * time limit.
+	 */
+	DPM_TIMER_PD_BUTTON_LONG_PRESS,
+
+	/*
+	 * Timer to check if a USB PD power button press exceeds the short press
+	 * time limit.
+	 */
+	DPM_TIMER_PD_BUTTON_SHORT_PRESS,
+
+	/*
 	 * In BIST_TX mode, this timer is used by a UUT to ensure that a
 	 * Continuous BIST Mode (i.e. BIST Carrier Mode) is exited in a timely
 	 * fashion.
@@ -167,7 +179,6 @@ enum pd_task_timer {
 	 */
 	PE_TIMER_WAIT_AND_ADD_JITTER,
 
-
 	/* Chunk Sender Response timer */
 	PR_TIMER_CHUNK_SENDER_RESPONSE,
 
@@ -183,7 +194,6 @@ enum pd_task_timer {
 	/* timeout to limit waiting on TCPC response (not in spec) */
 	PR_TIMER_TCPC_TX_TIMEOUT,
 
-
 	/* Time a port shall wait before it can determine it is attached */
 	TC_TIMER_CC_DEBOUNCE,
 
@@ -222,18 +232,22 @@ enum pd_task_timer {
 };
 
 enum pd_timer_range {
+	DPM_TIMER_RANGE,
 	PE_TIMER_RANGE,
 	PR_TIMER_RANGE,
 	TC_TIMER_RANGE,
 };
-#define PE_TIMER_START		PE_TIMER_BIST_CONT_MODE
-#define PE_TIMER_END		PE_TIMER_WAIT_AND_ADD_JITTER
+#define DPM_TIMER_START DPM_TIMER_PD_BUTTON_LONG_PRESS
+#define DPM_TIMER_END DPM_TIMER_PD_BUTTON_SHORT_PRESS
 
-#define PR_TIMER_START		PR_TIMER_CHUNK_SENDER_RESPONSE
-#define PR_TIMER_END		PR_TIMER_TCPC_TX_TIMEOUT
+#define PE_TIMER_START PE_TIMER_BIST_CONT_MODE
+#define PE_TIMER_END PE_TIMER_WAIT_AND_ADD_JITTER
 
-#define TC_TIMER_START		TC_TIMER_CC_DEBOUNCE
-#define TC_TIMER_END		TC_TIMER_VBUS_DEBOUNCE
+#define PR_TIMER_START PR_TIMER_CHUNK_SENDER_RESPONSE
+#define PR_TIMER_END PR_TIMER_TCPC_TX_TIMEOUT
+
+#define TC_TIMER_START TC_TIMER_CC_DEBOUNCE
+#define TC_TIMER_END TC_TIMER_VBUS_DEBOUNCE
 
 /*
  * pd_timer_init
@@ -311,7 +325,6 @@ void pd_timer_manage_expired(int port);
  */
 int pd_timer_next_expiration(int port);
 
-
 /*
  * pd_timer_dump
  * Debug display of the timers for a given port
@@ -333,30 +346,30 @@ void pd_timer_dump(int port);
  */
 
 /* exported: number of USB-C ports */
-#define MAX_PD_PORTS		CONFIG_USB_PD_PORT_MAX_COUNT
+#define MAX_PD_PORTS CONFIG_USB_PD_PORT_MAX_COUNT
 
 /* PD timers have three possible states: Active, Inactive and Disabled */
 /* exported: timer_active indicates if a timer is currently active */
-extern ATOMIC_DEFINE(timer_active, PD_TIMER_COUNT * MAX_PD_PORTS);
+extern ATOMIC_DEFINE(timer_active, PD_TIMER_COUNT *MAX_PD_PORTS);
 /* exported: timer_disabled indicates if a timer is currently disabled */
-extern ATOMIC_DEFINE(timer_disabled, PD_TIMER_COUNT * MAX_PD_PORTS);
+extern ATOMIC_DEFINE(timer_disabled, PD_TIMER_COUNT *MAX_PD_PORTS);
 
 /* exported: set/clear/check the current timer_active for a timer */
 #define PD_SET_ACTIVE(p, bit) \
-	atomic_set_bit(timer_active, (p) * PD_TIMER_COUNT + (bit))
+	atomic_set_bit(timer_active, (p)*PD_TIMER_COUNT + (bit))
 #define PD_CLR_ACTIVE(p, bit) \
-	atomic_clear_bit(timer_active, (p) * PD_TIMER_COUNT + (bit))
+	atomic_clear_bit(timer_active, (p)*PD_TIMER_COUNT + (bit))
 #define PD_CHK_ACTIVE(p, bit) \
-	atomic_test_bit(timer_active, (p) * PD_TIMER_COUNT + (bit))
+	atomic_test_bit(timer_active, (p)*PD_TIMER_COUNT + (bit))
 
 /* exported: set/clear/check the current timer_disabled for a timer */
 #define PD_SET_DISABLED(p, bit) \
-	atomic_set_bit(timer_disabled, (p) * PD_TIMER_COUNT + (bit))
+	atomic_set_bit(timer_disabled, (p)*PD_TIMER_COUNT + (bit))
 #define PD_CLR_DISABLED(p, bit) \
-	atomic_clear_bit(timer_disabled, (p) * PD_TIMER_COUNT + (bit))
+	atomic_clear_bit(timer_disabled, (p)*PD_TIMER_COUNT + (bit))
 #define PD_CHK_DISABLED(p, bit) \
-	atomic_test_bit(timer_disabled, (p) * PD_TIMER_COUNT + (bit))
+	atomic_test_bit(timer_disabled, (p)*PD_TIMER_COUNT + (bit))
 
 #endif /* TEST_BUILD */
 
-#endif  /* __CROS_EC_USB_PD_TIMER_H */
+#endif /* __CROS_EC_USB_PD_TIMER_H */
diff --git a/include/usb_pd_vdo.h b/include/usb_pd_vdo.h
index 9f6e35e117..ed1bc490f1 100644
--- a/include/usb_pd_vdo.h
+++ b/include/usb_pd_vdo.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -134,20 +134,20 @@ struct product_vdo {
 #define PD_PRODUCT_IS_TBT3(vdo) ((vdo) >> 3 & BIT(0))
 
 /* UFP VDO Version 1.2; update the value when UFP VDO version changes */
-#define VDO_UFP1(cap, ctype, alt, speed)			\
-	((0x2) << 29 | ((cap) & 0xf) << 24			\
-	| ((ctype) & 0x3) << 22 | ((alt) & 0x7) << 3 | ((speed) & 0x7))
+#define VDO_UFP1(cap, ctype, alt, speed)                         \
+	((0x2) << 29 | ((cap)&0xf) << 24 | ((ctype)&0x3) << 22 | \
+	 ((alt)&0x7) << 3 | ((speed)&0x7))
 
 /* UFP VDO 1 Alternate Modes */
-#define VDO_UFP1_ALT_MODE_TBT3           BIT(0)
-#define VDO_UFP1_ALT_MODE_RECONFIGURE    BIT(1)
+#define VDO_UFP1_ALT_MODE_TBT3 BIT(0)
+#define VDO_UFP1_ALT_MODE_RECONFIGURE BIT(1)
 #define VDO_UFP1_ALT_MODE_NO_RECONFIGURE BIT(2)
 
 /* UFP VDO 1 Device Capability */
-#define VDO_UFP1_CAPABILITY_USB20           BIT(0)
+#define VDO_UFP1_CAPABILITY_USB20 BIT(0)
 #define VDO_UFP1_CAPABILITY_USB20_BILLBOARD BIT(1)
-#define VDO_UFP1_CAPABILITY_USB32           BIT(2)
-#define VDO_UFP1_CAPABILITY_USB4            BIT(3)
+#define VDO_UFP1_CAPABILITY_USB32 BIT(2)
+#define VDO_UFP1_CAPABILITY_USB4 BIT(3)
 /*****************************************************************************/
 /*
  * Table 6-37 DFP VDO
@@ -170,15 +170,13 @@ struct product_vdo {
  * <4:0>   : Port number
  */
 /* DFP VDO Version 1.1; update the value when DFP VDO version changes */
-#define VDO_DFP(cap, ctype, port)			\
-	((0x1) << 29 | ((cap) & 0x7) << 24	\
-	| ((ctype) & 0x3) << 22 | ((port) & 0x1f))
+#define VDO_DFP(cap, ctype, port) \
+	((0x1) << 29 | ((cap)&0x7) << 24 | ((ctype)&0x3) << 22 | ((port)&0x1f))
 
 /* DFP VDO Host Capability */
 #define VDO_DFP_HOST_CAPABILITY_USB20 BIT(0)
 #define VDO_DFP_HOST_CAPABILITY_USB32 BIT(1)
-#define VDO_DFP_HOST_CAPABILITY_USB4  BIT(2)
-
+#define VDO_DFP_HOST_CAPABILITY_USB4 BIT(2)
 
 /*****************************************************************************/
 /*
@@ -246,6 +244,19 @@ struct product_vdo {
  * Table 5-1 Certified Cables Where USB4-compatible Operation is Expected
  * This table lists the USB-C cables those support USB4
  */
+enum usb_rev30_plug {
+	USB_REV30_TYPE_C = 2,
+	USB_REV30_CAPTIVE = 3,
+};
+
+enum usb_rev30_latency {
+	USB_REV30_LATENCY_1m = 1,
+	USB_REV30_LATENCY_2m = 2,
+	USB_REV30_LATENCY_3m = 3,
+	USB_REV30_LATENCY_4m = 4,
+	USB_REV30_LATENCY_5m = 5,
+	USB_REV30_LATENCY_6m = 6,
+};
 
 enum usb_rev30_ss {
 	USB_R30_SS_U2_ONLY,
@@ -267,7 +278,7 @@ enum usb_vbus_cur {
 
 union passive_cable_vdo_rev30 {
 	struct {
-		enum usb_rev30_ss ss: 3;
+		enum usb_rev30_ss ss : 3;
 		uint32_t reserved0 : 2;
 		enum usb_vbus_cur vbus_cur : 2;
 		uint32_t reserved1 : 2;
@@ -284,6 +295,11 @@ union passive_cable_vdo_rev30 {
 	uint32_t raw_value;
 };
 
+/* Macro passive VDO generator */
+#define VDO_REV30_PASSIVE(ss, vbus_cur, latency, plug)                \
+	((ss & 0x7) | (vbus_cur & 0x3) << 5 | (latency & 0xf) << 13 | \
+	 (plug & 0x3) << 18)
+
 /*****************************************************************************/
 /*
  * Table 6-39 Active Cable VDO 1
@@ -355,7 +371,7 @@ enum vdo_version {
 
 union active_cable_vdo1_rev30 {
 	struct {
-		enum usb_rev30_ss ss: 3;
+		enum usb_rev30_ss ss : 3;
 		uint32_t sop_p_p : 1;
 		uint32_t vbus_cable : 1;
 		enum usb_vbus_cur vbus_cur : 2;
@@ -541,17 +557,11 @@ union active_cable_vdo2_rev30 {
  *           1b – the VPD supports Charge Through
  *           0b – the VPD does not support Charge Through
  */
-#define VDO_VPD(hw, fw, vbus, ctc, vbusz, gndz, cts)  \
-	(((hw) & 0xf) << 28 | ((fw) & 0xf) << 24 \
-	 | ((vbus) & 0x3) << 15                  \
-	 | ((ctc) & 0x1) << 14			 \
-	 | ((vbusz) & 0x3f) << 7                 \
-	 | ((gndz) & 0x3f) << 1 | (cts))
-
-enum vpd_ctc_support {
-	VPD_CT_CURRENT_3A,
-	VPD_CT_CURRENT_5A
-};
+#define VDO_VPD(hw, fw, vbus, ctc, vbusz, gndz, cts)                \
+	(((hw)&0xf) << 28 | ((fw)&0xf) << 24 | ((vbus)&0x3) << 15 | \
+	 ((ctc)&0x1) << 14 | ((vbusz)&0x3f) << 7 | ((gndz)&0x3f) << 1 | (cts))
+
+enum vpd_ctc_support { VPD_CT_CURRENT_3A, VPD_CT_CURRENT_5A };
 
 enum vpd_vbus {
 	VPD_MAX_VBUS_20V,
@@ -566,12 +576,12 @@ enum vpd_cts_support {
 };
 
 #define VPD_VDO_MAX_VBUS(vdo) (((vdo) >> 15) & 0x3)
-#define VPD_VDO_CURRENT(vdo)  (((vdo) >> 14) & 1)
+#define VPD_VDO_CURRENT(vdo) (((vdo) >> 14) & 1)
 #define VPD_VDO_VBUS_IMP(vdo) (((vdo) >> 7) & 0x3f)
-#define VPD_VDO_GND_IMP(vdo)  (((vdo) >> 1) & 0x3f)
-#define VPD_VDO_CTS(vdo)      ((vdo) & 1)
-#define VPD_VBUS_IMP(mo)      ((mo + 1) >> 1)
-#define VPD_GND_IMP(mo)       (mo)
+#define VPD_VDO_GND_IMP(vdo) (((vdo) >> 1) & 0x3f)
+#define VPD_VDO_CTS(vdo) ((vdo)&1)
+#define VPD_VBUS_IMP(mo) ((mo + 1) >> 1)
+#define VPD_GND_IMP(mo) (mo)
 
 /*
  * ############################################################################
@@ -625,11 +635,10 @@ enum idh_ptype {
  * - Table 6-29 ID Header VDO PD spec 3.0 version 2.0 and
  * - Table 6-23 ID Header VDO PD spec 2.0 version 1.3.
  */
-#define IS_PD_IDH_UFP_PTYPE(ptype) (ptype == IDH_PTYPE_HUB || \
-				    ptype == IDH_PTYPE_PERIPH || \
-				    ptype == IDH_PTYPE_PSD || \
-				    ptype == IDH_PTYPE_AMA ||  \
-				    ptype == IDH_PTYPE_VPD)
+#define IS_PD_IDH_UFP_PTYPE(ptype)                              \
+	(ptype == IDH_PTYPE_HUB || ptype == IDH_PTYPE_PERIPH || \
+	 ptype == IDH_PTYPE_PSD || ptype == IDH_PTYPE_AMA ||    \
+	 ptype == IDH_PTYPE_VPD)
 
 struct id_header_vdo_rev20 {
 	uint16_t usb_vendor_id;
@@ -715,7 +724,7 @@ enum usb_rev20_ss {
 
 union passive_cable_vdo_rev20 {
 	struct {
-		enum usb_rev20_ss ss: 3;
+		enum usb_rev20_ss ss : 3;
 		uint32_t reserved0 : 1;
 		uint32_t vbus_cable : 1;
 		enum usb_vbus_cur vbus_cur : 2;
@@ -798,7 +807,7 @@ union passive_cable_vdo_rev20 {
  */
 union active_cable_vdo_rev20 {
 	struct {
-		enum usb_rev20_ss ss: 3;
+		enum usb_rev20_ss ss : 3;
 		uint32_t sop_p_p : 1;
 		uint32_t vbus_cable : 1;
 		enum usb_vbus_cur vbus_cur : 2;
@@ -866,14 +875,13 @@ union active_cable_vdo_rev20 {
  *           011b = [USB 2.0] billboard only
  *           100b..111b = Reserved, Shall Not be used
  */
-#define VDO_AMA(hw, fw, tx1d, tx2d, rx1d, rx2d, vcpwr, vcr, vbr, usbss) \
-	(((hw) & 0x7) << 28 | ((fw) & 0x7) << 24			\
-	 | (tx1d) << 11 | (tx2d) << 10 | (rx1d) << 9 | (rx2d) << 8	\
-	 | ((vcpwr) & 0x3) << 5 | (vcr) << 4 | (vbr) << 3		\
-	 | ((usbss) & 0x7))
+#define VDO_AMA(hw, fw, tx1d, tx2d, rx1d, rx2d, vcpwr, vcr, vbr, usbss)      \
+	(((hw)&0x7) << 28 | ((fw)&0x7) << 24 | (tx1d) << 11 | (tx2d) << 10 | \
+	 (rx1d) << 9 | (rx2d) << 8 | ((vcpwr)&0x3) << 5 | (vcr) << 4 |       \
+	 (vbr) << 3 | ((usbss)&0x7))
 
 #define PD_VDO_AMA_VCONN_REQ(vdo) (((vdo) >> 4) & 1)
-#define PD_VDO_AMA_VBUS_REQ(vdo)  (((vdo) >> 3) & 1)
+#define PD_VDO_AMA_VBUS_REQ(vdo) (((vdo) >> 3) & 1)
 
 enum ama_usb_ss {
 	AMA_USBSS_U2_ONLY,
diff --git a/include/usb_pe_sm.h b/include/usb_pe_sm.h
index 4018f16322..a2e2a0f951 100644
--- a/include/usb_pe_sm.h
+++ b/include/usb_pe_sm.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/usb_prl_sm.h b/include/usb_prl_sm.h
index 6607bd2824..99b69f156f 100644
--- a/include/usb_prl_sm.h
+++ b/include/usb_prl_sm.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -80,8 +80,7 @@ void prl_run(int port, int evt, int en);
  * @param type port address
  * @param rev revision
  */
-void prl_set_rev(int port, enum tcpci_msg_type type,
-					enum pd_rev_type rev);
+void prl_set_rev(int port, enum tcpci_msg_type type, enum pd_rev_type rev);
 
 /**
  * Get the PD revision
@@ -93,6 +92,15 @@ void prl_set_rev(int port, enum tcpci_msg_type type,
 enum pd_rev_type prl_get_rev(int port, enum tcpci_msg_type type);
 
 /**
+ * Reset Tx and Rx message IDs for the specified partner to their initial
+ * values.
+ *
+ * @param port USB-C port number
+ * @param type Transmit type
+ */
+void prl_reset_msg_ids(int port, enum tcpci_msg_type type);
+
+/**
  * Sends a PD control message
  *
  * @param port USB-C port number
@@ -100,7 +108,7 @@ enum pd_rev_type prl_get_rev(int port, enum tcpci_msg_type type);
  * @param msg  Control message type
  */
 void prl_send_ctrl_msg(int port, enum tcpci_msg_type type,
-	enum pd_ctrl_msg_type msg);
+		       enum pd_ctrl_msg_type msg);
 
 /**
  * Sends a PD data message
@@ -110,7 +118,7 @@ void prl_send_ctrl_msg(int port, enum tcpci_msg_type type,
  * @param msg  Data message type
  */
 void prl_send_data_msg(int port, enum tcpci_msg_type type,
-	enum pd_data_msg_type msg);
+		       enum pd_data_msg_type msg);
 
 /**
  * Sends a PD extended data message
@@ -120,7 +128,7 @@ void prl_send_data_msg(int port, enum tcpci_msg_type type,
  * @param msg  Extended data message type
  */
 void prl_send_ext_data_msg(int port, enum tcpci_msg_type type,
-	enum pd_ext_msg_type msg);
+			   enum pd_ext_msg_type msg);
 
 /**
  * Informs the Protocol Layer that a hard reset has completed
diff --git a/include/usb_sm.h b/include/usb_sm.h
index 2b5939bc04..d945ebd0ac 100644
--- a/include/usb_sm.h
+++ b/include/usb_sm.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,7 +8,7 @@
 #ifndef __CROS_EC_USB_SM_H
 #define __CROS_EC_USB_SM_H
 
-#include "compiler.h"	/* for typeof() on Zephyr */
+#include "compiler.h" /* for typeof() on Zephyr */
 
 /* Function pointer that implements a portion of a usb state */
 typedef void (*state_execution)(const int port);
@@ -101,13 +101,13 @@ struct test_sm_data {
 	/* Size fo the state machine array above */
 	const int size;
 	/* The array of names for states, can be NULL */
-	const char * const * const names;
+	const char *const *const names;
 	/* The size of the above names array */
 	const int names_size;
 };
 #endif
 
 /* Creates a state machine state that will never link. Useful with IS_ENABLED */
-#define GEN_NOT_SUPPORTED(state) extern typeof(state) state ## _NOT_SUPPORTED
+#define GEN_NOT_SUPPORTED(state) extern typeof(state) state##_NOT_SUPPORTED
 
 #endif /* __CROS_EC_USB_SM_H */
diff --git a/include/usb_tbt_alt_mode.h b/include/usb_tbt_alt_mode.h
index a187c1b42b..378cd0ccce 100644
--- a/include/usb_tbt_alt_mode.h
+++ b/include/usb_tbt_alt_mode.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -78,7 +78,7 @@ bool tbt_is_active(int port);
  * @param vdm       VDM from ACK
  */
 void intel_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count,
-		uint32_t *vdm);
+		     uint32_t *vdm);
 
 /*
  * Handles NAKed (or Not Supported or timed out) Thunderbolt VDM requests.
diff --git a/include/usb_tc_sm.h b/include/usb_tc_sm.h
index 4aaacd522b..ec6473edfd 100644
--- a/include/usb_tc_sm.h
+++ b/include/usb_tc_sm.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,7 +24,7 @@ enum try_src_override_t {
  * This is the maximum voltage a sink can request
  * while charging.
  */
-#define TYPE_C_VOLTAGE  5000 /* mV */
+#define TYPE_C_VOLTAGE 5000 /* mV */
 
 /*
  * Type C default sink current (mA)
@@ -32,7 +32,7 @@ enum try_src_override_t {
  * This is the maximum current a sink can draw if charging
  * while in the Audio Accessory State.
  */
-#define TYPE_C_AUDIO_ACC_CURRENT  500 /* mA */
+#define TYPE_C_AUDIO_ACC_CURRENT 500 /* mA */
 
 /**
  * Returns true if TypeC State machine is in attached source state.
@@ -256,7 +256,7 @@ void pd_request_vconn_swap_off(int port);
  * @return 0 if cc1 is connected, else 1 for cc2
  */
 enum tcpc_cc_polarity get_snk_polarity(enum tcpc_cc_voltage_status cc1,
-	enum tcpc_cc_voltage_status cc2);
+				       enum tcpc_cc_voltage_status cc2);
 
 /**
  * Called by the state machine framework to initialize the
diff --git a/include/usbc_ocp.h b/include/usbc_ocp.h
index d31ce57724..6c1d641931 100644
--- a/include/usbc_ocp.h
+++ b/include/usbc_ocp.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,8 +6,33 @@
 #ifndef __CROS_EC_USBC_OCP_H
 #define __CROS_EC_USBC_OCP_H
 
+#include "common.h"
+
 /* Common APIs for USB Type-C Overcurrent Protection (OCP) Module */
 
+/*
+ * PD 3.1 Ver 1.3 7.1.7.1 Output Over Current Protection
+ *
+ * "After three consecutive over current events Source Shall go to
+ * ErrorRecovery.
+ *
+ * Sources Should attempt to send a Hard Reset message when over
+ * current protection engages followed by an Alert Message indicating
+ * an OCP event once an Explicit Contract has been established.
+ *
+ * The Source Shall prevent continual system or port cycling if over
+ * current protection continues to engage after initially resuming
+ * either default operation or renegotiation. Latching off the port or
+ * system is an acceptable response to recurring over current."
+ *
+ * Our policy will be first two OCPs -> hard reset
+ * 3rd -> ErrorRecovery
+ * 4th -> port latched off
+ */
+#define OCP_HR_CNT 2
+
+#define OCP_MAX_CNT 4
+
 /**
  * Increment the overcurrent event counter.
  *
diff --git a/include/usbc_ppc.h b/include/usbc_ppc.h
index 5377f922ed..09d7107faf 100644
--- a/include/usbc_ppc.h
+++ b/include/usbc_ppc.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/include/util.h b/include/util.h
index e39b81ccdf..dc2e038705 100644
--- a/include/util.h
+++ b/include/util.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,13 +10,19 @@
 
 #include "common.h"
 #include "compile_time_macros.h"
-#include "panic.h"
 
-#include "builtin/assert.h"         /* For ASSERT(). */
+#include <ctype.h>
 #include <stdbool.h>
 #include <stddef.h>
+#include <stdlib.h>
+#include <string.h>
+#include <strings.h>
 #ifdef CONFIG_ZEPHYR
 #include <zephyr/sys/util.h>
+/**
+ * TODO(b/237712836): Remove once Zephyr's libc has strcasecmp.
+ */
+#include "builtin/strings.h"
 #endif
 
 #ifdef __cplusplus
@@ -27,21 +33,21 @@ extern "C" {
 #define GENERIC_MAX(x, y) ((x) > (y) ? (x) : (y))
 #define GENERIC_MIN(x, y) ((x) < (y) ? (x) : (y))
 #ifndef MAX
-#define MAX(a, b)					\
-	({						\
-		__typeof__(a) temp_a = (a);		\
-		__typeof__(b) temp_b = (b);		\
-							\
-		GENERIC_MAX(temp_a, temp_b);		\
+#define MAX(a, b)                            \
+	({                                   \
+		__typeof__(a) temp_a = (a);  \
+		__typeof__(b) temp_b = (b);  \
+                                             \
+		GENERIC_MAX(temp_a, temp_b); \
 	})
 #endif
 #ifndef MIN
-#define MIN(a, b)					\
-	({						\
-		__typeof__(a) temp_a = (a);		\
-		__typeof__(b) temp_b = (b);		\
-							\
-		GENERIC_MIN(temp_a, temp_b);		\
+#define MIN(a, b)                            \
+	({                                   \
+		__typeof__(a) temp_a = (a);  \
+		__typeof__(b) temp_b = (b);  \
+                                             \
+		GENERIC_MIN(temp_a, temp_b); \
 	})
 #endif
 #ifndef NULL
@@ -69,11 +75,11 @@ extern "C" {
  * contains the base struct.  This requires knowing where in the contained
  * struct the base struct resides, this is the member parameter to downcast.
  */
-#define DOWNCAST(pointer, type, member)					\
-	((type *)(((uint8_t *) pointer) - offsetof(type, member)))
+#define DOWNCAST(pointer, type, member) \
+	((type *)(((uint8_t *)pointer) - offsetof(type, member)))
 
 /* True of x is a power of two */
-#define POWER_OF_TWO(x) ((x) && !((x) & ((x) - 1)))
+#define POWER_OF_TWO(x) ((x) && !((x) & ((x)-1)))
 
 /* Macro to check if the value is in range */
 #ifndef CONFIG_ZEPHYR
@@ -84,7 +90,7 @@ extern "C" {
  * macros for integer division with various rounding variants
  * default integer division rounds down.
  */
-#define DIV_ROUND_UP(x, y) (((x) + ((y) - 1)) / (y))
+#define DIV_ROUND_UP(x, y) (((x) + ((y)-1)) / (y))
 #define DIV_ROUND_NEAREST(x, y) (((x) + ((y) / 2)) / (y))
 
 /*
@@ -93,60 +99,14 @@ extern "C" {
  * Swapping composites (e.g. a+b, x++) doesn't make sense. So, <a> and <b>
  * can only be a variable (x) or a pointer reference (*x) without operator.
  */
-#define swap(a, b) \
-	do { \
+#define swap(a, b)               \
+	do {                     \
 		typeof(a) __t__; \
-		__t__ = a; \
-		a = b; \
-		b = __t__; \
+		__t__ = a;       \
+		a = b;           \
+		b = __t__;       \
 	} while (0)
 
-#ifndef HIDE_EC_STDLIB
-
-/* Standard library functions */
-int atoi(const char *nptr);
-
-#ifdef CONFIG_ZEPHYR
-#include <ctype.h>
-#include <string.h>
-#else
-int isdigit(int c);
-int isspace(int c);
-int isalpha(int c);
-int isupper(int c);
-int isprint(int c);
-int tolower(int c);
-
-int memcmp(const void *s1, const void *s2, size_t len);
-void *memcpy(void *dest, const void *src, size_t len);
-void *memset(void *dest, int c, size_t len);
-void *memmove(void *dest, const void *src, size_t len);
-void *memchr(const void *buffer, int c, size_t n);
-
-/**
- * Find the first occurrence of the substring <s2> in the string <s1>
- *
- * @param s1	String where <s2> is searched.
- * @param s2	Substring to be located in <s1>
- * @return	Pointer to the located substring or NULL if not found.
- */
-char *strstr(const char *s1, const char *s2);
-
-/**
- * Calculates the length of the initial segment of s which consists
- * entirely of bytes not in reject.
- */
-size_t strcspn(const char *s, const char *reject);
-
-size_t strlen(const char *s);
-char *strncpy(char *dest, const char *src, size_t n);
-int strncmp(const char *s1, const char *s2, size_t n);
-#endif
-
-int strcasecmp(const char *s1, const char *s2);
-int strncasecmp(const char *s1, const char *s2, size_t size);
-size_t strnlen(const char *s, size_t maxlen);
-
 /* Like strtol(), but for integers. */
 int strtoi(const char *nptr, char **endptr, int base);
 
@@ -173,7 +133,6 @@ char *strzcpy(char *dest, const char *src, int len);
  * Other strings return 0 and leave *dest unchanged.
  */
 int parse_bool(const char *s, int *dest);
-#endif  /* !HIDE_EC_STDLIB */
 
 /**
  * Constant time implementation of memcmp to avoid timing side channels.
@@ -234,7 +193,7 @@ int alignment_log2(unsigned int x);
  */
 void reverse(void *dest, size_t len);
 
-
+int find_base(int base, int *c, const char **nptr);
 /****************************************************************************/
 /* Conditional stuff.
  *
@@ -261,25 +220,49 @@ typedef uint8_t cond_t;
 
 /* Initialize a conditional to a specific state. Do this first. */
 void cond_init(cond_t *c, int boolean);
-static inline void cond_init_false(cond_t *c) { cond_init(c, 0); }
-static inline void cond_init_true(cond_t *c) { cond_init(c, 1); }
+static inline void cond_init_false(cond_t *c)
+{
+	cond_init(c, 0);
+}
+static inline void cond_init_true(cond_t *c)
+{
+	cond_init(c, 1);
+}
 
 /* Set the current state. Do this as often as you like. */
 void cond_set(cond_t *c, int boolean);
-static inline void cond_set_false(cond_t *c) { cond_set(c, 0); }
-static inline void cond_set_true(cond_t *c) { cond_set(c, 1); }
+static inline void cond_set_false(cond_t *c)
+{
+	cond_set(c, 0);
+}
+static inline void cond_set_true(cond_t *c)
+{
+	cond_set(c, 1);
+}
 
 /* Get the current state. Do this as often as you like. */
 int cond_is(cond_t *c, int boolean);
-static inline int cond_is_false(cond_t *c) { return cond_is(c, 0); }
-static inline int cond_is_true(cond_t *c) { return cond_is(c, 1); }
+static inline int cond_is_false(cond_t *c)
+{
+	return cond_is(c, 0);
+}
+static inline int cond_is_true(cond_t *c)
+{
+	return cond_is(c, 1);
+}
 
 /* See if the state has transitioned. If it has, the corresponding function
  * will return true ONCE only, until it's changed back.
  */
 int cond_went(cond_t *c, int boolean);
-static inline int cond_went_false(cond_t *c) { return cond_went(c, 0); }
-static inline int cond_went_true(cond_t *c) { return cond_went(c, 1); }
+static inline int cond_went_false(cond_t *c)
+{
+	return cond_went(c, 0);
+}
+static inline int cond_went_true(cond_t *c)
+{
+	return cond_went(c, 1);
+}
 
 /****************************************************************************/
 /* Console command parsing */
@@ -287,8 +270,8 @@ static inline int cond_went_true(cond_t *c) { return cond_went(c, 1); }
 /* Parse command-line arguments given integer shift value to obtain
  * offset and size.
  */
-int parse_offset_size(int argc, char **argv, int shift,
-			     int *offset, int *size);
+int parse_offset_size(int argc, const char **argv, int shift, int *offset,
+		      int *size);
 
 /**
  * Print binary in hex and ASCII
@@ -396,4 +379,4 @@ int ternary_from_bits(int *bits, int nbits);
 }
 #endif
 
-#endif  /* __CROS_EC_UTIL_H */
+#endif /* __CROS_EC_UTIL_H */
diff --git a/include/vb21_struct.h b/include/vb21_struct.h
index 74d0ea3ad2..c8b49ac05e 100644
--- a/include/vb21_struct.h
+++ b/include/vb21_struct.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -28,25 +28,24 @@
  */
 enum vb21_struct_common_magic {
 	/* "Vb2B" = vb21_keyblock.c.magic */
-	VB21_MAGIC_KEYBLOCK		= 0x42326256,
+	VB21_MAGIC_KEYBLOCK = 0x42326256,
 
 	/* "Vb2F" = vb21_fw_preamble.c.magic */
-	VB21_MAGIC_FW_PREAMBLE		= 0x46326256,
+	VB21_MAGIC_FW_PREAMBLE = 0x46326256,
 
 	/* "Vb2I" = vb21_packed_private_key.c.magic */
-	VB21_MAGIC_PACKED_PRIVATE_KEY	= 0x49326256,
+	VB21_MAGIC_PACKED_PRIVATE_KEY = 0x49326256,
 
 	/* "Vb2K" = vb2_kernel_preamble.c.magic */
-	VB21_MAGIC_KERNEL_PREAMBLE	= 0x4b326256,
+	VB21_MAGIC_KERNEL_PREAMBLE = 0x4b326256,
 
 	/* "Vb2P" = vb21_packed_key.c.magic */
-	VB21_MAGIC_PACKED_KEY		= 0x50326256,
+	VB21_MAGIC_PACKED_KEY = 0x50326256,
 
 	/* "Vb2S" = vb21_signature.c.magic */
-	VB21_MAGIC_SIGNATURE		= 0x53326256,
+	VB21_MAGIC_SIGNATURE = 0x53326256,
 };
 
-
 /*
  * Generic struct header for all vboot2.1 structs.  This makes it easy to
  * automatically parse and identify vboot structs (e.g., in futility).  This
@@ -145,7 +144,7 @@ struct vb21_packed_key {
 	struct vb2_id id;
 } __attribute__((packed));
 
-#define EXPECTED_VB21_PACKED_KEY_SIZE					\
+#define EXPECTED_VB21_PACKED_KEY_SIZE \
 	(EXPECTED_VB21_STRUCT_COMMON_SIZE + 16 + EXPECTED_ID_SIZE)
 
 /* Current version of vb21_packed_private_key struct */
@@ -184,7 +183,7 @@ struct vb21_packed_private_key {
 	struct vb2_id id;
 } __attribute__((packed));
 
-#define EXPECTED_VB21_PACKED_PRIVATE_KEY_SIZE				\
+#define EXPECTED_VB21_PACKED_PRIVATE_KEY_SIZE \
 	(EXPECTED_VB21_STRUCT_COMMON_SIZE + 12 + EXPECTED_ID_SIZE)
 
 /* Current version of vb21_signature struct */
@@ -232,10 +231,9 @@ struct vb21_signature {
 	struct vb2_id id;
 } __attribute__((packed));
 
-#define EXPECTED_VB21_SIGNATURE_SIZE					\
+#define EXPECTED_VB21_SIGNATURE_SIZE \
 	(EXPECTED_VB21_STRUCT_COMMON_SIZE + 16 + EXPECTED_ID_SIZE)
 
-
 /* Current version of vb21_keyblock struct */
 #define VB21_KEYBLOCK_VERSION_MAJOR 3
 #define VB21_KEYBLOCK_VERSION_MINOR 0
@@ -290,7 +288,6 @@ struct vb21_keyblock {
 
 #define EXPECTED_VB21_KEYBLOCK_SIZE (EXPECTED_VB21_STRUCT_COMMON_SIZE + 16)
 
-
 /* Current version of vb21_fw_preamble struct */
 #define VB21_FW_PREAMBLE_VERSION_MAJOR 3
 #define VB21_FW_PREAMBLE_VERSION_MINOR 0
@@ -343,4 +340,4 @@ struct vb21_fw_preamble {
 
 #define EXPECTED_VB21_FW_PREAMBLE_SIZE (EXPECTED_VB21_STRUCT_COMMON_SIZE + 20)
 
-#endif  /* VBOOT_REFERENCE_VB21_STRUCT_H_ */
+#endif /* VBOOT_REFERENCE_VB21_STRUCT_H_ */
diff --git a/include/vboot.h b/include/vboot.h
index 52ccae6e90..55359e8044 100644
--- a/include/vboot.h
+++ b/include/vboot.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -31,7 +31,6 @@ int vb21_is_packed_key_valid(const struct vb21_packed_key *key);
 int vb21_is_signature_valid(const struct vb21_signature *sig,
 			    const struct vb21_packed_key *key);
 
-
 /**
  * Returns the public key in RO that was used to sign RW.
  *
@@ -58,8 +57,8 @@ int vboot_is_padding_valid(const uint8_t *data, uint32_t start, uint32_t end);
  * @param sig  Signature of <data>
  * @return EC_SUCCESS or EC_ERROR_*
  */
-int vboot_verify(const uint8_t *data, int len,
-		 const struct rsa_public_key *key, const uint8_t *sig);
+int vboot_verify(const uint8_t *data, int len, const struct rsa_public_key *key,
+		 const uint8_t *sig);
 
 /**
  * Entry point of EC EFS
@@ -100,19 +99,19 @@ __override_proto void board_enable_packet_mode(bool enable);
 void packet_mode_interrupt(enum gpio_signal signal);
 
 /* Maximum number of times EC retries packet transmission before giving up. */
-#define CR50_COMM_MAX_RETRY	5
+#define CR50_COMM_MAX_RETRY 5
 
 /* EC's timeout for packet transmission to Cr50. */
-#define CR50_COMM_TIMEOUT	(50 * MSEC)
+#define CR50_COMM_TIMEOUT (50 * MSEC)
 
 /* Preamble character repeated before the packet header starts. */
-#define CR50_COMM_PREAMBLE	0xec
+#define CR50_COMM_PREAMBLE 0xec
 
 /* Magic characters used to identify ec-cr50-comm packets */
-#define CR50_PACKET_MAGIC	0x4345	/* 'EC' in little endian */
+#define CR50_PACKET_MAGIC 0x4345 /* 'EC' in little endian */
 
 /* version of struct cr50_comm_request */
-#define CR50_COMM_PACKET_VERSION	(0 << 4 | 0 << 0)	/* 0.0 */
+#define CR50_COMM_PACKET_VERSION (0 << 4 | 0 << 0) /* 0.0 */
 
 /**
  * EC-Cr50 data frame looks like the following:
@@ -125,11 +124,11 @@ void packet_mode_interrupt(enum gpio_signal signal);
  */
 struct cr50_comm_request {
 	/* Header */
-	uint16_t magic;		/* CR50_PACKET_MAGIC */
-	uint8_t struct_version;	/* version of this struct msb:lsb=major:minor */
-	uint8_t crc;		/* checksum computed from all bytes after crc */
-	uint16_t type;		/* CR50_CMD_* */
-	uint8_t size;		/* Payload size. Be easy on Cr50 buffer. */
+	uint16_t magic; /* CR50_PACKET_MAGIC */
+	uint8_t struct_version; /* version of this struct msb:lsb=major:minor */
+	uint8_t crc; /* checksum computed from all bytes after crc */
+	uint16_t type; /* CR50_CMD_* */
+	uint8_t size; /* Payload size. Be easy on Cr50 buffer. */
 	/* Payload */
 	uint8_t data[];
 } __packed;
@@ -138,33 +137,33 @@ struct cr50_comm_response {
 	uint16_t error;
 } __packed;
 
-#define CR50_COMM_MAX_REQUEST_SIZE	(sizeof(struct cr50_comm_request) \
-					 + UINT8_MAX)
-#define CR50_UART_RX_BUFFER_SIZE	32	/* TODO: Get from Cr50 header */
+#define CR50_COMM_MAX_REQUEST_SIZE \
+	(sizeof(struct cr50_comm_request) + UINT8_MAX)
+#define CR50_UART_RX_BUFFER_SIZE 32 /* TODO: Get from Cr50 header */
 
 /* commands */
 enum cr50_comm_cmd {
-	CR50_COMM_CMD_HELLO =		0x0000,
-	CR50_COMM_CMD_SET_BOOT_MODE =	0x0001,
-	CR50_COMM_CMD_VERIFY_HASH =	0x0002,
-	CR50_COMM_CMD_LIMIT =		0xffff,
+	CR50_COMM_CMD_HELLO = 0x0000,
+	CR50_COMM_CMD_SET_BOOT_MODE = 0x0001,
+	CR50_COMM_CMD_VERIFY_HASH = 0x0002,
+	CR50_COMM_CMD_LIMIT = 0xffff,
 } __packed;
 BUILD_ASSERT(sizeof(enum cr50_comm_cmd) == sizeof(uint16_t));
 
-#define CR50_COMM_ERR_PREFIX		0xec
+#define CR50_COMM_ERR_PREFIX 0xec
 
 /* return code */
 enum cr50_comm_err {
-	CR50_COMM_SUCCESS =		0xec00,
-	CR50_COMM_ERR_UNKNOWN =		0xec01,
-	CR50_COMM_ERR_MAGIC =		0xec02,
-	CR50_COMM_ERR_CRC =		0xec03,
-	CR50_COMM_ERR_SIZE =		0xec04,
-	CR50_COMM_ERR_TIMEOUT =		0xec05,	/* Generated by EC */
-	CR50_COMM_ERR_UNDEFINED_CMD =	0xec06,
-	CR50_COMM_ERR_BAD_PAYLOAD =	0xec07,
-	CR50_COMM_ERR_STRUCT_VERSION =	0xec08,
-	CR50_COMM_ERR_NVMEM =		0xec09,
+	CR50_COMM_SUCCESS = 0xec00,
+	CR50_COMM_ERR_UNKNOWN = 0xec01,
+	CR50_COMM_ERR_MAGIC = 0xec02,
+	CR50_COMM_ERR_CRC = 0xec03,
+	CR50_COMM_ERR_SIZE = 0xec04,
+	CR50_COMM_ERR_TIMEOUT = 0xec05, /* Generated by EC */
+	CR50_COMM_ERR_UNDEFINED_CMD = 0xec06,
+	CR50_COMM_ERR_BAD_PAYLOAD = 0xec07,
+	CR50_COMM_ERR_STRUCT_VERSION = 0xec08,
+	CR50_COMM_ERR_NVMEM = 0xec09,
 } __packed;
 BUILD_ASSERT(sizeof(enum cr50_comm_err) == sizeof(uint16_t));
 
@@ -173,8 +172,8 @@ BUILD_ASSERT(sizeof(enum cr50_comm_err) == sizeof(uint16_t));
  * BIT(0) : RECOVERY flag
  */
 enum boot_mode {
-	BOOT_MODE_NORMAL           = 0x00,
-	BOOT_MODE_NO_BOOT          = 0x01,
+	BOOT_MODE_NORMAL = 0x00,
+	BOOT_MODE_NO_BOOT = 0x01,
 } __packed;
 BUILD_ASSERT(sizeof(enum boot_mode) == sizeof(uint8_t));
 
@@ -187,4 +186,11 @@ BUILD_ASSERT(sizeof(enum boot_mode) == sizeof(uint8_t));
  */
 __override_proto bool vboot_allow_usb_pd(void);
 
-#endif  /* __CROS_EC_INCLUDE_VBOOT_H */
+#ifdef TEST_BUILD
+/**
+ * Set the vboot_allow_usb_pd flag to false.
+ */
+__test_only void vboot_disable_pd(void);
+#endif
+
+#endif /* __CROS_EC_INCLUDE_VBOOT_H */
diff --git a/include/vboot_hash.h b/include/vboot_hash.h
index 126872393e..980a07df0b 100644
--- a/include/vboot_hash.h
+++ b/include/vboot_hash.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -49,4 +49,4 @@ int vboot_hash_in_progress(void);
  */
 void vboot_hash_abort(void);
 
-#endif  /* __CROS_EC_VBOOT_HASH_H */
+#endif /* __CROS_EC_VBOOT_HASH_H */
diff --git a/include/vec3.h b/include/vec3.h
index e7fcf92041..ebdb358cc1 100644
--- a/include/vec3.h
+++ b/include/vec3.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -80,4 +80,4 @@ fp_t fpv3_norm_squared(const fpv3_t v);
  */
 fp_t fpv3_norm(const fpv3_t v);
 
-#endif  /* __CROS_EC_VEC_3_H */
+#endif /* __CROS_EC_VEC_3_H */
diff --git a/include/vec4.h b/include/vec4.h
index f1724d955e..e951c0542f 100644
--- a/include/vec4.h
+++ b/include/vec4.h
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,4 +12,4 @@
 typedef float floatv4_t[4];
 typedef fp_t fpv4_t[4];
 
-#endif  /* __CROS_EC_VEC_4_H */
+#endif /* __CROS_EC_VEC_4_H */
diff --git a/include/virtual_battery.h b/include/virtual_battery.h
index a5cac1140c..2bd171f43c 100644
--- a/include/virtual_battery.h
+++ b/include/virtual_battery.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,8 +6,8 @@
 #ifndef __CROS_EC_VIRTUAL_BATTERY_H
 #define __CROS_EC_VIRTUAL_BATTERY_H
 
-#if defined(CONFIG_I2C_VIRTUAL_BATTERY) && defined(CONFIG_BATTERY_SMART) \
-	&& !defined(VIRTUAL_BATTERY_ADDR_FLAGS)
+#if defined(CONFIG_I2C_VIRTUAL_BATTERY) && defined(CONFIG_BATTERY_SMART) && \
+	!defined(VIRTUAL_BATTERY_ADDR_FLAGS)
 #define VIRTUAL_BATTERY_ADDR_FLAGS BATTERY_ADDR_FLAGS
 #endif
 
@@ -21,10 +21,8 @@
  * @return EC_SUCCESS if successful, non-zero if error.
  *
  */
-int virtual_battery_operation(const uint8_t *batt_cmd_head,
-			      uint8_t *dest,
-			      int read_len,
-			      int write_len);
+int virtual_battery_operation(const uint8_t *batt_cmd_head, uint8_t *dest,
+			      int read_len, int write_len);
 
 /**
  * Parse a command for virtual battery function.
@@ -39,10 +37,9 @@ int virtual_battery_operation(const uint8_t *batt_cmd_head,
  * @param out		Data to send
  * @return EC_SUCCESS if successful, non-zero if error.
  */
-int virtual_battery_handler(struct ec_response_i2c_passthru *resp,
-				   int in_len, int *err_code, int xferflags,
-				   int read_len, int write_len,
-				   const uint8_t *out);
+int virtual_battery_handler(struct ec_response_i2c_passthru *resp, int in_len,
+			    int *err_code, int xferflags, int read_len,
+			    int write_len, const uint8_t *out);
 
 /* Reset the state machine and static variables. */
 void reset_parse_state(void);
diff --git a/include/vstore.h b/include/vstore.h
new file mode 100644
index 0000000000..692d0e3012
--- /dev/null
+++ b/include/vstore.h
@@ -0,0 +1,16 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_VSTORE_H
+#define __CROS_EC_VSTORE_H
+
+#ifdef TEST_BUILD
+
+/* Clear all vstore locks */
+void vstore_clear_lock(void);
+
+#endif /* TEST_BUILD */
+
+#endif /* __CROS_EC_VSTORE_H */
diff --git a/include/watchdog.h b/include/watchdog.h
index 036f722d97..9bfed9c192 100644
--- a/include/watchdog.h
+++ b/include/watchdog.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -49,7 +49,9 @@ void watchdog_stop_and_unlock(void);
 #ifdef CONFIG_WATCHDOG
 void watchdog_reload(void);
 #else
-static inline void watchdog_reload(void) { }
+static inline void watchdog_reload(void)
+{
+}
 #endif
 
 #endif /* __CROS_EC_WATCHDOG_H */
diff --git a/include/wireless.h b/include/wireless.h
index d209d69fed..7232f92763 100644
--- a/include/wireless.h
+++ b/include/wireless.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,11 +11,7 @@
 #include "common.h"
 
 /* Wireless power state for wireless_set_state() */
-enum wireless_power_state {
-	WIRELESS_OFF,
-	WIRELESS_SUSPEND,
-	WIRELESS_ON
-};
+enum wireless_power_state { WIRELESS_OFF, WIRELESS_SUSPEND, WIRELESS_ON };
 
 /**
  * Set wireless power state.
@@ -23,7 +19,9 @@ enum wireless_power_state {
 #ifdef CONFIG_WIRELESS
 void wireless_set_state(enum wireless_power_state state);
 #else
-static inline void wireless_set_state(enum wireless_power_state state) { }
+static inline void wireless_set_state(enum wireless_power_state state)
+{
+}
 #endif
 
-#endif  /* __CROS_EC_WIRELESS_H */
+#endif /* __CROS_EC_WIRELESS_H */
diff --git a/include/write_protect.h b/include/write_protect.h
index 019243dd61..8e09111974 100644
--- a/include/write_protect.h
+++ b/include/write_protect.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/power/alderlake_slg4bd44540.c b/power/alderlake_slg4bd44540.c
index 0f7b5cb3e4..d55ef61531 100644
--- a/power/alderlake_slg4bd44540.c
+++ b/power/alderlake_slg4bd44540.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,30 +24,29 @@
  */
 
 /* PG_EC_ALL_SYS_PWRGD high to VCCST_PWRGD high delay */
-#define VCCST_PWRGD_DELAY_MS	2
+#define VCCST_PWRGD_DELAY_MS 2
 
 /* IMVP9_VRRDY high to PCH_PWROK high delay */
-#define PCH_PWROK_DELAY_MS	2
+#define PCH_PWROK_DELAY_MS 2
 
 /* PG_EC_ALL_SYS_PWRGD high to EC_PCH_SYS_PWROK high delay */
-#define SYS_PWROK_DELAY_MS	45
+#define SYS_PWROK_DELAY_MS 45
 
 /* IMVP9_VRRDY high timeout */
-#define VRRDY_TIMEOUT_MS	50
+#define VRRDY_TIMEOUT_MS 50
 
 /* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 #ifdef CONFIG_BRINGUP
 #define GPIO_SET_LEVEL(signal, value) \
 	gpio_set_level_verbose(CC_CHIPSET, signal, value)
 #else
-#define GPIO_SET_LEVEL(signal, value) \
-	gpio_set_level(signal, value)
+#define GPIO_SET_LEVEL(signal, value) gpio_set_level(signal, value)
 #endif
 
 /* The wait time is ~150 msec, allow for safety margin. */
-#define IN_PCH_SLP_SUS_WAIT_TIME_USEC	(250 * MSEC)
+#define IN_PCH_SLP_SUS_WAIT_TIME_USEC (250 * MSEC)
 
 /* Power signals list. Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
@@ -250,7 +249,6 @@ enum power_state power_handle_state(enum power_state state)
 	common_intel_x86_handle_rsmrst(state);
 
 	switch (state) {
-
 	case POWER_G3S5:
 		GPIO_SET_LEVEL(GPIO_EN_S5_RAILS, 1);
 
@@ -262,7 +260,8 @@ enum power_state power_handle_state(enum power_state state)
 		 * signal doesn't go high within 250 msec then go back to G3.
 		 */
 		if (power_wait_signals_timeout(IN_PCH_SLP_SUS_DEASSERTED,
-				IN_PCH_SLP_SUS_WAIT_TIME_USEC) != EC_SUCCESS) {
+					       IN_PCH_SLP_SUS_WAIT_TIME_USEC) !=
+		    EC_SUCCESS) {
 			CPRINTS("SLP_SUS_L didn't go high!  Going back to G3.");
 			return POWER_S5G3;
 		}
diff --git a/power/amd_x86.c b/power/amd_x86.c
index 2a35849039..e5b44a313f 100644
--- a/power/amd_x86.c
+++ b/power/amd_x86.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,6 +13,7 @@
 #include "hooks.h"
 #include "lid_switch.h"
 #include "lpc.h"
+#include "power/amd_x86.h"
 #include "power.h"
 #include "power_button.h"
 #include "system.h"
@@ -231,8 +232,7 @@ static void lpc_s0ix_resume_restore_masks(void)
 	backup_sci_mask = backup_smi_mask = 0;
 }
 
-__override void power_chipset_handle_sleep_hang(
-		enum sleep_hang_type hang_type)
+__override void power_chipset_handle_sleep_hang(enum sleep_hang_type hang_type)
 {
 	/*
 	 * Wake up the AP so they don't just chill in a non-suspended state and
@@ -274,15 +274,15 @@ void power_reset_host_sleep_state(void)
 
 #ifdef CONFIG_POWER_TRACK_HOST_SLEEP_STATE
 
-__overridable void power_board_handle_host_sleep_event(
-		enum host_sleep_event state)
+__overridable void
+power_board_handle_host_sleep_event(enum host_sleep_event state)
 {
 	/* Default weak implementation -- no action required. */
 }
 
-__override void power_chipset_handle_host_sleep_event(
-		enum host_sleep_event state,
-		struct host_sleep_event_context *ctx)
+__override void
+power_chipset_handle_host_sleep_event(enum host_sleep_event state,
+				      struct host_sleep_event_context *ctx)
 {
 	power_board_handle_host_sleep_event(state);
 
@@ -301,7 +301,6 @@ __override void power_chipset_handle_host_sleep_event(
 		sleep_set_notify(SLEEP_NOTIFY_SUSPEND);
 
 		sleep_start_suspend(ctx);
-		power_signal_enable_interrupt(GPIO_PCH_SLP_S0_L);
 	} else if (state == HOST_SLEEP_EVENT_S0IX_RESUME) {
 		/*
 		 * Wake up chipset task and indicate to power state machine that
@@ -310,7 +309,6 @@ __override void power_chipset_handle_host_sleep_event(
 		sleep_set_notify(SLEEP_NOTIFY_RESUME);
 		task_wake(TASK_ID_CHIPSET);
 		lpc_s0ix_resume_restore_masks();
-		power_signal_disable_interrupt(GPIO_PCH_SLP_S0_L);
 		sleep_complete_resume(ctx);
 		/*
 		 * If the sleep signal timed out and never transitioned, then
@@ -319,8 +317,6 @@ __override void power_chipset_handle_host_sleep_event(
 		 * mask to its S0 state now.
 		 */
 		power_update_wake_mask();
-	} else if (state == HOST_SLEEP_EVENT_DEFAULT_RESET) {
-		power_signal_disable_interrupt(GPIO_PCH_SLP_S0_L);
 	}
 #endif /* CONFIG_POWER_S0IX */
 }
@@ -438,9 +434,9 @@ enum power_state power_handle_state(enum power_state state)
 		 * Ignore the SLP_S0 assertions in idle scenario by checking
 		 * the host sleep state.
 		 */
-		else if (power_get_host_sleep_state()
-					== HOST_SLEEP_EVENT_S0IX_SUSPEND &&
-				gpio_get_level(GPIO_PCH_SLP_S0_L) == 0) {
+		else if (power_get_host_sleep_state() ==
+				 HOST_SLEEP_EVENT_S0IX_SUSPEND &&
+			 gpio_get_level(GPIO_PCH_SLP_S0_L) == 0) {
 			return POWER_S0S0ix;
 		}
 #endif
diff --git a/power/apollolake.c b/power/apollolake.c
index 3bc03af626..20244abee9 100644
--- a/power/apollolake.c
+++ b/power/apollolake.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,7 +13,7 @@
 #include "timer.h"
 
 /* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 /*
  * force_shutdown is used to maintain chipset shutdown request. This request
@@ -145,7 +145,6 @@ enum power_state power_handle_state(enum power_state state)
 
 		new_state = POWER_S5G3;
 		goto rsmrst_handle;
-
 	}
 
 	/* If force shutdown is requested, perform that. */
diff --git a/power/braswell.c b/power/braswell.c
deleted file mode 100644
index dd2e3a8bb5..0000000000
--- a/power/braswell.c
+++ /dev/null
@@ -1,324 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* X86 braswell chipset power control module for Chrome EC */
-
-#include "chipset.h"
-#include "common.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "lid_switch.h"
-#include "lpc.h"
-#include "power.h"
-#include "power_button.h"
-#include "system.h"
-#include "timer.h"
-#include "usb_charge.h"
-#include "util.h"
-#include "wireless.h"
-#include "registers.h"
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-
-/* Input state flags */
-#define IN_RSMRST_L_PWRGD          POWER_SIGNAL_MASK(X86_RSMRST_L_PWRGD)
-#define IN_ALL_SYS_PWRGD           POWER_SIGNAL_MASK(X86_ALL_SYS_PWRGD)
-#define IN_SLP_S3_DEASSERTED       POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
-#define IN_SLP_S4_DEASSERTED       POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED)
-
-/* All always-on supplies */
-#define IN_PGOOD_ALWAYS_ON   (IN_RSMRST_L_PWRGD)
-/* All non-core power rails */
-#define IN_PGOOD_ALL_NONCORE (IN_ALL_SYS_PWRGD)
-/* All core power rails */
-#define IN_PGOOD_ALL_CORE    (IN_ALL_SYS_PWRGD)
-/* Rails required for S5 */
-#define IN_PGOOD_S5          (IN_PGOOD_ALWAYS_ON)
-/* Rails required for S3 */
-#define IN_PGOOD_S3          (IN_PGOOD_ALWAYS_ON)
-/* Rails required for S0 */
-#define IN_PGOOD_S0          (IN_PGOOD_ALWAYS_ON | IN_PGOOD_ALL_NONCORE)
-
-/* All PM_SLP signals from PCH deasserted */
-#define IN_ALL_PM_SLP_DEASSERTED (IN_SLP_S3_DEASSERTED | IN_SLP_S4_DEASSERTED)
-/* All inputs in the right state for S0 */
-#define IN_ALL_S0 (IN_PGOOD_S0 | IN_ALL_PM_SLP_DEASSERTED)
-
-static int throttle_cpu;      /* Throttle CPU? */
-static int forcing_shutdown;  /* Forced shutdown in progress? */
-
-void chipset_force_shutdown(enum chipset_shutdown_reason reason)
-{
-	CPRINTS("%s(%d)", __func__, reason);
-	report_ap_reset(reason);
-
-	/*
-	 * Force power off. This condition will reset once the state machine
-	 * transitions to G3.
-	 */
-#ifndef CONFIG_PMIC
-	gpio_set_level(GPIO_PCH_SYS_PWROK, 0);
-#endif
-	gpio_set_level(GPIO_PCH_RSMRST_L, 0);
-	forcing_shutdown = 1;
-}
-
-void chipset_reset(enum chipset_shutdown_reason reason)
-{
-	CPRINTS("%s: %d", __func__, reason);
-	report_ap_reset(reason);
-
-	/*
-	 * Send a reset pulse to the PCH.  This just causes it to
-	 * assert INIT# to the CPU without dropping power or asserting
-	 * PLTRST# to reset the rest of the system.  The PCH uses a 16
-	 * ms debounce time, so assert the signal for twice that.
-	 */
-	gpio_set_level(GPIO_PCH_RCIN_L, 0);
-	usleep(32 * MSEC);
-	gpio_set_level(GPIO_PCH_RCIN_L, 1);
-}
-
-void chipset_throttle_cpu(int throttle)
-{
-#ifdef CONFIG_CPU_PROCHOT_ACTIVE_LOW
-	throttle = !throttle;
-#endif /* CONFIG_CPU_PROCHOT_ACTIVE_LOW */
-	if (chipset_in_state(CHIPSET_STATE_ON))
-		gpio_set_level(GPIO_CPU_PROCHOT, throttle);
-}
-
-enum power_state power_chipset_init(void)
-{
-	/* Pause in S5 when shutting down. */
-	power_set_pause_in_s5(1);
-
-	/*
-	 * If we're switching between images without rebooting, see if the x86
-	 * is already powered on; if so, leave it there instead of cycling
-	 * through G3.
-	 */
-	if (system_jumped_to_this_image()) {
-		if ((power_get_signals() & IN_PGOOD_S0) == IN_PGOOD_S0) {
-			/* Disable idle task deep sleep when in S0. */
-			disable_sleep(SLEEP_MASK_AP_RUN);
-
-			CPRINTS("already in S0");
-			return POWER_S0;
-		} else {
-			/* Force all signals to their G3 states */
-			CPRINTS("forcing G3");
-			gpio_set_level(GPIO_PCH_SYS_PWROK, 0);
-			gpio_set_level(GPIO_PCH_RSMRST_L, 0);
-
-			/*wireless_set_state(WIRELESS_OFF);*/
-		}
-	}
-
-	return POWER_G3;
-}
-
-enum power_state power_handle_state(enum power_state state)
-{
-	switch (state) {
-	case POWER_G3:
-		break;
-
-	case POWER_G3S5:
-		/* Exit SOC G3 */
-#ifdef CONFIG_PMIC
-		gpio_set_level(GPIO_PCH_SYS_PWROK, 1);
-#else
-		gpio_set_level(GPIO_SUSPWRDNACK_SOC_EC, 0);
-#endif
-		CPRINTS("Exit SOC G3");
-
-		if (power_wait_signals(IN_PGOOD_S5)) {
-			chipset_force_shutdown(CHIPSET_SHUTDOWN_WAIT);
-			return POWER_G3;
-		}
-
-		/* Deassert RSMRST# */
-		gpio_set_level(GPIO_PCH_RSMRST_L, 1);
-		return POWER_S5;
-
-	case POWER_S5:
-		/* Check for SLP S4 */
-		if (gpio_get_level(GPIO_PCH_SLP_S4_L) == 1)
-			return POWER_S5S3; /* Power up to next state */
-		break;
-
-	case POWER_S5S3:
-
-		/* Call hooks now that rails are up */
-		hook_notify(HOOK_CHIPSET_STARTUP);
-
-		return POWER_S3;
-
-
-	case POWER_S3:
-
-		/* Check for state transitions */
-		if (!power_has_signals(IN_PGOOD_S3)) {
-			/* Required rail went away */
-			chipset_force_shutdown(CHIPSET_SHUTDOWN_POWERFAIL);
-			return POWER_S3S5;
-		} else if (gpio_get_level(GPIO_PCH_SLP_S3_L) == 1) {
-			/* Power up to next state */
-			return POWER_S3S0;
-		} else if (gpio_get_level(GPIO_PCH_SLP_S4_L) == 0) {
-			/* Power down to next state */
-			return POWER_S3S5;
-		}
-		break;
-
-	case POWER_S3S0:
-		/* Enable wireless */
-
-		/*wireless_set_state(WIRELESS_ON);*/
-
-		if (!power_has_signals(IN_PGOOD_S3)) {
-			chipset_force_shutdown(CHIPSET_SHUTDOWN_POWERFAIL);
-
-		/*wireless_set_state(WIRELESS_OFF);*/
-			return POWER_S3S5;
-		}
-
-		/* Call hooks now that rails are up */
-		hook_notify(HOOK_CHIPSET_RESUME);
-
-		/*
-		 * Disable idle task deep sleep. This means that the low
-		 * power idle task will not go into deep sleep while in S0.
-		 */
-		disable_sleep(SLEEP_MASK_AP_RUN);
-
-		/*
-		 * Wait 15 ms after all voltages good.  100 ms is only needed
-		 * for PCIe devices; mini-PCIe devices should need only 10 ms.
-		 */
-		msleep(15);
-
-		/*
-		 * Throttle CPU if necessary.  This should only be asserted
-		 * when +VCCP is powered (it is by now).
-		 */
-#ifdef CONFIG_CPU_PROCHOT_ACTIVE_LOW
-		gpio_set_level(GPIO_CPU_PROCHOT, !throttle_cpu);
-#else
-		gpio_set_level(GPIO_CPU_PROCHOT, throttle_cpu);
-#endif /* CONFIG_CPU_PROCHOT_ACTIVE_LOW */
-
-		/* Set SYS and CORE PWROK */
-		gpio_set_level(GPIO_PCH_SYS_PWROK, 1);
-
-		return POWER_S0;
-
-
-	case POWER_S0:
-
-		if (!power_has_signals(IN_PGOOD_ALWAYS_ON)) {
-			chipset_force_shutdown(CHIPSET_SHUTDOWN_POWERFAIL);
-			return POWER_S0S3;
-		}
-
-		if (!power_has_signals(IN_ALL_S0)) {
-			return POWER_S0S3;
-		}
-
-		break;
-	case POWER_S0S3:
-		/* Call hooks before we remove power rails */
-		hook_notify(HOOK_CHIPSET_SUSPEND);
-
-#ifndef CONFIG_PMIC
-		/* Clear SYS and CORE PWROK */
-		gpio_set_level(GPIO_PCH_SYS_PWROK, 0);
-#endif
-		/* Wait 40ns */
-		udelay(1);
-
-		/* Suspend wireless */
-
-		/*wireless_set_state(WIRELESS_SUSPEND);*/
-
-		/*
-		 * Enable idle task deep sleep. Allow the low power idle task
-		 * to go into deep sleep in S3 or lower.
-		 */
-		enable_sleep(SLEEP_MASK_AP_RUN);
-
-		/*
-		 * Deassert prochot since CPU is off and we're about to drop
-		 * +VCCP.
-		 */
-		gpio_set_level(GPIO_CPU_PROCHOT, 0);
-
-		return POWER_S3;
-
-	case POWER_S3S5:
-
-		/* Call hooks before we remove power rails */
-		hook_notify(HOOK_CHIPSET_SHUTDOWN);
-
-		/*wireless_set_state(WIRELESS_OFF);*/
-
-		/* Call hooks after we remove power rails */
-		hook_notify(HOOK_CHIPSET_SHUTDOWN_COMPLETE);
-
-		/* Start shutting down */
-		return power_get_pause_in_s5() ? POWER_S5 : POWER_S5G3;
-
-	case POWER_S5G3:
-		/*
-		 * in case shutdown is already done by apshutdown
-		 * (or chipset_force_shutdown()), SOC already lost
-		 * power and can't assert PMC_SUSPWRDNACK any more.
-		 */
-		if (forcing_shutdown) {
-			/* Config pins for SOC G3 */
-			gpio_config_module(MODULE_GPIO, 1);
-#ifndef CONFIG_PMIC
-			gpio_set_level(GPIO_SUSPWRDNACK_SOC_EC, 1);
-#else
-			gpio_set_level(GPIO_PCH_SYS_PWROK, 0);
-#endif
-
-			forcing_shutdown = 0;
-
-			CPRINTS("Enter SOC G3");
-
-			return POWER_G3;
-		}
-
-		if (gpio_get_level(GPIO_PCH_SUSPWRDNACK) == 1) {
-			/* Assert RSMRST# */
-			gpio_set_level(GPIO_PCH_RSMRST_L, 0);
-
-			/* Config pins for SOC G3 */
-			gpio_config_module(MODULE_GPIO, 1);
-
-			/* Enter SOC G3 */
-#ifdef CONFIG_PMIC
-			gpio_set_level(GPIO_PCH_SYS_PWROK, 0);
-			udelay(1);
-			gpio_set_level(GPIO_PCH_RSMRST_L, 0);
-#else
-			gpio_set_level(GPIO_SUSPWRDNACK_SOC_EC, 1);
-#endif
-			CPRINTS("Enter SOC G3");
-
-			return POWER_G3;
-		} else {
-			CPRINTS("waiting for PMC_SUSPWRDNACK to assert!");
-			return POWER_S5;
-		}
-	}
-	return state;
-}
diff --git a/power/build.mk b/power/build.mk
index 82a55c14aa..8ef237c154 100644
--- a/power/build.mk
+++ b/power/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
+# Copyright 2013 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -9,7 +9,6 @@
 power-$(CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540)+=alderlake_slg4bd44540.o
 power-$(CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540)+=intel_x86.o
 power-$(CONFIG_CHIPSET_APL_GLK)+=apollolake.o intel_x86.o
-power-$(CONFIG_CHIPSET_BRASWELL)+=braswell.o
 power-$(CONFIG_CHIPSET_CANNONLAKE)+=cannonlake.o intel_x86.o
 power-$(CONFIG_CHIPSET_COMETLAKE)+=cometlake.o intel_x86.o
 power-$(CONFIG_CHIPSET_COMETLAKE_DISCRETE)+=cometlake-discrete.o intel_x86.o
diff --git a/power/cannonlake.c b/power/cannonlake.c
index 392db669df..b6f8d91e69 100644
--- a/power/cannonlake.c
+++ b/power/cannonlake.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,9 +16,9 @@
 #include "timer.h"
 
 /* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
-static int forcing_shutdown;  /* Forced shutdown in progress? */
+static int forcing_shutdown; /* Forced shutdown in progress? */
 
 void chipset_force_shutdown(enum chipset_shutdown_reason reason)
 {
@@ -47,7 +47,7 @@ void chipset_handle_espi_reset_assert(void)
 	 * power button. If yes, release power button.
 	 */
 	if ((power_get_signals() & IN_PCH_SLP_SUS_DEASSERTED) &&
-		forcing_shutdown) {
+	    forcing_shutdown) {
 		power_button_pch_release();
 		forcing_shutdown = 0;
 	}
diff --git a/power/cometlake-discrete.c b/power/cometlake-discrete.c
index a22e32a69f..85a08da2d2 100644
--- a/power/cometlake-discrete.c
+++ b/power/cometlake-discrete.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -217,7 +217,9 @@ void chipset_force_shutdown(enum chipset_shutdown_reason reason)
 	shutdown_s5_rails();
 }
 
-void chipset_handle_espi_reset_assert(void) {}
+void chipset_handle_espi_reset_assert(void)
+{
+}
 
 enum power_state chipset_force_g3(void)
 {
@@ -303,7 +305,7 @@ enum power_state power_handle_state(enum power_state state)
 		if (power_wait_signals(POWER_SIGNAL_MASK(PP1800_A_PGOOD) |
 				       POWER_SIGNAL_MASK(PP1050_A_PGOOD)))
 			return pgood_timeout(POWER_S5G3);
-		msleep(10);	/* tPCH03: VCCPRIM good -> RSMRST >10ms */
+		msleep(10); /* tPCH03: VCCPRIM good -> RSMRST >10ms */
 		gpio_set_level(GPIO_PCH_RSMRST_L, 1);
 		break;
 
@@ -383,7 +385,9 @@ enum power_state power_handle_state(enum power_state state)
  * implies power sequencing is all-off and we don't have any external
  * PMIC to synchronize state with.
  */
-void chipset_handle_reboot(void) {}
+void chipset_handle_reboot(void)
+{
+}
 #endif /* CONFIG_VBOOT_EFS */
 
 void c10_gate_interrupt(enum gpio_signal signal)
@@ -406,8 +410,8 @@ void c10_gate_interrupt(enum gpio_signal signal)
 
 void slp_s3_interrupt(enum gpio_signal signal)
 {
-	if (!gpio_get_level(GPIO_SLP_S3_L)
-	    && chipset_in_state(CHIPSET_STATE_ON)) {
+	if (!gpio_get_level(GPIO_SLP_S3_L) &&
+	    chipset_in_state(CHIPSET_STATE_ON)) {
 		/* Falling edge on SLP_S3_L means dropping to S3 from S0 */
 		shutdown_s0_rails();
 	}
diff --git a/power/cometlake.c b/power/cometlake.c
index 3c127b0c03..508ad22df4 100644
--- a/power/cometlake.c
+++ b/power/cometlake.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,7 +15,7 @@
 #include "timer.h"
 
 /* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 /* Power signals list. Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
@@ -53,12 +53,12 @@ const struct power_signal_info power_signal_list[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
-static int forcing_shutdown;  /* Forced shutdown in progress? */
+static int forcing_shutdown; /* Forced shutdown in progress? */
 
 /* Default no action, overwrite it in board.c if necessary*/
 __overridable void board_chipset_forced_shutdown(void)
 {
-        return;
+	return;
 }
 
 void chipset_force_shutdown(enum chipset_shutdown_reason reason)
@@ -84,7 +84,7 @@ void chipset_force_shutdown(enum chipset_shutdown_reason reason)
 
 	/* For b:143440730, stop checking GPIO_ALL_SYS_PGOOD if system is
 	 * already force to G3.
-         */
+	 */
 	board_chipset_forced_shutdown();
 
 	/* Need to wait a min of 10 msec before check for power good */
@@ -92,7 +92,8 @@ void chipset_force_shutdown(enum chipset_shutdown_reason reason)
 
 	/* Now wait for PP5000_A and RSMRST_L to go low */
 	while ((gpio_get_level(GPIO_PP5000_A_PG_OD) ||
-		power_has_signals(IN_PGOOD_ALL_CORE)) && (timeout_ms > 0)) {
+		power_has_signals(IN_PGOOD_ALL_CORE)) &&
+	       (timeout_ms > 0)) {
 		msleep(1);
 		timeout_ms--;
 	};
@@ -155,7 +156,6 @@ void chipset_pre_init_callback(void)
 
 enum power_state power_handle_state(enum power_state state)
 {
-
 	int all_sys_pwrgd_in;
 	int all_sys_pwrgd_out;
 
@@ -176,7 +176,6 @@ enum power_state power_handle_state(enum power_state state)
 		common_intel_x86_handle_rsmrst(state);
 
 	switch (state) {
-
 	case POWER_S5:
 		if (forcing_shutdown) {
 			power_button_pch_release();
diff --git a/power/common.c b/power/common.c
index 04d416ee5f..24b9f314f4 100644
--- a/power/common.c
+++ b/power/common.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,6 +18,7 @@
 #include "host_command.h"
 #include "lpc.h"
 #include "power.h"
+#include "power/amd_x86.h"
 #include "power/intel_x86.h"
 #include "power/qcom.h"
 #include "system.h"
@@ -27,8 +28,8 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ##args)
 
 /*
  * Default timeout in us; if we've been waiting this long for an input
@@ -43,37 +44,24 @@ static int s5_inactivity_timeout = 10;
 static const int s5_inactivity_timeout = 10;
 #endif
 
-static const char * const state_names[] = {
-	"G3",
-	"S5",
-	"S4",
-	"S3",
-	"S0",
+static const char *const state_names[] = {
+	"G3",	    "S5",	"S4",	  "S3",	    "S0",
 #ifdef CONFIG_POWER_S0IX
 	"S0ix",
 #endif
-	"G3->S5",
-	"S5->S3",
-	"S3->S0",
-	"S0->S3",
-	"S3->S5",
-	"S5->G3",
-	"S3->S4",
-	"S4->S3",
-	"S4->S5",
-	"S5->S4",
+	"G3->S5",   "S5->S3",	"S3->S0", "S0->S3", "S3->S5",
+	"S5->G3",   "S3->S4",	"S4->S3", "S4->S5", "S5->S4",
 #ifdef CONFIG_POWER_S0IX
-	"S0ix->S0",
-	"S0->S0ix",
+	"S0ix->S0", "S0->S0ix",
 #endif
 };
 
-static uint32_t in_signals;   /* Current input signal states (IN_PGOOD_*) */
-static uint32_t in_want;      /* Input signal state we're waiting for */
-static uint32_t in_debug;     /* Signal values which print debug output */
+static uint32_t in_signals; /* Current input signal states (IN_PGOOD_*) */
+static uint32_t in_want; /* Input signal state we're waiting for */
+static uint32_t in_debug; /* Signal values which print debug output */
 
-static enum power_state state = POWER_G3;  /* Current state */
-static int want_g3_exit;      /* Should we exit the G3 state? */
+static enum power_state state = POWER_G3; /* Current state */
+static int want_g3_exit; /* Should we exit the G3 state? */
 static uint64_t last_shutdown_time; /* When did we enter G3? */
 
 #ifdef CONFIG_HIBERNATE
@@ -86,7 +74,7 @@ static uint32_t hibernate_delay = CONFIG_HIBERNATE_DELAY_SEC;
 static int pause_in_s5;
 #endif
 
-static bool want_reboot_ap_at_g3;/* Want to reboot AP from G3? */
+static bool want_reboot_ap_at_g3; /* Want to reboot AP from G3? */
 /* Want to reboot AP from G3 with delay? */
 static uint64_t reboot_ap_at_g3_delay;
 
@@ -111,8 +99,7 @@ host_command_reboot_ap_on_g3(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_REBOOT_AP_ON_G3,
-		     host_command_reboot_ap_on_g3,
+DECLARE_HOST_COMMAND(EC_CMD_REBOOT_AP_ON_G3, host_command_reboot_ap_on_g3,
 		     EC_VER_MASK(0) | EC_VER_MASK(1));
 
 __overridable int power_signal_get_level(enum gpio_signal signal)
@@ -150,7 +137,7 @@ int power_signal_enable_interrupt(enum gpio_signal signal)
 int power_signal_is_asserted(const struct power_signal_info *s)
 {
 	return power_signal_get_level(s->gpio) ==
-		!!(s->flags & POWER_SIGNAL_ACTIVE_STATE);
+	       !!(s->flags & POWER_SIGNAL_ACTIVE_STATE);
 }
 
 #ifdef CONFIG_BRINGUP
@@ -196,8 +183,8 @@ int power_has_signals(uint32_t want)
 	if ((in_signals & want) == want)
 		return 1;
 
-	CPRINTS("power lost input; wanted 0x%04x, got 0x%04x",
-		want, in_signals & want);
+	CPRINTS("power lost input; wanted 0x%04x, got 0x%04x", want,
+		in_signals & want);
 
 	return 0;
 }
@@ -267,18 +254,19 @@ enum power_state power_get_state(void)
 #ifdef CONFIG_HOSTCMD_X86
 
 /* If host doesn't program s0ix lazy wake mask, use default s0ix mask */
-#define DEFAULT_WAKE_MASK_S0IX  (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \
-				EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
-
- /*
-  * Set the wake mask according to the current power state:
-  * 1. On transition to S0, wake mask is reset.
-  * 2. In non-S0 states, active mask set by host gets a higher preference.
-  * 3. If host has not set any active mask, then check if a lazy mask exists
-  *    for the current power state.
-  * 4. If state is S0ix and no lazy or active wake mask is set, then use default
-  *    S0ix mask to be compatible with older BIOS versions.
-  */
+#define DEFAULT_WAKE_MASK_S0IX                        \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
+
+/*
+ * Set the wake mask according to the current power state:
+ * 1. On transition to S0, wake mask is reset.
+ * 2. In non-S0 states, active mask set by host gets a higher preference.
+ * 3. If host has not set any active mask, then check if a lazy mask exists
+ *    for the current power state.
+ * 4. If state is S0ix and no lazy or active wake mask is set, then use default
+ *    S0ix mask to be compatible with older BIOS versions.
+ */
 
 void power_update_wake_mask(void)
 {
@@ -300,11 +288,11 @@ void power_update_wake_mask(void)
 
 	lpc_set_host_event_mask(LPC_HOST_EVENT_WAKE, wake_mask);
 }
- /*
-  * Set wake mask after power state has stabilized, 5ms after power state
-  * change. The reason for making this a deferred call is to avoid race
-  * conditions occurring from S0ix periodic wakes on the SoC.
-  */
+/*
+ * Set wake mask after power state has stabilized, 5ms after power state
+ * change. The reason for making this a deferred call is to avoid race
+ * conditions occurring from S0ix periodic wakes on the SoC.
+ */
 
 static void power_update_wake_mask_deferred(void);
 DECLARE_DEFERRED(power_update_wake_mask_deferred);
@@ -329,12 +317,13 @@ static void power_set_active_wake_mask(void)
 	 * that it takes ~2msec for the periodic wake cycle to complete on the
 	 * host for KBL.
 	 */
-	hook_call_deferred(&power_update_wake_mask_deferred_data,
-			   5 * MSEC);
+	hook_call_deferred(&power_update_wake_mask_deferred_data, 5 * MSEC);
 }
 
 #else
-static void power_set_active_wake_mask(void) { }
+static void power_set_active_wake_mask(void)
+{
+}
 #endif
 
 #ifdef CONFIG_HIBERNATE
@@ -378,15 +367,15 @@ static enum ec_status hc_smart_discharge(struct host_cmd_handler_args *args)
 		else if (p->drate.cutoff > 0 && p->drate.hibern > 0)
 			drate = p->drate;
 		else if (p->drate.cutoff == 0 && p->drate.hibern == 0)
-			;  /* no-op. use the current drate. */
+			; /* no-op. use the current drate. */
 		else
 			return EC_RES_INVALID_PARAM;
 
 		/* Commit */
 		hours_to_zero = p->hours_to_zero;
 		sdzone.stayup = MIN(hours_to_zero * drate.hibern / 1000, cap);
-		sdzone.cutoff = MIN(hours_to_zero * drate.cutoff / 1000,
-				    sdzone.stayup);
+		sdzone.cutoff =
+			MIN(hours_to_zero * drate.cutoff / 1000, sdzone.stayup);
 	}
 
 	/* Return the effective values. */
@@ -397,12 +386,12 @@ static enum ec_status hc_smart_discharge(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_SMART_DISCHARGE,
-		     hc_smart_discharge,
+DECLARE_HOST_COMMAND(EC_CMD_SMART_DISCHARGE, hc_smart_discharge,
 		     EC_VER_MASK(0));
 
-__overridable enum critical_shutdown board_system_is_idle(
-		uint64_t last_shutdown_time, uint64_t *target, uint64_t now)
+__overridable enum critical_shutdown
+board_system_is_idle(uint64_t last_shutdown_time, uint64_t *target,
+		     uint64_t now)
 {
 	int remain;
 
@@ -427,14 +416,15 @@ __overridable enum critical_shutdown board_system_is_idle(
 }
 #else
 /* Default implementation for battery-less systems */
-__overridable enum critical_shutdown board_system_is_idle(
-		uint64_t last_shutdown_time, uint64_t *target, uint64_t now)
+__overridable enum critical_shutdown
+board_system_is_idle(uint64_t last_shutdown_time, uint64_t *target,
+		     uint64_t now)
 {
-	return now > *target ?
-			CRITICAL_SHUTDOWN_HIBERNATE : CRITICAL_SHUTDOWN_IGNORE;
+	return now > *target ? CRITICAL_SHUTDOWN_HIBERNATE :
+			       CRITICAL_SHUTDOWN_IGNORE;
 }
-#endif	/* CONFIG_BATTERY */
-#endif	/* CONFIG_HIBERNATE */
+#endif /* CONFIG_BATTERY */
+#endif /* CONFIG_HIBERNATE */
 
 /**
  * Common handler for steady states
@@ -475,7 +465,7 @@ static enum power_state power_common_state(enum power_state state)
 
 			now = get_time().val;
 			target = last_shutdown_time +
-					(uint64_t)hibernate_delay * SECOND;
+				 (uint64_t)hibernate_delay * SECOND;
 			switch (board_system_is_idle(last_shutdown_time,
 						     &target, now)) {
 			case CRITICAL_SHUTDOWN_HIBERNATE:
@@ -708,8 +698,8 @@ void chipset_task(void *u)
 		 */
 		this_in_signals = in_signals;
 		if (this_in_signals != last_in_signals || state != last_state) {
-			CPRINTS("power state %d = %s, in 0x%04x",
-				state, state_names[state], this_in_signals);
+			CPRINTS("power state %d = %s, in 0x%04x", state,
+				state_names[state], this_in_signals);
 			if (IS_ENABLED(CONFIG_SEVEN_SEG_DISPLAY))
 				display_7seg_write(SEVEN_SEG_EC_DISPLAY, state);
 			last_in_signals = this_in_signals;
@@ -809,7 +799,7 @@ static struct {
 static void siglog_deferred(void)
 {
 	unsigned int i;
-	timestamp_t tdiff = {.val = 0};
+	timestamp_t tdiff = { .val = 0 };
 
 	/* Disable interrupts for input signals while we print stuff.*/
 	for (i = 0; i < POWER_SIGNAL_COUNT; i++)
@@ -818,10 +808,9 @@ static void siglog_deferred(void)
 	CPRINTF("%d signal changes:\n", siglog_entries);
 	for (i = 0; i < siglog_entries; i++) {
 		if (i)
-			tdiff.val = siglog[i].time.val - siglog[i-1].time.val;
-		CPRINTF("  %.6lld  +%.6lld  %s => %d\n",
-			siglog[i].time.val, tdiff.val,
-			power_signal_get_name(siglog[i].signal),
+			tdiff.val = siglog[i].time.val - siglog[i - 1].time.val;
+		CPRINTF("  %.6lld  +%.6lld  %s => %d\n", siglog[i].time.val,
+			tdiff.val, power_signal_get_name(siglog[i].signal),
 			siglog[i].level);
 	}
 	if (siglog_truncated)
@@ -853,7 +842,7 @@ static void siglog_add(enum gpio_signal signal)
 
 #else
 #define SIGLOG(S)
-#endif	/* CONFIG_BRINGUP */
+#endif /* CONFIG_BRINGUP */
 
 #ifdef CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD
 /*
@@ -870,8 +859,7 @@ static void reset_power_signal_interrupt_count(void)
 	for (i = 0; i < POWER_SIGNAL_COUNT; ++i)
 		power_signal_interrupt_count[i] = 0;
 }
-DECLARE_HOOK(HOOK_SECOND,
-	     reset_power_signal_interrupt_count,
+DECLARE_HOOK(HOOK_SECOND, reset_power_signal_interrupt_count,
 	     HOOK_PRIO_DEFAULT);
 #endif
 
@@ -884,7 +872,7 @@ void power_signal_interrupt(enum gpio_signal signal)
 	for (i = 0; i < POWER_SIGNAL_COUNT; ++i) {
 		if (power_signal_list[i].gpio == signal) {
 			if (power_signal_interrupt_count[i]++ ==
-			   CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD)
+			    CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD)
 				CPRINTS("Interrupt storm! Signal %d", i);
 			break;
 		}
@@ -915,23 +903,22 @@ inline void power_set_pause_in_s5(int pause)
 /*****************************************************************************/
 /* Console commands */
 
-static int command_powerinfo(int argc, char **argv)
+static int command_powerinfo(int argc, const char **argv)
 {
 	/*
 	 * Print power state in same format as state machine.  This is
 	 * used by FAFT tests, so must match exactly.
 	 */
-	ccprintf("power state %d = %s, in 0x%04x\n",
-		 state, state_names[state], in_signals);
+	ccprintf("power state %d = %s, in 0x%04x\n", state, state_names[state],
+		 in_signals);
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(powerinfo, command_powerinfo,
-			NULL,
+DECLARE_CONSOLE_COMMAND(powerinfo, command_powerinfo, NULL,
 			"Show current power state");
 
 #ifdef CONFIG_CMD_POWERINDEBUG
-static int command_powerindebug(int argc, char **argv)
+static int command_powerindebug(int argc, const char **argv)
 {
 	const struct power_signal_info *s = power_signal_list;
 	int i;
@@ -955,20 +942,19 @@ static int command_powerindebug(int argc, char **argv)
 	ccprintf("bit meanings:\n");
 	for (i = 0; i < POWER_SIGNAL_COUNT; i++, s++) {
 		int mask = 1 << i;
-		ccprintf("  0x%04x %d %s\n",
-			 mask, in_signals & mask ? 1 : 0, s->name);
+		ccprintf("  0x%04x %d %s\n", mask, in_signals & mask ? 1 : 0,
+			 s->name);
 	}
 
 	return EC_SUCCESS;
 };
-DECLARE_CONSOLE_COMMAND(powerindebug, command_powerindebug,
-			"[mask]",
+DECLARE_CONSOLE_COMMAND(powerindebug, command_powerindebug, "[mask]",
 			"Get/set power input debug mask");
 #endif
 
 #ifdef CONFIG_CMD_S5_TIMEOUT
 /* Allow command-line access to configure our S5 delay for power testing */
-static int command_s5_timeout(int argc, char **argv)
+static int command_s5_timeout(int argc, const char **argv)
 {
 	char *e;
 
@@ -985,18 +971,17 @@ static int command_s5_timeout(int argc, char **argv)
 	ccprintf("S5 inactivity timeout: %d s\n", s5_inactivity_timeout);
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(s5_timeout, command_s5_timeout,
-			"[sec]",
+DECLARE_CONSOLE_COMMAND(s5_timeout, command_s5_timeout, "[sec]",
 			"Set the timeout from S5 to G3 transition, "
 			"-1 to indicate no transition");
 #endif
 
 #ifdef CONFIG_HIBERNATE
-static int command_hibernation_delay(int argc, char **argv)
+static int command_hibernation_delay(int argc, const char **argv)
 {
 	char *e;
-	uint32_t time_g3 = ((uint32_t)(get_time().val - last_shutdown_time))
-				/ SECOND;
+	uint32_t time_g3 =
+		((uint32_t)(get_time().val - last_shutdown_time)) / SECOND;
 
 	if (argc >= 2) {
 		uint32_t s = strtoi(argv[1], &e, 0);
@@ -1014,8 +999,7 @@ static int command_hibernation_delay(int argc, char **argv)
 	}
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(hibdelay, command_hibernation_delay,
-			"[sec]",
+DECLARE_CONSOLE_COMMAND(hibdelay, command_hibernation_delay, "[sec]",
 			"Set the delay before going into hibernation");
 
 static enum ec_status
@@ -1048,8 +1032,7 @@ host_command_hibernation_delay(struct host_cmd_handler_args *args)
 	args->response_size = sizeof(struct ec_response_hibernation_delay);
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_HIBERNATION_DELAY,
-		     host_command_hibernation_delay,
+DECLARE_HOST_COMMAND(EC_CMD_HIBERNATION_DELAY, host_command_hibernation_delay,
 		     EC_VER_MASK(0));
 #endif /* CONFIG_HIBERNATE */
 
@@ -1068,11 +1051,10 @@ host_command_pause_in_s5(struct host_cmd_handler_args *args)
 	args->response_size = sizeof(*r);
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_GSV_PAUSE_IN_S5,
-		     host_command_pause_in_s5,
+DECLARE_HOST_COMMAND(EC_CMD_GSV_PAUSE_IN_S5, host_command_pause_in_s5,
 		     EC_VER_MASK(0));
 
-static int command_pause_in_s5(int argc, char **argv)
+static int command_pause_in_s5(int argc, const char **argv)
 {
 	if (argc > 1 && !parse_bool(argv[1], &pause_in_s5))
 		return EC_ERROR_INVAL;
@@ -1081,8 +1063,7 @@ static int command_pause_in_s5(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(pause_in_s5, command_pause_in_s5,
-			"[on|off]",
+DECLARE_CONSOLE_COMMAND(pause_in_s5, command_pause_in_s5, "[on|off]",
 			"Should the AP pause in S5 during shutdown?");
 #endif /* CONFIG_POWER_SHUTDOWN_PAUSE_IN_S5 */
 
@@ -1116,14 +1097,13 @@ void power_5v_enable(task_id_t tid, int enable)
 	mutex_unlock(&pwr_5v_ctl_mtx);
 }
 
-#define P5_SYSJUMP_TAG 0x5005  /* "P5" */
+#define P5_SYSJUMP_TAG 0x5005 /* "P5" */
 static void restore_enable_5v_state(void)
 {
 	const uint32_t *state;
 	int size;
 
-	state = (const uint32_t *) system_get_jump_tag(P5_SYSJUMP_TAG, 0,
-						       &size);
+	state = (const uint32_t *)system_get_jump_tag(P5_SYSJUMP_TAG, 0, &size);
 	if (state && size == sizeof(pwr_5v_en_req)) {
 		mutex_lock(&pwr_5v_ctl_mtx);
 		pwr_5v_en_req |= *state;
@@ -1136,14 +1116,14 @@ static void preserve_enable_5v_state(void)
 {
 	mutex_lock(&pwr_5v_ctl_mtx);
 	system_add_jump_tag(P5_SYSJUMP_TAG, 0, sizeof(pwr_5v_en_req),
-	    &pwr_5v_en_req);
+			    &pwr_5v_en_req);
 	mutex_unlock(&pwr_5v_ctl_mtx);
 }
 DECLARE_HOOK(HOOK_SYSJUMP, preserve_enable_5v_state, HOOK_PRIO_DEFAULT);
 #endif /* defined(CONFIG_POWER_PP5000_CONTROL) */
 
 #ifdef CONFIG_POWERSEQ_FAKE_CONTROL
-static int command_power_fake(int argc, char **argv)
+static int command_power_fake(int argc, const char **argv)
 {
 	if (argc < 2) {
 		ccprints("Error: Argument required");
diff --git a/power/ec_driven.c b/power/ec_driven.c
index 282941b941..f0aee46c60 100644
--- a/power/ec_driven.c
+++ b/power/ec_driven.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,7 +11,7 @@
  *
  */
 
-#include "chipset.h"  /* This module implements chipset functions too */
+#include "chipset.h" /* This module implements chipset functions too */
 #include "common.h"
 #include "console.h"
 #include "gpio.h"
@@ -22,7 +22,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 #define IN_SUSPEND POWER_SIGNAL_MASK(ECDRIVEN_SUSPEND_ASSERTED)
 
diff --git a/power/falconlite.c b/power/falconlite.c
index b418edfd84..04c428f5be 100644
--- a/power/falconlite.c
+++ b/power/falconlite.c
@@ -1,10 +1,11 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* FalconLite chipset power control module for Chrome EC */
 
+#include "builtin/assert.h"
 #include "charge_state.h"
 #include "chipset.h"
 #include "common.h"
@@ -29,7 +30,7 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 /* Long power key press to force shutdown in S0. go/crosdebug */
 #define FORCED_SHUTDOWN_DELAY (8 * SECOND)
@@ -39,61 +40,35 @@
 #define SYS_RST_PULSE_LENGTH (30 * MSEC)
 
 /* Masks for power signals */
-#define IN_PG_S5		POWER_SIGNAL_MASK(FCL_PG_S5)
-#define IN_PGOOD		(POWER_SIGNAL_MASK(FCL_PG_VDD1_VDD2) | \
-				 POWER_SIGNAL_MASK(FCL_PG_VDD_MEDIA_ML) | \
-				 POWER_SIGNAL_MASK(FCL_PG_VDD_SOC) | \
-				 POWER_SIGNAL_MASK(FCL_PG_VDD_DDR_OD) | \
-				 POWER_SIGNAL_MASK(FCL_PG_S5))
+#define IN_PG_S5 POWER_SIGNAL_MASK(FCL_PG_S5)
+#define IN_PGOOD                                  \
+	(POWER_SIGNAL_MASK(FCL_PG_VDD1_VDD2) |    \
+	 POWER_SIGNAL_MASK(FCL_PG_VDD_MEDIA_ML) | \
+	 POWER_SIGNAL_MASK(FCL_PG_VDD_SOC) |      \
+	 POWER_SIGNAL_MASK(FCL_PG_VDD_DDR_OD) | POWER_SIGNAL_MASK(FCL_PG_S5))
 
-#define IN_ALL_S0		IN_PGOOD
-#define IN_ALL_S3		IN_PGOOD
+#define IN_ALL_S0 IN_PGOOD
+#define IN_ALL_S3 IN_PGOOD
 
 /* Power signal list. Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
-	[FCL_AP_WARM_RST_REQ] = {
-		GPIO_AP_EC_WARM_RST_REQ,
-		POWER_SIGNAL_ACTIVE_HIGH,
-		"AP_WARM_RST_REQ"
-	},
-	[FCL_AP_SHUTDOWN_REQ] = {
-		GPIO_AP_EC_SHUTDOWN_REQ_L,
-		POWER_SIGNAL_ACTIVE_LOW,
-		"AP_SHUTDOWN_REQ"
-	},
-	[FCL_AP_WATCHDOG] = {
-		GPIO_AP_EC_WATCHDOG_L,
-		POWER_SIGNAL_ACTIVE_LOW,
-		"AP_WDT"
-	},
-	[FCL_PG_S5] = {
-		GPIO_PG_S5_PWR_OD,
-		POWER_SIGNAL_ACTIVE_HIGH,
-		"PG_S5"
-	},
-	[FCL_PG_VDD1_VDD2] = {
-		GPIO_PG_VDD1_VDD2_OD,
-		POWER_SIGNAL_ACTIVE_HIGH,
-		"PG_VDD1_VDD2"
-	},
-	[FCL_PG_VDD_MEDIA_ML] = {
-		GPIO_PG_VDD_MEDIA_ML_OD,
-		POWER_SIGNAL_ACTIVE_HIGH,
-		"PG_VDD_MEDIA_ML"
-	},
-	[FCL_PG_VDD_SOC] = {
-		GPIO_PG_VDD_SOC_OD,
-		POWER_SIGNAL_ACTIVE_HIGH,
-		"PG_VDD_SOC"
-	},
-	[FCL_PG_VDD_DDR_OD] = {
-		GPIO_PG_VDD_DDR_OD,
-		POWER_SIGNAL_ACTIVE_HIGH,
-		"PG_VDD_DDR"
-	},
+	[FCL_AP_WARM_RST_REQ] = { GPIO_AP_EC_WARM_RST_REQ,
+				  POWER_SIGNAL_ACTIVE_HIGH, "AP_WARM_RST_REQ" },
+	[FCL_AP_SHUTDOWN_REQ] = { GPIO_AP_EC_SHUTDOWN_REQ_L,
+				  POWER_SIGNAL_ACTIVE_LOW, "AP_SHUTDOWN_REQ" },
+	[FCL_AP_WATCHDOG] = { GPIO_AP_EC_WATCHDOG_L, POWER_SIGNAL_ACTIVE_LOW,
+			      "AP_WDT" },
+	[FCL_PG_S5] = { GPIO_PG_S5_PWR_OD, POWER_SIGNAL_ACTIVE_HIGH, "PG_S5" },
+	[FCL_PG_VDD1_VDD2] = { GPIO_PG_VDD1_VDD2_OD, POWER_SIGNAL_ACTIVE_HIGH,
+			       "PG_VDD1_VDD2" },
+	[FCL_PG_VDD_MEDIA_ML] = { GPIO_PG_VDD_MEDIA_ML_OD,
+				  POWER_SIGNAL_ACTIVE_HIGH, "PG_VDD_MEDIA_ML" },
+	[FCL_PG_VDD_SOC] = { GPIO_PG_VDD_SOC_OD, POWER_SIGNAL_ACTIVE_HIGH,
+			     "PG_VDD_SOC" },
+	[FCL_PG_VDD_DDR_OD] = { GPIO_PG_VDD_DDR_OD, POWER_SIGNAL_ACTIVE_HIGH,
+				"PG_VDD_DDR" },
 };
 
-
 /* Data structure for a GPIO operation for power sequencing */
 struct power_seq_op {
 	enum gpio_signal signal;
@@ -109,70 +84,63 @@ struct power_seq_op {
 
 /* The power sequence for POWER_S3S5 */
 static const struct power_seq_op s3s5_power_seq[] = {
-	{GPIO_EN_VDD_CPU, 0, 0},
-	{GPIO_EN_VDD_GPU, 0, 0},
-	{GPIO_EN_VDD_MEDIA_ML, 0, 4},
+	{ GPIO_EN_VDD_CPU, 0, 0 },	{ GPIO_EN_VDD_GPU, 0, 0 },
+	{ GPIO_EN_VDD_MEDIA_ML, 0, 4 },
 
-	{GPIO_EN_VDDQ_VR_D, 0, 4},    /* LPDDR */
+	{ GPIO_EN_VDDQ_VR_D, 0, 4 }, /* LPDDR */
 
-	{GPIO_EN_VDD1_VDD2_VR, 0, 4}, /* LPDDR */
+	{ GPIO_EN_VDD1_VDD2_VR, 0, 4 }, /* LPDDR */
 
-	{GPIO_EN_VDD_DDR, 0, 4},
+	{ GPIO_EN_VDD_DDR, 0, 4 },
 
-	{GPIO_EN_PP3300A_IO_X, 0, 0},
-	{GPIO_EN_PP3300_S3, 0, 4},
+	{ GPIO_EN_PP3300A_IO_X, 0, 0 }, { GPIO_EN_PP3300_S3, 0, 4 },
 
-	{GPIO_EN_PP1820A_IO_X, 0, 0},
-	{GPIO_EN_PP1800_S3, 0, 0},
+	{ GPIO_EN_PP1820A_IO_X, 0, 0 }, { GPIO_EN_PP1800_S3, 0, 0 },
 };
 
 /* The power sequence for POWER_G3S5 */
 static const struct power_seq_op g3s5_power_seq[] = {
 	/* delay 10ms as PP1800_S5 uses PP1800_S5 as alaternative supply */
-	{GPIO_EN_PP5000_S5, 1, 10},
+	{ GPIO_EN_PP5000_S5, 1, 10 },
 
-	{GPIO_EN_PP1800_S5, 1, 0},
+	{ GPIO_EN_PP1800_S5, 1, 0 },
 
-	{GPIO_EN_PP1800_VDDIO_PMC_X, 1, 4},
+	{ GPIO_EN_PP1800_VDDIO_PMC_X, 1, 4 },
 
-	{GPIO_EN_PP0800_VDD_PMC_X, 1, 0},
-	{GPIO_EN_VDD_SOC, 1, 4},
+	{ GPIO_EN_PP0800_VDD_PMC_X, 1, 0 },   { GPIO_EN_VDD_SOC, 1, 4 },
 
-	{GPIO_EN_PP1800_VDD33_PMC_X, 1, 0},
+	{ GPIO_EN_PP1800_VDD33_PMC_X, 1, 0 },
 };
 
 /* This is the power sequence for POWER_S5S3. */
 static const struct power_seq_op s5s3_power_seq[] = {
-	{GPIO_EN_PP1800_S3, 1, 0},
-	{GPIO_EN_PP1820A_IO_X, 1, 4},
+	{ GPIO_EN_PP1800_S3, 1, 0 },	{ GPIO_EN_PP1820A_IO_X, 1, 4 },
 
-	{GPIO_EN_PP3300_S3, 1, 0},
-	{GPIO_EN_PP3300A_IO_X, 1, 4},
+	{ GPIO_EN_PP3300_S3, 1, 0 },	{ GPIO_EN_PP3300A_IO_X, 1, 4 },
 
-	{GPIO_EN_VDD_DDR, 1, 4},
+	{ GPIO_EN_VDD_DDR, 1, 4 },
 
-	{GPIO_EN_VDD1_VDD2_VR, 1, 4}, /* LPDDR */
+	{ GPIO_EN_VDD1_VDD2_VR, 1, 4 }, /* LPDDR */
 
-	{GPIO_EN_VDDQ_VR_D, 1, 4},    /* LPDDR */
+	{ GPIO_EN_VDDQ_VR_D, 1, 4 }, /* LPDDR */
 
-	{GPIO_EN_VDD_MEDIA_ML, 1, 0},
-	{GPIO_EN_VDD_GPU, 1, 0},
-	{GPIO_EN_VDD_CPU, 1, 0},
+	{ GPIO_EN_VDD_MEDIA_ML, 1, 0 }, { GPIO_EN_VDD_GPU, 1, 0 },
+	{ GPIO_EN_VDD_CPU, 1, 0 },
 };
 
 /* The power sequence for POWER_S5G3 */
 static const struct power_seq_op s5g3_power_seq[] = {
-	{GPIO_EN_PP1800_VDD33_PMC_X, 0, 4},
+	{ GPIO_EN_PP1800_VDD33_PMC_X, 0, 4 },
 
-	{GPIO_EN_VDD_SOC, 0, 0},
+	{ GPIO_EN_VDD_SOC, 0, 0 },
 
-	{GPIO_EN_PP0800_VDD_PMC_X, 0, 4},
+	{ GPIO_EN_PP0800_VDD_PMC_X, 0, 4 },
 
-	{GPIO_EN_PP1800_VDDIO_PMC_X, 0, 4},
+	{ GPIO_EN_PP1800_VDDIO_PMC_X, 0, 4 },
 
-	{GPIO_EN_PP1800_S5, 0, 4},
+	{ GPIO_EN_PP1800_S5, 0, 4 },
 
-	{GPIO_EN_PP5000_S5, 0, 4},
+	{ GPIO_EN_PP5000_S5, 0, 4 },
 };
 
 /* most recently received sleep event */
@@ -265,7 +233,7 @@ enum power_state power_chipset_init(void)
 	} else if (reset_flags & EC_RESET_FLAG_AP_OFF) {
 		exit_hard_off = 0;
 	} else if ((reset_flags & EC_RESET_FLAG_HIBERNATE) &&
-			gpio_get_level(GPIO_AC_PRESENT)) {
+		   gpio_get_level(GPIO_AC_PRESENT)) {
 		/*
 		 * If AC present, assume this is a wake-up by AC insert.
 		 * Boot EC only.
@@ -324,8 +292,7 @@ static void power_seq_run(const struct power_seq_op *power_seq_ops,
 	int i;
 
 	for (i = 0; i < op_count; i++) {
-		GPIO_SET_LEVEL(power_seq_ops[i].signal,
-			       power_seq_ops[i].level);
+		GPIO_SET_LEVEL(power_seq_ops[i].signal, power_seq_ops[i].level);
 		if (!power_seq_ops[i].delay)
 			continue;
 		msleep(power_seq_ops[i].delay);
@@ -491,9 +458,9 @@ static void power_button_changed(void)
 DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, power_button_changed, HOOK_PRIO_DEFAULT);
 
 #ifdef CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-__override void power_chipset_handle_host_sleep_event(
-		enum host_sleep_event state,
-		struct host_sleep_event_context *ctx)
+__override void
+power_chipset_handle_host_sleep_event(enum host_sleep_event state,
+				      struct host_sleep_event_context *ctx)
 {
 	CPRINTS("Handle sleep: %d", state);
 
diff --git a/power/host_sleep.c b/power/host_sleep.c
index e352e677f2..b6f0de498e 100644
--- a/power/host_sleep.c
+++ b/power/host_sleep.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,15 +12,15 @@
 #include "util.h"
 
 /* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ##args)
 
 /* Track last reported sleep event */
 static enum host_sleep_event host_sleep_state;
 
-__overridable void power_chipset_handle_host_sleep_event(
-		enum host_sleep_event state,
-		struct host_sleep_event_context *ctx)
+__overridable void
+power_chipset_handle_host_sleep_event(enum host_sleep_event state,
+				      struct host_sleep_event_context *ctx)
 {
 	/* Default weak implementation -- no action required. */
 }
@@ -71,8 +71,7 @@ host_command_host_sleep_event(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_HOST_SLEEP_EVENT,
-		     host_command_host_sleep_event,
+DECLARE_HOST_COMMAND(EC_CMD_HOST_SLEEP_EVENT, host_command_host_sleep_event,
 		     EC_VER_MASK(0) | EC_VER_MASK(1));
 
 enum host_sleep_event power_get_host_sleep_state(void)
@@ -116,14 +115,13 @@ static enum sleep_hang_type timeout_hang_type;
 static void sleep_transition_timeout(void);
 DECLARE_DEFERRED(sleep_transition_timeout);
 
-__overridable void power_board_handle_sleep_hang(
-		enum sleep_hang_type hang_type)
+__overridable void power_board_handle_sleep_hang(enum sleep_hang_type hang_type)
 {
 	/* Default empty implementation */
 }
 
-__overridable void power_chipset_handle_sleep_hang(
-		enum sleep_hang_type hang_type)
+__overridable void
+power_chipset_handle_sleep_hang(enum sleep_hang_type hang_type)
 {
 	/* Default empty implementation */
 }
@@ -213,7 +211,7 @@ void sleep_reset_tracking(void)
 	timeout_hang_type = SLEEP_HANG_NONE;
 }
 
-static int command_sleep_fail_timeout(int argc, char **argv)
+static int command_sleep_fail_timeout(int argc, const char **argv)
 {
 	if (argc < 2) {
 		/* no arguments - just print the current timeout */
@@ -231,7 +229,7 @@ static int command_sleep_fail_timeout(int argc, char **argv)
 
 		if (val <= 0 || val >= EC_HOST_SLEEP_TIMEOUT_INFINITE) {
 			ccprintf("Error: timeout range is 1..%d [msec]\n",
-				EC_HOST_SLEEP_TIMEOUT_INFINITE - 1);
+				 EC_HOST_SLEEP_TIMEOUT_INFINITE - 1);
 			return EC_ERROR_PARAM1;
 		}
 
@@ -242,19 +240,18 @@ static int command_sleep_fail_timeout(int argc, char **argv)
 		ccprintf("Sleep failure detection timeout is disabled\n");
 	else
 		ccprintf("Sleep failure detection timeout is %d [msec]\n",
-			host_sleep_timeout_default);
+			 host_sleep_timeout_default);
 
 	return EC_SUCCESS;
 }
 DECLARE_CONSOLE_COMMAND(sleeptimeout, command_sleep_fail_timeout,
-		"[default | infinite | <msec>]",
-		"Display or set host sleep failure detection timeout.\n"
-		"Valid arguments are:\n"
-		" default\n"
-		" infinite - disables the timeout\n"
-		" <msec> - custom length in milliseconds\n"
-		" <none> - prints the current setting");
-
+			"[default | infinite | <msec>]",
+			"Display or set host sleep failure detection timeout.\n"
+			"Valid arguments are:\n"
+			" default\n"
+			" infinite - disables the timeout\n"
+			" <msec> - custom length in milliseconds\n"
+			" <none> - prints the current setting");
 
 #else /* !CONFIG_POWER_SLEEP_FAILURE_DETECTION */
 
diff --git a/power/icelake.c b/power/icelake.c
index 00248061e9..2fae215ab1 100644
--- a/power/icelake.c
+++ b/power/icelake.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,20 +17,19 @@
 #include "timer.h"
 
 /* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 #ifdef CONFIG_BRINGUP
 #define GPIO_SET_LEVEL(signal, value) \
 	gpio_set_level_verbose(CC_CHIPSET, signal, value)
 #else
-#define GPIO_SET_LEVEL(signal, value) \
-	gpio_set_level(signal, value)
+#define GPIO_SET_LEVEL(signal, value) gpio_set_level(signal, value)
 #endif
 
 /* The wait time is ~150 msec, allow for safety margin. */
-#define IN_PCH_SLP_SUS_WAIT_TIME_USEC	(250 * MSEC)
+#define IN_PCH_SLP_SUS_WAIT_TIME_USEC (250 * MSEC)
 
-static int forcing_shutdown;  /* Forced shutdown in progress? */
+static int forcing_shutdown; /* Forced shutdown in progress? */
 
 /* Power signals list. Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
@@ -152,7 +151,7 @@ void chipset_handle_espi_reset_assert(void)
 	 * power button. If yes, release power button.
 	 */
 	if ((power_get_signals() & IN_PCH_SLP_SUS_DEASSERTED) &&
-		forcing_shutdown) {
+	    forcing_shutdown) {
 		power_button_pch_release();
 		forcing_shutdown = 0;
 	}
@@ -171,7 +170,6 @@ static void enable_pp5000_rail(void)
 		power_5v_enable(task_get_current(), 1);
 	else
 		GPIO_SET_LEVEL(GPIO_EN_PP5000, 1);
-
 }
 
 static void dsw_pwrok_pass_thru(void)
@@ -180,8 +178,8 @@ static void dsw_pwrok_pass_thru(void)
 
 	/* Pass-through DSW_PWROK to ICL. */
 	if (dswpwrok_in != gpio_get_level(GPIO_PCH_DSW_PWROK)) {
-		if (IS_ENABLED(CONFIG_CHIPSET_SLP_S3_L_OVERRIDE)
-			&& dswpwrok_in) {
+		if (IS_ENABLED(CONFIG_CHIPSET_SLP_S3_L_OVERRIDE) &&
+		    dswpwrok_in) {
 			/*
 			 * Once DSW_PWROK is high, reconfigure SLP_S3_L back to
 			 * an input after a short delay.
@@ -208,7 +206,7 @@ static void dsw_pwrok_pass_thru(void)
  * &param level		0 deasserts the signal, other values assert the signal
  */
 static void pwrok_signal_set(const struct intel_x86_pwrok_signal *signal,
-	int level)
+			     int level)
 {
 	GPIO_SET_LEVEL(signal->gpio, signal->active_low ? !level : level);
 }
@@ -257,7 +255,6 @@ enum power_state power_handle_state(enum power_state state)
 	common_intel_x86_handle_rsmrst(state);
 
 	switch (state) {
-
 	case POWER_G3S5:
 		if (IS_ENABLED(CONFIG_CHIPSET_SLP_S3_L_OVERRIDE)) {
 			/*
@@ -297,7 +294,8 @@ enum power_state power_handle_state(enum power_state state)
 		 * signal doesn't go high within 250 msec then go back to G3.
 		 */
 		if (power_wait_signals_timeout(IN_PCH_SLP_SUS_DEASSERTED,
-				IN_PCH_SLP_SUS_WAIT_TIME_USEC) != EC_SUCCESS) {
+					       IN_PCH_SLP_SUS_WAIT_TIME_USEC) !=
+		    EC_SUCCESS) {
 			CPRINTS("SLP_SUS_L didn't go high!  Going back to G3.");
 			return POWER_S5G3;
 		}
@@ -318,7 +316,7 @@ enum power_state power_handle_state(enum power_state state)
 		GPIO_SET_LEVEL(GPIO_EN_VCCIO_EXT, 1);
 		/* Now wait for ALL_SYS_PWRGD. */
 		while (!intel_x86_get_pg_ec_all_sys_pwrgd() &&
-			(timeout_ms > 0)) {
+		       (timeout_ms > 0)) {
 			msleep(1);
 			timeout_ms--;
 		};
diff --git a/power/intel_x86.c b/power/intel_x86.c
index 35c0482831..1c9f2ef8c8 100644
--- a/power/intel_x86.c
+++ b/power/intel_x86.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,8 +23,8 @@
 #include "wireless.h"
 
 /* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ##args)
 
 enum sys_sleep_state {
 	SYS_SLEEP_S3,
@@ -44,7 +44,7 @@ static const int sleep_sig[] = {
 #endif
 };
 
-static int power_s5_up;       /* Chipset is sequencing up or down */
+static int power_s5_up; /* Chipset is sequencing up or down */
 
 #ifdef CONFIG_CHARGER
 /* Flag to indicate if power up was inhibited due to low battery SOC level. */
@@ -61,7 +61,7 @@ static int is_power_up_inhibited(void)
 	const int power_button_pressed = 0;
 
 	return charge_prevent_power_on(power_button_pressed) ||
-		charge_want_shutdown();
+	       charge_want_shutdown();
 }
 
 static void power_up_inhibited_cb(void)
@@ -179,8 +179,7 @@ static void lpc_s0ix_resume_restore_masks(void)
 	backup_sci_mask = backup_smi_mask = 0;
 }
 
-__override void power_chipset_handle_sleep_hang(
-		enum sleep_hang_type hang_type)
+__override void power_chipset_handle_sleep_hang(enum sleep_hang_type hang_type)
 {
 	/*
 	 * Wake up the AP so they don't just chill in a non-suspended state and
@@ -259,8 +258,8 @@ enum power_state power_chipset_init(void)
 		CPRINTS("already in S0");
 		return POWER_S0;
 	}
-	if ((power_get_signals() & CHIPSET_G3S5_POWERUP_SIGNAL)
-			== CHIPSET_G3S5_POWERUP_SIGNAL) {
+	if ((power_get_signals() & CHIPSET_G3S5_POWERUP_SIGNAL) ==
+	    CHIPSET_G3S5_POWERUP_SIGNAL) {
 		/* case #2 & #3 */
 		CPRINTS("already in S5");
 		return POWER_S5;
@@ -321,16 +320,16 @@ enum power_state common_intel_x86_power_handle_state(enum power_state state)
 			/* Power down to next state */
 			return POWER_S0S3;
 #ifdef CONFIG_POWER_S0IX
-		/*
-		 * SLP_S0 may assert in system idle scenario without a kernel
-		 * freeze call. This may cause interrupt storm since there is
-		 * no freeze/unfreeze of threads/process in the idle scenario.
-		 * Ignore the SLP_S0 assertions in idle scenario by checking
-		 * the host sleep state.
-		 */
-		} else if (power_get_host_sleep_state()
-					== HOST_SLEEP_EVENT_S0IX_SUSPEND &&
-				chipset_get_sleep_signal(SYS_SLEEP_S0IX) == 0) {
+			/*
+			 * SLP_S0 may assert in system idle scenario without a
+			 * kernel freeze call. This may cause interrupt storm
+			 * since there is no freeze/unfreeze of threads/process
+			 * in the idle scenario. Ignore the SLP_S0 assertions in
+			 * idle scenario by checking the host sleep state.
+			 */
+		} else if (power_get_host_sleep_state() ==
+				   HOST_SLEEP_EVENT_S0IX_SUSPEND &&
+			   chipset_get_sleep_signal(SYS_SLEEP_S0IX) == 0) {
 			return POWER_S0S0ix;
 		} else {
 			sleep_notify_transition(SLEEP_NOTIFY_RESUME,
@@ -344,7 +343,7 @@ enum power_state common_intel_x86_power_handle_state(enum power_state state)
 	case POWER_S0ix:
 		/* System in S0 only if SLP_S0 and SLP_S3 are de-asserted */
 		if ((chipset_get_sleep_signal(SYS_SLEEP_S0IX) == 1) &&
-		   (chipset_get_sleep_signal(SYS_SLEEP_S3) == 1)) {
+		    (chipset_get_sleep_signal(SYS_SLEEP_S3) == 1)) {
 			return POWER_S0ixS0;
 		} else if (!power_has_signals(IN_PGOOD_ALL_CORE)) {
 			return POWER_S0;
@@ -572,8 +571,8 @@ void common_intel_x86_handle_rsmrst(enum power_state state)
 	board_before_rsmrst(rsmrst_in);
 
 	/* Only passthrough RSMRST_L de-assertion on power up */
-	if (IS_ENABLED(CONFIG_CHIPSET_X86_RSMRST_AFTER_S5) &&
-		rsmrst_in && !power_s5_up)
+	if (IS_ENABLED(CONFIG_CHIPSET_X86_RSMRST_AFTER_S5) && rsmrst_in &&
+	    !power_s5_up)
 		return;
 	/*
 	 * Wait at least 10ms between power signals going high
@@ -591,15 +590,15 @@ void common_intel_x86_handle_rsmrst(enum power_state state)
 
 #ifdef CONFIG_POWER_TRACK_HOST_SLEEP_STATE
 
-__overridable void power_board_handle_host_sleep_event(
-		enum host_sleep_event state)
+__overridable void
+power_board_handle_host_sleep_event(enum host_sleep_event state)
 {
 	/* Default weak implementation -- no action required. */
 }
 
-__override void power_chipset_handle_host_sleep_event(
-		enum host_sleep_event state,
-		struct host_sleep_event_context *ctx)
+__override void
+power_chipset_handle_host_sleep_event(enum host_sleep_event state,
+				      struct host_sleep_event_context *ctx)
 {
 	power_board_handle_host_sleep_event(state);
 
@@ -635,7 +634,6 @@ __override void power_chipset_handle_host_sleep_event(
 		power_signal_disable_interrupt(sleep_sig[SYS_SLEEP_S0IX]);
 	}
 #endif
-
 }
 
 #endif
@@ -687,8 +685,7 @@ enum ec_error_list intel_x86_wait_power_up_ok(void)
 	 * Allow charger to be initialized for up to defined tries,
 	 * in case we're trying to boot the AP with no battery.
 	 */
-	while ((tries < CHARGER_INITIALIZED_TRIES) &&
-	       is_power_up_inhibited()) {
+	while ((tries < CHARGER_INITIALIZED_TRIES) && is_power_up_inhibited()) {
 		msleep(CHARGER_INITIALIZED_DELAY_MS);
 		tries++;
 	}
diff --git a/power/meteorlake.c b/power/meteorlake.c
index 80785c2345..c13ed1694d 100644
--- a/power/meteorlake.c
+++ b/power/meteorlake.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,14 +20,13 @@
 #include "timer.h"
 
 /* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 #ifdef CONFIG_BRINGUP
 #define GPIO_SET_LEVEL(signal, value) \
 	gpio_set_level_verbose(CC_CHIPSET, signal, value)
 #else
-#define GPIO_SET_LEVEL(signal, value) \
-	gpio_set_level(signal, value)
+#define GPIO_SET_LEVEL(signal, value) gpio_set_level(signal, value)
 #endif
 
 /* Power signals list. Must match order of enum power_signal. */
@@ -117,7 +116,6 @@ static void enable_pp5000_rail(void)
 		power_5v_enable(task_get_current(), 1);
 	else
 		GPIO_SET_LEVEL(GPIO_EN_PP5000, 1);
-
 }
 
 /*
@@ -126,7 +124,7 @@ static void enable_pp5000_rail(void)
  * &param level		0 deasserts the signal, other values assert the signal
  */
 static void pwrok_signal_set(const struct intel_x86_pwrok_signal *signal,
-	int level)
+			     int level)
 {
 	GPIO_SET_LEVEL(signal->gpio, signal->active_low ? !level : level);
 }
@@ -167,8 +165,9 @@ static void all_sys_pwrgd_pass_thru(void)
 	}
 
 	/* PCH_PWROK is combination of ALL_SYS_PWRGD and SLP_S3 */
-	gpio_set_level(GPIO_PCH_PWROK, all_sys_pwrgd_in &&
-				power_signal_get_level(SLP_S3_SIGNAL_L));
+	gpio_set_level(GPIO_PCH_PWROK,
+		       all_sys_pwrgd_in &&
+			       power_signal_get_level(SLP_S3_SIGNAL_L));
 }
 
 enum power_state power_handle_state(enum power_state state)
@@ -178,7 +177,6 @@ enum power_state power_handle_state(enum power_state state)
 	common_intel_x86_handle_rsmrst(state);
 
 	switch (state) {
-
 	case POWER_G3S5:
 		if (IS_ENABLED(CONFIG_CHIPSET_SLP_S3_L_OVERRIDE)) {
 			/*
diff --git a/power/mt817x.c b/power/mt817x.c
index 30d3ffed1e..a50e66b156 100644
--- a/power/mt817x.c
+++ b/power/mt817x.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,6 +26,7 @@
  */
 
 #include "battery.h"
+#include "builtin/assert.h"
 #include "chipset.h" /* ./common/chipset.c implements chipset functions too */
 #include "common.h"
 #include "gpio.h"
@@ -40,38 +41,38 @@
 #include "test_util.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
-#define INT_BOTH_PULL_UP	(GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH)
+#define INT_BOTH_PULL_UP (GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH)
 
 /* masks for power signals */
 #define IN_POWER_GOOD POWER_SIGNAL_MASK(MTK_POWER_GOOD)
 #define IN_SUSPEND POWER_SIGNAL_MASK(MTK_SUSPEND_ASSERTED)
 
 /* Long power key press to force shutdown */
-#define DELAY_FORCE_SHUTDOWN  (8000 * MSEC)	/* 8 seconds */
+#define DELAY_FORCE_SHUTDOWN (8000 * MSEC) /* 8 seconds */
 
 /*
  * The power signal from SoC should be kept at least 50ms.
  */
-#define POWER_DEBOUNCE_TIME     (50 * MSEC)
+#define POWER_DEBOUNCE_TIME (50 * MSEC)
 
 /*
  * The suspend signal from SoC should be kept at least 50ms.
  */
-#define SUSPEND_DEBOUNCE_TIME   (50 * MSEC)
+#define SUSPEND_DEBOUNCE_TIME (50 * MSEC)
 
 /*
  * The time to bootup the PMIC from power-off to power-on.
  */
-#define PMIC_PWRON_PRESS_TIME   (5000 * MSEC)
+#define PMIC_PWRON_PRESS_TIME (5000 * MSEC)
 
 /*
  * The minimum time to assert the PMIC THERM pin is 32us. However,
  * it needs to be extended to about 50ms to let the 5V rail
  * dissipate fully.
  */
-#define PMIC_THERM_HOLD_TIME  (50 * MSEC)
+#define PMIC_THERM_HOLD_TIME (50 * MSEC)
 
 /*
  * If the power key is pressed to turn on, then held for this long, we
@@ -81,7 +82,7 @@
  *    into the inner loop, waiting for next event to occur (power button
  *    press or POWER_GOOD == 0).
  */
-#define DELAY_SHUTDOWN_ON_POWER_HOLD	(8000 * MSEC)	/* 8 seconds */
+#define DELAY_SHUTDOWN_ON_POWER_HOLD (8000 * MSEC) /* 8 seconds */
 
 /*
  * The hold time for pulling down the PMIC_WARM_RESET_H pin so that
@@ -387,9 +388,8 @@ static void mtk_lid_event(void)
 	/* Override the panel backlight enable signal from SoC,
 	 * force the backlight off on lid close.
 	 */
-	bl_override = lid_is_open() ?
-		MTK_BACKLIGHT_CONTROL_BY_SOC :
-		MTK_BACKLIGHT_FORCE_OFF;
+	bl_override = lid_is_open() ? MTK_BACKLIGHT_CONTROL_BY_SOC :
+				      MTK_BACKLIGHT_FORCE_OFF;
 	mtk_backlight_override(bl_override);
 
 	/* Power task only cares about lid-open events */
@@ -539,7 +539,8 @@ static int check_for_power_on_event(void)
 			CPRINTS("system is on, but EC_RESET_FLAG_AP_OFF is on");
 			return POWER_ON_CANCEL;
 		} else {
-			CPRINTS("system is on, thus clear " "auto_power_on");
+			CPRINTS("system is on, thus clear "
+				"auto_power_on");
 			/* no need to arrange another power on */
 			auto_power_on = 0;
 			return POWER_ON_BY_IN_POWER_GOOD;
@@ -784,14 +785,14 @@ enum power_state_t {
 	PSTATE_COUNT,
 };
 
-static const char * const state_name[] = {
+static const char *const state_name[] = {
 	"unknown",
 	"off",
 	"suspend",
 	"on",
 };
 
-static int command_power(int argc, char **argv)
+static int command_power(int argc, const char **argv)
 {
 	int v;
 
@@ -819,6 +820,4 @@ static int command_power(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(power, command_power,
-			"on/off",
-			"Turn AP power on/off");
+DECLARE_CONSOLE_COMMAND(power, command_power, "on/off", "Turn AP power on/off");
diff --git a/power/mt8183.c b/power/mt8183.c
index f62ddafb51..eec8796427 100644
--- a/power/mt8183.c
+++ b/power/mt8183.c
@@ -1,10 +1,11 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* mt8183 chipset power control module for Chrome EC */
 
+#include "builtin/assert.h"
 #include "charge_state.h"
 #include "chipset.h"
 #include "common.h"
@@ -30,29 +31,29 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 /* Input state flags */
-#define IN_PGOOD_PMIC		POWER_SIGNAL_MASK(PMIC_PWR_GOOD)
-#define IN_SUSPEND_ASSERTED	POWER_SIGNAL_MASK(AP_IN_S3_L)
+#define IN_PGOOD_PMIC POWER_SIGNAL_MASK(PMIC_PWR_GOOD)
+#define IN_SUSPEND_ASSERTED POWER_SIGNAL_MASK(AP_IN_S3_L)
 
 /* Rails required for S3 and S0 */
-#define IN_PGOOD_S0		(IN_PGOOD_PMIC)
-#define IN_PGOOD_S3		(IN_PGOOD_PMIC)
+#define IN_PGOOD_S0 (IN_PGOOD_PMIC)
+#define IN_PGOOD_S3 (IN_PGOOD_PMIC)
 
 /* All inputs in the right state for S0 */
-#define IN_ALL_S0		(IN_PGOOD_S0 & ~IN_SUSPEND_ASSERTED)
+#define IN_ALL_S0 (IN_PGOOD_S0 & ~IN_SUSPEND_ASSERTED)
 
 /* Long power key press to force shutdown in S0. go/crosdebug */
 #ifdef VARIANT_KUKUI_JACUZZI
-#define FORCED_SHUTDOWN_DELAY	(8 * SECOND)
+#define FORCED_SHUTDOWN_DELAY (8 * SECOND)
 #else
-#define FORCED_SHUTDOWN_DELAY	(10 * SECOND)
+#define FORCED_SHUTDOWN_DELAY (10 * SECOND)
 #endif
 
 /* Long power key press to boot from S5/G3 state. */
 #ifndef POWERBTN_BOOT_DELAY
-#define POWERBTN_BOOT_DELAY	(1 * SECOND)
+#define POWERBTN_BOOT_DELAY (1 * SECOND)
 #endif
 
 #define CHARGER_INITIALIZED_DELAY_MS 100
@@ -96,12 +97,10 @@ static const struct power_seq_op s5s3_power_seq[] = {
 };
 
 /* The power sequence for POWER_S3S0 */
-static const struct power_seq_op s3s0_power_seq[] = {
-};
+static const struct power_seq_op s3s0_power_seq[] = {};
 
 /* The power sequence for POWER_S0S3 */
-static const struct power_seq_op s0s3_power_seq[] = {
-};
+static const struct power_seq_op s0s3_power_seq[] = {};
 
 /* The power sequence for POWER_S3S5 */
 static const struct power_seq_op s3s5_power_seq[] = {
@@ -261,8 +260,7 @@ static void power_seq_run(const struct power_seq_op *power_seq_ops,
 	int i;
 
 	for (i = 0; i < op_count; i++) {
-		gpio_set_level(power_seq_ops[i].signal,
-			       power_seq_ops[i].level);
+		gpio_set_level(power_seq_ops[i].signal, power_seq_ops[i].level);
 		if (!power_seq_ops[i].delay)
 			continue;
 		msleep(power_seq_ops[i].delay);
@@ -351,8 +349,7 @@ enum power_state power_handle_state(enum power_state state)
 		break;
 
 	case POWER_S0:
-		if (!power_has_signals(IN_PGOOD_S0) ||
-		    forcing_shutdown ||
+		if (!power_has_signals(IN_PGOOD_S0) || forcing_shutdown ||
 		    power_get_signals() & IN_SUSPEND_ASSERTED)
 			return POWER_S0S3;
 
@@ -525,7 +522,7 @@ enum power_state power_handle_state(enum power_state state)
 		if (power_button_is_pressed()) {
 			forcing_shutdown = 1;
 			hook_call_deferred(&chipset_force_shutdown_button_data,
-					-1);
+					   -1);
 		}
 
 		return POWER_S3;
@@ -564,7 +561,7 @@ enum power_state power_handle_state(enum power_state state)
 			gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 0);
 			msleep(5);
 			hook_call_deferred(&release_pmic_force_reset_data,
-				PMIC_FORCE_RESET_TIME);
+					   PMIC_FORCE_RESET_TIME);
 
 			return POWER_S5G3;
 		}
@@ -581,16 +578,15 @@ enum power_state power_handle_state(enum power_state state)
 }
 
 #ifdef CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-__override void power_chipset_handle_sleep_hang(
-		enum sleep_hang_type hang_type)
+__override void power_chipset_handle_sleep_hang(enum sleep_hang_type hang_type)
 {
 	CPRINTS("Warning: Detected sleep hang! Waking host up!");
 	host_set_single_event(EC_HOST_EVENT_HANG_DETECT);
 }
 
-__override void power_chipset_handle_host_sleep_event(
-		enum host_sleep_event state,
-		struct host_sleep_event_context *ctx)
+__override void
+power_chipset_handle_host_sleep_event(enum host_sleep_event state,
+				      struct host_sleep_event_context *ctx)
 {
 	CPRINTS("Handle sleep: %d", state);
 
@@ -611,7 +607,6 @@ __override void power_chipset_handle_host_sleep_event(
 		sleep_set_notify(SLEEP_NOTIFY_RESUME);
 		task_wake(TASK_ID_CHIPSET);
 		sleep_complete_resume(ctx);
-
 	}
 }
 #endif /* CONFIG_POWER_TRACK_HOST_SLEEP_STATE */
diff --git a/power/mt8186.c b/power/mt8186.c
index 39fc636127..b05700b599 100644
--- a/power/mt8186.c
+++ b/power/mt8186.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,8 +21,8 @@
  *  - Pressing and releaseing power within that 8s is ignored
  */
 
-#include "assert.h"
 #include "battery.h"
+#include "builtin/assert.h"
 #include "chipset.h"
 #include "common.h"
 #include "gpio.h"
@@ -71,10 +71,11 @@
 #ifndef CONFIG_ZEPHYR
 /* power signal list.  Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
-	{GPIO_AP_EC_SYSRST_ODL, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_RST"},
-	{GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3"},
-	{GPIO_AP_EC_WDTRST_L, POWER_SIGNAL_ACTIVE_LOW, "AP_WDT_ASSERTED"},
-	{GPIO_AP_EC_WARM_RST_REQ, POWER_SIGNAL_ACTIVE_HIGH, "AP_WARM_RST_REQ"},
+	{ GPIO_AP_EC_SYSRST_ODL, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_RST" },
+	{ GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3" },
+	{ GPIO_AP_EC_WDTRST_L, POWER_SIGNAL_ACTIVE_LOW, "AP_WDT_ASSERTED" },
+	{ GPIO_AP_EC_WARM_RST_REQ, POWER_SIGNAL_ACTIVE_HIGH,
+	  "AP_WARM_RST_REQ" },
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 #endif /* CONFIG_ZEPHYR */
@@ -136,7 +137,7 @@ DECLARE_DEFERRED(release_power_button);
 
 void chipset_force_shutdown(enum chipset_shutdown_reason reason)
 {
-	CPRINTS("%s(%d)", __func__, reason);
+	CPRINTS("%s: 0x%x", __func__, reason);
 	report_ap_reset(reason);
 
 	is_shutdown = true;
@@ -145,10 +146,12 @@ void chipset_force_shutdown(enum chipset_shutdown_reason reason)
 	 * transitions to G3.
 	 */
 	GPIO_SET_LEVEL(GPIO_SYS_RST_ODL, 0);
-	CPRINTS("Forcing pmic off with long press.");
-	GPIO_SET_LEVEL(GPIO_EC_PMIC_EN_ODL, 0);
-	hook_call_deferred(&release_power_button_data,
-			   FORCED_SHUTDOWN_DELAY + SECOND);
+	if (reason != CHIPSET_SHUTDOWN_BUTTON) {
+		CPRINTS("Forcing pmic off with long press.");
+		GPIO_SET_LEVEL(GPIO_EC_PMIC_EN_ODL, 0);
+		hook_call_deferred(&release_power_button_data,
+				   FORCED_SHUTDOWN_DELAY + SECOND);
+	}
 
 	task_wake(TASK_ID_CHIPSET);
 }
@@ -191,7 +194,7 @@ DECLARE_DEFERRED(reset_flag_deferred);
 
 void chipset_reset(enum chipset_shutdown_reason reason)
 {
-	CPRINTS("%s: %d", __func__, reason);
+	CPRINTS("%s: 0x%x", __func__, reason);
 	report_ap_reset(reason);
 
 	is_resetting = true;
@@ -278,7 +281,7 @@ enum power_state power_chipset_init(void)
 	} else if (system_get_reset_flags() & EC_RESET_FLAG_AP_OFF) {
 		exit_hard_off = 0;
 	} else if ((system_get_reset_flags() & EC_RESET_FLAG_HIBERNATE) &&
-			gpio_get_level(GPIO_AC_PRESENT)) {
+		   gpio_get_level(GPIO_AC_PRESENT)) {
 		/*
 		 * If AC present, assume this is a wake-up by AC insert.
 		 * Boot EC only.
@@ -297,9 +300,14 @@ enum power_state power_chipset_init(void)
 		 */
 		battery_wait_for_stable();
 
-	if (exit_hard_off)
-		/* Auto-power on */
-		mt8186_exit_off();
+	if (exit_hard_off) {
+		if (init_state == POWER_S5 || init_state == POWER_G3) {
+			/* Auto-power on */
+			mt8186_exit_off();
+		} else {
+			is_exiting_off = false;
+		}
+	}
 
 	if (init_state != POWER_G3 && !exit_hard_off)
 		/* Force shutdown from S5 if the PMIC is already up. */
@@ -365,7 +373,6 @@ enum power_state power_handle_state(enum power_state state)
 			/* Give up, go back to G3. */
 			return POWER_S5G3;
 
-		msleep(500);
 		/* Call hooks now that rails are up */
 		hook_notify(HOOK_CHIPSET_STARTUP);
 		/*
@@ -420,9 +427,18 @@ enum power_state power_handle_state(enum power_state state)
 		 * In case the power button is held awaiting power-off timeout,
 		 * power off immediately now that we're entering S3.
 		 */
-		if (power_button_is_pressed())
+		if (power_button_is_pressed()) {
 			hook_call_deferred(&chipset_force_shutdown_button_data,
 					   -1);
+			/*
+			 * if the ap is shutting down, but it doesn't report
+			 * the reason, report it now.
+			 */
+			if (!is_shutdown)
+				chipset_force_shutdown_button();
+		}
+
+		hook_notify(HOOK_CHIPSET_SUSPEND_COMPLETE);
 
 		return POWER_S3;
 
@@ -473,16 +489,15 @@ static void power_button_changed(void)
 DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, power_button_changed, HOOK_PRIO_DEFAULT);
 
 #ifdef CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-__override void power_chipset_handle_sleep_hang(
-		enum sleep_hang_type hang_type)
+__override void power_chipset_handle_sleep_hang(enum sleep_hang_type hang_type)
 {
 	CPRINTS("Warning: Detected sleep hang! Waking host up!");
 	host_set_single_event(EC_HOST_EVENT_HANG_DETECT);
 }
 
-__override void power_chipset_handle_host_sleep_event(
-		enum host_sleep_event state,
-		struct host_sleep_event_context *ctx)
+__override void
+power_chipset_handle_host_sleep_event(enum host_sleep_event state,
+				      struct host_sleep_event_context *ctx)
 {
 	CPRINTS("Handle sleep: %d", state);
 
@@ -503,7 +518,6 @@ __override void power_chipset_handle_host_sleep_event(
 		sleep_set_notify(SLEEP_NOTIFY_RESUME);
 		task_wake(TASK_ID_CHIPSET);
 		sleep_complete_resume(ctx);
-
 	}
 }
 #endif /* CONFIG_POWER_TRACK_HOST_SLEEP_STATE */
diff --git a/power/mt8192.c b/power/mt8192.c
index fc99bce5e0..67dcc2fec6 100644
--- a/power/mt8192.c
+++ b/power/mt8192.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,6 +22,7 @@
  */
 
 #include "battery.h"
+#include "builtin/assert.h"
 #include "chipset.h"
 #include "common.h"
 #include "gpio.h"
@@ -81,9 +82,9 @@
 
 /* power signal list.  Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
-	{GPIO_PMIC_EC_PWRGD, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"},
-	{GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L"},
-	{GPIO_AP_EC_WATCHDOG_L, POWER_SIGNAL_ACTIVE_LOW, "AP_WDT_ASSERTED"},
+	{ GPIO_PMIC_EC_PWRGD, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" },
+	{ GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" },
+	{ GPIO_AP_EC_WATCHDOG_L, POWER_SIGNAL_ACTIVE_LOW, "AP_WDT_ASSERTED" },
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
@@ -204,6 +205,7 @@ DECLARE_HOOK(HOOK_CHIPSET_RESET, handle_chipset_reset, HOOK_PRIO_FIRST);
 enum power_state power_chipset_init(void)
 {
 	int exit_hard_off = 1;
+	uint32_t reset_flags = system_get_reset_flags();
 
 	/* Enable reboot / sleep control inputs from AP */
 	gpio_enable_interrupt(GPIO_AP_EC_WARM_RST_REQ);
@@ -216,10 +218,11 @@ enum power_state power_chipset_init(void)
 			CPRINTS("already in S0");
 			return POWER_S0;
 		}
-	} else if (system_get_reset_flags() & EC_RESET_FLAG_AP_OFF) {
+	} else if ((reset_flags & EC_RESET_FLAG_AP_OFF) ||
+		   (reset_flags & EC_RESET_FLAG_AP_IDLE)) {
 		exit_hard_off = 0;
-	} else if ((system_get_reset_flags() & EC_RESET_FLAG_HIBERNATE) &&
-			gpio_get_level(GPIO_AC_PRESENT)) {
+	} else if ((reset_flags & EC_RESET_FLAG_HIBERNATE) &&
+		   gpio_get_level(GPIO_AC_PRESENT)) {
 		/*
 		 * If AC present, assume this is a wake-up by AC insert.
 		 * Boot EC only.
@@ -392,6 +395,11 @@ enum power_state power_handle_state(enum power_state state)
 		return POWER_S3;
 
 	case POWER_S3S0:
+#ifdef CONFIG_CHIPSET_RESUME_INIT_HOOK
+		/* Call hooks prior to chipset resume */
+		hook_notify(HOOK_CHIPSET_RESUME_INIT);
+#endif
+
 		if (power_wait_signals(IN_PGOOD_S0)) {
 			chipset_force_shutdown(CHIPSET_SHUTDOWN_WAIT);
 			return POWER_S0S3;
@@ -416,6 +424,10 @@ enum power_state power_handle_state(enum power_state state)
 	case POWER_S0S3:
 		/* Call hooks before we remove power rails */
 		hook_notify(HOOK_CHIPSET_SUSPEND);
+#ifdef CONFIG_CHIPSET_RESUME_INIT_HOOK
+		/* Call hooks after chipset suspend */
+		hook_notify(HOOK_CHIPSET_SUSPEND_COMPLETE);
+#endif
 
 #ifdef CONFIG_POWER_SLEEP_FAILURE_DETECTION
 		sleep_suspend_transition();
@@ -505,16 +517,16 @@ static void power_button_changed(void)
 DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, power_button_changed, HOOK_PRIO_DEFAULT);
 
 #ifdef CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-__overridable void power_chipset_handle_sleep_hang(
-		enum sleep_hang_type hang_type)
+__overridable void
+power_chipset_handle_sleep_hang(enum sleep_hang_type hang_type)
 {
 	CPRINTS("Warning: Detected sleep hang! Waking host up!");
 	host_set_single_event(EC_HOST_EVENT_HANG_DETECT);
 }
 
-__override void power_chipset_handle_host_sleep_event(
-		enum host_sleep_event state,
-		struct host_sleep_event_context *ctx)
+__override void
+power_chipset_handle_host_sleep_event(enum host_sleep_event state,
+				      struct host_sleep_event_context *ctx)
 {
 	CPRINTS("Handle sleep: %d", state);
 
@@ -535,7 +547,6 @@ __override void power_chipset_handle_host_sleep_event(
 		sleep_set_notify(SLEEP_NOTIFY_RESUME);
 		task_wake(TASK_ID_CHIPSET);
 		sleep_complete_resume(ctx);
-
 	}
 }
 #endif /* CONFIG_POWER_TRACK_HOST_SLEEP_STATE */
diff --git a/power/qcom.c b/power/qcom.c
index 107bdcb04d..418f2b3136 100644
--- a/power/qcom.c
+++ b/power/qcom.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,6 +22,7 @@
  *  - If POWER_GOOD is dropped by the AP, then we power the AP off
  */
 
+#include "builtin/assert.h"
 #include "charge_state.h"
 #include "chipset.h"
 #include "common.h"
@@ -35,7 +36,7 @@
 #include "task.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 /* Power signal list. Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
@@ -75,13 +76,12 @@ const struct power_signal_info power_signal_list[] = {
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
 /* Masks for power signals */
-#define IN_POWER_GOOD		POWER_SIGNAL_MASK(SC7X80_POWER_GOOD)
-#define IN_AP_RST_ASSERTED	POWER_SIGNAL_MASK(SC7X80_AP_RST_ASSERTED)
-#define IN_SUSPEND		POWER_SIGNAL_MASK(SC7X80_AP_SUSPEND)
-
+#define IN_POWER_GOOD POWER_SIGNAL_MASK(SC7X80_POWER_GOOD)
+#define IN_AP_RST_ASSERTED POWER_SIGNAL_MASK(SC7X80_AP_RST_ASSERTED)
+#define IN_SUSPEND POWER_SIGNAL_MASK(SC7X80_AP_SUSPEND)
 
 /* Long power key press to force shutdown */
-#define DELAY_FORCE_SHUTDOWN		(8 * SECOND)
+#define DELAY_FORCE_SHUTDOWN (8 * SECOND)
 
 /*
  * If the power button is pressed to turn on, then held for this long, we
@@ -91,37 +91,37 @@ BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
  *    into the inner loop, waiting for next event to occur (power button
  *    press or POWER_GOOD == 0).
  */
-#define DELAY_SHUTDOWN_ON_POWER_HOLD	(8 * SECOND)
+#define DELAY_SHUTDOWN_ON_POWER_HOLD (8 * SECOND)
 
 /*
  * After trigger PMIC power sequence, how long it triggers AP to turn on
  * or off. Observed that the worst case is ~150ms. Pick a safe vale.
  */
-#define PMIC_POWER_AP_RESPONSE_TIMEOUT	(350 * MSEC)
+#define PMIC_POWER_AP_RESPONSE_TIMEOUT (350 * MSEC)
 
 /*
  * After force off the switch cap, how long the PMIC/AP totally off.
  * Observed that the worst case is 2s. Pick a safe vale.
  */
-#define FORCE_OFF_RESPONSE_TIMEOUT	(4 * SECOND)
+#define FORCE_OFF_RESPONSE_TIMEOUT (4 * SECOND)
 
 /* Wait for polling the AP on signal */
-#define PMIC_POWER_AP_WAIT		(1 * MSEC)
+#define PMIC_POWER_AP_WAIT (1 * MSEC)
 
 /* The length of an issued low pulse to the PMIC_RESIN_L signal */
-#define PMIC_RESIN_PULSE_LENGTH		(20 * MSEC)
+#define PMIC_RESIN_PULSE_LENGTH (20 * MSEC)
 
 /* The timeout of the check if the system can boot AP */
-#define CAN_BOOT_AP_CHECK_TIMEOUT	(1500 * MSEC)
+#define CAN_BOOT_AP_CHECK_TIMEOUT (1500 * MSEC)
 
 /* Wait for polling if the system can boot AP */
-#define CAN_BOOT_AP_CHECK_WAIT		(200 * MSEC)
+#define CAN_BOOT_AP_CHECK_WAIT (200 * MSEC)
 
 /* The timeout of the check if the switchcap outputs good voltage */
-#define SWITCHCAP_PG_CHECK_TIMEOUT	(100 * MSEC)
+#define SWITCHCAP_PG_CHECK_TIMEOUT (100 * MSEC)
 
 /* Wait for polling if the switchcap outputs good voltage */
-#define SWITCHCAP_PG_CHECK_WAIT		(6 * MSEC)
+#define SWITCHCAP_PG_CHECK_WAIT (6 * MSEC)
 
 /*
  * Delay between power-on the system and power-on the PMIC.
@@ -131,7 +131,7 @@ BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
  * Measured on Herobrine IOB + Trogdor MLB, the delay takes ~200ms. Set
  * it with margin.
  */
-#define SYSTEM_POWER_ON_DELAY		(300 * MSEC)
+#define SYSTEM_POWER_ON_DELAY (300 * MSEC)
 
 /*
  * Delay between the PMIC power drop and power-off the system.
@@ -139,17 +139,17 @@ BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
  * this delay to the same value as the above power-on sequence, which
  * has much safer margin.
  */
-#define PMIC_POWER_OFF_DELAY		(150 * MSEC)
+#define PMIC_POWER_OFF_DELAY (150 * MSEC)
 
 /* The AP_RST_L transition count of a normal AP warm reset */
-#define EXPECTED_AP_RST_TRANSITIONS	3
+#define EXPECTED_AP_RST_TRANSITIONS 3
 
 /*
  * The timeout of waiting the next AP_RST_L transition. We measured
  * the interval between AP_RST_L transitions is 130ms ~ 150ms. Pick
  * a safer value.
  */
-#define AP_RST_TRANSITION_TIMEOUT	(450 * MSEC)
+#define AP_RST_TRANSITION_TIMEOUT (450 * MSEC)
 
 /* TODO(crosbug.com/p/25047): move to HOOK_POWER_BUTTON_CHANGE */
 /* 1 if the power button was pressed last time we checked */
@@ -282,9 +282,11 @@ void chipset_warm_reset_interrupt(enum gpio_signal signal)
 			 */
 			ap_rst_overdriven = 1;
 			gpio_set_flags(GPIO_PS_HOLD, GPIO_INT_BOTH |
-				       GPIO_SEL_1P8V | GPIO_OUT_HIGH);
+							     GPIO_SEL_1P8V |
+							     GPIO_OUT_HIGH);
 			gpio_set_flags(GPIO_AP_RST_L, GPIO_INT_BOTH |
-				       GPIO_SEL_1P8V | GPIO_OUT_LOW);
+							      GPIO_SEL_1P8V |
+							      GPIO_OUT_LOW);
 		}
 		/* Ignore the else clause, the pull-up rail drops. */
 	} else {
@@ -315,10 +317,8 @@ void chipset_power_good_interrupt(enum gpio_signal signal)
 		 * When POWER_GOOD drops, high-Z both AP_RST_L and PS_HOLD
 		 * to restore their states.
 		 */
-		gpio_set_flags(GPIO_AP_RST_L, GPIO_INT_BOTH |
-			       GPIO_SEL_1P8V);
-		gpio_set_flags(GPIO_PS_HOLD, GPIO_INT_BOTH |
-			       GPIO_SEL_1P8V);
+		gpio_set_flags(GPIO_AP_RST_L, GPIO_INT_BOTH | GPIO_SEL_1P8V);
+		gpio_set_flags(GPIO_PS_HOLD, GPIO_INT_BOTH | GPIO_SEL_1P8V);
 		ap_rst_overdriven = 0;
 	}
 	power_signal_interrupt(signal);
@@ -590,7 +590,7 @@ enum power_state power_chipset_init(void)
 	if (reset_flags & EC_RESET_FLAG_AP_OFF)
 		auto_power_on = 0;
 	else if (!(reset_flags & EC_RESET_FLAG_EFS) &&
-		    (reset_flags & EC_RESET_FLAG_SYSJUMP))
+		 (reset_flags & EC_RESET_FLAG_SYSJUMP))
 		auto_power_on = 0;
 
 	if (battery_is_present() == BP_YES) {
@@ -666,7 +666,7 @@ static int power_is_enough(void)
 	 * waste the time and exit the loop.
 	 */
 	while (!system_can_boot_ap() && !charge_want_shutdown() &&
-		get_time().val < poll_deadline.val) {
+	       get_time().val < poll_deadline.val) {
 		usleep(CAN_BOOT_AP_CHECK_WAIT);
 	}
 
@@ -814,7 +814,7 @@ static inline void cancel_power_button_timer(void)
 /*****************************************************************************/
 /* Chipset interface */
 
-void chipset_force_shutdown(enum chipset_shutdown_reason reason)
+test_mockable void chipset_force_shutdown(enum chipset_shutdown_reason reason)
 {
 	CPRINTS("%s(%d)", __func__, reason);
 	report_ap_reset(reason);
@@ -824,7 +824,7 @@ void chipset_force_shutdown(enum chipset_shutdown_reason reason)
 	task_wake(TASK_ID_CHIPSET);
 }
 
-void chipset_power_on(void)
+test_mockable void chipset_power_on(void)
 {
 	if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
 		power_request = POWER_REQ_ON;
@@ -887,7 +887,7 @@ static void check_for_warm_reset_event(void)
 	}
 }
 
-void chipset_reset(enum chipset_shutdown_reason reason)
+test_mockable void chipset_reset(enum chipset_shutdown_reason reason)
 {
 	CPRINTS("%s(%d)", __func__, reason);
 	report_ap_reset(reason);
@@ -904,14 +904,14 @@ void chipset_reset(enum chipset_shutdown_reason reason)
  */
 static int fake_suspend = -1;
 
-static int command_fake_suspend(int argc, char **argv)
+static int command_fake_suspend(int argc, const char **argv)
 {
 	int v;
 
 	if (argc < 2) {
 		ccprintf("fake_suspend: %s\n",
-			 fake_suspend == -1 ? "reset"
-					    : (fake_suspend ? "on" : "off"));
+			 fake_suspend == -1 ? "reset" :
+					      (fake_suspend ? "on" : "off"));
 		return EC_SUCCESS;
 	}
 
@@ -926,8 +926,7 @@ static int command_fake_suspend(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(fakesuspend, command_fake_suspend,
-			"on/off/reset",
+DECLARE_CONSOLE_COMMAND(fakesuspend, command_fake_suspend, "on/off/reset",
 			"Fake the AP_SUSPEND signal");
 
 /* Get system sleep state through GPIOs */
@@ -939,8 +938,7 @@ static inline int chipset_get_sleep_signal(void)
 		return fake_suspend;
 }
 
-__override void power_chipset_handle_sleep_hang(
-		enum sleep_hang_type hang_type)
+__override void power_chipset_handle_sleep_hang(enum sleep_hang_type hang_type)
 {
 	CPRINTS("Warning: Detected sleep hang! Waking host up!");
 	host_set_single_event(EC_HOST_EVENT_HANG_DETECT);
@@ -964,9 +962,9 @@ static void handle_chipset_reset(void)
 }
 DECLARE_HOOK(HOOK_CHIPSET_RESET, handle_chipset_reset, HOOK_PRIO_FIRST);
 
-__override void power_chipset_handle_host_sleep_event(
-		enum host_sleep_event state,
-		struct host_sleep_event_context *ctx)
+__override void
+power_chipset_handle_host_sleep_event(enum host_sleep_event state,
+				      struct host_sleep_event_context *ctx)
 {
 	CPRINTS("Handle sleep: %d", state);
 
@@ -1001,7 +999,7 @@ __override void power_chipset_handle_host_sleep_event(
  * @param state		Current power state
  * @return Updated power state
  */
-enum power_state power_handle_state(enum power_state state)
+test_mockable enum power_state power_handle_state(enum power_state state)
 {
 	static uint8_t boot_from_off, shutdown_from_on;
 
@@ -1110,9 +1108,9 @@ enum power_state power_handle_state(enum power_state state)
 		shutdown_from_on = check_for_power_off_event();
 		if (shutdown_from_on) {
 			return POWER_S0S3;
-		} else if (power_get_host_sleep_state()
-					== HOST_SLEEP_EVENT_S3_SUSPEND &&
-				chipset_get_sleep_signal()) {
+		} else if (power_get_host_sleep_state() ==
+				   HOST_SLEEP_EVENT_S3_SUSPEND &&
+			   chipset_get_sleep_signal()) {
 			return POWER_S0S3;
 		}
 		/* When receive the host event, trigger the RESUME hook. */
@@ -1200,13 +1198,13 @@ enum power_state_t {
 	PSTATE_COUNT,
 };
 
-static const char * const state_name[] = {
+static const char *const state_name[] = {
 	"unknown",
 	"off",
 	"on",
 };
 
-static int command_power(int argc, char **argv)
+test_mockable_static int command_power(int argc, const char **argv)
 {
 	int v;
 
@@ -1232,6 +1230,4 @@ static int command_power(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(power, command_power,
-			"on/off",
-			"Turn AP power on/off");
+DECLARE_CONSOLE_COMMAND(power, command_power, "on/off", "Turn AP power on/off");
diff --git a/power/rk3288.c b/power/rk3288.c
index 851a8b4e9d..e4e4ac9d69 100644
--- a/power/rk3288.c
+++ b/power/rk3288.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,8 +24,9 @@
  */
 
 #include "battery.h"
+#include "builtin/assert.h"
 #include "charge_state.h"
-#include "chipset.h"  /* This module implements chipset functions too */
+#include "chipset.h" /* This module implements chipset functions too */
 #include "clock.h"
 #include "common.h"
 #include "console.h"
@@ -43,14 +44,14 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 /* masks for power signals */
 #define IN_POWER_GOOD POWER_SIGNAL_MASK(RK_POWER_GOOD)
 #define IN_SUSPEND POWER_SIGNAL_MASK(RK_SUSPEND_ASSERTED)
 
 /* Long power key press to force shutdown */
-#define DELAY_FORCE_SHUTDOWN  (8 * SECOND)
+#define DELAY_FORCE_SHUTDOWN (8 * SECOND)
 
 /*
  * If the power key is pressed to turn on, then held for this long, we
@@ -60,7 +61,7 @@
  *    into the inner loop, waiting for next event to occur (power button
  *    press or power good == 0).
  */
-#define DELAY_SHUTDOWN_ON_POWER_HOLD	(8 * SECOND)
+#define DELAY_SHUTDOWN_ON_POWER_HOLD (8 * SECOND)
 
 /*
  * The hold time for pulling down the PMIC_WARM_RESET_L pin so that
@@ -101,11 +102,9 @@ enum power_request_t {
 
 static enum power_request_t power_request;
 
-
 /* Forward declaration */
 static void chipset_turn_off_power_rails(void);
 
-
 /**
  * Set the PMIC WARM RESET signal.
  *
@@ -117,7 +116,6 @@ static void set_pmic_warm_reset(int asserted)
 	gpio_set_level(GPIO_PMIC_WARM_RESET_L, asserted ? 0 : 1);
 }
 
-
 /**
  * Set the PMIC PWRON signal.
  *
@@ -161,7 +159,7 @@ static int check_for_power_off_event(void)
 		pressed = 1;
 	} else if (power_request == POWER_REQ_OFF) {
 		power_request = POWER_REQ_NONE;
-		return 4;  /* return non-zero for shudown down */
+		return 4; /* return non-zero for shudown down */
 	}
 
 	now = get_time();
@@ -294,13 +292,11 @@ static int check_for_power_on_event(void)
 	/* check if system is already ON */
 	if (power_get_signals() & IN_POWER_GOOD) {
 		if (ap_off_flag) {
-			CPRINTS(
-				"system is on, but "
+			CPRINTS("system is on, but "
 				"EC_RESET_FLAG_AP_OFF is on");
 			return 0;
 		} else {
-			CPRINTS(
-				"system is on, thus clear "
+			CPRINTS("system is on, thus clear "
 				"auto_power_on");
 			/* no need to arrange another power on */
 			auto_power_on = 0;
@@ -391,7 +387,7 @@ void chipset_reset(enum chipset_shutdown_reason reason)
 	report_ap_reset(reason);
 
 	CPRINTS("assert GPIO_PMIC_WARM_RESET_L for %d ms",
-			PMIC_WARM_RESET_L_HOLD_TIME / MSEC);
+		PMIC_WARM_RESET_L_HOLD_TIME / MSEC);
 	set_pmic_warm_reset(1);
 	usleep(PMIC_WARM_RESET_L_HOLD_TIME);
 	set_pmic_warm_reset(0);
@@ -437,16 +433,17 @@ enum power_state power_handle_state(enum power_state state)
 		if (power_wait_signals(IN_POWER_GOOD) == EC_SUCCESS) {
 			CPRINTS("POWER_GOOD seen");
 			if (power_button_wait_for_release(
-					DELAY_SHUTDOWN_ON_POWER_HOLD) ==
-					EC_SUCCESS) {
+				    DELAY_SHUTDOWN_ON_POWER_HOLD) ==
+			    EC_SUCCESS) {
 				power_button_was_pressed = 0;
 				set_pmic_pwron(0);
 
 				/* setup misc gpio for S3/S0 functionality */
-				gpio_set_flags(GPIO_SUSPEND_L, GPIO_INPUT
-					| GPIO_INT_BOTH | GPIO_PULL_DOWN);
-				gpio_set_flags(GPIO_EC_INT_L, GPIO_OUTPUT
-						| GPIO_OUT_HIGH);
+				gpio_set_flags(GPIO_SUSPEND_L,
+					       GPIO_INPUT | GPIO_INT_BOTH |
+						       GPIO_PULL_DOWN);
+				gpio_set_flags(GPIO_EC_INT_L,
+					       GPIO_OUTPUT | GPIO_OUT_HIGH);
 
 				/* Call hooks now that AP is running */
 				hook_notify(HOOK_CHIPSET_STARTUP);
@@ -521,7 +518,7 @@ static void powerbtn_rockchip_changed(void)
 	task_wake(TASK_ID_CHIPSET);
 }
 DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, powerbtn_rockchip_changed,
-		HOOK_PRIO_DEFAULT);
+	     HOOK_PRIO_DEFAULT);
 
 /*****************************************************************************/
 /* Console debug command */
@@ -542,14 +539,14 @@ enum power_state_t {
 	PSTATE_COUNT,
 };
 
-static const char * const state_name[] = {
+static const char *const state_name[] = {
 	"unknown",
 	"off",
 	"suspend",
 	"on",
 };
 
-static int command_power(int argc, char **argv)
+static int command_power(int argc, const char **argv)
 {
 	int v;
 
@@ -577,6 +574,4 @@ static int command_power(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(power, command_power,
-			"on/off",
-			"Turn AP power on/off");
+DECLARE_CONSOLE_COMMAND(power, command_power, "on/off", "Turn AP power on/off");
diff --git a/power/rk3399.c b/power/rk3399.c
index e0ea7ee483..ef4c0407b8 100644
--- a/power/rk3399.c
+++ b/power/rk3399.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,6 +12,7 @@
  * Version 1: Simplified power tree for tablet / detachable.
  */
 
+#include "builtin/assert.h"
 #include "charge_state.h"
 #include "chipset.h"
 #include "common.h"
@@ -30,46 +31,46 @@
 
 /* Console output macros */
 #define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 /* Input state flags */
 #if CONFIG_CHIPSET_POWER_SEQ_VERSION == 1
-	#define IN_PGOOD_PP1250_S3   POWER_SIGNAL_MASK(PP1250_S3_PWR_GOOD)
-	#define IN_PGOOD_PP900_S0    POWER_SIGNAL_MASK(PP900_S0_PWR_GOOD)
+#define IN_PGOOD_PP1250_S3 POWER_SIGNAL_MASK(PP1250_S3_PWR_GOOD)
+#define IN_PGOOD_PP900_S0 POWER_SIGNAL_MASK(PP900_S0_PWR_GOOD)
 #else
-	#define IN_PGOOD_PP5000      POWER_SIGNAL_MASK(PP5000_PWR_GOOD)
-	#define IN_PGOOD_SYS         POWER_SIGNAL_MASK(SYS_PWR_GOOD)
+#define IN_PGOOD_PP5000 POWER_SIGNAL_MASK(PP5000_PWR_GOOD)
+#define IN_PGOOD_SYS POWER_SIGNAL_MASK(SYS_PWR_GOOD)
 #endif
 
-#define IN_PGOOD_AP            POWER_SIGNAL_MASK(AP_PWR_GOOD)
-#define IN_SUSPEND_DEASSERTED  POWER_SIGNAL_MASK(SUSPEND_DEASSERTED)
+#define IN_PGOOD_AP POWER_SIGNAL_MASK(AP_PWR_GOOD)
+#define IN_SUSPEND_DEASSERTED POWER_SIGNAL_MASK(SUSPEND_DEASSERTED)
 
 /* Rails requires for S3 and S0 */
 #if CONFIG_CHIPSET_POWER_SEQ_VERSION == 1
-	#define IN_PGOOD_S3    (IN_PGOOD_PP1250_S3)
-	#define IN_PGOOD_S0    (IN_PGOOD_S3 | IN_PGOOD_PP900_S0 | IN_PGOOD_AP)
-	/* This board can optionally wake-on-USB in S3 */
-	#define S3_USB_WAKE
-	/* This board has non-INT power signal pins */
-	#define POWER_SIGNAL_POLLING
-	/* This board supports CR50 deep sleep mode */
-	#define CR50_DEEP_SLEEP
-	/*
-	 * If AP_PWR_GOOD assertion does not trigger an interrupt, poll the
-	 * signal every 5ms, up to 200 times (~ 1 second timeout).
-	 */
-	#define PGOOD_S0_POLL_TIMEOUT  (5 * MSEC)
-	#define PGOOD_S0_POLL_TRIES    200
+#define IN_PGOOD_S3 (IN_PGOOD_PP1250_S3)
+#define IN_PGOOD_S0 (IN_PGOOD_S3 | IN_PGOOD_PP900_S0 | IN_PGOOD_AP)
+/* This board can optionally wake-on-USB in S3 */
+#define S3_USB_WAKE
+/* This board has non-INT power signal pins */
+#define POWER_SIGNAL_POLLING
+/* This board supports CR50 deep sleep mode */
+#define CR50_DEEP_SLEEP
+/*
+ * If AP_PWR_GOOD assertion does not trigger an interrupt, poll the
+ * signal every 5ms, up to 200 times (~ 1 second timeout).
+ */
+#define PGOOD_S0_POLL_TIMEOUT (5 * MSEC)
+#define PGOOD_S0_POLL_TRIES 200
 #else
-	#define IN_PGOOD_S3    (IN_PGOOD_PP5000)
-	#define IN_PGOOD_S0    (IN_PGOOD_S3 | IN_PGOOD_AP | IN_PGOOD_SYS)
+#define IN_PGOOD_S3 (IN_PGOOD_PP5000)
+#define IN_PGOOD_S0 (IN_PGOOD_S3 | IN_PGOOD_AP | IN_PGOOD_SYS)
 #endif
 
 /* All inputs in the right state for S0 */
-#define IN_ALL_S0              (IN_PGOOD_S0 | IN_SUSPEND_DEASSERTED)
+#define IN_ALL_S0 (IN_PGOOD_S0 | IN_SUSPEND_DEASSERTED)
 
 /* Long power key press to force shutdown in S0 */
-#define FORCED_SHUTDOWN_DELAY  (8 * SECOND)
+#define FORCED_SHUTDOWN_DELAY (8 * SECOND)
 
 #define CHARGER_INITIALIZED_DELAY_MS 100
 #define CHARGER_INITIALIZED_TRIES 40
@@ -126,12 +127,9 @@ static const struct power_seq_op s3s0_power_seq[] = {
 };
 #else
 static const struct power_seq_op s3s0_power_seq[] = {
-	{ GPIO_PPVAR_CLOGIC_EN, 1, 2 },
-	{ GPIO_PP900_DDRPLL_EN, 1, 2 },
-	{ GPIO_PP1800_AP_AVDD_EN_L, 0, 2 },
-	{ GPIO_AP_CORE_EN, 1, 2 },
-	{ GPIO_PP1800_S0_EN_L, 0, 2 },
-	{ GPIO_PP3300_S0_EN_L, 0, 0 },
+	{ GPIO_PPVAR_CLOGIC_EN, 1, 2 },	    { GPIO_PP900_DDRPLL_EN, 1, 2 },
+	{ GPIO_PP1800_AP_AVDD_EN_L, 0, 2 }, { GPIO_AP_CORE_EN, 1, 2 },
+	{ GPIO_PP1800_S0_EN_L, 0, 2 },	    { GPIO_PP3300_S0_EN_L, 0, 0 },
 };
 #endif
 
@@ -151,12 +149,9 @@ static const struct power_seq_op s0s3_power_seq[] = {
 };
 #else
 static const struct power_seq_op s0s3_power_seq[] = {
-	{ GPIO_PP3300_S0_EN_L, 1, 20 },
-	{ GPIO_PP1800_S0_EN_L, 1, 1 },
-	{ GPIO_AP_CORE_EN, 0, 20 },
-	{ GPIO_PP1800_AP_AVDD_EN_L, 1, 1 },
-	{ GPIO_PP900_DDRPLL_EN, 0, 1 },
-	{ GPIO_PPVAR_CLOGIC_EN, 0, 0 },
+	{ GPIO_PP3300_S0_EN_L, 1, 20 }, { GPIO_PP1800_S0_EN_L, 1, 1 },
+	{ GPIO_AP_CORE_EN, 0, 20 },	{ GPIO_PP1800_AP_AVDD_EN_L, 1, 1 },
+	{ GPIO_PP900_DDRPLL_EN, 0, 1 }, { GPIO_PPVAR_CLOGIC_EN, 0, 0 },
 };
 #endif
 
@@ -173,28 +168,19 @@ static const struct power_seq_op s0s3_usb_wake_power_seq[] = {
 /* The power sequence for POWER_S3S5 */
 #if CONFIG_CHIPSET_POWER_SEQ_VERSION == 1
 static const struct power_seq_op s3s5_power_seq[] = {
-	{ GPIO_SYS_RST_L, 0, 0 },
-	{ GPIO_PP1250_S3_EN, 0, 2 },
-	{ GPIO_PP1800_S3_EN, 0, 2 },
-	{ GPIO_PP3300_S3_EN, 0, 2 },
+	{ GPIO_SYS_RST_L, 0, 0 },    { GPIO_PP1250_S3_EN, 0, 2 },
+	{ GPIO_PP1800_S3_EN, 0, 2 }, { GPIO_PP3300_S3_EN, 0, 2 },
 	{ GPIO_PP900_S3_EN, 0, 0 },
 };
 #else
 static const struct power_seq_op s3s5_power_seq[] = {
-	{ GPIO_PP1800_SENSOR_EN_L, 1, 0},
-	{ GPIO_PP1800_SIXAXIS_EN_L, 1, 0},
-	{ GPIO_PP1800_LID_EN_L, 1, 0 },
-	{ GPIO_PP3300_TRACKPAD_EN_L, 1, 0 },
-	{ GPIO_PP5000_EN, 0, 0 },
-	{ GPIO_PP3300_USB_EN_L, 1, 20 },
-	{ GPIO_PP1800_USB_EN_L, 1, 10 },
-	{ GPIO_LPDDR_PWR_EN, 0, 20 },
-	{ GPIO_PP1800_PMU_EN_L, 1, 2 },
-	{ GPIO_PP900_PLL_EN, 0, 0 },
-	{ GPIO_PP900_PMU_EN, 0, 0 },
-	{ GPIO_PP900_USB_EN, 0, 6 },
-	{ GPIO_PP900_PCIE_EN, 0, 0 },
-	{ GPIO_PP900_AP_EN, 0, 0 },
+	{ GPIO_PP1800_SENSOR_EN_L, 1, 0 }, { GPIO_PP1800_SIXAXIS_EN_L, 1, 0 },
+	{ GPIO_PP1800_LID_EN_L, 1, 0 },	   { GPIO_PP3300_TRACKPAD_EN_L, 1, 0 },
+	{ GPIO_PP5000_EN, 0, 0 },	   { GPIO_PP3300_USB_EN_L, 1, 20 },
+	{ GPIO_PP1800_USB_EN_L, 1, 10 },   { GPIO_LPDDR_PWR_EN, 0, 20 },
+	{ GPIO_PP1800_PMU_EN_L, 1, 2 },	   { GPIO_PP900_PLL_EN, 0, 0 },
+	{ GPIO_PP900_PMU_EN, 0, 0 },	   { GPIO_PP900_USB_EN, 0, 6 },
+	{ GPIO_PP900_PCIE_EN, 0, 0 },	   { GPIO_PP900_AP_EN, 0, 0 },
 	{ GPIO_PPVAR_LOGIC_EN, 0, 0 },
 };
 #endif
@@ -268,18 +254,18 @@ DECLARE_DEFERRED(force_shutdown);
  * power sequencing, and immediately transition out of suspend if necessary.
  */
 #define SLEEP_INTERVAL_MS 5
-#define MSLEEP_CHECK_ABORTED_SUSPEND(msec) \
-	do { \
-		int sleep_remain = msec; \
-		do { \
-			msleep(MIN(sleep_remain, SLEEP_INTERVAL_MS)); \
-			sleep_remain -= SLEEP_INTERVAL_MS; \
-			if (!forcing_shutdown && \
-			    power_get_signals() & IN_SUSPEND_DEASSERTED)  { \
-				CPRINTS("suspend aborted"); \
-				return POWER_S3S0; \
-			} \
-		} while (sleep_remain > 0); \
+#define MSLEEP_CHECK_ABORTED_SUSPEND(msec)                                 \
+	do {                                                               \
+		int sleep_remain = msec;                                   \
+		do {                                                       \
+			msleep(MIN(sleep_remain, SLEEP_INTERVAL_MS));      \
+			sleep_remain -= SLEEP_INTERVAL_MS;                 \
+			if (!forcing_shutdown &&                           \
+			    power_get_signals() & IN_SUSPEND_DEASSERTED) { \
+				CPRINTS("suspend aborted");                \
+				return POWER_S3S0;                         \
+			}                                                  \
+		} while (sleep_remain > 0);                                \
 	} while (0)
 BUILD_ASSERT(POWER_S3S0 != 0);
 
@@ -295,15 +281,14 @@ static int power_seq_run(const struct power_seq_op *power_seq_ops, int op_count)
 	int i;
 
 	for (i = 0; i < op_count; i++) {
-		gpio_set_level(power_seq_ops[i].signal,
-			       power_seq_ops[i].level);
+		gpio_set_level(power_seq_ops[i].signal, power_seq_ops[i].level);
 		if (!power_seq_ops[i].delay)
 			continue;
 		if ((power_seq_ops == s0s3_power_seq)
 #ifdef S3_USB_WAKE
 		    || (power_seq_ops == s0s3_usb_wake_power_seq)
 #endif
-		   )
+		)
 			MSLEEP_CHECK_ABORTED_SUSPEND(power_seq_ops[i].delay);
 		else
 			msleep(power_seq_ops[i].delay);
@@ -340,8 +325,7 @@ enum power_state power_handle_state(enum power_state state)
 		break;
 
 	case POWER_S0:
-		if (!power_has_signals(IN_PGOOD_S3) ||
-		    forcing_shutdown ||
+		if (!power_has_signals(IN_PGOOD_S3) || forcing_shutdown ||
 		    !(power_get_signals() & IN_SUSPEND_DEASSERTED))
 			return POWER_S0S3;
 
@@ -353,16 +337,15 @@ enum power_state power_handle_state(enum power_state state)
 		 * it here as well.
 		 */
 		if (power_wait_signals_timeout(IN_PGOOD_AP | IN_PGOOD_SYS,
-					       PGOOD_AP_DEBOUNCE_TIMEOUT)
-					       == EC_ERROR_TIMEOUT)
+					       PGOOD_AP_DEBOUNCE_TIMEOUT) ==
+		    EC_ERROR_TIMEOUT)
 			return POWER_S0S3;
 
 		/*
 		 * power_wait_signals_timeout() can block and consume task
 		 * wake events, so re-verify the state of the world.
 		 */
-		if (!power_has_signals(IN_PGOOD_S3) ||
-		    forcing_shutdown ||
+		if (!power_has_signals(IN_PGOOD_S3) || forcing_shutdown ||
 		    !(power_get_signals() & IN_SUSPEND_DEASSERTED))
 			return POWER_S0S3;
 #endif
@@ -444,7 +427,8 @@ enum power_state power_handle_state(enum power_state state)
 		 * interrupt.
 		 */
 		while (power_wait_signals_timeout(IN_PGOOD_S0,
-		       PGOOD_S0_POLL_TIMEOUT) == EC_ERROR_TIMEOUT &&
+						  PGOOD_S0_POLL_TIMEOUT) ==
+			       EC_ERROR_TIMEOUT &&
 		       ++tries < PGOOD_S0_POLL_TRIES)
 			;
 
@@ -553,8 +537,7 @@ static void power_button_changed(void)
 #endif
 		}
 		/* Delayed power down from S0/S3, cancel on PB release */
-		hook_call_deferred(&force_shutdown_data,
-				   FORCED_SHUTDOWN_DELAY);
+		hook_call_deferred(&force_shutdown_data, FORCED_SHUTDOWN_DELAY);
 	} else {
 #if CONFIG_CHIPSET_POWER_SEQ_VERSION == 1
 		if (tablet_boot_on_button_release) {
diff --git a/power/sdm845.c b/power/sdm845.c
index 7463e00069..aeed0d13d2 100644
--- a/power/sdm845.c
+++ b/power/sdm845.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,6 +22,7 @@
  *  - If POWER_GOOD is dropped by the AP, then we power the AP off
  */
 
+#include "builtin/assert.h"
 #include "charge_state.h"
 #include "chipset.h"
 #include "common.h"
@@ -34,15 +35,14 @@
 #include "task.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
 /* Masks for power signals */
-#define IN_POWER_GOOD		POWER_SIGNAL_MASK(SDM845_POWER_GOOD)
-#define IN_AP_RST_ASSERTED	POWER_SIGNAL_MASK(SDM845_AP_RST_ASSERTED)
-
+#define IN_POWER_GOOD POWER_SIGNAL_MASK(SDM845_POWER_GOOD)
+#define IN_AP_RST_ASSERTED POWER_SIGNAL_MASK(SDM845_AP_RST_ASSERTED)
 
 /* Long power key press to force shutdown */
-#define DELAY_FORCE_SHUTDOWN		(8 * SECOND)
+#define DELAY_FORCE_SHUTDOWN (8 * SECOND)
 
 /*
  * If the power button is pressed to turn on, then held for this long, we
@@ -52,40 +52,40 @@
  *    into the inner loop, waiting for next event to occur (power button
  *    press or POWER_GOOD == 0).
  */
-#define DELAY_SHUTDOWN_ON_POWER_HOLD	(8 * SECOND)
+#define DELAY_SHUTDOWN_ON_POWER_HOLD (8 * SECOND)
 
 /*
  * After trigger PMIC power sequence, how long it triggers AP to turn on
  * or off. Observed that the worst case is ~150ms. Pick a safe vale.
  */
-#define PMIC_POWER_AP_RESPONSE_TIMEOUT	(350 * MSEC)
+#define PMIC_POWER_AP_RESPONSE_TIMEOUT (350 * MSEC)
 
 /*
  * After force off the switch cap, how long the PMIC/AP totally off.
  * Observed that the worst case is 2s. Pick a safe vale.
  */
-#define FORCE_OFF_RESPONSE_TIMEOUT	(4 * SECOND)
+#define FORCE_OFF_RESPONSE_TIMEOUT (4 * SECOND)
 
 /* Wait for polling the AP on signal */
-#define PMIC_POWER_AP_WAIT		(1 * MSEC)
+#define PMIC_POWER_AP_WAIT (1 * MSEC)
 
 /* The length of an issued low pulse to the PMIC_RESIN_L signal */
-#define PMIC_RESIN_PULSE_LENGTH		(20 * MSEC)
+#define PMIC_RESIN_PULSE_LENGTH (20 * MSEC)
 
 /* The timeout of the check if the system can boot AP */
-#define CAN_BOOT_AP_CHECK_TIMEOUT	(500 * MSEC)
+#define CAN_BOOT_AP_CHECK_TIMEOUT (500 * MSEC)
 
 /* Wait for polling if the system can boot AP */
-#define CAN_BOOT_AP_CHECK_WAIT		(100 * MSEC)
+#define CAN_BOOT_AP_CHECK_WAIT (100 * MSEC)
 
 /* The timeout of the check if the switchcap outputs good voltage */
-#define SWITCHCAP_PG_CHECK_TIMEOUT	(50 * MSEC)
+#define SWITCHCAP_PG_CHECK_TIMEOUT (50 * MSEC)
 
 /* Wait for polling if the switchcap outputs good voltage */
-#define SWITCHCAP_PG_CHECK_WAIT		(5 * MSEC)
+#define SWITCHCAP_PG_CHECK_WAIT (5 * MSEC)
 
 /* Delay between power-on the system and power-on the PMIC */
-#define SYSTEM_POWER_ON_DELAY		(10 * MSEC)
+#define SYSTEM_POWER_ON_DELAY (10 * MSEC)
 
 /* TODO(crosbug.com/p/25047): move to HOOK_POWER_BUTTON_CHANGE */
 /* 1 if the power button was pressed last time we checked */
@@ -182,9 +182,11 @@ void chipset_warm_reset_interrupt(enum gpio_signal signal)
 			 */
 			ap_rst_overdriven = 1;
 			gpio_set_flags(GPIO_PS_HOLD, GPIO_INT_BOTH |
-				       GPIO_SEL_1P8V | GPIO_OUT_HIGH);
+							     GPIO_SEL_1P8V |
+							     GPIO_OUT_HIGH);
 			gpio_set_flags(GPIO_AP_RST_L, GPIO_INT_BOTH |
-				       GPIO_SEL_1P8V | GPIO_OUT_LOW);
+							      GPIO_SEL_1P8V |
+							      GPIO_OUT_LOW);
 		} else {
 			/*
 			 * The pull-up rail POWER_GOOD drops.
@@ -192,10 +194,10 @@ void chipset_warm_reset_interrupt(enum gpio_signal signal)
 			 * High-Z both AP_RST_L and PS_HOLD to restore their
 			 * states.
 			 */
-			gpio_set_flags(GPIO_AP_RST_L, GPIO_INT_BOTH |
-				       GPIO_SEL_1P8V);
-			gpio_set_flags(GPIO_PS_HOLD, GPIO_INT_BOTH |
-				       GPIO_SEL_1P8V);
+			gpio_set_flags(GPIO_AP_RST_L,
+				       GPIO_INT_BOTH | GPIO_SEL_1P8V);
+			gpio_set_flags(GPIO_PS_HOLD,
+				       GPIO_INT_BOTH | GPIO_SEL_1P8V);
 			ap_rst_overdriven = 0;
 		}
 	} else {
@@ -268,7 +270,6 @@ static void wait_switchcap_power_good(int enable)
 		else
 			CPRINTS("SWITCHCAP STILL POWER GOOD!");
 	}
-
 }
 
 /**
@@ -500,7 +501,7 @@ static int power_is_enough(void)
 	 * waste the time and exit the loop.
 	 */
 	while (!system_can_boot_ap() && !charge_want_shutdown() &&
-		get_time().val < poll_deadline.val) {
+	       get_time().val < poll_deadline.val) {
 		usleep(CAN_BOOT_AP_CHECK_WAIT);
 	}
 
@@ -850,13 +851,13 @@ enum power_state_t {
 	PSTATE_COUNT,
 };
 
-static const char * const state_name[] = {
+static const char *const state_name[] = {
 	"unknown",
 	"off",
 	"on",
 };
 
-static int command_power(int argc, char **argv)
+static int command_power(int argc, const char **argv)
 {
 	int v;
 
@@ -882,6 +883,4 @@ static int command_power(int argc, char **argv)
 
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(power, command_power,
-			"on/off",
-			"Turn AP power on/off");
+DECLARE_CONSOLE_COMMAND(power, command_power, "on/off", "Turn AP power on/off");
diff --git a/power/skylake.c b/power/skylake.c
index 511ab8c32f..24adb56f86 100644
--- a/power/skylake.c
+++ b/power/skylake.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,9 +17,9 @@
 #include "timer.h"
 
 /* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args)
 
-static int forcing_shutdown;  /* Forced shutdown in progress? */
+static int forcing_shutdown; /* Forced shutdown in progress? */
 
 /* Power signals list. Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
@@ -58,7 +58,6 @@ const struct power_signal_info power_signal_list[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
-
 void chipset_force_shutdown(enum chipset_shutdown_reason reason)
 {
 	CPRINTS("%s()", __func__);
@@ -110,7 +109,7 @@ void chipset_handle_espi_reset_assert(void)
 	 * power button. If yes, release power button.
 	 */
 	if ((power_get_signals() & IN_PCH_SLP_SUS_DEASSERTED) &&
-		forcing_shutdown) {
+	    forcing_shutdown) {
 		power_button_pch_release();
 		forcing_shutdown = 0;
 	}
@@ -157,9 +156,8 @@ void chipset_handle_reboot(void)
 	 * Do not make PMIC re-sequence the power rails if the following reset
 	 * conditions are not met.
 	 */
-	if (!(flags &
-		(EC_RESET_FLAG_WATCHDOG | EC_RESET_FLAG_SOFT |
-		 EC_RESET_FLAG_HARD)))
+	if (!(flags & (EC_RESET_FLAG_WATCHDOG | EC_RESET_FLAG_SOFT |
+		       EC_RESET_FLAG_HARD)))
 		return;
 
 	/* Preserve AP off request. */
diff --git a/pylintrc b/pylintrc
index 9ec7f3c61a..43a8deb58b 100644
--- a/pylintrc
+++ b/pylintrc
@@ -1,358 +1,21 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
-#
-# This file is copied Chromium OS platform2, as seen in the following link:
-# https://chromium.googlesource.com/chromiumos/platform2/+/HEAD/pylintrc
-# Please keep in sync.
-
-# NB: This is a fork of chromite/pylintrc with indent set to 4.
-# Everything else is kept the same.
-
-[MASTER]
-
-# Add files or directories matching the regex patterns to the ignore list.
-# The regex matches against base names, not paths.
-ignore-patterns=
-    .*_pb2\.py$,
-    .*third_party\/.*.py$
-
-
-# List of plugins (as comma separated values of python modules names) to load,
-# usually to register additional checkers.
-load-plugins=
-    chromite.cli.cros.lint,
-    pylint.extensions.bad_builtin,
-    pylint.extensions.docstyle,
-    pylint.extensions.redefined_variable_type,
-    pylint.extensions.overlapping_exceptions,
-
-# Configure quote preferences.
-string-quote = single-avoid-escape
-triple-quote = double
-docstring-quote = double
 
+# Changes to make pylint and black agree on the formatting.
 
 [MESSAGES CONTROL]
 
-# Enable the message, report, category or checker with the given id(s). You can
-# either give multiple identifier separated by comma (,) or put this option
-# multiple times.
-# eq-without-hash: We omit this as we don't require all objects be hashable.
-#   We'll wait for unittest coverage to detect missing __hash__ on objects.
-# no-absolute-import: We don't seem to rely on this behavior, so don't enforce
-#   using this future import everywhere.
-# round-builtin: We omit this as all our usage of round() is OK with either
-#   Python 2 or 3 behavior (and probably leans towards 3 anyways).
-enable=
-    apply-builtin,
-    backtick,
-    bad-python3-import,
-    basestring-builtin,
-    buffer-builtin,
-    cmp-builtin,
-    cmp-method,
-    coerce-builtin,
-    coerce-method,
-    delslice-method,
-    deprecated-itertools-function,
-    deprecated-str-translate-call,
-    deprecated-string-function,
-    deprecated-types-field,
-    dict-items-not-iterating,
-    dict-iter-method,
-    dict-keys-not-iterating,
-    dict-values-not-iterating,
-    dict-view-method,
-    div-method,
-    exception-message-attribute,
-    execfile-builtin,
-    file-builtin,
-    filter-builtin-not-iterating,
-    getslice-method,
-    hex-method,
-    idiv-method,
-    import-star-module-level,
-    indexing-exception,
-    intern-builtin,
-    invalid-str-codec,
-    long-builtin,
-    long-suffix,
-    map-builtin-not-iterating,
-    metaclass-assignment,
-    next-method-called,
-    next-method-defined,
-    nonzero-method,
-    oct-method,
-    old-ne-operator,
-    old-octal-literal,
-    old-raise-syntax,
-    parameter-unpacking,
-    print-statement,
-    raising-string,
-    range-builtin-not-iterating,
-    raw_input-builtin,
-    rdiv-method,
-    reduce-builtin,
-    reload-builtin,
-    setslice-method,
-    standarderror-builtin,
-    sys-max-int,
-    unichr-builtin,
-    unicode-builtin,
-    unpacking-in-except,
-    using-cmp-argument,
-    xrange-builtin,
-    zip-builtin-not-iterating,
-
-
-# Disable the message, report, category or checker with the given id(s). You
-# can either give multiple identifiers separated by comma (,) or put this
-# option multiple times (only on the command line, not in the configuration
-# file where it should appear only once). You can also use "--disable=all" to
-# disable everything first and then reenable specific checks. For example, if
-# you want to run only the similarities checker, you can use "--disable=all
-# --enable=similarities". If you want to run only the classes checker, but have
-# no Warning level messages displayed, use "--disable=all --enable=classes
-# --disable=W".
-# We leave many of the style warnings to judgement/peer review.
-# TODO: We need to re-enable broad-except, but requires cleaning up our code.
-# TODO: Re-enable redefined-variable-type.
-# TODO: Re-enable inconsistent-return-statements.
-# TODO: Re-enable keyword-arg-before-vararg once we're on Python 3-only.
-# TODO: Re-enable useless-object-inheritance once we're on Python 3-only and
-#       we update the style guide.
-# TODO: Re-enable import-outside-toplevel.
-# TODO: Re-enable unnecessary-comprehension.
-# TODO: Re-enable consider-using-dict-comprehension.
-# TODO: Re-enable consider-using-set-comprehension.
-# TODO: Re-enable consider-using-in.
-# TODO: Re-enable try-except-raise.
-# TODO: Re-enable chained-comparison.
 disable=
-    broad-except,
-    chained-comparison,
-    consider-iterating-dictionary,
-    consider-using-dict-comprehension,
-    consider-using-in,
-    consider-using-set-comprehension,
+    bad-continuation,
+    bad-whitespace,
+    # These have nothing to do with black, they are just annoying
     fixme,
-    file-ignored,
-    keyword-arg-before-vararg,
-    import-outside-toplevel,
-    inconsistent-return-statements,
-    invalid-name,
-    locally-disabled,
-    locally-enabled,
-    missing-docstring,
-    no-member,
-    no-else-break,
-    no-else-continue,
-    no-else-raise,
-    no-else-return,
-    no-self-use,
-    raise-missing-from,
-    redefined-variable-type,
-    relative-import,
-    super-with-arguments,
-    too-few-public-methods,
     too-many-arguments,
-    too-many-boolean-expressions,
-    too-many-branches,
-    too-many-instance-attributes,
-    too-many-lines,
-    too-many-locals,
-    too-many-nested-blocks,
-    too-many-public-methods,
-    too-many-return-statements,
     too-many-statements,
-    try-except-raise,
-    unnecessary-comprehension,
-    useless-object-inheritance,
-
-
-[REPORTS]
-
-# Tells whether to display a full report or only the messages
-# CHANGE: No report.
-reports=no
-
-# Activate the evaluation score.
-score=no
-
-
-[FORMAT]
-
-# Maximum number of characters on a single line.
-max-line-length=80
-
-# Disable line length enforcement for import statements or comment lines
-# containing URLs.
-ignore-long-lines=(^(import|from))|(^\s*(# )?<?https?://\S+>?$)
-
-# Maximum number of lines in a module
-#max-module-lines=1000
-
-# String used as indentation unit. This is usually " " (4 spaces) or "\t" (1
-# tab).
-indent-string='    '
-
-
-[TYPECHECK]
-
-# List of classes names for which member attributes should not be checked
-# (useful for classes with attributes dynamically set).
-ignored-classes=hashlib,numpy
-
-# List of members which are set dynamically and missed by pylint inference
-# system, and so shouldn't trigger E0201 when accessed.
-# CHANGE: Added tempdir for @osutils.TempDirDecorator.
-generated-members=REQUEST,acl_users,aq_parent,tempdir
-
-# List of modules for which member attributes should not be checked.
-# Modules listed here will not trigger import errors even if the linter can't
-# import them.
-#
-# pytest: Made available by our testing virtualenv and can be assumed exists.
-ignored-modules=pytest
-
-[BASIC]
-
-# List of builtins function names that should not be used, separated by a comma.
-# exit & quit are for the interactive interpreter shell only.
-# https://docs.python.org/3/library/constants.html#constants-added-by-the-site-module
-bad-functions=
-    apply,
-    exit,
-    filter,
-    map,
-    quit,
-    reduce,
-
-# Regular expression which should only match correct function names
-#
-# CHANGE: The ChromiumOS standard is different than PEP-8, so we need to
-# redefine this.
-#
-# Common exceptions to ChromiumOS standard:
-# - main: Standard for main function
-function-rgx=([A-Z_][a-zA-Z0-9]{2,30}|main)$
-
-# Regular expression which should only match correct method names
-#
-# CHANGE: The ChromiumOS standard is different than PEP-8, so we need to
-# redefine this. Here's what we allow:
-# - CamelCaps, starting with a capital letter.  No underscores in function
-#   names.  Can also have a "_" prefix (private method) or a "test" prefix
-#   (unit test).
-# - Methods that look like __xyz__, which are used to do things like
-#   __init__, __del__, etc.
-# - setUp, tearDown: For unit tests.
-method-rgx=((_|test)?[A-Z][a-zA-Z0-9]{2,30}|__[a-z]+__|setUp|tearDown)$
-
-
-[SIMILARITIES]
-
-# Minimum lines number of a similarity.
-min-similarity-lines=20
-
-
-[VARIABLES]
-
-# A regular expression matching the beginning of the name of dummy variables
-# (i.e. not used).
-dummy-variables-rgx=_|unused_
-
-
-[DESIGN]
-
-# Maximum number of parents for a class (see R0901).
-max-parents=10
-
-
-[IMPORTS]
-
-# Deprecated modules which should not be used, separated by a comma.
-# __builtin__: Use the 'six.moves.builtins' module instead
-#   (or 'builtins' in Python 3).
-# apiclient: Use the 'googleapiclient' module instead.
-# Bastion: Dropped in Python 3.
-# ConfigParser: Use the 'six.moves.configparser' module instead
-#   (or 'configparser' in Python 3).
-# cookielib: Use the 'six.moves.http_cookiejar' module instead
-#   (or 'http.cookiejar' in Python 3).
-# cPickle: Use the 'pickle' module instead.
-# cStringIO: Use 'io.StringIO' or 'io.BytesIO' instead.
-# exceptions: Dropped in Python 3.
-# HTMLParser: Use the 'six.moves.html_parser' module instead
-#   (or 'html.parser' in Python 3).
-# httplib: Use the 'six.moves.http_client' module instead
-#   (or 'http.client' in Python 3).
-# md5: Use the 'hashlib' module instead.
-# mox: Use the 'mock' module instead.
-# optparse: Use the 'argparse' module instead.
-# Queue: Use the 'six.moves.queue' module instead (or 'queue' in Python 3).
-# regsub: Use the 're' module instead.
-# rexec: Dropped in Python 3.
-# StringIO: Use 'io.StringIO' or 'io.BytesIO' instead.
-# TERMIOS: Use the 'termios' module instead.
-# urllib2: Use the 'six.moves.urllib' module instead
-#   (or 'urllib.request' in Python 3).
-# urlparse: Use the 'six.moves.urllib' module instead
-#   (or 'urllib.parse' in Python 3).
-deprecated-modules=
-    __builtin__,
-    apiclient,
-    Bastion,
-    ConfigParser,
-    cookielib,
-    cPickle,
-    cStringIO,
-    exceptions,
-    HTMLParser,
-    httplib,
-    md5,
-    mock,
-    mox,
-    optparse,
-    Queue,
-    regsub,
-    rexec,
-    StringIO,
-    TERMIOS,
-    urllib2,
-    urlparse,
-
-# Force import order to recognize a module as part of the standard
-# compatibility libraries.
-known-standard-library=
-
-# Force import order to recognize a module as part of a third party library.
-known-third-party=
-    _emerge,
-    apiclient,
-    elftools,
-    gcloud,
-    google,
-    googleapiclient,
-    httplib2,
-    jinja2,
-    jsonschema,
-    lddtree,
-    magic,
-    mock,
-    oauth2client,
-    portage,
-    pylint,
-    pytest,
-    requests,
-    six,
-    sqlalchemy,
-    yaml,
-
+    too-many-branches,
+    too-many-locals
 
-[LOGGING]
+[format]
 
-# Apply logging string format checks to calls on these modules.
-logging-modules=
-    logging,
+string-quote=double
diff --git a/pyproject.toml b/pyproject.toml
new file mode 100644
index 0000000000..83c116eb5f
--- /dev/null
+++ b/pyproject.toml
@@ -0,0 +1,2 @@
+[tool.black]
+line-length = 80
diff --git a/setup.py b/setup.py
index fc6c5d396b..51ab1cff64 100644
--- a/setup.py
+++ b/setup.py
@@ -1,4 +1,4 @@
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -10,7 +10,7 @@ setup(
     author="Aseda Aboagye",
     author_email="aaboagye@chromium.org",
     url="https://www.chromium.org/chromium-os/ec-development",
-    package_dir={"" : "util"},
+    package_dir={"": "util"},
     packages=["ec3po"],
     py_modules=["ec3po.console", "ec3po.interpreter"],
     description="EC console interpreter.",
@@ -22,7 +22,7 @@ setup(
     author="Nick Sanders",
     author_email="nsanders@chromium.org",
     url="https://www.chromium.org/chromium-os/ec-development",
-    package_dir={"" : "extra/tigertool"},
+    package_dir={"": "extra/tigertool"},
     packages=["ecusb"],
     description="Tiny implementation of servod.",
 )
@@ -33,17 +33,23 @@ setup(
     author="Nick Sanders",
     author_email="nsanders@chromium.org",
     url="https://www.chromium.org/chromium-os/ec-development",
-    package_dir={"" : "extra/usb_updater"},
+    package_dir={"": "extra/usb_updater"},
     py_modules=["servo_updater", "fw_update"],
-    entry_points = {
+    entry_points={
         "console_scripts": ["servo_updater=servo_updater:main"],
     },
-    data_files=[("share/servo_updater/configs",
-                    ["extra/usb_updater/c2d2.json",
-                     "extra/usb_updater/servo_v4.json",
-                     "extra/usb_updater/servo_v4p1.json",
-                     "extra/usb_updater/servo_micro.json",
-                     "extra/usb_updater/sweetberry.json"])],
+    data_files=[
+        (
+            "share/servo_updater/configs",
+            [
+                "extra/usb_updater/c2d2.json",
+                "extra/usb_updater/servo_v4.json",
+                "extra/usb_updater/servo_v4p1.json",
+                "extra/usb_updater/servo_micro.json",
+                "extra/usb_updater/sweetberry.json",
+            ],
+        )
+    ],
     description="Servo usb updater.",
 )
 
@@ -53,9 +59,9 @@ setup(
     author="Nick Sanders",
     author_email="nsanders@chromium.org",
     url="https://www.chromium.org/chromium-os/ec-development",
-    package_dir={"" : "extra/usb_power"},
+    package_dir={"": "extra/usb_power"},
     py_modules=["powerlog", "stats_manager"],
-    entry_points = {
+    entry_points={
         "console_scripts": ["powerlog=powerlog:main"],
     },
     description="Sweetberry power logger.",
@@ -67,9 +73,9 @@ setup(
     author="Nick Sanders",
     author_email="nsanders@chromium.org",
     url="https://www.chromium.org/chromium-os/ec-development",
-    package_dir={"" : "extra/usb_serial"},
+    package_dir={"": "extra/usb_serial"},
     py_modules=["console"],
-    entry_points = {
+    entry_points={
         "console_scripts": ["usb_console=console:main"],
     },
     description="Tool to open the usb console on servo, cr50.",
@@ -81,11 +87,10 @@ setup(
     author="Wei-Han Chen",
     author_email="stimim@chromium.org",
     url="https://www.chromium.org/chromium-os/ec-development",
-    package_dir={"" : "util"},
+    package_dir={"": "util"},
     py_modules=["unpack_ftb"],
-    entry_points = {
+    entry_points={
         "console_scripts": ["unpack_ftb=unpack_ftb:main"],
     },
     description="Tool to convert ST touchpad .ftb file to .bin",
 )
-
diff --git a/test/accel_cal.c b/test/accel_cal.c
index 34fd5678c2..840bed00c6 100644
--- a/test/accel_cal.c
+++ b/test/accel_cal.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -29,12 +29,12 @@ struct accel_cal cal = {
 
 static bool accumulate(float x, float y, float z, float temperature)
 {
-	return accel_cal_accumulate(&cal, 0, x, y, z, temperature)
-		|| accel_cal_accumulate(&cal, 200 * MSEC, x, y, z, temperature)
-		|| accel_cal_accumulate(&cal, 400 * MSEC, x, y, z, temperature)
-		|| accel_cal_accumulate(&cal, 600 * MSEC, x, y, z, temperature)
-		|| accel_cal_accumulate(&cal, 800 * MSEC, x, y, z, temperature)
-		|| accel_cal_accumulate(&cal, 1000 * MSEC, x, y, z, temperature);
+	return accel_cal_accumulate(&cal, 0, x, y, z, temperature) ||
+	       accel_cal_accumulate(&cal, 200 * MSEC, x, y, z, temperature) ||
+	       accel_cal_accumulate(&cal, 400 * MSEC, x, y, z, temperature) ||
+	       accel_cal_accumulate(&cal, 600 * MSEC, x, y, z, temperature) ||
+	       accel_cal_accumulate(&cal, 800 * MSEC, x, y, z, temperature) ||
+	       accel_cal_accumulate(&cal, 1000 * MSEC, x, y, z, temperature);
 }
 
 DECLARE_EC_TEST(test_calibrated_correctly_with_kasa)
@@ -66,20 +66,16 @@ DECLARE_EC_TEST(test_calibrated_correctly_with_newton)
 	float kasa_radius;
 	int i;
 	float data[] = {
-		1.00290f, 0.09170f, 0.09649f,
-		0.95183f, 0.23626f, 0.25853f,
-		0.95023f, 0.15387f, 0.31865f,
-		0.97374f, 0.01639f, 0.27675f,
-		0.88521f, 0.30212f, 0.39558f,
-		0.92787f, 0.35157f, 0.21209f,
-		0.95162f, 0.33173f, 0.10924f,
-		0.98397f, 0.22644f, 0.07737f,
+		1.00290f, 0.09170f, 0.09649f, 0.95183f, 0.23626f, 0.25853f,
+		0.95023f, 0.15387f, 0.31865f, 0.97374f, 0.01639f, 0.27675f,
+		0.88521f, 0.30212f, 0.39558f, 0.92787f, 0.35157f, 0.21209f,
+		0.95162f, 0.33173f, 0.10924f, 0.98397f, 0.22644f, 0.07737f,
 	};
 
 	kasa_reset(&kasa);
 	for (i = 0; i < ARRAY_SIZE(data); i += 3) {
 		zassert_false(has_bias, NULL);
-		kasa_accumulate(&kasa,  data[i], data[i + 1], data[i + 2]);
+		kasa_accumulate(&kasa, data[i], data[i + 1], data[i + 2]);
 		has_bias = accumulate(data[i], data[i + 1], data[i + 2], 21.0f);
 	}
 
@@ -93,9 +89,9 @@ DECLARE_EC_TEST(test_calibrated_correctly_with_newton)
 	zassert_true(sqrtf(powf(cal.bias[X] - 0.01f, 2.0f) +
 			   powf(cal.bias[Y] - 0.01f, 2.0f) +
 			   powf(cal.bias[Z] - 0.01f, 2.0f)) <
-		     sqrtf(powf(kasa_bias[X] - 0.01f, 2.0f) +
-			   powf(kasa_bias[Y] - 0.01f, 2.0f) +
-			   powf(kasa_bias[Z] - 0.01f, 2.0f)),
+			     sqrtf(powf(kasa_bias[X] - 0.01f, 2.0f) +
+				   powf(kasa_bias[Y] - 0.01f, 2.0f) +
+				   powf(kasa_bias[Z] - 0.01f, 2.0f)),
 		     NULL);
 
 	return EC_SUCCESS;
@@ -125,7 +121,9 @@ void before_test(void)
 	accel_cal_reset(&cal);
 }
 
-void after_test(void) {}
+void after_test(void)
+{
+}
 
 TEST_MAIN()
 {
diff --git a/test/accel_cal.tasklist b/test/accel_cal.tasklist
index 0e3696c3f0..d3fcf83121 100644
--- a/test/accel_cal.tasklist
+++ b/test/accel_cal.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/aes.c b/test/aes.c
index 1c71e2874e..0fc220d997 100644
--- a/test/aes.c
+++ b/test/aes.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -16,6 +16,7 @@
 
 #include "aes.h"
 #include "aes-gcm.h"
+#include "builtin/assert.h"
 #include "console.h"
 #include "common.h"
 #include "test_util.h"
@@ -29,23 +30,18 @@ static uint8_t tmp[512];
 /*
  * Do encryption, put result in |result|, and compare with |ciphertext|.
  */
-static int test_aes_gcm_encrypt(uint8_t *result,
-				const uint8_t *key,
-				int key_size,
-				const uint8_t *plaintext,
-				const uint8_t *ciphertext,
-				int plaintext_size,
-				const uint8_t *nonce,
-				int nonce_size,
-				const uint8_t *tag,
-				int tag_size)
+static int test_aes_gcm_encrypt(uint8_t *result, const uint8_t *key,
+				int key_size, const uint8_t *plaintext,
+				const uint8_t *ciphertext, int plaintext_size,
+				const uint8_t *nonce, int nonce_size,
+				const uint8_t *tag, int tag_size)
 {
 	static AES_KEY aes_key;
 	static GCM128_CONTEXT ctx;
 
 	TEST_ASSERT(AES_set_encrypt_key(key, 8 * key_size, &aes_key) == 0);
 
-	CRYPTO_gcm128_init(&ctx, &aes_key, (block128_f) AES_encrypt, 0);
+	CRYPTO_gcm128_init(&ctx, &aes_key, (block128_f)AES_encrypt, 0);
 	CRYPTO_gcm128_setiv(&ctx, &aes_key, nonce, nonce_size);
 	TEST_ASSERT(CRYPTO_gcm128_encrypt(&ctx, &aes_key, plaintext, result,
 					  plaintext_size));
@@ -58,23 +54,18 @@ static int test_aes_gcm_encrypt(uint8_t *result,
 /*
  * Do decryption, put result in |result|, and compare with |plaintext|.
  */
-static int test_aes_gcm_decrypt(uint8_t *result,
-				const uint8_t *key,
-				int key_size,
-				const uint8_t *plaintext,
-				const uint8_t *ciphertext,
-				int plaintext_size,
-				const uint8_t *nonce,
-				int nonce_size,
-				const uint8_t *tag,
-				int tag_size)
+static int test_aes_gcm_decrypt(uint8_t *result, const uint8_t *key,
+				int key_size, const uint8_t *plaintext,
+				const uint8_t *ciphertext, int plaintext_size,
+				const uint8_t *nonce, int nonce_size,
+				const uint8_t *tag, int tag_size)
 {
 	static AES_KEY aes_key;
 	static GCM128_CONTEXT ctx;
 
 	TEST_ASSERT(AES_set_encrypt_key(key, 8 * key_size, &aes_key) == 0);
 
-	CRYPTO_gcm128_init(&ctx, &aes_key, (block128_f) AES_encrypt, 0);
+	CRYPTO_gcm128_init(&ctx, &aes_key, (block128_f)AES_encrypt, 0);
 	CRYPTO_gcm128_setiv(&ctx, &aes_key, nonce, nonce_size);
 	TEST_ASSERT(CRYPTO_gcm128_decrypt(&ctx, &aes_key, ciphertext, result,
 					  plaintext_size));
@@ -84,17 +75,13 @@ static int test_aes_gcm_decrypt(uint8_t *result,
 	return EC_SUCCESS;
 }
 
-static int test_aes_gcm_raw_inplace(const uint8_t *key,
-				    int key_size,
+static int test_aes_gcm_raw_inplace(const uint8_t *key, int key_size,
 				    const uint8_t *plaintext,
 				    const uint8_t *ciphertext,
-				    int plaintext_size,
-				    const uint8_t *nonce,
-				    int nonce_size,
-				    const uint8_t *tag,
+				    int plaintext_size, const uint8_t *nonce,
+				    int nonce_size, const uint8_t *tag,
 				    int tag_size)
 {
-
 	/*
 	 * Make copies that will be clobbered during in-place encryption or
 	 * decryption.
@@ -105,95 +92,53 @@ static int test_aes_gcm_raw_inplace(const uint8_t *key,
 	memcpy(plaintext_copy, plaintext, plaintext_size);
 	memcpy(ciphertext_copy, ciphertext, plaintext_size);
 
-	TEST_ASSERT(test_aes_gcm_encrypt(plaintext_copy,
-					 key,
-					 key_size,
-					 plaintext_copy,
-					 ciphertext,
-					 plaintext_size,
-					 nonce,
-					 nonce_size,
-					 tag,
+	TEST_ASSERT(test_aes_gcm_encrypt(plaintext_copy, key, key_size,
+					 plaintext_copy, ciphertext,
+					 plaintext_size, nonce, nonce_size, tag,
 					 tag_size) == EC_SUCCESS);
 
-	TEST_ASSERT(test_aes_gcm_decrypt(ciphertext_copy,
-					 key,
-					 key_size,
-					 plaintext,
-					 ciphertext_copy,
-					 plaintext_size,
-					 nonce,
-					 nonce_size,
-					 tag,
+	TEST_ASSERT(test_aes_gcm_decrypt(ciphertext_copy, key, key_size,
+					 plaintext, ciphertext_copy,
+					 plaintext_size, nonce, nonce_size, tag,
 					 tag_size) == EC_SUCCESS);
 
 	return EC_SUCCESS;
 }
 
-static int test_aes_gcm_raw_non_inplace(const uint8_t *key,
-					int key_size,
+static int test_aes_gcm_raw_non_inplace(const uint8_t *key, int key_size,
 					const uint8_t *plaintext,
 					const uint8_t *ciphertext,
 					int plaintext_size,
-					const uint8_t *nonce,
-					int nonce_size,
-					const uint8_t *tag,
-					int tag_size)
+					const uint8_t *nonce, int nonce_size,
+					const uint8_t *tag, int tag_size)
 {
-	TEST_ASSERT(test_aes_gcm_encrypt(tmp,
-					 key,
-					 key_size,
-					 plaintext,
-					 ciphertext,
-					 plaintext_size,
-					 nonce,
-					 nonce_size,
-					 tag,
+	TEST_ASSERT(test_aes_gcm_encrypt(tmp, key, key_size, plaintext,
+					 ciphertext, plaintext_size, nonce,
+					 nonce_size, tag,
 					 tag_size) == EC_SUCCESS);
 
-	TEST_ASSERT(test_aes_gcm_decrypt(tmp,
-					 key,
-					 key_size,
-					 plaintext,
-					 ciphertext,
-					 plaintext_size,
-					 nonce,
-					 nonce_size,
-					 tag,
+	TEST_ASSERT(test_aes_gcm_decrypt(tmp, key, key_size, plaintext,
+					 ciphertext, plaintext_size, nonce,
+					 nonce_size, tag,
 					 tag_size) == EC_SUCCESS);
 
 	return EC_SUCCESS;
 }
 
-static int test_aes_gcm_raw(const uint8_t *key,
-			    int key_size,
-			    const uint8_t *plaintext,
-			    const uint8_t *ciphertext,
-			    int plaintext_size,
-			    const uint8_t *nonce,
-			    int nonce_size,
-			    const uint8_t *tag,
-			    int tag_size)
+static int test_aes_gcm_raw(const uint8_t *key, int key_size,
+			    const uint8_t *plaintext, const uint8_t *ciphertext,
+			    int plaintext_size, const uint8_t *nonce,
+			    int nonce_size, const uint8_t *tag, int tag_size)
 {
 	TEST_ASSERT(plaintext_size <= sizeof(tmp));
 
-	TEST_ASSERT(test_aes_gcm_raw_non_inplace(key,
-						 key_size,
-						 plaintext,
-						 ciphertext,
-						 plaintext_size,
-						 nonce,
-						 nonce_size,
-						 tag,
+	TEST_ASSERT(test_aes_gcm_raw_non_inplace(key, key_size, plaintext,
+						 ciphertext, plaintext_size,
+						 nonce, nonce_size, tag,
 						 tag_size) == EC_SUCCESS);
-	TEST_ASSERT(test_aes_gcm_raw_inplace(key,
-					     key_size,
-					     plaintext,
-					     ciphertext,
-					     plaintext_size,
-					     nonce,
-					     nonce_size,
-					     tag,
+	TEST_ASSERT(test_aes_gcm_raw_inplace(key, key_size, plaintext,
+					     ciphertext, plaintext_size, nonce,
+					     nonce_size, tag,
 					     tag_size) == EC_SUCCESS);
 
 	return EC_SUCCESS;
@@ -214,8 +159,8 @@ static int test_aes_gcm(void)
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	};
 	static const uint8_t nonce1[] = {
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	};
 	static const uint8_t cipher1[] = {
 		0x03, 0x88, 0xda, 0xce, 0x60, 0xb6, 0xa3, 0x92,
@@ -231,28 +176,26 @@ static int test_aes_gcm(void)
 		0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08,
 	};
 	static const uint8_t plain2[] = {
-		0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5,
-		0xa5, 0x59, 0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a,
-		0x86, 0xa7, 0xa9, 0x53, 0x15, 0x34, 0xf7, 0xda,
-		0x2e, 0x4c, 0x30, 0x3d, 0x8a, 0x31, 0x8a, 0x72,
-		0x1c, 0x3c, 0x0c, 0x95, 0x95, 0x68, 0x09, 0x53,
-		0x2f, 0xcf, 0x0e, 0x24, 0x49, 0xa6, 0xb5, 0x25,
-		0xb1, 0x6a, 0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57,
-		0xba, 0x63, 0x7b, 0x39, 0x1a, 0xaf, 0xd2, 0x55,
+		0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5, 0xa5, 0x59,
+		0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a, 0x86, 0xa7, 0xa9, 0x53,
+		0x15, 0x34, 0xf7, 0xda, 0x2e, 0x4c, 0x30, 0x3d, 0x8a, 0x31,
+		0x8a, 0x72, 0x1c, 0x3c, 0x0c, 0x95, 0x95, 0x68, 0x09, 0x53,
+		0x2f, 0xcf, 0x0e, 0x24, 0x49, 0xa6, 0xb5, 0x25, 0xb1, 0x6a,
+		0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57, 0xba, 0x63, 0x7b, 0x39,
+		0x1a, 0xaf, 0xd2, 0x55,
 	};
 	static const uint8_t nonce2[] = {
-		0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce, 0xdb, 0xad,
-		0xde, 0xca, 0xf8, 0x88,
+		0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce,
+		0xdb, 0xad, 0xde, 0xca, 0xf8, 0x88,
 	};
 	static const uint8_t cipher2[] = {
-		0x42, 0x83, 0x1e, 0xc2, 0x21, 0x77, 0x74, 0x24,
-		0x4b, 0x72, 0x21, 0xb7, 0x84, 0xd0, 0xd4, 0x9c,
-		0xe3, 0xaa, 0x21, 0x2f, 0x2c, 0x02, 0xa4, 0xe0,
-		0x35, 0xc1, 0x7e, 0x23, 0x29, 0xac, 0xa1, 0x2e,
-		0x21, 0xd5, 0x14, 0xb2, 0x54, 0x66, 0x93, 0x1c,
-		0x7d, 0x8f, 0x6a, 0x5a, 0xac, 0x84, 0xaa, 0x05,
-		0x1b, 0xa3, 0x0b, 0x39, 0x6a, 0x0a, 0xac, 0x97,
-		0x3d, 0x58, 0xe0, 0x91, 0x47, 0x3f, 0x59, 0x85,
+		0x42, 0x83, 0x1e, 0xc2, 0x21, 0x77, 0x74, 0x24, 0x4b, 0x72,
+		0x21, 0xb7, 0x84, 0xd0, 0xd4, 0x9c, 0xe3, 0xaa, 0x21, 0x2f,
+		0x2c, 0x02, 0xa4, 0xe0, 0x35, 0xc1, 0x7e, 0x23, 0x29, 0xac,
+		0xa1, 0x2e, 0x21, 0xd5, 0x14, 0xb2, 0x54, 0x66, 0x93, 0x1c,
+		0x7d, 0x8f, 0x6a, 0x5a, 0xac, 0x84, 0xaa, 0x05, 0x1b, 0xa3,
+		0x0b, 0x39, 0x6a, 0x0a, 0xac, 0x97, 0x3d, 0x58, 0xe0, 0x91,
+		0x47, 0x3f, 0x59, 0x85,
 	};
 	static const uint8_t tag2[] = {
 		0x4d, 0x5c, 0x2a, 0xf3, 0x27, 0xcd, 0x64, 0xa6,
@@ -269,8 +212,8 @@ static int test_aes_gcm(void)
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	};
 	static const uint8_t nonce3[] = {
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	};
 	static const uint8_t cipher3[] = {
 		0x98, 0xe7, 0x24, 0x7c, 0x07, 0xf0, 0xfe, 0x41,
@@ -287,28 +230,26 @@ static int test_aes_gcm(void)
 		0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c,
 	};
 	static const uint8_t plain4[] = {
-		0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5,
-		0xa5, 0x59, 0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a,
-		0x86, 0xa7, 0xa9, 0x53, 0x15, 0x34, 0xf7, 0xda,
-		0x2e, 0x4c, 0x30, 0x3d, 0x8a, 0x31, 0x8a, 0x72,
-		0x1c, 0x3c, 0x0c, 0x95, 0x95, 0x68, 0x09, 0x53,
-		0x2f, 0xcf, 0x0e, 0x24, 0x49, 0xa6, 0xb5, 0x25,
-		0xb1, 0x6a, 0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57,
-		0xba, 0x63, 0x7b, 0x39, 0x1a, 0xaf, 0xd2, 0x55,
+		0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5, 0xa5, 0x59,
+		0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a, 0x86, 0xa7, 0xa9, 0x53,
+		0x15, 0x34, 0xf7, 0xda, 0x2e, 0x4c, 0x30, 0x3d, 0x8a, 0x31,
+		0x8a, 0x72, 0x1c, 0x3c, 0x0c, 0x95, 0x95, 0x68, 0x09, 0x53,
+		0x2f, 0xcf, 0x0e, 0x24, 0x49, 0xa6, 0xb5, 0x25, 0xb1, 0x6a,
+		0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57, 0xba, 0x63, 0x7b, 0x39,
+		0x1a, 0xaf, 0xd2, 0x55,
 	};
 	static const uint8_t nonce4[] = {
-		0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce, 0xdb, 0xad,
-		0xde, 0xca, 0xf8, 0x88,
+		0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce,
+		0xdb, 0xad, 0xde, 0xca, 0xf8, 0x88,
 	};
 	static const uint8_t cipher4[] = {
-		0x39, 0x80, 0xca, 0x0b, 0x3c, 0x00, 0xe8, 0x41,
-		0xeb, 0x06, 0xfa, 0xc4, 0x87, 0x2a, 0x27, 0x57,
-		0x85, 0x9e, 0x1c, 0xea, 0xa6, 0xef, 0xd9, 0x84,
-		0x62, 0x85, 0x93, 0xb4, 0x0c, 0xa1, 0xe1, 0x9c,
-		0x7d, 0x77, 0x3d, 0x00, 0xc1, 0x44, 0xc5, 0x25,
-		0xac, 0x61, 0x9d, 0x18, 0xc8, 0x4a, 0x3f, 0x47,
-		0x18, 0xe2, 0x44, 0x8b, 0x2f, 0xe3, 0x24, 0xd9,
-		0xcc, 0xda, 0x27, 0x10, 0xac, 0xad, 0xe2, 0x56,
+		0x39, 0x80, 0xca, 0x0b, 0x3c, 0x00, 0xe8, 0x41, 0xeb, 0x06,
+		0xfa, 0xc4, 0x87, 0x2a, 0x27, 0x57, 0x85, 0x9e, 0x1c, 0xea,
+		0xa6, 0xef, 0xd9, 0x84, 0x62, 0x85, 0x93, 0xb4, 0x0c, 0xa1,
+		0xe1, 0x9c, 0x7d, 0x77, 0x3d, 0x00, 0xc1, 0x44, 0xc5, 0x25,
+		0xac, 0x61, 0x9d, 0x18, 0xc8, 0x4a, 0x3f, 0x47, 0x18, 0xe2,
+		0x44, 0x8b, 0x2f, 0xe3, 0x24, 0xd9, 0xcc, 0xda, 0x27, 0x10,
+		0xac, 0xad, 0xe2, 0x56,
 	};
 	static const uint8_t tag4[] = {
 		0x99, 0x24, 0xa7, 0xc8, 0x58, 0x73, 0x36, 0xbf,
@@ -326,8 +267,8 @@ static int test_aes_gcm(void)
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	};
 	static const uint8_t nonce5[] = {
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	};
 	static const uint8_t cipher5[] = {
 		0xce, 0xa7, 0x40, 0x3d, 0x4d, 0x60, 0x6b, 0x6e,
@@ -345,28 +286,26 @@ static int test_aes_gcm(void)
 		0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08,
 	};
 	static const uint8_t plain6[] = {
-		0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5,
-		0xa5, 0x59, 0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a,
-		0x86, 0xa7, 0xa9, 0x53, 0x15, 0x34, 0xf7, 0xda,
-		0x2e, 0x4c, 0x30, 0x3d, 0x8a, 0x31, 0x8a, 0x72,
-		0x1c, 0x3c, 0x0c, 0x95, 0x95, 0x68, 0x09, 0x53,
-		0x2f, 0xcf, 0x0e, 0x24, 0x49, 0xa6, 0xb5, 0x25,
-		0xb1, 0x6a, 0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57,
-		0xba, 0x63, 0x7b, 0x39, 0x1a, 0xaf, 0xd2, 0x55,
+		0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5, 0xa5, 0x59,
+		0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a, 0x86, 0xa7, 0xa9, 0x53,
+		0x15, 0x34, 0xf7, 0xda, 0x2e, 0x4c, 0x30, 0x3d, 0x8a, 0x31,
+		0x8a, 0x72, 0x1c, 0x3c, 0x0c, 0x95, 0x95, 0x68, 0x09, 0x53,
+		0x2f, 0xcf, 0x0e, 0x24, 0x49, 0xa6, 0xb5, 0x25, 0xb1, 0x6a,
+		0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57, 0xba, 0x63, 0x7b, 0x39,
+		0x1a, 0xaf, 0xd2, 0x55,
 	};
 	static const uint8_t nonce6[] = {
-		0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce, 0xdb, 0xad,
-		0xde, 0xca, 0xf8, 0x88,
+		0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce,
+		0xdb, 0xad, 0xde, 0xca, 0xf8, 0x88,
 	};
 	static const uint8_t cipher6[] = {
-		0x52, 0x2d, 0xc1, 0xf0, 0x99, 0x56, 0x7d, 0x07,
-		0xf4, 0x7f, 0x37, 0xa3, 0x2a, 0x84, 0x42, 0x7d,
-		0x64, 0x3a, 0x8c, 0xdc, 0xbf, 0xe5, 0xc0, 0xc9,
-		0x75, 0x98, 0xa2, 0xbd, 0x25, 0x55, 0xd1, 0xaa,
-		0x8c, 0xb0, 0x8e, 0x48, 0x59, 0x0d, 0xbb, 0x3d,
-		0xa7, 0xb0, 0x8b, 0x10, 0x56, 0x82, 0x88, 0x38,
-		0xc5, 0xf6, 0x1e, 0x63, 0x93, 0xba, 0x7a, 0x0a,
-		0xbc, 0xc9, 0xf6, 0x62, 0x89, 0x80, 0x15, 0xad,
+		0x52, 0x2d, 0xc1, 0xf0, 0x99, 0x56, 0x7d, 0x07, 0xf4, 0x7f,
+		0x37, 0xa3, 0x2a, 0x84, 0x42, 0x7d, 0x64, 0x3a, 0x8c, 0xdc,
+		0xbf, 0xe5, 0xc0, 0xc9, 0x75, 0x98, 0xa2, 0xbd, 0x25, 0x55,
+		0xd1, 0xaa, 0x8c, 0xb0, 0x8e, 0x48, 0x59, 0x0d, 0xbb, 0x3d,
+		0xa7, 0xb0, 0x8b, 0x10, 0x56, 0x82, 0x88, 0x38, 0xc5, 0xf6,
+		0x1e, 0x63, 0x93, 0xba, 0x7a, 0x0a, 0xbc, 0xc9, 0xf6, 0x62,
+		0x89, 0x80, 0x15, 0xad,
 	};
 	static const uint8_t tag6[] = {
 		0xb0, 0x94, 0xda, 0xc5, 0xd9, 0x34, 0x71, 0xbd,
@@ -378,90 +317,75 @@ static int test_aes_gcm(void)
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	};
 	static const uint8_t plain7[] = {
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	};
 	/* This nonce results in 0xfff in counter LSB. */
 	static const uint8_t nonce7[] = {
-		0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00,
 	};
 	static const uint8_t cipher7[] = {
-		0x56, 0xb3, 0x37, 0x3c, 0xa9, 0xef, 0x6e, 0x4a,
-		0x2b, 0x64, 0xfe, 0x1e, 0x9a, 0x17, 0xb6, 0x14,
-		0x25, 0xf1, 0x0d, 0x47, 0xa7, 0x5a, 0x5f, 0xce,
-		0x13, 0xef, 0xc6, 0xbc, 0x78, 0x4a, 0xf2, 0x4f,
-		0x41, 0x41, 0xbd, 0xd4, 0x8c, 0xf7, 0xc7, 0x70,
-		0x88, 0x7a, 0xfd, 0x57, 0x3c, 0xca, 0x54, 0x18,
-		0xa9, 0xae, 0xff, 0xcd, 0x7c, 0x5c, 0xed, 0xdf,
-		0xc6, 0xa7, 0x83, 0x97, 0xb9, 0xa8, 0x5b, 0x49,
-		0x9d, 0xa5, 0x58, 0x25, 0x72, 0x67, 0xca, 0xab,
-		0x2a, 0xd0, 0xb2, 0x3c, 0xa4, 0x76, 0xa5, 0x3c,
-		0xb1, 0x7f, 0xb4, 0x1c, 0x4b, 0x8b, 0x47, 0x5c,
-		0xb4, 0xf3, 0xf7, 0x16, 0x50, 0x94, 0xc2, 0x29,
-		0xc9, 0xe8, 0xc4, 0xdc, 0x0a, 0x2a, 0x5f, 0xf1,
-		0x90, 0x3e, 0x50, 0x15, 0x11, 0x22, 0x13, 0x76,
-		0xa1, 0xcd, 0xb8, 0x36, 0x4c, 0x50, 0x61, 0xa2,
-		0x0c, 0xae, 0x74, 0xbc, 0x4a, 0xcd, 0x76, 0xce,
-		0xb0, 0xab, 0xc9, 0xfd, 0x32, 0x17, 0xef, 0x9f,
-		0x8c, 0x90, 0xbe, 0x40, 0x2d, 0xdf, 0x6d, 0x86,
-		0x97, 0xf4, 0xf8, 0x80, 0xdf, 0xf1, 0x5b, 0xfb,
-		0x7a, 0x6b, 0x28, 0x24, 0x1e, 0xc8, 0xfe, 0x18,
-		0x3c, 0x2d, 0x59, 0xe3, 0xf9, 0xdf, 0xff, 0x65,
-		0x3c, 0x71, 0x26, 0xf0, 0xac, 0xb9, 0xe6, 0x42,
-		0x11, 0xf4, 0x2b, 0xae, 0x12, 0xaf, 0x46, 0x2b,
-		0x10, 0x70, 0xbe, 0xf1, 0xab, 0x5e, 0x36, 0x06,
-		0x87, 0x2c, 0xa1, 0x0d, 0xee, 0x15, 0xb3, 0x24,
-		0x9b, 0x1a, 0x1b, 0x95, 0x8f, 0x23, 0x13, 0x4c,
-		0x4b, 0xcc, 0xb7, 0xd0, 0x32, 0x00, 0xbc, 0xe4,
-		0x20, 0xa2, 0xf8, 0xeb, 0x66, 0xdc, 0xf3, 0x64,
-		0x4d, 0x14, 0x23, 0xc1, 0xb5, 0x69, 0x90, 0x03,
-		0xc1, 0x3e, 0xce, 0xf4, 0xbf, 0x38, 0xa3, 0xb6,
-		0x0e, 0xed, 0xc3, 0x40, 0x33, 0xba, 0xc1, 0x90,
-		0x27, 0x83, 0xdc, 0x6d, 0x89, 0xe2, 0xe7, 0x74,
-		0x18, 0x8a, 0x43, 0x9c, 0x7e, 0xbc, 0xc0, 0x67,
-		0x2d, 0xbd, 0xa4, 0xdd, 0xcf, 0xb2, 0x79, 0x46,
-		0x13, 0xb0, 0xbe, 0x41, 0x31, 0x5e, 0xf7, 0x78,
+		0x56, 0xb3, 0x37, 0x3c, 0xa9, 0xef, 0x6e, 0x4a, 0x2b, 0x64,
+		0xfe, 0x1e, 0x9a, 0x17, 0xb6, 0x14, 0x25, 0xf1, 0x0d, 0x47,
+		0xa7, 0x5a, 0x5f, 0xce, 0x13, 0xef, 0xc6, 0xbc, 0x78, 0x4a,
+		0xf2, 0x4f, 0x41, 0x41, 0xbd, 0xd4, 0x8c, 0xf7, 0xc7, 0x70,
+		0x88, 0x7a, 0xfd, 0x57, 0x3c, 0xca, 0x54, 0x18, 0xa9, 0xae,
+		0xff, 0xcd, 0x7c, 0x5c, 0xed, 0xdf, 0xc6, 0xa7, 0x83, 0x97,
+		0xb9, 0xa8, 0x5b, 0x49, 0x9d, 0xa5, 0x58, 0x25, 0x72, 0x67,
+		0xca, 0xab, 0x2a, 0xd0, 0xb2, 0x3c, 0xa4, 0x76, 0xa5, 0x3c,
+		0xb1, 0x7f, 0xb4, 0x1c, 0x4b, 0x8b, 0x47, 0x5c, 0xb4, 0xf3,
+		0xf7, 0x16, 0x50, 0x94, 0xc2, 0x29, 0xc9, 0xe8, 0xc4, 0xdc,
+		0x0a, 0x2a, 0x5f, 0xf1, 0x90, 0x3e, 0x50, 0x15, 0x11, 0x22,
+		0x13, 0x76, 0xa1, 0xcd, 0xb8, 0x36, 0x4c, 0x50, 0x61, 0xa2,
+		0x0c, 0xae, 0x74, 0xbc, 0x4a, 0xcd, 0x76, 0xce, 0xb0, 0xab,
+		0xc9, 0xfd, 0x32, 0x17, 0xef, 0x9f, 0x8c, 0x90, 0xbe, 0x40,
+		0x2d, 0xdf, 0x6d, 0x86, 0x97, 0xf4, 0xf8, 0x80, 0xdf, 0xf1,
+		0x5b, 0xfb, 0x7a, 0x6b, 0x28, 0x24, 0x1e, 0xc8, 0xfe, 0x18,
+		0x3c, 0x2d, 0x59, 0xe3, 0xf9, 0xdf, 0xff, 0x65, 0x3c, 0x71,
+		0x26, 0xf0, 0xac, 0xb9, 0xe6, 0x42, 0x11, 0xf4, 0x2b, 0xae,
+		0x12, 0xaf, 0x46, 0x2b, 0x10, 0x70, 0xbe, 0xf1, 0xab, 0x5e,
+		0x36, 0x06, 0x87, 0x2c, 0xa1, 0x0d, 0xee, 0x15, 0xb3, 0x24,
+		0x9b, 0x1a, 0x1b, 0x95, 0x8f, 0x23, 0x13, 0x4c, 0x4b, 0xcc,
+		0xb7, 0xd0, 0x32, 0x00, 0xbc, 0xe4, 0x20, 0xa2, 0xf8, 0xeb,
+		0x66, 0xdc, 0xf3, 0x64, 0x4d, 0x14, 0x23, 0xc1, 0xb5, 0x69,
+		0x90, 0x03, 0xc1, 0x3e, 0xce, 0xf4, 0xbf, 0x38, 0xa3, 0xb6,
+		0x0e, 0xed, 0xc3, 0x40, 0x33, 0xba, 0xc1, 0x90, 0x27, 0x83,
+		0xdc, 0x6d, 0x89, 0xe2, 0xe7, 0x74, 0x18, 0x8a, 0x43, 0x9c,
+		0x7e, 0xbc, 0xc0, 0x67, 0x2d, 0xbd, 0xa4, 0xdd, 0xcf, 0xb2,
+		0x79, 0x46, 0x13, 0xb0, 0xbe, 0x41, 0x31, 0x5e, 0xf7, 0x78,
 		0x70, 0x8a, 0x70, 0xee, 0x7d, 0x75, 0x16, 0x5c,
 	};
 	static const uint8_t tag7[] = {
@@ -469,27 +393,27 @@ static int test_aes_gcm(void)
 		0xb0, 0x26, 0xa9, 0xed, 0x3f, 0xe1, 0xe8, 0x5f,
 	};
 
-	TEST_ASSERT(!test_aes_gcm_raw(key1, sizeof(key1),
-			plain1, cipher1, sizeof(plain1),
-			nonce1, sizeof(nonce1), tag1, sizeof(tag1)));
-	TEST_ASSERT(!test_aes_gcm_raw(key2, sizeof(key2),
-			plain2, cipher2, sizeof(plain2),
-			nonce2, sizeof(nonce2), tag2, sizeof(tag2)));
-	TEST_ASSERT(!test_aes_gcm_raw(key3, sizeof(key3),
-			plain3, cipher3, sizeof(plain3),
-			nonce3, sizeof(nonce3), tag3, sizeof(tag3)));
-	TEST_ASSERT(!test_aes_gcm_raw(key4, sizeof(key4),
-			plain4, cipher4, sizeof(plain4),
-			nonce4, sizeof(nonce4), tag4, sizeof(tag4)));
-	TEST_ASSERT(!test_aes_gcm_raw(key5, sizeof(key5),
-			plain5, cipher5, sizeof(plain5),
-			nonce5, sizeof(nonce5), tag5, sizeof(tag5)));
-	TEST_ASSERT(!test_aes_gcm_raw(key6, sizeof(key6),
-			plain6, cipher6, sizeof(plain6),
-			nonce6, sizeof(nonce6), tag6, sizeof(tag6)));
-	TEST_ASSERT(!test_aes_gcm_raw(key7, sizeof(key7),
-			plain7, cipher7, sizeof(plain7),
-			nonce7, sizeof(nonce7), tag7, sizeof(tag7)));
+	TEST_ASSERT(!test_aes_gcm_raw(key1, sizeof(key1), plain1, cipher1,
+				      sizeof(plain1), nonce1, sizeof(nonce1),
+				      tag1, sizeof(tag1)));
+	TEST_ASSERT(!test_aes_gcm_raw(key2, sizeof(key2), plain2, cipher2,
+				      sizeof(plain2), nonce2, sizeof(nonce2),
+				      tag2, sizeof(tag2)));
+	TEST_ASSERT(!test_aes_gcm_raw(key3, sizeof(key3), plain3, cipher3,
+				      sizeof(plain3), nonce3, sizeof(nonce3),
+				      tag3, sizeof(tag3)));
+	TEST_ASSERT(!test_aes_gcm_raw(key4, sizeof(key4), plain4, cipher4,
+				      sizeof(plain4), nonce4, sizeof(nonce4),
+				      tag4, sizeof(tag4)));
+	TEST_ASSERT(!test_aes_gcm_raw(key5, sizeof(key5), plain5, cipher5,
+				      sizeof(plain5), nonce5, sizeof(nonce5),
+				      tag5, sizeof(tag5)));
+	TEST_ASSERT(!test_aes_gcm_raw(key6, sizeof(key6), plain6, cipher6,
+				      sizeof(plain6), nonce6, sizeof(nonce6),
+				      tag6, sizeof(tag6)));
+	TEST_ASSERT(!test_aes_gcm_raw(key7, sizeof(key7), plain7, cipher7,
+				      sizeof(plain7), nonce7, sizeof(nonce7),
+				      tag7, sizeof(tag7)));
 
 	return EC_SUCCESS;
 }
@@ -505,11 +429,11 @@ static void test_aes_gcm_speed(void)
 	static const uint8_t plaintext[512] = { 0 };
 	const int plaintext_size = sizeof(plaintext);
 	static const uint8_t nonce[] = {
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	};
 	const int nonce_size = sizeof(nonce);
-	uint8_t tag[16] = {0};
+	uint8_t tag[16] = { 0 };
 	const int tag_size = sizeof(tag);
 
 	uint8_t *out = tmp;
@@ -525,7 +449,7 @@ static void test_aes_gcm_speed(void)
 		CRYPTO_gcm128_init(&ctx, &aes_key, (block128_f)AES_encrypt, 0);
 		CRYPTO_gcm128_setiv(&ctx, &aes_key, nonce, nonce_size);
 		CRYPTO_gcm128_encrypt(&ctx, &aes_key, plaintext, out,
-				plaintext_size);
+				      plaintext_size);
 		CRYPTO_gcm128_tag(&ctx, tag, tag_size);
 	}
 	t1 = get_time();
@@ -644,7 +568,7 @@ static void test_aes_speed(void)
 	ccprintf("AES duration %lld us\n", (long long)(t1.val - t0.val));
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	watchdog_reload();
 
diff --git a/test/aes.tasklist b/test/aes.tasklist
index 24870f2abb..86bc8aa2d5 100644
--- a/test/aes.tasklist
+++ b/test/aes.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/base32.c b/test/base32.c
index faaefc266f..3559d0dc84 100644
--- a/test/base32.c
+++ b/test/base32.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -54,8 +54,7 @@ DECLARE_EC_TEST(test_crc5)
 	return EC_SUCCESS;
 }
 
-static int enctest(const void *src, int srcbits, int crc_every,
-		   const char *enc)
+static int enctest(const void *src, int srcbits, int crc_every, const char *enc)
 {
 	char dest[32];
 
@@ -73,7 +72,7 @@ static int enctest(const void *src, int srcbits, int crc_every,
 
 DECLARE_EC_TEST(test_encode)
 {
-	const uint8_t src1[5] = {0xff, 0x00, 0xff, 0x00, 0xff};
+	const uint8_t src1[5] = { 0xff, 0x00, 0xff, 0x00, 0xff };
 	char enc[32];
 
 	/* Test for enough space; error produces null string */
@@ -104,10 +103,9 @@ DECLARE_EC_TEST(test_encode)
 	/* CRC requires exact multiple of symbol count */
 	ENCTEST("\xff\x00\xff\x00\xff", 40, 4, "96ARU8AH9D");
 	ENCTEST("\xff\x00\xff\x00\xff", 40, 8, "96AR8AH9L");
-	zassert_equal(
-		base32_encode(enc, 16, (uint8_t *)"\xff\x00\xff\x00\xff",
-			40, 6),
-		EC_ERROR_INVAL, NULL);
+	zassert_equal(base32_encode(enc, 16, (uint8_t *)"\xff\x00\xff\x00\xff",
+				    40, 6),
+		      EC_ERROR_INVAL, NULL);
 	/* But what matters is symbol count, not bit count */
 	ENCTEST("\xff\x00\xff\x00\xfe", 39, 4, "96ARU8AH8P");
 
@@ -201,8 +199,7 @@ DECLARE_EC_TEST(test_decode)
 
 TEST_MAIN()
 {
-	ztest_test_suite(test_base32_lib,
-			 ztest_unit_test(test_crc5),
+	ztest_test_suite(test_base32_lib, ztest_unit_test(test_crc5),
 			 ztest_unit_test(test_encode),
 			 ztest_unit_test(test_decode));
 	ztest_run_test_suite(test_base32_lib);
diff --git a/test/base32.tasklist b/test/base32.tasklist
index 7150f17cbd..6373a70ab1 100644
--- a/test/base32.tasklist
+++ b/test/base32.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/battery_get_params_smart.c b/test/battery_get_params_smart.c
index 3163fb587e..42582df363 100644
--- a/test/battery_get_params_smart.c
+++ b/test/battery_get_params_smart.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,7 +19,6 @@ static int fail_on_first, fail_on_last;
 static int read_count, write_count;
 struct batt_params batt;
 
-
 void battery_compensate_params(struct batt_params *batt)
 {
 }
@@ -44,17 +43,14 @@ int sb_read(int cmd, int *param)
 	if (read_count >= fail_on_first && read_count <= fail_on_last)
 		return EC_ERROR_UNKNOWN;
 
-	return i2c_read16(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS,
-			  cmd, param);
+	return i2c_read16(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS, cmd, param);
 }
 int sb_write(int cmd, int param)
 {
 	write_count++;
-	return i2c_write16(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS,
-			   cmd, param);
+	return i2c_write16(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS, cmd, param);
 }
 
-
 /* Tests */
 static int test_param_failures(void)
 {
@@ -90,7 +86,7 @@ static int test_param_failures(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	RUN_TEST(test_param_failures);
 
diff --git a/test/battery_get_params_smart.tasklist b/test/battery_get_params_smart.tasklist
index c2eb8159a9..efcc6883a5 100644
--- a/test/battery_get_params_smart.tasklist
+++ b/test/battery_get_params_smart.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/bklight_lid.c b/test/bklight_lid.c
index 99167a71a6..52fc91f677 100644
--- a/test/bklight_lid.c
+++ b/test/bklight_lid.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -95,7 +95,7 @@ static int test_hostcommand(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/bklight_lid.tasklist b/test/bklight_lid.tasklist
index da0ab6211a..100cb6b5bd 100644
--- a/test/bklight_lid.tasklist
+++ b/test/bklight_lid.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/bklight_passthru.c b/test/bklight_passthru.c
index 170cc734cd..2bba2fe713 100644
--- a/test/bklight_passthru.c
+++ b/test/bklight_passthru.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -129,7 +129,7 @@ static int test_hostcommand(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/bklight_passthru.tasklist b/test/bklight_passthru.tasklist
index da0ab6211a..100cb6b5bd 100644
--- a/test/bklight_passthru.tasklist
+++ b/test/bklight_passthru.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/body_detection.c b/test/body_detection.c
index aa131f0a31..dac2202eac 100644
--- a/test/body_detection.c
+++ b/test/body_detection.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -105,8 +105,7 @@ static int test_body_detect(void)
 	return EC_SUCCESS;
 }
 
-
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/body_detection.tasklist b/test/body_detection.tasklist
index 95a30e9973..7926640d53 100644
--- a/test/body_detection.tasklist
+++ b/test/body_detection.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/body_detection_data_literals.c b/test/body_detection_data_literals.c
index 96a0cc2f8f..cafe1d6ade 100644
--- a/test/body_detection_data_literals.c
+++ b/test/body_detection_data_literals.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,6208 +6,6208 @@
 
 const struct body_detect_test_data kBodyDetectOnBodyTestData[] = {
 	/*       x,		y,		z, action*/
-	{3.233367f,	1.968032f,	8.875299f,	0},
-	{3.190272f,	2.127247f,	9.054865f,	0},
-	{3.361457f,	2.057815f,	9.054865f,	0},
-	{3.377019f,	1.917754f,	9.093172f,	0},
-	{3.460816f,	1.817198f,	9.058456f,	0},
-	{3.500320f,	1.726218f,	8.900438f,	0},
-	{3.715799f,	1.363497f,	8.836992f,	0},
-	{3.883393f,	0.884657f,	8.832204f,	0},
-	{3.948036f,	0.577002f,	9.016558f,	0},
-	{3.600877f,	0.717063f,	9.200911f,	0},
-	{3.318361f,	0.854729f,	9.166195f,	0},
-	{3.272871f,	0.731428f,	9.149436f,	0},
-	{3.452436f,	0.250194f,	9.297876f,	0},
-	{3.817552f,	-0.353144f,	9.424768f,	0},
-	{3.828326f,	-0.495599f,	9.284708f,	0},
-	{3.312376f,	-0.040701f,	9.204502f,	0},
-	{3.049014f,	0.515950f,	9.223656f,	0},
-	{3.099292f,	0.980425f,	8.882483f,	0},
-	{3.153162f,	1.443703f,	8.154645f,	0},
-	{3.501518f,	1.487995f,	8.054089f,	0},
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+	{ 9.215276f, -3.016692f, -0.532710f, 0 },
+	{ 9.226050f, -2.573765f, 1.215057f, 0 },
+	{ 9.278723f, -2.743753f, 0.444124f, 0 },
+	{ 9.779110f, -3.204637f, 1.349132f, 0 },
+	{ 9.914383f, -3.223790f, 1.940499f, 0 },
+	{ 9.907200f, -2.806002f, 1.668757f, 0 },
+	{ 10.375266f, -2.416945f, 2.098516f, 0 },
+	{ 11.027685f, -2.161963f, 2.414551f, 0 },
+	{ 11.603491f, -1.948879f, 2.486377f, 0 },
+	{ 11.531665f, -1.472433f, 2.813185f, 0 },
+	{ 10.983393f, -0.723048f, 2.525881f, 0 },
+	{ 9.938325f, 0.086191f, 2.130838f, 0 },
+	{ 8.816642f, 0.365116f, 2.731782f, 0 },
+	{ 10.491385f, 0.019154f, 3.318361f, 0 },
+	{ 10.913961f, -0.289698f, 4.115630f, 0 },
+	{ 9.964661f, 0.154426f, 4.765655f, 0 },
+	{ 7.896072f, 1.101332f, 4.291604f, 0 },
+	{ 7.783545f, 1.666363f, 4.158726f, 0 },
+	{ 8.256399f, 1.159990f, 4.963177f, 0 },
+	{ 8.441950f, 0.727837f, 5.633553f, 0 },
+	{ 7.973883f, 0.981622f, 5.418075f, 0 },
+	{ 7.131125f, 1.492784f, 4.759670f, 0 },
+	{ 7.067678f, 1.640027f, 4.987119f, 0 },
+	{ 7.246047f, 1.323993f, 5.380965f, 0 },
+	{ 7.788333f, 1.154004f, 5.783190f, 0 },
+	{ 8.256399f, 1.544259f, 6.980290f, 0 },
+	{ 8.076834f, 2.169145f, 7.654258f, 0 },
+	{ 7.649469f, 2.182313f, 7.368151f, 0 },
+	{ 7.462722f, 2.094925f, 6.817485f, 0 },
+	{ 6.956348f, 1.817198f, 6.009442f, 0 },
+	{ 6.156685f, 1.295262f, 5.595245f, 0 },
+	{ 5.171472f, 1.101332f, 5.043383f, 0 },
+	{ 4.614820f, 1.007958f, 4.921278f, 0 },
+	{ 4.693829f, 0.915781f, 5.402513f, 0 },
+	{ 4.863817f, 1.090558f, 5.463564f, 0 },
+	{ 4.620806f, 1.468842f, 5.919660f, 0 },
+	{ 4.741713f, 1.361103f, 6.609190f, 0 },
+	{ 4.047395f, 1.677137f, 6.482296f, 0 },
+	{ 4.094082f, 1.859096f, 6.527786f, 0 },
+	{ 4.349064f, 1.829169f, 6.309914f, 0 },
+	{ 4.477154f, 1.816001f, 6.591233f, 0 },
+	{ 4.513067f, 1.195903f, 7.651864f, 0 },
+	{ 5.130771f, 0.706289f, 8.787911f, 0 },
+	{ 5.143939f, 0.804451f, 8.456315f, 0 },
+	{ 4.619609f, 0.244208f, 7.931985f, 0 },
+	{ 3.963598f, -0.852335f, 8.146266f, 0 },
+	{ 4.163514f, -1.314416f, 8.972264f, 0 },
+	{ 4.601653f, -1.395819f, 9.185349f, 0 },
+	{ 4.854240f, -1.686714f, 8.943534f, 0 },
+	{ 4.542994f, -2.023099f, 8.414416f, 0 },
+	{ 3.835509f, -2.602495f, 8.085214f, 0 },
+	{ 2.978385f, -2.853886f, 8.039723f, 0 },
+	{ 2.686292f, -2.522290f, 7.716507f, 0 },
+	{ 2.425325f, -2.989159f, 10.263936f, 0 },
+	{ 1.680728f, -3.276463f, 12.568354f, 0 },
+	{ 1.449688f, -2.462435f, 9.834177f, 0 },
+	{ 1.904586f, -2.296038f, 8.819036f, 0 },
+	{ 2.072180f, -2.254139f, 9.337380f, 0 },
+	{ 2.197876f, -2.144006f, 9.494201f, 0 },
+	{ 2.105699f, -1.899798f, 9.169786f, 0 },
+	{ 1.717839f, -1.751357f, 9.096764f, 0 },
+	{ 1.574187f, -1.813607f, 9.458287f, 0 },
+	{ 1.502361f, -1.717839f, 9.576800f, 0 },
+	{ 1.379059f, -1.528697f, 9.473849f, 0 },
+	{ 1.168370f, -1.182735f, 9.206897f, 0 },
+	{ 1.060631f, -1.138442f, 9.701299f, 0 },
+	{ 0.893037f, -1.142033f, 10.007756f, 0 },
+	{ 0.729034f, -1.097741f, 10.362098f, 0 },
+	{ 0.847547f, -1.270123f, 11.415545f, 0 },
+	{ 0.700303f, -1.437717f, 11.802209f, 0 },
+	{ 0.657208f, -0.940921f, 10.297455f, 0 },
+	{ 0.820014f, -0.262165f, 8.865723f, 0 },
+	{ 1.120486f, -0.100556f, 9.303862f, 0 },
+	{ 1.000776f, -0.172382f, 10.194504f, 0 },
+	{ 0.691924f, 0.026336f, 8.984236f, 0 },
+	{ 0.712274f, 0.058658f, 8.265976f, 0 },
+	{ 0.530315f, -0.462081f, 10.773900f, 0 },
+	{ 0.463278f, -0.685938f, 10.289075f, 0 },
+	{ 0.442927f, -0.518344f, 7.893678f, 0 },
+	{ 0.445321f, -0.438139f, 7.972686f, 0 },
+	{ 0.378284f, -0.450110f, 8.655033f, 0 },
+	{ 0.043096f, 0.015562f, 8.980644f, 0 },
+	{ 0.220266f, 0.984016f, 9.639050f, 0 },
+	{ 0.154426f, 1.146822f, 9.488214f, 0 },
+	{ -0.119710f, 1.325190f, 9.168590f, 0 },
+	{ -0.130484f, 1.334767f, 9.746788f, 0 },
+	{ -0.025139f, 1.310825f, 10.338156f, 0 },
+	{ 0.028730f, 1.616085f, 9.712072f, 0 },
+	{ 0.044293f, 1.892615f, 8.583207f, 0 },
+	{ 0.069432f, 1.480813f, 8.564054f, 0 },
+	{ 0.033519f, 1.243787f, 8.768758f, 0 },
+	{ 0.373495f, 1.514332f, 8.633486f, 0 },
+	{ 0.353144f, 1.561018f, 8.446738f, 0 },
+	{ 0.129287f, 1.313219f, 8.616726f, 0 },
+	{ -0.028730f, 0.976834f, 9.123099f, 0 },
+	{ -0.076614f, 0.966060f, 9.351746f, 0 },
+	{ -0.161609f, 1.165975f, 8.965082f, 0 },
+	{ -0.343568f, 1.641224f, 8.194150f, 0 },
+	{ -0.442927f, 1.661575f, 8.437161f, 0 },
+	{ -0.363918f, 1.365891f, 9.854527f, 0 },
+	{ -0.282516f, 1.326387f, 10.666162f, 0 },
+	{ -0.314837f, 1.443703f, 10.433924f, 0 },
+	{ -0.644040f, 1.332372f, 9.327804f, 0 },
+	{ -0.999579f, 1.479616f, 8.036133f, 0 },
+	{ -0.799663f, 1.452082f, 8.346182f, 0 },
+	{ -0.858321f, 1.567004f, 9.868893f, 0 },
+	{ -0.938526f, 1.495178f, 11.599899f, 0 },
+	{ -1.193509f, 1.498769f, 11.905160f, 0 },
+	{ -1.556230f, 1.338358f, 10.947480f, 0 },
+	{ -1.557427f, 1.256955f, 11.003743f, 0 },
+	{ -1.413775f, 1.060631f, 11.848896f, 0 },
+	{ -1.280897f, 0.922964f, 12.215209f, 0 },
+	{ -1.132457f, 0.927753f, 11.399983f, 0 },
+	{ -1.037886f, 0.881066f, 10.413573f, 0 },
+	{ -0.605733f, 0.897825f, 10.074794f, 0 },
+	{ -0.149638f, 0.872686f, 10.181335f, 0 },
+	{ 0.278924f, 0.933738f, 10.765521f, 0 },
+	{ 0.741005f, 1.137245f, 10.898398f, 0 },
+	{ 1.114500f, 1.398213f, 10.672147f, 0 },
+	{ 1.337161f, 1.841140f, 11.609476f, 0 },
+	{ 1.916557f, 1.922543f, 13.679262f, 0 },
+	{ 2.594116f, 1.768117f, 13.814534f, 0 },
+	{ 3.088518f, 2.280476f, 12.144580f, 0 },
+	{ 3.426100f, 2.173934f, 11.726792f, 0 },
+	{ 3.564964f, 1.717839f, 11.662148f, 0 },
+	{ 3.779245f, 1.653195f, 11.219221f, 0 },
+	{ 3.823538f, 1.709459f, 10.377660f, 0 },
 };
 
 const size_t kBodyDetectOnBodyTestDataLength =
 	ARRAY_SIZE(kBodyDetectOnBodyTestData);
 
 const struct body_detect_test_data kBodyDetectOffOnTestData[] = {
-	{-0.269348,	0.220266,	10.030501,	0},
-	{-0.259771,	0.216675,	10.113101,	0},
-	{-0.253785,	0.213084,	10.096342,	0},
-	{-0.262165,	0.201113,	10.098736,	0},
-	{-0.257377,	0.210690,	10.093947,	0},
-	{-0.253785,	0.202310,	10.096342,	0},
-	{-0.257377,	0.213084,	10.113101,	0},
-	{-0.257377,	0.221464,	10.096342,	0},
-	{-0.262165,	0.217872,	10.115496,	0},
-	{-0.258574,	0.219069,	10.102327,	0},
-	{-0.275333,	0.205901,	10.123875,	0},
-	{-0.262165,	0.209493,	10.085567,	0},
-	{-0.271742,	0.209493,	10.110707,	0},
-	{-0.275333,	0.220266,	10.096342,	0},
-	{-0.251391,	0.210690,	10.097539,	0},
-	{-0.262165,	0.210690,	10.090356,	0},
-	{-0.268150,	0.208295,	10.108313,	0},
-	{-0.258574,	0.210690,	10.098736,	0},
-	{-0.270545,	0.219069,	10.097539,	0},
-	{-0.263362,	0.211887,	10.102327,	0},
-	{-0.264559,	0.211887,	10.097539,	0},
-	{-0.262165,	0.204704,	10.090356,	0},
-	{-0.246603,	0.203507,	10.089159,	0},
-	{-0.250194,	0.215478,	10.099933,	0},
-	{-0.270545,	0.225055,	10.109509,	0},
-	{-0.256179,	0.213084,	10.097539,	0},
-	{-0.248997,	0.207098,	10.086765,	0},
-	{-0.248997,	0.210690,	10.087962,	0},
-	{-0.256179,	0.201113,	10.089159,	0},
-	{-0.258574,	0.203507,	10.104721,	0},
-	{-0.262165,	0.208295,	10.093947,	0},
-	{-0.246603,	0.204704,	10.086765,	0},
-	{-0.247800,	0.208295,	10.108313,	0},
-	{-0.252588,	0.220266,	10.099933,	0},
-	{-0.264559,	0.210690,	10.098736,	0},
-	{-0.266953,	0.185551,	10.084371,	0},
-	{-0.253785,	0.213084,	10.109509,	0},
-	{-0.256179,	0.231040,	10.099933,	0},
-	{-0.252588,	0.205901,	10.091554,	0},
-	{-0.259771,	0.207098,	10.095144,	0},
-	{-0.260968,	0.203507,	10.096342,	0},
-	{-0.253785,	0.205901,	10.095144,	0},
-	{-0.256179,	0.217872,	10.093947,	0},
-	{-0.265756,	0.209493,	10.083174,	0},
-	{-0.263362,	0.204704,	10.103524,	0},
-	{-0.253785,	0.198719,	10.095144,	0},
-	{-0.252588,	0.209493,	10.103524,	0},
-	{-0.260968,	0.205901,	10.098736,	0},
-	{-0.259771,	0.205901,	10.083174,	0},
-	{-0.266953,	0.216675,	10.090356,	0},
-	{-0.265756,	0.207098,	10.101130,	0},
-	{-0.262165,	0.204704,	10.111904,	0},
-	{-0.248997,	0.199916,	10.101130,	0},
-	{-0.263362,	0.207098,	10.096342,	0},
-	{-0.281319,	0.227449,	10.108313,	0},
-	{-0.259771,	0.219069,	10.087962,	0},
-	{-0.258574,	0.214281,	10.079582,	0},
-	{-0.268150,	0.204704,	10.108313,	0},
-	{-0.277727,	0.204704,	10.114298,	0},
-	{-0.257377,	0.208295,	10.115496,	0},
-	{-0.260968,	0.222661,	10.104721,	0},
-	{-0.265756,	0.213084,	10.102327,	0},
-	{-0.256179,	0.210690,	10.099933,	0},
-	{-0.253785,	0.203507,	10.109509,	0},
-	{-0.270545,	0.201113,	10.103524,	0},
-	{-0.259771,	0.209493,	10.115496,	0},
-	{-0.264559,	0.207098,	10.103524,	0},
-	{-0.263362,	0.202310,	10.105919,	0},
-	{-0.260968,	0.220266,	10.110707,	0},
-	{-0.257377,	0.216675,	10.110707,	0},
-	{-0.259771,	0.195127,	10.093947,	0},
-	{-0.271742,	0.209493,	10.104721,	0},
-	{-0.257377,	0.223858,	10.108313,	0},
-	{-0.265756,	0.205901,	10.101130,	0},
-	{-0.270545,	0.196324,	10.101130,	0},
-	{-0.254982,	0.202310,	10.115496,	0},
-	{-0.248997,	0.214281,	10.116693,	0},
-	{-0.268150,	0.207098,	10.111904,	0},
-	{-0.263362,	0.204704,	10.091554,	0},
-	{-0.270545,	0.210690,	10.091554,	0},
-	{-0.268150,	0.215478,	10.102327,	0},
-	{-0.264559,	0.223858,	10.096342,	0},
-	{-0.262165,	0.203507,	10.099933,	0},
-	{-0.259771,	0.203507,	10.103524,	0},
-	{-0.269348,	0.204704,	10.119086,	0},
-	{-0.265756,	0.202310,	10.091554,	0},
-	{-0.260968,	0.201113,	10.092751,	0},
-	{-0.260968,	0.210690,	10.092751,	0},
-	{-0.266953,	0.205901,	10.109509,	0},
-	{-0.269348,	0.203507,	10.105919,	0},
-	{-0.264559,	0.193930,	10.114298,	0},
-	{-0.263362,	0.216675,	10.093947,	0},
-	{-0.256179,	0.208295,	10.095144,	0},
-	{-0.271742,	0.203507,	10.103524,	0},
-	{-0.259771,	0.208295,	10.089159,	0},
-	{-0.257377,	0.220266,	10.108313,	0},
-	{-0.266953,	0.207098,	10.101130,	0},
-	{-0.268150,	0.198719,	10.117889,	0},
-	{-0.258574,	0.204704,	10.091554,	0},
-	{-0.266953,	0.201113,	10.104721,	0},
-	{-0.265756,	0.205901,	10.091554,	0},
-	{-0.277727,	0.203507,	10.102327,	0},
-	{-0.266953,	0.204704,	10.093947,	0},
-	{-0.265756,	0.215478,	10.107116,	0},
-	{-0.254982,	0.215478,	10.110707,	0},
-	{-0.269348,	0.217872,	10.095144,	0},
-	{-0.265756,	0.229843,	10.109509,	0},
-	{-0.260968,	0.226252,	10.098736,	0},
-	{-0.253785,	0.208295,	10.095144,	0},
-	{-0.253785,	0.211887,	10.085567,	0},
-	{-0.268150,	0.214281,	10.109509,	0},
-	{-0.258574,	0.201113,	10.107116,	0},
-	{-0.265756,	0.211887,	10.103524,	0},
-	{-0.256179,	0.215478,	10.093947,	0},
-	{-0.263362,	0.204704,	10.107116,	0},
-	{-0.260968,	0.214281,	10.098736,	0},
-	{-0.259771,	0.213084,	10.110707,	0},
-	{-0.276530,	0.215478,	10.095144,	0},
-	{-0.263362,	0.211887,	10.084371,	0},
-	{-0.245406,	0.217872,	10.110707,	0},
-	{-0.251391,	0.209493,	10.105919,	0},
-	{-0.269348,	0.205901,	10.093947,	0},
-	{-0.271742,	0.201113,	10.099933,	0},
-	{-0.270545,	0.228646,	10.099933,	0},
-	{-0.262165,	0.217872,	10.096342,	0},
-	{-0.259771,	0.209493,	10.099933,	0},
-	{-0.260968,	0.210690,	10.105919,	0},
-	{-0.252588,	0.203507,	10.099933,	0},
-	{-0.263362,	0.197522,	10.095144,	0},
-	{-0.271742,	0.213084,	10.101130,	0},
-	{-0.268150,	0.196324,	10.110707,	0},
-	{-0.248997,	0.213084,	10.108313,	0},
-	{-0.254982,	0.215478,	10.095144,	0},
-	{-0.260968,	0.208295,	10.107116,	0},
-	{-0.259771,	0.219069,	10.108313,	0},
-	{-0.266953,	0.214281,	10.098736,	0},
-	{-0.269348,	0.202310,	10.090356,	0},
-	{-0.258574,	0.204704,	10.113101,	0},
-	{-0.263362,	0.226252,	10.086765,	0},
-	{-0.264559,	0.204704,	10.096342,	0},
-	{-0.271742,	0.219069,	10.096342,	0},
-	{-0.252588,	0.210690,	10.104721,	0},
-	{-0.258574,	0.211887,	10.113101,	0},
-	{-0.264559,	0.210690,	10.104721,	0},
-	{-0.269348,	0.214281,	10.103524,	0},
-	{-0.253785,	0.211887,	10.093947,	0},
-	{-0.256179,	0.223858,	10.110707,	0},
-	{-0.274136,	0.207098,	10.098736,	0},
-	{-0.274136,	0.207098,	10.092751,	0},
-	{-0.254982,	0.210690,	10.091554,	0},
-	{-0.257377,	0.204704,	10.098736,	0},
-	{-0.257377,	0.209493,	10.108313,	0},
-	{-0.257377,	0.211887,	10.095144,	0},
-	{-0.259771,	0.199916,	10.095144,	0},
-	{-0.257377,	0.214281,	10.101130,	0},
-	{-0.270545,	0.217872,	10.103524,	0},
-	{-0.281319,	0.204704,	10.104721,	0},
-	{-0.271742,	0.208295,	10.103524,	0},
-	{-0.258574,	0.211887,	10.104721,	0},
-	{-0.264559,	0.204704,	10.126269,	0},
-	{-0.262165,	0.201113,	10.101130,	0},
-	{-0.258574,	0.219069,	10.096342,	0},
-	{-0.263362,	0.211887,	10.107116,	0},
-	{-0.265756,	0.203507,	10.091554,	0},
-	{-0.264559,	0.205901,	10.107116,	0},
-	{-0.256179,	0.214281,	10.095144,	0},
-	{-0.263362,	0.202310,	10.097539,	0},
-	{-0.271742,	0.207098,	10.104721,	0},
-	{-0.272939,	0.210690,	10.101130,	0},
-	{-0.262165,	0.205901,	10.096342,	0},
-	{-0.260968,	0.209493,	10.107116,	0},
-	{-0.269348,	0.217872,	10.093947,	0},
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+	{ 5.475535, 0.949300, 8.026556, 0 },
+	{ 5.463564, 0.999579, 8.031344, 0 },
+	{ 5.469550, 0.994790, 7.918817, 0 },
+	{ 5.504266, 0.974439, 7.881707, 0 },
+	{ 5.546165, 0.991199, 7.955927, 0 },
+	{ 5.553347, 0.997184, 8.128309, 0 },
+	{ 5.567712, 1.010352, 8.230062, 0 },
+	{ 5.553347, 1.048660, 8.279144, 0 },
+	{ 5.578486, 1.033097, 8.268370, 0 },
+	{ 5.571303, 1.016338, 8.101973, 0 },
+	{ 5.543770, 0.985213, 7.933182, 0 },
+	{ 5.550953, 0.909796, 7.971489, 0 },
+	{ 5.547361, 0.855927, 7.951138, 0 },
+	{ 5.540179, 0.840364, 7.978672, 0 },
+	{ 5.523419, 0.848744, 8.152251, 0 },
+	{ 5.491098, 0.853532, 8.298298, 0 },
+	{ 5.420469, 0.901416, 8.333014, 0 },
+	{ 5.403709, 0.937329, 8.419205, 0 },
+	{ 5.440820, 0.964863, 8.601164, 0 },
+	{ 5.465959, 0.991199, 8.426387, 0 },
+	{ 5.457579, 1.051054, 8.109156, 0 },
+	{ 5.437228, 1.104923, 7.977475, 0 },
+	{ 5.428849, 1.102529, 8.027753, 0 },
+	{ 5.433637, 1.090558, 8.195347, 0 },
+	{ 5.432440, 1.100135, 8.276750, 0 },
+	{ 5.461170, 1.134851, 8.309072, 0 },
+	{ 5.511448, 1.119289, 8.292312, 0 },
+	{ 5.540179, 1.089361, 8.316254, 0 },
+	{ 5.518631, 1.103726, 8.358152, 0 },
+	{ 5.528208, 1.112106, 8.343787, 0 },
+	{ 5.527011, 1.094149, 8.257596, 0 },
+	{ 5.495886, 1.116894, 8.154645, 0 },
+	{ 5.510252, 1.092952, 8.208515, 0 },
+	{ 5.538982, 1.058236, 8.158237, 0 },
+	{ 5.511448, 1.088164, 7.948744, 0 },
+	{ 5.515040, 1.084573, 7.852976, 0 },
+	{ 5.507857, 1.104923, 7.959518, 0 },
+	{ 5.468353, 1.138442, 8.188165, 0 },
+	{ 5.468353, 1.148019, 8.327028, 0 },
+	{ 5.481521, 1.133654, 8.289918, 0 },
+	{ 5.511448, 1.120486, 8.226472, 0 },
+	{ 5.530602, 1.086967, 8.198938, 0 },
+	{ 5.529405, 1.065419, 8.166616, 0 },
+	{ 5.469550, 1.060631, 8.221684, 0 },
+	{ 5.440820, 1.053448, 8.240837, 0 },
+	{ 5.396527, 1.053448, 8.213304, 0 },
+	{ 5.386950, 1.055842, 8.234851, 0 },
+	{ 5.421666, 1.046265, 8.246822, 0 },
+	{ 5.431243, 1.029506, 8.155843, 0 },
+	{ 5.298365, 1.292868, 5.756854, 0 },
+	{ 5.191823, 1.255758, 8.088805, 0 },
+	{ 5.204991, 1.169567, 10.260345, 0 }
 };
 
 const size_t kBodyDetectOffOnTestDataLength =
 	ARRAY_SIZE(kBodyDetectOffOnTestData);
 
 const struct body_detect_test_data kBodyDetectOnOffTestData[] = {
-	{-6.536166,	0.264559,	7.560884,	0},
-	{-6.253651,	0.108936,	8.167813,	0},
-	{-5.890929,	-0.029928,	8.061272,	0},
-	{-5.833468,	-0.045490,	8.250414,	0},
-	{-5.932828,	0.038307,	8.573630,	0},
-	{-5.995077,	0.104148,	8.634683,	0},
-	{-6.080071,	0.181959,	8.317451,	0},
-	{-6.069297,	0.177171,	8.151054,	0},
-	{-5.978318,	0.113724,	8.407233,	0},
-	{-5.895718,	0.033519,	8.592784,	0},
-	{-5.828680,	-0.022745,	8.299495,	0},
-	{-5.768825,	-0.070629,	7.958321,	0},
-	{-5.770022,	-0.089783,	8.028950,	0},
-	{-5.832272,	-0.074220,	8.360547,	0},
-	{-5.880156,	-0.067038,	8.488636,	0},
-	{-5.987895,	-0.017957,	8.342590,	0},
-	{-6.148306,	0.014365,	8.317451,	0},
-	{-6.337448,	0.102951,	8.492228,	0},
-	{-6.411668,	0.148440,	8.571237,	0},
-	{-6.341039,	0.099359,	8.250414,	0},
-	{-6.232103,	0.067038,	7.899663,	0},
-	{-6.172248,	0.100556,	8.152251,	0},
-	{-6.095634,	0.111330,	8.632288,	0},
-	{-6.033384,	0.126893,	8.614332,	0},
-	{-5.936419,	0.131681,	8.136689,	0},
-	{-5.931631,	0.205901,	7.739252,	0},
-	{-5.986697,	0.271742,	7.870933,	0},
-	{-6.040567,	0.250194,	8.099579,	0},
-	{-6.077677,	0.244208,	8.191755,	0},
-	{-6.071692,	0.277727,	8.146266,	0},
-	{-5.953178,	0.292092,	8.025358,	0},
-	{-5.847834,	0.330400,	7.942759,	0},
-	{-5.776008,	0.392649,	8.036133,	0},
-	{-5.680240,	0.417788,	7.892480,	0},
-	{-5.617990,	0.458489,	7.609965,	0},
-	{-5.550953,	0.496797,	7.418429,	0},
-	{-5.301956,	0.369904,	8.050498,	0},
-	{-5.276817,	0.290895,	9.167392,	0},
-	{-5.890929,	0.215478,	9.044091,	0},
-	{-6.495465,	0.108936,	9.111129,	0},
-	{-6.545743,	-0.049081,	9.390053,	0},
-	{-5.966347,	-0.161609,	9.362519,	0},
-	{-5.325898,	-0.117316,	8.969871,	0},
-	{-5.263649,	0.105345,	8.404840,	0},
-	{-5.620385,	0.336385,	8.085214,	0},
-	{-5.886141,	0.472855,	8.037330,	0},
-	{-5.704182,	0.427365,	8.032541,	0},
-	{-5.359417,	0.301669,	7.813472,	0},
-	{-5.331883,	0.329203,	7.632710,	0},
-	{-5.483915,	0.433350,	7.621936,	0},
-	{-5.862199,	0.703895,	8.079228,	0},
-	{-5.808330,	0.616507,	9.142253,	0},
-	{-5.513843,	0.481234,	9.751576,	0},
-	{-5.365402,	0.470460,	9.706087,	0},
-	{-5.378571,	0.440533,	9.333789,	0},
-	{-5.637144,	0.565031,	8.905227,	0},
-	{-5.776008,	0.560243,	8.019373,	0},
-	{-5.779599,	0.676362,	7.132322,	0},
-	{-5.549756,	0.760159,	7.116760,	0},
-	{-5.303153,	0.730231,	7.817063,	0},
-	{-5.206188,	0.831985,	8.506593,	0},
-	{-5.151122,	0.725443,	8.941140,	0},
-	{-5.292379,	0.556652,	9.176969,	0},
-	{-5.622779,	0.563834,	9.362519,	0},
-	{-5.481521,	0.433350,	9.410403,	0},
-	{-5.045777,	-0.074220,	9.109931,	0},
-	{-5.035003,	-0.328005,	8.900438,	0},
-	{-5.307941,	-0.389058,	9.000996,	0},
-	{-5.561727,	-0.269348,	9.169786,	0},
-	{-5.603625,	0.213084,	9.216474,	0},
-	{-5.357023,	0.697909,	9.339774,	0},
-	{-5.081690,	0.764947,	9.429557,	0},
-	{-5.063733,	0.520739,	9.349351,	0},
-	{-5.212173,	0.463278,	9.210487,	0},
-	{-5.079296,	0.622492,	9.057259,	0},
-	{-4.827904,	0.758961,	8.755589,	0},
-	{-4.689041,	0.723048,	8.749604,	0},
-	{-4.681858,	0.731428,	9.129085,	0},
-	{-4.598061,	0.723048,	9.536098,	0},
-	{-4.378992,	0.730231,	9.668977,	0},
-	{-4.214989,	0.672770,	9.102749,	0},
-	{-4.241325,	0.641646,	8.643063,	0},
-	{-4.289209,	0.708683,	8.941140,	0},
-	{-4.304772,	0.984016,	9.394841,	0},
-	{-4.106053,	0.980425,	9.239218,	0},
-	{-3.926488,	0.615309,	8.754393,	0},
-	{-4.012679,	0.414197,	8.646653,	0},
-	{-4.191047,	0.730231,	9.080004,	0},
-	{-4.211398,	1.057039,	9.763548,	0},
-	{-4.055775,	0.944512,	9.933537,	0},
-	{-3.976766,	0.493205,	9.303862,	0},
-	{-4.319137,	0.397437,	8.835795,	0},
-	{-4.368218,	0.577002,	9.014163,	0},
-	{-4.213792,	0.700303,	9.281116,	0},
-	{-4.164711,	0.563834,	9.527719,	0},
-	{-4.132390,	0.458489,	9.472652,	0},
-	{-4.106053,	0.392649,	9.238021,	0},
-	{-4.090491,	0.524330,	9.093172,	0},
-	{-4.052184,	0.738611,	9.153027,	0},
-	{-4.015073,	0.524330,	9.047682,	0},
-	{-4.149149,	0.454898,	8.930367,	0},
-	{-4.250902,	0.724246,	9.131479,	0},
-	{-4.231749,	0.701501,	9.166195,	0},
-	{-4.356247,	0.757764,	9.208094,	0},
-	{-4.443635,	0.785298,	9.235627,	0},
-	{-4.355050,	0.804451,	9.149436,	0},
-	{-4.307166,	0.567425,	9.187743,	0},
-	{-4.550177,	0.476446,	9.249992,	0},
-	{-4.790794,	0.457292,	9.175772,	0},
-	{-4.935644,	0.417788,	9.200911,	0},
-	{-4.940432,	0.588973,	9.419980,	0},
-	{-4.709392,	0.357933,	9.624684,	0},
-	{-4.763261,	0.093374,	9.773125,	0},
-	{-5.021835,	0.171185,	9.756365,	0},
-	{-5.087675,	0.294487,	9.680948,	0},
-	{-4.916490,	0.357933,	9.610319,	0},
-	{-4.729742,	0.360327,	9.296679,	0},
-	{-4.635171,	0.266953,	8.780728,	0},
-	{-4.843467,	0.410605,	8.383291,	0},
-	{-4.898533,	0.500388,	8.177390,	0},
-	{-4.692632,	0.489614,	8.313860,	0},
-	{-4.566936,	0.451307,	8.595179,	0},
-	{-4.624397,	0.457292,	8.774743,	0},
-	{-4.781218,	0.441730,	8.777138,	0},
-	{-4.916490,	0.410605,	8.816642,	0},
-	{-5.014652,	0.482431,	8.795094,	0},
-	{-4.830298,	0.306458,	8.991419,	0},
-	{-5.154713,	0.448913,	8.974659,	0},
-	{-5.114011,	0.424971,	8.789108,	0},
-	{-4.894942,	0.238223,	8.692143,	0},
-	{-4.979936,	0.184353,	8.980644,	0},
-	{-5.267240,	0.381875,	9.326607,	0},
-	{-5.289985,	0.413000,	9.498989,	0},
-	{-5.128376,	0.320823,	9.273934,	0},
-	{-4.978739,	0.312443,	8.930367,	0},
-	{-5.054156,	0.391452,	8.816642,	0},
-	{-5.224144,	0.409408,	8.898045,	0},
-	{-5.287591,	0.392649,	8.862131,	0},
-	{-5.182246,	0.426168,	8.808262,	0},
-	{-5.039791,	0.471657,	8.797488,	0},
-	{-4.969162,	0.490811,	8.793897,	0},
-	{-5.032609,	0.511162,	8.804670,	0},
-	{-5.021835,	0.465672,	8.822627,	0},
-	{-4.967965,	0.496797,	8.820233,	0},
-	{-4.969162,	0.571017,	8.796291,	0},
-	{-4.904519,	0.560243,	8.785517,	0},
-	{-4.750093,	0.547075,	8.775940,	0},
-	{-4.687844,	0.500388,	8.554477,	0},
-	{-4.741713,	0.487220,	8.224077,	0},
-	{-4.880577,	0.569820,	8.147463,	0},
-	{-4.959586,	0.610521,	8.506593,	0},
-	{-4.977542,	0.555454,	8.856146,	0},
-	{-4.910504,	0.424971,	8.870511,	0},
-	{-4.947615,	0.316034,	8.845372,	0},
-	{-5.177458,	0.336385,	9.156618,	0},
-	{-5.345052,	0.371101,	9.455894,	0},
-	{-5.370191,	0.402226,	9.381673,	0},
-	{-5.357023,	0.372298,	9.232036,	0},
-	{-5.309139,	0.289698,	9.148238,	0},
-	{-5.236115,	0.247800,	9.085989,	0},
-	{-5.159501,	0.211887,	9.010572,	0},
-	{-5.081690,	0.173579,	8.878891,	0},
-	{-5.049368,	0.208295,	8.710100,	0},
-	{-5.026623,	0.229843,	8.664610,	0},
-	{-5.032609,	0.237026,	8.772349,	0},
-	{-4.967965,	0.233435,	8.868117,	0},
-	{-4.844664,	0.164003,	8.799882,	0},
-	{-4.906913,	0.155623,	8.500607,	0},
-	{-5.141545,	0.264559,	8.359349,	0},
-	{-5.264846,	0.310049,	8.640668,	0},
-	{-5.348643,	0.306458,	8.961491,	0},
-	{-5.366600,	0.301669,	8.968674,	0},
-	{-5.404907,	0.298078,	8.802277,	0},
-	{-5.386950,	0.259771,	8.801080,	0},
-	{-5.335475,	0.208295,	8.759181,	0},
-	{-5.300759,	0.174777,	8.723268,	0},
-	{-5.237313,	0.147243,	8.762773,	0},
-	{-5.303153,	0.185551,	8.772349,	0},
-	{-5.394133,	0.204704,	8.888468,	0},
-	{-5.383359,	0.167594,	8.965082,	0},
-	{-5.257663,	0.110133,	8.893256,	0},
-	{-5.116405,	0.039504,	8.738831,	0},
-	{-5.194217,	0.044293,	8.644259,	0},
-	{-5.336672,	0.111330,	8.772349,	0},
-	{-5.389344,	0.132878,	8.972264,	0},
-	{-5.400118,	0.136469,	8.959097,	0},
-	{-5.455185,	0.185551,	8.850161,	0},
-	{-5.519828,	0.210690,	8.804670,	0},
-	{-5.555741,	0.210690,	8.898045,	0},
-	{-5.507857,	0.222661,	8.835795,	0},
-	{-5.402513,	0.205901,	8.598769,	0},
-	{-5.368994,	0.257377,	8.353364,	0},
-	{-5.437228,	0.366313,	8.394066,	0},
-	{-5.401315,	0.345962,	8.656230,	0},
-	{-5.341460,	0.350750,	8.723268,	0},
-	{-5.272028,	0.362721,	8.585602,	0},
-	{-5.282803,	0.387860,	8.337802,	0},
-	{-5.285197,	0.420182,	8.268370,	0},
-	{-5.250481,	0.415394,	8.337802,	0},
-	{-5.185837,	0.379481,	8.416810,	0},
-	{-5.161895,	0.356736,	8.468286,	0},
-	{-5.203794,	0.344765,	8.577222,	0},
-	{-5.272028,	0.306458,	8.719677,	0},
-	{-5.315124,	0.271742,	8.868117,	0},
-	{-5.337869,	0.296881,	8.939943,	0},
-	{-5.376176,	0.299275,	8.894453,	0},
-	{-5.442017,	0.318429,	8.793897,	0},
-	{-5.452791,	0.331597,	8.714889,	0},
-	{-5.412089,	0.289698,	8.700523,	0},
-	{-5.406104,	0.251391,	8.773546,	0},
-	{-5.368994,	0.252588,	8.866920,	0},
-	{-5.323504,	0.240617,	8.942337,	0},
-	{-5.333081,	0.231040,	9.015361,	0},
-	{-5.377373,	0.231040,	8.980644,	0},
-	{-5.450397,	0.292092,	8.865723,	0},
-	{-5.483915,	0.336385,	8.750801,	0},
-	{-5.474339,	0.355539,	8.653836,	0},
-	{-5.404907,	0.342371,	8.593981,	0},
-	{-5.243298,	0.234632,	8.598769,	0},
-	{-5.164289,	0.198719,	8.635880,	0},
-	{-5.214568,	0.248997,	8.646653,	0},
-	{-5.316321,	0.288501,	8.589192,	0},
-	{-5.452791,	0.343568,	8.579616,	0},
-	{-5.509054,	0.366313,	8.670595,	0},
-	{-5.474339,	0.319626,	8.686158,	0},
-	{-5.384556,	0.275333,	8.689749,	0},
-	{-5.365402,	0.268150,	8.750801,	0},
-	{-5.437228,	0.357933,	8.748407,	0},
-	{-5.470747,	0.402226,	8.730451,	0},
-	{-5.386950,	0.362721,	8.672990,	0},
-	{-5.339066,	0.363918,	8.700523,	0},
-	{-5.295970,	0.398634,	8.793897,	0},
-	{-5.307941,	0.413000,	8.899241,	0},
-	{-5.295970,	0.392649,	8.924380,	0},
-	{-5.287591,	0.405817,	8.936352,	0},
-	{-5.269634,	0.417788,	8.896848,	0},
-	{-5.342658,	0.471657,	8.640668,	0},
-	{-5.464762,	0.557849,	8.434767,	0},
-	{-5.467156,	0.575805,	8.456315,	0},
-	{-5.443214,	0.561440,	8.497016,	0},
-	{-5.440820,	0.574608,	8.524549,	0},
-	{-5.438426,	0.598550,	8.480257,	0},
-	{-5.348643,	0.553060,	8.530535,	0},
-	{-5.238510,	0.509965,	8.638274,	0},
-	{-5.155910,	0.445321,	8.657428,	0},
-	{-5.111617,	0.395043,	8.583207,	0},
-	{-5.115209,	0.365116,	8.610741,	0},
-	{-5.176260,	0.344765,	8.625106,	0},
-	{-5.254072,	0.373495,	8.711297,	0},
-	{-5.267240,	0.379481,	8.808262,	0},
-	{-5.238510,	0.329203,	8.795094,	0},
-	{-5.266043,	0.282516,	8.694537,	0},
-	{-5.410892,	0.308852,	8.599967,	0},
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+	{ -0.235829, 0.087388, 10.125072, 0 },
+	{ -0.241814, 0.070629, 10.105919, 0 },
+	{ -0.251391, 0.081403, 10.140635, 0 },
+	{ -0.235829, 0.074220, 10.117889, 0 },
+	{ -0.244208, 0.076614, 10.134649, 0 },
+	{ -0.248997, 0.074220, 10.108313, 0 },
+	{ -0.240617, 0.089783, 10.123875, 0 },
+	{ -0.254982, 0.074220, 10.146620, 0 },
+	{ -0.252588, 0.079009, 10.120284, 0 },
+	{ -0.246603, 0.087388, 10.133451, 0 },
+	{ -0.246603, 0.074220, 10.116693, 0 },
+	{ -0.235829, 0.074220, 10.138240, 0 },
+	{ -0.239420, 0.076614, 10.111904, 0 },
+	{ -0.253785, 0.065841, 10.132255, 0 },
+	{ -0.246603, 0.074220, 10.117889, 0 },
+	{ -0.251391, 0.084994, 10.121481, 0 },
+	{ -0.260968, 0.087388, 10.131058, 0 },
+	{ -0.246603, 0.084994, 10.123875, 0 },
+	{ -0.247800, 0.087388, 10.119086, 0 },
+	{ -0.238223, 0.070629, 10.125072, 0 },
+	{ -0.248997, 0.075417, 10.137043, 0 },
+	{ -0.240617, 0.081403, 10.126269, 0 },
+	{ -0.225055, 0.075417, 10.117889, 0 },
+	{ -0.245406, 0.061052, 10.099933, 0 },
+	{ -0.229843, 0.071826, 10.133451, 0 },
+	{ -0.239420, 0.088585, 10.158591, 0 },
+	{ -0.251391, 0.079009, 10.111904, 0 },
+	{ -0.234632, 0.070629, 10.151408, 0 },
+	{ -0.232237, 0.068235, 10.127466, 0 },
+	{ -0.238223, 0.083797, 10.125072, 0 },
+	{ -0.240617, 0.083797, 10.104721, 0 },
+	{ -0.234632, 0.084994, 10.127466, 0 },
+	{ -0.243011, 0.068235, 10.098736, 0 },
+	{ -0.251391, 0.075417, 10.146620, 0 },
+	{ -0.257377, 0.082600, 10.117889, 0 },
+	{ -0.234632, 0.076614, 10.119086, 0 },
+	{ -0.244208, 0.080206, 10.132255, 0 },
+	{ -0.232237, 0.080206, 10.139438, 0 },
+	{ -0.235829, 0.083797, 10.134649, 0 },
+	{ -0.240617, 0.083797, 10.107116, 0 },
+	{ -0.239420, 0.087388, 10.134649, 0 },
+	{ -0.248997, 0.074220, 10.125072, 0 },
+	{ -0.247800, 0.064643, 10.150211, 0 },
+	{ -0.243011, 0.076614, 10.111904, 0 },
+	{ -0.247800, 0.069432, 10.139438, 0 },
+	{ -0.240617, 0.076614, 10.132255, 0 },
+	{ -0.240617, 0.076614, 10.129861, 0 },
+	{ -0.235829, 0.065841, 10.105919, 0 },
+	{ -0.252588, 0.080206, 10.113101, 0 },
+	{ -0.251391, 0.077812, 10.149014, 0 },
+	{ -0.241814, 0.082600, 10.056837, 0 },
+	{ -0.243011, 0.084994, 10.199292, 0 },
+	{ -0.253785, 0.077812, 10.098736, 0 },
+	{ -0.229843, 0.063446, 10.103524, 0 },
+	{ -0.250194, 0.069432, 10.183730, 0 },
+	{ -0.240617, 0.086191, 10.067612, 0 },
+	{ -0.246603, 0.070629, 10.201687, 0 },
+	{ -0.263362, 0.067038, 10.071202, 0 },
+	{ -0.245406, 0.059855, 10.166970, 0 },
+	{ -0.239420, 0.065841, 10.092751, 0 },
+	{ -0.238223, 0.068235, 10.139438, 0 },
+	{ -0.243011, 0.074220, 10.116693, 0 },
+	{ -0.240617, 0.081403, 10.122678, 0 },
+	{ -0.251391, 0.067038, 10.119086, 0 },
+	{ -0.240617, 0.075417, 10.113101, 0 },
+	{ -0.250194, 0.059855, 10.137043, 0 },
+	{ -0.244208, 0.062249, 10.129861, 0 },
+	{ -0.229843, 0.083797, 10.117889, 0 },
+	{ -0.246603, 0.076614, 10.123875, 0 },
+	{ -0.234632, 0.087388, 10.140635, 0 },
+	{ -0.254982, 0.079009, 10.119086, 0 },
+	{ -0.237026, 0.074220, 10.157393, 0 },
+	{ -0.247800, 0.088585, 10.115496, 0 },
+	{ -0.251391, 0.087388, 10.144226, 0 },
+	{ -0.238223, 0.071826, 10.116693, 0 },
+	{ -0.233435, 0.069432, 10.137043, 0 },
+	{ -0.231040, 0.081403, 10.119086, 0 },
+	{ -0.244208, 0.079009, 10.116693, 0 },
+	{ -0.245406, 0.073023, 10.147817, 0 },
+	{ -0.250194, 0.071826, 10.113101, 0 },
+	{ -0.238223, 0.077812, 10.135846, 0 },
+	{ -0.240617, 0.077812, 10.105919, 0 },
+	{ -0.239420, 0.076614, 10.145423, 0 },
+	{ -0.232237, 0.070629, 10.102327, 0 },
+	{ -0.241814, 0.080206, 10.119086, 0 },
+	{ -0.237026, 0.068235, 10.111904, 0 },
+	{ -0.260968, 0.082600, 10.137043, 0 },
+	{ -0.240617, 0.089783, 10.139438, 0 },
+	{ -0.238223, 0.077812, 10.128663, 0 },
+	{ -0.240617, 0.075417, 10.138240, 0 },
+	{ -0.247800, 0.075417, 10.129861, 0 },
+	{ -0.251391, 0.075417, 10.143028, 0 },
+	{ -0.254982, 0.076614, 10.128663, 0 },
+	{ -0.251391, 0.070629, 10.157393, 0 },
+	{ -0.253785, 0.086191, 10.134649, 0 },
+	{ -0.248997, 0.079009, 10.126269, 0 },
+	{ -0.244208, 0.087388, 10.117889, 0 },
+	{ -0.254982, 0.080206, 10.125072, 0 },
+	{ -0.244208, 0.071826, 10.122678, 0 },
+	{ -0.248997, 0.087388, 10.111904, 0 },
+	{ -0.246603, 0.075417, 10.133451, 0 },
+	{ -0.252588, 0.071826, 10.099933, 0 },
+	{ -0.245406, 0.082600, 10.132255, 0 },
+	{ -0.246603, 0.086191, 10.129861, 0 },
+	{ -0.227449, 0.067038, 10.151408, 0 },
+	{ -0.235829, 0.079009, 10.109509, 0 },
+	{ -0.239420, 0.080206, 10.137043, 0 },
+	{ -0.241814, 0.084994, 10.121481, 0 },
+	{ -0.251391, 0.081403, 10.116693, 0 },
+	{ -0.260968, 0.073023, 10.141831, 0 },
+	{ -0.245406, 0.073023, 10.122678, 0 },
+	{ -0.252588, 0.083797, 10.139438, 0 },
+	{ -0.243011, 0.080206, 10.122678, 0 },
+	{ -0.239420, 0.077812, 10.138240, 0 },
+	{ -0.241814, 0.068235, 10.113101, 0 },
+	{ -0.244208, 0.074220, 10.133451, 0 },
+	{ -0.257377, 0.079009, 10.128663, 0 },
+	{ -0.253785, 0.074220, 10.125072, 0 },
+	{ -0.238223, 0.062249, 10.132255, 0 },
+	{ -0.243011, 0.068235, 10.119086, 0 },
+	{ -0.240617, 0.074220, 10.132255, 0 },
+	{ -0.272939, 0.076614, 10.116693, 0 },
+	{ -0.234632, 0.075417, 10.138240, 0 },
+	{ -0.241814, 0.073023, 10.085567, 0 },
+	{ -0.246603, 0.075417, 10.163380, 0 },
+	{ -0.248997, 0.058658, 10.093947, 0 },
+	{ -0.243011, 0.070629, 10.146620, 0 },
+	{ -0.238223, 0.074220, 10.110707, 0 },
+	{ -0.252588, 0.065841, 10.141831, 0 },
+	{ -0.229843, 0.074220, 10.137043, 0 },
+	{ -0.248997, 0.076614, 10.099933, 0 },
+	{ -0.229843, 0.081403, 10.157393, 0 },
+	{ -0.243011, 0.082600, 10.074794, 0 },
+	{ -0.250194, 0.071826, 10.164577, 0 },
+	{ -0.263362, 0.076614, 10.103524, 0 },
+	{ -0.260968, 0.094571, 10.138240, 0 },
+	{ -0.240617, 0.077812, 10.116693, 0 },
+	{ -0.239420, 0.081403, 10.109509, 0 },
+	{ -0.253785, 0.086191, 10.135846, 0 },
+	{ -0.247800, 0.076614, 10.093947, 0 },
+	{ -0.256179, 0.068235, 10.158591, 0 },
+	{ -0.253785, 0.079009, 10.090356, 0 },
+	{ -0.239420, 0.076614, 10.151408, 0 },
+	{ -0.244208, 0.082600, 10.115496, 0 },
+	{ -0.244208, 0.081403, 10.134649, 0 },
+	{ -0.254982, 0.088585, 10.122678, 0 },
+	{ -0.252588, 0.069432, 10.120284, 0 },
+	{ -0.247800, 0.077812, 10.137043, 0 },
+	{ -0.250194, 0.076614, 10.117889, 0 },
+	{ -0.238223, 0.077812, 10.121481, 0 },
+	{ -0.245406, 0.065841, 10.186124, 0 },
+	{ -0.233435, 0.065841, 10.046063, 0 },
+	{ -0.237026, 0.094571, 10.243585, 0 },
+	{ -0.231040, 0.093374, 10.014939, 0 },
+	{ -0.243011, 0.084994, 10.223234, 0 },
+	{ -0.256179, 0.064643, 9.987406, 0 },
+	{ -0.250194, 0.098162, 10.247176, 0 },
+	{ -0.229843, 0.073023, 9.891638, 0 },
+	{ -0.268150, 0.062249, 10.406390, 0 },
+	{ -0.247800, 0.073023, 9.883258, 0 },
+	{ -0.237026, 0.076614, 10.360901, 0 },
+	{ -0.247800, 0.081403, 9.975434, 0 },
+	{ -0.225055, 0.080206, 10.178942, 0 },
+	{ -0.263362, 0.071826, 10.163380, 0 },
+	{ -0.237026, 0.076614, 10.062823, 0 },
+	{ -0.265756, 0.075417, 10.214854, 0 },
+	{ -0.234632, 0.083797, 10.053246, 0 },
+	{ -0.254982, 0.071826, 10.210066, 0 },
+	{ -0.241814, 0.076614, 10.001771, 0 },
+	{ -0.221464, 0.117316, 10.239994, 0 },
+	{ -0.269348, 0.076614, 10.064020, 0 },
+	{ -0.220266, 0.092177, 10.166970, 0 },
+	{ -0.252588, 0.075417, 10.111904, 0 },
+	{ -0.232237, 0.068235, 10.122678, 0 },
+	{ -0.259771, 0.075417, 10.110707, 0 },
+	{ -0.246603, 0.095768, 10.137043, 0 },
+	{ -0.235829, 0.076614, 10.138240, 0 },
+	{ -0.256179, 0.071826, 10.102327, 0 },
+	{ -0.229843, 0.089783, 10.175350, 0 },
+	{ -0.260968, 0.082600, 10.089159, 0 },
+	{ -0.225055, 0.086191, 10.169365, 0 },
+	{ -0.262165, 0.087388, 10.103524, 0 },
+	{ -0.234632, 0.077812, 10.149014, 0 },
+	{ -0.241814, 0.070629, 10.079582, 0 },
+	{ -0.256179, 0.077812, 10.163380, 0 },
+	{ -0.226252, 0.068235, 10.096342, 0 },
+	{ -0.253785, 0.080206, 10.117889, 0 },
+	{ -0.244208, 0.077812, 10.163380, 0 },
+	{ -0.269348, 0.076614, 10.097539, 0 },
+	{ -0.238223, 0.069432, 10.169365, 0 },
+	{ -0.254982, 0.068235, 10.096342, 0 },
+	{ -0.231040, 0.061052, 10.159788, 0 },
+	{ -0.248997, 0.075417, 10.079582, 0 },
+	{ -0.258574, 0.071826, 10.162182, 0 },
+	{ -0.232237, 0.079009, 10.102327, 0 },
+	{ -0.256179, 0.100556, 10.138240, 0 },
+	{ -0.232237, 0.084994, 10.116693, 0 },
+	{ -0.235829, 0.080206, 10.110707, 0 },
+	{ -0.225055, 0.065841, 10.129861, 0 },
+	{ -0.217872, 0.082600, 10.090356, 0 },
+	{ -0.244208, 0.081403, 10.157393, 0 },
 };
 
 const size_t kBodyDetectOnOffTestDataLength =
diff --git a/test/body_detection_test_data.h b/test/body_detection_test_data.h
index 4c22c3236f..913701455b 100644
--- a/test/body_detection_test_data.h
+++ b/test/body_detection_test_data.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/build.mk b/test/build.mk
index fac9544ca4..9ab2cf0f7a 100644
--- a/test/build.mk
+++ b/test/build.mk
@@ -1,10 +1,18 @@
 # -*- makefile -*-
-# Copyright 2013 The Chromium OS Authors. All rights reserved.
+# Copyright 2013 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 # Device test binaries
-test-list-y ?= flash_write_protect pingpong timer_calib timer_dos timer_jump mutex utils utils_str
+test-list-y ?= flash_write_protect \
+	pingpong \
+	stdlib \
+	timer_calib \
+	timer_dos \
+	timer_jump \
+	mutex \
+	utils \
+	utils_str
 #disable: powerdemo
 
 # Emulator tests
@@ -25,6 +33,7 @@ test-list-host += cec
 test-list-host += charge_manager
 test-list-host += charge_manager_drp_charging
 test-list-host += charge_ramp
+test-list-host += chipset
 test-list-host += compile_time_macros
 test-list-host += console_edit
 test-list-host += crc
@@ -66,6 +75,7 @@ test-list-host += motion_lid
 test-list-host += motion_sense_fifo
 test-list-host += mutex
 test-list-host += newton_fit
+test-list-host += nvidia_gpu
 test-list-host += online_calibration
 test-list-host += online_calibration_spoof
 test-list-host += pingpong
@@ -82,6 +92,10 @@ test-list-host += sha256_unrolled
 test-list-host += shmalloc
 test-list-host += static_if
 test-list-host += static_if_error
+# TODO(b/237823627): When building for the host, we're linking against the
+# toolchain's C standard library, so these tests are actually testing the
+# toolchain's C standard library.
+test-list-host += stdlib
 test-list-host += system
 test-list-host += thermal
 test-list-host += timer_dos
@@ -157,10 +171,12 @@ cec-y=cec.o
 charge_manager-y=charge_manager.o fake_usbc.o
 charge_manager_drp_charging-y=charge_manager.o fake_usbc.o
 charge_ramp-y+=charge_ramp.o
+chipset-y+=chipset.o
 compile_time_macros-y=compile_time_macros.o
 console_edit-y=console_edit.o
 cortexm_fpu-y=cortexm_fpu.o
 crc-y=crc.o
+debug-y=debug.o
 entropy-y=entropy.o
 extpwr_gpio-y=extpwr_gpio.o
 fan-y=fan.o
@@ -191,6 +207,7 @@ motion_angle-y=motion_angle.o motion_angle_data_literals.o motion_common.o
 motion_angle_tablet-y=motion_angle_tablet.o motion_angle_data_literals_tablet.o motion_common.o
 motion_lid-y=motion_lid.o
 motion_sense_fifo-y=motion_sense_fifo.o
+nvidia_gpu-y=nvidia_gpu.o
 online_calibration-y=online_calibration.o
 online_calibration_spoof-y=online_calibration_spoof.o gyro_cal_init_for_test.o
 rgb_keyboard-y=rgb_keyboard.o
@@ -216,6 +233,7 @@ sha256-y=sha256.o
 sha256_unrolled-y=sha256.o
 shmalloc-y=shmalloc.o
 static_if-y=static_if.o
+stdlib-y=stdlib.o
 stm32f_rtc-y=stm32f_rtc.o
 stress-y=stress.o
 system-y=system.o
diff --git a/test/button.c b/test/button.c
index e457eaa786..c1acba7048 100644
--- a/test/button.c
+++ b/test/button.c
@@ -1,9 +1,9 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Test non-keyboard buttons.
-*
+ *
  * Using GPIOS and buttons[] defined in board/host/board.c
  * Volume down is active low with a debounce time of 30 mSec.
  * Volume up is active high with a debounce time of 60 mSec.
@@ -272,7 +272,7 @@ static void button_test_init(void)
 		button_state[i] = UNCHANGED;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/button.tasklist b/test/button.tasklist
index 5a8fb1bfbe..e2f8671c60 100644
--- a/test/button.tasklist
+++ b/test/button.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/cbi.c b/test/cbi.c
index 0ef2129377..ce01545644 100644
--- a/test/cbi.c
+++ b/test/cbi.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -129,7 +129,7 @@ DECLARE_EC_TEST(test_not_found)
 
 DECLARE_EC_TEST(test_too_large)
 {
-	uint8_t buf[CBI_IMAGE_SIZE-1];
+	uint8_t buf[CBI_IMAGE_SIZE - 1];
 	const int tag = 0xff;
 
 	/* Data too large */
@@ -162,12 +162,12 @@ DECLARE_EC_TEST(test_all_tags)
 	zassert_equal(cbi_set_board_info(CBI_TAG_SKU_ID, &d8, sizeof(d8)),
 		      EC_SUCCESS, NULL);
 	count++;
-	zassert_equal(cbi_set_board_info(CBI_TAG_DRAM_PART_NUM,
-					 string, sizeof(string)),
+	zassert_equal(cbi_set_board_info(CBI_TAG_DRAM_PART_NUM, string,
+					 sizeof(string)),
 		      EC_SUCCESS, NULL);
 	count++;
-	zassert_equal(cbi_set_board_info(CBI_TAG_OEM_NAME,
-					 string, sizeof(string)),
+	zassert_equal(cbi_set_board_info(CBI_TAG_OEM_NAME, string,
+					 sizeof(string)),
 		      EC_SUCCESS, NULL);
 	count++;
 	zassert_equal(cbi_set_board_info(CBI_TAG_MODEL_ID, &d8, sizeof(d8)),
@@ -176,8 +176,7 @@ DECLARE_EC_TEST(test_all_tags)
 	zassert_equal(cbi_set_board_info(CBI_TAG_FW_CONFIG, &d8, sizeof(d8)),
 		      EC_SUCCESS, NULL);
 	count++;
-	zassert_equal(cbi_set_board_info(CBI_TAG_PCB_SUPPLIER, &d8,
-					 sizeof(d8)),
+	zassert_equal(cbi_set_board_info(CBI_TAG_PCB_SUPPLIER, &d8, sizeof(d8)),
 		      EC_SUCCESS, NULL);
 	count++;
 	zassert_equal(cbi_set_board_info(CBI_TAG_SSFC, &d8, sizeof(d8)),
@@ -186,6 +185,10 @@ DECLARE_EC_TEST(test_all_tags)
 	zassert_equal(cbi_set_board_info(CBI_TAG_REWORK_ID, &d8, sizeof(d8)),
 		      EC_SUCCESS, NULL);
 	count++;
+	zassert_equal(cbi_set_board_info(CBI_TAG_FACTORY_CALIBRATION_DATA, &d8,
+					 sizeof(d8)),
+		      EC_SUCCESS, NULL);
+	count++;
 
 	/* Read out all */
 	zassert_equal(cbi_get_board_version(&d32), EC_SUCCESS, NULL);
@@ -220,6 +223,8 @@ DECLARE_EC_TEST(test_all_tags)
 	zassert_equal(d32, d8, "0x%x, 0x%x", d32, d8);
 	zassert_equal(cbi_get_ssfc(&d32), EC_SUCCESS, NULL);
 	zassert_equal(d32, d8, "0x%x, 0x%x", d32, d8);
+	zassert_equal(cbi_get_factory_calibration_data(&d32), EC_SUCCESS, NULL);
+	zassert_equal(d32, d8, "0x%x, 0x%x", d32, d8);
 	zassert_equal(cbi_get_rework_id(&d64), EC_SUCCESS, NULL);
 	/* This should be zassert_equal, but for EC test fmt is always "0x%x"
 	 * which will generate compilation error.
@@ -250,7 +255,7 @@ DECLARE_EC_TEST(test_bad_crc)
 	zassert_equal(cbi_set_board_info(tag, &d8, sizeof(d8)), EC_SUCCESS,
 		      NULL);
 	i2c_read8(I2C_PORT_EEPROM, I2C_ADDR_EEPROM_FLAGS,
-		   offsetof(struct cbi_header, crc), &crc);
+		  offsetof(struct cbi_header, crc), &crc);
 	i2c_write8(I2C_PORT_EEPROM, I2C_ADDR_EEPROM_FLAGS,
 		   offsetof(struct cbi_header, crc), ++crc);
 	cbi_invalidate_cache();
@@ -263,24 +268,21 @@ DECLARE_EC_TEST(test_bad_crc)
 
 TEST_SUITE(test_suite_cbi)
 {
-	ztest_test_suite(test_cbi,
-			 ztest_unit_test_setup_teardown(test_uint8, test_setup,
-							test_teardown),
-			 ztest_unit_test_setup_teardown(test_uint32, test_setup,
-							test_teardown),
-			 ztest_unit_test_setup_teardown(test_string, test_setup,
-							test_teardown),
-			 ztest_unit_test_setup_teardown(test_not_found,
-							test_setup,
-							test_teardown),
-			 ztest_unit_test_setup_teardown(test_too_large,
-							test_setup,
-							test_teardown),
-			 ztest_unit_test_setup_teardown(test_all_tags,
-							test_setup,
-							test_teardown),
-			 ztest_unit_test_setup_teardown(test_bad_crc,
-							test_setup,
-							test_teardown));
+	ztest_test_suite(
+		test_cbi,
+		ztest_unit_test_setup_teardown(test_uint8, test_setup,
+					       test_teardown),
+		ztest_unit_test_setup_teardown(test_uint32, test_setup,
+					       test_teardown),
+		ztest_unit_test_setup_teardown(test_string, test_setup,
+					       test_teardown),
+		ztest_unit_test_setup_teardown(test_not_found, test_setup,
+					       test_teardown),
+		ztest_unit_test_setup_teardown(test_too_large, test_setup,
+					       test_teardown),
+		ztest_unit_test_setup_teardown(test_all_tags, test_setup,
+					       test_teardown),
+		ztest_unit_test_setup_teardown(test_bad_crc, test_setup,
+					       test_teardown));
 	ztest_run_test_suite(test_cbi);
 }
diff --git a/test/cbi.tasklist b/test/cbi.tasklist
index 52c0d390ef..08d31e0102 100644
--- a/test/cbi.tasklist
+++ b/test/cbi.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/cbi_wp.c b/test/cbi_wp.c
index 7bdfa4b0c8..625447dcb3 100644
--- a/test/cbi_wp.c
+++ b/test/cbi_wp.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -49,8 +49,7 @@ DECLARE_EC_TEST(test_wp)
 TEST_SUITE(test_suite_cbi_wp)
 {
 	ztest_test_suite(test_cbi_wp,
-			 ztest_unit_test_setup_teardown(test_wp,
-							test_setup,
+			 ztest_unit_test_setup_teardown(test_wp, test_setup,
 							test_teardown));
 	ztest_run_test_suite(test_cbi_wp);
 }
diff --git a/test/cbi_wp.tasklist b/test/cbi_wp.tasklist
index e54ea001bd..cd866d90e1 100644
--- a/test/cbi_wp.tasklist
+++ b/test/cbi_wp.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/cec.c b/test/cec.c
index 9377e4fcd3..7718b7b705 100644
--- a/test/cec.c
+++ b/test/cec.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -18,7 +18,6 @@ struct overflow_msg {
 BUILD_ASSERT(offsetof(struct overflow_msg, overflow_detector) ==
 	     offsetof(struct cec_msg_transfer, buf) + MAX_CEC_MSG_LEN);
 
-
 struct overflow_queue {
 	struct cec_rx_queue queue;
 	uint8_t overflow_detector[CEC_RX_BUFFER_SIZE];
@@ -35,7 +34,7 @@ static int test_msg_overflow(void)
 	int i;
 
 	/* Overwrite the buffer by 1 byte */
-	for (i = 0; i < (MAX_CEC_MSG_LEN+1)*8; i++) {
+	for (i = 0; i < (MAX_CEC_MSG_LEN + 1) * 8; i++) {
 		cec_transfer_set_bit(&overflow_msg.transfer, 1);
 		cec_transfer_inc_bit(&overflow_msg.transfer);
 	}
@@ -60,8 +59,6 @@ static int test_msg_overflow(void)
 	return EC_SUCCESS;
 }
 
-
-
 static int verify_no_queue_overflow(void)
 {
 	int i;
@@ -73,11 +70,9 @@ static int verify_no_queue_overflow(void)
 	return EC_SUCCESS;
 }
 
-
 static void clear_queue(void)
 {
 	memset(queue, 0, sizeof(struct cec_rx_queue));
-
 }
 
 static int fill_queue(uint8_t *msg, int msg_size)
@@ -92,12 +87,12 @@ static int fill_queue(uint8_t *msg, int msg_size)
 	 */
 	clear_queue();
 
-	for (i = 0; i < (CEC_RX_BUFFER_SIZE - 1)/(msg_size + 1); i++)
+	for (i = 0; i < (CEC_RX_BUFFER_SIZE - 1) / (msg_size + 1); i++)
 		TEST_ASSERT(cec_rx_queue_push(queue, msg, msg_size) == 0);
 
 	/* Now the queue should be full */
 	TEST_ASSERT(cec_rx_queue_push(queue, msg, msg_size) ==
-							EC_ERROR_OVERFLOW);
+		    EC_ERROR_OVERFLOW);
 
 	/* Verify nothing was written outside of the queue */
 	TEST_ASSERT(verify_no_queue_overflow() == EC_SUCCESS);
@@ -119,7 +114,7 @@ static int test_queue_overflow(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	queue = &overflow_queue.queue;
 
diff --git a/test/cec.tasklist b/test/cec.tasklist
index e7634958a9..df71bfc0f9 100644
--- a/test/cec.tasklist
+++ b/test/cec.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/test/charge_manager.c b/test/charge_manager.c
index 2a64ca3e98..9a27a419d0 100644
--- a/test/charge_manager.c
+++ b/test/charge_manager.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -18,16 +18,11 @@
 
 /* Charge supplier priority: lower number indicates higher priority. */
 const int supplier_priority[] = {
-	[CHARGE_SUPPLIER_TEST1] = 0,
-	[CHARGE_SUPPLIER_TEST2] = 1,
-	[CHARGE_SUPPLIER_TEST3] = 1,
-	[CHARGE_SUPPLIER_TEST4] = 1,
-	[CHARGE_SUPPLIER_TEST5] = 3,
-	[CHARGE_SUPPLIER_TEST6] = 3,
-	[CHARGE_SUPPLIER_TEST7] = 5,
-	[CHARGE_SUPPLIER_TEST8] = 6,
-	[CHARGE_SUPPLIER_TEST9] = 6,
-	[CHARGE_SUPPLIER_TEST10] = 7,
+	[CHARGE_SUPPLIER_TEST1] = 0, [CHARGE_SUPPLIER_TEST2] = 1,
+	[CHARGE_SUPPLIER_TEST3] = 1, [CHARGE_SUPPLIER_TEST4] = 1,
+	[CHARGE_SUPPLIER_TEST5] = 3, [CHARGE_SUPPLIER_TEST6] = 3,
+	[CHARGE_SUPPLIER_TEST7] = 5, [CHARGE_SUPPLIER_TEST8] = 6,
+	[CHARGE_SUPPLIER_TEST9] = 6, [CHARGE_SUPPLIER_TEST10] = 7,
 };
 BUILD_ASSERT((int)CHARGE_SUPPLIER_COUNT == (int)CHARGE_SUPPLIER_TEST_COUNT);
 BUILD_ASSERT(ARRAY_SIZE(supplier_priority) == CHARGE_SUPPLIER_COUNT);
@@ -39,8 +34,8 @@ static int new_power_request[CONFIG_USB_PD_PORT_MAX_COUNT];
 static enum pd_power_role power_role[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 /* Callback functions called by CM on state change */
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	active_charge_limit = charge_ma;
 }
@@ -156,8 +151,8 @@ static int test_initialization(void)
 	TEST_ASSERT(active_charge_port == CHARGE_PORT_NONE);
 
 	/* Update last pair and verify a charge port has been selected */
-	charge_manager_update_charge(CHARGE_SUPPLIER_COUNT-1,
-				     board_get_usb_pd_port_count()-1,
+	charge_manager_update_charge(CHARGE_SUPPLIER_COUNT - 1,
+				     board_get_usb_pd_port_count() - 1,
 				     &charge);
 	wait_for_charge_manager_refresh();
 	TEST_ASSERT(active_charge_port != CHARGE_PORT_NONE);
@@ -787,7 +782,7 @@ static int test_unknown_dualrole_capability(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
@@ -801,5 +796,8 @@ void run_test(int argc, char **argv)
 	RUN_TEST(test_rejected_port);
 	RUN_TEST(test_unknown_dualrole_capability);
 
+	/* Some handlers are still running after the test ends. */
+	sleep(2);
+
 	test_print_result();
 }
diff --git a/test/charge_manager.tasklist b/test/charge_manager.tasklist
index 1f6f139a63..8c05d700ee 100644
--- a/test/charge_manager.tasklist
+++ b/test/charge_manager.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/charge_manager_drp_charging.tasklist b/test/charge_manager_drp_charging.tasklist
index e39c934e44..7b9e5153c4 100644
--- a/test/charge_manager_drp_charging.tasklist
+++ b/test/charge_manager_drp_charging.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/charge_ramp.c b/test/charge_ramp.c
index 84cac57b8e..a4d53b31d6 100644
--- a/test/charge_ramp.c
+++ b/test/charge_ramp.c
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,7 +19,7 @@
 
 #define TASK_EVENT_OVERCURRENT (1 << 0)
 
-#define RAMP_STABLE_DELAY (120*SECOND)
+#define RAMP_STABLE_DELAY (120 * SECOND)
 
 /*
  * Time to delay for detecting the charger type. This value follows
@@ -27,7 +27,7 @@
  * CHARGE_DETECT_DELAY so we guarantee we wake up before the ramp
  * has started.
  */
-#define CHARGE_DETECT_DELAY_TEST (CHARGE_DETECT_DELAY - 100*MSEC)
+#define CHARGE_DETECT_DELAY_TEST (CHARGE_DETECT_DELAY - 100 * MSEC)
 
 static int system_load_current_ma;
 static int vbus_low_current_ma = 500;
@@ -73,8 +73,8 @@ int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
 	       vbus_low_current_ma;
 }
 
-void board_set_charge_limit(int port, int supplier, int limit_ma,
-			    int max_ma, int max_mv)
+void board_set_charge_limit(int port, int supplier, int limit_ma, int max_ma,
+			    int max_mv)
 {
 	charge_limit_ma = limit_ma;
 	if (charge_limit_ma > overcurrent_current_ma)
@@ -96,9 +96,8 @@ static void plug_charger_with_ts(int supplier_type, int port, int min_current,
 static void plug_charger(int supplier_type, int port, int min_current,
 			 int vbus_low_current, int overcurrent_current)
 {
-	plug_charger_with_ts(supplier_type, port, min_current,
-			     vbus_low_current, overcurrent_current,
-			     get_time());
+	plug_charger_with_ts(supplier_type, port, min_current, vbus_low_current,
+			     overcurrent_current, get_time());
 }
 
 static void unplug_charger(void)
@@ -137,7 +136,7 @@ static int test_no_ramp(void)
 	 * the charge limit.  This just needs at least transition to the
 	 * CHG_RAMP_OVERCURRENT_DETECT state.
 	 */
-	usleep(CHARGE_DETECT_DELAY_TEST + 200*MSEC);
+	usleep(CHARGE_DETECT_DELAY_TEST + 200 * MSEC);
 	/* That's right. Start at 500 mA */
 	TEST_ASSERT(charge_limit_ma == 500);
 	TEST_ASSERT(wait_stable_no_overcurrent());
@@ -442,14 +441,14 @@ static int test_equal_priority_overcurrent(void)
 	 * switches to the other one.
 	 */
 	while (1) {
-		plug_charger_with_ts(CHARGE_SUPPLIER_TEST4, 0, 500, 3000,
-				     2000, oc_time);
+		plug_charger_with_ts(CHARGE_SUPPLIER_TEST4, 0, 500, 3000, 2000,
+				     oc_time);
 		oc_time = get_time();
 		oc_time.val += 600 * MSEC;
 		if (wait_stable_no_overcurrent())
 			break;
-		plug_charger_with_ts(CHARGE_SUPPLIER_TEST4, 1, 500, 3000,
-				     2000, oc_time);
+		plug_charger_with_ts(CHARGE_SUPPLIER_TEST4, 1, 500, 3000, 2000,
+				     oc_time);
 		oc_time = get_time();
 		oc_time.val += 600 * MSEC;
 		if (wait_stable_no_overcurrent())
@@ -497,7 +496,7 @@ static int test_ramp_limit(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/charge_ramp.tasklist b/test/charge_ramp.tasklist
index 1e18846c75..ff0b0b7fd0 100644
--- a/test/charge_ramp.tasklist
+++ b/test/charge_ramp.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/chipset.c b/test/chipset.c
new file mode 100644
index 0000000000..6c9031e3f0
--- /dev/null
+++ b/test/chipset.c
@@ -0,0 +1,32 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Test chipset
+ */
+
+#define CONFIG_CMD_AP_RESET_LOG
+
+#include "chipset.h"
+#include "test_util.h"
+
+static int test_get_shutdown_reason(void)
+{
+	enum chipset_shutdown_reason reason = chipset_get_shutdown_reason();
+
+	TEST_ASSERT(reason == 0);
+	report_ap_reset(CHIPSET_SHUTDOWN_POWERFAIL);
+	reason = chipset_get_shutdown_reason();
+	TEST_ASSERT(reason == CHIPSET_SHUTDOWN_POWERFAIL);
+
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
+{
+	test_reset();
+
+	RUN_TEST(test_get_shutdown_reason);
+
+	test_print_result();
+}
diff --git a/test/chipset.tasklist b/test/chipset.tasklist
new file mode 100644
index 0000000000..45964224fe
--- /dev/null
+++ b/test/chipset.tasklist
@@ -0,0 +1,10 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST  \
+        TASK_TEST(CHIPSET, chipset_task, NULL, TASK_STACK_SIZE)
diff --git a/test/compile_time_macros.c b/test/compile_time_macros.c
index 7d4bee4aa6..544da9e0d8 100644
--- a/test/compile_time_macros.c
+++ b/test/compile_time_macros.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -9,10 +9,9 @@
 #include "common.h"
 #include "test_util.h"
 
-
 static int test_BIT(void)
 {
-	TEST_EQ(BIT(0),  0x00000001U, "%u");
+	TEST_EQ(BIT(0), 0x00000001U, "%u");
 	TEST_EQ(BIT(25), 0x02000000U, "%u");
 	TEST_EQ(BIT(31), 0x80000000U, "%u");
 
@@ -21,7 +20,7 @@ static int test_BIT(void)
 
 static int test_BIT_ULL(void)
 {
-	TEST_EQ(BIT_ULL(0),  0x0000000000000001ULL, "%Lu");
+	TEST_EQ(BIT_ULL(0), 0x0000000000000001ULL, "%Lu");
 	TEST_EQ(BIT_ULL(25), 0x0000000002000000ULL, "%Lu");
 	TEST_EQ(BIT_ULL(50), 0x0004000000000000ULL, "%Lu");
 	TEST_EQ(BIT_ULL(63), 0x8000000000000000ULL, "%Lu");
@@ -70,10 +69,10 @@ static int test_WRITE_BIT(void)
 
 static int test_GENMASK(void)
 {
-	TEST_EQ(GENMASK(0, 0),   0x00000001U, "%u");
-	TEST_EQ(GENMASK(31, 0),  0xFFFFFFFFU, "%u");
-	TEST_EQ(GENMASK(4, 4),   0x00000010U, "%u");
-	TEST_EQ(GENMASK(4, 0),   0x0000001FU, "%u");
+	TEST_EQ(GENMASK(0, 0), 0x00000001U, "%u");
+	TEST_EQ(GENMASK(31, 0), 0xFFFFFFFFU, "%u");
+	TEST_EQ(GENMASK(4, 4), 0x00000010U, "%u");
+	TEST_EQ(GENMASK(4, 0), 0x0000001FU, "%u");
 	TEST_EQ(GENMASK(21, 21), 0x00200000U, "%u");
 	TEST_EQ(GENMASK(31, 31), 0x80000000U, "%u");
 
@@ -82,11 +81,11 @@ static int test_GENMASK(void)
 
 static int test_GENMASK_ULL(void)
 {
-	TEST_EQ(GENMASK_ULL(0, 0),   0x0000000000000001ULL, "%Lu");
-	TEST_EQ(GENMASK_ULL(31, 0),  0x00000000FFFFFFFFULL, "%Lu");
-	TEST_EQ(GENMASK_ULL(63, 0),  0xFFFFFFFFFFFFFFFFULL, "%Lu");
-	TEST_EQ(GENMASK_ULL(4, 4),   0x0000000000000010ULL, "%Lu");
-	TEST_EQ(GENMASK_ULL(4, 0),   0x000000000000001FULL, "%Lu");
+	TEST_EQ(GENMASK_ULL(0, 0), 0x0000000000000001ULL, "%Lu");
+	TEST_EQ(GENMASK_ULL(31, 0), 0x00000000FFFFFFFFULL, "%Lu");
+	TEST_EQ(GENMASK_ULL(63, 0), 0xFFFFFFFFFFFFFFFFULL, "%Lu");
+	TEST_EQ(GENMASK_ULL(4, 4), 0x0000000000000010ULL, "%Lu");
+	TEST_EQ(GENMASK_ULL(4, 0), 0x000000000000001FULL, "%Lu");
 	TEST_EQ(GENMASK_ULL(21, 21), 0x0000000000200000ULL, "%Lu");
 	TEST_EQ(GENMASK_ULL(31, 31), 0x0000000080000000ULL, "%Lu");
 	TEST_EQ(GENMASK_ULL(63, 63), 0x8000000000000000ULL, "%Lu");
@@ -106,7 +105,7 @@ test_static int test_IS_ARRAY(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/compile_time_macros.tasklist b/test/compile_time_macros.tasklist
index 5ffe662d01..2d4595f76a 100644
--- a/test/compile_time_macros.tasklist
+++ b/test/compile_time_macros.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/console_edit.c b/test/console_edit.c
index 8d0721c14e..3ffb79609a 100644
--- a/test/console_edit.c
+++ b/test/console_edit.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,18 +10,20 @@
 #include "test_util.h"
 #include "timer.h"
 #include "util.h"
+#include "uart.h"
+#include "ec_commands.h"
 
 static int cmd_1_call_cnt;
 static int cmd_2_call_cnt;
 
-static int command_test_1(int argc, char **argv)
+static int command_test_1(int argc, const char **argv)
 {
 	cmd_1_call_cnt++;
 	return EC_SUCCESS;
 }
 DECLARE_CONSOLE_COMMAND(test1, command_test_1, NULL, NULL);
 
-static int command_test_2(int argc, char **argv)
+static int command_test_2(int argc, const char **argv)
 {
 	cmd_2_call_cnt++;
 	return EC_SUCCESS;
@@ -40,7 +42,7 @@ enum arrow_key_t {
 
 static void arrow_key(enum arrow_key_t k, int repeat)
 {
-	static char seq[4] = {0x1B, '[', 0, 0};
+	static char seq[4] = { 0x1B, '[', 0, 0 };
 	seq[2] = 'A' + k;
 	while (repeat--)
 		UART_INJECT(seq);
@@ -63,7 +65,7 @@ static void end_key(void)
 
 static void ctrl_key(char c)
 {
-	static char seq[2] = {0, 0};
+	static char seq[2] = { 0, 0 };
 	seq[0] = c - '@';
 	UART_INJECT(seq);
 }
@@ -98,7 +100,8 @@ static int test_backspace(void)
 	cmd_1_call_cnt = 0;
 	UART_INJECT("testx\b1\n");
 	msleep(30);
-	TEST_CHECK(cmd_1_call_cnt == 1);
+	TEST_ASSERT(cmd_1_call_cnt == 1);
+	return EC_SUCCESS;
 }
 
 static int test_insert_char(void)
@@ -108,7 +111,8 @@ static int test_insert_char(void)
 	arrow_key(ARROW_LEFT, 2);
 	UART_INJECT("s\n");
 	msleep(30);
-	TEST_CHECK(cmd_1_call_cnt == 1);
+	TEST_ASSERT(cmd_1_call_cnt == 1);
+	return EC_SUCCESS;
 }
 
 static int test_delete_char(void)
@@ -118,7 +122,8 @@ static int test_delete_char(void)
 	arrow_key(ARROW_LEFT, 1);
 	UART_INJECT("\b\n");
 	msleep(30);
-	TEST_CHECK(cmd_1_call_cnt == 1);
+	TEST_ASSERT(cmd_1_call_cnt == 1);
+	return EC_SUCCESS;
 }
 
 static int test_insert_delete_char(void)
@@ -130,7 +135,8 @@ static int test_insert_delete_char(void)
 	arrow_key(ARROW_RIGHT, 1);
 	UART_INJECT("s\n");
 	msleep(30);
-	TEST_CHECK(cmd_1_call_cnt == 1);
+	TEST_ASSERT(cmd_1_call_cnt == 1);
+	return EC_SUCCESS;
 }
 
 static int test_home_end_key(void)
@@ -142,7 +148,8 @@ static int test_home_end_key(void)
 	end_key();
 	UART_INJECT("1\n");
 	msleep(30);
-	TEST_CHECK(cmd_1_call_cnt == 1);
+	TEST_ASSERT(cmd_1_call_cnt == 1);
+	return EC_SUCCESS;
 }
 
 static int test_ctrl_k(void)
@@ -153,7 +160,8 @@ static int test_ctrl_k(void)
 	ctrl_key('K');
 	UART_INJECT("\n");
 	msleep(30);
-	TEST_CHECK(cmd_1_call_cnt == 1);
+	TEST_ASSERT(cmd_1_call_cnt == 1);
+	return EC_SUCCESS;
 }
 
 static int test_history_up(void)
@@ -164,7 +172,8 @@ static int test_history_up(void)
 	arrow_key(ARROW_UP, 1);
 	UART_INJECT("\n");
 	msleep(30);
-	TEST_CHECK(cmd_1_call_cnt == 2);
+	TEST_ASSERT(cmd_1_call_cnt == 2);
+	return EC_SUCCESS;
 }
 
 static int test_history_up_up(void)
@@ -178,7 +187,8 @@ static int test_history_up_up(void)
 	arrow_key(ARROW_UP, 2);
 	UART_INJECT("\n");
 	msleep(30);
-	TEST_CHECK(cmd_1_call_cnt == 2 && cmd_2_call_cnt == 1);
+	TEST_ASSERT(cmd_1_call_cnt == 2 && cmd_2_call_cnt == 1);
+	return EC_SUCCESS;
 }
 
 static int test_history_up_up_down(void)
@@ -193,7 +203,8 @@ static int test_history_up_up_down(void)
 	arrow_key(ARROW_DOWN, 1);
 	UART_INJECT("\n");
 	msleep(30);
-	TEST_CHECK(cmd_1_call_cnt == 1 && cmd_2_call_cnt == 2);
+	TEST_ASSERT(cmd_1_call_cnt == 1 && cmd_2_call_cnt == 2);
+	return EC_SUCCESS;
 }
 
 static int test_history_edit(void)
@@ -205,7 +216,8 @@ static int test_history_edit(void)
 	arrow_key(ARROW_UP, 1);
 	UART_INJECT("\b2\n");
 	msleep(30);
-	TEST_CHECK(cmd_1_call_cnt == 1 && cmd_2_call_cnt == 1);
+	TEST_ASSERT(cmd_1_call_cnt == 1 && cmd_2_call_cnt == 1);
+	return EC_SUCCESS;
 }
 
 static int test_history_stash(void)
@@ -219,13 +231,14 @@ static int test_history_stash(void)
 	arrow_key(ARROW_DOWN, 1);
 	UART_INJECT("2\n");
 	msleep(30);
-	TEST_CHECK(cmd_1_call_cnt == 1 && cmd_2_call_cnt == 1);
+	TEST_ASSERT(cmd_1_call_cnt == 1 && cmd_2_call_cnt == 1);
+	return EC_SUCCESS;
 }
 
 static int test_history_list(void)
 {
 	const char *exp_output = "history\n" /* Input command */
-				 "test3\n"   /* Output 4 last commands */
+				 "test3\n" /* Output 4 last commands */
 				 "test4\n"
 				 "test5\n"
 				 "history\n"
@@ -258,8 +271,8 @@ static int test_output_channel(void)
 	cputs(CC_TASK, "shouldn't see this either\n");
 	cflush();
 	test_capture_console(0);
-	TEST_ASSERT(compare_multiline_string(test_get_captured_console(),
-					     "") == 0);
+	TEST_ASSERT(compare_multiline_string(test_get_captured_console(), "") ==
+		    0);
 	UART_INJECT("chan restore\n");
 	msleep(30);
 	test_capture_console(1);
@@ -273,7 +286,35 @@ static int test_output_channel(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+/* This test is identical to console::buf_notify_null in
+ * zephyr/test/drivers/default/src/console.c. Please keep them in sync to
+ * verify that uart_console_read_buffer works identically in legacy EC and
+ * zephyr.
+ */
+static int test_buf_notify_null(void)
+{
+	char buffer[100];
+	uint16_t write_count;
+
+	/* Flush the console buffer before we start. */
+	TEST_ASSERT(uart_console_read_buffer_init() == 0);
+
+	/* Write a nul char to the buffer. */
+	cprintf(CC_SYSTEM, "ab%cc", 0);
+	cflush();
+
+	/* Check if the nul is present in the buffer. */
+	TEST_ASSERT(uart_console_read_buffer_init() == 0);
+	TEST_ASSERT(uart_console_read_buffer(CONSOLE_READ_RECENT, buffer,
+					     sizeof(buffer),
+					     &write_count) == 0);
+	TEST_ASSERT(strncmp(buffer, "abc", 4) == 0);
+	TEST_EQ(write_count, 4, "%d");
+
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
@@ -290,6 +331,7 @@ void run_test(int argc, char **argv)
 	RUN_TEST(test_history_stash);
 	RUN_TEST(test_history_list);
 	RUN_TEST(test_output_channel);
+	RUN_TEST(test_buf_notify_null);
 
 	test_print_result();
 }
diff --git a/test/console_edit.tasklist b/test/console_edit.tasklist
index da0ab6211a..100cb6b5bd 100644
--- a/test/console_edit.tasklist
+++ b/test/console_edit.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/cortexm_fpu.c b/test/cortexm_fpu.c
index 8564e2a4ef..c27edbaf40 100644
--- a/test/cortexm_fpu.c
+++ b/test/cortexm_fpu.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -33,11 +33,7 @@ static float divf(float a, float b)
 {
 	float result;
 
-	asm volatile(
-		"fdivs %0, %1, %2"
-		: "=w"(result)
-		: "w"(a), "w"(b)
-	);
+	asm volatile("fdivs %0, %1, %2" : "=w"(result) : "w"(a), "w"(b));
 
 	return result;
 }
@@ -162,7 +158,7 @@ test_static int test_cortexm_fpu_inexact(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/cortexm_fpu.tasklist b/test/cortexm_fpu.tasklist
index 7f9fb4dd8a..16313e9055 100644
--- a/test/cortexm_fpu.tasklist
+++ b/test/cortexm_fpu.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/crc.c b/test/crc.c
index e65be72ace..9943a7ac0c 100644
--- a/test/crc.c
+++ b/test/crc.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -37,7 +37,7 @@ static int test_8(void)
 {
 	uint32_t crc;
 	const uint32_t input = 0xdeadbeef;
-	const uint8_t *p = (const uint8_t *) &input;
+	const uint8_t *p = (const uint8_t *)&input;
 	int i;
 
 	crc32_init();
@@ -83,7 +83,7 @@ static int test_cros_crc8(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/crc.tasklist b/test/crc.tasklist
index f46a2eaa1d..bf2309064a 100644
--- a/test/crc.tasklist
+++ b/test/crc.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/debug.c b/test/debug.c
new file mode 100644
index 0000000000..2c637ab725
--- /dev/null
+++ b/test/debug.c
@@ -0,0 +1,47 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "debug.h"
+#include "string.h"
+#include "test_util.h"
+
+static bool debugger_connected;
+
+static void print_usage(void)
+{
+	ccprintf("usage: runtest [debugger|no_debugger]\n");
+}
+
+test_static int test_debugger_is_connected(void)
+{
+	ccprintf("debugger_is_connected: %d\n", debugger_connected);
+	TEST_EQ(debugger_is_connected(), debugger_connected, "%d");
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
+{
+	test_reset();
+
+	if (argc < 2) {
+		print_usage();
+		test_fail();
+		return;
+	}
+
+	if (strncmp(argv[1], "debugger", sizeof("debugger")) == 0)
+		debugger_connected = true;
+	else if (strncmp(argv[1], "no_debugger", sizeof("no_debugger")) == 0) {
+		debugger_connected = false;
+	} else {
+		print_usage();
+		test_fail();
+		return;
+	}
+
+	RUN_TEST(test_debugger_is_connected);
+	test_print_result();
+}
diff --git a/test/debug.tasklist b/test/debug.tasklist
new file mode 100644
index 0000000000..959f62ef79
--- /dev/null
+++ b/test/debug.tasklist
@@ -0,0 +1,9 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST
diff --git a/test/entropy.c b/test/entropy.c
index fb066a6c5b..8fbdb9147f 100644
--- a/test/entropy.c
+++ b/test/entropy.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -26,10 +26,10 @@ uint32_t log2(int32_t val)
 	int val1 = 31 - __builtin_clz(val);
 	int val2 = 32 - __builtin_clz(val - 1);
 
-	return log2_mult * (val1 + val2)/2;
+	return log2_mult * (val1 + val2) / 2;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	const int loopcount = 512;
 
@@ -52,7 +52,7 @@ void run_test(int argc, char **argv)
 		t1 = get_time();
 		if (i == 0)
 			ccprintf("Got %zd bytes in %" PRId64 " us\n",
-				sizeof(buffer), t1.val - t0.val);
+				 sizeof(buffer), t1.val - t0.val);
 
 		for (j = 0; j < sizeof(buffer); j++)
 			buckets[buffer[j]]++;
@@ -82,7 +82,7 @@ void run_test(int argc, char **argv)
 	ccprintf("\n");
 
 	ccprintf("Entropy: %u/1000 bits\n",
-		entropy * 1000 / (log2_mult * totalcount));
+		 entropy * 1000 / (log2_mult * totalcount));
 
 	/* We want at least 2 bits of entropy (out of a maximum of 8) */
 	if ((entropy / (log2_mult * totalcount)) >= 2)
diff --git a/test/entropy.tasklist b/test/entropy.tasklist
index 80072bb620..329f9a3d28 100644
--- a/test/entropy.tasklist
+++ b/test/entropy.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/extpwr_gpio.c b/test/extpwr_gpio.c
index d1f77c9167..8a17a9580c 100644
--- a/test/extpwr_gpio.c
+++ b/test/extpwr_gpio.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -51,7 +51,7 @@ static int test_hook(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/extpwr_gpio.tasklist b/test/extpwr_gpio.tasklist
index da0ab6211a..100cb6b5bd 100644
--- a/test/extpwr_gpio.tasklist
+++ b/test/extpwr_gpio.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/fake_battery.c b/test/fake_battery.c
index 4442300572..9dabbb31d9 100644
--- a/test/fake_battery.c
+++ b/test/fake_battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/test/fake_usbc.c b/test/fake_usbc.c
index 2cabb2dee0..1d9c42a97a 100644
--- a/test/fake_usbc.c
+++ b/test/fake_usbc.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -15,17 +15,20 @@ __overridable int pd_is_vbus_present(int port)
 }
 
 __overridable void pd_request_data_swap(int port)
-{}
+{
+}
 
 __overridable void pd_request_power_swap(int port)
-{}
+{
+}
 
 void pd_request_vconn_swap_off(int port)
-{}
+{
+}
 
 void pd_request_vconn_swap_on(int port)
-{}
-
+{
+}
 
 static enum pd_data_role data_role;
 __overridable enum pd_data_role pd_get_data_role(int port)
@@ -68,10 +71,12 @@ int tc_check_vconn_swap(int port)
 }
 
 void tc_ctvpd_detected(int port)
-{}
+{
+}
 
 void tc_disc_ident_complete(int port)
-{}
+{
+}
 
 static int attached_snk;
 int tc_is_attached_snk(int port)
@@ -91,28 +96,36 @@ int tc_is_vconn_src(int port)
 }
 
 void tc_hard_reset_request(int port)
-{}
+{
+}
 
 void tc_hard_reset_complete(int port)
-{}
+{
+}
 
 void tc_partner_dr_data(int port, int en)
-{}
+{
+}
 
 void tc_partner_dr_power(int port, int en)
-{}
+{
+}
 
 void tc_partner_unconstrainedpower(int port, int en)
-{}
+{
+}
 
 void tc_partner_usb_comm(int port, int en)
-{}
+{
+}
 
 void tc_pd_connection(int port, int en)
-{}
+{
+}
 
 void tc_pr_swap_complete(int port, bool success)
-{}
+{
+}
 
 void tc_prs_snk_src_assert_rp(int port)
 {
@@ -127,16 +140,20 @@ void tc_prs_src_snk_assert_rd(int port)
 }
 
 void tc_src_power_off(int port)
-{}
+{
+}
 
 void tc_set_timeout(int port, uint64_t timeout)
-{}
+{
+}
 
 __overridable void tc_start_error_recovery(int port)
-{}
+{
+}
 
 __overridable void tc_snk_power_off(int port)
-{}
+{
+}
 
 __overridable void pe_invalidate_explicit_contract(int port)
 {
@@ -148,7 +165,7 @@ __overridable enum pd_dual_role_states pd_get_dual_role(int port)
 }
 
 __overridable void pd_dev_get_rw_hash(int port, uint16_t *dev_id,
-		uint8_t *rw_hash, uint32_t *current_image)
+				      uint8_t *rw_hash, uint32_t *current_image)
 {
 }
 
@@ -185,7 +202,7 @@ enum idh_ptype get_usb_pd_mux_cable_type(int port)
 	return IDH_PTYPE_UNDEF;
 }
 
-const uint32_t * const pd_get_src_caps(int port)
+const uint32_t *const pd_get_src_caps(int port)
 {
 	return NULL;
 }
@@ -200,8 +217,7 @@ uint8_t pd_get_src_cap_cnt(int port)
 }
 #endif
 
-#if !defined(CONFIG_USB_DRP_ACC_TRYSRC) && \
-	!defined(CONFIG_USB_CTVPD)
+#if !defined(CONFIG_USB_DRP_ACC_TRYSRC) && !defined(CONFIG_USB_CTVPD)
 int pd_is_connected(int port)
 {
 	return true;
@@ -271,12 +287,12 @@ void dpm_mode_exit_complete(int port)
 }
 
 void dpm_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count,
-		uint32_t *vdm)
+		   uint32_t *vdm)
 {
 }
 
 void dpm_vdm_naked(int port, enum tcpci_msg_type type, uint16_t svid,
-		uint8_t vdm_cmd)
+		   uint8_t vdm_cmd)
 {
 }
 
@@ -312,6 +328,14 @@ void dpm_remove_source(int port)
 {
 }
 
+void dpm_bist_shared_mode_enter(int port)
+{
+}
+
+void dpm_bist_shared_mode_exit(int port)
+{
+}
+
 int dpm_get_source_pdo(const uint32_t **src_pdo, const int port)
 {
 	*src_pdo = pd_src_pdo;
@@ -323,9 +347,13 @@ int dpm_get_status_msg(int port, uint8_t *msg, uint32_t *len)
 	return EC_SUCCESS;
 }
 
+void dpm_handle_alert(int port, uint32_t ado)
+{
+}
+
 static enum tcpc_rp_value lcl_rp;
 __overridable void typec_select_src_current_limit_rp(int port,
-						  enum tcpc_rp_value rp)
+						     enum tcpc_rp_value rp)
 {
 	lcl_rp = rp;
 }
diff --git a/test/fan.c b/test/fan.c
index d03aa0213c..76c3208cc6 100644
--- a/test/fan.c
+++ b/test/fan.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,14 +10,13 @@
 #include "fan.h"
 #include "hooks.h"
 #include "host_command.h"
-#include "printf.h"
 #include "temp_sensor.h"
 #include "test_util.h"
 #include "thermal.h"
 #include "timer.h"
 #include "util.h"
 
-#define FAN_RPM(fan)	fans[fan].rpm
+#define FAN_RPM(fan) fans[fan].rpm
 
 /*****************************************************************************/
 /* Tests */
@@ -105,9 +104,16 @@ static int test_fan(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	RUN_TEST(test_fan);
 
 	test_print_result();
 }
+
+/* Doesn't do anything, but it makes this test stop intermittently covering
+ * some code in core/host/task.c:fast_forward().
+ */
+void interrupt_generator(void)
+{
+}
diff --git a/test/fan.tasklist b/test/fan.tasklist
index 25dcf124db..836bdd08ed 100644
--- a/test/fan.tasklist
+++ b/test/fan.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/flash.c b/test/flash.c
index 4f9ca74016..bd1b646f1f 100644
--- a/test/flash.c
+++ b/test/flash.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -103,60 +103,59 @@ static int verify_erase(int offset, int size)
 	return EC_SUCCESS;
 }
 
-
-#define VERIFY_NO_WRITE(off, sz, d) \
-	do { \
-		record_flash(off, sz); \
+#define VERIFY_NO_WRITE(off, sz, d)                                        \
+	do {                                                               \
+		record_flash(off, sz);                                     \
 		TEST_ASSERT(host_command_write(off, sz, d) != EC_SUCCESS); \
-		TEST_ASSERT(verify_flash(off, sz) == EC_SUCCESS); \
+		TEST_ASSERT(verify_flash(off, sz) == EC_SUCCESS);          \
 	} while (0)
 
-#define VERIFY_NO_ERASE(off, sz) \
-	do { \
-		record_flash(off, sz); \
+#define VERIFY_NO_ERASE(off, sz)                                        \
+	do {                                                            \
+		record_flash(off, sz);                                  \
 		TEST_ASSERT(host_command_erase(off, sz) != EC_SUCCESS); \
-		TEST_ASSERT(verify_flash(off, sz) == EC_SUCCESS); \
+		TEST_ASSERT(verify_flash(off, sz) == EC_SUCCESS);       \
 	} while (0)
 
-#define VERIFY_WRITE(off, sz, d) \
-	do { \
+#define VERIFY_WRITE(off, sz, d)                                           \
+	do {                                                               \
 		TEST_ASSERT(host_command_write(off, sz, d) == EC_SUCCESS); \
-		TEST_ASSERT(verify_write(off, sz, d) == EC_SUCCESS); \
+		TEST_ASSERT(verify_write(off, sz, d) == EC_SUCCESS);       \
 	} while (0)
 
-#define VERIFY_ERASE(off, sz) \
-	do { \
+#define VERIFY_ERASE(off, sz)                                           \
+	do {                                                            \
 		TEST_ASSERT(host_command_erase(off, sz) == EC_SUCCESS); \
-		TEST_ASSERT(verify_erase(off, sz) == EC_SUCCESS); \
+		TEST_ASSERT(verify_erase(off, sz) == EC_SUCCESS);       \
 	} while (0)
 
-#define SET_WP_FLAGS(m, f) \
-	TEST_ASSERT(host_command_protect(m, ((f) ? m : 0), \
-				NULL, NULL, NULL) == EC_RES_SUCCESS)
+#define SET_WP_FLAGS(m, f)                                             \
+	TEST_ASSERT(host_command_protect(m, ((f) ? m : 0), NULL, NULL, \
+					 NULL) == EC_RES_SUCCESS)
 
-#define ASSERT_WP_FLAGS(f) \
-	do { \
-		uint32_t flags; \
+#define ASSERT_WP_FLAGS(f)                                                    \
+	do {                                                                  \
+		uint32_t flags;                                               \
 		TEST_ASSERT(host_command_protect(0, 0, &flags, NULL, NULL) == \
-			    EC_RES_SUCCESS); \
-		TEST_ASSERT(flags & (f)); \
+			    EC_RES_SUCCESS);                                  \
+		TEST_ASSERT(flags &(f));                                      \
 	} while (0)
 
-#define ASSERT_WP_NO_FLAGS(f) \
-	do { \
-		uint32_t flags; \
+#define ASSERT_WP_NO_FLAGS(f)                                                 \
+	do {                                                                  \
+		uint32_t flags;                                               \
 		TEST_ASSERT(host_command_protect(0, 0, &flags, NULL, NULL) == \
-			    EC_RES_SUCCESS); \
-		TEST_ASSERT((flags & (f)) == 0); \
+			    EC_RES_SUCCESS);                                  \
+		TEST_ASSERT((flags & (f)) == 0);                              \
 	} while (0)
 
-#define VERIFY_REGION_INFO(r, o, s) \
-	do { \
-		uint32_t offset, size; \
+#define VERIFY_REGION_INFO(r, o, s)                                        \
+	do {                                                               \
+		uint32_t offset, size;                                     \
 		TEST_ASSERT(host_command_region_info(r, &offset, &size) == \
-			    EC_RES_SUCCESS); \
-		TEST_ASSERT(offset == (o)); \
-		TEST_ASSERT(size == (s)); \
+			    EC_RES_SUCCESS);                               \
+		TEST_ASSERT(offset == (o));                                \
+		TEST_ASSERT(size == (s));                                  \
 	} while (0)
 
 int host_command_read(int offset, int size, char *out)
@@ -195,9 +194,8 @@ int host_command_erase(int offset, int size)
 				      sizeof(params), NULL, 0);
 }
 
-int host_command_protect(uint32_t mask, uint32_t flags,
-			 uint32_t *flags_out, uint32_t *valid_out,
-			 uint32_t *writable_out)
+int host_command_protect(uint32_t mask, uint32_t flags, uint32_t *flags_out,
+			 uint32_t *valid_out, uint32_t *writable_out)
 {
 	struct ec_params_flash_protect params;
 	struct ec_response_flash_protect resp;
@@ -222,7 +220,7 @@ int host_command_protect(uint32_t mask, uint32_t flags,
 }
 
 int host_command_region_info(enum ec_flash_region reg, uint32_t *offset,
-				 uint32_t *size)
+			     uint32_t *size)
 {
 	struct ec_params_flash_region_info params;
 	struct ec_response_flash_region_info resp;
@@ -350,29 +348,31 @@ static int test_flash_info(void)
 {
 	struct ec_response_flash_info_1 resp;
 
-	TEST_ASSERT(test_send_host_command(EC_CMD_FLASH_INFO, 1, NULL, 0,
-		    &resp, sizeof(resp)) == EC_RES_SUCCESS);
+	TEST_ASSERT(test_send_host_command(EC_CMD_FLASH_INFO, 1, NULL, 0, &resp,
+					   sizeof(resp)) == EC_RES_SUCCESS);
 
-	TEST_CHECK((resp.flash_size == CONFIG_FLASH_SIZE_BYTES) &&
-		   (resp.write_block_size == CONFIG_FLASH_WRITE_SIZE) &&
-		   (resp.erase_block_size == CONFIG_FLASH_ERASE_SIZE) &&
-		   (resp.protect_block_size == CONFIG_FLASH_BANK_SIZE));
+	TEST_ASSERT(resp.flash_size == CONFIG_FLASH_SIZE_BYTES);
+	TEST_ASSERT(resp.write_block_size == CONFIG_FLASH_WRITE_SIZE);
+	TEST_ASSERT(resp.erase_block_size == CONFIG_FLASH_ERASE_SIZE);
+	TEST_ASSERT(resp.protect_block_size == CONFIG_FLASH_BANK_SIZE);
+	return EC_SUCCESS;
 }
 
 static int test_region_info(void)
 {
 	VERIFY_REGION_INFO(EC_FLASH_REGION_RO,
 			   CONFIG_EC_PROTECTED_STORAGE_OFF +
-			   CONFIG_RO_STORAGE_OFF, EC_FLASH_REGION_RO_SIZE);
+				   CONFIG_RO_STORAGE_OFF,
+			   EC_FLASH_REGION_RO_SIZE);
 	VERIFY_REGION_INFO(EC_FLASH_REGION_ACTIVE,
 			   CONFIG_EC_WRITABLE_STORAGE_OFF +
-			   CONFIG_RW_STORAGE_OFF,
+				   CONFIG_RW_STORAGE_OFF,
 			   CONFIG_EC_WRITABLE_STORAGE_SIZE);
-	VERIFY_REGION_INFO(EC_FLASH_REGION_WP_RO,
-			   CONFIG_WP_STORAGE_OFF, CONFIG_WP_STORAGE_SIZE);
+	VERIFY_REGION_INFO(EC_FLASH_REGION_WP_RO, CONFIG_WP_STORAGE_OFF,
+			   CONFIG_WP_STORAGE_SIZE);
 	VERIFY_REGION_INFO(EC_FLASH_REGION_UPDATE,
 			   CONFIG_EC_WRITABLE_STORAGE_OFF +
-			   CONFIG_RW_STORAGE_OFF,
+				   CONFIG_RW_STORAGE_OFF,
 			   CONFIG_EC_WRITABLE_STORAGE_SIZE);
 
 	return EC_SUCCESS;
@@ -401,9 +401,11 @@ static int test_write_protect(void)
 
 	/* Check we cannot erase anything */
 	TEST_ASSERT(crec_flash_physical_erase(CONFIG_RO_STORAGE_OFF,
-			CONFIG_FLASH_ERASE_SIZE) != EC_SUCCESS);
+					      CONFIG_FLASH_ERASE_SIZE) !=
+		    EC_SUCCESS);
 	TEST_ASSERT(crec_flash_physical_erase(CONFIG_RW_STORAGE_OFF,
-			CONFIG_FLASH_ERASE_SIZE) != EC_SUCCESS);
+					      CONFIG_FLASH_ERASE_SIZE) !=
+		    EC_SUCCESS);
 
 	/* We should not even try to write/erase */
 	VERIFY_NO_ERASE(CONFIG_RO_STORAGE_OFF, CONFIG_FLASH_ERASE_SIZE);
@@ -419,7 +421,8 @@ static int test_boot_write_protect(void)
 	/* Check write protect state persists through reboot */
 	ASSERT_WP_FLAGS(EC_FLASH_PROTECT_RO_NOW | EC_FLASH_PROTECT_RO_AT_BOOT);
 	TEST_ASSERT(crec_flash_physical_erase(CONFIG_RO_STORAGE_OFF,
-			CONFIG_FLASH_ERASE_SIZE) != EC_SUCCESS);
+					      CONFIG_FLASH_ERASE_SIZE) !=
+		    EC_SUCCESS);
 
 	return EC_SUCCESS;
 }
@@ -500,7 +503,7 @@ int task_test(void *data)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	msleep(30); /* Wait for TASK_ID_TEST to initialize */
 	task_wake(TASK_ID_TEST);
diff --git a/test/flash.tasklist b/test/flash.tasklist
index dae84c1635..dbebe0dabb 100644
--- a/test/flash.tasklist
+++ b/test/flash.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/flash_physical.c b/test/flash_physical.c
index 06dd495254..8136f6b5e3 100644
--- a/test/flash_physical.c
+++ b/test/flash_physical.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -30,7 +30,6 @@ struct flash_info flash_info = {
 #error "Flash info not defined for this chip. Please add it."
 #endif
 
-
 test_static int test_lock_option_bytes(void)
 {
 	TEST_EQ(flash_option_bytes_locked(), true, "%d");
@@ -119,7 +118,7 @@ test_static int test_flash_config(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	ccprintf("Running flash physical test\n");
 	RUN_TEST(test_flash_config);
diff --git a/test/flash_physical.tasklist b/test/flash_physical.tasklist
index 51734f058d..a1f1a94e2d 100644
--- a/test/flash_physical.tasklist
+++ b/test/flash_physical.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/flash_write_protect.c b/test/flash_write_protect.c
index 888482076f..138aab24ff 100644
--- a/test/flash_write_protect.c
+++ b/test/flash_write_protect.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -97,7 +97,6 @@ test_static int test_cbi_wb_asserted_immediately(void)
 	/* Now make sure EC_CBI_WP is asserted immediately. */
 	TEST_EQ(gpio_get_level(GPIO_EC_CBI_WP), 1, "%d");
 
-
 	return EC_SUCCESS;
 }
 
@@ -131,7 +130,7 @@ int task_test(void *unused)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	msleep(30); /* Wait for TASK_ID_TEST to initialize */
 	task_wake(TASK_ID_TEST);
diff --git a/test/flash_write_protect.tasklist b/test/flash_write_protect.tasklist
index 21619decc3..974106d6c2 100644
--- a/test/flash_write_protect.tasklist
+++ b/test/flash_write_protect.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/float.tasklist b/test/float.tasklist
index 9ad0114d8a..5216cd488c 100644
--- a/test/float.tasklist
+++ b/test/float.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/fp.c b/test/fp.c
index 2d9aa1ed5e..ab41868578 100644
--- a/test/fp.c
+++ b/test/fp.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -36,9 +36,9 @@
 #error "No such test configuration."
 #endif
 
-#define IS_FPV3_VECTOR_EQUAL(a, b, diff)                                       \
-	(IS_FP_EQUAL((a)[0], (b)[0], (diff)) &&                                \
-	 IS_FP_EQUAL((a)[1], (b)[1], (diff)) &&                                \
+#define IS_FPV3_VECTOR_EQUAL(a, b, diff)        \
+	(IS_FP_EQUAL((a)[0], (b)[0], (diff)) && \
+	 IS_FP_EQUAL((a)[1], (b)[1], (diff)) && \
 	 IS_FP_EQUAL((a)[2], (b)[2], (diff)))
 #define IS_FP_EQUAL(a, b, diff) ((a) >= ((b)-diff) && (a) <= ((b) + diff))
 #define IS_FLOAT_EQUAL(a, b, diff) IS_FP_EQUAL(a, b, diff)
@@ -47,9 +47,9 @@ static int test_fpv3_scalar_mul(void)
 {
 	const int N = 3;
 	const float s = 2.0f;
-	floatv3_t r = {1.0f, 2.0f, 4.0f};
+	floatv3_t r = { 1.0f, 2.0f, 4.0f };
 	/* Golden result g = s * r; */
-	const floatv3_t g = {2.0f, 4.0f, 8.0f};
+	const floatv3_t g = { 2.0f, 4.0f, 8.0f };
 	int i;
 	fpv3_t a;
 
@@ -68,8 +68,8 @@ static int test_fpv3_dot(void)
 {
 	const int N = 3;
 	int i;
-	floatv3_t a = {1.8f, 2.12f, 4.12f};
-	floatv3_t b = {3.1f, 4.3f, 5.8f};
+	floatv3_t a = { 1.8f, 2.12f, 4.12f };
+	floatv3_t b = { 3.1f, 4.3f, 5.8f };
 	/* Golden result g = dot(a, b). */
 	float g = 38.592f;
 	fpv3_t fpa, fpb;
@@ -81,8 +81,7 @@ static int test_fpv3_dot(void)
 	}
 
 	result = fpv3_dot(fpa, fpb);
-	TEST_ASSERT(IS_FP_EQUAL(result, FLOAT_TO_FP(g),
-				DOT_TOLERANCE));
+	TEST_ASSERT(IS_FP_EQUAL(result, FLOAT_TO_FP(g), DOT_TOLERANCE));
 
 	return EC_SUCCESS;
 }
@@ -91,7 +90,7 @@ static int test_fpv3_norm_squared(void)
 {
 	const int N = 3;
 	int i;
-	floatv3_t a = {3.0f, 4.0f, 5.0f};
+	floatv3_t a = { 3.0f, 4.0f, 5.0f };
 	/* Golden result g = norm_squared(a). */
 	float g = 50.0f;
 	fpv3_t fpa;
@@ -108,7 +107,7 @@ static int test_fpv3_norm_squared(void)
 static int test_fpv3_norm(void)
 {
 	const int N = 3;
-	floatv3_t a = {3.1f, 4.2f, 5.3f};
+	floatv3_t a = { 3.1f, 4.2f, 5.3f };
 	/* Golden result g = norm(a). */
 	float g = 7.439086f;
 	int i;
@@ -188,17 +187,14 @@ static int test_mat33_fp_scalar_mul(void)
 {
 	const int N = 3;
 	float scale = 3.11f;
-	mat33_float_t a = {
-		{1.0f, 2.0f, 3.0f},
-		{1.1f, 2.2f, 3.3f},
-		{0.38f, 13.2f, 88.3f}
-	};
+	mat33_float_t a = { { 1.0f, 2.0f, 3.0f },
+			    { 1.1f, 2.2f, 3.3f },
+			    { 0.38f, 13.2f, 88.3f } };
 	/* Golden result g = scalar_mul(a, scale). */
-	mat33_float_t g = {{3.11f, 6.22f, 9.33f},
-			   {3.421f, 6.842f, 10.263f},
-			   {1.18179988861083984375f, 41.051998138427734375f,
-			    274.613006591796875f}
-	};
+	mat33_float_t g = { { 3.11f, 6.22f, 9.33f },
+			    { 3.421f, 6.842f, 10.263f },
+			    { 1.18179988861083984375f, 41.051998138427734375f,
+			      274.613006591796875f } };
 	int i, j;
 	mat33_fp_t fpa;
 
@@ -219,9 +215,9 @@ static int test_mat33_fp_scalar_mul(void)
 static int test_mat33_fp_get_eigenbasis(void)
 {
 	mat33_fp_t s = {
-		{FLOAT_TO_FP(4.0f), FLOAT_TO_FP(2.0f), FLOAT_TO_FP(2.0f)},
-		{FLOAT_TO_FP(2.0f), FLOAT_TO_FP(4.0f), FLOAT_TO_FP(2.0f)},
-		{FLOAT_TO_FP(2.0f), FLOAT_TO_FP(2.0f), FLOAT_TO_FP(4.0f)}
+		{ FLOAT_TO_FP(4.0f), FLOAT_TO_FP(2.0f), FLOAT_TO_FP(2.0f) },
+		{ FLOAT_TO_FP(2.0f), FLOAT_TO_FP(4.0f), FLOAT_TO_FP(2.0f) },
+		{ FLOAT_TO_FP(2.0f), FLOAT_TO_FP(2.0f), FLOAT_TO_FP(4.0f) }
 	};
 	fpv3_t e_vals;
 	mat33_fp_t e_vecs;
@@ -229,15 +225,15 @@ static int test_mat33_fp_get_eigenbasis(void)
 
 	/* Golden result from float version. */
 	mat33_fp_t gold_vecs = {
-		{FLOAT_TO_FP(0.55735206f), FLOAT_TO_FP(0.55735206f),
-		 FLOAT_TO_FP(0.55735206f)},
-		{FLOAT_TO_FP(0.70710677f), FLOAT_TO_FP(-0.70710677f),
-		 FLOAT_TO_FP(0.0f)},
-		{FLOAT_TO_FP(-0.40824828f), FLOAT_TO_FP(-0.40824828f),
-		 FLOAT_TO_FP(0.81649655f)}
+		{ FLOAT_TO_FP(0.55735206f), FLOAT_TO_FP(0.55735206f),
+		  FLOAT_TO_FP(0.55735206f) },
+		{ FLOAT_TO_FP(0.70710677f), FLOAT_TO_FP(-0.70710677f),
+		  FLOAT_TO_FP(0.0f) },
+		{ FLOAT_TO_FP(-0.40824828f), FLOAT_TO_FP(-0.40824828f),
+		  FLOAT_TO_FP(0.81649655f) }
 	};
-	fpv3_t gold_vals = {FLOAT_TO_FP(8.0f), FLOAT_TO_FP(2.0f),
-			    FLOAT_TO_FP(2.0f)};
+	fpv3_t gold_vals = { FLOAT_TO_FP(8.0f), FLOAT_TO_FP(2.0f),
+			     FLOAT_TO_FP(2.0f) };
 
 	mat33_fp_get_eigenbasis(s, e_vals, e_vecs);
 
@@ -257,28 +253,26 @@ static int test_mat44_fp_decompose_lup(void)
 {
 	int i, j;
 	sizev4_t pivot;
-	mat44_fp_t fpa = {
-		{FLOAT_TO_FP(11.0f), FLOAT_TO_FP(9.0f),
-		 FLOAT_TO_FP(24.0f), FLOAT_TO_FP(2.0f)},
-		{FLOAT_TO_FP(1.0f), FLOAT_TO_FP(5.0f),
-		 FLOAT_TO_FP(2.0f), FLOAT_TO_FP(6.0f)},
-		{FLOAT_TO_FP(3.0f), FLOAT_TO_FP(17.0f),
-		 FLOAT_TO_FP(18.0f), FLOAT_TO_FP(1.0f)},
-		{FLOAT_TO_FP(2.0f), FLOAT_TO_FP(5.0f),
-		 FLOAT_TO_FP(7.0f), FLOAT_TO_FP(1.0f)}
-	};
+	mat44_fp_t fpa = { { FLOAT_TO_FP(11.0f), FLOAT_TO_FP(9.0f),
+			     FLOAT_TO_FP(24.0f), FLOAT_TO_FP(2.0f) },
+			   { FLOAT_TO_FP(1.0f), FLOAT_TO_FP(5.0f),
+			     FLOAT_TO_FP(2.0f), FLOAT_TO_FP(6.0f) },
+			   { FLOAT_TO_FP(3.0f), FLOAT_TO_FP(17.0f),
+			     FLOAT_TO_FP(18.0f), FLOAT_TO_FP(1.0f) },
+			   { FLOAT_TO_FP(2.0f), FLOAT_TO_FP(5.0f),
+			     FLOAT_TO_FP(7.0f), FLOAT_TO_FP(1.0f) } };
 	/* Golden result from float version. */
 	mat44_fp_t gold_lu = {
-		{FLOAT_TO_FP(11.0f), FLOAT_TO_FP(0.8181818f),
-		 FLOAT_TO_FP(2.1818182f), FLOAT_TO_FP(0.18181819f)},
-		{FLOAT_TO_FP(3.0f), FLOAT_TO_FP(14.545455f),
-		 FLOAT_TO_FP(0.78749999f), FLOAT_TO_FP(0.031249999f)},
-		{FLOAT_TO_FP(1.0f), FLOAT_TO_FP(4.181818f),
-		 FLOAT_TO_FP(-3.4749996f), FLOAT_TO_FP(-1.6366909f)},
-		{FLOAT_TO_FP(2.0f), FLOAT_TO_FP(3.3636365f),
-		 FLOAT_TO_FP(-0.012500112f), FLOAT_TO_FP(0.5107912f)}
+		{ FLOAT_TO_FP(11.0f), FLOAT_TO_FP(0.8181818f),
+		  FLOAT_TO_FP(2.1818182f), FLOAT_TO_FP(0.18181819f) },
+		{ FLOAT_TO_FP(3.0f), FLOAT_TO_FP(14.545455f),
+		  FLOAT_TO_FP(0.78749999f), FLOAT_TO_FP(0.031249999f) },
+		{ FLOAT_TO_FP(1.0f), FLOAT_TO_FP(4.181818f),
+		  FLOAT_TO_FP(-3.4749996f), FLOAT_TO_FP(-1.6366909f) },
+		{ FLOAT_TO_FP(2.0f), FLOAT_TO_FP(3.3636365f),
+		  FLOAT_TO_FP(-0.012500112f), FLOAT_TO_FP(0.5107912f) }
 	};
-	sizev4_t gold_pivot = {0, 2, 2, 3};
+	sizev4_t gold_pivot = { 0, 2, 2, 3 };
 
 	mat44_fp_decompose_lup(fpa, pivot);
 
@@ -296,22 +290,21 @@ static int test_mat44_fp_solve(void)
 {
 	int i;
 	fpv4_t x;
-	mat44_fp_t A = {
-		{FLOAT_TO_FP(11.0f), FLOAT_TO_FP(0.8181818f),
-		 FLOAT_TO_FP(2.1818182f), FLOAT_TO_FP(0.18181819f)},
-		{FLOAT_TO_FP(3.0f), FLOAT_TO_FP(14.545454),
-		 FLOAT_TO_FP(0.7875f), FLOAT_TO_FP(0.03125f)},
-		{FLOAT_TO_FP(1.0f), FLOAT_TO_FP(4.181818f),
-		 FLOAT_TO_FP(-3.4750001f), FLOAT_TO_FP(-1.6366906f)},
-		{FLOAT_TO_FP(2.0f), FLOAT_TO_FP(3.3636365f),
-		 FLOAT_TO_FP(-0.012500286f), FLOAT_TO_FP(0.5107909f)}
-	};
-	sizev4_t pivot = {0, 2, 2, 3};
-	fpv4_t b = {FLOAT_TO_FP(1.0f), FLOAT_TO_FP(3.3f), FLOAT_TO_FP(0.8f),
-		    FLOAT_TO_FP(8.9f)};
+	mat44_fp_t A = { { FLOAT_TO_FP(11.0f), FLOAT_TO_FP(0.8181818f),
+			   FLOAT_TO_FP(2.1818182f), FLOAT_TO_FP(0.18181819f) },
+			 { FLOAT_TO_FP(3.0f), FLOAT_TO_FP(14.545454),
+			   FLOAT_TO_FP(0.7875f), FLOAT_TO_FP(0.03125f) },
+			 { FLOAT_TO_FP(1.0f), FLOAT_TO_FP(4.181818f),
+			   FLOAT_TO_FP(-3.4750001f), FLOAT_TO_FP(-1.6366906f) },
+			 { FLOAT_TO_FP(2.0f), FLOAT_TO_FP(3.3636365f),
+			   FLOAT_TO_FP(-0.012500286f),
+			   FLOAT_TO_FP(0.5107909f) } };
+	sizev4_t pivot = { 0, 2, 2, 3 };
+	fpv4_t b = { FLOAT_TO_FP(1.0f), FLOAT_TO_FP(3.3f), FLOAT_TO_FP(0.8f),
+		     FLOAT_TO_FP(8.9f) };
 	/* Golden result from float version. */
-	fpv4_t gold_x = {FLOAT_TO_FP(-43.507435f), FLOAT_TO_FP(-21.459525f),
-			 FLOAT_TO_FP(26.629248f), FLOAT_TO_FP(16.80776f)};
+	fpv4_t gold_x = { FLOAT_TO_FP(-43.507435f), FLOAT_TO_FP(-21.459525f),
+			  FLOAT_TO_FP(26.629248f), FLOAT_TO_FP(16.80776f) };
 
 	mat44_fp_solve(A, x, b, pivot);
 
@@ -375,7 +368,7 @@ test_static int test_isinf(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/fp.tasklist b/test/fp.tasklist
index 9ad0114d8a..5216cd488c 100644
--- a/test/fp.tasklist
+++ b/test/fp.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/fpsensor.c b/test/fpsensor.c
index 1e7015882d..588374d4db 100644
--- a/test/fpsensor.c
+++ b/test/fpsensor.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -84,7 +84,7 @@ test_static int test_host_command_protocol_info_spi(void)
 		FP_TRANSPORT_TYPE_SPI, &expected_info[FP_TRANSPORT_TYPE_SPI]);
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	if (IS_ENABLED(HAS_TASK_FPSENSOR)) {
 		/* TODO(b/171924356): The "emulator" build only builds RO and
diff --git a/test/fpsensor.mocklist b/test/fpsensor.mocklist
index 3968a04e7e..3f2c60c583 100644
--- a/test/fpsensor.mocklist
+++ b/test/fpsensor.mocklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,6 +6,7 @@
 #ifdef BOARD_HOST
 #define CONFIG_TEST_MOCK_LIST \
 	MOCK(FP_SENSOR)       \
+	MOCK(FPSENSOR_CRYPTO) \
 	MOCK(FPSENSOR_DETECT) \
 	MOCK(FPSENSOR_STATE)  \
 	MOCK(MKBP_EVENTS)     \
diff --git a/test/fpsensor.tasklist b/test/fpsensor.tasklist
index ba137b7613..6c3ec6d65e 100644
--- a/test/fpsensor.tasklist
+++ b/test/fpsensor.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/fpsensor_crypto.c b/test/fpsensor_crypto.c
index d0fd92cf7c..9265a608b4 100644
--- a/test/fpsensor_crypto.c
+++ b/test/fpsensor_crypto.c
@@ -1,30 +1,33 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include <stdbool.h>
 
+#include "builtin/assert.h"
 #include "common.h"
 #include "ec_commands.h"
 #include "fpsensor_crypto.h"
 #include "fpsensor_state.h"
+#include "mock/fpsensor_crypto_mock.h"
 #include "mock/fpsensor_state_mock.h"
 #include "mock/rollback_mock.h"
 #include "mock/timer_mock.h"
 #include "test_util.h"
 #include "util.h"
 
+extern int get_ikm(uint8_t *ikm);
+
 static const uint8_t fake_positive_match_salt[] = {
 	0x04, 0x1f, 0x5a, 0xac, 0x5f, 0x79, 0x10, 0xaf,
 	0x04, 0x1d, 0x46, 0x3a, 0x5f, 0x08, 0xee, 0xcb,
 };
 
 static const uint8_t fake_user_id[] = {
-	0x28, 0xb5, 0x5a, 0x55, 0x57, 0x1b, 0x26, 0x88,
-	0xce, 0xc5, 0xd1, 0xfe, 0x1d, 0x58, 0x5b, 0x94,
-	0x51, 0xa2, 0x60, 0x49, 0x9f, 0xea, 0xb1, 0xea,
-	0xf7, 0x04, 0x2f, 0x0b, 0x20, 0xa5, 0x93, 0x64,
+	0x28, 0xb5, 0x5a, 0x55, 0x57, 0x1b, 0x26, 0x88, 0xce, 0xc5, 0xd1,
+	0xfe, 0x1d, 0x58, 0x5b, 0x94, 0x51, 0xa2, 0x60, 0x49, 0x9f, 0xea,
+	0xb1, 0xea, 0xf7, 0x04, 0x2f, 0x0b, 0x20, 0xa5, 0x93, 0x64,
 };
 
 /*
@@ -83,10 +86,9 @@ static const uint8_t fake_user_id[] = {
  * go run util/all_tests.go
  */
 static const uint8_t expected_positive_match_secret_for_empty_user_id[] = {
-	0x8d, 0xc4, 0x5b, 0xdf, 0x55, 0x1e, 0xa8, 0x72,
-	0xd6, 0xdd, 0xa1, 0x4c, 0xb8, 0xa1, 0x76, 0x2b,
-	0xde, 0x38, 0xd5, 0x03, 0xce, 0xe4, 0x74, 0x51,
-	0x63, 0x6c, 0x6a, 0x26, 0xa9, 0xb7, 0xfa, 0x68,
+	0x8d, 0xc4, 0x5b, 0xdf, 0x55, 0x1e, 0xa8, 0x72, 0xd6, 0xdd, 0xa1,
+	0x4c, 0xb8, 0xa1, 0x76, 0x2b, 0xde, 0x38, 0xd5, 0x03, 0xce, 0xe4,
+	0x74, 0x51, 0x63, 0x6c, 0x6a, 0x26, 0xa9, 0xb7, 0xfa, 0x68,
 };
 
 /*
@@ -94,20 +96,82 @@ static const uint8_t expected_positive_match_secret_for_empty_user_id[] = {
  * |fake_user_id| instead of all-zero user_id.
  */
 static const uint8_t expected_positive_match_secret_for_fake_user_id[] = {
-	0x0d, 0xf5, 0xac, 0x7c, 0xad, 0x37, 0x0a, 0x66,
-	0x2f, 0x71, 0xf6, 0xc6, 0xca, 0x8a, 0x41, 0x69,
-	0x8a, 0xd3, 0xcf, 0x0b, 0xc4, 0x5a, 0x5f, 0x4d,
-	0x54, 0xeb, 0x7b, 0xad, 0x5d, 0x1b, 0xbe, 0x30,
+	0x0d, 0xf5, 0xac, 0x7c, 0xad, 0x37, 0x0a, 0x66, 0x2f, 0x71, 0xf6,
+	0xc6, 0xca, 0x8a, 0x41, 0x69, 0x8a, 0xd3, 0xcf, 0x0b, 0xc4, 0x5a,
+	0x5f, 0x4d, 0x54, 0xeb, 0x7b, 0xad, 0x5d, 0x1b, 0xbe, 0x30,
 };
 
+test_static int test_get_ikm_failure_seed_not_set(void)
+{
+	uint8_t ikm;
+
+	TEST_ASSERT(fp_tpm_seed_is_set() == 0);
+	TEST_ASSERT(get_ikm(&ikm) == EC_ERROR_ACCESS_DENIED);
+	return EC_SUCCESS;
+}
+
+test_static int test_get_ikm_failure_cannot_get_rollback_secret(void)
+{
+	uint8_t ikm[CONFIG_ROLLBACK_SECRET_SIZE + FP_CONTEXT_TPM_BYTES];
+
+	/* Given that the tmp seed has been set. */
+	TEST_ASSERT(fp_tpm_seed_is_set());
+
+	/* GIVEN that reading the rollback secret will fail. */
+	mock_ctrl_rollback.get_secret_fail = true;
+
+	/* THEN get_ikm should fail. */
+	TEST_ASSERT(get_ikm(ikm) == EC_ERROR_HW_INTERNAL);
+
+	/*
+	 * Enable get_rollback_secret to succeed before returning from this
+	 * test function.
+	 */
+	mock_ctrl_rollback.get_secret_fail = false;
+
+	return EC_SUCCESS;
+}
+
+test_static int test_get_ikm_success(void)
+{
+	/*
+	 * Expected ikm is the concatenation of the rollback secret and the
+	 * seed from the TPM.
+	 */
+	uint8_t ikm[CONFIG_ROLLBACK_SECRET_SIZE + FP_CONTEXT_TPM_BYTES];
+	static const uint8_t expected_ikm[] = {
+		0xcf, 0xe3, 0x23, 0x76, 0x35, 0x04, 0xc2, 0x0f, 0x0d, 0xb6,
+		0x02, 0xa9, 0x68, 0xba, 0x2a, 0x61, 0x86, 0x2a, 0x85, 0xd1,
+		0xca, 0x09, 0x54, 0x8a, 0x6b, 0xe2, 0xe3, 0x38, 0xde, 0x5d,
+		0x59, 0x14, 0xd9, 0x71, 0xaf, 0xc4, 0xcd, 0x36, 0xe3, 0x60,
+		0xf8, 0x5a, 0xa0, 0xa6, 0x2c, 0xb3, 0xf5, 0xe2, 0xeb, 0xb9,
+		0xd8, 0x2f, 0xb5, 0x78, 0x5c, 0x79, 0x82, 0xce, 0x06, 0x3f,
+		0xcc, 0x23, 0xb9, 0xe7
+	};
+
+	/* GIVEN that the TPM seed has been set. */
+	TEST_ASSERT(fp_tpm_seed_is_set());
+
+	/* GIVEN that reading the rollback secret will succeed. */
+	mock_ctrl_rollback.get_secret_fail = false;
+
+	/* THEN get_ikm will succeed. */
+	TEST_ASSERT(get_ikm(ikm) == EC_SUCCESS);
+	TEST_ASSERT_ARRAY_EQ(ikm, expected_ikm,
+			     CONFIG_ROLLBACK_SECRET_SIZE +
+				     FP_CONTEXT_TPM_BYTES);
+
+	return EC_SUCCESS;
+}
+
 static int test_hkdf_expand_raw(const uint8_t *prk, size_t prk_size,
 				const uint8_t *info, size_t info_size,
 				const uint8_t *expected_okm, size_t okm_size)
 {
 	uint8_t actual_okm[okm_size];
 
-	TEST_ASSERT(hkdf_expand(actual_okm, okm_size, prk, prk_size,
-				info, info_size) == EC_SUCCESS);
+	TEST_ASSERT(hkdf_expand(actual_okm, okm_size, prk, prk_size, info,
+				info_size) == EC_SUCCESS);
 	TEST_ASSERT_ARRAY_EQ(expected_okm, actual_okm, okm_size);
 	return EC_SUCCESS;
 }
@@ -122,16 +186,14 @@ test_static int test_hkdf_expand(void)
 		0x22, 0xec, 0x84, 0x4a, 0xd7, 0xc2, 0xb3, 0xe5,
 	};
 	static const uint8_t info1[] = {
-		0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
-		0xf8, 0xf9,
+		0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9,
 	};
 	static const uint8_t expected_okm1[] = {
-		0x3c, 0xb2, 0x5f, 0x25, 0xfa, 0xac, 0xd5, 0x7a,
-		0x90, 0x43, 0x4f, 0x64, 0xd0, 0x36, 0x2f, 0x2a,
-		0x2d, 0x2d, 0x0a, 0x90, 0xcf, 0x1a, 0x5a, 0x4c,
-		0x5d, 0xb0, 0x2d, 0x56, 0xec, 0xc4, 0xc5, 0xbf,
-		0x34, 0x00, 0x72, 0x08, 0xd5, 0xb8, 0x87, 0x18,
-		0x58, 0x65,
+		0x3c, 0xb2, 0x5f, 0x25, 0xfa, 0xac, 0xd5, 0x7a, 0x90,
+		0x43, 0x4f, 0x64, 0xd0, 0x36, 0x2f, 0x2a, 0x2d, 0x2d,
+		0x0a, 0x90, 0xcf, 0x1a, 0x5a, 0x4c, 0x5d, 0xb0, 0x2d,
+		0x56, 0xec, 0xc4, 0xc5, 0xbf, 0x34, 0x00, 0x72, 0x08,
+		0xd5, 0xb8, 0x87, 0x18, 0x58, 0x65,
 	};
 	static const uint8_t prk2[] = {
 		0x06, 0xa6, 0xb8, 0x8c, 0x58, 0x53, 0x36, 0x1a,
@@ -140,28 +202,24 @@ test_static int test_hkdf_expand(void)
 		0x4a, 0x19, 0x3f, 0x40, 0xc1, 0x5f, 0xc2, 0x44,
 	};
 	static const uint8_t info2[] = {
-		0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7,
-		0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf,
-		0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
-		0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf,
-		0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
-		0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf,
-		0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
-		0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef,
-		0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
-		0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff,
+		0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, 0xb8, 0xb9,
+		0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, 0xc0, 0xc1, 0xc2, 0xc3,
+		0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd,
+		0xce, 0xcf, 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
+		0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, 0xe0, 0xe1,
+		0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xea, 0xeb,
+		0xec, 0xed, 0xee, 0xef, 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5,
+		0xf6, 0xf7, 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff,
 	};
 	static const uint8_t expected_okm2[] = {
-		0xb1, 0x1e, 0x39, 0x8d, 0xc8, 0x03, 0x27, 0xa1,
-		0xc8, 0xe7, 0xf7, 0x8c, 0x59, 0x6a, 0x49, 0x34,
-		0x4f, 0x01, 0x2e, 0xda, 0x2d, 0x4e, 0xfa, 0xd8,
-		0xa0, 0x50, 0xcc, 0x4c, 0x19, 0xaf, 0xa9, 0x7c,
-		0x59, 0x04, 0x5a, 0x99, 0xca, 0xc7, 0x82, 0x72,
-		0x71, 0xcb, 0x41, 0xc6, 0x5e, 0x59, 0x0e, 0x09,
-		0xda, 0x32, 0x75, 0x60, 0x0c, 0x2f, 0x09, 0xb8,
-		0x36, 0x77, 0x93, 0xa9, 0xac, 0xa3, 0xdb, 0x71,
-		0xcc, 0x30, 0xc5, 0x81, 0x79, 0xec, 0x3e, 0x87,
-		0xc1, 0x4c, 0x01, 0xd5, 0xc1, 0xf3, 0x43, 0x4f,
+		0xb1, 0x1e, 0x39, 0x8d, 0xc8, 0x03, 0x27, 0xa1, 0xc8, 0xe7,
+		0xf7, 0x8c, 0x59, 0x6a, 0x49, 0x34, 0x4f, 0x01, 0x2e, 0xda,
+		0x2d, 0x4e, 0xfa, 0xd8, 0xa0, 0x50, 0xcc, 0x4c, 0x19, 0xaf,
+		0xa9, 0x7c, 0x59, 0x04, 0x5a, 0x99, 0xca, 0xc7, 0x82, 0x72,
+		0x71, 0xcb, 0x41, 0xc6, 0x5e, 0x59, 0x0e, 0x09, 0xda, 0x32,
+		0x75, 0x60, 0x0c, 0x2f, 0x09, 0xb8, 0x36, 0x77, 0x93, 0xa9,
+		0xac, 0xa3, 0xdb, 0x71, 0xcc, 0x30, 0xc5, 0x81, 0x79, 0xec,
+		0x3e, 0x87, 0xc1, 0x4c, 0x01, 0xd5, 0xc1, 0xf3, 0x43, 0x4f,
 		0x1d, 0x87,
 	};
 	static const uint8_t prk3[] = {
@@ -171,52 +229,48 @@ test_static int test_hkdf_expand(void)
 		0xac, 0x43, 0x4c, 0x1c, 0x29, 0x3c, 0xcb, 0x04,
 	};
 	static const uint8_t expected_okm3[] = {
-		0x8d, 0xa4, 0xe7, 0x75, 0xa5, 0x63, 0xc1, 0x8f,
-		0x71, 0x5f, 0x80, 0x2a, 0x06, 0x3c, 0x5a, 0x31,
-		0xb8, 0xa1, 0x1f, 0x5c, 0x5e, 0xe1, 0x87, 0x9e,
-		0xc3, 0x45, 0x4e, 0x5f, 0x3c, 0x73, 0x8d, 0x2d,
-		0x9d, 0x20, 0x13, 0x95, 0xfa, 0xa4, 0xb6, 0x1a,
-		0x96, 0xc8,
+		0x8d, 0xa4, 0xe7, 0x75, 0xa5, 0x63, 0xc1, 0x8f, 0x71,
+		0x5f, 0x80, 0x2a, 0x06, 0x3c, 0x5a, 0x31, 0xb8, 0xa1,
+		0x1f, 0x5c, 0x5e, 0xe1, 0x87, 0x9e, 0xc3, 0x45, 0x4e,
+		0x5f, 0x3c, 0x73, 0x8d, 0x2d, 0x9d, 0x20, 0x13, 0x95,
+		0xfa, 0xa4, 0xb6, 0x1a, 0x96, 0xc8,
 	};
 	static uint8_t unused_output[SHA256_DIGEST_SIZE] = { 0 };
 
 	TEST_ASSERT(test_hkdf_expand_raw(prk1, sizeof(prk1), info1,
 					 sizeof(info1), expected_okm1,
-					 sizeof(expected_okm1))
-			    == EC_SUCCESS);
+					 sizeof(expected_okm1)) == EC_SUCCESS);
 	TEST_ASSERT(test_hkdf_expand_raw(prk2, sizeof(prk2), info2,
 					 sizeof(info2), expected_okm2,
-					 sizeof(expected_okm2))
-			    == EC_SUCCESS);
+					 sizeof(expected_okm2)) == EC_SUCCESS);
 	TEST_ASSERT(test_hkdf_expand_raw(prk3, sizeof(prk3), NULL, 0,
-					 expected_okm3, sizeof(expected_okm3))
-			    == EC_SUCCESS);
-
-	TEST_ASSERT(hkdf_expand(NULL, sizeof(unused_output), prk1,
-				sizeof(prk1), info1, sizeof(info1))
-			    == EC_ERROR_INVAL);
-	TEST_ASSERT(hkdf_expand(unused_output, sizeof(unused_output),
-				NULL, sizeof(prk1), info1, sizeof(info1))
-			    == EC_ERROR_INVAL);
-	TEST_ASSERT(hkdf_expand(unused_output, sizeof(unused_output),
-				prk1, sizeof(prk1), NULL, sizeof(info1))
-			    == EC_ERROR_INVAL);
+					 expected_okm3,
+					 sizeof(expected_okm3)) == EC_SUCCESS);
+
+	TEST_ASSERT(hkdf_expand(NULL, sizeof(unused_output), prk1, sizeof(prk1),
+				info1, sizeof(info1)) == EC_ERROR_INVAL);
+	TEST_ASSERT(hkdf_expand(unused_output, sizeof(unused_output), NULL,
+				sizeof(prk1), info1,
+				sizeof(info1)) == EC_ERROR_INVAL);
+	TEST_ASSERT(hkdf_expand(unused_output, sizeof(unused_output), prk1,
+				sizeof(prk1), NULL,
+				sizeof(info1)) == EC_ERROR_INVAL);
 	/* Info size too long. */
-	TEST_ASSERT(hkdf_expand(unused_output, sizeof(unused_output),
-				prk1, sizeof(prk1), info1, 1024)
-			    == EC_ERROR_INVAL);
+	TEST_ASSERT(hkdf_expand(unused_output, sizeof(unused_output), prk1,
+				sizeof(prk1), info1, 1024) == EC_ERROR_INVAL);
 	/* OKM size too big. */
-	TEST_ASSERT(hkdf_expand(unused_output, 256 * SHA256_DIGEST_SIZE,
-				prk1, sizeof(prk1), info1, sizeof(info1))
-			    == EC_ERROR_INVAL);
+	TEST_ASSERT(hkdf_expand(unused_output, 256 * SHA256_DIGEST_SIZE, prk1,
+				sizeof(prk1), info1,
+				sizeof(info1)) == EC_ERROR_INVAL);
 	return EC_SUCCESS;
 }
 
 test_static int test_derive_encryption_key_failure_seed_not_set(void)
 {
 	static uint8_t unused_key[SBP_ENC_KEY_LEN];
-	static const uint8_t unused_salt[FP_CONTEXT_ENCRYPTION_SALT_BYTES]
-		= { 0 };
+	static const uint8_t unused_salt[FP_CONTEXT_ENCRYPTION_SALT_BYTES] = {
+		0
+	};
 
 	/* GIVEN that the TPM seed is not set. */
 	if (fp_tpm_seed_is_set()) {
@@ -314,8 +368,9 @@ test_static int test_derive_encryption_key(void)
 test_static int test_derive_encryption_key_failure_rollback_fail(void)
 {
 	static uint8_t unused_key[SBP_ENC_KEY_LEN];
-	static const uint8_t unused_salt[FP_CONTEXT_ENCRYPTION_SALT_BYTES]
-		= { 0 };
+	static const uint8_t unused_salt[FP_CONTEXT_ENCRYPTION_SALT_BYTES] = {
+		0
+	};
 
 	/* GIVEN that reading the rollback secret will fail. */
 	mock_ctrl_rollback.get_secret_fail = true;
@@ -346,11 +401,10 @@ test_static int test_derive_positive_match_secret_fail_seed_not_set(void)
 
 	/* Deriving positive match secret will fail. */
 	TEST_ASSERT(derive_positive_match_secret(output,
-						 fake_positive_match_salt)
-		== EC_ERROR_ACCESS_DENIED);
+						 fake_positive_match_salt) ==
+		    EC_ERROR_ACCESS_DENIED);
 
 	return EC_SUCCESS;
-
 }
 
 test_static int test_derive_new_pos_match_secret(void)
@@ -367,30 +421,26 @@ test_static int test_derive_new_pos_match_secret(void)
 	 * GIVEN that the TPM seed is set, and reading the rollback secret will
 	 * succeed.
 	 */
-	TEST_ASSERT(
-		fp_tpm_seed_is_set() && !mock_ctrl_rollback.get_secret_fail);
+	TEST_ASSERT(fp_tpm_seed_is_set() &&
+		    !mock_ctrl_rollback.get_secret_fail);
 
 	/* GIVEN that the salt is not trivial. */
 	TEST_ASSERT(!bytes_are_trivial(fake_positive_match_salt,
 				       sizeof(fake_positive_match_salt)));
 
 	/* THEN the derivation will succeed. */
-	TEST_ASSERT(derive_positive_match_secret(output,
-						 fake_positive_match_salt)
-		== EC_SUCCESS);
+	TEST_ASSERT(derive_positive_match_secret(
+			    output, fake_positive_match_salt) == EC_SUCCESS);
 	TEST_ASSERT_ARRAY_EQ(
-		output,
-		expected_positive_match_secret_for_empty_user_id,
+		output, expected_positive_match_secret_for_empty_user_id,
 		sizeof(expected_positive_match_secret_for_empty_user_id));
 
 	/* Now change the user_id to be non-trivial. */
 	memcpy(user_id, fake_user_id, sizeof(fake_user_id));
-	TEST_ASSERT(derive_positive_match_secret(output,
-						 fake_positive_match_salt)
-		== EC_SUCCESS);
+	TEST_ASSERT(derive_positive_match_secret(
+			    output, fake_positive_match_salt) == EC_SUCCESS);
 	TEST_ASSERT_ARRAY_EQ(
-		output,
-		expected_positive_match_secret_for_fake_user_id,
+		output, expected_positive_match_secret_for_fake_user_id,
 		sizeof(expected_positive_match_secret_for_fake_user_id));
 	memset(user_id, 0, sizeof(user_id));
 
@@ -409,8 +459,8 @@ test_static int test_derive_positive_match_secret_fail_rollback_fail(void)
 
 	/* Deriving positive match secret will fail. */
 	TEST_ASSERT(derive_positive_match_secret(output,
-						 fake_positive_match_salt)
-		== EC_ERROR_HW_INTERNAL);
+						 fake_positive_match_salt) ==
+		    EC_ERROR_HW_INTERNAL);
 	mock_ctrl_rollback.get_secret_fail = false;
 
 	return EC_SUCCESS;
@@ -424,8 +474,94 @@ test_static int test_derive_positive_match_secret_fail_salt_trivial(void)
 	static const uint8_t salt[FP_CONTEXT_ENCRYPTION_SALT_BYTES] = { 0 };
 
 	/* THEN deriving positive match secret will fail. */
-	TEST_ASSERT(derive_positive_match_secret(output, salt)
-		== EC_ERROR_INVAL);
+	TEST_ASSERT(derive_positive_match_secret(output, salt) ==
+		    EC_ERROR_INVAL);
+	return EC_SUCCESS;
+}
+
+test_static int test_derive_positive_match_secret_fail_trivial_key_0x00(void)
+{
+	static uint8_t output[FP_POSITIVE_MATCH_SECRET_BYTES];
+
+	/* GIVEN that the user ID is set to a known value. */
+	memcpy(user_id, fake_user_id, sizeof(fake_user_id));
+
+	/*
+	 * GIVEN that the TPM seed is set, and reading the rollback secret will
+	 * succeed.
+	 */
+	TEST_ASSERT(fp_tpm_seed_is_set() &&
+		    !mock_ctrl_rollback.get_secret_fail);
+
+	/* GIVEN that the salt is not trivial. */
+	TEST_ASSERT(!bytes_are_trivial(fake_positive_match_salt,
+				       sizeof(fake_positive_match_salt)));
+
+	/* GIVEN that the sha256 output is trivial (0x00) */
+	mock_ctrl_fpsensor_crypto.output_type =
+		MOCK_CTRL_FPSENSOR_CRYPTO_SHA256_TYPE_ZEROS;
+
+	/* THEN the derivation will fail with EC_ERROR_HW_INTERNAL. */
+	TEST_ASSERT(derive_positive_match_secret(output,
+						 fake_positive_match_salt) ==
+		    EC_ERROR_HW_INTERNAL);
+
+	/* Now verify success is possible after reverting */
+
+	/* GIVEN that the sha256 output is non-trivial */
+	mock_ctrl_fpsensor_crypto.output_type =
+		MOCK_CTRL_FPSENSOR_CRYPTO_SHA256_TYPE_REAL;
+
+	/* THEN the derivation will succeed */
+	TEST_ASSERT(derive_positive_match_secret(
+			    output, fake_positive_match_salt) == EC_SUCCESS);
+
+	/* Clean up any mock changes */
+	mock_ctrl_fpsensor_crypto = MOCK_CTRL_DEFAULT_FPSENSOR_CRYPTO;
+
+	return EC_SUCCESS;
+}
+
+test_static int test_derive_positive_match_secret_fail_trivial_key_0xff(void)
+{
+	static uint8_t output[FP_POSITIVE_MATCH_SECRET_BYTES];
+
+	/* GIVEN that the user ID is set to a known value. */
+	memcpy(user_id, fake_user_id, sizeof(fake_user_id));
+
+	/*
+	 * GIVEN that the TPM seed is set, and reading the rollback secret will
+	 * succeed.
+	 */
+	TEST_ASSERT(fp_tpm_seed_is_set() &&
+		    !mock_ctrl_rollback.get_secret_fail);
+
+	/* GIVEN that the salt is not trivial. */
+	TEST_ASSERT(!bytes_are_trivial(fake_positive_match_salt,
+				       sizeof(fake_positive_match_salt)));
+
+	/* GIVEN that the sha256 output is trivial (0xFF) */
+	mock_ctrl_fpsensor_crypto.output_type =
+		MOCK_CTRL_FPSENSOR_CRYPTO_SHA256_TYPE_FF;
+
+	/* THEN the derivation will fail with EC_ERROR_HW_INTERNAL. */
+	TEST_ASSERT(derive_positive_match_secret(output,
+						 fake_positive_match_salt) ==
+		    EC_ERROR_HW_INTERNAL);
+
+	/* Now verify success is possible after reverting */
+
+	/* GIVEN that the sha256 output is non-trivial */
+	mock_ctrl_fpsensor_crypto.output_type =
+		MOCK_CTRL_FPSENSOR_CRYPTO_SHA256_TYPE_REAL;
+
+	/* THEN the derivation will succeed */
+	TEST_ASSERT(derive_positive_match_secret(
+			    output, fake_positive_match_salt) == EC_SUCCESS);
+
+	/* Clean up any mock changes */
+	mock_ctrl_fpsensor_crypto = MOCK_CTRL_DEFAULT_FPSENSOR_CRYPTO;
+
 	return EC_SUCCESS;
 }
 
@@ -435,8 +571,8 @@ static int test_enable_positive_match_secret_once(
 	const int8_t kIndexToEnable = 0;
 	timestamp_t now = get_time();
 
-	TEST_ASSERT(fp_enable_positive_match_secret(
-		kIndexToEnable, dumb_state) == EC_SUCCESS);
+	TEST_ASSERT(fp_enable_positive_match_secret(kIndexToEnable,
+						    dumb_state) == EC_SUCCESS);
 	TEST_ASSERT(dumb_state->template_matched == kIndexToEnable);
 	TEST_ASSERT(dumb_state->readable);
 	TEST_ASSERT(dumb_state->deadline.val == now.val + (5 * SECOND));
@@ -446,18 +582,19 @@ static int test_enable_positive_match_secret_once(
 
 test_static int test_enable_positive_match_secret(void)
 {
-	struct positive_match_secret_state dumb_state = {
-		.template_matched = FP_NO_SUCH_TEMPLATE,
-		.readable = false,
-		.deadline.val = 0,
-	};
-
-	TEST_ASSERT(test_enable_positive_match_secret_once(&dumb_state)
-		== EC_SUCCESS);
+	struct positive_match_secret_state
+		dumb_state = { .template_matched = FP_NO_SUCH_TEMPLATE,
+			       .readable = false,
+			       .deadline = {
+				       .val = 0,
+			       } };
+
+	TEST_ASSERT(test_enable_positive_match_secret_once(&dumb_state) ==
+		    EC_SUCCESS);
 
 	/* Trying to enable again before reading secret should fail. */
 	TEST_ASSERT(fp_enable_positive_match_secret(0, &dumb_state) ==
-		EC_ERROR_UNKNOWN);
+		    EC_ERROR_UNKNOWN);
 	TEST_ASSERT(dumb_state.template_matched == FP_NO_SUCH_TEMPLATE);
 	TEST_ASSERT(!dumb_state.readable);
 	TEST_ASSERT(dumb_state.deadline.val == 0);
@@ -467,14 +604,15 @@ test_static int test_enable_positive_match_secret(void)
 
 test_static int test_disable_positive_match_secret(void)
 {
-	struct positive_match_secret_state dumb_state = {
-		.template_matched = FP_NO_SUCH_TEMPLATE,
-		.readable = false,
-		.deadline.val = 0,
-	};
-
-	TEST_ASSERT(test_enable_positive_match_secret_once(&dumb_state)
-		== EC_SUCCESS);
+	struct positive_match_secret_state
+		dumb_state = { .template_matched = FP_NO_SUCH_TEMPLATE,
+			       .readable = false,
+			       .deadline = {
+				       .val = 0,
+			       } };
+
+	TEST_ASSERT(test_enable_positive_match_secret_once(&dumb_state) ==
+		    EC_SUCCESS);
 
 	fp_disable_positive_match_secret(&dumb_state);
 	TEST_ASSERT(dumb_state.template_matched == FP_NO_SUCH_TEMPLATE);
@@ -601,8 +739,7 @@ test_static int test_command_read_match_secret_unreadable(void)
 	positive_match_secret_state.readable = false;
 
 	/* EVEN IF the finger is just matched. */
-	TEST_ASSERT(positive_match_secret_state.template_matched
-		== params.fgr);
+	TEST_ASSERT(positive_match_secret_state.template_matched == params.fgr);
 
 	/* EVEN IF encryption salt is non-trivial. */
 	memcpy(fp_positive_match_salt[0], fake_positive_match_salt,
@@ -614,25 +751,29 @@ test_static int test_command_read_match_secret_unreadable(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	RUN_TEST(test_hkdf_expand);
 	RUN_TEST(test_derive_encryption_key_failure_seed_not_set);
 	RUN_TEST(test_derive_positive_match_secret_fail_seed_not_set);
-
+	RUN_TEST(test_get_ikm_failure_seed_not_set);
 	/*
 	 * Set the TPM seed here because it can only be set once and cannot be
 	 * cleared.
 	 */
 	ASSERT(fpsensor_state_mock_set_tpm_seed(default_fake_tpm_seed) ==
-		    EC_SUCCESS);
+	       EC_SUCCESS);
 
 	/* The following test requires TPM seed to be already set. */
+	RUN_TEST(test_get_ikm_failure_cannot_get_rollback_secret);
+	RUN_TEST(test_get_ikm_success);
 	RUN_TEST(test_derive_encryption_key);
 	RUN_TEST(test_derive_encryption_key_failure_rollback_fail);
 	RUN_TEST(test_derive_new_pos_match_secret);
 	RUN_TEST(test_derive_positive_match_secret_fail_rollback_fail);
 	RUN_TEST(test_derive_positive_match_secret_fail_salt_trivial);
+	RUN_TEST(test_derive_positive_match_secret_fail_trivial_key_0x00);
+	RUN_TEST(test_derive_positive_match_secret_fail_trivial_key_0xff);
 	RUN_TEST(test_enable_positive_match_secret);
 	RUN_TEST(test_disable_positive_match_secret);
 	RUN_TEST(test_command_read_match_secret);
diff --git a/test/fpsensor_hw.c b/test/fpsensor_hw.c
index f420001665..ff5b78ace2 100644
--- a/test/fpsensor_hw.c
+++ b/test/fpsensor_hw.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -32,8 +32,7 @@ test_static int test_fp_check_hwid(void)
 	return EC_SUCCESS;
 }
 
-
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	RUN_TEST(test_fp_check_hwid);
 	test_print_result();
diff --git a/test/fpsensor_hw.tasklist b/test/fpsensor_hw.tasklist
index 299cf25390..35fa6f24bd 100644
--- a/test/fpsensor_hw.tasklist
+++ b/test/fpsensor_hw.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/fpsensor_state.c b/test/fpsensor_state.c
index 3822fe49ab..0b61e1c2d4 100644
--- a/test/fpsensor_state.c
+++ b/test/fpsensor_state.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -186,7 +186,198 @@ test_static int test_fp_set_maintenance_mode(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+test_static int test_fp_command_read_match_secret_fail_fgr_less_than_zero(void)
+{
+	/* Create invalid param with fgr < 0 */
+	struct ec_params_fp_read_match_secret test_match_secret = {
+		.fgr = -1,
+	};
+
+	TEST_ASSERT(test_send_host_command(EC_CMD_FP_READ_MATCH_SECRET, 0,
+					   &test_match_secret,
+					   sizeof(test_match_secret), NULL,
+					   0) == EC_RES_INVALID_PARAM);
+
+	return EC_SUCCESS;
+}
+
+test_static int test_fp_command_read_match_secret_fail_fgr_large_than_max(void)
+{
+	/* Create invalid param with fgr = FP_MAX_FINGER_COUNT */
+	struct ec_params_fp_read_match_secret test_match_secret = {
+		.fgr = FP_MAX_FINGER_COUNT,
+	};
+
+	TEST_ASSERT(test_send_host_command(EC_CMD_FP_READ_MATCH_SECRET, 0,
+					   &test_match_secret,
+					   sizeof(test_match_secret), NULL,
+					   0) == EC_RES_INVALID_PARAM);
+	return EC_SUCCESS;
+}
+
+test_static int test_fp_command_read_match_secret_fail_timeout(void)
+{
+	/* Create valid param with 0 <= fgr < 5 */
+	struct ec_params_fp_read_match_secret test_match_secret_1 = {
+		.fgr = 1,
+	};
+
+	/* Disable positive secret match to create 0 deadline val */
+	fp_disable_positive_match_secret(&positive_match_secret_state);
+
+	TEST_ASSERT(positive_match_secret_state.deadline.val == 0);
+
+	TEST_ASSERT(test_send_host_command(EC_CMD_FP_READ_MATCH_SECRET, 0,
+					   &test_match_secret_1,
+					   sizeof(test_match_secret_1), NULL,
+					   0) == EC_RES_TIMEOUT);
+
+	return EC_SUCCESS;
+}
+
+test_static int test_fp_command_read_match_secret_unmatched_fgr(void)
+{
+	/* Create valid param with 0 <= fgr < 5 */
+	uint16_t matched_fgr = 1;
+	uint16_t unmatched_fgr = 2;
+	struct ec_params_fp_read_match_secret test_match_secret_1 = {
+		.fgr = matched_fgr,
+	};
+	/* Create positive secret match state with valid deadline value,
+	 * readable state, and wrong template matched
+	 */
+	struct positive_match_secret_state test_state = {
+		.deadline.val = 5000000,
+		.readable = true,
+		.template_matched = unmatched_fgr,
+	};
+
+	/* Test for the wrong matched finger state */
+	positive_match_secret_state = test_state;
+
+	TEST_ASSERT(test_send_host_command(EC_CMD_FP_READ_MATCH_SECRET, 0,
+					   &test_match_secret_1,
+					   sizeof(test_match_secret_1), NULL,
+					   0) == EC_RES_ACCESS_DENIED);
+
+	return EC_SUCCESS;
+}
+
+test_static int test_fp_command_read_match_secret_unreadable_state(void)
+{
+	/* Create valid param with 0 <= fgr < 5 */
+	uint16_t matched_fgr = 1;
+	struct ec_params_fp_read_match_secret test_match_secret_1 = {
+		.fgr = matched_fgr,
+	};
+	/*
+	 * Create positive secret match state with valid deadline value ,
+	 * unreadable state, and correct matched template
+	 */
+	struct positive_match_secret_state test_state = {
+		.deadline.val = 5000000,
+		.readable = false,
+		.template_matched = matched_fgr,
+	};
+
+	/* Test for the unreadable state */
+	positive_match_secret_state = test_state;
+
+	TEST_ASSERT(test_send_host_command(EC_CMD_FP_READ_MATCH_SECRET, 0,
+					   &test_match_secret_1,
+					   sizeof(test_match_secret_1), NULL,
+					   0) == EC_RES_ACCESS_DENIED);
+
+	return EC_SUCCESS;
+}
+
+test_static int test_fp_command_read_match_secret_derive_fail(void)
+{
+	struct ec_response_fp_read_match_secret response = { 0 };
+	/* Create valid param with 0 <= fgr < 5 */
+	uint16_t matched_fgr = 1;
+	struct ec_params_fp_read_match_secret test_match_secret_1 = {
+		.fgr = matched_fgr,
+	};
+	/* Create positive secret match state with valid deadline value,
+	 * readable state, and correct template matched
+	 */
+	struct positive_match_secret_state test_state_1 = {
+		.deadline.val = 5000000,
+		.readable = true,
+		.template_matched = matched_fgr,
+	};
+	positive_match_secret_state = test_state_1;
+	/* Set fp_positive_match_salt to the trivial value */
+	memcpy(fp_positive_match_salt, trivial_fp_positive_match_salt,
+	       sizeof(trivial_fp_positive_match_salt));
+
+	/* Test with the correct matched finger state and a trivial
+	 * fp_positive_match_salt
+	 */
+	TEST_ASSERT(test_send_host_command(
+			    EC_CMD_FP_READ_MATCH_SECRET, 0,
+			    &test_match_secret_1, sizeof(test_match_secret_1),
+			    &response, sizeof(response)) == EC_RES_ERROR);
+	return EC_SUCCESS;
+}
+
+test_static int test_fp_command_read_match_secret_derive_succeed(void)
+{
+	struct ec_response_fp_read_match_secret response = { 0 };
+	/* Create valid param with 0 <= fgr < 5 */
+	uint16_t matched_fgr = 1;
+	struct ec_params_fp_read_match_secret test_match_secret_1 = {
+		.fgr = matched_fgr,
+	};
+
+	/* Expected positive_match_secret same as  in test/fpsensor_crypto.c*/
+	static const uint8_t
+		expected_positive_match_secret_for_empty_user_id[] = {
+			0x8d, 0xc4, 0x5b, 0xdf, 0x55, 0x1e, 0xa8, 0x72,
+			0xd6, 0xdd, 0xa1, 0x4c, 0xb8, 0xa1, 0x76, 0x2b,
+			0xde, 0x38, 0xd5, 0x03, 0xce, 0xe4, 0x74, 0x51,
+			0x63, 0x6c, 0x6a, 0x26, 0xa9, 0xb7, 0xfa, 0x68,
+		};
+	/* Create positive secret match state with valid deadline value,
+	 * readable state, and correct template matched
+	 */
+	struct positive_match_secret_state test_state_1 = {
+		.deadline.val = 5000000,
+		.readable = true,
+		.template_matched = matched_fgr,
+	};
+	positive_match_secret_state = test_state_1;
+	/* Set fp_positive_match_salt to the trivial value */
+	memcpy(fp_positive_match_salt, default_fake_fp_positive_match_salt,
+	       sizeof(default_fake_fp_positive_match_salt));
+
+	TEST_ASSERT_ARRAY_EQ(
+		(uint8_t const *)fp_positive_match_salt,
+		(uint8_t const *)default_fake_fp_positive_match_salt,
+		sizeof(default_fake_fp_positive_match_salt));
+
+	/* Initialize an empty user_id to compare positive_match_secret */
+	memset(user_id, 0, sizeof(user_id));
+
+	TEST_ASSERT(fp_tpm_seed_is_set());
+	/* Test with the correct matched finger state and the default fake
+	 * fp_positive_match_salt
+	 */
+	TEST_ASSERT(test_send_host_command(
+			    EC_CMD_FP_READ_MATCH_SECRET, 0,
+			    &test_match_secret_1, sizeof(test_match_secret_1),
+			    &response, sizeof(response)) == EC_SUCCESS);
+
+	TEST_ASSERT_ARRAY_EQ(
+		response.positive_match_secret,
+		expected_positive_match_secret_for_empty_user_id,
+		sizeof(expected_positive_match_secret_for_empty_user_id));
+
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
 {
 	RUN_TEST(test_fp_enc_status_valid_flags);
 	RUN_TEST(test_fp_tpm_seed_not_set);
@@ -194,5 +385,12 @@ void run_test(int argc, char **argv)
 	RUN_TEST(test_set_fp_tpm_seed_again);
 	RUN_TEST(test_fp_set_sensor_mode);
 	RUN_TEST(test_fp_set_maintenance_mode);
+	RUN_TEST(test_fp_command_read_match_secret_fail_fgr_less_than_zero);
+	RUN_TEST(test_fp_command_read_match_secret_fail_fgr_large_than_max);
+	RUN_TEST(test_fp_command_read_match_secret_fail_timeout);
+	RUN_TEST(test_fp_command_read_match_secret_unmatched_fgr);
+	RUN_TEST(test_fp_command_read_match_secret_unreadable_state);
+	RUN_TEST(test_fp_command_read_match_secret_derive_fail);
+	RUN_TEST(test_fp_command_read_match_secret_derive_succeed);
 	test_print_result();
 }
diff --git a/test/genvif/Makefile b/test/genvif/Makefile
index 566b6bb042..a41e8308cc 100644
--- a/test/genvif/Makefile
+++ b/test/genvif/Makefile
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/test/genvif/genvif.sh b/test/genvif/genvif.sh
index 4a275ed2c1..b54d1de9eb 100755
--- a/test/genvif/genvif.sh
+++ b/test/genvif/genvif.sh
@@ -1,5 +1,5 @@
 #!/bin/bash -e
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/test/genvif/src/atomic.h b/test/genvif/src/atomic.h
index f2fa112e81..d58e57a1c2 100644
--- a/test/genvif/src/atomic.h
+++ b/test/genvif/src/atomic.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/genvif/src/board.h b/test/genvif/src/board.h
index 06122eeab9..c596b833e0 100644
--- a/test/genvif/src/board.h
+++ b/test/genvif/src/board.h
@@ -1,12 +1,12 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		65000
-#define PD_MAX_CURRENT_MA	3250
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW 65000
+#define PD_MAX_CURRENT_MA 3250
+#define PD_MAX_VOLTAGE_MV 20000
 
 /* Stubs required by the shared code */
 #define GPIO_PIN(port, index) (GPIO_##port, BIT(index))
diff --git a/test/genvif/src/config_chip.h b/test/genvif/src/config_chip.h
index f2fa112e81..d58e57a1c2 100644
--- a/test/genvif/src/config_chip.h
+++ b/test/genvif/src/config_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/genvif/src/fuzz_config.h b/test/genvif/src/fuzz_config.h
index f2fa112e81..d58e57a1c2 100644
--- a/test/genvif/src/fuzz_config.h
+++ b/test/genvif/src/fuzz_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/genvif/src/gpio.inc b/test/genvif/src/gpio.inc
index 6b96e08645..65e3066695 100644
--- a/test/genvif/src/gpio.inc
+++ b/test/genvif/src/gpio.inc
@@ -1,6 +1,6 @@
 /* -*- mode:c -*-
  *
- * Copyright 2022 The Chromium OS Authors. All rights reserved.
+ * Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/genvif/src/helper.c b/test/genvif/src/helper.c
index d604e63cfa..f3b5d97317 100644
--- a/test/genvif/src/helper.c
+++ b/test/genvif/src/helper.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,8 +7,8 @@
 #include "usb_pd.h"
 
 #ifndef CONFIG_USB_PD_CUSTOM_PDO
-#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\
-			 PDO_FIXED_COMM_CAP)
+#define PDO_FIXED_FLAGS \
+	(PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP | PDO_FIXED_COMM_CAP)
 
 const uint32_t pd_src_pdo[] = {
 	PDO_FIXED(5000, 1500, PDO_FIXED_FLAGS),
diff --git a/test/genvif/src/test_config.h b/test/genvif/src/test_config.h
index f2fa112e81..d58e57a1c2 100644
--- a/test/genvif/src/test_config.h
+++ b/test/genvif/src/test_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/genvif/src/timer.h b/test/genvif/src/timer.h
index f2fa112e81..d58e57a1c2 100644
--- a/test/genvif/src/timer.h
+++ b/test/genvif/src/timer.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/gyro_cal.c b/test/gyro_cal.c
index 3b55ab86d4..c8e8d30589 100644
--- a/test/gyro_cal.c
+++ b/test/gyro_cal.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -495,7 +495,7 @@ static int test_gyro_cal_remove_bias(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/gyro_cal.tasklist b/test/gyro_cal.tasklist
index 7d28eb5b64..7209a7441e 100644
--- a/test/gyro_cal.tasklist
+++ b/test/gyro_cal.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/gyro_cal_init_for_test.c b/test/gyro_cal_init_for_test.c
index 3963e5a207..0ba1a65e6b 100644
--- a/test/gyro_cal_init_for_test.c
+++ b/test/gyro_cal_init_for_test.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/gyro_cal_init_for_test.h b/test/gyro_cal_init_for_test.h
index e32040bab9..8af51b8e10 100644
--- a/test/gyro_cal_init_for_test.h
+++ b/test/gyro_cal_init_for_test.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/hooks.c b/test/hooks.c
index 8d12494688..0913f257b3 100644
--- a/test/hooks.c
+++ b/test/hooks.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -41,7 +41,7 @@ static void tick2_hook(void)
 	tick_count_seen_by_tick2 = tick_hook_count;
 }
 /* tick2_hook() prio means it should be called after tick_hook() */
-DECLARE_HOOK(HOOK_TICK, tick2_hook, HOOK_PRIO_DEFAULT+1);
+DECLARE_HOOK(HOOK_TICK, tick2_hook, HOOK_PRIO_DEFAULT + 1);
 
 static void second_hook(void)
 {
@@ -62,9 +62,7 @@ static void non_deferred_func(void)
 	deferred_call_count++;
 }
 
-static const struct deferred_data non_deferred_func_data = {
-	non_deferred_func
-};
+static const struct deferred_data non_deferred_func_data = { non_deferred_func };
 
 static int test_init_hook(void)
 {
@@ -85,8 +83,7 @@ static int test_ticks(void)
 	usleep(1300 * MSEC);
 
 	interval = tick_time[1].val - tick_time[0].val;
-	error_pct = (interval - HOOK_TICK_INTERVAL) * 100 /
-		    HOOK_TICK_INTERVAL;
+	error_pct = (interval - HOOK_TICK_INTERVAL) * 100 / HOOK_TICK_INTERVAL;
 	TEST_ASSERT_ABS_LESS(error_pct, 10);
 
 	interval = second_time[1].val - second_time[0].val;
@@ -159,7 +156,7 @@ static int test_repeating_deferred(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/hooks.tasklist b/test/hooks.tasklist
index da0ab6211a..100cb6b5bd 100644
--- a/test/hooks.tasklist
+++ b/test/hooks.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/host_command.c b/test/host_command.c
index ba1d4dcd96..e88ddc852c 100644
--- a/test/host_command.c
+++ b/test/host_command.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -8,6 +8,7 @@
 #include "common.h"
 #include "console.h"
 #include "host_command.h"
+#include "printf.h"
 #include "task.h"
 #include "test_util.h"
 #include "timer.h"
@@ -177,6 +178,7 @@ static int test_hostcmd_reuse_response_buffer(void)
 	struct ec_host_request *h = (struct ec_host_request *)resp_buf;
 	struct ec_params_hello *d =
 		(struct ec_params_hello *)(resp_buf + sizeof(*h));
+	char str_buf[hex_str_buf_size(BUFFER_SIZE)];
 
 	h->struct_version = 3;
 	h->checksum = 0;
@@ -201,16 +203,18 @@ static int test_hostcmd_reuse_response_buffer(void)
 
 	h->checksum = calculate_checksum(resp_buf, pkt.request_size);
 
-	ccprintf("\nBuffer contents before process 0x%ph\n",
-			HEX_BUF(resp_buf, BUFFER_SIZE));
+	snprintf_hex_buffer(str_buf, sizeof(str_buf),
+			    HEX_BUF(resp_buf, BUFFER_SIZE));
+	ccprintf("\nBuffer contents before process 0x%s\n", str_buf);
 	host_packet_receive(&pkt);
 	task_wait_event(-1);
 
-	ccprintf("\nBuffer contents after process 0x%ph\n",
-			HEX_BUF(resp_buf, BUFFER_SIZE));
+	snprintf_hex_buffer(str_buf, sizeof(str_buf),
+			    HEX_BUF(resp_buf, BUFFER_SIZE));
+	ccprintf("\nBuffer contents after process 0x%s\n", str_buf);
 
-	TEST_EQ(calculate_checksum(resp_buf,
-				sizeof(*resp) + resp->data_len), 0, "%d");
+	TEST_EQ(calculate_checksum(resp_buf, sizeof(*resp) + resp->data_len), 0,
+		"%d");
 	TEST_EQ(resp->result, EC_RES_SUCCESS, "%d");
 	TEST_EQ(r->out_data, 0x12243648, "0x%x");
 
@@ -239,6 +243,7 @@ static void hostcmd_fill_chip_info(void)
 static int test_hostcmd_clears_unused_data(void)
 {
 	int i, found_null;
+	char str_buf[hex_str_buf_size(BUFFER_SIZE)];
 
 	/* Set the buffer to junk and ensure that is gets cleared */
 	memset(resp_buf, 0xAA, BUFFER_SIZE);
@@ -246,11 +251,12 @@ static int test_hostcmd_clears_unused_data(void)
 
 	hostcmd_send();
 
-	ccprintf("\nBuffer contents 0x%ph\n",
-			HEX_BUF(resp_buf, BUFFER_SIZE));
+	snprintf_hex_buffer(str_buf, sizeof(str_buf),
+			    HEX_BUF(resp_buf, BUFFER_SIZE));
+	ccprintf("\nBuffer contents 0x%s\n", str_buf);
 
-	TEST_EQ(calculate_checksum(resp_buf,
-				sizeof(*resp) + resp->data_len), 0, "%d");
+	TEST_EQ(calculate_checksum(resp_buf, sizeof(*resp) + resp->data_len), 0,
+		"%d");
 	TEST_EQ(resp->result, EC_RES_SUCCESS, "%d");
 
 	/* Ensure partial strings have 0s after the NULL byte */
@@ -300,7 +306,7 @@ static int test_hostcmd_clears_unused_data(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	wait_for_task_started();
 	test_reset();
diff --git a/test/host_command.tasklist b/test/host_command.tasklist
index da0ab6211a..100cb6b5bd 100644
--- a/test/host_command.tasklist
+++ b/test/host_command.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/i2c_bitbang.c b/test/i2c_bitbang.c
index dd84c0b83a..6916110b5c 100644
--- a/test/i2c_bitbang.c
+++ b/test/i2c_bitbang.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,15 +10,11 @@
 #include "test_util.h"
 #include "util.h"
 
-const struct i2c_port_t i2c_bitbang_ports[] = {
-	{
-		.name = "",
-		.port = 0,
-		.kbps = 100,
-		.scl = GPIO_I2C_SCL,
-		.sda = GPIO_I2C_SDA
-	}
-};
+const struct i2c_port_t i2c_bitbang_ports[] = { { .name = "",
+						  .port = 0,
+						  .kbps = 100,
+						  .scl = GPIO_I2C_SCL,
+						  .sda = GPIO_I2C_SDA } };
 const unsigned int i2c_bitbang_ports_used = 1;
 
 struct pin_state {
@@ -29,7 +25,7 @@ int history_count;
 
 void reset_state(void)
 {
-	history[0] = (struct pin_state) {1, 1};
+	history[0] = (struct pin_state){ 1, 1 };
 	history_count = 1;
 	bitbang_set_started(0);
 }
@@ -48,7 +44,7 @@ void gpio_set_level(enum gpio_signal signal, int level)
 		new.scl = level;
 
 	if (new.scl != history[history_count - 1].scl ||
-			new.sda != history[history_count - 1].sda)
+	    new.sda != history[history_count - 1].sda)
 		history[history_count++] = new;
 }
 
@@ -66,12 +62,12 @@ static int test_i2c_start_stop(void)
 {
 	struct pin_state expected[] = {
 		/* start */
-		{1, 1},
-		{1, 0},
-		{0, 0},
+		{ 1, 1 },
+		{ 1, 0 },
+		{ 0, 0 },
 		/* stop */
-		{1, 0},
-		{1, 1},
+		{ 1, 0 },
+		{ 1, 1 },
 	};
 	int i;
 
@@ -94,14 +90,14 @@ static int test_i2c_repeated_start(void)
 {
 	struct pin_state expected[] = {
 		/* start */
-		{1, 1},
-		{1, 0},
-		{0, 0},
+		{ 1, 1 },
+		{ 1, 0 },
+		{ 0, 0 },
 		/* repeated start */
-		{0, 1},
-		{1, 1},
-		{1, 0},
-		{0, 0},
+		{ 0, 1 },
+		{ 1, 1 },
+		{ 1, 0 },
+		{ 0, 0 },
 	};
 	int i;
 
@@ -124,47 +120,47 @@ static int test_i2c_write(void)
 {
 	struct pin_state expected[] = {
 		/* start */
-		{1, 1},
-		{1, 0},
-		{0, 0},
+		{ 1, 1 },
+		{ 1, 0 },
+		{ 0, 0 },
 		/* bit 7: 0 */
-		{1, 0},
-		{0, 0},
+		{ 1, 0 },
+		{ 0, 0 },
 		/* bit 6: 1 */
-		{0, 1},
-		{1, 1},
-		{0, 1},
+		{ 0, 1 },
+		{ 1, 1 },
+		{ 0, 1 },
 		/* bit 5: 0 */
-		{0, 0},
-		{1, 0},
-		{0, 0},
+		{ 0, 0 },
+		{ 1, 0 },
+		{ 0, 0 },
 		/* bit 4: 1 */
-		{0, 1},
-		{1, 1},
-		{0, 1},
+		{ 0, 1 },
+		{ 1, 1 },
+		{ 0, 1 },
 		/* bit 3: 0 */
-		{0, 0},
-		{1, 0},
-		{0, 0},
+		{ 0, 0 },
+		{ 1, 0 },
+		{ 0, 0 },
 		/* bit 2: 1 */
-		{0, 1},
-		{1, 1},
-		{0, 1},
+		{ 0, 1 },
+		{ 1, 1 },
+		{ 0, 1 },
 		/* bit 1: 1 */
-		{1, 1},
-		{0, 1},
+		{ 1, 1 },
+		{ 0, 1 },
 		/* bit 0: 0 */
-		{0, 0},
-		{1, 0},
-		{0, 0},
+		{ 0, 0 },
+		{ 1, 0 },
+		{ 0, 0 },
 		/* read bit */
-		{0, 1},
-		{1, 1},
-		{0, 1},
+		{ 0, 1 },
+		{ 1, 1 },
+		{ 0, 1 },
 		/* stop */
-		{0, 0},
-		{1, 0},
-		{1, 1},
+		{ 0, 0 },
+		{ 1, 0 },
+		{ 1, 1 },
 	};
 	int i, ret;
 
@@ -186,7 +182,7 @@ static int test_i2c_write(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/i2c_bitbang.tasklist b/test/i2c_bitbang.tasklist
index 9fc1a80f4d..844ddb6c10 100644
--- a/test/i2c_bitbang.tasklist
+++ b/test/i2c_bitbang.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/inductive_charging.c b/test/inductive_charging.c
index d487e171fd..a5b23d1d8c 100644
--- a/test/inductive_charging.c
+++ b/test/inductive_charging.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -17,8 +17,8 @@
 
 #define START_CHARGE_DELAY 5000 /* ms */
 #define MONITOR_CHARGE_DONE_DELAY 1000 /* ms */
-#define TEST_CHECK_CHARGE_DELAY (START_CHARGE_DELAY + \
-				 MONITOR_CHARGE_DONE_DELAY + 500) /* ms */
+#define TEST_CHECK_CHARGE_DELAY \
+	(START_CHARGE_DELAY + MONITOR_CHARGE_DONE_DELAY + 500) /* ms */
 
 static void wait_for_lid_debounce(void)
 {
@@ -157,7 +157,7 @@ static int test_debounce_charge_done(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/inductive_charging.tasklist b/test/inductive_charging.tasklist
index f5c894ccaf..dbe560d4aa 100644
--- a/test/inductive_charging.tasklist
+++ b/test/inductive_charging.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/interrupt.c b/test/interrupt.c
index ca98309e1f..efd8b47a34 100644
--- a/test/interrupt.c
+++ b/test/interrupt.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -88,7 +88,7 @@ static int test_wait_for_ready(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/interrupt.tasklist b/test/interrupt.tasklist
index da0ab6211a..100cb6b5bd 100644
--- a/test/interrupt.tasklist
+++ b/test/interrupt.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/irq_locking.c b/test/irq_locking.c
index 6d08b1175d..c46b94e8c5 100644
--- a/test/irq_locking.c
+++ b/test/irq_locking.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -71,7 +71,7 @@ void before_test(void)
 	interrupt_enable_count = 0;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/irq_locking.tasklist b/test/irq_locking.tasklist
index 2d7fbb0541..5659b9033d 100644
--- a/test/irq_locking.tasklist
+++ b/test/irq_locking.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/is_enabled.c b/test/is_enabled.c
index fe93bafc31..d54f709bf9 100644
--- a/test/is_enabled.c
+++ b/test/is_enabled.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -7,8 +7,8 @@
 #include "common.h"
 #include "test_util.h"
 
-#undef	CONFIG_UNDEFINED
-#define	CONFIG_BLANK
+#undef CONFIG_UNDEFINED
+#define CONFIG_BLANK
 
 static int test_undef(void)
 {
@@ -24,7 +24,7 @@ static int test_blank(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/is_enabled.tasklist b/test/is_enabled.tasklist
index 5ffe662d01..2d4595f76a 100644
--- a/test/is_enabled.tasklist
+++ b/test/is_enabled.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/is_enabled_error.c b/test/is_enabled_error.c
index 3fcd80afe0..b5d6994c4d 100644
--- a/test/is_enabled_error.c
+++ b/test/is_enabled_error.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -7,7 +7,7 @@
 #include "common.h"
 #include "test_util.h"
 
-#define	CONFIG_VALUE		TEST_VALUE
+#define CONFIG_VALUE TEST_VALUE
 
 static int test_invalid_value(void)
 {
@@ -17,7 +17,7 @@ static int test_invalid_value(void)
 	return EC_ERROR_UNKNOWN;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/is_enabled_error.sh b/test/is_enabled_error.sh
index 1e5407f31f..c99c4f0e26 100644
--- a/test/is_enabled_error.sh
+++ b/test/is_enabled_error.sh
@@ -1,5 +1,5 @@
 #!/bin/bash -e
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/test/is_enabled_error.tasklist b/test/is_enabled_error.tasklist
index 5ffe662d01..2d4595f76a 100644
--- a/test/is_enabled_error.tasklist
+++ b/test/is_enabled_error.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/kasa.c b/test/kasa.c
index 6dea8a20e7..23968faf7c 100644
--- a/test/kasa.c
+++ b/test/kasa.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -62,7 +62,7 @@ static int test_kasa_calculate(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/kasa.tasklist b/test/kasa.tasklist
index 0e3696c3f0..d3fcf83121 100644
--- a/test/kasa.tasklist
+++ b/test/kasa.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/kb_8042.c b/test/kb_8042.c
index 9705b506fe..e7d7690cff 100644
--- a/test/kb_8042.c
+++ b/test/kb_8042.c
@@ -1,10 +1,12 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Tests for keyboard MKBP protocol
  */
 
+#include <stdbool.h>
+#include "atkbd_protocol.h"
 #include "common.h"
 #include "console.h"
 #include "ec_commands.h"
@@ -15,16 +17,28 @@
 #include "keyboard_scan.h"
 #include "lpc.h"
 #include "power_button.h"
+#include "queue.h"
 #include "system.h"
+#include "task.h"
 #include "test_util.h"
 #include "timer.h"
 #include "util.h"
 
-static const char *action[2] = {"release", "press"};
+static const char *action[2] = { "release", "press" };
 
-#define BUF_SIZE 16
-static char lpc_char_buf[BUF_SIZE];
-static unsigned int lpc_char_cnt;
+/*
+ * This simulates the hardware output buffer. The x86 will read the output
+ * buffer from IOx60. Since we don't have actual hardware, we emulate the
+ * output buffer.
+ */
+static volatile struct {
+	bool full;
+	uint8_t data;
+	bool irq;
+	bool from_aux;
+} output_buffer;
+
+static struct queue const aux_to_device = QUEUE_NULL(16, uint8_t);
 
 /*****************************************************************************/
 /* Mock functions */
@@ -34,97 +48,517 @@ int lid_is_open(void)
 	return 1;
 }
 
+int lpc_keyboard_has_char(void)
+{
+	return output_buffer.full;
+}
+
 void lpc_keyboard_put_char(uint8_t chr, int send_irq)
 {
-	lpc_char_buf[lpc_char_cnt++] = chr;
+	if (lpc_keyboard_has_char()) {
+		ccprintf("%s:%s ERROR: output buffer is full!\n", __FILE__,
+			 __func__);
+		/* We can't fail the test, but we can abort!. */
+		exit(1);
+	}
+
+	output_buffer.data = chr;
+	output_buffer.irq = send_irq;
+	output_buffer.from_aux = false;
+	output_buffer.full = true;
+}
+
+void send_aux_data_to_device(uint8_t data)
+{
+	if (queue_add_unit(&aux_to_device, &data) == 0) {
+		ccprintf("%s: ERROR: aux_to_device queue is full!\n", __FILE__);
+		/* We can't fail the test, but we can abort!. */
+		exit(1);
+	}
 }
 
+void lpc_aux_put_char(uint8_t chr, int send_irq)
+{
+	if (lpc_keyboard_has_char()) {
+		ccprintf("%s:%s ERROR: output buffer is full!\n", __FILE__,
+			 __func__);
+		/* We can't fail the test, but we can abort!. */
+		exit(1);
+	}
+
+	output_buffer.data = chr;
+	output_buffer.irq = send_irq;
+	output_buffer.from_aux = true;
+	output_buffer.full = true;
+}
 /*****************************************************************************/
 /* Test utilities */
 
+/*
+ * This is a bit tricky, the second parameter to _Static_assert must be a string
+ * literal, so we use that property to assert x is a string literal.
+ */
+#define ASSERT_IS_STRING_LITERAL(x) _Static_assert(true, x)
+
+int _wait_for_data(int delay_ms)
+{
+	while (!output_buffer.full) {
+		if (delay_ms <= 0)
+			break;
+		delay_ms -= 1;
+
+		msleep(1);
+	}
+	TEST_ASSERT(output_buffer.full);
+
+	return EC_SUCCESS;
+}
+
+#define WAIT_FOR_DATA(d) TEST_EQ(_wait_for_data(d), EC_SUCCESS, "%d")
+
+#define VERIFY_LPC_CHAR_ALL(s, d, aux, _irq)                               \
+	do {                                                               \
+		const uint8_t *expected = s;                               \
+		ASSERT_IS_STRING_LITERAL(s);                               \
+		for (int _i = 0; _i < sizeof(s) - 1; ++_i) {               \
+			WAIT_FOR_DATA(d);                                  \
+			TEST_EQ(output_buffer.from_aux, aux, "%d");        \
+			if (_irq >= 0)                                     \
+				TEST_EQ(output_buffer.irq,                 \
+					_irq > 0 ? true : false, "%d");    \
+			TEST_EQ(output_buffer.data, expected[_i], "0x%x"); \
+			output_buffer.full = false;                        \
+			task_wake(TASK_ID_KEYPROTO);                       \
+		}                                                          \
+	} while (0)
+
+#define VERIFY_LPC_CHAR_DELAY(s, d)                    \
+	do {                                           \
+		msleep(d);                             \
+		VERIFY_LPC_CHAR_ALL(s, 10, false, -1); \
+	} while (0)
+#define VERIFY_LPC_CHAR(s) VERIFY_LPC_CHAR_ALL(s, 30, false, -1)
+#define VERIFY_ATKBD_ACK(s) VERIFY_LPC_CHAR("\xfa") /* ATKBD_RET_ACK */
+
+#define VERIFY_NO_CHAR()                              \
+	do {                                          \
+		msleep(30);                           \
+		TEST_EQ(output_buffer.full, 0, "%d"); \
+	} while (0)
+
+#define VERIFY_AUX_TO_HOST(expected_data, expected_irq) \
+	VERIFY_LPC_CHAR_ALL(expected_data, 30, true, expected_irq)
+
+#define VERIFY_AUX_TO_HOST_EMPTY VERIFY_NO_CHAR
+
+#define VERIFY_AUX_TO_DEVICE(expected_data)                                   \
+	do {                                                                  \
+		uint8_t _data;                                                \
+		msleep(30);                                                   \
+		TEST_EQ(queue_remove_unit(&aux_to_device, &_data), (size_t)1, \
+			"%zd");                                               \
+		TEST_EQ(_data, expected_data, "%#x");                         \
+	} while (0)
+
+#define VERIFY_AUX_TO_DEVICE_EMPTY()                         \
+	do {                                                 \
+		msleep(30);                                  \
+		TEST_ASSERT(queue_is_empty(&aux_to_device)); \
+	} while (0)
+
 static void press_key(int c, int r, int pressed)
 {
 	ccprintf("Input %s (%d, %d)\n", action[pressed], c, r);
 	keyboard_state_changed(r, c, pressed);
 }
 
-static void enable_keystroke(int enabled)
+static int _enable_keystroke(int enabled)
 {
-	uint8_t data = enabled ? I8042_CMD_ENABLE : I8042_CMD_RESET_DIS;
+	uint8_t data = enabled ? ATKBD_CMD_ENABLE : ATKBD_CMD_RESET_DIS;
 	keyboard_host_write(data, 0);
-	msleep(30);
+	VERIFY_ATKBD_ACK();
+
+	return EC_SUCCESS;
 }
+#define ENABLE_KEYSTROKE(enabled) \
+	TEST_EQ(_enable_keystroke(enabled), EC_SUCCESS, "%d")
 
-static void reset_8042(void)
+static int _reset_8042(void)
 {
-	keyboard_host_write(I8042_CMD_RESET_DEF, 0);
-	msleep(30);
+	keyboard_host_write(ATKBD_CMD_RESET_DEF, 0);
+	VERIFY_ATKBD_ACK();
+
+	return EC_SUCCESS;
 }
+#define RESET_8042() TEST_EQ(_reset_8042(), EC_SUCCESS, "%d")
 
-static void set_typematic(uint8_t val)
+static int _set_typematic(uint8_t val)
 {
-	keyboard_host_write(I8042_CMD_SETREP, 0);
-	msleep(30);
+	keyboard_host_write(ATKBD_CMD_SETREP, 0);
+	VERIFY_ATKBD_ACK();
+
 	keyboard_host_write(val, 0);
-	msleep(30);
+	VERIFY_ATKBD_ACK();
+
+	return EC_SUCCESS;
 }
+#define SET_TYPEMATIC(val) TEST_EQ(_set_typematic(val), EC_SUCCESS, "%d")
 
-static void set_scancode(uint8_t s)
+static int _set_scancode(uint8_t s)
 {
-	keyboard_host_write(I8042_CMD_SSCANSET, 0);
-	msleep(30);
+	keyboard_host_write(ATKBD_CMD_SSCANSET, 0);
+	VERIFY_ATKBD_ACK();
+
 	keyboard_host_write(s, 0);
-	msleep(30);
+	VERIFY_ATKBD_ACK();
+
+	return EC_SUCCESS;
 }
+#define SET_SCANCODE(s) TEST_EQ(_set_scancode(s), EC_SUCCESS, "%d")
 
-static void write_cmd_byte(uint8_t val)
+static int _write_cmd_byte(uint8_t val)
 {
 	keyboard_host_write(I8042_WRITE_CMD_BYTE, 1);
-	msleep(30);
+	VERIFY_NO_CHAR();
+
 	keyboard_host_write(val, 0);
-	msleep(30);
+	VERIFY_NO_CHAR();
+
+	return EC_SUCCESS;
 }
+#define WRITE_CMD_BYTE(val) TEST_EQ(_write_cmd_byte(val), EC_SUCCESS, "%d")
 
-static uint8_t read_cmd_byte(void)
+static int _read_cmd_byte(uint8_t *cmd)
 {
-	lpc_char_cnt = 0;
 	keyboard_host_write(I8042_READ_CMD_BYTE, 1);
-	msleep(30);
-	return lpc_char_buf[0];
+	WAIT_FOR_DATA(30);
+	TEST_EQ(output_buffer.from_aux, 0, "%d");
+
+	*cmd = output_buffer.data;
+	output_buffer.full = false;
+	task_wake(TASK_ID_KEYPROTO);
+
+	return EC_SUCCESS;
+}
+#define READ_CMD_BYTE()                                          \
+	({                                                       \
+		uint8_t cmd;                                     \
+		TEST_EQ(_read_cmd_byte(&cmd), EC_SUCCESS, "%d"); \
+		cmd;                                             \
+	})
+
+/*
+ * We unfortunately don't have an Input Buffer Full (IBF). Instead we
+ * directly write to the task's input queue. Ideally we would have an
+ * emulator that emulates the 8042 input/output buffers.
+ */
+#define i8042_write_cmd(cmd) keyboard_host_write(cmd, 1)
+#define i8042_write_data(data) keyboard_host_write(data, 0)
+
+/*****************************************************************************/
+/* Tests */
+
+void before_test(void)
+{
+	/* Make sure all tests start with the controller in the same state */
+	_write_cmd_byte(I8042_XLATE | I8042_AUX_DIS | I8042_KBD_DIS);
+}
+
+void after_test(void)
+{
+	if (output_buffer.full) {
+		ccprintf("%s:%s ERROR: output buffer is not empty!\n", __FILE__,
+			 __func__);
+		/* We can't fail the test, but we can abort!. */
+		exit(1);
+	}
 }
 
-static int __verify_lpc_char(char *arr, unsigned int sz, int delay_ms)
+static int test_8042_aux_loopback(void)
 {
-	int i;
+	/* Disable all IRQs */
+	WRITE_CMD_BYTE(0);
+
+	i8042_write_cmd(I8042_ECHO_MOUSE);
+	i8042_write_data(0x01);
+	VERIFY_AUX_TO_HOST("\x01", 0);
+
+	/* Enable AUX IRQ */
+	WRITE_CMD_BYTE(I8042_ENIRQ12);
+
+	i8042_write_cmd(I8042_ECHO_MOUSE);
+	i8042_write_data(0x02);
+	VERIFY_AUX_TO_HOST("\x02", 1);
 
-	lpc_char_cnt = 0;
-	for (i = 0; i < sz; ++i)
-		lpc_char_buf[i] = 0;
-	msleep(delay_ms);
-	TEST_ASSERT_ARRAY_EQ(arr, lpc_char_buf, sz);
 	return EC_SUCCESS;
 }
 
-#define VERIFY_LPC_CHAR(s) \
-	TEST_ASSERT(__verify_lpc_char(s, strlen(s), 30) == EC_SUCCESS)
-#define VERIFY_LPC_CHAR_DELAY(s, t) \
-	TEST_ASSERT(__verify_lpc_char(s, strlen(s), t) == EC_SUCCESS)
+static int test_8042_aux_two_way_communication(void)
+{
+	/* Enable AUX IRQ */
+	WRITE_CMD_BYTE(I8042_ENIRQ12);
+
+	i8042_write_cmd(I8042_SEND_TO_MOUSE);
+	i8042_write_data(0x01);
+	/* No response expected from the 8042 controller*/
+	VERIFY_AUX_TO_HOST_EMPTY();
+	VERIFY_AUX_TO_DEVICE(0x01);
+
+	/* Simulate the AUX device sending a response to the host */
+	send_aux_data_to_host_interrupt(0x02);
+	VERIFY_AUX_TO_HOST("\x02", 1);
+
+	return EC_SUCCESS;
+}
 
-static int __verify_no_char(void)
+static int test_8042_aux_inhibit(void)
 {
-	lpc_char_cnt = 0;
-	msleep(30);
-	TEST_CHECK(lpc_char_cnt == 0);
+	/* Enable AUX IRQ, but inhibit the AUX device from sending data. */
+	WRITE_CMD_BYTE(I8042_ENIRQ12 | I8042_AUX_DIS);
+
+	/* Simulate the AUX device sending a response to the host */
+	send_aux_data_to_host_interrupt(0x02);
+	VERIFY_AUX_TO_HOST_EMPTY();
+
+	/* Stop inhibiting the AUX device */
+	WRITE_CMD_BYTE(I8042_ENIRQ12);
+	/*
+	 * This is wrong. When the CLK is inhibited the device will queue up
+	 * events/scan codes in it's internal buffer. Once the inhibit is
+	 * released, the device will start clocking out the data. So in this
+	 * test we should be receiving a 0x02 byte, but we don't.
+	 *
+	 * In order to fix this we either need to plumb an inhibit function
+	 * to the AUX PS/2 controller so it can hold the CLK line low, and thus
+	 * tell the AUX device to buffer. Or, we can have the 8042 controller
+	 * buffer the data internally and start replying it when the device is
+	 * no longer inhibited.
+	 */
+	VERIFY_AUX_TO_HOST_EMPTY();
+
+	return EC_SUCCESS;
 }
 
-#define VERIFY_NO_CHAR() TEST_ASSERT(__verify_no_char() == EC_SUCCESS)
+static int test_8042_aux_controller_commands(void)
+{
+	uint8_t ctrl;
 
-/*****************************************************************************/
-/* Tests */
+	/* Start with empty controller flags. i.e., AUX Enabled */
+	WRITE_CMD_BYTE(0);
+
+	/* Send the AUX DISABLE command and verify the ctrl got updated */
+	i8042_write_cmd(I8042_DIS_MOUSE);
+	ctrl = READ_CMD_BYTE();
+	TEST_ASSERT(ctrl & I8042_AUX_DIS);
+
+	/* Send the AUX ENABLE command and verify the ctrl got updated */
+	i8042_write_cmd(I8042_ENA_MOUSE);
+	ctrl = READ_CMD_BYTE();
+	TEST_ASSERT(!(ctrl & I8042_AUX_DIS));
+
+	return EC_SUCCESS;
+}
+
+static int test_8042_aux_test_command(void)
+{
+	i8042_write_cmd(I8042_TEST_MOUSE);
+
+	VERIFY_LPC_CHAR("\x00");
+
+	return EC_SUCCESS;
+}
+
+static int test_8042_self_test(void)
+{
+	i8042_write_cmd(I8042_RESET_SELF_TEST);
+	VERIFY_LPC_CHAR("\x55");
+
+	return EC_SUCCESS;
+}
+
+static int test_8042_keyboard_test_command(void)
+{
+	i8042_write_cmd(I8042_TEST_KB_PORT);
+	VERIFY_LPC_CHAR("\x00"); /* Data and Clock are not stuck */
+
+	return EC_SUCCESS;
+}
+
+static int test_8042_keyboard_controller_commands(void)
+{
+	uint8_t ctrl;
+
+	/* Start with empty controller flags. i.e., Keyboard Enabled */
+	WRITE_CMD_BYTE(0);
+
+	/* Send the Keyboard DISABLE command and verify the ctrl got updated */
+	i8042_write_cmd(I8042_DIS_KB);
+	ctrl = READ_CMD_BYTE();
+	TEST_ASSERT(ctrl & I8042_KBD_DIS);
+
+	/* Send the Keyboard ENABLE command and verify the ctrl got updated */
+	i8042_write_cmd(I8042_ENA_KB);
+	ctrl = READ_CMD_BYTE();
+	TEST_ASSERT(!(ctrl & I8042_KBD_DIS));
+
+	return EC_SUCCESS;
+}
+
+static int test_8042_keyboard_key_pressed_while_inhibited(void)
+{
+	ENABLE_KEYSTROKE(1);
+
+	/* Inhibit the keyboard device from sending data. */
+	WRITE_CMD_BYTE(I8042_XLATE | I8042_KBD_DIS);
+
+	/* Simulate a keypress on the keyboard */
+	press_key(1, 1, 1);
+
+	/*
+	 * FIXME: This is wrong! We shouldn't be sending scan codes to the
+	 * host while the keyboard channel is inhibited. This should be
+	 * VERIFY_NO_CHAR();
+	 */
+	VERIFY_LPC_CHAR("\x01");
+
+	/* FIXME: This is also wrong for the same reason as above! */
+	press_key(1, 1, 0);
+	VERIFY_LPC_CHAR("\x81");
+
+	/* Stop inhibiting the keyboard */
+	WRITE_CMD_BYTE(0);
+
+	/*
+	 * FIXME: This is wrong. When the CLK is inhibited the device will queue
+	 * up events/scan codes in it's internal buffer. Once the inhibit is
+	 * released, the device will start clocking out the data. So in this
+	 * test we should be receiving the 0x01, and x81 here, but we received
+	 * them above.
+	 */
+	VERIFY_NO_CHAR();
+
+	return EC_SUCCESS;
+}
+
+static int test_8042_keyboard_key_pressed_before_inhibit_using_cmd_byte(void)
+{
+	ENABLE_KEYSTROKE(1);
+	/* Simulate a keypress on the keyboard */
+	press_key(1, 1, 1);
+	press_key(1, 1, 0);
+
+	/*
+	 * We should have a press scan code in the output buffer, and a
+	 * release scan code queued up in the keyboard queue.
+	 */
+	WAIT_FOR_DATA(30);
+
+	/* Inhibit the keyboard device from sending data. */
+	keyboard_host_write(I8042_WRITE_CMD_BYTE, 1);
+	keyboard_host_write(I8042_XLATE | I8042_KBD_DIS, 0);
+	/* Wait for controller to processes the command */
+	msleep(10);
+
+	/* Stop inhibiting the keyboard */
+	keyboard_host_write(I8042_WRITE_CMD_BYTE, 1);
+	keyboard_host_write(I8042_XLATE, 0);
+	/* Wait for controller to processes the command */
+	msleep(10);
+
+	/* Verify the scan codes from above */
+	VERIFY_LPC_CHAR("\x01");
+	VERIFY_LPC_CHAR("\x81");
+
+	return EC_SUCCESS;
+}
+
+static int
+test_8042_keyboard_key_pressed_before_inhibit_using_cmd_byte_with_read(void)
+{
+	uint8_t cmd;
+
+	ENABLE_KEYSTROKE(1);
+	/* Simulate a keypress on the keyboard */
+	press_key(1, 1, 1);
+	press_key(1, 1, 0);
+
+	/*
+	 * We should have a press scan code in the output buffer, and a
+	 * release scan code queued up in the keyboard queue.
+	 */
+	WAIT_FOR_DATA(30);
+
+	/* Inhibit the keyboard device from sending data. */
+	keyboard_host_write(I8042_WRITE_CMD_BYTE, 1);
+	keyboard_host_write(I8042_XLATE | I8042_KBD_DIS, 0);
+	/* Wait for controller to processes the command */
+	msleep(10);
+
+	/* Read the key press scan code from the output buffer. */
+	VERIFY_LPC_CHAR("\x01");
+
+	/*
+	 * With the keyboard output suppressed, we should be able to read from
+	 * the 8042 controller.
+	 */
+	cmd = READ_CMD_BYTE();
+
+	/* Verify we got the cmd byte we set above */
+	TEST_EQ(cmd, I8042_XLATE | I8042_KBD_DIS, "%d");
+
+	/* Stop inhibiting the keyboard */
+	keyboard_host_write(I8042_WRITE_CMD_BYTE, 1);
+	keyboard_host_write(I8042_XLATE, 0);
+	/* Wait for controller to processes the command */
+	msleep(10);
+
+	/* Verify the key release scan code from above */
+	/*
+	 * FIXME: This is wrong. We should receive the key release scan code
+	 * 0x81. Instead the `I8042_READ_CMD_BYTE` above cleared the keyboard's
+	 * output queue. It did this because the 8042 and keyboard output queues
+	 * are implemented as the same thing.
+	 */
+	VERIFY_NO_CHAR();
+
+	return EC_SUCCESS;
+}
+
+static int test_8042_keyboard_key_pressed_before_inhibit_using_cmd(void)
+{
+	ENABLE_KEYSTROKE(1);
+	/* Simulate a keypress on the keyboard */
+	press_key(1, 1, 1);
+	press_key(1, 1, 0);
+
+	/*
+	 * We should have a press scan code in the output buffer, and a
+	 * release scan code queued up in the keyboard queue.
+	 */
+	WAIT_FOR_DATA(30);
+
+	/* Inhibit the keyboard device from sending data. */
+	keyboard_host_write(I8042_DIS_KB, 1);
+
+	/* Stop inhibiting the keyboard */
+	keyboard_host_write(I8042_ENA_KB, 1);
+
+	/* Verify the scan codes from above */
+	VERIFY_LPC_CHAR("\x01");
+	/*
+	 * FIXME: This is wrong. When the keyboard CLK is inhibited the keyboard
+	 * will queue up events/scan codes in it's internal buffer. Once the
+	 * inhibit is released, the keyboard will start clocking out the data.
+	 * So in this test we should be receiving 0x81, but the keyboard buffer
+	 * was cleared by the I8042_DIS_KB above.
+	 */
+	VERIFY_NO_CHAR();
+	return EC_SUCCESS;
+}
 
 static int test_single_key_press(void)
 {
-	enable_keystroke(1);
+	ENABLE_KEYSTROKE(1);
 	press_key(1, 1, 1);
 	VERIFY_LPC_CHAR("\x01");
 	press_key(1, 1, 0);
@@ -140,7 +574,7 @@ static int test_single_key_press(void)
 
 static int test_disable_keystroke(void)
 {
-	enable_keystroke(0);
+	ENABLE_KEYSTROKE(0);
 	press_key(1, 1, 1);
 	VERIFY_NO_CHAR();
 	press_key(1, 1, 0);
@@ -151,12 +585,12 @@ static int test_disable_keystroke(void)
 
 static int test_typematic(void)
 {
-	enable_keystroke(1);
+	ENABLE_KEYSTROKE(1);
 
 	/*
 	 * 250ms delay, 8 chars / sec.
 	 */
-	set_typematic(0xf);
+	SET_TYPEMATIC(0xf);
 
 	press_key(1, 1, 1);
 	VERIFY_LPC_CHAR_DELAY("\x01\x01\x01\x01\x01", 650);
@@ -166,7 +600,7 @@ static int test_typematic(void)
 	/*
 	 * 500ms delay, 10.9 chars / sec.
 	 */
-	reset_8042();
+	RESET_8042();
 
 	press_key(1, 1, 1);
 	VERIFY_LPC_CHAR_DELAY("\x01\x01\x01", 650);
@@ -176,17 +610,208 @@ static int test_typematic(void)
 	return EC_SUCCESS;
 }
 
+static int test_atkbd_get_scancode(void)
+{
+	SET_SCANCODE(1);
+
+	keyboard_host_write(ATKBD_CMD_GSCANSET, 0);
+	VERIFY_ATKBD_ACK();
+
+	/* Writing a 0 scan code will return the current scan code. */
+	keyboard_host_write(0, 0);
+	VERIFY_ATKBD_ACK();
+	VERIFY_LPC_CHAR("\x01");
+
+	SET_SCANCODE(2);
+
+	keyboard_host_write(ATKBD_CMD_GSCANSET, 0);
+	VERIFY_ATKBD_ACK();
+
+	/* Writing a 0 scan code will return the current scan code. */
+	keyboard_host_write(0, 0);
+	VERIFY_ATKBD_ACK();
+	VERIFY_LPC_CHAR("\x02");
+
+	return EC_SUCCESS;
+}
+
+static int test_atkbd_set_scancode_with_keystroke_disabled(void)
+{
+	ENABLE_KEYSTROKE(0);
+
+	SET_SCANCODE(1);
+
+	press_key(1, 1, 1);
+	VERIFY_NO_CHAR();
+
+	return EC_SUCCESS;
+}
+
+static int test_atkbd_set_scancode_with_key_press_before_set(void)
+{
+	ENABLE_KEYSTROKE(0);
+	ENABLE_KEYSTROKE(1);
+
+	/* Push data into the output buffer and keyboard queue */
+	press_key(1, 1, 1);
+	press_key(1, 1, 0);
+
+	/*
+	 * ATKBD_CMD_SSCANSET should cause the keyboard to stop scanning, flush
+	 * the keyboards output queue, and reset the typematic key.
+	 */
+	keyboard_host_write(ATKBD_CMD_SSCANSET, 0);
+	/* Read out the scan code that got pushed into the output buffer before
+	 * the command was sent.
+	 */
+	VERIFY_LPC_CHAR("\x01");
+
+	/*
+	 * FIXME: This is wrong. The keyboard's output queue should have been
+	 * flushed when it received the `ATKBD_CMD_SSCANSET` command.
+	 */
+	VERIFY_LPC_CHAR("\x81");
+
+	/* This is the ACK for `ATKBD_CMD_SSCANSET`. */
+	VERIFY_ATKBD_ACK();
+
+	/* The keyboard has flushed the buffer so no more keys. */
+	VERIFY_NO_CHAR();
+
+	/* Finish setting scan code 1 */
+	keyboard_host_write(1, 0);
+	VERIFY_ATKBD_ACK();
+
+	/* Key scanning should be restored. */
+	press_key(1, 1, 1);
+	press_key(1, 1, 0);
+	VERIFY_LPC_CHAR("\x01\x81");
+
+	return EC_SUCCESS;
+}
+
+static int test_atkbd_set_scancode_with_key_press_during_set(void)
+{
+	ENABLE_KEYSTROKE(1);
+
+	/*
+	 * ATKBD_CMD_SSCANSET should cause the keyboard to stop scanning, flush
+	 * the keyboards output queue, and reset the typematic key.
+	 */
+	keyboard_host_write(ATKBD_CMD_SSCANSET, 0);
+	VERIFY_ATKBD_ACK();
+
+	/* These keypresses should be dropped. */
+	press_key(1, 1, 1);
+	press_key(1, 1, 0);
+	/*
+	 * FIXME: So this is wrong. scanning should be stopped while waiting
+	 * for the scan code to be sent.
+	 */
+	VERIFY_LPC_CHAR("\x01\x81");
+
+	/* Finish setting scan code 1 */
+	keyboard_host_write(1, 0);
+	VERIFY_ATKBD_ACK();
+
+	/* Key scanning should be restored. */
+	press_key(1, 1, 1);
+	press_key(1, 1, 0);
+	VERIFY_LPC_CHAR("\x01\x81");
+
+	return EC_SUCCESS;
+}
+
+static int test_atkbd_echo(void)
+{
+	i8042_write_data(ATKBD_CMD_DIAG_ECHO);
+	VERIFY_ATKBD_ACK();
+
+	VERIFY_LPC_CHAR("\xee");
+
+	return EC_SUCCESS;
+}
+
+static int test_atkbd_get_id(void)
+{
+	i8042_write_data(ATKBD_CMD_GETID);
+	VERIFY_ATKBD_ACK();
+
+	VERIFY_LPC_CHAR("\xab\x83");
+
+	i8042_write_data(ATKBD_CMD_OK_GETID);
+	VERIFY_ATKBD_ACK();
+
+	VERIFY_LPC_CHAR("\xab\x83");
+
+	return EC_SUCCESS;
+}
+
+static int test_atkbd_set_leds_keypress_during(void)
+{
+	/* This should pause scanning. */
+	i8042_write_data(ATKBD_CMD_SETLEDS);
+	VERIFY_ATKBD_ACK();
+
+	/* Simulate keypress while keyboard is waiting for option byte */
+	press_key(1, 1, 1);
+	press_key(1, 1, 0);
+	/* FIXME: This is wrong, we shouldn't have any key strokes */
+	VERIFY_LPC_CHAR("\x01\x81");
+
+	i8042_write_data(0x01);
+	VERIFY_ATKBD_ACK();
+
+	return EC_SUCCESS;
+}
+
+static int test_atkbd_set_leds_abort_set(void)
+{
+	i8042_write_data(ATKBD_CMD_SETLEDS);
+	VERIFY_ATKBD_ACK();
+
+	/*
+	 * The spec says if we send a command instead of the option byte, the
+	 * keyboard will abort the SETLEDS command and processes the new
+	 * command. The way we can differentiate between a command and the
+	 * option byte is the option byte must have the top 5 bits set to 0.
+	 */
+	i8042_write_data(ATKBD_CMD_DIAG_ECHO);
+	VERIFY_ATKBD_ACK();
+
+	/* FIXME: This is wrong. We are expecting the 0xee echo byte. */
+	VERIFY_NO_CHAR();
+
+	return EC_SUCCESS;
+}
+
+static int test_atkbd_set_ex_leds(void)
+{
+	i8042_write_data(ATKBD_CMD_EX_SETLEDS);
+	VERIFY_ATKBD_ACK();
+
+	/* The extra set led command expects two option bytes. */
+
+	i8042_write_data(0x1);
+	VERIFY_ATKBD_ACK();
+
+	i8042_write_data(0x2);
+	VERIFY_ATKBD_ACK();
+
+	return EC_SUCCESS;
+}
+
 static int test_scancode_set2(void)
 {
-	set_scancode(2);
+	SET_SCANCODE(2);
 
-	write_cmd_byte(read_cmd_byte() | I8042_XLATE);
+	WRITE_CMD_BYTE(READ_CMD_BYTE() | I8042_XLATE);
 	press_key(1, 1, 1);
 	VERIFY_LPC_CHAR("\x01");
 	press_key(1, 1, 0);
 	VERIFY_LPC_CHAR("\x81");
 
-	write_cmd_byte(read_cmd_byte() & ~I8042_XLATE);
+	WRITE_CMD_BYTE(READ_CMD_BYTE() & ~I8042_XLATE);
 	press_key(1, 1, 1);
 	VERIFY_LPC_CHAR("\x76");
 	press_key(1, 1, 0);
@@ -197,8 +822,13 @@ static int test_scancode_set2(void)
 
 static int test_power_button(void)
 {
+	ENABLE_KEYSTROKE(0);
+
 	gpio_set_level(GPIO_POWER_BUTTON_L, 1);
-	set_scancode(1);
+	msleep(100);
+
+	SET_SCANCODE(1);
+	ENABLE_KEYSTROKE(1);
 	test_chipset_on();
 
 	gpio_set_level(GPIO_POWER_BUTTON_L, 0);
@@ -207,8 +837,8 @@ static int test_power_button(void)
 	gpio_set_level(GPIO_POWER_BUTTON_L, 1);
 	VERIFY_LPC_CHAR_DELAY("\xe0\xde", 100);
 
-	set_scancode(2);
-	write_cmd_byte(read_cmd_byte() & ~I8042_XLATE);
+	SET_SCANCODE(2);
+	WRITE_CMD_BYTE(READ_CMD_BYTE() & ~I8042_XLATE);
 
 	gpio_set_level(GPIO_POWER_BUTTON_L, 0);
 	VERIFY_LPC_CHAR_DELAY("\xe0\x37", 100);
@@ -229,8 +859,8 @@ static int test_power_button(void)
 
 static int test_sysjump(void)
 {
-	set_scancode(2);
-	enable_keystroke(1);
+	SET_SCANCODE(2);
+	ENABLE_KEYSTROKE(1);
 
 	system_run_image_copy(EC_IMAGE_RW);
 
@@ -240,13 +870,13 @@ static int test_sysjump(void)
 
 static int test_sysjump_cont(void)
 {
-	write_cmd_byte(read_cmd_byte() | I8042_XLATE);
+	WRITE_CMD_BYTE(READ_CMD_BYTE() | I8042_XLATE);
 	press_key(1, 1, 1);
 	VERIFY_LPC_CHAR("\x01");
 	press_key(1, 1, 0);
 	VERIFY_LPC_CHAR("\x81");
 
-	write_cmd_byte(read_cmd_byte() & ~I8042_XLATE);
+	WRITE_CMD_BYTE(READ_CMD_BYTE() & ~I8042_XLATE);
 	press_key(1, 1, 1);
 	VERIFY_LPC_CHAR("\x76");
 	press_key(1, 1, 0);
@@ -274,8 +904,8 @@ static const struct ec_response_keybd_config keybd_config = {
 	},
 };
 
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	return &keybd_config;
 }
@@ -285,8 +915,8 @@ static int test_ec_cmd_get_keybd_config(void)
 	struct ec_response_keybd_config resp;
 	int rv;
 
-	rv = test_send_host_command(EC_CMD_GET_KEYBD_CONFIG, 0, NULL, 0,
-				    &resp, sizeof(resp));
+	rv = test_send_host_command(EC_CMD_GET_KEYBD_CONFIG, 0, NULL, 0, &resp,
+				    sizeof(resp));
 	if (rv != EC_RES_SUCCESS) {
 		ccprintf("Error: EC_CMD_GET_KEYBD_CONFIG cmd returns %d\n", rv);
 		return EC_ERROR_INVAL;
@@ -303,32 +933,56 @@ static int test_ec_cmd_get_keybd_config(void)
 
 static int test_vivaldi_top_keys(void)
 {
-	set_scancode(2);
+	SET_SCANCODE(2);
 
 	/* Test REFRESH key */
-	write_cmd_byte(read_cmd_byte() | I8042_XLATE);
-	press_key(2, 3, 1);		/* Press T2 */
-	VERIFY_LPC_CHAR("\xe0\x67");	/* Check REFRESH scancode in set-1 */
+	WRITE_CMD_BYTE(READ_CMD_BYTE() | I8042_XLATE);
+	press_key(2, 3, 1); /* Press T2 */
+	VERIFY_LPC_CHAR("\xe0\x67"); /* Check REFRESH scancode in set-1 */
 
 	/* Test SNAPSHOT key */
-	write_cmd_byte(read_cmd_byte() | I8042_XLATE);
-	press_key(4, 3, 1);		/* Press T2 */
-	VERIFY_LPC_CHAR("\xe0\x13");	/* Check SNAPSHOT scancode in set-1 */
+	WRITE_CMD_BYTE(READ_CMD_BYTE() | I8042_XLATE);
+	press_key(4, 3, 1); /* Press T2 */
+	VERIFY_LPC_CHAR("\xe0\x13"); /* Check SNAPSHOT scancode in set-1 */
 
 	/* Test VOL_UP key */
-	write_cmd_byte(read_cmd_byte() | I8042_XLATE);
-	press_key(5, 3, 1);		/* Press T2 */
-	VERIFY_LPC_CHAR("\xe0\x30");	/* Check VOL_UP scancode in set-1 */
+	WRITE_CMD_BYTE(READ_CMD_BYTE() | I8042_XLATE);
+	press_key(5, 3, 1); /* Press T2 */
+	VERIFY_LPC_CHAR("\xe0\x30"); /* Check VOL_UP scancode in set-1 */
 
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 	wait_for_task_started();
 
 	if (system_get_image_copy() == EC_IMAGE_RO) {
+		RUN_TEST(test_8042_aux_loopback);
+		RUN_TEST(test_8042_aux_two_way_communication);
+		RUN_TEST(test_8042_aux_inhibit);
+		RUN_TEST(test_8042_aux_controller_commands);
+		RUN_TEST(test_8042_aux_test_command);
+		RUN_TEST(test_8042_self_test);
+		RUN_TEST(test_8042_keyboard_test_command);
+		RUN_TEST(test_8042_keyboard_controller_commands);
+		RUN_TEST(test_8042_keyboard_key_pressed_while_inhibited);
+		RUN_TEST(
+			test_8042_keyboard_key_pressed_before_inhibit_using_cmd_byte);
+		RUN_TEST(
+			test_8042_keyboard_key_pressed_before_inhibit_using_cmd_byte_with_read);
+		RUN_TEST(
+			test_8042_keyboard_key_pressed_before_inhibit_using_cmd);
+		RUN_TEST(test_atkbd_get_scancode);
+		RUN_TEST(test_atkbd_set_scancode_with_keystroke_disabled);
+		RUN_TEST(test_atkbd_set_scancode_with_key_press_before_set);
+		RUN_TEST(test_atkbd_set_scancode_with_key_press_during_set);
+		RUN_TEST(test_atkbd_echo);
+		RUN_TEST(test_atkbd_get_id);
+		RUN_TEST(test_atkbd_set_leds_keypress_during);
+		RUN_TEST(test_atkbd_set_leds_abort_set);
+		RUN_TEST(test_atkbd_set_ex_leds);
 		RUN_TEST(test_single_key_press);
 		RUN_TEST(test_disable_keystroke);
 		RUN_TEST(test_typematic);
diff --git a/test/kb_8042.tasklist b/test/kb_8042.tasklist
index 8cd35e6145..4d74e3c269 100644
--- a/test/kb_8042.tasklist
+++ b/test/kb_8042.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/kb_mkbp.c b/test/kb_mkbp.c
index 3b191a47ac..0bfd1e5a15 100644
--- a/test/kb_mkbp.c
+++ b/test/kb_mkbp.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,7 +19,7 @@
 static uint8_t state[KEYBOARD_COLS_MAX];
 static int ec_int_level;
 
-static const char *action[2] = {"release", "press"};
+static const char *action[2] = { "release", "press" };
 
 /*****************************************************************************/
 /* Mock functions */
@@ -43,7 +43,7 @@ int lid_is_open(void)
 /*****************************************************************************/
 /* Test utilities */
 
-#define FIFO_EMPTY()     (ec_int_level == 1)
+#define FIFO_EMPTY() (ec_int_level == 1)
 #define FIFO_NOT_EMPTY() (ec_int_level == 0)
 
 void clear_state(void)
@@ -71,7 +71,7 @@ int press_key(int c, int r, int pressed)
 int verify_key(int c, int r, int pressed)
 {
 	struct host_cmd_handler_args args;
-	struct  ec_response_get_next_event event;
+	struct ec_response_get_next_event event;
 	int i;
 
 	args.version = 0;
@@ -104,7 +104,7 @@ int verify_key(int c, int r, int pressed)
 int verify_key_v2(int c, int r, int pressed, int expect_more)
 {
 	struct host_cmd_handler_args args;
-	struct  ec_response_get_next_event_v1 event;
+	struct ec_response_get_next_event_v1 event;
 	int i;
 
 	args.version = 2;
@@ -286,7 +286,7 @@ int fifo_underrun(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	ec_int_level = 1;
 	test_reset();
diff --git a/test/kb_mkbp.tasklist b/test/kb_mkbp.tasklist
index d84996c71c..a255779878 100644
--- a/test/kb_mkbp.tasklist
+++ b/test/kb_mkbp.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/kb_scan.c b/test/kb_scan.c
index a43808c0c1..82693ff525 100644
--- a/test/kb_scan.c
+++ b/test/kb_scan.c
@@ -1,7 +1,7 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
- * Copyright 2013 Google Inc.
+ * Copyright 2013 Google LLC
  *
  * Tests for keyboard scan deghosting and debouncing.
  */
@@ -20,15 +20,15 @@
 #include "timer.h"
 #include "util.h"
 
-#define KEYDOWN_DELAY_MS     10
-#define KEYDOWN_RETRY        10
-#define NO_KEYDOWN_DELAY_MS  100
+#define KEYDOWN_DELAY_MS 10
+#define KEYDOWN_RETRY 10
+#define NO_KEYDOWN_DELAY_MS 100
 
-#define CHECK_KEY_COUNT(old, expected) \
-	do { \
+#define CHECK_KEY_COUNT(old, expected)                               \
+	do {                                                         \
 		if (verify_key_presses(old, expected) != EC_SUCCESS) \
-			return EC_ERROR_UNKNOWN; \
-		old = fifo_add_count; \
+			return EC_ERROR_UNKNOWN;                     \
+		old = fifo_add_count;                                \
 	} while (0)
 
 /* Emulated physical key state */
@@ -121,13 +121,10 @@ void chipset_reset(void)
 }
 #endif
 
-#define mock_defined_key(k, p) mock_key(KEYBOARD_ROW_ ## k, \
-					KEYBOARD_COL_ ## k, \
-					p)
+#define mock_defined_key(k, p) mock_key(KEYBOARD_ROW_##k, KEYBOARD_COL_##k, p)
 
-#define mock_default_key(k, p) mock_key(KEYBOARD_DEFAULT_ROW_ ## k, \
-					KEYBOARD_DEFAULT_COL_ ## k, \
-					p)
+#define mock_default_key(k, p) \
+	mock_key(KEYBOARD_DEFAULT_ROW_##k, KEYBOARD_DEFAULT_COL_##k, p)
 
 static void mock_key(int r, int c, int keydown)
 {
@@ -403,7 +400,7 @@ static int debounce_test(void)
 	 * Push down each subsequent key, until all 8 are pressed, each
 	 * time bouncing the former one once.
 	 */
-	for (i = 1 ; i < 8; i++) {
+	for (i = 1; i < 8; i++) {
 		mock_key(i, 1, 1);
 		task_wake(TASK_ID_KEYSCAN);
 		msleep(3);
@@ -547,12 +544,14 @@ static int lid_test(void)
 
 static int test_check_boot_esc(void)
 {
-	TEST_CHECK(keyboard_scan_get_boot_keys() == BOOT_KEY_ESC);
+	TEST_ASSERT(keyboard_scan_get_boot_keys() == BOOT_KEY_ESC);
+	return EC_SUCCESS;
 }
 
 static int test_check_boot_down(void)
 {
-	TEST_CHECK(keyboard_scan_get_boot_keys() == BOOT_KEY_DOWN_ARROW);
+	TEST_ASSERT(keyboard_scan_get_boot_keys() == BOOT_KEY_DOWN_ARROW);
+	return EC_SUCCESS;
 }
 
 void test_init(void)
@@ -587,7 +586,7 @@ static void run_test_step1(void)
 	else
 		RUN_TEST(debounce_test);
 
-	if (0)  /* crbug.com/976974 */
+	if (0) /* crbug.com/976974 */
 		RUN_TEST(simulate_key_test);
 #ifdef EMU_BUILD
 	RUN_TEST(runtime_key_test);
@@ -646,7 +645,7 @@ int test_task(void *data)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	msleep(30); /* Wait for TASK_ID_TEST to initialize */
 	task_wake(TASK_ID_TEST);
diff --git a/test/kb_scan.tasklist b/test/kb_scan.tasklist
index ded03b1112..3cac36bb23 100644
--- a/test/kb_scan.tasklist
+++ b/test/kb_scan.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/legacy_nvmem_dump.h b/test/legacy_nvmem_dump.h
index 6816673c23..401694d9d6 100644
--- a/test/legacy_nvmem_dump.h
+++ b/test/legacy_nvmem_dump.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,10 +12,10 @@
  * This binary dump is placed in a separate file not to free up the test file
  * using it.
  */
-	0x00, 0x65, 0x8e, 0x10, 0x80, 0xca, 0x52, 0x1e, 0x95, 0x81, 0x12, 0x4f,
-	0x36, 0x78, 0x9a, 0x34, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x10, 0xff, 0xff,
-	0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00,
+0x00, 0x65, 0x8e, 0x10, 0x80, 0xca, 0x52, 0x1e, 0x95, 0x81, 0x12, 0x4f, 0x36,
+	0x78, 0x9a, 0x34, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x10, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -32,12 +32,12 @@
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x63, 0x72, 0x6f, 0x73, 0x2d, 0x70,
-	0x61, 0x73, 0x73, 0x77, 0x6f, 0x72, 0x64, 0x00, 0xe1, 0xac, 0x01, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6b, 0x37, 0x01, 0x00,
-	0x03, 0x00, 0x00, 0x00, 0xbd, 0xfe, 0xff, 0xff, 0x85, 0xfc, 0x05, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0xb0, 0xde, 0x01, 0x00, 0xb4, 0xde, 0x01, 0x00,
-	0x9b, 0x0f, 0x06, 0x00, 0xbc, 0xde, 0x01, 0x00, 0x40, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x0d, 0x00, 0x63, 0x72, 0x6f, 0x73, 0x2d, 0x70, 0x61,
+	0x73, 0x73, 0x77, 0x6f, 0x72, 0x64, 0x00, 0xe1, 0xac, 0x01, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6b, 0x37, 0x01, 0x00, 0x03,
+	0x00, 0x00, 0x00, 0xbd, 0xfe, 0xff, 0xff, 0x85, 0xfc, 0x05, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0xb0, 0xde, 0x01, 0x00, 0xb4, 0xde, 0x01, 0x00, 0x9b,
+	0x0f, 0x06, 0x00, 0xbc, 0xde, 0x01, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -48,34 +48,33 @@
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
-	0x5b, 0x15, 0xa1, 0x0a, 0x05, 0x12, 0x58, 0x84, 0xbf, 0xf6, 0xc9, 0xf3,
-	0xdd, 0xb7, 0x26, 0xce, 0x56, 0x9e, 0x5f, 0x7a, 0xa8, 0xd4, 0x8a, 0x67,
-	0x5c, 0x26, 0x35, 0x0e, 0xb2, 0x13, 0x2c, 0x79, 0x20, 0x00, 0x26, 0xca,
-	0x7d, 0xb8, 0x1a, 0x1f, 0x0b, 0x5c, 0x0a, 0xf3, 0xb5, 0xe2, 0x6a, 0xec,
-	0x1a, 0x0d, 0x90, 0x8b, 0x92, 0x3c, 0x07, 0xb0, 0x41, 0xb0, 0x27, 0x20,
-	0x88, 0x33, 0xfe, 0x5c, 0xf2, 0x7b, 0x20, 0x00, 0x9e, 0xb7, 0xa2, 0x4c,
-	0xad, 0x6c, 0xc0, 0x92, 0x92, 0xef, 0xbc, 0x56, 0x65, 0x47, 0xf9, 0x09,
-	0xd1, 0xc4, 0xbc, 0x36, 0xe8, 0x3a, 0xc2, 0x8a, 0x11, 0x3a, 0xca, 0xe1,
-	0x66, 0xd7, 0x85, 0x57, 0x20, 0x00, 0x0c, 0x6d, 0xc7, 0x61, 0x92, 0xfc,
-	0x1b, 0x24, 0x02, 0xc1, 0x92, 0x0e, 0xf4, 0xa1, 0x75, 0xbe, 0xb1, 0x3d,
-	0x29, 0xfe, 0x1e, 0xe2, 0x65, 0xf5, 0x25, 0xae, 0xaf, 0xfe, 0x73, 0x32,
-	0x35, 0x75, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x5b,
+	0x15, 0xa1, 0x0a, 0x05, 0x12, 0x58, 0x84, 0xbf, 0xf6, 0xc9, 0xf3, 0xdd,
+	0xb7, 0x26, 0xce, 0x56, 0x9e, 0x5f, 0x7a, 0xa8, 0xd4, 0x8a, 0x67, 0x5c,
+	0x26, 0x35, 0x0e, 0xb2, 0x13, 0x2c, 0x79, 0x20, 0x00, 0x26, 0xca, 0x7d,
+	0xb8, 0x1a, 0x1f, 0x0b, 0x5c, 0x0a, 0xf3, 0xb5, 0xe2, 0x6a, 0xec, 0x1a,
+	0x0d, 0x90, 0x8b, 0x92, 0x3c, 0x07, 0xb0, 0x41, 0xb0, 0x27, 0x20, 0x88,
+	0x33, 0xfe, 0x5c, 0xf2, 0x7b, 0x20, 0x00, 0x9e, 0xb7, 0xa2, 0x4c, 0xad,
+	0x6c, 0xc0, 0x92, 0x92, 0xef, 0xbc, 0x56, 0x65, 0x47, 0xf9, 0x09, 0xd1,
+	0xc4, 0xbc, 0x36, 0xe8, 0x3a, 0xc2, 0x8a, 0x11, 0x3a, 0xca, 0xe1, 0x66,
+	0xd7, 0x85, 0x57, 0x20, 0x00, 0x0c, 0x6d, 0xc7, 0x61, 0x92, 0xfc, 0x1b,
+	0x24, 0x02, 0xc1, 0x92, 0x0e, 0xf4, 0xa1, 0x75, 0xbe, 0xb1, 0x3d, 0x29,
+	0xfe, 0x1e, 0xe2, 0x65, 0xf5, 0x25, 0xae, 0xaf, 0xfe, 0x73, 0x32, 0x35,
+	0x75, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
-	0x52, 0x01, 0x7b, 0x53, 0xc5, 0x95, 0xa0, 0x3a, 0x07, 0xd5, 0x62, 0x7f,
-	0xd3, 0x9c, 0x85, 0xaa, 0xfc, 0x56, 0xa0, 0xfa, 0x3a, 0xe8, 0x17, 0x38,
-	0xc3, 0x59, 0x65, 0xbe, 0x75, 0x1b, 0xdc, 0xdc, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x52,
+	0x01, 0x7b, 0x53, 0xc5, 0x95, 0xa0, 0x3a, 0x07, 0xd5, 0x62, 0x7f, 0xd3,
+	0x9c, 0x85, 0xaa, 0xfc, 0x56, 0xa0, 0xfa, 0x3a, 0xe8, 0x17, 0x38, 0xc3,
+	0x59, 0x65, 0xbe, 0x75, 0x1b, 0xdc, 0xdc, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x84, 0xe7, 0x7e, 0x46, 0xfe, 0xbd,
-	0x10, 0xdd, 0x5b, 0x09, 0xb2, 0xe2, 0xb1, 0x3f, 0xbf, 0x9a, 0xf3, 0xd7,
-	0xfb, 0xf7, 0x28, 0xbb, 0x24, 0x10, 0xa3, 0xf3, 0x18, 0xa4, 0xa2, 0x16,
-	0xd5, 0xea, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00,
+	0x00, 0x00, 0x00, 0x20, 0x00, 0x84, 0xe7, 0x7e, 0x46, 0xfe, 0xbd, 0x10,
+	0xdd, 0x5b, 0x09, 0xb2, 0xe2, 0xb1, 0x3f, 0xbf, 0x9a, 0xf3, 0xd7, 0xfb,
+	0xf7, 0x28, 0xbb, 0x24, 0x10, 0xa3, 0xf3, 0x18, 0xa4, 0xa2, 0x16, 0xd5,
+	0xea, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -86,15 +85,16 @@
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x04, 0x00, 0x00, 0x00, 0x04, 0x00, 0x03, 0xff, 0xff, 0xff, 0x0b, 0x00,
-	0x03, 0xff, 0xff, 0xff, 0x0c, 0x00, 0x03, 0xff, 0xff, 0xff, 0x0d, 0x00,
-	0x03, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8,
-	0x00, 0x00, 0x00, 0xe8, 0x03, 0x00, 0x00, 0xe8, 0x03, 0x00, 0x00, 0x01,
-	0x00, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
+	0x00, 0x00, 0x00, 0x04, 0x00, 0x03, 0xff, 0xff, 0xff, 0x0b, 0x00, 0x03,
+	0xff, 0xff, 0xff, 0x0c, 0x00, 0x03, 0xff, 0xff, 0xff, 0x0d, 0x00, 0x03,
+	0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x00,
+	0x00, 0x00, 0xe8, 0x03, 0x00, 0x00, 0xe8, 0x03, 0x00, 0x00, 0x01, 0x00,
+	0x00, 0x00, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
@@ -113,7 +113,7 @@
 	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff,
 	/* Manually added nonempty pcr. Array 0, index 0 */
 	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01, 0x02, 0x03, 0x04, 0x05, 0xff,
 	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
diff --git a/test/lid_sw.c b/test/lid_sw.c
index 8163f74716..123676a1fa 100644
--- a/test/lid_sw.c
+++ b/test/lid_sw.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -83,7 +83,7 @@ static int test_debounce(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/lid_sw.tasklist b/test/lid_sw.tasklist
index da0ab6211a..100cb6b5bd 100644
--- a/test/lid_sw.tasklist
+++ b/test/lid_sw.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/lightbar.c b/test/lightbar.c
index 363d73a36b..90400d1cf5 100644
--- a/test/lightbar.c
+++ b/test/lightbar.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,9 +20,8 @@ static int get_seq(void)
 	/* Get the state */
 	memset(&resp, 0, sizeof(resp));
 	params.cmd = LIGHTBAR_CMD_GET_SEQ;
-	rv = test_send_host_command(EC_CMD_LIGHTBAR_CMD, 0,
-				    &params, sizeof(params),
-				    &resp, sizeof(resp));
+	rv = test_send_host_command(EC_CMD_LIGHTBAR_CMD, 0, &params,
+				    sizeof(params), &resp, sizeof(resp));
 	if (rv != EC_RES_SUCCESS) {
 		ccprintf("%s:%s(): rv = %d\n", __FILE__, __func__, rv);
 		return -1;
@@ -41,9 +40,8 @@ static int set_seq(int s)
 	memset(&resp, 0, sizeof(resp));
 	params.cmd = LIGHTBAR_CMD_SEQ;
 	params.seq.num = s;
-	rv = test_send_host_command(EC_CMD_LIGHTBAR_CMD, 0,
-				    &params, sizeof(params),
-				    &resp, sizeof(resp));
+	rv = test_send_host_command(EC_CMD_LIGHTBAR_CMD, 0, &params,
+				    sizeof(params), &resp, sizeof(resp));
 	if (rv != EC_RES_SUCCESS) {
 		ccprintf("%s:%s(): rv = %d\n", __FILE__, __func__, rv);
 		return -1;
@@ -169,9 +167,8 @@ test_static int test_stop_timeout(void)
 		TEST_ASSERT(set_seq(i) == EC_RES_SUCCESS);
 		usleep(SECOND);
 		/* What happened? */
-		if (i == LIGHTBAR_RUN ||
-		    i == LIGHTBAR_S0S3 || i ==  LIGHTBAR_S3 ||
-		    i ==  LIGHTBAR_S3S5 || i ==  LIGHTBAR_S5)
+		if (i == LIGHTBAR_RUN || i == LIGHTBAR_S0S3 ||
+		    i == LIGHTBAR_S3 || i == LIGHTBAR_S3S5 || i == LIGHTBAR_S5)
 			/* RUN or shutdown sequences should stop it */
 			TEST_ASSERT(get_seq() == LIGHTBAR_S0);
 		else
@@ -290,7 +287,7 @@ const struct lb_brightness_def lb_brightness_levels[] = {
 	},
 };
 const unsigned int lb_brightness_levels_count =
-		ARRAY_SIZE(lb_brightness_levels);
+	ARRAY_SIZE(lb_brightness_levels);
 
 int lux_level_to_google_color(const int lux);
 extern int google_color_id;
@@ -303,8 +300,8 @@ int lid_is_open(void)
 test_static int test_als_lightbar(void)
 {
 	int lux_data[] = { 500, 100, 35, 15, 30, 35, 55, 70, 55, 100 };
-	int exp_gcid[] = {   0,   0,  1,  2,  2,  2,  1,  0,  0,   0 };
-	int exp_chg[]  = {   0,   0,  1,  1,  0,  0,  1,  1,  0,   0 };
+	int exp_gcid[] = { 0, 0, 1, 2, 2, 2, 1, 0, 0, 0 };
+	int exp_chg[] = { 0, 0, 1, 1, 0, 0, 1, 1, 0, 0 };
 	int i;
 
 	BUILD_ASSERT(ARRAY_SIZE(lux_data) == ARRAY_SIZE(exp_gcid));
@@ -319,7 +316,7 @@ test_static int test_als_lightbar(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	/* Ensure tasks are started before running tests */
 	usleep(SECOND);
diff --git a/test/lightbar.tasklist b/test/lightbar.tasklist
index b5e714765d..78c08cc652 100644
--- a/test/lightbar.tasklist
+++ b/test/lightbar.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/mag_cal.c b/test/mag_cal.c
index 8ee3b41480..245bad786c 100644
--- a/test/mag_cal.c
+++ b/test/mag_cal.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,35 +17,17 @@
  * the high values and [-5,5] (+- 1.53 uT) for the low values.
  */
 static intv3_t samples[] = {
-	{ -522, 5, -5 },
-	{ -528, -3, 1 },
-	{ -531, -2, 0 },
-	{ -525, -1, 3 },
+	{ -522, 5, -5 },  { -528, -3, 1 },  { -531, -2, 0 }, { -525, -1, 3 },
 
-	{ 527, 3, -2 },
-	{ 523, -5, 1 },
-	{ 520, -3, 2 },
-	{ 522, 0, -4 },
+	{ 527, 3, -2 },	  { 523, -5, 1 },   { 520, -3, 2 },  { 522, 0, -4 },
 
-	{ -3, -519, -2 },
-	{ 1, -521, 5 },
-	{ 2, -526, 4 },
-	{ 0, -532, -5 },
+	{ -3, -519, -2 }, { 1, -521, 5 },   { 2, -526, 4 },  { 0, -532, -5 },
 
-	{ -5, 528, 4 },
-	{ -2, 531, -4 },
-	{ 1, 522, 2 },
-	{ 5, 532, 3 },
+	{ -5, 528, 4 },	  { -2, 531, -4 },  { 1, 522, 2 },   { 5, 532, 3 },
 
-	{ -5, 0, -524 },
-	{ -1, -2, -527 },
-	{ -3, 4, -532 },
-	{ 5, 3, -531 },
+	{ -5, 0, -524 },  { -1, -2, -527 }, { -3, 4, -532 }, { 5, 3, -531 },
 
-	{ 4, -2, 524 },
-	{ 1, 3, 520 },
-	{ 5, -5, 528 },
-	{ 0, 2, 521 },
+	{ 4, -2, 524 },	  { 1, 3, 520 },    { 5, -5, 528 },  { 0, 2, 521 },
 };
 
 static int test_mag_cal_computes_bias(void)
@@ -81,7 +63,7 @@ static int test_mag_cal_computes_bias(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/mag_cal.tasklist b/test/mag_cal.tasklist
index ff715f69cd..a8b04538aa 100644
--- a/test/mag_cal.tasklist
+++ b/test/mag_cal.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/math_util.c b/test/math_util.c
index 6482888e55..1ee9b1484b 100644
--- a/test/math_util.c
+++ b/test/math_util.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -25,7 +25,7 @@ const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 /* Test utilities */
 
 /* Macro to compare two floats and check if they are equal within diff. */
-#define IS_FLOAT_EQUAL(a, b, diff) ((a) >= ((b) - diff) && (a) <= ((b) + diff))
+#define IS_FLOAT_EQUAL(a, b, diff) ((a) >= ((b)-diff) && (a) <= ((b) + diff))
 
 #define ACOS_TOLERANCE_DEG 0.5f
 #define RAD_TO_DEG (180.0f / 3.1415926f)
@@ -45,21 +45,19 @@ static int test_acos(void)
 	return EC_SUCCESS;
 }
 
-
 const mat33_fp_t test_matrices[] = {
-	{{ 0, FLOAT_TO_FP(-1), 0},
-	 {FLOAT_TO_FP(-1), 0, 0},
-	 { 0, 0, FLOAT_TO_FP(1)} },
-	{{ FLOAT_TO_FP(1), 0, FLOAT_TO_FP(5)},
-	 { FLOAT_TO_FP(2), FLOAT_TO_FP(1), FLOAT_TO_FP(6)},
-	 { FLOAT_TO_FP(3), FLOAT_TO_FP(4), 0} }
+	{ { 0, FLOAT_TO_FP(-1), 0 },
+	  { FLOAT_TO_FP(-1), 0, 0 },
+	  { 0, 0, FLOAT_TO_FP(1) } },
+	{ { FLOAT_TO_FP(1), 0, FLOAT_TO_FP(5) },
+	  { FLOAT_TO_FP(2), FLOAT_TO_FP(1), FLOAT_TO_FP(6) },
+	  { FLOAT_TO_FP(3), FLOAT_TO_FP(4), 0 } }
 };
 
-
 static int test_rotate(void)
 {
 	int i, j, k;
-	intv3_t v = {1, 2, 3};
+	intv3_t v = { 1, 2, 3 };
 	intv3_t w;
 
 	for (i = 0; i < ARRAY_SIZE(test_matrices); i++) {
@@ -122,7 +120,7 @@ test_static int test_temp_conversion(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/math_util.tasklist b/test/math_util.tasklist
index f5c894ccaf..dbe560d4aa 100644
--- a/test/math_util.tasklist
+++ b/test/math_util.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/motion_angle.c b/test/motion_angle.c
index 30f663de14..3f206de078 100644
--- a/test/motion_angle.c
+++ b/test/motion_angle.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -32,10 +32,10 @@ int filler(const struct motion_sensor_t *s, const float v)
 static int test_lid_angle_less180(void)
 {
 	int index = 0, lid_angle;
-	struct motion_sensor_t *lid = &motion_sensors[
-		CONFIG_LID_ANGLE_SENSOR_LID];
-	struct motion_sensor_t *base = &motion_sensors[
-		CONFIG_LID_ANGLE_SENSOR_BASE];
+	struct motion_sensor_t *lid =
+		&motion_sensors[CONFIG_LID_ANGLE_SENSOR_LID];
+	struct motion_sensor_t *base =
+		&motion_sensors[CONFIG_LID_ANGLE_SENSOR_BASE];
 
 	/* We don't have TASK_CHIP so simulate init ourselves */
 	hook_notify(HOOK_CHIPSET_SHUTDOWN);
@@ -56,42 +56,39 @@ static int test_lid_angle_less180(void)
 	cprints(CC_ACCEL, "start loop");
 	/* Check we will never enter tablet mode. */
 	while (index < kAccelerometerLaptopModeTestDataLength) {
-		feed_accel_data(kAccelerometerLaptopModeTestData,
-				&index, filler);
+		feed_accel_data(kAccelerometerLaptopModeTestData, &index,
+				filler);
 		wait_for_valid_sample();
 		lid_angle = motion_lid_get_angle();
 		cprints(CC_ACCEL, "%d : LID(%d, %d, %d)/BASE(%d, %d, %d): %d",
-				index / TEST_LID_SAMPLE_SIZE,
-				lid->xyz[X], lid->xyz[Y], lid->xyz[Z],
-				base->xyz[X], base->xyz[Y], base->xyz[Z],
-				lid_angle);
+			index / TEST_LID_SAMPLE_SIZE, lid->xyz[X], lid->xyz[Y],
+			lid->xyz[Z], base->xyz[X], base->xyz[Y], base->xyz[Z],
+			lid_angle);
 		/* We need few sample to debounce and enter laptop mode. */
 		TEST_ASSERT(index < TEST_LID_SAMPLE_SIZE *
-				(TABLET_MODE_DEBOUNCE_COUNT + 2) ||
+					    (TABLET_MODE_DEBOUNCE_COUNT + 2) ||
 			    !tablet_get_mode());
 	}
 
 	/* Check we will never exit tablet mode. */
 	index = 0;
 	while (index < kAccelerometerFullyOpenTestDataLength) {
-		feed_accel_data(kAccelerometerFullyOpenTestData,
-				&index, filler);
+		feed_accel_data(kAccelerometerFullyOpenTestData, &index,
+				filler);
 		wait_for_valid_sample();
 		lid_angle = motion_lid_get_angle();
 		cprints(CC_ACCEL, "%d : LID(%d, %d, %d)/BASE(%d, %d, %d): %d",
-				index / TEST_LID_SAMPLE_SIZE,
-				lid->xyz[X], lid->xyz[Y], lid->xyz[Z],
-				base->xyz[X], base->xyz[Y], base->xyz[Z],
-				lid_angle);
+			index / TEST_LID_SAMPLE_SIZE, lid->xyz[X], lid->xyz[Y],
+			lid->xyz[Z], base->xyz[X], base->xyz[Y], base->xyz[Z],
+			lid_angle);
 		TEST_ASSERT(index < TEST_LID_SAMPLE_SIZE *
-				(TABLET_MODE_DEBOUNCE_COUNT + 2) ||
+					    (TABLET_MODE_DEBOUNCE_COUNT + 2) ||
 			    tablet_get_mode());
 	}
 	return EC_SUCCESS;
 }
 
-
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/motion_angle.tasklist b/test/motion_angle.tasklist
index 0b774ebb4a..6c99c23eea 100644
--- a/test/motion_angle.tasklist
+++ b/test/motion_angle.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/motion_angle_data_literals.c b/test/motion_angle_data_literals.c
index 74d00f8232..d22a8230a2 100644
--- a/test/motion_angle_data_literals.c
+++ b/test/motion_angle_data_literals.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,991 +12,993 @@
  * [ CONFIG_ACCEL_STD_REF_FRAME_OLD must be defined to used this array. ]
  */
 const float kAccelerometerLaptopModeTestData[] = {
-    -0.166016f,   -0.00488281f,  0.924805f,     -0.770508f,    -0.0488281f,
-    -0.510742f,   -0.199219f,    -0.0078125f,   0.953125f,     -0.782227f,
-    -0.0244141f,  -0.652344f,    -0.177734f,    -0.0136719f,   0.936523f,
-    -0.772461f,   -0.0527344f,   -0.59375f,     -0.176758f,    -0.00878906f,
-    0.9375f,      -0.777344f,    -0.0419922f,   -0.637695f,    -0.165039f,
-    -0.00878906f, 0.942383f,     -0.782227f,    -0.046875f,    -0.613281f,
-    -0.180664f,   -0.00976562f,  0.943359f,     -0.777344f,    -0.0419922f,
-    -0.601562f,   -0.189453f,    -0.00488281f,  0.943359f,     -0.776367f,
-    -0.0263672f,  -0.613281f,    -0.166992f,    -0.00488281f,  0.935547f,
-    -0.78125f,    -0.0380859f,   -0.609375f,    -0.176758f,    -0.00878906f,
-    0.947266f,    -0.790039f,    -0.0576172f,   -0.585938f,    -0.173828f,
-    -0.0126953f,  0.93457f,      -0.780273f,    -0.0654297f,   -0.666016f,
-    -0.169922f,   -0.00195312f,  0.928711f,     -0.775391f,    -0.0351562f,
-    -0.561523f,   -0.193359f,    0.0f,          0.941406f,     -0.795898f,
-    -0.0478516f,  -0.640625f,    -0.162109f,    -0.00585938f,  0.917969f,
-    -0.768555f,   -0.0146484f,   -0.685547f,    -0.166992f,    -0.0136719f,
-    0.921875f,    -0.755859f,    -0.0166016f,   -0.425781f,    -0.175781f,
-    -0.0810547f,  1.00098f,      -0.802734f,    -0.117188f,    -0.585938f,
-    -0.210938f,   0.0214844f,    0.881836f,     -0.750977f,    -0.0302734f,
-    -0.677734f,   -0.285156f,    0.00976562f,   0.967773f,     -0.763672f,
-    -0.0283203f,  -0.850586f,    -0.222656f,    -0.0136719f,   0.943359f,
-    -0.763672f,   -0.0507812f,   -0.640625f,    -0.236328f,    0.0859375f,
-    0.892578f,    -0.742188f,    0.0302734f,    -0.484375f,    -0.269531f,
-    0.0263672f,   0.913086f,     -0.714844f,    -0.00585938f,  -0.745117f,
-    -0.275391f,   0.0927734f,    0.977539f,     -0.776367f,    -0.078125f,
-    -0.750977f,   -0.155273f,    -0.0341797f,   1.2334f,       -1.06445f,
-    -0.0478516f,  -0.823242f,    -0.196289f,    0.046875f,     1.19141f,
-    -1.00391f,    -0.140625f,    -0.541016f,    0.0917969f,    0.21582f,
-    0.717773f,    -0.764648f,    -0.0341797f,   -0.607422f,    -0.0351562f,
-    0.0888672f,   0.207031f,     -0.214844f,    -0.18457f,     -0.0664062f,
-    -0.0898438f,  0.0556641f,    0.418945f,     -0.232422f,    0.43457f,
-    0.0361328f,   0.143555f,     0.376953f,     1.23633f,      -1.09082f,
-    0.529297f,    0.0507812f,    0.205078f,     0.438477f,     1.66602f,
-    -1.59668f,    0.325195f,     -1.20996f,     -0.0791016f,   0.404297f,
-    1.50977f,     -1.40918f,     0.31543f,      -1.30273f,     -0.0654297f,
-    0.141602f,    0.699219f,     -0.589844f,    0.0732422f,    -0.27832f,
-    0.00488281f,  0.00683594f,   0.0566406f,    -0.0410156f,   -0.0292969f,
-    -0.0234375f,  -0.0488281f,   -0.00195312f,  -0.0292969f,   0.0849609f,
-    -0.139648f,   0.0585938f,    0.677734f,     0.667969f,     1.36523f,
-    -1.11816f,    0.412109f,     0.844727f,     0.142578f,     0.790039f,
-    1.73145f,     -1.68066f,     0.464844f,     -1.29492f,     -0.0800781f,
-    0.803711f,    0.879883f,     -0.765625f,    -0.0400391f,   -0.616211f,
-    -0.170898f,   0.879883f,     0.510742f,     0.158203f,     0.381836f,
-    -0.270508f,   -0.0693359f,   0.651367f,     0.431641f,     0.104492f,
-    0.991211f,    -0.0634766f,   -0.0478516f,   0.750977f,     0.283203f,
-    -0.0332031f,  1.52051f,      -0.00195312f,  -0.201172f,    1.08984f,
-    0.173828f,    0.0849609f,    1.44141f,      -0.214844f,    -0.0107422f,
-    1.29785f,     0.520508f,     0.00488281f,   1.73047f,      -0.523438f,
-    0.136719f,    1.42188f,      0.987305f,     0.0527344f,    1.74707f,
-    -0.525391f,   0.34668f,      0.469727f,     0.428711f,     0.114258f,
-    -0.788086f,   0.177734f,     0.400391f,     -0.106445f,    0.328125f,
-    -0.566406f,   -0.948242f,    0.670898f,     0.467773f,     -0.21875f,
-    0.55957f,     -0.767578f,    -0.232422f,    0.195312f,     0.625f,
-    -0.271484f,   0.865234f,     -0.765625f,    0.299805f,     0.0703125f,
-    0.378906f,    -0.526367f,    0.548828f,     -0.231445f,    -0.569336f,
-    0.455078f,    0.303711f,     -0.866211f,    -0.485352f,    0.566406f,
-    -1.60547f,    0.481445f,     0.183594f,     -0.782227f,    -0.260742f,
-    0.243164f,    -1.41504f,     0.373047f,     0.172852f,     -0.935547f,
-    -0.412109f,   0.133789f,     -1.69727f,     0.178711f,     0.407227f,
-    -0.952148f,   -0.227539f,    0.0751953f,    -1.67188f,     0.339844f,
-    0.498047f,    -0.795898f,    0.209961f,     0.177734f,     -1.3916f,
-    0.458984f,    0.295898f,     0.0390625f,    0.697266f,     0.258789f,
-    -0.0703125f,  -0.131836f,    0.56543f,      0.250977f,     0.913086f,
-    -0.353516f,   0.90332f,      0.191406f,     0.708008f,     0.352539f,
-    0.853516f,    -0.839844f,    0.955078f,     0.636719f,     0.657227f,
-    0.389648f,    0.620117f,     -0.725586f,    0.43457f,      0.485352f,
-    0.424805f,    0.479492f,     0.287109f,     -0.505859f,    -0.209961f,
-    0.0927734f,   0.21582f,      0.709961f,     0.492188f,     -0.413086f,
-    -0.0869141f,  0.0673828f,    -0.119141f,    1.20508f,      0.392578f,
-    0.229492f,    0.927734f,     -0.297852f,    0.142578f,     1.0293f,
-    0.430664f,    0.0449219f,    1.71875f,      -0.0283203f,   0.0107422f,
-    1.18164f,     0.0517578f,    0.0751953f,    1.80273f,      -0.0693359f,
-    -0.19043f,    1.1748f,       0.236328f,     0.0839844f,    1.78711f,
-    -0.472656f,   -0.270508f,    1.10254f,      0.964844f,     0.118164f,
-    1.75684f,     -0.901367f,    -0.211914f,    1.11133f,      0.65625f,
-    0.308594f,    0.142578f,     0.396484f,     0.239258f,     0.0800781f,
-    0.973633f,    -0.824219f,    -0.25293f,     0.485352f,     0.351562f,
-    -0.0771484f,  1.08984f,      -0.632812f,    0.240234f,     -0.258789f,
-    0.436523f,    -0.514648f,    0.491211f,     0.0664062f,    -0.244141f,
-    -0.148438f,   -0.171875f,    -0.477539f,    -0.459961f,    1.1084f,
-    -0.822266f,   -0.114258f,    -0.192383f,    -0.608398f,    -0.771484f,
-    1.11133f,     -1.25488f,     1.01953f,      -0.0839844f,   -0.620117f,
-    -0.794922f,   0.660156f,     -0.876953f,    0.0957031f,    -0.242188f,
-    -0.711914f,   -0.55957f,     0.736328f,     -0.649414f,    -0.0263672f,
-    -0.258789f,   -0.498047f,    -0.973633f,    0.957031f,     -0.660156f,
-    0.186523f,    -0.262695f,    -0.595703f,    -0.787109f,    0.893555f,
-    -0.429688f,   -0.0234375f,   -0.254883f,    -0.449219f,    -0.783203f,
-    0.90918f,     0.106445f,     -0.161133f,    -0.287109f,    -0.0800781f,
-    -0.729492f,   0.933594f,     -0.126953f,    -0.0742188f,   -0.550781f,
-    -0.271484f,   -0.989258f,    1.00098f,      -0.879883f,    0.0234375f,
-    -0.543945f,   -0.50293f,     -1.18945f,     1.24023f,      -1.33398f,
-    0.325195f,    -0.262695f,    -0.307617f,    -0.912109f,    1.39062f,
-    -1.06055f,    0.0107422f,    -0.00292969f,  -0.573242f,    -0.4375f,
-    1.15625f,     -0.651367f,    -0.310547f,    0.188477f,     -0.730469f,
-    -0.121094f,   0.611328f,     -0.779297f,    0.335938f,     0.731445f,
-    -0.475586f,   -0.00390625f,  0.100586f,     -0.693359f,    0.254883f,
-    0.813477f,    -0.345703f,    0.420898f,     -0.400391f,    -0.539062f,
-    0.365234f,    0.720703f,     0.0214844f,    0.673828f,     -0.370117f,
-    0.0585938f,   0.499023f,     0.523438f,     0.198242f,     0.759766f,
-    -0.544922f,   0.543945f,     0.226562f,     0.473633f,     0.34082f,
-    0.595703f,    -0.682617f,    0.292969f,     -0.217773f,    0.0742188f,
-    0.553711f,    0.762695f,     -0.504883f,    0.292969f,     0.0751953f,
-    0.0126953f,   0.427734f,     0.769531f,     -0.265625f,    0.552734f,
-    -0.0175781f,  -0.30957f,     0.253906f,     0.322266f,     0.117188f,
-    0.263672f,    -0.706055f,    -0.991211f,    0.266602f,     0.501953f,
-    0.00585938f,  0.0341797f,    -1.24805f,     -1.21777f,     0.488281f,
-    0.461914f,    0.0986328f,    0.362305f,     -1.1709f,      -1.17188f,
-    0.50293f,     0.458984f,     0.108398f,     0.460938f,     -1.52148f,
-    -1.27051f,    0.379883f,     0.90625f,      0.0400391f,    0.524414f,
-    -1.77832f,    -0.951172f,    0.397461f,     0.589844f,     0.520508f,
-    0.439453f,    -1.99902f,     -0.643555f,    0.313477f,     0.766602f,
-    0.450195f,    0.286133f,     -1.29883f,     -0.375f,       0.225586f,
-    0.697266f,    0.299805f,     0.108398f,     -0.976562f,    0.09375f,
-    0.0361328f,   0.851562f,     -0.210938f,    0.0615234f,    -0.0898438f,
-    0.59082f,     0.313477f,     0.756836f,     -0.731445f,    0.296875f,
-    -0.0927734f,  0.552734f,     0.223633f,     0.558594f,     -0.806641f,
-    0.00195312f,  0.03125f,      0.728516f,     0.276367f,     0.744141f,
-    -0.994141f,   0.197266f,     -0.425781f,    0.316406f,     0.046875f,
-    0.601562f,    -0.633789f,    -0.0576172f,   -0.320312f,    0.786133f,
-    0.0986328f,   1.0f,          -1.19922f,     0.34668f,      -0.546875f,
-    0.481445f,    0.00390625f,   0.876953f,     -1.04297f,     -0.0507812f,
-    -0.775391f,   0.333984f,     -0.0175781f,   1.02539f,      -1.07129f,
-    -0.12207f,    -0.212891f,    0.28125f,      0.00488281f,   0.998047f,
-    -0.97168f,    0.178711f,     -0.444336f,    0.178711f,     0.0136719f,
-    0.896484f,    -0.9375f,      0.0117188f,    -0.291992f,    0.132812f,
-    0.0234375f,   0.975586f,     -0.943359f,    -0.0078125f,   0.0546875f,
-    0.244141f,    -0.0771484f,   1.05469f,      -1.02148f,     0.313477f,
-    -0.349609f,   0.148438f,     0.0839844f,    0.619141f,     -0.75f,
-    -0.589844f,   -0.0488281f,   0.0263672f,    -0.176758f,    0.697266f,
-    -0.691406f,   -0.625977f,    -0.417969f,    0.408203f,     0.265625f,
-    1.01953f,     -1.09863f,     0.106445f,     0.0117188f,    0.157227f,
-    0.424805f,    1.07422f,      -0.816406f,    0.498047f,     0.0996094f,
-    0.00585938f,  0.53418f,      0.771484f,     -0.610352f,    0.744141f,
-    0.0195312f,   0.0478516f,    0.552734f,     0.734375f,     -0.72168f,
-    0.518555f,    -0.144531f,    -0.0361328f,   0.513672f,     0.822266f,
-    -0.736328f,   0.65918f,      -0.179688f,    -0.104492f,    0.425781f,
-    1.00098f,     -0.885742f,    0.739258f,     -0.681641f,    -0.443359f,
-    0.375977f,    0.884766f,     -0.724609f,    0.110352f,     -0.289062f,
-    -0.414062f,   0.494141f,     0.53125f,      -0.422852f,    0.216797f,
-    -0.786133f,   -0.569336f,    0.749023f,     0.75293f,      -0.529297f,
-    0.730469f,    -0.911133f,    -0.68457f,     0.611328f,     0.959961f,
-    -0.623047f,   1.06543f,      -0.499023f,    -0.392578f,    0.761719f,
-    0.43457f,     -0.357422f,    0.631836f,     -0.746094f,    -0.370117f,
-    0.777344f,    0.379883f,     -0.225586f,    0.677734f,     -0.478516f,
-    -0.358398f,   0.788086f,     0.569336f,     -0.34082f,     0.939453f,
-    -0.238281f,   -0.230469f,    0.861328f,     0.448242f,     -0.219727f,
-    0.966797f,    -0.310547f,    -0.242188f,    0.863281f,     0.369141f,
-    -0.0859375f,  0.87207f,      -0.400391f,    -0.385742f,    0.841797f,
-    0.401367f,    -0.0634766f,   0.912109f,     -0.458008f,    0.0107422f,
-    0.753906f,    0.758789f,     -0.675781f,    0.765625f,     -0.342773f,
-    -0.123047f,   0.855469f,     0.599609f,     -0.490234f,    0.963867f,
-    -0.118164f,   -0.0117188f,   0.889648f,     0.637695f,     -0.607422f,
-    0.803711f,    -0.597656f,    -0.242188f,    0.855469f,     0.550781f,
-    -0.607422f,   0.576172f,     -0.759766f,    -0.220703f,    0.832031f,
-    0.477539f,    -0.491211f,    0.470703f,     -0.575195f,    -0.0869141f,
-    1.01074f,     0.371094f,     -0.25293f,     0.678711f,     -0.316406f,
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+	-0.523438f,   0.015625f,     0.0f,	    1.13184f,	   -1.09961f,
+	-0.244141f,   -0.330078f,    -0.115234f,    0.0166016f,	   0.944336f,
+	-0.868164f,   -0.430664f,    -0.246094f,    -0.0185547f,   -0.00976562f,
+	0.819336f,    -0.822266f,    -0.380859f,    -1.1709f,	   0.0605469f,
+	-0.0498047f,  0.777344f,     -0.703125f,    0.0800781f,	   -0.451172f,
+	0.304688f,    0.0517578f,    0.825195f,	    -0.771484f,	   0.145508f,
+	0.495117f,    -0.0888672f,   -0.243164f,    1.48145f,	   -1.22168f,
+	0.0615234f,   -0.192383f,    -0.0537109f,   0.0195312f,	   1.21582f,
+	-1.06836f,    0.175781f,     -0.394531f,    0.237305f,	   -0.0126953f,
+	0.800781f,    -0.920898f,    -0.12207f,	    -0.391602f,	   -0.0917969f,
+	-0.0791016f,  1.08008f,	     -1.03613f,	    -0.0654297f,   -0.423828f,
+	0.0478516f,   -0.0253906f,   0.873047f,	    -0.884766f,	   -0.0722656f,
+	-0.579102f,   0.0136719f,    -0.0917969f,   0.954102f,	   -0.922852f,
+	-0.172852f,   -0.244141f,    0.0f,	    -0.141602f,	   0.929688f,
+	-0.894531f,   -0.179688f,    -0.291992f,    0.0283203f,	   -0.0947266f,
+	0.961914f,    -0.926758f,    -0.135742f,    -0.329102f,	   0.0576172f,
+	-0.0351562f,  0.999023f,     -0.958984f,    -0.0498047f,   -0.248047f,
+	0.0869141f,   -0.078125f,    1.01074f,	    -0.954102f,	   0.00976562f,
+	-0.217773f,   0.0986328f,    -0.0556641f,   0.916992f,	   -0.914062f,
+	-0.136719f,   -0.219727f,    0.0488281f,    -0.139648f,	   0.985352f,
+	-0.952148f,   -0.152344f,    -0.286133f,    0.0166016f,	   -0.0917969f,
+	1.0459f,      -0.972656f,    -0.0605469f,   -0.228516f,	   0.0507812f,
+	-0.0810547f,  0.956055f,     -0.9375f,	    -0.18457f,	   -0.275391f,
+	0.0703125f,   -0.0986328f,   0.948242f,	    -0.928711f,	   -0.162109f,
+	-0.333008f
+};
 const size_t kAccelerometerLaptopModeTestDataLength =
-    ARRAY_SIZE(kAccelerometerLaptopModeTestData);
+	ARRAY_SIZE(kAccelerometerLaptopModeTestData);
 
 const float kAccelerometerFullyOpenTestData[] = {
-    0.892578f,    -0.0810547f,  0.0146484f,    0.929688f,     -0.0644531f,
-    -0.0234375f,  0.996094f,    -0.0136719f,   0.0185547f,    1.02344f,
-    -0.0615234f,  -0.0449219f,  0.978516f,     0.125977f,     0.0400391f,
-    0.996094f,    0.0332031f,   -0.0117188f,   0.963867f,     0.107422f,
-    0.0214844f,   0.980469f,    0.0185547f,    -0.00683594f,  0.952148f,
-    0.0361328f,   0.0253906f,   0.976562f,     -0.00390625f,  -0.0126953f,
-    0.97168f,     0.0205078f,   0.0517578f,    1.01074f,      0.015625f,
-    -0.0234375f,  0.953125f,    -0.000976562f, 0.0390625f,    0.977539f,
-    -0.0224609f,  -0.00976562f, 0.954102f,     0.0244141f,    0.0439453f,
-    0.986328f,    0.00292969f,  -0.000976562f, 0.967773f,     0.0537109f,
-    0.046875f,    0.99707f,     0.0175781f,    -0.000976562f, 0.951172f,
-    0.0390625f,   0.0341797f,   0.974609f,     -0.00878906f,  -0.000976562f,
-    0.948242f,    0.0185547f,   0.0478516f,    0.976562f,     -0.000976562f,
-    -0.00683594f, 0.958984f,    0.0263672f,    0.078125f,     0.982422f,
-    -0.0205078f,  0.0283203f,   0.930664f,     0.00878906f,   0.0664062f,
-    0.970703f,    0.00390625f,  -0.0078125f,   0.945312f,     0.0380859f,
-    -0.00585938f, 0.972656f,    0.0419922f,    -0.0478516f,   1.01953f,
-    0.240234f,    -0.182617f,   1.00977f,      0.18457f,      -0.126953f,
-    1.05566f,     0.0751953f,   -0.0888672f,   1.09766f,      0.0732422f,
-    -0.0898438f,  1.21484f,     0.119141f,     -0.000976562f, 1.23633f,
-    0.194336f,    -0.447266f,   1.31445f,      0.213867f,     -0.118164f,
-    1.30762f,     0.0908203f,   -0.260742f,    0.860352f,     0.141602f,
-    -0.166016f,   0.868164f,    0.0429688f,    -0.258789f,    0.727539f,
-    0.0419922f,   -0.21875f,    0.740234f,     0.0126953f,    -0.162109f,
-    0.652344f,    -0.00292969f, -0.185547f,    0.666992f,     0.0800781f,
-    -0.272461f,   0.852539f,    -0.0478516f,   -0.228516f,    0.819336f,
-    -0.0996094f,  -0.180664f,   0.959961f,     -0.0537109f,   -0.240234f,
-    0.935547f,    -0.0917969f,  -0.269531f,    0.988281f,     -0.0507812f,
-    -0.197266f,   0.981445f,    -0.0712891f,   -0.323242f,    0.964844f,
-    -0.0683594f,  -0.203125f,   0.941406f,     -0.0898438f,   -0.236328f,
-    0.942383f,    -0.0429688f,  -0.206055f,    0.921875f,     -0.0527344f,
-    -0.239258f,   0.976562f,    -0.0742188f,   -0.261719f,    0.958008f,
-    -0.09375f,    -0.311523f,   0.949219f,     -0.0839844f,   -0.242188f,
-    0.949219f,    -0.0742188f,  -0.323242f,    0.973633f,     -0.0263672f,
-    -0.238281f,   0.958984f,    -0.0488281f,   -0.293945f,    0.931641f,
-    -0.0214844f,  -0.225586f,   0.931641f,     0.0195312f,    -0.225586f,
-    0.810547f,    -0.0947266f,  -0.15332f,     0.947266f,     0.241211f,
-    -0.100586f,   0.326172f,    0.286133f,     -0.12207f,     0.855469f,
-    0.677734f,    -0.228516f,   0.229492f,     1.08398f,      0.0224609f,
-    0.822266f,    0.759766f,    -0.0722656f,   0.294922f,     1.42676f,
-    0.147461f,    0.239258f,    0.755859f,     0.142578f,     -0.120117f,
-    1.00977f,     -0.0722656f,  -0.154297f,    0.832031f,     -0.0576172f,
-    -0.15332f,    1.10156f,     -0.0273438f,   -0.119141f,    1.05078f,
-    0.0166016f,   -0.0927734f,  1.09961f,      -0.0703125f,   -0.0751953f,
-    1.04688f,     -0.00195312f, -0.078125f,    0.897461f,     -0.0625f,
-    -0.078125f,   0.854492f,    -0.0947266f,   -0.123047f,    0.811523f,
-    -0.0488281f,  -0.113281f,   0.796875f,     0.0f,          -0.0488281f,
-    0.961914f,    -0.177734f,   -0.0898438f,   0.859375f,     -0.172852f,
-    0.0126953f,   1.1084f,      -0.158203f,    0.0292969f,    1.0791f,
-    -0.152344f,   0.154297f,    1.29492f,      -0.126953f,    0.134766f,
-    1.23145f,     -0.0878906f,  -0.200195f,    0.667969f,     -0.216797f,
-    -0.0888672f,  0.935547f,    -0.143555f,    0.000976562f,  1.13281f,
-    -0.0498047f,  0.00195312f,  1.05469f,      -0.231445f,    0.0927734f,
-    0.956055f,    -0.292969f,   0.0625f,       0.927734f,     -0.112305f,
-    0.0585938f,   0.975586f,    -0.163086f,    0.0957031f,    1.03418f,
-    -0.229492f,   0.000976562f, 0.985352f,     -0.09375f,     -0.00585938f,
-    0.945312f,    -0.140625f,   -0.0302734f,   0.998047f,     -0.208008f,
-    -0.0507812f,  0.916016f,    -0.112305f,    0.123047f,     0.981445f,
-    -0.205078f,   0.129883f,    1.02832f,      -0.211914f,    0.105469f,
-    1.01367f,     -0.142578f,   0.111328f,     1.00098f,      -0.110352f,
-    0.0986328f,   0.999023f,    -0.15918f,     0.0839844f,    0.922852f,
-    -0.223633f,   0.261719f,    1.06641f,      -0.138672f,    0.240234f,
-    0.916016f,    -0.296875f,   0.00488281f,   1.04199f,      -0.128906f,
-    0.0341797f,   1.0791f,      -0.265625f,    0.015625f,     0.963867f,
-    -0.161133f,   0.015625f,    0.958008f,     -0.0722656f,   -0.125f,
-    1.03125f,     -0.19043f,    -0.0722656f,   1.16602f,      -0.126953f,
-    -0.143555f,   1.12793f,     -0.197266f,    -0.120117f,    1.26465f,
-    -0.232422f,   -0.226562f,   1.125f,        -0.0712891f,   -0.0927734f,
-    1.26465f,     -0.145508f,   -0.551758f,    0.90918f,      -0.163086f,
-    -0.228516f,   1.2041f,      -0.0371094f,   -0.493164f,    0.827148f,
-    0.0371094f,   -0.162109f,   0.568359f,     -0.195312f,    -0.641602f,
-    0.438477f,    -0.212891f,   -0.513672f,    0.208008f,     -0.0488281f,
-    -0.776367f,   0.0488281f,   -0.115234f,    -0.84375f,     -0.314453f,
-    0.106445f,    -0.966797f,   -0.0078125f,   0.00976562f,   -1.01953f,
-    -0.220703f,   -0.0322266f,  -0.994141f,    0.0117188f,    -0.248047f,
-    -0.975586f,   0.121094f,    -0.0205078f,   -0.947266f,    0.00292969f,
-    -0.160156f,   -0.9375f,     0.0175781f,    -0.0986328f,   -0.916992f,
-    -0.0195312f,  -0.208008f,   -0.9375f,      -0.0654297f,   -0.134766f,
-    -0.948242f,   -0.0185547f,  -0.231445f,    -0.977539f,    -0.0537109f,
-    -0.198242f,   -1.0166f,     0.0439453f,    -0.433594f,    -0.994141f,
-    -0.0595703f,  -0.389648f,   -1.07129f,     0.0859375f,    -0.109375f,
-    -1.01953f,    0.0966797f,   -0.12207f,     -1.01074f,     0.125977f,
-    -0.192383f,   -1.0f,        0.0820312f,    -0.166016f,    -1.04688f,
-    0.0751953f,   -0.265625f,   -1.00879f,     0.139648f,     -0.135742f,
-    -1.00977f,    0.0644531f,   -0.235352f,    -0.989258f,    0.100586f,
-    -0.144531f,   -0.858398f,   0.0273438f,    -0.22168f,     -0.878906f,
-    -0.0634766f,  -0.1875f,     -0.905273f,    -0.0195312f,   -0.232422f,
-    -0.926758f,   -0.0732422f,  -0.319336f,    -1.05078f,     -0.00878906f,
-    -0.5625f,     -1.05176f,    0.111328f,     -0.456055f,    -0.942383f,
-    -0.0146484f,  -0.171875f,   -0.946289f,    -0.0224609f,   -0.174805f,
-    -0.901367f,   -0.0283203f,  -0.332031f,    -0.948242f,    -0.0732422f,
-    -0.262695f,   -0.867188f,   0.0351562f,    -0.271484f,    -0.913086f,
-    -0.0878906f,  -0.259766f,   -1.2793f,      -0.226562f,    -0.382812f,
-    -1.2334f,     0.0400391f,   -0.260742f,    -1.22949f,     -0.216797f,
-    -0.432617f,   -1.21191f,    -0.131836f,    -0.368164f,    -1.10938f,
-    -0.323242f,   -0.505859f,   -1.01953f,     -0.197266f,    -0.405273f,
-    -1.25488f,    -0.347656f,   -0.448242f,    -0.803711f,    0.0595703f,
-    -0.253906f,   -0.489258f,   -0.00390625f,  0.101562f,     0.15332f,
-    -0.423828f,   -0.0195312f,  0.527344f,     -0.350586f,    -0.24707f,
-    0.363281f,    -1.33789f,    -0.214844f,    0.322266f,     -0.768555f,
-    -0.279297f,   0.266602f,    -0.918945f,    -0.320312f,    0.0634766f,
-    -0.97168f,    -0.102539f,   0.114258f,     -0.891602f,    -0.158203f,
-    0.0283203f,   -0.998047f,   -0.198242f,    0.0634766f,    -0.931641f,
-    -0.239258f,   0.147461f,    -0.963867f,    -0.219727f,    0.142578f,
-    -1.02051f,    -0.279297f,   0.105469f,     -0.955078f,    -0.238281f,
-    0.104492f,    -1.02637f,    -0.291992f,    -0.0302734f,   -1.02637f,
-    -0.225586f,   0.000976562f, -0.907227f,    -0.12793f,     0.03125f,
-    -0.979492f,   -0.100586f,   0.0625f,       -0.921875f,    -0.155273f,
-    0.146484f,    -0.929688f,   -0.158203f,    0.155273f,     -0.981445f,
-    -0.171875f,   0.212891f,    -0.927734f,    -0.166992f,    0.198242f,
-    -1.05371f,    -0.197266f,   0.189453f,     -0.954102f,    -0.113281f,
-    0.189453f,    -1.00293f,    -0.180664f,    0.111328f,     -0.967773f,
-    -0.109375f,   0.125977f,    -0.966797f,    -0.146484f,    0.0712891f,
-    -0.982422f,   -0.0908203f,  0.112305f,     -0.928711f,    -0.149414f,
-    0.0146484f,   -1.00781f,    -0.0996094f,   0.102539f,     -0.810547f,
-    -0.157227f,   -0.0117188f,  -0.820312f,    -0.0371094f,   0.28418f,
-    -0.446289f,   -0.166016f,   0.208008f,     -0.03125f,     -0.0761719f,
-    0.755859f,    -0.280273f,   -0.316406f,    1.42188f,      0.198242f,
-    -0.49707f,    1.37207f,     -0.556641f,    -0.382812f,    1.36523f,
-    0.110352f,    -0.342773f,   1.25391f,      -0.225586f,    -0.570312f,
-    0.958984f,    0.0722656f,   -0.237305f,    0.984375f,     0.0957031f,
-    -0.416992f,   0.853516f,    0.0400391f,    -0.416016f,    0.873047f,
-    0.0644531f,   -0.370117f,   1.04004f,      0.0273438f,    -0.408203f,
-    0.920898f,    -0.0986328f,  -0.514648f,    0.956055f,     0.0527344f,
-    -0.428711f,   0.960938f,    0.109375f,     -0.522461f,    0.801758f,
-    -0.277344f,   -0.634766f,   0.882812f,     0.0527344f,    -0.34668f,
-    0.981445f,    -0.09375f,    -0.298828f,    0.952148f,     -0.213867f,
-    -0.25293f,    0.90918f,     -0.132812f,    -0.493164f,    0.885742f,
-    -0.177734f,   -0.525391f,   0.915039f,     -0.0605469f,   -0.439453f,
-    0.87207f,     -0.0986328f,  -0.506836f,    0.905273f,     -0.0732422f,
-    -0.462891f,   0.870117f,    -0.0966797f,   -0.511719f,    0.897461f,
-    -0.0234375f,  -0.464844f,   0.868164f,     -0.0283203f,   -0.474609f,
-    0.919922f,    0.0205078f,   -0.34375f,     0.889648f,     -0.00390625f,
-    -0.445312f,   0.804688f,    -0.0263672f,   -0.417969f,    0.806641f,
-    0.0410156f,   -0.399414f,   0.914062f,     -0.0722656f,   -0.386719f,
-    0.890625f,    -0.0615234f,  -0.40625f,     0.928711f,     0.0253906f,
-    -0.118164f,   0.943359f,    -0.000976562f, -0.398438f,    0.811523f,
-    -0.0605469f,  -0.234375f,   0.879883f,     0.198242f,     -0.509766f,
-    0.958008f,    0.0361328f,   -0.328125f,    0.938477f,     -0.00976562f,
-    -0.429688f,   0.916016f,    -0.0185547f,   -0.266602f,    0.898438f,
-    -0.0380859f,  -0.450195f,   0.870117f,     0.162109f,     -0.210938f,
-    0.899414f,    0.117188f,    -0.517578f,    0.756836f,     -0.0820312f,
-    -0.361328f,   0.868164f,    -0.0576172f,   -1.29883f,     0.515625f,
-    -0.00195312f, -1.13281f,    0.628906f,     0.00390625f,   -0.103516f,
-    0.485352f,    -0.046875f,   -0.922852f,    0.412109f,     -0.108398f,
-    -0.898438f,   0.446289f,    -0.111328f,    -0.925781f,    0.375977f,
-    -0.125977f,   -0.825195f,   0.446289f,     -0.0966797f,   -0.958008f,
-    0.389648f,    -0.0810547f,  -1.00781f,     0.532227f,     -0.104492f,
-    -1.0791f,     0.459961f,    -0.138672f,    -0.941406f,    0.509766f,
-    -0.107422f,   -1.14062f,    0.447266f,     -0.195312f,    -0.867188f,
-    0.474609f,    -0.233398f,   -0.751953f,    0.612305f,     -0.126953f,
-    -0.661133f,   0.702148f,    -0.199219f,    -0.260742f,    0.856445f,
-    -0.0292969f,  -0.743164f,   0.921875f,     -0.0371094f,   -0.293945f,
-    0.902344f,    -0.103516f,   -0.416016f,    0.955078f,     -0.00488281f,
-    -0.232422f,   0.951172f,    -0.0498047f,   -0.331055f,    0.871094f,
-    0.00390625f,  -0.186523f,   0.905273f,     0.0566406f,    -0.249023f,
-    0.677734f,    0.0253906f,   0.145508f,     0.826172f,     0.251953f,
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+	0.0136719f,   -0.492188f,   -0.779297f,	   -1.49316f,	  0.0957031f,
+	-0.179688f,   -0.587891f,   0.665039f,	   0.398438f,	  -0.980469f,
+	0.428711f,    0.254883f,    -0.828125f,	   0.724609f,	  0.663086f,
+	-0.90625f,    0.555664f,    0.0791016f,	   -0.837891f,	  0.591797f,
+	0.257812f,    -0.806641f,   0.609375f,	   0.0458984f,	  -0.779297f,
+	0.529297f,    0.00292969f,  -0.829102f,	   0.640625f,	  0.0371094f,
+	-0.797852f,   0.583008f,    0.208984f,	   -0.864258f,	  0.583984f,
+	-0.0615234f,  -0.758789f,   0.72168f,	   0.0947266f,	  -0.921875f,
+	0.605469f,    -0.264648f,   -0.75293f,	   0.701172f,	  0.107422f,
+	-0.735352f,   0.44043f,	    -0.527344f,	   -0.398438f,	  0.46875f,
+	-0.421875f,   -0.424805f,   0.0810547f,	   -0.754883f,	  -0.241211f,
+	-0.107422f,   -1.13574f,    -0.410156f,	   -0.0400391f,	  -0.942383f,
+	-0.454102f,   -0.12207f,    -1.24902f,	   -0.509766f,	  -0.393555f,
+	-0.959961f,   -0.511719f,   -0.381836f,	   -1.04883f,	  -0.924805f,
+	-0.756836f,   -1.17969f,    -0.521484f,	   -0.105469f,	  -1.16504f,
+	-0.767578f,   -0.477539f,   -0.401367f,	   -0.0341797f,	  -0.341797f,
+	0.0507812f,   0.389648f,    -0.507812f,	   0.186523f,	  0.438477f,
+	-1.33594f,    0.625977f,    0.518555f,	   -0.671875f,	  0.182617f,
+	0.432617f,    -1.18359f,    0.132812f,	   0.414062f,	  -0.782227f,
+	0.0615234f,   0.401367f,    -1.30176f,	   -0.0683594f,	  -0.100586f,
+	-0.586914f,   0.0302734f,   0.191406f,	   -0.983398f,	  -0.0273438f,
+	-0.735352f,   -0.224609f,   -0.342773f,	   -0.241211f,	  -0.566406f,
+	0.015625f,    -1.1084f,	    -0.00976562f,  -0.652344f,	  -0.75293f,
+	0.239258f,    -0.449219f,   -1.08789f,	   0.107422f,	  -0.572266f,
+	-0.887695f,   0.407227f,    -0.423828f,	   -0.919922f,	  0.173828f,
+	-0.705078f,   -0.825195f,   0.411133f,	   -0.484375f,	  -0.799805f,
+	0.237305f,    -0.776367f,   -0.745117f,	   0.459961f,	  -0.819336f,
+	-0.749023f,   0.208008f,    -0.788086f,	   -0.716797f,	  0.226562f,
+	-0.795898f,   -0.72168f,    0.123047f,	   -0.790039f,	  -0.705078f,
+	0.101562f,    -0.720703f,   -0.745117f,	   -0.0517578f,	  -0.771484f,
+	-0.701172f,   -0.0175781f,  -0.758789f,	   -0.765625f,	  -0.0917969f,
+	-0.745117f,   -0.751953f,   -0.149414f,	   -0.6875f,	  -0.660156f,
+	-0.0166016f,  -0.782227f,   -0.592773f,	   -0.0205078f,	  -0.726562f,
+	-0.376953f,   0.119141f,    -0.599609f,	   -0.371094f,	  0.0107422f,
+	-0.736328f,   -0.325195f,   0.0771484f,	   -0.768555f,	  -0.388672f,
+	-0.0273438f,  -0.750977f,   -0.477539f,	   0.107422f,	  -0.919922f,
+	-0.514648f,   0.125f,	    -0.961914f,	   -0.37793f,	  0.0136719f,
+	-0.981445f,   -0.447266f,   -0.0107422f,   -0.823242f,	  -0.303711f,
+	0.0986328f,   -1.00684f,    -0.366211f,	   0.0986328f,	  -1.14551f,
+	-0.239258f,   0.140625f,    -0.894531f,	   -0.297852f,	  0.0849609f,
+	-0.949219f,   -0.341797f,   0.131836f,	   -0.966797f,	  -0.380859f,
+	0.0947266f,   -0.75293f,    -0.391602f,	   0.0839844f,	  -0.908203f,
+	-0.40625f,    0.161133f,    -0.860352f,	   -0.452148f,	  0.1875f,
+	-0.950195f,   -0.496094f,   0.200195f,	   -0.828125f,	  -0.581055f,
+	0.0771484f,   -0.93457f,    -0.607422f,	   0.0996094f,	  -0.863281f,
+	-0.59375f,    0.0927734f,   -0.802734f,	   -0.604492f,	  0.0947266f,
+	-0.807617f,   -0.722656f,   0.101562f,	   -0.844727f,	  -0.711914f,
+	0.149414f,    -1.03125f,    -0.77832f,	   0.125977f,	  -0.78418f,
+	-0.740234f,   0.121094f,    -0.891602f,	   -0.808594f,	  0.164062f,
+	-0.650391f,   -0.80957f,    0.0888672f,	   -0.416992f,	  -0.866211f,
+	0.155273f,    -0.382812f,   -0.880859f,	   0.0849609f,	  -0.264648f,
+	-0.775391f,   0.229492f,    -0.389648f,	   -0.814453f,	  0.0664062f,
+	-0.226562f,   -0.625f,	    0.414062f,	   -0.274414f,	  -0.681641f,
+	0.0292969f,   -0.0478516f,  -0.711914f,	   0.794922f,	  -0.388672f,
+	-0.584961f,   0.368164f,    -0.257812f,	   -0.545898f,	  1.09277f,
+	-0.277344f,   -0.125977f,   0.822266f,	   -0.365234f,	  -0.467773f,
+	0.714844f,    -0.413086f,   -0.136719f,	   1.57227f,	  -0.0947266f,
+	-0.223633f,   0.817383f,    -0.0556641f,   -0.0322266f,	  1.18945f,
+	-0.191406f,   -0.498047f,   0.991211f,	   -0.231445f,	  -0.246094f,
+	0.8125f,      -0.239258f,   -0.755859f,	   0.853516f,	  -0.228516f,
+	-0.821289f,   0.503906f,    -0.121094f,	   -0.795898f,	  0.523438f,
+	-0.220703f,   -0.773438f,   0.517578f,	   -0.274414f,	  -0.757812f,
+	0.539062f,    -0.222656f,   -0.770508f,	   0.396484f,	  -0.115234f,
+	-1.2334f,     0.485352f,    -0.217773f,	   -0.94043f,	  1.01758f,
+	-0.202148f,   -0.605469f,   0.0546875f,	   0.0957031f,	  -0.639648f,
+	-0.661133f,   0.245117f,    -0.750977f,	   0.0615234f,	  -0.726562f,
+	-0.879883f,   -0.432617f,   -1.05859f,	   -1.29688f,	  0.00488281f,
+	0.193359f,    -0.939453f,   0.209961f,	   -0.209961f,	  -0.793945f,
+	0.251953f,    0.722656f,    -0.447266f,	   0.0615234f,	  0.855469f,
+	-0.454102f,   -0.0126953f,  0.0527344f,	   -0.342773f,	  0.154297f,
+	1.3877f,      -0.65918f,    0.133789f,	   0.0576172f,	  -0.233398f,
+	-0.12207f,    0.46582f,	    -1.09961f,	   0.438477f,	  -0.641602f,
+	-0.861328f,   0.197266f,    -1.99902f,	   -0.932617f,	  0.234375f,
+	0.389648f,    -0.792969f,   -0.0908203f,   1.66797f,	  -1.0459f,
+	0.0107422f,   -0.543945f,   -0.80957f,	   0.206055f,	  -0.27832f,
+	-0.915039f,   0.104492f,    -0.301758f,	   -0.891602f,	  0.0556641f,
+	-0.681641f,   -0.901367f,   0.0498047f,	   -0.461914f,	  -0.927734f,
+	-0.0390625f,  -0.229492f,   -1.04004f,	   0.0869141f,	  -0.435547f,
+	-1.02148f,    0.0947266f,   -0.527344f,	   -0.979492f,	  0.0751953f,
+	0.266602f,    -0.786133f,   -0.0224609f,   -0.0947266f,	  -0.702148f,
+	-0.00683594f, -0.316406f,   -0.698242f,	   -0.317383f,	  1.92578f,
+	-1.0498f,     0.0273438f,   -1.14258f,	   -0.226562f,	  0.233398f,
+	-0.995117f,   -0.9375f,	    0.0146484f,	   -0.223633f,	  -0.49707f,
+	-0.0078125f,  -1.95703f,    -0.847656f,	   0.157227f,	  0.129883f,
+	-0.459961f,   -0.114258f,   2.0f,	   -1.13574f,	  -0.0839844f,
+	-0.0878906f,  -0.783203f,   0.131836f,	   -0.803711f,	  -0.90332f,
+	0.208984f,    -0.365234f,   -0.97168f,	   -0.0322266f,	  0.186523f,
+	-0.924805f,   0.00292969f,  -0.272461f,	   -0.890625f,	  0.015625f,
+	-0.333008f,   -0.932617f,   0.180664f,	   -0.459961f,	  -0.90918f,
+	0.240234f,    -0.625977f,   -1.1582f,	   0.0996094f,	  -0.170898f,
+	-1.08887f,    -0.00976562f, -0.849609f,	   -0.430664f,	  0.139648f,
+	-0.308594f,   -0.572266f,   -0.722656f,	   1.83496f,	  -1.00977f,
+	0.387695f,    0.487305f,    -0.268555f,	   0.0712891f,	  -0.0136719f,
+	-1.5332f,     0.290039f,    -0.0351562f,   -0.861328f,	  1.98535f,
+	-1.16602f,    -0.602539f,   0.441406f,	   0.175781f,	  -0.605469f,
+	-0.831055f,   0.686523f,    -0.984375f,	   0.494141f,	  -0.489258f,
+	-0.895508f,   0.371094f,    -0.665039f,	   -1.14258f,	  -0.214844f,
+	-0.140625f,   -1.06348f,    -0.0996094f,   0.255859f,	  -0.874023f,
+	0.193359f,    -0.0947266f,  -0.959961f,	   -0.0966797f,	  0.00195312f,
+	-0.996094f,   -0.0117188f,  -0.174805f,	   -0.962891f,	  0.106445f,
+	-0.162109f,   -1.04297f,    -0.0283203f,   -0.306641f,	  -1.06738f,
+	-0.0224609f,  -0.129883f,   -1.03223f,	   0.129883f,	  0.195312f,
+	-1.08789f,    -0.130859f,   0.649414f,	   -0.572266f,	  -0.0136719f,
+	-0.793945f,   -0.382812f,   0.0f,	   -1.08301f,	  -0.78125f,
+	-0.0224609f,  -0.339844f,   -0.629883f,	   -0.0947266f,	  -1.83789f,
+	-1.01562f,    0.046875f,    0.223633f,	   -0.808594f,	  0.0957031f,
+	1.09766f,     -0.756836f,   -0.0488281f,   0.157227f,	  -0.59082f,
+	-0.103516f,   0.929688f,    -0.816406f,	   -0.0322266f,	  -0.426758f,
+	-0.868164f,   -0.209961f,   -1.99902f,	   -0.986328f,	  -0.00878906f,
+	-0.365234f,   -0.980469f,   0.0439453f,	   0.59375f,	  -0.994141f,
+	0.0253906f,   0.0371094f,   -0.970703f,	   -0.0273438f,	  -0.120117f,
+	-0.935547f,   0.00195312f,  -0.235352f,	   -0.952148f,	  -0.0263672f,
+	-0.194336f,   -0.917969f,   -0.0195312f,   -0.261719f,	  -0.928711f,
+	-0.0234375f,  -0.219727f,   -0.945312f,	   0.0107422f,	  -0.228516f,
+	-0.938477f,   0.00683594f,  -0.178711f,	   -0.791016f,	  0.03125f,
+	-0.255859f,   -0.789062f,   0.0f,	   -0.141602f,	  -0.789062f,
+	0.232422f,    -0.285156f,   -0.788086f,	   0.228516f,	  -0.28125f,
+	-1.0f,	      0.258789f,    -0.277344f,	   -0.999023f,	  0.28125f,
+	-0.25293f,    -1.06152f,    0.046875f,	   -0.421875f,	  -1.07715f,
+	0.0390625f,   -0.224609f,   -0.923828f,	   -0.0205078f,	  -0.335938f,
+	-0.984375f,   -0.0966797f,  -0.34668f,	   -0.990234f,	  -0.191406f,
+	-0.301758f,   -1.03613f,    -0.241211f,	   -0.37207f,	  -0.975586f,
+	-0.267578f,   -0.460938f,   -1.00977f,	   -0.320312f,	  -0.382812f,
+	-0.913086f,   -0.257812f,   -0.457031f,	   -0.925781f,	  -0.256836f,
+	-0.34668f,    -0.889648f,   -0.237305f,	   -0.393555f,	  -0.897461f,
+	-0.239258f,   -0.429688f,   -0.844727f,	   -0.21875f,	  -0.428711f,
+	-0.87207f,    -0.203125f,   -0.368164f,	   -0.84668f,	  -0.101562f,
+	-0.423828f,   -0.875977f,   -0.165039f,	   -0.363281f,	  -0.884766f,
+	-0.0625f,     -0.473633f,   -0.90332f,	   -0.078125f,	  -0.138672f,
+	-0.918945f,   -0.198242f,   -0.25f,	   -0.928711f,	  -0.138672f,
+	-0.267578f,   -1.08203f,    0.00488281f,   -0.575195f,	  -1.125f,
+	-0.0332031f,  -0.4375f,	    -0.924805f,	   0.078125f,	  -0.305664f,
+	-0.93457f,    -0.0166016f,  -0.475586f,	   -0.94043f,	  -0.00488281f,
+	-0.533203f,   -0.956055f,   0.00292969f,   -0.391602f,	  -1.00293f,
+	0.0361328f,   -0.711914f,   -1.0166f,	   0.0332031f,	  -0.448242f,
+	-0.806641f,   -0.21582f,    -0.556641f,	   -0.759766f,	  -0.0214844f,
+	-0.626953f,   -0.700195f,   -0.263672f,	   -0.308594f,	  -0.608398f,
+	-0.236328f,   -0.253906f,   -0.616211f,	   -0.378906f,	  0.224609f,
+	-0.498047f,   -0.399414f,   0.206055f,	   -0.516602f,	  -0.228516f,
+	0.743164f,    -0.174805f,   -0.125f,	   0.760742f,	  -0.0214844f,
+	-0.135742f,   0.966797f,    0.240234f,	   0.0332031f,	  1.01855f,
+	0.105469f,    0.15332f,	    0.950195f,	   0.240234f,	  0.0732422f,
+	1.16895f,     0.245117f,    0.206055f,	   0.952148f,	  0.273438f,
+	-0.0390625f,  1.2793f,	    0.404297f,	   0.303711f,	  0.720703f,
+	0.369141f,    0.0966797f,   0.918945f,	   0.329102f,	  0.0390625f,
+	0.991211f,    0.397461f,    -0.124023f,	   0.866211f,	  0.210938f,
+	0.130859f,    1.08789f,	    0.317383f,	   0.0537109f,	  0.858398f,
+	0.245117f,    0.0732422f,   0.741211f,	   0.419922f,	  0.0302734f,
+	0.681641f,    0.485352f,    -0.0214844f,   0.641602f,	  0.520508f,
+	-0.129883f,   0.839844f,    0.490234f,	   0.00390625f,	  0.676758f,
+	0.581055f,    -0.0146484f,  0.692383f,	   0.432617f,	  -0.0371094f,
+	0.807617f,    0.664062f,    0.255859f,	   0.216797f,	  1.22559f,
+	0.0195312f,   1.22168f,	    1.2793f,	   -0.405273f,	  1.72559f,
+	0.708984f,    -0.209961f,   0.579102f,	   0.821289f,	  0.0380859f,
+	0.605469f,    0.80957f,	    0.147461f,	   0.419922f,	  0.869141f,
+	0.0390625f,   0.5625f,	    0.786133f,	   0.0654297f,	  0.594727f,
+	0.879883f,    0.0166016f,   0.480469f,	   0.835938f,	  0.00195312f,
+	0.414062f,    0.899414f,    -0.03125f,	   0.344727f,	  0.889648f,
+	0.0185547f,   0.236328f,    0.932617f,	   -0.00585938f,  0.255859f,
+	0.910156f,    0.0898438f,   0.262695f,	   0.945312f,	  0.0126953f,
+	0.279297f,    0.860352f,    0.0507812f,	   0.322266f,	  0.913086f,
+	0.00195312f,  0.296875f,    0.875977f,	   0.0078125f,	  0.373047f,
+	0.922852f,    -0.0244141f,  0.267578f,	   0.884766f,	  0.0117188f,
+	0.347656f,    0.926758f,    -0.0371094f,   0.266602f,	  0.894531f,
+	-0.00683594f, 0.345703f,    0.926758f,	   -0.0478516f,	  0.269531f,
+	0.887695f,    0.0146484f,   0.360352f,	   0.927734f,	  -0.03125f,
+	0.272461f
+};
 const size_t kAccelerometerFullyOpenTestDataLength =
-    ARRAY_SIZE(kAccelerometerFullyOpenTestData);
+	ARRAY_SIZE(kAccelerometerFullyOpenTestData);
diff --git a/test/motion_angle_data_literals_tablet.c b/test/motion_angle_data_literals_tablet.c
index 456779f457..f5b00f5fba 100644
--- a/test/motion_angle_data_literals_tablet.c
+++ b/test/motion_angle_data_literals_tablet.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,1030 +11,1030 @@
  * The arrays contain actual accelerator readings.
  */
 const float kAccelerometerVerticalHingeTestData[] = {
-    -0.0766145f,  6.02381f,     7.85298f,     -0.268151f,   -8.84897f,
-    -1.3216f,     -0.402226f,   5.11401f,     8.77236f,     -1.10133f,
-    -10.1706f,    1.24498f,     -1.18752f,    6.40688f,     8.0924f,
-    -2.60489f,    -8.99262f,    2.58574f,     0.632069f,    9.05008f,
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+	0.47884f,     -1.47483f,    -9.22246f,	  1.25456f,	1.76213f,
+	-8.88728f,    -1.42694f,    -2.36547f,	  -10.1227f,	2.24097f,
+	2.09732f,     -9.09797f,    -2.35589f,	  -3.11246f,	-9.84496f,
+	2.75812f,     2.1069f,	    -9.26077f,	  -2.98796f,	-2.33674f,
+	-9.01178f,    0.0766145f,   4.2138f,	  -8.45632f,	1.02472f,
+	-3.69665f,    -8.51378f,    -0.344765f,	  3.95522f,	-8.90643f,
+	2.00155f,     -3.78284f,    -9.05966f,	  -0.497994f,	3.50511f,
+	-9.42358f,    1.86748f,	    -3.62003f,	  -9.68215f,	-0.488417f,
+	3.74453f,     -9.48104f,    1.69509f,	  -3.18908f,	-9.93115f,
+	-0.871489f,   3.54342f,	    -9.68215f,	  2.03986f,	-2.8922f,
+	-9.85453f,    -0.861913f,   3.16035f,	  -9.81623f,	2.08774f,
+	-2.66235f,    -9.95988f,    -0.852336f,	  2.74854f,	-9.59596f,
+	1.83875f,     -2.15478f,    -10.0652f,	  -0.622492f,	2.28886f,
+	-9.5385f,     1.46525f,	    -2.18351f,	  -9.67257f,	-0.632069f,
+	2.01113f,     -9.43316f,    1.3216f,	  -1.67594f,	-9.42358f,
+	-0.679953f,   1.05345f,	    -9.45231f,	  1.5706f,	-1.23541f,
+	-9.2895f,     -0.459687f,   1.39821f,	  -9.5385f,	1.46525f,
+	-1.16837f,    -9.58638f,    -0.316035f,	  1.47483f,	-9.54808f,
+	1.20668f,     -1.26414f,    -9.60554f,	  -0.411803f,	1.39821f,
+	-9.31823f,    1.14922f,	    -1.14922f,	  -9.76834f,	-0.354342f,
+	1.35991f,     -9.52892f,    1.11091f,	  -1.35991f,	-9.81623f,
+	0.0574608f,   1.46525f,	    -9.663f,	  0.833182f,	-1.1971f,
+	-9.80665f,    0.21069f,	    1.62806f,	  -9.70131f,	0.641646f,
+	-1.24498f,    -9.9503f,	    0.497994f,	  1.53229f,	-9.88326f,
+	0.325611f,    -1.05345f,    -9.86411f,	  0.565032f,	1.58017f,
+	-9.87369f,    0.220267f,    -1.24498f,	  -9.94073f,	0.268151f,
+	1.97282f,     -9.91199f,    0.584185f,	  -1.35033f,	-9.25119f,
+	0.306458f,    1.13006f,	    -9.46189f,	  0.383072f,	-1.11091f,
+	-8.97347f,    -0.0670376f,  1.22583f,	  -8.98304f,	0.459687f,
+	-0.488417f,   -9.30866f,    -0.737414f,	  1.23541f,	-9.13627f,
+	1.00556f,     -0.526724f,   -10.6781f,	  -0.775721f,	0.373495f,
+	-10.5919f,    1.13964f,	    0.42138f,	  -9.54808f,	-2.07817f,
+	0.68953f,     -9.26077f,    1.82917f,	  -0.105345f,	-9.03093f,
+	-0.976834f,   0.430956f,    -9.47146f,	  0.995988f,	-0.181959f,
+	-9.86411f,    -0.23942f,    0.124498f,	  -9.73004f,	0.153229f,
+	0.871489f,    -9.97903f,    -0.220267f,	  0.162806f,	-9.59596f,
+	0.153229f,    0.430956f,    -9.8258f,	  -0.114922f,	0.0957681f,
+	-9.76834f,    0.00957681f,  -0.0287304f,  -10.1801f,	-0.268151f,
+	0.258574f,    -10.0844f,    0.23942f,	  0.0766145f,	-10.1131f,
+	0.794875f,    0.0f,	    -9.86411f,	  -0.593762f,	0.909797f,
+	-9.29908f,    -2.09732f,    1.72383f,	  -9.17458f,	1.89621f,
+	-1.58975f,    -8.91601f,    -2.16436f,	  1.94409f,	-9.1267f,
+	2.03986f,     -1.96325f,    -9.30866f,	  -2.42293f,	2.02071f,
+	-9.43316f,    2.26013f,	    -1.38864f,	  -9.8258f,	-2.2697f,
+	1.16837f,     -9.44273f,    2.16436f,	  -1.09176f,	-9.14585f,
+	-2.03986f,    1.26414f,	    -9.01178f,	  1.82917f,	-1.28329f,
+	-8.89685f,    -2.09732f,    1.64721f,	  -8.95431f,	1.93451f,
+	-1.69509f,    -8.8777f,	    -2.19309f,	  1.28329f,	-9.03093f,
+	2.11647f,     -1.40779f,    -9.31823f,	  -2.2697f,	1.09176f,
+	-9.11712f,    2.06859f,	    -1.3216f,	  -9.2895f,	-2.21224f,
+	1.4461f,      -9.165f,	    2.00155f,	  -1.48441f,	-8.98304f,
+	-2.20267f,    1.46525f,	    -8.83939f,	  2.00155f,	-1.24498f,
+	-9.14585f,    -2.26013f,    1.43652f,	  -9.01178f,	2.1069f,
+	-1.45567f,    -9.1267f,	    -2.29843f,	  1.63763f,	-9.04051f,
+	2.12605f,     -1.76213f,    -9.18416f,	  -2.27928f,	1.9824f,
+	-9.09797f,    2.07817f,	    -1.79086f,	  -9.08839f,	-2.00155f,
+	1.79086f,     -9.44273f,    1.87705f,	  -1.62806f,	-9.14585f,
+	-2.31759f,    1.84832f,	    -8.86812f,	  2.06859f,	1.61848f,
+	-9.165f,      -2.24097f,    2.05901f,	  -9.0022f,	2.02071f,
+	-1.7334f,     -9.04051f,    -2.1452f,	  2.04944f,	-9.2895f,
+	2.06859f,     -1.70467f,    -9.20331f,	  -2.22182f,	2.06859f,
+	-9.33739f,    2.09732f,	    -1.76213f,	  -9.34696f,	-2.13563f,
+	1.99198f,     -9.1267f,	    1.9824f,	  -1.84832f,	-8.88728f,
+	-1.79086f,    1.55144f,	    -9.03093f,	  1.62806f,	-1.61848f,
+	-9.1267f,     -1.58975f,    1.47483f,	  -9.19373f,	1.49398f,
+	-1.47483f,    -8.92558f,    -1.48441f,	  1.76213f,	-8.69574f,
+	1.18752f,     -1.76213f,    -9.24162f,	  -1.35991f,	1.49398f,
+	-9.48104f,    1.23541f,	    -1.61848f,	  -9.51935f,	1.86748f,
+	2.00155f,     -8.71489f,    -1.24498f,	  -2.11647f,	-5.6982f,
+	8.15944f,     1.27372f,	    -4.52983f,	  -7.99663f,	-0.775721f,
+	-4.00311f,    8.31267f,	    0.632069f,	  -3.68707f,	-8.03494f,
+	0.344765f,    -2.16436f,    7.79552f,	  3.7158f,	-1.7334f,
+	-7.74764f,    -4.22337f,    -1.56102f,	  8.78193f,	4.39575f,
+	-1.58017f,    -8.76278f,    -4.5011f,	  -1.72383f,	9.05008f,
+	5.25767f,     -1.93451f,    -9.11712f,	  -3.9648f,	-0.995988f,
+	7.97748f,     5.34386f,	    -1.33118f,	  -7.92002f,	-4.03184f,
+	-0.670376f,   9.17458f,	    4.3766f,	  0.220267f,	-9.60554f,
+	-4.13718f,    -0.746991f,   7.33583f,	  5.34386f,	-1.1971f,
+	-7.28795f,    -5.14275f,    0.871489f,	  7.90087f,	5.80354f,
+	0.584185f,    -8.33182f,    -3.04542f,	  0.986411f,	7.59441f,
+	6.49307f,     -0.0670376f,  -7.85298f,	  -5.92804f,	2.07817f,
+	8.83939f,     5.4109f,	    0.325611f,	  -9.59596f,	-3.83072f,
+	0.718261f,    7.38372f,	    5.99508f,	  0.248997f,	-8.29351f,
+	-5.10444f,    1.72383f,	    7.83383f,	  5.85143f,	2.12605f,
+	-9.15543f,    -4.03184f,    2.05901f,	  7.37414f,	5.79397f,
+	2.19309f,     -8.49463f,    -4.95121f,	  2.13563f,	7.91044f,
+	4.29999f,     2.1452f,	    -8.76278f,	  -2.24097f,	1.31202f,
+	8.59997f,     5.72693f,	    0.746991f,	  -9.55765f,	-3.54342f,
+	1.36948f,     8.5042f,	    5.09486f,	  1.17795f,	-9.62469f,
+	-4.1276f,     1.77171f,	    8.69574f,	  5.46836f,	1.63763f,
+	-9.40442f,    -2.32716f,    1.91536f,	  7.75721f,	5.25767f,
+	2.04944f,     -8.81066f,    -2.40378f,	  0.392649f,	7.73806f,
+	5.63116f,     1.45567f,	    -9.24162f,	  -1.49398f,	-0.258574f,
+	6.82826f,     7.34541f,	    -0.42138f,	  -9.07881f,	-1.30245f,
+	-0.517148f,   6.97192f,	    7.6806f,	  -0.890643f,	-9.58638f,
+	-4.81713f,    -0.21069f,    3.13162f,	  9.20331f,	-0.967257f,
+	-10.0748f,    0.181959f,    -0.948104f,	  -5.9855f,	7.4316f,
+	-1.00556f,    -9.5385f,	    0.497994f,	  0.162806f,	-8.47547f,
+	4.32872f,     0.248997f,    -9.165f,	  -2.27928f,	0.143652f,
+	-8.6287f,     4.47237f,	    0.354342f,	  -9.51935f,	0.986411f,
 };
 
 const size_t kAccelerometerVerticalHingeTestDataLength =
-    ARRAY_SIZE(kAccelerometerVerticalHingeTestData);
+	ARRAY_SIZE(kAccelerometerVerticalHingeTestData);
 
 const float kAccelerometerVerticalHingeUnstableTestData[] = {
-    8.5904f,   -1.36948f,  -3.74453f,   8.72447f,  1.1971f,    4.00311f,
-    8.80109f,  -3.08373f,  2.27928f,    8.95431f,  -1.90578f,  -1.10133f,
-    8.93516f,  -2.03986f,  0.248997f,   9.05008f,  1.53229f,   -0.708684f,
-    -8.78193f, 1.43652f,   -2.63362f,   -8.66701f, 0.220267f,  2.79643f,
-    -8.66701f, -2.06859f,  2.42293f,    -8.79151f, -2.88262f,  -1.16837f,
-    8.74362f,  -1.9824f,   3.53384f,    9.04051f,  0.0574608f, -1.36948f,
-    8.78193f,  -4.1276f,   2.58574f,    8.8777f,   0.201113f,  -1.80044f,
-    8.70532f,  -0.296881f, 1.52271f,    9.02135f,  -0.871489f, -2.43251f,
-    -9.09797f, -1.3216f,   -3.60088f,   -8.97347f, 2.52828f,   2.6432f,
-    -8.82024f, 1.87705f,   0.354342f,   -7.93917f, -4.38618f,  0.258574f,
-    -8.81066f, 1.91536f,   -2.92093f,   -8.04452f, -5.4492f,   3.28484f,
-    -8.86812f, 2.05901f,   0.890643f,   -8.01579f, -5.65989f,  -2.20267f,
-    -9.0022f,  2.18351f,   -2.9305f,    -8.80109f, -4.01268f,  3.055f,
-    -9.37569f, -1.04387f,  0.277727f,   -6.80911f, 2.806f,     -6.0717f,
-    -8.79151f, -8.79151f,  -2.11647f,   -8.6287f,  -1.53229f,  3.58173f,
-    -8.97347f, -0.335188f, 1.26414f,    8.5042f,   1.51314f,   -2.20267f,
-    -9.19373f, -1.37906f,  1.41737f,    -7.67102f, 2.8922f,    -5.09486f,
-    -8.81066f, 0.986411f,  2.30801f,    -8.53294f, 3.26569f,   -3.11246f,
-    -9.03093f, 1.06303f,   1.39821f,    -8.8777f,  -4.47237f,  -0.632069f,
-    -8.74362f, -1.83875f,  -0.0957681f, -7.92002f, 1.0343f,    -3.84988f,
-    -8.92558f, 0.440533f,  1.26414f,    -8.71489f, -0.153229f, -3.64876f,
+	8.5904f,   -1.36948f,  -3.74453f,   8.72447f,  1.1971f,	   4.00311f,
+	8.80109f,  -3.08373f,  2.27928f,    8.95431f,  -1.90578f,  -1.10133f,
+	8.93516f,  -2.03986f,  0.248997f,   9.05008f,  1.53229f,   -0.708684f,
+	-8.78193f, 1.43652f,   -2.63362f,   -8.66701f, 0.220267f,  2.79643f,
+	-8.66701f, -2.06859f,  2.42293f,    -8.79151f, -2.88262f,  -1.16837f,
+	8.74362f,  -1.9824f,   3.53384f,    9.04051f,  0.0574608f, -1.36948f,
+	8.78193f,  -4.1276f,   2.58574f,    8.8777f,   0.201113f,  -1.80044f,
+	8.70532f,  -0.296881f, 1.52271f,    9.02135f,  -0.871489f, -2.43251f,
+	-9.09797f, -1.3216f,   -3.60088f,   -8.97347f, 2.52828f,   2.6432f,
+	-8.82024f, 1.87705f,   0.354342f,   -7.93917f, -4.38618f,  0.258574f,
+	-8.81066f, 1.91536f,   -2.92093f,   -8.04452f, -5.4492f,   3.28484f,
+	-8.86812f, 2.05901f,   0.890643f,   -8.01579f, -5.65989f,  -2.20267f,
+	-9.0022f,  2.18351f,   -2.9305f,    -8.80109f, -4.01268f,  3.055f,
+	-9.37569f, -1.04387f,  0.277727f,   -6.80911f, 2.806f,	   -6.0717f,
+	-8.79151f, -8.79151f,  -2.11647f,   -8.6287f,  -1.53229f,  3.58173f,
+	-8.97347f, -0.335188f, 1.26414f,    8.5042f,   1.51314f,   -2.20267f,
+	-9.19373f, -1.37906f,  1.41737f,    -7.67102f, 2.8922f,	   -5.09486f,
+	-8.81066f, 0.986411f,  2.30801f,    -8.53294f, 3.26569f,   -3.11246f,
+	-9.03093f, 1.06303f,   1.39821f,    -8.8777f,  -4.47237f,  -0.632069f,
+	-8.74362f, -1.83875f,  -0.0957681f, -7.92002f, 1.0343f,	   -3.84988f,
+	-8.92558f, 0.440533f,  1.26414f,    -8.71489f, -0.153229f, -3.64876f,
 };
 
 const size_t kAccelerometerVerticalHingeUnstableTestDataLength =
-    ARRAY_SIZE(kAccelerometerVerticalHingeUnstableTestData);
+	ARRAY_SIZE(kAccelerometerVerticalHingeUnstableTestData);
diff --git a/test/motion_angle_tablet.c b/test/motion_angle_tablet.c
index 8eea053405..2c0c15c828 100644
--- a/test/motion_angle_tablet.c
+++ b/test/motion_angle_tablet.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,25 +19,24 @@
 #include "test_util.h"
 #include "util.h"
 
-
 /*****************************************************************************/
 /* Test utilities */
 
 /* convert array value from g to m.s^2. */
 int filler(const struct motion_sensor_t *s, const float v)
 {
-	return FP_TO_INT( fp_div(
-		FLOAT_TO_FP(v) * MOTION_SCALING_FACTOR,
-		fp_mul(INT_TO_FP(s->current_range), MOTION_ONE_G)));
+	return FP_TO_INT(
+		fp_div(FLOAT_TO_FP(v) * MOTION_SCALING_FACTOR,
+		       fp_mul(INT_TO_FP(s->current_range), MOTION_ONE_G)));
 }
 
 static int test_lid_angle_less180(void)
 {
 	int index = 0, lid_angle;
-	struct motion_sensor_t *lid = &motion_sensors[
-		CONFIG_LID_ANGLE_SENSOR_LID];
-	struct motion_sensor_t *base = &motion_sensors[
-		CONFIG_LID_ANGLE_SENSOR_BASE];
+	struct motion_sensor_t *lid =
+		&motion_sensors[CONFIG_LID_ANGLE_SENSOR_LID];
+	struct motion_sensor_t *base =
+		&motion_sensors[CONFIG_LID_ANGLE_SENSOR_BASE];
 
 	/* We don't have TASK_CHIP so simulate init ourselves */
 	hook_notify(HOOK_CHIPSET_SHUTDOWN);
@@ -61,18 +60,17 @@ static int test_lid_angle_less180(void)
 
 	/* Check we stay in tablet mode, even when hinge is vertical. */
 	while (index < kAccelerometerVerticalHingeTestDataLength) {
-		feed_accel_data(kAccelerometerVerticalHingeTestData,
-				&index, filler);
+		feed_accel_data(kAccelerometerVerticalHingeTestData, &index,
+				filler);
 		wait_for_valid_sample();
 		lid_angle = motion_lid_get_angle();
 		cprints(CC_ACCEL, "%d : LID(%d, %d, %d)/BASE(%d, %d, %d): %d",
-				index / TEST_LID_SAMPLE_SIZE,
-				lid->xyz[X], lid->xyz[Y], lid->xyz[Z],
-				base->xyz[X], base->xyz[Y], base->xyz[Z],
-				lid_angle);
+			index / TEST_LID_SAMPLE_SIZE, lid->xyz[X], lid->xyz[Y],
+			lid->xyz[Z], base->xyz[X], base->xyz[Y], base->xyz[Z],
+			lid_angle);
 		/* We need few sample to debounce and enter laptop mode. */
-		TEST_ASSERT(index < 2 * TEST_LID_SAMPLE_SIZE * \
-				(TABLET_MODE_DEBOUNCE_COUNT + 2) ||
+		TEST_ASSERT(index < 2 * TEST_LID_SAMPLE_SIZE *
+					    (TABLET_MODE_DEBOUNCE_COUNT + 2) ||
 			    tablet_get_mode());
 	}
 	/*
@@ -86,20 +84,18 @@ static int test_lid_angle_less180(void)
 		wait_for_valid_sample();
 		lid_angle = motion_lid_get_angle();
 		cprints(CC_ACCEL, "%d : LID(%d, %d, %d)/BASE(%d, %d, %d): %d",
-				index / TEST_LID_SAMPLE_SIZE,
-				lid->xyz[X], lid->xyz[Y], lid->xyz[Z],
-				base->xyz[X], base->xyz[Y], base->xyz[Z],
-				lid_angle);
+			index / TEST_LID_SAMPLE_SIZE, lid->xyz[X], lid->xyz[Y],
+			lid->xyz[Z], base->xyz[X], base->xyz[Y], base->xyz[Z],
+			lid_angle);
 		/* We need few sample to debounce and enter laptop mode. */
 		TEST_ASSERT(index < TEST_LID_SAMPLE_SIZE *
-				(TABLET_MODE_DEBOUNCE_COUNT + 2) ||
+					    (TABLET_MODE_DEBOUNCE_COUNT + 2) ||
 			    tablet_get_mode());
 	}
 	return EC_SUCCESS;
 }
 
-
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/motion_angle_tablet.tasklist b/test/motion_angle_tablet.tasklist
index 0b774ebb4a..6c99c23eea 100644
--- a/test/motion_angle_tablet.tasklist
+++ b/test/motion_angle_tablet.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/motion_common.c b/test/motion_common.c
index c7c3395fc4..e274b206a9 100644
--- a/test/motion_common.c
+++ b/test/motion_common.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -43,9 +43,8 @@ static int accel_get_resolution(const struct motion_sensor_t *s)
 
 int test_data_rate[2] = { 0 };
 
-static int accel_set_data_rate(const struct motion_sensor_t *s,
-			      const int rate,
-			      const int rnd)
+static int accel_set_data_rate(const struct motion_sensor_t *s, const int rate,
+			       const int rnd)
 {
 	test_data_rate[s - motion_sensors] = rate | (rnd ? ROUND_UP_FLAG : 0);
 	return EC_SUCCESS;
@@ -62,8 +61,8 @@ static int accel_get_rms_noise(const struct motion_sensor_t *s)
 	/* Assume we are using BMI160 */
 	fp_t rate = INT_TO_FP(accel_get_data_rate(s) / 1000);
 	fp_t noise_100hz = INT_TO_FP(BMI160_ACCEL_RMS_NOISE_100HZ);
-	fp_t sqrt_rate_ratio = fp_sqrtf(fp_div(rate,
-					       INT_TO_FP(BMI_ACCEL_100HZ)));
+	fp_t sqrt_rate_ratio =
+		fp_sqrtf(fp_div(rate, INT_TO_FP(BMI_ACCEL_100HZ)));
 	return FP_TO_INT(fp_mul(noise_100hz, sqrt_rate_ratio));
 }
 #endif
@@ -118,7 +117,7 @@ const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
 
 /* Read 6 samples from array to sensor vectors, convert units if necessary. */
 void feed_accel_data(const float *array, int *idx,
-		int (filler)(const struct motion_sensor_t*, const float))
+		     int(filler)(const struct motion_sensor_t *, const float))
 {
 	int i, j;
 
diff --git a/test/motion_common.h b/test/motion_common.h
index 45d856d9ef..71e23cd9da 100644
--- a/test/motion_common.h
+++ b/test/motion_common.h
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -13,7 +13,7 @@
  * The task will read the vectors at that interval
  */
 #define TEST_LID_EC_RATE (1 * MSEC)
-#define TEST_LID_FREQUENCY (1e9 / TEST_LID_EC_RATE)   /* mHz */
+#define TEST_LID_FREQUENCY (1e9 / TEST_LID_EC_RATE) /* mHz */
 
 /*
  * Time in ms to wait for the task to read the vectors.
@@ -30,7 +30,8 @@ extern const unsigned int motion_sensor_count;
 
 void wait_for_valid_sample(void);
 void feed_accel_data(const float *array, int *idx,
-		int (filler)(const struct motion_sensor_t *s, const float f));
+		     int(filler)(const struct motion_sensor_t *s,
+				 const float f));
 
 /*
  * External data - from
@@ -65,4 +66,4 @@ extern const float kAccelerometerVerticalHingeTestData[];
 extern const size_t kAccelerometerVerticalHingeTestDataLength;
 extern const float kAccelerometerVerticalHingeUnstableTestData[];
 extern const size_t kAccelerometerVerticalHingeUnstableTestDataLength;
-#endif  /* __CROS_EC_MOTION_COMMON_H */
+#endif /* __CROS_EC_MOTION_COMMON_H */
diff --git a/test/motion_lid.c b/test/motion_lid.c
index 9935767a68..39b83ce6fc 100644
--- a/test/motion_lid.c
+++ b/test/motion_lid.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -48,8 +48,7 @@ static int accel_read(const struct motion_sensor_t *s, intv3_t v)
 	return EC_SUCCESS;
 }
 
-static int accel_set_range(struct motion_sensor_t *s,
-			   const int range,
+static int accel_set_range(struct motion_sensor_t *s, const int range,
 			   const int rnd)
 {
 	s->current_range = range;
@@ -63,9 +62,8 @@ static int accel_get_resolution(const struct motion_sensor_t *s)
 
 int test_data_rate[2] = { 0 };
 
-static int accel_set_data_rate(const struct motion_sensor_t *s,
-			      const int rate,
-			      const int rnd)
+static int accel_set_data_rate(const struct motion_sensor_t *s, const int rate,
+			       const int rnd)
 {
 	test_data_rate[s - motion_sensors] = rate;
 	return EC_SUCCESS;
@@ -148,11 +146,10 @@ static void wait_for_valid_sample(void)
 
 static int test_lid_angle(void)
 {
-
-	struct motion_sensor_t *base = &motion_sensors[
-		CONFIG_LID_ANGLE_SENSOR_BASE];
-	struct motion_sensor_t *lid = &motion_sensors[
-		CONFIG_LID_ANGLE_SENSOR_LID];
+	struct motion_sensor_t *base =
+		&motion_sensors[CONFIG_LID_ANGLE_SENSOR_BASE];
+	struct motion_sensor_t *lid =
+		&motion_sensors[CONFIG_LID_ANGLE_SENSOR_LID];
 	int lid_angle;
 
 	/* We don't have TASK_CHIP so simulate init ourselves */
@@ -189,10 +186,9 @@ static int test_lid_angle(void)
 
 	wait_for_valid_sample();
 	lid_angle = motion_lid_get_angle();
-	cprints(CC_ACCEL, "LID(%d, %d, %d)/BASE(%d, %d, %d): %d",
-			lid->xyz[X], lid->xyz[Y], lid->xyz[Z],
-			base->xyz[X], base->xyz[Y], base->xyz[Z],
-			lid_angle);
+	cprints(CC_ACCEL, "LID(%d, %d, %d)/BASE(%d, %d, %d): %d", lid->xyz[X],
+		lid->xyz[Y], lid->xyz[Z], base->xyz[X], base->xyz[Y],
+		base->xyz[Z], lid_angle);
 	TEST_ASSERT(lid_angle == 0);
 
 	/* Set lid open to 90 degrees. */
@@ -319,8 +315,7 @@ static int test_lid_angle(void)
 	return EC_SUCCESS;
 }
 
-
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/motion_lid.tasklist b/test/motion_lid.tasklist
index 0b774ebb4a..6c99c23eea 100644
--- a/test/motion_lid.tasklist
+++ b/test/motion_lid.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/motion_sense_fifo.c b/test/motion_sense_fifo.c
index afa9a4f5cf..c93e67951b 100644
--- a/test/motion_sense_fifo.c
+++ b/test/motion_sense_fifo.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -153,7 +153,11 @@ static int test_stage_data_removed_oversample(void)
 
 static int test_stage_data_remove_all_oversampling(void)
 {
-	struct ec_response_motion_sense_fifo_info fifo_info;
+	uint8_t fifo_info_buffer
+		[sizeof(struct ec_response_motion_sense_fifo_info) +
+		 sizeof(uint16_t) * MAX_MOTION_SENSORS];
+	struct ec_response_motion_sense_fifo_info *fifo_info =
+		(void *)fifo_info_buffer;
 	int read_count;
 
 	motion_sensors->oversampling_ratio = 0;
@@ -172,9 +176,9 @@ static int test_stage_data_remove_all_oversampling(void)
 	 * Check that count is 0 and total_lost is 0, oversampling should be
 	 * removing the data before it touches the FIFO.
 	 */
-	motion_sense_fifo_get_info(&fifo_info, /*reset=*/false);
-	TEST_EQ(fifo_info.count, 0, "%d");
-	TEST_EQ(fifo_info.total_lost, 0, "%d");
+	motion_sense_fifo_get_info(fifo_info, /*reset=*/false);
+	TEST_EQ(fifo_info->count, 0, "%d");
+	TEST_EQ(fifo_info->total_lost, 0, "%d");
 
 	motion_sense_fifo_commit_data();
 
@@ -191,7 +195,11 @@ static int test_stage_data_remove_all_oversampling(void)
 
 static int test_stage_data_evicts_data_with_timestamp(void)
 {
-	struct ec_response_motion_sense_fifo_info fifo_info;
+	uint8_t fifo_info_buffer
+		[sizeof(struct ec_response_motion_sense_fifo_info) +
+		 sizeof(uint16_t) * MAX_MOTION_SENSORS];
+	struct ec_response_motion_sense_fifo_info *fifo_info =
+		(void *)fifo_info_buffer;
 	int i, read_count;
 
 	/* Fill the fifo */
@@ -206,9 +214,9 @@ static int test_stage_data_evicts_data_with_timestamp(void)
 	 * Check that count is 1 smaller than the total size and total_lost is 2
 	 * because 2 entries were evicted together.
 	 */
-	motion_sense_fifo_get_info(&fifo_info, /*reset=*/false);
-	TEST_EQ(fifo_info.count, CONFIG_ACCEL_FIFO_SIZE - 1, "%d");
-	TEST_EQ(fifo_info.total_lost, 2, "%d");
+	motion_sense_fifo_get_info(fifo_info, /*reset=*/false);
+	TEST_EQ(fifo_info->count, CONFIG_ACCEL_FIFO_SIZE - 1, "%d");
+	TEST_EQ(fifo_info->total_lost, 2, "%d");
 
 	read_count = motion_sense_fifo_read(
 		sizeof(data), CONFIG_ACCEL_FIFO_SIZE, data, &data_bytes_read);
@@ -273,7 +281,7 @@ static int test_spread_data_in_window(void)
 	int read_count;
 
 	motion_sensors[0].oversampling_ratio = 1;
-	motion_sensors[0].collection_rate = 20; /* us */
+	motion_sense_set_data_period(0, 20 /* us */);
 	now = __hw_clock_source_read();
 
 	motion_sense_fifo_stage_data(data, motion_sensors, 3, now - 18);
@@ -300,9 +308,9 @@ static int test_spread_data_on_overflow(void)
 	int i, read_count;
 
 	/* Set up the sensors */
-	motion_sensors[0].collection_rate = 20; /* us */
 	motion_sensors[0].oversampling_ratio = 1;
 	motion_sensors[1].oversampling_ratio = 1;
+	motion_sense_set_data_period(0, 20 /* us */);
 
 	/* Add 1 sample for sensor [1]. This will be evicted. */
 	data->sensor_num = 1;
@@ -351,7 +359,7 @@ static int test_spread_data_by_collection_rate(void)
 	int read_count;
 
 	motion_sensors[0].oversampling_ratio = 1;
-	motion_sensors[0].collection_rate = 20; /* us */
+	motion_sense_set_data_period(0, 20 /* us */);
 	motion_sense_fifo_stage_data(data, motion_sensors, 3, now - 25);
 	motion_sense_fifo_stage_data(data, motion_sensors, 3, now - 25);
 	motion_sense_fifo_commit_data();
@@ -366,42 +374,13 @@ static int test_spread_data_by_collection_rate(void)
 	return EC_SUCCESS;
 }
 
-static int test_spread_double_commit_same_timestamp(void)
-{
-	const uint32_t now = __hw_clock_source_read();
-	int read_count;
-
-	/*
-	 * Stage and commit the same sample. This is not expected to happen
-	 * since batches of sensor samples should be staged together and only
-	 * commit once. We assume that the driver did this on purpose and will
-	 * allow the same timestamp to be sent.
-	 */
-	motion_sensors[0].oversampling_ratio = 1;
-	motion_sensors[0].collection_rate = 20; /* us */
-	motion_sense_fifo_stage_data(data, motion_sensors, 3, now - 25);
-	motion_sense_fifo_commit_data();
-	motion_sense_fifo_stage_data(data, motion_sensors, 3, now - 25);
-	motion_sense_fifo_commit_data();
-
-	read_count = motion_sense_fifo_read(
-		sizeof(data), CONFIG_ACCEL_FIFO_SIZE, data, &data_bytes_read);
-	TEST_EQ(read_count, 4, "%d");
-	TEST_BITS_SET(data[0].flags, MOTIONSENSE_SENSOR_FLAG_TIMESTAMP);
-	TEST_EQ(data[0].timestamp, now - 25, "%u");
-	TEST_BITS_SET(data[2].flags, MOTIONSENSE_SENSOR_FLAG_TIMESTAMP);
-	TEST_EQ(data[2].timestamp, now - 25, "%u");
-
-	return EC_SUCCESS;
-}
-
 static int test_commit_non_data_or_timestamp_entries(void)
 {
 	const uint32_t now = __hw_clock_source_read();
 	int read_count;
 
 	motion_sensors[0].oversampling_ratio = 1;
-	motion_sensors[0].collection_rate = 20; /* us */
+	motion_sense_set_data_period(0, 20 /* us */);
 
 	/* Insert non-data entry */
 	data[0].flags = MOTIONSENSE_SENSOR_FLAG_ODR;
@@ -426,28 +405,29 @@ static int test_commit_non_data_or_timestamp_entries(void)
 
 static int test_get_info_size(void)
 {
-	struct ec_response_motion_sense_fifo_info fifo_info;
+	uint8_t fifo_info_buffer
+		[sizeof(struct ec_response_motion_sense_fifo_info) +
+		 sizeof(uint16_t) * MAX_MOTION_SENSORS];
+	struct ec_response_motion_sense_fifo_info *fifo_info =
+		(void *)fifo_info_buffer;
 
-	motion_sense_fifo_get_info(&fifo_info, /*reset=*/false);
-	TEST_EQ(fifo_info.size, CONFIG_ACCEL_FIFO_SIZE, "%d");
+	motion_sense_fifo_get_info(fifo_info, /*reset=*/false);
+	TEST_EQ(fifo_info->size, CONFIG_ACCEL_FIFO_SIZE, "%d");
 
 	return EC_SUCCESS;
 }
 
 void before_test(void)
 {
-	static struct ec_response_motion_sense_fifo_info fifo_info;
-
 	motion_sense_fifo_commit_data();
 	motion_sense_fifo_read(sizeof(data), CONFIG_ACCEL_FIFO_SIZE, &data,
 			       &data_bytes_read);
 	motion_sense_fifo_reset_needed_flags();
 	memset(data, 0, sizeof(data));
 	motion_sense_fifo_reset();
-	motion_sense_fifo_get_info(&fifo_info, /*reset=*/true);
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 	motion_sense_fifo_init();
@@ -465,7 +445,6 @@ void run_test(int argc, char **argv)
 	RUN_TEST(test_spread_data_in_window);
 	RUN_TEST(test_spread_data_on_overflow);
 	RUN_TEST(test_spread_data_by_collection_rate);
-	RUN_TEST(test_spread_double_commit_same_timestamp);
 	RUN_TEST(test_commit_non_data_or_timestamp_entries);
 	RUN_TEST(test_get_info_size);
 
diff --git a/test/motion_sense_fifo.tasklist b/test/motion_sense_fifo.tasklist
index 9fc1a80f4d..844ddb6c10 100644
--- a/test/motion_sense_fifo.tasklist
+++ b/test/motion_sense_fifo.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/mpu.c b/test/mpu.c
index 25b2c58903..2193c0c617 100644
--- a/test/mpu.c
+++ b/test/mpu.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,22 +17,18 @@ struct mpu_info {
 };
 
 #if defined(CHIP_VARIANT_STM32F412)
-struct mpu_info mpu_info = {
-	.has_mpu = true,
-	.num_mpu_regions = 8,
-	.mpu_is_unified = true
-};
+struct mpu_info mpu_info = { .has_mpu = true,
+			     .num_mpu_regions = 8,
+			     .mpu_is_unified = true };
 
 struct mpu_rw_regions expected_rw_regions = { .num_regions = 2,
 					      .addr = { 0x08060000,
 							0x08080000 },
 					      .size = { 0x20000, 0x80000 } };
 #elif defined(CHIP_VARIANT_STM32H7X3)
-struct mpu_info mpu_info = {
-	.has_mpu = true,
-	.num_mpu_regions = 16,
-	.mpu_is_unified = true
-};
+struct mpu_info mpu_info = { .has_mpu = true,
+			     .num_mpu_regions = 16,
+			     .mpu_is_unified = true };
 
 struct mpu_rw_regions expected_rw_regions = { .num_regions = 1,
 					      .addr = { 0x08100000,
@@ -75,7 +71,7 @@ test_static int test_mpu_update_region_valid_region(void)
 {
 	volatile char data __maybe_unused;
 
-	char * const ram_base = (char * const)CONFIG_RAM_BASE;
+	char *const ram_base = (char *const)CONFIG_RAM_BASE;
 	const uint8_t size_bit = 5;
 	uint16_t mpu_attr = MPU_ATTR_NO_NO;
 
@@ -176,7 +172,7 @@ test_static int test_mpu_get_rw_regions(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	enum ec_image cur_image = system_get_image_copy();
 
diff --git a/test/mpu.tasklist b/test/mpu.tasklist
index 51734f058d..a1f1a94e2d 100644
--- a/test/mpu.tasklist
+++ b/test/mpu.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/mutex.c b/test/mutex.c
index 4fbf7d5cae..a03e504a0a 100644
--- a/test/mutex.c
+++ b/test/mutex.c
@@ -1,7 +1,7 @@
-/* Copyright 2011 The Chromium OS Authors. All rights reserved.
+/* Copyright 2011 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
- * Copyright 2011 Google Inc.
+ * Copyright 2011 Google LLC
  *
  * Tasks for mutexes basic tests.
  */
@@ -22,7 +22,7 @@ static struct mutex mtx;
 
 int mutex_random_task(void *unused)
 {
-	char letter = 'A'+(TASK_ID_MTX3A - task_get_current());
+	char letter = 'A' + (TASK_ID_MTX3A - task_get_current());
 	/* wait to be activated */
 
 	while (1) {
@@ -110,7 +110,7 @@ int mutex_main_task(void *unused)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	wait_for_task_started();
 	task_wake(TASK_ID_MTX1);
diff --git a/test/mutex.tasklist b/test/mutex.tasklist
index 8e3d08ddc2..46cdad7fa1 100644
--- a/test/mutex.tasklist
+++ b/test/mutex.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/newton_fit.c b/test/newton_fit.c
index 9648fbfd9a..07c35aad2a 100644
--- a/test/newton_fit.c
+++ b/test/newton_fit.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -126,7 +126,7 @@ static int test_newton_fit_calculate(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/newton_fit.tasklist b/test/newton_fit.tasklist
index 5ffe662d01..2d4595f76a 100644
--- a/test/newton_fit.tasklist
+++ b/test/newton_fit.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/nvidia_gpu.c b/test/nvidia_gpu.c
new file mode 100644
index 0000000000..d6086cc8c4
--- /dev/null
+++ b/test/nvidia_gpu.c
@@ -0,0 +1,215 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Tests for Nvidia GPU.
+ */
+#include <stdio.h>
+
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "common.h"
+#include "console.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "task.h"
+#include "test_util.h"
+#include "throttle_ap.h"
+#include "timer.h"
+#include "util.h"
+
+#include "driver/nvidia_gpu.h"
+
+struct d_notify_policy d_notify_policies[] = {
+	AC_ATLEAST_W(100),  AC_ATLEAST_W(65),  AC_DC,
+	DC_ATLEAST_SOC(20), DC_ATLEAST_SOC(5),
+};
+
+extern enum d_notify_level d_notify_level;
+extern bool policy_initialized;
+extern const struct d_notify_policy *d_notify_policy;
+static int extpower_presence = 1;
+static int nvidia_gpu_acoff_odl = 1;
+static int charge_percent = 100;
+static int charge_power = 100;
+static uint8_t *memmap_gpu;
+
+__override int charge_get_percent(void)
+{
+	return charge_percent;
+}
+
+__override int charge_manager_get_power_limit_uw(void)
+{
+	return charge_power * 1000000;
+}
+
+__override int extpower_is_present(void)
+{
+	return extpower_presence;
+}
+
+__override int gpio_get_level(enum gpio_signal signal)
+{
+	if (signal == GPIO_NVIDIA_GPU_ACOFF_ODL)
+		return nvidia_gpu_acoff_odl;
+	return 0;
+}
+
+__override void gpio_set_level(enum gpio_signal signal, int value)
+{
+	if (signal == GPIO_NVIDIA_GPU_ACOFF_ODL)
+		nvidia_gpu_acoff_odl = value;
+}
+
+static void setup(int extpower, int gpio_acoff, int percent, int power,
+		  enum d_notify_level level)
+{
+	extpower_presence = extpower;
+	nvidia_gpu_acoff_odl = gpio_acoff;
+	charge_percent = percent;
+	charge_power = power;
+	d_notify_level = level;
+	*memmap_gpu = level;
+}
+
+static void plug_ac(int plug)
+{
+	extpower_presence = plug;
+	hook_notify(HOOK_AC_CHANGE);
+}
+
+static int check_d_notify_level(enum d_notify_level expected_level)
+{
+	TEST_EQ(d_notify_level, expected_level, "%d");
+	TEST_EQ(*memmap_gpu, expected_level, "%d");
+
+	return EC_SUCCESS;
+}
+
+static int test_startup(void)
+{
+	/* Test initial values after HOOK_INIT. Don't call setup(). */
+
+	TEST_ASSERT(IS_ENABLED(HAS_GPU_DRIVER));
+	TEST_ASSERT(policy_initialized);
+	TEST_NE(d_notify_policy, NULL, "%p");
+	TEST_EQ(check_d_notify_level(D_NOTIFY_1), EC_SUCCESS, "%d");
+
+	return EC_SUCCESS;
+}
+
+static int test_ac_unplug(void)
+{
+	setup(1, 1, 100, 100, D_NOTIFY_1);
+
+	/* Unplug AC. D1 -> D5 */
+	plug_ac(0);
+	throttle_gpu(THROTTLE_ON, THROTTLE_HARD, THROTTLE_SRC_AC);
+	TEST_EQ(nvidia_gpu_acoff_odl, 0, "%d");
+	TEST_EQ(check_d_notify_level(D_NOTIFY_5), EC_SUCCESS, "%d");
+	TEST_ASSERT(host_is_event_set(EC_HOST_EVENT_GPU));
+	host_clear_events(EC_HOST_EVENT_MASK(EC_HOST_EVENT_GPU));
+
+	/* Wait half of NVIDIA_GPU_ACOFF_DURATION. D5 -> D5. */
+	usleep(NVIDIA_GPU_ACOFF_DURATION / 2);
+	TEST_EQ(nvidia_gpu_acoff_odl, 0, "%d");
+	TEST_EQ(check_d_notify_level(D_NOTIFY_5), EC_SUCCESS, "%d");
+	TEST_ASSERT(!host_is_event_set(EC_HOST_EVENT_GPU));
+
+	/* Wait another half of NVIDIA_GPU_ACOFF_DURATION. D5 -> D3. */
+	usleep(NVIDIA_GPU_ACOFF_DURATION / 2);
+	TEST_EQ(nvidia_gpu_acoff_odl, 1, "%d");
+	TEST_EQ(check_d_notify_level(D_NOTIFY_3), EC_SUCCESS, "%d");
+	TEST_ASSERT(host_is_event_set(EC_HOST_EVENT_GPU));
+	host_clear_events(EC_HOST_EVENT_MASK(EC_HOST_EVENT_GPU));
+
+	/* Discharge to 60%. D3 -> D3. */
+	charge_percent = 60;
+	hook_notify(HOOK_BATTERY_SOC_CHANGE);
+	TEST_EQ(nvidia_gpu_acoff_odl, 1, "%d");
+	TEST_EQ(check_d_notify_level(D_NOTIFY_3), EC_SUCCESS, "%d");
+	TEST_ASSERT(!host_is_event_set(EC_HOST_EVENT_GPU));
+
+	/* Discharge to 20%. D3 -> D4 */
+	charge_percent = 20;
+	hook_notify(HOOK_BATTERY_SOC_CHANGE);
+	TEST_EQ(nvidia_gpu_acoff_odl, 1, "%d");
+	TEST_EQ(check_d_notify_level(D_NOTIFY_4), EC_SUCCESS, "%d");
+	TEST_ASSERT(host_is_event_set(EC_HOST_EVENT_GPU));
+	host_clear_events(EC_HOST_EVENT_MASK(EC_HOST_EVENT_GPU));
+
+	/* Discharge to 5%. D4 -> D5 */
+	charge_percent = 5;
+	hook_notify(HOOK_BATTERY_SOC_CHANGE);
+	TEST_EQ(nvidia_gpu_acoff_odl, 1, "%d");
+	TEST_EQ(check_d_notify_level(D_NOTIFY_5), EC_SUCCESS, "%d");
+	TEST_ASSERT(host_is_event_set(EC_HOST_EVENT_GPU));
+	host_clear_events(EC_HOST_EVENT_MASK(EC_HOST_EVENT_GPU));
+
+	return EC_SUCCESS;
+}
+
+static int test_ac_plug(void)
+{
+	/* Plug 100W AC. D5 -> D1. */
+	setup(0, 1, 5, 100, D_NOTIFY_5);
+	plug_ac(1);
+	throttle_gpu(THROTTLE_OFF, THROTTLE_HARD, THROTTLE_SRC_AC);
+	TEST_EQ(nvidia_gpu_acoff_odl, 1, "%d");
+	TEST_EQ(check_d_notify_level(D_NOTIFY_1), EC_SUCCESS, "%d");
+	TEST_ASSERT(host_is_event_set(EC_HOST_EVENT_GPU));
+	host_clear_events(EC_HOST_EVENT_MASK(EC_HOST_EVENT_GPU));
+
+	/* Plug 65W AC. D5 -> D2. */
+	setup(0, 1, 5, 65, D_NOTIFY_5);
+	plug_ac(1);
+	throttle_gpu(THROTTLE_OFF, THROTTLE_HARD, THROTTLE_SRC_AC);
+	TEST_EQ(nvidia_gpu_acoff_odl, 1, "%d");
+	TEST_EQ(check_d_notify_level(D_NOTIFY_2), EC_SUCCESS, "%d");
+	TEST_ASSERT(host_is_event_set(EC_HOST_EVENT_GPU));
+	host_clear_events(EC_HOST_EVENT_MASK(EC_HOST_EVENT_GPU));
+
+	/* Plug 35W AC. D5 -> D3. */
+	setup(0, 1, 5, 35, D_NOTIFY_5);
+	plug_ac(1);
+	throttle_gpu(THROTTLE_OFF, THROTTLE_HARD, THROTTLE_SRC_AC);
+	TEST_EQ(nvidia_gpu_acoff_odl, 1, "%d");
+	TEST_EQ(check_d_notify_level(D_NOTIFY_3), EC_SUCCESS, "%d");
+	TEST_ASSERT(host_is_event_set(EC_HOST_EVENT_GPU));
+	host_clear_events(EC_HOST_EVENT_MASK(EC_HOST_EVENT_GPU));
+
+	return EC_SUCCESS;
+}
+
+static int test_overt(void)
+{
+	nvidia_gpu_over_temp(1);
+	TEST_ASSERT(*memmap_gpu & EC_MEMMAP_GPU_OVERT_BIT);
+	TEST_ASSERT(host_is_event_set(EC_HOST_EVENT_GPU));
+
+	nvidia_gpu_over_temp(0);
+	TEST_ASSERT(!(*memmap_gpu & EC_MEMMAP_GPU_OVERT_BIT));
+	TEST_ASSERT(host_is_event_set(EC_HOST_EVENT_GPU));
+
+	return EC_SUCCESS;
+}
+
+static void board_gpu_init(void)
+{
+	nvidia_gpu_init_policy(d_notify_policies);
+}
+DECLARE_HOOK(HOOK_INIT, board_gpu_init, HOOK_PRIO_DEFAULT);
+
+void run_test(int argc, const char **argv)
+{
+	memmap_gpu = (uint8_t *)host_get_memmap(EC_MEMMAP_GPU);
+
+	test_chipset_on();
+
+	RUN_TEST(test_startup);
+	RUN_TEST(test_ac_unplug);
+	RUN_TEST(test_ac_plug);
+	RUN_TEST(test_overt);
+	test_print_result();
+}
diff --git a/test/nvidia_gpu.tasklist b/test/nvidia_gpu.tasklist
new file mode 100644
index 0000000000..8918b4ee2f
--- /dev/null
+++ b/test/nvidia_gpu.tasklist
@@ -0,0 +1,10 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST \
+	TASK_TEST(CHIPSET, chipset_task, NULL, TASK_STACK_SIZE)
diff --git a/test/online_calibration.c b/test/online_calibration.c
index 1b3abf51bc..cecb543eef 100644
--- a/test/online_calibration.c
+++ b/test/online_calibration.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -48,17 +48,14 @@ static struct accelgyro_drv mock_sensor_driver = {
 	.read_temp = mock_read_temp,
 };
 
-static struct accel_cal_algo base_accel_cal_algos[] = {
-	{
-		.newton_fit = NEWTON_FIT(4, 15, FLOAT_TO_FP(0.01f),
-					 FLOAT_TO_FP(0.25f),
-					 FLOAT_TO_FP(1.0e-8f), 100),
-	}
-};
+static struct accel_cal_algo base_accel_cal_algos[] = { {
+	.newton_fit = NEWTON_FIT(4, 15, FLOAT_TO_FP(0.01f), FLOAT_TO_FP(0.25f),
+				 FLOAT_TO_FP(1.0e-8f), 100),
+} };
 
 static struct accel_cal base_accel_cal_data = {
-	.still_det = STILL_DET(FLOAT_TO_FP(0.00025f), 800 * MSEC, 1200 * MSEC,
-			       5),
+	.still_det =
+		STILL_DET(FLOAT_TO_FP(0.00025f), 800 * MSEC, 1200 * MSEC, 5),
 	.algos = base_accel_cal_algos,
 	.num_temp_windows = ARRAY_SIZE(base_accel_cal_algos),
 };
@@ -68,9 +65,8 @@ static struct mag_cal_t lid_mag_cal_data;
 static bool next_accel_cal_accumulate_result;
 static fpv3_t next_accel_cal_bias;
 
-bool accel_cal_accumulate(
-	struct accel_cal *cal, uint32_t sample_time, fp_t x, fp_t y, fp_t z,
-	fp_t temp)
+bool accel_cal_accumulate(struct accel_cal *cal, uint32_t sample_time, fp_t x,
+			  fp_t y, fp_t z, fp_t temp)
 {
 	if (next_accel_cal_accumulate_result) {
 		cal->bias[X] = next_accel_cal_bias[X];
@@ -110,8 +106,8 @@ static int test_read_temp_on_stage(void)
 
 	mock_read_temp_results = &expected;
 	data.sensor_num = BASE;
-	rc = online_calibration_process_data(
-		&data, &motion_sensors[0], __hw_clock_source_read());
+	rc = online_calibration_process_data(&data, &motion_sensors[0],
+					     __hw_clock_source_read());
 
 	TEST_EQ(rc, EC_SUCCESS, "%d");
 	TEST_EQ(expected.used_count, 1, "%d");
@@ -128,12 +124,12 @@ static int test_read_temp_from_cache_on_stage(void)
 
 	mock_read_temp_results = &expected;
 	data.sensor_num = BASE;
-	rc = online_calibration_process_data(
-		&data, &motion_sensors[0], __hw_clock_source_read());
+	rc = online_calibration_process_data(&data, &motion_sensors[0],
+					     __hw_clock_source_read());
 	TEST_EQ(rc, EC_SUCCESS, "%d");
 
-	rc = online_calibration_process_data(
-		&data, &motion_sensors[0], __hw_clock_source_read());
+	rc = online_calibration_process_data(&data, &motion_sensors[0],
+					     __hw_clock_source_read());
 	TEST_EQ(rc, EC_SUCCESS, "%d");
 
 	TEST_EQ(expected.used_count, 1, "%d");
@@ -150,13 +146,13 @@ static int test_read_temp_twice_after_cache_stale(void)
 
 	mock_read_temp_results = &expected;
 	data.sensor_num = BASE;
-	rc = online_calibration_process_data(
-		&data, &motion_sensors[0], __hw_clock_source_read());
+	rc = online_calibration_process_data(&data, &motion_sensors[0],
+					     __hw_clock_source_read());
 	TEST_EQ(rc, EC_SUCCESS, "%d");
 
 	sleep(2);
-	rc = online_calibration_process_data(
-		&data, &motion_sensors[0], __hw_clock_source_read());
+	rc = online_calibration_process_data(&data, &motion_sensors[0],
+					     __hw_clock_source_read());
 	TEST_EQ(rc, EC_SUCCESS, "%d");
 
 	TEST_EQ(expected.used_count, 2, "%d");
@@ -176,17 +172,17 @@ static int test_new_calibration_value(void)
 	next_accel_cal_accumulate_result = false;
 	data.sensor_num = BASE;
 
-	rc = online_calibration_process_data(
-		&data, &motion_sensors[BASE], __hw_clock_source_read());
+	rc = online_calibration_process_data(&data, &motion_sensors[BASE],
+					     __hw_clock_source_read());
 	TEST_EQ(rc, EC_SUCCESS, "%d");
 	TEST_EQ(online_calibration_has_new_values(), false, "%d");
 
 	next_accel_cal_accumulate_result = true;
-	next_accel_cal_bias[X] = 0.01f;		/* expect:  81  */
-	next_accel_cal_bias[Y] = -0.02f;	/* expect: -163 */
-	next_accel_cal_bias[Z] = 0;		/* expect:    0 */
-	rc = online_calibration_process_data(
-		&data, &motion_sensors[BASE], __hw_clock_source_read());
+	next_accel_cal_bias[X] = 0.01f; /* expect:  81  */
+	next_accel_cal_bias[Y] = -0.02f; /* expect: -163 */
+	next_accel_cal_bias[Z] = 0; /* expect:    0 */
+	rc = online_calibration_process_data(&data, &motion_sensors[BASE],
+					     __hw_clock_source_read());
 	TEST_EQ(rc, EC_SUCCESS, "%d");
 	TEST_EQ(online_calibration_has_new_values(), true, "%d");
 
@@ -216,8 +212,8 @@ int test_mag_reading_updated_cal(void)
 	init_mag_cal(&expected_results);
 	mag_cal_update(&expected_results, test_values);
 
-	rc = online_calibration_process_data(
-		&data, &motion_sensors[LID], __hw_clock_source_read());
+	rc = online_calibration_process_data(&data, &motion_sensors[LID],
+					     __hw_clock_source_read());
 	TEST_EQ(rc, EC_SUCCESS, "%d");
 	TEST_EQ(expected_results.kasa_fit.nsamples,
 		lid_mag_cal_data.kasa_fit.nsamples, "%d");
@@ -231,7 +227,7 @@ void before_test(void)
 	online_calibration_init();
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/online_calibration.tasklist b/test/online_calibration.tasklist
index 5b67239ff8..a9ba96907d 100644
--- a/test/online_calibration.tasklist
+++ b/test/online_calibration.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/online_calibration_spoof.c b/test/online_calibration_spoof.c
index 66ef5d01de..44a3b812d9 100644
--- a/test/online_calibration_spoof.c
+++ b/test/online_calibration_spoof.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -184,7 +184,7 @@ void before_test(void)
 	gyro_cal_initialization_for_test(&gyro_cal_data);
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/online_calibration_spoof.tasklist b/test/online_calibration_spoof.tasklist
index 7d28eb5b64..7209a7441e 100644
--- a/test/online_calibration_spoof.tasklist
+++ b/test/online_calibration_spoof.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/panic_data.c b/test/panic_data.c
index 9abbcb7745..334b766dfc 100644
--- a/test/panic_data.c
+++ b/test/panic_data.c
@@ -1,11 +1,11 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "test_util.h"
 
-#include "assert.h"
+#include "builtin/assert.h"
 #include "panic.h"
 #include "system.h"
 #include "task.h"
@@ -132,7 +132,7 @@ int task_test(void *unused)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 	msleep(30); /* Wait for TASK_ID_TEST to initialize */
diff --git a/test/panic_data.tasklist b/test/panic_data.tasklist
index 6a2f1834ca..273a9664c0 100644
--- a/test/panic_data.tasklist
+++ b/test/panic_data.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/pingpong.c b/test/pingpong.c
index 9d3a7ed7af..cb8c5af8c9 100644
--- a/test/pingpong.c
+++ b/test/pingpong.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -60,7 +60,7 @@ int task_tick(void *data)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	wait_for_task_started();
 	task_wake(TASK_ID_TICK);
diff --git a/test/pingpong.tasklist b/test/pingpong.tasklist
index 760d204b67..7db2ce33a6 100644
--- a/test/pingpong.tasklist
+++ b/test/pingpong.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/power_button.c b/test/power_button.c
index 5fe9136105..dc64e607fa 100644
--- a/test/power_button.c
+++ b/test/power_button.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -89,7 +89,7 @@ static int test_debounce(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/power_button.tasklist b/test/power_button.tasklist
index da0ab6211a..100cb6b5bd 100644
--- a/test/power_button.tasklist
+++ b/test/power_button.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/powerdemo.c b/test/powerdemo.c
index e695bb8e5e..7a4f0c5ccb 100644
--- a/test/powerdemo.c
+++ b/test/powerdemo.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,17 +13,16 @@
 #include "registers.h"
 
 static volatile enum {
-	POWER_STATE_IDLE = 0,    /* Idle */
-	POWER_STATE_DOWN1,       /* Assert output for 1ms */
-	POWER_STATE_UP1,         /* Deassert output for 1ms */
-	POWER_STATE_DOWN10,      /* Assert output for 10ms */
-	POWER_STATE_UP5,         /* Deassert output for 5ms */
-	POWER_STATE_DOWN15,      /* Assert output for 15ms */
-	POWER_STATE_WAIT,        /* Wait for button to be released */
-	POWER_STATE_DOWN2        /* Assert output for 2ms */
+	POWER_STATE_IDLE = 0, /* Idle */
+	POWER_STATE_DOWN1, /* Assert output for 1ms */
+	POWER_STATE_UP1, /* Deassert output for 1ms */
+	POWER_STATE_DOWN10, /* Assert output for 10ms */
+	POWER_STATE_UP5, /* Deassert output for 5ms */
+	POWER_STATE_DOWN15, /* Assert output for 15ms */
+	POWER_STATE_WAIT, /* Wait for button to be released */
+	POWER_STATE_DOWN2 /* Assert output for 2ms */
 } state = POWER_STATE_IDLE;
 
-
 /* Stops the timer. */
 static void __stop_timer(void)
 {
@@ -33,7 +32,6 @@ static void __stop_timer(void)
 	LM4_TIMER_ICR(7) = LM4_TIMER_RIS(7);
 }
 
-
 /* Starts the timer with the specified delay.  If the timer is already
  * started, resets it. */
 static void __start_timer(int usec)
@@ -46,7 +44,6 @@ static void __start_timer(int usec)
 	LM4_TIMER_CTL(7) |= 0x01;
 }
 
-
 static void __set_state(int new_state, int pin_value, int timeout)
 {
 	LM4_GPIO_DATA(LM4_GPIO_D, 0x08) = (pin_value ? 0x08 : 0);
@@ -57,7 +54,6 @@ static void __set_state(int new_state, int pin_value, int timeout)
 	state = new_state;
 }
 
-
 int power_demo_init(void)
 {
 	volatile uint32_t scratch __attribute__((unused));
@@ -102,7 +98,6 @@ int power_demo_init(void)
 	return EC_SUCCESS;
 }
 
-
 /* GPIO interrupt handler */
 static void __gpio_d_interrupt(void)
 {
@@ -125,7 +120,6 @@ static void __gpio_d_interrupt(void)
 
 DECLARE_IRQ(LM4_IRQ_GPIOD, __gpio_d_interrupt, 1);
 
-
 /* Timer interrupt handler */
 static void __timer_w1_interrupt(void)
 {
diff --git a/test/powerdemo.h b/test/powerdemo.h
index 17ed482042..a8ee854acb 100644
--- a/test/powerdemo.h
+++ b/test/powerdemo.h
@@ -1,4 +1,4 @@
-/* Copyright 2011 The Chromium OS Authors. All rights reserved.
+/* Copyright 2011 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,4 +13,4 @@
 /* Initializes the module. */
 int power_demo_init(void);
 
-#endif  /* __TEST_POWERDEMO_H */
+#endif /* __TEST_POWERDEMO_H */
diff --git a/test/powerdemo.tasklist b/test/powerdemo.tasklist
index a4fff562e3..3824306072 100644
--- a/test/powerdemo.tasklist
+++ b/test/powerdemo.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/printf.c b/test/printf.c
index f7e9b9dd2d..728aa9b4a8 100644
--- a/test/printf.c
+++ b/test/printf.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,14 +12,31 @@
 #include "test_util.h"
 #include "util.h"
 
+#ifdef USE_BUILTIN_STDLIB
+/*
+ * When USE_BUILTIN_STDLIB is defined, we want to test the EC printf
+ * implementation. We need to include the builtin header file directly so
+ * that we can call the EC version (crec_vsnprintf) when linking with the
+ * standard library on the host.
+ */
+#include "builtin/stdio.h"
+#define VSNPRINTF crec_vsnprintf
+#define SNPRINTF crec_snprintf
+static const bool use_builtin_stdlib = true;
+#else
+#include <stdio.h>
+#define VSNPRINTF vsnprintf
+#define SNPRINTF snprintf
+static const bool use_builtin_stdlib = false;
+#endif
+
 #define INIT_VALUE 0x5E
 #define NO_BYTES_TOUCHED NULL
 
 static const char err_str[] = "ERROR";
 static char output[1024];
 
-int run(int expect_ret, const char *expect,
-	bool output_null, size_t size_limit,
+int run(int expect_ret, const char *expect, bool output_null, size_t size_limit,
 	const char *format, va_list args)
 {
 	size_t expect_size = expect ? strlen(expect) + 1 : 0;
@@ -34,10 +51,8 @@ int run(int expect_ret, const char *expect,
 	TEST_ASSERT(expect_size <= size_limit);
 	memset(output, INIT_VALUE, sizeof(output));
 
-	rv = vsnprintf(output_null ? NULL : output, size_limit,
-		       format, args);
-	ccprintf("received='%.*s'   | ret          =%d\n",
-		 30, output, rv);
+	rv = VSNPRINTF(output_null ? NULL : output, size_limit, format, args);
+	ccprintf("received='%.*s'   | ret          =%d\n", 30, output, rv);
 
 	TEST_ASSERT_ARRAY_EQ(output, expect, expect_size);
 	TEST_ASSERT_MEMSET(&output[expect_size], INIT_VALUE,
@@ -59,252 +74,621 @@ int expect_success(const char *expect, const char *format, ...)
 	int rv;
 
 	va_start(args, format);
-	rv = run(EC_SUCCESS, expect,
-		 false, sizeof(output),
-		 format, args);
+	rv = run(EC_SUCCESS, expect, false, sizeof(output), format, args);
 	va_end(args);
 
 	return rv;
 }
 
-int expect(int expect_ret, const char *expect,
-	   bool output_null, size_t size_limit,
-	   const char *format, ...)
+int expect(int expect_ret, const char *expect, bool output_null,
+	   size_t size_limit, const char *format, ...)
 {
 	va_list args;
 	int rv;
 
 	va_start(args, format);
-	rv = run(expect_ret, expect,
-		 output_null, size_limit,
-		 format, args);
+	rv = run(expect_ret, expect, output_null, size_limit, format, args);
 	va_end(args);
 
 	return rv;
 }
 
-#define T(n)                                                                  \
-	do {                                                                  \
-		int rv = (n);                                                 \
-		if (rv != EC_SUCCESS)                                         \
-			return rv;                                            \
+#define T(n)                          \
+	do {                          \
+		int rv = (n);         \
+		if (rv != EC_SUCCESS) \
+			return rv;    \
 	} while (0)
 
 test_static int test_vsnprintf_args(void)
 {
-	T(expect_success("",          ""));
-	T(expect_success("a",         "a"));
-
-	T(expect(/* expect an invalid args error */
-		 EC_ERROR_INVAL, NO_BYTES_TOUCHED,
-		 /* given 0 as output size limit */
-		 false, 0, ""));
+	T(expect_success("", ""));
+	T(expect_success("a", "a"));
+
+	if (use_builtin_stdlib) {
+		/*
+		 * TODO(b/239233116): This differs from the C standard library
+		 * behavior and should probably be changed.
+		 */
+		T(expect(/* expect an invalid args error */
+			 EC_ERROR_INVAL, NO_BYTES_TOUCHED,
+			 /* given 0 as output size limit */
+			 false, 0, ""));
+		T(expect(/* expect an overflow error */
+			 EC_ERROR_OVERFLOW, "",
+			 /* given 1 as output size limit with a non-blank format
+			  */
+			 false, 1, "a"));
+		T(expect(/* expect an invalid args error */
+			 EC_ERROR_INVAL, NO_BYTES_TOUCHED,
+			 /* given NULL as the output buffer */
+			 true, sizeof(output), ""));
+		T(expect(/* expect an invalid args error */
+			 EC_ERROR_INVAL, NO_BYTES_TOUCHED,
+			 /* given a NULL format string */
+			 false, sizeof(output), NULL));
+	}
 	T(expect(/* expect SUCCESS */
 		 EC_SUCCESS, "",
 		 /* given 1 as output size limit and a blank format */
 		 false, 1, ""));
-	T(expect(/* expect an overflow error */
-		 EC_ERROR_OVERFLOW, "",
-		 /* given 1 as output size limit with a non-blank format */
-		 false, 1, "a"));
-
-	T(expect(/* expect an invalid args error */
-		 EC_ERROR_INVAL, NO_BYTES_TOUCHED,
-		 /* given NULL as the output buffer */
-		 true, sizeof(output), ""));
-	T(expect(/* expect an invalid args error */
-		 EC_ERROR_INVAL, NO_BYTES_TOUCHED,
-		 /* given a NULL format string */
-		 false, sizeof(output), NULL));
 
 	return EC_SUCCESS;
 }
 
 test_static int test_vsnprintf_int(void)
 {
-	T(expect_success("123",       "%d",      123));
-	T(expect_success("-123",      "%d",     -123));
-	T(expect_success("+123",      "%+d",     123));
-	T(expect_success("-123",      "%+d",    -123));
-	T(expect_success("123",       "%-d",     123));
-	T(expect_success("-123",      "%-d",    -123));
-
-	T(expect_success("  123",     "%5d",     123));
-	T(expect_success(" +123",     "%+5d",    123));
-	T(expect_success("00123",     "%05d",    123));
-	T(expect_success("00123",     "%005d",   123));
-	/*
-	 * TODO(crbug.com/974084): This odd behavior should be fixed.
-	 * T(expect_success("+0123",     "%+05d",   123));
-	 * Actual: "0+123"
-	 * T(expect_success("+0123",     "%+005d",  123));
-	 * Actual: "0+123"
-	 */
+	T(expect_success("123", "%d", 123));
+	T(expect_success("-123", "%d", -123));
+	T(expect_success("+123", "%+d", 123));
+	T(expect_success("-123", "%+d", -123));
+	T(expect_success("123", "%-d", 123));
+	T(expect_success("-123", "%-d", -123));
+
+	T(expect_success("  123", "%5d", 123));
+	T(expect_success(" +123", "%+5d", 123));
+	T(expect_success("00123", "%05d", 123));
+	T(expect_success("00123", "%005d", 123));
+
+	if (use_builtin_stdlib) {
+		/*
+		 * TODO(b/239233116): These are incorrect and should be fixed.
+		 */
+		/* Fixed point. */
+		T(expect_success("0.00123", "%.5d", 123));
+		T(expect_success("12.3", "%2.1d", 123));
+		/* Precision or width larger than buffer should fail. */
+		T(expect(EC_ERROR_OVERFLOW, "  1", false, 4, "%5d", 123));
+		T(expect(EC_ERROR_OVERFLOW, "   ", false, 4, "%10d", 123));
+		T(expect(EC_ERROR_OVERFLOW, "123", false, 4, "%-10d", 123));
+		T(expect(EC_ERROR_OVERFLOW, "0.0", false, 4, "%.10d", 123));
+	} else {
+		int ret;
+
+		T(expect_success("00123", "%.5d", 123));
+		T(expect_success("123", "%2.1d", 123));
+
+		/*
+		 * From the man page: The functions  snprintf() and vsnprintf()
+		 * do not write more than size bytes (including the
+		 * terminating null byte ('\0')). If the output was truncated
+		 * due to this limit, then the return value is the number of
+		 * characters (excluding the terminating null byte) which
+		 * would have been written to the final string if enough
+		 * space had been available. Thus, a return value of size or
+		 * more means that the output was truncated.
+		 */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wformat-truncation"
+		ret = SNPRINTF(output, 4, "%5d", 123);
+		TEST_ASSERT_ARRAY_EQ(output, "  1", 4);
+		TEST_EQ(ret, 5, "%d");
+
+		ret = SNPRINTF(output, 4, "%10d", 123);
+		TEST_ASSERT_ARRAY_EQ(output, "   ", 4);
+		TEST_EQ(ret, 10, "%d");
+
+		ret = SNPRINTF(output, 4, "%-10d", 123);
+		TEST_ASSERT_ARRAY_EQ(output, "123", 4);
+		TEST_EQ(ret, 10, "%d");
+
+		ret = SNPRINTF(output, 4, "%.10d", 123);
+		TEST_ASSERT_ARRAY_EQ(output, "000", 4);
+		TEST_EQ(ret, 10, "%d");
+#pragma GCC diagnostic pop
+	}
 
-	T(expect_success("  123",     "%*d",     5, 123));
-	T(expect_success(" +123",     "%+*d",    5, 123));
-	T(expect_success("00123",     "%0*d",    5, 123));
-	/*
-	 * TODO(crbug.com/974084): This odd behavior should be fixed.
-	 * T(expect_success("00123",     "%00*d",   5, 123));
-	 * Actual: "ERROR"
-	 */
-	T(expect_success("0+123",     "%+0*d",   5, 123));
-	/*
-	 * TODO(crbug.com/974084): This odd behavior should be fixed.
-	 * T(expect_success("0+123",     "%+00*d",  5, 123));
-	 * Actual: "ERROR"
-	 */
+	if (use_builtin_stdlib) {
+		/*
+		 * TODO(b/239233116): These are incorrect and should be fixed.
+		 */
+		T(expect_success("0+123", "%+05d", 123));
+		T(expect_success("0+123", "%+005d", 123));
+	} else {
+		T(expect_success("+0123", "%+05d", 123));
+		T(expect_success("+0123", "%+005d", 123));
+	}
+
+	T(expect_success("  123", "%*d", 5, 123));
+	T(expect_success(" +123", "%+*d", 5, 123));
+	T(expect_success("00123", "%0*d", 5, 123));
 
-	T(expect_success("123  ",     "%-5d",    123));
-	T(expect_success("+123 ",     "%-+5d",   123));
-	T(expect_success(err_str,     "%+-5d",   123));
-	T(expect_success("123  ",     "%-05d",   123));
-	T(expect_success("123  ",     "%-005d",  123));
-	T(expect_success("+123 ",     "%-+05d",  123));
-	T(expect_success("+123 ",     "%-+005d", 123));
-
-	T(expect_success("0.00123",   "%.5d",    123));
-	T(expect_success("+0.00123",  "%+.5d",   123));
-	T(expect_success("0.00123",   "%7.5d",   123));
-	T(expect_success("  0.00123", "%9.5d",   123));
-	T(expect_success(" +0.00123", "%+9.5d",  123));
-
-	T(expect_success("123",        "%u",    123));
-	T(expect_success("4294967295", "%u",   -1));
+	if (use_builtin_stdlib) {
+		/*
+		 * TODO(b/239233116): This incorrect and should be fixed.
+		 */
+		T(expect_success(err_str, "%00*d", 5, 123));
+	} else {
+		T(expect_success("00123", "%00*d", 5, 123));
+	}
+
+	if (use_builtin_stdlib) {
+		/*
+		 * TODO(b/239233116): This is incorrect and should be fixed.
+		 */
+		T(expect_success("0+123", "%+0*d", 5, 123));
+	} else {
+		T(expect_success("+0123", "%+0*d", 5, 123));
+	}
+
+	if (use_builtin_stdlib) {
+		/*
+		 * TODO(b/239233116): This is incorrect and should be fixed.
+		 */
+		T(expect_success(err_str, "%+00*d", 5, 123));
+	} else {
+		T(expect_success("+0123", "%+00*d", 5, 123));
+	}
+
+	T(expect_success("123  ", "%-5d", 123));
+	T(expect_success("+123 ", "%-+5d", 123));
+	if (use_builtin_stdlib) {
+		/*
+		 * TODO(b/239233116): This incorrect and should be fixed.
+		 */
+		T(expect_success(err_str, "%+-5d", 123));
+	} else {
+		T(expect_success("+123 ", "%+-5d", 123));
+	}
+	T(expect_success("123  ", "%-05d", 123));
+	T(expect_success("123  ", "%-005d", 123));
+	T(expect_success("+123 ", "%-+05d", 123));
+	T(expect_success("+123 ", "%-+005d", 123));
+
+	if (use_builtin_stdlib) {
+		/*
+		 * TODO(b/239233116): These are incorrect and should be fixed.
+		 */
+		T(expect_success("0.00123", "%.5d", 123));
+		T(expect_success("+0.00123", "%+.5d", 123));
+		T(expect_success("0.00123", "%7.5d", 123));
+		T(expect_success("  0.00123", "%9.5d", 123));
+		T(expect_success(" +0.00123", "%+9.5d", 123));
+	} else {
+		T(expect_success("00123", "%.5d", 123));
+		T(expect_success("+00123", "%+.5d", 123));
+		T(expect_success("  00123", "%7.5d", 123));
+		T(expect_success("    00123", "%9.5d", 123));
+		T(expect_success("   +00123", "%+9.5d", 123));
+	}
+
+	T(expect_success("123", "%u", 123));
+	T(expect_success("4294967295", "%u", -1));
 	T(expect_success("18446744073709551615", "%llu", (uint64_t)-1));
 
-	T(expect_success("0",         "%x",     0));
-	T(expect_success("0",         "%X",     0));
-	T(expect_success("5e",        "%x",     0X5E));
-	T(expect_success("5E",        "%X",     0X5E));
+	T(expect_success("0", "%x", 0));
+	T(expect_success("0", "%X", 0));
+	T(expect_success("5e", "%x", 0X5E));
+	T(expect_success("5E", "%X", 0X5E));
+
+	return EC_SUCCESS;
+}
+
+test_static int test_printf_long32_enabled(void)
+{
+	bool use_l32 = IS_ENABLED(CONFIG_PRINTF_LONG_IS_32BITS);
+
+	if (IS_ENABLED(BOARD_BLOONCHIPPER) || IS_ENABLED(BOARD_DARTMONKEY))
+		TEST_ASSERT(use_l32);
+	else
+		TEST_ASSERT(!use_l32);
+	return EC_SUCCESS;
+}
+
+test_static int test_vsnprintf_32bit_long_supported(void)
+{
+	long long_min = INT32_MIN;
+	long long_max = INT32_MAX;
+	unsigned long ulong_max = UINT32_MAX;
+	char const *long_min_str = "-2147483648";
+	char const *long_max_str = "2147483647";
+	char const *ulong_max_str = "4294967295";
+	char const *long_min_hexstr = "80000000";
+	char const *long_max_hexstr = "7fffffff";
+	char const *ulong_max_hexstr = "ffffffff";
+
+	T(expect_success(long_min_str, "%ld", long_min));
+	T(expect_success(long_min_hexstr, "%lx", long_min));
+	T(expect_success(long_max_str, "%ld", long_max));
+	T(expect_success(long_max_hexstr, "%lx", long_max));
+	T(expect_success(ulong_max_str, "%lu", ulong_max));
+	T(expect_success(ulong_max_hexstr, "%lx", ulong_max));
+	T(expect_success(long_max_str, "%ld", long_max));
+
+	T(expect_success(" +123", "%+*ld", 5, 123));
+	T(expect_success("00000123", "%08lu", 123));
+	T(expect_success("131415", "%d%lu%d", 13, 14L, 15));
 
 	/*
-	 * %l is deprecated on 32-bit systems (see crbug.com/984041), but is
-	 * is still functional on 64-bit systems.
+	 * %i and %li are only supported via the CONFIG_PRINTF_LONG_IS_32BITS
+	 * configuration (see https://issuetracker.google.com/issues/172210614).
 	 */
-	if (sizeof(long) == sizeof(uint32_t)) {
-		T(expect_success(err_str,     "%lx",    0x7b));
-		T(expect_success(err_str,     "%08lu",  0x7b));
-		T(expect_success("13ERROR",   "%d%lu", 13, 14));
+	T(expect_success("123", "%i", 123));
+	T(expect_success("123", "%li", 123));
+
+	return EC_SUCCESS;
+}
+
+test_static int test_vsnprintf_64bit_long_supported(void)
+{
+	/* These lines are only executed when sizeof(long) is 64-bits but are
+	 * still compiled by systems with 32-bit longs, so the casts are needed
+	 * to avoid compilation errors.
+	 */
+	long long_min = (long)INT64_MIN;
+	long long_max = (long)INT64_MAX;
+	unsigned long ulong_max = (unsigned long)UINT64_MAX;
+	char const *long_min_str = "-9223372036854775808";
+	char const *long_max_str = "9223372036854775807";
+	char const *ulong_max_str = "18446744073709551615";
+	char const *long_min_hexstr = "8000000000000000";
+	char const *long_max_hexstr = "7fffffffffffffff";
+	char const *ulong_max_hexstr = "ffffffffffffffff";
+
+	T(expect_success(long_min_str, "%ld", long_min));
+	T(expect_success(long_min_hexstr, "%lx", long_min));
+	T(expect_success(long_max_str, "%ld", long_max));
+	T(expect_success(long_max_hexstr, "%lx", long_max));
+	T(expect_success(ulong_max_str, "%lu", ulong_max));
+	T(expect_success(ulong_max_hexstr, "%lx", ulong_max));
+	T(expect_success(long_max_str, "%ld", long_max));
+
+	T(expect_success(" +123", "%+*ld", 5, 123));
+	T(expect_success("00000123", "%08lu", 123));
+	T(expect_success("131415", "%d%lu%d", 13, 14L, 15));
+
+	if (use_builtin_stdlib) {
+		/*
+		 * TODO(b/239233116): These are incorrect and should be fixed.
+		 */
+		T(expect_success(err_str, "%i", 123));
+		T(expect_success(err_str, "%li", 123));
 	} else {
-		T(expect_success("7b",        "%lx",    0x7b));
-		T(expect_success("00000123",  "%08lu",  123));
-		T(expect_success("131415",    "%d%lu%d", 13, 14L, 15));
+		T(expect_success("123", "%i", 123));
+		T(expect_success("123", "%li", 123));
 	}
 
 	return EC_SUCCESS;
 }
 
+test_static int test_vsnprintf_long_not_supported(void)
+{
+	T(expect_success(err_str, "%ld", 0x7b));
+	T(expect_success(err_str, "%li", 0x7b));
+	T(expect_success(err_str, "%lu", 0x7b));
+	T(expect_success(err_str, "%lx", 0x7b));
+	T(expect_success(err_str, "%08lu", 123));
+	T(expect_success("13ERROR", "%d%lu%d", 13, 14L, 15));
+
+	T(expect_success(err_str, "%i", 123));
+	T(expect_success(err_str, "%li", 123));
+
+	return EC_SUCCESS;
+}
+
+test_static int test_vsnprintf_long(void)
+{
+	/*
+	 * %l is functional on 64-bit systems but is not supported on 32-bit
+	 * systems (see https://issuetracker.google.com/issues/172210614) unless
+	 * explicitly enabled via configuration.
+	 */
+	if (IS_ENABLED(CONFIG_PRINTF_LONG_IS_32BITS))
+		return test_vsnprintf_32bit_long_supported();
+	else if (sizeof(long) == sizeof(uint64_t))
+		return test_vsnprintf_64bit_long_supported();
+	else
+		return test_vsnprintf_long_not_supported();
+}
+
 test_static int test_vsnprintf_pointers(void)
 {
 	void *ptr = (void *)0x55005E00;
-	unsigned int val = 0;
-
-	T(expect_success("55005e00",  "%pP",     ptr));
-	T(expect_success(err_str,     "%P",      ptr));
-	/* %p by itself is invalid */
-	T(expect(EC_ERROR_INVAL, NO_BYTES_TOUCHED,
-		 false, 0, "%p"));
-	/* %p with an unknown suffix is invalid */
-	T(expect(EC_ERROR_INVAL, NO_BYTES_TOUCHED,
-		 false, 0, "%p "));
-	/* %p with an unknown suffix is invalid */
-	T(expect(EC_ERROR_INVAL, NO_BYTES_TOUCHED,
-		 false, 0, "%pQ"));
-
-	/* Test %pb, binary format */
-	T(expect_success("0",         "%pb",     BINARY_VALUE(val, 0)));
-	val = 0x5E;
-	T(expect_success("1011110",   "%pb",     BINARY_VALUE(val, 0)));
-	T(expect_success("0000000001011110", "%pb", BINARY_VALUE(val, 16)));
-	val = 0x12345678;
-	T(expect_success("10010001101000101011001111000", "%pb",
-			 BINARY_VALUE(val, 0)));
-	val = 0xFEDCBA90;
-	/* Test a number that makes the longest string possible */
-	T(expect_success("11111110110111001011101010010000", "%pb",
-			 BINARY_VALUE(val, 0)));
+
+	if (use_builtin_stdlib) {
+		/*
+		 * TODO(b/239233116): This incorrect and should be fixed.
+		 */
+		T(expect_success("55005e00", "%p", ptr));
+	} else {
+		T(expect_success("0x55005e00", "%p", ptr));
+	}
+
 	return EC_SUCCESS;
 }
 
 test_static int test_vsnprintf_chars(void)
 {
-	T(expect_success("a",         "%c",      'a'));
-	T(expect_success("*",         "%c",      '*'));
+	T(expect_success("a", "%c", 'a'));
+	T(expect_success("*", "%c", '*'));
 	return EC_SUCCESS;
 }
 
 test_static int test_vsnprintf_strings(void)
 {
-	T(expect_success("abc",       "%s",      "abc"));
-	T(expect_success("  abc",     "%5s",     "abc"));
-	T(expect_success("abc",       "%0s",     "abc"));
-	T(expect_success("abc  ",     "%-5s",    "abc"));
-	T(expect_success("abc",       "%*s",     0, "abc"));
-	T(expect_success("a",         "%.1s",    "abc"));
-	T(expect_success("a",         "%.*s",    1, "abc"));
-	T(expect_success("",          "%.0s",    "abc"));
-	T(expect_success("",          "%.*s",    0, "abc"));
-	/*
-	 * TODO(crbug.com/974084):
-	 * Ignoring the padding parameter is slightly
-	 * odd behavior and could use a review.
-	 */
-	T(expect_success("ab",        "%5.2s",   "abc"));
-	T(expect_success("abc",        "%.4s",   "abc"));
+	T(expect_success("abc", "%s", "abc"));
+	T(expect_success("  abc", "%5s", "abc"));
+	T(expect_success("abc", "%0s", "abc"));
+	T(expect_success("abc  ", "%-5s", "abc"));
+	T(expect_success("abc", "%*s", 0, "abc"));
+	T(expect_success("a", "%.1s", "abc"));
+	T(expect_success("a", "%.*s", 1, "abc"));
+	T(expect_success("", "%.0s", "abc"));
+	T(expect_success("", "%.*s", 0, "abc"));
+	if (use_builtin_stdlib) {
+		/*
+		 * TODO(b/239233116): This incorrect and should be fixed.
+		 */
+		T(expect_success("ab", "%5.2s", "abc"));
+	} else {
+		T(expect_success("   ab", "%5.2s", "abc"));
+	}
+	T(expect_success("abc", "%.4s", "abc"));
 
 	/*
 	 * Given a malformed string (address 0x1 is a good example),
 	 * if we ask for zero precision, expect no bytes to be read
 	 * from the malformed address and a blank output string.
 	 */
-	T(expect_success("",          "%.0s",    (char *)1));
+	T(expect_success("", "%.0s", (char *)1));
 
 	return EC_SUCCESS;
 }
 
-test_static int test_vsnprintf_timestamps(void)
+test_static int test_snprintf_timestamp(void)
 {
+	char str[PRINTF_TIMESTAMP_BUF_SIZE];
+	int size;
+	int ret;
 	uint64_t ts = 0;
 
-	T(expect_success("0.000000",       "%pT",      &ts));
+	/* Success cases. */
+
+	ret = snprintf_timestamp(str, sizeof(str), ts);
+	TEST_EQ(ret, 8, "%d");
+	TEST_ASSERT_ARRAY_EQ(str, "0.000000", sizeof("0.000000"));
+
 	ts = 123456;
-	T(expect_success("0.123456",       "%pT",      &ts));
+	ret = snprintf_timestamp(str, sizeof(str), ts);
+	TEST_EQ(ret, 8, "%d");
+	TEST_ASSERT_ARRAY_EQ(str, "0.123456", sizeof("0.123456"));
+
 	ts = 9999999000000;
-	T(expect_success("9999999.000000", "%pT",      &ts));
+	ret = snprintf_timestamp(str, sizeof(str), ts);
+	TEST_EQ(ret, 14, "%d");
+	TEST_ASSERT_ARRAY_EQ(str, "9999999.000000", sizeof("9999999.000000"));
+
+	ts = UINT64_MAX;
+	ret = snprintf_timestamp(str, sizeof(str), ts);
+	TEST_EQ(ret, 21, "%d");
+	TEST_ASSERT_ARRAY_EQ(str, "18446744073709.551615",
+			     sizeof("18446744073709.551615"));
+
+	/* Error cases. */
+
+	/* Buffer is too small by one. */
+	size = 21;
+	ts = UINT64_MAX;
+	str[0] = 'f';
+	ret = snprintf_timestamp(str, size, ts);
+	TEST_EQ(ret, -EC_ERROR_OVERFLOW, "%d");
+	TEST_EQ(str[0], '\0', "%d");
+
+	/* Size is zero. */
+	size = 0;
+	ts = UINT64_MAX;
+	str[0] = 'f';
+	ret = snprintf_timestamp(str, size, ts);
+	TEST_EQ(ret, -EC_ERROR_INVAL, "%d");
+	TEST_EQ(str[0], 'f', "%d");
+
+	/* Size is one. */
+	size = 1;
+	ts = UINT64_MAX;
+	str[0] = 'f';
+	ret = snprintf_timestamp(str, size, ts);
+	TEST_EQ(ret, -EC_ERROR_OVERFLOW, "%d");
+	TEST_EQ(str[0], '\0', "%d");
+
 	return EC_SUCCESS;
 }
 
-test_static int test_vsnprintf_hexdump(void)
+test_static int test_snprintf_hex_buffer(void)
 {
-	const char bytes[] = {0x00, 0x5E};
+	const uint8_t bytes[] = { 0xAB, 0x5E };
+	char str_buf[5];
+	int rv;
+
+	/* Success cases. */
+
+	memset(str_buf, 0xff, sizeof(str_buf));
+	rv = snprintf_hex_buffer(str_buf, sizeof(str_buf), HEX_BUF(bytes, 2));
+	TEST_ASSERT_ARRAY_EQ(str_buf, "ab5e", sizeof("ab5e"));
+	TEST_EQ(rv, 4, "%d");
+
+	memset(str_buf, 0xff, sizeof(str_buf));
+	rv = snprintf_hex_buffer(str_buf, sizeof(str_buf), HEX_BUF(bytes, 0));
+	TEST_ASSERT_ARRAY_EQ(str_buf, "", sizeof(""));
+	TEST_EQ(rv, 0, "%d");
+
+	memset(str_buf, 0xff, sizeof(str_buf));
+	rv = snprintf_hex_buffer(str_buf, sizeof(str_buf), HEX_BUF(bytes, 1));
+	TEST_ASSERT_ARRAY_EQ(str_buf, "ab", sizeof("ab"));
+	TEST_EQ(rv, 2, "%d");
+
+	/* Error cases. */
+
+	/* Zero for buffer size argument is an error. */
+	memset(str_buf, 0xff, sizeof(str_buf));
+	TEST_ASSERT_MEMSET(str_buf, (char)0xff, sizeof(str_buf));
+	rv = snprintf_hex_buffer(str_buf, 0, HEX_BUF(bytes, 2));
+	TEST_EQ(rv, -EC_ERROR_INVAL, "%d");
+	TEST_ASSERT_MEMSET(str_buf, (char)0xff, sizeof(str_buf));
+
+	/* Buffer only has space for terminating '\0'. */
+	memset(str_buf, 0xff, sizeof(str_buf));
+	TEST_ASSERT_MEMSET(str_buf, (char)0xff, sizeof(str_buf));
+	rv = snprintf_hex_buffer(str_buf, 1, HEX_BUF(bytes, 1));
+	TEST_ASSERT_ARRAY_EQ(str_buf, "", sizeof(""));
+	TEST_EQ(rv, -EC_ERROR_OVERFLOW, "%d");
+
+	/* Buffer only has space for one character and '\0'. */
+	memset(str_buf, 0xff, sizeof(str_buf));
+	TEST_ASSERT_MEMSET(str_buf, (char)0xff, sizeof(str_buf));
+	rv = snprintf_hex_buffer(str_buf, 2, HEX_BUF(bytes, 1));
+	TEST_ASSERT_ARRAY_EQ(str_buf, "a", sizeof("a"));
+	TEST_EQ(rv, -EC_ERROR_OVERFLOW, "%d");
 
-	T(expect_success("005e",      "%ph",      HEX_BUF(bytes, 2)));
-	T(expect_success("",          "%ph",      HEX_BUF(bytes, 0)));
-	T(expect_success("00",        "%ph",      HEX_BUF(bytes, 1)));
 	return EC_SUCCESS;
 }
 
 test_static int test_vsnprintf_combined(void)
 {
-	T(expect_success("abc",       "%c%s",    'a', "bc"));
-	T(expect_success("12\tbc",    "%d\t%s",  12, "bc"));
+	T(expect_success("abc", "%c%s", 'a', "bc"));
+	T(expect_success("12\tbc", "%d\t%s", 12, "bc"));
+	return EC_SUCCESS;
+}
+
+test_static int test_uint64_to_str(void)
+{
+	/* Longest uin64 in decimal = 20, plus terminating NUL. */
+	char buf[21];
+	char *str;
+
+	str = uint64_to_str(buf, sizeof(buf), /*val=*/0, /*precision=*/-1,
+			    /*base=*/10, /*uppercase=*/false);
+	TEST_ASSERT_ARRAY_EQ(str, "0", sizeof("0"));
+
+	str = uint64_to_str(buf, sizeof(buf), /*val=*/UINT64_MAX,
+			    /*precision=*/-1, /*base=*/10,
+			    /*uppercase=*/false);
+	TEST_ASSERT_ARRAY_EQ(str, "18446744073709551615",
+			     sizeof("18446744073709551615"));
+
+	/* Buffer too small by 1. */
+	str = uint64_to_str(buf, /*buf_len=*/20, /*val=*/UINT64_MAX,
+			    /*precision=*/-1, /*base=*/10, /*uppercase=*/false);
+	TEST_ASSERT(str == NULL);
+
+	/* lower case hex */
+	str = uint64_to_str(buf, sizeof(buf), /*val=*/0, /*precision=*/-1,
+			    /*base=*/16, /*uppercase=*/false);
+	TEST_ASSERT_ARRAY_EQ(str, "0", sizeof("0"));
+
+	/* lower case hex */
+	str = uint64_to_str(buf, sizeof(buf), /*val=*/UINT64_MAX,
+			    /*precision=*/-1, /*base=*/16,
+			    /*uppercase=*/false);
+	TEST_ASSERT_ARRAY_EQ(str, "ffffffffffffffff",
+			     sizeof("fffffffffffffff"));
+
+	/* upper case hex */
+	str = uint64_to_str(buf, sizeof(buf), /*val=*/0, /*precision=*/-1,
+			    /*base=*/16, /*uppercase=*/true);
+	TEST_ASSERT_ARRAY_EQ(str, "0", sizeof("0"));
+
+	str = uint64_to_str(buf, sizeof(buf), /*val=*/UINT64_MAX,
+			    /*precision=*/-1, /*base=*/16,
+			    /*uppercase=*/true);
+	TEST_ASSERT_ARRAY_EQ(str, "FFFFFFFFFFFFFFFF",
+			     sizeof("FFFFFFFFFFFFFFF"));
+
+	/* precision 0 */
+	str = uint64_to_str(buf, sizeof(buf), /*val=*/1, /*precision=*/0,
+			    /*base=*/10, /*uppercase=*/false);
+	TEST_ASSERT_ARRAY_EQ(str, "1.", sizeof("1."));
+
+	/* precision 6 */
+	str = uint64_to_str(buf, sizeof(buf), /*val=*/1, /*precision=*/6,
+			    /*base=*/10, /*uppercase=*/false);
+	TEST_ASSERT_ARRAY_EQ(str, "0.000001", sizeof("0.000001"));
+
+	/* Reduced precision due to buffer that is too small. */
+	str = uint64_to_str(buf, /*buf_len=*/8, /*val=*/1, /*precision=*/6,
+			    /*base=*/10, /*uppercase=*/false);
+	TEST_ASSERT_ARRAY_EQ(str, "0.00001", sizeof("0.00001"));
+
+	/*
+	 * Reduced precision due to buffer that is too small, so precision
+	 * gets changed to 0.
+	 */
+	str = uint64_to_str(buf, /*buf_len=*/3, /*val=*/1, /*precision=*/6,
+			    /*base=*/10, /*uppercase=*/false);
+	TEST_ASSERT_ARRAY_EQ(str, "1.", sizeof("1."));
+
+	/* Precision is unable to fit in provided buffer. */
+	str = uint64_to_str(buf, /*buf_len=*/2, /*val=*/1, /*precision=*/6,
+			    /*base=*/10, /*uppercase=*/false);
+	TEST_ASSERT(str == NULL);
+
+	/* Negative base. */
+	str = uint64_to_str(buf, sizeof(buf), /*val=*/0, /*precision=*/-1,
+			    /*base=*/-1, /*uppercase=*/false);
+	TEST_ASSERT(str == NULL);
+
+	/* Base zero. */
+	str = uint64_to_str(buf, sizeof(buf), /*val=*/1, /*precision=*/-1,
+			    /*base=*/0, /*uppercase=*/false);
+	TEST_ASSERT(str == NULL);
+
+	/* Base one. */
+	str = uint64_to_str(buf, sizeof(buf), /*val=*/1, /*precision=*/-1,
+			    /*base=*/1, /*uppercase=*/false);
+	TEST_ASSERT(str == NULL);
+
+	/* Buffer size 1. */
+	str = uint64_to_str(buf, /*buf_len=*/1, /*val=*/0, /*precision=*/-1,
+			    /*base=*/10, /*uppercase=*/false);
+	TEST_ASSERT(str == NULL);
+
+	/* Buffer size 0. */
+	str = uint64_to_str(buf, /*buf_len=*/0, /*val=*/0, /*precision=*/-1,
+			    /*base=*/10, /*uppercase=*/false);
+	TEST_ASSERT(str == NULL);
+
+	/* Buffer size -1. */
+	str = uint64_to_str(buf, /*buf_len=*/-1, /*val=*/0, /*precision=*/-1,
+			    /*base=*/10, /*uppercase=*/false);
+	TEST_ASSERT(str == NULL);
+
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
 	RUN_TEST(test_vsnprintf_args);
 	RUN_TEST(test_vsnprintf_int);
+	RUN_TEST(test_printf_long32_enabled);
+	RUN_TEST(test_vsnprintf_long);
 	RUN_TEST(test_vsnprintf_pointers);
 	RUN_TEST(test_vsnprintf_chars);
 	RUN_TEST(test_vsnprintf_strings);
-	RUN_TEST(test_vsnprintf_timestamps);
-	RUN_TEST(test_vsnprintf_hexdump);
 	RUN_TEST(test_vsnprintf_combined);
+	RUN_TEST(test_uint64_to_str);
+	RUN_TEST(test_snprintf_timestamp);
+	RUN_TEST(test_snprintf_hex_buffer);
 
 	test_print_result();
 }
diff --git a/test/printf.tasklist b/test/printf.tasklist
index 9fc1a80f4d..844ddb6c10 100644
--- a/test/printf.tasklist
+++ b/test/printf.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/queue.c b/test/queue.c
index e0be1b5d9a..c21e00a050 100644
--- a/test/queue.c
+++ b/test/queue.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -40,7 +40,7 @@ static int test_queue8_init(void)
 
 static int test_queue8_fifo(void)
 {
-	char buf1[3] = {1, 2, 3};
+	char buf1[3] = { 1, 2, 3 };
 	char buf2[3];
 
 	TEST_ASSERT(queue_add_units(&test_queue8, buf1 + 0, 1) == 1);
@@ -55,7 +55,7 @@ static int test_queue8_fifo(void)
 
 static int test_queue8_multiple_units_add(void)
 {
-	char buf1[5] = {1, 2, 3, 4, 5};
+	char buf1[5] = { 1, 2, 3, 4, 5 };
 	char buf2[5];
 
 	TEST_ASSERT(queue_space(&test_queue8) >= 5);
@@ -68,7 +68,7 @@ static int test_queue8_multiple_units_add(void)
 
 static int test_queue8_removal(void)
 {
-	char buf1[5] = {1, 2, 3, 4, 5};
+	char buf1[5] = { 1, 2, 3, 4, 5 };
 	char buf2[5];
 
 	TEST_ASSERT(queue_add_units(&test_queue8, buf1, 5) == 5);
@@ -105,7 +105,7 @@ static int test_queue8_removal(void)
 
 static int test_queue8_peek(void)
 {
-	char buf1[5] = {1, 2, 3, 4, 5};
+	char buf1[5] = { 1, 2, 3, 4, 5 };
 	char buf2[5];
 
 	TEST_ASSERT(queue_add_units(&test_queue8, buf1, 5) == 5);
@@ -122,7 +122,7 @@ static int test_queue8_peek(void)
 
 static int test_queue2_odd_even(void)
 {
-	uint16_t buf1[3] = {1, 2, 3};
+	uint16_t buf1[3] = { 1, 2, 3 };
 	uint16_t buf2[3];
 
 	TEST_ASSERT(queue_add_units(&test_queue2, buf1, 1) == 1);
@@ -147,7 +147,7 @@ static int test_queue2_odd_even(void)
 
 static int test_queue8_chunks(void)
 {
-	static uint8_t const data[3] = {1, 2, 3};
+	static uint8_t const data[3] = { 1, 2, 3 };
 	struct queue_chunk chunk;
 
 	chunk = queue_get_write_chunk(&test_queue8, 0);
@@ -161,7 +161,7 @@ static int test_queue8_chunks(void)
 	chunk = queue_get_read_chunk(&test_queue8);
 
 	TEST_ASSERT(chunk.count == 3);
-	TEST_ASSERT_ARRAY_EQ((uint8_t *) chunk.buffer, data, 3);
+	TEST_ASSERT_ARRAY_EQ((uint8_t *)chunk.buffer, data, 3);
 
 	TEST_ASSERT(queue_advance_head(&test_queue8, 3) == 3);
 	TEST_ASSERT(queue_is_empty(&test_queue8));
@@ -171,7 +171,7 @@ static int test_queue8_chunks(void)
 
 static int test_queue8_chunks_wrapped(void)
 {
-	static uint8_t const data[3] = {1, 2, 3};
+	static uint8_t const data[3] = { 1, 2, 3 };
 
 	/* Move near the end of the queue */
 	TEST_ASSERT(queue_advance_tail(&test_queue8, 6) == 6);
@@ -213,7 +213,7 @@ static int test_queue8_chunks_wrapped(void)
 
 static int test_queue8_chunks_full(void)
 {
-	static uint8_t const data[8] = {1, 2, 3, 4, 5, 6, 7, 8};
+	static uint8_t const data[8] = { 1, 2, 3, 4, 5, 6, 7, 8 };
 	struct queue_chunk chunk;
 
 	/* Move near the end of the queue */
@@ -230,7 +230,7 @@ static int test_queue8_chunks_full(void)
 	chunk = queue_get_read_chunk(&test_queue8);
 
 	TEST_ASSERT(chunk.count == 2);
-	TEST_ASSERT_ARRAY_EQ((uint8_t *) chunk.buffer, data, 2);
+	TEST_ASSERT_ARRAY_EQ((uint8_t *)chunk.buffer, data, 2);
 
 	/* Signal that we have read both units */
 	TEST_ASSERT(queue_advance_head(&test_queue8, 2) == 2);
@@ -239,8 +239,7 @@ static int test_queue8_chunks_full(void)
 	chunk = queue_get_read_chunk(&test_queue8);
 
 	TEST_ASSERT(chunk.count == 6);
-	TEST_ASSERT_ARRAY_EQ((uint8_t *) chunk.buffer, data + 2, 6);
-
+	TEST_ASSERT_ARRAY_EQ((uint8_t *)chunk.buffer, data + 2, 6);
 
 	return EC_SUCCESS;
 }
@@ -287,12 +286,12 @@ static int test_queue8_chunks_offset(void)
 	/* Check offsetting by 1 */
 	TEST_ASSERT(queue_get_write_chunk(&test_queue8, 1).count == 7);
 	TEST_ASSERT(queue_get_write_chunk(&test_queue8, 1).buffer ==
-			test_queue8.buffer + 1);
+		    test_queue8.buffer + 1);
 
 	/* Check offsetting by 4 */
 	TEST_ASSERT(queue_get_write_chunk(&test_queue8, 4).count == 4);
 	TEST_ASSERT(queue_get_write_chunk(&test_queue8, 4).buffer ==
-			test_queue8.buffer + 4);
+		    test_queue8.buffer + 4);
 
 	/* Check offset wrapping around */
 	TEST_ASSERT(queue_get_write_chunk(&test_queue8, 10).count == 0);
@@ -309,12 +308,12 @@ static int test_queue8_chunks_offset(void)
 	/* Get writable chunk to right of tail. */
 	TEST_ASSERT(queue_get_write_chunk(&test_queue8, 2).count == 2);
 	TEST_ASSERT(queue_get_write_chunk(&test_queue8, 2).buffer ==
-			test_queue8.buffer + 6);
+		    test_queue8.buffer + 6);
 
 	/* Get writable chunk wrapped and before head. */
 	TEST_ASSERT(queue_get_write_chunk(&test_queue8, 4).count == 2);
 	TEST_ASSERT(queue_get_write_chunk(&test_queue8, 4).buffer ==
-			test_queue8.buffer);
+		    test_queue8.buffer);
 
 	/* Check offsetting into non-writable memory. */
 	TEST_ASSERT(queue_get_write_chunk(&test_queue8, 6).count == 0);
@@ -415,7 +414,7 @@ void before_test(void)
 	queue_init(&test_queue8);
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/queue.tasklist b/test/queue.tasklist
index da0ab6211a..100cb6b5bd 100644
--- a/test/queue.tasklist
+++ b/test/queue.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/rgb_keyboard.c b/test/rgb_keyboard.c
index a8da437f7c..d32215e649 100644
--- a/test/rgb_keyboard.c
+++ b/test/rgb_keyboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -51,12 +51,11 @@ const uint8_t rgbkbd_count = ARRAY_SIZE(rgbkbds);
 const uint8_t rgbkbd_hsize = RGB_GRID0_COL + RGB_GRID1_COL;
 const uint8_t rgbkbd_vsize = RGB_GRID0_ROW;
 
+enum ec_rgbkbd_type rgbkbd_type = EC_RGBKBD_TYPE_UNKNOWN;
+
 const uint8_t rgbkbd_map[] = {
-	RGBKBD_DELM,
-	RGBKBD_COORD(1, 2), RGBKBD_DELM,
-	RGBKBD_COORD(3, 4), RGBKBD_COORD(5, 6), RGBKBD_DELM,
-	RGBKBD_DELM,
-	RGBKBD_DELM,
+	RGBKBD_DELM,	    RGBKBD_COORD(1, 2), RGBKBD_DELM, RGBKBD_COORD(3, 4),
+	RGBKBD_COORD(5, 6), RGBKBD_DELM,	RGBKBD_DELM, RGBKBD_DELM,
 };
 const size_t rgbkbd_map_size = ARRAY_SIZE(rgbkbd_map);
 
@@ -72,9 +71,13 @@ static struct rgbkbd_mock {
 	uint32_t gcc_level;
 } mock_state;
 
-__override void board_kblight_init(void) {}
+__override void board_kblight_init(void)
+{
+}
 
-__override void board_kblight_shutdown(void) {}
+__override void board_kblight_shutdown(void)
+{
+}
 
 void before_test(void)
 {
@@ -106,7 +109,6 @@ static int test_drv_set_color(struct rgbkbd *ctx, uint8_t offset,
 	return EC_SUCCESS;
 }
 
-
 static int test_drv_set_scale(struct rgbkbd *ctx, uint8_t offset,
 			      struct rgb_s scale, uint8_t len)
 {
@@ -130,8 +132,8 @@ static int test_rgbkbd_map(void)
 	rgbkbd_init_lookup_table();
 
 	led.u8 = rgbkbd_map[rgbkbd_table[0]];
-	zassert_equal(RGBKBD_COORD(led.coord.x, led.coord.y),
-		      RGBKBD_DELM, "key[0] -> None");
+	zassert_equal(RGBKBD_COORD(led.coord.x, led.coord.y), RGBKBD_DELM,
+		      "key[0] -> None");
 
 	led.u8 = rgbkbd_map[rgbkbd_table[1]];
 	zassert_equal(RGBKBD_COORD(led.coord.x, led.coord.y),
@@ -145,12 +147,12 @@ static int test_rgbkbd_map(void)
 		      RGBKBD_COORD(5, 6), "key[2] -> LED(5,6)");
 
 	led.u8 = rgbkbd_map[rgbkbd_table[3]];
-	zassert_equal(RGBKBD_COORD(led.coord.x, led.coord.y),
-		      RGBKBD_DELM, "key[3] -> None");
+	zassert_equal(RGBKBD_COORD(led.coord.x, led.coord.y), RGBKBD_DELM,
+		      "key[3] -> None");
 
 	led.u8 = rgbkbd_map[rgbkbd_table[4]];
-	zassert_equal(RGBKBD_COORD(led.coord.x, led.coord.y),
-		      RGBKBD_DELM, "key[4] -> None");
+	zassert_equal(RGBKBD_COORD(led.coord.x, led.coord.y), RGBKBD_DELM,
+		      "key[4] -> None");
 
 	return EC_SUCCESS;
 }
@@ -210,7 +212,7 @@ static int test_rgbkbd_startup(void)
 	return EC_SUCCESS;
 }
 
-int cc_rgb(int argc, char **argv);
+int cc_rgb(int argc, const char **argv);
 extern enum ec_rgbkbd_demo demo;
 
 static int test_rgbkbd_console_command(void)
@@ -220,10 +222,10 @@ static int test_rgbkbd_console_command(void)
 	char buf[8];
 	int i, x, y, r, c;
 	uint8_t offset;
-	char *argv_demo[] = {"rgbk", "demo", "0"};
-	char *argv_gcc[] = {"rgbk", "100"};
-	char *argv_color[] = {"rgbk", buf, "0x010203"};
-	char *argv_all[] = {"rgbk", "all", "0x010203"};
+	const char *argv_demo[] = { "rgbk", "demo", "0" };
+	const char *argv_gcc[] = { "rgbk", "100" };
+	const char *argv_color[] = { "rgbk", buf, "0x010203" };
+	const char *argv_all[] = { "rgbk", "all", "0x010203" };
 
 	/* Test 'rgbk demo 0'. */
 	before_test();
@@ -248,8 +250,8 @@ static int test_rgbkbd_console_command(void)
 	offset = rgbkbd_vsize * x + y;
 	sprintf(buf, "%d,%d", x, y);
 	argc = ARRAY_SIZE(argv_color);
-	zassert_equal(cc_rgb(argc, argv_color), EC_SUCCESS,
-		      "rgbk %s 0x010203", buf);
+	zassert_equal(cc_rgb(argc, argv_color), EC_SUCCESS, "rgbk %s 0x010203",
+		      buf);
 	zassert_equal(ctx->buf[offset].r, 1, "R = 1");
 	zassert_equal(ctx->buf[offset].g, 2, "G = 2");
 	zassert_equal(ctx->buf[offset].b, 3, "B = 3");
@@ -261,8 +263,8 @@ static int test_rgbkbd_console_command(void)
 	y = -1;
 	sprintf(buf, "%d,%d", x, y);
 	argc = ARRAY_SIZE(argv_color);
-	zassert_equal(cc_rgb(argc, argv_color), EC_SUCCESS,
-		      "rgbk %s 1 2 3", buf);
+	zassert_equal(cc_rgb(argc, argv_color), EC_SUCCESS, "rgbk %s 1 2 3",
+		      buf);
 	for (r = 0; r < rgbkbd_vsize; r++) {
 		offset = rgbkbd_vsize * x + r;
 		zassert_equal(ctx->buf[offset].r, 1, "R = 1");
@@ -276,8 +278,8 @@ static int test_rgbkbd_console_command(void)
 	y = 1;
 	sprintf(buf, "%d,%d", x, y);
 	argc = ARRAY_SIZE(argv_color);
-	zassert_equal(cc_rgb(argc, argv_color), EC_SUCCESS,
-		      "rgbk %s 1 2 3", buf);
+	zassert_equal(cc_rgb(argc, argv_color), EC_SUCCESS, "rgbk %s 1 2 3",
+		      buf);
 	for (c = 0; c < rgbkbd_hsize; c++) {
 		ctx = &rgbkbds[c / rgbkbds[0].cfg->col_len];
 		offset = rgbkbd_vsize * (c % ctx->cfg->col_len) + y;
@@ -340,7 +342,7 @@ static int test_rgbkbd_rotate_color(void)
 static int test_rgbkbd_demo_flow(void)
 {
 	struct rgb_s copy[ARRAY_SIZE(rgbkbds)][RGB_GRID0_COL * RGB_GRID0_ROW];
-	char *argv_demo[] = {"rgbk", "demo", "1"};
+	const char *argv_demo[] = { "rgbk", "demo", "1" };
 	struct rgb_s *p;
 	int argc;
 	struct rgbkbd *ctx;
@@ -385,7 +387,7 @@ static int test_rgbkbd_demo_flow(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	RUN_TEST(test_rgbkbd_startup);
 	RUN_TEST(test_rgbkbd_console_command);
diff --git a/test/rgb_keyboard.tasklist b/test/rgb_keyboard.tasklist
index fb85751609..9b25deacfb 100644
--- a/test/rgb_keyboard.tasklist
+++ b/test/rgb_keyboard.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/rollback.c b/test/rollback.c
index 2038333311..e2c1070ef4 100644
--- a/test/rollback.c
+++ b/test/rollback.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -47,7 +47,7 @@ test_static int read_rollback_region(const struct rollback_info *info,
 
 	for (i = 0; i < info->region_size_bytes; i++) {
 		if (crec_flash_read(offset + i, sizeof(data), &data) ==
-			EC_SUCCESS)
+		    EC_SUCCESS)
 			bytes_read++;
 	}
 
@@ -105,7 +105,7 @@ test_static int test_lock_rollback_region_1(void)
 	return _test_lock_rollback(&rollback_info, 1);
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	if (argc < 2) {
 		ccprintf("usage: runtest [region0|region1]\n");
diff --git a/test/rollback.tasklist b/test/rollback.tasklist
index 51734f058d..a1f1a94e2d 100644
--- a/test/rollback.tasklist
+++ b/test/rollback.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/rollback_entropy.c b/test/rollback_entropy.c
index 788fab2572..50a8cb4701 100644
--- a/test/rollback_entropy.c
+++ b/test/rollback_entropy.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,9 +12,7 @@
 static const uint32_t VALID_ROLLBACK_COOKIE = 0x0b112233;
 static const uint32_t UNINITIALIZED_ROLLBACK_COOKIE = 0xffffffff;
 
-static const uint8_t FAKE_ENTROPY[] = {
-	0xff, 0xff, 0xff, 0xff
-};
+static const uint8_t FAKE_ENTROPY[] = { 0xff, 0xff, 0xff, 0xff };
 
 /*
  * Generated by concatenating 32-bytes (256-bits) of zeros with the 4 bytes
@@ -26,13 +24,12 @@ static const uint8_t FAKE_ENTROPY[] = {
  *
  * 890ed82cf09f22243bdc4252e4d79c8a9810c1391f455dce37a7b732eb0a0e4f
  */
-#define EXPECTED_SECRET \
-	0x89, 0x0e, 0xd8, 0x2c, 0xf0, 0x9f, 0x22, 0x24, 0x3b, 0xdc, 0x42, \
-	0x52, 0xe4, 0xd7, 0x9c, 0x8a, 0x98, 0x10, 0xc1, 0x39, 0x1f, 0x45, \
-	0x5d, 0xce, 0x37, 0xa7, 0xb7, 0x32, 0xeb, 0x0a, 0x0e, 0x4f
-__maybe_unused static const uint8_t _EXPECTED_SECRET[] = {
-	EXPECTED_SECRET
-};
+#define EXPECTED_SECRET                                                     \
+	0x89, 0x0e, 0xd8, 0x2c, 0xf0, 0x9f, 0x22, 0x24, 0x3b, 0xdc, 0x42,   \
+		0x52, 0xe4, 0xd7, 0x9c, 0x8a, 0x98, 0x10, 0xc1, 0x39, 0x1f, \
+		0x45, 0x5d, 0xce, 0x37, 0xa7, 0xb7, 0x32, 0xeb, 0x0a, 0x0e, \
+		0x4f
+__maybe_unused static const uint8_t _EXPECTED_SECRET[] = { EXPECTED_SECRET };
 BUILD_ASSERT(sizeof(_EXPECTED_SECRET) == CONFIG_ROLLBACK_SECRET_SIZE);
 
 /*
@@ -45,22 +42,20 @@ BUILD_ASSERT(sizeof(_EXPECTED_SECRET) == CONFIG_ROLLBACK_SECRET_SIZE);
  *
  * b5d2c08b1f9109ac5c67de15486f0ac267ef9501bd9f646f4ea80085cb08284c
  */
-#define EXPECTED_SECRET2 \
-	0xb5, 0xd2, 0xc0, 0x8b, 0x1f, 0x91, 0x09, 0xac, 0x5c, 0x67, 0xde, \
-	0x15, 0x48, 0x6f, 0x0a, 0xc2, 0x67, 0xef, 0x95, 0x01, 0xbd, 0x9f, \
-	0x64, 0x6f, 0x4e, 0xa8, 0x00, 0x85, 0xcb, 0x08, 0x28, 0x4c
-__maybe_unused static const uint8_t _EXPECTED_SECRET2[] = {
-	EXPECTED_SECRET2
-};
+#define EXPECTED_SECRET2                                                    \
+	0xb5, 0xd2, 0xc0, 0x8b, 0x1f, 0x91, 0x09, 0xac, 0x5c, 0x67, 0xde,   \
+		0x15, 0x48, 0x6f, 0x0a, 0xc2, 0x67, 0xef, 0x95, 0x01, 0xbd, \
+		0x9f, 0x64, 0x6f, 0x4e, 0xa8, 0x00, 0x85, 0xcb, 0x08, 0x28, \
+		0x4c
+__maybe_unused static const uint8_t _EXPECTED_SECRET2[] = { EXPECTED_SECRET2 };
 BUILD_ASSERT(sizeof(_EXPECTED_SECRET2) == CONFIG_ROLLBACK_SECRET_SIZE);
 
-#define EXPECTED_UNINITIALIZED_ROLLBACK_SECRET \
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, \
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, \
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, \
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-__maybe_unused static const uint8_t
-_EXPECTED_UNINITIALIZED_ROLLBACK_SECRET[] = {
+#define EXPECTED_UNINITIALIZED_ROLLBACK_SECRET                              \
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,   \
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, \
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, \
+		0xff,
+__maybe_unused static const uint8_t _EXPECTED_UNINITIALIZED_ROLLBACK_SECRET[] = {
 	EXPECTED_UNINITIALIZED_ROLLBACK_SECRET
 };
 BUILD_ASSERT(sizeof(_EXPECTED_UNINITIALIZED_ROLLBACK_SECRET) ==
@@ -143,7 +138,8 @@ test_static int test_add_entropy(void)
 	/* Immediately after boot region 1 should not yet be initialized. */
 	rv = read_rollback(1, &rb_data);
 	TEST_EQ(rv, EC_SUCCESS, "%d");
-	TEST_EQ(check_equal(&rb_data, &expected_uninitialized), EC_SUCCESS, "%d");
+	TEST_EQ(check_equal(&rb_data, &expected_uninitialized), EC_SUCCESS,
+		"%d");
 
 	/*
 	 * Add entropy. The result should end up being written to the unused
@@ -186,7 +182,7 @@ test_static int test_add_entropy(void)
 	return rv;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	ccprintf("Running rollback_entropy test\n");
 	RUN_TEST(test_add_entropy);
diff --git a/test/rollback_entropy.tasklist b/test/rollback_entropy.tasklist
index 51734f058d..a1f1a94e2d 100644
--- a/test/rollback_entropy.tasklist
+++ b/test/rollback_entropy.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/rsa.c b/test/rsa.c
index 8e4eeef54c..2774e9edb4 100644
--- a/test/rsa.c
+++ b/test/rsa.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -21,9 +21,9 @@
 #include "rsa2048-F4.h"
 #endif
 
-static uint32_t rsa_workbuf[3 * RSANUMBYTES/4];
+static uint32_t rsa_workbuf[3 * RSANUMBYTES / 4];
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	int good;
 
@@ -45,7 +45,7 @@ void run_test(int argc, char **argv)
 	ccprintf("RSA verify FAILED (as expected)\n");
 
 	/* Test with a wrong signature */
-	good = rsa_verify(rsa_key, sig+1, hash, rsa_workbuf);
+	good = rsa_verify(rsa_key, sig + 1, hash, rsa_workbuf);
 	if (good) {
 		ccprintf("RSA verify OK (expected fail)\n");
 		test_fail();
diff --git a/test/rsa.tasklist b/test/rsa.tasklist
index f46a2eaa1d..bf2309064a 100644
--- a/test/rsa.tasklist
+++ b/test/rsa.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/rsa2048-3.h b/test/rsa2048-3.h
index d1b15c15a4..17b3c8989a 100644
--- a/test/rsa2048-3.h
+++ b/test/rsa2048-3.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -13,7 +13,7 @@
  * # dumpRSAPublicKey -pub key.pub | xxd -i
  */
 const uint8_t rsa_data[] = {
-	0x40, 0x00, 0x00, 0x00, 0x0f, 0x46, 0xe8, 0x2c,	0x11, 0x17, 0x38, 0xfd,
+	0x40, 0x00, 0x00, 0x00, 0x0f, 0x46, 0xe8, 0x2c, 0x11, 0x17, 0x38, 0xfd,
 	0xef, 0xa2, 0xb5, 0x2d, 0x6d, 0x76, 0xe1, 0x70, 0x7d, 0x67, 0xb1, 0x9a,
 	0x18, 0x78, 0x90, 0xe2, 0xce, 0xa6, 0x81, 0xa0, 0x13, 0x37, 0xf2, 0x71,
 	0xf0, 0x44, 0x96, 0xaf, 0x52, 0x53, 0xd4, 0x23, 0x51, 0x19, 0xe5, 0xb0,
@@ -65,18 +65,16 @@ BUILD_ASSERT(sizeof(*rsa_key) == sizeof(rsa_data));
 /* SHA-256 sum to verify:
  * # sha256sum README | sed -e 's/\(..\)/0x\1, /mg'
  */
-const uint8_t hash[] = {
-	0x6c, 0x5f, 0xef, 0x7f, 0x63, 0x1d, 0xb4, 0x35, 0x6c, 0xae, 0x8b, 0x2a,
-	0x4e, 0xde, 0xc5, 0xeb, 0x11, 0xba, 0x1f, 0x44, 0x40, 0xb6, 0x3a, 0x52,
-	0xf2, 0x70, 0xef, 0xee, 0x44, 0x4b, 0x57, 0x62
-};
+const uint8_t hash[] = { 0x6c, 0x5f, 0xef, 0x7f, 0x63, 0x1d, 0xb4, 0x35,
+			 0x6c, 0xae, 0x8b, 0x2a, 0x4e, 0xde, 0xc5, 0xeb,
+			 0x11, 0xba, 0x1f, 0x44, 0x40, 0xb6, 0x3a, 0x52,
+			 0xf2, 0x70, 0xef, 0xee, 0x44, 0x4b, 0x57, 0x62 };
 
 /* Incorrect hash to test the negative case */
-const uint8_t hash_wrong[] = {
-	0x61, 0x1b, 0xd2, 0x44, 0xc7, 0x18, 0xa7, 0x2d, 0x0f, 0x2d, 0x3d, 0x0f,
-	0xe3, 0xb3, 0xc5, 0xe4, 0x12, 0xc2, 0x7b, 0x1e, 0x05, 0x2c, 0x6f, 0xad,
-	0xc4, 0xac, 0x71, 0x55, 0xe8, 0x80, 0x5c, 0x38
-};
+const uint8_t hash_wrong[] = { 0x61, 0x1b, 0xd2, 0x44, 0xc7, 0x18, 0xa7, 0x2d,
+			       0x0f, 0x2d, 0x3d, 0x0f, 0xe3, 0xb3, 0xc5, 0xe4,
+			       0x12, 0xc2, 0x7b, 0x1e, 0x05, 0x2c, 0x6f, 0xad,
+			       0xc4, 0xac, 0x71, 0x55, 0xe8, 0x80, 0x5c, 0x38 };
 
 /* Generate signature using futility:
  * # futility create key.pem
diff --git a/test/rsa2048-F4.h b/test/rsa2048-F4.h
index afe66a198f..08b8f70155 100644
--- a/test/rsa2048-F4.h
+++ b/test/rsa2048-F4.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -65,18 +65,16 @@ BUILD_ASSERT(sizeof(*rsa_key) == sizeof(rsa_data));
 /* SHA-256 sum to verify:
  * # sha256sum README | sed -e 's/\(..\)/0x\1, /mg'
  */
-const uint8_t hash[] = {
-	0x6c, 0x5f, 0xef, 0x7f, 0x63, 0x1d, 0xb4, 0x35, 0x6c, 0xae, 0x8b, 0x2a,
-	0x4e, 0xde, 0xc5, 0xeb, 0x11, 0xba, 0x1f, 0x44, 0x40, 0xb6, 0x3a, 0x52,
-	0xf2, 0x70, 0xef, 0xee, 0x44, 0x4b, 0x57, 0x62
-};
+const uint8_t hash[] = { 0x6c, 0x5f, 0xef, 0x7f, 0x63, 0x1d, 0xb4, 0x35,
+			 0x6c, 0xae, 0x8b, 0x2a, 0x4e, 0xde, 0xc5, 0xeb,
+			 0x11, 0xba, 0x1f, 0x44, 0x40, 0xb6, 0x3a, 0x52,
+			 0xf2, 0x70, 0xef, 0xee, 0x44, 0x4b, 0x57, 0x62 };
 
 /* Incorrect hash to test the negative case */
-const uint8_t hash_wrong[] = {
-	0x61, 0x1b, 0xd2, 0x44, 0xc7, 0x18, 0xa7, 0x2d, 0x0f, 0x2d, 0x3d, 0x0f,
-	0xe3, 0xb3, 0xc5, 0xe4, 0x12, 0xc2, 0x7b, 0x1e, 0x05, 0x2c, 0x6f, 0xad,
-	0xc4, 0xac, 0x71, 0x55, 0xe8, 0x80, 0x5c, 0x38
-};
+const uint8_t hash_wrong[] = { 0x61, 0x1b, 0xd2, 0x44, 0xc7, 0x18, 0xa7, 0x2d,
+			       0x0f, 0x2d, 0x3d, 0x0f, 0xe3, 0xb3, 0xc5, 0xe4,
+			       0x12, 0xc2, 0x7b, 0x1e, 0x05, 0x2c, 0x6f, 0xad,
+			       0xc4, 0xac, 0x71, 0x55, 0xe8, 0x80, 0x5c, 0x38 };
 
 /* Generate signature using futility:
  * # futility create key.pem
diff --git a/test/rsa3072-3.h b/test/rsa3072-3.h
index c407a4ed2b..3ad93fafe8 100644
--- a/test/rsa3072-3.h
+++ b/test/rsa3072-3.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/test/rtc.c b/test/rtc.c
index 3e53f85611..7c38c4fa6d 100644
--- a/test/rtc.c
+++ b/test/rtc.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -16,15 +16,14 @@ static struct {
 	struct calendar_date time;
 	uint32_t sec;
 } test_case[] = {
-	{{8, 3, 1}, 1204329600},
-	{{17, 10, 1}, 1506816000},
+	{ { 8, 3, 1 }, 1204329600 },
+	{ { 17, 10, 1 }, 1506816000 },
 };
 
 static int calendar_time_comp(struct calendar_date time_1,
-			   struct calendar_date time_2)
+			      struct calendar_date time_2)
 {
-	return (time_1.year == time_2.year &&
-		time_1.month == time_2.month &&
+	return (time_1.year == time_2.year && time_1.month == time_2.month &&
 		time_1.day == time_2.day);
 }
 
@@ -96,7 +95,7 @@ static int test_time_conversion(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	RUN_TEST(test_time_conversion);
 
diff --git a/test/rtc.tasklist b/test/rtc.tasklist
index 80072bb620..329f9a3d28 100644
--- a/test/rtc.tasklist
+++ b/test/rtc.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/run_device_tests.py b/test/run_device_tests.py
index 337e4e6693..9b762fc1d6 100755
--- a/test/run_device_tests.py
+++ b/test/run_device_tests.py
@@ -1,6 +1,6 @@
 #!/usr/bin/env python3
 
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -49,118 +49,132 @@ import subprocess
 import sys
 import time
 from concurrent.futures.thread import ThreadPoolExecutor
+from dataclasses import dataclass, field
 from enum import Enum
 from pathlib import Path
-from typing import Optional, BinaryIO, List
+from typing import BinaryIO, Dict, List, Optional
 
 # pylint: disable=import-error
 import colorama  # type: ignore[import]
-from contextlib2 import ExitStack
 import fmap
+from contextlib2 import ExitStack
+
 # pylint: enable=import-error
 
 EC_DIR = Path(os.path.dirname(os.path.realpath(__file__))).parent
-JTRACE_FLASH_SCRIPT = os.path.join(EC_DIR, 'util/flash_jlink.py')
-SERVO_MICRO_FLASH_SCRIPT = os.path.join(EC_DIR, 'util/flash_ec')
+JTRACE_FLASH_SCRIPT = os.path.join(EC_DIR, "util/flash_jlink.py")
+SERVO_MICRO_FLASH_SCRIPT = os.path.join(EC_DIR, "util/flash_ec")
 
-ALL_TESTS_PASSED_REGEX = re.compile(r'Pass!\r\n')
-ALL_TESTS_FAILED_REGEX = re.compile(r'Fail! \(\d+ tests\)\r\n')
+ALL_TESTS_PASSED_REGEX = re.compile(r"Pass!\r\n")
+ALL_TESTS_FAILED_REGEX = re.compile(r"Fail! \(\d+ tests\)\r\n")
 
-SINGLE_CHECK_PASSED_REGEX = re.compile(r'Pass: .*')
-SINGLE_CHECK_FAILED_REGEX = re.compile(r'.*failed:.*')
+SINGLE_CHECK_PASSED_REGEX = re.compile(r"Pass: .*")
+SINGLE_CHECK_FAILED_REGEX = re.compile(r".*failed:.*")
 
-ASSERTION_FAILURE_REGEX = re.compile(r'ASSERTION FAILURE.*')
+ASSERTION_FAILURE_REGEX = re.compile(r"ASSERTION FAILURE.*")
 
 DATA_ACCESS_VIOLATION_8020000_REGEX = re.compile(
-    r'Data access violation, mfar = 8020000\r\n')
+    r"Data access violation, mfar = 8020000\r\n"
+)
 DATA_ACCESS_VIOLATION_8040000_REGEX = re.compile(
-    r'Data access violation, mfar = 8040000\r\n')
+    r"Data access violation, mfar = 8040000\r\n"
+)
 DATA_ACCESS_VIOLATION_80C0000_REGEX = re.compile(
-    r'Data access violation, mfar = 80c0000\r\n')
+    r"Data access violation, mfar = 80c0000\r\n"
+)
 DATA_ACCESS_VIOLATION_80E0000_REGEX = re.compile(
-    r'Data access violation, mfar = 80e0000\r\n')
+    r"Data access violation, mfar = 80e0000\r\n"
+)
 DATA_ACCESS_VIOLATION_20000000_REGEX = re.compile(
-    r'Data access violation, mfar = 20000000\r\n')
+    r"Data access violation, mfar = 20000000\r\n"
+)
 DATA_ACCESS_VIOLATION_24000000_REGEX = re.compile(
-    r'Data access violation, mfar = 24000000\r\n')
+    r"Data access violation, mfar = 24000000\r\n"
+)
 
-BLOONCHIPPER = 'bloonchipper'
-DARTMONKEY = 'dartmonkey'
+BLOONCHIPPER = "bloonchipper"
+DARTMONKEY = "dartmonkey"
 
-JTRACE = 'jtrace'
-SERVO_MICRO = 'servo_micro'
+JTRACE = "jtrace"
+SERVO_MICRO = "servo_micro"
 
-GCC = 'gcc'
-CLANG = 'clang'
+GCC = "gcc"
+CLANG = "clang"
 
-TEST_ASSETS_BUCKET = 'gs://chromiumos-test-assets-public/fpmcu/RO'
+TEST_ASSETS_BUCKET = "gs://chromiumos-test-assets-public/fpmcu/RO"
 DARTMONKEY_IMAGE_PATH = os.path.join(
-    TEST_ASSETS_BUCKET, 'dartmonkey_v2.0.2887-311310808.bin')
+    TEST_ASSETS_BUCKET, "dartmonkey_v2.0.2887-311310808.bin"
+)
 NOCTURNE_FP_IMAGE_PATH = os.path.join(
-    TEST_ASSETS_BUCKET, 'nocturne_fp_v2.2.64-58cf5974e.bin')
+    TEST_ASSETS_BUCKET, "nocturne_fp_v2.2.64-58cf5974e.bin"
+)
 NAMI_FP_IMAGE_PATH = os.path.join(
-    TEST_ASSETS_BUCKET, 'nami_fp_v2.2.144-7a08e07eb.bin')
+    TEST_ASSETS_BUCKET, "nami_fp_v2.2.144-7a08e07eb.bin"
+)
 BLOONCHIPPER_V4277_IMAGE_PATH = os.path.join(
-    TEST_ASSETS_BUCKET, 'bloonchipper_v2.0.4277-9f652bb3.bin')
+    TEST_ASSETS_BUCKET, "bloonchipper_v2.0.4277-9f652bb3.bin"
+)
 BLOONCHIPPER_V5938_IMAGE_PATH = os.path.join(
-    TEST_ASSETS_BUCKET, 'bloonchipper_v2.0.5938-197506c1.bin')
+    TEST_ASSETS_BUCKET, "bloonchipper_v2.0.5938-197506c1.bin"
+)
 
 
 class ImageType(Enum):
     """EC Image type to use for the test."""
+
     RO = 1
     RW = 2
 
 
+@dataclass
 class BoardConfig:
     """Board-specific configuration."""
 
-    def __init__(self, name, servo_uart_name, servo_power_enable,
-                 rollback_region0_regex, rollback_region1_regex, mpu_regex,
-                 variants):
-        self.name = name
-        self.servo_uart_name = servo_uart_name
-        self.servo_power_enable = servo_power_enable
-        self.rollback_region0_regex = rollback_region0_regex
-        self.rollback_region1_regex = rollback_region1_regex
-        self.mpu_regex = mpu_regex
-        self.variants = variants
+    name: str
+    servo_uart_name: str
+    servo_power_enable: str
+    rollback_region0_regex: object
+    rollback_region1_regex: object
+    mpu_regex: object
+    variants: Dict
 
 
+@dataclass
 class TestConfig:
     """Configuration for a given test."""
 
-    def __init__(self, test_name, image_to_use=ImageType.RW,
-                 finish_regexes=None, fail_regexes=None, toggle_power=False,
-                 test_args=None, num_flash_attempts=2, timeout_secs=10,
-                 enable_hw_write_protect=False, ro_image=None, build_board=None,
-                 config_name=None):
-        if test_args is None:
-            test_args = []
-        if finish_regexes is None:
-            finish_regexes = [ALL_TESTS_PASSED_REGEX, ALL_TESTS_FAILED_REGEX]
-        if fail_regexes is None:
-            fail_regexes = [SINGLE_CHECK_FAILED_REGEX, ALL_TESTS_FAILED_REGEX,
-                            ASSERTION_FAILURE_REGEX]
-        if config_name is None:
-            config_name = test_name
-
-        self.test_name = test_name
-        self.config_name = config_name
-        self.image_to_use = image_to_use
-        self.finish_regexes = finish_regexes
-        self.fail_regexes = fail_regexes
-        self.test_args = test_args
-        self.toggle_power = toggle_power
-        self.num_flash_attempts = num_flash_attempts
-        self.timeout_secs = timeout_secs
-        self.enable_hw_write_protect = enable_hw_write_protect
-        self.logs = []
-        self.passed = False
-        self.num_fails = 0
-        self.num_passes = 0
-        self.ro_image = ro_image
-        self.build_board = build_board
+    # pylint: disable=too-many-instance-attributes
+    test_name: str
+    image_to_use: ImageType = ImageType.RW
+    finish_regexes: List = None
+    fail_regexes: List = None
+    toggle_power: bool = False
+    test_args: List[str] = field(default_factory=list)
+    num_flash_attempts: int = 2
+    timeout_secs: int = 10
+    enable_hw_write_protect: bool = False
+    ro_image: str = None
+    build_board: str = None
+    config_name: str = None
+    logs: List = field(init=False, default_factory=list)
+    passed: bool = field(init=False, default=False)
+    num_passes: int = field(init=False, default=0)
+    num_fails: int = field(init=False, default=0)
+
+    def __post_init__(self):
+        if self.finish_regexes is None:
+            self.finish_regexes = [
+                ALL_TESTS_PASSED_REGEX,
+                ALL_TESTS_FAILED_REGEX,
+            ]
+        if self.fail_regexes is None:
+            self.fail_regexes = [
+                SINGLE_CHECK_FAILED_REGEX,
+                ALL_TESTS_FAILED_REGEX,
+                ASSERTION_FAILURE_REGEX,
+            ]
+        if self.config_name is None:
+            self.config_name = self.test_name
 
 
 # All possible tests.
@@ -169,6 +183,7 @@ class AllTests:
 
     @staticmethod
     def get(board_config: BoardConfig) -> List[TestConfig]:
+        """Return public and private test configs for the specified board."""
         public_tests = AllTests.get_public_tests(board_config)
         private_tests = AllTests.get_private_tests()
 
@@ -176,146 +191,192 @@ class AllTests:
 
     @staticmethod
     def get_public_tests(board_config: BoardConfig) -> List[TestConfig]:
+        """Return public test configs for the specified board."""
         tests = [
-            TestConfig(test_name='aes'),
-            TestConfig(test_name='cec'),
-            TestConfig(test_name='cortexm_fpu'),
-            TestConfig(test_name='crc'),
-            TestConfig(test_name='flash_physical', image_to_use=ImageType.RO,
-                       toggle_power=True),
-            TestConfig(test_name='flash_write_protect',
-                       image_to_use=ImageType.RO,
-                       toggle_power=True, enable_hw_write_protect=True),
-            TestConfig(test_name='fpsensor_hw'),
-            TestConfig(config_name='fpsensor_spi_ro', test_name='fpsensor',
-                       image_to_use=ImageType.RO, test_args=['spi']),
-            TestConfig(config_name='fpsensor_spi_rw', test_name='fpsensor',
-                       test_args=['spi']),
-            TestConfig(config_name='fpsensor_uart_ro', test_name='fpsensor',
-                       image_to_use=ImageType.RO, test_args=['uart']),
-            TestConfig(config_name='fpsensor_uart_rw', test_name='fpsensor',
-                       test_args=['uart']),
-            TestConfig(config_name='mpu_ro', test_name='mpu',
-                       image_to_use=ImageType.RO,
-                       finish_regexes=[board_config.mpu_regex]),
-            TestConfig(config_name='mpu_rw', test_name='mpu',
-                       finish_regexes=[board_config.mpu_regex]),
-            TestConfig(test_name='mutex'),
-            TestConfig(test_name='pingpong'),
-            TestConfig(test_name='printf'),
-            TestConfig(test_name='queue'),
-            TestConfig(config_name='rollback_region0', test_name='rollback',
-                       finish_regexes=[board_config.rollback_region0_regex],
-                       test_args=['region0']),
-            TestConfig(config_name='rollback_region1', test_name='rollback',
-                       finish_regexes=[board_config.rollback_region1_regex],
-                       test_args=['region1']),
-            TestConfig(test_name='rollback_entropy', image_to_use=ImageType.RO),
-            TestConfig(test_name='rtc'),
-            TestConfig(test_name='sha256'),
-            TestConfig(test_name='sha256_unrolled'),
-            TestConfig(test_name='static_if'),
-            TestConfig(config_name='system_is_locked_wp_on',
-                       test_name='system_is_locked', test_args=['wp_on'],
-                       toggle_power=True, enable_hw_write_protect=True),
-            TestConfig(config_name='system_is_locked_wp_off',
-                       test_name='system_is_locked', test_args=['wp_off'],
-                       toggle_power=True, enable_hw_write_protect=False),
-            TestConfig(test_name='timer_dos'),
-            TestConfig(test_name='utils', timeout_secs=20),
-            TestConfig(test_name='utils_str'),
+            TestConfig(test_name="aes"),
+            TestConfig(test_name="cec"),
+            TestConfig(test_name="cortexm_fpu"),
+            TestConfig(test_name="crc"),
+            TestConfig(
+                test_name="flash_physical",
+                image_to_use=ImageType.RO,
+                toggle_power=True,
+            ),
+            TestConfig(
+                test_name="flash_write_protect",
+                image_to_use=ImageType.RO,
+                toggle_power=True,
+                enable_hw_write_protect=True,
+            ),
+            TestConfig(test_name="fpsensor_hw"),
+            TestConfig(
+                config_name="fpsensor_spi_ro",
+                test_name="fpsensor",
+                image_to_use=ImageType.RO,
+                test_args=["spi"],
+            ),
+            TestConfig(
+                config_name="fpsensor_spi_rw",
+                test_name="fpsensor",
+                test_args=["spi"],
+            ),
+            TestConfig(
+                config_name="fpsensor_uart_ro",
+                test_name="fpsensor",
+                image_to_use=ImageType.RO,
+                test_args=["uart"],
+            ),
+            TestConfig(
+                config_name="fpsensor_uart_rw",
+                test_name="fpsensor",
+                test_args=["uart"],
+            ),
+            TestConfig(
+                config_name="mpu_ro",
+                test_name="mpu",
+                image_to_use=ImageType.RO,
+                finish_regexes=[board_config.mpu_regex],
+            ),
+            TestConfig(
+                config_name="mpu_rw",
+                test_name="mpu",
+                finish_regexes=[board_config.mpu_regex],
+            ),
+            TestConfig(test_name="mutex"),
+            TestConfig(test_name="pingpong"),
+            TestConfig(test_name="printf"),
+            TestConfig(test_name="queue"),
+            TestConfig(
+                config_name="rollback_region0",
+                test_name="rollback",
+                finish_regexes=[board_config.rollback_region0_regex],
+                test_args=["region0"],
+            ),
+            TestConfig(
+                config_name="rollback_region1",
+                test_name="rollback",
+                finish_regexes=[board_config.rollback_region1_regex],
+                test_args=["region1"],
+            ),
+            TestConfig(test_name="rollback_entropy", image_to_use=ImageType.RO),
+            TestConfig(test_name="rtc"),
+            TestConfig(test_name="sha256"),
+            TestConfig(test_name="sha256_unrolled"),
+            TestConfig(test_name="static_if"),
+            TestConfig(test_name="stdlib"),
+            TestConfig(
+                config_name="system_is_locked_wp_on",
+                test_name="system_is_locked",
+                test_args=["wp_on"],
+                toggle_power=True,
+                enable_hw_write_protect=True,
+            ),
+            TestConfig(
+                config_name="system_is_locked_wp_off",
+                test_name="system_is_locked",
+                test_args=["wp_off"],
+                toggle_power=True,
+                enable_hw_write_protect=False,
+            ),
+            TestConfig(test_name="timer_dos"),
+            TestConfig(test_name="utils", timeout_secs=20),
+            TestConfig(test_name="utils_str"),
         ]
 
         if board_config.name == BLOONCHIPPER:
-            tests.append(TestConfig(test_name='stm32f_rtc'))
+            tests.append(TestConfig(test_name="stm32f_rtc"))
 
         # Run panic data tests for all boards and RO versions.
         for variant_name, variant_info in board_config.variants.items():
             tests.append(
-                TestConfig(config_name='panic_data_' + variant_name,
-                           test_name='panic_data',
-                           fail_regexes=[SINGLE_CHECK_FAILED_REGEX,
-                                         ALL_TESTS_FAILED_REGEX],
-                           ro_image=variant_info.get('ro_image_path'),
-                           build_board=variant_info.get('build_board')))
+                TestConfig(
+                    config_name="panic_data_" + variant_name,
+                    test_name="panic_data",
+                    fail_regexes=[
+                        SINGLE_CHECK_FAILED_REGEX,
+                        ALL_TESTS_FAILED_REGEX,
+                    ],
+                    ro_image=variant_info.get("ro_image_path"),
+                    build_board=variant_info.get("build_board"),
+                )
+            )
 
         return tests
 
     @staticmethod
     def get_private_tests() -> List[TestConfig]:
-        # Return all private tests, if the folder exists
+        """Return private test configs for the specified board, if available."""
         tests = []
         try:
             current_dir = os.path.dirname(__file__)
-            private_dir = os.path.join(current_dir, os.pardir, 'private/test')
+            private_dir = os.path.join(current_dir, os.pardir, "private/test")
             have_private = os.path.isdir(private_dir)
             if not have_private:
                 return []
             sys.path.append(private_dir)
-            import private_tests  # pylint: disable=import-error
+            import private_tests  # pylint: disable=import-error,import-outside-toplevel
+
             for test_args in private_tests.tests:
                 tests.append(TestConfig(**test_args))
         # Catch all exceptions to avoid disruptions in public repo
-        except BaseException as e:
-            logging.debug('Failed to get list of private tests: %s', str(e))
-            logging.debug('Ignore error and continue.')
+        except BaseException as e:  # pylint: disable=broad-except
+            logging.debug("Failed to get list of private tests: %s", str(e))
+            logging.debug("Ignore error and continue.")
             return []
         return tests
 
 
 BLOONCHIPPER_CONFIG = BoardConfig(
     name=BLOONCHIPPER,
-    servo_uart_name='raw_fpmcu_console_uart_pty',
-    servo_power_enable='fpmcu_pp3300',
+    servo_uart_name="raw_fpmcu_console_uart_pty",
+    servo_power_enable="fpmcu_pp3300",
     rollback_region0_regex=DATA_ACCESS_VIOLATION_8020000_REGEX,
     rollback_region1_regex=DATA_ACCESS_VIOLATION_8040000_REGEX,
     mpu_regex=DATA_ACCESS_VIOLATION_20000000_REGEX,
     variants={
-        'bloonchipper_v2.0.4277': {
-            'ro_image_path': BLOONCHIPPER_V4277_IMAGE_PATH
+        "bloonchipper_v2.0.4277": {
+            "ro_image_path": BLOONCHIPPER_V4277_IMAGE_PATH
+        },
+        "bloonchipper_v2.0.5938": {
+            "ro_image_path": BLOONCHIPPER_V5938_IMAGE_PATH
         },
-        'bloonchipper_v2.0.5938': {
-            'ro_image_path': BLOONCHIPPER_V5938_IMAGE_PATH
-        }
-    }
+    },
 )
 
 DARTMONKEY_CONFIG = BoardConfig(
     name=DARTMONKEY,
-    servo_uart_name='raw_fpmcu_console_uart_pty',
-    servo_power_enable='fpmcu_pp3300',
+    servo_uart_name="raw_fpmcu_console_uart_pty",
+    servo_power_enable="fpmcu_pp3300",
     rollback_region0_regex=DATA_ACCESS_VIOLATION_80C0000_REGEX,
     rollback_region1_regex=DATA_ACCESS_VIOLATION_80E0000_REGEX,
     mpu_regex=DATA_ACCESS_VIOLATION_24000000_REGEX,
     # For dartmonkey board, run panic data test also on nocturne_fp and
     # nami_fp boards with appropriate RO image.
     variants={
-        'dartmonkey_v2.0.2887': {
-            'ro_image_path': DARTMONKEY_IMAGE_PATH
+        "dartmonkey_v2.0.2887": {"ro_image_path": DARTMONKEY_IMAGE_PATH},
+        "nocturne_fp_v2.2.64": {
+            "ro_image_path": NOCTURNE_FP_IMAGE_PATH,
+            "build_board": "nocturne_fp",
         },
-        'nocturne_fp_v2.2.64': {
-            'ro_image_path': NOCTURNE_FP_IMAGE_PATH,
-            'build_board': 'nocturne_fp'
+        "nami_fp_v2.2.144": {
+            "ro_image_path": NAMI_FP_IMAGE_PATH,
+            "build_board": "nami_fp",
         },
-        'nami_fp_v2.2.144': {
-            'ro_image_path': NAMI_FP_IMAGE_PATH,
-            'build_board': 'nami_fp'
-        }
-    }
+    },
 )
 
 BOARD_CONFIGS = {
-    'bloonchipper': BLOONCHIPPER_CONFIG,
-    'dartmonkey': DARTMONKEY_CONFIG,
+    "bloonchipper": BLOONCHIPPER_CONFIG,
+    "dartmonkey": DARTMONKEY_CONFIG,
 }
 
 
 def read_file_gsutil(path: str) -> bytes:
     """Get data from bucket, using gsutil tool"""
-    cmd = ['gsutil', 'cat', path]
+    cmd = ["gsutil", "cat", path]
 
-    logging.debug('Running command: "%s"', ' '.join(cmd))
-    gsutil = subprocess.run(cmd, stdout=subprocess.PIPE)  # pylint: disable=subprocess-run-check
+    logging.debug('Running command: "%s"', " ".join(cmd))
+    gsutil = subprocess.run(cmd, stdout=subprocess.PIPE, check=False)
     gsutil.check_returncode()
 
     return gsutil.stdout
@@ -323,9 +384,9 @@ def read_file_gsutil(path: str) -> bytes:
 
 def find_section_offset_size(section: str, image: bytes) -> (int, int):
     """Get offset and size of the section in image"""
-    areas = fmap.fmap_decode(image)['areas']
-    area = next(area for area in areas if area['name'] == section)
-    return area['offset'], area['size']
+    areas = fmap.fmap_decode(image)["areas"]
+    area = next(area for area in areas if area["name"] == section)
+    return area["offset"], area["size"]
 
 
 def read_section(src: bytes, section: str) -> bytes:
@@ -340,10 +401,10 @@ def write_section(data: bytes, image: bytearray, section: str):
     (section_start, section_size) = find_section_offset_size(section, image)
 
     if section_size < len(data):
-        raise ValueError(section + ' section size is not enough to store data')
+        raise ValueError(section + " section size is not enough to store data")
 
     section_end = section_start + section_size
-    filling = bytes([0xff for _ in range(section_size - len(data))])
+    filling = bytes([0xFF for _ in range(section_size - len(data))])
 
     image[section_start:section_end] = data + filling
 
@@ -354,12 +415,14 @@ def copy_section(src: bytes, dst: bytearray, section: str):
     (dst_start, dst_size) = find_section_offset_size(section, dst)
 
     if dst_size < src_size:
-        raise ValueError('Section ' + section + ' from source image has '
-                         'greater size than the section in destination image')
+        raise ValueError(
+            "Section " + section + " from source image has "
+            "greater size than the section in destination image"
+        )
 
     src_end = src_start + src_size
     dst_end = dst_start + dst_size
-    filling = bytes([0xff for _ in range(dst_size - src_size)])
+    filling = bytes([0xFF for _ in range(dst_size - src_size)])
 
     dst[dst_start:dst_end] = src[src_start:src_end] + filling
 
@@ -367,28 +430,28 @@ def copy_section(src: bytes, dst: bytearray, section: str):
 def replace_ro(image: bytearray, ro: bytes):
     """Replace RO in image with provided one"""
     # Backup RO public key since its private part was used to sign RW.
-    ro_pubkey = read_section(image, 'KEY_RO')
+    ro_pubkey = read_section(image, "KEY_RO")
 
     # Copy RO part of the firmware to the image. Please note that RO public key
     # is copied too since EC_RO area includes KEY_RO area.
-    copy_section(ro, image, 'EC_RO')
+    copy_section(ro, image, "EC_RO")
 
     # Restore RO public key.
-    write_section(ro_pubkey, image, 'KEY_RO')
+    write_section(ro_pubkey, image, "KEY_RO")
 
 
 def get_console(board_config: BoardConfig) -> Optional[str]:
     """Get the name of the console for a given board."""
     cmd = [
-        'dut-control',
+        "dut-control",
         board_config.servo_uart_name,
     ]
-    logging.debug('Running command: "%s"', ' '.join(cmd))
+    logging.debug('Running command: "%s"', " ".join(cmd))
 
     with subprocess.Popen(cmd, stdout=subprocess.PIPE) as proc:
         for line in io.TextIOWrapper(proc.stdout):  # type: ignore[arg-type]
             logging.debug(line)
-            pty = line.split(':')
+            pty = line.split(":")
             if len(pty) == 2 and pty[0] == board_config.servo_uart_name:
                 return pty[1].strip()
 
@@ -398,77 +461,90 @@ def get_console(board_config: BoardConfig) -> Optional[str]:
 def power(board_config: BoardConfig, on: bool) -> None:
     """Turn power to board on/off."""
     if on:
-        state = 'pp3300'
+        state = "pp3300"
     else:
-        state = 'off'
+        state = "off"
 
     cmd = [
-        'dut-control',
-        board_config.servo_power_enable + ':' + state,
+        "dut-control",
+        board_config.servo_power_enable + ":" + state,
     ]
-    logging.debug('Running command: "%s"', ' '.join(cmd))
-    subprocess.run(cmd).check_returncode()  # pylint: disable=subprocess-run-check
+    logging.debug('Running command: "%s"', " ".join(cmd))
+    subprocess.run(
+        cmd
+    ).check_returncode()  # pylint: disable=subprocess-run-check
 
 
 def hw_write_protect(enable: bool) -> None:
     """Enable/disable hardware write protect."""
     if enable:
-        state = 'force_on'
+        state = "force_on"
     else:
-        state = 'force_off'
+        state = "force_off"
 
     cmd = [
-        'dut-control',
-        'fw_wp_state:' + state,
-        ]
-    logging.debug('Running command: "%s"', ' '.join(cmd))
-    subprocess.run(cmd).check_returncode()  # pylint: disable=subprocess-run-check
+        "dut-control",
+        "fw_wp_state:" + state,
+    ]
+    logging.debug('Running command: "%s"', " ".join(cmd))
+    subprocess.run(
+        cmd
+    ).check_returncode()  # pylint: disable=subprocess-run-check
 
 
 def build(test_name: str, board_name: str, compiler: str) -> None:
     """Build specified test for specified board."""
-    cmd = ['make']
+    cmd = ["make"]
 
     if compiler == CLANG:
-        cmd = cmd + ['CC=arm-none-eabi-clang']
+        cmd = cmd + ["CC=arm-none-eabi-clang"]
 
     cmd = cmd + [
-        'BOARD=' + board_name,
-        'test-' + test_name,
-        '-j',
+        "BOARD=" + board_name,
+        "test-" + test_name,
+        "-j",
     ]
 
-    logging.debug('Running command: "%s"', ' '.join(cmd))
-    subprocess.run(cmd).check_returncode()  # pylint: disable=subprocess-run-check
+    logging.debug('Running command: "%s"', " ".join(cmd))
+    subprocess.run(
+        cmd
+    ).check_returncode()  # pylint: disable=subprocess-run-check
 
 
-def flash(image_path: str, board: str, flasher: str, remote_ip: str,
-          remote_port: int) -> bool:
+def flash(
+    image_path: str, board: str, flasher: str, remote_ip: str, remote_port: int
+) -> bool:
     """Flash specified test to specified board."""
-    logging.info('Flashing test')
+    logging.info("Flashing test")
 
     cmd = []
     if flasher == JTRACE:
         cmd.append(JTRACE_FLASH_SCRIPT)
         if remote_ip:
-            cmd.extend(['--remote', remote_ip + ':' + str(remote_port)])
+            cmd.extend(["--remote", remote_ip + ":" + str(remote_port)])
     elif flasher == SERVO_MICRO:
         cmd.append(SERVO_MICRO_FLASH_SCRIPT)
     else:
         logging.error('Unknown flasher: "%s"', flasher)
         return False
-    cmd.extend([
-        '--board', board,
-        '--image', image_path,
-    ])
-    logging.debug('Running command: "%s"', ' '.join(cmd))
-    completed_process = subprocess.run(cmd)  # pylint: disable=subprocess-run-check
+    cmd.extend(
+        [
+            "--board",
+            board,
+            "--image",
+            image_path,
+        ]
+    )
+    logging.debug('Running command: "%s"', " ".join(cmd))
+    completed_process = subprocess.run(
+        cmd
+    )  # pylint: disable=subprocess-run-check
     return completed_process.returncode == 0
 
 
 def patch_image(test: TestConfig, image_path: str):
     """Replace RO part of the firmware with provided one."""
-    with open(image_path, 'rb+') as f:
+    with open(image_path, "rb+") as f:
         image = bytearray(f.read())
         ro = read_file_gsutil(test.ro_image)
         replace_ro(image, ro)
@@ -477,8 +553,9 @@ def patch_image(test: TestConfig, image_path: str):
         f.truncate()
 
 
-def readline(executor: ThreadPoolExecutor, f: BinaryIO, timeout_secs: int) -> \
-             Optional[bytes]:
+def readline(
+    executor: ThreadPoolExecutor, f: BinaryIO, timeout_secs: int
+) -> Optional[bytes]:
     """Read a line with timeout."""
     a = executor.submit(f.readline)
     try:
@@ -487,8 +564,9 @@ def readline(executor: ThreadPoolExecutor, f: BinaryIO, timeout_secs: int) -> \
         return None
 
 
-def readlines_until_timeout(executor, f: BinaryIO, timeout_secs: int) -> \
-                            List[bytes]:
+def readlines_until_timeout(
+    executor, f: BinaryIO, timeout_secs: int
+) -> List[bytes]:
     """Continuously read lines for timeout_secs."""
     lines: List[bytes] = []
     while True:
@@ -499,6 +577,7 @@ def readlines_until_timeout(executor, f: BinaryIO, timeout_secs: int) -> \
 
 
 def process_console_output_line(line: bytes, test: TestConfig):
+    """Parse console output line and update test pass/fail counters."""
     try:
         line_str = line.decode()
 
@@ -518,19 +597,20 @@ def process_console_output_line(line: bytes, test: TestConfig):
         return None
 
 
-def run_test(test: TestConfig, console: io.FileIO,
-             executor: ThreadPoolExecutor) -> bool:
+def run_test(
+    test: TestConfig, console: io.FileIO, executor: ThreadPoolExecutor
+) -> bool:
     """Run specified test."""
     start = time.time()
 
     # Wait for boot to finish
     time.sleep(1)
-    console.write('\n'.encode())
+    console.write("\n".encode())
     if test.image_to_use == ImageType.RO:
-        console.write('reboot ro\n'.encode())
+        console.write("reboot ro\n".encode())
         time.sleep(1)
 
-    test_cmd = 'runtest ' + ' '.join(test.test_args) + '\n'
+    test_cmd = "runtest " + " ".join(test.test_args) + "\n"
     console.write(test_cmd.encode())
 
     while True:
@@ -539,7 +619,7 @@ def run_test(test: TestConfig, console: io.FileIO,
         if not line:
             now = time.time()
             if now - start > test.timeout_secs:
-                logging.debug('Test timed out')
+                logging.debug("Test timed out")
                 return False
             continue
 
@@ -568,15 +648,18 @@ def run_test(test: TestConfig, console: io.FileIO,
 
 def get_test_list(config: BoardConfig, test_args) -> List[TestConfig]:
     """Get a list of tests to run."""
-    if test_args == 'all':
+    if test_args == "all":
         return AllTests.get(config)
 
     test_list = []
     for t in test_args:
-        logging.debug('test: %s', t)
+        logging.debug("test: %s", t)
         test_regex = re.compile(t)
-        tests = [test for test in AllTests.get(config)
-                 if test_regex.fullmatch(test.config_name)]
+        tests = [
+            test
+            for test in AllTests.get(config)
+            if test_regex.fullmatch(test.config_name)
+        ]
         if not tests:
             logging.error('Unable to find test config for "%s"', t)
             sys.exit(1)
@@ -585,9 +668,81 @@ def get_test_list(config: BoardConfig, test_args) -> List[TestConfig]:
     return test_list
 
 
+def flash_and_run_test(
+    test: TestConfig,
+    board_config: BoardConfig,
+    args: argparse.Namespace,
+    executor,
+) -> bool:
+    """Run a single test using the test and board configuration specified"""
+    build_board = args.board
+    # If test provides this information, build image for board specified
+    # by test.
+    if test.build_board is not None:
+        build_board = test.build_board
+
+    # build test binary
+    build(test.test_name, build_board, args.compiler)
+
+    image_path = os.path.join(
+        EC_DIR, "build", build_board, test.test_name, test.test_name + ".bin"
+    )
+
+    if test.ro_image is not None:
+        try:
+            patch_image(test, image_path)
+        except Exception as exception:  # pylint: disable=broad-except
+            logging.warning(
+                "An exception occurred while patching " "image: %s", exception
+            )
+            return False
+
+    # flash test binary
+    # TODO(b/158327221): First attempt to flash fails after
+    #  flash_write_protect test is run; works after second attempt.
+    flash_succeeded = False
+    for i in range(0, test.num_flash_attempts):
+        logging.debug("Flash attempt %d", i + 1)
+        if flash(
+            image_path, args.board, args.flasher, args.remote, args.jlink_port
+        ):
+            flash_succeeded = True
+            break
+        time.sleep(1)
+
+    if not flash_succeeded:
+        logging.debug(
+            "Flashing failed after max attempts: %d", test.num_flash_attempts
+        )
+        return False
+
+    if test.toggle_power:
+        power(board_config, on=False)
+        time.sleep(1)
+        power(board_config, on=True)
+
+    hw_write_protect(test.enable_hw_write_protect)
+
+    # run the test
+    logging.info('Running test: "%s"', test.config_name)
+
+    with ExitStack() as stack:
+        if args.remote and args.console_port:
+            s = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
+            s.connect((args.remote, args.console_port))
+            console = stack.enter_context(s.makefile(mode="rwb", buffering=0))
+        else:
+            console = stack.enter_context(
+                open(get_console(board_config), "wb+", buffering=0)
+            )
+
+        return run_test(test, console, executor=executor)
+
+
 def parse_remote_arg(remote: str) -> str:
+    """Convert the 'remote' input argument to IP address, if available."""
     if not remote:
-        return ''
+        return ""
 
     try:
         ip = socket.gethostbyname(remote)
@@ -597,165 +752,127 @@ def parse_remote_arg(remote: str) -> str:
         sys.exit(1)
 
 
+def validate_args_combination(args: argparse.Namespace):
+    """Check that the current combination of arguments is supported.
+
+    Not all combinations of command line arguments are valid or currently
+    supported. If tests can't be executed, print and error message and exit.
+    """
+    if args.jlink_port and not args.flasher == JTRACE:
+        logging.error("jlink_port specified, but flasher is not set to J-Link.")
+        sys.exit(1)
+
+    if args.remote and not (args.jlink_port or args.console_port):
+        logging.error(
+            "jlink_port or console_port must be specified when using "
+            "the remote option."
+        )
+        sys.exit(1)
+
+    if (args.jlink_port or args.console_port) and not args.remote:
+        logging.error(
+            "The remote option must be specified when using the "
+            "jlink_port or console_port options."
+        )
+        sys.exit(1)
+
+    if args.remote and args.flasher == SERVO_MICRO:
+        logging.error(
+            "The remote option is not supported when flashing with servo "
+            "micro. Use J-Link instead or flash with a local servo micro."
+        )
+        sys.exit(1)
+
+    if args.board not in BOARD_CONFIGS:
+        logging.error('Unable to find a config for board: "%s"', args.board)
+        sys.exit(1)
+
+
 def main():
+    """Run unit tests on device and displays the results."""
     parser = argparse.ArgumentParser()
 
-    default_board = 'bloonchipper'
+    default_board = "bloonchipper"
     parser.add_argument(
-        '--board', '-b',
-        help='Board (default: ' + default_board + ')',
-        default=default_board)
+        "--board",
+        "-b",
+        help="Board (default: " + default_board + ")",
+        default=default_board,
+    )
 
-    default_tests = 'all'
+    default_tests = "all"
     parser.add_argument(
-        '--tests', '-t',
-        nargs='+',
-        help='Tests (default: ' + default_tests + ')',
-        default=default_tests)
+        "--tests",
+        "-t",
+        nargs="+",
+        help="Tests (default: " + default_tests + ")",
+        default=default_tests,
+    )
 
-    log_level_choices = ['DEBUG', 'INFO', 'WARNING', 'ERROR', 'CRITICAL']
+    log_level_choices = ["DEBUG", "INFO", "WARNING", "ERROR", "CRITICAL"]
     parser.add_argument(
-        '--log_level', '-l',
-        choices=log_level_choices,
-        default='DEBUG'
+        "--log_level", "-l", choices=log_level_choices, default="DEBUG"
     )
 
     flasher_choices = [SERVO_MICRO, JTRACE]
     parser.add_argument(
-        '--flasher', '-f',
-        choices=flasher_choices,
-        default=JTRACE
+        "--flasher", "-f", choices=flasher_choices, default=JTRACE
     )
 
     compiler_options = [GCC, CLANG]
-    parser.add_argument('--compiler', '-c',
-                        choices=compiler_options,
-                        default=GCC)
+    parser.add_argument(
+        "--compiler", "-c", choices=compiler_options, default=GCC
+    )
 
     # This might be expanded to serve as a "remote" for flash_ec also, so
     # we will leave it generic.
     parser.add_argument(
-        '--remote', '-n',
-        help='The remote host connected to one or both of: J-Link and Servo.',
+        "--remote",
+        "-n",
+        help="The remote host connected to one or both of: J-Link and Servo.",
+        type=parse_remote_arg,
     )
 
-    parser.add_argument('--jlink_port', '-j',
-                        type=int,
-                        help='The port to use when connecting to JLink.')
-    parser.add_argument('--console_port', '-p',
-                        type=int,
-                        help='The port connected to the FPMCU console.')
+    parser.add_argument(
+        "--jlink_port",
+        "-j",
+        type=int,
+        help="The port to use when connecting to JLink.",
+    )
+    parser.add_argument(
+        "--console_port",
+        "-p",
+        type=int,
+        help="The port connected to the FPMCU console.",
+    )
 
     args = parser.parse_args()
     logging.basicConfig(level=args.log_level)
-
-    if args.jlink_port and not args.flasher == JTRACE:
-        logging.error('jlink_port specified, but flasher is not set to J-Link.')
-        sys.exit(1)
-
-    if args.remote and not (args.jlink_port or args.console_port):
-        logging.error('jlink_port or console_port must be specified when using '
-                      'the remote option.')
-        sys.exit(1)
-
-    if (args.jlink_port or args.console_port) and not args.remote:
-        logging.error('The remote option must be specified when using the '
-                      'jlink_port or console_port options.')
-        sys.exit(1)
-
-    if args.board not in BOARD_CONFIGS:
-        logging.error('Unable to find a config for board: "%s"', args.board)
-        sys.exit(1)
+    validate_args_combination(args)
 
     board_config = BOARD_CONFIGS[args.board]
-
-    remote_ip = parse_remote_arg(args.remote)
-
-    e = ThreadPoolExecutor(max_workers=1)
-
     test_list = get_test_list(board_config, args.tests)
-    logging.debug(
-        'Running tests: %s', [
-            test.config_name for test in test_list])
-
-    for test in test_list:
-        build_board = args.board
-        # If test provides this information, build image for board specified
-        # by test.
-        if test.build_board is not None:
-            build_board = test.build_board
-
-        # build test binary
-        build(test.test_name, build_board, args.compiler)
-
-        image_path = os.path.join(EC_DIR, 'build', build_board, test.test_name,
-                                  test.test_name + '.bin')
-
-        if test.ro_image is not None:
-            try:
-                patch_image(test, image_path)
-            except Exception as exception:
-                logging.warning('An exception occurred while patching '
-                                'image: %s', exception)
-                test.passed = False
-                continue
-
-        # flash test binary
-        # TODO(b/158327221): First attempt to flash fails after
-        #  flash_write_protect test is run; works after second attempt.
-        flash_succeeded = False
-        for i in range(0, test.num_flash_attempts):
-            logging.debug('Flash attempt %d', i + 1)
-            if flash(image_path, args.board, args.flasher, remote_ip,
-                     args.jlink_port):
-                flash_succeeded = True
-                break
-            time.sleep(1)
-
-        if not flash_succeeded:
-            logging.debug('Flashing failed after max attempts: %d',
-                          test.num_flash_attempts)
-            test.passed = False
-            continue
-
-        if test.toggle_power:
-            power(board_config, on=False)
-            time.sleep(1)
-            power(board_config, on=True)
-
-        hw_write_protect(test.enable_hw_write_protect)
-
-        # run the test
-        logging.info('Running test: "%s"', test.config_name)
-
-        with ExitStack() as stack:
-            if remote_ip and args.console_port:
-                s = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
-                s.connect((remote_ip, args.console_port))
-                console = stack.enter_context(
-                    s.makefile(mode='rwb', buffering=0))
+    logging.debug("Running tests: %s", [test.config_name for test in test_list])
+
+    with ThreadPoolExecutor(max_workers=1) as e:
+        for test in test_list:
+            test.passed = flash_and_run_test(test, board_config, args, e)
+
+        colorama.init()
+        exit_code = 0
+        for test in test_list:
+            # print results
+            print('Test "' + test.config_name + '": ', end="")
+            if test.passed:
+                print(colorama.Fore.GREEN + "PASSED")
             else:
-                console = stack.enter_context(
-                    open(get_console(board_config), 'wb+', buffering=0))
-
-            test.passed = run_test(test, console, executor=e)
-
-    colorama.init()
-    exit_code = 0
-    for test in test_list:
-        # print results
-        print('Test "' + test.config_name + '": ', end='')
-        if test.passed:
-            print(colorama.Fore.GREEN + 'PASSED')
-        else:
-            print(colorama.Fore.RED + 'FAILED')
-            exit_code = 1
+                print(colorama.Fore.RED + "FAILED")
+                exit_code = 1
 
-        print(colorama.Style.RESET_ALL)
+            print(colorama.Style.RESET_ALL)
 
-    e.shutdown(wait=False)
     sys.exit(exit_code)
 
 
-if __name__ == '__main__':
+if __name__ == "__main__":
     sys.exit(main())
diff --git a/test/sbs_charging_v2.c b/test/sbs_charging_v2.c
index 2f9ddee57c..b30f377c67 100644
--- a/test/sbs_charging_v2.c
+++ b/test/sbs_charging_v2.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -279,7 +279,7 @@ static int test_charge_state(void)
 	TEST_ASSERT(!(flags & CHARGE_FLAG_FORCE_IDLE));
 	charge_control(CHARGE_CONTROL_IDLE);
 	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_IDLE);
+	TEST_ASSERT(state == PWR_STATE_FORCED_IDLE);
 	flags = charge_get_flags();
 	TEST_ASSERT(flags & CHARGE_FLAG_EXTERNAL_POWER);
 	TEST_ASSERT(flags & CHARGE_FLAG_FORCE_IDLE);
@@ -293,7 +293,7 @@ static int test_charge_state(void)
 	sb_write(SB_CURRENT, 1000);
 	charge_control(CHARGE_CONTROL_DISCHARGE);
 	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_IDLE);
+	TEST_ASSERT(state == PWR_STATE_FORCED_IDLE);
 	TEST_ASSERT(is_force_discharge);
 	charge_control(CHARGE_CONTROL_NORMAL);
 	state = wait_charging_state();
@@ -386,7 +386,7 @@ static int test_deep_charge_battery(void)
 	state_v2 = charge_get_state_v2();
 	TEST_ASSERT(state_v2 == ST_IDLE);
 
-        /* recovery from a low voltage. */
+	/* recovery from a low voltage. */
 	sb_write(SB_VOLTAGE, (bat_info->voltage_normal));
 	wait_charging_state();
 	state_v2 = charge_get_state_v2();
@@ -490,7 +490,7 @@ static int test_external_funcs(void)
 	/* Now let's force idle on and off */
 	UART_INJECT("chg idle on\n");
 	state = wait_charging_state();
-	TEST_ASSERT(state == PWR_STATE_IDLE);
+	TEST_ASSERT(state == PWR_STATE_FORCED_IDLE);
 	flags = charge_get_flags();
 	TEST_ASSERT(flags & CHARGE_FLAG_EXTERNAL_POWER);
 	TEST_ASSERT(flags & CHARGE_FLAG_FORCE_IDLE);
@@ -533,9 +533,8 @@ static int test_hc_charge_state(void)
 	/* Get the state */
 	memset(&resp, 0, sizeof(resp));
 	params.cmd = CHARGE_STATE_CMD_GET_STATE;
-	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0,
-				    &params, sizeof(params),
-				    &resp, sizeof(resp));
+	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, &params,
+				    sizeof(params), &resp, sizeof(resp));
 	TEST_ASSERT(rv == EC_RES_SUCCESS);
 	TEST_ASSERT(resp.get_state.ac);
 	TEST_ASSERT(resp.get_state.chg_voltage);
@@ -545,14 +544,13 @@ static int test_hc_charge_state(void)
 
 	/* Check all the params */
 	for (i = 0; i < CS_NUM_BASE_PARAMS; i++) {
-
 		/* Read it */
 		memset(&resp, 0, sizeof(resp));
 		params.cmd = CHARGE_STATE_CMD_GET_PARAM;
 		params.get_param.param = i;
-		rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0,
-					    &params, sizeof(params),
-					    &resp, sizeof(resp));
+		rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, &params,
+					    sizeof(params), &resp,
+					    sizeof(resp));
 		TEST_ASSERT(rv == EC_RES_SUCCESS);
 		if (i != CS_PARAM_LIMIT_POWER)
 			TEST_ASSERT(resp.get_param.value);
@@ -565,7 +563,7 @@ static int test_hc_charge_state(void)
 		case CS_PARAM_CHG_VOLTAGE:
 		case CS_PARAM_CHG_CURRENT:
 		case CS_PARAM_CHG_INPUT_CURRENT:
-			tmp -= 128;		/* Should be valid delta */
+			tmp -= 128; /* Should be valid delta */
 			break;
 		case CS_PARAM_CHG_STATUS:
 		case CS_PARAM_LIMIT_POWER:
@@ -578,9 +576,9 @@ static int test_hc_charge_state(void)
 		params.cmd = CHARGE_STATE_CMD_SET_PARAM;
 		params.set_param.param = i;
 		params.set_param.value = tmp;
-		rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0,
-					    &params, sizeof(params),
-					    &resp, sizeof(resp));
+		rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, &params,
+					    sizeof(params), &resp,
+					    sizeof(resp));
 		if (i == CS_PARAM_CHG_STATUS || i == CS_PARAM_LIMIT_POWER)
 			TEST_ASSERT(rv == EC_RES_ACCESS_DENIED);
 		else
@@ -593,9 +591,9 @@ static int test_hc_charge_state(void)
 		memset(&resp, 0, sizeof(resp));
 		params.cmd = CHARGE_STATE_CMD_GET_PARAM;
 		params.get_param.param = i;
-		rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0,
-					    &params, sizeof(params),
-					    &resp, sizeof(resp));
+		rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, &params,
+					    sizeof(params), &resp,
+					    sizeof(resp));
 		TEST_ASSERT(rv == EC_RES_SUCCESS);
 		TEST_ASSERT(resp.get_param.value == tmp);
 	}
@@ -605,17 +603,15 @@ static int test_hc_charge_state(void)
 	memset(&resp, 0, sizeof(resp));
 	params.cmd = CHARGE_STATE_CMD_GET_PARAM;
 	params.get_param.param = CS_PARAM_CUSTOM_PROFILE_MIN;
-	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0,
-				    &params, sizeof(params),
-				    &resp, sizeof(resp));
+	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, &params,
+				    sizeof(params), &resp, sizeof(resp));
 	TEST_ASSERT(rv == EC_RES_SUCCESS);
 	TEST_ASSERT(resp.get_param.value == meh);
 	params.cmd = CHARGE_STATE_CMD_SET_PARAM;
 	params.set_param.param = CS_PARAM_CUSTOM_PROFILE_MIN;
 	params.set_param.value = 0xc0def00d;
-	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0,
-				    &params, sizeof(params),
-				    &resp, sizeof(resp));
+	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, &params,
+				    sizeof(params), &resp, sizeof(resp));
 	TEST_ASSERT(rv == EC_RES_SUCCESS);
 	/* Allow the change to take effect */
 	state = wait_charging_state();
@@ -624,23 +620,20 @@ static int test_hc_charge_state(void)
 	/* param out of range */
 	params.cmd = CHARGE_STATE_CMD_GET_PARAM;
 	params.get_param.param = CS_NUM_BASE_PARAMS;
-	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0,
-				    &params, sizeof(params),
-				    &resp, sizeof(resp));
+	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, &params,
+				    sizeof(params), &resp, sizeof(resp));
 	TEST_ASSERT(rv == EC_RES_INVALID_PARAM);
 	params.cmd = CHARGE_STATE_CMD_SET_PARAM;
 	params.set_param.param = CS_NUM_BASE_PARAMS;
-	params.set_param.value = 0x1000;	/* random value */
-	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0,
-				    &params, sizeof(params),
-				    &resp, sizeof(resp));
+	params.set_param.value = 0x1000; /* random value */
+	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, &params,
+				    sizeof(params), &resp, sizeof(resp));
 	TEST_ASSERT(rv == EC_RES_INVALID_PARAM);
 
 	/* command out of range */
 	params.cmd = CHARGE_STATE_NUM_CMDS;
-	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0,
-				    &params, sizeof(params),
-				    &resp, sizeof(resp));
+	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, &params,
+				    sizeof(params), &resp, sizeof(resp));
 	TEST_ASSERT(rv == EC_RES_INVALID_PARAM);
 
 	/*
@@ -665,40 +658,38 @@ static int test_hc_current_limit(void)
 
 	/* See what current the charger is delivering */
 	cs_params.cmd = CHARGE_STATE_CMD_GET_STATE;
-	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0,
-				    &cs_params, sizeof(cs_params),
-				    &cs_resp, sizeof(cs_resp));
+	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, &cs_params,
+				    sizeof(cs_params), &cs_resp,
+				    sizeof(cs_resp));
 	TEST_ASSERT(rv == EC_RES_SUCCESS);
 	norm_current = cs_resp.get_state.chg_current;
 
 	/* Lower it a bit */
 	lower_current = norm_current - 256;
 	cl_params.limit = lower_current;
-	rv = test_send_host_command(EC_CMD_CHARGE_CURRENT_LIMIT, 0,
-				    &cl_params, sizeof(cl_params),
-				    0, 0);
+	rv = test_send_host_command(EC_CMD_CHARGE_CURRENT_LIMIT, 0, &cl_params,
+				    sizeof(cl_params), 0, 0);
 	TEST_ASSERT(rv == EC_RES_SUCCESS);
 	wait_charging_state();
 
 	/* See that it's changed */
-	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0,
-				    &cs_params, sizeof(cs_params),
-				    &cs_resp, sizeof(cs_resp));
+	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, &cs_params,
+				    sizeof(cs_params), &cs_resp,
+				    sizeof(cs_resp));
 	TEST_ASSERT(rv == EC_RES_SUCCESS);
 	TEST_ASSERT(lower_current == cs_resp.get_state.chg_current);
 
 	/* Remove the limit */
 	cl_params.limit = -1U;
-	rv = test_send_host_command(EC_CMD_CHARGE_CURRENT_LIMIT, 0,
-				    &cl_params, sizeof(cl_params),
-				    0, 0);
+	rv = test_send_host_command(EC_CMD_CHARGE_CURRENT_LIMIT, 0, &cl_params,
+				    sizeof(cl_params), 0, 0);
 	TEST_ASSERT(rv == EC_RES_SUCCESS);
 	wait_charging_state();
 
 	/* See that it's back */
-	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0,
-				    &cs_params, sizeof(cs_params),
-				    &cs_resp, sizeof(cs_resp));
+	rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, &cs_params,
+				    sizeof(cs_params), &cs_resp,
+				    sizeof(cs_resp));
 	TEST_ASSERT(rv == EC_RES_SUCCESS);
 	TEST_ASSERT(norm_current == cs_resp.get_state.chg_current);
 
@@ -734,7 +725,8 @@ static int test_low_battery_hostevents(void)
 	TEST_ASSERT(!is_shutdown);
 
 	/* (Shout) a little bit louder now */
-	sb_write(SB_RELATIVE_STATE_OF_CHARGE, BATTERY_LEVEL_CRITICAL + 1);
+	sb_write(SB_RELATIVE_STATE_OF_CHARGE,
+		 CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE + 1);
 	state = wait_charging_state();
 	TEST_ASSERT(state == PWR_STATE_DISCHARGE);
 	TEST_ASSERT(ev_is_set(EC_HOST_EVENT_BATTERY_LOW));
@@ -743,7 +735,8 @@ static int test_low_battery_hostevents(void)
 	TEST_ASSERT(!is_shutdown);
 
 	/* (Shout) a little bit louder now */
-	sb_write(SB_RELATIVE_STATE_OF_CHARGE, BATTERY_LEVEL_CRITICAL - 1);
+	sb_write(SB_RELATIVE_STATE_OF_CHARGE,
+		 CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE - 1);
 	state = wait_charging_state();
 	TEST_ASSERT(state == PWR_STATE_DISCHARGE);
 	TEST_ASSERT(ev_is_set(EC_HOST_EVENT_BATTERY_LOW));
@@ -789,13 +782,13 @@ static int test_battery_sustainer(void)
 	p.mode = CHARGE_CONTROL_NORMAL;
 	p.sustain_soc.lower = 79;
 	p.sustain_soc.upper = 80;
-	rv = test_send_host_command(EC_CMD_CHARGE_CONTROL, 2,
-				    &p, sizeof(p), NULL, 0);
+	rv = test_send_host_command(EC_CMD_CHARGE_CONTROL, 2, &p, sizeof(p),
+				    NULL, 0);
 	TEST_ASSERT(rv == EC_RES_SUCCESS);
 
 	p.cmd = EC_CHARGE_CONTROL_CMD_GET;
-	rv = test_send_host_command(EC_CMD_CHARGE_CONTROL, 2,
-				    &p, sizeof(p), &r, sizeof(r));
+	rv = test_send_host_command(EC_CMD_CHARGE_CONTROL, 2, &p, sizeof(p), &r,
+				    sizeof(r));
 	TEST_ASSERT(rv == EC_RES_SUCCESS);
 	TEST_ASSERT(r.sustain_soc.lower == 79);
 	TEST_ASSERT(r.sustain_soc.upper == 80);
@@ -854,8 +847,8 @@ static int test_battery_sustainer(void)
 	p.mode = CHARGE_CONTROL_NORMAL;
 	p.sustain_soc.lower = 79;
 	p.sustain_soc.upper = 80;
-	rv = test_send_host_command(EC_CMD_CHARGE_CONTROL, 2,
-				    &p, sizeof(p), NULL, 0);
+	rv = test_send_host_command(EC_CMD_CHARGE_CONTROL, 2, &p, sizeof(p),
+				    NULL, 0);
 	TEST_ASSERT(rv == EC_RES_SUCCESS);
 	wait_charging_state();
 	TEST_ASSERT(get_chg_ctrl_mode() == CHARGE_CONTROL_DISCHARGE);
@@ -876,8 +869,8 @@ static int test_battery_sustainer(void)
 	p.mode = CHARGE_CONTROL_NORMAL;
 	p.sustain_soc.lower = 79;
 	p.sustain_soc.upper = 80;
-	rv = test_send_host_command(EC_CMD_CHARGE_CONTROL, 2,
-				    &p, sizeof(p), NULL, 0);
+	rv = test_send_host_command(EC_CMD_CHARGE_CONTROL, 2, &p, sizeof(p),
+				    NULL, 0);
 	TEST_ASSERT(rv == EC_RES_SUCCESS);
 	wait_charging_state();
 	TEST_ASSERT(get_chg_ctrl_mode() == CHARGE_CONTROL_DISCHARGE);
@@ -898,8 +891,8 @@ static int test_battery_sustainer_discharge_idle(void)
 	p.mode = CHARGE_CONTROL_NORMAL;
 	p.sustain_soc.lower = 80;
 	p.sustain_soc.upper = 80;
-	rv = test_send_host_command(EC_CMD_CHARGE_CONTROL, 2,
-				    &p, sizeof(p), NULL, 0);
+	rv = test_send_host_command(EC_CMD_CHARGE_CONTROL, 2, &p, sizeof(p),
+				    NULL, 0);
 	TEST_ASSERT(rv == EC_RES_SUCCESS);
 
 	/* Check mode transition as the SoC changes. */
@@ -939,8 +932,8 @@ static int test_battery_sustainer_discharge_idle(void)
 	p.mode = CHARGE_CONTROL_NORMAL;
 	p.sustain_soc.lower = -1;
 	p.sustain_soc.upper = -1;
-	rv = test_send_host_command(EC_CMD_CHARGE_CONTROL, 2,
-				    &p, sizeof(p), NULL, 0);
+	rv = test_send_host_command(EC_CMD_CHARGE_CONTROL, 2, &p, sizeof(p),
+				    NULL, 0);
 	TEST_ASSERT(rv == EC_RES_SUCCESS);
 
 	/* This time, mode will stay in NORMAL even when upper < SoC. */
@@ -951,7 +944,7 @@ static int test_battery_sustainer_discharge_idle(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	RUN_TEST(test_charge_state);
 	RUN_TEST(test_low_battery);
diff --git a/test/sbs_charging_v2.tasklist b/test/sbs_charging_v2.tasklist
index 3895762986..202541188f 100644
--- a/test/sbs_charging_v2.tasklist
+++ b/test/sbs_charging_v2.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/scratchpad.c b/test/scratchpad.c
index 1bea76f7a1..c023f1dc72 100644
--- a/test/scratchpad.c
+++ b/test/scratchpad.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,7 +27,7 @@ test_static int test_scratchpad(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	RUN_TEST(test_scratchpad);
 	test_print_result();
diff --git a/test/scratchpad.tasklist b/test/scratchpad.tasklist
index 51734f058d..a1f1a94e2d 100644
--- a/test/scratchpad.tasklist
+++ b/test/scratchpad.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/sha256.c b/test/sha256.c
index 105ae8fec5..4b5326d189 100644
--- a/test/sha256.c
+++ b/test/sha256.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -12,23 +12,20 @@
 #include "util.h"
 
 /* Short Msg from NIST FIPS 180-4 (Len = 8) */
-static const uint8_t sha256_8_input[] = {
-	0xd3
-};
+static const uint8_t sha256_8_input[] = { 0xd3 };
 static const uint8_t sha256_8_output[SHA256_DIGEST_SIZE] = {
-	0x28, 0x96, 0x9c, 0xdf, 0xa7, 0x4a, 0x12, 0xc8, 0x2f, 0x3b, 0xad, 0x96,
-	0x0b, 0x0b, 0x00, 0x0a, 0xca, 0x2a, 0xc3, 0x29, 0xde, 0xea, 0x5c, 0x23,
-	0x28, 0xeb, 0xc6, 0xf2, 0xba, 0x98, 0x02, 0xc1
+	0x28, 0x96, 0x9c, 0xdf, 0xa7, 0x4a, 0x12, 0xc8, 0x2f, 0x3b, 0xad,
+	0x96, 0x0b, 0x0b, 0x00, 0x0a, 0xca, 0x2a, 0xc3, 0x29, 0xde, 0xea,
+	0x5c, 0x23, 0x28, 0xeb, 0xc6, 0xf2, 0xba, 0x98, 0x02, 0xc1
 };
 
 /* Short Msg from NIST FIPS 180-4 (Len = 72) */
-static const uint8_t sha256_72_input[] = {
-	0x33, 0x34, 0xc5, 0x80, 0x75, 0xd3, 0xf4, 0x13, 0x9e
-};
+static const uint8_t sha256_72_input[] = { 0x33, 0x34, 0xc5, 0x80, 0x75,
+					   0xd3, 0xf4, 0x13, 0x9e };
 static const uint8_t sha256_72_output[SHA256_DIGEST_SIZE] = {
-	0x07, 0x8d, 0xa3, 0xd7, 0x7e, 0xd4, 0x3b, 0xd3, 0x03, 0x7a, 0x43, 0x3f,
-	0xd0, 0x34, 0x18, 0x55, 0x02, 0x37, 0x93, 0xf9, 0xaf, 0xd0, 0x8b, 0x4b,
-	0x08, 0xea, 0x1e, 0x55, 0x97, 0xce, 0xef, 0x20
+	0x07, 0x8d, 0xa3, 0xd7, 0x7e, 0xd4, 0x3b, 0xd3, 0x03, 0x7a, 0x43,
+	0x3f, 0xd0, 0x34, 0x18, 0x55, 0x02, 0x37, 0x93, 0xf9, 0xaf, 0xd0,
+	0x8b, 0x4b, 0x08, 0xea, 0x1e, 0x55, 0x97, 0xce, 0xef, 0x20
 };
 
 /* Long Msg from NIST FIPS 180-4 (Len = 2888) */
@@ -66,9 +63,9 @@ static const uint8_t sha256_2888_input[] = {
 	0x93
 };
 static const uint8_t sha256_2888_output[SHA256_DIGEST_SIZE] = {
-	0x5f, 0x4e, 0x16, 0xa7, 0x2d, 0x6c, 0x98, 0x57, 0xda, 0x0b, 0xa0, 0x09,
-	0xcc, 0xac, 0xd4, 0xf2, 0x6d, 0x7f, 0x6b, 0xf6, 0xc1, 0xb7, 0x8a, 0x2e,
-	0xd3, 0x5e, 0x68, 0xfc, 0xb1, 0x5b, 0x8e, 0x40
+	0x5f, 0x4e, 0x16, 0xa7, 0x2d, 0x6c, 0x98, 0x57, 0xda, 0x0b, 0xa0,
+	0x09, 0xcc, 0xac, 0xd4, 0xf2, 0x6d, 0x7f, 0x6b, 0xf6, 0xc1, 0xb7,
+	0x8a, 0x2e, 0xd3, 0x5e, 0x68, 0xfc, 0xb1, 0x5b, 0x8e, 0x40
 };
 
 /* HMAC short key (40 bytes) from NIST FIPS 198-1 (Count = 34) */
@@ -86,15 +83,15 @@ static const uint8_t hmac_short_msg[] = {
 	0x03, 0x2b, 0x31, 0xd2, 0x41, 0xad, 0x33, 0x71
 };
 static const uint8_t hmac_short_key[] = {
-	0x9d, 0xa0, 0xc1, 0x14, 0x68, 0x2f, 0x82, 0xc1, 0xd1, 0xe9, 0xb5, 0x44,
-	0x30, 0x58, 0x0b, 0x9c, 0x56, 0x94, 0x89, 0xca, 0x16, 0xb9, 0x2e, 0xe1,
-	0x04, 0x98, 0xd5, 0x5d, 0x7c, 0xad, 0x5d, 0xb5, 0xe6, 0x52, 0x06, 0x34,
-	0x39, 0x31, 0x1e, 0x04
+	0x9d, 0xa0, 0xc1, 0x14, 0x68, 0x2f, 0x82, 0xc1, 0xd1, 0xe9,
+	0xb5, 0x44, 0x30, 0x58, 0x0b, 0x9c, 0x56, 0x94, 0x89, 0xca,
+	0x16, 0xb9, 0x2e, 0xe1, 0x04, 0x98, 0xd5, 0x5d, 0x7c, 0xad,
+	0x5d, 0xb5, 0xe6, 0x52, 0x06, 0x34, 0x39, 0x31, 0x1e, 0x04
 };
 static const uint8_t hmac_short_output[] = {
-	0xcd, 0xea, 0xcf, 0xce, 0xbf, 0x46, 0xcc, 0x9d, 0x7e, 0x4d, 0x41, 0x75,
-	0xe5, 0xd8, 0xd2, 0x67, 0xc2, 0x3a, 0x64, 0xcd, 0xe8, 0x3e, 0x86, 0x7e,
-	0x50, 0x01, 0xec, 0xf2, 0x6f, 0xbd, 0x30, 0xd2
+	0xcd, 0xea, 0xcf, 0xce, 0xbf, 0x46, 0xcc, 0x9d, 0x7e, 0x4d, 0x41,
+	0x75, 0xe5, 0xd8, 0xd2, 0x67, 0xc2, 0x3a, 0x64, 0xcd, 0xe8, 0x3e,
+	0x86, 0x7e, 0x50, 0x01, 0xec, 0xf2, 0x6f, 0xbd, 0x30, 0xd2
 };
 
 /* HMAC medium key (64 bytes) from NIST FIPS 198-1 (Count = 120) */
@@ -112,17 +109,17 @@ static const uint8_t hmac_medium_msg[] = {
 	0x85, 0x46, 0x80, 0x4f, 0x9c, 0xf2, 0xec, 0xfe
 };
 static const uint8_t hmac_medium_key[] = {
-	0x99, 0x28, 0x68, 0x50, 0x4d, 0x25, 0x64, 0xc4, 0xfb, 0x47, 0xbc, 0xbd,
-	0x4a, 0xe4, 0x82, 0xd8, 0xfb, 0x0e, 0x8e, 0x56, 0xd7, 0xb8, 0x18, 0x64,
-	0xe6, 0x19, 0x86, 0xa0, 0xe2, 0x56, 0x82, 0xda, 0xeb, 0x5b, 0x50, 0x17,
-	0x7c, 0x09, 0x5e, 0xdc, 0x9e, 0x97, 0x1d, 0xa9, 0x5c, 0x32, 0x10, 0xc3,
-	0x76, 0xe7, 0x23, 0x36, 0x5a, 0xc3, 0x3d, 0x1b, 0x4f, 0x39, 0x18, 0x17,
-	0xf4, 0xc3, 0x51, 0x24
+	0x99, 0x28, 0x68, 0x50, 0x4d, 0x25, 0x64, 0xc4, 0xfb, 0x47, 0xbc,
+	0xbd, 0x4a, 0xe4, 0x82, 0xd8, 0xfb, 0x0e, 0x8e, 0x56, 0xd7, 0xb8,
+	0x18, 0x64, 0xe6, 0x19, 0x86, 0xa0, 0xe2, 0x56, 0x82, 0xda, 0xeb,
+	0x5b, 0x50, 0x17, 0x7c, 0x09, 0x5e, 0xdc, 0x9e, 0x97, 0x1d, 0xa9,
+	0x5c, 0x32, 0x10, 0xc3, 0x76, 0xe7, 0x23, 0x36, 0x5a, 0xc3, 0x3d,
+	0x1b, 0x4f, 0x39, 0x18, 0x17, 0xf4, 0xc3, 0x51, 0x24
 };
 static const uint8_t hmac_medium_output[] = {
-	0x2f, 0x83, 0x21, 0xf4, 0x16, 0xb9, 0xbb, 0x24, 0x9f, 0x11, 0x3b, 0x13,
-	0xfc, 0x12, 0xd7, 0x0e, 0x16, 0x68, 0xdc, 0x33, 0x28, 0x39, 0xc1, 0x0d,
-	0xaa, 0x57, 0x17, 0x89, 0x6c, 0xb7, 0x0d, 0xdf
+	0x2f, 0x83, 0x21, 0xf4, 0x16, 0xb9, 0xbb, 0x24, 0x9f, 0x11, 0x3b,
+	0x13, 0xfc, 0x12, 0xd7, 0x0e, 0x16, 0x68, 0xdc, 0x33, 0x28, 0x39,
+	0xc1, 0x0d, 0xaa, 0x57, 0x17, 0x89, 0x6c, 0xb7, 0x0d, 0xdf
 };
 
 static int test_sha256(const uint8_t *input, int input_len,
@@ -156,9 +153,8 @@ static int test_sha256(const uint8_t *input, int input_len,
 	return 1;
 }
 
-static int test_hmac(const uint8_t *key, int key_len,
-		     const uint8_t *input, int input_len,
-		     const uint8_t *output)
+static int test_hmac(const uint8_t *key, int key_len, const uint8_t *input,
+		     int input_len, const uint8_t *output)
 {
 	uint8_t tmp[SHA256_DIGEST_SIZE];
 
@@ -172,7 +168,7 @@ static int test_hmac(const uint8_t *key, int key_len,
 	return 1;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	ccprintf("Testing short message (8 bytes)\n");
 	if (!test_sha256(sha256_8_input, sizeof(sha256_8_input),
@@ -196,9 +192,8 @@ void run_test(int argc, char **argv)
 	}
 
 	ccprintf("HMAC: Testing short key\n");
-	if (!test_hmac(hmac_short_key, sizeof(hmac_short_key),
-		       hmac_short_msg, sizeof(hmac_short_msg),
-		       hmac_short_output)) {
+	if (!test_hmac(hmac_short_key, sizeof(hmac_short_key), hmac_short_msg,
+		       sizeof(hmac_short_msg), hmac_short_output)) {
 		test_fail();
 		return;
 	}
diff --git a/test/sha256.tasklist b/test/sha256.tasklist
index 80072bb620..329f9a3d28 100644
--- a/test/sha256.tasklist
+++ b/test/sha256.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/shmalloc.c b/test/shmalloc.c
index a596d173e7..899876ab43 100644
--- a/test/shmalloc.c
+++ b/test/shmalloc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -36,14 +36,14 @@ static uint32_t next = 127;
 static uint32_t myrand(void)
 {
 	next = next * 1103515245 + 12345;
-	return ((uint32_t)(next/65536) % 32768);
+	return ((uint32_t)(next / 65536) % 32768);
 }
 
 /* Keep track of buffers allocated by the test function. */
 static struct {
 	void *buf;
 	size_t buffer_size;
-} allocations[12];  /* Up to 12 buffers could be allocated concurrently. */
+} allocations[12]; /* Up to 12 buffers could be allocated concurrently. */
 
 /*
  * Verify that allocated and free buffers do not overlap, and that our and
@@ -77,8 +77,7 @@ static int check_for_overlaps(void)
 		 * multiple times to keep things simple.
 		 */
 		allocated_count = 0;
-		for (allocced_buf = allocced_buf_chain;
-		     allocced_buf;
+		for (allocced_buf = allocced_buf_chain; allocced_buf;
 		     allocced_buf = allocced_buf->next_buffer) {
 			int allocated_size, allocation_size;
 
@@ -112,13 +111,13 @@ static int check_for_overlaps(void)
 			}
 		}
 		if (!allocation_match) {
-			ccprintf("missing match %pP!\n", allocations[i].buf);
+			ccprintf("missing match %p!\n", allocations[i].buf);
 			return 0;
 		}
 	}
 	if (allocations_count != allocated_count) {
-		ccprintf("count mismatch (%d != %d)!\n",
-			 allocations_count, allocated_count);
+		ccprintf("count mismatch (%d != %d)!\n", allocations_count,
+			 allocated_count);
 		return 0;
 	}
 	return 1;
@@ -137,7 +136,7 @@ static int shmem_is_ok(int line)
 	struct shm_buffer *pbuf = free_buf_chain;
 
 	if (pbuf && pbuf->prev_buffer) {
-		ccprintf("Bad free buffer list start %pP\n", pbuf);
+		ccprintf("Bad free buffer list start %p\n", pbuf);
 		goto bailout;
 	}
 
@@ -146,20 +145,20 @@ static int shmem_is_ok(int line)
 
 		running_size += pbuf->buffer_size;
 		if (count++ > 100)
-			goto bailout;  /* Is there a loop? */
+			goto bailout; /* Is there a loop? */
 
 		top = (struct shm_buffer *)((uintptr_t)pbuf +
-					     pbuf->buffer_size);
+					    pbuf->buffer_size);
 		if (pbuf->next_buffer) {
 			if (top >= pbuf->next_buffer) {
 				ccprintf("%s:%d"
-					 " - inconsistent buffer size at %pP\n",
+					 " - inconsistent buffer size at %p\n",
 					 __func__, __LINE__, pbuf);
 				goto bailout;
 			}
 			if (pbuf->next_buffer->prev_buffer != pbuf) {
 				ccprintf("%s:%d"
-					 " - inconsistent next buffer at %pP\n",
+					 " - inconsistent next buffer at %p\n",
 					 __func__, __LINE__, pbuf);
 				goto bailout;
 			}
@@ -193,7 +192,7 @@ static int shmem_is_ok(int line)
 
 	return 1;
 
- bailout:
+bailout:
 	ccprintf("Line %d, counter %d. The list has been corrupted, "
 		 "total size %d, running size %d\n",
 		 line, counter, total_size, running_size);
@@ -207,7 +206,7 @@ static int shmem_is_ok(int line)
  */
 static uint32_t test_map;
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	int index;
 	const int shmem_size = shared_mem_size();
@@ -229,8 +228,7 @@ void run_test(int argc, char **argv)
 			if (test_map & ~ALL_PATHS_MASK) {
 				ccprintf("Unexpected mask bits set: %x"
 					 ", counter %d\n",
-					 test_map & ~ALL_PATHS_MASK,
-					 counter);
+					 test_map & ~ALL_PATHS_MASK, counter);
 				test_fail();
 				return;
 			}
@@ -261,7 +259,7 @@ void run_test(int argc, char **argv)
 			 */
 			if (shared_mem_acquire(alloc_size, &shptr) ==
 			    EC_SUCCESS) {
-				allocations[index].buf = (void *) shptr;
+				allocations[index].buf = (void *)shptr;
 				allocations[index].buffer_size = alloc_size;
 
 				/*
@@ -269,8 +267,8 @@ void run_test(int argc, char **argv)
 				 * modified.
 				 */
 				while (alloc_size--)
-					shptr[alloc_size] =
-					shptr[alloc_size] ^ 0xff;
+					shptr[alloc_size] = shptr[alloc_size] ^
+							    0xff;
 
 				if (!shmem_is_ok(__LINE__)) {
 					test_fail();
@@ -294,8 +292,8 @@ void run_test(int argc, char **argv)
 			}
 		}
 
-	ccprintf("Did not pass all paths, map %x != %x\n",
-		 test_map, ALL_PATHS_MASK);
+	ccprintf("Did not pass all paths, map %x != %x\n", test_map,
+		 ALL_PATHS_MASK);
 	test_fail();
 }
 
diff --git a/test/shmalloc.tasklist b/test/shmalloc.tasklist
index a8ef01a489..1413e373b1 100644
--- a/test/shmalloc.tasklist
+++ b/test/shmalloc.tasklist
@@ -1,5 +1,5 @@
 /*
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/static_if.c b/test/static_if.c
index f70f7d30c3..9e8b9db465 100644
--- a/test/static_if.c
+++ b/test/static_if.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -39,7 +39,7 @@ static int test_static_if_unused_no_fail(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/static_if.tasklist b/test/static_if.tasklist
index 5ffe662d01..2d4595f76a 100644
--- a/test/static_if.tasklist
+++ b/test/static_if.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/static_if_error.c b/test/static_if_error.c
index 65882b3bbd..99765ece99 100644
--- a/test/static_if_error.c
+++ b/test/static_if_error.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,7 +24,7 @@
 /* This is intended to cause a compilation error. */
 TEST_MACRO(CONFIG_FOO) __maybe_unused int foo;
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/static_if_error.sh b/test/static_if_error.sh
index efc7cd3e1e..ef17780f4c 100644
--- a/test/static_if_error.sh
+++ b/test/static_if_error.sh
@@ -1,5 +1,5 @@
 #!/bin/bash -e
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/test/static_if_error.tasklist b/test/static_if_error.tasklist
index 5ffe662d01..2d4595f76a 100644
--- a/test/static_if_error.tasklist
+++ b/test/static_if_error.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/stdlib.c b/test/stdlib.c
new file mode 100644
index 0000000000..efff64829d
--- /dev/null
+++ b/test/stdlib.c
@@ -0,0 +1,520 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Test standard library functions.
+ */
+
+#include "common.h"
+#include "console.h"
+#include "system.h"
+#include "printf.h"
+#include "shared_mem.h"
+#include "test_util.h"
+#include "timer.h"
+#include "util.h"
+
+#ifdef USE_BUILTIN_STDLIB
+static const bool use_builtin_stdlib = true;
+#else
+static const bool use_builtin_stdlib = false;
+#endif
+
+static int test_isalpha(void)
+{
+	TEST_ASSERT(isalpha('a'));
+	TEST_ASSERT(isalpha('z'));
+	TEST_ASSERT(isalpha('A'));
+	TEST_ASSERT(isalpha('Z'));
+	TEST_ASSERT(!isalpha('0'));
+	TEST_ASSERT(!isalpha('~'));
+	TEST_ASSERT(!isalpha(' '));
+	TEST_ASSERT(!isalpha('\0'));
+	TEST_ASSERT(!isalpha('\n'));
+	return EC_SUCCESS;
+}
+
+static int test_isprint(void)
+{
+	TEST_ASSERT(isprint('a'));
+	TEST_ASSERT(isprint('z'));
+	TEST_ASSERT(isprint('A'));
+	TEST_ASSERT(isprint('Z'));
+	TEST_ASSERT(isprint('0'));
+	TEST_ASSERT(isprint('~'));
+	TEST_ASSERT(isprint(' '));
+	TEST_ASSERT(!isprint('\0'));
+	TEST_ASSERT(!isprint('\n'));
+	return EC_SUCCESS;
+}
+
+static int test_strstr(void)
+{
+	const char s1[] = "abcde";
+
+	TEST_ASSERT(strstr(s1, "ab") == s1);
+	if (use_builtin_stdlib) {
+		/*
+		 * TODO(http://b/243192369): This is incorrect and should be
+		 * fixed.
+		 */
+		TEST_ASSERT(strstr(s1, "") == NULL);
+	} else {
+		/*
+		 * From the man page: If needle is the empty string, the return
+		 * value is always haystack itself.
+		 */
+		TEST_ASSERT(strstr(s1, "") == s1);
+	}
+	TEST_ASSERT(strstr("", "ab") == NULL);
+	TEST_ASSERT(strstr("", "x") == NULL);
+	TEST_ASSERT(strstr(s1, "de") == &s1[3]);
+	TEST_ASSERT(strstr(s1, "def") == NULL);
+
+	return EC_SUCCESS;
+}
+
+static int test_strtoull(void)
+{
+	char *e;
+
+	TEST_ASSERT(strtoull("10", &e, 0) == 10);
+	TEST_ASSERT(e && (*e == '\0'));
+	TEST_ASSERT(strtoull("010", &e, 0) == 8);
+	TEST_ASSERT(e && (*e == '\0'));
+	TEST_ASSERT(strtoull("+010", &e, 0) == 8);
+	TEST_ASSERT(e && (*e == '\0'));
+
+	if (use_builtin_stdlib) {
+		/*
+		 * TODO(http://b/243192369): This is incorrect and should be
+		 * fixed.
+		 */
+		TEST_ASSERT(strtoull("-010", &e, 0) == 0);
+		TEST_ASSERT(e && (*e == '-'));
+	} else {
+		/*
+		 * From the man page: The strtoull() function returns either
+		 * the result of the conversion or, if there was a leading
+		 * minus sign, the negation of the result of the conversion
+		 * represented as an unsigned value, unless the original
+		 * (nonnegated) value would overflow
+		 */
+		TEST_ASSERT(strtoull("-010", &e, 0) == 0xFFFFFFFFFFFFFFF8);
+	}
+
+	TEST_ASSERT(strtoull("0x1f z", &e, 0) == 31);
+	TEST_ASSERT(e && (*e == ' '));
+	TEST_ASSERT(strtoull("0X1f z", &e, 0) == 31);
+	TEST_ASSERT(e && (*e == ' '));
+	TEST_ASSERT(strtoull("10a", &e, 16) == 266);
+	TEST_ASSERT(e && (*e == '\0'));
+	TEST_ASSERT(strtoull("0x02C", &e, 16) == 44);
+	TEST_ASSERT(e && (*e == '\0'));
+	TEST_ASSERT(strtoull("+0x02C", &e, 16) == 44);
+	TEST_ASSERT(e && (*e == '\0'));
+
+	if (use_builtin_stdlib) {
+		/*
+		 * TODO(http://b/243192369): This is incorrect and should be
+		 * fixed.
+		 */
+		TEST_ASSERT(strtoull("-0x02C", &e, 16) == 0);
+		TEST_ASSERT(e && (*e == '-'));
+	} else {
+		TEST_ASSERT(strtoull("-0x02C", &e, 16) == 0xFFFFFFFFFFFFFFD4);
+	}
+
+	TEST_ASSERT(strtoull("0x02C", &e, 0) == 44);
+	TEST_ASSERT(e && (*e == '\0'));
+	TEST_ASSERT(strtoull("+0x02C", &e, 0) == 44);
+	TEST_ASSERT(e && (*e == '\0'));
+
+	if (use_builtin_stdlib) {
+		/*
+		 * TODO(http://b/243192369): This is incorrect and should be
+		 * fixed.
+		 */
+		TEST_ASSERT(strtoull("-0x02C", &e, 0) == 0);
+		TEST_ASSERT(e && (*e == '-'));
+	} else {
+		TEST_ASSERT(strtoull("-0x02C", &e, 0) == 0xFFFFFFFFFFFFFFD4);
+	}
+
+	TEST_ASSERT(strtoull("0X02C", &e, 16) == 44);
+	TEST_ASSERT(e && (*e == '\0'));
+	TEST_ASSERT(strtoull("+0X02C", &e, 16) == 44);
+	TEST_ASSERT(e && (*e == '\0'));
+
+	if (use_builtin_stdlib) {
+		/*
+		 * TODO(http://b/243192369): This is incorrect and should be
+		 * fixed.
+		 */
+		TEST_ASSERT(strtoull("-0X02C", &e, 16) == 0);
+		TEST_ASSERT(e && (*e == '-'));
+	} else {
+		TEST_ASSERT(strtoull("-0X02C", &e, 16) == 0xFFFFFFFFFFFFFFD4);
+	}
+
+	TEST_ASSERT(strtoull("0X02C", &e, 0) == 44);
+	TEST_ASSERT(e && (*e == '\0'));
+	TEST_ASSERT(strtoull("+0X02C", &e, 0) == 44);
+	TEST_ASSERT(e && (*e == '\0'));
+
+	if (use_builtin_stdlib) {
+		/*
+		 * TODO(http://b/243192369): This is incorrect and should be
+		 * fixed.
+		 */
+		TEST_ASSERT(strtoull("-0X02C", &e, 0) == 0);
+		TEST_ASSERT(e && (*e == '-'));
+	} else {
+		TEST_ASSERT(strtoull("-0X02C", &e, 0) == 0xFFFFFFFFFFFFFFD4);
+	}
+
+	if (use_builtin_stdlib) {
+		/*
+		 * TODO(http://b/243192369): This is incorrect and should be
+		 * fixed.
+		 */
+		TEST_ASSERT(strtoull("   -12", &e, 0) == 0);
+		TEST_ASSERT(e && (*e == '-'));
+	} else {
+		TEST_ASSERT(strtoull("   -12", &e, 0) == 0xFFFFFFFFFFFFFFF4);
+	}
+
+	TEST_ASSERT(strtoull("!", &e, 0) == 0);
+	TEST_ASSERT(e && (*e == '!'));
+
+	TEST_ASSERT(strtoull("+!", &e, 0) == 0);
+	if (use_builtin_stdlib) {
+		/*
+		 * TODO(http://b/243192369): This is incorrect and should be
+		 * fixed.
+		 */
+		TEST_ASSERT(e && (*e == '!'));
+	} else {
+		TEST_ASSERT(e && (*e == '+'));
+	}
+
+	TEST_ASSERT(strtoull("+0!", &e, 0) == 0);
+	TEST_ASSERT(e && (*e == '!'));
+
+	TEST_ASSERT(strtoull("+0x!", &e, 0) == 0);
+	if (use_builtin_stdlib) {
+		TEST_ASSERT(e && (*e == '!'));
+	} else {
+		if (IS_ENABLED(EMU_BUILD))
+			TEST_ASSERT(e && (*e == 'x'));
+		else
+			TEST_ASSERT(e && (*e == '+'));
+	}
+
+	TEST_ASSERT(strtoull("+0X!", &e, 0) == 0);
+	if (use_builtin_stdlib) {
+		TEST_ASSERT(e && (*e == '!'));
+	} else {
+		if (IS_ENABLED(EMU_BUILD))
+			TEST_ASSERT(e && (*e == 'X'));
+		else
+			TEST_ASSERT(e && (*e == '+'));
+	}
+
+	return EC_SUCCESS;
+}
+
+static int test_strncpy(void)
+{
+	char dest[10];
+
+	strncpy(dest, "test", 10);
+	TEST_ASSERT_ARRAY_EQ("test", dest, 5);
+	strncpy(dest, "12345", 6);
+	TEST_ASSERT_ARRAY_EQ("12345", dest, 6);
+	/*
+	 * gcc complains:
+	 * error: ‘__builtin_strncpy’ output truncated copying 10 bytes from a
+	 * string of length 12 [-Werror=stringop-truncation]
+	 */
+#pragma GCC diagnostic push
+#if defined(__GNUC__) && __GNUC__ >= 8
+#pragma GCC diagnostic ignored "-Wstringop-truncation"
+#endif
+	strncpy(dest, "testtesttest", 10);
+#pragma GCC diagnostic pop
+	TEST_ASSERT_ARRAY_EQ("testtestte", dest, 10);
+
+	return EC_SUCCESS;
+}
+
+static int test_strncmp(void)
+{
+	TEST_ASSERT(strncmp("123", "123", 8) == 0);
+	TEST_ASSERT(strncmp("789", "456", 8) > 0);
+	TEST_ASSERT(strncmp("abc", "abd", 4) < 0);
+	TEST_ASSERT(strncmp("abc", "abd", 2) == 0);
+	return EC_SUCCESS;
+}
+
+static int test_strlen(void)
+{
+	TEST_ASSERT(strlen("this is a string") == 16);
+	return EC_SUCCESS;
+}
+
+static int test_strnlen(void)
+{
+	TEST_ASSERT(strnlen("this is a string", 17) == 16);
+	TEST_ASSERT(strnlen("this is a string", 16) == 16);
+	TEST_ASSERT(strnlen("this is a string", 5) == 5);
+
+	return EC_SUCCESS;
+}
+
+static int test_strcasecmp(void)
+{
+	TEST_ASSERT(strcasecmp("test string", "TEST strIng") == 0);
+	TEST_ASSERT(strcasecmp("test123!@#", "TesT123!@#") == 0);
+	TEST_ASSERT(strcasecmp("lower", "UPPER") != 0);
+	return EC_SUCCESS;
+}
+
+static int test_strncasecmp(void)
+{
+	TEST_ASSERT(strncasecmp("test string", "TEST str", 4) == 0);
+	TEST_ASSERT(strncasecmp("test string", "TEST str", 8) == 0);
+	TEST_ASSERT(strncasecmp("test123!@#", "TesT321!@#", 5) != 0);
+	TEST_ASSERT(strncasecmp("test123!@#", "TesT321!@#", 4) == 0);
+	TEST_ASSERT(strncasecmp("1test123!@#", "1TesT321!@#", 5) == 0);
+	TEST_ASSERT(strncasecmp("1test123", "teststr", 0) == 0);
+	return EC_SUCCESS;
+}
+
+static int test_atoi(void)
+{
+	TEST_ASSERT(atoi("  901") == 901);
+	TEST_ASSERT(atoi("-12c") == -12);
+	TEST_ASSERT(atoi("   0  ") == 0);
+	TEST_ASSERT(atoi("\t111") == 111);
+	return EC_SUCCESS;
+}
+
+static int test_snprintf(void)
+{
+	char buffer[32];
+
+	TEST_ASSERT(snprintf(buffer, sizeof(buffer), "%u", 1234) == 4);
+	TEST_ASSERT(strncmp(buffer, "1234", sizeof(buffer)) == 0);
+	return EC_SUCCESS;
+}
+
+static int test_strcspn(void)
+{
+	const char str1[] = "abc";
+	const char str2[] = "This is a string\nwith newlines!";
+
+	TEST_EQ(strcspn(str1, "a"), (size_t)0, "%zu");
+	TEST_EQ(strcspn(str1, "b"), (size_t)1, "%zu");
+	TEST_EQ(strcspn(str1, "c"), (size_t)2, "%zu");
+	TEST_EQ(strcspn(str1, "ccc"), (size_t)2, "%zu");
+	TEST_EQ(strcspn(str1, "cba"), (size_t)0, "%zu");
+	TEST_EQ(strcspn(str1, "cb"), (size_t)1, "%zu");
+	TEST_EQ(strcspn(str1, "bc"), (size_t)1, "%zu");
+	TEST_EQ(strcspn(str1, "cbc"), (size_t)1, "%zu");
+	TEST_EQ(strcspn(str1, "z"), strlen(str1), "%zu");
+	TEST_EQ(strcspn(str1, "xyz"), strlen(str1), "%zu");
+	TEST_EQ(strcspn(str1, ""), strlen(str1), "%zu");
+
+	TEST_EQ(strcspn(str2, " "), (size_t)4, "%zu");
+	TEST_EQ(strcspn(str2, "\n"), (size_t)16, "%zu");
+	TEST_EQ(strcspn(str2, "\n "), (size_t)4, "%zu");
+	TEST_EQ(strcspn(str2, "!"), strlen(str2) - 1, "%zu");
+	TEST_EQ(strcspn(str2, "z"), strlen(str2), "%zu");
+	TEST_EQ(strcspn(str2, "z!"), strlen(str2) - 1, "%zu");
+
+	return EC_SUCCESS;
+}
+
+static int test_memmove(void)
+{
+	int i;
+	timestamp_t t0, t1, t2, t3;
+	char *buf;
+	const int buf_size = 1000;
+	const int len = 400;
+	const int iteration = 1000;
+
+	TEST_ASSERT(shared_mem_acquire(buf_size, &buf) == EC_SUCCESS);
+
+	for (i = 0; i < len; ++i)
+		buf[i] = i & 0x7f;
+	for (i = len; i < buf_size; ++i)
+		buf[i] = 0;
+
+	t0 = get_time();
+	for (i = 0; i < iteration; ++i)
+		memmove(buf + 101, buf, len); /* unaligned */
+	t1 = get_time();
+	TEST_ASSERT_ARRAY_EQ(buf + 101, buf, len);
+	ccprintf(" (speed gain: %" PRId64 " ->", t1.val - t0.val);
+
+	t2 = get_time();
+	for (i = 0; i < iteration; ++i)
+		memmove(buf + 100, buf, len); /* aligned */
+	t3 = get_time();
+	ccprintf(" %" PRId64 " us) ", t3.val - t2.val);
+	TEST_ASSERT_ARRAY_EQ(buf + 100, buf, len);
+
+	if (!IS_ENABLED(EMU_BUILD) && use_builtin_stdlib)
+		TEST_ASSERT((t1.val - t0.val) > (t3.val - t2.val));
+
+	/* Test small moves */
+	memmove(buf + 1, buf, 1);
+	TEST_ASSERT_ARRAY_EQ(buf + 1, buf, 1);
+	memmove(buf + 5, buf, 4);
+	memmove(buf + 1, buf, 4);
+	TEST_ASSERT_ARRAY_EQ(buf + 1, buf + 5, 4);
+
+	shared_mem_release(buf);
+	return EC_SUCCESS;
+}
+
+static int test_memcpy(void)
+{
+	int i;
+	timestamp_t t0, t1, t2, t3;
+	char *buf;
+	const int buf_size = 1000;
+	const int len = 400;
+	const int dest_offset = 500;
+	const int iteration = 1000;
+
+	TEST_ASSERT(shared_mem_acquire(buf_size, &buf) == EC_SUCCESS);
+
+	for (i = 0; i < len; ++i)
+		buf[i] = i & 0x7f;
+	for (i = len; i < buf_size; ++i)
+		buf[i] = 0;
+
+	t0 = get_time();
+	for (i = 0; i < iteration; ++i)
+		memcpy(buf + dest_offset + 1, buf, len); /* unaligned */
+	t1 = get_time();
+	TEST_ASSERT_ARRAY_EQ(buf + dest_offset + 1, buf, len);
+	ccprintf(" (speed gain: %" PRId64 " ->", t1.val - t0.val);
+
+	t2 = get_time();
+	for (i = 0; i < iteration; ++i)
+		memcpy(buf + dest_offset, buf, len); /* aligned */
+	t3 = get_time();
+	ccprintf(" %" PRId64 " us) ", t3.val - t2.val);
+	TEST_ASSERT_ARRAY_EQ(buf + dest_offset, buf, len);
+
+	if (!IS_ENABLED(EMU_BUILD))
+		TEST_ASSERT((t1.val - t0.val) > (t3.val - t2.val));
+
+	memcpy(buf + dest_offset + 1, buf + 1, len - 1);
+	TEST_ASSERT_ARRAY_EQ(buf + dest_offset + 1, buf + 1, len - 1);
+
+	/* Test small copies */
+	memcpy(buf + dest_offset, buf, 1);
+	TEST_ASSERT_ARRAY_EQ(buf + dest_offset, buf, 1);
+	memcpy(buf + dest_offset, buf, 4);
+	TEST_ASSERT_ARRAY_EQ(buf + dest_offset, buf, 4);
+	memcpy(buf + dest_offset + 1, buf, 1);
+	TEST_ASSERT_ARRAY_EQ(buf + dest_offset + 1, buf, 1);
+	memcpy(buf + dest_offset + 1, buf, 4);
+	TEST_ASSERT_ARRAY_EQ(buf + dest_offset + 1, buf, 4);
+
+	shared_mem_release(buf);
+	return EC_SUCCESS;
+}
+
+/* Plain memset, used as a reference to measure speed gain */
+static void *dumb_memset(void *dest, int c, int len)
+{
+	char *d = (char *)dest;
+	while (len > 0) {
+		*(d++) = c;
+		len--;
+	}
+	return dest;
+}
+
+static int test_memset(void)
+{
+	int i;
+	timestamp_t t0, t1, t2, t3;
+	char *buf;
+	const int buf_size = 1000;
+	const int len = 400;
+	const int iteration = 1000;
+
+	TEST_ASSERT(shared_mem_acquire(buf_size, &buf) == EC_SUCCESS);
+
+	t0 = get_time();
+	for (i = 0; i < iteration; ++i)
+		dumb_memset(buf, 1, len);
+	t1 = get_time();
+	TEST_ASSERT_MEMSET(buf, (char)1, len);
+	ccprintf(" (speed gain: %" PRId64 " ->", t1.val - t0.val);
+
+	t2 = get_time();
+	for (i = 0; i < iteration; ++i)
+		memset(buf, 1, len);
+	t3 = get_time();
+	TEST_ASSERT_MEMSET(buf, (char)1, len);
+	ccprintf(" %" PRId64 " us) ", t3.val - t2.val);
+
+	if (!IS_ENABLED(EMU_BUILD))
+		TEST_ASSERT((t1.val - t0.val) > (t3.val - t2.val));
+
+	memset(buf, 128, len);
+	TEST_ASSERT_MEMSET(buf, (char)128, len);
+
+	memset(buf, -2, len);
+	TEST_ASSERT_MEMSET(buf, (char)-2, len);
+
+	memset(buf + 1, 1, len - 2);
+	TEST_ASSERT_MEMSET(buf + 1, (char)1, len - 2);
+
+	shared_mem_release(buf);
+	return EC_SUCCESS;
+}
+
+static int test_memchr(void)
+{
+	char *buf = "1234";
+
+	TEST_ASSERT(memchr("123567890", '4', 8) == NULL);
+	TEST_ASSERT(memchr("123", '3', 2) == NULL);
+	TEST_ASSERT(memchr(buf, '3', 4) == buf + 2);
+	TEST_ASSERT(memchr(buf, '4', 4) == buf + 3);
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
+{
+	test_reset();
+
+	RUN_TEST(test_isalpha);
+	RUN_TEST(test_isprint);
+	RUN_TEST(test_strstr);
+	RUN_TEST(test_strtoull);
+	RUN_TEST(test_strncpy);
+	RUN_TEST(test_strncmp);
+	RUN_TEST(test_strlen);
+	RUN_TEST(test_strnlen);
+	RUN_TEST(test_strcasecmp);
+	RUN_TEST(test_strncasecmp);
+	RUN_TEST(test_atoi);
+	RUN_TEST(test_snprintf);
+	RUN_TEST(test_strcspn);
+	RUN_TEST(test_memmove);
+	RUN_TEST(test_memcpy);
+	RUN_TEST(test_memset);
+	RUN_TEST(test_memchr);
+
+	test_print_result();
+}
diff --git a/test/stdlib.tasklist b/test/stdlib.tasklist
new file mode 100644
index 0000000000..1154b1ae8b
--- /dev/null
+++ b/test/stdlib.tasklist
@@ -0,0 +1,9 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TEST_TASK_LIST  /* No test task */
diff --git a/test/stillness_detector.c b/test/stillness_detector.c
index 57057e217e..8858d751d7 100644
--- a/test/stillness_detector.c
+++ b/test/stillness_detector.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -35,8 +35,8 @@ static int test_not_still_short_window(void)
 	int i;
 
 	for (i = 0; i < 6; ++i)
-		TEST_ASSERT(!still_det_update(&det, i * 100 * MSEC,
-					      0.0f, 0.0f, 0.0f));
+		TEST_ASSERT(!still_det_update(&det, i * 100 * MSEC, 0.0f, 0.0f,
+					      0.0f));
 
 	return EC_SUCCESS;
 }
@@ -47,8 +47,8 @@ static int test_not_still_long_window(void)
 	int i;
 
 	for (i = 0; i < 5; ++i)
-		TEST_ASSERT(!still_det_update(&det, i * 300 * MSEC,
-					      0.0f, 0.0f, 0.0f));
+		TEST_ASSERT(!still_det_update(&det, i * 300 * MSEC, 0.0f, 0.0f,
+					      0.0f));
 
 	return EC_SUCCESS;
 }
@@ -59,8 +59,8 @@ static int test_not_still_not_enough_samples(void)
 	int i;
 
 	for (i = 0; i < 4; ++i)
-		TEST_ASSERT(!still_det_update(&det, i * 200 * MSEC,
-					      0.0f, 0.0f, 0.0f));
+		TEST_ASSERT(!still_det_update(&det, i * 200 * MSEC, 0.0f, 0.0f,
+					      0.0f));
 
 	return EC_SUCCESS;
 }
@@ -71,9 +71,8 @@ static int test_is_still_all_axes(void)
 	int i;
 
 	for (i = 0; i < 9; ++i) {
-		int result = still_det_update(&det, i * 100 * MSEC,
-					      i * 0.001f, i * 0.001f,
-					      i * 0.001f);
+		int result = still_det_update(&det, i * 100 * MSEC, i * 0.001f,
+					      i * 0.001f, i * 0.001f);
 
 		TEST_EQ(result, i == 8 ? 1 : 0, "%d");
 	}
@@ -90,9 +89,8 @@ static int test_not_still_one_axis(void)
 	int i;
 
 	for (i = 0; i < 9; ++i) {
-		TEST_ASSERT(!still_det_update(&det, i * 100 * MSEC,
-					      i * 0.001f, i * 0.001f,
-					      i * 0.01f));
+		TEST_ASSERT(!still_det_update(&det, i * 100 * MSEC, i * 0.001f,
+					      i * 0.001f, i * 0.01f));
 	}
 
 	return EC_SUCCESS;
@@ -104,15 +102,13 @@ static int test_resets(void)
 	int i;
 
 	for (i = 0; i < 9; ++i) {
-		TEST_ASSERT(!still_det_update(&det, i * 100 * MSEC,
-					      i * 0.001f, i * 0.001f,
-					      i * 0.01f));
+		TEST_ASSERT(!still_det_update(&det, i * 100 * MSEC, i * 0.001f,
+					      i * 0.001f, i * 0.01f));
 	}
 
 	for (i = 0; i < 9; ++i) {
-		int result = still_det_update(&det, i * 100 * MSEC,
-					      i * 0.001f, i * 0.001f,
-					      i * 0.001f);
+		int result = still_det_update(&det, i * 100 * MSEC, i * 0.001f,
+					      i * 0.001f, i * 0.001f);
 
 		TEST_EQ(result, i == 8 ? 1 : 0, "%d");
 	}
@@ -123,7 +119,7 @@ static int test_resets(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
@@ -136,6 +132,6 @@ void run_test(int argc, char **argv)
 	RUN_TEST(test_resets);
 
 	/* Wait for all background tasks to start. */
-	sleep(2);
+	sleep(4);
 	test_print_result();
 }
diff --git a/test/stillness_detector.tasklist b/test/stillness_detector.tasklist
index 5ffe662d01..2d4595f76a 100644
--- a/test/stillness_detector.tasklist
+++ b/test/stillness_detector.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/stm32f_rtc.c b/test/stm32f_rtc.c
index b9b48ec043..b055398b28 100644
--- a/test/stm32f_rtc.c
+++ b/test/stm32f_rtc.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -67,7 +67,7 @@ test_static int test_rtc_match_delay(void)
 	}
 
 	ccprintf("Expected number of RTC alarm interrupts %d\n",
-	    rtc_match_delay_iterations);
+		 rtc_match_delay_iterations);
 	ccprintf("Actual number of RTC alarm interrupts %d\n", rtc_fired);
 
 	/* Make sure each set_rtc_alarm() generated the interrupt. */
@@ -76,7 +76,7 @@ test_static int test_rtc_match_delay(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/stm32f_rtc.tasklist b/test/stm32f_rtc.tasklist
index 51734f058d..a1f1a94e2d 100644
--- a/test/stm32f_rtc.tasklist
+++ b/test/stm32f_rtc.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/stress.c b/test/stress.c
index 91a65197f8..f497644602 100644
--- a/test/stress.c
+++ b/test/stress.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -46,8 +46,7 @@ struct i2c_test_param_t {
 /* period between 500us and 32ms */
 #define RAND_US() (((prng_no_seed() % 64) + 1) * 500)
 
-static int stress(const char *name,
-		  int (*test_routine)(void),
+static int stress(const char *name, int (*test_routine)(void),
 		  const int iteration)
 {
 	int i;
@@ -65,12 +64,12 @@ static int stress(const char *name,
 	return EC_SUCCESS;
 }
 
-#define RUN_STRESS_TEST(n, r, iter) \
-	do { \
+#define RUN_STRESS_TEST(n, r, iter)                     \
+	do {                                            \
 		if (stress(n, r, iter) != EC_SUCCESS) { \
-			ccputs("Fail\n"); \
-			error_count++; \
-		} \
+			ccputs("Fail\n");               \
+			error_count++;                  \
+		}                                       \
 	} while (0)
 
 /*****************************************************************************/
@@ -81,26 +80,27 @@ static int test_i2c(void)
 	int res = EC_ERROR_UNKNOWN;
 	int mock_data;
 	struct i2c_test_param_t *param;
-	param = i2c_test_params + (prng_no_seed() % (sizeof(i2c_test_params) /
-				   sizeof(struct i2c_test_param_t)));
+	param = i2c_test_params +
+		(prng_no_seed() %
+		 (sizeof(i2c_test_params) / sizeof(struct i2c_test_param_t)));
 	if (param->width == 8 && param->data == -1)
-		res = i2c_read8(param->port, param->addr,
-				param->offset, &mock_data);
+		res = i2c_read8(param->port, param->addr, param->offset,
+				&mock_data);
 	else if (param->width == 8 && param->data >= 0)
-		res = i2c_write8(param->port, param->addr,
-				 param->offset, param->data);
+		res = i2c_write8(param->port, param->addr, param->offset,
+				 param->data);
 	else if (param->width == 16 && param->data == -1)
-		res = i2c_read16(param->port, param->addr,
-				 param->offset, &mock_data);
+		res = i2c_read16(param->port, param->addr, param->offset,
+				 &mock_data);
 	else if (param->width == 16 && param->data >= 0)
-		res = i2c_write16(param->port, param->addr,
-				  param->offset, param->data);
+		res = i2c_write16(param->port, param->addr, param->offset,
+				  param->data);
 	else if (param->width == 32 && param->data == -1)
-		res = i2c_read32(param->port, param->addr,
-				 param->offset, &mock_data);
+		res = i2c_read32(param->port, param->addr, param->offset,
+				 &mock_data);
 	else if (param->width == 32 && param->data >= 0)
-		res = i2c_write32(param->port, param->addr,
-				  param->offset, param->data);
+		res = i2c_write32(param->port, param->addr, param->offset,
+				  param->data);
 
 	return res;
 }
@@ -128,7 +128,7 @@ static int test_adc(void)
 }
 #endif
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/stress.tasklist b/test/stress.tasklist
index da0ab6211a..100cb6b5bd 100644
--- a/test/stress.tasklist
+++ b/test/stress.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/system.c b/test/system.c
index 79383b82d9..d123bd5cee 100644
--- a/test/system.c
+++ b/test/system.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -13,8 +13,8 @@
 #include "timer.h"
 #include "util.h"
 
-#define TEST_STATE_STEP_2	(1 << 0)
-#define TEST_STATE_FAIL		(1 << 1)
+#define TEST_STATE_STEP_2 (1 << 0)
+#define TEST_STATE_FAIL (1 << 1)
 
 static int test_reboot_on_shutdown(void)
 {
@@ -92,7 +92,7 @@ static void fail_and_clean_up(void)
 	test_fail();
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	uint32_t state = 0;
 
diff --git a/test/system.tasklist b/test/system.tasklist
index 4e455a7ea3..6967ec1095 100644
--- a/test/system.tasklist
+++ b/test/system.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/system_is_locked.c b/test/system_is_locked.c
index 9870f77ebc..47a7977601 100644
--- a/test/system_is_locked.c
+++ b/test/system_is_locked.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -60,7 +60,7 @@ void test_run_step(uint32_t state)
 		else if (write_protect_enabled) {
 			ccprintf("Request RO protection at boot\n");
 			crec_flash_set_protect(EC_FLASH_PROTECT_RO_AT_BOOT,
-			    EC_FLASH_PROTECT_RO_AT_BOOT);
+					       EC_FLASH_PROTECT_RO_AT_BOOT);
 			test_reboot_to_next_step(TEST_STATE_STEP_2);
 		} else {
 			/* Write protect is disabled, nothing else to do */
@@ -90,7 +90,7 @@ int task_test(void *unused)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/system_is_locked.tasklist b/test/system_is_locked.tasklist
index 6a2f1834ca..273a9664c0 100644
--- a/test/system_is_locked.tasklist
+++ b/test/system_is_locked.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/test_config.h b/test/test_config.h
index afd72ce1d2..d72a078434 100644
--- a/test/test_config.h
+++ b/test/test_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,9 +20,13 @@
 
 /* Don't compile features unless specifically testing for them */
 #undef CONFIG_VBOOT_HASH
+
+/* Only disable this if we didn't explicitly enable it in Kconfig */
+#ifndef CONFIG_PLATFORM_EC_USB_PD_LOGGING
 #undef CONFIG_USB_PD_LOGGING
+#endif
 
-#ifdef TEST_AES
+#if defined(TEST_AES) || defined(TEST_CRYPTO_BENCHMARK)
 #define CONFIG_AES
 #define CONFIG_AES_GCM
 #endif
@@ -55,6 +59,8 @@
 
 #ifdef TEST_KB_8042
 #define CONFIG_KEYBOARD_PROTOCOL_8042
+#define CONFIG_8042_AUX
+#define CONFIG_KEYBOARD_DEBUG
 #endif
 
 #ifdef TEST_KB_MKBP
@@ -142,6 +148,11 @@
 #define CONFIG_RGBKBD_DEMO_DOT
 #endif
 
+#ifdef TEST_NVIDIA_GPU
+#define CONFIG_GPU_NVIDIA
+#define GPIO_NVIDIA_GPU_ACOFF_ODL 123
+#endif
+
 #ifdef TEST_STILLNESS_DETECTOR
 #define CONFIG_MKBP_EVENT
 #define CONFIG_MKBP_USE_GPIO
@@ -169,17 +180,13 @@
 #define CONFIG_MKBP_USE_GPIO
 #endif
 
-#if defined(CONFIG_ONLINE_CALIB) && \
-	!defined(CONFIG_TEMP_CACHE_STALE_THRES)
+#if defined(CONFIG_ONLINE_CALIB) && !defined(CONFIG_TEMP_CACHE_STALE_THRES)
 #define CONFIG_TEMP_CACHE_STALE_THRES (1 * SECOND)
 #endif /* CONFIG_ONLINE_CALIB && !CONFIG_TEMP_CACHE_STALE_THRES */
 
-#if defined(CONFIG_ONLINE_CALIB) || \
-	defined(TEST_BODY_DETECTION) || \
-	defined(TEST_MOTION_ANGLE) || \
-	defined(TEST_MOTION_ANGLE_TABLET) || \
-	defined(TEST_MOTION_LID) || \
-	defined(TEST_MOTION_SENSE_FIFO)
+#if defined(CONFIG_ONLINE_CALIB) || defined(TEST_BODY_DETECTION) ||        \
+	defined(TEST_MOTION_ANGLE) || defined(TEST_MOTION_ANGLE_TABLET) || \
+	defined(TEST_MOTION_LID) || defined(TEST_MOTION_SENSE_FIFO)
 enum sensor_id {
 	BASE,
 	LID,
@@ -195,15 +202,14 @@ enum sensor_id {
 #endif
 
 #if defined(TEST_MOTION_ANGLE)
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
+#define CONFIG_ACCEL_FORCE_MODE_MASK           \
 	((1 << CONFIG_LID_ANGLE_SENSOR_BASE) | \
 	 (1 << CONFIG_LID_ANGLE_SENSOR_LID))
 #define CONFIG_ACCEL_STD_REF_FRAME_OLD
 #endif
 
-#if defined(TEST_MOTION_ANGLE_TABLET) || \
-	defined(TEST_MOTION_LID)
-#define CONFIG_ACCEL_FORCE_MODE_MASK \
+#if defined(TEST_MOTION_ANGLE_TABLET) || defined(TEST_MOTION_LID)
+#define CONFIG_ACCEL_FORCE_MODE_MASK           \
 	((1 << CONFIG_LID_ANGLE_SENSOR_BASE) | \
 	 (1 << CONFIG_LID_ANGLE_SENSOR_LID))
 #endif
@@ -216,19 +222,21 @@ enum sensor_id {
 #ifdef TEST_RMA_AUTH
 
 /* Test server public and private keys */
-#define RMA_KEY_BLOB	{					\
-		0x03, 0xae, 0x2d, 0x2c, 0x06, 0x23, 0xe0, 0x73, \
-		0x0d, 0xd3, 0xb7, 0x92, 0xac, 0x54, 0xc5, 0xfd,	\
-		0x7e, 0x9c, 0xf0, 0xa8, 0xeb, 0x7e, 0x2a, 0xb5,	\
-		0xdb, 0xf4, 0x79, 0x5f, 0x8a, 0x0f, 0x28, 0x3f, \
-		0x10						\
+#define RMA_KEY_BLOB                                                          \
+	{                                                                     \
+		0x03, 0xae, 0x2d, 0x2c, 0x06, 0x23, 0xe0, 0x73, 0x0d, 0xd3,   \
+			0xb7, 0x92, 0xac, 0x54, 0xc5, 0xfd, 0x7e, 0x9c, 0xf0, \
+			0xa8, 0xeb, 0x7e, 0x2a, 0xb5, 0xdb, 0xf4, 0x79, 0x5f, \
+			0x8a, 0x0f, 0x28, 0x3f, 0x10                          \
 	}
 
-#define RMA_TEST_SERVER_PRIVATE_KEY {				\
-		0x47, 0x3b, 0xa5, 0xdb, 0xc4, 0xbb, 0xd6, 0x77, \
-		0x20, 0xbd, 0xd8, 0xbd, 0xc8, 0x7a, 0xbb, 0x07,	\
-		0x03, 0x79, 0xba, 0x7b, 0x52, 0x8c, 0xec, 0xb3,	\
-		0x4d, 0xaa, 0x69, 0xf5, 0x65, 0xb4, 0x31, 0xad}
+#define RMA_TEST_SERVER_PRIVATE_KEY                                           \
+	{                                                                     \
+		0x47, 0x3b, 0xa5, 0xdb, 0xc4, 0xbb, 0xd6, 0x77, 0x20, 0xbd,   \
+			0xd8, 0xbd, 0xc8, 0x7a, 0xbb, 0x07, 0x03, 0x79, 0xba, \
+			0x7b, 0x52, 0x8c, 0xec, 0xb3, 0x4d, 0xaa, 0x69, 0xf5, \
+			0x65, 0xb4, 0x31, 0xad                                \
+	}
 #define RMA_TEST_SERVER_KEY_ID 0x10
 
 #define CONFIG_BASE32
@@ -290,8 +298,8 @@ int board_discharge_on_ac(int enabled);
 #define I2C_PORT_BATTERY 0
 #define I2C_PORT_CHARGER 0
 #define CONFIG_BATTERY_LOW_VOLTAGE_PROTECTION
-#undef  CONFIG_BATTERY_LOW_VOLTAGE_TIMEOUT
-#define CONFIG_BATTERY_LOW_VOLTAGE_TIMEOUT  (2*SECOND)
+#undef CONFIG_BATTERY_LOW_VOLTAGE_TIMEOUT
+#define CONFIG_BATTERY_LOW_VOLTAGE_TIMEOUT (2 * SECOND)
 #endif
 
 #ifdef TEST_THERMAL
@@ -361,10 +369,8 @@ int ncp15wb_calculate_temp(uint16_t adc);
 #define CONFIG_USB_PD_ONLY_FIXED_PDOS
 #endif
 
-#if defined(TEST_USB_SM_FRAMEWORK_H3) || \
-	defined(TEST_USB_SM_FRAMEWORK_H2) || \
-	defined(TEST_USB_SM_FRAMEWORK_H1) || \
-	defined(TEST_USB_SM_FRAMEWORK_H0)
+#if defined(TEST_USB_SM_FRAMEWORK_H3) || defined(TEST_USB_SM_FRAMEWORK_H2) || \
+	defined(TEST_USB_SM_FRAMEWORK_H1) || defined(TEST_USB_SM_FRAMEWORK_H0)
 #define CONFIG_TEST_SM
 #endif
 
@@ -457,8 +463,7 @@ int ncp15wb_calculate_temp(uint16_t adc);
 #endif /* TEST_USB_PE_DRP || TEST_USB_PE_DRP_NOEXTENDED */
 
 /* Common TypeC tests defines */
-#if defined(TEST_USB_TYPEC_VPD) || \
-	defined(TEST_USB_TYPEC_CTVPD)
+#if defined(TEST_USB_TYPEC_VPD) || defined(TEST_USB_TYPEC_CTVPD)
 #define CONFIG_USB_PID 0x5036
 #define VPD_HW_VERSION 0x0001
 #define VPD_FW_VERSION 0x0001
@@ -629,18 +634,17 @@ int ncp15wb_calculate_temp(uint16_t adc);
 #define CONFIG_RSA
 #define CONFIG_RWSIG_TYPE_RWSIG
 #define CONFIG_RW_B
-#define CONFIG_RW_B_MEM_OFF		CONFIG_RO_MEM_OFF
-#undef  CONFIG_RO_SIZE
-#define CONFIG_RO_SIZE			(CONFIG_FLASH_SIZE_BYTES / 4)
-#undef  CONFIG_RW_SIZE
-#define CONFIG_RW_SIZE			CONFIG_RO_SIZE
-#define CONFIG_RW_A_STORAGE_OFF		CONFIG_RW_STORAGE_OFF
-#define CONFIG_RW_B_STORAGE_OFF		(CONFIG_RW_A_STORAGE_OFF + \
-					 CONFIG_RW_SIZE)
-#define CONFIG_RW_A_SIGN_STORAGE_OFF	(CONFIG_RW_A_STORAGE_OFF + \
-					 CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE)
-#define CONFIG_RW_B_SIGN_STORAGE_OFF	(CONFIG_RW_B_STORAGE_OFF + \
-					 CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE)
+#define CONFIG_RW_B_MEM_OFF CONFIG_RO_MEM_OFF
+#undef CONFIG_RO_SIZE
+#define CONFIG_RO_SIZE (CONFIG_FLASH_SIZE_BYTES / 4)
+#undef CONFIG_RW_SIZE
+#define CONFIG_RW_SIZE CONFIG_RO_SIZE
+#define CONFIG_RW_A_STORAGE_OFF CONFIG_RW_STORAGE_OFF
+#define CONFIG_RW_B_STORAGE_OFF (CONFIG_RW_A_STORAGE_OFF + CONFIG_RW_SIZE)
+#define CONFIG_RW_A_SIGN_STORAGE_OFF \
+	(CONFIG_RW_A_STORAGE_OFF + CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE)
+#define CONFIG_RW_B_SIGN_STORAGE_OFF \
+	(CONFIG_RW_B_STORAGE_OFF + CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE)
 #endif
 
 #ifdef TEST_X25519
@@ -654,5 +658,5 @@ int ncp15wb_calculate_temp(uint16_t adc);
 #define I2C_BITBANG_PORT_COUNT 1
 #endif
 
-#endif  /* TEST_BUILD */
-#endif  /* __TEST_TEST_CONFIG_H */
+#endif /* TEST_BUILD */
+#endif /* __TEST_TEST_CONFIG_H */
diff --git a/test/thermal.c b/test/thermal.c
index 1161ecbf1b..a70137238d 100644
--- a/test/thermal.c
+++ b/test/thermal.c
@@ -1,10 +1,11 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
  * Test thermal engine.
  */
 
+#include "builtin/assert.h"
 #include "common.h"
 #include "console.h"
 #include "driver/temp_sensor/thermistor.h"
@@ -18,7 +19,6 @@
 #include "timer.h"
 #include "util.h"
 
-
 /*****************************************************************************/
 /* Exported data */
 
@@ -95,7 +95,7 @@ static void reset_mocks(void)
 	memset(thermal_params, 0, sizeof(thermal_params));
 
 	/* All sensors report error anyway */
-	set_temps(-1, -1 , -1, -1);
+	set_temps(-1, -1, -1, -1);
 
 	/* Reset expectations */
 	host_throttled = 0;
@@ -105,7 +105,6 @@ static void reset_mocks(void)
 	no_temps_read = 0;
 }
 
-
 /*****************************************************************************/
 /* Tests */
 
@@ -147,7 +146,6 @@ static int test_sensors_can_be_read(void)
 	return EC_SUCCESS;
 }
 
-
 static int test_one_fan(void)
 {
 	reset_mocks();
@@ -448,42 +446,41 @@ static int test_several_limits(void)
 	TEST_ASSERT(cpu_throttled == 0);
 	TEST_ASSERT(cpu_shutdown == 0);
 
-	set_temps(500, 50, -1, 10);	/* 1=low, 2=X, 3=low */
+	set_temps(500, 50, -1, 10); /* 1=low, 2=X, 3=low */
 	sleep(2);
 	TEST_ASSERT(host_throttled == 0);
 	TEST_ASSERT(cpu_throttled == 0);
 	TEST_ASSERT(cpu_shutdown == 0);
 
-	set_temps(500, 170, 210, 10);	/* 1=warn, 2=high, 3=low */
+	set_temps(500, 170, 210, 10); /* 1=warn, 2=high, 3=low */
 	sleep(2);
 	TEST_ASSERT(host_throttled == 1);
 	TEST_ASSERT(cpu_throttled == 1);
 	TEST_ASSERT(cpu_shutdown == 0);
 
-	set_temps(500, 100, 50, 40);	/* 1=low, 2=low, 3=high */
+	set_temps(500, 100, 50, 40); /* 1=low, 2=low, 3=high */
 	sleep(2);
 	TEST_ASSERT(host_throttled == 1);
 	TEST_ASSERT(cpu_throttled == 1);
 	TEST_ASSERT(cpu_shutdown == 0);
 
-	set_temps(500, 100, 50, 41);	/* 1=low, 2=low, 3=shutdown */
+	set_temps(500, 100, 50, 41); /* 1=low, 2=low, 3=shutdown */
 	sleep(2);
 	TEST_ASSERT(host_throttled == 1);
 	TEST_ASSERT(cpu_throttled == 1);
 	TEST_ASSERT(cpu_shutdown == 1);
 
-	all_temps(0);			/* reset from shutdown */
+	all_temps(0); /* reset from shutdown */
 	sleep(2);
 	TEST_ASSERT(host_throttled == 0);
 	TEST_ASSERT(cpu_throttled == 0);
 
-
 	return EC_SUCCESS;
 }
 
 /* Tests for ncp15wb thermistor ADC-to-temp calculation */
-#define LOW_ADC_TEST_VALUE	887 /* 0 C */
-#define HIGH_ADC_TEST_VALUE	100 /* > 100C */
+#define LOW_ADC_TEST_VALUE 887 /* 0 C */
+#define HIGH_ADC_TEST_VALUE 100 /* > 100C */
 
 static int test_ncp15wb_adc_to_temp(void)
 {
@@ -496,18 +493,11 @@ static int test_ncp15wb_adc_to_temp(void)
 		int adc;
 		int temp;
 	} adc_temp_datapoints[] = {
-		{ 615, 30 },
-		{ 561, 35 },
-		{ 508, 40 },
-		{ 407, 50 },
-		{ 315, 60 },
-		{ 243, 70 },
-		{ 186, 80 },
-		{ 140, 90 },
-		{ 107, 100 },
+		{ 615, 30 }, { 561, 35 }, { 508, 40 },
+		{ 407, 50 }, { 315, 60 }, { 243, 70 },
+		{ 186, 80 }, { 140, 90 }, { 107, 100 },
 	};
 
-
 	/*
 	 * Verify that calculated temp is decreasing for entire ADC range,
 	 * and that a tick down in ADC value results in no more than 1C
@@ -518,8 +508,7 @@ static int test_ncp15wb_adc_to_temp(void)
 
 	while (--i > HIGH_ADC_TEST_VALUE) {
 		new_temp = ncp15wb_calculate_temp(i);
-		TEST_ASSERT(new_temp == temp ||
-			    new_temp == temp + 1);
+		TEST_ASSERT(new_temp == temp || new_temp == temp + 1);
 		temp = new_temp;
 	}
 
@@ -539,9 +528,7 @@ static int test_thermistor_linear_interpolate(void)
 	int i, t, t0;
 	uint16_t mv;
 	/* Simple test case - a straight line. */
-	struct thermistor_data_pair line_data[] = {
-		{ 100, 0 }, { 0, 100 }
-	};
+	struct thermistor_data_pair line_data[] = { { 100, 0 }, { 0, 100 } };
 	struct thermistor_info line_info = {
 		.scaling_factor = 1,
 		.num_pairs = ARRAY_SIZE(line_data),
@@ -576,19 +563,17 @@ static int test_thermistor_linear_interpolate(void)
 	 * of derived values but at temp - 1, temp + 1, and in between.
 	 */
 	struct {
-		uint16_t mv;	/* not scaled */
+		uint16_t mv; /* not scaled */
 		int temp;
 	} cmp[] = {
-		{ 3030, 1 },  { 2341, 5 }, { 2195, 9 },
-		{ 2120, 11 }, { 1966, 15 }, { 1811, 19 },
-		{ 1733, 21 }, { 1581, 25 }, { 1434, 29 },
-		{ 1363, 31 }, { 1227, 35 }, { 1100, 39 },
-		{ 1040, 41 }, { 929, 45 }, { 827, 49 },
-		{ 780, 51 }, { 693, 55 }, { 615, 59 },
-		{ 579, 61 }, { 514, 65 }, { 460, 69 },
-		{ 430, 71 }, { 382, 75 }, { 339, 79 },
-		{ 320, 81 }, { 285, 85 }, { 254, 89 },
-		{ 240, 91 }, { 214, 95 }, { 192, 99 },
+		{ 3030, 1 },  { 2341, 5 },  { 2195, 9 },  { 2120, 11 },
+		{ 1966, 15 }, { 1811, 19 }, { 1733, 21 }, { 1581, 25 },
+		{ 1434, 29 }, { 1363, 31 }, { 1227, 35 }, { 1100, 39 },
+		{ 1040, 41 }, { 929, 45 },  { 827, 49 },  { 780, 51 },
+		{ 693, 55 },  { 615, 59 },  { 579, 61 },  { 514, 65 },
+		{ 460, 69 },  { 430, 71 },  { 382, 75 },  { 339, 79 },
+		{ 320, 81 },  { 285, 85 },  { 254, 89 },  { 240, 91 },
+		{ 214, 95 },  { 192, 99 },
 	};
 
 	/* Return lowest temperature in data set if voltage is too high. */
@@ -602,9 +587,8 @@ static int test_thermistor_linear_interpolate(void)
 	TEST_ASSERT(t == data[info.num_pairs - 1].temp);
 
 	/* Simple line test */
-	for (mv = line_data[0].mv;
-		mv > line_data[line_info.num_pairs - 1].mv;
-		mv--) {
+	for (mv = line_data[0].mv; mv > line_data[line_info.num_pairs - 1].mv;
+	     mv--) {
 		t = thermistor_linear_interpolate(mv, &line_info);
 		TEST_ASSERT(mv == line_data[line_info.num_pairs - 1].temp - t);
 	}
@@ -614,8 +598,7 @@ static int test_thermistor_linear_interpolate(void)
 	 * decreases with increase in voltage (0-5V, 10mV steps).
 	 */
 	for (mv = data[0].mv * info.scaling_factor, t0 = data[0].temp;
-		mv > data[info.num_pairs - 1].mv;
-		mv -= 10) {
+	     mv > data[info.num_pairs - 1].mv; mv -= 10) {
 		int t1 = thermistor_linear_interpolate(mv, &info);
 
 		TEST_ASSERT(t1 >= t0);
@@ -642,7 +625,7 @@ static int test_thermistor_linear_interpolate(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	RUN_TEST(test_init_val);
 	RUN_TEST(test_sensors_can_be_read);
diff --git a/test/thermal.tasklist b/test/thermal.tasklist
index d22719d1fb..7494e757cf 100644
--- a/test/thermal.tasklist
+++ b/test/thermal.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/timer_calib.c b/test/timer_calib.c
index 68603762fe..9a58237e2f 100644
--- a/test/timer_calib.c
+++ b/test/timer_calib.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -13,7 +13,7 @@
 
 uint32_t difftime(timestamp_t t0, timestamp_t t1)
 {
-	return (uint32_t)(t1.val-t0.val);
+	return (uint32_t)(t1.val - t0.val);
 }
 
 int timer_calib_task(void *data)
@@ -56,7 +56,7 @@ int timer_calib_task(void *data)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	task_wake(TASK_ID_TESTTMR);
 }
diff --git a/test/timer_calib.py b/test/timer_calib.py
index 2a625d80c7..2b7c33060e 100644
--- a/test/timer_calib.py
+++ b/test/timer_calib.py
@@ -1,4 +1,4 @@
-# Copyright 2011 The Chromium OS Authors. All rights reserved.
+# Copyright 2011 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -7,48 +7,54 @@
 
 import time
 
-def one_pass(helper):
-      helper.wait_output("=== Timer calibration ===")
-      res = helper.wait_output("back-to-back get_time : (?P<lat>[0-9]+) us",
-                               use_re=True)["lat"]
-      minlat = int(res)
-      helper.trace("get_time latency %d us\n" % minlat)
-
-      helper.wait_output("sleep 1s")
-      t0 = time.time()
-      second = helper.wait_output("done. delay = (?P<second>[0-9]+) us",
-                               use_re=True)["second"]
-      t1 = time.time()
-      secondreal = t1 - t0
-      secondlat = int(second) - 1000000
-      helper.trace("1s timer latency %d us / real time %f s\n" % (secondlat,
-                                                                  secondreal))
-
 
-      us = {}
-      for pow2 in range(7):
-          delay = 1 << (7-pow2)
-          us[delay] = helper.wait_output("%d us => (?P<us>[0-9]+) us" % delay,
-                                  use_re=True)["us"]
-      helper.wait_output("Done.")
-
-      return minlat, secondlat, secondreal
+def one_pass(helper):
+    helper.wait_output("=== Timer calibration ===")
+    res = helper.wait_output(
+        "back-to-back get_time : (?P<lat>[0-9]+) us", use_re=True
+    )["lat"]
+    minlat = int(res)
+    helper.trace("get_time latency %d us\n" % minlat)
+
+    helper.wait_output("sleep 1s")
+    t0 = time.time()
+    second = helper.wait_output(
+        "done. delay = (?P<second>[0-9]+) us", use_re=True
+    )["second"]
+    t1 = time.time()
+    secondreal = t1 - t0
+    secondlat = int(second) - 1000000
+    helper.trace(
+        "1s timer latency %d us / real time %f s\n" % (secondlat, secondreal)
+    )
+
+    us = {}
+    for pow2 in range(7):
+        delay = 1 << (7 - pow2)
+        us[delay] = helper.wait_output(
+            "%d us => (?P<us>[0-9]+) us" % delay, use_re=True
+        )["us"]
+    helper.wait_output("Done.")
+
+    return minlat, secondlat, secondreal
 
 
 def test(helper):
-      one_pass(helper)
+    one_pass(helper)
 
-      helper.ec_command("reboot")
-      helper.wait_output("--- UART initialized")
+    helper.ec_command("reboot")
+    helper.wait_output("--- UART initialized")
 
-      # get the timing results on the second pass
-      # to avoid binary translation overhead
-      minlat, secondlat, secondreal = one_pass(helper)
+    # get the timing results on the second pass
+    # to avoid binary translation overhead
+    minlat, secondlat, secondreal = one_pass(helper)
 
-      # check that the timings somewhat make sense
-      if minlat > 220 or secondlat > 500 or abs(secondreal-1.0) > 0.200:
-           helper.fail("imprecise timings " +
-                       "(get_time %d us sleep %d us / real time %.3f s)" %
-                       (minlat, secondlat, secondreal))
+    # check that the timings somewhat make sense
+    if minlat > 220 or secondlat > 500 or abs(secondreal - 1.0) > 0.200:
+        helper.fail(
+            "imprecise timings "
+            + "(get_time %d us sleep %d us / real time %.3f s)"
+            % (minlat, secondlat, secondreal)
+        )
 
-      return True # PASS !
+    return True  # PASS !
diff --git a/test/timer_calib.tasklist b/test/timer_calib.tasklist
index 51f5beb6c1..22a63c247e 100644
--- a/test/timer_calib.tasklist
+++ b/test/timer_calib.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/timer_dos.c b/test/timer_dos.c
index c681300102..ef9cc3ef0c 100644
--- a/test/timer_dos.c
+++ b/test/timer_dos.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -68,7 +68,7 @@ int task_timer(void *seed)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	wait_for_task_started();
 	task_wake(TASK_ID_TMRD);
diff --git a/test/timer_dos.tasklist b/test/timer_dos.tasklist
index 4da3419f77..5bd77b0580 100644
--- a/test/timer_dos.tasklist
+++ b/test/timer_dos.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/timer_jump.py b/test/timer_jump.py
index f506a69fcf..a4350cecdf 100644
--- a/test/timer_jump.py
+++ b/test/timer_jump.py
@@ -1,4 +1,4 @@
-# Copyright 2012 The Chromium OS Authors. All rights reserved.
+# Copyright 2012 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -10,22 +10,25 @@ import time
 DELAY = 5
 ERROR_MARGIN = 0.5
 
+
 def test(helper):
-      helper.wait_output("idle task started")
-      helper.ec_command("sysinfo")
-      copy = helper.wait_output("Copy:\s+(?P<c>\S+)", use_re=True)["c"]
-      if copy != "RO":
-          helper.ec_command("sysjump ro")
-          helper.wait_output("idle task started")
-      helper.ec_command("gettime")
-      ec_start_time = helper.wait_output("Time: 0x[0-9a-f]* = (?P<t>[\d\.]+) s",
-                                         use_re=True)["t"]
-      time.sleep(DELAY)
-      helper.ec_command("sysjump a")
-      helper.wait_output("idle task started")
-      helper.ec_command("gettime")
-      ec_end_time = helper.wait_output("Time: 0x[0-9a-f]* = (?P<t>[\d\.]+) s",
-                                       use_re=True)["t"]
+    helper.wait_output("idle task started")
+    helper.ec_command("sysinfo")
+    copy = helper.wait_output("Copy:\s+(?P<c>\S+)", use_re=True)["c"]
+    if copy != "RO":
+        helper.ec_command("sysjump ro")
+        helper.wait_output("idle task started")
+    helper.ec_command("gettime")
+    ec_start_time = helper.wait_output(
+        "Time: 0x[0-9a-f]* = (?P<t>[\d\.]+) s", use_re=True
+    )["t"]
+    time.sleep(DELAY)
+    helper.ec_command("sysjump a")
+    helper.wait_output("idle task started")
+    helper.ec_command("gettime")
+    ec_end_time = helper.wait_output(
+        "Time: 0x[0-9a-f]* = (?P<t>[\d\.]+) s", use_re=True
+    )["t"]
 
-      time_diff = float(ec_end_time) - float(ec_start_time)
-      return time_diff >= DELAY and time_diff <= DELAY + ERROR_MARGIN
+    time_diff = float(ec_end_time) - float(ec_start_time)
+    return time_diff >= DELAY and time_diff <= DELAY + ERROR_MARGIN
diff --git a/test/timer_jump.tasklist b/test/timer_jump.tasklist
index da0ab6211a..100cb6b5bd 100644
--- a/test/timer_jump.tasklist
+++ b/test/timer_jump.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/uptime.c b/test/uptime.c
index 651628ab7b..0b6c9b56e6 100644
--- a/test/uptime.c
+++ b/test/uptime.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -62,7 +62,7 @@ test_static int test_host_uptime_info_command_failure(void)
 	return EC_RES_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/uptime.tasklist b/test/uptime.tasklist
index 9bf1c80c20..b5c09fb4c3 100644
--- a/test/uptime.tasklist
+++ b/test/uptime.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/usb_common.tasklist b/test/usb_common.tasklist
index 9bf1c80c20..b5c09fb4c3 100644
--- a/test/usb_common.tasklist
+++ b/test/usb_common.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/usb_common_test.c b/test/usb_common_test.c
index 620e061f74..e385b57c16 100644
--- a/test/usb_common_test.c
+++ b/test/usb_common_test.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -194,7 +194,7 @@ int test_pd_extract_pdo_power(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	RUN_TEST(test_pd_get_cc_state);
 	RUN_TEST(test_pd_extract_pdo_power);
diff --git a/test/usb_pd.c b/test/usb_pd.c
index 9fdb439b49..505b80e830 100644
--- a/test/usb_pd.c
+++ b/test/usb_pd.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -14,8 +14,8 @@
 #include "usb_pd_test_util.h"
 #include "util.h"
 
-#define PORT0	0
-#define PORT1	1
+#define PORT0 0
+#define PORT1 1
 
 #define BATTERY_DESIGN_VOLTAGE 7600
 #define BATTERY_DESIGN_CAPACITY 5131
@@ -87,7 +87,7 @@ int pd_adc_read(int port, int cc)
 		/* we are source connected to sink, return Rd/Open */
 		return (pd_port[port].partner_polarity == cc) ? 400 : 3000;
 	else if (!pd_port[port].host_mode &&
-		  pd_port[port].partner_role == PD_ROLE_SOURCE)
+		 pd_port[port].partner_role == PD_ROLE_SOURCE)
 		/* we are sink connected to source, return Rp/Open */
 		return (pd_port[port].partner_polarity == cc) ? 1700 : 0;
 	else if (pd_port[port].host_mode)
@@ -179,39 +179,38 @@ static void simulate_rx_msg(int port, uint16_t header, int cnt,
 
 static void simulate_wait(int port)
 {
-	uint16_t header = PD_HEADER(PD_CTRL_WAIT, PD_ROLE_SOURCE,
-				    PD_ROLE_DFP, pd_port[port].msg_rx_id,
-				    0, pd_port[port].rev, 0);
+	uint16_t header = PD_HEADER(PD_CTRL_WAIT, PD_ROLE_SOURCE, PD_ROLE_DFP,
+				    pd_port[port].msg_rx_id, 0,
+				    pd_port[port].rev, 0);
 
 	simulate_rx_msg(port, header, 0, NULL);
 }
 
 static void simulate_accept(int port)
 {
-	uint16_t header = PD_HEADER(PD_CTRL_ACCEPT, PD_ROLE_SOURCE,
-				PD_ROLE_DFP, pd_port[port].msg_rx_id,
-				0, pd_port[port].rev, 0);
+	uint16_t header = PD_HEADER(PD_CTRL_ACCEPT, PD_ROLE_SOURCE, PD_ROLE_DFP,
+				    pd_port[port].msg_rx_id, 0,
+				    pd_port[port].rev, 0);
 
 	simulate_rx_msg(port, header, 0, NULL);
 }
 
 static void simulate_reject(int port)
 {
-	uint16_t header = PD_HEADER(PD_CTRL_REJECT, PD_ROLE_SOURCE,
-				PD_ROLE_DFP, pd_port[port].msg_rx_id,
-				0, pd_port[port].rev, 0);
+	uint16_t header = PD_HEADER(PD_CTRL_REJECT, PD_ROLE_SOURCE, PD_ROLE_DFP,
+				    pd_port[port].msg_rx_id, 0,
+				    pd_port[port].rev, 0);
 
 	simulate_rx_msg(port, header, 0, NULL);
 }
 
-
 #ifdef CONFIG_USB_PD_REV30
 static void simulate_get_bat_cap(int port)
 {
 	uint16_t msg[2];
 	uint16_t header = PD_HEADER(PD_EXT_GET_BATTERY_CAP, PD_ROLE_SOURCE,
-			PD_ROLE_DFP, pd_port[port].msg_rx_id,
-			1, pd_port[port].rev, 1);
+				    PD_ROLE_DFP, pd_port[port].msg_rx_id, 1,
+				    pd_port[port].rev, 1);
 
 	/* set extended header */
 	msg[0] = PD_EXT_HEADER(0, 0, 1);
@@ -226,8 +225,8 @@ static void simulate_get_bat_status(int port)
 {
 	uint16_t msg[2];
 	uint16_t header = PD_HEADER(PD_EXT_GET_BATTERY_STATUS, PD_ROLE_SOURCE,
-			PD_ROLE_DFP, pd_port[port].msg_rx_id,
-			1, pd_port[port].rev, 1);
+				    PD_ROLE_DFP, pd_port[port].msg_rx_id, 1,
+				    pd_port[port].rev, 1);
 
 	/* set extended header */
 	msg[0] = PD_EXT_HEADER(0, 0, 1);
@@ -252,18 +251,20 @@ static void simulate_source_cap(int port, uint32_t cnt)
 
 static void simulate_goodcrc(int port, int role, int id)
 {
-	simulate_rx_msg(port, PD_HEADER(PD_CTRL_GOOD_CRC, role, role, id, 0,
-					pd_port[port].rev, 0), 0, NULL);
+	simulate_rx_msg(port,
+			PD_HEADER(PD_CTRL_GOOD_CRC, role, role, id, 0,
+				  pd_port[port].rev, 0),
+			0, NULL);
 }
 
 static int verify_goodcrc(int port, int role, int id)
 {
-
 	return pd_test_tx_msg_verify_sop(port) &&
-		pd_test_tx_msg_verify_short(port, PD_HEADER(PD_CTRL_GOOD_CRC,
-					role, role, id, 0, 0, 0)) &&
-		pd_test_tx_msg_verify_crc(port) &&
-		pd_test_tx_msg_verify_eop(port);
+	       pd_test_tx_msg_verify_short(port,
+					   PD_HEADER(PD_CTRL_GOOD_CRC, role,
+						     role, id, 0, 0, 0)) &&
+	       pd_test_tx_msg_verify_crc(port) &&
+	       pd_test_tx_msg_verify_eop(port);
 }
 
 static void plug_in_source(int port, int polarity)
@@ -296,7 +297,7 @@ static void unplug(int port)
 	usleep(30 * MSEC);
 }
 
-void pd_snk_give_back(int port, uint32_t * const ma, uint32_t * const mv)
+void pd_snk_give_back(int port, uint32_t *const ma, uint32_t *const mv)
 {
 	if (*ma == 3000)
 		give_back_called = 1;
@@ -304,9 +305,9 @@ void pd_snk_give_back(int port, uint32_t * const ma, uint32_t * const mv)
 
 static void simulate_ps_rdy(int port)
 {
-	uint16_t header = PD_HEADER(PD_CTRL_PS_RDY, PD_ROLE_SOURCE,
-				PD_ROLE_DFP, pd_port[port].msg_rx_id,
-				0, pd_port[port].rev, 0);
+	uint16_t header = PD_HEADER(PD_CTRL_PS_RDY, PD_ROLE_SOURCE, PD_ROLE_DFP,
+				    pd_port[port].msg_rx_id, 0,
+				    pd_port[port].rev, 0);
 
 	simulate_rx_msg(port, header, 0, NULL);
 }
@@ -314,7 +315,8 @@ static void simulate_ps_rdy(int port)
 static void simulate_goto_min(int port)
 {
 	uint16_t header = PD_HEADER(PD_CTRL_GOTO_MIN, PD_ROLE_SOURCE,
-		PD_ROLE_DFP, pd_port[port].msg_rx_id, 0, pd_port[port].rev, 0);
+				    PD_ROLE_DFP, pd_port[port].msg_rx_id, 0,
+				    pd_port[port].rev, 0);
 
 	simulate_rx_msg(port, header, 0, NULL);
 }
@@ -324,8 +326,9 @@ static int test_request_with_wait_and_contract(void)
 #ifdef CONFIG_USB_PD_REV30
 	uint32_t expected_status_bsdo =
 		BSDO_CAP(DIV_ROUND_NEAREST(BATTERY_REMAINING_CAPACITY *
-					BATTERY_DESIGN_VOLTAGE, 100000)) |
-					BSDO_PRESENT;
+						   BATTERY_DESIGN_VOLTAGE,
+					   100000)) |
+		BSDO_PRESENT;
 	uint16_t expected_cap_hdr = PD_EXT_HEADER(0, 0, 9);
 	uint16_t expected_cap_vid = USB_VID_GOOGLE;
 #ifdef CONFIG_USB_PID
@@ -333,12 +336,10 @@ static int test_request_with_wait_and_contract(void)
 #else
 	uint16_t expected_cap_pid = 0;
 #endif
-	uint16_t expected_cap_des =
-		DIV_ROUND_NEAREST(BATTERY_DESIGN_CAPACITY *
-			BATTERY_DESIGN_VOLTAGE, 100000);
-	uint16_t expected_cap_ful =
-		DIV_ROUND_NEAREST(BATTERY_FULL_CHARGE_CAPACITY *
-			BATTERY_DESIGN_VOLTAGE, 100000);
+	uint16_t expected_cap_des = DIV_ROUND_NEAREST(
+		BATTERY_DESIGN_CAPACITY * BATTERY_DESIGN_VOLTAGE, 100000);
+	uint16_t expected_cap_ful = DIV_ROUND_NEAREST(
+		BATTERY_FULL_CHARGE_CAPACITY * BATTERY_DESIGN_VOLTAGE, 100000);
 	uint16_t expected_cap_type = 0;
 #endif
 
@@ -358,8 +359,8 @@ static int test_request_with_wait_and_contract(void)
 	/* We're in SNK_DISCOVERY now. Let's send the source cap. */
 	simulate_source_cap(port, 1);
 	task_wait_event(30 * MSEC);
-	TEST_ASSERT(verify_goodcrc(port, PD_ROLE_SINK,
-						pd_port[port].msg_rx_id));
+	TEST_ASSERT(
+		verify_goodcrc(port, PD_ROLE_SINK, pd_port[port].msg_rx_id));
 
 	/* Wait for the power request */
 	task_wake(PD_PORT_TO_TASK_ID(port));
@@ -368,9 +369,10 @@ static int test_request_with_wait_and_contract(void)
 
 	/* Process the request */
 	TEST_ASSERT(pd_test_tx_msg_verify_sop(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
-			PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
-			pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
+	TEST_ASSERT(pd_test_tx_msg_verify_short(
+		port,
+		PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
+			  pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
 	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_rdo));
 	TEST_ASSERT(pd_test_tx_msg_verify_crc(port));
 	TEST_ASSERT(pd_test_tx_msg_verify_eop(port));
@@ -399,8 +401,8 @@ static int test_request_with_wait_and_contract(void)
 	 */
 	simulate_source_cap(port, 1);
 	task_wait_event(30 * MSEC);
-	TEST_ASSERT(verify_goodcrc(port, PD_ROLE_SINK,
-					pd_port[port].msg_rx_id));
+	TEST_ASSERT(
+		verify_goodcrc(port, PD_ROLE_SINK, pd_port[port].msg_rx_id));
 
 	/* Wait for the power request */
 	task_wake(PD_PORT_TO_TASK_ID(port));
@@ -409,9 +411,10 @@ static int test_request_with_wait_and_contract(void)
 
 	/* Process the request */
 	TEST_ASSERT(pd_test_tx_msg_verify_sop(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
-			PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
-			pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
+	TEST_ASSERT(pd_test_tx_msg_verify_short(
+		port,
+		PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
+			  pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
 	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_rdo));
 	TEST_ASSERT(pd_test_tx_msg_verify_crc(port));
 	TEST_ASSERT(pd_test_tx_msg_verify_eop(port));
@@ -441,11 +444,10 @@ static int test_request_with_wait_and_contract(void)
 	/* We had an explicit contract. So request should have been resent. */
 	/* Process the request */
 	TEST_ASSERT(pd_test_tx_msg_verify_sop(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
-			PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
-			pd_port[port].msg_tx_id, 1,
-			pd_port[port].rev, 0
-	)));
+	TEST_ASSERT(pd_test_tx_msg_verify_short(
+		port,
+		PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
+			  pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
 	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_rdo));
 	TEST_ASSERT(pd_test_tx_msg_verify_crc(port));
 	TEST_ASSERT(pd_test_tx_msg_verify_eop(port));
@@ -492,9 +494,10 @@ static int test_request_with_wait_and_contract(void)
 
 	/* Process the request */
 	TEST_ASSERT(pd_test_tx_msg_verify_sop(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
+	TEST_ASSERT(pd_test_tx_msg_verify_short(
+		port,
 		PD_HEADER(PD_EXT_BATTERY_CAP, PD_ROLE_SINK, PD_ROLE_UFP,
-		pd_port[port].msg_tx_id, 3, pd_port[port].rev, 1)));
+			  pd_port[port].msg_tx_id, 3, pd_port[port].rev, 1)));
 	TEST_ASSERT(pd_test_tx_msg_verify_short(port, expected_cap_hdr));
 	TEST_ASSERT(pd_test_tx_msg_verify_short(port, expected_cap_vid));
 	TEST_ASSERT(pd_test_tx_msg_verify_short(port, expected_cap_pid));
@@ -524,9 +527,10 @@ static int test_request_with_wait_and_contract(void)
 
 	/* Process the request */
 	TEST_ASSERT(pd_test_tx_msg_verify_sop(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
+	TEST_ASSERT(pd_test_tx_msg_verify_short(
+		port,
 		PD_HEADER(PD_DATA_BATTERY_STATUS, PD_ROLE_SINK, PD_ROLE_UFP,
-		pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
+			  pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
 	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_status_bsdo));
 	TEST_ASSERT(pd_test_tx_msg_verify_crc(port));
 	TEST_ASSERT(pd_test_tx_msg_verify_eop(port));
@@ -564,7 +568,7 @@ static int test_request_with_wait(void)
 {
 #ifdef CONFIG_USB_PD_GIVE_BACK
 	uint32_t expected_rdo = RDO_FIXED(1, 900, PD_MIN_CURRENT_MA,
-					RDO_CAP_MISMATCH | RDO_GIVE_BACK);
+					  RDO_CAP_MISMATCH | RDO_GIVE_BACK);
 #else
 	uint32_t expected_rdo = RDO_FIXED(1, 900, 900, RDO_CAP_MISMATCH);
 #endif
@@ -578,8 +582,8 @@ static int test_request_with_wait(void)
 	/* We're in SNK_DISCOVERY now. Let's send the source cap. */
 	simulate_source_cap(port, 0);
 	task_wait_event(30 * MSEC);
-	TEST_ASSERT(verify_goodcrc(port,
-			PD_ROLE_SINK, pd_port[port].msg_rx_id));
+	TEST_ASSERT(
+		verify_goodcrc(port, PD_ROLE_SINK, pd_port[port].msg_rx_id));
 
 	/* Wait for the power request */
 	task_wake(PD_PORT_TO_TASK_ID(port));
@@ -588,9 +592,10 @@ static int test_request_with_wait(void)
 
 	/* Process the request */
 	TEST_ASSERT(pd_test_tx_msg_verify_sop(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
-			PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
-			pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
+	TEST_ASSERT(pd_test_tx_msg_verify_short(
+		port,
+		PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
+			  pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
 	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_rdo));
 	TEST_ASSERT(pd_test_tx_msg_verify_crc(port));
 	TEST_ASSERT(pd_test_tx_msg_verify_eop(port));
@@ -617,8 +622,8 @@ static int test_request_with_wait(void)
 	/* Resend Source Cap. */
 	simulate_source_cap(port, 0);
 	task_wait_event(30 * MSEC);
-	TEST_ASSERT(verify_goodcrc(port,
-			PD_ROLE_SINK, pd_port[port].msg_rx_id));
+	TEST_ASSERT(
+		verify_goodcrc(port, PD_ROLE_SINK, pd_port[port].msg_rx_id));
 
 	/* Wait for the power request */
 	task_wake(PD_PORT_TO_TASK_ID(port));
@@ -627,9 +632,10 @@ static int test_request_with_wait(void)
 
 	/* Process the request */
 	TEST_ASSERT(pd_test_tx_msg_verify_sop(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
-			PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
-			pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
+	TEST_ASSERT(pd_test_tx_msg_verify_short(
+		port,
+		PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
+			  pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
 	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_rdo));
 	TEST_ASSERT(pd_test_tx_msg_verify_crc(port));
 	TEST_ASSERT(pd_test_tx_msg_verify_eop(port));
@@ -652,7 +658,7 @@ static int test_request_with_wait_no_src_cap(void)
 {
 #ifdef CONFIG_USB_PD_GIVE_BACK
 	uint32_t expected_rdo = RDO_FIXED(1, 900, PD_MIN_CURRENT_MA,
-					RDO_CAP_MISMATCH | RDO_GIVE_BACK);
+					  RDO_CAP_MISMATCH | RDO_GIVE_BACK);
 #else
 	uint32_t expected_rdo = RDO_FIXED(1, 900, 900, RDO_CAP_MISMATCH);
 #endif
@@ -666,8 +672,8 @@ static int test_request_with_wait_no_src_cap(void)
 	/* We're in SNK_DISCOVERY now. Let's send the source cap. */
 	simulate_source_cap(port, 0);
 	task_wait_event(30 * MSEC);
-	TEST_ASSERT(verify_goodcrc(port,
-			PD_ROLE_SINK, pd_port[port].msg_rx_id));
+	TEST_ASSERT(
+		verify_goodcrc(port, PD_ROLE_SINK, pd_port[port].msg_rx_id));
 
 	/* Wait for the power request */
 	task_wake(PD_PORT_TO_TASK_ID(port));
@@ -676,9 +682,10 @@ static int test_request_with_wait_no_src_cap(void)
 
 	/* Process the request */
 	TEST_ASSERT(pd_test_tx_msg_verify_sop(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
-			PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
-			pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
+	TEST_ASSERT(pd_test_tx_msg_verify_short(
+		port,
+		PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
+			  pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
 	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_rdo));
 	TEST_ASSERT(pd_test_tx_msg_verify_crc(port));
 	TEST_ASSERT(pd_test_tx_msg_verify_eop(port));
@@ -711,9 +718,10 @@ static int test_request_with_wait_no_src_cap(void)
 
 	/* Process the request */
 	TEST_ASSERT(pd_test_tx_msg_verify_sop(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
-			PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
-			pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
+	TEST_ASSERT(pd_test_tx_msg_verify_short(
+		port,
+		PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
+			  pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
 	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_rdo));
 	TEST_ASSERT(pd_test_tx_msg_verify_crc(port));
 	TEST_ASSERT(pd_test_tx_msg_verify_eop(port));
@@ -736,7 +744,7 @@ static int test_request_with_reject(void)
 {
 #ifdef CONFIG_USB_PD_GIVE_BACK
 	uint32_t expected_rdo = RDO_FIXED(1, 900, PD_MIN_CURRENT_MA,
-					RDO_CAP_MISMATCH | RDO_GIVE_BACK);
+					  RDO_CAP_MISMATCH | RDO_GIVE_BACK);
 #else
 	uint32_t expected_rdo = RDO_FIXED(1, 900, 900, RDO_CAP_MISMATCH);
 #endif
@@ -750,8 +758,8 @@ static int test_request_with_reject(void)
 	/* We're in SNK_DISCOVERY now. Let's send the source cap. */
 	simulate_source_cap(port, 0);
 	task_wait_event(30 * MSEC);
-	TEST_ASSERT(verify_goodcrc(port,
-			PD_ROLE_SINK, pd_port[port].msg_rx_id));
+	TEST_ASSERT(
+		verify_goodcrc(port, PD_ROLE_SINK, pd_port[port].msg_rx_id));
 
 	/* Wait for the power request */
 	task_wake(PD_PORT_TO_TASK_ID(port));
@@ -760,9 +768,10 @@ static int test_request_with_reject(void)
 
 	/* Process the request */
 	TEST_ASSERT(pd_test_tx_msg_verify_sop(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
-			PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
-			pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
+	TEST_ASSERT(pd_test_tx_msg_verify_short(
+		port,
+		PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
+			  pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
 	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_rdo));
 	TEST_ASSERT(pd_test_tx_msg_verify_crc(port));
 	TEST_ASSERT(pd_test_tx_msg_verify_eop(port));
@@ -788,8 +797,8 @@ static int test_request_with_reject(void)
 	/* We're in SNK_READY. Send source cap. again. */
 	simulate_source_cap(port, 0);
 	task_wait_event(30 * MSEC);
-	TEST_ASSERT(verify_goodcrc(port,
-			PD_ROLE_SINK, pd_port[port].msg_rx_id));
+	TEST_ASSERT(
+		verify_goodcrc(port, PD_ROLE_SINK, pd_port[port].msg_rx_id));
 
 	/* Wait for the power request */
 	task_wake(PD_PORT_TO_TASK_ID(port));
@@ -798,9 +807,10 @@ static int test_request_with_reject(void)
 
 	/* Process the request */
 	TEST_ASSERT(pd_test_tx_msg_verify_sop(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
-			PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
-			pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
+	TEST_ASSERT(pd_test_tx_msg_verify_short(
+		port,
+		PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
+			  pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
 	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_rdo));
 	TEST_ASSERT(pd_test_tx_msg_verify_crc(port));
 	TEST_ASSERT(pd_test_tx_msg_verify_eop(port));
@@ -814,7 +824,7 @@ static int test_request(void)
 {
 #ifdef CONFIG_USB_PD_GIVE_BACK
 	uint32_t expected_rdo = RDO_FIXED(1, 900, PD_MIN_CURRENT_MA,
-					RDO_CAP_MISMATCH | RDO_GIVE_BACK);
+					  RDO_CAP_MISMATCH | RDO_GIVE_BACK);
 #else
 	uint32_t expected_rdo = RDO_FIXED(1, 900, 900, RDO_CAP_MISMATCH);
 #endif
@@ -828,8 +838,8 @@ static int test_request(void)
 	/* We're in SNK_DISCOVERY now. Let's send the source cap. */
 	simulate_source_cap(port, 0);
 	task_wait_event(30 * MSEC);
-	TEST_ASSERT(verify_goodcrc(port,
-				PD_ROLE_SINK, pd_port[port].msg_rx_id));
+	TEST_ASSERT(
+		verify_goodcrc(port, PD_ROLE_SINK, pd_port[port].msg_rx_id));
 
 	/* Wait for the power request */
 	task_wake(PD_PORT_TO_TASK_ID(port));
@@ -838,9 +848,10 @@ static int test_request(void)
 
 	/* Process the request */
 	TEST_ASSERT(pd_test_tx_msg_verify_sop(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
-			PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
-			pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
+	TEST_ASSERT(pd_test_tx_msg_verify_short(
+		port,
+		PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
+			  pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0)));
 	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_rdo));
 	TEST_ASSERT(pd_test_tx_msg_verify_crc(port));
 	TEST_ASSERT(pd_test_tx_msg_verify_eop(port));
@@ -872,10 +883,10 @@ static int test_sink(void)
 
 	/* The source cap should be sent */
 	TEST_ASSERT(pd_test_tx_msg_verify_sop(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
-			PD_HEADER(PD_DATA_SOURCE_CAP, PD_ROLE_SOURCE,
-				  PD_ROLE_DFP, pd_port[port].msg_tx_id,
-				  pd_src_pdo_cnt, pd_port[port].rev, 0)));
+	TEST_ASSERT(pd_test_tx_msg_verify_short(
+		port, PD_HEADER(PD_DATA_SOURCE_CAP, PD_ROLE_SOURCE, PD_ROLE_DFP,
+				pd_port[port].msg_tx_id, pd_src_pdo_cnt,
+				pd_port[port].rev, 0)));
 
 	for (i = 0; i < pd_src_pdo_cnt; ++i)
 		TEST_ASSERT(pd_test_tx_msg_verify_word(port, pd_src_pdo[i]));
@@ -900,7 +911,7 @@ static int test_sink(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 	init_ports();
diff --git a/test/usb_pd.tasklist b/test/usb_pd.tasklist
index fbd319148e..6ba85de1aa 100644
--- a/test/usb_pd.tasklist
+++ b/test/usb_pd.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/usb_pd_console.c b/test/usb_pd_console.c
index c762bebfc8..711664aeb0 100644
--- a/test/usb_pd_console.c
+++ b/test/usb_pd_console.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -17,8 +17,7 @@
 #include "test_util.h"
 
 /* Defined in implementation */
-int command_pd(int argc, char **argv);
-int remote_flashing(int argc, char **argv);
+int command_pd(int argc, const char **argv);
 
 static enum debug_level prl_debug_level;
 static enum debug_level pe_debug_level;
@@ -43,6 +42,7 @@ static int test_port;
 static enum pd_dpm_request request;
 static int max_volt;
 static int comm_enable;
+static int pd_suspended;
 static int dev_info;
 static int vdm_cmd;
 static int vdm_count;
@@ -140,7 +140,7 @@ uint8_t board_get_usb_pd_port_count(void)
 }
 
 void pe_send_vdm(int port, uint32_t vid, int cmd, const uint32_t *data,
-					int count)
+		 int count)
 {
 	int i;
 
@@ -180,6 +180,12 @@ void pd_comm_enable(int port, int enable)
 	comm_enable = enable;
 }
 
+void pd_set_suspend(int port, int enable)
+{
+	test_port = port;
+	pd_suspended = enable;
+}
+
 void tc_print_dev_info(int port)
 {
 	test_port = port;
@@ -241,10 +247,15 @@ enum try_src_override_t tc_get_try_src_override(void)
 	return try_src_override;
 }
 
+enum pd_cc_states pd_get_task_cc_state(int port)
+{
+	return PD_CC_NONE;
+}
+
 static int test_command_pd_dump(void)
 {
 	int argc = 3;
-	char *argv[] = {"pd", "dump", "", 0, 0, 0};
+	const char *argv[] = { "pd", "dump", "", 0, 0, 0 };
 	char test[2];
 
 	sprintf(test, "e");
@@ -272,7 +283,7 @@ static int test_command_pd_dump(void)
 static int test_command_pd_try_src(void)
 {
 	int argc = 3;
-	char *argv[] = {"pd", "trysrc", "2", 0, 0};
+	const char *argv[] = { "pd", "trysrc", "2", 0, 0 };
 
 	try_src_override = 0;
 	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
@@ -292,7 +303,7 @@ static int test_command_pd_try_src(void)
 static int test_command_pd_version(void)
 {
 	int argc = 2;
-	char *argv[] = {"pd", "version", 0, 0, 0};
+	const char *argv[] = { "pd", "version", 0, 0, 0 };
 
 	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
 
@@ -302,7 +313,7 @@ static int test_command_pd_version(void)
 static int test_command_pd_arg_count(void)
 {
 	int argc;
-	char *argv[] = {"pd", "", 0, 0, 0};
+	const char *argv[] = { "pd", "", 0, 0, 0 };
 
 	for (argc = 0; argc < 3; argc++)
 		TEST_ASSERT(command_pd(argc, argv) == EC_ERROR_PARAM_COUNT);
@@ -313,7 +324,7 @@ static int test_command_pd_arg_count(void)
 static int test_command_pd_port_num(void)
 {
 	int argc = 3;
-	char *argv[10] = {"pd", "0", 0, 0, 0};
+	const char *argv[10] = { "pd", "0", 0, 0, 0 };
 	char test[2];
 
 	sprintf(test, "%d", CONFIG_USB_PD_PORT_MAX_COUNT);
@@ -326,7 +337,7 @@ static int test_command_pd_port_num(void)
 static int test_command_pd_tx(void)
 {
 	int argc = 3;
-	char *argv[] = {"pd", "0", "tx", 0, 0};
+	const char *argv[] = { "pd", "0", "tx", 0, 0 };
 
 	request = 0;
 	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
@@ -339,7 +350,7 @@ static int test_command_pd_tx(void)
 static int test_command_pd_charger(void)
 {
 	int argc = 3;
-	char *argv[] = {"pd", "1", "charger", 0, 0};
+	const char *argv[] = { "pd", "1", "charger", 0, 0 };
 
 	request = 0;
 	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
@@ -352,7 +363,7 @@ static int test_command_pd_charger(void)
 static int test_command_pd_dev1(void)
 {
 	int argc = 4;
-	char *argv[] = {"pd", "0", "dev", "20", 0};
+	const char *argv[] = { "pd", "0", "dev", "20", 0 };
 
 	request = 0;
 	max_volt = 0;
@@ -367,7 +378,7 @@ static int test_command_pd_dev1(void)
 static int test_command_pd_dev2(void)
 {
 	int argc = 3;
-	char *argv[] = {"pd", "1", "dev", 0, 0};
+	const char *argv[] = { "pd", "1", "dev", 0, 0 };
 
 	request = 0;
 	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
@@ -381,7 +392,7 @@ static int test_command_pd_dev2(void)
 static int test_command_pd_disable(void)
 {
 	int argc = 3;
-	char *argv[] = {"pd", "0", "disable", 0, 0};
+	const char *argv[] = { "pd", "0", "disable", 0, 0 };
 
 	comm_enable = 1;
 	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
@@ -394,7 +405,7 @@ static int test_command_pd_disable(void)
 static int test_command_pd_enable(void)
 {
 	int argc = 3;
-	char *argv[] = {"pd", "1", "enable", 0, 0};
+	const char *argv[] = { "pd", "1", "enable", 0, 0 };
 
 	comm_enable = 0;
 	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
@@ -407,7 +418,7 @@ static int test_command_pd_enable(void)
 static int test_command_pd_hard(void)
 {
 	int argc = 3;
-	char *argv[] = {"pd", "0", "hard", 0, 0};
+	const char *argv[] = { "pd", "0", "hard", 0, 0 };
 
 	request = 0;
 	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
@@ -420,7 +431,7 @@ static int test_command_pd_hard(void)
 static int test_command_pd_soft(void)
 {
 	int argc = 3;
-	char *argv[] = {"pd", "0", "soft", 0, 0};
+	const char *argv[] = { "pd", "0", "soft", 0, 0 };
 
 	request = 0;
 	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
@@ -430,10 +441,42 @@ static int test_command_pd_soft(void)
 	return EC_SUCCESS;
 }
 
+static int test_command_pd_suspend(void)
+{
+	int argc = 3;
+	static const char *argv[] = { "pd", "0", "suspend" };
+
+	test_port = -1;
+	comm_enable = -1;
+	pd_suspended = -1;
+	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
+	TEST_ASSERT(test_port == 0);
+	TEST_ASSERT(comm_enable == 0);
+	TEST_ASSERT(pd_suspended == 1);
+
+	return EC_SUCCESS;
+}
+
+static int test_command_pd_resume(void)
+{
+	int argc = 3;
+	static const char *argv[] = { "pd", "1", "resume" };
+
+	test_port = -1;
+	comm_enable = -1;
+	pd_suspended = -1;
+	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
+	TEST_ASSERT(test_port == 1);
+	TEST_ASSERT(comm_enable == 1);
+	TEST_ASSERT(pd_suspended == 0);
+
+	return EC_SUCCESS;
+}
+
 static int test_command_pd_swap1(void)
 {
 	int argc = 3;
-	char *argv[] = {"pd", "0", "swap", 0, 0};
+	const char *argv[] = { "pd", "0", "swap", 0, 0 };
 
 	TEST_ASSERT(command_pd(argc, argv) == EC_ERROR_PARAM_COUNT);
 
@@ -443,7 +486,7 @@ static int test_command_pd_swap1(void)
 static int test_command_pd_swap2(void)
 {
 	int argc = 4;
-	char *argv[] = {"pd", "0", "swap", "power", 0};
+	const char *argv[] = { "pd", "0", "swap", "power", 0 };
 
 	request = 0;
 	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
@@ -456,7 +499,7 @@ static int test_command_pd_swap2(void)
 static int test_command_pd_swap3(void)
 {
 	int argc = 4;
-	char *argv[] = {"pd", "1", "swap", "data", 0};
+	const char *argv[] = { "pd", "1", "swap", "data", 0 };
 
 	request = 0;
 	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
@@ -469,7 +512,7 @@ static int test_command_pd_swap3(void)
 static int test_command_pd_swap4(void)
 {
 	int argc = 4;
-	char *argv[] = {"pd", "0", "swap", "vconn", 0};
+	const char *argv[] = { "pd", "0", "swap", "vconn", 0 };
 
 	request = 0;
 	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
@@ -482,7 +525,7 @@ static int test_command_pd_swap4(void)
 static int test_command_pd_swap5(void)
 {
 	int argc = 4;
-	char *argv[] = {"pd", "0", "swap", "xyz", 0};
+	const char *argv[] = { "pd", "0", "swap", "xyz", 0 };
 
 	TEST_ASSERT(command_pd(argc, argv) == EC_ERROR_PARAM3);
 
@@ -492,7 +535,7 @@ static int test_command_pd_swap5(void)
 static int test_command_pd_dualrole0(void)
 {
 	int argc = 3;
-	char *argv[] = {"pd", "0", "dualrole", 0, 0};
+	const char *argv[] = { "pd", "0", "dualrole", 0, 0 };
 
 	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
 
@@ -502,7 +545,7 @@ static int test_command_pd_dualrole0(void)
 static int test_command_pd_dualrole1(void)
 {
 	int argc = 4;
-	char *argv[] = {"pd", "0", "dualrole", "on", 0};
+	const char *argv[] = { "pd", "0", "dualrole", "on", 0 };
 
 	dr_state = 0;
 	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
@@ -515,7 +558,7 @@ static int test_command_pd_dualrole1(void)
 static int test_command_pd_dualrole2(void)
 {
 	int argc = 4;
-	char *argv[] = {"pd", "0", "dualrole", "off", 0};
+	const char *argv[] = { "pd", "0", "dualrole", "off", 0 };
 
 	dr_state = 0;
 	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
@@ -528,7 +571,7 @@ static int test_command_pd_dualrole2(void)
 static int test_command_pd_dualrole3(void)
 {
 	int argc = 4;
-	char *argv[] = {"pd", "0", "dualrole", "freeze", 0};
+	const char *argv[] = { "pd", "0", "dualrole", "freeze", 0 };
 
 	dr_state = 0;
 	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
@@ -541,7 +584,7 @@ static int test_command_pd_dualrole3(void)
 static int test_command_pd_dualrole4(void)
 {
 	int argc = 4;
-	char *argv[] = {"pd", "0", "dualrole", "sink", 0};
+	const char *argv[] = { "pd", "0", "dualrole", "sink", 0 };
 
 	dr_state = 0;
 	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
@@ -554,7 +597,7 @@ static int test_command_pd_dualrole4(void)
 static int test_command_pd_dualrole5(void)
 {
 	int argc = 4;
-	char *argv[] = {"pd", "0", "dualrole", "source", 0};
+	const char *argv[] = { "pd", "0", "dualrole", "source", 0 };
 
 	dr_state = 0;
 	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
@@ -567,7 +610,7 @@ static int test_command_pd_dualrole5(void)
 static int test_command_pd_state(void)
 {
 	int argc = 3;
-	char *argv[] = {"pd", "0", "state", 0, 0};
+	const char *argv[] = { "pd", "0", "state", 0, 0 };
 
 	pd_get_polarity_called = false;
 	pd_comm_is_enabled_called = false;
@@ -596,7 +639,7 @@ static int test_command_pd_state(void)
 static int test_command_pd_srccaps(void)
 {
 	int argc = 3;
-	char *argv[] = {"pd", "0", "srccaps", 0, 0};
+	const char *argv[] = { "pd", "0", "srccaps", 0, 0 };
 
 	pd_srccaps_dump_called = false;
 	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
@@ -608,7 +651,7 @@ static int test_command_pd_srccaps(void)
 static int test_command_pd_timer(void)
 {
 	int argc = 3;
-	char *argv[] = {"pd", "0", "timer", 0, 0};
+	const char *argv[] = { "pd", "0", "timer", 0, 0 };
 
 	pd_timer_dump_called = false;
 	TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS);
@@ -617,8 +660,7 @@ static int test_command_pd_timer(void)
 	return EC_SUCCESS;
 }
 
-
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
@@ -635,6 +677,8 @@ void run_test(int argc, char **argv)
 	RUN_TEST(test_command_pd_enable);
 	RUN_TEST(test_command_pd_hard);
 	RUN_TEST(test_command_pd_soft);
+	RUN_TEST(test_command_pd_suspend);
+	RUN_TEST(test_command_pd_resume);
 	RUN_TEST(test_command_pd_swap1);
 	RUN_TEST(test_command_pd_swap2);
 	RUN_TEST(test_command_pd_swap3);
diff --git a/test/usb_pd_console.tasklist b/test/usb_pd_console.tasklist
index 8889009b0a..959f62ef79 100644
--- a/test/usb_pd_console.tasklist
+++ b/test/usb_pd_console.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/usb_pd_int.c b/test/usb_pd_int.c
index 5d3cbbf0f2..44cc280ed1 100644
--- a/test/usb_pd_int.c
+++ b/test/usb_pd_int.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -19,11 +19,12 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.driver = &mock_usb_mux_driver,
-	}
-};
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { {
+	.mux =
+		&(const struct usb_mux){
+			.driver = &mock_usb_mux_driver,
+		},
+} };
 
 void board_reset_pd_mcu(void)
 {
@@ -32,74 +33,74 @@ void board_reset_pd_mcu(void)
 static int deferred_resume_called;
 void pd_deferred_resume(int port)
 {
-		deferred_resume_called = 1;
+	deferred_resume_called = 1;
 }
 
 static int num_events;
 uint16_t tcpc_get_alert_status(void)
 {
-		if (--num_events > 0)
-			return PD_STATUS_TCPC_ALERT_0;
-		else
-			return 0;
+	if (--num_events > 0)
+		return PD_STATUS_TCPC_ALERT_0;
+	else
+		return 0;
 }
 
 test_static int test_storm_not_triggered(void)
 {
-		num_events = 100;
-		deferred_resume_called = 0;
-		schedule_deferred_pd_interrupt(PORT0);
-		task_wait_event(SECOND);
-		TEST_EQ(deferred_resume_called, 0, "%d");
+	num_events = 100;
+	deferred_resume_called = 0;
+	schedule_deferred_pd_interrupt(PORT0);
+	task_wait_event(SECOND);
+	TEST_EQ(deferred_resume_called, 0, "%d");
 
-		return EC_SUCCESS;
+	return EC_SUCCESS;
 }
 
 test_static int test_storm_triggered(void)
 {
-		num_events = 1000;
-		deferred_resume_called = 0;
-		schedule_deferred_pd_interrupt(PORT0);
-		task_wait_event(SECOND);
-		TEST_EQ(deferred_resume_called, 1, "%d");
+	num_events = 1000;
+	deferred_resume_called = 0;
+	schedule_deferred_pd_interrupt(PORT0);
+	task_wait_event(SECOND);
+	TEST_EQ(deferred_resume_called, 1, "%d");
 
-		return EC_SUCCESS;
+	return EC_SUCCESS;
 }
 
 test_static int test_storm_not_triggered_for_32bit_overflow(void)
 {
-		int i;
-		timestamp_t time;
-
-		/*
-		 * Ensure the MSB is 1 for overflow comparison tests.
-		 * But make sure not to move time backwards.
-		 */
-		time.val = (get_time().val + 0x100000000) | 0xff000000;
-		force_time(time);
-
-		/*
-		 * 100 events every second for 10 seconds should never trigger
-		 * a shutdown call.
-		 */
-		for (i = 0; i < 10; ++i) {
-			num_events = 100;
-			deferred_resume_called = 0;
-			schedule_deferred_pd_interrupt(PORT0);
-			task_wait_event(SECOND);
-
-			TEST_EQ(deferred_resume_called, 0, "%d");
-		}
-
-		return EC_SUCCESS;
+	int i;
+	timestamp_t time;
+
+	/*
+	 * Ensure the MSB is 1 for overflow comparison tests.
+	 * But make sure not to move time backwards.
+	 */
+	time.val = (get_time().val + 0x100000000) | 0xff000000;
+	force_time(time);
+
+	/*
+	 * 100 events every second for 10 seconds should never trigger
+	 * a shutdown call.
+	 */
+	for (i = 0; i < 10; ++i) {
+		num_events = 100;
+		deferred_resume_called = 0;
+		schedule_deferred_pd_interrupt(PORT0);
+		task_wait_event(SECOND);
+
+		TEST_EQ(deferred_resume_called, 0, "%d");
+	}
+
+	return EC_SUCCESS;
 }
 
 void before_test(void)
 {
-		pd_set_suspend(PORT0, 0);
+	pd_set_suspend(PORT0, 0);
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	/* Let tasks settle down */
 	task_wait_event(MINUTE);
diff --git a/test/usb_pd_int.mocklist b/test/usb_pd_int.mocklist
index 71c2e2cee9..cbff5e73eb 100644
--- a/test/usb_pd_int.mocklist
+++ b/test/usb_pd_int.mocklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/usb_pd_int.tasklist b/test/usb_pd_int.tasklist
index 3487d55dc7..1888d3fa8c 100644
--- a/test/usb_pd_int.tasklist
+++ b/test/usb_pd_int.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/usb_pd_pdo_fixed.tasklist b/test/usb_pd_pdo_fixed.tasklist
index 9a1e6b3e08..1d7b3e08c1 100644
--- a/test/usb_pd_pdo_fixed.tasklist
+++ b/test/usb_pd_pdo_fixed.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/usb_pd_pdo_fixed_test.c b/test/usb_pd_pdo_fixed_test.c
index ad247c3ba2..530f90843a 100644
--- a/test/usb_pd_pdo_fixed_test.c
+++ b/test/usb_pd_pdo_fixed_test.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -39,7 +39,7 @@ test_static int test_pd_find_pdo_index(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	RUN_TEST(test_pd_find_pdo_index);
 
diff --git a/test/usb_pd_test_util.h b/test/usb_pd_test_util.h
index 02fae22b41..c25d07db5d 100644
--- a/test/usb_pd_test_util.h
+++ b/test/usb_pd_test_util.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -31,4 +31,4 @@ int pd_test_tx_msg_verify_short(int port, uint16_t val);
 int pd_test_tx_msg_verify_word(int port, uint32_t val);
 int pd_test_tx_msg_verify_crc(int port);
 
-#endif  /* __TEST_USB_PD_TEST_UTIL_H */
+#endif /* __TEST_USB_PD_TEST_UTIL_H */
diff --git a/test/usb_pd_timer.c b/test/usb_pd_timer.c
index 85044fc987..d469e67c48 100644
--- a/test/usb_pd_timer.c
+++ b/test/usb_pd_timer.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -195,9 +195,10 @@ int test_pd_timers(void)
 		TEST_ASSERT(pd_timer_is_disabled(port, bit));
 
 	/*
-	 * Disable the PE timer range, which contains the previously enabled
-	 * timers 1-5.
+	 * Disable the PE and DPM timer ranges, which contain the previously
+	 * enabled timers 1-5.
 	 */
+	pd_timer_disable_range(port, DPM_TIMER_RANGE);
 	pd_timer_disable_range(port, PE_TIMER_RANGE);
 	/* Verify all timers are disabled. */
 	for (bit = 0; bit < PD_TIMER_COUNT; ++bit)
@@ -206,7 +207,7 @@ int test_pd_timers(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	RUN_TEST(test_pd_timers_init);
 	RUN_TEST(test_pd_timers_bit_ops);
diff --git a/test/usb_pd_timer.tasklist b/test/usb_pd_timer.tasklist
index 9a1e6b3e08..1d7b3e08c1 100644
--- a/test/usb_pd_timer.tasklist
+++ b/test/usb_pd_timer.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/usb_pe.h b/test/usb_pe.h
index f0c7f603ee..41891af557 100644
--- a/test/usb_pe.h
+++ b/test/usb_pe.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/test/usb_pe_drp.c b/test/usb_pe_drp.c
index 5130c4a4a9..8d75454c6a 100644
--- a/test/usb_pe_drp.c
+++ b/test/usb_pe_drp.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -28,11 +28,12 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.driver = &mock_usb_mux_driver,
-	}
-};
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { {
+	.mux =
+		&(const struct usb_mux){
+			.driver = &mock_usb_mux_driver,
+		},
+} };
 
 void before_test(void)
 {
@@ -57,8 +58,7 @@ void before_test(void)
 test_static void rx_message(enum tcpci_msg_type sop,
 			    enum pd_ctrl_msg_type ctrl_msg,
 			    enum pd_data_msg_type data_msg,
-			    enum pd_power_role prole,
-			    enum pd_data_role drole,
+			    enum pd_power_role prole, enum pd_data_role drole,
 			    uint32_t data)
 {
 	int type, cnt;
@@ -70,8 +70,9 @@ test_static void rx_message(enum tcpci_msg_type sop,
 		type = data_msg;
 		cnt = 1;
 	}
-	rx_emsg[PORT0].header = (PD_HEADER_SOP(sop)
-		| PD_HEADER(type, prole, drole, 0, cnt, PD_REV30, 0));
+	rx_emsg[PORT0].header =
+		(PD_HEADER_SOP(sop) |
+		 PD_HEADER(type, prole, drole, 0, cnt, PD_REV30, 0));
 	rx_emsg[PORT0].len = cnt * 4;
 	*(uint32_t *)rx_emsg[PORT0].buf = data;
 	mock_prl_message_received(PORT0);
@@ -94,8 +95,8 @@ test_static int finish_src_discovery(int startup_cable_probes)
 		EC_SUCCESS, "%d");
 	mock_prl_message_sent(PORT0);
 	task_wait_event(10 * MSEC);
-	rx_message(TCPCI_MSG_SOP, PD_CTRL_NOT_SUPPORTED, 0,
-		   PD_ROLE_SINK, PD_ROLE_UFP, 0);
+	rx_message(TCPCI_MSG_SOP, PD_CTRL_NOT_SUPPORTED, 0, PD_ROLE_SINK,
+		   PD_ROLE_UFP, 0);
 
 	/* Expect GET_REVISION, reply NOT_SUPPORTED. */
 	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP,
@@ -103,29 +104,28 @@ test_static int finish_src_discovery(int startup_cable_probes)
 		EC_SUCCESS, "%d");
 	mock_prl_message_sent(PORT0);
 	task_wait_event(10 * MSEC);
-	rx_message(TCPCI_MSG_SOP, PD_CTRL_NOT_SUPPORTED, 0,
-		   PD_ROLE_SINK, PD_ROLE_UFP, 0);
+	rx_message(TCPCI_MSG_SOP, PD_CTRL_NOT_SUPPORTED, 0, PD_ROLE_SINK,
+		   PD_ROLE_UFP, 0);
 
 	/*
 	 * Cable identity discovery is attempted 6 times total. 1 was done
 	 * above, so expect 5 more now.
 	 */
 	for (i = startup_cable_probes; i < 6; i++) {
-		TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP_PRIME,
-						 0, PD_DATA_VENDOR_DEF,
-						 60 * MSEC),
+		TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP_PRIME, 0,
+						 PD_DATA_VENDOR_DEF, 60 * MSEC),
 			EC_SUCCESS, "%d");
 		mock_prl_report_error(PORT0, ERR_TCH_XMIT, TCPCI_MSG_SOP_PRIME);
 	}
 
 	/* Expect VENDOR_DEF for partner identity, reply NOT_SUPPORTED. */
-	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP,
-					 0, PD_DATA_VENDOR_DEF, 10 * MSEC),
+	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, 0,
+					 PD_DATA_VENDOR_DEF, 10 * MSEC),
 		EC_SUCCESS, "%d");
 	mock_prl_message_sent(PORT0);
 	task_wait_event(10 * MSEC);
-	rx_message(TCPCI_MSG_SOP, PD_CTRL_NOT_SUPPORTED, 0,
-		   PD_ROLE_SINK, PD_ROLE_UFP, 0);
+	rx_message(TCPCI_MSG_SOP, PD_CTRL_NOT_SUPPORTED, 0, PD_ROLE_SINK,
+		   PD_ROLE_UFP, 0);
 
 	return EC_SUCCESS;
 }
@@ -140,8 +140,8 @@ test_static int test_send_caps_error_before_connected(void)
 	mock_tc_port[PORT0].power_role = PD_ROLE_SOURCE;
 	mock_tc_port[PORT0].pd_enable = 1;
 	mock_tc_port[PORT0].vconn_src = true;
-	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP,
-					 0, PD_DATA_SOURCE_CAP, 10 * MSEC),
+	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, 0,
+					 PD_DATA_SOURCE_CAP, 10 * MSEC),
 		EC_SUCCESS, "%d");
 
 	/*
@@ -155,8 +155,8 @@ test_static int test_send_caps_error_before_connected(void)
 	 * We should have gone to PE_SRC_Discovery on above error, so expect
 	 * VENDOR_DEF for cable identity, simulate no cable.
 	 */
-	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP_PRIME,
-					 0, PD_DATA_VENDOR_DEF, 10 * MSEC),
+	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP_PRIME, 0,
+					 PD_DATA_VENDOR_DEF, 10 * MSEC),
 		EC_SUCCESS, "%d");
 	mock_prl_report_error(PORT0, ERR_TCH_XMIT, TCPCI_MSG_SOP_PRIME);
 
@@ -164,8 +164,8 @@ test_static int test_send_caps_error_before_connected(void)
 	 * Expect SOURCE_CAP again. This is a retry since the first one above
 	 * got ERR_TCH_XMIT. Now simulate success (ie GoodCRC).
 	 */
-	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP,
-					 0, PD_DATA_SOURCE_CAP, 110 * MSEC),
+	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, 0,
+					 PD_DATA_SOURCE_CAP, 110 * MSEC),
 		EC_SUCCESS, "%d");
 	mock_prl_message_sent(PORT0);
 	task_wait_event(10 * MSEC);
@@ -179,14 +179,14 @@ test_static int test_send_caps_error_before_connected(void)
 	 */
 
 	/* REQUEST 5V, expect ACCEPT, PS_RDY. */
-	rx_message(TCPCI_MSG_SOP, 0, PD_DATA_REQUEST,
-		   PD_ROLE_SINK, PD_ROLE_UFP, RDO_FIXED(1, 500, 500, 0));
-	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP,
-					 PD_CTRL_ACCEPT, 0, 10 * MSEC),
+	rx_message(TCPCI_MSG_SOP, 0, PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
+		   RDO_FIXED(1, 500, 500, 0));
+	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, PD_CTRL_ACCEPT,
+					 0, 10 * MSEC),
 		EC_SUCCESS, "%d");
 	mock_prl_message_sent(PORT0);
-	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP,
-					 PD_CTRL_PS_RDY, 0, 35 * MSEC),
+	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, PD_CTRL_PS_RDY,
+					 0, 35 * MSEC),
 		EC_SUCCESS, "%d");
 	mock_prl_message_sent(PORT0);
 
@@ -207,21 +207,21 @@ test_static int test_send_caps_error_when_connected(void)
 	mock_tc_port[PORT0].power_role = PD_ROLE_SOURCE;
 	mock_tc_port[PORT0].pd_enable = 1;
 	mock_tc_port[PORT0].vconn_src = true;
-	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP,
-					 0, PD_DATA_SOURCE_CAP, 10 * MSEC),
+	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, 0,
+					 PD_DATA_SOURCE_CAP, 10 * MSEC),
 		EC_SUCCESS, "%d");
 	mock_prl_message_sent(PORT0);
 	task_wait_event(10 * MSEC);
 
 	/* REQUEST 5V, expect ACCEPT, PS_RDY. */
-	rx_message(TCPCI_MSG_SOP, 0, PD_DATA_REQUEST,
-		   PD_ROLE_SINK, PD_ROLE_UFP, RDO_FIXED(1, 500, 500, 0));
-	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP,
-					 PD_CTRL_ACCEPT, 0, 10 * MSEC),
+	rx_message(TCPCI_MSG_SOP, 0, PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
+		   RDO_FIXED(1, 500, 500, 0));
+	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, PD_CTRL_ACCEPT,
+					 0, 10 * MSEC),
 		EC_SUCCESS, "%d");
 	mock_prl_message_sent(PORT0);
-	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP,
-					 PD_CTRL_PS_RDY, 0, 35 * MSEC),
+	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, PD_CTRL_PS_RDY,
+					 0, 35 * MSEC),
 		EC_SUCCESS, "%d");
 	mock_prl_message_sent(PORT0);
 
@@ -233,10 +233,10 @@ test_static int test_send_caps_error_when_connected(void)
 	 * Now connected. Send GET_SOURCE_CAP, to check how error sending
 	 * SOURCE_CAP is handled.
 	 */
-	rx_message(TCPCI_MSG_SOP, PD_CTRL_GET_SOURCE_CAP, 0,
-		   PD_ROLE_SINK, PD_ROLE_UFP, 0);
-	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP,
-					 0, PD_DATA_SOURCE_CAP, 10 * MSEC),
+	rx_message(TCPCI_MSG_SOP, PD_CTRL_GET_SOURCE_CAP, 0, PD_ROLE_SINK,
+		   PD_ROLE_UFP, 0);
+	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, 0,
+					 PD_DATA_SOURCE_CAP, 10 * MSEC),
 		EC_SUCCESS, "%d");
 
 	/* Simulate error sending SOURCE_CAP. */
@@ -269,21 +269,21 @@ test_static int test_interrupting_pr_swap(void)
 	mock_tc_port[PORT0].power_role = PD_ROLE_SOURCE;
 	mock_tc_port[PORT0].pd_enable = 1;
 	mock_tc_port[PORT0].vconn_src = true;
-	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP,
-					 0, PD_DATA_SOURCE_CAP, 10 * MSEC),
+	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, 0,
+					 PD_DATA_SOURCE_CAP, 10 * MSEC),
 		EC_SUCCESS, "%d");
 	mock_prl_message_sent(PORT0);
 	task_wait_event(10 * MSEC);
 
 	/* REQUEST 5V, expect ACCEPT, PS_RDY. */
-	rx_message(TCPCI_MSG_SOP, 0, PD_DATA_REQUEST,
-		   PD_ROLE_SINK, PD_ROLE_UFP, RDO_FIXED(1, 500, 500, 0));
-	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP,
-					 PD_CTRL_ACCEPT, 0, 10 * MSEC),
+	rx_message(TCPCI_MSG_SOP, 0, PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP,
+		   RDO_FIXED(1, 500, 500, 0));
+	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, PD_CTRL_ACCEPT,
+					 0, 10 * MSEC),
 		EC_SUCCESS, "%d");
 	mock_prl_message_sent(PORT0);
-	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP,
-					 PD_CTRL_PS_RDY, 0, 35 * MSEC),
+	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, PD_CTRL_PS_RDY,
+					 0, 35 * MSEC),
 		EC_SUCCESS, "%d");
 	mock_prl_message_sent(PORT0);
 
@@ -295,32 +295,32 @@ test_static int test_interrupting_pr_swap(void)
 	 * Now connected.  Initiate a PR swap and then interrupt it after the
 	 * Accept, when power is transitioning to off.
 	 */
-	rx_message(TCPCI_MSG_SOP, PD_CTRL_PR_SWAP, 0,
-		   PD_ROLE_SINK, PD_ROLE_UFP, 0);
+	rx_message(TCPCI_MSG_SOP, PD_CTRL_PR_SWAP, 0, PD_ROLE_SINK, PD_ROLE_UFP,
+		   0);
 
-	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP,
-					 PD_CTRL_ACCEPT, 0, 10 * MSEC),
+	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, PD_CTRL_ACCEPT,
+					 0, 10 * MSEC),
 		EC_SUCCESS, "%d");
 	mock_prl_message_sent(PORT0);
 
 	task_wait_event(5 * SECOND);
 
 	/* Interrupt the non-interruptible AMS */
-	rx_message(TCPCI_MSG_SOP, PD_CTRL_PR_SWAP, 0,
-		   PD_ROLE_SINK, PD_ROLE_UFP, 0);
+	rx_message(TCPCI_MSG_SOP, PD_CTRL_PR_SWAP, 0, PD_ROLE_SINK, PD_ROLE_UFP,
+		   0);
 
 	/*
 	 * Expect a hard reset since power was transitioning during this
 	 * interruption
 	 */
-	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_TX_HARD_RESET,
-					 0, 0, 10 * MSEC),
+	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_TX_HARD_RESET, 0, 0,
+					 10 * MSEC),
 		EC_SUCCESS, "%d");
 
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/usb_pe_drp.mocklist b/test/usb_pe_drp.mocklist
index b8879415d8..633b43d48d 100644
--- a/test/usb_pe_drp.mocklist
+++ b/test/usb_pe_drp.mocklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/usb_pe_drp.tasklist b/test/usb_pe_drp.tasklist
index eb41326e3e..5c7f804157 100644
--- a/test/usb_pe_drp.tasklist
+++ b/test/usb_pe_drp.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/usb_pe_drp_noextended.c b/test/usb_pe_drp_noextended.c
index 68da7426e2..6108458c9c 100644
--- a/test/usb_pe_drp_noextended.c
+++ b/test/usb_pe_drp_noextended.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -24,18 +24,19 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.driver = &mock_usb_mux_driver,
-	}
-};
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { {
+	.mux =
+		&(const struct usb_mux){
+			.driver = &mock_usb_mux_driver,
+		},
+} };
 
 void before_test(void)
 {
 	mock_tc_port_reset();
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/usb_pe_drp_noextended.tasklist b/test/usb_pe_drp_noextended.tasklist
index eb41326e3e..5c7f804157 100644
--- a/test/usb_pe_drp_noextended.tasklist
+++ b/test/usb_pe_drp_noextended.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/usb_pe_drp_old.c b/test/usb_pe_drp_old.c
index 1954ae065b..0985a4cae9 100644
--- a/test/usb_pe_drp_old.c
+++ b/test/usb_pe_drp_old.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -21,9 +21,9 @@
 #include "usb_tc_sm.h"
 #include "mock/usb_prl_mock.h"
 
-#define pe_set_flag(_p, name) pe_set_fn((_p), (name ## _FN))
-#define pe_clr_flag(_p, name) pe_clr_fn((_p), (name ## _FN))
-#define pe_chk_flag(_p, name) pe_chk_fn((_p), (name ## _FN))
+#define pe_set_flag(_p, name) pe_set_fn((_p), (name##_FN))
+#define pe_clr_flag(_p, name) pe_clr_fn((_p), (name##_FN))
+#define pe_chk_flag(_p, name) pe_chk_fn((_p), (name##_FN))
 
 /**
  * STUB Section
@@ -35,7 +35,7 @@ const struct svdm_response svdm_rsp = {
 };
 
 const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT];
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT];
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 static bool prl_is_busy_flag;
 
@@ -77,12 +77,10 @@ bool pd_alt_mode_capable(int port)
 
 void pd_set_suspend(int port, int suspend)
 {
-
 }
 
 void pd_set_error_recovery(int port)
 {
-
 }
 
 test_static void setup_source(void)
@@ -219,8 +217,8 @@ static int test_snk_give_source_cap(void)
 
 	TEST_ASSERT(!pe_chk_flag(PORT0, PE_FLAGS_MSG_RECEIVED));
 	TEST_ASSERT(!pe_chk_flag(PORT0, PE_FLAGS_TX_COMPLETE));
-	TEST_EQ(mock_prl_get_last_sent_data_msg(PORT0),
-		PD_DATA_SOURCE_CAP, "%d");
+	TEST_EQ(mock_prl_get_last_sent_data_msg(PORT0), PD_DATA_SOURCE_CAP,
+		"%d");
 	TEST_EQ(get_state_pe(PORT0), PE_DR_SNK_GIVE_SOURCE_CAP, "%d");
 
 	pe_set_flag(PORT0, PE_FLAGS_TX_COMPLETE);
@@ -249,9 +247,9 @@ test_static int test_extended_message_not_supported(void)
 	 * Receive an extended, non-chunked message; expect a Not Supported
 	 * response.
 	 */
-	rx_emsg[PORT0].header = PD_HEADER(
-			PD_DATA_BATTERY_STATUS, PD_ROLE_SINK, PD_ROLE_UFP, 0,
-			PDO_MAX_OBJECTS, PD_REV30, 1);
+	rx_emsg[PORT0].header = PD_HEADER(PD_DATA_BATTERY_STATUS, PD_ROLE_SINK,
+					  PD_ROLE_UFP, 0, PDO_MAX_OBJECTS,
+					  PD_REV30, 1);
 	*(uint16_t *)rx_emsg[PORT0].buf =
 		PD_EXT_HEADER(0, 0, ARRAY_SIZE(rx_emsg[PORT0].buf)) & ~BIT(15);
 	pe_set_flag(PORT0, PE_FLAGS_MSG_RECEIVED);
@@ -261,16 +259,16 @@ test_static int test_extended_message_not_supported(void)
 	pe_set_flag(PORT0, PE_FLAGS_TX_COMPLETE);
 	task_wait_event(10 * MSEC);
 	TEST_EQ(mock_prl_get_last_sent_ctrl_msg(PORT0), PD_CTRL_NOT_SUPPORTED,
-			"%d");
+		"%d");
 	/* At this point, the PE should again be running in PE_SRC_Ready. */
 
 	/*
 	 * Receive an extended, chunked, single-chunk message; expect a Not
 	 * Supported response.
 	 */
-	rx_emsg[PORT0].header = PD_HEADER(
-			PD_DATA_BATTERY_STATUS, PD_ROLE_SINK, PD_ROLE_UFP, 0,
-			PDO_MAX_OBJECTS, PD_REV30, 1);
+	rx_emsg[PORT0].header = PD_HEADER(PD_DATA_BATTERY_STATUS, PD_ROLE_SINK,
+					  PD_ROLE_UFP, 0, PDO_MAX_OBJECTS,
+					  PD_REV30, 1);
 	*(uint16_t *)rx_emsg[PORT0].buf =
 		PD_EXT_HEADER(0, 0, PD_MAX_EXTENDED_MSG_CHUNK_LEN);
 	pe_set_flag(PORT0, PE_FLAGS_MSG_RECEIVED);
@@ -280,16 +278,16 @@ test_static int test_extended_message_not_supported(void)
 	pe_set_flag(PORT0, PE_FLAGS_TX_COMPLETE);
 	task_wait_event(10 * MSEC);
 	TEST_EQ(mock_prl_get_last_sent_ctrl_msg(PORT0), PD_CTRL_NOT_SUPPORTED,
-			"%d");
+		"%d");
 	/* At this point, the PE should again be running in PE_SRC_Ready. */
 
 	/*
 	 * Receive an extended, chunked, multi-chunk message; expect a Not
 	 * Supported response after tChunkingNotSupported (not earlier).
 	 */
-	rx_emsg[PORT0].header = PD_HEADER(
-			PD_DATA_BATTERY_STATUS, PD_ROLE_SINK, PD_ROLE_UFP, 0,
-			PDO_MAX_OBJECTS, PD_REV30, 1);
+	rx_emsg[PORT0].header = PD_HEADER(PD_DATA_BATTERY_STATUS, PD_ROLE_SINK,
+					  PD_ROLE_UFP, 0, PDO_MAX_OBJECTS,
+					  PD_REV30, 1);
 	*(uint16_t *)rx_emsg[PORT0].buf =
 		PD_EXT_HEADER(0, 0, ARRAY_SIZE(rx_emsg[PORT0].buf));
 	pe_set_flag(PORT0, PE_FLAGS_MSG_RECEIVED);
@@ -301,13 +299,13 @@ test_static int test_extended_message_not_supported(void)
 	 */
 	task_wait_event(10 * MSEC);
 	TEST_NE(mock_prl_get_last_sent_ctrl_msg(PORT0), PD_CTRL_NOT_SUPPORTED,
-			"%d");
+		"%d");
 
 	task_wait_event(PD_T_CHUNKING_NOT_SUPPORTED);
 	pe_set_flag(PORT0, PE_FLAGS_TX_COMPLETE);
 	task_wait_event(10 * MSEC);
 	TEST_EQ(mock_prl_get_last_sent_ctrl_msg(PORT0), PD_CTRL_NOT_SUPPORTED,
-			"%d");
+		"%d");
 	/* At this point, the PE should again be running in PE_SRC_Ready. */
 
 	/*
@@ -408,14 +406,14 @@ static int test_send_caps_error(void)
 	pe_set_flag(PORT0, PE_FLAGS_PD_CONNECTION);
 	set_state_pe(PORT0, PE_SRC_SEND_CAPABILITIES);
 	task_wait_event(10 * MSEC);
-	TEST_EQ(mock_prl_get_last_sent_ctrl_msg(PORT0),
-		PD_CTRL_SOFT_RESET, "%d");
+	TEST_EQ(mock_prl_get_last_sent_ctrl_msg(PORT0), PD_CTRL_SOFT_RESET,
+		"%d");
 	TEST_EQ(get_state_pe(PORT0), PE_SEND_SOFT_RESET, "%d");
 
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/usb_pe_drp_old.mocklist b/test/usb_pe_drp_old.mocklist
index 0582e5cbb3..118cec69a0 100644
--- a/test/usb_pe_drp_old.mocklist
+++ b/test/usb_pe_drp_old.mocklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/usb_pe_drp_old.tasklist b/test/usb_pe_drp_old.tasklist
index eb41326e3e..5c7f804157 100644
--- a/test/usb_pe_drp_old.tasklist
+++ b/test/usb_pe_drp_old.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/usb_pe_drp_old_noextended.c b/test/usb_pe_drp_old_noextended.c
index cefd77b7d2..43df6375b0 100644
--- a/test/usb_pe_drp_old_noextended.c
+++ b/test/usb_pe_drp_old_noextended.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -27,7 +27,7 @@ const struct svdm_response svdm_rsp = {
 };
 
 const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT];
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT];
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT];
 
 int board_vbus_source_enabled(int port)
 {
@@ -62,12 +62,10 @@ bool pd_alt_mode_capable(int port)
 
 void pd_set_suspend(int port, int suspend)
 {
-
 }
 
 void pd_set_error_recovery(int port)
 {
-
 }
 
 test_static void setup_source(void)
@@ -198,8 +196,8 @@ static int test_snk_give_source_cap(void)
 
 	TEST_ASSERT(!pe_chk_flag(PORT0, PE_FLAGS_MSG_RECEIVED));
 	TEST_ASSERT(!pe_chk_flag(PORT0, PE_FLAGS_TX_COMPLETE));
-	TEST_EQ(fake_prl_get_last_sent_data_msg_type(PORT0),
-		PD_DATA_SOURCE_CAP, "%d");
+	TEST_EQ(fake_prl_get_last_sent_data_msg_type(PORT0), PD_DATA_SOURCE_CAP,
+		"%d");
 	TEST_EQ(get_state_pe(PORT0), PE_DR_SNK_GIVE_SOURCE_CAP, "%d");
 
 	pe_set_flag(PORT0, PE_FLAGS_TX_COMPLETE);
@@ -228,9 +226,9 @@ test_static int test_extended_message_not_supported(void)
 	 * Receive an extended, non-chunked message; expect a Not Supported
 	 * response.
 	 */
-	rx_emsg[PORT0].header = PD_HEADER(
-			PD_DATA_BATTERY_STATUS, PD_ROLE_SINK, PD_ROLE_UFP, 0,
-			PDO_MAX_OBJECTS, PD_REV30, 1);
+	rx_emsg[PORT0].header = PD_HEADER(PD_DATA_BATTERY_STATUS, PD_ROLE_SINK,
+					  PD_ROLE_UFP, 0, PDO_MAX_OBJECTS,
+					  PD_REV30, 1);
 	*(uint16_t *)rx_emsg[PORT0].buf =
 		PD_EXT_HEADER(0, 0, ARRAY_SIZE(rx_emsg[PORT0].buf)) & ~BIT(15);
 	pe_set_flag(PORT0, PE_FLAGS_MSG_RECEIVED);
@@ -240,16 +238,16 @@ test_static int test_extended_message_not_supported(void)
 	pe_set_flag(PORT0, PE_FLAGS_TX_COMPLETE);
 	task_wait_event(10 * MSEC);
 	TEST_EQ(fake_prl_get_last_sent_ctrl_msg(PORT0), PD_CTRL_NOT_SUPPORTED,
-			"%d");
+		"%d");
 	/* At this point, the PE should again be running in PE_SRC_Ready. */
 
 	/*
 	 * Receive an extended, chunked, single-chunk message; expect a Not
 	 * Supported response.
 	 */
-	rx_emsg[PORT0].header = PD_HEADER(
-			PD_DATA_BATTERY_STATUS, PD_ROLE_SINK, PD_ROLE_UFP, 0,
-			PDO_MAX_OBJECTS, PD_REV30, 1);
+	rx_emsg[PORT0].header = PD_HEADER(PD_DATA_BATTERY_STATUS, PD_ROLE_SINK,
+					  PD_ROLE_UFP, 0, PDO_MAX_OBJECTS,
+					  PD_REV30, 1);
 	*(uint16_t *)rx_emsg[PORT0].buf =
 		PD_EXT_HEADER(0, 0, PD_MAX_EXTENDED_MSG_CHUNK_LEN);
 	pe_set_flag(PORT0, PE_FLAGS_MSG_RECEIVED);
@@ -259,16 +257,16 @@ test_static int test_extended_message_not_supported(void)
 	pe_set_flag(PORT0, PE_FLAGS_TX_COMPLETE);
 	task_wait_event(10 * MSEC);
 	TEST_EQ(fake_prl_get_last_sent_ctrl_msg(PORT0), PD_CTRL_NOT_SUPPORTED,
-			"%d");
+		"%d");
 	/* At this point, the PE should again be running in PE_SRC_Ready. */
 
 	/*
 	 * Receive an extended, chunked, multi-chunk message; expect a Not
 	 * Supported response after tChunkingNotSupported (not earlier).
 	 */
-	rx_emsg[PORT0].header = PD_HEADER(
-			PD_DATA_BATTERY_STATUS, PD_ROLE_SINK, PD_ROLE_UFP, 0,
-			PDO_MAX_OBJECTS, PD_REV30, 1);
+	rx_emsg[PORT0].header = PD_HEADER(PD_DATA_BATTERY_STATUS, PD_ROLE_SINK,
+					  PD_ROLE_UFP, 0, PDO_MAX_OBJECTS,
+					  PD_REV30, 1);
 	*(uint16_t *)rx_emsg[PORT0].buf =
 		PD_EXT_HEADER(0, 0, ARRAY_SIZE(rx_emsg[PORT0].buf));
 	pe_set_flag(PORT0, PE_FLAGS_MSG_RECEIVED);
@@ -280,13 +278,13 @@ test_static int test_extended_message_not_supported(void)
 	 */
 	task_wait_event(10 * MSEC);
 	TEST_NE(fake_prl_get_last_sent_ctrl_msg(PORT0), PD_CTRL_NOT_SUPPORTED,
-			"%d");
+		"%d");
 
 	task_wait_event(PD_T_CHUNKING_NOT_SUPPORTED);
 	pe_set_flag(PORT0, PE_FLAGS_TX_COMPLETE);
 	task_wait_event(10 * MSEC);
 	TEST_EQ(fake_prl_get_last_sent_ctrl_msg(PORT0), PD_CTRL_NOT_SUPPORTED,
-			"%d");
+		"%d");
 	/* At this point, the PE should again be running in PE_SRC_Ready. */
 
 	/*
@@ -337,14 +335,14 @@ static int test_send_caps_error(void)
 	pe_set_flag(PORT0, PE_FLAGS_PD_CONNECTION);
 	set_state_pe(PORT0, PE_SRC_SEND_CAPABILITIES);
 	task_wait_event(10 * MSEC);
-	TEST_EQ(fake_prl_get_last_sent_ctrl_msg(PORT0),
-		PD_CTRL_SOFT_RESET, "%d");
+	TEST_EQ(fake_prl_get_last_sent_ctrl_msg(PORT0), PD_CTRL_SOFT_RESET,
+		"%d");
 	TEST_EQ(get_state_pe(PORT0), PE_SEND_SOFT_RESET, "%d");
 
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/usb_pe_drp_old_noextended.mocklist b/test/usb_pe_drp_old_noextended.mocklist
index 0582e5cbb3..118cec69a0 100644
--- a/test/usb_pe_drp_old_noextended.mocklist
+++ b/test/usb_pe_drp_old_noextended.mocklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/usb_pe_drp_old_noextended.tasklist b/test/usb_pe_drp_old_noextended.tasklist
index eb41326e3e..5c7f804157 100644
--- a/test/usb_pe_drp_old_noextended.tasklist
+++ b/test/usb_pe_drp_old_noextended.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/usb_ppc.c b/test/usb_ppc.c
index 0cf6f69bf3..d08ae47946 100644
--- a/test/usb_ppc.c
+++ b/test/usb_ppc.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -28,15 +28,12 @@ const struct ppc_drv null_drv = {
 };
 
 struct ppc_config_t ppc_chips[] = {
-	[0] = {
-		.drv = &null_drv
-	},
+	[0] = { .drv = &null_drv },
 };
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
 const struct tcpc_config_t tcpc_config[] = {
-	[0] = {
-	},
+	[0] = {},
 };
 
 static int test_ppc_init(void)
@@ -171,9 +168,7 @@ static int test_ppc_is_vbus_present(void)
 	return EC_SUCCESS;
 }
 
-
-
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/usb_ppc.tasklist b/test/usb_ppc.tasklist
index 9fc1a80f4d..844ddb6c10 100644
--- a/test/usb_ppc.tasklist
+++ b/test/usb_ppc.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/usb_prl.c b/test/usb_prl.c
index 3ef3450649..9b4c956649 100644
--- a/test/usb_prl.c
+++ b/test/usb_prl.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -34,14 +34,14 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 
 static enum pd_power_role get_partner_power_role(int port)
 {
-	return pd_get_power_role(port) == PD_ROLE_SINK ?
-				PD_ROLE_SOURCE : PD_ROLE_SINK;
+	return pd_get_power_role(port) == PD_ROLE_SINK ? PD_ROLE_SOURCE :
+							 PD_ROLE_SINK;
 }
 
 static enum pd_data_role get_partner_data_role(int port)
 {
-	return pd_get_data_role(port) == PD_ROLE_UFP ?
-				PD_ROLE_DFP : PD_ROLE_UFP;
+	return pd_get_data_role(port) == PD_ROLE_UFP ? PD_ROLE_DFP :
+						       PD_ROLE_UFP;
 }
 
 static void enable_prl(int port, int en)
@@ -50,7 +50,7 @@ static void enable_prl(int port, int en)
 
 	mock_tc_port[port].pd_enable = en;
 
-	task_wait_event(10*MSEC);
+	task_wait_event(10 * MSEC);
 
 	prl_set_rev(port, TCPCI_MSG_SOP, mock_tc_port[port].rev);
 }
@@ -59,16 +59,16 @@ static int test_receive_control_msg(void)
 {
 	int port = PORT0;
 	uint16_t header = PD_HEADER(PD_CTRL_DR_SWAP,
-		get_partner_power_role(port),
-		get_partner_data_role(port),
-		mock_tc_port[port].msg_rx_id,
-		0, mock_tc_port[port].rev, 0);
+				    get_partner_power_role(port),
+				    get_partner_data_role(port),
+				    mock_tc_port[port].msg_rx_id, 0,
+				    mock_tc_port[port].rev, 0);
 
 	/* Set up the message to be received. */
 	mock_tcpm_rx_msg(port, header, 0, NULL);
 
 	/* Process the message. */
-	task_wait_event(10*MSEC);
+	task_wait_event(10 * MSEC);
 
 	/* Check results. */
 	TEST_NE(mock_pe_port[port].mock_pe_message_received, 0, "%d");
@@ -94,7 +94,7 @@ static int test_send_control_msg(void)
 	/* Simulate the TX complete that the PD_INT handler would signal */
 	pd_transmit_complete(port, TCPC_TX_COMPLETE_SUCCESS);
 
-	task_wait_event(10*MSEC);
+	task_wait_event(10 * MSEC);
 
 	/* Check results. */
 	TEST_NE(mock_pe_port[port].mock_pe_message_sent, 0, "%d");
@@ -111,16 +111,16 @@ static int test_discard_queued_tx_when_rx_happens(void)
 {
 	int port = PORT0;
 	uint16_t header = PD_HEADER(PD_CTRL_DR_SWAP,
-		get_partner_power_role(port),
-		get_partner_data_role(port),
-		mock_tc_port[port].msg_rx_id,
-		0, mock_tc_port[port].rev, 0);
+				    get_partner_power_role(port),
+				    get_partner_data_role(port),
+				    mock_tc_port[port].msg_rx_id, 0,
+				    mock_tc_port[port].rev, 0);
 	uint8_t *buf = tx_emsg[port].buf;
 	uint8_t len = 8;
 	uint8_t i = 0;
 
 	/* Set up the message to be sent. */
-	for (i = 0 ; i < len ; i++)
+	for (i = 0; i < len; i++)
 		buf[i] = (uint8_t)i;
 
 	tx_emsg[port].len = len;
@@ -130,7 +130,7 @@ static int test_discard_queued_tx_when_rx_happens(void)
 	mock_tcpm_rx_msg(port, header, 0, NULL);
 
 	/* Process the message. */
-	task_wait_event(10*MSEC);
+	task_wait_event(10 * MSEC);
 
 	/* Check results. Source should have discarded its message queued up
 	 * to TX, and should have received the message from the sink.
@@ -166,14 +166,13 @@ void after_test(void)
 	enable_prl(PORT0, 0);
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	RUN_TEST(test_receive_control_msg);
 	RUN_TEST(test_send_control_msg);
 	RUN_TEST(test_discard_queued_tx_when_rx_happens);
 	/* TODO add tests here */
 
-
 	/* Do basic state machine validity checks last. */
 	RUN_TEST(test_prl_no_parent_cycles);
 	RUN_TEST(test_prl_all_states_named);
diff --git a/test/usb_prl.mocklist b/test/usb_prl.mocklist
index bf5357334a..7a5af3392e 100644
--- a/test/usb_prl.mocklist
+++ b/test/usb_prl.mocklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/usb_prl.tasklist b/test/usb_prl.tasklist
index eb41326e3e..5c7f804157 100644
--- a/test/usb_prl.tasklist
+++ b/test/usb_prl.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/usb_prl_noextended.c b/test/usb_prl_noextended.c
index a47c01a13e..956c0027f5 120000..100644
--- a/test/usb_prl_noextended.c
+++ b/test/usb_prl_noextended.c
@@ -1 +1,1347 @@
-usb_prl_old.c
\ No newline at end of file
+/* Copyright 2019 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Test USB Protocol Layer module.
+ */
+#include "common.h"
+#include "crc.h"
+#include "task.h"
+#include "tcpm/tcpm.h"
+#include "test_util.h"
+#include "timer.h"
+#include "usb_emsg.h"
+#include "usb_pd_test_util.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "usb_pe_sm.h"
+#include "usb_prl_sm.h"
+#include "usb_sm_checks.h"
+#include "usb_tc_sm.h"
+#include "util.h"
+
+#define PORT0 0
+
+/*
+ * These enum definitions are declared in usb_prl_sm and are private to that
+ * file. If those definitions are re-ordered, then we need to update these
+ * definitions (should be very rare).
+ */
+enum usb_prl_tx_state {
+	PRL_TX_PHY_LAYER_RESET,
+	PRL_TX_WAIT_FOR_MESSAGE_REQUEST,
+	PRL_TX_LAYER_RESET_FOR_TRANSMIT,
+	PRL_TX_WAIT_FOR_PHY_RESPONSE,
+	PRL_TX_SRC_SOURCE_TX,
+	PRL_TX_SNK_START_AMS,
+	PRL_TX_SRC_PENDING,
+	PRL_TX_SNK_PENDING,
+	PRL_TX_DISCARD_MESSAGE,
+};
+
+enum usb_prl_hr_state {
+	PRL_HR_WAIT_FOR_REQUEST,
+	PRL_HR_RESET_LAYER,
+	PRL_HR_WAIT_FOR_PHY_HARD_RESET_COMPLETE,
+	PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE,
+};
+
+enum usb_rch_state {
+	RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER,
+	RCH_PASS_UP_MESSAGE,
+	RCH_PROCESSING_EXTENDED_MESSAGE,
+	RCH_REQUESTING_CHUNK,
+	RCH_WAITING_CHUNK,
+	RCH_REPORT_ERROR,
+};
+
+enum usb_tch_state {
+	TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE,
+	TCH_WAIT_FOR_TRANSMISSION_COMPLETE,
+	TCH_CONSTRUCT_CHUNKED_MESSAGE,
+	TCH_SENDING_CHUNKED_MESSAGE,
+	TCH_WAIT_CHUNK_REQUEST,
+	TCH_MESSAGE_RECEIVED,
+	TCH_MESSAGE_SENT,
+	TCH_REPORT_ERROR,
+};
+
+/* Defined in implementation */
+enum usb_prl_tx_state prl_tx_get_state(const int port);
+enum usb_prl_hr_state prl_hr_get_state(const int port);
+enum usb_rch_state rch_get_state(const int port);
+enum usb_tch_state tch_get_state(const int port);
+
+#ifndef CONFIG_USB_PD_EXTENDED_MESSAGES
+enum usb_rch_state rch_get_state(const int port)
+{
+	return RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER;
+}
+#endif
+
+static uint32_t test_data[] = {
+	0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617,
+	0x1819a0b0, 0xc0d0e0f0, 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f,
+	0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f, 0x40414243, 0x44454647,
+	0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f,
+	0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677,
+	0x78797a7b, 0x7c7d7e7f, 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f,
+	0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f, 0xa0a1a2a3, 0xa4a5a6a7,
+	0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf,
+	0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7,
+	0xd8d9dadb, 0xdcdddedf, 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef,
+	0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff, 0x11223344
+};
+
+void pd_set_suspend(int port, int suspend)
+{
+}
+
+void pd_set_error_recovery(int port)
+{
+}
+
+static enum pd_power_role get_partner_power_role(int port);
+static enum pd_data_role get_partner_data_role(int port);
+
+static struct pd_prl {
+	int rev;
+	int pd_enable;
+	enum pd_power_role power_role;
+	enum pd_data_role data_role;
+	int msg_tx_id;
+	int msg_rx_id;
+	enum tcpci_msg_type sop;
+
+	int mock_pe_message_sent;
+	int mock_pe_error;
+	int mock_pe_hard_reset_sent;
+	int mock_pe_got_hard_reset;
+	int mock_pe_message_received;
+	int mock_got_soft_reset;
+	int mock_message_discard;
+} pd_port[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+static void init_port(int port, int rev)
+{
+	pd_port[port].rev = rev;
+	pd_port[port].pd_enable = 0;
+	pd_port[port].power_role = PD_ROLE_SINK;
+	pd_port[port].data_role = PD_ROLE_UFP;
+	pd_port[port].msg_tx_id = 0;
+	pd_port[port].msg_rx_id = 0;
+
+	tcpm_init(port);
+	tcpm_set_polarity(port, 0);
+	tcpm_set_rx_enable(port, 0);
+}
+
+static inline uint32_t pending_pd_task_events(int port)
+{
+	return *task_get_event_bitmap(PD_PORT_TO_TASK_ID(port));
+}
+
+void inc_tx_id(int port)
+{
+	pd_port[port].msg_tx_id = (pd_port[port].msg_tx_id + 1) & 7;
+}
+
+void inc_rx_id(int port)
+{
+	pd_port[port].msg_rx_id = (pd_port[port].msg_rx_id + 1) % 7;
+}
+
+static int verify_goodcrc(int port, int role, int id)
+{
+	return pd_test_tx_msg_verify_sop(port) &&
+	       pd_test_tx_msg_verify_short(port,
+					   PD_HEADER(PD_CTRL_GOOD_CRC, role,
+						     role, id, 0, 0, 0)) &&
+	       pd_test_tx_msg_verify_crc(port) &&
+	       pd_test_tx_msg_verify_eop(port);
+}
+
+static void simulate_rx_msg(int port, uint16_t header, int cnt,
+			    const uint32_t *data)
+{
+	int i;
+
+	pd_test_rx_set_preamble(port, 1);
+	pd_test_rx_msg_append_sop(port);
+	pd_test_rx_msg_append_short(port, header);
+
+	crc32_init();
+	crc32_hash16(header);
+
+	for (i = 0; i < cnt; ++i) {
+		pd_test_rx_msg_append_word(port, data[i]);
+		crc32_hash32(data[i]);
+	}
+
+	pd_test_rx_msg_append_word(port, crc32_result());
+
+	pd_test_rx_msg_append_eop(port);
+	pd_test_rx_msg_append_last_edge(port);
+
+	pd_simulate_rx(port);
+}
+
+static void simulate_goodcrc(int port, int role, int id)
+{
+	simulate_rx_msg(port,
+			PD_HEADER(PD_CTRL_GOOD_CRC, role, role, id, 0,
+				  pd_port[port].rev, 0),
+			0, NULL);
+}
+
+static void cycle_through_state_machine(int port, uint32_t num, uint32_t time)
+{
+	int i;
+
+	for (i = 0; i < num; i++) {
+		task_wake(PD_PORT_TO_TASK_ID(port));
+		task_wait_event(time);
+	}
+}
+
+static int simulate_request_chunk(int port, enum pd_ext_msg_type msg_type,
+				  int chunk_num, int len)
+{
+	uint16_t header = PD_HEADER(msg_type, get_partner_power_role(port),
+				    get_partner_data_role(port),
+				    pd_port[port].msg_rx_id, 1,
+				    pd_port[port].rev, 1);
+	uint32_t msg = PD_EXT_HEADER(chunk_num, 1, len);
+
+	simulate_rx_msg(port, header, 1, (const uint32_t *)&msg);
+	task_wait_event(30 * MSEC);
+
+	if (!verify_goodcrc(port, pd_port[port].data_role,
+			    pd_port[port].msg_rx_id))
+		return 0;
+
+	return 1;
+}
+
+static int simulate_receive_ctrl_msg(int port, enum pd_ctrl_msg_type msg_type)
+{
+	uint16_t header = PD_HEADER(msg_type, get_partner_power_role(port),
+				    get_partner_data_role(port),
+				    pd_port[port].msg_rx_id, 0,
+				    pd_port[port].rev, 0);
+
+	simulate_rx_msg(port, header, 0, NULL);
+	task_wait_event(30 * MSEC);
+
+	if (!verify_goodcrc(port, pd_port[port].data_role,
+			    pd_port[port].msg_rx_id))
+		return 0;
+
+	return 1;
+}
+
+static int verify_data_reception(int port, uint16_t header, int len)
+{
+	int i;
+	int cnt = (len + 3) & ~3;
+
+	cycle_through_state_machine(port, 3, 10 * MSEC);
+
+	if (pd_port[port].mock_pe_error >= 0)
+		return 0;
+
+	if (!pd_port[port].mock_pe_message_received)
+		return 0;
+
+	if (rx_emsg[port].header != header)
+		return 0;
+
+	if (rx_emsg[port].len != cnt)
+		return 0;
+
+	for (i = 0; i < cnt; i++) {
+		if (i < len) {
+			if (rx_emsg[port].buf[i] !=
+			    *((unsigned char *)test_data + i))
+				return 0;
+		} else {
+			if (rx_emsg[port].buf[i] != 0)
+				return 0;
+		}
+	}
+
+	return 1;
+}
+
+static int verify_chunk_data_reception(int port, uint16_t header, int len)
+{
+	int i;
+	uint8_t *td = (uint8_t *)test_data;
+
+	if (pd_port[port].mock_got_soft_reset) {
+		ccprintf("Got mock soft reset\n");
+		return 0;
+	}
+
+	if (!pd_port[port].mock_pe_message_received) {
+		ccprintf("No mock pe msg received\n");
+		return 0;
+	}
+
+	if (pd_port[port].mock_pe_error >= 0) {
+		ccprintf("Mock pe error (%d)\n", pd_port[port].mock_pe_error);
+		return 0;
+	}
+
+	if (rx_emsg[port].len != len) {
+		ccprintf("emsg len (%d) != 0\n", rx_emsg[port].len);
+		return 0;
+	}
+
+	for (i = 0; i < len; i++) {
+		if (rx_emsg[port].buf[i] != td[i]) {
+			ccprintf("emsg buf[%d] != td\n", i);
+			return 0;
+		}
+	}
+
+	return 1;
+}
+
+static int simulate_receive_data(int port, enum pd_data_msg_type msg_type,
+				 int len)
+{
+	int i;
+	int nw = (len + 3) >> 2;
+	uint8_t td[28];
+	uint16_t header = PD_HEADER(msg_type, get_partner_power_role(port),
+				    get_partner_data_role(port),
+				    pd_port[port].msg_rx_id, nw,
+				    pd_port[port].rev, 0);
+
+	pd_port[port].mock_pe_error = -1;
+	pd_port[port].mock_pe_message_received = 0;
+	rx_emsg[port].header = 0;
+	rx_emsg[port].len = 0;
+	memset(rx_emsg[port].buf, 0, ARRAY_SIZE(rx_emsg[port].buf));
+
+	for (i = 0; i < 28; i++) {
+		if (i < len)
+			td[i] = *((uint8_t *)test_data + i);
+		else
+			td[i] = 0;
+	}
+
+	simulate_rx_msg(port, header, nw, (uint32_t *)td);
+	task_wait_event(30 * MSEC);
+
+	if (!verify_goodcrc(port, pd_port[port].data_role,
+			    pd_port[port].msg_rx_id))
+		return 0;
+
+	inc_rx_id(port);
+
+	return verify_data_reception(port, header, len);
+}
+
+static int simulate_receive_extended_data(int port,
+					  enum pd_data_msg_type msg_type,
+					  int len)
+{
+	int i;
+	int j;
+	int byte_len;
+	int nw;
+	int dsize;
+	uint8_t td[28];
+	int chunk_num = 0;
+	int data_offset = 0;
+	uint8_t *expected_data = (uint8_t *)test_data;
+	uint16_t header;
+
+	pd_port[port].mock_pe_error = -1;
+	pd_port[port].mock_pe_message_received = 0;
+	rx_emsg[port].header = 0;
+	rx_emsg[port].len = 0;
+	memset(rx_emsg[port].buf, 0, ARRAY_SIZE(rx_emsg[port].buf));
+
+	dsize = len;
+	for (j = 0; j < 10; j++) {
+		/* Let state machine settle before starting another round */
+		cycle_through_state_machine(port, 10, MSEC);
+
+		byte_len = len;
+		if (byte_len > PD_MAX_EXTENDED_MSG_CHUNK_LEN)
+			byte_len = PD_MAX_EXTENDED_MSG_CHUNK_LEN;
+
+		len -= PD_MAX_EXTENDED_MSG_CHUNK_LEN;
+
+		memset(td, 0, 28);
+		*(uint16_t *)td = PD_EXT_HEADER(chunk_num, 0, dsize);
+
+		for (i = 0; i < byte_len; i++)
+			td[i + 2] = *(expected_data + data_offset++);
+
+		nw = (byte_len + 2 + 3) >> 2;
+		header = PD_HEADER(msg_type, get_partner_power_role(port),
+				   get_partner_data_role(port),
+				   pd_port[port].msg_rx_id, nw,
+				   pd_port[port].rev, 1);
+
+		if (pd_port[port].mock_pe_error >= 0) {
+			ccprintf("Mock pe error (%d) iteration (%d)\n",
+				 pd_port[port].mock_pe_error, j);
+			return 0;
+		}
+
+		if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES) &&
+		    pd_port[port].mock_pe_message_received) {
+			ccprintf("Mock pe msg received iteration (%d)\n", j);
+			return 0;
+		}
+
+		if (rx_emsg[port].len != 0) {
+			ccprintf("emsg len (%d) != 0 iteration (%d)\n",
+				 rx_emsg[port].len, j);
+			return 0;
+		}
+
+		simulate_rx_msg(port, header, nw, (uint32_t *)td);
+		cycle_through_state_machine(port, 1, MSEC);
+
+		if (!verify_goodcrc(port, pd_port[port].data_role,
+				    pd_port[port].msg_rx_id)) {
+			ccprintf("Verify goodcrc bad iteration (%d)\n", j);
+			return 0;
+		}
+
+		cycle_through_state_machine(port, 1, MSEC);
+		inc_rx_id(port);
+
+		if (!IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES)) {
+			if (pd_port[port].mock_pe_message_received)
+				return 1;
+			return 0;
+		}
+
+		/*
+		 * If no more data, do expected to get a chunk request
+		 */
+		if (len <= 0)
+			break;
+
+		/*
+		 * We need to ensure that the TX event has been set, which may
+		 * require an extra cycle through the state machine
+		 */
+		if (!(PD_EVENT_TX & pending_pd_task_events(port)))
+			cycle_through_state_machine(port, 1, MSEC);
+
+		chunk_num++;
+
+		/* Test Request next chunk packet */
+		if (!pd_test_tx_msg_verify_sop(port)) {
+			ccprintf("Verify sop bad iteration (%d)\n", j);
+			return 0;
+		}
+
+		if (!pd_test_tx_msg_verify_short(
+			    port, PD_HEADER(msg_type, pd_port[port].power_role,
+					    pd_port[port].data_role,
+					    pd_port[port].msg_tx_id, 1,
+					    pd_port[port].rev, 1))) {
+			ccprintf("Verify msg short bad iteration (%d)\n", j);
+			return 0;
+		}
+
+		if (!pd_test_tx_msg_verify_word(port, PD_EXT_HEADER(chunk_num,
+								    1, 0))) {
+			ccprintf("Verify msg word bad iteration (%d)\n", j);
+			return 0;
+		}
+
+		if (!pd_test_tx_msg_verify_crc(port)) {
+			ccprintf("Verify msg crc bad iteration (%d)\n", j);
+			return 0;
+		}
+
+		if (!pd_test_tx_msg_verify_eop(port)) {
+			ccprintf("Verify msg eop bad iteration (%d)\n", j);
+			return 0;
+		}
+
+		cycle_through_state_machine(port, 1, MSEC);
+
+		/* Request next chunk packet was good. Send GoodCRC */
+		simulate_goodcrc(port, get_partner_power_role(port),
+				 pd_port[port].msg_tx_id);
+
+		cycle_through_state_machine(port, 1, MSEC);
+
+		inc_tx_id(port);
+	}
+
+	cycle_through_state_machine(port, 1, MSEC);
+
+	return verify_chunk_data_reception(port, header, dsize);
+}
+
+static int verify_ctrl_msg_transmission(int port,
+					enum pd_ctrl_msg_type msg_type)
+{
+	if (!pd_test_tx_msg_verify_sop(port))
+		return 0;
+
+	if (!pd_test_tx_msg_verify_short(
+		    port,
+		    PD_HEADER(msg_type, pd_port[port].power_role,
+			      pd_port[port].data_role, pd_port[port].msg_tx_id,
+			      0, pd_port[port].rev, 0)))
+		return 0;
+
+	if (!pd_test_tx_msg_verify_crc(port))
+		return 0;
+
+	if (!pd_test_tx_msg_verify_eop(port))
+		return 0;
+
+	return 1;
+}
+
+static int
+simulate_send_ctrl_msg_request_from_pe(int port, enum tcpci_msg_type type,
+				       enum pd_ctrl_msg_type msg_type)
+{
+	pd_port[port].mock_got_soft_reset = 0;
+	pd_port[port].mock_pe_error = -1;
+	pd_port[port].mock_pe_message_sent = 0;
+	prl_send_ctrl_msg(port, type, msg_type);
+	cycle_through_state_machine(port, 1, MSEC);
+
+	return verify_ctrl_msg_transmission(port, msg_type);
+}
+
+static int verify_data_msg_transmission(int port,
+					enum pd_data_msg_type msg_type, int len)
+{
+	int i;
+	int num_words = (len + 3) >> 2;
+	int data_obj_in_bytes;
+	uint32_t td;
+
+	if (!pd_test_tx_msg_verify_sop(port))
+		return 0;
+
+	if (!pd_test_tx_msg_verify_short(
+		    port,
+		    PD_HEADER(msg_type, pd_port[port].power_role,
+			      pd_port[port].data_role, pd_port[port].msg_tx_id,
+			      num_words, pd_port[port].rev, 0)))
+		return 0;
+
+	for (i = 0; i < num_words; i++) {
+		td = test_data[i];
+		data_obj_in_bytes = (i + 1) * 4;
+		if (data_obj_in_bytes > len) {
+			switch (data_obj_in_bytes - len) {
+			case 1:
+				td &= 0x00ffffff;
+				break;
+			case 2:
+				td &= 0x0000ffff;
+				break;
+			case 3:
+				td &= 0x000000ff;
+				break;
+			}
+		}
+
+		if (!pd_test_tx_msg_verify_word(port, td))
+			return 0;
+	}
+
+	if (!pd_test_tx_msg_verify_crc(port))
+		return 0;
+
+	if (!pd_test_tx_msg_verify_eop(port))
+		return 0;
+
+	return 1;
+}
+
+static int
+simulate_send_data_msg_request_from_pe(int port, enum tcpci_msg_type type,
+				       enum pd_data_msg_type msg_type, int len)
+{
+	int i;
+	uint8_t *buf = tx_emsg[port].buf;
+	uint8_t *td = (uint8_t *)test_data;
+
+	pd_port[port].mock_got_soft_reset = 0;
+	pd_port[port].mock_pe_error = -1;
+	pd_port[port].mock_pe_message_sent = 0;
+
+	for (i = 0; i < len; i++)
+		buf[i] = td[i];
+
+	tx_emsg[port].len = len;
+
+	prl_send_data_msg(port, type, msg_type);
+	cycle_through_state_machine(port, 1, MSEC);
+
+	return verify_data_msg_transmission(port, msg_type, len);
+}
+
+static int verify_extended_data_msg_transmission(int port,
+						 enum pd_ext_msg_type msg_type,
+						 int len)
+{
+	int i;
+	int j;
+	int nw;
+	int byte_len;
+	int dsize;
+	uint32_t td;
+	uint8_t *expected_data = (uint8_t *)&test_data;
+	int data_offset = 0;
+	int chunk_number_to_send = 0;
+
+	dsize = len;
+
+	for (j = 0; j < 10; j++) {
+		byte_len = len;
+		if (byte_len > PD_MAX_EXTENDED_MSG_CHUNK_LEN)
+			byte_len = PD_MAX_EXTENDED_MSG_CHUNK_LEN;
+
+		nw = (byte_len + 2 + 3) >> 2;
+
+		if (!pd_test_tx_msg_verify_sop(port)) {
+			ccprintf("failed tx sop; iteration (%d)\n", j);
+			return 0;
+		}
+
+		if (!pd_test_tx_msg_verify_short(
+			    port, PD_HEADER(msg_type, pd_port[port].power_role,
+					    pd_port[port].data_role,
+					    pd_port[port].msg_tx_id, nw,
+					    pd_port[port].rev, 1))) {
+			ccprintf("failed tx short\n");
+			return 0;
+		}
+		td = PD_EXT_HEADER(chunk_number_to_send, 0, dsize);
+		td |= *(expected_data + data_offset++) << 16;
+		td |= *(expected_data + data_offset++) << 24;
+
+		if (byte_len == 1)
+			td &= 0x00ffffff;
+
+		if (!pd_test_tx_msg_verify_word(port, td)) {
+			ccprintf("failed tx word\n");
+			return 0;
+		}
+
+		byte_len -= 2;
+
+		if (byte_len > 0) {
+			nw = (byte_len + 3) >> 2;
+			for (i = 0; i < nw; i++) {
+				td = *(expected_data + data_offset++) << 0;
+				td |= *(expected_data + data_offset++) << 8;
+				td |= *(expected_data + data_offset++) << 16;
+				td |= *(expected_data + data_offset++) << 24;
+
+				switch (byte_len) {
+				case 3:
+					td &= 0x00ffffff;
+					break;
+				case 2:
+					td &= 0x0000ffff;
+					break;
+				case 1:
+					td &= 0x000000ff;
+					break;
+				}
+
+				if (!pd_test_tx_msg_verify_word(port, td))
+					return 0;
+				byte_len -= 4;
+			}
+		}
+
+		if (!pd_test_tx_msg_verify_crc(port)) {
+			ccprintf("failed tx crc\n");
+			return 0;
+		}
+
+		if (!pd_test_tx_msg_verify_eop(port)) {
+			ccprintf("failed tx eop\n");
+			return 0;
+		}
+
+		cycle_through_state_machine(port, 1, MSEC);
+
+		/* Send GoodCRC */
+		simulate_goodcrc(port, get_partner_power_role(port),
+				 pd_port[port].msg_tx_id);
+		cycle_through_state_machine(port, 1, MSEC);
+		inc_tx_id(port);
+
+		len -= PD_MAX_EXTENDED_MSG_CHUNK_LEN;
+		if (len <= 0)
+			break;
+
+		chunk_number_to_send++;
+		/* Let state machine settle */
+		cycle_through_state_machine(port, 10, MSEC);
+		if (!simulate_request_chunk(port, msg_type,
+					    chunk_number_to_send, dsize)) {
+			ccprintf("failed request chunk\n");
+			return 0;
+		}
+
+		cycle_through_state_machine(port, 1, MSEC);
+		inc_rx_id(port);
+	}
+
+	return 1;
+}
+
+static int simulate_send_extended_data_msg(int port, enum tcpci_msg_type type,
+					   enum pd_ext_msg_type msg_type,
+					   int len)
+{
+	int i;
+	uint8_t *buf = tx_emsg[port].buf;
+	uint8_t *td = (uint8_t *)test_data;
+
+	memset(buf, 0, ARRAY_SIZE(tx_emsg[port].buf));
+	tx_emsg[port].len = len;
+
+	/* don't overflow buffer */
+	if (len > ARRAY_SIZE(tx_emsg[port].buf))
+		len = ARRAY_SIZE(tx_emsg[port].buf);
+
+	for (i = 0; i < len; i++)
+		buf[i] = td[i];
+
+	prl_send_ext_data_msg(port, type, msg_type);
+	cycle_through_state_machine(port, 1, MSEC);
+
+	return verify_extended_data_msg_transmission(port, msg_type, len);
+}
+
+uint8_t tc_get_pd_enabled(int port)
+{
+	return pd_port[port].pd_enable;
+}
+
+static void enable_prl(int port, int en)
+{
+	tcpm_set_rx_enable(port, en);
+
+	pd_port[port].pd_enable = en;
+	pd_port[port].msg_tx_id = 0;
+	pd_port[port].msg_rx_id = 0;
+
+	/* Init PRL */
+	cycle_through_state_machine(port, 10, MSEC);
+
+	prl_set_rev(port, TCPCI_MSG_SOP, pd_port[port].rev);
+}
+
+enum pd_power_role pd_get_power_role(int port)
+{
+	return pd_port[port].power_role;
+}
+
+static enum pd_power_role get_partner_power_role(int port)
+{
+	return pd_port[port].power_role == PD_ROLE_SINK ? PD_ROLE_SOURCE :
+							  PD_ROLE_SINK;
+}
+
+enum pd_data_role pd_get_data_role(int port)
+{
+	return pd_port[port].data_role;
+}
+
+static enum pd_data_role get_partner_data_role(int port)
+{
+	return pd_port[port].data_role == PD_ROLE_UFP ? PD_ROLE_DFP :
+							PD_ROLE_UFP;
+}
+
+enum pd_cable_plug tc_get_cable_plug(int port)
+{
+	return PD_PLUG_FROM_DFP_UFP;
+}
+
+void pe_report_error(int port, enum pe_error e, enum tcpci_msg_type type)
+{
+	pd_port[port].mock_pe_error = e;
+	pd_port[port].sop = type;
+}
+
+void pe_report_discard(int port)
+{
+	pd_port[port].mock_message_discard = 1;
+}
+
+void pe_got_hard_reset(int port)
+{
+	pd_port[port].mock_pe_got_hard_reset = 1;
+}
+
+void pe_message_received(int port)
+{
+	pd_port[port].mock_pe_message_received = 1;
+}
+
+void pe_message_sent(int port)
+{
+	pd_port[port].mock_pe_message_sent = 1;
+}
+
+void pe_hard_reset_sent(int port)
+{
+	pd_port[port].mock_pe_hard_reset_sent = 1;
+}
+
+void pe_got_soft_reset(int port)
+{
+	pd_port[port].mock_got_soft_reset = 1;
+}
+
+bool pe_in_frs_mode(int port)
+{
+	return false;
+}
+
+bool pe_in_local_ams(int port)
+{
+	/* We will probably want to change this in the future */
+	return false;
+}
+
+static int test_prl_reset(void)
+{
+	int port = PORT0;
+
+	enable_prl(port, 1);
+
+	prl_reset_soft(port);
+
+	TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u");
+	TEST_EQ(rch_get_state(port), RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER,
+		"%u");
+	TEST_EQ(tch_get_state(port), TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE,
+		"%u");
+	TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_REQUEST, "%u");
+	enable_prl(port, 0);
+
+	return EC_SUCCESS;
+}
+
+static int test_send_ctrl_msg(void)
+{
+	int i;
+	int port = PORT0;
+
+	enable_prl(port, 1);
+
+	/*
+	 * TEST: Control message transmission and tx_id increment
+	 */
+	for (i = 0; i < 10; i++) {
+		task_wake(PD_PORT_TO_TASK_ID(port));
+		task_wait_event(40 * MSEC);
+
+		TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST,
+			"%u");
+
+		TEST_NE(simulate_send_ctrl_msg_request_from_pe(
+				port, TCPCI_MSG_SOP, PD_CTRL_ACCEPT),
+			0, "%d");
+
+		cycle_through_state_machine(port, 1, MSEC);
+
+		simulate_goodcrc(port, get_partner_power_role(port),
+				 pd_port[port].msg_tx_id);
+		inc_tx_id(port);
+
+		/* Let statemachine settle */
+		cycle_through_state_machine(port, 10, MSEC);
+
+		TEST_EQ(pd_port[port].mock_got_soft_reset, 0, "%d");
+		TEST_NE(pd_port[port].mock_pe_message_sent, 0, "%d");
+		TEST_LE(pd_port[port].mock_pe_error, 0, "%d");
+	}
+
+	enable_prl(port, 0);
+
+	return EC_SUCCESS;
+}
+
+static int test_send_data_msg(void)
+{
+	int i;
+	int port = PORT0;
+
+	enable_prl(port, 1);
+
+	/*
+	 * TEST: Sending data  message with 1 to 28 bytes
+	 */
+	for (i = 1; i <= 28; i++) {
+		cycle_through_state_machine(port, 1, MSEC);
+
+		TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST,
+			"%u");
+
+		TEST_NE(simulate_send_data_msg_request_from_pe(
+				port, TCPCI_MSG_SOP, PD_DATA_SOURCE_CAP, i),
+			0, "%d");
+
+		cycle_through_state_machine(port, 1, MSEC);
+
+		simulate_goodcrc(port, get_partner_power_role(port),
+				 pd_port[port].msg_tx_id);
+		inc_tx_id(port);
+
+		cycle_through_state_machine(port, 10, MSEC);
+
+		TEST_EQ(pd_port[port].mock_got_soft_reset, 0, "%d");
+		TEST_NE(pd_port[port].mock_pe_message_sent, 0, "%d");
+		TEST_LE(pd_port[port].mock_pe_error, 0, "%d");
+	}
+
+	enable_prl(port, 0);
+
+	return EC_SUCCESS;
+}
+
+static int test_send_data_msg_to_much_data(void)
+{
+	int port = PORT0;
+
+	enable_prl(port, 1);
+
+	/*
+	 * TEST: Send data message with more than 28-bytes, should fail
+	 */
+	task_wake(PD_PORT_TO_TASK_ID(port));
+	task_wait_event(40 * MSEC);
+
+	TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u");
+
+	/* Try to send 29-bytes */
+	TEST_EQ(simulate_send_data_msg_request_from_pe(port, TCPCI_MSG_SOP,
+						       PD_DATA_SOURCE_CAP, 29),
+		0, "%d");
+
+	task_wake(PD_PORT_TO_TASK_ID(port));
+	task_wait_event(30 * MSEC);
+
+	cycle_through_state_machine(port, 10, MSEC);
+
+	TEST_EQ(pd_port[port].mock_got_soft_reset, 0, "%d");
+	TEST_EQ(pd_port[port].mock_pe_message_sent, 0, "%d");
+	TEST_EQ(pd_port[port].mock_pe_error, ERR_TCH_XMIT, "%d");
+
+	enable_prl(port, 0);
+
+	return EC_SUCCESS;
+}
+
+static int test_send_extended_data_msg(void)
+{
+	int i;
+	int port = PORT0;
+
+	if (!IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES)) {
+		ccprints("CONFIG_USB_PD_EXTENDED_MESSAGES disabled; skipping");
+		return EC_SUCCESS;
+	}
+
+	enable_prl(port, 1);
+
+	/*
+	 * TEST: Sending extended data message with 29 to 260 bytes
+	 */
+
+	pd_port[port].mock_got_soft_reset = 0;
+	pd_port[port].mock_pe_error = -1;
+
+	ccprintf("Iteration ");
+	for (i = 29; i <= PD_MAX_EXTENDED_MSG_LEN; i++) {
+		ccprintf(".%d", i);
+		pd_port[port].mock_pe_message_sent = 0;
+
+		cycle_through_state_machine(port, 10, MSEC);
+
+		TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST,
+			"%d");
+
+		TEST_NE(simulate_send_extended_data_msg(
+				port, TCPCI_MSG_SOP, PD_EXT_MANUFACTURER_INFO,
+				i),
+			0, "%d");
+
+		cycle_through_state_machine(port, 10, MSEC);
+
+		TEST_EQ(pd_port[port].mock_got_soft_reset, 0, "%d");
+		TEST_NE(pd_port[port].mock_pe_message_sent, 0, "%d");
+		TEST_LE(pd_port[port].mock_pe_error, 0, "%d");
+	}
+	enable_prl(port, 0);
+
+	return EC_SUCCESS;
+}
+
+static int test_receive_soft_reset_msg(void)
+{
+	int port = PORT0;
+
+	enable_prl(port, 1);
+
+	/*
+	 * TEST: Receiving Soft Reset
+	 */
+
+	task_wake(PD_PORT_TO_TASK_ID(port));
+	task_wait_event(40 * MSEC);
+
+	TEST_EQ(rch_get_state(port), RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER,
+		"%u");
+
+	pd_port[port].mock_got_soft_reset = 0;
+	pd_port[port].mock_pe_error = -1;
+	pd_port[port].mock_pe_message_received = 0;
+
+	TEST_NE(simulate_receive_ctrl_msg(port, PD_CTRL_SOFT_RESET), 0, "%d");
+
+	task_wake(PD_PORT_TO_TASK_ID(port));
+	task_wait_event(30 * MSEC);
+
+	cycle_through_state_machine(port, 10, MSEC);
+
+	TEST_EQ(pd_port[port].mock_got_soft_reset, 1, "%d");
+	TEST_LE(pd_port[port].mock_pe_error, 0, "%d");
+	/*
+	 * We don't want to get  pe_got_soft_reset and pe_message_received, just
+	 * pe_got_soft_reset.
+	 */
+	TEST_EQ(pd_port[port].mock_pe_message_received, 0, "%d");
+
+	enable_prl(port, 0);
+
+	return EC_SUCCESS;
+}
+
+static int test_receive_control_msg(void)
+{
+	int port = PORT0;
+	int expected_header =
+		PD_HEADER(PD_CTRL_DR_SWAP, get_partner_power_role(port),
+			  get_partner_data_role(port), pd_port[port].msg_rx_id,
+			  0, pd_port[port].rev, 0);
+
+	enable_prl(port, 1);
+
+	/*
+	 * TEST: Receiving a control message
+	 */
+
+	task_wake(PD_PORT_TO_TASK_ID(port));
+	task_wait_event(40 * MSEC);
+
+	TEST_EQ(rch_get_state(port), RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER,
+		"%u");
+
+	pd_port[port].mock_got_soft_reset = 0;
+	pd_port[port].mock_pe_error = -1;
+	pd_port[port].mock_pe_message_received = 0;
+
+	TEST_NE(simulate_receive_ctrl_msg(port, PD_CTRL_DR_SWAP), 0, "%d");
+
+	task_wake(PD_PORT_TO_TASK_ID(port));
+	task_wait_event(30 * MSEC);
+
+	cycle_through_state_machine(port, 3, 10 * MSEC);
+
+	TEST_EQ(pd_port[port].mock_got_soft_reset, 0, "%d");
+	TEST_LE(pd_port[port].mock_pe_error, 0, "%d");
+	TEST_NE(pd_port[port].mock_pe_message_received, 0, "%d");
+	TEST_EQ(expected_header, rx_emsg[port].header, "%d");
+	TEST_EQ(rx_emsg[port].len, 0, "%d");
+
+	enable_prl(port, 0);
+
+	return EC_SUCCESS;
+}
+
+static int test_receive_data_msg(void)
+{
+	int port = PORT0;
+	int i;
+
+	enable_prl(port, 1);
+
+	/*
+	 * TEST: Receiving data message with 1 to 28 bytes
+	 */
+
+	for (i = 1; i <= 28; i++) {
+		task_wake(PD_PORT_TO_TASK_ID(port));
+		task_wait_event(40 * MSEC);
+
+		TEST_EQ(rch_get_state(port),
+			RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER, "%u");
+		TEST_NE(simulate_receive_data(port, PD_DATA_BATTERY_STATUS, i),
+			0, "%d");
+	}
+
+	enable_prl(port, 0);
+
+	return EC_SUCCESS;
+}
+
+static int test_receive_extended_data_msg(void)
+{
+	int len;
+	int port = PORT0;
+
+	enable_prl(port, 1);
+
+	if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES)) {
+		/*
+		 * TEST: Receiving extended data message with 29 to 260 bytes
+		 */
+
+		task_wake(PD_PORT_TO_TASK_ID(port));
+		task_wait_event(40 * MSEC);
+
+		TEST_EQ(rch_get_state(port),
+			RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER, "%u");
+
+		for (len = 29; len <= PD_MAX_EXTENDED_MSG_LEN; len++) {
+			TEST_NE(simulate_receive_extended_data(
+					port, PD_DATA_BATTERY_STATUS, len),
+				0, "%d");
+		}
+	} else {
+		/*
+		 * TEST: Receiving unsupported extended data message and then
+		 * subsequently receiving a support non-extended data message.
+		 */
+		task_wake(PD_PORT_TO_TASK_ID(port));
+		task_wait_event(40 * MSEC);
+		TEST_NE(simulate_receive_extended_data(
+				port, PD_DATA_BATTERY_STATUS, 29),
+			0, "%d");
+
+		task_wake(PD_PORT_TO_TASK_ID(port));
+		task_wait_event(40 * MSEC);
+		TEST_NE(simulate_receive_data(port, PD_DATA_BATTERY_STATUS, 28),
+			0, "%d");
+	}
+
+	enable_prl(port, 0);
+
+	return EC_SUCCESS;
+}
+
+static int test_send_soft_reset_msg(void)
+{
+	int port = PORT0;
+
+	enable_prl(port, 1);
+
+	/*
+	 * TEST: Send soft reset
+	 */
+
+	task_wake(PD_PORT_TO_TASK_ID(port));
+	task_wait_event(40 * MSEC);
+
+	TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u");
+
+	TEST_NE(simulate_send_ctrl_msg_request_from_pe(port, TCPCI_MSG_SOP,
+						       PD_CTRL_SOFT_RESET),
+		0, "%d");
+
+	task_wake(PD_PORT_TO_TASK_ID(port));
+	task_wait_event(30 * MSEC);
+
+	simulate_goodcrc(port, get_partner_power_role(port),
+			 pd_port[port].msg_tx_id);
+	inc_tx_id(port);
+
+	TEST_EQ(prl_tx_get_state(port), PRL_TX_LAYER_RESET_FOR_TRANSMIT, "%u");
+
+	cycle_through_state_machine(port, 3, 10 * MSEC);
+
+	TEST_EQ(pd_port[port].mock_got_soft_reset, 0, "%d");
+	TEST_NE(pd_port[port].mock_pe_message_sent, 0, "%d");
+	TEST_LE(pd_port[port].mock_pe_error, 0, "%d");
+
+	enable_prl(port, 0);
+
+	return EC_SUCCESS;
+}
+
+static int test_pe_execute_hard_reset_msg(void)
+{
+	int port = PORT0;
+
+	enable_prl(port, 1);
+
+	pd_port[port].mock_pe_hard_reset_sent = 0;
+
+	/*
+	 * TEST: Policy Engine initiated hard reset
+	 */
+
+	task_wake(PD_PORT_TO_TASK_ID(port));
+	task_wait_event(40 * MSEC);
+
+	TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_REQUEST, "%u");
+
+	/* Simulate receiving hard reset from policy engine */
+	prl_execute_hard_reset(port);
+
+	TEST_EQ(prl_hr_get_state(port), PRL_HR_RESET_LAYER, "%u");
+	TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u");
+
+	cycle_through_state_machine(port, 1, 10 * MSEC);
+
+	TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_PHY_HARD_RESET_COMPLETE,
+		"%u");
+
+	cycle_through_state_machine(port, 2, PD_T_PS_HARD_RESET);
+	TEST_NE(pd_port[port].mock_pe_hard_reset_sent, 0, "%d");
+
+	TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE,
+		"%u");
+
+	/* Simulate policy engine indicating that it is done hard reset */
+	prl_hard_reset_complete(port);
+
+	cycle_through_state_machine(port, 1, 10 * MSEC);
+
+	TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_REQUEST, "%u");
+
+	enable_prl(port, 0);
+
+	return EC_SUCCESS;
+}
+
+static int test_phy_execute_hard_reset_msg(void)
+{
+	int port = PORT0;
+
+	enable_prl(port, 1);
+
+	/*
+	 * TEST: Port partner initiated hard reset
+	 */
+
+	pd_port[port].mock_pe_got_hard_reset = 0;
+
+	task_wake(PD_PORT_TO_TASK_ID(port));
+	task_wait_event(40 * MSEC);
+
+	TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_REQUEST, "%u");
+
+	/* Simulate receiving hard reset from port partner */
+	pd_execute_hard_reset(port);
+
+	TEST_EQ(prl_hr_get_state(port), PRL_HR_RESET_LAYER, "%u");
+	TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u");
+
+	cycle_through_state_machine(port, 1, 10 * MSEC);
+
+	TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE,
+		"%u");
+
+	cycle_through_state_machine(port, 2, PD_T_PS_HARD_RESET);
+	TEST_NE(pd_port[port].mock_pe_got_hard_reset, 0, "%d");
+
+	TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE,
+		"%u");
+
+	/* Simulate policy engine indicating that it is done hard reset */
+	prl_hard_reset_complete(port);
+
+	cycle_through_state_machine(port, 1, 10 * MSEC);
+
+	TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_REQUEST, "%u");
+
+	enable_prl(port, 0);
+
+	return EC_SUCCESS;
+}
+
+/* Reset the state machine between each test */
+void before_test(void)
+{
+	/* This test relies on explicitly cycling through events manually */
+	tc_pause_event_loop(PORT0);
+
+	pd_port[PORT0].mock_pe_message_sent = 0;
+	pd_port[PORT0].mock_pe_error = -1;
+	pd_port[PORT0].mock_message_discard = 0;
+	pd_port[PORT0].mock_pe_hard_reset_sent = 0;
+	pd_port[PORT0].mock_pe_got_hard_reset = 0;
+	pd_port[PORT0].mock_pe_message_received = 0;
+	pd_port[PORT0].mock_got_soft_reset = 0;
+	pd_port[PORT0].pd_enable = false;
+	cycle_through_state_machine(PORT0, 10, MSEC);
+	pd_port[PORT0].pd_enable = true;
+	cycle_through_state_machine(PORT0, 10, MSEC);
+}
+
+void run_test(int argc, const char **argv)
+{
+	test_reset();
+
+	/* Test PD 2.0 Protocol */
+	init_port(PORT0, PD_REV20);
+	RUN_TEST(test_prl_reset);
+	RUN_TEST(test_send_ctrl_msg);
+	RUN_TEST(test_send_data_msg);
+	RUN_TEST(test_send_data_msg_to_much_data);
+	RUN_TEST(test_receive_control_msg);
+	RUN_TEST(test_receive_data_msg);
+	RUN_TEST(test_receive_soft_reset_msg);
+	RUN_TEST(test_send_soft_reset_msg);
+	RUN_TEST(test_pe_execute_hard_reset_msg);
+	RUN_TEST(test_phy_execute_hard_reset_msg);
+
+	/* TODO(shurst): More PD 2.0 Tests */
+
+	ccprints("Starting PD 3.0 tests");
+
+	/* Test PD 3.0 Protocol */
+	init_port(PORT0, PD_REV30);
+	RUN_TEST(test_prl_reset);
+	RUN_TEST(test_send_ctrl_msg);
+	RUN_TEST(test_send_data_msg);
+	RUN_TEST(test_send_data_msg_to_much_data);
+	RUN_TEST(test_send_extended_data_msg);
+	RUN_TEST(test_receive_control_msg);
+	RUN_TEST(test_receive_data_msg);
+	RUN_TEST(test_receive_extended_data_msg);
+	RUN_TEST(test_receive_soft_reset_msg);
+	RUN_TEST(test_send_soft_reset_msg);
+	RUN_TEST(test_pe_execute_hard_reset_msg);
+	RUN_TEST(test_phy_execute_hard_reset_msg);
+
+	/* TODO(shurst): More PD 3.0 Tests */
+
+	/* Do basic state machine validity checks last. */
+	RUN_TEST(test_prl_no_parent_cycles);
+	RUN_TEST(test_prl_all_states_named);
+
+	test_print_result();
+}
diff --git a/test/usb_prl_old.c b/test/usb_prl_old.c
index a6ae6acb0e..956c0027f5 100644
--- a/test/usb_prl_old.c
+++ b/test/usb_prl_old.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -79,25 +79,18 @@ enum usb_rch_state rch_get_state(const int port)
 }
 #endif
 
-
 static uint32_t test_data[] = {
-	0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f,
-	0x10111213, 0x14151617, 0x1819a0b0, 0xc0d0e0f0,
-	0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f,
-	0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f,
-	0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f,
-	0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f,
-	0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f,
-	0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f,
-	0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f,
-	0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f,
-	0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf,
-	0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf,
-	0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf,
-	0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf,
-	0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef,
-	0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff,
-	0x11223344
+	0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617,
+	0x1819a0b0, 0xc0d0e0f0, 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f,
+	0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f, 0x40414243, 0x44454647,
+	0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f,
+	0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677,
+	0x78797a7b, 0x7c7d7e7f, 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f,
+	0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f, 0xa0a1a2a3, 0xa4a5a6a7,
+	0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf,
+	0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7,
+	0xd8d9dadb, 0xdcdddedf, 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef,
+	0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff, 0x11223344
 };
 
 void pd_set_suspend(int port, int suspend)
@@ -161,14 +154,15 @@ void inc_rx_id(int port)
 static int verify_goodcrc(int port, int role, int id)
 {
 	return pd_test_tx_msg_verify_sop(port) &&
-		pd_test_tx_msg_verify_short(port, PD_HEADER(PD_CTRL_GOOD_CRC,
-				role, role, id, 0, 0, 0)) &&
-		pd_test_tx_msg_verify_crc(port) &&
-		pd_test_tx_msg_verify_eop(port);
+	       pd_test_tx_msg_verify_short(port,
+					   PD_HEADER(PD_CTRL_GOOD_CRC, role,
+						     role, id, 0, 0, 0)) &&
+	       pd_test_tx_msg_verify_crc(port) &&
+	       pd_test_tx_msg_verify_eop(port);
 }
 
 static void simulate_rx_msg(int port, uint16_t header, int cnt,
-							const uint32_t *data)
+			    const uint32_t *data)
 {
 	int i;
 
@@ -194,8 +188,10 @@ static void simulate_rx_msg(int port, uint16_t header, int cnt,
 
 static void simulate_goodcrc(int port, int role, int id)
 {
-	simulate_rx_msg(port, PD_HEADER(PD_CTRL_GOOD_CRC, role, role, id, 0,
-					pd_port[port].rev, 0), 0, NULL);
+	simulate_rx_msg(port,
+			PD_HEADER(PD_CTRL_GOOD_CRC, role, role, id, 0,
+				  pd_port[port].rev, 0),
+			0, NULL);
 }
 
 static void cycle_through_state_machine(int port, uint32_t num, uint32_t time)
@@ -209,19 +205,19 @@ static void cycle_through_state_machine(int port, uint32_t num, uint32_t time)
 }
 
 static int simulate_request_chunk(int port, enum pd_ext_msg_type msg_type,
-							int chunk_num, int len)
+				  int chunk_num, int len)
 {
 	uint16_t header = PD_HEADER(msg_type, get_partner_power_role(port),
-					get_partner_data_role(port),
-					pd_port[port].msg_rx_id,
-					1, pd_port[port].rev, 1);
+				    get_partner_data_role(port),
+				    pd_port[port].msg_rx_id, 1,
+				    pd_port[port].rev, 1);
 	uint32_t msg = PD_EXT_HEADER(chunk_num, 1, len);
 
 	simulate_rx_msg(port, header, 1, (const uint32_t *)&msg);
 	task_wait_event(30 * MSEC);
 
 	if (!verify_goodcrc(port, pd_port[port].data_role,
-						pd_port[port].msg_rx_id))
+			    pd_port[port].msg_rx_id))
 		return 0;
 
 	return 1;
@@ -230,14 +226,15 @@ static int simulate_request_chunk(int port, enum pd_ext_msg_type msg_type,
 static int simulate_receive_ctrl_msg(int port, enum pd_ctrl_msg_type msg_type)
 {
 	uint16_t header = PD_HEADER(msg_type, get_partner_power_role(port),
-			get_partner_data_role(port), pd_port[port].msg_rx_id,
-			0, pd_port[port].rev, 0);
+				    get_partner_data_role(port),
+				    pd_port[port].msg_rx_id, 0,
+				    pd_port[port].rev, 0);
 
 	simulate_rx_msg(port, header, 0, NULL);
 	task_wait_event(30 * MSEC);
 
 	if (!verify_goodcrc(port, pd_port[port].data_role,
-						pd_port[port].msg_rx_id))
+			    pd_port[port].msg_rx_id))
 		return 0;
 
 	return 1;
@@ -265,7 +262,7 @@ static int verify_data_reception(int port, uint16_t header, int len)
 	for (i = 0; i < cnt; i++) {
 		if (i < len) {
 			if (rx_emsg[port].buf[i] !=
-					*((unsigned char *)test_data + i))
+			    *((unsigned char *)test_data + i))
 				return 0;
 		} else {
 			if (rx_emsg[port].buf[i] != 0)
@@ -312,14 +309,15 @@ static int verify_chunk_data_reception(int port, uint16_t header, int len)
 }
 
 static int simulate_receive_data(int port, enum pd_data_msg_type msg_type,
-									int len)
+				 int len)
 {
 	int i;
 	int nw = (len + 3) >> 2;
 	uint8_t td[28];
 	uint16_t header = PD_HEADER(msg_type, get_partner_power_role(port),
-		get_partner_data_role(port), pd_port[port].msg_rx_id,
-		nw, pd_port[port].rev, 0);
+				    get_partner_data_role(port),
+				    pd_port[port].msg_rx_id, nw,
+				    pd_port[port].rev, 0);
 
 	pd_port[port].mock_pe_error = -1;
 	pd_port[port].mock_pe_message_received = 0;
@@ -338,7 +336,7 @@ static int simulate_receive_data(int port, enum pd_data_msg_type msg_type,
 	task_wait_event(30 * MSEC);
 
 	if (!verify_goodcrc(port, pd_port[port].data_role,
-						pd_port[port].msg_rx_id))
+			    pd_port[port].msg_rx_id))
 		return 0;
 
 	inc_rx_id(port);
@@ -347,7 +345,8 @@ static int simulate_receive_data(int port, enum pd_data_msg_type msg_type,
 }
 
 static int simulate_receive_extended_data(int port,
-					enum pd_data_msg_type msg_type, int len)
+					  enum pd_data_msg_type msg_type,
+					  int len)
 {
 	int i;
 	int j;
@@ -385,24 +384,25 @@ static int simulate_receive_extended_data(int port,
 
 		nw = (byte_len + 2 + 3) >> 2;
 		header = PD_HEADER(msg_type, get_partner_power_role(port),
-			get_partner_data_role(port), pd_port[port].msg_rx_id,
-			nw, pd_port[port].rev, 1);
+				   get_partner_data_role(port),
+				   pd_port[port].msg_rx_id, nw,
+				   pd_port[port].rev, 1);
 
 		if (pd_port[port].mock_pe_error >= 0) {
 			ccprintf("Mock pe error (%d) iteration (%d)\n",
-				pd_port[port].mock_pe_error, j);
+				 pd_port[port].mock_pe_error, j);
 			return 0;
 		}
 
 		if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES) &&
-				pd_port[port].mock_pe_message_received) {
+		    pd_port[port].mock_pe_message_received) {
 			ccprintf("Mock pe msg received iteration (%d)\n", j);
 			return 0;
 		}
 
 		if (rx_emsg[port].len != 0) {
 			ccprintf("emsg len (%d) != 0 iteration (%d)\n",
-				rx_emsg[port].len, j);
+				 rx_emsg[port].len, j);
 			return 0;
 		}
 
@@ -410,7 +410,7 @@ static int simulate_receive_extended_data(int port,
 		cycle_through_state_machine(port, 1, MSEC);
 
 		if (!verify_goodcrc(port, pd_port[port].data_role,
-						pd_port[port].msg_rx_id)) {
+				    pd_port[port].msg_rx_id)) {
 			ccprintf("Verify goodcrc bad iteration (%d)\n", j);
 			return 0;
 		}
@@ -445,18 +445,17 @@ static int simulate_receive_extended_data(int port,
 			return 0;
 		}
 
-		if (!pd_test_tx_msg_verify_short(port,
-				PD_HEADER(msg_type,
-				pd_port[port].power_role,
-				pd_port[port].data_role,
-				pd_port[port].msg_tx_id,
-				1, pd_port[port].rev, 1))) {
+		if (!pd_test_tx_msg_verify_short(
+			    port, PD_HEADER(msg_type, pd_port[port].power_role,
+					    pd_port[port].data_role,
+					    pd_port[port].msg_tx_id, 1,
+					    pd_port[port].rev, 1))) {
 			ccprintf("Verify msg short bad iteration (%d)\n", j);
 			return 0;
 		}
 
-		if (!pd_test_tx_msg_verify_word(port,
-				PD_EXT_HEADER(chunk_num, 1, 0))) {
+		if (!pd_test_tx_msg_verify_word(port, PD_EXT_HEADER(chunk_num,
+								    1, 0))) {
 			ccprintf("Verify msg word bad iteration (%d)\n", j);
 			return 0;
 		}
@@ -475,7 +474,7 @@ static int simulate_receive_extended_data(int port,
 
 		/* Request next chunk packet was good. Send GoodCRC */
 		simulate_goodcrc(port, get_partner_power_role(port),
-					pd_port[port].msg_tx_id);
+				 pd_port[port].msg_tx_id);
 
 		cycle_through_state_machine(port, 1, MSEC);
 
@@ -488,15 +487,16 @@ static int simulate_receive_extended_data(int port,
 }
 
 static int verify_ctrl_msg_transmission(int port,
-						enum pd_ctrl_msg_type msg_type)
+					enum pd_ctrl_msg_type msg_type)
 {
 	if (!pd_test_tx_msg_verify_sop(port))
 		return 0;
 
-	if (!pd_test_tx_msg_verify_short(port,
-			PD_HEADER(msg_type, pd_port[port].power_role,
-			pd_port[port].data_role, pd_port[port].msg_tx_id, 0,
-			pd_port[port].rev, 0)))
+	if (!pd_test_tx_msg_verify_short(
+		    port,
+		    PD_HEADER(msg_type, pd_port[port].power_role,
+			      pd_port[port].data_role, pd_port[port].msg_tx_id,
+			      0, pd_port[port].rev, 0)))
 		return 0;
 
 	if (!pd_test_tx_msg_verify_crc(port))
@@ -508,8 +508,9 @@ static int verify_ctrl_msg_transmission(int port,
 	return 1;
 }
 
-static int simulate_send_ctrl_msg_request_from_pe(int port,
-	enum tcpci_msg_type type, enum pd_ctrl_msg_type msg_type)
+static int
+simulate_send_ctrl_msg_request_from_pe(int port, enum tcpci_msg_type type,
+				       enum pd_ctrl_msg_type msg_type)
 {
 	pd_port[port].mock_got_soft_reset = 0;
 	pd_port[port].mock_pe_error = -1;
@@ -521,7 +522,7 @@ static int simulate_send_ctrl_msg_request_from_pe(int port,
 }
 
 static int verify_data_msg_transmission(int port,
-				enum pd_data_msg_type msg_type, int len)
+					enum pd_data_msg_type msg_type, int len)
 {
 	int i;
 	int num_words = (len + 3) >> 2;
@@ -531,10 +532,11 @@ static int verify_data_msg_transmission(int port,
 	if (!pd_test_tx_msg_verify_sop(port))
 		return 0;
 
-	if (!pd_test_tx_msg_verify_short(port,
-			PD_HEADER(msg_type, pd_port[port].power_role,
-			pd_port[port].data_role, pd_port[port].msg_tx_id,
-			num_words, pd_port[port].rev, 0)))
+	if (!pd_test_tx_msg_verify_short(
+		    port,
+		    PD_HEADER(msg_type, pd_port[port].power_role,
+			      pd_port[port].data_role, pd_port[port].msg_tx_id,
+			      num_words, pd_port[port].rev, 0)))
 		return 0;
 
 	for (i = 0; i < num_words; i++) {
@@ -567,8 +569,9 @@ static int verify_data_msg_transmission(int port,
 	return 1;
 }
 
-static int simulate_send_data_msg_request_from_pe(int port,
-	enum tcpci_msg_type type, enum pd_data_msg_type msg_type, int len)
+static int
+simulate_send_data_msg_request_from_pe(int port, enum tcpci_msg_type type,
+				       enum pd_data_msg_type msg_type, int len)
 {
 	int i;
 	uint8_t *buf = tx_emsg[port].buf;
@@ -590,7 +593,8 @@ static int simulate_send_data_msg_request_from_pe(int port,
 }
 
 static int verify_extended_data_msg_transmission(int port,
-			enum pd_ext_msg_type msg_type, int len)
+						 enum pd_ext_msg_type msg_type,
+						 int len)
 {
 	int i;
 	int j;
@@ -616,11 +620,11 @@ static int verify_extended_data_msg_transmission(int port,
 			return 0;
 		}
 
-		if (!pd_test_tx_msg_verify_short(port,
-				PD_HEADER(msg_type, pd_port[port].power_role,
-				pd_port[port].data_role,
-				pd_port[port].msg_tx_id,
-				nw, pd_port[port].rev, 1))) {
+		if (!pd_test_tx_msg_verify_short(
+			    port, PD_HEADER(msg_type, pd_port[port].power_role,
+					    pd_port[port].data_role,
+					    pd_port[port].msg_tx_id, nw,
+					    pd_port[port].rev, 1))) {
 			ccprintf("failed tx short\n");
 			return 0;
 		}
@@ -642,9 +646,9 @@ static int verify_extended_data_msg_transmission(int port,
 			nw = (byte_len + 3) >> 2;
 			for (i = 0; i < nw; i++) {
 				td = *(expected_data + data_offset++) << 0;
-				td |= *(expected_data +	data_offset++) << 8;
-				td |= *(expected_data +	data_offset++) << 16;
-				td |= *(expected_data +	data_offset++) << 24;
+				td |= *(expected_data + data_offset++) << 8;
+				td |= *(expected_data + data_offset++) << 16;
+				td |= *(expected_data + data_offset++) << 24;
 
 				switch (byte_len) {
 				case 3:
@@ -678,7 +682,7 @@ static int verify_extended_data_msg_transmission(int port,
 
 		/* Send GoodCRC */
 		simulate_goodcrc(port, get_partner_power_role(port),
-						pd_port[port].msg_tx_id);
+				 pd_port[port].msg_tx_id);
 		cycle_through_state_machine(port, 1, MSEC);
 		inc_tx_id(port);
 
@@ -690,7 +694,7 @@ static int verify_extended_data_msg_transmission(int port,
 		/* Let state machine settle */
 		cycle_through_state_machine(port, 10, MSEC);
 		if (!simulate_request_chunk(port, msg_type,
-				chunk_number_to_send, dsize)) {
+					    chunk_number_to_send, dsize)) {
 			ccprintf("failed request chunk\n");
 			return 0;
 		}
@@ -702,9 +706,9 @@ static int verify_extended_data_msg_transmission(int port,
 	return 1;
 }
 
-static int simulate_send_extended_data_msg(int port,
-		enum tcpci_msg_type type, enum pd_ext_msg_type msg_type,
-		int len)
+static int simulate_send_extended_data_msg(int port, enum tcpci_msg_type type,
+					   enum pd_ext_msg_type msg_type,
+					   int len)
 {
 	int i;
 	uint8_t *buf = tx_emsg[port].buf;
@@ -723,8 +727,7 @@ static int simulate_send_extended_data_msg(int port,
 	prl_send_ext_data_msg(port, type, msg_type);
 	cycle_through_state_machine(port, 1, MSEC);
 
-	return verify_extended_data_msg_transmission(port, msg_type,
-							len);
+	return verify_extended_data_msg_transmission(port, msg_type, len);
 }
 
 uint8_t tc_get_pd_enabled(int port)
@@ -753,8 +756,8 @@ enum pd_power_role pd_get_power_role(int port)
 
 static enum pd_power_role get_partner_power_role(int port)
 {
-	return pd_port[port].power_role == PD_ROLE_SINK ?
-				PD_ROLE_SOURCE : PD_ROLE_SINK;
+	return pd_port[port].power_role == PD_ROLE_SINK ? PD_ROLE_SOURCE :
+							  PD_ROLE_SINK;
 }
 
 enum pd_data_role pd_get_data_role(int port)
@@ -764,8 +767,8 @@ enum pd_data_role pd_get_data_role(int port)
 
 static enum pd_data_role get_partner_data_role(int port)
 {
-	return pd_port[port].data_role == PD_ROLE_UFP ?
-				PD_ROLE_DFP : PD_ROLE_UFP;
+	return pd_port[port].data_role == PD_ROLE_UFP ? PD_ROLE_DFP :
+							PD_ROLE_UFP;
 }
 
 enum pd_cable_plug tc_get_cable_plug(int port)
@@ -828,14 +831,12 @@ static int test_prl_reset(void)
 
 	prl_reset_soft(port);
 
-	TEST_EQ(prl_tx_get_state(port),
-			PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u");
-	TEST_EQ(rch_get_state(port),
-			RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER, "%u");
-	TEST_EQ(tch_get_state(port),
-			TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE, "%u");
-	TEST_EQ(prl_hr_get_state(port),
-			PRL_HR_WAIT_FOR_REQUEST, "%u");
+	TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u");
+	TEST_EQ(rch_get_state(port), RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER,
+		"%u");
+	TEST_EQ(tch_get_state(port), TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE,
+		"%u");
+	TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_REQUEST, "%u");
 	enable_prl(port, 0);
 
 	return EC_SUCCESS;
@@ -855,16 +856,17 @@ static int test_send_ctrl_msg(void)
 		task_wake(PD_PORT_TO_TASK_ID(port));
 		task_wait_event(40 * MSEC);
 
-		TEST_EQ(prl_tx_get_state(port),
-				PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u");
+		TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST,
+			"%u");
 
-		TEST_NE(simulate_send_ctrl_msg_request_from_pe(port,
-				TCPCI_MSG_SOP, PD_CTRL_ACCEPT), 0, "%d");
+		TEST_NE(simulate_send_ctrl_msg_request_from_pe(
+				port, TCPCI_MSG_SOP, PD_CTRL_ACCEPT),
+			0, "%d");
 
 		cycle_through_state_machine(port, 1, MSEC);
 
 		simulate_goodcrc(port, get_partner_power_role(port),
-						pd_port[port].msg_tx_id);
+				 pd_port[port].msg_tx_id);
 		inc_tx_id(port);
 
 		/* Let statemachine settle */
@@ -893,16 +895,17 @@ static int test_send_data_msg(void)
 	for (i = 1; i <= 28; i++) {
 		cycle_through_state_machine(port, 1, MSEC);
 
-		TEST_EQ(prl_tx_get_state(port),
-				PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u");
+		TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST,
+			"%u");
 
-		TEST_NE(simulate_send_data_msg_request_from_pe(port,
-				TCPCI_MSG_SOP, PD_DATA_SOURCE_CAP, i), 0, "%d");
+		TEST_NE(simulate_send_data_msg_request_from_pe(
+				port, TCPCI_MSG_SOP, PD_DATA_SOURCE_CAP, i),
+			0, "%d");
 
 		cycle_through_state_machine(port, 1, MSEC);
 
 		simulate_goodcrc(port, get_partner_power_role(port),
-						pd_port[port].msg_tx_id);
+				 pd_port[port].msg_tx_id);
 		inc_tx_id(port);
 
 		cycle_through_state_machine(port, 10, MSEC);
@@ -929,12 +932,12 @@ static int test_send_data_msg_to_much_data(void)
 	task_wake(PD_PORT_TO_TASK_ID(port));
 	task_wait_event(40 * MSEC);
 
-	TEST_EQ(prl_tx_get_state(port),
-			PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u");
+	TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u");
 
 	/* Try to send 29-bytes */
-	TEST_EQ(simulate_send_data_msg_request_from_pe(port,
-			TCPCI_MSG_SOP, PD_DATA_SOURCE_CAP, 29), 0, "%d");
+	TEST_EQ(simulate_send_data_msg_request_from_pe(port, TCPCI_MSG_SOP,
+						       PD_DATA_SOURCE_CAP, 29),
+		0, "%d");
 
 	task_wake(PD_PORT_TO_TASK_ID(port));
 	task_wait_event(30 * MSEC);
@@ -976,12 +979,13 @@ static int test_send_extended_data_msg(void)
 
 		cycle_through_state_machine(port, 10, MSEC);
 
-		TEST_EQ(prl_tx_get_state(port),
-				PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%d");
+		TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST,
+			"%d");
 
-		TEST_NE(simulate_send_extended_data_msg(port, TCPCI_MSG_SOP,
-					PD_EXT_MANUFACTURER_INFO, i),
-					0, "%d");
+		TEST_NE(simulate_send_extended_data_msg(
+				port, TCPCI_MSG_SOP, PD_EXT_MANUFACTURER_INFO,
+				i),
+			0, "%d");
 
 		cycle_through_state_machine(port, 10, MSEC);
 
@@ -1007,8 +1011,8 @@ static int test_receive_soft_reset_msg(void)
 	task_wake(PD_PORT_TO_TASK_ID(port));
 	task_wait_event(40 * MSEC);
 
-	TEST_EQ(rch_get_state(port),
-			RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER, "%u");
+	TEST_EQ(rch_get_state(port), RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER,
+		"%u");
 
 	pd_port[port].mock_got_soft_reset = 0;
 	pd_port[port].mock_pe_error = -1;
@@ -1037,11 +1041,10 @@ static int test_receive_soft_reset_msg(void)
 static int test_receive_control_msg(void)
 {
 	int port = PORT0;
-	int expected_header = PD_HEADER(PD_CTRL_DR_SWAP,
-				get_partner_power_role(port),
-				get_partner_data_role(port),
-				pd_port[port].msg_rx_id,
-				0, pd_port[port].rev, 0);
+	int expected_header =
+		PD_HEADER(PD_CTRL_DR_SWAP, get_partner_power_role(port),
+			  get_partner_data_role(port), pd_port[port].msg_rx_id,
+			  0, pd_port[port].rev, 0);
 
 	enable_prl(port, 1);
 
@@ -1052,8 +1055,8 @@ static int test_receive_control_msg(void)
 	task_wake(PD_PORT_TO_TASK_ID(port));
 	task_wait_event(40 * MSEC);
 
-	TEST_EQ(rch_get_state(port),
-			RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER, "%u");
+	TEST_EQ(rch_get_state(port), RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER,
+		"%u");
 
 	pd_port[port].mock_got_soft_reset = 0;
 	pd_port[port].mock_pe_error = -1;
@@ -1093,9 +1096,9 @@ static int test_receive_data_msg(void)
 		task_wait_event(40 * MSEC);
 
 		TEST_EQ(rch_get_state(port),
-				RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER, "%u");
-		TEST_NE(simulate_receive_data(port,
-				PD_DATA_BATTERY_STATUS, i), 0, "%d");
+			RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER, "%u");
+		TEST_NE(simulate_receive_data(port, PD_DATA_BATTERY_STATUS, i),
+			0, "%d");
 	}
 
 	enable_prl(port, 0);
@@ -1119,11 +1122,12 @@ static int test_receive_extended_data_msg(void)
 		task_wait_event(40 * MSEC);
 
 		TEST_EQ(rch_get_state(port),
-				RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER, "%u");
+			RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER, "%u");
 
 		for (len = 29; len <= PD_MAX_EXTENDED_MSG_LEN; len++) {
-			TEST_NE(simulate_receive_extended_data(port,
-					PD_DATA_BATTERY_STATUS, len), 0, "%d");
+			TEST_NE(simulate_receive_extended_data(
+					port, PD_DATA_BATTERY_STATUS, len),
+				0, "%d");
 		}
 	} else {
 		/*
@@ -1132,13 +1136,14 @@ static int test_receive_extended_data_msg(void)
 		 */
 		task_wake(PD_PORT_TO_TASK_ID(port));
 		task_wait_event(40 * MSEC);
-		TEST_NE(simulate_receive_extended_data(port,
-					PD_DATA_BATTERY_STATUS, 29), 0, "%d");
+		TEST_NE(simulate_receive_extended_data(
+				port, PD_DATA_BATTERY_STATUS, 29),
+			0, "%d");
 
 		task_wake(PD_PORT_TO_TASK_ID(port));
 		task_wait_event(40 * MSEC);
-		TEST_NE(simulate_receive_data(port,
-				PD_DATA_BATTERY_STATUS, 28), 0, "%d");
+		TEST_NE(simulate_receive_data(port, PD_DATA_BATTERY_STATUS, 28),
+			0, "%d");
 	}
 
 	enable_prl(port, 0);
@@ -1159,21 +1164,20 @@ static int test_send_soft_reset_msg(void)
 	task_wake(PD_PORT_TO_TASK_ID(port));
 	task_wait_event(40 * MSEC);
 
-	TEST_EQ(prl_tx_get_state(port),
-				PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u");
+	TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u");
 
-	TEST_NE(simulate_send_ctrl_msg_request_from_pe(port,
-			TCPCI_MSG_SOP, PD_CTRL_SOFT_RESET), 0, "%d");
+	TEST_NE(simulate_send_ctrl_msg_request_from_pe(port, TCPCI_MSG_SOP,
+						       PD_CTRL_SOFT_RESET),
+		0, "%d");
 
 	task_wake(PD_PORT_TO_TASK_ID(port));
 	task_wait_event(30 * MSEC);
 
 	simulate_goodcrc(port, get_partner_power_role(port),
-						pd_port[port].msg_tx_id);
+			 pd_port[port].msg_tx_id);
 	inc_tx_id(port);
 
-	TEST_EQ(prl_tx_get_state(port),
-			PRL_TX_LAYER_RESET_FOR_TRANSMIT, "%u");
+	TEST_EQ(prl_tx_get_state(port), PRL_TX_LAYER_RESET_FOR_TRANSMIT, "%u");
 
 	cycle_through_state_machine(port, 3, 10 * MSEC);
 
@@ -1207,19 +1211,18 @@ static int test_pe_execute_hard_reset_msg(void)
 	prl_execute_hard_reset(port);
 
 	TEST_EQ(prl_hr_get_state(port), PRL_HR_RESET_LAYER, "%u");
-	TEST_EQ(prl_tx_get_state(port),
-			PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u");
+	TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u");
 
 	cycle_through_state_machine(port, 1, 10 * MSEC);
 
-	TEST_EQ(prl_hr_get_state(port),
-			PRL_HR_WAIT_FOR_PHY_HARD_RESET_COMPLETE, "%u");
+	TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_PHY_HARD_RESET_COMPLETE,
+		"%u");
 
 	cycle_through_state_machine(port, 2, PD_T_PS_HARD_RESET);
 	TEST_NE(pd_port[port].mock_pe_hard_reset_sent, 0, "%d");
 
-	TEST_EQ(prl_hr_get_state(port),
-			PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE, "%u");
+	TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE,
+		"%u");
 
 	/* Simulate policy engine indicating that it is done hard reset */
 	prl_hard_reset_complete(port);
@@ -1254,19 +1257,18 @@ static int test_phy_execute_hard_reset_msg(void)
 	pd_execute_hard_reset(port);
 
 	TEST_EQ(prl_hr_get_state(port), PRL_HR_RESET_LAYER, "%u");
-	TEST_EQ(prl_tx_get_state(port),
-			PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u");
+	TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u");
 
 	cycle_through_state_machine(port, 1, 10 * MSEC);
 
-	TEST_EQ(prl_hr_get_state(port),
-			PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE, "%u");
+	TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE,
+		"%u");
 
 	cycle_through_state_machine(port, 2, PD_T_PS_HARD_RESET);
 	TEST_NE(pd_port[port].mock_pe_got_hard_reset, 0, "%d");
 
-	TEST_EQ(prl_hr_get_state(port),
-			PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE, "%u");
+	TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE,
+		"%u");
 
 	/* Simulate policy engine indicating that it is done hard reset */
 	prl_hard_reset_complete(port);
@@ -1299,7 +1301,7 @@ void before_test(void)
 	cycle_through_state_machine(PORT0, 10, MSEC);
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/usb_prl_old.tasklist b/test/usb_prl_old.tasklist
index eb41326e3e..5c7f804157 100644
--- a/test/usb_prl_old.tasklist
+++ b/test/usb_prl_old.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/usb_sm_checks.c b/test/usb_sm_checks.c
index 49b2dbae28..a8dbdad872 100644
--- a/test/usb_sm_checks.c
+++ b/test/usb_sm_checks.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -39,7 +39,7 @@ const struct test_sm_data test_pe_sm_data[] = {};
 const int test_pe_sm_data_size;
 #endif
 
-test_static int test_no_parent_cycles(const struct test_sm_data * const sm_data)
+test_static int test_no_parent_cycles(const struct test_sm_data *const sm_data)
 {
 	int i;
 
diff --git a/test/usb_sm_checks.h b/test/usb_sm_checks.h
index d8e5f8ea06..1041afbaa4 100644
--- a/test/usb_sm_checks.h
+++ b/test/usb_sm_checks.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,11 +11,9 @@
 int test_tc_no_parent_cycles(void);
 int test_tc_all_states_named(void);
 
-
 int test_prl_no_parent_cycles(void);
 int test_prl_all_states_named(void);
 
-
 int test_pe_no_parent_cycles(void);
 int test_pe_all_states_named(void);
 
diff --git a/test/usb_sm_framework_h3.c b/test/usb_sm_framework_h3.c
index ba544a749a..20f9b706c6 100644
--- a/test/usb_sm_framework_h3.c
+++ b/test/usb_sm_framework_h3.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -112,7 +112,7 @@ enum state_id {
 	EXIT_C,
 };
 
-#define PORT0   0
+#define PORT0 0
 
 struct sm_ {
 	/* struct sm_obj must be first */
@@ -198,7 +198,6 @@ static void sm_test_super_A2_exit(const int port)
 	sm[port].seq[sm[port].idx++] = EXIT_A2;
 }
 
-
 static void sm_test_super_B2_entry(const int port)
 {
 	sm[port].seq[sm[port].idx++] = ENTER_B2;
@@ -269,7 +268,6 @@ static void sm_test_A4_exit(const int port)
 	sm[port].seq[sm[port].idx++] = EXIT_A4;
 }
 
-
 static void sm_test_A5_entry(const int port)
 {
 	sm[port].sv_tmp = 0;
@@ -291,7 +289,6 @@ static void sm_test_A5_exit(const int port)
 	sm[port].seq[sm[port].idx++] = EXIT_A5;
 }
 
-
 static void sm_test_A6_entry(const int port)
 {
 	sm[port].sv_tmp = 0;
@@ -355,7 +352,6 @@ static void sm_test_B4_exit(const int port)
 	sm[port].seq[sm[port].idx++] = EXIT_B4;
 }
 
-
 static void sm_test_B5_entry(const int port)
 {
 	sm[port].sv_tmp = 0;
@@ -377,7 +373,6 @@ static void sm_test_B5_exit(const int port)
 	sm[port].seq[sm[port].idx++] = EXIT_B5;
 }
 
-
 static void sm_test_B6_entry(const int port)
 {
 	sm[port].sv_tmp = 0;
@@ -440,63 +435,88 @@ test_static int test_hierarchy_0(void)
 	set_state_sm(port, SM_TEST_A4);
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], ENTER_A4, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A4, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A4, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_A4, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B4, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A4, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B4, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_B4, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_B4, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_B4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B5, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_B4, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B5, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_B5, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_B5, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_B5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B6, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_B5, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B6, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_B6, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_B6, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_B6, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_C, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_B6, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_C, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_C, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_C, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_C, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A7, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_C, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A7, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A7, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_A7, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A7, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A6, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A7, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A6, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A6, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_A6, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A6, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A5, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A6, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A5, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A5, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_A5, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A4, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A5, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A4, "%d");
+	++i;
 
 	for (; i < SEQUENCE_SIZE; i++)
 		TEST_EQ(sm[port].seq[i], 0, "%d");
@@ -512,71 +532,104 @@ test_static int test_hierarchy_1(void)
 	set_state_sm(port, SM_TEST_A4);
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], ENTER_A3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A4, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A4, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A3, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_A4, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_A3, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_A3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B4, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A4, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B4, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_B4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_B3, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_B4, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_B3, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_B4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_B3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B5, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_B4, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], EXIT_B3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B5, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_B5, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_B5, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_B5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B6, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_B5, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B6, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_B6, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_B6, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_B6, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_C, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_B6, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_C, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_C, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_C, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_C, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A7, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_C, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A7, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A7, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_A7, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A7, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A6, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A7, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A6, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A6, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_A6, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A6, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A5, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A6, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A5, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A3, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_A5, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_A3, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A4, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A5, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A4, "%d");
+	++i;
 
 	for (i = 33; i < SEQUENCE_SIZE; i++)
 		TEST_EQ(sm[port].seq[i], 0, "%d");
@@ -586,88 +639,130 @@ test_static int test_hierarchy_1(void)
 
 test_static int test_hierarchy_2(void)
 {
-
 	int port = PORT0;
 	int i = 0;
 
 	set_state_sm(port, SM_TEST_A4);
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], ENTER_A2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A4, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A2, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A4, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A2, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_A4, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_A3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_A2, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_A3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_A2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B4, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A4, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A2, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B2, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B4, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_B4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_B3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_B2, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_B4, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_B3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_B2, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_B4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_B3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B5, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_B4, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], EXIT_B3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B5, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_B5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_B2, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_B5, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_B2, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_B5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_B2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B6, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_B5, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], EXIT_B2, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B6, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_B6, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_B6, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_B6, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_C, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_B6, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_C, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_C, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_C, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_C, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A7, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_C, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A7, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A7, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_A7, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A7, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A6, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A7, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A2, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A6, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A6, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A2, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_A6, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_A2, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A6, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A5, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A6, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A5, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A2, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_A5, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_A3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_A2, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A4, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A5, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A4, "%d");
+	++i;
 
 	for (; i < SEQUENCE_SIZE; i++)
 		TEST_EQ(sm[port].seq[i], 0, "%d");
@@ -677,100 +772,154 @@ test_static int test_hierarchy_2(void)
 
 test_static int test_hierarchy_3(void)
 {
-
 	int port = PORT0;
 	int i = 0;
 
 	set_state_sm(port, SM_TEST_A4);
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], ENTER_A1, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A4, "%d"); ++i;
-
+	TEST_EQ(sm[port].seq[i], ENTER_A1, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A2, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A4, "%d");
+	++i;
+
+	run_sm();
+	TEST_EQ(sm[port].seq[i], RUN_A4, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_A3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_A2, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_A1, "%d");
+	++i;
+
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A1, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A4, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A2, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A1, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B1, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B2, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B4, "%d");
+	++i;
+
+	run_sm();
+	TEST_EQ(sm[port].seq[i], RUN_B4, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_B3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_B2, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_B1, "%d");
+	++i;
+
+	run_sm();
+	TEST_EQ(sm[port].seq[i], EXIT_B4, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], EXIT_B3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B5, "%d");
+	++i;
+
+	run_sm();
+	TEST_EQ(sm[port].seq[i], RUN_B5, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_B2, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_B1, "%d");
+	++i;
+
+	run_sm();
+	TEST_EQ(sm[port].seq[i], EXIT_B5, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], EXIT_B2, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B6, "%d");
+	++i;
+
+	run_sm();
+	TEST_EQ(sm[port].seq[i], RUN_B6, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_B1, "%d");
+	++i;
+
+	run_sm();
+	TEST_EQ(sm[port].seq[i], EXIT_B6, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], EXIT_B1, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_C, "%d");
+	++i;
+
+	run_sm();
+	TEST_EQ(sm[port].seq[i], RUN_C, "%d");
+	++i;
+
+	run_sm();
+	TEST_EQ(sm[port].seq[i], EXIT_C, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A1, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A7, "%d");
+	++i;
+
+	run_sm();
+	TEST_EQ(sm[port].seq[i], RUN_A7, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_A1, "%d");
+	++i;
+
+	run_sm();
+	TEST_EQ(sm[port].seq[i], EXIT_A7, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A2, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A6, "%d");
+	++i;
+
+	run_sm();
+	TEST_EQ(sm[port].seq[i], RUN_A6, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_A2, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_A1, "%d");
+	++i;
 
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_A3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_A2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_A1, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B1, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B4, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_B4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_B3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_B2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_B1, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_B4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_B3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B5, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_B5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_B2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_B1, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_B5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_B2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B6, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_B6, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_B1, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_B6, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_B1, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_C, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_C, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_C, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A1, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A7, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A7, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A1, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A7, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A6, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A6, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A1, "%d"); ++i;
-
-	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A6, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A5, "%d"); ++i;
+	run_sm();
+	TEST_EQ(sm[port].seq[i], EXIT_A6, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A5, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_A5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_A1, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_A5, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_A3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_A2, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_A1, "%d");
+	++i;
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_A5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A4, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A5, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A4, "%d");
+	++i;
 
 	for (; i < SEQUENCE_SIZE; i++)
 		TEST_EQ(sm[port].seq[i], 0, "%d");
@@ -787,35 +936,53 @@ test_static int test_set_state_from_parents(void)
 	test_control.a3_entry_to = &states[SM_TEST_B4];
 	run_sm();
 	set_state_sm(port, SM_TEST_A4);
-	TEST_EQ(sm[port].seq[i], ENTER_A1, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A3, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A1, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A2, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A3, "%d");
+	++i;
 	/* Does not enter or exit A4 */
-	TEST_EQ(sm[port].seq[i], EXIT_A3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_A2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_A1, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B1, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B4, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A2, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], EXIT_A1, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B1, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B2, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B4, "%d");
+	++i;
 	/* Ensure we didn't go further than above statements */
 	TEST_EQ(sm[port].seq[i], 0, "%d");
 
 	test_control.b3_run_to = &states[SM_TEST_B5];
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_B4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_B3, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_B4, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_B3, "%d");
+	++i;
 	/* Does not run b2 or b1 */
-	TEST_EQ(sm[port].seq[i], EXIT_B4, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_B3, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B5, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_B4, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], EXIT_B3, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B5, "%d");
+	++i;
 	/* Ensure we didn't go further than above statements */
 	TEST_EQ(sm[port].seq[i], 0, "%d");
 
 	run_sm();
-	TEST_EQ(sm[port].seq[i], RUN_B5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_B2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], RUN_B1, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], RUN_B5, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_B2, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], RUN_B1, "%d");
+	++i;
 	/* Ensure we didn't go further than above statements */
 	TEST_EQ(sm[port].seq[i], 0, "%d");
 
@@ -827,15 +994,24 @@ test_static int test_set_state_from_parents(void)
 	test_control.c_entry_to = &states[SM_TEST_A7];
 	test_control.c_exit_to = &states[SM_TEST_A4];
 	run_sm();
-	TEST_EQ(sm[port].seq[i], EXIT_B5, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_B2, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_B6, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_B6, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_B1, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_C, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], EXIT_C, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A1, "%d"); ++i;
-	TEST_EQ(sm[port].seq[i], ENTER_A7, "%d"); ++i;
+	TEST_EQ(sm[port].seq[i], EXIT_B5, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], EXIT_B2, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_B6, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], EXIT_B6, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], EXIT_B1, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_C, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], EXIT_C, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A1, "%d");
+	++i;
+	TEST_EQ(sm[port].seq[i], ENTER_A7, "%d");
+	++i;
 	/* Ensure we didn't go further than above statements */
 	TEST_EQ(sm[port].seq[i], 0, "%d");
 
@@ -985,7 +1161,7 @@ int test_task(void *u)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 #if defined(TEST_USB_SM_FRAMEWORK_H3)
diff --git a/test/usb_sm_framework_h3.tasklist b/test/usb_sm_framework_h3.tasklist
index 998998fd6c..9db4e49e5e 100644
--- a/test/usb_sm_framework_h3.tasklist
+++ b/test/usb_sm_framework_h3.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/usb_tcpmv2_compliance.c b/test/usb_tcpmv2_compliance.c
index e0288feb18..2acd2c1660 100644
--- a/test/usb_tcpmv2_compliance.c
+++ b/test/usb_tcpmv2_compliance.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -30,7 +30,7 @@ void before_test(void)
 	tc_try_src_override(TRY_SRC_OVERRIDE_OFF);
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/usb_tcpmv2_compliance.h b/test/usb_tcpmv2_compliance.h
index 331e3c5ee8..0ca4717173 100644
--- a/test/usb_tcpmv2_compliance.h
+++ b/test/usb_tcpmv2_compliance.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,18 +22,16 @@ enum mock_connect_result {
 	MOCK_CC_DUT_IS_SNK = 1,
 };
 
-
 extern uint32_t rdo;
 extern uint32_t pdo;
 
 extern const struct tcpc_config_t tcpc_config[];
-extern const struct usb_mux usb_muxes[];
-
+extern const struct usb_mux_chain usb_muxes[];
 
-void mock_set_cc(enum mock_connect_result cr,
-	enum mock_cc_state cc1, enum mock_cc_state cc2);
-void mock_set_role(int drp, enum tcpc_rp_value rp,
-	enum tcpc_cc_pull cc1, enum tcpc_cc_pull cc2);
+void mock_set_cc(enum mock_connect_result cr, enum mock_cc_state cc1,
+		 enum mock_cc_state cc2);
+void mock_set_role(int drp, enum tcpc_rp_value rp, enum tcpc_cc_pull cc1,
+		   enum tcpc_cc_pull cc2);
 void mock_set_alert(int alert);
 uint16_t tcpc_get_alert_status(void);
 bool vboot_allow_usb_pd(void);
@@ -54,20 +52,15 @@ enum pd_rev_type partner_get_pd_rev(void);
 #define TCPCI_MSG_SOP_ALL -1
 void partner_tx_msg_id_reset(int sop);
 
-void partner_send_msg(enum tcpci_msg_type sop,
-		      uint16_t type,
-		      uint16_t cnt,
-		      uint16_t ext,
-		      uint32_t *payload);
-
+void partner_send_msg(enum tcpci_msg_type sop, uint16_t type, uint16_t cnt,
+		      uint16_t ext, uint32_t *payload);
 
 int handle_attach_expected_msgs(enum pd_data_role data_role);
 
-
 enum proc_pd_e1_attach {
-	INITIAL_ATTACH			= BIT(0),
-	ALREADY_ATTACHED		= BIT(1),
-	INITIAL_AND_ALREADY_ATTACHED	= INITIAL_ATTACH | ALREADY_ATTACHED
+	INITIAL_ATTACH = BIT(0),
+	ALREADY_ATTACHED = BIT(1),
+	INITIAL_AND_ALREADY_ATTACHED = INITIAL_ATTACH | ALREADY_ATTACHED
 };
 int proc_pd_e1(enum pd_data_role data_role, enum proc_pd_e1_attach attach);
 int proc_pd_e3(void);
diff --git a/test/usb_tcpmv2_compliance.mocklist b/test/usb_tcpmv2_compliance.mocklist
index f364fb1050..311397fe43 100644
--- a/test/usb_tcpmv2_compliance.mocklist
+++ b/test/usb_tcpmv2_compliance.mocklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/usb_tcpmv2_compliance.tasklist b/test/usb_tcpmv2_compliance.tasklist
index 654e4eca2b..794669adbe 100644
--- a/test/usb_tcpmv2_compliance.tasklist
+++ b/test/usb_tcpmv2_compliance.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/usb_tcpmv2_compliance_common.c b/test/usb_tcpmv2_compliance_common.c
index 6145f59388..9f839ecf1c 100644
--- a/test/usb_tcpmv2_compliance_common.c
+++ b/test/usb_tcpmv2_compliance_common.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,9 +15,8 @@
 
 uint32_t rdo = RDO_FIXED(1, 500, 500, 0);
 uint32_t pdo = PDO_FIXED(5000, 3000,
-			 PDO_FIXED_DUAL_ROLE |
-			 PDO_FIXED_DATA_SWAP |
-			 PDO_FIXED_COMM_CAP);
+			 PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |
+				 PDO_FIXED_COMM_CAP);
 
 const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
@@ -31,25 +30,25 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.driver = &mock_usb_mux_driver,
-	}
-};
-
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { {
+	.mux =
+		&(const struct usb_mux){
+			.driver = &mock_usb_mux_driver,
+		},
+} };
 
-void mock_set_cc(enum mock_connect_result cr,
-	enum mock_cc_state cc1, enum mock_cc_state cc2)
+void mock_set_cc(enum mock_connect_result cr, enum mock_cc_state cc1,
+		 enum mock_cc_state cc2)
 {
 	mock_tcpci_set_reg(TCPC_REG_CC_STATUS,
-		TCPC_REG_CC_STATUS_SET(cr, cc1, cc2));
+			   TCPC_REG_CC_STATUS_SET(cr, cc1, cc2));
 }
 
-void mock_set_role(int drp, enum tcpc_rp_value rp,
-	enum tcpc_cc_pull cc1, enum tcpc_cc_pull cc2)
+void mock_set_role(int drp, enum tcpc_rp_value rp, enum tcpc_cc_pull cc1,
+		   enum tcpc_cc_pull cc2)
 {
 	mock_tcpci_set_reg(TCPC_REG_ROLE_CTRL,
-		TCPC_REG_ROLE_CTRL_SET(drp, rp, cc1, cc2));
+			   TCPC_REG_ROLE_CTRL_SET(drp, rp, cc1, cc2));
 }
 
 static int mock_alert_count;
@@ -80,7 +79,9 @@ int pd_check_vconn_swap(int port)
 	return 1;
 }
 
-void board_reset_pd_mcu(void) {}
+void board_reset_pd_mcu(void)
+{
+}
 
 /*****************************************************************************
  * Partner utility functions
@@ -125,38 +126,31 @@ void partner_tx_msg_id_reset(int sop)
 		partner_tx_id[sop] = 0;
 }
 
-void partner_send_msg(enum tcpci_msg_type sop,
-		      uint16_t type,
-		      uint16_t cnt,
-		      uint16_t ext,
-		      uint32_t *payload)
+void partner_send_msg(enum tcpci_msg_type sop, uint16_t type, uint16_t cnt,
+		      uint16_t ext, uint32_t *payload)
 {
 	uint16_t header;
 
 	partner_tx_id[sop] &= 7;
 	header = PD_HEADER(type,
-			sop == TCPCI_MSG_SOP ? partner_get_power_role()
-			: PD_PLUG_FROM_CABLE,
-			partner_get_data_role(),
-			partner_tx_id[sop],
-			cnt,
-			partner_get_pd_rev(),
-			ext);
+			   sop == TCPCI_MSG_SOP ? partner_get_power_role() :
+						  PD_PLUG_FROM_CABLE,
+			   partner_get_data_role(), partner_tx_id[sop], cnt,
+			   partner_get_pd_rev(), ext);
 
 	mock_tcpci_receive(sop, header, payload);
 	++partner_tx_id[sop];
 	mock_set_alert(TCPC_REG_ALERT_RX_STATUS);
 }
 
-
 /*****************************************************************************
  * TCPCI clean power up
  */
 int tcpci_startup(void)
 {
 	/* Should be in low power mode before AP boots. */
-	TEST_EQ(mock_tcpci_get_reg(TCPC_REG_COMMAND),
-		TCPC_REG_COMMAND_I2CIDLE, "%d");
+	TEST_EQ(mock_tcpci_get_reg(TCPC_REG_COMMAND), TCPC_REG_COMMAND_I2CIDLE,
+		"%d");
 	task_wait_event(10 * SECOND);
 
 	hook_notify(HOOK_CHIPSET_STARTUP);
@@ -165,12 +159,12 @@ int tcpci_startup(void)
 
 	task_wait_event(10 * SECOND);
 	/* Should be in low power mode and DRP auto-toggling with AP in S0. */
-	TEST_EQ((mock_tcpci_get_reg(TCPC_REG_ROLE_CTRL)
-		 & TCPC_REG_ROLE_CTRL_DRP_MASK),
+	TEST_EQ((mock_tcpci_get_reg(TCPC_REG_ROLE_CTRL) &
+		 TCPC_REG_ROLE_CTRL_DRP_MASK),
 		TCPC_REG_ROLE_CTRL_DRP_MASK, "%d");
 	/* TODO: check previous command was TCPC_REG_COMMAND_LOOK4CONNECTION */
-	TEST_EQ(mock_tcpci_get_reg(TCPC_REG_COMMAND),
-		TCPC_REG_COMMAND_I2CIDLE, "%d");
+	TEST_EQ(mock_tcpci_get_reg(TCPC_REG_COMMAND), TCPC_REG_COMMAND_I2CIDLE,
+		"%d");
 
 	/* TODO: this should be performed in TCPCI mock on startup but needs
 	 * more TCPCI functionality added before that can happen.  So until
@@ -198,13 +192,12 @@ int proc_pd_e1(enum pd_data_role data_role, enum proc_pd_e1_attach attach)
 		TEST_EQ(pd_get_data_role(I2C_PORT_HOST_TCPC),
 			PD_ROLE_DISCONNECTED, "%d");
 
-		partner_set_data_role((data_role == PD_ROLE_UFP)
-						? PD_ROLE_DFP
-						: PD_ROLE_UFP);
+		partner_set_data_role((data_role == PD_ROLE_UFP) ? PD_ROLE_DFP :
+								   PD_ROLE_UFP);
 
-		partner_set_power_role((data_role == PD_ROLE_UFP)
-						? PD_ROLE_SOURCE
-						: PD_ROLE_SINK);
+		partner_set_power_role((data_role == PD_ROLE_UFP) ?
+					       PD_ROLE_SOURCE :
+					       PD_ROLE_SINK);
 
 		switch (partner_get_power_role()) {
 		case PD_ROLE_SOURCE:
@@ -212,11 +205,10 @@ int proc_pd_e1(enum pd_data_role data_role, enum proc_pd_e1_attach attach)
 			 * b) The tester applies Rp (PD3=1.5A, PD2=3A) and
 			 *    waits for the UUT attachment.
 			 */
-			mock_set_cc(MOCK_CC_DUT_IS_SNK,
-				    MOCK_CC_SNK_OPEN,
-				    (partner_get_pd_rev() == PD_REV30
-					? MOCK_CC_SNK_RP_1_5
-					: MOCK_CC_SNK_RP_3_0));
+			mock_set_cc(MOCK_CC_DUT_IS_SNK, MOCK_CC_SNK_OPEN,
+				    (partner_get_pd_rev() == PD_REV30 ?
+					     MOCK_CC_SNK_RP_1_5 :
+					     MOCK_CC_SNK_RP_3_0));
 			mock_set_alert(TCPC_REG_ALERT_CC_STATUS);
 			task_wait_event(5 * MSEC);
 
@@ -227,11 +219,12 @@ int proc_pd_e1(enum pd_data_role data_role, enum proc_pd_e1_attach attach)
 			/*
 			 * d) The tester applies Vbus and waits 50 ms.
 			 */
-			mock_tcpci_set_reg_bits(TCPC_REG_POWER_STATUS,
-					TCPC_REG_POWER_STATUS_VBUS_PRES);
+			mock_tcpci_set_reg_bits(
+				TCPC_REG_POWER_STATUS,
+				TCPC_REG_POWER_STATUS_VBUS_PRES);
 
 			mock_tcpci_clr_reg_bits(TCPC_REG_EXT_STATUS,
-					TCPC_REG_EXT_STATUS_SAFE0V);
+						TCPC_REG_EXT_STATUS_SAFE0V);
 			mock_set_alert(TCPC_REG_ALERT_EXT_STATUS |
 				       TCPC_REG_ALERT_POWER_STATUS);
 			task_wait_event(50 * MSEC);
@@ -242,8 +235,7 @@ int proc_pd_e1(enum pd_data_role data_role, enum proc_pd_e1_attach attach)
 			 * b) The tester applies Rd and waits for Vbus for
 			 *    tNoResponse max (5.5 s).
 			 */
-			mock_set_cc(MOCK_CC_DUT_IS_SRC,
-				    MOCK_CC_SRC_OPEN,
+			mock_set_cc(MOCK_CC_DUT_IS_SRC, MOCK_CC_SRC_OPEN,
 				    MOCK_CC_SRC_RD);
 			mock_set_alert(TCPC_REG_ALERT_CC_STATUS);
 			break;
@@ -260,7 +252,7 @@ int proc_pd_e1(enum pd_data_role data_role, enum proc_pd_e1_attach attach)
 			 */
 			task_wait_event(1 * MSEC);
 			partner_send_msg(TCPCI_MSG_SOP, PD_DATA_SOURCE_CAP, 1,
-					0, &pdo);
+					 0, &pdo);
 
 			/*
 			 * f) The tester waits for the Request from the UUT for
@@ -324,8 +316,7 @@ int proc_pd_e1(enum pd_data_role data_role, enum proc_pd_e1_attach attach)
 			TEST_EQ(tc_is_attached_src(PORT0), true, "%d");
 			break;
 		}
-		TEST_EQ(pd_get_data_role(I2C_PORT_HOST_TCPC),
-			data_role, "%d");
+		TEST_EQ(pd_get_data_role(I2C_PORT_HOST_TCPC), data_role, "%d");
 	}
 
 	return EC_SUCCESS;
@@ -390,13 +381,8 @@ int handle_attach_expected_msgs(enum pd_data_role data_role)
 		possible[4].data_msg = 0;
 
 		do {
-			rv = verify_tcpci_possible_tx(possible,
-						 5,
-						 &found_index,
-						 NULL,
-						 0,
-						 NULL,
-						 -1);
+			rv = verify_tcpci_possible_tx(possible, 5, &found_index,
+						      NULL, 0, NULL, -1);
 
 			TEST_NE(rv, EC_ERROR_UNKNOWN, "%d");
 			if (rv == EC_ERROR_TIMEOUT)
@@ -406,30 +392,29 @@ int handle_attach_expected_msgs(enum pd_data_role data_role)
 			task_wait_event(10 * MSEC);
 
 			switch (found_index) {
-			case 0:	/* TCPCI_MSG_SOP PD_CTRL_GET_SOURCE_CAP */
+			case 0: /* TCPCI_MSG_SOP PD_CTRL_GET_SOURCE_CAP */
 				partner_send_msg(TCPCI_MSG_SOP,
-						 PD_DATA_SOURCE_CAP,
-						 1, 0, &pdo);
+						 PD_DATA_SOURCE_CAP, 1, 0,
+						 &pdo);
 				break;
 			case 1: /* TCPCI_MSG_SOP PD_CTRL_GET_SINK_CAP */
 				partner_send_msg(TCPCI_MSG_SOP,
-						 PD_DATA_SINK_CAP,
-						 1, 0, &pdo);
+						 PD_DATA_SINK_CAP, 1, 0, &pdo);
 				break;
 			case 2: /* TCPCI_MSG_SOP_PRIME PD_DATA_VENDOR_DEF */
 				partner_send_msg(TCPCI_MSG_SOP_PRIME,
-						 PD_CTRL_NOT_SUPPORTED,
-						 0, 0, NULL);
+						 PD_CTRL_NOT_SUPPORTED, 0, 0,
+						 NULL);
 				break;
 			case 3: /* TCPCI_MSG_SOP PD_DATA_VENDOR_DEF */
 				partner_send_msg(TCPCI_MSG_SOP,
-						 PD_CTRL_NOT_SUPPORTED,
-						 0, 0, NULL);
+						 PD_CTRL_NOT_SUPPORTED, 0, 0,
+						 NULL);
 				break;
 			case 4: /* TCPCI_MSG_SOP PD_CTRL_GET_REVISION */
 				partner_send_msg(TCPCI_MSG_SOP,
-						 PD_CTRL_NOT_SUPPORTED,
-						 0, 0, NULL);
+						 PD_CTRL_NOT_SUPPORTED, 0, 0,
+						 NULL);
 				break;
 			default:
 				TEST_ASSERT(0);
@@ -460,13 +445,8 @@ int handle_attach_expected_msgs(enum pd_data_role data_role)
 		possible[4].data_msg = 0;
 
 		do {
-			rv = verify_tcpci_possible_tx(possible,
-						 5,
-						 &found_index,
-						 NULL,
-						 0,
-						 NULL,
-						 -1);
+			rv = verify_tcpci_possible_tx(possible, 5, &found_index,
+						      NULL, 0, NULL, -1);
 
 			TEST_NE(rv, EC_ERROR_UNKNOWN, "%d");
 			if (rv == EC_ERROR_TIMEOUT)
@@ -478,29 +458,25 @@ int handle_attach_expected_msgs(enum pd_data_role data_role)
 			switch (found_index) {
 			case 0: /* TCPCI_MSG_SOP PD_CTRL_GET_SINK_CAP */
 				partner_send_msg(TCPCI_MSG_SOP,
-						 PD_DATA_SINK_CAP,
-						 1, 0, &pdo);
+						 PD_DATA_SINK_CAP, 1, 0, &pdo);
 				break;
 			case 1: /* TCPCI_MSG_SOP PD_CTRL_DR_SWAP */
-				partner_send_msg(TCPCI_MSG_SOP,
-						 PD_CTRL_REJECT,
+				partner_send_msg(TCPCI_MSG_SOP, PD_CTRL_REJECT,
 						 0, 0, NULL);
 				break;
-			case 2:	/* TCPCI_MSG_SOP PD_CTRL_PR_SWAP */
-				partner_send_msg(TCPCI_MSG_SOP,
-						 PD_CTRL_REJECT,
+			case 2: /* TCPCI_MSG_SOP PD_CTRL_PR_SWAP */
+				partner_send_msg(TCPCI_MSG_SOP, PD_CTRL_REJECT,
 						 0, 0, NULL);
 				break;
 			case 3: /* TCPCI_MSG_SOP PD_CTRL_VCONN_SWAP */
 				TEST_LT(vcs++, 4, "%d");
-				partner_send_msg(TCPCI_MSG_SOP,
-						 PD_CTRL_REJECT,
+				partner_send_msg(TCPCI_MSG_SOP, PD_CTRL_REJECT,
 						 0, 0, NULL);
 				break;
 			case 4: /* TCPCI_MSG_SOP PD_CTRL_GET_REVISION */
 				partner_send_msg(TCPCI_MSG_SOP,
-						 PD_CTRL_NOT_SUPPORTED,
-						 0, 0, NULL);
+						 PD_CTRL_NOT_SUPPORTED, 0, 0,
+						 NULL);
 				break;
 			default:
 				TEST_ASSERT(0);
diff --git a/test/usb_tcpmv2_td_pd_ll_e3.c b/test/usb_tcpmv2_td_pd_ll_e3.c
index 46fbee393f..f239c87885 100644
--- a/test/usb_tcpmv2_td_pd_ll_e3.c
+++ b/test/usb_tcpmv2_td_pd_ll_e3.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -29,8 +29,8 @@ static int td_pd_ll_e3(enum pd_data_role data_role)
 	/*
 	 * a) Run PROC.PD.E1 Bring-up according to the UUT role.
 	 */
-	TEST_EQ(proc_pd_e1(data_role, INITIAL_AND_ALREADY_ATTACHED),
-		EC_SUCCESS, "%d");
+	TEST_EQ(proc_pd_e1(data_role, INITIAL_AND_ALREADY_ATTACHED), EC_SUCCESS,
+		"%d");
 
 	/*
 	 * Make sure we are idle. Reject everything that is pending
@@ -42,13 +42,11 @@ static int td_pd_ll_e3(enum pd_data_role data_role)
 	 *    and do not send GoodCrc for nRetryCount + 1 times
 	 *    (nRetryCount equals 3 since PD 2.1).
 	 */
-	partner_send_msg(TCPCI_MSG_SOP,
-			 PD_CTRL_GET_SINK_CAP,
-			 0, 0, NULL);
+	partner_send_msg(TCPCI_MSG_SOP, PD_CTRL_GET_SINK_CAP, 0, 0, NULL);
 
 	retries = (partner_get_pd_rev() == PD_REV30) ? 2 : 3;
 	TEST_EQ(verify_tcpci_tx_retry_count(TCPCI_MSG_SOP, 0, PD_DATA_SINK_CAP,
-			retries),
+					    retries),
 		EC_SUCCESS, "%d");
 	mock_set_alert(TCPC_REG_ALERT_TX_FAILED);
 
diff --git a/test/usb_tcpmv2_td_pd_ll_e4.c b/test/usb_tcpmv2_td_pd_ll_e4.c
index cb6aa8e8b6..f315fc2a63 100644
--- a/test/usb_tcpmv2_td_pd_ll_e4.c
+++ b/test/usb_tcpmv2_td_pd_ll_e4.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -31,8 +31,8 @@ static int td_pd_ll_e4(enum pd_data_role data_role)
 	/*
 	 * a) Run PROC.PD.E1 Bring-up according to the UUT role.
 	 */
-	TEST_EQ(proc_pd_e1(data_role, INITIAL_AND_ALREADY_ATTACHED),
-		EC_SUCCESS, "%d");
+	TEST_EQ(proc_pd_e1(data_role, INITIAL_AND_ALREADY_ATTACHED), EC_SUCCESS,
+		"%d");
 
 	/*
 	 * Make sure we are idle. Reject everything that is pending
@@ -44,13 +44,11 @@ static int td_pd_ll_e4(enum pd_data_role data_role)
 	 *    and do not send GoodCrc for nRetryCount + 1 times
 	 *    (nRetryCount equals 3 since PD 2.1).
 	 */
-	partner_send_msg(TCPCI_MSG_SOP,
-			 PD_CTRL_GET_SINK_CAP,
-			 0, 0, NULL);
+	partner_send_msg(TCPCI_MSG_SOP, PD_CTRL_GET_SINK_CAP, 0, 0, NULL);
 
 	retries = 3;
 	TEST_EQ(verify_tcpci_tx_retry_count(TCPCI_MSG_SOP, 0, PD_DATA_SINK_CAP,
-			retries),
+					    retries),
 		EC_SUCCESS, "%d");
 	mock_set_alert(TCPC_REG_ALERT_TX_FAILED);
 
@@ -60,7 +58,7 @@ static int td_pd_ll_e4(enum pd_data_role data_role)
 	 */
 	retries = 3;
 	TEST_EQ(verify_tcpci_tx_retry_count(TCPCI_MSG_SOP, PD_CTRL_SOFT_RESET,
-				0, retries),
+					    0, retries),
 		EC_SUCCESS, "%d");
 	mock_set_alert(TCPC_REG_ALERT_TX_FAILED);
 	task_wait_event(1 * MSEC);
@@ -68,8 +66,8 @@ static int td_pd_ll_e4(enum pd_data_role data_role)
 	/*
 	 * d) Check that the UUT issues a Hard Reset.
 	 */
-	TEST_EQ(mock_tcpci_get_reg(TCPC_REG_TRANSMIT),
-		TCPCI_MSG_TX_HARD_RESET, "%d");
+	TEST_EQ(mock_tcpci_get_reg(TCPC_REG_TRANSMIT), TCPCI_MSG_TX_HARD_RESET,
+		"%d");
 	mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS | TCPC_REG_ALERT_TX_FAILED);
 	mock_tcpci_set_reg(TCPC_REG_TRANSMIT, 0);
 	task_wait_event(1 * MSEC);
diff --git a/test/usb_tcpmv2_td_pd_ll_e5.c b/test/usb_tcpmv2_td_pd_ll_e5.c
index ae6409eb20..7c7446a7b3 100644
--- a/test/usb_tcpmv2_td_pd_ll_e5.c
+++ b/test/usb_tcpmv2_td_pd_ll_e5.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,8 +26,8 @@ static int td_pd_ll_e5(enum pd_data_role data_role)
 	/*
 	 * a) Run PROC.PD.E1 Bring-up according to the UUT role.
 	 */
-	TEST_EQ(proc_pd_e1(data_role, INITIAL_AND_ALREADY_ATTACHED),
-		EC_SUCCESS, "%d");
+	TEST_EQ(proc_pd_e1(data_role, INITIAL_AND_ALREADY_ATTACHED), EC_SUCCESS,
+		"%d");
 
 	/*
 	 * Make sure we are idle. Reject everything that is pending
diff --git a/test/usb_tcpmv2_td_pd_other.c b/test/usb_tcpmv2_td_pd_other.c
index 1882480150..18477ac825 100644
--- a/test/usb_tcpmv2_td_pd_other.c
+++ b/test/usb_tcpmv2_td_pd_other.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -57,7 +57,7 @@ int test_retry_count_sop(void)
 	 * The retry count for PD3 should be 2.
 	 */
 	TEST_EQ(verify_tcpci_tx_retry_count(TCPCI_MSG_SOP, 0,
-				PD_DATA_SOURCE_CAP, 2),
+					    PD_DATA_SOURCE_CAP, 2),
 		EC_SUCCESS, "%d");
 	return EC_SUCCESS;
 }
diff --git a/test/usb_tcpmv2_td_pd_snk3_e12.c b/test/usb_tcpmv2_td_pd_snk3_e12.c
index 0195d39dba..11aa51016e 100644
--- a/test/usb_tcpmv2_td_pd_snk3_e12.c
+++ b/test/usb_tcpmv2_td_pd_snk3_e12.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -46,8 +46,8 @@ int test_td_pd_snk3_e12(void)
 	 * d) The Tester verifies that a Soft_Reset message is sent by the UUT
 	 * within tReceive max + tSoftReset max
 	 */
-	TEST_EQ(verify_tcpci_tx_timeout(
-			TCPCI_MSG_SOP, PD_CTRL_SOFT_RESET, 0, 16 * MSEC),
+	TEST_EQ(verify_tcpci_tx_timeout(TCPCI_MSG_SOP, PD_CTRL_SOFT_RESET, 0,
+					16 * MSEC),
 		EC_SUCCESS, "%d");
 	mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
 
diff --git a/test/usb_tcpmv2_td_pd_src3_e1.c b/test/usb_tcpmv2_td_pd_src3_e1.c
index 751e354b11..4f5637ccd2 100644
--- a/test/usb_tcpmv2_td_pd_src3_e1.c
+++ b/test/usb_tcpmv2_td_pd_src3_e1.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -69,21 +69,17 @@ int test_td_pd_src3_e1(void)
 	 *    5. Message Type field = 00001b (Source Capabilities)
 	 *    6. Extended field = 0b
 	 */
-	TEST_EQ(verify_tcpci_tx_with_data(TCPCI_MSG_SOP,
-					  PD_DATA_SOURCE_CAP,
-					  data,
-					  sizeof(data),
-					  &msg_len,
-					  0),
+	TEST_EQ(verify_tcpci_tx_with_data(TCPCI_MSG_SOP, PD_DATA_SOURCE_CAP,
+					  data, sizeof(data), &msg_len, 0),
 		EC_SUCCESS, "%d");
 	TEST_GE(msg_len, HEADER_BYTE_CNT, "%d");
 
 	header = UINT16_FROM_BYTE_ARRAY_LE(data, HEADER_BYTE_OFFSET);
 	pd_cnt = PD_HEADER_CNT(header);
 	TEST_NE(pd_cnt, 0, "%d");
-	TEST_EQ(msg_len, HEADER_BYTE_OFFSET +
-			 HEADER_BYTE_CNT +
-			 (pd_cnt * PDO_BYTE_CNT), "%d");
+	TEST_EQ(msg_len,
+		HEADER_BYTE_OFFSET + HEADER_BYTE_CNT + (pd_cnt * PDO_BYTE_CNT),
+		"%d");
 	TEST_EQ(PD_HEADER_PROLE(header), PD_ROLE_SOURCE, "%d");
 	TEST_EQ(PD_HEADER_REV(header), REVISION_3, "%d");
 	TEST_EQ(PD_HEADER_DROLE(header), PD_ROLE_DFP, "%d");
@@ -96,8 +92,8 @@ int test_td_pd_src3_e1(void)
 	 *    2. Voltage field = 100 (5 V)
 	 *    3. Bits 23..22 = 000b (Reserved)
 	 */
-	pdo = UINT32_FROM_BYTE_ARRAY_LE(data, HEADER_BYTE_OFFSET +
-					      HEADER_BYTE_CNT);
+	pdo = UINT32_FROM_BYTE_ARRAY_LE(data,
+					HEADER_BYTE_OFFSET + HEADER_BYTE_CNT);
 
 	type = pdo & PDO_TYPE_MASK;
 	TEST_EQ(type, PDO_TYPE_FIXED, "%d");
@@ -135,15 +131,14 @@ int test_td_pd_src3_e1(void)
 		int offset;
 		uint32_t voltage;
 
-		offset = HEADER_BYTE_OFFSET +
-			 HEADER_BYTE_CNT +
+		offset = HEADER_BYTE_OFFSET + HEADER_BYTE_CNT +
 			 (i * PDO_BYTE_CNT);
 		pdo = UINT32_FROM_BYTE_ARRAY_LE(data, offset);
 
 		type = pdo & PDO_TYPE_MASK;
 		if (type == PDO_TYPE_FIXED) {
-			TEST_EQ(pdo & (GENMASK(28, 26)|GENMASK(24, 22)),
-				0, "%d");
+			TEST_EQ(pdo & (GENMASK(28, 26) | GENMASK(24, 22)), 0,
+				"%d");
 			TEST_EQ(last_battery_voltage, 0, "%d");
 			TEST_EQ(last_variable_voltage, 0, "%d");
 			TEST_EQ(last_programmable_voltage, 0, "%d");
diff --git a/test/usb_tcpmv2_td_pd_src3_e26.c b/test/usb_tcpmv2_td_pd_src3_e26.c
index f5f5bcd3c4..aef472884b 100644
--- a/test/usb_tcpmv2_td_pd_src3_e26.c
+++ b/test/usb_tcpmv2_td_pd_src3_e26.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -47,8 +47,8 @@ int test_td_pd_src3_e26(void)
 	 * d) The Tester verifies that a Soft_Reset message is sent by the UUT
 	 * within tReceive max (1.1 ms) + tSoftReset max (15 ms).
 	 */
-	TEST_EQ(verify_tcpci_tx_timeout(
-			TCPCI_MSG_SOP, PD_CTRL_SOFT_RESET, 0, 15 * MSEC),
+	TEST_EQ(verify_tcpci_tx_timeout(TCPCI_MSG_SOP, PD_CTRL_SOFT_RESET, 0,
+					15 * MSEC),
 		EC_SUCCESS, "%d");
 	mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
 
diff --git a/test/usb_tcpmv2_td_pd_src3_e32.c b/test/usb_tcpmv2_td_pd_src3_e32.c
index 9ade7b83c8..395a251b22 100644
--- a/test/usb_tcpmv2_td_pd_src3_e32.c
+++ b/test/usb_tcpmv2_td_pd_src3_e32.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,18 +10,17 @@
 #include "timer.h"
 #include "usb_tcpmv2_compliance.h"
 
-#define PD_T_CHUNK_RECEIVER_REQUEST_MAX		(15 * MSEC)
-#define PD_T_CHUNK_SENDER_RSP_MAX		(30 * MSEC)
-#define PD_T_CHUNKING_NOT_SUPPORTED_MIN		(40 * MSEC)
-#define PD_T_CHUNKING_NOT_SUPPORTED_MAX		(50 * MSEC)
+#define PD_T_CHUNK_RECEIVER_REQUEST_MAX (15 * MSEC)
+#define PD_T_CHUNK_SENDER_RSP_MAX (30 * MSEC)
+#define PD_T_CHUNKING_NOT_SUPPORTED_MIN (40 * MSEC)
+#define PD_T_CHUNKING_NOT_SUPPORTED_MAX (50 * MSEC)
 
 static void setup_chunk_msg(int chunk, char *data)
 {
 	int i;
 	int base_msg_byte = chunk * PD_MAX_EXTENDED_MSG_CHUNK_LEN;
 
-	*(uint16_t *)data = PD_EXT_HEADER(chunk, 0,
-					  PD_MAX_EXTENDED_MSG_LEN);
+	*(uint16_t *)data = PD_EXT_HEADER(chunk, 0, PD_MAX_EXTENDED_MSG_LEN);
 
 	for (i = 0; i < PD_MAX_EXTENDED_MSG_CHUNK_LEN; ++i) {
 		int val = (i + base_msg_byte) % 256;
@@ -85,12 +84,8 @@ int test_td_pd_src3_e32(void)
 	possible[1].ctrl_msg = 0;
 	possible[1].data_msg = 0x1F;
 
-	TEST_EQ(verify_tcpci_possible_tx(possible,
-					 2,
-					 &found_index,
-					 data,
-					 sizeof(data),
-					 &msg_len,
+	TEST_EQ(verify_tcpci_possible_tx(possible, 2, &found_index, data,
+					 sizeof(data), &msg_len,
 					 PD_T_CHUNKING_NOT_SUPPORTED_MAX),
 		EC_SUCCESS, "%d");
 	mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
@@ -112,7 +107,7 @@ int test_td_pd_src3_e32(void)
 	 * tChunkReceiverRequest max (15ms), the test fails.
 	 */
 	TEST_ASSERT((get_time().val - start_time) <=
-					PD_T_CHUNK_RECEIVER_REQUEST_MAX);
+		    PD_T_CHUNK_RECEIVER_REQUEST_MAX);
 
 	while (chunk < 4) {
 		int next_chunk;
@@ -130,12 +125,9 @@ int test_td_pd_src3_e32(void)
 		setup_chunk_msg(chunk, data);
 		partner_send_msg(TCPCI_MSG_SOP, 0x1F, 7, 1, (uint32_t *)data);
 
-		TEST_EQ(verify_tcpci_tx_with_data(TCPCI_MSG_SOP,
-					0x1F,
-					data,
-					sizeof(data),
-					&msg_len,
-					PD_T_CHUNK_RECEIVER_REQUEST_MAX),
+		TEST_EQ(verify_tcpci_tx_with_data(
+				TCPCI_MSG_SOP, 0x1F, data, sizeof(data),
+				&msg_len, PD_T_CHUNK_RECEIVER_REQUEST_MAX),
 			EC_SUCCESS, "%d");
 		mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
 
@@ -159,12 +151,9 @@ int test_td_pd_src3_e32(void)
 	 * i) If a message is not received within tChunkReceiverRequest max,
 	 * the test fails.
 	 */
-	TEST_EQ(verify_tcpci_tx_with_data(TCPCI_MSG_SOP,
-				0x1F,
-				data,
-				sizeof(data),
-				&msg_len,
-				PD_T_CHUNK_RECEIVER_REQUEST_MAX),
+	TEST_EQ(verify_tcpci_tx_with_data(TCPCI_MSG_SOP, 0x1F, data,
+					  sizeof(data), &msg_len,
+					  PD_T_CHUNK_RECEIVER_REQUEST_MAX),
 		EC_SUCCESS, "%d");
 	mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
 
@@ -207,9 +196,7 @@ int test_td_pd_src3_e32(void)
 	 *	   Number of Data Objects field
 	 */
 	header = *(uint32_t *)&data[1];
-	TEST_EQ(msg_len - 3,
-		PD_HEADER_CNT(header) * 4,
-		"%d");
+	TEST_EQ(msg_len - 3, PD_HEADER_CNT(header) * 4, "%d");
 
 	/*
 	 *	4. The last 2 bytes of the Data Object are 0
diff --git a/test/usb_tcpmv2_td_pd_src3_e7.c b/test/usb_tcpmv2_td_pd_src3_e7.c
index fa2c68b64e..40f65f2b9a 100644
--- a/test/usb_tcpmv2_td_pd_src3_e7.c
+++ b/test/usb_tcpmv2_td_pd_src3_e7.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,7 +22,6 @@
 #define EXT_MSG_DATA_SIZE_1 1
 #define GBSDB_FIXED_BATTERY_0 (0 << 16)
 
-
 static int number_of_fixed_batteries(void)
 {
 	return CONFIG_NUM_FIXED_BATTERIES;
@@ -78,13 +77,8 @@ int test_td_pd_src3_e7(void)
 	possible[1].ctrl_msg = 0;
 	possible[1].data_msg = PD_DATA_SOURCE_CAP;
 
-	TEST_EQ(verify_tcpci_possible_tx(possible,
-					 2,
-					 &found_index,
-					 data,
-					 sizeof(data),
-					 &msg_len,
-					 0),
+	TEST_EQ(verify_tcpci_possible_tx(possible, 2, &found_index, data,
+					 sizeof(data), &msg_len, 0),
 		EC_SUCCESS, "%d");
 	if (found_index == 0) {
 		mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
@@ -104,8 +98,7 @@ int test_td_pd_src3_e7(void)
 		mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
 		task_wait_event(10 * MSEC);
 
-		if (data[HEADER_BYTE_OFFSET +
-			 HEADER_BYTE_CNT +
+		if (data[HEADER_BYTE_OFFSET + HEADER_BYTE_CNT +
 			 SRC_CAP_EXT_NUM_BATTERY_OFFSET] == 0)
 			return EC_SUCCESS;
 	}
@@ -114,11 +107,9 @@ int test_td_pd_src3_e7(void)
 	 * e) The Tester waits until it can start an AMS (Run PROC.PD.E3) and
 	 *    sends a Get_Battery_Status message to the UUT
 	 */
-	ext_msg = EXT_MSG_CHUNKED |
-		  EXT_MSG_DATA_SIZE_1 |
-		  GBSDB_FIXED_BATTERY_0;
+	ext_msg = EXT_MSG_CHUNKED | EXT_MSG_DATA_SIZE_1 | GBSDB_FIXED_BATTERY_0;
 	partner_send_msg(TCPCI_MSG_SOP, PD_EXT_GET_BATTERY_STATUS, 1, 1,
-			&ext_msg);
+			 &ext_msg);
 
 	/*
 	 * f) If a Battery_Status message is not received within
@@ -127,10 +118,8 @@ int test_td_pd_src3_e7(void)
 	 *    been transmitted to the time the first bit of the Battery_Status
 	 *    message preamble has been received.
 	 */
-	TEST_EQ(verify_tcpci_tx_timeout(TCPCI_MSG_SOP,
-					0,
-					PD_DATA_BATTERY_STATUS,
-					(15 * MSEC)),
+	TEST_EQ(verify_tcpci_tx_timeout(TCPCI_MSG_SOP, 0,
+					PD_DATA_BATTERY_STATUS, (15 * MSEC)),
 		EC_SUCCESS, "%d");
 	mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
 	task_wait_event(10 * MSEC);
diff --git a/test/usb_tcpmv2_td_pd_src3_e8.c b/test/usb_tcpmv2_td_pd_src3_e8.c
index b884156d43..8686226a50 100644
--- a/test/usb_tcpmv2_td_pd_src3_e8.c
+++ b/test/usb_tcpmv2_td_pd_src3_e8.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,10 +24,10 @@
 #define SCEDB_NUM_BYTES 24
 
 #define BSDO_NUM_BYTES 4
-#define BSDO_INV_BATTERY_REF(bsdo)	(((bsdo) >> 8) & 1)
-#define BSDO_BATTERY_PRESENT(bsdo)	(((bsdo) >> 9) & 1)
-#define BSDO_BATTERY_CHRG_STS(bsdo)	(((bsdo) >> 10) & 3)
-#define BSDO_BATTERY_INFO(bsdo)		(((bsdo) >> 8) & 0xFF)
+#define BSDO_INV_BATTERY_REF(bsdo) (((bsdo) >> 8) & 1)
+#define BSDO_BATTERY_PRESENT(bsdo) (((bsdo) >> 9) & 1)
+#define BSDO_BATTERY_CHRG_STS(bsdo) (((bsdo) >> 10) & 3)
+#define BSDO_BATTERY_INFO(bsdo) (((bsdo) >> 8) & 0xFF)
 
 static int number_of_fixed_batteries(void)
 {
@@ -88,33 +88,26 @@ int test_td_pd_src3_e8(void)
 	possible[1].ctrl_msg = 0;
 	possible[1].data_msg = PD_DATA_SOURCE_CAP;
 
-	TEST_EQ(verify_tcpci_possible_tx(possible,
-					 2,
-					 &found_index,
-					 data,
-					 sizeof(data),
-					 &msg_len,
-					 0),
+	TEST_EQ(verify_tcpci_possible_tx(possible, 2, &found_index, data,
+					 sizeof(data), &msg_len, 0),
 		EC_SUCCESS, "%d");
 	if (found_index == 1) {
 		mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
 		task_wait_event(10 * MSEC);
 
-		TEST_EQ(msg_len, HEADER_BYTE_OFFSET +
-				 HEADER_NUM_BYTES +
-				 SCEDB_NUM_BYTES,
+		TEST_EQ(msg_len,
+			HEADER_BYTE_OFFSET + HEADER_NUM_BYTES + SCEDB_NUM_BYTES,
 			"%d");
 
 		num_fixed_batteries =
-				data[HEADER_BYTE_OFFSET +
-				     HEADER_NUM_BYTES +
-				     SCEDB_NUM_BATTERY_OFFSET] &
-				0x0F;
+			data[HEADER_BYTE_OFFSET + HEADER_NUM_BYTES +
+			     SCEDB_NUM_BATTERY_OFFSET] &
+			0x0F;
 		num_swappable_battery_slots =
-				(data[HEADER_BYTE_OFFSET +
-				      HEADER_NUM_BYTES +
-				      SCEDB_NUM_BATTERY_OFFSET] >> 4) &
-				0x0F;
+			(data[HEADER_BYTE_OFFSET + HEADER_NUM_BYTES +
+			      SCEDB_NUM_BATTERY_OFFSET] >>
+			 4) &
+			0x0F;
 	}
 	/*
 	 *    If a Not_Supported message is received, the Tester reads the
@@ -141,8 +134,7 @@ int test_td_pd_src3_e8(void)
 		uint16_t header;
 		uint32_t bsdo;
 
-		ext_msg = EXT_MSG_CHUNKED | EXT_MSG_DATA_SIZE_1 |
-			  (ref << 16);
+		ext_msg = EXT_MSG_CHUNKED | EXT_MSG_DATA_SIZE_1 | (ref << 16);
 		partner_send_msg(TCPCI_MSG_SOP, PD_EXT_GET_BATTERY_STATUS, 1, 1,
 				 &ext_msg);
 
@@ -151,17 +143,13 @@ int test_td_pd_src3_e8(void)
 		 *    verifies:
 		 */
 		TEST_EQ(verify_tcpci_tx_with_data(TCPCI_MSG_SOP,
-						  PD_DATA_BATTERY_STATUS,
-						  data,
-						  sizeof(data),
-						  &msg_len,
-						  0),
+						  PD_DATA_BATTERY_STATUS, data,
+						  sizeof(data), &msg_len, 0),
 			EC_SUCCESS, "%d");
 		mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
 		task_wait_event(10 * MSEC);
-		TEST_EQ(msg_len, HEADER_BYTE_OFFSET +
-				 HEADER_NUM_BYTES +
-				 BSDO_NUM_BYTES,
+		TEST_EQ(msg_len,
+			HEADER_BYTE_OFFSET + HEADER_NUM_BYTES + BSDO_NUM_BYTES,
 			"%d");
 
 		/*
@@ -200,33 +188,26 @@ int test_td_pd_src3_e8(void)
 		 *    8. If Invalid Battery Reference field is 1, Battery is
 		 *       present field shall be 0
 		 */
-		bsdo = UINT32_FROM_BYTE_ARRAY_LE(data, HEADER_BYTE_OFFSET +
-						       HEADER_NUM_BYTES);
+		bsdo = UINT32_FROM_BYTE_ARRAY_LE(
+			data, HEADER_BYTE_OFFSET + HEADER_NUM_BYTES);
 
 		/* FIXED BATTERY */
 		if (ref < 4) {
 			if (ref < num_fixed_batteries) {
-				TEST_EQ(BSDO_INV_BATTERY_REF(bsdo),
-					0, "%d");
-				TEST_EQ(BSDO_BATTERY_PRESENT(bsdo),
-					1, "%d");
+				TEST_EQ(BSDO_INV_BATTERY_REF(bsdo), 0, "%d");
+				TEST_EQ(BSDO_BATTERY_PRESENT(bsdo), 1, "%d");
 			} else {
-				TEST_EQ(BSDO_INV_BATTERY_REF(bsdo),
-					1, "%d");
-				TEST_EQ(BSDO_BATTERY_PRESENT(bsdo),
-					0, "%d");
+				TEST_EQ(BSDO_INV_BATTERY_REF(bsdo), 1, "%d");
+				TEST_EQ(BSDO_BATTERY_PRESENT(bsdo), 0, "%d");
 			}
 		}
 		/* BATTERY SLOT */
 		else {
 			if ((ref - 4) < num_swappable_battery_slots) {
-				TEST_EQ(BSDO_INV_BATTERY_REF(bsdo),
-					0, "%d");
+				TEST_EQ(BSDO_INV_BATTERY_REF(bsdo), 0, "%d");
 			} else {
-				TEST_EQ(BSDO_INV_BATTERY_REF(bsdo),
-					1, "%d");
-				TEST_EQ(BSDO_BATTERY_PRESENT(bsdo),
-					0, "%d");
+				TEST_EQ(BSDO_INV_BATTERY_REF(bsdo), 1, "%d");
+				TEST_EQ(BSDO_BATTERY_PRESENT(bsdo), 0, "%d");
 			}
 		}
 
diff --git a/test/usb_tcpmv2_td_pd_src3_e9.c b/test/usb_tcpmv2_td_pd_src3_e9.c
index 49b8209669..59b7a22d74 100644
--- a/test/usb_tcpmv2_td_pd_src3_e9.c
+++ b/test/usb_tcpmv2_td_pd_src3_e9.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,8 +23,8 @@
 #define SCEDB_NUM_BATTERY_OFFSET 22
 #define SCEDB_NUM_BYTES 24
 
-#define BSDO_INV_BATTERY_REF(bsdo)	(((bsdo) >> 8) & 1)
-#define BSDO_BATTERY_INFO(bsdo)		(((bsdo) >> 8) & 0xFF)
+#define BSDO_INV_BATTERY_REF(bsdo) (((bsdo) >> 8) & 1)
+#define BSDO_BATTERY_INFO(bsdo) (((bsdo) >> 8) & 0xFF)
 
 static int number_of_fixed_batteries(void)
 {
@@ -84,33 +84,26 @@ int test_td_pd_src3_e9(void)
 	possible[1].ctrl_msg = 0;
 	possible[1].data_msg = PD_DATA_SOURCE_CAP;
 
-	TEST_EQ(verify_tcpci_possible_tx(possible,
-					 2,
-					 &found_index,
-					 data,
-					 sizeof(data),
-					 &msg_len,
-					 0),
+	TEST_EQ(verify_tcpci_possible_tx(possible, 2, &found_index, data,
+					 sizeof(data), &msg_len, 0),
 		EC_SUCCESS, "%d");
 	if (found_index == 1) {
 		mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
 		task_wait_event(10 * MSEC);
 
-		TEST_EQ(msg_len, HEADER_BYTE_OFFSET +
-				 HEADER_NUM_BYTES +
-				 SCEDB_NUM_BYTES,
+		TEST_EQ(msg_len,
+			HEADER_BYTE_OFFSET + HEADER_NUM_BYTES + SCEDB_NUM_BYTES,
 			"%d");
 
 		num_fixed_batteries =
-				data[HEADER_BYTE_OFFSET +
-				     HEADER_NUM_BYTES +
-				     SCEDB_NUM_BATTERY_OFFSET] &
-				0x0F;
+			data[HEADER_BYTE_OFFSET + HEADER_NUM_BYTES +
+			     SCEDB_NUM_BATTERY_OFFSET] &
+			0x0F;
 		num_swappable_battery_slots =
-				(data[HEADER_BYTE_OFFSET +
-				      HEADER_NUM_BYTES +
-				      SCEDB_NUM_BATTERY_OFFSET] >> 4) &
-				0x0F;
+			(data[HEADER_BYTE_OFFSET + HEADER_NUM_BYTES +
+			      SCEDB_NUM_BATTERY_OFFSET] >>
+			 4) &
+			0x0F;
 	}
 	/*
 	 *    If a Not_Supported message is received, the Tester reads the
@@ -133,8 +126,7 @@ int test_td_pd_src3_e9(void)
 	 *    to 8, to the UUT.
 	 */
 	ref = 8;
-	ext_msg = EXT_MSG_CHUNKED | EXT_MSG_DATA_SIZE_1 |
-		  (ref << 16);
+	ext_msg = EXT_MSG_CHUNKED | EXT_MSG_DATA_SIZE_1 | (ref << 16);
 	partner_send_msg(TCPCI_MSG_SOP, PD_EXT_GET_BATTERY_STATUS, 1, 1,
 			 &ext_msg);
 
@@ -153,13 +145,8 @@ int test_td_pd_src3_e9(void)
 	possible[1].ctrl_msg = 0;
 	possible[1].data_msg = PD_DATA_BATTERY_STATUS;
 
-	TEST_EQ(verify_tcpci_possible_tx(possible,
-					 2,
-					 &found_index,
-					 data,
-					 sizeof(data),
-					 &msg_len,
-					 0),
+	TEST_EQ(verify_tcpci_possible_tx(possible, 2, &found_index, data,
+					 sizeof(data), &msg_len, 0),
 		EC_SUCCESS, "%d");
 	if (found_index == 0) {
 		mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS);
@@ -210,8 +197,8 @@ int test_td_pd_src3_e9(void)
 		 *    6. Invalid Battery Reference field (Bit 0) of the
 		 *       Battery Info field in the BSDO is 1
 		 */
-		bsdo = UINT32_FROM_BYTE_ARRAY_LE(data, HEADER_BYTE_OFFSET +
-						       HEADER_NUM_BYTES);
+		bsdo = UINT32_FROM_BYTE_ARRAY_LE(
+			data, HEADER_BYTE_OFFSET + HEADER_NUM_BYTES);
 		TEST_EQ(BSDO_INV_BATTERY_REF(bsdo), 1, "%d");
 
 		/*
diff --git a/test/usb_tcpmv2_td_pd_src_e1.c b/test/usb_tcpmv2_td_pd_src_e1.c
index a617f90ca2..cfb62764b2 100644
--- a/test/usb_tcpmv2_td_pd_src_e1.c
+++ b/test/usb_tcpmv2_td_pd_src_e1.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -38,8 +38,7 @@ int test_td_pd_src_e1(void)
 	 *    is not received from the Provider within 250 ms (tFirstSourceCap
 	 *    max) after VBus present.
 	 */
-	TEST_EQ(verify_tcpci_tx_timeout(TCPCI_MSG_SOP, 0,
-					PD_DATA_SOURCE_CAP,
+	TEST_EQ(verify_tcpci_tx_timeout(TCPCI_MSG_SOP, 0, PD_DATA_SOURCE_CAP,
 					250 * MSEC),
 		EC_SUCCESS, "%d");
 
diff --git a/test/usb_tcpmv2_td_pd_src_e2.c b/test/usb_tcpmv2_td_pd_src_e2.c
index f0e1b64c7e..cabba40bb9 100644
--- a/test/usb_tcpmv2_td_pd_src_e2.c
+++ b/test/usb_tcpmv2_td_pd_src_e2.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -63,12 +63,8 @@ int test_td_pd_src_e2(void)
 	 *    Provider, if the Specification Revision field is 10b
 	 *    (Rev 3.0), the test passes and stops here,
 	 */
-	TEST_EQ(verify_tcpci_tx_with_data(TCPCI_MSG_SOP,
-					  PD_DATA_SOURCE_CAP,
-					  data,
-					  sizeof(data),
-					  &msg_len,
-					  0),
+	TEST_EQ(verify_tcpci_tx_with_data(TCPCI_MSG_SOP, PD_DATA_SOURCE_CAP,
+					  data, sizeof(data), &msg_len, 0),
 		EC_SUCCESS, "%d");
 	TEST_GE(msg_len, HEADER_BYTE_CNT, "%d");
 
@@ -95,7 +91,7 @@ int test_td_pd_src_e2(void)
 	TEST_EQ(revision, REVISION_2, "%d");
 	TEST_EQ(PD_HEADER_DROLE(header), PD_ROLE_DFP, "%d");
 	TEST_EQ(PD_HEADER_TYPE(header), PD_DATA_SOURCE_CAP, "%d");
-	TEST_EQ(header & (BIT(4)|BIT(15)), 0, "%d");
+	TEST_EQ(header & (BIT(4) | BIT(15)), 0, "%d");
 
 	/*
 	 * c) For the first PDO, the Tester verifies:
@@ -103,8 +99,8 @@ int test_td_pd_src_e2(void)
 	 *    2. Voltage field = 100 (5 V)
 	 *    3. Bits 24..22 = 000b (Reserved)
 	 */
-	pdo = UINT32_FROM_BYTE_ARRAY_LE(data, HEADER_BYTE_OFFSET +
-					      HEADER_BYTE_CNT);
+	pdo = UINT32_FROM_BYTE_ARRAY_LE(data,
+					HEADER_BYTE_OFFSET + HEADER_BYTE_CNT);
 
 	type = pdo & PDO_TYPE_MASK;
 	TEST_EQ(type, PDO_TYPE_FIXED, "%d");
@@ -132,8 +128,7 @@ int test_td_pd_src_e2(void)
 		int offset;
 		uint32_t voltage;
 
-		offset = HEADER_BYTE_OFFSET +
-			 HEADER_BYTE_CNT +
+		offset = HEADER_BYTE_OFFSET + HEADER_BYTE_CNT +
 			 (i * PDO_BYTE_CNT);
 		pdo = UINT32_FROM_BYTE_ARRAY_LE(data, offset);
 
diff --git a/test/usb_tcpmv2_td_pd_src_e5.c b/test/usb_tcpmv2_td_pd_src_e5.c
index eac1b93e8f..ef40ee75cf 100644
--- a/test/usb_tcpmv2_td_pd_src_e5.c
+++ b/test/usb_tcpmv2_td_pd_src_e5.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -71,12 +71,12 @@ int test_td_pd_src_e5(void)
 	end_time += 6 * MSEC;
 	while (get_time().val < end_time) {
 		if (mock_tcpci_get_reg(TCPC_REG_TRANSMIT) ==
-						TCPCI_MSG_TX_HARD_RESET)
+		    TCPCI_MSG_TX_HARD_RESET)
 			break;
 		task_wait_event(1 * MSEC);
 	}
-	TEST_EQ(mock_tcpci_get_reg(TCPC_REG_TRANSMIT),
-		TCPCI_MSG_TX_HARD_RESET, "%d");
+	TEST_EQ(mock_tcpci_get_reg(TCPC_REG_TRANSMIT), TCPCI_MSG_TX_HARD_RESET,
+		"%d");
 	mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS | TCPC_REG_ALERT_TX_FAILED);
 	mock_tcpci_set_reg(TCPC_REG_TRANSMIT, 0);
 	task_wait_event(1 * MSEC);
diff --git a/test/usb_tcpmv2_td_pd_vndi3_e3.c b/test/usb_tcpmv2_td_pd_vndi3_e3.c
index cbfc0d75e3..8157835328 100644
--- a/test/usb_tcpmv2_td_pd_vndi3_e3.c
+++ b/test/usb_tcpmv2_td_pd_vndi3_e3.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,10 +11,8 @@
 #include "usb_tcpmv2_compliance.h"
 #include "usb_tc_sm.h"
 
-uint32_t vdo = VDO(USB_SID_PD, 1,
-		   VDO_SVDM_VERS(VDM_VER20) |
-		   CMD_DISCOVER_IDENT);
-
+uint32_t vdo =
+	VDO(USB_SID_PD, 1, VDO_SVDM_VERS(VDM_VER20) | CMD_DISCOVER_IDENT);
 
 /*****************************************************************************
  * TD.PD.VNDI3.E3.VDM Identity
@@ -32,8 +30,8 @@ static int td_pd_vndi3_e3(enum pd_data_role data_role)
 	/*
 	 * a) Run PROC.PD.E1 Bring-up according to the UUT role.
 	 */
-	TEST_EQ(proc_pd_e1(data_role, INITIAL_AND_ALREADY_ATTACHED),
-		EC_SUCCESS, "%d");
+	TEST_EQ(proc_pd_e1(data_role, INITIAL_AND_ALREADY_ATTACHED), EC_SUCCESS,
+		"%d");
 
 	/*
 	 * Make sure we are idle. Reject everything that is pending
@@ -43,8 +41,7 @@ static int td_pd_vndi3_e3(enum pd_data_role data_role)
 	/*
 	 * b) Tester executes a Discover Identity exchange
 	 */
-	partner_send_msg(TCPCI_MSG_SOP, PD_DATA_VENDOR_DEF,
-			 1, 0, &vdo);
+	partner_send_msg(TCPCI_MSG_SOP, PD_DATA_VENDOR_DEF, 1, 0, &vdo);
 
 	/*
 	 * c) If the UUT is not a cable and if Responds_To_Discov_SOP is set to
diff --git a/test/usb_test/Makefile b/test/usb_test/Makefile
index e18e4a7c3b..df21c7d331 100644
--- a/test/usb_test/Makefile
+++ b/test/usb_test/Makefile
@@ -1,4 +1,4 @@
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/test/usb_test/device_configuration.c b/test/usb_test/device_configuration.c
index 69f889c2d3..06c71fefd9 100644
--- a/test/usb_test/device_configuration.c
+++ b/test/usb_test/device_configuration.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
+ * Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,8 +13,8 @@
 #include <string.h>
 
 /* Options */
-static uint16_t vid = 0x18d1;			/* Google */
-static uint16_t pid = 0x5014;			/* Cr50 */
+static uint16_t vid = 0x18d1; /* Google */
+static uint16_t pid = 0x5014; /* Cr50 */
 
 static char *progname;
 
@@ -25,7 +25,8 @@ static void usage(int errs)
 	       "Set/Get the USB Device Configuration value\n"
 	       "\n"
 	       "The default vid:pid is %04x:%04x\n"
-	       "\n", progname, vid, pid);
+	       "\n",
+	       progname, vid, pid);
 
 	exit(!!errs);
 }
@@ -49,14 +50,13 @@ static void stupid_usb(const char *format, ...)
 	exit(1);
 }
 
-
 int main(int argc, char *argv[])
 {
 	int r = 1;
 	int errorcnt = 0;
 	int do_set = 0;
 	uint16_t setval = 0;
-	uint8_t buf[80];			/* Arbitrary size */
+	uint8_t buf[80]; /* Arbitrary size */
 	int i;
 
 	progname = strrchr(argv[0], '/');
@@ -65,13 +65,13 @@ int main(int argc, char *argv[])
 	else
 		progname = argv[0];
 
-	opterr = 0;				/* quiet, you */
+	opterr = 0; /* quiet, you */
 	while ((i = getopt(argc, argv, "")) != -1) {
 		switch (i) {
 		case 'h':
 			usage(errorcnt);
 			break;
-		case 0:				/* auto-handled option */
+		case 0: /* auto-handled option */
 			break;
 		case '?':
 			if (optopt)
@@ -111,8 +111,8 @@ int main(int argc, char *argv[])
 
 	r = libusb_init(NULL);
 	if (r) {
-		printf("libusb_init() returned 0x%x: %s\n",
-		       r, libusb_error_name(r));
+		printf("libusb_init() returned 0x%x: %s\n", r,
+		       libusb_error_name(r));
 		return 1;
 	}
 
@@ -122,41 +122,36 @@ int main(int argc, char *argv[])
 		stupid_usb("Can't open device %04x:%04x\n", vid, pid);
 	}
 
-
 	/* Set config*/
 	if (do_set) {
 		printf("SetCfg %d\n", setval);
-		r = libusb_control_transfer(
-			devh,
-			0x00,			/* bmRequestType */
-			0x09,			/* bRequest */
-			setval,			/* wValue */
-			0x0000,			/* wIndex */
-			NULL,			/* data */
-			0x0000,			/* wLength */
-			1000);			/* timeout (ms) */
+		r = libusb_control_transfer(devh, 0x00, /* bmRequestType */
+					    0x09, /* bRequest */
+					    setval, /* wValue */
+					    0x0000, /* wIndex */
+					    NULL, /* data */
+					    0x0000, /* wLength */
+					    1000); /* timeout (ms) */
 
 		if (r < 0)
-			printf("transfer returned 0x%x %s\n",
-			       r, libusb_error_name(r));
+			printf("transfer returned 0x%x %s\n", r,
+			       libusb_error_name(r));
 	}
 
 	/* Get config */
 	memset(buf, 0, sizeof(buf));
 
-	r = libusb_control_transfer(
-		devh,
-		0x80,				/* bmRequestType */
-		0x08,				/* bRequest */
-		0x0000,				/* wValue */
-		0x0000,				/* wIndex */
-		buf,				/* data */
-		0x0001,				/* wLength */
-		1000);				/* timeout (ms) */
+	r = libusb_control_transfer(devh, 0x80, /* bmRequestType */
+				    0x08, /* bRequest */
+				    0x0000, /* wValue */
+				    0x0000, /* wIndex */
+				    buf, /* data */
+				    0x0001, /* wLength */
+				    1000); /* timeout (ms) */
 
 	if (r <= 0)
-		stupid_usb("GetCfg transfer() returned 0x%x %s\n",
-			   r, libusb_error_name(r));
+		stupid_usb("GetCfg transfer() returned 0x%x %s\n", r,
+			   libusb_error_name(r));
 
 	printf("GetCfg returned %d bytes:", r);
 	for (i = 0; i < r; i++)
diff --git a/test/usb_typec_ctvpd.c b/test/usb_typec_ctvpd.c
index 583c529fca..71d543cec0 100644
--- a/test/usb_typec_ctvpd.c
+++ b/test/usb_typec_ctvpd.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -18,12 +18,12 @@
 #include "usb_sm_checks.h"
 #include "vpd_api.h"
 
-#define PORT0	0
+#define PORT0 0
 
-enum cc_type {CC1, CC2};
-enum vbus_type {VBUS_0 = 0, VBUS_5 = 5000};
-enum vconn_type {VCONN_0 = 0, VCONN_3 = 3000, VCONN_5 = 5000};
-enum snk_con_voltage_type {SRC_CON_DEF, SRC_CON_1_5, SRC_CON_3_0};
+enum cc_type { CC1, CC2 };
+enum vbus_type { VBUS_0 = 0, VBUS_5 = 5000 };
+enum vconn_type { VCONN_0 = 0, VCONN_3 = 3000, VCONN_5 = 5000 };
+enum snk_con_voltage_type { SRC_CON_DEF, SRC_CON_1_5, SRC_CON_3_0 };
 
 /*
  * These enum definitions are declared in usb_tc_*_sm and are private to that
@@ -92,15 +92,15 @@ static int ct_connect_sink(enum cc_type cc, enum snk_con_voltage_type v)
 	switch (v) {
 	case SRC_CON_DEF:
 		ret = (cc) ? mock_set_cc2_rp3a0_rd_l(PD_SRC_DEF_RD_THRESH_MV) :
-			mock_set_cc1_rp3a0_rd_l(PD_SRC_DEF_RD_THRESH_MV);
+			     mock_set_cc1_rp3a0_rd_l(PD_SRC_DEF_RD_THRESH_MV);
 		break;
 	case SRC_CON_1_5:
 		ret = (cc) ? mock_set_cc2_rp3a0_rd_l(PD_SRC_1_5_RD_THRESH_MV) :
-			mock_set_cc1_rp3a0_rd_l(PD_SRC_1_5_RD_THRESH_MV);
+			     mock_set_cc1_rp3a0_rd_l(PD_SRC_1_5_RD_THRESH_MV);
 		break;
 	case SRC_CON_3_0:
 		ret = (cc) ? mock_set_cc2_rp3a0_rd_l(PD_SRC_3_0_RD_THRESH_MV) :
-			mock_set_cc1_rp3a0_rd_l(PD_SRC_3_0_RD_THRESH_MV);
+			     mock_set_cc1_rp3a0_rd_l(PD_SRC_3_0_RD_THRESH_MV);
 		break;
 	default:
 		ret = 0;
@@ -124,7 +124,7 @@ static int ct_connect_source(enum cc_type cc, enum vbus_type vbus)
 {
 	mock_set_ct_vbus(vbus);
 	return (cc) ? mock_set_cc2_rpusb_odh(PD_SNK_VA_MV) :
-				mock_set_cc1_rpusb_odh(PD_SNK_VA_MV);
+		      mock_set_cc1_rpusb_odh(PD_SNK_VA_MV);
 }
 
 static int ct_disconnect_source(void)
@@ -297,14 +297,15 @@ void inc_rx_id(int port)
 static int verify_goodcrc(int port, int role, int id)
 {
 	return pd_test_tx_msg_verify_sop_prime(port) &&
-		pd_test_tx_msg_verify_short(port, PD_HEADER(PD_CTRL_GOOD_CRC,
-					role, role, id, 0, 0, 0)) &&
-		pd_test_tx_msg_verify_crc(port) &&
-		pd_test_tx_msg_verify_eop(port);
+	       pd_test_tx_msg_verify_short(port,
+					   PD_HEADER(PD_CTRL_GOOD_CRC, role,
+						     role, id, 0, 0, 0)) &&
+	       pd_test_tx_msg_verify_crc(port) &&
+	       pd_test_tx_msg_verify_eop(port);
 }
 
 static void simulate_rx_msg(int port, uint16_t header, int cnt,
-							const uint32_t *data)
+			    const uint32_t *data)
 {
 	int i;
 
@@ -330,20 +331,20 @@ static void simulate_rx_msg(int port, uint16_t header, int cnt,
 
 static void simulate_goodcrc(int port, int role, int id)
 {
-	simulate_rx_msg(port, PD_HEADER(PD_CTRL_GOOD_CRC, role, role, id, 0,
-						pd_port[port].rev, 0), 0, NULL);
+	simulate_rx_msg(port,
+			PD_HEADER(PD_CTRL_GOOD_CRC, role, role, id, 0,
+				  pd_port[port].rev, 0),
+			0, NULL);
 }
 
 static void simulate_discovery_identity(int port)
 {
-	uint16_t header = PD_HEADER(PD_DATA_VENDOR_DEF, PD_ROLE_SOURCE,
-					1, pd_port[port].msg_rx_id,
-					1, pd_port[port].rev, 0);
-	uint32_t msg = VDO(USB_SID_PD,
-			1, /* Structured VDM */
-			VDO_SVDM_VERS(1) |
-			VDO_CMDT(CMDT_INIT) |
-			CMD_DISCOVER_IDENT);
+	uint16_t header = PD_HEADER(PD_DATA_VENDOR_DEF, PD_ROLE_SOURCE, 1,
+				    pd_port[port].msg_rx_id, 1,
+				    pd_port[port].rev, 0);
+	uint32_t msg = VDO(USB_SID_PD, 1, /* Structured VDM */
+			   VDO_SVDM_VERS(1) | VDO_CMDT(CMDT_INIT) |
+				   CMD_DISCOVER_IDENT);
 
 	simulate_rx_msg(port, header, 1, (const uint32_t *)&msg);
 }
@@ -538,35 +539,27 @@ static int test_vpd_host_src_detection_vconn(void)
 static int test_vpd_host_src_detection_message_reception(void)
 {
 	int port = PORT0;
-	uint32_t expected_vdm_header = VDO(USB_VID_GOOGLE,
-			1, /* Structured VDM */
-			VDO_SVDM_VERS(1) |
-			VDO_CMDT(CMDT_RSP_ACK) |
-			CMD_DISCOVER_IDENT);
-	uint32_t expected_vdo_id_header = VDO_IDH(
-			0, /* Not a USB Host */
+	uint32_t expected_vdm_header = VDO(
+		USB_VID_GOOGLE, 1, /* Structured VDM */
+		VDO_SVDM_VERS(1) | VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_IDENT);
+	uint32_t expected_vdo_id_header =
+		VDO_IDH(0, /* Not a USB Host */
 			1, /* Capable of being enumerated as USB Device */
-			IDH_PTYPE_VPD,
-			0, /* Modal Operation Not Supported */
+			IDH_PTYPE_VPD, 0, /* Modal Operation Not Supported */
 			USB_VID_GOOGLE);
 	uint32_t expected_vdo_cert = 0;
-	uint32_t expected_vdo_product = VDO_PRODUCT(
-			CONFIG_USB_PID,
-			USB_BCD_DEVICE);
+	uint32_t expected_vdo_product =
+		VDO_PRODUCT(CONFIG_USB_PID, USB_BCD_DEVICE);
 	uint32_t expected_vdo_vpd = VDO_VPD(
-			VPD_HW_VERSION,
-			VPD_FW_VERSION,
-			VPD_MAX_VBUS_20V,
-			IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_CT_CURRENT
-						: 0,
-			IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_VBUS_IMP(
-						VPD_VBUS_IMPEDANCE)
-						: 0,
-			IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_GND_IMP(
-						VPD_GND_IMPEDANCE)
-						: 0,
-			IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_CTS_SUPPORTED
-						: VPD_CTS_NOT_SUPPORTED);
+		VPD_HW_VERSION, VPD_FW_VERSION, VPD_MAX_VBUS_20V,
+		IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_CT_CURRENT : 0,
+		IS_ENABLED(CONFIG_USB_CTVPD) ?
+			VPD_VBUS_IMP(VPD_VBUS_IMPEDANCE) :
+			0,
+		IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_GND_IMP(VPD_GND_IMPEDANCE) :
+					       0,
+		IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_CTS_SUPPORTED :
+					       VPD_CTS_NOT_SUPPORTED);
 
 	mock_set_vconn(VCONN_0);
 	host_disconnect_source();
@@ -608,8 +601,8 @@ static int test_vpd_host_src_detection_message_reception(void)
 	simulate_discovery_identity(port);
 	task_wait_event(30 * MSEC);
 
-	TEST_ASSERT(verify_goodcrc(port,
-				PD_ROLE_SINK, pd_port[port].msg_rx_id));
+	TEST_ASSERT(
+		verify_goodcrc(port, PD_ROLE_SINK, pd_port[port].msg_rx_id));
 
 	task_wake(PD_PORT_TO_TASK_ID(port));
 	task_wait_event(30 * MSEC);
@@ -617,9 +610,10 @@ static int test_vpd_host_src_detection_message_reception(void)
 
 	/* Test Discover Identity Ack */
 	TEST_ASSERT(pd_test_tx_msg_verify_sop_prime(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
-			PD_HEADER(PD_DATA_VENDOR_DEF, PD_PLUG_FROM_CABLE, 0,
-			pd_port[port].msg_tx_id, 5, pd_port[port].rev, 0)));
+	TEST_ASSERT(pd_test_tx_msg_verify_short(
+		port,
+		PD_HEADER(PD_DATA_VENDOR_DEF, PD_PLUG_FROM_CABLE, 0,
+			  pd_port[port].msg_tx_id, 5, pd_port[port].rev, 0)));
 	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_vdm_header));
 	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_vdo_id_header));
 	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_vdo_cert));
@@ -648,7 +642,6 @@ static int test_vpd_host_src_detection_message_reception(void)
 
 	TEST_EQ(get_state_tc(port), TC_UNATTACHED_SNK, "%d");
 
-
 	return EC_SUCCESS;
 }
 
@@ -992,35 +985,27 @@ static int test_ctvpd_behavior_case3(void)
 static int test_ctvpd_behavior_case4(void)
 {
 	int port = PORT0;
-	uint32_t expected_vdm_header = VDO(USB_VID_GOOGLE,
-			1, /* Structured VDM */
-			VDO_SVDM_VERS(1) |
-			VDO_CMDT(CMDT_RSP_ACK) |
-			CMD_DISCOVER_IDENT);
-	uint32_t expected_vdo_id_header = VDO_IDH(
-			0, /* Not a USB Host */
+	uint32_t expected_vdm_header = VDO(
+		USB_VID_GOOGLE, 1, /* Structured VDM */
+		VDO_SVDM_VERS(1) | VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_IDENT);
+	uint32_t expected_vdo_id_header =
+		VDO_IDH(0, /* Not a USB Host */
 			1, /* Capable of being enumerated as USB Device */
-			IDH_PTYPE_VPD,
-			0, /* Modal Operation Not Supported */
+			IDH_PTYPE_VPD, 0, /* Modal Operation Not Supported */
 			USB_VID_GOOGLE);
 	uint32_t expected_vdo_cert = 0;
-	uint32_t expected_vdo_product = VDO_PRODUCT(
-			CONFIG_USB_PID,
-			USB_BCD_DEVICE);
+	uint32_t expected_vdo_product =
+		VDO_PRODUCT(CONFIG_USB_PID, USB_BCD_DEVICE);
 	uint32_t expected_vdo_vpd = VDO_VPD(
-			VPD_HW_VERSION,
-			VPD_FW_VERSION,
-			VPD_MAX_VBUS_20V,
-			IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_CT_CURRENT
-						: 0,
-			IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_VBUS_IMP(
-						VPD_VBUS_IMPEDANCE)
-						: 0,
-			IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_GND_IMP(
-						VPD_GND_IMPEDANCE)
-						: 0,
-			IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_CTS_SUPPORTED
-						: VPD_CTS_NOT_SUPPORTED);
+		VPD_HW_VERSION, VPD_FW_VERSION, VPD_MAX_VBUS_20V,
+		IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_CT_CURRENT : 0,
+		IS_ENABLED(CONFIG_USB_CTVPD) ?
+			VPD_VBUS_IMP(VPD_VBUS_IMPEDANCE) :
+			0,
+		IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_GND_IMP(VPD_GND_IMPEDANCE) :
+					       0,
+		IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_CTS_SUPPORTED :
+					       VPD_CTS_NOT_SUPPORTED);
 
 	init_port(port);
 	mock_set_vconn(VCONN_0);
@@ -1107,8 +1092,8 @@ static int test_ctvpd_behavior_case4(void)
 	simulate_discovery_identity(port);
 	task_wait_event(40 * MSEC);
 
-	TEST_ASSERT(verify_goodcrc(port,
-				PD_ROLE_SINK, pd_port[port].msg_rx_id));
+	TEST_ASSERT(
+		verify_goodcrc(port, PD_ROLE_SINK, pd_port[port].msg_rx_id));
 
 	task_wake(PD_PORT_TO_TASK_ID(port));
 	task_wait_event(40 * MSEC);
@@ -1116,9 +1101,10 @@ static int test_ctvpd_behavior_case4(void)
 
 	/* Test Discover Identity Ack */
 	TEST_ASSERT(pd_test_tx_msg_verify_sop_prime(port));
-	TEST_ASSERT(pd_test_tx_msg_verify_short(port,
-			PD_HEADER(PD_DATA_VENDOR_DEF, PD_PLUG_FROM_CABLE, 0,
-			pd_port[port].msg_tx_id, 5, pd_port[port].rev, 0)));
+	TEST_ASSERT(pd_test_tx_msg_verify_short(
+		port,
+		PD_HEADER(PD_DATA_VENDOR_DEF, PD_PLUG_FROM_CABLE, 0,
+			  pd_port[port].msg_tx_id, 5, pd_port[port].rev, 0)));
 	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_vdm_header));
 	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_vdo_id_header));
 	TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_vdo_cert));
@@ -1268,8 +1254,8 @@ static int test_ctvpd_behavior_case5(void)
 	 *    e. CTVPD connects VBUS from the Charge-Through side to the Host
 	 *       side
 	 */
-	wait_for_state_change(port, PD_T_TRY_CC_DEBOUNCE +
-						PD_T_DRP_TRY + 40 * MSEC);
+	wait_for_state_change(port,
+			      PD_T_TRY_CC_DEBOUNCE + PD_T_DRP_TRY + 40 * MSEC);
 
 	TEST_ASSERT(get_state_tc(port) == TC_TRY_WAIT_SRC);
 	TEST_ASSERT(check_host_rpusb());
@@ -1502,7 +1488,7 @@ static int test_ctvpd_behavior_case6(void)
 }
 #endif
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/usb_typec_ctvpd.tasklist b/test/usb_typec_ctvpd.tasklist
index eb41326e3e..5c7f804157 100644
--- a/test/usb_typec_ctvpd.tasklist
+++ b/test/usb_typec_ctvpd.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/usb_typec_drp_acc_trysrc.c b/test/usb_typec_drp_acc_trysrc.c
index 106370db72..28da84e228 100644
--- a/test/usb_typec_drp_acc_trysrc.c
+++ b/test/usb_typec_drp_acc_trysrc.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -34,11 +34,12 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	},
 };
 
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.driver = &mock_usb_mux_driver,
-	}
-};
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { {
+	.mux =
+		&(const struct usb_mux){
+			.driver = &mock_usb_mux_driver,
+		},
+} };
 
 void charge_manager_set_ceil(int port, enum ceil_requestor requestor, int ceil)
 {
@@ -732,8 +733,8 @@ __maybe_unused static int test_auto_toggle_delay_early_connect(void)
 
 	/* Ensure the auto toggle enable was never called */
 	task_wait_event(SECOND);
-	TEST_EQ(mock_tcpc.first_call_to_enable_auto_toggle,
-		TIMER_DISABLED, "%" PRIu64);
+	TEST_EQ(mock_tcpc.first_call_to_enable_auto_toggle, TIMER_DISABLED,
+		"%" PRIu64);
 
 	/* Ensure that the first CC set call was to Rd. */
 	TEST_GT(cc_pull_count, 0, "%d");
@@ -816,7 +817,7 @@ void before_test(void)
 	mock_tcpc.should_print_call = true;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/usb_typec_drp_acc_trysrc.mocklist b/test/usb_typec_drp_acc_trysrc.mocklist
index 71c2e2cee9..cbff5e73eb 100644
--- a/test/usb_typec_drp_acc_trysrc.mocklist
+++ b/test/usb_typec_drp_acc_trysrc.mocklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/usb_typec_drp_acc_trysrc.tasklist b/test/usb_typec_drp_acc_trysrc.tasklist
index eb41326e3e..5c7f804157 100644
--- a/test/usb_typec_drp_acc_trysrc.tasklist
+++ b/test/usb_typec_drp_acc_trysrc.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/utils.c b/test/utils.c
index 3fc70cdc75..fccfee0923 100644
--- a/test/utils.c
+++ b/test/utils.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -14,171 +14,14 @@
 #include "util.h"
 #include "watchdog.h"
 
-static int test_memmove(void)
-{
-	int i;
-	timestamp_t t0, t1, t2, t3;
-	char *buf;
-	const int buf_size = 1000;
-	const int len = 400;
-	const int iteration = 1000;
-
-	TEST_ASSERT(shared_mem_acquire(buf_size, &buf) == EC_SUCCESS);
-
-	for (i = 0; i < len; ++i)
-		buf[i] = i & 0x7f;
-	for (i = len; i < buf_size; ++i)
-		buf[i] = 0;
-
-	t0 = get_time();
-	for (i = 0; i < iteration; ++i)
-		memmove(buf + 101, buf, len);  /* unaligned */
-	t1 = get_time();
-	TEST_ASSERT_ARRAY_EQ(buf + 101, buf, len);
-	ccprintf(" (speed gain: %" PRId64 " ->", t1.val-t0.val);
-
-	t2 = get_time();
-	for (i = 0; i < iteration; ++i)
-		memmove(buf + 100, buf, len);	  /* aligned */
-	t3 = get_time();
-	ccprintf(" %" PRId64 " us) ", t3.val-t2.val);
-	TEST_ASSERT_ARRAY_EQ(buf + 100, buf, len);
-
-	if (!IS_ENABLED(EMU_BUILD))
-		TEST_ASSERT((t1.val - t0.val) > (t3.val - t2.val));
-
-	/* Test small moves */
-	memmove(buf + 1, buf, 1);
-	TEST_ASSERT_ARRAY_EQ(buf + 1, buf, 1);
-	memmove(buf + 5, buf, 4);
-	memmove(buf + 1, buf, 4);
-	TEST_ASSERT_ARRAY_EQ(buf + 1, buf + 5, 4);
-
-	shared_mem_release(buf);
-	return EC_SUCCESS;
-}
-
-static int test_memcpy(void)
-{
-	int i;
-	timestamp_t t0, t1, t2, t3;
-	char *buf;
-	const int buf_size = 1000;
-	const int len = 400;
-	const int dest_offset = 500;
-	const int iteration = 1000;
-
-	TEST_ASSERT(shared_mem_acquire(buf_size, &buf) == EC_SUCCESS);
-
-	for (i = 0; i < len; ++i)
-		buf[i] = i & 0x7f;
-	for (i = len; i < buf_size; ++i)
-		buf[i] = 0;
-
-	t0 = get_time();
-	for (i = 0; i < iteration; ++i)
-		memcpy(buf + dest_offset + 1, buf, len);  /* unaligned */
-	t1 = get_time();
-	TEST_ASSERT_ARRAY_EQ(buf + dest_offset + 1, buf, len);
-	ccprintf(" (speed gain: %" PRId64 " ->", t1.val-t0.val);
-
-	t2 = get_time();
-	for (i = 0; i < iteration; ++i)
-		memcpy(buf + dest_offset, buf, len);	  /* aligned */
-	t3 = get_time();
-	ccprintf(" %" PRId64 " us) ", t3.val-t2.val);
-	TEST_ASSERT_ARRAY_EQ(buf + dest_offset, buf, len);
-
-	if (!IS_ENABLED(EMU_BUILD))
-		TEST_ASSERT((t1.val - t0.val) > (t3.val - t2.val));
-
-	memcpy(buf + dest_offset + 1, buf + 1, len - 1);
-	TEST_ASSERT_ARRAY_EQ(buf + dest_offset + 1, buf + 1, len - 1);
-
-	/* Test small copies */
-	memcpy(buf + dest_offset, buf, 1);
-	TEST_ASSERT_ARRAY_EQ(buf + dest_offset, buf, 1);
-	memcpy(buf + dest_offset, buf, 4);
-	TEST_ASSERT_ARRAY_EQ(buf + dest_offset, buf, 4);
-	memcpy(buf + dest_offset + 1, buf, 1);
-	TEST_ASSERT_ARRAY_EQ(buf + dest_offset + 1, buf, 1);
-	memcpy(buf + dest_offset + 1, buf, 4);
-	TEST_ASSERT_ARRAY_EQ(buf + dest_offset + 1, buf, 4);
-
-	shared_mem_release(buf);
-	return EC_SUCCESS;
-}
-
-/* Plain memset, used as a reference to measure speed gain */
-static void *dumb_memset(void *dest, int c, int len)
-{
-	char *d = (char *)dest;
-	while (len > 0) {
-		*(d++) = c;
-		len--;
-	}
-	return dest;
-}
-
-static int test_memset(void)
-{
-	int i;
-	timestamp_t t0, t1, t2, t3;
-	char *buf;
-	const int buf_size = 1000;
-	const int len = 400;
-	const int iteration = 1000;
-
-	TEST_ASSERT(shared_mem_acquire(buf_size, &buf) == EC_SUCCESS);
-
-	t0 = get_time();
-	for (i = 0; i < iteration; ++i)
-		dumb_memset(buf, 1, len);
-	t1 = get_time();
-	TEST_ASSERT_MEMSET(buf, (char)1, len);
-	ccprintf(" (speed gain: %" PRId64 " ->", t1.val-t0.val);
-
-	t2 = get_time();
-	for (i = 0; i < iteration; ++i)
-		memset(buf, 1, len);
-	t3 = get_time();
-	TEST_ASSERT_MEMSET(buf, (char)1, len);
-	ccprintf(" %" PRId64 " us) ", t3.val-t2.val);
-
-	if (!IS_ENABLED(EMU_BUILD))
-		TEST_ASSERT((t1.val - t0.val) > (t3.val - t2.val));
-
-	memset(buf, 128, len);
-	TEST_ASSERT_MEMSET(buf, (char)128, len);
-
-	memset(buf, -2, len);
-	TEST_ASSERT_MEMSET(buf, (char)-2, len);
-
-	memset(buf + 1, 1, len - 2);
-	TEST_ASSERT_MEMSET(buf + 1, (char)1, len - 2);
-
-	shared_mem_release(buf);
-	return EC_SUCCESS;
-}
-
-static int test_memchr(void)
-{
-	char *buf = "1234";
-
-	TEST_ASSERT(memchr("123567890", '4', 8) == NULL);
-	TEST_ASSERT(memchr("123", '3', 2) == NULL);
-	TEST_ASSERT(memchr(buf, '3', 4) == buf + 2);
-	TEST_ASSERT(memchr(buf, '4', 4) == buf + 3);
-	return EC_SUCCESS;
-}
-
 static int test_uint64divmod_0(void)
 {
 	uint64_t n = 8567106442584750ULL;
 	int d = 54870071;
 	int r = uint64divmod(&n, d);
 
-	TEST_CHECK(r == 5991285 && n == 156134415ULL);
+	TEST_ASSERT(r == 5991285 && n == 156134415ULL);
+	return EC_SUCCESS;
 }
 
 static int test_uint64divmod_1(void)
@@ -187,7 +30,8 @@ static int test_uint64divmod_1(void)
 	int d = 2;
 	int r = uint64divmod(&n, d);
 
-	TEST_CHECK(r == 0 && n == 4283553221292375ULL);
+	TEST_ASSERT(r == 0 && n == 4283553221292375ULL);
+	return EC_SUCCESS;
 }
 
 static int test_uint64divmod_2(void)
@@ -196,7 +40,8 @@ static int test_uint64divmod_2(void)
 	int d = 0;
 	int r = uint64divmod(&n, d);
 
-	TEST_CHECK(r == 0 && n == 0ULL);
+	TEST_ASSERT(r == 0 && n == 0ULL);
+	return EC_SUCCESS;
 }
 
 static int test_get_next_bit(void)
@@ -361,25 +206,24 @@ static int test_mula32(void)
 	}
 	t1 = get_time();
 
-	ccprintf("After %d iterations, r=%08x%08x, r2=%08x%08x (time: %d)\n",
-		i, (uint32_t)(r >> 32), (uint32_t)r,
-		(uint32_t)(r2 >> 32), (uint32_t)r2, t1.le.lo-t0.le.lo);
-	TEST_ASSERT(r  == 0x9df59b9fb0ab9d96L);
+	ccprintf("After %d iterations, r=%08x%08x, r2=%08x%08x (time: %d)\n", i,
+		 (uint32_t)(r >> 32), (uint32_t)r, (uint32_t)(r2 >> 32),
+		 (uint32_t)r2, t1.le.lo - t0.le.lo);
+	TEST_ASSERT(r == 0x9df59b9fb0ab9d96L);
 	TEST_ASSERT(r2 == 0x9df59b9fb0beabd6L);
 
 	/* well okay then */
 	return EC_SUCCESS;
 }
 
-#define SWAP_TEST_HARNESS(t, x, y) \
-	do { \
-		t a = x, b = y; \
-		swap(a, b); \
+#define SWAP_TEST_HARNESS(t, x, y)   \
+	do {                         \
+		t a = x, b = y;      \
+		swap(a, b);          \
 		TEST_ASSERT(a == y); \
 		TEST_ASSERT(b == x); \
 	} while (0)
 
-
 static int test_swap(void)
 {
 	SWAP_TEST_HARNESS(uint8_t, UINT8_MAX, 0);
@@ -455,15 +299,15 @@ test_static int test_alignment_log2(void)
 
 test_static int test_binary_first_base3_from_bits(void)
 {
-	int n0[] = {0, 0, 0};  /* LSB first */
-	int n7[] = {1, 1, 1};
-	int n8[] = {2, 0, 0};
-	int n9[] = {2, 1, 0};
-	int n10[] = {0, 2, 0};
-	int n11[] = {1, 2, 0};
-	int n18[] = {0, 0, 2};
-	int n26[] = {2, 2, 2};
-	int n38[] = {1, 2, 0, 1};
+	int n0[] = { 0, 0, 0 }; /* LSB first */
+	int n7[] = { 1, 1, 1 };
+	int n8[] = { 2, 0, 0 };
+	int n9[] = { 2, 1, 0 };
+	int n10[] = { 0, 2, 0 };
+	int n11[] = { 1, 2, 0 };
+	int n18[] = { 0, 0, 2 };
+	int n26[] = { 2, 2, 2 };
+	int n38[] = { 1, 2, 0, 1 };
 
 	TEST_EQ(binary_first_base3_from_bits(n0, ARRAY_SIZE(n0)), 0, "%d");
 	TEST_EQ(binary_first_base3_from_bits(n7, ARRAY_SIZE(n7)), 7, "%d");
@@ -477,14 +321,68 @@ test_static int test_binary_first_base3_from_bits(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+test_static int test_parse_bool(void)
+{
+	int bool_val;
+	int rv;
+
+	/* False cases. */
+
+	bool_val = 1;
+	rv = parse_bool("off", &bool_val);
+	TEST_EQ(rv, 1, "%d");
+	TEST_EQ(bool_val, 0, "%d");
+
+	bool_val = 1;
+	rv = parse_bool("dis", &bool_val);
+	TEST_EQ(rv, 1, "%d");
+	TEST_EQ(bool_val, 0, "%d");
+
+	bool_val = 1;
+	rv = parse_bool("f", &bool_val);
+	TEST_EQ(rv, 1, "%d");
+	TEST_EQ(bool_val, 0, "%d");
+
+	bool_val = 1;
+	rv = parse_bool("n", &bool_val);
+	TEST_EQ(rv, 1, "%d");
+	TEST_EQ(bool_val, 0, "%d");
+
+	/* True cases. */
+
+	bool_val = 0;
+	rv = parse_bool("on", &bool_val);
+	TEST_EQ(rv, 1, "%d");
+	TEST_EQ(bool_val, 1, "%d");
+
+	bool_val = 0;
+	rv = parse_bool("ena", &bool_val);
+	TEST_EQ(rv, 1, "%d");
+	TEST_EQ(bool_val, 1, "%d");
+
+	bool_val = 0;
+	rv = parse_bool("t", &bool_val);
+	TEST_EQ(rv, 1, "%d");
+	TEST_EQ(bool_val, 1, "%d");
+
+	bool_val = 0;
+	rv = parse_bool("y", &bool_val);
+	TEST_EQ(rv, 1, "%d");
+	TEST_EQ(bool_val, 1, "%d");
+
+	/* Error case. */
+	bool_val = -1;
+	rv = parse_bool("a", &bool_val);
+	TEST_EQ(rv, 0, "%d");
+	TEST_EQ(bool_val, -1, "%d");
+
+	return EC_SUCCESS;
+}
+
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
-	RUN_TEST(test_memmove);
-	RUN_TEST(test_memcpy);
-	RUN_TEST(test_memset);
-	RUN_TEST(test_memchr);
 	RUN_TEST(test_uint64divmod_0);
 	RUN_TEST(test_uint64divmod_1);
 	RUN_TEST(test_uint64divmod_2);
@@ -499,6 +397,7 @@ void run_test(int argc, char **argv)
 	RUN_TEST(test_safe_memcmp);
 	RUN_TEST(test_alignment_log2);
 	RUN_TEST(test_binary_first_base3_from_bits);
+	RUN_TEST(test_parse_bool);
 
 	test_print_result();
 }
diff --git a/test/utils.tasklist b/test/utils.tasklist
index da0ab6211a..100cb6b5bd 100644
--- a/test/utils.tasklist
+++ b/test/utils.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/utils_str.c b/test/utils_str.c
index f184abffa6..36ad63989e 100644
--- a/test/utils_str.c
+++ b/test/utils_str.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -13,34 +13,6 @@
 #include "timer.h"
 #include "util.h"
 
-static int test_isalpha(void)
-{
-	TEST_CHECK(isalpha('a') && isalpha('z') && isalpha('A') &&
-		   isalpha('Z') && !isalpha('0') && !isalpha('~') &&
-		   !isalpha(' ') && !isalpha('\0') && !isalpha('\n'));
-}
-
-static int test_isprint(void)
-{
-	TEST_CHECK(isprint('a') && isprint('z') && isprint('A') &&
-		   isprint('Z') && isprint('0') && isprint('~') &&
-		   isprint(' ') && !isprint('\0') && !isprint('\n'));
-}
-
-static int test_strstr(void)
-{
-	const char s1[] = "abcde";
-
-	TEST_ASSERT(strstr(s1, "ab") == s1);
-	TEST_ASSERT(strstr(s1, "") == NULL);
-	TEST_ASSERT(strstr("", "ab") == NULL);
-	TEST_ASSERT(strstr("", "x") == NULL);
-	TEST_ASSERT(strstr(s1, "de") == &s1[3]);
-	TEST_ASSERT(strstr(s1, "def") == NULL);
-
-	return EC_SUCCESS;
-}
-
 static int test_strtoi(void)
 {
 	char *e;
@@ -99,64 +71,6 @@ static int test_strtoi(void)
 	return EC_SUCCESS;
 }
 
-static int test_strtoull(void)
-{
-	char *e;
-
-	TEST_ASSERT(strtoull("10", &e, 0) == 10);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoull("010", &e, 0) == 8);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoull("+010", &e, 0) == 8);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoull("-010", &e, 0) == 0);
-	TEST_ASSERT(e && (*e == '-'));
-	TEST_ASSERT(strtoull("0x1f z", &e, 0) == 31);
-	TEST_ASSERT(e && (*e == ' '));
-	TEST_ASSERT(strtoull("0X1f z", &e, 0) == 31);
-	TEST_ASSERT(e && (*e == ' '));
-	TEST_ASSERT(strtoull("10a", &e, 16) == 266);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoull("0x02C", &e, 16) == 44);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoull("+0x02C", &e, 16) == 44);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoull("-0x02C", &e, 16) == 0);
-	TEST_ASSERT(e && (*e == '-'));
-	TEST_ASSERT(strtoull("0x02C", &e, 0) == 44);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoull("+0x02C", &e, 0) == 44);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoull("-0x02C", &e, 0) == 0);
-	TEST_ASSERT(e && (*e == '-'));
-	TEST_ASSERT(strtoull("0X02C", &e, 16) == 44);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoull("+0X02C", &e, 16) == 44);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoull("-0X02C", &e, 16) == 0);
-	TEST_ASSERT(e && (*e == '-'));
-	TEST_ASSERT(strtoull("0X02C", &e, 0) == 44);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoull("+0X02C", &e, 0) == 44);
-	TEST_ASSERT(e && (*e == '\0'));
-	TEST_ASSERT(strtoull("-0X02C", &e, 0) == 0);
-	TEST_ASSERT(e && (*e == '-'));
-	TEST_ASSERT(strtoull("   -12", &e, 0) == 0);
-	TEST_ASSERT(e && (*e == '-'));
-	TEST_ASSERT(strtoull("!", &e, 0) == 0);
-	TEST_ASSERT(e && (*e == '!'));
-	TEST_ASSERT(strtoull("+!", &e, 0) == 0);
-	TEST_ASSERT(e && (*e == '!'));
-	TEST_ASSERT(strtoull("+0!", &e, 0) == 0);
-	TEST_ASSERT(e && (*e == '!'));
-	TEST_ASSERT(strtoull("+0x!", &e, 0) == 0);
-	TEST_ASSERT(e && (*e == '!'));
-	TEST_ASSERT(strtoull("+0X!", &e, 0) == 0);
-	TEST_ASSERT(e && (*e == '!'));
-
-	return EC_SUCCESS;
-}
-
 static int test_parse_bool(void)
 {
 	int v;
@@ -190,123 +104,13 @@ static int test_strzcpy(void)
 	return EC_SUCCESS;
 }
 
-static int test_strncpy(void)
-{
-	char dest[10];
-
-	strncpy(dest, "test", 10);
-	TEST_ASSERT_ARRAY_EQ("test", dest, 5);
-	strncpy(dest, "12345", 6);
-	TEST_ASSERT_ARRAY_EQ("12345", dest, 6);
-	strncpy(dest, "testtesttest", 10);
-	TEST_ASSERT_ARRAY_EQ("testtestte", dest, 10);
-
-	return EC_SUCCESS;
-}
-
-static int test_strncmp(void)
-{
-	TEST_ASSERT(strncmp("123", "123", 8) == 0);
-	TEST_ASSERT(strncmp("789", "456", 8) > 0);
-	TEST_ASSERT(strncmp("abc", "abd", 4) < 0);
-	TEST_ASSERT(strncmp("abc", "abd", 2) == 0);
-	return EC_SUCCESS;
-}
-
-static int test_strlen(void)
-{
-	TEST_CHECK(strlen("this is a string") == 16);
-}
-
-static int test_strnlen(void)
-{
-	TEST_ASSERT(strnlen("this is a string", 17) == 16);
-	TEST_ASSERT(strnlen("this is a string", 16) == 16);
-	TEST_ASSERT(strnlen("this is a string", 5) == 5);
-
-	return EC_SUCCESS;
-}
-
-static int test_strcasecmp(void)
-{
-	TEST_CHECK((strcasecmp("test string", "TEST strIng") == 0) &&
-		   (strcasecmp("test123!@#", "TesT123!@#") == 0) &&
-		   (strcasecmp("lower", "UPPER") != 0));
-}
-
-static int test_strncasecmp(void)
-{
-	TEST_CHECK((strncasecmp("test string", "TEST str", 4) == 0) &&
-		   (strncasecmp("test string", "TEST str", 8) == 0) &&
-		   (strncasecmp("test123!@#", "TesT321!@#", 5) != 0) &&
-		   (strncasecmp("test123!@#", "TesT321!@#", 4) == 0) &&
-		   (strncasecmp("1test123!@#", "1TesT321!@#", 5) == 0) &&
-		   (strncasecmp("1test123", "teststr", 0) == 0));
-}
-
-static int test_atoi(void)
-{
-	TEST_CHECK((atoi("  901") == 901) &&
-		   (atoi("-12c") == -12) &&
-		   (atoi("   0  ") == 0) &&
-		   (atoi("\t111") == 111));
-}
-
-static int test_snprintf(void)
-{
-	char buffer[32];
-
-	TEST_CHECK(snprintf(buffer, sizeof(buffer), "%u", 1234) == 4);
-	TEST_CHECK(strncmp(buffer, "1234", sizeof(buffer)));
-}
-
-static int test_strcspn(void)
-{
-	const char str1[] = "abc";
-	const char str2[] = "This is a string\nwith newlines!";
-
-	TEST_EQ(strcspn(str1, "a"), (size_t)0, "%zu");
-	TEST_EQ(strcspn(str1, "b"), (size_t)1, "%zu");
-	TEST_EQ(strcspn(str1, "c"), (size_t)2, "%zu");
-	TEST_EQ(strcspn(str1, "ccc"), (size_t)2, "%zu");
-	TEST_EQ(strcspn(str1, "cba"), (size_t)0, "%zu");
-	TEST_EQ(strcspn(str1, "cb"), (size_t)1, "%zu");
-	TEST_EQ(strcspn(str1, "bc"), (size_t)1, "%zu");
-	TEST_EQ(strcspn(str1, "cbc"), (size_t)1, "%zu");
-	TEST_EQ(strcspn(str1, "z"), strlen(str1), "%zu");
-	TEST_EQ(strcspn(str1, "xyz"), strlen(str1), "%zu");
-	TEST_EQ(strcspn(str1, ""), strlen(str1), "%zu");
-
-	TEST_EQ(strcspn(str2, " "), (size_t)4, "%zu");
-	TEST_EQ(strcspn(str2, "\n"), (size_t)16, "%zu");
-	TEST_EQ(strcspn(str2, "\n "), (size_t)4, "%zu");
-	TEST_EQ(strcspn(str2, "!"), strlen(str2) - 1, "%zu");
-	TEST_EQ(strcspn(str2, "z"), strlen(str2), "%zu");
-	TEST_EQ(strcspn(str2, "z!"), strlen(str2) - 1, "%zu");
-
-	return EC_SUCCESS;
-}
-
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
-	RUN_TEST(test_isalpha);
-	RUN_TEST(test_isprint);
-	RUN_TEST(test_strstr);
 	RUN_TEST(test_strtoi);
-	RUN_TEST(test_strtoull);
 	RUN_TEST(test_parse_bool);
 	RUN_TEST(test_strzcpy);
-	RUN_TEST(test_strncpy);
-	RUN_TEST(test_strncmp);
-	RUN_TEST(test_strlen);
-	RUN_TEST(test_strnlen);
-	RUN_TEST(test_strcasecmp);
-	RUN_TEST(test_strncasecmp);
-	RUN_TEST(test_atoi);
-	RUN_TEST(test_snprintf);
-	RUN_TEST(test_strcspn);
 
 	test_print_result();
 }
diff --git a/test/utils_str.tasklist b/test/utils_str.tasklist
index 7150f17cbd..6373a70ab1 100644
--- a/test/utils_str.tasklist
+++ b/test/utils_str.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/vboot.c b/test/vboot.c
index 7dab08ac05..f75208de90 100644
--- a/test/vboot.c
+++ b/test/vboot.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -131,7 +131,7 @@ static int test_vboot(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	test_reset();
 
diff --git a/test/vboot.tasklist b/test/vboot.tasklist
index 7150f17cbd..6373a70ab1 100644
--- a/test/vboot.tasklist
+++ b/test/vboot.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/version.c b/test/version.c
index ad7571d5f6..9731863f29 100644
--- a/test/version.c
+++ b/test/version.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -139,7 +139,7 @@ static int test_image_unknown(void)
 	return EC_SUCCESS;
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	RUN_TEST(test_version);
 	RUN_TEST(test_fwid);
diff --git a/test/version.tasklist b/test/version.tasklist
index e54ea001bd..cd866d90e1 100644
--- a/test/version.tasklist
+++ b/test/version.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/test/vpd_api.c b/test/vpd_api.c
index 65e86adb96..51a2e76cd6 100644
--- a/test/vpd_api.c
+++ b/test/vpd_api.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -33,11 +33,11 @@
 #endif
 
 #ifndef CC_RA
-#define CC_RA(port, cc, sel)  (cc < pd_src_rd_threshold[ct_cc_rp_value])
+#define CC_RA(port, cc, sel) (cc < pd_src_rd_threshold[ct_cc_rp_value])
 #endif
 #define CC_RD(cc) ((cc >= PD_SRC_RD_THRESHOLD) && (cc < PD_SRC_VNC))
 #ifndef CC_NC
-#define CC_NC(port, cc, sel)  (cc >= PD_SRC_VNC)
+#define CC_NC(port, cc, sel) (cc >= PD_SRC_VNC)
 #endif
 
 /*
@@ -54,7 +54,7 @@
 #define PD_SNK_VA PD_SNK_VA_MV
 #endif
 
-#define CC_RP(cc)  (cc >= PD_SNK_VA)
+#define CC_RP(cc) (cc >= PD_SNK_VA)
 
 /* Mock Board State */
 static enum vpd_pwr mock_vconn_pwr_sel_odl;
@@ -266,7 +266,7 @@ static int vpd_cc_voltage_to_status(int cc_volt, int cc_pull)
 			return TYPEC_CC_VOLT_RA;
 		else
 			return TYPEC_CC_VOLT_RD;
-	/* If we have a pull-down, then we are sink, check for Rp. */
+		/* If we have a pull-down, then we are sink, check for Rp. */
 	} else if (cc_pull == TYPEC_CC_RD || cc_pull == TYPEC_CC_RA_RD) {
 		if (cc_volt >= TYPE_C_SRC_3000_THRESHOLD)
 			return TYPEC_CC_VOLT_RP_3_0;
diff --git a/test/vpd_api.h b/test/vpd_api.h
index f848138172..62dab34377 100644
--- a/test/vpd_api.h
+++ b/test/vpd_api.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,39 +16,22 @@
  * voltage (set by selecting the proper Rd resistor). Any voltage below
  * TYPE_C_SRC_DEFAULT_THRESHOLD will not be identified as a type C charger.
  */
-#define TYPE_C_SRC_DEFAULT_THRESHOLD    200  /* mV */
-#define TYPE_C_SRC_1500_THRESHOLD       660  /* mV */
-#define TYPE_C_SRC_3000_THRESHOLD       1230 /* mV */
+#define TYPE_C_SRC_DEFAULT_THRESHOLD 200 /* mV */
+#define TYPE_C_SRC_1500_THRESHOLD 660 /* mV */
+#define TYPE_C_SRC_3000_THRESHOLD 1230 /* mV */
 
+enum vpd_pin { PIN_ADC, PIN_CMP, PIN_GPO };
 
-enum vpd_pin {
-	PIN_ADC,
-	PIN_CMP,
-	PIN_GPO
-};
-
-enum vpd_gpo {
-	GPO_HZ,
-	GPO_HIGH,
-	GPO_LOW
-};
+enum vpd_gpo { GPO_HZ, GPO_HIGH, GPO_LOW };
 
 enum vpd_pwr {
 	PWR_VCONN,
 	PWR_VBUS,
 };
 
-enum vpd_cc {
-	CT_OPEN,
-	CT_CC1,
-	CT_CC2
-};
+enum vpd_cc { CT_OPEN, CT_CC1, CT_CC2 };
 
-enum vpd_billboard {
-	BB_NONE,
-	BB_SRC,
-	BB_SNK
-};
+enum vpd_billboard { BB_NONE, BB_SRC, BB_SNK };
 
 struct mock_pin {
 	enum vpd_pin cfg;
diff --git a/test/x25519.tasklist b/test/x25519.tasklist
index 80072bb620..329f9a3d28 100644
--- a/test/x25519.tasklist
+++ b/test/x25519.tasklist
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/third_party/boringssl/LICENSE b/third_party/boringssl/LICENSE
index 49c41fa7af..e9667cb9c2 100644
--- a/third_party/boringssl/LICENSE
+++ b/third_party/boringssl/LICENSE
@@ -142,7 +142,7 @@ record keeping.)
 
 ISC license used for completely new code in BoringSSL:
 
-/* Copyright (c) 2015, Google Inc.
+/* Copyright 2015 Google LLC
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -200,7 +200,7 @@ notice, this list of conditions and the following disclaimer.
 copyright notice, this list of conditions and the following disclaimer
 in the documentation and/or other materials provided with the
 distribution.
-   * Neither the name of Google Inc. nor the names of its
+   * Neither the name of Google LLC nor the names of its
 contributors may be used to endorse or promote products derived from
 this software without specific prior written permission.
 
@@ -222,7 +222,7 @@ trybots etc. The scripts which manage this, and the script for generating build
 metadata, are under the Chromium license. Distributing code linked against
 BoringSSL does not trigger this license.
 
-Copyright 2015 The Chromium Authors. All rights reserved.
+Copyright 2015 The Chromium Authors
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions are
@@ -234,7 +234,7 @@ notice, this list of conditions and the following disclaimer.
 copyright notice, this list of conditions and the following disclaimer
 in the documentation and/or other materials provided with the
 distribution.
-   * Neither the name of Google Inc. nor the names of its
+   * Neither the name of Google LLC nor the names of its
 contributors may be used to endorse or promote products derived from
 this software without specific prior written permission.
 
diff --git a/third_party/boringssl/common/aes-gcm.c b/third_party/boringssl/common/aes-gcm.c
index edb98b88b3..8fe5f75307 100644
--- a/third_party/boringssl/common/aes-gcm.c
+++ b/third_party/boringssl/common/aes-gcm.c
@@ -48,7 +48,6 @@
 
 #include "aes-gcm.h"
 #include "common.h"
-#include "endian.h"
 #include "util.h"
 
 #define STRICT_ALIGNMENT 1
diff --git a/third_party/boringssl/common/curve25519-generic.c b/third_party/boringssl/common/curve25519-generic.c
index e0d09b2acb..16e0668071 100644
--- a/third_party/boringssl/common/curve25519-generic.c
+++ b/third_party/boringssl/common/curve25519-generic.c
@@ -1,4 +1,4 @@
-/* Copyright 2015, Google Inc.
+/* Copyright 2015 Google LLC
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
diff --git a/third_party/boringssl/common/curve25519.c b/third_party/boringssl/common/curve25519.c
index 2a7fad6509..1c902e424c 100644
--- a/third_party/boringssl/common/curve25519.c
+++ b/third_party/boringssl/common/curve25519.c
@@ -1,4 +1,4 @@
-/* Copyright 2015, Google Inc.
+/* Copyright 2015 Google LLC
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -27,7 +27,7 @@
 
 #ifdef CONFIG_RNG
 void X25519_keypair(uint8_t out_public_value[32], uint8_t out_private_key[32]) {
-  rand_bytes(out_private_key, 32);
+  trng_rand_bytes(out_private_key, 32);
 
   /* All X25519 implementations should decode scalars correctly (see
    * https://tools.ietf.org/html/rfc7748#section-5). However, if an
diff --git a/third_party/boringssl/include/aes-gcm.h b/third_party/boringssl/include/aes-gcm.h
index e3ef457224..77ca52a3ed 100644
--- a/third_party/boringssl/include/aes-gcm.h
+++ b/third_party/boringssl/include/aes-gcm.h
@@ -50,7 +50,6 @@
 #define __CROS_EC_AES_GCM_H
 
 #include "common.h"
-#include "endian.h"
 #include "util.h"
 
 // block128_f is the type of a 128-bit, block cipher.
diff --git a/third_party/boringssl/include/curve25519.h b/third_party/boringssl/include/curve25519.h
index 8287c94466..05cebeed99 100644
--- a/third_party/boringssl/include/curve25519.h
+++ b/third_party/boringssl/include/curve25519.h
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/third_party/boringssl/test/x25519.c b/third_party/boringssl/test/x25519.c
index dac8795b63..cd773653e5 100644
--- a/third_party/boringssl/test/x25519.c
+++ b/third_party/boringssl/test/x25519.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2015, Google Inc.
+/* Copyright 2015 Google LLC
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -180,7 +180,7 @@ static void test_x25519_speed(void)
 	ccprintf("X25519 duration %lld us\n", (long long)(t1.val - t0.val));
 }
 
-void run_test(int argc, char **argv)
+void run_test(int argc, const char **argv)
 {
 	watchdog_reload();
 	/* do not check speed, just as a benchmark */
diff --git a/third_party/rules.mk b/third_party/rules.mk
index 16fd1e52e3..eb4391b70c 100644
--- a/third_party/rules.mk
+++ b/third_party/rules.mk
@@ -1,6 +1,6 @@
 # -*- makefile -*-
 # vim: set filetype=make :
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -13,7 +13,7 @@ ifeq ($(CONFIG_LIBCRYPTOC),y)
 
 # The cryptoc path can be overridden on invocation, as in the following example:
 # $ make CRYPTOC_DIR=~/src/cryptoc BOARD=bloonchipper
-CRYPTOC_DIR ?= $(realpath ../../third_party/cryptoc)
+CRYPTOC_DIR ?= ../../third_party/cryptoc
 
 # SUPPORT_UNALIGNED indicates to libcryptoc that provided data buffers
 # may be unaligned and please handle them safely.
@@ -22,9 +22,6 @@ cmd_libcryptoc = $(MAKE) -C $(CRYPTOC_DIR) \
 	SUPPORT_UNALIGNED=1
 cmd_libcryptoc_clean = $(cmd_libcryptoc) -q && echo clean
 
-ifneq ($(BOARD),host)
-CPPFLAGS += -I$(abspath ./builtin)
-endif
 CPPFLAGS += -I$(CRYPTOC_DIR)/include
 CRYPTOC_LDFLAGS := -L$(out)/cryptoc -lcryptoc
 
@@ -36,6 +33,10 @@ CRYPTOC_LDFLAGS := -L$(out)/cryptoc -lcryptoc
 ifneq ($(shell $(cmd_libcryptoc_clean)),clean)
 .PHONY: $(out)/cryptoc/libcryptoc.a
 endif
+# Rewrite the CFLAGS include paths to be absolute, since cryptoc is built
+# using a different working directory. This is only relevant because
+# cryptoc makes use of stdlibs, which EC provides from the builtin/ directory.
+$(out)/cryptoc/libcryptoc.a: CFLAGS := $(patsubst -I%,-I$(abspath %),$(CFLAGS))
 $(out)/cryptoc/libcryptoc.a:
 	+$(call quiet,libcryptoc,MAKE   )
 
diff --git a/third_party/sha2/sha256.c b/third_party/sha2/sha256.c
index 2d6eaa43f2..475092b1fd 100644
--- a/third_party/sha2/sha256.c
+++ b/third_party/sha2/sha256.c
@@ -35,6 +35,7 @@
  * SUCH DAMAGE.
  */
 
+#include "builtin/assert.h"
 #include "sha256.h"
 #include "util.h"
 
diff --git a/twister b/twister
new file mode 120000
index 0000000000..7b6dd74c5c
--- /dev/null
+++ b/twister
@@ -0,0 +1 @@
+util/twister_launcher.py
\ No newline at end of file
diff --git a/util/battery_temp b/util/battery_temp
index c69e3d4778..01f4002b99 100755
--- a/util/battery_temp
+++ b/util/battery_temp
@@ -1,5 +1,5 @@
 #!/bin/bash
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/util/bin2h.sh b/util/bin2h.sh
index 1507bc4004..276d89f0cf 100755
--- a/util/bin2h.sh
+++ b/util/bin2h.sh
@@ -1,6 +1,6 @@
 #!/bin/bash
 #
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/util/build.mk b/util/build.mk
index 2948bd9d91..8f047dd1d2 100644
--- a/util/build.mk
+++ b/util/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
+# Copyright 2014 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/util/build_with_clang.py b/util/build_with_clang.py
index a38ade2cb8..e73f765e1e 100755
--- a/util/build_with_clang.py
+++ b/util/build_with_clang.py
@@ -1,6 +1,6 @@
 #!/usr/bin/env python3
 
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -12,15 +12,14 @@ import multiprocessing
 import os
 import subprocess
 import sys
-
 from concurrent.futures import ThreadPoolExecutor
 
 # Add to this list as compilation errors are fixed for boards.
 BOARDS_THAT_COMPILE_SUCCESSFULLY_WITH_CLANG = [
-    'dartmonkey',
-    'bloonchipper',
-    'nucleo-f412zg',
-    'nucleo-h743zi',
+    "dartmonkey",
+    "bloonchipper",
+    "nucleo-f412zg",
+    "nucleo-h743zi",
 ]
 
 
@@ -29,35 +28,31 @@ def build(board_name: str) -> None:
     logging.debug('Building board: "%s"', board_name)
 
     cmd = [
-        'make',
-        'BOARD=' + board_name,
-        '-j',
+        "make",
+        "BOARD=" + board_name,
+        "-j",
     ]
 
-    logging.debug('Running command: "%s"', ' '.join(cmd))
-    subprocess.run(cmd, env=dict(os.environ, CC='clang'), check=True)
+    logging.debug('Running command: "%s"', " ".join(cmd))
+    subprocess.run(cmd, env=dict(os.environ, CC="clang"), check=True)
 
 
 def main() -> int:
     parser = argparse.ArgumentParser()
 
-    log_level_choices = ['DEBUG', 'INFO', 'WARNING', 'ERROR', 'CRITICAL']
+    log_level_choices = ["DEBUG", "INFO", "WARNING", "ERROR", "CRITICAL"]
     parser.add_argument(
-        '--log_level', '-l',
-        choices=log_level_choices,
-        default='DEBUG'
+        "--log_level", "-l", choices=log_level_choices, default="DEBUG"
     )
 
     parser.add_argument(
-        '--num_threads', '-j',
-        type=int,
-        default=multiprocessing.cpu_count()
+        "--num_threads", "-j", type=int, default=multiprocessing.cpu_count()
     )
 
     args = parser.parse_args()
     logging.basicConfig(level=args.log_level)
 
-    logging.debug('Building with %d threads', args.num_threads)
+    logging.debug("Building with %d threads", args.num_threads)
 
     failed_boards = []
     with ThreadPoolExecutor(max_workers=args.num_threads) as executor:
@@ -73,13 +68,15 @@ def main() -> int:
                 failed_boards.append(board)
 
     if len(failed_boards) > 0:
-        logging.error('The following boards failed to compile:\n%s',
-                      '\n'.join(failed_boards))
+        logging.error(
+            "The following boards failed to compile:\n%s",
+            "\n".join(failed_boards),
+        )
         return 1
 
-    logging.info('All boards compiled successfully!')
+    logging.info("All boards compiled successfully!")
     return 0
 
 
-if __name__ == '__main__':
+if __name__ == "__main__":
     sys.exit(main())
diff --git a/util/cbi-util.c b/util/cbi-util.c
index fe0c4c2bce..5bea9a04b9 100644
--- a/util/cbi-util.c
+++ b/util/cbi-util.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -20,10 +20,10 @@
 #include "cros_board_info.h"
 #include "crc8.h"
 
-#define ARGS_MASK_BOARD_VERSION		BIT(0)
-#define ARGS_MASK_FILENAME		BIT(1)
-#define ARGS_MASK_SIZE			BIT(2)
-#define ARGS_MASK_SKU_ID		BIT(3)
+#define ARGS_MASK_BOARD_VERSION BIT(0)
+#define ARGS_MASK_FILENAME BIT(1)
+#define ARGS_MASK_SIZE BIT(2)
+#define ARGS_MASK_SKU_ID BIT(3)
 
 /* TODO: Set it by macro */
 const char cmd_name[] = "cbi-util";
@@ -41,6 +41,7 @@ enum {
 	OPT_PCB_SUPPLIER,
 	OPT_SSFC,
 	OPT_REWORK_ID,
+	OPT_FACTORY_CALIBRATION_DATA,
 	OPT_SIZE,
 	OPT_ERASE_BYTE,
 	OPT_SHOW_ALL,
@@ -48,27 +49,26 @@ enum {
 };
 
 static const struct option opts_create[] = {
-	{"file", 1, 0, OPT_FILENAME},
-	{"board_version", 1, 0, OPT_BOARD_VERSION},
-	{"oem_id", 1, 0, OPT_OEM_ID},
-	{"sku_id", 1, 0, OPT_SKU_ID},
-	{"dram_part_num", 1, 0, OPT_DRAM_PART_NUM},
-	{"oem_name", 1, 0, OPT_OEM_NAME},
-	{"model_id", 1, 0, OPT_MODEL_ID},
-	{"fw_config", 1, 0, OPT_FW_CONFIG},
-	{"pcb_supplier", 1, 0, OPT_PCB_SUPPLIER},
-	{"ssfc", 1, 0, OPT_SSFC},
-	{"rework_id", 1, 0, OPT_REWORK_ID},
-	{"size", 1, 0, OPT_SIZE},
-	{"erase_byte", 1, 0, OPT_ERASE_BYTE},
-	{NULL, 0, 0, 0}
+	{ "file", 1, 0, OPT_FILENAME },
+	{ "board_version", 1, 0, OPT_BOARD_VERSION },
+	{ "oem_id", 1, 0, OPT_OEM_ID },
+	{ "sku_id", 1, 0, OPT_SKU_ID },
+	{ "dram_part_num", 1, 0, OPT_DRAM_PART_NUM },
+	{ "oem_name", 1, 0, OPT_OEM_NAME },
+	{ "model_id", 1, 0, OPT_MODEL_ID },
+	{ "fw_config", 1, 0, OPT_FW_CONFIG },
+	{ "pcb_supplier", 1, 0, OPT_PCB_SUPPLIER },
+	{ "ssfc", 1, 0, OPT_SSFC },
+	{ "rework_id", 1, 0, OPT_REWORK_ID },
+	{ "factory_calibration_data", 1, 0, OPT_FACTORY_CALIBRATION_DATA },
+	{ "size", 1, 0, OPT_SIZE },
+	{ "erase_byte", 1, 0, OPT_ERASE_BYTE },
+	{ NULL, 0, 0, 0 }
 };
 
-static const struct option opts_show[] = {
-	{"file", 1, 0, OPT_FILENAME},
-	{"all", 0, 0, OPT_SHOW_ALL},
-	{NULL, 0, 0, 0}
-};
+static const struct option opts_show[] = { { "file", 1, 0, OPT_FILENAME },
+					   { "all", 0, 0, OPT_SHOW_ALL },
+					   { NULL, 0, 0, 0 } };
 
 static const char *field_name[] = {
 	/* Same order as enum cbi_data_tag */
@@ -82,6 +82,7 @@ static const char *field_name[] = {
 	"PCB_SUPPLIER",
 	"SSFC",
 	"REWORK_ID",
+	"FACTORY_CALIBRATION_DATA",
 };
 BUILD_ASSERT(ARRAY_SIZE(field_name) == CBI_TAG_COUNT);
 
@@ -105,6 +106,7 @@ const char help_create[] =
 	"  --pcb_supplier <value>     PCB supplier\n"
 	"  --ssfc <value>             Second Source Factory Cache bit-field\n"
 	"  --rework_id <lvalue>       REWORK_ID\n"
+	"  --factory_calibration_data <value>    Factory calibration data\n"
 	"\n"
 	"<value> must be a positive integer <= 0XFFFFFFFF, <lvalue> must be a\n"
 	"  positive integer <= 0xFFFFFFFFFFFFFFFF and field size can be\n"
@@ -147,8 +149,9 @@ static void print_help_show(void)
 static void print_help(void)
 {
 	printf("\nUsage: %s <create|show> [ARGS]\n"
-		"\n"
-		"Utility for CBI:Cros Board Info images.\n", cmd_name);
+	       "\n"
+	       "Utility for CBI:Cros Board Info images.\n",
+	       cmd_name);
 	print_help_create();
 	print_help_show();
 }
@@ -314,6 +317,7 @@ static int cmd_create(int argc, char **argv)
 		struct integer_field pcb_supplier;
 		struct integer_field ssfc;
 		struct long_integer_field rework;
+		struct integer_field factory_calibration_data;
 		const char *dram_part_num;
 		const char *oem_name;
 	} bi;
@@ -398,11 +402,16 @@ static int cmd_create(int argc, char **argv)
 			if (parse_uint64_field(optarg, &bi.rework))
 				return -1;
 			break;
+		case OPT_FACTORY_CALIBRATION_DATA:
+			if (parse_integer_field(optarg,
+						&bi.factory_calibration_data))
+				return -1;
+			break;
 		}
 	}
 
 	if (set_mask != (ARGS_MASK_BOARD_VERSION | ARGS_MASK_FILENAME |
-			ARGS_MASK_SIZE | ARGS_MASK_SKU_ID)) {
+			 ARGS_MASK_SIZE | ARGS_MASK_SKU_ID)) {
 		fprintf(stderr, "Missing required arguments\n");
 		print_help_create();
 		return -1;
@@ -427,9 +436,12 @@ static int cmd_create(int argc, char **argv)
 	p = cbi_set_data(p, CBI_TAG_FW_CONFIG, &bi.fw_config.val,
 			 bi.fw_config.size);
 	p = cbi_set_data(p, CBI_TAG_PCB_SUPPLIER, &bi.pcb_supplier.val,
-			bi.pcb_supplier.size);
+			 bi.pcb_supplier.size);
 	p = cbi_set_data(p, CBI_TAG_SSFC, &bi.ssfc.val, bi.ssfc.size);
 	p = cbi_set_data(p, CBI_TAG_REWORK_ID, &bi.rework.val, bi.rework.size);
+	p = cbi_set_data(p, CBI_TAG_FACTORY_CALIBRATION_DATA,
+			 &bi.factory_calibration_data.val,
+			 bi.factory_calibration_data.size);
 	p = cbi_set_string(p, CBI_TAG_DRAM_PART_NUM, bi.dram_part_num);
 	p = cbi_set_string(p, CBI_TAG_OEM_NAME, bi.oem_name);
 
@@ -460,7 +472,7 @@ static void print_string(const uint8_t *buf, enum cbi_data_tag tag)
 	name = d->tag < CBI_TAG_COUNT ? field_name[d->tag] : "???";
 
 	printf("    %s: %.*s (%u, %u)\n", name, d->size, (const char *)d->value,
-		d->tag, d->size);
+	       d->tag, d->size);
 }
 
 static void print_integer(const uint8_t *buf, enum cbi_data_tag tag)
@@ -489,12 +501,12 @@ static void print_integer(const uint8_t *buf, enum cbi_data_tag tag)
 		v = *(uint64_t *)d->value;
 		break;
 	default:
-		printf("    %s: Integer of size %d not supported\n",
-		       name, d->size);
+		printf("    %s: Integer of size %d not supported\n", name,
+		       d->size);
 		return;
 	}
 	printf("    %s: %llu (0x%llx, %u, %u)\n", name, (unsigned long long)v,
-		(unsigned long long)v, d->tag, d->size);
+	       (unsigned long long)v, d->tag, d->size);
 }
 
 static int cmd_show(int argc, char **argv)
@@ -564,6 +576,7 @@ static int cmd_show(int argc, char **argv)
 	print_integer(buf, CBI_TAG_PCB_SUPPLIER);
 	print_integer(buf, CBI_TAG_SSFC);
 	print_integer(buf, CBI_TAG_REWORK_ID);
+	print_integer(buf, CBI_TAG_FACTORY_CALIBRATION_DATA);
 	print_string(buf, CBI_TAG_DRAM_PART_NUM);
 	print_string(buf, CBI_TAG_OEM_NAME);
 
diff --git a/util/chargen b/util/chargen
index 9ba14d3d6a..fd9e73cbda 100644
--- a/util/chargen
+++ b/util/chargen
@@ -1,10 +1,11 @@
 #!/usr/bin/env python3
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 import sys
 
+
 def chargen(modulo, max_chars):
     """Generate a stream of characters on the console.
 
@@ -18,7 +19,7 @@ def chargen(modulo, max_chars):
                  zero, if zero - print indefinitely
     """
 
-    base = '0'
+    base = "0"
     c = base
     counter = 0
     while True:
@@ -26,25 +27,25 @@ def chargen(modulo, max_chars):
         counter = counter + 1
 
         if (max_chars != 0) and (counter == max_chars):
-            sys.stdout.write('\n')
+            sys.stdout.write("\n")
             return
 
         if modulo and ((counter % modulo) == 0):
             c = base
             continue
 
-        if c == 'z':
+        if c == "z":
             c = base
-        elif c == 'Z':
-            c = 'a'
-        elif c == '9':
-            c = 'A'
+        elif c == "Z":
+            c = "a"
+        elif c == "9":
+            c = "A"
         else:
-            c = '%c' % (ord(c) + 1)
+            c = "%c" % (ord(c) + 1)
 
 
 def main(args):
-    '''Process command line arguments and invoke chargen if args are valid'''
+    """Process command line arguments and invoke chargen if args are valid"""
 
     modulo = 0
     max_chars = 0
@@ -55,8 +56,7 @@ def main(args):
             if len(args) > 1:
                 max_chars = int(args[1])
     except ValueError:
-        sys.stderr.write('usage %s:'
-                         "['seq_length' ['max_chars']]\n")
+        sys.stderr.write("usage %s:" "['seq_length' ['max_chars']]\n")
         sys.exit(1)
 
     try:
@@ -64,6 +64,7 @@ def main(args):
     except KeyboardInterrupt:
         print()
 
-if __name__ == '__main__':
+
+if __name__ == "__main__":
     main(sys.argv[1:])
     sys.exit(0)
diff --git a/util/check_clang_format.py b/util/check_clang_format.py
new file mode 100755
index 0000000000..3be63774f7
--- /dev/null
+++ b/util/check_clang_format.py
@@ -0,0 +1,70 @@
+#!/usr/bin/env python3
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Validate all C source is formatted with clang-format.
+
+This isn't very useful to users to call directly, but it is run it the
+CQ.  Most users will likely find out they forgot to clang-format by
+the pre-upload checks.
+"""
+
+import logging
+import pathlib
+import subprocess
+import sys
+
+from chromite.lib import commandline
+
+
+def main(argv=None):
+    """Find all C files and runs clang-format on them."""
+    parser = commandline.ArgumentParser()
+    parser.parse_args(argv)
+
+    logging.info("Validating all code is formatted with clang-format.")
+    ec_dir = pathlib.Path(__file__).resolve().parent.parent
+    all_files = [
+        ec_dir / path
+        for path in subprocess.run(
+            ["git", "ls-files", "-z"],
+            check=True,
+            cwd=ec_dir,
+            stdout=subprocess.PIPE,
+            encoding="utf-8",
+        ).stdout.split("\0")
+        if path
+    ]
+
+    clang_format_files = []
+    for path in all_files:
+        if not path.is_file() or path.is_symlink():
+            continue
+        if "third_party" in path.parts:
+            continue
+        if path.name.endswith(".c") or path.name.endswith(".h"):
+            clang_format_files.append(path)
+
+    result = subprocess.run(
+        ["clang-format", "--dry-run", *clang_format_files],
+        check=False,
+        cwd=ec_dir,
+        stderr=subprocess.PIPE,
+        encoding="utf-8",
+    )
+    if result.stderr:
+        logging.error("All C source must be formatted with clang-format!")
+        for line in result.stderr.splitlines():
+            logging.error("%s", line)
+        return 1
+    if result.returncode != 0:
+        logging.error("clang-format failed with no output!")
+        return result.returncode
+
+    logging.info("No clang-format issues found!")
+    return 0
+
+
+if __name__ == "__main__":
+    sys.exit(main(sys.argv[1:]))
diff --git a/util/comm-dev.c b/util/comm-dev.c
index e73538b323..f6467492f9 100644
--- a/util/comm-dev.c
+++ b/util/comm-dev.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,7 +27,7 @@ static int fd = -1;
 #define ARRAY_SIZE(t) (sizeof(t) / sizeof(t[0]))
 #endif
 
-static const char * const meanings[] = {
+static const char *const meanings[] = {
 	"SUCCESS",
 	"INVALID_COMMAND",
 	"ERROR",
@@ -60,9 +60,8 @@ static const char *strresult(int i)
 
 /* Old ioctl format, used by Chrome OS 3.18 and older */
 
-static int ec_command_dev(int command, int version,
-			  const void *outdata, int outsize,
-			  void *indata, int insize)
+static int ec_command_dev(int command, int version, const void *outdata,
+			  int outsize, void *indata, int insize)
 {
 	struct cros_ec_command s_cmd;
 	int r;
@@ -83,12 +82,15 @@ static int ec_command_dev(int command, int version,
 		if (errno == EAGAIN && s_cmd.result == EC_RES_IN_PROGRESS) {
 			s_cmd.command = EC_CMD_RESEND_RESPONSE;
 			r = ioctl(fd, CROS_EC_DEV_IOCXCMD, &s_cmd);
-			fprintf(stderr,
-				"ioctl %d, errno %d (%s), EC result %d (%s)\n",
-				r, errno, strerror(errno), s_cmd.result,
-				strresult(s_cmd.result));
+			if (r < 0) {
+				fprintf(stderr,
+					"ioctl %d, errno %d (%s), EC result %d (%s)\n",
+					r, errno, strerror(errno), s_cmd.result,
+					strresult(s_cmd.result));
+			}
 		}
-	} else if (s_cmd.result != EC_RES_SUCCESS) {
+	}
+	if (r >= 0 && s_cmd.result != EC_RES_SUCCESS) {
 		fprintf(stderr, "EC result %d (%s)\n", s_cmd.result,
 			strresult(s_cmd.result));
 		return -EECRESULT - s_cmd.result;
@@ -117,16 +119,14 @@ static int ec_readmem_dev(int offset, int bytes, void *dest)
 
 	r_mem.offset = offset;
 	r_mem.size = bytes;
-	return ec_command_dev(EC_CMD_READ_MEMMAP, 0,
-			      &r_mem, sizeof(r_mem),
+	return ec_command_dev(EC_CMD_READ_MEMMAP, 0, &r_mem, sizeof(r_mem),
 			      dest, bytes);
 }
 
 /* New ioctl format, used by Chrome OS 4.4 and later as well as upstream 4.0+ */
 
-static int ec_command_dev_v2(int command, int version,
-			     const void *outdata, int outsize,
-			     void *indata, int insize)
+static int ec_command_dev_v2(int command, int version, const void *outdata,
+			     int outsize, void *indata, int insize)
 {
 	struct cros_ec_command_v2 *s_cmd;
 	int r;
@@ -153,18 +153,22 @@ static int ec_command_dev_v2(int command, int version,
 			strresult(s_cmd->result));
 		if (errno == EAGAIN && s_cmd->result == EC_RES_IN_PROGRESS) {
 			s_cmd->command = EC_CMD_RESEND_RESPONSE;
-			r = ioctl(fd, CROS_EC_DEV_IOCXCMD_V2, &s_cmd);
-			fprintf(stderr,
-				"ioctl %d, errno %d (%s), EC result %d (%s)\n",
-				r, errno, strerror(errno), s_cmd->result,
-				strresult(s_cmd->result));
+			r = ioctl(fd, CROS_EC_DEV_IOCXCMD_V2, s_cmd);
+			if (r < 0) {
+				fprintf(stderr,
+					"ioctl %d, errno %d (%s), EC result %d (%s)\n",
+					r, errno, strerror(errno),
+					s_cmd->result,
+					strresult(s_cmd->result));
+			}
 		}
-	} else {
+	}
+	if (r >= 0) {
 		memcpy(indata, s_cmd->data, MIN(r, insize));
 		if (s_cmd->result != EC_RES_SUCCESS) {
 			fprintf(stderr, "EC result %d (%s)\n", s_cmd->result,
 				strresult(s_cmd->result));
-			r =  -EECRESULT - s_cmd->result;
+			r = -EECRESULT - s_cmd->result;
 		}
 	}
 	free(s_cmd);
@@ -193,8 +197,7 @@ static int ec_readmem_dev_v2(int offset, int bytes, void *dest)
 
 	r_mem.offset = offset;
 	r_mem.size = bytes;
-	return ec_command_dev_v2(EC_CMD_READ_MEMMAP, 0,
-				 &r_mem, sizeof(r_mem),
+	return ec_command_dev_v2(EC_CMD_READ_MEMMAP, 0, &r_mem, sizeof(r_mem),
 				 dest, bytes);
 }
 
@@ -204,11 +207,9 @@ static int ec_readmem_dev_v2(int offset, int bytes, void *dest)
  */
 static int ec_dev_is_v2(void)
 {
-	struct ec_params_hello h_req = {
-		.in_data = 0xa0b0c0d0
-	};
+	struct ec_params_hello h_req = { .in_data = 0xa0b0c0d0 };
 	struct ec_response_hello h_resp;
-	struct cros_ec_command s_cmd = { };
+	struct cros_ec_command s_cmd = {};
 	int r;
 
 	s_cmd.command = EC_CMD_HELLO;
@@ -256,7 +257,7 @@ int comm_init_dev(const char *device_name)
 	if (fd < 0)
 		return 1;
 
-	r = read(fd, version, sizeof(version)-1);
+	r = read(fd, version, sizeof(version) - 1);
 	if (r <= 0) {
 		close(fd);
 		return 2;
diff --git a/util/comm-host.c b/util/comm-host.c
index 45d6f85a02..914e6d27e8 100644
--- a/util/comm-host.c
+++ b/util/comm-host.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,10 +15,8 @@
 #include "ec_commands.h"
 #include "misc_util.h"
 
-
-int (*ec_command_proto)(int command, int version,
-			const void *outdata, int outsize,
-			void *indata, int insize);
+int (*ec_command_proto)(int command, int version, const void *outdata,
+			int outsize, void *indata, int insize);
 
 int (*ec_readmem)(int offset, int bytes, void *dest);
 
@@ -45,8 +43,8 @@ static int fake_readmem(int offset, int bytes, void *dest)
 
 	if (bytes) {
 		p.size = bytes;
-		c = ec_command(EC_CMD_READ_MEMMAP, 0, &p, sizeof(p),
-			       dest, p.size);
+		c = ec_command(EC_CMD_READ_MEMMAP, 0, &p, sizeof(p), dest,
+			       p.size);
 		if (c < 0)
 			return c;
 		return p.size;
@@ -73,14 +71,12 @@ void set_command_offset(int offset)
 	command_offset = offset;
 }
 
-int ec_command(int command, int version,
-	       const void *outdata, int outsize,
+int ec_command(int command, int version, const void *outdata, int outsize,
 	       void *indata, int insize)
 {
 	/* Offset command code to support sub-devices */
-	return ec_command_proto(command_offset + command, version,
-				outdata, outsize,
-				indata, insize);
+	return ec_command_proto(command_offset + command, version, outdata,
+				outsize, indata, insize);
 }
 
 int comm_init_alt(int interfaces, const char *device_name, int i2c_bus)
@@ -99,13 +95,13 @@ int comm_init_alt(int interfaces, const char *device_name, int i2c_bus)
 	dev_is_cros_ec = !strcmp(CROS_EC_DEV_NAME, device_name);
 
 	/* Fallback to direct LPC on x86 */
-	if (dev_is_cros_ec && (interfaces & COMM_LPC) &&
-			comm_init_lpc && !comm_init_lpc())
+	if (dev_is_cros_ec && (interfaces & COMM_LPC) && comm_init_lpc &&
+	    !comm_init_lpc())
 		return 0;
 
 	/* Fallback to direct I2C */
 	if ((dev_is_cros_ec || i2c_bus != -1) && (interfaces & COMM_I2C) &&
-			comm_init_i2c && !comm_init_i2c(i2c_bus))
+	    comm_init_i2c && !comm_init_i2c(i2c_bus))
 		return 0;
 
 	/* Give up */
@@ -134,11 +130,11 @@ int comm_init_buffer(void)
 
 	/* read max request / response size from ec for protocol v3+ */
 	if (ec_command(EC_CMD_GET_PROTOCOL_INFO, 0, NULL, 0, &info,
-		sizeof(info)) == sizeof(info)) {
+		       sizeof(info)) == sizeof(info)) {
 		int outsize = info.max_request_packet_size -
-			sizeof(struct ec_host_request);
+			      sizeof(struct ec_host_request);
 		int insize = info.max_response_packet_size -
-			sizeof(struct ec_host_response);
+			     sizeof(struct ec_host_response);
 		if ((allow_large_buffer) || (outsize < ec_max_outsize))
 			ec_max_outsize = outsize;
 		if ((allow_large_buffer) || (insize < ec_max_insize))
diff --git a/util/comm-host.h b/util/comm-host.h
index bd22655e57..907df3df96 100644
--- a/util/comm-host.h
+++ b/util/comm-host.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -63,9 +63,12 @@ int comm_init_buffer(void);
  * Send a command to the EC.  Returns the length of output data returned (0 if
  * none), or negative on error.
  */
-int ec_command(int command, int version,
-	       const void *outdata, int outsize,   /* to the EC */
-	       void *indata, int insize);	   /* from the EC */
+int ec_command(int command, int version, const void *outdata,
+	       int outsize, /* to
+			       the
+			       EC
+			     */
+	       void *indata, int insize); /* from the EC */
 
 /**
  * Set the offset to be applied to the command number when ec_command() calls
@@ -79,9 +82,9 @@ void set_command_offset(int offset);
  * by the protocol-specific driver.  DO NOT call this version directly from
  * anywhere but ec_command(), or the --device option will not work.
  */
-extern int (*ec_command_proto)(int command, int version,
-			       const void *outdata, int outsize, /* to EC */
-			       void *indata, int insize);        /* from EC */
+extern int (*ec_command_proto)(int command, int version, const void *outdata,
+			       int outsize, /* to EC */
+			       void *indata, int insize); /* from EC */
 
 /**
  * Return the content of the EC information area mapped as "memory".
diff --git a/util/comm-i2c.c b/util/comm-i2c.c
index d76749fbe5..1548beaaa2 100644
--- a/util/comm-i2c.c
+++ b/util/comm-i2c.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,7 +27,7 @@
 
 #define I2C_ADAPTER_NODE "/sys/class/i2c-adapter/i2c-%d/%d-%04x/name"
 #define I2C_ADAPTER_NAME "cros-ec-i2c"
-#define I2C_MAX_ADAPTER  32
+#define I2C_MAX_ADAPTER 32
 #define I2C_NODE "/dev/i2c-%d"
 
 #ifdef DEBUG
@@ -62,9 +62,8 @@ static void dump_buffer(const uint8_t *data, int length)
  * Sends a command to the EC (protocol v3). Returns the command status code
  * (>= 0), or a negative EC_RES_* value on error.
  */
-static int ec_command_i2c_3(int command, int version,
-			    const void *outdata, int outsize,
-			    void *indata, int insize)
+static int ec_command_i2c_3(int command, int version, const void *outdata,
+			    int outsize, void *indata, int insize)
 {
 	int ret = -EC_RES_ERROR;
 	int error;
@@ -87,8 +86,8 @@ static int ec_command_i2c_3(int command, int version,
 			insize, ec_max_insize);
 		return -EC_RES_ERROR;
 	}
-	req_len = I2C_REQUEST_HEADER_SIZE + sizeof(struct ec_host_request)
-		+ outsize;
+	req_len = I2C_REQUEST_HEADER_SIZE + sizeof(struct ec_host_request) +
+		  outsize;
 	req_buf = (uint8_t *)(calloc(1, req_len));
 	if (!req_buf)
 		goto done;
@@ -102,8 +101,8 @@ static int ec_command_i2c_3(int command, int version,
 	req->reserved = 0;
 	req->data_len = outsize;
 
-	memcpy(&req_buf[I2C_REQUEST_HEADER_SIZE
-			+ sizeof(struct ec_host_request)],
+	memcpy(&req_buf[I2C_REQUEST_HEADER_SIZE +
+			sizeof(struct ec_host_request)],
 	       outdata, outsize);
 
 	req->checksum =
@@ -115,8 +114,8 @@ static int ec_command_i2c_3(int command, int version,
 	i2c_msg.len = req_len;
 	i2c_msg.buf = req_buf;
 
-	resp_len = I2C_RESPONSE_HEADER_SIZE + sizeof(struct ec_host_response)
-		+ insize;
+	resp_len = I2C_RESPONSE_HEADER_SIZE + sizeof(struct ec_host_response) +
+		   insize;
 	resp_buf = (uint8_t *)(calloc(1, resp_len));
 	if (!resp_buf)
 		goto done;
@@ -135,8 +134,8 @@ static int ec_command_i2c_3(int command, int version,
 	data.nmsgs = 1;
 	error = ioctl(i2c_fd, I2C_RDWR, &data);
 	if (error < 0) {
-		fprintf(stderr, "I2C write failed: %d (err: %d, %s)\n",
-			error, errno, strerror(errno));
+		fprintf(stderr, "I2C write failed: %d (err: %d, %s)\n", error,
+			errno, strerror(errno));
 		goto done;
 	}
 
@@ -146,8 +145,8 @@ static int ec_command_i2c_3(int command, int version,
 	i2c_msg.buf = resp_buf;
 	error = ioctl(i2c_fd, I2C_RDWR, &data);
 	if (error < 0) {
-		fprintf(stderr, "I2C read failed: %d (err: %d, %s)\n",
-			error, errno, strerror(errno));
+		fprintf(stderr, "I2C read failed: %d (err: %d, %s)\n", error,
+			errno, strerror(errno));
 		goto done;
 	}
 
@@ -177,15 +176,16 @@ static int ec_command_i2c_3(int command, int version,
 		goto done;
 	}
 
-	if ((uint8_t)sum_bytes(&resp_buf[I2C_RESPONSE_HEADER_SIZE], resp_buf[1])
-			!= 0) {
+	if ((uint8_t)sum_bytes(&resp_buf[I2C_RESPONSE_HEADER_SIZE],
+			       resp_buf[1]) != 0) {
 		debug("Bad checksum on EC response.\n");
 		ret = -EC_RES_INVALID_CHECKSUM;
 		goto done;
 	}
 
-	memcpy(indata, &resp_buf[I2C_RESPONSE_HEADER_SIZE
-				 + sizeof(struct ec_host_response)],
+	memcpy(indata,
+	       &resp_buf[I2C_RESPONSE_HEADER_SIZE +
+			 sizeof(struct ec_host_response)],
 	       insize);
 
 	ret = resp->data_len;
@@ -208,7 +208,8 @@ int comm_init_i2c(int i2c_bus)
 		i = i2c_bus;
 
 		if (i >= I2C_MAX_ADAPTER) {
-			fprintf(stderr, "Invalid I2C bus number %d. (The highest possible bus number is %d.)\n",
+			fprintf(stderr,
+				"Invalid I2C bus number %d. (The highest possible bus number is %d.)\n",
 				i, I2C_MAX_ADAPTER);
 			return -1;
 		}
@@ -217,8 +218,8 @@ int comm_init_i2c(int i2c_bus)
 		for (i = 0; i < I2C_MAX_ADAPTER; i++) {
 			FILE *f;
 
-			if (asprintf(&file_path, I2C_ADAPTER_NODE,
-				     i, i, EC_I2C_ADDR) < 0)
+			if (asprintf(&file_path, I2C_ADAPTER_NODE, i, i,
+				     EC_I2C_ADDR) < 0)
 				return -1;
 			f = fopen(file_path, "r");
 			if (f) {
@@ -248,10 +249,10 @@ int comm_init_i2c(int i2c_bus)
 	free(file_path);
 
 	ec_command_proto = ec_command_i2c_3;
-	ec_max_outsize = I2C_MAX_HOST_PACKET_SIZE - I2C_REQUEST_HEADER_SIZE
-		- sizeof(struct ec_host_request);
-	ec_max_insize = I2C_MAX_HOST_PACKET_SIZE - I2C_RESPONSE_HEADER_SIZE
-		- sizeof(struct ec_host_response);
+	ec_max_outsize = I2C_MAX_HOST_PACKET_SIZE - I2C_REQUEST_HEADER_SIZE -
+			 sizeof(struct ec_host_request);
+	ec_max_insize = I2C_MAX_HOST_PACKET_SIZE - I2C_RESPONSE_HEADER_SIZE -
+			sizeof(struct ec_host_response);
 
 	return 0;
 }
diff --git a/util/comm-lpc.c b/util/comm-lpc.c
index d1ce761fc2..8e2042f0cc 100644
--- a/util/comm-lpc.c
+++ b/util/comm-lpc.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,7 +14,7 @@
 
 #include "comm-host.h"
 
-#define INITIAL_UDELAY 5     /* 5 us */
+#define INITIAL_UDELAY 5 /* 5 us */
 #define MAXIMUM_UDELAY 10000 /* 10 ms */
 
 /*
@@ -43,12 +43,11 @@ static int wait_for_ec(int status_addr, int timeout_usec)
 		if (i > 20)
 			delay = MIN(delay * 2, MAXIMUM_UDELAY);
 	}
-	return -1;  /* Timeout */
+	return -1; /* Timeout */
 }
 
-static int ec_command_lpc(int command, int version,
-			  const void *outdata, int outsize,
-			  void *indata, int insize)
+static int ec_command_lpc(int command, int version, const void *outdata,
+			  int outsize, void *indata, int insize)
 {
 	struct ec_lpc_host_args args;
 	const uint8_t *d;
@@ -112,8 +111,7 @@ static int ec_command_lpc(int command, int version,
 	csum = command + args.flags + args.command_version + args.data_size;
 
 	/* Read response and update checksum */
-	for (i = 0, dout = (uint8_t *)indata; i < args.data_size;
-	     i++, dout++) {
+	for (i = 0, dout = (uint8_t *)indata; i < args.data_size; i++, dout++) {
 		*dout = inb(EC_LPC_ADDR_HOST_PARAM + i);
 		csum += *dout;
 	}
@@ -128,9 +126,8 @@ static int ec_command_lpc(int command, int version,
 	return args.data_size;
 }
 
-static int ec_command_lpc_3(int command, int version,
-			  const void *outdata, int outsize,
-			  void *indata, int insize)
+static int ec_command_lpc_3(int command, int version, const void *outdata,
+			    int outsize, void *indata, int insize)
 {
 	struct ec_host_request rq;
 	struct ec_host_response rs;
@@ -231,10 +228,10 @@ static int ec_readmem_lpc(int offset, int bytes, void *dest)
 	if (offset >= EC_MEMMAP_SIZE - bytes)
 		return -1;
 
-	if (bytes) {				/* fixed length */
+	if (bytes) { /* fixed length */
 		for (; cnt < bytes; i++, s++, cnt++)
 			*s = inb(EC_LPC_ADDR_MEMMAP + i);
-	} else {				/* string */
+	} else { /* string */
 		for (; i < EC_MEMMAP_SIZE; i++, s++) {
 			*s = inb(EC_LPC_ADDR_MEMMAP + i);
 			cnt++;
@@ -294,9 +291,9 @@ int comm_init_lpc(void)
 		/* Protocol version 3 */
 		ec_command_proto = ec_command_lpc_3;
 		ec_max_outsize = EC_LPC_HOST_PACKET_SIZE -
-			sizeof(struct ec_host_request);
+				 sizeof(struct ec_host_request);
 		ec_max_insize = EC_LPC_HOST_PACKET_SIZE -
-			sizeof(struct ec_host_response);
+				sizeof(struct ec_host_response);
 
 	} else if (i & EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED) {
 		/* Protocol version 2 */
diff --git a/util/comm-servo-spi.c b/util/comm-servo-spi.c
index ef6dc7880b..170b1e4e40 100644
--- a/util/comm-servo-spi.c
+++ b/util/comm-servo-spi.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -74,8 +74,8 @@ enum mpsse_pins {
  * propagates data on the falling edge
  * and reads data on the rising edge of the clock.
  */
-#define SPI_CMD_TX   (MPSSE_DO_WRITE | MPSSE_WRITE_NEG)
-#define SPI_CMD_RX   (MPSSE_DO_READ)
+#define SPI_CMD_TX (MPSSE_DO_WRITE | MPSSE_WRITE_NEG)
+#define SPI_CMD_RX (MPSSE_DO_READ)
 #define SPI_CMD_TXRX (MPSSE_DO_WRITE | MPSSE_DO_READ | MPSSE_WRITE_NEG)
 
 static int raw_read(uint8_t *buf, int size)
@@ -94,7 +94,7 @@ static int raw_read(uint8_t *buf, int size)
 
 static int mpsse_set_pins(uint8_t levels)
 {
-	uint8_t buf[MPSSE_CMD_SIZE] = {0};
+	uint8_t buf[MPSSE_CMD_SIZE] = { 0 };
 
 	buf[0] = SET_BITS_LOW;
 	buf[1] = levels;
@@ -103,8 +103,8 @@ static int mpsse_set_pins(uint8_t levels)
 	return ftdi_write_data(&ftdi, buf, sizeof(buf)) != sizeof(buf);
 }
 
-static int send_request(int cmd, int version,
-			const uint8_t *outdata, size_t outsize)
+static int send_request(int cmd, int version, const uint8_t *outdata,
+			size_t outsize)
 {
 	uint8_t *txbuf;
 	struct ec_host_request *request;
@@ -133,8 +133,8 @@ static int send_request(int cmd, int version,
 	request->data_len = outsize;
 
 	/* copy the data to transmit after the command header */
-	memcpy(txbuf + MPSSE_CMD_SIZE + sizeof(struct ec_host_request),
-	       outdata, outsize);
+	memcpy(txbuf + MPSSE_CMD_SIZE + sizeof(struct ec_host_request), outdata,
+	       outsize);
 
 	/* Compute the checksum */
 	for (i = MPSSE_CMD_SIZE; i < total_len; i++)
@@ -212,13 +212,12 @@ static int get_response(uint8_t *bodydest, size_t bodylen)
 	/* Check the header */
 	if (hdr.struct_version != EC_HOST_RESPONSE_VERSION) {
 		fprintf(stderr, "response version %d (should be %d)\n",
-			hdr.struct_version,
-			EC_HOST_RESPONSE_VERSION);
+			hdr.struct_version, EC_HOST_RESPONSE_VERSION);
 		return -EC_RES_ERROR;
 	}
 	if (hdr.data_len > bodylen) {
-		fprintf(stderr, "response data_len %d is > %zd\n",
-			hdr.data_len, bodylen);
+		fprintf(stderr, "response data_len %d is > %zd\n", hdr.data_len,
+			bodylen);
 		return -EC_RES_ERROR;
 	}
 
@@ -243,9 +242,8 @@ read_error:
 	return -EC_RES_ERROR;
 }
 
-static int ec_command_servo_spi(int cmd, int version,
-				const void *outdata, int outsize,
-				void *indata, int insize)
+static int ec_command_servo_spi(int cmd, int version, const void *outdata,
+				int outsize, void *indata, int insize)
 {
 	int ret = -EC_RES_ERROR;
 
@@ -275,7 +273,7 @@ static int mpsse_set_clock(uint32_t freq)
 {
 	uint32_t system_clock = 0;
 	uint16_t divisor = 0;
-	uint8_t buf[MPSSE_CMD_SIZE] = {0};
+	uint8_t buf[MPSSE_CMD_SIZE] = { 0 };
 
 	if (freq > 6000000) {
 		buf[0] = TCK_X5;
@@ -307,10 +305,10 @@ static void servo_spi_close(void)
 int comm_init_servo_spi(const char *device_name)
 {
 	int status;
-	uint8_t buf[MPSSE_CMD_SIZE] = {0};
+	uint8_t buf[MPSSE_CMD_SIZE] = { 0 };
 	/* if the user mentioned a device name, use it as serial string */
-	const char *serial = strcmp(CROS_EC_DEV_NAME, device_name) ?
-		device_name : NULL;
+	const char *serial =
+		strcmp(CROS_EC_DEV_NAME, device_name) ? device_name : NULL;
 
 	if (ftdi_init(&ftdi))
 		return -EC_RES_ERROR;
diff --git a/util/comm-usb.c b/util/comm-usb.c
index 9b362aa2f4..3d481b5532 100644
--- a/util/comm-usb.c
+++ b/util/comm-usb.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,12 +17,11 @@
 #include "misc_util.h"
 #include "usb_descriptor.h"
 
-#define USB_ERROR(m, r) \
-	fprintf(stderr, "%s:%d, %s returned %d (%s)\n", __FILE__, __LINE__, \
-		m, r, libusb_strerror(r))
+#define USB_ERROR(m, r) print_libusb_error(__FILE__, __LINE__, m, r)
 
 #ifdef DEBUG
-#define debug(fmt, arg...) printf("%s:%d: " fmt, __FILE__, __LINE__, ##arg)
+#define debug(fmt, arg...) \
+	fprintf(stderr, "%s:%d: " fmt, __FILE__, __LINE__, ##arg)
 #else
 #define debug(...)
 #endif
@@ -36,6 +35,16 @@ struct usb_endpoint {
 
 struct usb_endpoint uep;
 
+static void print_libusb_error(const char *file, int line, const char *message,
+			       int error_code)
+{
+	/*
+	 * TODO(b/247573723): Remove cast when libusb is upgraded.
+	 */
+	fprintf(stderr, "%s:%d, %s returned %d (%s)\n", file, line, message,
+		error_code, libusb_strerror((enum libusb_error)error_code));
+}
+
 void comm_usb_exit(void)
 {
 	debug("Exit libusb.\n");
@@ -53,21 +62,21 @@ void comm_usb_exit(void)
  * Actual USB transfer function, <allow_less> indicates that a valid response
  * (e.g. EC_CMD_GET_BUILD_INFO) could be shorter than <inlen>.
  *
- * Returns enum libusb_error (< 0) or -EECRESULT on error, <outlen> on success.
+ * Returns enum libusb_error (< 0) or -EECRESULT on error. On success, returns
+ * actually transferred OUT data size or IN data size if read is performed.
  */
 static int do_xfer(struct usb_endpoint *uep, void *outbuf, int outlen,
 		   void *inbuf, int inlen, int allow_less)
 {
-
 	int r, actual;
 
 	/* Send data out */
 	if (outbuf && outlen) {
 		actual = 0;
 		r = libusb_bulk_transfer(uep->devh, uep->ep_num,
-					 outbuf, outlen,
-					 &actual, 2000);
-		if (r < 0) {
+					 (uint8_t *)outbuf, outlen, &actual,
+					 2000);
+		if (r != 0) {
 			USB_ERROR("libusb_bulk_transfer", r);
 			return r;
 		}
@@ -77,15 +86,19 @@ static int do_xfer(struct usb_endpoint *uep, void *outbuf, int outlen,
 			return -EECRESULT;
 		}
 	}
-	debug("Sent %d bytes, expecting %d bytes.\n", outlen, inlen);
+	debug("Sent %d bytes, expecting to receive %d bytes.\n", outlen, inlen);
 
 	/* Read reply back */
 	if (inbuf && inlen) {
 		actual = 0;
+		/*
+		 * libusb_bulk_transfer may time out if actual < inlen and
+		 * actual is a multiple of ep->wMaxPacketSize.
+		 */
 		r = libusb_bulk_transfer(uep->devh, uep->ep_num | USB_DIR_IN,
-					 inbuf, inlen,
-					 &actual, 5000);
-		if (r < 0) {
+					 (uint8_t *)inbuf, inlen, &actual,
+					 5000);
+		if (r != 0) {
 			USB_ERROR("libusb_bulk_transfer", r);
 			return r;
 		}
@@ -96,8 +109,10 @@ static int do_xfer(struct usb_endpoint *uep, void *outbuf, int outlen,
 		}
 	}
 
-	debug("Received %d bytes.\n", inlen);
-	return outlen;
+	debug("Received %d bytes.\n", actual);
+
+	/* actual is useful for allow_less. */
+	return actual;
 }
 
 /* Return iface # or -1 if not found. */
@@ -141,29 +156,37 @@ int parse_vidpid(const char *input, uint16_t *vid_ptr, uint16_t *pid_ptr)
 {
 	char *copy, *s, *e;
 
+	int ret = 1;
+
 	copy = strdup(input);
 
 	s = strchr(copy, ':');
-	if (!s)
-		return 0;
+	if (!s) {
+		ret = 0;
+		goto cleanup;
+	}
 	*s++ = '\0';
 
 	e = NULL;
 	*vid_ptr = strtoul(copy, &e, 16);
-	if (e && *e)
-		return 0;
+	if (e && *e) {
+		ret = 0;
+		goto cleanup;
+	}
 
 	e = NULL;
 	*pid_ptr = strtoul(s, &e, 16);
-	if (e && *e)
-		return 0;
-
-	return 1;
+	if (e && *e) {
+		ret = 0;
+		goto cleanup;
+	}
+cleanup:
+	free(copy);
+	return ret;
 }
 
-static libusb_device_handle *check_device(libusb_device *dev,
-					  uint16_t vid, uint16_t pid,
-					  char *serialno)
+static libusb_device_handle *check_device(libusb_device *dev, uint16_t vid,
+					  uint16_t pid, char *serialno)
 {
 	struct libusb_device_descriptor desc;
 	libusb_device_handle *handle = NULL;
@@ -181,7 +204,9 @@ static libusb_device_handle *check_device(libusb_device *dev,
 
 	if (desc.iSerialNumber) {
 		r = libusb_get_string_descriptor_ascii(handle,
-			desc.iSerialNumber, (unsigned char *)sn, sizeof(sn));
+						       desc.iSerialNumber,
+						       (unsigned char *)sn,
+						       sizeof(sn));
 		if (r > 0)
 			snvalid = 1;
 	}
@@ -196,8 +221,8 @@ static libusb_device_handle *check_device(libusb_device *dev,
 	return handle;
 }
 
-static int find_endpoint(uint16_t vid, uint16_t pid,
-			 char *serialno, struct usb_endpoint *uep)
+static int find_endpoint(uint16_t vid, uint16_t pid, char *serialno,
+			 struct usb_endpoint *uep)
 {
 	int iface_num, r, i;
 	libusb_device **devs;
@@ -244,8 +269,8 @@ static int find_endpoint(uint16_t vid, uint16_t pid,
 		return -1;
 	}
 
-	debug("Found interface %d endpoint=%d, chunk_len=%d\n",
-	      iface_num, uep->ep_num, uep->chunk_len);
+	debug("Found interface %d endpoint=%d, chunk_len=%d\n", iface_num,
+	      uep->ep_num, uep->chunk_len);
 
 	libusb_set_auto_detach_kernel_driver(uep->devh, 1);
 	r = libusb_claim_interface(uep->devh, iface_num);
@@ -270,9 +295,8 @@ static int sum_bytes(const void *data, int length)
 	return sum;
 }
 
-static int ec_command_usb(int command, int version,
-			  const void *outdata, int outsize,
-			  void *indata, int insize)
+static int ec_command_usb(int command, int version, const void *outdata,
+			  int outsize, void *indata, int insize)
 {
 	struct ec_host_request *req;
 	struct ec_host_response *res;
@@ -283,13 +307,13 @@ static int ec_command_usb(int command, int version,
 	assert(insize == 0 || indata != NULL);
 
 	req_len = sizeof(*req) + outsize;
-	req = malloc(req_len);
+	req = (struct ec_host_request *)malloc(req_len);
 	res_len = sizeof(*res) + insize;
-	res = malloc(res_len);
+	res = (struct ec_host_response *)malloc(res_len);
 	if (req == NULL || res == NULL)
 		goto out;
 
-	req->struct_version = EC_HOST_REQUEST_VERSION;  /* 3 */
+	req->struct_version = EC_HOST_REQUEST_VERSION; /* 3 */
 	req->checksum = 0;
 	req->command = command;
 	req->command_version = version;
@@ -308,9 +332,10 @@ static int ec_command_usb(int command, int version,
 
 	if (indata)
 		memcpy(indata, &res[1], insize);
-	if (res->result != EC_RES_SUCCESS) {
+	if (res->result == EC_RES_SUCCESS)
+		rv = res->data_len;
+	else
 		rv = -EECRESULT - res->result;
-	}
 
 out:
 	if (req)
@@ -338,4 +363,3 @@ int comm_init_usb(uint16_t vid, uint16_t pid)
 
 	return 0;
 }
-
diff --git a/util/comm-usb.h b/util/comm-usb.h
index f821a10fe8..b43d1bf66f 100644
--- a/util/comm-usb.h
+++ b/util/comm-usb.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -34,4 +34,4 @@ int comm_init_usb(uint16_t vid, uint16_t pid);
  */
 void comm_usb_exit(void);
 
-#endif  /* __UTIL_COMM_USB_H */
+#endif /* __UTIL_COMM_USB_H */
diff --git a/util/compare_build.sh b/util/compare_build.sh
index 1b6030453a..e70dcdbed2 100755
--- a/util/compare_build.sh
+++ b/util/compare_build.sh
@@ -1,6 +1,6 @@
 #!/bin/bash
 
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -14,6 +14,7 @@
 # * all       - All boards that are built by the "buildall" target
 # * fp        - All relevant boards for fingerprint
 # * stm32     - All boards that use an STM32 chip
+# * stm32f0   - All boards that use an STM32F0 family of chip
 # * stm32f4   - All boards that use an STM32F4 family of chip
 # * stm32h7   - All boards that use an STM32H7 family of chip
 # * npcx      - "
@@ -50,7 +51,7 @@ DEFINE_string 'ref2' "HEAD^" 'Git reference (commit, branch, etc)'
 DEFINE_boolean 'keep' "${FLAGS_FALSE}" \
                'Remove the temp directory after comparison.' 'k'
 # Integer type can still be passed blank ("")
-DEFINE_integer 'jobs' "-1" 'Number of jobs to pass to make' 'j'
+DEFINE_integer 'jobs' "$(nproc)" 'Number of jobs to pass to make' 'j'
 # When compiling both refs for all boards, mem usage was larger than 32GB.
 # If you don't have more than 32GB, you probably don't want to build both
 # refs at the same time. Use the -o flag.
@@ -61,6 +62,9 @@ DEFINE_boolean 'private' "${FLAGS_PRIVATE_DEFAULT}" \
 
 # Usage: assoc-add-keys <associate_array_name> [item1 [item2...]]
 assoc-add-keys() {
+  # Shellcheck doesn't seem to support nameref variables yet.
+  # See https://github.com/koalaman/shellcheck/issues/1544.
+  # shellcheck disable=SC2034,SC2178
   local -n arr="${1}"
   shift
 
@@ -71,6 +75,9 @@ assoc-add-keys() {
 
 # Usage: assoc-rm-keys <associate_array_name> [item1 [item2...]
 assoc-rm-keys() {
+  # Shellcheck doesn't seem to support nameref variables yet.
+  # See https://github.com/koalaman/shellcheck/issues/1544.
+  # shellcheck disable=SC2034,SC2178
   local -n arr="${1}"
   shift
 
@@ -102,6 +109,8 @@ boards-with() {
 
 # Usage: parse-boards <associate_array_name> [board-grp1 [board-grp2...]]
 parse-boards() {
+  # Shellcheck doesn't seem to support nameref variables yet.
+  # See https://github.com/koalaman/shellcheck/issues/1544.
   # shellcheck disable=SC2034
   local -n boards="$1"
   shift
@@ -116,6 +125,7 @@ parse-boards() {
     [all]="$(make-print-boards)"
     [fp]="dartmonkey bloonchipper nucleo-dartmonkey nucleo-h743zi"
     [stm32]="$(boards-with 'CHIP[[:space:]:=]*stm32')"
+    [stm32f0]="$(boards-with 'CHIP_VARIANT[[:space:]:=]*stm32f0')"
     [stm32f4]="$(boards-with 'CHIP_VARIANT[[:space:]:=]*stm32f4')"
     [stm32h7]="$(boards-with 'CHIP_VARIANT[[:space:]:=]*stm32h7')"
     [npcx]="$(boards-with 'CHIP[[:space:]:=]*npcx')"
@@ -216,6 +226,7 @@ echo "# Preparing Makefile"
 cat > "${TMP_DIR}/Makefile" <<HEREDOC
 ORIGIN ?= $(realpath .)
 CRYPTOC_DIR ?= $(realpath ../../third_party/cryptoc)
+ZEPHYR_BASE ?= $(realpath ../../../src/third_party/zephyr/main)
 BOARDS ?= ${BOARDS[*]}
 LINKS ?= ${LINKS[*]}
 
@@ -233,6 +244,7 @@ build-%: ec-%
 	\$(MAKE) --no-print-directory -C \$(@:build-%=ec-%)                   \\
 		STATIC_VERSION=1                                              \\
 		CRYPTOC_DIR=\$(CRYPTOC_DIR)                                   \\
+		ZEPHYR_BASE=\$(ZEPHYR_BASE)                                   \\
 		\$(addprefix proj-,\$(BOARDS))
 	@printf "  MKDIR   %s\n" "\$@"
 	@mkdir -p \$@
diff --git a/util/config_allowed.txt b/util/config_allowed.txt
index 933f22a83c..7a8e3ffbba 100644
--- a/util/config_allowed.txt
+++ b/util/config_allowed.txt
@@ -10,7 +10,6 @@ CONFIG_ACCELGYRO_ICM42607_INT_EVENT
 CONFIG_ACCELGYRO_ICM426XX_INT_EVENT
 CONFIG_ACCELGYRO_ICM_I2C
 CONFIG_ACCELGYRO_LSM6DS0
-CONFIG_ACCELGYRO_LSM6DSM
 CONFIG_ACCELGYRO_SEC_ADDR_FLAGS
 CONFIG_ACCEL_CAL_KASA_RADIUS_THRES
 CONFIG_ACCEL_CAL_MAX_TEMP
@@ -31,6 +30,7 @@ CONFIG_ACCEL_LNG2DM
 CONFIG_ACCEL_LSM6DSM_INT_EVENT
 CONFIG_ACCEL_LSM6DSO_INT_EVENT
 CONFIG_ACCEL_STD_REF_FRAME_OLD
+CONFIG_ADC
 CONFIG_ADC_BUTTONS
 CONFIG_ADC_PROFILE
 CONFIG_ADC_PROFILE_FAST_CONTINUOUS
@@ -175,7 +175,6 @@ CONFIG_CHARGE_STATE_DEBUG
 CONFIG_CHIPSET_ALDERLAKE
 CONFIG_CHIPSET_APL_GLK
 CONFIG_CHIPSET_APOLLOLAKE
-CONFIG_CHIPSET_BRASWELL
 CONFIG_CHIPSET_CANNONLAKE
 CONFIG_CHIPSET_CEZANNE
 CONFIG_CHIPSET_COMETLAKE
@@ -203,8 +202,8 @@ CONFIG_CHIPSET_SKYLAKE
 CONFIG_CHIPSET_SLP_S3_L_OVERRIDE
 CONFIG_CHIPSET_STONEY
 CONFIG_CHIPSET_TIGERLAKE
-CONFIG_CHIPSET_X86_RSMRST_DELAY
 CONFIG_CHIPSET_X86_RSMRST_AFTER_S5
+CONFIG_CHIPSET_X86_RSMRST_DELAY
 CONFIG_CHIP_DATA_IN_INIT_ROM
 CONFIG_CHIP_LFW_USE_ROM_SPI
 CONFIG_CHIP_MEMORY_REGIONS
@@ -388,7 +387,6 @@ CONFIG_EC_PROTECTED_STORAGE_OFF
 CONFIG_EC_PROTECTED_STORAGE_SIZE
 CONFIG_EC_WRITABLE_STORAGE_OFF
 CONFIG_EC_WRITABLE_STORAGE_SIZE
-CONFIG_EEPROM
 CONFIG_ENABLE_JTAG_SELECTION
 CONFIG_EVENT_LOG_SIZE
 CONFIG_EXPERIMENTAL_CONSOLE
@@ -480,13 +478,6 @@ CONFIG_HOSTCMD_ALIGNED
 CONFIG_HOSTCMD_AP_SET_SKUID
 CONFIG_HOSTCMD_BUTTON
 CONFIG_HOSTCMD_DEBUG_MODE
-CONFIG_HOSTCMD_ESPI_EC_CHAN_BITMAP
-CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ
-CONFIG_HOSTCMD_ESPI_EC_MODE
-CONFIG_HOSTCMD_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST
-CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-CONFIG_HOSTCMD_ESPI_VW_SLP_S5
 CONFIG_HOSTCMD_EVENTS
 CONFIG_HOSTCMD_FLASHPD
 CONFIG_HOSTCMD_FLASH_SPI_INFO
@@ -507,6 +498,10 @@ CONFIG_HOST_ESPI_VW_POWER_SIGNAL
 CONFIG_HOST_EVENT64
 CONFIG_HOST_EVENT64_REPORT_MASK
 CONFIG_HOST_EVENT_REPORT_MASK
+CONFIG_HOST_INTERFACE_ESPI_EC_CHAN_BITMAP
+CONFIG_HOST_INTERFACE_ESPI_EC_MAX_FREQ
+CONFIG_HOST_INTERFACE_ESPI_EC_MODE
+CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S5RFACE_ESPI_
 CONFIG_HOSYCMD_BATTERY_V2
 CONFIG_HWTIMER_64BIT
 CONFIG_HW_CRC
@@ -582,11 +577,11 @@ CONFIG_KEYBOARD_IRQ_GPIO
 CONFIG_KEYBOARD_KSO_BASE
 CONFIG_KEYBOARD_KSO_HIGH_DRIVE
 CONFIG_KEYBOARD_LANGUAGE_ID
+CONFIG_KEYBOARD_MULTIPLE
 CONFIG_KEYBOARD_POST_SCAN_CLOCKS
 CONFIG_KEYBOARD_PRINT_SCAN_TIMES
 CONFIG_KEYBOARD_RUNTIME_KEYS
 CONFIG_KEYBOARD_SCANCODE_CALLBACK
-CONFIG_KEYBOARD_STRICT_DEBOUNCE
 CONFIG_KEYBOARD_SUPPRESS_NOISE
 CONFIG_KEYBOARD_TABLET_MODE_SWITCH
 CONFIG_KEYBOARD_TEST
@@ -618,7 +613,6 @@ CONFIG_LN9310
 CONFIG_LOADER_MEM_OFF
 CONFIG_LOADER_SIZE
 CONFIG_LOADER_STORAGE_OFF
-CONFIG_LOG_MAX_LEVEL
 CONFIG_LOW_POWER_IDLE_LIMITED
 CONFIG_LOW_POWER_S0
 CONFIG_LOW_POWER_USE_LFIOSC
@@ -665,7 +659,6 @@ CONFIG_MEC_SRAM_BASE_START
 CONFIG_MEC_SRAM_SIZE
 CONFIG_MEC_TEST_EC_RORW_CRC
 CONFIG_MEMORY_REGIONS
-CONFIG_MFT_INPUT_LFCLK
 CONFIG_MIA_WDT_VEC
 CONFIG_MKBP_
 CONFIG_MKBP_USE_
@@ -675,6 +668,7 @@ CONFIG_MOTION_MIN_SENSE_WAIT_TIME
 CONFIG_MOTION_SENSE_RESUME_DELAY_US
 CONFIG_MOTION_SENSE_SUSPEND_DELAY_US
 CONFIG_MP4245
+CONFIG_MPU
 CONFIG_NAME
 CONFIG_NB7V904M_LPM_OVERRIDE
 CONFIG_NO_PINHOLD
@@ -716,14 +710,13 @@ CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD
 CONFIG_POWER_SIGNAL_RUNTIME_CONFIG
 CONFIG_POWER_TRACK_HOST_SLEEP_STATE
 CONFIG_PRESERVE_LOGS
-CONFIG_PRINTF_LEGACY_LI_FORMAT
+CONFIG_PRINTF_LONG_IS_32BITS
 CONFIG_PRINT_IN_INT
 CONFIG_PROGRAM_MEMORY_BASE
 CONFIG_PROGRAM_MEMORY_BASE_LOAD
 CONFIG_PS2
 CONFIG_PSTORE
 CONFIG_PVD
-CONFIG_PWM
 CONFIG_PWM_INPUT_LFCLK
 CONFIG_PWR_STATE_DISCHARGE_FULL
 CONFIG_RAM_BANKS
@@ -800,12 +793,9 @@ CONFIG_SHAREDLIB_SIZE
 CONFIG_SHAREDLIB_STORAGE_OFF
 CONFIG_SHAREDMEM_MINIMUM_SIZE
 CONFIG_SHAREDMEM_MINIMUM_SIZE_RWSIG
-CONFIG_SHELL_BACKEND_SERIAL_LOG_LEVEL
-CONFIG_SHELL_HELP
 CONFIG_SIMULATED_BUTTON
 CONFIG_SLEEP_TIMEOUT_MS
 CONFIG_SMBUS
-CONFIG_SOC
 CONFIG_SOFTWARE_CLZ
 CONFIG_SOFTWARE_CTZ
 CONFIG_SOMETHING
@@ -857,6 +847,8 @@ CONFIG_STREAM_USART1
 CONFIG_STREAM_USART2
 CONFIG_STREAM_USART3
 CONFIG_STREAM_USART4
+CONFIG_STREAM_USART5
+CONFIG_STREAM_USART9
 CONFIG_STREAM_USB
 CONFIG_SUPPORT_CHIP_HIBERNATION
 CONFIG_SUPPRESSED_HOST_COMMANDS
@@ -867,7 +859,6 @@ CONFIG_SYNC_COMMAND
 CONFIG_SYNC_INT_EVENT
 CONFIG_SYNC_QUEUE_SIZE
 CONFIG_SYSTEM_UNLOCK
-CONFIG_SYS_CLOCK_TICKS_PER_SEC
 CONFIG_SYV682X_HV_ILIM
 CONFIG_TASK_LIST
 CONFIG_TASK_PROFILING
@@ -897,8 +888,6 @@ CONFIG_TEST_TASK_LIST
 CONFIG_TEST_USB_PD_TIMER
 CONFIG_TEST_USB_PE_SM
 CONFIG_THERMISTOR_NCP15WB
-CONFIG_THREAD_MONITOR
-CONFIG_THREAD_NAME
 CONFIG_THROTTLE_AP_ON_BAT_OLTAGE
 CONFIG_THROTTLE_AP_ON_BAT_VOLTAGE
 CONFIG_TICK
@@ -1010,6 +999,7 @@ CONFIG_USB_PD_IDENTITY_HW_VERS
 CONFIG_USB_PD_IDENTITY_SW_VERS
 CONFIG_USB_PD_INITIAL_DRP_STATE
 CONFIG_USB_PD_INTERNAL_COMP
+CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT
 CONFIG_USB_PD_LOW_POWER
 CONFIG_USB_PD_LOW_POWER_IDLE_WHEN_CONNECTED
 CONFIG_USB_PD_MANUFACTURER_INFO
@@ -1062,7 +1052,6 @@ CONFIG_USB_RAM_ACCESS_TYPE
 CONFIG_USB_RAM_BASE
 CONFIG_USB_RAM_SIZE
 CONFIG_USB_REMOTE_WAKEUP
-CONFIG_USB_SELF_POWERED
 CONFIG_USB_SERIALNO
 CONFIG_USB_SPI
 CONFIG_USB_SPI_BUFFER_SIZE
@@ -1074,7 +1063,6 @@ CONFIG_WATCHDOG_HELP
 CONFIG_WATCHDOG_MAX_RETRIES
 CONFIG_WEBUSB_URL
 CONFIG_WIRELESS
-CONFIG_WIRELESS_CHARGER_P9221_R7
 CONFIG_WIRELESS_SUSPEND
 CONFIG_WLAN_POWER_ACTIVE_LOW
 CONFIG_WOV_FIFO_THRESH_WORDS
@@ -1083,6 +1071,5 @@ CONFIG_WP_ACTIVE_HIGH
 CONFIG_WP_ALWAYS
 CONFIG_WP_STORAGE_OFF
 CONFIG_WP_STORAGE_SIZE
-CONFIG_X86_64
 CONFIG_ZEPHYR
 CONFIG_xxx
diff --git a/util/config_option_check.py b/util/config_option_check.py
index 8bd8ecb1f0..25c026afe5 100755
--- a/util/config_option_check.py
+++ b/util/config_option_check.py
@@ -1,11 +1,7 @@
 #!/usr/bin/env python3
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
 
 """Configuration Option Checker.
 
@@ -13,6 +9,7 @@ Script to ensure that all configuration options for the Chrome EC are defined
 in config.h.
 """
 from __future__ import print_function
+
 import enum
 import os
 import re
@@ -21,368 +18,398 @@ import sys
 
 
 class Line(object):
-  """Class for each changed line in diff output.
+    """Class for each changed line in diff output.
 
-  Attributes:
-    line_num: The integer line number that this line appears in the file.
-    string: The literal string of this line.
-    line_type: '+' or '-' indicating if this line was an addition or
-      deletion.
-  """
+    Attributes:
+      line_num: The integer line number that this line appears in the file.
+      string: The literal string of this line.
+      line_type: '+' or '-' indicating if this line was an addition or
+        deletion.
+    """
 
-  def __init__(self, line_num, string, line_type):
-    """Inits Line with the line number and the actual string."""
-    self.line_num = line_num
-    self.string = string
-    self.line_type = line_type
+    def __init__(self, line_num, string, line_type):
+        """Inits Line with the line number and the actual string."""
+        self.line_num = line_num
+        self.string = string
+        self.line_type = line_type
 
 
 class Hunk(object):
-  """Class for a git diff hunk.
+    """Class for a git diff hunk.
 
-  Attributes:
-    filename: The name of the file that this hunk belongs to.
-    lines: A list of Line objects that are a part of this hunk.
-  """
+    Attributes:
+      filename: The name of the file that this hunk belongs to.
+      lines: A list of Line objects that are a part of this hunk.
+    """
 
-  def __init__(self, filename, lines):
-    """Inits Hunk with the filename and the list of lines of the hunk."""
-    self.filename = filename
-    self.lines = lines
+    def __init__(self, filename, lines):
+        """Inits Hunk with the filename and the list of lines of the hunk."""
+        self.filename = filename
+        self.lines = lines
 
 
 # Master file which is supposed to include all CONFIG_xxxx descriptions.
-CONFIG_FILE = 'include/config.h'
+CONFIG_FILE = "include/config.h"
 
 # Specific files which the checker should ignore.
-ALLOWLIST = [CONFIG_FILE, 'util/config_option_check.py']
+ALLOWLIST = [CONFIG_FILE, "util/config_option_check.py"]
 
 # Specific directories which the checker should ignore.
-ALLOW_PATTERN = re.compile('zephyr/.*')
+ALLOW_PATTERN = re.compile("zephyr/.*")
 
 # Specific CONFIG_* flags which the checker should ignore.
-ALLOWLIST_CONFIGS = ['CONFIG_ZTEST']
+ALLOWLIST_CONFIGS = ["CONFIG_ZTEST"]
+
 
 def obtain_current_config_options():
-  """Obtains current config options from include/config.h.
-
-  Scans through the main config file defined in CONFIG_FILE for all CONFIG_*
-  options.
-
-  Returns:
-    config_options: A list of all the config options in the main CONFIG_FILE.
-  """
-
-  config_options = []
-  config_option_re = re.compile(r'^#(define|undef)\s+(CONFIG_[A-Z0-9_]+)')
-  with open(CONFIG_FILE, 'r') as config_file:
-    for line in config_file:
-      result = config_option_re.search(line)
-      if not result:
-        continue
-      word = result.groups()[1]
-      if word not in config_options:
-        config_options.append(word)
-  return config_options
+    """Obtains current config options from include/config.h.
+
+    Scans through the main config file defined in CONFIG_FILE for all CONFIG_*
+    options.
+
+    Returns:
+      config_options: A list of all the config options in the main CONFIG_FILE.
+    """
+
+    config_options = []
+    config_option_re = re.compile(r"^#(define|undef)\s+(CONFIG_[A-Z0-9_]+)")
+    with open(CONFIG_FILE, "r") as config_file:
+        for line in config_file:
+            result = config_option_re.search(line)
+            if not result:
+                continue
+            word = result.groups()[1]
+            if word not in config_options:
+                config_options.append(word)
+    return config_options
+
 
 def obtain_config_options_in_use():
-  """Obtains all the config options in use in the repo.
-
-  Scans through the entire repo looking for all CONFIG_* options actively used.
-
-  Returns:
-   options_in_use: A set of all the config options in use in the repo.
-  """
-  file_list = []
-  cwd = os.getcwd()
-  config_option_re = re.compile(r'\b(CONFIG_[a-zA-Z0-9_]+)')
-  config_debug_option_re = re.compile(r'\b(CONFIG_DEBUG_[a-zA-Z0-9_]+)')
-  options_in_use = set()
-  for (dirpath, dirnames, filenames) in os.walk(cwd, topdown=True):
-    # Ignore the build and private directories (taken from .gitignore)
-    if 'build' in dirnames:
-      dirnames.remove('build')
-    if 'private' in dirnames:
-      dirnames.remove('private')
-    for f in filenames:
-      # Ignore hidden files.
-      if f.startswith('.'):
-        continue
-      # Only consider C source, assembler, and Make-style files.
-      if (os.path.splitext(f)[1] in ('.c', '.h', '.inc', '.S', '.mk') or
-          'Makefile' in f):
-        file_list.append(os.path.join(dirpath, f))
-
-  # Search through each file and build a set of the CONFIG_* options being
-  # used.
-
-  for f in file_list:
-    if CONFIG_FILE in f:
-      continue
-    with open(f, 'r') as cur_file:
-      for line in cur_file:
-        match = config_option_re.findall(line)
-        if match:
-          for option in match:
-            if not in_comment(f, line, option):
-              if option not in options_in_use:
-                options_in_use.add(option)
-
-  # Since debug options can be turned on at any time, assume that they are
-  # always in use in case any aren't being used.
-
-  with open(CONFIG_FILE, 'r') as config_file:
-    for line in config_file:
-      match = config_debug_option_re.findall(line)
-      if match:
-        for option in match:
-          if not in_comment(CONFIG_FILE, line, option):
-            if option not in options_in_use:
-              options_in_use.add(option)
-
-  return options_in_use
+    """Obtains all the config options in use in the repo.
+
+    Scans through the entire repo looking for all CONFIG_* options actively used.
+
+    Returns:
+     options_in_use: A set of all the config options in use in the repo.
+    """
+    file_list = []
+    cwd = os.getcwd()
+    config_option_re = re.compile(r"\b(CONFIG_[a-zA-Z0-9_]+)")
+    config_debug_option_re = re.compile(r"\b(CONFIG_DEBUG_[a-zA-Z0-9_]+)")
+    options_in_use = set()
+    for (dirpath, dirnames, filenames) in os.walk(cwd, topdown=True):
+        # Ignore the build and private directories (taken from .gitignore)
+        if "build" in dirnames:
+            dirnames.remove("build")
+        if "private" in dirnames:
+            dirnames.remove("private")
+        for f in filenames:
+            # Ignore hidden files.
+            if f.startswith("."):
+                continue
+            # Only consider C source, assembler, and Make-style files.
+            if (
+                os.path.splitext(f)[1] in (".c", ".h", ".inc", ".S", ".mk")
+                or "Makefile" in f
+            ):
+                file_list.append(os.path.join(dirpath, f))
+
+    # Search through each file and build a set of the CONFIG_* options being
+    # used.
+
+    for f in file_list:
+        if CONFIG_FILE in f:
+            continue
+        with open(f, "r") as cur_file:
+            for line in cur_file:
+                match = config_option_re.findall(line)
+                if match:
+                    for option in match:
+                        if not in_comment(f, line, option):
+                            if option not in options_in_use:
+                                options_in_use.add(option)
+
+    # Since debug options can be turned on at any time, assume that they are
+    # always in use in case any aren't being used.
+
+    with open(CONFIG_FILE, "r") as config_file:
+        for line in config_file:
+            match = config_debug_option_re.findall(line)
+            if match:
+                for option in match:
+                    if not in_comment(CONFIG_FILE, line, option):
+                        if option not in options_in_use:
+                            options_in_use.add(option)
+
+    return options_in_use
+
 
 def print_missing_config_options(hunks, config_options):
-  """Searches thru all the changes in hunks for missing options and prints them.
-
-  Args:
-    hunks: A list of Hunk objects which represent the hunks from the git
-      diff output.
-    config_options: A list of all the config options in the main CONFIG_FILE.
-
-  Returns:
-    missing_config_option: A boolean indicating if any CONFIG_* options
-      are missing from the main CONFIG_FILE in this commit or if any CONFIG_*
-      options removed are no longer being used in the repo.
-  """
-  missing_config_option = False
-  print_banner = True
-  deprecated_options = set()
-  # Determine longest CONFIG_* length to be used for formatting.
-  max_option_length = max(len(option) for option in config_options)
-  config_option_re = re.compile(r'\b(CONFIG_[a-zA-Z0-9_]+)')
-
-  # Search for all CONFIG_* options in use in the repo.
-  options_in_use = obtain_config_options_in_use()
-
-  # Check each hunk's line for a missing config option.
-  for h in hunks:
-    for l in h.lines:
-      # Check for the existence of a CONFIG_* in the line.
-      match = filter(lambda opt: opt in ALLOWLIST_CONFIGS,
-                     config_option_re.findall(l.string))
-      if not match:
-        continue
-
-      # At this point, an option was found in the line.  However, we need to
-      # verify that it is not within a comment.
-      violations = set()
-
-      for option in match:
-        if not in_comment(h.filename, l.string, option):
-          # Since the CONFIG_* option is not within a comment, we've found a
-          # violation.  We now need to determine if this line is a deletion or
-          # not.  For deletions, we will need to verify if this CONFIG_* option
-          # is no longer being used in the entire repo.
-
-          if l.line_type == '-':
-            if option not in options_in_use and option in config_options:
-              deprecated_options.add(option)
-          else:
-            violations.add(option)
-
-      # Check to see if the CONFIG_* option is in the config file and print the
-      # violations.
-      for option in match:
-        if option not in config_options and option in violations:
-          # Print the banner once.
-          if print_banner:
-            print('The following config options were found to be missing '
-                  'from %s.\n'
-                  'Please add new config options there along with '
-                  'descriptions.\n\n' % CONFIG_FILE)
-            print_banner = False
+    """Searches thru all the changes in hunks for missing options and prints them.
+
+    Args:
+      hunks: A list of Hunk objects which represent the hunks from the git
+        diff output.
+      config_options: A list of all the config options in the main CONFIG_FILE.
+
+    Returns:
+      missing_config_option: A boolean indicating if any CONFIG_* options
+        are missing from the main CONFIG_FILE in this commit or if any CONFIG_*
+        options removed are no longer being used in the repo.
+    """
+    missing_config_option = False
+    print_banner = True
+    deprecated_options = set()
+    # Determine longest CONFIG_* length to be used for formatting.
+    max_option_length = max(len(option) for option in config_options)
+    config_option_re = re.compile(r"\b(CONFIG_[a-zA-Z0-9_]+)")
+
+    # Search for all CONFIG_* options in use in the repo.
+    options_in_use = obtain_config_options_in_use()
+
+    # Check each hunk's line for a missing config option.
+    for h in hunks:
+        for l in h.lines:
+            # Check for the existence of a CONFIG_* in the line.
+            match = filter(
+                lambda opt: opt in ALLOWLIST_CONFIGS,
+                config_option_re.findall(l.string),
+            )
+            if not match:
+                continue
+
+            # At this point, an option was found in the line.  However, we need to
+            # verify that it is not within a comment.
+            violations = set()
+
+            for option in match:
+                if not in_comment(h.filename, l.string, option):
+                    # Since the CONFIG_* option is not within a comment, we've found a
+                    # violation.  We now need to determine if this line is a deletion or
+                    # not.  For deletions, we will need to verify if this CONFIG_* option
+                    # is no longer being used in the entire repo.
+
+                    if l.line_type == "-":
+                        if (
+                            option not in options_in_use
+                            and option in config_options
+                        ):
+                            deprecated_options.add(option)
+                    else:
+                        violations.add(option)
+
+            # Check to see if the CONFIG_* option is in the config file and print the
+            # violations.
+            for option in match:
+                if option not in config_options and option in violations:
+                    # Print the banner once.
+                    if print_banner:
+                        print(
+                            "The following config options were found to be missing "
+                            "from %s.\n"
+                            "Please add new config options there along with "
+                            "descriptions.\n\n" % CONFIG_FILE
+                        )
+                        print_banner = False
+                        missing_config_option = True
+                    # Print the misssing config option.
+                    print(
+                        "> %-*s %s:%s"
+                        % (max_option_length, option, h.filename, l.line_num)
+                    )
+
+    if deprecated_options:
+        print(
+            "\n\nThe following config options are being removed and also appear"
+            " to be the last uses\nof that option.  Please remove these "
+            "options from %s.\n\n" % CONFIG_FILE
+        )
+        for option in deprecated_options:
+            print("> %s" % option)
             missing_config_option = True
-          # Print the misssing config option.
-          print('> %-*s %s:%s' % (max_option_length, option,
-                                  h.filename,
-                                  l.line_num))
 
-  if deprecated_options:
-    print('\n\nThe following config options are being removed and also appear'
-          ' to be the last uses\nof that option.  Please remove these '
-          'options from %s.\n\n' % CONFIG_FILE)
-    for option in deprecated_options:
-      print('> %s' % option)
-      missing_config_option = True
+    return missing_config_option
 
-  return missing_config_option
 
 def in_comment(filename, line, substr):
-  """Checks if given substring appears in a comment.
-
-  Args:
-    filename: The filename where this line is from.  This is used to determine
-      what kind of comments to look for.
-    line: String of line to search in.
-    substr: Substring to search for in the line.
-
-  Returns:
-    is_in_comment: Boolean indicating if substr was in a comment.
-  """
-
-  c_style_ext = ('.c', '.h', '.inc', '.S')
-  make_style_ext = ('.mk')
-  is_in_comment = False
-
-  extension = os.path.splitext(filename)[1]
-  substr_idx = line.find(substr)
-
-  # Different files have different comment syntax;  Handle appropriately.
-  if extension in c_style_ext:
-    beg_comment_idx = line.find('/*')
-    end_comment_idx = line.find('*/')
-    if end_comment_idx == -1:
-      end_comment_idx = len(line)
-
-    if beg_comment_idx == -1:
-      # Check to see if this line is from a multi-line comment.
-      if line.lstrip().startswith('* '):
-        # It _seems_ like it is.
-        is_in_comment = True
-    else:
-      # Check to see if its actually inside the comment.
-      if beg_comment_idx < substr_idx < end_comment_idx:
-        is_in_comment = True
-  elif extension in make_style_ext or 'Makefile' in filename:
-    beg_comment_idx = line.find('#')
-    # Ignore everything to the right of the hash.
-    if beg_comment_idx < substr_idx and beg_comment_idx != -1:
-      is_in_comment = True
-  return is_in_comment
+    """Checks if given substring appears in a comment.
+
+    Args:
+      filename: The filename where this line is from.  This is used to determine
+        what kind of comments to look for.
+      line: String of line to search in.
+      substr: Substring to search for in the line.
+
+    Returns:
+      is_in_comment: Boolean indicating if substr was in a comment.
+    """
+
+    c_style_ext = (".c", ".h", ".inc", ".S")
+    make_style_ext = ".mk"
+    is_in_comment = False
+
+    extension = os.path.splitext(filename)[1]
+    substr_idx = line.find(substr)
+
+    # Different files have different comment syntax;  Handle appropriately.
+    if extension in c_style_ext:
+        beg_comment_idx = line.find("/*")
+        end_comment_idx = line.find("*/")
+        if end_comment_idx == -1:
+            end_comment_idx = len(line)
+
+        if beg_comment_idx == -1:
+            # Check to see if this line is from a multi-line comment.
+            if line.lstrip().startswith("* "):
+                # It _seems_ like it is.
+                is_in_comment = True
+        else:
+            # Check to see if its actually inside the comment.
+            if beg_comment_idx < substr_idx < end_comment_idx:
+                is_in_comment = True
+    elif extension in make_style_ext or "Makefile" in filename:
+        beg_comment_idx = line.find("#")
+        # Ignore everything to the right of the hash.
+        if beg_comment_idx < substr_idx and beg_comment_idx != -1:
+            is_in_comment = True
+    return is_in_comment
+
 
 def get_hunks():
-  """Gets the hunks of the most recent commit.
-
-  States:
-    new_file: Searching for a new file in the git diff.
-    filename_search: Searching for the filename of this hunk.
-    hunk: Searching for the beginning of a new hunk.
-    lines: Counting line numbers and searching for changes.
-
-  Returns:
-    hunks: A list of Hunk objects which represent the hunks in the git diff
-      output.
-  """
-
-  diff = []
-  hunks = []
-  hunk_lines = []
-  line = ''
-  filename = ''
-  i = 0
-  line_num = 0
-
-  # Regex patterns
-  new_file_re = re.compile(r'^diff --git')
-  filename_re = re.compile(r'^[+]{3} (.*)')
-  hunk_line_num_re = re.compile(r'^@@ -[0-9]+,[0-9]+ \+([0-9]+),[0-9]+ @@.*')
-  line_re = re.compile(r'^([+| |-])(.*)')
-
-  # Get the diff output.
-  proc = subprocess.run(['git', 'diff', '--cached', '-GCONFIG_*', '--no-prefix',
-                         '--no-ext-diff', 'HEAD~1'],
-                        stdout=subprocess.PIPE,
-                        encoding='utf-8',
-                        check=True)
-  diff = proc.stdout.splitlines()
-  if not diff:
-    return []
-  line = diff[0]
-
-  state = enum.Enum('state', 'NEW_FILE FILENAME_SEARCH HUNK LINES')
-  current_state = state.NEW_FILE
-
-  while True:
-    # Search for the beginning of a new file.
-    if current_state is state.NEW_FILE:
-      match = new_file_re.search(line)
-      if match:
-        current_state = state.FILENAME_SEARCH
-
-    # Search the diff output for a file name.
-    elif current_state is state.FILENAME_SEARCH:
-      # Search for a file name.
-      match = filename_re.search(line)
-      if match:
-        filename = match.groups(1)[0]
-        if filename in ALLOWLIST or ALLOW_PATTERN.match(filename):
-          # Skip the file if it's allowlisted.
-          current_state = state.NEW_FILE
-        else:
-          current_state = state.HUNK
-
-    # Search for a hunk.  Each hunk starts with a line describing the line
-    # numbers in the file.
-    elif current_state is state.HUNK:
-      hunk_lines = []
-      match = hunk_line_num_re.search(line)
-      if match:
-        # Extract the line number offset.
-        line_num = int(match.groups(1)[0])
-        current_state = state.LINES
-
-    # Start looking for changes.
-    elif current_state is state.LINES:
-      # Check if state needs updating.
-      new_hunk = hunk_line_num_re.search(line)
-      new_file = new_file_re.search(line)
-      if new_hunk:
-        current_state = state.HUNK
-        hunks.append(Hunk(filename, hunk_lines))
-        continue
-      elif new_file:
-        current_state = state.NEW_FILE
-        hunks.append(Hunk(filename, hunk_lines))
-        continue
-
-      match = line_re.search(line)
-      if match:
-        line_type = match.groups(1)[0]
-        # We only care about modifications.
-        if line_type != ' ':
-          hunk_lines.append(Line(line_num, match.groups(2)[1], line_type))
-        # Deletions don't count towards the line numbers.
-        if line_type != '-':
-          line_num += 1
-
-    # Advance to the next line
-    try:
-      i += 1
-      line = diff[i]
-    except IndexError:
-      # We've reached the end of the diff.  Return what we have.
-      if hunk_lines:
-        hunks.append(Hunk(filename, hunk_lines))
-      return hunks
+    """Gets the hunks of the most recent commit.
+
+    States:
+      new_file: Searching for a new file in the git diff.
+      filename_search: Searching for the filename of this hunk.
+      hunk: Searching for the beginning of a new hunk.
+      lines: Counting line numbers and searching for changes.
+
+    Returns:
+      hunks: A list of Hunk objects which represent the hunks in the git diff
+        output.
+    """
+
+    diff = []
+    hunks = []
+    hunk_lines = []
+    line = ""
+    filename = ""
+    i = 0
+    line_num = 0
+
+    # Regex patterns
+    new_file_re = re.compile(r"^diff --git")
+    filename_re = re.compile(r"^[+]{3} (.*)")
+    hunk_line_num_re = re.compile(r"^@@ -[0-9]+,[0-9]+ \+([0-9]+),[0-9]+ @@.*")
+    line_re = re.compile(r"^([+| |-])(.*)")
+
+    # Get the diff output.
+    proc = subprocess.run(
+        [
+            "git",
+            "diff",
+            "--cached",
+            "-GCONFIG_*",
+            "--no-prefix",
+            "--no-ext-diff",
+            "HEAD~1",
+        ],
+        stdout=subprocess.PIPE,
+        encoding="utf-8",
+        check=True,
+    )
+    diff = proc.stdout.splitlines()
+    if not diff:
+        return []
+    line = diff[0]
+
+    state = enum.Enum("state", "NEW_FILE FILENAME_SEARCH HUNK LINES")
+    current_state = state.NEW_FILE
+
+    while True:
+        # Search for the beginning of a new file.
+        if current_state is state.NEW_FILE:
+            match = new_file_re.search(line)
+            if match:
+                current_state = state.FILENAME_SEARCH
+
+        # Search the diff output for a file name.
+        elif current_state is state.FILENAME_SEARCH:
+            # Search for a file name.
+            match = filename_re.search(line)
+            if match:
+                filename = match.groups(1)[0]
+                if filename in ALLOWLIST or ALLOW_PATTERN.match(filename):
+                    # Skip the file if it's allowlisted.
+                    current_state = state.NEW_FILE
+                else:
+                    current_state = state.HUNK
+
+        # Search for a hunk.  Each hunk starts with a line describing the line
+        # numbers in the file.
+        elif current_state is state.HUNK:
+            hunk_lines = []
+            match = hunk_line_num_re.search(line)
+            if match:
+                # Extract the line number offset.
+                line_num = int(match.groups(1)[0])
+                current_state = state.LINES
+
+        # Start looking for changes.
+        elif current_state is state.LINES:
+            # Check if state needs updating.
+            new_hunk = hunk_line_num_re.search(line)
+            new_file = new_file_re.search(line)
+            if new_hunk:
+                current_state = state.HUNK
+                hunks.append(Hunk(filename, hunk_lines))
+                continue
+            elif new_file:
+                current_state = state.NEW_FILE
+                hunks.append(Hunk(filename, hunk_lines))
+                continue
+
+            match = line_re.search(line)
+            if match:
+                line_type = match.groups(1)[0]
+                # We only care about modifications.
+                if line_type != " ":
+                    hunk_lines.append(
+                        Line(line_num, match.groups(2)[1], line_type)
+                    )
+                # Deletions don't count towards the line numbers.
+                if line_type != "-":
+                    line_num += 1
+
+        # Advance to the next line
+        try:
+            i += 1
+            line = diff[i]
+        except IndexError:
+            # We've reached the end of the diff.  Return what we have.
+            if hunk_lines:
+                hunks.append(Hunk(filename, hunk_lines))
+            return hunks
+
 
 def main():
-  """Searches through committed changes for missing config options.
-
-  Checks through committed changes for CONFIG_* options.  Then checks to make
-  sure that all CONFIG_* options used are defined in include/config.h.  Finally,
-  reports any missing config options.
-  """
-  # Obtain the hunks of the commit to search through.
-  hunks = get_hunks()
-  # Obtain config options from include/config.h.
-  config_options = obtain_current_config_options()
-  # Find any missing config options from the hunks and print them.
-  missing_opts = print_missing_config_options(hunks, config_options)
-
-  if missing_opts:
-    print('\nIt may also be possible that you have a typo.')
-    sys.exit(1)
-
-if __name__ == '__main__':
-  main()
+    """Searches through committed changes for missing config options.
+
+    Checks through committed changes for CONFIG_* options.  Then checks to make
+    sure that all CONFIG_* options used are defined in include/config.h.  Finally,
+    reports any missing config options.
+    """
+    # Obtain the hunks of the commit to search through.
+    hunks = get_hunks()
+    # Obtain config options from include/config.h.
+    config_options = obtain_current_config_options()
+    # Find any missing config options from the hunks and print them.
+    missing_opts = print_missing_config_options(hunks, config_options)
+
+    if missing_opts:
+        print("\nIt may also be possible that you have a typo.")
+        sys.exit(1)
+
+
+if __name__ == "__main__":
+    main()
diff --git a/util/cros_ec_dev.h b/util/cros_ec_dev.h
index 41930f97dd..3ffed56632 100644
--- a/util/cros_ec_dev.h
+++ b/util/cros_ec_dev.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -50,9 +50,9 @@ struct cros_ec_readmem {
 	char *buffer;
 };
 
-#define CROS_EC_DEV_IOC              ':'
-#define CROS_EC_DEV_IOCXCMD    _IOWR(':', 0, struct cros_ec_command)
-#define CROS_EC_DEV_IOCRDMEM   _IOWR(':', 1, struct cros_ec_readmem)
+#define CROS_EC_DEV_IOC ':'
+#define CROS_EC_DEV_IOCXCMD _IOWR(':', 0, struct cros_ec_command)
+#define CROS_EC_DEV_IOCRDMEM _IOWR(':', 1, struct cros_ec_readmem)
 
 /*
  * @version: Command version number (often 0)
@@ -84,12 +84,12 @@ struct cros_ec_readmem_v2 {
 	uint8_t buffer[EC_MEMMAP_SIZE];
 };
 
-#define CROS_EC_DEV_IOC_V2	0xEC
-#define CROS_EC_DEV_IOCXCMD_V2	_IOWR(CROS_EC_DEV_IOC_V2, 0, \
-				      struct cros_ec_command_v2)
-#define CROS_EC_DEV_IOCRDMEM_V2	_IOWR(CROS_EC_DEV_IOC_V2, 1, \
-				      struct cros_ec_readmem_v2)
-#define CROS_EC_DEV_IOCEVENTMASK_V2	_IO(CROS_EC_DEV_IOC_V2, 2)
+#define CROS_EC_DEV_IOC_V2 0xEC
+#define CROS_EC_DEV_IOCXCMD_V2 \
+	_IOWR(CROS_EC_DEV_IOC_V2, 0, struct cros_ec_command_v2)
+#define CROS_EC_DEV_IOCRDMEM_V2 \
+	_IOWR(CROS_EC_DEV_IOC_V2, 1, struct cros_ec_readmem_v2)
+#define CROS_EC_DEV_IOCEVENTMASK_V2 _IO(CROS_EC_DEV_IOC_V2, 2)
 
 #ifdef __cplusplus
 }
diff --git a/util/dt-gpionames/dt.go b/util/dt-gpionames/dt.go
index 547d69708f..9e95aeb946 100644
--- a/util/dt-gpionames/dt.go
+++ b/util/dt-gpionames/dt.go
@@ -1,4 +1,4 @@
-// Copyright 2022 The Chromium OS Authors. All rights reserved.
+// Copyright 2022 The ChromiumOS Authors
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
diff --git a/util/dt-gpionames/gpionames.sh b/util/dt-gpionames/gpionames.sh
index 92b2bd4580..972dbbacd9 100755
--- a/util/dt-gpionames/gpionames.sh
+++ b/util/dt-gpionames/gpionames.sh
@@ -1,6 +1,6 @@
 #!/bin/bash
 #
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/util/ec3po/__init__.py b/util/ec3po/__init__.py
index 376ffdba04..b3534114ac 100644
--- a/util/ec3po/__init__.py
+++ b/util/ec3po/__init__.py
@@ -1,4 +1,4 @@
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/util/ec3po/console.py b/util/ec3po/console.py
index e71216e3f2..12b31baa60 100755
--- a/util/ec3po/console.py
+++ b/util/ec3po/console.py
@@ -1,5 +1,5 @@
 #!/usr/bin/env python
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -17,7 +17,6 @@ from __future__ import print_function
 import argparse
 import binascii
 import ctypes
-from datetime import datetime
 import logging
 import os
 import pty
@@ -26,26 +25,25 @@ import select
 import stat
 import sys
 import traceback
+from datetime import datetime
 
 import six
+from ec3po import interpreter, threadproc_shim
 
-from ec3po import interpreter
-from ec3po import threadproc_shim
-
-
-PROMPT = b'> '
+PROMPT = b"> "
 CONSOLE_INPUT_LINE_SIZE = 80  # Taken from the CONFIG_* with the same name.
 CONSOLE_MAX_READ = 100  # Max bytes to read at a time from the user.
 LOOK_BUFFER_SIZE = 256  # Size of search window when looking for the enhanced EC
-                        # image string.
+# image string.
 
 # In console_init(), the EC will print a string saying that the EC console is
 # enabled.  Enhanced images will print a slightly different string.  These
 # regular expressions are used to determine at reboot whether the EC image is
 # enhanced or not.
-ENHANCED_IMAGE_RE = re.compile(br'Enhanced Console is enabled '
-                               br'\(v([0-9]+\.[0-9]+\.[0-9]+)\)')
-NON_ENHANCED_IMAGE_RE = re.compile(br'Console is enabled; ')
+ENHANCED_IMAGE_RE = re.compile(
+    rb"Enhanced Console is enabled " rb"\(v([0-9]+\.[0-9]+\.[0-9]+)\)"
+)
+NON_ENHANCED_IMAGE_RE = re.compile(rb"Console is enabled; ")
 
 # The timeouts are really only useful for enhanced EC images, but otherwise just
 # serve as a delay for non-enhanced EC images.  Therefore, we can keep this
@@ -54,1118 +52,1225 @@ NON_ENHANCED_IMAGE_RE = re.compile(br'Console is enabled; ')
 # EC image, we can increase the timeout for stability just in case it takes a
 # bit longer to receive an ACK for some reason.
 NON_ENHANCED_EC_INTERROGATION_TIMEOUT = 0.3  # Maximum number of seconds to wait
-                                             # for a response to an
-                                             # interrogation of a non-enhanced
-                                             # EC image.
+# for a response to an
+# interrogation of a non-enhanced
+# EC image.
 ENHANCED_EC_INTERROGATION_TIMEOUT = 1.0  # Maximum number of seconds to wait for
-                                         # a response to an interrogation of an
-                                         # enhanced EC image.
+# a response to an interrogation of an
+# enhanced EC image.
 # List of modes which control when interrogations are performed with the EC.
-INTERROGATION_MODES = [b'never', b'always', b'auto']
+INTERROGATION_MODES = [b"never", b"always", b"auto"]
 # Format for printing host timestamp
-HOST_STRFTIME="%y-%m-%d %H:%M:%S.%f"
+HOST_STRFTIME = "%y-%m-%d %H:%M:%S.%f"
 
 
 class EscState(object):
-  """Class which contains an enumeration for states of ESC sequences."""
-  ESC_START = 1
-  ESC_BRACKET = 2
-  ESC_BRACKET_1 = 3
-  ESC_BRACKET_3 = 4
-  ESC_BRACKET_8 = 5
-
+    """Class which contains an enumeration for states of ESC sequences."""
 
-class ControlKey(object):
-  """Class which contains codes for various control keys."""
-  BACKSPACE = 0x08
-  CTRL_A = 0x01
-  CTRL_B = 0x02
-  CTRL_D = 0x04
-  CTRL_E = 0x05
-  CTRL_F = 0x06
-  CTRL_K = 0x0b
-  CTRL_N = 0xe
-  CTRL_P = 0x10
-  CARRIAGE_RETURN = 0x0d
-  ESC = 0x1b
+    ESC_START = 1
+    ESC_BRACKET = 2
+    ESC_BRACKET_1 = 3
+    ESC_BRACKET_3 = 4
+    ESC_BRACKET_8 = 5
 
 
-class Console(object):
-  """Class which provides the console interface between the EC and the user.
-
-  This class essentially represents the console interface between the user and
-  the EC.  It handles all of the console editing behaviour
-
-  Attributes:
-    logger: A logger for this module.
-    controller_pty: File descriptor to the controller side of the PTY. Used for
-      driving output to the user and receiving user input.
-    user_pty: A string representing the PTY name of the served console.
-    cmd_pipe: A socket.socket or multiprocessing.Connection object which
-      represents the console side of the command pipe.  This must be a
-      bidirectional pipe.  Console commands and responses utilize this pipe.
-    dbg_pipe: A socket.socket or multiprocessing.Connection object which
-      represents the console's read-only side of the debug pipe.  This must be a
-      unidirectional pipe attached to the intepreter.  EC debug messages use
-      this pipe.
-    oobm_queue: A queue.Queue or multiprocessing.Queue which is used for out of
-      band management for the interactive console.
-    input_buffer: A string representing the current input command.
-    input_buffer_pos: An integer representing the current position in the buffer
-      to insert a char.
-    partial_cmd: A string representing the command entered on a line before
-      pressing the up arrow keys.
-    esc_state: An integer represeting the current state within an escape
-      sequence.
-    line_limit: An integer representing the maximum number of characters on a
-      line.
-    history: A list of strings containing the past entered console commands.
-    history_pos: An integer representing the current history buffer position.
-      This index is used to show previous commands.
-    prompt: A string representing the console prompt displayed to the user.
-    enhanced_ec: A boolean indicating if the EC image that we are currently
-      communicating with is enhanced or not.  Enhanced EC images will support
-      packed commands and host commands over the UART.  This defaults to False
-      until we perform some handshaking.
-    interrogation_timeout: A float representing the current maximum seconds to
-      wait for a response to an interrogation.
-    receiving_oobm_cmd: A boolean indicating whether or not the console is in
-      the middle of receiving an out of band command.
-    pending_oobm_cmd: A string containing the pending OOBM command.
-    interrogation_mode: A string containing the current mode of whether
-      interrogations are performed with the EC or not and how often.
-    raw_debug: Flag to indicate whether per interrupt data should be logged to
-      debug
-    output_line_log_buffer: buffer for lines coming from the EC to log to debug
-  """
-
-  def __init__(self, controller_pty, user_pty, interface_pty, cmd_pipe, dbg_pipe,
-               name=None):
-    """Initalises a Console object with the provided arguments.
+class ControlKey(object):
+    """Class which contains codes for various control keys."""
 
-    Args:
-    controller_pty: File descriptor to the controller side of the PTY. Used for
-      driving output to the user and receiving user input.
-    user_pty: A string representing the PTY name of the served console.
-    interface_pty: A string representing the PTY name of the served command
-      interface.
-    cmd_pipe: A socket.socket or multiprocessing.Connection object which
-      represents the console side of the command pipe.  This must be a
-      bidirectional pipe.  Console commands and responses utilize this pipe.
-    dbg_pipe: A socket.socket or multiprocessing.Connection object which
-      represents the console's read-only side of the debug pipe.  This must be a
-      unidirectional pipe attached to the intepreter.  EC debug messages use
-      this pipe.
-    name: the console source name
-    """
-    # Create a unique logger based on the console name
-    console_prefix = ('%s - ' % name) if name else ''
-    logger = logging.getLogger('%sEC3PO.Console' % console_prefix)
-    self.logger = interpreter.LoggerAdapter(logger, {'pty': user_pty})
-    self.controller_pty = controller_pty
-    self.user_pty = user_pty
-    self.interface_pty = interface_pty
-    self.cmd_pipe = cmd_pipe
-    self.dbg_pipe = dbg_pipe
-    self.oobm_queue = threadproc_shim.Queue()
-    self.input_buffer = b''
-    self.input_buffer_pos = 0
-    self.partial_cmd = b''
-    self.esc_state = 0
-    self.line_limit = CONSOLE_INPUT_LINE_SIZE
-    self.history = []
-    self.history_pos = 0
-    self.prompt = PROMPT
-    self.enhanced_ec = False
-    self.interrogation_timeout = NON_ENHANCED_EC_INTERROGATION_TIMEOUT
-    self.receiving_oobm_cmd = False
-    self.pending_oobm_cmd = b''
-    self.interrogation_mode = b'auto'
-    self.timestamp_enabled = True
-    self.look_buffer = b''
-    self.raw_debug = False
-    self.output_line_log_buffer = []
-
-  def __str__(self):
-    """Show internal state of Console object as a string."""
-    string = []
-    string.append('controller_pty: %s' % self.controller_pty)
-    string.append('user_pty: %s' % self.user_pty)
-    string.append('interface_pty: %s' % self.interface_pty)
-    string.append('cmd_pipe: %s' % self.cmd_pipe)
-    string.append('dbg_pipe: %s' % self.dbg_pipe)
-    string.append('oobm_queue: %s' % self.oobm_queue)
-    string.append('input_buffer: %s' % self.input_buffer)
-    string.append('input_buffer_pos: %d' % self.input_buffer_pos)
-    string.append('esc_state: %d' % self.esc_state)
-    string.append('line_limit: %d' % self.line_limit)
-    string.append('history: %r' % self.history)
-    string.append('history_pos: %d' % self.history_pos)
-    string.append('prompt: %r' % self.prompt)
-    string.append('partial_cmd: %r'% self.partial_cmd)
-    string.append('interrogation_mode: %r' % self.interrogation_mode)
-    string.append('look_buffer: %r' % self.look_buffer)
-    return '\n'.join(string)
-
-  def LogConsoleOutput(self, data):
-    """Log to debug user MCU output to controller_pty when line is filled.
-
-    The logging also suppresses the Cr50 spinner lines by removing characters
-    when it sees backspaces.
+    BACKSPACE = 0x08
+    CTRL_A = 0x01
+    CTRL_B = 0x02
+    CTRL_D = 0x04
+    CTRL_E = 0x05
+    CTRL_F = 0x06
+    CTRL_K = 0x0B
+    CTRL_N = 0xE
+    CTRL_P = 0x10
+    CARRIAGE_RETURN = 0x0D
+    ESC = 0x1B
 
-    Args:
-      data: bytes - string received from MCU
-    """
-    data = list(data)
-    # For compatibility with python2 and python3, standardize on the data
-    # being a list of integers. This requires one more transformation in py2
-    if not isinstance(data[0], int):
-      data = [ord(c) for c in data]
-
-    # This is a list of already filtered characters (or placeholders).
-    line = self.output_line_log_buffer
-
-    # TODO(b/177480273): use raw strings here
-    symbols = {
-            ord(b'\n'): u'\\n',
-            ord(b'\r'): u'\\r',
-            ord(b'\t'): u'\\t'
-    }
-    # self.logger.debug(u'%s + %r', u''.join(line), ''.join(data))
-    while data:
-      # Recall, data is a list of integers, namely the byte values sent by
-      # the MCU.
-      byte = data.pop(0)
-      # This means that |byte| is an int.
-      if byte == ord('\n'):
-        line.append(symbols[byte])
-        if line:
-          self.logger.debug(u'%s', ''.join(line))
-        line = []
-      elif byte == ord('\b'):
-        # Backspace: trim the last character off the buffer
-        if line:
-          line.pop(-1)
-      elif byte in symbols:
-        line.append(symbols[byte])
-      elif byte < ord(' ') or byte > ord('~'):
-        # Turn any character that isn't printable ASCII into escaped hex.
-        # ' ' is chr(20), and 0-19 are unprintable control characters.
-        # '~' is chr(126), and 127 is DELETE.  128-255 are control and Latin-1.
-        line.append(u'\\x%02x' % byte)
-      else:
-        # byte is printable. Thus it is safe to use chr() to get the printable
-        # character out of it again.
-        line.append(u'%s' % chr(byte))
-    self.output_line_log_buffer = line
-
-  def PrintHistory(self):
-    """Print the history of entered commands."""
-    fd = self.controller_pty
-    # Make it pretty by figuring out how wide to pad the numbers.
-    wide = (len(self.history) // 10) + 1
-    for i in range(len(self.history)):
-      line = b' %*d %s\r\n' % (wide, i, self.history[i])
-      os.write(fd, line)
-
-  def ShowPreviousCommand(self):
-    """Shows the previous command from the history list."""
-    # There's nothing to do if there's no history at all.
-    if not self.history:
-      self.logger.debug('No history to print.')
-      return
-
-    # Don't do anything if there's no more history to show.
-    if self.history_pos == 0:
-      self.logger.debug('No more history to show.')
-      return
-
-    self.logger.debug('current history position: %d.', self.history_pos)
-
-    # Decrement the history buffer position.
-    self.history_pos -= 1
-    self.logger.debug('new history position.: %d', self.history_pos)
-
-    # Save the text entered on the console if any.
-    if self.history_pos == len(self.history)-1:
-      self.logger.debug('saving partial_cmd: %r', self.input_buffer)
-      self.partial_cmd = self.input_buffer
-
-    # Backspace the line.
-    for _ in range(self.input_buffer_pos):
-      self.SendBackspace()
-
-    # Print the last entry in the history buffer.
-    self.logger.debug('printing previous entry %d - %s', self.history_pos,
-                      self.history[self.history_pos])
-    fd = self.controller_pty
-    prev_cmd = self.history[self.history_pos]
-    os.write(fd, prev_cmd)
-    # Update the input buffer.
-    self.input_buffer = prev_cmd
-    self.input_buffer_pos = len(prev_cmd)
-
-  def ShowNextCommand(self):
-    """Shows the next command from the history list."""
-    # Don't do anything if there's no history at all.
-    if not self.history:
-      self.logger.debug('History buffer is empty.')
-      return
-
-    fd = self.controller_pty
-
-    self.logger.debug('current history position: %d', self.history_pos)
-    # Increment the history position.
-    self.history_pos += 1
-
-    # Restore the partial cmd.
-    if self.history_pos == len(self.history):
-      self.logger.debug('Restoring partial command of %r', self.partial_cmd)
-      # Backspace the line.
-      for _ in range(self.input_buffer_pos):
-        self.SendBackspace()
-      # Print the partially entered command if any.
-      os.write(fd, self.partial_cmd)
-      self.input_buffer = self.partial_cmd
-      self.input_buffer_pos = len(self.input_buffer)
-      # Now that we've printed it, clear the partial cmd storage.
-      self.partial_cmd = b''
-      # Reset history position.
-      self.history_pos = len(self.history)
-      return
-
-    self.logger.debug('new history position: %d', self.history_pos)
-    if self.history_pos > len(self.history)-1:
-      self.logger.debug('No more history to show.')
-      self.history_pos -= 1
-      self.logger.debug('Reset history position to %d', self.history_pos)
-      return
-
-    # Backspace the line.
-    for _ in range(self.input_buffer_pos):
-      self.SendBackspace()
-
-    # Print the newer entry from the history buffer.
-    self.logger.debug('printing next entry %d - %s', self.history_pos,
-                      self.history[self.history_pos])
-    next_cmd = self.history[self.history_pos]
-    os.write(fd, next_cmd)
-    # Update the input buffer.
-    self.input_buffer = next_cmd
-    self.input_buffer_pos = len(next_cmd)
-    self.logger.debug('new history position: %d.', self.history_pos)
-
-  def SliceOutChar(self):
-    """Remove a char from the line and shift everything over 1 column."""
-    fd = self.controller_pty
-    # Remove the character at the input_buffer_pos by slicing it out.
-    self.input_buffer = self.input_buffer[0:self.input_buffer_pos] + \
-                        self.input_buffer[self.input_buffer_pos+1:]
-    # Write the rest of the line
-    moved_col = os.write(fd, self.input_buffer[self.input_buffer_pos:])
-    # Write a space to clear out the last char
-    moved_col += os.write(fd, b' ')
-    # Update the input buffer position.
-    self.input_buffer_pos += moved_col
-    # Reset the cursor
-    self.MoveCursor('left', moved_col)
-
-  def HandleEsc(self, byte):
-    """HandleEsc processes escape sequences.
 
-    Args:
-      byte: An integer representing the current byte in the sequence.
+class Console(object):
+    """Class which provides the console interface between the EC and the user.
+
+    This class essentially represents the console interface between the user and
+    the EC.  It handles all of the console editing behaviour
+
+    Attributes:
+      logger: A logger for this module.
+      controller_pty: File descriptor to the controller side of the PTY. Used for
+        driving output to the user and receiving user input.
+      user_pty: A string representing the PTY name of the served console.
+      cmd_pipe: A socket.socket or multiprocessing.Connection object which
+        represents the console side of the command pipe.  This must be a
+        bidirectional pipe.  Console commands and responses utilize this pipe.
+      dbg_pipe: A socket.socket or multiprocessing.Connection object which
+        represents the console's read-only side of the debug pipe.  This must be a
+        unidirectional pipe attached to the intepreter.  EC debug messages use
+        this pipe.
+      oobm_queue: A queue.Queue or multiprocessing.Queue which is used for out of
+        band management for the interactive console.
+      input_buffer: A string representing the current input command.
+      input_buffer_pos: An integer representing the current position in the buffer
+        to insert a char.
+      partial_cmd: A string representing the command entered on a line before
+        pressing the up arrow keys.
+      esc_state: An integer represeting the current state within an escape
+        sequence.
+      line_limit: An integer representing the maximum number of characters on a
+        line.
+      history: A list of strings containing the past entered console commands.
+      history_pos: An integer representing the current history buffer position.
+        This index is used to show previous commands.
+      prompt: A string representing the console prompt displayed to the user.
+      enhanced_ec: A boolean indicating if the EC image that we are currently
+        communicating with is enhanced or not.  Enhanced EC images will support
+        packed commands and host commands over the UART.  This defaults to False
+        until we perform some handshaking.
+      interrogation_timeout: A float representing the current maximum seconds to
+        wait for a response to an interrogation.
+      receiving_oobm_cmd: A boolean indicating whether or not the console is in
+        the middle of receiving an out of band command.
+      pending_oobm_cmd: A string containing the pending OOBM command.
+      interrogation_mode: A string containing the current mode of whether
+        interrogations are performed with the EC or not and how often.
+      raw_debug: Flag to indicate whether per interrupt data should be logged to
+        debug
+      output_line_log_buffer: buffer for lines coming from the EC to log to debug
     """
-    # We shouldn't be handling an escape sequence if we haven't seen one.
-    assert self.esc_state != 0
-
-    if self.esc_state is EscState.ESC_START:
-      self.logger.debug('ESC_START')
-      if byte == ord('['):
-        self.esc_state = EscState.ESC_BRACKET
-        return
 
-      else:
-        self.logger.error('Unexpected sequence. %c', byte)
-        self.esc_state = 0
-
-    elif self.esc_state is EscState.ESC_BRACKET:
-      self.logger.debug('ESC_BRACKET')
-      # Left Arrow key was pressed.
-      if byte == ord('D'):
-        self.logger.debug('Left arrow key pressed.')
-        self.MoveCursor('left', 1)
-        self.esc_state = 0 # Reset the state.
-        return
-
-      # Right Arrow key.
-      elif byte == ord('C'):
-        self.logger.debug('Right arrow key pressed.')
-        self.MoveCursor('right', 1)
-        self.esc_state = 0 # Reset the state.
-        return
-
-      # Up Arrow key.
-      elif byte == ord('A'):
-        self.logger.debug('Up arrow key pressed.')
-        self.ShowPreviousCommand()
-        # Reset the state.
-        self.esc_state = 0 # Reset the state.
-        return
-
-      # Down Arrow key.
-      elif byte == ord('B'):
-        self.logger.debug('Down arrow key pressed.')
-        self.ShowNextCommand()
-        # Reset the state.
-        self.esc_state = 0 # Reset the state.
-        return
-
-      # For some reason, minicom sends a 1 instead of 7. /shrug
-      # TODO(aaboagye): Figure out why this happens.
-      elif byte == ord('1') or byte == ord('7'):
-        self.esc_state = EscState.ESC_BRACKET_1
-
-      elif byte == ord('3'):
-        self.esc_state = EscState.ESC_BRACKET_3
-
-      elif byte == ord('8'):
-        self.esc_state = EscState.ESC_BRACKET_8
-
-      else:
-        self.logger.error(r'Bad or unhandled escape sequence. got ^[%c\(%d)',
-                          chr(byte), byte)
-        self.esc_state = 0
-        return
-
-    elif self.esc_state is EscState.ESC_BRACKET_1:
-      self.logger.debug('ESC_BRACKET_1')
-      # HOME key.
-      if byte == ord('~'):
-        self.logger.debug('Home key pressed.')
-        self.MoveCursor('left', self.input_buffer_pos)
-        self.esc_state = 0 # Reset the state.
-        self.logger.debug('ESC sequence complete.')
-        return
-
-    elif self.esc_state is EscState.ESC_BRACKET_3:
-      self.logger.debug('ESC_BRACKET_3')
-      # DEL key.
-      if byte == ord('~'):
-        self.logger.debug('Delete key pressed.')
-        if self.input_buffer_pos != len(self.input_buffer):
-          self.SliceOutChar()
-        self.esc_state = 0 # Reset the state.
-
-    elif self.esc_state is EscState.ESC_BRACKET_8:
-      self.logger.debug('ESC_BRACKET_8')
-      # END key.
-      if byte == ord('~'):
-        self.logger.debug('End key pressed.')
-        self.MoveCursor('right',
-                        len(self.input_buffer) - self.input_buffer_pos)
-        self.esc_state = 0 # Reset the state.
-        self.logger.debug('ESC sequence complete.')
-        return
-
-      else:
-        self.logger.error('Unexpected sequence. %c', byte)
+    def __init__(
+        self,
+        controller_pty,
+        user_pty,
+        interface_pty,
+        cmd_pipe,
+        dbg_pipe,
+        name=None,
+    ):
+        """Initalises a Console object with the provided arguments.
+
+        Args:
+        controller_pty: File descriptor to the controller side of the PTY. Used for
+          driving output to the user and receiving user input.
+        user_pty: A string representing the PTY name of the served console.
+        interface_pty: A string representing the PTY name of the served command
+          interface.
+        cmd_pipe: A socket.socket or multiprocessing.Connection object which
+          represents the console side of the command pipe.  This must be a
+          bidirectional pipe.  Console commands and responses utilize this pipe.
+        dbg_pipe: A socket.socket or multiprocessing.Connection object which
+          represents the console's read-only side of the debug pipe.  This must be a
+          unidirectional pipe attached to the intepreter.  EC debug messages use
+          this pipe.
+        name: the console source name
+        """
+        # Create a unique logger based on the console name
+        console_prefix = ("%s - " % name) if name else ""
+        logger = logging.getLogger("%sEC3PO.Console" % console_prefix)
+        self.logger = interpreter.LoggerAdapter(logger, {"pty": user_pty})
+        self.controller_pty = controller_pty
+        self.user_pty = user_pty
+        self.interface_pty = interface_pty
+        self.cmd_pipe = cmd_pipe
+        self.dbg_pipe = dbg_pipe
+        self.oobm_queue = threadproc_shim.Queue()
+        self.input_buffer = b""
+        self.input_buffer_pos = 0
+        self.partial_cmd = b""
         self.esc_state = 0
+        self.line_limit = CONSOLE_INPUT_LINE_SIZE
+        self.history = []
+        self.history_pos = 0
+        self.prompt = PROMPT
+        self.enhanced_ec = False
+        self.interrogation_timeout = NON_ENHANCED_EC_INTERROGATION_TIMEOUT
+        self.receiving_oobm_cmd = False
+        self.pending_oobm_cmd = b""
+        self.interrogation_mode = b"auto"
+        self.timestamp_enabled = True
+        self.look_buffer = b""
+        self.raw_debug = False
+        self.output_line_log_buffer = []
+
+    def __str__(self):
+        """Show internal state of Console object as a string."""
+        string = []
+        string.append("controller_pty: %s" % self.controller_pty)
+        string.append("user_pty: %s" % self.user_pty)
+        string.append("interface_pty: %s" % self.interface_pty)
+        string.append("cmd_pipe: %s" % self.cmd_pipe)
+        string.append("dbg_pipe: %s" % self.dbg_pipe)
+        string.append("oobm_queue: %s" % self.oobm_queue)
+        string.append("input_buffer: %s" % self.input_buffer)
+        string.append("input_buffer_pos: %d" % self.input_buffer_pos)
+        string.append("esc_state: %d" % self.esc_state)
+        string.append("line_limit: %d" % self.line_limit)
+        string.append("history: %r" % self.history)
+        string.append("history_pos: %d" % self.history_pos)
+        string.append("prompt: %r" % self.prompt)
+        string.append("partial_cmd: %r" % self.partial_cmd)
+        string.append("interrogation_mode: %r" % self.interrogation_mode)
+        string.append("look_buffer: %r" % self.look_buffer)
+        return "\n".join(string)
+
+    def LogConsoleOutput(self, data):
+        """Log to debug user MCU output to controller_pty when line is filled.
+
+        The logging also suppresses the Cr50 spinner lines by removing characters
+        when it sees backspaces.
+
+        Args:
+          data: bytes - string received from MCU
+        """
+        data = list(data)
+        # For compatibility with python2 and python3, standardize on the data
+        # being a list of integers. This requires one more transformation in py2
+        if not isinstance(data[0], int):
+            data = [ord(c) for c in data]
+
+        # This is a list of already filtered characters (or placeholders).
+        line = self.output_line_log_buffer
+
+        # TODO(b/177480273): use raw strings here
+        symbols = {ord(b"\n"): "\\n", ord(b"\r"): "\\r", ord(b"\t"): "\\t"}
+        # self.logger.debug(u'%s + %r', u''.join(line), ''.join(data))
+        while data:
+            # Recall, data is a list of integers, namely the byte values sent by
+            # the MCU.
+            byte = data.pop(0)
+            # This means that |byte| is an int.
+            if byte == ord("\n"):
+                line.append(symbols[byte])
+                if line:
+                    self.logger.debug("%s", "".join(line))
+                line = []
+            elif byte == ord("\b"):
+                # Backspace: trim the last character off the buffer
+                if line:
+                    line.pop(-1)
+            elif byte in symbols:
+                line.append(symbols[byte])
+            elif byte < ord(" ") or byte > ord("~"):
+                # Turn any character that isn't printable ASCII into escaped hex.
+                # ' ' is chr(20), and 0-19 are unprintable control characters.
+                # '~' is chr(126), and 127 is DELETE.  128-255 are control and Latin-1.
+                line.append("\\x%02x" % byte)
+            else:
+                # byte is printable. Thus it is safe to use chr() to get the printable
+                # character out of it again.
+                line.append("%s" % chr(byte))
+        self.output_line_log_buffer = line
+
+    def PrintHistory(self):
+        """Print the history of entered commands."""
+        fd = self.controller_pty
+        # Make it pretty by figuring out how wide to pad the numbers.
+        wide = (len(self.history) // 10) + 1
+        for i in range(len(self.history)):
+            line = b" %*d %s\r\n" % (wide, i, self.history[i])
+            os.write(fd, line)
+
+    def ShowPreviousCommand(self):
+        """Shows the previous command from the history list."""
+        # There's nothing to do if there's no history at all.
+        if not self.history:
+            self.logger.debug("No history to print.")
+            return
+
+        # Don't do anything if there's no more history to show.
+        if self.history_pos == 0:
+            self.logger.debug("No more history to show.")
+            return
+
+        self.logger.debug("current history position: %d.", self.history_pos)
+
+        # Decrement the history buffer position.
+        self.history_pos -= 1
+        self.logger.debug("new history position.: %d", self.history_pos)
+
+        # Save the text entered on the console if any.
+        if self.history_pos == len(self.history) - 1:
+            self.logger.debug("saving partial_cmd: %r", self.input_buffer)
+            self.partial_cmd = self.input_buffer
+
+        # Backspace the line.
+        for _ in range(self.input_buffer_pos):
+            self.SendBackspace()
+
+        # Print the last entry in the history buffer.
+        self.logger.debug(
+            "printing previous entry %d - %s",
+            self.history_pos,
+            self.history[self.history_pos],
+        )
+        fd = self.controller_pty
+        prev_cmd = self.history[self.history_pos]
+        os.write(fd, prev_cmd)
+        # Update the input buffer.
+        self.input_buffer = prev_cmd
+        self.input_buffer_pos = len(prev_cmd)
+
+    def ShowNextCommand(self):
+        """Shows the next command from the history list."""
+        # Don't do anything if there's no history at all.
+        if not self.history:
+            self.logger.debug("History buffer is empty.")
+            return
+
+        fd = self.controller_pty
+
+        self.logger.debug("current history position: %d", self.history_pos)
+        # Increment the history position.
+        self.history_pos += 1
+
+        # Restore the partial cmd.
+        if self.history_pos == len(self.history):
+            self.logger.debug(
+                "Restoring partial command of %r", self.partial_cmd
+            )
+            # Backspace the line.
+            for _ in range(self.input_buffer_pos):
+                self.SendBackspace()
+            # Print the partially entered command if any.
+            os.write(fd, self.partial_cmd)
+            self.input_buffer = self.partial_cmd
+            self.input_buffer_pos = len(self.input_buffer)
+            # Now that we've printed it, clear the partial cmd storage.
+            self.partial_cmd = b""
+            # Reset history position.
+            self.history_pos = len(self.history)
+            return
+
+        self.logger.debug("new history position: %d", self.history_pos)
+        if self.history_pos > len(self.history) - 1:
+            self.logger.debug("No more history to show.")
+            self.history_pos -= 1
+            self.logger.debug("Reset history position to %d", self.history_pos)
+            return
+
+        # Backspace the line.
+        for _ in range(self.input_buffer_pos):
+            self.SendBackspace()
+
+        # Print the newer entry from the history buffer.
+        self.logger.debug(
+            "printing next entry %d - %s",
+            self.history_pos,
+            self.history[self.history_pos],
+        )
+        next_cmd = self.history[self.history_pos]
+        os.write(fd, next_cmd)
+        # Update the input buffer.
+        self.input_buffer = next_cmd
+        self.input_buffer_pos = len(next_cmd)
+        self.logger.debug("new history position: %d.", self.history_pos)
+
+    def SliceOutChar(self):
+        """Remove a char from the line and shift everything over 1 column."""
+        fd = self.controller_pty
+        # Remove the character at the input_buffer_pos by slicing it out.
+        self.input_buffer = (
+            self.input_buffer[0 : self.input_buffer_pos]
+            + self.input_buffer[self.input_buffer_pos + 1 :]
+        )
+        # Write the rest of the line
+        moved_col = os.write(fd, self.input_buffer[self.input_buffer_pos :])
+        # Write a space to clear out the last char
+        moved_col += os.write(fd, b" ")
+        # Update the input buffer position.
+        self.input_buffer_pos += moved_col
+        # Reset the cursor
+        self.MoveCursor("left", moved_col)
+
+    def HandleEsc(self, byte):
+        """HandleEsc processes escape sequences.
+
+        Args:
+          byte: An integer representing the current byte in the sequence.
+        """
+        # We shouldn't be handling an escape sequence if we haven't seen one.
+        assert self.esc_state != 0
+
+        if self.esc_state is EscState.ESC_START:
+            self.logger.debug("ESC_START")
+            if byte == ord("["):
+                self.esc_state = EscState.ESC_BRACKET
+                return
+
+            else:
+                self.logger.error("Unexpected sequence. %c", byte)
+                self.esc_state = 0
+
+        elif self.esc_state is EscState.ESC_BRACKET:
+            self.logger.debug("ESC_BRACKET")
+            # Left Arrow key was pressed.
+            if byte == ord("D"):
+                self.logger.debug("Left arrow key pressed.")
+                self.MoveCursor("left", 1)
+                self.esc_state = 0  # Reset the state.
+                return
+
+            # Right Arrow key.
+            elif byte == ord("C"):
+                self.logger.debug("Right arrow key pressed.")
+                self.MoveCursor("right", 1)
+                self.esc_state = 0  # Reset the state.
+                return
+
+            # Up Arrow key.
+            elif byte == ord("A"):
+                self.logger.debug("Up arrow key pressed.")
+                self.ShowPreviousCommand()
+                # Reset the state.
+                self.esc_state = 0  # Reset the state.
+                return
+
+            # Down Arrow key.
+            elif byte == ord("B"):
+                self.logger.debug("Down arrow key pressed.")
+                self.ShowNextCommand()
+                # Reset the state.
+                self.esc_state = 0  # Reset the state.
+                return
+
+            # For some reason, minicom sends a 1 instead of 7. /shrug
+            # TODO(aaboagye): Figure out why this happens.
+            elif byte == ord("1") or byte == ord("7"):
+                self.esc_state = EscState.ESC_BRACKET_1
+
+            elif byte == ord("3"):
+                self.esc_state = EscState.ESC_BRACKET_3
+
+            elif byte == ord("8"):
+                self.esc_state = EscState.ESC_BRACKET_8
+
+            else:
+                self.logger.error(
+                    r"Bad or unhandled escape sequence. got ^[%c\(%d)",
+                    chr(byte),
+                    byte,
+                )
+                self.esc_state = 0
+                return
+
+        elif self.esc_state is EscState.ESC_BRACKET_1:
+            self.logger.debug("ESC_BRACKET_1")
+            # HOME key.
+            if byte == ord("~"):
+                self.logger.debug("Home key pressed.")
+                self.MoveCursor("left", self.input_buffer_pos)
+                self.esc_state = 0  # Reset the state.
+                self.logger.debug("ESC sequence complete.")
+                return
+
+        elif self.esc_state is EscState.ESC_BRACKET_3:
+            self.logger.debug("ESC_BRACKET_3")
+            # DEL key.
+            if byte == ord("~"):
+                self.logger.debug("Delete key pressed.")
+                if self.input_buffer_pos != len(self.input_buffer):
+                    self.SliceOutChar()
+                self.esc_state = 0  # Reset the state.
+
+        elif self.esc_state is EscState.ESC_BRACKET_8:
+            self.logger.debug("ESC_BRACKET_8")
+            # END key.
+            if byte == ord("~"):
+                self.logger.debug("End key pressed.")
+                self.MoveCursor(
+                    "right", len(self.input_buffer) - self.input_buffer_pos
+                )
+                self.esc_state = 0  # Reset the state.
+                self.logger.debug("ESC sequence complete.")
+                return
+
+            else:
+                self.logger.error("Unexpected sequence. %c", byte)
+                self.esc_state = 0
+
+        else:
+            self.logger.error("Unexpected sequence. %c", byte)
+            self.esc_state = 0
+
+    def ProcessInput(self):
+        """Captures the input determines what actions to take."""
+        # There's nothing to do if the input buffer is empty.
+        if len(self.input_buffer) == 0:
+            return
+
+        # Don't store 2 consecutive identical commands in the history.
+        if (
+            self.history
+            and self.history[-1] != self.input_buffer
+            or not self.history
+        ):
+            self.history.append(self.input_buffer)
+
+        # Split the command up by spaces.
+        line = self.input_buffer.split(b" ")
+        self.logger.debug("cmd: %s", self.input_buffer)
+        cmd = line[0].lower()
+
+        # The 'history' command is a special case that we handle locally.
+        if cmd == "history":
+            self.PrintHistory()
+            return
+
+        # Send the command to the interpreter.
+        self.logger.debug("Sending command to interpreter.")
+        self.cmd_pipe.send(self.input_buffer)
+
+    def CheckForEnhancedECImage(self):
+        """Performs an interrogation of the EC image.
+
+        Send a SYN and expect an ACK.  If no ACK or the response is incorrect, then
+        assume that the current EC image that we are talking to is not enhanced.
+
+        Returns:
+          is_enhanced: A boolean indicating whether the EC responded to the
+            interrogation correctly.
+
+        Raises:
+          EOFError: Allowed to propagate through from self.dbg_pipe.recv().
+        """
+        # Send interrogation byte and wait for the response.
+        self.logger.debug("Performing interrogation.")
+        self.cmd_pipe.send(interpreter.EC_SYN)
+
+        response = ""
+        if self.dbg_pipe.poll(self.interrogation_timeout):
+            response = self.dbg_pipe.recv()
+            self.logger.debug("response: %r", binascii.hexlify(response))
+        else:
+            self.logger.debug("Timed out waiting for EC_ACK")
+
+        # Verify the acknowledgment.
+        is_enhanced = response == interpreter.EC_ACK
+
+        if is_enhanced:
+            # Increase the interrogation timeout for stability purposes.
+            self.interrogation_timeout = ENHANCED_EC_INTERROGATION_TIMEOUT
+            self.logger.debug(
+                "Increasing interrogation timeout to %rs.",
+                self.interrogation_timeout,
+            )
+        else:
+            # Reduce the timeout in order to reduce the perceivable delay.
+            self.interrogation_timeout = NON_ENHANCED_EC_INTERROGATION_TIMEOUT
+            self.logger.debug(
+                "Reducing interrogation timeout to %rs.",
+                self.interrogation_timeout,
+            )
+
+        return is_enhanced
+
+    def HandleChar(self, byte):
+        """HandleChar does a certain action when it receives a character.
+
+        Args:
+          byte: An integer representing the character received from the user.
+
+        Raises:
+          EOFError: Allowed to propagate through from self.CheckForEnhancedECImage()
+              i.e. from self.dbg_pipe.recv().
+        """
+        fd = self.controller_pty
+
+        # Enter the OOBM prompt mode if the user presses '%'.
+        if byte == ord("%"):
+            self.logger.debug("Begin OOBM command.")
+            self.receiving_oobm_cmd = True
+            # Print a "prompt".
+            os.write(self.controller_pty, b"\r\n% ")
+            return
+
+        # Add chars to the pending OOBM command if we're currently receiving one.
+        if self.receiving_oobm_cmd and byte != ControlKey.CARRIAGE_RETURN:
+            tmp_bytes = six.int2byte(byte)
+            self.pending_oobm_cmd += tmp_bytes
+            self.logger.debug("%s", tmp_bytes)
+            os.write(self.controller_pty, tmp_bytes)
+            return
+
+        if byte == ControlKey.CARRIAGE_RETURN:
+            if self.receiving_oobm_cmd:
+                # Terminate the command and place it in the OOBM queue.
+                self.logger.debug("End OOBM command.")
+                if self.pending_oobm_cmd:
+                    self.oobm_queue.put(self.pending_oobm_cmd)
+                    self.logger.debug(
+                        "Placed %r into OOBM command queue.",
+                        self.pending_oobm_cmd,
+                    )
+
+                # Reset the state.
+                os.write(self.controller_pty, b"\r\n" + self.prompt)
+                self.input_buffer = b""
+                self.input_buffer_pos = 0
+                self.receiving_oobm_cmd = False
+                self.pending_oobm_cmd = b""
+                return
+
+            if self.interrogation_mode == b"never":
+                self.logger.debug(
+                    "Skipping interrogation because interrogation mode"
+                    " is set to never."
+                )
+            elif self.interrogation_mode == b"always":
+                # Only interrogate the EC if the interrogation mode is set to 'always'.
+                self.enhanced_ec = self.CheckForEnhancedECImage()
+                self.logger.debug("Enhanced EC image? %r", self.enhanced_ec)
+
+        if not self.enhanced_ec:
+            # Send everything straight to the EC to handle.
+            self.cmd_pipe.send(six.int2byte(byte))
+            # Reset the input buffer.
+            self.input_buffer = b""
+            self.input_buffer_pos = 0
+            self.logger.log(1, "Reset input buffer.")
+            return
+
+        # Keep handling the ESC sequence if we're in the middle of it.
+        if self.esc_state != 0:
+            self.HandleEsc(byte)
+            return
+
+        # When we're at the end of the line, we should only allow going backwards,
+        # backspace, carriage return, up, or down.  The arrow keys are escape
+        # sequences, so we let the escape...escape.
+        if self.input_buffer_pos >= self.line_limit and byte not in [
+            ControlKey.CTRL_B,
+            ControlKey.ESC,
+            ControlKey.BACKSPACE,
+            ControlKey.CTRL_A,
+            ControlKey.CARRIAGE_RETURN,
+            ControlKey.CTRL_P,
+            ControlKey.CTRL_N,
+        ]:
+            return
+
+        # If the input buffer is full we can't accept new chars.
+        buffer_full = len(self.input_buffer) >= self.line_limit
+
+        # Carriage_Return/Enter
+        if byte == ControlKey.CARRIAGE_RETURN:
+            self.logger.debug("Enter key pressed.")
+            # Put a carriage return/newline and the print the prompt.
+            os.write(fd, b"\r\n")
+
+            # TODO(aaboagye): When we control the printing of all output, print the
+            # prompt AFTER printing all the output.  We can't do it yet because we
+            # don't know how much is coming from the EC.
+
+            # Print the prompt.
+            os.write(fd, self.prompt)
+            # Process the input.
+            self.ProcessInput()
+            # Now, clear the buffer.
+            self.input_buffer = b""
+            self.input_buffer_pos = 0
+            # Reset history buffer pos.
+            self.history_pos = len(self.history)
+            # Clear partial command.
+            self.partial_cmd = b""
+
+        # Backspace
+        elif byte == ControlKey.BACKSPACE:
+            self.logger.debug("Backspace pressed.")
+            if self.input_buffer_pos > 0:
+                # Move left 1 column.
+                self.MoveCursor("left", 1)
+                # Remove the character at the input_buffer_pos by slicing it out.
+                self.SliceOutChar()
+
+            self.logger.debug("input_buffer_pos: %d", self.input_buffer_pos)
+
+        # Ctrl+A. Move cursor to beginning of the line
+        elif byte == ControlKey.CTRL_A:
+            self.logger.debug("Control+A pressed.")
+            self.MoveCursor("left", self.input_buffer_pos)
+
+        # Ctrl+B. Move cursor left 1 column.
+        elif byte == ControlKey.CTRL_B:
+            self.logger.debug("Control+B pressed.")
+            self.MoveCursor("left", 1)
+
+        # Ctrl+D. Delete a character.
+        elif byte == ControlKey.CTRL_D:
+            self.logger.debug("Control+D pressed.")
+            if self.input_buffer_pos != len(self.input_buffer):
+                # Remove the character by slicing it out.
+                self.SliceOutChar()
+
+        # Ctrl+E. Move cursor to end of the line.
+        elif byte == ControlKey.CTRL_E:
+            self.logger.debug("Control+E pressed.")
+            self.MoveCursor(
+                "right", len(self.input_buffer) - self.input_buffer_pos
+            )
+
+        # Ctrl+F. Move cursor right 1 column.
+        elif byte == ControlKey.CTRL_F:
+            self.logger.debug("Control+F pressed.")
+            self.MoveCursor("right", 1)
+
+        # Ctrl+K. Kill line.
+        elif byte == ControlKey.CTRL_K:
+            self.logger.debug("Control+K pressed.")
+            self.KillLine()
+
+        # Ctrl+N. Next line.
+        elif byte == ControlKey.CTRL_N:
+            self.logger.debug("Control+N pressed.")
+            self.ShowNextCommand()
+
+        # Ctrl+P. Previous line.
+        elif byte == ControlKey.CTRL_P:
+            self.logger.debug("Control+P pressed.")
+            self.ShowPreviousCommand()
+
+        # ESC sequence
+        elif byte == ControlKey.ESC:
+            # Starting an ESC sequence
+            self.esc_state = EscState.ESC_START
+
+        # Only print printable chars.
+        elif IsPrintable(byte):
+            # Drop the character if we're full.
+            if buffer_full:
+                self.logger.debug("Dropped char: %c(%d)", byte, byte)
+                return
+            # Print the character.
+            os.write(fd, six.int2byte(byte))
+            # Print the rest of the line (if any).
+            extra_bytes_written = os.write(
+                fd, self.input_buffer[self.input_buffer_pos :]
+            )
+
+            # Recreate the input buffer.
+            self.input_buffer = (
+                self.input_buffer[0 : self.input_buffer_pos]
+                + six.int2byte(byte)
+                + self.input_buffer[self.input_buffer_pos :]
+            )
+            # Update the input buffer position.
+            self.input_buffer_pos += 1 + extra_bytes_written
+
+            # Reset the cursor if we wrote any extra bytes.
+            if extra_bytes_written:
+                self.MoveCursor("left", extra_bytes_written)
+
+            self.logger.debug("input_buffer_pos: %d", self.input_buffer_pos)
+
+    def MoveCursor(self, direction, count):
+        """MoveCursor moves the cursor left or right by count columns.
+
+        Args:
+          direction: A string that should be either 'left' or 'right' representing
+            the direction to move the cursor on the console.
+          count: An integer representing how many columns the cursor should be
+            moved.
+
+        Raises:
+          AssertionError: If the direction is not equal to 'left' or 'right'.
+        """
+        # If there's nothing to move, we're done.
+        if not count:
+            return
+        fd = self.controller_pty
+        seq = b"\033[" + str(count).encode("ascii")
+        if direction == "left":
+            # Bind the movement.
+            if count > self.input_buffer_pos:
+                count = self.input_buffer_pos
+            seq += b"D"
+            self.logger.debug("move cursor left %d", count)
+            self.input_buffer_pos -= count
+
+        elif direction == "right":
+            # Bind the movement.
+            if (count + self.input_buffer_pos) > len(self.input_buffer):
+                count = 0
+            seq += b"C"
+            self.logger.debug("move cursor right %d", count)
+            self.input_buffer_pos += count
+
+        else:
+            raise AssertionError(
+                ("The only valid directions are 'left' and 'right'")
+            )
+
+        self.logger.debug("input_buffer_pos: %d", self.input_buffer_pos)
+        # Move the cursor.
+        if count != 0:
+            os.write(fd, seq)
+
+    def KillLine(self):
+        """Kill the rest of the line based on the input buffer position."""
+        # Killing the line is killing all the text to the right.
+        diff = len(self.input_buffer) - self.input_buffer_pos
+        self.logger.debug("diff: %d", diff)
+        # Diff shouldn't be negative, but if it is for some reason, let's try to
+        # correct the cursor.
+        if diff < 0:
+            self.logger.warning(
+                "Resetting input buffer position to %d...",
+                len(self.input_buffer),
+            )
+            self.MoveCursor("left", -diff)
+            return
+        if diff:
+            self.MoveCursor("right", diff)
+            for _ in range(diff):
+                self.SendBackspace()
+            self.input_buffer_pos -= diff
+            self.input_buffer = self.input_buffer[0 : self.input_buffer_pos]
+
+    def SendBackspace(self):
+        """Backspace a character on the console."""
+        os.write(self.controller_pty, b"\033[1D \033[1D")
+
+    def ProcessOOBMQueue(self):
+        """Retrieve an item from the OOBM queue and process it."""
+        item = self.oobm_queue.get()
+        self.logger.debug("OOBM cmd: %r", item)
+        cmd = item.split(b" ")
+
+        if cmd[0] == b"loglevel":
+            # An integer is required in order to set the log level.
+            if len(cmd) < 2:
+                self.logger.debug("Insufficient args")
+                self.PrintOOBMHelp()
+                return
+            try:
+                self.logger.debug("Log level change request.")
+                new_log_level = int(cmd[1])
+                self.logger.logger.setLevel(new_log_level)
+                self.logger.info("Log level changed to %d.", new_log_level)
+
+                # Forward the request to the interpreter as well.
+                self.cmd_pipe.send(item)
+            except ValueError:
+                # Ignoring the request if an integer was not provided.
+                self.PrintOOBMHelp()
+
+        elif cmd[0] == b"timestamp":
+            mode = cmd[1].lower()
+            self.timestamp_enabled = mode == b"on"
+            self.logger.info(
+                "%sabling uart timestamps.",
+                "En" if self.timestamp_enabled else "Dis",
+            )
+
+        elif cmd[0] == b"rawdebug":
+            mode = cmd[1].lower()
+            self.raw_debug = mode == b"on"
+            self.logger.info(
+                "%sabling per interrupt debug logs.",
+                "En" if self.raw_debug else "Dis",
+            )
+
+        elif cmd[0] == b"interrogate" and len(cmd) >= 2:
+            enhanced = False
+            mode = cmd[1]
+            if len(cmd) >= 3 and cmd[2] == b"enhanced":
+                enhanced = True
+
+            # Set the mode if correct.
+            if mode in INTERROGATION_MODES:
+                self.interrogation_mode = mode
+                self.logger.debug("Updated interrogation mode to %s.", mode)
+
+                # Update the assumptions of the EC image.
+                self.enhanced_ec = enhanced
+                self.logger.debug(
+                    "Enhanced EC image is now %r", self.enhanced_ec
+                )
+
+                # Send command to interpreter as well.
+                self.cmd_pipe.send(
+                    b"enhanced " + str(self.enhanced_ec).encode("ascii")
+                )
+            else:
+                self.PrintOOBMHelp()
+
+        else:
+            self.PrintOOBMHelp()
+
+    def PrintOOBMHelp(self):
+        """Prints out the OOBM help."""
+        # Print help syntax.
+        os.write(self.controller_pty, b"\r\n" + b"Known OOBM commands:\r\n")
+        os.write(
+            self.controller_pty,
+            b"  interrogate <never | always | auto> " b"[enhanced]\r\n",
+        )
+        os.write(self.controller_pty, b"  loglevel <int>\r\n")
+
+    def CheckBufferForEnhancedImage(self, data):
+        """Adds data to a look buffer and checks to see for enhanced EC image.
+
+        The EC's console task prints a string upon initialization which says that
+        "Console is enabled; type HELP for help.".  The enhanced EC images print a
+        different string as a part of their init.  This function searches through a
+        "look" buffer, scanning for the presence of either of those strings and
+        updating the enhanced_ec state accordingly.
+
+        Args:
+          data: A string containing the data sent from the interpreter.
+        """
+        self.look_buffer += data
+
+        # Search the buffer for any of the EC image strings.
+        enhanced_match = re.search(ENHANCED_IMAGE_RE, self.look_buffer)
+        non_enhanced_match = re.search(NON_ENHANCED_IMAGE_RE, self.look_buffer)
+
+        # Update the state if any matches were found.
+        if enhanced_match or non_enhanced_match:
+            if enhanced_match:
+                self.enhanced_ec = True
+            elif non_enhanced_match:
+                self.enhanced_ec = False
+
+            # Inform the interpreter of the result.
+            self.cmd_pipe.send(
+                b"enhanced " + str(self.enhanced_ec).encode("ascii")
+            )
+            self.logger.debug("Enhanced EC image? %r", self.enhanced_ec)
+
+            # Clear look buffer since a match was found.
+            self.look_buffer = b""
+
+        # Move the sliding window.
+        self.look_buffer = self.look_buffer[-LOOK_BUFFER_SIZE:]
 
-    else:
-      self.logger.error('Unexpected sequence. %c', byte)
-      self.esc_state = 0
-
-  def ProcessInput(self):
-    """Captures the input determines what actions to take."""
-    # There's nothing to do if the input buffer is empty.
-    if len(self.input_buffer) == 0:
-      return
-
-    # Don't store 2 consecutive identical commands in the history.
-    if (self.history and self.history[-1] != self.input_buffer
-        or not self.history):
-      self.history.append(self.input_buffer)
-
-    # Split the command up by spaces.
-    line = self.input_buffer.split(b' ')
-    self.logger.debug('cmd: %s', self.input_buffer)
-    cmd = line[0].lower()
-
-    # The 'history' command is a special case that we handle locally.
-    if cmd == 'history':
-      self.PrintHistory()
-      return
-
-    # Send the command to the interpreter.
-    self.logger.debug('Sending command to interpreter.')
-    self.cmd_pipe.send(self.input_buffer)
 
-  def CheckForEnhancedECImage(self):
-    """Performs an interrogation of the EC image.
+def CanonicalizeTimeString(timestr):
+    """Canonicalize the timestamp string.
 
-    Send a SYN and expect an ACK.  If no ACK or the response is incorrect, then
-    assume that the current EC image that we are talking to is not enhanced.
+    Args:
+      timestr: A timestamp string ended with 6 digits msec.
 
     Returns:
-      is_enhanced: A boolean indicating whether the EC responded to the
-        interrogation correctly.
-
-    Raises:
-      EOFError: Allowed to propagate through from self.dbg_pipe.recv().
+      A string with 3 digits msec and an extra space.
     """
-    # Send interrogation byte and wait for the response.
-    self.logger.debug('Performing interrogation.')
-    self.cmd_pipe.send(interpreter.EC_SYN)
-
-    response = ''
-    if self.dbg_pipe.poll(self.interrogation_timeout):
-      response = self.dbg_pipe.recv()
-      self.logger.debug('response: %r', binascii.hexlify(response))
-    else:
-      self.logger.debug('Timed out waiting for EC_ACK')
+    return timestr[:-3].encode("ascii") + b" "
 
-    # Verify the acknowledgment.
-    is_enhanced = response == interpreter.EC_ACK
-
-    if is_enhanced:
-      # Increase the interrogation timeout for stability purposes.
-      self.interrogation_timeout = ENHANCED_EC_INTERROGATION_TIMEOUT
-      self.logger.debug('Increasing interrogation timeout to %rs.',
-                        self.interrogation_timeout)
-    else:
-      # Reduce the timeout in order to reduce the perceivable delay.
-      self.interrogation_timeout = NON_ENHANCED_EC_INTERROGATION_TIMEOUT
-      self.logger.debug('Reducing interrogation timeout to %rs.',
-                        self.interrogation_timeout)
-
-    return is_enhanced
-
-  def HandleChar(self, byte):
-    """HandleChar does a certain action when it receives a character.
-
-    Args:
-      byte: An integer representing the character received from the user.
 
-    Raises:
-      EOFError: Allowed to propagate through from self.CheckForEnhancedECImage()
-          i.e. from self.dbg_pipe.recv().
-    """
-    fd = self.controller_pty
-
-    # Enter the OOBM prompt mode if the user presses '%'.
-    if byte == ord('%'):
-      self.logger.debug('Begin OOBM command.')
-      self.receiving_oobm_cmd = True
-      # Print a "prompt".
-      os.write(self.controller_pty, b'\r\n% ')
-      return
-
-    # Add chars to the pending OOBM command if we're currently receiving one.
-    if self.receiving_oobm_cmd and byte != ControlKey.CARRIAGE_RETURN:
-      tmp_bytes = six.int2byte(byte)
-      self.pending_oobm_cmd += tmp_bytes
-      self.logger.debug('%s', tmp_bytes)
-      os.write(self.controller_pty, tmp_bytes)
-      return
-
-    if byte == ControlKey.CARRIAGE_RETURN:
-      if self.receiving_oobm_cmd:
-        # Terminate the command and place it in the OOBM queue.
-        self.logger.debug('End OOBM command.')
-        if self.pending_oobm_cmd:
-          self.oobm_queue.put(self.pending_oobm_cmd)
-          self.logger.debug('Placed %r into OOBM command queue.',
-                            self.pending_oobm_cmd)
-
-        # Reset the state.
-        os.write(self.controller_pty, b'\r\n' + self.prompt)
-        self.input_buffer = b''
-        self.input_buffer_pos = 0
-        self.receiving_oobm_cmd = False
-        self.pending_oobm_cmd = b''
-        return
-
-      if self.interrogation_mode == b'never':
-        self.logger.debug('Skipping interrogation because interrogation mode'
-                          ' is set to never.')
-      elif self.interrogation_mode == b'always':
-        # Only interrogate the EC if the interrogation mode is set to 'always'.
-        self.enhanced_ec = self.CheckForEnhancedECImage()
-        self.logger.debug('Enhanced EC image? %r', self.enhanced_ec)
-
-    if not self.enhanced_ec:
-      # Send everything straight to the EC to handle.
-      self.cmd_pipe.send(six.int2byte(byte))
-      # Reset the input buffer.
-      self.input_buffer = b''
-      self.input_buffer_pos = 0
-      self.logger.log(1, 'Reset input buffer.')
-      return
-
-    # Keep handling the ESC sequence if we're in the middle of it.
-    if self.esc_state != 0:
-      self.HandleEsc(byte)
-      return
-
-    # When we're at the end of the line, we should only allow going backwards,
-    # backspace, carriage return, up, or down.  The arrow keys are escape
-    # sequences, so we let the escape...escape.
-    if (self.input_buffer_pos >= self.line_limit and
-        byte not in [ControlKey.CTRL_B, ControlKey.ESC, ControlKey.BACKSPACE,
-                     ControlKey.CTRL_A, ControlKey.CARRIAGE_RETURN,
-                     ControlKey.CTRL_P, ControlKey.CTRL_N]):
-      return
-
-    # If the input buffer is full we can't accept new chars.
-    buffer_full = len(self.input_buffer) >= self.line_limit
-
-
-    # Carriage_Return/Enter
-    if byte == ControlKey.CARRIAGE_RETURN:
-      self.logger.debug('Enter key pressed.')
-      # Put a carriage return/newline and the print the prompt.
-      os.write(fd, b'\r\n')
-
-      # TODO(aaboagye): When we control the printing of all output, print the
-      # prompt AFTER printing all the output.  We can't do it yet because we
-      # don't know how much is coming from the EC.
-
-      # Print the prompt.
-      os.write(fd, self.prompt)
-      # Process the input.
-      self.ProcessInput()
-      # Now, clear the buffer.
-      self.input_buffer = b''
-      self.input_buffer_pos = 0
-      # Reset history buffer pos.
-      self.history_pos = len(self.history)
-      # Clear partial command.
-      self.partial_cmd = b''
-
-    # Backspace
-    elif byte == ControlKey.BACKSPACE:
-      self.logger.debug('Backspace pressed.')
-      if self.input_buffer_pos > 0:
-        # Move left 1 column.
-        self.MoveCursor('left', 1)
-        # Remove the character at the input_buffer_pos by slicing it out.
-        self.SliceOutChar()
-
-      self.logger.debug('input_buffer_pos: %d', self.input_buffer_pos)
-
-    # Ctrl+A. Move cursor to beginning of the line
-    elif byte == ControlKey.CTRL_A:
-      self.logger.debug('Control+A pressed.')
-      self.MoveCursor('left', self.input_buffer_pos)
-
-    # Ctrl+B. Move cursor left 1 column.
-    elif byte == ControlKey.CTRL_B:
-      self.logger.debug('Control+B pressed.')
-      self.MoveCursor('left', 1)
-
-    # Ctrl+D. Delete a character.
-    elif byte == ControlKey.CTRL_D:
-      self.logger.debug('Control+D pressed.')
-      if self.input_buffer_pos != len(self.input_buffer):
-        # Remove the character by slicing it out.
-        self.SliceOutChar()
-
-    # Ctrl+E. Move cursor to end of the line.
-    elif byte == ControlKey.CTRL_E:
-      self.logger.debug('Control+E pressed.')
-      self.MoveCursor('right',
-                      len(self.input_buffer) - self.input_buffer_pos)
-
-    # Ctrl+F. Move cursor right 1 column.
-    elif byte == ControlKey.CTRL_F:
-      self.logger.debug('Control+F pressed.')
-      self.MoveCursor('right', 1)
-
-    # Ctrl+K. Kill line.
-    elif byte == ControlKey.CTRL_K:
-      self.logger.debug('Control+K pressed.')
-      self.KillLine()
-
-    # Ctrl+N. Next line.
-    elif byte == ControlKey.CTRL_N:
-      self.logger.debug('Control+N pressed.')
-      self.ShowNextCommand()
-
-    # Ctrl+P. Previous line.
-    elif byte == ControlKey.CTRL_P:
-      self.logger.debug('Control+P pressed.')
-      self.ShowPreviousCommand()
-
-    # ESC sequence
-    elif byte == ControlKey.ESC:
-      # Starting an ESC sequence
-      self.esc_state = EscState.ESC_START
-
-    # Only print printable chars.
-    elif IsPrintable(byte):
-      # Drop the character if we're full.
-      if buffer_full:
-        self.logger.debug('Dropped char: %c(%d)', byte, byte)
-        return
-      # Print the character.
-      os.write(fd, six.int2byte(byte))
-      # Print the rest of the line (if any).
-      extra_bytes_written = os.write(fd,
-                                     self.input_buffer[self.input_buffer_pos:])
-
-      # Recreate the input buffer.
-      self.input_buffer = (self.input_buffer[0:self.input_buffer_pos] +
-                           six.int2byte(byte) +
-                           self.input_buffer[self.input_buffer_pos:])
-      # Update the input buffer position.
-      self.input_buffer_pos += 1 + extra_bytes_written
-
-      # Reset the cursor if we wrote any extra bytes.
-      if extra_bytes_written:
-        self.MoveCursor('left', extra_bytes_written)
-
-      self.logger.debug('input_buffer_pos: %d', self.input_buffer_pos)
-
-  def MoveCursor(self, direction, count):
-    """MoveCursor moves the cursor left or right by count columns.
+def IsPrintable(byte):
+    """Determines if a byte is printable.
 
     Args:
-      direction: A string that should be either 'left' or 'right' representing
-        the direction to move the cursor on the console.
-      count: An integer representing how many columns the cursor should be
-        moved.
+      byte: An integer potentially representing a printable character.
 
-    Raises:
-      AssertionError: If the direction is not equal to 'left' or 'right'.
+    Returns:
+      A boolean indicating whether the byte is a printable character.
     """
-    # If there's nothing to move, we're done.
-    if not count:
-      return
-    fd = self.controller_pty
-    seq = b'\033[' + str(count).encode('ascii')
-    if direction == 'left':
-      # Bind the movement.
-      if count > self.input_buffer_pos:
-        count = self.input_buffer_pos
-      seq += b'D'
-      self.logger.debug('move cursor left %d', count)
-      self.input_buffer_pos -= count
-
-    elif direction == 'right':
-      # Bind the movement.
-      if (count + self.input_buffer_pos) > len(self.input_buffer):
-        count = 0
-      seq += b'C'
-      self.logger.debug('move cursor right %d', count)
-      self.input_buffer_pos += count
-
-    else:
-      raise AssertionError(('The only valid directions are \'left\' and '
-                            '\'right\''))
-
-    self.logger.debug('input_buffer_pos: %d', self.input_buffer_pos)
-    # Move the cursor.
-    if count != 0:
-      os.write(fd, seq)
-
-  def KillLine(self):
-    """Kill the rest of the line based on the input buffer position."""
-    # Killing the line is killing all the text to the right.
-    diff = len(self.input_buffer) - self.input_buffer_pos
-    self.logger.debug('diff: %d', diff)
-    # Diff shouldn't be negative, but if it is for some reason, let's try to
-    # correct the cursor.
-    if diff < 0:
-      self.logger.warning('Resetting input buffer position to %d...',
-                          len(self.input_buffer))
-      self.MoveCursor('left', -diff)
-      return
-    if diff:
-      self.MoveCursor('right', diff)
-      for _ in range(diff):
-        self.SendBackspace()
-      self.input_buffer_pos -= diff
-      self.input_buffer = self.input_buffer[0:self.input_buffer_pos]
-
-  def SendBackspace(self):
-    """Backspace a character on the console."""
-    os.write(self.controller_pty, b'\033[1D \033[1D')
-
-  def ProcessOOBMQueue(self):
-    """Retrieve an item from the OOBM queue and process it."""
-    item = self.oobm_queue.get()
-    self.logger.debug('OOBM cmd: %r', item)
-    cmd = item.split(b' ')
-
-    if cmd[0] == b'loglevel':
-      # An integer is required in order to set the log level.
-      if len(cmd) < 2:
-        self.logger.debug('Insufficient args')
-        self.PrintOOBMHelp()
-        return
-      try:
-        self.logger.debug('Log level change request.')
-        new_log_level = int(cmd[1])
-        self.logger.logger.setLevel(new_log_level)
-        self.logger.info('Log level changed to %d.', new_log_level)
-
-        # Forward the request to the interpreter as well.
-        self.cmd_pipe.send(item)
-      except ValueError:
-        # Ignoring the request if an integer was not provided.
-        self.PrintOOBMHelp()
-
-    elif cmd[0] == b'timestamp':
-      mode = cmd[1].lower()
-      self.timestamp_enabled = (mode == b'on')
-      self.logger.info('%sabling uart timestamps.',
-                       'En' if self.timestamp_enabled else 'Dis')
-
-    elif cmd[0] == b'rawdebug':
-      mode = cmd[1].lower()
-      self.raw_debug = (mode == b'on')
-      self.logger.info('%sabling per interrupt debug logs.',
-                       'En' if self.raw_debug else 'Dis')
-
-    elif cmd[0] == b'interrogate' and len(cmd) >= 2:
-      enhanced = False
-      mode = cmd[1]
-      if len(cmd) >= 3 and cmd[2] == b'enhanced':
-        enhanced = True
-
-      # Set the mode if correct.
-      if mode in INTERROGATION_MODES:
-        self.interrogation_mode = mode
-        self.logger.debug('Updated interrogation mode to %s.', mode)
-
-        # Update the assumptions of the EC image.
-        self.enhanced_ec = enhanced
-        self.logger.debug('Enhanced EC image is now %r', self.enhanced_ec)
-
-        # Send command to interpreter as well.
-        self.cmd_pipe.send(b'enhanced ' + str(self.enhanced_ec).encode('ascii'))
-      else:
-        self.PrintOOBMHelp()
-
-    else:
-      self.PrintOOBMHelp()
+    return byte >= ord(" ") and byte <= ord("~")
 
-  def PrintOOBMHelp(self):
-    """Prints out the OOBM help."""
-    # Print help syntax.
-    os.write(self.controller_pty, b'\r\n' + b'Known OOBM commands:\r\n')
-    os.write(self.controller_pty, b'  interrogate <never | always | auto> '
-             b'[enhanced]\r\n')
-    os.write(self.controller_pty, b'  loglevel <int>\r\n')
 
-  def CheckBufferForEnhancedImage(self, data):
-    """Adds data to a look buffer and checks to see for enhanced EC image.
-
-    The EC's console task prints a string upon initialization which says that
-    "Console is enabled; type HELP for help.".  The enhanced EC images print a
-    different string as a part of their init.  This function searches through a
-    "look" buffer, scanning for the presence of either of those strings and
-    updating the enhanced_ec state accordingly.
+def StartLoop(console, command_active, shutdown_pipe=None):
+    """Starts the infinite loop of console processing.
 
     Args:
-      data: A string containing the data sent from the interpreter.
+      console: A Console object that has been properly initialzed.
+      command_active: ctypes data object or multiprocessing.Value indicating if
+        servod owns the console, or user owns the console. This prevents input
+        collisions.
+      shutdown_pipe: A file object for a pipe or equivalent that becomes readable
+        (not blocked) to indicate that the loop should exit.  Can be None to never
+        exit the loop.
     """
-    self.look_buffer += data
-
-    # Search the buffer for any of the EC image strings.
-    enhanced_match = re.search(ENHANCED_IMAGE_RE, self.look_buffer)
-    non_enhanced_match = re.search(NON_ENHANCED_IMAGE_RE, self.look_buffer)
-
-    # Update the state if any matches were found.
-    if enhanced_match or non_enhanced_match:
-      if enhanced_match:
-        self.enhanced_ec = True
-      elif non_enhanced_match:
-        self.enhanced_ec = False
-
-      # Inform the interpreter of the result.
-      self.cmd_pipe.send(b'enhanced ' + str(self.enhanced_ec).encode('ascii'))
-      self.logger.debug('Enhanced EC image? %r', self.enhanced_ec)
-
-      # Clear look buffer since a match was found.
-      self.look_buffer = b''
-
-    # Move the sliding window.
-    self.look_buffer = self.look_buffer[-LOOK_BUFFER_SIZE:]
-
-
-def CanonicalizeTimeString(timestr):
-  """Canonicalize the timestamp string.
-
-  Args:
-    timestr: A timestamp string ended with 6 digits msec.
-
-  Returns:
-    A string with 3 digits msec and an extra space.
-  """
-  return timestr[:-3].encode('ascii') + b' '
-
-
-def IsPrintable(byte):
-  """Determines if a byte is printable.
-
-  Args:
-    byte: An integer potentially representing a printable character.
-
-  Returns:
-    A boolean indicating whether the byte is a printable character.
-  """
-  return byte >= ord(' ') and byte <= ord('~')
-
-
-def StartLoop(console, command_active, shutdown_pipe=None):
-  """Starts the infinite loop of console processing.
-
-  Args:
-    console: A Console object that has been properly initialzed.
-    command_active: ctypes data object or multiprocessing.Value indicating if
-      servod owns the console, or user owns the console. This prevents input
-      collisions.
-    shutdown_pipe: A file object for a pipe or equivalent that becomes readable
-      (not blocked) to indicate that the loop should exit.  Can be None to never
-      exit the loop.
-  """
-  try:
-    console.logger.debug('Console is being served on %s.', console.user_pty)
-    console.logger.debug('Console controller is on %s.', console.controller_pty)
-    console.logger.debug('Command interface is being served on %s.',
-        console.interface_pty)
-    console.logger.debug(console)
-
-    # This checks for HUP to indicate if the user has connected to the pty.
-    ep = select.epoll()
-    ep.register(console.controller_pty, select.EPOLLHUP)
-
-    # This is used instead of "break" to avoid exiting the loop in the middle of
-    # an iteration.
-    continue_looping = True
-
-    # Used for determining when to print host timestamps
-    tm_req = True
-
-    while continue_looping:
-      # Check to see if pts is connected to anything
-      events = ep.poll(0)
-      controller_connected = not events
-
-      # Check to see if pipes or the console are ready for reading.
-      read_list = [console.interface_pty,
-                   console.cmd_pipe, console.dbg_pipe]
-      if controller_connected:
-        read_list.append(console.controller_pty)
-      if shutdown_pipe is not None:
-        read_list.append(shutdown_pipe)
-
-      # Check if any input is ready, or wait for .1 sec and re-poll if
-      # a user has connected to the pts.
-      select_output = select.select(read_list, [], [], .1)
-      if not select_output:
-        continue
-      ready_for_reading = select_output[0]
-
-      for obj in ready_for_reading:
-        if obj is console.controller_pty:
-          if not command_active.value:
-            # Convert to bytes so we can look for non-printable chars such as
-            # Ctrl+A, Ctrl+E, etc.
-            try:
-              line = bytearray(os.read(console.controller_pty, CONSOLE_MAX_READ))
-              console.logger.debug('Input from user: %s, locked:%s',
-                  str(line).strip(), command_active.value)
-              for i in line:
-                try:
-                  # Handle each character as it arrives.
-                  console.HandleChar(i)
-                except EOFError:
-                  console.logger.debug(
-                      'ec3po console received EOF from dbg_pipe in HandleChar()'
-                      ' while reading console.controller_pty')
-                  continue_looping = False
-                  break
-            except OSError:
-              console.logger.debug('Ptm read failed, probably user disconnect.')
-
-        elif obj is console.interface_pty:
-          if command_active.value:
-            # Convert to bytes so we can look for non-printable chars such as
-            # Ctrl+A, Ctrl+E, etc.
-            line = bytearray(os.read(console.interface_pty, CONSOLE_MAX_READ))
-            console.logger.debug('Input from interface: %s, locked:%s',
-                str(line).strip(), command_active.value)
-            for i in line:
-              try:
-                # Handle each character as it arrives.
-                console.HandleChar(i)
-              except EOFError:
-                console.logger.debug(
-                    'ec3po console received EOF from dbg_pipe in HandleChar()'
-                    ' while reading console.interface_pty')
-                continue_looping = False
-                break
-
-        elif obj is console.cmd_pipe:
-          try:
-            data = console.cmd_pipe.recv()
-          except EOFError:
-            console.logger.debug('ec3po console received EOF from cmd_pipe')
-            continue_looping = False
-          else:
-            # Write it to the user console.
-            if console.raw_debug:
-              console.logger.debug('|CMD|-%s->%r',
-                                   ('u' if controller_connected else '') +
-                                   ('i' if command_active.value else ''),
-                                   data.strip())
+    try:
+        console.logger.debug("Console is being served on %s.", console.user_pty)
+        console.logger.debug(
+            "Console controller is on %s.", console.controller_pty
+        )
+        console.logger.debug(
+            "Command interface is being served on %s.", console.interface_pty
+        )
+        console.logger.debug(console)
+
+        # This checks for HUP to indicate if the user has connected to the pty.
+        ep = select.epoll()
+        ep.register(console.controller_pty, select.EPOLLHUP)
+
+        # This is used instead of "break" to avoid exiting the loop in the middle of
+        # an iteration.
+        continue_looping = True
+
+        # Used for determining when to print host timestamps
+        tm_req = True
+
+        while continue_looping:
+            # Check to see if pts is connected to anything
+            events = ep.poll(0)
+            controller_connected = not events
+
+            # Check to see if pipes or the console are ready for reading.
+            read_list = [
+                console.interface_pty,
+                console.cmd_pipe,
+                console.dbg_pipe,
+            ]
             if controller_connected:
-              os.write(console.controller_pty, data)
-            if command_active.value:
-              os.write(console.interface_pty, data)
-
-        elif obj is console.dbg_pipe:
-          try:
-            data = console.dbg_pipe.recv()
-          except EOFError:
-            console.logger.debug('ec3po console received EOF from dbg_pipe')
-            continue_looping = False
-          else:
-            if console.interrogation_mode == b'auto':
-              # Search look buffer for enhanced EC image string.
-              console.CheckBufferForEnhancedImage(data)
-            # Write it to the user console.
-            if len(data) > 1 and console.raw_debug:
-              console.logger.debug('|DBG|-%s->%r',
-                                   ('u' if controller_connected else '') +
-                                   ('i' if command_active.value else ''),
-                                   data.strip())
-            console.LogConsoleOutput(data)
-            if controller_connected:
-              end = len(data) - 1
-              if console.timestamp_enabled:
-                # A timestamp is required at the beginning of this line
-                if tm_req is True:
-                  now = datetime.now()
-                  tm = CanonicalizeTimeString(now.strftime(HOST_STRFTIME))
-                  os.write(console.controller_pty, tm)
-                  tm_req = False
-
-                # Insert timestamps into the middle where appropriate
-                # except if the last character is a newline
-                nls_found = data.count(b'\n', 0, end)
-                now = datetime.now()
-                tm = CanonicalizeTimeString(now.strftime('\n' + HOST_STRFTIME))
-                data_tm = data.replace(b'\n', tm, nls_found)
-              else:
-                data_tm = data
-
-              # timestamp required on next input
-              if data[end] == b'\n'[0]:
-                tm_req = True
-              os.write(console.controller_pty, data_tm)
-            if command_active.value:
-              os.write(console.interface_pty, data)
-
-        elif obj is shutdown_pipe:
-          console.logger.debug(
-              'ec3po console received shutdown pipe unblocked notification')
-          continue_looping = False
-
-      while not console.oobm_queue.empty():
-        console.logger.debug('OOBM queue ready for reading.')
-        console.ProcessOOBMQueue()
-
-  except KeyboardInterrupt:
-    pass
-
-  finally:
-    ep.unregister(console.controller_pty)
-    console.dbg_pipe.close()
-    console.cmd_pipe.close()
-    os.close(console.controller_pty)
-    os.close(console.interface_pty)
-    if shutdown_pipe is not None:
-      shutdown_pipe.close()
-    console.logger.debug('Exit ec3po console loop for %s', console.user_pty)
+                read_list.append(console.controller_pty)
+            if shutdown_pipe is not None:
+                read_list.append(shutdown_pipe)
+
+            # Check if any input is ready, or wait for .1 sec and re-poll if
+            # a user has connected to the pts.
+            select_output = select.select(read_list, [], [], 0.1)
+            if not select_output:
+                continue
+            ready_for_reading = select_output[0]
+
+            for obj in ready_for_reading:
+                if obj is console.controller_pty:
+                    if not command_active.value:
+                        # Convert to bytes so we can look for non-printable chars such as
+                        # Ctrl+A, Ctrl+E, etc.
+                        try:
+                            line = bytearray(
+                                os.read(
+                                    console.controller_pty, CONSOLE_MAX_READ
+                                )
+                            )
+                            console.logger.debug(
+                                "Input from user: %s, locked:%s",
+                                str(line).strip(),
+                                command_active.value,
+                            )
+                            for i in line:
+                                try:
+                                    # Handle each character as it arrives.
+                                    console.HandleChar(i)
+                                except EOFError:
+                                    console.logger.debug(
+                                        "ec3po console received EOF from dbg_pipe in HandleChar()"
+                                        " while reading console.controller_pty"
+                                    )
+                                    continue_looping = False
+                                    break
+                        except OSError:
+                            console.logger.debug(
+                                "Ptm read failed, probably user disconnect."
+                            )
+
+                elif obj is console.interface_pty:
+                    if command_active.value:
+                        # Convert to bytes so we can look for non-printable chars such as
+                        # Ctrl+A, Ctrl+E, etc.
+                        line = bytearray(
+                            os.read(console.interface_pty, CONSOLE_MAX_READ)
+                        )
+                        console.logger.debug(
+                            "Input from interface: %s, locked:%s",
+                            str(line).strip(),
+                            command_active.value,
+                        )
+                        for i in line:
+                            try:
+                                # Handle each character as it arrives.
+                                console.HandleChar(i)
+                            except EOFError:
+                                console.logger.debug(
+                                    "ec3po console received EOF from dbg_pipe in HandleChar()"
+                                    " while reading console.interface_pty"
+                                )
+                                continue_looping = False
+                                break
+
+                elif obj is console.cmd_pipe:
+                    try:
+                        data = console.cmd_pipe.recv()
+                    except EOFError:
+                        console.logger.debug(
+                            "ec3po console received EOF from cmd_pipe"
+                        )
+                        continue_looping = False
+                    else:
+                        # Write it to the user console.
+                        if console.raw_debug:
+                            console.logger.debug(
+                                "|CMD|-%s->%r",
+                                ("u" if controller_connected else "")
+                                + ("i" if command_active.value else ""),
+                                data.strip(),
+                            )
+                        if controller_connected:
+                            os.write(console.controller_pty, data)
+                        if command_active.value:
+                            os.write(console.interface_pty, data)
+
+                elif obj is console.dbg_pipe:
+                    try:
+                        data = console.dbg_pipe.recv()
+                    except EOFError:
+                        console.logger.debug(
+                            "ec3po console received EOF from dbg_pipe"
+                        )
+                        continue_looping = False
+                    else:
+                        if console.interrogation_mode == b"auto":
+                            # Search look buffer for enhanced EC image string.
+                            console.CheckBufferForEnhancedImage(data)
+                        # Write it to the user console.
+                        if len(data) > 1 and console.raw_debug:
+                            console.logger.debug(
+                                "|DBG|-%s->%r",
+                                ("u" if controller_connected else "")
+                                + ("i" if command_active.value else ""),
+                                data.strip(),
+                            )
+                        console.LogConsoleOutput(data)
+                        if controller_connected:
+                            end = len(data) - 1
+                            if console.timestamp_enabled:
+                                # A timestamp is required at the beginning of this line
+                                if tm_req is True:
+                                    now = datetime.now()
+                                    tm = CanonicalizeTimeString(
+                                        now.strftime(HOST_STRFTIME)
+                                    )
+                                    os.write(console.controller_pty, tm)
+                                    tm_req = False
+
+                                # Insert timestamps into the middle where appropriate
+                                # except if the last character is a newline
+                                nls_found = data.count(b"\n", 0, end)
+                                now = datetime.now()
+                                tm = CanonicalizeTimeString(
+                                    now.strftime("\n" + HOST_STRFTIME)
+                                )
+                                data_tm = data.replace(b"\n", tm, nls_found)
+                            else:
+                                data_tm = data
+
+                            # timestamp required on next input
+                            if data[end] == b"\n"[0]:
+                                tm_req = True
+                            os.write(console.controller_pty, data_tm)
+                        if command_active.value:
+                            os.write(console.interface_pty, data)
+
+                elif obj is shutdown_pipe:
+                    console.logger.debug(
+                        "ec3po console received shutdown pipe unblocked notification"
+                    )
+                    continue_looping = False
+
+            while not console.oobm_queue.empty():
+                console.logger.debug("OOBM queue ready for reading.")
+                console.ProcessOOBMQueue()
+
+    except KeyboardInterrupt:
+        pass
+
+    finally:
+        ep.unregister(console.controller_pty)
+        console.dbg_pipe.close()
+        console.cmd_pipe.close()
+        os.close(console.controller_pty)
+        os.close(console.interface_pty)
+        if shutdown_pipe is not None:
+            shutdown_pipe.close()
+        console.logger.debug("Exit ec3po console loop for %s", console.user_pty)
 
 
 def main(argv):
-  """Kicks off the EC-3PO interactive console interface and interpreter.
-
-  We create some pipes to communicate with an interpreter, instantiate an
-  interpreter, create a PTY pair, and begin serving the console interface.
-
-  Args:
-    argv: A list of strings containing the arguments this module was called
-      with.
-  """
-  # Set up argument parser.
-  parser = argparse.ArgumentParser(description=('Start interactive EC console '
-                                                'and interpreter.'))
-  parser.add_argument('ec_uart_pty',
-                      help=('The full PTY name that the EC UART'
-                            ' is present on. eg: /dev/pts/12'))
-  parser.add_argument('--log-level',
-                      default='info',
-                      help='info, debug, warning, error, or critical')
-
-  # Parse arguments.
-  opts = parser.parse_args(argv)
-
-  # Set logging level.
-  opts.log_level = opts.log_level.lower()
-  if opts.log_level == 'info':
-    log_level = logging.INFO
-  elif opts.log_level == 'debug':
-    log_level = logging.DEBUG
-  elif opts.log_level == 'warning':
-    log_level = logging.WARNING
-  elif opts.log_level == 'error':
-    log_level = logging.ERROR
-  elif opts.log_level == 'critical':
-    log_level = logging.CRITICAL
-  else:
-    parser.error('Invalid log level. (info, debug, warning, error, critical)')
-
-  # Start logging with a timestamp, module, and log level shown in each log
-  # entry.
-  logging.basicConfig(level=log_level, format=('%(asctime)s - %(module)s -'
-                                               ' %(levelname)s - %(message)s'))
-
-  # Create some pipes to communicate between the interpreter and the console.
-  # The command pipe is bidirectional.
-  cmd_pipe_interactive, cmd_pipe_interp = threadproc_shim.Pipe()
-  # The debug pipe is unidirectional from interpreter to console only.
-  dbg_pipe_interactive, dbg_pipe_interp = threadproc_shim.Pipe(duplex=False)
-
-  # Create an interpreter instance.
-  itpr = interpreter.Interpreter(opts.ec_uart_pty, cmd_pipe_interp,
-                                 dbg_pipe_interp, log_level)
-
-  # Spawn an interpreter process.
-  itpr_process = threadproc_shim.ThreadOrProcess(
-      target=interpreter.StartLoop, args=(itpr,))
-  # Make sure to kill the interpreter when we terminate.
-  itpr_process.daemon = True
-  # Start the interpreter.
-  itpr_process.start()
-
-  # Open a new pseudo-terminal pair
-  (controller_pty, user_pty) = pty.openpty()
-  # Set the permissions to 660.
-  os.chmod(os.ttyname(user_pty), (stat.S_IRGRP | stat.S_IWGRP |
-                                  stat.S_IRUSR | stat.S_IWUSR))
-  # Create a console.
-  console = Console(controller_pty, os.ttyname(user_pty), cmd_pipe_interactive,
-                    dbg_pipe_interactive)
-  # Start serving the console.
-  v = threadproc_shim.Value(ctypes.c_bool, False)
-  StartLoop(console, v)
-
-
-if __name__ == '__main__':
-  main(sys.argv[1:])
+    """Kicks off the EC-3PO interactive console interface and interpreter.
+
+    We create some pipes to communicate with an interpreter, instantiate an
+    interpreter, create a PTY pair, and begin serving the console interface.
+
+    Args:
+      argv: A list of strings containing the arguments this module was called
+        with.
+    """
+    # Set up argument parser.
+    parser = argparse.ArgumentParser(
+        description=("Start interactive EC console and interpreter.")
+    )
+    parser.add_argument(
+        "ec_uart_pty",
+        help=(
+            "The full PTY name that the EC UART is present on. eg: /dev/pts/12"
+        ),
+    )
+    parser.add_argument(
+        "--log-level",
+        default="info",
+        help="info, debug, warning, error, or critical",
+    )
+
+    # Parse arguments.
+    opts = parser.parse_args(argv)
+
+    # Set logging level.
+    opts.log_level = opts.log_level.lower()
+    if opts.log_level == "info":
+        log_level = logging.INFO
+    elif opts.log_level == "debug":
+        log_level = logging.DEBUG
+    elif opts.log_level == "warning":
+        log_level = logging.WARNING
+    elif opts.log_level == "error":
+        log_level = logging.ERROR
+    elif opts.log_level == "critical":
+        log_level = logging.CRITICAL
+    else:
+        parser.error(
+            "Invalid log level. (info, debug, warning, error, critical)"
+        )
+
+    # Start logging with a timestamp, module, and log level shown in each log
+    # entry.
+    logging.basicConfig(
+        level=log_level,
+        format=("%(asctime)s - %(module)s - %(levelname)s - %(message)s"),
+    )
+
+    # Create some pipes to communicate between the interpreter and the console.
+    # The command pipe is bidirectional.
+    cmd_pipe_interactive, cmd_pipe_interp = threadproc_shim.Pipe()
+    # The debug pipe is unidirectional from interpreter to console only.
+    dbg_pipe_interactive, dbg_pipe_interp = threadproc_shim.Pipe(duplex=False)
+
+    # Create an interpreter instance.
+    itpr = interpreter.Interpreter(
+        opts.ec_uart_pty, cmd_pipe_interp, dbg_pipe_interp, log_level
+    )
+
+    # Spawn an interpreter process.
+    itpr_process = threadproc_shim.ThreadOrProcess(
+        target=interpreter.StartLoop, args=(itpr,)
+    )
+    # Make sure to kill the interpreter when we terminate.
+    itpr_process.daemon = True
+    # Start the interpreter.
+    itpr_process.start()
+
+    # Open a new pseudo-terminal pair
+    (controller_pty, user_pty) = pty.openpty()
+    # Set the permissions to 660.
+    os.chmod(
+        os.ttyname(user_pty),
+        (stat.S_IRGRP | stat.S_IWGRP | stat.S_IRUSR | stat.S_IWUSR),
+    )
+    # Create a console.
+    console = Console(
+        controller_pty,
+        os.ttyname(user_pty),
+        os.ttyname(controller_pty),
+        cmd_pipe_interactive,
+        dbg_pipe_interactive,
+    )
+    # Start serving the console.
+    v = threadproc_shim.Value(ctypes.c_bool, False)
+    StartLoop(console, v)
+
+
+if __name__ == "__main__":
+    main(sys.argv[1:])
diff --git a/util/ec3po/console_unittest.py b/util/ec3po/console_unittest.py
index 7e341e7e8d..e2a3d588fd 100755
--- a/util/ec3po/console_unittest.py
+++ b/util/ec3po/console_unittest.py
@@ -1,5 +1,5 @@
 #!/usr/bin/env python
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -11,1262 +11,1317 @@ from __future__ import print_function
 
 import binascii
 import logging
-import mock
 import tempfile
 import unittest
 
+import mock  # pylint:disable=import-error
 import six
-
-from ec3po import console
-from ec3po import interpreter
-from ec3po import threadproc_shim
+from ec3po import console, interpreter, threadproc_shim
 
 ESC_STRING = six.int2byte(console.ControlKey.ESC)
 
+
 class Keys(object):
-  """A class that contains the escape sequences for special keys."""
-  LEFT_ARROW = [console.ControlKey.ESC, ord('['), ord('D')]
-  RIGHT_ARROW = [console.ControlKey.ESC, ord('['), ord('C')]
-  UP_ARROW = [console.ControlKey.ESC, ord('['), ord('A')]
-  DOWN_ARROW = [console.ControlKey.ESC, ord('['), ord('B')]
-  HOME = [console.ControlKey.ESC, ord('['), ord('1'), ord('~')]
-  END = [console.ControlKey.ESC, ord('['), ord('8'), ord('~')]
-  DEL = [console.ControlKey.ESC, ord('['), ord('3'), ord('~')]
+    """A class that contains the escape sequences for special keys."""
+
+    LEFT_ARROW = [console.ControlKey.ESC, ord("["), ord("D")]
+    RIGHT_ARROW = [console.ControlKey.ESC, ord("["), ord("C")]
+    UP_ARROW = [console.ControlKey.ESC, ord("["), ord("A")]
+    DOWN_ARROW = [console.ControlKey.ESC, ord("["), ord("B")]
+    HOME = [console.ControlKey.ESC, ord("["), ord("1"), ord("~")]
+    END = [console.ControlKey.ESC, ord("["), ord("8"), ord("~")]
+    DEL = [console.ControlKey.ESC, ord("["), ord("3"), ord("~")]
+
 
 class OutputStream(object):
-  """A class that has methods which return common console output."""
+    """A class that has methods which return common console output."""
 
-  @staticmethod
-  def MoveCursorLeft(count):
-    """Produces what would be printed to the console if the cursor moved left.
+    @staticmethod
+    def MoveCursorLeft(count):
+        """Produces what would be printed to the console if the cursor moved left.
 
-    Args:
-      count: An integer representing how many columns to move left.
+        Args:
+          count: An integer representing how many columns to move left.
 
-    Returns:
-      string: A string which contains what would be printed to the console if
-        the cursor moved left.
-    """
-    string = ESC_STRING
-    string += b'[' + str(count).encode('ascii') + b'D'
-    return string
+        Returns:
+          string: A string which contains what would be printed to the console if
+            the cursor moved left.
+        """
+        string = ESC_STRING
+        string += b"[" + str(count).encode("ascii") + b"D"
+        return string
 
-  @staticmethod
-  def MoveCursorRight(count):
-    """Produces what would be printed to the console if the cursor moved right.
+    @staticmethod
+    def MoveCursorRight(count):
+        """Produces what would be printed to the console if the cursor moved right.
 
-    Args:
-      count: An integer representing how many columns to move right.
+        Args:
+          count: An integer representing how many columns to move right.
+
+        Returns:
+          string: A string which contains what would be printed to the console if
+            the cursor moved right.
+        """
+        string = ESC_STRING
+        string += b"[" + str(count).encode("ascii") + b"C"
+        return string
 
-    Returns:
-      string: A string which contains what would be printed to the console if
-        the cursor moved right.
-    """
-    string = ESC_STRING
-    string += b'[' + str(count).encode('ascii') + b'C'
-    return string
 
-BACKSPACE_STRING = b''
+BACKSPACE_STRING = b""
 # Move cursor left 1 column.
 BACKSPACE_STRING += OutputStream.MoveCursorLeft(1)
 # Write a space.
-BACKSPACE_STRING += b' '
+BACKSPACE_STRING += b" "
 # Move cursor left 1 column.
 BACKSPACE_STRING += OutputStream.MoveCursorLeft(1)
 
-def BytesToByteList(string):
-  """Converts a bytes string to list of bytes.
-
-  Args:
-    string: A literal bytes to turn into a list of bytes.
-
-  Returns:
-    A list of integers representing the byte value of each character in the
-      string.
-  """
-  if six.PY3:
-    return [c for c in string]
-  return [ord(c) for c in string]
 
-def CheckConsoleOutput(test_case, exp_console_out):
-  """Verify what was sent out the console matches what we expect.
+def BytesToByteList(string):
+    """Converts a bytes string to list of bytes.
 
-  Args:
-    test_case: A unittest.TestCase object representing the current unit test.
-    exp_console_out: A string representing the console output stream.
-  """
-  # Read what was sent out the console.
-  test_case.tempfile.seek(0)
-  console_out = test_case.tempfile.read()
+    Args:
+      string: A literal bytes to turn into a list of bytes.
 
-  test_case.assertEqual(exp_console_out, console_out)
+    Returns:
+      A list of integers representing the byte value of each character in the
+        string.
+    """
+    if six.PY3:
+        return [c for c in string]
+    return [ord(c) for c in string]
 
-def CheckInputBuffer(test_case, exp_input_buffer):
-  """Verify that the input buffer contains what we expect.
-
-  Args:
-    test_case: A unittest.TestCase object representing the current unit test.
-    exp_input_buffer: A string containing the contents of the current input
-      buffer.
-  """
-  test_case.assertEqual(exp_input_buffer, test_case.console.input_buffer,
-                        (b'input buffer does not match expected.\n'
-                         b'expected: |' + exp_input_buffer + b'|\n'
-                         b'got:      |' + test_case.console.input_buffer +
-                         b'|\n' + str(test_case.console).encode('ascii')))
 
-def CheckInputBufferPosition(test_case, exp_pos):
-  """Verify the input buffer position.
+def CheckConsoleOutput(test_case, exp_console_out):
+    """Verify what was sent out the console matches what we expect.
 
-  Args:
-    test_case: A unittest.TestCase object representing the current unit test.
-    exp_pos: An integer representing the expected input buffer position.
-  """
-  test_case.assertEqual(exp_pos, test_case.console.input_buffer_pos,
-                        'input buffer position is incorrect.\ngot: ' +
-                        str(test_case.console.input_buffer_pos) + '\nexp: ' +
-                        str(exp_pos) + '\n' + str(test_case.console))
+    Args:
+      test_case: A unittest.TestCase object representing the current unit test.
+      exp_console_out: A string representing the console output stream.
+    """
+    # Read what was sent out the console.
+    test_case.tempfile.seek(0)
+    console_out = test_case.tempfile.read()
 
-def CheckHistoryBuffer(test_case, exp_history):
-  """Verify that the items in the history buffer are what we expect.
-
-  Args:
-    test_case: A unittest.TestCase object representing the current unit test.
-    exp_history: A list of strings representing the expected contents of the
-      history buffer.
-  """
-  # First, check to see if the length is what we expect.
-  test_case.assertEqual(len(exp_history), len(test_case.console.history),
-                        ('The number of items in the history is unexpected.\n'
-                         'exp: ' + str(len(exp_history)) + '\n'
-                         'got: ' + str(len(test_case.console.history)) + '\n'
-                         'internal state:\n' + str(test_case.console)))
-
-  # Next, check the actual contents of the history buffer.
-  for i in range(len(exp_history)):
-    test_case.assertEqual(exp_history[i], test_case.console.history[i],
-                          (b'history buffer contents are incorrect.\n'
-                           b'exp: ' + exp_history[i] + b'\n'
-                           b'got: ' + test_case.console.history[i] + b'\n'
-                           b'internal state:\n' +
-                           str(test_case.console).encode('ascii')))
+    test_case.assertEqual(exp_console_out, console_out)
 
 
-class TestConsoleEditingMethods(unittest.TestCase):
-  """Test case to verify all console editing methods."""
-
-  def setUp(self):
-    """Setup the test harness."""
-    # Setup logging with a timestamp, the module, and the log level.
-    logging.basicConfig(level=logging.DEBUG,
-                        format=('%(asctime)s - %(module)s -'
-                                ' %(levelname)s - %(message)s'))
-
-    # Create a temp file and set both the controller and peripheral PTYs to the
-    # file to create a loopback.
-    self.tempfile = tempfile.TemporaryFile()
-
-    # Create some mock pipes. These won't be used since we'll mock out sends
-    # to the interpreter.
-    mock_pipe_end_0, mock_pipe_end_1 = threadproc_shim.Pipe()
-    self.console = console.Console(self.tempfile.fileno(), self.tempfile,
-                                   tempfile.TemporaryFile(),
-                                   mock_pipe_end_0, mock_pipe_end_1, "EC")
-
-    # Console editing methods are only valid for enhanced EC images, therefore
-    # we have to assume that the "EC" we're talking to is enhanced.  By default,
-    # the console believes that the EC it's communicating with is NOT enhanced
-    # which is why we have to override it here.
-    self.console.enhanced_ec = True
-    self.console.CheckForEnhancedECImage = mock.MagicMock(return_value=True)
-
-  def test_EnteringChars(self):
-    """Verify that characters are echoed onto the console."""
-    test_str = b'abc'
-    input_stream = BytesToByteList(test_str)
-
-    # Send the characters in.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Check the input position.
-    exp_pos = len(test_str)
-    CheckInputBufferPosition(self, exp_pos)
-
-    # Verify that the input buffer is correct.
-    expected_buffer = test_str
-    CheckInputBuffer(self, expected_buffer)
-
-    # Check console output
-    exp_console_out = test_str
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_EnteringDeletingMoreCharsThanEntered(self):
-    """Verify that we can press backspace more than we have entered chars."""
-    test_str = b'spamspam'
-    input_stream = BytesToByteList(test_str)
-
-    # Send the characters in.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Now backspace 1 more than what we sent.
-    input_stream = []
-    for _ in range(len(test_str) + 1):
-      input_stream.append(console.ControlKey.BACKSPACE)
-
-    # Send that sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # First, verify that input buffer position is 0.
-    CheckInputBufferPosition(self, 0)
-
-    # Next, examine the output stream for the correct sequence.
-    exp_console_out = test_str
-    for _ in range(len(test_str)):
-      exp_console_out += BACKSPACE_STRING
-
-    # Now, verify that we got what we expected.
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_EnteringMoreThanCharLimit(self):
-    """Verify that we drop characters when the line is too long."""
-    test_str = self.console.line_limit * b'o' # All allowed.
-    test_str += 5 * b'x' # All should be dropped.
-    input_stream = BytesToByteList(test_str)
-
-    # Send the characters in.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # First, we expect that input buffer position should be equal to the line
-    # limit.
-    exp_pos = self.console.line_limit
-    CheckInputBufferPosition(self, exp_pos)
-
-    # The input buffer should only hold until the line limit.
-    exp_buffer = test_str[0:self.console.line_limit]
-    CheckInputBuffer(self, exp_buffer)
-
-    # Lastly, check that the extra characters are not printed.
-    exp_console_out = exp_buffer
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_ValidKeysOnLongLine(self):
-    """Verify that we can still press valid keys if the line is too long."""
-    # Fill the line.
-    test_str = self.console.line_limit * b'o'
-    exp_console_out = test_str
-    # Try to fill it even more; these should all be dropped.
-    test_str += 5 * b'x'
-    input_stream = BytesToByteList(test_str)
-
-    # We should be able to press the following keys:
-    # - Backspace
-    # - Arrow Keys/CTRL+B/CTRL+F/CTRL+P/CTRL+N
-    # - Delete
-    # - Home/CTRL+A
-    # - End/CTRL+E
-    # - Carriage Return
-
-    # Backspace 1 character
-    input_stream.append(console.ControlKey.BACKSPACE)
-    exp_console_out += BACKSPACE_STRING
-    # Refill the line.
-    input_stream.extend(BytesToByteList(b'o'))
-    exp_console_out += b'o'
-
-    # Left arrow key.
-    input_stream.extend(Keys.LEFT_ARROW)
-    exp_console_out += OutputStream.MoveCursorLeft(1)
-
-    # Right arrow key.
-    input_stream.extend(Keys.RIGHT_ARROW)
-    exp_console_out += OutputStream.MoveCursorRight(1)
-
-    # CTRL+B
-    input_stream.append(console.ControlKey.CTRL_B)
-    exp_console_out += OutputStream.MoveCursorLeft(1)
-
-    # CTRL+F
-    input_stream.append(console.ControlKey.CTRL_F)
-    exp_console_out += OutputStream.MoveCursorRight(1)
-
-    # Let's press enter now so we can test up and down.
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-    exp_console_out += b'\r\n' + self.console.prompt
-
-    # Up arrow key.
-    input_stream.extend(Keys.UP_ARROW)
-    exp_console_out += test_str[:self.console.line_limit]
-
-    # Down arrow key.
-    input_stream.extend(Keys.DOWN_ARROW)
-    # Since the line was blank, we have to backspace the entire line.
-    exp_console_out += self.console.line_limit * BACKSPACE_STRING
-
-    # CTRL+P
-    input_stream.append(console.ControlKey.CTRL_P)
-    exp_console_out += test_str[:self.console.line_limit]
-
-    # CTRL+N
-    input_stream.append(console.ControlKey.CTRL_N)
-    # Since the line was blank, we have to backspace the entire line.
-    exp_console_out += self.console.line_limit * BACKSPACE_STRING
-
-    # Press the Up arrow key to reprint the long line.
-    input_stream.extend(Keys.UP_ARROW)
-    exp_console_out += test_str[:self.console.line_limit]
-
-    # Press the Home key to jump to the beginning of the line.
-    input_stream.extend(Keys.HOME)
-    exp_console_out += OutputStream.MoveCursorLeft(self.console.line_limit)
-
-    # Press the End key to jump to the end of the line.
-    input_stream.extend(Keys.END)
-    exp_console_out += OutputStream.MoveCursorRight(self.console.line_limit)
-
-    # Press CTRL+A to jump to the beginning of the line.
-    input_stream.append(console.ControlKey.CTRL_A)
-    exp_console_out += OutputStream.MoveCursorLeft(self.console.line_limit)
-
-    # Press CTRL+E to jump to the end of the line.
-    input_stream.extend(Keys.END)
-    exp_console_out += OutputStream.MoveCursorRight(self.console.line_limit)
-
-    # Move left one column so we can delete a character.
-    input_stream.extend(Keys.LEFT_ARROW)
-    exp_console_out += OutputStream.MoveCursorLeft(1)
-
-    # Press the delete key.
-    input_stream.extend(Keys.DEL)
-    # This should look like a space, and then move cursor left 1 column since
-    # we're at the end of line.
-    exp_console_out += b' ' + OutputStream.MoveCursorLeft(1)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Verify everything happened correctly.
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_BackspaceOnEmptyLine(self):
-    """Verify that we can backspace on an empty line with no bad effects."""
-    # Send a single backspace.
-    test_str = [console.ControlKey.BACKSPACE]
-
-    # Send the characters in.
-    for byte in test_str:
-      self.console.HandleChar(byte)
-
-    # Check the input position.
-    exp_pos = 0
-    CheckInputBufferPosition(self, exp_pos)
-
-    # Check that buffer is empty.
-    exp_input_buffer = b''
-    CheckInputBuffer(self, exp_input_buffer)
-
-    # Check that the console output is empty.
-    exp_console_out = b''
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_BackspaceWithinLine(self):
-    """Verify that we shift the chars over when backspacing within a line."""
-    # Misspell 'help'
-    test_str = b'heelp'
-    input_stream = BytesToByteList(test_str)
-    # Use the arrow key to go back to fix it.
-    # Move cursor left 1 column.
-    input_stream.extend(2*Keys.LEFT_ARROW)
-    # Backspace once to remove the extra 'e'.
-    input_stream.append(console.ControlKey.BACKSPACE)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Verify the input buffer
-    exp_input_buffer = b'help'
-    CheckInputBuffer(self, exp_input_buffer)
-
-    # Verify the input buffer position. It should be at 2 (cursor over the 'l')
-    CheckInputBufferPosition(self, 2)
-
-    # We expect the console output to be the test string, with two moves to the
-    # left, another move left, and then the rest of the line followed by a
-    # space.
-    exp_console_out = test_str
-    exp_console_out += 2 * OutputStream.MoveCursorLeft(1)
-
-    # Move cursor left 1 column.
-    exp_console_out += OutputStream.MoveCursorLeft(1)
-    # Rest of the line and a space. (test_str in this case)
-    exp_console_out += b'lp '
-    # Reset the cursor 2 + 1 to the left.
-    exp_console_out += OutputStream.MoveCursorLeft(3)
-
-    # Verify console output.
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_JumpToBeginningOfLineViaCtrlA(self):
-    """Verify that we can jump to the beginning of a line with Ctrl+A."""
-    # Enter some chars and press CTRL+A
-    test_str = b'abc'
-    input_stream = BytesToByteList(test_str) + [console.ControlKey.CTRL_A]
-
-    # Send the characters in.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # We expect to see our test string followed by a move cursor left.
-    exp_console_out = test_str
-    exp_console_out += OutputStream.MoveCursorLeft(len(test_str))
-
-    # Check to see what whas printed on the console.
-    CheckConsoleOutput(self, exp_console_out)
-
-    # Check that the input buffer position is now 0.
-    CheckInputBufferPosition(self, 0)
-
-    # Check input buffer still contains our test string.
-    CheckInputBuffer(self, test_str)
-
-  def test_JumpToBeginningOfLineViaHomeKey(self):
-    """Jump to beginning of line via HOME key."""
-    test_str = b'version'
-    input_stream = BytesToByteList(test_str)
-    input_stream.extend(Keys.HOME)
-
-    # Send out the stream.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # First, verify that input buffer position is now 0.
-    CheckInputBufferPosition(self, 0)
-
-    # Next, verify that the input buffer did not change.
-    CheckInputBuffer(self, test_str)
-
-    # Lastly, check that the cursor moved correctly.
-    exp_console_out = test_str
-    exp_console_out += OutputStream.MoveCursorLeft(len(test_str))
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_JumpToEndOfLineViaEndKey(self):
-    """Jump to the end of the line using the END key."""
-    test_str = b'version'
-    input_stream = BytesToByteList(test_str)
-    input_stream += [console.ControlKey.CTRL_A]
-    # Now, jump to the end of the line.
-    input_stream.extend(Keys.END)
-
-    # Send out the stream.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Verify that the input buffer position is correct.  This should be at the
-    # end of the test string.
-    CheckInputBufferPosition(self, len(test_str))
-
-    # The expected output should be the test string, followed by a jump to the
-    # beginning of the line, and lastly a jump to the end of the line.
-    exp_console_out = test_str
-    exp_console_out += OutputStream.MoveCursorLeft(len(test_str))
-    # Now the jump back to the end of the line.
-    exp_console_out += OutputStream.MoveCursorRight(len(test_str))
-
-    # Verify console output stream.
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_JumpToEndOfLineViaCtrlE(self):
-    """Enter some chars and then try to jump to the end. (Should be a no-op)"""
-    test_str = b'sysinfo'
-    input_stream = BytesToByteList(test_str)
-    input_stream.append(console.ControlKey.CTRL_E)
-
-    # Send out the stream
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Verify that the input buffer position isn't any further than we expect.
-    # At this point, the position should be at the end of the test string.
-    CheckInputBufferPosition(self, len(test_str))
-
-    # Now, let's try to jump to the beginning and then jump back to the end.
-    input_stream = [console.ControlKey.CTRL_A, console.ControlKey.CTRL_E]
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Perform the same verification.
-    CheckInputBufferPosition(self, len(test_str))
-
-    # Lastly try to jump again, beyond the end.
-    input_stream = [console.ControlKey.CTRL_E]
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Perform the same verification.
-    CheckInputBufferPosition(self, len(test_str))
-
-    # We expect to see the test string, a jump to the beginning of the line, and
-    # one jump to the end of the line.
-    exp_console_out = test_str
-    # Jump to beginning.
-    exp_console_out += OutputStream.MoveCursorLeft(len(test_str))
-    # Jump back to end.
-    exp_console_out += OutputStream.MoveCursorRight(len(test_str))
-
-    # Verify the console output.
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_MoveLeftWithArrowKey(self):
-    """Move cursor left one column with arrow key."""
-    test_str = b'tastyspam'
-    input_stream = BytesToByteList(test_str)
-    input_stream.extend(Keys.LEFT_ARROW)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Verify that the input buffer position is 1 less than the length.
-    CheckInputBufferPosition(self, len(test_str) - 1)
-
-    # Also, verify that the input buffer is not modified.
-    CheckInputBuffer(self, test_str)
-
-    # We expect the test string, followed by a one column move left.
-    exp_console_out = test_str + OutputStream.MoveCursorLeft(1)
-
-    # Verify console output.
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_MoveLeftWithCtrlB(self):
-    """Move cursor back one column with Ctrl+B."""
-    test_str = b'tastyspam'
-    input_stream = BytesToByteList(test_str)
-    input_stream.append(console.ControlKey.CTRL_B)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Verify that the input buffer position is 1 less than the length.
-    CheckInputBufferPosition(self, len(test_str) - 1)
+def CheckInputBuffer(test_case, exp_input_buffer):
+    """Verify that the input buffer contains what we expect.
 
-    # Also, verify that the input buffer is not modified.
-    CheckInputBuffer(self, test_str)
+    Args:
+      test_case: A unittest.TestCase object representing the current unit test.
+      exp_input_buffer: A string containing the contents of the current input
+        buffer.
+    """
+    test_case.assertEqual(
+        exp_input_buffer,
+        test_case.console.input_buffer,
+        (
+            b"input buffer does not match expected.\n"
+            b"expected: |" + exp_input_buffer + b"|\n"
+            b"got:      |"
+            + test_case.console.input_buffer
+            + b"|\n"
+            + str(test_case.console).encode("ascii")
+        ),
+    )
 
-    # We expect the test string, followed by a one column move left.
-    exp_console_out = test_str + OutputStream.MoveCursorLeft(1)
 
-    # Verify console output.
-    CheckConsoleOutput(self, exp_console_out)
+def CheckInputBufferPosition(test_case, exp_pos):
+    """Verify the input buffer position.
 
-  def test_MoveRightWithArrowKey(self):
-    """Move cursor one column to the right with the arrow key."""
-    test_str = b'version'
-    input_stream = BytesToByteList(test_str)
-    # Jump to beginning of line.
-    input_stream.append(console.ControlKey.CTRL_A)
-    # Press right arrow key.
-    input_stream.extend(Keys.RIGHT_ARROW)
+    Args:
+      test_case: A unittest.TestCase object representing the current unit test.
+      exp_pos: An integer representing the expected input buffer position.
+    """
+    test_case.assertEqual(
+        exp_pos,
+        test_case.console.input_buffer_pos,
+        "input buffer position is incorrect.\ngot: "
+        + str(test_case.console.input_buffer_pos)
+        + "\nexp: "
+        + str(exp_pos)
+        + "\n"
+        + str(test_case.console),
+    )
 
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
 
-    # Verify that the input buffer position is 1.
-    CheckInputBufferPosition(self, 1)
+def CheckHistoryBuffer(test_case, exp_history):
+    """Verify that the items in the history buffer are what we expect.
 
-    # Also, verify that the input buffer is not modified.
-    CheckInputBuffer(self, test_str)
+    Args:
+      test_case: A unittest.TestCase object representing the current unit test.
+      exp_history: A list of strings representing the expected contents of the
+        history buffer.
+    """
+    # First, check to see if the length is what we expect.
+    test_case.assertEqual(
+        len(exp_history),
+        len(test_case.console.history),
+        (
+            "The number of items in the history is unexpected.\n"
+            "exp: " + str(len(exp_history)) + "\n"
+            "got: " + str(len(test_case.console.history)) + "\n"
+            "internal state:\n" + str(test_case.console)
+        ),
+    )
+
+    # Next, check the actual contents of the history buffer.
+    for i in range(len(exp_history)):
+        test_case.assertEqual(
+            exp_history[i],
+            test_case.console.history[i],
+            (
+                b"history buffer contents are incorrect.\n"
+                b"exp: " + exp_history[i] + b"\n"
+                b"got: " + test_case.console.history[i] + b"\n"
+                b"internal state:\n" + str(test_case.console).encode("ascii")
+            ),
+        )
 
-    # We expect the test string, followed by a jump to the beginning of the
-    # line, and finally a move right 1.
-    exp_console_out = test_str + OutputStream.MoveCursorLeft(len((test_str)))
-
-    # A move right 1 column.
-    exp_console_out += OutputStream.MoveCursorRight(1)
-
-    # Verify console output.
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_MoveRightWithCtrlF(self):
-    """Move cursor forward one column with Ctrl+F."""
-    test_str = b'panicinfo'
-    input_stream = BytesToByteList(test_str)
-    input_stream.append(console.ControlKey.CTRL_A)
-    # Now, move right one column.
-    input_stream.append(console.ControlKey.CTRL_F)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Verify that the input buffer position is 1.
-    CheckInputBufferPosition(self, 1)
-
-    # Also, verify that the input buffer is not modified.
-    CheckInputBuffer(self, test_str)
-
-    # We expect the test string, followed by a jump to the beginning of the
-    # line, and finally a move right 1.
-    exp_console_out = test_str + OutputStream.MoveCursorLeft(len((test_str)))
-
-    # A move right 1 column.
-    exp_console_out += OutputStream.MoveCursorRight(1)
-
-    # Verify console output.
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_ImpossibleMoveLeftWithArrowKey(self):
-    """Verify that we can't move left at the beginning of the line."""
-    # We shouldn't be able to move left if we're at the beginning of the line.
-    input_stream = Keys.LEFT_ARROW
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Nothing should have been output.
-    exp_console_output = b''
-    CheckConsoleOutput(self, exp_console_output)
-
-    # The input buffer position should still be 0.
-    CheckInputBufferPosition(self, 0)
-
-    # The input buffer itself should be empty.
-    CheckInputBuffer(self, b'')
-
-  def test_ImpossibleMoveRightWithArrowKey(self):
-    """Verify that we can't move right at the end of the line."""
-    # We shouldn't be able to move right if we're at the end of the line.
-    input_stream = Keys.RIGHT_ARROW
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Nothing should have been output.
-    exp_console_output = b''
-    CheckConsoleOutput(self, exp_console_output)
-
-    # The input buffer position should still be 0.
-    CheckInputBufferPosition(self, 0)
-
-    # The input buffer itself should be empty.
-    CheckInputBuffer(self, b'')
-
-  def test_KillEntireLine(self):
-    """Verify that we can kill an entire line with Ctrl+K."""
-    test_str = b'accelinfo on'
-    input_stream = BytesToByteList(test_str)
-    # Jump to beginning of line and then kill it with Ctrl+K.
-    input_stream.extend([console.ControlKey.CTRL_A, console.ControlKey.CTRL_K])
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # First, we expect that the input buffer is empty.
-    CheckInputBuffer(self, b'')
-
-    # The buffer position should be 0.
-    CheckInputBufferPosition(self, 0)
-
-    # What we expect to see on the console stream should be the following.  The
-    # test string, a jump to the beginning of the line, then jump back to the
-    # end of the line and replace the line with spaces.
-    exp_console_out = test_str
-    # Jump to beginning of line.
-    exp_console_out += OutputStream.MoveCursorLeft(len(test_str))
-    # Jump to end of line.
-    exp_console_out += OutputStream.MoveCursorRight(len(test_str))
-    # Replace line with spaces, which looks like backspaces.
-    for _ in range(len(test_str)):
-      exp_console_out += BACKSPACE_STRING
-
-    # Verify the console output.
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_KillPartialLine(self):
-    """Verify that we can kill a portion of a line."""
-    test_str = b'accelread 0 1'
-    input_stream = BytesToByteList(test_str)
-    len_to_kill = 5
-    for _ in range(len_to_kill):
-      # Move cursor left
-      input_stream.extend(Keys.LEFT_ARROW)
-    # Now kill
-    input_stream.append(console.ControlKey.CTRL_K)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # First, check that the input buffer was truncated.
-    exp_input_buffer = test_str[:-len_to_kill]
-    CheckInputBuffer(self, exp_input_buffer)
-
-    # Verify the input buffer position.
-    CheckInputBufferPosition(self, len(test_str) - len_to_kill)
-
-    # The console output stream that we expect is the test string followed by a
-    # move left of len_to_kill, then a jump to the end of the line and backspace
-    # of len_to_kill.
-    exp_console_out = test_str
-    for _ in range(len_to_kill):
-      # Move left 1 column.
-      exp_console_out += OutputStream.MoveCursorLeft(1)
-    # Then jump to the end of the line
-    exp_console_out += OutputStream.MoveCursorRight(len_to_kill)
-    # Backspace of len_to_kill
-    for _ in range(len_to_kill):
-      exp_console_out += BACKSPACE_STRING
-
-    # Verify console output.
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_InsertingCharacters(self):
-    """Verify that we can insert characters within the line."""
-    test_str = b'accel 0 1' # Here we forgot the 'read' part in 'accelread'
-    input_stream = BytesToByteList(test_str)
-    # We need to move over to the 'l' and add read.
-    insertion_point = test_str.find(b'l') + 1
-    for i in range(len(test_str) - insertion_point):
-      # Move cursor left.
-      input_stream.extend(Keys.LEFT_ARROW)
-    # Now, add in 'read'
-    added_str = b'read'
-    input_stream.extend(BytesToByteList(added_str))
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # First, verify that the input buffer is correct.
-    exp_input_buffer = test_str[:insertion_point] + added_str
-    exp_input_buffer += test_str[insertion_point:]
-    CheckInputBuffer(self, exp_input_buffer)
-
-    # Verify that the input buffer position is correct.
-    exp_input_buffer_pos = insertion_point + len(added_str)
-    CheckInputBufferPosition(self, exp_input_buffer_pos)
-
-    # The console output stream that we expect is the test string, followed by
-    # move cursor left until the 'l' was found, the added test string while
-    # shifting characters around.
-    exp_console_out = test_str
-    for i in range(len(test_str) - insertion_point):
-      # Move cursor left.
-      exp_console_out += OutputStream.MoveCursorLeft(1)
-
-    # Now for each character, write the rest of the line will be shifted to the
-    # right one column.
-    for i in range(len(added_str)):
-      # Printed character.
-      exp_console_out += added_str[i:i+1]
-      # The rest of the line
-      exp_console_out += test_str[insertion_point:]
-      # Reset the cursor back left
-      reset_dist = len(test_str[insertion_point:])
-      exp_console_out += OutputStream.MoveCursorLeft(reset_dist)
-
-    # Verify the console output.
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_StoreCommandHistory(self):
-    """Verify that entered commands are stored in the history."""
-    test_commands = []
-    test_commands.append(b'help')
-    test_commands.append(b'version')
-    test_commands.append(b'accelread 0 1')
-    input_stream = []
-    for c in test_commands:
-      input_stream.extend(BytesToByteList(c))
-      input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # We expect to have the test commands in the history buffer.
-    exp_history_buf = test_commands
-    CheckHistoryBuffer(self, exp_history_buf)
-
-  def test_CycleUpThruCommandHistory(self):
-    """Verify that the UP arrow key will print itmes in the history buffer."""
-    # Enter some commands.
-    test_commands = [b'version', b'accelrange 0', b'battery', b'gettime']
-    input_stream = []
-    for command in test_commands:
-      input_stream.extend(BytesToByteList(command))
-      input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Now, hit the UP arrow key to print the previous entries.
-    for i in range(len(test_commands)):
-      input_stream.extend(Keys.UP_ARROW)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # The expected output should be test commands with prompts printed in
-    # between, followed by line kills with the previous test commands printed.
-    exp_console_out = b''
-    for i in range(len(test_commands)):
-      exp_console_out += test_commands[i] + b'\r\n' + self.console.prompt
-
-    # When we press up, the line should be cleared and print the previous buffer
-    # entry.
-    for i in range(len(test_commands)-1, 0, -1):
-      exp_console_out += test_commands[i]
-      # Backspace to the beginning.
-      for i in range(len(test_commands[i])):
-        exp_console_out += BACKSPACE_STRING
 
-    # The last command should just be printed out with no backspacing.
-    exp_console_out += test_commands[0]
-
-    # Now, verify.
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_UpArrowOnEmptyHistory(self):
-    """Ensure nothing happens if the history is empty."""
-    # Press the up arrow key twice.
-    input_stream = 2 * Keys.UP_ARROW
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # We expect nothing to have happened.
-    exp_console_out = b''
-    exp_input_buffer = b''
-    exp_input_buffer_pos = 0
-    exp_history_buf = []
-
-    # Verify.
-    CheckConsoleOutput(self, exp_console_out)
-    CheckInputBufferPosition(self, exp_input_buffer_pos)
-    CheckInputBuffer(self, exp_input_buffer)
-    CheckHistoryBuffer(self, exp_history_buf)
-
-  def test_UpArrowDoesNotGoOutOfBounds(self):
-    """Verify that pressing the up arrow many times won't go out of bounds."""
-    # Enter one command.
-    test_str = b'help version'
-    input_stream = BytesToByteList(test_str)
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-    # Then press the up arrow key twice.
-    input_stream.extend(2 * Keys.UP_ARROW)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Verify that the history buffer is correct.
-    exp_history_buf = [test_str]
-    CheckHistoryBuffer(self, exp_history_buf)
-
-    # We expect that the console output should only contain our entered command,
-    # a new prompt, and then our command aggain.
-    exp_console_out = test_str + b'\r\n' + self.console.prompt
-    # Pressing up should reprint the command we entered.
-    exp_console_out += test_str
-
-    # Verify.
-    CheckConsoleOutput(self, exp_console_out)
-
-  def test_CycleDownThruCommandHistory(self):
-    """Verify that we can select entries by hitting the down arrow."""
-    # Enter at least 4 commands.
-    test_commands = [b'version', b'accelrange 0', b'battery', b'gettime']
-    input_stream = []
-    for command in test_commands:
-      input_stream.extend(BytesToByteList(command))
-      input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Now, hit the UP arrow key twice to print the previous two entries.
-    for i in range(2):
-      input_stream.extend(Keys.UP_ARROW)
-
-    # Now, hit the DOWN arrow key twice to print the newer entries.
-    input_stream.extend(2*Keys.DOWN_ARROW)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # The expected output should be commands that we entered, followed by
-    # prompts, then followed by our last two commands in reverse.  Then, we
-    # should see the last entry in the list, followed by the saved partial cmd
-    # of a blank line.
-    exp_console_out = b''
-    for i in range(len(test_commands)):
-      exp_console_out += test_commands[i] + b'\r\n' + self.console.prompt
-
-    # When we press up, the line should be cleared and print the previous buffer
-    # entry.
-    for i in range(len(test_commands)-1, 1, -1):
-      exp_console_out += test_commands[i]
-      # Backspace to the beginning.
-      for i in range(len(test_commands[i])):
+class TestConsoleEditingMethods(unittest.TestCase):
+    """Test case to verify all console editing methods."""
+
+    def setUp(self):
+        """Setup the test harness."""
+        # Setup logging with a timestamp, the module, and the log level.
+        logging.basicConfig(
+            level=logging.DEBUG,
+            format=("%(asctime)s - %(module)s - %(levelname)s - %(message)s"),
+        )
+
+        # Create a temp file and set both the controller and peripheral PTYs to the
+        # file to create a loopback.
+        self.tempfile = tempfile.TemporaryFile()
+
+        # Create some mock pipes. These won't be used since we'll mock out sends
+        # to the interpreter.
+        mock_pipe_end_0, mock_pipe_end_1 = threadproc_shim.Pipe()
+        self.console = console.Console(
+            self.tempfile.fileno(),
+            self.tempfile,
+            tempfile.TemporaryFile(),
+            mock_pipe_end_0,
+            mock_pipe_end_1,
+            "EC",
+        )
+
+        # Console editing methods are only valid for enhanced EC images, therefore
+        # we have to assume that the "EC" we're talking to is enhanced.  By default,
+        # the console believes that the EC it's communicating with is NOT enhanced
+        # which is why we have to override it here.
+        self.console.enhanced_ec = True
+        self.console.CheckForEnhancedECImage = mock.MagicMock(return_value=True)
+
+    def test_EnteringChars(self):
+        """Verify that characters are echoed onto the console."""
+        test_str = b"abc"
+        input_stream = BytesToByteList(test_str)
+
+        # Send the characters in.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # Check the input position.
+        exp_pos = len(test_str)
+        CheckInputBufferPosition(self, exp_pos)
+
+        # Verify that the input buffer is correct.
+        expected_buffer = test_str
+        CheckInputBuffer(self, expected_buffer)
+
+        # Check console output
+        exp_console_out = test_str
+        CheckConsoleOutput(self, exp_console_out)
+
+    def test_EnteringDeletingMoreCharsThanEntered(self):
+        """Verify that we can press backspace more than we have entered chars."""
+        test_str = b"spamspam"
+        input_stream = BytesToByteList(test_str)
+
+        # Send the characters in.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # Now backspace 1 more than what we sent.
+        input_stream = []
+        for _ in range(len(test_str) + 1):
+            input_stream.append(console.ControlKey.BACKSPACE)
+
+        # Send that sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # First, verify that input buffer position is 0.
+        CheckInputBufferPosition(self, 0)
+
+        # Next, examine the output stream for the correct sequence.
+        exp_console_out = test_str
+        for _ in range(len(test_str)):
+            exp_console_out += BACKSPACE_STRING
+
+        # Now, verify that we got what we expected.
+        CheckConsoleOutput(self, exp_console_out)
+
+    def test_EnteringMoreThanCharLimit(self):
+        """Verify that we drop characters when the line is too long."""
+        test_str = self.console.line_limit * b"o"  # All allowed.
+        test_str += 5 * b"x"  # All should be dropped.
+        input_stream = BytesToByteList(test_str)
+
+        # Send the characters in.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # First, we expect that input buffer position should be equal to the line
+        # limit.
+        exp_pos = self.console.line_limit
+        CheckInputBufferPosition(self, exp_pos)
+
+        # The input buffer should only hold until the line limit.
+        exp_buffer = test_str[0 : self.console.line_limit]
+        CheckInputBuffer(self, exp_buffer)
+
+        # Lastly, check that the extra characters are not printed.
+        exp_console_out = exp_buffer
+        CheckConsoleOutput(self, exp_console_out)
+
+    def test_ValidKeysOnLongLine(self):
+        """Verify that we can still press valid keys if the line is too long."""
+        # Fill the line.
+        test_str = self.console.line_limit * b"o"
+        exp_console_out = test_str
+        # Try to fill it even more; these should all be dropped.
+        test_str += 5 * b"x"
+        input_stream = BytesToByteList(test_str)
+
+        # We should be able to press the following keys:
+        # - Backspace
+        # - Arrow Keys/CTRL+B/CTRL+F/CTRL+P/CTRL+N
+        # - Delete
+        # - Home/CTRL+A
+        # - End/CTRL+E
+        # - Carriage Return
+
+        # Backspace 1 character
+        input_stream.append(console.ControlKey.BACKSPACE)
         exp_console_out += BACKSPACE_STRING
+        # Refill the line.
+        input_stream.extend(BytesToByteList(b"o"))
+        exp_console_out += b"o"
+
+        # Left arrow key.
+        input_stream.extend(Keys.LEFT_ARROW)
+        exp_console_out += OutputStream.MoveCursorLeft(1)
+
+        # Right arrow key.
+        input_stream.extend(Keys.RIGHT_ARROW)
+        exp_console_out += OutputStream.MoveCursorRight(1)
+
+        # CTRL+B
+        input_stream.append(console.ControlKey.CTRL_B)
+        exp_console_out += OutputStream.MoveCursorLeft(1)
+
+        # CTRL+F
+        input_stream.append(console.ControlKey.CTRL_F)
+        exp_console_out += OutputStream.MoveCursorRight(1)
+
+        # Let's press enter now so we can test up and down.
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+        exp_console_out += b"\r\n" + self.console.prompt
+
+        # Up arrow key.
+        input_stream.extend(Keys.UP_ARROW)
+        exp_console_out += test_str[: self.console.line_limit]
+
+        # Down arrow key.
+        input_stream.extend(Keys.DOWN_ARROW)
+        # Since the line was blank, we have to backspace the entire line.
+        exp_console_out += self.console.line_limit * BACKSPACE_STRING
+
+        # CTRL+P
+        input_stream.append(console.ControlKey.CTRL_P)
+        exp_console_out += test_str[: self.console.line_limit]
+
+        # CTRL+N
+        input_stream.append(console.ControlKey.CTRL_N)
+        # Since the line was blank, we have to backspace the entire line.
+        exp_console_out += self.console.line_limit * BACKSPACE_STRING
+
+        # Press the Up arrow key to reprint the long line.
+        input_stream.extend(Keys.UP_ARROW)
+        exp_console_out += test_str[: self.console.line_limit]
+
+        # Press the Home key to jump to the beginning of the line.
+        input_stream.extend(Keys.HOME)
+        exp_console_out += OutputStream.MoveCursorLeft(self.console.line_limit)
+
+        # Press the End key to jump to the end of the line.
+        input_stream.extend(Keys.END)
+        exp_console_out += OutputStream.MoveCursorRight(self.console.line_limit)
+
+        # Press CTRL+A to jump to the beginning of the line.
+        input_stream.append(console.ControlKey.CTRL_A)
+        exp_console_out += OutputStream.MoveCursorLeft(self.console.line_limit)
+
+        # Press CTRL+E to jump to the end of the line.
+        input_stream.extend(Keys.END)
+        exp_console_out += OutputStream.MoveCursorRight(self.console.line_limit)
+
+        # Move left one column so we can delete a character.
+        input_stream.extend(Keys.LEFT_ARROW)
+        exp_console_out += OutputStream.MoveCursorLeft(1)
+
+        # Press the delete key.
+        input_stream.extend(Keys.DEL)
+        # This should look like a space, and then move cursor left 1 column since
+        # we're at the end of line.
+        exp_console_out += b" " + OutputStream.MoveCursorLeft(1)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # Verify everything happened correctly.
+        CheckConsoleOutput(self, exp_console_out)
+
+    def test_BackspaceOnEmptyLine(self):
+        """Verify that we can backspace on an empty line with no bad effects."""
+        # Send a single backspace.
+        test_str = [console.ControlKey.BACKSPACE]
+
+        # Send the characters in.
+        for byte in test_str:
+            self.console.HandleChar(byte)
+
+        # Check the input position.
+        exp_pos = 0
+        CheckInputBufferPosition(self, exp_pos)
+
+        # Check that buffer is empty.
+        exp_input_buffer = b""
+        CheckInputBuffer(self, exp_input_buffer)
+
+        # Check that the console output is empty.
+        exp_console_out = b""
+        CheckConsoleOutput(self, exp_console_out)
+
+    def test_BackspaceWithinLine(self):
+        """Verify that we shift the chars over when backspacing within a line."""
+        # Misspell 'help'
+        test_str = b"heelp"
+        input_stream = BytesToByteList(test_str)
+        # Use the arrow key to go back to fix it.
+        # Move cursor left 1 column.
+        input_stream.extend(2 * Keys.LEFT_ARROW)
+        # Backspace once to remove the extra 'e'.
+        input_stream.append(console.ControlKey.BACKSPACE)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # Verify the input buffer
+        exp_input_buffer = b"help"
+        CheckInputBuffer(self, exp_input_buffer)
+
+        # Verify the input buffer position. It should be at 2 (cursor over the 'l')
+        CheckInputBufferPosition(self, 2)
+
+        # We expect the console output to be the test string, with two moves to the
+        # left, another move left, and then the rest of the line followed by a
+        # space.
+        exp_console_out = test_str
+        exp_console_out += 2 * OutputStream.MoveCursorLeft(1)
+
+        # Move cursor left 1 column.
+        exp_console_out += OutputStream.MoveCursorLeft(1)
+        # Rest of the line and a space. (test_str in this case)
+        exp_console_out += b"lp "
+        # Reset the cursor 2 + 1 to the left.
+        exp_console_out += OutputStream.MoveCursorLeft(3)
+
+        # Verify console output.
+        CheckConsoleOutput(self, exp_console_out)
+
+    def test_JumpToBeginningOfLineViaCtrlA(self):
+        """Verify that we can jump to the beginning of a line with Ctrl+A."""
+        # Enter some chars and press CTRL+A
+        test_str = b"abc"
+        input_stream = BytesToByteList(test_str) + [console.ControlKey.CTRL_A]
+
+        # Send the characters in.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # We expect to see our test string followed by a move cursor left.
+        exp_console_out = test_str
+        exp_console_out += OutputStream.MoveCursorLeft(len(test_str))
+
+        # Check to see what whas printed on the console.
+        CheckConsoleOutput(self, exp_console_out)
+
+        # Check that the input buffer position is now 0.
+        CheckInputBufferPosition(self, 0)
+
+        # Check input buffer still contains our test string.
+        CheckInputBuffer(self, test_str)
+
+    def test_JumpToBeginningOfLineViaHomeKey(self):
+        """Jump to beginning of line via HOME key."""
+        test_str = b"version"
+        input_stream = BytesToByteList(test_str)
+        input_stream.extend(Keys.HOME)
+
+        # Send out the stream.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # First, verify that input buffer position is now 0.
+        CheckInputBufferPosition(self, 0)
+
+        # Next, verify that the input buffer did not change.
+        CheckInputBuffer(self, test_str)
+
+        # Lastly, check that the cursor moved correctly.
+        exp_console_out = test_str
+        exp_console_out += OutputStream.MoveCursorLeft(len(test_str))
+        CheckConsoleOutput(self, exp_console_out)
+
+    def test_JumpToEndOfLineViaEndKey(self):
+        """Jump to the end of the line using the END key."""
+        test_str = b"version"
+        input_stream = BytesToByteList(test_str)
+        input_stream += [console.ControlKey.CTRL_A]
+        # Now, jump to the end of the line.
+        input_stream.extend(Keys.END)
+
+        # Send out the stream.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # Verify that the input buffer position is correct.  This should be at the
+        # end of the test string.
+        CheckInputBufferPosition(self, len(test_str))
+
+        # The expected output should be the test string, followed by a jump to the
+        # beginning of the line, and lastly a jump to the end of the line.
+        exp_console_out = test_str
+        exp_console_out += OutputStream.MoveCursorLeft(len(test_str))
+        # Now the jump back to the end of the line.
+        exp_console_out += OutputStream.MoveCursorRight(len(test_str))
+
+        # Verify console output stream.
+        CheckConsoleOutput(self, exp_console_out)
+
+    def test_JumpToEndOfLineViaCtrlE(self):
+        """Enter some chars and then try to jump to the end. (Should be a no-op)"""
+        test_str = b"sysinfo"
+        input_stream = BytesToByteList(test_str)
+        input_stream.append(console.ControlKey.CTRL_E)
+
+        # Send out the stream
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # Verify that the input buffer position isn't any further than we expect.
+        # At this point, the position should be at the end of the test string.
+        CheckInputBufferPosition(self, len(test_str))
+
+        # Now, let's try to jump to the beginning and then jump back to the end.
+        input_stream = [console.ControlKey.CTRL_A, console.ControlKey.CTRL_E]
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # Perform the same verification.
+        CheckInputBufferPosition(self, len(test_str))
+
+        # Lastly try to jump again, beyond the end.
+        input_stream = [console.ControlKey.CTRL_E]
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # Perform the same verification.
+        CheckInputBufferPosition(self, len(test_str))
+
+        # We expect to see the test string, a jump to the beginning of the line, and
+        # one jump to the end of the line.
+        exp_console_out = test_str
+        # Jump to beginning.
+        exp_console_out += OutputStream.MoveCursorLeft(len(test_str))
+        # Jump back to end.
+        exp_console_out += OutputStream.MoveCursorRight(len(test_str))
+
+        # Verify the console output.
+        CheckConsoleOutput(self, exp_console_out)
+
+    def test_MoveLeftWithArrowKey(self):
+        """Move cursor left one column with arrow key."""
+        test_str = b"tastyspam"
+        input_stream = BytesToByteList(test_str)
+        input_stream.extend(Keys.LEFT_ARROW)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # Verify that the input buffer position is 1 less than the length.
+        CheckInputBufferPosition(self, len(test_str) - 1)
+
+        # Also, verify that the input buffer is not modified.
+        CheckInputBuffer(self, test_str)
+
+        # We expect the test string, followed by a one column move left.
+        exp_console_out = test_str + OutputStream.MoveCursorLeft(1)
+
+        # Verify console output.
+        CheckConsoleOutput(self, exp_console_out)
+
+    def test_MoveLeftWithCtrlB(self):
+        """Move cursor back one column with Ctrl+B."""
+        test_str = b"tastyspam"
+        input_stream = BytesToByteList(test_str)
+        input_stream.append(console.ControlKey.CTRL_B)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # Verify that the input buffer position is 1 less than the length.
+        CheckInputBufferPosition(self, len(test_str) - 1)
+
+        # Also, verify that the input buffer is not modified.
+        CheckInputBuffer(self, test_str)
+
+        # We expect the test string, followed by a one column move left.
+        exp_console_out = test_str + OutputStream.MoveCursorLeft(1)
 
-    # When we press down, it should have cleared the last command (which we
-    # covered with the previous for loop), and then prints the next command.
-    exp_console_out += test_commands[3]
-    for i in range(len(test_commands[3])):
-      exp_console_out += BACKSPACE_STRING
-
-    # Verify console output.
-    CheckConsoleOutput(self, exp_console_out)
-
-    # Verify input buffer.
-    exp_input_buffer = b'' # Empty because our partial command was empty.
-    exp_input_buffer_pos = len(exp_input_buffer)
-    CheckInputBuffer(self, exp_input_buffer)
-    CheckInputBufferPosition(self, exp_input_buffer_pos)
-
-  def test_SavingPartialCommandWhenNavigatingHistory(self):
-    """Verify that partial commands are saved when navigating history."""
-    # Enter a command.
-    test_str = b'accelinfo'
-    input_stream = BytesToByteList(test_str)
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Enter a partial command.
-    partial_cmd = b'ver'
-    input_stream.extend(BytesToByteList(partial_cmd))
-
-    # Hit the UP arrow key.
-    input_stream.extend(Keys.UP_ARROW)
-    # Then, the DOWN arrow key.
-    input_stream.extend(Keys.DOWN_ARROW)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # The expected output should be the command we entered, a prompt, the
-    # partial command, clearing of the partial command, the command entered,
-    # clearing of the command entered, and then the partial command.
-    exp_console_out = test_str + b'\r\n' + self.console.prompt
-    exp_console_out += partial_cmd
-    for _ in range(len(partial_cmd)):
-      exp_console_out += BACKSPACE_STRING
-    exp_console_out += test_str
-    for _ in range(len(test_str)):
-      exp_console_out += BACKSPACE_STRING
-    exp_console_out += partial_cmd
-
-    # Verify console output.
-    CheckConsoleOutput(self, exp_console_out)
-
-    # Verify input buffer.
-    exp_input_buffer = partial_cmd
-    exp_input_buffer_pos = len(exp_input_buffer)
-    CheckInputBuffer(self, exp_input_buffer)
-    CheckInputBufferPosition(self, exp_input_buffer_pos)
-
-  def test_DownArrowOnEmptyHistory(self):
-    """Ensure nothing happens if the history is empty."""
-    # Then press the up down arrow twice.
-    input_stream = 2 * Keys.DOWN_ARROW
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # We expect nothing to have happened.
-    exp_console_out = b''
-    exp_input_buffer = b''
-    exp_input_buffer_pos = 0
-    exp_history_buf = []
-
-    # Verify.
-    CheckConsoleOutput(self, exp_console_out)
-    CheckInputBufferPosition(self, exp_input_buffer_pos)
-    CheckInputBuffer(self, exp_input_buffer)
-    CheckHistoryBuffer(self, exp_history_buf)
-
-  def test_DeleteCharsUsingDELKey(self):
-    """Verify that we can delete characters using the DEL key."""
-    test_str = b'version'
-    input_stream = BytesToByteList(test_str)
-
-    # Hit the left arrow key 2 times.
-    input_stream.extend(2 * Keys.LEFT_ARROW)
-
-    # Press the DEL key.
-    input_stream.extend(Keys.DEL)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # The expected output should be the command we entered, 2 individual cursor
-    # moves to the left, and then removing a char and shifting everything to the
-    # left one column.
-    exp_console_out = test_str
-    exp_console_out += 2 * OutputStream.MoveCursorLeft(1)
-
-    # Remove the char by shifting everything to the left one, slicing out the
-    # remove char.
-    exp_console_out += test_str[-1:] + b' '
-
-    # Reset the cursor by moving back 2 columns because of the 'n' and space.
-    exp_console_out += OutputStream.MoveCursorLeft(2)
-
-    # Verify console output.
-    CheckConsoleOutput(self, exp_console_out)
-
-    # Verify input buffer.  The input buffer should have the char sliced out and
-    # be positioned where the char was removed.
-    exp_input_buffer = test_str[:-2] + test_str[-1:]
-    exp_input_buffer_pos = len(exp_input_buffer) - 1
-    CheckInputBuffer(self, exp_input_buffer)
-    CheckInputBufferPosition(self, exp_input_buffer_pos)
-
-  def test_RepeatedCommandInHistory(self):
-    """Verify that we don't store 2 consecutive identical commands in history"""
-    # Enter a few commands.
-    test_commands = [b'version', b'accelrange 0', b'battery', b'gettime']
-    # Repeat the last command.
-    test_commands.append(test_commands[len(test_commands)-1])
-
-    input_stream = []
-    for command in test_commands:
-      input_stream.extend(BytesToByteList(command))
-      input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Verify that the history buffer is correct.  The last command, since
-    # it was repeated, should not have been added to the history.
-    exp_history_buf = test_commands[0:len(test_commands)-1]
-    CheckHistoryBuffer(self, exp_history_buf)
+        # Verify console output.
+        CheckConsoleOutput(self, exp_console_out)
 
+    def test_MoveRightWithArrowKey(self):
+        """Move cursor one column to the right with the arrow key."""
+        test_str = b"version"
+        input_stream = BytesToByteList(test_str)
+        # Jump to beginning of line.
+        input_stream.append(console.ControlKey.CTRL_A)
+        # Press right arrow key.
+        input_stream.extend(Keys.RIGHT_ARROW)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # Verify that the input buffer position is 1.
+        CheckInputBufferPosition(self, 1)
 
-class TestConsoleCompatibility(unittest.TestCase):
-  """Verify that console can speak to enhanced and non-enhanced EC images."""
-  def setUp(self):
-    """Setup the test harness."""
-    # Setup logging with a timestamp, the module, and the log level.
-    logging.basicConfig(level=logging.DEBUG,
-                        format=('%(asctime)s - %(module)s -'
-                                ' %(levelname)s - %(message)s'))
-    # Create a temp file and set both the controller and peripheral PTYs to the
-    # file to create a loopback.
-    self.tempfile = tempfile.TemporaryFile()
-
-    # Mock out the pipes.
-    mock_pipe_end_0, mock_pipe_end_1 = mock.MagicMock(), mock.MagicMock()
-    self.console = console.Console(self.tempfile.fileno(), self.tempfile,
-                                   tempfile.TemporaryFile(),
-                                   mock_pipe_end_0, mock_pipe_end_1, "EC")
-
-  @mock.patch('ec3po.console.Console.CheckForEnhancedECImage')
-  def test_ActAsPassThruInNonEnhancedMode(self, mock_check):
-    """Verify we simply pass everything thru to non-enhanced ECs.
+        # Also, verify that the input buffer is not modified.
+        CheckInputBuffer(self, test_str)
 
-    Args:
-      mock_check: A MagicMock object replacing the CheckForEnhancedECImage()
-        method.
-    """
-    # Set the interrogation mode to always so that we actually interrogate.
-    self.console.interrogation_mode = b'always'
-
-    # Assume EC interrogations indicate that the image is non-enhanced.
-    mock_check.return_value = False
-
-    # Press enter, followed by the command, and another enter.
-    input_stream = []
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-    test_command = b'version'
-    input_stream.extend(BytesToByteList(test_command))
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Expected calls to send down the pipe would be each character of the test
-    # command.
-    expected_calls = []
-    expected_calls.append(mock.call(
-        six.int2byte(console.ControlKey.CARRIAGE_RETURN)))
-    for char in test_command:
-      if six.PY3:
-        expected_calls.append(mock.call(bytes([char])))
-      else:
-        expected_calls.append(mock.call(char))
-    expected_calls.append(mock.call(
-        six.int2byte(console.ControlKey.CARRIAGE_RETURN)))
-
-    # Verify that the calls happened.
-    self.console.cmd_pipe.send.assert_has_calls(expected_calls)
-
-    # Since we're acting as a pass-thru, the input buffer should be empty and
-    # input_buffer_pos is 0.
-    CheckInputBuffer(self, b'')
-    CheckInputBufferPosition(self, 0)
-
-  @mock.patch('ec3po.console.Console.CheckForEnhancedECImage')
-  def test_TransitionFromNonEnhancedToEnhanced(self, mock_check):
-    """Verify that we transition correctly to enhanced mode.
+        # We expect the test string, followed by a jump to the beginning of the
+        # line, and finally a move right 1.
+        exp_console_out = test_str + OutputStream.MoveCursorLeft(
+            len((test_str))
+        )
+
+        # A move right 1 column.
+        exp_console_out += OutputStream.MoveCursorRight(1)
+
+        # Verify console output.
+        CheckConsoleOutput(self, exp_console_out)
+
+    def test_MoveRightWithCtrlF(self):
+        """Move cursor forward one column with Ctrl+F."""
+        test_str = b"panicinfo"
+        input_stream = BytesToByteList(test_str)
+        input_stream.append(console.ControlKey.CTRL_A)
+        # Now, move right one column.
+        input_stream.append(console.ControlKey.CTRL_F)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # Verify that the input buffer position is 1.
+        CheckInputBufferPosition(self, 1)
+
+        # Also, verify that the input buffer is not modified.
+        CheckInputBuffer(self, test_str)
+
+        # We expect the test string, followed by a jump to the beginning of the
+        # line, and finally a move right 1.
+        exp_console_out = test_str + OutputStream.MoveCursorLeft(
+            len((test_str))
+        )
+
+        # A move right 1 column.
+        exp_console_out += OutputStream.MoveCursorRight(1)
+
+        # Verify console output.
+        CheckConsoleOutput(self, exp_console_out)
+
+    def test_ImpossibleMoveLeftWithArrowKey(self):
+        """Verify that we can't move left at the beginning of the line."""
+        # We shouldn't be able to move left if we're at the beginning of the line.
+        input_stream = Keys.LEFT_ARROW
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # Nothing should have been output.
+        exp_console_output = b""
+        CheckConsoleOutput(self, exp_console_output)
+
+        # The input buffer position should still be 0.
+        CheckInputBufferPosition(self, 0)
+
+        # The input buffer itself should be empty.
+        CheckInputBuffer(self, b"")
+
+    def test_ImpossibleMoveRightWithArrowKey(self):
+        """Verify that we can't move right at the end of the line."""
+        # We shouldn't be able to move right if we're at the end of the line.
+        input_stream = Keys.RIGHT_ARROW
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # Nothing should have been output.
+        exp_console_output = b""
+        CheckConsoleOutput(self, exp_console_output)
+
+        # The input buffer position should still be 0.
+        CheckInputBufferPosition(self, 0)
+
+        # The input buffer itself should be empty.
+        CheckInputBuffer(self, b"")
+
+    def test_KillEntireLine(self):
+        """Verify that we can kill an entire line with Ctrl+K."""
+        test_str = b"accelinfo on"
+        input_stream = BytesToByteList(test_str)
+        # Jump to beginning of line and then kill it with Ctrl+K.
+        input_stream.extend(
+            [console.ControlKey.CTRL_A, console.ControlKey.CTRL_K]
+        )
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # First, we expect that the input buffer is empty.
+        CheckInputBuffer(self, b"")
+
+        # The buffer position should be 0.
+        CheckInputBufferPosition(self, 0)
+
+        # What we expect to see on the console stream should be the following.  The
+        # test string, a jump to the beginning of the line, then jump back to the
+        # end of the line and replace the line with spaces.
+        exp_console_out = test_str
+        # Jump to beginning of line.
+        exp_console_out += OutputStream.MoveCursorLeft(len(test_str))
+        # Jump to end of line.
+        exp_console_out += OutputStream.MoveCursorRight(len(test_str))
+        # Replace line with spaces, which looks like backspaces.
+        for _ in range(len(test_str)):
+            exp_console_out += BACKSPACE_STRING
+
+        # Verify the console output.
+        CheckConsoleOutput(self, exp_console_out)
+
+    def test_KillPartialLine(self):
+        """Verify that we can kill a portion of a line."""
+        test_str = b"accelread 0 1"
+        input_stream = BytesToByteList(test_str)
+        len_to_kill = 5
+        for _ in range(len_to_kill):
+            # Move cursor left
+            input_stream.extend(Keys.LEFT_ARROW)
+        # Now kill
+        input_stream.append(console.ControlKey.CTRL_K)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # First, check that the input buffer was truncated.
+        exp_input_buffer = test_str[:-len_to_kill]
+        CheckInputBuffer(self, exp_input_buffer)
+
+        # Verify the input buffer position.
+        CheckInputBufferPosition(self, len(test_str) - len_to_kill)
+
+        # The console output stream that we expect is the test string followed by a
+        # move left of len_to_kill, then a jump to the end of the line and backspace
+        # of len_to_kill.
+        exp_console_out = test_str
+        for _ in range(len_to_kill):
+            # Move left 1 column.
+            exp_console_out += OutputStream.MoveCursorLeft(1)
+        # Then jump to the end of the line
+        exp_console_out += OutputStream.MoveCursorRight(len_to_kill)
+        # Backspace of len_to_kill
+        for _ in range(len_to_kill):
+            exp_console_out += BACKSPACE_STRING
+
+        # Verify console output.
+        CheckConsoleOutput(self, exp_console_out)
+
+    def test_InsertingCharacters(self):
+        """Verify that we can insert characters within the line."""
+        test_str = b"accel 0 1"  # Here we forgot the 'read' part in 'accelread'
+        input_stream = BytesToByteList(test_str)
+        # We need to move over to the 'l' and add read.
+        insertion_point = test_str.find(b"l") + 1
+        for i in range(len(test_str) - insertion_point):
+            # Move cursor left.
+            input_stream.extend(Keys.LEFT_ARROW)
+        # Now, add in 'read'
+        added_str = b"read"
+        input_stream.extend(BytesToByteList(added_str))
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # First, verify that the input buffer is correct.
+        exp_input_buffer = test_str[:insertion_point] + added_str
+        exp_input_buffer += test_str[insertion_point:]
+        CheckInputBuffer(self, exp_input_buffer)
+
+        # Verify that the input buffer position is correct.
+        exp_input_buffer_pos = insertion_point + len(added_str)
+        CheckInputBufferPosition(self, exp_input_buffer_pos)
+
+        # The console output stream that we expect is the test string, followed by
+        # move cursor left until the 'l' was found, the added test string while
+        # shifting characters around.
+        exp_console_out = test_str
+        for i in range(len(test_str) - insertion_point):
+            # Move cursor left.
+            exp_console_out += OutputStream.MoveCursorLeft(1)
+
+        # Now for each character, write the rest of the line will be shifted to the
+        # right one column.
+        for i in range(len(added_str)):
+            # Printed character.
+            exp_console_out += added_str[i : i + 1]
+            # The rest of the line
+            exp_console_out += test_str[insertion_point:]
+            # Reset the cursor back left
+            reset_dist = len(test_str[insertion_point:])
+            exp_console_out += OutputStream.MoveCursorLeft(reset_dist)
+
+        # Verify the console output.
+        CheckConsoleOutput(self, exp_console_out)
+
+    def test_StoreCommandHistory(self):
+        """Verify that entered commands are stored in the history."""
+        test_commands = []
+        test_commands.append(b"help")
+        test_commands.append(b"version")
+        test_commands.append(b"accelread 0 1")
+        input_stream = []
+        for c in test_commands:
+            input_stream.extend(BytesToByteList(c))
+            input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # We expect to have the test commands in the history buffer.
+        exp_history_buf = test_commands
+        CheckHistoryBuffer(self, exp_history_buf)
+
+    def test_CycleUpThruCommandHistory(self):
+        """Verify that the UP arrow key will print itmes in the history buffer."""
+        # Enter some commands.
+        test_commands = [b"version", b"accelrange 0", b"battery", b"gettime"]
+        input_stream = []
+        for command in test_commands:
+            input_stream.extend(BytesToByteList(command))
+            input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+
+        # Now, hit the UP arrow key to print the previous entries.
+        for i in range(len(test_commands)):
+            input_stream.extend(Keys.UP_ARROW)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # The expected output should be test commands with prompts printed in
+        # between, followed by line kills with the previous test commands printed.
+        exp_console_out = b""
+        for i in range(len(test_commands)):
+            exp_console_out += test_commands[i] + b"\r\n" + self.console.prompt
+
+        # When we press up, the line should be cleared and print the previous buffer
+        # entry.
+        for i in range(len(test_commands) - 1, 0, -1):
+            exp_console_out += test_commands[i]
+            # Backspace to the beginning.
+            for i in range(len(test_commands[i])):
+                exp_console_out += BACKSPACE_STRING
+
+        # The last command should just be printed out with no backspacing.
+        exp_console_out += test_commands[0]
+
+        # Now, verify.
+        CheckConsoleOutput(self, exp_console_out)
+
+    def test_UpArrowOnEmptyHistory(self):
+        """Ensure nothing happens if the history is empty."""
+        # Press the up arrow key twice.
+        input_stream = 2 * Keys.UP_ARROW
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # We expect nothing to have happened.
+        exp_console_out = b""
+        exp_input_buffer = b""
+        exp_input_buffer_pos = 0
+        exp_history_buf = []
+
+        # Verify.
+        CheckConsoleOutput(self, exp_console_out)
+        CheckInputBufferPosition(self, exp_input_buffer_pos)
+        CheckInputBuffer(self, exp_input_buffer)
+        CheckHistoryBuffer(self, exp_history_buf)
+
+    def test_UpArrowDoesNotGoOutOfBounds(self):
+        """Verify that pressing the up arrow many times won't go out of bounds."""
+        # Enter one command.
+        test_str = b"help version"
+        input_stream = BytesToByteList(test_str)
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+        # Then press the up arrow key twice.
+        input_stream.extend(2 * Keys.UP_ARROW)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # Verify that the history buffer is correct.
+        exp_history_buf = [test_str]
+        CheckHistoryBuffer(self, exp_history_buf)
+
+        # We expect that the console output should only contain our entered command,
+        # a new prompt, and then our command aggain.
+        exp_console_out = test_str + b"\r\n" + self.console.prompt
+        # Pressing up should reprint the command we entered.
+        exp_console_out += test_str
+
+        # Verify.
+        CheckConsoleOutput(self, exp_console_out)
+
+    def test_CycleDownThruCommandHistory(self):
+        """Verify that we can select entries by hitting the down arrow."""
+        # Enter at least 4 commands.
+        test_commands = [b"version", b"accelrange 0", b"battery", b"gettime"]
+        input_stream = []
+        for command in test_commands:
+            input_stream.extend(BytesToByteList(command))
+            input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+
+        # Now, hit the UP arrow key twice to print the previous two entries.
+        for i in range(2):
+            input_stream.extend(Keys.UP_ARROW)
+
+        # Now, hit the DOWN arrow key twice to print the newer entries.
+        input_stream.extend(2 * Keys.DOWN_ARROW)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # The expected output should be commands that we entered, followed by
+        # prompts, then followed by our last two commands in reverse.  Then, we
+        # should see the last entry in the list, followed by the saved partial cmd
+        # of a blank line.
+        exp_console_out = b""
+        for i in range(len(test_commands)):
+            exp_console_out += test_commands[i] + b"\r\n" + self.console.prompt
+
+        # When we press up, the line should be cleared and print the previous buffer
+        # entry.
+        for i in range(len(test_commands) - 1, 1, -1):
+            exp_console_out += test_commands[i]
+            # Backspace to the beginning.
+            for i in range(len(test_commands[i])):
+                exp_console_out += BACKSPACE_STRING
+
+        # When we press down, it should have cleared the last command (which we
+        # covered with the previous for loop), and then prints the next command.
+        exp_console_out += test_commands[3]
+        for i in range(len(test_commands[3])):
+            exp_console_out += BACKSPACE_STRING
+
+        # Verify console output.
+        CheckConsoleOutput(self, exp_console_out)
+
+        # Verify input buffer.
+        exp_input_buffer = b""  # Empty because our partial command was empty.
+        exp_input_buffer_pos = len(exp_input_buffer)
+        CheckInputBuffer(self, exp_input_buffer)
+        CheckInputBufferPosition(self, exp_input_buffer_pos)
+
+    def test_SavingPartialCommandWhenNavigatingHistory(self):
+        """Verify that partial commands are saved when navigating history."""
+        # Enter a command.
+        test_str = b"accelinfo"
+        input_stream = BytesToByteList(test_str)
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+
+        # Enter a partial command.
+        partial_cmd = b"ver"
+        input_stream.extend(BytesToByteList(partial_cmd))
+
+        # Hit the UP arrow key.
+        input_stream.extend(Keys.UP_ARROW)
+        # Then, the DOWN arrow key.
+        input_stream.extend(Keys.DOWN_ARROW)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # The expected output should be the command we entered, a prompt, the
+        # partial command, clearing of the partial command, the command entered,
+        # clearing of the command entered, and then the partial command.
+        exp_console_out = test_str + b"\r\n" + self.console.prompt
+        exp_console_out += partial_cmd
+        for _ in range(len(partial_cmd)):
+            exp_console_out += BACKSPACE_STRING
+        exp_console_out += test_str
+        for _ in range(len(test_str)):
+            exp_console_out += BACKSPACE_STRING
+        exp_console_out += partial_cmd
+
+        # Verify console output.
+        CheckConsoleOutput(self, exp_console_out)
+
+        # Verify input buffer.
+        exp_input_buffer = partial_cmd
+        exp_input_buffer_pos = len(exp_input_buffer)
+        CheckInputBuffer(self, exp_input_buffer)
+        CheckInputBufferPosition(self, exp_input_buffer_pos)
+
+    def test_DownArrowOnEmptyHistory(self):
+        """Ensure nothing happens if the history is empty."""
+        # Then press the up down arrow twice.
+        input_stream = 2 * Keys.DOWN_ARROW
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # We expect nothing to have happened.
+        exp_console_out = b""
+        exp_input_buffer = b""
+        exp_input_buffer_pos = 0
+        exp_history_buf = []
+
+        # Verify.
+        CheckConsoleOutput(self, exp_console_out)
+        CheckInputBufferPosition(self, exp_input_buffer_pos)
+        CheckInputBuffer(self, exp_input_buffer)
+        CheckHistoryBuffer(self, exp_history_buf)
+
+    def test_DeleteCharsUsingDELKey(self):
+        """Verify that we can delete characters using the DEL key."""
+        test_str = b"version"
+        input_stream = BytesToByteList(test_str)
+
+        # Hit the left arrow key 2 times.
+        input_stream.extend(2 * Keys.LEFT_ARROW)
+
+        # Press the DEL key.
+        input_stream.extend(Keys.DEL)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # The expected output should be the command we entered, 2 individual cursor
+        # moves to the left, and then removing a char and shifting everything to the
+        # left one column.
+        exp_console_out = test_str
+        exp_console_out += 2 * OutputStream.MoveCursorLeft(1)
+
+        # Remove the char by shifting everything to the left one, slicing out the
+        # remove char.
+        exp_console_out += test_str[-1:] + b" "
+
+        # Reset the cursor by moving back 2 columns because of the 'n' and space.
+        exp_console_out += OutputStream.MoveCursorLeft(2)
+
+        # Verify console output.
+        CheckConsoleOutput(self, exp_console_out)
+
+        # Verify input buffer.  The input buffer should have the char sliced out and
+        # be positioned where the char was removed.
+        exp_input_buffer = test_str[:-2] + test_str[-1:]
+        exp_input_buffer_pos = len(exp_input_buffer) - 1
+        CheckInputBuffer(self, exp_input_buffer)
+        CheckInputBufferPosition(self, exp_input_buffer_pos)
+
+    def test_RepeatedCommandInHistory(self):
+        """Verify that we don't store 2 consecutive identical commands in history"""
+        # Enter a few commands.
+        test_commands = [b"version", b"accelrange 0", b"battery", b"gettime"]
+        # Repeat the last command.
+        test_commands.append(test_commands[len(test_commands) - 1])
+
+        input_stream = []
+        for command in test_commands:
+            input_stream.extend(BytesToByteList(command))
+            input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # Verify that the history buffer is correct.  The last command, since
+        # it was repeated, should not have been added to the history.
+        exp_history_buf = test_commands[0 : len(test_commands) - 1]
+        CheckHistoryBuffer(self, exp_history_buf)
 
-    Args:
-      mock_check: A MagicMock object replacing the CheckForEnhancedECImage()
-        method.
-    """
-    # Set the interrogation mode to always so that we actually interrogate.
-    self.console.interrogation_mode = b'always'
-
-    # First, assume that the EC interrogations indicate an enhanced EC image.
-    mock_check.return_value = True
-    # But our current knowledge of the EC image (which was actually the
-    # 'previous' EC) was a non-enhanced image.
-    self.console.enhanced_ec = False
-
-    test_command = b'sysinfo'
-    input_stream = []
-    input_stream.extend(BytesToByteList(test_command))
-
-    expected_calls = []
-    # All keystrokes to the console should be directed straight through to the
-    # EC until we press the enter key.
-    for char in test_command:
-      if six.PY3:
-        expected_calls.append(mock.call(bytes([char])))
-      else:
-        expected_calls.append(mock.call(char))
-
-    # Press the enter key.
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-    # The enter key should not be sent to the pipe since we should negotiate
-    # to an enhanced EC image.
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # At this point, we should have negotiated to enhanced.
-    self.assertTrue(self.console.enhanced_ec, msg=('Did not negotiate to '
-                                                   'enhanced EC image.'))
-
-    # The command would have been dropped however, so verify this...
-    CheckInputBuffer(self, b'')
-    CheckInputBufferPosition(self, 0)
-    # ...and repeat the command.
-    input_stream = BytesToByteList(test_command)
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Since we're enhanced now, we should have sent the entire command as one
-    # string with no trailing carriage return
-    expected_calls.append(mock.call(test_command))
-
-    # Verify all of the calls.
-    self.console.cmd_pipe.send.assert_has_calls(expected_calls)
-
-  @mock.patch('ec3po.console.Console.CheckForEnhancedECImage')
-  def test_TransitionFromEnhancedToNonEnhanced(self, mock_check):
-    """Verify that we transition correctly to non-enhanced mode.
 
-    Args:
-      mock_check: A MagicMock object replacing the CheckForEnhancedECImage()
-        method.
-    """
-    # Set the interrogation mode to always so that we actually interrogate.
-    self.console.interrogation_mode = b'always'
-
-    # First, assume that the EC interrogations indicate an non-enhanced EC
-    # image.
-    mock_check.return_value = False
-    # But our current knowledge of the EC image (which was actually the
-    # 'previous' EC) was an enhanced image.
-    self.console.enhanced_ec = True
-
-    test_command = b'sysinfo'
-    input_stream = []
-    input_stream.extend(BytesToByteList(test_command))
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # But, we will negotiate to non-enhanced however, dropping this command.
-    # Verify this.
-    self.assertFalse(self.console.enhanced_ec, msg=('Did not negotiate to'
-                                                    'non-enhanced EC image.'))
-    CheckInputBuffer(self, b'')
-    CheckInputBufferPosition(self, 0)
-
-    # The carriage return should have passed through though.
-    expected_calls = []
-    expected_calls.append(mock.call(
-        six.int2byte(console.ControlKey.CARRIAGE_RETURN)))
-
-    # Since the command was dropped, repeat the command.
-    input_stream = BytesToByteList(test_command)
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # Since we're not enhanced now, we should have sent each character in the
-    # entire command separately and a carriage return.
-    for char in test_command:
-      if six.PY3:
-        expected_calls.append(mock.call(bytes([char])))
-      else:
-        expected_calls.append(mock.call(char))
-    expected_calls.append(mock.call(
-        six.int2byte(console.ControlKey.CARRIAGE_RETURN)))
-
-    # Verify all of the calls.
-    self.console.cmd_pipe.send.assert_has_calls(expected_calls)
-
-  def test_EnhancedCheckIfTimedOut(self):
-    """Verify that the check returns false if it times out."""
-    # Make the debug pipe "time out".
-    self.console.dbg_pipe.poll.return_value = False
-    self.assertFalse(self.console.CheckForEnhancedECImage())
-
-  def test_EnhancedCheckIfACKReceived(self):
-    """Verify that the check returns true if the ACK is received."""
-    # Make the debug pipe return EC_ACK.
-    self.console.dbg_pipe.poll.return_value = True
-    self.console.dbg_pipe.recv.return_value = interpreter.EC_ACK
-    self.assertTrue(self.console.CheckForEnhancedECImage())
-
-  def test_EnhancedCheckIfWrong(self):
-    """Verify that the check returns false if byte received is wrong."""
-    # Make the debug pipe return the wrong byte.
-    self.console.dbg_pipe.poll.return_value = True
-    self.console.dbg_pipe.recv.return_value = b'\xff'
-    self.assertFalse(self.console.CheckForEnhancedECImage())
-
-  def test_EnhancedCheckUsingBuffer(self):
-    """Verify that given reboot output, enhanced EC images are detected."""
-    enhanced_output_stream = b"""
+class TestConsoleCompatibility(unittest.TestCase):
+    """Verify that console can speak to enhanced and non-enhanced EC images."""
+
+    def setUp(self):
+        """Setup the test harness."""
+        # Setup logging with a timestamp, the module, and the log level.
+        logging.basicConfig(
+            level=logging.DEBUG,
+            format=("%(asctime)s - %(module)s - %(levelname)s - %(message)s"),
+        )
+        # Create a temp file and set both the controller and peripheral PTYs to the
+        # file to create a loopback.
+        self.tempfile = tempfile.TemporaryFile()
+
+        # Mock out the pipes.
+        mock_pipe_end_0, mock_pipe_end_1 = mock.MagicMock(), mock.MagicMock()
+        self.console = console.Console(
+            self.tempfile.fileno(),
+            self.tempfile,
+            tempfile.TemporaryFile(),
+            mock_pipe_end_0,
+            mock_pipe_end_1,
+            "EC",
+        )
+
+    @mock.patch("ec3po.console.Console.CheckForEnhancedECImage")
+    def test_ActAsPassThruInNonEnhancedMode(self, mock_check):
+        """Verify we simply pass everything thru to non-enhanced ECs.
+
+        Args:
+          mock_check: A MagicMock object replacing the CheckForEnhancedECImage()
+            method.
+        """
+        # Set the interrogation mode to always so that we actually interrogate.
+        self.console.interrogation_mode = b"always"
+
+        # Assume EC interrogations indicate that the image is non-enhanced.
+        mock_check.return_value = False
+
+        # Press enter, followed by the command, and another enter.
+        input_stream = []
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+        test_command = b"version"
+        input_stream.extend(BytesToByteList(test_command))
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # Expected calls to send down the pipe would be each character of the test
+        # command.
+        expected_calls = []
+        expected_calls.append(
+            mock.call(six.int2byte(console.ControlKey.CARRIAGE_RETURN))
+        )
+        for char in test_command:
+            if six.PY3:
+                expected_calls.append(mock.call(bytes([char])))
+            else:
+                expected_calls.append(mock.call(char))
+        expected_calls.append(
+            mock.call(six.int2byte(console.ControlKey.CARRIAGE_RETURN))
+        )
+
+        # Verify that the calls happened.
+        self.console.cmd_pipe.send.assert_has_calls(expected_calls)
+
+        # Since we're acting as a pass-thru, the input buffer should be empty and
+        # input_buffer_pos is 0.
+        CheckInputBuffer(self, b"")
+        CheckInputBufferPosition(self, 0)
+
+    @mock.patch("ec3po.console.Console.CheckForEnhancedECImage")
+    def test_TransitionFromNonEnhancedToEnhanced(self, mock_check):
+        """Verify that we transition correctly to enhanced mode.
+
+        Args:
+          mock_check: A MagicMock object replacing the CheckForEnhancedECImage()
+            method.
+        """
+        # Set the interrogation mode to always so that we actually interrogate.
+        self.console.interrogation_mode = b"always"
+
+        # First, assume that the EC interrogations indicate an enhanced EC image.
+        mock_check.return_value = True
+        # But our current knowledge of the EC image (which was actually the
+        # 'previous' EC) was a non-enhanced image.
+        self.console.enhanced_ec = False
+
+        test_command = b"sysinfo"
+        input_stream = []
+        input_stream.extend(BytesToByteList(test_command))
+
+        expected_calls = []
+        # All keystrokes to the console should be directed straight through to the
+        # EC until we press the enter key.
+        for char in test_command:
+            if six.PY3:
+                expected_calls.append(mock.call(bytes([char])))
+            else:
+                expected_calls.append(mock.call(char))
+
+        # Press the enter key.
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+        # The enter key should not be sent to the pipe since we should negotiate
+        # to an enhanced EC image.
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # At this point, we should have negotiated to enhanced.
+        self.assertTrue(
+            self.console.enhanced_ec,
+            msg=("Did not negotiate to enhanced EC image."),
+        )
+
+        # The command would have been dropped however, so verify this...
+        CheckInputBuffer(self, b"")
+        CheckInputBufferPosition(self, 0)
+        # ...and repeat the command.
+        input_stream = BytesToByteList(test_command)
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # Since we're enhanced now, we should have sent the entire command as one
+        # string with no trailing carriage return
+        expected_calls.append(mock.call(test_command))
+
+        # Verify all of the calls.
+        self.console.cmd_pipe.send.assert_has_calls(expected_calls)
+
+    @mock.patch("ec3po.console.Console.CheckForEnhancedECImage")
+    def test_TransitionFromEnhancedToNonEnhanced(self, mock_check):
+        """Verify that we transition correctly to non-enhanced mode.
+
+        Args:
+          mock_check: A MagicMock object replacing the CheckForEnhancedECImage()
+            method.
+        """
+        # Set the interrogation mode to always so that we actually interrogate.
+        self.console.interrogation_mode = b"always"
+
+        # First, assume that the EC interrogations indicate an non-enhanced EC
+        # image.
+        mock_check.return_value = False
+        # But our current knowledge of the EC image (which was actually the
+        # 'previous' EC) was an enhanced image.
+        self.console.enhanced_ec = True
+
+        test_command = b"sysinfo"
+        input_stream = []
+        input_stream.extend(BytesToByteList(test_command))
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # But, we will negotiate to non-enhanced however, dropping this command.
+        # Verify this.
+        self.assertFalse(
+            self.console.enhanced_ec,
+            msg=("Did not negotiate to non-enhanced EC image."),
+        )
+        CheckInputBuffer(self, b"")
+        CheckInputBufferPosition(self, 0)
+
+        # The carriage return should have passed through though.
+        expected_calls = []
+        expected_calls.append(
+            mock.call(six.int2byte(console.ControlKey.CARRIAGE_RETURN))
+        )
+
+        # Since the command was dropped, repeat the command.
+        input_stream = BytesToByteList(test_command)
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # Since we're not enhanced now, we should have sent each character in the
+        # entire command separately and a carriage return.
+        for char in test_command:
+            if six.PY3:
+                expected_calls.append(mock.call(bytes([char])))
+            else:
+                expected_calls.append(mock.call(char))
+        expected_calls.append(
+            mock.call(six.int2byte(console.ControlKey.CARRIAGE_RETURN))
+        )
+
+        # Verify all of the calls.
+        self.console.cmd_pipe.send.assert_has_calls(expected_calls)
+
+    def test_EnhancedCheckIfTimedOut(self):
+        """Verify that the check returns false if it times out."""
+        # Make the debug pipe "time out".
+        self.console.dbg_pipe.poll.return_value = False
+        self.assertFalse(self.console.CheckForEnhancedECImage())
+
+    def test_EnhancedCheckIfACKReceived(self):
+        """Verify that the check returns true if the ACK is received."""
+        # Make the debug pipe return EC_ACK.
+        self.console.dbg_pipe.poll.return_value = True
+        self.console.dbg_pipe.recv.return_value = interpreter.EC_ACK
+        self.assertTrue(self.console.CheckForEnhancedECImage())
+
+    def test_EnhancedCheckIfWrong(self):
+        """Verify that the check returns false if byte received is wrong."""
+        # Make the debug pipe return the wrong byte.
+        self.console.dbg_pipe.poll.return_value = True
+        self.console.dbg_pipe.recv.return_value = b"\xff"
+        self.assertFalse(self.console.CheckForEnhancedECImage())
+
+    def test_EnhancedCheckUsingBuffer(self):
+        """Verify that given reboot output, enhanced EC images are detected."""
+        enhanced_output_stream = b"""
 --- UART initialized after reboot ---
 [Reset cause: reset-pin soft]
 [Image: RO, jerry_v1.1.4363-2af8572-dirty 2016-02-23 13:26:20 aaboagye@lithium.mtv.corp.google.com]
@@ -1295,19 +1350,19 @@ Enhanced Console is enabled (v1.0.0); type HELP for help.
 [0.224060 hash done 41dac382e3a6e3d2ea5b4d789c1bc46525cae7cc5ff6758f0de8d8369b506f57]
 [0.375150 POWER_GOOD seen]
 """
-    for line in enhanced_output_stream.split(b'\n'):
-      self.console.CheckBufferForEnhancedImage(line)
+        for line in enhanced_output_stream.split(b"\n"):
+            self.console.CheckBufferForEnhancedImage(line)
 
-    # Since the enhanced console string was present in the output, the console
-    # should have caught it.
-    self.assertTrue(self.console.enhanced_ec)
+        # Since the enhanced console string was present in the output, the console
+        # should have caught it.
+        self.assertTrue(self.console.enhanced_ec)
 
-    # Also should check that the command was sent to the interpreter.
-    self.console.cmd_pipe.send.assert_called_once_with(b'enhanced True')
+        # Also should check that the command was sent to the interpreter.
+        self.console.cmd_pipe.send.assert_called_once_with(b"enhanced True")
 
-    # Now test the non-enhanced EC image.
-    self.console.cmd_pipe.reset_mock()
-    non_enhanced_output_stream = b"""
+        # Now test the non-enhanced EC image.
+        self.console.cmd_pipe.reset_mock()
+        non_enhanced_output_stream = b"""
 --- UART initialized after reboot ---
 [Reset cause: reset-pin soft]
 [Image: RO, jerry_v1.1.4363-2af8572-dirty 2016-02-23 13:03:15 aaboagye@lithium.mtv.corp.google.com]
@@ -1331,239 +1386,254 @@ Console is enabled; type HELP for help.
 [0.010285 power on 2]
 [0.010385 power state 5 = S5->S3, in 0x0000]
 """
-    for line in non_enhanced_output_stream.split(b'\n'):
-      self.console.CheckBufferForEnhancedImage(line)
+        for line in non_enhanced_output_stream.split(b"\n"):
+            self.console.CheckBufferForEnhancedImage(line)
 
-    # Since the default console string is present in the output, it should be
-    # determined to be non enhanced now.
-    self.assertFalse(self.console.enhanced_ec)
+        # Since the default console string is present in the output, it should be
+        # determined to be non enhanced now.
+        self.assertFalse(self.console.enhanced_ec)
 
-    # Check that command was also sent to the interpreter.
-    self.console.cmd_pipe.send.assert_called_once_with(b'enhanced False')
+        # Check that command was also sent to the interpreter.
+        self.console.cmd_pipe.send.assert_called_once_with(b"enhanced False")
 
 
 class TestOOBMConsoleCommands(unittest.TestCase):
-  """Verify that OOBM console commands work correctly."""
-  def setUp(self):
-    """Setup the test harness."""
-    # Setup logging with a timestamp, the module, and the log level.
-    logging.basicConfig(level=logging.DEBUG,
-                        format=('%(asctime)s - %(module)s -'
-                                ' %(levelname)s - %(message)s'))
-    # Create a temp file and set both the controller and peripheral PTYs to the
-    # file to create a loopback.
-    self.tempfile = tempfile.TemporaryFile()
-
-    # Mock out the pipes.
-    mock_pipe_end_0, mock_pipe_end_1 = mock.MagicMock(), mock.MagicMock()
-    self.console = console.Console(self.tempfile.fileno(), self.tempfile,
-                                   tempfile.TemporaryFile(),
-                                   mock_pipe_end_0, mock_pipe_end_1, "EC")
-    self.console.oobm_queue = mock.MagicMock()
-
-  @mock.patch('ec3po.console.Console.CheckForEnhancedECImage')
-  def test_InterrogateCommand(self, mock_check):
-    """Verify that 'interrogate' command works as expected.
-
-    Args:
-      mock_check: A MagicMock object replacing the CheckForEnhancedECIMage()
-        method.
-    """
-    input_stream = []
-    expected_calls = []
-    mock_check.side_effect = [False]
-
-    # 'interrogate never' should disable the interrogation from happening at
-    # all.
-    cmd = b'interrogate never'
-    # Enter the OOBM prompt.
-    input_stream.extend(BytesToByteList(b'%'))
-    # Type the command
-    input_stream.extend(BytesToByteList(cmd))
-    # Press enter.
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    input_stream = []
-
-    # The OOBM queue should have been called with the command being put.
-    expected_calls.append(mock.call.put(cmd))
-    self.console.oobm_queue.assert_has_calls(expected_calls)
-
-    # Process the OOBM queue.
-    self.console.oobm_queue.get.side_effect = [cmd]
-    self.console.ProcessOOBMQueue()
-
-    # Type out a few commands.
-    input_stream.extend(BytesToByteList(b'version'))
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-    input_stream.extend(BytesToByteList(b'flashinfo'))
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-    input_stream.extend(BytesToByteList(b'sysinfo'))
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # The Check function should NOT have been called at all.
-    mock_check.assert_not_called()
-
-    # The EC image should be assumed to be not enhanced.
-    self.assertFalse(self.console.enhanced_ec, 'The image should be assumed to'
-                     ' be NOT enhanced.')
-
-    # Reset the mocks.
-    mock_check.reset_mock()
-    self.console.oobm_queue.reset_mock()
-
-    # 'interrogate auto' should not interrogate at all.  It should only be
-    # scanning the output stream for the 'console is enabled' strings.
-    cmd = b'interrogate auto'
-    # Enter the OOBM prompt.
-    input_stream.extend(BytesToByteList(b'%'))
-    # Type the command
-    input_stream.extend(BytesToByteList(cmd))
-    # Press enter.
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    input_stream = []
-    expected_calls = []
-
-    # The OOBM queue should have been called with the command being put.
-    expected_calls.append(mock.call.put(cmd))
-    self.console.oobm_queue.assert_has_calls(expected_calls)
-
-    # Process the OOBM queue.
-    self.console.oobm_queue.get.side_effect = [cmd]
-    self.console.ProcessOOBMQueue()
-
-    # Type out a few commands.
-    input_stream.extend(BytesToByteList(b'version'))
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-    input_stream.extend(BytesToByteList(b'flashinfo'))
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-    input_stream.extend(BytesToByteList(b'sysinfo'))
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # The Check function should NOT have been called at all.
-    mock_check.assert_not_called()
-
-    # The EC image should be assumed to be not enhanced.
-    self.assertFalse(self.console.enhanced_ec, 'The image should be assumed to'
-                     ' be NOT enhanced.')
-
-    # Reset the mocks.
-    mock_check.reset_mock()
-    self.console.oobm_queue.reset_mock()
-
-    # 'interrogate always' should, like its name implies, interrogate always
-    # after each press of the enter key.  This was the former way of doing
-    # interrogation.
-    cmd = b'interrogate always'
-    # Enter the OOBM prompt.
-    input_stream.extend(BytesToByteList(b'%'))
-    # Type the command
-    input_stream.extend(BytesToByteList(cmd))
-    # Press enter.
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    input_stream = []
-    expected_calls = []
-
-    # The OOBM queue should have been called with the command being put.
-    expected_calls.append(mock.call.put(cmd))
-    self.console.oobm_queue.assert_has_calls(expected_calls)
-
-    # Process the OOBM queue.
-    self.console.oobm_queue.get.side_effect = [cmd]
-    self.console.ProcessOOBMQueue()
-
-    # The Check method should be called 3 times here.
-    mock_check.side_effect = [False, False, False]
-
-    # Type out a few commands.
-    input_stream.extend(BytesToByteList(b'help list'))
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-    input_stream.extend(BytesToByteList(b'taskinfo'))
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-    input_stream.extend(BytesToByteList(b'hibdelay'))
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # The Check method should have been called 3 times here.
-    expected_calls = [mock.call(), mock.call(), mock.call()]
-    mock_check.assert_has_calls(expected_calls)
-
-    # The EC image should be assumed to be not enhanced.
-    self.assertFalse(self.console.enhanced_ec, 'The image should be assumed to'
-                     ' be NOT enhanced.')
-
-    # Now, let's try to assume that the image is enhanced while still disabling
-    # interrogation.
-    mock_check.reset_mock()
-    self.console.oobm_queue.reset_mock()
-    input_stream = []
-    cmd = b'interrogate never enhanced'
-    # Enter the OOBM prompt.
-    input_stream.extend(BytesToByteList(b'%'))
-    # Type the command
-    input_stream.extend(BytesToByteList(cmd))
-    # Press enter.
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    input_stream = []
-    expected_calls = []
-
-    # The OOBM queue should have been called with the command being put.
-    expected_calls.append(mock.call.put(cmd))
-    self.console.oobm_queue.assert_has_calls(expected_calls)
-
-    # Process the OOBM queue.
-    self.console.oobm_queue.get.side_effect = [cmd]
-    self.console.ProcessOOBMQueue()
-
-    # Type out a few commands.
-    input_stream.extend(BytesToByteList(b'chgstate'))
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-    input_stream.extend(BytesToByteList(b'hash'))
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-    input_stream.extend(BytesToByteList(b'sysjump rw'))
-    input_stream.append(console.ControlKey.CARRIAGE_RETURN)
-
-    # Send the sequence out.
-    for byte in input_stream:
-      self.console.HandleChar(byte)
-
-    # The check method should have never been called.
-    mock_check.assert_not_called()
-
-    # The EC image should be assumed to be enhanced.
-    self.assertTrue(self.console.enhanced_ec, 'The image should be'
-                    ' assumed to be enhanced.')
-
-
-if __name__ == '__main__':
-  unittest.main()
+    """Verify that OOBM console commands work correctly."""
+
+    def setUp(self):
+        """Setup the test harness."""
+        # Setup logging with a timestamp, the module, and the log level.
+        logging.basicConfig(
+            level=logging.DEBUG,
+            format=("%(asctime)s - %(module)s - %(levelname)s - %(message)s"),
+        )
+        # Create a temp file and set both the controller and peripheral PTYs to the
+        # file to create a loopback.
+        self.tempfile = tempfile.TemporaryFile()
+
+        # Mock out the pipes.
+        mock_pipe_end_0, mock_pipe_end_1 = mock.MagicMock(), mock.MagicMock()
+        self.console = console.Console(
+            self.tempfile.fileno(),
+            self.tempfile,
+            tempfile.TemporaryFile(),
+            mock_pipe_end_0,
+            mock_pipe_end_1,
+            "EC",
+        )
+        self.console.oobm_queue = mock.MagicMock()
+
+    @mock.patch("ec3po.console.Console.CheckForEnhancedECImage")
+    def test_InterrogateCommand(self, mock_check):
+        """Verify that 'interrogate' command works as expected.
+
+        Args:
+          mock_check: A MagicMock object replacing the CheckForEnhancedECIMage()
+            method.
+        """
+        input_stream = []
+        expected_calls = []
+        mock_check.side_effect = [False]
+
+        # 'interrogate never' should disable the interrogation from happening at
+        # all.
+        cmd = b"interrogate never"
+        # Enter the OOBM prompt.
+        input_stream.extend(BytesToByteList(b"%"))
+        # Type the command
+        input_stream.extend(BytesToByteList(cmd))
+        # Press enter.
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        input_stream = []
+
+        # The OOBM queue should have been called with the command being put.
+        expected_calls.append(mock.call.put(cmd))
+        self.console.oobm_queue.assert_has_calls(expected_calls)
+
+        # Process the OOBM queue.
+        self.console.oobm_queue.get.side_effect = [cmd]
+        self.console.ProcessOOBMQueue()
+
+        # Type out a few commands.
+        input_stream.extend(BytesToByteList(b"version"))
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+        input_stream.extend(BytesToByteList(b"flashinfo"))
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+        input_stream.extend(BytesToByteList(b"sysinfo"))
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # The Check function should NOT have been called at all.
+        mock_check.assert_not_called()
+
+        # The EC image should be assumed to be not enhanced.
+        self.assertFalse(
+            self.console.enhanced_ec,
+            "The image should be assumed to be NOT enhanced.",
+        )
+
+        # Reset the mocks.
+        mock_check.reset_mock()
+        self.console.oobm_queue.reset_mock()
+
+        # 'interrogate auto' should not interrogate at all.  It should only be
+        # scanning the output stream for the 'console is enabled' strings.
+        cmd = b"interrogate auto"
+        # Enter the OOBM prompt.
+        input_stream.extend(BytesToByteList(b"%"))
+        # Type the command
+        input_stream.extend(BytesToByteList(cmd))
+        # Press enter.
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        input_stream = []
+        expected_calls = []
+
+        # The OOBM queue should have been called with the command being put.
+        expected_calls.append(mock.call.put(cmd))
+        self.console.oobm_queue.assert_has_calls(expected_calls)
+
+        # Process the OOBM queue.
+        self.console.oobm_queue.get.side_effect = [cmd]
+        self.console.ProcessOOBMQueue()
+
+        # Type out a few commands.
+        input_stream.extend(BytesToByteList(b"version"))
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+        input_stream.extend(BytesToByteList(b"flashinfo"))
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+        input_stream.extend(BytesToByteList(b"sysinfo"))
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # The Check function should NOT have been called at all.
+        mock_check.assert_not_called()
+
+        # The EC image should be assumed to be not enhanced.
+        self.assertFalse(
+            self.console.enhanced_ec,
+            "The image should be assumed to be NOT enhanced.",
+        )
+
+        # Reset the mocks.
+        mock_check.reset_mock()
+        self.console.oobm_queue.reset_mock()
+
+        # 'interrogate always' should, like its name implies, interrogate always
+        # after each press of the enter key.  This was the former way of doing
+        # interrogation.
+        cmd = b"interrogate always"
+        # Enter the OOBM prompt.
+        input_stream.extend(BytesToByteList(b"%"))
+        # Type the command
+        input_stream.extend(BytesToByteList(cmd))
+        # Press enter.
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        input_stream = []
+        expected_calls = []
+
+        # The OOBM queue should have been called with the command being put.
+        expected_calls.append(mock.call.put(cmd))
+        self.console.oobm_queue.assert_has_calls(expected_calls)
+
+        # Process the OOBM queue.
+        self.console.oobm_queue.get.side_effect = [cmd]
+        self.console.ProcessOOBMQueue()
+
+        # The Check method should be called 3 times here.
+        mock_check.side_effect = [False, False, False]
+
+        # Type out a few commands.
+        input_stream.extend(BytesToByteList(b"help list"))
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+        input_stream.extend(BytesToByteList(b"taskinfo"))
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+        input_stream.extend(BytesToByteList(b"hibdelay"))
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # The Check method should have been called 3 times here.
+        expected_calls = [mock.call(), mock.call(), mock.call()]
+        mock_check.assert_has_calls(expected_calls)
+
+        # The EC image should be assumed to be not enhanced.
+        self.assertFalse(
+            self.console.enhanced_ec,
+            "The image should be assumed to be NOT enhanced.",
+        )
+
+        # Now, let's try to assume that the image is enhanced while still disabling
+        # interrogation.
+        mock_check.reset_mock()
+        self.console.oobm_queue.reset_mock()
+        input_stream = []
+        cmd = b"interrogate never enhanced"
+        # Enter the OOBM prompt.
+        input_stream.extend(BytesToByteList(b"%"))
+        # Type the command
+        input_stream.extend(BytesToByteList(cmd))
+        # Press enter.
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        input_stream = []
+        expected_calls = []
+
+        # The OOBM queue should have been called with the command being put.
+        expected_calls.append(mock.call.put(cmd))
+        self.console.oobm_queue.assert_has_calls(expected_calls)
+
+        # Process the OOBM queue.
+        self.console.oobm_queue.get.side_effect = [cmd]
+        self.console.ProcessOOBMQueue()
+
+        # Type out a few commands.
+        input_stream.extend(BytesToByteList(b"chgstate"))
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+        input_stream.extend(BytesToByteList(b"hash"))
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+        input_stream.extend(BytesToByteList(b"sysjump rw"))
+        input_stream.append(console.ControlKey.CARRIAGE_RETURN)
+
+        # Send the sequence out.
+        for byte in input_stream:
+            self.console.HandleChar(byte)
+
+        # The check method should have never been called.
+        mock_check.assert_not_called()
+
+        # The EC image should be assumed to be enhanced.
+        self.assertTrue(
+            self.console.enhanced_ec,
+            "The image should be assumed to be enhanced.",
+        )
+
+
+if __name__ == "__main__":
+    unittest.main()
diff --git a/util/ec3po/interpreter.py b/util/ec3po/interpreter.py
index 4e151083bd..8d21af247a 100644
--- a/util/ec3po/interpreter.py
+++ b/util/ec3po/interpreter.py
@@ -1,4 +1,4 @@
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -25,443 +25,457 @@ import traceback
 
 import six
 
-
 COMMAND_RETRIES = 3  # Number of attempts to retry a command.
 EC_MAX_READ = 1024  # Max bytes to read at a time from the EC.
-EC_SYN = b'\xec'  # Byte indicating EC interrogation.
-EC_ACK = b'\xc0'  # Byte representing correct EC response to interrogation.
+EC_SYN = b"\xec"  # Byte indicating EC interrogation.
+EC_ACK = b"\xc0"  # Byte representing correct EC response to interrogation.
 
 
 class LoggerAdapter(logging.LoggerAdapter):
-  """Class which provides a small adapter for the logger."""
+    """Class which provides a small adapter for the logger."""
 
-  def process(self, msg, kwargs):
-    """Prepends the served PTY to the beginning of the log message."""
-    return '%s - %s' % (self.extra['pty'], msg), kwargs
+    def process(self, msg, kwargs):
+        """Prepends the served PTY to the beginning of the log message."""
+        return "%s - %s" % (self.extra["pty"], msg), kwargs
 
 
 class Interpreter(object):
-  """Class which provides the interpretation layer between the EC and user.
-
-  This class essentially performs all of the intepretation for the EC and the
-  user.  It handles all of the automatic command retrying as well as the
-  formation of commands for EC images which support that.
-
-  Attributes:
-    logger: A logger for this module.
-    ec_uart_pty: An opened file object to the raw EC UART PTY.
-    ec_uart_pty_name: A string containing the name of the raw EC UART PTY.
-    cmd_pipe: A socket.socket or multiprocessing.Connection object which
-      represents the Interpreter side of the command pipe.  This must be a
-      bidirectional pipe.  Commands and responses will utilize this pipe.
-    dbg_pipe: A socket.socket or multiprocessing.Connection object which
-      represents the Interpreter side of the debug pipe. This must be a
-      unidirectional pipe with write capabilities.  EC debug output will utilize
-      this pipe.
-    cmd_retries: An integer representing the number of attempts the console
-      should retry commands if it receives an error.
-    log_level: An integer representing the numeric value of the log level.
-    inputs: A list of objects that the intpreter selects for reading.
-      Initially, these are the EC UART and the command pipe.
-    outputs: A list of objects that the interpreter selects for writing.
-    ec_cmd_queue: A FIFO queue used for sending commands down to the EC UART.
-    last_cmd: A string that represents the last command sent to the EC.  If an
-      error is encountered, the interpreter will attempt to retry this command
-      up to COMMAND_RETRIES.
-    enhanced_ec: A boolean indicating if the EC image that we are currently
-      communicating with is enhanced or not.  Enhanced EC images will support
-      packed commands and host commands over the UART.  This defaults to False
-      and is changed depending on the result of an interrogation.
-    interrogating: A boolean indicating if we are in the middle of interrogating
-      the EC.
-    connected: A boolean indicating if the interpreter is actually connected to
-      the UART and listening.
-  """
-  def __init__(self, ec_uart_pty, cmd_pipe, dbg_pipe, log_level=logging.INFO,
-               name=None):
-    """Intializes an Interpreter object with the provided args.
+    """Class which provides the interpretation layer between the EC and user.
 
-    Args:
-      ec_uart_pty: A string representing the EC UART to connect to.
+    This class essentially performs all of the intepretation for the EC and the
+    user.  It handles all of the automatic command retrying as well as the
+    formation of commands for EC images which support that.
+
+    Attributes:
+      logger: A logger for this module.
+      ec_uart_pty: An opened file object to the raw EC UART PTY.
+      ec_uart_pty_name: A string containing the name of the raw EC UART PTY.
       cmd_pipe: A socket.socket or multiprocessing.Connection object which
         represents the Interpreter side of the command pipe.  This must be a
         bidirectional pipe.  Commands and responses will utilize this pipe.
       dbg_pipe: A socket.socket or multiprocessing.Connection object which
         represents the Interpreter side of the debug pipe. This must be a
-        unidirectional pipe with write capabilities.  EC debug output will
-        utilize this pipe.
+        unidirectional pipe with write capabilities.  EC debug output will utilize
+        this pipe.
       cmd_retries: An integer representing the number of attempts the console
         should retry commands if it receives an error.
-      log_level: An optional integer representing the numeric value of the log
-        level.  By default, the log level will be logging.INFO (20).
-      name: the console source name
-    """
-    # Create a unique logger based on the interpreter name
-    interpreter_prefix = ('%s - ' % name) if name else ''
-    logger = logging.getLogger('%sEC3PO.Interpreter' % interpreter_prefix)
-    self.logger = LoggerAdapter(logger, {'pty': ec_uart_pty})
-    # TODO(https://crbug.com/1162189): revist the 2 TODOs below
-    # TODO(https://bugs.python.org/issue27805, python3.7+): revert to ab+
-    # TODO(https://bugs.python.org/issue20074): removing buffering=0 if/when
-    # that gets fixed, or keep two pty: one for reading and one for writing
-    self.ec_uart_pty = open(ec_uart_pty, 'r+b', buffering=0)
-    self.ec_uart_pty_name = ec_uart_pty
-    self.cmd_pipe = cmd_pipe
-    self.dbg_pipe = dbg_pipe
-    self.cmd_retries = COMMAND_RETRIES
-    self.log_level = log_level
-    self.inputs = [self.ec_uart_pty, self.cmd_pipe]
-    self.outputs = []
-    self.ec_cmd_queue = six.moves.queue.Queue()
-    self.last_cmd = b''
-    self.enhanced_ec = False
-    self.interrogating = False
-    self.connected = True
-
-  def __str__(self):
-    """Show internal state of the Interpreter object.
-
-    Returns:
-      A string that shows the values of the attributes.
-    """
-    string = []
-    string.append('%r' % self)
-    string.append('ec_uart_pty: %s' % self.ec_uart_pty)
-    string.append('cmd_pipe: %r' % self.cmd_pipe)
-    string.append('dbg_pipe: %r' % self.dbg_pipe)
-    string.append('cmd_retries: %d' % self.cmd_retries)
-    string.append('log_level: %d' % self.log_level)
-    string.append('inputs: %r' % self.inputs)
-    string.append('outputs: %r' % self.outputs)
-    string.append('ec_cmd_queue: %r' % self.ec_cmd_queue)
-    string.append('last_cmd: \'%s\'' % self.last_cmd)
-    string.append('enhanced_ec: %r' % self.enhanced_ec)
-    string.append('interrogating: %r' % self.interrogating)
-    return '\n'.join(string)
-
-  def EnqueueCmd(self, command):
-    """Enqueue a command to be sent to the EC UART.
-
-    Args:
-      command: A string which contains the command to be sent.
+      log_level: An integer representing the numeric value of the log level.
+      inputs: A list of objects that the intpreter selects for reading.
+        Initially, these are the EC UART and the command pipe.
+      outputs: A list of objects that the interpreter selects for writing.
+      ec_cmd_queue: A FIFO queue used for sending commands down to the EC UART.
+      last_cmd: A string that represents the last command sent to the EC.  If an
+        error is encountered, the interpreter will attempt to retry this command
+        up to COMMAND_RETRIES.
+      enhanced_ec: A boolean indicating if the EC image that we are currently
+        communicating with is enhanced or not.  Enhanced EC images will support
+        packed commands and host commands over the UART.  This defaults to False
+        and is changed depending on the result of an interrogation.
+      interrogating: A boolean indicating if we are in the middle of interrogating
+        the EC.
+      connected: A boolean indicating if the interpreter is actually connected to
+        the UART and listening.
     """
-    self.ec_cmd_queue.put(command)
-    self.logger.log(1, 'Commands now in queue: %d', self.ec_cmd_queue.qsize())
 
-    # Add the EC UART as an output to be serviced.
-    if self.connected and self.ec_uart_pty not in self.outputs:
-      self.outputs.append(self.ec_uart_pty)
-
-  def PackCommand(self, raw_cmd):
-    r"""Packs a command for use with error checking.
-
-    For error checking, we pack console commands in a particular format.  The
-    format is as follows:
-
-      &&[x][x][x][x]&{cmd}\n\n
-      ^ ^    ^^    ^^  ^  ^-- 2 newlines.
-      | |    ||    ||  |-- the raw console command.
-      | |    ||    ||-- 1 ampersand.
-      | |    ||____|--- 2 hex digits representing the CRC8 of cmd.
-      | |____|-- 2 hex digits reprsenting the length of cmd.
-      |-- 2 ampersands
-
-    Args:
-      raw_cmd: A pre-packed string which contains the raw command.
-
-    Returns:
-      A string which contains the packed command.
-    """
-    # Don't pack a single carriage return.
-    if raw_cmd != b'\r':
-      # The command format is as follows.
-      # &&[x][x][x][x]&{cmd}\n\n
-      packed_cmd = []
-      packed_cmd.append(b'&&')
-      # The first pair of hex digits are the length of the command.
-      packed_cmd.append(b'%02x' % len(raw_cmd))
-      # Then the CRC8 of cmd.
-      packed_cmd.append(b'%02x' % Crc8(raw_cmd))
-      packed_cmd.append(b'&')
-      # Now, the raw command followed by 2 newlines.
-      packed_cmd.append(raw_cmd)
-      packed_cmd.append(b'\n\n')
-      return b''.join(packed_cmd)
-    else:
-      return raw_cmd
-
-  def ProcessCommand(self, command):
-    """Captures the input determines what actions to take.
-
-    Args:
-      command: A string representing the command sent by the user.
-    """
-    if command == b'disconnect':
-      if self.connected:
-        self.logger.debug('UART disconnect request.')
-        # Drop all pending commands if any.
-        while not self.ec_cmd_queue.empty():
-          c = self.ec_cmd_queue.get()
-          self.logger.debug('dropped: \'%s\'', c)
-        if self.enhanced_ec:
-          # Reset retry state.
-          self.cmd_retries = COMMAND_RETRIES
-          self.last_cmd = b''
-        # Get the UART that the interpreter is attached to.
-        fileobj = self.ec_uart_pty
-        self.logger.debug('fileobj: %r', fileobj)
-        # Remove the descriptor from the inputs and outputs.
-        self.inputs.remove(fileobj)
-        if fileobj in self.outputs:
-          self.outputs.remove(fileobj)
-        self.logger.debug('Removed fileobj. Remaining inputs: %r', self.inputs)
-        # Close the file.
-        fileobj.close()
-        # Mark the interpreter as disconnected now.
-        self.connected = False
-        self.logger.debug('Disconnected from %s.', self.ec_uart_pty_name)
-      return
-
-    elif command == b'reconnect':
-      if not self.connected:
-        self.logger.debug('UART reconnect request.')
-        # Reopen the PTY.
+    def __init__(
+        self, ec_uart_pty, cmd_pipe, dbg_pipe, log_level=logging.INFO, name=None
+    ):
+        """Intializes an Interpreter object with the provided args.
+
+        Args:
+          ec_uart_pty: A string representing the EC UART to connect to.
+          cmd_pipe: A socket.socket or multiprocessing.Connection object which
+            represents the Interpreter side of the command pipe.  This must be a
+            bidirectional pipe.  Commands and responses will utilize this pipe.
+          dbg_pipe: A socket.socket or multiprocessing.Connection object which
+            represents the Interpreter side of the debug pipe. This must be a
+            unidirectional pipe with write capabilities.  EC debug output will
+            utilize this pipe.
+          cmd_retries: An integer representing the number of attempts the console
+            should retry commands if it receives an error.
+          log_level: An optional integer representing the numeric value of the log
+            level.  By default, the log level will be logging.INFO (20).
+          name: the console source name
+        """
+        # Create a unique logger based on the interpreter name
+        interpreter_prefix = ("%s - " % name) if name else ""
+        logger = logging.getLogger("%sEC3PO.Interpreter" % interpreter_prefix)
+        self.logger = LoggerAdapter(logger, {"pty": ec_uart_pty})
+        # TODO(https://crbug.com/1162189): revist the 2 TODOs below
         # TODO(https://bugs.python.org/issue27805, python3.7+): revert to ab+
         # TODO(https://bugs.python.org/issue20074): removing buffering=0 if/when
         # that gets fixed, or keep two pty: one for reading and one for writing
-        fileobj = open(self.ec_uart_pty_name, 'r+b', buffering=0)
-        self.logger.debug('fileobj: %r', fileobj)
-        self.ec_uart_pty = fileobj
-        # Add the descriptor to the inputs.
-        self.inputs.append(fileobj)
-        self.logger.debug('fileobj added. curr inputs: %r', self.inputs)
-        # Mark the interpreter as connected now.
-        self.connected = True
-        self.logger.debug('Connected to %s.', self.ec_uart_pty_name)
-      return
-
-    elif command.startswith(b'enhanced'):
-      self.enhanced_ec = command.split(b' ')[1] == b'True'
-      return
-
-    # Ignore any other commands while in the disconnected state.
-    self.logger.log(1, 'command: \'%s\'', command)
-    if not self.connected:
-      self.logger.debug('Ignoring command because currently disconnected.')
-      return
-
-    # Remove leading and trailing spaces only if this is an enhanced EC image.
-    # For non-enhanced EC images, commands will be single characters at a time
-    # and can be spaces.
-    if self.enhanced_ec:
-      command = command.strip(b' ')
-
-    # There's nothing to do if the command is empty.
-    if len(command) == 0:
-      return
-
-    # Handle log level change requests.
-    if command.startswith(b'loglevel'):
-      self.logger.debug('Log level change request.')
-      new_log_level = int(command.split(b' ')[1])
-      self.logger.logger.setLevel(new_log_level)
-      self.logger.info('Log level changed to %d.', new_log_level)
-      return
-
-    # Check for interrogation command.
-    if command == EC_SYN:
-      # User is requesting interrogation.  Send SYN as is.
-      self.logger.debug('User requesting interrogation.')
-      self.interrogating = True
-      # Assume the EC isn't enhanced until we get a response.
-      self.enhanced_ec = False
-    elif self.enhanced_ec:
-      # Enhanced EC images require the plaintext commands to be packed.
-      command = self.PackCommand(command)
-      # TODO(aaboagye): Make a dict of commands and keys and eventually,
-      # handle partial matching based on unique prefixes.
-
-    self.EnqueueCmd(command)
-
-  def HandleCmdRetries(self):
-    """Attempts to retry commands if possible."""
-    if self.cmd_retries > 0:
-      # The EC encountered an error.  We'll have to retry again.
-      self.logger.warning('Retrying command...')
-      self.cmd_retries -= 1
-      self.logger.warning('Retries remaining: %d', self.cmd_retries)
-      # Retry the command and add the EC UART to the writers again.
-      self.EnqueueCmd(self.last_cmd)
-      self.outputs.append(self.ec_uart_pty)
-    else:
-      # We're out of retries, so just give up.
-      self.logger.error('Command failed.  No retries left.')
-      # Clear the command in progress.
-      self.last_cmd = b''
-      # Reset the retry count.
-      self.cmd_retries = COMMAND_RETRIES
-
-  def SendCmdToEC(self):
-    """Sends a command to the EC."""
-    # If we're retrying a command, just try to send it again.
-    if self.cmd_retries < COMMAND_RETRIES:
-      cmd = self.last_cmd
-    else:
-      # If we're not retrying, we should not be writing to the EC if we have no
-      # items in our command queue.
-      assert not self.ec_cmd_queue.empty()
-      # Get the command to send.
-      cmd = self.ec_cmd_queue.get()
-
-    # Send the command.
-    self.ec_uart_pty.write(cmd)
-    self.ec_uart_pty.flush()
-    self.logger.log(1, 'Sent command to EC.')
-
-    if self.enhanced_ec and cmd != EC_SYN:
-      # Now, that we've sent the command, store the current command as the last
-      # command sent.  If we encounter an error string, we will attempt to retry
-      # this command.
-      if cmd != self.last_cmd:
-        self.last_cmd = cmd
-        # Reset the retry count.
+        self.ec_uart_pty = open(ec_uart_pty, "r+b", buffering=0)
+        self.ec_uart_pty_name = ec_uart_pty
+        self.cmd_pipe = cmd_pipe
+        self.dbg_pipe = dbg_pipe
         self.cmd_retries = COMMAND_RETRIES
+        self.log_level = log_level
+        self.inputs = [self.ec_uart_pty, self.cmd_pipe]
+        self.outputs = []
+        self.ec_cmd_queue = six.moves.queue.Queue()
+        self.last_cmd = b""
+        self.enhanced_ec = False
+        self.interrogating = False
+        self.connected = True
 
-    # If no command is pending to be sent, then we can remove the EC UART from
-    # writers.  Might need better checking for command retry logic in here.
-    if self.ec_cmd_queue.empty():
-      # Remove the EC UART from the writers while we wait for a response.
-      self.logger.debug('Removing EC UART from writers.')
-      self.outputs.remove(self.ec_uart_pty)
-
-  def HandleECData(self):
-    """Handle any debug prints from the EC."""
-    self.logger.log(1, 'EC has data')
-    # Read what the EC sent us.
-    data = os.read(self.ec_uart_pty.fileno(), EC_MAX_READ)
-    self.logger.log(1, 'got: \'%s\'', binascii.hexlify(data))
-    if b'&E' in data and self.enhanced_ec:
-      # We received an error, so we should retry it if possible.
-      self.logger.warning('Error string found in data.')
-      self.HandleCmdRetries()
-      return
-
-    # If we were interrogating, check the response and update our knowledge
-    # of the current EC image.
-    if self.interrogating:
-      self.enhanced_ec = data == EC_ACK
-      if self.enhanced_ec:
-        self.logger.debug('The current EC image seems enhanced.')
-      else:
-        self.logger.debug('The current EC image does NOT seem enhanced.')
-      # Done interrogating.
-      self.interrogating = False
-    # For now, just forward everything the EC sends us.
-    self.logger.log(1, 'Forwarding to user...')
-    self.dbg_pipe.send(data)
-
-  def HandleUserData(self):
-    """Handle any incoming commands from the user.
-
-    Raises:
-      EOFError: Allowed to propagate through from self.cmd_pipe.recv().
-    """
-    self.logger.log(1, 'Command data available.  Begin processing.')
-    data = self.cmd_pipe.recv()
-    # Process the command.
-    self.ProcessCommand(data)
+    def __str__(self):
+        """Show internal state of the Interpreter object.
+
+        Returns:
+          A string that shows the values of the attributes.
+        """
+        string = []
+        string.append("%r" % self)
+        string.append("ec_uart_pty: %s" % self.ec_uart_pty)
+        string.append("cmd_pipe: %r" % self.cmd_pipe)
+        string.append("dbg_pipe: %r" % self.dbg_pipe)
+        string.append("cmd_retries: %d" % self.cmd_retries)
+        string.append("log_level: %d" % self.log_level)
+        string.append("inputs: %r" % self.inputs)
+        string.append("outputs: %r" % self.outputs)
+        string.append("ec_cmd_queue: %r" % self.ec_cmd_queue)
+        string.append("last_cmd: '%s'" % self.last_cmd)
+        string.append("enhanced_ec: %r" % self.enhanced_ec)
+        string.append("interrogating: %r" % self.interrogating)
+        return "\n".join(string)
+
+    def EnqueueCmd(self, command):
+        """Enqueue a command to be sent to the EC UART.
+
+        Args:
+          command: A string which contains the command to be sent.
+        """
+        self.ec_cmd_queue.put(command)
+        self.logger.log(
+            1, "Commands now in queue: %d", self.ec_cmd_queue.qsize()
+        )
+
+        # Add the EC UART as an output to be serviced.
+        if self.connected and self.ec_uart_pty not in self.outputs:
+            self.outputs.append(self.ec_uart_pty)
+
+    def PackCommand(self, raw_cmd):
+        r"""Packs a command for use with error checking.
+
+        For error checking, we pack console commands in a particular format.  The
+        format is as follows:
+
+          &&[x][x][x][x]&{cmd}\n\n
+          ^ ^    ^^    ^^  ^  ^-- 2 newlines.
+          | |    ||    ||  |-- the raw console command.
+          | |    ||    ||-- 1 ampersand.
+          | |    ||____|--- 2 hex digits representing the CRC8 of cmd.
+          | |____|-- 2 hex digits reprsenting the length of cmd.
+          |-- 2 ampersands
+
+        Args:
+          raw_cmd: A pre-packed string which contains the raw command.
+
+        Returns:
+          A string which contains the packed command.
+        """
+        # Don't pack a single carriage return.
+        if raw_cmd != b"\r":
+            # The command format is as follows.
+            # &&[x][x][x][x]&{cmd}\n\n
+            packed_cmd = []
+            packed_cmd.append(b"&&")
+            # The first pair of hex digits are the length of the command.
+            packed_cmd.append(b"%02x" % len(raw_cmd))
+            # Then the CRC8 of cmd.
+            packed_cmd.append(b"%02x" % Crc8(raw_cmd))
+            packed_cmd.append(b"&")
+            # Now, the raw command followed by 2 newlines.
+            packed_cmd.append(raw_cmd)
+            packed_cmd.append(b"\n\n")
+            return b"".join(packed_cmd)
+        else:
+            return raw_cmd
+
+    def ProcessCommand(self, command):
+        """Captures the input determines what actions to take.
+
+        Args:
+          command: A string representing the command sent by the user.
+        """
+        if command == b"disconnect":
+            if self.connected:
+                self.logger.debug("UART disconnect request.")
+                # Drop all pending commands if any.
+                while not self.ec_cmd_queue.empty():
+                    c = self.ec_cmd_queue.get()
+                    self.logger.debug("dropped: '%s'", c)
+                if self.enhanced_ec:
+                    # Reset retry state.
+                    self.cmd_retries = COMMAND_RETRIES
+                    self.last_cmd = b""
+                # Get the UART that the interpreter is attached to.
+                fileobj = self.ec_uart_pty
+                self.logger.debug("fileobj: %r", fileobj)
+                # Remove the descriptor from the inputs and outputs.
+                self.inputs.remove(fileobj)
+                if fileobj in self.outputs:
+                    self.outputs.remove(fileobj)
+                self.logger.debug(
+                    "Removed fileobj. Remaining inputs: %r", self.inputs
+                )
+                # Close the file.
+                fileobj.close()
+                # Mark the interpreter as disconnected now.
+                self.connected = False
+                self.logger.debug(
+                    "Disconnected from %s.", self.ec_uart_pty_name
+                )
+            return
+
+        elif command == b"reconnect":
+            if not self.connected:
+                self.logger.debug("UART reconnect request.")
+                # Reopen the PTY.
+                # TODO(https://bugs.python.org/issue27805, python3.7+): revert to ab+
+                # TODO(https://bugs.python.org/issue20074): removing buffering=0 if/when
+                # that gets fixed, or keep two pty: one for reading and one for writing
+                fileobj = open(self.ec_uart_pty_name, "r+b", buffering=0)
+                self.logger.debug("fileobj: %r", fileobj)
+                self.ec_uart_pty = fileobj
+                # Add the descriptor to the inputs.
+                self.inputs.append(fileobj)
+                self.logger.debug("fileobj added. curr inputs: %r", self.inputs)
+                # Mark the interpreter as connected now.
+                self.connected = True
+                self.logger.debug("Connected to %s.", self.ec_uart_pty_name)
+            return
+
+        elif command.startswith(b"enhanced"):
+            self.enhanced_ec = command.split(b" ")[1] == b"True"
+            return
+
+        # Ignore any other commands while in the disconnected state.
+        self.logger.log(1, "command: '%s'", command)
+        if not self.connected:
+            self.logger.debug(
+                "Ignoring command because currently disconnected."
+            )
+            return
+
+        # Remove leading and trailing spaces only if this is an enhanced EC image.
+        # For non-enhanced EC images, commands will be single characters at a time
+        # and can be spaces.
+        if self.enhanced_ec:
+            command = command.strip(b" ")
+
+        # There's nothing to do if the command is empty.
+        if len(command) == 0:
+            return
+
+        # Handle log level change requests.
+        if command.startswith(b"loglevel"):
+            self.logger.debug("Log level change request.")
+            new_log_level = int(command.split(b" ")[1])
+            self.logger.logger.setLevel(new_log_level)
+            self.logger.info("Log level changed to %d.", new_log_level)
+            return
+
+        # Check for interrogation command.
+        if command == EC_SYN:
+            # User is requesting interrogation.  Send SYN as is.
+            self.logger.debug("User requesting interrogation.")
+            self.interrogating = True
+            # Assume the EC isn't enhanced until we get a response.
+            self.enhanced_ec = False
+        elif self.enhanced_ec:
+            # Enhanced EC images require the plaintext commands to be packed.
+            command = self.PackCommand(command)
+            # TODO(aaboagye): Make a dict of commands and keys and eventually,
+            # handle partial matching based on unique prefixes.
+
+        self.EnqueueCmd(command)
+
+    def HandleCmdRetries(self):
+        """Attempts to retry commands if possible."""
+        if self.cmd_retries > 0:
+            # The EC encountered an error.  We'll have to retry again.
+            self.logger.warning("Retrying command...")
+            self.cmd_retries -= 1
+            self.logger.warning("Retries remaining: %d", self.cmd_retries)
+            # Retry the command and add the EC UART to the writers again.
+            self.EnqueueCmd(self.last_cmd)
+            self.outputs.append(self.ec_uart_pty)
+        else:
+            # We're out of retries, so just give up.
+            self.logger.error("Command failed.  No retries left.")
+            # Clear the command in progress.
+            self.last_cmd = b""
+            # Reset the retry count.
+            self.cmd_retries = COMMAND_RETRIES
+
+    def SendCmdToEC(self):
+        """Sends a command to the EC."""
+        # If we're retrying a command, just try to send it again.
+        if self.cmd_retries < COMMAND_RETRIES:
+            cmd = self.last_cmd
+        else:
+            # If we're not retrying, we should not be writing to the EC if we have no
+            # items in our command queue.
+            assert not self.ec_cmd_queue.empty()
+            # Get the command to send.
+            cmd = self.ec_cmd_queue.get()
+
+        # Send the command.
+        self.ec_uart_pty.write(cmd)
+        self.ec_uart_pty.flush()
+        self.logger.log(1, "Sent command to EC.")
+
+        if self.enhanced_ec and cmd != EC_SYN:
+            # Now, that we've sent the command, store the current command as the last
+            # command sent.  If we encounter an error string, we will attempt to retry
+            # this command.
+            if cmd != self.last_cmd:
+                self.last_cmd = cmd
+                # Reset the retry count.
+                self.cmd_retries = COMMAND_RETRIES
+
+        # If no command is pending to be sent, then we can remove the EC UART from
+        # writers.  Might need better checking for command retry logic in here.
+        if self.ec_cmd_queue.empty():
+            # Remove the EC UART from the writers while we wait for a response.
+            self.logger.debug("Removing EC UART from writers.")
+            self.outputs.remove(self.ec_uart_pty)
+
+    def HandleECData(self):
+        """Handle any debug prints from the EC."""
+        self.logger.log(1, "EC has data")
+        # Read what the EC sent us.
+        data = os.read(self.ec_uart_pty.fileno(), EC_MAX_READ)
+        self.logger.log(1, "got: '%s'", binascii.hexlify(data))
+        if b"&E" in data and self.enhanced_ec:
+            # We received an error, so we should retry it if possible.
+            self.logger.warning("Error string found in data.")
+            self.HandleCmdRetries()
+            return
+
+        # If we were interrogating, check the response and update our knowledge
+        # of the current EC image.
+        if self.interrogating:
+            self.enhanced_ec = data == EC_ACK
+            if self.enhanced_ec:
+                self.logger.debug("The current EC image seems enhanced.")
+            else:
+                self.logger.debug(
+                    "The current EC image does NOT seem enhanced."
+                )
+            # Done interrogating.
+            self.interrogating = False
+        # For now, just forward everything the EC sends us.
+        self.logger.log(1, "Forwarding to user...")
+        self.dbg_pipe.send(data)
+
+    def HandleUserData(self):
+        """Handle any incoming commands from the user.
+
+        Raises:
+          EOFError: Allowed to propagate through from self.cmd_pipe.recv().
+        """
+        self.logger.log(1, "Command data available.  Begin processing.")
+        data = self.cmd_pipe.recv()
+        # Process the command.
+        self.ProcessCommand(data)
 
 
 def Crc8(data):
-  """Calculates the CRC8 of data.
+    """Calculates the CRC8 of data.
 
-  The generator polynomial used is: x^8 + x^2 + x + 1.
-  This is the same implementation that is used in the EC.
+    The generator polynomial used is: x^8 + x^2 + x + 1.
+    This is the same implementation that is used in the EC.
 
-  Args:
-    data: A string of data that we wish to calculate the CRC8 on.
+    Args:
+      data: A string of data that we wish to calculate the CRC8 on.
 
-  Returns:
-    crc >> 8: An integer representing the CRC8 value.
-  """
-  crc = 0
-  for byte in six.iterbytes(data):
-    crc ^= (byte << 8)
-    for _ in range(8):
-      if crc & 0x8000:
-        crc ^= (0x1070 << 3)
-      crc <<= 1
-  return crc >> 8
+    Returns:
+      crc >> 8: An integer representing the CRC8 value.
+    """
+    crc = 0
+    for byte in six.iterbytes(data):
+        crc ^= byte << 8
+        for _ in range(8):
+            if crc & 0x8000:
+                crc ^= 0x1070 << 3
+            crc <<= 1
+    return crc >> 8
 
 
 def StartLoop(interp, shutdown_pipe=None):
-  """Starts an infinite loop of servicing the user and the EC.
-
-  StartLoop checks to see if there are any commands to process, processing them
-  if any, and forwards EC output to the user.
-
-  When sending a command to the EC, we send the command once and check the
-  response to see if the EC encountered an error when receiving the command.  An
-  error condition is reported to the interpreter by a string with at least one
-  '&' and 'E'.  The full string is actually '&&EE', however it's possible that
-  the leading ampersand or trailing 'E' could be dropped.  If an error is
-  encountered, the interpreter will retry up to the amount configured.
-
-  Args:
-    interp: An Interpreter object that has been properly initialised.
-    shutdown_pipe: A file object for a pipe or equivalent that becomes readable
-      (not blocked) to indicate that the loop should exit.  Can be None to never
-      exit the loop.
-  """
-  try:
-    # This is used instead of "break" to avoid exiting the loop in the middle of
-    # an iteration.
-    continue_looping = True
-
-    while continue_looping:
-      # The inputs list is created anew in each loop iteration because the
-      # Interpreter class sometimes modifies the interp.inputs list.
-      if shutdown_pipe is None:
-        inputs = interp.inputs
-      else:
-        inputs = list(interp.inputs)
-        inputs.append(shutdown_pipe)
-
-      readable, writeable, _ = select.select(inputs, interp.outputs, [])
-
-      for obj in readable:
-        # Handle any debug prints from the EC.
-        if obj is interp.ec_uart_pty:
-          interp.HandleECData()
-
-        # Handle any commands from the user.
-        elif obj is interp.cmd_pipe:
-          try:
-            interp.HandleUserData()
-          except EOFError:
-            interp.logger.debug(
-                'ec3po interpreter received EOF from cmd_pipe in '
-                'HandleUserData()')
-            continue_looping = False
-
-        elif obj is shutdown_pipe:
-          interp.logger.debug(
-              'ec3po interpreter received shutdown pipe unblocked notification')
-          continue_looping = False
-
-      for obj in writeable:
-        # Send a command to the EC.
-        if obj is interp.ec_uart_pty:
-          interp.SendCmdToEC()
-
-  except KeyboardInterrupt:
-    pass
-
-  finally:
-    interp.cmd_pipe.close()
-    interp.dbg_pipe.close()
-    interp.ec_uart_pty.close()
-    if shutdown_pipe is not None:
-      shutdown_pipe.close()
-    interp.logger.debug('Exit ec3po interpreter loop for %s',
-                        interp.ec_uart_pty_name)
+    """Starts an infinite loop of servicing the user and the EC.
+
+    StartLoop checks to see if there are any commands to process, processing them
+    if any, and forwards EC output to the user.
+
+    When sending a command to the EC, we send the command once and check the
+    response to see if the EC encountered an error when receiving the command.  An
+    error condition is reported to the interpreter by a string with at least one
+    '&' and 'E'.  The full string is actually '&&EE', however it's possible that
+    the leading ampersand or trailing 'E' could be dropped.  If an error is
+    encountered, the interpreter will retry up to the amount configured.
+
+    Args:
+      interp: An Interpreter object that has been properly initialised.
+      shutdown_pipe: A file object for a pipe or equivalent that becomes readable
+        (not blocked) to indicate that the loop should exit.  Can be None to never
+        exit the loop.
+    """
+    try:
+        # This is used instead of "break" to avoid exiting the loop in the middle of
+        # an iteration.
+        continue_looping = True
+
+        while continue_looping:
+            # The inputs list is created anew in each loop iteration because the
+            # Interpreter class sometimes modifies the interp.inputs list.
+            if shutdown_pipe is None:
+                inputs = interp.inputs
+            else:
+                inputs = list(interp.inputs)
+                inputs.append(shutdown_pipe)
+
+            readable, writeable, _ = select.select(inputs, interp.outputs, [])
+
+            for obj in readable:
+                # Handle any debug prints from the EC.
+                if obj is interp.ec_uart_pty:
+                    interp.HandleECData()
+
+                # Handle any commands from the user.
+                elif obj is interp.cmd_pipe:
+                    try:
+                        interp.HandleUserData()
+                    except EOFError:
+                        interp.logger.debug(
+                            "ec3po interpreter received EOF from cmd_pipe in "
+                            "HandleUserData()"
+                        )
+                        continue_looping = False
+
+                elif obj is shutdown_pipe:
+                    interp.logger.debug(
+                        "ec3po interpreter received shutdown pipe unblocked notification"
+                    )
+                    continue_looping = False
+
+            for obj in writeable:
+                # Send a command to the EC.
+                if obj is interp.ec_uart_pty:
+                    interp.SendCmdToEC()
+
+    except KeyboardInterrupt:
+        pass
+
+    finally:
+        interp.cmd_pipe.close()
+        interp.dbg_pipe.close()
+        interp.ec_uart_pty.close()
+        if shutdown_pipe is not None:
+            shutdown_pipe.close()
+        interp.logger.debug(
+            "Exit ec3po interpreter loop for %s", interp.ec_uart_pty_name
+        )
diff --git a/util/ec3po/interpreter_unittest.py b/util/ec3po/interpreter_unittest.py
index fe4d43c351..e8f19e2e46 100755
--- a/util/ec3po/interpreter_unittest.py
+++ b/util/ec3po/interpreter_unittest.py
@@ -1,5 +1,5 @@
 #!/usr/bin/env python
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -10,371 +10,409 @@
 from __future__ import print_function
 
 import logging
-import mock
 import tempfile
 import unittest
 
+import mock  # pylint:disable=import-error
 import six
-
-from ec3po import interpreter
-from ec3po import threadproc_shim
+from ec3po import interpreter, threadproc_shim
 
 
 def GetBuiltins(func):
-  if six.PY2:
-    return '__builtin__.' + func
-  return 'builtins.' + func
+    if six.PY2:
+        return "__builtin__." + func
+    return "builtins." + func
 
 
 class TestEnhancedECBehaviour(unittest.TestCase):
-  """Test case to verify all enhanced EC interpretation tasks."""
-  def setUp(self):
-    """Setup the test harness."""
-    # Setup logging with a timestamp, the module, and the log level.
-    logging.basicConfig(level=logging.DEBUG,
-                        format=('%(asctime)s - %(module)s -'
-                                ' %(levelname)s - %(message)s'))
-
-    # Create a tempfile that would represent the EC UART PTY.
-    self.tempfile = tempfile.NamedTemporaryFile()
-
-    # Create the pipes that the interpreter will use.
-    self.cmd_pipe_user, self.cmd_pipe_itpr = threadproc_shim.Pipe()
-    self.dbg_pipe_user, self.dbg_pipe_itpr = threadproc_shim.Pipe(duplex=False)
-
-    # Mock the open() function so we can inspect reads/writes to the EC.
-    self.ec_uart_pty = mock.mock_open()
-
-    with mock.patch(GetBuiltins('open'), self.ec_uart_pty):
-      # Create an interpreter.
-      self.itpr = interpreter.Interpreter(self.tempfile.name,
-                                          self.cmd_pipe_itpr,
-                                          self.dbg_pipe_itpr,
-                                          log_level=logging.DEBUG,
-                                          name="EC")
-
-  @mock.patch('ec3po.interpreter.os')
-  def test_HandlingCommandsThatProduceNoOutput(self, mock_os):
-    """Verify that the Interpreter correctly handles non-output commands.
-
-    Args:
-      mock_os: MagicMock object replacing the 'os' module for this test
-        case.
-    """
-    # The interpreter init should open the EC UART PTY.
-    expected_ec_calls = [mock.call(self.tempfile.name, 'r+b', buffering=0)]
-    # Have a command come in the command pipe.  The first command will be an
-    # interrogation to determine if the EC is enhanced or not.
-    self.cmd_pipe_user.send(interpreter.EC_SYN)
-    self.itpr.HandleUserData()
-    # At this point, the command should be queued up waiting to be sent, so
-    # let's actually send it to the EC.
-    self.itpr.SendCmdToEC()
-    expected_ec_calls.extend([mock.call().write(interpreter.EC_SYN),
-                              mock.call().flush()])
-    # Now, assume that the EC sends only 1 response back of EC_ACK.
-    mock_os.read.side_effect = [interpreter.EC_ACK]
-    # When reading the EC, the interpreter will call file.fileno() to pass to
-    # os.read().
-    expected_ec_calls.append(mock.call().fileno())
-    # Simulate the response.
-    self.itpr.HandleECData()
-
-    # Now that the interrogation was complete, it's time to send down the real
-    # command.
-    test_cmd = b'chan save'
-    # Send the test command down the pipe.
-    self.cmd_pipe_user.send(test_cmd)
-    self.itpr.HandleUserData()
-    self.itpr.SendCmdToEC()
-    # Since the EC image is enhanced, we should have sent a packed command.
-    expected_ec_calls.append(mock.call().write(self.itpr.PackCommand(test_cmd)))
-    expected_ec_calls.append(mock.call().flush())
-
-    # Now that the first command was sent, we should send another command which
-    # produces no output.  The console would send another interrogation.
-    self.cmd_pipe_user.send(interpreter.EC_SYN)
-    self.itpr.HandleUserData()
-    self.itpr.SendCmdToEC()
-    expected_ec_calls.extend([mock.call().write(interpreter.EC_SYN),
-                              mock.call().flush()])
-    # Again, assume that the EC sends only 1 response back of EC_ACK.
-    mock_os.read.side_effect = [interpreter.EC_ACK]
-    # When reading the EC, the interpreter will call file.fileno() to pass to
-    # os.read().
-    expected_ec_calls.append(mock.call().fileno())
-    # Simulate the response.
-    self.itpr.HandleECData()
-
-    # Now send the second test command.
-    test_cmd = b'chan 0'
-    self.cmd_pipe_user.send(test_cmd)
-    self.itpr.HandleUserData()
-    self.itpr.SendCmdToEC()
-    # Since the EC image is enhanced, we should have sent a packed command.
-    expected_ec_calls.append(mock.call().write(self.itpr.PackCommand(test_cmd)))
-    expected_ec_calls.append(mock.call().flush())
-
-    # Finally, verify that the appropriate writes were actually sent to the EC.
-    self.ec_uart_pty.assert_has_calls(expected_ec_calls)
-
-  @mock.patch('ec3po.interpreter.os')
-  def test_CommandRetryingOnError(self, mock_os):
-    """Verify that commands are retried if an error is encountered.
-
-    Args:
-      mock_os: MagicMock object replacing the 'os' module for this test
-        case.
-    """
-    # The interpreter init should open the EC UART PTY.
-    expected_ec_calls = [mock.call(self.tempfile.name, 'r+b', buffering=0)]
-    # Have a command come in the command pipe.  The first command will be an
-    # interrogation to determine if the EC is enhanced or not.
-    self.cmd_pipe_user.send(interpreter.EC_SYN)
-    self.itpr.HandleUserData()
-    # At this point, the command should be queued up waiting to be sent, so
-    # let's actually send it to the EC.
-    self.itpr.SendCmdToEC()
-    expected_ec_calls.extend([mock.call().write(interpreter.EC_SYN),
-                              mock.call().flush()])
-    # Now, assume that the EC sends only 1 response back of EC_ACK.
-    mock_os.read.side_effect = [interpreter.EC_ACK]
-    # When reading the EC, the interpreter will call file.fileno() to pass to
-    # os.read().
-    expected_ec_calls.append(mock.call().fileno())
-    # Simulate the response.
-    self.itpr.HandleECData()
-
-    # Let's send a command that is received on the EC-side with an error.
-    test_cmd = b'accelinfo'
-    self.cmd_pipe_user.send(test_cmd)
-    self.itpr.HandleUserData()
-    self.itpr.SendCmdToEC()
-    packed_cmd = self.itpr.PackCommand(test_cmd)
-    expected_ec_calls.extend([mock.call().write(packed_cmd),
-                              mock.call().flush()])
-    # Have the EC return the error string twice.
-    mock_os.read.side_effect = [b'&&EE', b'&&EE']
-    for i in range(2):
-      # When reading the EC, the interpreter will call file.fileno() to pass to
-      # os.read().
-      expected_ec_calls.append(mock.call().fileno())
-      # Simulate the response.
-      self.itpr.HandleECData()
-
-      # Since an error was received, the EC should attempt to retry the command.
-      expected_ec_calls.extend([mock.call().write(packed_cmd),
-                                mock.call().flush()])
-      # Verify that the retry count was decremented.
-      self.assertEqual(interpreter.COMMAND_RETRIES-i-1, self.itpr.cmd_retries,
-                       'Unexpected cmd_remaining count.')
-      # Actually retry the command.
-      self.itpr.SendCmdToEC()
-
-    # Now assume that the last one goes through with no trouble.
-    expected_ec_calls.extend([mock.call().write(packed_cmd),
-                              mock.call().flush()])
-    self.itpr.SendCmdToEC()
-
-    # Verify all the calls.
-    self.ec_uart_pty.assert_has_calls(expected_ec_calls)
-
-  def test_PackCommandsForEnhancedEC(self):
-    """Verify that the interpreter packs commands for enhanced EC images."""
-    # Assume current EC image is enhanced.
-    self.itpr.enhanced_ec = True
-    # Receive a command from the user.
-    test_cmd = b'gettime'
-    self.cmd_pipe_user.send(test_cmd)
-    # Mock out PackCommand to see if it was called.
-    self.itpr.PackCommand = mock.MagicMock()
-    # Have the interpreter handle the command.
-    self.itpr.HandleUserData()
-    # Verify that PackCommand() was called.
-    self.itpr.PackCommand.assert_called_once_with(test_cmd)
-
-  def test_DontPackCommandsForNonEnhancedEC(self):
-    """Verify the interpreter doesn't pack commands for non-enhanced images."""
-    # Assume current EC image is not enhanced.
-    self.itpr.enhanced_ec = False
-    # Receive a command from the user.
-    test_cmd = b'gettime'
-    self.cmd_pipe_user.send(test_cmd)
-    # Mock out PackCommand to see if it was called.
-    self.itpr.PackCommand = mock.MagicMock()
-    # Have the interpreter handle the command.
-    self.itpr.HandleUserData()
-    # Verify that PackCommand() was called.
-    self.itpr.PackCommand.assert_not_called()
-
-  @mock.patch('ec3po.interpreter.os')
-  def test_KeepingTrackOfInterrogation(self, mock_os):
-    """Verify that the interpreter can track the state of the interrogation.
-
-    Args:
-      mock_os: MagicMock object replacing the 'os' module. for this test
-        case.
-    """
-    # Upon init, the interpreter should assume that the current EC image is not
-    # enhanced.
-    self.assertFalse(self.itpr.enhanced_ec, msg=('State of enhanced_ec upon'
-                                                 ' init is not False.'))
-
-    # Assume an interrogation request comes in from the user.
-    self.cmd_pipe_user.send(interpreter.EC_SYN)
-    self.itpr.HandleUserData()
-
-    # Verify the state is now within an interrogation.
-    self.assertTrue(self.itpr.interrogating, 'interrogating should be True')
-    # The state of enhanced_ec should not be changed yet because we haven't
-    # received a valid response yet.
-    self.assertFalse(self.itpr.enhanced_ec, msg=('State of enhanced_ec is '
-                                                 'not False.'))
-
-    # Assume that the EC responds with an EC_ACK.
-    mock_os.read.side_effect = [interpreter.EC_ACK]
-    self.itpr.HandleECData()
-
-    # Now, the interrogation should be complete and we should know that the
-    # current EC image is enhanced.
-    self.assertFalse(self.itpr.interrogating, msg=('interrogating should be '
-                                                   'False'))
-    self.assertTrue(self.itpr.enhanced_ec, msg='enhanced_ec sholud be True')
-
-    # Now let's perform another interrogation, but pretend that the EC ignores
-    # it.
-    self.cmd_pipe_user.send(interpreter.EC_SYN)
-    self.itpr.HandleUserData()
-
-    # Verify interrogating state.
-    self.assertTrue(self.itpr.interrogating, 'interrogating sholud be True')
-    # We should assume that the image is not enhanced until we get the valid
-    # response.
-    self.assertFalse(self.itpr.enhanced_ec, 'enhanced_ec should be False now.')
-
-    # Let's pretend that we get a random debug print.  This should clear the
-    # interrogating flag.
-    mock_os.read.side_effect = [b'[1660.593076 HC 0x103]']
-    self.itpr.HandleECData()
-
-    # Verify that interrogating flag is cleared and enhanced_ec is still False.
-    self.assertFalse(self.itpr.interrogating, 'interrogating should be False.')
-    self.assertFalse(self.itpr.enhanced_ec,
-                     'enhanced_ec should still be False.')
+    """Test case to verify all enhanced EC interpretation tasks."""
+
+    def setUp(self):
+        """Setup the test harness."""
+        # Setup logging with a timestamp, the module, and the log level.
+        logging.basicConfig(
+            level=logging.DEBUG,
+            format=("%(asctime)s - %(module)s - %(levelname)s - %(message)s"),
+        )
+
+        # Create a tempfile that would represent the EC UART PTY.
+        self.tempfile = tempfile.NamedTemporaryFile()
+
+        # Create the pipes that the interpreter will use.
+        self.cmd_pipe_user, self.cmd_pipe_itpr = threadproc_shim.Pipe()
+        self.dbg_pipe_user, self.dbg_pipe_itpr = threadproc_shim.Pipe(
+            duplex=False
+        )
+
+        # Mock the open() function so we can inspect reads/writes to the EC.
+        self.ec_uart_pty = mock.mock_open()
+
+        with mock.patch(GetBuiltins("open"), self.ec_uart_pty):
+            # Create an interpreter.
+            self.itpr = interpreter.Interpreter(
+                self.tempfile.name,
+                self.cmd_pipe_itpr,
+                self.dbg_pipe_itpr,
+                log_level=logging.DEBUG,
+                name="EC",
+            )
+
+    @mock.patch("ec3po.interpreter.os")
+    def test_HandlingCommandsThatProduceNoOutput(self, mock_os):
+        """Verify that the Interpreter correctly handles non-output commands.
+
+        Args:
+          mock_os: MagicMock object replacing the 'os' module for this test
+            case.
+        """
+        # The interpreter init should open the EC UART PTY.
+        expected_ec_calls = [mock.call(self.tempfile.name, "r+b", buffering=0)]
+        # Have a command come in the command pipe.  The first command will be an
+        # interrogation to determine if the EC is enhanced or not.
+        self.cmd_pipe_user.send(interpreter.EC_SYN)
+        self.itpr.HandleUserData()
+        # At this point, the command should be queued up waiting to be sent, so
+        # let's actually send it to the EC.
+        self.itpr.SendCmdToEC()
+        expected_ec_calls.extend(
+            [mock.call().write(interpreter.EC_SYN), mock.call().flush()]
+        )
+        # Now, assume that the EC sends only 1 response back of EC_ACK.
+        mock_os.read.side_effect = [interpreter.EC_ACK]
+        # When reading the EC, the interpreter will call file.fileno() to pass to
+        # os.read().
+        expected_ec_calls.append(mock.call().fileno())
+        # Simulate the response.
+        self.itpr.HandleECData()
+
+        # Now that the interrogation was complete, it's time to send down the real
+        # command.
+        test_cmd = b"chan save"
+        # Send the test command down the pipe.
+        self.cmd_pipe_user.send(test_cmd)
+        self.itpr.HandleUserData()
+        self.itpr.SendCmdToEC()
+        # Since the EC image is enhanced, we should have sent a packed command.
+        expected_ec_calls.append(
+            mock.call().write(self.itpr.PackCommand(test_cmd))
+        )
+        expected_ec_calls.append(mock.call().flush())
+
+        # Now that the first command was sent, we should send another command which
+        # produces no output.  The console would send another interrogation.
+        self.cmd_pipe_user.send(interpreter.EC_SYN)
+        self.itpr.HandleUserData()
+        self.itpr.SendCmdToEC()
+        expected_ec_calls.extend(
+            [mock.call().write(interpreter.EC_SYN), mock.call().flush()]
+        )
+        # Again, assume that the EC sends only 1 response back of EC_ACK.
+        mock_os.read.side_effect = [interpreter.EC_ACK]
+        # When reading the EC, the interpreter will call file.fileno() to pass to
+        # os.read().
+        expected_ec_calls.append(mock.call().fileno())
+        # Simulate the response.
+        self.itpr.HandleECData()
+
+        # Now send the second test command.
+        test_cmd = b"chan 0"
+        self.cmd_pipe_user.send(test_cmd)
+        self.itpr.HandleUserData()
+        self.itpr.SendCmdToEC()
+        # Since the EC image is enhanced, we should have sent a packed command.
+        expected_ec_calls.append(
+            mock.call().write(self.itpr.PackCommand(test_cmd))
+        )
+        expected_ec_calls.append(mock.call().flush())
+
+        # Finally, verify that the appropriate writes were actually sent to the EC.
+        self.ec_uart_pty.assert_has_calls(expected_ec_calls)
+
+    @mock.patch("ec3po.interpreter.os")
+    def test_CommandRetryingOnError(self, mock_os):
+        """Verify that commands are retried if an error is encountered.
+
+        Args:
+          mock_os: MagicMock object replacing the 'os' module for this test
+            case.
+        """
+        # The interpreter init should open the EC UART PTY.
+        expected_ec_calls = [mock.call(self.tempfile.name, "r+b", buffering=0)]
+        # Have a command come in the command pipe.  The first command will be an
+        # interrogation to determine if the EC is enhanced or not.
+        self.cmd_pipe_user.send(interpreter.EC_SYN)
+        self.itpr.HandleUserData()
+        # At this point, the command should be queued up waiting to be sent, so
+        # let's actually send it to the EC.
+        self.itpr.SendCmdToEC()
+        expected_ec_calls.extend(
+            [mock.call().write(interpreter.EC_SYN), mock.call().flush()]
+        )
+        # Now, assume that the EC sends only 1 response back of EC_ACK.
+        mock_os.read.side_effect = [interpreter.EC_ACK]
+        # When reading the EC, the interpreter will call file.fileno() to pass to
+        # os.read().
+        expected_ec_calls.append(mock.call().fileno())
+        # Simulate the response.
+        self.itpr.HandleECData()
+
+        # Let's send a command that is received on the EC-side with an error.
+        test_cmd = b"accelinfo"
+        self.cmd_pipe_user.send(test_cmd)
+        self.itpr.HandleUserData()
+        self.itpr.SendCmdToEC()
+        packed_cmd = self.itpr.PackCommand(test_cmd)
+        expected_ec_calls.extend(
+            [mock.call().write(packed_cmd), mock.call().flush()]
+        )
+        # Have the EC return the error string twice.
+        mock_os.read.side_effect = [b"&&EE", b"&&EE"]
+        for i in range(2):
+            # When reading the EC, the interpreter will call file.fileno() to pass to
+            # os.read().
+            expected_ec_calls.append(mock.call().fileno())
+            # Simulate the response.
+            self.itpr.HandleECData()
+
+            # Since an error was received, the EC should attempt to retry the command.
+            expected_ec_calls.extend(
+                [mock.call().write(packed_cmd), mock.call().flush()]
+            )
+            # Verify that the retry count was decremented.
+            self.assertEqual(
+                interpreter.COMMAND_RETRIES - i - 1,
+                self.itpr.cmd_retries,
+                "Unexpected cmd_remaining count.",
+            )
+            # Actually retry the command.
+            self.itpr.SendCmdToEC()
+
+        # Now assume that the last one goes through with no trouble.
+        expected_ec_calls.extend(
+            [mock.call().write(packed_cmd), mock.call().flush()]
+        )
+        self.itpr.SendCmdToEC()
+
+        # Verify all the calls.
+        self.ec_uart_pty.assert_has_calls(expected_ec_calls)
+
+    def test_PackCommandsForEnhancedEC(self):
+        """Verify that the interpreter packs commands for enhanced EC images."""
+        # Assume current EC image is enhanced.
+        self.itpr.enhanced_ec = True
+        # Receive a command from the user.
+        test_cmd = b"gettime"
+        self.cmd_pipe_user.send(test_cmd)
+        # Mock out PackCommand to see if it was called.
+        self.itpr.PackCommand = mock.MagicMock()
+        # Have the interpreter handle the command.
+        self.itpr.HandleUserData()
+        # Verify that PackCommand() was called.
+        self.itpr.PackCommand.assert_called_once_with(test_cmd)
+
+    def test_DontPackCommandsForNonEnhancedEC(self):
+        """Verify the interpreter doesn't pack commands for non-enhanced images."""
+        # Assume current EC image is not enhanced.
+        self.itpr.enhanced_ec = False
+        # Receive a command from the user.
+        test_cmd = b"gettime"
+        self.cmd_pipe_user.send(test_cmd)
+        # Mock out PackCommand to see if it was called.
+        self.itpr.PackCommand = mock.MagicMock()
+        # Have the interpreter handle the command.
+        self.itpr.HandleUserData()
+        # Verify that PackCommand() was called.
+        self.itpr.PackCommand.assert_not_called()
+
+    @mock.patch("ec3po.interpreter.os")
+    def test_KeepingTrackOfInterrogation(self, mock_os):
+        """Verify that the interpreter can track the state of the interrogation.
+
+        Args:
+          mock_os: MagicMock object replacing the 'os' module. for this test
+            case.
+        """
+        # Upon init, the interpreter should assume that the current EC image is not
+        # enhanced.
+        self.assertFalse(
+            self.itpr.enhanced_ec,
+            msg=("State of enhanced_ec upon init is not False."),
+        )
+
+        # Assume an interrogation request comes in from the user.
+        self.cmd_pipe_user.send(interpreter.EC_SYN)
+        self.itpr.HandleUserData()
+
+        # Verify the state is now within an interrogation.
+        self.assertTrue(self.itpr.interrogating, "interrogating should be True")
+        # The state of enhanced_ec should not be changed yet because we haven't
+        # received a valid response yet.
+        self.assertFalse(
+            self.itpr.enhanced_ec, msg=("State of enhanced_ec is not False.")
+        )
+
+        # Assume that the EC responds with an EC_ACK.
+        mock_os.read.side_effect = [interpreter.EC_ACK]
+        self.itpr.HandleECData()
+
+        # Now, the interrogation should be complete and we should know that the
+        # current EC image is enhanced.
+        self.assertFalse(
+            self.itpr.interrogating, msg=("interrogating should be False")
+        )
+        self.assertTrue(self.itpr.enhanced_ec, msg="enhanced_ec sholud be True")
+
+        # Now let's perform another interrogation, but pretend that the EC ignores
+        # it.
+        self.cmd_pipe_user.send(interpreter.EC_SYN)
+        self.itpr.HandleUserData()
+
+        # Verify interrogating state.
+        self.assertTrue(self.itpr.interrogating, "interrogating sholud be True")
+        # We should assume that the image is not enhanced until we get the valid
+        # response.
+        self.assertFalse(
+            self.itpr.enhanced_ec, "enhanced_ec should be False now."
+        )
+
+        # Let's pretend that we get a random debug print.  This should clear the
+        # interrogating flag.
+        mock_os.read.side_effect = [b"[1660.593076 HC 0x103]"]
+        self.itpr.HandleECData()
+
+        # Verify that interrogating flag is cleared and enhanced_ec is still False.
+        self.assertFalse(
+            self.itpr.interrogating, "interrogating should be False."
+        )
+        self.assertFalse(
+            self.itpr.enhanced_ec, "enhanced_ec should still be False."
+        )
 
 
 class TestUARTDisconnection(unittest.TestCase):
-  """Test case to verify interpreter disconnection/reconnection."""
-  def setUp(self):
-    """Setup the test harness."""
-    # Setup logging with a timestamp, the module, and the log level.
-    logging.basicConfig(level=logging.DEBUG,
-                        format=('%(asctime)s - %(module)s -'
-                                ' %(levelname)s - %(message)s'))
-
-    # Create a tempfile that would represent the EC UART PTY.
-    self.tempfile = tempfile.NamedTemporaryFile()
-
-    # Create the pipes that the interpreter will use.
-    self.cmd_pipe_user, self.cmd_pipe_itpr = threadproc_shim.Pipe()
-    self.dbg_pipe_user, self.dbg_pipe_itpr = threadproc_shim.Pipe(duplex=False)
-
-    # Mock the open() function so we can inspect reads/writes to the EC.
-    self.ec_uart_pty = mock.mock_open()
-
-    with mock.patch(GetBuiltins('open'), self.ec_uart_pty):
-      # Create an interpreter.
-      self.itpr = interpreter.Interpreter(self.tempfile.name,
-                                          self.cmd_pipe_itpr,
-                                          self.dbg_pipe_itpr,
-                                          log_level=logging.DEBUG,
-                                          name="EC")
-
-    # First, check that interpreter is initialized to connected.
-    self.assertTrue(self.itpr.connected, ('The interpreter should be'
-                                          ' initialized in a connected state'))
-
-  def test_DisconnectStopsECTraffic(self):
-    """Verify that when in disconnected state, no debug prints are sent."""
-    # Let's send a disconnect command through the command pipe.
-    self.cmd_pipe_user.send(b'disconnect')
-    self.itpr.HandleUserData()
-
-    # Verify interpreter is disconnected from EC.
-    self.assertFalse(self.itpr.connected, ('The interpreter should be'
-                                           'disconnected.'))
-    # Verify that the EC UART is no longer a member of the inputs.  The
-    # interpreter will never pull data from the EC if it's not a member of the
-    # inputs list.
-    self.assertFalse(self.itpr.ec_uart_pty in self.itpr.inputs)
-
-  def test_CommandsDroppedWhenDisconnected(self):
-    """Verify that when in disconnected state, commands are dropped."""
-    # Send a command, followed by 'disconnect'.
-    self.cmd_pipe_user.send(b'taskinfo')
-    self.itpr.HandleUserData()
-    self.cmd_pipe_user.send(b'disconnect')
-    self.itpr.HandleUserData()
-
-    # Verify interpreter is disconnected from EC.
-    self.assertFalse(self.itpr.connected, ('The interpreter should be'
-                                           'disconnected.'))
-    # Verify that the EC UART is no longer a member of the inputs nor outputs.
-    self.assertFalse(self.itpr.ec_uart_pty in self.itpr.inputs)
-    self.assertFalse(self.itpr.ec_uart_pty in self.itpr.outputs)
-
-    # Have the user send a few more commands in the disconnected state.
-    command = 'help\n'
-    for char in command:
-      self.cmd_pipe_user.send(char.encode('utf-8'))
-      self.itpr.HandleUserData()
-
-    # The command queue should be empty.
-    self.assertEqual(0, self.itpr.ec_cmd_queue.qsize())
-
-    # Now send the reconnect command.
-    self.cmd_pipe_user.send(b'reconnect')
-
-    with mock.patch(GetBuiltins('open'), mock.mock_open()):
-      self.itpr.HandleUserData()
-
-    # Verify interpreter is connected.
-    self.assertTrue(self.itpr.connected)
-    # Verify that EC UART is a member of the inputs.
-    self.assertTrue(self.itpr.ec_uart_pty in self.itpr.inputs)
-    # Since no command was sent after reconnection, verify that the EC UART is
-    # not a member of the outputs.
-    self.assertFalse(self.itpr.ec_uart_pty in self.itpr.outputs)
-
-  def test_ReconnectAllowsECTraffic(self):
-    """Verify that when connected, EC UART traffic is allowed."""
-    # Let's send a disconnect command through the command pipe.
-    self.cmd_pipe_user.send(b'disconnect')
-    self.itpr.HandleUserData()
-
-    # Verify interpreter is disconnected.
-    self.assertFalse(self.itpr.connected, ('The interpreter should be'
-                                           'disconnected.'))
-    # Verify that the EC UART is no longer a member of the inputs nor outputs.
-    self.assertFalse(self.itpr.ec_uart_pty in self.itpr.inputs)
-    self.assertFalse(self.itpr.ec_uart_pty in self.itpr.outputs)
-
-    # Issue reconnect command through the command pipe.
-    self.cmd_pipe_user.send(b'reconnect')
-
-    with mock.patch(GetBuiltins('open'), mock.mock_open()):
-      self.itpr.HandleUserData()
-
-    # Verify interpreter is connected.
-    self.assertTrue(self.itpr.connected, ('The interpreter should be'
-                                          'connected.'))
-    # Verify that the EC UART is now a member of the inputs.
-    self.assertTrue(self.itpr.ec_uart_pty in self.itpr.inputs)
-    # Since we have issued no commands during the disconnected state, no
-    # commands are pending and therefore the PTY should not be added to the
-    # outputs.
-    self.assertFalse(self.itpr.ec_uart_pty in self.itpr.outputs)
-
-
-if __name__ == '__main__':
-  unittest.main()
+    """Test case to verify interpreter disconnection/reconnection."""
+
+    def setUp(self):
+        """Setup the test harness."""
+        # Setup logging with a timestamp, the module, and the log level.
+        logging.basicConfig(
+            level=logging.DEBUG,
+            format=("%(asctime)s - %(module)s - %(levelname)s - %(message)s"),
+        )
+
+        # Create a tempfile that would represent the EC UART PTY.
+        self.tempfile = tempfile.NamedTemporaryFile()
+
+        # Create the pipes that the interpreter will use.
+        self.cmd_pipe_user, self.cmd_pipe_itpr = threadproc_shim.Pipe()
+        self.dbg_pipe_user, self.dbg_pipe_itpr = threadproc_shim.Pipe(
+            duplex=False
+        )
+
+        # Mock the open() function so we can inspect reads/writes to the EC.
+        self.ec_uart_pty = mock.mock_open()
+
+        with mock.patch(GetBuiltins("open"), self.ec_uart_pty):
+            # Create an interpreter.
+            self.itpr = interpreter.Interpreter(
+                self.tempfile.name,
+                self.cmd_pipe_itpr,
+                self.dbg_pipe_itpr,
+                log_level=logging.DEBUG,
+                name="EC",
+            )
+
+        # First, check that interpreter is initialized to connected.
+        self.assertTrue(
+            self.itpr.connected,
+            ("The interpreter should be initialized in a connected state"),
+        )
+
+    def test_DisconnectStopsECTraffic(self):
+        """Verify that when in disconnected state, no debug prints are sent."""
+        # Let's send a disconnect command through the command pipe.
+        self.cmd_pipe_user.send(b"disconnect")
+        self.itpr.HandleUserData()
+
+        # Verify interpreter is disconnected from EC.
+        self.assertFalse(
+            self.itpr.connected, ("The interpreter should be disconnected.")
+        )
+        # Verify that the EC UART is no longer a member of the inputs.  The
+        # interpreter will never pull data from the EC if it's not a member of the
+        # inputs list.
+        self.assertFalse(self.itpr.ec_uart_pty in self.itpr.inputs)
+
+    def test_CommandsDroppedWhenDisconnected(self):
+        """Verify that when in disconnected state, commands are dropped."""
+        # Send a command, followed by 'disconnect'.
+        self.cmd_pipe_user.send(b"taskinfo")
+        self.itpr.HandleUserData()
+        self.cmd_pipe_user.send(b"disconnect")
+        self.itpr.HandleUserData()
+
+        # Verify interpreter is disconnected from EC.
+        self.assertFalse(
+            self.itpr.connected, ("The interpreter should be disconnected.")
+        )
+        # Verify that the EC UART is no longer a member of the inputs nor outputs.
+        self.assertFalse(self.itpr.ec_uart_pty in self.itpr.inputs)
+        self.assertFalse(self.itpr.ec_uart_pty in self.itpr.outputs)
+
+        # Have the user send a few more commands in the disconnected state.
+        command = "help\n"
+        for char in command:
+            self.cmd_pipe_user.send(char.encode("utf-8"))
+            self.itpr.HandleUserData()
+
+        # The command queue should be empty.
+        self.assertEqual(0, self.itpr.ec_cmd_queue.qsize())
+
+        # Now send the reconnect command.
+        self.cmd_pipe_user.send(b"reconnect")
+
+        with mock.patch(GetBuiltins("open"), mock.mock_open()):
+            self.itpr.HandleUserData()
+
+        # Verify interpreter is connected.
+        self.assertTrue(self.itpr.connected)
+        # Verify that EC UART is a member of the inputs.
+        self.assertTrue(self.itpr.ec_uart_pty in self.itpr.inputs)
+        # Since no command was sent after reconnection, verify that the EC UART is
+        # not a member of the outputs.
+        self.assertFalse(self.itpr.ec_uart_pty in self.itpr.outputs)
+
+    def test_ReconnectAllowsECTraffic(self):
+        """Verify that when connected, EC UART traffic is allowed."""
+        # Let's send a disconnect command through the command pipe.
+        self.cmd_pipe_user.send(b"disconnect")
+        self.itpr.HandleUserData()
+
+        # Verify interpreter is disconnected.
+        self.assertFalse(
+            self.itpr.connected, ("The interpreter should be disconnected.")
+        )
+        # Verify that the EC UART is no longer a member of the inputs nor outputs.
+        self.assertFalse(self.itpr.ec_uart_pty in self.itpr.inputs)
+        self.assertFalse(self.itpr.ec_uart_pty in self.itpr.outputs)
+
+        # Issue reconnect command through the command pipe.
+        self.cmd_pipe_user.send(b"reconnect")
+
+        with mock.patch(GetBuiltins("open"), mock.mock_open()):
+            self.itpr.HandleUserData()
+
+        # Verify interpreter is connected.
+        self.assertTrue(
+            self.itpr.connected, ("The interpreter should be connected.")
+        )
+        # Verify that the EC UART is now a member of the inputs.
+        self.assertTrue(self.itpr.ec_uart_pty in self.itpr.inputs)
+        # Since we have issued no commands during the disconnected state, no
+        # commands are pending and therefore the PTY should not be added to the
+        # outputs.
+        self.assertFalse(self.itpr.ec_uart_pty in self.itpr.outputs)
+
+
+if __name__ == "__main__":
+    unittest.main()
diff --git a/util/ec3po/run_tests.sh b/util/ec3po/run_tests.sh
index ba513abe30..d61b2b428e 100755
--- a/util/ec3po/run_tests.sh
+++ b/util/ec3po/run_tests.sh
@@ -1,6 +1,6 @@
 #!/bin/bash
 #
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Copyright 2015 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/util/ec3po/threadproc_shim.py b/util/ec3po/threadproc_shim.py
index da5440b1f3..f76841dbf7 100644
--- a/util/ec3po/threadproc_shim.py
+++ b/util/ec3po/threadproc_shim.py
@@ -1,4 +1,4 @@
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -34,33 +34,34 @@ wait until after completing the TODO above to stop using multiprocessing.Pipe!
 
 # Imports to bring objects into this namespace for users of this module.
 from multiprocessing import Pipe
-from six.moves.queue import Queue
 from threading import Thread as ThreadOrProcess
 
+from six.moves.queue import Queue
+
 # True if this module has ec3po using subprocesses, False if using threads.
 USING_SUBPROCS = False
 
 
 def _DoNothing():
-  """Do-nothing function for use as a callback with DoIf()."""
+    """Do-nothing function for use as a callback with DoIf()."""
 
 
 def DoIf(subprocs=_DoNothing, threads=_DoNothing):
-  """Return a callback or not based on ec3po use of subprocesses or threads.
+    """Return a callback or not based on ec3po use of subprocesses or threads.
 
-  Args:
-    subprocs: callback that does not require any args - This will be returned
-        (not called!) if and only if ec3po is using subprocesses.  This is
-        OPTIONAL, the default value is a do-nothing callback that returns None.
-    threads: callback that does not require any args - This will be returned
-        (not called!) if and only if ec3po is using threads.  This is OPTIONAL,
-        the default value is a do-nothing callback that returns None.
+    Args:
+      subprocs: callback that does not require any args - This will be returned
+          (not called!) if and only if ec3po is using subprocesses.  This is
+          OPTIONAL, the default value is a do-nothing callback that returns None.
+      threads: callback that does not require any args - This will be returned
+          (not called!) if and only if ec3po is using threads.  This is OPTIONAL,
+          the default value is a do-nothing callback that returns None.
 
-  Returns:
-    Either the subprocs or threads argument will be returned.
-  """
-  return subprocs if USING_SUBPROCS else threads
+    Returns:
+      Either the subprocs or threads argument will be returned.
+    """
+    return subprocs if USING_SUBPROCS else threads
 
 
 def Value(ctype, *args):
-  return ctype(*args)
+    return ctype(*args)
diff --git a/util/ec_flash.c b/util/ec_flash.c
index ffa4eca4b7..ba18bb8d4c 100644
--- a/util/ec_flash.c
+++ b/util/ec_flash.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,8 +27,8 @@ int ec_flash_read(uint8_t *buf, int offset, int size)
 	for (i = 0; i < size; i += ec_max_insize) {
 		p.offset = offset + i;
 		p.size = MIN(size - i, ec_max_insize);
-		rv = ec_command(EC_CMD_FLASH_READ, 0,
-				&p, sizeof(p), ec_inbuf, p.size);
+		rv = ec_command(EC_CMD_FLASH_READ, 0, &p, sizeof(p), ec_inbuf,
+				p.size);
 		if (rv < 0) {
 			fprintf(stderr, "Read error at offset %d\n", i);
 			return rv;
@@ -58,7 +58,8 @@ int ec_flash_verify(const uint8_t *buf, int offset, int size)
 
 	for (i = 0; i < size; i++) {
 		if (buf[i] != rbuf[i]) {
-			fprintf(stderr, "Mismatch at offset 0x%x: "
+			fprintf(stderr,
+				"Mismatch at offset 0x%x: "
 				"want 0x%02x, got 0x%02x\n",
 				i, buf[i], rbuf[i]);
 			free(rbuf);
@@ -76,12 +77,15 @@ int ec_flash_verify(const uint8_t *buf, int offset, int size)
  */
 static int get_flash_info_v2(struct ec_response_flash_info_2 *info_response)
 {
-	struct ec_params_flash_info_2 info_params = {
-		/*
-		 * By setting this to zero we indicate that we don't care
-		 * about getting the bank description in the response.
-		 */
-		.num_banks_desc = 0
+	struct ec_params_flash_info_2 info_params = { /*
+						       * By setting this to zero
+						       * we indicate that we
+						       * don't care about
+						       * getting the bank
+						       * description in the
+						       * response.
+						       */
+						      .num_banks_desc = 0
 	};
 
 	return ec_command(EC_CMD_FLASH_INFO, 2, &info_params,
diff --git a/util/ec_flash.h b/util/ec_flash.h
index f4aea3b7a3..179df1979b 100644
--- a/util/ec_flash.h
+++ b/util/ec_flash.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/util/ec_openocd.py b/util/ec_openocd.py
index a84c00643c..e0a15bd08b 100755
--- a/util/ec_openocd.py
+++ b/util/ec_openocd.py
@@ -1,6 +1,6 @@
 #!/usr/bin/env python3
 
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -16,6 +16,7 @@ import time
 Flashes and debugs the EC through openocd
 """
 
+
 @dataclasses.dataclass
 class BoardInfo:
     gdb_variant: str
@@ -24,9 +25,7 @@ class BoardInfo:
 
 
 # Debuggers for each board, OpenOCD currently only supports GDB
-boards = {
-    "skyrim": BoardInfo("arm-none-eabi-gdb", 6, 4)
-}
+boards = {"skyrim": BoardInfo("arm-none-eabi-gdb", 6, 4)}
 
 
 def create_openocd_args(interface, board):
@@ -36,9 +35,12 @@ def create_openocd_args(interface, board):
     board_info = boards[board]
     args = [
         "openocd",
-        "-f", f"interface/{interface}.cfg",
-        "-c", "add_script_search_dir openocd",
-        "-f", f"board/{board}.cfg",
+        "-f",
+        f"interface/{interface}.cfg",
+        "-c",
+        "add_script_search_dir openocd",
+        "-f",
+        f"board/{board}.cfg",
     ]
 
     return args
@@ -53,11 +55,13 @@ def create_gdb_args(board, port, executable):
         board_info.gdb_variant,
         executable,
         # GDB can't autodetect these according to OpenOCD
-        "-ex", f"set remote hardware-breakpoint-limit {board_info.num_breakpoints}",
-        "-ex", f"set remote hardware-watchpoint-limit {board_info.num_watchpoints}",
-
+        "-ex",
+        f"set remote hardware-breakpoint-limit {board_info.num_breakpoints}",
+        "-ex",
+        f"set remote hardware-watchpoint-limit {board_info.num_watchpoints}",
         # Connect to OpenOCD
-        "-ex", f"target extended-remote localhost:{port}",
+        "-ex",
+        f"target extended-remote localhost:{port}",
     ]
 
     return args
@@ -79,7 +83,10 @@ def debug(interface, board, port, executable):
     openocd_args += ["-c", f"gdb_port {port}"]
 
     openocd = subprocess.Popen(
-        openocd_args, encoding="utf-8", stdout=subprocess.PIPE, stderr=subprocess.STDOUT
+        openocd_args,
+        encoding="utf-8",
+        stdout=subprocess.PIPE,
+        stderr=subprocess.STDOUT,
     )
 
     # Wait for OpenOCD to start, it'll open a port for GDB connections
@@ -134,7 +141,7 @@ def get_flash_file(board):
         / "zephyr"
         / board
         / "output"
-        / "zephyr.bin"
+        / "ec.bin"
     ).resolve()
 
 
@@ -209,11 +216,15 @@ def main():
         target_file = args.file.resolve()
 
     if args.command == "flash":
-        image_file = get_flash_file(args.board) if target_file == None else target_file
+        image_file = (
+            get_flash_file(args.board) if target_file == None else target_file
+        )
         flash(args.interface, args.board, image_file, args.verify)
     elif args.command == "debug":
         executable_file = (
-            get_executable_file(args.board) if target_file == None else target_file
+            get_executable_file(args.board)
+            if target_file == None
+            else target_file
         )
         debug(args.interface, args.board, args.port, executable_file)
     else:
diff --git a/util/ec_panicinfo.c b/util/ec_panicinfo.c
index 0294ac90de..0aa412bfe1 100644
--- a/util/ec_panicinfo.c
+++ b/util/ec_panicinfo.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,11 +12,10 @@
 
 static void print_panic_reg(int regnum, const uint32_t *regs, int index)
 {
-	static const char * const regname[] = {
-		"r0 ", "r1 ", "r2 ", "r3 ", "r4 ",
-		"r5 ", "r6 ", "r7 ", "r8 ", "r9 ",
-		"r10", "r11", "r12", "sp ", "lr ",
-		"pc "};
+	static const char *const regname[] = { "r0 ", "r1 ", "r2 ", "r3 ",
+					       "r4 ", "r5 ", "r6 ", "r7 ",
+					       "r8 ", "r9 ", "r10", "r11",
+					       "r12", "sp ", "lr ", "pc " };
 
 	printf("%s:", regname[regnum]);
 	if (regs)
@@ -56,14 +55,15 @@ static int parse_panic_info_cm(const struct panic_data *pdata)
 		ORIG_HANDLER
 	} origin = ORIG_UNKNOWN;
 	int i;
-	const char *panic_origins[3] = {"", "PROCESS", "HANDLER"};
+	const char *panic_origins[3] = { "", "PROCESS", "HANDLER" };
 
 	printf("Saved panic data:%s\n",
 	       (pdata->flags & PANIC_DATA_FLAG_OLD_HOSTCMD ? "" : " (NEW)"));
 
 	if (pdata->struct_version == 2)
 		origin = ((lregs[11] & 0xf) == 1 || (lregs[11] & 0xf) == 9) ?
-			 ORIG_HANDLER : ORIG_PROCESS;
+				 ORIG_HANDLER :
+				 ORIG_PROCESS;
 
 	/*
 	 * In pdata struct, 'regs', which is allocated before 'frame', has
@@ -75,8 +75,7 @@ static int parse_panic_info_cm(const struct panic_data *pdata)
 		sregs = pdata->cm.frame - (pdata->struct_version == 1 ? 1 : 0);
 
 	printf("=== %s EXCEPTION: %02x ====== xPSR: %08x ===\n",
-	       panic_origins[origin],
-	       lregs[1] & 0xff, sregs ? sregs[7] : -1);
+	       panic_origins[origin], lregs[1] & 0xff, sregs ? sregs[7] : -1);
 	for (i = 0; i < 4; ++i)
 		print_panic_reg(i, sregs, i);
 	for (i = 4; i < 10; ++i)
@@ -104,14 +103,14 @@ static int parse_panic_info_nds32(const struct panic_data *pdata)
 	       (pdata->flags & PANIC_DATA_FLAG_OLD_HOSTCMD ? "" : " (NEW)"));
 
 	printf("=== EXCEP: ITYPE=%x ===\n", itype);
-	printf("R0  %08x R1  %08x R2  %08x R3  %08x\n",
-		     regs[0], regs[1], regs[2], regs[3]);
-	printf("R4  %08x R5  %08x R6  %08x R7  %08x\n",
-		     regs[4], regs[5], regs[6], regs[7]);
-	printf("R8  %08x R9  %08x R10 %08x R15 %08x\n",
-		     regs[8], regs[9], regs[10], regs[11]);
-	printf("FP  %08x GP  %08x LP  %08x SP  %08x\n",
-		     regs[12], regs[13], regs[14], regs[15]);
+	printf("R0  %08x R1  %08x R2  %08x R3  %08x\n", regs[0], regs[1],
+	       regs[2], regs[3]);
+	printf("R4  %08x R5  %08x R6  %08x R7  %08x\n", regs[4], regs[5],
+	       regs[6], regs[7]);
+	printf("R8  %08x R9  %08x R10 %08x R15 %08x\n", regs[8], regs[9],
+	       regs[10], regs[11]);
+	printf("FP  %08x GP  %08x LP  %08x SP  %08x\n", regs[12], regs[13],
+	       regs[14], regs[15]);
 	printf("IPC %08x IPSW   %05x\n", ipc, ipsw);
 	printf("SWID of ITYPE: %x\n", ((itype >> 16) & 0x7fff));
 
@@ -127,22 +126,22 @@ static int parse_panic_info_rv32i(const struct panic_data *pdata)
 	mepc = pdata->riscv.mepc;
 
 	printf("=== EXCEPTION: MCAUSE=%x ===\n", mcause);
-	printf("S11 %08x S10 %08x  S9 %08x  S8   %08x\n",
-	       regs[0], regs[1], regs[2], regs[3]);
-	printf("S7  %08x S6  %08x  S5 %08x  S4   %08x\n",
-	       regs[4], regs[5], regs[6], regs[7]);
-	printf("S3  %08x S2  %08x  S1 %08x  S0   %08x\n",
-	       regs[8], regs[9], regs[10], regs[11]);
-	printf("T6  %08x T5  %08x  T4 %08x  T3   %08x\n",
-	       regs[12], regs[13], regs[14], regs[15]);
-	printf("T2  %08x T1  %08x  T0 %08x  A7   %08x\n",
-	       regs[16], regs[17], regs[18], regs[19]);
-	printf("A6  %08x A5  %08x  A4 %08x  A3   %08x\n",
-	       regs[20], regs[21], regs[22], regs[23]);
-	printf("A2  %08x A1  %08x  A0 %08x  TP   %08x\n",
-	       regs[24], regs[25], regs[26], regs[27]);
-	printf("GP  %08x RA  %08x  SP %08x  MEPC %08x\n",
-	       regs[28], regs[29], regs[30], mepc);
+	printf("S11 %08x S10 %08x  S9 %08x  S8   %08x\n", regs[0], regs[1],
+	       regs[2], regs[3]);
+	printf("S7  %08x S6  %08x  S5 %08x  S4   %08x\n", regs[4], regs[5],
+	       regs[6], regs[7]);
+	printf("S3  %08x S2  %08x  S1 %08x  S0   %08x\n", regs[8], regs[9],
+	       regs[10], regs[11]);
+	printf("T6  %08x T5  %08x  T4 %08x  T3   %08x\n", regs[12], regs[13],
+	       regs[14], regs[15]);
+	printf("T2  %08x T1  %08x  T0 %08x  A7   %08x\n", regs[16], regs[17],
+	       regs[18], regs[19]);
+	printf("A6  %08x A5  %08x  A4 %08x  A3   %08x\n", regs[20], regs[21],
+	       regs[22], regs[23]);
+	printf("A2  %08x A1  %08x  A0 %08x  TP   %08x\n", regs[24], regs[25],
+	       regs[26], regs[27]);
+	printf("GP  %08x RA  %08x  SP %08x  MEPC %08x\n", regs[28], regs[29],
+	       regs[30], mepc);
 
 	return 0;
 }
@@ -153,7 +152,7 @@ int parse_panic_info(const char *data, size_t size)
 	const size_t header_size = 4;
 	/* Size of the panic information "trailer" (struct_size and magic). */
 	const size_t trailer_size = sizeof(struct panic_data) -
-				 offsetof(struct panic_data, struct_size);
+				    offsetof(struct panic_data, struct_size);
 
 	struct panic_data pdata = { 0 };
 	size_t copy_size;
@@ -164,7 +163,8 @@ int parse_panic_info(const char *data, size_t size)
 	}
 
 	if (size > sizeof(pdata)) {
-		fprintf(stderr, "WARNING: Panic data too large (%zd > %zd). "
+		fprintf(stderr,
+			"WARNING: Panic data too large (%zd > %zd). "
 			"Following data may be incorrect!\n",
 			size, sizeof(pdata));
 		copy_size = sizeof(pdata);
@@ -175,20 +175,22 @@ int parse_panic_info(const char *data, size_t size)
 	memcpy(&pdata, data, copy_size);
 	/* Then copy the trailer in position. */
 	memcpy((char *)&pdata + (sizeof(struct panic_data) - trailer_size),
-		data + (size - trailer_size), trailer_size);
+	       data + (size - trailer_size), trailer_size);
 
 	/*
 	 * We only understand panic data with version <= 2. Warn the user
 	 * of higher versions.
 	 */
 	if (pdata.struct_version > 2)
-		fprintf(stderr, "WARNING: Unknown panic data version (%d). "
+		fprintf(stderr,
+			"WARNING: Unknown panic data version (%d). "
 			"Following data may be incorrect!\n",
 			pdata.struct_version);
 
 	/* Validate magic number */
 	if (pdata.magic != PANIC_DATA_MAGIC)
-		fprintf(stderr, "WARNING: Incorrect panic magic (%d). "
+		fprintf(stderr,
+			"WARNING: Incorrect panic magic (%d). "
 			"Following data may be incorrect!\n",
 			pdata.magic);
 
diff --git a/util/ec_panicinfo.h b/util/ec_panicinfo.h
index c61cf797e6..0d7dba79f5 100644
--- a/util/ec_panicinfo.h
+++ b/util/ec_panicinfo.h
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/util/ec_parse_panicinfo.c b/util/ec_parse_panicinfo.c
index 3a2da4590a..33c904b512 100644
--- a/util/ec_parse_panicinfo.c
+++ b/util/ec_parse_panicinfo.c
@@ -1,4 +1,4 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -20,7 +20,7 @@ int main(int argc, char *argv[])
 	size_t size = 0;
 	size_t read;
 
-	BUILD_ASSERT(sizeof(pdata) > sizeof(struct panic_data)*2);
+	BUILD_ASSERT(sizeof(pdata) > sizeof(struct panic_data) * 2);
 
 	/*
 	 * Provide a minimal help message.
@@ -36,7 +36,7 @@ int main(int argc, char *argv[])
 	}
 
 	while (1) {
-		read = fread(&pdata[size], 1, sizeof(pdata)-size, stdin);
+		read = fread(&pdata[size], 1, sizeof(pdata) - size, stdin);
 		if (read < 0) {
 			fprintf(stderr, "Cannot read panicinfo from stdin.\n");
 			return 1;
diff --git a/util/ec_sb_firmware_update.c b/util/ec_sb_firmware_update.c
index a959cd6fe9..a2fb70d2a3 100644
--- a/util/ec_sb_firmware_update.c
+++ b/util/ec_sb_firmware_update.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,8 +21,8 @@
 /* Subcommands: [check|update] */
 enum {
 	OP_UNKNOWN = 0,
-	OP_CHECK   = 1,
-	OP_UPDATE  = 2,
+	OP_CHECK = 1,
+	OP_UPDATE = 2,
 };
 
 struct delay_value {
@@ -33,54 +33,50 @@ struct delay_value {
 /* Default retry counter on errors */
 #define SB_FW_UPDATE_DEFAULT_RETRY_CNT 3
 /* Default delay value */
-#define SB_FW_UPDATE_DEFAULT_DELAY  1000
+#define SB_FW_UPDATE_DEFAULT_DELAY 1000
 
-#define DELAY_US_BEGIN  500000
-#define DELAY_US_END   1000000
-#define DELAY_US_BUSY  1000000
-#define DELAY_US_WRITE_END  50000
+#define DELAY_US_BEGIN 500000
+#define DELAY_US_END 1000000
+#define DELAY_US_BUSY 1000000
+#define DELAY_US_WRITE_END 50000
 
 static struct delay_value sb_delays[] = {
-	{1,             100000},
-	{2,            9000000},
-	{4,             100000},
-	{771,            30000},
-	{2200,           10000},
-	{0xFFFFFF,       50000},
+	{ 1, 100000 },	{ 2, 9000000 },	 { 4, 100000 },
+	{ 771, 30000 }, { 2200, 10000 }, { 0xFFFFFF, 50000 },
 };
 
 enum fw_update_state {
-	S0_READ_STATUS   = 0,
-	S1_READ_INFO     = 1,
+	S0_READ_STATUS = 0,
+	S1_READ_INFO = 1,
 	S2_WRITE_PREPARE = 2,
-	S3_READ_STATUS   = 3,
-	S4_WRITE_UPDATE  = 4,
-	S5_READ_STATUS   = 5,
-	S6_WRITE_BLOCK   = 6,
-	S7_READ_STATUS   = 7,
-	S8_WRITE_END     = 8,
-	S9_READ_STATUS   = 9,
-	S10_TERMINAL     = 10
+	S3_READ_STATUS = 3,
+	S4_WRITE_UPDATE = 4,
+	S5_READ_STATUS = 5,
+	S6_WRITE_BLOCK = 6,
+	S7_READ_STATUS = 7,
+	S8_WRITE_END = 8,
+	S9_READ_STATUS = 9,
+	S10_TERMINAL = 10
 };
 
 #define MAX_FW_IMAGE_NAME_SIZE 80
 
 /* Firmware Update Control Flags */
 enum {
-	F_AC_PRESENT    = 0x1, /* AC Present */
+	F_AC_PRESENT = 0x1, /* AC Present */
 	F_VERSION_CHECK = 0x2, /* do firmware version check */
-	F_UPDATE        = 0x4, /* do firmware update */
-	F_NEED_UPDATE   = 0x8,  /* need firmware update */
-	F_POWERD_DISABLED = 0x10,  /* powerd is disabled */
-	F_LFCC_ZERO =       0x20,  /* last full charge is zero */
-	F_BATT_DISCHARGE =  0x40   /* battery discharging */
+	F_UPDATE = 0x4, /* do firmware update */
+	F_NEED_UPDATE = 0x8, /* need firmware update */
+	F_POWERD_DISABLED = 0x10, /* powerd is disabled */
+	F_LFCC_ZERO = 0x20, /* last full charge is zero */
+	F_BATT_DISCHARGE = 0x40 /* battery discharging */
 };
 
 struct fw_update_ctrl {
 	uint32_t flags; /* fw update control flags */
-	int size;    /* size of battery firmware image */
-	char *ptr;   /* current read pointer of the firmware image */
-	int  offset; /* current block write offset */
+	int size; /* size of battery firmware image */
+	char *ptr; /* current read pointer of the firmware image */
+	int offset; /* current block write offset */
 	struct sb_fw_header *fw_img_hdr; /*pointer to firmware image header*/
 	struct sb_fw_update_status status;
 	struct sb_fw_update_info info;
@@ -106,76 +102,59 @@ static uint32_t get_delay_value(uint32_t offset, uint32_t step_size)
 		if (offset <= sb_delays[i].steps * step_size)
 			return sb_delays[i].value;
 	}
-	return sb_delays[sz-1].value;
+	return sb_delays[sz - 1].value;
 }
 
-static void print_battery_firmware_image_hdr(
-	struct sb_fw_header *hdr)
+static void print_battery_firmware_image_hdr(struct sb_fw_header *hdr)
 {
 	printf("Latest Battery Firmware:\n");
-	printf("\t%c%c%c%c hdr_ver:%04x major_minor:%04x\n",
-		hdr->signature[0],
-		hdr->signature[1],
-		hdr->signature[2],
-		hdr->signature[3],
-		hdr->hdr_version, hdr->pkg_version_major_minor);
+	printf("\t%c%c%c%c hdr_ver:%04x major_minor:%04x\n", hdr->signature[0],
+	       hdr->signature[1], hdr->signature[2], hdr->signature[3],
+	       hdr->hdr_version, hdr->pkg_version_major_minor);
 
 	printf("\tmaker:0x%04x hwid:0x%04x fw_ver:0x%04x tbl_ver:0x%04x\n",
-		hdr->vendor_id, hdr->battery_type, hdr->fw_version,
-		hdr->data_table_version);
+	       hdr->vendor_id, hdr->battery_type, hdr->fw_version,
+	       hdr->data_table_version);
 
 	printf("\tbinary offset:0x%08x size:0x%08x chk_sum:0x%02x\n",
-		hdr->fw_binary_offset, hdr->fw_binary_size, hdr->checksum);
+	       hdr->fw_binary_offset, hdr->fw_binary_size, hdr->checksum);
 }
 
 static void print_info(struct sb_fw_update_info *info)
 {
 	printf("\nCurrent Battery Firmware:\n");
 	printf("\tmaker:0x%04x hwid:0x%04x fw_ver:0x%04x tbl_ver:0x%04x\n",
-		info->maker_id,
-		info->hardware_id,
-		info->fw_version,
-		info->data_version);
+	       info->maker_id, info->hardware_id, info->fw_version,
+	       info->data_version);
 	return;
 }
 
 static void print_status(struct sb_fw_update_status *sts)
 {
 	printf("f_maker_id:%d f_hw_id:%d f_fw_ver:%d f_permnent:%d\n",
-		sts->v_fail_maker_id,
-		sts->v_fail_hw_id,
-		sts->v_fail_fw_version,
-		sts->v_fail_permanent);
+	       sts->v_fail_maker_id, sts->v_fail_hw_id, sts->v_fail_fw_version,
+	       sts->v_fail_permanent);
 	printf("permanent failure:%d abnormal:%d fw_update:%d\n",
-		sts->permanent_failure,
-		sts->abnormal_condition,
-		sts->fw_update_supported);
+	       sts->permanent_failure, sts->abnormal_condition,
+	       sts->fw_update_supported);
 	printf("fw_update_mode:%d fw_corrupted:%d cmd_reject:%d\n",
-		sts->fw_update_mode,
-		sts->fw_corrupted,
-		sts->cmd_reject);
+	       sts->fw_update_mode, sts->fw_corrupted, sts->cmd_reject);
 	printf("invliad data:%d fw_fatal_err:%d fec_err:%d busy:%d\n",
-		sts->invalid_data,
-		sts->fw_fatal_error,
-		sts->fec_error,
-		sts->busy);
+	       sts->invalid_data, sts->fw_fatal_error, sts->fec_error,
+	       sts->busy);
 	printf("\n");
 	return;
 }
 
 /* @return 1 (True) if img signature is valid */
-static int check_battery_firmware_image_signature(
-	struct sb_fw_header *hdr)
+static int check_battery_firmware_image_signature(struct sb_fw_header *hdr)
 {
-	return (hdr->signature[0] == 'B') &&
-		(hdr->signature[1] == 'T') &&
-		(hdr->signature[2] == 'F') &&
-		(hdr->signature[3] == 'W');
+	return (hdr->signature[0] == 'B') && (hdr->signature[1] == 'T') &&
+	       (hdr->signature[2] == 'F') && (hdr->signature[3] == 'W');
 }
 
 /* @return 1 (True) if img checksum is valid. */
-static int check_battery_firmware_image_checksum(
-	struct sb_fw_header *hdr)
+static int check_battery_firmware_image_checksum(struct sb_fw_header *hdr)
 {
 	int i;
 	uint8_t sum = 0;
@@ -189,22 +168,19 @@ static int check_battery_firmware_image_checksum(
 }
 
 /* @return 1 (True) if img versions are ok to update. */
-static int check_battery_firmware_image_version(
-	struct sb_fw_header *hdr,
-	struct sb_fw_update_info *p)
+static int check_battery_firmware_image_version(struct sb_fw_header *hdr,
+						struct sb_fw_update_info *p)
 {
 	/*
 	 * If the battery firmware has a newer fw version
 	 * or a newer data table version, then it is ok to update.
 	 */
-	return (hdr->fw_version > p->fw_version)
-		|| (hdr->data_table_version > p->data_version);
+	return (hdr->fw_version > p->fw_version) ||
+	       (hdr->data_table_version > p->data_version);
 }
 
-
-static int check_battery_firmware_ids(
-	struct sb_fw_header *hdr,
-	struct sb_fw_update_info *p)
+static int check_battery_firmware_ids(struct sb_fw_header *hdr,
+				      struct sb_fw_update_info *p)
 {
 	return ((hdr->vendor_id == p->maker_id) &&
 		(hdr->battery_type == p->hardware_id));
@@ -213,33 +189,30 @@ static int check_battery_firmware_ids(
 /* check_if_need_update_fw
  * @return 1 (true) if need; 0 (false) if not.
  */
-static int check_if_valid_fw(
-		struct sb_fw_header *hdr,
-		struct sb_fw_update_info *info)
+static int check_if_valid_fw(struct sb_fw_header *hdr,
+			     struct sb_fw_update_info *info)
 {
-	return check_battery_firmware_image_signature(hdr)
-		&& check_battery_firmware_ids(hdr, info)
-		&& check_battery_firmware_image_checksum(hdr);
+	return check_battery_firmware_image_signature(hdr) &&
+	       check_battery_firmware_ids(hdr, info) &&
+	       check_battery_firmware_image_checksum(hdr);
 }
 
 /* check_if_need_update_fw
  * @return 1 (true) if need; 0 (false) if not.
  */
-static int check_if_need_update_fw(
-		struct sb_fw_header *hdr,
-		struct sb_fw_update_info *info)
+static int check_if_need_update_fw(struct sb_fw_header *hdr,
+				   struct sb_fw_update_info *info)
 {
 	return check_battery_firmware_image_version(hdr, info);
 }
 
 static void log_msg(struct fw_update_ctrl *fw_update,
-			enum fw_update_state state, const char *msg)
+		    enum fw_update_state state, const char *msg)
 {
-	sprintf(fw_update->msg,
-		"Battery Firmware Updater State:%d %s", state, msg);
+	sprintf(fw_update->msg, "Battery Firmware Updater State:%d %s", state,
+		msg);
 }
 
-
 static char *read_fw_image(struct fw_update_ctrl *fw_update)
 {
 	int size;
@@ -259,11 +232,11 @@ static char *read_fw_image(struct fw_update_ctrl *fw_update)
 	print_battery_firmware_image_hdr(fw_update->fw_img_hdr);
 
 	if (fw_update->fw_img_hdr->fw_binary_offset >= fw_update->size ||
-		fw_update->size < 256) {
+	    fw_update->size < 256) {
 		printf("Load Firmware Image[%s] Error offset:%d size:%d\n",
-			fw_update->image_name,
-			fw_update->fw_img_hdr->fw_binary_offset,
-			fw_update->size);
+		       fw_update->image_name,
+		       fw_update->fw_img_hdr->fw_binary_offset,
+		       fw_update->size);
 		free(buf);
 		return NULL;
 	}
@@ -284,9 +257,9 @@ static int get_status(struct sb_fw_update_status *status)
 	param->hdr.subcmd = EC_SB_FW_UPDATE_STATUS;
 	do {
 		usleep(SB_FW_UPDATE_DEFAULT_DELAY);
-		rv = ec_command(EC_CMD_SB_FW_UPDATE, 0,
-			param, sizeof(struct ec_sb_fw_update_header),
-			resp, SB_FW_UPDATE_CMD_STATUS_SIZE);
+		rv = ec_command(EC_CMD_SB_FW_UPDATE, 0, param,
+				sizeof(struct ec_sb_fw_update_header), resp,
+				SB_FW_UPDATE_CMD_STATUS_SIZE);
 	} while ((rv < 0) && (cnt++ < SB_FW_UPDATE_DEFAULT_RETRY_CNT));
 
 	if (rv < 0) {
@@ -312,9 +285,9 @@ static int get_info(struct sb_fw_update_info *info)
 	param->hdr.subcmd = EC_SB_FW_UPDATE_INFO;
 	do {
 		usleep(SB_FW_UPDATE_DEFAULT_DELAY);
-		rv = ec_command(EC_CMD_SB_FW_UPDATE, 0,
-			param, sizeof(struct ec_sb_fw_update_header),
-			resp, SB_FW_UPDATE_CMD_INFO_SIZE);
+		rv = ec_command(EC_CMD_SB_FW_UPDATE, 0, param,
+				sizeof(struct ec_sb_fw_update_header), resp,
+				SB_FW_UPDATE_CMD_INFO_SIZE);
 	} while ((rv < 0) && (cnt++ < SB_FW_UPDATE_DEFAULT_RETRY_CNT));
 
 	if (rv < 0) {
@@ -334,8 +307,8 @@ static int send_subcmd(int subcmd)
 		(struct ec_params_sb_fw_update *)ec_outbuf;
 
 	param->hdr.subcmd = subcmd;
-	rv = ec_command(EC_CMD_SB_FW_UPDATE, 0,
-		param, sizeof(struct ec_sb_fw_update_header), NULL, 0);
+	rv = ec_command(EC_CMD_SB_FW_UPDATE, 0, param,
+			sizeof(struct ec_sb_fw_update_header), NULL, 0);
 	if (rv < 0) {
 		printf("Firmware Update subcmd:%d Error\n", subcmd);
 		return -EC_RES_ERROR;
@@ -343,22 +316,21 @@ static int send_subcmd(int subcmd)
 	return EC_RES_SUCCESS;
 }
 
-static int write_block(struct fw_update_ctrl *fw_update,
-			int offset, int bsize)
+static int write_block(struct fw_update_ctrl *fw_update, int offset, int bsize)
 {
 	int rv;
 
 	struct ec_params_sb_fw_update *param =
 		(struct ec_params_sb_fw_update *)ec_outbuf;
 
-	memcpy(param->write.data, fw_update->ptr+offset, bsize);
+	memcpy(param->write.data, fw_update->ptr + offset, bsize);
 
 	param->hdr.subcmd = EC_SB_FW_UPDATE_WRITE;
-	rv = ec_command(EC_CMD_SB_FW_UPDATE, 0,
-		param, sizeof(struct ec_params_sb_fw_update), NULL, 0);
+	rv = ec_command(EC_CMD_SB_FW_UPDATE, 0, param,
+			sizeof(struct ec_params_sb_fw_update), NULL, 0);
 	if (rv < 0) {
 		printf("Firmware Update Write Error ptr:%p offset@%x\n",
-			fw_update->ptr, offset);
+		       fw_update->ptr, offset);
 		return -EC_RES_ERROR;
 	}
 	return EC_RES_SUCCESS;
@@ -373,7 +345,7 @@ static void dump_data(char *data, int offset, int size)
 
 	printf("Offset:0x%X\n", offset);
 	for (i = 0; i < size; i++) {
-		if ((i%16) == 0)
+		if ((i % 16) == 0)
 			printf("\n");
 		printf("%02X ", data[i]);
 	}
@@ -397,8 +369,8 @@ static enum fw_update_state s0_read_status(struct fw_update_ctrl *fw_update)
 		return S10_TERMINAL;
 	}
 
-	if (!((fw_update->status.abnormal_condition == 0)
-		&& (fw_update->status.fw_update_supported == 1))) {
+	if (!((fw_update->status.abnormal_condition == 0) &&
+	      (fw_update->status.fw_update_supported == 1))) {
 		return S0_READ_STATUS;
 	}
 
@@ -409,8 +381,8 @@ static enum fw_update_state s0_read_status(struct fw_update_ctrl *fw_update)
 		return S1_READ_INFO;
 }
 
-static enum fw_update_state s1_read_battery_info(
-		struct fw_update_ctrl *fw_update)
+static enum fw_update_state
+s1_read_battery_info(struct fw_update_ctrl *fw_update)
 {
 	int rv;
 
@@ -431,9 +403,8 @@ static enum fw_update_state s1_read_battery_info(
 	print_info(&fw_update->info);
 
 	sprintf(fw_update->image_name,
-			"/lib/firmware/battery/maker.%04x.hwid.%04x.bin",
-			fw_update->info.maker_id,
-			fw_update->info.hardware_id);
+		"/lib/firmware/battery/maker.%04x.hwid.%04x.bin",
+		fw_update->info.maker_id, fw_update->info.hardware_id);
 
 	if (NULL == read_fw_image(fw_update)) {
 		fw_update->rv = 0;
@@ -520,7 +491,6 @@ static enum fw_update_state s3_read_status(struct fw_update_ctrl *fw_update)
 		return S10_TERMINAL;
 	}
 	return S4_WRITE_UPDATE;
-
 }
 
 static enum fw_update_state s4_write_update(struct fw_update_ctrl *fw_update)
@@ -589,7 +559,7 @@ static enum fw_update_state s6_write_block(struct fw_update_ctrl *fw_update)
 	 * Add more delays after the last few (3) block writes.
 	 * 3 is chosen based on current test results.
 	 */
-	if ((offset + 3*fw_update->step_size) >= fw_update->size)
+	if ((offset + 3 * fw_update->step_size) >= fw_update->size)
 		usleep(DELAY_US_WRITE_END);
 
 	usleep(get_delay_value(offset, fw_update->step_size));
@@ -609,38 +579,36 @@ static enum fw_update_state s7_read_status(struct fw_update_ctrl *fw_update)
 		usleep(SB_FW_UPDATE_DEFAULT_DELAY);
 		rv = get_status(&fw_update->status);
 		if (rv) {
-			dump_data(fw_update->ptr+offset, offset, bsize);
+			dump_data(fw_update->ptr + offset, offset, bsize);
 			print_status(&fw_update->status);
 			fw_update->rv = -1;
 			log_msg(fw_update, S7_READ_STATUS, "Interface Error");
 			return S10_TERMINAL;
 		}
 	} while (fw_update->status.busy &&
-			(cnt++ < SB_FW_UPDATE_DEFAULT_RETRY_CNT));
+		 (cnt++ < SB_FW_UPDATE_DEFAULT_RETRY_CNT));
 
 	if (fw_update->status.fec_error) {
-		dump_data(fw_update->ptr+offset, offset, bsize);
+		dump_data(fw_update->ptr + offset, offset, bsize);
 		print_status(&fw_update->status);
 		fw_update->rv = 0;
 		return S6_WRITE_BLOCK;
 	}
 	if (fw_update->status.permanent_failure ||
-		fw_update->status.v_fail_permanent) {
-		dump_data(fw_update->ptr+offset, offset, bsize);
+	    fw_update->status.v_fail_permanent) {
+		dump_data(fw_update->ptr + offset, offset, bsize);
 		print_status(&fw_update->status);
 		fw_update->rv = -1;
 		log_msg(fw_update, S7_READ_STATUS, "Battery Permanent Error");
 		return S8_WRITE_END;
 	}
 	if (fw_update->status.v_fail_maker_id ||
-		fw_update->status.v_fail_hw_id ||
-		fw_update->status.v_fail_fw_version ||
-		fw_update->status.fw_corrupted ||
-		fw_update->status.cmd_reject ||
-		fw_update->status.invalid_data ||
-		fw_update->status.fw_fatal_error) {
-
-		dump_data(fw_update->ptr+offset, offset, bsize);
+	    fw_update->status.v_fail_hw_id ||
+	    fw_update->status.v_fail_fw_version ||
+	    fw_update->status.fw_corrupted || fw_update->status.cmd_reject ||
+	    fw_update->status.invalid_data ||
+	    fw_update->status.fw_fatal_error) {
+		dump_data(fw_update->ptr + offset, offset, bsize);
 		print_status(&fw_update->status);
 		fw_update->rv = 0;
 		return S1_READ_INFO;
@@ -651,7 +619,6 @@ static enum fw_update_state s7_read_status(struct fw_update_ctrl *fw_update)
 	return S6_WRITE_BLOCK;
 }
 
-
 static enum fw_update_state s8_write_end(struct fw_update_ctrl *fw_update)
 {
 	int rv;
@@ -686,8 +653,8 @@ static enum fw_update_state s9_read_status(struct fw_update_ctrl *fw_update)
 		log_msg(fw_update, S9_READ_STATUS, "Interface Error");
 		return S10_TERMINAL;
 	}
-	if ((fw_update->status.fw_update_mode == 1)
-		|| (fw_update->status.busy == 1)) {
+	if ((fw_update->status.fw_update_mode == 1) ||
+	    (fw_update->status.busy == 1)) {
 		usleep(SB_FW_UPDATE_DEFAULT_DELAY);
 		fw_update->busy_retry_cnt--;
 		return S9_READ_STATUS;
@@ -697,22 +664,13 @@ static enum fw_update_state s9_read_status(struct fw_update_ctrl *fw_update)
 	return S10_TERMINAL;
 }
 
-
 typedef enum fw_update_state (*fw_state_func)(struct fw_update_ctrl *fw_update);
 
-fw_state_func state_table[] = {
-	s0_read_status,
-	s1_read_battery_info,
-	s2_write_prepare,
-	s3_read_status,
-	s4_write_update,
-	s5_read_status,
-	s6_write_block,
-	s7_read_status,
-	s8_write_end,
-	s9_read_status
-};
-
+fw_state_func state_table[] = { s0_read_status,	  s1_read_battery_info,
+				s2_write_prepare, s3_read_status,
+				s4_write_update,  s5_read_status,
+				s6_write_block,	  s7_read_status,
+				s8_write_end,	  s9_read_status };
 
 /**
  * Update Smart Battery Firmware
@@ -740,13 +698,13 @@ static int ec_sb_firmware_update(struct fw_update_ctrl *fw_update)
 	return fw_update->rv;
 }
 
-#define GEC_LOCK_TIMEOUT_SECS   30  /* 30 secs */
+#define GEC_LOCK_TIMEOUT_SECS 30 /* 30 secs */
 void usage(char *argv[])
 {
 	printf("Usage: %s [check|update]\n"
-		"	check: check if AC Adaptor is connected.\n"
-		"	update: trigger battery firmware update.\n",
-		argv[0]);
+	       "	check: check if AC Adaptor is connected.\n"
+	       "	update: trigger battery firmware update.\n",
+	       argv[0]);
 }
 
 int main(int argc, char *argv[])
@@ -827,10 +785,8 @@ int main(int argc, char *argv[])
 	fw_update.flags |= F_VERSION_CHECK;
 
 	rv = ec_sb_firmware_update(&fw_update);
-	printf("Battery Firmware Update:0x%02x %s\n%s\n",
-			fw_update.flags,
-			((rv) ? "FAIL " : " "),
-			fw_update.msg);
+	printf("Battery Firmware Update:0x%02x %s\n%s\n", fw_update.flags,
+	       ((rv) ? "FAIL " : " "), fw_update.msg);
 
 	/* Update battery firmware update interface to be protected */
 	if (!(fw_update.flags & F_NEED_UPDATE))
diff --git a/util/ec_sb_firmware_update.h b/util/ec_sb_firmware_update.h
index 5bddebaf4a..2757dca9a5 100644
--- a/util/ec_sb_firmware_update.h
+++ b/util/ec_sb_firmware_update.h
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -55,7 +55,7 @@ struct sb_fw_header {
 	uint16_t data_table_version; /* E F */
 	uint32_t fw_binary_offset; /*0x10 0x11 0x12 0x13 */
 	uint32_t fw_binary_size; /* 0x14 0x15 0x16 0x17 */
-	uint8_t  checksum; /* 0x18 */
+	uint8_t checksum; /* 0x18 */
 };
 
 /**
@@ -63,25 +63,25 @@ struct sb_fw_header {
  *    Firmware Update Status
  */
 struct sb_fw_update_status {
-	uint16_t v_fail_maker_id:1; /* b0 */
-	uint16_t v_fail_hw_id:1; /* b1 */
-	uint16_t v_fail_fw_version:1; /* b2 */
-	uint16_t v_fail_permanent:1; /* b3 */
+	uint16_t v_fail_maker_id : 1; /* b0 */
+	uint16_t v_fail_hw_id : 1; /* b1 */
+	uint16_t v_fail_fw_version : 1; /* b2 */
+	uint16_t v_fail_permanent : 1; /* b3 */
 
-	uint16_t rsvd5:1; /* b4 */
-	uint16_t permanent_failure:1; /* b5 */
-	uint16_t abnormal_condition:1; /* b6 */
-	uint16_t fw_update_supported:1; /* b7 */
+	uint16_t rsvd5 : 1; /* b4 */
+	uint16_t permanent_failure : 1; /* b5 */
+	uint16_t abnormal_condition : 1; /* b6 */
+	uint16_t fw_update_supported : 1; /* b7 */
 
-	uint16_t fw_update_mode:1; /* b8 */
-	uint16_t fw_corrupted:1; /* b9 */
-	uint16_t cmd_reject:1; /* b10 */
-	uint16_t invalid_data:1; /* b11 */
+	uint16_t fw_update_mode : 1; /* b8 */
+	uint16_t fw_corrupted : 1; /* b9 */
+	uint16_t cmd_reject : 1; /* b10 */
+	uint16_t invalid_data : 1; /* b11 */
 
-	uint16_t fw_fatal_error:1; /* b12 */
-	uint16_t fec_error:1; /* b13 */
-	uint16_t busy:1; /* b14 */
-	uint16_t rsvd15:1; /* b15 */
+	uint16_t fw_fatal_error : 1; /* b12 */
+	uint16_t fec_error : 1; /* b13 */
+	uint16_t busy : 1; /* b14 */
+	uint16_t rsvd15 : 1; /* b15 */
 } __packed;
 
 /**
@@ -90,22 +90,22 @@ struct sb_fw_update_status {
  *     sequence:=b1,b0,b3,b2,b5,b5,b7,b6
  */
 struct sb_fw_update_info {
-	uint16_t maker_id;    /* b0, b1 */
+	uint16_t maker_id; /* b0, b1 */
 	uint16_t hardware_id; /* b2, b3 */
-	uint16_t fw_version;  /* b4, b5 */
-	uint16_t data_version;/* b6, b7 */
+	uint16_t fw_version; /* b4, b5 */
+	uint16_t data_version; /* b6, b7 */
 } __packed;
 
 /**
  * smart.battery.maker.id
  */
 enum sb_maker_id {
-	sb_maker_id_lgc       = 0x0001, /* b0=0; b1=1 */
+	sb_maker_id_lgc = 0x0001, /* b0=0; b1=1 */
 	sb_maker_id_panasonic = 0x0002,
-	sb_maker_id_sanyo     = 0x0003,
-	sb_maker_id_sony      = 0x0004,
-	sb_maker_id_simplo    = 0x0005,
-	sb_maker_id_celxpert  = 0x0006,
+	sb_maker_id_sanyo = 0x0003,
+	sb_maker_id_sony = 0x0004,
+	sb_maker_id_simplo = 0x0005,
+	sb_maker_id_celxpert = 0x0006,
 };
 
 /*
@@ -119,8 +119,8 @@ enum sb_maker_id {
  * case 5. If battery interface is busy, retry < 10 times.
  *    Delay 1 second between retries.
  */
-#define SB_FW_UPDATE_ERROR_RETRY_CNT      2
-#define SB_FW_UPDATE_FEC_ERROR_RETRY_CNT  2
+#define SB_FW_UPDATE_ERROR_RETRY_CNT 2
+#define SB_FW_UPDATE_FEC_ERROR_RETRY_CNT 2
 #define SB_FW_UPDATE_BUSY_ERROR_RETRY_CNT 4
 
 #endif
diff --git a/util/ecst.c b/util/ecst.c
index 8d0ce940d6..2c3150c34a 100644
--- a/util/ecst.c
+++ b/util/ecst.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -39,20 +39,21 @@ int is_mrider15 = FALSE;
 
 /* Chips information, RAM start address and RAM size. */
 struct chip_info chip_info[] = {
-	[NPCX5M5G] = {NPCX5M5G_RAM_ADDR, NPCX5M5G_RAM_SIZE},
-	[NPCX5M6G] = {NPCX5M6G_RAM_ADDR, NPCX5M6G_RAM_SIZE},
-	[NPCX7M5] = {NPCX7M5X_RAM_ADDR, NPCX7M5X_RAM_SIZE},
-	[NPCX7M6] = {NPCX7M6X_RAM_ADDR, NPCX7M6X_RAM_SIZE},
-	[NPCX7M7] = {NPCX7M7X_RAM_ADDR, NPCX7M7X_RAM_SIZE},
-	[NPCX9M3] = {NPCX9M3X_RAM_ADDR, NPCX9M3X_RAM_SIZE},
-	[NPCX9M6] = {NPCX9M6X_RAM_ADDR, NPCX9M6X_RAM_SIZE},
+	[NPCX5M5G] = { NPCX5M5G_RAM_ADDR, NPCX5M5G_RAM_SIZE },
+	[NPCX5M6G] = { NPCX5M6G_RAM_ADDR, NPCX5M6G_RAM_SIZE },
+	[NPCX7M5] = { NPCX7M5X_RAM_ADDR, NPCX7M5X_RAM_SIZE },
+	[NPCX7M6] = { NPCX7M6X_RAM_ADDR, NPCX7M6X_RAM_SIZE },
+	[NPCX7M7] = { NPCX7M7X_RAM_ADDR, NPCX7M7X_RAM_SIZE },
+	[NPCX9M3] = { NPCX9M3X_RAM_ADDR, NPCX9M3X_RAM_SIZE },
+	[NPCX9M6] = { NPCX9M6X_RAM_ADDR, NPCX9M6X_RAM_SIZE },
 };
 BUILD_ASSERT(ARRAY_SIZE(chip_info) == NPCX_CHIP_RAM_VAR_NONE);
 
 /* Support chips name strings */
-const char *supported_chips = "npcx5m5g, npcx5m6g, npcx7m5g, npcx7m6g, "
-		"npcx7m6f, npcx7m6fb, npcx7m6fc, npcx7m7fc, npcx7m7wb, "
-		"npcx7m7wc, npcx9m3f or npcx9m6f";
+const char *supported_chips =
+	"npcx5m5g, npcx5m6g, npcx7m5g, npcx7m6g, "
+	"npcx7m6f, npcx7m6fb, npcx7m6fc, npcx7m7fc, npcx7m7wb, "
+	"npcx7m7wc, npcx9m3f or npcx9m6f";
 
 static unsigned int calc_api_csum_bin(void);
 static unsigned int initialize_crc_32(void);
@@ -70,16 +71,17 @@ static unsigned int finalize_crc_32(unsigned int crc);
  *    and returns FALSE.
  */
 static int splice_into_path(char *result, const char *path, int resultsz,
-	const char *prefix) {
+			    const char *prefix)
+{
 	char *last_delim, *result_last_delim;
 
 	if (strlen(path) + strlen(prefix) + 1 > resultsz) {
 		my_printf(TERR,
-			"\n\nfilename '%s' with prefix '%s' too long\n\n",
-			path, prefix);
+			  "\n\nfilename '%s' with prefix '%s' too long\n\n",
+			  path, prefix);
 		my_printf(TINF,
-			"\n\n%zu + %zu + 1 needs to fit in %d bytes\n\n",
-			strlen(path), strlen(prefix), resultsz);
+			  "\n\n%zu + %zu + 1 needs to fit in %d bytes\n\n",
+			  strlen(path), strlen(prefix), resultsz);
 		return FALSE;
 	}
 
@@ -124,7 +126,7 @@ static enum npcx_chip_ram_variant chip_to_ram_var(const char *chip_name)
 	else if (str_cmp_no_case(chip_name, "npcx7m6fc") == 0)
 		return NPCX7M6;
 	else if (str_cmp_no_case(chip_name, "npcx7m6g") == 0)
-		return  NPCX7M6;
+		return NPCX7M6;
 	else if (str_cmp_no_case(chip_name, "npcx7m5g") == 0)
 		return NPCX7M5;
 	else if (str_cmp_no_case(chip_name, "npcx5m6g") == 0)
@@ -149,7 +151,6 @@ static enum npcx_chip_ram_variant chip_to_ram_var(const char *chip_name)
 int main(int argc, char *argv[])
 
 {
-
 	int mode_choose = FALSE;
 	/* Do we get a bin File? */
 	int main_fw_hdr_flag = FALSE;
@@ -160,7 +161,7 @@ int main(int argc, char *argv[])
 
 	/* Following variables: common to all modes */
 	int main_status = TRUE;
-	unsigned int  main_temp = 0L;
+	unsigned int main_temp = 0L;
 	char main_str_temp[TMP_STR_SIZE];
 	char *end_ptr;
 
@@ -189,17 +190,15 @@ int main(int argc, char *argv[])
 	g_verbose = NO_VERBOSE;
 
 	g_ram_start_address = chip_info[DEFAULT_CHIP].ram_addr;
-	g_ram_size          = chip_info[DEFAULT_CHIP].ram_size;
+	g_ram_size = chip_info[DEFAULT_CHIP].ram_size;
 
 	/* Set default values */
 	g_calc_type = CALC_TYPE_NONE;
 	bin_params.spi_max_clk = SPI_MAX_CLOCK_DEFAULT;
 	bin_params.spi_clk_ratio = 0x00;
 	bin_params.spi_read_mode = SPI_READ_MODE_DEFAULT;
-	bin_params.fw_load_addr =
-				chip_info[DEFAULT_CHIP].ram_addr;
-	bin_params.fw_ep =
-				chip_info[DEFAULT_CHIP].ram_addr;
+	bin_params.fw_load_addr = chip_info[DEFAULT_CHIP].ram_addr;
+	bin_params.fw_ep = chip_info[DEFAULT_CHIP].ram_addr;
 	bin_params.fw_err_detec_s_addr = FW_CRC_START_ADDR;
 	bin_params.fw_err_detec_e_addr = FW_CRC_START_ADDR;
 	bin_params.flash_size = FLASH_SIZE_DEFAULT;
@@ -234,20 +233,18 @@ int main(int argc, char *argv[])
 		else if (str_cmp_no_case(hdr_args[arg_ind], "-vv") == 0)
 			g_verbose = SUPER_VERBOSE;
 
-		else if (str_cmp_no_case(hdr_args[arg_ind],
-							"-mode") == 0) {
+		else if (str_cmp_no_case(hdr_args[arg_ind], "-mode") == 0) {
 			mode_choose = TRUE;
 			arg_ind++;
 			if ((hdr_args[arg_ind] == NULL) ||
-				(sscanf(hdr_args[arg_ind],
-					"%s", main_str_temp) != 1)) {
+			    (sscanf(hdr_args[arg_ind], "%s", main_str_temp) !=
+			     1)) {
 				my_printf(TERR, "\nCannot read operation mode");
 				my_printf(TERR, ", bt, bh or api. !\n");
 				main_status = FALSE;
 			} else {
 				/* bt, bh and api should not coexist */
-				if (main_fw_hdr_flag ||
-				    main_api_flag ||
+				if (main_fw_hdr_flag || main_api_flag ||
 				    main_hdr_flag) {
 					my_printf(TERR, "\nOperation modes bt");
 					my_printf(TERR, ", bh, and api should");
@@ -257,8 +254,8 @@ int main(int argc, char *argv[])
 
 				if (str_cmp_no_case(main_str_temp, "bt") == 0)
 					main_fw_hdr_flag = TRUE;
-				else if (str_cmp_no_case(main_str_temp,
-							 "bh") == 0)
+				else if (str_cmp_no_case(main_str_temp, "bh") ==
+					 0)
 					main_hdr_flag = TRUE;
 				else if (str_cmp_no_case(main_str_temp,
 							 "api") == 0)
@@ -266,8 +263,8 @@ int main(int argc, char *argv[])
 				else {
 					my_printf(TERR,
 						  "\nInvalid operation mode ");
-					my_printf(TERR,
-						  "(%s)\n", main_str_temp);
+					my_printf(TERR, "(%s)\n",
+						  main_str_temp);
 					main_status = FALSE;
 				}
 			}
@@ -276,11 +273,10 @@ int main(int argc, char *argv[])
 		else if (str_cmp_no_case(hdr_args[arg_ind], "-chip") == 0) {
 			arg_ind++;
 			if ((hdr_args[arg_ind] == NULL) ||
-				(sscanf(hdr_args[arg_ind],
-					"%s",
-					main_str_temp) != 1)) {
+			    (sscanf(hdr_args[arg_ind], "%s", main_str_temp) !=
+			     1)) {
 				my_printf(TERR, "\nCannot read chip name %s.\n",
-						supported_chips);
+					  supported_chips);
 				main_status = FALSE;
 			} else {
 				enum npcx_chip_ram_variant ram_variant;
@@ -291,41 +287,38 @@ int main(int argc, char *argv[])
 						  "\nInvalid chip name (%s) ",
 						  main_str_temp);
 					my_printf(TERR, ", it should be %s.\n",
-						supported_chips);
+						  supported_chips);
 					main_status = FALSE;
 					break;
 				}
 
-				if ((bin_params.bin_params
-					& BIN_FW_LOAD_START_ADDR) ==
-					0x00000000)
+				if ((bin_params.bin_params &
+				     BIN_FW_LOAD_START_ADDR) == 0x00000000)
 					bin_params.fw_load_addr =
-					chip_info[ram_variant].ram_addr;
+						chip_info[ram_variant].ram_addr;
 
-				if ((bin_params.bin_params
-					& BIN_FW_ENTRY_POINT) ==
-					0x00000000)
+				if ((bin_params.bin_params &
+				     BIN_FW_ENTRY_POINT) == 0x00000000)
 					bin_params.fw_ep =
-					chip_info[ram_variant].ram_addr;
+						chip_info[ram_variant].ram_addr;
 
 				g_ram_start_address =
 					chip_info[ram_variant].ram_addr;
-				g_ram_size =
-					chip_info[ram_variant].ram_size;
+				g_ram_size = chip_info[ram_variant].ram_size;
 
 				if ((ram_variant == NPCX5M5G) ||
-					(ram_variant == NPCX5M6G)) {
+				    (ram_variant == NPCX5M6G)) {
 					is_mrider15 = TRUE;
 				}
 			}
-		  /* -argfile Read argument file. File name must be after it.*/
-		} else if (str_cmp_no_case(hdr_args[arg_ind],
-					   "-argfile") == 0) {
+			/* -argfile Read argument file. File name must be after
+			 * it.*/
+		} else if (str_cmp_no_case(hdr_args[arg_ind], "-argfile") ==
+			   0) {
 			arg_ind++;
 			if (arg_ind < arg_num) {
-				strncpy(arg_file_name,
-						hdr_args[arg_ind],
-						sizeof(arg_file_name) - 1);
+				strncpy(arg_file_name, hdr_args[arg_ind],
+					sizeof(arg_file_name) - 1);
 				arg_file_pointer = fopen(arg_file_name, "rt");
 				if (arg_file_pointer == NULL) {
 					my_printf(TERR,
@@ -340,16 +333,15 @@ int main(int argc, char *argv[])
 					     (tmp_ind + arg_ind + 1) < arg_num;
 					     tmp_ind++)
 						strncpy(tmp_hdr_args[tmp_ind],
-							hdr_args
-							   [tmp_ind+arg_ind+1],
+							hdr_args[tmp_ind +
+								 arg_ind + 1],
 							ARG_SIZE);
 
 					tmp_arg_num = tmp_ind;
 
 					/* Read arguments from file to array */
 					for (arg_ind++;
-					     fscanf(arg_file_pointer,
-						    "%s",
+					     fscanf(arg_file_pointer, "%s",
 						    hdr_args[arg_ind]) == 1;
 					     arg_ind++)
 						;
@@ -359,9 +351,9 @@ int main(int argc, char *argv[])
 
 					/* Copy back the restored arguments. */
 					for (tmp_ind = 0;
-						 (tmp_ind < tmp_arg_num) &&
-						 (arg_ind < MAX_ARGS);
-						 tmp_ind++) {
+					     (tmp_ind < tmp_arg_num) &&
+					     (arg_ind < MAX_ARGS);
+					     tmp_ind++) {
 						strncpy(hdr_args[arg_ind++],
 							tmp_hdr_args[tmp_ind],
 							ARG_SIZE);
@@ -379,120 +371,113 @@ int main(int argc, char *argv[])
 		} else if (str_cmp_no_case(hdr_args[arg_ind], "-i") == 0) {
 			arg_ind++;
 			if (arg_ind < arg_num) {
-				strncpy(input_file_name,
-				hdr_args[arg_ind],
-				sizeof(input_file_name) - 1);
+				strncpy(input_file_name, hdr_args[arg_ind],
+					sizeof(input_file_name) - 1);
 			} else {
 				my_printf(TERR, "\nMissing Input File Name\n");
 				main_status = FALSE;
 			}
-		  /* -o Get output file name. */
+			/* -o Get output file name. */
 		} else if (str_cmp_no_case(hdr_args[arg_ind], "-o") == 0) {
 			arg_ind++;
 			if (arg_ind < arg_num) {
-				strncpy(output_file_name,
-					hdr_args[arg_ind],
+				strncpy(output_file_name, hdr_args[arg_ind],
 					sizeof(output_file_name) - 1);
 			} else {
 				my_printf(TERR,
 					  "\nMissing Output File Name.\n");
 				main_status = FALSE;
 			}
-		  /* -usearmrst get FW entry point from FW image offset 4.*/
-		} else if (str_cmp_no_case(hdr_args[arg_ind],
-					   "-usearmrst") == 0) {
-			if ((bin_params.bin_params &
-			     BIN_FW_ENTRY_POINT) != 0x00000000) {
+			/* -usearmrst get FW entry point from FW image
+			 * offset 4.*/
+		} else if (str_cmp_no_case(hdr_args[arg_ind], "-usearmrst") ==
+			   0) {
+			if ((bin_params.bin_params & BIN_FW_ENTRY_POINT) !=
+			    0x00000000) {
 				my_printf(TERR, "\n-usearmrst not allowed, ");
 				my_printf(TERR, "FW entry point already set ");
 				my_printf(TERR, "using -fwep !\n");
 				main_status = FALSE;
 			} else
-				bin_params.bin_params |=
-							BIN_FW_USER_ARM_RESET;
-		/* -nohcrs disable header CRC*/
+				bin_params.bin_params |= BIN_FW_USER_ARM_RESET;
+			/* -nohcrs disable header CRC*/
 		} else if (str_cmp_no_case(hdr_args[arg_ind], "-nohcrc") == 0)
-			bin_params.bin_params |=
-							BIN_FW_HDR_CRC_DISABLE;
+			bin_params.bin_params |= BIN_FW_HDR_CRC_DISABLE;
 		/* -ph merg header in BIN file. */
 		else if (str_cmp_no_case(hdr_args[arg_ind], "-ph") == 0) {
-			bin_params.bin_params |=
-							BIN_FW_HDR_OFFSET;
-			if ((strlen(hdr_args[arg_ind+1]) == 0) ||
-				(sscanf(hdr_args[arg_ind+1],
-					"%x",
-					&main_temp) != 1))
+			bin_params.bin_params |= BIN_FW_HDR_OFFSET;
+			if ((strlen(hdr_args[arg_ind + 1]) == 0) ||
+			    (sscanf(hdr_args[arg_ind + 1], "%x", &main_temp) !=
+			     1))
 				bin_params.fw_hdr_offset = 0;
 			else {
 				arg_ind++;
 				bin_params.fw_hdr_offset = main_temp;
 			}
-		/* -spimaxclk  Get SPI flash max clock. */
-		} else if (str_cmp_no_case(hdr_args[arg_ind],
-					   "-spimaxclk") == 0) {
+			/* -spimaxclk  Get SPI flash max clock. */
+		} else if (str_cmp_no_case(hdr_args[arg_ind], "-spimaxclk") ==
+			   0) {
 			arg_ind++;
 			if ((hdr_args[arg_ind] == NULL) ||
-				(sscanf(hdr_args[arg_ind],
-					"%d", &main_temp) != 1)) {
+			    (sscanf(hdr_args[arg_ind], "%d", &main_temp) !=
+			     1)) {
 				my_printf(TERR, "\nCannot read SPI Flash Max");
 				my_printf(TERR, " Clock !\n");
 				main_status = FALSE;
 			} else
 				bin_params.spi_max_clk =
-						(unsigned char) main_temp;
-		/* -spiclkratio  Get SPI flash max clock ratio. */
-		} else if (str_cmp_no_case(hdr_args[arg_ind],
-			"-spiclkratio") == 0) {
+					(unsigned char)main_temp;
+			/* -spiclkratio  Get SPI flash max clock ratio. */
+		} else if (str_cmp_no_case(hdr_args[arg_ind], "-spiclkratio") ==
+			   0) {
 			arg_ind++;
 			if ((hdr_args[arg_ind] == NULL) ||
-				(sscanf(hdr_args[arg_ind],
-				"%d", &main_temp) != 1)) {
+			    (sscanf(hdr_args[arg_ind], "%d", &main_temp) !=
+			     1)) {
 				my_printf(TERR,
 					  "\nCannot read SPI Clock Ratio\n");
 				main_status = FALSE;
 			} else
 				bin_params.spi_clk_ratio =
-						(unsigned char)main_temp;
+					(unsigned char)main_temp;
 
-		/* spireadmode	get SPI read mode. */
-		} else if (str_cmp_no_case(hdr_args[arg_ind],
-					   "-spireadmode") == 0) {
+			/* spireadmode	get SPI read mode. */
+		} else if (str_cmp_no_case(hdr_args[arg_ind], "-spireadmode") ==
+			   0) {
 			arg_ind++;
 			if ((hdr_args[arg_ind] == NULL) ||
-				(sscanf(hdr_args[arg_ind],
-						"%20s",
-						main_str_temp) != 1)) {
+			    (sscanf(hdr_args[arg_ind], "%20s", main_str_temp) !=
+			     1)) {
 				my_printf(TERR, "\nCannot read SPI Flash");
 				my_printf(TERR, " Read Mode !\n");
 				main_status = FALSE;
 			} else {
 				if (str_cmp_no_case(main_str_temp,
-						SPI_NORMAL_MODE_VAL) == 0)
+						    SPI_NORMAL_MODE_VAL) == 0)
 					bin_params.spi_read_mode =
-					(unsigned char) SPI_NORMAL_MODE;
+						(unsigned char)SPI_NORMAL_MODE;
 				else if (str_cmp_no_case(main_str_temp,
-					 SPI_SINGLE_MODE_VAL) == 0)
+							 SPI_SINGLE_MODE_VAL) ==
+					 0)
 					bin_params.spi_read_mode =
-						(unsigned char)
-						SPI_SINGLE_MODE;
+						(unsigned char)SPI_SINGLE_MODE;
 				else if (str_cmp_no_case(main_str_temp,
-					 SPI_DUAL_MODE_VAL) == 0)
+							 SPI_DUAL_MODE_VAL) ==
+					 0)
 					bin_params.spi_read_mode =
-						(unsigned char)
-						SPI_DUAL_MODE;
+						(unsigned char)SPI_DUAL_MODE;
 				else if (str_cmp_no_case(main_str_temp,
-					SPI_QUAD_MODE_VAL) == 0)
+							 SPI_QUAD_MODE_VAL) ==
+					 0)
 					bin_params.spi_read_mode =
-						(unsigned char)
-						SPI_QUAD_MODE;
+						(unsigned char)SPI_QUAD_MODE;
 				else {
 					my_printf(TERR,
 						  "\nInvalid SPI Flash Read ");
 					my_printf(TERR,
 						  "Mode (%s), it should be ",
 						  main_str_temp);
-					my_printf(TERR,
-						  "normal, singleMode, ");
+					my_printf(TERR, "normal, singleMode, ");
 					my_printf(TERR,
 						  "dualMode or quadMode !\n");
 					main_status = FALSE;
@@ -508,95 +493,88 @@ int main(int argc, char *argv[])
 			bin_params.bin_params |= BIN_FW_CRC_DISABLE;
 
 		/* -fwloadaddr,  Get the FW load address. */
-		else if (str_cmp_no_case(hdr_args[arg_ind],
-					 "-fwloadaddr") == 0) {
+		else if (str_cmp_no_case(hdr_args[arg_ind], "-fwloadaddr") ==
+			 0) {
 			arg_ind++;
 			if ((hdr_args[arg_ind] == NULL) ||
-				(sscanf(hdr_args[arg_ind],
-					"%x",
-					&main_temp) != 1)) {
+			    (sscanf(hdr_args[arg_ind], "%x", &main_temp) !=
+			     1)) {
 				my_printf(TERR, "\nCannot read FW Load ");
 				my_printf(TERR, "\nstart address !\n");
 				main_status = FALSE;
 			} else {
 				/* Check that the address is 16-bytes aligned */
-				if ((main_temp &
-					ADDR_16_BYTES_ALIGNED_MASK) != 0) {
+				if ((main_temp & ADDR_16_BYTES_ALIGNED_MASK) !=
+				    0) {
 					my_printf(TERR,
 						  "\nFW load address start ");
 					my_printf(TERR,
 						  "address (0x%08X) is not ",
 						  main_temp);
-					my_printf(TERR,
-						  "16-bytes aligned !\n");
+					my_printf(TERR, "16-bytes aligned !\n");
 					main_status = FALSE;
 				} else {
-					bin_params.fw_load_addr =
-								     main_temp;
+					bin_params.fw_load_addr = main_temp;
 					bin_params.bin_params |=
-							BIN_FW_LOAD_START_ADDR;
+						BIN_FW_LOAD_START_ADDR;
 				}
 			}
-		  /* -fwep, Get the FW entry point. */
+			/* -fwep, Get the FW entry point. */
 		} else if (str_cmp_no_case(hdr_args[arg_ind], "-fwep") == 0) {
-			if ((bin_params.bin_params & BIN_FW_USER_ARM_RESET)
-								!= 0x00000000) {
-				my_printf(TERR,
-					 "\n-fwep not allowed, FW entry point");
+			if ((bin_params.bin_params & BIN_FW_USER_ARM_RESET) !=
+			    0x00000000) {
+				my_printf(
+					TERR,
+					"\n-fwep not allowed, FW entry point");
 				my_printf(TERR,
 					  " already set using -usearmrst!\n");
 				main_status = FALSE;
 			} else {
 				arg_ind++;
 				if ((hdr_args[arg_ind] == NULL) ||
-					(sscanf(hdr_args[arg_ind],
-						"%x",
-						&main_temp) != 1)) {
+				    (sscanf(hdr_args[arg_ind], "%x",
+					    &main_temp) != 1)) {
 					my_printf(TERR,
 						  "\nCan't read FW E-Point\n");
 					main_status = FALSE;
 				} else {
-					bin_params.fw_ep =
-								main_temp;
+					bin_params.fw_ep = main_temp;
 					bin_params.bin_params |=
-							BIN_FW_ENTRY_POINT;
+						BIN_FW_ENTRY_POINT;
 				}
 			}
-		  /*
-		   * -crcstart, Get the address from where to calculate
-		   * the FW CRC.
-		   */
-		} else if (str_cmp_no_case(hdr_args[arg_ind],
-					   "-crcstart") == 0) {
+			/*
+			 * -crcstart, Get the address from where to calculate
+			 * the FW CRC.
+			 */
+		} else if (str_cmp_no_case(hdr_args[arg_ind], "-crcstart") ==
+			   0) {
 			arg_ind++;
 			if ((hdr_args[arg_ind] == NULL) ||
-				(sscanf(hdr_args[arg_ind],
-					"%x",
-					&main_temp) != 1)) {
-						my_printf(TERR,
-						  "\nCannot read FW CRC");
-						my_printf(TERR,
-						  " start address !\n");
+			    (sscanf(hdr_args[arg_ind], "%x", &main_temp) !=
+			     1)) {
+				my_printf(TERR, "\nCannot read FW CRC");
+				my_printf(TERR, " start address !\n");
 				main_status = FALSE;
 			} else {
 				bin_params.fw_err_detec_e_addr =
 					bin_params.fw_err_detec_e_addr -
-					bin_params.fw_err_detec_s_addr
-					+ main_temp;
-				bin_params.fw_err_detec_s_addr =
-								main_temp;
+					bin_params.fw_err_detec_s_addr +
+					main_temp;
+				bin_params.fw_err_detec_s_addr = main_temp;
 				bin_params.bin_params |= BIN_FW_CKS_START;
 			}
-		  /* -crcsize,  Get the area size that need to be CRCed. */
-		} else if (str_cmp_no_case(hdr_args[arg_ind],
-					   "-crcsize") == 0) {
+			/* -crcsize,  Get the area size that need to be CRCed.
+			 */
+		} else if (str_cmp_no_case(hdr_args[arg_ind], "-crcsize") ==
+			   0) {
 			arg_ind++;
 			main_temp = 0x00;
 			if (hdr_args[arg_ind] == NULL)
 				end_ptr = NULL;
 			else
-				main_temp = strtol(hdr_args[arg_ind],
-						   &end_ptr, 16);
+				main_temp =
+					strtol(hdr_args[arg_ind], &end_ptr, 16);
 
 			if (hdr_args[arg_ind] == end_ptr) {
 				my_printf(TERR,
@@ -604,8 +582,8 @@ int main(int argc, char *argv[])
 				main_status = FALSE;
 			} else {
 				bin_params.fw_err_detec_e_addr =
-					bin_params.fw_err_detec_s_addr
-					+ main_temp - 1;
+					bin_params.fw_err_detec_s_addr +
+					main_temp - 1;
 				bin_params.bin_params |= BIN_FW_CKS_SIZE;
 			}
 		}
@@ -613,9 +591,8 @@ int main(int argc, char *argv[])
 		else if (str_cmp_no_case(hdr_args[arg_ind], "-fwlen") == 0) {
 			arg_ind++;
 			if ((hdr_args[arg_ind] == NULL) ||
-				(sscanf(hdr_args[arg_ind],
-					"%x",
-					&main_temp) != 1)) {
+			    (sscanf(hdr_args[arg_ind], "%x", &main_temp) !=
+			     1)) {
 				my_printf(TERR, "\nCannot read FW length !\n");
 				main_status = FALSE;
 			} else {
@@ -624,25 +601,24 @@ int main(int argc, char *argv[])
 			}
 		}
 		/* flashsize, Get the flash size. */
-		else if (str_cmp_no_case(hdr_args[arg_ind],
-					 "-flashsize") == 0) {
+		else if (str_cmp_no_case(hdr_args[arg_ind], "-flashsize") ==
+			 0) {
 			arg_ind++;
 			if ((hdr_args[arg_ind] == NULL) ||
-				(sscanf(hdr_args[arg_ind],
-					"%d",
-					&main_temp) != 1)) {
+			    (sscanf(hdr_args[arg_ind], "%d", &main_temp) !=
+			     1)) {
 				my_printf(TERR, "\nCannot read Flash size !\n");
 				main_status = FALSE;
 			} else
 				bin_params.flash_size = main_temp;
-		  /* -apisign, Get the method for error detect calculation. */
-		} else if (str_cmp_no_case(hdr_args[arg_ind],
-					   "-apisign") == 0) {
+			/* -apisign, Get the method for error detect
+			 * calculation. */
+		} else if (str_cmp_no_case(hdr_args[arg_ind], "-apisign") ==
+			   0) {
 			arg_ind++;
 			if ((hdr_args[arg_ind] == NULL) ||
-				(sscanf(hdr_args[arg_ind],
-					"%s",
-					main_str_temp) != 1)) {
+			    (sscanf(hdr_args[arg_ind], "%s", main_str_temp) !=
+			     1)) {
 				my_printf(TERR, "\nCannot read API sign, CRC,");
 				my_printf(TERR, " CheckSum or None. !\n");
 				main_status = FALSE;
@@ -666,23 +642,21 @@ int main(int argc, char *argv[])
 						  main_str_temp);
 					main_status = FALSE;
 				}
-
 			}
-		  /* -pointer,  Get the FW image address. */
-		} else if (str_cmp_no_case(hdr_args[arg_ind],
-					   "-pointer") == 0) {
+			/* -pointer,  Get the FW image address. */
+		} else if (str_cmp_no_case(hdr_args[arg_ind], "-pointer") ==
+			   0) {
 			arg_ind++;
 			if ((hdr_args[arg_ind] == NULL) ||
-				(sscanf(hdr_args[arg_ind],
-					"%x",
-					&main_temp) != 1)) {
+			    (sscanf(hdr_args[arg_ind], "%x", &main_temp) !=
+			     1)) {
 				my_printf(TERR,
 					  "\nCannot read FW Image address !\n");
 				main_status = FALSE;
 			} else {
 				/* Check that the address is 16-bytes aligned */
-				if ((main_temp & ADDR_16_BYTES_ALIGNED_MASK)
-									!= 0) {
+				if ((main_temp & ADDR_16_BYTES_ALIGNED_MASK) !=
+				    0) {
 					my_printf(TERR,
 						  "\nFW Image address (0x%08X)"
 						  " isn't 16-bytes aligned !\n",
@@ -696,8 +670,7 @@ int main(int argc, char *argv[])
 						  main_temp);
 					my_printf(TERR,
 						  "is higher from flash size");
-					my_printf(TERR,
-						  " (0x%08X) !\n",
+					my_printf(TERR, " (0x%08X) !\n",
 						  MAX_FLASH_SIZE);
 					main_status = FALSE;
 				} else {
@@ -713,8 +686,8 @@ int main(int argc, char *argv[])
 			if (hdr_args[arg_ind] == NULL)
 				end_ptr = NULL;
 			else
-				main_temp = strtol(hdr_args[arg_ind],
-						   &end_ptr, 16);
+				main_temp =
+					strtol(hdr_args[arg_ind], &end_ptr, 16);
 
 			if (hdr_args[arg_ind] == end_ptr) {
 				my_printf(TERR, "\nCannot read BootLoader");
@@ -722,11 +695,12 @@ int main(int argc, char *argv[])
 				main_status = FALSE;
 			} else {
 				/* Check that the address is 16-bytes aligned */
-				if ((main_temp & ADDR_16_BYTES_ALIGNED_MASK)
-									!= 0) {
-					my_printf(TERR,
-						  "\nFW Image address (0x%08X) ",
-						  main_temp);
+				if ((main_temp & ADDR_16_BYTES_ALIGNED_MASK) !=
+				    0) {
+					my_printf(
+						TERR,
+						"\nFW Image address (0x%08X) ",
+						main_temp);
 					my_printf(TERR,
 						  "is not 16-bytes aligned!\n");
 				}
@@ -737,8 +711,7 @@ int main(int argc, char *argv[])
 						  main_temp);
 					my_printf(TERR,
 						  " is higher from flash size");
-					my_printf(TERR,
-						  " (0x%08X) !\n",
+					my_printf(TERR, " (0x%08X) !\n",
 						  MAX_FLASH_SIZE);
 					main_status = FALSE;
 				} else {
@@ -747,27 +720,25 @@ int main(int argc, char *argv[])
 				}
 			}
 		} else {
-			my_printf(TERR,
-				  "\nUnknown flag: %s\n",
+			my_printf(TERR, "\nUnknown flag: %s\n",
 				  hdr_args[arg_ind]);
 			main_status = FALSE;
 		}
 	}
 
 	/*
-	* If the input and output file have the same name then exit with error.
-	*/
+	 * If the input and output file have the same name then exit with error.
+	 */
 	if (strcmp(output_file_name, input_file_name) == 0) {
 		my_printf(TINF,
-			"Input file name (%s) should be differed from\n",
-			input_file_name);
+			  "Input file name (%s) should be differed from\n",
+			  input_file_name);
 		my_printf(TINF, "Output file name (%s).\n", output_file_name);
 		main_status = FALSE;
 	}
 
 	/* No problems reading argv? So go on... */
 	if (main_status) {
-
 		/* if output file already exist, then delete it. */
 		tmp_file = fopen(output_file_name, "w");
 		if (tmp_file != NULL)
@@ -802,18 +773,17 @@ int main(int argc, char *argv[])
 	/* Say Bye Bye */
 	if (main_status) {
 		my_printf(TPAS, "\n\n******************************");
-		my_printf(TPAS,   "\n***    SUCCESS     ***");
-		my_printf(TPAS,   "\n******************************\n");
+		my_printf(TPAS, "\n***    SUCCESS     ***");
+		my_printf(TPAS, "\n******************************\n");
 
 		exit(EXIT_SUCCESS);
 	} else {
 		my_printf(TERR, "\n\n******************************");
-		my_printf(TERR,   "\n***    FAILED      ***");
-		my_printf(TERR,   "\n******************************\n");
+		my_printf(TERR, "\n***    FAILED      ***");
+		my_printf(TERR, "\n******************************\n");
 
 		exit(EXIT_FAILURE);
 	}
-
 }
 
 /*
@@ -930,12 +900,9 @@ void exit_with_usage(void)
  * Description: Copy the source file to the end of the destination file.
  *--------------------------------------------------------------------------
  */
-int copy_file_to_file(char *dst_file_name,
-		      char *src_file_name,
-		      int offset,
-		      int  origin)
+int copy_file_to_file(char *dst_file_name, char *src_file_name, int offset,
+		      int origin)
 {
-
 	int index = 0;
 	int result = 0;
 	unsigned char local_val;
@@ -1030,12 +997,9 @@ void my_printf(int error_level, char *fmt, ...)
  * Description:	 Writes to ELF or BIN files - whatever is open
  *--------------------------------------------------------------------------
  */
-int write_to_file(unsigned int write_value,
-		  unsigned int offset,
-		  unsigned char num_of_bytes,
-		  char *print_string)
+int write_to_file(unsigned int write_value, unsigned int offset,
+		  unsigned char num_of_bytes, char *print_string)
 {
-
 	int result = 0;
 	int index;
 	unsigned int localValue4;
@@ -1046,32 +1010,23 @@ int write_to_file(unsigned int write_value,
 		return FALSE;
 
 	switch (num_of_bytes) {
-	case(1):
+	case (1):
 		localValue1 = (unsigned char)write_value;
-		result = (int)(fwrite(&localValue1, 1,
-							  1, g_hfd_pointer));
-	break;
-	case(2):
+		result = (int)(fwrite(&localValue1, 1, 1, g_hfd_pointer));
+		break;
+	case (2):
 		localValue2 = (unsigned short)write_value;
-		result = (int)(fwrite(&localValue2,
-				      2,
-				      1,
-				      g_hfd_pointer));
+		result = (int)(fwrite(&localValue2, 2, 1, g_hfd_pointer));
 		break;
-	case(4):
+	case (4):
 		localValue4 = write_value;
-		result = (int)(fwrite(&localValue4,
-				      4,
-				      1,
-				      g_hfd_pointer));
+		result = (int)(fwrite(&localValue4, 4, 1, g_hfd_pointer));
 		break;
 	default:
 		/* Pad the same value N times. */
 		localValue1 = (unsigned char)write_value;
 		for (index = 0; index < num_of_bytes; index++)
-			result = (int)(fwrite(&localValue1,
-					      1,
-					      1,
+			result = (int)(fwrite(&localValue1, 1, 1,
 					      g_hfd_pointer));
 		break;
 	}
@@ -1079,18 +1034,15 @@ int write_to_file(unsigned int write_value,
 	my_printf(TINF, "\nIn write_to_file  - %s", print_string);
 
 	if (result) {
-		my_printf(TINF,
-			" - Offset %2d - value 0x%x",
-			offset, write_value);
+		my_printf(TINF, " - Offset %2d - value 0x%x", offset,
+			  write_value);
 	} else {
-		my_printf(TERR,
-			"\n\nCouldn't write %x to file at %x\n\n",
-			write_value, offset);
+		my_printf(TERR, "\n\nCouldn't write %x to file at %x\n\n",
+			  write_value, offset);
 		return FALSE;
 	}
 
 	return TRUE;
-
 }
 
 /*
@@ -1101,10 +1053,8 @@ int write_to_file(unsigned int write_value,
  * Description : Reads from open BIN file
  *--------------------------------------------------------------------------
  */
-int read_from_file(unsigned int offset,
-				   unsigned char size_to_read,
-				   unsigned int *read_value,
-				   char *print_string)
+int read_from_file(unsigned int offset, unsigned char size_to_read,
+		   unsigned int *read_value, char *print_string)
 {
 	int result;
 	unsigned int localValue4;
@@ -1115,25 +1065,16 @@ int read_from_file(unsigned int offset,
 		return FALSE;
 
 	switch (size_to_read) {
-	case(1):
-		result = (int)(fread(&localValue1,
-				     1,
-				     1,
-				     input_file_pointer));
+	case (1):
+		result = (int)(fread(&localValue1, 1, 1, input_file_pointer));
 		*read_value = localValue1;
 		break;
-	case(2):
-		result = (int)(fread(&localValue2,
-				     2,
-				     1,
-				     input_file_pointer));
+	case (2):
+		result = (int)(fread(&localValue2, 2, 1, input_file_pointer));
 		*read_value = localValue2;
 		break;
-	case(4):
-		result = (int)(fread(&localValue4,
-				     4,
-				     1,
-				     input_file_pointer));
+	case (4):
+		result = (int)(fread(&localValue4, 4, 1, input_file_pointer));
 		*read_value = localValue4;
 		break;
 	default:
@@ -1145,13 +1086,10 @@ int read_from_file(unsigned int offset,
 	my_printf(TINF, "\nIn read_from_file - %s", print_string);
 
 	if (result) {
-		my_printf(TINF,
-			" - Offset %d - value %x",
-			offset, *read_value);
+		my_printf(TINF, " - Offset %d - value %x", offset, *read_value);
 	} else {
-		my_printf(TERR,
-			"\n\nCouldn't read from file at %x\n\n",
-			offset);
+		my_printf(TERR, "\n\nCouldn't read from file at %x\n\n",
+			  offset);
 		return FALSE;
 	}
 
@@ -1210,12 +1148,11 @@ void finalize_calculation(unsigned int *check_sum_crc)
  *		 given the previous checksum\crc
  *--------------------------------------------------------------------------
  */
-void update_calculation(unsigned int *check_sum_crc,
-						unsigned char byte_to_add)
+void update_calculation(unsigned int *check_sum_crc, unsigned char byte_to_add)
 {
 	switch (g_calc_type) {
 	case CALC_TYPE_NONE:
-			/* Do nothing */
+		/* Do nothing */
 		break;
 	case CALC_TYPE_CHECKSUM:
 		*check_sum_crc += byte_to_add;
@@ -1328,25 +1265,22 @@ int main_bin(struct tbinparams binary_params)
 		bin_fw_offset = binary_params.fw_hdr_offset + HEADER_SIZE;
 
 	my_printf(TINF, "\nBIN file:  %s, size: %d (0x%x) bytes\n",
-			  input_file_name,
-			  bin_file_size_bytes,
-			  bin_file_size_bytes);
+		  input_file_name, bin_file_size_bytes, bin_file_size_bytes);
 
 	/* Check validity of FW header offset. */
 	if (((int)binary_params.fw_hdr_offset < 0) ||
-		(binary_params.fw_hdr_offset > bin_file_size_bytes)) {
+	    (binary_params.fw_hdr_offset > bin_file_size_bytes)) {
 		my_printf(TERR,
 			  "\nFW header offset 0x%08x (%d) should be in the"
 			  " range of 0 and file size (%d).\n",
 			  binary_params.fw_hdr_offset,
-			  binary_params.fw_hdr_offset,
-			  bin_file_size_bytes);
+			  binary_params.fw_hdr_offset, bin_file_size_bytes);
 		return FALSE;
 	}
 
 	/* Create the header file in the same directory as the input file. */
 	if (!splice_into_path(g_hdr_input_name, input_file_name,
-		sizeof(g_hdr_input_name), "hdr_"))
+			      sizeof(g_hdr_input_name), "hdr_"))
 		return FALSE;
 	g_hfd_pointer = fopen(g_hdr_input_name, "w+b");
 	if (g_hfd_pointer == NULL) {
@@ -1356,7 +1290,7 @@ int main_bin(struct tbinparams binary_params)
 
 	if (strlen(output_file_name) == 0) {
 		if (!splice_into_path(output_file_name, input_file_name,
-			sizeof(output_file_name), "out_"))
+				      sizeof(output_file_name), "out_"))
 			return FALSE;
 	}
 
@@ -1368,15 +1302,12 @@ int main_bin(struct tbinparams binary_params)
 	 *********************************************************************
 	 */
 	/* Write the ancore. */
-	if (!write_to_file(FW_HDR_ANCHOR,
-			   HDR_ANCHOR_OFFSET,
-			   4,
+	if (!write_to_file(FW_HDR_ANCHOR, HDR_ANCHOR_OFFSET, 4,
 			   "HDR - FW Header ANCHOR		  "))
 		return FALSE;
 
 	/* Write the extended anchor. */
 	if (binary_params.bin_params & BIN_FW_HDR_CRC_DISABLE) {
-
 		/* Write the ancore and the extended anchor. */
 		if (!write_to_file(FW_HDR_EXT_ANCHOR_DISABLE,
 				   HDR_EXTENDED_ANCHOR_OFFSET, 2,
@@ -1409,14 +1340,13 @@ int main_bin(struct tbinparams binary_params)
 		break;
 	default:
 		my_printf(TERR, "\n\nInvalid SPI Flash MAX clock (%d MHz) ",
-				  binary_params.spi_max_clk);
+			  binary_params.spi_max_clk);
 		my_printf(TERR, "- it should be 20, 25, 33, 40 or 50 MHz");
 		return FALSE;
 	}
 
 	/* If SPI clock ratio set for MRIDER15, then it is error. */
 	if ((binary_params.spi_clk_ratio != 0x00) && (is_mrider15 == TRUE)) {
-
 		my_printf(TERR, "\nspiclkratio is not relevant for");
 		my_printf(TERR, " npcx5mng chips family !\n");
 
@@ -1439,13 +1369,13 @@ int main_bin(struct tbinparams binary_params)
 		break;
 	default:
 		my_printf(TERR, "\n\nInvalid SPI Core Clock Ratio (%d) ",
-			binary_params.spi_clk_ratio);
+			  binary_params.spi_clk_ratio);
 		my_printf(TERR, "- it should be 1 or 2");
 		return FALSE;
 	}
 
 	if (!write_to_file(tmp_param, HDR_SPI_MAX_CLK_OFFSET, 1,
-					   "HDR - SPI flash MAX Clock	  "))
+			   "HDR - SPI flash MAX Clock	  "))
 		return FALSE;
 
 	/* Write the SPI flash Read Mode. */
@@ -1453,7 +1383,6 @@ int main_bin(struct tbinparams binary_params)
 	/* If needed, set the unlimited burst bit. */
 	if (binary_params.bin_params & BIN_UNLIM_BURST_ENABLE) {
 		if (is_mrider15 == TRUE) {
-
 			my_printf(TERR, "\nunlimburst is not relevant for");
 			my_printf(TERR, " npcx5mng chips family !\n");
 
@@ -1462,35 +1391,29 @@ int main_bin(struct tbinparams binary_params)
 
 		tmp_param |= SPI_UNLIMITED_BURST_ENABLE;
 	}
-	if (!write_to_file(tmp_param,
-					   HDR_SPI_READ_MODE_OFFSET, 1,
-					   "HDR - SPI flash Read Mode	   "))
+	if (!write_to_file(tmp_param, HDR_SPI_READ_MODE_OFFSET, 1,
+			   "HDR - SPI flash Read Mode	   "))
 		return FALSE;
 
 	/* Write the error detection configuration. */
 	if (binary_params.bin_params & BIN_FW_CRC_DISABLE) {
 		if (!write_to_file(FW_CRC_DISABLE,
-				   HDR_ERR_DETECTION_CONF_OFFSET,
-				   1,
+				   HDR_ERR_DETECTION_CONF_OFFSET, 1,
 				   "HDR - FW CRC Disabled		   "))
 			return FALSE;
 	} else {
 		/* Write the ancore and the extended anchor. */
-		if (!write_to_file(FW_CRC_ENABLE,
-				   HDR_ERR_DETECTION_CONF_OFFSET, 1,
-				   "HDR - FW CRC Enabled		  "))
+		if (!write_to_file(FW_CRC_ENABLE, HDR_ERR_DETECTION_CONF_OFFSET,
+				   1, "HDR - FW CRC Enabled		  "))
 			return FALSE;
 	}
 
 	/* FW entry point should be between the FW load address and RAM size */
-	if ((binary_params.fw_load_addr >
-					(g_ram_start_address + g_ram_size)) ||
-		(binary_params.fw_load_addr < g_ram_start_address)) {
-		my_printf(TERR,
-			  "\nFW load address (0x%08x) should be between ",
+	if ((binary_params.fw_load_addr > (g_ram_start_address + g_ram_size)) ||
+	    (binary_params.fw_load_addr < g_ram_start_address)) {
+		my_printf(TERR, "\nFW load address (0x%08x) should be between ",
 			  binary_params.fw_load_addr);
-		my_printf(TERR,
-			  "start (0x%08x) and end (0x%08x) of RAM ).",
+		my_printf(TERR, "start (0x%08x) and end (0x%08x) of RAM ).",
 			  g_ram_start_address,
 			  (g_ram_start_address + g_ram_size));
 
@@ -1499,8 +1422,8 @@ int main_bin(struct tbinparams binary_params)
 
 	/* Write the FW load start address */
 	if (!write_to_file(binary_params.fw_load_addr,
-					   HDR_FW_LOAD_START_ADDR_OFFSET, 4,
-					   "HDR - FW load start address	 "))
+			   HDR_FW_LOAD_START_ADDR_OFFSET, 4,
+			   "HDR - FW load start address	 "))
 		return FALSE;
 
 	/*
@@ -1512,25 +1435,22 @@ int main_bin(struct tbinparams binary_params)
 		 * size of the binary file minus the offset of the start of the
 		 * FW.
 		 */
-		binary_params.fw_len = bin_file_size_bytes-bin_fw_offset;
+		binary_params.fw_len = bin_file_size_bytes - bin_fw_offset;
 	}
 
 	if ((int)binary_params.fw_len < 0) {
 		my_printf(TERR,
 			  "\nFW length %d (0x%08x) should be greater than 0x0.",
-			  binary_params.fw_len,
-			  binary_params.fw_len);
+			  binary_params.fw_len, binary_params.fw_len);
 		return FALSE;
 	}
 
 	if (((int)binary_params.fw_len >
-				(bin_file_size_bytes - bin_fw_offset)) ||
-		((int)binary_params.fw_len > g_ram_size)) {
-		my_printf(TERR,
-			  "\nFW length %d (0x%08x) should be within the",
+	     (bin_file_size_bytes - bin_fw_offset)) ||
+	    ((int)binary_params.fw_len > g_ram_size)) {
+		my_printf(TERR, "\nFW length %d (0x%08x) should be within the",
 			  binary_params.fw_len, binary_params.fw_len);
-		my_printf(TERR,
-			  " input-file (related to the FW offset)");
+		my_printf(TERR, " input-file (related to the FW offset)");
 		my_printf(TERR,
 			  "\n (0x%08x) and within the RAM (RAM size: 0x%08x).",
 			  (bin_file_size_bytes - bin_fw_offset), g_ram_size);
@@ -1538,61 +1458,48 @@ int main_bin(struct tbinparams binary_params)
 	}
 
 	if ((binary_params.bin_params & BIN_FW_USER_ARM_RESET) != 0x00000000) {
-		read_from_file((bin_fw_offset + ARM_FW_ENTRY_POINT_OFFSET),
-			4,
-			&binary_params.fw_ep,
-			"read FW entry point for FW image ");
-
-		if ((binary_params.fw_ep <
-				binary_params.fw_load_addr) ||
-			(binary_params.fw_ep >
-				(binary_params.fw_load_addr +
-						binary_params.fw_len))) {
+		read_from_file((bin_fw_offset + ARM_FW_ENTRY_POINT_OFFSET), 4,
+			       &binary_params.fw_ep,
+			       "read FW entry point for FW image ");
+
+		if ((binary_params.fw_ep < binary_params.fw_load_addr) ||
+		    (binary_params.fw_ep >
+		     (binary_params.fw_load_addr + binary_params.fw_len))) {
 			my_printf(TERR,
 				  "\nFW entry point (0x%08x) should be between",
 				  binary_params.fw_ep);
-			my_printf(TERR,
-				  " the FW load address (0x%08x) ",
+			my_printf(TERR, " the FW load address (0x%08x) ",
 				  binary_params.fw_load_addr);
-			my_printf(TERR,
-				  "and FW length (0x%08x).\n",
+			my_printf(TERR, "and FW length (0x%08x).\n",
 				  (binary_params.fw_load_addr +
-							binary_params.fw_len));
+				   binary_params.fw_len));
 			return FALSE;
 		}
 	}
 
 	/* FW entry point should be between the FW load address and RAM size */
-	if ((binary_params.fw_ep <
-				binary_params.fw_load_addr) ||
-		(binary_params.fw_ep >
-				(binary_params.fw_load_addr +
-						binary_params.fw_len))) {
+	if ((binary_params.fw_ep < binary_params.fw_load_addr) ||
+	    (binary_params.fw_ep >
+	     (binary_params.fw_load_addr + binary_params.fw_len))) {
 		if (((binary_params.bin_params & BIN_FW_ENTRY_POINT) ==
-								0x00000000) &&
-			((binary_params.bin_params &
-			  BIN_FW_LOAD_START_ADDR) != 0x00000000)) {
-			binary_params.fw_ep =
-					binary_params.fw_load_addr;
+		     0x00000000) &&
+		    ((binary_params.bin_params & BIN_FW_LOAD_START_ADDR) !=
+		     0x00000000)) {
+			binary_params.fw_ep = binary_params.fw_load_addr;
 		} else {
-			my_printf(TERR,
-				  "\nFW entry point (0x%08x) should be ",
+			my_printf(TERR, "\nFW entry point (0x%08x) should be ",
 				  binary_params.fw_ep);
-			my_printf(TERR,
-				  "\between the FW load address (0x%08x)",
+			my_printf(TERR, "\between the FW load address (0x%08x)",
 				  binary_params.fw_load_addr);
-			my_printf(TERR,
-				  " and FW length (0x%08x).\n",
+			my_printf(TERR, " and FW length (0x%08x).\n",
 				  (binary_params.fw_load_addr +
-							binary_params.fw_len));
+				   binary_params.fw_len));
 			return FALSE;
 		}
 	}
 
 	/* Write the FW entry point */
-	if (!write_to_file(binary_params.fw_ep,
-			   HDR_FW_ENTRY_POINT_OFFSET,
-			   4,
+	if (!write_to_file(binary_params.fw_ep, HDR_FW_ENTRY_POINT_OFFSET, 4,
 			   "HDR - FW Entry point		 "))
 		return FALSE;
 
@@ -1602,17 +1509,15 @@ int main_bin(struct tbinparams binary_params)
 		 * In case the size was not set, then CRC end address is
 		 * the size of the binary file.
 		 */
-		binary_params.fw_err_detec_e_addr =
-						binary_params.fw_len - 1;
+		binary_params.fw_err_detec_e_addr = binary_params.fw_len - 1;
 	} else {
 		/* CRC end address should be less than FW length. */
 		if (binary_params.fw_err_detec_e_addr >
-					(binary_params.fw_len - 1)) {
+		    (binary_params.fw_len - 1)) {
 			my_printf(TERR,
 				  "\nCRC end address (0x%08x) should be less ",
 				  binary_params.fw_err_detec_e_addr);
-			my_printf(TERR,
-				  "than the FW length %d (0x%08x)",
+			my_printf(TERR, "than the FW length %d (0x%08x)",
 				  (binary_params.fw_len),
 				  (binary_params.fw_len));
 			return FALSE;
@@ -1621,40 +1526,35 @@ int main_bin(struct tbinparams binary_params)
 
 	/* Check CRC start and end addresses. */
 	if (binary_params.fw_err_detec_s_addr >
-					binary_params.fw_err_detec_e_addr) {
+	    binary_params.fw_err_detec_e_addr) {
 		my_printf(TERR,
 			  "\nCRC start address (0x%08x) should be less or ",
 			  binary_params.fw_err_detec_s_addr);
 		my_printf(TERR,
 			  "equal to CRC end address (0x%08x)\nPlease check ",
 			  binary_params.fw_err_detec_e_addr);
-		my_printf(TERR,
-			  "CRC start address and CRC size arguments.");
+		my_printf(TERR, "CRC start address and CRC size arguments.");
 		return FALSE;
 	}
 
 	/* CRC start addr should be between the FW load address and RAM size */
-	if (binary_params.fw_err_detec_s_addr >
-				binary_params.fw_len) {
+	if (binary_params.fw_err_detec_s_addr > binary_params.fw_len) {
 		my_printf(TERR, "\nCRC start address (0x%08x) should ",
 			  binary_params.fw_err_detec_s_addr);
-		my_printf(TERR, "be FW length (0x%08x).",
-			  binary_params.fw_len);
+		my_printf(TERR, "be FW length (0x%08x).", binary_params.fw_len);
 		return FALSE;
 	}
 
 	/* Write the CRC start address */
 	if (!write_to_file(binary_params.fw_err_detec_s_addr,
-			   HDR_FW_ERR_DETECT_START_ADDR_OFFSET,
-			   4,
+			   HDR_FW_ERR_DETECT_START_ADDR_OFFSET, 4,
 			   "HDR - FW CRC Start			 "))
 		return FALSE;
 
 	/* CRC end addr should be between the CRC start address and RAM size */
 	if ((binary_params.fw_err_detec_e_addr <
-				binary_params.fw_err_detec_s_addr) ||
-		(binary_params.fw_err_detec_e_addr >
-				binary_params.fw_len)) {
+	     binary_params.fw_err_detec_s_addr) ||
+	    (binary_params.fw_err_detec_e_addr > binary_params.fw_len)) {
 		my_printf(TERR,
 			  "\nCRC end address (0x%08x) should be between the ",
 			  binary_params.fw_err_detec_e_addr);
@@ -1667,8 +1567,7 @@ int main_bin(struct tbinparams binary_params)
 
 	/* Write the CRC end address */
 	if (!write_to_file(binary_params.fw_err_detec_e_addr,
-			   HDR_FW_ERR_DETECT_END_ADDR_OFFSET,
-			   4,
+			   HDR_FW_ERR_DETECT_END_ADDR_OFFSET, 4,
 			   "HDR - FW CRC End			 "))
 		return FALSE;
 
@@ -1678,22 +1577,18 @@ int main_bin(struct tbinparams binary_params)
 		binary_params.fw_len += (16 - tmp_param);
 
 	/* FW load address + FW length should be less than the RAM size. */
-	if ((binary_params.fw_load_addr +
-			binary_params.fw_len) >
-					(g_ram_start_address + g_ram_size)) {
+	if ((binary_params.fw_load_addr + binary_params.fw_len) >
+	    (g_ram_start_address + g_ram_size)) {
 		my_printf(TERR,
 			  "\nFW load address + FW length should (0x%08x) be ",
 			  (binary_params.fw_load_addr + binary_params.fw_len));
-		my_printf(TERR,
-			  "less than the RAM size (0x%08x).",
+		my_printf(TERR, "less than the RAM size (0x%08x).",
 			  (g_ram_start_address + g_ram_size));
 		return FALSE;
 	}
 
 	/* Write the FW length */
-	if (!write_to_file(binary_params.fw_len,
-			   HDR_FW_LENGTH_OFFSET,
-			   4,
+	if (!write_to_file(binary_params.fw_len, HDR_FW_LENGTH_OFFSET, 4,
 			   "HDR - FW Length			   "))
 		return FALSE;
 
@@ -1716,30 +1611,26 @@ int main_bin(struct tbinparams binary_params)
 		break;
 	default:
 		my_printf(TERR, "\n\nInvalid Flash size (%d MBytes) -",
-				  binary_params.flash_size);
+			  binary_params.flash_size);
 		my_printf(TERR, " it should be 1, 2, 4, 8 or 16 MBytes\n");
 		return FALSE;
 	}
-	if (!write_to_file(tmp_param,
-			   HDR_FLASH_SIZE_OFFSET,
-			   1,
+	if (!write_to_file(tmp_param, HDR_FLASH_SIZE_OFFSET, 1,
 			   "HDR - Flash size			 "))
 
 		return FALSE;
 
 	/* Write the reserved bytes. */
 	if (!write_to_file(PAD_VALUE, HDR_RESERVED, 26,
-					   "HDR - Reserved (26 bytes)	  "))
+			   "HDR - Reserved (26 bytes)	  "))
 		return FALSE;
 
-
 	/* Refresh the FW header bin file in order to calculate CRC */
 	if (g_hfd_pointer) {
 		fclose(g_hfd_pointer);
 		g_hfd_pointer = fopen(g_hdr_input_name, "r+b");
 		if (g_hfd_pointer == NULL) {
-			my_printf(TERR,
-				  "\n\nCannot open %s\n\n",
+			my_printf(TERR, "\n\nCannot open %s\n\n",
 				  input_file_name);
 			return FALSE;
 		}
@@ -1757,9 +1648,7 @@ int main_bin(struct tbinparams binary_params)
 		binary_params.hdr_crc = 0;
 
 	/* Write FW header CRC to header file */
-	if (!write_to_file(binary_params.hdr_crc,
-			   HDR_FW_HEADER_SIG_OFFSET,
-			   4,
+	if (!write_to_file(binary_params.hdr_crc, HDR_FW_HEADER_SIG_OFFSET, 4,
 			   "HDR - Header CRC				"))
 		return FALSE;
 
@@ -1767,11 +1656,11 @@ int main_bin(struct tbinparams binary_params)
 	if ((binary_params.bin_params & BIN_FW_CRC_DISABLE) == 0) {
 		/* Calculate ... */
 		g_calc_type = CALC_TYPE_CRC;
-		if (!calc_firmware_csum_bin(&binary_params.fw_crc,
-			(bin_fw_offset +
-				binary_params.fw_err_detec_s_addr),
-			(binary_params.fw_err_detec_e_addr -
-				binary_params.fw_err_detec_s_addr+1)))
+		if (!calc_firmware_csum_bin(
+			    &binary_params.fw_crc,
+			    (bin_fw_offset + binary_params.fw_err_detec_s_addr),
+			    (binary_params.fw_err_detec_e_addr -
+			     binary_params.fw_err_detec_s_addr + 1)))
 			return FALSE;
 
 		g_calc_type = CALC_TYPE_NONE;
@@ -1779,9 +1668,7 @@ int main_bin(struct tbinparams binary_params)
 		binary_params.fw_crc = 0;
 
 	/* Write the FW CRC into file header file */
-	if (!write_to_file(binary_params.fw_crc,
-			   HDR_FW_IMAGE_SIG_OFFSET,
-			   4,
+	if (!write_to_file(binary_params.fw_crc, HDR_FW_IMAGE_SIG_OFFSET, 4,
 			   "HDR - FW CRC				   "))
 		return FALSE;
 
@@ -1802,22 +1689,14 @@ int main_bin(struct tbinparams binary_params)
 		fclose(output_file_pointer);
 
 	if ((binary_params.bin_params & BIN_FW_HDR_OFFSET) != 0) {
-		copy_file_to_file(output_file_name,
-				  input_file_name,
-				  0,
-				  SEEK_SET);
-		copy_file_to_file(output_file_name,
-				  g_hdr_input_name,
-				  binary_params.fw_hdr_offset,
+		copy_file_to_file(output_file_name, input_file_name, 0,
 				  SEEK_SET);
+		copy_file_to_file(output_file_name, g_hdr_input_name,
+				  binary_params.fw_hdr_offset, SEEK_SET);
 	} else {
-		copy_file_to_file(output_file_name,
-				  g_hdr_input_name,
-				  0,
+		copy_file_to_file(output_file_name, g_hdr_input_name, 0,
 				  SEEK_END);
-		copy_file_to_file(output_file_name,
-				  input_file_name,
-				  0,
+		copy_file_to_file(output_file_name, input_file_name, 0,
 				  SEEK_END);
 	}
 
@@ -1848,20 +1727,16 @@ int calc_header_crc_bin(unsigned int *p_cksum)
 	if (fseek(g_hfd_pointer, 0x00000000, SEEK_SET) < 0)
 		return FALSE;
 
-	if (fread(g_header_array,
-		  HEADER_SIZE,
-		  1,
-		  g_hfd_pointer) != 1)
+	if (fread(g_header_array, HEADER_SIZE, 1, g_hfd_pointer) != 1)
 		return FALSE;
 
 	for (i = 0; i < (HEADER_SIZE - HEADER_CRC_FIELDS_SIZE); i++) {
-
 		/*
 		 * I had once the Verbose check inside the my_printf, but
 		 * it made ECST run sloooowwwwwly....
 		 */
 		if (g_verbose == SUPER_VERBOSE) {
-			if (i%line_print_size == 0)
+			if (i % line_print_size == 0)
 				my_printf(TDBG, "\n[%.4x]: ", i);
 
 			my_printf(TDBG, "%.2x ", g_header_array[i]);
@@ -1872,10 +1747,8 @@ int calc_header_crc_bin(unsigned int *p_cksum)
 
 		if (g_verbose == SUPER_VERBOSE) {
 			if ((i + 1) % line_print_size == 0)
-				my_printf(TDBG,
-					  "FW Header ChecksumCRC = %.8x",
-					   calc_header_checksum_crc);
-
+				my_printf(TDBG, "FW Header ChecksumCRC = %.8x",
+					  calc_header_checksum_crc);
 		}
 	}
 
@@ -1895,11 +1768,9 @@ int calc_header_crc_bin(unsigned int *p_cksum)
  * Description:	 TBD
  *******************************************************************
  */
-int calc_firmware_csum_bin(unsigned int *p_cksum,
-						   unsigned int fw_offset,
-						   unsigned int fw_length)
+int calc_firmware_csum_bin(unsigned int *p_cksum, unsigned int fw_offset,
+			   unsigned int fw_length)
 {
-
 	unsigned int i;
 	unsigned int calc_read_bytes;
 	unsigned int calc_num_of_bytes_to_read;
@@ -1912,16 +1783,12 @@ int calc_firmware_csum_bin(unsigned int *p_cksum,
 	calc_curr_position = fw_offset;
 
 	if (g_verbose == REGULAR_VERBOSE) {
-		my_printf(TINF,
-			  "\nFW Error Detect Start Dddress: 0x%08x",
+		my_printf(TINF, "\nFW Error Detect Start Dddress: 0x%08x",
 			  calc_curr_position);
-		my_printf(TINF,
-			  "\nFW Error Detect End Dddress: 0x%08x",
+		my_printf(TINF, "\nFW Error Detect End Dddress: 0x%08x",
 			  calc_curr_position + calc_num_of_bytes_to_read - 1);
-		my_printf(TINF,
-			  "\nFW Error Detect Size:  %d (0x%X)",
-			  calc_num_of_bytes_to_read,
-			  calc_num_of_bytes_to_read);
+		my_printf(TINF, "\nFW Error Detect Size:  %d (0x%X)",
+			  calc_num_of_bytes_to_read, calc_num_of_bytes_to_read);
 	}
 
 	init_calculation(&calc_fw_checksum_crc);
@@ -1932,13 +1799,10 @@ int calc_firmware_csum_bin(unsigned int *p_cksum,
 		else
 			calc_read_bytes = calc_num_of_bytes_to_read;
 
-		if (fseek(input_file_pointer,
-			calc_curr_position, SEEK_SET) < 0)
+		if (fseek(input_file_pointer, calc_curr_position, SEEK_SET) < 0)
 			return 0;
-		if (fread(g_fw_array,
-			  calc_read_bytes,
-			  1,
-			  input_file_pointer) != 1)
+		if (fread(g_fw_array, calc_read_bytes, 1, input_file_pointer) !=
+		    1)
 			return 0;
 
 		for (i = 0; i < calc_read_bytes; i++) {
@@ -1947,9 +1811,8 @@ int calc_firmware_csum_bin(unsigned int *p_cksum,
 			 * but it made ECST run sloooowwwwwly....
 			 */
 			if (g_verbose == SUPER_VERBOSE) {
-				if (i%line_print_size == 0)
-					my_printf(TDBG,
-						  "\n[%.4x]: ",
+				if (i % line_print_size == 0)
+					my_printf(TDBG, "\n[%.4x]: ",
 						  calc_curr_position + i);
 
 				my_printf(TDBG, "%.2x ", g_fw_array[i]);
@@ -1960,8 +1823,7 @@ int calc_firmware_csum_bin(unsigned int *p_cksum,
 
 			if (g_verbose == SUPER_VERBOSE) {
 				if ((i + 1) % line_print_size == 0)
-					my_printf(TDBG,
-						  "FW Checksum= %.8x",
+					my_printf(TDBG, "FW Checksum= %.8x",
 						  calc_fw_checksum_crc);
 			}
 		}
@@ -2006,24 +1868,19 @@ int main_hdr(void)
 		}
 
 		if (strlen(output_file_name) == 0)
-			strncpy(tmp_file_name,
-				input_file_name,
+			strncpy(tmp_file_name, input_file_name,
 				sizeof(tmp_file_name) - 1);
 		else {
-			copy_file_to_file(output_file_name,
-					  input_file_name,
-					  0,
+			copy_file_to_file(output_file_name, input_file_name, 0,
 					  SEEK_END);
-			strncpy(tmp_file_name,
-				output_file_name,
+			strncpy(tmp_file_name, output_file_name,
 				sizeof(tmp_file_name) - 1);
 		}
 
 		/* Open Header file */
 		g_hdr_pointer = fopen(tmp_file_name, "r+b");
 		if (g_hdr_pointer == NULL) {
-			my_printf(TERR,
-				  "\n\nCannot open %s file.\n\n",
+			my_printf(TERR, "\n\nCannot open %s file.\n\n",
 				  tmp_file_name);
 			return FALSE;
 		}
@@ -2035,10 +1892,9 @@ int main_hdr(void)
 			my_printf(TERR,
 				  "\n\nFW offset 0x%08x should be less than ",
 				  fw_offset);
-			my_printf(TERR,
-				  "file size 0x%x (%d).\n\n",
+			my_printf(TERR, "file size 0x%x (%d).\n\n",
 				  bin_file_size_bytes, bin_file_size_bytes);
-			 return FALSE;
+			return FALSE;
 		}
 
 		/* FW table should be less than file size. */
@@ -2046,7 +1902,7 @@ int main_hdr(void)
 			my_printf(TERR, "\n\nFW table 0x%08x should be less ",
 				  ptr_fw_addr);
 			my_printf(TERR, "than file size 0x%x (%d).\n\n",
-				bin_file_size_bytes, bin_file_size_bytes);
+				  bin_file_size_bytes, bin_file_size_bytes);
 			return FALSE;
 		}
 
@@ -2054,25 +1910,15 @@ int main_hdr(void)
 			return FALSE;
 
 		tmp_long_val = HDR_PTR_SIGNATURE;
-		result = (int)(fwrite(&tmp_long_val,
-				      4,
-				      1,
-				      g_hdr_pointer));
-		result |= (int)(fwrite(&ptr_fw_addr,
-				       4,
-				       1,
-				       g_hdr_pointer));
+		result = (int)(fwrite(&tmp_long_val, 4, 1, g_hdr_pointer));
+		result |= (int)(fwrite(&ptr_fw_addr, 4, 1, g_hdr_pointer));
 
 		if (result) {
-			my_printf(TINF,
-				  "\nBootLoader Header file: %s\n",
+			my_printf(TINF, "\nBootLoader Header file: %s\n",
 				  tmp_file_name);
-			my_printf(TINF,
-				  " Offset: 0x%08X,  Signature: 0x%08X,",
+			my_printf(TINF, " Offset: 0x%08X,  Signature: 0x%08X,",
 				  fw_offset, HDR_PTR_SIGNATURE);
-			my_printf(TINF,
-				  " Pointer: 0x%08X\n",
-				  ptr_fw_addr);
+			my_printf(TINF, " Pointer: 0x%08X\n", ptr_fw_addr);
 		} else {
 			my_printf(TERR,
 				  "\n\nCouldn't write signature (%x) and "
@@ -2082,7 +1928,6 @@ int main_hdr(void)
 		}
 
 	} else {
-
 		if (strlen(output_file_name) == 0) {
 			my_printf(TERR, "\n\nNo output file selected ");
 			my_printf(TERR, "for BootLoader header file.\n\n");
@@ -2092,8 +1937,7 @@ int main_hdr(void)
 		/* Open Output file */
 		g_hdr_pointer = fopen(output_file_name, "w+b");
 		if (g_hdr_pointer == NULL) {
-			my_printf(TERR,
-				  "\n\nCannot open %s file.\n\n",
+			my_printf(TERR, "\n\nCannot open %s file.\n\n",
 				  output_file_name);
 			return FALSE;
 		}
@@ -2102,23 +1946,15 @@ int main_hdr(void)
 			return FALSE;
 
 		tmp_long_val = HDR_PTR_SIGNATURE;
-		result = (int)(fwrite(&tmp_long_val,
-				      4,
-				      1,
-				      g_hdr_pointer));
-		result |= (int)(fwrite(&ptr_fw_addr,
-				       4,
-				       1,
-				       g_hdr_pointer));
+		result = (int)(fwrite(&tmp_long_val, 4, 1, g_hdr_pointer));
+		result |= (int)(fwrite(&ptr_fw_addr, 4, 1, g_hdr_pointer));
 
 		if (result) {
-			my_printf(TINF,
-				  "\nBootLoader Header file: %s\n",
+			my_printf(TINF, "\nBootLoader Header file: %s\n",
 				  output_file_name);
 			my_printf(TINF,
 				  "     Signature: 0x%08X,   Pointer: 0x%08X\n",
-				  HDR_PTR_SIGNATURE,
-				  ptr_fw_addr);
+				  HDR_PTR_SIGNATURE, ptr_fw_addr);
 		} else {
 			my_printf(TERR,
 				  "\n\nCouldn't write signature (%x) and ",
@@ -2128,7 +1964,6 @@ int main_hdr(void)
 				  output_file_name);
 			return FALSE;
 		}
-
 	}
 
 	/* Close if needed... */
@@ -2166,15 +2001,15 @@ int main_api(void)
 
 	/* If API input file was not declared, then print error message. */
 	if (strlen(input_file_name) == 0) {
-		my_printf(TERR,
+		my_printf(
+			TERR,
 			"\n\nNeed to define API input file, using -i flag\n\n");
 		return FALSE;
-
 	}
 
 	if (strlen(output_file_name) == 0) {
 		if (!splice_into_path(tmp_file_name, input_file_name,
-			sizeof(tmp_file_name), "api_"))
+				      sizeof(tmp_file_name), "api_"))
 			return FALSE;
 	} else
 		strncpy(tmp_file_name, output_file_name,
@@ -2204,27 +2039,20 @@ int main_api(void)
 	api_file_size_bytes = get_file_length(api_file_pointer);
 	if (api_file_size_bytes < 0)
 		return FALSE;
-	my_printf(TINF,
-		  "\nAPI file: %s, size: %d bytes (0x%x)\n",
-		  tmp_file_name,
-		  api_file_size_bytes,
-		  api_file_size_bytes);
+	my_printf(TINF, "\nAPI file: %s, size: %d bytes (0x%x)\n",
+		  tmp_file_name, api_file_size_bytes, api_file_size_bytes);
 
 	crc_checksum = calc_api_csum_bin();
 
 	if (fseek(api_file_pointer, api_file_size_bytes, SEEK_SET) < 0)
 		return FALSE;
 
-	result = (int)(fwrite(&crc_checksum,
-			      4,
-			      1,
-			      api_file_pointer));
+	result = (int)(fwrite(&crc_checksum, 4, 1, api_file_pointer));
 
 	if (result)
 		my_printf(TINF,
 			  "\nIn API BIN file - Offset 0x%08X - value 0x%08X",
-			  api_file_size_bytes,
-			  crc_checksum);
+			  api_file_size_bytes, crc_checksum);
 	else {
 		my_printf(TERR,
 			  "\n\nCouldn't write %x to API BIN file at %08x\n\n",
@@ -2241,7 +2069,6 @@ int main_api(void)
 	return TRUE;
 }
 
-
 /*
  *******************************************************************
  * Function: calc_api_csum_bin
@@ -2250,10 +2077,9 @@ int main_api(void)
  * Return: Return the CRC \ checksum, or "0" in case of fail.
  * Description:	 TBD
  *******************************************************************
-*/
+ */
 unsigned int calc_api_csum_bin(void)
 {
-
 	unsigned int i;
 	unsigned int calc_read_bytes;
 	int calc_num_of_bytes_to_read;
@@ -2269,10 +2095,8 @@ unsigned int calc_api_csum_bin(void)
 		my_printf(TDBG,
 			  "\nAPI CRC \\ Checksum First Byte Address: 0x%08x",
 			  calc_curr_position);
-		my_printf(TDBG,
-			  "\nAPI CRC \\ Checksum Size:  %d (0x%X)",
-			  calc_num_of_bytes_to_read,
-			  calc_num_of_bytes_to_read);
+		my_printf(TDBG, "\nAPI CRC \\ Checksum Size:  %d (0x%X)",
+			  calc_num_of_bytes_to_read, calc_num_of_bytes_to_read);
 	}
 
 	init_calculation(&calc_fw_checksum_crc);
@@ -2283,13 +2107,10 @@ unsigned int calc_api_csum_bin(void)
 		else
 			calc_read_bytes = calc_num_of_bytes_to_read;
 
-		if (fseek(api_file_pointer,
-			calc_curr_position, SEEK_SET) < 0)
+		if (fseek(api_file_pointer, calc_curr_position, SEEK_SET) < 0)
 			return 0;
-		if (fread(g_fw_array,
-			  calc_read_bytes,
-			  1,
-			  api_file_pointer) != 1)
+		if (fread(g_fw_array, calc_read_bytes, 1, api_file_pointer) !=
+		    1)
 			return 0;
 
 		for (i = 0; i < calc_read_bytes; i++) {
@@ -2298,10 +2119,9 @@ unsigned int calc_api_csum_bin(void)
 			 * but it made ecst run sloooowwwwwly....
 			 */
 			if (g_verbose == SUPER_VERBOSE) {
-				if (i%line_print_size == 0)
-					my_printf(TDBG,
-					"\n[%.4x]: ",
-					calc_curr_position + i);
+				if (i % line_print_size == 0)
+					my_printf(TDBG, "\n[%.4x]: ",
+						  calc_curr_position + i);
 
 				my_printf(TDBG, "%.2x ", g_fw_array[i]);
 			}
@@ -2311,8 +2131,7 @@ unsigned int calc_api_csum_bin(void)
 
 			if (g_verbose == SUPER_VERBOSE) {
 				if ((i + 1) % line_print_size == 0)
-					my_printf(TDBG,
-						  "FW Checksum= %.8x",
+					my_printf(TDBG, "FW Checksum= %.8x",
 						  calc_fw_checksum_crc);
 			}
 		}
@@ -2323,14 +2142,13 @@ unsigned int calc_api_csum_bin(void)
 	finalize_calculation(&calc_fw_checksum_crc);
 
 	return calc_fw_checksum_crc;
-
 }
 
 /*
  **************************************************************************
  *			CRC Handler
  **************************************************************************
-*/
+ */
 
 /*
  *******************************************************************
@@ -2343,7 +2161,7 @@ unsigned int calc_api_csum_bin(void)
  *******************************************************************
  */
 
-#define P_32        0xEDB88320L
+#define P_32 0xEDB88320L
 
 /*
  *******************************************************************
@@ -2394,7 +2212,7 @@ static void init_crc32_tab(void);
 unsigned int initialize_crc_32(void)
 {
 	return 0xffffffffL;
-}  /* initialize_crc_32 */
+} /* initialize_crc_32 */
 
 /*
  *******************************************************************
@@ -2410,7 +2228,6 @@ unsigned int initialize_crc_32(void)
 
 unsigned int update_crc_32(unsigned int crc, char c)
 {
-
 	unsigned int tmp, long_c;
 
 	long_c = 0x000000ffL & (unsigned int)c;
@@ -2423,7 +2240,7 @@ unsigned int update_crc_32(unsigned int crc, char c)
 
 	return crc;
 
-}  /* update_crc_32 */
+} /* update_crc_32 */
 
 /*
  *******************************************************************
@@ -2437,16 +2254,13 @@ unsigned int update_crc_32(unsigned int crc, char c)
  */
 static void init_crc32_tab(void)
 {
-
 	int i, j;
 	unsigned int crc;
 
 	for (i = 0; i < 256; i++) {
-
 		crc = (unsigned int)i;
 
 		for (j = 0; j < 8; j++) {
-
 			if (crc & 0x00000001L)
 				crc = (crc >> 1) ^ P_32;
 			else
@@ -2458,7 +2272,7 @@ static void init_crc32_tab(void)
 
 	crc_tab32_init = TRUE;
 
-}  /* init_crc32_tab */
+} /* init_crc32_tab */
 
 /*
  *******************************************************************
@@ -2473,13 +2287,13 @@ static void init_crc32_tab(void)
 
 unsigned int finalize_crc_32(unsigned int crc)
 {
-
 	int i;
 	unsigned int result = 0;
 
 	for (i = 0; i < NUM_OF_BYTES; i++)
-		SET_VAR_BIT(result, NUM_OF_BYTES - (i+1), READ_VAR_BIT(crc, i));
+		SET_VAR_BIT(result, NUM_OF_BYTES - (i + 1),
+			    READ_VAR_BIT(crc, i));
 
 	return result;
 
-}  /* finalize_crc_32 */
+} /* finalize_crc_32 */
diff --git a/util/ecst.h b/util/ecst.h
index 628eaebe9b..7d3dbbe153 100644
--- a/util/ecst.h
+++ b/util/ecst.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,149 +16,146 @@
 #include <stdio.h>
 #include <curses.h>
 
-
 /*---------------------------------------------------------------------------
   Defines
   --------------------------------------------------------------------------*/
 
 /* For the beauty */
-#define TRUE                            1
-#define FALSE                           0
+#define TRUE 1
+#define FALSE 0
 
 /* CHANGEME when the version is updated */
-#define T_VER                           1
-#define T_REV_MAJOR                     0
-#define T_REV_MINOR                     3
+#define T_VER 1
+#define T_REV_MAJOR 0
+#define T_REV_MINOR 3
 
 /* Header starts by default at 0x20000 */
-#define FIRMWARE_OFFSET_FROM_HEADER     0x40
+#define FIRMWARE_OFFSET_FROM_HEADER 0x40
 
-#define ARM_FW_ENTRY_POINT_OFFSET       0x04
+#define ARM_FW_ENTRY_POINT_OFFSET 0x04
 
 /* Some useful offsets inside the header */
-#define	HDR_ANCHOR_OFFSET                    0
-#define	HDR_EXTENDED_ANCHOR_OFFSET           4
-#define	HDR_SPI_MAX_CLK_OFFSET               6
-#define	HDR_SPI_READ_MODE_OFFSET             7
-#define	HDR_ERR_DETECTION_CONF_OFFSET        8
-#define	HDR_FW_LOAD_START_ADDR_OFFSET        9
-#define	HDR_FW_ENTRY_POINT_OFFSET            13
-#define	HDR_FW_ERR_DETECT_START_ADDR_OFFSET  17
-#define	HDR_FW_ERR_DETECT_END_ADDR_OFFSET    21
-#define	HDR_FW_LENGTH_OFFSET                 25
-#define	HDR_FLASH_SIZE_OFFSET                29
-#define HDR_RESERVED                         30
-#define	HDR_FW_HEADER_SIG_OFFSET             56
-#define HDR_FW_IMAGE_SIG_OFFSET              60
-
-
-#define FIRMW_CKSM_OFFSET               0x3C
+#define HDR_ANCHOR_OFFSET 0
+#define HDR_EXTENDED_ANCHOR_OFFSET 4
+#define HDR_SPI_MAX_CLK_OFFSET 6
+#define HDR_SPI_READ_MODE_OFFSET 7
+#define HDR_ERR_DETECTION_CONF_OFFSET 8
+#define HDR_FW_LOAD_START_ADDR_OFFSET 9
+#define HDR_FW_ENTRY_POINT_OFFSET 13
+#define HDR_FW_ERR_DETECT_START_ADDR_OFFSET 17
+#define HDR_FW_ERR_DETECT_END_ADDR_OFFSET 21
+#define HDR_FW_LENGTH_OFFSET 25
+#define HDR_FLASH_SIZE_OFFSET 29
+#define HDR_RESERVED 30
+#define HDR_FW_HEADER_SIG_OFFSET 56
+#define HDR_FW_IMAGE_SIG_OFFSET 60
+
+#define FIRMW_CKSM_OFFSET 0x3C
 
 /* Header field known values */
-#define FW_HDR_ANCHOR                   0x2A3B4D5E
-#define FW_HDR_EXT_ANCHOR_ENABLE        0xAB1E
-#define FW_HDR_EXT_ANCHOR_DISABLE       0x54E1
-#define FW_CRC_DISABLE                  0x00
-#define FW_CRC_ENABLE                   0x02
-#define HEADER_CRC_FIELDS_SIZE          8
+#define FW_HDR_ANCHOR 0x2A3B4D5E
+#define FW_HDR_EXT_ANCHOR_ENABLE 0xAB1E
+#define FW_HDR_EXT_ANCHOR_DISABLE 0x54E1
+#define FW_CRC_DISABLE 0x00
+#define FW_CRC_ENABLE 0x02
+#define HEADER_CRC_FIELDS_SIZE 8
 
-#define HDR_PTR_SIGNATURE               0x55AA650E
+#define HDR_PTR_SIGNATURE 0x55AA650E
 
-#define CKSMCRC_INV_BIT_OFFSET          0x1
+#define CKSMCRC_INV_BIT_OFFSET 0x1
 
 /* Some common Sizes */
-#define STR_SIZE                        200
-#define	ARG_SIZE                        100
-#define NAME_SIZE                       160
-#define BUFF_SIZE                       0x400
-#define HEADER_SIZE                     64
-#define TMP_STR_SIZE                    21
-#define PAD_VALUE                       0x00
-
+#define STR_SIZE 200
+#define ARG_SIZE 100
+#define NAME_SIZE 160
+#define BUFF_SIZE 0x400
+#define HEADER_SIZE 64
+#define TMP_STR_SIZE 21
+#define PAD_VALUE 0x00
 
-#define MAX_ARGS                        100
+#define MAX_ARGS 100
 
 /* Text Colors */
-#define TDBG                            0x02  /* Dark Green     */
-#define TPAS                            0x0A  /* light green    */
-#define TINF                            0x0B  /* light turquise */
-#define TERR                            0x0C  /* light red      */
-#define TUSG                            0x0E  /* light yellow   */
+#define TDBG 0x02 /* Dark Green     */
+#define TPAS 0x0A /* light green    */
+#define TINF 0x0B /* light turquise */
+#define TERR 0x0C /* light red      */
+#define TUSG 0x0E /* light yellow   */
 
 /* Indicates bin Command line parameters */
-#define BIN_FW_HDR_CRC_DISABLE          0x0001
-#define BIN_FW_CRC_DISABLE              0x0002
-#define BIN_FW_START                    0x0004
-#define BIN_FW_SIZE                     0x0008
-#define BIN_CK_FIRMWARE                 0x0010
-#define BIN_FW_CKS_START                0x0020
-#define BIN_FW_CKS_SIZE                 0x0040
-#define BIN_FW_CHANGE_SIG               0x0080
-#define BIN_FW_SPI_MAX_CLK              0x0100
-#define BIN_FW_LOAD_START_ADDR          0x0200
-#define BIN_FW_ENTRY_POINT              0x0400
-#define BIN_FW_LENGTH                   0x0800
-#define BIN_FW_HDR_OFFSET               0x1000
-#define	BIN_FW_USER_ARM_RESET           0x2000
-#define BIN_UNLIM_BURST_ENABLE          0x4000
-
-#define ECRP_OFFSET                     0x01
-#define ECRP_INPUT_FILE                 0x02
-#define ECRP_OUTPUT_FILE                0x04
-
-#define SPI_MAX_CLOCK_20_MHZ_VAL        20
-#define SPI_MAX_CLOCK_25_MHZ_VAL        25
-#define SPI_MAX_CLOCK_33_MHZ_VAL        33
-#define SPI_MAX_CLOCK_40_MHZ_VAL        40
-#define SPI_MAX_CLOCK_50_MHZ_VAL        50
-
-#define SPI_MAX_CLOCK_20_MHZ            0x00
-#define SPI_MAX_CLOCK_25_MHZ            0x01
-#define SPI_MAX_CLOCK_33_MHZ            0x02
-#define SPI_MAX_CLOCK_40_MHZ            0x03
-#define SPI_MAX_CLOCK_50_MHZ            0x04
-#define SPI_MAX_CLOCK_MASK              0xF8
-
-#define SPI_CLOCK_RATIO_1_VAL           1
-#define SPI_CLOCK_RATIO_2_VAL           2
-
-#define SPI_CLOCK_RATIO_1               0x07
-#define SPI_CLOCK_RATIO_2               0x08
-
-#define SPI_NORMAL_MODE_VAL             "normal"
-#define SPI_SINGLE_MODE_VAL             "fast"
-#define SPI_DUAL_MODE_VAL               "dual"
-#define SPI_QUAD_MODE_VAL               "quad"
-
-#define SPI_NORMAL_MODE                 0x00
-#define SPI_SINGLE_MODE                 0x01
-#define SPI_DUAL_MODE                   0x03
-#define SPI_QUAD_MODE                   0x04
-
-#define SPI_UNLIMITED_BURST_ENABLE      0x08
-
-#define FLASH_SIZE_1_MBYTES_VAL         1
-#define FLASH_SIZE_2_MBYTES_VAL         2
-#define FLASH_SIZE_4_MBYTES_VAL         4
-#define FLASH_SIZE_8_MBYTES_VAL         8
-#define FLASH_SIZE_16_MBYTES_VAL        16
-
-#define FLASH_SIZE_1_MBYTES             0x01
-#define FLASH_SIZE_2_MBYTES             0x03
-#define FLASH_SIZE_4_MBYTES             0x07
-#define FLASH_SIZE_8_MBYTES             0x0F
-#define FLASH_SIZE_16_MBYTES            0x1F
+#define BIN_FW_HDR_CRC_DISABLE 0x0001
+#define BIN_FW_CRC_DISABLE 0x0002
+#define BIN_FW_START 0x0004
+#define BIN_FW_SIZE 0x0008
+#define BIN_CK_FIRMWARE 0x0010
+#define BIN_FW_CKS_START 0x0020
+#define BIN_FW_CKS_SIZE 0x0040
+#define BIN_FW_CHANGE_SIG 0x0080
+#define BIN_FW_SPI_MAX_CLK 0x0100
+#define BIN_FW_LOAD_START_ADDR 0x0200
+#define BIN_FW_ENTRY_POINT 0x0400
+#define BIN_FW_LENGTH 0x0800
+#define BIN_FW_HDR_OFFSET 0x1000
+#define BIN_FW_USER_ARM_RESET 0x2000
+#define BIN_UNLIM_BURST_ENABLE 0x4000
+
+#define ECRP_OFFSET 0x01
+#define ECRP_INPUT_FILE 0x02
+#define ECRP_OUTPUT_FILE 0x04
+
+#define SPI_MAX_CLOCK_20_MHZ_VAL 20
+#define SPI_MAX_CLOCK_25_MHZ_VAL 25
+#define SPI_MAX_CLOCK_33_MHZ_VAL 33
+#define SPI_MAX_CLOCK_40_MHZ_VAL 40
+#define SPI_MAX_CLOCK_50_MHZ_VAL 50
+
+#define SPI_MAX_CLOCK_20_MHZ 0x00
+#define SPI_MAX_CLOCK_25_MHZ 0x01
+#define SPI_MAX_CLOCK_33_MHZ 0x02
+#define SPI_MAX_CLOCK_40_MHZ 0x03
+#define SPI_MAX_CLOCK_50_MHZ 0x04
+#define SPI_MAX_CLOCK_MASK 0xF8
+
+#define SPI_CLOCK_RATIO_1_VAL 1
+#define SPI_CLOCK_RATIO_2_VAL 2
+
+#define SPI_CLOCK_RATIO_1 0x07
+#define SPI_CLOCK_RATIO_2 0x08
+
+#define SPI_NORMAL_MODE_VAL "normal"
+#define SPI_SINGLE_MODE_VAL "fast"
+#define SPI_DUAL_MODE_VAL "dual"
+#define SPI_QUAD_MODE_VAL "quad"
+
+#define SPI_NORMAL_MODE 0x00
+#define SPI_SINGLE_MODE 0x01
+#define SPI_DUAL_MODE 0x03
+#define SPI_QUAD_MODE 0x04
+
+#define SPI_UNLIMITED_BURST_ENABLE 0x08
+
+#define FLASH_SIZE_1_MBYTES_VAL 1
+#define FLASH_SIZE_2_MBYTES_VAL 2
+#define FLASH_SIZE_4_MBYTES_VAL 4
+#define FLASH_SIZE_8_MBYTES_VAL 8
+#define FLASH_SIZE_16_MBYTES_VAL 16
+
+#define FLASH_SIZE_1_MBYTES 0x01
+#define FLASH_SIZE_2_MBYTES 0x03
+#define FLASH_SIZE_4_MBYTES 0x07
+#define FLASH_SIZE_8_MBYTES 0x0F
+#define FLASH_SIZE_16_MBYTES 0x1F
 
 /* Header fields default values. */
-#define SPI_MAX_CLOCK_DEFAULT           SPI_MAX_CLOCK_20_MHZ_VAL
-#define SPI_READ_MODE_DEFAULT           SPI_NORMAL_MODE
-#define FLASH_SIZE_DEFAULT              FLASH_SIZE_16_MBYTES_VAL
-#define	FW_CRC_START_ADDR               0x00000000
+#define SPI_MAX_CLOCK_DEFAULT SPI_MAX_CLOCK_20_MHZ_VAL
+#define SPI_READ_MODE_DEFAULT SPI_NORMAL_MODE
+#define FLASH_SIZE_DEFAULT FLASH_SIZE_16_MBYTES_VAL
+#define FW_CRC_START_ADDR 0x00000000
 
-#define ADDR_16_BYTES_ALIGNED_MASK      0x0000000F
-#define ADDR_4_BYTES_ALIGNED_MASK       0x00000003
+#define ADDR_16_BYTES_ALIGNED_MASK 0x0000000F
+#define ADDR_4_BYTES_ALIGNED_MASK 0x00000003
 
-#define MAX_FLASH_SIZE                  0x03ffffff
+#define MAX_FLASH_SIZE 0x03ffffff
 
 /* Chips: convert from name to index. */
 enum npcx_chip_ram_variant {
@@ -172,25 +169,25 @@ enum npcx_chip_ram_variant {
 	NPCX_CHIP_RAM_VAR_NONE
 };
 
-#define DEFAULT_CHIP                    NPCX5M5G
+#define DEFAULT_CHIP NPCX5M5G
 
 /* NPCX5 */
-#define NPCX5M5G_RAM_ADDR               0x100A8000
-#define NPCX5M5G_RAM_SIZE               0x20000
-#define NPCX5M6G_RAM_ADDR               0x10088000
-#define NPCX5M6G_RAM_SIZE               0x40000
+#define NPCX5M5G_RAM_ADDR 0x100A8000
+#define NPCX5M5G_RAM_SIZE 0x20000
+#define NPCX5M6G_RAM_ADDR 0x10088000
+#define NPCX5M6G_RAM_SIZE 0x40000
 /* NPCX7 */
-#define NPCX7M5X_RAM_ADDR               0x100A8000
-#define NPCX7M5X_RAM_SIZE               0x20000
-#define NPCX7M6X_RAM_ADDR               0x10090000
-#define NPCX7M6X_RAM_SIZE               0x40000
-#define NPCX7M7X_RAM_ADDR               0x10070000
-#define NPCX7M7X_RAM_SIZE               0x60000
+#define NPCX7M5X_RAM_ADDR 0x100A8000
+#define NPCX7M5X_RAM_SIZE 0x20000
+#define NPCX7M6X_RAM_ADDR 0x10090000
+#define NPCX7M6X_RAM_SIZE 0x40000
+#define NPCX7M7X_RAM_ADDR 0x10070000
+#define NPCX7M7X_RAM_SIZE 0x60000
 /* NPCX9 */
-#define NPCX9M3X_RAM_ADDR               0x10080000
-#define NPCX9M3X_RAM_SIZE               0x50000
-#define NPCX9M6X_RAM_ADDR               0x10090000
-#define NPCX9M6X_RAM_SIZE               0x40000
+#define NPCX9M3X_RAM_ADDR 0x10080000
+#define NPCX9M3X_RAM_SIZE 0x50000
+#define NPCX9M6X_RAM_ADDR 0x10090000
+#define NPCX9M6X_RAM_SIZE 0x40000
 
 /*---------------------------------------------------------------------------
   Typedefs
@@ -198,47 +195,39 @@ enum npcx_chip_ram_variant {
 
 /* Parameters for Binary manipulation */
 struct tbinparams {
-	unsigned int	anchor;
-	unsigned short	ext_anchor;
-	unsigned char	spi_max_clk;
-	unsigned char	spi_clk_ratio;
-	unsigned char	spi_read_mode;
-	unsigned char	err_detec_cnf;
-	unsigned int	fw_load_addr;
-	unsigned int	fw_ep;
-	unsigned int	fw_err_detec_s_addr;
-	unsigned int	fw_err_detec_e_addr;
-	unsigned int	fw_len;
-	unsigned int	flash_size;
-	unsigned int	hdr_crc;
-	unsigned int	fw_crc;
-	unsigned int	fw_hdr_offset;
-	unsigned int	bin_params;
+	unsigned int anchor;
+	unsigned short ext_anchor;
+	unsigned char spi_max_clk;
+	unsigned char spi_clk_ratio;
+	unsigned char spi_read_mode;
+	unsigned char err_detec_cnf;
+	unsigned int fw_load_addr;
+	unsigned int fw_ep;
+	unsigned int fw_err_detec_s_addr;
+	unsigned int fw_err_detec_e_addr;
+	unsigned int fw_len;
+	unsigned int flash_size;
+	unsigned int hdr_crc;
+	unsigned int fw_crc;
+	unsigned int fw_hdr_offset;
+	unsigned int bin_params;
 } bin_params_struct;
 
-enum verbose_level {
-	NO_VERBOSE = 0,
-	REGULAR_VERBOSE,
-	SUPER_VERBOSE
-};
+enum verbose_level { NO_VERBOSE = 0, REGULAR_VERBOSE, SUPER_VERBOSE };
 
-enum calc_type {
-	CALC_TYPE_NONE	= 0,
-	CALC_TYPE_CHECKSUM ,
-	CALC_TYPE_CRC
-};
+enum calc_type { CALC_TYPE_NONE = 0, CALC_TYPE_CHECKSUM, CALC_TYPE_CRC };
 
 struct chip_info {
-	unsigned int	ram_addr;
-	unsigned int   ram_size;
+	unsigned int ram_addr;
+	unsigned int ram_size;
 } chip_info_struct;
 
 /*------------------------------------------------------------------------*/
 /* CRC Variable bit operation macros                                      */
 /*------------------------------------------------------------------------*/
-#define NUM_OF_BYTES					32
-#define READ_VAR_BIT(var, nb)			(((var) >> (nb)) & 0x1)
-#define SET_VAR_BIT(var, nb, val)		((var) |= ((val)<<(nb)))
+#define NUM_OF_BYTES 32
+#define READ_VAR_BIT(var, nb) (((var) >> (nb)) & 0x1)
+#define SET_VAR_BIT(var, nb, val) ((var) |= ((val) << (nb)))
 
 /*---------------------------------------------------------------------------
   Functions Declaration
@@ -254,35 +243,27 @@ void init_calculation(unsigned int *check_sum_crc);
 void finalize_calculation(unsigned int *check_sum_crc);
 void update_calculation_information(unsigned char crc_con_dat);
 
-
 /* Checksum calculation etc. (BIN Specific) */
 int calc_header_crc_bin(unsigned int *pointer_header_checksum);
-int calc_firmware_csum_bin(unsigned int *p_cksum,
-						   unsigned int fw_offset,
-						   unsigned int fw_length);
+int calc_firmware_csum_bin(unsigned int *p_cksum, unsigned int fw_offset,
+			   unsigned int fw_length);
 
 /* Checksum calculation etc. (ERP Specific) */
 int calc_erp_csum_bin(unsigned short *region_pointer_header_checksum,
-					  unsigned int region_pointer_ofs);
+		      unsigned int region_pointer_ofs);
 
 /* No words - General */
 void exit_with_usage(void);
-int copy_file_to_file(char *dst_file_name,
-					  char *src_file_name,
-					  int offset,
-					  int origin);
-int write_to_file(unsigned int write_value,
-				  unsigned int offset,
-				  unsigned char num_of_bytes,
-				  char *print_string);
-int read_from_file(unsigned int offset,
-				   unsigned char size_to_read,
-				   unsigned int *read_value,
-				   char *print_string);
+int copy_file_to_file(char *dst_file_name, char *src_file_name, int offset,
+		      int origin);
+int write_to_file(unsigned int write_value, unsigned int offset,
+		  unsigned char num_of_bytes, char *print_string);
+int read_from_file(unsigned int offset, unsigned char size_to_read,
+		   unsigned int *read_value, char *print_string);
 
 /* Nice Particular Printf - General */
-__attribute__((__format__(__printf__, 2, 3)))
-void my_printf(int error_level, char *fmt, ...);
+__attribute__((__format__(__printf__, 2, 3))) void my_printf(int error_level,
+							     char *fmt, ...);
 
 int str_cmp_no_case(const char *s1, const char *s2);
 int get_file_length(FILE *stream);
diff --git a/util/ectool.c b/util/ectool.c
index 028828ebd5..b05e75d14e 100644
--- a/util/ectool.c
+++ b/util/ectool.c
@@ -1,8 +1,9 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include <assert.h>
 #include <ctype.h>
 #include <errno.h>
 #include <getopt.h>
@@ -42,8 +43,8 @@
  */
 #define HELLO_RESP(in_data) ((in_data) + 0x01020304)
 
-#define USB_VID_GOOGLE	0x18d1
-#define USB_PID_HAMMER	0x5022
+#define USB_VID_GOOGLE 0x18d1
+#define USB_PID_HAMMER 0x5022
 
 /* Command line options */
 enum {
@@ -55,17 +56,15 @@ enum {
 	OPT_DEVICE,
 };
 
-static struct option long_opts[] = {
-	{"dev", 1, 0, OPT_DEV},
-	{"interface", 1, 0, OPT_INTERFACE},
-	{"name", 1, 0, OPT_NAME},
-	{"ascii", 0, 0, OPT_ASCII},
-	{"i2c_bus", 1, 0, OPT_I2C_BUS},
-	{"device", 1, 0, OPT_DEVICE},
-	{NULL, 0, 0, 0}
-};
+static struct option long_opts[] = { { "dev", 1, 0, OPT_DEV },
+				     { "interface", 1, 0, OPT_INTERFACE },
+				     { "name", 1, 0, OPT_NAME },
+				     { "ascii", 0, 0, OPT_ASCII },
+				     { "i2c_bus", 1, 0, OPT_I2C_BUS },
+				     { "device", 1, 0, OPT_DEVICE },
+				     { NULL, 0, 0, 0 } };
 
-#define GEC_LOCK_TIMEOUT_SECS	30  /* 30 secs */
+#define GEC_LOCK_TIMEOUT_SECS 30 /* 30 secs */
 
 const char help_str[] =
 	"Commands:\n"
@@ -216,6 +215,8 @@ const char help_str[] =
 	"      Set the color of an LED or query brightness range\n"
 	"  lightbar [CMDS]\n"
 	"      Various lightbar control commands\n"
+	"  locatechip <type> <index>\n"
+	"      Get the addresses and ports of i2c connected and embedded chips\n"
 	"  mkbpget <buttons|switches>\n"
 	"      Get MKBP buttons/switches supported mask and current state\n"
 	"  mkbpwakemask <get|set> <event|hostevent> [mask]\n"
@@ -275,7 +276,7 @@ const char help_str[] =
 	"  readtest <patternoffset> <size>\n"
 	"      Reads a pattern from the EC via LPC\n"
 	"  reboot_ec <RO|RW|cold|hibernate|hibernate-clear-ap-off|disable-jump|cold-ap-off>"
-			" [at-shutdown|switch-slot]\n"
+	" [at-shutdown|switch-slot]\n"
 	"      Reboot EC to RO or RW\n"
 	"  reboot_ap_on_g3 [<delay>]\n"
 	"      Requests that the EC will automatically reboot the AP after a\n"
@@ -344,17 +345,17 @@ const char help_str[] =
 	"  usbmux <mux>\n"
 	"      Set USB mux switch state\n"
 	"  usbpd <port> <auto | "
-			"[toggle|toggle-off|sink|source] [none|usb|dp|dock] "
-			"[dr_swap|pr_swap|vconn_swap]>\n"
+	"[toggle|toggle-off|sink|source] [none|usb|dp|dock] "
+	"[dr_swap|pr_swap|vconn_swap]>\n"
 	"      Control USB PD/type-C [deprecated]\n"
 	"  usbpddps [enable | disable]\n"
 	"      Enable or disable dynamic pdo selection\n"
 	"  usbpdmuxinfo [tsv]\n"
 	"      Get USB-C SS mux info.\n"
 	"          tsv: Output as tab separated values. Columns are defined "
-			"as:\n"
+	"as:\n"
 	"               Port, USB enabled, DP enabled, Polarity, HPD IRQ, "
-			"HPD LVL\n"
+	"HPD LVL\n"
 	"  usbpdpower [port]\n"
 	"      Get USB PD power information\n"
 	"  version\n"
@@ -366,17 +367,18 @@ const char help_str[] =
 	"";
 
 /* Note: depends on enum ec_image */
-static const char * const image_names[] = {"unknown", "RO", "RW"};
+static const char *const image_names[] = { "unknown", "RO", "RW" };
 
 /* Note: depends on enum ec_led_colors */
-static const char * const led_color_names[] = {
-	"red", "green", "blue", "yellow", "white", "amber"};
+static const char *const led_color_names[] = { "red",	 "green", "blue",
+					       "yellow", "white", "amber" };
 BUILD_ASSERT(ARRAY_SIZE(led_color_names) == EC_LED_COLOR_COUNT);
 
 /* Note: depends on enum ec_led_id */
-static const char * const led_names[] = {
-	"battery", "power", "adapter", "left", "right", "recovery_hwreinit",
-	"sysrq debug" };
+static const char *const led_names[] = { "battery",    "power",
+					 "adapter",    "left",
+					 "right",      "recovery_hwreinit",
+					 "sysrq debug" };
 BUILD_ASSERT(ARRAY_SIZE(led_names) == EC_LED_ID_COUNT);
 
 /* ASCII mode for printing, default off */
@@ -395,7 +397,7 @@ int parse_bool(const char *s, int *dest)
 		*dest = 0;
 		return 1;
 	} else if (!strcasecmp(s, "on") || !strncasecmp(s, "ena", 3) ||
-	    tolower(*s) == 't' || tolower(*s) == 'y') {
+		   tolower(*s) == 't' || tolower(*s) == 'y') {
 		*dest = 1;
 		return 1;
 	} else {
@@ -403,6 +405,48 @@ int parse_bool(const char *s, int *dest)
 	}
 }
 
+/**
+ * @brief Find the enum value associated the string of enum text or value.
+ *
+ * @param str The input string to parse an enum from.
+ * @param enum_text_map The array that maps enum value (index) to text.
+ * @param enum_text_map_length The length of the enum_text_map array.
+ * @param enum_value Output parsed enum value.
+ * @return int 0 on success, -1 if result cannot be found
+ */
+static int find_enum_from_text(const char *str,
+			       const char *const enum_text_map[],
+			       long enum_text_map_length, long *enum_value)
+{
+	char *e;
+	long value;
+
+	assert(str);
+	assert(enum_value);
+	assert(enum_text_map);
+	assert(enum_text_map_length >= 0);
+
+	if (*str == '\0')
+		return -1;
+
+	value = strtol(str, &e, 0);
+	if (!e || !*e) {
+		*enum_value = value;
+		return 0;
+	}
+
+	for (value = 0; value < enum_text_map_length; value++) {
+		if (!enum_text_map[value])
+			continue;
+		if (strcasecmp(str, enum_text_map[value]) == 0) {
+			*enum_value = value;
+			return 0;
+		}
+	}
+
+	return -1;
+}
+
 void print_help(const char *prog, int print_cmds)
 {
 	printf("Usage: %s [--dev=n] "
@@ -546,11 +590,11 @@ int cmd_add_entropy(int argc, char *argv[])
 		}
 
 		/* Abort if EC returns an error other than EC_RES_BUSY. */
-		if (rv <= -EECRESULT && rv != -EECRESULT-EC_RES_BUSY)
+		if (rv <= -EECRESULT && rv != -EECRESULT - EC_RES_BUSY)
 			goto out;
 	}
 
-	rv = -EECRESULT-EC_RES_TIMEOUT;
+	rv = -EECRESULT - EC_RES_TIMEOUT;
 out:
 	fprintf(stderr, "Failed to add entropy: %d\n", rv);
 	return rv;
@@ -595,8 +639,8 @@ int cmd_hibdelay(int argc, char *argv[])
 		}
 	}
 
-	rv = ec_command(EC_CMD_HIBERNATION_DELAY, 0, &p, sizeof(p),
-			&r, sizeof(r));
+	rv = ec_command(EC_CMD_HIBERNATION_DELAY, 0, &p, sizeof(p), &r,
+			sizeof(r));
 	if (rv < 0) {
 		fprintf(stderr, "err: rv=%d\n", rv);
 		return -1;
@@ -611,18 +655,18 @@ int cmd_hibdelay(int argc, char *argv[])
 static void cmd_hostevent_help(char *cmd)
 {
 	fprintf(stderr,
-	"  Usage: %s get <type>\n"
-	"  Usage: %s set <type> <value>\n"
-	"    <type> is one of:\n"
-	"      1: EC_HOST_EVENT_B\n"
-	"      2: EC_HOST_EVENT_SCI_MASK\n"
-	"      3: EC_HOST_EVENT_SMI_MASK\n"
-	"      4: EC_HOST_EVENT_ALWAYS_REPORT_MASK\n"
-	"      5: EC_HOST_EVENT_ACTIVE_WAKE_MASK\n"
-	"      6: EC_HOST_EVENT_LAZY_WAKE_MASK_S0IX\n"
-	"      7: EC_HOST_EVENT_LAZY_WAKE_MASK_S3\n"
-	"      8: EC_HOST_EVENT_LAZY_WAKE_MASK_S5\n"
-		, cmd, cmd);
+		"  Usage: %s get <type>\n"
+		"  Usage: %s set <type> <value>\n"
+		"    <type> is one of:\n"
+		"      1: EC_HOST_EVENT_B\n"
+		"      2: EC_HOST_EVENT_SCI_MASK\n"
+		"      3: EC_HOST_EVENT_SMI_MASK\n"
+		"      4: EC_HOST_EVENT_ALWAYS_REPORT_MASK\n"
+		"      5: EC_HOST_EVENT_ACTIVE_WAKE_MASK\n"
+		"      6: EC_HOST_EVENT_LAZY_WAKE_MASK_S0IX\n"
+		"      7: EC_HOST_EVENT_LAZY_WAKE_MASK_S3\n"
+		"      8: EC_HOST_EVENT_LAZY_WAKE_MASK_S5\n",
+		cmd, cmd);
 }
 
 static int cmd_hostevent(int argc, char *argv[])
@@ -693,12 +737,12 @@ static int get_latest_cmd_version(uint8_t cmd, int *version)
 	*version = 0;
 	/* Figure out the latest version of the given command the EC supports */
 	p.cmd = cmd;
-	rv = ec_command(EC_CMD_GET_CMD_VERSIONS, 0, &p, sizeof(p),
-			&r, sizeof(r));
+	rv = ec_command(EC_CMD_GET_CMD_VERSIONS, 0, &p, sizeof(p), &r,
+			sizeof(r));
 	if (rv < 0) {
 		if (rv == -EC_RES_INVALID_PARAM)
 			printf("Command 0x%02x not supported by EC.\n",
-					EC_CMD_GET_CMD_VERSIONS);
+			       EC_CMD_GET_CMD_VERSIONS);
 		return rv;
 	}
 
@@ -721,7 +765,8 @@ int cmd_hostsleepstate(int argc, char *argv[])
 	uint32_t timeout, transitions;
 
 	if (argc < 2) {
-		fprintf(stderr, "Usage: %s "
+		fprintf(stderr,
+			"Usage: %s "
 			"[suspend|wsuspend|resume|freeze|thaw] [timeout]\n",
 			argv[0]);
 		return -1;
@@ -751,8 +796,7 @@ int cmd_hostsleepstate(int argc, char *argv[])
 
 				if ((*afterscan != '\0') ||
 				    (afterscan == argv[2])) {
-					fprintf(stderr,
-						"Invalid value: %s\n",
+					fprintf(stderr, "Invalid value: %s\n",
 						argv[2]);
 
 					return -1;
@@ -789,8 +833,7 @@ int cmd_hostsleepstate(int argc, char *argv[])
 			      EC_HOST_RESUME_SLEEP_TRANSITIONS_MASK;
 
 		printf("%s%d sleep line transitions.\n",
-		       timeout ? "Timeout: " : "",
-		       transitions);
+		       timeout ? "Timeout: " : "", transitions);
 	}
 
 	return 0;
@@ -799,7 +842,7 @@ int cmd_hostsleepstate(int argc, char *argv[])
 int cmd_test(int argc, char *argv[])
 {
 	struct ec_params_test_protocol p = {
-		.buf = { 1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11,
+		.buf = { 1,  2,	 3,  4,	 5,  6,	 7,  8,	 9,  10, 11,
 			 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22,
 			 23, 24, 25, 26, 27, 28, 29, 30, 31, 32 }
 	};
@@ -808,8 +851,7 @@ int cmd_test(int argc, char *argv[])
 	char *e;
 
 	if (argc < 3) {
-		fprintf(stderr, "Usage: %s result length [version]\n",
-			argv[0]);
+		fprintf(stderr, "Usage: %s result length [version]\n", argv[0]);
 		return -1;
 	}
 
@@ -832,8 +874,8 @@ int cmd_test(int argc, char *argv[])
 		}
 	}
 
-	rv = ec_command(EC_CMD_TEST_PROTOCOL, version,
-			&p, sizeof(p), &r, sizeof(r));
+	rv = ec_command(EC_CMD_TEST_PROTOCOL, version, &p, sizeof(p), &r,
+			sizeof(r));
 	printf("rv = %d\n", rv);
 
 	return rv;
@@ -856,15 +898,15 @@ int cmd_s5(int argc, char *argv[])
 		p.value = param;
 	}
 
-	rv = ec_command(EC_CMD_GSV_PAUSE_IN_S5, 0,
-			&p, sizeof(p), &r, sizeof(r));
+	rv = ec_command(EC_CMD_GSV_PAUSE_IN_S5, 0, &p, sizeof(p), &r,
+			sizeof(r));
 	if (rv > 0)
 		printf("%s\n", r.value ? "on" : "off");
 
 	return rv < 0;
 }
 
-static const char * const ec_feature_names[] = {
+static const char *const ec_feature_names[] = {
 	[EC_FEATURE_LIMITED] = "Limited image, load RW for more",
 	[EC_FEATURE_FLASH] = "Flash",
 	[EC_FEATURE_PWM_FAN] = "Direct Fan power management",
@@ -913,6 +955,7 @@ static const char * const ec_feature_names[] = {
 	[EC_FEATURE_TYPEC_MUX_REQUIRE_AP_ACK] =
 		"AP ack for Type-C mux configuration",
 	[EC_FEATURE_S4_RESIDENCY] = "S4 residency",
+	[EC_FEATURE_TYPEC_AP_MUX_SET] = "AP directed mux sets",
 };
 
 int cmd_inventory(int argc, char *argv[])
@@ -933,15 +976,14 @@ int cmd_inventory(int argc, char *argv[])
 				    strlen(ec_feature_names[idx]) == 0)
 					printf("%-4d: Unknown feature\n", idx);
 				else
-					printf("%-4d: %s support\n",
-					       idx, ec_feature_names[idx]);
+					printf("%-4d: %s support\n", idx,
+					       ec_feature_names[idx]);
 			}
 		}
 	}
 	return 0;
 }
 
-
 int cmd_cmdversions(int argc, char *argv[])
 {
 	struct ec_params_get_cmd_versions p;
@@ -961,8 +1003,8 @@ int cmd_cmdversions(int argc, char *argv[])
 	}
 
 	p.cmd = cmd;
-	rv = ec_command(EC_CMD_GET_CMD_VERSIONS, 0, &p, sizeof(p),
-			&r, sizeof(r));
+	rv = ec_command(EC_CMD_GET_CMD_VERSIONS, 0, &p, sizeof(p), &r,
+			sizeof(r));
 	if (rv < 0) {
 		if (rv == -EC_RES_INVALID_PARAM)
 			printf("Command 0x%02x not supported by EC.\n", cmd);
@@ -970,8 +1012,8 @@ int cmd_cmdversions(int argc, char *argv[])
 		return rv;
 	}
 
-	printf("Command 0x%02x supports version mask 0x%08x\n",
-	       cmd, r.version_mask);
+	printf("Command 0x%02x supports version mask 0x%08x\n", cmd,
+	       r.version_mask);
 	return 0;
 }
 
@@ -982,7 +1024,7 @@ int cmd_cmdversions(int argc, char *argv[])
  */
 static const char *reset_cause_to_str(uint16_t cause)
 {
-	static const char * const reset_causes[] = {
+	static const char *const reset_causes[] = {
 		"(reset unknown)",
 		"reset: board custom",
 		"reset: ap hang detected",
@@ -997,7 +1039,7 @@ static const char *reset_cause_to_str(uint16_t cause)
 	};
 	BUILD_ASSERT(ARRAY_SIZE(reset_causes) == CHIPSET_RESET_COUNT);
 
-	static const char * const shutdown_causes[] = {
+	static const char *const shutdown_causes[] = {
 		"shutdown: power failure",
 		"shutdown: during EC initialization",
 		"shutdown: board custom",
@@ -1031,8 +1073,8 @@ int cmd_uptimeinfo(int argc, char *argv[])
 	int i;
 	int flag_count;
 	uint32_t flag;
-	static const char * const reset_flag_descs[] = {
-		#include "reset_flag_desc.inc"
+	static const char *const reset_flag_descs[] = {
+#include "reset_flag_desc.inc"
 	};
 
 	if (argc != 1) {
@@ -1047,9 +1089,8 @@ int cmd_uptimeinfo(int argc, char *argv[])
 		return rv;
 	}
 
-	printf("EC uptime: %d.%03d seconds\n",
-		r.time_since_ec_boot_ms / 1000,
-		r.time_since_ec_boot_ms % 1000);
+	printf("EC uptime: %d.%03d seconds\n", r.time_since_ec_boot_ms / 1000,
+	       r.time_since_ec_boot_ms % 1000);
 
 	printf("AP resets since EC boot: %d\n", r.ap_resets_since_ec_boot);
 
@@ -1059,9 +1100,9 @@ int cmd_uptimeinfo(int argc, char *argv[])
 			continue;
 
 		printf("\t%d.%03d: %s\n",
-			r.recent_ap_reset[i].reset_time_ms / 1000,
-			r.recent_ap_reset[i].reset_time_ms % 1000,
-			reset_cause_to_str(r.recent_ap_reset[i].reset_cause));
+		       r.recent_ap_reset[i].reset_time_ms / 1000,
+		       r.recent_ap_reset[i].reset_time_ms % 1000,
+		       reset_cause_to_str(r.recent_ap_reset[i].reset_cause));
 	}
 
 	printf("EC reset flags at last EC boot: ");
@@ -1112,11 +1153,11 @@ int cmd_version(int argc, char *argv[])
 		goto exit;
 	}
 
-	rv = ec_command(EC_CMD_GET_BUILD_INFO, 0,
-			NULL, 0, ec_inbuf, ec_max_insize);
+	rv = ec_command(EC_CMD_GET_BUILD_INFO, 0, NULL, 0, ec_inbuf,
+			ec_max_insize);
 	if (rv < 0) {
 		fprintf(stderr, "ERROR: EC_CMD_GET_BUILD_INFO failed: %d\n",
-				rv);
+			rv);
 		goto exit;
 	}
 
@@ -1137,7 +1178,8 @@ int cmd_version(int argc, char *argv[])
 		printf("RW cros fwid:  %s\n", r.cros_fwid_rw);
 	printf("Firmware copy: %s\n",
 	       (r.current_image < ARRAY_SIZE(image_names) ?
-		image_names[r.current_image] : "?"));
+			image_names[r.current_image] :
+			"?"));
 	printf("Build info:    %s\n", build_string);
 exit:
 	printf("Tool version:  %s %s %s\n", CROS_ECTOOL_VERSION, DATE, BUILDER);
@@ -1145,7 +1187,6 @@ exit:
 	return rv;
 }
 
-
 int cmd_read_test(int argc, char *argv[])
 {
 	struct ec_params_read_test p;
@@ -1180,8 +1221,8 @@ int cmd_read_test(int argc, char *argv[])
 	for (i = 0; i < size; i += sizeof(r.data)) {
 		p.offset = offset + i / sizeof(uint32_t);
 		p.size = MIN(size - i, sizeof(r.data));
-		rv = ec_command(EC_CMD_READ_TEST, 0, &p, sizeof(p),
-				&r, sizeof(r));
+		rv = ec_command(EC_CMD_READ_TEST, 0, &p, sizeof(p), &r,
+				sizeof(r));
 		if (rv < 0) {
 			fprintf(stderr, "Read error at offset %d\n", i);
 			free(buf);
@@ -1210,7 +1251,6 @@ int cmd_read_test(int argc, char *argv[])
 	return 0;
 }
 
-
 int cmd_reboot_ec(int argc, char *argv[])
 {
 	struct ec_params_reboot_ec p;
@@ -1293,22 +1333,25 @@ int cmd_reboot_ap_on_g3(int argc, char *argv[])
 static void cmd_rgbkbd_help(char *cmd)
 {
 	fprintf(stderr,
-	"  Usage1: %s <key> <RGB> [<RGB> ...]\n"
-	"          Set the color of <key> to <RGB>. Multiple colors for\n"
-	"          adjacent keys can be set at once.\n"
-	"\n"
-	"  Usage2: %s clear <RGB>\n"
-	"          Set the color of all keys to <RGB>.\n"
-	"\n"
-	"  Usage3: %s demo <num>\n"
-	"          Run demo-<num>. 0: Off, 1: Flow, 2: Dot.\n"
-	"\n"
-	"  Usage4: %s scale <key> <val>\n"
-	"          Set the scale parameter of key_<key> to <val>.\n"
-	"          <val> is a 24-bit integer where scale values are encoded\n"
-	"          as R=23:16, G=15:8, B=7:0.\n"
-	"\n",
-	cmd, cmd, cmd, cmd);
+		"  Usage1: %s <key> <RGB> [<RGB> ...]\n"
+		"          Set the color of <key> to <RGB>. Multiple colors for\n"
+		"          adjacent keys can be set at once.\n"
+		"\n"
+		"  Usage2: %s clear <RGB>\n"
+		"          Set the color of all keys to <RGB>.\n"
+		"\n"
+		"  Usage3: %s demo <num>\n"
+		"          Run demo-<num>. 0: Off, 1: Flow, 2: Dot.\n"
+		"\n"
+		"  Usage4: %s scale <key> <val>\n"
+		"          Set the scale parameter of key_<key> to <val>.\n"
+		"          <val> is a 24-bit integer where scale values are encoded\n"
+		"          as R=23:16, G=15:8, B=7:0.\n"
+		"\n"
+		"  Usage5: %s getconfig\n"
+		"          Get the HW config supported.\n"
+		"\n",
+		cmd, cmd, cmd, cmd, cmd);
 }
 
 static int cmd_rgbkbd_parse_rgb_text(const char *text, struct rgb_s *color)
@@ -1336,7 +1379,7 @@ static int cmd_rgbkbd_set_color(int argc, char *argv[])
 	int rv = -1;
 
 	outlen = sizeof(*p) + sizeof(struct rgb_s) * EC_RGBKBD_MAX_KEY_COUNT;
-	p = malloc(outlen);
+	p = (struct ec_params_rgbkbd_set_color *)malloc(outlen);
 	if (p == NULL)
 		return -1;
 	memset(p, 0, outlen);
@@ -1372,26 +1415,24 @@ static int cmd_rgbkbd(int argc, char *argv[])
 {
 	int val;
 	char *e;
-	int rv = -1;;
+	int rv = -1;
+	struct ec_params_rgbkbd p;
+	struct ec_response_rgbkbd r;
 
-	if (argc < 3) {
+	if (argc < 2) {
 		cmd_rgbkbd_help(argv[0]);
 		return -1;
 	}
 
 	if (argc == 3 && !strcasecmp(argv[1], "clear")) {
 		/* Usage 2 */
-		struct ec_params_rgbkbd p;
-
 		p.subcmd = EC_RGBKBD_SUBCMD_CLEAR;
 		if (cmd_rgbkbd_parse_rgb_text(argv[2], &p.color))
 			return -1;
 
-		rv = ec_command(EC_CMD_RGBKBD, 0, &p, sizeof(p), NULL, 0);
+		rv = ec_command(EC_CMD_RGBKBD, 0, &p, sizeof(p), &r, sizeof(r));
 	} else if (argc == 3 && !strcasecmp(argv[1], "demo")) {
 		/* Usage 3 */
-		struct ec_params_rgbkbd p;
-
 		val = strtol(argv[2], &e, 0);
 		if ((e && *e) || val >= EC_RGBKBD_DEMO_COUNT) {
 			fprintf(stderr, "Invalid demo id: %s\n", argv[2]);
@@ -1399,11 +1440,9 @@ static int cmd_rgbkbd(int argc, char *argv[])
 		}
 		p.subcmd = EC_RGBKBD_SUBCMD_DEMO;
 		p.demo = val;
-		rv = ec_command(EC_CMD_RGBKBD, 0, &p, sizeof(p), NULL, 0);
+		rv = ec_command(EC_CMD_RGBKBD, 0, &p, sizeof(p), &r, sizeof(r));
 	} else if (argc == 4 && !strcasecmp(argv[1], "scale")) {
 		/* Usage 4 */
-		struct ec_params_rgbkbd p;
-
 		val = strtol(argv[2], &e, 0);
 		if ((e && *e) || val > EC_RGBKBD_MAX_KEY_COUNT) {
 			fprintf(stderr, "Invalid key number: %s\n", argv[2]);
@@ -1415,7 +1454,35 @@ static int cmd_rgbkbd(int argc, char *argv[])
 			return -1;
 		}
 		p.subcmd = EC_RGBKBD_SUBCMD_SET_SCALE;
-		rv = ec_command(EC_CMD_RGBKBD, 0, &p, sizeof(p), NULL, 0);
+		rv = ec_command(EC_CMD_RGBKBD, 0, &p, sizeof(p), &r, sizeof(r));
+	} else if (argc == 2 && !strcasecmp(argv[1], "getconfig")) {
+		/* Usage 5 */
+		const char *type;
+
+		p.subcmd = EC_RGBKBD_SUBCMD_GET_CONFIG;
+		rv = ec_command(EC_CMD_RGBKBD, 0, &p, sizeof(p), &r, sizeof(r));
+
+		if (rv < 0)
+			return rv;
+
+		switch ((enum ec_rgbkbd_type)r.rgbkbd_type) {
+		case EC_RGBKBD_TYPE_PER_KEY:
+			type = "EC_RGBKBD_TYPE_PER_KEY";
+			break;
+		case EC_RGBKBD_TYPE_FOUR_ZONES_40_LEDS:
+			type = "EC_RGBKBD_TYPE_FOUR_ZONES_40_LEDS";
+			break;
+		case EC_RGBKBD_TYPE_FOUR_ZONES_12_LEDS:
+			type = "EC_RGBKBD_TYPE_FOUR_ZONES_12_LEDS";
+			break;
+		case EC_RGBKBD_TYPE_FOUR_ZONES_4_LEDS:
+			type = "EC_RGBKBD_TYPE_FOUR_ZONES_4_LEDS";
+			break;
+		default:
+			type = "EC_RGBKBD_TYPE_UNKNOWN";
+		}
+
+		printf("RGBKBD_TYPE: %s\n", type);
 	} else {
 		/* Usage 1 */
 		rv = cmd_rgbkbd_set_color(argc, argv);
@@ -1501,8 +1568,8 @@ int cmd_flash_info(int argc, char *argv[])
 
 	if (cmdver >= 1) {
 		/* Fields added in ver.1 available */
-		printf("WriteIdealSize %d\nFlags 0x%x\n",
-		       r.write_ideal_size, r.flags);
+		printf("WriteIdealSize %d\nFlags 0x%x\n", r.write_ideal_size,
+		       r.flags);
 	}
 
 	return 0;
@@ -1590,8 +1657,8 @@ int cmd_flash_read(int argc, char *argv[])
 	uint8_t *buf;
 
 	if (argc < 4) {
-		fprintf(stderr,
-			"Usage: %s <offset> <size> <filename>\n", argv[0]);
+		fprintf(stderr, "Usage: %s <offset> <size> <filename>\n",
+			argv[0]);
 		return -1;
 	}
 	offset = strtol(argv[1], &e, 0);
@@ -1654,8 +1721,7 @@ int cmd_flash_write(int argc, char *argv[])
 	printf("Writing to offset %d...\n", offset);
 
 	/* Write data in chunks */
-	rv = ec_flash_write((const uint8_t *)(buf), offset,
-			    size);
+	rv = ec_flash_write((const uint8_t *)(buf), offset, size);
 
 	free(buf);
 
@@ -1705,7 +1771,6 @@ int cmd_flash_erase(int argc, char *argv[])
 	return 0;
 }
 
-
 static void print_flash_protect_flags(const char *desc, uint32_t flags)
 {
 	printf("%s 0x%08x", desc, flags);
@@ -1736,7 +1801,6 @@ static void print_flash_protect_flags(const char *desc, uint32_t flags)
 	printf("\n");
 }
 
-
 int cmd_flash_protect(int argc, char *argv[])
 {
 	struct ec_params_flash_protect p;
@@ -1759,8 +1823,8 @@ int cmd_flash_protect(int argc, char *argv[])
 			p.mask |= EC_FLASH_PROTECT_RO_AT_BOOT;
 	}
 
-	rv = ec_command(EC_CMD_FLASH_PROTECT, EC_VER_FLASH_PROTECT,
-			&p, sizeof(p), &r, sizeof(r));
+	rv = ec_command(EC_CMD_FLASH_PROTECT, EC_VER_FLASH_PROTECT, &p,
+			sizeof(p), &r, sizeof(r));
 	if (rv < 0)
 		return rv;
 	if (rv < sizeof(r)) {
@@ -1775,12 +1839,15 @@ int cmd_flash_protect(int argc, char *argv[])
 
 	/* Check if we got all the flags we asked for */
 	if ((r.flags & p.mask) != (p.flags & p.mask)) {
-		fprintf(stderr, "Unable to set requested flags "
+		fprintf(stderr,
+			"Unable to set requested flags "
 			"(wanted mask 0x%08x flags 0x%08x)\n",
 			p.mask, p.flags);
 		if (p.mask & ~r.writable_flags)
-			fprintf(stderr, "Which is expected, because writable "
-				"mask is 0x%08x.\n", r.writable_flags);
+			fprintf(stderr,
+				"Which is expected, because writable "
+				"mask is 0x%08x.\n",
+				r.writable_flags);
 
 		return -1;
 	}
@@ -1816,10 +1883,10 @@ int cmd_rw_hash_pd(int argc, char *argv[])
 			fprintf(stderr, "Bad RW hash\n");
 			return -1;
 		}
-		rwp[0] = (uint8_t)  (val >> 0) & 0xff;
-		rwp[1] = (uint8_t)  (val >> 8) & 0xff;
-		rwp[2] = (uint8_t) (val >> 16) & 0xff;
-		rwp[3] = (uint8_t) (val >> 24) & 0xff;
+		rwp[0] = (uint8_t)(val >> 0) & 0xff;
+		rwp[1] = (uint8_t)(val >> 8) & 0xff;
+		rwp[2] = (uint8_t)(val >> 16) & 0xff;
+		rwp[3] = (uint8_t)(val >> 24) & 0xff;
 		rwp += 4;
 	}
 	rv = ec_command(EC_CMD_USB_PD_RW_HASH_ENTRY, 0, p, sizeof(*p), NULL, 0);
@@ -1832,8 +1899,8 @@ int cmd_rwsig_status(int argc, char *argv[])
 	int rv;
 	struct ec_response_rwsig_check_status resp;
 
-	rv = ec_command(EC_CMD_RWSIG_CHECK_STATUS, 0, NULL, 0,
-			&resp, sizeof(resp));
+	rv = ec_command(EC_CMD_RWSIG_CHECK_STATUS, 0, NULL, 0, &resp,
+			sizeof(resp));
 	if (rv < 0)
 		return rv;
 
@@ -1883,9 +1950,10 @@ enum rwsig_info_fields {
 	RWSIG_INFO_FIELD_HASH_ALG = BIT(2),
 	RWSIG_INFO_FIELD_KEY_IS_VALID = BIT(3),
 	RWSIG_INFO_FIELD_KEY_ID = BIT(4),
-	RWSIG_INFO_FIELD_ALL = RWSIG_INFO_FIELD_SIG_ALG |
-		RWSIG_INFO_FIELD_KEY_VERSION | RWSIG_INFO_FIELD_HASH_ALG |
-		RWSIG_INFO_FIELD_KEY_IS_VALID | RWSIG_INFO_FIELD_KEY_ID
+	RWSIG_INFO_FIELD_ALL =
+		RWSIG_INFO_FIELD_SIG_ALG | RWSIG_INFO_FIELD_KEY_VERSION |
+		RWSIG_INFO_FIELD_HASH_ALG | RWSIG_INFO_FIELD_KEY_IS_VALID |
+		RWSIG_INFO_FIELD_KEY_ID
 };
 
 static int rwsig_info(enum rwsig_info_fields fields)
@@ -2070,7 +2138,6 @@ int cmd_sysinfo(int argc, char **argv)
 		if (print_prefix)
 			printf("Flags: ");
 		printf("0x%08x\n", r.flags);
-
 	}
 
 	if (fields & SYSINFO_FIELD_CURRENT_IMAGE) {
@@ -2082,8 +2149,9 @@ int cmd_sysinfo(int argc, char **argv)
 	return 0;
 
 sysinfo_error_usage:
-	fprintf(stderr, "Usage: %s "
-			"[flags|reset_flags|firmware_copy]\n",
+	fprintf(stderr,
+		"Usage: %s "
+		"[flags|reset_flags|firmware_copy]\n",
 		argv[0]);
 	return -1;
 }
@@ -2138,8 +2206,8 @@ static void *fp_download_frame(struct ec_response_fp_info *info, int index)
 	void *buffer;
 	uint8_t *ptr;
 	int cmdver = ec_cmd_version_supported(EC_CMD_FP_INFO, 1) ? 1 : 0;
-	int rsize = cmdver == 1 ? sizeof(*info)
-				: sizeof(struct ec_response_fp_info_v0);
+	int rsize = cmdver == 1 ? sizeof(*info) :
+				  sizeof(struct ec_response_fp_info_v0);
 	const int max_attempts = 3;
 	int num_attempts;
 
@@ -2152,7 +2220,7 @@ static void *fp_download_frame(struct ec_response_fp_info *info, int index)
 		return NULL;
 
 	if (index == FP_FRAME_INDEX_SIMPLE_IMAGE) {
-		size = (size_t)info->width * info->bpp/8 * info->height;
+		size = (size_t)info->width * info->bpp / 8 * info->height;
 		index = FP_FRAME_INDEX_RAW_IMAGE;
 	} else if (index == FP_FRAME_INDEX_RAW_IMAGE) {
 		size = info->frame_size;
@@ -2174,8 +2242,8 @@ static void *fp_download_frame(struct ec_response_fp_info *info, int index)
 		num_attempts = 0;
 		while (num_attempts < max_attempts) {
 			num_attempts++;
-			rv = ec_command(EC_CMD_FP_FRAME, 0, &p, sizeof(p),
-					ptr, stride);
+			rv = ec_command(EC_CMD_FP_FRAME, 0, &p, sizeof(p), ptr,
+					stride);
 			if (rv >= 0)
 				break;
 			if (rv == -EECRESULT - EC_RES_ACCESS_DENIED)
@@ -2253,7 +2321,7 @@ int cmd_fp_mode(int argc, char *argv[])
 		printf("finger-up ");
 	if (r.mode & FP_MODE_ENROLL_SESSION)
 		printf("enroll%s ",
-			r.mode & FP_MODE_ENROLL_IMAGE ? "+image" : "");
+		       r.mode & FP_MODE_ENROLL_IMAGE ? "+image" : "");
 	if (r.mode & FP_MODE_MATCH)
 		printf("match ");
 	if (r.mode & FP_MODE_CAPTURE)
@@ -2307,7 +2375,7 @@ int cmd_fp_stats(int argc, char *argv[])
 		printf("Invalid\n");
 	else
 		printf("%d us (finger: %d)\n", r.matching_time_us,
-			r.template_matched);
+		       r.template_matched);
 
 	printf("Last overall time:  ");
 	if (r.timestamps_invalid)
@@ -2323,8 +2391,8 @@ int cmd_fp_info(int argc, char *argv[])
 	struct ec_response_fp_info r;
 	int rv;
 	int cmdver = ec_cmd_version_supported(EC_CMD_FP_INFO, 1) ? 1 : 0;
-	int rsize = cmdver == 1 ? sizeof(r)
-				: sizeof(struct ec_response_fp_info_v0);
+	int rsize = cmdver == 1 ? sizeof(r) :
+				  sizeof(struct ec_response_fp_info_v0);
 	uint16_t dead;
 
 	rv = ec_command(EC_CMD_FP_INFO, cmdver, NULL, 0, &r, rsize);
@@ -2332,7 +2400,7 @@ int cmd_fp_info(int argc, char *argv[])
 		return rv;
 
 	printf("Fingerprint sensor: vendor %x product %x model %x version %x\n",
-		r.vendor_id, r.product_id, r.model_id, r.version);
+	       r.vendor_id, r.product_id, r.model_id, r.version);
 	printf("Image: size %dx%d %d bpp\n", r.width, r.height, r.bpp);
 	printf("Error flags: %s%s%s%s\n",
 	       r.errors & FP_ERROR_NO_IRQ ? "NO_IRQ " : "",
@@ -2437,7 +2505,8 @@ int cmd_fp_frame(int argc, char *argv[])
 {
 	struct ec_response_fp_info r;
 	int idx = (argc == 2 && !strcasecmp(argv[1], "raw")) ?
-		FP_FRAME_INDEX_RAW_IMAGE : FP_FRAME_INDEX_SIMPLE_IMAGE;
+			  FP_FRAME_INDEX_RAW_IMAGE :
+			  FP_FRAME_INDEX_SIMPLE_IMAGE;
 	uint8_t *buffer = (uint8_t *)(fp_download_frame(&r, idx));
 	uint8_t *ptr = buffer;
 	int x, y;
@@ -2472,8 +2541,8 @@ int cmd_fp_template(int argc, char *argv[])
 	struct ec_params_fp_template *p =
 		(struct ec_params_fp_template *)(ec_outbuf);
 	/* TODO(b/78544921): removing 32 bits is a workaround for the MCU bug */
-	int max_chunk = ec_max_outsize
-			- offsetof(struct ec_params_fp_template, data) - 4;
+	int max_chunk = ec_max_outsize -
+			offsetof(struct ec_params_fp_template, data) - 4;
 	int idx = -1;
 	char *e;
 	int size;
@@ -2513,8 +2582,9 @@ int cmd_fp_template(int argc, char *argv[])
 		if (!size)
 			p->size |= FP_TEMPLATE_COMMIT;
 		memcpy(p->data, buffer + offset, tlen);
-		rv = ec_command(EC_CMD_FP_TEMPLATE, 0, p, tlen +
-				offsetof(struct ec_params_fp_template, data),
+		rv = ec_command(EC_CMD_FP_TEMPLATE, 0, p,
+				tlen + offsetof(struct ec_params_fp_template,
+						data),
 				NULL, 0);
 		if (rv < 0)
 			break;
@@ -2547,8 +2617,8 @@ static int in_gfu_mode(int *opos, int port)
 	p->port = port;
 	p->svid_idx = 0;
 	do {
-		ec_command(EC_CMD_USB_PD_GET_AMODE, 0, p, sizeof(*p),
-			   ec_inbuf, ec_max_insize);
+		ec_command(EC_CMD_USB_PD_GET_AMODE, 0, p, sizeof(*p), ec_inbuf,
+			   ec_max_insize);
 		if (!r->svid || (r->svid == USB_VID_GOOGLE))
 			break;
 		p->svid_idx++;
@@ -2598,8 +2668,7 @@ static int enter_gfu_mode(int port)
 		p->opos = opos;
 		p->cmd = PD_ENTER_MODE;
 
-		ec_command(EC_CMD_USB_PD_SET_AMODE, 0, p, sizeof(*p),
-			   NULL, 0);
+		ec_command(EC_CMD_USB_PD_SET_AMODE, 0, p, sizeof(*p), NULL, 0);
 		usleep(500000); /* sleep to allow time for set mode */
 		gfu_mode = in_gfu_mode(&opos, port);
 	}
@@ -2629,8 +2698,8 @@ int cmd_pd_device_info(int argc, char *argv[])
 
 	p->port = port;
 	r1 = (struct ec_params_usb_pd_discovery_entry *)ec_inbuf;
-	rv = ec_command(EC_CMD_USB_PD_DISCOVERY, 0, p, sizeof(*p),
-			ec_inbuf, ec_max_insize);
+	rv = ec_command(EC_CMD_USB_PD_DISCOVERY, 0, p, sizeof(*p), ec_inbuf,
+			ec_max_insize);
 	if (rv < 0)
 		return rv;
 
@@ -2647,8 +2716,8 @@ int cmd_pd_device_info(int argc, char *argv[])
 	}
 
 	p->port = port;
-	rv = ec_command(EC_CMD_USB_PD_DEV_INFO, 0, p, sizeof(*p),
-			ec_inbuf, ec_max_insize);
+	rv = ec_command(EC_CMD_USB_PD_DEV_INFO, 0, p, sizeof(*p), ec_inbuf,
+			ec_max_insize);
 	if (rv < 0)
 		return rv;
 
@@ -2713,8 +2782,8 @@ int cmd_flash_pd(int argc, char *argv[])
 	p->port = port;
 	p->cmd = USB_PD_FW_ERASE_SIG;
 	p->size = 0;
-	rv = ec_command(EC_CMD_USB_PD_FW_UPDATE, 0,
-			p, p->size + sizeof(*p), NULL, 0);
+	rv = ec_command(EC_CMD_USB_PD_FW_UPDATE, 0, p, p->size + sizeof(*p),
+			NULL, 0);
 
 	if (rv < 0)
 		goto pd_flash_error;
@@ -2725,8 +2794,8 @@ int cmd_flash_pd(int argc, char *argv[])
 	p->port = port;
 	p->cmd = USB_PD_FW_REBOOT;
 	p->size = 0;
-	rv = ec_command(EC_CMD_USB_PD_FW_UPDATE, 0,
-			p, p->size + sizeof(*p), NULL, 0);
+	rv = ec_command(EC_CMD_USB_PD_FW_UPDATE, 0, p, p->size + sizeof(*p),
+			NULL, 0);
 
 	if (rv < 0)
 		goto pd_flash_error;
@@ -2745,8 +2814,8 @@ int cmd_flash_pd(int argc, char *argv[])
 	p->port = port;
 	p->cmd = USB_PD_FW_FLASH_ERASE;
 	p->size = 0;
-	rv = ec_command(EC_CMD_USB_PD_FW_UPDATE, 0,
-			p, p->size + sizeof(*p), NULL, 0);
+	rv = ec_command(EC_CMD_USB_PD_FW_UPDATE, 0, p, p->size + sizeof(*p),
+			NULL, 0);
 
 	/* 3 secs should allow ample time for 2KB page erases at 40ms */
 	usleep(3000000);
@@ -2764,8 +2833,8 @@ int cmd_flash_pd(int argc, char *argv[])
 	for (i = 0; i < fsize; i += step) {
 		p->size = MIN(fsize - i, step);
 		memcpy(data, buf + i, p->size);
-		rv = ec_command(EC_CMD_USB_PD_FW_UPDATE, 0,
-				p, p->size + sizeof(*p), NULL, 0);
+		rv = ec_command(EC_CMD_USB_PD_FW_UPDATE, 0, p,
+				p->size + sizeof(*p), NULL, 0);
 		if (rv < 0)
 			goto pd_flash_error;
 
@@ -2783,8 +2852,8 @@ int cmd_flash_pd(int argc, char *argv[])
 	fprintf(stderr, "Rebooting PD into new RW\n");
 	p->cmd = USB_PD_FW_REBOOT;
 	p->size = 0;
-	rv = ec_command(EC_CMD_USB_PD_FW_UPDATE, 0,
-			p, p->size + sizeof(*p), NULL, 0);
+	rv = ec_command(EC_CMD_USB_PD_FW_UPDATE, 0, p, p->size + sizeof(*p),
+			NULL, 0);
 
 	if (rv < 0)
 		goto pd_flash_error;
@@ -2859,15 +2928,15 @@ int cmd_pd_get_amode(int argc, char *argv[])
 
 	p->svid_idx = 0;
 	do {
-		ec_command(EC_CMD_USB_PD_GET_AMODE, 0, p, sizeof(*p),
-			   ec_inbuf, ec_max_insize);
+		ec_command(EC_CMD_USB_PD_GET_AMODE, 0, p, sizeof(*p), ec_inbuf,
+			   ec_max_insize);
 		if (!r->svid)
 			break;
-		printf("%cSVID:0x%04x ", (r->opos) ? '*' : ' ',
-		       r->svid);
+		printf("%cSVID:0x%04x ", (r->opos) ? '*' : ' ', r->svid);
 		for (i = 0; i < PDO_MODES; i++) {
-			printf("%c0x%08x ", (r->opos && (r->opos == i + 1)) ?
-			       '*' : ' ', r->vdo[i]);
+			printf("%c0x%08x ",
+			       (r->opos && (r->opos == i + 1)) ? '*' : ' ',
+			       r->vdo[i]);
 		}
 		printf("\n");
 		p->svid_idx++;
@@ -2898,7 +2967,6 @@ int cmd_serial_test(int argc, char *argv[])
 	return 0;
 }
 
-
 int cmd_port_80_flood(int argc, char *argv[])
 {
 	int i;
@@ -2970,8 +3038,8 @@ int cmd_smart_discharge(int argc, char *argv[])
 		}
 	}
 
-	rv = ec_command(EC_CMD_SMART_DISCHARGE, 0, p, sizeof(*p),
-			r, ec_max_insize);
+	rv = ec_command(EC_CMD_SMART_DISCHARGE, 0, p, sizeof(*p), r,
+			ec_max_insize);
 	if (rv < 0) {
 		perror("ERROR: EC_CMD_SMART_DISCHARGE failed");
 		return rv;
@@ -2984,10 +3052,10 @@ int cmd_smart_discharge(int argc, char *argv[])
 	}
 
 	printf("%-27s %5d h\n", "Hours to zero capacity:", r->hours_to_zero);
-	printf("%-27s %5d mAh (%d %%)\n", "Stay-up threshold:",
-	       r->dzone.stayup, cap > 0 ? r->dzone.stayup * 100 / cap : -1);
-	printf("%-27s %5d mAh (%d %%)\n", "Cutoff threshold:",
-	       r->dzone.cutoff, cap > 0 ? r->dzone.cutoff * 100 / cap : -1);
+	printf("%-27s %5d mAh (%d %%)\n", "Stay-up threshold:", r->dzone.stayup,
+	       cap > 0 ? r->dzone.stayup * 100 / cap : -1);
+	printf("%-27s %5d mAh (%d %%)\n", "Cutoff threshold:", r->dzone.cutoff,
+	       cap > 0 ? r->dzone.cutoff * 100 / cap : -1);
 	printf("%-27s %5d uA\n", "Hibernate discharge rate:", r->drate.hibern);
 	printf("%-27s %5d uA\n", "Cutoff discharge rate:", r->drate.cutoff);
 
@@ -3041,8 +3109,8 @@ int cmd_stress_test(int argc, char *argv[])
 		}
 	}
 
-	printf("Stress test tool version: %s %s %s\n",
-	       CROS_ECTOOL_VERSION, DATE, BUILDER);
+	printf("Stress test tool version: %s %s %s\n", CROS_ECTOOL_VERSION,
+	       DATE, BUILDER);
 
 	start_time = time(NULL);
 	last_update_time = start_time;
@@ -3067,16 +3135,16 @@ int cmd_stress_test(int argc, char *argv[])
 		struct ec_response_hello hello_r;
 
 		/* Request EC Version Strings */
-		rv = ec_command(EC_CMD_GET_VERSION, 0,
-				NULL, 0, &ver_r, sizeof(ver_r));
+		rv = ec_command(EC_CMD_GET_VERSION, 0, NULL, 0, &ver_r,
+				sizeof(ver_r));
 		if (rv < 0) {
 			failures++;
 			perror("ERROR: EC_CMD_GET_VERSION failed");
 		}
-		ver_r.version_string_ro[sizeof(ver_r.version_string_ro) - 1]
-			= '\0';
-		ver_r.version_string_rw[sizeof(ver_r.version_string_rw) - 1]
-			= '\0';
+		ver_r.version_string_ro[sizeof(ver_r.version_string_ro) - 1] =
+			'\0';
+		ver_r.version_string_rw[sizeof(ver_r.version_string_rw) - 1] =
+			'\0';
 		if (strlen(ver_r.version_string_ro) == 0) {
 			failures++;
 			fprintf(stderr, "RO version string is empty\n");
@@ -3089,8 +3157,8 @@ int cmd_stress_test(int argc, char *argv[])
 		usleep(rand_r(&rand_seed) % max_sleep_usec);
 
 		/* Request EC Build String */
-		rv = ec_command(EC_CMD_GET_BUILD_INFO, 0,
-				NULL, 0, ec_inbuf, ec_max_insize);
+		rv = ec_command(EC_CMD_GET_BUILD_INFO, 0, NULL, 0, ec_inbuf,
+				ec_max_insize);
 		if (rv < 0) {
 			failures++;
 			perror("ERROR: EC_CMD_GET_BUILD_INFO failed");
@@ -3133,8 +3201,7 @@ int cmd_stress_test(int argc, char *argv[])
 			now = time(NULL);
 			printf("Update: attempt %" PRIu64 " round %" PRIu64
 			       " | took %.f seconds\n",
-			       attempt, round,
-			       difftime(now, last_update_time));
+			       attempt, round, difftime(now, last_update_time));
 			last_update_time = now;
 		}
 
@@ -3146,7 +3213,7 @@ int cmd_stress_test(int argc, char *argv[])
 	now = time(NULL);
 	printf("End time:        %s\n", ctime(&now));
 	printf("Total runtime:   %.f seconds\n",
-		difftime(time(NULL), start_time));
+	       difftime(time(NULL), start_time));
 	printf("Total failures:  %" PRIu64 "\n", failures);
 	return 0;
 }
@@ -3164,8 +3231,8 @@ int read_mapped_temperature(int id)
 	} else if (id < EC_TEMP_SENSOR_ENTRIES)
 		rv = read_mapped_mem8(EC_MEMMAP_TEMP_SENSOR + id);
 	else if (read_mapped_mem8(EC_MEMMAP_THERMAL_VERSION) >= 2)
-		rv = read_mapped_mem8(EC_MEMMAP_TEMP_SENSOR_B +
-				      id - EC_TEMP_SENSOR_ENTRIES);
+		rv = read_mapped_mem8(EC_MEMMAP_TEMP_SENSOR_B + id -
+				      EC_TEMP_SENSOR_ENTRIES);
 	else {
 		/* Sensor in second bank, but second bank isn't supported */
 		rv = EC_TEMP_SENSOR_NOT_PRESENT;
@@ -3180,8 +3247,8 @@ static int get_thermal_fan_percent(int temp, int sensor_id)
 	int rv = 0;
 
 	p.sensor_num = sensor_id;
-	rv = ec_command(EC_CMD_THERMAL_GET_THRESHOLD, 1, &p, sizeof(p),
-			&r, sizeof(r));
+	rv = ec_command(EC_CMD_THERMAL_GET_THRESHOLD, 1, &p, sizeof(p), &r,
+			sizeof(r));
 
 	if (rv <= 0 || r.temp_fan_max == r.temp_fan_off)
 		return -1;
@@ -3190,7 +3257,7 @@ static int get_thermal_fan_percent(int temp, int sensor_id)
 	if (temp > r.temp_fan_max)
 		return 100;
 	return 100 * (temp - r.temp_fan_off) /
-		     (r.temp_fan_max - r.temp_fan_off);
+	       (r.temp_fan_max - r.temp_fan_off);
 }
 
 static int cmd_temperature_print(int id, int mtemp)
@@ -3201,8 +3268,8 @@ static int cmd_temperature_print(int id, int mtemp)
 	int temp = mtemp + EC_TEMP_SENSOR_OFFSET;
 
 	p.id = id;
-	rc = ec_command(EC_CMD_TEMP_SENSOR_GET_INFO, 0, &p, sizeof(p),
-			&r, sizeof(r));
+	rc = ec_command(EC_CMD_TEMP_SENSOR_GET_INFO, 0, &p, sizeof(p), &r,
+			sizeof(r));
 	if (rc < 0)
 		return rc;
 	printf("%-20s  %d K (= %d C) %11d%%\n", r.sensor_name, temp,
@@ -3254,8 +3321,7 @@ int cmd_temperature(int argc, char *argv[])
 		return -1;
 	}
 
-	if (id < 0 ||
-	    id >= EC_MAX_TEMP_SENSOR_ENTRIES) {
+	if (id < 0 || id >= EC_MAX_TEMP_SENSOR_ENTRIES) {
 		printf("Sensor ID invalid.\n");
 		return -1;
 	}
@@ -3283,7 +3349,6 @@ int cmd_temperature(int argc, char *argv[])
 	}
 }
 
-
 int cmd_temp_sensor_info(int argc, char *argv[])
 {
 	struct ec_params_temp_sensor_get_info p;
@@ -3301,8 +3366,8 @@ int cmd_temp_sensor_info(int argc, char *argv[])
 			if (read_mapped_temperature(p.id) ==
 			    EC_TEMP_SENSOR_NOT_PRESENT)
 				continue;
-			rv = ec_command(EC_CMD_TEMP_SENSOR_GET_INFO, 0,
-					&p, sizeof(p), &r, sizeof(r));
+			rv = ec_command(EC_CMD_TEMP_SENSOR_GET_INFO, 0, &p,
+					sizeof(p), &r, sizeof(r));
 			if (rv < 0)
 				continue;
 			printf("%d: %d %s\n", p.id, r.sensor_type,
@@ -3317,8 +3382,8 @@ int cmd_temp_sensor_info(int argc, char *argv[])
 		return -1;
 	}
 
-	rv = ec_command(EC_CMD_TEMP_SENSOR_GET_INFO, 0,
-			&p, sizeof(p), &r, sizeof(r));
+	rv = ec_command(EC_CMD_TEMP_SENSOR_GET_INFO, 0, &p, sizeof(p), &r,
+			sizeof(r));
 	if (rv < 0)
 		return rv;
 
@@ -3328,7 +3393,6 @@ int cmd_temp_sensor_info(int argc, char *argv[])
 	return 0;
 }
 
-
 int cmd_thermal_get_threshold_v0(int argc, char *argv[])
 {
 	struct ec_params_thermal_get_threshold p;
@@ -3337,8 +3401,8 @@ int cmd_thermal_get_threshold_v0(int argc, char *argv[])
 	int rv;
 
 	if (argc != 3) {
-		fprintf(stderr,
-			"Usage: %s <sensortypeid> <thresholdid>\n", argv[0]);
+		fprintf(stderr, "Usage: %s <sensortypeid> <thresholdid>\n",
+			argv[0]);
 		return -1;
 	}
 
@@ -3354,18 +3418,17 @@ int cmd_thermal_get_threshold_v0(int argc, char *argv[])
 		return -1;
 	}
 
-	rv = ec_command(EC_CMD_THERMAL_GET_THRESHOLD, 0,
-			&p, sizeof(p), &r, sizeof(r));
+	rv = ec_command(EC_CMD_THERMAL_GET_THRESHOLD, 0, &p, sizeof(p), &r,
+			sizeof(r));
 	if (rv < 0)
 		return rv;
 
-	printf("Threshold %d for sensor type %d is %d K.\n",
-			p.threshold_id, p.sensor_type, r.value);
+	printf("Threshold %d for sensor type %d is %d K.\n", p.threshold_id,
+	       p.sensor_type, r.value);
 
 	return 0;
 }
 
-
 int cmd_thermal_set_threshold_v0(int argc, char *argv[])
 {
 	struct ec_params_thermal_set_threshold p;
@@ -3397,18 +3460,17 @@ int cmd_thermal_set_threshold_v0(int argc, char *argv[])
 		return -1;
 	}
 
-	rv = ec_command(EC_CMD_THERMAL_SET_THRESHOLD, 0,
-			&p, sizeof(p), NULL, 0);
+	rv = ec_command(EC_CMD_THERMAL_SET_THRESHOLD, 0, &p, sizeof(p), NULL,
+			0);
 	if (rv < 0)
 		return rv;
 
-	printf("Threshold %d for sensor type %d set to %d.\n",
-			p.threshold_id, p.sensor_type, p.value);
+	printf("Threshold %d for sensor type %d set to %d.\n", p.threshold_id,
+	       p.sensor_type, p.value);
 
 	return 0;
 }
 
-
 int cmd_thermal_get_threshold_v1(int argc, char *argv[])
 {
 	struct ec_params_thermal_get_threshold_v1 p;
@@ -3420,31 +3482,27 @@ int cmd_thermal_get_threshold_v1(int argc, char *argv[])
 
 	printf("sensor  warn  high  halt   fan_off fan_max   name\n");
 	for (i = 0; i < EC_MAX_TEMP_SENSOR_ENTRIES; i++) {
-
-		if (read_mapped_temperature(i) ==
-			EC_TEMP_SENSOR_NOT_PRESENT)
+		if (read_mapped_temperature(i) == EC_TEMP_SENSOR_NOT_PRESENT)
 			continue;
 
 		/* ask for one */
 		p.sensor_num = i;
-		rv = ec_command(EC_CMD_THERMAL_GET_THRESHOLD, 1,
-				&p, sizeof(p), &r, sizeof(r));
-		if (rv <= 0)		/* stop on first failure */
+		rv = ec_command(EC_CMD_THERMAL_GET_THRESHOLD, 1, &p, sizeof(p),
+				&r, sizeof(r));
+		if (rv <= 0) /* stop on first failure */
 			break;
 
 		/* ask for its name, too */
 		pi.id = i;
-		rv = ec_command(EC_CMD_TEMP_SENSOR_GET_INFO, 0,
-				&pi, sizeof(pi), &ri, sizeof(ri));
+		rv = ec_command(EC_CMD_TEMP_SENSOR_GET_INFO, 0, &pi, sizeof(pi),
+				&ri, sizeof(ri));
 
 		/* print what we know */
-		printf(" %2d      %3d   %3d    %3d    %3d     %3d     %s\n",
-		       i,
+		printf(" %2d      %3d   %3d    %3d    %3d     %3d     %s\n", i,
 		       r.temp_host[EC_TEMP_THRESH_WARN],
 		       r.temp_host[EC_TEMP_THRESH_HIGH],
-		       r.temp_host[EC_TEMP_THRESH_HALT],
-		       r.temp_fan_off, r.temp_fan_max,
-		       rv > 0 ? ri.sensor_name : "?");
+		       r.temp_host[EC_TEMP_THRESH_HALT], r.temp_fan_off,
+		       r.temp_fan_max, rv > 0 ? ri.sensor_name : "?");
 	}
 	if (i)
 		printf("(all temps in degrees Kelvin)\n");
@@ -3474,8 +3532,8 @@ int cmd_thermal_set_threshold_v1(int argc, char *argv[])
 	}
 
 	p.sensor_num = n;
-	rv = ec_command(EC_CMD_THERMAL_GET_THRESHOLD, 1,
-			&p, sizeof(p), &r, sizeof(r));
+	rv = ec_command(EC_CMD_THERMAL_GET_THRESHOLD, 1, &p, sizeof(p), &r,
+			sizeof(r));
 	if (rv <= 0)
 		return rv;
 
@@ -3495,7 +3553,7 @@ int cmd_thermal_set_threshold_v1(int argc, char *argv[])
 		case 2:
 		case 3:
 		case 4:
-			s.cfg.temp_host[i-2] = val;
+			s.cfg.temp_host[i - 2] = val;
 			break;
 		case 5:
 			s.cfg.temp_fan_off = val;
@@ -3506,8 +3564,8 @@ int cmd_thermal_set_threshold_v1(int argc, char *argv[])
 		}
 	}
 
-	rv = ec_command(EC_CMD_THERMAL_SET_THRESHOLD, 1,
-			&s, sizeof(s), NULL, 0);
+	rv = ec_command(EC_CMD_THERMAL_SET_THRESHOLD, 1, &s, sizeof(s), NULL,
+			0);
 
 	return rv;
 }
@@ -3534,7 +3592,6 @@ int cmd_thermal_set_threshold(int argc, char *argv[])
 	return -1;
 }
 
-
 static int get_num_fans(void)
 {
 	int idx, rv;
@@ -3564,13 +3621,13 @@ int cmd_thermal_auto_fan_ctrl(int argc, char *argv[])
 	char *e;
 	int cmdver = 1;
 
-	if (!ec_cmd_version_supported(EC_CMD_THERMAL_AUTO_FAN_CTRL, cmdver)
-	    || (argc == 1)) {
+	if (!ec_cmd_version_supported(EC_CMD_THERMAL_AUTO_FAN_CTRL, cmdver) ||
+	    (argc == 1)) {
 		/* If no argument is provided then enable auto fan ctrl */
 		/* for all fans by using version 0 of the host command */
 
-		rv = ec_command(EC_CMD_THERMAL_AUTO_FAN_CTRL, 0,
-				NULL, 0, NULL, 0);
+		rv = ec_command(EC_CMD_THERMAL_AUTO_FAN_CTRL, 0, NULL, 0, NULL,
+				0);
 		if (rv < 0)
 			return rv;
 
@@ -3590,8 +3647,8 @@ int cmd_thermal_auto_fan_ctrl(int argc, char *argv[])
 		return -1;
 	}
 
-	rv = ec_command(EC_CMD_THERMAL_AUTO_FAN_CTRL, cmdver,
-			&p_v1, sizeof(p_v1), NULL, 0);
+	rv = ec_command(EC_CMD_THERMAL_AUTO_FAN_CTRL, cmdver, &p_v1,
+			sizeof(p_v1), NULL, 0);
 	if (rv < 0)
 		return rv;
 
@@ -3654,7 +3711,6 @@ int cmd_pwm_get_fan_rpm(int argc, char *argv[])
 	return 0;
 }
 
-
 int cmd_pwm_set_fan_rpm(int argc, char *argv[])
 {
 	struct ec_params_pwm_set_fan_target_rpm_v1 p_v1;
@@ -3669,8 +3725,7 @@ int cmd_pwm_set_fan_rpm(int argc, char *argv[])
 		cmdver = 0;
 
 		if (argc != 2) {
-			fprintf(stderr,
-				"Usage: %s <targetrpm>\n", argv[0]);
+			fprintf(stderr, "Usage: %s <targetrpm>\n", argv[0]);
 			return -1;
 		}
 		p_v0.rpm = strtol(argv[1], &e, 0);
@@ -3679,8 +3734,8 @@ int cmd_pwm_set_fan_rpm(int argc, char *argv[])
 			return -1;
 		}
 
-		rv = ec_command(EC_CMD_PWM_SET_FAN_TARGET_RPM, cmdver,
-				&p_v0, sizeof(p_v0), NULL, 0);
+		rv = ec_command(EC_CMD_PWM_SET_FAN_TARGET_RPM, cmdver, &p_v0,
+				sizeof(p_v0), NULL, 0);
 		if (rv < 0)
 			return rv;
 
@@ -3710,8 +3765,8 @@ int cmd_pwm_set_fan_rpm(int argc, char *argv[])
 		cmdver = 0;
 		p_v0.rpm = p_v1.rpm;
 
-		rv = ec_command(EC_CMD_PWM_SET_FAN_TARGET_RPM, cmdver,
-				&p_v0, sizeof(p_v0), NULL, 0);
+		rv = ec_command(EC_CMD_PWM_SET_FAN_TARGET_RPM, cmdver, &p_v0,
+				sizeof(p_v0), NULL, 0);
 		if (rv < 0)
 			return rv;
 
@@ -3723,8 +3778,8 @@ int cmd_pwm_set_fan_rpm(int argc, char *argv[])
 			return -1;
 		}
 
-		rv = ec_command(EC_CMD_PWM_SET_FAN_TARGET_RPM, cmdver,
-				&p_v1, sizeof(p_v1), NULL, 0);
+		rv = ec_command(EC_CMD_PWM_SET_FAN_TARGET_RPM, cmdver, &p_v1,
+				sizeof(p_v1), NULL, 0);
 		if (rv < 0)
 			return rv;
 
@@ -3739,8 +3794,8 @@ int cmd_pwm_get_keyboard_backlight(int argc, char *argv[])
 	struct ec_response_pwm_get_keyboard_backlight r;
 	int rv;
 
-	rv = ec_command(EC_CMD_PWM_GET_KEYBOARD_BACKLIGHT, 0,
-			NULL, 0, &r, sizeof(r));
+	rv = ec_command(EC_CMD_PWM_GET_KEYBOARD_BACKLIGHT, 0, NULL, 0, &r,
+			sizeof(r));
 	if (rv < 0)
 		return rv;
 
@@ -3752,7 +3807,6 @@ int cmd_pwm_get_keyboard_backlight(int argc, char *argv[])
 	return 0;
 }
 
-
 int cmd_pwm_set_keyboard_backlight(int argc, char *argv[])
 {
 	struct ec_params_pwm_set_keyboard_backlight p;
@@ -3769,8 +3823,8 @@ int cmd_pwm_set_keyboard_backlight(int argc, char *argv[])
 		return -1;
 	}
 
-	rv = ec_command(EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT, 0,
-			&p, sizeof(p), NULL, 0);
+	rv = ec_command(EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT, 0, &p, sizeof(p),
+			NULL, 0);
 	if (rv < 0)
 		return rv;
 
@@ -3813,7 +3867,6 @@ int cmd_pwm_get_duty(int argc, char *argv[])
 	return 0;
 }
 
-
 int cmd_pwm_set_duty(int argc, char *argv[])
 {
 	struct ec_params_pwm_set_duty p;
@@ -3847,8 +3900,7 @@ int cmd_pwm_set_duty(int argc, char *argv[])
 		return -1;
 	}
 
-	rv = ec_command(EC_CMD_PWM_SET_DUTY, 0,
-			&p, sizeof(p), NULL, 0);
+	rv = ec_command(EC_CMD_PWM_SET_DUTY, 0, &p, sizeof(p), NULL, 0);
 	if (rv < 0)
 		return rv;
 
@@ -3867,8 +3919,7 @@ int cmd_fanduty(int argc, char *argv[])
 		struct ec_params_pwm_set_fan_duty_v0 p_v0;
 
 		if (argc != 2) {
-			fprintf(stderr,
-				"Usage: %s <percent>\n", argv[0]);
+			fprintf(stderr, "Usage: %s <percent>\n", argv[0]);
 			return -1;
 		}
 		p_v0.percent = strtol(argv[1], &e, 0);
@@ -3877,8 +3928,8 @@ int cmd_fanduty(int argc, char *argv[])
 			return -1;
 		}
 
-		rv = ec_command(EC_CMD_PWM_SET_FAN_DUTY, 0,
-				&p_v0, sizeof(p_v0), NULL, 0);
+		rv = ec_command(EC_CMD_PWM_SET_FAN_DUTY, 0, &p_v0, sizeof(p_v0),
+				NULL, 0);
 		if (rv < 0)
 			return rv;
 
@@ -3889,9 +3940,9 @@ int cmd_fanduty(int argc, char *argv[])
 	if (argc > 3 || (argc == 2 && !strcmp(argv[1], "help")) || argc == 1) {
 		printf("Usage: %s [idx] <percent>\n", argv[0]);
 		printf("'%s 0 50' - Set fan 0 duty cycle to 50 percent\n",
-			argv[0]);
+		       argv[0]);
 		printf("'%s 30' - Set all fans duty cycle to 30 percent\n",
-			argv[0]);
+		       argv[0]);
 		return -1;
 	}
 
@@ -3910,8 +3961,8 @@ int cmd_fanduty(int argc, char *argv[])
 		cmdver = 0;
 		p_v0.percent = p_v1.percent;
 
-		rv = ec_command(EC_CMD_PWM_SET_FAN_DUTY, cmdver,
-				&p_v0, sizeof(p_v0), NULL, 0);
+		rv = ec_command(EC_CMD_PWM_SET_FAN_DUTY, cmdver, &p_v0,
+				sizeof(p_v0), NULL, 0);
 		if (rv < 0)
 			return rv;
 
@@ -3923,8 +3974,8 @@ int cmd_fanduty(int argc, char *argv[])
 			return -1;
 		}
 
-		rv = ec_command(EC_CMD_PWM_SET_FAN_DUTY, cmdver,
-				&p_v1, sizeof(p_v1), NULL, 0);
+		rv = ec_command(EC_CMD_PWM_SET_FAN_DUTY, cmdver, &p_v1,
+				sizeof(p_v1), NULL, 0);
 		if (rv < 0)
 			return rv;
 
@@ -3936,9 +3987,7 @@ int cmd_fanduty(int argc, char *argv[])
 
 #define LBMSG(state) #state
 #include "lightbar_msg_list.h"
-static const char * const lightbar_cmds[] = {
-	LIGHTBAR_MSG_LIST
-};
+static const char *const lightbar_cmds[] = { LIGHTBAR_MSG_LIST };
 #undef LBMSG
 
 /* Size of field <FLD> in structure <ST> */
@@ -3957,36 +4006,36 @@ static const struct {
 	{ ST_CMD_SIZE, 0 },
 	{ ST_CMD_SIZE, 0 },
 	{ ST_CMD_SIZE, 0 },
-	{ ST_PRM_SIZE(set_brightness), 0},
-	{ ST_PRM_SIZE(seq), 0},
-	{ ST_PRM_SIZE(reg), 0},
-	{ ST_PRM_SIZE(set_rgb), 0},
+	{ ST_PRM_SIZE(set_brightness), 0 },
+	{ ST_PRM_SIZE(seq), 0 },
+	{ ST_PRM_SIZE(reg), 0 },
+	{ ST_PRM_SIZE(set_rgb), 0 },
 	{ ST_CMD_SIZE, ST_RSP_SIZE(get_seq) },
-	{ ST_PRM_SIZE(demo), 0},
+	{ ST_PRM_SIZE(demo), 0 },
 	{ ST_CMD_SIZE, ST_RSP_SIZE(get_params_v0) },
-	{ ST_PRM_SIZE(set_params_v0), 0},
+	{ ST_PRM_SIZE(set_params_v0), 0 },
 	{ ST_CMD_SIZE, ST_RSP_SIZE(version) },
 	{ ST_CMD_SIZE, ST_RSP_SIZE(get_brightness) },
 	{ ST_PRM_SIZE(get_rgb), ST_RSP_SIZE(get_rgb) },
 	{ ST_CMD_SIZE, ST_RSP_SIZE(get_demo) },
 	{ ST_CMD_SIZE, ST_RSP_SIZE(get_params_v1) },
-	{ ST_PRM_SIZE(set_params_v1), 0},
-	{ ST_PRM_SIZE(set_program), 0},
-	{ ST_PRM_SIZE(manual_suspend_ctrl), 0},
+	{ ST_PRM_SIZE(set_params_v1), 0 },
+	{ ST_PRM_SIZE(set_program), 0 },
+	{ ST_PRM_SIZE(manual_suspend_ctrl), 0 },
 	{ ST_CMD_SIZE, 0 },
 	{ ST_CMD_SIZE, 0 },
 	{ ST_CMD_SIZE, ST_RSP_SIZE(get_params_v2_timing) },
-	{ ST_PRM_SIZE(set_v2par_timing), 0},
+	{ ST_PRM_SIZE(set_v2par_timing), 0 },
 	{ ST_CMD_SIZE, ST_RSP_SIZE(get_params_v2_tap) },
-	{ ST_PRM_SIZE(set_v2par_tap), 0},
+	{ ST_PRM_SIZE(set_v2par_tap), 0 },
 	{ ST_CMD_SIZE, ST_RSP_SIZE(get_params_v2_osc) },
-	{ ST_PRM_SIZE(set_v2par_osc), 0},
+	{ ST_PRM_SIZE(set_v2par_osc), 0 },
 	{ ST_CMD_SIZE, ST_RSP_SIZE(get_params_v2_bright) },
-	{ ST_PRM_SIZE(set_v2par_bright), 0},
+	{ ST_PRM_SIZE(set_v2par_bright), 0 },
 	{ ST_CMD_SIZE, ST_RSP_SIZE(get_params_v2_thlds) },
-	{ ST_PRM_SIZE(set_v2par_thlds), 0},
+	{ ST_PRM_SIZE(set_v2par_thlds), 0 },
 	{ ST_CMD_SIZE, ST_RSP_SIZE(get_params_v2_colors) },
-	{ ST_PRM_SIZE(set_v2par_colors), 0},
+	{ ST_PRM_SIZE(set_v2par_colors), 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(lb_command_paramcount) == LIGHTBAR_NUM_CMDS);
 
@@ -4003,16 +4052,20 @@ static int lb_help(const char *cmd)
 	printf("  %s init                    - load default vals\n", cmd);
 	printf("  %s brightness [NUM]        - get/set intensity(0-ff)\n", cmd);
 	printf("  %s seq [NUM|SEQUENCE]      - run given pattern"
-		 " (no arg for list)\n", cmd);
+	       " (no arg for list)\n",
+	       cmd);
 	printf("  %s CTRL REG VAL            - set LED controller regs\n", cmd);
 	printf("  %s LED RED GREEN BLUE      - set color manually"
-		 " (LED=4 for all)\n", cmd);
+	       " (LED=4 for all)\n",
+	       cmd);
 	printf("  %s LED                     - get current LED color\n", cmd);
 	printf("  %s demo [0|1]              - turn demo mode on & off\n", cmd);
 	printf("  %s params [setfile]        - get params"
-	       " (or set from file)\n", cmd);
+	       " (or set from file)\n",
+	       cmd);
 	printf("  %s params2 group [setfile] - get params by group\n"
-	       " (or set from file)\n", cmd);
+	       " (or set from file)\n",
+	       cmd);
 	printf("  %s program file            - load program from file\n", cmd);
 	return 0;
 }
@@ -4027,15 +4080,14 @@ static uint8_t lb_find_msg_by_name(const char *str)
 	return LIGHTBAR_NUM_SEQUENCES;
 }
 
-static int lb_do_cmd(enum lightbar_command cmd,
-		     struct ec_params_lightbar *in,
+static int lb_do_cmd(enum lightbar_command cmd, struct ec_params_lightbar *in,
 		     struct ec_response_lightbar *out)
 {
 	int rv;
 	in->cmd = cmd;
-	rv = ec_command(EC_CMD_LIGHTBAR_CMD, 0,
-			in, lb_command_paramcount[cmd].insize,
-			out, lb_command_paramcount[cmd].outsize);
+	rv = ec_command(EC_CMD_LIGHTBAR_CMD, 0, in,
+			lb_command_paramcount[cmd].insize, out,
+			lb_command_paramcount[cmd].outsize);
 	return (rv < 0 ? rv : 0);
 }
 
@@ -4072,38 +4124,50 @@ static int lb_read_params_v0_from_file(const char *filename,
 
 	fp = fopen(filename, "rb");
 	if (!fp) {
-		fprintf(stderr, "Can't open %s: %s\n",
-			filename, strerror(errno));
+		fprintf(stderr, "Can't open %s: %s\n", filename,
+			strerror(errno));
 		return 1;
 	}
 
 	/* We must read the correct number of params from each line */
-#define READ(N) do {							\
-		line++;							\
-		want = (N);						\
-		got = -1;						\
-		if (!fgets(buf, sizeof(buf), fp))			\
-			goto done;					\
-		got = sscanf(buf, "%i %i %i %i",			\
-			     &val[0], &val[1], &val[2], &val[3]);	\
-		if (want != got)					\
-			goto done;					\
+#define READ(N)                                                             \
+	do {                                                                \
+		line++;                                                     \
+		want = (N);                                                 \
+		got = -1;                                                   \
+		if (!fgets(buf, sizeof(buf), fp))                           \
+			goto done;                                          \
+		got = sscanf(buf, "%i %i %i %i", &val[0], &val[1], &val[2], \
+			     &val[3]);                                      \
+		if (want != got)                                            \
+			goto done;                                          \
 	} while (0)
 
-
 	/* Do it */
-	READ(1); p->google_ramp_up = val[0];
-	READ(1); p->google_ramp_down = val[0];
-	READ(1); p->s3s0_ramp_up = val[0];
-	READ(1); p->s0_tick_delay[0] = val[0];
-	READ(1); p->s0_tick_delay[1] = val[0];
-	READ(1); p->s0a_tick_delay[0] = val[0];
-	READ(1); p->s0a_tick_delay[1] = val[0];
-	READ(1); p->s0s3_ramp_down = val[0];
-	READ(1); p->s3_sleep_for = val[0];
-	READ(1); p->s3_ramp_up = val[0];
-	READ(1); p->s3_ramp_down = val[0];
-	READ(1); p->new_s0 = val[0];
+	READ(1);
+	p->google_ramp_up = val[0];
+	READ(1);
+	p->google_ramp_down = val[0];
+	READ(1);
+	p->s3s0_ramp_up = val[0];
+	READ(1);
+	p->s0_tick_delay[0] = val[0];
+	READ(1);
+	p->s0_tick_delay[1] = val[0];
+	READ(1);
+	p->s0a_tick_delay[0] = val[0];
+	READ(1);
+	p->s0a_tick_delay[1] = val[0];
+	READ(1);
+	p->s0s3_ramp_down = val[0];
+	READ(1);
+	p->s3_sleep_for = val[0];
+	READ(1);
+	p->s3_ramp_up = val[0];
+	READ(1);
+	p->s3_ramp_down = val[0];
+	READ(1);
+	p->new_s0 = val[0];
 
 	READ(2);
 	p->osc_min[0] = val[0];
@@ -4191,39 +4255,30 @@ static void lb_show_params_v0(const struct lightbar_params_v0 *p)
 	printf("%d\t\t# .s3_ramp_up\n", p->s3_ramp_up);
 	printf("%d\t\t# .s3_ramp_down\n", p->s3_ramp_down);
 	printf("%d\t\t# .new_s0\n", p->new_s0);
-	printf("0x%02x 0x%02x\t# .osc_min (battery, AC)\n",
-	       p->osc_min[0], p->osc_min[1]);
-	printf("0x%02x 0x%02x\t# .osc_max (battery, AC)\n",
-	       p->osc_max[0], p->osc_max[1]);
-	printf("%d %d\t\t# .w_ofs (battery, AC)\n",
-	       p->w_ofs[0], p->w_ofs[1]);
+	printf("0x%02x 0x%02x\t# .osc_min (battery, AC)\n", p->osc_min[0],
+	       p->osc_min[1]);
+	printf("0x%02x 0x%02x\t# .osc_max (battery, AC)\n", p->osc_max[0],
+	       p->osc_max[1]);
+	printf("%d %d\t\t# .w_ofs (battery, AC)\n", p->w_ofs[0], p->w_ofs[1]);
 	printf("0x%02x 0x%02x\t# .bright_bl_off_fixed (battery, AC)\n",
 	       p->bright_bl_off_fixed[0], p->bright_bl_off_fixed[1]);
 	printf("0x%02x 0x%02x\t# .bright_bl_on_min (battery, AC)\n",
 	       p->bright_bl_on_min[0], p->bright_bl_on_min[1]);
 	printf("0x%02x 0x%02x\t# .bright_bl_on_max (battery, AC)\n",
 	       p->bright_bl_on_max[0], p->bright_bl_on_max[1]);
-	printf("%d %d %d\t\t# .battery_threshold\n",
-	       p->battery_threshold[0],
-	       p->battery_threshold[1],
-	       p->battery_threshold[2]);
-	printf("%d %d %d %d\t\t# .s0_idx[] (battery)\n",
-	       p->s0_idx[0][0], p->s0_idx[0][1],
-	       p->s0_idx[0][2], p->s0_idx[0][3]);
-	printf("%d %d %d %d\t\t# .s0_idx[] (AC)\n",
-	       p->s0_idx[1][0], p->s0_idx[1][1],
-	       p->s0_idx[1][2], p->s0_idx[1][3]);
-	printf("%d %d %d %d\t# .s3_idx[] (battery)\n",
-	       p->s3_idx[0][0], p->s3_idx[0][1],
-	       p->s3_idx[0][2], p->s3_idx[0][3]);
-	printf("%d %d %d %d\t# .s3_idx[] (AC)\n",
-	       p->s3_idx[1][0], p->s3_idx[1][1],
-	       p->s3_idx[1][2], p->s3_idx[1][3]);
+	printf("%d %d %d\t\t# .battery_threshold\n", p->battery_threshold[0],
+	       p->battery_threshold[1], p->battery_threshold[2]);
+	printf("%d %d %d %d\t\t# .s0_idx[] (battery)\n", p->s0_idx[0][0],
+	       p->s0_idx[0][1], p->s0_idx[0][2], p->s0_idx[0][3]);
+	printf("%d %d %d %d\t\t# .s0_idx[] (AC)\n", p->s0_idx[1][0],
+	       p->s0_idx[1][1], p->s0_idx[1][2], p->s0_idx[1][3]);
+	printf("%d %d %d %d\t# .s3_idx[] (battery)\n", p->s3_idx[0][0],
+	       p->s3_idx[0][1], p->s3_idx[0][2], p->s3_idx[0][3]);
+	printf("%d %d %d %d\t# .s3_idx[] (AC)\n", p->s3_idx[1][0],
+	       p->s3_idx[1][1], p->s3_idx[1][2], p->s3_idx[1][3]);
 	for (i = 0; i < ARRAY_SIZE(p->color); i++)
-		printf("0x%02x 0x%02x 0x%02x\t# color[%d]\n",
-		       p->color[i].r,
-		       p->color[i].g,
-		       p->color[i].b, i);
+		printf("0x%02x 0x%02x 0x%02x\t# color[%d]\n", p->color[i].r,
+		       p->color[i].g, p->color[i].b, i);
 }
 
 static int lb_read_params_v1_from_file(const char *filename,
@@ -4239,46 +4294,65 @@ static int lb_read_params_v1_from_file(const char *filename,
 
 	fp = fopen(filename, "rb");
 	if (!fp) {
-		fprintf(stderr, "Can't open %s: %s\n",
-			filename, strerror(errno));
+		fprintf(stderr, "Can't open %s: %s\n", filename,
+			strerror(errno));
 		return 1;
 	}
 
 	/* We must read the correct number of params from each line */
-#define READ(N) do {							\
-		line++;							\
-		want = (N);						\
-		got = -1;						\
-		if (!fgets(buf, sizeof(buf), fp))			\
-			goto done;					\
-		got = sscanf(buf, "%i %i %i %i",			\
-			     &val[0], &val[1], &val[2], &val[3]);	\
-		if (want != got)					\
-			goto done;					\
+#define READ(N)                                                             \
+	do {                                                                \
+		line++;                                                     \
+		want = (N);                                                 \
+		got = -1;                                                   \
+		if (!fgets(buf, sizeof(buf), fp))                           \
+			goto done;                                          \
+		got = sscanf(buf, "%i %i %i %i", &val[0], &val[1], &val[2], \
+			     &val[3]);                                      \
+		if (want != got)                                            \
+			goto done;                                          \
 	} while (0)
 
-
 	/* Do it */
-	READ(1); p->google_ramp_up = val[0];
-	READ(1); p->google_ramp_down = val[0];
-	READ(1); p->s3s0_ramp_up = val[0];
-	READ(1); p->s0_tick_delay[0] = val[0];
-	READ(1); p->s0_tick_delay[1] = val[0];
-	READ(1); p->s0a_tick_delay[0] = val[0];
-	READ(1); p->s0a_tick_delay[1] = val[0];
-	READ(1); p->s0s3_ramp_down = val[0];
-	READ(1); p->s3_sleep_for = val[0];
-	READ(1); p->s3_ramp_up = val[0];
-	READ(1); p->s3_ramp_down = val[0];
-	READ(1); p->tap_tick_delay = val[0];
-	READ(1); p->tap_gate_delay = val[0];
-	READ(1); p->tap_display_time = val[0];
-
-	READ(1); p->tap_pct_red = val[0];
-	READ(1); p->tap_pct_green = val[0];
-	READ(1); p->tap_seg_min_on = val[0];
-	READ(1); p->tap_seg_max_on = val[0];
-	READ(1); p->tap_seg_osc = val[0];
+	READ(1);
+	p->google_ramp_up = val[0];
+	READ(1);
+	p->google_ramp_down = val[0];
+	READ(1);
+	p->s3s0_ramp_up = val[0];
+	READ(1);
+	p->s0_tick_delay[0] = val[0];
+	READ(1);
+	p->s0_tick_delay[1] = val[0];
+	READ(1);
+	p->s0a_tick_delay[0] = val[0];
+	READ(1);
+	p->s0a_tick_delay[1] = val[0];
+	READ(1);
+	p->s0s3_ramp_down = val[0];
+	READ(1);
+	p->s3_sleep_for = val[0];
+	READ(1);
+	p->s3_ramp_up = val[0];
+	READ(1);
+	p->s3_ramp_down = val[0];
+	READ(1);
+	p->tap_tick_delay = val[0];
+	READ(1);
+	p->tap_gate_delay = val[0];
+	READ(1);
+	p->tap_display_time = val[0];
+
+	READ(1);
+	p->tap_pct_red = val[0];
+	READ(1);
+	p->tap_pct_green = val[0];
+	READ(1);
+	p->tap_seg_min_on = val[0];
+	READ(1);
+	p->tap_seg_max_on = val[0];
+	READ(1);
+	p->tap_seg_osc = val[0];
 	READ(3);
 	p->tap_idx[0] = val[0];
 	p->tap_idx[1] = val[1];
@@ -4377,41 +4451,32 @@ static void lb_show_params_v1(const struct lightbar_params_v1 *p)
 	printf("%d\t\t# .tap_seg_min_on\n", p->tap_seg_min_on);
 	printf("%d\t\t# .tap_seg_max_on\n", p->tap_seg_max_on);
 	printf("%d\t\t# .tap_seg_osc\n", p->tap_seg_osc);
-	printf("%d %d %d\t\t# .tap_idx\n",
-	       p->tap_idx[0], p->tap_idx[1], p->tap_idx[2]);
-	printf("0x%02x 0x%02x\t# .osc_min (battery, AC)\n",
-	       p->osc_min[0], p->osc_min[1]);
-	printf("0x%02x 0x%02x\t# .osc_max (battery, AC)\n",
-	       p->osc_max[0], p->osc_max[1]);
-	printf("%d %d\t\t# .w_ofs (battery, AC)\n",
-	       p->w_ofs[0], p->w_ofs[1]);
+	printf("%d %d %d\t\t# .tap_idx\n", p->tap_idx[0], p->tap_idx[1],
+	       p->tap_idx[2]);
+	printf("0x%02x 0x%02x\t# .osc_min (battery, AC)\n", p->osc_min[0],
+	       p->osc_min[1]);
+	printf("0x%02x 0x%02x\t# .osc_max (battery, AC)\n", p->osc_max[0],
+	       p->osc_max[1]);
+	printf("%d %d\t\t# .w_ofs (battery, AC)\n", p->w_ofs[0], p->w_ofs[1]);
 	printf("0x%02x 0x%02x\t# .bright_bl_off_fixed (battery, AC)\n",
 	       p->bright_bl_off_fixed[0], p->bright_bl_off_fixed[1]);
 	printf("0x%02x 0x%02x\t# .bright_bl_on_min (battery, AC)\n",
 	       p->bright_bl_on_min[0], p->bright_bl_on_min[1]);
 	printf("0x%02x 0x%02x\t# .bright_bl_on_max (battery, AC)\n",
 	       p->bright_bl_on_max[0], p->bright_bl_on_max[1]);
-	printf("%d %d %d\t# .battery_threshold\n",
-	       p->battery_threshold[0],
-	       p->battery_threshold[1],
-	       p->battery_threshold[2]);
-	printf("%d %d %d %d\t\t# .s0_idx[] (battery)\n",
-	       p->s0_idx[0][0], p->s0_idx[0][1],
-	       p->s0_idx[0][2], p->s0_idx[0][3]);
-	printf("%d %d %d %d\t\t# .s0_idx[] (AC)\n",
-	       p->s0_idx[1][0], p->s0_idx[1][1],
-	       p->s0_idx[1][2], p->s0_idx[1][3]);
-	printf("%d %d %d %d\t# .s3_idx[] (battery)\n",
-	       p->s3_idx[0][0], p->s3_idx[0][1],
-	       p->s3_idx[0][2], p->s3_idx[0][3]);
-	printf("%d %d %d %d\t# .s3_idx[] (AC)\n",
-	       p->s3_idx[1][0], p->s3_idx[1][1],
-	       p->s3_idx[1][2], p->s3_idx[1][3]);
+	printf("%d %d %d\t# .battery_threshold\n", p->battery_threshold[0],
+	       p->battery_threshold[1], p->battery_threshold[2]);
+	printf("%d %d %d %d\t\t# .s0_idx[] (battery)\n", p->s0_idx[0][0],
+	       p->s0_idx[0][1], p->s0_idx[0][2], p->s0_idx[0][3]);
+	printf("%d %d %d %d\t\t# .s0_idx[] (AC)\n", p->s0_idx[1][0],
+	       p->s0_idx[1][1], p->s0_idx[1][2], p->s0_idx[1][3]);
+	printf("%d %d %d %d\t# .s3_idx[] (battery)\n", p->s3_idx[0][0],
+	       p->s3_idx[0][1], p->s3_idx[0][2], p->s3_idx[0][3]);
+	printf("%d %d %d %d\t# .s3_idx[] (AC)\n", p->s3_idx[1][0],
+	       p->s3_idx[1][1], p->s3_idx[1][2], p->s3_idx[1][3]);
 	for (i = 0; i < ARRAY_SIZE(p->color); i++)
-		printf("0x%02x 0x%02x 0x%02x\t# color[%d]\n",
-		       p->color[i].r,
-		       p->color[i].g,
-		       p->color[i].b, i);
+		printf("0x%02x 0x%02x 0x%02x\t# color[%d]\n", p->color[i].r,
+		       p->color[i].g, p->color[i].b, i);
 }
 
 static int lb_rd_timing_v2par_from_file(const char *filename,
@@ -4426,38 +4491,53 @@ static int lb_rd_timing_v2par_from_file(const char *filename,
 
 	fp = fopen(filename, "rb");
 	if (!fp) {
-		fprintf(stderr, "Can't open %s: %s\n",
-			filename, strerror(errno));
+		fprintf(stderr, "Can't open %s: %s\n", filename,
+			strerror(errno));
 		return 1;
 	}
 
 	/* We must read the correct number of params from each line */
-#define READ(N) do {							\
-		line++;							\
-		want = (N);						\
-		got = -1;						\
-		if (!fgets(buf, sizeof(buf), fp))			\
-			goto done;					\
-		got = sscanf(buf, "%i %i %i %i",			\
-			     &val[0], &val[1], &val[2], &val[3]);	\
-		if (want != got)					\
-			goto done;					\
+#define READ(N)                                                             \
+	do {                                                                \
+		line++;                                                     \
+		want = (N);                                                 \
+		got = -1;                                                   \
+		if (!fgets(buf, sizeof(buf), fp))                           \
+			goto done;                                          \
+		got = sscanf(buf, "%i %i %i %i", &val[0], &val[1], &val[2], \
+			     &val[3]);                                      \
+		if (want != got)                                            \
+			goto done;                                          \
 	} while (0)
 
-	READ(1); p->google_ramp_up = val[0];
-	READ(1); p->google_ramp_down = val[0];
-	READ(1); p->s3s0_ramp_up = val[0];
-	READ(1); p->s0_tick_delay[0] = val[0];
-	READ(1); p->s0_tick_delay[1] = val[0];
-	READ(1); p->s0a_tick_delay[0] = val[0];
-	READ(1); p->s0a_tick_delay[1] = val[0];
-	READ(1); p->s0s3_ramp_down = val[0];
-	READ(1); p->s3_sleep_for = val[0];
-	READ(1); p->s3_ramp_up = val[0];
-	READ(1); p->s3_ramp_down = val[0];
-	READ(1); p->tap_tick_delay = val[0];
-	READ(1); p->tap_gate_delay = val[0];
-	READ(1); p->tap_display_time = val[0];
+	READ(1);
+	p->google_ramp_up = val[0];
+	READ(1);
+	p->google_ramp_down = val[0];
+	READ(1);
+	p->s3s0_ramp_up = val[0];
+	READ(1);
+	p->s0_tick_delay[0] = val[0];
+	READ(1);
+	p->s0_tick_delay[1] = val[0];
+	READ(1);
+	p->s0a_tick_delay[0] = val[0];
+	READ(1);
+	p->s0a_tick_delay[1] = val[0];
+	READ(1);
+	p->s0s3_ramp_down = val[0];
+	READ(1);
+	p->s3_sleep_for = val[0];
+	READ(1);
+	p->s3_ramp_up = val[0];
+	READ(1);
+	p->s3_ramp_down = val[0];
+	READ(1);
+	p->tap_tick_delay = val[0];
+	READ(1);
+	p->tap_gate_delay = val[0];
+	READ(1);
+	p->tap_display_time = val[0];
 #undef READ
 
 	/* Yay */
@@ -4482,29 +4562,35 @@ static int lb_rd_tap_v2par_from_file(const char *filename,
 
 	fp = fopen(filename, "rb");
 	if (!fp) {
-		fprintf(stderr, "Can't open %s: %s\n",
-			filename, strerror(errno));
+		fprintf(stderr, "Can't open %s: %s\n", filename,
+			strerror(errno));
 		return 1;
 	}
 
 	/* We must read the correct number of params from each line */
-#define READ(N) do {							\
-		line++;							\
-		want = (N);						\
-		got = -1;						\
-		if (!fgets(buf, sizeof(buf), fp))			\
-			goto done;					\
-		got = sscanf(buf, "%i %i %i %i",			\
-			     &val[0], &val[1], &val[2], &val[3]);	\
-		if (want != got)					\
-			goto done;					\
+#define READ(N)                                                             \
+	do {                                                                \
+		line++;                                                     \
+		want = (N);                                                 \
+		got = -1;                                                   \
+		if (!fgets(buf, sizeof(buf), fp))                           \
+			goto done;                                          \
+		got = sscanf(buf, "%i %i %i %i", &val[0], &val[1], &val[2], \
+			     &val[3]);                                      \
+		if (want != got)                                            \
+			goto done;                                          \
 	} while (0)
 
-	READ(1); p->tap_pct_red = val[0];
-	READ(1); p->tap_pct_green = val[0];
-	READ(1); p->tap_seg_min_on = val[0];
-	READ(1); p->tap_seg_max_on = val[0];
-	READ(1); p->tap_seg_osc = val[0];
+	READ(1);
+	p->tap_pct_red = val[0];
+	READ(1);
+	p->tap_pct_green = val[0];
+	READ(1);
+	p->tap_seg_min_on = val[0];
+	READ(1);
+	p->tap_seg_max_on = val[0];
+	READ(1);
+	p->tap_seg_osc = val[0];
 	READ(3);
 	p->tap_idx[0] = val[0];
 	p->tap_idx[1] = val[1];
@@ -4533,22 +4619,23 @@ static int lb_rd_osc_v2par_from_file(const char *filename,
 
 	fp = fopen(filename, "rb");
 	if (!fp) {
-		fprintf(stderr, "Can't open %s: %s\n",
-			filename, strerror(errno));
+		fprintf(stderr, "Can't open %s: %s\n", filename,
+			strerror(errno));
 		return 1;
 	}
 
 	/* We must read the correct number of params from each line */
-#define READ(N) do {							\
-		line++;							\
-		want = (N);						\
-		got = -1;						\
-		if (!fgets(buf, sizeof(buf), fp))			\
-			goto done;					\
-		got = sscanf(buf, "%i %i %i %i",			\
-			     &val[0], &val[1], &val[2], &val[3]);	\
-		if (want != got)					\
-			goto done;					\
+#define READ(N)                                                             \
+	do {                                                                \
+		line++;                                                     \
+		want = (N);                                                 \
+		got = -1;                                                   \
+		if (!fgets(buf, sizeof(buf), fp))                           \
+			goto done;                                          \
+		got = sscanf(buf, "%i %i %i %i", &val[0], &val[1], &val[2], \
+			     &val[3]);                                      \
+		if (want != got)                                            \
+			goto done;                                          \
 	} while (0)
 
 	READ(2);
@@ -4584,22 +4671,23 @@ static int lb_rd_bright_v2par_from_file(const char *filename,
 
 	fp = fopen(filename, "rb");
 	if (!fp) {
-		fprintf(stderr, "Can't open %s: %s\n",
-			filename, strerror(errno));
+		fprintf(stderr, "Can't open %s: %s\n", filename,
+			strerror(errno));
 		return 1;
 	}
 
 	/* We must read the correct number of params from each line */
-#define READ(N) do {							\
-		line++;							\
-		want = (N);						\
-		got = -1;						\
-		if (!fgets(buf, sizeof(buf), fp))			\
-			goto done;					\
-		got = sscanf(buf, "%i %i %i %i",			\
-			     &val[0], &val[1], &val[2], &val[3]);	\
-		if (want != got)					\
-			goto done;					\
+#define READ(N)                                                             \
+	do {                                                                \
+		line++;                                                     \
+		want = (N);                                                 \
+		got = -1;                                                   \
+		if (!fgets(buf, sizeof(buf), fp))                           \
+			goto done;                                          \
+		got = sscanf(buf, "%i %i %i %i", &val[0], &val[1], &val[2], \
+			     &val[3]);                                      \
+		if (want != got)                                            \
+			goto done;                                          \
 	} while (0)
 
 	READ(2);
@@ -4637,22 +4725,23 @@ static int lb_rd_thlds_v2par_from_file(const char *filename,
 
 	fp = fopen(filename, "rb");
 	if (!fp) {
-		fprintf(stderr, "Can't open %s: %s\n",
-			filename, strerror(errno));
+		fprintf(stderr, "Can't open %s: %s\n", filename,
+			strerror(errno));
 		return 1;
 	}
 
 	/* We must read the correct number of params from each line */
-#define READ(N) do {							\
-		line++;							\
-		want = (N);						\
-		got = -1;						\
-		if (!fgets(buf, sizeof(buf), fp))			\
-			goto done;					\
-		got = sscanf(buf, "%i %i %i %i",			\
-			     &val[0], &val[1], &val[2], &val[3]);	\
-		if (want != got)					\
-			goto done;					\
+#define READ(N)                                                             \
+	do {                                                                \
+		line++;                                                     \
+		want = (N);                                                 \
+		got = -1;                                                   \
+		if (!fgets(buf, sizeof(buf), fp))                           \
+			goto done;                                          \
+		got = sscanf(buf, "%i %i %i %i", &val[0], &val[1], &val[2], \
+			     &val[3]);                                      \
+		if (want != got)                                            \
+			goto done;                                          \
 	} while (0)
 
 	READ(3);
@@ -4684,22 +4773,23 @@ static int lb_rd_colors_v2par_from_file(const char *filename,
 
 	fp = fopen(filename, "rb");
 	if (!fp) {
-		fprintf(stderr, "Can't open %s: %s\n",
-			filename, strerror(errno));
+		fprintf(stderr, "Can't open %s: %s\n", filename,
+			strerror(errno));
 		return 1;
 	}
 
 	/* We must read the correct number of params from each line */
-#define READ(N) do {							\
-		line++;							\
-		want = (N);						\
-		got = -1;						\
-		if (!fgets(buf, sizeof(buf), fp))			\
-			goto done;					\
-		got = sscanf(buf, "%i %i %i %i",			\
-			     &val[0], &val[1], &val[2], &val[3]);	\
-		if (want != got)					\
-			goto done;					\
+#define READ(N)                                                             \
+	do {                                                                \
+		line++;                                                     \
+		want = (N);                                                 \
+		got = -1;                                                   \
+		if (!fgets(buf, sizeof(buf), fp))                           \
+			goto done;                                          \
+		got = sscanf(buf, "%i %i %i %i", &val[0], &val[1], &val[2], \
+			     &val[3]);                                      \
+		if (want != got)                                            \
+			goto done;                                          \
 	} while (0)
 
 	READ(4);
@@ -4769,18 +4859,17 @@ static void lb_show_v2par_tap(const struct lightbar_params_v2_tap *p)
 	printf("%d\t\t# .tap_seg_min_on\n", p->tap_seg_min_on);
 	printf("%d\t\t# .tap_seg_max_on\n", p->tap_seg_max_on);
 	printf("%d\t\t# .tap_seg_osc\n", p->tap_seg_osc);
-	printf("%d %d %d\t\t# .tap_idx\n",
-	       p->tap_idx[0], p->tap_idx[1], p->tap_idx[2]);
+	printf("%d %d %d\t\t# .tap_idx\n", p->tap_idx[0], p->tap_idx[1],
+	       p->tap_idx[2]);
 }
 
 static void lb_show_v2par_osc(const struct lightbar_params_v2_oscillation *p)
 {
-	printf("0x%02x 0x%02x\t# .osc_min (battery, AC)\n",
-	       p->osc_min[0], p->osc_min[1]);
-	printf("0x%02x 0x%02x\t# .osc_max (battery, AC)\n",
-	       p->osc_max[0], p->osc_max[1]);
-	printf("%d %d\t\t# .w_ofs (battery, AC)\n",
-	       p->w_ofs[0], p->w_ofs[1]);
+	printf("0x%02x 0x%02x\t# .osc_min (battery, AC)\n", p->osc_min[0],
+	       p->osc_min[1]);
+	printf("0x%02x 0x%02x\t# .osc_max (battery, AC)\n", p->osc_max[0],
+	       p->osc_max[1]);
+	printf("%d %d\t\t# .w_ofs (battery, AC)\n", p->w_ofs[0], p->w_ofs[1]);
 }
 
 static void lb_show_v2par_bright(const struct lightbar_params_v2_brightness *p)
@@ -4795,34 +4884,26 @@ static void lb_show_v2par_bright(const struct lightbar_params_v2_brightness *p)
 
 static void lb_show_v2par_thlds(const struct lightbar_params_v2_thresholds *p)
 {
-	printf("%d %d %d\t# .battery_threshold\n",
-	       p->battery_threshold[0],
-	       p->battery_threshold[1],
-	       p->battery_threshold[2]);
+	printf("%d %d %d\t# .battery_threshold\n", p->battery_threshold[0],
+	       p->battery_threshold[1], p->battery_threshold[2]);
 }
 
 static void lb_show_v2par_colors(const struct lightbar_params_v2_colors *p)
 {
 	int i;
 
-	printf("%d %d %d %d\t\t# .s0_idx[] (battery)\n",
-	       p->s0_idx[0][0], p->s0_idx[0][1],
-	       p->s0_idx[0][2], p->s0_idx[0][3]);
-	printf("%d %d %d %d\t\t# .s0_idx[] (AC)\n",
-	       p->s0_idx[1][0], p->s0_idx[1][1],
-	       p->s0_idx[1][2], p->s0_idx[1][3]);
-	printf("%d %d %d %d\t# .s3_idx[] (battery)\n",
-	       p->s3_idx[0][0], p->s3_idx[0][1],
-	       p->s3_idx[0][2], p->s3_idx[0][3]);
-	printf("%d %d %d %d\t# .s3_idx[] (AC)\n",
-	       p->s3_idx[1][0], p->s3_idx[1][1],
-	       p->s3_idx[1][2], p->s3_idx[1][3]);
+	printf("%d %d %d %d\t\t# .s0_idx[] (battery)\n", p->s0_idx[0][0],
+	       p->s0_idx[0][1], p->s0_idx[0][2], p->s0_idx[0][3]);
+	printf("%d %d %d %d\t\t# .s0_idx[] (AC)\n", p->s0_idx[1][0],
+	       p->s0_idx[1][1], p->s0_idx[1][2], p->s0_idx[1][3]);
+	printf("%d %d %d %d\t# .s3_idx[] (battery)\n", p->s3_idx[0][0],
+	       p->s3_idx[0][1], p->s3_idx[0][2], p->s3_idx[0][3]);
+	printf("%d %d %d %d\t# .s3_idx[] (AC)\n", p->s3_idx[1][0],
+	       p->s3_idx[1][1], p->s3_idx[1][2], p->s3_idx[1][3]);
 
 	for (i = 0; i < ARRAY_SIZE(p->color); i++)
-		printf("0x%02x 0x%02x 0x%02x\t# color[%d]\n",
-		       p->color[i].r,
-		       p->color[i].g,
-		       p->color[i].b, i);
+		printf("0x%02x 0x%02x 0x%02x\t# color[%d]\n", p->color[i].r,
+		       p->color[i].g, p->color[i].b, i);
 }
 
 static int lb_load_program(const char *filename, struct lightbar_program *prog)
@@ -4833,19 +4914,18 @@ static int lb_load_program(const char *filename, struct lightbar_program *prog)
 
 	fp = fopen(filename, "rb");
 	if (!fp) {
-		fprintf(stderr, "Can't open %s: %s\n",
-			filename, strerror(errno));
+		fprintf(stderr, "Can't open %s: %s\n", filename,
+			strerror(errno));
 		return 1;
 	}
 
 	rc = fseek(fp, 0, SEEK_END);
 	if (rc) {
-		fprintf(stderr, "Couldn't find end of file %s",
-				filename);
+		fprintf(stderr, "Couldn't find end of file %s", filename);
 		fclose(fp);
 		return 1;
 	}
-	rc = (int) ftell(fp);
+	rc = (int)ftell(fp);
 	if (rc > EC_LB_PROG_LEN) {
 		fprintf(stderr, "File %s is too long, aborting\n", filename);
 		fclose(fp);
@@ -4869,12 +4949,10 @@ static int cmd_lightbar_params_v0(int argc, char **argv)
 	int r;
 
 	if (argc > 2) {
-		r = lb_read_params_v0_from_file(argv[2],
-						&param.set_params_v0);
+		r = lb_read_params_v0_from_file(argv[2], &param.set_params_v0);
 		if (r)
 			return r;
-		return lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V0,
-				 &param, &resp);
+		return lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V0, &param, &resp);
 	}
 	r = lb_do_cmd(LIGHTBAR_CMD_GET_PARAMS_V0, &param, &resp);
 	if (!r)
@@ -4889,12 +4967,10 @@ static int cmd_lightbar_params_v1(int argc, char **argv)
 	int r;
 
 	if (argc > 2) {
-		r = lb_read_params_v1_from_file(argv[2],
-						&param.set_params_v1);
+		r = lb_read_params_v1_from_file(argv[2], &param.set_params_v1);
 		if (r)
 			return r;
-		return lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V1,
-				 &param, &resp);
+		return lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V1, &param, &resp);
 	}
 	r = lb_do_cmd(LIGHTBAR_CMD_GET_PARAMS_V1, &param, &resp);
 	if (!r)
@@ -4943,8 +5019,8 @@ static int cmd_lightbar_params_v2(int argc, char **argv)
 							 &p.set_v2par_timing);
 			if (r)
 				return r;
-			r = lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V2_TIMING,
-				      &p, &resp);
+			r = lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V2_TIMING, &p,
+				      &resp);
 			if (r)
 				return r;
 		}
@@ -4958,8 +5034,8 @@ static int cmd_lightbar_params_v2(int argc, char **argv)
 						      &p.set_v2par_tap);
 			if (r)
 				return r;
-			r = lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V2_TAP,
-				      &p, &resp);
+			r = lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V2_TAP, &p,
+				      &resp);
 			if (r)
 				return r;
 		}
@@ -4989,13 +5065,12 @@ static int cmd_lightbar_params_v2(int argc, char **argv)
 							 &p.set_v2par_bright);
 			if (r)
 				return r;
-			r = lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V2_BRIGHTNESS,
-				      &p, &resp);
+			r = lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V2_BRIGHTNESS, &p,
+				      &resp);
 			if (r)
 				return r;
 		}
-		r = lb_do_cmd(LIGHTBAR_CMD_GET_PARAMS_V2_BRIGHTNESS, &p,
-			      &resp);
+		r = lb_do_cmd(LIGHTBAR_CMD_GET_PARAMS_V2_BRIGHTNESS, &p, &resp);
 		if (r)
 			return r;
 		lb_show_v2par_bright(&resp.get_params_v2_bright);
@@ -5005,13 +5080,12 @@ static int cmd_lightbar_params_v2(int argc, char **argv)
 							&p.set_v2par_thlds);
 			if (r)
 				return r;
-			r = lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V2_THRESHOLDS,
-				      &p, &resp);
+			r = lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V2_THRESHOLDS, &p,
+				      &resp);
 			if (r)
 				return r;
 		}
-		r = lb_do_cmd(LIGHTBAR_CMD_GET_PARAMS_V2_THRESHOLDS, &p,
-			      &resp);
+		r = lb_do_cmd(LIGHTBAR_CMD_GET_PARAMS_V2_THRESHOLDS, &p, &resp);
 		if (r)
 			return r;
 		lb_show_v2par_thlds(&resp.get_params_v2_thlds);
@@ -5021,8 +5095,8 @@ static int cmd_lightbar_params_v2(int argc, char **argv)
 							 &p.set_v2par_colors);
 			if (r)
 				return r;
-			r = lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V2_COLORS,
-				      &p, &resp);
+			r = lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V2_COLORS, &p,
+				      &resp);
 			if (r)
 				return r;
 		}
@@ -5043,14 +5117,13 @@ static int cmd_lightbar(int argc, char **argv)
 	struct ec_params_lightbar param;
 	struct ec_response_lightbar resp;
 
-	if (1 == argc) {		/* no args = dump 'em all */
+	if (1 == argc) { /* no args = dump 'em all */
 		r = lb_do_cmd(LIGHTBAR_CMD_DUMP, &param, &resp);
 		if (r)
 			return r;
 		for (i = 0; i < ARRAY_SIZE(resp.dump.vals); i++) {
 			printf(" %02x     %02x     %02x\n",
-			       resp.dump.vals[i].reg,
-			       resp.dump.vals[i].ic0,
+			       resp.dump.vals[i].reg, resp.dump.vals[i].ic0,
 			       resp.dump.vals[i].ic1);
 		}
 		return 0;
@@ -5086,8 +5159,8 @@ static int cmd_lightbar(int argc, char **argv)
 	if (!strcasecmp(argv[1], "version")) {
 		r = lb_do_cmd(LIGHTBAR_CMD_VERSION, &param, &resp);
 		if (!r)
-			printf("version %d flags 0x%x\n",
-			       resp.version.num, resp.version.flags);
+			printf("version %d flags 0x%x\n", resp.version.num,
+			       resp.version.flags);
 		return r;
 	}
 
@@ -5096,12 +5169,11 @@ static int cmd_lightbar(int argc, char **argv)
 		int rv;
 		if (argc > 2) {
 			param.set_brightness.num = 0xff &
-				strtoull(argv[2], &e, 16);
-			return lb_do_cmd(LIGHTBAR_CMD_SET_BRIGHTNESS,
-					 &param, &resp);
+						   strtoull(argv[2], &e, 16);
+			return lb_do_cmd(LIGHTBAR_CMD_SET_BRIGHTNESS, &param,
+					 &resp);
 		}
-		rv = lb_do_cmd(LIGHTBAR_CMD_GET_BRIGHTNESS,
-			       &param, &resp);
+		rv = lb_do_cmd(LIGHTBAR_CMD_GET_BRIGHTNESS, &param, &resp);
 		if (rv)
 			return rv;
 		printf("%02x\n", resp.get_brightness.num);
@@ -5176,10 +5248,8 @@ static int cmd_lightbar(int argc, char **argv)
 			r = lb_do_cmd(LIGHTBAR_CMD_GET_RGB, &param, &resp);
 			if (r)
 				return r;
-			printf("%02x %02x %02x\n",
-			       resp.get_rgb.red,
-			       resp.get_rgb.green,
-			       resp.get_rgb.blue);
+			printf("%02x %02x %02x\n", resp.get_rgb.red,
+			       resp.get_rgb.green, resp.get_rgb.blue);
 			return 0;
 		}
 	}
@@ -5192,7 +5262,10 @@ static int cmd_lightbar(int argc, char **argv)
 #define ST_PRM_SIZE(SUBCMD) \
 	(ST_CMD_SIZE + ST_FLD_SIZE(ec_params_motion_sense, SUBCMD))
 #define ST_RSP_SIZE(SUBCMD) ST_FLD_SIZE(ec_response_motion_sense, SUBCMD)
-#define ST_BOTH_SIZES(SUBCMD) { ST_PRM_SIZE(SUBCMD), ST_RSP_SIZE(SUBCMD) }
+#define ST_BOTH_SIZES(SUBCMD)                            \
+	{                                                \
+		ST_PRM_SIZE(SUBCMD), ST_RSP_SIZE(SUBCMD) \
+	}
 
 /*
  * For ectool only, assume no more than 16 sensors.  More advanced
@@ -5205,22 +5278,17 @@ static const struct {
 	uint8_t outsize;
 	uint8_t insize;
 } ms_command_sizes[] = {
-	{
-		ST_PRM_SIZE(dump),
-		ST_RSP_SIZE(dump) +
-		sizeof(struct ec_response_motion_sensor_data) *
-		ECTOOL_MAX_SENSOR
-	},
+	{ ST_PRM_SIZE(dump),
+	  ST_RSP_SIZE(dump) + sizeof(struct ec_response_motion_sensor_data) *
+				      ECTOOL_MAX_SENSOR },
 	ST_BOTH_SIZES(info_4),
 	ST_BOTH_SIZES(ec_rate),
 	ST_BOTH_SIZES(sensor_odr),
 	ST_BOTH_SIZES(sensor_range),
 	ST_BOTH_SIZES(kb_wake_angle),
 	ST_BOTH_SIZES(data),
-	{
-		ST_CMD_SIZE,
-		ST_RSP_SIZE(fifo_info) + sizeof(uint16_t) * ECTOOL_MAX_SENSOR
-	},
+	{ ST_CMD_SIZE,
+	  ST_RSP_SIZE(fifo_info) + sizeof(uint16_t) * ECTOOL_MAX_SENSOR },
 	ST_BOTH_SIZES(fifo_flush),
 	ST_BOTH_SIZES(fifo_read),
 	ST_BOTH_SIZES(perform_calib),
@@ -5246,40 +5314,43 @@ static int ms_help(const char *cmd)
 {
 	printf("Usage:\n");
 	printf("  %s                              - dump all motion data\n",
-		cmd);
+	       cmd);
 	printf("  %s active                       - print active flag\n", cmd);
 	printf("  %s info NUM                     - print sensor info\n", cmd);
 	printf("  %s ec_rate NUM [RATE_MS]        - set/get sample rate\n",
-		cmd);
-	printf("  %s odr NUM [ODR [ROUNDUP]]      - set/get sensor ODR\n",
-		cmd);
+	       cmd);
+	printf("  %s odr NUM [ODR [ROUNDUP]]      - set/get sensor ODR\n", cmd);
 	printf("  %s range NUM [RANGE [ROUNDUP]]  - set/get sensor range\n",
-		cmd);
+	       cmd);
 	printf("  %s offset NUM [-- X Y Z [TEMP]] - set/get sensor offset\n",
-		cmd);
+	       cmd);
 	printf("  %s kb_wake NUM                  - set/get KB wake ang\n",
-		cmd);
+	       cmd);
 	printf("  %s fifo_info                    - print fifo info\n", cmd);
 	printf("  %s fifo_int_enable [0/1]        - enable/disable/get fifo "
-		"interrupt status\n", cmd);
+	       "interrupt status\n",
+	       cmd);
 	printf("  %s fifo_read MAX_DATA           - read fifo data\n", cmd);
 	printf("  %s fifo_flush NUM               - trigger fifo interrupt\n",
-		cmd);
+	       cmd);
 	printf("  %s list_activities              - list supported "
-		"activities\n", cmd);
+	       "activities\n",
+	       cmd);
 	printf("  %s set_activity ACT EN          - enable/disable activity\n",
-		cmd);
+	       cmd);
 	printf("  %s get_activity ACT             - get activity status\n",
-		cmd);
+	       cmd);
 	printf("  %s lid_angle                    - print lid angle\n", cmd);
 	printf("  %s spoof -- NUM [0/1] [X Y Z]   - enable/disable spoofing\n",
-		cmd);
+	       cmd);
 	printf("  %s spoof -- NUM activity ACT [0/1] [STATE] - enable/disable "
-		"activity spoofing\n", cmd);
+	       "activity spoofing\n",
+	       cmd);
 	printf("  %s tablet_mode_angle ANG HYS    - set/get tablet mode "
-		"angle\n", cmd);
+	       "angle\n",
+	       cmd);
 	printf("  %s calibrate NUM                - run sensor calibration\n",
-		cmd);
+	       cmd);
 
 	return 0;
 }
@@ -5290,11 +5361,9 @@ static void motionsense_display_activities(uint32_t activities)
 		printf("%d: Significant motion\n",
 		       MOTIONSENSE_ACTIVITY_SIG_MOTION);
 	if (activities & BIT(MOTIONSENSE_ACTIVITY_DOUBLE_TAP))
-		printf("%d: Double tap\n",
-		       MOTIONSENSE_ACTIVITY_DOUBLE_TAP);
+		printf("%d: Double tap\n", MOTIONSENSE_ACTIVITY_DOUBLE_TAP);
 	if (activities & BIT(MOTIONSENSE_ACTIVITY_ORIENTATION))
-		printf("%d: Orientation\n",
-		       MOTIONSENSE_ACTIVITY_ORIENTATION);
+		printf("%d: Orientation\n", MOTIONSENSE_ACTIVITY_ORIENTATION);
 	if (activities & BIT(MOTIONSENSE_ACTIVITY_BODY_DETECTION))
 		printf("%d: Body Detection\n",
 		       MOTIONSENSE_ACTIVITY_BODY_DETECTION);
@@ -5315,32 +5384,30 @@ static int cmd_motionsense(int argc, char **argv)
 	 * for kernel_CrosECSysfsAccel.
 	 */
 	const char *motion_status_string[2][2] = {
-		{ "Motion sensing inactive", "0"},
-		{ "Motion sensing active", "1"},
+		{ "Motion sensing inactive", "0" },
+		{ "Motion sensing active", "1" },
 	};
 	/* No motionsense command has more than 7 args. */
 	if (argc > 7)
 		return ms_help(argv[0]);
 
-	if ((argc == 1) ||
-	    (argc == 2 && !strcasecmp(argv[1], "active"))) {
+	if ((argc == 1) || (argc == 2 && !strcasecmp(argv[1], "active"))) {
 		param.cmd = MOTIONSENSE_CMD_DUMP;
 		param.dump.max_sensor_count = ECTOOL_MAX_SENSOR;
-		rv = ec_command(
-			EC_CMD_MOTION_SENSE_CMD, 1,
-			&param, ms_command_sizes[param.cmd].outsize,
-			resp, ms_command_sizes[param.cmd].insize);
+		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1, &param,
+				ms_command_sizes[param.cmd].outsize, resp,
+				ms_command_sizes[param.cmd].insize);
 		if (rv > 0) {
-			printf("%s\n", motion_status_string[
-					!!(resp->dump.module_flags &
-					   MOTIONSENSE_MODULE_FLAG_ACTIVE)][
-					status_only]);
+			printf("%s\n", motion_status_string[!!(
+					       resp->dump.module_flags &
+					       MOTIONSENSE_MODULE_FLAG_ACTIVE)]
+							   [status_only]);
 			if (status_only)
 				return 0;
 
 			if (resp->dump.sensor_count > ECTOOL_MAX_SENSOR) {
 				printf("Too many sensors to handle: %d",
-						resp->dump.sensor_count);
+				       resp->dump.sensor_count);
 				return -1;
 			}
 			for (i = 0; i < resp->dump.sensor_count; i++) {
@@ -5352,11 +5419,11 @@ static int cmd_motionsense(int argc, char **argv)
 				 */
 				printf("Sensor %d: ", i);
 				if (resp->dump.sensor[i].flags &
-						MOTIONSENSE_SENSOR_FLAG_PRESENT)
+				    MOTIONSENSE_SENSOR_FLAG_PRESENT)
 					printf("%d\t%d\t%d\n",
-						resp->dump.sensor[i].data[0],
-						resp->dump.sensor[i].data[1],
-						resp->dump.sensor[i].data[2]);
+					       resp->dump.sensor[i].data[0],
+					       resp->dump.sensor[i].data[1],
+					       resp->dump.sensor[i].data[2]);
 				else
 					printf("None\n");
 			}
@@ -5380,9 +5447,9 @@ static int cmd_motionsense(int argc, char **argv)
 			return -1;
 		}
 
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, version,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
+		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, version, &param,
+				ms_command_sizes[param.cmd].outsize, resp,
+				ms_command_sizes[param.cmd].insize);
 		if (rv < 0)
 			return rv;
 
@@ -5529,11 +5596,11 @@ static int cmd_motionsense(int argc, char **argv)
 
 		if (version >= 3) {
 			printf("Min Frequency:              %d mHz\n",
-				resp->info_3.min_frequency);
+			       resp->info_3.min_frequency);
 			printf("Max Frequency:              %d mHz\n",
-				resp->info_3.max_frequency);
+			       resp->info_3.max_frequency);
 			printf("FIFO Max Event Count:       %d\n",
-				resp->info_3.fifo_max_event_count);
+			       resp->info_3.fifo_max_event_count);
 		}
 		if (version >= 4) {
 			printf("Flags:                      %d\n",
@@ -5558,9 +5625,9 @@ static int cmd_motionsense(int argc, char **argv)
 			}
 		}
 
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
+		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1, &param,
+				ms_command_sizes[param.cmd].outsize, resp,
+				ms_command_sizes[param.cmd].insize);
 
 		if (rv < 0)
 			return rv;
@@ -5596,9 +5663,9 @@ static int cmd_motionsense(int argc, char **argv)
 			}
 		}
 
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
+		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1, &param,
+				ms_command_sizes[param.cmd].outsize, resp,
+				ms_command_sizes[param.cmd].insize);
 
 		if (rv < 0)
 			return rv;
@@ -5634,9 +5701,9 @@ static int cmd_motionsense(int argc, char **argv)
 			}
 		}
 
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
+		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1, &param,
+				ms_command_sizes[param.cmd].outsize, resp,
+				ms_command_sizes[param.cmd].insize);
 
 		if (rv < 0)
 			return rv;
@@ -5657,9 +5724,9 @@ static int cmd_motionsense(int argc, char **argv)
 			}
 		}
 
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
+		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1, &param,
+				ms_command_sizes[param.cmd].outsize, resp,
+				ms_command_sizes[param.cmd].insize);
 
 		if (rv < 0)
 			return rv;
@@ -5680,16 +5747,16 @@ static int cmd_motionsense(int argc, char **argv)
 			EC_MOTION_SENSE_NO_VALUE;
 
 		if (argc == 4) {
-			param.tablet_mode_threshold.lid_angle = strtol(argv[2],
-								     &e, 0);
+			param.tablet_mode_threshold.lid_angle =
+				strtol(argv[2], &e, 0);
 
 			if (e && *e) {
 				fprintf(stderr, "Bad %s arg.\n", argv[2]);
 				return -1;
 			}
 
-			param.tablet_mode_threshold.hys_degree = strtol(argv[3],
-								     &e, 0);
+			param.tablet_mode_threshold.hys_degree =
+				strtol(argv[3], &e, 0);
 			if (e && *e) {
 				fprintf(stderr, "Bad %s arg.\n", argv[3]);
 				return -1;
@@ -5698,9 +5765,9 @@ static int cmd_motionsense(int argc, char **argv)
 			return ms_help(argv[0]);
 		}
 
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
+		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2, &param,
+				ms_command_sizes[param.cmd].outsize, resp,
+				ms_command_sizes[param.cmd].insize);
 
 		if (rv < 0)
 			return rv;
@@ -5717,17 +5784,17 @@ static int cmd_motionsense(int argc, char **argv)
 
 		param.cmd = MOTIONSENSE_CMD_DUMP;
 		param.dump.max_sensor_count = 0;
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
+		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1, &param,
+				ms_command_sizes[param.cmd].outsize, resp,
+				ms_command_sizes[param.cmd].insize);
 		if (rv < 0)
 			return rv;
 		sensor_count = resp->dump.sensor_count;
 
 		param.cmd = MOTIONSENSE_CMD_FIFO_INFO;
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
+		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2, &param,
+				ms_command_sizes[param.cmd].outsize, resp,
+				ms_command_sizes[param.cmd].insize);
 		if (rv < 0)
 			return rv;
 
@@ -5749,9 +5816,9 @@ static int cmd_motionsense(int argc, char **argv)
 			param.fifo_int_enable.enable = strtol(argv[2], &e, 0);
 		else
 			param.fifo_int_enable.enable = EC_MOTION_SENSE_NO_VALUE;
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
+		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2, &param,
+				ms_command_sizes[param.cmd].outsize, resp,
+				ms_command_sizes[param.cmd].insize);
 		if (rv < 0)
 			return rv;
 
@@ -5767,7 +5834,7 @@ static int cmd_motionsense(int argc, char **argv)
 		} fifo_read_buffer = {
 			.number_data = UINT32_MAX,
 		};
-		int print_data = 0,  max_data = strtol(argv[2], &e, 0);
+		int print_data = 0, max_data = strtol(argv[2], &e, 0);
 
 		if (e && *e) {
 			fprintf(stderr, "Bad %s arg.\n", argv[2]);
@@ -5781,8 +5848,7 @@ static int cmd_motionsense(int argc, char **argv)
 				MIN(ARRAY_SIZE(fifo_read_buffer.data),
 				    max_data - print_data);
 
-			rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2,
-					&param,
+			rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2, &param,
 					ms_command_sizes[param.cmd].outsize,
 					&fifo_read_buffer, ec_max_insize);
 			if (rv < 0)
@@ -5792,24 +5858,21 @@ static int cmd_motionsense(int argc, char **argv)
 			for (i = 0; i < fifo_read_buffer.number_data; i++) {
 				vector = &fifo_read_buffer.data[i];
 				if (vector->flags &
-					(MOTIONSENSE_SENSOR_FLAG_TIMESTAMP |
-					 MOTIONSENSE_SENSOR_FLAG_FLUSH)) {
-
+				    (MOTIONSENSE_SENSOR_FLAG_TIMESTAMP |
+				     MOTIONSENSE_SENSOR_FLAG_FLUSH)) {
 					printf("Timestamp:%" PRIx32 "%s\n",
-						vector->timestamp,
-						(vector->flags &
-						 MOTIONSENSE_SENSOR_FLAG_FLUSH ?
-						 " - Flush" : ""));
+					       vector->timestamp,
+					       (vector->flags & MOTIONSENSE_SENSOR_FLAG_FLUSH ?
+							" - Flush" :
+							""));
 				} else {
 					printf("Sensor %d: %d\t%d\t%d "
 					       "(as uint16: %u\t%u\t%u)\n",
-						vector->sensor_num,
-						vector->data[0],
-						vector->data[1],
-						vector->data[2],
-						vector->data[0],
-						vector->data[1],
-						vector->data[2]);
+					       vector->sensor_num,
+					       vector->data[0], vector->data[1],
+					       vector->data[2], vector->data[0],
+					       vector->data[1],
+					       vector->data[2]);
 				}
 			}
 		}
@@ -5824,9 +5887,9 @@ static int cmd_motionsense(int argc, char **argv)
 			return -1;
 		}
 
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
+		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1, &param,
+				ms_command_sizes[param.cmd].outsize, resp,
+				ms_command_sizes[param.cmd].insize);
 
 		return rv < 0 ? rv : 0;
 	}
@@ -5840,18 +5903,18 @@ static int cmd_motionsense(int argc, char **argv)
 			return -1;
 		}
 
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
+		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1, &param,
+				ms_command_sizes[param.cmd].outsize, resp,
+				ms_command_sizes[param.cmd].insize);
 
 		if (rv < 0)
 			return rv;
 
 		printf("--- Calibrated well ---\n");
 		printf("New offset vector: X:%d, Y:%d, Z:%d\n",
-			resp->perform_calib.offset[0],
-			resp->perform_calib.offset[1],
-			resp->perform_calib.offset[2]);
+		       resp->perform_calib.offset[0],
+		       resp->perform_calib.offset[1],
+		       resp->perform_calib.offset[2]);
 		if ((uint16_t)resp->perform_calib.temp ==
 		    EC_MOTION_SENSE_INVALID_CALIB_TEMP)
 			printf("Temperature at calibration unknown\n");
@@ -5877,19 +5940,24 @@ static int cmd_motionsense(int argc, char **argv)
 			/* Regarded as a command to set offset */
 			if (argc >= 6 && argc < 8) {
 				/* Set offset : X, Y, Z */
-				param.sensor_offset.flags = MOTION_SENSE_SET_OFFSET;
+				param.sensor_offset.flags =
+					MOTION_SENSE_SET_OFFSET;
 				for (i = 0; i < 3; i++) {
-					param.sensor_offset.offset[i] = strtol(argv[3+i], &e, 0);
+					param.sensor_offset.offset[i] =
+						strtol(argv[3 + i], &e, 0);
 					if (e && *e) {
-						fprintf(stderr, "Bad %s arg.\n", argv[3+i]);
+						fprintf(stderr, "Bad %s arg.\n",
+							argv[3 + i]);
 						return -1;
 					}
 				}
 				if (argc == 7) {
 					/* Set offset : Temperature */
-					param.sensor_offset.temp = strtol(argv[6], &e, 0);
+					param.sensor_offset.temp =
+						strtol(argv[6], &e, 0);
 					if (e && *e) {
-						fprintf(stderr, "Bad %s arg.\n", argv[6]);
+						fprintf(stderr, "Bad %s arg.\n",
+							argv[6]);
 						return -1;
 					}
 				}
@@ -5898,17 +5966,17 @@ static int cmd_motionsense(int argc, char **argv)
 			}
 		}
 
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
+		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1, &param,
+				ms_command_sizes[param.cmd].outsize, resp,
+				ms_command_sizes[param.cmd].insize);
 
 		if (rv < 0)
 			return rv;
 
 		printf("Offset vector: X:%d, Y:%d, Z:%d\n",
-			resp->sensor_offset.offset[0],
-			resp->sensor_offset.offset[1],
-			resp->sensor_offset.offset[2]);
+		       resp->sensor_offset.offset[0],
+		       resp->sensor_offset.offset[1],
+		       resp->sensor_offset.offset[2]);
 		if ((uint16_t)resp->sensor_offset.temp ==
 		    EC_MOTION_SENSE_INVALID_CALIB_TEMP)
 			printf("temperature at calibration unknown\n");
@@ -5921,9 +5989,9 @@ static int cmd_motionsense(int argc, char **argv)
 
 	if (argc == 2 && !strcasecmp(argv[1], "list_activities")) {
 		param.cmd = MOTIONSENSE_CMD_LIST_ACTIVITIES;
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
+		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2, &param,
+				ms_command_sizes[param.cmd].outsize, resp,
+				ms_command_sizes[param.cmd].insize);
 		if (rv < 0)
 			return rv;
 
@@ -5938,9 +6006,9 @@ static int cmd_motionsense(int argc, char **argv)
 		param.set_activity.activity = strtol(argv[2], &e, 0);
 		param.set_activity.enable = strtol(argv[3], &e, 0);
 
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
+		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2, &param,
+				ms_command_sizes[param.cmd].outsize, resp,
+				ms_command_sizes[param.cmd].insize);
 		if (rv < 0)
 			return rv;
 		return 0;
@@ -5949,9 +6017,9 @@ static int cmd_motionsense(int argc, char **argv)
 		param.cmd = MOTIONSENSE_CMD_GET_ACTIVITY;
 		param.get_activity.activity = strtol(argv[2], &e, 0);
 
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
+		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2, &param,
+				ms_command_sizes[param.cmd].outsize, resp,
+				ms_command_sizes[param.cmd].insize);
 		if (rv < 0)
 			return rv;
 		printf("State: %d\n", resp->get_activity.state);
@@ -5959,9 +6027,9 @@ static int cmd_motionsense(int argc, char **argv)
 	}
 	if (argc == 2 && !strcasecmp(argv[1], "lid_angle")) {
 		param.cmd = MOTIONSENSE_CMD_LID_ANGLE;
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
+		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2, &param,
+				ms_command_sizes[param.cmd].outsize, resp,
+				ms_command_sizes[param.cmd].insize);
 		if (rv < 0)
 			return rv;
 
@@ -6022,7 +6090,7 @@ static int cmd_motionsense(int argc, char **argv)
 			} else if (argc != 5) {
 				return ms_help(argv[0]);
 			}
-		/* spoof accel data */
+			/* spoof accel data */
 		} else if (argc >= 4) {
 			int enable, i;
 			int16_t val;
@@ -6048,10 +6116,10 @@ static int cmd_motionsense(int argc, char **argv)
 				param.spoof.spoof_enable =
 					MOTIONSENSE_SPOOF_MODE_CUSTOM;
 				for (i = 0; i < 3; i++) {
-					val = strtol(argv[4+i], &e, 0);
+					val = strtol(argv[4 + i], &e, 0);
 					if (e && *e) {
 						fprintf(stderr, "Bad %s arg.\n",
-							argv[4+i]);
+							argv[4 + i]);
 						return -1;
 					}
 					param.spoof.components[i] = val;
@@ -6064,9 +6132,9 @@ static int cmd_motionsense(int argc, char **argv)
 			}
 		}
 
-		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2,
-				&param, ms_command_sizes[param.cmd].outsize,
-				resp, ms_command_sizes[param.cmd].insize);
+		rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2, &param,
+				ms_command_sizes[param.cmd].outsize, resp,
+				ms_command_sizes[param.cmd].insize);
 		if (rv < 0)
 			return rv;
 
@@ -6091,8 +6159,8 @@ int cmd_next_event(int argc, char *argv[])
 	int rv;
 	int i;
 
-	rv = ec_command(EC_CMD_GET_NEXT_EVENT, 0,
-			NULL, 0, rdata, ec_max_insize);
+	rv = ec_command(EC_CMD_GET_NEXT_EVENT, 0, NULL, 0, rdata,
+			ec_max_insize);
 	if (rv < 0)
 		return rv;
 
@@ -6145,7 +6213,8 @@ int cmd_led(int argc, char *argv[])
 	if (argc < 3) {
 		fprintf(stderr,
 			"Usage: %s <name> <query | auto | "
-			"off | <color> | <color>=<value>...>\n", argv[0]);
+			"off | <color> | <color>=<value>...>\n",
+			argv[0]);
 		return -1;
 	}
 
@@ -6161,16 +6230,15 @@ int cmd_led(int argc, char *argv[])
 
 	if (!strcasecmp(argv[2], "query")) {
 		p.flags = EC_LED_FLAGS_QUERY;
-		rv = ec_command(EC_CMD_LED_CONTROL, 1, &p, sizeof(p),
-				&r, sizeof(r));
+		rv = ec_command(EC_CMD_LED_CONTROL, 1, &p, sizeof(p), &r,
+				sizeof(r));
 		printf("Brightness range for LED %d:\n", p.led_id);
 		if (rv < 0) {
 			fprintf(stderr, "Error: Unsupported LED.\n");
 			return rv;
 		}
 		for (i = 0; i < EC_LED_COLOR_COUNT; ++i)
-			printf("\t%s\t: 0x%x\n",
-			       led_color_names[i],
+			printf("\t%s\t: 0x%x\n", led_color_names[i],
 			       r.brightness_range[i]);
 		return 0;
 	}
@@ -6211,7 +6279,6 @@ int cmd_led(int argc, char *argv[])
 	return (rv < 0 ? rv : 0);
 }
 
-
 int cmd_usb_charge_set_mode(int argc, char *argv[])
 {
 	struct ec_params_usb_charge_set_mode p;
@@ -6237,18 +6304,17 @@ int cmd_usb_charge_set_mode(int argc, char *argv[])
 	p.inhibit_charge = 0;
 	if (argc == 4) {
 		p.inhibit_charge = strtol(argv[3], &e, 0);
-		if ((e && *e) || (p.inhibit_charge != 0 &&
-			p.inhibit_charge != 1)) {
+		if ((e && *e) ||
+		    (p.inhibit_charge != 0 && p.inhibit_charge != 1)) {
 			fprintf(stderr, "Bad value\n");
 			return -1;
 		}
 	}
 
 	printf("Setting port %d to mode %d inhibit_charge %d...\n",
-		p.usb_port_id, p.mode, p.inhibit_charge);
+	       p.usb_port_id, p.mode, p.inhibit_charge);
 
-	rv = ec_command(EC_CMD_USB_CHARGE_SET_MODE, 0,
-			&p, sizeof(p), NULL, 0);
+	rv = ec_command(EC_CMD_USB_CHARGE_SET_MODE, 0, &p, sizeof(p), NULL, 0);
 	if (rv < 0)
 		return rv;
 
@@ -6256,7 +6322,6 @@ int cmd_usb_charge_set_mode(int argc, char *argv[])
 	return 0;
 }
 
-
 int cmd_usb_mux(int argc, char *argv[])
 {
 	struct ec_params_usb_mux p;
@@ -6274,8 +6339,7 @@ int cmd_usb_mux(int argc, char *argv[])
 		return -1;
 	}
 
-	rv = ec_command(EC_CMD_USB_MUX, 0,
-			&p, sizeof(p), NULL, 0);
+	rv = ec_command(EC_CMD_USB_MUX, 0, &p, sizeof(p), NULL, 0);
 	if (rv < 0)
 		return rv;
 
@@ -6284,13 +6348,12 @@ int cmd_usb_mux(int argc, char *argv[])
 	return 0;
 }
 
-
 int cmd_usb_pd(int argc, char *argv[])
 {
-	const char *role_str[] = {"", "toggle", "toggle-off", "sink", "source",
-				  "freeze"};
-	const char *mux_str[] = {"", "none", "usb", "dp", "dock", "auto"};
-	const char *swap_str[] = {"", "dr_swap", "pr_swap", "vconn_swap"};
+	const char *role_str[] = { "",	   "toggle", "toggle-off",
+				   "sink", "source", "freeze" };
+	const char *mux_str[] = { "", "none", "usb", "dp", "dock", "auto" };
+	const char *swap_str[] = { "", "dr_swap", "pr_swap", "vconn_swap" };
 	struct ec_params_usb_pd_control p;
 	struct ec_response_usb_pd_control_v2 *r_v2 =
 		(struct ec_response_usb_pd_control_v2 *)ec_inbuf;
@@ -6377,7 +6440,6 @@ int cmd_usb_pd(int argc, char *argv[])
 			}
 		}
 
-
 		if (!option_ok) {
 			fprintf(stderr, "Unknown option: %s\n", argv[i]);
 			return -1;
@@ -6391,8 +6453,8 @@ int cmd_usb_pd(int argc, char *argv[])
 	else
 		cmdver = 0;
 
-	rv = ec_command(EC_CMD_USB_PD_CONTROL, cmdver, &p, sizeof(p),
-			ec_inbuf, ec_max_insize);
+	rv = ec_command(EC_CMD_USB_PD_CONTROL, cmdver, &p, sizeof(p), ec_inbuf,
+			ec_max_insize);
 
 	if (rv < 0 || argc != 2)
 		return (rv < 0) ? rv : 0;
@@ -6407,9 +6469,11 @@ int cmd_usb_pd(int argc, char *argv[])
 		       "Role:%s %s%s, Polarity:CC%d\n",
 		       p.port,
 		       (r_v1->enabled & PD_CTRL_RESP_ENABLED_COMMS) ?
-				"enabled" : "disabled",
+			       "enabled" :
+			       "disabled",
 		       (r_v1->enabled & PD_CTRL_RESP_ENABLED_CONNECTED) ?
-				"connected" : "disconnected",
+			       "connected" :
+			       "disconnected",
 		       r_v1->state,
 
 		       (r_v1->role & PD_CTRL_RESP_ROLE_POWER) ? "SRC" : "SNK",
@@ -6455,21 +6519,26 @@ int cmd_usb_pd(int argc, char *argv[])
 			}
 
 			printf("Cable type:%s\n",
-				r_v2->control_flags & USB_PD_CTRL_ACTIVE_CABLE ?
-					"Active" : "Passive");
+			       r_v2->control_flags & USB_PD_CTRL_ACTIVE_CABLE ?
+				       "Active" :
+				       "Passive");
 
 			printf("TBT Adapter type:%s\n",
-				r_v2->control_flags &
-				USB_PD_CTRL_TBT_LEGACY_ADAPTER ?
-					"Legacy" : "Gen3");
+			       r_v2->control_flags &
+					       USB_PD_CTRL_TBT_LEGACY_ADAPTER ?
+				       "Legacy" :
+				       "Gen3");
 
 			printf("Optical Cable:%s\n",
-				r_v2->control_flags &
-				USB_PD_CTRL_OPTICAL_CABLE ? "True" : "False");
+			       r_v2->control_flags & USB_PD_CTRL_OPTICAL_CABLE ?
+				       "True" :
+				       "False");
 
 			printf("Link LSRX Communication:%s-directional\n",
-				r_v2->control_flags &
-				USB_PD_CTRL_ACTIVE_LINK_UNIDIR ? "Uni" : "Bi");
+			       r_v2->control_flags &
+					       USB_PD_CTRL_ACTIVE_LINK_UNIDIR ?
+				       "Uni" :
+				       "Bi");
 
 			printf("TBT Cable Speed:");
 			switch (r_v2->cable_speed) {
@@ -6488,20 +6557,24 @@ int cmd_usb_pd(int argc, char *argv[])
 			printf("\n");
 
 			printf("Rounded support: 3rd Gen %srounded support\n",
-				r_v2->cable_gen ? "and 4th Gen " : "");
+			       r_v2->cable_gen ? "and 4th Gen " : "");
 		}
 		/* If connected to a PD device, then print port partner info */
 		if ((r_v1->enabled & PD_CTRL_RESP_ENABLED_CONNECTED) &&
 		    (r_v1->enabled & PD_CTRL_RESP_ENABLED_PD_CAPABLE))
 			printf("PD Partner Capabilities:\n%s%s%s%s",
-				(r_v1->role & PD_CTRL_RESP_ROLE_DR_POWER) ?
-					" DR power\n" : "",
-				(r_v1->role & PD_CTRL_RESP_ROLE_DR_DATA) ?
-					" DR data\n" : "",
-				(r_v1->role & PD_CTRL_RESP_ROLE_USB_COMM) ?
-					" USB capable\n" : "",
-				(r_v1->role & PD_CTRL_RESP_ROLE_UNCONSTRAINED) ?
-					" Unconstrained power\n" : "");
+			       (r_v1->role & PD_CTRL_RESP_ROLE_DR_POWER) ?
+				       " DR power\n" :
+				       "",
+			       (r_v1->role & PD_CTRL_RESP_ROLE_DR_DATA) ?
+				       " DR data\n" :
+				       "",
+			       (r_v1->role & PD_CTRL_RESP_ROLE_USB_COMM) ?
+				       " USB capable\n" :
+				       "",
+			       (r_v1->role & PD_CTRL_RESP_ROLE_UNCONSTRAINED) ?
+				       " Unconstrained power\n" :
+				       "");
 	}
 	return 0;
 }
@@ -6529,8 +6602,7 @@ int cmd_usb_pd_dps(int argc, char *argv[])
 		return -1;
 	}
 
-	rv = ec_command(EC_CMD_USB_PD_DPS_CONTROL, 0,
-			&p, sizeof(p), NULL, 0);
+	rv = ec_command(EC_CMD_USB_PD_DPS_CONTROL, 0, &p, sizeof(p), NULL, 0);
 	if (rv < 0)
 		return rv;
 
@@ -6556,8 +6628,7 @@ static void print_pd_power_info(struct ec_response_usb_pd_power_info *r)
 		printf("Unknown");
 	}
 
-	if ((r->role == USB_PD_PORT_POWER_SOURCE) &&
-	    (r->meas.current_max))
+	if ((r->role == USB_PD_PORT_POWER_SOURCE) && (r->meas.current_max))
 		printf(" %dmA", r->meas.current_max);
 
 	if ((r->role == USB_PD_PORT_POWER_DISCONNECTED) ||
@@ -6596,9 +6667,8 @@ static void print_pd_power_info(struct ec_response_usb_pd_power_info *r)
 		printf(" Unknown");
 		break;
 	}
-	printf(" %dmV / %dmA, max %dmV / %dmA",
-		r->meas.voltage_now, r->meas.current_lim, r->meas.voltage_max,
-		r->meas.current_max);
+	printf(" %dmV / %dmA, max %dmV / %dmA", r->meas.voltage_now,
+	       r->meas.current_lim, r->meas.voltage_max, r->meas.current_max);
 	if (r->max_power)
 		printf(" / %dmW", r->max_power / 1000);
 	printf("\n");
@@ -6618,17 +6688,16 @@ int cmd_usb_pd_mux_info(int argc, char *argv[])
 		return -1;
 	}
 
-	rv = ec_command(EC_CMD_USB_PD_PORTS, 0, NULL, 0,
-			ec_inbuf, ec_max_insize);
+	rv = ec_command(EC_CMD_USB_PD_PORTS, 0, NULL, 0, ec_inbuf,
+			ec_max_insize);
 	if (rv < 0)
 		return rv;
 	num_ports = ((struct ec_response_usb_pd_ports *)ec_inbuf)->num_ports;
 
 	for (i = 0; i < num_ports; i++) {
 		p.port = i;
-		rv = ec_command(EC_CMD_USB_PD_MUX_INFO, 0,
-				&p, sizeof(p),
-				&r, sizeof(r));
+		rv = ec_command(EC_CMD_USB_PD_MUX_INFO, 0, &p, sizeof(p), &r,
+				sizeof(r));
 		if (rv < 0)
 			return rv;
 
@@ -6642,29 +6711,27 @@ int cmd_usb_pd_mux_info(int argc, char *argv[])
 			printf("%d\t", i);
 			printf("%d\t", !!(r.flags & USB_PD_MUX_USB_ENABLED));
 			printf("%d\t", !!(r.flags & USB_PD_MUX_DP_ENABLED));
-			printf("%s\t",
-				r.flags & USB_PD_MUX_POLARITY_INVERTED ?
-							"INVERTED" : "NORMAL");
+			printf("%s\t", r.flags & USB_PD_MUX_POLARITY_INVERTED ?
+					       "INVERTED" :
+					       "NORMAL");
 			printf("%d\t", !!(r.flags & USB_PD_MUX_HPD_IRQ));
 			printf("%d\n", !!(r.flags & USB_PD_MUX_HPD_LVL));
 		} else {
 			/* Human-readable mux info. */
 			printf("Port %d: ", i);
-			printf("USB=%d ",
-				!!(r.flags & USB_PD_MUX_USB_ENABLED));
+			printf("USB=%d ", !!(r.flags & USB_PD_MUX_USB_ENABLED));
 			printf("DP=%d ", !!(r.flags & USB_PD_MUX_DP_ENABLED));
 			printf("POLARITY=%s ",
-				r.flags & USB_PD_MUX_POLARITY_INVERTED ?
-							"INVERTED" : "NORMAL");
-			printf("HPD_IRQ=%d ",
-				!!(r.flags & USB_PD_MUX_HPD_IRQ));
-			printf("HPD_LVL=%d ",
-				!!(r.flags & USB_PD_MUX_HPD_LVL));
+			       r.flags & USB_PD_MUX_POLARITY_INVERTED ?
+				       "INVERTED" :
+				       "NORMAL");
+			printf("HPD_IRQ=%d ", !!(r.flags & USB_PD_MUX_HPD_IRQ));
+			printf("HPD_LVL=%d ", !!(r.flags & USB_PD_MUX_HPD_LVL));
 			printf("SAFE=%d ", !!(r.flags & USB_PD_MUX_SAFE_MODE));
 			printf("TBT=%d ",
-				!!(r.flags & USB_PD_MUX_TBT_COMPAT_ENABLED));
+			       !!(r.flags & USB_PD_MUX_TBT_COMPAT_ENABLED));
 			printf("USB4=%d ",
-				!!(r.flags & USB_PD_MUX_USB4_ENABLED));
+			       !!(r.flags & USB_PD_MUX_USB4_ENABLED));
 			printf("\n");
 		}
 	}
@@ -6680,8 +6747,8 @@ int cmd_usb_pd_power(int argc, char *argv[])
 	int num_ports, i, rv;
 	char *e;
 
-	rv = ec_command(EC_CMD_USB_PD_PORTS, 0, NULL, 0,
-			ec_inbuf, ec_max_insize);
+	rv = ec_command(EC_CMD_USB_PD_PORTS, 0, NULL, 0, ec_inbuf,
+			ec_max_insize);
 	if (rv < 0)
 		return rv;
 	num_ports = ((struct ec_response_usb_pd_ports *)r)->num_ports;
@@ -6689,9 +6756,8 @@ int cmd_usb_pd_power(int argc, char *argv[])
 	if (argc < 2) {
 		for (i = 0; i < num_ports; i++) {
 			p.port = i;
-			rv = ec_command(EC_CMD_USB_PD_POWER_INFO, 0,
-					&p, sizeof(p),
-					ec_inbuf, ec_max_insize);
+			rv = ec_command(EC_CMD_USB_PD_POWER_INFO, 0, &p,
+					sizeof(p), ec_inbuf, ec_max_insize);
 			if (rv < 0)
 				return rv;
 
@@ -6704,8 +6770,7 @@ int cmd_usb_pd_power(int argc, char *argv[])
 			fprintf(stderr, "Bad port.\n");
 			return -1;
 		}
-		rv = ec_command(EC_CMD_USB_PD_POWER_INFO, 0,
-				&p, sizeof(p),
+		rv = ec_command(EC_CMD_USB_PD_POWER_INFO, 0, &p, sizeof(p),
 				ec_inbuf, ec_max_insize);
 		if (rv < 0)
 			return rv;
@@ -6724,8 +6789,7 @@ int cmd_kbpress(int argc, char *argv[])
 	int rv;
 
 	if (argc != 4) {
-		fprintf(stderr,
-			"Usage: %s <row> <col> <0|1>\n", argv[0]);
+		fprintf(stderr, "Usage: %s <row> <col> <0|1>\n", argv[0]);
 		return -1;
 	}
 	p.row = strtol(argv[1], &e, 0);
@@ -6745,11 +6809,9 @@ int cmd_kbpress(int argc, char *argv[])
 	}
 
 	printf("%s row %d col %d.\n", p.pressed ? "Pressing" : "Releasing",
-				      p.row,
-				      p.col);
+	       p.row, p.col);
 
-	rv = ec_command(EC_CMD_MKBP_SIMULATE_KEY, 0,
-			&p, sizeof(p), NULL, 0);
+	rv = ec_command(EC_CMD_MKBP_SIMULATE_KEY, 0, &p, sizeof(p), NULL, 0);
 	if (rv < 0)
 		return rv;
 	printf("Done.\n");
@@ -6761,14 +6823,14 @@ int cmd_keyboard_factory_test(int argc, char *argv[])
 	struct ec_response_keyboard_factory_test r;
 	int rv;
 
-	rv = ec_command(EC_CMD_KEYBOARD_FACTORY_TEST, 0,
-			NULL, 0, &r, sizeof(r));
+	rv = ec_command(EC_CMD_KEYBOARD_FACTORY_TEST, 0, NULL, 0, &r,
+			sizeof(r));
 	if (rv < 0)
 		return rv;
 
 	if (r.shorted != 0)
 		printf("Keyboard %d and %d pin are shorted.\n",
-				r.shorted & 0x00ff, r.shorted >> 8);
+		       r.shorted & 0x00ff, r.shorted >> 8);
 	else
 		printf("Keyboard factory test passed.\n");
 
@@ -6779,8 +6841,8 @@ int cmd_panic_info(int argc, char *argv[])
 {
 	int rv;
 
-	rv = ec_command(EC_CMD_GET_PANIC_INFO, 0, NULL, 0,
-			ec_inbuf, ec_max_insize);
+	rv = ec_command(EC_CMD_GET_PANIC_INFO, 0, NULL, 0, ec_inbuf,
+			ec_max_insize);
 	if (rv < 0)
 		return rv;
 
@@ -6792,7 +6854,6 @@ int cmd_panic_info(int argc, char *argv[])
 	return parse_panic_info((char *)(ec_inbuf), rv);
 }
 
-
 int cmd_power_info(int argc, char *argv[])
 {
 	struct ec_response_power_info_v1 r;
@@ -6832,7 +6893,6 @@ int cmd_power_info(int argc, char *argv[])
 	return 0;
 }
 
-
 int cmd_pse(int argc, char *argv[])
 {
 	struct ec_params_pse p;
@@ -6895,7 +6955,6 @@ int cmd_pse(int argc, char *argv[])
 	return 0;
 }
 
-
 int cmd_pstore_info(int argc, char *argv[])
 {
 	struct ec_response_pstore_info r;
@@ -6909,7 +6968,6 @@ int cmd_pstore_info(int argc, char *argv[])
 	return 0;
 }
 
-
 int cmd_pstore_read(int argc, char *argv[])
 {
 	struct ec_params_pstore_read p;
@@ -6921,8 +6979,8 @@ int cmd_pstore_read(int argc, char *argv[])
 	char *buf;
 
 	if (argc < 4) {
-		fprintf(stderr,
-			"Usage: %s <offset> <size> <filename>\n", argv[0]);
+		fprintf(stderr, "Usage: %s <offset> <size> <filename>\n",
+			argv[0]);
 		return -1;
 	}
 	offset = strtol(argv[1], &e, 0);
@@ -6947,8 +7005,8 @@ int cmd_pstore_read(int argc, char *argv[])
 	for (i = 0; i < size; i += EC_PSTORE_SIZE_MAX) {
 		p.offset = offset + i;
 		p.size = MIN(size - i, EC_PSTORE_SIZE_MAX);
-		rv = ec_command(EC_CMD_PSTORE_READ, 0,
-				&p, sizeof(p), rdata, sizeof(rdata));
+		rv = ec_command(EC_CMD_PSTORE_READ, 0, &p, sizeof(p), rdata,
+				sizeof(rdata));
 		if (rv < 0) {
 			fprintf(stderr, "Read error at offset %d\n", i);
 			free(buf);
@@ -6966,7 +7024,6 @@ int cmd_pstore_read(int argc, char *argv[])
 	return 0;
 }
 
-
 int cmd_pstore_write(int argc, char *argv[])
 {
 	struct ec_params_pstore_write p;
@@ -6998,8 +7055,7 @@ int cmd_pstore_write(int argc, char *argv[])
 		p.offset = offset + i;
 		p.size = MIN(size - i, EC_PSTORE_SIZE_MAX);
 		memcpy(p.data, buf + i, p.size);
-		rv = ec_command(EC_CMD_PSTORE_WRITE, 0,
-				&p, sizeof(p), NULL, 0);
+		rv = ec_command(EC_CMD_PSTORE_WRITE, 0, &p, sizeof(p), NULL, 0);
 		if (rv < 0) {
 			fprintf(stderr, "Write error at offset %d\n", i);
 			free(buf);
@@ -7012,7 +7068,6 @@ int cmd_pstore_write(int argc, char *argv[])
 	return 0;
 }
 
-
 int cmd_host_event_get_raw(int argc, char *argv[])
 {
 	uint32_t events = read_mapped_mem32(EC_MEMMAP_HOST_EVENTS);
@@ -7026,14 +7081,12 @@ int cmd_host_event_get_raw(int argc, char *argv[])
 	return 0;
 }
 
-
 int cmd_host_event_get_b(int argc, char *argv[])
 {
 	struct ec_response_host_event_mask r;
 	int rv;
 
-	rv = ec_command(EC_CMD_HOST_EVENT_GET_B, 0,
-			NULL, 0, &r, sizeof(r));
+	rv = ec_command(EC_CMD_HOST_EVENT_GET_B, 0, NULL, 0, &r, sizeof(r));
 	if (rv < 0)
 		return rv;
 	if (rv < sizeof(r)) {
@@ -7050,14 +7103,13 @@ int cmd_host_event_get_b(int argc, char *argv[])
 	return 0;
 }
 
-
 int cmd_host_event_get_smi_mask(int argc, char *argv[])
 {
 	struct ec_response_host_event_mask r;
 	int rv;
 
-	rv = ec_command(EC_CMD_HOST_EVENT_GET_SMI_MASK, 0,
-			NULL, 0, &r, sizeof(r));
+	rv = ec_command(EC_CMD_HOST_EVENT_GET_SMI_MASK, 0, NULL, 0, &r,
+			sizeof(r));
 	if (rv < 0)
 		return rv;
 
@@ -7065,14 +7117,13 @@ int cmd_host_event_get_smi_mask(int argc, char *argv[])
 	return 0;
 }
 
-
 int cmd_host_event_get_sci_mask(int argc, char *argv[])
 {
 	struct ec_response_host_event_mask r;
 	int rv;
 
-	rv = ec_command(EC_CMD_HOST_EVENT_GET_SCI_MASK, 0,
-			NULL, 0, &r, sizeof(r));
+	rv = ec_command(EC_CMD_HOST_EVENT_GET_SCI_MASK, 0, NULL, 0, &r,
+			sizeof(r));
 	if (rv < 0)
 		return rv;
 
@@ -7080,14 +7131,13 @@ int cmd_host_event_get_sci_mask(int argc, char *argv[])
 	return 0;
 }
 
-
 int cmd_host_event_get_wake_mask(int argc, char *argv[])
 {
 	struct ec_response_host_event_mask r;
 	int rv;
 
-	rv = ec_command(EC_CMD_HOST_EVENT_GET_WAKE_MASK, 0,
-			NULL, 0, &r, sizeof(r));
+	rv = ec_command(EC_CMD_HOST_EVENT_GET_WAKE_MASK, 0, NULL, 0, &r,
+			sizeof(r));
 	if (rv < 0)
 		return rv;
 
@@ -7095,7 +7145,6 @@ int cmd_host_event_get_wake_mask(int argc, char *argv[])
 	return 0;
 }
 
-
 int cmd_host_event_set_smi_mask(int argc, char *argv[])
 {
 	struct ec_params_host_event_mask p;
@@ -7112,8 +7161,8 @@ int cmd_host_event_set_smi_mask(int argc, char *argv[])
 		return -1;
 	}
 
-	rv = ec_command(EC_CMD_HOST_EVENT_SET_SMI_MASK, 0,
-			&p, sizeof(p), NULL, 0);
+	rv = ec_command(EC_CMD_HOST_EVENT_SET_SMI_MASK, 0, &p, sizeof(p), NULL,
+			0);
 	if (rv < 0)
 		return rv;
 
@@ -7121,7 +7170,6 @@ int cmd_host_event_set_smi_mask(int argc, char *argv[])
 	return 0;
 }
 
-
 int cmd_host_event_set_sci_mask(int argc, char *argv[])
 {
 	struct ec_params_host_event_mask p;
@@ -7138,8 +7186,8 @@ int cmd_host_event_set_sci_mask(int argc, char *argv[])
 		return -1;
 	}
 
-	rv = ec_command(EC_CMD_HOST_EVENT_SET_SCI_MASK, 0,
-			&p, sizeof(p), NULL, 0);
+	rv = ec_command(EC_CMD_HOST_EVENT_SET_SCI_MASK, 0, &p, sizeof(p), NULL,
+			0);
 	if (rv < 0)
 		return rv;
 
@@ -7147,7 +7195,6 @@ int cmd_host_event_set_sci_mask(int argc, char *argv[])
 	return 0;
 }
 
-
 int cmd_host_event_set_wake_mask(int argc, char *argv[])
 {
 	struct ec_params_host_event_mask p;
@@ -7164,8 +7211,8 @@ int cmd_host_event_set_wake_mask(int argc, char *argv[])
 		return -1;
 	}
 
-	rv = ec_command(EC_CMD_HOST_EVENT_SET_WAKE_MASK, 0,
-			&p, sizeof(p), NULL, 0);
+	rv = ec_command(EC_CMD_HOST_EVENT_SET_WAKE_MASK, 0, &p, sizeof(p), NULL,
+			0);
 	if (rv < 0)
 		return rv;
 
@@ -7173,7 +7220,6 @@ int cmd_host_event_set_wake_mask(int argc, char *argv[])
 	return 0;
 }
 
-
 int cmd_host_event_clear(int argc, char *argv[])
 {
 	struct ec_params_host_event_mask p;
@@ -7190,8 +7236,7 @@ int cmd_host_event_clear(int argc, char *argv[])
 		return -1;
 	}
 
-	rv = ec_command(EC_CMD_HOST_EVENT_CLEAR, 0,
-			&p, sizeof(p), NULL, 0);
+	rv = ec_command(EC_CMD_HOST_EVENT_CLEAR, 0, &p, sizeof(p), NULL, 0);
 	if (rv < 0)
 		return rv;
 
@@ -7199,7 +7244,6 @@ int cmd_host_event_clear(int argc, char *argv[])
 	return 0;
 }
 
-
 int cmd_host_event_clear_b(int argc, char *argv[])
 {
 	struct ec_params_host_event_mask p;
@@ -7216,8 +7260,7 @@ int cmd_host_event_clear_b(int argc, char *argv[])
 		return -1;
 	}
 
-	rv = ec_command(EC_CMD_HOST_EVENT_CLEAR_B, 0,
-			&p, sizeof(p), NULL, 0);
+	rv = ec_command(EC_CMD_HOST_EVENT_CLEAR_B, 0, &p, sizeof(p), NULL, 0);
 	if (rv < 0)
 		return rv;
 
@@ -7225,7 +7268,6 @@ int cmd_host_event_clear_b(int argc, char *argv[])
 	return 0;
 }
 
-
 int cmd_switches(int argc, char *argv[])
 {
 	uint8_t s = read_mapped_mem8(EC_MEMMAP_SWITCHES);
@@ -7242,7 +7284,6 @@ int cmd_switches(int argc, char *argv[])
 	return 0;
 }
 
-
 int cmd_wireless(int argc, char *argv[])
 {
 	char *e;
@@ -7271,8 +7312,8 @@ int cmd_wireless(int argc, char *argv[])
 		struct ec_params_switch_enable_wireless_v0 p;
 
 		p.enabled = now_flags;
-		rv = ec_command(EC_CMD_SWITCH_ENABLE_WIRELESS, 0,
-				&p, sizeof(p), NULL, 0);
+		rv = ec_command(EC_CMD_SWITCH_ENABLE_WIRELESS, 0, &p, sizeof(p),
+				NULL, 0);
 		if (rv < 0)
 			return rv;
 
@@ -7307,19 +7348,18 @@ int cmd_wireless(int argc, char *argv[])
 		}
 
 		rv = ec_command(EC_CMD_SWITCH_ENABLE_WIRELESS,
-				EC_VER_SWITCH_ENABLE_WIRELESS,
-				&p, sizeof(p), &r, sizeof(r));
+				EC_VER_SWITCH_ENABLE_WIRELESS, &p, sizeof(p),
+				&r, sizeof(r));
 		if (rv < 0)
 			return rv;
 
-		printf("Now=0x%x, suspend=0x%x\n",
-		       r.now_flags, r.suspend_flags);
+		printf("Now=0x%x, suspend=0x%x\n", r.now_flags,
+		       r.suspend_flags);
 	}
 
 	return 0;
 }
 
-
 static void cmd_locate_chip_help(const char *const cmd)
 {
 	fprintf(stderr,
@@ -7331,15 +7371,12 @@ static void cmd_locate_chip_help(const char *const cmd)
 		cmd);
 }
 
-static const char *bus_type[] = {
-	"I2C",
-	"EMBEDDED"
-};
+static const char *bus_type[] = { "I2C", "EMBEDDED" };
 
 int cmd_locate_chip(int argc, char *argv[])
 {
 	struct ec_params_locate_chip p;
-	struct ec_response_locate_chip r = {0};
+	struct ec_response_locate_chip r = { 0 };
 	char *e;
 	int rv;
 
@@ -7382,8 +7419,8 @@ int cmd_locate_chip(int argc, char *argv[])
 	if (rv < 0)
 		return rv;
 
-	if (r.bus_type >= EC_BUS_TYPE_COUNT
-			|| r.bus_type >= ARRAY_SIZE(bus_type)) {
+	if (r.bus_type >= EC_BUS_TYPE_COUNT ||
+	    r.bus_type >= ARRAY_SIZE(bus_type)) {
 		fprintf(stderr, "Unknown bus type (%d)\n", r.bus_type);
 		return -1;
 	}
@@ -7415,8 +7452,8 @@ int cmd_lcd_backlight(int argc, char *argv[])
 		return -1;
 	}
 
-	rv = ec_command(EC_CMD_SWITCH_ENABLE_BKLIGHT, 0,
-			&p, sizeof(p), NULL, 0);
+	rv = ec_command(EC_CMD_SWITCH_ENABLE_BKLIGHT, 0, &p, sizeof(p), NULL,
+			0);
 	if (rv < 0)
 		return rv;
 
@@ -7426,8 +7463,7 @@ int cmd_lcd_backlight(int argc, char *argv[])
 
 static void cmd_basestate_help(void)
 {
-	fprintf(stderr,
-		"Usage: ectool basestate [attach | detach | reset]\n");
+	fprintf(stderr, "Usage: ectool basestate [attach | detach | reset]\n");
 }
 
 int cmd_basestate(int argc, char *argv[])
@@ -7450,8 +7486,7 @@ int cmd_basestate(int argc, char *argv[])
 		return -1;
 	}
 
-	return ec_command(EC_CMD_SET_BASE_STATE, 0,
-			  &p, sizeof(p), NULL, 0);
+	return ec_command(EC_CMD_SET_BASE_STATE, 0, &p, sizeof(p), NULL, 0);
 }
 
 int cmd_ext_power_limit(int argc, char *argv[])
@@ -7461,8 +7496,7 @@ int cmd_ext_power_limit(int argc, char *argv[])
 	char *e;
 
 	if (argc != 3) {
-		fprintf(stderr,
-			"Usage: %s <max_current_mA> <max_voltage_mV>\n",
+		fprintf(stderr, "Usage: %s <max_current_mA> <max_voltage_mV>\n",
 			argv[0]);
 		return -1;
 	}
@@ -7480,11 +7514,10 @@ int cmd_ext_power_limit(int argc, char *argv[])
 	}
 
 	/* Send version 1 of command */
-	return ec_command(EC_CMD_EXTERNAL_POWER_LIMIT, 1, &p, sizeof(p),
-			  NULL, 0);
+	return ec_command(EC_CMD_EXTERNAL_POWER_LIMIT, 1, &p, sizeof(p), NULL,
+			  0);
 }
 
-
 int cmd_charge_current_limit(int argc, char *argv[])
 {
 	struct ec_params_current_limit p;
@@ -7502,8 +7535,7 @@ int cmd_charge_current_limit(int argc, char *argv[])
 		return -1;
 	}
 
-	rv = ec_command(EC_CMD_CHARGE_CURRENT_LIMIT, 0, &p, sizeof(p),
-			NULL, 0);
+	rv = ec_command(EC_CMD_CHARGE_CURRENT_LIMIT, 0, &p, sizeof(p), NULL, 0);
 	return rv;
 }
 
@@ -7513,16 +7545,16 @@ static void cmd_charge_control_help(const char *cmd, const char *msg)
 		fprintf(stderr, "ERROR: %s\n", msg);
 
 	fprintf(stderr,
-	"\n"
-	"  Usage: %s\n"
-	"    Get current settings.\n"
-	"  Usage: %s normal|idle|discharge\n"
-	"    Set charge mode (and disable battery sustainer).\n"
-	"  Usage: %s normal <lower> <upper>\n"
-	"    Enable battery sustainer. <lower> and <upper> are battery SoC\n"
-	"    between which EC tries to keep the battery level.\n"
-	"\n",
-	cmd, cmd, cmd);
+		"\n"
+		"  Usage: %s\n"
+		"    Get current settings.\n"
+		"  Usage: %s normal|idle|discharge\n"
+		"    Set charge mode (and disable battery sustainer).\n"
+		"  Usage: %s normal <lower> <upper>\n"
+		"    Enable battery sustainer. <lower> and <upper> are battery SoC\n"
+		"    between which EC tries to keep the battery level.\n"
+		"\n",
+		cmd, cmd, cmd);
 }
 
 int cmd_charge_control(int argc, char *argv[])
@@ -7530,7 +7562,7 @@ int cmd_charge_control(int argc, char *argv[])
 	struct ec_params_charge_control p;
 	struct ec_response_charge_control r;
 	int version = 2;
-	const char * const charge_mode_text[] = EC_CHARGE_MODE_TEXT;
+	const char *const charge_mode_text[] = EC_CHARGE_MODE_TEXT;
 	char *e;
 	int rv;
 
@@ -7544,19 +7576,22 @@ int cmd_charge_control(int argc, char *argv[])
 			return -1;
 		}
 		p.cmd = EC_CHARGE_CONTROL_CMD_GET;
-		rv = ec_command(EC_CMD_CHARGE_CONTROL, version,
-				&p, sizeof(p), &r, sizeof(r));
+		rv = ec_command(EC_CMD_CHARGE_CONTROL, version, &p, sizeof(p),
+				&r, sizeof(r));
 		if (rv < 0) {
 			fprintf(stderr, "Command failed.\n");
 			return rv;
 		}
 		printf("Charge mode = %s (%d)\n",
-		       r.mode < ARRAY_SIZE(charge_mode_text)
-		       		? charge_mode_text[r.mode] : "UNDEFINED",
+		       r.mode < ARRAY_SIZE(charge_mode_text) ?
+			       charge_mode_text[r.mode] :
+			       "UNDEFINED",
 		       r.mode);
 		printf("Battery sustainer = %s (%d%% ~ %d%%)\n",
-		       (r.sustain_soc.lower != -1 && r.sustain_soc.upper != -1)
-				? "on" : "off",
+		       (r.sustain_soc.lower != -1 &&
+			r.sustain_soc.upper != -1) ?
+			       "on" :
+			       "off",
 		       r.sustain_soc.lower, r.sustain_soc.upper);
 		return 0;
 	}
@@ -7569,20 +7604,21 @@ int cmd_charge_control(int argc, char *argv[])
 			p.sustain_soc.upper = -1;
 		} else if (argc == 4) {
 			if (version < 2) {
-				cmd_charge_control_help(argv[0],
+				cmd_charge_control_help(
+					argv[0],
 					"Old EC doesn't support sustainer.");
 				return -1;
 			}
 			p.sustain_soc.lower = strtol(argv[2], &e, 0);
 			if (e && *e) {
-				cmd_charge_control_help(argv[0],
-						"Bad character in <lower>");
+				cmd_charge_control_help(
+					argv[0], "Bad character in <lower>");
 				return -1;
 			}
 			p.sustain_soc.upper = strtol(argv[3], &e, 0);
 			if (e && *e) {
-				cmd_charge_control_help(argv[0],
-						"Bad character in <upper>");
+				cmd_charge_control_help(
+					argv[0], "Bad character in <upper>");
 				return -1;
 			}
 		} else {
@@ -7615,8 +7651,10 @@ int cmd_charge_control(int argc, char *argv[])
 	switch (p.mode) {
 	case CHARGE_CONTROL_NORMAL:
 		printf("Charge state machine is in normal mode%s.\n",
-		       (p.sustain_soc.lower == -1 || p.sustain_soc.upper == -1)
-		       		? "" : " with sustainer enabled");
+		       (p.sustain_soc.lower == -1 ||
+			p.sustain_soc.upper == -1) ?
+			       "" :
+			       " with sustainer enabled");
 		break;
 	case CHARGE_CONTROL_IDLE:
 		printf("Charge state machine force idle.\n");
@@ -7630,7 +7668,6 @@ int cmd_charge_control(int argc, char *argv[])
 	return 0;
 }
 
-
 static void print_bool(const char *name, bool value)
 {
 	printf("%s = %s\n", name, value ? "true" : "false");
@@ -7677,7 +7714,6 @@ usage:
 	return -1;
 }
 
-
 #define ST_CMD_SIZE ST_FLD_SIZE(ec_params_charge_state, cmd)
 #define ST_PRM_SIZE(SUBCMD) \
 	(ST_CMD_SIZE + ST_FLD_SIZE(ec_params_charge_state, SUBCMD))
@@ -7691,7 +7727,7 @@ static const struct {
 	/* Order must match enum charge_state_command */
 	{ ST_CMD_SIZE, ST_RSP_SIZE(get_state) },
 	{ ST_PRM_SIZE(get_param), ST_RSP_SIZE(get_param) },
-	{ ST_PRM_SIZE(set_param), 0},
+	{ ST_PRM_SIZE(set_param), 0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(cs_paramcount) == CHARGE_STATE_NUM_CMDS);
 
@@ -7705,20 +7741,16 @@ static int cs_do_cmd(struct ec_params_charge_state *to_ec,
 	int rv;
 	int cmd = to_ec->cmd;
 
-	rv = ec_command(EC_CMD_CHARGE_STATE, 0,
-			to_ec, cs_paramcount[cmd].to_ec_size,
-			from_ec, cs_paramcount[cmd].from_ec_size);
+	rv = ec_command(EC_CMD_CHARGE_STATE, 0, to_ec,
+			cs_paramcount[cmd].to_ec_size, from_ec,
+			cs_paramcount[cmd].from_ec_size);
 
 	return (rv < 0 ? 1 : 0);
 }
 
-static const char * const base_params[] = {
-	"chg_voltage",
-	"chg_current",
-	"chg_input_current",
-	"chg_status",
-	"chg_option",
-	"limit_power",
+static const char *const base_params[] = {
+	"chg_voltage", "chg_current", "chg_input_current",
+	"chg_status",  "chg_option",  "limit_power",
 };
 BUILD_ASSERT(ARRAY_SIZE(base_params) == CS_NUM_BASE_PARAMS);
 
@@ -7825,8 +7857,8 @@ int cmd_gpio_get(int argc, char *argv[])
 		}
 		strcpy(p.name, argv[1]);
 
-		rv = ec_command(EC_CMD_GPIO_GET, cmdver, &p,
-				sizeof(p), &r, sizeof(r));
+		rv = ec_command(EC_CMD_GPIO_GET, cmdver, &p, sizeof(p), &r,
+				sizeof(r));
 		if (rv < 0)
 			return rv;
 
@@ -7860,21 +7892,21 @@ int cmd_gpio_get(int argc, char *argv[])
 		}
 		strcpy(p_v1.get_value_by_name.name, argv[1]);
 
-		rv = ec_command(EC_CMD_GPIO_GET, cmdver, &p_v1,
-				sizeof(p_v1), &r_v1, sizeof(r_v1));
+		rv = ec_command(EC_CMD_GPIO_GET, cmdver, &p_v1, sizeof(p_v1),
+				&r_v1, sizeof(r_v1));
 
 		if (rv < 0)
 			return rv;
 
 		printf("GPIO %s = %d\n", p_v1.get_value_by_name.name,
-			r_v1.get_value_by_name.val);
+		       r_v1.get_value_by_name.val);
 		return 0;
 	}
 
 	/* Need GPIO count for EC_GPIO_GET_COUNT or EC_GPIO_GET_INFO */
 	p_v1.subcmd = EC_GPIO_GET_COUNT;
-	rv = ec_command(EC_CMD_GPIO_GET, cmdver, &p_v1,
-			sizeof(p_v1), &r_v1, sizeof(r_v1));
+	rv = ec_command(EC_CMD_GPIO_GET, cmdver, &p_v1, sizeof(p_v1), &r_v1,
+			sizeof(r_v1));
 	if (rv < 0)
 		return rv;
 
@@ -7890,19 +7922,18 @@ int cmd_gpio_get(int argc, char *argv[])
 	for (i = 0; i < num_gpios; i++) {
 		p_v1.get_info.index = i;
 
-		rv = ec_command(EC_CMD_GPIO_GET, cmdver, &p_v1,
-				sizeof(p_v1), &r_v1, sizeof(r_v1));
+		rv = ec_command(EC_CMD_GPIO_GET, cmdver, &p_v1, sizeof(p_v1),
+				&r_v1, sizeof(r_v1));
 		if (rv < 0)
 			return rv;
 
 		printf("%2d %-32s 0x%04X\n", r_v1.get_info.val,
-			r_v1.get_info.name, r_v1.get_info.flags);
+		       r_v1.get_info.name, r_v1.get_info.flags);
 	}
 
 	return 0;
 }
 
-
 int cmd_gpio_set(int argc, char *argv[])
 {
 	struct ec_params_gpio_set p;
@@ -7947,6 +7978,8 @@ void print_battery_flags(int flags)
 		printf(" CHARGING");
 	if (flags & EC_BATT_FLAG_LEVEL_CRITICAL)
 		printf(" LEVEL_CRITICAL");
+	if (flags & EC_BATT_FLAG_CUT_OFF)
+		printf(" CUT_OFF");
 	printf("\n");
 }
 
@@ -7961,16 +7994,14 @@ int get_battery_command(int index)
 	printf("Battery %d info:\n", index);
 
 	static_p.index = index;
-	rv = ec_command(EC_CMD_BATTERY_GET_STATIC, 1,
-			&static_p, sizeof(static_p),
-			&static_r, sizeof(static_r));
+	rv = ec_command(EC_CMD_BATTERY_GET_STATIC, 1, &static_p,
+			sizeof(static_p), &static_r, sizeof(static_r));
 	if (rv < 0)
 		return -1;
 
 	dynamic_p.index = index;
-	rv = ec_command(EC_CMD_BATTERY_GET_DYNAMIC, 0,
-			&dynamic_p, sizeof(dynamic_p),
-			&dynamic_r, sizeof(dynamic_r));
+	rv = ec_command(EC_CMD_BATTERY_GET_DYNAMIC, 0, &dynamic_p,
+			sizeof(dynamic_p), &dynamic_r, sizeof(dynamic_r));
 	if (rv < 0)
 		return -1;
 
@@ -8021,7 +8052,7 @@ int get_battery_command(int index)
 	if (!is_battery_range(dynamic_r.remaining_capacity))
 		goto cmd_error;
 	printf("  Remaining capacity      %u mAh\n",
-						dynamic_r.remaining_capacity);
+	       dynamic_r.remaining_capacity);
 
 	if (!is_battery_range(dynamic_r.desired_voltage))
 		goto cmd_error;
@@ -8062,8 +8093,7 @@ int cmd_battery(int argc, char *argv[])
 	 * Read non-primary batteries through hostcmd, and all batteries
 	 * if longer strings are supported for static info.
 	 */
-	if (index > 0 ||
-	    ec_cmd_version_supported(EC_CMD_BATTERY_GET_STATIC, 1))
+	if (index > 0 || ec_cmd_version_supported(EC_CMD_BATTERY_GET_STATIC, 1))
 		return get_battery_command(index);
 
 	val = read_mapped_mem8(EC_MEMMAP_BATTERY_VERSION);
@@ -8077,25 +8107,25 @@ int cmd_battery(int argc, char *argv[])
 	printf("Battery info:\n");
 
 	rv = read_mapped_string(EC_MEMMAP_BATT_MFGR, batt_text,
-			sizeof(batt_text));
+				sizeof(batt_text));
 	if (rv < 0 || !is_string_printable(batt_text))
 		goto cmd_error;
 	printf("  OEM name:               %s\n", batt_text);
 
 	rv = read_mapped_string(EC_MEMMAP_BATT_MODEL, batt_text,
-			sizeof(batt_text));
+				sizeof(batt_text));
 	if (rv < 0 || !is_string_printable(batt_text))
 		goto cmd_error;
 	printf("  Model number:           %s\n", batt_text);
 
 	rv = read_mapped_string(EC_MEMMAP_BATT_TYPE, batt_text,
-			sizeof(batt_text));
+				sizeof(batt_text));
 	if (rv < 0 || !is_string_printable(batt_text))
 		goto cmd_error;
 	printf("  Chemistry   :           %s\n", batt_text);
 
 	rv = read_mapped_string(EC_MEMMAP_BATT_SERIAL, batt_text,
-			sizeof(batt_text));
+				sizeof(batt_text));
 	printf("  Serial number:          %s\n", batt_text);
 
 	val = read_mapped_mem32(EC_MEMMAP_BATT_DCAP);
@@ -8179,10 +8209,11 @@ int cmd_battery_cut_off(int argc, char *argv[])
 
 	if (rv < 0) {
 		fprintf(stderr, "Failed to cut off battery, rv=%d\n", rv);
-		fprintf(stderr, "It is expected if the rv is -%d "
-				"(EC_RES_INVALID_COMMAND) if the battery "
-				"doesn't support cut-off function.\n",
-				EC_RES_INVALID_COMMAND);
+		fprintf(stderr,
+			"It is expected if the rv is -%d "
+			"(EC_RES_INVALID_COMMAND) if the battery "
+			"doesn't support cut-off function.\n",
+			EC_RES_INVALID_COMMAND);
 	} else {
 		printf("\n");
 		printf("SUCCESS. The battery has arranged a cut-off.\n");
@@ -8234,8 +8265,8 @@ int cmd_battery_vendor_param(int argc, char *argv[])
 		}
 	}
 
-	rv = ec_command(EC_CMD_BATTERY_VENDOR_PARAM, 0, &p, sizeof(p),
-			&r, sizeof(r));
+	rv = ec_command(EC_CMD_BATTERY_VENDOR_PARAM, 0, &p, sizeof(p), &r,
+			sizeof(r));
 
 	if (rv < 0)
 		return rv;
@@ -8269,28 +8300,30 @@ int cmd_board_version(int argc, char *argv[])
 static void cmd_cbi_help(char *cmd)
 {
 	fprintf(stderr,
-	"  Usage: %s get <tag> [get_flag]\n"
-	"  Usage: %s set <tag> <value/string> <size> [set_flag]\n"
-	"  Usage: %s remove <tag> [set_flag]\n"
-	"    <tag> is one of:\n"
-	"      0: BOARD_VERSION\n"
-	"      1: OEM_ID\n"
-	"      2: SKU_ID\n"
-	"      3: DRAM_PART_NUM (string)\n"
-	"      4: OEM_NAME (string)\n"
-	"      5: MODEL_ID\n"
-	"      6: FW_CONFIG\n"
-	"      7: PCB_VENDOR\n"
-	"      8: SSFC\n"
-	"      9: REWORK_ID\n"
-	"    <size> is the size of the data in byte. It should be zero for\n"
-	"      string types.\n"
-	"    <value/string> is an integer or a string to be set\n"
-	"    [get_flag] is combination of:\n"
-	"      01b: Invalidate cache and reload data from EEPROM\n"
-	"    [set_flag] is combination of:\n"
-	"      01b: Skip write to EEPROM. Use for back-to-back writes\n"
-	"      10b: Set all fields to defaults first\n", cmd, cmd, cmd);
+		"  Usage: %s get <tag> [get_flag]\n"
+		"  Usage: %s set <tag> <value/string> <size> [set_flag]\n"
+		"  Usage: %s remove <tag> [set_flag]\n"
+		"    <tag> is one of:\n"
+		"      0: BOARD_VERSION\n"
+		"      1: OEM_ID\n"
+		"      2: SKU_ID\n"
+		"      3: DRAM_PART_NUM (string)\n"
+		"      4: OEM_NAME (string)\n"
+		"      5: MODEL_ID\n"
+		"      6: FW_CONFIG\n"
+		"      7: PCB_VENDOR\n"
+		"      8: SSFC\n"
+		"      9: REWORK_ID\n"
+		"      10: FACTORY_CALIBRATION_DATA\n"
+		"    <size> is the size of the data in byte. It should be zero for\n"
+		"      string types.\n"
+		"    <value/string> is an integer or a string to be set\n"
+		"    [get_flag] is combination of:\n"
+		"      01b: Invalidate cache and reload data from EEPROM\n"
+		"    [set_flag] is combination of:\n"
+		"      01b: Skip write to EEPROM. Use for back-to-back writes\n"
+		"      10b: Set all fields to defaults first\n",
+		cmd, cmd, cmd);
 }
 
 static int cmd_cbi_is_string_field(enum cbi_data_tag tag)
@@ -8347,15 +8380,15 @@ static int cmd_cbi(int argc, char *argv[])
 		if (cmd_cbi_is_string_field(tag)) {
 			printf("%.*s", rv, (const char *)ec_inbuf);
 		} else {
-			const uint8_t * const buffer =
+			const uint8_t *const buffer =
 				(const uint8_t *const)(ec_inbuf);
 			uint64_t int_value = 0;
-                        for(i = 0; i < rv; i++)
+			for (i = 0; i < rv; i++)
 				int_value |= (uint64_t)buffer[i] << (i * 8);
 
-                        printf("As uint: %llu (0x%llx)\n",
-				(unsigned long long)int_value,
-                                (unsigned long long)int_value);
+			printf("As uint: %llu (0x%llx)\n",
+			       (unsigned long long)int_value,
+			       (unsigned long long)int_value);
 			printf("As binary:");
 			for (i = 0; i < rv; i++) {
 				if (i % 32 == 31)
@@ -8367,7 +8400,7 @@ static int cmd_cbi(int argc, char *argv[])
 		return 0;
 	} else if (!strcasecmp(argv[1], "set")) {
 		struct ec_params_set_cbi *p =
-				(struct ec_params_set_cbi *)ec_outbuf;
+			(struct ec_params_set_cbi *)ec_outbuf;
 		void *val_ptr;
 		uint64_t val = 0;
 		uint8_t size;
@@ -8397,11 +8430,11 @@ static int cmd_cbi(int argc, char *argv[])
 			size = strtol(argv[4], &e, 0);
 			if (tag == CBI_TAG_REWORK_ID) {
 				if ((e && *e) || size < 1 || size > 8 ||
-				     (size < 8 && val >= (1ull << size*8)))
+				    (size < 8 && val >= (1ull << size * 8)))
 					bad_size = 1;
 			} else {
 				if ((e && *e) || size < 1 || 4 < size ||
-						 val >= (1ull << size*8))
+				    val >= (1ull << size * 8))
 					bad_size = 1;
 			}
 			if (bad_size == 1) {
@@ -8427,11 +8460,12 @@ static int cmd_cbi(int argc, char *argv[])
 				return -1;
 			}
 		}
-		rv = ec_command(EC_CMD_SET_CROS_BOARD_INFO, 0,
-				p, sizeof(*p) + size, NULL, 0);
+		rv = ec_command(EC_CMD_SET_CROS_BOARD_INFO, 0, p,
+				sizeof(*p) + size, NULL, 0);
 		if (rv < 0) {
 			if (rv == -EC_RES_ACCESS_DENIED - EECRESULT)
-				fprintf(stderr, "Write-protect is enabled or "
+				fprintf(stderr,
+					"Write-protect is enabled or "
 					"EC explicitly refused to change the "
 					"requested field.\n");
 			else
@@ -8451,11 +8485,12 @@ static int cmd_cbi(int argc, char *argv[])
 				return -1;
 			}
 		}
-		rv = ec_command(EC_CMD_SET_CROS_BOARD_INFO, 0,
-				&p, sizeof(p), NULL, 0);
+		rv = ec_command(EC_CMD_SET_CROS_BOARD_INFO, 0, &p, sizeof(p),
+				NULL, 0);
 		if (rv < 0) {
 			if (rv == -EC_RES_ACCESS_DENIED - EECRESULT)
-				fprintf(stderr, "Write-protect is enabled or "
+				fprintf(stderr,
+					"Write-protect is enabled or "
 					"EC explicitly refused to change the "
 					"requested field.\n");
 			else
@@ -8496,8 +8531,8 @@ int cmd_proto_info(int argc, char *argv[])
 
 	printf("Protocol info:\n");
 
-	rv = ec_command(EC_CMD_GET_PROTOCOL_INFO, 0, NULL, 0,
-			&info, sizeof(info));
+	rv = ec_command(EC_CMD_GET_PROTOCOL_INFO, 0, NULL, 0, &info,
+			sizeof(info));
 	if (rv < 0) {
 		fprintf(stderr, "Protocol info unavailable.  EC probably only "
 				"supports protocol version 2.\n");
@@ -8533,7 +8568,6 @@ static int ec_hash_help(const char *cmd)
 	return 0;
 }
 
-
 static int ec_hash_print(const struct ec_response_vboot_hash *r)
 {
 	int i;
@@ -8565,7 +8599,6 @@ static int ec_hash_print(const struct ec_response_vboot_hash *r)
 	return 0;
 }
 
-
 int cmd_ec_hash(int argc, char *argv[])
 {
 	struct ec_params_vboot_hash p;
@@ -8577,8 +8610,8 @@ int cmd_ec_hash(int argc, char *argv[])
 	if (argc < 2) {
 		/* Get hash status */
 		p.cmd = EC_VBOOT_HASH_GET;
-		rv = ec_command(EC_CMD_VBOOT_HASH, 0,
-				&p, sizeof(p), &r, sizeof(r));
+		rv = ec_command(EC_CMD_VBOOT_HASH, 0, &p, sizeof(p), &r,
+				sizeof(r));
 		if (rv < 0)
 			return rv;
 
@@ -8588,8 +8621,8 @@ int cmd_ec_hash(int argc, char *argv[])
 	if (argc == 2 && !strcasecmp(argv[1], "abort")) {
 		/* Abort hash calculation */
 		p.cmd = EC_VBOOT_HASH_ABORT;
-		rv = ec_command(EC_CMD_VBOOT_HASH, 0,
-				&p, sizeof(p), &r, sizeof(r));
+		rv = ec_command(EC_CMD_VBOOT_HASH, 0, &p, sizeof(p), &r,
+				sizeof(r));
 		return (rv < 0 ? rv : 0);
 	}
 
@@ -8660,7 +8693,6 @@ int cmd_ec_hash(int argc, char *argv[])
 	return ec_hash_print(&r);
 }
 
-
 int cmd_rtc_get(int argc, char *argv[])
 {
 	struct ec_response_rtc r;
@@ -8674,7 +8706,6 @@ int cmd_rtc_get(int argc, char *argv[])
 	return 0;
 }
 
-
 int cmd_rtc_set(int argc, char *argv[])
 {
 	struct ec_params_rtc p;
@@ -8754,8 +8785,8 @@ int cmd_console(int argc, char *argv[])
 
 	/* Loop and read from the snapshot until it's done */
 	while (1) {
-		rv = ec_command(EC_CMD_CONSOLE_READ, 0,
-				NULL, 0, ec_inbuf, ec_max_insize);
+		rv = ec_command(EC_CMD_CONSOLE_READ, 0, NULL, 0, ec_inbuf,
+				ec_max_insize);
 		if (rv < 0)
 			return rv;
 
@@ -8771,17 +8802,16 @@ int cmd_console(int argc, char *argv[])
 	return 0;
 }
 struct param_info {
-	const char *name;	/* name of this parameter */
-	const char *help;	/* help message */
-	int size;		/* size in bytes */
-	int offset;		/* offset within structure */
+	const char *name; /* name of this parameter */
+	const char *help; /* help message */
+	int size; /* size in bytes */
+	int offset; /* offset within structure */
 };
 
-#define FIELD(fname, field, help_str) \
-	{ \
-		.name = fname, \
-		.help = help_str, \
-		.size = sizeof(((struct ec_mkbp_config *)NULL)->field), \
+#define FIELD(fname, field, help_str)                                       \
+	{                                                                   \
+		.name = fname, .help = help_str,                            \
+		.size = sizeof(((struct ec_mkbp_config *)NULL)->field),     \
 		.offset = __builtin_offsetof(struct ec_mkbp_config, field), \
 	}
 
@@ -8802,7 +8832,8 @@ static const struct param_info keyconfig_params[] = {
 };
 
 static const struct param_info *find_field(const struct param_info *params,
-		int count, const char *name, unsigned int *nump)
+					   int count, const char *name,
+					   unsigned int *nump)
 {
 	const struct param_info *param;
 	int i;
@@ -8846,7 +8877,7 @@ static int show_fields(struct ec_mkbp_config *config, int argc, char *argv[])
 	int i;
 
 	if (!argc) {
-		mask = -1U;	/* show all fields */
+		mask = -1U; /* show all fields */
 	} else {
 		mask = 0;
 		while (argc > 0) {
@@ -8938,7 +8969,8 @@ static int cmd_keyconfig(int argc, char *argv[])
 		const struct param_info *param;
 		int i;
 
-		fprintf(stderr, "Usage: %s get [<param>] - print params\n"
+		fprintf(stderr,
+			"Usage: %s get [<param>] - print params\n"
 			"\t%s set [<param>> <value>]\n"
 			"   Available params are: (all time values are in us)",
 			argv[0], argv[0]);
@@ -8974,14 +9006,14 @@ static int cmd_keyconfig(int argc, char *argv[])
 	return 0;
 }
 
-static const char * const mkbp_button_strings[] = {
+static const char *const mkbp_button_strings[] = {
 	[EC_MKBP_POWER_BUTTON] = "Power",
 	[EC_MKBP_VOL_UP] = "Volume up",
 	[EC_MKBP_VOL_DOWN] = "Volume down",
 	[EC_MKBP_RECOVERY] = "Recovery",
 };
 
-static const char * const mkbp_switch_strings[] = {
+static const char *const mkbp_switch_strings[] = {
 	[EC_MKBP_LID_OPEN] = "Lid open",
 	[EC_MKBP_TABLET_MODE] = "Tablet mode",
 	[EC_MKBP_BASE_ATTACHED] = "Base attached",
@@ -9010,8 +9042,7 @@ static int cmd_mkbp_get(int argc, char *argv[])
 	}
 
 	p.info_type = EC_MKBP_INFO_SUPPORTED;
-	rv = ec_command(EC_CMD_MKBP_INFO, 0, &p, sizeof(p), &r,
-			sizeof(r));
+	rv = ec_command(EC_CMD_MKBP_INFO, 0, &p, sizeof(p), &r, sizeof(r));
 	if (rv < 0)
 		return rv;
 	if (p.event_type == EC_MKBP_EVENT_BUTTON)
@@ -9022,8 +9053,7 @@ static int cmd_mkbp_get(int argc, char *argv[])
 		return -1;
 
 	p.info_type = EC_MKBP_INFO_CURRENT;
-	rv = ec_command(EC_CMD_MKBP_INFO, 0, &p, sizeof(p), &r,
-			sizeof(r));
+	rv = ec_command(EC_CMD_MKBP_INFO, 0, &p, sizeof(p), &r, sizeof(r));
 	if (rv < 0)
 		return rv;
 
@@ -9063,9 +9093,10 @@ static int cmd_mkbp_wake_mask(int argc, char *argv[])
 	int rv;
 
 	if (argc < 3) {
-		fprintf(stderr, "Usage: %s get <event|hostevent>\n"
-			"\t%s set <event|hostevent> <mask>\n", argv[0],
-			argv[0]);
+		fprintf(stderr,
+			"Usage: %s get <event|hostevent>\n"
+			"\t%s set <event|hostevent> <mask>\n",
+			argv[0], argv[0]);
 		return -1;
 	}
 
@@ -9104,15 +9135,16 @@ static int cmd_mkbp_wake_mask(int argc, char *argv[])
 		}
 	}
 
-	rv = ec_command(EC_CMD_MKBP_WAKE_MASK, 0, &p, sizeof(p), &r,
-			sizeof(r));
+	rv = ec_command(EC_CMD_MKBP_WAKE_MASK, 0, &p, sizeof(p), &r, sizeof(r));
 	if (rv < 0) {
-		if (rv == -EECRESULT-EC_RES_INVALID_PARAM) {
-			fprintf(stderr, "Unknown mask, or mask is not in use.  "
+		if (rv == -EECRESULT - EC_RES_INVALID_PARAM) {
+			fprintf(stderr,
+				"Unknown mask, or mask is not in use.  "
 				"You may need to enable the "
-				"CONFIG_MKBP_%s_WAKEUP_MASK option in the EC.\n"
-				, p.mask_type == EC_MKBP_EVENT_WAKE_MASK ?
-				"EVENT" : "HOSTEVENT");
+				"CONFIG_MKBP_%s_WAKEUP_MASK option in the EC.\n",
+				p.mask_type == EC_MKBP_EVENT_WAKE_MASK ?
+					"EVENT" :
+					"HOSTEVENT");
 		}
 		return rv;
 	}
@@ -9137,8 +9169,8 @@ static int cmd_tmp006cal_v0(int idx, int argc, char *argv[])
 
 	/* Get current values */
 	pg.index = idx;
-	rv = ec_command(EC_CMD_TMP006_GET_CALIBRATION, 0,
-			&pg, sizeof(pg), &rg, sizeof(rg));
+	rv = ec_command(EC_CMD_TMP006_GET_CALIBRATION, 0, &pg, sizeof(pg), &rg,
+			sizeof(rg));
 	if (rv < 0)
 		return rv;
 
@@ -9187,8 +9219,8 @@ static int cmd_tmp006cal_v0(int idx, int argc, char *argv[])
 	}
 
 	/* Set 'em */
-	return ec_command(EC_CMD_TMP006_SET_CALIBRATION, 0,
-			  &ps, sizeof(ps), NULL, 0);
+	return ec_command(EC_CMD_TMP006_SET_CALIBRATION, 0, &ps, sizeof(ps),
+			  NULL, 0);
 }
 
 /* Index is already checked. argv[0] is first param value */
@@ -9204,15 +9236,15 @@ static int cmd_tmp006cal_v1(int idx, int argc, char *argv[])
 	int i, rv, cmdsize;
 
 	/* Algorithm 1 parameter names */
-	static const char * const alg1_pname[] = {
-		"s0", "a1", "a2", "b0", "b1", "b2", "c2",
-		"d0", "d1", "ds", "e0", "e1",
+	static const char *const alg1_pname[] = {
+		"s0", "a1", "a2", "b0", "b1", "b2",
+		"c2", "d0", "d1", "ds", "e0", "e1",
 	};
 
 	/* Get current values */
 	pg.index = idx;
-	rv = ec_command(EC_CMD_TMP006_GET_CALIBRATION, 1,
-			&pg, sizeof(pg), rg, ec_max_insize);
+	rv = ec_command(EC_CMD_TMP006_GET_CALIBRATION, 1, &pg, sizeof(pg), rg,
+			ec_max_insize);
 	if (rv < 0)
 		return rv;
 
@@ -9254,8 +9286,8 @@ static int cmd_tmp006cal_v1(int idx, int argc, char *argv[])
 
 	/* Set 'em */
 	cmdsize = sizeof(*ps) + ps->num_params * sizeof(ps->val[0]);
-	return ec_command(EC_CMD_TMP006_SET_CALIBRATION, 1,
-			  ps, cmdsize, NULL, 0);
+	return ec_command(EC_CMD_TMP006_SET_CALIBRATION, 1, ps, cmdsize, NULL,
+			  0);
 }
 
 int cmd_tmp006cal(int argc, char *argv[])
@@ -9372,8 +9404,8 @@ static int cmd_hang_detect(int argc, char *argv[])
 }
 
 enum port_80_event {
-	PORT_80_EVENT_RESUME = 0x1001,  /* S3->S0 transition */
-	PORT_80_EVENT_RESET = 0x1002,   /* RESET transition */
+	PORT_80_EVENT_RESUME = 0x1001, /* S3->S0 transition */
+	PORT_80_EVENT_RESET = 0x1002, /* RESET transition */
 };
 
 int cmd_port80_read(int argc, char *argv[])
@@ -9389,18 +9421,17 @@ int cmd_port80_read(int argc, char *argv[])
 	if (!ec_cmd_version_supported(EC_CMD_PORT80_READ, cmdver)) {
 		/* fall back to last boot */
 		struct ec_response_port80_last_boot r;
-		rv = ec_command(EC_CMD_PORT80_LAST_BOOT, 0,
-				NULL, 0, &r, sizeof(r));
+		rv = ec_command(EC_CMD_PORT80_LAST_BOOT, 0, NULL, 0, &r,
+				sizeof(r));
 		fprintf(stderr, "Last boot %2x\n", r.code);
 		printf("done.\n");
 		return 0;
 	}
 
-
 	/* read writes and history_size */
 	p.subcmd = EC_PORT80_GET_INFO;
-	rv = ec_command(EC_CMD_PORT80_READ, cmdver,
-			&p, sizeof(p), &rsp, sizeof(rsp));
+	rv = ec_command(EC_CMD_PORT80_READ, cmdver, &p, sizeof(p), &rsp,
+			sizeof(rsp));
 	if (rv < 0) {
 		fprintf(stderr, "Read error at writes\n");
 		return rv;
@@ -9408,8 +9439,7 @@ int cmd_port80_read(int argc, char *argv[])
 	writes = rsp.get_info.writes;
 	history_size = rsp.get_info.history_size;
 
-	history = (uint16_t *)(
-		malloc(history_size * sizeof(uint16_t)));
+	history = (uint16_t *)(malloc(history_size * sizeof(uint16_t)));
 	if (!history) {
 		fprintf(stderr, "Unable to allocate buffer.\n");
 		return -1;
@@ -9427,15 +9457,15 @@ int cmd_port80_read(int argc, char *argv[])
 	for (i = 0; i < history_size; i += EC_PORT80_SIZE_MAX) {
 		p.read_buffer.offset = i;
 		p.read_buffer.num_entries = EC_PORT80_SIZE_MAX;
-		rv = ec_command(EC_CMD_PORT80_READ, cmdver,
-				&p, sizeof(p), &rsp, sizeof(rsp));
+		rv = ec_command(EC_CMD_PORT80_READ, cmdver, &p, sizeof(p), &rsp,
+				sizeof(rsp));
 		if (rv < 0) {
 			fprintf(stderr, "Read error at offset %d\n", i);
 			free(history);
 			return rv;
 		}
 		memcpy((void *)(history + i), rsp.data.codes,
-			EC_PORT80_SIZE_MAX*sizeof(uint16_t));
+		       EC_PORT80_SIZE_MAX * sizeof(uint16_t));
 	}
 
 	head = writes;
@@ -9516,8 +9546,8 @@ int cmd_charge_port_override(int argc, char *argv[])
 		}
 	}
 
-	rv = ec_command(EC_CMD_PD_CHARGE_PORT_OVERRIDE, 0, &p, sizeof(p),
-			NULL, 0);
+	rv = ec_command(EC_CMD_PD_CHARGE_PORT_OVERRIDE, 0, &p, sizeof(p), NULL,
+			0);
 	if (rv < 0)
 		return rv;
 
@@ -9528,28 +9558,30 @@ int cmd_charge_port_override(int argc, char *argv[])
 static void cmd_pchg_help(char *cmd)
 {
 	fprintf(stderr,
-	"  Usage1: %s\n"
-	"          Print the number of ports.\n"
-	"\n"
-	"  Usage2: %s <port>\n"
-	"          Print the status of <port>.\n"
-	"\n"
-	"  Usage3: %s <port> reset\n"
-	"          Reset <port>.\n"
-	"\n"
-	"  Usage4: %s <port> update <version> <addr1> <file1> <addr2> <file2> ...\n"
-	"          Update firmware of <port>.\n",
-	cmd, cmd, cmd, cmd);
+		"  Usage1: %s\n"
+		"          Print the number of ports.\n"
+		"\n"
+		"  Usage2: %s <port>\n"
+		"          Print the status of <port>.\n"
+		"\n"
+		"  Usage3: %s <port> reset\n"
+		"          Reset <port>.\n"
+		"\n"
+		"  Usage4: %s <port> update <version> <addr1> <file1> <addr2> <file2> ...\n"
+		"          Update firmware of <port>.\n",
+		cmd, cmd, cmd, cmd);
 }
 
 static int cmd_pchg_info(const struct ec_response_pchg *res)
 {
-	static const char * const pchg_state_text[] = EC_PCHG_STATE_TEXT;
+	static const char *const pchg_state_text[] = EC_PCHG_STATE_TEXT;
 
 	BUILD_ASSERT(ARRAY_SIZE(pchg_state_text) == PCHG_STATE_COUNT);
 
-	printf("State: %s (%d)\n", res->state < PCHG_STATE_COUNT
-	       ? pchg_state_text[res->state] : "UNDEF", res->state);
+	printf("State: %s (%d)\n",
+	       res->state < PCHG_STATE_COUNT ? pchg_state_text[res->state] :
+					       "UNDEF",
+	       res->state);
 	printf("Battery: %u%%\n", res->battery_percentage);
 	printf("Errors: 0x%x\n", res->error);
 	printf("FW Version: 0x%x\n", res->fw_version);
@@ -9577,8 +9609,8 @@ static int cmd_pchg_wait_event(int port, uint32_t expected)
 			return 0;
 	}
 
-	fprintf(stderr, "\nExpected event=0x%x but received 0x%x\n",
-		expected, *e);
+	fprintf(stderr, "\nExpected event=0x%x but received 0x%x\n", expected,
+		*e);
 	return -1;
 }
 
@@ -9617,8 +9649,8 @@ static int cmd_pchg_update_open(int port, uint32_t version,
 	rv = ec_command(EC_CMD_PCHG, 2, &p, sizeof(p), &rv2, sizeof(rv2));
 	if (rv == -EC_RES_INVALID_VERSION - EECRESULT)
 		/* We can use v2 because it's a superset of v1. */
-		rv = ec_command(EC_CMD_PCHG, 1, &p, sizeof(p),
-				&rv2, sizeof(struct ec_response_pchg));
+		rv = ec_command(EC_CMD_PCHG, 1, &p, sizeof(p), &rv2,
+				sizeof(struct ec_response_pchg));
 	if (rv < 0) {
 		fprintf(stderr, "EC_CMD_PCHG failed: %d\n", rv);
 		return rv;
@@ -9632,8 +9664,8 @@ static int cmd_pchg_update_open(int port, uint32_t version,
 	if (rv)
 		return rv;
 
-	printf("Opened update session (port=%d ver=0x%x bsize=%d):\n",
-	       port, version, r->block_size);
+	printf("Opened update session (port=%d ver=0x%x bsize=%d):\n", port,
+	       version, r->block_size);
 
 	*block_size = r->block_size;
 	crc32_ctx_init(crc);
@@ -9654,8 +9686,8 @@ static int cmd_pchg_update_write(int port, uint32_t address,
 
 	fp = fopen(filename, "rb");
 	if (!fp) {
-		fprintf(stderr, "\nCan't open %s: %s\n",
-			filename, strerror(errno));
+		fprintf(stderr, "\nCan't open %s: %s\n", filename,
+			strerror(errno));
 		return -1;
 	}
 
@@ -9675,8 +9707,8 @@ static int cmd_pchg_update_write(int port, uint32_t address,
 
 		crc32_ctx_hash(crc, p->data, len);
 		p->size = len;
-		rv = ec_command(EC_CMD_PCHG_UPDATE, 0, p,
-				sizeof(*p) + len, NULL, 0);
+		rv = ec_command(EC_CMD_PCHG_UPDATE, 0, p, sizeof(*p) + len,
+				NULL, 0);
 		if (rv < 0) {
 			fprintf(stderr, "\nFailed to write FW: %d\n", rv);
 			fclose(fp);
@@ -9775,8 +9807,8 @@ static int cmd_pchg(int argc, char *argv[])
 		u->cmd = EC_PCHG_UPDATE_CMD_RESET_TO_NORMAL;
 		rv = ec_command(EC_CMD_PCHG_UPDATE, 0, u, sizeof(*u), NULL, 0);
 		if (rv < 0) {
-			fprintf(stderr, "\nFailed to reset port %d: %d\n",
-				port, rv);
+			fprintf(stderr, "\nFailed to reset port %d: %d\n", port,
+				rv);
 			cmd_pchg_help(argv[0]);
 			return rv;
 		}
@@ -9824,12 +9856,12 @@ static int cmd_pchg(int argc, char *argv[])
 				cmd_pchg_help(argv[0]);
 				return -1;
 			}
-			rv = cmd_pchg_update_write(port, address, argv[i+1],
+			rv = cmd_pchg_update_write(port, address, argv[i + 1],
 						   block_size, &crc);
 			if (rv < 0) {
 				fprintf(stderr,
 					"\nFailed to write file '%s': %d",
-					argv[i+i], rv);
+					argv[i + i], rv);
 				return -1;
 			}
 		}
@@ -9867,8 +9899,8 @@ int cmd_pd_log(int argc, char *argv[])
 
 	while (1) {
 		now = time(NULL);
-		rv = ec_command(EC_CMD_PD_GET_LOG_ENTRY, 0,
-				NULL, 0, &u, sizeof(u));
+		rv = ec_command(EC_CMD_PD_GET_LOG_ENTRY, 0, NULL, 0, &u,
+				sizeof(u));
 		if (rv < 0)
 			return rv;
 
@@ -9878,8 +9910,9 @@ int cmd_pd_log(int argc, char *argv[])
 		}
 
 		/* the timestamp is in 1024th of seconds */
-		milliseconds = ((uint64_t)u.r.timestamp <<
-					 PD_LOG_TIMESTAMP_SHIFT) / 1000;
+		milliseconds =
+			((uint64_t)u.r.timestamp << PD_LOG_TIMESTAMP_SHIFT) /
+			1000;
 		/* the timestamp is the number of milliseconds in the past */
 		seconds = (milliseconds + 999) / 1000;
 		milliseconds -= seconds * 1000;
@@ -9887,18 +9920,18 @@ int cmd_pd_log(int argc, char *argv[])
 		localtime_r(&now, &ltime);
 		strftime(time_str, sizeof(time_str), "%F %T", &ltime);
 		printf("%s.%03lld P%d ", time_str, -milliseconds,
-			PD_LOG_PORT(u.r.size_port));
+		       PD_LOG_PORT(u.r.size_port));
 		if (u.r.type == PD_EVENT_MCU_CHARGE) {
 			if (u.r.data & CHARGE_FLAGS_OVERRIDE)
 				printf("override ");
 			if (u.r.data & CHARGE_FLAGS_DELAYED_OVERRIDE)
 				printf("pending_override ");
 			memcpy(&pinfo.meas, u.r.payload,
-				sizeof(struct usb_chg_measures));
+			       sizeof(struct usb_chg_measures));
 			pinfo.dualrole = !!(u.r.data & CHARGE_FLAGS_DUAL_ROLE);
 			pinfo.role = u.r.data & CHARGE_FLAGS_ROLE_MASK;
-			pinfo.type = (u.r.data & CHARGE_FLAGS_TYPE_MASK)
-					>> CHARGE_FLAGS_TYPE_SHIFT;
+			pinfo.type = (u.r.data & CHARGE_FLAGS_TYPE_MASK) >>
+				     CHARGE_FLAGS_TYPE_SHIFT;
 			pinfo.max_power = 0;
 			print_pd_power_info(&pinfo);
 		} else if (u.r.type == PD_EVENT_MCU_CONNECT) {
@@ -9908,25 +9941,24 @@ int cmd_pd_log(int argc, char *argv[])
 		} else if (u.r.type == PD_EVENT_ACC_RW_FAIL) {
 			printf("RW signature check failed\n");
 		} else if (u.r.type == PD_EVENT_PS_FAULT) {
-			static const char * const fault_names[] = {
+			static const char *const fault_names[] = {
 				"---", "OCP", "fast OCP", "OVP", "Discharge"
 			};
 			const char *fault = u.r.data < ARRAY_SIZE(fault_names) ?
-					fault_names[u.r.data] : "???";
+						    fault_names[u.r.data] :
+						    "???";
 			printf("Power supply fault: %s\n", fault);
 		} else if (u.r.type == PD_EVENT_VIDEO_DP_MODE) {
-			printf("DP mode %sabled\n", (u.r.data == 1) ?
-			       "en" : "dis");
+			printf("DP mode %sabled\n",
+			       (u.r.data == 1) ? "en" : "dis");
 		} else if (u.r.type == PD_EVENT_VIDEO_CODEC) {
-			memcpy(&minfo, u.r.payload,
-			       sizeof(struct mcdp_info));
+			memcpy(&minfo, u.r.payload, sizeof(struct mcdp_info));
 			printf("HDMI info: family:%04x chipid:%04x "
 			       "irom:%d.%d.%d fw:%d.%d.%d\n",
 			       MCDP_FAMILY(minfo.family),
-			       MCDP_CHIPID(minfo.chipid),
-			       minfo.irom.major, minfo.irom.minor,
-			       minfo.irom.build, minfo.fw.major,
-			       minfo.fw.minor, minfo.fw.build);
+			       MCDP_CHIPID(minfo.chipid), minfo.irom.major,
+			       minfo.irom.minor, minfo.irom.build,
+			       minfo.fw.major, minfo.fw.minor, minfo.fw.build);
 		} else { /* Unknown type */
 			int i;
 			printf("Event %02x (%04x) [", u.r.type, u.r.data);
@@ -9989,7 +10021,8 @@ int cmd_pd_chip_info(int argc, char *argv[])
 	int cmdver = 1;
 
 	if (argc < 2 || 3 < argc) {
-		fprintf(stderr, "Usage: %s <port> [<live>]\n"
+		fprintf(stderr,
+			"Usage: %s <port> [<live>]\n"
 			"live parameter can take values 0 or 1\n"
 			"0 -> Return hard-coded value for VID/PID and\n"
 			"     cached value for Firmware Version\n"
@@ -10045,8 +10078,7 @@ int cmd_pd_write_log(int argc, char *argv[])
 	char *e;
 
 	if (argc < 3) {
-		fprintf(stderr, "Usage: %s <log_type> <port>\n",
-			argv[0]);
+		fprintf(stderr, "Usage: %s <log_type> <port>\n", argv[0]);
 		return -1;
 	}
 
@@ -10129,7 +10161,7 @@ int cmd_typec_control(int argc, char *argv[])
 
 		conversion_result = strtol(argv[3], &endptr, 0);
 		if ((endptr && *endptr) || conversion_result > UINT8_MAX ||
-				conversion_result < 0) {
+		    conversion_result < 0) {
 			fprintf(stderr, "Bad mode\n");
 			return -1;
 		}
@@ -10143,7 +10175,7 @@ int cmd_typec_control(int argc, char *argv[])
 
 		conversion_result = strtol(argv[3], &endptr, 0);
 		if ((endptr && *endptr) || conversion_result > UINT8_MAX ||
-						conversion_result < 0) {
+		    conversion_result < 0) {
 			fprintf(stderr, "Bad reply\n");
 			return -1;
 		}
@@ -10157,7 +10189,7 @@ int cmd_typec_control(int argc, char *argv[])
 
 		conversion_result = strtol(argv[3], &endptr, 0);
 		if ((endptr && *endptr) || conversion_result > UINT8_MAX ||
-						conversion_result < 0) {
+		    conversion_result < 0) {
 			fprintf(stderr, "Bad index\n");
 			return -1;
 		}
@@ -10183,8 +10215,8 @@ int cmd_typec_control(int argc, char *argv[])
 		break;
 	}
 
-	rv = ec_command(EC_CMD_TYPEC_CONTROL, 0, &p, sizeof(p),
-			ec_inbuf, ec_max_insize);
+	rv = ec_command(EC_CMD_TYPEC_CONTROL, 0, &p, sizeof(p), ec_inbuf,
+			ec_max_insize);
 	if (rv < 0)
 		return -1;
 
@@ -10195,7 +10227,7 @@ int cmd_typec_discovery(int argc, char *argv[])
 {
 	struct ec_params_typec_discovery p;
 	struct ec_response_typec_discovery *r =
-				(struct ec_response_typec_discovery *)ec_inbuf;
+		(struct ec_response_typec_discovery *)ec_inbuf;
 	char *e;
 	int rv, i, j;
 
@@ -10205,7 +10237,8 @@ int cmd_typec_discovery(int argc, char *argv[])
 			"  <port> is the type-c port to query\n"
 			"  <type> is one of:\n"
 			"    0: SOP\n"
-			"    1: SOP prime\n", argv[0]);
+			"    1: SOP prime\n",
+			argv[0]);
 		return -1;
 	}
 
@@ -10221,8 +10254,8 @@ int cmd_typec_discovery(int argc, char *argv[])
 		return -1;
 	}
 
-	rv = ec_command(EC_CMD_TYPEC_DISCOVERY, 0, &p, sizeof(p),
-			ec_inbuf, ec_max_insize);
+	rv = ec_command(EC_CMD_TYPEC_DISCOVERY, 0, &p, sizeof(p), ec_inbuf,
+			ec_max_insize);
 	if (rv < 0)
 		return -1;
 
@@ -10252,10 +10285,8 @@ int cmd_typec_discovery(int argc, char *argv[])
 /* Print shared fields of sink and source cap PDOs */
 static inline void print_pdo_fixed(uint32_t pdo)
 {
-	printf("    Fixed: %dmV %dmA %s%s%s%s",
-	       PDO_FIXED_VOLTAGE(pdo),
-	       PDO_FIXED_CURRENT(pdo),
-	       pdo & PDO_FIXED_DUAL_ROLE ? "DRP " : "",
+	printf("    Fixed: %dmV %dmA %s%s%s%s", PDO_FIXED_VOLTAGE(pdo),
+	       PDO_FIXED_CURRENT(pdo), pdo & PDO_FIXED_DUAL_ROLE ? "DRP " : "",
 	       pdo & PDO_FIXED_UNCONSTRAINED ? "UP " : "",
 	       pdo & PDO_FIXED_COMM_CAP ? "USB " : "",
 	       pdo & PDO_FIXED_DATA_SWAP ? "DRD" : "");
@@ -10264,24 +10295,21 @@ static inline void print_pdo_fixed(uint32_t pdo)
 static inline void print_pdo_battery(uint32_t pdo)
 {
 	printf("    Battery: max %dmV min %dmV max %dmW\n",
-	       PDO_BATT_MAX_VOLTAGE(pdo),
-	       PDO_BATT_MIN_VOLTAGE(pdo),
+	       PDO_BATT_MAX_VOLTAGE(pdo), PDO_BATT_MIN_VOLTAGE(pdo),
 	       PDO_BATT_MAX_POWER(pdo));
 }
 
 static inline void print_pdo_variable(uint32_t pdo)
 {
 	printf("    Variable: max %dmV min %dmV max %dmA\n",
-	       PDO_VAR_MAX_VOLTAGE(pdo),
-	       PDO_VAR_MIN_VOLTAGE(pdo),
+	       PDO_VAR_MAX_VOLTAGE(pdo), PDO_VAR_MIN_VOLTAGE(pdo),
 	       PDO_VAR_MAX_CURRENT(pdo));
 }
 
 static inline void print_pdo_augmented(uint32_t pdo)
 {
 	printf("    Augmented: max %dmV min %dmV max %dmA\n",
-	       PDO_AUG_MAX_VOLTAGE(pdo),
-	       PDO_AUG_MIN_VOLTAGE(pdo),
+	       PDO_AUG_MAX_VOLTAGE(pdo), PDO_AUG_MIN_VOLTAGE(pdo),
 	       PDO_AUG_MAX_CURRENT(pdo));
 }
 
@@ -10289,7 +10317,7 @@ int cmd_typec_status(int argc, char *argv[])
 {
 	struct ec_params_typec_status p;
 	struct ec_response_typec_status *r =
-				(struct ec_response_typec_status *)ec_inbuf;
+		(struct ec_response_typec_status *)ec_inbuf;
 	char *endptr;
 	int rv, i;
 	const char *desc;
@@ -10297,7 +10325,8 @@ int cmd_typec_status(int argc, char *argv[])
 	if (argc != 2) {
 		fprintf(stderr,
 			"Usage: %s <port>\n"
-			"  <port> is the type-c port to query\n", argv[0]);
+			"  <port> is the type-c port to query\n",
+			argv[0]);
 		return -1;
 	}
 
@@ -10307,8 +10336,8 @@ int cmd_typec_status(int argc, char *argv[])
 		return -1;
 	}
 
-	rv = ec_command(EC_CMD_TYPEC_STATUS, 0, &p, sizeof(p),
-			ec_inbuf, ec_max_insize);
+	rv = ec_command(EC_CMD_TYPEC_STATUS, 0, &p, sizeof(p), ec_inbuf,
+			ec_max_insize);
 	if (rv == -EC_RES_INVALID_COMMAND - EECRESULT)
 		/* Fall back to PD_CONTROL to support older ECs */
 		return cmd_usb_pd(argc, argv);
@@ -10317,15 +10346,14 @@ int cmd_typec_status(int argc, char *argv[])
 
 	printf("Port C%d: %s, %s  State:%s\n"
 	       "Role:%s %s%s, Polarity:CC%d\n",
-		p.port,
-		r->pd_enabled ? "enabled" : "disabled",
-		r->dev_connected ? "connected" : "disconnected",
-		r->tc_state,
-		(r->power_role == PD_ROLE_SOURCE) ? "SRC" : "SNK",
-		(r->data_role == PD_ROLE_DFP) ? "DFP" :
-			(r->data_role == PD_ROLE_UFP) ? "UFP" : "",
-		(r->vconn_role == PD_ROLE_VCONN_SRC) ? " VCONN" : "",
-		(r->polarity % 2 + 1));
+	       p.port, r->pd_enabled ? "enabled" : "disabled",
+	       r->dev_connected ? "connected" : "disconnected", r->tc_state,
+	       (r->power_role == PD_ROLE_SOURCE) ? "SRC" : "SNK",
+	       (r->data_role == PD_ROLE_DFP) ? "DFP" :
+	       (r->data_role == PD_ROLE_UFP) ? "UFP" :
+					       "",
+	       (r->vconn_role == PD_ROLE_VCONN_SRC) ? " VCONN" : "",
+	       (r->polarity % 2 + 1));
 
 	switch (r->cc_state) {
 	case PD_CC_NONE:
@@ -10384,8 +10412,9 @@ int cmd_typec_status(int argc, char *argv[])
 		       "     SAFE=%d TBT=%d USB4=%d\n",
 		       !!(r->mux_state & USB_PD_MUX_USB_ENABLED),
 		       !!(r->mux_state & USB_PD_MUX_DP_ENABLED),
-			(r->mux_state & USB_PD_MUX_POLARITY_INVERTED) ?
-						"INVERTED" : "NORMAL",
+		       (r->mux_state & USB_PD_MUX_POLARITY_INVERTED) ?
+			       "INVERTED" :
+			       "NORMAL",
 		       !!(r->mux_state & USB_PD_MUX_HPD_IRQ),
 		       !!(r->mux_state & USB_PD_MUX_HPD_LVL),
 		       !!(r->mux_state & USB_PD_MUX_SAFE_MODE),
@@ -10444,8 +10473,8 @@ int cmd_typec_status(int argc, char *argv[])
 		if (pdo_type == PDO_TYPE_FIXED) {
 			print_pdo_fixed(pdo);
 			/* Note: FRS bits are reserved in PD 2.0 spec */
-			printf("%s\n", pdo & PDO_FIXED_FRS_CURR_MASK ?
-			       "FRS" : "");
+			printf("%s\n",
+			       pdo & PDO_FIXED_FRS_CURR_MASK ? "FRS" : "");
 		} else if (pdo_type == PDO_TYPE_BATTERY) {
 			print_pdo_battery(pdo);
 		} else if (pdo_type == PDO_TYPE_VARIABLE) {
@@ -10458,7 +10487,7 @@ int cmd_typec_status(int argc, char *argv[])
 	return 0;
 }
 
-int cmd_tp_self_test(int argc, char* argv[])
+int cmd_tp_self_test(int argc, char *argv[])
 {
 	int rv;
 
@@ -10472,13 +10501,13 @@ int cmd_tp_self_test(int argc, char* argv[])
 	return rv;
 }
 
-int cmd_tp_frame_get(int argc, char* argv[])
+int cmd_tp_frame_get(int argc, char *argv[])
 {
 	int i, j;
 	uint32_t remaining = 0, offset = 0;
 	int rv = EC_SUCCESS;
 	uint8_t *data;
-	struct ec_response_tp_frame_info* r;
+	struct ec_response_tp_frame_info *r;
 	struct ec_params_tp_frame_get p;
 
 	data = (uint8_t *)(malloc(ec_max_insize));
@@ -10512,11 +10541,13 @@ int cmd_tp_frame_get(int argc, char* argv[])
 			p.offset = offset;
 			p.size = MIN(remaining, ec_max_insize);
 
-			rv = ec_command(EC_CMD_TP_FRAME_GET, 0,
-					&p, sizeof(p), data, p.size);
+			rv = ec_command(EC_CMD_TP_FRAME_GET, 0, &p, sizeof(p),
+					data, p.size);
 			if (rv < 0) {
-				fprintf(stderr, "Failed to get frame data "
-						"at offset 0x%x\n", offset);
+				fprintf(stderr,
+					"Failed to get frame data "
+					"at offset 0x%x\n",
+					offset);
 				goto err;
 			}
 
@@ -10538,25 +10569,41 @@ err:
 
 int cmd_wait_event(int argc, char *argv[])
 {
+	static const char *const mkbp_event_text[] = EC_MKBP_EVENT_TEXT;
+	static const char *const host_event_text[] = HOST_EVENT_TEXT;
+
 	int rv, i;
 	struct ec_response_get_next_event_v1 buffer;
 	long timeout = 5000;
 	long event_type;
 	char *e;
 
+	BUILD_ASSERT(ARRAY_SIZE(mkbp_event_text) == EC_MKBP_EVENT_COUNT);
+	BUILD_ASSERT(ARRAY_SIZE(host_event_text) == 33); /* events start at 1 */
+
 	if (!ec_pollevent) {
 		fprintf(stderr, "Polling for MKBP event not supported\n");
 		return -EINVAL;
 	}
 
 	if (argc < 2) {
-		fprintf(stderr, "Usage: %s <type> [<timeout>]\n",
-			argv[0]);
+		fprintf(stderr, "Usage: %s <type> [<timeout>]\n", argv[0]);
+		fprintf(stderr, "\n");
+		fprintf(stderr, "type: MKBP event number or name.\n");
+		for (int i = 0; i < ARRAY_SIZE(mkbp_event_text); i++) {
+			const char *name = mkbp_event_text[i];
+
+			if (name) {
+				fprintf(stderr, "      %s or %d\n", name, i);
+			}
+		}
+
 		return -1;
 	}
 
-	event_type = strtol(argv[1], &e, 0);
-	if ((e && *e) || event_type < 0 || event_type >= EC_MKBP_EVENT_COUNT) {
+	rv = find_enum_from_text(argv[1], mkbp_event_text,
+				 ARRAY_SIZE(mkbp_event_text), &event_type);
+	if (rv < 0 || event_type < 0 || event_type >= EC_MKBP_EVENT_COUNT) {
 		fprintf(stderr, "Bad event type '%s'.\n", argv[1]);
 		return -1;
 	}
@@ -10577,6 +10624,20 @@ int cmd_wait_event(int argc, char *argv[])
 		printf("%02x ", buffer.data.key_matrix[i]);
 	printf("\n");
 
+	switch (event_type) {
+	case EC_MKBP_EVENT_HOST_EVENT:
+		printf("Host events:");
+		for (int evt = 1; evt <= 32; evt++) {
+			if (buffer.data.host_event & EC_HOST_EVENT_MASK(evt)) {
+				const char *name = host_event_text[evt];
+
+				printf(" %s", name ? name : "UNKNOWN");
+			}
+		}
+		printf("\n");
+		break;
+	}
+
 	return 0;
 }
 
@@ -10595,7 +10656,6 @@ static void cmd_cec_help(const char *cmd)
 		"      enable: Enable or disable CEC\n"
 		"        <val> is 1 to enable, 0 to disable\n",
 		cmd, cmd, cmd, cmd);
-
 }
 
 static int cmd_cec_write(int argc, char *argv[])
@@ -10668,8 +10728,8 @@ static int cmd_cec_read(int argc, char *argv[])
 		}
 	}
 
-	rv = wait_event(EC_MKBP_EVENT_CEC_MESSAGE, &buffer,
-			sizeof(buffer), timeout);
+	rv = wait_event(EC_MKBP_EVENT_CEC_MESSAGE, &buffer, sizeof(buffer),
+			timeout);
 	if (rv < 0)
 		return rv;
 
@@ -10717,18 +10777,15 @@ static int cmd_cec_set(int argc, char *argv[])
 	p.cmd = cmd;
 	p.val = val;
 
-	return ec_command(EC_CMD_CEC_SET,
-			  0, &p, sizeof(p), NULL, 0);
+	return ec_command(EC_CMD_CEC_SET, 0, &p, sizeof(p), NULL, 0);
 }
 
-
 static int cmd_cec_get(int argc, char *argv[])
 {
 	int rv, cmd;
 	struct ec_params_cec_get p;
 	struct ec_response_cec_get r;
 
-
 	if (argc != 3) {
 		fprintf(stderr, "Invalid number of params\n");
 		cmd_cec_help(argv[0]);
@@ -10742,7 +10799,6 @@ static int cmd_cec_get(int argc, char *argv[])
 	}
 	p.cmd = cmd;
 
-
 	rv = ec_command(EC_CMD_CEC_GET, 0, &p, sizeof(p), &r, sizeof(r));
 	if (rv < 0)
 		return rv;
@@ -10776,150 +10832,150 @@ int cmd_cec(int argc, char *argv[])
 
 /* NULL-terminated list of commands */
 const struct command commands[] = {
-	{"adcread", cmd_adc_read},
-	{"addentropy", cmd_add_entropy},
-	{"apreset", cmd_apreset},
-	{"autofanctrl", cmd_thermal_auto_fan_ctrl},
-	{"backlight", cmd_lcd_backlight},
-	{"basestate", cmd_basestate},
-	{"battery", cmd_battery},
-	{"batterycutoff", cmd_battery_cut_off},
-	{"batteryparam", cmd_battery_vendor_param},
-	{"boardversion", cmd_board_version},
-	{"button", cmd_button},
-	{"cbi", cmd_cbi},
-	{"chargecurrentlimit", cmd_charge_current_limit},
-	{"chargecontrol", cmd_charge_control},
-	{"chargeoverride", cmd_charge_port_override},
-	{"chargesplash", cmd_chargesplash},
-	{"chargestate", cmd_charge_state},
-	{"chipinfo", cmd_chipinfo},
-	{"cmdversions", cmd_cmdversions},
-	{"console", cmd_console},
-	{"cec", cmd_cec},
-	{"echash", cmd_ec_hash},
-	{"eventclear", cmd_host_event_clear},
-	{"eventclearb", cmd_host_event_clear_b},
-	{"eventget", cmd_host_event_get_raw},
-	{"eventgetb", cmd_host_event_get_b},
-	{"eventgetscimask", cmd_host_event_get_sci_mask},
-	{"eventgetsmimask", cmd_host_event_get_smi_mask},
-	{"eventgetwakemask", cmd_host_event_get_wake_mask},
-	{"eventsetscimask", cmd_host_event_set_sci_mask},
-	{"eventsetsmimask", cmd_host_event_set_smi_mask},
-	{"eventsetwakemask", cmd_host_event_set_wake_mask},
-	{"extpwrlimit", cmd_ext_power_limit},
-	{"fanduty", cmd_fanduty},
-	{"flasherase", cmd_flash_erase},
-	{"flasheraseasync", cmd_flash_erase},
-	{"flashprotect", cmd_flash_protect},
-	{"flashread", cmd_flash_read},
-	{"flashwrite", cmd_flash_write},
-	{"flashinfo", cmd_flash_info},
-	{"flashspiinfo", cmd_flash_spi_info},
-	{"flashpd", cmd_flash_pd},
-	{"forcelidopen", cmd_force_lid_open},
-	{"fpcontext", cmd_fp_context},
-	{"fpencstatus", cmd_fp_enc_status},
-	{"fpframe", cmd_fp_frame},
-	{"fpinfo", cmd_fp_info},
-	{"fpmode", cmd_fp_mode},
-	{"fpseed", cmd_fp_seed},
-	{"fpstats", cmd_fp_stats},
-	{"fptemplate", cmd_fp_template},
-	{"gpioget", cmd_gpio_get},
-	{"gpioset", cmd_gpio_set},
-	{"hangdetect", cmd_hang_detect},
-	{"hello", cmd_hello},
-	{"hibdelay", cmd_hibdelay},
-	{"hostevent", cmd_hostevent},
-	{"hostsleepstate", cmd_hostsleepstate},
-	{"locatechip", cmd_locate_chip},
-	{"i2cprotect", cmd_i2c_protect},
-	{"i2cread", cmd_i2c_read},
-	{"i2cspeed", cmd_i2c_speed},
-	{"i2cwrite", cmd_i2c_write},
-	{"i2cxfer", cmd_i2c_xfer},
-	{"infopddev", cmd_pd_device_info},
-	{"inventory", cmd_inventory},
-	{"led", cmd_led},
-	{"lightbar", cmd_lightbar},
-	{"kbfactorytest", cmd_keyboard_factory_test},
-	{"kbid", cmd_kbid},
-	{"kbinfo", cmd_kbinfo},
-	{"kbpress", cmd_kbpress},
-	{"keyconfig", cmd_keyconfig},
-	{"keyscan", cmd_keyscan},
-	{"mkbpget", cmd_mkbp_get},
-	{"mkbpwakemask", cmd_mkbp_wake_mask},
-	{"motionsense", cmd_motionsense},
-	{"nextevent", cmd_next_event},
-	{"panicinfo", cmd_panic_info},
-	{"pause_in_s5", cmd_s5},
-	{"pchg", cmd_pchg},
-	{"pdgetmode", cmd_pd_get_amode},
-	{"pdsetmode", cmd_pd_set_amode},
-	{"port80read", cmd_port80_read},
-	{"pdlog", cmd_pd_log},
-	{"pdcontrol", cmd_pd_control},
-	{"pdchipinfo", cmd_pd_chip_info},
-	{"pdwritelog", cmd_pd_write_log},
-	{"powerinfo", cmd_power_info},
-	{"protoinfo", cmd_proto_info},
-	{"pse", cmd_pse},
-	{"pstoreinfo", cmd_pstore_info},
-	{"pstoreread", cmd_pstore_read},
-	{"pstorewrite", cmd_pstore_write},
-	{"pwmgetfanrpm", cmd_pwm_get_fan_rpm},
-	{"pwmgetkblight", cmd_pwm_get_keyboard_backlight},
-	{"pwmgetnumfans", cmd_pwm_get_num_fans},
-	{"pwmgetduty", cmd_pwm_get_duty},
-	{"pwmsetfanrpm", cmd_pwm_set_fan_rpm},
-	{"pwmsetkblight", cmd_pwm_set_keyboard_backlight},
-	{"pwmsetduty", cmd_pwm_set_duty},
-	{"rand", cmd_rand},
-	{"readtest", cmd_read_test},
-	{"reboot_ec", cmd_reboot_ec},
-	{"rgbkbd", cmd_rgbkbd},
-	{"rollbackinfo", cmd_rollback_info},
-	{"rtcget", cmd_rtc_get},
-	{"rtcgetalarm", cmd_rtc_get_alarm},
-	{"rtcset", cmd_rtc_set},
-	{"rtcsetalarm", cmd_rtc_set_alarm},
-	{"rwhashpd", cmd_rw_hash_pd},
-	{"rwsig", cmd_rwsig},
-	{"rwsigaction", cmd_rwsig_action_legacy},
-	{"rwsigstatus", cmd_rwsig_status},
-	{"sertest", cmd_serial_test},
-	{"smartdischarge", cmd_smart_discharge},
-	{"stress", cmd_stress_test},
-	{"sysinfo", cmd_sysinfo},
-	{"port80flood", cmd_port_80_flood},
-	{"switches", cmd_switches},
-	{"temps", cmd_temperature},
-	{"tempsinfo", cmd_temp_sensor_info},
-	{"test", cmd_test},
-	{"thermalget", cmd_thermal_get_threshold},
-	{"thermalset", cmd_thermal_set_threshold},
-	{"tpselftest", cmd_tp_self_test},
-	{"tpframeget", cmd_tp_frame_get},
-	{"tmp006cal", cmd_tmp006cal},
-	{"tmp006raw", cmd_tmp006raw},
-	{"typeccontrol", cmd_typec_control},
-	{"typecdiscovery", cmd_typec_discovery},
-	{"typecstatus", cmd_typec_status},
-	{"uptimeinfo", cmd_uptimeinfo},
-	{"usbchargemode", cmd_usb_charge_set_mode},
-	{"usbmux", cmd_usb_mux},
-	{"usbpd", cmd_usb_pd},
-	{"usbpddps", cmd_usb_pd_dps},
-	{"usbpdmuxinfo", cmd_usb_pd_mux_info},
-	{"usbpdpower", cmd_usb_pd_power},
-	{"version", cmd_version},
-	{"waitevent", cmd_wait_event},
-	{"wireless", cmd_wireless},
-	{"reboot_ap_on_g3", cmd_reboot_ap_on_g3},
-	{NULL, NULL}
+	{ "adcread", cmd_adc_read },
+	{ "addentropy", cmd_add_entropy },
+	{ "apreset", cmd_apreset },
+	{ "autofanctrl", cmd_thermal_auto_fan_ctrl },
+	{ "backlight", cmd_lcd_backlight },
+	{ "basestate", cmd_basestate },
+	{ "battery", cmd_battery },
+	{ "batterycutoff", cmd_battery_cut_off },
+	{ "batteryparam", cmd_battery_vendor_param },
+	{ "boardversion", cmd_board_version },
+	{ "button", cmd_button },
+	{ "cbi", cmd_cbi },
+	{ "chargecurrentlimit", cmd_charge_current_limit },
+	{ "chargecontrol", cmd_charge_control },
+	{ "chargeoverride", cmd_charge_port_override },
+	{ "chargesplash", cmd_chargesplash },
+	{ "chargestate", cmd_charge_state },
+	{ "chipinfo", cmd_chipinfo },
+	{ "cmdversions", cmd_cmdversions },
+	{ "console", cmd_console },
+	{ "cec", cmd_cec },
+	{ "echash", cmd_ec_hash },
+	{ "eventclear", cmd_host_event_clear },
+	{ "eventclearb", cmd_host_event_clear_b },
+	{ "eventget", cmd_host_event_get_raw },
+	{ "eventgetb", cmd_host_event_get_b },
+	{ "eventgetscimask", cmd_host_event_get_sci_mask },
+	{ "eventgetsmimask", cmd_host_event_get_smi_mask },
+	{ "eventgetwakemask", cmd_host_event_get_wake_mask },
+	{ "eventsetscimask", cmd_host_event_set_sci_mask },
+	{ "eventsetsmimask", cmd_host_event_set_smi_mask },
+	{ "eventsetwakemask", cmd_host_event_set_wake_mask },
+	{ "extpwrlimit", cmd_ext_power_limit },
+	{ "fanduty", cmd_fanduty },
+	{ "flasherase", cmd_flash_erase },
+	{ "flasheraseasync", cmd_flash_erase },
+	{ "flashprotect", cmd_flash_protect },
+	{ "flashread", cmd_flash_read },
+	{ "flashwrite", cmd_flash_write },
+	{ "flashinfo", cmd_flash_info },
+	{ "flashspiinfo", cmd_flash_spi_info },
+	{ "flashpd", cmd_flash_pd },
+	{ "forcelidopen", cmd_force_lid_open },
+	{ "fpcontext", cmd_fp_context },
+	{ "fpencstatus", cmd_fp_enc_status },
+	{ "fpframe", cmd_fp_frame },
+	{ "fpinfo", cmd_fp_info },
+	{ "fpmode", cmd_fp_mode },
+	{ "fpseed", cmd_fp_seed },
+	{ "fpstats", cmd_fp_stats },
+	{ "fptemplate", cmd_fp_template },
+	{ "gpioget", cmd_gpio_get },
+	{ "gpioset", cmd_gpio_set },
+	{ "hangdetect", cmd_hang_detect },
+	{ "hello", cmd_hello },
+	{ "hibdelay", cmd_hibdelay },
+	{ "hostevent", cmd_hostevent },
+	{ "hostsleepstate", cmd_hostsleepstate },
+	{ "locatechip", cmd_locate_chip },
+	{ "i2cprotect", cmd_i2c_protect },
+	{ "i2cread", cmd_i2c_read },
+	{ "i2cspeed", cmd_i2c_speed },
+	{ "i2cwrite", cmd_i2c_write },
+	{ "i2cxfer", cmd_i2c_xfer },
+	{ "infopddev", cmd_pd_device_info },
+	{ "inventory", cmd_inventory },
+	{ "led", cmd_led },
+	{ "lightbar", cmd_lightbar },
+	{ "kbfactorytest", cmd_keyboard_factory_test },
+	{ "kbid", cmd_kbid },
+	{ "kbinfo", cmd_kbinfo },
+	{ "kbpress", cmd_kbpress },
+	{ "keyconfig", cmd_keyconfig },
+	{ "keyscan", cmd_keyscan },
+	{ "mkbpget", cmd_mkbp_get },
+	{ "mkbpwakemask", cmd_mkbp_wake_mask },
+	{ "motionsense", cmd_motionsense },
+	{ "nextevent", cmd_next_event },
+	{ "panicinfo", cmd_panic_info },
+	{ "pause_in_s5", cmd_s5 },
+	{ "pchg", cmd_pchg },
+	{ "pdgetmode", cmd_pd_get_amode },
+	{ "pdsetmode", cmd_pd_set_amode },
+	{ "port80read", cmd_port80_read },
+	{ "pdlog", cmd_pd_log },
+	{ "pdcontrol", cmd_pd_control },
+	{ "pdchipinfo", cmd_pd_chip_info },
+	{ "pdwritelog", cmd_pd_write_log },
+	{ "powerinfo", cmd_power_info },
+	{ "protoinfo", cmd_proto_info },
+	{ "pse", cmd_pse },
+	{ "pstoreinfo", cmd_pstore_info },
+	{ "pstoreread", cmd_pstore_read },
+	{ "pstorewrite", cmd_pstore_write },
+	{ "pwmgetfanrpm", cmd_pwm_get_fan_rpm },
+	{ "pwmgetkblight", cmd_pwm_get_keyboard_backlight },
+	{ "pwmgetnumfans", cmd_pwm_get_num_fans },
+	{ "pwmgetduty", cmd_pwm_get_duty },
+	{ "pwmsetfanrpm", cmd_pwm_set_fan_rpm },
+	{ "pwmsetkblight", cmd_pwm_set_keyboard_backlight },
+	{ "pwmsetduty", cmd_pwm_set_duty },
+	{ "rand", cmd_rand },
+	{ "readtest", cmd_read_test },
+	{ "reboot_ec", cmd_reboot_ec },
+	{ "rgbkbd", cmd_rgbkbd },
+	{ "rollbackinfo", cmd_rollback_info },
+	{ "rtcget", cmd_rtc_get },
+	{ "rtcgetalarm", cmd_rtc_get_alarm },
+	{ "rtcset", cmd_rtc_set },
+	{ "rtcsetalarm", cmd_rtc_set_alarm },
+	{ "rwhashpd", cmd_rw_hash_pd },
+	{ "rwsig", cmd_rwsig },
+	{ "rwsigaction", cmd_rwsig_action_legacy },
+	{ "rwsigstatus", cmd_rwsig_status },
+	{ "sertest", cmd_serial_test },
+	{ "smartdischarge", cmd_smart_discharge },
+	{ "stress", cmd_stress_test },
+	{ "sysinfo", cmd_sysinfo },
+	{ "port80flood", cmd_port_80_flood },
+	{ "switches", cmd_switches },
+	{ "temps", cmd_temperature },
+	{ "tempsinfo", cmd_temp_sensor_info },
+	{ "test", cmd_test },
+	{ "thermalget", cmd_thermal_get_threshold },
+	{ "thermalset", cmd_thermal_set_threshold },
+	{ "tpselftest", cmd_tp_self_test },
+	{ "tpframeget", cmd_tp_frame_get },
+	{ "tmp006cal", cmd_tmp006cal },
+	{ "tmp006raw", cmd_tmp006raw },
+	{ "typeccontrol", cmd_typec_control },
+	{ "typecdiscovery", cmd_typec_discovery },
+	{ "typecstatus", cmd_typec_status },
+	{ "uptimeinfo", cmd_uptimeinfo },
+	{ "usbchargemode", cmd_usb_charge_set_mode },
+	{ "usbmux", cmd_usb_mux },
+	{ "usbpd", cmd_usb_pd },
+	{ "usbpddps", cmd_usb_pd_dps },
+	{ "usbpdmuxinfo", cmd_usb_pd_mux_info },
+	{ "usbpdpower", cmd_usb_pd_power },
+	{ "version", cmd_version },
+	{ "waitevent", cmd_wait_event },
+	{ "wireless", cmd_wireless },
+	{ "reboot_ap_on_g3", cmd_reboot_ap_on_g3 },
+	{ NULL, NULL }
 };
 
 int main(int argc, char *argv[])
@@ -10980,8 +11036,8 @@ int main(int argc, char *argv[])
 			break;
 		case OPT_I2C_BUS:
 			i2c_bus = strtoull(optarg, &e, 0);
-			if (*optarg == '\0' || (e && *e != '\0')
-			    || i2c_bus < 0) {
+			if (*optarg == '\0' || (e && *e != '\0') ||
+			    i2c_bus < 0) {
 				fprintf(stderr, "Invalid --i2c_bus\n");
 				parse_error = 1;
 			}
@@ -10992,9 +11048,10 @@ int main(int argc, char *argv[])
 		}
 	}
 
-	if (i2c_bus != -1)  {
+	if (i2c_bus != -1) {
 		if (!(interfaces & COMM_I2C)) {
-			fprintf(stderr, "--i2c_bus is specified, but --interface is set to something other than I2C\n");
+			fprintf(stderr,
+				"--i2c_bus is specified, but --interface is set to something other than I2C\n");
 			parse_error = 1;
 		} else {
 			interfaces = COMM_I2C;
@@ -11030,7 +11087,10 @@ int main(int argc, char *argv[])
 	/* Prefer /dev method, which supports built-in mutex */
 	if (!(interfaces & COMM_DEV) || comm_init_dev(device_name)) {
 		/* If dev is excluded or isn't supported, find alternative */
-		if (acquire_gec_lock(GEC_LOCK_TIMEOUT_SECS) < 0) {
+
+		/* Lock is not needed for COMM_USB */
+		if (!(interfaces & COMM_USB) &&
+		    acquire_gec_lock(GEC_LOCK_TIMEOUT_SECS) < 0) {
 			fprintf(stderr, "Could not acquire GEC lock.\n");
 			exit(1);
 		}
diff --git a/util/ectool.h b/util/ectool.h
index c76e1652cc..3b398af273 100644
--- a/util/ectool.h
+++ b/util/ectool.h
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/util/ectool_i2c.c b/util/ectool_i2c.c
index 97e47e6e85..efe2b723a2 100644
--- a/util/ectool_i2c.c
+++ b/util/ectool_i2c.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,8 +20,7 @@ int cmd_i2c_protect(int argc, char *argv[])
 	int rv;
 
 	if (argc != 2 && (argc != 3 || strcmp(argv[2], "status"))) {
-		fprintf(stderr, "Usage: %s <port> [status]\n",
-			argv[0]);
+		fprintf(stderr, "Usage: %s <port> [status]\n", argv[0]);
 		return -1;
 	}
 
@@ -56,9 +55,8 @@ int cmd_i2c_protect(int argc, char *argv[])
 	return 0;
 }
 
-static int do_i2c_xfer(unsigned int port, unsigned int addr,
-		       uint8_t *write_buf, int write_len,
-		       uint8_t **read_buf, int read_len)
+static int do_i2c_xfer(unsigned int port, unsigned int addr, uint8_t *write_buf,
+		       int write_len, uint8_t **read_buf, int read_len)
 {
 	struct ec_params_i2c_passthru *p =
 		(struct ec_params_i2c_passthru *)ec_outbuf;
@@ -96,8 +94,8 @@ static int do_i2c_xfer(unsigned int port, unsigned int addr,
 		msg->len = read_len;
 	}
 
-	rv = ec_command(EC_CMD_I2C_PASSTHRU, 0, p, size + write_len,
-			r, sizeof(*r) + read_len);
+	rv = ec_command(EC_CMD_I2C_PASSTHRU, 0, p, size + write_len, r,
+			sizeof(*r) + read_len);
 	if (rv < 0)
 		return rv;
 
@@ -132,9 +130,7 @@ static void cmd_i2c_help(void)
 		"    <offset> offset to read from or write to\n"
 		"    <data> data to write\n"
 		"    <read_count> number of bytes to read\n"
-		"    [bytes ...] data to write\n"
-		);
-
+		"    [bytes ...] data to write\n");
 }
 
 int cmd_i2c_read(int argc, char *argv[])
@@ -184,8 +180,8 @@ int cmd_i2c_read(int argc, char *argv[])
 	if (rv < 0)
 		return rv;
 
-	printf("Read from I2C port %d at 0x%x offset 0x%x = 0x%x\n",
-	       port, addr8, write_buf[0], *(uint16_t *)read_buf);
+	printf("Read from I2C port %d at 0x%x offset 0x%x = 0x%x\n", port,
+	       addr8, write_buf[0], *(uint16_t *)read_buf);
 	return 0;
 }
 
@@ -324,7 +320,7 @@ int cmd_i2c_xfer(int argc, char *argv[])
 
 static int i2c_get(int port)
 {
-	struct ec_params_i2c_control  p;
+	struct ec_params_i2c_control p;
 	struct ec_response_i2c_control r;
 	uint16_t speed_khz;
 	int rv;
@@ -348,7 +344,7 @@ static int i2c_get(int port)
 
 static int i2c_set(int port, int new_speed_khz)
 {
-	struct ec_params_i2c_control  p;
+	struct ec_params_i2c_control p;
 	struct ec_response_i2c_control r;
 	uint16_t old_speed_khz;
 	int rv;
@@ -374,8 +370,7 @@ static int i2c_set(int port, int new_speed_khz)
 		printf("Port %d speed set to %d kHz\n", port, new_speed_khz);
 	} else {
 		printf("Port %d speed changed from %u kHz to %d kHz\n", port,
-		       old_speed_khz,
-		       new_speed_khz);
+		       old_speed_khz, new_speed_khz);
 	}
 
 	return 0;
@@ -403,7 +398,7 @@ int cmd_i2c_speed(int argc, char *argv[])
 	speed = strtol(argv[2], &e, 0);
 	if (e && *e) {
 		fprintf(stderr, "Bad speed. "
-			"Typical speeds are one of {100,400,1000}.\n");
+				"Typical speeds are one of {100,400,1000}.\n");
 		return -1;
 	}
 
diff --git a/util/ectool_keyscan.c b/util/ectool_keyscan.c
index 4f5393157d..796e197a9a 100644
--- a/util/ectool_keyscan.c
+++ b/util/ectool_keyscan.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,39 +18,39 @@
 
 enum {
 	/* Alloc this many more scans when needed */
-	KEYSCAN_ALLOC_STEP	= 64,
-	KEYSCAN_MAX_TESTS	= 10,	/* Maximum number of tests supported */
-	KEYSCAN_MAX_INPUT_LEN	= 20,	/* Maximum characters we can receive */
+	KEYSCAN_ALLOC_STEP = 64,
+	KEYSCAN_MAX_TESTS = 10, /* Maximum number of tests supported */
+	KEYSCAN_MAX_INPUT_LEN = 20, /* Maximum characters we can receive */
 };
 
 /* A single entry of the key matrix */
 struct matrix_entry {
-	int row;	/* key matrix row */
-	int col;	/* key matrix column */
-	int keycode;	/* corresponding linux key code */
+	int row; /* key matrix row */
+	int col; /* key matrix column */
+	int keycode; /* corresponding linux key code */
 };
 
 struct keyscan_test_item {
-	uint32_t beat;			/* Beat number */
-	uint8_t scan[KEYBOARD_COLS_MAX];	/* Scan data */
+	uint32_t beat; /* Beat number */
+	uint8_t scan[KEYBOARD_COLS_MAX]; /* Scan data */
 };
 
 /* A single test, consisting of a list of key scans and expected ascii input */
 struct keyscan_test {
-	char *name;		/* name of test */
-	char *expect;		/* resulting input we expect to see */
-	int item_count;		/* number of items in data */
-	int item_alloced;	/* number of items alloced in data */
-	struct keyscan_test_item *items;	/* key data for EC */
+	char *name; /* name of test */
+	char *expect; /* resulting input we expect to see */
+	int item_count; /* number of items in data */
+	int item_alloced; /* number of items alloced in data */
+	struct keyscan_test_item *items; /* key data for EC */
 };
 
 /* A list of tests that we can run */
 struct keyscan_info {
-	unsigned int beat_us;	/* length of each beat in microseconds */
-	struct keyscan_test tests[KEYSCAN_MAX_TESTS];	/* the tests */
-	int test_count;		/* number of tests */
-	struct matrix_entry *matrix;	/* the key matrix info */
-	int matrix_count;	/* number of keys in matrix */
+	unsigned int beat_us; /* length of each beat in microseconds */
+	struct keyscan_test tests[KEYSCAN_MAX_TESTS]; /* the tests */
+	int test_count; /* number of tests */
+	struct matrix_entry *matrix; /* the key matrix info */
+	int matrix_count; /* number of keys in matrix */
 };
 
 /**
@@ -125,18 +125,18 @@ static int keyscan_read_fdt_matrix(struct keyscan_info *keyscan,
  * when we see a space in a key sequence file.
  */
 static const unsigned char kbd_plain_xlate[] = {
-	0xff, 0x1b, '1',  '2',  '3',  '4',  '5',  '6',
-	'7',  '8',  '9',  '0',  '-',  '=', '\b', '\t',	/* 0x00 - 0x0f */
-	'q',  'w',  'e',  'r',  't',  'y',  'u',  'i',
-	'o',  'p',  '[',  ']', '\r', 0xff,  'a',  's',  /* 0x10 - 0x1f */
-	'd',  'f',  'g',  'h',  'j',  'k',  'l',  ';',
-	'\'',  '`', 0xff, '\\', 'z',  'x',  'c',  'v',	/* 0x20 - 0x2f */
-	'b',  'n',  'm',  ',' ,  '.', '/', 0xff, 0xff, 0xff,
-	0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,	/* 0x30 - 0x3f */
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  '7',
-	'8',  '9',  '-',  '4',  '5',  '6',  '+',  '1',	/* 0x40 - 0x4f */
-	'2',  '3',  '0',  '.', 0xff, 0xff, 0xff, 0xff,
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,	/* 0x50 - 0x5F */
+	0xff, 0x1b, '1',  '2',	'3',  '4',  '5',  '6',
+	'7',  '8',  '9',  '0',	'-',  '=',  '\b', '\t', /* 0x00 - 0x0f */
+	'q',  'w',  'e',  'r',	't',  'y',  'u',  'i',
+	'o',  'p',  '[',  ']',	'\r', 0xff, 'a',  's', /* 0x10 - 0x1f */
+	'd',  'f',  'g',  'h',	'j',  'k',  'l',  ';',
+	'\'', '`',  0xff, '\\', 'z',  'x',  'c',  'v', /* 0x20 - 0x2f */
+	'b',  'n',  'm',  ',',	'.',  '/',  0xff, 0xff,
+	0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x30 - 0x3f */
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, '7',
+	'8',  '9',  '-',  '4',	'5',  '6',  '+',  '1', /* 0x40 - 0x4f */
+	'2',  '3',  '0',  '.',	0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x50 - 0x5F */
 	'\r', 0xff, 0xff, '\0'
 };
 
@@ -216,7 +216,7 @@ static int keyscan_add_to_scan(struct keyscan_info *keyscan, char **keysp,
 
 	/* Look up keycode in matrix */
 	for (i = 0, matrix = keyscan->matrix; i < keyscan->matrix_count;
-			i++, matrix++) {
+	     i++, matrix++) {
 		if (matrix->keycode == keycode) {
 #ifdef DEBUG
 			printf("%d: %d,%d\n", matrix->keycode, matrix->row,
@@ -289,15 +289,15 @@ static int keyscan_process_keys(struct keyscan_info *keyscan, int linenum,
 		keys++;
 		while (*keys) {
 			if (keyscan_add_to_scan(keyscan, &keys, item->scan)) {
-				fprintf(stderr, "Line %d: Cannot parse"
-					" key input '%s'\n", linenum,
-					keys);
+				fprintf(stderr,
+					"Line %d: Cannot parse"
+					" key input '%s'\n",
+					linenum, keys);
 				return -1;
 			}
 		}
 	} else if (*keys) {
-		fprintf(stderr, "Line %d: Need space after beat\n",
-			linenum);
+		fprintf(stderr, "Line %d: Need space after beat\n", linenum);
 		return -1;
 	}
 	test->item_count++;
@@ -307,10 +307,10 @@ static int keyscan_process_keys(struct keyscan_info *keyscan, int linenum,
 
 /* These are the commands we understand in a key sequence file */
 enum keyscan_cmd {
-	KEYSCAN_CMD_TEST,	/* start a new test */
-	KEYSCAN_CMD_ENDTEST,	/* end a test */
-	KEYSCAN_CMD_SEQ,	/* add a keyscan to a test sequence */
-	KEYSCAN_CMD_EXPECT,	/* indicate what input is expected */
+	KEYSCAN_CMD_TEST, /* start a new test */
+	KEYSCAN_CMD_ENDTEST, /* end a test */
+	KEYSCAN_CMD_SEQ, /* add a keyscan to a test sequence */
+	KEYSCAN_CMD_EXPECT, /* indicate what input is expected */
 
 	KEYSCAN_CMD_COUNT
 };
@@ -388,7 +388,7 @@ static int keyscan_process_file(FILE *f, struct keyscan_info *keyscan)
 			/* Start a new test */
 			if (keyscan->test_count == KEYSCAN_MAX_TESTS) {
 				fprintf(stderr, "KEYSCAN_MAX_TESTS "
-					"exceeded\n");
+						"exceeded\n");
 				return -1;
 			}
 			cur_test = &keyscan->tests[keyscan->test_count];
@@ -401,8 +401,10 @@ static int keyscan_process_file(FILE *f, struct keyscan_info *keyscan)
 		case KEYSCAN_CMD_EXPECT:
 			/* Get expect string */
 			if (!cur_test) {
-				fprintf(stderr, "Line %d: expect should be "
-					"inside test\n", linenum);
+				fprintf(stderr,
+					"Line %d: expect should be "
+					"inside test\n",
+					linenum);
 				return -1;
 			}
 			cur_test->expect = strdup(args);
@@ -418,9 +420,11 @@ static int keyscan_process_file(FILE *f, struct keyscan_info *keyscan)
 			break;
 		case KEYSCAN_CMD_SEQ:
 			if (keyscan_process_keys(keyscan, linenum, cur_test,
-					args)) {
-				fprintf(stderr, "Line %d: Cannot parse key "
-					"input '%s'\n", linenum, args);
+						 args)) {
+				fprintf(stderr,
+					"Line %d: Cannot parse key "
+					"input '%s'\n",
+					linenum, args);
 				return -1;
 			}
 			break;
@@ -519,8 +523,8 @@ static int keyscan_send_sequence(struct keyscan_info *keyscan,
 		fprintf(stderr, "Out of memory for message\n");
 		return -1;
 	}
-	for (upto = rv = 0, item = test->items; rv >= 0 &&
-			upto < test->item_count; upto++, item++) {
+	for (upto = rv = 0, item = test->items;
+	     rv >= 0 && upto < test->item_count; upto++, item++) {
 		req->cmd = EC_KEYSCAN_SEQ_ADD;
 		req->add.time_us = item->beat * keyscan->beat_us;
 		memcpy(req->add.scan, item->scan, sizeof(item->scan));
@@ -553,8 +557,8 @@ static int run_test(struct keyscan_info *keyscan, struct keyscan_test *test)
 
 	/* First clear the sequence */
 	ctrl.cmd = EC_KEYSCAN_SEQ_CLEAR;
-	rv = ec_command(EC_CMD_KEYSCAN_SEQ_CTRL, 0, &ctrl, sizeof(ctrl),
-			NULL, 0);
+	rv = ec_command(EC_CMD_KEYSCAN_SEQ_CTRL, 0, &ctrl, sizeof(ctrl), NULL,
+			0);
 	if (rv < 0)
 		return rv;
 
@@ -565,13 +569,13 @@ static int run_test(struct keyscan_info *keyscan, struct keyscan_test *test)
 	/* Start it */
 	set_to_raw(fd, 1);
 	ctrl.cmd = EC_KEYSCAN_SEQ_START;
-	rv = ec_command(EC_CMD_KEYSCAN_SEQ_CTRL, 0, &ctrl, sizeof(ctrl),
-			NULL, 0);
+	rv = ec_command(EC_CMD_KEYSCAN_SEQ_CTRL, 0, &ctrl, sizeof(ctrl), NULL,
+			0);
 	if (rv < 0)
 		return rv;
 
 	/* Work out how long we need to wait */
-	wait_us = 100 * 1000;	/* Wait 100ms to at least */
+	wait_us = 100 * 1000; /* Wait 100ms to at least */
 	if (test->item_count) {
 		struct keyscan_test_item *ksi;
 
@@ -593,8 +597,8 @@ static int run_test(struct keyscan_info *keyscan, struct keyscan_test *test)
 	ctrl.cmd = EC_KEYSCAN_SEQ_COLLECT;
 	ctrl.collect.start_item = 0;
 	ctrl.collect.num_items = test->item_count;
-	rv = ec_command(EC_CMD_KEYSCAN_SEQ_CTRL, 0, &ctrl, sizeof(ctrl),
-			resp, size);
+	rv = ec_command(EC_CMD_KEYSCAN_SEQ_CTRL, 0, &ctrl, sizeof(ctrl), resp,
+			size);
 	if (rv < 0)
 		return rv;
 
diff --git a/util/env_changed.sh b/util/env_changed.sh
index 5bab64760d..eadc94ae01 100755
--- a/util/env_changed.sh
+++ b/util/env_changed.sh
@@ -1,5 +1,5 @@
 #!/bin/bash
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/util/export_taskinfo.c b/util/export_taskinfo.c
index 4c09bafb90..af40ef8de6 100644
--- a/util/export_taskinfo.c
+++ b/util/export_taskinfo.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -25,14 +25,13 @@ struct taskinfo {
 	uint32_t stack_size;
 };
 
-#define TASK(n, r, d, s, ...)  {	\
-	.name = #n,			\
-	.routine = #r,			\
-	.stack_size = s,		\
-},
-static const struct taskinfo taskinfos[] = {
-	CONFIG_TASK_LIST
-};
+#define TASK(n, r, d, s, ...)    \
+	{                        \
+		.name = #n,      \
+		.routine = #r,   \
+		.stack_size = s, \
+	},
+static const struct taskinfo taskinfos[] = { CONFIG_TASK_LIST };
 #undef TASK
 
 uint32_t GET_TASKINFOS_FUNC(const struct taskinfo **infos)
diff --git a/util/flash_ec b/util/flash_ec
index 7cb4ebcda8..8557b637e5 100755
--- a/util/flash_ec
+++ b/util/flash_ec
@@ -1,11 +1,11 @@
 #!/bin/bash
 
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
+# Copyright 2014 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 SCRIPT="$(readlink -f "$0")"
-SCRIPT_DIR="$(dirname "$SCRIPT")"
+SCRIPT_DIR="$(dirname "${SCRIPT}")"
 
 EC_DIR="$(readlink -f "${SCRIPT_DIR}/..")"
 if [[ "$(basename "${EC_DIR}")" != "ec" ]]; then
@@ -147,9 +147,9 @@ BITBANG_RATE="57600"  # Could be overwritten by a command line option.
 
 # Flags
 DEFINE_integer bitbang_rate "${BITBANG_RATE}" \
-	"UART baud rate to use when bit bang programming, "\
+	"UART baud rate to use when bit bang programming, " \
 "standard UART rates from 9600 to 57600 are supported."
-DEFINE_string board "${DEFAULT_BOARD}" \
+DEFINE_string board "" \
 	"The board to run debugger on."
 DEFINE_string chip "" \
 	"The chip to run debugger on."
@@ -223,15 +223,15 @@ function print_or_run() {
 function dut_control() {
 	local DUT_CTRL_CML=( "${DUT_CONTROL_CMD[@]}" )
 
-	for p in $@ ; do
+	for p in "$@" ; do
 		# Only add the prefix if the arg is a control name.
 		if [[ ${p} != -* ]] ; then
 			p="${DUT_CTRL_PREFIX}${p}"
 		fi
-		DUT_CTRL_CML+=( "$p" )
+		DUT_CTRL_CML+=( "${p}" )
 	done
 
-	if [ "${FLAGS_verbose}" = ${FLAGS_TRUE} ]; then
+	if [ "${FLAGS_verbose}" = "${FLAGS_TRUE}" ]; then
 		echo "${DUT_CTRL_CML[*]}" 1>&2
 	fi
 
@@ -244,7 +244,7 @@ function dut_control_or_die {
 
 function dut_control_get() {
 	if [ $# -gt 1 ]; then
-		error "${FUNCNAME[0]} failed: more than one argument: $@"
+		error "${FUNCNAME[0]} failed: more than one argument: $*"
 		return 1
 	fi
 
@@ -266,7 +266,11 @@ function dut_control_get_or_die {
 	    die "command exited $? (non-zero): dut-control --value_only $*"
 }
 
-: ${BOARD:=${FLAGS_board}}
+: "${BOARD:=${FLAGS_board}}"
+
+if [ "${BOARD}" == "" ]; then
+  die "Must specify board."
+fi
 
 in_array() {
 	local n=$#
@@ -282,48 +286,48 @@ in_array() {
 
 declare -a SUPPORTED_CHIPS
 
-if $(in_array "${BOARDS_STM32[@]}" "${BOARD}"); then
+if in_array "${BOARDS_STM32[@]}" "${BOARD}"; then
 	SUPPORTED_CHIPS+=("stm32")
 fi
 
-if $(in_array "${BOARDS_STM32_DFU[@]}" "${BOARD}"); then
+if in_array "${BOARDS_STM32_DFU[@]}" "${BOARD}"; then
 	SUPPORTED_CHIPS+=("stm32_dfu")
 fi
 
-if $(in_array "${BOARDS_NPCX_5M5G_JTAG[@]}" "${BOARD}"); then
+if in_array "${BOARDS_NPCX_5M5G_JTAG[@]}" "${BOARD}"; then
 	SUPPORTED_CHIPS+=("npcx_5m5g_jtag")
 fi
 
-if $(in_array "${BOARDS_NPCX_5M6G_JTAG[@]}" "${BOARD}"); then
+if in_array "${BOARDS_NPCX_5M6G_JTAG[@]}" "${BOARD}"; then
 	SUPPORTED_CHIPS+=("npcx_5m6g_jtag")
 fi
 
-if $(in_array "${BOARDS_NPCX_7M6X_JTAG[@]}" "${BOARD}"); then
+if in_array "${BOARDS_NPCX_7M6X_JTAG[@]}" "${BOARD}"; then
 	SUPPORTED_CHIPS+=("npcx_7m6x_jtag")
 fi
 
-if $(in_array "${BOARDS_NPCX_7M7X_JTAG[@]}" "${BOARD}"); then
+if in_array "${BOARDS_NPCX_7M7X_JTAG[@]}" "${BOARD}"; then
 	SUPPORTED_CHIPS+=("npcx_7m7x_jtag")
 fi
 
-if $(in_array "${BOARDS_NPCX_SPI[@]}" "${BOARD}"); then
+if in_array "${BOARDS_NPCX_SPI[@]}" "${BOARD}"; then
 	SUPPORTED_CHIPS+=("npcx_spi")
 fi
 
-if $(in_array "${BOARDS_NPCX_INT_SPI[@]}" "${BOARD}"); then
+if in_array "${BOARDS_NPCX_INT_SPI[@]}" "${BOARD}"; then
 	SUPPORTED_CHIPS+=("npcx_int_spi")
 fi
 
-if $(in_array "${BOARDS_IT83XX[@]}" "${BOARD}"); then
+if in_array "${BOARDS_IT83XX[@]}" "${BOARD}"; then
 	SUPPORTED_CHIPS+=("it83xx")
 fi
 
-if $(in_array "${BOARDS_IT83XX_SPI_PROGRAMMING[@]}" "${BOARD}"); then
+if in_array "${BOARDS_IT83XX_SPI_PROGRAMMING[@]}" "${BOARD}"; then
 	SUPPORTED_CHIPS+=("ite_spi")
 fi
 
 if [[ ${#SUPPORTED_CHIPS[@]} -eq 0 && -n "${FLAGS_chip}" ]]; then
-	SUPPORTED_CHIPS+="${FLAGS_chip}"
+	SUPPORTED_CHIPS+=("${FLAGS_chip}")
 fi
 
 if [[ ${#SUPPORTED_CHIPS[@]} -eq 0 ]]; then
@@ -345,10 +349,10 @@ if [[ ${#SUPPORTED_CHIPS[@]} -eq 0 ]]; then
 elif [[ ${#SUPPORTED_CHIPS[@]} -eq 1 ]]; then
 	CHIP="${SUPPORTED_CHIPS[0]}"
 elif [ -n "${FLAGS_chip}" ]; then
-	if $(in_array "${SUPPORTED_CHIPS[@]}" "${FLAGS_chip}"); then
+	if in_array "${SUPPORTED_CHIPS[@]}" "${FLAGS_chip}"; then
 		CHIP="${FLAGS_chip}"
 	else
-		die "board ${BOARD} only supports (${SUPPORTED_CHIPS[@]})," \
+		die "board ${BOARD} only supports (${SUPPORTED_CHIPS[*]})," \
 			"not ${FLAGS_chip}."
 	fi
 else
@@ -356,10 +360,10 @@ else
 	# file, instead of having multiple board-to-chip mapping info in this
 	# script. Please refer to crrev.com/c/1496460 for example.
 	die "board ${BOARD} supports multiple chips" \
-	"(${FILTERED_CHIPS[@]}). Use --chip= to choose one."
+	"(${SUPPORTED_CHIPS[*]}). Use --chip= to choose one."
 fi
 
-if [ -n "${FLAGS_chip}" -a "${CHIP}" != "${FLAGS_chip}" ]; then
+if [ -n "${FLAGS_chip}" ] && [ "${CHIP}" != "${FLAGS_chip}" ]; then
 	die "board ${BOARD} doesn't use chip ${FLAGS_chip}"
 fi
 
@@ -379,7 +383,7 @@ esac
 
 case "${CHIP}" in
 	"stm32"|"npcx_spi"|"npcx_int_spi"|"it83xx"|"npcx_uut"|"ite_spi"| \
-			"ite_spi_ccd_i2c")
+			"ite_spi_ccd_i2c"|"it8xxx2")
 		;;
 	*)
 		if [[ -n "${FLAGS_read}" ]]; then
@@ -388,7 +392,7 @@ case "${CHIP}" in
 
 		# If verification is not supported, then show a warning message.
 		# Keep it running however.
-		if [[ "${FLAGS_verify}" == ${FLAGS_TRUE} ]]; then
+		if [[ "${FLAGS_verify}" == "${FLAGS_TRUE}" ]]; then
 			warn "Ignoring '--verify'" \
 			"since read is not supported on ${CHIP}."
 		fi
@@ -399,6 +403,9 @@ SERVO_TYPE="$(dut_control_get servo_type || :)"
 
 if [[ "${SERVO_TYPE}" =~ ^servo_v4(p1)?_with_.*$ ]]; then
 	ACTIVE_DEVICE="$(dut_control_get active_dut_controller)"
+	if [[ ${ACTIVE_DEVICE} == neither ]]; then
+          die "Could not determine servo V4 active device"
+        fi
 else
 	ACTIVE_DEVICE="${SERVO_TYPE}"
 fi
@@ -464,6 +471,15 @@ servo_usbpd_hard_reset() {
 
 servo_fpmcu_hard_reset() {
 	dut_control fpmcu_reset:on sleep:0.5 fpmcu_reset:off
+
+	# b/177331210: Workaround for an outstanding issue that prevents
+	# flashing dartmonkey with a servo_micro. The exact root cause is still
+	# unknown, but it's been observed that repeating the FPMCU reset
+	# sequence twice makes the operation succeed.
+	if [[ "${BOARD}" =~ "dartmonkey" ]] ; then
+		warn "Workaround for dartmonkey + servo_micro: repeat FPMCU reset sequence"
+		dut_control fpmcu_reset:on sleep:0.5 fpmcu_reset:off
+	fi
 }
 
 servo_sh_hard_reset() {
@@ -481,7 +497,7 @@ ec_reset() {
 	fi
 
 	if [[ -n "${stype}" ]]; then
-		eval ${stype}_${MCU}_hard_reset
+		eval "${stype}_${MCU}_hard_reset"
 	fi
 }
 
@@ -497,7 +513,7 @@ ccd_ec_boot0() {
 		dut_control cold_reset:on
 	fi
 
-	dut_control "ccd_ec_boot_mode_${boot_mode}":"${on_value}"
+	dut_control "ccd_ec_boot_mode_${boot_mode}:${on_value}"
 }
 
 servo_micro_ec_boot0() {
@@ -505,7 +521,7 @@ servo_micro_ec_boot0() {
 	# circuit that is controlled by the EC_FLASH_ODL pin. For those boards,
 	# we want to continue to drive the EC_FLASH_ODL if they do not have the
 	# servo micro rework listed below.
-	if [[ "${FLAGS_servo_micro_uart_rx_rework}" == ${FLAGS_TRUE} ]]; then
+	if [[ "${FLAGS_servo_micro_uart_rx_rework}" == "${FLAGS_TRUE}" ]]; then
 		info "Servo micro $2 mode: $1 (using rx_rework)"
 
 		# Setting the test point allows the EC_TX_SERVO_RX line
@@ -515,28 +531,28 @@ servo_micro_ec_boot0() {
 		# HW Rework (b/143163043#comment3):
 		#   - Disconnect U45.1 from ground
 		#   - Connected U45.1 to TP1 pad
-		dut_control tp1:$1
-		dut_control servo_micro_ec_boot_mode_$2:$1
+		dut_control "tp1:$1"
+		dut_control "servo_micro_ec_boot_mode_$2:$1"
 	else
 		info "Servo micro $2 mode: $1 (using FW_UP_L)"
-		dut_control ec_boot_mode:$1
+		dut_control "ec_boot_mode:$1"
 	fi
 }
 
 servo_ec_boot0() {
-	dut_control ec_boot_mode:$1
+	dut_control "ec_boot_mode:$1"
 }
 
 c2d2_ec_boot0() {
-	dut_control ec_boot_mode_uut:$1
+	dut_control "ec_boot_mode_uut:$1"
 }
 
 servo_usbpd_boot0() {
-	dut_control usbpd_boot_mode:$1
+	dut_control "usbpd_boot_mode:$1"
 }
 
 servo_fpmcu_boot0() {
-	dut_control fpmcu_boot_mode:"$1"
+	dut_control "fpmcu_boot_mode:$1"
 }
 
 servo_micro_fpmcu_boot0() {
@@ -548,13 +564,13 @@ servo_micro_usbpd_boot0() {
 }
 
 servo_sh_boot0() {
-	dut_control sh_boot_mode:$1
+	dut_control "sh_boot_mode:$1"
 }
 
 ec_switch_boot0() {
 	local on_value=$1
 	# Enable programming GPIOs
-	if $(in_array "${BOARDS_STM32_PROG_EN[@]}" "${BOARD}"); then
+	if in_array "${BOARDS_STM32_PROG_EN[@]}" "${BOARD}"; then
 		servo_save_add "prog_en"
 
 		dut_control prog_en:yes
@@ -568,15 +584,15 @@ ec_switch_boot0() {
 	else
 		stype=${SERVO_TYPE}
 	fi
-	eval ${stype}_${MCU}_boot0 "${on_value}" $2
+	eval "${stype}_${MCU}_boot0" "${on_value}" "$2"
 }
 
 ec_enable_boot0() {
-	ec_switch_boot0 "on" $1
+	ec_switch_boot0 "on" "$1"
 }
 
 ec_disable_boot0() {
-	ec_switch_boot0 "off" $1
+	ec_switch_boot0 "off" "$1"
 }
 
 # Returns 0 on success (if on beaglebone)
@@ -593,9 +609,9 @@ on_raiden() {
 		return 0
 	fi
 	if [ -z "${BOARD}" ]; then
-		[ "${FLAGS_raiden}" = ${FLAGS_TRUE} ] && return 0 || return 1
+		[ "${FLAGS_raiden}" = "${FLAGS_TRUE}" ] && return 0 || return 1
 	fi
-	if [ "${FLAGS_raiden}" = ${FLAGS_TRUE} ]; then
+	if [ "${FLAGS_raiden}" = "${FLAGS_TRUE}" ]; then
 		if in_array "${BOARDS_RAIDEN[@]}" "${BOARD}"; then
 			return 0
 		fi
@@ -646,7 +662,7 @@ cleanup() {
 
 	servo_restore
 
-	if [ "${CHIP}" = "stm32" -o "${CHIP}" = "npcx_uut" ]; then
+	if [ "${CHIP}" = "stm32" ] || [ "${CHIP}" = "npcx_uut" ]; then
 		dut_control "${MCU}"_boot_mode:off
 	fi
 
@@ -665,25 +681,23 @@ trap cleanup EXIT
 # the RO image includes a header.
 # NPCX images use "build-ro/zephyr/zephyr.npcx.bin"
 # ITE images use "build-ro/zephyr/zephyr.bin"
-if [ "${FLAGS_ro}" = ${FLAGS_TRUE} ] && [ "${FLAGS_zephyr}" = ${FLAGS_TRUE} ]
+if [ "${FLAGS_ro}" = "${FLAGS_TRUE}" ] && [ "${FLAGS_zephyr}" = "${FLAGS_TRUE}" ]
 then
 	die "The --ro flag is not supported with the --zephyr flag"
 fi
 
 # Possible default EC images
-if [ "${FLAGS_ro}" = ${FLAGS_TRUE} ] ; then
+if [ "${FLAGS_ro}" = "${FLAGS_TRUE}" ] ; then
 	EC_FILE=ec.RO.flat
-elif [ "${FLAGS_zephyr}" = ${FLAGS_TRUE} ] ; then
-	EC_FILE=zephyr.bin
 else
 	EC_FILE=ec.bin
 fi
 
 LOCAL_BUILD=
 if [[ -n "${EC_DIR}" ]]; then
-	if [ "${FLAGS_ro}" = ${FLAGS_TRUE} ] ; then
+	if [ "${FLAGS_ro}" = "${FLAGS_TRUE}" ] ; then
 		LOCAL_BUILD="${EC_DIR}/build/${BOARD}/RO/${EC_FILE}"
-	elif [ "${FLAGS_zephyr}" = ${FLAGS_TRUE} ] ; then
+	elif [ "${FLAGS_zephyr}" = "${FLAGS_TRUE}" ] ; then
 		LOCAL_BUILD="${EC_DIR}/build/zephyr/${BOARD}/output/${EC_FILE}"
 	else
 		LOCAL_BUILD="${EC_DIR}/build/${BOARD}/${EC_FILE}"
@@ -697,14 +711,15 @@ BASEBOARD=
 # setting BASEBOARD
 set +e
 if [[ -n "${EC_DIR}" ]]; then
-	BASEBOARD=$(make --quiet -C ${EC_DIR} BOARD=${BOARD} print-baseboard \
+	BASEBOARD=$(make --quiet -C "${EC_DIR}" BOARD="${BOARD}" print-baseboard \
 		2>/dev/null)
 elif [[ -d "${HOME}/trunk/src/platform/ec" ]]; then
-	BASEBOARD=$(make --quiet -C ${HOME}/trunk/src/platform/ec \
-		BOARD=${BOARD} print-baseboard 2>/dev/null)
+	BASEBOARD=$(make --quiet -C "${HOME}"/trunk/src/platform/ec \
+		BOARD="${BOARD}" print-baseboard 2>/dev/null)
 else
 	info "Could not find ec build folder to calculate baseboard."
 fi
+# shellcheck disable=SC2181
 if [ $? -ne 0 ]; then
 	info "EC build system didn't recognize ${BOARD}. Assuming no baseboard."
 fi
@@ -763,20 +778,9 @@ function servo_ec_uart() {
 	if [[ -z "${PTY}" ]]; then
 	    die "${SERVOD_FAIL}"
 	fi
-	echo $PTY
+	echo "${PTY}"
 }
 
-# Not every control is supported on every servo type.  Therefore, define which
-# controls are supported by each servo type.
-servo_v2_VARS=( "cold_reset" )
-servo_micro_VARS=( "cold_reset" )
-servo_v4_with_ccd_cr50_VARS=( "cold_reset" )
-c2d2_VARS=( "cold_reset" )
-
-# Some servo boards use the same controls.
-servo_v3_VARS=( "${servo_v2_VARS[@]}" )
-servo_v4_with_servo_micro_VARS=( "${servo_micro_VARS[@]}" )
-
 declare -a save
 
 #######################################
@@ -789,12 +793,12 @@ function servo_save_add() {
 	local CTRL_RESULT=
 	case $# in
 		1) CTRL_RESULT="$( "${DUT_CONTROL_CMD[@]}" \
-				"${DUT_CTRL_PREFIX}$@" )"
+				"${DUT_CTRL_PREFIX}$*" )"
 		   if [[ -n "${CTRL_RESULT}" ]]; then
 			# Don't save the control with the prefix, because
 			# dut_control will add the prefix again when we restore
 			# the settings.
-			save=( "${CTRL_RESULT#$DUT_CTRL_PREFIX}" "${save[@]}" )
+			save=( "${CTRL_RESULT#${DUT_CTRL_PREFIX}}" "${save[@]}" )
 		   fi
 		   ;;
 		2) save=( "$1:$2" "${save[@]}" )
@@ -805,10 +809,7 @@ function servo_save_add() {
 }
 
 function servo_save() {
-	local SERVO_VARS_NAME="${SERVO_TYPE}_VARS[@]"
-	for ctrl in "${!SERVO_VARS_NAME}"; do
-		servo_save_add "${ctrl}"
-	done
+	servo_save_add "cold_reset"
 
 	if [[ "${SERVO_TYPE}" == "servo_v2" ]]; then
 		servo_save_add "i2c_mux_en"
@@ -844,22 +845,22 @@ function claim_pty() {
 	# interfere with flashing.
 	servo_save_add "${MCU}_ec3po_interp_connect"
 
-	dut_control ${MCU}_ec3po_interp_connect:off || \
+	dut_control "${MCU}_ec3po_interp_connect:off" || \
 	    warn "hdctools cannot disconnect the EC-3PO interpreter from" \
 	    "the UART."
 
-	pids=$(lsof -FR 2>/dev/null -- $1 | grep -v '^f' | tr -d 'pR')
+	pids=$(lsof -FR 2>/dev/null -- "$1" | grep -v '^f' | tr -d 'pR')
 	FROZEN_PIDS=""
 
 	# reverse order to SIGSTOP parents before children
-	for pid in $(echo ${pids} | tac -s " "); do
+	for pid in $(echo "${pids}" | tac -s " "); do
 		if ps -o cmd= "${pid}" | grep -qE "(servod|/sbin/init)"; then
 			info "Skip stopping servod or init: process ${pid}."
 		else
 			info "Sending SIGSTOP to process ${pid}!"
 			FROZEN_PIDS+=" ${pid}"
 			sleep 0.02
-			kill -STOP ${pid}
+			kill -STOP "${pid}"
 		fi
 	done
 }
@@ -901,7 +902,7 @@ repo sync && sudo emerge hdctools servo-firmware && sudo servo_updater -b c2d2"
 		while [[ "$(dut_control_get h1_vref_present)" = "off" \
 			&& "${LOOP_COUNTER}" -gt 1 ]] ; do
 			sleep 0.1
-			let LOOP_COUNTER=LOOP_COUNTER-1
+			(( LOOP_COUNTER=LOOP_COUNTER-1 ))
 		done
 		# If we ran out of time, then just die now
 		if [[ "${LOOP_COUNTER}" -eq 1 ]] ; then
@@ -944,7 +945,7 @@ function flash_openocd() {
 
 # helper function for using servo with flashrom
 function flash_flashrom() {
-	TOOL_PATH="${EC_DIR}/build/${BOARD}/util:$PATH:/usr/sbin"
+	TOOL_PATH="${EC_DIR}/build/${BOARD}/util:${PATH}:/usr/sbin"
 	FLASHROM=$(PATH="${TOOL_PATH}" which flashrom)
 
 	if on_servov3; then
@@ -960,21 +961,24 @@ function flash_flashrom() {
 		FLASHROM_ARGS="-p ft2232_spi:type=google-servo-v2,port=B,"
 	fi
 
-	if [ ! -x "$FLASHROM" ]; then
+	if [ ! -x "${FLASHROM}" ]; then
 		die "no flashrom util found."
 	fi
 
 	if ! on_servov3; then
 		SERIALNAME=$(get_serial)
-		if [[ "$SERIALNAME" != "" ]] ; then
+		if [[ "${SERIALNAME}" != "" ]] ; then
 			FLASHROM_ARGS+="serial=${SERIALNAME}"
 		fi
 	fi
 
+	# Eventually remove ite_spi_ccd_i2c once all references are removed
 	if ! on_raiden || [[ "${SERVO_TYPE}" =~ "servo_micro" ]] ; then
-		if $(in_array "${BOARDS_SPI_1800MV[@]}" "${BOARD}"); then
+		if in_array "${BOARDS_SPI_1800MV[@]}" "${BOARD}"; then
 			SPI_VOLTAGE="pp1800"
-		elif [[ "${CHIP}" == "ite_spi" || "${CHIP}" == "ite_spi_ccd_i2c" ]]; then
+		elif [[ "${CHIP}" == "ite_spi" ||
+		        "${CHIP}" == "ite_spi_ccd_i2c" ||
+			"${CHIP}" == "it8xxx2" ]]; then
 			SPI_VOLTAGE="pp1800"
 		else
 			SPI_VOLTAGE="pp3300"
@@ -993,7 +997,9 @@ function flash_flashrom() {
 		fi
 
 		# Enable SPI programming mode.
-		if [[ "${CHIP}" == "ite_spi" || "${CHIP}" == "ite_spi_ccd_i2c" ]]; then
+		if [[ "${CHIP}" == "ite_spi" ||
+		      "${CHIP}" == "ite_spi_ccd_i2c" ||
+		      "${CHIP}" == "it8xxx2" ]]; then
 			# Set hardware strap pin (GPG6) of SPI programming as low then start ec
 			dut_control fw_up:on
 			sleep 0.1
@@ -1007,7 +1013,7 @@ function flash_flashrom() {
 		servo_save_add "spi1_buf_en" "off"
 
 		# Turn on SPI1 interface on servo for SPI Flash Chip
-		dut_control spi1_vref:${SPI_VOLTAGE} spi1_buf_en:on
+		dut_control "spi1_vref:${SPI_VOLTAGE}" spi1_buf_en:on
 		if [[ ! "${SERVO_TYPE}" =~ "servo_micro" ]]; then
 			# Servo micro doesn't support this control.
 			servo_save_add "spi1_buf_on_flex_en" "off"
@@ -1033,24 +1039,25 @@ function flash_flashrom() {
 
 		[[ -z "${FLAGS_read}" ]] && dump_fmap -F "${IMG}" > "${L}"
 
-		FLASHROM_OPTIONS="-i EC_RW -i WP_RO -l "${L}" --noverify-all"
+		FLASHROM_OPTIONS=(-i EC_RW -i WP_RO -l "${L}" --noverify-all)
 	fi
 
 	# Generate the correct flashrom command base.
-	FLASHROM_CMDLINE="${FLASHROM} ${FLASHROM_ARGS}"
+	# shellcheck disable=SC2206
+	FLASHROM_CMDLINE=("${FLASHROM}" ${FLASHROM_ARGS})
 	if [[ -z "${FLAGS_read}" ]]; then
 		# Program EC image.
 		# flashrom should report the image size at the end of the output.
-		local FLASHROM_GETSIZE="sudo ${FLASHROM_CMDLINE} --flash-size"
-		if [[ "${FLAGS_verbose}" == ${FLAGS_TRUE} ]]; then
+		local FLASHROM_GETSIZE=(sudo "${FLASHROM_CMDLINE[@]}" --flash-size)
+		if [[ "${FLAGS_verbose}" == "${FLAGS_TRUE}" ]]; then
 			info "Running flashrom:" 1>&2
-			echo " ${FLASHROM_GETSIZE}" 1>&2
+			echo " ${FLASHROM_GETSIZE[*]}" 1>&2
 		fi
-		SPI_SIZE=$(${FLASHROM_GETSIZE} | grep -oe '[0-9]\+$' |
+		SPI_SIZE=$("${FLASHROM_GETSIZE[@]}" | grep -oe '[0-9]\+$' |
 			   tail -n1) || die "Failed to determine chip size!"
 		[[ ${SPI_SIZE} -eq 0 ]] && die "Chip size is 0!"
 
-		PATCH_SIZE=$((${SPI_SIZE} - ${IMG_SIZE}))
+		PATCH_SIZE=$(( SPI_SIZE - IMG_SIZE ))
 
 		# Temp image
 		T=/tmp/flash_spi_$$
@@ -1058,66 +1065,67 @@ function flash_flashrom() {
 
 		if [[ "${CHIP}" =~ ^npcx(|_int)_spi$ ]] || \
 		   [[ "${CHIP}" =~ "ite_spi_ccd_i2c" ]] ||
+		   [[ "${CHIP}" =~ "it8xxx2" ]] ||
 		   [[ "${CHIP}" =~ "ite_spi" ]] ; then
 		{	# Patch temp image up to SPI_SIZE
-			cat "$IMG"
+			cat "${IMG}"
 			if [[ ${IMG_SIZE} -lt ${SPI_SIZE} ]] ; then
-				dd if=/dev/zero bs=${PATCH_SIZE} count=1 | \
+				dd if=/dev/zero bs="${PATCH_SIZE}" count=1 | \
 					tr '\0' '\377'
 			fi
-		} > $T
+		} > "${T}"
 		else
 		{	# Patch temp image up to SPI_SIZE
 			if [[ ${IMG_SIZE} -lt ${SPI_SIZE} ]] ; then
-				dd if=/dev/zero bs=${PATCH_SIZE} count=1 | \
+				dd if=/dev/zero bs="${PATCH_SIZE}" count=1 | \
 					tr '\0' '\377'
 			fi
-			cat "$IMG"
-		} > $T
+			cat "${IMG}"
+		} > "${T}"
 		fi
 
 		info "Programming EC firmware image."
-		local FLASHROM_WRITE="${FLASHROM_CMDLINE} ${FLASHROM_OPTIONS}"
-		if [[ "${FLAGS_verbose}" == ${FLAGS_TRUE} ]]; then
+		local FLASHROM_WRITE=("${FLASHROM_CMDLINE[@]}" "${FLASHROM_OPTIONS[@]}")
+		if [[ "${FLAGS_verbose}" == "${FLAGS_TRUE}" ]]; then
 			info "Running flashrom:" 1>&2
-			echo " ${FLASHROM_WRITE} -w ${T}" 1>&2
+			echo " ${FLASHROM_WRITE[*]} -w ${T}" 1>&2
 		fi
 		print_or_run sudo timeout -k 10 -s 9 "${FLAGS_timeout}" \
-			${FLASHROM_WRITE} -w "${T}" \
+			"${FLASHROM_WRITE[@]}" -w "${T}" \
 			|| die "${MSG_PROGRAM_FAIL}"
 	else
 		# Read EC image.
 		info "Reading EC firmware image."
-		if [[ "${FLAGS_verbose}" == ${FLAGS_TRUE} ]]; then
+		if [[ "${FLAGS_verbose}" == "${FLAGS_TRUE}" ]]; then
 			info "Running flashrom:" 1>&2
-			echo " ${FLASHROM_CMDLINE} -r ${FLAGS_read}" 1>&2
+			echo " ${FLASHROM_CMDLINE[*]} -r ${FLAGS_read}" 1>&2
 		fi
 		print_or_run sudo timeout -k 10 -s 9 "${FLAGS_timeout}" \
-			${FLASHROM_CMDLINE} -r "${FLAGS_read}" \
+			"${FLASHROM_CMDLINE[@]}" -r "${FLAGS_read}" \
 			|| die "${MSG_READ_FAIL}"
 	fi
 }
 
 function flash_stm32() {
 	local STM32MON
-	local STM32MON_OPT
+	local STM32MON_OPT=()
 
 	if ! servo_has_cold_reset; then
 		die "Cold reset must be available for STM32 programming"
 	fi
 
-	TOOL_PATH="${EC_DIR}/build/${BOARD}/util:$PATH"
+	TOOL_PATH="${EC_DIR}/build/${BOARD}/util:${PATH}"
 	STM32MON=$(PATH="${TOOL_PATH}" which stm32mon)
 	EC_UART="$(servo_ec_uart)"
 	EC_UART_PREFIX="$(servo_ec_uart_prefix)"
-	if [ ! -x "$STM32MON" ]; then
+	if [ ! -x "${STM32MON}" ]; then
 		die "no stm32mon util found."
 	fi
 
 	info "Using serial flasher : ${STM32MON}"
 	info "${MCU} UART pty : ${EC_UART}"
-	claim_pty ${EC_UART}
-	STM32MON_OPT="-d ${EC_UART}"
+	claim_pty "${EC_UART}"
+	STM32MON_OPT+=(-d "${EC_UART}")
 
 	# Make sure EC reboots in serial monitor mode.
 	ec_enable_boot0 "bitbang"
@@ -1160,12 +1168,12 @@ function flash_stm32() {
 	# ccdstate once a second, so a 2 second delay should be safe.
 	if servo_is_ccd ; then
 		sleep 2
-		STM32MON_OPT+=" -c"
+		STM32MON_OPT+=(-c)
 	fi
 
 	if [ -n "${FLAGS_logfile}" ]; then
 		info "Saving log in ${FLAGS_logfile}"
-		STM32MON_OPT+=" -L ${FLAGS_logfile}"
+		STM32MON_OPT+=(-L "${FLAGS_logfile}")
 	fi
 
 	local IMG_READ="${FLAGS_read}"
@@ -1173,19 +1181,21 @@ function flash_stm32() {
 	if [[ -z "${IMG_READ}" ]]; then
 		info "Programming EC firmware image."
 		# Unprotect flash, erase, and write
-		local STM32MON_COMMAND="${STM32MON} ${STM32MON_OPT} -U -u -e -w"
-		if [[ "${FLAGS_verbose}" == ${FLAGS_TRUE} ]]; then
-			echo "${STM32MON_COMMAND} ${IMG}"
+		local STM32MON_COMMAND=("${STM32MON}" "${STM32MON_OPT[@]}" -U -u -e -w)
+		if [[ "${FLAGS_verbose}" == "${FLAGS_TRUE}" ]]; then
+			echo "${STM32MON_COMMAND[*]} ${IMG}"
 		fi
 		print_or_run timeout -k 10 -s 9 "${FLAGS_timeout}" \
-			${STM32MON_COMMAND} "${IMG}" \
+			"${STM32MON_COMMAND[@]}" "${IMG}" \
 			|| die "${MSG_PROGRAM_FAIL}"
 
 		# If it is a program-verify request, then make a temporary
 		# directory to store the image
-		if [[ "${FLAGS_verify}" == ${FLAGS_TRUE} ]]; then
-			local TEMP_SUFFIX=".$(basename ${SCRIPT}).${CHIP}"
-			local TEMP_DIR="$(mktemp -d --suffix="${TEMP_SUFFIX}")"
+		if [[ "${FLAGS_verify}" == "${FLAGS_TRUE}" ]]; then
+			local TEMP_SUFFIX
+			local TEMP_DIR
+			TEMP_SUFFIX=".$(basename "${SCRIPT}").${CHIP}"
+			TEMP_DIR="$(mktemp -d --suffix="${TEMP_SUFFIX}")"
 
 			IMG_READ="${TEMP_DIR}/ec.read.bin"
 			DELETE_LIST+=( "${TEMP_DIR}" )
@@ -1195,20 +1205,20 @@ function flash_stm32() {
 	# Read EC image.
 	if [[ -n "${IMG_READ}" ]]; then
 		info "Reading EC firmware image."
-		local STM32MON_READ_CMD="${STM32MON} ${STM32MON_OPT} -U -r"
-		if [[ "${FLAGS_verbose}" == ${FLAGS_TRUE} ]]; then
-			echo "${STM32MON_READ_CMD} ${IMG_READ}"
+		local STM32MON_READ_CMD=("${STM32MON}" "${STM32MON_OPT[@]}" -U -r)
+		if [[ "${FLAGS_verbose}" == "${FLAGS_TRUE}" ]]; then
+			echo "${STM32MON_READ_CMD[*]} ${IMG_READ}"
 		fi
 		print_or_run timeout -k 10 -s 9 "${FLAGS_timeout}" \
-			${STM32MON_READ_CMD} "${IMG_READ}" \
+			"${STM32MON_READ_CMD[@]}" "${IMG_READ}" \
 			|| die "${MSG_READ_FAIL}"
 	fi
 
 	# Verify the flash by comparing the source image to the read image,
 	# only if it was a flash write request.
-	if [[ -z "${FLAGS_read}" && "${FLAGS_verify}" == ${FLAGS_TRUE} ]]; then
+	if [[ -z "${FLAGS_read}" && "${FLAGS_verify}" == "${FLAGS_TRUE}" ]]; then
 		info "Verifying EC firmware image."
-		if [[ "${FLAGS_verbose}" == ${FLAGS_TRUE} ]]; then
+		if [[ "${FLAGS_verbose}" == "${FLAGS_TRUE}" ]]; then
 			echo "cmp -n ${IMG_SIZE} ${IMG} ${IMG_READ}"
 		fi
 		cmp -s -n "${IMG_SIZE}" "${IMG}" "${IMG_READ}" \
@@ -1226,41 +1236,42 @@ function flash_stm32_dfu() {
 	DFU_DEVICE=0483:df11
 	ADDR=0x08000000
 	DFU_UTIL='dfu-util'
-	which $DFU_UTIL &> /dev/null || die \
+	which "${DFU_UTIL}" &> /dev/null || die \
 		"no dfu-util util found.  Did you 'sudo emerge dfu-util'"
 
 	info "Using dfu flasher : ${DFU_UTIL}"
 
-	dev_cnt=$(lsusb -d $DFU_DEVICE | wc -l)
-	if [ $dev_cnt -eq 0 ] ; then
-		die "unable to locate dfu device at $DFU_DEVICE"
-	elif [ $dev_cnt -ne 1 ] ; then
+	dev_cnt=$(lsusb -d "${DFU_DEVICE}" | wc -l)
+	if [ "${dev_cnt}" -eq 0 ] ; then
+		die "unable to locate dfu device at ${DFU_DEVICE}"
+	elif [ "${dev_cnt}" -ne 1 ] ; then
 		die "too many dfu devices (${dev_cnt}). Disconnect all but one."
 	fi
 
-	SIZE=$(wc -c ${IMG} | cut -d' ' -f1)
+	SIZE=$(wc -c "${IMG}" | cut -d' ' -f1)
 	# Remove read protection
-	print_or_run sudo timeout -k 10 -s 9 "${FLAGS_timeout}" $DFU_UTIL -a 0 \
-		-d "${DFU_DEVICE}" -s ${ADDR}:${SIZE}:force:unprotect -D "${IMG}"
+	print_or_run sudo timeout -k 10 -s 9 "${FLAGS_timeout}" "${DFU_UTIL}" -a 0 \
+		-d "${DFU_DEVICE}" -s "${ADDR}:${SIZE}:force:unprotect" -D "${IMG}"
 	# Wait for mass-erase and reboot after unprotection
 	print_or_run sleep 1
 	# Actual image flashing
-	print_or_run sudo timeout -k 10 -s 9 "${FLAGS_timeout}" $DFU_UTIL -a 0 \
-		-d "${DFU_DEVICE}" -s ${ADDR}:${SIZE} -D "${IMG}"
+	print_or_run sudo timeout -k 10 -s 9 "${FLAGS_timeout}" "${DFU_UTIL}" -a 0 \
+		-d "${DFU_DEVICE}" -s "${ADDR}:${SIZE}" -D "${IMG}"
 }
 
 function dut_i2c_dev() {
-	if [ -n "$DUT_I2C_DEV" ]; then
-		[ -e "$DUT_I2C_DEV" ] ||
-			die "\$DUT_I2C_DEV is a non-existent path: $DUT_I2C_DEV"
-		echo "$DUT_I2C_DEV"
+	if [ -n "${DUT_I2C_DEV}" ]; then
+		[ -e "${DUT_I2C_DEV}" ] ||
+			die "\$DUT_I2C_DEV is a non-existent path: ${DUT_I2C_DEV}"
+		echo "${DUT_I2C_DEV}"
 		return
 	fi
 
-	local has_i2c_pseudo="$(dut_control_get_or_die \
+	local has_i2c_pseudo
+	has_i2c_pseudo="$(dut_control_get_or_die \
 		"${ACTIVE_DEVICE}_i2c_pseudo_is_running")"
 	if [[ "${has_i2c_pseudo}" == False ]]; then
-		error "i2c-pseudo module is not running."
+		error "i2c-pseudo module is not running on ${ACTIVE_DEVICE}."
 		error "Please follow https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/util/iteflash.md#i2c-pseudo"
 		die "to install i2c-pseudo module."
 	fi
@@ -1268,14 +1279,15 @@ function dut_i2c_dev() {
 	local adap_num=
 	adap_num="$(dut_control_get_or_die \
 	    "${ACTIVE_DEVICE}_i2c_pseudo_adapter_num")"
-	echo /dev/i2c-"$adap_num"
+	echo /dev/i2c-"${adap_num}"
 }
 
 function flash_it83xx() {
-	local TOOL_PATH="${EC_DIR}/build/${BOARD}/util:$PATH"
-	local ITEFLASH_BIN=$(PATH="${TOOL_PATH}" which iteflash)
+	local TOOL_PATH="${EC_DIR}/build/${BOARD}/util:${PATH}"
+	local ITEFLASH_BIN
+	ITEFLASH_BIN=$(PATH="${TOOL_PATH}" which iteflash)
 
-	if [[ ! -x "$ITEFLASH_BIN" ]]; then
+	if [[ ! -x "${ITEFLASH_BIN}" ]]; then
 		die "no iteflash util found."
 	fi
 
@@ -1291,7 +1303,10 @@ function flash_it83xx() {
 		dut_control_or_die i2c_ec_bus_speed:400
 
 		# We need to swing the DUT-side muxes to I2C instead of UART.
-		# This is done by convention with EC_FLASH_SELECT pin from H1
+		# This is done by convention with EC_FLASH_SELECT pin of the
+		# GSC. Also make sure that the setting is restored after
+		# completion.
+		servo_save_add "ec_flash_select" "off"
 		dut_control_or_die ec_flash_select:on
 	fi
 
@@ -1318,7 +1333,8 @@ function flash_it83xx() {
 		info "Asking servo to send the dbgr special waveform to ${CHIP}"
 		dut_control_or_die enable_ite_dfu
 	elif servo_is_ccd; then
-		local CCD_I2C_CAP="$(dut_control_get ccd_i2c_en)"
+		local CCD_I2C_CAP
+		CCD_I2C_CAP="$(dut_control_get ccd_i2c_en)"
 		if [[ "${CCD_I2C_CAP,,}" != "always" ]]; then
 			die "CCD I2C capability is not set as 'Always'" \
 				": ${CCD_I2C_CAP}"
@@ -1364,7 +1380,7 @@ function flash_it83xx() {
 		ITEFLASH_ARGS+=( "--noverify" )
 	fi
 
-	if [[ "${FLAGS_verbose}" == ${FLAGS_TRUE} ]]; then
+	if [[ "${FLAGS_verbose}" == "${FLAGS_TRUE}" ]]; then
 		ITEFLASH_ARGS+=( "--debug" )
 		echo "${ITEFLASH_ARGS[@]}"
 	fi
@@ -1393,10 +1409,14 @@ function flash_ite_spi_ccd_i2c() {
 	fi
 }
 
+function flash_it8xxx2() {
+	flash_ite_spi_ccd_i2c
+}
+
 function flash_npcx_jtag() {
 	IMG_PATH="${EC_DIR}/build/${BOARD}"
 	OCD_CHIP_CFG="npcx_chip.cfg"
-	if [ "${FLAGS_ro}" = ${FLAGS_TRUE} ] ; then
+	if [ "${FLAGS_ro}" = "${FLAGS_TRUE}" ] ; then
 		# Program RO region only
 		OCD_CMDS="init; flash_npcx_ro ${CHIP} ${IMG_PATH} ${FLAGS_offset}; shutdown;"
 	else
@@ -1411,23 +1431,25 @@ function flash_npcx_jtag() {
 }
 
 function flash_npcx_uut() {
-	local TOOL_PATH="${EC_DIR}/build/${BOARD}/util:$PATH"
-	local NPCX_UUT=$(PATH="${TOOL_PATH}" which uartupdatetool)
-	local EC_UART="$(servo_ec_uart)"
+	local NPCX_UUT
+	local EC_UART
+	local TOOL_PATH="${EC_DIR}/build/${BOARD}/util:${PATH}"
+	NPCX_UUT=$(PATH="${TOOL_PATH}" which uartupdatetool)
+	EC_UART="$(servo_ec_uart)"
 
 	# Look for npcx_monitor.bin in multiple directories, starting with
 	# the same path as the EC binary.
 	local MON=""
 	for dir in \
-		"$(dirname "$IMG")/chip/npcx/spiflashfw" \
-		"$(dirname "$IMG")" \
+		"$(dirname "${IMG}")/chip/npcx/spiflashfw" \
+		"$(dirname "${IMG}")" \
 		"${EC_DIR}/build/${BOARD}/chip/npcx/spiflashfw" \
 		"${EC_DIR}/build/zephyr/${BOARD}/output" \
-		"$(dirname "$LOCAL_BUILD")" \
-		"$(dirname "$EMERGE_BUILD")" ;
+		"$(dirname "${LOCAL_BUILD}")" \
+		"$(dirname "${EMERGE_BUILD}")" ;
 	do
-		if [ -f "$dir/npcx_monitor.bin" ] ; then
-			MON="$dir/npcx_monitor.bin"
+		if [ -f "${dir}/npcx_monitor.bin" ] ; then
+			MON="${dir}/npcx_monitor.bin"
 			break
 		fi
 	done
@@ -1440,13 +1462,13 @@ function flash_npcx_uut() {
 	# The start address to restore monitor firmware binary
 	local MON_ADDR="0x200C3020"
 
-	if [ ! -x "$NPCX_UUT" ]; then
+	if [ ! -x "${NPCX_UUT}" ]; then
 		die "no NPCX UART Update Tool found."
 	fi
 
 	info "Using: NPCX UART Update Tool"
 	info "${MCU} UART pty : ${EC_UART}"
-	claim_pty ${EC_UART}
+	claim_pty "${EC_UART}"
 
 	if [[ "${SERVO_TYPE}" =~ "ccd_cr50" ]] ; then
 		# Ti50 does not yet support ccd_keepalive option which
@@ -1495,7 +1517,7 @@ function flash_npcx_uut() {
 				"--file=${MON}" )
 
 		# Load monitor binary to address 0x200C3020
-		if [[ "${FLAGS_verbose}" = ${FLAGS_TRUE} ]]; then
+		if [[ "${FLAGS_verbose}" = "${FLAGS_TRUE}" ]]; then
 			echo "${UUT_MON[*]}"
 		fi
 
@@ -1523,7 +1545,7 @@ function flash_npcx_uut() {
 		local UUT_WR=( "${NPCX_UUT}" "${UUT_ARGS[@]}"      \
 			       "--auto" "--offset=${FLAGS_offset}" \
 			       "--file=${IMG}" )
-		if [[ "${FLAGS_verbose}" = ${FLAGS_TRUE} ]]; then
+		if [[ "${FLAGS_verbose}" = "${FLAGS_TRUE}" ]]; then
 			echo "${UUT_WR[*]}"
 		fi
 		print_or_run timeout -k 10 -s 9 "${FLAGS_timeout}" \
@@ -1531,9 +1553,11 @@ function flash_npcx_uut() {
 
 		# If it is a program-verify request, then make a temporary
 		# directory to store the image.
-		if [[ "${FLAGS_verify}" == ${FLAGS_TRUE} ]]; then
-			local TEMP_SUFFIX=".$(basename ${SCRIPT}).${CHIP}.$$"
-			local TEMP_DIR="$(mktemp -d --suffix="${TEMP_SUFFIX}")"
+		if [[ "${FLAGS_verify}" == "${FLAGS_TRUE}" ]]; then
+			local TEMP_SUFFIX
+			local TEMP_DIR
+			TEMP_SUFFIX=".$(basename "${SCRIPT}").${CHIP}.$$"
+			TEMP_DIR="$(mktemp -d --suffix="${TEMP_SUFFIX}")"
 
 			IMG_READ="${TEMP_DIR}/ec.read.bin"
 			DELETE_LIST+=( "${TEMP_DIR}" )
@@ -1547,7 +1571,7 @@ function flash_npcx_uut() {
 		local UUT_RD=( "${NPCX_UUT}" "${UUT_ARGS[@]}"   \
 			      "--read-flash" "--file=${IMG_READ}" )
 
-		if [[ "${FLAGS_verbose}" == ${FLAGS_TRUE} ]]; then
+		if [[ "${FLAGS_verbose}" == "${FLAGS_TRUE}" ]]; then
 			echo "${UUT_RD[*]}"
 		fi
 		print_or_run timeout -k 10 -s 9 "${FLAGS_timeout}" \
@@ -1556,10 +1580,10 @@ function flash_npcx_uut() {
 
 	# Verify the flash by comparing the source image to the read image,
 	# only if it was a flash write request.
-	if [[ -z "${FLAGS_read}" && "${FLAGS_verify}" == ${FLAGS_TRUE} ]]; then
+	if [[ -z "${FLAGS_read}" && "${FLAGS_verify}" == "${FLAGS_TRUE}" ]]; then
 		info "Verifying EC firmware image."
 
-		if [[ "${FLAGS_verbose}" == ${FLAGS_TRUE} ]]; then
+		if [[ "${FLAGS_verbose}" == "${FLAGS_TRUE}" ]]; then
 			echo "cmp -n ${IMG_SIZE} ${IMG} ${IMG_READ}"
 		fi
 
@@ -1610,5 +1634,5 @@ if [ "${NEED_SERVO}" != "no" ] ; then
 fi
 
 info "Flashing chip ${CHIP}."
-flash_${CHIP}
+flash_"${CHIP}"
 info "Flashing done."
diff --git a/util/flash_fp_mcu b/util/flash_fp_mcu
index 75a989e1f4..a823174c94 100644
--- a/util/flash_fp_mcu
+++ b/util/flash_fp_mcu
@@ -1,5 +1,5 @@
 #!/bin/bash
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -430,19 +430,7 @@ flash_fp_mcu_stm32() {
   fi
 
   # Go back to normal mode
-  gpio out "${gpio_nrst}"
-  gpio 0   "${gpio_boot0}" "${gpio_nrst}"
-  gpio 1   "${gpio_nrst}"
-
-  # Give up GPIO control, unless we need to keep these driving as
-  # outputs because they're not open-drain signals.
-  # TODO(b/179839337): Make this the default and properly support
-  # open-drain outputs on other platforms.
-  if [[ "${PLATFORM_BASE_NAME}" != "strongbad" ]] &&
-     [[ "${PLATFORM_BASE_NAME}" != "herobrine" ]]; then
-    gpio in       "${gpio_boot0}" "${gpio_nrst}"
-  fi
-  gpio unexport "${gpio_boot0}" "${gpio_nrst}"
+  gpio 0   "${gpio_boot0}"
 
   # Dartmonkey's RO has a flashprotect logic issue that forces reboot loops
   # when SW-WP is enabled and HW-WP is disabled. It is avoided if a POR is
@@ -458,8 +446,25 @@ flash_fp_mcu_stm32() {
     gpio 1      "${gpio_pwren}"
     # Power enable line is externally pulled down, so leave as output-high.
     gpio unexport "${gpio_pwren}"
+  else
+    echo "Reset the FPMCU."
+    gpio out	"${gpio_nrst}"
+    gpio 0	"${gpio_nrst}"
+    # Make sure that we keep nRST line low long enough.
+    sleep 0.01
+    gpio 1	"${gpio_nrst}"
   fi
 
+  # Give up GPIO control, unless we need to keep these driving as
+  # outputs because they're not open-drain signals.
+  # TODO(b/179839337): Make this the default and properly support
+  # open-drain outputs on other platforms.
+  if [[ "${PLATFORM_BASE_NAME}" != "strongbad" ]] &&
+     [[ "${PLATFORM_BASE_NAME}" != "herobrine" ]]; then
+    gpio in       "${gpio_boot0}" "${gpio_nrst}"
+  fi
+  gpio unexport "${gpio_boot0}" "${gpio_nrst}"
+
   # Put back cros_fp driver if transport is SPI
   if [[ "${transport}" != "UART" ]]; then
     # wait for FP MCU to come back up (including RWSIG delay)
@@ -467,6 +472,18 @@ flash_fp_mcu_stm32() {
     klog "Binding cros-ec driver"
     echo "" > "/sys/bus/spi/devices/${deviceid}/driver_override"
     echo "${deviceid}" > /sys/bus/spi/drivers/cros-ec-spi/bind
+  else
+    # FPMCU can still have ro_now protection (sector write protection) enabled
+    # e.g. when flash_fp_mcu was run with --read option. It is disabled when
+    # FPMCU boots with HW write protect disabled.
+    # Disabling sector write protection takes some time due to flash internal
+    # structures update. During that time we can't reset or power cycle FPMCU
+    # otherwise we will corrupt internal flash state which will brick FPMCU.
+    # This situation can occur if DUT is rebooted immediately after flash_fp_mcu
+    # finishes, so give some time to remove sector write protection. No need to
+    # wait if transport is SPI because later we query for version and reset
+    # flags.
+    sleep 3
   fi
 
   if [[ "${cmd_exit_status}" -ne 0 ]]; then
@@ -493,13 +510,25 @@ config_hatch() {
   # for pin name to number mapping.
   # Examine `cat /sys/kernel/debug/pinctrl/INT34BB:00/gpio-ranges` on a hatch
   # device to determine gpio number from pin number.
-  readonly GPIO_CHIP="gpiochip200"
-  # FPMCU RST_ODL is on GPP_A12 = 200 + 12 = 212
-  readonly GPIO_NRST=212
-  # FPMCU BOOT0 is on GPP_A22 = 200 + 22 = 222
-  readonly GPIO_BOOT0=222
-  # FP_PWR_EN is on GPP_C11 = 456 + (192 - 181) = 456 + 11 = 467
-  readonly GPIO_PWREN=467
+ 
+  local gpiochip="gpiochip712"
+  # Support kernel version 4.x, 5.4 and 5.10 during transition to 5.15+
+  match_kernel_regex "^((4\..)|(5\.4\.)|(5\.10\.))" && gpiochip="gpiochip200"
+  readonly GPIO_CHIP="${gpiochip}"
+  local offset=0
+  # Support kernel version 4.x, 5.4 and 5.10 during transition to 5.15+
+  # v4.4 has GPIOs that are offset by -512
+  match_kernel_regex "^((4\..)|(5\.4\.)|(5\.10\.))" && offset=512
+  
+  # FPMCU RST_ODL is on GPP_A12 = 712 + 12 = 724
+  local gpionrst=724
+  readonly GPIO_NRST=$(( gpionrst - offset ))
+  # FPMCU BOOT0 is on GPP_A22 = 712 + 22 = 734
+  local gpioboot=734
+  readonly GPIO_BOOT0=$(( gpioboot - offset ))
+  # FP_PWR_EN is on GPP_C11 = 968 + (192 - 181) = 968 + 11 = 979
+  local gpiopwren=979
+  readonly GPIO_PWREN=$(( gpiopwren - offset ))
 }
 
 config_herobrine() {
@@ -542,26 +571,13 @@ config_nami() {
   readonly GPIO_PWREN=395
 }
 
-config_nami-kernelnext() {
-  config_nami
-}
-
 config_nocturne() {
-  readonly TRANSPORT="SPI"
-  readonly DEVICE="/dev/spidev32765.0"
-
-  readonly GPIO_CHIP="gpiochip360"
-  # FPMCU RST_ODL is on GPP_C10 = 360 + 58 = 418
-  readonly GPIO_NRST=418
-  # FPMCU BOOT0 is on GPP_C8 = 360 + 56 = 416
-  readonly GPIO_BOOT0=416
-  # FP_PWR_EN is on GPP_A11 = 360 + 11 = 371
-  readonly GPIO_PWREN=371
-}
+  local device="/dev/spidev1.0"
+  # Support kernel version 4.4 during transition to 5.10
+  match_kernel_regex "^4\.4\." && device="/dev/spidev32765.0"
 
-config_nocturne-kernelnext() {
   readonly TRANSPORT="SPI"
-  readonly DEVICE="/dev/spidev1.0"
+  readonly DEVICE="${device}"
 
   readonly GPIO_CHIP="gpiochip360"
   # FPMCU RST_ODL is on GPP_C10 = 360 + 58 = 418
@@ -610,15 +626,26 @@ config_volteer() {
   # volteer device to determine gpio number from pin number.
   # For example: GPP_C23 is UART2_CTS which can be queried from EDS
   # the pin number is 194. From the gpio-ranges, the gpio value is
-  # 408 + (194-171) = 431
-
-  readonly GPIO_CHIP="gpiochip152"
-  # FPMCU RST_ODL is on GPP_C23 = 408 + (194 - 171) = 431
-  readonly GPIO_NRST=431
-  # FPMCU BOOT0 is on GPP_C22 = 408 + (193 - 171) = 430
-  readonly GPIO_BOOT0=430
-  # FP_PWR_EN is on GPP_A21 = 216 + (63 - 42) = 237
-  readonly GPIO_PWREN=237
+  # 920 + (194-171) = 943
+
+  local gpiochip="gpiochip664"
+  # Support kernel version 4.x, 5.4, 5.10 during transition to 5.15+
+  match_kernel_regex "^((4\..)|(5\.4\.)|(5\.10\..))" && gpiochip="gpiochip152"
+  readonly GPIO_CHIP="${gpiochip}"
+  local offset=0
+  # Support kernel version 4.x, 5.4, 5.10 during transition to 5.15+
+  # v4.4 has GPIOs that are offset by -512
+  match_kernel_regex "^((4\..)|(5\.4\.)|(5\.10\.))" && offset=512
+
+  # FPMCU RST_ODL is on GPP_C23 = 920 + (194 - 171) = 943
+  local gpionrst=943
+  readonly GPIO_NRST=$(( gpionrst - offset ))
+  # FPMCU BOOT0 is on GPP_C22 = 920 + (193 - 171) = 942
+  local gpioboot=942
+  readonly GPIO_BOOT0=$(( gpioboot - offset ))
+  # FP_PWR_EN is on GPP_A21 = 728 + (63 - 42) = 749
+  local gpiopwren=749
+  readonly GPIO_PWREN=$(( gpiopwren - offset ))
 }
 
 config_brya() {
@@ -631,15 +658,27 @@ config_brya() {
   # brya device to determine gpio number from pin number.
   # For example: GPP_D1 is ISH_GP_1 which can be queried from EDS
   # the pin number is 100 from the pinctrl-tigerlake.c.
-  # From the gpio-ranges, the gpio value is 312 + (100-99) = 313
-
-  readonly GPIO_CHIP="gpiochip152"
-  # FPMCU RST_ODL is on GPP_D1 = 312 + (100 - 99) = 313
-  readonly GPIO_NRST=313
-  # FPMCU BOOT0 is on GPP_D0 = 312 + (99 - 99) = 312
-  readonly GPIO_BOOT0=312
-  # FP_PWR_EN is on GPP_D2 = 312 + (101 - 99) = 314
-  readonly GPIO_PWREN=314
+  # From the gpio-ranges, the gpio value is 824 + (100-99) = 825
+
+  local gpiochip="gpiochip664"
+  # Support kernel version 5.10 during transition to 5.15+
+  match_kernel_regex "^5\.10\." && gpiochip="gpiochip152"
+  readonly GPIO_CHIP="${gpiochip}"
+
+  local offset=0
+  # Support kernel version 5.10 during transition to 5.15+
+  # v5.10 has GPIOs that are offset by -512
+  match_kernel_regex "^5\.10\." && offset=512
+
+  # FPMCU RST_ODL is on GPP_D1 = 824 + (100 - 99) = 825
+  local gpionrst=825
+  readonly GPIO_NRST=$(( gpionrst - offset ))
+  # FPMCU BOOT0 is on GPP_D0 = 824 + (99 - 99) = 824
+  local gpioboot=824
+  readonly GPIO_BOOT0=$(( gpioboot - offset ))
+  # FP_PWR_EN is on GPP_D2 = 824 + (101 - 99) = 826
+  local gpiopwren=826
+  readonly GPIO_PWREN=$(( gpiopwren - offset ))
 }
 
 config_brask() {
@@ -647,6 +686,11 @@ config_brask() {
   config_brya
 }
 
+config_ghost() {
+  # No changes to brya.
+  config_brya
+}
+
 config_zork() {
   readonly TRANSPORT="UART"
   readonly DEVICE="/dev/ttyS1"
@@ -674,6 +718,20 @@ config_guybrush() {
   readonly GPIO_PWREN=259
 }
 
+config_skyrim() {
+  readonly TRANSPORT="UART"
+
+  readonly DEVICE="/dev/ttyS1"
+
+  readonly GPIO_CHIP="gpiochip768"
+  # FPMCU RST_ODL is on AGPIO 12 = 768 + 12 = 780
+  readonly GPIO_NRST=780
+  # FPMCU BOOT0 is on AGPIO 130 = 768 + 130 = 898
+  readonly GPIO_BOOT0=898
+  # FPMCU PWR_EN is on AGPIO 4 = 768 + 4 = 772
+  readonly GPIO_PWREN=772
+}
+
 main() {
   local filename="$1"
 
diff --git a/util/flash_jlink.py b/util/flash_jlink.py
index 26c3c2e709..dc462e354b 100755
--- a/util/flash_jlink.py
+++ b/util/flash_jlink.py
@@ -1,6 +1,6 @@
 #!/usr/bin/env python3
 
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -25,7 +25,6 @@ import sys
 import tempfile
 import time
 
-
 DEFAULT_SEGGER_REMOTE_PORT = 19020
 
 # Commands are documented here: https://wiki.segger.com/J-Link_Commander
@@ -41,27 +40,34 @@ exit
 
 class BoardConfig:
     """Board configuration."""
+
     def __init__(self, interface, device, flash_address):
         self.interface = interface
         self.device = device
         self.flash_address = flash_address
 
 
-SWD_INTERFACE = 'SWD'
-STM32_DEFAULT_FLASH_ADDRESS = '0x8000000'
-DRAGONCLAW_CONFIG = BoardConfig(interface=SWD_INTERFACE, device='STM32F412CG',
-                                flash_address=STM32_DEFAULT_FLASH_ADDRESS)
-ICETOWER_CONFIG = BoardConfig(interface=SWD_INTERFACE, device='STM32H743ZI',
-                              flash_address=STM32_DEFAULT_FLASH_ADDRESS)
+SWD_INTERFACE = "SWD"
+STM32_DEFAULT_FLASH_ADDRESS = "0x8000000"
+DRAGONCLAW_CONFIG = BoardConfig(
+    interface=SWD_INTERFACE,
+    device="STM32F412CG",
+    flash_address=STM32_DEFAULT_FLASH_ADDRESS,
+)
+ICETOWER_CONFIG = BoardConfig(
+    interface=SWD_INTERFACE,
+    device="STM32H743ZI",
+    flash_address=STM32_DEFAULT_FLASH_ADDRESS,
+)
 
 BOARD_CONFIGS = {
-    'dragonclaw': DRAGONCLAW_CONFIG,
-    'bloonchipper': DRAGONCLAW_CONFIG,
-    'nucleo-f412zg': DRAGONCLAW_CONFIG,
-    'dartmonkey': ICETOWER_CONFIG,
-    'icetower': ICETOWER_CONFIG,
-    'nucleo-dartmonkey': ICETOWER_CONFIG,
-    'nucleo-h743zi': ICETOWER_CONFIG,
+    "dragonclaw": DRAGONCLAW_CONFIG,
+    "bloonchipper": DRAGONCLAW_CONFIG,
+    "nucleo-f412zg": DRAGONCLAW_CONFIG,
+    "dartmonkey": ICETOWER_CONFIG,
+    "icetower": ICETOWER_CONFIG,
+    "nucleo-dartmonkey": ICETOWER_CONFIG,
+    "nucleo-h743zi": ICETOWER_CONFIG,
 }
 
 
@@ -93,9 +99,11 @@ def is_tcp_port_open(host: str, tcp_port: int) -> bool:
 
 def create_jlink_command_file(firmware_file, config):
     tmp = tempfile.NamedTemporaryFile()
-    tmp.write(JLINK_COMMANDS.format(FIRMWARE=firmware_file,
-                                    FLASH_ADDRESS=config.flash_address).encode(
-                                        'utf-8'))
+    tmp.write(
+        JLINK_COMMANDS.format(
+            FIRMWARE=firmware_file, FLASH_ADDRESS=config.flash_address
+        ).encode("utf-8")
+    )
     tmp.flush()
     return tmp
 
@@ -106,8 +114,8 @@ def flash(jlink_exe, remote, device, interface, cmd_file):
     ]
 
     if remote:
-        logging.debug(f'Connecting to J-Link over TCP/IP {remote}.')
-        remote_components = remote.split(':')
+        logging.debug(f"Connecting to J-Link over TCP/IP {remote}.")
+        remote_components = remote.split(":")
         if len(remote_components) not in [1, 2]:
             logging.debug(f'Given remote "{remote}" is malformed.')
             return 1
@@ -118,7 +126,7 @@ def flash(jlink_exe, remote, device, interface, cmd_file):
         except socket.gaierror as e:
             logging.error(f'Failed to resolve host "{host}": {e}.')
             return 1
-        logging.debug(f'Resolved {host} as {ip}.')
+        logging.debug(f"Resolved {host} as {ip}.")
         port = DEFAULT_SEGGER_REMOTE_PORT
 
         if len(remote_components) == 2:
@@ -126,29 +134,40 @@ def flash(jlink_exe, remote, device, interface, cmd_file):
                 port = int(remote_components[1])
             except ValueError:
                 logging.error(
-                    f'Given remote port "{remote_components[1]}" is malformed.')
+                    f'Given remote port "{remote_components[1]}" is malformed.'
+                )
                 return 1
 
-        remote = f'{ip}:{port}'
+        remote = f"{ip}:{port}"
 
-        logging.debug(f'Checking connection to {remote}.')
+        logging.debug(f"Checking connection to {remote}.")
         if not is_tcp_port_open(ip, port):
             logging.error(
-                f"JLink server doesn't seem to be listening on {remote}.")
-            logging.error('Ensure that JLinkRemoteServerCLExe is running.')
+                f"JLink server doesn't seem to be listening on {remote}."
+            )
+            logging.error("Ensure that JLinkRemoteServerCLExe is running.")
             return 1
-        cmd.extend(['-ip', remote])
-
-    cmd.extend([
-        '-device', device,
-        '-if', interface,
-        '-speed', 'auto',
-        '-autoconnect', '1',
-        '-CommandFile', cmd_file,
-        ])
-    logging.debug('Running command: "%s"', ' '.join(cmd))
-    completed_process = subprocess.run(cmd)  # pylint: disable=subprocess-run-check
-    logging.debug('JLink return code: %d', completed_process.returncode)
+        cmd.extend(["-ip", remote])
+
+    cmd.extend(
+        [
+            "-device",
+            device,
+            "-if",
+            interface,
+            "-speed",
+            "auto",
+            "-autoconnect",
+            "1",
+            "-CommandFile",
+            cmd_file,
+        ]
+    )
+    logging.debug('Running command: "%s"', " ".join(cmd))
+    completed_process = subprocess.run(
+        cmd
+    )  # pylint: disable=subprocess-run-check
+    logging.debug("JLink return code: %d", completed_process.returncode)
     return completed_process.returncode
 
 
@@ -156,36 +175,42 @@ def main(argv: list):
 
     parser = argparse.ArgumentParser()
 
-    default_jlink = './JLink_Linux_V684a_x86_64/JLinkExe'
+    default_jlink = "./JLink_Linux_V684a_x86_64/JLinkExe"
     if shutil.which(default_jlink) is None:
-        default_jlink = 'JLinkExe'
+        default_jlink = "JLinkExe"
     parser.add_argument(
-        '--jlink', '-j',
-        help='JLinkExe path (default: ' + default_jlink + ')',
-        default=default_jlink)
+        "--jlink",
+        "-j",
+        help="JLinkExe path (default: " + default_jlink + ")",
+        default=default_jlink,
+    )
 
     parser.add_argument(
-        '--remote', '-n',
-        help='Use TCP/IP host[:port] to connect to a J-Link or '
-        'JLinkRemoteServerCLExe. If unspecified, connect over USB.')
+        "--remote",
+        "-n",
+        help="Use TCP/IP host[:port] to connect to a J-Link or "
+        "JLinkRemoteServerCLExe. If unspecified, connect over USB.",
+    )
 
-    default_board = 'bloonchipper'
+    default_board = "bloonchipper"
     parser.add_argument(
-        '--board', '-b',
-        help='Board (default: ' + default_board + ')',
-        default=default_board)
+        "--board",
+        "-b",
+        help="Board (default: " + default_board + ")",
+        default=default_board,
+    )
 
-    default_firmware = os.path.join('./build', default_board, 'ec.bin')
+    default_firmware = os.path.join("./build", default_board, "ec.bin")
     parser.add_argument(
-        '--image', '-i',
-        help='Firmware binary (default: ' + default_firmware + ')',
-        default=default_firmware)
+        "--image",
+        "-i",
+        help="Firmware binary (default: " + default_firmware + ")",
+        default=default_firmware,
+    )
 
-    log_level_choices = ['DEBUG', 'INFO', 'WARNING', 'ERROR', 'CRITICAL']
+    log_level_choices = ["DEBUG", "INFO", "WARNING", "ERROR", "CRITICAL"]
     parser.add_argument(
-        '--log_level', '-l',
-        choices=log_level_choices,
-        default='DEBUG'
+        "--log_level", "-l", choices=log_level_choices, default="DEBUG"
     )
 
     args = parser.parse_args(argv)
@@ -201,11 +226,12 @@ def main(argv: list):
     args.jlink = args.jlink
 
     cmd_file = create_jlink_command_file(args.image, config)
-    ret_code = flash(args.jlink, args.remote, config.device, config.interface,
-                     cmd_file.name)
+    ret_code = flash(
+        args.jlink, args.remote, config.device, config.interface, cmd_file.name
+    )
     cmd_file.close()
     return ret_code
 
 
-if __name__ == '__main__':
+if __name__ == "__main__":
     sys.exit(main(sys.argv[1:]))
diff --git a/util/fptool.py b/util/fptool.py
index 5d73302bbc..ba00c0020a 100755
--- a/util/fptool.py
+++ b/util/fptool.py
@@ -1,5 +1,5 @@
 #!/usr/bin/env python3
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -19,14 +19,14 @@ def cmd_flash(args: argparse.Namespace) -> int:
     disabled.
     """
 
-    if not shutil.which('flash_fp_mcu'):
-        print('Error - The flash_fp_mcu utility does not exist.')
+    if not shutil.which("flash_fp_mcu"):
+        print("Error - The flash_fp_mcu utility does not exist.")
         return 1
 
-    cmd = ['flash_fp_mcu']
+    cmd = ["flash_fp_mcu"]
     if args.image:
         if not os.path.isfile(args.image):
-            print(f'Error - image {args.image} is not a file.')
+            print(f"Error - image {args.image} is not a file.")
             return 1
         cmd.append(args.image)
 
@@ -38,18 +38,19 @@ def cmd_flash(args: argparse.Namespace) -> int:
 
 def main(argv: list) -> int:
     parser = argparse.ArgumentParser(description=__doc__)
-    subparsers = parser.add_subparsers(dest='subcommand', title='subcommands')
+    subparsers = parser.add_subparsers(dest="subcommand", title="subcommands")
     # This method of setting required is more compatible with older python.
     subparsers.required = True
 
     # Parser for "flash" subcommand.
-    parser_decrypt = subparsers.add_parser('flash', help=cmd_flash.__doc__)
+    parser_decrypt = subparsers.add_parser("flash", help=cmd_flash.__doc__)
     parser_decrypt.add_argument(
-        'image', nargs='?', help='Path to the firmware image')
+        "image", nargs="?", help="Path to the firmware image"
+    )
     parser_decrypt.set_defaults(func=cmd_flash)
     opts = parser.parse_args(argv)
     return opts.func(opts)
 
 
-if __name__ == '__main__':
+if __name__ == "__main__":
     sys.exit(main(sys.argv[1:]))
diff --git a/util/gdbinit b/util/gdbinit
index ff71e4c39c..1854b4bdc0 100644
--- a/util/gdbinit
+++ b/util/gdbinit
@@ -1,4 +1,4 @@
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/util/gen_emmc_transfer_data.c b/util/gen_emmc_transfer_data.c
index 98417beb9b..3c80724594 100644
--- a/util/gen_emmc_transfer_data.c
+++ b/util/gen_emmc_transfer_data.c
@@ -1,4 +1,4 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -16,8 +16,8 @@
 #include <compile_time_macros.h>
 
 /* eMMC transfer block size */
-#define BLOCK_SIZE		512
-#define BLOCK_RAW_DATA		"bootblock_raw_data"
+#define BLOCK_SIZE 512
+#define BLOCK_RAW_DATA "bootblock_raw_data"
 
 uint16_t crc16_arg(uint8_t data, uint16_t previous_crc)
 {
@@ -42,12 +42,11 @@ void header_format(FILE *fin, FILE *fout)
 	size_t cnt = 0;
 
 	fprintf(fout, "/* This file is auto-generated. Do not modify. */\n"
-		"#ifndef __CROS_EC_BOOTBLOCK_DATA_H\n"
-		"#define __CROS_EC_BOOTBLOCK_DATA_H\n"
-		"\n"
-		"#include <stdint.h>\n"
-		"\n"
-		);
+		      "#ifndef __CROS_EC_BOOTBLOCK_DATA_H\n"
+		      "#define __CROS_EC_BOOTBLOCK_DATA_H\n"
+		      "\n"
+		      "#include <stdint.h>\n"
+		      "\n");
 
 	fprintf(fout,
 		"static const uint8_t %s[] __attribute__((aligned(4))) =\n"
@@ -64,18 +63,19 @@ void header_format(FILE *fin, FILE *fout)
 		if (cnt == 0)
 			break;
 		else if (cnt < BLOCK_SIZE)
-			memset(&data[cnt], 0xff, BLOCK_SIZE-cnt);
+			memset(&data[cnt], 0xff, BLOCK_SIZE - cnt);
 
 		fprintf(fout, "\t/* Block %d (%ld) */\n", blk, cnt);
 		fprintf(fout, "\t0xff, 0xfe, /* idle, start bit. */");
 		for (j = 0; j < sizeof(data); j++) {
-			fprintf(fout, "%s0x%02x,",
-				(j % 8) == 0 ? "\n\t" : " ", data[j]);
+			fprintf(fout, "%s0x%02x,", (j % 8) == 0 ? "\n\t" : " ",
+				data[j]);
 			crc16 = crc16_arg(data[j], crc16);
 		}
 		fprintf(fout, "\n");
 
-		fprintf(fout, "\t0x%02x, 0x%02x, 0xff,"
+		fprintf(fout,
+			"\t0x%02x, 0x%02x, 0xff,"
 			" /* CRC, end bit, idle */\n",
 			crc16 >> 8, crc16 & 0xff);
 	}
@@ -96,16 +96,14 @@ int main(int argc, char **argv)
 	FILE *fout = NULL;
 
 	const char short_opts[] = "i:ho:";
-	const struct option long_opts[] = {
-		{ "input", 1, NULL, 'i' },
-		{ "help", 0, NULL, 'h' },
-		{ "out", 1, NULL, 'o' },
-		{ NULL }
-	};
+	const struct option long_opts[] = { { "input", 1, NULL, 'i' },
+					    { "help", 0, NULL, 'h' },
+					    { "out", 1, NULL, 'o' },
+					    { NULL } };
 	const char usage[] = "USAGE: %s [-i <input>] -o <output>\n";
 
-	while ((nopt = getopt_long(argc, argv, short_opts, long_opts,
-								NULL)) != -1) {
+	while ((nopt = getopt_long(argc, argv, short_opts, long_opts, NULL)) !=
+	       -1) {
 		switch (nopt) {
 		case 'i': /* -i or --input*/
 			input_name = optarg;
diff --git a/util/gen_ipi_table.c b/util/gen_ipi_table.c
index 07a3a39be0..6c1407973c 100644
--- a/util/gen_ipi_table.c
+++ b/util/gen_ipi_table.c
@@ -1,4 +1,4 @@
-/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+/* Copyright 2019 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -12,7 +12,7 @@
 
 #include "board.h"
 
-#define FPRINTF(format, args...) fprintf(fout, format, ## args)
+#define FPRINTF(format, args...) fprintf(fout, format, ##args)
 
 int main(int argc, char **argv)
 {
diff --git a/util/gen_touchpad_hash.c b/util/gen_touchpad_hash.c
index e03c4638f3..98370038b7 100644
--- a/util/gen_touchpad_hash.c
+++ b/util/gen_touchpad_hash.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -35,7 +35,7 @@ static int hash_fw_blank(FILE *hashes)
 		CONFIG_TOUCHPAD_VIRTUAL_SIZE / CONFIG_UPDATE_PDU_SIZE,
 		SHA256_DIGEST_LENGTH);
 	for (len = 0; len < CONFIG_TOUCHPAD_VIRTUAL_SIZE;
-				len += CONFIG_UPDATE_PDU_SIZE) {
+	     len += CONFIG_UPDATE_PDU_SIZE) {
 		print_hex(hashes, digest, sizeof(digest), 0);
 	}
 	fputs("};\n", hashes);
@@ -93,7 +93,7 @@ static int hash_fw(FILE *tp_fw, FILE *hashes)
 
 	if (len != CONFIG_TOUCHPAD_VIRTUAL_SIZE) {
 		warnx("Incorrect TP FW size (%d vs %d)", len,
-			CONFIG_TOUCHPAD_VIRTUAL_SIZE);
+		      CONFIG_TOUCHPAD_VIRTUAL_SIZE);
 		return 1;
 	}
 
@@ -109,16 +109,14 @@ int main(int argc, char **argv)
 	FILE *tp_fw = NULL;
 	FILE *hashes;
 	const char short_opt[] = "f:ho:";
-	const struct option long_opts[] = {
-		{ "firmware", 1, NULL, 'f' },
-		{ "help", 0, NULL, 'h' },
-		{ "out", 1, NULL, 'o' },
-		{ NULL }
-	};
+	const struct option long_opts[] = { { "firmware", 1, NULL, 'f' },
+					    { "help", 0, NULL, 'h' },
+					    { "out", 1, NULL, 'o' },
+					    { NULL } };
 	const char usage[] = "USAGE: %s -f <touchpad FW> -o <output file>\n";
 
-	while ((nopt = getopt_long(argc, argv, short_opt,
-						long_opts, NULL)) != -1) {
+	while ((nopt = getopt_long(argc, argv, short_opt, long_opts, NULL)) !=
+	       -1) {
 		switch (nopt) {
 		case 'f': /* -f or --firmware */
 			tp_fw_name = optarg;
diff --git a/util/genvif.c b/util/genvif.c
index 2b1ba8c494..543577cb11 100644
--- a/util/genvif.c
+++ b/util/genvif.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,14 +25,14 @@
 
 #include "genvif.h"
 
-#define VIF_APP_VENDOR_VALUE	"Google"
-#define VIF_APP_NAME_VALUE	"EC GENVIF"
-#define VIF_APP_VERSION_VALUE	"3.2.3.0"
-#define VENDOR_NAME_VALUE	"Google"
+#define VIF_APP_VENDOR_VALUE "Google"
+#define VIF_APP_NAME_VALUE "EC GENVIF"
+#define VIF_APP_VERSION_VALUE "3.2.3.0"
+#define VENDOR_NAME_VALUE "Google"
 
-#define DEFAULT_MISSING_TID	0xFFFF
-#define DEFAULT_MISSING_PID	0xFFFF
-#define DEFAULT_MISSING_BCD_DEV	0x0000
+#define DEFAULT_MISSING_TID 0xFFFF
+#define DEFAULT_MISSING_PID 0xFFFF
+#define DEFAULT_MISSING_BCD_DEV 0x0000
 
 /*
  * XML namespace for VIF as of VifEditorRelease 3.2.3.0
@@ -47,11 +47,7 @@ struct vif_t vif;
 /*
  * local type to make decisions on the output for Source, Sink and DRP
  */
-enum dtype {
-	SRC = 0,
-	SNK,
-	DRP
-};
+enum dtype { SRC = 0, SNK, DRP };
 
 enum ptype {
 	PORT_CONSUMER_ONLY = 0,
@@ -309,14 +305,10 @@ const char *vif_component_name[] = {
 BUILD_ASSERT(ARRAY_SIZE(vif_component_name) == Component_Indexes);
 
 const char *vif_component_snk_pdo_name[] = {
-	NAME_INIT(Snk_PDO_Supply_Type),
-	NAME_INIT(Snk_PDO_APDO_Type),
-	NAME_INIT(Snk_PDO_Voltage),
-	NAME_INIT(Snk_PDO_PDP_Rating),
-	NAME_INIT(Snk_PDO_Op_Power),
-	NAME_INIT(Snk_PDO_Min_Voltage),
-	NAME_INIT(Snk_PDO_Max_Voltage),
-	NAME_INIT(Snk_PDO_Op_Current),
+	NAME_INIT(Snk_PDO_Supply_Type), NAME_INIT(Snk_PDO_APDO_Type),
+	NAME_INIT(Snk_PDO_Voltage),	NAME_INIT(Snk_PDO_PDP_Rating),
+	NAME_INIT(Snk_PDO_Op_Power),	NAME_INIT(Snk_PDO_Min_Voltage),
+	NAME_INIT(Snk_PDO_Max_Voltage), NAME_INIT(Snk_PDO_Op_Current),
 };
 BUILD_ASSERT(ARRAY_SIZE(vif_component_snk_pdo_name) == Snk_PDO_Indexes);
 
@@ -343,7 +335,7 @@ const char *vif_component_sop_svid_mode_name[] = {
 	NAME_INIT(SVID_Mode_Recog_Value_SOP),
 };
 BUILD_ASSERT(ARRAY_SIZE(vif_component_sop_svid_mode_name) ==
-						SopSVID_Mode_Indexes);
+	     SopSVID_Mode_Indexes);
 
 const char *vif_component_sop_svid_name[] = {
 	NAME_INIT(SVID_SOP),
@@ -393,7 +385,7 @@ const char *vif_product_pcie_endpoint_name[] = {
 	NAME_INIT(USB4_PCIe_Endpoint_Class_Code),
 };
 BUILD_ASSERT(ARRAY_SIZE(vif_product_pcie_endpoint_name) ==
-						PCIe_Endpoint_Indexes);
+	     PCIe_Endpoint_Indexes);
 
 const char *vif_product_usb4_router_name[] = {
 	NAME_INIT(USB4_Router_ID),
@@ -414,7 +406,6 @@ const char *vif_product_usb4_router_name[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(vif_product_usb4_router_name) == USB4_Router_Indexes);
 
-
 static bool streq(const char *str1, const char *str2)
 {
 	if (str1 == NULL && str2 == NULL)
@@ -479,8 +470,8 @@ static bool get_vif_field_number(struct vif_field_t *vif_field, int *value)
 
 	return rv;
 }
-__maybe_unused
-static int get_vif_number(struct vif_field_t *vif_field, int default_value)
+__maybe_unused static int get_vif_number(struct vif_field_t *vif_field,
+					 int default_value)
 {
 	int ret_value;
 
@@ -528,8 +519,8 @@ static bool get_vif_bool(struct vif_field_t *vif_field, bool default_value)
 }
 
 /** String **/
-__maybe_unused
-static bool get_vif_field_tag_str(struct vif_field_t *vif_field, char **value)
+__maybe_unused static bool get_vif_field_tag_str(struct vif_field_t *vif_field,
+						 char **value)
 {
 	if (vif_field->tag_value == NULL)
 		return false;
@@ -537,8 +528,8 @@ static bool get_vif_field_tag_str(struct vif_field_t *vif_field, char **value)
 	*value = vif_field->tag_value;
 	return true;
 }
-__maybe_unused
-static bool get_vif_field_str_str(struct vif_field_t *vif_field, char **value)
+__maybe_unused static bool get_vif_field_str_str(struct vif_field_t *vif_field,
+						 char **value)
 {
 	if (vif_field->str_value == NULL)
 		return false;
@@ -550,7 +541,6 @@ static bool get_vif_field_str_str(struct vif_field_t *vif_field, char **value)
  * VIF Structure Override Value Retrieve Functions
  *****************************************************************************/
 
-
 /*****************************************************************************
  * Generic Helper Functions
  */
@@ -561,9 +551,8 @@ static bool is_src(void)
 
 	/* Determine if we are DRP, SRC or SNK */
 	was_overridden = get_vif_field_tag_number(
-				&vif.Component[component_index]
-					.vif_field[Type_C_State_Machine],
-				&override_value);
+		&vif.Component[component_index].vif_field[Type_C_State_Machine],
+		&override_value);
 	if (was_overridden) {
 		switch (override_value) {
 		case SRC:
@@ -578,15 +567,14 @@ static bool is_src(void)
 	}
 	if (!was_overridden) {
 		was_overridden = get_vif_field_tag_number(
-					&vif.Component[component_index]
-						.vif_field[PD_Port_Type],
-					&override_value);
+			&vif.Component[component_index].vif_field[PD_Port_Type],
+			&override_value);
 		if (was_overridden) {
 			switch (override_value) {
-			case PORT_PROVIDER_ONLY:	/* SRC */
-			case PORT_DRP:			/* DRP */
+			case PORT_PROVIDER_ONLY: /* SRC */
+			case PORT_DRP: /* DRP */
 				return true;
-			case PORT_CONSUMER_ONLY:	/* SNK */
+			case PORT_CONSUMER_ONLY: /* SNK */
 				return false;
 			default:
 				was_overridden = false;
@@ -602,9 +590,8 @@ static bool is_snk(void)
 
 	/* Determine if we are DRP, SRC or SNK */
 	was_overridden = get_vif_field_tag_number(
-				&vif.Component[component_index]
-					.vif_field[Type_C_State_Machine],
-				&override_value);
+		&vif.Component[component_index].vif_field[Type_C_State_Machine],
+		&override_value);
 	if (was_overridden) {
 		switch (override_value) {
 		case SNK:
@@ -619,15 +606,14 @@ static bool is_snk(void)
 	}
 	if (!was_overridden) {
 		was_overridden = get_vif_field_tag_number(
-					&vif.Component[component_index]
-						.vif_field[PD_Port_Type],
-					&override_value);
+			&vif.Component[component_index].vif_field[PD_Port_Type],
+			&override_value);
 		if (was_overridden) {
 			switch (override_value) {
-			case PORT_CONSUMER_ONLY:	/* SNK */
-			case PORT_DRP:			/* DRP */
+			case PORT_CONSUMER_ONLY: /* SNK */
+			case PORT_DRP: /* DRP */
 				return true;
-			case PORT_PROVIDER_ONLY:	/* SRC */
+			case PORT_PROVIDER_ONLY: /* SRC */
 				return false;
 			default:
 				was_overridden = false;
@@ -643,9 +629,8 @@ static bool is_drp(void)
 
 	/* Determine if we are DRP, SRC or SNK */
 	was_overridden = get_vif_field_tag_number(
-				&vif.Component[component_index]
-					.vif_field[Type_C_State_Machine],
-				&override_value);
+		&vif.Component[component_index].vif_field[Type_C_State_Machine],
+		&override_value);
 	if (was_overridden) {
 		switch (override_value) {
 		case DRP:
@@ -660,16 +645,15 @@ static bool is_drp(void)
 	}
 	if (!was_overridden) {
 		was_overridden = get_vif_field_tag_number(
-					&vif.Component[component_index]
-						.vif_field[PD_Port_Type],
-					&override_value);
+			&vif.Component[component_index].vif_field[PD_Port_Type],
+			&override_value);
 		if (was_overridden) {
 			switch (override_value) {
-			case PORT_DRP:			/* DRP */
+			case PORT_DRP: /* DRP */
 				return true;
-			case PORT_CONSUMER_ONLY:	/* SNK */
+			case PORT_CONSUMER_ONLY: /* SNK */
 				return false;
-			case PORT_PROVIDER_ONLY:	/* SRC */
+			case PORT_PROVIDER_ONLY: /* SRC */
 			default:
 				was_overridden = false;
 			}
@@ -683,80 +667,79 @@ static bool is_drp(void)
 static bool can_act_as_device(void)
 {
 	return get_vif_bool(&vif.Component[component_index]
-				.vif_field[Type_C_Can_Act_As_Device],
+				     .vif_field[Type_C_Can_Act_As_Device],
 #if defined(USB_DEV_CLASS) && defined(USB_CLASS_BILLBOARD)
 			    USB_DEV_CLASS == USB_CLASS_BILLBOARD
 #else
 			    false
 #endif
-			);
+	);
 }
 
 static bool can_act_as_host(void)
 {
 	return get_vif_bool(&vif.Component[component_index]
-				.vif_field[Type_C_Can_Act_As_Host],
+				     .vif_field[Type_C_Can_Act_As_Host],
 			    (!(IS_ENABLED(CONFIG_USB_CTVPD) ||
 			       IS_ENABLED(CONFIG_USB_VPD))));
 }
 
 static bool is_usb4_supported(void)
 {
-	return get_vif_bool(&vif.Component[component_index]
-				.vif_field[USB4_Supported],
-			    IS_ENABLED(CONFIG_USB_PD_USB4));
+	return get_vif_bool(
+		&vif.Component[component_index].vif_field[USB4_Supported],
+		IS_ENABLED(CONFIG_USB_PD_USB4));
 }
 
 static bool is_usb4_tbt3_compatible(void)
 {
-	return get_vif_bool(&vif.Component[component_index]
-				.vif_field[USB4_TBT3_Compatibility_Supported],
-			    IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE));
+	return get_vif_bool(
+		&vif.Component[component_index]
+			 .vif_field[USB4_TBT3_Compatibility_Supported],
+		IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE));
 }
 
 static bool is_usb4_pcie_tunneling_supported(void)
 {
 	return get_vif_bool(&vif.Component[component_index]
-				.vif_field[USB4_PCIe_Tunneling_Supported],
+				     .vif_field[USB4_PCIe_Tunneling_Supported],
 			    IS_ENABLED(CONFIG_USB_PD_PCIE_TUNNELING));
 }
 
 static bool is_usb_pd_supported(void)
 {
-	return get_vif_bool(&vif.Component[component_index]
-				.vif_field[USB_PD_Support],
-			    (is_usb4_supported() ||
-			     IS_ENABLED(CONFIG_USB_PRL_SM) ||
-			     IS_ENABLED(CONFIG_USB_POWER_DELIVERY)));
+	return get_vif_bool(
+		&vif.Component[component_index].vif_field[USB_PD_Support],
+		(is_usb4_supported() || IS_ENABLED(CONFIG_USB_PRL_SM) ||
+		 IS_ENABLED(CONFIG_USB_POWER_DELIVERY)));
 }
 
 static bool is_usb_comms_capable(void)
 {
-	return get_vif_bool(&vif.Component[component_index]
-				.vif_field[USB_Comms_Capable],
-			    is_usb4_supported() ||
-			    (!(IS_ENABLED(CONFIG_USB_VPD) ||
-			       IS_ENABLED(CONFIG_USB_CTVPD))));
+	return get_vif_bool(
+		&vif.Component[component_index].vif_field[USB_Comms_Capable],
+		is_usb4_supported() || (!(IS_ENABLED(CONFIG_USB_VPD) ||
+					  IS_ENABLED(CONFIG_USB_CTVPD))));
 }
 
 static bool is_alt_mode_controller(void)
 {
 	return get_vif_bool(&vif.Component[component_index]
-				.vif_field[Type_C_Is_Alt_Mode_Controller],
+				     .vif_field[Type_C_Is_Alt_Mode_Controller],
 			    IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP));
 }
 
 static bool is_alt_mode_adapter(void)
 {
 	return get_vif_bool(&vif.Component[component_index]
-			    .vif_field[Type_C_Is_Alt_Mode_Adapter],
+				     .vif_field[Type_C_Is_Alt_Mode_Adapter],
 			    IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP));
 }
 
 static bool does_respond_to_discov_sop_ufp(void)
 {
 	return get_vif_bool(&vif.Component[component_index]
-				.vif_field[Responds_To_Discov_SOP_UFP],
+				     .vif_field[Responds_To_Discov_SOP_UFP],
 			    (is_usb4_supported() ||
 			     IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE)));
 }
@@ -764,7 +747,7 @@ static bool does_respond_to_discov_sop_ufp(void)
 static bool does_respond_to_discov_sop_dfp(void)
 {
 	return get_vif_bool(&vif.Component[component_index]
-				.vif_field[Responds_To_Discov_SOP_DFP],
+				     .vif_field[Responds_To_Discov_SOP_DFP],
 			    (is_usb4_supported() ||
 			     IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE)));
 }
@@ -772,23 +755,21 @@ static bool does_respond_to_discov_sop_dfp(void)
 static bool does_support_device_usb_data(void)
 {
 	return get_vif_bool(&vif.Component[component_index]
-				.vif_field[Device_Supports_USB_Data],
-			    (is_usb4_supported() ||
-			     can_act_as_device()));
+				     .vif_field[Device_Supports_USB_Data],
+			    (is_usb4_supported() || can_act_as_device()));
 }
 
 static bool does_support_host_usb_data(void)
 {
 	int type_c_state_machine;
 
-	if (!get_vif_field_tag_number(
-			&vif.Component[component_index]
-				.vif_field[Type_C_State_Machine],
-			&type_c_state_machine))
+	if (!get_vif_field_tag_number(&vif.Component[component_index]
+					       .vif_field[Type_C_State_Machine],
+				      &type_c_state_machine))
 		return false;
 
 	return get_vif_bool(&vif.Component[component_index]
-				.vif_field[Host_Supports_USB_Data],
+				     .vif_field[Host_Supports_USB_Data],
 			    can_act_as_host());
 }
 
@@ -831,7 +812,6 @@ static bool vif_fields_present(const struct vif_field_t *vif_fields, int count)
  * Generic Helper Functions
  *****************************************************************************/
 
-
 /*****************************************************************************
  * VIF XML Output Functions
  */
@@ -874,9 +854,8 @@ static void vif_out_comment(FILE *vif_file, int level, const char *fmt, ...)
 	fprintf(vif_file, "-->\r\n");
 }
 
-static const char vif_separator[] =
-	";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;"
-	";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;";
+static const char vif_separator[] = ";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;"
+				    ";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;";
 
 static void vif_out_field(FILE *vif_file, int level,
 			  const struct vif_field_t *vif_field)
@@ -901,8 +880,7 @@ static void vif_out_field(FILE *vif_file, int level,
 			fprintf(vif_file, " value=\"%s\"",
 				vif_field->tag_value);
 		if (vif_field->str_value)
-			fprintf(vif_file, ">%s</%s>\r\n",
-				vif_field->str_value,
+			fprintf(vif_file, ">%s</%s>\r\n", vif_field->str_value,
 				vif_field->name);
 		else
 			fprintf(vif_file, " />\r\n");
@@ -910,8 +888,8 @@ static void vif_out_field(FILE *vif_file, int level,
 }
 
 static void vif_out_fields_range(FILE *vif_file, int level,
-			   const struct vif_field_t *vif_fields,
-			   int start, int count)
+				 const struct vif_field_t *vif_fields,
+				 int start, int count)
 {
 	int index;
 
@@ -925,10 +903,8 @@ static void vif_out_fields(FILE *vif_file, int level,
 	vif_out_fields_range(vif_file, level, vif_fields, 0, count);
 }
 
-
-
-static void vif_output_vif_component_cable_svid_mode_list(FILE *vif_file,
-			const struct vif_cableSVIDList_t *svid_list, int level)
+static void vif_output_vif_component_cable_svid_mode_list(
+	FILE *vif_file, const struct vif_cableSVIDList_t *svid_list, int level)
 {
 	int index;
 
@@ -939,22 +915,22 @@ static void vif_output_vif_component_cable_svid_mode_list(FILE *vif_file,
 	vif_out_start(vif_file, level++, "CableSVIDModeList");
 	for (index = 0; index < MAX_NUM_CABLE_SVID_MODES; ++index) {
 		const struct vif_cableSVIDModeList_t *mode_list =
-				&svid_list->CableSVIDModeList[index];
+			&svid_list->CableSVIDModeList[index];
 
 		if (!vif_fields_present(mode_list->vif_field,
 					CableSVID_Mode_Indexes))
 			break;
 
 		vif_out_start(vif_file, level++, "SOPSVIDMode");
-		vif_out_fields(vif_file, level,
-			       mode_list->vif_field, CableSVID_Mode_Indexes);
+		vif_out_fields(vif_file, level, mode_list->vif_field,
+			       CableSVID_Mode_Indexes);
 		vif_out_end(vif_file, --level, "SOPSVIDMode");
 	}
 	vif_out_end(vif_file, --level, "CableSVIDModeList");
 }
 
-static void vif_output_vif_component_cable_svid_list(FILE *vif_file,
-			const struct vif_Component_t *component, int level)
+static void vif_output_vif_component_cable_svid_list(
+	FILE *vif_file, const struct vif_Component_t *component, int level)
 {
 	int index;
 
@@ -965,24 +941,24 @@ static void vif_output_vif_component_cable_svid_list(FILE *vif_file,
 	vif_out_start(vif_file, level++, "CableSVIDList");
 	for (index = 0; index < MAX_NUM_CABLE_SVIDS; ++index) {
 		const struct vif_cableSVIDList_t *svid_list =
-				&component->CableSVIDList[index];
+			&component->CableSVIDList[index];
 
 		if (!vif_fields_present(svid_list->vif_field,
 					CableSVID_Indexes))
 			break;
 
 		vif_out_start(vif_file, level++, "CableSVID");
-		vif_out_fields(vif_file, level,
-			       svid_list->vif_field, CableSVID_Indexes);
+		vif_out_fields(vif_file, level, svid_list->vif_field,
+			       CableSVID_Indexes);
 		vif_output_vif_component_cable_svid_mode_list(vif_file,
-						svid_list, level);
+							      svid_list, level);
 		vif_out_end(vif_file, --level, "CableSVID");
 	}
 	vif_out_end(vif_file, --level, "CableSVIDList");
 }
 
-static void vif_output_vif_component_sop_svid_mode_list(FILE *vif_file,
-			const struct vif_sopSVIDList_t *svid_list, int level)
+static void vif_output_vif_component_sop_svid_mode_list(
+	FILE *vif_file, const struct vif_sopSVIDList_t *svid_list, int level)
 {
 	int index;
 
@@ -993,22 +969,22 @@ static void vif_output_vif_component_sop_svid_mode_list(FILE *vif_file,
 	vif_out_start(vif_file, level++, "SOPSVIDModeList");
 	for (index = 0; index < MAX_NUM_SOP_SVID_MODES; ++index) {
 		const struct vif_sopSVIDModeList_t *mode_list =
-				&svid_list->SOPSVIDModeList[index];
+			&svid_list->SOPSVIDModeList[index];
 
 		if (!vif_fields_present(mode_list->vif_field,
 					SopSVID_Mode_Indexes))
 			break;
 
 		vif_out_start(vif_file, level++, "SOPSVIDMode");
-		vif_out_fields(vif_file, level,
-			       mode_list->vif_field, SopSVID_Mode_Indexes);
+		vif_out_fields(vif_file, level, mode_list->vif_field,
+			       SopSVID_Mode_Indexes);
 		vif_out_end(vif_file, --level, "SOPSVIDMode");
 	}
 	vif_out_end(vif_file, --level, "SOPSVIDModeList");
 }
 
-static void vif_output_vif_component_sop_svid_list(FILE *vif_file,
-			const struct vif_Component_t *component, int level)
+static void vif_output_vif_component_sop_svid_list(
+	FILE *vif_file, const struct vif_Component_t *component, int level)
 {
 	int index;
 
@@ -1019,24 +995,23 @@ static void vif_output_vif_component_sop_svid_list(FILE *vif_file,
 	vif_out_start(vif_file, level++, "SOPSVIDList");
 	for (index = 0; index < MAX_NUM_SOP_SVIDS; ++index) {
 		const struct vif_sopSVIDList_t *svid_list =
-				&component->SOPSVIDList[index];
+			&component->SOPSVIDList[index];
 
-		if (!vif_fields_present(svid_list->vif_field,
-					SopSVID_Indexes))
+		if (!vif_fields_present(svid_list->vif_field, SopSVID_Indexes))
 			break;
 
 		vif_out_start(vif_file, level++, "SOPSVID");
-		vif_out_fields(vif_file, level,
-			       svid_list->vif_field, SopSVID_Indexes);
-		vif_output_vif_component_sop_svid_mode_list(vif_file,
-						svid_list, level);
+		vif_out_fields(vif_file, level, svid_list->vif_field,
+			       SopSVID_Indexes);
+		vif_output_vif_component_sop_svid_mode_list(vif_file, svid_list,
+							    level);
 		vif_out_end(vif_file, --level, "SOPSVID");
 	}
 	vif_out_end(vif_file, --level, "SOPSVIDList");
 }
 
-static void vif_output_vif_component_snk_pdo_list(FILE *vif_file,
-			const struct vif_Component_t *component, int level)
+static void vif_output_vif_component_snk_pdo_list(
+	FILE *vif_file, const struct vif_Component_t *component, int level)
 {
 	int index;
 
@@ -1048,23 +1023,22 @@ static void vif_output_vif_component_snk_pdo_list(FILE *vif_file,
 	vif_out_start(vif_file, level++, "SnkPdoList");
 	for (index = 0; index < MAX_NUM_SNK_PDOS; ++index) {
 		const struct vif_snkPdoList_t *pdo_list =
-				&component->SnkPdoList[index];
+			&component->SnkPdoList[index];
 
-		if (!vif_fields_present(pdo_list->vif_field,
-					Snk_PDO_Indexes))
+		if (!vif_fields_present(pdo_list->vif_field, Snk_PDO_Indexes))
 			break;
 
 		vif_out_start(vif_file, level++, "SnkPDO");
 		vif_out_comment(vif_file, level, "Sink PDO %d", index + 1);
-		vif_out_fields(vif_file, level,
-			       pdo_list->vif_field, Snk_PDO_Indexes);
+		vif_out_fields(vif_file, level, pdo_list->vif_field,
+			       Snk_PDO_Indexes);
 		vif_out_end(vif_file, --level, "SnkPDO");
 	}
 	vif_out_end(vif_file, --level, "SnkPdoList");
 }
 
-static void vif_output_vif_component_src_pdo_list(FILE *vif_file,
-			const struct vif_Component_t *component, int level)
+static void vif_output_vif_component_src_pdo_list(
+	FILE *vif_file, const struct vif_Component_t *component, int level)
 {
 	int index;
 
@@ -1076,23 +1050,22 @@ static void vif_output_vif_component_src_pdo_list(FILE *vif_file,
 	vif_out_start(vif_file, level++, "SrcPdoList");
 	for (index = 0; index < MAX_NUM_SRC_PDOS; ++index) {
 		const struct vif_srcPdoList_t *pdo_list =
-				&component->SrcPdoList[index];
+			&component->SrcPdoList[index];
 
-		if (!vif_fields_present(pdo_list->vif_field,
-					Src_PDO_Indexes))
+		if (!vif_fields_present(pdo_list->vif_field, Src_PDO_Indexes))
 			break;
 
 		vif_out_start(vif_file, level++, "SrcPDO");
 		vif_out_comment(vif_file, level, "Source PDO %d", index + 1);
-		vif_out_fields(vif_file, level,
-			       pdo_list->vif_field, Src_PDO_Indexes);
+		vif_out_fields(vif_file, level, pdo_list->vif_field,
+			       Src_PDO_Indexes);
 		vif_out_end(vif_file, --level, "SrcPDO");
 	}
 	vif_out_end(vif_file, --level, "SrcPdoList");
 }
 
-static void vif_output_vif_component(FILE *vif_file,
-			const struct vif_t *vif, int level)
+static void vif_output_vif_component(FILE *vif_file, const struct vif_t *vif,
+				     int level)
 {
 	int index;
 
@@ -1106,26 +1079,23 @@ static void vif_output_vif_component(FILE *vif_file,
 
 		vif_out_start(vif_file, level++, "Component");
 		vif_out_comment(vif_file, level, "Component %d", index);
-		vif_out_fields(vif_file, level,
-			       component->vif_field, Component_Indexes);
-		vif_output_vif_component_snk_pdo_list(vif_file,
-						component,
-						level);
-		vif_output_vif_component_src_pdo_list(vif_file,
-						component,
-						level);
-		vif_output_vif_component_sop_svid_list(vif_file,
-						component,
-						level);
-		vif_output_vif_component_cable_svid_list(vif_file,
-						component,
-						level);
+		vif_out_fields(vif_file, level, component->vif_field,
+			       Component_Indexes);
+		vif_output_vif_component_snk_pdo_list(vif_file, component,
+						      level);
+		vif_output_vif_component_src_pdo_list(vif_file, component,
+						      level);
+		vif_output_vif_component_sop_svid_list(vif_file, component,
+						       level);
+		vif_output_vif_component_cable_svid_list(vif_file, component,
+							 level);
 		vif_out_end(vif_file, --level, "Component");
 	}
 }
 
-static void vif_output_vif_product_usb4router_endpoint(FILE *vif_file,
-		const struct vif_Usb4RouterListType_t *router, int level)
+static void vif_output_vif_product_usb4router_endpoint(
+	FILE *vif_file, const struct vif_Usb4RouterListType_t *router,
+	int level)
 {
 	int index;
 
@@ -1136,22 +1106,23 @@ static void vif_output_vif_product_usb4router_endpoint(FILE *vif_file,
 	vif_out_start(vif_file, level++, "PCIeEndpointList");
 	for (index = 0; index < MAX_NUM_PCIE_ENDPOINTS; ++index) {
 		const struct vif_PCIeEndpointListType_t *endpont =
-				&router->PCIeEndpointList[index];
+			&router->PCIeEndpointList[index];
 
 		if (!vif_fields_present(endpont->vif_field,
 					PCIe_Endpoint_Indexes))
 			break;
 
 		vif_out_start(vif_file, level++, "PCIeEndpoint");
-		vif_out_fields(vif_file, level,
-			       endpont->vif_field, PCIe_Endpoint_Indexes);
+		vif_out_fields(vif_file, level, endpont->vif_field,
+			       PCIe_Endpoint_Indexes);
 		vif_out_end(vif_file, --level, "PCIeEndpoint");
 	}
 	vif_out_end(vif_file, --level, "PCIeEndpointList");
 }
 
 static void vif_output_vif_product_usb4router(FILE *vif_file,
-			const struct vif_t *vif, int level)
+					      const struct vif_t *vif,
+					      int level)
 {
 	int index;
 
@@ -1163,34 +1134,32 @@ static void vif_output_vif_product_usb4router(FILE *vif_file,
 	vif_out_start(vif_file, level++, "USB4RouterList");
 	for (index = 0; index < MAX_NUM_USB4_ROUTERS; ++index) {
 		const struct vif_Usb4RouterListType_t *router =
-				&vif->Product.USB4RouterList[index];
+			&vif->Product.USB4RouterList[index];
 
-		if (!vif_fields_present(router->vif_field,
-					USB4_Router_Indexes))
+		if (!vif_fields_present(router->vif_field, USB4_Router_Indexes))
 			break;
 
 		vif_out_start(vif_file, level++, "Usb4Router");
 		vif_out_comment(vif_file, level, "USB4 Router %d", index);
-		vif_out_fields(vif_file, level,
-			       router->vif_field, USB4_Router_Indexes);
-		vif_output_vif_product_usb4router_endpoint(vif_file,
-							   router,
+		vif_out_fields(vif_file, level, router->vif_field,
+			       USB4_Router_Indexes);
+		vif_output_vif_product_usb4router_endpoint(vif_file, router,
 							   level);
 		vif_out_end(vif_file, --level, "Usb4Router");
 	}
 	vif_out_end(vif_file, --level, "USB4RouterList");
 }
 
-static void vif_output_vif_product(FILE *vif_file,
-			const struct vif_t *vif, int level)
+static void vif_output_vif_product(FILE *vif_file, const struct vif_t *vif,
+				   int level)
 {
 	if (!vif_fields_present(vif->Product.vif_field, Product_Indexes))
 		return;
 
 	vif_out_start(vif_file, level++, "Product");
 	vif_out_comment(vif_file, level, "Product Level Content:");
-	vif_out_fields(vif_file, level,
-		       vif->Product.vif_field, Product_Indexes);
+	vif_out_fields(vif_file, level, vif->Product.vif_field,
+		       Product_Indexes);
 	vif_output_vif_product_usb4router(vif_file, vif, level);
 	vif_out_end(vif_file, --level, "Product");
 }
@@ -1203,8 +1172,8 @@ static void vif_output_vif_xml(FILE *vif_file, struct vif_t *vif, int level)
 	vif_out_fields(vif_file, level, vif->vif_app_field, VIF_App_Indexes);
 	vif_out_end(vif_file, --level, "VIF_App");
 
-	vif_out_fields_range(vif_file, level,
-		       vif->vif_field, Vendor_Name, VIF_Indexes);
+	vif_out_fields_range(vif_file, level, vif->vif_field, Vendor_Name,
+			     VIF_Indexes);
 }
 
 static int vif_output_xml(const char *name, struct vif_t *vif)
@@ -1220,12 +1189,13 @@ static int vif_output_xml(const char *name, struct vif_t *vif)
 	}
 
 	vif_out_str(vif_file, level,
-		"<?xml version=\"1.0\" encoding=\"utf-8\"?>");
-	vif_out_start(vif_file, level++,
+		    "<?xml version=\"1.0\" encoding=\"utf-8\"?>");
+	vif_out_start(
+		vif_file, level++,
 		"VIF "
-		    "xmlns:opt=\"http://usb.org/VendorInfoFileOptionalContent.xsd\" "
-		    "xmlns:xsi=\"http://www.w3.org/2001/XMLSchema-instance\" "
-		    "xmlns:vif=\"http://usb.org/VendorInfoFile.xsd\"");
+		"xmlns:opt=\"http://usb.org/VendorInfoFileOptionalContent.xsd\" "
+		"xmlns:xsi=\"http://www.w3.org/2001/XMLSchema-instance\" "
+		"xmlns:vif=\"http://usb.org/VendorInfoFile.xsd\"");
 
 	vif_output_vif_xml(vif_file, vif, level);
 	vif_output_vif_product(vif_file, vif, level);
@@ -1240,7 +1210,6 @@ static int vif_output_xml(const char *name, struct vif_t *vif)
  * VIF XML Output Functions
  *****************************************************************************/
 
-
 /*****************************************************************************
  * VIF Structure Override from XML file functions
  */
@@ -1298,11 +1267,9 @@ static void ov_close(void)
 	override_file = NULL;
 }
 
-
 static void set_override_vif_field(struct vif_field_t *vif_field,
-			const char *name,
-			const char *tag_value,
-			const char *str_value)
+				   const char *name, const char *tag_value,
+				   const char *str_value)
 {
 	char *ptr;
 
@@ -1317,12 +1284,12 @@ static void set_override_vif_field(struct vif_field_t *vif_field,
 
 	vif_field->name = name;
 	if (tag_value && tag_value[0]) {
-		ptr = malloc(strlen(tag_value)+1);
+		ptr = malloc(strlen(tag_value) + 1);
 		strcpy(ptr, tag_value);
 		vif_field->tag_value = ptr;
 	}
 	if (str_value && str_value[0]) {
-		ptr = malloc(strlen(str_value)+1);
+		ptr = malloc(strlen(str_value) + 1);
 		strcpy(ptr, str_value);
 		vif_field->str_value = ptr;
 	}
@@ -1346,10 +1313,9 @@ static void ignore_comment_tag(void)
 	int ch;
 
 	while ((ch = ov_getc()) != EOF) {
-		if (ch ==  '-') {
+		if (ch == '-') {
 			ovpre_getc(2);
-			if (ovpre_peek(0) == '-' &&
-			    ovpre_peek(1) == '>') {
+			if (ovpre_peek(0) == '-' && ovpre_peek(1) == '>') {
 				/* --> */
 				ovpre_drop(2);
 				break;
@@ -1388,9 +1354,7 @@ static void ignore_to_end_tag(void)
  *
  * <tag><nested value=x /></tag>     next call returns <nested>
  */
-static bool get_next_tag(char *name,
-			 char *tag_value,
-			 char *str_value)
+static bool get_next_tag(char *name, char *tag_value, char *str_value)
 {
 	int ch;
 	int name_index = 0;
@@ -1422,8 +1386,7 @@ static bool get_next_tag(char *name,
 			 * Ignore XML comment <!-- ... -->
 			 */
 			ovpre_getc(3);
-			if (ovpre_peek(0) == '!' &&
-			    ovpre_peek(1) == '-' &&
+			if (ovpre_peek(0) == '!' && ovpre_peek(1) == '-' &&
 			    ovpre_peek(2) == '-') {
 				ovpre_drop(3);
 				ignore_comment_tag();
@@ -1444,8 +1407,8 @@ static bool get_next_tag(char *name,
 
 			/* Looking for a tag name */
 			while ((ch = ov_getc()) != EOF) {
-				if (ch == '_' || ch == ':' ||
-				    isalpha(ch) || isdigit(ch)) {
+				if (ch == '_' || ch == ':' || isalpha(ch) ||
+				    isdigit(ch)) {
 					name[name_index++] = ch;
 				} else {
 					ov_pushback(ch);
@@ -1459,12 +1422,9 @@ static bool get_next_tag(char *name,
 
 			/* See if there is a tag_string value */
 			ovpre_getc(7);
-			if (ovpre_peek(0) == 'v' &&
-			    ovpre_peek(1) == 'a' &&
-			    ovpre_peek(2) == 'l' &&
-			    ovpre_peek(3) == 'u' &&
-			    ovpre_peek(4) == 'e' &&
-			    ovpre_peek(5) == '=' &&
+			if (ovpre_peek(0) == 'v' && ovpre_peek(1) == 'a' &&
+			    ovpre_peek(2) == 'l' && ovpre_peek(3) == 'u' &&
+			    ovpre_peek(4) == 'e' && ovpre_peek(5) == '=' &&
 			    ovpre_peek(6) == '"') {
 				ovpre_drop(7);
 				while ((ch = ov_getc()) != EOF) {
@@ -1480,8 +1440,7 @@ static bool get_next_tag(char *name,
 
 			/* /> ending the tag will conclude this tag */
 			ovpre_getc(2);
-			if (ovpre_peek(0) == '/' &&
-			    ovpre_peek(1) == '>') {
+			if (ovpre_peek(0) == '/' && ovpre_peek(1) == '>') {
 				ovpre_drop(2);
 				return true;
 			}
@@ -1510,7 +1469,7 @@ static bool get_next_tag(char *name,
 }
 
 static void override_vif_product_pcie_endpoint_field(
-		struct vif_PCIeEndpointListType_t *endpoint)
+	struct vif_PCIeEndpointListType_t *endpoint)
 {
 	char name[80];
 	char tag_value[80];
@@ -1528,17 +1487,17 @@ static void override_vif_product_pcie_endpoint_field(
 		if (i != PCIe_Endpoint_Indexes)
 			set_override_vif_field(
 				&endpoint->vif_field[i],
-				vif_product_pcie_endpoint_name[i],
-				tag_value,
+				vif_product_pcie_endpoint_name[i], tag_value,
 				str_value);
 		else
 			fprintf(stderr,
 				"VIF/Component/Usb4Router/PCIeEndpoint:"
-				" Unknown tag '%s'\n", name);
+				" Unknown tag '%s'\n",
+				name);
 	}
 }
 static void override_vif_product_pcie_endpoint_list_field(
-		struct vif_PCIeEndpointListType_t *endpoint_list)
+	struct vif_PCIeEndpointListType_t *endpoint_list)
 {
 	char name[80];
 	char tag_value[80];
@@ -1551,16 +1510,17 @@ static void override_vif_product_pcie_endpoint_list_field(
 
 		if (is_start_tag(name, "PCIeEndpoint"))
 			override_vif_product_pcie_endpoint_field(
-					&endpoint_list[endpoint_index++]);
+				&endpoint_list[endpoint_index++]);
 		else
 			fprintf(stderr,
 				"VIF/Product/Usb4Router/PCIeEndpointList:"
-				" Unknown tag '%s'\n", name);
+				" Unknown tag '%s'\n",
+				name);
 	}
 }
 
-static void override_vif_product_usb4router_fields(
-		struct vif_Usb4RouterListType_t *router)
+static void
+override_vif_product_usb4router_fields(struct vif_Usb4RouterListType_t *router)
 {
 	char name[80];
 	char tag_value[80];
@@ -1585,17 +1545,17 @@ static void override_vif_product_usb4router_fields(
 				set_override_vif_field(
 					&router->vif_field[i],
 					vif_product_usb4_router_name[i],
-					tag_value,
-					str_value);
+					tag_value, str_value);
 			else
 				fprintf(stderr,
 					"VIF/Component/Usb4Router:"
-					" Unknown tag '%s'\n", name);
+					" Unknown tag '%s'\n",
+					name);
 		}
 	}
 }
 static void override_vif_product_usb4routerlist_fields(
-		struct vif_Usb4RouterListType_t *router_list)
+	struct vif_Usb4RouterListType_t *router_list)
 {
 	char name[80];
 	char tag_value[80];
@@ -1612,7 +1572,8 @@ static void override_vif_product_usb4routerlist_fields(
 		else
 			fprintf(stderr,
 				"VIF/Product/USB4RouterList:"
-				" Unknown tag '%s'\n", name);
+				" Unknown tag '%s'\n",
+				name);
 	}
 }
 
@@ -1641,19 +1602,19 @@ static void override_vif_product_fields(struct vif_Product_t *vif_product)
 			if (i != Product_Indexes)
 				set_override_vif_field(
 					&vif_product->vif_field[i],
-					vif_product_name[i],
-					tag_value,
+					vif_product_name[i], tag_value,
 					str_value);
 			else
 				fprintf(stderr,
 					"VIF/Product:"
-					" Unknown tag '%s'\n", name);
+					" Unknown tag '%s'\n",
+					name);
 		}
 	}
 }
 
-static void override_vif_component_src_pdo_fields(
-		struct vif_srcPdoList_t *vif_src_pdo)
+static void
+override_vif_component_src_pdo_fields(struct vif_srcPdoList_t *vif_src_pdo)
 {
 	char name[80];
 	char tag_value[80];
@@ -1669,19 +1630,18 @@ static void override_vif_component_src_pdo_fields(
 			if (streq(name, vif_component_src_pdo_name[i]))
 				break;
 		if (i != Src_PDO_Indexes)
-			set_override_vif_field(
-				&vif_src_pdo->vif_field[i],
-				vif_component_src_pdo_name[i],
-				tag_value,
-				str_value);
+			set_override_vif_field(&vif_src_pdo->vif_field[i],
+					       vif_component_src_pdo_name[i],
+					       tag_value, str_value);
 		else
 			fprintf(stderr,
 				"VIF/Component/SrcPdo:"
-				" Unknown tag '%s'\n", name);
+				" Unknown tag '%s'\n",
+				name);
 	}
 }
 static void override_vif_component_src_pdo_list_fields(
-		struct vif_srcPdoList_t *vif_src_pdo_list)
+	struct vif_srcPdoList_t *vif_src_pdo_list)
 {
 	char name[80];
 	char tag_value[80];
@@ -1698,12 +1658,13 @@ static void override_vif_component_src_pdo_list_fields(
 		else
 			fprintf(stderr,
 				"VIF/Component/SrcPdoList:"
-				" Unknown tag '%s'\n", name);
+				" Unknown tag '%s'\n",
+				name);
 	}
 }
 
-static void override_vif_component_snk_pdo_fields(
-		struct vif_snkPdoList_t *vif_snk_pdo)
+static void
+override_vif_component_snk_pdo_fields(struct vif_snkPdoList_t *vif_snk_pdo)
 {
 	char name[80];
 	char tag_value[80];
@@ -1719,19 +1680,18 @@ static void override_vif_component_snk_pdo_fields(
 			if (streq(name, vif_component_snk_pdo_name[i]))
 				break;
 		if (i != Snk_PDO_Indexes)
-			set_override_vif_field(
-				&vif_snk_pdo->vif_field[i],
-				vif_component_snk_pdo_name[i],
-				tag_value,
-				str_value);
+			set_override_vif_field(&vif_snk_pdo->vif_field[i],
+					       vif_component_snk_pdo_name[i],
+					       tag_value, str_value);
 		else
 			fprintf(stderr,
 				"VIF/Component/SnkPdo:"
-				" Unknown tag '%s'\n", name);
+				" Unknown tag '%s'\n",
+				name);
 	}
 }
 static void override_vif_component_snk_pdo_list_fields(
-		struct vif_snkPdoList_t *vif_snk_pdo_list)
+	struct vif_snkPdoList_t *vif_snk_pdo_list)
 {
 	char name[80];
 	char tag_value[80];
@@ -1748,12 +1708,13 @@ static void override_vif_component_snk_pdo_list_fields(
 		else
 			fprintf(stderr,
 				"VIF/Component/SnkPdoList:"
-				" Unknown tag '%s'\n", name);
+				" Unknown tag '%s'\n",
+				name);
 	}
 }
 
 static void override_vif_component_sop_svid_mode_fields(
-		struct vif_sopSVIDModeList_t *svid_mode)
+	struct vif_sopSVIDModeList_t *svid_mode)
 {
 	char name[80];
 	char tag_value[80];
@@ -1771,17 +1732,17 @@ static void override_vif_component_sop_svid_mode_fields(
 		if (i != SopSVID_Indexes)
 			set_override_vif_field(
 				&svid_mode->vif_field[i],
-				vif_component_sop_svid_mode_name[i],
-				tag_value,
+				vif_component_sop_svid_mode_name[i], tag_value,
 				str_value);
 		else
 			fprintf(stderr,
 				"VIF/Component/SOPSVIDMode:"
-				" Unknown tag '%s'\n", name);
+				" Unknown tag '%s'\n",
+				name);
 	}
 }
 static void override_vif_component_sop_svid_mode_list_fields(
-		struct vif_sopSVIDModeList_t *svid_mode_list)
+	struct vif_sopSVIDModeList_t *svid_mode_list)
 {
 	char name[80];
 	char tag_value[80];
@@ -1798,12 +1759,13 @@ static void override_vif_component_sop_svid_mode_list_fields(
 		else
 			fprintf(stderr,
 				"VIF/Component/SOPSVIDModeList:"
-				" Unknown tag '%s'\n", name);
+				" Unknown tag '%s'\n",
+				name);
 	}
 }
 
-static void override_vif_component_sop_svid_fields(
-		struct vif_sopSVIDList_t *vif_sop_svid)
+static void
+override_vif_component_sop_svid_fields(struct vif_sopSVIDList_t *vif_sop_svid)
 {
 	char name[80];
 	char tag_value[80];
@@ -1820,24 +1782,23 @@ static void override_vif_component_sop_svid_fields(
 			int i;
 
 			for (i = 0; i < SopSVID_Indexes; i++)
-				if (streq(name,
-					  vif_component_sop_svid_name[i]))
+				if (streq(name, vif_component_sop_svid_name[i]))
 					break;
 			if (i != SopSVID_Indexes)
 				set_override_vif_field(
 					&vif_sop_svid->vif_field[i],
 					vif_component_sop_svid_name[i],
-					tag_value,
-					str_value);
+					tag_value, str_value);
 			else
 				fprintf(stderr,
 					"VIF/Component/SOPSVID:"
-					" Unknown tag '%s'\n", name);
+					" Unknown tag '%s'\n",
+					name);
 		}
 	}
 }
 static void override_vif_component_sop_svid_list_fields(
-		struct vif_sopSVIDList_t *vif_sop_svid_list)
+	struct vif_sopSVIDList_t *vif_sop_svid_list)
 {
 	char name[80];
 	char tag_value[80];
@@ -1854,12 +1815,13 @@ static void override_vif_component_sop_svid_list_fields(
 		else
 			fprintf(stderr,
 				"VIF/Component/SOPSVIDList:"
-				" Unknown tag '%s'\n", name);
+				" Unknown tag '%s'\n",
+				name);
 	}
 }
 
 static void override_vif_component_cable_svid_mode_fields(
-		struct vif_cableSVIDModeList_t *vif_cable_mode)
+	struct vif_cableSVIDModeList_t *vif_cable_mode)
 {
 	char name[80];
 	char tag_value[80];
@@ -1875,19 +1837,18 @@ static void override_vif_component_cable_svid_mode_fields(
 			if (streq(name, vif_cable_mode_name[i]))
 				break;
 		if (i != CableSVID_Mode_Indexes)
-			set_override_vif_field(
-				&vif_cable_mode->vif_field[i],
-				vif_cable_mode_name[i],
-				tag_value,
-				str_value);
+			set_override_vif_field(&vif_cable_mode->vif_field[i],
+					       vif_cable_mode_name[i],
+					       tag_value, str_value);
 		else
 			fprintf(stderr,
 				"VIF/Component/CableSVIDMode:"
-				" Unknown tag '%s'\n", name);
+				" Unknown tag '%s'\n",
+				name);
 	}
 }
 static void override_vif_component_cable_svid_mode_list_fields(
-		struct vif_cableSVIDModeList_t *vif_cable_mode_list)
+	struct vif_cableSVIDModeList_t *vif_cable_mode_list)
 {
 	char name[80];
 	char tag_value[80];
@@ -1904,12 +1865,13 @@ static void override_vif_component_cable_svid_mode_list_fields(
 		else
 			fprintf(stderr,
 				"VIF/Component/CableSVIDModeList:"
-				" Unknown tag '%s'\n", name);
+				" Unknown tag '%s'\n",
+				name);
 	}
 }
 
 static void override_vif_component_cable_svid_fields(
-		struct vif_cableSVIDList_t *vif_cable_svid)
+	struct vif_cableSVIDList_t *vif_cable_svid)
 {
 	char name[80];
 	char tag_value[80];
@@ -1922,8 +1884,8 @@ static void override_vif_component_cable_svid_fields(
 
 		if (is_start_tag(name, "CableSVIDModeList"))
 			override_vif_component_cable_svid_mode_list_fields(
-				&vif_cable_svid->CableSVIDModeList[
-							mode_index++]);
+				&vif_cable_svid
+					 ->CableSVIDModeList[mode_index++]);
 		else {
 			int i;
 
@@ -1933,18 +1895,18 @@ static void override_vif_component_cable_svid_fields(
 			if (i != CableSVID_Indexes)
 				set_override_vif_field(
 					&vif_cable_svid->vif_field[i],
-					vif_cable_svid_name[i],
-					tag_value,
+					vif_cable_svid_name[i], tag_value,
 					str_value);
 			else
 				fprintf(stderr,
 					"VIF/Component/CableSVID:"
-					" Unknown tag '%s'\n", name);
+					" Unknown tag '%s'\n",
+					name);
 		}
 	}
 }
 static void override_vif_component_cable_svid_list_fields(
-		struct vif_cableSVIDList_t *vif_cable_svid_list)
+	struct vif_cableSVIDList_t *vif_cable_svid_list)
 {
 	char name[80];
 	char tag_value[80];
@@ -1961,12 +1923,12 @@ static void override_vif_component_cable_svid_list_fields(
 		else
 			fprintf(stderr,
 				"VIF/Component/CableSVIDList:"
-				" Unknown tag '%s'\n", name);
+				" Unknown tag '%s'\n",
+				name);
 	}
 }
 
-static void override_vif_component_fields(
-		struct vif_Component_t *vif_component)
+static void override_vif_component_fields(struct vif_Component_t *vif_component)
 {
 	char name[80];
 	char tag_value[80];
@@ -1978,16 +1940,16 @@ static void override_vif_component_fields(
 
 		if (is_start_tag(name, "SrcPdoList"))
 			override_vif_component_src_pdo_list_fields(
-					vif_component->SrcPdoList);
+				vif_component->SrcPdoList);
 		else if (is_start_tag(name, "SnkPdoList"))
 			override_vif_component_snk_pdo_list_fields(
-					vif_component->SnkPdoList);
+				vif_component->SnkPdoList);
 		else if (is_start_tag(name, "SOPSVIDList"))
 			override_vif_component_sop_svid_list_fields(
-					vif_component->SOPSVIDList);
+				vif_component->SOPSVIDList);
 		else if (is_start_tag(name, "CableSVIDList"))
 			override_vif_component_cable_svid_list_fields(
-					vif_component->CableSVIDList);
+				vif_component->CableSVIDList);
 		else {
 			int i;
 
@@ -1996,14 +1958,14 @@ static void override_vif_component_fields(
 					break;
 			if (i != Component_Indexes)
 				set_override_vif_field(
-						&vif_component->vif_field[i],
-						vif_component_name[i],
-						tag_value,
-						str_value);
+					&vif_component->vif_field[i],
+					vif_component_name[i], tag_value,
+					str_value);
 			else
 				fprintf(stderr,
 					"VIF/Component:"
-					" Unknown tag '%s'\n", name);
+					" Unknown tag '%s'\n",
+					name);
 		}
 	}
 }
@@ -2026,7 +1988,8 @@ static void override_vif_app_fields(struct vif_t *vif)
 		if (i == VIF_App_Indexes)
 			fprintf(stderr,
 				"VIF/VIF_App:"
-				" Unknown tag '%s'\n", name);
+				" Unknown tag '%s'\n",
+				name);
 	}
 }
 
@@ -2055,15 +2018,14 @@ static void override_vif_fields(struct vif_t *vif)
 				if (streq(name, vif_name[i]))
 					break;
 			if (i != VIF_Indexes)
-				set_override_vif_field(
-						&vif->vif_field[i],
-						vif_name[i],
-						tag_value,
-						str_value);
+				set_override_vif_field(&vif->vif_field[i],
+						       vif_name[i], tag_value,
+						       str_value);
 			else
 				fprintf(stderr,
 					"VIF:"
-					" Unknown tag '%s'\n", name);
+					" Unknown tag '%s'\n",
+					name);
 		}
 	}
 
@@ -2072,19 +2034,15 @@ static void override_vif_fields(struct vif_t *vif)
 	 * means VIF/VIF_App is to be set by me.
 	 */
 	set_override_vif_field(&vif->vif_app_field[Vendor],
-		vif_app_name[Vendor],
-		NULL,
-		VIF_APP_VENDOR_VALUE);
+			       vif_app_name[Vendor], NULL,
+			       VIF_APP_VENDOR_VALUE);
 
-	set_override_vif_field(&vif->vif_app_field[Name],
-		vif_app_name[Name],
-		NULL,
-		VIF_APP_NAME_VALUE);
+	set_override_vif_field(&vif->vif_app_field[Name], vif_app_name[Name],
+			       NULL, VIF_APP_NAME_VALUE);
 
 	set_override_vif_field(&vif->vif_app_field[Version],
-		vif_app_name[Version],
-		NULL,
-		VIF_APP_VERSION_VALUE);
+			       vif_app_name[Version], NULL,
+			       VIF_APP_VERSION_VALUE);
 }
 
 static int override_gen_vif(char *over_name, struct vif_t *vif)
@@ -2103,8 +2061,7 @@ static int override_gen_vif(char *over_name, struct vif_t *vif)
 		if (is_start_tag(name, "VIF"))
 			override_vif_fields(vif);
 		else
-			fprintf(stderr,
-				"Unknown tag '%s'\n", name);
+			fprintf(stderr, "Unknown tag '%s'\n", name);
 	}
 
 	ov_close();
@@ -2114,14 +2071,11 @@ static int override_gen_vif(char *over_name, struct vif_t *vif)
  * VIF Structure Override from XML file functions
  *****************************************************************************/
 
-
 /*****************************************************************************
  * VIF Structure Initialization Helper Functions
  */
-static void set_vif_field(struct vif_field_t *vif_field,
-			const char *name,
-			const char *tag_value,
-			const char *str_value)
+static void set_vif_field(struct vif_field_t *vif_field, const char *name,
+			  const char *tag_value, const char *str_value)
 {
 	char *ptr;
 
@@ -2135,19 +2089,18 @@ static void set_vif_field(struct vif_field_t *vif_field,
 
 	vif_field->name = name;
 	if (tag_value) {
-		ptr = malloc(strlen(tag_value)+1);
+		ptr = malloc(strlen(tag_value) + 1);
 		strcpy(ptr, tag_value);
 		vif_field->tag_value = ptr;
 	}
 	if (str_value) {
-		ptr = malloc(strlen(str_value)+1);
+		ptr = malloc(strlen(str_value) + 1);
 		strcpy(ptr, str_value);
 		vif_field->str_value = ptr;
 	}
 }
 __maybe_unused static void set_vif_field_b(struct vif_field_t *vif_field,
-			const char *name,
-			const bool val)
+					   const char *name, const bool val)
 {
 	if (val)
 		set_vif_field(vif_field, name, "true", NULL);
@@ -2155,9 +2108,9 @@ __maybe_unused static void set_vif_field_b(struct vif_field_t *vif_field,
 		set_vif_field(vif_field, name, "false", NULL);
 }
 __maybe_unused static void set_vif_field_stis(struct vif_field_t *vif_field,
-			const char *name,
-			const char *tag_value,
-			const int str_value)
+					      const char *name,
+					      const char *tag_value,
+					      const int str_value)
 {
 	char str_str[20];
 
@@ -2165,9 +2118,9 @@ __maybe_unused static void set_vif_field_stis(struct vif_field_t *vif_field,
 	set_vif_field(vif_field, name, tag_value, str_str);
 }
 __maybe_unused static void set_vif_field_itss(struct vif_field_t *vif_field,
-			const char *name,
-			const int tag_value,
-			const char *str_value)
+					      const char *name,
+					      const int tag_value,
+					      const char *str_value)
 {
 	char str_tag[20];
 
@@ -2175,9 +2128,9 @@ __maybe_unused static void set_vif_field_itss(struct vif_field_t *vif_field,
 	set_vif_field(vif_field, name, str_tag, str_value);
 }
 __maybe_unused static void set_vif_field_itis(struct vif_field_t *vif_field,
-			const char *name,
-			const int tag_value,
-			const int str_value)
+					      const char *name,
+					      const int tag_value,
+					      const int str_value)
 {
 	char str_tag[20];
 	char str_str[20];
@@ -2369,16 +2322,17 @@ __maybe_unused static int32_t init_vif_snk_pdo(struct vif_snkPdoList_t *snkPdo,
 		power_mw = (current_ma * voltage_mv) / 1000;
 
 		set_vif_field(&snkPdo->vif_field[Snk_PDO_Supply_Type],
-			vif_component_snk_pdo_name[Snk_PDO_Supply_Type],
-			"0", "Fixed");
+			      vif_component_snk_pdo_name[Snk_PDO_Supply_Type],
+			      "0", "Fixed");
 		sprintf(str, "%d mV", voltage_mv);
 		set_vif_field_itss(&snkPdo->vif_field[Snk_PDO_Voltage],
-			vif_component_snk_pdo_name[Snk_PDO_Voltage],
-			voltage, str);
+				   vif_component_snk_pdo_name[Snk_PDO_Voltage],
+				   voltage, str);
 		sprintf(str, "%d mA", current_ma);
-		set_vif_field_itss(&snkPdo->vif_field[Snk_PDO_Op_Current],
-			vif_component_snk_pdo_name[Snk_PDO_Op_Current],
-			current, str);
+		set_vif_field_itss(
+			&snkPdo->vif_field[Snk_PDO_Op_Current],
+			vif_component_snk_pdo_name[Snk_PDO_Op_Current], current,
+			str);
 
 	} else if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_BATTERY) {
 		uint32_t max_voltage = (pdo >> 20) & 0x3ff;
@@ -2391,20 +2345,22 @@ __maybe_unused static int32_t init_vif_snk_pdo(struct vif_snkPdoList_t *snkPdo,
 		power_mw = power * 250;
 
 		set_vif_field(&snkPdo->vif_field[Snk_PDO_Supply_Type],
-			vif_component_snk_pdo_name[Snk_PDO_Supply_Type],
-			"1", "Battery");
+			      vif_component_snk_pdo_name[Snk_PDO_Supply_Type],
+			      "1", "Battery");
 		sprintf(str, "%d mV", min_voltage_mv);
-		set_vif_field_itss(&snkPdo->vif_field[Snk_PDO_Min_Voltage],
+		set_vif_field_itss(
+			&snkPdo->vif_field[Snk_PDO_Min_Voltage],
 			vif_component_snk_pdo_name[Snk_PDO_Min_Voltage],
 			min_voltage, str);
 		sprintf(str, "%d mV", max_voltage_mv);
-		set_vif_field_itss(&snkPdo->vif_field[Snk_PDO_Max_Voltage],
+		set_vif_field_itss(
+			&snkPdo->vif_field[Snk_PDO_Max_Voltage],
 			vif_component_snk_pdo_name[Snk_PDO_Max_Voltage],
 			max_voltage, str);
 		sprintf(str, "%d mW", power_mw);
 		set_vif_field_itss(&snkPdo->vif_field[Snk_PDO_Op_Power],
-			vif_component_snk_pdo_name[Snk_PDO_Op_Power],
-			power, str);
+				   vif_component_snk_pdo_name[Snk_PDO_Op_Power],
+				   power, str);
 
 	} else if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_VARIABLE) {
 		uint32_t max_voltage = (pdo >> 20) & 0x3ff;
@@ -2417,20 +2373,23 @@ __maybe_unused static int32_t init_vif_snk_pdo(struct vif_snkPdoList_t *snkPdo,
 		power_mw = (current_ma * max_voltage_mv) / 1000;
 
 		set_vif_field(&snkPdo->vif_field[Snk_PDO_Supply_Type],
-			vif_component_snk_pdo_name[Snk_PDO_Supply_Type],
-			"2", "Variable");
+			      vif_component_snk_pdo_name[Snk_PDO_Supply_Type],
+			      "2", "Variable");
 		sprintf(str, "%d mV", min_voltage_mv);
-		set_vif_field_itss(&snkPdo->vif_field[Snk_PDO_Min_Voltage],
+		set_vif_field_itss(
+			&snkPdo->vif_field[Snk_PDO_Min_Voltage],
 			vif_component_snk_pdo_name[Snk_PDO_Min_Voltage],
 			min_voltage, str);
 		sprintf(str, "%d mV", max_voltage_mv);
-		set_vif_field_itss(&snkPdo->vif_field[Snk_PDO_Max_Voltage],
+		set_vif_field_itss(
+			&snkPdo->vif_field[Snk_PDO_Max_Voltage],
 			vif_component_snk_pdo_name[Snk_PDO_Max_Voltage],
 			max_voltage, str);
 		sprintf(str, "%d mA", current_ma);
-		set_vif_field_itss(&snkPdo->vif_field[Snk_PDO_Op_Current],
-			vif_component_snk_pdo_name[Snk_PDO_Op_Current],
-			current, str);
+		set_vif_field_itss(
+			&snkPdo->vif_field[Snk_PDO_Op_Current],
+			vif_component_snk_pdo_name[Snk_PDO_Op_Current], current,
+			str);
 
 	} else if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_AUGMENTED) {
 		uint32_t pps = (pdo >> 28) & 3;
@@ -2449,18 +2408,21 @@ __maybe_unused static int32_t init_vif_snk_pdo(struct vif_snkPdoList_t *snkPdo,
 		power_mw = (pps_current_ma * pps_max_voltage_mv) / 1000;
 
 		set_vif_field(&snkPdo->vif_field[Snk_PDO_Supply_Type],
-			vif_component_snk_pdo_name[Snk_PDO_Supply_Type],
-			"3", "PPS");
+			      vif_component_snk_pdo_name[Snk_PDO_Supply_Type],
+			      "3", "PPS");
 		sprintf(str, "%d mA", pps_current_ma);
-		set_vif_field_itss(&snkPdo->vif_field[Snk_PDO_Op_Current],
+		set_vif_field_itss(
+			&snkPdo->vif_field[Snk_PDO_Op_Current],
 			vif_component_snk_pdo_name[Snk_PDO_Op_Current],
 			pps_current, str);
 		sprintf(str, "%d mV", pps_min_voltage_mv);
-		set_vif_field_itss(&snkPdo->vif_field[Snk_PDO_Min_Voltage],
+		set_vif_field_itss(
+			&snkPdo->vif_field[Snk_PDO_Min_Voltage],
 			vif_component_snk_pdo_name[Snk_PDO_Min_Voltage],
 			pps_min_voltage, str);
 		sprintf(str, "%d mV", pps_max_voltage_mv);
-		set_vif_field_itss(&snkPdo->vif_field[Snk_PDO_Max_Voltage],
+		set_vif_field_itss(
+			&snkPdo->vif_field[Snk_PDO_Max_Voltage],
 			vif_component_snk_pdo_name[Snk_PDO_Max_Voltage],
 			pps_max_voltage, str);
 	} else {
@@ -2501,17 +2463,18 @@ __maybe_unused static int32_t init_vif_src_pdo(struct vif_srcPdoList_t *srcPdo,
 		power_mw = (current_ma * voltage_mv) / 1000;
 
 		set_vif_field(&srcPdo->vif_field[Src_PDO_Supply_Type],
-			vif_component_src_pdo_name[Src_PDO_Supply_Type],
-			"0", "Fixed");
+			      vif_component_src_pdo_name[Src_PDO_Supply_Type],
+			      "0", "Fixed");
 		set_vif_field(&srcPdo->vif_field[Src_PDO_Peak_Current],
-			vif_component_src_pdo_name[Src_PDO_Peak_Current],
-			"0", "100% IOC");
+			      vif_component_src_pdo_name[Src_PDO_Peak_Current],
+			      "0", "100% IOC");
 		sprintf(str, "%d mV", voltage_mv);
 		set_vif_field_itss(&srcPdo->vif_field[Src_PDO_Voltage],
-			vif_component_src_pdo_name[Src_PDO_Voltage],
-			voltage, str);
+				   vif_component_src_pdo_name[Src_PDO_Voltage],
+				   voltage, str);
 		sprintf(str, "%d mA", current_ma);
-		set_vif_field_itss(&srcPdo->vif_field[Src_PDO_Max_Current],
+		set_vif_field_itss(
+			&srcPdo->vif_field[Src_PDO_Max_Current],
 			vif_component_src_pdo_name[Src_PDO_Max_Current],
 			current, str);
 
@@ -2526,20 +2489,23 @@ __maybe_unused static int32_t init_vif_src_pdo(struct vif_srcPdoList_t *srcPdo,
 		power_mw = power * 250;
 
 		set_vif_field(&srcPdo->vif_field[Src_PDO_Supply_Type],
-			vif_component_src_pdo_name[Src_PDO_Supply_Type],
-			"1", "Battery");
+			      vif_component_src_pdo_name[Src_PDO_Supply_Type],
+			      "1", "Battery");
 		sprintf(str, "%d mV", min_voltage_mv);
-		set_vif_field_itss(&srcPdo->vif_field[Src_PDO_Min_Voltage],
+		set_vif_field_itss(
+			&srcPdo->vif_field[Src_PDO_Min_Voltage],
 			vif_component_src_pdo_name[Src_PDO_Min_Voltage],
 			min_voltage, str);
 		sprintf(str, "%d mV", max_voltage_mv);
-		set_vif_field_itss(&srcPdo->vif_field[Src_PDO_Max_Voltage],
+		set_vif_field_itss(
+			&srcPdo->vif_field[Src_PDO_Max_Voltage],
 			vif_component_src_pdo_name[Src_PDO_Max_Voltage],
 			max_voltage, str);
 		sprintf(str, "%d mW", power_mw);
-		set_vif_field_itss(&srcPdo->vif_field[Src_PDO_Max_Power],
-			vif_component_src_pdo_name[Src_PDO_Max_Power],
-			power, str);
+		set_vif_field_itss(
+			&srcPdo->vif_field[Src_PDO_Max_Power],
+			vif_component_src_pdo_name[Src_PDO_Max_Power], power,
+			str);
 
 	} else if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_VARIABLE) {
 		uint32_t max_voltage = (pdo >> 20) & 0x3ff;
@@ -2552,21 +2518,24 @@ __maybe_unused static int32_t init_vif_src_pdo(struct vif_srcPdoList_t *srcPdo,
 		power_mw = (current_ma * max_voltage_mv) / 1000;
 
 		set_vif_field(&srcPdo->vif_field[Src_PDO_Supply_Type],
-			vif_component_src_pdo_name[Src_PDO_Supply_Type],
-			"2", "Variable");
+			      vif_component_src_pdo_name[Src_PDO_Supply_Type],
+			      "2", "Variable");
 		set_vif_field(&srcPdo->vif_field[Src_PDO_Peak_Current],
-			vif_component_src_pdo_name[Src_PDO_Peak_Current],
-			"0", "100% IOC");
+			      vif_component_src_pdo_name[Src_PDO_Peak_Current],
+			      "0", "100% IOC");
 		sprintf(str, "%d mV", min_voltage_mv);
-		set_vif_field_itss(&srcPdo->vif_field[Src_PDO_Min_Voltage],
+		set_vif_field_itss(
+			&srcPdo->vif_field[Src_PDO_Min_Voltage],
 			vif_component_src_pdo_name[Src_PDO_Min_Voltage],
 			min_voltage, str);
 		sprintf(str, "%d mV", max_voltage_mv);
-		set_vif_field_itss(&srcPdo->vif_field[Src_PDO_Max_Voltage],
+		set_vif_field_itss(
+			&srcPdo->vif_field[Src_PDO_Max_Voltage],
 			vif_component_src_pdo_name[Src_PDO_Max_Voltage],
 			max_voltage, str);
 		sprintf(str, "%d mA", current_ma);
-		set_vif_field_itss(&srcPdo->vif_field[Src_PDO_Max_Current],
+		set_vif_field_itss(
+			&srcPdo->vif_field[Src_PDO_Max_Current],
 			vif_component_src_pdo_name[Src_PDO_Max_Current],
 			current, str);
 
@@ -2587,18 +2556,21 @@ __maybe_unused static int32_t init_vif_src_pdo(struct vif_srcPdoList_t *srcPdo,
 		power_mw = (pps_current_ma * pps_max_voltage_mv) / 1000;
 
 		set_vif_field(&srcPdo->vif_field[Src_PDO_Supply_Type],
-			vif_component_src_pdo_name[Src_PDO_Supply_Type],
-			"3", "PPS");
+			      vif_component_src_pdo_name[Src_PDO_Supply_Type],
+			      "3", "PPS");
 		sprintf(str, "%d mA", pps_current_ma);
-		set_vif_field_itss(&srcPdo->vif_field[Src_PDO_Max_Current],
+		set_vif_field_itss(
+			&srcPdo->vif_field[Src_PDO_Max_Current],
 			vif_component_src_pdo_name[Src_PDO_Max_Current],
 			pps_current, str);
 		sprintf(str, "%d mV", pps_min_voltage_mv);
-		set_vif_field_itss(&srcPdo->vif_field[Src_PDO_Min_Voltage],
+		set_vif_field_itss(
+			&srcPdo->vif_field[Src_PDO_Min_Voltage],
 			vif_component_src_pdo_name[Src_PDO_Min_Voltage],
 			pps_min_voltage, str);
 		sprintf(str, "%d mV", pps_max_voltage_mv);
-		set_vif_field_itss(&srcPdo->vif_field[Src_PDO_Max_Voltage],
+		set_vif_field_itss(
+			&srcPdo->vif_field[Src_PDO_Max_Voltage],
 			vif_component_src_pdo_name[Src_PDO_Max_Voltage],
 			pps_max_voltage, str);
 
@@ -2614,157 +2586,120 @@ __maybe_unused static int32_t init_vif_src_pdo(struct vif_srcPdoList_t *srcPdo,
  * Init VIF Fields
  */
 static void init_vif_fields(struct vif_field_t *vif_fields,
-			struct vif_field_t *vif_app_fields,
-			const char *board)
+			    struct vif_field_t *vif_app_fields,
+			    const char *board)
 {
 	set_vif_field(&vif_fields[VIF_Specification],
-		vif_name[VIF_Specification],
-		NULL,
-		"3.18");
-
-	set_vif_field(&vif_app_fields[Vendor],
-		vif_app_name[Vendor],
-		NULL,
-		VIF_APP_VENDOR_VALUE);
-
-	set_vif_field(&vif_app_fields[Name],
-		vif_app_name[Name],
-		NULL,
-		VIF_APP_NAME_VALUE);
-
-	set_vif_field(&vif_app_fields[Version],
-		vif_app_name[Version],
-		NULL,
-		VIF_APP_VERSION_VALUE);
-
-	set_vif_field(&vif_fields[Vendor_Name],
-		vif_name[Vendor_Name],
-		NULL,
-		VENDOR_NAME_VALUE);
-
-	#if defined(CONFIG_USB_PD_MODEL_PART_NUMBER)
+		      vif_name[VIF_Specification], NULL, "3.18");
+
+	set_vif_field(&vif_app_fields[Vendor], vif_app_name[Vendor], NULL,
+		      VIF_APP_VENDOR_VALUE);
+
+	set_vif_field(&vif_app_fields[Name], vif_app_name[Name], NULL,
+		      VIF_APP_NAME_VALUE);
+
+	set_vif_field(&vif_app_fields[Version], vif_app_name[Version], NULL,
+		      VIF_APP_VERSION_VALUE);
+
+	set_vif_field(&vif_fields[Vendor_Name], vif_name[Vendor_Name], NULL,
+		      VENDOR_NAME_VALUE);
+
+#if defined(CONFIG_USB_PD_MODEL_PART_NUMBER)
+	set_vif_field(&vif_fields[Model_Part_Number],
+		      vif_name[Model_Part_Number], NULL,
+		      CONFIG_USB_PD_MODEL_PART_NUMBER);
+#else
+	if (board && strlen(board) > 0)
 		set_vif_field(&vif_fields[Model_Part_Number],
-			vif_name[Model_Part_Number],
-			NULL,
-			CONFIG_USB_PD_MODEL_PART_NUMBER);
-	#else
-		if (board && strlen(board) > 0)
-			set_vif_field(&vif_fields[Model_Part_Number],
-				vif_name[Model_Part_Number],
-				NULL,
-				board);
-		else
-			set_vif_field(&vif_fields[Model_Part_Number],
-				vif_name[Model_Part_Number],
-				NULL,
-				"FIX-ME");
-	#endif
-
-	#if defined(CONFIG_USB_PD_PRODUCT_REVISION)
-		set_vif_field(&vif_fields[Product_Revision],
-			vif_name[Product_Revision],
-			NULL,
-			CONFIG_USB_PD_PRODUCT_REVISION);
-	#else
-		set_vif_field(&vif_fields[Product_Revision],
-			vif_name[Product_Revision],
-			NULL,
-			"FIX-ME");
-	#endif
-
-	#if defined(CONFIG_USB_PD_TID)
-		set_vif_field_stis(&vif_fields[TID],
-			vif_name[TID],
-			NULL,
-			CONFIG_USB_PD_TID);
-	#else
-		set_vif_field_stis(&vif_fields[TID],
-			vif_name[TID],
-			NULL,
-			DEFAULT_MISSING_TID);
-	#endif
-
-	set_vif_field(&vif_fields[VIF_Product_Type],
-		vif_name[VIF_Product_Type],
-		"0",
-		"Port Product");
+			      vif_name[Model_Part_Number], NULL, board);
+	else
+		set_vif_field(&vif_fields[Model_Part_Number],
+			      vif_name[Model_Part_Number], NULL, "FIX-ME");
+#endif
+
+#if defined(CONFIG_USB_PD_PRODUCT_REVISION)
+	set_vif_field(&vif_fields[Product_Revision], vif_name[Product_Revision],
+		      NULL, CONFIG_USB_PD_PRODUCT_REVISION);
+#else
+	set_vif_field(&vif_fields[Product_Revision], vif_name[Product_Revision],
+		      NULL, "FIX-ME");
+#endif
+
+#if defined(CONFIG_USB_PD_TID)
+	set_vif_field_stis(&vif_fields[TID], vif_name[TID], NULL,
+			   CONFIG_USB_PD_TID);
+#else
+	set_vif_field_stis(&vif_fields[TID], vif_name[TID], NULL,
+			   DEFAULT_MISSING_TID);
+#endif
+
+	set_vif_field(&vif_fields[VIF_Product_Type], vif_name[VIF_Product_Type],
+		      "0", "Port Product");
 
 	set_vif_field(&vif_fields[Certification_Type],
-		vif_name[Certification_Type],
-		"0",
-		"End Product");
+		      vif_name[Certification_Type], "0", "End Product");
 }
 
 /*********************************************************************
  * Init VIF/Component[] Fields
  */
 static void init_vif_component_fields(struct vif_field_t *vif_fields,
-			enum bc_1_2_support *bc_support,
-			enum dtype type)
-{
-	#if defined(CONFIG_USB_PD_PORT_LABEL)
-		set_vif_field_stis(&vif_fields[Port_Label],
-			vif_component_name[Port_Label],
-			NULL,
-			CONFIG_USB_PD_PORT_LABEL);
-	#else
-		set_vif_field_stis(&vif_fields[Port_Label],
-			vif_component_name[Port_Label],
-			NULL,
-			component_index);
-	#endif
+				      enum bc_1_2_support *bc_support,
+				      enum dtype type)
+{
+#if defined(CONFIG_USB_PD_PORT_LABEL)
+	set_vif_field_stis(&vif_fields[Port_Label],
+			   vif_component_name[Port_Label], NULL,
+			   CONFIG_USB_PD_PORT_LABEL);
+#else
+	set_vif_field_stis(&vif_fields[Port_Label],
+			   vif_component_name[Port_Label], NULL,
+			   component_index);
+#endif
 
 	set_vif_field(&vif_fields[Connector_Type],
-		vif_component_name[Connector_Type],
-		"2",
-		"Type-C®");
+		      vif_component_name[Connector_Type], "2", "Type-C®");
 
 	if (is_usb4_supported()) {
 		int router_index;
 
 		set_vif_field_b(&vif_fields[USB4_Supported],
-			vif_component_name[USB4_Supported],
-			true);
+				vif_component_name[USB4_Supported], true);
 
 		if (!get_vif_field_tag_number(
-				&vif.Product.USB4RouterList[0]
-					.vif_field[USB4_Router_ID],
-				&router_index)) {
+			    &vif.Product.USB4RouterList[0]
+				     .vif_field[USB4_Router_ID],
+			    &router_index)) {
 			router_index = 0;
 		}
 		set_vif_field_itss(&vif_fields[USB4_Router_Index],
-			vif_component_name[USB4_Router_Index],
-			router_index,
-			NULL);
+				   vif_component_name[USB4_Router_Index],
+				   router_index, NULL);
 	} else {
 		set_vif_field_b(&vif_fields[USB4_Supported],
-			vif_component_name[USB4_Supported],
-			false);
+				vif_component_name[USB4_Supported], false);
 	}
 
 	set_vif_field_b(&vif_fields[USB_PD_Support],
-		vif_component_name[USB_PD_Support],
-		is_usb_pd_supported());
+			vif_component_name[USB_PD_Support],
+			is_usb_pd_supported());
 
 	if (is_usb_pd_supported()) {
 		switch (type) {
 		case SNK:
 			set_vif_field(&vif_fields[PD_Port_Type],
-				vif_component_name[PD_Port_Type],
-				"0",
-				"Consumer Only");
+				      vif_component_name[PD_Port_Type], "0",
+				      "Consumer Only");
 			break;
 		case SRC:
 			set_vif_field(&vif_fields[PD_Port_Type],
-				vif_component_name[PD_Port_Type],
-				"3",
-				"Provider Only");
+				      vif_component_name[PD_Port_Type], "3",
+				      "Provider Only");
 			break;
 		case DRP:
 			set_vif_field(&vif_fields[PD_Port_Type],
-				vif_component_name[PD_Port_Type],
-				"4",
-				"DRP");
+				      vif_component_name[PD_Port_Type], "4",
+				      "DRP");
 			break;
 		}
 	}
@@ -2772,31 +2707,27 @@ static void init_vif_component_fields(struct vif_field_t *vif_fields,
 	switch (type) {
 	case SNK:
 		set_vif_field(&vif_fields[Type_C_State_Machine],
-			vif_component_name[Type_C_State_Machine],
-			"1",
-			"SNK");
+			      vif_component_name[Type_C_State_Machine], "1",
+			      "SNK");
 		break;
 	case SRC:
 		set_vif_field(&vif_fields[Type_C_State_Machine],
-			vif_component_name[Type_C_State_Machine],
-			"0",
-			"SRC");
+			      vif_component_name[Type_C_State_Machine], "0",
+			      "SRC");
 		break;
 	case DRP:
 		set_vif_field(&vif_fields[Type_C_State_Machine],
-			vif_component_name[Type_C_State_Machine],
-			"2",
-			"DRP");
+			      vif_component_name[Type_C_State_Machine], "2",
+			      "DRP");
 		break;
 	}
 
 	set_vif_field_b(&vif_fields[Captive_Cable],
-		vif_component_name[Captive_Cable],
-		false);
+			vif_component_name[Captive_Cable], false);
 
 	set_vif_field_b(&vif_fields[Port_Battery_Powered],
-		vif_component_name[Port_Battery_Powered],
-		IS_ENABLED(CONFIG_BATTERY));
+			vif_component_name[Port_Battery_Powered],
+			IS_ENABLED(CONFIG_BATTERY));
 
 	*bc_support = BC_1_2_SUPPORT_NONE;
 	if (IS_ENABLED(CONFIG_BC12_DETECT_MAX14637))
@@ -2811,27 +2742,21 @@ static void init_vif_component_fields(struct vif_field_t *vif_fields,
 	switch (*bc_support) {
 	case BC_1_2_SUPPORT_NONE:
 		set_vif_field(&vif_fields[BC_1_2_Support],
-			vif_component_name[BC_1_2_Support],
-			"0",
-			"None");
+			      vif_component_name[BC_1_2_Support], "0", "None");
 		break;
 	case BC_1_2_SUPPORT_PORTABLE_DEVICE:
 		set_vif_field(&vif_fields[BC_1_2_Support],
-			vif_component_name[BC_1_2_Support],
-			"1",
-			"Portable Device");
+			      vif_component_name[BC_1_2_Support], "1",
+			      "Portable Device");
 		break;
 	case BC_1_2_SUPPORT_CHARGING_PORT:
 		set_vif_field(&vif_fields[BC_1_2_Support],
-			vif_component_name[BC_1_2_Support],
-			"2",
-			"Charging Port");
+			      vif_component_name[BC_1_2_Support], "2",
+			      "Charging Port");
 		break;
 	case BC_1_2_SUPPORT_BOTH:
 		set_vif_field(&vif_fields[BC_1_2_Support],
-			vif_component_name[BC_1_2_Support],
-			"3",
-			"Both");
+			      vif_component_name[BC_1_2_Support], "3", "Both");
 		break;
 	}
 }
@@ -2839,54 +2764,43 @@ static void init_vif_component_fields(struct vif_field_t *vif_fields,
 /*********************************************************************
  * Init VIF/Component[] General PD Fields
  */
-static void init_vif_component_general_pd_fields(
-			struct vif_field_t *vif_fields,
-			enum dtype type)
+static void init_vif_component_general_pd_fields(struct vif_field_t *vif_fields,
+						 enum dtype type)
 {
 	if (IS_ENABLED(CONFIG_USB_PD_REV30) || IS_ENABLED(CONFIG_USB_PRL_SM)) {
 		set_vif_field(&vif_fields[PD_Spec_Revision_Major],
-			vif_component_name[PD_Spec_Revision_Major],
-			"3",
-			NULL);
+			      vif_component_name[PD_Spec_Revision_Major], "3",
+			      NULL);
 		set_vif_field(&vif_fields[PD_Spec_Revision_Minor],
-			vif_component_name[PD_Spec_Revision_Minor],
-			"1",
-			NULL);
+			      vif_component_name[PD_Spec_Revision_Minor], "1",
+			      NULL);
 		set_vif_field(&vif_fields[PD_Spec_Version_Major],
-			vif_component_name[PD_Spec_Version_Major],
-			"1",
-			NULL);
+			      vif_component_name[PD_Spec_Version_Major], "1",
+			      NULL);
 		set_vif_field(&vif_fields[PD_Spec_Version_Minor],
-			vif_component_name[PD_Spec_Version_Minor],
-			"3",
-			NULL);
+			      vif_component_name[PD_Spec_Version_Minor], "3",
+			      NULL);
 
 		set_vif_field(&vif_fields[PD_Specification_Revision],
-			vif_component_name[PD_Specification_Revision],
-			"2",
-			"Revision 3");
+			      vif_component_name[PD_Specification_Revision],
+			      "2", "Revision 3");
 	} else {
 		set_vif_field(&vif_fields[PD_Spec_Revision_Major],
-			vif_component_name[PD_Spec_Revision_Major],
-			"2",
-			NULL);
+			      vif_component_name[PD_Spec_Revision_Major], "2",
+			      NULL);
 		set_vif_field(&vif_fields[PD_Spec_Revision_Minor],
-			vif_component_name[PD_Spec_Revision_Minor],
-			"0",
-			NULL);
+			      vif_component_name[PD_Spec_Revision_Minor], "0",
+			      NULL);
 		set_vif_field(&vif_fields[PD_Spec_Version_Major],
-			vif_component_name[PD_Spec_Version_Major],
-			"1",
-			NULL);
+			      vif_component_name[PD_Spec_Version_Major], "1",
+			      NULL);
 		set_vif_field(&vif_fields[PD_Spec_Version_Minor],
-			vif_component_name[PD_Spec_Version_Minor],
-			"3",
-			NULL);
+			      vif_component_name[PD_Spec_Version_Minor], "3",
+			      NULL);
 
 		set_vif_field(&vif_fields[PD_Specification_Revision],
-			vif_component_name[PD_Specification_Revision],
-			"1",
-			"Revision 2");
+			      vif_component_name[PD_Specification_Revision],
+			      "1", "Revision 2");
 	}
 
 	set_vif_field_b(&vif_fields[USB_Comms_Capable],
@@ -2926,18 +2840,18 @@ static void init_vif_component_general_pd_fields(
 			supports_to_dfp = can_act_as_device();
 			break;
 		case SNK:
-			supports_to_dfp = (can_act_as_host() ||
-					   is_alt_mode_controller());
+			supports_to_dfp =
+				(can_act_as_host() || is_alt_mode_controller());
 			break;
 		case DRP:
-			supports_to_dfp = (can_act_as_host() &&
-					   !can_act_as_device());
+			supports_to_dfp =
+				(can_act_as_host() && !can_act_as_device());
 			break;
 		}
 
 		set_vif_field_b(&vif_fields[DR_Swap_To_DFP_Supported],
-			vif_component_name[DR_Swap_To_DFP_Supported],
-			supports_to_dfp);
+				vif_component_name[DR_Swap_To_DFP_Supported],
+				supports_to_dfp);
 	}
 
 	/*
@@ -2968,18 +2882,18 @@ static void init_vif_component_general_pd_fields(
 			supports_to_ufp = can_act_as_device();
 			break;
 		case SNK:
-			supports_to_ufp = (can_act_as_host() ||
-					   is_alt_mode_controller());
+			supports_to_ufp =
+				(can_act_as_host() || is_alt_mode_controller());
 			break;
 		case DRP:
-			supports_to_ufp = (can_act_as_device() &&
-					   !can_act_as_host());
+			supports_to_ufp =
+				(can_act_as_device() && !can_act_as_host());
 			break;
 		}
 
 		set_vif_field_b(&vif_fields[DR_Swap_To_UFP_Supported],
-			vif_component_name[DR_Swap_To_UFP_Supported],
-			supports_to_ufp);
+				vif_component_name[DR_Swap_To_UFP_Supported],
+				supports_to_ufp);
 	}
 
 	if (is_src()) {
@@ -2987,52 +2901,50 @@ static void init_vif_component_general_pd_fields(
 		if (IS_ENABLED(CONFIG_CHARGER))
 			/* USB-C UP bit set */
 			set_vif_field_b(&vif_fields[Unconstrained_Power],
-				vif_component_name[Unconstrained_Power],
-				(src_pdo[0] & PDO_FIXED_UNCONSTRAINED));
+					vif_component_name[Unconstrained_Power],
+					(src_pdo[0] & PDO_FIXED_UNCONSTRAINED));
 		else {
 			/* Barrel charger being used */
 			int32_t dedicated_charge_port_count = 0;
 
-			#ifdef CONFIG_DEDICATED_CHARGE_PORT_COUNT
-				dedicated_charge_port_count =
-					CONFIG_DEDICATED_CHARGE_PORT_COUNT;
-			#endif
+#ifdef CONFIG_DEDICATED_CHARGE_PORT_COUNT
+			dedicated_charge_port_count =
+				CONFIG_DEDICATED_CHARGE_PORT_COUNT;
+#endif
 
 			set_vif_field_b(&vif_fields[Unconstrained_Power],
-				vif_component_name[Unconstrained_Power],
-				(dedicated_charge_port_count > 0));
+					vif_component_name[Unconstrained_Power],
+					(dedicated_charge_port_count > 0));
 		}
 	} else {
 		/* Not SRC capable */
 		set_vif_field_b(&vif_fields[Unconstrained_Power],
-			vif_component_name[Unconstrained_Power],
-			false);
+				vif_component_name[Unconstrained_Power], false);
 	}
 
 	set_vif_field_b(&vif_fields[VCONN_Swap_To_On_Supported],
-		vif_component_name[VCONN_Swap_To_On_Supported],
-		IS_ENABLED(CONFIG_USBC_VCONN_SWAP));
+			vif_component_name[VCONN_Swap_To_On_Supported],
+			IS_ENABLED(CONFIG_USBC_VCONN_SWAP));
 
 	set_vif_field_b(&vif_fields[VCONN_Swap_To_Off_Supported],
-		vif_component_name[VCONN_Swap_To_Off_Supported],
-		IS_ENABLED(CONFIG_USBC_VCONN_SWAP));
+			vif_component_name[VCONN_Swap_To_Off_Supported],
+			IS_ENABLED(CONFIG_USBC_VCONN_SWAP));
 
 	set_vif_field_b(&vif_fields[Responds_To_Discov_SOP_UFP],
-		vif_component_name[Responds_To_Discov_SOP_UFP],
-		does_respond_to_discov_sop_ufp());
+			vif_component_name[Responds_To_Discov_SOP_UFP],
+			does_respond_to_discov_sop_ufp());
 
 	set_vif_field_b(&vif_fields[Responds_To_Discov_SOP_DFP],
-		vif_component_name[Responds_To_Discov_SOP_DFP],
-		does_respond_to_discov_sop_dfp());
+			vif_component_name[Responds_To_Discov_SOP_DFP],
+			does_respond_to_discov_sop_dfp());
 
 	set_vif_field_b(&vif_fields[Attempts_Discov_SOP],
-		vif_component_name[Attempts_Discov_SOP],
-		((!IS_ENABLED(CONFIG_USB_PD_SIMPLE_DFP)) ||
-		 (type != SRC)));
+			vif_component_name[Attempts_Discov_SOP],
+			((!IS_ENABLED(CONFIG_USB_PD_SIMPLE_DFP)) ||
+			 (type != SRC)));
 
 	set_vif_field(&vif_fields[Power_Interruption_Available],
-		      vif_component_name[Power_Interruption_Available],
-		      "0",
+		      vif_component_name[Power_Interruption_Available], "0",
 		      "No Interruption Possible");
 
 	set_vif_field_b(&vif_fields[Data_Reset_Supported],
@@ -3044,141 +2956,137 @@ static void init_vif_component_general_pd_fields(
 			IS_ENABLED(CONFIG_USB_PD_USB4));
 
 	set_vif_field_b(&vif_fields[Chunking_Implemented_SOP],
-		vif_component_name[Chunking_Implemented_SOP],
-		(IS_ENABLED(CONFIG_USB_PD_REV30) &&
-		 IS_ENABLED(CONFIG_USB_PRL_SM)));
+			vif_component_name[Chunking_Implemented_SOP],
+			(IS_ENABLED(CONFIG_USB_PD_REV30) &&
+			 IS_ENABLED(CONFIG_USB_PRL_SM)));
 
-	set_vif_field_b(&vif_fields[Unchunked_Extended_Messages_Supported],
+	set_vif_field_b(
+		&vif_fields[Unchunked_Extended_Messages_Supported],
 		vif_component_name[Unchunked_Extended_Messages_Supported],
 		false);
 
 	if (IS_ENABLED(CONFIG_USB_PD_MANUFACTURER_INFO)) {
 		char hex_str[10];
 
-		set_vif_field_b(&vif_fields[Manufacturer_Info_Supported_Port],
+		set_vif_field_b(
+			&vif_fields[Manufacturer_Info_Supported_Port],
 			vif_component_name[Manufacturer_Info_Supported_Port],
 			true);
 
 		sprintf(hex_str, "%04X", USB_VID_GOOGLE);
-		set_vif_field_itss(&vif_fields[Manufacturer_Info_VID_Port],
+		set_vif_field_itss(
+			&vif_fields[Manufacturer_Info_VID_Port],
 			vif_component_name[Manufacturer_Info_VID_Port],
 			USB_VID_GOOGLE, hex_str);
 
-		#if defined(CONFIG_USB_PID)
-			sprintf(hex_str, "%04X", CONFIG_USB_PID);
-			set_vif_field_itss(&vif_fields[
-				Manufacturer_Info_PID_Port],
-				vif_component_name[Manufacturer_Info_PID_Port],
-				CONFIG_USB_PID, hex_str);
-		#else
-			sprintf(hex_str, "%04X", DEFAULT_MISSING_PID);
-			set_vif_field_itss(&vif_fields[
-				Manufacturer_Info_PID_Port],
-				vif_component_name[Manufacturer_Info_PID_Port],
-				DEFAULT_MISSING_PID, hex_str);
-		#endif
+#if defined(CONFIG_USB_PID)
+		sprintf(hex_str, "%04X", CONFIG_USB_PID);
+		set_vif_field_itss(
+			&vif_fields[Manufacturer_Info_PID_Port],
+			vif_component_name[Manufacturer_Info_PID_Port],
+			CONFIG_USB_PID, hex_str);
+#else
+		sprintf(hex_str, "%04X", DEFAULT_MISSING_PID);
+		set_vif_field_itss(
+			&vif_fields[Manufacturer_Info_PID_Port],
+			vif_component_name[Manufacturer_Info_PID_Port],
+			DEFAULT_MISSING_PID, hex_str);
+#endif
 	} else {
-		set_vif_field_b(&vif_fields[Manufacturer_Info_Supported_Port],
+		set_vif_field_b(
+			&vif_fields[Manufacturer_Info_Supported_Port],
 			vif_component_name[Manufacturer_Info_Supported_Port],
 			false);
 	}
 
 	set_vif_field_b(&vif_fields[Security_Msgs_Supported_SOP],
-		vif_component_name[Security_Msgs_Supported_SOP],
-		IS_ENABLED(CONFIG_USB_PD_SECURITY_MSGS));
-
-	#if defined(CONFIG_NUM_FIXED_BATTERIES)
-		set_vif_field_itss(&vif_fields[Num_Fixed_Batteries],
-			vif_component_name[Num_Fixed_Batteries],
-			CONFIG_NUM_FIXED_BATTERIES, NULL);
-	#elif defined(CONFIG_USB_CTVPD) || defined(CONFIG_USB_VPD)
-		set_vif_field(&vif_fields[Num_Fixed_Batteries],
-			vif_component_name[Num_Fixed_Batteries],
-			"0", NULL);
-	#else
-		set_vif_field(&vif_fields[Num_Fixed_Batteries],
-			vif_component_name[Num_Fixed_Batteries],
-			"1", NULL);
-	#endif
+			vif_component_name[Security_Msgs_Supported_SOP],
+			IS_ENABLED(CONFIG_USB_PD_SECURITY_MSGS));
+
+#if defined(CONFIG_NUM_FIXED_BATTERIES)
+	set_vif_field_itss(&vif_fields[Num_Fixed_Batteries],
+			   vif_component_name[Num_Fixed_Batteries],
+			   CONFIG_NUM_FIXED_BATTERIES, NULL);
+#elif defined(CONFIG_USB_CTVPD) || defined(CONFIG_USB_VPD)
+	set_vif_field(&vif_fields[Num_Fixed_Batteries],
+		      vif_component_name[Num_Fixed_Batteries], "0", NULL);
+#else
+	set_vif_field(&vif_fields[Num_Fixed_Batteries],
+		      vif_component_name[Num_Fixed_Batteries], "1", NULL);
+#endif
 
 	set_vif_field(&vif_fields[Num_Swappable_Battery_Slots],
-		vif_component_name[Num_Swappable_Battery_Slots],
-		"0", NULL);
+		      vif_component_name[Num_Swappable_Battery_Slots], "0",
+		      NULL);
 
 	set_vif_field(&vif_fields[ID_Header_Connector_Type_SOP],
-		vif_component_name[ID_Header_Connector_Type_SOP],
-		"2", "USB Type-C\u00ae Receptacle");
+		      vif_component_name[ID_Header_Connector_Type_SOP], "2",
+		      "USB Type-C\u00ae Receptacle");
 }
 
 /*********************************************************************
  * Init VIF/Component[] SOP* Capabilities Fields
  */
-static void init_vif_component_sop_capabilities_fields(
-			struct vif_field_t *vif_fields)
+static void
+init_vif_component_sop_capabilities_fields(struct vif_field_t *vif_fields)
 {
 	set_vif_field_b(&vif_fields[SOP_Capable],
-		vif_component_name[SOP_Capable],
-		can_act_as_host());
+			vif_component_name[SOP_Capable], can_act_as_host());
 
 	set_vif_field_b(&vif_fields[SOP_P_Capable],
-		vif_component_name[SOP_P_Capable],
-		IS_ENABLED(CONFIG_USB_PD_DECODE_SOP));
+			vif_component_name[SOP_P_Capable],
+			IS_ENABLED(CONFIG_USB_PD_DECODE_SOP));
 
 	set_vif_field_b(&vif_fields[SOP_PP_Capable],
-		vif_component_name[SOP_PP_Capable],
-		IS_ENABLED(CONFIG_USB_PD_DECODE_SOP));
+			vif_component_name[SOP_PP_Capable],
+			IS_ENABLED(CONFIG_USB_PD_DECODE_SOP));
 
 	set_vif_field_b(&vif_fields[SOP_P_Debug_Capable],
-		vif_component_name[SOP_P_Debug_Capable],
-		false);
+			vif_component_name[SOP_P_Debug_Capable], false);
 
 	set_vif_field_b(&vif_fields[SOP_PP_Debug_Capable],
-		vif_component_name[SOP_PP_Debug_Capable],
-		false);
+			vif_component_name[SOP_PP_Debug_Capable], false);
 }
 
 /*********************************************************************
  * Init VIF/Component[] USB Type-C Fields
  */
-static void init_vif_component_usb_type_c_fields(
-			struct vif_field_t *vif_fields,
-			enum dtype type)
+static void init_vif_component_usb_type_c_fields(struct vif_field_t *vif_fields,
+						 enum dtype type)
 {
 	set_vif_field_b(&vif_fields[Type_C_Implements_Try_SRC],
-		vif_component_name[Type_C_Implements_Try_SRC],
-		IS_ENABLED(CONFIG_USB_PD_TRY_SRC));
+			vif_component_name[Type_C_Implements_Try_SRC],
+			IS_ENABLED(CONFIG_USB_PD_TRY_SRC));
 
 	set_vif_field_b(&vif_fields[Type_C_Implements_Try_SNK],
-		vif_component_name[Type_C_Implements_Try_SNK],
-		false);
+			vif_component_name[Type_C_Implements_Try_SNK], false);
 
 	{
 		int rp = CONFIG_USB_PD_PULLUP;
 
-		#if defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT)
-			rp = CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT;
-		#endif
+#if defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT)
+		rp = CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT;
+#endif
 
 		switch (rp) {
 		case 0:
 			set_vif_field(&vif_fields[RP_Value],
-				vif_component_name[RP_Value],
-				"0", "Default");
+				      vif_component_name[RP_Value], "0",
+				      "Default");
 			break;
 		case 1:
 			set_vif_field(&vif_fields[RP_Value],
-				vif_component_name[RP_Value],
-				"1", "1.5A");
+				      vif_component_name[RP_Value], "1",
+				      "1.5A");
 			break;
 		case 2:
 			set_vif_field(&vif_fields[RP_Value],
-				vif_component_name[RP_Value],
-				"2", "3A");
+				      vif_component_name[RP_Value], "2", "3A");
 			break;
 		default:
 			set_vif_field_itss(&vif_fields[RP_Value],
-				vif_component_name[RP_Value],
-				rp, NULL);
+					   vif_component_name[RP_Value], rp,
+					   NULL);
 		}
 	}
 
@@ -3190,39 +3098,37 @@ static void init_vif_component_usb_type_c_fields(
 			false);
 
 	set_vif_field_b(&vif_fields[Type_C_Is_VCONN_Powered_Accessory],
-		vif_component_name[Type_C_Is_VCONN_Powered_Accessory],
-		false);
+			vif_component_name[Type_C_Is_VCONN_Powered_Accessory],
+			false);
 
 	set_vif_field_b(&vif_fields[Type_C_Is_Debug_Target_SRC],
-		vif_component_name[Type_C_Is_Debug_Target_SRC],
-		true);
+			vif_component_name[Type_C_Is_Debug_Target_SRC], true);
 
 	set_vif_field_b(&vif_fields[Type_C_Is_Debug_Target_SNK],
-		vif_component_name[Type_C_Is_Debug_Target_SNK],
-		true);
+			vif_component_name[Type_C_Is_Debug_Target_SNK], true);
 
 	set_vif_field_b(&vif_fields[Type_C_Can_Act_As_Host],
-		vif_component_name[Type_C_Can_Act_As_Host],
-		can_act_as_host());
+			vif_component_name[Type_C_Can_Act_As_Host],
+			can_act_as_host());
 
 	set_vif_field_b(&vif_fields[Type_C_Is_Alt_Mode_Controller],
-		vif_component_name[Type_C_Is_Alt_Mode_Controller],
-		is_alt_mode_controller());
+			vif_component_name[Type_C_Is_Alt_Mode_Controller],
+			is_alt_mode_controller());
 
 	if (can_act_as_device()) {
 		set_vif_field_b(&vif_fields[Type_C_Can_Act_As_Device],
-			vif_component_name[Type_C_Can_Act_As_Device],
-			true);
+				vif_component_name[Type_C_Can_Act_As_Device],
+				true);
 
-		if (is_usb_pd_supported() &&
-		    does_respond_to_discov_sop_ufp())
-			set_vif_field_b(&vif_fields[Type_C_Is_Alt_Mode_Adapter],
+		if (is_usb_pd_supported() && does_respond_to_discov_sop_ufp())
+			set_vif_field_b(
+				&vif_fields[Type_C_Is_Alt_Mode_Adapter],
 				vif_component_name[Type_C_Is_Alt_Mode_Adapter],
 				IS_ENABLED(CONFIG_USB_ALT_MODE_ADAPTER));
 	} else {
 		set_vif_field_b(&vif_fields[Type_C_Can_Act_As_Device],
-			vif_component_name[Type_C_Can_Act_As_Device],
-			false);
+				vif_component_name[Type_C_Can_Act_As_Device],
+				false);
 		set_vif_field_b(&vif_fields[Type_C_Is_Alt_Mode_Adapter],
 				vif_component_name[Type_C_Is_Alt_Mode_Adapter],
 				false);
@@ -3247,37 +3153,37 @@ static void init_vif_component_usb_type_c_fields(
 		switch (ps) {
 		case POWER_EXTERNAL:
 			set_vif_field(&vif_fields[Type_C_Power_Source],
-				vif_component_name[Type_C_Power_Source],
-				"0", "Externally Powered");
+				      vif_component_name[Type_C_Power_Source],
+				      "0", "Externally Powered");
 			break;
 		case POWER_UFP:
 			set_vif_field(&vif_fields[Type_C_Power_Source],
-				vif_component_name[Type_C_Power_Source],
-				"1", "UFP-powered");
+				      vif_component_name[Type_C_Power_Source],
+				      "1", "UFP-powered");
 			break;
 		case POWER_BOTH:
 			set_vif_field(&vif_fields[Type_C_Power_Source],
-				vif_component_name[Type_C_Power_Source],
-				"2", "Both");
+				      vif_component_name[Type_C_Power_Source],
+				      "2", "Both");
 			break;
 		default:
-			set_vif_field_itss(&vif_fields[Type_C_Power_Source],
-				vif_component_name[Type_C_Power_Source],
-				ps, NULL);
+			set_vif_field_itss(
+				&vif_fields[Type_C_Power_Source],
+				vif_component_name[Type_C_Power_Source], ps,
+				NULL);
 		}
 	}
 
 	set_vif_field_b(&vif_fields[Type_C_Port_On_Hub],
-		vif_component_name[Type_C_Port_On_Hub],
-		false);
+			vif_component_name[Type_C_Port_On_Hub], false);
 
 	set_vif_field_b(&vif_fields[Type_C_Supports_Audio_Accessory],
-		vif_component_name[Type_C_Supports_Audio_Accessory],
-		false);
+			vif_component_name[Type_C_Supports_Audio_Accessory],
+			false);
 
 	set_vif_field_b(&vif_fields[Type_C_Sources_VCONN],
-		vif_component_name[Type_C_Sources_VCONN],
-		IS_ENABLED(CONFIG_USBC_VCONN));
+			vif_component_name[Type_C_Sources_VCONN],
+			IS_ENABLED(CONFIG_USBC_VCONN));
 }
 
 static void init_vif_component_usb4_port_fields(struct vif_field_t *vif_fields)
@@ -3288,8 +3194,7 @@ static void init_vif_component_usb4_port_fields(struct vif_field_t *vif_fields)
 	if (!is_usb4_supported())
 		return;
 
-	set_vif_field_c(&vif_fields[USB4_Port_Header],
-			"USB4\u2122 Port");
+	set_vif_field_c(&vif_fields[USB4_Port_Header], "USB4\u2122 Port");
 
 	vi = vif_get_max_tbt_speed();
 	switch (vi) {
@@ -3304,8 +3209,7 @@ static void init_vif_component_usb4_port_fields(struct vif_field_t *vif_fields)
 	}
 
 	set_vif_field_itss(&vif_fields[USB4_Max_Speed],
-			   vif_component_name[USB4_Max_Speed],
-			   vi, vs);
+			   vif_component_name[USB4_Max_Speed], vi, vs);
 
 	set_vif_field_b(&vif_fields[USB4_TBT3_Compatibility_Supported],
 			vif_component_name[USB4_TBT3_Compatibility_Supported],
@@ -3330,8 +3234,8 @@ static void init_vif_component_usb4_port_fields(struct vif_field_t *vif_fields)
  *	Device_Gen1x1_tLinkTurnaround		numericFieldType
  *	Device_Gen2x1_tLinkTurnaround		numericFieldType
  */
-static void init_vif_component_usb_data_ufp_fields(
-			struct vif_field_t *vif_fields)
+static void
+init_vif_component_usb_data_ufp_fields(struct vif_field_t *vif_fields)
 {
 	/*
 	 * TOTO(b:172441959) Adjust the speed based on CONFIG_
@@ -3351,37 +3255,36 @@ static void init_vif_component_usb_data_ufp_fields(
 		return;
 
 	supports_usb_data = does_support_device_usb_data();
-	set_vif_field_b(
-		&vif_fields[Device_Supports_USB_Data],
-		vif_component_name[Device_Supports_USB_Data],
-		supports_usb_data);
+	set_vif_field_b(&vif_fields[Device_Supports_USB_Data],
+			vif_component_name[Device_Supports_USB_Data],
+			supports_usb_data);
 
 	if (supports_usb_data) {
 		switch (ds) {
 		case USB_2:
 			set_vif_field_itss(&vif_fields[Device_Speed],
-				vif_component_name[Device_Speed],
-				USB_2, "USB 2");
+					   vif_component_name[Device_Speed],
+					   USB_2, "USB 2");
 			break;
 		case USB_GEN11:
 			set_vif_field_itss(&vif_fields[Device_Speed],
-				vif_component_name[Device_Speed],
-				USB_GEN11, "USB 3.2 Gen 1x1");
+					   vif_component_name[Device_Speed],
+					   USB_GEN11, "USB 3.2 Gen 1x1");
 			break;
 		case USB_GEN21:
 			set_vif_field_itss(&vif_fields[Device_Speed],
-				vif_component_name[Device_Speed],
-				USB_GEN21, "USB 3.2 Gen 2x1");
+					   vif_component_name[Device_Speed],
+					   USB_GEN21, "USB 3.2 Gen 2x1");
 			break;
 		case USB_GEN12:
 			set_vif_field_itss(&vif_fields[Device_Speed],
-				vif_component_name[Device_Speed],
-				USB_GEN12, "USB 3.2 Gen 1x2");
+					   vif_component_name[Device_Speed],
+					   USB_GEN12, "USB 3.2 Gen 1x2");
 			break;
 		case USB_GEN22:
 			set_vif_field_itss(&vif_fields[Device_Speed],
-				vif_component_name[Device_Speed],
-				USB_GEN22, "USB 3.2 Gen 2x2");
+					   vif_component_name[Device_Speed],
+					   USB_GEN22, "USB 3.2 Gen 2x2");
 			break;
 		}
 	}
@@ -3402,8 +3305,8 @@ static void init_vif_component_usb_data_ufp_fields(
  *	Host_Gen2x1_tLinkTurnaround		numericFieldType
  *	Host_Suspend_Supported			booleanFieldType
  */
-static void init_vif_component_usb_data_dfp_fields(
-			struct vif_field_t *vif_fields)
+static void
+init_vif_component_usb_data_dfp_fields(struct vif_field_t *vif_fields)
 {
 	/*
 	 * TOTO(b:172438944) Adjust the speed based on CONFIG_
@@ -3426,65 +3329,63 @@ static void init_vif_component_usb_data_dfp_fields(
 
 	supports_usb_data = does_support_host_usb_data();
 	set_vif_field_b(&vif_fields[Host_Supports_USB_Data],
-		vif_component_name[Host_Supports_USB_Data],
-		supports_usb_data);
+			vif_component_name[Host_Supports_USB_Data],
+			supports_usb_data);
 
 	if (supports_usb_data) {
 		switch (ds) {
 		case USB_2:
 			set_vif_field_itss(&vif_fields[Host_Speed],
-				vif_component_name[Host_Speed],
-				USB_2, "USB 2");
+					   vif_component_name[Host_Speed],
+					   USB_2, "USB 2");
 			break;
 		case USB_GEN11:
 			set_vif_field_itss(&vif_fields[Host_Speed],
-				vif_component_name[Host_Speed],
-				USB_GEN11, "USB 3.2 Gen 1x1");
+					   vif_component_name[Host_Speed],
+					   USB_GEN11, "USB 3.2 Gen 1x1");
 			break;
 		case USB_GEN21:
 			set_vif_field_itss(&vif_fields[Host_Speed],
-				vif_component_name[Host_Speed],
-				USB_GEN21, "USB 3.2 Gen 2x1");
+					   vif_component_name[Host_Speed],
+					   USB_GEN21, "USB 3.2 Gen 2x1");
 			break;
 		case USB_GEN12:
 			set_vif_field_itss(&vif_fields[Host_Speed],
-				vif_component_name[Host_Speed],
-				USB_GEN12, "USB 3.2 Gen 1x2");
+					   vif_component_name[Host_Speed],
+					   USB_GEN12, "USB 3.2 Gen 1x2");
 			break;
 		case USB_GEN22:
 			set_vif_field_itss(&vif_fields[Host_Speed],
-				vif_component_name[Host_Speed],
-				USB_GEN22, "USB 3.2 Gen 2x2");
+					   vif_component_name[Host_Speed],
+					   USB_GEN22, "USB 3.2 Gen 2x2");
 			break;
 		}
 
-		if (!get_vif_field_tag_bool(
-				&vif_fields[Type_C_Port_On_Hub],
-				&is_dfp_on_hub))
+		if (!get_vif_field_tag_bool(&vif_fields[Type_C_Port_On_Hub],
+					    &is_dfp_on_hub))
 			is_dfp_on_hub = false;
 
 		set_vif_field_b(&vif_fields[Is_DFP_On_Hub],
-			vif_component_name[Is_DFP_On_Hub],
-			is_dfp_on_hub);
+				vif_component_name[Is_DFP_On_Hub],
+				is_dfp_on_hub);
 
-		set_vif_field_b(&vif_fields[Host_Contains_Captive_Retimer],
+		set_vif_field_b(
+			&vif_fields[Host_Contains_Captive_Retimer],
 			vif_component_name[Host_Contains_Captive_Retimer],
 			false);
 
 		set_vif_field_b(&vif_fields[Host_Is_Embedded],
-			vif_component_name[Host_Is_Embedded],
-			false);
+				vif_component_name[Host_Is_Embedded], false);
 	}
 }
 
 /*********************************************************************
  * Init VIF/Component[] PD Source Fields
  */
-static int init_vif_component_pd_source_fields(
-			struct vif_field_t *vif_fields,
-			struct vif_srcPdoList_t *comp_src_pdo_list,
-			int32_t *src_max_power,
-			enum dtype type)
+static int
+init_vif_component_pd_source_fields(struct vif_field_t *vif_fields,
+				    struct vif_srcPdoList_t *comp_src_pdo_list,
+				    int32_t *src_max_power, enum dtype type)
 {
 	if (type == DRP || type == SRC) {
 		int i;
@@ -3511,78 +3412,78 @@ static int init_vif_component_pd_source_fields(
 
 		sprintf(str, "%d mW", *src_max_power);
 		set_vif_field_itss(&vif_fields[PD_Power_As_Source],
-			vif_component_name[PD_Power_As_Source],
-			*src_max_power, str);
+				   vif_component_name[PD_Power_As_Source],
+				   *src_max_power, str);
 	}
 
 	if (type == DRP || type == SRC)
 		set_vif_field_b(&vif_fields[USB_Suspend_May_Be_Cleared],
-			vif_component_name[USB_Suspend_May_Be_Cleared],
-			false);
+				vif_component_name[USB_Suspend_May_Be_Cleared],
+				false);
 
 	if (type == DRP || type == SRC)
 		set_vif_field_b(&vif_fields[Sends_Pings],
-			vif_component_name[Sends_Pings],
-			false);
+				vif_component_name[Sends_Pings], false);
 
-	if (IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE) &&
-	    type == DRP &&
+	if (IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE) && type == DRP &&
 	    IS_ENABLED(CONFIG_USB_PD_FRS))
-		set_vif_field(&vif_fields[
-			FR_Swap_Type_C_Current_Capability_As_Initial_Sink],
+		set_vif_field(
+			&vif_fields
+				[FR_Swap_Type_C_Current_Capability_As_Initial_Sink],
 			vif_component_name
-			[FR_Swap_Type_C_Current_Capability_As_Initial_Sink],
+				[FR_Swap_Type_C_Current_Capability_As_Initial_Sink],
 			"3", "3A @ 5V");
 	else
-		set_vif_field(&vif_fields[
-			FR_Swap_Type_C_Current_Capability_As_Initial_Sink],
+		set_vif_field(
+			&vif_fields
+				[FR_Swap_Type_C_Current_Capability_As_Initial_Sink],
 			vif_component_name
-			[FR_Swap_Type_C_Current_Capability_As_Initial_Sink],
+				[FR_Swap_Type_C_Current_Capability_As_Initial_Sink],
 			"0", "FR_Swap not supported");
 
 	if (IS_ENABLED(CONFIG_USB_PD_REV30) || IS_ENABLED(CONFIG_USB_PRL_SM))
 		set_vif_field_b(&vif_fields[Master_Port],
-				vif_component_name[Master_Port],
-				false);
+				vif_component_name[Master_Port], false);
 
 	if (type == DRP || type == SRC)
 		set_vif_field_itss(&vif_fields[Num_Src_PDOs],
-			vif_component_name[Num_Src_PDOs],
-			src_pdo_cnt, NULL);
+				   vif_component_name[Num_Src_PDOs],
+				   src_pdo_cnt, NULL);
 
 	if (type == DRP || type == SRC) {
 		if (IS_ENABLED(CONFIG_USBC_OCP)) {
 			int resp = 0;
 
 			set_vif_field_b(&vif_fields[PD_OC_Protection],
-				vif_component_name[PD_OC_Protection],
-				true);
+					vif_component_name[PD_OC_Protection],
+					true);
 
 			switch (resp) {
 			case 0:
 				set_vif_field(&vif_fields[PD_OCP_Method],
-					vif_component_name[PD_OCP_Method],
-					"0", "Over-Current Response");
+					      vif_component_name[PD_OCP_Method],
+					      "0", "Over-Current Response");
 				break;
 			case 1:
 				set_vif_field(&vif_fields[PD_OCP_Method],
-					vif_component_name[PD_OCP_Method],
-					"1", "Under-Voltage Response");
+					      vif_component_name[PD_OCP_Method],
+					      "1", "Under-Voltage Response");
 				break;
 			case 2:
 				set_vif_field(&vif_fields[PD_OCP_Method],
-					vif_component_name[PD_OCP_Method],
-					"2", "Both");
+					      vif_component_name[PD_OCP_Method],
+					      "2", "Both");
 				break;
 			default:
-				set_vif_field_itss(&vif_fields[PD_OCP_Method],
-					vif_component_name[PD_OCP_Method],
-					resp, NULL);
+				set_vif_field_itss(
+					&vif_fields[PD_OCP_Method],
+					vif_component_name[PD_OCP_Method], resp,
+					NULL);
 			}
 		} else {
 			set_vif_field_b(&vif_fields[PD_OC_Protection],
-				vif_component_name[PD_OC_Protection],
-				false);
+					vif_component_name[PD_OC_Protection],
+					false);
 		}
 	}
 
@@ -3592,10 +3493,10 @@ static int init_vif_component_pd_source_fields(
 /*********************************************************************
  * Init VIF/Component[] PD Sink Fields
  */
-static int init_vif_component_pd_sink_fields(
-			struct vif_field_t *vif_fields,
-			struct vif_snkPdoList_t *comp_snk_pdo_list,
-			enum dtype type)
+static int
+init_vif_component_pd_sink_fields(struct vif_field_t *vif_fields,
+				  struct vif_snkPdoList_t *comp_snk_pdo_list,
+				  enum dtype type)
 {
 	int i;
 	int32_t snk_max_power = 0;
@@ -3607,15 +3508,13 @@ static int init_vif_component_pd_sink_fields(
 	set_vif_field_c(&vif_fields[PD_Sink_Header], "PD Sink");
 
 	set_vif_field_b(&vif_fields[EPR_Supported_As_Snk],
-			vif_component_name[EPR_Supported_As_Snk],
-			false);
+			vif_component_name[EPR_Supported_As_Snk], false);
 
 	/* Sink PDOs */
 	for (i = 0; i < pd_snk_pdo_cnt; i++) {
 		int32_t pwr;
 
-		pwr = init_vif_snk_pdo(&comp_snk_pdo_list[i],
-				       pd_snk_pdo[i]);
+		pwr = init_vif_snk_pdo(&comp_snk_pdo_list[i], pd_snk_pdo[i]);
 		if (pwr < 0) {
 			fprintf(stderr, "ERROR: Setting SNK PDO.\n");
 			return 1;
@@ -3627,30 +3526,27 @@ static int init_vif_component_pd_sink_fields(
 
 	sprintf(str, "%d mW", snk_max_power);
 	set_vif_field_itss(&vif_fields[PD_Power_As_Sink],
-		vif_component_name[PD_Power_As_Sink],
-		snk_max_power, str);
+			   vif_component_name[PD_Power_As_Sink], snk_max_power,
+			   str);
 
 	set_vif_field_b(&vif_fields[No_USB_Suspend_May_Be_Set],
-		vif_component_name[No_USB_Suspend_May_Be_Set],
-		true);
+			vif_component_name[No_USB_Suspend_May_Be_Set], true);
 
 	set_vif_field_b(&vif_fields[GiveBack_May_Be_Set],
-		vif_component_name[GiveBack_May_Be_Set],
-		IS_ENABLED(CONFIG_USB_PD_GIVE_BACK));
+			vif_component_name[GiveBack_May_Be_Set],
+			IS_ENABLED(CONFIG_USB_PD_GIVE_BACK));
 
 	set_vif_field_b(&vif_fields[Higher_Capability_Set],
-		vif_component_name[Higher_Capability_Set],
-		false);
+			vif_component_name[Higher_Capability_Set], false);
 
-	set_vif_field(&vif_fields[
-		FR_Swap_Reqd_Type_C_Current_As_Initial_Source],
-		vif_component_name
-			[FR_Swap_Reqd_Type_C_Current_As_Initial_Source],
+	set_vif_field(
+		&vif_fields[FR_Swap_Reqd_Type_C_Current_As_Initial_Source],
+		vif_component_name[FR_Swap_Reqd_Type_C_Current_As_Initial_Source],
 		"0", "FR_Swap not supported");
 
 	set_vif_field_itss(&vif_fields[Num_Snk_PDOs],
-		vif_component_name[Num_Snk_PDOs],
-		pd_snk_pdo_cnt, NULL);
+			   vif_component_name[Num_Snk_PDOs], pd_snk_pdo_cnt,
+			   NULL);
 
 	return 0;
 }
@@ -3658,32 +3554,28 @@ static int init_vif_component_pd_sink_fields(
 /*********************************************************************
  * Init VIF/Component[] PD Dual Role Fields
  */
-static void init_vif_component_pd_dual_role_fields(
-			struct vif_field_t *vif_fields,
-			enum dtype type)
+static void
+init_vif_component_pd_dual_role_fields(struct vif_field_t *vif_fields,
+				       enum dtype type)
 {
 	if (!IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE) || type != DRP)
 		return;
 
 	set_vif_field_b(&vif_fields[Accepts_PR_Swap_As_Src],
-		vif_component_name[Accepts_PR_Swap_As_Src],
-		true);
+			vif_component_name[Accepts_PR_Swap_As_Src], true);
 
 	set_vif_field_b(&vif_fields[Accepts_PR_Swap_As_Snk],
-		vif_component_name[Accepts_PR_Swap_As_Snk],
-		true);
+			vif_component_name[Accepts_PR_Swap_As_Snk], true);
 
 	set_vif_field_b(&vif_fields[Requests_PR_Swap_As_Src],
-		vif_component_name[Requests_PR_Swap_As_Src],
-		true);
+			vif_component_name[Requests_PR_Swap_As_Src], true);
 
 	set_vif_field_b(&vif_fields[Requests_PR_Swap_As_Snk],
-		vif_component_name[Requests_PR_Swap_As_Snk],
-		true);
+			vif_component_name[Requests_PR_Swap_As_Snk], true);
 
 	set_vif_field_b(&vif_fields[FR_Swap_Supported_As_Initial_Sink],
-		vif_component_name[FR_Swap_Supported_As_Initial_Sink],
-		IS_ENABLED(CONFIG_USB_PD_FRS));
+			vif_component_name[FR_Swap_Supported_As_Initial_Sink],
+			IS_ENABLED(CONFIG_USB_PD_FRS));
 }
 
 /*********************************************************************
@@ -3702,8 +3594,8 @@ static void init_vif_component_pd_dual_role_fields(
  *	Num_SVIDs_Max_SOP			numericFieldType
  *	SVID_Fixed_SOP				booleanFieldType
  */
-static void init_vif_component_sop_discovery_fields(
-			struct vif_field_t *vif_fields)
+static void
+init_vif_component_sop_discovery_fields(struct vif_field_t *vif_fields)
 {
 	char hex_str[10];
 
@@ -3716,77 +3608,69 @@ static void init_vif_component_sop_discovery_fields(
 	    !does_respond_to_discov_sop_dfp())
 		return;
 
-	set_vif_field(&vif_fields[XID_SOP],
-		vif_component_name[XID_SOP],
-		"0",
-		NULL);
+	set_vif_field(&vif_fields[XID_SOP], vif_component_name[XID_SOP], "0",
+		      NULL);
 
 	set_vif_field_b(&vif_fields[Data_Capable_As_USB_Host_SOP],
-		vif_component_name[Data_Capable_As_USB_Host_SOP],
-		can_act_as_host());
+			vif_component_name[Data_Capable_As_USB_Host_SOP],
+			can_act_as_host());
 
 	set_vif_field_b(&vif_fields[Data_Capable_As_USB_Device_SOP],
-		vif_component_name[Data_Capable_As_USB_Device_SOP],
-		can_act_as_device());
+			vif_component_name[Data_Capable_As_USB_Device_SOP],
+			can_act_as_device());
 
 	if (does_respond_to_discov_sop_dfp() &&
 	    IS_ENABLED(CONFIG_USB_PD_REV30)) {
 #if defined(CONFIG_USB_PD_PORT_LABEL)
 		set_vif_field_stis(&vif_fields[DFP_VDO_Port_Number],
-			vif_component_name[DFP_VDO_Port_Number],
-			NULL,
-			CONFIG_USB_PD_PORT_LABEL);
+				   vif_component_name[DFP_VDO_Port_Number],
+				   NULL, CONFIG_USB_PD_PORT_LABEL);
 #else
 		set_vif_field_itss(&vif_fields[DFP_VDO_Port_Number],
-			vif_component_name[DFP_VDO_Port_Number],
-			component_index,
-			NULL);
+				   vif_component_name[DFP_VDO_Port_Number],
+				   component_index, NULL);
 #endif
 	}
 
 	sprintf(hex_str, "%04X", USB_VID_GOOGLE);
 	set_vif_field_itss(&vif_fields[USB_VID_SOP],
-		vif_component_name[USB_VID_SOP],
-		USB_VID_GOOGLE, hex_str);
+			   vif_component_name[USB_VID_SOP], USB_VID_GOOGLE,
+			   hex_str);
 
-	#if defined(CONFIG_USB_PID)
-		sprintf(hex_str, "%04X", CONFIG_USB_PID);
-		set_vif_field_itss(&vif_fields[PID_SOP],
-			vif_component_name[PID_SOP],
-			CONFIG_USB_PID, hex_str);
-	#else
-		sprintf(hex_str, "%04X", DEFAULT_MISSING_PID);
-		set_vif_field_itss(&vif_fields[PID_SOP],
-			vif_component_name[PID_SOP],
-			DEFAULT_MISSING_PID, hex_str);
-	#endif
+#if defined(CONFIG_USB_PID)
+	sprintf(hex_str, "%04X", CONFIG_USB_PID);
+	set_vif_field_itss(&vif_fields[PID_SOP], vif_component_name[PID_SOP],
+			   CONFIG_USB_PID, hex_str);
+#else
+	sprintf(hex_str, "%04X", DEFAULT_MISSING_PID);
+	set_vif_field_itss(&vif_fields[PID_SOP], vif_component_name[PID_SOP],
+			   DEFAULT_MISSING_PID, hex_str);
+#endif
 
-	#if defined(CONFIG_USB_BCD_DEV)
-		sprintf(hex_str, "%04X", CONFIG_USB_BCD_DEV);
-		set_vif_field_itss(&vif_fields[bcdDevice_SOP],
-			vif_component_name[bcdDevice_SOP],
-			CONFIG_USB_BCD_DEV, hex_str);
-	#else
-		sprintf(hex_str, "%04X", DEFAULT_MISSING_BCD_DEV);
-		set_vif_field_itss(&vif_fields[bcdDevice_SOP],
-			vif_component_name[bcdDevice_SOP],
-			DEFAULT_MISSING_BCD_DEV, hex_str);
-	#endif
+#if defined(CONFIG_USB_BCD_DEV)
+	sprintf(hex_str, "%04X", CONFIG_USB_BCD_DEV);
+	set_vif_field_itss(&vif_fields[bcdDevice_SOP],
+			   vif_component_name[bcdDevice_SOP],
+			   CONFIG_USB_BCD_DEV, hex_str);
+#else
+	sprintf(hex_str, "%04X", DEFAULT_MISSING_BCD_DEV);
+	set_vif_field_itss(&vif_fields[bcdDevice_SOP],
+			   vif_component_name[bcdDevice_SOP],
+			   DEFAULT_MISSING_BCD_DEV, hex_str);
+#endif
 }
 
 /*********************************************************************
  * Init VIF/Component[] Battery Charging 1.2 Fields
  */
-static void init_vif_component_bc_1_2_fields(
-			struct vif_field_t *vif_fields,
-			enum bc_1_2_support bc_support)
+static void init_vif_component_bc_1_2_fields(struct vif_field_t *vif_fields,
+					     enum bc_1_2_support bc_support)
 {
 	if (bc_support == BC_1_2_SUPPORT_CHARGING_PORT ||
 	    bc_support == BC_1_2_SUPPORT_BOTH)
 		set_vif_field(&vif_fields[BC_1_2_Charging_Port_Type],
-			vif_component_name[BC_1_2_Charging_Port_Type],
-			"1",
-			"CDP");
+			      vif_component_name[BC_1_2_Charging_Port_Type],
+			      "1", "CDP");
 }
 
 /*********************************************************************
@@ -3801,24 +3685,24 @@ static void init_vif_component_bc_1_2_fields(
  *	Port_Source_Power_Gang			nonEmptyString
  *	Port_Source_Power_Gang_Max_Power	numericFieldType
  */
-static void init_vif_component_product_power_fields(
-			struct vif_field_t *vif_fields,
-			int32_t src_max_power,
-			enum dtype type)
+static void
+init_vif_component_product_power_fields(struct vif_field_t *vif_fields,
+					int32_t src_max_power, enum dtype type)
 {
 	if (type == DRP || type == SRC) {
 		char str[14];
 
 		sprintf(str, "%d mW", src_max_power);
-		set_vif_field_itss(&vif_fields[Product_Total_Source_Power_mW],
+		set_vif_field_itss(
+			&vif_fields[Product_Total_Source_Power_mW],
 			vif_component_name[Product_Total_Source_Power_mW],
 			src_max_power, str);
 	}
 
 	if (type == DRP || type == SRC)
 		set_vif_field(&vif_fields[Port_Source_Power_Type],
-			vif_component_name[Port_Source_Power_Type],
-			"0", "Assured");
+			      vif_component_name[Port_Source_Power_Type], "0",
+			      "Assured");
 }
 
 static void init_remarks(struct vif_t *vif)
@@ -3852,24 +3736,18 @@ static void init_remarks(struct vif_t *vif)
 		set_vif_field_c(&vif_fields[SOP_Discover_ID_Header],
 				"SOP Discover ID");
 	}
-
 }
 
-static int gen_vif(const char *board,
-		   struct vif_t *vif)
+static int gen_vif(const char *board, struct vif_t *vif)
 {
 	int max_component_index = board_get_usb_pd_port_count();
 
 	/*********************************************************************
 	 * Initialize the vif structure
 	 */
-	init_vif_fields(
-			vif->vif_field,
-			vif->vif_app_field,
-			board);
+	init_vif_fields(vif->vif_field, vif->vif_app_field, board);
 
-	for (component_index = 0;
-	     component_index < max_component_index;
+	for (component_index = 0; component_index < max_component_index;
 	     component_index++) {
 		int override_value;
 		bool was_overridden;
@@ -3878,11 +3756,10 @@ static int gen_vif(const char *board,
 		enum bc_1_2_support bc_support = BC_1_2_SUPPORT_NONE;
 
 		/* Determine if we are DRP, SRC or SNK */
-		was_overridden =
-			get_vif_field_tag_number(
-				&vif->Component[component_index]
-					.vif_field[Type_C_State_Machine],
-				&override_value);
+		was_overridden = get_vif_field_tag_number(
+			&vif->Component[component_index]
+				 .vif_field[Type_C_State_Machine],
+			&override_value);
 		if (was_overridden) {
 			switch (override_value) {
 			case SRC:
@@ -3895,20 +3772,19 @@ static int gen_vif(const char *board,
 			}
 		}
 		if (!was_overridden) {
-			was_overridden =
-				get_vif_field_tag_number(
-					&vif->Component[component_index]
-						.vif_field[PD_Port_Type],
-					&override_value);
+			was_overridden = get_vif_field_tag_number(
+				&vif->Component[component_index]
+					 .vif_field[PD_Port_Type],
+				&override_value);
 			if (was_overridden) {
 				switch (override_value) {
-				case PORT_CONSUMER_ONLY:	/* SNK */
+				case PORT_CONSUMER_ONLY: /* SNK */
 					type = SNK;
 					break;
-				case PORT_PROVIDER_ONLY:	/* SRC */
+				case PORT_PROVIDER_ONLY: /* SRC */
 					type = SRC;
 					break;
-				case PORT_DRP:			/* DRP */
+				case PORT_DRP: /* DRP */
 					type = DRP;
 					break;
 				default:
@@ -3933,60 +3809,51 @@ static int gen_vif(const char *board,
 				return 1;
 		}
 
-
 		init_vif_component_fields(
-				vif->Component[component_index].vif_field,
-				&bc_support,
-				type);
+			vif->Component[component_index].vif_field, &bc_support,
+			type);
 
 		init_vif_component_general_pd_fields(
-				vif->Component[component_index].vif_field,
-				type);
+			vif->Component[component_index].vif_field, type);
 
 		init_vif_component_sop_capabilities_fields(
-				vif->Component[component_index].vif_field);
+			vif->Component[component_index].vif_field);
 
 		init_vif_component_usb_type_c_fields(
-				vif->Component[component_index].vif_field,
-				type);
+			vif->Component[component_index].vif_field, type);
 
 		init_vif_component_usb4_port_fields(
 			vif->Component[component_index].vif_field);
 
 		init_vif_component_usb_data_ufp_fields(
-				vif->Component[component_index].vif_field);
+			vif->Component[component_index].vif_field);
 
 		init_vif_component_usb_data_dfp_fields(
-				vif->Component[component_index].vif_field);
+			vif->Component[component_index].vif_field);
 
 		if (init_vif_component_pd_source_fields(
-				vif->Component[component_index].vif_field,
-				vif->Component[component_index].SrcPdoList,
-				&src_max_power,
-				type))
+			    vif->Component[component_index].vif_field,
+			    vif->Component[component_index].SrcPdoList,
+			    &src_max_power, type))
 			return 1;
 
 		if (init_vif_component_pd_sink_fields(
-				vif->Component[component_index].vif_field,
-				vif->Component[component_index].SnkPdoList,
-				type))
+			    vif->Component[component_index].vif_field,
+			    vif->Component[component_index].SnkPdoList, type))
 			return 1;
 
 		init_vif_component_pd_dual_role_fields(
-				vif->Component[component_index].vif_field,
-				type);
+			vif->Component[component_index].vif_field, type);
 
 		init_vif_component_sop_discovery_fields(
-				vif->Component[component_index].vif_field);
+			vif->Component[component_index].vif_field);
 
 		init_vif_component_bc_1_2_fields(
-				vif->Component[component_index].vif_field,
-				bc_support);
+			vif->Component[component_index].vif_field, bc_support);
 
 		init_vif_component_product_power_fields(
-				vif->Component[component_index].vif_field,
-				src_max_power,
-				type);
+			vif->Component[component_index].vif_field,
+			src_max_power, type);
 	}
 
 	return 0;
@@ -4005,14 +3872,11 @@ int main(int argc, char **argv)
 	DIR *vifdir;
 	char *name;
 	int name_size;
-	const char * const short_opt = "hb:o:nv:";
+	const char *const short_opt = "hb:o:nv:";
 	const struct option long_opts[] = {
-		{ "help",      0, NULL, 'h' },
-		{ "board",     1, NULL, 'b' },
-		{ "out",       1, NULL, 'o' },
-		{ "no-config", 0, NULL, 'n' },
-		{ "over",      1, NULL, 'v' },
-		{ NULL }
+		{ "help", 0, NULL, 'h' }, { "board", 1, NULL, 'b' },
+		{ "out", 1, NULL, 'o' },  { "no-config", 0, NULL, 'n' },
+		{ "over", 1, NULL, 'v' }, { NULL }
 	};
 
 	/* Clear the VIF structure */
diff --git a/util/genvif.h b/util/genvif.h
index b9b5ed77bd..448d8bfb43 100644
--- a/util/genvif.h
+++ b/util/genvif.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,399 +24,399 @@ struct vif_field_t {
 /* 3.2.15.2 Cable SVID Modes */
 
 enum vif_cableSVIDModeList_indexes {
-	SVID_Mode_Enter,			/* booleanFieldType */
-	SVID_Mode_Recog_Mask,			/* numericFieldType */
-	SVID_Mode_Recog_Value,			/* numericFieldType */
+	SVID_Mode_Enter, /* booleanFieldType */
+	SVID_Mode_Recog_Mask, /* numericFieldType */
+	SVID_Mode_Recog_Value, /* numericFieldType */
 	CableSVID_Mode_Indexes
 };
 
 struct vif_cableSVIDModeList_t {
-	struct vif_field_t		vif_field[CableSVID_Mode_Indexes];
+	struct vif_field_t vif_field[CableSVID_Mode_Indexes];
 };
 
 /* 3.2.15.1 Cable SVIDs */
 
 enum vif_cableSVIDList_indexes {
-	SVID,					/* numericFieldType */
-	SVID_Num_Modes_Min,			/* numericFieldType */
-	SVID_Num_Modes_Max,			/* numericFieldType */
-	SVID_Modes_Fixed,			/* booleanFieldType */
+	SVID, /* numericFieldType */
+	SVID_Num_Modes_Min, /* numericFieldType */
+	SVID_Num_Modes_Max, /* numericFieldType */
+	SVID_Modes_Fixed, /* booleanFieldType */
 	CableSVID_Indexes
 };
 
 struct vif_cableSVIDList_t {
-	struct vif_field_t		vif_field[CableSVID_Indexes];
+	struct vif_field_t vif_field[CableSVID_Indexes];
 
 	struct vif_cableSVIDModeList_t
-			CableSVIDModeList[MAX_NUM_CABLE_SVID_MODES];
+		CableSVIDModeList[MAX_NUM_CABLE_SVID_MODES];
 };
 
 /* 3.2.12.2 SOP SVID Modes */
 
 enum vif_sopSVIDModeList_indexes {
-	SVID_Mode_Enter_SOP,			/* booleanFieldType */
-	SVID_Mode_Recog_Mask_SOP,		/* numericFieldType */
-	SVID_Mode_Recog_Value_SOP,		/* numericFieldType */
+	SVID_Mode_Enter_SOP, /* booleanFieldType */
+	SVID_Mode_Recog_Mask_SOP, /* numericFieldType */
+	SVID_Mode_Recog_Value_SOP, /* numericFieldType */
 	SopSVID_Mode_Indexes
 };
 
 struct vif_sopSVIDModeList_t {
-	struct vif_field_t		vif_field[SopSVID_Mode_Indexes];
+	struct vif_field_t vif_field[SopSVID_Mode_Indexes];
 };
 
 /* 3.2.12.1 SOP SVIDs */
 
 enum vif_sopSVIDList_indexes {
-	SVID_SOP,				/* numericFieldType */
-	SVID_Num_Modes_Min_SOP,			/* numericFieldType */
-	SVID_Num_Modes_Max_SOP,			/* numericFieldType */
-	SVID_Modes_Fixed_SOP,			/* booleanFieldType */
+	SVID_SOP, /* numericFieldType */
+	SVID_Num_Modes_Min_SOP, /* numericFieldType */
+	SVID_Num_Modes_Max_SOP, /* numericFieldType */
+	SVID_Modes_Fixed_SOP, /* booleanFieldType */
 	SopSVID_Indexes
 };
 
 struct vif_sopSVIDList_t {
-	struct vif_field_t		vif_field[SopSVID_Indexes];
+	struct vif_field_t vif_field[SopSVID_Indexes];
 
-	struct vif_sopSVIDModeList_t
-			SOPSVIDModeList[MAX_NUM_SOP_SVID_MODES];
+	struct vif_sopSVIDModeList_t SOPSVIDModeList[MAX_NUM_SOP_SVID_MODES];
 };
 
 /* 3.2.10.1 Sink PDOs */
 
 enum vif_snkPdoList_indexes {
-	Snk_PDO_Supply_Type,			/* numericFieldType */
-	Snk_PDO_APDO_Type,			/* numericFieldType */
-	Snk_PDO_Voltage,			/* numericFieldType */
-	Snk_PDO_PDP_Rating,			/* numericFieldType */
-	Snk_PDO_Op_Power,			/* numericFieldType */
-	Snk_PDO_Min_Voltage,			/* numericFieldType */
-	Snk_PDO_Max_Voltage,			/* numericFieldType */
-	Snk_PDO_Op_Current,			/* numericFieldType */
+	Snk_PDO_Supply_Type, /* numericFieldType */
+	Snk_PDO_APDO_Type, /* numericFieldType */
+	Snk_PDO_Voltage, /* numericFieldType */
+	Snk_PDO_PDP_Rating, /* numericFieldType */
+	Snk_PDO_Op_Power, /* numericFieldType */
+	Snk_PDO_Min_Voltage, /* numericFieldType */
+	Snk_PDO_Max_Voltage, /* numericFieldType */
+	Snk_PDO_Op_Current, /* numericFieldType */
 	Snk_PDO_Indexes
 };
 
 struct vif_snkPdoList_t {
-	struct vif_field_t		vif_field[Snk_PDO_Indexes];
+	struct vif_field_t vif_field[Snk_PDO_Indexes];
 };
 
 /* 3.2.9.1 Source PDOs */
 
 enum vif_srcPdoList_indexes {
-	Src_PDO_Supply_Type,			/* numericFieldType */
-	Src_PDO_APDO_Type,			/* numericFieldType */
-	Src_PDO_Peak_Current,			/* numericFieldType */
-	Src_PDO_Voltage,			/* numericFieldType */
-	Src_PDO_Max_Current,			/* numericFieldType */
-	Src_PDO_Min_Voltage,			/* numericFieldType */
-	Src_PDO_Max_Voltage,			/* numericFieldType */
-	Src_PDO_Max_Power,			/* numericFieldType */
-	Src_PD_OCP_OC_Debounce,			/* numericFieldType */
-	Src_PD_OCP_OC_Threshold,		/* numericFieldType */
-	Src_PD_OCP_UV_Debounce,			/* numericFieldType */
-	Src_PD_OCP_UV_Threshold_Type,		/* numericFieldType */
-	Src_PD_OCP_UV_Threshold,		/* numericFieldType */
+	Src_PDO_Supply_Type, /* numericFieldType */
+	Src_PDO_APDO_Type, /* numericFieldType */
+	Src_PDO_Peak_Current, /* numericFieldType */
+	Src_PDO_Voltage, /* numericFieldType */
+	Src_PDO_Max_Current, /* numericFieldType */
+	Src_PDO_Min_Voltage, /* numericFieldType */
+	Src_PDO_Max_Voltage, /* numericFieldType */
+	Src_PDO_Max_Power, /* numericFieldType */
+	Src_PD_OCP_OC_Debounce, /* numericFieldType */
+	Src_PD_OCP_OC_Threshold, /* numericFieldType */
+	Src_PD_OCP_UV_Debounce, /* numericFieldType */
+	Src_PD_OCP_UV_Threshold_Type, /* numericFieldType */
+	Src_PD_OCP_UV_Threshold, /* numericFieldType */
 	Src_PDO_Indexes
 };
 
 struct vif_srcPdoList_t {
-	struct vif_field_t		vif_field[Src_PDO_Indexes];
+	struct vif_field_t vif_field[Src_PDO_Indexes];
 };
 
 /* 3.2.2.1.3 PCIe Endpoint Fields */
 
 enum vif_PCIeEndpointListType_indexes {
-	USB4_PCIe_Endpoint_Vendor_ID,		/* numericFieldType */
-	USB4_PCIe_Endpoint_Device_ID,		/* numericFieldType */
-	USB4_PCIe_Endpoint_Class_Code,		/* numericFieldType */
+	USB4_PCIe_Endpoint_Vendor_ID, /* numericFieldType */
+	USB4_PCIe_Endpoint_Device_ID, /* numericFieldType */
+	USB4_PCIe_Endpoint_Class_Code, /* numericFieldType */
 	PCIe_Endpoint_Indexes
 };
 
 struct vif_PCIeEndpointListType_t {
-	struct vif_field_t		vif_field[PCIe_Endpoint_Indexes];
+	struct vif_field_t vif_field[PCIe_Endpoint_Indexes];
 };
 
 /* 3.2.2.1.2 USB4 Router Fields */
 
 enum vif_Usb4RouterListType_indexes {
-	USB4_Router_ID,				/* numericFieldType */
-	USB4_Silicon_VID,			/* numericFieldType */
-	USB4_Num_Lane_Adapters,			/* numericFieldType */
-	USB4_Num_USB3_DN_Adapters,		/* numericFieldType */
-	USB4_Num_DP_IN_Adapters,		/* numericFieldType */
-	USB4_Num_DP_OUT_Adapters,		/* numericFieldType */
-	USB4_Num_PCIe_DN_Adapters,		/* numericFieldType */
-	USB4_TBT3_Not_Supported,		/* numericFieldType */
-	USB4_PCIe_Wake_Supported,		/* booleanFieldType */
-	USB4_USB3_Wake_Supported,		/* booleanFieldType */
-	USB4_Num_Unused_Adapters,		/* numericFieldType */
-	USB4_TBT3_VID,				/* numericFieldType */
-	USB4_PCIe_Switch_Vendor_ID,		/* numericFieldType */
-	USB4_PCIe_Switch_Device_ID,		/* numericFieldType */
-	USB4_Num_PCIe_Endpoints,		/* numericFieldType */
+	USB4_Router_ID, /* numericFieldType */
+	USB4_Silicon_VID, /* numericFieldType */
+	USB4_Num_Lane_Adapters, /* numericFieldType */
+	USB4_Num_USB3_DN_Adapters, /* numericFieldType */
+	USB4_Num_DP_IN_Adapters, /* numericFieldType */
+	USB4_Num_DP_OUT_Adapters, /* numericFieldType */
+	USB4_Num_PCIe_DN_Adapters, /* numericFieldType */
+	USB4_TBT3_Not_Supported, /* numericFieldType */
+	USB4_PCIe_Wake_Supported, /* booleanFieldType */
+	USB4_USB3_Wake_Supported, /* booleanFieldType */
+	USB4_Num_Unused_Adapters, /* numericFieldType */
+	USB4_TBT3_VID, /* numericFieldType */
+	USB4_PCIe_Switch_Vendor_ID, /* numericFieldType */
+	USB4_PCIe_Switch_Device_ID, /* numericFieldType */
+	USB4_Num_PCIe_Endpoints, /* numericFieldType */
 	USB4_Router_Indexes
 };
 
 struct vif_Usb4RouterListType_t {
-	struct vif_field_t		vif_field[USB4_Router_Indexes];
+	struct vif_field_t vif_field[USB4_Router_Indexes];
 
 	struct vif_PCIeEndpointListType_t
-			PCIeEndpointList[MAX_NUM_PCIE_ENDPOINTS];
+		PCIeEndpointList[MAX_NUM_PCIE_ENDPOINTS];
 };
 
 /* 3.2.3 Component Fields */
 
 enum vif_Component_indexes {
-	Component_Header,			/* comment */
-	Port_Label,				/* nonEmptyString */
-	Connector_Type,				/* numericFieldType */
-	USB4_Supported,				/* booleanFieldType */
-	USB4_Router_Index,			/* numericFieldType */
-	USB_PD_Support,				/* booleanFieldType */
-	PD_Port_Type,				/* numericFieldType */
-	Type_C_State_Machine,			/* numericFieldType */
-	Port_Battery_Powered,			/* booleanFieldType */
-	BC_1_2_Support,				/* numericFieldType */
-	Captive_Cable,				/* booleanFieldType */
-	Captive_Cable_Is_eMarked,		/* booleanFieldType */
+	Component_Header, /* comment */
+	Port_Label, /* nonEmptyString */
+	Connector_Type, /* numericFieldType */
+	USB4_Supported, /* booleanFieldType */
+	USB4_Router_Index, /* numericFieldType */
+	USB_PD_Support, /* booleanFieldType */
+	PD_Port_Type, /* numericFieldType */
+	Type_C_State_Machine, /* numericFieldType */
+	Port_Battery_Powered, /* booleanFieldType */
+	BC_1_2_Support, /* numericFieldType */
+	Captive_Cable, /* booleanFieldType */
+	Captive_Cable_Is_eMarked, /* booleanFieldType */
 
 	/* 3.2.4 General PD Fields */
-	General_PD_Header,			/* comment */
-	PD_Spec_Revision_Major,			/* numericFieldType */
-	PD_Spec_Revision_Minor,			/* numericFieldType */
-	PD_Spec_Version_Major,			/* numericFieldType */
-	PD_Spec_Version_Minor,			/* numericFieldType */
-	PD_Specification_Revision,		/* numericFieldType */
+	General_PD_Header, /* comment */
+	PD_Spec_Revision_Major, /* numericFieldType */
+	PD_Spec_Revision_Minor, /* numericFieldType */
+	PD_Spec_Version_Major, /* numericFieldType */
+	PD_Spec_Version_Minor, /* numericFieldType */
+	PD_Specification_Revision, /* numericFieldType */
 
 	/* 3.2.4.1 SOP* Capabilities */
-	SOP_Capable,				/* booleanFieldType */
-	SOP_P_Capable,				/* booleanFieldType */
-	SOP_PP_Capable,				/* booleanFieldType */
-	SOP_P_Debug_Capable,			/* booleanFieldType */
-	SOP_PP_Debug_Capable,			/* booleanFieldType */
-
-	Manufacturer_Info_Supported_Port,	/* booleanFieldType */
-	Manufacturer_Info_VID_Port,		/* numericFieldType */
-	Manufacturer_Info_PID_Port,		/* numericFieldType */
-	Chunking_Implemented_SOP,		/* booleanFieldType */
-	Unchunked_Extended_Messages_Supported,	/* booleanFieldType */
-	Security_Msgs_Supported_SOP,		/* booleanFieldType */
-	Unconstrained_Power,			/* booleanFieldType */
-	Num_Fixed_Batteries,			/* numericFieldType */
-	Num_Swappable_Battery_Slots,		/* numericFieldType */
-	ID_Header_Connector_Type_SOP,		/* numericFieldType */
+	SOP_Capable, /* booleanFieldType */
+	SOP_P_Capable, /* booleanFieldType */
+	SOP_PP_Capable, /* booleanFieldType */
+	SOP_P_Debug_Capable, /* booleanFieldType */
+	SOP_PP_Debug_Capable, /* booleanFieldType */
+
+	Manufacturer_Info_Supported_Port, /* booleanFieldType */
+	Manufacturer_Info_VID_Port, /* numericFieldType */
+	Manufacturer_Info_PID_Port, /* numericFieldType */
+	Chunking_Implemented_SOP, /* booleanFieldType */
+	Unchunked_Extended_Messages_Supported, /* booleanFieldType */
+	Security_Msgs_Supported_SOP, /* booleanFieldType */
+	Unconstrained_Power, /* booleanFieldType */
+	Num_Fixed_Batteries, /* numericFieldType */
+	Num_Swappable_Battery_Slots, /* numericFieldType */
+	ID_Header_Connector_Type_SOP, /* numericFieldType */
 
 	/* 3.2.4 General PD Fields */
-	PD_Capabilities_Header,			/* comment */
-	USB_Comms_Capable,			/* booleanFieldType */
-	DR_Swap_To_DFP_Supported,		/* booleanFieldType */
-	DR_Swap_To_UFP_Supported,		/* booleanFieldType */
-	VCONN_Swap_To_On_Supported,		/* booleanFieldType */
-	VCONN_Swap_To_Off_Supported,		/* booleanFieldType */
-	Responds_To_Discov_SOP_UFP,		/* booleanFieldType */
-	Responds_To_Discov_SOP_DFP,		/* booleanFieldType */
-	Attempts_Discov_SOP,			/* booleanFieldType */
-	Power_Interruption_Available,		/* numericFieldType */
-	Data_Reset_Supported,			/* booleanFieldType */
-	Enter_USB_Supported,			/* booleanFieldType */
+	PD_Capabilities_Header, /* comment */
+	USB_Comms_Capable, /* booleanFieldType */
+	DR_Swap_To_DFP_Supported, /* booleanFieldType */
+	DR_Swap_To_UFP_Supported, /* booleanFieldType */
+	VCONN_Swap_To_On_Supported, /* booleanFieldType */
+	VCONN_Swap_To_Off_Supported, /* booleanFieldType */
+	Responds_To_Discov_SOP_UFP, /* booleanFieldType */
+	Responds_To_Discov_SOP_DFP, /* booleanFieldType */
+	Attempts_Discov_SOP, /* booleanFieldType */
+	Power_Interruption_Available, /* numericFieldType */
+	Data_Reset_Supported, /* booleanFieldType */
+	Enter_USB_Supported, /* booleanFieldType */
 
 	/* 3.2.5 USB Type-C Fields */
-	USB_Type_C_Header,			/* comment */
-	Type_C_Can_Act_As_Host,			/* booleanFieldType */
-	Type_C_Can_Act_As_Device,		/* booleanFieldType */
+	USB_Type_C_Header, /* comment */
+	Type_C_Can_Act_As_Host, /* booleanFieldType */
+	Type_C_Can_Act_As_Device, /* booleanFieldType */
 
 	/* 3.2.5 USB Type-C Fields */
-	Type_C_Implements_Try_SRC,		/* booleanFieldType */
-	Type_C_Implements_Try_SNK,		/* booleanFieldType */
-	Type_C_Supports_Audio_Accessory,	/* booleanFieldType */
-	Type_C_Is_VCONN_Powered_Accessory,	/* booleanFieldType */
-	Type_C_Is_Debug_Target_SRC,		/* booleanFieldType */
-	Type_C_Is_Debug_Target_SNK,		/* booleanFieldType */
-	RP_Value,				/* numericFieldType */
-	Type_C_Supports_VCONN_Powered_Accessory,/* booleanFieldType */
-	Type_C_Port_On_Hub,			/* booleanFieldType */
-	Type_C_Power_Source,			/* numericFieldType */
-	Type_C_Sources_VCONN,			/* booleanFieldType */
-	Type_C_Is_Alt_Mode_Controller,		/* booleanFieldType */
-	Type_C_Is_Alt_Mode_Adapter,		/* booleanFieldType */
+	Type_C_Implements_Try_SRC, /* booleanFieldType */
+	Type_C_Implements_Try_SNK, /* booleanFieldType */
+	Type_C_Supports_Audio_Accessory, /* booleanFieldType */
+	Type_C_Is_VCONN_Powered_Accessory, /* booleanFieldType */
+	Type_C_Is_Debug_Target_SRC, /* booleanFieldType */
+	Type_C_Is_Debug_Target_SNK, /* booleanFieldType */
+	RP_Value, /* numericFieldType */
+	Type_C_Supports_VCONN_Powered_Accessory, /* booleanFieldType */
+	Type_C_Port_On_Hub, /* booleanFieldType */
+	Type_C_Power_Source, /* numericFieldType */
+	Type_C_Sources_VCONN, /* booleanFieldType */
+	Type_C_Is_Alt_Mode_Controller, /* booleanFieldType */
+	Type_C_Is_Alt_Mode_Adapter, /* booleanFieldType */
 
 	/* 3.2.6 USB4 Port Fields (missing from output) */
-	USB4_Port_Header,			/* comment */
-	USB4_Lane_0_Adapter,			/* numericFieldType */
-	USB4_Max_Speed,				/* numericFieldType */
-	USB4_DFP_Supported,			/* booleanFieldType */
-	USB4_UFP_Supported,			/* booleanFieldType */
-	USB4_USB3_Tunneling_Supported,		/* booleanFieldType */
-	USB4_DP_Tunneling_Supported,		/* booleanFieldType */
-	USB4_PCIe_Tunneling_Supported,		/* booleanFieldType */
-	USB4_TBT3_Compatibility_Supported,	/* booleanFieldType */
-	USB4_CL1_State_Supported,		/* booleanFieldType */
-	USB4_CL2_State_Supported,		/* booleanFieldType */
-	USB4_Num_Retimers,			/* numericFieldType */
-	USB4_DP_Bit_Rate,			/* numericFieldType */
-	USB4_Num_DP_Lanes,			/* numericFieldType */
+	USB4_Port_Header, /* comment */
+	USB4_Lane_0_Adapter, /* numericFieldType */
+	USB4_Max_Speed, /* numericFieldType */
+	USB4_DFP_Supported, /* booleanFieldType */
+	USB4_UFP_Supported, /* booleanFieldType */
+	USB4_USB3_Tunneling_Supported, /* booleanFieldType */
+	USB4_DP_Tunneling_Supported, /* booleanFieldType */
+	USB4_PCIe_Tunneling_Supported, /* booleanFieldType */
+	USB4_TBT3_Compatibility_Supported, /* booleanFieldType */
+	USB4_CL1_State_Supported, /* booleanFieldType */
+	USB4_CL2_State_Supported, /* booleanFieldType */
+	USB4_Num_Retimers, /* numericFieldType */
+	USB4_DP_Bit_Rate, /* numericFieldType */
+	USB4_Num_DP_Lanes, /* numericFieldType */
 
 	/* 3.2.7 USB Data - Upstream Facing Port Fields */
-	Device_Supports_USB_Data,		/* booleanFieldType */
-	Device_Speed,				/* numericFieldType */
-	Device_Contains_Captive_Retimer,	/* booleanFieldType */
-	Device_Truncates_DP_For_tDHPResponse,	/* booleanFieldType */
-	Device_Gen1x1_tLinkTurnaround,		/* numericFieldType */
-	Device_Gen2x1_tLinkTurnaround,		/* numericFieldType */
+	Device_Supports_USB_Data, /* booleanFieldType */
+	Device_Speed, /* numericFieldType */
+	Device_Contains_Captive_Retimer, /* booleanFieldType */
+	Device_Truncates_DP_For_tDHPResponse, /* booleanFieldType */
+	Device_Gen1x1_tLinkTurnaround, /* numericFieldType */
+	Device_Gen2x1_tLinkTurnaround, /* numericFieldType */
 
 	/* 3.2.19 Product Power Fields */
-	Product_Power_Header,			/* comment */
-	Product_Total_Source_Power_mW,		/* numericFieldType */
-	Port_Source_Power_Type,			/* numericFieldType */
-	Port_Source_Power_Gang,			/* nonEmptyString */
-	Port_Source_Power_Gang_Max_Power,	/* numericFieldType */
+	Product_Power_Header, /* comment */
+	Product_Total_Source_Power_mW, /* numericFieldType */
+	Port_Source_Power_Type, /* numericFieldType */
+	Port_Source_Power_Gang, /* nonEmptyString */
+	Port_Source_Power_Gang_Max_Power, /* numericFieldType */
 
 	/* 3.2.8 USB Data - Downstream Facing Port Fields */
-	USB_Host_Header,			/* comment */
-	Host_Supports_USB_Data,			/* booleanFieldType */
-	Host_Speed,				/* numericFieldType */
-	Host_Contains_Captive_Retimer,		/* booleanFieldType */
-	Host_Truncates_DP_For_tDHPResponse,	/* booleanFieldType */
-	Host_Gen1x1_tLinkTurnaround,		/* numericFieldType */
-	Host_Gen2x1_tLinkTurnaround,		/* numericFieldType */
-	Host_Is_Embedded,			/* booleanFieldType */
-	Host_Suspend_Supported,			/* booleanFieldType */
-	Is_DFP_On_Hub,				/* booleanFieldType */
-	Hub_Port_Number,			/* numericFieldType */
+	USB_Host_Header, /* comment */
+	Host_Supports_USB_Data, /* booleanFieldType */
+	Host_Speed, /* numericFieldType */
+	Host_Contains_Captive_Retimer, /* booleanFieldType */
+	Host_Truncates_DP_For_tDHPResponse, /* booleanFieldType */
+	Host_Gen1x1_tLinkTurnaround, /* numericFieldType */
+	Host_Gen2x1_tLinkTurnaround, /* numericFieldType */
+	Host_Is_Embedded, /* booleanFieldType */
+	Host_Suspend_Supported, /* booleanFieldType */
+	Is_DFP_On_Hub, /* booleanFieldType */
+	Hub_Port_Number, /* numericFieldType */
 
 	/* 3.2.14 Battery Charging 1.2 Fields */
-	BC_1_2_Header,				/* comment */
-	BC_1_2_Charging_Port_Type,		/* numericFieldType */
+	BC_1_2_Header, /* comment */
+	BC_1_2_Charging_Port_Type, /* numericFieldType */
 
 	/* 3.2.9 PD Source Fields */
-	PD_Source_Header,			/* comment */
-	PD_Power_As_Source,			/* numericFieldType */
-	EPR_Supported_As_Src,			/* booleanFieldType */
-	USB_Suspend_May_Be_Cleared,		/* booleanFieldType */
-	Sends_Pings,				/* booleanFieldType */
-	FR_Swap_Type_C_Current_Capability_As_Initial_Sink,/* numericFieldType */
-	Master_Port,				/* booleanFieldType */
-	Num_Src_PDOs,				/* numericFieldType */
-	PD_OC_Protection,			/* booleanFieldType */
-	PD_OCP_Method,				/* numericFieldType */
+	PD_Source_Header, /* comment */
+	PD_Power_As_Source, /* numericFieldType */
+	EPR_Supported_As_Src, /* booleanFieldType */
+	USB_Suspend_May_Be_Cleared, /* booleanFieldType */
+	Sends_Pings, /* booleanFieldType */
+	FR_Swap_Type_C_Current_Capability_As_Initial_Sink, /* numericFieldType
+							    */
+	Master_Port, /* booleanFieldType */
+	Num_Src_PDOs, /* numericFieldType */
+	PD_OC_Protection, /* booleanFieldType */
+	PD_OCP_Method, /* numericFieldType */
 
 	/* insert: SrcPdoList */
 
 	/* 3.2.10 PD Sink Fields */
-	PD_Sink_Header,				/* comment */
-	PD_Power_As_Sink,			/* numericFieldType */
-	EPR_Supported_As_Snk,			/* booleanFieldType */
-	No_USB_Suspend_May_Be_Set,		/* booleanFieldType */
-	GiveBack_May_Be_Set,			/* booleanFieldType */
-	Higher_Capability_Set,			/* booleanFieldType */
-	FR_Swap_Reqd_Type_C_Current_As_Initial_Source,/* numericFieldType */
-	Num_Snk_PDOs,				/* numericFieldType */
+	PD_Sink_Header, /* comment */
+	PD_Power_As_Sink, /* numericFieldType */
+	EPR_Supported_As_Snk, /* booleanFieldType */
+	No_USB_Suspend_May_Be_Set, /* booleanFieldType */
+	GiveBack_May_Be_Set, /* booleanFieldType */
+	Higher_Capability_Set, /* booleanFieldType */
+	FR_Swap_Reqd_Type_C_Current_As_Initial_Source, /* numericFieldType */
+	Num_Snk_PDOs, /* numericFieldType */
 
 	/* insert: SnkPdoList */
 
 	/* 3.2.11 PD Dual Role Fields */
-	Dual_Role_Header,			/* comment */
-	Accepts_PR_Swap_As_Src,			/* booleanFieldType */
-	Accepts_PR_Swap_As_Snk,			/* booleanFieldType */
-	Requests_PR_Swap_As_Src,		/* booleanFieldType */
-	Requests_PR_Swap_As_Snk,		/* booleanFieldType */
-	FR_Swap_Supported_As_Initial_Sink,	/* booleanFieldType */
+	Dual_Role_Header, /* comment */
+	Accepts_PR_Swap_As_Src, /* booleanFieldType */
+	Accepts_PR_Swap_As_Snk, /* booleanFieldType */
+	Requests_PR_Swap_As_Src, /* booleanFieldType */
+	Requests_PR_Swap_As_Snk, /* booleanFieldType */
+	FR_Swap_Supported_As_Initial_Sink, /* booleanFieldType */
 
 	/* 3.2.12 SOP Discover ID Fields */
-	SOP_Discover_ID_Header,			/* comment */
-	XID_SOP,				/* numericFieldType */
-	Data_Capable_As_USB_Host_SOP,		/* booleanFieldType */
-	Data_Capable_As_USB_Device_SOP,		/* booleanFieldType */
-	Product_Type_UFP_SOP,			/* numericFieldType */
-	Product_Type_DFP_SOP,			/* numericFieldType */
-	DFP_VDO_Port_Number,			/* numericFieldType */
-	Modal_Operation_Supported_SOP,		/* booleanFieldType */
-	USB_VID_SOP,				/* numericFieldType */
-	PID_SOP,				/* numericFieldType */
-	bcdDevice_SOP,				/* numericFieldType */
-	Num_SVIDs_Min_SOP,			/* numericFieldType */
-	Num_SVIDs_Max_SOP,			/* numericFieldType */
-	SVID_Fixed_SOP,				/* booleanFieldType */
+	SOP_Discover_ID_Header, /* comment */
+	XID_SOP, /* numericFieldType */
+	Data_Capable_As_USB_Host_SOP, /* booleanFieldType */
+	Data_Capable_As_USB_Device_SOP, /* booleanFieldType */
+	Product_Type_UFP_SOP, /* numericFieldType */
+	Product_Type_DFP_SOP, /* numericFieldType */
+	DFP_VDO_Port_Number, /* numericFieldType */
+	Modal_Operation_Supported_SOP, /* booleanFieldType */
+	USB_VID_SOP, /* numericFieldType */
+	PID_SOP, /* numericFieldType */
+	bcdDevice_SOP, /* numericFieldType */
+	Num_SVIDs_Min_SOP, /* numericFieldType */
+	Num_SVIDs_Max_SOP, /* numericFieldType */
+	SVID_Fixed_SOP, /* booleanFieldType */
 
 	/* 3.2.13 Alternate Mode Adapter (AMA) Fields */
-	AMA_HW_Vers,				/* numericFieldType */
-	AMA_FW_Vers,				/* numericFieldType */
-	AMA_VCONN_Power,			/* booleanFieldType */
-	AMA_VCONN_Reqd,				/* booleanFieldType */
-	AMA_VBUS_Reqd,				/* booleanFieldType */
-	AMA_Superspeed_Support,			/* numericFieldType */
+	AMA_HW_Vers, /* numericFieldType */
+	AMA_FW_Vers, /* numericFieldType */
+	AMA_VCONN_Power, /* booleanFieldType */
+	AMA_VCONN_Reqd, /* booleanFieldType */
+	AMA_VBUS_Reqd, /* booleanFieldType */
+	AMA_Superspeed_Support, /* numericFieldType */
 
 	/* 3.2.15 Cable/eMarker Fields */
-	XID,					/* numericFieldType */
-	Data_Capable_As_USB_Host,		/* booleanFieldType */
-	Data_Capable_As_USB_Device,		/* booleanFieldType */
-	Product_Type,				/* numericFieldType */
-	Modal_Operation_Supported,		/* booleanFieldType */
-	USB_VID,				/* numericFieldType */
-	PID,					/* numericFieldType */
-	bcdDevice,				/* numericFieldType */
-	Cable_HW_Vers,				/* numericFieldType */
-	Cable_FW_Vers,				/* numericFieldType */
-	Type_C_To_Type_A_B_C,			/* numericFieldType */
-	Type_C_To_Type_C_Capt_Vdm_V2,		/* numericFieldType */
-	EPR_Mode_Capable,			/* booleanFieldType */
-	Cable_Latency,				/* numericFieldType */
-	Cable_Termination_Type,			/* numericFieldType */
-	Cable_VBUS_Current,			/* numericFieldType */
-	VBUS_Through_Cable,			/* booleanFieldType */
-	Cable_Superspeed_Support,		/* numericFieldType */
-	Cable_USB_Highest_Speed,		/* numericFieldType */
-	Max_VBUS_Voltage_Vdm_V2,		/* numericFieldType */
-	Manufacturer_Info_Supported,		/* booleanFieldType */
-	Manufacturer_Info_VID,			/* numericFieldType */
-	Manufacturer_Info_PID,			/* numericFieldType */
-	Chunking_Implemented,			/* booleanFieldType */
-	Security_Msgs_Supported,		/* booleanFieldType */
-	ID_Header_Connector_Type,		/* numericFieldType */
-	Cable_Num_SVIDs_Min,			/* numericFieldType */
-	Cable_Num_SVIDs_Max,			/* numericFieldType */
-	SVID_Fixed,				/* booleanFieldType */
+	XID, /* numericFieldType */
+	Data_Capable_As_USB_Host, /* booleanFieldType */
+	Data_Capable_As_USB_Device, /* booleanFieldType */
+	Product_Type, /* numericFieldType */
+	Modal_Operation_Supported, /* booleanFieldType */
+	USB_VID, /* numericFieldType */
+	PID, /* numericFieldType */
+	bcdDevice, /* numericFieldType */
+	Cable_HW_Vers, /* numericFieldType */
+	Cable_FW_Vers, /* numericFieldType */
+	Type_C_To_Type_A_B_C, /* numericFieldType */
+	Type_C_To_Type_C_Capt_Vdm_V2, /* numericFieldType */
+	EPR_Mode_Capable, /* booleanFieldType */
+	Cable_Latency, /* numericFieldType */
+	Cable_Termination_Type, /* numericFieldType */
+	Cable_VBUS_Current, /* numericFieldType */
+	VBUS_Through_Cable, /* booleanFieldType */
+	Cable_Superspeed_Support, /* numericFieldType */
+	Cable_USB_Highest_Speed, /* numericFieldType */
+	Max_VBUS_Voltage_Vdm_V2, /* numericFieldType */
+	Manufacturer_Info_Supported, /* booleanFieldType */
+	Manufacturer_Info_VID, /* numericFieldType */
+	Manufacturer_Info_PID, /* numericFieldType */
+	Chunking_Implemented, /* booleanFieldType */
+	Security_Msgs_Supported, /* booleanFieldType */
+	ID_Header_Connector_Type, /* numericFieldType */
+	Cable_Num_SVIDs_Min, /* numericFieldType */
+	Cable_Num_SVIDs_Max, /* numericFieldType */
+	SVID_Fixed, /* booleanFieldType */
 
 	/* 3.2.16 Active Cable Fields */
-	Cable_SOP_PP_Controller,		/* booleanFieldType */
-	SBU_Supported,				/* booleanFieldType */
-	SBU_Type,				/* numericFieldType */
-	Active_Cable_Max_Operating_Temp,	/* numericFieldType */
-	Active_Cable_Shutdown_Temp,		/* numericFieldType */
-	Active_Cable_U3_CLd_Power,		/* numericFieldType */
-	Active_Cable_U3_U0_Trans_Mode,		/* numericFieldType */
-	Active_Cable_Physical_Connection,	/* numericFieldType */
-	Active_Cable_Active_Element,		/* numericFieldType */
-	Active_Cable_USB4_Support,		/* booleanFieldType */
-	Active_Cable_USB2_Supported,		/* booleanFieldType */
-	Active_Cable_USB2_Hub_Hops_Consumed,	/* numericFieldType */
-	Active_Cable_USB32_Supported,		/* booleanFieldType */
-	Active_Cable_USB_Lanes,			/* numericFieldType */
-	Active_Cable_Optically_Isolated,	/* booleanFieldType */
-	Active_Cable_USB_Gen,			/* numericFieldType */
+	Cable_SOP_PP_Controller, /* booleanFieldType */
+	SBU_Supported, /* booleanFieldType */
+	SBU_Type, /* numericFieldType */
+	Active_Cable_Max_Operating_Temp, /* numericFieldType */
+	Active_Cable_Shutdown_Temp, /* numericFieldType */
+	Active_Cable_U3_CLd_Power, /* numericFieldType */
+	Active_Cable_U3_U0_Trans_Mode, /* numericFieldType */
+	Active_Cable_Physical_Connection, /* numericFieldType */
+	Active_Cable_Active_Element, /* numericFieldType */
+	Active_Cable_USB4_Support, /* booleanFieldType */
+	Active_Cable_USB2_Supported, /* booleanFieldType */
+	Active_Cable_USB2_Hub_Hops_Consumed, /* numericFieldType */
+	Active_Cable_USB32_Supported, /* booleanFieldType */
+	Active_Cable_USB_Lanes, /* numericFieldType */
+	Active_Cable_Optically_Isolated, /* booleanFieldType */
+	Active_Cable_USB_Gen, /* numericFieldType */
 
 	/* 3.2.17 VCONN Powered Devices */
-	VPD_HW_Vers,				/* numericFieldType */
-	VPD_FW_Vers,				/* numericFieldType */
-	VPD_Max_VBUS_Voltage,			/* numericFieldType */
-	VPD_Charge_Through_Support,		/* booleanFieldType */
-	VPD_Charge_Through_Current,		/* numericFieldType */
-	VPD_VBUS_Impedance,			/* numericFieldType */
-	VPD_Ground_Impedance,			/* numericFieldType */
+	VPD_HW_Vers, /* numericFieldType */
+	VPD_FW_Vers, /* numericFieldType */
+	VPD_Max_VBUS_Voltage, /* numericFieldType */
+	VPD_Charge_Through_Support, /* booleanFieldType */
+	VPD_Charge_Through_Current, /* numericFieldType */
+	VPD_VBUS_Impedance, /* numericFieldType */
+	VPD_Ground_Impedance, /* numericFieldType */
 
 	/* 3.2.18 Repeater Fields */
-	Repeater_One_Type,			/* numericFieldType */
-	Repeater_Two_Type,			/* numericFieldType */
+	Repeater_One_Type, /* numericFieldType */
+	Repeater_Two_Type, /* numericFieldType */
 
 	Component_Indexes
 };
 
 struct vif_Component_t {
-	struct vif_field_t		vif_field[Component_Indexes];
+	struct vif_field_t vif_field[Component_Indexes];
 
-	struct vif_srcPdoList_t		SrcPdoList[MAX_NUM_SRC_PDOS];
-	struct vif_snkPdoList_t		SnkPdoList[MAX_NUM_SNK_PDOS];
-	struct vif_sopSVIDList_t	SOPSVIDList[MAX_NUM_SOP_SVIDS];
-	struct vif_cableSVIDList_t	CableSVIDList[MAX_NUM_CABLE_SVIDS];
+	struct vif_srcPdoList_t SrcPdoList[MAX_NUM_SRC_PDOS];
+	struct vif_snkPdoList_t SnkPdoList[MAX_NUM_SNK_PDOS];
+	struct vif_sopSVIDList_t SOPSVIDList[MAX_NUM_SOP_SVIDS];
+	struct vif_cableSVIDList_t CableSVIDList[MAX_NUM_CABLE_SVIDS];
 
 	/*
 	 * The following fields are deprecated.  They should not be written
@@ -434,55 +434,55 @@ struct vif_Component_t {
 /* 3.2.2 Product Fields */
 
 enum vif_Product_indexes {
-	USB4_Product_Header,			/* comment */
-	USB4_DROM_Vendor_ID,			/* numericFieldType */
-	USB4_Dock,				/* booleanFieldType */
-	USB4_Num_Internal_Host_Controllers,	/* numericFieldType */
-	USB4_Num_PCIe_DN_Bridges,		/* numericFieldType */
-	USB4_Device_HiFi_Bi_TMU_Mode_Required,	/* booleanFieldType */
-	USB4_Audio_Supported,			/* booleanFieldType */
-	USB4_HID_Supported,			/* booleanFieldType */
-	USB4_Printer_Supported,			/* booleanFieldType */
-	USB4_Mass_Storage_Supported,		/* booleanFieldType */
-	USB4_Video_Supported,			/* booleanFieldType */
-	USB4_Comms_Networking_Supported,	/* booleanFieldType */
-	USB4_Media_Transfer_Protocol_Supported,	/* booleanFieldType */
-	USB4_Smart_Card_Supported,		/* booleanFieldType */
-	USB4_Still_Image_Capture_Supported,	/* booleanFieldType */
-	USB4_Monitor_Device_Supported,		/* booleanFieldType */
+	USB4_Product_Header, /* comment */
+	USB4_DROM_Vendor_ID, /* numericFieldType */
+	USB4_Dock, /* booleanFieldType */
+	USB4_Num_Internal_Host_Controllers, /* numericFieldType */
+	USB4_Num_PCIe_DN_Bridges, /* numericFieldType */
+	USB4_Device_HiFi_Bi_TMU_Mode_Required, /* booleanFieldType */
+	USB4_Audio_Supported, /* booleanFieldType */
+	USB4_HID_Supported, /* booleanFieldType */
+	USB4_Printer_Supported, /* booleanFieldType */
+	USB4_Mass_Storage_Supported, /* booleanFieldType */
+	USB4_Video_Supported, /* booleanFieldType */
+	USB4_Comms_Networking_Supported, /* booleanFieldType */
+	USB4_Media_Transfer_Protocol_Supported, /* booleanFieldType */
+	USB4_Smart_Card_Supported, /* booleanFieldType */
+	USB4_Still_Image_Capture_Supported, /* booleanFieldType */
+	USB4_Monitor_Device_Supported, /* booleanFieldType */
 	Product_Indexes
 };
 
 struct vif_Product_t {
-	struct vif_field_t		vif_field[Product_Indexes];
+	struct vif_field_t vif_field[Product_Indexes];
 
 	struct vif_Usb4RouterListType_t USB4RouterList[MAX_NUM_USB4_ROUTERS];
 };
 
 enum vif_indexes {
-	VIF_Specification,		/* version */
-	Vendor_Name,			/* nonEmptyString */
-	Model_Part_Number,		/* nonEmptyString */
-	Product_Revision,		/* nonEmptyString */
-	TID,				/* nonEmptyString */
-	VIF_Product_Type,		/* numericFieldType */
-	Certification_Type,		/* numericFieldType */
+	VIF_Specification, /* version */
+	Vendor_Name, /* nonEmptyString */
+	Model_Part_Number, /* nonEmptyString */
+	Product_Revision, /* nonEmptyString */
+	TID, /* nonEmptyString */
+	VIF_Product_Type, /* numericFieldType */
+	Certification_Type, /* numericFieldType */
 	VIF_Indexes
 };
 
 enum vif_app_indexes {
-	Vendor,				/* nonEmptyString */
-	Name,				/* nonEmptyString */
-	Version,			/* version */
+	Vendor, /* nonEmptyString */
+	Name, /* nonEmptyString */
+	Version, /* version */
 	VIF_App_Indexes
 };
 
 struct vif_t {
-	struct vif_field_t		vif_field[VIF_Indexes];
-	struct vif_field_t		vif_app_field[VIF_App_Indexes];
+	struct vif_field_t vif_field[VIF_Indexes];
+	struct vif_field_t vif_app_field[VIF_App_Indexes];
 
-	struct vif_Product_t		Product;
-	struct vif_Component_t		Component[MAX_NUM_COMPONENTS];
+	struct vif_Product_t Product;
+	struct vif_Component_t Component[MAX_NUM_COMPONENTS];
 };
 
 #endif /* __GENVIF_H__ */
diff --git a/util/getversion.sh b/util/getversion.sh
index 3146b29c88..f096229db9 100755
--- a/util/getversion.sh
+++ b/util/getversion.sh
@@ -1,6 +1,6 @@
 #!/bin/bash
 #
-# Copyright 2012 The Chromium OS Authors. All rights reserved.
+# Copyright 2012 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -77,7 +77,7 @@ get_tree_version() {
     # Ex VCSID: 0.0.1-r1519-9b368af6a4943b90941471d0bdf7e7208788f898
     if [[ -n "${VCSID}" ]]; then
       ghash="${VCSID##*-}"
-      vbase="1.1.9999-${ghash:0:7}"
+      vbase="v2.1.9999-${ghash:0:8}"
     else
       # then ultimately fails to "no_version"
       vbase="no_version"
@@ -140,9 +140,11 @@ main() {
       if [[ -n "${values[1]}" ]]; then
         # From each modified repo get the most recently modified file.
         most_recent_file="$(git status --porcelain | \
-                                 awk '$1 ~ /[M|A|?]/ {print $2}' |  \
-                                 xargs ls -t | head -1)"
-        most_recents+=("$(realpath "${most_recent_file}")")
+                                 awk '$1 ~ /[M|A|?]/ {print $2}' | \
+                                 xargs -r ls -t | head -1)"
+        if [[ -n "${most_recent_file}" ]]; then
+          most_recents+=("$(realpath "${most_recent_file}")")
+        fi
       fi
       if [ "${component}" != "." ]; then
       ver+=" ${component}:"
diff --git a/util/gpios_to_zephyr_dts.c b/util/gpios_to_zephyr_dts.c
index 166c16dde7..d0e51b3e46 100644
--- a/util/gpios_to_zephyr_dts.c
+++ b/util/gpios_to_zephyr_dts.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/util/host_command_check.sh b/util/host_command_check.sh
index f699803b2e..8dc8280cbd 100755
--- a/util/host_command_check.sh
+++ b/util/host_command_check.sh
@@ -1,6 +1,6 @@
 #!/bin/bash
 #
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/util/ide-config.sh b/util/ide-config.sh
index 25edca2407..a172cf5767 100755
--- a/util/ide-config.sh
+++ b/util/ide-config.sh
@@ -1,5 +1,5 @@
 #!/bin/bash
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/util/inject-keys.py b/util/inject-keys.py
index bd10b693ad..7ff72ea134 100755
--- a/util/inject-keys.py
+++ b/util/inject-keys.py
@@ -1,57 +1,133 @@
 #!/usr/bin/env python
 # -*- coding: utf-8 -*-
 #
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 # Note: This is a py2/3 compatible file.
 
 from __future__ import print_function
+
 import string
 import subprocess
 import sys
 
-
-KEYMATRIX = {'`': (3, 1), '1': (6, 1), '2': (6, 4), '3': (6, 2), '4': (6, 3),
-             '5': (3, 3), '6': (3, 6), '7': (6, 6), '8': (6, 5), '9': (6, 9),
-             '0': (6, 8), '-': (3, 8), '=': (0, 8), 'q': (7, 1), 'w': (7, 4),
-             'e': (7, 2), 'r': (7, 3), 't': (2, 3), 'y': (2, 6), 'u': (7, 6),
-             'i': (7, 5), 'o': (7, 9), 'p': (7, 8), '[': (2, 8), ']': (2, 5),
-             '\\': (3, 11), 'a': (4, 1), 's': (4, 4), 'd': (4, 2), 'f': (4, 3),
-             'g': (1, 3), 'h': (1, 6), 'j': (4, 6), 'k': (4, 5), 'l': (4, 9),
-             ';': (4, 8), '\'': (1, 8), 'z': (5, 1), 'x': (5, 4), 'c': (5, 2),
-             'v': (5, 3), 'b': (0, 3), 'n': (0, 6), 'm': (5, 6), ',': (5, 5),
-             '.': (5, 9), '/': (5, 8), ' ': (5, 11), '<right>': (6, 12),
-             '<alt_r>': (0, 10), '<down>': (6, 11), '<tab>': (2, 1),
-             '<f10>': (0, 4), '<shift_r>': (7, 7), '<ctrl_r>': (4, 0),
-             '<esc>': (1, 1), '<backspace>': (1, 11), '<f2>': (3, 2),
-             '<alt_l>': (6, 10), '<ctrl_l>': (2, 0), '<f1>': (0, 2),
-             '<search>': (0, 1), '<f3>': (2, 2), '<f4>': (1, 2), '<f5>': (3, 4),
-             '<f6>': (2, 4), '<f7>': (1, 4), '<f8>': (2, 9), '<f9>': (1, 9),
-             '<up>': (7, 11), '<shift_l>': (5, 7), '<enter>': (4, 11),
-             '<left>': (7, 12)}
-
-
-UNSHIFT_TABLE = { '~': '`', '!': '1', '@': '2', '#': '3', '$': '4',
-                  '%': '5', '^': '6', '&': '7', '*': '8', '(': '9',
-                  ')': '0', '_': '-', '+': '=', '{': '[', '}': ']',
-                  '|': '\\',
-                  ':': ';', '"': "'", '<': ',', '>': '.', '?': '/'}
+KEYMATRIX = {
+    "`": (3, 1),
+    "1": (6, 1),
+    "2": (6, 4),
+    "3": (6, 2),
+    "4": (6, 3),
+    "5": (3, 3),
+    "6": (3, 6),
+    "7": (6, 6),
+    "8": (6, 5),
+    "9": (6, 9),
+    "0": (6, 8),
+    "-": (3, 8),
+    "=": (0, 8),
+    "q": (7, 1),
+    "w": (7, 4),
+    "e": (7, 2),
+    "r": (7, 3),
+    "t": (2, 3),
+    "y": (2, 6),
+    "u": (7, 6),
+    "i": (7, 5),
+    "o": (7, 9),
+    "p": (7, 8),
+    "[": (2, 8),
+    "]": (2, 5),
+    "\\": (3, 11),
+    "a": (4, 1),
+    "s": (4, 4),
+    "d": (4, 2),
+    "f": (4, 3),
+    "g": (1, 3),
+    "h": (1, 6),
+    "j": (4, 6),
+    "k": (4, 5),
+    "l": (4, 9),
+    ";": (4, 8),
+    "'": (1, 8),
+    "z": (5, 1),
+    "x": (5, 4),
+    "c": (5, 2),
+    "v": (5, 3),
+    "b": (0, 3),
+    "n": (0, 6),
+    "m": (5, 6),
+    ",": (5, 5),
+    ".": (5, 9),
+    "/": (5, 8),
+    " ": (5, 11),
+    "<right>": (6, 12),
+    "<alt_r>": (0, 10),
+    "<down>": (6, 11),
+    "<tab>": (2, 1),
+    "<f10>": (0, 4),
+    "<shift_r>": (7, 7),
+    "<ctrl_r>": (4, 0),
+    "<esc>": (1, 1),
+    "<backspace>": (1, 11),
+    "<f2>": (3, 2),
+    "<alt_l>": (6, 10),
+    "<ctrl_l>": (2, 0),
+    "<f1>": (0, 2),
+    "<search>": (0, 1),
+    "<f3>": (2, 2),
+    "<f4>": (1, 2),
+    "<f5>": (3, 4),
+    "<f6>": (2, 4),
+    "<f7>": (1, 4),
+    "<f8>": (2, 9),
+    "<f9>": (1, 9),
+    "<up>": (7, 11),
+    "<shift_l>": (5, 7),
+    "<enter>": (4, 11),
+    "<left>": (7, 12),
+}
+
+
+UNSHIFT_TABLE = {
+    "~": "`",
+    "!": "1",
+    "@": "2",
+    "#": "3",
+    "$": "4",
+    "%": "5",
+    "^": "6",
+    "&": "7",
+    "*": "8",
+    "(": "9",
+    ")": "0",
+    "_": "-",
+    "+": "=",
+    "{": "[",
+    "}": "]",
+    "|": "\\",
+    ":": ";",
+    '"': "'",
+    "<": ",",
+    ">": ".",
+    "?": "/",
+}
 
 for c in string.ascii_lowercase:
     UNSHIFT_TABLE[c.upper()] = c
 
 
 def inject_event(key, press):
-    if len(key) >= 2 and key[0] != '<':
-        key = '<' + key + '>'
+    if len(key) >= 2 and key[0] != "<":
+        key = "<" + key + ">"
     if key not in KEYMATRIX:
         print("%s: invalid key: %s" % (this_script, key))
         sys.exit(1)
     (row, col) = KEYMATRIX[key]
-    subprocess.call(["ectool", "kbpress", str(row), str(col),
-                     "1" if press else "0"])
+    subprocess.call(
+        ["ectool", "kbpress", str(row), str(col), "1" if press else "0"]
+    )
 
 
 def inject_key(key):
@@ -73,8 +149,10 @@ def inject_string(string):
 
 
 def usage():
-    print("Usage: %s [-s <string>] [-k <key>]" % this_script,
-          "[-p <pressed-key>] [-r <released-key>] ...")
+    print(
+        "Usage: %s [-s <string>] [-k <key>]" % this_script,
+        "[-p <pressed-key>] [-r <released-key>] ...",
+    )
     print("Examples:")
     print("%s -s MyPassw0rd -k enter" % this_script)
     print("%s -p ctrl_l -p alt_l -k f3 -r alt_l -r ctrl_l" % this_script)
@@ -85,7 +163,7 @@ def help():
     print("Valid keys are:")
     i = 0
     for key in KEYMATRIX:
-        print("%12s" % key, end='')
+        print("%12s" % key, end="")
         i += 1
         if i % 4 == 0:
             print()
@@ -114,12 +192,14 @@ usage_check(arg_len > 1, "not enough arguments")
 usage_check(arg_len % 2 == 1, "mismatched arguments")
 
 for i in range(1, arg_len, 2):
-    usage_check(sys.argv[i] in ("-s", "-k", "-p", "-r"),
-                "unknown flag: %s" % sys.argv[i])
+    usage_check(
+        sys.argv[i] in ("-s", "-k", "-p", "-r"),
+        "unknown flag: %s" % sys.argv[i],
+    )
 
 for i in range(1, arg_len, 2):
     flag = sys.argv[i]
-    arg = sys.argv[i+1]
+    arg = sys.argv[i + 1]
     if flag == "-s":
         inject_string(arg)
     elif flag == "-k":
diff --git a/util/iteflash.c b/util/iteflash.c
index a4a166d3d8..9085365135 100644
--- a/util/iteflash.c
+++ b/util/iteflash.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -38,65 +38,65 @@
 #define CR50_USB_PID 0x5014
 
 /* Cr50 exposed properties of the USB I2C endpoint. */
-#define CR50_I2C_SUBCLASS  82
-#define CR50_I2C_PROTOCOL  1
+#define CR50_I2C_SUBCLASS 82
+#define CR50_I2C_PROTOCOL 1
 
-#define CROS_CMD_ADDR		0x78	/* USB_I2C_CMD_ADDR 0xF0 >> 1 */
-#define CROS_CMD_ITE_SYNC	0
+#define CROS_CMD_ADDR 0x78 /* USB_I2C_CMD_ADDR 0xF0 >> 1 */
+#define CROS_CMD_ITE_SYNC 0
 
 /* DBGR I2C addresses */
-#define I2C_CMD_ADDR   0x5A
-#define I2C_DATA_ADDR  0x35
+#define I2C_CMD_ADDR 0x5A
+#define I2C_DATA_ADDR 0x35
 #define I2C_BLOCK_ADDR 0x79
 
 #define FTDI_I2C_FREQ 400000
 
 /* I2C pins on the FTDI interface */
-#define SCL_BIT        BIT(0)
-#define SDA_BIT        BIT(1)
+#define SCL_BIT BIT(0)
+#define SDA_BIT BIT(1)
 
 /* Chip ID register value */
 #define CHIP_ID 0x8380
 
 /* Embedded flash page size */
-#define PAGE_SIZE		(1<<8)
+#define PAGE_SIZE (1 << 8)
 
 /* Embedded flash block write size for different programming modes. */
-#define FTDI_BLOCK_WRITE_SIZE	(1<<16)
+#define FTDI_BLOCK_WRITE_SIZE (1 << 16)
 
 /* JEDEC SPI Flash commands */
-#define SPI_CMD_PAGE_PROGRAM	0x02
-#define SPI_CMD_WRITE_DISABLE	0x04
-#define SPI_CMD_READ_STATUS	0x05
-#define SPI_CMD_WRITE_ENABLE	0x06
-#define SPI_CMD_FAST_READ	0x0B
-#define SPI_CMD_CHIP_ERASE	0x60
-#define SPI_CMD_SECTOR_ERASE_1K	0xD7
-#define SPI_CMD_SECTOR_ERASE_4K	0x20
-#define SPI_CMD_WORD_PROGRAM	0xAD
-#define SPI_CMD_EWSR		0x50 /* Enable Write Status Register */
-#define SPI_CMD_WRSR		0x01 /* Write Status Register */
-#define SPI_CMD_RDID		0x9F /* Read Flash ID */
+#define SPI_CMD_PAGE_PROGRAM 0x02
+#define SPI_CMD_WRITE_DISABLE 0x04
+#define SPI_CMD_READ_STATUS 0x05
+#define SPI_CMD_WRITE_ENABLE 0x06
+#define SPI_CMD_FAST_READ 0x0B
+#define SPI_CMD_CHIP_ERASE 0x60
+#define SPI_CMD_SECTOR_ERASE_1K 0xD7
+#define SPI_CMD_SECTOR_ERASE_4K 0x20
+#define SPI_CMD_WORD_PROGRAM 0xAD
+#define SPI_CMD_EWSR 0x50 /* Enable Write Status Register */
+#define SPI_CMD_WRSR 0x01 /* Write Status Register */
+#define SPI_CMD_RDID 0x9F /* Read Flash ID */
 
 /* Size for FTDI outgoing buffer */
-#define FTDI_CMD_BUF_SIZE (1<<12)
+#define FTDI_CMD_BUF_SIZE (1 << 12)
 
 /* Reset Status */
-#define RSTS_VCCDO_PW_ON	0x40
-#define RSTS_VFSPIPG		0x20
-#define RSTS_HGRST		0x08
-#define RSTS_GRST		0x04
+#define RSTS_VCCDO_PW_ON 0x40
+#define RSTS_VFSPIPG 0x20
+#define RSTS_HGRST 0x08
+#define RSTS_GRST 0x04
 
 /* I2C MUX Configuration: TCA9543 or PCA9546 */
-#define I2C_MUX_CMD_ADDR		0x70
-#define I2C_MUX_CMD_NONE		0x00
-#define I2C_MUX_CMD_INAS		0x01
-#define I2C_MUX_CMD_EC			0x02
+#define I2C_MUX_CMD_ADDR 0x70
+#define I2C_MUX_CMD_NONE 0x00
+#define I2C_MUX_CMD_INAS 0x01
+#define I2C_MUX_CMD_EC 0x02
 
 /* Eflash Type*/
-#define EFLASH_TYPE_8315	0x01
-#define EFLASH_TYPE_KGD		0x02
-#define EFLASH_TYPE_NONE	0xFF
+#define EFLASH_TYPE_8315 0x01
+#define EFLASH_TYPE_KGD 0x02
+#define EFLASH_TYPE_NONE 0xFF
 
 uint8_t eflash_type;
 uint8_t spi_cmd_sector_erase;
@@ -104,7 +104,6 @@ uint8_t spi_cmd_sector_erase;
 /* Embedded flash number of pages in a sector erase */
 uint8_t sector_erase_pages;
 
-
 static volatile sig_atomic_t exit_requested;
 
 struct i2c_interface;
@@ -113,17 +112,17 @@ struct i2c_interface;
 struct iteflash_config {
 	char *input_filename;
 	char *output_filename;
-	int send_waveform;  /* boolean */
-	int erase;  /* boolean */
+	int send_waveform; /* boolean */
+	int erase; /* boolean */
 	int i2c_mux; /* boolean */
-	int debug;  /* boolean */
-	int disable_watchdog;  /* boolean */
-	int disable_protect_path;  /* boolean */
+	int debug; /* boolean */
+	int disable_watchdog; /* boolean */
+	int disable_protect_path; /* boolean */
 	int block_write_size;
 	int usb_interface;
 	int usb_vid;
 	int usb_pid;
-	int verify;  /* boolean */
+	int verify; /* boolean */
 	char *usb_serial;
 	char *i2c_dev_path;
 	const struct i2c_interface *i2c_if;
@@ -134,8 +133,8 @@ struct iteflash_config {
 struct common_hnd {
 	struct iteflash_config conf;
 	int flash_size;
-	int flash_cmd_v2;      /* boolean */
-	int dbgr_addr_3bytes;  /* boolean */
+	int flash_cmd_v2; /* boolean */
+	int dbgr_addr_3bytes; /* boolean */
 	union {
 		int i2c_dev_fd;
 		struct usb_endpoint uep;
@@ -162,13 +161,13 @@ struct i2c_interface {
 	int (*send_special_waveform)(struct common_hnd *chnd);
 	/* Required, must not be NULL. */
 	int (*byte_transfer)(struct common_hnd *chnd, uint8_t addr,
-		uint8_t *data, int write, int numbytes);
+			     uint8_t *data, int write, int numbytes);
 	/* Required, must be positive. */
 	int default_block_write_size;
 };
 
-static int spi_flash_command_short(struct common_hnd *chnd,
-				   uint8_t cmd, char *desc);
+static int spi_flash_command_short(struct common_hnd *chnd, uint8_t cmd,
+				   char *desc);
 
 static void null_and_free(void **ptr)
 {
@@ -192,7 +191,7 @@ static void config_release(struct iteflash_config *conf)
 }
 
 /* number of bytes to send consecutively before checking for ACKs */
-#define FTDI_TX_BUFFER_LIMIT	32
+#define FTDI_TX_BUFFER_LIMIT 32
 
 static inline int i2c_byte_transfer(struct common_hnd *chnd, uint8_t addr,
 				    uint8_t *data, int write, int numbytes)
@@ -202,7 +201,7 @@ static inline int i2c_byte_transfer(struct common_hnd *chnd, uint8_t addr,
 		return -1;
 
 	return chnd->conf.i2c_if->byte_transfer(chnd, addr, data, write,
-		numbytes);
+						numbytes);
 }
 
 static int linux_i2c_byte_transfer(struct common_hnd *chnd, uint8_t addr,
@@ -225,8 +224,10 @@ static int linux_i2c_byte_transfer(struct common_hnd *chnd, uint8_t addr,
 	ret = ioctl(chnd->i2c_dev_fd, I2C_RDWR, &msgset);
 	if (ret < 0) {
 		extra_int = errno;
-		fprintf(stderr, "%s: ioctl() failed with return value %d and "
-			"errno %d\n", __func__, ret, extra_int);
+		fprintf(stderr,
+			"%s: ioctl() failed with return value %d and "
+			"errno %d\n",
+			__func__, ret, extra_int);
 		if (ret == -1 && extra_int)
 			ret = -abs(extra_int);
 	} else if (ret < nmsgs) {
@@ -250,12 +251,17 @@ static int i2c_add_send_byte(struct ftdi_context *ftdi, uint8_t *buf,
 
 	for (i = 0; i < tcnt; i++) {
 		/* WORKAROUND: force SDA before sending the next byte */
-		*b++ = SET_BITS_LOW; *b++ = SDA_BIT; *b++ = SCL_BIT | SDA_BIT;
+		*b++ = SET_BITS_LOW;
+		*b++ = SDA_BIT;
+		*b++ = SCL_BIT | SDA_BIT;
 		/* write byte */
 		*b++ = MPSSE_DO_WRITE | MPSSE_BITMODE | MPSSE_WRITE_NEG;
-		*b++ = 0x07; *b++ = *tbuf++;
+		*b++ = 0x07;
+		*b++ = *tbuf++;
 		/* prepare for ACK */
-		*b++ = SET_BITS_LOW; *b++ = 0; *b++ = SCL_BIT;
+		*b++ = SET_BITS_LOW;
+		*b++ = 0;
+		*b++ = SCL_BIT;
 		/* read ACK */
 		*b++ = MPSSE_DO_READ | MPSSE_BITMODE | MPSSE_LSB;
 		*b++ = 0;
@@ -267,7 +273,7 @@ static int i2c_add_send_byte(struct ftdi_context *ftdi, uint8_t *buf,
 		 * On the last byte, or every FTDI_TX_BUFFER_LIMIT bytes, read
 		 * the ACK bits.
 		 */
-		if (i == tcnt-1 || (tx_buffered == FTDI_TX_BUFFER_LIMIT)) {
+		if (i == tcnt - 1 || (tx_buffered == FTDI_TX_BUFFER_LIMIT)) {
 			/* write data */
 			ret = ftdi_write_data(ftdi, buf, b - buf);
 			if (ret < 0) {
@@ -280,7 +286,7 @@ static int i2c_add_send_byte(struct ftdi_context *ftdi, uint8_t *buf,
 			ack_idx = 0;
 			do {
 				ret = ftdi_read_data(ftdi, &ack[ack_idx],
-					remaining_data);
+						     remaining_data);
 				if (ret < 0) {
 					fprintf(stderr, "read ACK failed\n");
 					return ret;
@@ -299,7 +305,7 @@ static int i2c_add_send_byte(struct ftdi_context *ftdi, uint8_t *buf,
 					fprintf(stderr,
 						"write ACK fail: %d, 0x%02x\n",
 						ret, failed_ack);
-				return  -ENXIO;
+				return -ENXIO;
 			}
 
 			/* reset for next set of transactions */
@@ -318,20 +324,32 @@ static int i2c_add_recv_bytes(struct ftdi_context *ftdi, uint8_t *buf,
 
 	for (i = 0; i < rcnt; i++) {
 		/* set SCL low */
-		*b++ = SET_BITS_LOW; *b++ = 0; *b++ = SCL_BIT;
+		*b++ = SET_BITS_LOW;
+		*b++ = 0;
+		*b++ = SCL_BIT;
 		/* read the byte on the wire */
-		*b++ = MPSSE_DO_READ; *b++ = 0; *b++ = 0;
+		*b++ = MPSSE_DO_READ;
+		*b++ = 0;
+		*b++ = 0;
 
 		if (i == rcnt - 1) {
 			/* NACK last byte */
-			*b++ = SET_BITS_LOW; *b++ = 0; *b++ = SCL_BIT;
+			*b++ = SET_BITS_LOW;
+			*b++ = 0;
+			*b++ = SCL_BIT;
 			*b++ = MPSSE_DO_WRITE | MPSSE_BITMODE | MPSSE_WRITE_NEG;
-			*b++ = 0; *b++ = 0xff; *b++ = SEND_IMMEDIATE;
+			*b++ = 0;
+			*b++ = 0xff;
+			*b++ = SEND_IMMEDIATE;
 		} else {
 			/* ACK all other bytes */
-			*b++ = SET_BITS_LOW; *b++ = 0; *b++ = SCL_BIT | SDA_BIT;
+			*b++ = SET_BITS_LOW;
+			*b++ = 0;
+			*b++ = SCL_BIT | SDA_BIT;
 			*b++ = MPSSE_DO_WRITE | MPSSE_BITMODE | MPSSE_WRITE_NEG;
-			*b++ = 0; *b++ = 0; *b++ = SEND_IMMEDIATE;
+			*b++ = 0;
+			*b++ = 0;
+			*b++ = SEND_IMMEDIATE;
 		}
 	}
 
@@ -401,7 +419,7 @@ static int ccd_i2c_byte_transfer(struct common_hnd *chnd, uint8_t addr,
 		write ? sizeof(usb_buffer) : USB_I2C_HEADER_SIZE + extra,
 		usb_buffer, sizeof(usb_buffer), 1, &response_size);
 
-	if (response_size < (USB_I2C_HEADER_SIZE  + (write ? 0 : numbytes))) {
+	if (response_size < (USB_I2C_HEADER_SIZE + (write ? 0 : numbytes))) {
 		fprintf(stderr, "%s: got too few bytes (%zd) in response\n",
 			__func__, response_size);
 		return -1;
@@ -417,8 +435,7 @@ static int ccd_i2c_byte_transfer(struct common_hnd *chnd, uint8_t addr,
 		rv = usb_buffer[1];
 		rv = (rv << 8) + usb_buffer[0];
 
-		fprintf(stderr, "%s: usb i2c error %d\n",
-			__func__,
+		fprintf(stderr, "%s: usb i2c error %d\n", __func__,
 			(((uint16_t)usb_buffer[1]) << 8) + usb_buffer[0]);
 
 		return -rv;
@@ -445,14 +462,26 @@ static int ftdi_i2c_byte_transfer(struct common_hnd *chnd, uint8_t addr,
 
 	/* START condition */
 	/* SCL & SDA high */
-	*b++ = SET_BITS_LOW; *b++ = 0; *b++ = 0;
-	*b++ = SET_BITS_LOW; *b++ = 0; *b++ = 0;
+	*b++ = SET_BITS_LOW;
+	*b++ = 0;
+	*b++ = 0;
+	*b++ = SET_BITS_LOW;
+	*b++ = 0;
+	*b++ = 0;
 	/* SCL high, SDA low */
-	*b++ = SET_BITS_LOW; *b++ = 0; *b++ = SDA_BIT;
-	*b++ = SET_BITS_LOW; *b++ = 0; *b++ = SDA_BIT;
+	*b++ = SET_BITS_LOW;
+	*b++ = 0;
+	*b++ = SDA_BIT;
+	*b++ = SET_BITS_LOW;
+	*b++ = 0;
+	*b++ = SDA_BIT;
 	/* SCL low, SDA low */
-	*b++ = SET_BITS_LOW; *b++ = 0; *b++ = SCL_BIT | SDA_BIT;
-	*b++ = SET_BITS_LOW; *b++ = 0; *b++ = SCL_BIT | SDA_BIT;
+	*b++ = SET_BITS_LOW;
+	*b++ = 0;
+	*b++ = SCL_BIT | SDA_BIT;
+	*b++ = SET_BITS_LOW;
+	*b++ = 0;
+	*b++ = SCL_BIT | SDA_BIT;
 
 	/* send address */
 	slave_addr = (addr << 1) | (write ? 0 : 1);
@@ -467,7 +496,7 @@ static int ftdi_i2c_byte_transfer(struct common_hnd *chnd, uint8_t addr,
 	b = buf;
 	if (write) /* write data */
 		ret = i2c_add_send_byte(ftdi, buf, b, data, numbytes,
-			chnd->conf.debug);
+					chnd->conf.debug);
 	else /* read data */
 		ret = i2c_add_recv_bytes(ftdi, buf, b, data, numbytes);
 
@@ -475,11 +504,19 @@ exit_xfer:
 	b = buf;
 	/* STOP condition */
 	/* SCL high, SDA low */
-	*b++ = SET_BITS_LOW; *b++ = 0; *b++ = SDA_BIT;
-	*b++ = SET_BITS_LOW; *b++ = 0; *b++ = SDA_BIT;
+	*b++ = SET_BITS_LOW;
+	*b++ = 0;
+	*b++ = SDA_BIT;
+	*b++ = SET_BITS_LOW;
+	*b++ = 0;
+	*b++ = SDA_BIT;
 	/* SCL high, SDA high */
-	*b++ = SET_BITS_LOW; *b++ = 0; *b++ = 0;
-	*b++ = SET_BITS_LOW; *b++ = 0; *b++ = 0;
+	*b++ = SET_BITS_LOW;
+	*b++ = 0;
+	*b++ = 0;
+	*b++ = SET_BITS_LOW;
+	*b++ = 0;
+	*b++ = 0;
 
 	rets = ftdi_write_data(ftdi, buf, b - buf);
 	if (rets < 0)
@@ -549,21 +586,16 @@ static int check_flashid(struct common_hnd *chnd)
 {
 	int ret = 0;
 	uint8_t id[16], i;
-	struct cmds commands[] = {
-		{0x07, 0x7f},
-		{0x06, 0xff},
-		{0x04, 0x00},
-		{0x05, 0xfe},
-		{0x08, 0x00},
-		{0x05, 0xfd},
-		{0x08, 0x9f}
-	};
+	struct cmds commands[] = { { 0x07, 0x7f }, { 0x06, 0xff },
+				   { 0x04, 0x00 }, { 0x05, 0xfe },
+				   { 0x08, 0x00 }, { 0x05, 0xfd },
+				   { 0x08, 0x9f } };
 
 	for (i = 0; i < ARRAY_SIZE(commands); i++) {
 		ret = i2c_write_byte(chnd, commands[i].addr, commands[i].cmd);
 		if (ret) {
 			fprintf(stderr, "Flash ID Failed : cmd %x ,data %x\n",
-			commands[i].addr, commands[i].cmd);
+				commands[i].addr, commands[i].cmd);
 			return ret;
 		}
 	}
@@ -595,7 +627,7 @@ static int check_chipid(struct common_hnd *chnd)
 	int ret;
 	uint8_t ver = 0xff;
 	uint32_t id = 0xffff;
-	uint16_t v2[7] = {128, 192, 256, 384, 512, 0, 1024};
+	uint16_t v2[7] = { 128, 192, 256, 384, 512, 0, 1024 };
 	/*
 	 * Chip Version is mapping from bit 3-0
 	 * Flash size is mapping from bit 7-4
@@ -637,7 +669,7 @@ static int check_chipid(struct common_hnd *chnd)
 
 	if ((id & 0xff00) != (CHIP_ID & 0xff00)) {
 		id |= 0xff0000;
-		ret = get_3rd_chip_id_byte(chnd, (uint8_t *)&id+2);
+		ret = get_3rd_chip_id_byte(chnd, (uint8_t *)&id + 2);
 		if (ret < 0)
 			return ret;
 
@@ -657,7 +689,7 @@ static int check_chipid(struct common_hnd *chnd)
 	}
 	/* compute embedded flash size from CHIPVER field */
 	if (chnd->flash_cmd_v2)
-		chnd->flash_size = v2[(ver & 0xF0)>>5] * 1024;
+		chnd->flash_size = v2[(ver & 0xF0) >> 5] * 1024;
 	else
 		chnd->flash_size = (128 + (ver & 0xF0)) * 1024;
 
@@ -667,29 +699,7 @@ static int check_chipid(struct common_hnd *chnd)
 	}
 
 	printf("CHIPID %05x, CHIPVER %02x, Flash size %d kB\n", id, ver,
-		chnd->flash_size / 1024);
-
-	return 0;
-}
-
-/* DBGR Reset */
-static int dbgr_reset(struct common_hnd *chnd, unsigned char val)
-{
-	int ret = 0;
-
-	/* Reset CPU only, and we keep power state until flashing is done. */
-	if (chnd->dbgr_addr_3bytes)
-		ret |= i2c_write_byte(chnd, 0x80, 0xf0);
-
-	ret |= i2c_write_byte(chnd, 0x2f, 0x20);
-	ret |= i2c_write_byte(chnd, 0x2e, 0x06);
-
-	/* Enable the Reset Status by val */
-	ret |= i2c_write_byte(chnd, 0x30, val);
-
-	ret |= i2c_write_byte(chnd, 0x27, 0x80);
-	if (ret < 0)
-		fprintf(stderr, "DBGR RESET FAILED\n");
+	       chnd->flash_size / 1024);
 
 	return 0;
 }
@@ -761,7 +771,7 @@ static int dbgr_disable_protect_path(struct common_hnd *chnd)
 
 	ret |= i2c_write_byte(chnd, 0x2f, 0x20);
 	for (i = 0; i < 32; i++) {
-		ret |= i2c_write_byte(chnd, 0x2e, 0xa0+i);
+		ret |= i2c_write_byte(chnd, 0x2e, 0xa0 + i);
 		ret |= i2c_write_byte(chnd, 0x30, 0);
 	}
 
@@ -800,8 +810,8 @@ static int spi_flash_follow_mode_exit(struct common_hnd *chnd, char *desc)
 
 	ret = (ret ? -EIO : 0);
 	if (ret < 0)
-		fprintf(stderr, "Flash %s exit follow mode FAILED (%d)\n",
-			desc, ret);
+		fprintf(stderr, "Flash %s exit follow mode FAILED (%d)\n", desc,
+			ret);
 
 	return ret;
 }
@@ -821,8 +831,8 @@ static int dbgr_stop_ec(struct common_hnd *chnd)
 }
 
 /* SPI Flash generic command, short version */
-static int spi_flash_command_short(struct common_hnd *chnd,
-				   uint8_t cmd, char *desc)
+static int spi_flash_command_short(struct common_hnd *chnd, uint8_t cmd,
+				   char *desc)
 {
 	int ret = 0;
 
@@ -839,8 +849,8 @@ static int spi_flash_command_short(struct common_hnd *chnd,
 }
 
 /* SPI Flash set erase page */
-static int spi_flash_set_erase_page(struct common_hnd *chnd,
-				    int page, char *desc)
+static int spi_flash_set_erase_page(struct common_hnd *chnd, int page,
+				    char *desc)
 {
 	int ret = 0;
 
@@ -862,7 +872,7 @@ static int spi_poll_busy(struct common_hnd *chnd, char *desc)
 	int ret = -EIO;
 
 	if (spi_flash_command_short(chnd, SPI_CMD_READ_STATUS,
-		"read status for busy bit") < 0) {
+				    "read status for busy bit") < 0) {
 		fprintf(stderr, "Flash %s wait busy cleared FAILED\n", desc);
 		goto failed_read_status;
 	}
@@ -889,7 +899,7 @@ static int spi_check_write_enable(struct common_hnd *chnd, char *desc)
 	int ret = -EIO;
 
 	if (spi_flash_command_short(chnd, SPI_CMD_READ_STATUS,
-		"read status for write enable bit") < 0) {
+				    "read status for write enable bit") < 0) {
 		fprintf(stderr, "Flash %s wait WE FAILED\n", desc);
 		goto failed_read_status;
 	}
@@ -915,12 +925,8 @@ static int ftdi_config_i2c(struct ftdi_context *ftdi)
 	int ret;
 	static const uint16_t divisor =
 		60000000 / (2 * FTDI_I2C_FREQ * 3 / 2 /* 3-phase CLK */) - 1;
-	uint8_t clock_buf[] = {
-		EN_3_PHASE,
-		DIS_DIV_5,
-		TCK_DIVISOR,
-		divisor & 0xff,
-		divisor >> 8};
+	uint8_t clock_buf[] = { EN_3_PHASE, DIS_DIV_5, TCK_DIVISOR,
+				divisor & 0xff, divisor >> 8 };
 
 	ret = ftdi_set_latency_timer(ftdi, 16 /* ms */);
 	if (ret < 0)
@@ -951,7 +957,7 @@ static int ftdi_config_i2c(struct ftdi_context *ftdi)
 
 /* Special waveform definition */
 #define SPECIAL_LEN_USEC 50000ULL /* us */
-#define SPECIAL_FREQ    400000ULL
+#define SPECIAL_FREQ 400000ULL
 
 #define SPECIAL_PATTERN 0x0000020301010302ULL
 #define SPECIAL_PATTERN_SDA_L_SCL_L 0x0000000000000000ULL
@@ -960,7 +966,7 @@ static int ftdi_config_i2c(struct ftdi_context *ftdi)
 #define SPECIAL_PATTERN_SDA_H_SCL_H 0x0303030303030303ULL
 #define TICK_COUNT 24
 
-#define MSEC    1000
+#define MSEC 1000
 #define USEC 1000000
 
 #define SPECIAL_BUFFER_SIZE \
@@ -975,8 +981,8 @@ static int connect_to_ccd_i2c_bridge(struct common_hnd *chnd)
 			CR50_I2C_PROTOCOL, &chnd->uep);
 
 	if (rv) {
-		fprintf(stderr, "%s: usb_findit returned error %d\n",
-			__func__, rv);
+		fprintf(stderr, "%s: usb_findit returned error %d\n", __func__,
+			rv);
 	}
 
 	return rv;
@@ -986,13 +992,11 @@ static int ccd_trigger_special_waveform(struct common_hnd *chnd)
 {
 	uint8_t response[20];
 	size_t rsize;
-	uint8_t req[] = {
-		0, /* Port 0. Might be necessary to modify. */
-		CROS_CMD_ADDR, /* Chrome OS dedicated address. */
-		1,	/* Will send a single byte command. */
-		0,	/* No need to read back anything. */
-		CROS_CMD_ITE_SYNC
-	};
+	uint8_t req[] = { 0, /* Port 0. Might be necessary to modify. */
+			  CROS_CMD_ADDR, /* Chrome OS dedicated address. */
+			  1, /* Will send a single byte command. */
+			  0, /* No need to read back anything. */
+			  CROS_CMD_ITE_SYNC };
 
 	usb_trx(&chnd->uep, req, sizeof(req), response, sizeof(response), 1,
 		&rsize);
@@ -1019,7 +1023,7 @@ static int ftdi_send_special_waveform(struct common_hnd *chnd)
 	int i;
 	uint64_t *wave;
 	struct ftdi_context *ftdi = chnd->ftdi_hnd;
-	uint8_t release_lines[] = {SET_BITS_LOW, 0, 0};
+	uint8_t release_lines[] = { SET_BITS_LOW, 0, 0 };
 
 	wave = malloc(SPECIAL_BUFFER_SIZE);
 	if (!wave) {
@@ -1058,7 +1062,7 @@ static int ftdi_send_special_waveform(struct common_hnd *chnd)
 	usleep(5000);
 
 	/* program each special tick */
-	for (i = 0; i < TICK_COUNT; ) {
+	for (i = 0; i < TICK_COUNT;) {
 		wave[i++] = SPECIAL_PATTERN_SDA_L_SCL_L;
 		wave[i++] = SPECIAL_PATTERN_SDA_H_SCL_L;
 		wave[i++] = SPECIAL_PATTERN_SDA_L_SCL_L;
@@ -1082,7 +1086,7 @@ static int ftdi_send_special_waveform(struct common_hnd *chnd)
 	ftdi_config_i2c(ftdi);
 	ftdi_write_data(ftdi, release_lines, sizeof(release_lines));
 
- free_and_return:
+free_and_return:
 	free(wave);
 	return ret;
 }
@@ -1094,7 +1098,8 @@ static int send_special_waveform(struct common_hnd *chnd)
 	int iterations;
 
 	if (!chnd->conf.i2c_if->send_special_waveform) {
-		fprintf(stderr, "This binary does not support sending the ITE "
+		fprintf(stderr,
+			"This binary does not support sending the ITE "
 			"special waveform with the chosen I2C interface.\n");
 		return -1;
 	}
@@ -1120,7 +1125,7 @@ static int send_special_waveform(struct common_hnd *chnd)
 			ret = -1;
 			if (!(iterations % max_iterations))
 				fprintf(stderr, "!please reset EC if flashing"
-					" sequence is not starting!\n");
+						" sequence is not starting!\n");
 		}
 	} while (ret && (iterations++ < max_iterations));
 
@@ -1133,10 +1138,10 @@ static int send_special_waveform(struct common_hnd *chnd)
 }
 
 static int windex;
-static const char wheel[] = {'|', '/', '-', '\\' };
+static const char wheel[] = { '|', '/', '-', '\\' };
 static void draw_spinner(uint32_t remaining, uint32_t size)
 {
-	int percent = (size - remaining)*100/size;
+	int percent = (size - remaining) * 100 / size;
 	fprintf(stderr, "\r%c%3d%%", wheel[windex++], percent);
 	windex %= sizeof(wheel);
 }
@@ -1151,8 +1156,8 @@ static int spi_send_cmd_fast_read(struct common_hnd *chnd, uint32_t addr)
 	ret = spi_flash_command_short(chnd, SPI_CMD_FAST_READ, "fast read");
 	/* Send address */
 	ret |= i2c_write_byte(chnd, 0x08, ((addr >> 16) & 0xff)); /* addr_h */
-	ret |= i2c_write_byte(chnd, 0x08, ((addr >> 8) & 0xff));  /* addr_m */
-	ret |= i2c_write_byte(chnd, 0x08, (addr & 0xff));         /* addr_l */
+	ret |= i2c_write_byte(chnd, 0x08, ((addr >> 8) & 0xff)); /* addr_m */
+	ret |= i2c_write_byte(chnd, 0x08, (addr & 0xff)); /* addr_l */
 	/* fake byte */
 	ret |= i2c_write_byte(chnd, 0x08, 0x00);
 	/* use i2c block read command */
@@ -1171,8 +1176,10 @@ static int command_read_pages(struct common_hnd *chnd, uint32_t address,
 	int cnt;
 
 	if (address & 0xFF) {
-		fprintf(stderr, "page read requested at non-page boundary: "
-			"0x%X\n", address);
+		fprintf(stderr,
+			"page read requested at non-page boundary: "
+			"0x%X\n",
+			address);
 		return -EINVAL;
 	}
 
@@ -1238,8 +1245,8 @@ static int command_write_pages(struct common_hnd *chnd, uint32_t address,
 		goto failed_write;
 
 	while (remaining) {
-		cnt = (remaining > block_write_size) ?
-			block_write_size : remaining;
+		cnt = (remaining > block_write_size) ? block_write_size :
+						       remaining;
 		addr_H = (address >> 16) & 0xFF;
 		addr_M = (address >> 8) & 0xFF;
 		addr_L = address & 0xFF;
@@ -1248,7 +1255,7 @@ static int command_write_pages(struct common_hnd *chnd, uint32_t address,
 
 		/* Write enable */
 		if (spi_flash_command_short(chnd, SPI_CMD_WRITE_ENABLE,
-			"write enable for AAI write") < 0)
+					    "write enable for AAI write") < 0)
 			goto failed_write;
 
 		/* Check write enable bit */
@@ -1257,7 +1264,7 @@ static int command_write_pages(struct common_hnd *chnd, uint32_t address,
 
 		/* Setup write */
 		if (spi_flash_command_short(chnd, SPI_CMD_WORD_PROGRAM,
-			"AAI write") < 0)
+					    "AAI write") < 0)
 			goto failed_write;
 
 		/* Set eflash page address */
@@ -1266,7 +1273,7 @@ static int command_write_pages(struct common_hnd *chnd, uint32_t address,
 		res |= i2c_byte_transfer(chnd, I2C_DATA_ADDR, &addr_L, 1, 1);
 		if (res < 0) {
 			fprintf(stderr, "Flash write set page FAILED (%d)\n",
-					res);
+				res);
 			goto failed_write;
 		}
 
@@ -1289,13 +1296,13 @@ static int command_write_pages(struct common_hnd *chnd, uint32_t address,
 		res |= i2c_write_byte(chnd, 0x10, 0x00);
 		if (res < 0) {
 			fprintf(stderr, "Flash end data write FAILED (%d)\n",
-					res);
+				res);
 			goto failed_write;
 		}
 
 		/* Write disable */
 		if (spi_flash_command_short(chnd, SPI_CMD_WRITE_DISABLE,
-			"write disable for AAI write") < 0)
+					    "write disable for AAI write") < 0)
 			goto failed_write;
 
 		/* Wait until available */
@@ -1310,7 +1317,7 @@ static int command_write_pages(struct common_hnd *chnd, uint32_t address,
 	res = size;
 failed_write:
 	if (spi_flash_command_short(chnd, SPI_CMD_WRITE_DISABLE,
-		"write disable exit AAI write") < 0)
+				    "write disable exit AAI write") < 0)
 		res = -EIO;
 
 	if (spi_flash_follow_mode_exit(chnd, "AAI write") < 0)
@@ -1330,13 +1337,13 @@ static int command_write_pages3(struct common_hnd *chnd, uint32_t address,
 
 	/* SMB_SPI_Flash_Write_Enable */
 	if (spi_flash_command_short(chnd, SPI_CMD_WRITE_ENABLE,
-		"SPI Command Write Enable") < 0) {
+				    "SPI Command Write Enable") < 0) {
 		ret = -EIO;
 		goto failed_write;
 	}
 
 	if (spi_flash_command_short(chnd, SPI_CMD_PAGE_PROGRAM,
-		"SPI_CMD_PAGE_PROGRAM") < 0) {
+				    "SPI_CMD_PAGE_PROGRAM") < 0) {
 		ret = -EIO;
 		goto failed_write;
 	}
@@ -1361,8 +1368,6 @@ failed_write:
 	return ret;
 }
 
-
-
 static int command_erase(struct common_hnd *chnd, uint32_t len, uint32_t off)
 {
 	int res = -EIO;
@@ -1383,7 +1388,7 @@ static int command_erase(struct common_hnd *chnd, uint32_t len, uint32_t off)
 		draw_spinner(remaining, len);
 
 		if (spi_flash_command_short(chnd, SPI_CMD_WRITE_ENABLE,
-			"write enable for erase") < 0)
+					    "write enable for erase") < 0)
 			goto failed_erase;
 
 		if (spi_check_write_enable(chnd, "erase") < 0)
@@ -1392,28 +1397,28 @@ static int command_erase(struct common_hnd *chnd, uint32_t len, uint32_t off)
 		/* do chip erase */
 		if (remaining == chnd->flash_size) {
 			if (spi_flash_command_short(chnd, SPI_CMD_CHIP_ERASE,
-				"chip erase") < 0)
+						    "chip erase") < 0)
 				goto failed_erase;
 			goto wait_busy_cleared;
 		}
 
 		/* do sector erase */
 		if (spi_flash_command_short(chnd, spi_cmd_sector_erase,
-			"sector erase") < 0)
+					    "sector erase") < 0)
 			goto failed_erase;
 
 		if (spi_flash_set_erase_page(chnd, page, "sector erase") < 0)
 			goto failed_erase;
 
-wait_busy_cleared:
+	wait_busy_cleared:
 		if (spi_poll_busy(chnd, "erase") < 0)
 			goto failed_erase;
 
 		if (spi_flash_command_short(chnd, SPI_CMD_WRITE_DISABLE,
-			"write disable for erase") < 0)
+					    "write disable for erase") < 0)
 			goto failed_erase;
 
-		if (remaining == chnd->flash_size)  {
+		if (remaining == chnd->flash_size) {
 			remaining = 0;
 			draw_spinner(remaining, len);
 		} else {
@@ -1428,7 +1433,7 @@ wait_busy_cleared:
 
 failed_erase:
 	if (spi_flash_command_short(chnd, SPI_CMD_WRITE_DISABLE,
-		"write disable exit erase") < 0)
+				    "write disable exit erase") < 0)
 		res = -EIO;
 
 	if (spi_flash_follow_mode_exit(chnd, "erase") < 0)
@@ -1443,8 +1448,8 @@ failed_erase:
  * reset issue while flash.
  * Add such function to prevent the reset issue.
  */
-static int command_erase2(struct common_hnd *chnd, uint32_t len,
-			  uint32_t off, uint32_t reset)
+static int command_erase2(struct common_hnd *chnd, uint32_t len, uint32_t off,
+			  uint32_t reset)
 {
 	int res = -EIO;
 	int page = 0;
@@ -1468,11 +1473,10 @@ static int command_erase2(struct common_hnd *chnd, uint32_t len,
 		goto failed_erase;
 
 	while (remaining) {
-
 		draw_spinner(remaining, len);
 
 		if (spi_flash_command_short(chnd, SPI_CMD_WRITE_ENABLE,
-			"write enable for erase") < 0)
+					    "write enable for erase") < 0)
 			goto failed_erase;
 
 		if (spi_check_write_enable(chnd, "erase") < 0)
@@ -1480,7 +1484,7 @@ static int command_erase2(struct common_hnd *chnd, uint32_t len,
 
 		/* do sector erase */
 		if (spi_flash_command_short(chnd, spi_cmd_sector_erase,
-			"sector erase") < 0)
+					    "sector erase") < 0)
 			goto failed_erase;
 
 		if (spi_flash_set_erase_page(chnd, page, "sector erase") < 0)
@@ -1490,7 +1494,7 @@ static int command_erase2(struct common_hnd *chnd, uint32_t len,
 			goto failed_erase;
 
 		if (spi_flash_command_short(chnd, SPI_CMD_WRITE_DISABLE,
-			"write disable for erase") < 0)
+					    "write disable for erase") < 0)
 			goto failed_erase;
 
 		if (reset) {
@@ -1501,7 +1505,6 @@ static int command_erase2(struct common_hnd *chnd, uint32_t len,
 		page += sector_erase_pages;
 		remaining -= sector_erase_pages * PAGE_SIZE;
 		draw_spinner(remaining, len);
-
 	}
 
 	/* No error so far */
@@ -1510,7 +1513,7 @@ static int command_erase2(struct common_hnd *chnd, uint32_t len,
 
 failed_erase:
 	if (spi_flash_command_short(chnd, SPI_CMD_WRITE_DISABLE,
-		"write disable exit erase") < 0)
+				    "write disable exit erase") < 0)
 		res = -EIO;
 
 	if (spi_flash_follow_mode_exit(chnd, "erase") < 0)
@@ -1604,8 +1607,10 @@ static int write_flash(struct common_hnd *chnd, const char *filename,
 	}
 	res = fread(buffer, 1, size, hnd);
 	if (res <= 0) {
-		fprintf(stderr, "%s: Failed to read %d bytes from %s with "
-			"ferror() %d\n", __func__, size, filename, ferror(hnd));
+		fprintf(stderr,
+			"%s: Failed to read %d bytes from %s with "
+			"ferror() %d\n",
+			__func__, size, filename, ferror(hnd));
 		free(buffer);
 		fclose(hnd);
 		return -EIO;
@@ -1658,8 +1663,10 @@ static int write_flash2(struct common_hnd *chnd, const char *filename,
 	}
 	res = fread(buffer, 1, size, hnd);
 	if (res <= 0) {
-		fprintf(stderr, "%s: Failed to read %d bytes from %s with "
-			"ferror() %d\n", __func__, size, filename, ferror(hnd));
+		fprintf(stderr,
+			"%s: Failed to read %d bytes from %s with "
+			"ferror() %d\n",
+			__func__, size, filename, ferror(hnd));
 		fclose(hnd);
 		free(buffer);
 		return -EIO;
@@ -1689,7 +1696,8 @@ __send_aai_cmd:
 	ret |= i2c_byte_transfer(chnd, I2C_DATA_ADDR, &addr_l, 1, 1);
 	/* Send first two bytes of buffe */
 	ret |= i2c_byte_transfer(chnd, I2C_DATA_ADDR, &buffer[offset], 1, 1);
-	ret |= i2c_byte_transfer(chnd, I2C_DATA_ADDR, &buffer[offset+1], 1, 1);
+	ret |= i2c_byte_transfer(chnd, I2C_DATA_ADDR, &buffer[offset + 1], 1,
+				 1);
 	/* we had sent two bytes */
 	offset += 2;
 	res -= 2;
@@ -1711,8 +1719,8 @@ __send_aai_cmd:
 			two_bytes_sent = 0;
 			cnt -= 2;
 		}
-		if (i2c_byte_transfer(chnd, I2C_BLOCK_ADDR, &buffer[offset],
-			1, cnt) < 0) {
+		if (i2c_byte_transfer(chnd, I2C_BLOCK_ADDR, &buffer[offset], 1,
+				      cnt) < 0) {
 			ret = -EIO;
 			goto failed_write;
 		}
@@ -1728,7 +1736,7 @@ __send_aai_cmd:
 			i2c_write_byte(chnd, 0x10, 0x00);
 			/* write disable command */
 			spi_flash_command_short(chnd, SPI_CMD_WRITE_DISABLE,
-				"SPI write disable");
+						"SPI write disable");
 			goto __send_aai_cmd;
 		}
 	}
@@ -1739,7 +1747,7 @@ failed_write:
 	i2c_write_byte(chnd, 0x10, 0x00);
 	/* write disable command */
 	spi_flash_command_short(chnd, SPI_CMD_WRITE_DISABLE,
-		"SPI write disable");
+				"SPI write disable");
 failed_enter_mode:
 	/* exit follow mode */
 	spi_flash_follow_mode_exit(chnd, "AAI write");
@@ -1786,8 +1794,10 @@ static int write_flash3(struct common_hnd *chnd, const char *filename,
 	}
 	res = fread(buf, 1, size, hnd);
 	if (res <= 0) {
-		fprintf(stderr, "%s: Failed to read %d bytes from %s with "
-			"ferror() %d\n", __func__, size, filename, ferror(hnd));
+		fprintf(stderr,
+			"%s: Failed to read %d bytes from %s with "
+			"ferror() %d\n",
+			__func__, size, filename, ferror(hnd));
 		fclose(hnd);
 		free(buf);
 		return -EIO;
@@ -1809,8 +1819,8 @@ static int write_flash3(struct common_hnd *chnd, const char *filename,
 		cnt = (res > block_write_size) ? block_write_size : res;
 		if (chnd->conf.erase && is_empty_page(&buf[offset], cnt)) {
 			/* do nothing */
-		} else if (command_write_pages3(chnd, offset, cnt, &buf[offset])
-				< 0) {
+		} else if (command_write_pages3(chnd, offset, cnt,
+						&buf[offset]) < 0) {
 			ret = -EIO;
 			goto failed_write;
 		}
@@ -1823,7 +1833,7 @@ static int write_flash3(struct common_hnd *chnd, const char *filename,
 failed_write:
 	free(buf);
 	spi_flash_command_short(chnd, SPI_CMD_WRITE_DISABLE,
-		"SPI write disable");
+				"SPI write disable");
 	spi_flash_follow_mode_exit(chnd, "Page program");
 	if (ret < 0)
 		fprintf(stderr, "%s: Error writing to flash\n", __func__);
@@ -1833,8 +1843,6 @@ failed_write:
 	return ret;
 }
 
-
-
 /* Return zero on success, a non-zero value on failures. */
 static int verify_flash(struct common_hnd *chnd, const char *filename,
 			uint32_t offset)
@@ -1842,7 +1850,7 @@ static int verify_flash(struct common_hnd *chnd, const char *filename,
 	int res;
 	int file_size;
 	FILE *hnd;
-	uint8_t *buffer  = malloc(chnd->flash_size);
+	uint8_t *buffer = malloc(chnd->flash_size);
 	uint8_t *buffer2 = malloc(chnd->flash_size);
 
 	if (!buffer || !buffer2) {
@@ -1863,9 +1871,10 @@ static int verify_flash(struct common_hnd *chnd, const char *filename,
 
 	file_size = fread(buffer, 1, chnd->flash_size, hnd);
 	if (file_size <= 0) {
-		fprintf(stderr, "%s: Failed to read %d bytes from %s with "
-			"ferror() %d\n", __func__, chnd->flash_size, filename,
-			ferror(hnd));
+		fprintf(stderr,
+			"%s: Failed to read %d bytes from %s with "
+			"ferror() %d\n",
+			__func__, chnd->flash_size, filename, ferror(hnd));
 		fclose(hnd);
 		res = -EIO;
 		goto exit;
@@ -1885,8 +1894,8 @@ exit:
 	return res;
 }
 
-static struct ftdi_context *open_ftdi_device(int vid, int pid,
-					     int interface, const char *serial)
+static struct ftdi_context *open_ftdi_device(int vid, int pid, int interface,
+					     const char *serial)
 {
 	struct ftdi_context *ftdi;
 	int ret;
@@ -1926,17 +1935,19 @@ static int linux_i2c_interface_init(struct common_hnd *chnd)
 		return -1;
 	}
 	printf("Attempting to open Linux i2c-dev path %s\n",
-		chnd->conf.i2c_dev_path);
+	       chnd->conf.i2c_dev_path);
 	chnd->i2c_dev_fd = open(chnd->conf.i2c_dev_path, O_RDWR);
 	if (chnd->i2c_dev_fd < 0) {
 		err = errno;
 		perror("Failed to open Linux i2c-dev file path with error");
-		fprintf(stderr, "Linux i2c-dev file path from --i2c_dev_path "
-			"is: %s\n", chnd->conf.i2c_dev_path);
+		fprintf(stderr,
+			"Linux i2c-dev file path from --i2c_dev_path "
+			"is: %s\n",
+			chnd->conf.i2c_dev_path);
 		return err ? err : -1;
 	}
 	printf("Successfully opened Linux i2c-dev path %s\n",
-		chnd->conf.i2c_dev_path);
+	       chnd->conf.i2c_dev_path);
 	return 0;
 }
 
@@ -1945,15 +1956,15 @@ static int linux_i2c_interface_shutdown(struct common_hnd *chnd)
 	int err;
 
 	printf("Attempting to close Linux i2c-dev file descriptor %d\n",
-		chnd->i2c_dev_fd);
+	       chnd->i2c_dev_fd);
 	if (close(chnd->i2c_dev_fd)) {
 		err = errno;
 		perror("Failed to close Linux i2c-dev file descriptor with "
-			"error");
+		       "error");
 		return err ? err : -1;
 	}
 	printf("Successfully closed Linux i2c-dev file descriptor %d\n",
-		chnd->i2c_dev_fd);
+	       chnd->i2c_dev_fd);
 	return 0;
 }
 
@@ -1973,8 +1984,9 @@ static int ccd_i2c_interface_shutdown(struct common_hnd *chnd)
 static int ftdi_i2c_interface_init(struct common_hnd *chnd)
 {
 	chnd->ftdi_hnd = open_ftdi_device(chnd->conf.usb_vid,
-		chnd->conf.usb_pid, chnd->conf.usb_interface,
-		chnd->conf.usb_serial);
+					  chnd->conf.usb_pid,
+					  chnd->conf.usb_interface,
+					  chnd->conf.usb_serial);
 	if (chnd->ftdi_hnd == NULL)
 		return -1;
 	return 0;
@@ -2067,31 +2079,31 @@ static int strdup_with_errmsg(const char *source, char **dest, const char *name)
 	return ret;
 }
 
-static const struct option longopts[] = {
-	{"block-write-size", 1, 0, 'b'},
-	{"debug", 0, 0, 'd'},
-	{"erase", 0, 0, 'e'},
-	{"help", 0, 0, 'h'},
-	{"i2c-dev-path", 1, 0, 'D'},
-	{"i2c-interface", 1, 0, 'c'},
-	{"i2c-mux", 0, 0, 'm'},
-	{"interface", 1, 0, 'i'},
-	{"nodisable-protect-path", 0, 0, 'Z'},
-	{"nodisable-watchdog", 0, 0, 'z'},
-	{"noverify", 0, 0, 'n'},
-	{"product", 1, 0, 'p'},
-	{"range", 1, 0, 'R'},
-	{"read", 1, 0, 'r'},
-	{"send-waveform", 1, 0, 'W'},
-	{"serial", 1, 0, 's'},
-	{"vendor", 1, 0, 'v'},
-	{"write", 1, 0, 'w'},
-	{NULL, 0, 0, 0}
-};
+static const struct option longopts[] = { { "block-write-size", 1, 0, 'b' },
+					  { "debug", 0, 0, 'd' },
+					  { "erase", 0, 0, 'e' },
+					  { "help", 0, 0, 'h' },
+					  { "i2c-dev-path", 1, 0, 'D' },
+					  { "i2c-interface", 1, 0, 'c' },
+					  { "i2c-mux", 0, 0, 'm' },
+					  { "interface", 1, 0, 'i' },
+					  { "nodisable-protect-path", 0, 0,
+					    'Z' },
+					  { "nodisable-watchdog", 0, 0, 'z' },
+					  { "noverify", 0, 0, 'n' },
+					  { "product", 1, 0, 'p' },
+					  { "range", 1, 0, 'R' },
+					  { "read", 1, 0, 'r' },
+					  { "send-waveform", 1, 0, 'W' },
+					  { "serial", 1, 0, 's' },
+					  { "vendor", 1, 0, 'v' },
+					  { "write", 1, 0, 'w' },
+					  { NULL, 0, 0, 0 } };
 
 static void display_usage(const char *program)
 {
-	fprintf(stderr, "Usage: %s [-d] [-v <VID>] [-p <PID>] \\\n"
+	fprintf(stderr,
+		"Usage: %s [-d] [-v <VID>] [-p <PID>] \\\n"
 		"\t[-c <linux|ccd|ftdi>] [-D /dev/i2c-<N>] [-i <1|2>] [-S] \\\n"
 		"\t[-s <serial>] [-e] [-r <file>] [-W <0|1|false|true>] \\\n"
 		"\t[-w <file>] [-R base[:size]] [-m] [-b <size>]\n",
@@ -2105,14 +2117,16 @@ static void display_usage(const char *program)
 			"\tonly applicable with --i2c-interface=linux\n");
 	fprintf(stderr, "-i, --interface <1> : FTDI interface: A=1, B=2,"
 			" ...\n");
-	fprintf(stderr, "-m, --i2c-mux : Enable i2c-mux (to EC).\n"
+	fprintf(stderr,
+		"-m, --i2c-mux : Enable i2c-mux (to EC).\n"
 		"\tSpecify this flag only if the board has an I2C MUX and\n"
 		"\tyou are not using servod.\n");
 	fprintf(stderr, "-n, --noverify : Don't auto verify.\n");
 	fprintf(stderr, "-b, --block-write-size <size> : Perform writes in\n"
-		"\tblocks of this many bytes.\n");
+			"\tblocks of this many bytes.\n");
 	fprintf(stderr, "-p, --product <0x1234> : USB product ID\n");
-	fprintf(stderr, "-R, --range base[:size] : Allow to read or write"
+	fprintf(stderr,
+		"-R, --range base[:size] : Allow to read or write"
 		" just a slice\n"
 		"\tof the file, starting at <base>:<size> bytes, or til\n"
 		"\tthe end of the file if <size> is not specified, expressed\n"
@@ -2121,15 +2135,16 @@ static void display_usage(const char *program)
 			" write it into <file>.\n");
 	fprintf(stderr, "-s, --serial <serialname> : USB serial string\n");
 	fprintf(stderr, "-v, --vendor <0x1234> : USB vendor ID\n");
-	fprintf(stderr, "-W, --send-waveform <0|1|false|true> : Send the"
+	fprintf(stderr,
+		"-W, --send-waveform <0|1|false|true> : Send the"
 		" special waveform.\n"
 		"\tDefault is true. Set to false if ITE direct firmware\n"
 		"\tupdate mode has already been enabled.\n");
 	fprintf(stderr, "-w, --write <file> : Write <file> to flash.\n");
 	fprintf(stderr, "-z, --nodisable-watchdog : Do *not* disable EC "
-		"watchdog.\n");
+			"watchdog.\n");
 	fprintf(stderr, "-Z, --nodisable-protect-path : Do *not* disable EC "
-		"protect path.\n");
+			"protect path.\n");
 }
 
 /*
@@ -2141,7 +2156,7 @@ static int parse_range_options(char *str, struct iteflash_config *conf)
 	char *size;
 
 	if (!str) {
-		fprintf(stderr,	"missing range base address specification\n");
+		fprintf(stderr, "missing range base address specification\n");
 		return -1;
 	}
 
@@ -2187,14 +2202,16 @@ static int parse_parameters(int argc, char **argv, struct iteflash_config *conf)
 			} else if (!strcasecmp(optarg, "ftdi")) {
 				conf->i2c_if = &ftdi_i2c_interface;
 			} else {
-				fprintf(stderr, "Unexpected -c / "
-					"--i2c-interface value: %s\n", optarg);
+				fprintf(stderr,
+					"Unexpected -c / "
+					"--i2c-interface value: %s\n",
+					optarg);
 				ret = -1;
 			}
 			break;
 		case 'D':
 			ret = strdup_with_errmsg(optarg, &conf->i2c_dev_path,
-				"-D / --i2c-dev-path");
+						 "-D / --i2c-dev-path");
 			break;
 		case 'd':
 			conf->debug = 1;
@@ -2224,11 +2241,11 @@ static int parse_parameters(int argc, char **argv, struct iteflash_config *conf)
 			break;
 		case 'r':
 			ret = strdup_with_errmsg(optarg, &conf->input_filename,
-				"-r / --read");
+						 "-r / --read");
 			break;
 		case 's':
 			ret = strdup_with_errmsg(optarg, &conf->usb_serial,
-				"-s / --serial");
+						 "-s / --serial");
 			break;
 		case 'v':
 			conf->usb_vid = strtol(optarg, NULL, 16);
@@ -2244,13 +2261,15 @@ static int parse_parameters(int argc, char **argv, struct iteflash_config *conf)
 				conf->send_waveform = 1;
 				break;
 			}
-			fprintf(stderr, "Unexpected -W / --special-waveform "
-				"value: %s\n", optarg);
+			fprintf(stderr,
+				"Unexpected -W / --special-waveform "
+				"value: %s\n",
+				optarg);
 			ret = -1;
 			break;
 		case 'w':
 			ret = strdup_with_errmsg(optarg, &conf->output_filename,
-				"-w / --write");
+						 "-w / --write");
 			break;
 		case 'z':
 			conf->disable_watchdog = 0;
@@ -2269,8 +2288,8 @@ static int parse_parameters(int argc, char **argv, struct iteflash_config *conf)
 static void sighandler(int signum)
 {
 	int status;
-	printf("\nCaught signal %d: %s\nExiting...\n",
-		signum, strsignal(signum));
+	printf("\nCaught signal %d: %s\nExiting...\n", signum,
+	       strsignal(signum));
 	wait(&status);
 	exit_requested = status;
 }
@@ -2340,7 +2359,8 @@ int main(int argc, char **argv)
 
 		ret = check_chipid(&chnd);
 		if (ret) {
-			fprintf(stderr, "Failed to get ITE chip ID.  This "
+			fprintf(stderr,
+				"Failed to get ITE chip ID.  This "
 				"could be because the ITE direct firmware "
 				"update (DFU) mode is not enabled.\n");
 			goto return_after_init;
@@ -2386,20 +2406,18 @@ int main(int argc, char **argv)
 			command_erase2(&chnd, chnd.flash_size, 0, 0);
 		else
 			command_erase(&chnd, chnd.flash_size, 0);
-		/* Call DBGR Rest to clear the EC lock status after erasing */
-		dbgr_reset(&chnd, RSTS_VCCDO_PW_ON|RSTS_HGRST|RSTS_GRST);
 	}
 
 	if (chnd.conf.output_filename) {
 		if (chnd.flash_cmd_v2)
 			switch (eflash_type) {
 			case EFLASH_TYPE_8315:
-				ret = write_flash2(&chnd,
-					chnd.conf.output_filename, 0);
+				ret = write_flash2(
+					&chnd, chnd.conf.output_filename, 0);
 				break;
 			case EFLASH_TYPE_KGD:
-				ret = write_flash3(&chnd,
-					chnd.conf.output_filename, 0);
+				ret = write_flash3(
+					&chnd, chnd.conf.output_filename, 0);
 				break;
 			default:
 				printf("Invalid EFLASH TYPE!");
@@ -2420,7 +2438,7 @@ int main(int argc, char **argv)
 	/* Normal exit */
 	ret = 0;
 
- return_after_init:
+return_after_init:
 	/*
 	 * Exit DBGR mode. This ensures EC won't hold clock/data pins of I2C.
 	 * Avoid resetting EC here because flash_ec will after iteflash exits.
@@ -2439,7 +2457,7 @@ int main(int argc, char **argv)
 			ret = other_ret;
 	}
 
- return_after_parse:
+return_after_parse:
 	config_release(&chnd.conf);
 	return ret;
 }
diff --git a/util/iteflash.md b/util/iteflash.md
index 68f7600d74..d85d99013a 100644
--- a/util/iteflash.md
+++ b/util/iteflash.md
@@ -6,8 +6,8 @@ First written: 2019-04-02
 <br>
 Last updated: 2019-04-03
 
-Familiarity with [Chromium OS](https://www.chromium.org/chromium-os)
-[Embedded Controller (EC) development](../README.md) is assumed.
+Familiarity with [Chromium OS](https://www.chromium.org/chromium-os) and
+[Embedded Controller (EC)](../README.md) development is assumed.
 
 [TOC]
 
@@ -48,9 +48,10 @@ An ITE EC is reflashed using a Servo by:
 
 ### Further reading
 
-Googlers, and Partners involved in ITE EC projects, see
-[The State of ITE CrOS EC Reflashing](https://docs.google.com/document/d/1fs29eBvwKrOWYozLZXTg7ObwAO5dyM4Js2Vq301EwAU/preview).
-That document is not public, do not request access if you lack it.
+* [ITE EC firmware reflashing via Servo: How it works](../docs/ite-ec-reflashing.md)
+* Googlers, and Partners involved in ITE EC projects *only*:
+[The State of ITE CrOS EC Reflashing](https://docs.google.com/document/d/1fs29eBvwKrOWYozLZXTg7ObwAO5dyM4Js2Vq301EwAU/preview)
+  * That document is not public, do not request access if you lack it.
 
 ## How to reflash
 
diff --git a/util/kconfig_check.py b/util/kconfig_check.py
index d1eba8e62b..e745b3aeca 100755
--- a/util/kconfig_check.py
+++ b/util/kconfig_check.py
@@ -1,5 +1,5 @@
 #!/usr/bin/env python3
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 """Kconfig checker
@@ -25,6 +25,7 @@ import os
 import pathlib
 import re
 import sys
+import traceback
 
 # Try to use kconfiglib if available, but fall back to a simple recursive grep.
 # This is used by U-Boot in some situations so we keep it to avoid forking this
@@ -32,12 +33,13 @@ import sys
 USE_KCONFIGLIB = False
 try:
     import kconfiglib
+
     USE_KCONFIGLIB = True
 except ImportError:
     pass
 
 # Where we put the new config_allowed file
-NEW_ALLOWED_FNAME = pathlib.Path('/tmp/new_config_allowed.txt')
+NEW_ALLOWED_FNAME = pathlib.Path("/tmp/new_config_allowed.txt")
 
 
 def parse_args(argv):
@@ -49,38 +51,72 @@ def parse_args(argv):
     Returns:
         argparse.Namespace object containing the results
     """
-    epilog = '''Checks that new ad-hoc CONFIG options are not introduced without
-a corresponding Kconfig option for Zephyr'''
+    epilog = """Checks that new ad-hoc CONFIG options are not introduced without
+a corresponding Kconfig option for Zephyr"""
 
     parser = argparse.ArgumentParser(epilog=epilog)
-    parser.add_argument('-a', '--allowed', type=str,
-                        default='util/config_allowed.txt',
-                        help='File containing list of allowed ad-hoc CONFIGs')
-    parser.add_argument('-c', '--configs', type=str, default='.config',
-                        help='File containing CONFIG options to check')
-    parser.add_argument('-d', '--use-defines', action='store_true',
-                        help='Lines in the configs file use #define')
     parser.add_argument(
-        '-D', '--debug', action='store_true',
-        help='Enabling debugging (provides a full traceback on error)')
+        "-a",
+        "--allowed",
+        type=str,
+        default="util/config_allowed.txt",
+        help="File containing list of allowed ad-hoc CONFIGs",
+    )
+    parser.add_argument(
+        "-c",
+        "--configs",
+        type=str,
+        default=".config",
+        help="File containing CONFIG options to check",
+    )
+    parser.add_argument(
+        "-d",
+        "--use-defines",
+        action="store_true",
+        help="Lines in the configs file use #define",
+    )
+    parser.add_argument(
+        "-D",
+        "--debug",
+        action="store_true",
+        help="Enabling debugging (provides a full traceback on error)",
+    )
+    parser.add_argument(
+        "-i",
+        "--ignore",
+        action="append",
+        help="Kconfig options to ignore (without CONFIG_ prefix)",
+    )
     parser.add_argument(
-        '-i', '--ignore', action='append',
-        help='Kconfig options to ignore (without CONFIG_ prefix)')
-    parser.add_argument('-I', '--search-path', type=str, action='append',
-                        help='Search paths to look for Kconfigs')
-    parser.add_argument('-p', '--prefix', type=str, default='PLATFORM_EC_',
-                        help='Prefix to string from Kconfig options')
-    parser.add_argument('-s', '--srctree', type=str, default='zephyr/',
-                        help='Path to source tree to look for Kconfigs')
+        "-I",
+        "--search-path",
+        type=str,
+        action="append",
+        help="Search paths to look for Kconfigs",
+    )
+    parser.add_argument(
+        "-p",
+        "--prefix",
+        type=str,
+        default="PLATFORM_EC_",
+        help="Prefix to string from Kconfig options",
+    )
+    parser.add_argument(
+        "-s",
+        "--srctree",
+        type=str,
+        default="zephyr/",
+        help="Path to source tree to look for Kconfigs",
+    )
 
     # TODO(sjg@chromium.org): The chroot uses a very old Python. Once it moves
     # to 3.7 or later we can use this instead:
     #    subparsers = parser.add_subparsers(dest='cmd', required=True)
-    subparsers = parser.add_subparsers(dest='cmd')
+    subparsers = parser.add_subparsers(dest="cmd")
     subparsers.required = True
 
-    subparsers.add_parser('build', help='Build new list of ad-hoc CONFIGs')
-    subparsers.add_parser('check', help='Check for new ad-hoc CONFIGs')
+    subparsers.add_parser("build", help="Build new list of ad-hoc CONFIGs")
+    subparsers.add_parser("check", help="Check for new ad-hoc CONFIGs")
 
     return parser.parse_args(argv)
 
@@ -107,6 +143,7 @@ class KconfigCheck:
     the user is exhorted to add a new Kconfig. This helps avoid adding new ad-hoc
     CONFIG options, eventually returning the number to zero.
     """
+
     @classmethod
     def find_new_adhoc(cls, configs, kconfigs, allowed):
         """Get a list of new ad-hoc CONFIG options
@@ -172,11 +209,15 @@ class KconfigCheck:
             List of CONFIG_xxx options found in the file, with the 'CONFIG_'
                 prefix removed
         """
-        with open(configs_file, 'r') as inf:
-            configs = re.findall('%sCONFIG_([A-Za-z0-9_]*)%s' %
-                                 ((use_defines and '#define ' or ''),
-                                  (use_defines and ' ' or '')),
-                                 inf.read())
+        with open(configs_file, "r") as inf:
+            configs = re.findall(
+                "%sCONFIG_([A-Za-z0-9_]*)%s"
+                % (
+                    (use_defines and "#define " or ""),
+                    (use_defines and " " or ""),
+                ),
+                inf.read(),
+            )
         return configs
 
     @classmethod
@@ -190,8 +231,8 @@ class KconfigCheck:
             List of CONFIG_xxx options found in the file, with the 'CONFIG_'
                 prefix removed
         """
-        with open(allowed_file, 'r') as inf:
-            configs = re.findall('CONFIG_([A-Za-z0-9_]*)', inf.read())
+        with open(allowed_file, "r") as inf:
+            configs = re.findall("CONFIG_([A-Za-z0-9_]*)", inf.read())
         return configs
 
     @classmethod
@@ -209,15 +250,27 @@ class KconfigCheck:
         """
         kconfig_files = []
         for root, dirs, files in os.walk(srcdir):
-            kconfig_files += [os.path.join(root, fname)
-                              for fname in files if fname.startswith('Kconfig')]
-            if 'Kconfig' in dirs:
-                dirs.remove('Kconfig')
+            kconfig_files += [
+                os.path.join(root, fname)
+                for fname in files
+                if fname.startswith("Kconfig")
+            ]
+            if "Kconfig" in dirs:
+                dirs.remove("Kconfig")
+            if "boards" in dirs:
+                dirs.remove("boards")
+            if "projects" in dirs:
+                dirs.remove("projects")
+            if "test" in dirs:
+                dirs.remove("test")
+            if "chip" in dirs:
+                dirs.remove("chip")
         return kconfig_files
 
     @classmethod
-    def scan_kconfigs(cls, srcdir, prefix='', search_paths=None,
-                      try_kconfiglib=True):
+    def scan_kconfigs(
+        cls, srcdir, prefix="", search_paths=None, try_kconfiglib=True
+    ):
         """Scan a source tree for Kconfig options
 
         Args:
@@ -231,31 +284,42 @@ class KconfigCheck:
             List of config and menuconfig options found
         """
         if USE_KCONFIGLIB and try_kconfiglib:
-            os.environ['srctree'] = srcdir
-            kconf = kconfiglib.Kconfig('Kconfig', warn=False,
-                                       search_paths=search_paths,
-                                       allow_empty_macros=True)
+            os.environ["srctree"] = srcdir
+            kconf = kconfiglib.Kconfig(
+                "Kconfig",
+                warn=False,
+                search_paths=search_paths,
+                allow_empty_macros=True,
+            )
 
             # There is always a MODULES config, since kconfiglib is designed for
             # linux, but we don't want it
-            kconfigs = [name for name in kconf.syms if name != 'MODULES']
+            kconfigs = [name for name in kconf.syms if name != "MODULES"]
 
             if prefix:
-                re_drop_prefix = re.compile(r'^%s' % prefix)
-                kconfigs = [re_drop_prefix.sub('', name) for name in kconfigs]
+                re_drop_prefix = re.compile(r"^%s" % prefix)
+                kconfigs = [re_drop_prefix.sub("", name) for name in kconfigs]
         else:
             kconfigs = []
             # Remove the prefix if present
-            expr = re.compile(r'\n(config|menuconfig) (%s)?([A-Za-z0-9_]*)\n' %
-                              prefix)
+            expr = re.compile(
+                r"\n(config|menuconfig) (%s)?([A-Za-z0-9_]*)\n" % prefix
+            )
             for fname in cls.find_kconfigs(srcdir):
                 with open(fname) as inf:
                     found = re.findall(expr, inf.read())
                     kconfigs += [name for kctype, _, name in found]
         return sorted(kconfigs)
 
-    def check_adhoc_configs(self, configs_file, srcdir, allowed_file,
-                            prefix='', use_defines=False, search_paths=None):
+    def check_adhoc_configs(
+        self,
+        configs_file,
+        srcdir,
+        allowed_file,
+        prefix="",
+        use_defines=False,
+        search_paths=None,
+    ):
         """Find new and unneeded ad-hoc configs in the configs_file
 
         Args:
@@ -283,8 +347,11 @@ class KconfigCheck:
         except kconfiglib.KconfigError:
             # If we don't actually have access to the full Kconfig then we may
             # get an error. Fall back to using manual methods.
-            kconfigs = self.scan_kconfigs(srcdir, prefix, search_paths,
-                                          try_kconfiglib=False)
+            print("WARNING: kconfiglib failed", file=sys.stderr)
+            traceback.print_exc()
+            kconfigs = self.scan_kconfigs(
+                srcdir, prefix, search_paths, try_kconfiglib=False
+            )
 
         allowed = self.read_allowed(allowed_file)
         new_adhoc = self.find_new_adhoc(configs, kconfigs, allowed)
@@ -292,8 +359,16 @@ class KconfigCheck:
         updated_adhoc = self.get_updated_adhoc(unneeded_adhoc, allowed)
         return new_adhoc, unneeded_adhoc, updated_adhoc
 
-    def do_check(self, configs_file, srcdir, allowed_file, prefix, use_defines,
-                 search_paths, ignore=None):
+    def do_check(
+        self,
+        configs_file,
+        srcdir,
+        allowed_file,
+        prefix,
+        use_defines,
+        search_paths,
+        ignore=None,
+    ):
         """Find new ad-hoc configs in the configs_file
 
         Args:
@@ -313,11 +388,17 @@ class KconfigCheck:
             Exit code: 0 if OK, 1 if a problem was found
         """
         new_adhoc, unneeded_adhoc, updated_adhoc = self.check_adhoc_configs(
-            configs_file, srcdir, allowed_file, prefix, use_defines,
-            search_paths)
+            configs_file,
+            srcdir,
+            allowed_file,
+            prefix,
+            use_defines,
+            search_paths,
+        )
         if new_adhoc:
-            file_list = '\n'.join(['CONFIG_%s' % name for name in new_adhoc])
-            print(f'''Error:\tThe EC is in the process of migrating to Zephyr.
+            file_list = "\n".join(["CONFIG_%s" % name for name in new_adhoc])
+            print(
+                f"""Error:\tThe EC is in the process of migrating to Zephyr.
 \tZephyr uses Kconfig for configuration rather than ad-hoc #defines.
 \tAny new EC CONFIG options must ALSO be added to Zephyr so that new
 \tfunctionality is available in Zephyr also. The following new ad-hoc
@@ -330,19 +411,23 @@ file in zephyr/ and add a 'config' or 'menuconfig' option.
 Also see details in http://issuetracker.google.com/181253613
 
 To temporarily disable this, use: ALLOW_CONFIG=1 make ...
-''', file=sys.stderr)
+""",
+                file=sys.stderr,
+            )
             return 1
 
         if not ignore:
             ignore = []
         unneeded_adhoc = [name for name in unneeded_adhoc if name not in ignore]
         if unneeded_adhoc:
-            with open(NEW_ALLOWED_FNAME, 'w') as out:
+            with open(NEW_ALLOWED_FNAME, "w") as out:
                 for config in updated_adhoc:
-                    print('CONFIG_%s' % config, file=out)
-            now_in_kconfig = '\n'.join(
-                ['CONFIG_%s' % name for name in unneeded_adhoc])
-            print(f'''The following options are now in Kconfig:
+                    print("CONFIG_%s" % config, file=out)
+            now_in_kconfig = "\n".join(
+                ["CONFIG_%s" % name for name in unneeded_adhoc]
+            )
+            print(
+                f"""The following options are now in Kconfig:
 
 {now_in_kconfig}
 
@@ -350,12 +435,20 @@ Please run this to update the list of allowed ad-hoc CONFIGs and include this
 update in your CL:
 
    cp {NEW_ALLOWED_FNAME} util/config_allowed.txt
-''')
+"""
+            )
             return 1
         return 0
 
-    def do_build(self, configs_file, srcdir, allowed_file, prefix, use_defines,
-                 search_paths):
+    def do_build(
+        self,
+        configs_file,
+        srcdir,
+        allowed_file,
+        prefix,
+        use_defines,
+        search_paths,
+    ):
         """Find new ad-hoc configs in the configs_file
 
         Args:
@@ -372,13 +465,19 @@ update in your CL:
             Exit code: 0 if OK, 1 if a problem was found
         """
         new_adhoc, _, updated_adhoc = self.check_adhoc_configs(
-            configs_file, srcdir, allowed_file, prefix, use_defines,
-            search_paths)
-        with open(NEW_ALLOWED_FNAME, 'w') as out:
+            configs_file,
+            srcdir,
+            allowed_file,
+            prefix,
+            use_defines,
+            search_paths,
+        )
+        with open(NEW_ALLOWED_FNAME, "w") as out:
             combined = sorted(new_adhoc + updated_adhoc)
             for config in combined:
-                print(f'CONFIG_{config}', file=out)
-        print(f'New list is in {NEW_ALLOWED_FNAME}')
+                print(f"CONFIG_{config}", file=out)
+        print(f"New list is in {NEW_ALLOWED_FNAME}")
+
 
 def main(argv):
     """Main function"""
@@ -386,18 +485,27 @@ def main(argv):
     if not args.debug:
         sys.tracebacklimit = 0
     checker = KconfigCheck()
-    if args.cmd == 'check':
+    if args.cmd == "check":
         return checker.do_check(
-            configs_file=args.configs, srcdir=args.srctree,
-            allowed_file=args.allowed, prefix=args.prefix,
-            use_defines=args.use_defines, search_paths=args.search_path,
-            ignore=args.ignore)
-    elif args.cmd == 'build':
-        return checker.do_build(configs_file=args.configs, srcdir=args.srctree,
-            allowed_file=args.allowed, prefix=args.prefix,
-            use_defines=args.use_defines, search_paths=args.search_path)
+            configs_file=args.configs,
+            srcdir=args.srctree,
+            allowed_file=args.allowed,
+            prefix=args.prefix,
+            use_defines=args.use_defines,
+            search_paths=args.search_path,
+            ignore=args.ignore,
+        )
+    if args.cmd == "build":
+        return checker.do_build(
+            configs_file=args.configs,
+            srcdir=args.srctree,
+            allowed_file=args.allowed,
+            prefix=args.prefix,
+            use_defines=args.use_defines,
+            search_paths=args.search_path,
+        )
     return 2
 
 
-if __name__ == '__main__':
+if __name__ == "__main__":
     sys.exit(main(sys.argv[1:]))
diff --git a/util/kconfiglib.py b/util/kconfiglib.py
deleted file mode 100644
index 0e05aaaeac..0000000000
--- a/util/kconfiglib.py
+++ /dev/null
@@ -1,7196 +0,0 @@
-# Copyright (c) 2011-2019, Ulf Magnusson
-# SPDX-License-Identifier: ISC
-
-"""
-Overview
-========
-
-Kconfiglib is a Python 2/3 library for scripting and extracting information
-from Kconfig (https://www.kernel.org/doc/Documentation/kbuild/kconfig-language.txt)
-configuration systems.
-
-See the homepage at https://github.com/ulfalizer/Kconfiglib for a longer
-overview.
-
-Since Kconfiglib 12.0.0, the library version is available in
-kconfiglib.VERSION, which is a (<major>, <minor>, <patch>) tuple, e.g.
-(12, 0, 0).
-
-
-Using Kconfiglib on the Linux kernel with the Makefile targets
-==============================================================
-
-For the Linux kernel, a handy interface is provided by the
-scripts/kconfig/Makefile patch, which can be applied with either 'git am' or
-the 'patch' utility:
-
-  $ wget -qO- https://raw.githubusercontent.com/ulfalizer/Kconfiglib/master/makefile.patch | git am
-  $ wget -qO- https://raw.githubusercontent.com/ulfalizer/Kconfiglib/master/makefile.patch | patch -p1
-
-Warning: Not passing -p1 to patch will cause the wrong file to be patched.
-
-Please tell me if the patch does not apply. It should be trivial to apply
-manually, as it's just a block of text that needs to be inserted near the other
-*conf: targets in scripts/kconfig/Makefile.
-
-Look further down for a motivation for the Makefile patch and for instructions
-on how you can use Kconfiglib without it.
-
-If you do not wish to install Kconfiglib via pip, the Makefile patch is set up
-so that you can also just clone Kconfiglib into the kernel root:
-
-  $ git clone git://github.com/ulfalizer/Kconfiglib.git
-  $ git am Kconfiglib/makefile.patch  (or 'patch -p1 < Kconfiglib/makefile.patch')
-
-Warning: The directory name Kconfiglib/ is significant in this case, because
-it's added to PYTHONPATH by the new targets in makefile.patch.
-
-The targets added by the Makefile patch are described in the following
-sections.
-
-
-make kmenuconfig
-----------------
-
-This target runs the curses menuconfig interface with Python 3. As of
-Kconfiglib 12.2.0, both Python 2 and Python 3 are supported (previously, only
-Python 3 was supported, so this was a backport).
-
-
-make guiconfig
---------------
-
-This target runs the Tkinter menuconfig interface. Both Python 2 and Python 3
-are supported. To change the Python interpreter used, pass
-PYTHONCMD=<executable> to 'make'. The default is 'python'.
-
-
-make [ARCH=<arch>] iscriptconfig
---------------------------------
-
-This target gives an interactive Python prompt where a Kconfig instance has
-been preloaded and is available in 'kconf'. To change the Python interpreter
-used, pass PYTHONCMD=<executable> to 'make'. The default is 'python'.
-
-To get a feel for the API, try evaluating and printing the symbols in
-kconf.defined_syms, and explore the MenuNode menu tree starting at
-kconf.top_node by following 'next' and 'list' pointers.
-
-The item contained in a menu node is found in MenuNode.item (note that this can
-be one of the constants kconfiglib.MENU and kconfiglib.COMMENT), and all
-symbols and choices have a 'nodes' attribute containing their menu nodes
-(usually only one). Printing a menu node will print its item, in Kconfig
-format.
-
-If you want to look up a symbol by name, use the kconf.syms dictionary.
-
-
-make scriptconfig SCRIPT=<script> [SCRIPT_ARG=<arg>]
-----------------------------------------------------
-
-This target runs the Python script given by the SCRIPT parameter on the
-configuration. sys.argv[1] holds the name of the top-level Kconfig file
-(currently always "Kconfig" in practice), and sys.argv[2] holds the SCRIPT_ARG
-argument, if given.
-
-See the examples/ subdirectory for example scripts.
-
-
-make dumpvarsconfig
--------------------
-
-This target prints a list of all environment variables referenced from the
-Kconfig files, together with their values. See the
-Kconfiglib/examples/dumpvars.py script.
-
-Only environment variables that are referenced via the Kconfig preprocessor
-$(FOO) syntax are included. The preprocessor was added in Linux 4.18.
-
-
-Using Kconfiglib without the Makefile targets
-=============================================
-
-The make targets are only needed to pick up environment variables exported from
-the Kbuild makefiles and referenced inside Kconfig files, via e.g.
-'source "arch/$(SRCARCH)/Kconfig" and commands run via '$(shell,...)'.
-
-These variables are referenced as of writing (Linux 4.18), together with sample
-values:
-
-  srctree          (.)
-  ARCH             (x86)
-  SRCARCH          (x86)
-  KERNELVERSION    (4.18.0)
-  CC               (gcc)
-  HOSTCC           (gcc)
-  HOSTCXX          (g++)
-  CC_VERSION_TEXT  (gcc (Ubuntu 7.3.0-16ubuntu3) 7.3.0)
-
-Older kernels only reference ARCH, SRCARCH, and KERNELVERSION.
-
-If your kernel is recent enough (4.18+), you can get a list of referenced
-environment variables via 'make dumpvarsconfig' (see above). Note that this
-command is added by the Makefile patch.
-
-To run Kconfiglib without the Makefile patch, set the environment variables
-manually:
-
-  $ srctree=. ARCH=x86 SRCARCH=x86 KERNELVERSION=`make kernelversion` ... python(3)
-  >>> import kconfiglib
-  >>> kconf = kconfiglib.Kconfig()  # filename defaults to "Kconfig"
-
-Search the top-level Makefile for "Additional ARCH settings" to see other
-possibilities for ARCH and SRCARCH.
-
-
-Intro to symbol values
-======================
-
-Kconfiglib has the same assignment semantics as the C implementation.
-
-Any symbol can be assigned a value by the user (via Kconfig.load_config() or
-Symbol.set_value()), but this user value is only respected if the symbol is
-visible, which corresponds to it (currently) being visible in the menuconfig
-interface.
-
-For symbols with prompts, the visibility of the symbol is determined by the
-condition on the prompt. Symbols without prompts are never visible, so setting
-a user value on them is pointless. A warning will be printed by default if
-Symbol.set_value() is called on a promptless symbol. Assignments to promptless
-symbols are normal within a .config file, so no similar warning will be printed
-by load_config().
-
-Dependencies from parents and 'if'/'depends on' are propagated to properties,
-including prompts, so these two configurations are logically equivalent:
-
-(1)
-
-  menu "menu"
-      depends on A
-
-  if B
-
-  config FOO
-      tristate "foo" if D
-      default y
-      depends on C
-
-  endif
-
-  endmenu
-
-(2)
-
-  menu "menu"
-      depends on A
-
-  config FOO
-      tristate "foo" if A && B && C && D
-      default y if A && B && C
-
-  endmenu
-
-In this example, A && B && C && D (the prompt condition) needs to be non-n for
-FOO to be visible (assignable). If its value is m, the symbol can only be
-assigned the value m: The visibility sets an upper bound on the value that can
-be assigned by the user, and any higher user value will be truncated down.
-
-'default' properties are independent of the visibility, though a 'default' will
-often get the same condition as the prompt due to dependency propagation.
-'default' properties are used if the symbol is not visible or has no user
-value.
-
-Symbols with no user value (or that have a user value but are not visible) and
-no (active) 'default' default to n for bool/tristate symbols, and to the empty
-string for other symbol types.
-
-'select' works similarly to symbol visibility, but sets a lower bound on the
-value of the symbol. The lower bound is determined by the value of the
-select*ing* symbol. 'select' does not respect visibility, so non-visible
-symbols can be forced to a particular (minimum) value by a select as well.
-
-For non-bool/tristate symbols, it only matters whether the visibility is n or
-non-n: m visibility acts the same as y visibility.
-
-Conditions on 'default' and 'select' work in mostly intuitive ways. If the
-condition is n, the 'default' or 'select' is disabled. If it is m, the
-'default' or 'select' value (the value of the selecting symbol) is truncated
-down to m.
-
-When writing a configuration with Kconfig.write_config(), only symbols that are
-visible, have an (active) default, or are selected will get written out (note
-that this includes all symbols that would accept user values). Kconfiglib
-matches the .config format produced by the C implementations down to the
-character. This eases testing.
-
-For a visible bool/tristate symbol FOO with value n, this line is written to
-.config:
-
-    # CONFIG_FOO is not set
-
-The point is to remember the user n selection (which might differ from the
-default value the symbol would get), while at the same sticking to the rule
-that undefined corresponds to n (.config uses Makefile format, making the line
-above a comment). When the .config file is read back in, this line will be
-treated the same as the following assignment:
-
-    CONFIG_FOO=n
-
-In Kconfiglib, the set of (currently) assignable values for a bool/tristate
-symbol appear in Symbol.assignable. For other symbol types, just check if
-sym.visibility is non-0 (non-n) to see whether the user value will have an
-effect.
-
-
-Intro to the menu tree
-======================
-
-The menu structure, as seen in e.g. menuconfig, is represented by a tree of
-MenuNode objects. The top node of the configuration corresponds to an implicit
-top-level menu, the title of which is shown at the top in the standard
-menuconfig interface. (The title is also available in Kconfig.mainmenu_text in
-Kconfiglib.)
-
-The top node is found in Kconfig.top_node. From there, you can visit child menu
-nodes by following the 'list' pointer, and any following menu nodes by
-following the 'next' pointer. Usually, a non-None 'list' pointer indicates a
-menu or Choice, but menu nodes for symbols can sometimes have a non-None 'list'
-pointer too due to submenus created implicitly from dependencies.
-
-MenuNode.item is either a Symbol or a Choice object, or one of the constants
-MENU and COMMENT. The prompt of the menu node can be found in MenuNode.prompt,
-which also holds the title for menus and comments. For Symbol and Choice,
-MenuNode.help holds the help text (if any, otherwise None).
-
-Most symbols will only have a single menu node. A symbol defined in multiple
-locations will have one menu node for each location. The list of menu nodes for
-a Symbol or Choice can be found in the Symbol/Choice.nodes attribute.
-
-Note that prompts and help texts for symbols and choices are stored in their
-menu node(s) rather than in the Symbol or Choice objects themselves. This makes
-it possible to define a symbol in multiple locations with a different prompt or
-help text in each location. To get the help text or prompt for a symbol with a
-single menu node, do sym.nodes[0].help and sym.nodes[0].prompt, respectively.
-The prompt is a (text, condition) tuple, where condition determines the
-visibility (see 'Intro to expressions' below).
-
-This organization mirrors the C implementation. MenuNode is called
-'struct menu' there, but I thought "menu" was a confusing name.
-
-It is possible to give a Choice a name and define it in multiple locations,
-hence why Choice.nodes is also a list.
-
-As a convenience, the properties added at a particular definition location are
-available on the MenuNode itself, in e.g. MenuNode.defaults. This is helpful
-when generating documentation, so that symbols/choices defined in multiple
-locations can be shown with the correct properties at each location.
-
-
-Intro to expressions
-====================
-
-Expressions can be evaluated with the expr_value() function and printed with
-the expr_str() function (these are used internally as well). Evaluating an
-expression always yields a tristate value, where n, m, and y are represented as
-0, 1, and 2, respectively.
-
-The following table should help you figure out how expressions are represented.
-A, B, C, ... are symbols (Symbol instances), NOT is the kconfiglib.NOT
-constant, etc.
-
-Expression            Representation
-----------            --------------
-A                     A
-"A"                   A (constant symbol)
-!A                    (NOT, A)
-A && B                (AND, A, B)
-A && B && C           (AND, A, (AND, B, C))
-A || B                (OR, A, B)
-A || (B && C && D)    (OR, A, (AND, B, (AND, C, D)))
-A = B                 (EQUAL, A, B)
-A != "foo"            (UNEQUAL, A, foo (constant symbol))
-A && B = C && D       (AND, A, (AND, (EQUAL, B, C), D))
-n                     Kconfig.n (constant symbol)
-m                     Kconfig.m (constant symbol)
-y                     Kconfig.y (constant symbol)
-"y"                   Kconfig.y (constant symbol)
-
-Strings like "foo" in 'default "foo"' or 'depends on SYM = "foo"' are
-represented as constant symbols, so the only values that appear in expressions
-are symbols***. This mirrors the C implementation.
-
-***For choice symbols, the parent Choice will appear in expressions as well,
-but it's usually invisible as the value interfaces of Symbol and Choice are
-identical. This mirrors the C implementation and makes different choice modes
-"just work".
-
-Manual evaluation examples:
-
-  - The value of A && B is min(A.tri_value, B.tri_value)
-
-  - The value of A || B is max(A.tri_value, B.tri_value)
-
-  - The value of !A is 2 - A.tri_value
-
-  - The value of A = B is 2 (y) if A.str_value == B.str_value, and 0 (n)
-    otherwise. Note that str_value is used here instead of tri_value.
-
-    For constant (as well as undefined) symbols, str_value matches the name of
-    the symbol. This mirrors the C implementation and explains why
-    'depends on SYM = "foo"' above works as expected.
-
-n/m/y are automatically converted to the corresponding constant symbols
-"n"/"m"/"y" (Kconfig.n/m/y) during parsing.
-
-Kconfig.const_syms is a dictionary like Kconfig.syms but for constant symbols.
-
-If a condition is missing (e.g., <cond> when the 'if <cond>' is removed from
-'default A if <cond>'), it is actually Kconfig.y. The standard __str__()
-functions just avoid printing 'if y' conditions to give cleaner output.
-
-
-Kconfig extensions
-==================
-
-Kconfiglib includes a couple of Kconfig extensions:
-
-'source' with relative path
----------------------------
-
-The 'rsource' statement sources Kconfig files with a path relative to directory
-of the Kconfig file containing the 'rsource' statement, instead of relative to
-the project root.
-
-Consider following directory tree:
-
-  Project
-  +--Kconfig
-  |
-  +--src
-     +--Kconfig
-     |
-     +--SubSystem1
-        +--Kconfig
-        |
-        +--ModuleA
-           +--Kconfig
-
-In this example, assume that src/SubSystem1/Kconfig wants to source
-src/SubSystem1/ModuleA/Kconfig.
-
-With 'source', this statement would be used:
-
-  source "src/SubSystem1/ModuleA/Kconfig"
-
-With 'rsource', this turns into
-
-  rsource "ModuleA/Kconfig"
-
-If an absolute path is given to 'rsource', it acts the same as 'source'.
-
-'rsource' can be used to create "position-independent" Kconfig trees that can
-be moved around freely.
-
-
-Globbing 'source'
------------------
-
-'source' and 'rsource' accept glob patterns, sourcing all matching Kconfig
-files. They require at least one matching file, raising a KconfigError
-otherwise.
-
-For example, the following statement might source sub1/foofoofoo and
-sub2/foobarfoo:
-
-  source "sub[12]/foo*foo"
-
-The glob patterns accepted are the same as for the standard glob.glob()
-function.
-
-Two additional statements are provided for cases where it's acceptable for a
-pattern to match no files: 'osource' and 'orsource' (the o is for "optional").
-
-For example, the following statements will be no-ops if neither "foo" nor any
-files matching "bar*" exist:
-
-  osource "foo"
-  osource "bar*"
-
-'orsource' does a relative optional source.
-
-'source' and 'osource' are analogous to 'include' and '-include' in Make.
-
-
-Generalized def_* keywords
---------------------------
-
-def_int, def_hex, and def_string are available in addition to def_bool and
-def_tristate, allowing int, hex, and string symbols to be given a type and a
-default at the same time.
-
-
-Extra optional warnings
------------------------
-
-Some optional warnings can be controlled via environment variables:
-
-  - KCONFIG_WARN_UNDEF: If set to 'y', warnings will be generated for all
-    references to undefined symbols within Kconfig files. The only gotcha is
-    that all hex literals must be prefixed with "0x" or "0X", to make it
-    possible to distinguish them from symbol references.
-
-    Some projects (e.g. the Linux kernel) use multiple Kconfig trees with many
-    shared Kconfig files, leading to some safe undefined symbol references.
-    KCONFIG_WARN_UNDEF is useful in projects that only have a single Kconfig
-    tree though.
-
-    KCONFIG_STRICT is an older alias for this environment variable, supported
-    for backwards compatibility.
-
-  - KCONFIG_WARN_UNDEF_ASSIGN: If set to 'y', warnings will be generated for
-    all assignments to undefined symbols within .config files. By default, no
-    such warnings are generated.
-
-    This warning can also be enabled/disabled via the Kconfig.warn_assign_undef
-    variable.
-
-
-Preprocessor user functions defined in Python
----------------------------------------------
-
-Preprocessor functions can be defined in Python, which makes it simple to
-integrate information from existing Python tools into Kconfig (e.g. to have
-Kconfig symbols depend on hardware information stored in some other format).
-
-Putting a Python module named kconfigfunctions(.py) anywhere in sys.path will
-cause it to be imported by Kconfiglib (in Kconfig.__init__()). Note that
-sys.path can be customized via PYTHONPATH, and includes the directory of the
-module being run by default, as well as installation directories.
-
-If the KCONFIG_FUNCTIONS environment variable is set, it gives a different
-module name to use instead of 'kconfigfunctions'.
-
-The imported module is expected to define a global dictionary named 'functions'
-that maps function names to Python functions, as follows:
-
-  def my_fn(kconf, name, arg_1, arg_2, ...):
-      # kconf:
-      #   Kconfig instance
-      #
-      # name:
-      #   Name of the user-defined function ("my-fn"). Think argv[0].
-      #
-      # arg_1, arg_2, ...:
-      #   Arguments passed to the function from Kconfig (strings)
-      #
-      # Returns a string to be substituted as the result of calling the
-      # function
-      ...
-
-  def my_other_fn(kconf, name, arg_1, arg_2, ...):
-      ...
-
-  functions = {
-      "my-fn":       (my_fn,       <min.args>, <max.args>/None),
-      "my-other-fn": (my_other_fn, <min.args>, <max.args>/None),
-      ...
-  }
-
-  ...
-
-<min.args> and <max.args> are the minimum and maximum number of arguments
-expected by the function (excluding the implicit 'name' argument). If
-<max.args> is None, there is no upper limit to the number of arguments. Passing
-an invalid number of arguments will generate a KconfigError exception.
-
-Functions can access the current parsing location as kconf.filename/linenr.
-Accessing other fields of the Kconfig object is not safe. See the warning
-below.
-
-Keep in mind that for a variable defined like 'foo = $(fn)', 'fn' will be
-called only when 'foo' is expanded. If 'fn' uses the parsing location and the
-intent is to use the location of the assignment, you want 'foo := $(fn)'
-instead, which calls the function immediately.
-
-Once defined, user functions can be called from Kconfig in the same way as
-other preprocessor functions:
-
-    config FOO
-        ...
-        depends on $(my-fn,arg1,arg2)
-
-If my_fn() returns "n", this will result in
-
-    config FOO
-        ...
-        depends on n
-
-Warning
-*******
-
-User-defined preprocessor functions are called as they're encountered at parse
-time, before all Kconfig files have been processed, and before the menu tree
-has been finalized. There are no guarantees that accessing Kconfig symbols or
-the menu tree via the 'kconf' parameter will work, and it could potentially
-lead to a crash.
-
-Preferably, user-defined functions should be stateless.
-
-
-Feedback
-========
-
-Send bug reports, suggestions, and questions to ulfalizer a.t Google's email
-service, or open a ticket on the GitHub page.
-"""
-import errno
-import importlib
-import os
-import re
-import sys
-
-# Get rid of some attribute lookups. These are obvious in context.
-from glob import iglob
-from os.path import dirname, exists, expandvars, islink, join, realpath
-
-
-VERSION = (14, 1, 0)
-
-
-# File layout:
-#
-# Public classes
-# Public functions
-# Internal functions
-# Global constants
-
-# Line length: 79 columns
-
-
-#
-# Public classes
-#
-
-
-class Kconfig(object):
-    """
-    Represents a Kconfig configuration, e.g. for x86 or ARM. This is the set of
-    symbols, choices, and menu nodes appearing in the configuration. Creating
-    any number of Kconfig objects (including for different architectures) is
-    safe. Kconfiglib doesn't keep any global state.
-
-    The following attributes are available. They should be treated as
-    read-only, and some are implemented through @property magic.
-
-    syms:
-      A dictionary with all symbols in the configuration, indexed by name. Also
-      includes all symbols that are referenced in expressions but never
-      defined, except for constant (quoted) symbols.
-
-      Undefined symbols can be recognized by Symbol.nodes being empty -- see
-      the 'Intro to the menu tree' section in the module docstring.
-
-    const_syms:
-      A dictionary like 'syms' for constant (quoted) symbols
-
-    named_choices:
-      A dictionary like 'syms' for named choices (choice FOO)
-
-    defined_syms:
-      A list with all defined symbols, in the same order as they appear in the
-      Kconfig files. Symbols defined in multiple locations appear multiple
-      times.
-
-      Note: You probably want to use 'unique_defined_syms' instead. This
-      attribute is mostly maintained for backwards compatibility.
-
-    unique_defined_syms:
-      A list like 'defined_syms', but with duplicates removed. Just the first
-      instance is kept for symbols defined in multiple locations. Kconfig order
-      is preserved otherwise.
-
-      Using this attribute instead of 'defined_syms' can save work, and
-      automatically gives reasonable behavior when writing configuration output
-      (symbols defined in multiple locations only generate output once, while
-      still preserving Kconfig order for readability).
-
-    choices:
-      A list with all choices, in the same order as they appear in the Kconfig
-      files.
-
-      Note: You probably want to use 'unique_choices' instead. This attribute
-      is mostly maintained for backwards compatibility.
-
-    unique_choices:
-      Analogous to 'unique_defined_syms', for choices. Named choices can have
-      multiple definition locations.
-
-    menus:
-      A list with all menus, in the same order as they appear in the Kconfig
-      files
-
-    comments:
-      A list with all comments, in the same order as they appear in the Kconfig
-      files
-
-    kconfig_filenames:
-      A list with the filenames of all Kconfig files included in the
-      configuration, relative to $srctree (or relative to the current directory
-      if $srctree isn't set), except absolute paths (e.g.
-      'source "/foo/Kconfig"') are kept as-is.
-
-      The files are listed in the order they are source'd, starting with the
-      top-level Kconfig file. If a file is source'd multiple times, it will
-      appear multiple times. Use set() to get unique filenames.
-
-      Note that Kconfig.sync_deps() already indirectly catches any file
-      modifications that change configuration output.
-
-    env_vars:
-      A set() with the names of all environment variables referenced in the
-      Kconfig files.
-
-      Only environment variables referenced with the preprocessor $(FOO) syntax
-      will be registered. The older $FOO syntax is only supported for backwards
-      compatibility.
-
-      Also note that $(FOO) won't be registered unless the environment variable
-      $FOO is actually set. If it isn't, $(FOO) is an expansion of an unset
-      preprocessor variable (which gives the empty string).
-
-      Another gotcha is that environment variables referenced in the values of
-      recursively expanded preprocessor variables (those defined with =) will
-      only be registered if the variable is actually used (expanded) somewhere.
-
-      The note from the 'kconfig_filenames' documentation applies here too.
-
-    n/m/y:
-      The predefined constant symbols n/m/y. Also available in const_syms.
-
-    modules:
-      The Symbol instance for the modules symbol. Currently hardcoded to
-      MODULES, which is backwards compatible. Kconfiglib will warn if
-      'option modules' is set on some other symbol. Tell me if you need proper
-      'option modules' support.
-
-      'modules' is never None. If the MODULES symbol is not explicitly defined,
-      its tri_value will be 0 (n), as expected.
-
-      A simple way to enable modules is to do 'kconf.modules.set_value(2)'
-      (provided the MODULES symbol is defined and visible). Modules are
-      disabled by default in the kernel Kconfig files as of writing, though
-      nearly all defconfig files enable them (with 'CONFIG_MODULES=y').
-
-    defconfig_list:
-      The Symbol instance for the 'option defconfig_list' symbol, or None if no
-      defconfig_list symbol exists. The defconfig filename derived from this
-      symbol can be found in Kconfig.defconfig_filename.
-
-    defconfig_filename:
-      The filename given by the defconfig_list symbol. This is taken from the
-      first 'default' with a satisfied condition where the specified file
-      exists (can be opened for reading). If a defconfig file foo/defconfig is
-      not found and $srctree was set when the Kconfig was created,
-      $srctree/foo/defconfig is looked up as well.
-
-      'defconfig_filename' is None if either no defconfig_list symbol exists,
-      or if the defconfig_list symbol has no 'default' with a satisfied
-      condition that specifies a file that exists.
-
-      Gotcha: scripts/kconfig/Makefile might pass --defconfig=<defconfig> to
-      scripts/kconfig/conf when running e.g. 'make defconfig'. This option
-      overrides the defconfig_list symbol, meaning defconfig_filename might not
-      always match what 'make defconfig' would use.
-
-    top_node:
-      The menu node (see the MenuNode class) of the implicit top-level menu.
-      Acts as the root of the menu tree.
-
-    mainmenu_text:
-      The prompt (title) of the top menu (top_node). Defaults to "Main menu".
-      Can be changed with the 'mainmenu' statement (see kconfig-language.txt).
-
-    variables:
-      A dictionary with all preprocessor variables, indexed by name. See the
-      Variable class.
-
-    warn:
-      Set this variable to True/False to enable/disable warnings. See
-      Kconfig.__init__().
-
-      When 'warn' is False, the values of the other warning-related variables
-      are ignored.
-
-      This variable as well as the other warn* variables can be read to check
-      the current warning settings.
-
-    warn_to_stderr:
-      Set this variable to True/False to enable/disable warnings on stderr. See
-      Kconfig.__init__().
-
-    warn_assign_undef:
-      Set this variable to True to generate warnings for assignments to
-      undefined symbols in configuration files.
-
-      This variable is False by default unless the KCONFIG_WARN_UNDEF_ASSIGN
-      environment variable was set to 'y' when the Kconfig instance was
-      created.
-
-    warn_assign_override:
-      Set this variable to True to generate warnings for multiple assignments
-      to the same symbol in configuration files, where the assignments set
-      different values (e.g. CONFIG_FOO=m followed by CONFIG_FOO=y, where the
-      last value would get used).
-
-      This variable is True by default. Disabling it might be useful when
-      merging configurations.
-
-    warn_assign_redun:
-      Like warn_assign_override, but for multiple assignments setting a symbol
-      to the same value.
-
-      This variable is True by default. Disabling it might be useful when
-      merging configurations.
-
-    warnings:
-      A list of strings containing all warnings that have been generated, for
-      cases where more flexibility is needed.
-
-      See the 'warn_to_stderr' parameter to Kconfig.__init__() and the
-      Kconfig.warn_to_stderr variable as well. Note that warnings still get
-      added to Kconfig.warnings when 'warn_to_stderr' is True.
-
-      Just as for warnings printed to stderr, only warnings that are enabled
-      will get added to Kconfig.warnings. See the various Kconfig.warn*
-      variables.
-
-    missing_syms:
-      A list with (name, value) tuples for all assignments to undefined symbols
-      within the most recently loaded .config file(s). 'name' is the symbol
-      name without the 'CONFIG_' prefix. 'value' is a string that gives the
-      right-hand side of the assignment verbatim.
-
-      See Kconfig.load_config() as well.
-
-    srctree:
-      The value the $srctree environment variable had when the Kconfig instance
-      was created, or the empty string if $srctree wasn't set. This gives nice
-      behavior with os.path.join(), which treats "" as the current directory,
-      without adding "./".
-
-      Kconfig files are looked up relative to $srctree (unless absolute paths
-      are used), and .config files are looked up relative to $srctree if they
-      are not found in the current directory. This is used to support
-      out-of-tree builds. The C tools use this environment variable in the same
-      way.
-
-      Changing $srctree after creating the Kconfig instance has no effect. Only
-      the value when the configuration is loaded matters. This avoids surprises
-      if multiple configurations are loaded with different values for $srctree.
-
-    config_prefix:
-      The value the CONFIG_ environment variable had when the Kconfig instance
-      was created, or "CONFIG_" if CONFIG_ wasn't set. This is the prefix used
-      (and expected) on symbol names in .config files and C headers. Used in
-      the same way in the C tools.
-
-    config_header:
-      The value the KCONFIG_CONFIG_HEADER environment variable had when the
-      Kconfig instance was created, or the empty string if
-      KCONFIG_CONFIG_HEADER wasn't set. This string is inserted verbatim at the
-      beginning of configuration files. See write_config().
-
-    header_header:
-      The value the KCONFIG_AUTOHEADER_HEADER environment variable had when the
-      Kconfig instance was created, or the empty string if
-      KCONFIG_AUTOHEADER_HEADER wasn't set. This string is inserted verbatim at
-      the beginning of header files. See write_autoconf().
-
-    filename/linenr:
-      The current parsing location, for use in Python preprocessor functions.
-      See the module docstring.
-    """
-    __slots__ = (
-        "_encoding",
-        "_functions",
-        "_set_match",
-        "_srctree_prefix",
-        "_unset_match",
-        "_warn_assign_no_prompt",
-        "allow_empty_macros",
-        "choices",
-        "comments",
-        "config_header",
-        "config_prefix",
-        "const_syms",
-        "defconfig_list",
-        "defined_syms",
-        "env_vars",
-        "header_header",
-        "kconfig_filenames",
-        "m",
-        "menus",
-        "missing_syms",
-        "modules",
-        "n",
-        "named_choices",
-        "srctree",
-        "search_paths",
-        "syms",
-        "top_node",
-        "unique_choices",
-        "unique_defined_syms",
-        "variables",
-        "warn",
-        "warn_assign_override",
-        "warn_assign_redun",
-        "warn_assign_undef",
-        "warn_to_stderr",
-        "warnings",
-        "y",
-
-        # Parsing-related
-        "_parsing_kconfigs",
-        "_readline",
-        "filename",
-        "linenr",
-        "_include_path",
-        "_filestack",
-        "_line",
-        "_tokens",
-        "_tokens_i",
-        "_reuse_tokens",
-    )
-
-    #
-    # Public interface
-    #
-
-    def __init__(self, filename="Kconfig", warn=True, warn_to_stderr=True,
-                 encoding="utf-8", suppress_traceback=False, search_paths=None,
-                 allow_empty_macros=False):
-        """
-        Creates a new Kconfig object by parsing Kconfig files.
-        Note that Kconfig files are not the same as .config files (which store
-        configuration symbol values).
-
-        See the module docstring for some environment variables that influence
-        default warning settings (KCONFIG_WARN_UNDEF and
-        KCONFIG_WARN_UNDEF_ASSIGN).
-
-        Raises KconfigError on syntax/semantic errors, and OSError or (possibly
-        a subclass of) IOError on IO errors ('errno', 'strerror', and
-        'filename' are available). Note that IOError is an alias for OSError on
-        Python 3, so it's enough to catch OSError there. If you need Python 2/3
-        compatibility, it's easiest to catch EnvironmentError, which is a
-        common base class of OSError/IOError on Python 2 and an alias for
-        OSError on Python 3.
-
-        filename (default: "Kconfig"):
-          The Kconfig file to load. For the Linux kernel, you'll want "Kconfig"
-          from the top-level directory, as environment variables will make sure
-          the right Kconfig is included from there (arch/$SRCARCH/Kconfig as of
-          writing).
-
-          If $srctree is set, 'filename' will be looked up relative to it.
-          $srctree is also used to look up source'd files within Kconfig files.
-          See the class documentation.
-
-          If you are using Kconfiglib via 'make scriptconfig', the filename of
-          the base base Kconfig file will be in sys.argv[1]. It's currently
-          always "Kconfig" in practice.
-
-        warn (default: True):
-          True if warnings related to this configuration should be generated.
-          This can be changed later by setting Kconfig.warn to True/False. It
-          is provided as a constructor argument since warnings might be
-          generated during parsing.
-
-          See the other Kconfig.warn_* variables as well, which enable or
-          suppress certain warnings when warnings are enabled.
-
-          All generated warnings are added to the Kconfig.warnings list. See
-          the class documentation.
-
-        warn_to_stderr (default: True):
-          True if warnings should be printed to stderr in addition to being
-          added to Kconfig.warnings.
-
-          This can be changed later by setting Kconfig.warn_to_stderr to
-          True/False.
-
-        encoding (default: "utf-8"):
-          The encoding to use when reading and writing files, and when decoding
-          output from commands run via $(shell). If None, the encoding
-          specified in the current locale will be used.
-
-          The "utf-8" default avoids exceptions on systems that are configured
-          to use the C locale, which implies an ASCII encoding.
-
-          This parameter has no effect on Python 2, due to implementation
-          issues (regular strings turning into Unicode strings, which are
-          distinct in Python 2). Python 2 doesn't decode regular strings
-          anyway.
-
-          Related PEP: https://www.python.org/dev/peps/pep-0538/
-
-        suppress_traceback (default: False):
-          Helper for tools. When True, any EnvironmentError or KconfigError
-          generated during parsing is caught, the exception message is printed
-          to stderr together with the command name, and sys.exit(1) is called
-          (which generates SystemExit).
-
-          This hides the Python traceback for "expected" errors like syntax
-          errors in Kconfig files.
-
-          Other exceptions besides EnvironmentError and KconfigError are still
-          propagated when suppress_traceback is True.
-
-        search_paths (default: None):
-          List of paths to search for Kconfig files. This is needed when the
-          files are split between two project directories, as is done with
-          Zephyr OS, for example. It allows files in one project to reference
-          files in another.
-
-          This argument affects the operation of commands which include other
-          Kconfig files, such as `source` and `rsource`.
-
-          When not None, it should be a list of paths to directories to search.
-          Each search path is prepended to the relative filename to assist in
-          finding the file. The proeect directories should have distinct
-          filenames and/or subdirectory structures, so avoid ambiguity.
-
-        allow_empty_macros (default: False):
-          Normally when macros expand to empty it means that the macro is not
-          defined. This is considered an error and parsing of the Kconfig files
-          aborts with an exception. In some cases it is useful to continue
-          parsing, to obtain what information is available.
-
-          An example is where the value of various macros is not known but the
-          caller simply wants to get a list of the available Kconfig options.
-
-          Pass True here to allow empty / undefined macros.
-        """
-        try:
-            self._init(filename, warn, warn_to_stderr, encoding, search_paths,
-                       allow_empty_macros)
-        except (EnvironmentError, KconfigError) as e:
-            if suppress_traceback:
-                cmd = sys.argv[0]  # Empty string if missing
-                if cmd:
-                    cmd += ": "
-                # Some long exception messages have extra newlines for better
-                # formatting when reported as an unhandled exception. Strip
-                # them here.
-                sys.exit(cmd + str(e).strip())
-            raise
-
-    def _init(self, filename, warn, warn_to_stderr, encoding, search_paths,
-              allow_empty_macros):
-        # See __init__()
-
-        self._encoding = encoding
-
-        self.srctree = os.getenv("srctree", "")
-        # A prefix we can reliably strip from glob() results to get a filename
-        # relative to $srctree. relpath() can cause issues for symlinks,
-        # because it assumes symlink/../foo is the same as foo/.
-        self._srctree_prefix = realpath(self.srctree) + os.sep
-        self.search_paths = search_paths
-        self.allow_empty_macros = allow_empty_macros
-
-        self.warn = warn
-        self.warn_to_stderr = warn_to_stderr
-        self.warn_assign_undef = os.getenv("KCONFIG_WARN_UNDEF_ASSIGN") == "y"
-        self.warn_assign_override = True
-        self.warn_assign_redun = True
-        self._warn_assign_no_prompt = True
-
-        self.warnings = []
-
-        self.config_prefix = os.getenv("CONFIG_", "CONFIG_")
-        # Regular expressions for parsing .config files
-        self._set_match = _re_match(self.config_prefix + r"([^=]+)=(.*)")
-        self._unset_match = _re_match(r"# {}([^ ]+) is not set".format(
-            self.config_prefix))
-
-        self.config_header = os.getenv("KCONFIG_CONFIG_HEADER", "")
-        self.header_header = os.getenv("KCONFIG_AUTOHEADER_HEADER", "")
-
-        self.syms = {}
-        self.const_syms = {}
-        self.defined_syms = []
-        self.missing_syms = []
-        self.named_choices = {}
-        self.choices = []
-        self.menus = []
-        self.comments = []
-
-        for nmy in "n", "m", "y":
-            sym = Symbol()
-            sym.kconfig = self
-            sym.name = nmy
-            sym.is_constant = True
-            sym.orig_type = TRISTATE
-            sym._cached_tri_val = STR_TO_TRI[nmy]
-
-            self.const_syms[nmy] = sym
-
-        self.n = self.const_syms["n"]
-        self.m = self.const_syms["m"]
-        self.y = self.const_syms["y"]
-
-        # Make n/m/y well-formed symbols
-        for nmy in "n", "m", "y":
-            sym = self.const_syms[nmy]
-            sym.rev_dep = sym.weak_rev_dep = sym.direct_dep = self.n
-
-        # Maps preprocessor variables names to Variable instances
-        self.variables = {}
-
-        # Predefined preprocessor functions, with min/max number of arguments
-        self._functions = {
-            "info":       (_info_fn,       1, 1),
-            "error-if":   (_error_if_fn,   2, 2),
-            "filename":   (_filename_fn,   0, 0),
-            "lineno":     (_lineno_fn,     0, 0),
-            "shell":      (_shell_fn,      1, 1),
-            "warning-if": (_warning_if_fn, 2, 2),
-        }
-
-        # Add any user-defined preprocessor functions
-        try:
-            self._functions.update(
-                importlib.import_module(
-                    os.getenv("KCONFIG_FUNCTIONS", "kconfigfunctions")
-                ).functions)
-        except ImportError:
-            pass
-
-        # This determines whether previously unseen symbols are registered.
-        # They shouldn't be if we parse expressions after parsing, as part of
-        # Kconfig.eval_string().
-        self._parsing_kconfigs = True
-
-        self.modules = self._lookup_sym("MODULES")
-        self.defconfig_list = None
-
-        self.top_node = MenuNode()
-        self.top_node.kconfig = self
-        self.top_node.item = MENU
-        self.top_node.is_menuconfig = True
-        self.top_node.visibility = self.y
-        self.top_node.prompt = ("Main menu", self.y)
-        self.top_node.parent = None
-        self.top_node.dep = self.y
-        self.top_node.filename = filename
-        self.top_node.linenr = 1
-        self.top_node.include_path = ()
-
-        # Parse the Kconfig files
-
-        # Not used internally. Provided as a convenience.
-        self.kconfig_filenames = [filename]
-        self.env_vars = set()
-
-        # Keeps track of the location in the parent Kconfig files. Kconfig
-        # files usually source other Kconfig files. See _enter_file().
-        self._filestack = []
-        self._include_path = ()
-
-        # The current parsing location
-        self.filename = filename
-        self.linenr = 0
-
-        # Used to avoid retokenizing lines when we discover that they're not
-        # part of the construct currently being parsed. This is kinda like an
-        # unget operation.
-        self._reuse_tokens = False
-
-        # Open the top-level Kconfig file. Store the readline() method directly
-        # as a small optimization.
-        self._readline = self._open(join(self.srctree, filename), "r").readline
-
-        try:
-            # Parse the Kconfig files. Returns the last node, which we
-            # terminate with '.next = None'.
-            self._parse_block(None, self.top_node, self.top_node).next = None
-            self.top_node.list = self.top_node.next
-            self.top_node.next = None
-        except UnicodeDecodeError as e:
-            _decoding_error(e, self.filename)
-
-        # Close the top-level Kconfig file. __self__ fetches the 'file' object
-        # for the method.
-        self._readline.__self__.close()
-
-        self._parsing_kconfigs = False
-
-        # Do various menu tree post-processing
-        self._finalize_node(self.top_node, self.y)
-
-        self.unique_defined_syms = _ordered_unique(self.defined_syms)
-        self.unique_choices = _ordered_unique(self.choices)
-
-        # Do sanity checks. Some of these depend on everything being finalized.
-        self._check_sym_sanity()
-        self._check_choice_sanity()
-
-        # KCONFIG_STRICT is an older alias for KCONFIG_WARN_UNDEF, supported
-        # for backwards compatibility
-        if os.getenv("KCONFIG_WARN_UNDEF") == "y" or \
-           os.getenv("KCONFIG_STRICT") == "y":
-
-            self._check_undef_syms()
-
-        # Build Symbol._dependents for all symbols and choices
-        self._build_dep()
-
-        # Check for dependency loops
-        check_dep_loop_sym = _check_dep_loop_sym  # Micro-optimization
-        for sym in self.unique_defined_syms:
-            check_dep_loop_sym(sym, False)
-
-        # Add extra dependencies from choices to choice symbols that get
-        # awkward during dependency loop detection
-        self._add_choice_deps()
-
-    @property
-    def mainmenu_text(self):
-        """
-        See the class documentation.
-        """
-        return self.top_node.prompt[0]
-
-    @property
-    def defconfig_filename(self):
-        """
-        See the class documentation.
-        """
-        if self.defconfig_list:
-            for filename, cond in self.defconfig_list.defaults:
-                if expr_value(cond):
-                    try:
-                        with self._open_config(filename.str_value) as f:
-                            return f.name
-                    except EnvironmentError:
-                        continue
-
-        return None
-
-    def load_config(self, filename=None, replace=True, verbose=None):
-        """
-        Loads symbol values from a file in the .config format. Equivalent to
-        calling Symbol.set_value() to set each of the values.
-
-        "# CONFIG_FOO is not set" within a .config file sets the user value of
-        FOO to n. The C tools work the same way.
-
-        For each symbol, the Symbol.user_value attribute holds the value the
-        symbol was assigned in the .config file (if any). The user value might
-        differ from Symbol.str/tri_value if there are unsatisfied dependencies.
-
-        Calling this function also updates the Kconfig.missing_syms attribute
-        with a list of all assignments to undefined symbols within the
-        configuration file. Kconfig.missing_syms is cleared if 'replace' is
-        True, and appended to otherwise. See the documentation for
-        Kconfig.missing_syms as well.
-
-        See the Kconfig.__init__() docstring for raised exceptions
-        (OSError/IOError). KconfigError is never raised here.
-
-        filename (default: None):
-          Path to load configuration from (a string). Respects $srctree if set
-          (see the class documentation).
-
-          If 'filename' is None (the default), the configuration file to load
-          (if any) is calculated automatically, giving the behavior you'd
-          usually want:
-
-            1. If the KCONFIG_CONFIG environment variable is set, it gives the
-               path to the configuration file to load. Otherwise, ".config" is
-               used. See standard_config_filename().
-
-            2. If the path from (1.) doesn't exist, the configuration file
-               given by kconf.defconfig_filename is loaded instead, which is
-               derived from the 'option defconfig_list' symbol.
-
-            3. If (1.) and (2.) fail to find a configuration file to load, no
-               configuration file is loaded, and symbols retain their current
-               values (e.g., their default values). This is not an error.
-
-           See the return value as well.
-
-        replace (default: True):
-          If True, all existing user values will be cleared before loading the
-          .config. Pass False to merge configurations.
-
-        verbose (default: None):
-          Limited backwards compatibility to prevent crashes. A warning is
-          printed if anything but None is passed.
-
-          Prior to Kconfiglib 12.0.0, this option enabled printing of messages
-          to stdout when 'filename' was None. A message is (always) returned
-          now instead, which is more flexible.
-
-          Will probably be removed in some future version.
-
-        Returns a string with a message saying which file got loaded (or
-        possibly that no file got loaded, when 'filename' is None). This is
-        meant to reduce boilerplate in tools, which can do e.g.
-        print(kconf.load_config()). The returned message distinguishes between
-        loading (replace == True) and merging (replace == False).
-        """
-        if verbose is not None:
-            _warn_verbose_deprecated("load_config")
-
-        msg = None
-        if filename is None:
-            filename = standard_config_filename()
-            if not exists(filename) and \
-               not exists(join(self.srctree, filename)):
-                defconfig = self.defconfig_filename
-                if defconfig is None:
-                    return "Using default symbol values (no '{}')" \
-                           .format(filename)
-
-                msg = " default configuration '{}' (no '{}')" \
-                      .format(defconfig, filename)
-                filename = defconfig
-
-        if not msg:
-            msg = " configuration '{}'".format(filename)
-
-        # Disable the warning about assigning to symbols without prompts. This
-        # is normal and expected within a .config file.
-        self._warn_assign_no_prompt = False
-
-        # This stub only exists to make sure _warn_assign_no_prompt gets
-        # reenabled
-        try:
-            self._load_config(filename, replace)
-        except UnicodeDecodeError as e:
-            _decoding_error(e, filename)
-        finally:
-            self._warn_assign_no_prompt = True
-
-        return ("Loaded" if replace else "Merged") + msg
-
-    def _load_config(self, filename, replace):
-        with self._open_config(filename) as f:
-            if replace:
-                self.missing_syms = []
-
-                # If we're replacing the configuration, keep track of which
-                # symbols and choices got set so that we can unset the rest
-                # later. This avoids invalidating everything and is faster.
-                # Another benefit is that invalidation must be rock solid for
-                # it to work, making it a good test.
-
-                for sym in self.unique_defined_syms:
-                    sym._was_set = False
-
-                for choice in self.unique_choices:
-                    choice._was_set = False
-
-            # Small optimizations
-            set_match = self._set_match
-            unset_match = self._unset_match
-            get_sym = self.syms.get
-
-            for linenr, line in enumerate(f, 1):
-                # The C tools ignore trailing whitespace
-                line = line.rstrip()
-
-                match = set_match(line)
-                if match:
-                    name, val = match.groups()
-                    sym = get_sym(name)
-                    if not sym or not sym.nodes:
-                        self._undef_assign(name, val, filename, linenr)
-                        continue
-
-                    if sym.orig_type in _BOOL_TRISTATE:
-                        # The C implementation only checks the first character
-                        # to the right of '=', for whatever reason
-                        if not (sym.orig_type is BOOL
-                                and val.startswith(("y", "n")) or
-                                sym.orig_type is TRISTATE
-                                and val.startswith(("y", "m", "n"))):
-                            self._warn("'{}' is not a valid value for the {} "
-                                       "symbol {}. Assignment ignored."
-                                       .format(val, TYPE_TO_STR[sym.orig_type],
-                                               sym.name_and_loc),
-                                       filename, linenr)
-                            continue
-
-                        val = val[0]
-
-                        if sym.choice and val != "n":
-                            # During .config loading, we infer the mode of the
-                            # choice from the kind of values that are assigned
-                            # to the choice symbols
-
-                            prev_mode = sym.choice.user_value
-                            if prev_mode is not None and \
-                               TRI_TO_STR[prev_mode] != val:
-
-                                self._warn("both m and y assigned to symbols "
-                                           "within the same choice",
-                                           filename, linenr)
-
-                            # Set the choice's mode
-                            sym.choice.set_value(val)
-
-                    elif sym.orig_type is STRING:
-                        match = _conf_string_match(val)
-                        if not match:
-                            self._warn("malformed string literal in "
-                                       "assignment to {}. Assignment ignored."
-                                       .format(sym.name_and_loc),
-                                       filename, linenr)
-                            continue
-
-                        val = unescape(match.group(1))
-
-                else:
-                    match = unset_match(line)
-                    if not match:
-                        # Print a warning for lines that match neither
-                        # set_match() nor unset_match() and that are not blank
-                        # lines or comments. 'line' has already been
-                        # rstrip()'d, so blank lines show up as "" here.
-                        if line and not line.lstrip().startswith("#"):
-                            self._warn("ignoring malformed line '{}'"
-                                       .format(line),
-                                       filename, linenr)
-
-                        continue
-
-                    name = match.group(1)
-                    sym = get_sym(name)
-                    if not sym or not sym.nodes:
-                        self._undef_assign(name, "n", filename, linenr)
-                        continue
-
-                    if sym.orig_type not in _BOOL_TRISTATE:
-                        continue
-
-                    val = "n"
-
-                # Done parsing the assignment. Set the value.
-
-                if sym._was_set:
-                    self._assigned_twice(sym, val, filename, linenr)
-
-                sym.set_value(val)
-
-        if replace:
-            # If we're replacing the configuration, unset the symbols that
-            # didn't get set
-
-            for sym in self.unique_defined_syms:
-                if not sym._was_set:
-                    sym.unset_value()
-
-            for choice in self.unique_choices:
-                if not choice._was_set:
-                    choice.unset_value()
-
-    def _undef_assign(self, name, val, filename, linenr):
-        # Called for assignments to undefined symbols during .config loading
-
-        self.missing_syms.append((name, val))
-        if self.warn_assign_undef:
-            self._warn(
-                "attempt to assign the value '{}' to the undefined symbol {}"
-                .format(val, name), filename, linenr)
-
-    def _assigned_twice(self, sym, new_val, filename, linenr):
-        # Called when a symbol is assigned more than once in a .config file
-
-        # Use strings for bool/tristate user values in the warning
-        if sym.orig_type in _BOOL_TRISTATE:
-            user_val = TRI_TO_STR[sym.user_value]
-        else:
-            user_val = sym.user_value
-
-        msg = '{} set more than once. Old value "{}", new value "{}".'.format(
-            sym.name_and_loc, user_val, new_val)
-
-        if user_val == new_val:
-            if self.warn_assign_redun:
-                self._warn(msg, filename, linenr)
-        elif self.warn_assign_override:
-            self._warn(msg, filename, linenr)
-
-    def load_allconfig(self, filename):
-        """
-        Helper for all*config. Loads (merges) the configuration file specified
-        by KCONFIG_ALLCONFIG, if any. See Documentation/kbuild/kconfig.txt in
-        the Linux kernel.
-
-        Disables warnings for duplicated assignments within configuration files
-        for the duration of the call
-        (kconf.warn_assign_override/warn_assign_redun = False), and restores
-        the previous warning settings at the end. The KCONFIG_ALLCONFIG
-        configuration file is expected to override symbols.
-
-        Exits with sys.exit() (which raises a SystemExit exception) and prints
-        an error to stderr if KCONFIG_ALLCONFIG is set but the configuration
-        file can't be opened.
-
-        filename:
-          Command-specific configuration filename - "allyes.config",
-          "allno.config", etc.
-        """
-        load_allconfig(self, filename)
-
-    def write_autoconf(self, filename=None, header=None):
-        r"""
-        Writes out symbol values as a C header file, matching the format used
-        by include/generated/autoconf.h in the kernel.
-
-        The ordering of the #defines matches the one generated by
-        write_config(). The order in the C implementation depends on the hash
-        table implementation as of writing, and so won't match.
-
-        If 'filename' exists and its contents is identical to what would get
-        written out, it is left untouched. This avoids updating file metadata
-        like the modification time and possibly triggering redundant work in
-        build tools.
-
-        filename (default: None):
-          Path to write header to.
-
-          If None (the default), the path in the environment variable
-          KCONFIG_AUTOHEADER is used if set, and "include/generated/autoconf.h"
-          otherwise. This is compatible with the C tools.
-
-        header (default: None):
-          Text inserted verbatim at the beginning of the file. You would
-          usually want it enclosed in '/* */' to make it a C comment, and
-          include a trailing newline.
-
-          If None (the default), the value of the environment variable
-          KCONFIG_AUTOHEADER_HEADER had when the Kconfig instance was created
-          will be used if it was set, and no header otherwise. See the
-          Kconfig.header_header attribute.
-
-        Returns a string with a message saying that the header got saved, or
-        that there were no changes to it. This is meant to reduce boilerplate
-        in tools, which can do e.g. print(kconf.write_autoconf()).
-        """
-        if filename is None:
-            filename = os.getenv("KCONFIG_AUTOHEADER",
-                                 "include/generated/autoconf.h")
-
-        if self._write_if_changed(filename, self._autoconf_contents(header)):
-            return "Kconfig header saved to '{}'".format(filename)
-        return "No change to Kconfig header in '{}'".format(filename)
-
-    def _autoconf_contents(self, header):
-        # write_autoconf() helper. Returns the contents to write as a string,
-        # with 'header' or KCONFIG_AUTOHEADER_HEADER at the beginning.
-
-        if header is None:
-            header = self.header_header
-
-        chunks = [header]  # "".join()ed later
-        add = chunks.append
-
-        for sym in self.unique_defined_syms:
-            # _write_to_conf is determined when the value is calculated. This
-            # is a hidden function call due to property magic.
-            #
-            # Note: In client code, you can check if sym.config_string is empty
-            # instead, to avoid accessing the internal _write_to_conf variable
-            # (though it's likely to keep working).
-            val = sym.str_value
-            if not sym._write_to_conf:
-                continue
-
-            if sym.orig_type in _BOOL_TRISTATE:
-                if val == "y":
-                    add("#define {}{} 1\n"
-                        .format(self.config_prefix, sym.name))
-                elif val == "m":
-                    add("#define {}{}_MODULE 1\n"
-                        .format(self.config_prefix, sym.name))
-
-            elif sym.orig_type is STRING:
-                add('#define {}{} "{}"\n'
-                    .format(self.config_prefix, sym.name, escape(val)))
-
-            else:  # sym.orig_type in _INT_HEX:
-                if sym.orig_type is HEX and \
-                   not val.startswith(("0x", "0X")):
-                    val = "0x" + val
-
-                add("#define {}{} {}\n"
-                    .format(self.config_prefix, sym.name, val))
-
-        return "".join(chunks)
-
-    def write_config(self, filename=None, header=None, save_old=True,
-                     verbose=None):
-        r"""
-        Writes out symbol values in the .config format. The format matches the
-        C implementation, including ordering.
-
-        Symbols appear in the same order in generated .config files as they do
-        in the Kconfig files. For symbols defined in multiple locations, a
-        single assignment is written out corresponding to the first location
-        where the symbol is defined.
-
-        See the 'Intro to symbol values' section in the module docstring to
-        understand which symbols get written out.
-
-        If 'filename' exists and its contents is identical to what would get
-        written out, it is left untouched. This avoids updating file metadata
-        like the modification time and possibly triggering redundant work in
-        build tools.
-
-        See the Kconfig.__init__() docstring for raised exceptions
-        (OSError/IOError). KconfigError is never raised here.
-
-        filename (default: None):
-          Path to write configuration to (a string).
-
-          If None (the default), the path in the environment variable
-          KCONFIG_CONFIG is used if set, and ".config" otherwise. See
-          standard_config_filename().
-
-        header (default: None):
-          Text inserted verbatim at the beginning of the file. You would
-          usually want each line to start with '#' to make it a comment, and
-          include a trailing newline.
-
-          if None (the default), the value of the environment variable
-          KCONFIG_CONFIG_HEADER had when the Kconfig instance was created will
-          be used if it was set, and no header otherwise. See the
-          Kconfig.config_header attribute.
-
-        save_old (default: True):
-          If True and <filename> already exists, a copy of it will be saved to
-          <filename>.old in the same directory before the new configuration is
-          written.
-
-          Errors are silently ignored if <filename>.old cannot be written (e.g.
-          due to being a directory, or <filename> being something like
-          /dev/null).
-
-        verbose (default: None):
-          Limited backwards compatibility to prevent crashes. A warning is
-          printed if anything but None is passed.
-
-          Prior to Kconfiglib 12.0.0, this option enabled printing of messages
-          to stdout when 'filename' was None. A message is (always) returned
-          now instead, which is more flexible.
-
-          Will probably be removed in some future version.
-
-        Returns a string with a message saying which file got saved. This is
-        meant to reduce boilerplate in tools, which can do e.g.
-        print(kconf.write_config()).
-        """
-        if verbose is not None:
-            _warn_verbose_deprecated("write_config")
-
-        if filename is None:
-            filename = standard_config_filename()
-
-        contents = self._config_contents(header)
-        if self._contents_eq(filename, contents):
-            return "No change to configuration in '{}'".format(filename)
-
-        if save_old:
-            _save_old(filename)
-
-        with self._open(filename, "w") as f:
-            f.write(contents)
-
-        return "Configuration saved to '{}'".format(filename)
-
-    def _config_contents(self, header):
-        # write_config() helper. Returns the contents to write as a string,
-        # with 'header' or KCONFIG_CONFIG_HEADER at the beginning.
-        #
-        # More memory friendly would be to 'yield' the strings and
-        # "".join(_config_contents()), but it was a bit slower on my system.
-
-        # node_iter() was used here before commit 3aea9f7 ("Add '# end of
-        # <menu>' after menus in .config"). Those comments get tricky to
-        # implement with it.
-
-        for sym in self.unique_defined_syms:
-            sym._visited = False
-
-        if header is None:
-            header = self.config_header
-
-        chunks = [header]  # "".join()ed later
-        add = chunks.append
-
-        # Did we just print an '# end of ...' comment?
-        after_end_comment = False
-
-        node = self.top_node
-        while 1:
-            # Jump to the next node with an iterative tree walk
-            if node.list:
-                node = node.list
-            elif node.next:
-                node = node.next
-            else:
-                while node.parent:
-                    node = node.parent
-
-                    # Add a comment when leaving visible menus
-                    if node.item is MENU and expr_value(node.dep) and \
-                       expr_value(node.visibility) and \
-                       node is not self.top_node:
-                        add("# end of {}\n".format(node.prompt[0]))
-                        after_end_comment = True
-
-                    if node.next:
-                        node = node.next
-                        break
-                else:
-                    # No more nodes
-                    return "".join(chunks)
-
-            # Generate configuration output for the node
-
-            item = node.item
-
-            if item.__class__ is Symbol:
-                if item._visited:
-                    continue
-                item._visited = True
-
-                conf_string = item.config_string
-                if not conf_string:
-                    continue
-
-                if after_end_comment:
-                    # Add a blank line before the first symbol printed after an
-                    # '# end of ...' comment
-                    after_end_comment = False
-                    add("\n")
-                add(conf_string)
-
-            elif expr_value(node.dep) and \
-                 ((item is MENU and expr_value(node.visibility)) or
-                  item is COMMENT):
-
-                add("\n#\n# {}\n#\n".format(node.prompt[0]))
-                after_end_comment = False
-
-    def write_min_config(self, filename, header=None):
-        """
-        Writes out a "minimal" configuration file, omitting symbols whose value
-        matches their default value. The format matches the one produced by
-        'make savedefconfig'.
-
-        The resulting configuration file is incomplete, but a complete
-        configuration can be derived from it by loading it. Minimal
-        configuration files can serve as a more manageable configuration format
-        compared to a "full" .config file, especially when configurations files
-        are merged or edited by hand.
-
-        See the Kconfig.__init__() docstring for raised exceptions
-        (OSError/IOError). KconfigError is never raised here.
-
-        filename:
-          Path to write minimal configuration to.
-
-        header (default: None):
-          Text inserted verbatim at the beginning of the file. You would
-          usually want each line to start with '#' to make it a comment, and
-          include a final terminating newline.
-
-          if None (the default), the value of the environment variable
-          KCONFIG_CONFIG_HEADER had when the Kconfig instance was created will
-          be used if it was set, and no header otherwise. See the
-          Kconfig.config_header attribute.
-
-        Returns a string with a message saying the minimal configuration got
-        saved, or that there were no changes to it. This is meant to reduce
-        boilerplate in tools, which can do e.g.
-        print(kconf.write_min_config()).
-        """
-        if self._write_if_changed(filename, self._min_config_contents(header)):
-            return "Minimal configuration saved to '{}'".format(filename)
-        return "No change to minimal configuration in '{}'".format(filename)
-
-    def _min_config_contents(self, header):
-        # write_min_config() helper. Returns the contents to write as a string,
-        # with 'header' or KCONFIG_CONFIG_HEADER at the beginning.
-
-        if header is None:
-            header = self.config_header
-
-        chunks = [header]  # "".join()ed later
-        add = chunks.append
-
-        for sym in self.unique_defined_syms:
-            # Skip symbols that cannot be changed. Only check
-            # non-choice symbols, as selects don't affect choice
-            # symbols.
-            if not sym.choice and \
-               sym.visibility <= expr_value(sym.rev_dep):
-                continue
-
-            # Skip symbols whose value matches their default
-            if sym.str_value == sym._str_default():
-                continue
-
-            # Skip symbols that would be selected by default in a
-            # choice, unless the choice is optional or the symbol type
-            # isn't bool (it might be possible to set the choice mode
-            # to n or the symbol to m in those cases).
-            if sym.choice and \
-               not sym.choice.is_optional and \
-               sym.choice._selection_from_defaults() is sym and \
-               sym.orig_type is BOOL and \
-               sym.tri_value == 2:
-                continue
-
-            add(sym.config_string)
-
-        return "".join(chunks)
-
-    def sync_deps(self, path):
-        """
-        Creates or updates a directory structure that can be used to avoid
-        doing a full rebuild whenever the configuration is changed, mirroring
-        include/config/ in the kernel.
-
-        This function is intended to be called during each build, before
-        compiling source files that depend on configuration symbols.
-
-        See the Kconfig.__init__() docstring for raised exceptions
-        (OSError/IOError). KconfigError is never raised here.
-
-        path:
-          Path to directory
-
-        sync_deps(path) does the following:
-
-          1. If the directory <path> does not exist, it is created.
-
-          2. If <path>/auto.conf exists, old symbol values are loaded from it,
-             which are then compared against the current symbol values. If a
-             symbol has changed value (would generate different output in
-             autoconf.h compared to before), the change is signaled by
-             touch'ing a file corresponding to the symbol.
-
-             The first time sync_deps() is run on a directory, <path>/auto.conf
-             won't exist, and no old symbol values will be available. This
-             logically has the same effect as updating the entire
-             configuration.
-
-             The path to a symbol's file is calculated from the symbol's name
-             by replacing all '_' with '/' and appending '.h'. For example, the
-             symbol FOO_BAR_BAZ gets the file <path>/foo/bar/baz.h, and FOO
-             gets the file <path>/foo.h.
-
-             This scheme matches the C tools. The point is to avoid having a
-             single directory with a huge number of files, which the underlying
-             filesystem might not handle well.
-
-          3. A new auto.conf with the current symbol values is written, to keep
-             track of them for the next build.
-
-             If auto.conf exists and its contents is identical to what would
-             get written out, it is left untouched. This avoids updating file
-             metadata like the modification time and possibly triggering
-             redundant work in build tools.
-
-
-        The last piece of the puzzle is knowing what symbols each source file
-        depends on. Knowing that, dependencies can be added from source files
-        to the files corresponding to the symbols they depends on. The source
-        file will then get recompiled (only) when the symbol value changes
-        (provided sync_deps() is run first during each build).
-
-        The tool in the kernel that extracts symbol dependencies from source
-        files is scripts/basic/fixdep.c. Missing symbol files also correspond
-        to "not changed", which fixdep deals with by using the $(wildcard) Make
-        function when adding symbol prerequisites to source files.
-
-        In case you need a different scheme for your project, the sync_deps()
-        implementation can be used as a template.
-        """
-        if not exists(path):
-            os.mkdir(path, 0o755)
-
-        # Load old values from auto.conf, if any
-        self._load_old_vals(path)
-
-        for sym in self.unique_defined_syms:
-            # _write_to_conf is determined when the value is calculated. This
-            # is a hidden function call due to property magic.
-            #
-            # Note: In client code, you can check if sym.config_string is empty
-            # instead, to avoid accessing the internal _write_to_conf variable
-            # (though it's likely to keep working).
-            val = sym.str_value
-
-            # n tristate values do not get written to auto.conf and autoconf.h,
-            # making a missing symbol logically equivalent to n
-
-            if sym._write_to_conf:
-                if sym._old_val is None and \
-                   sym.orig_type in _BOOL_TRISTATE and \
-                   val == "n":
-                    # No old value (the symbol was missing or n), new value n.
-                    # No change.
-                    continue
-
-                if val == sym._old_val:
-                    # New value matches old. No change.
-                    continue
-
-            elif sym._old_val is None:
-                # The symbol wouldn't appear in autoconf.h (because
-                # _write_to_conf is false), and it wouldn't have appeared in
-                # autoconf.h previously either (because it didn't appear in
-                # auto.conf). No change.
-                continue
-
-            # 'sym' has a new value. Flag it.
-            _touch_dep_file(path, sym.name)
-
-        # Remember the current values as the "new old" values.
-        #
-        # This call could go anywhere after the call to _load_old_vals(), but
-        # putting it last means _sync_deps() can be safely rerun if it fails
-        # before this point.
-        self._write_old_vals(path)
-
-    def _load_old_vals(self, path):
-        # Loads old symbol values from auto.conf into a dedicated
-        # Symbol._old_val field. Mirrors load_config().
-        #
-        # The extra field could be avoided with some trickery involving dumping
-        # symbol values and restoring them later, but this is simpler and
-        # faster. The C tools also use a dedicated field for this purpose.
-
-        for sym in self.unique_defined_syms:
-            sym._old_val = None
-
-        try:
-            auto_conf = self._open(join(path, "auto.conf"), "r")
-        except EnvironmentError as e:
-            if e.errno == errno.ENOENT:
-                # No old values
-                return
-            raise
-
-        with auto_conf as f:
-            for line in f:
-                match = self._set_match(line)
-                if not match:
-                    # We only expect CONFIG_FOO=... (and possibly a header
-                    # comment) in auto.conf
-                    continue
-
-                name, val = match.groups()
-                if name in self.syms:
-                    sym = self.syms[name]
-
-                    if sym.orig_type is STRING:
-                        match = _conf_string_match(val)
-                        if not match:
-                            continue
-                        val = unescape(match.group(1))
-
-                    self.syms[name]._old_val = val
-                else:
-                    # Flag that the symbol no longer exists, in
-                    # case something still depends on it
-                    _touch_dep_file(path, name)
-
-    def _write_old_vals(self, path):
-        # Helper for writing auto.conf. Basically just a simplified
-        # write_config() that doesn't write any comments (including
-        # '# CONFIG_FOO is not set' comments). The format matches the C
-        # implementation, though the ordering is arbitrary there (depends on
-        # the hash table implementation).
-        #
-        # A separate helper function is neater than complicating write_config()
-        # by passing a flag to it, plus we only need to look at symbols here.
-
-        self._write_if_changed(
-            os.path.join(path, "auto.conf"),
-            self._old_vals_contents())
-
-    def _old_vals_contents(self):
-        # _write_old_vals() helper. Returns the contents to write as a string.
-
-        # Temporary list instead of generator makes this a bit faster
-        return "".join([
-            sym.config_string for sym in self.unique_defined_syms
-                if not (sym.orig_type in _BOOL_TRISTATE and not sym.tri_value)
-        ])
-
-    def node_iter(self, unique_syms=False):
-        """
-        Returns a generator for iterating through all MenuNode's in the Kconfig
-        tree. The iteration is done in Kconfig definition order (each node is
-        visited before its children, and the children of a node are visited
-        before the next node).
-
-        The Kconfig.top_node menu node is skipped. It contains an implicit menu
-        that holds the top-level items.
-
-        As an example, the following code will produce a list equal to
-        Kconfig.defined_syms:
-
-          defined_syms = [node.item for node in kconf.node_iter()
-                          if isinstance(node.item, Symbol)]
-
-        unique_syms (default: False):
-          If True, only the first MenuNode will be included for symbols defined
-          in multiple locations.
-
-          Using kconf.node_iter(True) in the example above would give a list
-          equal to unique_defined_syms.
-        """
-        if unique_syms:
-            for sym in self.unique_defined_syms:
-                sym._visited = False
-
-        node = self.top_node
-        while 1:
-            # Jump to the next node with an iterative tree walk
-            if node.list:
-                node = node.list
-            elif node.next:
-                node = node.next
-            else:
-                while node.parent:
-                    node = node.parent
-                    if node.next:
-                        node = node.next
-                        break
-                else:
-                    # No more nodes
-                    return
-
-            if unique_syms and node.item.__class__ is Symbol:
-                if node.item._visited:
-                    continue
-                node.item._visited = True
-
-            yield node
-
-    def eval_string(self, s):
-        """
-        Returns the tristate value of the expression 's', represented as 0, 1,
-        and 2 for n, m, and y, respectively. Raises KconfigError on syntax
-        errors. Warns if undefined symbols are referenced.
-
-        As an example, if FOO and BAR are tristate symbols at least one of
-        which has the value y, then eval_string("y && (FOO || BAR)") returns
-        2 (y).
-
-        To get the string value of non-bool/tristate symbols, use
-        Symbol.str_value. eval_string() always returns a tristate value, and
-        all non-bool/tristate symbols have the tristate value 0 (n).
-
-        The expression parsing is consistent with how parsing works for
-        conditional ('if ...') expressions in the configuration, and matches
-        the C implementation. m is rewritten to 'm && MODULES', so
-        eval_string("m") will return 0 (n) unless modules are enabled.
-        """
-        # The parser is optimized to be fast when parsing Kconfig files (where
-        # an expression can never appear at the beginning of a line). We have
-        # to monkey-patch things a bit here to reuse it.
-
-        self.filename = None
-
-        self._tokens = self._tokenize("if " + s)
-        # Strip "if " to avoid giving confusing error messages
-        self._line = s
-        self._tokens_i = 1  # Skip the 'if' token
-
-        return expr_value(self._expect_expr_and_eol())
-
-    def unset_values(self):
-        """
-        Removes any user values from all symbols, as if Kconfig.load_config()
-        or Symbol.set_value() had never been called.
-        """
-        self._warn_assign_no_prompt = False
-        try:
-            # set_value() already rejects undefined symbols, and they don't
-            # need to be invalidated (because their value never changes), so we
-            # can just iterate over defined symbols
-            for sym in self.unique_defined_syms:
-                sym.unset_value()
-
-            for choice in self.unique_choices:
-                choice.unset_value()
-        finally:
-            self._warn_assign_no_prompt = True
-
-    def enable_warnings(self):
-        """
-        Do 'Kconfig.warn = True' instead. Maintained for backwards
-        compatibility.
-        """
-        self.warn = True
-
-    def disable_warnings(self):
-        """
-        Do 'Kconfig.warn = False' instead. Maintained for backwards
-        compatibility.
-        """
-        self.warn = False
-
-    def enable_stderr_warnings(self):
-        """
-        Do 'Kconfig.warn_to_stderr = True' instead. Maintained for backwards
-        compatibility.
-        """
-        self.warn_to_stderr = True
-
-    def disable_stderr_warnings(self):
-        """
-        Do 'Kconfig.warn_to_stderr = False' instead. Maintained for backwards
-        compatibility.
-        """
-        self.warn_to_stderr = False
-
-    def enable_undef_warnings(self):
-        """
-        Do 'Kconfig.warn_assign_undef = True' instead. Maintained for backwards
-        compatibility.
-        """
-        self.warn_assign_undef = True
-
-    def disable_undef_warnings(self):
-        """
-        Do 'Kconfig.warn_assign_undef = False' instead. Maintained for
-        backwards compatibility.
-        """
-        self.warn_assign_undef = False
-
-    def enable_override_warnings(self):
-        """
-        Do 'Kconfig.warn_assign_override = True' instead. Maintained for
-        backwards compatibility.
-        """
-        self.warn_assign_override = True
-
-    def disable_override_warnings(self):
-        """
-        Do 'Kconfig.warn_assign_override = False' instead. Maintained for
-        backwards compatibility.
-        """
-        self.warn_assign_override = False
-
-    def enable_redun_warnings(self):
-        """
-        Do 'Kconfig.warn_assign_redun = True' instead. Maintained for backwards
-        compatibility.
-        """
-        self.warn_assign_redun = True
-
-    def disable_redun_warnings(self):
-        """
-        Do 'Kconfig.warn_assign_redun = False' instead. Maintained for
-        backwards compatibility.
-        """
-        self.warn_assign_redun = False
-
-    def __repr__(self):
-        """
-        Returns a string with information about the Kconfig object when it is
-        evaluated on e.g. the interactive Python prompt.
-        """
-        def status(flag):
-            return "enabled" if flag else "disabled"
-
-        return "<{}>".format(", ".join((
-            "configuration with {} symbols".format(len(self.syms)),
-            'main menu prompt "{}"'.format(self.mainmenu_text),
-            "srctree is current directory" if not self.srctree else
-                'srctree "{}"'.format(self.srctree),
-            'config symbol prefix "{}"'.format(self.config_prefix),
-            "warnings " + status(self.warn),
-            "printing of warnings to stderr " + status(self.warn_to_stderr),
-            "undef. symbol assignment warnings " +
-                status(self.warn_assign_undef),
-            "overriding symbol assignment warnings " +
-                status(self.warn_assign_override),
-            "redundant symbol assignment warnings " +
-                status(self.warn_assign_redun)
-        )))
-
-    #
-    # Private methods
-    #
-
-
-    #
-    # File reading
-    #
-
-    def _open_config(self, filename):
-        # Opens a .config file. First tries to open 'filename', then
-        # '$srctree/filename' if $srctree was set when the configuration was
-        # loaded.
-
-        try:
-            return self._open(filename, "r")
-        except EnvironmentError as e:
-            # This will try opening the same file twice if $srctree is unset,
-            # but it's not a big deal
-            try:
-                return self._open(join(self.srctree, filename), "r")
-            except EnvironmentError as e2:
-                # This is needed for Python 3, because e2 is deleted after
-                # the try block:
-                #
-                # https://docs.python.org/3/reference/compound_stmts.html#the-try-statement
-                e = e2
-
-            raise _KconfigIOError(
-                e, "Could not open '{}' ({}: {}). Check that the $srctree "
-                   "environment variable ({}) is set correctly."
-                   .format(filename, errno.errorcode[e.errno], e.strerror,
-                           "set to '{}'".format(self.srctree) if self.srctree
-                               else "unset or blank"))
-
-    def _enter_file(self, filename):
-        # Jumps to the beginning of a sourced Kconfig file, saving the previous
-        # position and file object.
-        #
-        # filename:
-        #   Absolute path to file
-
-        # Path relative to $srctree, stored in e.g. self.filename (which makes
-        # it indirectly show up in MenuNode.filename). Equals 'filename' for
-        # absolute paths passed to 'source'.
-        if filename.startswith(self._srctree_prefix):
-            # Relative path (or a redundant absolute path to within $srctree,
-            # but it's probably fine to reduce those too)
-            rel_filename = filename[len(self._srctree_prefix):]
-        else:
-            # Absolute path
-            rel_filename = filename
-
-        self.kconfig_filenames.append(rel_filename)
-
-        # The parent Kconfig files are represented as a list of
-        # (<include path>, <Python 'file' object for Kconfig file>) tuples.
-        #
-        # <include path> is immutable and holds a *tuple* of
-        # (<filename>, <linenr>) tuples, giving the locations of the 'source'
-        # statements in the parent Kconfig files. The current include path is
-        # also available in Kconfig._include_path.
-        #
-        # The point of this redundant setup is to allow Kconfig._include_path
-        # to be assigned directly to MenuNode.include_path without having to
-        # copy it, sharing it wherever possible.
-
-        # Save include path and 'file' object (via its 'readline' function)
-        # before entering the file
-        self._filestack.append((self._include_path, self._readline))
-
-        # _include_path is a tuple, so this rebinds the variable instead of
-        # doing in-place modification
-        self._include_path += ((self.filename, self.linenr),)
-
-        # Check for recursive 'source'
-        for name, _ in self._include_path:
-            if name == rel_filename:
-                raise KconfigError(
-                    "\n{}:{}: recursive 'source' of '{}' detected. Check that "
-                    "environment variables are set correctly.\n"
-                    "Include path:\n{}"
-                    .format(self.filename, self.linenr, rel_filename,
-                            "\n".join("{}:{}".format(name, linenr)
-                                      for name, linenr in self._include_path)))
-
-        try:
-            self._readline = self._open(filename, "r").readline
-        except EnvironmentError as e:
-            # We already know that the file exists
-            raise _KconfigIOError(
-                e, "{}:{}: Could not open '{}' (in '{}') ({}: {})"
-                   .format(self.filename, self.linenr, filename,
-                           self._line.strip(),
-                           errno.errorcode[e.errno], e.strerror))
-
-        self.filename = rel_filename
-        self.linenr = 0
-
-    def _leave_file(self):
-        # Returns from a Kconfig file to the file that sourced it. See
-        # _enter_file().
-
-        # Restore location from parent Kconfig file
-        self.filename, self.linenr = self._include_path[-1]
-        # Restore include path and 'file' object
-        self._readline.__self__.close()  # __self__ fetches the 'file' object
-        self._include_path, self._readline = self._filestack.pop()
-
-    def _next_line(self):
-        # Fetches and tokenizes the next line from the current Kconfig file.
-        # Returns False at EOF and True otherwise.
-
-        # We might already have tokens from parsing a line and discovering that
-        # it's part of a different construct
-        if self._reuse_tokens:
-            self._reuse_tokens = False
-            # self._tokens_i is known to be 1 here, because _parse_props()
-            # leaves it like that when it can't recognize a line (or parses a
-            # help text)
-            return True
-
-        # readline() returns '' over and over at EOF, which we rely on for help
-        # texts at the end of files (see _line_after_help())
-        line = self._readline()
-        if not line:
-            return False
-        self.linenr += 1
-
-        # Handle line joining
-        while line.endswith("\\\n"):
-            line = line[:-2] + self._readline()
-            self.linenr += 1
-
-        self._tokens = self._tokenize(line)
-        # Initialize to 1 instead of 0 to factor out code from _parse_block()
-        # and _parse_props(). They immediately fetch self._tokens[0].
-        self._tokens_i = 1
-
-        return True
-
-    def _line_after_help(self, line):
-        # Tokenizes a line after a help text. This case is special in that the
-        # line has already been fetched (to discover that it isn't part of the
-        # help text).
-        #
-        # An earlier version used a _saved_line variable instead that was
-        # checked in _next_line(). This special-casing gets rid of it and makes
-        # _reuse_tokens alone sufficient to handle unget.
-
-        # Handle line joining
-        while line.endswith("\\\n"):
-            line = line[:-2] + self._readline()
-            self.linenr += 1
-
-        self._tokens = self._tokenize(line)
-        self._reuse_tokens = True
-
-    def _write_if_changed(self, filename, contents):
-        # Writes 'contents' into 'filename', but only if it differs from the
-        # current contents of the file.
-        #
-        # Another variant would be write a temporary file on the same
-        # filesystem, compare the files, and rename() the temporary file if it
-        # differs, but it breaks stuff like write_config("/dev/null"), which is
-        # used out there to force evaluation-related warnings to be generated.
-        # This simple version is pretty failsafe and portable.
-        #
-        # Returns True if the file has changed and is updated, and False
-        # otherwise.
-
-        if self._contents_eq(filename, contents):
-            return False
-        with self._open(filename, "w") as f:
-            f.write(contents)
-        return True
-
-    def _contents_eq(self, filename, contents):
-        # Returns True if the contents of 'filename' is 'contents' (a string),
-        # and False otherwise (including if 'filename' can't be opened/read)
-
-        try:
-            with self._open(filename, "r") as f:
-                # Robust re. things like encoding and line endings (mmap()
-                # trickery isn't)
-                return f.read(len(contents) + 1) == contents
-        except EnvironmentError:
-            # If the error here would prevent writing the file as well, we'll
-            # notice it later
-            return False
-
-    #
-    # Tokenization
-    #
-
-    def _lookup_sym(self, name):
-        # Fetches the symbol 'name' from the symbol table, creating and
-        # registering it if it does not exist. If '_parsing_kconfigs' is False,
-        # it means we're in eval_string(), and new symbols won't be registered.
-
-        if name in self.syms:
-            return self.syms[name]
-
-        sym = Symbol()
-        sym.kconfig = self
-        sym.name = name
-        sym.is_constant = False
-        sym.rev_dep = sym.weak_rev_dep = sym.direct_dep = self.n
-
-        if self._parsing_kconfigs:
-            self.syms[name] = sym
-        else:
-            self._warn("no symbol {} in configuration".format(name))
-
-        return sym
-
-    def _lookup_const_sym(self, name):
-        # Like _lookup_sym(), for constant (quoted) symbols
-
-        if name in self.const_syms:
-            return self.const_syms[name]
-
-        sym = Symbol()
-        sym.kconfig = self
-        sym.name = name
-        sym.is_constant = True
-        sym.rev_dep = sym.weak_rev_dep = sym.direct_dep = self.n
-
-        if self._parsing_kconfigs:
-            self.const_syms[name] = sym
-
-        return sym
-
-    def _tokenize(self, s):
-        # Parses 's', returning a None-terminated list of tokens. Registers any
-        # new symbols encountered with _lookup(_const)_sym().
-        #
-        # Tries to be reasonably speedy by processing chunks of text via
-        # regexes and string operations where possible. This is the biggest
-        # hotspot during parsing.
-        #
-        # It might be possible to rewrite this to 'yield' tokens instead,
-        # working across multiple lines. Lookback and compatibility with old
-        # janky versions of the C tools complicate things though.
-
-        self._line = s  # Used for error reporting
-
-        # Initial token on the line
-        match = _command_match(s)
-        if not match:
-            if s.isspace() or s.lstrip().startswith("#"):
-                return (None,)
-            self._parse_error("unknown token at start of line")
-
-        # Tricky implementation detail: While parsing a token, 'token' refers
-        # to the previous token. See _STRING_LEX for why this is needed.
-        token = _get_keyword(match.group(1))
-        if not token:
-            # Backwards compatibility with old versions of the C tools, which
-            # (accidentally) accepted stuff like "--help--" and "-help---".
-            # This was fixed in the C tools by commit c2264564 ("kconfig: warn
-            # of unhandled characters in Kconfig commands"), committed in July
-            # 2015, but it seems people still run Kconfiglib on older kernels.
-            if s.strip(" \t\n-") == "help":
-                return (_T_HELP, None)
-
-            # If the first token is not a keyword (and not a weird help token),
-            # we have a preprocessor variable assignment (or a bare macro on a
-            # line)
-            self._parse_assignment(s)
-            return (None,)
-
-        tokens = [token]
-        # The current index in the string being tokenized
-        i = match.end()
-
-        # Main tokenization loop (for tokens past the first one)
-        while i < len(s):
-            # Test for an identifier/keyword first. This is the most common
-            # case.
-            match = _id_keyword_match(s, i)
-            if match:
-                # We have an identifier or keyword
-
-                # Check what it is. lookup_sym() will take care of allocating
-                # new symbols for us the first time we see them. Note that
-                # 'token' still refers to the previous token.
-
-                name = match.group(1)
-                keyword = _get_keyword(name)
-                if keyword:
-                    # It's a keyword
-                    token = keyword
-                    # Jump past it
-                    i = match.end()
-
-                elif token not in _STRING_LEX:
-                    # It's a non-const symbol, except we translate n, m, and y
-                    # into the corresponding constant symbols, like the C
-                    # implementation
-
-                    if "$" in name:
-                        # Macro expansion within symbol name
-                        name, s, i = self._expand_name(s, i)
-                    else:
-                        i = match.end()
-
-                    token = self.const_syms[name] if name in STR_TO_TRI else \
-                        self._lookup_sym(name)
-
-                else:
-                    # It's a case of missing quotes. For example, the
-                    # following is accepted:
-                    #
-                    #   menu unquoted_title
-                    #
-                    #   config A
-                    #       tristate unquoted_prompt
-                    #
-                    #   endmenu
-                    #
-                    # Named choices ('choice FOO') also end up here.
-
-                    if token is not _T_CHOICE:
-                        self._warn("style: quotes recommended around '{}' in '{}'"
-                                   .format(name, self._line.strip()),
-                                   self.filename, self.linenr)
-
-                    token = name
-                    i = match.end()
-
-            else:
-                # Neither a keyword nor a non-const symbol
-
-                # We always strip whitespace after tokens, so it is safe to
-                # assume that s[i] is the start of a token here.
-                c = s[i]
-
-                if c in "\"'":
-                    if "$" not in s and "\\" not in s:
-                        # Fast path for lines without $ and \. Find the
-                        # matching quote.
-                        end_i = s.find(c, i + 1) + 1
-                        if not end_i:
-                            self._parse_error("unterminated string")
-                        val = s[i + 1:end_i - 1]
-                        i = end_i
-                    else:
-                        # Slow path
-                        s, end_i = self._expand_str(s, i)
-
-                        # os.path.expandvars() and the $UNAME_RELEASE replace()
-                        # is a backwards compatibility hack, which should be
-                        # reasonably safe as expandvars() leaves references to
-                        # undefined env. vars. as is.
-                        #
-                        # The preprocessor functionality changed how
-                        # environment variables are referenced, to $(FOO).
-                        val = expandvars(s[i + 1:end_i - 1]
-                                         .replace("$UNAME_RELEASE",
-                                                  _UNAME_RELEASE))
-
-                        i = end_i
-
-                    # This is the only place where we don't survive with a
-                    # single token of lookback: 'option env="FOO"' does not
-                    # refer to a constant symbol named "FOO".
-                    token = \
-                        val if token in _STRING_LEX or tokens[0] is _T_OPTION \
-                        else self._lookup_const_sym(val)
-
-                elif s.startswith("&&", i):
-                    token = _T_AND
-                    i += 2
-
-                elif s.startswith("||", i):
-                    token = _T_OR
-                    i += 2
-
-                elif c == "=":
-                    token = _T_EQUAL
-                    i += 1
-
-                elif s.startswith("!=", i):
-                    token = _T_UNEQUAL
-                    i += 2
-
-                elif c == "!":
-                    token = _T_NOT
-                    i += 1
-
-                elif c == "(":
-                    token = _T_OPEN_PAREN
-                    i += 1
-
-                elif c == ")":
-                    token = _T_CLOSE_PAREN
-                    i += 1
-
-                elif c == "#":
-                    break
-
-
-                # Very rare
-
-                elif s.startswith("<=", i):
-                    token = _T_LESS_EQUAL
-                    i += 2
-
-                elif c == "<":
-                    token = _T_LESS
-                    i += 1
-
-                elif s.startswith(">=", i):
-                    token = _T_GREATER_EQUAL
-                    i += 2
-
-                elif c == ">":
-                    token = _T_GREATER
-                    i += 1
-
-
-                else:
-                    self._parse_error("unknown tokens in line")
-
-
-                # Skip trailing whitespace
-                while i < len(s) and s[i].isspace():
-                    i += 1
-
-
-            # Add the token
-            tokens.append(token)
-
-        # None-terminating the token list makes token fetching simpler/faster
-        tokens.append(None)
-
-        return tokens
-
-    # Helpers for syntax checking and token fetching. See the
-    # 'Intro to expressions' section for what a constant symbol is.
-    #
-    # More of these could be added, but the single-use cases are inlined as an
-    # optimization.
-
-    def _expect_sym(self):
-        token = self._tokens[self._tokens_i]
-        self._tokens_i += 1
-
-        if token.__class__ is not Symbol:
-            self._parse_error("expected symbol")
-
-        return token
-
-    def _expect_nonconst_sym(self):
-        # Used for 'select' and 'imply' only. We know the token indices.
-
-        token = self._tokens[1]
-        self._tokens_i = 2
-
-        if token.__class__ is not Symbol or token.is_constant:
-            self._parse_error("expected nonconstant symbol")
-
-        return token
-
-    def _expect_str_and_eol(self):
-        token = self._tokens[self._tokens_i]
-        self._tokens_i += 1
-
-        if token.__class__ is not str:
-            self._parse_error("expected string")
-
-        if self._tokens[self._tokens_i] is not None:
-            self._trailing_tokens_error()
-
-        return token
-
-    def _expect_expr_and_eol(self):
-        expr = self._parse_expr(True)
-
-        if self._tokens[self._tokens_i] is not None:
-            self._trailing_tokens_error()
-
-        return expr
-
-    def _check_token(self, token):
-        # If the next token is 'token', removes it and returns True
-
-        if self._tokens[self._tokens_i] is token:
-            self._tokens_i += 1
-            return True
-        return False
-
-    #
-    # Preprocessor logic
-    #
-
-    def _parse_assignment(self, s):
-        # Parses a preprocessor variable assignment, registering the variable
-        # if it doesn't already exist. Also takes care of bare macros on lines
-        # (which are allowed, and can be useful for their side effects).
-
-        # Expand any macros in the left-hand side of the assignment (the
-        # variable name)
-        s = s.lstrip()
-        i = 0
-        while 1:
-            i = _assignment_lhs_fragment_match(s, i).end()
-            if s.startswith("$(", i):
-                s, i = self._expand_macro(s, i, ())
-            else:
-                break
-
-        if s.isspace():
-            # We also accept a bare macro on a line (e.g.
-            # $(warning-if,$(foo),ops)), provided it expands to a blank string
-            return
-
-        # Assigned variable
-        name = s[:i]
-
-
-        # Extract assignment operator (=, :=, or +=) and value
-        rhs_match = _assignment_rhs_match(s, i)
-        if not rhs_match:
-            self._parse_error("syntax error")
-
-        op, val = rhs_match.groups()
-
-
-        if name in self.variables:
-            # Already seen variable
-            var = self.variables[name]
-        else:
-            # New variable
-            var = Variable()
-            var.kconfig = self
-            var.name = name
-            var._n_expansions = 0
-            self.variables[name] = var
-
-            # += acts like = on undefined variables (defines a recursive
-            # variable)
-            if op == "+=":
-                op = "="
-
-        if op == "=":
-            var.is_recursive = True
-            var.value = val
-        elif op == ":=":
-            var.is_recursive = False
-            var.value = self._expand_whole(val, ())
-        else:  # op == "+="
-            # += does immediate expansion if the variable was last set
-            # with :=
-            var.value += " " + (val if var.is_recursive else
-                                self._expand_whole(val, ()))
-
-    def _expand_whole(self, s, args):
-        # Expands preprocessor macros in all of 's'. Used whenever we don't
-        # have to worry about delimiters. See _expand_macro() re. the 'args'
-        # parameter.
-        #
-        # Returns the expanded string.
-
-        i = 0
-        while 1:
-            i = s.find("$(", i)
-            if i == -1:
-                break
-            s, i = self._expand_macro(s, i, args)
-        return s
-
-    def _expand_name(self, s, i):
-        # Expands a symbol name starting at index 'i' in 's'.
-        #
-        # Returns the expanded name, the expanded 's' (including the part
-        # before the name), and the index of the first character in the next
-        # token after the name.
-
-        s, end_i = self._expand_name_iter(s, i)
-        name = s[i:end_i]
-        # isspace() is False for empty strings
-        if not name.strip():
-            # Avoid creating a Kconfig symbol with a blank name. It's almost
-            # guaranteed to be an error.
-            if not self.allow_empty_macros:
-                self._parse_error("macro expanded to blank string")
-
-        # Skip trailing whitespace
-        while end_i < len(s) and s[end_i].isspace():
-            end_i += 1
-
-        return name, s, end_i
-
-    def _expand_name_iter(self, s, i):
-        # Expands a symbol name starting at index 'i' in 's'.
-        #
-        # Returns the expanded 's' (including the part before the name) and the
-        # index of the first character after the expanded name in 's'.
-
-        while 1:
-            match = _name_special_search(s, i)
-
-            if match.group() != "$(":
-                return (s, match.start())
-            s, i = self._expand_macro(s, match.start(), ())
-
-    def _expand_str(self, s, i):
-        # Expands a quoted string starting at index 'i' in 's'. Handles both
-        # backslash escapes and macro expansion.
-        #
-        # Returns the expanded 's' (including the part before the string) and
-        # the index of the first character after the expanded string in 's'.
-
-        quote = s[i]
-        i += 1  # Skip over initial "/'
-        while 1:
-            match = _string_special_search(s, i)
-            if not match:
-                self._parse_error("unterminated string")
-
-
-            if match.group() == quote:
-                # Found the end of the string
-                return (s, match.end())
-
-            elif match.group() == "\\":
-                # Replace '\x' with 'x'. 'i' ends up pointing to the character
-                # after 'x', which allows macros to be canceled with '\$(foo)'.
-                i = match.end()
-                s = s[:match.start()] + s[i:]
-
-            elif match.group() == "$(":
-                # A macro call within the string
-                s, i = self._expand_macro(s, match.start(), ())
-
-            else:
-                # A ' quote within " quotes or vice versa
-                i += 1
-
-    def _expand_macro(self, s, i, args):
-        # Expands a macro starting at index 'i' in 's'. If this macro resulted
-        # from the expansion of another macro, 'args' holds the arguments
-        # passed to that macro.
-        #
-        # Returns the expanded 's' (including the part before the macro) and
-        # the index of the first character after the expanded macro in 's'.
-
-        res = s[:i]
-        i += 2  # Skip over "$("
-
-        arg_start = i  # Start of current macro argument
-        new_args = []  # Arguments of this macro call
-        nesting = 0  # Current parentheses nesting level
-
-        while 1:
-            match = _macro_special_search(s, i)
-            if not match:
-                self._parse_error("missing end parenthesis in macro expansion")
-
-
-            if match.group() == "(":
-                nesting += 1
-                i = match.end()
-
-            elif match.group() == ")":
-                if nesting:
-                    nesting -= 1
-                    i = match.end()
-                    continue
-
-                # Found the end of the macro
-
-                new_args.append(s[arg_start:match.start()])
-
-                # $(1) is replaced by the first argument to the function, etc.,
-                # provided at least that many arguments were passed
-
-                try:
-                    # Does the macro look like an integer, with a corresponding
-                    # argument? If so, expand it to the value of the argument.
-                    res += args[int(new_args[0])]
-                except (ValueError, IndexError):
-                    # Regular variables are just functions without arguments,
-                    # and also go through the function value path
-                    res += self._fn_val(new_args)
-
-                return (res + s[match.end():], len(res))
-
-            elif match.group() == ",":
-                i = match.end()
-                if nesting:
-                    continue
-
-                # Found the end of a macro argument
-                new_args.append(s[arg_start:match.start()])
-                arg_start = i
-
-            else:  # match.group() == "$("
-                # A nested macro call within the macro
-                s, i = self._expand_macro(s, match.start(), args)
-
-    def _fn_val(self, args):
-        # Returns the result of calling the function args[0] with the arguments
-        # args[1..len(args)-1]. Plain variables are treated as functions
-        # without arguments.
-
-        fn = args[0]
-
-        if fn in self.variables:
-            var = self.variables[fn]
-
-            if len(args) == 1:
-                # Plain variable
-                if var._n_expansions:
-                    self._parse_error("Preprocessor variable {} recursively "
-                                      "references itself".format(var.name))
-            elif var._n_expansions > 100:
-                # Allow functions to call themselves, but guess that functions
-                # that are overly recursive are stuck
-                self._parse_error("Preprocessor function {} seems stuck "
-                                  "in infinite recursion".format(var.name))
-
-            var._n_expansions += 1
-            res = self._expand_whole(self.variables[fn].value, args)
-            var._n_expansions -= 1
-            return res
-
-        if fn in self._functions:
-            # Built-in or user-defined function
-
-            py_fn, min_arg, max_arg = self._functions[fn]
-
-            if len(args) - 1 < min_arg or \
-               (max_arg is not None and len(args) - 1 > max_arg):
-
-                if min_arg == max_arg:
-                    expected_args = min_arg
-                elif max_arg is None:
-                    expected_args = "{} or more".format(min_arg)
-                else:
-                    expected_args = "{}-{}".format(min_arg, max_arg)
-
-                raise KconfigError("{}:{}: bad number of arguments in call "
-                                   "to {}, expected {}, got {}"
-                                   .format(self.filename, self.linenr, fn,
-                                           expected_args, len(args) - 1))
-
-            return py_fn(self, *args)
-
-        # Environment variables are tried last
-        if fn in os.environ:
-            self.env_vars.add(fn)
-            return os.environ[fn]
-
-        return ""
-
-    #
-    # Parsing
-    #
-
-    def _make_and(self, e1, e2):
-        # Constructs an AND (&&) expression. Performs trivial simplification.
-
-        if e1 is self.y:
-            return e2
-
-        if e2 is self.y:
-            return e1
-
-        if e1 is self.n or e2 is self.n:
-            return self.n
-
-        return (AND, e1, e2)
-
-    def _make_or(self, e1, e2):
-        # Constructs an OR (||) expression. Performs trivial simplification.
-
-        if e1 is self.n:
-            return e2
-
-        if e2 is self.n:
-            return e1
-
-        if e1 is self.y or e2 is self.y:
-            return self.y
-
-        return (OR, e1, e2)
-
-    def _parse_block(self, end_token, parent, prev):
-        # Parses a block, which is the contents of either a file or an if,
-        # menu, or choice statement.
-        #
-        # end_token:
-        #   The token that ends the block, e.g. _T_ENDIF ("endif") for ifs.
-        #   None for files.
-        #
-        # parent:
-        #   The parent menu node, corresponding to a menu, Choice, or 'if'.
-        #   'if's are flattened after parsing.
-        #
-        # prev:
-        #   The previous menu node. New nodes will be added after this one (by
-        #   modifying 'next' pointers).
-        #
-        #   'prev' is reused to parse a list of child menu nodes (for a menu or
-        #   Choice): After parsing the children, the 'next' pointer is assigned
-        #   to the 'list' pointer to "tilt up" the children above the node.
-        #
-        # Returns the final menu node in the block (or 'prev' if the block is
-        # empty). This allows chaining.
-
-        while self._next_line():
-            t0 = self._tokens[0]
-
-            if t0 is _T_CONFIG or t0 is _T_MENUCONFIG:
-                # The tokenizer allocates Symbol objects for us
-                sym = self._tokens[1]
-
-                if sym.__class__ is not Symbol or sym.is_constant:
-                    self._parse_error("missing or bad symbol name")
-
-                if self._tokens[2] is not None:
-                    self._trailing_tokens_error()
-
-                self.defined_syms.append(sym)
-
-                node = MenuNode()
-                node.kconfig = self
-                node.item = sym
-                node.is_menuconfig = (t0 is _T_MENUCONFIG)
-                node.prompt = node.help = node.list = None
-                node.parent = parent
-                node.filename = self.filename
-                node.linenr = self.linenr
-                node.include_path = self._include_path
-
-                sym.nodes.append(node)
-
-                self._parse_props(node)
-
-                if node.is_menuconfig and not node.prompt:
-                    self._warn("the menuconfig symbol {} has no prompt"
-                               .format(sym.name_and_loc))
-
-                # Equivalent to
-                #
-                #   prev.next = node
-                #   prev = node
-                #
-                # due to tricky Python semantics. The order matters.
-                prev.next = prev = node
-
-            elif t0 is None:
-                # Blank line
-                continue
-
-            elif t0 in _SOURCE_TOKENS:
-                pattern = self._expect_str_and_eol()
-
-                if t0 in _REL_SOURCE_TOKENS:
-                    # Relative source
-                    pattern = join(dirname(self.filename), pattern)
-
-                # - glob() doesn't support globbing relative to a directory, so
-                #   we need to prepend $srctree to 'pattern'. Use join()
-                #   instead of '+' so that an absolute path in 'pattern' is
-                #   preserved.
-                #
-                # - Sort the glob results to ensure a consistent ordering of
-                #   Kconfig symbols, which indirectly ensures a consistent
-                #   ordering in e.g. .config files
-                filenames = sorted(iglob(join(self._srctree_prefix, pattern)))
-                if self.search_paths:
-                    for prefix in self.search_paths:
-                        filenames += sorted(iglob(join(prefix, pattern)))
-
-                if not filenames and t0 in _OBL_SOURCE_TOKENS:
-                    raise KconfigError(
-                        "{}:{}: '{}' not found (in '{}'). Check that "
-                        "environment variables are set correctly (e.g. "
-                        "$srctree, which is {}). Also note that unset "
-                        "environment variables expand to the empty string."
-                        .format(self.filename, self.linenr, pattern,
-                                self._line.strip(),
-                                "set to '{}'".format(self.srctree)
-                                    if self.srctree else "unset or blank"))
-
-                for filename in filenames:
-                    self._enter_file(filename)
-                    prev = self._parse_block(None, parent, prev)
-                    self._leave_file()
-
-            elif t0 is end_token:
-                # Reached the end of the block. Terminate the final node and
-                # return it.
-
-                if self._tokens[1] is not None:
-                    self._trailing_tokens_error()
-
-                prev.next = None
-                return prev
-
-            elif t0 is _T_IF:
-                node = MenuNode()
-                node.item = node.prompt = None
-                node.parent = parent
-                node.dep = self._expect_expr_and_eol()
-
-                self._parse_block(_T_ENDIF, node, node)
-                node.list = node.next
-
-                prev.next = prev = node
-
-            elif t0 is _T_MENU:
-                node = MenuNode()
-                node.kconfig = self
-                node.item = t0  # _T_MENU == MENU
-                node.is_menuconfig = True
-                node.prompt = (self._expect_str_and_eol(), self.y)
-                node.visibility = self.y
-                node.parent = parent
-                node.filename = self.filename
-                node.linenr = self.linenr
-                node.include_path = self._include_path
-
-                self.menus.append(node)
-
-                self._parse_props(node)
-                self._parse_block(_T_ENDMENU, node, node)
-                node.list = node.next
-
-                prev.next = prev = node
-
-            elif t0 is _T_COMMENT:
-                node = MenuNode()
-                node.kconfig = self
-                node.item = t0  # _T_COMMENT == COMMENT
-                node.is_menuconfig = False
-                node.prompt = (self._expect_str_and_eol(), self.y)
-                node.list = None
-                node.parent = parent
-                node.filename = self.filename
-                node.linenr = self.linenr
-                node.include_path = self._include_path
-
-                self.comments.append(node)
-
-                self._parse_props(node)
-
-                prev.next = prev = node
-
-            elif t0 is _T_CHOICE:
-                if self._tokens[1] is None:
-                    choice = Choice()
-                    choice.direct_dep = self.n
-                else:
-                    # Named choice
-                    name = self._expect_str_and_eol()
-                    choice = self.named_choices.get(name)
-                    if not choice:
-                        choice = Choice()
-                        choice.name = name
-                        choice.direct_dep = self.n
-                        self.named_choices[name] = choice
-
-                self.choices.append(choice)
-
-                node = MenuNode()
-                node.kconfig = choice.kconfig = self
-                node.item = choice
-                node.is_menuconfig = True
-                node.prompt = node.help = None
-                node.parent = parent
-                node.filename = self.filename
-                node.linenr = self.linenr
-                node.include_path = self._include_path
-
-                choice.nodes.append(node)
-
-                self._parse_props(node)
-                self._parse_block(_T_ENDCHOICE, node, node)
-                node.list = node.next
-
-                prev.next = prev = node
-
-            elif t0 is _T_MAINMENU:
-                self.top_node.prompt = (self._expect_str_and_eol(), self.y)
-
-            else:
-                # A valid endchoice/endif/endmenu is caught by the 'end_token'
-                # check above
-                self._parse_error(
-                    "no corresponding 'choice'" if t0 is _T_ENDCHOICE else
-                    "no corresponding 'if'"     if t0 is _T_ENDIF else
-                    "no corresponding 'menu'"   if t0 is _T_ENDMENU else
-                    "unrecognized construct")
-
-        # End of file reached. Return the last node.
-
-        if end_token:
-            raise KconfigError(
-                "error: expected '{}' at end of '{}'"
-                .format("endchoice" if end_token is _T_ENDCHOICE else
-                        "endif"     if end_token is _T_ENDIF else
-                        "endmenu",
-                        self.filename))
-
-        return prev
-
-    def _parse_cond(self):
-        # Parses an optional 'if <expr>' construct and returns the parsed
-        # <expr>, or self.y if the next token is not _T_IF
-
-        expr = self._parse_expr(True) if self._check_token(_T_IF) else self.y
-
-        if self._tokens[self._tokens_i] is not None:
-            self._trailing_tokens_error()
-
-        return expr
-
-    def _parse_props(self, node):
-        # Parses and adds properties to the MenuNode 'node' (type, 'prompt',
-        # 'default's, etc.) Properties are later copied up to symbols and
-        # choices in a separate pass after parsing, in e.g.
-        # _add_props_to_sym().
-        #
-        # An older version of this code added properties directly to symbols
-        # and choices instead of to their menu nodes (and handled dependency
-        # propagation simultaneously), but that loses information on where a
-        # property is added when a symbol or choice is defined in multiple
-        # locations. Some Kconfig configuration systems rely heavily on such
-        # symbols, and better docs can be generated by keeping track of where
-        # properties are added.
-        #
-        # node:
-        #   The menu node we're parsing properties on
-
-        # Dependencies from 'depends on'. Will get propagated to the properties
-        # below.
-        node.dep = self.y
-
-        while self._next_line():
-            t0 = self._tokens[0]
-
-            if t0 in _TYPE_TOKENS:
-                # Relies on '_T_BOOL is BOOL', etc., to save a conversion
-                self._set_type(node.item, t0)
-                if self._tokens[1] is not None:
-                    self._parse_prompt(node)
-
-            elif t0 is _T_DEPENDS:
-                if not self._check_token(_T_ON):
-                    self._parse_error("expected 'on' after 'depends'")
-
-                node.dep = self._make_and(node.dep,
-                                          self._expect_expr_and_eol())
-
-            elif t0 is _T_HELP:
-                self._parse_help(node)
-
-            elif t0 is _T_SELECT:
-                if node.item.__class__ is not Symbol:
-                    self._parse_error("only symbols can select")
-
-                node.selects.append((self._expect_nonconst_sym(),
-                                     self._parse_cond()))
-
-            elif t0 is None:
-                # Blank line
-                continue
-
-            elif t0 is _T_DEFAULT:
-                node.defaults.append((self._parse_expr(False),
-                                      self._parse_cond()))
-
-            elif t0 in _DEF_TOKEN_TO_TYPE:
-                self._set_type(node.item, _DEF_TOKEN_TO_TYPE[t0])
-                node.defaults.append((self._parse_expr(False),
-                                      self._parse_cond()))
-
-            elif t0 is _T_PROMPT:
-                self._parse_prompt(node)
-
-            elif t0 is _T_RANGE:
-                node.ranges.append((self._expect_sym(), self._expect_sym(),
-                                    self._parse_cond()))
-
-            elif t0 is _T_IMPLY:
-                if node.item.__class__ is not Symbol:
-                    self._parse_error("only symbols can imply")
-
-                node.implies.append((self._expect_nonconst_sym(),
-                                     self._parse_cond()))
-
-            elif t0 is _T_VISIBLE:
-                if not self._check_token(_T_IF):
-                    self._parse_error("expected 'if' after 'visible'")
-
-                node.visibility = self._make_and(node.visibility,
-                                                 self._expect_expr_and_eol())
-
-            elif t0 is _T_OPTION:
-                if self._check_token(_T_ENV):
-                    if not self._check_token(_T_EQUAL):
-                        self._parse_error("expected '=' after 'env'")
-
-                    env_var = self._expect_str_and_eol()
-                    node.item.env_var = env_var
-
-                    if env_var in os.environ:
-                        node.defaults.append(
-                            (self._lookup_const_sym(os.environ[env_var]),
-                             self.y))
-                    else:
-                        self._warn("{1} has 'option env=\"{0}\"', "
-                                   "but the environment variable {0} is not "
-                                   "set".format(node.item.name, env_var),
-                                   self.filename, self.linenr)
-
-                    if env_var != node.item.name:
-                        self._warn("Kconfiglib expands environment variables "
-                                   "in strings directly, meaning you do not "
-                                   "need 'option env=...' \"bounce\" symbols. "
-                                   "For compatibility with the C tools, "
-                                   "rename {} to {} (so that the symbol name "
-                                   "matches the environment variable name)."
-                                   .format(node.item.name, env_var),
-                                   self.filename, self.linenr)
-
-                elif self._check_token(_T_DEFCONFIG_LIST):
-                    if not self.defconfig_list:
-                        self.defconfig_list = node.item
-                    else:
-                        self._warn("'option defconfig_list' set on multiple "
-                                   "symbols ({0} and {1}). Only {0} will be "
-                                   "used.".format(self.defconfig_list.name,
-                                                  node.item.name),
-                                   self.filename, self.linenr)
-
-                elif self._check_token(_T_MODULES):
-                    # To reduce warning spam, only warn if 'option modules' is
-                    # set on some symbol that isn't MODULES, which should be
-                    # safe. I haven't run into any projects that make use
-                    # modules besides the kernel yet, and there it's likely to
-                    # keep being called "MODULES".
-                    if node.item is not self.modules:
-                        self._warn("the 'modules' option is not supported. "
-                                   "Let me know if this is a problem for you, "
-                                   "as it wouldn't be that hard to implement. "
-                                   "Note that modules are supported -- "
-                                   "Kconfiglib just assumes the symbol name "
-                                   "MODULES, like older versions of the C "
-                                   "implementation did when 'option modules' "
-                                   "wasn't used.",
-                                   self.filename, self.linenr)
-
-                elif self._check_token(_T_ALLNOCONFIG_Y):
-                    if node.item.__class__ is not Symbol:
-                        self._parse_error("the 'allnoconfig_y' option is only "
-                                          "valid for symbols")
-
-                    node.item.is_allnoconfig_y = True
-
-                else:
-                    self._parse_error("unrecognized option")
-
-            elif t0 is _T_OPTIONAL:
-                if node.item.__class__ is not Choice:
-                    self._parse_error('"optional" is only valid for choices')
-
-                node.item.is_optional = True
-
-            else:
-                # Reuse the tokens for the non-property line later
-                self._reuse_tokens = True
-                return
-
-    def _set_type(self, sc, new_type):
-        # Sets the type of 'sc' (symbol or choice) to 'new_type'
-
-        # UNKNOWN is falsy
-        if sc.orig_type and sc.orig_type is not new_type:
-            self._warn("{} defined with multiple types, {} will be used"
-                       .format(sc.name_and_loc, TYPE_TO_STR[new_type]))
-
-        sc.orig_type = new_type
-
-    def _parse_prompt(self, node):
-        # 'prompt' properties override each other within a single definition of
-        # a symbol, but additional prompts can be added by defining the symbol
-        # multiple times
-
-        if node.prompt:
-            self._warn(node.item.name_and_loc +
-                       " defined with multiple prompts in single location")
-
-        prompt = self._tokens[1]
-        self._tokens_i = 2
-
-        if prompt.__class__ is not str:
-            self._parse_error("expected prompt string")
-
-        if prompt != prompt.strip():
-            self._warn(node.item.name_and_loc +
-                       " has leading or trailing whitespace in its prompt")
-
-            # This avoid issues for e.g. reStructuredText documentation, where
-            # '*prompt *' is invalid
-            prompt = prompt.strip()
-
-        node.prompt = (prompt, self._parse_cond())
-
-    def _parse_help(self, node):
-        if node.help is not None:
-            self._warn(node.item.name_and_loc + " defined with more than "
-                       "one help text -- only the last one will be used")
-
-        # Micro-optimization. This code is pretty hot.
-        readline = self._readline
-
-        # Find first non-blank (not all-space) line and get its
-        # indentation
-
-        while 1:
-            line = readline()
-            self.linenr += 1
-            if not line:
-                self._empty_help(node, line)
-                return
-            if not line.isspace():
-                break
-
-        len_ = len  # Micro-optimization
-
-        # Use a separate 'expline' variable here and below to avoid stomping on
-        # any tabs people might've put deliberately into the first line after
-        # the help text
-        expline = line.expandtabs()
-        indent = len_(expline) - len_(expline.lstrip())
-        if not indent:
-            self._empty_help(node, line)
-            return
-
-        # The help text goes on till the first non-blank line with less indent
-        # than the first line
-
-        # Add the first line
-        lines = [expline[indent:]]
-        add_line = lines.append  # Micro-optimization
-
-        while 1:
-            line = readline()
-            if line.isspace():
-                # No need to preserve the exact whitespace in these
-                add_line("\n")
-            elif not line:
-                # End of file
-                break
-            else:
-                expline = line.expandtabs()
-                if len_(expline) - len_(expline.lstrip()) < indent:
-                    break
-                add_line(expline[indent:])
-
-        self.linenr += len_(lines)
-        node.help = "".join(lines).rstrip()
-        if line:
-            self._line_after_help(line)
-
-    def _empty_help(self, node, line):
-        self._warn(node.item.name_and_loc +
-                   " has 'help' but empty help text")
-        node.help = ""
-        if line:
-            self._line_after_help(line)
-
-    def _parse_expr(self, transform_m):
-        # Parses an expression from the tokens in Kconfig._tokens using a
-        # simple top-down approach. See the module docstring for the expression
-        # format.
-        #
-        # transform_m:
-        #   True if m should be rewritten to m && MODULES. See the
-        #   Kconfig.eval_string() documentation.
-
-        # Grammar:
-        #
-        #   expr:     and_expr ['||' expr]
-        #   and_expr: factor ['&&' and_expr]
-        #   factor:   <symbol> ['='/'!='/'<'/... <symbol>]
-        #             '!' factor
-        #             '(' expr ')'
-        #
-        # It helps to think of the 'expr: and_expr' case as a single-operand OR
-        # (no ||), and of the 'and_expr: factor' case as a single-operand AND
-        # (no &&). Parsing code is always a bit tricky.
-
-        # Mind dump: parse_factor() and two nested loops for OR and AND would
-        # work as well. The straightforward implementation there gives a
-        # (op, (op, (op, A, B), C), D) parse for A op B op C op D. Representing
-        # expressions as (op, [list of operands]) instead goes nicely with that
-        # version, but is wasteful for short expressions and complicates
-        # expression evaluation and other code that works on expressions (more
-        # complicated code likely offsets any performance gain from less
-        # recursion too). If we also try to optimize the list representation by
-        # merging lists when possible (e.g. when ANDing two AND expressions),
-        # we end up allocating a ton of lists instead of reusing expressions,
-        # which is bad.
-
-        and_expr = self._parse_and_expr(transform_m)
-
-        # Return 'and_expr' directly if we have a "single-operand" OR.
-        # Otherwise, parse the expression on the right and make an OR node.
-        # This turns A || B || C || D into (OR, A, (OR, B, (OR, C, D))).
-        return and_expr if not self._check_token(_T_OR) else \
-            (OR, and_expr, self._parse_expr(transform_m))
-
-    def _parse_and_expr(self, transform_m):
-        factor = self._parse_factor(transform_m)
-
-        # Return 'factor' directly if we have a "single-operand" AND.
-        # Otherwise, parse the right operand and make an AND node. This turns
-        # A && B && C && D into (AND, A, (AND, B, (AND, C, D))).
-        return factor if not self._check_token(_T_AND) else \
-            (AND, factor, self._parse_and_expr(transform_m))
-
-    def _parse_factor(self, transform_m):
-        token = self._tokens[self._tokens_i]
-        self._tokens_i += 1
-
-        if token.__class__ is Symbol:
-            # Plain symbol or relation
-
-            if self._tokens[self._tokens_i] not in _RELATIONS:
-                # Plain symbol
-
-                # For conditional expressions ('depends on <expr>',
-                # '... if <expr>', etc.), m is rewritten to m && MODULES.
-                if transform_m and token is self.m:
-                    return (AND, self.m, self.modules)
-
-                return token
-
-            # Relation
-            #
-            # _T_EQUAL, _T_UNEQUAL, etc., deliberately have the same values as
-            # EQUAL, UNEQUAL, etc., so we can just use the token directly
-            self._tokens_i += 1
-            return (self._tokens[self._tokens_i - 1], token,
-                    self._expect_sym())
-
-        if token is _T_NOT:
-            # token == _T_NOT == NOT
-            return (token, self._parse_factor(transform_m))
-
-        if token is _T_OPEN_PAREN:
-            expr_parse = self._parse_expr(transform_m)
-            if self._check_token(_T_CLOSE_PAREN):
-                return expr_parse
-
-        self._parse_error("malformed expression")
-
-    #
-    # Caching and invalidation
-    #
-
-    def _build_dep(self):
-        # Populates the Symbol/Choice._dependents sets, which contain all other
-        # items (symbols and choices) that immediately depend on the item in
-        # the sense that changing the value of the item might affect the value
-        # of the dependent items. This is used for caching/invalidation.
-        #
-        # The calculated sets might be larger than necessary as we don't do any
-        # complex analysis of the expressions.
-
-        depend_on = _depend_on  # Micro-optimization
-
-        # Only calculate _dependents for defined symbols. Constant and
-        # undefined symbols could theoretically be selected/implied, but it
-        # wouldn't change their value, so it's not a true dependency.
-        for sym in self.unique_defined_syms:
-            # Symbols depend on the following:
-
-            # The prompt conditions
-            for node in sym.nodes:
-                if node.prompt:
-                    depend_on(sym, node.prompt[1])
-
-            # The default values and their conditions
-            for value, cond in sym.defaults:
-                depend_on(sym, value)
-                depend_on(sym, cond)
-
-            # The reverse and weak reverse dependencies
-            depend_on(sym, sym.rev_dep)
-            depend_on(sym, sym.weak_rev_dep)
-
-            # The ranges along with their conditions
-            for low, high, cond in sym.ranges:
-                depend_on(sym, low)
-                depend_on(sym, high)
-                depend_on(sym, cond)
-
-            # The direct dependencies. This is usually redundant, as the direct
-            # dependencies get propagated to properties, but it's needed to get
-            # invalidation solid for 'imply', which only checks the direct
-            # dependencies (even if there are no properties to propagate it
-            # to).
-            depend_on(sym, sym.direct_dep)
-
-            # In addition to the above, choice symbols depend on the choice
-            # they're in, but that's handled automatically since the Choice is
-            # propagated to the conditions of the properties before
-            # _build_dep() runs.
-
-        for choice in self.unique_choices:
-            # Choices depend on the following:
-
-            # The prompt conditions
-            for node in choice.nodes:
-                if node.prompt:
-                    depend_on(choice, node.prompt[1])
-
-            # The default symbol conditions
-            for _, cond in choice.defaults:
-                depend_on(choice, cond)
-
-    def _add_choice_deps(self):
-        # Choices also depend on the choice symbols themselves, because the
-        # y-mode selection of the choice might change if a choice symbol's
-        # visibility changes.
-        #
-        # We add these dependencies separately after dependency loop detection.
-        # The invalidation algorithm can handle the resulting
-        # <choice symbol> <-> <choice> dependency loops, but they make loop
-        # detection awkward.
-
-        for choice in self.unique_choices:
-            for sym in choice.syms:
-                sym._dependents.add(choice)
-
-    def _invalidate_all(self):
-        # Undefined symbols never change value and don't need to be
-        # invalidated, so we can just iterate over defined symbols.
-        # Invalidating constant symbols would break things horribly.
-        for sym in self.unique_defined_syms:
-            sym._invalidate()
-
-        for choice in self.unique_choices:
-            choice._invalidate()
-
-    #
-    # Post-parsing menu tree processing, including dependency propagation and
-    # implicit submenu creation
-    #
-
-    def _finalize_node(self, node, visible_if):
-        # Finalizes a menu node and its children:
-        #
-        #  - Copies properties from menu nodes up to their contained
-        #    symbols/choices
-        #
-        #  - Propagates dependencies from parent to child nodes
-        #
-        #  - Creates implicit menus (see kconfig-language.txt)
-        #
-        #  - Removes 'if' nodes
-        #
-        #  - Sets 'choice' types and registers choice symbols
-        #
-        # menu_finalize() in the C implementation is similar.
-        #
-        # node:
-        #   The menu node to finalize. This node and its children will have
-        #   been finalized when the function returns, and any implicit menus
-        #   will have been created.
-        #
-        # visible_if:
-        #   Dependencies from 'visible if' on parent menus. These are added to
-        #   the prompts of symbols and choices.
-
-        if node.item.__class__ is Symbol:
-            # Copy defaults, ranges, selects, and implies to the Symbol
-            self._add_props_to_sym(node)
-
-            # Find any items that should go in an implicit menu rooted at the
-            # symbol
-            cur = node
-            while cur.next and _auto_menu_dep(node, cur.next):
-                # This makes implicit submenu creation work recursively, with
-                # implicit menus inside implicit menus
-                self._finalize_node(cur.next, visible_if)
-                cur = cur.next
-                cur.parent = node
-
-            if cur is not node:
-                # Found symbols that should go in an implicit submenu. Tilt
-                # them up above us.
-                node.list = node.next
-                node.next = cur.next
-                cur.next = None
-
-        elif node.list:
-            # The menu node is a choice, menu, or if. Finalize each child node.
-
-            if node.item is MENU:
-                visible_if = self._make_and(visible_if, node.visibility)
-
-            # Propagate the menu node's dependencies to each child menu node.
-            #
-            # This needs to go before the recursive _finalize_node() call so
-            # that implicit submenu creation can look ahead at dependencies.
-            self._propagate_deps(node, visible_if)
-
-            # Finalize the children
-            cur = node.list
-            while cur:
-                self._finalize_node(cur, visible_if)
-                cur = cur.next
-
-        if node.list:
-            # node's children have been individually finalized. Do final steps
-            # to finalize this "level" in the menu tree.
-            _flatten(node.list)
-            _remove_ifs(node)
-
-        # Empty choices (node.list None) are possible, so this needs to go
-        # outside
-        if node.item.__class__ is Choice:
-            # Add the node's non-node-specific properties to the choice, like
-            # _add_props_to_sym() does
-            choice = node.item
-            choice.direct_dep = self._make_or(choice.direct_dep, node.dep)
-            choice.defaults += node.defaults
-
-            _finalize_choice(node)
-
-    def _propagate_deps(self, node, visible_if):
-        # Propagates 'node's dependencies to its child menu nodes
-
-        # If the parent node holds a Choice, we use the Choice itself as the
-        # parent dependency. This makes sense as the value (mode) of the choice
-        # limits the visibility of the contained choice symbols. The C
-        # implementation works the same way.
-        #
-        # Due to the similar interface, Choice works as a drop-in replacement
-        # for Symbol here.
-        basedep = node.item if node.item.__class__ is Choice else node.dep
-
-        cur = node.list
-        while cur:
-            dep = cur.dep = self._make_and(cur.dep, basedep)
-
-            if cur.item.__class__ in _SYMBOL_CHOICE:
-                # Propagate 'visible if' and dependencies to the prompt
-                if cur.prompt:
-                    cur.prompt = (cur.prompt[0],
-                                  self._make_and(
-                                      cur.prompt[1],
-                                      self._make_and(visible_if, dep)))
-
-                # Propagate dependencies to defaults
-                if cur.defaults:
-                    cur.defaults = [(default, self._make_and(cond, dep))
-                                    for default, cond in cur.defaults]
-
-                # Propagate dependencies to ranges
-                if cur.ranges:
-                    cur.ranges = [(low, high, self._make_and(cond, dep))
-                                  for low, high, cond in cur.ranges]
-
-                # Propagate dependencies to selects
-                if cur.selects:
-                    cur.selects = [(target, self._make_and(cond, dep))
-                                   for target, cond in cur.selects]
-
-                # Propagate dependencies to implies
-                if cur.implies:
-                    cur.implies = [(target, self._make_and(cond, dep))
-                                   for target, cond in cur.implies]
-
-            elif cur.prompt:  # Not a symbol/choice
-                # Propagate dependencies to the prompt. 'visible if' is only
-                # propagated to symbols/choices.
-                cur.prompt = (cur.prompt[0],
-                              self._make_and(cur.prompt[1], dep))
-
-            cur = cur.next
-
-    def _add_props_to_sym(self, node):
-        # Copies properties from the menu node 'node' up to its contained
-        # symbol, and adds (weak) reverse dependencies to selected/implied
-        # symbols.
-        #
-        # This can't be rolled into _propagate_deps(), because that function
-        # traverses the menu tree roughly breadth-first, meaning properties on
-        # symbols defined in multiple locations could end up in the wrong
-        # order.
-
-        sym = node.item
-
-        # See the Symbol class docstring
-        sym.direct_dep = self._make_or(sym.direct_dep, node.dep)
-
-        sym.defaults += node.defaults
-        sym.ranges += node.ranges
-        sym.selects += node.selects
-        sym.implies += node.implies
-
-        # Modify the reverse dependencies of the selected symbol
-        for target, cond in node.selects:
-            target.rev_dep = self._make_or(
-                target.rev_dep,
-                self._make_and(sym, cond))
-
-        # Modify the weak reverse dependencies of the implied
-        # symbol
-        for target, cond in node.implies:
-            target.weak_rev_dep = self._make_or(
-                target.weak_rev_dep,
-                self._make_and(sym, cond))
-
-    #
-    # Misc.
-    #
-
-    def _check_sym_sanity(self):
-        # Checks various symbol properties that are handiest to check after
-        # parsing. Only generates errors and warnings.
-
-        def num_ok(sym, type_):
-            # Returns True if the (possibly constant) symbol 'sym' is valid as a value
-            # for a symbol of type type_ (INT or HEX)
-
-            # 'not sym.nodes' implies a constant or undefined symbol, e.g. a plain
-            # "123"
-            if not sym.nodes:
-                return _is_base_n(sym.name, _TYPE_TO_BASE[type_])
-
-            return sym.orig_type is type_
-
-        for sym in self.unique_defined_syms:
-            if sym.orig_type in _BOOL_TRISTATE:
-                # A helper function could be factored out here, but keep it
-                # speedy/straightforward
-
-                for target_sym, _ in sym.selects:
-                    if target_sym.orig_type not in _BOOL_TRISTATE_UNKNOWN:
-                        self._warn("{} selects the {} symbol {}, which is not "
-                                   "bool or tristate"
-                                   .format(sym.name_and_loc,
-                                           TYPE_TO_STR[target_sym.orig_type],
-                                           target_sym.name_and_loc))
-
-                for target_sym, _ in sym.implies:
-                    if target_sym.orig_type not in _BOOL_TRISTATE_UNKNOWN:
-                        self._warn("{} implies the {} symbol {}, which is not "
-                                   "bool or tristate"
-                                   .format(sym.name_and_loc,
-                                           TYPE_TO_STR[target_sym.orig_type],
-                                           target_sym.name_and_loc))
-
-            elif sym.orig_type:  # STRING/INT/HEX
-                for default, _ in sym.defaults:
-                    if default.__class__ is not Symbol:
-                        raise KconfigError(
-                            "the {} symbol {} has a malformed default {} -- "
-                            "expected a single symbol"
-                            .format(TYPE_TO_STR[sym.orig_type],
-                                    sym.name_and_loc, expr_str(default)))
-
-                    if sym.orig_type is STRING:
-                        if not default.is_constant and not default.nodes and \
-                           not default.name.isupper():
-                            # 'default foo' on a string symbol could be either a symbol
-                            # reference or someone leaving out the quotes. Guess that
-                            # the quotes were left out if 'foo' isn't all-uppercase
-                            # (and no symbol named 'foo' exists).
-                            self._warn("style: quotes recommended around "
-                                       "default value for string symbol "
-                                       + sym.name_and_loc)
-
-                    elif not num_ok(default, sym.orig_type):  # INT/HEX
-                        self._warn("the {0} symbol {1} has a non-{0} default {2}"
-                                   .format(TYPE_TO_STR[sym.orig_type],
-                                           sym.name_and_loc,
-                                           default.name_and_loc))
-
-                if sym.selects or sym.implies:
-                    self._warn("the {} symbol {} has selects or implies"
-                               .format(TYPE_TO_STR[sym.orig_type],
-                                       sym.name_and_loc))
-
-            else:  # UNKNOWN
-                self._warn("{} defined without a type"
-                           .format(sym.name_and_loc))
-
-
-            if sym.ranges:
-                if sym.orig_type not in _INT_HEX:
-                    self._warn(
-                        "the {} symbol {} has ranges, but is not int or hex"
-                        .format(TYPE_TO_STR[sym.orig_type],
-                                sym.name_and_loc))
-                else:
-                    for low, high, _ in sym.ranges:
-                        if not num_ok(low, sym.orig_type) or \
-                           not num_ok(high, sym.orig_type):
-
-                            self._warn("the {0} symbol {1} has a non-{0} "
-                                       "range [{2}, {3}]"
-                                       .format(TYPE_TO_STR[sym.orig_type],
-                                               sym.name_and_loc,
-                                               low.name_and_loc,
-                                               high.name_and_loc))
-
-    def _check_choice_sanity(self):
-        # Checks various choice properties that are handiest to check after
-        # parsing. Only generates errors and warnings.
-
-        def warn_select_imply(sym, expr, expr_type):
-            msg = "the choice symbol {} is {} by the following symbols, but " \
-                  "select/imply has no effect on choice symbols" \
-                  .format(sym.name_and_loc, expr_type)
-
-            # si = select/imply
-            for si in split_expr(expr, OR):
-                msg += "\n - " + split_expr(si, AND)[0].name_and_loc
-
-            self._warn(msg)
-
-        for choice in self.unique_choices:
-            if choice.orig_type not in _BOOL_TRISTATE:
-                self._warn("{} defined with type {}"
-                           .format(choice.name_and_loc,
-                                   TYPE_TO_STR[choice.orig_type]))
-
-            for node in choice.nodes:
-                if node.prompt:
-                    break
-            else:
-                self._warn(choice.name_and_loc + " defined without a prompt")
-
-            for default, _ in choice.defaults:
-                if default.__class__ is not Symbol:
-                    raise KconfigError(
-                        "{} has a malformed default {}"
-                        .format(choice.name_and_loc, expr_str(default)))
-
-                if default.choice is not choice:
-                    self._warn("the default selection {} of {} is not "
-                               "contained in the choice"
-                               .format(default.name_and_loc,
-                                       choice.name_and_loc))
-
-            for sym in choice.syms:
-                if sym.defaults:
-                    self._warn("default on the choice symbol {} will have "
-                               "no effect, as defaults do not affect choice "
-                               "symbols".format(sym.name_and_loc))
-
-                if sym.rev_dep is not sym.kconfig.n:
-                    warn_select_imply(sym, sym.rev_dep, "selected")
-
-                if sym.weak_rev_dep is not sym.kconfig.n:
-                    warn_select_imply(sym, sym.weak_rev_dep, "implied")
-
-                for node in sym.nodes:
-                    if node.parent.item is choice:
-                        if not node.prompt:
-                            self._warn("the choice symbol {} has no prompt"
-                                       .format(sym.name_and_loc))
-
-                    elif node.prompt:
-                        self._warn("the choice symbol {} is defined with a "
-                                   "prompt outside the choice"
-                                   .format(sym.name_and_loc))
-
-    def _parse_error(self, msg):
-        raise KconfigError("{}error: couldn't parse '{}': {}".format(
-            "" if self.filename is None else
-                "{}:{}: ".format(self.filename, self.linenr),
-            self._line.strip(), msg))
-
-    def _trailing_tokens_error(self):
-        self._parse_error("extra tokens at end of line")
-
-    def _open(self, filename, mode):
-        # open() wrapper:
-        #
-        # - Enable universal newlines mode on Python 2 to ease
-        #   interoperability between Linux and Windows. It's already the
-        #   default on Python 3.
-        #
-        #   The "U" flag would currently work for both Python 2 and 3, but it's
-        #   deprecated on Python 3, so play it future-safe.
-        #
-        #   io.open() defaults to universal newlines on Python 2 (and is an
-        #   alias for open() on Python 3), but it returns 'unicode' strings and
-        #   slows things down:
-        #
-        #     Parsing x86 Kconfigs on Python 2
-        #
-        #     with open(..., "rU"):
-        #
-        #       real  0m0.930s
-        #       user  0m0.905s
-        #       sys   0m0.025s
-        #
-        #     with io.open():
-        #
-        #       real  0m1.069s
-        #       user  0m1.040s
-        #       sys   0m0.029s
-        #
-        #   There's no appreciable performance difference between "r" and
-        #   "rU" for parsing performance on Python 2.
-        #
-        # - For Python 3, force the encoding. Forcing the encoding on Python 2
-        #   turns strings into Unicode strings, which gets messy. Python 2
-        #   doesn't decode regular strings anyway.
-        return open(filename, "rU" if mode == "r" else mode) if _IS_PY2 else \
-               open(filename, mode, encoding=self._encoding)
-
-    def _check_undef_syms(self):
-        # Prints warnings for all references to undefined symbols within the
-        # Kconfig files
-
-        def is_num(s):
-            # Returns True if the string 's' looks like a number.
-            #
-            # Internally, all operands in Kconfig are symbols, only undefined symbols
-            # (which numbers usually are) get their name as their value.
-            #
-            # Only hex numbers that start with 0x/0X are classified as numbers.
-            # Otherwise, symbols whose names happen to contain only the letters A-F
-            # would trigger false positives.
-
-            try:
-                int(s)
-            except ValueError:
-                if not s.startswith(("0x", "0X")):
-                    return False
-
-                try:
-                    int(s, 16)
-                except ValueError:
-                    return False
-
-            return True
-
-        for sym in (self.syms.viewvalues if _IS_PY2 else self.syms.values)():
-            # - sym.nodes empty means the symbol is undefined (has no
-            #   definition locations)
-            #
-            # - Due to Kconfig internals, numbers show up as undefined Kconfig
-            #   symbols, but shouldn't be flagged
-            #
-            # - The MODULES symbol always exists
-            if not sym.nodes and not is_num(sym.name) and \
-               sym.name != "MODULES":
-
-                msg = "undefined symbol {}:".format(sym.name)
-                for node in self.node_iter():
-                    if sym in node.referenced:
-                        msg += "\n\n- Referenced at {}:{}:\n\n{}" \
-                               .format(node.filename, node.linenr, node)
-                self._warn(msg)
-
-    def _warn(self, msg, filename=None, linenr=None):
-        # For printing general warnings
-
-        if not self.warn:
-            return
-
-        msg = "warning: " + msg
-        if filename is not None:
-            msg = "{}:{}: {}".format(filename, linenr, msg)
-
-        self.warnings.append(msg)
-        if self.warn_to_stderr:
-            sys.stderr.write(msg + "\n")
-
-
-class Symbol(object):
-    """
-    Represents a configuration symbol:
-
-      (menu)config FOO
-          ...
-
-    The following attributes are available. They should be viewed as read-only,
-    and some are implemented through @property magic (but are still efficient
-    to access due to internal caching).
-
-    Note: Prompts, help texts, and locations are stored in the Symbol's
-    MenuNode(s) rather than in the Symbol itself. Check the MenuNode class and
-    the Symbol.nodes attribute. This organization matches the C tools.
-
-    name:
-      The name of the symbol, e.g. "FOO" for 'config FOO'.
-
-    type:
-      The type of the symbol. One of BOOL, TRISTATE, STRING, INT, HEX, UNKNOWN.
-      UNKNOWN is for undefined symbols, (non-special) constant symbols, and
-      symbols defined without a type.
-
-      When running without modules (MODULES having the value n), TRISTATE
-      symbols magically change type to BOOL. This also happens for symbols
-      within choices in "y" mode. This matches the C tools, and makes sense for
-      menuconfig-like functionality.
-
-    orig_type:
-      The type as given in the Kconfig file, without any magic applied. Used
-      when printing the symbol.
-
-    tri_value:
-      The tristate value of the symbol as an integer. One of 0, 1, 2,
-      representing n, m, y. Always 0 (n) for non-bool/tristate symbols.
-
-      This is the symbol value that's used outside of relation expressions
-      (A, !A, A && B, A || B).
-
-    str_value:
-      The value of the symbol as a string. Gives the value for string/int/hex
-      symbols. For bool/tristate symbols, gives "n", "m", or "y".
-
-      This is the symbol value that's used in relational expressions
-      (A = B, A != B, etc.)
-
-      Gotcha: For int/hex symbols, the exact format of the value is often
-      preserved (e.g. when writing a .config file), hence why you can't get it
-      directly as an int. Do int(int_sym.str_value) or
-      int(hex_sym.str_value, 16) to get the integer value.
-
-    user_value:
-      The user value of the symbol. None if no user value has been assigned
-      (via Kconfig.load_config() or Symbol.set_value()).
-
-      Holds 0, 1, or 2 for bool/tristate symbols, and a string for the other
-      symbol types.
-
-      WARNING: Do not assign directly to this. It will break things. Use
-      Symbol.set_value().
-
-    assignable:
-      A tuple containing the tristate user values that can currently be
-      assigned to the symbol (that would be respected), ordered from lowest (0,
-      representing n) to highest (2, representing y). This corresponds to the
-      selections available in the menuconfig interface. The set of assignable
-      values is calculated from the symbol's visibility and selects/implies.
-
-      Returns the empty set for non-bool/tristate symbols and for symbols with
-      visibility n. The other possible values are (0, 2), (0, 1, 2), (1, 2),
-      (1,), and (2,). A (1,) or (2,) result means the symbol is visible but
-      "locked" to m or y through a select, perhaps in combination with the
-      visibility. menuconfig represents this as -M- and -*-, respectively.
-
-      For string/hex/int symbols, check if Symbol.visibility is non-0 (non-n)
-      instead to determine if the value can be changed.
-
-      Some handy 'assignable' idioms:
-
-        # Is 'sym' an assignable (visible) bool/tristate symbol?
-        if sym.assignable:
-            # What's the highest value it can be assigned? [-1] in Python
-            # gives the last element.
-            sym_high = sym.assignable[-1]
-
-            # The lowest?
-            sym_low = sym.assignable[0]
-
-            # Can the symbol be set to at least m?
-            if sym.assignable[-1] >= 1:
-                ...
-
-        # Can the symbol be set to m?
-        if 1 in sym.assignable:
-            ...
-
-    visibility:
-      The visibility of the symbol. One of 0, 1, 2, representing n, m, y. See
-      the module documentation for an overview of symbol values and visibility.
-
-    config_string:
-      The .config assignment string that would get written out for the symbol
-      by Kconfig.write_config(). Returns the empty string if no .config
-      assignment would get written out.
-
-      In general, visible symbols, symbols with (active) defaults, and selected
-      symbols get written out. This includes all non-n-valued bool/tristate
-      symbols, and all visible string/int/hex symbols.
-
-      Symbols with the (no longer needed) 'option env=...' option generate no
-      configuration output, and neither does the special
-      'option defconfig_list' symbol.
-
-      Tip: This field is useful when generating custom configuration output,
-      even for non-.config-like formats. To write just the symbols that would
-      get written out to .config files, do this:
-
-        if sym.config_string:
-            *Write symbol, e.g. by looking sym.str_value*
-
-      This is a superset of the symbols written out by write_autoconf().
-      That function skips all n-valued symbols.
-
-      There usually won't be any great harm in just writing all symbols either,
-      though you might get some special symbols and possibly some "redundant"
-      n-valued symbol entries in there.
-
-    name_and_loc:
-      Holds a string like
-
-        "MY_SYMBOL (defined at foo/Kconfig:12, bar/Kconfig:14)"
-
-      , giving the name of the symbol and its definition location(s).
-
-      If the symbol is undefined, the location is given as "(undefined)".
-
-    nodes:
-      A list of MenuNodes for this symbol. Will contain a single MenuNode for
-      most symbols. Undefined and constant symbols have an empty nodes list.
-      Symbols defined in multiple locations get one node for each location.
-
-    choice:
-      Holds the parent Choice for choice symbols, and None for non-choice
-      symbols. Doubles as a flag for whether a symbol is a choice symbol.
-
-    defaults:
-      List of (default, cond) tuples for the symbol's 'default' properties. For
-      example, 'default A && B if C || D' is represented as
-      ((AND, A, B), (OR, C, D)). If no condition was given, 'cond' is
-      self.kconfig.y.
-
-      Note that 'depends on' and parent dependencies are propagated to
-      'default' conditions.
-
-    selects:
-      List of (symbol, cond) tuples for the symbol's 'select' properties. For
-      example, 'select A if B && C' is represented as (A, (AND, B, C)). If no
-      condition was given, 'cond' is self.kconfig.y.
-
-      Note that 'depends on' and parent dependencies are propagated to 'select'
-      conditions.
-
-    implies:
-      Like 'selects', for imply.
-
-    ranges:
-      List of (low, high, cond) tuples for the symbol's 'range' properties. For
-      example, 'range 1 2 if A' is represented as (1, 2, A). If there is no
-      condition, 'cond' is self.kconfig.y.
-
-      Note that 'depends on' and parent dependencies are propagated to 'range'
-      conditions.
-
-      Gotcha: 1 and 2 above will be represented as (undefined) Symbols rather
-      than plain integers. Undefined symbols get their name as their string
-      value, so this works out. The C tools work the same way.
-
-    orig_defaults:
-    orig_selects:
-    orig_implies:
-    orig_ranges:
-      See the corresponding attributes on the MenuNode class.
-
-    rev_dep:
-      Reverse dependency expression from other symbols selecting this symbol.
-      Multiple selections get ORed together. A condition on a select is ANDed
-      with the selecting symbol.
-
-      For example, if A has 'select FOO' and B has 'select FOO if C', then
-      FOO's rev_dep will be (OR, A, (AND, B, C)).
-
-    weak_rev_dep:
-      Like rev_dep, for imply.
-
-    direct_dep:
-      The direct ('depends on') dependencies for the symbol, or self.kconfig.y
-      if there are no direct dependencies.
-
-      This attribute includes any dependencies from surrounding menus and ifs.
-      Those get propagated to the direct dependencies, and the resulting direct
-      dependencies in turn get propagated to the conditions of all properties.
-
-      If the symbol is defined in multiple locations, the dependencies from the
-      different locations get ORed together.
-
-    referenced:
-      A set() with all symbols and choices referenced in the properties and
-      property conditions of the symbol.
-
-      Also includes dependencies from surrounding menus and ifs, because those
-      get propagated to the symbol (see the 'Intro to symbol values' section in
-      the module docstring).
-
-      Choices appear in the dependencies of choice symbols.
-
-      For the following definitions, only B and not C appears in A's
-      'referenced'. To get transitive references, you'll have to recursively
-      expand 'references' until no new items appear.
-
-        config A
-                bool
-                depends on B
-
-        config B
-                bool
-                depends on C
-
-        config C
-                bool
-
-      See the Symbol.direct_dep attribute if you're only interested in the
-      direct dependencies of the symbol (its 'depends on'). You can extract the
-      symbols in it with the global expr_items() function.
-
-    env_var:
-      If the Symbol has an 'option env="FOO"' option, this contains the name
-      ("FOO") of the environment variable. None for symbols without no
-      'option env'.
-
-      'option env="FOO"' acts like a 'default' property whose value is the
-      value of $FOO.
-
-      Symbols with 'option env' are never written out to .config files, even if
-      they are visible. env_var corresponds to a flag called SYMBOL_AUTO in the
-      C implementation.
-
-    is_allnoconfig_y:
-      True if the symbol has 'option allnoconfig_y' set on it. This has no
-      effect internally (except when printing symbols), but can be checked by
-      scripts.
-
-    is_constant:
-      True if the symbol is a constant (quoted) symbol.
-
-    kconfig:
-      The Kconfig instance this symbol is from.
-    """
-    __slots__ = (
-        "_cached_assignable",
-        "_cached_str_val",
-        "_cached_tri_val",
-        "_cached_vis",
-        "_dependents",
-        "_old_val",
-        "_visited",
-        "_was_set",
-        "_write_to_conf",
-        "choice",
-        "defaults",
-        "direct_dep",
-        "env_var",
-        "implies",
-        "is_allnoconfig_y",
-        "is_constant",
-        "kconfig",
-        "name",
-        "nodes",
-        "orig_type",
-        "ranges",
-        "rev_dep",
-        "selects",
-        "user_value",
-        "weak_rev_dep",
-    )
-
-    #
-    # Public interface
-    #
-
-    @property
-    def type(self):
-        """
-        See the class documentation.
-        """
-        if self.orig_type is TRISTATE and \
-           (self.choice and self.choice.tri_value == 2 or
-            not self.kconfig.modules.tri_value):
-
-            return BOOL
-
-        return self.orig_type
-
-    @property
-    def str_value(self):
-        """
-        See the class documentation.
-        """
-        if self._cached_str_val is not None:
-            return self._cached_str_val
-
-        if self.orig_type in _BOOL_TRISTATE:
-            # Also calculates the visibility, so invalidation safe
-            self._cached_str_val = TRI_TO_STR[self.tri_value]
-            return self._cached_str_val
-
-        # As a quirk of Kconfig, undefined symbols get their name as their
-        # string value. This is why things like "FOO = bar" work for seeing if
-        # FOO has the value "bar".
-        if not self.orig_type:  # UNKNOWN
-            self._cached_str_val = self.name
-            return self.name
-
-        val = ""
-        # Warning: See Symbol._rec_invalidate(), and note that this is a hidden
-        # function call (property magic)
-        vis = self.visibility
-
-        self._write_to_conf = (vis != 0)
-
-        if self.orig_type in _INT_HEX:
-            # The C implementation checks the user value against the range in a
-            # separate code path (post-processing after loading a .config).
-            # Checking all values here instead makes more sense for us. It
-            # requires that we check for a range first.
-
-            base = _TYPE_TO_BASE[self.orig_type]
-
-            # Check if a range is in effect
-            for low_expr, high_expr, cond in self.ranges:
-                if expr_value(cond):
-                    has_active_range = True
-
-                    # The zeros are from the C implementation running strtoll()
-                    # on empty strings
-                    low = int(low_expr.str_value, base) if \
-                      _is_base_n(low_expr.str_value, base) else 0
-                    high = int(high_expr.str_value, base) if \
-                      _is_base_n(high_expr.str_value, base) else 0
-
-                    break
-            else:
-                has_active_range = False
-
-            # Defaults are used if the symbol is invisible, lacks a user value,
-            # or has an out-of-range user value
-            use_defaults = True
-
-            if vis and self.user_value:
-                user_val = int(self.user_value, base)
-                if has_active_range and not low <= user_val <= high:
-                    num2str = str if base == 10 else hex
-                    self.kconfig._warn(
-                        "user value {} on the {} symbol {} ignored due to "
-                        "being outside the active range ([{}, {}]) -- falling "
-                        "back on defaults"
-                        .format(num2str(user_val), TYPE_TO_STR[self.orig_type],
-                                self.name_and_loc,
-                                num2str(low), num2str(high)))
-                else:
-                    # If the user value is well-formed and satisfies range
-                    # contraints, it is stored in exactly the same form as
-                    # specified in the assignment (with or without "0x", etc.)
-                    val = self.user_value
-                    use_defaults = False
-
-            if use_defaults:
-                # No user value or invalid user value. Look at defaults.
-
-                # Used to implement the warning below
-                has_default = False
-
-                for sym, cond in self.defaults:
-                    if expr_value(cond):
-                        has_default = self._write_to_conf = True
-
-                        val = sym.str_value
-
-                        if _is_base_n(val, base):
-                            val_num = int(val, base)
-                        else:
-                            val_num = 0  # strtoll() on empty string
-
-                        break
-                else:
-                    val_num = 0  # strtoll() on empty string
-
-                # This clamping procedure runs even if there's no default
-                if has_active_range:
-                    clamp = None
-                    if val_num < low:
-                        clamp = low
-                    elif val_num > high:
-                        clamp = high
-
-                    if clamp is not None:
-                        # The value is rewritten to a standard form if it is
-                        # clamped
-                        val = str(clamp) \
-                              if self.orig_type is INT else \
-                              hex(clamp)
-
-                        if has_default:
-                            num2str = str if base == 10 else hex
-                            self.kconfig._warn(
-                                "default value {} on {} clamped to {} due to "
-                                "being outside the active range ([{}, {}])"
-                                .format(val_num, self.name_and_loc,
-                                        num2str(clamp), num2str(low),
-                                        num2str(high)))
-
-        elif self.orig_type is STRING:
-            if vis and self.user_value is not None:
-                # If the symbol is visible and has a user value, use that
-                val = self.user_value
-            else:
-                # Otherwise, look at defaults
-                for sym, cond in self.defaults:
-                    if expr_value(cond):
-                        val = sym.str_value
-                        self._write_to_conf = True
-                        break
-
-        # env_var corresponds to SYMBOL_AUTO in the C implementation, and is
-        # also set on the defconfig_list symbol there. Test for the
-        # defconfig_list symbol explicitly instead here, to avoid a nonsensical
-        # env_var setting and the defconfig_list symbol being printed
-        # incorrectly. This code is pretty cold anyway.
-        if self.env_var is not None or self is self.kconfig.defconfig_list:
-            self._write_to_conf = False
-
-        self._cached_str_val = val
-        return val
-
-    @property
-    def tri_value(self):
-        """
-        See the class documentation.
-        """
-        if self._cached_tri_val is not None:
-            return self._cached_tri_val
-
-        if self.orig_type not in _BOOL_TRISTATE:
-            if self.orig_type:  # != UNKNOWN
-                # Would take some work to give the location here
-                self.kconfig._warn(
-                    "The {} symbol {} is being evaluated in a logical context "
-                    "somewhere. It will always evaluate to n."
-                    .format(TYPE_TO_STR[self.orig_type], self.name_and_loc))
-
-            self._cached_tri_val = 0
-            return 0
-
-        # Warning: See Symbol._rec_invalidate(), and note that this is a hidden
-        # function call (property magic)
-        vis = self.visibility
-        self._write_to_conf = (vis != 0)
-
-        val = 0
-
-        if not self.choice:
-            # Non-choice symbol
-
-            if vis and self.user_value is not None:
-                # If the symbol is visible and has a user value, use that
-                val = min(self.user_value, vis)
-
-            else:
-                # Otherwise, look at defaults and weak reverse dependencies
-                # (implies)
-
-                for default, cond in self.defaults:
-                    dep_val = expr_value(cond)
-                    if dep_val:
-                        val = min(expr_value(default), dep_val)
-                        if val:
-                            self._write_to_conf = True
-                        break
-
-                # Weak reverse dependencies are only considered if our
-                # direct dependencies are met
-                dep_val = expr_value(self.weak_rev_dep)
-                if dep_val and expr_value(self.direct_dep):
-                    val = max(dep_val, val)
-                    self._write_to_conf = True
-
-            # Reverse (select-related) dependencies take precedence
-            dep_val = expr_value(self.rev_dep)
-            if dep_val:
-                if expr_value(self.direct_dep) < dep_val:
-                    self._warn_select_unsatisfied_deps()
-
-                val = max(dep_val, val)
-                self._write_to_conf = True
-
-            # m is promoted to y for (1) bool symbols and (2) symbols with a
-            # weak_rev_dep (from imply) of y
-            if val == 1 and \
-               (self.type is BOOL or expr_value(self.weak_rev_dep) == 2):
-                val = 2
-
-        elif vis == 2:
-            # Visible choice symbol in y-mode choice. The choice mode limits
-            # the visibility of choice symbols, so it's sufficient to just
-            # check the visibility of the choice symbols themselves.
-            val = 2 if self.choice.selection is self else 0
-
-        elif vis and self.user_value:
-            # Visible choice symbol in m-mode choice, with set non-0 user value
-            val = 1
-
-        self._cached_tri_val = val
-        return val
-
-    @property
-    def assignable(self):
-        """
-        See the class documentation.
-        """
-        if self._cached_assignable is None:
-            self._cached_assignable = self._assignable()
-        return self._cached_assignable
-
-    @property
-    def visibility(self):
-        """
-        See the class documentation.
-        """
-        if self._cached_vis is None:
-            self._cached_vis = _visibility(self)
-        return self._cached_vis
-
-    @property
-    def config_string(self):
-        """
-        See the class documentation.
-        """
-        # _write_to_conf is determined when the value is calculated. This is a
-        # hidden function call due to property magic.
-        val = self.str_value
-        if not self._write_to_conf:
-            return ""
-
-        if self.orig_type in _BOOL_TRISTATE:
-            return "{}{}={}\n" \
-                   .format(self.kconfig.config_prefix, self.name, val) \
-                   if val != "n" else \
-                   "# {}{} is not set\n" \
-                   .format(self.kconfig.config_prefix, self.name)
-
-        if self.orig_type in _INT_HEX:
-            return "{}{}={}\n" \
-                   .format(self.kconfig.config_prefix, self.name, val)
-
-        # sym.orig_type is STRING
-        return '{}{}="{}"\n' \
-               .format(self.kconfig.config_prefix, self.name, escape(val))
-
-    @property
-    def name_and_loc(self):
-        """
-        See the class documentation.
-        """
-        return self.name + " " + _locs(self)
-
-    def set_value(self, value):
-        """
-        Sets the user value of the symbol.
-
-        Equal in effect to assigning the value to the symbol within a .config
-        file. For bool and tristate symbols, use the 'assignable' attribute to
-        check which values can currently be assigned. Setting values outside
-        'assignable' will cause Symbol.user_value to differ from
-        Symbol.str/tri_value (be truncated down or up).
-
-        Setting a choice symbol to 2 (y) sets Choice.user_selection to the
-        choice symbol in addition to setting Symbol.user_value.
-        Choice.user_selection is considered when the choice is in y mode (the
-        "normal" mode).
-
-        Other symbols that depend (possibly indirectly) on this symbol are
-        automatically recalculated to reflect the assigned value.
-
-        value:
-          The user value to give to the symbol. For bool and tristate symbols,
-          n/m/y can be specified either as 0/1/2 (the usual format for tristate
-          values in Kconfiglib) or as one of the strings "n", "m", or "y". For
-          other symbol types, pass a string.
-
-          Note that the value for an int/hex symbol is passed as a string, e.g.
-          "123" or "0x0123". The format of this string is preserved in the
-          output.
-
-          Values that are invalid for the type (such as "foo" or 1 (m) for a
-          BOOL or "0x123" for an INT) are ignored and won't be stored in
-          Symbol.user_value. Kconfiglib will print a warning by default for
-          invalid assignments, and set_value() will return False.
-
-        Returns True if the value is valid for the type of the symbol, and
-        False otherwise. This only looks at the form of the value. For BOOL and
-        TRISTATE symbols, check the Symbol.assignable attribute to see what
-        values are currently in range and would actually be reflected in the
-        value of the symbol. For other symbol types, check whether the
-        visibility is non-n.
-        """
-        if self.orig_type in _BOOL_TRISTATE and value in STR_TO_TRI:
-            value = STR_TO_TRI[value]
-
-        # If the new user value matches the old, nothing changes, and we can
-        # avoid invalidating cached values.
-        #
-        # This optimization is skipped for choice symbols: Setting a choice
-        # symbol's user value to y might change the state of the choice, so it
-        # wouldn't be safe (symbol user values always match the values set in a
-        # .config file or via set_value(), and are never implicitly updated).
-        if value == self.user_value and not self.choice:
-            self._was_set = True
-            return True
-
-        # Check if the value is valid for our type
-        if not (self.orig_type is BOOL     and value in (2, 0)     or
-                self.orig_type is TRISTATE and value in TRI_TO_STR or
-                value.__class__ is str and
-                (self.orig_type is STRING                        or
-                 self.orig_type is INT and _is_base_n(value, 10) or
-                 self.orig_type is HEX and _is_base_n(value, 16)
-                                       and int(value, 16) >= 0)):
-
-            # Display tristate values as n, m, y in the warning
-            self.kconfig._warn(
-                "the value {} is invalid for {}, which has type {} -- "
-                "assignment ignored"
-                .format(TRI_TO_STR[value] if value in TRI_TO_STR else
-                            "'{}'".format(value),
-                        self.name_and_loc, TYPE_TO_STR[self.orig_type]))
-
-            return False
-
-        self.user_value = value
-        self._was_set = True
-
-        if self.choice and value == 2:
-            # Setting a choice symbol to y makes it the user selection of the
-            # choice. Like for symbol user values, the user selection is not
-            # guaranteed to match the actual selection of the choice, as
-            # dependencies come into play.
-            self.choice.user_selection = self
-            self.choice._was_set = True
-            self.choice._rec_invalidate()
-        else:
-            self._rec_invalidate_if_has_prompt()
-
-        return True
-
-    def unset_value(self):
-        """
-        Removes any user value from the symbol, as if the symbol had never
-        gotten a user value via Kconfig.load_config() or Symbol.set_value().
-        """
-        if self.user_value is not None:
-            self.user_value = None
-            self._rec_invalidate_if_has_prompt()
-
-    @property
-    def referenced(self):
-        """
-        See the class documentation.
-        """
-        return {item for node in self.nodes for item in node.referenced}
-
-    @property
-    def orig_defaults(self):
-        """
-        See the class documentation.
-        """
-        return [d for node in self.nodes for d in node.orig_defaults]
-
-    @property
-    def orig_selects(self):
-        """
-        See the class documentation.
-        """
-        return [s for node in self.nodes for s in node.orig_selects]
-
-    @property
-    def orig_implies(self):
-        """
-        See the class documentation.
-        """
-        return [i for node in self.nodes for i in node.orig_implies]
-
-    @property
-    def orig_ranges(self):
-        """
-        See the class documentation.
-        """
-        return [r for node in self.nodes for r in node.orig_ranges]
-
-    def __repr__(self):
-        """
-        Returns a string with information about the symbol (including its name,
-        value, visibility, and location(s)) when it is evaluated on e.g. the
-        interactive Python prompt.
-        """
-        fields = ["symbol " + self.name, TYPE_TO_STR[self.type]]
-        add = fields.append
-
-        for node in self.nodes:
-            if node.prompt:
-                add('"{}"'.format(node.prompt[0]))
-
-        # Only add quotes for non-bool/tristate symbols
-        add("value " + (self.str_value if self.orig_type in _BOOL_TRISTATE
-                        else '"{}"'.format(self.str_value)))
-
-        if not self.is_constant:
-            # These aren't helpful to show for constant symbols
-
-            if self.user_value is not None:
-                # Only add quotes for non-bool/tristate symbols
-                add("user value " + (TRI_TO_STR[self.user_value]
-                                     if self.orig_type in _BOOL_TRISTATE
-                                     else '"{}"'.format(self.user_value)))
-
-            add("visibility " + TRI_TO_STR[self.visibility])
-
-            if self.choice:
-                add("choice symbol")
-
-            if self.is_allnoconfig_y:
-                add("allnoconfig_y")
-
-            if self is self.kconfig.defconfig_list:
-                add("is the defconfig_list symbol")
-
-            if self.env_var is not None:
-                add("from environment variable " + self.env_var)
-
-            if self is self.kconfig.modules:
-                add("is the modules symbol")
-
-            add("direct deps " + TRI_TO_STR[expr_value(self.direct_dep)])
-
-        if self.nodes:
-            for node in self.nodes:
-                add("{}:{}".format(node.filename, node.linenr))
-        else:
-            add("constant" if self.is_constant else "undefined")
-
-        return "<{}>".format(", ".join(fields))
-
-    def __str__(self):
-        """
-        Returns a string representation of the symbol when it is printed.
-        Matches the Kconfig format, with any parent dependencies propagated to
-        the 'depends on' condition.
-
-        The string is constructed by joining the strings returned by
-        MenuNode.__str__() for each of the symbol's menu nodes, so symbols
-        defined in multiple locations will return a string with all
-        definitions.
-
-        The returned string does not end in a newline. An empty string is
-        returned for undefined and constant symbols.
-        """
-        return self.custom_str(standard_sc_expr_str)
-
-    def custom_str(self, sc_expr_str_fn):
-        """
-        Works like Symbol.__str__(), but allows a custom format to be used for
-        all symbol/choice references. See expr_str().
-        """
-        return "\n\n".join(node.custom_str(sc_expr_str_fn)
-                           for node in self.nodes)
-
-    #
-    # Private methods
-    #
-
-    def __init__(self):
-        """
-        Symbol constructor -- not intended to be called directly by Kconfiglib
-        clients.
-        """
-        # These attributes are always set on the instance from outside and
-        # don't need defaults:
-        #   kconfig
-        #   direct_dep
-        #   is_constant
-        #   name
-        #   rev_dep
-        #   weak_rev_dep
-
-        # - UNKNOWN == 0
-        # - _visited is used during tree iteration and dep. loop detection
-        self.orig_type = self._visited = 0
-
-        self.nodes = []
-
-        self.defaults = []
-        self.selects = []
-        self.implies = []
-        self.ranges = []
-
-        self.user_value = \
-        self.choice = \
-        self.env_var = \
-        self._cached_str_val = self._cached_tri_val = self._cached_vis = \
-        self._cached_assignable = None
-
-        # _write_to_conf is calculated along with the value. If True, the
-        # Symbol gets a .config entry.
-
-        self.is_allnoconfig_y = \
-        self._was_set = \
-        self._write_to_conf = False
-
-        # See Kconfig._build_dep()
-        self._dependents = set()
-
-    def _assignable(self):
-        # Worker function for the 'assignable' attribute
-
-        if self.orig_type not in _BOOL_TRISTATE:
-            return ()
-
-        # Warning: See Symbol._rec_invalidate(), and note that this is a hidden
-        # function call (property magic)
-        vis = self.visibility
-        if not vis:
-            return ()
-
-        rev_dep_val = expr_value(self.rev_dep)
-
-        if vis == 2:
-            if self.choice:
-                return (2,)
-
-            if not rev_dep_val:
-                if self.type is BOOL or expr_value(self.weak_rev_dep) == 2:
-                    return (0, 2)
-                return (0, 1, 2)
-
-            if rev_dep_val == 2:
-                return (2,)
-
-            # rev_dep_val == 1
-
-            if self.type is BOOL or expr_value(self.weak_rev_dep) == 2:
-                return (2,)
-            return (1, 2)
-
-        # vis == 1
-
-        # Must be a tristate here, because bool m visibility gets promoted to y
-
-        if not rev_dep_val:
-            return (0, 1) if expr_value(self.weak_rev_dep) != 2 else (0, 2)
-
-        if rev_dep_val == 2:
-            return (2,)
-
-        # vis == rev_dep_val == 1
-
-        return (1,)
-
-    def _invalidate(self):
-        # Marks the symbol as needing to be recalculated
-
-        self._cached_str_val = self._cached_tri_val = self._cached_vis = \
-        self._cached_assignable = None
-
-    def _rec_invalidate(self):
-        # Invalidates the symbol and all items that (possibly) depend on it
-
-        if self is self.kconfig.modules:
-            # Invalidating MODULES has wide-ranging effects
-            self.kconfig._invalidate_all()
-        else:
-            self._invalidate()
-
-            for item in self._dependents:
-                # _cached_vis doubles as a flag that tells us whether 'item'
-                # has cached values, because it's calculated as a side effect
-                # of calculating all other (non-constant) cached values.
-                #
-                # If item._cached_vis is None, it means there can't be cached
-                # values on other items that depend on 'item', because if there
-                # were, some value on 'item' would have been calculated and
-                # item._cached_vis set as a side effect. It's therefore safe to
-                # stop the invalidation at symbols with _cached_vis None.
-                #
-                # This approach massively speeds up scripts that set a lot of
-                # values, vs simply invalidating all possibly dependent symbols
-                # (even when you already have a list of all the dependent
-                # symbols, because some symbols get huge dependency trees).
-                #
-                # This gracefully handles dependency loops too, which is nice
-                # for choices, where the choice depends on the choice symbols
-                # and vice versa.
-                if item._cached_vis is not None:
-                    item._rec_invalidate()
-
-    def _rec_invalidate_if_has_prompt(self):
-        # Invalidates the symbol and its dependent symbols, but only if the
-        # symbol has a prompt. User values never have an effect on promptless
-        # symbols, so we skip invalidation for them as an optimization.
-        #
-        # This also prevents constant (quoted) symbols from being invalidated
-        # if set_value() is called on them, which would make them lose their
-        # value and break things.
-        #
-        # Prints a warning if the symbol has no prompt. In some contexts (e.g.
-        # when loading a .config files) assignments to promptless symbols are
-        # normal and expected, so the warning can be disabled.
-
-        for node in self.nodes:
-            if node.prompt:
-                self._rec_invalidate()
-                return
-
-        if self.kconfig._warn_assign_no_prompt:
-            self.kconfig._warn(self.name_and_loc + " has no prompt, meaning "
-                               "user values have no effect on it")
-
-    def _str_default(self):
-        # write_min_config() helper function. Returns the value the symbol
-        # would get from defaults if it didn't have a user value. Uses exactly
-        # the same algorithm as the C implementation (though a bit cleaned up),
-        # for compatibility.
-
-        if self.orig_type in _BOOL_TRISTATE:
-            val = 0
-
-            # Defaults, selects, and implies do not affect choice symbols
-            if not self.choice:
-                for default, cond in self.defaults:
-                    cond_val = expr_value(cond)
-                    if cond_val:
-                        val = min(expr_value(default), cond_val)
-                        break
-
-                val = max(expr_value(self.rev_dep),
-                          expr_value(self.weak_rev_dep),
-                          val)
-
-                # Transpose mod to yes if type is bool (possibly due to modules
-                # being disabled)
-                if val == 1 and self.type is BOOL:
-                    val = 2
-
-            return TRI_TO_STR[val]
-
-        if self.orig_type:  # STRING/INT/HEX
-            for default, cond in self.defaults:
-                if expr_value(cond):
-                    return default.str_value
-
-        return ""
-
-    def _warn_select_unsatisfied_deps(self):
-        # Helper for printing an informative warning when a symbol with
-        # unsatisfied direct dependencies (dependencies from 'depends on', ifs,
-        # and menus) is selected by some other symbol. Also warn if a symbol
-        # whose direct dependencies evaluate to m is selected to y.
-
-        msg = "{} has direct dependencies {} with value {}, but is " \
-              "currently being {}-selected by the following symbols:" \
-              .format(self.name_and_loc, expr_str(self.direct_dep),
-                      TRI_TO_STR[expr_value(self.direct_dep)],
-                      TRI_TO_STR[expr_value(self.rev_dep)])
-
-        # The reverse dependencies from each select are ORed together
-        for select in split_expr(self.rev_dep, OR):
-            if expr_value(select) <= expr_value(self.direct_dep):
-                # Only include selects that exceed the direct dependencies
-                continue
-
-            # - 'select A if B' turns into A && B
-            # - 'select A' just turns into A
-            #
-            # In both cases, we can split on AND and pick the first operand
-            selecting_sym = split_expr(select, AND)[0]
-
-            msg += "\n - {}, with value {}, direct dependencies {} " \
-                   "(value: {})" \
-                   .format(selecting_sym.name_and_loc,
-                           selecting_sym.str_value,
-                           expr_str(selecting_sym.direct_dep),
-                           TRI_TO_STR[expr_value(selecting_sym.direct_dep)])
-
-            if select.__class__ is tuple:
-                msg += ", and select condition {} (value: {})" \
-                       .format(expr_str(select[2]),
-                               TRI_TO_STR[expr_value(select[2])])
-
-        self.kconfig._warn(msg)
-
-
-class Choice(object):
-    """
-    Represents a choice statement:
-
-      choice
-          ...
-      endchoice
-
-    The following attributes are available on Choice instances. They should be
-    treated as read-only, and some are implemented through @property magic (but
-    are still efficient to access due to internal caching).
-
-    Note: Prompts, help texts, and locations are stored in the Choice's
-    MenuNode(s) rather than in the Choice itself. Check the MenuNode class and
-    the Choice.nodes attribute. This organization matches the C tools.
-
-    name:
-      The name of the choice, e.g. "FOO" for 'choice FOO', or None if the
-      Choice has no name.
-
-    type:
-      The type of the choice. One of BOOL, TRISTATE, UNKNOWN. UNKNOWN is for
-      choices defined without a type where none of the contained symbols have a
-      type either (otherwise the choice inherits the type of the first symbol
-      defined with a type).
-
-      When running without modules (CONFIG_MODULES=n), TRISTATE choices
-      magically change type to BOOL. This matches the C tools, and makes sense
-      for menuconfig-like functionality.
-
-    orig_type:
-      The type as given in the Kconfig file, without any magic applied. Used
-      when printing the choice.
-
-    tri_value:
-      The tristate value (mode) of the choice. A choice can be in one of three
-      modes:
-
-        0 (n) - The choice is disabled and no symbols can be selected. For
-                visible choices, this mode is only possible for choices with
-                the 'optional' flag set (see kconfig-language.txt).
-
-        1 (m) - Any number of choice symbols can be set to m, the rest will
-                be n.
-
-        2 (y) - One symbol will be y, the rest n.
-
-      Only tristate choices can be in m mode. The visibility of the choice is
-      an upper bound on the mode, and the mode in turn is an upper bound on the
-      visibility of the choice symbols.
-
-      To change the mode, use Choice.set_value().
-
-      Implementation note:
-        The C tools internally represent choices as a type of symbol, with
-        special-casing in many code paths. This is why there is a lot of
-        similarity to Symbol. The value (mode) of a choice is really just a
-        normal symbol value, and an implicit reverse dependency forces its
-        lower bound to m for visible non-optional choices (the reverse
-        dependency is 'm && <visibility>').
-
-        Symbols within choices get the choice propagated as a dependency to
-        their properties. This turns the mode of the choice into an upper bound
-        on e.g. the visibility of choice symbols, and explains the gotcha
-        related to printing choice symbols mentioned in the module docstring.
-
-        Kconfiglib uses a separate Choice class only because it makes the code
-        and interface less confusing (especially in a user-facing interface).
-        Corresponding attributes have the same name in the Symbol and Choice
-        classes, for consistency and compatibility.
-
-    str_value:
-      Like choice.tri_value, but gives the value as one of the strings
-      "n", "m", or "y"
-
-    user_value:
-      The value (mode) selected by the user through Choice.set_value(). Either
-      0, 1, or 2, or None if the user hasn't selected a mode. See
-      Symbol.user_value.
-
-      WARNING: Do not assign directly to this. It will break things. Use
-      Choice.set_value() instead.
-
-    assignable:
-      See the symbol class documentation. Gives the assignable values (modes).
-
-    selection:
-      The Symbol instance of the currently selected symbol. None if the Choice
-      is not in y mode or has no selected symbol (due to unsatisfied
-      dependencies on choice symbols).
-
-      WARNING: Do not assign directly to this. It will break things. Call
-      sym.set_value(2) on the choice symbol you want to select instead.
-
-    user_selection:
-      The symbol selected by the user (by setting it to y). Ignored if the
-      choice is not in y mode, but still remembered so that the choice "snaps
-      back" to the user selection if the mode is changed back to y. This might
-      differ from 'selection' due to unsatisfied dependencies.
-
-      WARNING: Do not assign directly to this. It will break things. Call
-      sym.set_value(2) on the choice symbol to be selected instead.
-
-    visibility:
-      See the Symbol class documentation. Acts on the value (mode).
-
-    name_and_loc:
-      Holds a string like
-
-        "<choice MY_CHOICE> (defined at foo/Kconfig:12)"
-
-      , giving the name of the choice and its definition location(s). If the
-      choice has no name (isn't defined with 'choice MY_CHOICE'), then it will
-      be shown as "<choice>" before the list of locations (always a single one
-      in that case).
-
-    syms:
-      List of symbols contained in the choice.
-
-      Obscure gotcha: If a symbol depends on the previous symbol within a
-      choice so that an implicit menu is created, it won't be a choice symbol,
-      and won't be included in 'syms'.
-
-    nodes:
-      A list of MenuNodes for this choice. In practice, the list will probably
-      always contain a single MenuNode, but it is possible to give a choice a
-      name and define it in multiple locations.
-
-    defaults:
-      List of (symbol, cond) tuples for the choice's 'defaults' properties. For
-      example, 'default A if B && C' is represented as (A, (AND, B, C)). If
-      there is no condition, 'cond' is self.kconfig.y.
-
-      Note that 'depends on' and parent dependencies are propagated to
-      'default' conditions.
-
-    orig_defaults:
-      See the corresponding attribute on the MenuNode class.
-
-    direct_dep:
-      See Symbol.direct_dep.
-
-    referenced:
-      A set() with all symbols referenced in the properties and property
-      conditions of the choice.
-
-      Also includes dependencies from surrounding menus and ifs, because those
-      get propagated to the choice (see the 'Intro to symbol values' section in
-      the module docstring).
-
-    is_optional:
-      True if the choice has the 'optional' flag set on it and can be in
-      n mode.
-
-    kconfig:
-      The Kconfig instance this choice is from.
-    """
-    __slots__ = (
-        "_cached_assignable",
-        "_cached_selection",
-        "_cached_vis",
-        "_dependents",
-        "_visited",
-        "_was_set",
-        "defaults",
-        "direct_dep",
-        "is_constant",
-        "is_optional",
-        "kconfig",
-        "name",
-        "nodes",
-        "orig_type",
-        "syms",
-        "user_selection",
-        "user_value",
-    )
-
-    #
-    # Public interface
-    #
-
-    @property
-    def type(self):
-        """
-        Returns the type of the choice. See Symbol.type.
-        """
-        if self.orig_type is TRISTATE and not self.kconfig.modules.tri_value:
-            return BOOL
-        return self.orig_type
-
-    @property
-    def str_value(self):
-        """
-        See the class documentation.
-        """
-        return TRI_TO_STR[self.tri_value]
-
-    @property
-    def tri_value(self):
-        """
-        See the class documentation.
-        """
-        # This emulates a reverse dependency of 'm && visibility' for
-        # non-optional choices, which is how the C implementation does it
-
-        val = 0 if self.is_optional else 1
-
-        if self.user_value is not None:
-            val = max(val, self.user_value)
-
-        # Warning: See Symbol._rec_invalidate(), and note that this is a hidden
-        # function call (property magic)
-        val = min(val, self.visibility)
-
-        # Promote m to y for boolean choices
-        return 2 if val == 1 and self.type is BOOL else val
-
-    @property
-    def assignable(self):
-        """
-        See the class documentation.
-        """
-        if self._cached_assignable is None:
-            self._cached_assignable = self._assignable()
-        return self._cached_assignable
-
-    @property
-    def visibility(self):
-        """
-        See the class documentation.
-        """
-        if self._cached_vis is None:
-            self._cached_vis = _visibility(self)
-        return self._cached_vis
-
-    @property
-    def name_and_loc(self):
-        """
-        See the class documentation.
-        """
-        # Reuse the expression format, which is '<choice (name, if any)>'.
-        return standard_sc_expr_str(self) + " " + _locs(self)
-
-    @property
-    def selection(self):
-        """
-        See the class documentation.
-        """
-        if self._cached_selection is _NO_CACHED_SELECTION:
-            self._cached_selection = self._selection()
-        return self._cached_selection
-
-    def set_value(self, value):
-        """
-        Sets the user value (mode) of the choice. Like for Symbol.set_value(),
-        the visibility might truncate the value. Choices without the 'optional'
-        attribute (is_optional) can never be in n mode, but 0/"n" is still
-        accepted since it's not a malformed value (though it will have no
-        effect).
-
-        Returns True if the value is valid for the type of the choice, and
-        False otherwise. This only looks at the form of the value. Check the
-        Choice.assignable attribute to see what values are currently in range
-        and would actually be reflected in the mode of the choice.
-        """
-        if value in STR_TO_TRI:
-            value = STR_TO_TRI[value]
-
-        if value == self.user_value:
-            # We know the value must be valid if it was successfully set
-            # previously
-            self._was_set = True
-            return True
-
-        if not (self.orig_type is BOOL     and value in (2, 0) or
-                self.orig_type is TRISTATE and value in TRI_TO_STR):
-
-            # Display tristate values as n, m, y in the warning
-            self.kconfig._warn(
-                "the value {} is invalid for {}, which has type {} -- "
-                "assignment ignored"
-                .format(TRI_TO_STR[value] if value in TRI_TO_STR else
-                            "'{}'".format(value),
-                        self.name_and_loc, TYPE_TO_STR[self.orig_type]))
-
-            return False
-
-        self.user_value = value
-        self._was_set = True
-        self._rec_invalidate()
-
-        return True
-
-    def unset_value(self):
-        """
-        Resets the user value (mode) and user selection of the Choice, as if
-        the user had never touched the mode or any of the choice symbols.
-        """
-        if self.user_value is not None or self.user_selection:
-            self.user_value = self.user_selection = None
-            self._rec_invalidate()
-
-    @property
-    def referenced(self):
-        """
-        See the class documentation.
-        """
-        return {item for node in self.nodes for item in node.referenced}
-
-    @property
-    def orig_defaults(self):
-        """
-        See the class documentation.
-        """
-        return [d for node in self.nodes for d in node.orig_defaults]
-
-    def __repr__(self):
-        """
-        Returns a string with information about the choice when it is evaluated
-        on e.g. the interactive Python prompt.
-        """
-        fields = ["choice " + self.name if self.name else "choice",
-                  TYPE_TO_STR[self.type]]
-        add = fields.append
-
-        for node in self.nodes:
-            if node.prompt:
-                add('"{}"'.format(node.prompt[0]))
-
-        add("mode " + self.str_value)
-
-        if self.user_value is not None:
-            add('user mode {}'.format(TRI_TO_STR[self.user_value]))
-
-        if self.selection:
-            add("{} selected".format(self.selection.name))
-
-        if self.user_selection:
-            user_sel_str = "{} selected by user" \
-                           .format(self.user_selection.name)
-
-            if self.selection is not self.user_selection:
-                user_sel_str += " (overridden)"
-
-            add(user_sel_str)
-
-        add("visibility " + TRI_TO_STR[self.visibility])
-
-        if self.is_optional:
-            add("optional")
-
-        for node in self.nodes:
-            add("{}:{}".format(node.filename, node.linenr))
-
-        return "<{}>".format(", ".join(fields))
-
-    def __str__(self):
-        """
-        Returns a string representation of the choice when it is printed.
-        Matches the Kconfig format (though without the contained choice
-        symbols), with any parent dependencies propagated to the 'depends on'
-        condition.
-
-        The returned string does not end in a newline.
-
-        See Symbol.__str__() as well.
-        """
-        return self.custom_str(standard_sc_expr_str)
-
-    def custom_str(self, sc_expr_str_fn):
-        """
-        Works like Choice.__str__(), but allows a custom format to be used for
-        all symbol/choice references. See expr_str().
-        """
-        return "\n\n".join(node.custom_str(sc_expr_str_fn)
-                           for node in self.nodes)
-
-    #
-    # Private methods
-    #
-
-    def __init__(self):
-        """
-        Choice constructor -- not intended to be called directly by Kconfiglib
-        clients.
-        """
-        # These attributes are always set on the instance from outside and
-        # don't need defaults:
-        #   direct_dep
-        #   kconfig
-
-        # - UNKNOWN == 0
-        # - _visited is used during dep. loop detection
-        self.orig_type = self._visited = 0
-
-        self.nodes = []
-
-        self.syms = []
-        self.defaults = []
-
-        self.name = \
-        self.user_value = self.user_selection = \
-        self._cached_vis = self._cached_assignable = None
-
-        self._cached_selection = _NO_CACHED_SELECTION
-
-        # is_constant is checked by _depend_on(). Just set it to avoid having
-        # to special-case choices.
-        self.is_constant = self.is_optional = False
-
-        # See Kconfig._build_dep()
-        self._dependents = set()
-
-    def _assignable(self):
-        # Worker function for the 'assignable' attribute
-
-        # Warning: See Symbol._rec_invalidate(), and note that this is a hidden
-        # function call (property magic)
-        vis = self.visibility
-
-        if not vis:
-            return ()
-
-        if vis == 2:
-            if not self.is_optional:
-                return (2,) if self.type is BOOL else (1, 2)
-            return (0, 2) if self.type is BOOL else (0, 1, 2)
-
-        # vis == 1
-
-        return (0, 1) if self.is_optional else (1,)
-
-    def _selection(self):
-        # Worker function for the 'selection' attribute
-
-        # Warning: See Symbol._rec_invalidate(), and note that this is a hidden
-        # function call (property magic)
-        if self.tri_value != 2:
-            # Not in y mode, so no selection
-            return None
-
-        # Use the user selection if it's visible
-        if self.user_selection and self.user_selection.visibility:
-            return self.user_selection
-
-        # Otherwise, check if we have a default
-        return self._selection_from_defaults()
-
-    def _selection_from_defaults(self):
-        # Check if we have a default
-        for sym, cond in self.defaults:
-            # The default symbol must be visible too
-            if expr_value(cond) and sym.visibility:
-                return sym
-
-        # Otherwise, pick the first visible symbol, if any
-        for sym in self.syms:
-            if sym.visibility:
-                return sym
-
-        # Couldn't find a selection
-        return None
-
-    def _invalidate(self):
-        self._cached_vis = self._cached_assignable = None
-        self._cached_selection = _NO_CACHED_SELECTION
-
-    def _rec_invalidate(self):
-        # See Symbol._rec_invalidate()
-
-        self._invalidate()
-
-        for item in self._dependents:
-            if item._cached_vis is not None:
-                item._rec_invalidate()
-
-
-class MenuNode(object):
-    """
-    Represents a menu node in the configuration. This corresponds to an entry
-    in e.g. the 'make menuconfig' interface, though non-visible choices, menus,
-    and comments also get menu nodes. If a symbol or choice is defined in
-    multiple locations, it gets one menu node for each location.
-
-    The top-level menu node, corresponding to the implicit top-level menu, is
-    available in Kconfig.top_node.
-
-    The menu nodes for a Symbol or Choice can be found in the
-    Symbol/Choice.nodes attribute. Menus and comments are represented as plain
-    menu nodes, with their text stored in the prompt attribute (prompt[0]).
-    This mirrors the C implementation.
-
-    The following attributes are available on MenuNode instances. They should
-    be viewed as read-only.
-
-    item:
-      Either a Symbol, a Choice, or one of the constants MENU and COMMENT.
-      Menus and comments are represented as plain menu nodes. Ifs are collapsed
-      (matching the C implementation) and do not appear in the final menu tree.
-
-    next:
-      The following menu node. None if there is no following node.
-
-    list:
-      The first child menu node. None if there are no children.
-
-      Choices and menus naturally have children, but Symbols can also have
-      children because of menus created automatically from dependencies (see
-      kconfig-language.txt).
-
-    parent:
-      The parent menu node. None if there is no parent.
-
-    prompt:
-      A (string, cond) tuple with the prompt for the menu node and its
-      conditional expression (which is self.kconfig.y if there is no
-      condition). None if there is no prompt.
-
-      For symbols and choices, the prompt is stored in the MenuNode rather than
-      the Symbol or Choice instance. For menus and comments, the prompt holds
-      the text.
-
-    defaults:
-      The 'default' properties for this particular menu node. See
-      symbol.defaults.
-
-      When evaluating defaults, you should use Symbol/Choice.defaults instead,
-      as it include properties from all menu nodes (a symbol/choice can have
-      multiple definition locations/menu nodes). MenuNode.defaults is meant for
-      documentation generation.
-
-    selects:
-      Like MenuNode.defaults, for selects.
-
-    implies:
-      Like MenuNode.defaults, for implies.
-
-    ranges:
-      Like MenuNode.defaults, for ranges.
-
-    orig_prompt:
-    orig_defaults:
-    orig_selects:
-    orig_implies:
-    orig_ranges:
-      These work the like the corresponding attributes without orig_*, but omit
-      any dependencies propagated from 'depends on' and surrounding 'if's (the
-      direct dependencies, stored in MenuNode.dep).
-
-      One use for this is generating less cluttered documentation, by only
-      showing the direct dependencies in one place.
-
-    help:
-      The help text for the menu node for Symbols and Choices. None if there is
-      no help text. Always stored in the node rather than the Symbol or Choice.
-      It is possible to have a separate help text at each location if a symbol
-      is defined in multiple locations.
-
-      Trailing whitespace (including a final newline) is stripped from the help
-      text. This was not the case before Kconfiglib 10.21.0, where the format
-      was undocumented.
-
-    dep:
-      The direct ('depends on') dependencies for the menu node, or
-      self.kconfig.y if there are no direct dependencies.
-
-      This attribute includes any dependencies from surrounding menus and ifs.
-      Those get propagated to the direct dependencies, and the resulting direct
-      dependencies in turn get propagated to the conditions of all properties.
-
-      If a symbol or choice is defined in multiple locations, only the
-      properties defined at a particular location get the corresponding
-      MenuNode.dep dependencies propagated to them.
-
-    visibility:
-      The 'visible if' dependencies for the menu node (which must represent a
-      menu), or self.kconfig.y if there are no 'visible if' dependencies.
-      'visible if' dependencies are recursively propagated to the prompts of
-      symbols and choices within the menu.
-
-    referenced:
-      A set() with all symbols and choices referenced in the properties and
-      property conditions of the menu node.
-
-      Also includes dependencies inherited from surrounding menus and ifs.
-      Choices appear in the dependencies of choice symbols.
-
-    is_menuconfig:
-      Set to True if the children of the menu node should be displayed in a
-      separate menu. This is the case for the following items:
-
-        - Menus (node.item == MENU)
-
-        - Choices
-
-        - Symbols defined with the 'menuconfig' keyword. The children come from
-          implicitly created submenus, and should be displayed in a separate
-          menu rather than being indented.
-
-      'is_menuconfig' is just a hint on how to display the menu node. It's
-      ignored internally by Kconfiglib, except when printing symbols.
-
-    filename/linenr:
-      The location where the menu node appears. The filename is relative to
-      $srctree (or to the current directory if $srctree isn't set), except
-      absolute paths are used for paths outside $srctree.
-
-    include_path:
-      A tuple of (filename, linenr) tuples, giving the locations of the
-      'source' statements via which the Kconfig file containing this menu node
-      was included. The first element is the location of the 'source' statement
-      in the top-level Kconfig file passed to Kconfig.__init__(), etc.
-
-      Note that the Kconfig file of the menu node itself isn't included. Check
-      'filename' and 'linenr' for that.
-
-    kconfig:
-      The Kconfig instance the menu node is from.
-    """
-    __slots__ = (
-        "dep",
-        "filename",
-        "help",
-        "include_path",
-        "is_menuconfig",
-        "item",
-        "kconfig",
-        "linenr",
-        "list",
-        "next",
-        "parent",
-        "prompt",
-        "visibility",
-
-        # Properties
-        "defaults",
-        "selects",
-        "implies",
-        "ranges",
-    )
-
-    def __init__(self):
-        # Properties defined on this particular menu node. A local 'depends on'
-        # only applies to these, in case a symbol is defined in multiple
-        # locations.
-        self.defaults = []
-        self.selects = []
-        self.implies = []
-        self.ranges = []
-
-    @property
-    def orig_prompt(self):
-        """
-        See the class documentation.
-        """
-        if not self.prompt:
-            return None
-        return (self.prompt[0], self._strip_dep(self.prompt[1]))
-
-    @property
-    def orig_defaults(self):
-        """
-        See the class documentation.
-        """
-        return [(default, self._strip_dep(cond))
-                for default, cond in self.defaults]
-
-    @property
-    def orig_selects(self):
-        """
-        See the class documentation.
-        """
-        return [(select, self._strip_dep(cond))
-                for select, cond in self.selects]
-
-    @property
-    def orig_implies(self):
-        """
-        See the class documentation.
-        """
-        return [(imply, self._strip_dep(cond))
-                for imply, cond in self.implies]
-
-    @property
-    def orig_ranges(self):
-        """
-        See the class documentation.
-        """
-        return [(low, high, self._strip_dep(cond))
-                for low, high, cond in self.ranges]
-
-    @property
-    def referenced(self):
-        """
-        See the class documentation.
-        """
-        # self.dep is included to catch dependencies from a lone 'depends on'
-        # when there are no properties to propagate it to
-        res = expr_items(self.dep)
-
-        if self.prompt:
-            res |= expr_items(self.prompt[1])
-
-        if self.item is MENU:
-            res |= expr_items(self.visibility)
-
-        for value, cond in self.defaults:
-            res |= expr_items(value)
-            res |= expr_items(cond)
-
-        for value, cond in self.selects:
-            res.add(value)
-            res |= expr_items(cond)
-
-        for value, cond in self.implies:
-            res.add(value)
-            res |= expr_items(cond)
-
-        for low, high, cond in self.ranges:
-            res.add(low)
-            res.add(high)
-            res |= expr_items(cond)
-
-        return res
-
-    def __repr__(self):
-        """
-        Returns a string with information about the menu node when it is
-        evaluated on e.g. the interactive Python prompt.
-        """
-        fields = []
-        add = fields.append
-
-        if self.item.__class__ is Symbol:
-            add("menu node for symbol " + self.item.name)
-
-        elif self.item.__class__ is Choice:
-            s = "menu node for choice"
-            if self.item.name is not None:
-                s += " " + self.item.name
-            add(s)
-
-        elif self.item is MENU:
-            add("menu node for menu")
-
-        else:  # self.item is COMMENT
-            add("menu node for comment")
-
-        if self.prompt:
-            add('prompt "{}" (visibility {})'.format(
-                self.prompt[0], TRI_TO_STR[expr_value(self.prompt[1])]))
-
-        if self.item.__class__ is Symbol and self.is_menuconfig:
-            add("is menuconfig")
-
-        add("deps " + TRI_TO_STR[expr_value(self.dep)])
-
-        if self.item is MENU:
-            add("'visible if' deps " + TRI_TO_STR[expr_value(self.visibility)])
-
-        if self.item.__class__ in _SYMBOL_CHOICE and self.help is not None:
-            add("has help")
-
-        if self.list:
-            add("has child")
-
-        if self.next:
-            add("has next")
-
-        add("{}:{}".format(self.filename, self.linenr))
-
-        return "<{}>".format(", ".join(fields))
-
-    def __str__(self):
-        """
-        Returns a string representation of the menu node. Matches the Kconfig
-        format, with any parent dependencies propagated to the 'depends on'
-        condition.
-
-        The output could (almost) be fed back into a Kconfig parser to redefine
-        the object associated with the menu node. See the module documentation
-        for a gotcha related to choice symbols.
-
-        For symbols and choices with multiple menu nodes (multiple definition
-        locations), properties that aren't associated with a particular menu
-        node are shown on all menu nodes ('option env=...', 'optional' for
-        choices, etc.).
-
-        The returned string does not end in a newline.
-        """
-        return self.custom_str(standard_sc_expr_str)
-
-    def custom_str(self, sc_expr_str_fn):
-        """
-        Works like MenuNode.__str__(), but allows a custom format to be used
-        for all symbol/choice references. See expr_str().
-        """
-        return self._menu_comment_node_str(sc_expr_str_fn) \
-               if self.item in _MENU_COMMENT else \
-               self._sym_choice_node_str(sc_expr_str_fn)
-
-    def _menu_comment_node_str(self, sc_expr_str_fn):
-        s = '{} "{}"'.format("menu" if self.item is MENU else "comment",
-                             self.prompt[0])
-
-        if self.dep is not self.kconfig.y:
-            s += "\n\tdepends on {}".format(expr_str(self.dep, sc_expr_str_fn))
-
-        if self.item is MENU and self.visibility is not self.kconfig.y:
-            s += "\n\tvisible if {}".format(expr_str(self.visibility,
-                                                     sc_expr_str_fn))
-
-        return s
-
-    def _sym_choice_node_str(self, sc_expr_str_fn):
-        def indent_add(s):
-            lines.append("\t" + s)
-
-        def indent_add_cond(s, cond):
-            if cond is not self.kconfig.y:
-                s += " if " + expr_str(cond, sc_expr_str_fn)
-            indent_add(s)
-
-        sc = self.item
-
-        if sc.__class__ is Symbol:
-            lines = [("menuconfig " if self.is_menuconfig else "config ")
-                     + sc.name]
-        else:
-            lines = ["choice " + sc.name if sc.name else "choice"]
-
-        if sc.orig_type and not self.prompt:  # sc.orig_type != UNKNOWN
-            # If there's a prompt, we'll use the '<type> "prompt"' shorthand
-            # instead
-            indent_add(TYPE_TO_STR[sc.orig_type])
-
-        if self.prompt:
-            if sc.orig_type:
-                prefix = TYPE_TO_STR[sc.orig_type]
-            else:
-                # Symbol defined without a type (which generates a warning)
-                prefix = "prompt"
-
-            indent_add_cond(prefix + ' "{}"'.format(escape(self.prompt[0])),
-                            self.orig_prompt[1])
-
-        if sc.__class__ is Symbol:
-            if sc.is_allnoconfig_y:
-                indent_add("option allnoconfig_y")
-
-            if sc is sc.kconfig.defconfig_list:
-                indent_add("option defconfig_list")
-
-            if sc.env_var is not None:
-                indent_add('option env="{}"'.format(sc.env_var))
-
-            if sc is sc.kconfig.modules:
-                indent_add("option modules")
-
-            for low, high, cond in self.orig_ranges:
-                indent_add_cond(
-                    "range {} {}".format(sc_expr_str_fn(low),
-                                         sc_expr_str_fn(high)),
-                    cond)
-
-        for default, cond in self.orig_defaults:
-            indent_add_cond("default " + expr_str(default, sc_expr_str_fn),
-                            cond)
-
-        if sc.__class__ is Choice and sc.is_optional:
-            indent_add("optional")
-
-        if sc.__class__ is Symbol:
-            for select, cond in self.orig_selects:
-                indent_add_cond("select " + sc_expr_str_fn(select), cond)
-
-            for imply, cond in self.orig_implies:
-                indent_add_cond("imply " + sc_expr_str_fn(imply), cond)
-
-        if self.dep is not sc.kconfig.y:
-            indent_add("depends on " + expr_str(self.dep, sc_expr_str_fn))
-
-        if self.help is not None:
-            indent_add("help")
-            for line in self.help.splitlines():
-                indent_add("  " + line)
-
-        return "\n".join(lines)
-
-    def _strip_dep(self, expr):
-        # Helper function for removing MenuNode.dep from 'expr'. Uses two
-        # pieces of internal knowledge: (1) Expressions are reused rather than
-        # copied, and (2) the direct dependencies always appear at the end.
-
-        # ... if dep -> ... if y
-        if self.dep is expr:
-            return self.kconfig.y
-
-        # (AND, X, dep) -> X
-        if expr.__class__ is tuple and expr[0] is AND and expr[2] is self.dep:
-            return expr[1]
-
-        return expr
-
-
-class Variable(object):
-    """
-    Represents a preprocessor variable/function.
-
-    The following attributes are available:
-
-    name:
-      The name of the variable.
-
-    value:
-      The unexpanded value of the variable.
-
-    expanded_value:
-      The expanded value of the variable. For simple variables (those defined
-      with :=), this will equal 'value'. Accessing this property will raise a
-      KconfigError if the expansion seems to be stuck in a loop.
-
-      Accessing this field is the same as calling expanded_value_w_args() with
-      no arguments. I hadn't considered function arguments when adding it. It
-      is retained for backwards compatibility though.
-
-    is_recursive:
-      True if the variable is recursive (defined with =).
-    """
-    __slots__ = (
-        "_n_expansions",
-        "is_recursive",
-        "kconfig",
-        "name",
-        "value",
-    )
-
-    @property
-    def expanded_value(self):
-        """
-        See the class documentation.
-        """
-        return self.expanded_value_w_args()
-
-    def expanded_value_w_args(self, *args):
-        """
-        Returns the expanded value of the variable/function. Any arguments
-        passed will be substituted for $(1), $(2), etc.
-
-        Raises a KconfigError if the expansion seems to be stuck in a loop.
-        """
-        return self.kconfig._fn_val((self.name,) + args)
-
-    def __repr__(self):
-        return "<variable {}, {}, value '{}'>" \
-               .format(self.name,
-                       "recursive" if self.is_recursive else "immediate",
-                       self.value)
-
-
-class KconfigError(Exception):
-    """
-    Exception raised for Kconfig-related errors.
-
-    KconfigError and KconfigSyntaxError are the same class. The
-    KconfigSyntaxError alias is only maintained for backwards compatibility.
-    """
-
-KconfigSyntaxError = KconfigError  # Backwards compatibility
-
-
-class InternalError(Exception):
-    "Never raised. Kept around for backwards compatibility."
-
-
-# Workaround:
-#
-# If 'errno' and 'strerror' are set on IOError, then __str__() always returns
-# "[Errno <errno>] <strerror>", ignoring any custom message passed to the
-# constructor. By defining our own subclass, we can use a custom message while
-# also providing 'errno', 'strerror', and 'filename' to scripts.
-class _KconfigIOError(IOError):
-    def __init__(self, ioerror, msg):
-        self.msg = msg
-        super(_KconfigIOError, self).__init__(
-            ioerror.errno, ioerror.strerror, ioerror.filename)
-
-    def __str__(self):
-        return self.msg
-
-
-#
-# Public functions
-#
-
-
-def expr_value(expr):
-    """
-    Evaluates the expression 'expr' to a tristate value. Returns 0 (n), 1 (m),
-    or 2 (y).
-
-    'expr' must be an already-parsed expression from a Symbol, Choice, or
-    MenuNode property. To evaluate an expression represented as a string, use
-    Kconfig.eval_string().
-
-    Passing subexpressions of expressions to this function works as expected.
-    """
-    if expr.__class__ is not tuple:
-        return expr.tri_value
-
-    if expr[0] is AND:
-        v1 = expr_value(expr[1])
-        # Short-circuit the n case as an optimization (~5% faster
-        # allnoconfig.py and allyesconfig.py, as of writing)
-        return 0 if not v1 else min(v1, expr_value(expr[2]))
-
-    if expr[0] is OR:
-        v1 = expr_value(expr[1])
-        # Short-circuit the y case as an optimization
-        return 2 if v1 == 2 else max(v1, expr_value(expr[2]))
-
-    if expr[0] is NOT:
-        return 2 - expr_value(expr[1])
-
-    # Relation
-    #
-    # Implements <, <=, >, >= comparisons as well. These were added to
-    # kconfig in 31847b67 (kconfig: allow use of relations other than
-    # (in)equality).
-
-    rel, v1, v2 = expr
-
-    # If both operands are strings...
-    if v1.orig_type is STRING and v2.orig_type is STRING:
-        # ...then compare them lexicographically
-        comp = _strcmp(v1.str_value, v2.str_value)
-    else:
-        # Otherwise, try to compare them as numbers
-        try:
-            comp = _sym_to_num(v1) - _sym_to_num(v2)
-        except ValueError:
-            # Fall back on a lexicographic comparison if the operands don't
-            # parse as numbers
-            comp = _strcmp(v1.str_value, v2.str_value)
-
-    return 2*(comp == 0 if rel is EQUAL else
-              comp != 0 if rel is UNEQUAL else
-              comp <  0 if rel is LESS else
-              comp <= 0 if rel is LESS_EQUAL else
-              comp >  0 if rel is GREATER else
-              comp >= 0)
-
-
-def standard_sc_expr_str(sc):
-    """
-    Standard symbol/choice printing function. Uses plain Kconfig syntax, and
-    displays choices as <choice> (or <choice NAME>, for named choices).
-
-    See expr_str().
-    """
-    if sc.__class__ is Symbol:
-        if sc.is_constant and sc.name not in STR_TO_TRI:
-            return '"{}"'.format(escape(sc.name))
-        return sc.name
-
-    return "<choice {}>".format(sc.name) if sc.name else "<choice>"
-
-
-def expr_str(expr, sc_expr_str_fn=standard_sc_expr_str):
-    """
-    Returns the string representation of the expression 'expr', as in a Kconfig
-    file.
-
-    Passing subexpressions of expressions to this function works as expected.
-
-    sc_expr_str_fn (default: standard_sc_expr_str):
-      This function is called for every symbol/choice (hence "sc") appearing in
-      the expression, with the symbol/choice as the argument. It is expected to
-      return a string to be used for the symbol/choice.
-
-      This can be used e.g. to turn symbols/choices into links when generating
-      documentation, or for printing the value of each symbol/choice after it.
-
-      Note that quoted values are represented as constants symbols
-      (Symbol.is_constant == True).
-    """
-    if expr.__class__ is not tuple:
-        return sc_expr_str_fn(expr)
-
-    if expr[0] is AND:
-        return "{} && {}".format(_parenthesize(expr[1], OR, sc_expr_str_fn),
-                                 _parenthesize(expr[2], OR, sc_expr_str_fn))
-
-    if expr[0] is OR:
-        # This turns A && B || C && D into "(A && B) || (C && D)", which is
-        # redundant, but more readable
-        return "{} || {}".format(_parenthesize(expr[1], AND, sc_expr_str_fn),
-                                 _parenthesize(expr[2], AND, sc_expr_str_fn))
-
-    if expr[0] is NOT:
-        if expr[1].__class__ is tuple:
-            return "!({})".format(expr_str(expr[1], sc_expr_str_fn))
-        return "!" + sc_expr_str_fn(expr[1])  # Symbol
-
-    # Relation
-    #
-    # Relation operands are always symbols (quoted strings are constant
-    # symbols)
-    return "{} {} {}".format(sc_expr_str_fn(expr[1]), REL_TO_STR[expr[0]],
-                             sc_expr_str_fn(expr[2]))
-
-
-def expr_items(expr):
-    """
-    Returns a set() of all items (symbols and choices) that appear in the
-    expression 'expr'.
-
-    Passing subexpressions of expressions to this function works as expected.
-    """
-    res = set()
-
-    def rec(subexpr):
-        if subexpr.__class__ is tuple:
-            # AND, OR, NOT, or relation
-
-            rec(subexpr[1])
-
-            # NOTs only have a single operand
-            if subexpr[0] is not NOT:
-                rec(subexpr[2])
-
-        else:
-            # Symbol or choice
-            res.add(subexpr)
-
-    rec(expr)
-    return res
-
-
-def split_expr(expr, op):
-    """
-    Returns a list containing the top-level AND or OR operands in the
-    expression 'expr', in the same (left-to-right) order as they appear in
-    the expression.
-
-    This can be handy e.g. for splitting (weak) reverse dependencies
-    from 'select' and 'imply' into individual selects/implies.
-
-    op:
-      Either AND to get AND operands, or OR to get OR operands.
-
-      (Having this as an operand might be more future-safe than having two
-      hardcoded functions.)
-
-
-    Pseudo-code examples:
-
-      split_expr( A                    , OR  )  ->  [A]
-      split_expr( A && B               , OR  )  ->  [A && B]
-      split_expr( A || B               , OR  )  ->  [A, B]
-      split_expr( A || B               , AND )  ->  [A || B]
-      split_expr( A || B || (C && D)   , OR  )  ->  [A, B, C && D]
-
-      # Second || is not at the top level
-      split_expr( A || (B && (C || D)) , OR )  ->  [A, B && (C || D)]
-
-      # Parentheses don't matter as long as we stay at the top level (don't
-      # encounter any non-'op' nodes)
-      split_expr( (A || B) || C        , OR )  ->  [A, B, C]
-      split_expr( A || (B || C)        , OR )  ->  [A, B, C]
-    """
-    res = []
-
-    def rec(subexpr):
-        if subexpr.__class__ is tuple and subexpr[0] is op:
-            rec(subexpr[1])
-            rec(subexpr[2])
-        else:
-            res.append(subexpr)
-
-    rec(expr)
-    return res
-
-
-def escape(s):
-    r"""
-    Escapes the string 's' in the same fashion as is done for display in
-    Kconfig format and when writing strings to a .config file. " and \ are
-    replaced by \" and \\, respectively.
-    """
-    # \ must be escaped before " to avoid double escaping
-    return s.replace("\\", r"\\").replace('"', r'\"')
-
-
-def unescape(s):
-    r"""
-    Unescapes the string 's'. \ followed by any character is replaced with just
-    that character. Used internally when reading .config files.
-    """
-    return _unescape_sub(r"\1", s)
-
-# unescape() helper
-_unescape_sub = re.compile(r"\\(.)").sub
-
-
-def standard_kconfig(description=None):
-    """
-    Argument parsing helper for tools that take a single optional Kconfig file
-    argument (default: Kconfig). Returns the Kconfig instance for the parsed
-    configuration. Uses argparse internally.
-
-    Exits with sys.exit() (which raises SystemExit) on errors.
-
-    description (default: None):
-      The 'description' passed to argparse.ArgumentParser().
-      argparse.RawDescriptionHelpFormatter is used, so formatting is preserved.
-    """
-    import argparse
-
-    parser = argparse.ArgumentParser(
-        formatter_class=argparse.RawDescriptionHelpFormatter,
-        description=description)
-
-    parser.add_argument(
-        "kconfig",
-        metavar="KCONFIG",
-        default="Kconfig",
-        nargs="?",
-        help="Top-level Kconfig file (default: Kconfig)")
-
-    return Kconfig(parser.parse_args().kconfig, suppress_traceback=True)
-
-
-def standard_config_filename():
-    """
-    Helper for tools. Returns the value of KCONFIG_CONFIG (which specifies the
-    .config file to load/save) if it is set, and ".config" otherwise.
-
-    Calling load_config() with filename=None might give the behavior you want,
-    without having to use this function.
-    """
-    return os.getenv("KCONFIG_CONFIG", ".config")
-
-
-def load_allconfig(kconf, filename):
-    """
-    Use Kconfig.load_allconfig() instead, which was added in Kconfiglib 13.4.0.
-    Supported for backwards compatibility. Might be removed at some point after
-    a long period of deprecation warnings.
-    """
-    allconfig = os.getenv("KCONFIG_ALLCONFIG")
-    if allconfig is None:
-        return
-
-    def std_msg(e):
-        # "Upcasts" a _KconfigIOError to an IOError, removing the custom
-        # __str__() message. The standard message is better here.
-        #
-        # This might also convert an OSError to an IOError in obscure cases,
-        # but it's probably not a big deal. The distinction is shaky (see
-        # PEP-3151).
-        return IOError(e.errno, e.strerror, e.filename)
-
-    old_warn_assign_override = kconf.warn_assign_override
-    old_warn_assign_redun = kconf.warn_assign_redun
-    kconf.warn_assign_override = kconf.warn_assign_redun = False
-
-    if allconfig in ("", "1"):
-        try:
-            print(kconf.load_config(filename, False))
-        except EnvironmentError as e1:
-            try:
-                print(kconf.load_config("all.config", False))
-            except EnvironmentError as e2:
-                sys.exit("error: KCONFIG_ALLCONFIG is set, but neither {} "
-                         "nor all.config could be opened: {}, {}"
-                         .format(filename, std_msg(e1), std_msg(e2)))
-    else:
-        try:
-            print(kconf.load_config(allconfig, False))
-        except EnvironmentError as e:
-            sys.exit("error: KCONFIG_ALLCONFIG is set to '{}', which "
-                     "could not be opened: {}"
-                     .format(allconfig, std_msg(e)))
-
-    kconf.warn_assign_override = old_warn_assign_override
-    kconf.warn_assign_redun = old_warn_assign_redun
-
-
-#
-# Internal functions
-#
-
-
-def _visibility(sc):
-    # Symbols and Choices have a "visibility" that acts as an upper bound on
-    # the values a user can set for them, corresponding to the visibility in
-    # e.g. 'make menuconfig'. This function calculates the visibility for the
-    # Symbol or Choice 'sc' -- the logic is nearly identical.
-
-    vis = 0
-
-    for node in sc.nodes:
-        if node.prompt:
-            vis = max(vis, expr_value(node.prompt[1]))
-
-    if sc.__class__ is Symbol and sc.choice:
-        if sc.choice.orig_type is TRISTATE and \
-           sc.orig_type is not TRISTATE and sc.choice.tri_value != 2:
-            # Non-tristate choice symbols are only visible in y mode
-            return 0
-
-        if sc.orig_type is TRISTATE and vis == 1 and sc.choice.tri_value == 2:
-            # Choice symbols with m visibility are not visible in y mode
-            return 0
-
-    # Promote m to y if we're dealing with a non-tristate (possibly due to
-    # modules being disabled)
-    if vis == 1 and sc.type is not TRISTATE:
-        return 2
-
-    return vis
-
-
-def _depend_on(sc, expr):
-    # Adds 'sc' (symbol or choice) as a "dependee" to all symbols in 'expr'.
-    # Constant symbols in 'expr' are skipped as they can never change value
-    # anyway.
-
-    if expr.__class__ is tuple:
-        # AND, OR, NOT, or relation
-
-        _depend_on(sc, expr[1])
-
-        # NOTs only have a single operand
-        if expr[0] is not NOT:
-            _depend_on(sc, expr[2])
-
-    elif not expr.is_constant:
-        # Non-constant symbol, or choice
-        expr._dependents.add(sc)
-
-
-def _parenthesize(expr, type_, sc_expr_str_fn):
-    # expr_str() helper. Adds parentheses around expressions of type 'type_'.
-
-    if expr.__class__ is tuple and expr[0] is type_:
-        return "({})".format(expr_str(expr, sc_expr_str_fn))
-    return expr_str(expr, sc_expr_str_fn)
-
-
-def _ordered_unique(lst):
-    # Returns 'lst' with any duplicates removed, preserving order. This hacky
-    # version seems to be a common idiom. It relies on short-circuit evaluation
-    # and set.add() returning None, which is falsy.
-
-    seen = set()
-    seen_add = seen.add
-    return [x for x in lst if x not in seen and not seen_add(x)]
-
-
-def _is_base_n(s, n):
-    try:
-        int(s, n)
-        return True
-    except ValueError:
-        return False
-
-
-def _strcmp(s1, s2):
-    # strcmp()-alike that returns -1, 0, or 1
-
-    return (s1 > s2) - (s1 < s2)
-
-
-def _sym_to_num(sym):
-    # expr_value() helper for converting a symbol to a number. Raises
-    # ValueError for symbols that can't be converted.
-
-    # For BOOL and TRISTATE, n/m/y count as 0/1/2. This mirrors 9059a3493ef
-    # ("kconfig: fix relational operators for bool and tristate symbols") in
-    # the C implementation.
-    return sym.tri_value if sym.orig_type in _BOOL_TRISTATE else \
-           int(sym.str_value, _TYPE_TO_BASE[sym.orig_type])
-
-
-def _touch_dep_file(path, sym_name):
-    # If sym_name is MY_SYM_NAME, touches my/sym/name.h. See the sync_deps()
-    # docstring.
-
-    sym_path = path + os.sep + sym_name.lower().replace("_", os.sep) + ".h"
-    sym_path_dir = dirname(sym_path)
-    if not exists(sym_path_dir):
-        os.makedirs(sym_path_dir, 0o755)
-
-    # A kind of truncating touch, mirroring the C tools
-    os.close(os.open(
-        sym_path, os.O_WRONLY | os.O_CREAT | os.O_TRUNC, 0o644))
-
-
-def _save_old(path):
-    # See write_config()
-
-    def copy(src, dst):
-        # Import as needed, to save some startup time
-        import shutil
-        shutil.copyfile(src, dst)
-
-    if islink(path):
-        # Preserve symlinks
-        copy_fn = copy
-    elif hasattr(os, "replace"):
-        # Python 3 (3.3+) only. Best choice when available, because it
-        # removes <filename>.old on both *nix and Windows.
-        copy_fn = os.replace
-    elif os.name == "posix":
-        # Removes <filename>.old on POSIX systems
-        copy_fn = os.rename
-    else:
-        # Fall back on copying
-        copy_fn = copy
-
-    try:
-        copy_fn(path, path + ".old")
-    except Exception:
-        # Ignore errors from 'path' missing as well as other errors.
-        # <filename>.old file is usually more of a nice-to-have, and not worth
-        # erroring out over e.g. if <filename>.old happens to be a directory or
-        # <filename> is something like /dev/null.
-        pass
-
-
-def _locs(sc):
-    # Symbol/Choice.name_and_loc helper. Returns the "(defined at ...)" part of
-    # the string. 'sc' is a Symbol or Choice.
-
-    if sc.nodes:
-        return "(defined at {})".format(
-            ", ".join("{0.filename}:{0.linenr}".format(node)
-                      for node in sc.nodes))
-
-    return "(undefined)"
-
-
-# Menu manipulation
-
-
-def _expr_depends_on(expr, sym):
-    # Reimplementation of expr_depends_symbol() from mconf.c. Used to determine
-    # if a submenu should be implicitly created. This also influences which
-    # items inside choice statements are considered choice items.
-
-    if expr.__class__ is not tuple:
-        return expr is sym
-
-    if expr[0] in _EQUAL_UNEQUAL:
-        # Check for one of the following:
-        # sym = m/y, m/y = sym, sym != n, n != sym
-
-        left, right = expr[1:]
-
-        if right is sym:
-            left, right = right, left
-        elif left is not sym:
-            return False
-
-        return (expr[0] is EQUAL and right is sym.kconfig.m or
-                                     right is sym.kconfig.y) or \
-               (expr[0] is UNEQUAL and right is sym.kconfig.n)
-
-    return expr[0] is AND and \
-           (_expr_depends_on(expr[1], sym) or
-            _expr_depends_on(expr[2], sym))
-
-
-def _auto_menu_dep(node1, node2):
-    # Returns True if node2 has an "automatic menu dependency" on node1. If
-    # node2 has a prompt, we check its condition. Otherwise, we look directly
-    # at node2.dep.
-
-    return _expr_depends_on(node2.prompt[1] if node2.prompt else node2.dep,
-                            node1.item)
-
-
-def _flatten(node):
-    # "Flattens" menu nodes without prompts (e.g. 'if' nodes and non-visible
-    # symbols with children from automatic menu creation) so that their
-    # children appear after them instead. This gives a clean menu structure
-    # with no unexpected "jumps" in the indentation.
-    #
-    # Do not flatten promptless choices (which can appear "legitimately" if a
-    # named choice is defined in multiple locations to add on symbols). It
-    # looks confusing, and the menuconfig already shows all choice symbols if
-    # you enter the choice at some location with a prompt.
-
-    while node:
-        if node.list and not node.prompt and \
-           node.item.__class__ is not Choice:
-
-            last_node = node.list
-            while 1:
-                last_node.parent = node.parent
-                if not last_node.next:
-                    break
-                last_node = last_node.next
-
-            last_node.next = node.next
-            node.next = node.list
-            node.list = None
-
-        node = node.next
-
-
-def _remove_ifs(node):
-    # Removes 'if' nodes (which can be recognized by MenuNode.item being None),
-    # which are assumed to already have been flattened. The C implementation
-    # doesn't bother to do this, but we expose the menu tree directly, and it
-    # makes it nicer to work with.
-
-    cur = node.list
-    while cur and not cur.item:
-        cur = cur.next
-
-    node.list = cur
-
-    while cur:
-        next = cur.next
-        while next and not next.item:
-            next = next.next
-
-        # Equivalent to
-        #
-        #   cur.next = next
-        #   cur = next
-        #
-        # due to tricky Python semantics. The order matters.
-        cur.next = cur = next
-
-
-def _finalize_choice(node):
-    # Finalizes a choice, marking each symbol whose menu node has the choice as
-    # the parent as a choice symbol, and automatically determining types if not
-    # specified.
-
-    choice = node.item
-
-    cur = node.list
-    while cur:
-        if cur.item.__class__ is Symbol:
-            cur.item.choice = choice
-            choice.syms.append(cur.item)
-        cur = cur.next
-
-    # If no type is specified for the choice, its type is that of
-    # the first choice item with a specified type
-    if not choice.orig_type:
-        for item in choice.syms:
-            if item.orig_type:
-                choice.orig_type = item.orig_type
-                break
-
-    # Each choice item of UNKNOWN type gets the type of the choice
-    for sym in choice.syms:
-        if not sym.orig_type:
-            sym.orig_type = choice.orig_type
-
-
-def _check_dep_loop_sym(sym, ignore_choice):
-    # Detects dependency loops using depth-first search on the dependency graph
-    # (which is calculated earlier in Kconfig._build_dep()).
-    #
-    # Algorithm:
-    #
-    #  1. Symbols/choices start out with _visited = 0, meaning unvisited.
-    #
-    #  2. When a symbol/choice is first visited, _visited is set to 1, meaning
-    #     "visited, potentially part of a dependency loop". The recursive
-    #     search then continues from the symbol/choice.
-    #
-    #  3. If we run into a symbol/choice X with _visited already set to 1,
-    #     there's a dependency loop. The loop is found on the call stack by
-    #     recording symbols while returning ("on the way back") until X is seen
-    #     again.
-    #
-    #  4. Once a symbol/choice and all its dependencies (or dependents in this
-    #     case) have been checked recursively without detecting any loops, its
-    #     _visited is set to 2, meaning "visited, not part of a dependency
-    #     loop".
-    #
-    #     This saves work if we run into the symbol/choice again in later calls
-    #     to _check_dep_loop_sym(). We just return immediately.
-    #
-    # Choices complicate things, as every choice symbol depends on every other
-    # choice symbol in a sense. When a choice is "entered" via a choice symbol
-    # X, we visit all choice symbols from the choice except X, and prevent
-    # immediately revisiting the choice with a flag (ignore_choice).
-    #
-    # Maybe there's a better way to handle this (different flags or the
-    # like...)
-
-    if not sym._visited:
-        # sym._visited == 0, unvisited
-
-        sym._visited = 1
-
-        for dep in sym._dependents:
-            # Choices show up in Symbol._dependents when the choice has the
-            # symbol in a 'prompt' or 'default' condition (e.g.
-            # 'default ... if SYM').
-            #
-            # Since we aren't entering the choice via a choice symbol, all
-            # choice symbols need to be checked, hence the None.
-            loop = _check_dep_loop_choice(dep, None) \
-                   if dep.__class__ is Choice \
-                   else _check_dep_loop_sym(dep, False)
-
-            if loop:
-                # Dependency loop found
-                return _found_dep_loop(loop, sym)
-
-        if sym.choice and not ignore_choice:
-            loop = _check_dep_loop_choice(sym.choice, sym)
-            if loop:
-                # Dependency loop found
-                return _found_dep_loop(loop, sym)
-
-        # The symbol is not part of a dependency loop
-        sym._visited = 2
-
-        # No dependency loop found
-        return None
-
-    if sym._visited == 2:
-        # The symbol was checked earlier and is already known to not be part of
-        # a dependency loop
-        return None
-
-    # sym._visited == 1, found a dependency loop. Return the symbol as the
-    # first element in it.
-    return (sym,)
-
-
-def _check_dep_loop_choice(choice, skip):
-    if not choice._visited:
-        # choice._visited == 0, unvisited
-
-        choice._visited = 1
-
-        # Check for loops involving choice symbols. If we came here via a
-        # choice symbol, skip that one, as we'd get a false positive
-        # '<sym FOO> -> <choice> -> <sym FOO>' loop otherwise.
-        for sym in choice.syms:
-            if sym is not skip:
-                # Prevent the choice from being immediately re-entered via the
-                # "is a choice symbol" path by passing True
-                loop = _check_dep_loop_sym(sym, True)
-                if loop:
-                    # Dependency loop found
-                    return _found_dep_loop(loop, choice)
-
-        # The choice is not part of a dependency loop
-        choice._visited = 2
-
-        # No dependency loop found
-        return None
-
-    if choice._visited == 2:
-        # The choice was checked earlier and is already known to not be part of
-        # a dependency loop
-        return None
-
-    # choice._visited == 1, found a dependency loop. Return the choice as the
-    # first element in it.
-    return (choice,)
-
-
-def _found_dep_loop(loop, cur):
-    # Called "on the way back" when we know we have a loop
-
-    # Is the symbol/choice 'cur' where the loop started?
-    if cur is not loop[0]:
-        # Nope, it's just a part of the loop
-        return loop + (cur,)
-
-    # Yep, we have the entire loop. Throw an exception that shows it.
-
-    msg = "\nDependency loop\n" \
-            "===============\n\n"
-
-    for item in loop:
-        if item is not loop[0]:
-            msg += "...depends on "
-            if item.__class__ is Symbol and item.choice:
-                msg += "the choice symbol "
-
-        msg += "{}, with definition...\n\n{}\n\n" \
-               .format(item.name_and_loc, item)
-
-        # Small wart: Since we reuse the already calculated
-        # Symbol/Choice._dependents sets for recursive dependency detection, we
-        # lose information on whether a dependency came from a 'select'/'imply'
-        # condition or e.g. a 'depends on'.
-        #
-        # This might cause selecting symbols to "disappear". For example,
-        # a symbol B having 'select A if C' gives a direct dependency from A to
-        # C, since it corresponds to a reverse dependency of B && C.
-        #
-        # Always print reverse dependencies for symbols that have them to make
-        # sure information isn't lost. I wonder if there's some neat way to
-        # improve this.
-
-        if item.__class__ is Symbol:
-            if item.rev_dep is not item.kconfig.n:
-                msg += "(select-related dependencies: {})\n\n" \
-                       .format(expr_str(item.rev_dep))
-
-            if item.weak_rev_dep is not item.kconfig.n:
-                msg += "(imply-related dependencies: {})\n\n" \
-                       .format(expr_str(item.rev_dep))
-
-    msg += "...depends again on " + loop[0].name_and_loc
-
-    raise KconfigError(msg)
-
-
-def _decoding_error(e, filename, macro_linenr=None):
-    # Gives the filename and context for UnicodeDecodeError's, which are a pain
-    # to debug otherwise. 'e' is the UnicodeDecodeError object.
-    #
-    # If the decoding error is for the output of a $(shell,...) command,
-    # macro_linenr holds the line number where it was run (the exact line
-    # number isn't available for decoding errors in files).
-
-    raise KconfigError(
-        "\n"
-        "Malformed {} in {}\n"
-        "Context: {}\n"
-        "Problematic data: {}\n"
-        "Reason: {}".format(
-            e.encoding,
-            "'{}'".format(filename) if macro_linenr is None else
-                "output from macro at {}:{}".format(filename, macro_linenr),
-            e.object[max(e.start - 40, 0):e.end + 40],
-            e.object[e.start:e.end],
-            e.reason))
-
-
-def _warn_verbose_deprecated(fn_name):
-    sys.stderr.write(
-        "Deprecation warning: {0}()'s 'verbose' argument has no effect. Since "
-        "Kconfiglib 12.0.0, the message is returned from {0}() instead, "
-        "and is always generated. Do e.g. print(kconf.{0}()) if you want to "
-        "want to show a message like \"Loaded configuration '.config'\" on "
-        "stdout. The old API required ugly hacks to reuse messages in "
-        "configuration interfaces.\n".format(fn_name))
-
-
-# Predefined preprocessor functions
-
-
-def _filename_fn(kconf, _):
-    return kconf.filename
-
-
-def _lineno_fn(kconf, _):
-    return str(kconf.linenr)
-
-
-def _info_fn(kconf, _, msg):
-    print("{}:{}: {}".format(kconf.filename, kconf.linenr, msg))
-
-    return ""
-
-
-def _warning_if_fn(kconf, _, cond, msg):
-    if cond == "y":
-        kconf._warn(msg, kconf.filename, kconf.linenr)
-
-    return ""
-
-
-def _error_if_fn(kconf, _, cond, msg):
-    if cond == "y":
-        raise KconfigError("{}:{}: {}".format(
-            kconf.filename, kconf.linenr, msg))
-
-    return ""
-
-
-def _shell_fn(kconf, _, command):
-    import subprocess  # Only import as needed, to save some startup time
-
-    stdout, stderr = subprocess.Popen(
-        command, shell=True, stdout=subprocess.PIPE, stderr=subprocess.PIPE
-    ).communicate()
-
-    if not _IS_PY2:
-        try:
-            stdout = stdout.decode(kconf._encoding)
-            stderr = stderr.decode(kconf._encoding)
-        except UnicodeDecodeError as e:
-            _decoding_error(e, kconf.filename, kconf.linenr)
-
-    if stderr:
-        kconf._warn("'{}' wrote to stderr: {}".format(
-                        command, "\n".join(stderr.splitlines())),
-                    kconf.filename, kconf.linenr)
-
-    # Universal newlines with splitlines() (to prevent e.g. stray \r's in
-    # command output on Windows), trailing newline removal, and
-    # newline-to-space conversion.
-    #
-    # On Python 3 versions before 3.6, it's not possible to specify the
-    # encoding when passing universal_newlines=True to Popen() (the 'encoding'
-    # parameter was added in 3.6), so we do this manual version instead.
-    return "\n".join(stdout.splitlines()).rstrip("\n").replace("\n", " ")
-
-#
-# Global constants
-#
-
-TRI_TO_STR = {
-    0: "n",
-    1: "m",
-    2: "y",
-}
-
-STR_TO_TRI = {
-    "n": 0,
-    "m": 1,
-    "y": 2,
-}
-
-# Constant representing that there's no cached choice selection. This is
-# distinct from a cached None (no selection). Any object that's not None or a
-# Symbol will do. We test this with 'is'.
-_NO_CACHED_SELECTION = 0
-
-# Are we running on Python 2?
-_IS_PY2 = sys.version_info[0] < 3
-
-try:
-    _UNAME_RELEASE = os.uname()[2]
-except AttributeError:
-    # Only import as needed, to save some startup time
-    import platform
-    _UNAME_RELEASE = platform.uname()[2]
-
-# The token and type constants below are safe to test with 'is', which is a bit
-# faster (~30% faster on my machine, and a few % faster for total parsing
-# time), even without assuming Python's small integer optimization (which
-# caches small integer objects). The constants end up pointing to unique
-# integer objects, and since we consistently refer to them via the names below,
-# we always get the same object.
-#
-# Client code should use == though.
-
-# Tokens, with values 1, 2, ... . Avoiding 0 simplifies some checks by making
-# all tokens except empty strings truthy.
-(
-    _T_ALLNOCONFIG_Y,
-    _T_AND,
-    _T_BOOL,
-    _T_CHOICE,
-    _T_CLOSE_PAREN,
-    _T_COMMENT,
-    _T_CONFIG,
-    _T_DEFAULT,
-    _T_DEFCONFIG_LIST,
-    _T_DEF_BOOL,
-    _T_DEF_HEX,
-    _T_DEF_INT,
-    _T_DEF_STRING,
-    _T_DEF_TRISTATE,
-    _T_DEPENDS,
-    _T_ENDCHOICE,
-    _T_ENDIF,
-    _T_ENDMENU,
-    _T_ENV,
-    _T_EQUAL,
-    _T_GREATER,
-    _T_GREATER_EQUAL,
-    _T_HELP,
-    _T_HEX,
-    _T_IF,
-    _T_IMPLY,
-    _T_INT,
-    _T_LESS,
-    _T_LESS_EQUAL,
-    _T_MAINMENU,
-    _T_MENU,
-    _T_MENUCONFIG,
-    _T_MODULES,
-    _T_NOT,
-    _T_ON,
-    _T_OPEN_PAREN,
-    _T_OPTION,
-    _T_OPTIONAL,
-    _T_OR,
-    _T_ORSOURCE,
-    _T_OSOURCE,
-    _T_PROMPT,
-    _T_RANGE,
-    _T_RSOURCE,
-    _T_SELECT,
-    _T_SOURCE,
-    _T_STRING,
-    _T_TRISTATE,
-    _T_UNEQUAL,
-    _T_VISIBLE,
-) = range(1, 51)
-
-# Keyword to token map, with the get() method assigned directly as a small
-# optimization
-_get_keyword = {
-    "---help---":     _T_HELP,
-    "allnoconfig_y":  _T_ALLNOCONFIG_Y,
-    "bool":           _T_BOOL,
-    "boolean":        _T_BOOL,
-    "choice":         _T_CHOICE,
-    "comment":        _T_COMMENT,
-    "config":         _T_CONFIG,
-    "def_bool":       _T_DEF_BOOL,
-    "def_hex":        _T_DEF_HEX,
-    "def_int":        _T_DEF_INT,
-    "def_string":     _T_DEF_STRING,
-    "def_tristate":   _T_DEF_TRISTATE,
-    "default":        _T_DEFAULT,
-    "defconfig_list": _T_DEFCONFIG_LIST,
-    "depends":        _T_DEPENDS,
-    "endchoice":      _T_ENDCHOICE,
-    "endif":          _T_ENDIF,
-    "endmenu":        _T_ENDMENU,
-    "env":            _T_ENV,
-    "grsource":       _T_ORSOURCE,  # Backwards compatibility
-    "gsource":        _T_OSOURCE,   # Backwards compatibility
-    "help":           _T_HELP,
-    "hex":            _T_HEX,
-    "if":             _T_IF,
-    "imply":          _T_IMPLY,
-    "int":            _T_INT,
-    "mainmenu":       _T_MAINMENU,
-    "menu":           _T_MENU,
-    "menuconfig":     _T_MENUCONFIG,
-    "modules":        _T_MODULES,
-    "on":             _T_ON,
-    "option":         _T_OPTION,
-    "optional":       _T_OPTIONAL,
-    "orsource":       _T_ORSOURCE,
-    "osource":        _T_OSOURCE,
-    "prompt":         _T_PROMPT,
-    "range":          _T_RANGE,
-    "rsource":        _T_RSOURCE,
-    "select":         _T_SELECT,
-    "source":         _T_SOURCE,
-    "string":         _T_STRING,
-    "tristate":       _T_TRISTATE,
-    "visible":        _T_VISIBLE,
-}.get
-
-# The constants below match the value of the corresponding tokens to remove the
-# need for conversion
-
-# Node types
-MENU    = _T_MENU
-COMMENT = _T_COMMENT
-
-# Expression types
-AND           = _T_AND
-OR            = _T_OR
-NOT           = _T_NOT
-EQUAL         = _T_EQUAL
-UNEQUAL       = _T_UNEQUAL
-LESS          = _T_LESS
-LESS_EQUAL    = _T_LESS_EQUAL
-GREATER       = _T_GREATER
-GREATER_EQUAL = _T_GREATER_EQUAL
-
-REL_TO_STR = {
-    EQUAL:         "=",
-    UNEQUAL:       "!=",
-    LESS:          "<",
-    LESS_EQUAL:    "<=",
-    GREATER:       ">",
-    GREATER_EQUAL: ">=",
-}
-
-# Symbol/choice types. UNKNOWN is 0 (falsy) to simplify some checks.
-# Client code shouldn't rely on it though, as it was non-zero in
-# older versions.
-UNKNOWN  = 0
-BOOL     = _T_BOOL
-TRISTATE = _T_TRISTATE
-STRING   = _T_STRING
-INT      = _T_INT
-HEX      = _T_HEX
-
-TYPE_TO_STR = {
-    UNKNOWN:  "unknown",
-    BOOL:     "bool",
-    TRISTATE: "tristate",
-    STRING:   "string",
-    INT:      "int",
-    HEX:      "hex",
-}
-
-# Used in comparisons. 0 means the base is inferred from the format of the
-# string.
-_TYPE_TO_BASE = {
-    HEX:      16,
-    INT:      10,
-    STRING:   0,
-    UNKNOWN:  0,
-}
-
-# def_bool -> BOOL, etc.
-_DEF_TOKEN_TO_TYPE = {
-    _T_DEF_BOOL:     BOOL,
-    _T_DEF_HEX:      HEX,
-    _T_DEF_INT:      INT,
-    _T_DEF_STRING:   STRING,
-    _T_DEF_TRISTATE: TRISTATE,
-}
-
-# Tokens after which strings are expected. This is used to tell strings from
-# constant symbol references during tokenization, both of which are enclosed in
-# quotes.
-#
-# Identifier-like lexemes ("missing quotes") are also treated as strings after
-# these tokens. _T_CHOICE is included to avoid symbols being registered for
-# named choices.
-_STRING_LEX = frozenset({
-    _T_BOOL,
-    _T_CHOICE,
-    _T_COMMENT,
-    _T_HEX,
-    _T_INT,
-    _T_MAINMENU,
-    _T_MENU,
-    _T_ORSOURCE,
-    _T_OSOURCE,
-    _T_PROMPT,
-    _T_RSOURCE,
-    _T_SOURCE,
-    _T_STRING,
-    _T_TRISTATE,
-})
-
-# Various sets for quick membership tests. Gives a single global lookup and
-# avoids creating temporary dicts/tuples.
-
-_TYPE_TOKENS = frozenset({
-    _T_BOOL,
-    _T_TRISTATE,
-    _T_INT,
-    _T_HEX,
-    _T_STRING,
-})
-
-_SOURCE_TOKENS = frozenset({
-    _T_SOURCE,
-    _T_RSOURCE,
-    _T_OSOURCE,
-    _T_ORSOURCE,
-})
-
-_REL_SOURCE_TOKENS = frozenset({
-    _T_RSOURCE,
-    _T_ORSOURCE,
-})
-
-# Obligatory (non-optional) sources
-_OBL_SOURCE_TOKENS = frozenset({
-    _T_SOURCE,
-    _T_RSOURCE,
-})
-
-_BOOL_TRISTATE = frozenset({
-    BOOL,
-    TRISTATE,
-})
-
-_BOOL_TRISTATE_UNKNOWN = frozenset({
-    BOOL,
-    TRISTATE,
-    UNKNOWN,
-})
-
-_INT_HEX = frozenset({
-    INT,
-    HEX,
-})
-
-_SYMBOL_CHOICE = frozenset({
-    Symbol,
-    Choice,
-})
-
-_MENU_COMMENT = frozenset({
-    MENU,
-    COMMENT,
-})
-
-_EQUAL_UNEQUAL = frozenset({
-    EQUAL,
-    UNEQUAL,
-})
-
-_RELATIONS = frozenset({
-    EQUAL,
-    UNEQUAL,
-    LESS,
-    LESS_EQUAL,
-    GREATER,
-    GREATER_EQUAL,
-})
-
-# Helper functions for getting compiled regular expressions, with the needed
-# matching function returned directly as a small optimization.
-#
-# Use ASCII regex matching on Python 3. It's already the default on Python 2.
-
-
-def _re_match(regex):
-    return re.compile(regex, 0 if _IS_PY2 else re.ASCII).match
-
-
-def _re_search(regex):
-    return re.compile(regex, 0 if _IS_PY2 else re.ASCII).search
-
-
-# Various regular expressions used during parsing
-
-# The initial token on a line. Also eats leading and trailing whitespace, so
-# that we can jump straight to the next token (or to the end of the line if
-# there is only one token).
-#
-# This regex will also fail to match for empty lines and comment lines.
-#
-# '$' is included to detect preprocessor variable assignments with macro
-# expansions in the left-hand side.
-_command_match = _re_match(r"\s*([A-Za-z0-9_$-]+)\s*")
-
-# An identifier/keyword after the first token. Also eats trailing whitespace.
-# '$' is included to detect identifiers containing macro expansions.
-_id_keyword_match = _re_match(r"([A-Za-z0-9_$/.-]+)\s*")
-
-# A fragment in the left-hand side of a preprocessor variable assignment. These
-# are the portions between macro expansions ($(foo)). Macros are supported in
-# the LHS (variable name).
-_assignment_lhs_fragment_match = _re_match("[A-Za-z0-9_-]*")
-
-# The assignment operator and value (right-hand side) in a preprocessor
-# variable assignment
-_assignment_rhs_match = _re_match(r"\s*(=|:=|\+=)\s*(.*)")
-
-# Special characters/strings while expanding a macro ('(', ')', ',', and '$(')
-_macro_special_search = _re_search(r"\(|\)|,|\$\(")
-
-# Special characters/strings while expanding a string (quotes, '\', and '$(')
-_string_special_search = _re_search(r'"|\'|\\|\$\(')
-
-# Special characters/strings while expanding a symbol name. Also includes
-# end-of-line, in case the macro is the last thing on the line.
-_name_special_search = _re_search(r'[^A-Za-z0-9_$/.-]|\$\(|$')
-
-# A valid right-hand side for an assignment to a string symbol in a .config
-# file, including escaped characters. Extracts the contents.
-_conf_string_match = _re_match(r'"((?:[^\\"]|\\.)*)"')
diff --git a/util/lbcc.c b/util/lbcc.c
index 4a3633153e..2429400cad 100644
--- a/util/lbcc.c
+++ b/util/lbcc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2014 The Chromium OS Authors. All rights reserved.
+ * Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -31,10 +31,10 @@ static const char usage[] =
 /* globals */
 static int hit_errors;
 static int opt_verbose;
-static int is_jump_target[EC_LB_PROG_LEN];	/* does program jump here? */
-static int is_instruction[EC_LB_PROG_LEN];	/* instruction or operand? */
-static char *label[EC_LB_PROG_LEN];		/* labels we've seen */
-static char *reloc_label[EC_LB_PROG_LEN];	/* put label target here */
+static int is_jump_target[EC_LB_PROG_LEN]; /* does program jump here? */
+static int is_instruction[EC_LB_PROG_LEN]; /* instruction or operand? */
+static char *label[EC_LB_PROG_LEN]; /* labels we've seen */
+static char *reloc_label[EC_LB_PROG_LEN]; /* put label target here */
 
 static void Error(const char *format, ...)
 {
@@ -66,32 +66,21 @@ struct safe_lightbar_program {
 
 #define OP(NAME, BYTES, MNEMONIC) NAME,
 #include "lightbar_opcode_list.h"
-enum lightbyte_opcode {
-	LIGHTBAR_OPCODE_TABLE
-	MAX_OPCODE
-};
+enum lightbyte_opcode { LIGHTBAR_OPCODE_TABLE MAX_OPCODE };
 #undef OP
 
 #define OP(NAME, BYTES, MNEMONIC) BYTES,
 #include "lightbar_opcode_list.h"
-static const int num_operands[] = {
-	LIGHTBAR_OPCODE_TABLE
-};
+static const int num_operands[] = { LIGHTBAR_OPCODE_TABLE };
 #undef OP
 
 #define OP(NAME, BYTES, MNEMONIC) MNEMONIC,
 #include "lightbar_opcode_list.h"
-static const char * const opcode_sym[] = {
-	LIGHTBAR_OPCODE_TABLE
-};
+static const char *const opcode_sym[] = { LIGHTBAR_OPCODE_TABLE };
 #undef OP
 
-static const char * const control_sym[] = {
-	"beg", "end", "phase", "<invalid>"
-};
-static const char * const color_sym[] = {
-	"r", "g", "b", "<invalid>"
-};
+static const char *const control_sym[] = { "beg", "end", "phase", "<invalid>" };
+static const char *const color_sym[] = { "r", "g", "b", "<invalid>" };
 
 static void read_binary(FILE *fp, struct safe_lightbar_program *prog)
 {
@@ -232,7 +221,8 @@ static void set_jump_target(uint8_t targ)
 {
 	if (targ >= EC_LB_PROG_LEN) {
 		Warning("program jumps to 0x%02x, "
-			"which out of bounds\n", targ);
+			"which out of bounds\n",
+			targ);
 		return;
 	}
 	is_jump_target[targ] = 1;
@@ -266,7 +256,8 @@ static void disassemble_prog(FILE *fp, struct safe_lightbar_program *prog)
 	for (i = 0; i < EC_LB_PROG_LEN; i++)
 		if (is_jump_target[i] && !is_instruction[i]) {
 			Warning("program jumps to 0x%02x, "
-				"which is not a valid instruction\n", i);
+				"which is not a valid instruction\n",
+				i);
 		}
 }
 
@@ -295,7 +286,6 @@ static int split_line(char *buf, const char *delim, struct parse_s *elt,
 		elt[i].val = (uint32_t)strtoull(w, &e, 0);
 		if (!e || !*e)
 			elt[i].is_num = 1;
-
 	}
 
 	return i;
@@ -377,7 +367,6 @@ static int is_color_arg(char *buf, int expected, uint32_t *valp)
 	} else
 		color = 0;
 
-
 	*valp = ((led & 0xF) << 4) | ((control & 0x3) << 2) | (color & 0x3);
 	return 1;
 }
@@ -390,8 +379,8 @@ static void fixup_symbols(struct safe_lightbar_program *prog)
 		if (reloc_label[i]) {
 			/* Looking for reloc label */
 			for (j = 0; j < EC_LB_PROG_LEN; j++) {
-				if (label[j] && !strcmp(label[j],
-							reloc_label[i])) {
+				if (label[j] &&
+				    !strcmp(label[j], reloc_label[i])) {
 					prog->p.data[i] = j;
 					break;
 				}
@@ -402,7 +391,6 @@ static void fixup_symbols(struct safe_lightbar_program *prog)
 	}
 }
 
-
 static void compile(FILE *fp, struct safe_lightbar_program *prog)
 {
 	char buf[128];
@@ -415,7 +403,6 @@ static void compile(FILE *fp, struct safe_lightbar_program *prog)
 	int i;
 
 	while (fgets(buf, sizeof(buf), fp)) {
-
 		/* We truncate lines that are too long */
 		s = strchr(buf, '\n');
 		if (chopping) {
@@ -458,7 +445,8 @@ static void compile(FILE *fp, struct safe_lightbar_program *prog)
 
 		if (opcode >= MAX_OPCODE) {
 			Error("Unrecognized opcode \"%s\""
-			      " at line %d\n", token[wnum].word, line);
+			      " at line %d\n",
+			      token[wnum].word, line);
 			continue;
 		}
 
@@ -488,7 +476,8 @@ static void compile(FILE *fp, struct safe_lightbar_program *prog)
 				reloc_label[addr++] = strdup(token[wnum].word);
 			else {
 				Error("Missing first jump target "
-				      "at line %d\n", line);
+				      "at line %d\n",
+				      line);
 				break;
 			}
 			wnum++;
@@ -496,7 +485,8 @@ static void compile(FILE *fp, struct safe_lightbar_program *prog)
 				reloc_label[addr++] = strdup(token[wnum].word);
 			else
 				Error("Missing second jump target "
-				      "at line %d\n", line);
+				      "at line %d\n",
+				      line);
 			break;
 
 		case SET_BRIGHTNESS:
@@ -511,14 +501,13 @@ static void compile(FILE *fp, struct safe_lightbar_program *prog)
 		case SET_RAMP_DELAY:
 			/* one 32-bit arg */
 			if (token[wnum].is_num) {
-				prog->p.data[addr++] =
-					(token[wnum].val >> 24) & 0xff;
-				prog->p.data[addr++] =
-					(token[wnum].val >> 16) & 0xff;
-				prog->p.data[addr++] =
-					(token[wnum].val >> 8) & 0xff;
-				prog->p.data[addr++] =
-					token[wnum].val & 0xff;
+				prog->p.data[addr++] = (token[wnum].val >> 24) &
+						       0xff;
+				prog->p.data[addr++] = (token[wnum].val >> 16) &
+						       0xff;
+				prog->p.data[addr++] = (token[wnum].val >> 8) &
+						       0xff;
+				prog->p.data[addr++] = token[wnum].val & 0xff;
 			} else {
 				Error("Missing/invalid arg at line %d\n", line);
 			}
@@ -535,11 +524,11 @@ static void compile(FILE *fp, struct safe_lightbar_program *prog)
 			prog->p.data[addr++] = token[wnum++].val;
 			/* and the color immediate */
 			if (token[wnum].is_num) {
-				prog->p.data[addr++] =
-					token[wnum++].val;
+				prog->p.data[addr++] = token[wnum++].val;
 			} else {
 				Error("Missing/Invalid arg "
-				      "at line %d\n", line);
+				      "at line %d\n",
+				      line);
 				break;
 			}
 			break;
@@ -559,7 +548,8 @@ static void compile(FILE *fp, struct safe_lightbar_program *prog)
 						token[wnum++].val;
 				} else {
 					Error("Missing/Invalid arg "
-					      "at line %d\n", line);
+					      "at line %d\n",
+					      line);
 					break;
 				}
 			}
@@ -604,7 +594,7 @@ int main(int argc, char *argv[])
 	else
 		progname = argv[0];
 
-	opterr = 0;                     /* quiet, you */
+	opterr = 0; /* quiet, you */
 	while ((c = getopt(argc, argv, ":dv")) != -1) {
 		switch (c) {
 		case 'd':
@@ -676,8 +666,8 @@ int main(int argc, char *argv[])
 		compile(ifp, &safe_prog);
 		fclose(ifp);
 		if (!hit_errors) {
-			if (1 != fwrite(safe_prog.p.data,
-					safe_prog.p.size, 1, ofp))
+			if (1 !=
+			    fwrite(safe_prog.p.data, safe_prog.p.size, 1, ofp))
 				Error("%s: Unable to write to %s: %s\n",
 				      progname, outfile, strerror(errno));
 			else
diff --git a/util/lbplay.c b/util/lbplay.c
index 9ab0564b74..8c02903175 100644
--- a/util/lbplay.c
+++ b/util/lbplay.c
@@ -1,4 +1,4 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+/* Copyright 2014 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -126,11 +126,8 @@ int main(int argc, char **argv)
 	 * to see what the limit is. The default is 50msec (20Hz).
 	 */
 	for (i = 0; i < 256; i += 4) {
-		sprintf(buf, "0 %d %d %d 1 %d %d %d 2 %d %d %d 3 %d %d %d",
-			i, 0, 0,
-			0, 0, i,
-			255-i, 255, 0,
-			0, 255, 255-i);
+		sprintf(buf, "0 %d %d %d 1 %d %d %d 2 %d %d %d 3 %d %d %d", i,
+			0, 0, 0, 0, i, 255 - i, 255, 0, 0, 255, 255 - i);
 		lseek(fd_l, 0, SEEK_SET);
 		if (write(fd_l, buf, strlen(buf) + 1) < 0)
 			perror("write to led control");
diff --git a/util/linux_ec_commands_h_check.sh b/util/linux_ec_commands_h_check.sh
index 4c55faca0a..d24beb9b54 100755
--- a/util/linux_ec_commands_h_check.sh
+++ b/util/linux_ec_commands_h_check.sh
@@ -1,6 +1,6 @@
 #!/bin/bash
 #
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/util/llvm-gcov.sh b/util/llvm-gcov.sh
index 7c1c97a7d5..826a901134 100755
--- a/util/llvm-gcov.sh
+++ b/util/llvm-gcov.sh
@@ -1,6 +1,6 @@
 #!/bin/bash
 #
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/util/lock/android.c b/util/lock/android.c
index 8472b6db68..857d6a9473 100644
--- a/util/lock/android.c
+++ b/util/lock/android.c
@@ -1,6 +1,5 @@
 /*
- * Copyright 2016, Google Inc.
- * All rights reserved.
+ * Copyright 2016 Google LLC
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
@@ -12,7 +11,7 @@
  *      copyright notice, this list of conditions and the following
  *      disclaimer in the documentation and/or other materials provided
  *      with the distribution.
- *    * Neither the name of Google Inc. nor the names of its
+ *    * Neither the name of Google LLC nor the names of its
  *      contributors may be used to endorse or promote products derived
  *      from this software without specific prior written permission.
  *
diff --git a/util/lock/android.h b/util/lock/android.h
index bb08486919..dfdd16ce97 100644
--- a/util/lock/android.h
+++ b/util/lock/android.h
@@ -1,6 +1,5 @@
 /*
- * Copyright 2016, Google Inc.
- * All rights reserved.
+ * Copyright 2016 Google LLC
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
@@ -12,7 +11,7 @@
  *      copyright notice, this list of conditions and the following
  *      disclaimer in the documentation and/or other materials provided
  *      with the distribution.
- *    * Neither the name of Google Inc. nor the names of its
+ *    * Neither the name of Google LLC nor the names of its
  *      contributors may be used to endorse or promote products derived
  *      from this software without specific prior written permission.
  *
diff --git a/util/lock/build.mk b/util/lock/build.mk
index 65a63ab9db..ea9bf9bf04 100644
--- a/util/lock/build.mk
+++ b/util/lock/build.mk
@@ -1,5 +1,5 @@
 # -*- makefile -*-
-# Copyright 2012 The Chromium OS Authors. All rights reserved.
+# Copyright 2012 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/util/lock/file_lock.c b/util/lock/file_lock.c
index 36b420d287..c0ed8bd88c 100644
--- a/util/lock/file_lock.c
+++ b/util/lock/file_lock.c
@@ -1,5 +1,4 @@
-/* Copyright 2016, Google Inc.
- * All rights reserved.
+/* Copyright 2016 Google LLC
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
@@ -11,7 +10,7 @@
  *      copyright notice, this list of conditions and the following
  *      disclaimer in the documentation and/or other materials provided
  *      with the distribution.
- *    * Neither the name of Google Inc. nor the names of its
+ *    * Neither the name of Google LLC nor the names of its
  *      contributors may be used to endorse or promote products derived
  *      from this software without specific prior written permission.
  *
@@ -59,7 +58,7 @@
 #include "ipc_lock.h"
 #include "locks.h"
 
-#define SLEEP_INTERVAL_MS	50
+#define SLEEP_INTERVAL_MS 50
 
 static void msecs_to_timespec(int msecs, struct timespec *tmspec)
 {
@@ -100,8 +99,8 @@ static int file_lock_open_or_create(struct ipc_lock *lock)
 		if (!tmpdir)
 			return -1;
 
-		if (snprintf(path, sizeof(path), "%s/%s",
-				tmpdir, lock->filename) < 0) {
+		if (snprintf(path, sizeof(path), "%s/%s", tmpdir,
+			     lock->filename) < 0) {
 			return -1;
 		}
 	} else {
@@ -115,10 +114,9 @@ static int file_lock_open_or_create(struct ipc_lock *lock)
 				return -1;
 		}
 
-		if (snprintf(path, sizeof(path),
-			"%s/%s", dir, lock->filename) < 0)
+		if (snprintf(path, sizeof(path), "%s/%s", dir, lock->filename) <
+		    0)
 			return -1;
-
 	}
 
 	lock->fd = open(path, O_RDWR | O_CREAT, 0600);
@@ -180,9 +178,9 @@ static int file_lock_write_pid(struct ipc_lock *lock)
 {
 	ssize_t len;
 	/*
-         * PIDs are usually 5 digits, but we'll reserve enough room for
+	 * PIDs are usually 5 digits, but we'll reserve enough room for
 	 * a value of 2^32 (10 digits) out of paranoia.
-         */
+	 */
 	char pid_str[11];
 
 	if (ftruncate(lock->fd, 0) < 0) {
diff --git a/util/lock/gec_lock.c b/util/lock/gec_lock.c
index d354ea08f3..64aad0f353 100644
--- a/util/lock/gec_lock.c
+++ b/util/lock/gec_lock.c
@@ -1,5 +1,4 @@
-/* Copyright 2012, Google Inc.
- * All rights reserved.
+/* Copyright 2012 Google LLC
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
@@ -11,7 +10,7 @@
  *      copyright notice, this list of conditions and the following
  *      disclaimer in the documentation and/or other materials provided
  *      with the distribution.
- *    * Neither the name of Google Inc. nor the names of its
+ *    * Neither the name of Google LLC nor the names of its
  *      contributors may be used to endorse or promote products derived
  *      from this software without specific prior written permission.
  *
diff --git a/util/lock/gec_lock.h b/util/lock/gec_lock.h
index 8480700ddd..2e0d8018bc 100644
--- a/util/lock/gec_lock.h
+++ b/util/lock/gec_lock.h
@@ -1,5 +1,4 @@
-/* Copyright 2012, Google Inc.
- * All rights reserved.
+/* Copyright 2012 Google LLC
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
@@ -11,7 +10,7 @@
  *      copyright notice, this list of conditions and the following
  *      disclaimer in the documentation and/or other materials provided
  *      with the distribution.
- *    * Neither the name of Google Inc. nor the names of its
+ *    * Neither the name of Google LLC nor the names of its
  *      contributors may be used to endorse or promote products derived
  *      from this software without specific prior written permission.
  *
diff --git a/util/lock/ipc_lock.h b/util/lock/ipc_lock.h
index 5d0d321af4..aaa4217ae8 100644
--- a/util/lock/ipc_lock.h
+++ b/util/lock/ipc_lock.h
@@ -1,5 +1,4 @@
-/* Copyright 2012, Google Inc.
- * All rights reserved.
+/* Copyright 2012 Google LLC
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
@@ -11,7 +10,7 @@
  *      copyright notice, this list of conditions and the following
  *      disclaimer in the documentation and/or other materials provided
  *      with the distribution.
- *    * Neither the name of Google Inc. nor the names of its
+ *    * Neither the name of Google LLC nor the names of its
  *      contributors may be used to endorse or promote products derived
  *      from this software without specific prior written permission.
  *
@@ -32,17 +31,17 @@
 #define __UTIL_IPC_LOCK_H
 
 struct ipc_lock {
-	int is_held;	/* internal */
-	const char *filename;	/* provided by the developer */
-	int fd;		/* internal */
+	int is_held; /* internal */
+	const char *filename; /* provided by the developer */
+	int fd; /* internal */
 };
 
 /* don't use C99 initializers here, so this can be used in C++ code */
-#define LOCKFILE_INIT(lockfile) \
-	{ \
-		0,		/* is_held */	\
-		lockfile,	/* filename */	\
-		-1,		/* fd */	\
+#define LOCKFILE_INIT(lockfile)                  \
+	{                                        \
+		0, /* is_held */                 \
+			lockfile, /* filename */ \
+			-1, /* fd */             \
 	}
 
 /*
diff --git a/util/lock/locks.h b/util/lock/locks.h
index 6875d91454..9e470b5f7e 100644
--- a/util/lock/locks.h
+++ b/util/lock/locks.h
@@ -1,5 +1,4 @@
-/* Copyright 2012, Google Inc.
- * All rights reserved.
+/* Copyright 2012 Google LLC
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
@@ -11,7 +10,7 @@
  *      copyright notice, this list of conditions and the following
  *      disclaimer in the documentation and/or other materials provided
  *      with the distribution.
- *    * Neither the name of Google Inc. nor the names of its
+ *    * Neither the name of Google LLC nor the names of its
  *      contributors may be used to endorse or promote products derived
  *      from this software without specific prior written permission.
  *
@@ -31,8 +30,8 @@
 #ifndef __UTIL_LOCKS_H
 #define __UTIL_LOCKS_H
 
-#define SYSTEM_LOCKFILE_DIR	"/run/lock"
-#define LOCKFILE_NAME		"firmware_utility_lock"
-#define CROS_EC_LOCKFILE_NAME	"cros_ec_lock"
+#define SYSTEM_LOCKFILE_DIR "/run/lock"
+#define LOCKFILE_NAME "firmware_utility_lock"
+#define CROS_EC_LOCKFILE_NAME "cros_ec_lock"
 
 #endif /* __UTIL_LOCKS_H */
diff --git a/util/make_linux_ec_commands_h.sh b/util/make_linux_ec_commands_h.sh
index 3afb7c2f41..141a5086de 100755
--- a/util/make_linux_ec_commands_h.sh
+++ b/util/make_linux_ec_commands_h.sh
@@ -1,6 +1,6 @@
 #!/bin/bash
 #
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -47,14 +47,14 @@ trap cleanup EXIT
 # Replace license
 patch "${tmp}" << EOF
 @@ -1,6 +1,11 @@
--/* Copyright 2014 The Chromium OS Authors. All rights reserved.
+-/* Copyright 2014 The ChromiumOS Authors
 - * Use of this source code is governed by a BSD-style license that can be
 - * found in the LICENSE file.
 +/* SPDX-License-Identifier: GPL-2.0-only */
 +/*
 + * Host communication command constants for ChromeOS EC
 + *
-+ * Copyright (C) 2012 Google, Inc
++ * Copyright 2012 Google, Inc
 + *
 + * NOTE: This file is auto-generated from ChromeOS EC Open Source code from
 + * https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/include/ec_commands.h
diff --git a/util/migrated_files.sh b/util/migrated_files.sh
index 8ed549b6c5..cec86b565b 100755
--- a/util/migrated_files.sh
+++ b/util/migrated_files.sh
@@ -1,6 +1,6 @@
 #!/bin/bash
 #
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -12,7 +12,7 @@ exit_code=0
 for file in "$@"; do
   ec_file="${file##**/platform/ec/}"
   case "${ec_file}" in
-    baseboard/*|board/*|chip/*|common/fpsensor/*|test/*|util/*|zephyr/*) ;;
+    baseboard/*|board/*|chip/*|*fpsensor*|test/*|util/*|zephyr/*) ;;
     **.c)
       if ! grep -q -F "\${PLATFORM_EC}/${ec_file}" "${cmakes[@]}" ; then
         echo -n "WARNING: ${ec_file} is not used in Zephyr EC. Do not edit this"
diff --git a/util/misc_util.c b/util/misc_util.c
index 1eb6577dbb..29b346f534 100644
--- a/util/misc_util.c
+++ b/util/misc_util.c
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/util/misc_util.h b/util/misc_util.h
index 240d735556..d514a2516e 100644
--- a/util/misc_util.h
+++ b/util/misc_util.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,8 +7,14 @@
 #define __UTIL_MISC_UTIL_H
 
 /* Don't use a macro where an inline will do... */
-static inline int MIN(int a, int b) { return a < b ? a : b; }
-static inline int MAX(int a, int b) { return a > b ? a : b; }
+static inline int MIN(int a, int b)
+{
+	return a < b ? a : b;
+}
+static inline int MAX(int a, int b)
+{
+	return a > b ? a : b;
+}
 
 /**
  * Write a buffer to the file.
diff --git a/util/openocd/board/skyrim.cfg b/util/openocd/board/skyrim.cfg
index a8047ade22..11f31c22ef 100644
--- a/util/openocd/board/skyrim.cfg
+++ b/util/openocd/board/skyrim.cfg
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/util/openocd/npcx.cfg b/util/openocd/npcx.cfg
index 0ab2b42888..888ebafcec 100644
--- a/util/openocd/npcx.cfg
+++ b/util/openocd/npcx.cfg
@@ -1,4 +1,4 @@
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
+# Copyright 2014 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/util/openocd/npcx_cmds.tcl b/util/openocd/npcx_cmds.tcl
index 759e897131..fb7f634bff 100644
--- a/util/openocd/npcx_cmds.tcl
+++ b/util/openocd/npcx_cmds.tcl
@@ -1,4 +1,4 @@
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
+# Copyright 2014 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/util/openocd/target/npcx993f.cfg b/util/openocd/target/npcx993f.cfg
index 690bee489d..b9c7c4e43d 100644
--- a/util/openocd/target/npcx993f.cfg
+++ b/util/openocd/target/npcx993f.cfg
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/util/openocd/target/npcx99nf.cfg b/util/openocd/target/npcx99nf.cfg
index 14dbac9f13..8d0828c4c1 100644
--- a/util/openocd/target/npcx99nf.cfg
+++ b/util/openocd/target/npcx99nf.cfg
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/util/pinmap/chips/it81302.go b/util/pinmap/chips/it81302.go
index 6e593a2c5e..058ac9a03b 100644
--- a/util/pinmap/chips/it81302.go
+++ b/util/pinmap/chips/it81302.go
@@ -1,4 +1,4 @@
-// Copyright 2021 The Chromium OS Authors. All rights reserved.
+// Copyright 2021 The ChromiumOS Authors
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
diff --git a/util/pinmap/chips/npcx993.go b/util/pinmap/chips/npcx993.go
index 7a865c115d..720cd99fb6 100644
--- a/util/pinmap/chips/npcx993.go
+++ b/util/pinmap/chips/npcx993.go
@@ -1,4 +1,4 @@
-// Copyright 2021 The Chromium OS Authors. All rights reserved.
+// Copyright 2021 The ChromiumOS Authors
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
diff --git a/util/pinmap/chips/npcx993_test.go b/util/pinmap/chips/npcx993_test.go
index 6ed4bf2357..a3910416a2 100644
--- a/util/pinmap/chips/npcx993_test.go
+++ b/util/pinmap/chips/npcx993_test.go
@@ -1,4 +1,4 @@
-// Copyright 2021 The Chromium OS Authors. All rights reserved.
+// Copyright 2021 The ChromiumOS Authors
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
diff --git a/util/pinmap/chips/register.go b/util/pinmap/chips/register.go
index 96b655814e..ff6d047140 100644
--- a/util/pinmap/chips/register.go
+++ b/util/pinmap/chips/register.go
@@ -1,4 +1,4 @@
-// Copyright 2021 The Chromium OS Authors. All rights reserved.
+// Copyright 2021 The ChromiumOS Authors
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
diff --git a/util/pinmap/pinmap/main.go b/util/pinmap/pinmap/main.go
index 8b1f1f38f6..1576bac0dd 100644
--- a/util/pinmap/pinmap/main.go
+++ b/util/pinmap/pinmap/main.go
@@ -1,4 +1,4 @@
-// Copyright 2021 The Chromium OS Authors. All rights reserved.
+// Copyright 2021 The ChromiumOS Authors
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
diff --git a/util/pinmap/pm/chip.go b/util/pinmap/pm/chip.go
index a940e7c5fe..9175647c9c 100644
--- a/util/pinmap/pm/chip.go
+++ b/util/pinmap/pm/chip.go
@@ -1,4 +1,4 @@
-// Copyright 2021 The Chromium OS Authors. All rights reserved.
+// Copyright 2021 The ChromiumOS Authors
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
diff --git a/util/pinmap/pm/chip_test.go b/util/pinmap/pm/chip_test.go
index 0bfe601093..1606646588 100644
--- a/util/pinmap/pm/chip_test.go
+++ b/util/pinmap/pm/chip_test.go
@@ -1,4 +1,4 @@
-// Copyright 2021 The Chromium OS Authors. All rights reserved.
+// Copyright 2021 The ChromiumOS Authors
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
diff --git a/util/pinmap/pm/generate.go b/util/pinmap/pm/generate.go
index 835206ad7b..629aeaee15 100644
--- a/util/pinmap/pm/generate.go
+++ b/util/pinmap/pm/generate.go
@@ -1,4 +1,4 @@
-// Copyright 2021 The Chromium OS Authors. All rights reserved.
+// Copyright 2021 The ChromiumOS Authors
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
@@ -17,7 +17,7 @@ type lineName struct {
 	name string // Pin name
 }
 
-const header = `/* Copyright %d The Chromium OS Authors. All rights reserved.
+const header = `/* Copyright %d The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -87,7 +87,6 @@ func adcConfig(out io.Writer, pin *Pin, chip Chip) {
 	}
 	lc := strings.ToLower(pin.Signal)
 	fmt.Fprintf(out, "\t\tadc_%s: %s {\n", lc, lc)
-	fmt.Fprintf(out, "\t\t\tlabel = \"%s\";\n", pin.Signal)
 	if len(pin.Enum) > 0 {
 		fmt.Fprintf(out, "\t\t\tenum-name = \"%s\";\n", pin.Enum)
 	}
@@ -153,7 +152,7 @@ func i2cConfig(out io.Writer, pin *Pin, chip Chip) {
 	fmt.Fprintf(out, "\t\ti2c_%s: %s {\n", lc, lc)
 	fmt.Fprintf(out, "\t\t\ti2c-port = <&%s>;\n", c)
 	if len(pin.Enum) > 0 {
-		fmt.Fprintf(out, "\t\t\tenum-name = \"%s\";\n", pin.Enum)
+		fmt.Fprintf(out, "\t\t\tenum-names = \"%s\";\n", pin.Enum)
 	}
 	fmt.Fprintf(out, "\t\t};\n")
 }
@@ -193,7 +192,7 @@ func generateEnabledNodes(out io.Writer, nodes []string) {
 func generateLineNames(out io.Writer, gpios map[string][]lineName) {
 	// Sort the GPIO controller names.
 	var gcList []string
-	for gc, _ := range gpios {
+	for gc := range gpios {
 		gcList = append(gcList, gc)
 	}
 	sort.Strings(gcList)
diff --git a/util/pinmap/pm/generate_test.go b/util/pinmap/pm/generate_test.go
index 3903180b1b..3ecdb7d1c2 100644
--- a/util/pinmap/pm/generate_test.go
+++ b/util/pinmap/pm/generate_test.go
@@ -1,4 +1,4 @@
-// Copyright 2021 The Chromium OS Authors. All rights reserved.
+// Copyright 2021 The ChromiumOS Authors
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
@@ -72,7 +72,7 @@ func TestGenerate(t *testing.T) {
 	 * However this would considerably complicate this test.
 	 */
 	expFmt :=
-		`/* Copyright %d The Chromium OS Authors. All rights reserved.
+		`/* Copyright %d The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -85,7 +85,6 @@ func TestGenerate(t *testing.T) {
 		compatible = "named-adc-channels";
 
 		adc_ec_adc_1: ec_adc_1 {
-			label = "EC_ADC_1";
 			enum-name = "ENUM_ADC_1";
 			io-channels = <&adc0 A1>;
 		};
@@ -117,15 +116,15 @@ func TestGenerate(t *testing.T) {
 
 		i2c_ec_c_i2c_clk: ec_c_i2c_clk {
 			i2c-port = <&i2c0>;
-			enum-name = "ENUM_I2C_0";
+			enum-names = "ENUM_I2C_0";
 		};
 		i2c_ec_b_i2c_clk: ec_b_i2c_clk {
 			i2c-port = <&i2c1>;
-			enum-name = "ENUM_I2C_1";
+			enum-names = "ENUM_I2C_1";
 		};
 		i2c_ec_a_i2c_clk: ec_a_i2c_clk {
 			i2c-port = <&i2c2>;
-			enum-name = "ENUM_I2C_2";
+			enum-names = "ENUM_I2C_2";
 		};
 	};
 };
diff --git a/util/pinmap/pm/pins.go b/util/pinmap/pm/pins.go
index cb749eb166..61cd7cc043 100644
--- a/util/pinmap/pm/pins.go
+++ b/util/pinmap/pm/pins.go
@@ -1,4 +1,4 @@
-// Copyright 2021 The Chromium OS Authors. All rights reserved.
+// Copyright 2021 The ChromiumOS Authors
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
diff --git a/util/pinmap/pm/reader.go b/util/pinmap/pm/reader.go
index 08dbb9e3af..4af8e29ed9 100644
--- a/util/pinmap/pm/reader.go
+++ b/util/pinmap/pm/reader.go
@@ -1,4 +1,4 @@
-// Copyright 2021 The Chromium OS Authors. All rights reserved.
+// Copyright 2021 The ChromiumOS Authors
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
diff --git a/util/pinmap/pm/reader_test.go b/util/pinmap/pm/reader_test.go
index 5eabf67490..ca004eab6a 100644
--- a/util/pinmap/pm/reader_test.go
+++ b/util/pinmap/pm/reader_test.go
@@ -1,4 +1,4 @@
-// Copyright 2021 The Chromium OS Authors. All rights reserved.
+// Copyright 2021 The ChromiumOS Authors
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
diff --git a/util/pinmap/readers/csv/csv.go b/util/pinmap/readers/csv/csv.go
index 562b5c6383..df763561bb 100644
--- a/util/pinmap/readers/csv/csv.go
+++ b/util/pinmap/readers/csv/csv.go
@@ -1,4 +1,4 @@
-// Copyright 2021 The Chromium OS Authors. All rights reserved.
+// Copyright 2021 The ChromiumOS Authors
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
diff --git a/util/pinmap/readers/csv/csv_test.go b/util/pinmap/readers/csv/csv_test.go
index c0a79ba784..e1140ccb75 100644
--- a/util/pinmap/readers/csv/csv_test.go
+++ b/util/pinmap/readers/csv/csv_test.go
@@ -1,4 +1,4 @@
-// Copyright 2021 The Chromium OS Authors. All rights reserved.
+// Copyright 2021 The ChromiumOS Authors
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
diff --git a/util/pinmap/readers/csv/register.go b/util/pinmap/readers/csv/register.go
index b2f2529061..7ccb18e78a 100644
--- a/util/pinmap/readers/csv/register.go
+++ b/util/pinmap/readers/csv/register.go
@@ -1,4 +1,4 @@
-// Copyright 2021 The Chromium OS Authors. All rights reserved.
+// Copyright 2021 The ChromiumOS Authors
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
diff --git a/util/powerd_lock.c b/util/powerd_lock.c
index 524b456df2..4fdc799203 100644
--- a/util/powerd_lock.c
+++ b/util/powerd_lock.c
@@ -1,7 +1,7 @@
 /*
  * This file is ported from the flashrom project.
  *
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/util/powerd_lock.h b/util/powerd_lock.h
index 86be184a19..1487f28bb7 100644
--- a/util/powerd_lock.h
+++ b/util/powerd_lock.h
@@ -1,7 +1,7 @@
 /*
  * This file is ported from the flashrom project.
  *
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -27,8 +27,8 @@
 enum POWERD_ERROR_CODE {
 	POWERD_OK = 0,
 	POWERD_CREATE_LOCK_FILE_ERROR = 0x1,
-	POWERD_WRITE_LOCK_FILE_ERROR  = 0x2,
-	POWERD_CLOSE_LOCK_FILE_ERROR  = 0x4,
+	POWERD_WRITE_LOCK_FILE_ERROR = 0x2,
+	POWERD_CLOSE_LOCK_FILE_ERROR = 0x4,
 	POWERD_DELETE_LOCK_FILE_ERROR = 0x8
 };
 
@@ -38,4 +38,4 @@ int disable_power_management(void);
 /* Re-enable power management. */
 int restore_power_management(void);
 
-#endif	/* __UTIL_POWERD_LOCK_H */
+#endif /* __UTIL_POWERD_LOCK_H */
diff --git a/util/presubmit_check.sh b/util/presubmit_check.sh
index 7d46f38a0f..5cec68ddd4 100755
--- a/util/presubmit_check.sh
+++ b/util/presubmit_check.sh
@@ -1,6 +1,6 @@
 #!/bin/bash
 #
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
+# Copyright 2014 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/util/run_ects.py b/util/run_ects.py
index 9178328e5f..a3bf4d295c 100644
--- a/util/run_ects.py
+++ b/util/run_ects.py
@@ -1,10 +1,6 @@
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
 
 """Run all eCTS tests and publish results."""
 
@@ -16,81 +12,84 @@ import subprocess
 import sys
 
 # List of tests to run.
-TESTS = ['meta', 'gpio', 'hook', 'i2c', 'interrupt', 'mutex', 'task', 'timer']
+TESTS = ["meta", "gpio", "hook", "i2c", "interrupt", "mutex", "task", "timer"]
 
 
 class CtsRunner(object):
-  """Class running eCTS tests."""
-
-  def __init__(self, ec_dir, dryrun):
-    self.ec_dir = ec_dir
-    self.cts_py = []
-    if dryrun:
-      self.cts_py += ['echo']
-    self.cts_py += [os.path.join(ec_dir, 'cts/cts.py')]
-
-  def run_cmd(self, cmd):
-    try:
-      rc = subprocess.call(cmd)
-      if rc != 0:
-        return False
-    except OSError:
-      return False
-    return True
-
-  def run_test(self, test):
-    cmd = self.cts_py + ['-m', test]
-    self.run_cmd(cmd)
-
-  def run(self, tests):
-    for test in tests:
-      logging.info('Running', test, 'test.')
-      self.run_test(test)
-
-  def sync(self):
-    logging.info('Syncing tree...')
-    os.chdir(self.ec_dir)
-    cmd = ['repo', 'sync', '.']
-    return self.run_cmd(cmd)
-
-  def upload(self):
-    logging.info('Uploading results...')
+    """Class running eCTS tests."""
+
+    def __init__(self, ec_dir, dryrun):
+        self.ec_dir = ec_dir
+        self.cts_py = []
+        if dryrun:
+            self.cts_py += ["echo"]
+        self.cts_py += [os.path.join(ec_dir, "cts/cts.py")]
+
+    def run_cmd(self, cmd):
+        try:
+            rc = subprocess.call(cmd)
+            if rc != 0:
+                return False
+        except OSError:
+            return False
+        return True
+
+    def run_test(self, test):
+        cmd = self.cts_py + ["-m", test]
+        self.run_cmd(cmd)
+
+    def run(self, tests):
+        for test in tests:
+            logging.info("Running %s test.", test)
+            self.run_test(test)
+
+    def sync(self):
+        logging.info("Syncing tree...")
+        os.chdir(self.ec_dir)
+        cmd = ["repo", "sync", "."]
+        return self.run_cmd(cmd)
+
+    def upload(self):
+        logging.info("Uploading results...")
 
 
 def main():
-  if not os.path.exists('/etc/cros_chroot_version'):
-    logging.error('This script has to run inside chroot.')
-    sys.exit(-1)
-
-  ec_dir = os.path.realpath(os.path.dirname(__file__) + '/..')
-
-  parser = argparse.ArgumentParser(description='Run eCTS and report results.')
-  parser.add_argument('-d',
-                      '--dryrun',
-                      action='store_true',
-                      help='Echo commands to be executed without running them.')
-  parser.add_argument('-s',
-                      '--sync',
-                      action='store_true',
-                      help='Sync tree before running tests.')
-  parser.add_argument('-u',
-                      '--upload',
-                      action='store_true',
-                      help='Upload test results.')
-  args = parser.parse_args()
-
-  runner = CtsRunner(ec_dir, args.dryrun)
-
-  if args.sync:
-    if not runner.sync():
-      logging.error('Failed to sync.')
-      sys.exit(-1)
-
-  runner.run(TESTS)
-
-  if args.upload:
-    runner.upload()
-
-
-if __name__ == '__main__':
-  main()
+    if not os.path.exists("/etc/cros_chroot_version"):
+        logging.error("This script has to run inside chroot.")
+        sys.exit(-1)
+
+    ec_dir = os.path.realpath(os.path.dirname(__file__) + "/..")
+
+    parser = argparse.ArgumentParser(description="Run eCTS and report results.")
+    parser.add_argument(
+        "-d",
+        "--dryrun",
+        action="store_true",
+        help="Echo commands to be executed without running them.",
+    )
+    parser.add_argument(
+        "-s",
+        "--sync",
+        action="store_true",
+        help="Sync tree before running tests.",
+    )
+    parser.add_argument(
+        "-u", "--upload", action="store_true", help="Upload test results."
+    )
+    args = parser.parse_args()
+
+    runner = CtsRunner(ec_dir, args.dryrun)
+
+    if args.sync:
+        if not runner.sync():
+            logging.error("Failed to sync.")
+            sys.exit(-1)
+
+    runner.run(TESTS)
+
+    if args.upload:
+        runner.upload()
+
+
+if __name__ == "__main__":
+    main()
diff --git a/util/run_host_test b/util/run_host_test
index cee969dd8c..3108da1852 100755
--- a/util/run_host_test
+++ b/util/run_host_test
@@ -1,6 +1,6 @@
 #!/usr/bin/env python3
 # -*- coding: utf-8 -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/util/run_tests.sh b/util/run_tests.sh
new file mode 100755
index 0000000000..f8af2dc681
--- /dev/null
+++ b/util/run_tests.sh
@@ -0,0 +1,23 @@
+#!/bin/bash
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Runs all the unit tests in the util dir. Uses relative paths, so don't run
+# from any ebuild.
+
+# Show commands being run.
+set -x
+
+# Exit if any command exits non-zero.
+set -e
+
+# cd to the ec directory.
+cd "$(dirname "$(realpath -e "${BASH_SOURCE[0]}")")"/..
+
+# Run pytest
+pytest util "$@"
+
+# Run shell tests
+cd util
+./test-inject-keys.sh
diff --git a/util/shuffle_test.sh b/util/shuffle_test.sh
new file mode 100755
index 0000000000..dfbc1b7a15
--- /dev/null
+++ b/util/shuffle_test.sh
@@ -0,0 +1,59 @@
+#!/bin/bash
+
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+set +x
+
+if [ $# -ne 2 ]; then
+  echo "Usage: $0 <target> <error regex>"
+  exit 1
+fi
+
+target=$1
+pattern=$2
+
+zmake build --clobber "${target}" || exit 1
+
+echo "Searching for '${pattern}'..."
+found_errors=0
+loop_count=100
+start_time=$(date +%Y-%m-%d_%H.%M.%S)
+log_dir="/tmp"
+EXECUTABLE=./build/zephyr/${target}/build-singleimage/zephyr/zephyr.exe
+while [ "${loop_count}" -gt 0 ]; do
+  seed=${RANDOM}
+  log_file_prefix="${log_dir}"/shuffle_"${start_time}"_"${seed}"
+
+  echo "[$((100 - loop_count))] Using seed=${seed}"
+  error_count=$(timeout 150s "${EXECUTABLE}" -seed="${seed}" 2>&1 |
+    tee "${log_file_prefix}".log |
+    grep -c "${pattern}")
+  status=$?
+
+  result="0-matches"
+  if [ "${status}" -eq 124 ]; then
+    echo "    Timeout"
+    result="timed-out"
+  elif [ "${status}" -eq 0 ]; then
+    echo "    Error/timeout"
+    result="exit-code-${status}"
+  fi
+  if [ "${error_count}" -gt 0 ]; then
+    echo "    Found ${error_count} errors matching '${pattern}'"
+    result="${error_count}-matches"
+  fi
+
+  # Rename the log file to include the outcome
+  mv \
+    "${log_file_prefix}".log \
+    "${log_file_prefix}"_"${result}".log
+
+  found_errors=$((found_errors + error_count))
+  loop_count=$((loop_count - 1))
+done
+
+if [ "${found_errors}" -ne 0 ]; then
+  exit 1
+fi
diff --git a/util/sort_by_unconvered.py b/util/sort_by_unconvered.py
new file mode 100755
index 0000000000..217c613aaa
--- /dev/null
+++ b/util/sort_by_unconvered.py
@@ -0,0 +1,59 @@
+#!/usr/bin/python3
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Prints out the lines in an lcov info file in order by uncovered lines.
+
+For example to find the file with the most uncovered lines in herobrine (and
+therefore the likest easy win) run the coverage commands in zephyr/README.md
+and then run:
+
+util/sort_by_unconvered.py build/zephyr/herobrine_final.info | head
+"""
+
+import argparse
+import re
+import subprocess
+
+
+def main():
+    """Main function"""
+    parser = argparse.ArgumentParser(allow_abbrev=False)
+    parser.add_argument(
+        "lcov_files",
+        nargs="+",
+        metavar="lcov_file",
+        help="Name(s) of the lcov files to analyze",
+        default=[],
+    )
+    args = parser.parse_args()
+
+    cmd = ["lcov", "--list-full-path", "--list"] + args.lcov_files
+    output = subprocess.run(
+        cmd, check=True, stdout=subprocess.PIPE, universal_newlines=True
+    ).stdout
+
+    pattern = re.compile(r"^(/\S+)\s*\|\s*([0-9\.]*)%\s*(\d+)\s*\|")
+    results = []
+    for line in output.splitlines():
+        match = pattern.match(line)
+        if match:
+            results.append(
+                (
+                    match[1],  # Filename
+                    match[2],  # Percent
+                    int(match[3]),  # Total lines
+                    int(
+                        float(match[2]) * int(match[3]) / 100.0
+                    ),  # Covered Lines
+                )
+            )
+
+    results.sort(key=lambda x: x[2] - x[3], reverse=True)
+    for res in results:
+        print(f"{res[0]}: {res[3]}/{res[2]} ({res[1]}%)")
+
+
+if __name__ == "__main__":
+    main()
diff --git a/util/stm32mon.c b/util/stm32mon.c
index 129e602439..352158ae73 100644
--- a/util/stm32mon.c
+++ b/util/stm32mon.c
@@ -1,4 +1,4 @@
-/* Copyright 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright 2012 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -17,7 +17,7 @@
 
 /* use cfmakeraw() */
 #define _DEFAULT_SOURCE /* Newer glibc */
-#define _BSD_SOURCE     /* Older glibc */
+#define _BSD_SOURCE /* Older glibc */
 
 #include <arpa/inet.h>
 #include <compile_time_macros.h>
@@ -39,52 +39,48 @@
 
 #include "ec_version.h"
 
-#define KBYTES_TO_BYTES		1024
+#define KBYTES_TO_BYTES 1024
 
 /*
  * Some Ubuntu versions do not export SPI_IOC_WR_MODE32 even though
  * the kernel shipped on those supports it.
  */
 #ifndef SPI_IOC_WR_MODE32
-#define SPI_IOC_WR_MODE32		_IOW(SPI_IOC_MAGIC, 5, __u32)
+#define SPI_IOC_WR_MODE32 _IOW(SPI_IOC_MAGIC, 5, __u32)
 #endif
 
 /* Monitor command set */
-#define CMD_INIT 0x7f    /* Starts the monitor */
+#define CMD_INIT 0x7f /* Starts the monitor */
 
-#define CMD_GETCMD   0x00 /* Gets the allowed commands */
-#define CMD_GETVER   0x01 /* Gets the bootloader version */
-#define CMD_GETID    0x02 /* Gets the Chip ID */
-#define CMD_READMEM  0x11 /* Reads memory */
-#define CMD_GO       0x21 /* Jumps to user code */
+#define CMD_GETCMD 0x00 /* Gets the allowed commands */
+#define CMD_GETVER 0x01 /* Gets the bootloader version */
+#define CMD_GETID 0x02 /* Gets the Chip ID */
+#define CMD_READMEM 0x11 /* Reads memory */
+#define CMD_GO 0x21 /* Jumps to user code */
 #define CMD_WRITEMEM 0x31 /* Writes memory (SRAM or Flash) */
-#define CMD_ERASE    0x43 /* Erases n pages of Flash memory */
+#define CMD_ERASE 0x43 /* Erases n pages of Flash memory */
 #define CMD_EXTERASE 0x44 /* Erases n pages of Flash memory */
 #define CMD_NO_STRETCH_ERASE 0x45 /* Erases while sending busy frame */
-#define CMD_WP       0x63 /* Enables write protect */
-#define CMD_WU       0x73 /* Disables write protect */
-#define CMD_RP       0x82 /* Enables the read protection */
-#define CMD_RU       0x92 /* Disables the read protection */
-
-#define CMD_LOOKUP_ENTRY(COMMAND) {CMD_##COMMAND, #COMMAND}
+#define CMD_WP 0x63 /* Enables write protect */
+#define CMD_WU 0x73 /* Disables write protect */
+#define CMD_RP 0x82 /* Enables the read protection */
+#define CMD_RU 0x92 /* Disables the read protection */
+
+#define CMD_LOOKUP_ENTRY(COMMAND)       \
+	{                               \
+		CMD_##COMMAND, #COMMAND \
+	}
 const struct {
 	const uint8_t cmd;
 	const char *name;
 } cmd_lookup_table[] = {
-	CMD_LOOKUP_ENTRY(INIT),
-	CMD_LOOKUP_ENTRY(GETCMD),
-	CMD_LOOKUP_ENTRY(GETVER),
-	CMD_LOOKUP_ENTRY(GETID),
-	CMD_LOOKUP_ENTRY(READMEM),
-	CMD_LOOKUP_ENTRY(GO),
-	CMD_LOOKUP_ENTRY(WRITEMEM),
-	CMD_LOOKUP_ENTRY(ERASE),
-	CMD_LOOKUP_ENTRY(EXTERASE),
-	CMD_LOOKUP_ENTRY(NO_STRETCH_ERASE),
-	CMD_LOOKUP_ENTRY(WP),
-	CMD_LOOKUP_ENTRY(WU),
-	CMD_LOOKUP_ENTRY(RP),
-	CMD_LOOKUP_ENTRY(RU),
+	CMD_LOOKUP_ENTRY(INIT),	    CMD_LOOKUP_ENTRY(GETCMD),
+	CMD_LOOKUP_ENTRY(GETVER),   CMD_LOOKUP_ENTRY(GETID),
+	CMD_LOOKUP_ENTRY(READMEM),  CMD_LOOKUP_ENTRY(GO),
+	CMD_LOOKUP_ENTRY(WRITEMEM), CMD_LOOKUP_ENTRY(ERASE),
+	CMD_LOOKUP_ENTRY(EXTERASE), CMD_LOOKUP_ENTRY(NO_STRETCH_ERASE),
+	CMD_LOOKUP_ENTRY(WP),	    CMD_LOOKUP_ENTRY(WU),
+	CMD_LOOKUP_ENTRY(RP),	    CMD_LOOKUP_ENTRY(RU),
 };
 
 const char *cmd_lookup_name(uint8_t cmd)
@@ -98,27 +94,27 @@ const char *cmd_lookup_name(uint8_t cmd)
 	return NULL;
 }
 
-#define RESP_NACK        0x1f
-#define RESP_ACK         0x79 /* 0b 0111 1001 */
-#define RESP_BUSY        0x76
+#define RESP_NACK 0x1f
+#define RESP_ACK 0x79 /* 0b 0111 1001 */
+#define RESP_BUSY 0x76
 #define RESP_DAMAGED_ACK 0xBC /* 0b 1011 1100, 1 bit shifted REST_ACK */
 
 /* SPI Start of Frame */
-#define SOF          0x5A
+#define SOF 0x5A
 
 /* Extended erase special parameters */
-#define ERASE_ALL    0xffff
-#define ERASE_BANK1  0xfffe
-#define ERASE_BANK2  0xfffd
+#define ERASE_ALL 0xffff
+#define ERASE_BANK1 0xfffe
+#define ERASE_BANK2 0xfffd
 
 /* Upper bound of rebooting the monitor */
 #define MAX_DELAY_REBOOT 100000 /* us */
 
 /* Standard addresses common across various ST chips */
-#define STM32_MAIN_MEMORY_ADDR		0x08000000
-#define STM32_SYSTEM_MEMORY_ADDR	0x1FFF0000
+#define STM32_MAIN_MEMORY_ADDR 0x08000000
+#define STM32_SYSTEM_MEMORY_ADDR 0x1FFF0000
 
-#define STM32_UNIQUE_ID_SIZE_BYTES	12
+#define STM32_UNIQUE_ID_SIZE_BYTES 12
 
 /*
  * Device electronic signature contains factory-programmed identification
@@ -166,7 +162,7 @@ struct memory_layout {
 
 /* known STM32 SoC parameters */
 struct stm32_def {
-	uint16_t   id;
+	uint16_t id;
 	const char *name;
 	uint32_t flash_size;
 	uint32_t page_size;
@@ -285,8 +281,8 @@ struct stm32_def {
 #define DEFAULT_BAUDRATE B38400
 #define PAGE_SIZE 256
 #define INVALID_I2C_ADAPTER -1
-#define MAX_ACK_RETRY_COUNT	(EXT_ERASE_TIMEOUT / DEFAULT_TIMEOUT)
-#define MAX_RETRY_COUNT		3
+#define MAX_ACK_RETRY_COUNT (EXT_ERASE_TIMEOUT / DEFAULT_TIMEOUT)
+#define MAX_RETRY_COUNT 3
 
 enum interface_mode {
 	MODE_SERIAL,
@@ -315,24 +311,24 @@ int retry_on_damaged_ack;
 
 /* STM32MON function return values */
 enum {
-	STM32_SUCCESS   = 0,
-	STM32_EIO       = -1,	/* IO error */
-	STM32_EINVAL    = -2,	/* Got a faulty response from device */
-	STM32_ETIMEDOUT = -3,	/* Device didn't respond in a time window. */
-	STM32_ENOMEM    = -4,	/* Failed to allocate memory. */
-	STM32_ENACK     = -5,	/* Got NACK. */
-	STM32_EDACK     = -6,	/* Got a damanged ACK. */
+	STM32_SUCCESS = 0,
+	STM32_EIO = -1, /* IO error */
+	STM32_EINVAL = -2, /* Got a faulty response from device */
+	STM32_ETIMEDOUT = -3, /* Device didn't respond in a time window. */
+	STM32_ENOMEM = -4, /* Failed to allocate memory. */
+	STM32_ENACK = -5, /* Got NACK. */
+	STM32_EDACK = -6, /* Got a damanged ACK. */
 };
 BUILD_ASSERT(STM32_SUCCESS == 0);
-#define IS_STM32_ERROR(res)		((res) < STM32_SUCCESS)
+#define IS_STM32_ERROR(res) ((res) < STM32_SUCCESS)
 
 /* optional command flags */
 enum {
-	FLAG_UNPROTECT      = 0x01,
-	FLAG_ERASE          = 0x02,
-	FLAG_GO             = 0x04,
+	FLAG_UNPROTECT = 0x01,
+	FLAG_ERASE = 0x02,
+	FLAG_GO = 0x04,
 	FLAG_READ_UNPROTECT = 0x08,
-	FLAG_CR50_MODE	    = 0x10,
+	FLAG_CR50_MODE = 0x10,
 };
 
 typedef struct {
@@ -357,14 +353,11 @@ static FILE *log_file;
 
 /* Statistic data structure for response kind. */
 struct {
-	const char * const event_name;
+	const char *const event_name;
 	uint32_t event_count;
 } stat_resp[] = {
-	{ "RESP_ACK",	0 },
-	{ "RESP_NACK",	0 },
-	{ "RESP_BUSY",	0 },
-	{ "RESP_DAMAGED_ACK", 0 },
-	{ "JUNK",	0 },
+	{ "RESP_ACK", 0 },	   { "RESP_NACK", 0 }, { "RESP_BUSY", 0 },
+	{ "RESP_DAMAGED_ACK", 0 }, { "JUNK", 0 },
 };
 
 enum {
@@ -389,7 +382,7 @@ static void dump_log(const char *prefix, const void *data, size_t count)
 
 	fprintf(log_file, "%s: ", prefix);
 	for (i = 0; i < count; i++) {
-		if (i && !(i  % 16))
+		if (i && !(i % 16))
 			fprintf(log_file, "\n   ");
 		fprintf(log_file, " %02x", ((uint8_t *)data)[i]);
 	}
@@ -560,7 +553,6 @@ static void discard_input(int fd)
 	do {
 		res = read_wrapper(fd, buffer, sizeof(buffer));
 		if (res > 0) {
-
 			/* Discard zeros in the beginning of the buffer. */
 			for (i = 0; i < res; i++)
 				if (buffer[i])
@@ -652,8 +644,8 @@ int wait_for_ack(int fd)
 	return STM32_ETIMEDOUT;
 }
 
-int send_command(int fd, uint8_t cmd, payload_t *loads, int cnt,
-		 uint8_t *resp, int resp_size, int ack_requested)
+int send_command(int fd, uint8_t cmd, payload_t *loads, int cnt, uint8_t *resp,
+		 int resp_size, int ack_requested)
 {
 	int res, i, c;
 	payload_t *p;
@@ -755,7 +747,8 @@ int send_command(int fd, uint8_t cmd, payload_t *loads, int cnt,
 			} else if (IS_STM32_ERROR(res)) {
 				fprintf(stderr,
 					"Failed to get response to command"
-					" 0x%02x ACK\n", cmd);
+					" 0x%02x ACK\n",
+					cmd);
 				return res;
 			}
 		}
@@ -767,8 +760,8 @@ int send_command(int fd, uint8_t cmd, payload_t *loads, int cnt,
 	return readcnt;
 }
 
-int send_command_retry(int fd, uint8_t cmd, payload_t *loads,
-		int cnt, uint8_t *resp, int resp_size, int ack_requested)
+int send_command_retry(int fd, uint8_t cmd, payload_t *loads, int cnt,
+		       uint8_t *resp, int resp_size, int ack_requested)
 {
 	int res;
 	int retries = MAX_RETRY_COUNT;
@@ -777,7 +770,7 @@ int send_command_retry(int fd, uint8_t cmd, payload_t *loads,
 		int ack_tries = MAX_ACK_RETRY_COUNT;
 
 		res = send_command(fd, cmd, loads, cnt, resp, resp_size,
-			ack_requested);
+				   ack_requested);
 
 		while (res == STM32_ETIMEDOUT && ack_tries--) {
 			if (cmd == CMD_WRITEMEM) {
@@ -807,8 +800,8 @@ struct stm32_def *command_get_id(int fd)
 	res = send_command(fd, CMD_GETID, NULL, 0, id, sizeof(id), 1);
 	if (res > 0) {
 		if (id[0] != 1) {
-			fprintf(stderr, "unknown ID : %02x %02x %02x\n",
-				id[0], id[1], id[2]);
+			fprintf(stderr, "unknown ID : %02x %02x %02x\n", id[0],
+				id[1], id[2]);
 			return NULL;
 		}
 		chipid = (id[1] << 8) | id[2];
@@ -891,8 +884,8 @@ int command_get_commands(int fd, struct stm32_def *chip)
 				cmds[0]);
 			return STM32_EINVAL;
 		}
-		printf("Bootloader v%d.%d, commands : ",
-		       cmds[1] >> 4, cmds[1] & 0xf);
+		printf("Bootloader v%d.%d, commands : ", cmds[1] >> 4,
+		       cmds[1] & 0xf);
 		boot_loader_version = cmds[1];
 
 		erase = command_erase;
@@ -920,10 +913,10 @@ int command_get_commands(int fd, struct stm32_def *chip)
 
 static int use_progressbar;
 static int windex;
-static const char wheel[] = {'|', '/', '-', '\\' };
+static const char wheel[] = { '|', '/', '-', '\\' };
 static void draw_spinner(uint32_t remaining, uint32_t size)
 {
-	int percent = (size - remaining)*100/size;
+	int percent = (size - remaining) * 100 / size;
 	if (use_progressbar) {
 		int dots = percent / 4;
 
@@ -944,15 +937,12 @@ int command_read_mem(int fd, uint32_t address, uint32_t size, uint8_t *buffer)
 	uint32_t remaining = size;
 	uint32_t addr_be;
 	uint8_t cnt;
-	payload_t loads[2] = {
-		{4, (uint8_t *)&addr_be},
-		{1, &cnt}
-	};
+	payload_t loads[2] = { { 4, (uint8_t *)&addr_be }, { 1, &cnt } };
 
 	while (remaining) {
 		uint32_t bytes = MIN(remaining, PAGE_SIZE);
 
-		cnt = (uint8_t) (bytes - 1);
+		cnt = (uint8_t)(bytes - 1);
 		addr_be = htonl(address);
 
 		draw_spinner(remaining, size);
@@ -978,10 +968,8 @@ int command_write_mem(int fd, uint32_t address, uint32_t size, uint8_t *buffer)
 	uint32_t addr_be;
 	uint32_t cnt;
 	uint8_t outbuf[257];
-	payload_t loads[2] = {
-		{4, (uint8_t *)&addr_be},
-		{sizeof(outbuf), outbuf}
-	};
+	payload_t loads[2] = { { 4, (uint8_t *)&addr_be },
+			       { sizeof(outbuf), outbuf } };
 
 	while (remaining) {
 		cnt = MIN(remaining, PAGE_SIZE);
@@ -997,7 +985,7 @@ int command_write_mem(int fd, uint32_t address, uint32_t size, uint8_t *buffer)
 			draw_spinner(remaining, size);
 
 			res = send_command_retry(fd, CMD_WRITEMEM, loads, 2,
-					   NULL, 0, 1);
+						 NULL, 0, 1);
 			if (IS_STM32_ERROR(res))
 				return STM32_EIO;
 		}
@@ -1026,7 +1014,7 @@ int command_ext_erase(int fd, uint16_t count, uint16_t start)
 		load.data = (uint8_t *)pages;
 		pages[0] = htons(count - 1);
 		for (i = 0; i < count; i++)
-			pages[i+1] = htons(start + i);
+			pages[i + 1] = htons(start + i);
 	}
 
 	printf("Erasing...\n");
@@ -1045,8 +1033,8 @@ int command_erase_i2c(int fd, uint16_t count, uint16_t start)
 	uint8_t erase_cmd;
 	uint16_t count_be = htons(count);
 	payload_t load[2] = {
-		{ 2, (uint8_t *)&count_be},
-		{ 0, NULL},
+		{ 2, (uint8_t *)&count_be },
+		{ 0, NULL },
 	};
 	int load_cnt = 1;
 	uint16_t *pages = NULL;
@@ -1071,7 +1059,7 @@ int command_erase_i2c(int fd, uint16_t count, uint16_t start)
 	}
 
 	erase_cmd = (boot_loader_version == 0x10) ? CMD_EXTERASE :
-		     CMD_NO_STRETCH_ERASE;
+						    CMD_NO_STRETCH_ERASE;
 
 	printf("Erasing...\n");
 	res = send_command(fd, erase_cmd, load, load_cnt, NULL, 0, 1);
@@ -1083,7 +1071,6 @@ int command_erase_i2c(int fd, uint16_t count, uint16_t start)
 	return res;
 }
 
-
 int command_erase(int fd, uint16_t count, uint16_t start)
 {
 	int res;
@@ -1101,7 +1088,7 @@ int command_erase(int fd, uint16_t count, uint16_t start)
 		load.data = (uint8_t *)pages;
 		pages[0] = count - 1;
 		for (i = 0; i < count; i++)
-			pages[i+1] = start + i;
+			pages[i + 1] = start + i;
 	}
 
 	printf("Erasing...\n");
@@ -1241,8 +1228,10 @@ int read_device_signature_register(int fd, const struct stm32_def *chip,
 	}
 
 	if (addr <= otp_end_addr) {
-		fprintf(stderr, "Attempting to read from invalid address: "
-				"%08X\n", addr);
+		fprintf(stderr,
+			"Attempting to read from invalid address: "
+			"%08X\n",
+			addr);
 		return STM32_EINVAL;
 	}
 
@@ -1290,9 +1279,9 @@ int read_flash_size_register(int fd, struct stm32_def *chip,
 	if (!flash_size_addr)
 		return STM32_EINVAL;
 
-	res = read_device_signature_register(fd, chip,
-		flash_size_addr, sizeof(*flash_size_kbytes),
-		(uint8_t *)flash_size_kbytes);
+	res = read_device_signature_register(fd, chip, flash_size_addr,
+					     sizeof(*flash_size_kbytes),
+					     (uint8_t *)flash_size_kbytes);
 
 	if (!IS_STM32_ERROR(res))
 		printf("Flash size: %" PRIu16 " KB\n", *flash_size_kbytes);
@@ -1306,7 +1295,7 @@ int read_flash_size_register(int fd, struct stm32_def *chip,
 
 /* Return zero on success, a negative error value on failures. */
 int read_unique_device_id_register(int fd, struct stm32_def *chip,
-	uint8_t device_id[STM32_UNIQUE_ID_SIZE_BYTES])
+				   uint8_t device_id[STM32_UNIQUE_ID_SIZE_BYTES])
 {
 	int i;
 	int res;
@@ -1317,7 +1306,8 @@ int read_unique_device_id_register(int fd, struct stm32_def *chip,
 		return STM32_EINVAL;
 
 	res = read_device_signature_register(fd, chip, unique_device_id_addr,
-		STM32_UNIQUE_ID_SIZE_BYTES, device_id);
+					     STM32_UNIQUE_ID_SIZE_BYTES,
+					     device_id);
 
 	if (!IS_STM32_ERROR(res)) {
 		printf("Unique Device ID: 0x");
@@ -1353,7 +1343,8 @@ int read_package_data_register(int fd, struct stm32_def *chip,
 	else
 		fprintf(stderr,
 			"Failed to read package data register (0x%08X). "
-			"Ignoring non-critical failure.\n", package_data_addr);
+			"Ignoring non-critical failure.\n",
+			package_data_addr);
 
 	return res;
 }
@@ -1445,25 +1436,16 @@ int write_flash(int fd, struct stm32_def *chip, const char *filename,
 }
 
 static const struct option longopts[] = {
-	{"adapter", 1, 0, 'a'},
-	{"baudrate", 1, 0, 'b'},
-	{"cr50", 0, 0, 'c'},
-	{"device", 1, 0, 'd'},
-	{"erase", 0, 0, 'e'},
-	{"go", 0, 0, 'g'},
-	{"help", 0, 0, 'h'},
-	{"length", 1, 0, 'n'},
-	{"location", 1, 0, 'l'},
-	{"logfile", 1, 0, 'L'},
-	{"offset", 1, 0, 'o'},
-	{"progressbar", 0, 0, 'p'},
-	{"read", 1, 0, 'r'},
-	{"retries", 1, 0, 'R'},
-	{"spi", 1, 0, 's'},
-	{"unprotect", 0, 0, 'u'},
-	{"version", 0, 0, 'v'},
-	{"write", 1, 0, 'w'},
-	{NULL, 0, 0, 0}
+	{ "adapter", 1, 0, 'a' },  { "baudrate", 1, 0, 'b' },
+	{ "cr50", 0, 0, 'c' },	   { "device", 1, 0, 'd' },
+	{ "erase", 0, 0, 'e' },	   { "go", 0, 0, 'g' },
+	{ "help", 0, 0, 'h' },	   { "length", 1, 0, 'n' },
+	{ "location", 1, 0, 'l' }, { "logfile", 1, 0, 'L' },
+	{ "offset", 1, 0, 'o' },   { "progressbar", 0, 0, 'p' },
+	{ "read", 1, 0, 'r' },	   { "retries", 1, 0, 'R' },
+	{ "spi", 1, 0, 's' },	   { "unprotect", 0, 0, 'u' },
+	{ "version", 0, 0, 'v' },  { "write", 1, 0, 'w' },
+	{ NULL, 0, 0, 0 }
 };
 
 void display_usage(char *program)
@@ -1498,9 +1480,9 @@ void display_usage(char *program)
 			"the spinner\n");
 	fprintf(stderr, "--R[etries] <num> : limit connect retries to num\n");
 	fprintf(stderr, "-L[ogfile] <file> : save all communications exchange "
-		"in a log file\n");
+			"in a log file\n");
 	fprintf(stderr, "-c[r50_mode] : consider device to be a Cr50 interface,"
-		" no need to set UART port attributes\n");
+			" no need to set UART port attributes\n");
 	fprintf(stderr, "--v[ersion] : print version and exit\n");
 
 	exit(2);
@@ -1509,7 +1491,7 @@ void display_usage(char *program)
 void display_version(const char *exe_name)
 {
 	printf("%s version: %s %s %s\n", exe_name, CROS_STM32MON_VERSION, DATE,
-		BUILDER);
+	       BUILDER);
 }
 
 speed_t parse_baudrate(const char *value)
@@ -1528,8 +1510,8 @@ speed_t parse_baudrate(const char *value)
 	case 115200:
 		return B115200;
 	default:
-		fprintf(stderr, "Invalid baudrate %s, using %d\n",
-			value, DEFAULT_BAUDRATE);
+		fprintf(stderr, "Invalid baudrate %s, using %d\n", value,
+			DEFAULT_BAUDRATE);
 		return DEFAULT_BAUDRATE;
 	}
 }
@@ -1626,7 +1608,7 @@ static void display_stat_response(void)
 	printf("--\n");
 	for (idx = 0; idx < total_events; ++idx) {
 		printf("%-18s %d\n", stat_resp[idx].event_name,
-				stat_resp[idx].event_count);
+		       stat_resp[idx].event_count);
 	}
 	printf("--\n");
 }
diff --git a/util/tagbranch.sh b/util/tagbranch.sh
index e925ddf33a..850886e08c 100755
--- a/util/tagbranch.sh
+++ b/util/tagbranch.sh
@@ -1,6 +1,6 @@
 #!/bin/bash
 #
-# Copyright 2017 The Chromium OS Authors. All rights reserved.
+# Copyright 2017 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/util/temp_metrics.conf b/util/temp_metrics.conf
index ccd3254beb..174571f72a 100644
--- a/util/temp_metrics.conf
+++ b/util/temp_metrics.conf
@@ -1,4 +1,4 @@
-# Copyright 2012 The Chromium OS Authors. All rights reserved.
+# Copyright 2012 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/util/test-inject-keys.sh b/util/test-inject-keys.sh
index 031452150e..44ba3324d3 100755
--- a/util/test-inject-keys.sh
+++ b/util/test-inject-keys.sh
@@ -1,6 +1,6 @@
 #!/bin/bash
 #
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
+# Copyright 2016 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/util/test_kconfig_check.py b/util/test_kconfig_check.py
index cd1b9bf098..3e459006b1 100644
--- a/util/test_kconfig_check.py
+++ b/util/test_kconfig_check.py
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 """Test for Kconfig checker"""
@@ -16,7 +16,8 @@ import kconfig_check
 
 # Prefix that we strip from each Kconfig option, when considering whether it is
 # equivalent to a CONFIG option with the same name
-PREFIX = 'PLATFORM_EC_'
+PREFIX = "PLATFORM_EC_"
+
 
 @contextlib.contextmanager
 def capture_sys_output():
@@ -39,38 +40,50 @@ def capture_sys_output():
 # directly from Python. You can still run this test with 'pytest' if you like.
 class KconfigCheck(unittest.TestCase):
     """Tests for the KconfigCheck class"""
+
     def test_simple_check(self):
         """Check it detected a new ad-hoc CONFIG"""
         checker = kconfig_check.KconfigCheck()
-        self.assertEqual(['NEW_ONE'], checker.find_new_adhoc(
-            configs=['NEW_ONE', 'OLD_ONE', 'IN_KCONFIG'],
-            kconfigs=['IN_KCONFIG'],
-            allowed=['OLD_ONE']))
+        self.assertEqual(
+            ["NEW_ONE"],
+            checker.find_new_adhoc(
+                configs=["NEW_ONE", "OLD_ONE", "IN_KCONFIG"],
+                kconfigs=["IN_KCONFIG"],
+                allowed=["OLD_ONE"],
+            ),
+        )
 
     def test_sorted_check(self):
         """Check it sorts the results in order"""
         checker = kconfig_check.KconfigCheck()
         self.assertSequenceEqual(
-            ['ANOTHER_NEW_ONE', 'NEW_ONE'],
+            ["ANOTHER_NEW_ONE", "NEW_ONE"],
             checker.find_new_adhoc(
-                configs=['NEW_ONE', 'ANOTHER_NEW_ONE', 'OLD_ONE', 'IN_KCONFIG'],
-                kconfigs=['IN_KCONFIG'],
-                allowed=['OLD_ONE']))
+                configs=["NEW_ONE", "ANOTHER_NEW_ONE", "OLD_ONE", "IN_KCONFIG"],
+                kconfigs=["IN_KCONFIG"],
+                allowed=["OLD_ONE"],
+            ),
+        )
 
     def check_read_configs(self, use_defines):
+        """Check that kconfigs can be read."""
         checker = kconfig_check.KconfigCheck()
         with tempfile.NamedTemporaryFile() as configs:
-            with open(configs.name, 'w') as out:
-                prefix = '#define ' if use_defines else ''
-                suffix = ' ' if use_defines else '='
-                out.write(f'''{prefix}CONFIG_OLD_ONE{suffix}y
+            with open(configs.name, "w") as out:
+                prefix = "#define " if use_defines else ""
+                suffix = " " if use_defines else "="
+                out.write(
+                    f"""{prefix}CONFIG_OLD_ONE{suffix}y
 {prefix}NOT_A_CONFIG{suffix}
 {prefix}CONFIG_STRING{suffix}"something"
 {prefix}CONFIG_INT{suffix}123
 {prefix}CONFIG_HEX{suffix}45ab
-''')
-            self.assertEqual(['OLD_ONE', 'STRING', 'INT', 'HEX'],
-                             checker.read_configs(configs.name, use_defines))
+"""
+                )
+            self.assertEqual(
+                ["OLD_ONE", "STRING", "INT", "HEX"],
+                checker.read_configs(configs.name, use_defines),
+            )
 
     def test_read_configs(self):
         """Test KconfigCheck.read_configs()"""
@@ -87,22 +100,24 @@ class KconfigCheck(unittest.TestCase):
         Args:
             srctree: Directory to write to
         """
-        with open(os.path.join(srctree, 'Kconfig'), 'w') as out:
-            out.write(f'''config {PREFIX}MY_KCONFIG
+        with open(os.path.join(srctree, "Kconfig"), "w") as out:
+            out.write(
+                f"""config {PREFIX}MY_KCONFIG
 \tbool "my kconfig"
 
 rsource "subdir/Kconfig.wibble"
-''')
-        subdir = os.path.join(srctree, 'subdir')
+"""
+            )
+        subdir = os.path.join(srctree, "subdir")
         os.mkdir(subdir)
-        with open(os.path.join(subdir, 'Kconfig.wibble'), 'w') as out:
-            out.write('menuconfig %sMENU_KCONFIG\n' % PREFIX)
+        with open(os.path.join(subdir, "Kconfig.wibble"), "w") as out:
+            out.write("menuconfig %sMENU_KCONFIG\n" % PREFIX)
 
         # Add a directory which should be ignored
-        bad_subdir = os.path.join(subdir, 'Kconfig')
+        bad_subdir = os.path.join(subdir, "Kconfig")
         os.mkdir(bad_subdir)
-        with open(os.path.join(bad_subdir, 'Kconfig.bad'), 'w') as out:
-            out.write('menuconfig %sBAD_KCONFIG' % PREFIX)
+        with open(os.path.join(bad_subdir, "Kconfig.bad"), "w") as out:
+            out.write("menuconfig %sBAD_KCONFIG" % PREFIX)
 
     def test_find_kconfigs(self):
         """Test KconfigCheck.find_kconfigs()"""
@@ -110,20 +125,23 @@ rsource "subdir/Kconfig.wibble"
         with tempfile.TemporaryDirectory() as srctree:
             self.setup_srctree(srctree)
             files = checker.find_kconfigs(srctree)
-            fnames = [fname[len(srctree):] for fname in files]
-            self.assertEqual(['/Kconfig', '/subdir/Kconfig.wibble'], fnames)
+            fnames = [fname[len(srctree) :] for fname in files]
+            self.assertEqual(["/Kconfig", "/subdir/Kconfig.wibble"], fnames)
 
     def test_scan_kconfigs(self):
         """Test KconfigCheck.scan_configs()"""
         checker = kconfig_check.KconfigCheck()
         with tempfile.TemporaryDirectory() as srctree:
             self.setup_srctree(srctree)
-            self.assertEqual(['MENU_KCONFIG', 'MY_KCONFIG'],
-                             checker.scan_kconfigs(srctree, PREFIX))
+            self.assertEqual(
+                ["MENU_KCONFIG", "MY_KCONFIG"],
+                checker.scan_kconfigs(srctree, PREFIX),
+            )
 
     @classmethod
-    def setup_allowed_and_configs(cls, allowed_fname, configs_fname,
-                                  add_new_one=True):
+    def setup_allowed_and_configs(
+        cls, allowed_fname, configs_fname, add_new_one=True
+    ):
         """Set up the 'allowed' and 'configs' files for tests
 
         Args:
@@ -131,14 +149,14 @@ rsource "subdir/Kconfig.wibble"
             configs_fname: Filename to which CONFIGs to check should be written
             add_new_one: True to add CONFIG_NEW_ONE to the configs_fname file
         """
-        with open(allowed_fname, 'w') as out:
-            out.write('CONFIG_OLD_ONE\n')
-            out.write('CONFIG_MENU_KCONFIG\n')
-        with open(configs_fname, 'w') as out:
-            to_add = ['CONFIG_OLD_ONE', 'CONFIG_MY_KCONFIG']
+        with open(allowed_fname, "w") as out:
+            out.write("CONFIG_OLD_ONE\n")
+            out.write("CONFIG_MENU_KCONFIG\n")
+        with open(configs_fname, "w") as out:
+            to_add = ["CONFIG_OLD_ONE", "CONFIG_MY_KCONFIG"]
             if add_new_one:
-                to_add.append('CONFIG_NEW_ONE')
-            out.write('\n'.join(to_add))
+                to_add.append("CONFIG_NEW_ONE")
+            out.write("\n".join(to_add))
 
     def test_check_adhoc_configs(self):
         """Test KconfigCheck.check_adhoc_configs()"""
@@ -148,12 +166,16 @@ rsource "subdir/Kconfig.wibble"
             with tempfile.NamedTemporaryFile() as allowed:
                 with tempfile.NamedTemporaryFile() as configs:
                     self.setup_allowed_and_configs(allowed.name, configs.name)
-                    new_adhoc, unneeded_adhoc, updated_adhoc = (
-                        checker.check_adhoc_configs(
-                            configs.name, srctree, allowed.name, PREFIX))
-                    self.assertEqual(['NEW_ONE'], new_adhoc)
-                    self.assertEqual(['MENU_KCONFIG'], unneeded_adhoc)
-                    self.assertEqual(['OLD_ONE'], updated_adhoc)
+                    (
+                        new_adhoc,
+                        unneeded_adhoc,
+                        updated_adhoc,
+                    ) = checker.check_adhoc_configs(
+                        configs.name, srctree, allowed.name, PREFIX
+                    )
+                    self.assertEqual(["NEW_ONE"], new_adhoc)
+                    self.assertEqual(["MENU_KCONFIG"], unneeded_adhoc)
+                    self.assertEqual(["OLD_ONE"], updated_adhoc)
 
     def test_check(self):
         """Test running the 'check' subcommand"""
@@ -162,45 +184,57 @@ rsource "subdir/Kconfig.wibble"
                 self.setup_srctree(srctree)
                 with tempfile.NamedTemporaryFile() as allowed:
                     with tempfile.NamedTemporaryFile() as configs:
-                        self.setup_allowed_and_configs(allowed.name,
-                                                       configs.name)
+                        self.setup_allowed_and_configs(
+                            allowed.name, configs.name
+                        )
                         ret_code = kconfig_check.main(
-                            ['-c', configs.name, '-s', srctree,
-                             '-a', allowed.name, '-p', PREFIX, 'check'])
+                            [
+                                "-c",
+                                configs.name,
+                                "-s",
+                                srctree,
+                                "-a",
+                                allowed.name,
+                                "-p",
+                                PREFIX,
+                                "check",
+                            ]
+                        )
                         self.assertEqual(1, ret_code)
-        self.assertEqual('', stdout.getvalue())
-        found = re.findall('(CONFIG_.*)', stderr.getvalue())
-        self.assertEqual(['CONFIG_NEW_ONE'], found)
+        self.assertEqual("", stdout.getvalue())
+        found = re.findall("(CONFIG_.*)", stderr.getvalue())
+        self.assertEqual(["CONFIG_NEW_ONE"], found)
 
     def test_real_kconfig(self):
         """Same Kconfig should be returned for kconfiglib / adhoc"""
         if not kconfig_check.USE_KCONFIGLIB:
-            self.skipTest('No kconfiglib available')
-        zephyr_path = pathlib.Path('../../third_party/zephyr/main').resolve()
+            self.fail("No kconfiglib available")
+        zephyr_path = pathlib.Path(
+            "../../../src/third_party/zephyr/main"
+        ).resolve()
         if not zephyr_path.exists():
-            self.skipTest('No zephyr tree available')
+            self.fail("No zephyr tree available")
+        os.environ["ZEPHYR_BASE"] = str(zephyr_path)
 
         checker = kconfig_check.KconfigCheck()
-        srcdir = 'zephyr'
+        srcdir = "zephyr"
         search_paths = [zephyr_path]
         kc_version = checker.scan_kconfigs(
-            srcdir, search_paths=search_paths, try_kconfiglib=True)
+            srcdir, search_paths=search_paths, try_kconfiglib=True
+        )
         adhoc_version = checker.scan_kconfigs(srcdir, try_kconfiglib=False)
 
         # List of things missing from the Kconfig
         missing = sorted(list(set(adhoc_version) - set(kc_version)))
 
-        # The Kconfig is disjoint in some places, e.g. the boards have their
-        # own Kconfig files which are not included from the main Kconfig
-        missing = [item for item in missing
-                   if not item.startswith('BOARD') and
-                   not item.startswith('VARIANT')]
-
-        # Similarly, some other items are defined in files that are not included
+        # Some items are defined in files that are not included
         # in all cases, only for particular values of $(ARCH)
         self.assertEqual(
-            ['FLASH_LOAD_OFFSET', 'NPCX_HEADER', 'SYS_CLOCK_HW_CYCLES_PER_SEC'],
-            missing)
+            [
+                "TRAP_UNALIGNED_ACCESS",
+            ],
+            missing,
+        )
 
     def test_check_unneeded(self):
         """Test running the 'check' subcommand with unneeded ad-hoc configs"""
@@ -209,18 +243,29 @@ rsource "subdir/Kconfig.wibble"
                 self.setup_srctree(srctree)
                 with tempfile.NamedTemporaryFile() as allowed:
                     with tempfile.NamedTemporaryFile() as configs:
-                        self.setup_allowed_and_configs(allowed.name,
-                                                       configs.name, False)
+                        self.setup_allowed_and_configs(
+                            allowed.name, configs.name, False
+                        )
                         ret_code = kconfig_check.main(
-                            ['-c', configs.name, '-s', srctree,
-                             '-a', allowed.name, '-p', PREFIX, 'check'])
+                            [
+                                "-c",
+                                configs.name,
+                                "-s",
+                                srctree,
+                                "-a",
+                                allowed.name,
+                                "-p",
+                                PREFIX,
+                                "check",
+                            ]
+                        )
                         self.assertEqual(1, ret_code)
-        self.assertEqual('', stderr.getvalue())
-        found = re.findall('(CONFIG_.*)', stdout.getvalue())
-        self.assertEqual(['CONFIG_MENU_KCONFIG'], found)
+        self.assertEqual("", stderr.getvalue())
+        found = re.findall("(CONFIG_.*)", stdout.getvalue())
+        self.assertEqual(["CONFIG_MENU_KCONFIG"], found)
         allowed = kconfig_check.NEW_ALLOWED_FNAME.read_text().splitlines()
-        self.assertEqual(['CONFIG_OLD_ONE'], allowed)
+        self.assertEqual(["CONFIG_OLD_ONE"], allowed)
 
 
-if __name__ == '__main__':
+if __name__ == "__main__":
     unittest.main()
diff --git a/util/twister_launcher.py b/util/twister_launcher.py
new file mode 100755
index 0000000000..d98768fed5
--- /dev/null
+++ b/util/twister_launcher.py
@@ -0,0 +1,317 @@
+#!/usr/bin/env vpython3
+
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""
+This script is a wrapper for invoking Twister, the Zephyr test runner, using
+default parameters for the ChromiumOS EC project. For an overview of CLI
+parameters that may be used, please consult the Twister documentation.
+"""
+
+# [VPYTHON:BEGIN]
+# python_version: "3.8"
+# wheel: <
+#   name: "infra/python/wheels/anytree-py2_py3"
+#   version: "version:2.8.0"
+# >
+# wheel: <
+#   name: "infra/python/wheels/colorama-py3"
+#   version: "version:0.4.1"
+# >
+# wheel: <
+#   name: "infra/python/wheels/docopt-py2_py3"
+#   version: "version:0.6.2"
+# >
+# wheel: <
+#   name: "infra/python/wheels/ply-py2_py3"
+#   version: "version:3.11"
+# >
+# wheel: <
+#   name: "infra/python/wheels/psutil/${vpython_platform}"
+#   version: "version:5.8.0.chromium.3"
+# >
+# wheel: <
+#   name: "infra/python/wheels/pykwalify-py2_py3"
+#   version: "version:1.8.0"
+# >
+# wheel: <
+#   name: "infra/python/wheels/pyserial-py2_py3"
+#   version: "version:3.4"
+# >
+# wheel: <
+#   name: "infra/python/wheels/python-dateutil-py2_py3"
+#   version: "version:2.8.1"
+# >
+# wheel: <
+#   name: "infra/python/wheels/pyyaml-py3"
+#   version: "version:5.3.1"
+# >
+# wheel: <
+#   name: "infra/python/wheels/ruamel_yaml_clib/${vpython_platform}"
+#   version: "version:0.2.6"
+# >
+# wheel: <
+#   name: "infra/python/wheels/ruamel_yaml-py3"
+#   version: "version:0.17.16"
+# >
+# wheel: <
+#   name: "infra/python/wheels/six-py2_py3"
+#   version: "version:1.16.0"
+# >
+# [VPYTHON:END]
+
+import argparse
+import os
+import re
+import shlex
+import subprocess
+import sys
+import time
+from pathlib import Path
+from shutil import which
+
+
+def find_checkout() -> Path:
+    """Find the location of the source checkout or return None."""
+    cros_checkout = os.environ.get("CROS_WORKON_SRCROOT")
+    if cros_checkout is not None:
+        return Path(cros_checkout)
+
+    # Attempt to locate checkout location relatively if being run outside of chroot.
+    try:
+        cros_checkout = Path(__file__).resolve().parents[4]
+        assert (cros_checkout / "src").exists()
+        return cros_checkout
+    except (IndexError, AssertionError):
+        # Not in the chroot or matching directory structure
+        return None
+
+
+def find_paths():
+    """Find EC base, Zephyr base, and Zephyr modules paths and return as a 3-tuple."""
+
+    # Determine where the source tree is checked out. Will be None if operating outside
+    # of the chroot (e.g. Gitlab builds). In this case, additional paths need to be
+    # passed in through environment variables.
+    cros_checkout = find_checkout()
+
+    if cros_checkout:
+        ec_base = cros_checkout / "src" / "platform" / "ec"
+        zephyr_base = cros_checkout / "src" / "third_party" / "zephyr" / "main"
+        zephyr_modules_dir = cros_checkout / "src" / "third_party" / "zephyr"
+    else:
+        try:
+            ec_base = Path(os.environ["EC_DIR"]).resolve()
+        except KeyError as err:
+            raise RuntimeError(
+                "EC_DIR unspecified. Please pass as env var or use chroot."
+            ) from err
+
+        try:
+            zephyr_base = Path(os.environ["ZEPHYR_BASE"]).resolve()
+        except KeyError as err:
+            raise RuntimeError(
+                "ZEPHYR_BASE unspecified. Please pass as env var or use chroot."
+            ) from err
+
+        try:
+            zephyr_modules_dir = Path(os.environ["MODULES_DIR"]).resolve()
+        except KeyError as err:
+            raise RuntimeError(
+                "MODULES_DIR unspecified. Please pass as env var or use chroot."
+            ) from err
+
+    return (ec_base, zephyr_base, zephyr_modules_dir)
+
+
+def find_modules(mod_dir: Path) -> list:
+    """Find Zephyr modules in the given directory `dir`."""
+
+    modules = []
+    for child in mod_dir.iterdir():
+        if child.is_dir() and (child / "zephyr" / "module.yml").exists():
+            modules.append(child.resolve())
+    return modules
+
+
+def is_tool(name):
+    """Check if 'name' is on PATH and marked executable."""
+    return which(name) is not None
+
+
+def is_rdb_login():
+    """Checks if user is logged into rdb"""
+    cmd = ["rdb", "auth-info"]
+    ret = subprocess.run(cmd, capture_output=True, text=True, check=False)
+
+    if ret.returncode == 0:
+        print("\nrdb auth-info: " + ret.stdout.split("\n")[0])
+    else:
+        print("\nrdb auth-info: " + ret.stderr)
+
+    return ret.returncode == 0
+
+
+def upload_results(ec_base):
+    """Uploads Zephyr Test results to ResultDB"""
+    flag = False
+
+    if is_rdb_login():
+        json_path = ec_base / "twister-out" / "twister.json"
+        cmd = [
+            "rdb",
+            "stream",
+            "-new",
+            "-realm",
+            "chromium:public",
+            "--",
+            str(ec_base / "util/zephyr_to_resultdb.py"),
+            "--result=" + str(json_path),
+            "--upload=True",
+        ]
+
+        start_time = time.time()
+        ret = subprocess.run(cmd, capture_output=True, text=True, check=True)
+        end_time = time.time()
+
+        # Extract URL to test report from captured output
+        rdb_url = re.search(
+            r"(?P<url>https?://[^\s]+)", ret.stderr.split("\n")[0]
+        ).group("url")
+        print(f"\nTEST RESULTS ({end_time - start_time:.3f}s): {rdb_url}\n")
+        flag = ret.returncode == 0
+    else:
+        print("Unable to upload test results, please run 'rdb auth-login'\n")
+
+    return flag
+
+
+def main():
+    """Run Twister using defaults for the EC project."""
+
+    # Get paths for the build.
+    ec_base, zephyr_base, zephyr_modules_dir = find_paths()
+
+    zephyr_modules = find_modules(zephyr_modules_dir)
+
+    # Add the EC dir as a module if not already included (resolve all paths to
+    # account for symlinked or relative paths)
+    if ec_base.resolve() not in zephyr_modules:
+        zephyr_modules.append(ec_base)
+
+    # Prepare environment variables for export to Twister. Inherit the parent
+    # process's environment, but set some default values if not already set.
+    twister_env = dict(os.environ)
+    is_in_chroot = Path("/etc/cros_chroot_version").is_file()
+    extra_env_vars = {
+        "TOOLCHAIN_ROOT": os.environ.get(
+            "TOOLCHAIN_ROOT",
+            str(ec_base / "zephyr") if is_in_chroot else zephyr_base,
+        ),
+        "ZEPHYR_TOOLCHAIN_VARIANT": os.environ.get(
+            "ZEPHYR_TOOLCHAIN_VARIANT", "llvm" if is_in_chroot else "host"
+        ),
+    }
+    twister_env.update(extra_env_vars)
+
+    # Twister CLI args
+    # TODO(b/239165779): Reduce or remove the usage of label properties
+    # Zephyr upstream has deprecated the label property. We need to allow
+    # warnings during twister runs until all the label properties are removed
+    # from all board and test overlays.
+    twister_cli = [
+        sys.executable,
+        str(zephyr_base / "scripts" / "twister"),  # Executable path
+        "--ninja",
+        "--disable-warnings-as-errors",
+        f"-x=DTS_ROOT={str( ec_base / 'zephyr')}",
+        f"-x=SYSCALL_INCLUDE_DIRS={str(ec_base / 'zephyr' / 'include' / 'drivers')}",
+        f"-x=ZEPHYR_BASE={zephyr_base}",
+        f"-x=ZEPHYR_MODULES={';'.join([str(p) for p in zephyr_modules])}",
+    ]
+
+    # `-T` flags (used for specifying test directories to build and run)
+    # require special handling. When run without `-T` flags, Twister will
+    # search for tests in `zephyr_base`. This is undesirable and we want
+    # Twister to look in the EC tree by default, instead. Use argparse to
+    # intercept `-T` flags and pass in a new default if none are found. If
+    # user does pass their own `-T` flags, pass them through instead. Do the
+    # same with verbosity. Other arguments get passed straight through,
+    # including -h/--help so that Twister's own help text gets displayed.
+    parser = argparse.ArgumentParser(add_help=False, allow_abbrev=False)
+    parser.add_argument("-T", "--testsuite-root", action="append")
+    parser.add_argument("-p", "--platform", action="append")
+    parser.add_argument("-v", "--verbose", action="count", default=0)
+    parser.add_argument(
+        "--gcov-tool", default=str(ec_base / "util" / "llvm-gcov.sh")
+    )
+    parser.add_argument(
+        "--no-upload-cros-rdb", dest="upload_cros_rdb", action="store_false"
+    )
+
+    intercepted_args, other_args = parser.parse_known_args()
+
+    for _ in range(intercepted_args.verbose):
+        # Pass verbosity setting through to twister
+        twister_cli.append("-v")
+
+    if intercepted_args.testsuite_root:
+        # Pass user-provided -T args when present.
+        for arg in intercepted_args.testsuite_root:
+            twister_cli.extend(["-T", arg])
+    else:
+        # Use EC base dir when no -T args specified. This will cause all
+        # Twister-compatible EC tests to run.
+        twister_cli.extend(["-T", str(ec_base)])
+        twister_cli.extend(["-T", str(zephyr_base / "tests/subsys/shell")])
+
+    # Pass through the chosen coverage tool, or fall back on the default choice
+    # (see add_argument above).
+    twister_cli.extend(
+        [
+            "--gcov-tool",
+            intercepted_args.gcov_tool,
+        ]
+    )
+    if intercepted_args.platform:
+        # Pass user-provided -p args when present.
+        for arg in intercepted_args.platform:
+            twister_cli.extend(["-p", arg])
+    else:
+        # posix_native and unit_testing when nothing was requested by user.
+        twister_cli.extend(["-p", "native_posix"])
+        twister_cli.extend(["-p", "unit_testing"])
+
+    # Append additional user-supplied args
+    twister_cli.extend(other_args)
+
+    # Print exact CLI args and environment variables depending on verbosity.
+    if intercepted_args.verbose > 0:
+        print("Calling:", " ".join(shlex.quote(str(x)) for x in twister_cli))
+        print(
+            "With environment overrides:",
+            " ".join(
+                f"{name}={shlex.quote(val)}"
+                for name, val in extra_env_vars.items()
+            ),
+        )
+        sys.stdout.flush()
+
+    # Invoke Twister and wait for it to exit.
+    result = subprocess.run(twister_cli, env=twister_env, check=False)
+
+    if result.returncode == 0:
+        print("TEST EXECUTION SUCCESSFUL")
+    else:
+        print("TEST EXECUTION FAILED")
+
+    if is_tool("rdb") and intercepted_args.upload_cros_rdb:
+        upload_results(ec_base)
+
+    sys.exit(result.returncode)
+
+
+if __name__ == "__main__":
+    main()
diff --git a/util/uart_stress_tester.py b/util/uart_stress_tester.py
index b3db60060e..d7b2341e93 100755
--- a/util/uart_stress_tester.py
+++ b/util/uart_stress_tester.py
@@ -1,12 +1,8 @@
 #!/usr/bin/env python3
 # -*- coding: utf-8 -*-
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Copyright 2019 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
 
 """ChromeOS Uart Stress Test
 
@@ -21,9 +17,7 @@ Prerequisite:
         e.g. dut-control cr50_uart_timestamp:off
 """
 
-from __future__ import absolute_import
-from __future__ import division
-from __future__ import print_function
+from __future__ import absolute_import, division, print_function
 
 import argparse
 import atexit
@@ -34,474 +28,518 @@ import sys
 import threading
 import time
 
-import serial
+import serial  # pylint:disable=import-error
 
-BAUDRATE = 115200                # Default baudrate setting for UART port
-CROS_USERNAME = 'root'           # Account name to login to ChromeOS
-CROS_PASSWORD = 'test0000'       # Password to login to ChromeOS
-CHARGEN_TXT = '0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz'
-                                 # The result of 'chargen 62 62'
+BAUDRATE = 115200  # Default baudrate setting for UART port
+CROS_USERNAME = "root"  # Account name to login to ChromeOS
+CROS_PASSWORD = "test0000"  # Password to login to ChromeOS
+CHARGEN_TXT = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz"
+# The result of 'chargen 62 62'
 CHARGEN_TXT_LEN = len(CHARGEN_TXT)
-CR = '\r'                        # Carriage Return
-LF = '\n'                        # Line Feed
+CR = "\r"  # Carriage Return
+LF = "\n"  # Line Feed
 CRLF = CR + LF
-FLAG_FILENAME = '/tmp/chargen_testing'
-TPM_CMD = ('trunks_client --key_create --rsa=2048 --usage=sign'
-           ' --key_blob=/tmp/blob &> /dev/null')
-                                 # A ChromeOS TPM command for the cr50 stress
-                                 # purpose.
-CR50_LOAD_GEN_CMD = ('while [[ -f %s ]]; do   %s; done &'
-                     % (FLAG_FILENAME, TPM_CMD))
-                                 # A command line to run TPM_CMD in background
-                                 # infinitely.
+FLAG_FILENAME = "/tmp/chargen_testing"
+TPM_CMD = (
+    "trunks_client --key_create --rsa=2048 --usage=sign"
+    " --key_blob=/tmp/blob &> /dev/null"
+)
+# A ChromeOS TPM command for the cr50 stress
+# purpose.
+CR50_LOAD_GEN_CMD = "while [[ -f %s ]]; do   %s; done &" % (
+    FLAG_FILENAME,
+    TPM_CMD,
+)
+# A command line to run TPM_CMD in background
+# infinitely.
 
 
 class ChargenTestError(Exception):
-  """Exception for Uart Stress Test Error"""
-  pass
+    """Exception for Uart Stress Test Error"""
 
+    pass
 
-class UartSerial(object):
-  """Test Object for a single UART serial device
-
-  Attributes:
-    UART_DEV_PROFILES
-    char_loss_occurrences: Number that character loss happens
-    cleanup_cli: Command list to perform before the test exits
-    cr50_workload: True if cr50 should be stressed, or False otherwise
-    usb_output: True if output should be generated to USB channel
-    dev_prof: Dictionary of device profile
-    duration: Time to keep chargen running
-    eol: Characters to add at the end of input
-    logger: object that store the log
-    num_ch_exp: Expected number of characters in output
-    num_ch_cap: Number of captured characters in output
-    test_cli: Command list to run for chargen test
-    test_thread: Thread object that captures the UART output
-    serial: serial.Serial object
-  """
-  UART_DEV_PROFILES = (
-      # Kernel
-      {
-          'prompt':'localhost login:',
-          'device_type':'AP',
-          'prepare_cmd':[
-              CROS_USERNAME,             # Login
-              CROS_PASSWORD,             # Password
-              'dmesg -D',                # Disable console message
-              'touch ' + FLAG_FILENAME,  # Create a temp file
-          ],
-          'cleanup_cmd':[
-              'rm -f ' + FLAG_FILENAME,  # Remove the temp file
-              'dmesg -E',                # Enable console message
-              'logout',                  # Logout
-          ],
-          'end_of_input':LF,
-      },
-      # EC
-      {
-          'prompt':'> ',
-          'device_type':'EC',
-          'prepare_cmd':[
-              'chan save',
-              'chan 0'                   # Disable console message
-          ],
-          'cleanup_cmd':['', 'chan restore'],
-          'end_of_input':CRLF,
-      },
-  )
-
-  def __init__(self, port, duration, timeout=1,
-               baudrate=BAUDRATE, cr50_workload=False,
-               usb_output=False):
-    """Initialize UartSerial
-
-    Args:
-      port: UART device path. e.g. /dev/ttyUSB0
-      duration: Time to test, in seconds
-      timeout: Read timeout value.
-      baudrate: Baud rate such as 9600 or 115200.
-      cr50_workload: True if a workload should be generated on cr50
-      usb_output: True if a workload should be generated to USB channel
-    """
-
-    # Initialize serial object
-    self.serial = serial.Serial()
-    self.serial.port = port
-    self.serial.timeout = timeout
-    self.serial.baudrate = baudrate
-
-    self.duration = duration
-    self.cr50_workload = cr50_workload
-    self.usb_output = usb_output
-
-    self.logger = logging.getLogger(type(self).__name__ + '| ' + port)
-    self.test_thread = threading.Thread(target=self.stress_test_thread)
 
-    self.dev_prof = {}
-    self.cleanup_cli = []
-    self.test_cli = []
-    self.eol = CRLF
-    self.num_ch_exp = 0
-    self.num_ch_cap = 0
-    self.char_loss_occurrences = 0
-    atexit.register(self.cleanup)
-
-  def run_command(self, command_lines, delay=0):
-    """Run command(s) at UART prompt
-
-    Args:
-      command_lines: list of commands to run.
-      delay: delay after a command in second
+class UartSerial(object):
+    """Test Object for a single UART serial device
+
+    Attributes:
+      UART_DEV_PROFILES
+      char_loss_occurrences: Number that character loss happens
+      cleanup_cli: Command list to perform before the test exits
+      cr50_workload: True if cr50 should be stressed, or False otherwise
+      usb_output: True if output should be generated to USB channel
+      dev_prof: Dictionary of device profile
+      duration: Time to keep chargen running
+      eol: Characters to add at the end of input
+      logger: object that store the log
+      num_ch_exp: Expected number of characters in output
+      num_ch_cap: Number of captured characters in output
+      test_cli: Command list to run for chargen test
+      test_thread: Thread object that captures the UART output
+      serial: serial.Serial object
     """
-    for cli in command_lines:
-      self.logger.debug('run %r', cli)
-
-      self.serial.write((cli + self.eol).encode())
-      self.serial.flush()
-      if delay:
-        time.sleep(delay)
-
-  def cleanup(self):
-    """Before termination, clean up the UART device."""
-    self.logger.debug('Closing...')
-
-    self.serial.open()
-    self.run_command(self.cleanup_cli)          # Run cleanup commands
-    self.serial.close()
 
-    self.logger.debug('Cleanup done')
+    UART_DEV_PROFILES = (
+        # Kernel
+        {
+            "prompt": "localhost login:",
+            "device_type": "AP",
+            "prepare_cmd": [
+                CROS_USERNAME,  # Login
+                CROS_PASSWORD,  # Password
+                "dmesg -D",  # Disable console message
+                "touch " + FLAG_FILENAME,  # Create a temp file
+            ],
+            "cleanup_cmd": [
+                "rm -f " + FLAG_FILENAME,  # Remove the temp file
+                "dmesg -E",  # Enable console message
+                "logout",  # Logout
+            ],
+            "end_of_input": LF,
+        },
+        # EC
+        {
+            "prompt": "> ",
+            "device_type": "EC",
+            "prepare_cmd": ["chan save", "chan 0"],  # Disable console message
+            "cleanup_cmd": ["", "chan restore"],
+            "end_of_input": CRLF,
+        },
+    )
+
+    def __init__(
+        self,
+        port,
+        duration,
+        timeout=1,
+        baudrate=BAUDRATE,
+        cr50_workload=False,
+        usb_output=False,
+    ):
+        """Initialize UartSerial
+
+        Args:
+          port: UART device path. e.g. /dev/ttyUSB0
+          duration: Time to test, in seconds
+          timeout: Read timeout value.
+          baudrate: Baud rate such as 9600 or 115200.
+          cr50_workload: True if a workload should be generated on cr50
+          usb_output: True if a workload should be generated to USB channel
+        """
+
+        # Initialize serial object
+        self.serial = serial.Serial()
+        self.serial.port = port
+        self.serial.timeout = timeout
+        self.serial.baudrate = baudrate
+
+        self.duration = duration
+        self.cr50_workload = cr50_workload
+        self.usb_output = usb_output
+
+        self.logger = logging.getLogger(type(self).__name__ + "| " + port)
+        self.test_thread = threading.Thread(target=self.stress_test_thread)
+
+        self.dev_prof = {}
+        self.cleanup_cli = []
+        self.test_cli = []
+        self.eol = CRLF
+        self.num_ch_exp = 0
+        self.num_ch_cap = 0
+        self.char_loss_occurrences = 0
+        atexit.register(self.cleanup)
+
+    def run_command(self, command_lines, delay=0):
+        """Run command(s) at UART prompt
+
+        Args:
+          command_lines: list of commands to run.
+          delay: delay after a command in second
+        """
+        for cli in command_lines:
+            self.logger.debug("run %r", cli)
+
+            self.serial.write((cli + self.eol).encode())
+            self.serial.flush()
+            if delay:
+                time.sleep(delay)
+
+    def cleanup(self):
+        """Before termination, clean up the UART device."""
+        self.logger.debug("Closing...")
+
+        self.serial.open()
+        self.run_command(self.cleanup_cli)  # Run cleanup commands
+        self.serial.close()
+
+        self.logger.debug("Cleanup done")
+
+    def get_output(self):
+        """Capture the UART output
+
+        Args:
+          stop_char: Read output buffer until it reads stop_char.
+
+        Returns:
+          text from UART output.
+        """
+        if self.serial.inWaiting() == 0:
+            time.sleep(1)
+
+        return self.serial.read(self.serial.inWaiting()).decode()
+
+    def prepare(self):
+        """Prepare the test:
+
+        Identify the type of UART device (EC or Kernel?), then
+        decide what kind of commands to use to generate stress loads.
+
+        Raises:
+          ChargenTestError if UART source can't be identified.
+        """
+        try:
+            self.logger.info("Preparing...")
+
+            self.serial.open()
+
+            # Prepare the device for test
+            self.serial.flushInput()
+            self.serial.flushOutput()
+
+            self.get_output()  # drain data
+
+            # Give a couple of line feeds, and capture the prompt text
+            self.run_command(["", ""])
+            prompt_txt = self.get_output()
+
+            # Detect the device source: EC or AP?
+            # Detect if the device is AP or EC console based on the captured.
+            for dev_prof in self.UART_DEV_PROFILES:
+                if dev_prof["prompt"] in prompt_txt:
+                    self.dev_prof = dev_prof
+                    break
+            else:
+                # No prompt patterns were found. UART seems not responding or in
+                # an undesirable status.
+                if prompt_txt:
+                    raise ChargenTestError(
+                        "%s: Got an unknown prompt text: %s\n"
+                        "Check manually whether %s is available."
+                        % (self.serial.port, prompt_txt, self.serial.port)
+                    )
+                else:
+                    raise ChargenTestError(
+                        "%s: Got no input. Close any other connections"
+                        " to this port, and try it again." % self.serial.port
+                    )
+
+            self.logger.info(
+                "Detected as %s UART", self.dev_prof["device_type"]
+            )
+            # Log displays the UART type (AP|EC) instead of device filename.
+            self.logger = logging.getLogger(
+                type(self).__name__ + "| " + self.dev_prof["device_type"]
+            )
+
+            # Either login to AP or run some commands to prepare the device
+            # for test
+            self.eol = self.dev_prof["end_of_input"]
+            self.run_command(self.dev_prof["prepare_cmd"], delay=2)
+            self.cleanup_cli += self.dev_prof["cleanup_cmd"]
+
+            # 'chargen' of AP does not have option for USB output.
+            # Force it work on UART.
+            if self.dev_prof["device_type"] == "AP":
+                self.usb_output = False
+
+            # Check whether the command 'chargen' is available in the device.
+            # 'chargen 1 4' is supposed to print '0000'
+            self.get_output()  # drain data
+
+            chargen_cmd = "chargen 1 4"
+            if self.usb_output:
+                chargen_cmd += " usb"
+            self.run_command([chargen_cmd])
+            tmp_txt = self.get_output()
+
+            # Check whether chargen command is available.
+            if "0000" not in tmp_txt:
+                raise ChargenTestError(
+                    "%s: Chargen got an unexpected result: %s"
+                    % (self.dev_prof["device_type"], tmp_txt)
+                )
+
+            self.num_ch_exp = int(self.serial.baudrate * self.duration / 10)
+            chargen_cmd = (
+                "chargen " + str(CHARGEN_TXT_LEN) + " " + str(self.num_ch_exp)
+            )
+            if self.usb_output:
+                chargen_cmd += " usb"
+            self.test_cli = [chargen_cmd]
+
+            self.logger.info("Ready to test")
+        finally:
+            self.serial.close()
+
+    def stress_test_thread(self):
+        """Test thread
+
+        Raises:
+          ChargenTestError: if broken character is found.
+        """
+        try:
+            self.serial.open()
+            self.serial.flushInput()
+            self.serial.flushOutput()
+
+            # Run TPM command in background to burden cr50.
+            if self.dev_prof["device_type"] == "AP" and self.cr50_workload:
+                self.run_command([CR50_LOAD_GEN_CMD])
+                self.logger.debug("run TPM job while %s exists", FLAG_FILENAME)
+
+            # Run the command 'chargen', one time
+            self.run_command([""])  # Give a line feed
+            self.get_output()  # Drain the output
+            self.run_command(self.test_cli)
+            self.serial.readline()  # Drain the echoed command line.
+
+            err_msg = "%s: Expected %r but got %s after %d char received"
+
+            # Keep capturing the output until the test timer is expired.
+            self.num_ch_cap = 0
+            self.char_loss_occurrences = 0
+            data_starve_count = 0
+
+            total_num_ch = (
+                self.num_ch_exp
+            )  # Expected number of characters in total
+            ch_exp = CHARGEN_TXT[0]
+            ch_cap = (
+                "z"  # any character value is ok for loop initial condition.
+            )
+            while self.num_ch_cap < total_num_ch:
+                captured = self.get_output()
+
+                if captured:
+                    # There is some output data. Reset the data starvation count.
+                    data_starve_count = 0
+                else:
+                    data_starve_count += 1
+                    if data_starve_count > 1:
+                        # If nothing was captured more than once, then terminate the test.
+                        self.logger.debug("No more output")
+                        break
+
+                for ch_cap in captured:
+                    if ch_cap not in CHARGEN_TXT:
+                        # If it is not alpha-numeric, terminate the test.
+                        if ch_cap not in CRLF:
+                            # If it is neither a CR nor LF, then it is an error case.
+                            self.logger.error(
+                                "Whole captured characters: %r", captured
+                            )
+                            raise ChargenTestError(
+                                err_msg
+                                % (
+                                    "Broken char captured",
+                                    ch_exp,
+                                    hex(ord(ch_cap)),
+                                    self.num_ch_cap,
+                                )
+                            )
+
+                        # Set the loop termination condition true.
+                        total_num_ch = self.num_ch_cap
+
+                    if self.num_ch_cap >= total_num_ch:
+                        break
+
+                    if ch_exp != ch_cap:
+                        # If it is alpha-numeric but not continuous, then some characters
+                        # are lost.
+                        self.logger.error(
+                            err_msg,
+                            "Char loss detected",
+                            ch_exp,
+                            repr(ch_cap),
+                            self.num_ch_cap,
+                        )
+                        self.char_loss_occurrences += 1
+
+                        # Recalculate the expected number of characters to adjust
+                        # termination condition. The loss might be bigger than this
+                        # adjustment, but it is okay since it will terminates by either
+                        # CR/LF detection or by data starvation.
+                        idx_ch_exp = CHARGEN_TXT.find(ch_exp)
+                        idx_ch_cap = CHARGEN_TXT.find(ch_cap)
+                        if idx_ch_cap < idx_ch_exp:
+                            idx_ch_cap += len(CHARGEN_TXT)
+                        total_num_ch -= idx_ch_cap - idx_ch_exp
+
+                    self.num_ch_cap += 1
+
+                    # Determine What character is expected next?
+                    ch_exp = CHARGEN_TXT[
+                        (CHARGEN_TXT.find(ch_cap) + 1) % CHARGEN_TXT_LEN
+                    ]
+
+        finally:
+            self.serial.close()
+
+    def start_test(self):
+        """Start the test thread"""
+        self.logger.info("Test thread starts")
+        self.test_thread.start()
+
+    def wait_test_done(self):
+        """Wait until the test thread get done and join"""
+        self.test_thread.join()
+        self.logger.info("Test thread is done")
+
+    def get_result(self):
+        """Display the result
+
+        Returns:
+          Integer = the number of lost character
+
+        Raises:
+          ChargenTestError: if the capture is corrupted.
+        """
+        # If more characters than expected are captured, it means some messages
+        # from other than chargen are mixed. Stop processing further.
+        if self.num_ch_exp < self.num_ch_cap:
+            raise ChargenTestError(
+                "%s: UART output is corrupted." % self.dev_prof["device_type"]
+            )
+
+        # Get the count difference between the expected to the captured
+        # as the number of lost character.
+        char_lost = self.num_ch_exp - self.num_ch_cap
+        self.logger.info(
+            "%8d char lost / %10d (%.1f %%)",
+            char_lost,
+            self.num_ch_exp,
+            char_lost * 100.0 / self.num_ch_exp,
+        )
+
+        return char_lost, self.num_ch_exp, self.char_loss_occurrences
 
-  def get_output(self):
-    """Capture the UART output
 
-    Args:
-      stop_char: Read output buffer until it reads stop_char.
+class ChargenTest(object):
+    """UART stress tester
 
-    Returns:
-      text from UART output.
+    Attributes:
+      logger: logging object
+      serials: Dictionary where key is filename of UART device, and the value is
+               UartSerial object
     """
-    if self.serial.inWaiting() == 0:
-      time.sleep(1)
-
-    return self.serial.read(self.serial.inWaiting()).decode()
 
-  def prepare(self):
-    """Prepare the test:
-
-    Identify the type of UART device (EC or Kernel?), then
-    decide what kind of commands to use to generate stress loads.
-
-    Raises:
-      ChargenTestError if UART source can't be identified.
-    """
-    try:
-      self.logger.info('Preparing...')
-
-      self.serial.open()
-
-      # Prepare the device for test
-      self.serial.flushInput()
-      self.serial.flushOutput()
-
-      self.get_output()      # drain data
-
-      # Give a couple of line feeds, and capture the prompt text
-      self.run_command(['', ''])
-      prompt_txt = self.get_output()
-
-      # Detect the device source: EC or AP?
-      # Detect if the device is AP or EC console based on the captured.
-      for dev_prof in self.UART_DEV_PROFILES:
-        if dev_prof['prompt'] in prompt_txt:
-          self.dev_prof = dev_prof
-          break
-      else:
-        # No prompt patterns were found. UART seems not responding or in
-        # an undesirable status.
-        if prompt_txt:
-          raise ChargenTestError('%s: Got an unknown prompt text: %s\n'
-                                 'Check manually whether %s is available.' %
-                                 (self.serial.port, prompt_txt,
-                                  self.serial.port))
-        else:
-          raise ChargenTestError('%s: Got no input. Close any other connections'
-                                 ' to this port, and try it again.' %
-                                 self.serial.port)
-
-      self.logger.info('Detected as %s UART', self.dev_prof['device_type'])
-      # Log displays the UART type (AP|EC) instead of device filename.
-      self.logger = logging.getLogger(type(self).__name__ + '| ' +
-                                      self.dev_prof['device_type'])
-
-      # Either login to AP or run some commands to prepare the device
-      # for test
-      self.eol = self.dev_prof['end_of_input']
-      self.run_command(self.dev_prof['prepare_cmd'], delay=2)
-      self.cleanup_cli += self.dev_prof['cleanup_cmd']
-
-      # 'chargen' of AP does not have option for USB output.
-      # Force it work on UART.
-      if self.dev_prof['device_type'] == 'AP':
-        self.usb_output = False
-
-      # Check whether the command 'chargen' is available in the device.
-      # 'chargen 1 4' is supposed to print '0000'
-      self.get_output()      # drain data
-
-      chargen_cmd = 'chargen 1 4'
-      if self.usb_output:
-        chargen_cmd += ' usb'
-      self.run_command([chargen_cmd])
-      tmp_txt = self.get_output()
-
-      # Check whether chargen command is available.
-      if '0000' not in tmp_txt:
-        raise ChargenTestError('%s: Chargen got an unexpected result: %s' %
-                               (self.dev_prof['device_type'], tmp_txt))
-
-      self.num_ch_exp = int(self.serial.baudrate * self.duration / 10)
-      chargen_cmd = 'chargen ' + str(CHARGEN_TXT_LEN) + ' ' + \
-                    str(self.num_ch_exp)
-      if self.usb_output:
-        chargen_cmd += ' usb'
-      self.test_cli = [chargen_cmd]
-
-      self.logger.info('Ready to test')
-    finally:
-      self.serial.close()
-
-  def stress_test_thread(self):
-    """Test thread
-
-    Raises:
-      ChargenTestError: if broken character is found.
-    """
-    try:
-      self.serial.open()
-      self.serial.flushInput()
-      self.serial.flushOutput()
-
-      # Run TPM command in background to burden cr50.
-      if self.dev_prof['device_type'] == 'AP' and self.cr50_workload:
-        self.run_command([CR50_LOAD_GEN_CMD])
-        self.logger.debug('run TPM job while %s exists', FLAG_FILENAME)
-
-      # Run the command 'chargen', one time
-      self.run_command([''])  # Give a line feed
-      self.get_output()    # Drain the output
-      self.run_command(self.test_cli)
-      self.serial.readline()    # Drain the echoed command line.
-
-      err_msg = '%s: Expected %r but got %s after %d char received'
-
-      # Keep capturing the output until the test timer is expired.
-      self.num_ch_cap = 0
-      self.char_loss_occurrences = 0
-      data_starve_count = 0
-
-      total_num_ch = self.num_ch_exp    # Expected number of characters in total
-      ch_exp = CHARGEN_TXT[0]
-      ch_cap = 'z'      # any character value is ok for loop initial condition.
-      while self.num_ch_cap < total_num_ch:
-        captured = self.get_output()
-
-        if captured:
-          # There is some output data. Reset the data starvation count.
-          data_starve_count = 0
+    def __init__(self, ports, duration, cr50_workload=False, usb_output=False):
+        """Initialize UART stress tester
+
+        Args:
+          ports: List of UART ports to test.
+          duration: Time to keep testing in seconds.
+          cr50_workload: True if a workload should be generated on cr50
+          usb_output: True if a workload should be generated to USB channel
+
+        Raises:
+          ChargenTestError: if any of ports is not a valid character device.
+        """
+
+        # Save the arguments
+        for port in ports:
+            try:
+                mode = os.stat(port).st_mode
+            except OSError as e:
+                raise ChargenTestError(e)
+            if not stat.S_ISCHR(mode):
+                raise ChargenTestError("%s is not a character device." % port)
+
+        if duration <= 0:
+            raise ChargenTestError("Input error: duration is not positive.")
+
+        # Initialize logging object
+        self.logger = logging.getLogger(type(self).__name__)
+
+        # Create an UartSerial object per UART port
+        self.serials = {}  # UartSerial objects
+        for port in ports:
+            self.serials[port] = UartSerial(
+                port=port,
+                duration=duration,
+                cr50_workload=cr50_workload,
+                usb_output=usb_output,
+            )
+
+    def prepare(self):
+        """Prepare the test for each UART port"""
+        self.logger.info("Prepare ports for test")
+        for _, ser in self.serials.items():
+            ser.prepare()
+        self.logger.info("Ports are ready to test")
+
+    def print_result(self):
+        """Display the test result for each UART port
+
+        Returns:
+          char_lost: Total number of characters lost
+        """
+        char_lost = 0
+        for _, ser in self.serials.items():
+            (tmp_lost, _, _) = ser.get_result()
+            char_lost += tmp_lost
+
+        # If any characters are lost, then test fails.
+        msg = "lost %d character(s) from the test" % char_lost
+        if char_lost > 0:
+            self.logger.error("FAIL: %s", msg)
         else:
-          data_starve_count += 1
-          if data_starve_count > 1:
-            # If nothing was captured more than once, then terminate the test.
-            self.logger.debug('No more output')
-            break
-
-        for ch_cap in captured:
-          if ch_cap not in CHARGEN_TXT:
-            # If it is not alpha-numeric, terminate the test.
-            if ch_cap not in CRLF:
-              # If it is neither a CR nor LF, then it is an error case.
-              self.logger.error('Whole captured characters: %r', captured)
-              raise ChargenTestError(err_msg % ('Broken char captured', ch_exp,
-                                                hex(ord(ch_cap)),
-                                                self.num_ch_cap))
-
-            # Set the loop termination condition true.
-            total_num_ch = self.num_ch_cap
-
-          if self.num_ch_cap >= total_num_ch:
-            break
-
-          if ch_exp != ch_cap:
-            # If it is alpha-numeric but not continuous, then some characters
-            # are lost.
-            self.logger.error(err_msg, 'Char loss detected',
-                              ch_exp, repr(ch_cap), self.num_ch_cap)
-            self.char_loss_occurrences += 1
-
-            # Recalculate the expected number of characters to adjust
-            # termination condition. The loss might be bigger than this
-            # adjustment, but it is okay since it will terminates by either
-            # CR/LF detection or by data starvation.
-            idx_ch_exp = CHARGEN_TXT.find(ch_exp)
-            idx_ch_cap = CHARGEN_TXT.find(ch_cap)
-            if idx_ch_cap < idx_ch_exp:
-              idx_ch_cap += len(CHARGEN_TXT)
-            total_num_ch -= (idx_ch_cap - idx_ch_exp)
-
-          self.num_ch_cap += 1
-
-          # Determine What character is expected next?
-          ch_exp = CHARGEN_TXT[(CHARGEN_TXT.find(ch_cap) + 1) % CHARGEN_TXT_LEN]
-
-    finally:
-      self.serial.close()
-
-  def start_test(self):
-    """Start the test thread"""
-    self.logger.info('Test thread starts')
-    self.test_thread.start()
-
-  def wait_test_done(self):
-    """Wait until the test thread get done and join"""
-    self.test_thread.join()
-    self.logger.info('Test thread is done')
-
-  def get_result(self):
-    """Display the result
+            self.logger.info("PASS: %s", msg)
 
-    Returns:
-      Integer = the number of lost character
+        return char_lost
 
-    Raises:
-      ChargenTestError: if the capture is corrupted.
-    """
-    # If more characters than expected are captured, it means some messages
-    # from other than chargen are mixed. Stop processing further.
-    if self.num_ch_exp < self.num_ch_cap:
-      raise ChargenTestError('%s: UART output is corrupted.' %
-                             self.dev_prof['device_type'])
+    def run(self):
+        """Run the stress test on UART port(s)
 
-    # Get the count difference between the expected to the captured
-    # as the number of lost character.
-    char_lost = self.num_ch_exp - self.num_ch_cap
-    self.logger.info('%8d char lost / %10d (%.1f %%)',
-                     char_lost, self.num_ch_exp,
-                     char_lost * 100.0 / self.num_ch_exp)
+        Raises:
+          ChargenTestError: If any characters are lost.
+        """
 
-    return char_lost, self.num_ch_exp, self.char_loss_occurrences
+        # Detect UART source type, and decide which command to test.
+        self.prepare()
 
+        # Run the test on each UART port in thread.
+        self.logger.info("Test starts")
+        for _, ser in self.serials.items():
+            ser.start_test()
 
-class ChargenTest(object):
-  """UART stress tester
+        # Wait all tests to finish.
+        for _, ser in self.serials.items():
+            ser.wait_test_done()
 
-  Attributes:
-    logger: logging object
-    serials: Dictionary where key is filename of UART device, and the value is
-             UartSerial object
-  """
+        # Print the result.
+        char_lost = self.print_result()
+        if char_lost:
+            raise ChargenTestError(
+                "Test failed: lost %d character(s)" % char_lost
+            )
 
-  def __init__(self, ports, duration, cr50_workload=False,
-               usb_output=False):
-    """Initialize UART stress tester
+        self.logger.info("Test is done")
 
-    Args:
-      ports: List of UART ports to test.
-      duration: Time to keep testing in seconds.
-      cr50_workload: True if a workload should be generated on cr50
-      usb_output: True if a workload should be generated to USB channel
 
-    Raises:
-      ChargenTestError: if any of ports is not a valid character device.
-    """
+def parse_args(cmdline):
+    """Parse command line arguments.
 
-    # Save the arguments
-    for port in ports:
-      try:
-        mode = os.stat(port).st_mode
-      except OSError as e:
-        raise ChargenTestError(e)
-      if not stat.S_ISCHR(mode):
-        raise ChargenTestError('%s is not a character device.' % port)
-
-    if duration <= 0:
-      raise ChargenTestError('Input error: duration is not positive.')
-
-    # Initialize logging object
-    self.logger = logging.getLogger(type(self).__name__)
-
-    # Create an UartSerial object per UART port
-    self.serials = {}     # UartSerial objects
-    for port in ports:
-      self.serials[port] = UartSerial(port=port, duration=duration,
-                                      cr50_workload=cr50_workload,
-                                      usb_output=usb_output)
-
-  def prepare(self):
-    """Prepare the test for each UART port"""
-    self.logger.info('Prepare ports for test')
-    for _, ser in self.serials.items():
-      ser.prepare()
-    self.logger.info('Ports are ready to test')
-
-  def print_result(self):
-    """Display the test result for each UART port
+    Args:
+      cmdline: list to be parsed
 
     Returns:
-      char_lost: Total number of characters lost
-    """
-    char_lost = 0
-    for _, ser in self.serials.items():
-      (tmp_lost, _, _) = ser.get_result()
-      char_lost += tmp_lost
-
-    # If any characters are lost, then test fails.
-    msg = 'lost %d character(s) from the test' % char_lost
-    if char_lost > 0:
-      self.logger.error('FAIL: %s', msg)
-    else:
-      self.logger.info('PASS: %s', msg)
-
-    return char_lost
-
-  def run(self):
-    """Run the stress test on UART port(s)
-
-    Raises:
-      ChargenTestError: If any characters are lost.
+      tuple (options, args) where args is a list of cmdline arguments that the
+      parser was unable to match i.e. they're servod controls, not options.
     """
-
-    # Detect UART source type, and decide which command to test.
-    self.prepare()
-
-    # Run the test on each UART port in thread.
-    self.logger.info('Test starts')
-    for _, ser in self.serials.items():
-      ser.start_test()
-
-    # Wait all tests to finish.
-    for _, ser in self.serials.items():
-      ser.wait_test_done()
-
-    # Print the result.
-    char_lost = self.print_result()
-    if char_lost:
-      raise ChargenTestError('Test failed: lost %d character(s)' %
-                             char_lost)
-
-    self.logger.info('Test is done')
-
-def parse_args(cmdline):
-  """Parse command line arguments.
-
-  Args:
-    cmdline: list to be parsed
-
-  Returns:
-    tuple (options, args) where args is a list of cmdline arguments that the
-    parser was unable to match i.e. they're servod controls, not options.
-  """
-  description = """%(prog)s repeats sending a uart console command
+    description = """%(prog)s repeats sending a uart console command
 to each UART device for a given time, and check if output
 has any missing characters.
 
@@ -511,52 +549,74 @@ Examples:
     %(prog)s /dev/ttyUSB1 /dev/ttyUSB2 --cr50
 """
 
-  parser = argparse.ArgumentParser(description=description,
-                                   formatter_class=argparse.RawTextHelpFormatter
-                                  )
-  parser.add_argument('port', type=str, nargs='*',
-                      help='UART device path to test')
-  parser.add_argument('-c', '--cr50', action='store_true', default=False,
-                      help='generate TPM workload on cr50')
-  parser.add_argument('-d', '--debug', action='store_true', default=False,
-                      help='enable debug messages')
-  parser.add_argument('-t', '--time', type=int,
-                      help='Test duration in second', default=300)
-  parser.add_argument('-u', '--usb', action='store_true', default=False,
-                      help='Generate output to USB channel instead')
-  return parser.parse_known_args(cmdline)
+    parser = argparse.ArgumentParser(
+        description=description, formatter_class=argparse.RawTextHelpFormatter
+    )
+    parser.add_argument(
+        "port", type=str, nargs="*", help="UART device path to test"
+    )
+    parser.add_argument(
+        "-c",
+        "--cr50",
+        action="store_true",
+        default=False,
+        help="generate TPM workload on cr50",
+    )
+    parser.add_argument(
+        "-d",
+        "--debug",
+        action="store_true",
+        default=False,
+        help="enable debug messages",
+    )
+    parser.add_argument(
+        "-t", "--time", type=int, help="Test duration in second", default=300
+    )
+    parser.add_argument(
+        "-u",
+        "--usb",
+        action="store_true",
+        default=False,
+        help="Generate output to USB channel instead",
+    )
+    return parser.parse_known_args(cmdline)
 
 
 def main():
-  """Main function wrapper"""
-  try:
-    (options, _) = parse_args(sys.argv[1:])
-
-    # Set Log format
-    log_format = '%(asctime)s %(levelname)-6s | %(name)-25s'
-    date_format = '%Y-%m-%d %H:%M:%S'
-    if options.debug:
-      log_format += ' | %(filename)s:%(lineno)4d:%(funcName)-18s'
-      loglevel = logging.DEBUG
-    else:
-      loglevel = logging.INFO
-    log_format += ' | %(message)s'
-
-    logging.basicConfig(level=loglevel, format=log_format,
-                        datefmt=date_format)
-
-    # Create a ChargenTest object
-    utest = ChargenTest(options.port, options.time,
-                        cr50_workload=options.cr50,
-                        usb_output=options.usb)
-    utest.run()    # Run
-
-  except KeyboardInterrupt:
-    sys.exit(0)
-
-  except ChargenTestError as e:
-    logging.error(str(e))
-    sys.exit(1)
-
-if __name__ == '__main__':
-  main()
+    """Main function wrapper"""
+    try:
+        (options, _) = parse_args(sys.argv[1:])
+
+        # Set Log format
+        log_format = "%(asctime)s %(levelname)-6s | %(name)-25s"
+        date_format = "%Y-%m-%d %H:%M:%S"
+        if options.debug:
+            log_format += " | %(filename)s:%(lineno)4d:%(funcName)-18s"
+            loglevel = logging.DEBUG
+        else:
+            loglevel = logging.INFO
+        log_format += " | %(message)s"
+
+        logging.basicConfig(
+            level=loglevel, format=log_format, datefmt=date_format
+        )
+
+        # Create a ChargenTest object
+        utest = ChargenTest(
+            options.port,
+            options.time,
+            cr50_workload=options.cr50,
+            usb_output=options.usb,
+        )
+        utest.run()  # Run
+
+    except KeyboardInterrupt:
+        sys.exit(0)
+
+    except ChargenTestError as e:
+        logging.error(str(e))
+        sys.exit(1)
+
+
+if __name__ == "__main__":
+    main()
diff --git a/util/unpack_ftb.py b/util/unpack_ftb.py
index 03127a7089..4873190fb3 100755
--- a/util/unpack_ftb.py
+++ b/util/unpack_ftb.py
@@ -1,35 +1,33 @@
 #!/usr/bin/env python
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Copyright 2018 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
-#
-# Ignore indention messages, since legacy scripts use 2 spaces instead of 4.
-# pylint: disable=bad-indentation,docstring-section-indent
-# pylint: disable=docstring-trailing-quotes
 
 # Note: This is a py2/3 compatible file.
 
 from __future__ import print_function
+
 import argparse
 import ctypes
 import os
 
 
 class Header(ctypes.Structure):
-  _pack_ = 1
-  _fields_ = [
-      ('signature', ctypes.c_uint32),
-      ('ftb_ver', ctypes.c_uint32),
-      ('chip_id', ctypes.c_uint32),
-      ('svn_ver', ctypes.c_uint32),
-      ('fw_ver', ctypes.c_uint32),
-      ('config_id', ctypes.c_uint32),
-      ('config_ver', ctypes.c_uint32),
-      ('reserved', ctypes.c_uint8 * 8),
-      ('release_info', ctypes.c_ulonglong),
-      ('sec_size', ctypes.c_uint32 * 4),
-      ('crc', ctypes.c_uint32),
-  ]
+    _pack_ = 1
+    _fields_ = [
+        ("signature", ctypes.c_uint32),
+        ("ftb_ver", ctypes.c_uint32),
+        ("chip_id", ctypes.c_uint32),
+        ("svn_ver", ctypes.c_uint32),
+        ("fw_ver", ctypes.c_uint32),
+        ("config_id", ctypes.c_uint32),
+        ("config_ver", ctypes.c_uint32),
+        ("reserved", ctypes.c_uint8 * 8),
+        ("release_info", ctypes.c_ulonglong),
+        ("sec_size", ctypes.c_uint32 * 4),
+        ("crc", ctypes.c_uint32),
+    ]
+
 
 FW_HEADER_SIZE = 64
 FW_HEADER_SIGNATURE = 0xAA55AA55
@@ -44,7 +42,7 @@ FLASH_SEC_ADDR = [
     0x0000 * 4,  # CODE
     0x7C00 * 4,  # CONFIG
     0x7000 * 4,  # CX
-    None  # This section shouldn't exist
+    None,  # This section shouldn't exist
 ]
 
 UPDATE_PDU_SIZE = 4096
@@ -59,64 +57,66 @@ OUTPUT_FILE_SIZE = UPDATE_PDU_SIZE + 128 * 1024
 
 
 def main():
-  parser = argparse.ArgumentParser()
-  parser.add_argument('--input', '-i', required=True)
-  parser.add_argument('--output', '-o', required=True)
-  args = parser.parse_args()
+    parser = argparse.ArgumentParser()
+    parser.add_argument("--input", "-i", required=True)
+    parser.add_argument("--output", "-o", required=True)
+    args = parser.parse_args()
 
-  with open(args.input, 'rb') as f:
-    bs = f.read()
+    with open(args.input, "rb") as f:
+        bs = f.read()
 
-  size = len(bs)
-  if size < FW_HEADER_SIZE + FW_BYTES_ALIGN:
-    raise Exception('FW size too small')
+    size = len(bs)
+    if size < FW_HEADER_SIZE + FW_BYTES_ALIGN:
+        raise Exception("FW size too small")
 
-  print('FTB file size:', size)
+    print("FTB file size:", size)
 
-  header = Header()
-  assert ctypes.sizeof(header) == FW_HEADER_SIZE
+    header = Header()
+    assert ctypes.sizeof(header) == FW_HEADER_SIZE
 
-  ctypes.memmove(ctypes.addressof(header), bs, ctypes.sizeof(header))
-  if (header.signature != FW_HEADER_SIGNATURE or
-      header.ftb_ver != FW_FTB_VER or
-      header.chip_id != FW_CHIP_ID):
-    raise Exception('Invalid header')
+    ctypes.memmove(ctypes.addressof(header), bs, ctypes.sizeof(header))
+    if (
+        header.signature != FW_HEADER_SIGNATURE
+        or header.ftb_ver != FW_FTB_VER
+        or header.chip_id != FW_CHIP_ID
+    ):
+        raise Exception("Invalid header")
 
-  for key, _ in header._fields_:
-    v = getattr(header, key)
-    if isinstance(v, ctypes.Array):
-      print(key, list(map(hex, v)))
-    else:
-      print(key, hex(v))
+    for key, _ in header._fields_:
+        v = getattr(header, key)
+        if isinstance(v, ctypes.Array):
+            print(key, list(map(hex, v)))
+        else:
+            print(key, hex(v))
 
-  dimension = sum(header.sec_size)
+    dimension = sum(header.sec_size)
 
-  assert dimension + FW_HEADER_SIZE + FW_BYTES_ALIGN == size
-  data = bs[FW_HEADER_SIZE:FW_HEADER_SIZE + dimension]
+    assert dimension + FW_HEADER_SIZE + FW_BYTES_ALIGN == size
+    data = bs[FW_HEADER_SIZE : FW_HEADER_SIZE + dimension]
 
-  with open(args.output, 'wb') as f:
-    # ensure the file size
-    f.seek(OUTPUT_FILE_SIZE - 1, os.SEEK_SET)
-    f.write(b'\x00')
+    with open(args.output, "wb") as f:
+        # ensure the file size
+        f.seek(OUTPUT_FILE_SIZE - 1, os.SEEK_SET)
+        f.write(b"\x00")
 
-    f.seek(0, os.SEEK_SET)
-    f.write(bs[0 : ctypes.sizeof(header)])
+        f.seek(0, os.SEEK_SET)
+        f.write(bs[0 : ctypes.sizeof(header)])
 
-    offset = 0
-    # write each sections
-    for i, addr in enumerate(FLASH_SEC_ADDR):
-      size = header.sec_size[i]
-      assert addr is not None or size == 0
+        offset = 0
+        # write each sections
+        for i, addr in enumerate(FLASH_SEC_ADDR):
+            size = header.sec_size[i]
+            assert addr is not None or size == 0
 
-      if size == 0:
-        continue
+            if size == 0:
+                continue
 
-      f.seek(UPDATE_PDU_SIZE + addr, os.SEEK_SET)
-      f.write(data[offset : offset + size])
-      offset += size
+            f.seek(UPDATE_PDU_SIZE + addr, os.SEEK_SET)
+            f.write(data[offset : offset + size])
+            offset += size
 
-    f.flush()
+        f.flush()
 
 
-if __name__ == '__main__':
-  main()
+if __name__ == "__main__":
+    main()
diff --git a/util/update_release_branch.py b/util/update_release_branch.py
index b9063d4970..0a871724fe 100755
--- a/util/update_release_branch.py
+++ b/util/update_release_branch.py
@@ -1,5 +1,5 @@
 #!/usr/bin/env python3
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 """Release branch updater tool.
@@ -19,11 +19,10 @@ import subprocess
 import sys
 import textwrap
 
+BUG_NONE_PATTERN = re.compile("none", flags=re.IGNORECASE)
 
-BUG_NONE_PATTERN = re.compile('none', flags=re.IGNORECASE)
 
-
-def git_commit_msg(branch, head, merge_head, rel_paths, cmd):
+def git_commit_msg(cros_main, branch, head, merge_head, rel_paths, cmd):
     """Generates a merge commit message based off of relevant changes.
 
     This function obtains the relevant commits from the given relative paths in
@@ -31,6 +30,7 @@ def git_commit_msg(branch, head, merge_head, rel_paths, cmd):
     showing the command used to find the relevant commits.
 
     Args:
+        cros_main: String indicating the origin branch name
         branch: String indicating the release branch name
         head: String indicating the HEAD refspec
         merge_head: String indicating the merge branch refspec.
@@ -42,18 +42,17 @@ def git_commit_msg(branch, head, merge_head, rel_paths, cmd):
         A String containing the git commit message with the exception of the
         Signed-Off-By field and Change-ID field.
     """
-    relevant_commits_cmd, relevant_commits = get_relevant_commits(head,
-                                                                  merge_head,
-                                                                  '--oneline',
-                                                                  rel_paths)
+    relevant_commits_cmd, relevant_commits = get_relevant_commits(
+        head, merge_head, "--oneline", rel_paths
+    )
 
-    _, relevant_bugs = get_relevant_commits(head, merge_head, '', rel_paths)
-    relevant_bugs = set(re.findall('BUG=(.*)', relevant_bugs))
+    _, relevant_bugs = get_relevant_commits(head, merge_head, "", rel_paths)
+    relevant_bugs = set(re.findall("BUG=(.*)", relevant_bugs))
     # Filter out "none" from set of bugs
     filtered = []
     for bug_line in relevant_bugs:
-        bug_line = bug_line.replace(',', ' ')
-        bugs = bug_line.split(' ')
+        bug_line = bug_line.replace(",", " ")
+        bugs = bug_line.split(" ")
         for bug in bugs:
             if bug and not BUG_NONE_PATTERN.match(bug):
                 filtered.append(bug)
@@ -61,8 +60,8 @@ def git_commit_msg(branch, head, merge_head, rel_paths, cmd):
 
     # TODO(b/179509333): remove Cq-Include-Trybots line when regular CQ and
     # firmware CQ do not behave differently.
-    COMMIT_MSG_TEMPLATE = """
-Merge remote-tracking branch cros/main into {BRANCH}
+    commit_msg_template = """
+Merge remote-tracking branch {CROS_MAIN} into {BRANCH}
 
 Generated by: {COMMAND_LINE}
 
@@ -76,24 +75,27 @@ BRANCH=None
 {BUG_FIELD}
 TEST=`make -j buildall`
 
-Cq-Include-Trybots: chromeos/cq:cq-orchestrator
+Force-Relevant-Builds: all
 """
-    # Wrap the relevant commits command and bug field such that we don't exceed
-    # 72 cols.
+    # Wrap the commands and bug field such that we don't exceed 72 cols.
     relevant_commits_cmd = textwrap.fill(relevant_commits_cmd, width=72)
+    cmd = textwrap.fill(cmd, width=72)
     # Wrap at 68 cols to save room for 'BUG='
-    bugs = textwrap.wrap(' '.join(relevant_bugs), width=68)
-    bug_field = ''
+    bugs = textwrap.wrap(" ".join(relevant_bugs), width=68)
+    bug_field = ""
     for line in bugs:
-        bug_field += 'BUG=' + line + '\n'
+        bug_field += "BUG=" + line + "\n"
     # Remove the final newline since the template adds it for us.
     bug_field = bug_field[:-1]
 
-    return COMMIT_MSG_TEMPLATE.format(BRANCH=branch,
-                                      RELEVANT_COMMITS_CMD=relevant_commits_cmd,
-                                      RELEVANT_COMMITS=relevant_commits,
-                                      BUG_FIELD=bug_field,
-                                      COMMAND_LINE=cmd)
+    return commit_msg_template.format(
+        CROS_MAIN=cros_main,
+        BRANCH=branch,
+        RELEVANT_COMMITS_CMD=relevant_commits_cmd,
+        RELEVANT_COMMITS=relevant_commits,
+        BUG_FIELD=bug_field,
+        COMMAND_LINE=cmd,
+    )
 
 
 def get_relevant_boards(baseboard):
@@ -105,15 +107,16 @@ def get_relevant_boards(baseboard):
     Returns:
         A list of strings containing the boards based off of the baseboard.
     """
-    proc = subprocess.run(['git', 'grep', 'BASEBOARD:=' + baseboard, '--',
-                           'board/'],
-                          stdout=subprocess.PIPE,
-                          encoding='utf-8',
-                          check=True)
+    proc = subprocess.run(
+        ["git", "grep", "BASEBOARD:=" + baseboard, "--", "board/"],
+        stdout=subprocess.PIPE,
+        encoding="utf-8",
+        check=True,
+    )
     boards = []
     res = proc.stdout.splitlines()
     for line in res:
-        boards.append(line.split('/')[1])
+        boards.append(line.split("/")[1])
     return boards
 
 
@@ -135,21 +138,25 @@ def get_relevant_commits(head, merge_head, fmt, relevant_paths):
         stdout.
     """
     if fmt:
-        cmd = ['git', 'log', fmt, head + '..' + merge_head, '--',
-               relevant_paths]
+        cmd = [
+            "git",
+            "log",
+            fmt,
+            head + ".." + merge_head,
+            "--",
+            relevant_paths,
+        ]
     else:
-        cmd = ['git', 'log', head + '..' + merge_head, '--', relevant_paths]
+        cmd = ["git", "log", head + ".." + merge_head, "--", relevant_paths]
 
     # Pass cmd as a string to subprocess.run() since we need to run with shell
     # equal to True.  The reason we are using shell equal to True is to take
     # advantage of the glob expansion for the relevant paths.
-    cmd = ' '.join(cmd)
-    proc = subprocess.run(cmd,
-                          stdout=subprocess.PIPE,
-                          encoding='utf-8',
-                          check=True,
-                          shell=True)
-    return ''.join(proc.args), proc.stdout
+    cmd = " ".join(cmd)
+    proc = subprocess.run(
+        cmd, stdout=subprocess.PIPE, encoding="utf-8", check=True, shell=True
+    )
+    return "".join(proc.args), proc.stdout
 
 
 def main(argv):
@@ -165,112 +172,235 @@ def main(argv):
         argv: A list of the command line arguments passed to this script.
     """
     # Set up argument parser.
-    parser = argparse.ArgumentParser(description=('A script that generates a '
-                                                  'merge commit from cros/main'
-                                                  ' to a desired release '
-                                                  'branch.  By default, the '
-                                                  '"recursive" merge strategy '
-                                                  'with the "theirs" strategy '
-                                                  'option is used.'))
-    parser.add_argument('--baseboard')
-    parser.add_argument('--board')
-    parser.add_argument('release_branch', help=('The name of the target release'
-                                                ' branch'))
-    parser.add_argument('--relevant_paths_file',
-                        help=('A path to a text file which includes other '
-                              'relevant paths of interest for this board '
-                              'or baseboard'))
-    parser.add_argument('--merge_strategy', '-s', default='recursive',
-                        help='The merge strategy to pass to `git merge -s`')
-    parser.add_argument('--strategy_option', '-X',
-                        help=('The strategy option for the chosen merge '
-                              'strategy'))
+    parser = argparse.ArgumentParser(
+        description=(
+            "A script that generates a "
+            "merge commit from cros/main"
+            " to a desired release "
+            "branch.  By default, the "
+            '"recursive" merge strategy '
+            'with the "theirs" strategy '
+            "option is used."
+        )
+    )
+    parser.add_argument("--baseboard")
+    parser.add_argument("--board")
+    parser.add_argument(
+        "release_branch", help=("The name of the target release" " branch")
+    )
+    parser.add_argument(
+        "--remote_prefix",
+        help=(
+            "The name of the remote branch prefix (default cros). "
+            "Private repos typically use cros-internal instead."
+        ),
+        default="cros",
+    )
+    parser.add_argument(
+        "--relevant_paths_file",
+        help=(
+            "A path to a text file which includes other "
+            "relevant paths of interest for this board "
+            "or baseboard"
+        ),
+    )
+    parser.add_argument(
+        "--merge_strategy",
+        "-s",
+        default="recursive",
+        help="The merge strategy to pass to `git merge -s`",
+    )
+    parser.add_argument(
+        "--strategy_option",
+        "-X",
+        help=("The strategy option for the chosen merge " "strategy"),
+    )
+    parser.add_argument(
+        "--remove_owners",
+        "-r",
+        action=("store_true"),
+        help=("Remove non-root OWNERS level files if present"),
+    )
 
     opts = parser.parse_args(argv[1:])
 
-    baseboard_dir = ''
-    board_dir = ''
+    baseboard_dir = ""
+    board_dir = ""
 
     if opts.baseboard:
         # Dereference symlinks so "git log" works as expected.
-        baseboard_dir = os.path.relpath('baseboard/' + opts.baseboard)
+        baseboard_dir = os.path.relpath("baseboard/" + opts.baseboard)
         baseboard_dir = os.path.relpath(os.path.realpath(baseboard_dir))
 
         boards = get_relevant_boards(opts.baseboard)
     elif opts.board:
-        board_dir = os.path.relpath('board/' + opts.board)
+        board_dir = os.path.relpath("board/" + opts.board)
         board_dir = os.path.relpath(os.path.realpath(board_dir))
         boards = [opts.board]
     else:
-        parser.error('You must specify a board OR a baseboard')
+        boards = []
 
-    print('Gathering relevant paths...')
+    print("Gathering relevant paths...")
     relevant_paths = []
     if opts.baseboard:
         relevant_paths.append(baseboard_dir)
-    else:
+    elif opts.board:
         relevant_paths.append(board_dir)
 
     for board in boards:
-        relevant_paths.append('board/' + board)
+        relevant_paths.append("board/" + board)
 
     # Check for the existence of a file that has other paths of interest.
     if opts.relevant_paths_file and os.path.exists(opts.relevant_paths_file):
-        with open(opts.relevant_paths_file, 'r') as relevant_paths_file:
+        with open(opts.relevant_paths_file, "r") as relevant_paths_file:
             for line in relevant_paths_file:
-                if not line.startswith('#'):
+                if not line.startswith("#"):
                     relevant_paths.append(line.rstrip())
-    relevant_paths.append('util/getversion.sh')
-    relevant_paths = ' '.join(relevant_paths)
+    if os.path.exists("util/getversion.sh"):
+        relevant_paths.append("util/getversion.sh")
+    relevant_paths = " ".join(relevant_paths)
 
     # Check if we are already in merge process
-    result = subprocess.run(['git', 'rev-parse', '--quiet', '--verify',
-                             'MERGE_HEAD'], stdout=subprocess.DEVNULL,
-                            stderr=subprocess.DEVNULL, check=False)
+    result = subprocess.run(
+        ["git", "rev-parse", "--quiet", "--verify", "MERGE_HEAD"],
+        stdout=subprocess.DEVNULL,
+        stderr=subprocess.DEVNULL,
+        check=False,
+    )
+
+    # Prune OWNERS files if desired
+    if opts.remove_owners:
+        prunelist = []
+        for root, dirs, files in os.walk("."):
+            for name in dirs:
+                if "build" in name:
+                    continue
+            for name in files:
+                if "OWNERS" in name:
+                    path = os.path.join(root, name)
+                    prunelist.append(path[2:])  # Strip the "./"
+
+        # Remove the top level OWNERS file from the prunelist.
+        try:
+            prunelist.remove("OWNERS")
+        except ValueError:
+            pass
+
+        if prunelist:
+            print("Not merging the following OWNERS files:")
+            for path in prunelist:
+                print("  " + path)
+
     if result.returncode:
         # Let's perform the merge
-        print('Updating remote...')
-        subprocess.run(['git', 'remote', 'update'], check=True)
-        subprocess.run(['git', 'checkout', '-B', opts.release_branch, 'cros/' +
-                        opts.release_branch], check=True)
-        print('Attempting git merge...')
-        if opts.merge_strategy == 'recursive' and not opts.strategy_option:
-            opts.strategy_option = 'theirs'
-        print('Using "%s" merge strategy' % opts.merge_strategy,
-              ("with strategy option '%s'" % opts.strategy_option
-               if opts.strategy_option else ''))
-        arglist = ['git', 'merge', '--no-ff', '--no-commit', 'cros/main', '-s',
-                   opts.merge_strategy]
+        print("Updating remote...")
+        subprocess.run(["git", "remote", "update"], check=True)
+        subprocess.run(
+            [
+                "git",
+                "checkout",
+                "-B",
+                opts.release_branch,
+                opts.remote_prefix + "/" + opts.release_branch,
+            ],
+            check=True,
+        )
+        print("Attempting git merge...")
+        if opts.merge_strategy == "recursive" and not opts.strategy_option:
+            opts.strategy_option = "theirs"
+        print(
+            'Using "%s" merge strategy' % opts.merge_strategy,
+            (
+                "with strategy option '%s'" % opts.strategy_option
+                if opts.strategy_option
+                else ""
+            ),
+        )
+        cros_main = opts.remote_prefix + "/" + "main"
+        arglist = [
+            "git",
+            "merge",
+            "--no-ff",
+            "--no-commit",
+            cros_main,
+            "-s",
+            opts.merge_strategy,
+        ]
         if opts.strategy_option:
-            arglist.append('-X' + opts.strategy_option)
-        subprocess.run(arglist, check=True)
+            arglist.append("-X" + opts.strategy_option)
+        try:
+            subprocess.run(arglist, check=True)
+        except:
+            # We've likely encountered a merge conflict due to new OWNERS file
+            # modifications. If we're removing the owners, we'll delete them.
+            if opts.remove_owners and prunelist:
+                # Find the unmerged files
+                unmerged = (
+                    subprocess.run(
+                        ["git", "diff", "--name-only", "--diff-filter=U"],
+                        stdout=subprocess.PIPE,
+                        encoding="utf-8",
+                        check=True,
+                    )
+                    .stdout.rstrip()
+                    .split()
+                )
+
+                # Prune OWNERS files
+                for file in unmerged:
+                    if file in prunelist:
+                        subprocess.run(["git", "rm", file], check=False)
+                        unmerged.remove(file)
+
+                print("Removed non-root OWNERS files.")
+                if unmerged:
+                    print(
+                        "Unmerged files still exist! You need to manually resolve this."
+                    )
+                    print("\n".join(unmerged))
+                    sys.exit(1)
+            else:
+                raise
     else:
-        print('We have already started merge process.',
-              'Attempt to generate commit.')
-
-    print('Generating commit message...')
-    branch = subprocess.run(['git', 'rev-parse', '--abbrev-ref', 'HEAD'],
-                            stdout=subprocess.PIPE,
-                            encoding='utf-8',
-                            check=True).stdout.rstrip()
-    head = subprocess.run(['git', 'rev-parse', '--short', 'HEAD'],
-                          stdout=subprocess.PIPE,
-                          encoding='utf-8',
-                          check=True).stdout.rstrip()
-    merge_head = subprocess.run(['git', 'rev-parse', '--short',
-                                 'MERGE_HEAD'],
-                                stdout=subprocess.PIPE,
-                                encoding='utf-8',
-                                check=True).stdout.rstrip()
-
-    cmd = ' '.join(argv)
-    print('Typing as fast as I can...')
-    commit_msg = git_commit_msg(branch, head, merge_head, relevant_paths, cmd)
-    subprocess.run(['git', 'commit', '--signoff', '-m', commit_msg], check=True)
-    subprocess.run(['git', 'commit', '--amend'], check=True)
-    print(("Finished! **Please review the commit to see if it's to your "
-           'liking.**'))
-
-
-if __name__ == '__main__':
+        print(
+            "We have already started merge process.",
+            "Attempt to generate commit.",
+        )
+
+    print("Generating commit message...")
+    branch = subprocess.run(
+        ["git", "rev-parse", "--abbrev-ref", "HEAD"],
+        stdout=subprocess.PIPE,
+        encoding="utf-8",
+        check=True,
+    ).stdout.rstrip()
+    head = subprocess.run(
+        ["git", "rev-parse", "--short", "HEAD"],
+        stdout=subprocess.PIPE,
+        encoding="utf-8",
+        check=True,
+    ).stdout.rstrip()
+    merge_head = subprocess.run(
+        ["git", "rev-parse", "--short", "MERGE_HEAD"],
+        stdout=subprocess.PIPE,
+        encoding="utf-8",
+        check=True,
+    ).stdout.rstrip()
+
+    cmd = " ".join(argv)
+    print("Typing as fast as I can...")
+    commit_msg = git_commit_msg(
+        cros_main, branch, head, merge_head, relevant_paths, cmd
+    )
+    subprocess.run(["git", "commit", "--signoff", "-m", commit_msg], check=True)
+    subprocess.run(["git", "commit", "--amend"], check=True)
+    print(
+        (
+            "Finished! **Please review the commit to see if it's to your "
+            "liking.**"
+        )
+    )
+
+
+if __name__ == "__main__":
     main(sys.argv)
diff --git a/util/usb_if.c b/util/usb_if.c
index f8aa6bfd7e..0cd642834a 100644
--- a/util/usb_if.c
+++ b/util/usb_if.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,16 +12,14 @@
 
 /* Return 0 on error, since it's never gonna be EP 0 */
 static int find_endpoint(const struct libusb_interface_descriptor *iface,
-			 uint16_t subclass,
-			 uint16_t protocol,
+			 uint16_t subclass, uint16_t protocol,
 			 struct usb_endpoint *uep)
 {
 	const struct libusb_endpoint_descriptor *ep;
 
 	if (iface->bInterfaceClass == 255 &&
 	    iface->bInterfaceSubClass == subclass &&
-	    iface->bInterfaceProtocol == protocol &&
-	    iface->bNumEndpoints) {
+	    iface->bInterfaceProtocol == protocol && iface->bNumEndpoints) {
 		ep = &iface->endpoint[0];
 		uep->ep_num = ep->bEndpointAddress & 0x7f;
 		uep->chunk_len = ep->wMaxPacketSize;
@@ -32,8 +30,7 @@ static int find_endpoint(const struct libusb_interface_descriptor *iface,
 }
 
 /* Return -1 on error */
-static int find_interface(uint16_t subclass,
-			  uint16_t protocol,
+static int find_interface(uint16_t subclass, uint16_t protocol,
 			  struct usb_endpoint *uep)
 {
 	int iface_num = -1;
@@ -66,8 +63,8 @@ out:
 	return iface_num;
 }
 
-static libusb_device_handle *check_device(libusb_device *dev,
-	uint16_t vid, uint16_t pid, const char *serial)
+static libusb_device_handle *check_device(libusb_device *dev, uint16_t vid,
+					  uint16_t pid, const char *serial)
 {
 	struct libusb_device_descriptor desc;
 	libusb_device_handle *handle = NULL;
@@ -81,18 +78,17 @@ static libusb_device_handle *check_device(libusb_device *dev,
 		return NULL;
 
 	if (desc.iSerialNumber && serial) {
-		sn_size = libusb_get_string_descriptor_ascii(handle,
-				desc.iSerialNumber, (unsigned char *)sn,
-				sizeof(sn));
+		sn_size = libusb_get_string_descriptor_ascii(
+			handle, desc.iSerialNumber, (unsigned char *)sn,
+			sizeof(sn));
 	}
 	/*
 	 * If the VID, PID, and serial number don't match, then it's not the
 	 * correct device. Close the handle and return NULL.
 	 */
-	if ((vid && vid != desc.idVendor) ||
-	    (pid && pid != desc.idProduct) ||
-	    (serial && ((sn_size != strlen(serial)) ||
-	    memcmp(sn, serial, sn_size)))) {
+	if ((vid && vid != desc.idVendor) || (pid && pid != desc.idProduct) ||
+	    (serial &&
+	     ((sn_size != strlen(serial)) || memcmp(sn, serial, sn_size)))) {
 		libusb_close(handle);
 		return NULL;
 	}
@@ -156,8 +152,8 @@ int usb_findit(const char *serial, uint16_t vid, uint16_t pid,
 		goto terminate_usb_findit;
 	}
 
-	printf("found interface %d endpoint %d, chunk_len %d\n",
-	       iface_num, uep->ep_num, uep->chunk_len);
+	printf("found interface %d endpoint %d, chunk_len %d\n", iface_num,
+	       uep->ep_num, uep->chunk_len);
 
 	libusb_set_auto_detach_kernel_driver(uep->devh, 1);
 	r = libusb_claim_interface(uep->devh, iface_num);
@@ -175,17 +171,15 @@ terminate_usb_findit:
 	return -1;
 }
 
-int usb_trx(struct usb_endpoint *uep, void *outbuf, int outlen,
-	    void *inbuf, int inlen, int allow_less, size_t *rxed_count)
+int usb_trx(struct usb_endpoint *uep, void *outbuf, int outlen, void *inbuf,
+	    int inlen, int allow_less, size_t *rxed_count)
 {
-
 	int r, actual;
 
 	/* Send data out */
 	if (outbuf && outlen) {
 		actual = 0;
-		r = libusb_bulk_transfer(uep->devh, uep->ep_num,
-					 outbuf, outlen,
+		r = libusb_bulk_transfer(uep->devh, uep->ep_num, outbuf, outlen,
 					 &actual, 1000);
 		if (r < 0) {
 			USB_ERROR("libusb_bulk_transfer", r);
@@ -200,11 +194,9 @@ int usb_trx(struct usb_endpoint *uep, void *outbuf, int outlen,
 
 	/* Read reply back */
 	if (inbuf && inlen) {
-
 		actual = 0;
-		r = libusb_bulk_transfer(uep->devh, uep->ep_num | 0x80,
-					 inbuf, inlen,
-					 &actual, 1000);
+		r = libusb_bulk_transfer(uep->devh, uep->ep_num | 0x80, inbuf,
+					 inlen, &actual, 1000);
 		if (r < 0) {
 			USB_ERROR("libusb_bulk_transfer", r);
 			return -1;
diff --git a/util/usb_if.h b/util/usb_if.h
index 8cc1088c6e..37a33f6287 100644
--- a/util/usb_if.h
+++ b/util/usb_if.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,7 +13,7 @@
 struct usb_endpoint {
 	struct libusb_device_handle *devh;
 	uint8_t ep_num;
-	int     chunk_len;
+	int chunk_len;
 };
 
 /*
@@ -34,9 +34,8 @@ int usb_findit(const char *serialno, uint16_t vid, uint16_t pid,
  * pointer, if provided along with 'allow_less', lets the caller know how many
  * bytes were received.
  */
-int usb_trx(struct usb_endpoint *uep, void *outbuf, int outlen,
-	    void *inbuf, int inlen, int allow_less,
-	    size_t *rxed_count);
+int usb_trx(struct usb_endpoint *uep, void *outbuf, int outlen, void *inbuf,
+	    int inlen, int allow_less, size_t *rxed_count);
 
 /*
  * This function should be called for graceful tear down of the USB interface
@@ -46,8 +45,8 @@ int usb_trx(struct usb_endpoint *uep, void *outbuf, int outlen,
  */
 void usb_shut_down(struct usb_endpoint *uep);
 
-#define USB_ERROR(m, r) \
-	fprintf(stderr, "%s:%d, %s returned %d (%s)\n", __FILE__, __LINE__, \
-		m, r, libusb_strerror(r))
+#define USB_ERROR(m, r)                                                        \
+	fprintf(stderr, "%s:%d, %s returned %d (%s)\n", __FILE__, __LINE__, m, \
+		r, libusb_strerror(r))
 
-#endif  /* ! __EC_EXTRA_USB_UPDATER_USB_IF_H */
+#endif /* ! __EC_EXTRA_USB_UPDATER_USB_IF_H */
diff --git a/util/uut/cmd.c b/util/uut/cmd.c
index 57cf75a29e..02810b686a 100644
--- a/util/uut/cmd.c
+++ b/util/uut/cmd.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,7 +14,7 @@
 #include "lib_crc.h"
 #include "main.h"
 
- /* Extracting Byte - 8 bit: MSB, LSB */
+/* Extracting Byte - 8 bit: MSB, LSB */
 #define MSB(u16) ((uint8_t)((uint16_t)(u16) >> 8))
 #define LSB(u16) ((uint8_t)(u16))
 
@@ -85,7 +85,7 @@ void cmd_create_sync(uint8_t *cmd_info, uint32_t *cmd_len)
  *---------------------------------------------------------------------------
  */
 void cmd_create_write(uint32_t addr, uint32_t size, uint8_t *data_buf,
-					uint8_t *cmd_info, uint32_t *cmd_len)
+		      uint8_t *cmd_info, uint32_t *cmd_len)
 {
 	uint32_t i;
 	union cmd_addr adr_tr;
@@ -136,7 +136,7 @@ void cmd_create_write(uint32_t addr, uint32_t size, uint8_t *data_buf,
  *---------------------------------------------------------------------------
  */
 void cmd_create_read(uint32_t addr, uint8_t size, uint8_t *cmd_info,
-					uint32_t *cmd_len)
+		     uint32_t *cmd_len)
 {
 	uint32_t i;
 	union cmd_addr adr_tr;
@@ -251,7 +251,7 @@ void cmd_build_sync(struct command_node *cmd_buf, uint32_t *cmd_num)
  *---------------------------------------------------------------------------
  */
 void cmd_build_exec_exit(uint32_t addr, struct command_node *cmd_buf,
-						uint32_t *cmd_num)
+			 uint32_t *cmd_num)
 {
 	uint32_t cmd = 0;
 
@@ -280,7 +280,7 @@ void cmd_build_exec_exit(uint32_t addr, struct command_node *cmd_buf,
  *---------------------------------------------------------------------------
  */
 void cmd_build_exec_ret(uint32_t addr, struct command_node *cmd_buf,
-						uint32_t *cmd_num)
+			uint32_t *cmd_num)
 {
 	uint32_t cmd = 0;
 
@@ -325,10 +325,11 @@ bool cmd_disp_sync(uint8_t *resp_buf)
  *---------------------------------------------------------------------------
  */
 bool cmd_disp_write(uint8_t *resp_buf, uint32_t resp_size, uint32_t resp_num,
-					  uint32_t total_size)
+		    uint32_t total_size)
 {
 	if (resp_buf[0] == (uint8_t)(UFPP_WRITE_CMD)) {
-		display_color_msg(SUCCESS,
+		display_color_msg(
+			SUCCESS,
 			"\rTransmitted packet of size %u bytes, packet "
 			"[%u]out of [%u]",
 			resp_size, resp_num, total_size);
@@ -352,10 +353,11 @@ bool cmd_disp_write(uint8_t *resp_buf, uint32_t resp_size, uint32_t resp_num,
  *---------------------------------------------------------------------------
  */
 bool cmd_disp_read(uint8_t *resp_buf, uint32_t resp_size, uint32_t resp_num,
-					uint32_t total_size)
+		   uint32_t total_size)
 {
 	if (resp_buf[0] == (uint8_t)(UFPP_READ_CMD)) {
-		display_color_msg(SUCCESS,
+		display_color_msg(
+			SUCCESS,
 			"\rReceived packet of size %u bytes, packet [%u] out "
 			"of [%u]",
 			resp_size, resp_num, total_size);
@@ -412,10 +414,11 @@ void cmd_disp_flash_erase_dev(uint8_t *resp_buf, uint32_t dev_num)
 {
 	if (resp_buf[0] == (uint8_t)(UFPP_WRITE_CMD)) {
 		display_color_msg(SUCCESS,
-			"Flash Erase of device [%u] Passed\n", dev_num);
+				  "Flash Erase of device [%u] Passed\n",
+				  dev_num);
 	} else {
-		display_color_msg(
-			FAIL, "Flash Erase of device [%u] Failed\n", dev_num);
+		display_color_msg(FAIL, "Flash Erase of device [%u] Failed\n",
+				  dev_num);
 	}
 }
 
@@ -433,10 +436,11 @@ void cmd_disp_flash_erase_sect(uint8_t *resp_buf, uint32_t dev_num)
 {
 	if (resp_buf[0] == (uint8_t)(UFPP_WRITE_CMD)) {
 		display_color_msg(SUCCESS,
-			"Sector Erase of device [%lu] Passed\n", dev_num);
+				  "Sector Erase of device [%lu] Passed\n",
+				  dev_num);
 	} else {
-		display_color_msg(
-			FAIL, "Sector Erase of device [%lu] Failed\n", dev_num);
+		display_color_msg(FAIL, "Sector Erase of device [%lu] Failed\n",
+				  dev_num);
 	}
 }
 
@@ -471,11 +475,13 @@ void cmd_disp_exec_exit(uint8_t *resp_buf)
 void cmd_disp_exec_ret(uint8_t *resp_buf)
 {
 	if (resp_buf[1] == (uint8_t)(UFPP_FCALL_RSLT_CMD)) {
-		display_color_msg(SUCCESS,
+		display_color_msg(
+			SUCCESS,
 			"Execute Command Passed, execution result is [0x%X]\n",
 			resp_buf[2]);
 	} else {
-		display_color_msg(FAIL,
+		display_color_msg(
+			FAIL,
 			"Execute Command Failed  [0x%X]  [0x%X], rslt=[0x%X]\n",
 			resp_buf[0], resp_buf[1], resp_buf[2]);
 	}
diff --git a/util/uut/cmd.h b/util/uut/cmd.h
index 44cebbe989..cf8457000b 100644
--- a/util/uut/cmd.h
+++ b/util/uut/cmd.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,17 +18,17 @@
 #define MAX_RESP_BUF_SIZE 512
 
 enum uart_protocol_cmd {
-	UFPP_H2D_SYNC_CMD = 0x55,   /* Single-Byte Host to Device	 */
-				    /* synchronization command	 */
-	UFPP_D2H_SYNC_CMD = 0x5A,   /* Single-Byte Device to Host	 */
-				    /* synchronization response	 */
-	UFPP_WRITE_CMD = 0x07,      /* Write command and response	 */
-	UFPP_READ_CMD = 0x1C,       /* Read command and response	 */
-	UFPP_READ_CRC_CMD = 0x89,   /* Read CRC command and response */
-	UFPP_FCALL_CMD = 0x70,      /* Call function command	 */
+	UFPP_H2D_SYNC_CMD = 0x55, /* Single-Byte Host to Device	 */
+	/* synchronization command	 */
+	UFPP_D2H_SYNC_CMD = 0x5A, /* Single-Byte Device to Host	 */
+	/* synchronization response	 */
+	UFPP_WRITE_CMD = 0x07, /* Write command and response	 */
+	UFPP_READ_CMD = 0x1C, /* Read command and response	 */
+	UFPP_READ_CRC_CMD = 0x89, /* Read CRC command and response */
+	UFPP_FCALL_CMD = 0x70, /* Call function command	 */
 	UFPP_FCALL_RSLT_CMD = 0x73, /* Call function response	 */
-	UFPP_SPI_CMD = 0x92,        /* SPI specific command		 */
-	UFPP_ERROR_CMD = 0xFF       /* Error response		 */
+	UFPP_SPI_CMD = 0x92, /* SPI specific command		 */
+	UFPP_ERROR_CMD = 0xFF /* Error response		 */
 };
 
 struct command_node {
@@ -44,22 +44,22 @@ struct command_node {
 
 void cmd_create_sync(uint8_t *cmd_info, uint32_t *cmd_len);
 void cmd_create_write(uint32_t addr, uint32_t size, uint8_t *data_buf,
-					uint8_t *cmd_info, uint32_t *cmd_len);
+		      uint8_t *cmd_info, uint32_t *cmd_len);
 void cmd_create_read(uint32_t addr, uint8_t size, uint8_t *cmd_info,
-					uint32_t *cmd_len);
+		     uint32_t *cmd_len);
 void cmd_create_exec(uint32_t addr, uint8_t *cmd_info, uint32_t *cmd_len);
 
 void cmd_build_sync(struct command_node *cmd_buf, uint32_t *cmd_num);
 void cmd_build_exec_exit(uint32_t addr, struct command_node *cmd_buf,
-						uint32_t *cmd_num);
+			 uint32_t *cmd_num);
 void cmd_build_exec_ret(uint32_t addr, struct command_node *cmd_buf,
-						uint32_t *cmd_num);
+			uint32_t *cmd_num);
 
 bool cmd_disp_sync(uint8_t *resp_buf);
 bool cmd_disp_write(uint8_t *resp_buf, uint32_t resp_size, uint32_t resp_num,
-					uint32_t total_size);
+		    uint32_t total_size);
 bool cmd_disp_read(uint8_t *resp_buf, uint32_t resp_size, uint32_t resp_num,
-					uint32_t total_size);
+		   uint32_t total_size);
 void cmd_disp_data(uint8_t *resp_buf, uint32_t resp_size);
 void cmd_disp_flash_erase_dev(uint8_t *resp_buf, uint32_t dev_num);
 void cmd_disp_flash_erase_sect(uint8_t *resp_buf, uint32_t dev_num);
diff --git a/util/uut/com_port.h b/util/uut/com_port.h
index 36331f2fb6..ca52bdd234 100644
--- a/util/uut/com_port.h
+++ b/util/uut/com_port.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -35,10 +35,10 @@ extern "C" {
 #define COMP_PORT_PREFIX_3 "pts"
 
 struct comport_fields {
-	uint32_t baudrate;    /* Baudrate at which running               */
-	tcflag_t byte_size;   /* Number of bits/byte, 4-8                */
-	tcflag_t parity;       /* 0-4=None,Odd,Even,Mark,Space            */
-	uint8_t stop_bits;    /* 0,1,2 = 1, 1.5, 2                       */
+	uint32_t baudrate; /* Baudrate at which running               */
+	tcflag_t byte_size; /* Number of bits/byte, 4-8                */
+	tcflag_t parity; /* 0-4=None,Odd,Even,Mark,Space            */
+	uint8_t stop_bits; /* 0,1,2 = 1, 1.5, 2                       */
 	uint8_t flow_control; /* 0-none, 1-SwFlowControl,2-HwFlowControl */
 };
 
@@ -60,7 +60,7 @@ struct comport_fields {
  *---------------------------------------------------------------------------
  */
 int com_port_open(const char *com_port_dev_name,
-				struct comport_fields com_port_fields);
+		  struct comport_fields com_port_fields);
 
 /*---------------------------------------------------------------------------
  * Function: int com_config_uart()
@@ -110,7 +110,7 @@ bool com_port_close(int device_id);
  *---------------------------------------------------------------------------
  */
 bool com_port_write_bin(int device_id, const uint8_t *buffer,
-						uint32_t buf_size);
+			uint32_t buf_size);
 
 /*---------------------------------------------------------------------------
  * Function: uint32_t com_port_read_bin()
diff --git a/util/uut/l_com_port.c b/util/uut/l_com_port.c
index 018dec9950..e774743160 100644
--- a/util/uut/l_com_port.c
+++ b/util/uut/l_com_port.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -100,7 +100,8 @@ void set_read_blocking(int dev_drv, bool block)
 	memset(&tty, 0, sizeof(tty));
 
 	if (tcgetattr(dev_drv, &tty) != 0) {
-		display_color_msg(FAIL,
+		display_color_msg(
+			FAIL,
 			"set_read_blocking Error: %d Fail to get attribute "
 			"from Device number %d.\n",
 			errno, dev_drv);
@@ -111,7 +112,8 @@ void set_read_blocking(int dev_drv, bool block)
 	tty.c_cc[VTIME] = 5; /* 0.5 seconds read timeout */
 
 	if (tcsetattr(dev_drv, TCSANOW, &tty) != 0) {
-		display_color_msg(FAIL,
+		display_color_msg(
+			FAIL,
 			"set_read_blocking Error: %d Fail to set attribute to "
 			"Device number %d.\n",
 			errno, dev_drv);
@@ -145,7 +147,8 @@ bool com_config_uart(int h_dev_drv, struct comport_fields com_port_fields)
 	memset(&tty, 0, sizeof(tty));
 
 	if (tcgetattr(h_dev_drv, &tty) != 0) {
-		display_color_msg(FAIL,
+		display_color_msg(
+			FAIL,
 			"com_config_uart Error: Fail to get attribute from "
 			"Device number %d.\n",
 			h_dev_drv);
@@ -171,12 +174,13 @@ bool com_config_uart(int h_dev_drv, struct comport_fields com_port_fields)
 	tty.c_lflag &= ~(ECHO | ECHONL | ICANON | ISIG | IEXTEN);
 
 	tty.c_oflag = ~OPOST;
-	tty.c_cc[VMIN] = 0;  /* read doesn't block		*/
+	tty.c_cc[VMIN] = 0; /* read doesn't block		*/
 	tty.c_cc[VTIME] = 5; /* 0.5 seconds read timeout	*/
 
-	tty.c_iflag |= (com_port_fields.flow_control == 0x01)
-			       ? (IXON | IXOFF)
-			       : 0x00; /* xon/xoff ctrl */
+	tty.c_iflag |= (com_port_fields.flow_control == 0x01) ?
+			       (IXON | IXOFF) :
+			       0x00; /* xon/xoff
+					ctrl */
 
 	tty.c_cflag |= (CLOCAL | CREAD); /* ignore modem controls */
 	/* enable reading */
@@ -191,7 +195,8 @@ bool com_config_uart(int h_dev_drv, struct comport_fields com_port_fields)
 	tcflush(h_dev_drv, TCIFLUSH);
 
 	if (tcsetattr(h_dev_drv, TCSANOW, &tty) != 0) {
-		display_color_msg(FAIL,
+		display_color_msg(
+			FAIL,
 			"com_config_uart Error: %d setting port handle %d: %s.\n",
 			errno, h_dev_drv, strerror(errno));
 		return false;
@@ -221,7 +226,6 @@ static void discard_input(int fd)
 	do {
 		res = read(fd, buffer, sizeof(buffer));
 		if (res > 0) {
-
 			/* Discard zeros in the beginning of the buffer. */
 			for (i = 0; i < res; i++)
 				if (buffer[i])
@@ -250,7 +254,6 @@ static void discard_input(int fd)
 		printf("%d zeros ignored\n", count_of_zeros);
 }
 
-
 /******************************************************************************
  * Function: int com_port_open()
  *
@@ -268,7 +271,7 @@ static void discard_input(int fd)
  *****************************************************************************
  */
 int com_port_open(const char *com_port_dev_name,
-				struct comport_fields com_port_fields)
+		  struct comport_fields com_port_fields)
 {
 	int port_handler;
 
@@ -276,15 +279,16 @@ int com_port_open(const char *com_port_dev_name,
 
 	if (port_handler < 0) {
 		display_color_msg(FAIL,
-				"com_port_open Error %d opening %s: %s\n",
-				errno, com_port_dev_name, strerror(errno));
+				  "com_port_open Error %d opening %s: %s\n",
+				  errno, com_port_dev_name, strerror(errno));
 		return INVALID_HANDLE_VALUE;
 	}
 
 	tcgetattr(port_handler, &savetty);
 
 	if (!com_config_uart(port_handler, com_port_fields)) {
-		display_color_msg(FAIL,
+		display_color_msg(
+			FAIL,
 			"com_port_open() Error %d, Failed on com_config_uart() %s, "
 			"%s\n",
 			errno, com_port_dev_name, strerror(errno));
@@ -318,7 +322,8 @@ bool com_port_close(int device_id)
 	tcsetattr(device_id, TCSANOW, &savetty);
 
 	if (close(device_id) == INVALID_HANDLE_VALUE) {
-		display_color_msg(FAIL,
+		display_color_msg(
+			FAIL,
 			"com_port_close() Error: %d Device com%u was not opened, "
 			"%s.\n",
 			errno, (uint32_t)device_id, strerror(errno));
@@ -345,14 +350,14 @@ bool com_port_close(int device_id)
  *
  *****************************************************************************
  */
-bool com_port_write_bin(int device_id, const uint8_t *buffer,
-						uint32_t buf_size)
+bool com_port_write_bin(int device_id, const uint8_t *buffer, uint32_t buf_size)
 {
 	uint32_t bytes_written;
 
 	bytes_written = write(device_id, buffer, buf_size);
 	if (bytes_written != buf_size) {
-		display_color_msg(FAIL,
+		display_color_msg(
+			FAIL,
 			"com_port_write_bin() Error: %d  Failed to write data to "
 			"Uart Port %d, %s.\n",
 			errno, (uint32_t)device_id, strerror(errno));
@@ -389,9 +394,10 @@ uint32_t com_port_read_bin(int device_id, uint8_t *buffer, uint32_t buf_size)
 
 	if (read_bytes == -1) {
 		display_color_msg(FAIL,
-			"%s() Error: %d Device number %u was not "
-			"opened, %s.\n",
-			__func__, errno, (uint32_t)device_id, strerror(errno));
+				  "%s() Error: %d Device number %u was not "
+				  "opened, %s.\n",
+				  __func__, errno, (uint32_t)device_id,
+				  strerror(errno));
 	}
 
 	return read_bytes;
@@ -422,9 +428,9 @@ uint32_t com_port_wait_read(int device_id)
 	fds.events = POLLIN;
 	ret_val = poll(&fds, 1, COMMAND_TIMEOUT);
 	if (ret_val < 0) {
-		display_color_msg(FAIL,
-			"%s() Error: %d Device number %u %s\n",
-			__func__, errno, (uint32_t)device_id, strerror(errno));
+		display_color_msg(FAIL, "%s() Error: %d Device number %u %s\n",
+				  __func__, errno, (uint32_t)device_id,
+				  strerror(errno));
 		return 0;
 	}
 
@@ -434,7 +440,8 @@ uint32_t com_port_wait_read(int device_id)
 	if (ret_val > 0) {
 		/* Get number of bytes that are ready to be read. */
 		if (ioctl(device_id, FIONREAD, &bytes) < 0) {
-			display_color_msg(FAIL,
+			display_color_msg(
+				FAIL,
 				"com_port_wait_for_read() Error: %d Device number "
 				"%u %s\n",
 				errno, (uint32_t)device_id, strerror(errno));
diff --git a/util/uut/lib_crc.c b/util/uut/lib_crc.c
index 176e91327c..ae83581063 100644
--- a/util/uut/lib_crc.c
+++ b/util/uut/lib_crc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -54,38 +54,35 @@
 
 /* CRC16 lookup table for polynom 0xA001 */
 static const unsigned short crc16_tab[256] = {
-	0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
-	0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
-	0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
-	0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
-	0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
-	0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
-	0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
-	0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
-	0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
-	0x3600, 0xF6C1, 0xF781, 0x3740, 0xF501, 0x35C0, 0x3480, 0xF441,
-	0x3C00, 0xFCC1, 0xFD81, 0x3D40, 0xFF01, 0x3FC0, 0x3E80, 0xFE41,
-	0xFA01, 0x3AC0, 0x3B80, 0xFB41, 0x3900, 0xF9C1, 0xF881, 0x3840,
-	0x2800, 0xE8C1, 0xE981, 0x2940, 0xEB01, 0x2BC0, 0x2A80, 0xEA41,
-	0xEE01, 0x2EC0, 0x2F80, 0xEF41, 0x2D00, 0xEDC1, 0xEC81, 0x2C40,
-	0xE401, 0x24C0, 0x2580, 0xE541, 0x2700, 0xE7C1, 0xE681, 0x2640,
-	0x2200, 0xE2C1, 0xE381, 0x2340, 0xE101, 0x21C0, 0x2080, 0xE041,
-	0xA001, 0x60C0, 0x6180, 0xA141, 0x6300, 0xA3C1, 0xA281, 0x6240,
-	0x6600, 0xA6C1, 0xA781, 0x6740, 0xA501, 0x65C0, 0x6480, 0xA441,
-	0x6C00, 0xACC1, 0xAD81, 0x6D40, 0xAF01, 0x6FC0, 0x6E80, 0xAE41,
-	0xAA01, 0x6AC0, 0x6B80, 0xAB41, 0x6900, 0xA9C1, 0xA881, 0x6840,
-	0x7800, 0xB8C1, 0xB981, 0x7940, 0xBB01, 0x7BC0, 0x7A80, 0xBA41,
-	0xBE01, 0x7EC0, 0x7F80, 0xBF41, 0x7D00, 0xBDC1, 0xBC81, 0x7C40,
-	0xB401, 0x74C0, 0x7580, 0xB541, 0x7700, 0xB7C1, 0xB681, 0x7640,
-	0x7200, 0xB2C1, 0xB381, 0x7340, 0xB101, 0x71C0, 0x7080, 0xB041,
-	0x5000, 0x90C1, 0x9181, 0x5140, 0x9301, 0x53C0, 0x5280, 0x9241,
-	0x9601, 0x56C0, 0x5780, 0x9741, 0x5500, 0x95C1, 0x9481, 0x5440,
-	0x9C01, 0x5CC0, 0x5D80, 0x9D41, 0x5F00, 0x9FC1, 0x9E81, 0x5E40,
-	0x5A00, 0x9AC1, 0x9B81, 0x5B40, 0x9901, 0x59C0, 0x5880, 0x9841,
-	0x8801, 0x48C0, 0x4980, 0x8941, 0x4B00, 0x8BC1, 0x8A81, 0x4A40,
-	0x4E00, 0x8EC1, 0x8F81, 0x4F40, 0x8D01, 0x4DC0, 0x4C80, 0x8C41,
-	0x4400, 0x84C1, 0x8581, 0x4540, 0x8701, 0x47C0, 0x4680, 0x8641,
-	0x8201, 0x42C0, 0x4380, 0x8341, 0x4100, 0x81C1, 0x8081, 0x4040
+	0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241, 0xC601,
+	0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440, 0xCC01, 0x0CC0,
+	0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40, 0x0A00, 0xCAC1, 0xCB81,
+	0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841, 0xD801, 0x18C0, 0x1980, 0xD941,
+	0x1B00, 0xDBC1, 0xDA81, 0x1A40, 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01,
+	0x1DC0, 0x1C80, 0xDC41, 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0,
+	0x1680, 0xD641, 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081,
+	0x1040, 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
+	0x3600, 0xF6C1, 0xF781, 0x3740, 0xF501, 0x35C0, 0x3480, 0xF441, 0x3C00,
+	0xFCC1, 0xFD81, 0x3D40, 0xFF01, 0x3FC0, 0x3E80, 0xFE41, 0xFA01, 0x3AC0,
+	0x3B80, 0xFB41, 0x3900, 0xF9C1, 0xF881, 0x3840, 0x2800, 0xE8C1, 0xE981,
+	0x2940, 0xEB01, 0x2BC0, 0x2A80, 0xEA41, 0xEE01, 0x2EC0, 0x2F80, 0xEF41,
+	0x2D00, 0xEDC1, 0xEC81, 0x2C40, 0xE401, 0x24C0, 0x2580, 0xE541, 0x2700,
+	0xE7C1, 0xE681, 0x2640, 0x2200, 0xE2C1, 0xE381, 0x2340, 0xE101, 0x21C0,
+	0x2080, 0xE041, 0xA001, 0x60C0, 0x6180, 0xA141, 0x6300, 0xA3C1, 0xA281,
+	0x6240, 0x6600, 0xA6C1, 0xA781, 0x6740, 0xA501, 0x65C0, 0x6480, 0xA441,
+	0x6C00, 0xACC1, 0xAD81, 0x6D40, 0xAF01, 0x6FC0, 0x6E80, 0xAE41, 0xAA01,
+	0x6AC0, 0x6B80, 0xAB41, 0x6900, 0xA9C1, 0xA881, 0x6840, 0x7800, 0xB8C1,
+	0xB981, 0x7940, 0xBB01, 0x7BC0, 0x7A80, 0xBA41, 0xBE01, 0x7EC0, 0x7F80,
+	0xBF41, 0x7D00, 0xBDC1, 0xBC81, 0x7C40, 0xB401, 0x74C0, 0x7580, 0xB541,
+	0x7700, 0xB7C1, 0xB681, 0x7640, 0x7200, 0xB2C1, 0xB381, 0x7340, 0xB101,
+	0x71C0, 0x7080, 0xB041, 0x5000, 0x90C1, 0x9181, 0x5140, 0x9301, 0x53C0,
+	0x5280, 0x9241, 0x9601, 0x56C0, 0x5780, 0x9741, 0x5500, 0x95C1, 0x9481,
+	0x5440, 0x9C01, 0x5CC0, 0x5D80, 0x9D41, 0x5F00, 0x9FC1, 0x9E81, 0x5E40,
+	0x5A00, 0x9AC1, 0x9B81, 0x5B40, 0x9901, 0x59C0, 0x5880, 0x9841, 0x8801,
+	0x48C0, 0x4980, 0x8941, 0x4B00, 0x8BC1, 0x8A81, 0x4A40, 0x4E00, 0x8EC1,
+	0x8F81, 0x4F40, 0x8D01, 0x4DC0, 0x4C80, 0x8C41, 0x4400, 0x84C1, 0x8581,
+	0x4540, 0x8701, 0x47C0, 0x4680, 0x8641, 0x8201, 0x42C0, 0x4380, 0x8341,
+	0x4100, 0x81C1, 0x8081, 0x4040
 };
 
 /*********************************************************************
diff --git a/util/uut/lib_crc.h b/util/uut/lib_crc.h
index 58db81c4e5..7d75c9b501 100644
--- a/util/uut/lib_crc.h
+++ b/util/uut/lib_crc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/util/uut/main.c b/util/uut/main.c
index 146ddc0275..915bff34d6 100644
--- a/util/uut/main.c
+++ b/util/uut/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -36,20 +36,20 @@
 #define DEFAULT_FLASH_OFFSET 0
 
 /* The magic number in monitor header */
-#define MONITOR_HDR_TAG        0xA5075001
+#define MONITOR_HDR_TAG 0xA5075001
 /* The location of monitor header */
-#define MONITOR_HDR_ADDR       0x200C3000
+#define MONITOR_HDR_ADDR 0x200C3000
 /* The start address of the monitor little firmware to execute */
-#define MONITOR_ADDR           0x200C3020
+#define MONITOR_ADDR 0x200C3020
 /* The start address to store the firmware segment to be programmed */
-#define FIRMWARE_START_ADDR    0x10090000
+#define FIRMWARE_START_ADDR 0x10090000
 /* Divide the ec firmware image into 4K byte */
-#define FIRMWARE_SEGMENT       0x1000
+#define FIRMWARE_SEGMENT 0x1000
 /* Register address for chip ID */
-#define NPCX_SRID_CR           0x400C101C
+#define NPCX_SRID_CR 0x400C101C
 /* Register address for device ID */
-#define NPCX_DEVICE_ID_CR      0x400C1022
-#define NPCX_FLASH_BASE_ADDR   0x64000000
+#define NPCX_DEVICE_ID_CR 0x400C1022
+#define NPCX_FLASH_BASE_ADDR 0x64000000
 
 /*---------------------------------------------------------------------------
  * Global variables
@@ -64,8 +64,8 @@ struct comport_fields port_cfg;
  *---------------------------------------------------------------------------
  */
 
-static const char tool_name[] = {"LINUX UART Update Tool"};
-static const char tool_version[] = {"2.0.1"};
+static const char tool_name[] = { "LINUX UART Update Tool" };
+static const char tool_version[] = { "2.0.1" };
 
 static char port_name[MAX_PARAM_SIZE];
 static char opr_name[MAX_PARAM_SIZE];
@@ -185,7 +185,7 @@ enum EXIT_CODE {
  *---------------------------------------------------------------------------
  */
 static bool image_auto_write(uint32_t offset, uint8_t *buffer,
-				uint32_t file_size)
+			     uint32_t file_size)
 {
 	uint32_t data_buf[4];
 	uint32_t addr, chunk_remain, file_seg, flash_index, seg;
@@ -199,8 +199,8 @@ static bool image_auto_write(uint32_t offset, uint8_t *buffer,
 	file_seg = file_size;
 	total = 0;
 	while (file_seg) {
-		seg = (file_seg > FIRMWARE_SEGMENT) ?
-					FIRMWARE_SEGMENT : file_seg;
+		seg = (file_seg > FIRMWARE_SEGMENT) ? FIRMWARE_SEGMENT :
+						      file_seg;
 		/*
 		 * Check if the content of the segment is all 0xff.
 		 * If yes, there is no need to write.
@@ -218,7 +218,7 @@ static bool image_auto_write(uint32_t offset, uint8_t *buffer,
 			data_buf[2] = 0;
 			data_buf[3] = flash_index;
 			opr_write_chunk((uint8_t *)data_buf, MONITOR_HDR_ADDR,
-						sizeof(data_buf));
+					sizeof(data_buf));
 			if (opr_execute_return(MONITOR_ADDR) != true)
 				return false;
 			file_seg -= seg;
@@ -242,10 +242,11 @@ static bool image_auto_write(uint32_t offset, uint8_t *buffer,
 		data_buf[3] = flash_index;
 		/* Write the monitor header to RAM */
 		opr_write_chunk((uint8_t *)data_buf, MONITOR_HDR_ADDR,
-						sizeof(data_buf));
+				sizeof(data_buf));
 		while (chunk_remain) {
 			count = (chunk_remain > MAX_RW_DATA_SIZE) ?
-						MAX_RW_DATA_SIZE : chunk_remain;
+					MAX_RW_DATA_SIZE :
+					chunk_remain;
 			if (opr_write_chunk(buffer, addr, count) != true)
 				return false;
 
@@ -281,13 +282,13 @@ static bool get_flash_size(uint32_t *flash_size)
 
 	for (i = 0; i < ARRAY_SIZE(chip_info); i++) {
 		if (chip_info[i].device_id == dev_id &&
-				chip_info[i].chip_id == chip_id) {
+		    chip_info[i].chip_id == chip_id) {
 			*flash_size = chip_info[i].flash_size;
 			return true;
 		}
 	}
-	printf("Unknown NPCX device ID:0x%02x chip ID:0x%02x\n",
-				dev_id, chip_id);
+	printf("Unknown NPCX device ID:0x%02x chip ID:0x%02x\n", dev_id,
+	       chip_id);
 
 	return false;
 }
@@ -315,8 +316,8 @@ static uint8_t *read_input_file(uint32_t size, const char *file_name)
 	}
 	input_fp = fopen(file_name, "r");
 	if (!input_fp) {
-		display_color_msg(FAIL,
-			"ERROR: cannot open file %s\n", file_name);
+		display_color_msg(FAIL, "ERROR: cannot open file %s\n",
+				  file_name);
 		free(buffer);
 		return NULL;
 	}
@@ -396,9 +397,11 @@ int main(int argc, char *argv[])
 		 * It might fail for garbage data drainage from H1, or
 		 * for timeout due to unstable data transfer yet.
 		 */
-		display_color_msg(FAIL,
+		display_color_msg(
+			FAIL,
 			"Host/Device synchronization failed, error = %d,"
-			" fail count = %d\n", sr, sync_cnt);
+			" fail count = %d\n",
+			sr, sync_cnt);
 	}
 	if (sync_cnt > MAX_SYNC_RETRIES)
 		exit_uart_app(EC_SYNC_ERR);
@@ -412,8 +415,8 @@ int main(int argc, char *argv[])
 		if (!buffer)
 			exit_uart_app(EC_FILE_ERR);
 
-		printf("Write file %s at %d with %d bytes\n",
-					file_name, flash_offset, size);
+		printf("Write file %s at %d with %d bytes\n", file_name,
+		       flash_offset, size);
 		if (image_auto_write(flash_offset, buffer, size)) {
 			printf("Flash Done.\n");
 			free(buffer);
@@ -429,7 +432,7 @@ int main(int argc, char *argv[])
 		if (get_flash_size(&flash_size)) {
 			printf("Read %d bytes from flash...\n", flash_size);
 			opr_read_mem(file_name, NPCX_FLASH_BASE_ADDR,
-					flash_size);
+				     flash_size);
 			exit_uart_app(EC_OK);
 		}
 
@@ -506,20 +509,13 @@ int main(int argc, char *argv[])
  */
 
 static const struct option long_opts[] = {
-	{"version",         0, 0, 'v'},
-	{"help",            0, 0, 'h'},
-	{"quiet",           0, 0, 'q'},
-	{"console",         0, 0, 'c'},
-	{"auto",            0, 0, 'A'},
-	{"read-flash",      0, 0, 'r'},
-	{"baudrate",        1, 0, 'b'},
-	{"opr",             1, 0, 'o'},
-	{"port",            1, 0, 'p'},
-	{"file",            1, 0, 'f'},
-	{"addr",            1, 0, 'a'},
-	{"size",            1, 0, 's'},
-	{"offset",          1, 0, 'O'},
-	{NULL,       0, 0, 0}
+	{ "version", 0, 0, 'v' },  { "help", 0, 0, 'h' },
+	{ "quiet", 0, 0, 'q' },	   { "console", 0, 0, 'c' },
+	{ "auto", 0, 0, 'A' },	   { "read-flash", 0, 0, 'r' },
+	{ "baudrate", 1, 0, 'b' }, { "opr", 1, 0, 'o' },
+	{ "port", 1, 0, 'p' },	   { "file", 1, 0, 'f' },
+	{ "addr", 1, 0, 'a' },	   { "size", 1, 0, 's' },
+	{ "offset", 1, 0, 'O' },   { NULL, 0, 0, 0 }
 };
 
 static const char *short_opts = "vhqcArb:o:p:f:a:s:O:?";
@@ -528,9 +524,8 @@ static void param_parse_cmd_line(int argc, char *argv[])
 {
 	int opt, idx;
 
-	while ((opt = getopt_long(argc, argv, short_opts,
-				long_opts, &idx)) != -1) {
-
+	while ((opt = getopt_long(argc, argv, short_opts, long_opts, &idx)) !=
+	       -1) {
 		switch (opt) {
 		case 'v':
 			main_print_version();
@@ -558,23 +553,23 @@ static void param_parse_cmd_line(int argc, char *argv[])
 			break;
 		case 'o':
 			strncpy(opr_name, optarg, sizeof(opr_name));
-			opr_name[sizeof(opr_name)-1] = '\0';
+			opr_name[sizeof(opr_name) - 1] = '\0';
 			break;
 		case 'p':
 			strncpy(port_name, optarg, sizeof(port_name));
-			port_name[sizeof(port_name)-1] = '\0';
+			port_name[sizeof(port_name) - 1] = '\0';
 			break;
 		case 'f':
 			strncpy(file_name, optarg, sizeof(file_name));
-			file_name[sizeof(file_name)-1] = '\0';
+			file_name[sizeof(file_name) - 1] = '\0';
 			break;
 		case 'a':
 			strncpy(addr_str, optarg, sizeof(addr_str));
-			addr_str[sizeof(addr_str)-1] = '\0';
+			addr_str[sizeof(addr_str) - 1] = '\0';
 			break;
 		case 's':
 			strncpy(size_str, optarg, sizeof(size_str));
-			size_str[sizeof(size_str)-1] = '\0';
+			size_str[sizeof(size_str) - 1] = '\0';
 			break;
 		case 'O':
 			flash_offset = strtol(optarg, NULL, 0);
@@ -595,12 +590,12 @@ static void param_parse_cmd_line(int argc, char *argv[])
  */
 static void param_check_opr_num(const char *opr)
 {
-
 	if ((strcasecmp(opr, OPR_WRITE_MEM) != 0) &&
-		(strcasecmp(opr, OPR_READ_MEM) != 0) &&
-		(strcasecmp(opr, OPR_EXECUTE_EXIT) != 0) &&
-		(strcasecmp(opr, OPR_EXECUTE_CONT) != 0)) {
-		display_color_msg(FAIL,
+	    (strcasecmp(opr, OPR_READ_MEM) != 0) &&
+	    (strcasecmp(opr, OPR_EXECUTE_EXIT) != 0) &&
+	    (strcasecmp(opr, OPR_EXECUTE_CONT) != 0)) {
+		display_color_msg(
+			FAIL,
 			"ERROR: Operation %s not supported, Supported "
 			"operations are %s, %s, %s & %s\n",
 			opr, OPR_WRITE_MEM, OPR_READ_MEM, OPR_EXECUTE_EXIT,
@@ -624,12 +619,11 @@ static uint32_t param_get_file_size(const char *file_name)
 	struct stat fst;
 
 	if (stat(file_name, &fst)) {
-		display_color_msg(FAIL,
-				"ERROR: Could not stat file [%s]\n", file_name);
+		display_color_msg(FAIL, "ERROR: Could not stat file [%s]\n",
+				  file_name);
 		return 0;
 	}
 	return fst.st_size;
-
 }
 
 /*---------------------------------------------------------------------------
@@ -653,7 +647,7 @@ static uint32_t param_get_str_size(char *string)
 	/* Verify string is non-NULL */
 	if ((string == NULL) || (strlen(string) == 0)) {
 		display_color_msg(FAIL,
-			"ERROR: Zero length input string provided\n");
+				  "ERROR: Zero length input string provided\n");
 		return 0;
 	}
 
@@ -692,14 +686,14 @@ static void tool_usage(void)
 	printf("  -c, --console        - Print data to console (default is "
 	       "print to file)\n");
 	printf("  -p, --port <name>    - Serial port name (default is %s)\n",
-		DEFAULT_PORT_NAME);
+	       DEFAULT_PORT_NAME);
 	printf("  -b, --baudrate <num> - COM Port baud-rate (default is %d)\n",
-		DEFAULT_BAUD_RATE);
+	       DEFAULT_BAUD_RATE);
 	printf("  -A, --auto           - Enable auto mode. (default is off)\n");
 	printf("  -O, --offset <num>   - With --auto, assign the offset of");
 	printf(" flash where the image to be written.\n");
 	printf("  -r, --read-flash     - With --file=<file>, Read the whole"
-			" flash content and write it to <file>.\n");
+	       " flash content and write it to <file>.\n");
 	printf("\n");
 	printf("Operation specific switches:\n");
 	printf("  -o, --opr   <name>   - Operation number (see list below)\n");
diff --git a/util/uut/main.h b/util/uut/main.h
index 2885e7368a..43c80dddae 100644
--- a/util/uut/main.h
+++ b/util/uut/main.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,11 +21,11 @@
 #define BASE_HEXADECIMAL 16
 
 /* Verbose control messages display */
-#define DISPLAY_MSG(msg) \
-{                        \
-	if (verbose)         \
-		printf msg;      \
-}
+#define DISPLAY_MSG(msg)            \
+	{                           \
+		if (verbose)        \
+			printf msg; \
+	}
 
 #define SUCCESS true
 #define FAIL false
diff --git a/util/uut/opr.c b/util/uut/opr.c
index 5c979afb16..8ad60bd3d4 100644
--- a/util/uut/opr.c
+++ b/util/uut/opr.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -34,7 +34,7 @@ int port_handle = INVALID_HANDLE_VALUE;
  *---------------------------------------------------------------------------
  */
 #define MAX_PORT_NAME_SIZE 32
-#define OPR_TIMEOUT 10L		 /* 10  seconds */
+#define OPR_TIMEOUT 10L /* 10  seconds */
 #define FLASH_ERASE_TIMEOUT 120L /* 120 seconds */
 
 #define STS_MSG_MIN_SIZE 8
@@ -119,9 +119,8 @@ bool opr_open_port(const char *port_name, struct comport_fields port_cfg)
 
 	if (port_handle <= 0) {
 		display_color_msg(FAIL, "\nERROR: COM Port failed to open.\n");
-		DISPLAY_MSG(
-			("Please select the right serial port or check if "
-			 "other serial\n"));
+		DISPLAY_MSG(("Please select the right serial port or check if "
+			     "other serial\n"));
 		DISPLAY_MSG(("communication applications are opened.\n"));
 		return false;
 	}
@@ -150,13 +149,13 @@ bool opr_write_chunk(uint8_t *buffer, uint32_t addr, uint32_t size)
 	struct command_node wr_cmd_buf;
 
 	if (size > MAX_RW_DATA_SIZE) {
-		display_color_msg(FAIL,
-			"ERROR: Block cannot exceed %d\n", MAX_RW_DATA_SIZE);
+		display_color_msg(FAIL, "ERROR: Block cannot exceed %d\n",
+				  MAX_RW_DATA_SIZE);
 	}
 	/* Initialize response size */
 	wr_cmd_buf.resp_size = 1;
-	cmd_create_write(addr, size, buffer,
-			wr_cmd_buf.cmd, &wr_cmd_buf.cmd_size);
+	cmd_create_write(addr, size, buffer, wr_cmd_buf.cmd,
+			 &wr_cmd_buf.cmd_size);
 	return opr_send_cmds(&wr_cmd_buf, 1);
 }
 
@@ -179,13 +178,13 @@ bool opr_read_chunk(uint8_t *buffer, uint32_t addr, uint32_t size)
 	struct command_node rd_cmd_buf;
 
 	if (size > MAX_RW_DATA_SIZE) {
-		display_color_msg(FAIL,
-			"ERROR: Block cannot exceed %d\n", MAX_RW_DATA_SIZE);
+		display_color_msg(FAIL, "ERROR: Block cannot exceed %d\n",
+				  MAX_RW_DATA_SIZE);
 		return false;
 	}
 
-	cmd_create_read(addr, ((uint8_t)size - 1),
-					rd_cmd_buf.cmd, &rd_cmd_buf.cmd_size);
+	cmd_create_read(addr, ((uint8_t)size - 1), rd_cmd_buf.cmd,
+			&rd_cmd_buf.cmd_size);
 	rd_cmd_buf.resp_size = size + 3;
 	if (opr_send_cmds(&rd_cmd_buf, 1)) {
 		if (resp_buf[0] == (uint8_t)(UFPP_READ_CMD)) {
@@ -228,7 +227,7 @@ void opr_write_mem(uint8_t *buffer, uint32_t addr, uint32_t size)
 	wr_cmd_buf.resp_size = 1;
 
 	DISPLAY_MSG(("Writing [%d] bytes in [%d] packets\n", size,
-		((size + (block_size - 1)) / block_size)));
+		     ((size + (block_size - 1)) / block_size)));
 
 	/* Read first token from string */
 	if (console)
@@ -248,21 +247,21 @@ void opr_write_mem(uint8_t *buffer, uint32_t addr, uint32_t size)
 			/* Prepare the next iteration */
 			token = strtok(NULL, seps);
 		}
-		write_size = (size_remain > block_size) ?
-					block_size : size_remain;
+		write_size = (size_remain > block_size) ? block_size :
+							  size_remain;
 		if (console) {
 			cmd_create_write(cur_addr, write_size, data_buf,
-					wr_cmd_buf.cmd, &wr_cmd_buf.cmd_size);
+					 wr_cmd_buf.cmd, &wr_cmd_buf.cmd_size);
 		} else {
 			cmd_create_write(cur_addr, write_size, buffer,
-					wr_cmd_buf.cmd, &wr_cmd_buf.cmd_size);
+					 wr_cmd_buf.cmd, &wr_cmd_buf.cmd_size);
 			buffer += write_size;
 		}
 		if (opr_send_cmds(&wr_cmd_buf, 1) != true)
 			break;
 
 		cmd_disp_write(resp_buf, write_size, cmd_idx,
-			((size + (block_size - 1)) / block_size));
+			       ((size + (block_size - 1)) / block_size));
 		cur_addr += write_size;
 		size_remain -= write_size;
 		cmd_idx++;
@@ -302,7 +301,8 @@ void opr_read_mem(char *output, uint32_t addr, uint32_t size)
 		output_file_id = fopen(output, "w+b");
 
 		if (output_file_id == NULL) {
-			display_color_msg(FAIL,
+			display_color_msg(
+				FAIL,
 				"ERROR: could not open output file [%s]\n",
 				output);
 			return;
@@ -310,21 +310,22 @@ void opr_read_mem(char *output, uint32_t addr, uint32_t size)
 	}
 
 	DISPLAY_MSG(("Reading [%d] bytes in [%d] packets\n", size,
-		((size + (MAX_RW_DATA_SIZE - 1)) / MAX_RW_DATA_SIZE)));
+		     ((size + (MAX_RW_DATA_SIZE - 1)) / MAX_RW_DATA_SIZE)));
 
 	for (cur_addr = addr; cur_addr < (addr + size);
-		cur_addr += MAX_RW_DATA_SIZE) {
+	     cur_addr += MAX_RW_DATA_SIZE) {
 		bytes_left = (uint32_t)(addr + size - cur_addr);
 		read_size = MIN(bytes_left, MAX_RW_DATA_SIZE);
 
 		cmd_create_read(cur_addr, ((uint8_t)read_size - 1),
-					rd_cmd_buf.cmd, &rd_cmd_buf.cmd_size);
+				rd_cmd_buf.cmd, &rd_cmd_buf.cmd_size);
 		rd_cmd_buf.resp_size = read_size + 3;
 
 		if (opr_send_cmds(&rd_cmd_buf, 1) != true)
 			break;
 
-		cmd_disp_read(resp_buf, read_size, cmd_idx,
+		cmd_disp_read(
+			resp_buf, read_size, cmd_idx,
 			((size + (MAX_RW_DATA_SIZE - 1)) / MAX_RW_DATA_SIZE));
 
 		if (console)
@@ -386,8 +387,8 @@ bool opr_execute_return(uint32_t addr)
 	 * Check the response command code is UFPP_FCALL_RSLT_CMD and
 	 * the return value from monitor is 0x03. (program finish and verify ok)
 	 */
-	if (resp_buf[1] != (uint8_t)(UFPP_FCALL_RSLT_CMD)
-					|| resp_buf[2] != 0x03)
+	if (resp_buf[1] != (uint8_t)(UFPP_FCALL_RSLT_CMD) ||
+	    resp_buf[2] != 0x03)
 		return false;
 	return true;
 }
@@ -473,29 +474,31 @@ bool opr_scan_baudrate(void)
 		sr = opr_check_sync(baud);
 		step = (baud * BR_BIG_STEP) / 100;
 		if (sr == SR_OK) {
-			printf("SR_OK: Baud rate - %d, resp_buf - 0x%x\n",
-				baud, resp_buf[0]);
+			printf("SR_OK: Baud rate - %d, resp_buf - 0x%x\n", baud,
+			       resp_buf[0]);
 			synched = true;
 			step = (baud * BR_SMALL_STEP) / 100;
 		} else if (sr == SR_WRONG_DATA) {
 			printf("SR_WRONG_DATA: Baud rate - %d, resp_buf - "
-			       "0x%x\n", baud, resp_buf[0]);
+			       "0x%x\n",
+			       baud, resp_buf[0]);
 			data_received = true;
 			step = (baud * BR_MEDIUM_STEP) / 100;
 		} else if (sr == SR_TIMEOUT) {
 			printf("SR_TIMEOUT: Baud rate - %d, resp_buf - 0x%x\n",
-				baud, resp_buf[0]);
+			       baud, resp_buf[0]);
 
 			if (synched || data_received)
 				break;
 		} else if (sr == SR_ERROR) {
 			printf("SR_ERROR: Baud rate - %d, resp_buf - 0x%x\n",
-				baud, resp_buf[0]);
+			       baud, resp_buf[0]);
 			if (synched || data_received)
 				break;
 		} else
 			printf("Unknown error code: Baud rate - %d, resp_buf - "
-				"0x%x\n", baud, resp_buf[0]);
+			       "0x%x\n",
+			       baud, resp_buf[0]);
 	}
 
 	return true;
@@ -524,7 +527,7 @@ static bool opr_send_cmds(struct command_node *cmd_buf, uint32_t cmd_num)
 
 	for (cmd = 0; cmd < cmd_num; cmd++, cur_cmd++) {
 		if (com_port_write_bin(port_handle, cur_cmd->cmd,
-						cur_cmd->cmd_size) == true) {
+				       cur_cmd->cmd_size) == true) {
 			time(&start);
 
 			do {
@@ -533,15 +536,17 @@ static bool opr_send_cmds(struct command_node *cmd_buf, uint32_t cmd_num)
 			} while ((read < cur_cmd->resp_size) &&
 				 (elapsed_time <= OPR_TIMEOUT));
 			com_port_read_bin(port_handle, resp_buf,
-							cur_cmd->resp_size);
+					  cur_cmd->resp_size);
 
 			if (elapsed_time > OPR_TIMEOUT)
-				display_color_msg(FAIL,
+				display_color_msg(
+					FAIL,
 					"ERROR: [%d] bytes received for read, "
 					"[%d] bytes are expected\n",
 					read, cur_cmd->resp_size);
 		} else {
-			display_color_msg(FAIL,
+			display_color_msg(
+				FAIL,
 				"ERROR: Failed to send Command number %d\n",
 				cmd);
 			return false;
diff --git a/util/uut/opr.h b/util/uut/opr.h
index 3b166f0c7e..820639d6a1 100644
--- a/util/uut/opr.h
+++ b/util/uut/opr.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Copyright 2018 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,16 +15,16 @@
  */
 
 /* Baud rate scan steps: */
-#define BR_BIG_STEP 20       /* in percents from current baud rate */
-#define BR_MEDIUM_STEP 10    /* in percents from current baud rate */
-#define BR_SMALL_STEP 1      /* in percents from current baud rate */
-#define BR_MIN_STEP 5        /* in absolute baud rate units */
-#define BR_LOW_LIMIT 400     /* Automatic BR detection starts at this value */
+#define BR_BIG_STEP 20 /* in percents from current baud rate */
+#define BR_MEDIUM_STEP 10 /* in percents from current baud rate */
+#define BR_SMALL_STEP 1 /* in percents from current baud rate */
+#define BR_MIN_STEP 5 /* in absolute baud rate units */
+#define BR_LOW_LIMIT 400 /* Automatic BR detection starts at this value */
 #define BR_HIGH_LIMIT 150000 /* Automatic BR detection ends at this value */
 
-#define OPR_WRITE_MEM "wr"      /* Write To Memory/Flash */
-#define OPR_READ_MEM "rd"       /* Read From Memory/Flash */
-#define OPR_EXECUTE_EXIT "go"   /* Execute a non-return code */
+#define OPR_WRITE_MEM "wr" /* Write To Memory/Flash */
+#define OPR_READ_MEM "rd" /* Read From Memory/Flash */
+#define OPR_EXECUTE_EXIT "go" /* Execute a non-return code */
 #define OPR_EXECUTE_CONT "call" /* Execute returnable code */
 
 enum sync_result {
diff --git a/util/zephyr_to_resultdb.py b/util/zephyr_to_resultdb.py
new file mode 100755
index 0000000000..48bfe151e4
--- /dev/null
+++ b/util/zephyr_to_resultdb.py
@@ -0,0 +1,173 @@
+#!/usr/bin/env python3
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+""" Upload twister results to ResultDB
+
+    Usage:
+    $ rdb stream -new -realm chromium:public -- ./util/zephyr_to_resultdb.py
+      --results=twister-out/twister.json --upload=True
+"""
+
+import argparse
+import base64
+import json
+import os
+
+import requests  # pylint: disable=import-error
+
+
+def translate_status(status):
+    """Translates ZTEST status to ResultDB status"""
+    ret_status = "SKIP"
+
+    if status == "passed":
+        ret_status = "PASS"
+    elif status == "failed":
+        ret_status = "FAIL"
+    elif status in ["skipped", "filtered"]:
+        ret_status = "SKIP"
+
+    return ret_status
+
+
+def translate_expected(status):
+    """Translates ZTEST status to ResultDB expected"""
+    flag = False
+
+    if status in ["passed", "filtered"]:
+        flag = True
+
+    return flag
+
+
+def translate_duration(testcase):
+    """Translates ZTEST execution_time to ResultDB duration"""
+    time = testcase.get("execution_time")
+    if not time:
+        return None
+
+    return f"{time}ms"
+
+
+def testcase_summary(testcase):
+    """Translates ZTEST testcase to ResultDB summaryHtml"""
+    html = "<p>None</p>"
+
+    if (
+        "log" in testcase
+        or "reason" in testcase
+        or translate_status(testcase["status"]) == "SKIP"
+    ):
+        html = (
+            '<p><text-artifact artifact-id="artifact-content-in-request"></p>'
+        )
+
+    return html
+
+
+def testcase_artifact(testcase):
+    """Translates ZTEST testcase to ResultDB artifact"""
+    artifact = "Unknown"
+
+    if "log" in testcase and testcase["log"]:
+        artifact = testcase["log"]
+    elif "reason" in testcase and testcase["reason"]:
+        artifact = testcase["reason"]
+    elif testcase["status"] == "filtered":
+        artifact = "filtered"
+    elif testcase["status"] == "skipped":
+        artifact = "skipped"
+
+    return base64.b64encode(artifact.encode())
+
+
+def testcase_to_result(testsuite, testcase):
+    """Translates ZTEST testcase to ResultDB format"""
+    result = {
+        "testId": testcase["identifier"],
+        "status": translate_status(testcase["status"]),
+        "expected": translate_expected(testcase["status"]),
+        "summaryHtml": testcase_summary(testcase),
+        "artifacts": {
+            "artifact-content-in-request": {
+                "contents": testcase_artifact(testcase),
+            }
+        },
+        # TODO(b/239952573) Add all test configs as tags
+        "tags": [
+            {"key": "category", "value": "ChromeOS/EC"},
+            {"key": "platform", "value": testsuite["platform"]},
+        ],
+        "duration": translate_duration(testcase),
+        "testMetadata": {"name": testcase["identifier"]},
+    }
+
+    return result
+
+
+def json_to_resultdb(result_file):
+    """Translates Twister json test report to ResultDB format"""
+    with open(result_file) as file:
+        data = json.load(file)
+        results = []
+
+        for testsuite in data["testsuites"]:
+            for testcase in testsuite["testcases"]:
+                if testcase["status"]:
+                    results.append(testcase_to_result(testsuite, testcase))
+
+        file.close()
+
+    return results
+
+
+class BytesEncoder(json.JSONEncoder):
+    """Encoder for ResultDB format"""
+
+    def default(self, obj):
+        if isinstance(obj, bytes):
+            return obj.decode("utf-8")
+        return json.JSONEncoder.default(self, obj)
+
+
+def upload_results(results):
+    """Upload results to ResultDB"""
+    with open(os.environ["LUCI_CONTEXT"]) as file:
+        sink = json.load(file)["result_sink"]
+
+    # Uploads all test results at once.
+    res = requests.post(
+        url="http://%s/prpc/luci.resultsink.v1.Sink/ReportTestResults"
+        % sink["address"],
+        headers={
+            "Content-Type": "application/json",
+            "Accept": "application/json",
+            "Authorization": "ResultSink %s" % sink["auth_token"],
+        },
+        data=json.dumps({"testResults": results}, cls=BytesEncoder),
+    )
+    res.raise_for_status()
+
+
+def main():
+    """main"""
+    # Set up argument parser.
+    parser = argparse.ArgumentParser(
+        description=("Upload Zephyr Twister test results to ResultDB")
+    )
+    parser.add_argument("--results")
+    parser.add_argument("--upload", default=False)
+    args = parser.parse_args()
+
+    if args.results:
+        print("Converting:", args.results)
+        rdb_results = json_to_resultdb(args.results)
+        if args.upload:
+            upload_results(rdb_results)
+    else:
+        raise Exception("Missing test result file for conversion")
+
+
+if __name__ == "__main__":
+    main()
diff --git a/util/zephyr_to_resultdb.py.vpython3 b/util/zephyr_to_resultdb.py.vpython3
new file mode 100644
index 0000000000..9a086bffdf
--- /dev/null
+++ b/util/zephyr_to_resultdb.py.vpython3
@@ -0,0 +1,18 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# vpython VirtualEnv protobuf for "zephyr_to_resultdb.py".
+#
+# Dependencies needed to run zephyr_to_resultdb.py in
+#   infra/recipes/recipes/build_firmware.py
+#
+# For info on this file, see:
+# https://chromium.googlesource.com/infra/infra/+/HEAD/doc/users/vpython.md#available-wheels
+#
+
+python_version: "3.8"
+wheel: <
+  name: "infra/python/wheels/requests-py2_py3"
+  version: "version:2.13.0"
+>
diff --git a/zephyr/.pylintrc b/zephyr/.pylintrc
index 817f2453b3..066e00da9d 100644
--- a/zephyr/.pylintrc
+++ b/zephyr/.pylintrc
@@ -1,6 +1,20 @@
 [MASTER]
 init-hook='import sys; sys.path.extend(["zephyr/zmake"])'
 
+# cros lint doesn't inherit the pylintrc from the parent dir.
+# These settings are copied from platform/ec/pylintrc
 [MESSAGES CONTROL]
 
-disable=fixme
+disable=
+    bad-continuation,
+    bad-whitespace,
+    # These have nothing to do with black, they are just annoying
+    fixme,
+    too-many-arguments,
+    too-many-statements,
+    too-many-branches,
+    too-many-locals
+
+[format]
+
+string-quote=double
diff --git a/zephyr/CMakeLists.txt b/zephyr/CMakeLists.txt
index 451406c8b3..7a71823bc8 100644
--- a/zephyr/CMakeLists.txt
+++ b/zephyr/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -29,6 +29,19 @@ if(DEFINED ZMAKE_INCLUDE_DIR)
   zephyr_include_directories("${ZMAKE_INCLUDE_DIR}")
 endif()
 
+# When CONFIG_ASSERT is enabled, the __FILE__ macro may add full paths into the
+# read-only strings. This wastes space and can cause non-reproducible builds.
+# When the compiler supports it, replace common path prefixes with static
+# strings.
+
+# PLATFORM_EC points to the build directory, which symlinks to the actual
+# source. ZEPHYR_CURRENT_CMAKE_DIR points to the actual source directory
+# containing this file.  Set the PLATFORM_EC_SRC to the parent.
+# Replace the paths of the both the build and source directories with "EC_BASE".
+cmake_path(GET ZEPHYR_CURRENT_CMAKE_DIR PARENT_PATH PLATFORM_EC_SRC)
+zephyr_cc_option(-fmacro-prefix-map=${PLATFORM_EC}=EC_BASE)
+zephyr_cc_option(-fmacro-prefix-map=${PLATFORM_EC_SRC}=EC_BASE)
+
 if(DEFINED CONFIG_PLATFORM_EC)
   # Add CHROMIUM_EC definition, which is used by ec_commands.h to
   # determine that the header is being compiled for the EC instead of
@@ -65,6 +78,8 @@ endif()
 
 # Set extra compiler flags.
 zephyr_cc_option(-mno-unaligned-access)
+zephyr_cc_option(-fno-PIC)
+
 if (DEFINED CONFIG_RISCV)
   zephyr_cc_option(-fsanitize=integer-divide-by-zero)
   zephyr_cc_option(-fsanitize-undefined-trap-on-error)
@@ -90,12 +105,12 @@ set(ZEPHYR_CURRENT_LIBRARY app)
 # Custom function that ensures the include path is always updated for both
 # libraries.
 function(cros_ec_library_include_directories)
-  target_include_directories(app PRIVATE ${ARGN})
+  target_include_directories(app PUBLIC ${ARGN})
   target_include_directories(ec_shim PRIVATE ${ARGN})
 endfunction()
 function(cros_ec_library_include_directories_ifdef feature_toggle)
   if(${${feature_toggle}})
-    target_include_directories(app PRIVATE ${ARGN})
+    target_include_directories(app PUBLIC ${ARGN})
     target_include_directories(ec_shim PRIVATE ${ARGN})
   endif()
 endfunction()
@@ -132,7 +147,11 @@ configure_file(gcov.tmpl.sh ${CMAKE_BINARY_DIR}/gcov.sh)
 # included here, sorted by filename. This is common functionality which is
 # supported by all boards and emulators (including unit tests) using the shim
 # layer.
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC "${PLATFORM_EC}/common/base32.c"
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC
+                                                # TODO(b/237712836): Remove once
+                                                # Zephyr's libc has strcasecmp.
+                                                "${PLATFORM_EC}/builtin/stdlib.c"
+                                                "${PLATFORM_EC}/common/base32.c"
                                                 "${PLATFORM_EC}/common/console_output.c"
                                                 "${PLATFORM_EC}/common/ec_features.c"
                                                 "${PLATFORM_EC}/common/gpio_commands.c"
@@ -173,9 +192,11 @@ zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ACCELGYRO_ICM42607
                                                 "${PLATFORM_EC}/driver/accelgyro_icm42607.c")
 zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSO
                                                 "${PLATFORM_EC}/driver/accelgyro_lsm6dso.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSM
+                                                "${PLATFORM_EC}/driver/accelgyro_lsm6dsm.c")
 zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ACCEL_FIFO
                                                 "${PLATFORM_EC}/common/motion_sense_fifo.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ADC_CMD
+zephyr_library_sources_ifdef(CONFIG_ADC
                                                 "${PLATFORM_EC}/common/adc.c")
 zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ALS_TCS3400
                                                 "${PLATFORM_EC}/driver/als_tcs3400.c")
@@ -183,6 +204,10 @@ zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ALS_CM32183
                                                 "${PLATFORM_EC}/driver/als_cm32183.c")
 zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ACPI
                                                 "${PLATFORM_EC}/common/acpi.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_AMD_SB_RMI
+						"${PLATFORM_EC}/driver/sb_rmi.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_AMD_STT
+						"${PLATFORM_EC}/driver/amd_stt.c")
 zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_BACKLIGHT_LID
                                                 "${PLATFORM_EC}/common/backlight_lid.c")
 zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_BATTERY
@@ -228,6 +253,8 @@ zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGE_RAMP_HW
 zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGE_RAMP_SW
                                                 "${PLATFORM_EC}/common/charge_ramp.c"
                                                 "${PLATFORM_EC}/common/charge_ramp_sw.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CPS8100
+                                                "${PLATFORM_EC}/driver/wpc/cps8100.c")
 zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_OCPC
                                                 "${PLATFORM_EC}/common/ocpc.c")
 
@@ -319,6 +346,8 @@ zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_MOTIONSENSE
                                                 "${PLATFORM_EC}/common/motion_sense.c")
 zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_MP2964
                                                 "${PLATFORM_EC}/driver/mp2964.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_PERIPHERAL_CHARGER
+                                                "${PLATFORM_EC}/common/peripheral_charger.c")
 zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_PORT80
                                                 "${PLATFORM_EC}/common/port80.c")
 zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_POWER_BUTTON
@@ -475,11 +504,7 @@ zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_TCPM_CCGXXF
                                                 "${PLATFORM_EC}/driver/tcpm/ccgxxf.c")
 zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_TCPM_NCT38XX
                                                 "${PLATFORM_EC}/driver/tcpm/nct38xx.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8751
-                                                "${PLATFORM_EC}/driver/tcpm/ps8xxx.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8805
-                                                "${PLATFORM_EC}/driver/tcpm/ps8xxx.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8815
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8XXX
                                                 "${PLATFORM_EC}/driver/tcpm/ps8xxx.c")
 zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_TCPM_RAA489000
                                                 "${PLATFORM_EC}/driver/tcpm/raa489000.c")
@@ -535,8 +560,6 @@ zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_MAX695X_SEVEN_SEGMENT_DISPLAY
 						"${PLATFORM_EC}/driver/led/max695x.c")
 zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LED_DRIVER_TLC59116F
                                                 "${PLATFORM_EC}/driver/led/tlc59116f.c")
-zephyr_library_sources_ifdef(CONFIG_AP_PWRSEQ_HOST_SLEEP
-						"${PLATFORM_EC}/power/host_sleep.c")
 # Switch to ec_shim library for all Zephyr sources
 set(ZEPHYR_CURRENT_LIBRARY ec_shim)
 
@@ -544,4 +567,24 @@ add_subdirectory(linker)
 add_subdirectory("app")
 add_subdirectory("drivers")
 add_subdirectory("emul")
+add_subdirectory("fake")
+add_subdirectory("mock")
 add_subdirectory_ifdef(CONFIG_PLATFORM_EC "shim")
+
+# Use external script to generate the ec_version.h header and add as
+# a dependency to the EC application library.
+add_custom_target(
+  ec_version_header
+  VERBATIM COMMAND
+  "PYTHONPATH=${PLATFORM_EC}/zephyr/zmake/" ${PYTHON_EXECUTABLE}
+  "${PLATFORM_EC}/zephyr/zmake/zephyr_build_tools/generate_ec_version.py"
+  "${CMAKE_CURRENT_BINARY_DIR}/include/ec_version.h"
+  "--base" "${ZEPHYR_BASE}"
+  "--name" "${CMAKE_PROJECT_NAME}"
+  "--module" "${ZEPHYR_MODULES}"
+  ${EXTRA_EC_VERSION_FLAGS}
+)
+add_dependencies(app ec_version_header)
+
+# Include the directory containing the generated header.
+zephyr_include_directories("${CMAKE_CURRENT_BINARY_DIR}/include")
diff --git a/zephyr/DIR_METADATA b/zephyr/DIR_METADATA
new file mode 100644
index 0000000000..c7bfb79d83
--- /dev/null
+++ b/zephyr/DIR_METADATA
@@ -0,0 +1,9 @@
+# Metadata information for this directory.
+#
+# For more information on DIR_METADATA files, see:
+#   https://source.chromium.org/chromium/infra/infra/+/main:go/src/infra/tools/dirmd/README.md
+#
+# For the schema of this file, see Metadata message:
+#   https://source.chromium.org/chromium/infra/infra/+/main:go/src/infra/tools/dirmd/proto/dir_metadata.proto
+
+team_email: "zephyr-task-force@google.com"
diff --git a/zephyr/Kconfig b/zephyr/Kconfig
index 6e17b9ed13..62b9fac62c 100644
--- a/zephyr/Kconfig
+++ b/zephyr/Kconfig
@@ -1,10 +1,12 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 rsource "app/Kconfig"
 rsource "drivers/Kconfig"
 rsource "emul/Kconfig"
+rsource "fake/Kconfig"
+rsource "mock/Kconfig"
 rsource "subsys/Kconfig"
 
 if ZTEST
@@ -72,6 +74,7 @@ rsource "Kconfig.throttle_ap"
 rsource "Kconfig.usba"
 rsource "Kconfig.usbc"
 rsource "Kconfig.watchdog"
+rsource "Kconfig.wireless_charger"
 
 # Define PLATFORM_EC_... options to enable EC features. Each Kconfig should be
 # matched by a line in zephyr/shim/include/config_chip.h which #defines the
@@ -327,7 +330,7 @@ config PLATFORM_EC_EXTPOWER_GPIO
 	  Enable shimming the extpower_gpio module, which provides
 	  GPIO-based external power presence detection features.  The
 	  project should define a GPIO pin named GPIO_AC_PRESENT, with
-	  extpower_interrupt configured as the handler in gpio_map.h.
+	  extpower_interrupt configured as the handler.
 
 config PLATFORM_EC_FLASH_CROS
 	bool
@@ -429,7 +432,7 @@ config PLATFORM_EC_LID_SWITCH
 	  behaviour. For example, when the lid is opened, the device may
 	  automatically power on.
 
-	  This requires a GPIO named GPIO_LID_OPEN to be defined in gpio_map.h.
+	  This requires a GPIO named GPIO_LID_OPEN to be defined or aliased.
 
 config PLATFORM_EC_MKBP_INPUT_DEVICES
 	bool "Input devices via MKBP"
@@ -490,23 +493,6 @@ config PLATFORM_EC_MKBP_HOST_EVENT_WAKEUP_MASK
                           HOST_EVENT_AC_CONNECTED)>;
       The host events are defined in dt-bindings/wake_mask_event_defines.h
 
-config PLATFORM_EC_MPU
-	bool "Support Memory-Protection Unit (MPU)"
-	depends on CPU_CORTEX_M
-	select ARM_MPU
-	default y
-	help
-	  This enables support a Memory-Protection Unit which can limit access
-	  to certain areas of memory. This can be used to protect code or data
-	  from being written to improve security or to find bugs.
-
-	  It causes any code in the iram.text section to be protected when
-	  system jump is disabled (see system_disable_jump()). It also stops
-	  execution of the image that is not currently being executed (read-only
-	  or read-write). If internal storage is used, this is achieved by not
-	  allowing code execution in that area. For external storage, it
-	  disallows loading any code into RAM.
-
 config PLATFORM_EC_PANIC
 	bool "Panic output"
 	default y
@@ -540,7 +526,7 @@ config PLATFORM_EC_POWER_BUTTON
 	  commands in platform/ec.  This is used to implement the Chromium OS
 	  shutdown sequence.
 
-	  This requires a GPIO named GPIO_POWER_BUTTON_L in gpio_map.h.
+	  This requires a GPIO named GPIO_POWER_BUTTON_L.
 
 config PLATFORM_EC_PWM_HC
 	bool
@@ -548,11 +534,10 @@ config PLATFORM_EC_PWM_HC
 	  Enable the PWM (Pulse Width Modulation) host command support. This
 	  implements EC_CMD_PWM_SET_DUTY and EC_CMD_PWM_GET_DUTY.
 
-DT_COMPAT_CROS_EC_DISPLIGHT := cros-ec,displight
-
 config PLATFORM_EC_PWM_DISPLIGHT
 	bool "PWM display backlight"
-	default $(dt_compat_enabled,$(DT_COMPAT_CROS_EC_DISPLIGHT))
+	default y
+	depends on DT_HAS_CROS_EC_DISPLIGHT_ENABLED
 	select PLATFORM_EC_PWM_HC
 	help
 	  Enables display backlight controlled by a PWM signal connected
diff --git a/zephyr/Kconfig.accelgyro_bmi b/zephyr/Kconfig.accelgyro_bmi
index bb8239f6d8..e08ba08838 100644
--- a/zephyr/Kconfig.accelgyro_bmi
+++ b/zephyr/Kconfig.accelgyro_bmi
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/Kconfig.accelgyro_icm b/zephyr/Kconfig.accelgyro_icm
index 2bee9184b5..a8b52c0d38 100644
--- a/zephyr/Kconfig.accelgyro_icm
+++ b/zephyr/Kconfig.accelgyro_icm
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/Kconfig.adc b/zephyr/Kconfig.adc
index a1e3bd63eb..40ec1e4e89 100644
--- a/zephyr/Kconfig.adc
+++ b/zephyr/Kconfig.adc
@@ -1,17 +1,9 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
-menuconfig PLATFORM_EC_ADC
-	bool "ADC shim"
-	default n if ARCH_POSIX
-	default y
-	imply ADC
-	help
-	  Enable compilation of the EC ADC module. Once enabled, it is
-	  possible to call platform/ec adc_read_channel() function.
-
-if PLATFORM_EC_ADC
+# Note - CONFIG_ADC is defined in upstream Zephyr
+if ADC
 
 # Chromium EC provides it's own "adc" command.  Disable the Zephyr
 # built-in ADC shell command.
@@ -59,4 +51,4 @@ config PLATFORM_EC_ADC_CHANNELS_RUNTIME_CONFIG
 	  Without this, multiple EC images would need to be installed
 	  depending on the board.
 
-endif # PLATFORM_EC_ADC
+endif # ADC
diff --git a/zephyr/Kconfig.ap_power b/zephyr/Kconfig.ap_power
index 03c92759f0..4e3b4139aa 100644
--- a/zephyr/Kconfig.ap_power
+++ b/zephyr/Kconfig.ap_power
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/Kconfig.battery b/zephyr/Kconfig.battery
index 7b3f20da38..92bce6b618 100644
--- a/zephyr/Kconfig.battery
+++ b/zephyr/Kconfig.battery
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -57,19 +57,17 @@ config PLATFORM_EC_BATTERY_PRESENT_GPIO
 	  GPIO should read low if the battery is present, high if absent.
 
 	  The GPIO is hard-coded to GPIO_BATT_PRES_ODL so you should define this
-	  in the device tree and GPIO map. The convention is to use the signal
+	  in the device tree. The convention is to use the signal
 	  name from schematic as both the node name and label for the GPIO. For
 	  example:
 
 	    /* gpio.dts */
 	    ec_batt_pres_odl {
 	    	gpios = <&gpioe 5 GPIO_INPUT>;
-	    	label = "EC_BATT_PRES_ODL";
+	    	enum-name = "EC_BATT_PRES_ODL";
+		alias = "GPIO_BATT_PRES_ODL";
 	    };
 
-	    /* gpio_map.h */
-	    #define GPIO_BATT_PRES_ODL		NAMED_GPIO(ec_batt_pres_odl)
-
 endchoice # PLATFORM_EC_BATTERY_PRESENT_MODE
 
 config PLATFORM_EC_USE_BATTERY_DEVICE_CHEMISTRY
diff --git a/zephyr/Kconfig.board_version b/zephyr/Kconfig.board_version
index e24957764d..7b7581d90a 100644
--- a/zephyr/Kconfig.board_version
+++ b/zephyr/Kconfig.board_version
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/Kconfig.cbi b/zephyr/Kconfig.cbi
index 962392e56c..a2be51375e 100644
--- a/zephyr/Kconfig.cbi
+++ b/zephyr/Kconfig.cbi
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/Kconfig.charger b/zephyr/Kconfig.charger
index fe2dd9f408..baa751f138 100644
--- a/zephyr/Kconfig.charger
+++ b/zephyr/Kconfig.charger
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/Kconfig.chargesplash b/zephyr/Kconfig.chargesplash
index 83a914e497..c23b51f2a7 100644
--- a/zephyr/Kconfig.chargesplash
+++ b/zephyr/Kconfig.chargesplash
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/Kconfig.console b/zephyr/Kconfig.console
index 8f0241a4d9..74de199067 100644
--- a/zephyr/Kconfig.console
+++ b/zephyr/Kconfig.console
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -66,3 +66,25 @@ menuconfig PLATFORM_EC_CONSOLE_DEBUG
 	  Write all zephyr_print() messages to printk() also. Not recommended
 	  outside of tests.
 
+
+config PLATFORM_EC_LOG_BACKEND_CONSOLE_BUFFER
+	bool "Logging backend for the console buffer"
+	depends on PLATFORM_EC_HOSTCMD_CONSOLE
+	select LOG_OUTPUT
+	help
+	  Enable the logging backend for the console buffer.
+
+	  This will copy messages sent to the zephyr logging subsystem
+	  to the EC console buffer. This allows the AP to access the
+	  log messages with the console host command.
+
+config PLATFORM_EC_LOG_BACKEND_CONSOLE_BUFFER_TMP_BUF_SIZE
+	int "Size of temporary buffer used by console buffer logging backend"
+	default 128 if LOG_MODE_DEFERRED
+	default 1
+	depends on PLATFORM_EC_LOG_BACKEND_CONSOLE_BUFFER
+	help
+	  The size of the temporary buffer used by the console buffer backend.
+	  The logging subsystem will buffer up to this many bytes before calling
+	  the backend in deferred logging mode. Ideally this will be large
+	  enough to fit an entire log line.
diff --git a/zephyr/Kconfig.console_cmd_mem b/zephyr/Kconfig.console_cmd_mem
index 4b69cc1778..9be465b488 100644
--- a/zephyr/Kconfig.console_cmd_mem
+++ b/zephyr/Kconfig.console_cmd_mem
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/Kconfig.debug_assert b/zephyr/Kconfig.debug_assert
index ad94f525f6..c05dceae02 100644
--- a/zephyr/Kconfig.debug_assert
+++ b/zephyr/Kconfig.debug_assert
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/Kconfig.defaults b/zephyr/Kconfig.defaults
index a92971b3c7..ded7516748 100644
--- a/zephyr/Kconfig.defaults
+++ b/zephyr/Kconfig.defaults
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -9,6 +9,10 @@
 config TIMESLICING
 	default n
 
+config LOG
+	default y
+	imply LOG_DEFAULT_MINIMAL
+
 config GPIO_EMUL
 	default y if ARCH_POSIX
 
@@ -21,4 +25,13 @@ config THREAD_MAX_NAME_LEN
 config SHELL_PROMPT_UART
 	default "ec:~$ "
 
+config SHELL_THREAD_PRIORITY_OVERRIDE
+	default y
+
+config SHELL_THREAD_PRIORITY
+	default 12  # track EC_SHELL_PRIO
+
+config EXTRA_EXCEPTION_INFO
+	default y if ARCH_HAS_EXTRA_EXCEPTION_INFO
+
 orsource "Kconfig.defaults-$(ARCH)"
diff --git a/zephyr/Kconfig.defaults-arm b/zephyr/Kconfig.defaults-arm
index 4dddf87304..2d55aaf7d4 100644
--- a/zephyr/Kconfig.defaults-arm
+++ b/zephyr/Kconfig.defaults-arm
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/Kconfig.espi b/zephyr/Kconfig.espi
index 60ea99def7..3e7210362c 100644
--- a/zephyr/Kconfig.espi
+++ b/zephyr/Kconfig.espi
@@ -1,28 +1,28 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 if PLATFORM_EC_HOST_INTERFACE_ESPI
 
-config PLATFORM_EC_ESPI_VW_SLP_S3
+config PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S3
 	bool "SLP_S3 is an eSPI virtual wire instead of a GPIO"
 	help
 	  For power sequencing, use an eSPI virtual wire instead of
-	  defining GPIO_PCH_SLP_S3 in gpio_map.h.
+	  defining GPIO_PCH_SLP_S3 in the GPIO device tree.
 
-config PLATFORM_EC_ESPI_VW_SLP_S4
+config PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S4
 	bool "SLP_S4 is an eSPI virtual wire instead of a GPIO"
 	help
 	  For power sequencing, use an eSPI virtual wire instead of
-	  defining GPIO_PCH_SLP_S4 in gpio_map.h.
+	  defining GPIO_PCH_SLP_S4 in the GPIO device tree.
 
-config PLATFORM_EC_ESPI_VW_SLP_S5
+config PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S5
 	bool "SLP_S5 is an eSPI virtual wire instead of an alias for SLP_S4"
 	help
 	  For power sequencing, use an eSPI virtual wire to read the SLP_S5 line,
 	  as opposed to merging it into the same net as SLP_S4.
 
-config PLATFORM_EC_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST
+config PLATFORM_EC_HOST_INTERFACE_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST
 	bool "Reset SLP VW signals on eSPI reset"
 	help
 	  Enable this config to reset SLP* VW when eSPI_RST is asserted
@@ -31,7 +31,7 @@ config PLATFORM_EC_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST
 	  maintain these pins' states per request. Note that this is
 	  currently unimplemented for Zephyr. Please see b/183148073.
 
-config PLATFORM_EC_ESPI_DEFAULT_VW_WIDTH_US
+config PLATFORM_EC_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US
 	int "Virtual wire pulse width (microseconds)"
 	default 65
 	help
diff --git a/zephyr/Kconfig.flash b/zephyr/Kconfig.flash
index 8611c8731b..b8b176e987 100644
--- a/zephyr/Kconfig.flash
+++ b/zephyr/Kconfig.flash
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -18,6 +18,7 @@ config PLATFORM_EC_SPI_FLASH_REGS
 config PLATFORM_EC_CONSOLE_CMD_CHARGEN
 	bool "Console command: chargen"
 	depends on UART_INTERRUPT_DRIVEN
+	default y
 	help
 	  Enables the "chargen" console command, which sends a continuous
 	  stream of characters to the EC console.
diff --git a/zephyr/Kconfig.header b/zephyr/Kconfig.header
index 931d7dbaf1..02f9ecc1a7 100644
--- a/zephyr/Kconfig.header
+++ b/zephyr/Kconfig.header
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/Kconfig.host_interface b/zephyr/Kconfig.host_interface
index 95fe6a0543..41ff23970f 100644
--- a/zephyr/Kconfig.host_interface
+++ b/zephyr/Kconfig.host_interface
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/Kconfig.i2c b/zephyr/Kconfig.i2c
index 23ccf88bd0..0187409b31 100644
--- a/zephyr/Kconfig.i2c
+++ b/zephyr/Kconfig.i2c
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/Kconfig.init_priority b/zephyr/Kconfig.init_priority
index c974bb4d8f..42d03e8794 100644
--- a/zephyr/Kconfig.init_priority
+++ b/zephyr/Kconfig.init_priority
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/Kconfig.ioex b/zephyr/Kconfig.ioex
index 24a946777d..e9bb8065e1 100644
--- a/zephyr/Kconfig.ioex
+++ b/zephyr/Kconfig.ioex
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/Kconfig.keyboard b/zephyr/Kconfig.keyboard
index 8bcc32af8e..f7c0df77ee 100644
--- a/zephyr/Kconfig.keyboard
+++ b/zephyr/Kconfig.keyboard
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -99,15 +99,15 @@ config PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI2
 	bool "Forces KSI2 to be asserted"
 	help
 	  Enable this if KSI2 is stuck 'asserted' for all scan columns if the
-	  power button is held. We must be aware of this case in order to
-	  correctly handle recovery-mode key combinations.
+	  power button is held. This applies if the refresh key is on KSI2.
+	  The GSC will assert this row for all columns during a recovery boot.
 
 config PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI3
 	bool "Forces KSI3 to be asserted"
 	help
 	  Enable this if KSI3 is stuck 'asserted' for all scan columns if the
-	  power button is held. We must be aware of this case in order to
-	  correctly handle recovery-mode key combinations.
+	  power button is held. This applies if the refresh key is on KSI3.
+	  The GSC will assert this row for all columns during a recovery boot.
 
 endchoice # PLATFORM_EC_KEYBOARD_PWRBTN_MODE
 
@@ -145,8 +145,8 @@ config PLATFORM_EC_VOLUME_BUTTONS
 	  These are buttons controlled by GPIOs and are not part of the keyboard
 	  matrix.
 
-	  Your board must define GPIO_VOLUME_UP_L and GPIO_VOLUME_DOWN_L in
-	  gpio_map.h
+	  Your board must define GPIO_VOLUME_UP_L and GPIO_VOLUME_DOWN_L as
+	  GPIOs names or as aliases in the GPIO devicetree configuration.
 
 config PLATFORM_EC_BUTTONS_RUNTIME_CONFIG
 	bool "Enable buttons runtime configuration"
@@ -180,11 +180,10 @@ config PLATFORM_EC_CONSOLE_CMD_KEYBOARD
 	    kblog	- Print or toggle keyboard event log (current disabled)
 	    typematic	- Get/set typematic delays
 
-DT_COMPAT_CROS_EC_KBLIGHT_PWM := cros-ec,kblight-pwm
-
 config PLATFORM_EC_PWM_KBLIGHT
 	bool "PWM keyboard backlight"
-	default $(dt_compat_enabled,$(DT_COMPAT_CROS_EC_KBLIGHT_PWM))
+	default y
+	depends on DT_HAS_CROS_EC_KBLIGHT_PWM_ENABLED
 	select PLATFORM_EC_PWM_HC
 	help
 	  Enables a PWM-controlled keyboard backlight controlled by a PWM signal
@@ -197,6 +196,16 @@ config PLATFORM_EC_KBLIGHT_ENABLE_PIN
 	  Enables control of the keyboard backlight through a GPIO enable and
 	  disable pin.  This pin must be defined as GPIO_EN_KEYBOARD_BACKLIGHT.
 
+config PLATFORM_EC_KEYBOARD_STRICT_DEBOUNCE
+	bool "Keyboard strict debouncer"
+	help
+	  Enable strict debouncer. A strict debouncer waits until debounce
+	  is done before registering key up/down while a non-strict debouncer
+	  registers a key up/down as soon as a key is pressed or released.
+	  If a strict debouncer is used, it's recommended to set
+	  debounce_down_us and debounce_up_us to an equal value. This guarantees
+	  key events are registered in the order the keys are pressed.
+
 endif # PLATFORM_EC_KEYBOARD
 
 
diff --git a/zephyr/Kconfig.led b/zephyr/Kconfig.led
index 03f2ebed56..d3d50ccc56 100644
--- a/zephyr/Kconfig.led
+++ b/zephyr/Kconfig.led
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/Kconfig.led_dt b/zephyr/Kconfig.led_dt
index 16b5842c06..25993802a3 100644
--- a/zephyr/Kconfig.led_dt
+++ b/zephyr/Kconfig.led_dt
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/Kconfig.mkbp_event b/zephyr/Kconfig.mkbp_event
index e24cf370d2..28d791bbdc 100644
--- a/zephyr/Kconfig.mkbp_event
+++ b/zephyr/Kconfig.mkbp_event
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -14,7 +14,7 @@ config PLATFORM_EC_MKBP_USE_GPIO
     bool "Use GPIO"
     help
       Select to send MKBP events via GPIO. You should define GPIO_EC_INT_L
-      in gpio_map.h as output from the EC. The GPIO is used to indicate an
+      as a GPIO output from the EC. The GPIO is used to indicate an
       event is ready for serving by the AP.
 
 config PLATFORM_EC_MKBP_USE_HOST_EVENT
diff --git a/zephyr/Kconfig.motionsense b/zephyr/Kconfig.motionsense
index abfdacc5be..7cf991918b 100644
--- a/zephyr/Kconfig.motionsense
+++ b/zephyr/Kconfig.motionsense
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/Kconfig.panic b/zephyr/Kconfig.panic
index 322aaee25d..c402fc1e70 100644
--- a/zephyr/Kconfig.panic
+++ b/zephyr/Kconfig.panic
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -40,4 +40,11 @@ config PLATFORM_EC_STACKOVERFLOW
 	  This can be used to check that stack-overflow detection is working
 	  as expected.
 
+config PLATFORM_EC_DEBUG_ASSERT_BRIEF
+	bool "Enable brief panic messages"
+	default n
+	help
+	  On assertion failure, prints only the file name and the line number.
+	  Boards typically define this option in order to reduce image size.
+
 endif # PLATFORM_EC_PANIC
diff --git a/zephyr/Kconfig.pd b/zephyr/Kconfig.pd
index e1ca76a298..57d348007d 100644
--- a/zephyr/Kconfig.pd
+++ b/zephyr/Kconfig.pd
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -76,6 +76,16 @@ config PLATFORM_EC_USB_PD_DEBUG_LEVEL
 	  The meaning of each level depends on the module in question, but
 	  the maximum available level is 3.
 
+config PLATFORM_EC_USB_PD_INITIAL_DEBUG_LEVEL
+	int "Initial debug level to use"
+	default 1
+	help
+	  Sets the initial value of the debug level to use, while
+	  still allowing the debug level to be changed using 'pd dump'.
+	  A value of 0 will initially disable debug logging, and values 1
+	  through to 3 will increase the level of debug logging.
+	  If this config is not set, the default level will be set to 1.
+
 config PLATFORM_EC_USB_PD_5V_EN_CUSTOM
 	bool "Custom method of detecting VBUS"
 	help
@@ -343,6 +353,27 @@ config PLATFORM_EC_USB_PD_TEMP_SENSOR
 	 one temperature. But, Chromebooks can have multiple temperature sensors.
 	 This option selects which temperature sensor is used for USB PD.
 
+config PLATFORM_EC_USB_PD_SHORT_PRESS_MAX_MS
+	int "Time limit in ms for short presses with a USB PD power button"
+	default 4000
+	help
+	 USB PD supports power buttons over USB-C using button press and button
+	 release alerts. How a chromeOS device responds depends on whether the button
+	 press is considered short or long. This config is used to set the short press
+	 time limit in ms. Any press shorter will be a short press and any press
+	 longer will either be a long press or invalid.
+
+config PLATFORM_EC_USB_PD_LONG_PRESS_MAX_MS
+	int "Time limit in ms for valid presses with a USB PD power button"
+	default 8000
+	help
+	 USB PD supports power buttons over USB-C using button press and button
+	 release alerts. If a USB PD partner sends a press but never a release alert,
+	 the EC should time out while waiting for the release and return to an idle
+	 state. This value sets how long the EC waits for a release alert from the
+	 partner in ms. Any press longer than this will not be considered a valid USB
+	 PD button press.
+
 endif  # PLATFORM_EC_USB_POWER_DELIVERY
 
 endif # PLATFORM_EC_USBC
diff --git a/zephyr/Kconfig.pd_console_cmd b/zephyr/Kconfig.pd_console_cmd
index bc654f3274..bba130718f 100644
--- a/zephyr/Kconfig.pd_console_cmd
+++ b/zephyr/Kconfig.pd_console_cmd
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/Kconfig.pd_discharge b/zephyr/Kconfig.pd_discharge
index 3631beffa7..6d2bd58b82 100644
--- a/zephyr/Kconfig.pd_discharge
+++ b/zephyr/Kconfig.pd_discharge
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/Kconfig.pd_frs b/zephyr/Kconfig.pd_frs
index 8883542c56..5faf16b05c 100644
--- a/zephyr/Kconfig.pd_frs
+++ b/zephyr/Kconfig.pd_frs
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/Kconfig.pd_int_shared b/zephyr/Kconfig.pd_int_shared
index 6f90d2e3e9..8385496b62 100644
--- a/zephyr/Kconfig.pd_int_shared
+++ b/zephyr/Kconfig.pd_int_shared
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/Kconfig.pd_meas_vbus b/zephyr/Kconfig.pd_meas_vbus
index cffe35985c..1484ad6979 100644
--- a/zephyr/Kconfig.pd_meas_vbus
+++ b/zephyr/Kconfig.pd_meas_vbus
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/Kconfig.pd_usbc_device_type b/zephyr/Kconfig.pd_usbc_device_type
index 4bf1a2d442..62797128cd 100644
--- a/zephyr/Kconfig.pd_usbc_device_type
+++ b/zephyr/Kconfig.pd_usbc_device_type
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/Kconfig.pd_vbus_detection b/zephyr/Kconfig.pd_vbus_detection
index 019eca654a..8e25d973eb 100644
--- a/zephyr/Kconfig.pd_vbus_detection
+++ b/zephyr/Kconfig.pd_vbus_detection
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/Kconfig.pmic b/zephyr/Kconfig.pmic
index dc79305439..831767c546 100644
--- a/zephyr/Kconfig.pmic
+++ b/zephyr/Kconfig.pmic
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/Kconfig.port80 b/zephyr/Kconfig.port80
index adeea08d20..a03d8295f7 100644
--- a/zephyr/Kconfig.port80
+++ b/zephyr/Kconfig.port80
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -11,4 +11,12 @@ config PLATFORM_EC_PORT80_4_BYTE
 	  codes when AP sends 4-byte Port80 codes via eSPI PUT_IOWR_SHORT
 	  protocol in a single transaction.
 
+config PLATFORM_EC_PORT80_QUIET
+	bool "Do not log Port80 codes when they are received"
+	help
+	  Enable this config to avoid logging the entire buffer of
+	  Port80 codes as each are received.
+	  The history is still available via the 'port80' EC command.
+	  Enabling this will reduce the logging overhead during AP startup.
+
 endif # PLATFORM_EC_HOST_INTERFACE_ESPI
diff --git a/zephyr/Kconfig.powerseq b/zephyr/Kconfig.powerseq
index f0db496082..e7c0891ab4 100644
--- a/zephyr/Kconfig.powerseq
+++ b/zephyr/Kconfig.powerseq
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -126,12 +126,12 @@ config PLATFORM_EC_POWERSEQ_RTC_RESET
 	bool "Board has an RTC reset"
 	help
 	  This project has a gpio named GPIO_PCH_RTCRST defined in
-	  gpio_map.h, which can be used to reset the AP's RTC when set
-	  high.
+	  the GPIO configuration, which can be used to reset the AP's RTC when
+	  set high.
 
 config PLATFORM_EC_POWERSEQ_S4
 	bool "Advertise S4 residency"
-	depends on PLATFORM_EC_ESPI_VW_SLP_S5
+	depends on PLATFORM_HOST_INTERFACE_EC_HOST_INTERFACE_ESPI_VW_SLP_S5
 	default y if AP_X86_INTEL_TGL
 	default y if AP_X86_INTEL_ADL
 	default y if AP_X86_INTEL_MTL
diff --git a/zephyr/Kconfig.ppc b/zephyr/Kconfig.ppc
index 9d0ff3b86c..06f78dcf01 100644
--- a/zephyr/Kconfig.ppc
+++ b/zephyr/Kconfig.ppc
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -89,6 +89,13 @@ config PLATFORM_EC_USBC_PPC_NX20P3483
 	  The NX20P3483 is a product with combined multiple power switches
 	  and a LDO for USB PD application.
 
+config PLATFORM_EC_USBC_NX20P348X_RCP_5VSRC_MASK_ENABLE
+	bool "NX20P3483 RCP 5VSRC MASK enable"
+	depends on PLATFORM_EC_USBC_PPC_NX20P3483
+	help
+	  The NX20P3483 is a product with 5V SRC reverse current protection
+	  mask enable and disable.
+
 config PLATFORM_EC_USBC_PPC_RT1739
 	bool "Richtek RT1739 Type-C Power Path Controller"
 	help
diff --git a/zephyr/Kconfig.retimer b/zephyr/Kconfig.retimer
index f328ffea17..8a460715cb 100644
--- a/zephyr/Kconfig.retimer
+++ b/zephyr/Kconfig.retimer
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/Kconfig.rtc b/zephyr/Kconfig.rtc
index 5f36893122..a157ffdc77 100644
--- a/zephyr/Kconfig.rtc
+++ b/zephyr/Kconfig.rtc
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/Kconfig.sensor_devices b/zephyr/Kconfig.sensor_devices
index 1c8e38ac6f..12f5951ff5 100644
--- a/zephyr/Kconfig.sensor_devices
+++ b/zephyr/Kconfig.sensor_devices
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -113,6 +113,13 @@ config PLATFORM_EC_ACCELGYRO_LSM6DSO
 	  The driver supports ST's LSM6DSO 3D digital accelerometer sensor.
 	  It allows measurements of acceleration in three perpendicular axes.
 
+config PLATFORM_EC_ACCELGYRO_LSM6DSM
+	bool "LSM6DSM Accelgyro Driver"
+	select PLATFORM_EC_STM_MEMS_COMMON
+	help
+	  The driver supports ST's LSM6DSM 3D digital accelerometer sensor.
+	  It allows measurements of acceleration in three perpendicular axes.
+
 config PLATFORM_EC_STM_MEMS_COMMON
 	bool
 	help
diff --git a/zephyr/Kconfig.stacks b/zephyr/Kconfig.stacks
index 519a827b7c..6d983a3d05 100644
--- a/zephyr/Kconfig.stacks
+++ b/zephyr/Kconfig.stacks
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/Kconfig.system b/zephyr/Kconfig.system
index c9b67a6ab7..5467bc7422 100644
--- a/zephyr/Kconfig.system
+++ b/zephyr/Kconfig.system
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -20,6 +20,8 @@ config PLATFORM_EC_CONSOLE_CMD_SYSINFO
 
 config PLATFORM_EC_HIBERNATE_PSL
 	bool "System hibernating with PSL (Power Switch Logic) mechanism"
+	default y
+	depends on DT_HAS_NUVOTON_NPCX_POWER_PSL_ENABLED
 	depends on SOC_FAMILY_NPCX
 	help
 	  Use PSL (Power Switch Logic) for hibernating. It turns off VCC power
diff --git a/zephyr/Kconfig.tasks b/zephyr/Kconfig.tasks
index d329150e22..0a3c24f1fa 100644
--- a/zephyr/Kconfig.tasks
+++ b/zephyr/Kconfig.tasks
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/Kconfig.tcpm b/zephyr/Kconfig.tcpm
index 1e7d52358a..4078f3f9be 100644
--- a/zephyr/Kconfig.tcpm
+++ b/zephyr/Kconfig.tcpm
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -49,15 +49,6 @@ config PLATFORM_EC_USB_PD_TCPM_ITE_ON_CHIP
 	  This is selected by the ITE USB Type-C drivers. It cannot be set
 	  otherwise, even in prj.conf
 
-config PLATFORM_EC_USB_PD_ITE_ACTIVE_PORT_COUNT
-	int "Number of ITE USB PD active ports"
-	depends on PLATFORM_EC_USB_PD_TCPM_ITE_ON_CHIP
-	default 1
-	help
-	  This sets the number of active USB Power Delivery (USB PD) ports
-	  in use on the ITE microcontroller. The active port usage should
-	  follow the order of ITE TCPC port index.
-
 config PLATFORM_EC_USB_PD_PPC
 	bool "Enable Power Path Control from PD"
 	default n
@@ -79,27 +70,6 @@ config PLATFORM_EC_USB_PD_TCPC_RUNTIME_CONFIG
 	  factory. Without this, multiple EC images would need to be installed
 	  depending on the board.
 
-config PLATFORM_EC_USB_PD_TCPM_MULTI_PS8XXX
-	bool "Support multiple PS8xxx devices"
-	help
-	  PS8XXX-series chips are all supported by a single driver. Enable
-	  this If a board with the same EC firmware is expected to support
-	  multiple products here. Then enable the required PS8xxx options
-	  below.
-
-	  In this case the board must provide a function to return the correct
-	  product ID actually used by a particular board:
-
-	     uint16_t board_get_ps8xxx_product_id(int port)
-
-	  Supported return values are:
-
-	     PS8705_PRODUCT_ID
-	     PS8751_PRODUCT_ID
-	     PS8755_PRODUCT_ID
-	     PS8805_PRODUCT_ID
-	     PS8815_PRODUCT_ID
-
 config PLATFORM_EC_USB_PD_TCPM_ANX7447
 	bool "Analogix ANX7447 USB-C Gen 2 Type-C Port Controller"
 	select PLATFORM_EC_USB_PD_TCPM_MUX
@@ -150,10 +120,63 @@ config PLATFORM_EC_USB_PD_TCPM_NCT38XX
 	  (TCPC). It incorporates a Power Delivery (PD) PHY with BMC encoding,
 	  Protocol logic and USB Type-C Configuration Channel (CC) logic.
 
+config PLATFORM_EC_USB_PD_TCPM_PS8XXX
+  bool
+  select PLATFORM_EC_USB_PD_TCPM_MUX
+  imply PLATFORM_EC_HOSTCMD_I2C_CONTROL
+  help
+    Enable the driver for PS8xxx active retimer/redrivers with integrated
+    USB Type-C Port Controller (TCPC) for USB Type-C Host and DisplayPort
+    applications. They support Power Delivery and the DisplayPort Alt Mode.
+
+    Support for specific devices in the driver (below) must also be enabled.
+
+if PLATFORM_EC_USB_PD_TCPM_PS8XXX
+config PLATFORM_EC_USB_PD_TCPM_MULTI_PS8XXX
+	bool "Support multiple PS8xxx devices"
+	help
+	  PS8XXX-series chips are all supported by a single driver. Enable
+	  this if a board with the same EC firmware is expected to support
+	  multiple products here.
+
+	  In this case the board must provide a function to return the correct
+	  product ID actually used by a particular board:
+
+	     uint16_t board_get_ps8xxx_product_id(int port)
+
+	  Supported return values are:
+
+	     PS8705_PRODUCT_ID
+	     PS8745_PRODUCT_ID
+	     PS8751_PRODUCT_ID
+	     PS8755_PRODUCT_ID
+	     PS8805_PRODUCT_ID
+	     PS8815_PRODUCT_ID
+endif # PLATFORM_EC_USB_PD_TCPM_PS8XXX
+
+config PLATFORM_EC_USB_PD_TCPM_PS8745
+	bool "Parade PS8745 USB-C Gen 2 Type-C Port Controller"
+	select PLATFORM_EC_USB_PD_TCPM_PS8XXX
+	help
+	  The Parade Technologies PS8815 is an active retiming/redriving
+	  (respectively for USB 3.1 Gen 2 / DisplayPort 1.4a HBR3) integrated
+	  with a USB Type-C Port Controller (TCPC) for USB Type-C Host and
+	  DisplayPort applications. It supports Power Delivery and the
+	  DisplayPort Alt Mode.
+
+if PLATFORM_EC_USB_PD_TCPM_PS8745
+config PLATFORM_EC_USB_PD_TCPM_PS8745_FORCE_ID
+	bool "Disambiguate PS8745 and PS8815"
+	default y
+	help
+	  Some firmware versions of the PS8745 report incorrect product and device
+	  IDs. Enable this option to check vendor-specific registers and force the
+	  correct device and product IDs.
+endif # PLATFORM_EC_USB_PD_TCPM_PS8745
+
 config PLATFORM_EC_USB_PD_TCPM_PS8751
 	bool "Parade PS8751 USB-C Gen 2 Type-C Port Controller"
-	select PLATFORM_EC_USB_PD_TCPM_MUX
-	imply PLATFORM_EC_HOSTCMD_I2C_CONTROL
+	select PLATFORM_EC_USB_PD_TCPM_PS8XXX
 	help
 	  The Parade Technologies PS8751 is a USB Type-C Port Controller (TCPC)
 	  for USB Type-C Host and DisplayPort applications. It supports
@@ -161,8 +184,7 @@ config PLATFORM_EC_USB_PD_TCPM_PS8751
 
 config PLATFORM_EC_USB_PD_TCPM_PS8805
 	bool "Parade PS8805 USB-C Gen 2 Type-C Port Controller"
-	select PLATFORM_EC_USB_PD_TCPM_MUX
-	imply PLATFORM_EC_HOSTCMD_I2C_CONTROL
+	select PLATFORM_EC_USB_PD_TCPM_PS8XXX
 	help
 	  The Parade Technologies PS8805 is an active retiming/redriving
 	  (respectively for USB 3.1 Gen 2 / DisplayPort 1.4a HBR3) integrated
@@ -182,8 +204,7 @@ endif # PLATFORM_EC_USB_PD_TCPM_PS8805
 
 config PLATFORM_EC_USB_PD_TCPM_PS8815
 	bool "Parade PS8815 USB-C Gen 2 Type-C Port Controller"
-	select PLATFORM_EC_USB_PD_TCPM_MUX
-	imply PLATFORM_EC_HOSTCMD_I2C_CONTROL
+	select PLATFORM_EC_USB_PD_TCPM_PS8XXX
 	help
 	  The Parade Technologies PS8815 is an active retiming/redriving
 	  (respectively for USB 3.1 Gen 2 / DisplayPort 1.4a HBR3) integrated
diff --git a/zephyr/Kconfig.temperature b/zephyr/Kconfig.temperature
index 1718a8dc53..09756663bc 100644
--- a/zephyr/Kconfig.temperature
+++ b/zephyr/Kconfig.temperature
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -33,7 +33,7 @@ config PLATFORM_EC_DPTF
 
 config PLATFORM_EC_THERMISTOR
 	bool "Thermistor support"
-	depends on PLATFORM_EC_ADC
+	depends on ADC
 	help
 	  Enables support for thermistors (resistor whose resistance is
 	  strongly dependent on temperature) as temperature-sensor type.
@@ -77,11 +77,10 @@ config PLATFORM_EC_TEMP_SENSOR_FIRST_READ_DELAY_MS
 
 endif # PLATFORM_EC_TEMP_SENSOR_FIRST_READ_DELAY
 
-DT_COMPAT_CROS_EC_FANS := cros-ec,fans
-
 config PLATFORM_EC_FAN
 	bool "Fan support"
-	default $(dt_compat_enabled,$(DT_COMPAT_CROS_EC_FANS))
+	default y
+	depends on DT_HAS_CROS_EC_FANS_ENABLED
 	help
 	  Enables support for fans. Allows periodic thermal task to
 	  automatically set the fan speed (control temperature).
@@ -101,3 +100,12 @@ config PLATFORM_EC_NUM_FANS
 	  for control through fan APIs.
 
 endif # PLATFORM_EC_FAN
+
+config PLATFORM_EC_FAN_BYPASS_SLOW_RESPONSE
+	bool "Enable fan slow response control mechanism"
+	default n
+	help
+	  A specific type of fan needs a longer time to output the TACH
+	  signal to EC after EC outputs the PWM signal to the fan.
+	  During this period, the driver will read two consecutive RPM = 0.
+	  In this case, don't step the PWM duty too aggressively.
diff --git a/zephyr/Kconfig.throttle_ap b/zephyr/Kconfig.throttle_ap
index ad5bfe9c77..e4dba3f2b4 100644
--- a/zephyr/Kconfig.throttle_ap
+++ b/zephyr/Kconfig.throttle_ap
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -58,4 +58,14 @@ config PLATFORM_EC_THROTTLE_AP_ON_BAT_LOW_VOLTAGE_THRESH
 	default 0
 endif
 
+config PLATFORM_EC_GPU_NVIDIA
+	bool "Nvidia GPU supports throttling"
+	default n
+	help
+	  Enable GPU throttling. When the GPU is throttled, a software (D-Notify)
+	  and a hardware throttle (GPIO_NVIDIA_GPU_ACOFF_ODL) are enabled. A
+	  hardware throttle will be automatically disabled after a fixed period
+	  of time but a software throttle may remain and keep changing as the
+	  situation changes.
+
 endif # PLATFORM_EC_THROTTLE_AP
diff --git a/zephyr/Kconfig.timer b/zephyr/Kconfig.timer
index 5b615961eb..0e19f2d551 100644
--- a/zephyr/Kconfig.timer
+++ b/zephyr/Kconfig.timer
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/Kconfig.usb_charger b/zephyr/Kconfig.usb_charger
index dd167dddae..1c58753412 100644
--- a/zephyr/Kconfig.usb_charger
+++ b/zephyr/Kconfig.usb_charger
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -16,10 +16,12 @@ config PLATFORM_EC_USB_CHARGER
 if PLATFORM_EC_USB_CHARGER
 
 config PLATFORM_EC_USB_CHARGER_SINGLE_TASK
-	bool "Run all charger code in a single task"
+	bool
 	default y
 	help
-	  Run all USB charger code in a single task rather than a task per port.
+	  Helper symbol use in the common EC code for Zephyr specific charger
+	  changes.
+
 
 config PLATFORM_EC_BC12_DETECT_DATA_ROLE_TRIGGER
 	bool
@@ -27,6 +29,14 @@ config PLATFORM_EC_BC12_DETECT_DATA_ROLE_TRIGGER
 	  This is a helper symbol that indicates the BC1.2 chip needs to be
 	  triggered on data role swaps in addition to VBUS changes.
 
+config PLATFORM_EC_BC12_CLIENT_MODE_ONLY_PI3USB9201
+	bool "Run as BC1.2 client while using PI3USB9201"
+	depends on PLATFORM_EC_BC12_DETECT_PI3USB9201
+	default n
+	help
+	  This is a helper symbol that indicates the PI3USB9201 will only
+	  advertise itself as a BC1.2 client, not a BC1.2 host.
+
 config PLATFORM_EC_BC12_DETECT_PI3USB9201
 	bool "Enable support for Pericom PI3USB9201"
 	select PLATFORM_EC_BC12_DETECT_DATA_ROLE_TRIGGER
diff --git a/zephyr/Kconfig.usb_mux b/zephyr/Kconfig.usb_mux
index a0db4f666d..6f4e31a2cf 100644
--- a/zephyr/Kconfig.usb_mux
+++ b/zephyr/Kconfig.usb_mux
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/Kconfig.usba b/zephyr/Kconfig.usba
index 380d277d2c..8abbe839f6 100644
--- a/zephyr/Kconfig.usba
+++ b/zephyr/Kconfig.usba
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -81,6 +81,30 @@ config PLATFORM_EC_USB_PORT_POWER_SMART_INVERTED
 	  is inverted, meaning a low value indicates a high current limit and a
 	  high value requests a low current limit.
 
+choice PLATFORM_EC_USBA_PORT_POWER_SMART_DEFAULT_MODE
+	prompt "Port power smart charging default mode"
+	default PLATFORM_EC_USB_PORT_POWER_SMART_DEFAULT_SDP
+
+config PLATFORM_EC_USB_PORT_POWER_SMART_DEFAULT_DISABLED
+	bool "Disabled"
+	help
+	  USB-A ports charging mode default set to disabled.
+	  If set, the USB-A charging mode is disabled.
+
+config PLATFORM_EC_USB_PORT_POWER_SMART_DEFAULT_SDP
+	bool "SDP"
+	help
+	  USB-A ports charging mode default set to Standard Downstream
+	  Port, USB 2.0 mode.
+
+config PLATFORM_EC_USB_PORT_POWER_SMART_DEFAULT_CDP
+	bool "CDP"
+	help
+	  USB-A ports charging mode default set to Charging Downstream
+	  Port, BC 1.2.
+
+endchoice
+
 endif # PLATFORM_EC_USB_PORT_POWER_SMART
 
 endif # PLATFORM_EC_USBA
diff --git a/zephyr/Kconfig.usbc b/zephyr/Kconfig.usbc
index cfee1172f4..37c57bcdd2 100644
--- a/zephyr/Kconfig.usbc
+++ b/zephyr/Kconfig.usbc
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -56,6 +56,7 @@ config PLATFORM_EC_USBC_OCP
 
 config PLATFORM_EC_USB_PID
 	hex "USB Product ID"
+	default 0
 	help
 	  Each platform (e.g. baseboard set) should have a single VID/PID
 	  combination. If there is a big enough change within a platform,
@@ -133,6 +134,16 @@ config PLATFORM_EC_CONSOLE_CMD_PPC_DUMP
 	  reference to the datasheet for the part this can help you figure out
 	  what is going on.
 
+config PLATFORM_EC_USBC_PPC_LOGGING
+	bool "Enable PPC Related logging"
+	depends on PLATFORM_EC_USBC_PPC
+	default y
+	help
+	  PPC drivers use two print functions for logging error messages
+	  (ppc_prints and ppc_err_prints). Setting this config adds the
+	  CPRINTS call to both of these function which will enable PPC
+	  related logging but increase EC image size.
+
 config PLATFORM_EC_USB_PD_TCPM_DRIVER_IT83XX
 	bool "Enable IT83XX driver"
 	depends on PLATFORM_EC_USB_PD_TCPM_ITE_ON_CHIP
@@ -163,4 +174,55 @@ config PLATFORM_EC_USB_PD_ONLY_FIXED_PDOS
 	  Ignore all non-fixed PDOs received from a src_caps message. Enable
 	  this for boards (like servo_v4) which only support FIXED PDO types.
 
+# Define power related settings here for now to allow projects to overwrite
+# them. Ideally they would be defined in the devicetree.
+config PLATFORM_EC_PD_OPERATING_POWER_MW
+	int "PD operating power in milliwatt"
+	default 15000
+	help
+	  Base configuration for PD power operating power value, which is used
+	  in PD negotiation. The final PD parameter used in negotiation is
+	  affected by PLATFORM_EC_PD_MAX_POWER_MW,
+	  PLATFORM_EC_PD_MAX_CURRENT_MA, and PLATFORM_EC_PD_MAX_VOLTAGE_MV.
+	  Increase this value is the system requires more than 15 watts to boot
+	  without a battery.
+
+config PLATFORM_EC_PD_MAX_POWER_MW
+	int "PD maximum power in milliwatt"
+	default 60000
+	help
+	  The maximum PD negotiated power for the system. The value should match
+	  with configured PLATFORM_EC_PD_MAX_CURRENT_MA and
+	  PLATFORM_EC_PD_MAX_VOLTAGE_MV.
+
+config PLATFORM_EC_PD_MAX_CURRENT_MA
+	int "PD maximum current in milliampere"
+	default 3000
+	help
+	  The maximum PD negotiated current for the system. The value should
+	  match with configured PLATFORM_EC_PD_MAX_POWER_MW and
+	  PLATFORM_EC_PD_MAX_VOLTAGE_MV.
+
+config PLATFORM_EC_PD_MAX_VOLTAGE_MV
+	int "PD maximum voltage in millivolt"
+	default 20000
+	help
+	  The maximum PD negotiated voltage for the system. The value should
+	  match with configured PLATFORM_EC_PD_MAX_POWER_MW and
+	  PLATFORM_EC_PD_MAX_CURRENT_MA.
+
+config PLATFORM_EC_PD_POWER_SUPPLY_TURN_ON_DELAY
+	int "Power supply turn on delay in us"
+	default 30000
+	help
+	  Each platform could have different power sequencing and transition
+	  timing for turning on the power on the PD port.
+
+config PLATFORM_EC_PD_POWER_SUPPLY_TURN_OFF_DELAY
+	int "Power supply turn off delay in us"
+	default 30000
+	help
+	  Each platform could have different power sequencing and transition
+	  timing for turning off the power on the PD port.
+
 endif  # PLATFORM_EC_USBC
diff --git a/zephyr/Kconfig.usbc_ss_mux b/zephyr/Kconfig.usbc_ss_mux
index 5578deaa6b..5d09bb3b02 100644
--- a/zephyr/Kconfig.usbc_ss_mux
+++ b/zephyr/Kconfig.usbc_ss_mux
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/Kconfig.watchdog b/zephyr/Kconfig.watchdog
index 57d93d7c39..f6c9002233 100644
--- a/zephyr/Kconfig.watchdog
+++ b/zephyr/Kconfig.watchdog
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/Kconfig.wireless_charger b/zephyr/Kconfig.wireless_charger
index e0608d0b57..c53bd6f7cc 100644
--- a/zephyr/Kconfig.wireless_charger
+++ b/zephyr/Kconfig.wireless_charger
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/README.md b/zephyr/README.md
index 1a4967a8b2..403cf7132e 100644
--- a/zephyr/README.md
+++ b/zephyr/README.md
@@ -25,9 +25,10 @@ See the piplines [here](https://gitlab.com/zephyr-ec/ec/-/pipelines).
 To test the cq builder script run these commands:
 
 ### firmware-zephyr-cq
+
 ```
 rm -rf /tmp/artifact_bundles /tmp/artifact_bundle_metadata \
-  ~/chromiumos/src/platform/ec/build
+ ~/chromiumos/src/platform/ec/build
 ( cd ~/chromiumos/src/platform/ec/zephyr ; \
 ./firmware_builder.py --metrics /tmp/metrics-build build && \
 ./firmware_builder.py --metrics /tmp/metrics-test test && \
@@ -39,6 +40,7 @@ ls -l /tmp/artifact_bundles/
 ```
 
 ### firmware-zephyr-cov-cq
+
 ```
 rm -rf /tmp/artifact_bundles-cov /tmp/artifact_bundle_metadata-cov \
   ~/chromiumos/src/platform/ec/build && \
diff --git a/zephyr/app/CMakeLists.txt b/zephyr/app/CMakeLists.txt
index dfc45f19f9..0365782963 100644
--- a/zephyr/app/CMakeLists.txt
+++ b/zephyr/app/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/app/Kconfig b/zephyr/app/Kconfig
index 3cac46afa7..7fb8c917ed 100644
--- a/zephyr/app/Kconfig
+++ b/zephyr/app/Kconfig
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/app/ec/CMakeLists.txt b/zephyr/app/ec/CMakeLists.txt
index fc7205462d..ac3d3fe3d2 100644
--- a/zephyr/app/ec/CMakeLists.txt
+++ b/zephyr/app/ec/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -7,3 +7,5 @@ zephyr_library_sources(ec_app_main.c)
 if(NOT DEFINED CONFIG_ZTEST)
     zephyr_library_sources(main_shim.c)
 endif()
+
+add_subdirectory(chip)
\ No newline at end of file
diff --git a/zephyr/app/ec/Kconfig b/zephyr/app/ec/Kconfig
index ebdeebfdf2..fbf6185740 100644
--- a/zephyr/app/ec/Kconfig
+++ b/zephyr/app/ec/Kconfig
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -34,6 +34,11 @@ config NUM_PREEMPT_PRIORITIES
 config SYSTEM_WORKQUEUE_PRIORITY
 	default 24
 
+# eSPI is chatty, so default to Error only
+choice ESPI_LOG_LEVEL_CHOICE
+	default ESPI_LOG_LEVEL_ERR
+endchoice
+
 config LTO
 	bool "Link Time Optimization (LTO)"
 	default y if !SOC_POSIX
diff --git a/zephyr/app/ec/chip/CMakeLists.txt b/zephyr/app/ec/chip/CMakeLists.txt
new file mode 100644
index 0000000000..e92dbc5d5d
--- /dev/null
+++ b/zephyr/app/ec/chip/CMakeLists.txt
@@ -0,0 +1 @@
+add_subdirectory_ifdef(CONFIG_RISCV riscv)
\ No newline at end of file
diff --git a/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec b/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec
index d05ad020e7..3baca08d04 100644
--- a/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec
+++ b/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -8,6 +8,10 @@
 
 if SOC_FAMILY_MEC
 
+# Enable MPU for ARM targets
+config ARM_MPU
+	default y
+
 # ADC
 config PLATFORM_EC_ADC_RESOLUTION
 	default 10
diff --git a/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec_mec172x b/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec_mec172x
index 9e37b6a534..bfcfeb8235 100644
--- a/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec_mec172x
+++ b/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec_mec172x
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx b/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx
index 2da9252775..17936ab05d 100644
--- a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx
+++ b/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -8,6 +8,10 @@
 
 if SOC_FAMILY_NPCX
 
+# Enable MPU for ARM targets
+config ARM_MPU
+	default y
+
 # Enable NPCX firmware header generator
 config NPCX_HEADER
 	default y
diff --git a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx7 b/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx7
index 37561f4dad..cb00db3345 100644
--- a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx7
+++ b/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx7
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx9 b/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx9
index aceec4f3ca..9c807a732c 100644
--- a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx9
+++ b/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx9
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/app/ec/chip/riscv/CMakeLists.txt b/zephyr/app/ec/chip/riscv/CMakeLists.txt
new file mode 100644
index 0000000000..b11c4e9a90
--- /dev/null
+++ b/zephyr/app/ec/chip/riscv/CMakeLists.txt
@@ -0,0 +1 @@
+add_subdirectory_ifdef(CONFIG_SOC_FAMILY_RISCV_ITE riscv-ite)
\ No newline at end of file
diff --git a/zephyr/app/ec/chip/riscv/riscv-ite/CMakeLists.txt b/zephyr/app/ec/chip/riscv/riscv-ite/CMakeLists.txt
new file mode 100644
index 0000000000..69608c33e3
--- /dev/null
+++ b/zephyr/app/ec/chip/riscv/riscv-ite/CMakeLists.txt
@@ -0,0 +1,3 @@
+if (CONFIG_ESPI_IT8XXX2)
+    zephyr_library_sources_ifdef(CONFIG_AP_POWER_CONTROL it8xxx2-espi.c)
+endif ()
\ No newline at end of file
diff --git a/zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2 b/zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2
index 809b9a6401..e0ea15c5b7 100644
--- a/zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2
+++ b/zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/app/ec/chip/riscv/riscv-ite/it8xxx2-espi.c b/zephyr/app/ec/chip/riscv/riscv-ite/it8xxx2-espi.c
new file mode 100644
index 0000000000..6109964cb9
--- /dev/null
+++ b/zephyr/app/ec/chip/riscv/riscv-ite/it8xxx2-espi.c
@@ -0,0 +1,63 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include <soc_espi.h>
+#include <ap_power/ap_power.h>
+#include <chipset.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(ec_chip_it8xxx2_espi, CONFIG_ESPI_LOG_LEVEL);
+
+/*
+ * When eSPI CS# is held low, it prevents IT8xxx2 from entering deep doze.
+ * To allow deep doze and save power, disable the eSPI inputs while the AP is
+ * in G3.
+ */
+static const struct device *const espi_device =
+	DEVICE_DT_GET(DT_NODELABEL(espi0));
+
+static void espi_enable_callback(struct ap_power_ev_callback *cb,
+				 struct ap_power_ev_data data)
+{
+	switch (data.event) {
+	case AP_POWER_INITIALIZED:
+		/* When AP power state becomes known, sync eSPI enable */
+		if (chipset_in_state(CHIPSET_STATE_HARD_OFF)) {
+			LOG_DBG("AP off; disabling eSPI");
+			espi_it8xxx2_enable_pad_ctrl(espi_device, false);
+		}
+		break;
+	case AP_POWER_PRE_INIT:
+	case AP_POWER_HARD_OFF: {
+		bool enable = data.event == AP_POWER_PRE_INIT;
+
+		LOG_DBG("%sabling eSPI in response to AP power event",
+			enable ? "en" : "dis");
+		espi_it8xxx2_enable_pad_ctrl(espi_device, enable);
+		break;
+	}
+	default:
+		__ASSERT(false, "%s: unhandled event: %d", __func__,
+			 data.event);
+		break;
+	}
+}
+
+static int init_espi_enable_callback(const struct device *unused)
+{
+	static struct ap_power_ev_callback cb;
+
+	if (!device_is_ready(espi_device))
+		k_oops();
+
+	ap_power_ev_init_callback(&cb, espi_enable_callback,
+				  AP_POWER_INITIALIZED | AP_POWER_PRE_INIT |
+					  AP_POWER_HARD_OFF);
+	ap_power_ev_add_callback(&cb);
+
+	return 0;
+}
+/* Should run before power sequencing init so INITIALIZED callback can fire */
+SYS_INIT(init_espi_enable_callback, APPLICATION, 0);
diff --git a/zephyr/app/ec/ec_app_main.c b/zephyr/app/ec/ec_app_main.c
index 12043a3c4a..9b13c8ab86 100644
--- a/zephyr/app/ec/ec_app_main.c
+++ b/zephyr/app/ec/ec_app_main.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,11 +6,11 @@
 #include <zephyr/kernel.h>
 #include <zephyr/sys/printk.h>
 #include <zephyr/shell/shell_uart.h>
-#include <zephyr/zephyr.h>
 
 #include "ap_power/ap_pwrseq.h"
 #include "button.h"
 #include "chipset.h"
+#include "cros_board_info.h"
 #include "ec_tasks.h"
 #include "hooks.h"
 #include "keyboard_scan.h"
@@ -38,7 +38,7 @@ void ec_app_main(void)
 	system_print_banner();
 
 	if (IS_ENABLED(CONFIG_PLATFORM_EC_WATCHDOG) &&
-		!IS_ENABLED(CONFIG_WDT_DISABLE_AT_BOOT)) {
+	    !IS_ENABLED(CONFIG_WDT_DISABLE_AT_BOOT)) {
 		watchdog_init();
 	}
 
@@ -77,6 +77,14 @@ void ec_app_main(void)
 	}
 
 	/*
+	 * If the EC has exclusive control over the CBI EEPROM WP signal, have
+	 * the EC set the WP if appropriate.  Note that once the WP is set, the
+	 * EC must be reset via EC_RST_ODL in order for the WP to become unset.
+	 */
+	if (IS_ENABLED(CONFIG_PLATFORM_EC_EEPROM_CBI_WP) && system_is_locked())
+		cbi_latch_eeprom_wp();
+
+	/*
 	 * Print the init time.  Not completely accurate because it can't take
 	 * into account the time before timer_init(), but it'll at least catch
 	 * the majority of the time.
diff --git a/zephyr/app/ec/include/ec_app_main.h b/zephyr/app/ec/include/ec_app_main.h
index a5043be84a..472e0b5c0e 100644
--- a/zephyr/app/ec/include/ec_app_main.h
+++ b/zephyr/app/ec/include/ec_app_main.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/app/ec/main_shim.c b/zephyr/app/ec/main_shim.c
index 7e54c83295..a14cff2dcb 100644
--- a/zephyr/app/ec/main_shim.c
+++ b/zephyr/app/ec/main_shim.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/app/ec/soc/Kconfig b/zephyr/app/ec/soc/Kconfig
index 9d3c851a36..3dccfa3a2a 100644
--- a/zephyr/app/ec/soc/Kconfig
+++ b/zephyr/app/ec/soc/Kconfig
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/boards/arm/mec1727/Kconfig.board b/zephyr/boards/arm/mec1727/Kconfig.board
index 66a3993185..7b11c1a0e9 100644
--- a/zephyr/boards/arm/mec1727/Kconfig.board
+++ b/zephyr/boards/arm/mec1727/Kconfig.board
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/boards/arm/mec1727/Kconfig.defconfig b/zephyr/boards/arm/mec1727/Kconfig.defconfig
index 0708bda48c..8afdc63abf 100644
--- a/zephyr/boards/arm/mec1727/Kconfig.defconfig
+++ b/zephyr/boards/arm/mec1727/Kconfig.defconfig
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/boards/arm/mec1727/board.cmake b/zephyr/boards/arm/mec1727/board.cmake
index b67f47c819..d28d9c55e2 100644
--- a/zephyr/boards/arm/mec1727/board.cmake
+++ b/zephyr/boards/arm/mec1727/board.cmake
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/boards/arm/mec1727/mec1727.dts b/zephyr/boards/arm/mec1727/mec1727.dts
index d371f8a2dc..3852f35fa8 100644
--- a/zephyr/boards/arm/mec1727/mec1727.dts
+++ b/zephyr/boards/arm/mec1727/mec1727.dts
@@ -58,22 +58,18 @@
 		compatible = "named-adc-channels";
 
 		adc_ddr_soc: ddr_soc {
-			label = "TEMP_DDR_SOC";
 			enum-name = "ADC_TEMP_SENSOR_1_DDR_SOC";
 			io-channels = <&adc0 5>;
 		};
 		adc_ambient: ambient {
-			label = "TEMP_AMBIENT";
 			enum-name = "ADC_TEMP_SENSOR_2_AMBIENT";
 			io-channels = <&adc0 3>;
 		};
 		adc_charger: charger {
-			label = "TEMP_CHARGER";
 			enum-name = "ADC_TEMP_SENSOR_3_CHARGER";
 			io-channels = <&adc0 0>;
 		};
 		adc_wwan: wwan {
-			label = "TEMP_WWAN";
 			enum-name = "ADC_TEMP_SENSOR_4_WWAN";
 			io-channels = <&adc0 4>;
 		};
@@ -93,7 +89,6 @@
 		cros_kb_raw: cros-kb-raw@40009c00 {
 			compatible = "microchip,xec-cros-kb-raw";
 			reg = <0x40009c00 0x18>;
-			label = "CROS_KB_RAW_0";
 			interrupts = <135 0>;
 		};
 	};
diff --git a/zephyr/boards/arm/mec1727/mec1727_defconfig b/zephyr/boards/arm/mec1727/mec1727_defconfig
index 69f0ff53f5..b6aa0dd1e9 100644
--- a/zephyr/boards/arm/mec1727/mec1727_defconfig
+++ b/zephyr/boards/arm/mec1727/mec1727_defconfig
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -12,6 +12,10 @@ CONFIG_RTOS_TIMER=y
 CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=32768
 CONFIG_SYS_CLOCK_TICKS_PER_SEC=32768
 
+# ADC
+CONFIG_ADC=y
+CONFIG_ADC_SHELL=n
+
 # Serial Drivers
 CONFIG_SERIAL=y
 CONFIG_UART_INTERRUPT_DRIVEN=y
@@ -28,6 +32,7 @@ CONFIG_PINCTRL=y
 
 # GPIO Controller
 CONFIG_GPIO=y
+CONFIG_GPIO_GET_CONFIG=y
 
 # Clock configuration
 CONFIG_CLOCK_CONTROL=y
diff --git a/zephyr/boards/arm/npcx7/Kconfig.board b/zephyr/boards/arm/npcx7/Kconfig.board
index 706f03a577..b5c0134b75 100644
--- a/zephyr/boards/arm/npcx7/Kconfig.board
+++ b/zephyr/boards/arm/npcx7/Kconfig.board
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/boards/arm/npcx7/Kconfig.defconfig b/zephyr/boards/arm/npcx7/Kconfig.defconfig
index fcea4f964e..afa9640b5a 100644
--- a/zephyr/boards/arm/npcx7/Kconfig.defconfig
+++ b/zephyr/boards/arm/npcx7/Kconfig.defconfig
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/boards/arm/npcx7/board.cmake b/zephyr/boards/arm/npcx7/board.cmake
index f2117625b3..e1d12397eb 100644
--- a/zephyr/boards/arm/npcx7/board.cmake
+++ b/zephyr/boards/arm/npcx7/board.cmake
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/boards/arm/npcx7/npcx7.dts b/zephyr/boards/arm/npcx7/npcx7.dts
index 551c3fe3af..99e152c260 100644
--- a/zephyr/boards/arm/npcx7/npcx7.dts
+++ b/zephyr/boards/arm/npcx7/npcx7.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -38,10 +38,6 @@
 	named-adc-channels {
 		compatible = "named-adc-channels";
 	};
-
-	def-lvol-io-list {
-		compatible = "nuvoton,npcx-lvolctrl-def";
-	};
 };
 
 &uart1 {
@@ -88,3 +84,8 @@
 		     >;
 	pinctrl-names = "default";
 };
+
+/* PSL_OUT is fixed to GPIO85 in npcx7 series. */
+&power_ctrl_psl {
+	enable-gpios = <&gpio8 5 0>;
+};
diff --git a/zephyr/boards/arm/npcx7/npcx7_defconfig b/zephyr/boards/arm/npcx7/npcx7_defconfig
index 6cced28039..c6c8f6c3f4 100644
--- a/zephyr/boards/arm/npcx7/npcx7_defconfig
+++ b/zephyr/boards/arm/npcx7/npcx7_defconfig
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -12,6 +12,10 @@ CONFIG_BOARD_NPCX7=y
 CONFIG_SERIAL=y
 CONFIG_UART_INTERRUPT_DRIVEN=y
 
+# ADC
+CONFIG_ADC=y
+CONFIG_ADC_SHELL=n
+
 # Enable console
 CONFIG_CONSOLE=y
 CONFIG_UART_CONSOLE=y
@@ -24,6 +28,7 @@ CONFIG_PINCTRL=y
 
 # GPIO Controller
 CONFIG_GPIO=y
+CONFIG_GPIO_GET_CONFIG=y
 
 # Clock configuration
 CONFIG_CLOCK_CONTROL=y
diff --git a/zephyr/boards/arm/npcx9/Kconfig.board b/zephyr/boards/arm/npcx9/Kconfig.board
index c469ada39e..64e02d2c92 100644
--- a/zephyr/boards/arm/npcx9/Kconfig.board
+++ b/zephyr/boards/arm/npcx9/Kconfig.board
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/boards/arm/npcx9/Kconfig.defconfig b/zephyr/boards/arm/npcx9/Kconfig.defconfig
index a8e2fbc0fd..f764ad0454 100644
--- a/zephyr/boards/arm/npcx9/Kconfig.defconfig
+++ b/zephyr/boards/arm/npcx9/Kconfig.defconfig
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/boards/arm/npcx9/board.cmake b/zephyr/boards/arm/npcx9/board.cmake
index a204305534..e5e2fedd4f 100644
--- a/zephyr/boards/arm/npcx9/board.cmake
+++ b/zephyr/boards/arm/npcx9/board.cmake
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/boards/arm/npcx9/npcx9.dtsi b/zephyr/boards/arm/npcx9/npcx9.dtsi
index 27ece8cdd6..d253928dea 100644
--- a/zephyr/boards/arm/npcx9/npcx9.dtsi
+++ b/zephyr/boards/arm/npcx9/npcx9.dtsi
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -33,10 +33,6 @@
 	named-adc-channels {
 		compatible = "named-adc-channels";
 	};
-
-	def-lvol-io-list {
-		compatible = "nuvoton,npcx-lvolctrl-def";
-	};
 };
 
 &uart1 {
@@ -56,3 +52,8 @@
 		pinmux-gpio;
 	};
 };
+
+/* PSL_OUT is fixed to GPIO85 in npcx9 series. */
+&power_ctrl_psl {
+	enable-gpios = <&gpio8 5 0>;
+};
diff --git a/zephyr/boards/arm/npcx9/npcx9m3f.dts b/zephyr/boards/arm/npcx9/npcx9m3f.dts
index 1b009dfa0b..a51aeccae1 100644
--- a/zephyr/boards/arm/npcx9/npcx9m3f.dts
+++ b/zephyr/boards/arm/npcx9/npcx9m3f.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/boards/arm/npcx9/npcx9m3f_defconfig b/zephyr/boards/arm/npcx9/npcx9m3f_defconfig
index f35fa4564b..d3b4bcc3a2 100644
--- a/zephyr/boards/arm/npcx9/npcx9m3f_defconfig
+++ b/zephyr/boards/arm/npcx9/npcx9m3f_defconfig
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -9,6 +9,10 @@ CONFIG_SOC_NPCX9M3F=y
 # Platform Configuration
 CONFIG_BOARD_NPCX9=y
 
+# ADC
+CONFIG_ADC=y
+CONFIG_ADC_SHELL=n
+
 # Serial Drivers
 CONFIG_SERIAL=y
 CONFIG_UART_INTERRUPT_DRIVEN=y
@@ -25,6 +29,7 @@ CONFIG_PINCTRL=y
 
 # GPIO Controller
 CONFIG_GPIO=y
+CONFIG_GPIO_GET_CONFIG=y
 
 # Clock configuration
 CONFIG_CLOCK_CONTROL=y
diff --git a/zephyr/boards/arm/npcx9/npcx9m7f.dts b/zephyr/boards/arm/npcx9/npcx9m7f.dts
index ebb355c877..5f936173e1 100644
--- a/zephyr/boards/arm/npcx9/npcx9m7f.dts
+++ b/zephyr/boards/arm/npcx9/npcx9m7f.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/boards/arm/npcx9/npcx9m7f_defconfig b/zephyr/boards/arm/npcx9/npcx9m7f_defconfig
index b2015041f4..e742904aed 100644
--- a/zephyr/boards/arm/npcx9/npcx9m7f_defconfig
+++ b/zephyr/boards/arm/npcx9/npcx9m7f_defconfig
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -9,6 +9,10 @@ CONFIG_SOC_NPCX9M7F=y
 # Platform Configuration
 CONFIG_BOARD_NPCX9=y
 
+# ADC
+CONFIG_ADC=y
+CONFIG_ADC_SHELL=n
+
 # Serial Drivers
 CONFIG_SERIAL=y
 CONFIG_UART_INTERRUPT_DRIVEN=y
@@ -25,6 +29,7 @@ CONFIG_PINCTRL=y
 
 # GPIO Controller
 CONFIG_GPIO=y
+CONFIG_GPIO_GET_CONFIG=y
 
 # Clock configuration
 CONFIG_CLOCK_CONTROL=y
diff --git a/zephyr/boards/arm/npcx_evb/Kconfig.board b/zephyr/boards/arm/npcx_evb/Kconfig.board
index 0a64548887..00b6b75f72 100644
--- a/zephyr/boards/arm/npcx_evb/Kconfig.board
+++ b/zephyr/boards/arm/npcx_evb/Kconfig.board
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/boards/arm/npcx_evb/Kconfig.defconfig b/zephyr/boards/arm/npcx_evb/Kconfig.defconfig
index c0c874ad26..512a8403e7 100644
--- a/zephyr/boards/arm/npcx_evb/Kconfig.defconfig
+++ b/zephyr/boards/arm/npcx_evb/Kconfig.defconfig
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/boards/arm/npcx_evb/npcx7_evb.dts b/zephyr/boards/arm/npcx_evb/npcx7_evb.dts
index 1780495feb..75ad9e33a6 100644
--- a/zephyr/boards/arm/npcx_evb/npcx7_evb.dts
+++ b/zephyr/boards/arm/npcx_evb/npcx7_evb.dts
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,3 +22,8 @@
 	pinctrl-0 = <&uart1_2_sin_sout_gp64_65>;
 	pinctrl-names = "default";
 };
+
+/* PSL_OUT is fixed to GPIO85 in npcx7 series. */
+&power_ctrl_psl {
+	enable-gpios = <&gpio8 5 0>;
+};
diff --git a/zephyr/boards/arm/npcx_evb/npcx7_evb_defconfig b/zephyr/boards/arm/npcx_evb/npcx7_evb_defconfig
index 169108f18b..faee09f492 100644
--- a/zephyr/boards/arm/npcx_evb/npcx7_evb_defconfig
+++ b/zephyr/boards/arm/npcx_evb/npcx7_evb_defconfig
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -29,6 +29,7 @@ CONFIG_PINCTRL=y
 
 # GPIO Controller
 CONFIG_GPIO=y
+CONFIG_GPIO_GET_CONFIG=y
 
 # Clock configuration
 CONFIG_CLOCK_CONTROL=y
diff --git a/zephyr/boards/arm/npcx_evb/npcx9_evb.dts b/zephyr/boards/arm/npcx_evb/npcx9_evb.dts
index 6669575466..1def8dc48f 100644
--- a/zephyr/boards/arm/npcx_evb/npcx9_evb.dts
+++ b/zephyr/boards/arm/npcx_evb/npcx9_evb.dts
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,3 +23,8 @@
 		     &uart1_2_sout_gp65>;
 	pinctrl-names = "default";
 };
+
+/* PSL_OUT is fixed to GPIO85 in npcx9 series. */
+&power_ctrl_psl {
+	enable-gpios = <&gpio8 5 0>;
+};
diff --git a/zephyr/boards/arm/npcx_evb/npcx9_evb_defconfig b/zephyr/boards/arm/npcx_evb/npcx9_evb_defconfig
index e64abd9e73..da75b3d113 100644
--- a/zephyr/boards/arm/npcx_evb/npcx9_evb_defconfig
+++ b/zephyr/boards/arm/npcx_evb/npcx9_evb_defconfig
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -29,6 +29,7 @@ CONFIG_PINCTRL=y
 
 # GPIO Controller
 CONFIG_GPIO=y
+CONFIG_GPIO_GET_CONFIG=y
 
 # Clock configuration
 CONFIG_CLOCK_CONTROL=y
diff --git a/zephyr/boards/arm/npcx_evb/npcx_evb.dtsi b/zephyr/boards/arm/npcx_evb/npcx_evb.dtsi
index 9a9f221bfc..615df09a64 100644
--- a/zephyr/boards/arm/npcx_evb/npcx_evb.dtsi
+++ b/zephyr/boards/arm/npcx_evb/npcx_evb.dtsi
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,23 +22,23 @@
 
 		i2c_evb_0_0 {
 			i2c-port = <&i2c0_0>;
-			enum-name = "I2C_PORT_EVB_0";
+			enum-names = "I2C_PORT_EVB_0";
 		};
 		i2c_evb_1_0 {
 			i2c-port = <&i2c1_0>;
-			enum-name = "I2C_PORT_EVB_1";
+			enum-names = "I2C_PORT_EVB_1";
 		};
 		i2c_evb_2_0 {
 			i2c-port = <&i2c2_0>;
-			enum-name = "I2C_PORT_EVB_2";
+			enum-names = "I2C_PORT_EVB_2";
 		};
 		i2c_evb_3_0 {
 			i2c-port = <&i2c3_0>;
-			enum-name = "I2C_PORT_EVB_3";
+			enum-names = "I2C_PORT_EVB_3";
 		};
 		i2c_evb_7_0 {
 			i2c-port = <&i2c7_0>;
-			enum-name = "I2C_PORT_EVB_7";
+			enum-names = "I2C_PORT_EVB_7";
 		};
 	};
 
@@ -46,27 +46,22 @@
 		compatible = "named-adc-channels";
 
 		adc_ch_0 {
-			label = "ADC0";
 			enum-name = "ADC_EVB_CH_0";
 			io-channels = <&adc0 0>;
 		};
 		adc_ch_1 {
-			label = "ADC1";
 			enum-name = "ADC_EVB_CH_1";
 			io-channels = <&adc0 1>;
 		};
 		adc_ch_2 {
-			label = "ADC2";
 			enum-name = "ADC_EVB_CH_2";
 			io-channels = <&adc0 2>;
 		};
 		adc_ch_3 {
-			label = "ADC3";
 			enum-name = "ADC_EVB_CH_3";
 			io-channels = <&adc0 3>;
 		};
 		adc_ch_4 {
-			label = "ADC4";
 			enum-name = "ADC_EVB_CH_4";
 			io-channels = <&adc0 4>;
 		};
diff --git a/zephyr/boards/riscv/it8xxx2/Kconfig.board b/zephyr/boards/riscv/it8xxx2/Kconfig.board
index 0e58c236f8..157d269c77 100644
--- a/zephyr/boards/riscv/it8xxx2/Kconfig.board
+++ b/zephyr/boards/riscv/it8xxx2/Kconfig.board
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/boards/riscv/it8xxx2/Kconfig.defconfig b/zephyr/boards/riscv/it8xxx2/Kconfig.defconfig
index 6cf9bd039b..6b38f9395b 100644
--- a/zephyr/boards/riscv/it8xxx2/Kconfig.defconfig
+++ b/zephyr/boards/riscv/it8xxx2/Kconfig.defconfig
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -11,4 +11,52 @@ choice PLATFORM_EC_HOSTCMD_DEBUG_MODE
 	default HCDEBUG_OFF
 endchoice # PLATFORM_EC_HOSTCMD_DEBUG_MODE
 
+config CROS_EC_HOOK_TICK_INTERVAL
+	default 500000
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 32768
+
+config SYS_CLOCK_TICKS_PER_SEC
+	default 32768
+
+if ADC
+config PLATFORM_EC_ADC_RESOLUTION
+	default 10
+endif # ADC
+
+if CONSOLE
+config UART_CONSOLE
+	default y
+	depends on SERIAL
+endif # CONSOLE
+
+if FLASH
+config PLATFORM_EC_CONSOLE_CMD_FLASH
+	default y
+endif # FLASH
+
+if SERIAL
+config UART_INTERRUPT_DRIVEN
+	default y
+endif # SERIAL
+
+if SHELL
+config SHELL_TAB
+	default y
+config SHELL_TAB_AUTOCOMPLETION
+	default y
+config SHELL_HISTORY
+	default y
+endif # SHELL
+
+if WATCHDOG
+config PLATFORM_EC_WATCHDOG_PERIOD_MS
+	default 2500
+config WDT_ITE_WARNING_LEADING_TIME_MS
+	default 500
+config WDT_ITE_REDUCE_WARNING_LEADING_TIME
+	default y
+endif # WATCHDOG
+
 endif # BOARD_IT8XXX2
diff --git a/zephyr/projects/posix-ec/include/gpio_map.h b/zephyr/boards/riscv/it8xxx2/it81202bx.dts
index 93e5f644ba..d2c892f735 100644
--- a/zephyr/projects/posix-ec/include/gpio_map.h
+++ b/zephyr/boards/riscv/it8xxx2/it81202bx.dts
@@ -1,4 +1,8 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
+
+/dts-v1/;
+
+#include "it8xxx2.dts"
diff --git a/zephyr/boards/riscv/it8xxx2/it81202bx_defconfig b/zephyr/boards/riscv/it8xxx2/it81202bx_defconfig
new file mode 100644
index 0000000000..a024ab5824
--- /dev/null
+++ b/zephyr/boards/riscv/it8xxx2/it81202bx_defconfig
@@ -0,0 +1,39 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Zephyr Kernel Configuration
+CONFIG_SOC_SERIES_RISCV32_IT8XXX2=y
+CONFIG_SOC_IT8XXX2=y
+CONFIG_SOC_IT81202_BX=y
+
+# Platform Configuration
+CONFIG_BOARD_IT8XXX2=y
+
+# ADC
+CONFIG_ADC=y
+CONFIG_ADC_SHELL=n
+
+# Power Management
+CONFIG_PM=y
+CONFIG_PM_DEVICE=y
+CONFIG_PM_POLICY_CUSTOM=y
+
+# Console
+CONFIG_CONSOLE=y
+
+# GPIO Controller
+CONFIG_GPIO=y
+CONFIG_GPIO_GET_CONFIG=y
+
+# Clock Controller
+CONFIG_CLOCK_CONTROL=n
+
+# Serial Drivers
+CONFIG_SERIAL=y
+
+# WATCHDOG configuration
+CONFIG_WATCHDOG=y
+
+# BBRAM
+CONFIG_BBRAM=y
diff --git a/zephyr/projects/nissa/include/gpio_map.h b/zephyr/boards/riscv/it8xxx2/it81302bx.dts
index e99bf2c131..d2c892f735 100644
--- a/zephyr/projects/nissa/include/gpio_map.h
+++ b/zephyr/boards/riscv/it8xxx2/it81302bx.dts
@@ -1,4 +1,8 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
+
+/dts-v1/;
+
+#include "it8xxx2.dts"
diff --git a/zephyr/boards/riscv/it8xxx2/it81302bx_defconfig b/zephyr/boards/riscv/it8xxx2/it81302bx_defconfig
new file mode 100644
index 0000000000..2841b9663c
--- /dev/null
+++ b/zephyr/boards/riscv/it8xxx2/it81302bx_defconfig
@@ -0,0 +1,39 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Zephyr Kernel Configuration
+CONFIG_SOC_SERIES_RISCV32_IT8XXX2=y
+CONFIG_SOC_IT8XXX2=y
+CONFIG_SOC_IT81302_BX=y
+
+# Platform Configuration
+CONFIG_BOARD_IT8XXX2=y
+
+# ADC
+CONFIG_ADC=y
+CONFIG_ADC_SHELL=n
+
+# Power Management
+CONFIG_PM=y
+CONFIG_PM_DEVICE=y
+CONFIG_PM_POLICY_CUSTOM=y
+
+# Console
+CONFIG_CONSOLE=y
+
+# GPIO Controller
+CONFIG_GPIO=y
+CONFIG_GPIO_GET_CONFIG=y
+
+# Clock Controller
+CONFIG_CLOCK_CONTROL=n
+
+# Serial Drivers
+CONFIG_SERIAL=y
+
+# WATCHDOG configuration
+CONFIG_WATCHDOG=y
+
+# BBRAM
+CONFIG_BBRAM=y
diff --git a/zephyr/boards/riscv/it8xxx2/it8xxx2.dts b/zephyr/boards/riscv/it8xxx2/it8xxx2.dts
index 405d8f7a3e..640efd1433 100644
--- a/zephyr/boards/riscv/it8xxx2/it8xxx2.dts
+++ b/zephyr/boards/riscv/it8xxx2/it8xxx2.dts
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/boards/riscv/it8xxx2/it8xxx2_defconfig b/zephyr/boards/riscv/it8xxx2/it8xxx2_defconfig
deleted file mode 100644
index 740910d5ab..0000000000
--- a/zephyr/boards/riscv/it8xxx2/it8xxx2_defconfig
+++ /dev/null
@@ -1,78 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Zephyr Kernel Configuration
-CONFIG_SOC_SERIES_RISCV32_IT8XXX2=y
-CONFIG_SOC_IT8XXX2=y
-
-# Platform Configuration
-CONFIG_BOARD_IT8XXX2=y
-
-# Power Management
-CONFIG_PM=y
-CONFIG_PM_DEVICE=y
-CONFIG_PM_POLICY_CUSTOM=y
-
-# Console
-CONFIG_CONSOLE=y
-CONFIG_UART_CONSOLE=y
-CONFIG_UART_NS16550=y
-CONFIG_SHELL_TAB=y
-CONFIG_SHELL_TAB_AUTOCOMPLETION=y
-CONFIG_SHELL_HISTORY=y
-
-# GPIO Controller
-CONFIG_GPIO=y
-CONFIG_GPIO_ITE_IT8XXX2=y
-# For IT81202, the GPIO group k/l are not brought out to pins,
-# so by default they can be set to pull down inputs.
-# However with the IT81302, they are available on pins,
-# and should not be set to pull down inputs by default.
-CONFIG_SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN=n
-
-# ADC Driver
-CONFIG_ADC_ITE_IT8XXX2=y
-CONFIG_PLATFORM_EC_ADC=y
-CONFIG_PLATFORM_EC_ADC_RESOLUTION=10
-
-# Clock configuration
-CONFIG_CLOCK_CONTROL=y
-CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=32768
-CONFIG_SYS_CLOCK_TICKS_PER_SEC=32768
-
-# Hook tick
-CONFIG_CROS_EC_HOOK_TICK_INTERVAL=500000
-
-# Flash
-CONFIG_PLATFORM_EC_CONSOLE_CMD_FLASH=y
-CONFIG_SOC_FLASH_ITE_IT8XXX2=y
-
-# I2C
-CONFIG_I2C=y
-CONFIG_I2C_ITE_IT8XXX2=y
-
-# Power Button
-CONFIG_PLATFORM_EC_POWER_BUTTON=y
-
-# PWM
-CONFIG_PWM=y
-CONFIG_PWM_SHELL=n
-CONFIG_PWM_ITE_IT8XXX2=y
-
-# Serial Drivers
-CONFIG_SERIAL=y
-CONFIG_UART_INTERRUPT_DRIVEN=y
-
-# Timer configuration
-CONFIG_ITE_IT8XXX2_TIMER=y
-
-# WATCHDOG configuration
-CONFIG_WATCHDOG=y
-CONFIG_PLATFORM_EC_WATCHDOG_PERIOD_MS=2500
-CONFIG_WDT_ITE_WARNING_LEADING_TIME_MS=500
-CONFIG_WDT_ITE_REDUCE_WARNING_LEADING_TIME=y
-
-# BBRAM
-CONFIG_BBRAM=y
-CONFIG_BBRAM_IT8XXX2=y
diff --git a/zephyr/cmake/bintools/gnu/target.cmake b/zephyr/cmake/bintools/gnu/target.cmake
index 2ec9d075dc..13e81ed4a0 100644
--- a/zephyr/cmake/bintools/gnu/target.cmake
+++ b/zephyr/cmake/bintools/gnu/target.cmake
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/cmake/bintools/llvm/generic.cmake b/zephyr/cmake/bintools/llvm/generic.cmake
index 94b35ed51d..f85236d39c 100644
--- a/zephyr/cmake/bintools/llvm/generic.cmake
+++ b/zephyr/cmake/bintools/llvm/generic.cmake
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/cmake/bintools/llvm/target.cmake b/zephyr/cmake/bintools/llvm/target.cmake
index a77d459288..9e747483ae 100644
--- a/zephyr/cmake/bintools/llvm/target.cmake
+++ b/zephyr/cmake/bintools/llvm/target.cmake
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/cmake/compiler/clang/compiler_flags.cmake b/zephyr/cmake/compiler/clang/compiler_flags.cmake
index 5f97625a58..3423f1c36c 100644
--- a/zephyr/cmake/compiler/clang/compiler_flags.cmake
+++ b/zephyr/cmake/compiler/clang/compiler_flags.cmake
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -7,6 +7,9 @@ include("${ZEPHYR_BASE}/cmake/compiler/clang/compiler_flags.cmake")
 # Disable -fno-freestanding.
 set_compiler_property(PROPERTY hosted)
 
+# Disable position independent code.
+add_compile_options(-fno-PIC)
+
 check_set_compiler_property(APPEND PROPERTY warning_extended -Wunused-variable
 	-Werror=unused-variable -Werror=missing-braces
 	-Werror=sometimes-uninitialized -Werror=unused-function
diff --git a/zephyr/cmake/compiler/clang/generic.cmake b/zephyr/cmake/compiler/clang/generic.cmake
index aa3665ad39..b848c8bd03 100644
--- a/zephyr/cmake/compiler/clang/generic.cmake
+++ b/zephyr/cmake/compiler/clang/generic.cmake
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/cmake/compiler/clang/target.cmake b/zephyr/cmake/compiler/clang/target.cmake
index 6702087df5..bda3efdeae 100644
--- a/zephyr/cmake/compiler/clang/target.cmake
+++ b/zephyr/cmake/compiler/clang/target.cmake
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/cmake/compiler/gcc/compiler_flags.cmake b/zephyr/cmake/compiler/gcc/compiler_flags.cmake
index 125f909c87..adc111835e 100644
--- a/zephyr/cmake/compiler/gcc/compiler_flags.cmake
+++ b/zephyr/cmake/compiler/gcc/compiler_flags.cmake
@@ -1,7 +1,10 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 # Zephyr cmake system looks into ${TOOLCHAIN_ROOT}, but we just send
 # this out to the copy in ${ZEPHYR_BASE}.
 include("${ZEPHYR_BASE}/cmake/compiler/gcc/compiler_flags.cmake")
+
+# Disable position independent code.
+add_compile_options(-fno-PIC)
diff --git a/zephyr/cmake/compiler/gcc/target.cmake b/zephyr/cmake/compiler/gcc/target.cmake
index 5bdb6fc5f6..943ea167ca 100644
--- a/zephyr/cmake/compiler/gcc/target.cmake
+++ b/zephyr/cmake/compiler/gcc/target.cmake
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/cmake/linker/ld/gcc/linker_flags.cmake b/zephyr/cmake/linker/ld/gcc/linker_flags.cmake
new file mode 100644
index 0000000000..f71793c431
--- /dev/null
+++ b/zephyr/cmake/linker/ld/gcc/linker_flags.cmake
@@ -0,0 +1,7 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# GCC 11 by default emits DWARF version 5 which cannot be parsed by
+# pyelftools. Can be removed once pyelftools supports v5.
+add_link_options(-gdwarf-4)
diff --git a/zephyr/cmake/linker/ld/linker_flags.cmake b/zephyr/cmake/linker/ld/linker_flags.cmake
index c80d1d2452..d6045ba6ed 100644
--- a/zephyr/cmake/linker/ld/linker_flags.cmake
+++ b/zephyr/cmake/linker/ld/linker_flags.cmake
@@ -1,7 +1,11 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 # Zephyr cmake system looks into ${TOOLCHAIN_ROOT}, but we just send
 # this out to the copy in ${ZEPHYR_BASE}.
 include("${ZEPHYR_BASE}/cmake/linker/ld/linker_flags.cmake")
+
+# There can also be compiler specific linker options, so try to include
+# our version of that also.
+include("${TOOLCHAIN_ROOT}/cmake/linker/${LINKER}/${COMPILER}/linker_flags.cmake" OPTIONAL)
diff --git a/zephyr/cmake/linker/ld/target.cmake b/zephyr/cmake/linker/ld/target.cmake
index 0e2ad1f4d7..02dd95b236 100644
--- a/zephyr/cmake/linker/ld/target.cmake
+++ b/zephyr/cmake/linker/ld/target.cmake
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/cmake/linker/lld/linker_flags.cmake b/zephyr/cmake/linker/lld/linker_flags.cmake
index 5055e4c5a4..d382bd5b60 100644
--- a/zephyr/cmake/linker/lld/linker_flags.cmake
+++ b/zephyr/cmake/linker/lld/linker_flags.cmake
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/cmake/linker/lld/target.cmake b/zephyr/cmake/linker/lld/target.cmake
index 1bbc6f479d..10774909a2 100644
--- a/zephyr/cmake/linker/lld/target.cmake
+++ b/zephyr/cmake/linker/lld/target.cmake
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -21,6 +21,7 @@ macro(toolchain_ld_base)
   # Default flags
   zephyr_ld_options(
     ${TOOLCHAIN_LD_FLAGS}
+    -no-pie
     -Wl,--gc-sections
     --build-id=none)
 endmacro()
diff --git a/zephyr/cmake/toolchain/coreboot-sdk/generic.cmake b/zephyr/cmake/toolchain/coreboot-sdk/generic.cmake
index 1b86948bcd..d20f19528d 100644
--- a/zephyr/cmake/toolchain/coreboot-sdk/generic.cmake
+++ b/zephyr/cmake/toolchain/coreboot-sdk/generic.cmake
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/cmake/toolchain/coreboot-sdk/target.cmake b/zephyr/cmake/toolchain/coreboot-sdk/target.cmake
index 5f3d86459b..82804e6b32 100644
--- a/zephyr/cmake/toolchain/coreboot-sdk/target.cmake
+++ b/zephyr/cmake/toolchain/coreboot-sdk/target.cmake
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/cmake/toolchain/llvm/generic.cmake b/zephyr/cmake/toolchain/llvm/generic.cmake
index 6a248a13cf..933162d9bb 100644
--- a/zephyr/cmake/toolchain/llvm/generic.cmake
+++ b/zephyr/cmake/toolchain/llvm/generic.cmake
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/cmake/toolchain/llvm/target.cmake b/zephyr/cmake/toolchain/llvm/target.cmake
index d79d73d1ae..e6960dade5 100644
--- a/zephyr/cmake/toolchain/llvm/target.cmake
+++ b/zephyr/cmake/toolchain/llvm/target.cmake
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/drivers/CMakeLists.txt b/zephyr/drivers/CMakeLists.txt
index ae74955a44..38d8b3f7bb 100644
--- a/zephyr/drivers/CMakeLists.txt
+++ b/zephyr/drivers/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/drivers/Kconfig b/zephyr/drivers/Kconfig
index 041a6cf212..0848d83939 100644
--- a/zephyr/drivers/Kconfig
+++ b/zephyr/drivers/Kconfig
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/drivers/cros_displight/CMakeLists.txt b/zephyr/drivers/cros_displight/CMakeLists.txt
index 9f6d99ee34..5e43d5fedd 100644
--- a/zephyr/drivers/cros_displight/CMakeLists.txt
+++ b/zephyr/drivers/cros_displight/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/drivers/cros_displight/cros_displight.c b/zephyr/drivers/cros_displight/cros_displight.c
index e730caf409..98d1dd0823 100644
--- a/zephyr/drivers/cros_displight/cros_displight.c
+++ b/zephyr/drivers/cros_displight/cros_displight.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,7 +21,7 @@ BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
 #define DISPLIGHT_PWM_NODE DT_INST_PWMS_CTLR(0)
 #define DISPLIGHT_PWM_CHANNEL DT_INST_PWMS_CHANNEL(0)
 #define DISPLIGHT_PWM_FLAGS DT_INST_PWMS_FLAGS(0)
-#define DISPLIGHT_PWM_PERIOD_NS (NSEC_PER_SEC/DT_INST_PROP(0, frequency))
+#define DISPLIGHT_PWM_PERIOD_NS DT_INST_PWMS_PERIOD(0)
 
 static int displight_percent;
 
@@ -38,8 +38,8 @@ static void displight_set_duty(int percent)
 
 	pulse_ns = DIV_ROUND_NEAREST(DISPLIGHT_PWM_PERIOD_NS * percent, 100);
 
-	LOG_DBG("displight PWM %s set percent (%d), pulse %d",
-		pwm_dev->name, percent, pulse_ns);
+	LOG_DBG("displight PWM %s set percent (%d), pulse %d", pwm_dev->name,
+		percent, pulse_ns);
 
 	rv = pwm_set(pwm_dev, DISPLIGHT_PWM_CHANNEL, DISPLIGHT_PWM_PERIOD_NS,
 		     pulse_ns, DISPLIGHT_PWM_FLAGS);
diff --git a/zephyr/drivers/cros_flash/CMakeLists.txt b/zephyr/drivers/cros_flash/CMakeLists.txt
index 1846d10576..fdd60a2f44 100644
--- a/zephyr/drivers/cros_flash/CMakeLists.txt
+++ b/zephyr/drivers/cros_flash/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/drivers/cros_flash/Kconfig b/zephyr/drivers/cros_flash/Kconfig
index 68ed451f27..247f261cc5 100644
--- a/zephyr/drivers/cros_flash/Kconfig
+++ b/zephyr/drivers/cros_flash/Kconfig
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/drivers/cros_flash/cros_flash_it8xxx2.c b/zephyr/drivers/cros_flash/cros_flash_it8xxx2.c
index 7be6ef86fb..4838c5d583 100644
--- a/zephyr/drivers/cros_flash/cros_flash_it8xxx2.c
+++ b/zephyr/drivers/cros_flash/cros_flash_it8xxx2.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -102,7 +102,7 @@ static int cros_flash_it8xxx2_init(const struct device *dev)
 	reset_flags = system_get_reset_flags();
 	prot_flags = crec_flash_get_protect();
 	unwanted_prot_flags = EC_FLASH_PROTECT_ALL_NOW |
-		EC_FLASH_PROTECT_ERROR_INCONSISTENT;
+			      EC_FLASH_PROTECT_ERROR_INCONSISTENT;
 
 	/*
 	 * If we have already jumped between images, an earlier image could
@@ -113,12 +113,12 @@ static int cros_flash_it8xxx2_init(const struct device *dev)
 
 	if (prot_flags & EC_FLASH_PROTECT_GPIO_ASSERTED) {
 		/* Protect the entire flash of host interface */
-		flash_protect_banks(0,
-			CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE,
+		flash_protect_banks(
+			0, CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE,
 			FLASH_WP_HOST);
 		/* Protect the entire flash of DBGR interface */
-		flash_protect_banks(0,
-			CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE,
+		flash_protect_banks(
+			0, CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE,
 			FLASH_WP_DBGR);
 		/*
 		 * Write protect is asserted.  If we want RO flash protected,
@@ -126,8 +126,9 @@ static int cros_flash_it8xxx2_init(const struct device *dev)
 		 */
 		if ((prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT) &&
 		    !(prot_flags & EC_FLASH_PROTECT_RO_NOW)) {
-			int rv = crec_flash_set_protect(EC_FLASH_PROTECT_RO_NOW,
-						   EC_FLASH_PROTECT_RO_NOW);
+			int rv =
+				crec_flash_set_protect(EC_FLASH_PROTECT_RO_NOW,
+						       EC_FLASH_PROTECT_RO_NOW);
 			if (rv)
 				return rv;
 
@@ -206,13 +207,13 @@ static int cros_flash_it8xxx2_erase(const struct device *dev, int offset,
 	 * during erasing.
 	 */
 	if (IS_ENABLED(HAS_TASK_HOSTCMD) &&
-		IS_ENABLED(CONFIG_HOST_COMMAND_STATUS)) {
+	    IS_ENABLED(CONFIG_HOST_COMMAND_STATUS)) {
 		irq_enable(DT_IRQN(DT_NODELABEL(shi)));
 	}
 	/* Always use sector erase command */
 	for (; size > 0; size -= CONFIG_FLASH_ERASE_SIZE) {
 		ret = flash_erase(flash_controller, offset,
-			CONFIG_FLASH_ERASE_SIZE);
+				  CONFIG_FLASH_ERASE_SIZE);
 		if (ret)
 			break;
 
@@ -273,17 +274,16 @@ static int cros_flash_it8xxx2_protect_now(const struct device *dev, int all)
 
 	if (all) {
 		/* Protect the entire flash */
-		flash_protect_banks(0,
-			CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE,
+		flash_protect_banks(
+			0, CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE,
 			FLASH_WP_EC);
 		data->all_protected = 1;
 	} else {
 		/* Protect the read-only section and persistent state */
-		flash_protect_banks(WP_BANK_OFFSET,
-			WP_BANK_COUNT, FLASH_WP_EC);
+		flash_protect_banks(WP_BANK_OFFSET, WP_BANK_COUNT, FLASH_WP_EC);
 #ifdef PSTATE_BANK
-		flash_protect_banks(PSTATE_BANK,
-			PSTATE_BANK_COUNT, FLASH_WP_EC);
+		flash_protect_banks(PSTATE_BANK, PSTATE_BANK_COUNT,
+				    FLASH_WP_EC);
 #endif
 	}
 
diff --git a/zephyr/drivers/cros_flash/cros_flash_npcx.c b/zephyr/drivers/cros_flash/cros_flash_npcx.c
index e0ffe9f348..032bb5906c 100644
--- a/zephyr/drivers/cros_flash/cros_flash_npcx.c
+++ b/zephyr/drivers/cros_flash/cros_flash_npcx.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/drivers/cros_flash/cros_flash_xec.c b/zephyr/drivers/cros_flash/cros_flash_xec.c
index 2424c2a499..2b92eae25b 100644
--- a/zephyr/drivers/cros_flash/cros_flash_xec.c
+++ b/zephyr/drivers/cros_flash/cros_flash_xec.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -184,7 +184,7 @@ static int cros_flash_xec_set_status_reg(const struct device *dev,
 }
 
 static int cros_flash_xec_write_protection_set(const struct device *dev,
-						bool enable)
+					       bool enable)
 {
 	int ret = 0;
 
@@ -303,8 +303,7 @@ static int flash_set_status_for_prot(const struct device *dev, int reg1)
 
 	flash_set_status(dev, reg1);
 
-	spi_flash_reg_to_protect(reg1, 0, &addr_prot_start,
-				 &addr_prot_length);
+	spi_flash_reg_to_protect(reg1, 0, &addr_prot_start, &addr_prot_length);
 
 	return EC_SUCCESS;
 }
@@ -392,7 +391,6 @@ static int cros_flash_xec_init(const struct device *dev)
 	return 0;
 }
 
-
 static int cros_flash_xec_write(const struct device *dev, int offset, int size,
 				const char *src_data)
 {
@@ -524,7 +522,7 @@ static int cros_flash_xec_protect_now(const struct device *dev, int all)
 }
 
 static int cros_flash_xec_get_jedec_id(const struct device *dev,
-					uint8_t *manufacturer, uint16_t *device)
+				       uint8_t *manufacturer, uint16_t *device)
 {
 	int ret;
 	uint8_t jedec_id[3];
@@ -546,7 +544,7 @@ static int cros_flash_xec_get_jedec_id(const struct device *dev,
 }
 
 static int cros_flash_xec_get_status(const struct device *dev, uint8_t *sr1,
-				      uint8_t *sr2)
+				     uint8_t *sr2)
 {
 	flash_get_status(dev, sr1);
 	*sr2 = 0;
diff --git a/zephyr/drivers/cros_kb_raw/CMakeLists.txt b/zephyr/drivers/cros_kb_raw/CMakeLists.txt
index 0b51057dbf..680b15342e 100644
--- a/zephyr/drivers/cros_kb_raw/CMakeLists.txt
+++ b/zephyr/drivers/cros_kb_raw/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/drivers/cros_kb_raw/Kconfig b/zephyr/drivers/cros_kb_raw/Kconfig
index 682c7843b9..1055c8a4b2 100644
--- a/zephyr/drivers/cros_kb_raw/Kconfig
+++ b/zephyr/drivers/cros_kb_raw/Kconfig
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/drivers/cros_kb_raw/cros_kb_raw_ite.c b/zephyr/drivers/cros_kb_raw/cros_kb_raw_ite.c
index 49c80b2211..fdbc8ee30d 100644
--- a/zephyr/drivers/cros_kb_raw/cros_kb_raw_ite.c
+++ b/zephyr/drivers/cros_kb_raw/cros_kb_raw_ite.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -120,7 +120,7 @@ static int cros_kb_raw_ite_drive_column(const struct device *dev, int col)
 	 * we are using).
 	 */
 	inst->KBS_KSOH1 = ((inst->KBS_KSOH1) & ~KSOH_PIN_MASK) |
-		      ((mask >> 8) & KSOH_PIN_MASK);
+			  ((mask >> 8) & KSOH_PIN_MASK);
 	/* restore interrupts */
 	irq_unlock(key);
 
@@ -208,7 +208,7 @@ static int cros_kb_raw_ite_init(const struct device *dev)
 		 */
 		if (IS_ENABLED(CONFIG_LOG)) {
 			if (config->wuc_map_list[i].wucs !=
-				config->wuc_map_list[0].wucs) {
+			    config->wuc_map_list[0].wucs) {
 				LOG_ERR("KSI%d isn't in the same wuc node!", i);
 			}
 		}
diff --git a/zephyr/drivers/cros_kb_raw/cros_kb_raw_npcx.c b/zephyr/drivers/cros_kb_raw/cros_kb_raw_npcx.c
index cc60794d24..c720f4b431 100644
--- a/zephyr/drivers/cros_kb_raw/cros_kb_raw_npcx.c
+++ b/zephyr/drivers/cros_kb_raw/cros_kb_raw_npcx.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/drivers/cros_kb_raw/cros_kb_raw_xec.c b/zephyr/drivers/cros_kb_raw/cros_kb_raw_xec.c
index 31dcfdd29d..797377f84f 100644
--- a/zephyr/drivers/cros_kb_raw/cros_kb_raw_xec.c
+++ b/zephyr/drivers/cros_kb_raw/cros_kb_raw_xec.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -103,7 +103,7 @@ static int cros_kb_raw_xec_drive_column(const struct device *dev, int col)
 	/* Drive all lines to low for detection any key press */
 	else if (col == KEYBOARD_COLUMN_ALL) {
 		mchp_soc_ecia_girq_src_dis(MCHP_GIRQ21_ID,
-			MCHP_KEYSCAN_GIRQ_POS);
+					   MCHP_KEYSCAN_GIRQ_POS);
 		inst->KSO_SEL = MCHP_KSCAN_KSO_ALL;
 		/* Set logical level low on COL2 */
 		cros_kb_raw_set_col2(0);
@@ -122,7 +122,7 @@ static int cros_kb_raw_xec_drive_column(const struct device *dev, int col)
 			kb_raw_xec_clr_src(dev);
 		}
 		mchp_soc_ecia_girq_src_en(MCHP_GIRQ21_ID,
-			MCHP_KEYSCAN_GIRQ_POS);
+					  MCHP_KEYSCAN_GIRQ_POS);
 	}
 	/* Drive one line to low for determining
 	 * which key's state changed.
@@ -164,7 +164,7 @@ static int cros_kb_raw_xec_init(const struct device *dev)
 
 	/* Set up Kscan IRQ and ISR */
 	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
-		cros_kb_raw_xec_ksi_isr, DEVICE_DT_INST_GET(0), 0);
+		    cros_kb_raw_xec_ksi_isr, DEVICE_DT_INST_GET(0), 0);
 
 	/* Disable Kscan NVIC and source interrupts */
 	irq_disable(cfg->irq);
diff --git a/zephyr/drivers/cros_kblight/CMakeLists.txt b/zephyr/drivers/cros_kblight/CMakeLists.txt
index a9e8516f85..6371370b65 100644
--- a/zephyr/drivers/cros_kblight/CMakeLists.txt
+++ b/zephyr/drivers/cros_kblight/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/drivers/cros_kblight/pwm_kblight.c b/zephyr/drivers/cros_kblight/pwm_kblight.c
index b57adff26d..59b4ef20ef 100644
--- a/zephyr/drivers/cros_kblight/pwm_kblight.c
+++ b/zephyr/drivers/cros_kblight/pwm_kblight.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,7 +21,7 @@ BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
 #define KBLIGHT_PWM_NODE DT_INST_PWMS_CTLR(0)
 #define KBLIGHT_PWM_CHANNEL DT_INST_PWMS_CHANNEL(0)
 #define KBLIGHT_PWM_FLAGS DT_INST_PWMS_FLAGS(0)
-#define KBLIGHT_PWM_PERIOD_NS (NSEC_PER_SEC/DT_INST_PROP(0, frequency))
+#define KBLIGHT_PWM_PERIOD_NS DT_INST_PWMS_PERIOD(0)
 
 static bool kblight_enabled;
 static int kblight_percent;
@@ -39,8 +39,8 @@ static void kblight_pwm_set_duty(int percent)
 
 	pulse_ns = DIV_ROUND_NEAREST(KBLIGHT_PWM_PERIOD_NS * percent, 100);
 
-	LOG_DBG("kblight PWM %s set percent (%d), pulse %d",
-		pwm_dev->name, percent, pulse_ns);
+	LOG_DBG("kblight PWM %s set percent (%d), pulse %d", pwm_dev->name,
+		percent, pulse_ns);
 
 	rv = pwm_set(pwm_dev, KBLIGHT_PWM_CHANNEL, KBLIGHT_PWM_PERIOD_NS,
 		     pulse_ns, KBLIGHT_PWM_FLAGS);
diff --git a/zephyr/drivers/cros_rtc/CMakeLists.txt b/zephyr/drivers/cros_rtc/CMakeLists.txt
index bfec8b9ad5..d9ae577254 100644
--- a/zephyr/drivers/cros_rtc/CMakeLists.txt
+++ b/zephyr/drivers/cros_rtc/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/drivers/cros_rtc/Kconfig b/zephyr/drivers/cros_rtc/Kconfig
index 50a4d00022..2839b03c62 100644
--- a/zephyr/drivers/cros_rtc/Kconfig
+++ b/zephyr/drivers/cros_rtc/Kconfig
@@ -1,8 +1,8 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
-if PLATFORM_EC_RTC
+if PLATFORM_EC_RTC && !ARCH_POSIX
 
 choice CROS_RTC_TYPE
 	prompt "Select the RTC to use"
diff --git a/zephyr/drivers/cros_rtc/cros_rtc_xec.c b/zephyr/drivers/cros_rtc/cros_rtc_xec.c
index ec8e0e6d07..c543aab6af 100644
--- a/zephyr/drivers/cros_rtc/cros_rtc_xec.c
+++ b/zephyr/drivers/cros_rtc/cros_rtc_xec.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -123,7 +123,7 @@ static const struct cros_rtc_xec_config cros_rtc_xec_cfg_0 = {
 
 static struct cros_rtc_xec_data cros_rtc_xec_data_0;
 
-DEVICE_DT_INST_DEFINE(0, cros_rtc_xec_init, NULL,
-		      &cros_rtc_xec_data_0, &cros_rtc_xec_cfg_0, POST_KERNEL,
+DEVICE_DT_INST_DEFINE(0, cros_rtc_xec_init, NULL, &cros_rtc_xec_data_0,
+		      &cros_rtc_xec_cfg_0, POST_KERNEL,
 		      CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
 		      &cros_rtc_xec_driver_api);
diff --git a/zephyr/drivers/cros_rtc/nxp_rtc_pcf85063a.c b/zephyr/drivers/cros_rtc/nxp_rtc_pcf85063a.c
index e7821c1dac..c5580eaeef 100644
--- a/zephyr/drivers/cros_rtc/nxp_rtc_pcf85063a.c
+++ b/zephyr/drivers/cros_rtc/nxp_rtc_pcf85063a.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -58,12 +58,12 @@ static int pcf85063a_read_time_regs(const struct device *dev, bool is_alarm)
 		num_reg = NUM_TIMER_REGS;
 	}
 
-	return i2c_burst_read(config->bus,
-		config->i2c_addr_flags, start_reg, data->time_reg, num_reg);
+	return i2c_burst_read(config->bus, config->i2c_addr_flags, start_reg,
+			      data->time_reg, num_reg);
 }
 
-static int pcf85063a_read_reg(const struct device *dev,
-						uint8_t reg, uint8_t *val)
+static int pcf85063a_read_reg(const struct device *dev, uint8_t reg,
+			      uint8_t *val)
 {
 	const struct nxp_rtc_pcf85063a_config *const config = DRV_CONFIG(dev);
 
@@ -95,13 +95,12 @@ static int pcf85063a_write_time_regs(const struct device *dev, bool is_alarm)
 		tx_buf[i] = data->time_reg[i];
 	}
 
-	return i2c_burst_write(config->bus,
-			config->i2c_addr_flags, start_reg, tx_buf, num_reg);
+	return i2c_burst_write(config->bus, config->i2c_addr_flags, start_reg,
+			       tx_buf, num_reg);
 }
 
-
-static int pcf85063a_write_reg(const struct device *dev,
-						uint8_t reg, uint8_t val)
+static int pcf85063a_write_reg(const struct device *dev, uint8_t reg,
+			       uint8_t val)
 {
 	const struct nxp_rtc_pcf85063a_config *const config = DRV_CONFIG(dev);
 	uint8_t tx_buf[2];
@@ -109,8 +108,8 @@ static int pcf85063a_write_reg(const struct device *dev,
 	tx_buf[0] = reg;
 	tx_buf[1] = val;
 
-	return i2c_write(config->bus,
-		tx_buf, sizeof(tx_buf), config->i2c_addr_flags);
+	return i2c_write(config->bus, tx_buf, sizeof(tx_buf),
+			 config->i2c_addr_flags);
 }
 
 /*
@@ -138,7 +137,7 @@ static uint8_t dec_to_bcd(uint32_t val, enum bcd_mask mask)
 }
 
 static int nxp_rtc_pcf85063a_read_seconds(const struct device *dev,
-					uint32_t *value, bool is_alarm)
+					  uint32_t *value, bool is_alarm)
 {
 	struct nxp_rtc_pcf85063a_data *data = DRV_DATA(dev);
 	struct calendar_date time;
@@ -152,31 +151,30 @@ static int nxp_rtc_pcf85063a_read_seconds(const struct device *dev,
 
 	if (is_alarm) {
 		*value = (bcd_to_dec(data->time_reg[DAYS], DAYS_MASK) *
-				SECS_PER_DAY) +
-			(bcd_to_dec(data->time_reg[HOURS], HOURS24_MASK) *
-				SECS_PER_HOUR) +
-			(bcd_to_dec(data->time_reg[MINUTES], MINUTES_MASK) *
-				SECS_PER_MINUTE) +
-			bcd_to_dec(data->time_reg[SECONDS], SECONDS_MASK);
+			  SECS_PER_DAY) +
+			 (bcd_to_dec(data->time_reg[HOURS], HOURS24_MASK) *
+			  SECS_PER_HOUR) +
+			 (bcd_to_dec(data->time_reg[MINUTES], MINUTES_MASK) *
+			  SECS_PER_MINUTE) +
+			 bcd_to_dec(data->time_reg[SECONDS], SECONDS_MASK);
 	} else {
 		time.year = bcd_to_dec(data->time_reg[YEARS], YEARS_MASK);
-		time.month =
-			bcd_to_dec(data->time_reg[MONTHS], MONTHS_MASK);
+		time.month = bcd_to_dec(data->time_reg[MONTHS], MONTHS_MASK);
 		time.day = bcd_to_dec(data->time_reg[DAYS], DAYS_MASK);
 
 		*value = date_to_sec(time) - SECS_TILL_YEAR_2K +
-			(bcd_to_dec(data->time_reg[HOURS], HOURS24_MASK) *
-				SECS_PER_HOUR) +
-			(bcd_to_dec(data->time_reg[MINUTES], MINUTES_MASK) *
-				SECS_PER_MINUTE) +
-			bcd_to_dec(data->time_reg[SECONDS], SECONDS_MASK);
+			 (bcd_to_dec(data->time_reg[HOURS], HOURS24_MASK) *
+			  SECS_PER_HOUR) +
+			 (bcd_to_dec(data->time_reg[MINUTES], MINUTES_MASK) *
+			  SECS_PER_MINUTE) +
+			 bcd_to_dec(data->time_reg[SECONDS], SECONDS_MASK);
 	}
 
 	return ret;
 }
 
 static int nxp_rtc_pcf85063a_write_seconds(const struct device *dev,
-				uint32_t value, bool is_alarm)
+					   uint32_t value, bool is_alarm)
 {
 	struct nxp_rtc_pcf85063a_data *data = DRV_DATA(dev);
 	struct calendar_date time;
@@ -186,8 +184,7 @@ static int nxp_rtc_pcf85063a_write_seconds(const struct device *dev,
 
 	if (!is_alarm) {
 		data->time_reg[YEARS] = dec_to_bcd(time.year, YEARS_MASK);
-		data->time_reg[MONTHS] =
-				dec_to_bcd(time.month, MONTHS_MASK);
+		data->time_reg[MONTHS] = dec_to_bcd(time.month, MONTHS_MASK);
 	}
 
 	data->time_reg[DAYS] = dec_to_bcd(time.day, DAYS_MASK);
@@ -223,7 +220,7 @@ static int nxp_rtc_pcf85063a_write_seconds(const struct device *dev,
 }
 
 static int nxp_rtc_pcf85063a_configure(const struct device *dev,
-				   cros_rtc_alarm_callback_t callback)
+				       cros_rtc_alarm_callback_t callback)
 {
 	struct nxp_rtc_pcf85063a_data *data = DRV_DATA(dev);
 
@@ -237,7 +234,7 @@ static int nxp_rtc_pcf85063a_configure(const struct device *dev,
 }
 
 static int nxp_rtc_pcf85063a_get_value(const struct device *dev,
-							uint32_t *value)
+				       uint32_t *value)
 {
 	return nxp_rtc_pcf85063a_read_seconds(dev, value, false);
 }
@@ -248,7 +245,8 @@ static int nxp_rtc_pcf85063a_set_value(const struct device *dev, uint32_t value)
 }
 
 static int nxp_rtc_pcf85063a_get_alarm(const struct device *dev,
-			uint32_t *seconds, uint32_t *microseconds)
+				       uint32_t *seconds,
+				       uint32_t *microseconds)
 {
 	*microseconds = 0;
 	return nxp_rtc_pcf85063a_read_seconds(dev, seconds, true);
@@ -275,7 +273,7 @@ static int nxp_rtc_pcf85063a_reset_alarm(const struct device *dev)
 }
 
 static int nxp_rtc_pcf85063a_set_alarm(const struct device *dev,
-			uint32_t seconds, uint32_t microseconds)
+				       uint32_t seconds, uint32_t microseconds)
 {
 	int ret;
 
@@ -297,7 +295,7 @@ static int nxp_rtc_pcf85063a_set_alarm(const struct device *dev,
 }
 
 static void nxp_pcf85063a_isr(const struct device *port,
-				struct gpio_callback *cb, uint32_t pin)
+			      struct gpio_callback *cb, uint32_t pin)
 {
 	struct nxp_rtc_pcf85063a_data *data =
 		CONTAINER_OF(cb, struct nxp_rtc_pcf85063a_data, gpio_cb);
@@ -400,8 +398,8 @@ static int nxp_rtc_pcf85063a_init(const struct device *dev)
 		return ret;
 	}
 
-	gpio_init_callback(&data->gpio_cb,
-			nxp_pcf85063a_isr, BIT(config->gpio_alert.pin));
+	gpio_init_callback(&data->gpio_cb, nxp_pcf85063a_isr,
+			   BIT(config->gpio_alert.pin));
 
 	ret = gpio_add_callback(config->gpio_alert.port, &data->gpio_cb);
 
@@ -416,8 +414,7 @@ static int nxp_rtc_pcf85063a_init(const struct device *dev)
 					       GPIO_INT_EDGE_FALLING);
 }
 
-#define PCF85063A_INT_GPIOS \
-	DT_PHANDLE(DT_NODELABEL(pcf85063a), int_pin)
+#define PCF85063A_INT_GPIOS DT_PHANDLE(DT_NODELABEL(pcf85063a), int_pin)
 
 /*
  * dt_flags is a uint8_t type.  However, for platform/ec
@@ -426,19 +423,17 @@ static int nxp_rtc_pcf85063a_init(const struct device *dev)
  * Cast back to a gpio_dt_flags to compile, discarding the bits
  * that are not supported by the Zephyr GPIO API.
  */
-#define CROS_EC_GPIO_DT_SPEC_GET(node_id, prop)                     \
-	{                                                           \
-		.port = DEVICE_DT_GET(DT_GPIO_CTLR(node_id, prop)), \
-		.pin = DT_GPIO_PIN(node_id, prop),                  \
-		.dt_flags =                                         \
-		(gpio_dt_flags_t)DT_GPIO_FLAGS(node_id, prop),      \
+#define CROS_EC_GPIO_DT_SPEC_GET(node_id, prop)                            \
+	{                                                                  \
+		.port = DEVICE_DT_GET(DT_GPIO_CTLR(node_id, prop)),        \
+		.pin = DT_GPIO_PIN(node_id, prop),                         \
+		.dt_flags = (gpio_dt_flags_t)DT_GPIO_FLAGS(node_id, prop), \
 	}
 
 static const struct nxp_rtc_pcf85063a_config nxp_rtc_pcf85063a_cfg_0 = {
 	.bus = DEVICE_DT_GET(DT_INST_BUS(0)),
 	.i2c_addr_flags = DT_INST_REG_ADDR(0),
-	.gpio_alert =
-		CROS_EC_GPIO_DT_SPEC_GET(PCF85063A_INT_GPIOS, gpios)
+	.gpio_alert = CROS_EC_GPIO_DT_SPEC_GET(PCF85063A_INT_GPIOS, gpios)
 };
 
 static struct nxp_rtc_pcf85063a_data nxp_rtc_pcf85063a_data_0;
diff --git a/zephyr/drivers/cros_rtc/nxp_rtc_pcf85063a.h b/zephyr/drivers/cros_rtc/nxp_rtc_pcf85063a.h
index dc4fcd24fc..54b1fbd2ea 100644
--- a/zephyr/drivers/cros_rtc/nxp_rtc_pcf85063a.h
+++ b/zephyr/drivers/cros_rtc/nxp_rtc_pcf85063a.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,53 +6,53 @@
 #ifndef __CROS_EC_RTC_PCF85063A_H
 #define __CROS_EC_RTC_PCF85063A_H
 
-#define PCF85063A_REG_NUM       18
-#define SOFT_RESET              0x58
+#define PCF85063A_REG_NUM 18
+#define SOFT_RESET 0x58
 #define CONTROL_1_DEFAULT_VALUE 0
-#define OS_BIT                  0x80
-#define DISABLE_ALARM           0x80
-#define ENABLE_ALARM_INTERRUPT	0x80
-#define RTC_STOP_CLOCKS		0x20
-#define RTC_START_CLOCKS	0x00
+#define OS_BIT 0x80
+#define DISABLE_ALARM 0x80
+#define ENABLE_ALARM_INTERRUPT 0x80
+#define RTC_STOP_CLOCKS 0x20
+#define RTC_START_CLOCKS 0x00
 
-#define NUM_TIMER_REGS       7
-#define NUM_ALARM_REGS       4
+#define NUM_TIMER_REGS 7
+#define NUM_ALARM_REGS 4
 
-#define REG_CONTROL_1        0x00
-#define REG_CONTROL_2        0x01
-#define REG_OFFSET           0x02
-#define REG_RAM_BYTE         0x03
-#define REG_SECONDS          0x04
-#define REG_MINUTES          0x05
-#define REG_HOURS            0x06
-#define REG_DAYS             0x07
-#define REG_WEEKDAYS         0x08
-#define REG_MONTHS           0x09
-#define REG_YEARS            0x0a
-#define REG_SECOND_ALARM     0x0b
-#define REG_MINUTE_ALARM     0x0c
-#define REG_HOUR_ALARM       0x0d
-#define REG_DAY_ALARM        0x0e
-#define REG_WEEKDAY_ALARM    0x0f
-#define REG_TIMER_VALUE      0x10
-#define REG_TIMER_MODE       0x11
+#define REG_CONTROL_1 0x00
+#define REG_CONTROL_2 0x01
+#define REG_OFFSET 0x02
+#define REG_RAM_BYTE 0x03
+#define REG_SECONDS 0x04
+#define REG_MINUTES 0x05
+#define REG_HOURS 0x06
+#define REG_DAYS 0x07
+#define REG_WEEKDAYS 0x08
+#define REG_MONTHS 0x09
+#define REG_YEARS 0x0a
+#define REG_SECOND_ALARM 0x0b
+#define REG_MINUTE_ALARM 0x0c
+#define REG_HOUR_ALARM 0x0d
+#define REG_DAY_ALARM 0x0e
+#define REG_WEEKDAY_ALARM 0x0f
+#define REG_TIMER_VALUE 0x10
+#define REG_TIMER_MODE 0x11
 
 /* Macros for indexing time_reg buffer */
-#define SECONDS           0
-#define MINUTES           1
-#define HOURS             2
-#define DAYS              3
-#define WEEKDAYS          4
-#define MONTHS            5
-#define YEARS             6
+#define SECONDS 0
+#define MINUTES 1
+#define HOURS 2
+#define DAYS 3
+#define WEEKDAYS 4
+#define MONTHS 5
+#define YEARS 6
 
 enum bcd_mask {
 	SECONDS_MASK = 0x70,
 	MINUTES_MASK = 0x70,
 	HOURS24_MASK = 0x30,
-	DAYS_MASK    = 0x30,
-	MONTHS_MASK  = 0x10,
-	YEARS_MASK   = 0xf0
+	DAYS_MASK = 0x30,
+	MONTHS_MASK = 0x10,
+	YEARS_MASK = 0xf0
 };
 
 #endif /* __CROS_EC_RTC_PCF85063A_H */
diff --git a/zephyr/drivers/cros_rtc/renesas_rtc_idt1337ag.c b/zephyr/drivers/cros_rtc/renesas_rtc_idt1337ag.c
index 661268ee9b..7a9a11fd41 100644
--- a/zephyr/drivers/cros_rtc/renesas_rtc_idt1337ag.c
+++ b/zephyr/drivers/cros_rtc/renesas_rtc_idt1337ag.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -43,8 +43,8 @@ enum timer_type {
  * type == RTC_TIMER: Reads time registers SECONDS, MINUTES, HOURS, DAYS, and
  *			MONTHS, YEARS
  */
-static int idt1337ag_read_time_regs(const struct device *dev,
-				    uint8_t *time_reg, enum timer_type type)
+static int idt1337ag_read_time_regs(const struct device *dev, uint8_t *time_reg,
+				    enum timer_type type)
 {
 	const struct renesas_rtc_idt1337ag_config *const config = dev->config;
 	uint8_t start_reg;
@@ -58,12 +58,12 @@ static int idt1337ag_read_time_regs(const struct device *dev,
 		num_reg = NUM_TIMER_REGS;
 	}
 
-	return i2c_burst_read(config->bus,
-		config->i2c_addr_flags, start_reg, time_reg, num_reg);
+	return i2c_burst_read(config->bus, config->i2c_addr_flags, start_reg,
+			      time_reg, num_reg);
 }
 
-static int idt1337ag_read_reg(const struct device *dev,
-			      uint8_t reg, uint8_t *val)
+static int idt1337ag_read_reg(const struct device *dev, uint8_t reg,
+			      uint8_t *val)
 {
 	const struct renesas_rtc_idt1337ag_config *const config = dev->config;
 
@@ -97,12 +97,12 @@ static int idt1337ag_write_time_regs(const struct device *dev,
 		num_reg = NUM_TIMER_REGS;
 	}
 
-	return i2c_burst_write(config->bus,
-			config->i2c_addr_flags, start_reg, time_reg, num_reg);
+	return i2c_burst_write(config->bus, config->i2c_addr_flags, start_reg,
+			       time_reg, num_reg);
 }
 
-static int idt1337ag_write_reg(const struct device *dev,
-			       uint8_t reg, uint8_t val)
+static int idt1337ag_write_reg(const struct device *dev, uint8_t reg,
+			       uint8_t val)
 {
 	const struct renesas_rtc_idt1337ag_config *const config = dev->config;
 	uint8_t tx_buf[2];
@@ -110,8 +110,8 @@ static int idt1337ag_write_reg(const struct device *dev,
 	tx_buf[0] = reg;
 	tx_buf[1] = val;
 
-	return i2c_write(config->bus,
-		tx_buf, sizeof(tx_buf), config->i2c_addr_flags);
+	return i2c_write(config->bus, tx_buf, sizeof(tx_buf),
+			 config->i2c_addr_flags);
 }
 
 /*
@@ -139,7 +139,8 @@ static uint8_t dec_to_bcd(uint32_t val, enum bcd_mask mask)
 }
 
 static int renesas_rtc_idt1337ag_read_seconds(const struct device *dev,
-					uint32_t *value, enum timer_type type)
+					      uint32_t *value,
+					      enum timer_type type)
 {
 	uint8_t time_reg[NUM_TIMER_REGS];
 	struct calendar_date time;
@@ -152,12 +153,12 @@ static int renesas_rtc_idt1337ag_read_seconds(const struct device *dev,
 	}
 
 	if (type == ALARM_TIMER) {
-		*value = (bcd_to_dec(time_reg[DAYS], DAYS_MASK) *
-				SECS_PER_DAY) +
+		*value =
+			(bcd_to_dec(time_reg[DAYS], DAYS_MASK) * SECS_PER_DAY) +
 			(bcd_to_dec(time_reg[HOURS], HOURS24_MASK) *
-				SECS_PER_HOUR) +
+			 SECS_PER_HOUR) +
 			(bcd_to_dec(time_reg[MINUTES], MINUTES_MASK) *
-				SECS_PER_MINUTE) +
+			 SECS_PER_MINUTE) +
 			bcd_to_dec(time_reg[SECONDS], SECONDS_MASK);
 	} else {
 		time.year = bcd_to_dec(time_reg[YEARS], YEARS_MASK);
@@ -165,18 +166,19 @@ static int renesas_rtc_idt1337ag_read_seconds(const struct device *dev,
 		time.day = bcd_to_dec(time_reg[DAYS], DAYS_MASK);
 
 		*value = date_to_sec(time) - SECS_TILL_YEAR_2K +
-			(bcd_to_dec(time_reg[HOURS], HOURS24_MASK) *
-				SECS_PER_HOUR) +
-			(bcd_to_dec(time_reg[MINUTES], MINUTES_MASK) *
-				SECS_PER_MINUTE) +
-			bcd_to_dec(time_reg[SECONDS], SECONDS_MASK);
+			 (bcd_to_dec(time_reg[HOURS], HOURS24_MASK) *
+			  SECS_PER_HOUR) +
+			 (bcd_to_dec(time_reg[MINUTES], MINUTES_MASK) *
+			  SECS_PER_MINUTE) +
+			 bcd_to_dec(time_reg[SECONDS], SECONDS_MASK);
 	}
 
 	return ret;
 }
 
 static int renesas_rtc_idt1337ag_write_seconds(const struct device *dev,
-					uint32_t value, enum timer_type type)
+					       uint32_t value,
+					       enum timer_type type)
 {
 	uint8_t time_reg[NUM_TIMER_REGS];
 	struct calendar_date time;
@@ -206,7 +208,7 @@ static int renesas_rtc_idt1337ag_write_seconds(const struct device *dev,
 }
 
 static int renesas_rtc_idt1337ag_configure(const struct device *dev,
-				   cros_rtc_alarm_callback_t callback)
+					   cros_rtc_alarm_callback_t callback)
 {
 	struct renesas_rtc_idt1337ag_data *data = dev->data;
 
@@ -232,7 +234,8 @@ static int renesas_rtc_idt1337ag_set_value(const struct device *dev,
 }
 
 static int renesas_rtc_idt1337ag_get_alarm(const struct device *dev,
-				uint32_t *seconds, uint32_t *microseconds)
+					   uint32_t *seconds,
+					   uint32_t *microseconds)
 {
 	*microseconds = 0;
 	return renesas_rtc_idt1337ag_read_seconds(dev, seconds, ALARM_TIMER);
@@ -283,7 +286,8 @@ static int renesas_rtc_idt1337ag_reset_alarm(const struct device *dev)
 }
 
 static int renesas_rtc_idt1337ag_set_alarm(const struct device *dev,
-				uint32_t seconds, uint32_t microseconds)
+					   uint32_t seconds,
+					   uint32_t microseconds)
 {
 	int ret;
 	uint8_t val;
@@ -429,8 +433,8 @@ static int renesas_rtc_idt1337ag_init(const struct device *dev)
 		return ret;
 	}
 
-	gpio_init_callback(&data->gpio_cb,
-			renesas_rtc_idt1337ag_isr, BIT(config->gpio_alert.pin));
+	gpio_init_callback(&data->gpio_cb, renesas_rtc_idt1337ag_isr,
+			   BIT(config->gpio_alert.pin));
 
 	ret = gpio_add_callback(config->gpio_alert.port, &data->gpio_cb);
 
@@ -445,8 +449,7 @@ static int renesas_rtc_idt1337ag_init(const struct device *dev)
 					       GPIO_INT_EDGE_FALLING);
 }
 
-#define IDT1337AG_INT_PIN \
-	DT_PHANDLE(DT_NODELABEL(idt1337ag), int_pin)
+#define IDT1337AG_INT_PIN DT_PHANDLE(DT_NODELABEL(idt1337ag), int_pin)
 
 /*
  * dt_flags is a uint8_t type.  However, for platform/ec
@@ -455,12 +458,11 @@ static int renesas_rtc_idt1337ag_init(const struct device *dev)
  * Cast back to a gpio_dt_flags to compile, discarding the bits
  * that are not supported by the Zephyr GPIO API.
  */
-#define CROS_EC_GPIO_DT_SPEC_GET(node_id, prop)                     \
-	{                                                           \
-		.port = DEVICE_DT_GET(DT_GPIO_CTLR(node_id, prop)), \
-		.pin = DT_GPIO_PIN(node_id, prop),                  \
-		.dt_flags =                                         \
-		(gpio_dt_flags_t)DT_GPIO_FLAGS(node_id, prop),      \
+#define CROS_EC_GPIO_DT_SPEC_GET(node_id, prop)                            \
+	{                                                                  \
+		.port = DEVICE_DT_GET(DT_GPIO_CTLR(node_id, prop)),        \
+		.pin = DT_GPIO_PIN(node_id, prop),                         \
+		.dt_flags = (gpio_dt_flags_t)DT_GPIO_FLAGS(node_id, prop), \
 	}
 
 static const struct renesas_rtc_idt1337ag_config renesas_rtc_idt1337ag_cfg_0 = {
@@ -473,6 +475,6 @@ static struct renesas_rtc_idt1337ag_data renesas_rtc_idt1337ag_data_0;
 
 DEVICE_DT_INST_DEFINE(0, renesas_rtc_idt1337ag_init, /* pm_control_fn= */ NULL,
 		      &renesas_rtc_idt1337ag_data_0,
-		      &renesas_rtc_idt1337ag_cfg_0,
-		      POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
+		      &renesas_rtc_idt1337ag_cfg_0, POST_KERNEL,
+		      CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
 		      &renesas_rtc_idt1337ag_driver_api);
diff --git a/zephyr/drivers/cros_rtc/renesas_rtc_idt1337ag.h b/zephyr/drivers/cros_rtc/renesas_rtc_idt1337ag.h
index 3296f80992..9dd195e8c3 100644
--- a/zephyr/drivers/cros_rtc/renesas_rtc_idt1337ag.h
+++ b/zephyr/drivers/cros_rtc/renesas_rtc_idt1337ag.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,54 +7,54 @@
 #define __CROS_EC_RTC_IDT1337AG_H
 
 /* Setting bit 6 of register 0Ah selects the DAY as alarm source */
-#define SELECT_DAYS_ALARM  0x40
-#define DISABLE_ALARM      0x80
-
-#define CONTROL_A1IE       BIT(0)
-#define CONTROL_A2IE       BIT(1)
-#define CONTROL_INTCN      BIT(2)
-#define CONTROL_EOSC       BIT(7)
-
-#define STATUS_A1F         BIT(0)
-#define STATUS_A2F         BIT(1)
-#define STATUS_OSF         BIT(7)
-
-#define NUM_TIMER_REGS       7
-#define NUM_ALARM_REGS       4
-
-#define REG_SECONDS        0x00
-#define REG_MINUTES        0x01
-#define REG_HOURS          0x02
-#define REG_DAYS           0x03
-#define REG_DATE           0x04
-#define REG_MONTHS         0x05
-#define REG_YEARS          0x06
-#define REG_SECOND_ALARM1  0x07
-#define REG_MINUTE_ALARM1  0x08
-#define REG_HOUR_ALARM1    0x09
-#define REG_DAY_ALARM1     0x0a
-#define REG_MINUTE_ALARM2  0x0b
-#define REG_HOUR_ALARM2    0x0c
-#define REG_DAY_ALARM2     0x0d
-#define REG_CONTROL        0x0e
-#define REG_STATUS         0x0f
+#define SELECT_DAYS_ALARM 0x40
+#define DISABLE_ALARM 0x80
+
+#define CONTROL_A1IE BIT(0)
+#define CONTROL_A2IE BIT(1)
+#define CONTROL_INTCN BIT(2)
+#define CONTROL_EOSC BIT(7)
+
+#define STATUS_A1F BIT(0)
+#define STATUS_A2F BIT(1)
+#define STATUS_OSF BIT(7)
+
+#define NUM_TIMER_REGS 7
+#define NUM_ALARM_REGS 4
+
+#define REG_SECONDS 0x00
+#define REG_MINUTES 0x01
+#define REG_HOURS 0x02
+#define REG_DAYS 0x03
+#define REG_DATE 0x04
+#define REG_MONTHS 0x05
+#define REG_YEARS 0x06
+#define REG_SECOND_ALARM1 0x07
+#define REG_MINUTE_ALARM1 0x08
+#define REG_HOUR_ALARM1 0x09
+#define REG_DAY_ALARM1 0x0a
+#define REG_MINUTE_ALARM2 0x0b
+#define REG_HOUR_ALARM2 0x0c
+#define REG_DAY_ALARM2 0x0d
+#define REG_CONTROL 0x0e
+#define REG_STATUS 0x0f
 
 /* Macros for indexing time_reg buffer */
-#define SECONDS           0
-#define MINUTES           1
-#define HOURS             2
-#define DAYS              3
-#define DATE              4
-#define MONTHS            5
-#define YEARS             6
+#define SECONDS 0
+#define MINUTES 1
+#define HOURS 2
+#define DAYS 3
+#define DATE 4
+#define MONTHS 5
+#define YEARS 6
 
 enum bcd_mask {
 	SECONDS_MASK = 0x70,
 	MINUTES_MASK = 0x70,
 	HOURS24_MASK = 0x30,
-	DAYS_MASK    = 0x00,
-	MONTHS_MASK  = 0x10,
-	YEARS_MASK   = 0xf0
+	DAYS_MASK = 0x00,
+	MONTHS_MASK = 0x10,
+	YEARS_MASK = 0xf0
 };
 
 #endif /* __CROS_EC_RTC_IDT1337AG_H */
diff --git a/zephyr/drivers/cros_shi/CMakeLists.txt b/zephyr/drivers/cros_shi/CMakeLists.txt
index f0b3c8bb5a..c4708f3551 100644
--- a/zephyr/drivers/cros_shi/CMakeLists.txt
+++ b/zephyr/drivers/cros_shi/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/drivers/cros_shi/Kconfig b/zephyr/drivers/cros_shi/Kconfig
index 8ca08b6b19..ebcd937c7d 100644
--- a/zephyr/drivers/cros_shi/Kconfig
+++ b/zephyr/drivers/cros_shi/Kconfig
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/drivers/cros_shi/cros_shi_it8xxx2.c b/zephyr/drivers/cros_shi/cros_shi_it8xxx2.c
index 3d0db3bc89..ee6ce3f7a4 100644
--- a/zephyr/drivers/cros_shi/cros_shi_it8xxx2.c
+++ b/zephyr/drivers/cros_shi/cros_shi_it8xxx2.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,12 +21,12 @@
 #include "host_command.h"
 
 /* Console output macros */
-#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SPI, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SPI, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SPI, format, ##args)
 
 LOG_MODULE_REGISTER(cros_shi, LOG_LEVEL_ERR);
 
-#define DRV_CONFIG(dev) ((struct cros_shi_it8xxx2_cfg * const)(dev)->config)
+#define DRV_CONFIG(dev) ((struct cros_shi_it8xxx2_cfg *const)(dev)->config)
 
 /*
  * Strcture cros_shi_it8xxx2_cfg is about the setting of SHI,
@@ -45,8 +45,8 @@ struct cros_shi_it8xxx2_cfg {
 
 /* Max data size for a version 3 request/response packet. */
 #define SPI_MAX_REQUEST_SIZE SPI_RX_MAX_FIFO_SIZE
-#define SPI_MAX_RESPONSE_SIZE (SPI_TX_MAX_FIFO_SIZE - \
-	EC_SPI_PREAMBLE_LENGTH - EC_SPI_PAST_END_LENGTH)
+#define SPI_MAX_RESPONSE_SIZE \
+	(SPI_TX_MAX_FIFO_SIZE - EC_SPI_PREAMBLE_LENGTH - EC_SPI_PAST_END_LENGTH)
 
 static const uint8_t out_preamble[EC_SPI_PREAMBLE_LENGTH] = {
 	EC_SPI_PROCESSING,
@@ -80,9 +80,9 @@ static enum shi_state_machine shi_state;
 
 static const int spi_response_state[] = {
 	[SPI_STATE_READY_TO_RECV] = EC_SPI_RX_READY,
-	[SPI_STATE_RECEIVING]     = EC_SPI_RECEIVING,
-	[SPI_STATE_PROCESSING]    = EC_SPI_PROCESSING,
-	[SPI_STATE_RX_BAD]        = EC_SPI_RX_BAD_DATA,
+	[SPI_STATE_RECEIVING] = EC_SPI_RECEIVING,
+	[SPI_STATE_PROCESSING] = EC_SPI_PROCESSING,
+	[SPI_STATE_RX_BAD] = EC_SPI_RX_BAD_DATA,
 };
 BUILD_ASSERT(ARRAY_SIZE(spi_response_state) == SPI_STATE_COUNT);
 
@@ -169,12 +169,12 @@ static void spi_send_response_packet(struct host_packet *pkt)
 
 	/* Append our past-end byte, which we reserved space for. */
 	for (int i = 0; i < EC_SPI_PAST_END_LENGTH; i++) {
-		((uint8_t *)pkt->response)[pkt->response_size + i]
-			= EC_SPI_PAST_END;
+		((uint8_t *)pkt->response)[pkt->response_size + i] =
+			EC_SPI_PAST_END;
 	}
 
 	tx_size = pkt->response_size + EC_SPI_PREAMBLE_LENGTH +
-			EC_SPI_PAST_END_LENGTH;
+		  EC_SPI_PAST_END_LENGTH;
 
 	/* Transmit the reply */
 	spi_response_host_data(out_msg, tx_size);
@@ -340,8 +340,8 @@ static int cros_shi_ite_init(const struct device *dev)
 	 * bit3 : Rx FIFO1 will not be overwrited once it's full.
 	 * bit0 : Rx FIFO1/FIFO2 will reset after each CS_N goes high.
 	 */
-	IT83XX_SPI_GCR2 = IT83XX_SPI_RXF2OC | IT83XX_SPI_RXF1OC
-				| IT83XX_SPI_RXFAR;
+	IT83XX_SPI_GCR2 = IT83XX_SPI_RXF2OC | IT83XX_SPI_RXF1OC |
+			  IT83XX_SPI_RXFAR;
 	/*
 	 * Interrupt mask register (0b:Enable, 1b:Mask)
 	 * bit5 : Rx byte reach interrupt mask
@@ -384,10 +384,8 @@ static const struct cros_shi_it8xxx2_cfg cros_shi_cfg = {
 	CONFIG_PLATFORM_EC_GPIO_INIT_PRIORITY
 #error "CROS_SHI must initialize after the GPIOs initialization"
 #endif
-DEVICE_DT_INST_DEFINE(0, cros_shi_ite_init, NULL,
-		      NULL, &cros_shi_cfg, POST_KERNEL,
-		      CONFIG_CROS_SHI_IT8XXX2_INIT_PRIORITY,
-		      NULL);
+DEVICE_DT_INST_DEFINE(0, cros_shi_ite_init, NULL, NULL, &cros_shi_cfg,
+		      POST_KERNEL, CONFIG_CROS_SHI_IT8XXX2_INIT_PRIORITY, NULL);
 
 /* Get protocol information */
 enum ec_status spi_get_protocol_info(struct host_cmd_handler_args *args)
@@ -404,6 +402,5 @@ enum ec_status spi_get_protocol_info(struct host_cmd_handler_args *args)
 
 	return EC_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO,
-		     spi_get_protocol_info,
+DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, spi_get_protocol_info,
 		     EC_VER_MASK(0));
diff --git a/zephyr/drivers/cros_shi/cros_shi_npcx.c b/zephyr/drivers/cros_shi/cros_shi_npcx.c
index b236980205..ce3279288b 100644
--- a/zephyr/drivers/cros_shi/cros_shi_npcx.c
+++ b/zephyr/drivers/cros_shi/cros_shi_npcx.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -810,7 +810,7 @@ static int cros_shi_npcx_disable(const struct device *dev)
 	}
 
 	ret = clock_control_off(clk_dev,
-			       (clock_control_subsys_t *)&config->clk_cfg);
+				(clock_control_subsys_t *)&config->clk_cfg);
 	if (ret < 0) {
 		DEBUG_CPRINTF("Turn off SHI clock fail %d", ret);
 		return ret;
diff --git a/zephyr/drivers/cros_system/CMakeLists.txt b/zephyr/drivers/cros_system/CMakeLists.txt
index b0d3730cbc..0838dca1ae 100644
--- a/zephyr/drivers/cros_system/CMakeLists.txt
+++ b/zephyr/drivers/cros_system/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/drivers/cros_system/Kconfig b/zephyr/drivers/cros_system/Kconfig
index 3f58f0eb21..80fc701285 100644
--- a/zephyr/drivers/cros_system/Kconfig
+++ b/zephyr/drivers/cros_system/Kconfig
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/drivers/cros_system/cros_system_it8xxx2.c b/zephyr/drivers/cros_system/cros_system_it8xxx2.c
index 693b981e83..8c63886808 100644
--- a/zephyr/drivers/cros_system/cros_system_it8xxx2.c
+++ b/zephyr/drivers/cros_system/cros_system_it8xxx2.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -36,8 +36,7 @@ static uint32_t system_get_chip_id(void)
 	struct gctrl_it8xxx2_regs *const gctrl_base = GCTRL_IT8XXX2_REG_BASE;
 
 	return (gctrl_base->GCTRL_ECHIPID1 << 16) |
-		(gctrl_base->GCTRL_ECHIPID2 << 8) |
-		gctrl_base->GCTRL_ECHIPID3;
+	       (gctrl_base->GCTRL_ECHIPID2 << 8) | gctrl_base->GCTRL_ECHIPID3;
 }
 
 static uint8_t system_get_chip_version(void)
@@ -52,26 +51,26 @@ static const char *cros_system_it8xxx2_get_chip_name(const struct device *dev)
 {
 	ARG_UNUSED(dev);
 
-	static char buf[8] = {'i', 't'};
+	static char buf[8] = { 'i', 't' };
 	uint32_t chip_id = system_get_chip_id();
 	int num = 4;
 
 	for (int n = 2; num >= 0; n++, num--)
-		snprintf(buf+n, (sizeof(buf)-n), "%x",
+		snprintf(buf + n, (sizeof(buf) - n), "%x",
 			 chip_id >> (num * 4) & 0xF);
 
 	return buf;
 }
 
-static const char *cros_system_it8xxx2_get_chip_revision(const struct device
-							 *dev)
+static const char *
+cros_system_it8xxx2_get_chip_revision(const struct device *dev)
 {
 	ARG_UNUSED(dev);
 
 	static char buf[3];
 	uint8_t rev = system_get_chip_version();
 
-	snprintf(buf, sizeof(buf), "%1xx", rev+0xa);
+	snprintf(buf, sizeof(buf), "%1xx", rev + 0xa);
 
 	return buf;
 }
@@ -81,9 +80,10 @@ static int cros_system_it8xxx2_get_reset_cause(const struct device *dev)
 	ARG_UNUSED(dev);
 	struct gctrl_it8xxx2_regs *const gctrl_base = GCTRL_IT8XXX2_REG_BASE;
 	uint8_t last_reset_source = gctrl_base->GCTRL_RSTS & IT8XXX2_GCTRL_LRS;
-	uint8_t raw_reset_cause2 = gctrl_base->GCTRL_SPCTRL4 &
+	uint8_t raw_reset_cause2 =
+		gctrl_base->GCTRL_SPCTRL4 &
 		(IT8XXX2_GCTRL_LRSIWR | IT8XXX2_GCTRL_LRSIPWRSWTR |
-		IT8XXX2_GCTRL_LRSIPGWR);
+		 IT8XXX2_GCTRL_LRSIPGWR);
 
 	/* Clear reset cause. */
 	gctrl_base->GCTRL_RSTS |= IT8XXX2_GCTRL_LRS;
@@ -185,8 +185,8 @@ static int cros_system_it8xxx2_hibernate(const struct device *dev,
 		 * Convert milliseconds(or at least 1 ms) to 32 Hz
 		 * free run timer count for hibernate.
 		 */
-		uint32_t c = (seconds * 1000 + microseconds / 1000 + 1) *
-				32 / 1000;
+		uint32_t c =
+			(seconds * 1000 + microseconds / 1000 + 1) * 32 / 1000;
 
 		/* Enable a 32-bit timer and clock source is 32 Hz */
 		/* Disable external timer x */
@@ -205,7 +205,7 @@ static int cros_system_it8xxx2_hibernate(const struct device *dev,
 /*
  * Get the interrupt DTS node for this wakeup pin
  */
-#define WAKEUP_INT(id, prop, idx)  DT_PHANDLE_BY_IDX(id, prop, idx)
+#define WAKEUP_INT(id, prop, idx) DT_PHANDLE_BY_IDX(id, prop, idx)
 
 /*
  * Get the named-gpio node for this wakeup pin by reading the
@@ -217,19 +217,19 @@ static int cros_system_it8xxx2_hibernate(const struct device *dev,
 /*
  * Reset and re-enable interrupts on this wake pin.
  */
-#define WAKEUP_SETUP(id, prop, idx)					       \
-do {									       \
-	gpio_pin_configure_dt(GPIO_DT_FROM_NODE(WAKEUP_NGPIO(id, prop, idx)),  \
-			      GPIO_INPUT);				       \
-	gpio_enable_dt_interrupt(					       \
-		GPIO_INT_FROM_NODE(WAKEUP_INT(id, prop, idx)));	       \
+#define WAKEUP_SETUP(id, prop, idx)                                     \
+	do {                                                            \
+		gpio_pin_configure_dt(                                  \
+			GPIO_DT_FROM_NODE(WAKEUP_NGPIO(id, prop, idx)), \
+			GPIO_INPUT);                                    \
+		gpio_enable_dt_interrupt(                               \
+			GPIO_INT_FROM_NODE(WAKEUP_INT(id, prop, idx))); \
 	} while (0);
 
-/*
- * For all the wake-pins, re-init the GPIO and re-enable the interrupt.
- */
-	DT_FOREACH_PROP_ELEM(SYSTEM_DT_NODE_HIBERNATE_CONFIG,
-			     wakeup_irqs,
+	/*
+	 * For all the wake-pins, re-init the GPIO and re-enable the interrupt.
+	 */
+	DT_FOREACH_PROP_ELEM(SYSTEM_DT_NODE_HIBERNATE_CONFIG, wakeup_irqs,
 			     WAKEUP_SETUP);
 
 #undef WAKEUP_INT
@@ -242,7 +242,7 @@ do {									       \
 	chip_pll_ctrl(CHIP_PLL_SLEEP);
 
 	/* Chip sleep and wait timer wake it up */
-	__asm__ volatile ("wfi");
+	__asm__ volatile("wfi");
 
 	/* Reset EC when wake up from sleep mode (system hibernate) */
 	system_reset(SYSTEM_RESET_HIBERNATE);
diff --git a/zephyr/drivers/cros_system/cros_system_npcx.c b/zephyr/drivers/cros_system/cros_system_npcx.c
index 2952831cee..4ab21ca549 100644
--- a/zephyr/drivers/cros_system/cros_system_npcx.c
+++ b/zephyr/drivers/cros_system/cros_system_npcx.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -82,7 +82,7 @@ struct cros_system_npcx_data {
 #define NPCX_RAM_BLOCK_PD_MASK (BIT(NPCX_RAM_PD_DEPTH) - 1)
 
 /* Get saved reset flag address in battery-backed ram */
-#define BBRAM_SAVED_RESET_FLAG_ADDR                         \
+#define BBRAM_SAVED_RESET_FLAG_ADDR                    \
 	(DT_REG_ADDR(DT_INST(0, nuvoton_npcx_bbram)) + \
 	 DT_PROP(DT_PATH(named_bbram_regions, saved_reset_flags), offset))
 
@@ -90,8 +90,8 @@ struct cros_system_npcx_data {
 static int system_npcx_watchdog_stop(void)
 {
 	if (IS_ENABLED(CONFIG_WATCHDOG)) {
-		const struct device *wdt_dev = DEVICE_DT_GET(
-				DT_NODELABEL(twd0));
+		const struct device *wdt_dev =
+			DEVICE_DT_GET(DT_NODELABEL(twd0));
 		if (!device_is_ready(wdt_dev)) {
 			LOG_ERR("Error: device %s is not ready", wdt_dev->name);
 			return -ENODEV;
@@ -182,7 +182,7 @@ static void system_npcx_set_wakeup_gpios_before_hibernate(void)
 /*
  * Get the interrupt DTS node for this wakeup pin
  */
-#define WAKEUP_INT(id, prop, idx)  DT_PHANDLE_BY_IDX(id, prop, idx)
+#define WAKEUP_INT(id, prop, idx) DT_PHANDLE_BY_IDX(id, prop, idx)
 
 /*
  * Get the named-gpio node for this wakeup pin by reading the
@@ -194,19 +194,19 @@ static void system_npcx_set_wakeup_gpios_before_hibernate(void)
 /*
  * Reset and re-enable interrupts on this wake pin.
  */
-#define WAKEUP_SETUP(id, prop, idx)		\
-do {									       \
-	gpio_pin_configure_dt(GPIO_DT_FROM_NODE(WAKEUP_NGPIO(id, prop, idx)),  \
-			      GPIO_INPUT);				       \
-	gpio_enable_dt_interrupt(					       \
-		GPIO_INT_FROM_NODE(WAKEUP_INT(id, prop, idx)));	       \
+#define WAKEUP_SETUP(id, prop, idx)                                     \
+	do {                                                            \
+		gpio_pin_configure_dt(                                  \
+			GPIO_DT_FROM_NODE(WAKEUP_NGPIO(id, prop, idx)), \
+			GPIO_INPUT);                                    \
+		gpio_enable_dt_interrupt(                               \
+			GPIO_INT_FROM_NODE(WAKEUP_INT(id, prop, idx))); \
 	} while (0);
 
-/*
- * For all the wake-pins, re-init the GPIO and re-enable the interrupt.
- */
-	DT_FOREACH_PROP_ELEM(SYSTEM_DT_NODE_HIBERNATE_CONFIG,
-			     wakeup_irqs,
+	/*
+	 * For all the wake-pins, re-init the GPIO and re-enable the interrupt.
+	 */
+	DT_FOREACH_PROP_ELEM(SYSTEM_DT_NODE_HIBERNATE_CONFIG, wakeup_irqs,
 			     WAKEUP_SETUP);
 
 #undef WAKEUP_INT
@@ -412,11 +412,42 @@ static const char *cros_system_npcx_get_chip_revision(const struct device *dev)
 	return rev;
 }
 
+#define PSL_NODE DT_INST(0, nuvoton_npcx_power_psl)
+#if DT_NODE_HAS_STATUS(PSL_NODE, okay)
+PINCTRL_DT_DEFINE(PSL_NODE);
+static int cros_system_npcx_configure_psl_in(void)
+{
+	const struct pinctrl_dev_config *pcfg =
+		PINCTRL_DT_DEV_CONFIG_GET(PSL_NODE);
+
+	return pinctrl_apply_state(pcfg, PINCTRL_STATE_SLEEP);
+}
+
+static void cros_system_npcx_psl_out_inactive(void)
+{
+	struct gpio_dt_spec enable = GPIO_DT_SPEC_GET(PSL_NODE, enable_gpios);
+
+	gpio_pin_set_dt(&enable, 1);
+}
+#else
+static int cros_system_npcx_configure_psl_in(void)
+{
+	return -EINVAL;
+}
+
+static void cros_system_npcx_psl_out_inactive(void)
+{
+	return;
+}
+#endif
+
 static void system_npcx_hibernate_by_psl(const struct device *dev,
 					 uint32_t seconds,
 					 uint32_t microseconds)
 {
 	ARG_UNUSED(dev);
+	int ret;
+
 	/*
 	 * TODO(b/178230662): RTC wake-up in PSL mode only support in npcx9
 	 * series. Nuvoton will introduce CLs for it later.
@@ -424,11 +455,12 @@ static void system_npcx_hibernate_by_psl(const struct device *dev,
 	ARG_UNUSED(seconds);
 	ARG_UNUSED(microseconds);
 
-	/*
-	 * Configure PSL input pads from "psl-in-pads" property in device tree
-	 * file.
-	 */
-	npcx_pinctrl_psl_input_configure();
+	/* Configure detection settings of PSL_IN pads first */
+	ret = cros_system_npcx_configure_psl_in();
+	if (ret < 0) {
+		LOG_ERR("PSL_IN pinctrl setup failed (%d)", ret);
+		return;
+	}
 
 	/*
 	 * Give the board a chance to do any late stage hibernation work.  This
@@ -439,8 +471,12 @@ static void system_npcx_hibernate_by_psl(const struct device *dev,
 	if (board_hibernate_late)
 		board_hibernate_late();
 
-	/* Turn off VCC1 to enter ultra-low-power mode for hibernating */
-	npcx_pinctrl_psl_output_set_inactive();
+	/*
+	 * A transition from 0 to 1 of specific IO (GPIO85) data-out bit
+	 * set PSL_OUT to inactive state. Then, it will turn Core Domain
+	 * power supply (VCC1) off for better power consumption.
+	 */
+	cros_system_npcx_psl_out_inactive();
 }
 
 static int cros_system_npcx_get_reset_cause(const struct device *dev)
@@ -460,8 +496,8 @@ static int cros_system_npcx_init(const struct device *dev)
 	data->reset = UNKNOWN_RST;
 	/* Use scratch bit to check power on reset or VCC1_RST reset. */
 	if (!IS_BIT_SET(inst_scfg->RSTCTL, NPCX_RSTCTL_VCC1_RST_SCRATCH)) {
-		bool is_vcc1_rst = IS_BIT_SET(inst_scfg->RSTCTL,
-				       NPCX_RSTCTL_VCC1_RST_STS);
+		bool is_vcc1_rst =
+			IS_BIT_SET(inst_scfg->RSTCTL, NPCX_RSTCTL_VCC1_RST_STS);
 		data->reset = is_vcc1_rst ? VCC1_RST_PIN : POWERUP;
 	}
 
@@ -526,8 +562,8 @@ static int cros_system_npcx_soc_reset(const struct device *dev)
 #error "cros-ec,hibernate-wake-pins cannot be used with HIBERNATE_PSL"
 #endif
 #else
-#if DT_HAS_COMPAT_STATUS_OKAY(nuvoton_npcx_pslctrl_def)
-#error "vsby-psl-in-list cannot be used with non-HIBERNATE_PSL"
+#if DT_NODE_HAS_STATUS(PSL_NODE, okay)
+#error "power_ctrl_psl cannot be used with non-HIBERNATE_PSL"
 #endif
 #endif
 
@@ -587,9 +623,9 @@ DEVICE_DEFINE(cros_system_npcx_0, "CROS_SYSTEM", cros_system_npcx_init, NULL,
 #define HAL_DBG_REG_BASE_ADDR \
 	((struct dbg_reg *)DT_REG_ADDR(DT_INST(0, nuvoton_npcx_cros_dbg)))
 
-#define DBG_NODE           DT_NODELABEL(dbg)
-#define DBG_PINCTRL_PH     DT_PHANDLE_BY_IDX(DBG_NODE, pinctrl_0, 0)
-#define DBG_ALT_FILED(f)   DT_PHA_BY_IDX(DBG_PINCTRL_PH, alts, 0, f)
+#define DBG_NODE DT_NODELABEL(dbg)
+#define DBG_PINCTRL_PH DT_PHANDLE_BY_IDX(DBG_NODE, pinctrl_0, 0)
+#define DBG_ALT_FILED(f) DT_PHA_BY_IDX(DBG_PINCTRL_PH, alts, 0, f)
 
 PINCTRL_DT_DEFINE(DBG_NODE);
 
diff --git a/zephyr/drivers/cros_system/cros_system_xec.c b/zephyr/drivers/cros_system/cros_system_xec.c
index 8d0c8f864c..a3cf9aea22 100644
--- a/zephyr/drivers/cros_system/cros_system_xec.c
+++ b/zephyr/drivers/cros_system/cros_system_xec.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,9 +13,42 @@
 
 #include "system.h"
 #include "system_chip.h"
+#include <zephyr/drivers/interrupt_controller/intc_mchp_xec_ecia.h>
+#include "gpio/gpio_int.h"
 
 LOG_MODULE_REGISTER(cros_system, LOG_LEVEL_ERR);
 
+/* Modules Map */
+#define STRUCT_ADC_REG_BASE_ADDR \
+	((struct adc_regs *)(DT_REG_ADDR(DT_NODELABEL(adc0))))
+
+#define STRUCT_UART_REG_BASE_ADDR \
+	((struct uart_regs *)(DT_REG_ADDR(DT_NODELABEL(uart0))))
+
+#define STRUCT_ECS_REG_BASE_ADDR \
+	((struct ecs_regs *)(DT_REG_ADDR(DT_NODELABEL(ecs))))
+
+#define STRUCT_TIMER4_REG_BASE_ADDR \
+	((struct btmr_regs *)(DT_REG_ADDR(DT_NODELABEL(timer4))))
+
+#define STRUCT_ESPI_REG_BASE_ADDR \
+	((struct espi_iom_regs *)(DT_REG_ADDR(DT_NODELABEL(espi0))))
+
+#define STRUCT_KBD_REG_BASE_ADDR \
+	((struct kscan_regs *)(DT_REG_ADDR(DT_NODELABEL(cros_kb_raw))))
+
+#define STRUCT_QMSPI_REG_BASE_ADDR \
+	((struct qmspi_regs *)(DT_REG_ADDR(DT_NODELABEL(spi0))))
+
+#define STRUCT_PWM_REG_BASE_ADDR \
+	((struct pwm_regs *)(DT_REG_ADDR(DT_NODELABEL(pwm0))))
+
+#define STRUCT_TACH_REG_BASE_ADDR \
+	((struct tach_regs *)(DT_REG_ADDR(DT_NODELABEL(tach0))))
+
+#define STRUCT_HTMR0_REG_BASE_ADDR \
+	((struct htmr_regs *)(DT_REG_ADDR(DT_NODELABEL(hibtimer0))))
+
 /* Driver config */
 struct cros_system_xec_config {
 	/* hardware module base address */
@@ -38,7 +71,7 @@ struct cros_system_xec_data {
 #define HAL_WDOG_INST(dev) (struct wdt_regs *)(DRV_CONFIG(dev)->base_wdog)
 
 /* Get saved reset flag address in battery-backed ram */
-#define BBRAM_SAVED_RESET_FLAG_ADDR                         \
+#define BBRAM_SAVED_RESET_FLAG_ADDR                     \
 	(DT_REG_ADDR(DT_INST(0, microchip_xec_bbram)) + \
 	 DT_PROP(DT_PATH(named_bbram_regions, saved_reset_flags), offset))
 
@@ -46,8 +79,8 @@ struct cros_system_xec_data {
 static int system_xec_watchdog_stop(void)
 {
 	if (IS_ENABLED(CONFIG_WATCHDOG)) {
-		const struct device *wdt_dev = DEVICE_DT_GET(
-				DT_NODELABEL(wdog));
+		const struct device *wdt_dev =
+			DEVICE_DT_GET(DT_NODELABEL(wdog));
 		if (!device_is_ready(wdt_dev)) {
 			LOG_ERR("Error: device %s is not ready", wdt_dev->name);
 			return -ENODEV;
@@ -120,6 +153,8 @@ noreturn static int cros_system_xec_soc_reset(const struct device *dev)
 
 	/* Disable interrupts to avoid task swaps during reboot */
 	interrupt_disable_all();
+	/* Stop the watchdog */
+	system_xec_watchdog_stop();
 
 	/* Trigger chip reset */
 	pcr->SYS_RST |= MCHP_PCR_SYS_RESET_NOW;
@@ -130,20 +165,254 @@ noreturn static int cros_system_xec_soc_reset(const struct device *dev)
 	/* return 0; */
 }
 
-static int cros_system_xec_hibernate(const struct device *dev,
-				     uint32_t seconds, uint32_t microseconds)
+/* Configure wakeup GPIOs in hibernate (from hibernate-wake-pins). */
+static void system_xec_set_wakeup_gpios_before_hibernate(void)
+{
+#if DT_NODE_EXISTS(SYSTEM_DT_NODE_HIBERNATE_CONFIG)
+
+/*
+ * Get the interrupt DTS node for this wakeup pin
+ */
+#define WAKEUP_INT(id, prop, idx) DT_PHANDLE_BY_IDX(id, prop, idx)
+
+/*
+ * Get the named-gpio node for this wakeup pin by reading the
+ * irq-gpio property from the interrupt node.
+ */
+#define WAKEUP_NGPIO(id, prop, idx) \
+	DT_PHANDLE(WAKEUP_INT(id, prop, idx), irq_pin)
+
+/*
+ * Reset and re-enable interrupts on this wake pin.
+ */
+#define WAKEUP_SETUP(id, prop, idx)                                     \
+	do {                                                            \
+		gpio_pin_configure_dt(                                  \
+			GPIO_DT_FROM_NODE(WAKEUP_NGPIO(id, prop, idx)), \
+			GPIO_INPUT);                                    \
+		gpio_enable_dt_interrupt(                               \
+			GPIO_INT_FROM_NODE(WAKEUP_INT(id, prop, idx))); \
+	} while (0);
+
+	/*
+	 * For all the wake-pins, re-init the GPIO and re-enable the interrupt.
+	 */
+	DT_FOREACH_PROP_ELEM(SYSTEM_DT_NODE_HIBERNATE_CONFIG, wakeup_irqs,
+			     WAKEUP_SETUP);
+
+#undef WAKEUP_INT
+#undef WAKEUP_NGPIO
+#undef WAKEUP_SETUP
+
+#endif
+}
+
+/**
+ * initialization of Hibernation timer 0
+ * GIRQ=23, aggregator bit = 16, Direct NVIC = 112
+ * NVIC direct connect interrupts are used for all peripherals
+ * (exception GPIO's)
+ */
+static void htimer_init(void)
+{
+	struct htmr_regs *htmr0 = STRUCT_HTMR0_REG_BASE_ADDR;
+
+	/* disable HT0 at beginning */
+	htmr0->PRLD = 0U;
+	mchp_soc_ecia_girq_src_clr(MCHP_GIRQ23_ID, MCHP_HTMR_0_GIRQ_POS);
+	mchp_soc_ecia_girq_src_en(MCHP_GIRQ23_ID, MCHP_HTMR_0_GIRQ_POS);
+
+	/* enable NVIC interrupt for HT0 */
+	irq_enable(MCHP_HTMR_0_GIRQ_NVIC_DIRECT);
+}
+
+/**
+ * Use hibernate module to set up an htimer interrupt at a given
+ * time from now
+ *
+ * @param seconds      Number of seconds before htimer interrupt
+ * @param microseconds Number of microseconds before htimer interrupt
+ * @note hibernation timer input clock is 32.768KHz.
+ */
+static void system_set_htimer_alarm(uint32_t seconds, uint32_t microseconds)
+{
+	uint32_t hcnt, ns;
+	uint8_t hctrl;
+	struct htmr_regs *htmr0 = STRUCT_HTMR0_REG_BASE_ADDR;
+
+	/* disable HT0 */
+	htmr0->PRLD = 0U;
+
+	if (microseconds > 1000000ul) {
+		ns = (microseconds / 1000000ul);
+		microseconds %= 1000000ul;
+		if ((0xfffffffful - seconds) > ns)
+			seconds += ns;
+		else
+			seconds = 0xfffffffful;
+	}
+
+	/*
+	 * Hibernation timer input clock is 32.768KHz.
+	 * Control register bit[0] selects the divider.
+	 * If bit[0] is 0, divide by 1 for 30.5 us per LSB for a maximum of
+	 * 65535 * 30.5 us = 1998817.5 us or 32.786 counts per second
+	 * If bit[0] is 1, divide by 4096 for 0.125 s per LSB for a maximum
+	 * of ~2 hours, 65535 * 0.125 s ~ 8192 s = 2.27 hours
+	 */
+	if (seconds > 1) {
+		hcnt = (seconds << 3); /* divide by 0.125 */
+		if (hcnt > 0xfffful)
+			hcnt = 0xfffful;
+		hctrl = 1;
+	} else {
+		/*
+		 * approximate(~2% error) as seconds is 0 or 1
+		 * seconds / 30.5e-6 + microseconds / 30.5
+		 */
+		hcnt = (seconds << 15) + (microseconds >> 5) +
+		       (microseconds >> 10);
+		hctrl = 0;
+	}
+
+	htmr0->CTRL = hctrl;
+	htmr0->PRLD = hcnt;
+}
+
+/* Put the EC in hibernate (lowest EC power state). */
+noreturn static int cros_system_xec_hibernate(const struct device *dev,
+					      uint32_t seconds,
+					      uint32_t microseconds)
 {
+	struct pcr_regs *const pcr = HAL_PCR_INST(dev);
+#ifdef CONFIG_ADC_XEC_V2
+	struct adc_regs *adc0 = STRUCT_ADC_REG_BASE_ADDR;
+#endif
+#ifdef CONFIG_UART_XEC
+	struct uart_regs *uart0 = STRUCT_UART_REG_BASE_ADDR;
+#endif
+	struct ecs_regs *ecs = STRUCT_ECS_REG_BASE_ADDR;
+	struct btmr_regs *btmr4 = STRUCT_TIMER4_REG_BASE_ADDR;
+	struct espi_iom_regs *espi0 = STRUCT_ESPI_REG_BASE_ADDR;
+#ifdef CONFIG_CROS_KB_RAW_XEC
+	struct kscan_regs *kbd = STRUCT_KBD_REG_BASE_ADDR;
+#endif
+	struct qmspi_regs *qmspi0 = STRUCT_QMSPI_REG_BASE_ADDR;
+#if defined(CONFIG_PWM_XEC)
+	struct pwm_regs *pwm0 = STRUCT_PWM_REG_BASE_ADDR;
+#endif
+#if defined(CONFIG_TACH_XEC)
+	struct tach_regs *tach0 = STRUCT_TACH_REG_BASE_ADDR;
+#endif
+	struct ecia_regs *ecia = (struct ecia_regs *)(ECIA_BASE_ADDR);
+	int i;
+
 	/* Disable interrupt first */
 	interrupt_disable_all();
-
 	/* Stop the watchdog */
 	system_xec_watchdog_stop();
 
-	/* Enter hibernate mode */
+	/* Disable all individaul block interrupt and source */
+	for (i = 0; i < MCHP_GIRQ_IDX_MAX; ++i) {
+		ecia->GIRQ[i].EN_CLR = 0xffffffff;
+		ecia->GIRQ[i].SRC = 0xffffffff;
+	}
 
-	/* MCHP TODO */
+	/* Disable and clear all NVIC interrupt pending */
+	for (i = 0; i < MCHP_MAX_NVIC_EXT_INPUTS; ++i) {
+		mchp_xec_ecia_nvic_clr_pend(i);
+	}
 
-	return 0;
+	/* Disable blocks */
+#ifdef CONFIG_ADC_XEC_V2
+	/* Disable ADC */
+	adc0->CONTROL &= ~(MCHP_ADC_CTRL_ACTV);
+#endif
+	/* Disable eSPI */
+	espi0->ACTV &= ~0x01;
+#ifdef CONFIG_CROS_KB_RAW_XEC
+	/* Disable Keyboard Scanner */
+	kbd->KSO_SEL &= ~(MCHP_KSCAN_KSO_EN);
+#endif
+#ifdef CONFIG_I2C
+	/* Disable SMB / I2C */
+	for (i = 0; i < MCHP_I2C_SMB_INSTANCES; i++) {
+		uint32_t addr =
+			MCHP_I2C_SMB_BASE_ADDR(i) + MCHP_I2C_SMB_CFG_OFS;
+		uint32_t regval = sys_read32(addr);
+
+		sys_write32(regval & ~(MCHP_I2C_SMB_CFG_ENAB), addr);
+	}
+#endif
+	/* Disable QMSPI */
+	qmspi0->MODE &= ~MCHP_QMSPI_M_ACTIVATE;
+#if defined(CONFIG_PWM_XEC)
+	/* Disable PWM0 */
+	pwm0->CONFIG &= ~MCHP_PWM_CFG_ENABLE;
+#endif
+#if defined(CONFIG_TACH_XEC)
+	/* Disable TACH0 */
+	tach0->CONTROL &= ~MCHP_TACH_CTRL_EN;
+#endif
+#if defined(CONFIG_TACH_XEC) || defined(CONFIG_PWM_XEC)
+	/* This low-speed clock derived from the 48MHz clock domain is used as
+	 * a time base for PWMs and TACHs
+	 * Set SLOW_CLOCK_DIVIDE = CLKOFF to save additional power
+	 */
+	pcr->SLOW_CLK_CTRL &=
+		(~MCHP_PCR_SLOW_CLK_CTRL_100KHZ & MCHP_PCR_SLOW_CLK_CTRL_MASK);
+#endif
+	/* Disable timers - 32bit timer 0 */
+	btmr4->CTRL &= ~MCHP_BTMR_CTRL_ENABLE;
+	/*
+	 * Give the board a chance to do any late stage hibernation work.  This
+	 * is likely going to configure GPIOs for hibernation.  On some boards,
+	 * it's possible that this may not return at all.  On those boards,
+	 * power to the EC is likely being turn off entirely.
+	 */
+	if (board_hibernate_late) {
+		board_hibernate_late();
+	}
+
+	/* Setup wakeup GPIOs for hibernate */
+	system_xec_set_wakeup_gpios_before_hibernate();
+	/* Init htimer and enable interrupt if times are not 0 */
+	if (seconds || microseconds) {
+		htimer_init();
+		system_set_htimer_alarm(seconds, microseconds);
+	}
+
+#ifdef CONFIG_UART_XEC
+	/* Disable UART0 */
+	/* Flush console before hibernating */
+	cflush();
+	uart0->ACTV &= ~(MCHP_UART_LD_ACTIVATE);
+#endif
+
+	/* Disable JATG and RTM */
+	ecs->DEBUG_CTRL = 0;
+	ecs->ETM_CTRL = 0;
+
+	/*
+	 * Set sleep state
+	 * arm sleep state to trigger on next WFI
+	 */
+	pcr->SYS_SLP_CTRL |= MCHP_PCR_SYS_SLP_HEAVY;
+	/*
+	 * Set PRIMASK = 1 so on wake the CPU will not vector to any ISR.
+	 * Set BASEPRI = 0 to allow any priority to wake.
+	 */
+	__set_BASEPRI(0);
+	/* triggers sleep hardware */
+	__WFI();
+	__NOP();
+	__NOP();
+
+	/* Reset EC chip */
+	cros_system_xec_soc_reset(dev);
+
+	/* Should not reach here... */
+	/* return 0; */
 }
 
 static struct cros_system_xec_data cros_system_xec_dev_data;
diff --git a/zephyr/dts/bindings/adc/named-adc.yaml b/zephyr/dts/bindings/adc/named-adc-channels.yaml
index 80ae9d145f..f1b6f19790 100644
--- a/zephyr/dts/bindings/adc/named-adc.yaml
+++ b/zephyr/dts/bindings/adc/named-adc-channels.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -9,11 +9,6 @@ compatible: "named-adc-channels"
 child-binding:
   description: Named ADCs child node
   properties:
-    label:
-      required: true
-      type: string
-      description:
-        String used to describe an ADC channel in the 'adc' console command.
     io-channels:
       required: true
       type: phandle-array
diff --git a/zephyr/dts/bindings/battery/aec,5477109.yaml b/zephyr/dts/bindings/battery/aec,5477109.yaml
index ca0ce51eb1..3cb8e44135 100644
--- a/zephyr/dts/bindings/battery/aec,5477109.yaml
+++ b/zephyr/dts/bindings/battery/aec,5477109.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/battery/atl,cfd72.yaml b/zephyr/dts/bindings/battery/atl,cfd72.yaml
new file mode 100644
index 0000000000..0f5c4ba511
--- /dev/null
+++ b/zephyr/dts/bindings/battery/atl,cfd72.yaml
@@ -0,0 +1,53 @@
+description: "ATL-NVT ATL-ATL3.66 DELL CFD72"
+compatible: "atl,cfd72"
+
+include: battery-smart.yaml
+
+properties:
+   enum-name:
+      type: string
+      default: "atl,cfd72"
+
+   # Fuel Gauge
+   manuf_name:
+      default: "ATL-ATL3.66"
+   device_name:
+      default: "DELL CFD72"
+   ship_mode_reg_addr:
+      default: 0x00
+   ship_mode_reg_data:
+      default: [ 0x0010, 0x0010 ]
+   fet_mfgacc_support:
+      default: 0
+   fet_reg_addr:
+      default: 0x43
+   fet_reg_mask:
+      default: 0x0001
+   fet_disconnect_val:
+      default: 0x0000
+   fet_cfet_mask:
+      default: 0x0002
+   fet_cfet_off_val:
+      default: 0x0000
+
+   # Battery info
+   voltage_max:
+      default: 17600
+   voltage_normal:
+      default: 15000
+   voltage_min:
+      default: 12000
+   precharge_current:
+      default: 256
+   start_charging_min_c:
+      default: 0
+   start_charging_max_c:
+      default: 45
+   charging_min_c:
+      default: 0
+   charging_max_c:
+      default: 50
+   discharging_min_c:
+      default: -20
+   discharging_max_c:
+      default: 70
diff --git a/zephyr/dts/bindings/battery/battery-fuel-gauge.yaml b/zephyr/dts/bindings/battery/battery-fuel-gauge.yaml
index 2572090024..d2fed4bfa6 100644
--- a/zephyr/dts/bindings/battery/battery-fuel-gauge.yaml
+++ b/zephyr/dts/bindings/battery/battery-fuel-gauge.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -9,10 +9,16 @@ compatible: "battery-fuel-gauge"
 
 properties:
    manuf_name:
-      description: Manufacturer name
+      description: |
+        String returned by the smart battery attribute
+        ManufacturerName (0x20), which is used to help
+        uniquely identify the type of battery.
       type: string
    device_name:
-      description: Model/Device name
+      description: |
+        String returned by the smart battery attribute
+        DeviceName (0x21), which is used to help
+        uniquely identify the type of battery.
       type: string
    ship_mode_wb_support:
       description: |
diff --git a/zephyr/dts/bindings/battery/battery-info.yaml b/zephyr/dts/bindings/battery/battery-info.yaml
index 3a4cb875e7..54e81cedeb 100644
--- a/zephyr/dts/bindings/battery/battery-info.yaml
+++ b/zephyr/dts/bindings/battery/battery-info.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/battery/battery-smart.yaml b/zephyr/dts/bindings/battery/battery-smart.yaml
index c2c6d28175..81c96f0115 100644
--- a/zephyr/dts/bindings/battery/battery-smart.yaml
+++ b/zephyr/dts/bindings/battery/battery-smart.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -12,7 +12,19 @@ properties:
       type: string
       enum:
          - "aec,5477109"
-         - "as3gwrc3ka,c235-41"
+         - "atl,cfd72"
+         - "byd,l22b3pg0"
+         - "byd,wv3k8"
+         - "celxpert,c235-41"
+         - "celxpert,l22c3pg0"
+         - "cosmx,ap20cbl"
+         - "cosmx,ap20cbl-2"
+         - "cosmx,gh02047xl"
+         - "cosmx,l22x3pg0"
+         - "cosmx,mvk11"
+         - "dynapack,atl_gh02047xl"
+         - "dynapack,cosmx_gh02047xl"
+         - "dynapack,c140254"
          - "ganfeng,7c01"
          - "getac,bq40z50-R3-S3"
          - "getac,bq40z50-R3-S2"
@@ -20,12 +32,27 @@ properties:
          - "lgc,ap16l8j"
          - "lgc,ap18c8k"
          - "lgc,ap19a8k"
+         - "lgc,ap19b8m"
          - "lgc,l20l3pg2"
+         - "lgc,xphx8"
          - "murata,ap18c4k"
          - "panasonic,ap16l5j"
          - "panasonic,ap16l5j-009"
          - "panasonic,ap19a5k"
          - "powertech,batgqa05l22"
+         - "smp,atlxdy9k"
+         - "smp,c31n1915"
+         - "smp,c31n2005"
          - "smp,l20m3pg0"
          - "smp,l20m3pg1"
          - "smp,l20m3pg2"
+         - "smp,l22m3pg0"
+         - "smp,l22m3pg1"
+         - "smp,pc-vp-bp153"
+         - "smp,coslight_gh02047xl"
+         - "smp,cosxdy9k"
+         - "smp,highpower_gh02047xl"
+         - "sunwoda,atl3rr09"
+         - "sunwoda,cos3rr09"
+         - "sunwoda,l22d3pg0"
+         - "sunwoda,l22d3pg1"
diff --git a/zephyr/dts/bindings/battery/byd,l22b3pg0.yaml b/zephyr/dts/bindings/battery/byd,l22b3pg0.yaml
new file mode 100644
index 0000000000..dbe82d5aaa
--- /dev/null
+++ b/zephyr/dts/bindings/battery/byd,l22b3pg0.yaml
@@ -0,0 +1,54 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "BYD L22B3PG0"
+compatible: "byd,l22b3pg0"
+
+include: battery-smart.yaml
+
+properties:
+   enum-name:
+      type: string
+      default: "byd,l22b3pg0"
+
+   # Fuel gauge
+   manuf_name:
+      default: "BYD"
+   device_name:
+      default: "L22B3PG0"
+   ship_mode_reg_addr:
+      default: 0x34
+   ship_mode_reg_data:
+      default: [ 0x0000, 0x1000 ]
+   fet_mfgacc_support:
+      default: 0
+   fet_reg_addr:
+      default: 0x34
+   fet_reg_mask:
+      default: 0x0100
+   fet_disconnect_val:
+      default: 0x0100
+
+   # Battery info
+   voltage_max:
+      default: 13200
+   voltage_normal:
+      default: 11310
+   voltage_min:
+      default: 9000
+   precharge_current:
+      default: 416
+   start_charging_min_c:
+      default: 0
+   start_charging_max_c:
+      default: 50
+   charging_min_c:
+      default: 0
+   charging_max_c:
+      default: 60
+   discharging_min_c:
+      default: -20
+   discharging_max_c:
+      default: 70
+
diff --git a/zephyr/dts/bindings/battery/byd,wv3k8.yaml b/zephyr/dts/bindings/battery/byd,wv3k8.yaml
new file mode 100644
index 0000000000..98c3313632
--- /dev/null
+++ b/zephyr/dts/bindings/battery/byd,wv3k8.yaml
@@ -0,0 +1,54 @@
+description: "BYD DELL WV3K8"
+compatible: "byd,wv3k8"
+
+include: battery-smart.yaml
+
+properties:
+   enum-name:
+      type: string
+      default: "byd,wv3k8"
+
+   # Fuel gauge
+   manuf_name:
+      default: "BYD"
+   device_name:
+      default: "DELL WV3K8"
+   ship_mode_reg_addr:
+      default: 0x00
+   ship_mode_reg_data:
+      default: [ 0x0010, 0x0010 ]
+   fet_mfgacc_support:
+      default: 0
+   fet_reg_addr:
+      default: 0x54
+   fet_reg_mask:
+      default: 0x0002
+   fet_disconnect_val:
+      default: 0x0000
+   fet_cfet_mask:
+      default: 0x0004
+   fet_cfet_off_val:
+      default: 0x0000
+
+   # Battery info
+   voltage_max:
+      default: 17400
+   voltage_normal:
+      default: 15000
+   voltage_min:
+      default: 12000
+   precharge_current:
+      default: 256
+   start_charging_min_c:
+      default: -3
+   start_charging_max_c:
+      default: 45
+   charging_min_c:
+      default: -3
+   charging_max_c:
+      default: 50
+   discharging_min_c:
+      default: -5
+   discharging_max_c:
+      default: 70
+
diff --git a/zephyr/dts/bindings/battery/as3gwrc3ka,c235-41.yaml b/zephyr/dts/bindings/battery/celxpert,c235-41.yaml
index c4359b29d2..cffe1c2f0d 100644
--- a/zephyr/dts/bindings/battery/as3gwrc3ka,c235-41.yaml
+++ b/zephyr/dts/bindings/battery/celxpert,c235-41.yaml
@@ -1,12 +1,12 @@
-description: "AS3GWRc3KA C235-41"
-compatible: "as3gwrc3ka,c235-41"
+description: "Celxpert C235-41"
+compatible: "celxpert,c235-41"
 
 include: battery-smart.yaml
 
 properties:
    enum-name:
       type: string
-      default: "as3gwrc3ka,c235-41"
+      default: "celxpert,c235-41"
 
    # Fuel gauge
    manuf_name:
diff --git a/zephyr/dts/bindings/battery/celxpert,l22c3pg0.yaml b/zephyr/dts/bindings/battery/celxpert,l22c3pg0.yaml
new file mode 100644
index 0000000000..2e99336c06
--- /dev/null
+++ b/zephyr/dts/bindings/battery/celxpert,l22c3pg0.yaml
@@ -0,0 +1,54 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "CELXPERT L22C3PG0"
+compatible: "celxpert,l22c3pg0"
+
+include: battery-smart.yaml
+
+properties:
+   enum-name:
+      type: string
+      default: "celxpert,l22c3pg0"
+
+   # Fuel gauge
+   manuf_name:
+      default: "Celxpert"
+   device_name:
+      default: "L22C3PG0"
+   ship_mode_reg_addr:
+      default: 0x34
+   ship_mode_reg_data:
+      default: [ 0x0000, 0x1000 ]
+   fet_mfgacc_support:
+      default: 0
+   fet_reg_addr:
+      default: 0x00
+   fet_reg_mask:
+      default: 0x0018
+   fet_disconnect_val:
+      default: 0x0000
+
+   # Battery info
+   voltage_max:
+      default: 13200
+   voltage_normal:
+      default: 11310
+   voltage_min:
+      default: 9000
+   precharge_current:
+      default: 416
+   start_charging_min_c:
+      default: 0
+   start_charging_max_c:
+      default: 50
+   charging_min_c:
+      default: 0
+   charging_max_c:
+      default: 60
+   discharging_min_c:
+      default: -20
+   discharging_max_c:
+      default: 60
+
diff --git a/zephyr/dts/bindings/battery/cosmx,ap20cbl-2.yaml b/zephyr/dts/bindings/battery/cosmx,ap20cbl-2.yaml
new file mode 100644
index 0000000000..5e64834f15
--- /dev/null
+++ b/zephyr/dts/bindings/battery/cosmx,ap20cbl-2.yaml
@@ -0,0 +1,57 @@
+description: "COSMX AP20CBL-2"
+compatible: "cosmx,ap20cbl-2"
+
+include: battery-smart.yaml
+
+properties:
+   enum-name:
+      type: string
+      default: "cosmx,ap20cbl-2"
+
+   # Fuel gauge
+   manuf_name:
+      default: "COSMX KT0030B004"
+   device_name:
+      default: "AP20CBL"
+   ship_mode_reg_addr:
+      default: 0x3A
+   ship_mode_reg_data:
+      default: [ 0xC574, 0xC574 ]
+   # Documentation: b/243772306
+   # Manufacturer Access 0x00
+   # b14: C-FET Status (0: Off, 1: On)
+   # b15: D-FET Status (0: Off, 1: On)
+   fet_mfgacc_support:
+      default: 1
+   fet_reg_addr:
+      default: 0x0
+   fet_reg_mask:
+      default: 0x8000
+   fet_disconnect_val:
+      default: 0x0000
+   fet_cfet_mask:
+      default: 0x4000
+   fet_cfet_off_val:
+      default: 0x0000
+
+   # Battery info
+   voltage_max:
+      default: 13200
+   voltage_normal:
+      default: 11550
+   voltage_min:
+      default: 9000
+   precharge_current:
+      default: 256
+   start_charging_min_c:
+      default: 0
+   start_charging_max_c:
+      default: 50
+   charging_min_c:
+      default: 0
+   charging_max_c:
+      default: 60
+   discharging_min_c:
+      default: -20
+   discharging_max_c:
+      default: 75
diff --git a/zephyr/dts/bindings/battery/cosmx,ap20cbl.yaml b/zephyr/dts/bindings/battery/cosmx,ap20cbl.yaml
new file mode 100644
index 0000000000..193ef649f1
--- /dev/null
+++ b/zephyr/dts/bindings/battery/cosmx,ap20cbl.yaml
@@ -0,0 +1,57 @@
+description: "COSMX AP20CBL"
+compatible: "cosmx,ap20cbl"
+
+include: battery-smart.yaml
+
+properties:
+   enum-name:
+      type: string
+      default: "cosmx,ap20cbl"
+
+   # Fuel gauge
+   manuf_name:
+      default: "COSMX KT0030B002"
+   device_name:
+      default: "AP20CBL"
+   ship_mode_reg_addr:
+      default: 0x3A
+   ship_mode_reg_data:
+      default: [ 0xC574, 0xC574 ]
+   # Documentation: b/230427330
+   # Manufacturer Access 0x00
+   # b14: Charging Disabled (0: Off, 1: On)
+   # b13: Discharging Disabled (0: Off, 1: On)
+   fet_mfgacc_support:
+      default: 1
+   fet_reg_addr:
+      default: 0x0
+   fet_reg_mask:
+      default: 0x2000
+   fet_disconnect_val:
+      default: 0x2000
+   fet_cfet_mask:
+      default: 0x4000
+   fet_cfet_off_val:
+      default: 0x4000
+
+   # Battery info
+   voltage_max:
+      default: 13200
+   voltage_normal:
+      default: 11550
+   voltage_min:
+      default: 9000
+   precharge_current:
+      default: 256
+   start_charging_min_c:
+      default: 0
+   start_charging_max_c:
+      default: 50
+   charging_min_c:
+      default: 0
+   charging_max_c:
+      default: 60
+   discharging_min_c:
+      default: -20
+   discharging_max_c:
+      default: 75
diff --git a/zephyr/dts/bindings/battery/cosmx,gh02047xl.yaml b/zephyr/dts/bindings/battery/cosmx,gh02047xl.yaml
new file mode 100644
index 0000000000..aa44980621
--- /dev/null
+++ b/zephyr/dts/bindings/battery/cosmx,gh02047xl.yaml
@@ -0,0 +1,54 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "COSMX GH02047XL"
+compatible: "cosmx,gh02047xl"
+
+include: battery-smart.yaml
+
+properties:
+   enum-name:
+      type: string
+      default: "cosmx,gh02047xl"
+
+   # Fuel gauge
+   manuf_name:
+      default: "333-AC-DA-A"
+   device_name:
+      default: "GH02047XL"
+   ship_mode_reg_addr:
+      default: 0x00
+   ship_mode_reg_data:
+      default: [ 0x0010, 0x0010 ]
+   fet_mfgacc_support:
+      default: 1
+   fet_reg_addr:
+      default: 0x0
+   fet_reg_mask:
+      default: 0x0006
+   fet_disconnect_val:
+      default: 0x0
+
+   # Battery info
+   voltage_max:
+      default: 8800
+   voltage_normal:
+      default: 7700
+   voltage_min:
+      default: 6000
+   precharge_current:
+      default: 256
+   start_charging_min_c:
+      default: 0
+   start_charging_max_c:
+      default: 45
+   charging_min_c:
+      default: 0
+   charging_max_c:
+      default: 45
+   discharging_min_c:
+      default: -10
+   discharging_max_c:
+      default: 60
+
diff --git a/zephyr/dts/bindings/battery/cosmx,l22x3pg0.yaml b/zephyr/dts/bindings/battery/cosmx,l22x3pg0.yaml
new file mode 100644
index 0000000000..b8e199d6cb
--- /dev/null
+++ b/zephyr/dts/bindings/battery/cosmx,l22x3pg0.yaml
@@ -0,0 +1,54 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "COSMX L22X3PG0"
+compatible: "cosmx,l22x3pg0"
+
+include: battery-smart.yaml
+
+properties:
+   enum-name:
+      type: string
+      default: "cosmx,l22x3pg0"
+
+   # Fuel gauge
+   manuf_name:
+      default: "COSMX"
+   device_name:
+      default: "L22X3PG0"
+   ship_mode_reg_addr:
+      default: 0x34
+   ship_mode_reg_data:
+      default: [ 0x0000, 0x1000 ]
+   fet_mfgacc_support:
+      default: 0
+   fet_reg_addr:
+      default: 0x34
+   fet_reg_mask:
+      default: 0x0100
+   fet_disconnect_val:
+      default: 0x0100
+
+   # Battery info
+   voltage_max:
+      default: 13200
+   voltage_normal:
+      default: 11310
+   voltage_min:
+      default: 9000
+   precharge_current:
+      default: 207
+   start_charging_min_c:
+      default: 0
+   start_charging_max_c:
+      default: 50
+   charging_min_c:
+      default: 0
+   charging_max_c:
+      default: 60
+   discharging_min_c:
+      default: -20
+   discharging_max_c:
+      default: 70
+
diff --git a/zephyr/dts/bindings/battery/cosmx,mvk11.yaml b/zephyr/dts/bindings/battery/cosmx,mvk11.yaml
new file mode 100644
index 0000000000..c493d27cef
--- /dev/null
+++ b/zephyr/dts/bindings/battery/cosmx,mvk11.yaml
@@ -0,0 +1,53 @@
+description: "COSMX COM DELL MVK11"
+compatible: "cosmx,mvk11"
+
+include: battery-smart.yaml
+
+properties:
+   enum-name:
+      type: string
+      default: "cosmx,mvk11"
+
+   # Fuel Gauge
+   manuf_name:
+      default: "COM"
+   device_name:
+      default: "DELL MVK11"
+   ship_mode_reg_addr:
+      default: 0x00
+   ship_mode_reg_data:
+      default: [ 0x0010, 0x0010 ]
+   fet_mfgacc_support:
+      default: 0
+   fet_reg_addr:
+      default: 0x54
+   fet_reg_mask:
+      default: 0x0002
+   fet_disconnect_val:
+      default: 0x0000
+   fet_cfet_mask:
+      default: 0x0004
+   fet_cfet_off_val:
+      default: 0x0000
+
+   # Battery info
+   voltage_max:
+      default: 17600
+   voltage_normal:
+      default: 15000
+   voltage_min:
+      default: 12000
+   precharge_current:
+      default: 256
+   start_charging_min_c:
+      default: 0
+   start_charging_max_c:
+      default: 50
+   charging_min_c:
+      default: 0
+   charging_max_c:
+      default: 60
+   discharging_min_c:
+      default: -20
+   discharging_max_c:
+      default: 70
diff --git a/zephyr/dts/bindings/battery/dynapack,atl_gh02047xl.yaml b/zephyr/dts/bindings/battery/dynapack,atl_gh02047xl.yaml
new file mode 100644
index 0000000000..3bc3eccb4c
--- /dev/null
+++ b/zephyr/dts/bindings/battery/dynapack,atl_gh02047xl.yaml
@@ -0,0 +1,54 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "DYNAPACK ATL_GH02047XL"
+compatible: "dynapack,atl_gh02047xl"
+
+include: battery-smart.yaml
+
+properties:
+   enum-name:
+      type: string
+      default: "dynapack,atl_gh02047xl"
+
+   # Fuel gauge
+   manuf_name:
+      default: "333-27-DA-A"
+   device_name:
+      default: "GH02047XL"
+   ship_mode_reg_addr:
+      default: 0x00
+   ship_mode_reg_data:
+      default: [ 0x0010, 0x0010 ]
+   fet_mfgacc_support:
+      default: 1
+   fet_reg_addr:
+      default: 0x0
+   fet_reg_mask:
+      default: 0x0006
+   fet_disconnect_val:
+      default: 0x0
+
+   # Battery info
+   voltage_max:
+      default: 8800
+   voltage_normal:
+      default: 7700
+   voltage_min:
+      default: 6000
+   precharge_current:
+      default: 256
+   start_charging_min_c:
+      default: 0
+   start_charging_max_c:
+      default: 45
+   charging_min_c:
+      default: 0
+   charging_max_c:
+      default: 45
+   discharging_min_c:
+      default: -10
+   discharging_max_c:
+      default: 60
+
diff --git a/zephyr/dts/bindings/battery/dynapack,c140254.yaml b/zephyr/dts/bindings/battery/dynapack,c140254.yaml
new file mode 100644
index 0000000000..1c9f4c59de
--- /dev/null
+++ b/zephyr/dts/bindings/battery/dynapack,c140254.yaml
@@ -0,0 +1,56 @@
+description: "DYNAPACK AS3GXXE3KA C140254"
+compatible: "dynapack,c140254"
+
+include: battery-smart.yaml
+
+properties:
+   enum-name:
+      type: string
+      default: "dynapack,c140254"
+
+   # Fuel gauge
+   manuf_name:
+      default: "AS3GXXE3KA"
+   device_name:
+      default: "C140254"
+   ship_mode_reg_addr:
+      default: 0x00
+   ship_mode_reg_data:
+      default: [ 0x0010, 0x0010 ]
+   # Documentation: b/150833879
+   # Charging/Discharging FETs Status
+   # Register SBS_PackStatus_ACCESS (0x99)
+   # Bit-3: XDSG
+   # Bit-2: XCHG
+   fet_reg_addr:
+      default: 0x99
+   fet_reg_mask:
+      default: 0x0C
+   fet_disconnect_val:
+      default: 0x0C
+   fet_cfet_mask:
+      default: 0x04
+   fet_cfet_off_val:
+      default: 0x04
+
+   # Battery info
+   voltage_max:
+      default: 8900
+   voltage_normal:
+      default: 7970
+   voltage_min:
+      default: 6000
+   precharge_current:
+      default: 256
+   start_charging_min_c:
+      default: 0
+   start_charging_max_c:
+      default: 45
+   charging_min_c:
+      default: 0
+   charging_max_c:
+      default: 60
+   discharging_min_c:
+      default: -20
+   discharging_max_c:
+      default: 60
\ No newline at end of file
diff --git a/zephyr/dts/bindings/battery/dynapack,cosmx_gh02047xl.yaml b/zephyr/dts/bindings/battery/dynapack,cosmx_gh02047xl.yaml
new file mode 100644
index 0000000000..8fb6315914
--- /dev/null
+++ b/zephyr/dts/bindings/battery/dynapack,cosmx_gh02047xl.yaml
@@ -0,0 +1,54 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "DYNAPACK COSMX_GH02047XL"
+compatible: "dynapack,cosmx_gh02047xl"
+
+include: battery-smart.yaml
+
+properties:
+   enum-name:
+      type: string
+      default: "dynapack,cosmx_gh02047xl"
+
+   # Fuel gauge
+   manuf_name:
+      default: "333-2C-DA-A"
+   device_name:
+      default: "GH02047XL"
+   ship_mode_reg_addr:
+      default: 0x00
+   ship_mode_reg_data:
+      default: [ 0x0010, 0x0010 ]
+   fet_mfgacc_support:
+      default: 1
+   fet_reg_addr:
+      default: 0x0
+   fet_reg_mask:
+      default: 0x0006
+   fet_disconnect_val:
+      default: 0x0
+
+   # Battery info
+   voltage_max:
+      default: 8800
+   voltage_normal:
+      default: 7700
+   voltage_min:
+      default: 6000
+   precharge_current:
+      default: 256
+   start_charging_min_c:
+      default: 0
+   start_charging_max_c:
+      default: 45
+   charging_min_c:
+      default: 0
+   charging_max_c:
+      default: 45
+   discharging_min_c:
+      default: -10
+   discharging_max_c:
+      default: 60
+
diff --git a/zephyr/dts/bindings/battery/getac,bq40z50-R3-S2.yaml b/zephyr/dts/bindings/battery/getac,bq40z50-R3-S2.yaml
index b144c30be3..e59f6c1e37 100644
--- a/zephyr/dts/bindings/battery/getac,bq40z50-R3-S2.yaml
+++ b/zephyr/dts/bindings/battery/getac,bq40z50-R3-S2.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/battery/getac,bq40z50-R3-S3.yaml b/zephyr/dts/bindings/battery/getac,bq40z50-R3-S3.yaml
index 57d220abbb..aed466ad11 100644
--- a/zephyr/dts/bindings/battery/getac,bq40z50-R3-S3.yaml
+++ b/zephyr/dts/bindings/battery/getac,bq40z50-R3-S3.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/battery/lgc,ac17a8m.yaml b/zephyr/dts/bindings/battery/lgc,ac17a8m.yaml
index 53eeedc8a4..939713bbe5 100644
--- a/zephyr/dts/bindings/battery/lgc,ac17a8m.yaml
+++ b/zephyr/dts/bindings/battery/lgc,ac17a8m.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/battery/lgc,ap19b8m.yaml b/zephyr/dts/bindings/battery/lgc,ap19b8m.yaml
new file mode 100644
index 0000000000..8a3beb49fe
--- /dev/null
+++ b/zephyr/dts/bindings/battery/lgc,ap19b8m.yaml
@@ -0,0 +1,54 @@
+description: "LGC KT0030G024 AP19B8M"
+compatible: "lgc,ap19b8m"
+
+include: battery-smart.yaml
+
+properties:
+   enum-name:
+      type: string
+      default: "lgc,ap19b8m"
+
+   # Fuel gauge
+   manuf_name:
+      default: "LGC KT0030G024"
+   device_name:
+      default: "AP19B8M"
+   ship_mode_reg_addr:
+      default: 0x3A
+   ship_mode_reg_data:
+      default: [ 0xC574, 0xC574 ]
+   # Documentation: b/135496272
+   fet_mfgacc_support:
+      default: 0
+   fet_reg_addr:
+      default: 0x43
+   fet_reg_mask:
+      default: 0x0001
+   fet_disconnect_val:
+      default: 0x0000
+   fet_cfet_mask:
+      default: 0x0002
+   fet_cfet_off_val:
+      default: 0x0000
+
+   # Battery info
+   voltage_max:
+      default: 13350
+   voltage_normal:
+      default: 11610
+   voltage_min:
+      default: 9000
+   precharge_current:
+      default: 256
+   start_charging_min_c:
+      default: 0
+   start_charging_max_c:
+      default: 50
+   charging_min_c:
+      default: 0
+   charging_max_c:
+      default: 60
+   discharging_min_c:
+      default: -20
+   discharging_max_c:
+      default: 75
diff --git a/zephyr/dts/bindings/battery/lgc,l20l3pg2.yaml b/zephyr/dts/bindings/battery/lgc,l20l3pg2.yaml
index bf2b62bc44..73d2ca5ec6 100644
--- a/zephyr/dts/bindings/battery/lgc,l20l3pg2.yaml
+++ b/zephyr/dts/bindings/battery/lgc,l20l3pg2.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/battery/lgc,xphx8.yaml b/zephyr/dts/bindings/battery/lgc,xphx8.yaml
new file mode 100644
index 0000000000..98b27fbe5b
--- /dev/null
+++ b/zephyr/dts/bindings/battery/lgc,xphx8.yaml
@@ -0,0 +1,57 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "LGC-LGC3.600 DELL_XPHX8"
+compatible: "lgc,xphx8"
+
+include: battery-smart.yaml
+
+properties:
+   enum-name:
+      type: string
+      default: "lgc,xphx8"
+
+   # Fuel Gauge
+   manuf_name:
+      default: "LGC-LGC3.600"
+   device_name:
+      default: "DELL XPHX8"
+   ship_mode_reg_addr:
+      default: 0x00
+   ship_mode_reg_data:
+      default: [ 0x0010, 0x0010 ]
+   fet_mfgacc_support:
+      default: 0
+   fet_reg_addr:
+      default: 0x43
+   fet_reg_mask:
+      default: 0x0001
+   fet_disconnect_val:
+      default: 0x0000
+   fet_cfet_mask:
+      default: 0x0002
+   fet_cfet_off_val:
+      default: 0x0000
+
+   # Battery info
+   voltage_max:
+      default: 17600
+   voltage_normal:
+      default: 15000
+   voltage_min:
+      default: 12000
+   precharge_current:
+      default: 256
+   start_charging_min_c:
+      default: -3
+   start_charging_max_c:
+      default: 45
+   charging_min_c:
+      default: -3
+   charging_max_c:
+      default: 50
+   discharging_min_c:
+      default: -20
+   discharging_max_c:
+      default: 70
diff --git a/zephyr/dts/bindings/battery/powertech,batgqa05l22.yaml b/zephyr/dts/bindings/battery/powertech,batgqa05l22.yaml
index a12ef741e6..45b067ee4d 100644
--- a/zephyr/dts/bindings/battery/powertech,batgqa05l22.yaml
+++ b/zephyr/dts/bindings/battery/powertech,batgqa05l22.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/battery/smp,atlxdy9k.yaml b/zephyr/dts/bindings/battery/smp,atlxdy9k.yaml
new file mode 100644
index 0000000000..dd437f705a
--- /dev/null
+++ b/zephyr/dts/bindings/battery/smp,atlxdy9k.yaml
@@ -0,0 +1,53 @@
+description: "SMP-ATL SMP-ATL3.66 "
+compatible: "smp,atlxdy9k"
+
+include: battery-smart.yaml
+
+properties:
+   enum-name:
+      type: string
+      default: "smp,atlxdy9k"
+
+   # Fuel gauge
+   manuf_name:
+      default: "SMP-ATL3.66"
+   device_name:
+      default: "DELL XDY9K"
+   ship_mode_reg_addr:
+      default: 0x00
+   ship_mode_reg_data:
+      default: [ 0x0010, 0x0010 ]
+   fet_mfgacc_support:
+      default: 0
+   fet_reg_addr:
+      default: 0x43
+   fet_reg_mask:
+      default: 0x0001
+   fet_disconnect_val:
+      default: 0x0000
+   fet_cfet_mask:
+      default: 0x0002
+   fet_cfet_off_val:
+      default: 0x0000
+
+   # Battery info
+   voltage_max:
+      default: 17600
+   voltage_normal:
+      default: 15000
+   voltage_min:
+      default: 12000
+   precharge_current:
+      default: 256
+   start_charging_min_c:
+      default: -3
+   start_charging_max_c:
+      default: 45
+   charging_min_c:
+      default: -3
+   charging_max_c:
+      default: 50
+   discharging_min_c:
+      default: -17
+   discharging_max_c:
+      default: 70
diff --git a/zephyr/dts/bindings/battery/smp,c31n1915.yaml b/zephyr/dts/bindings/battery/smp,c31n1915.yaml
new file mode 100644
index 0000000000..03dd7d3915
--- /dev/null
+++ b/zephyr/dts/bindings/battery/smp,c31n1915.yaml
@@ -0,0 +1,47 @@
+description: "SMP Rechargeable Li-Polymer Battery Pack 3640mAh"
+compatible: "smp,c31n1915"
+
+include: battery-smart.yaml
+
+properties:
+   enum-name:
+      type: string
+      default: "smp,c31n1915"
+
+   # Fuel gauge
+   manuf_name:
+      default: "AS3GWND3jB"
+   device_name:
+      default: "B340035"
+   ship_mode_reg_addr:
+      default: 0x00
+   ship_mode_reg_data:
+      default: [ 0x0010, 0x0010 ]
+   fet_reg_addr:
+      default: 0x99
+   fet_reg_mask:
+      default: 0x000c
+   fet_disconnect_val:
+      default: 0x000c
+
+   # Battery info
+   voltage_max:
+      default: 13200
+   voltage_normal:
+      default: 11850
+   voltage_min:
+      default: 9000
+   precharge_current:
+      default: 256
+   start_charging_min_c:
+      default: 0
+   start_charging_max_c:
+      default: 45
+   charging_min_c:
+      default: 0
+   charging_max_c:
+      default: 60
+   discharging_min_c:
+      default: -20
+   discharging_max_c:
+      default: 60
diff --git a/zephyr/dts/bindings/battery/smp,c31n2005.yaml b/zephyr/dts/bindings/battery/smp,c31n2005.yaml
new file mode 100644
index 0000000000..07b7e9f0b6
--- /dev/null
+++ b/zephyr/dts/bindings/battery/smp,c31n2005.yaml
@@ -0,0 +1,48 @@
+# SMP Li-Po 4335mAh
+description: "SMP LiPo 4335mAh AS3GWQd3jB C490-42"
+compatible: "smp,c31n2005"
+
+include: battery-smart.yaml
+
+properties:
+   enum-name:
+      type: string
+      default: "smp,c31n2005"
+
+   # Fuel gauge
+   manuf_name:
+      default: "AS3GWQd3jB"
+   device_name:
+      default: "C490-42"
+   ship_mode_reg_addr:
+      default: 0x00
+   ship_mode_reg_data:
+      default: [ 0x0010, 0x0010 ]
+   fet_reg_addr:
+      default: 0x99
+   fet_reg_mask:
+      default: 0x000c
+   fet_disconnect_val:
+      default: 0x000c
+
+   # Battery info
+   voltage_max:
+      default: 13200
+   voltage_normal:
+      default: 11880
+   voltage_min:
+      default: 9000
+   precharge_current:
+      default: 256
+   start_charging_min_c:
+      default: 0
+   start_charging_max_c:
+      default: 45
+   charging_min_c:
+      default: 0
+   charging_max_c:
+      default: 60
+   discharging_min_c:
+      default: -20
+   discharging_max_c:
+      default: 60
diff --git a/zephyr/dts/bindings/battery/smp,coslight_gh02047xl.yaml b/zephyr/dts/bindings/battery/smp,coslight_gh02047xl.yaml
new file mode 100644
index 0000000000..19f8751998
--- /dev/null
+++ b/zephyr/dts/bindings/battery/smp,coslight_gh02047xl.yaml
@@ -0,0 +1,54 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "SMP COSLIGHT_GH02047XL"
+compatible: "smp,coslight_gh02047xl"
+
+include: battery-smart.yaml
+
+properties:
+   enum-name:
+      type: string
+      default: "smp,coslight_gh02047xl"
+
+   # Fuel gauge
+   manuf_name:
+      default: "333-1C-DA-A"
+   device_name:
+      default: "GH02047XL"
+   ship_mode_reg_addr:
+      default: 0x00
+   ship_mode_reg_data:
+      default: [ 0x0010, 0x0010 ]
+   fet_mfgacc_support:
+      default: 1
+   fet_reg_addr:
+      default: 0x0
+   fet_reg_mask:
+      default: 0x0006
+   fet_disconnect_val:
+      default: 0x0
+
+   # Battery info
+   voltage_max:
+      default: 8800
+   voltage_normal:
+      default: 7700
+   voltage_min:
+      default: 6000
+   precharge_current:
+      default: 256
+   start_charging_min_c:
+      default: 0
+   start_charging_max_c:
+      default: 45
+   charging_min_c:
+      default: 0
+   charging_max_c:
+      default: 45
+   discharging_min_c:
+      default: -10
+   discharging_max_c:
+      default: 60
+
diff --git a/zephyr/dts/bindings/battery/smp,cosxdy9k.yaml b/zephyr/dts/bindings/battery/smp,cosxdy9k.yaml
new file mode 100644
index 0000000000..29baf7b807
--- /dev/null
+++ b/zephyr/dts/bindings/battery/smp,cosxdy9k.yaml
@@ -0,0 +1,51 @@
+description: "SMP-ATL SMP-COS3.66 "
+compatible: "smp,cosxdy9k"
+
+include: battery-smart.yaml
+
+properties:
+   enum-name:
+      type: string
+      default: "smp,cosxdy9k"
+
+   # Fuel gauge
+   manuf_name:
+      default: "SMP-COS3.66"
+   device_name:
+      default: "DELL XDY9K"
+   ship_mode_reg_addr:
+      default: 0x00
+   ship_mode_reg_data:
+      default: [ 0x0010, 0x0010 ]
+   fet_reg_addr:
+      default: 0x43
+   fet_reg_mask:
+      default: 0x0001
+   fet_disconnect_val:
+      default: 0x0000
+   fet_cfet_mask:
+      default: 0x0002
+   fet_cfet_off_val:
+      default: 0x0000
+
+   # Battery info
+   voltage_max:
+      default: 17600
+   voltage_normal:
+      default: 15000
+   voltage_min:
+      default: 12000
+   precharge_current:
+      default: 256
+   start_charging_min_c:
+      default: -3
+   start_charging_max_c:
+      default: 45
+   charging_min_c:
+      default: -3
+   charging_max_c:
+      default: 50
+   discharging_min_c:
+      default: -17
+   discharging_max_c:
+      default: 70
diff --git a/zephyr/dts/bindings/battery/smp,highpower_gh02047xl.yaml b/zephyr/dts/bindings/battery/smp,highpower_gh02047xl.yaml
new file mode 100644
index 0000000000..f3d039dfdf
--- /dev/null
+++ b/zephyr/dts/bindings/battery/smp,highpower_gh02047xl.yaml
@@ -0,0 +1,54 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "SMP HIGHPOWER_GH02047XL"
+compatible: "smp,highpower_gh02047xl"
+
+include: battery-smart.yaml
+
+properties:
+   enum-name:
+      type: string
+      default: "smp,highpower_gh02047xl"
+
+   # Fuel gauge
+   manuf_name:
+      default: "333-1D-DA-A"
+   device_name:
+      default: "GH02047XL"
+   ship_mode_reg_addr:
+      default: 0x00
+   ship_mode_reg_data:
+      default: [ 0x0010, 0x0010 ]
+   fet_mfgacc_support:
+      default: 1
+   fet_reg_addr:
+      default: 0x0
+   fet_reg_mask:
+      default: 0x0006
+   fet_disconnect_val:
+      default: 0x0
+
+   # Battery info
+   voltage_max:
+      default: 8800
+   voltage_normal:
+      default: 7700
+   voltage_min:
+      default: 6000
+   precharge_current:
+      default: 256
+   start_charging_min_c:
+      default: 0
+   start_charging_max_c:
+      default: 45
+   charging_min_c:
+      default: 0
+   charging_max_c:
+      default: 45
+   discharging_min_c:
+      default: -10
+   discharging_max_c:
+      default: 60
+
diff --git a/zephyr/dts/bindings/battery/smp,l20m3pg0.yaml b/zephyr/dts/bindings/battery/smp,l20m3pg0.yaml
index ecb0678dc7..437a3ca140 100644
--- a/zephyr/dts/bindings/battery/smp,l20m3pg0.yaml
+++ b/zephyr/dts/bindings/battery/smp,l20m3pg0.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/battery/smp,l20m3pg1.yaml b/zephyr/dts/bindings/battery/smp,l20m3pg1.yaml
index f462f8b388..00a6b99a84 100644
--- a/zephyr/dts/bindings/battery/smp,l20m3pg1.yaml
+++ b/zephyr/dts/bindings/battery/smp,l20m3pg1.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/battery/smp,l20m3pg2.yaml b/zephyr/dts/bindings/battery/smp,l20m3pg2.yaml
index 874e1f8d0c..37a5cb2052 100644
--- a/zephyr/dts/bindings/battery/smp,l20m3pg2.yaml
+++ b/zephyr/dts/bindings/battery/smp,l20m3pg2.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/battery/smp,l22m3pg0.yaml b/zephyr/dts/bindings/battery/smp,l22m3pg0.yaml
new file mode 100644
index 0000000000..991734c9bc
--- /dev/null
+++ b/zephyr/dts/bindings/battery/smp,l22m3pg0.yaml
@@ -0,0 +1,54 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "SMP L22M3PG0"
+compatible: "smp,l22m3pg0"
+
+include: battery-smart.yaml
+
+properties:
+   enum-name:
+      type: string
+      default: "smp,l22m3pg0"
+
+   # Fuel gauge
+   manuf_name:
+      default: "SMP"
+   device_name:
+      default: "L22M3PG0"
+   ship_mode_reg_addr:
+      default: 0x34
+   ship_mode_reg_data:
+      default: [ 0x0000, 0x1000 ]
+   fet_mfgacc_support:
+      default: 0
+   fet_reg_addr:
+      default: 0x00
+   fet_reg_mask:
+      default: 0x0018
+   fet_disconnect_val:
+      default: 0x0000
+
+   # Battery info
+   voltage_max:
+      default: 13200
+   voltage_normal:
+      default: 11310
+   voltage_min:
+      default: 9000
+   precharge_current:
+      default: 208
+   start_charging_min_c:
+      default: 0
+   start_charging_max_c:
+      default: 50
+   charging_min_c:
+      default: 0
+   charging_max_c:
+      default: 60
+   discharging_min_c:
+      default: -20
+   discharging_max_c:
+      default: 60
+
diff --git a/zephyr/dts/bindings/battery/smp,l22m3pg1.yaml b/zephyr/dts/bindings/battery/smp,l22m3pg1.yaml
new file mode 100644
index 0000000000..48152e0722
--- /dev/null
+++ b/zephyr/dts/bindings/battery/smp,l22m3pg1.yaml
@@ -0,0 +1,54 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "SMP L22M3PG1"
+compatible: "smp,l22m3pg1"
+
+include: battery-smart.yaml
+
+properties:
+   enum-name:
+      type: string
+      default: "smp,l22m3pg1"
+
+   # Fuel gauge
+   manuf_name:
+      default: "SMP"
+   device_name:
+      default: "L22M3PG1"
+   ship_mode_reg_addr:
+      default: 0x34
+   ship_mode_reg_data:
+      default: [ 0x0000, 0x1000 ]
+   fet_mfgacc_support:
+      default: 0
+   fet_reg_addr:
+      default: 0x00
+   fet_reg_mask:
+      default: 0x0018
+   fet_disconnect_val:
+      default: 0x0000
+
+   # Battery info
+   voltage_max:
+      default: 13200
+   voltage_normal:
+      default: 11520
+   voltage_min:
+      default: 9000
+   precharge_current:
+      default: 248
+   start_charging_min_c:
+      default: 0
+   start_charging_max_c:
+      default: 50
+   charging_min_c:
+      default: 0
+   charging_max_c:
+      default: 60
+   discharging_min_c:
+      default: -20
+   discharging_max_c:
+      default: 60
+
diff --git a/zephyr/dts/bindings/battery/smp,pc-vp-bp153.yaml b/zephyr/dts/bindings/battery/smp,pc-vp-bp153.yaml
new file mode 100644
index 0000000000..3341b40d14
--- /dev/null
+++ b/zephyr/dts/bindings/battery/smp,pc-vp-bp153.yaml
@@ -0,0 +1,54 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "SMP PC-VP-BP153"
+compatible: "smp,pc-vp-bp153"
+
+include: battery-smart.yaml
+
+properties:
+   enum-name:
+      type: string
+      default: "smp,pc-vp-bp153"
+
+   # Fuel gauge
+   manuf_name:
+      default: "SIMPLO"
+   device_name:
+      default: "PC-VP-BP153"
+   ship_mode_reg_addr:
+      default: 0x34
+   ship_mode_reg_data:
+      default: [ 0x0000, 0x1000 ]
+   fet_mfgacc_support:
+      default: 0
+   fet_reg_addr:
+      default: 0x34
+   fet_reg_mask:
+      default: 0x0100
+   fet_disconnect_val:
+      default: 0x0100
+
+   # Battery info
+   voltage_max:
+      default: 8800
+   voltage_normal:
+      default: 7680
+   voltage_min:
+      default: 6000
+   precharge_current:
+      default: 128
+   start_charging_min_c:
+      default: 0
+   start_charging_max_c:
+      default: 50
+   charging_min_c:
+      default: 0
+   charging_max_c:
+      default: 60
+   discharging_min_c:
+      default: -20
+   discharging_max_c:
+      default: 70
+
diff --git a/zephyr/dts/bindings/battery/sunwoda,atl3rr09.yaml b/zephyr/dts/bindings/battery/sunwoda,atl3rr09.yaml
new file mode 100644
index 0000000000..5ca2477f87
--- /dev/null
+++ b/zephyr/dts/bindings/battery/sunwoda,atl3rr09.yaml
@@ -0,0 +1,53 @@
+description: "SUNWODA SWD-ATL4.242"
+compatible: "sunwoda,atl3rr09"
+
+include: battery-smart.yaml
+
+properties:
+   enum-name:
+      type: string
+      default: "sunwoda,atl3rr09"
+
+   # Fuel Gauge
+   manuf_name:
+      default: "SWD-ATL4.242"
+   device_name:
+      default: "DELL 3RR09"
+   ship_mode_reg_addr:
+      default: 0x00
+   ship_mode_reg_data:
+      default: [ 0x0010, 0x0010 ]
+   fet_mfgacc_support:
+      default: 0
+   fet_reg_addr:
+      default: 0x54
+   fet_reg_mask:
+      default: 0x0002
+   fet_disconnect_val:
+      default: 0x0000
+   fet_cfet_mask:
+      default: 0x0004
+   fet_cfet_off_val:
+      default: 0x0000
+
+   # Battery info
+   voltage_max:
+      default: 17800
+   voltage_normal:
+      default: 15200
+   voltage_min:
+      default: 12000
+   precharge_current:
+      default: 256
+   start_charging_min_c:
+      default: 0
+   start_charging_max_c:
+      default: 45
+   charging_min_c:
+      default: -3
+   charging_max_c:
+      default: 50
+   discharging_min_c:
+      default: -5
+   discharging_max_c:
+      default: 70
diff --git a/zephyr/dts/bindings/battery/sunwoda,cos3rr09.yaml b/zephyr/dts/bindings/battery/sunwoda,cos3rr09.yaml
new file mode 100644
index 0000000000..58d6b7d635
--- /dev/null
+++ b/zephyr/dts/bindings/battery/sunwoda,cos3rr09.yaml
@@ -0,0 +1,53 @@
+description: "SUNWODA SWD-COS4.264"
+compatible: "sunwoda,cos3rr09"
+
+include: battery-smart.yaml
+
+properties:
+   enum-name:
+      type: string
+      default: "sunwoda,cos3rr09"
+
+   # Fuel Gauge
+   manuf_name:
+      default: "SWD-COS4.264"
+   device_name:
+      default: "DELL 3RR09YMD"
+   ship_mode_reg_addr:
+      default: 0x00
+   ship_mode_reg_data:
+      default: [ 0x0010, 0x0010 ]
+   fet_mfgacc_support:
+      default: 0
+   fet_reg_addr:
+      default: 0x54
+   fet_reg_mask:
+      default: 0x0002
+   fet_disconnect_val:
+      default: 0x0000
+   fet_cfet_mask:
+      default: 0x0004
+   fet_cfet_off_val:
+      default: 0x0000
+
+   # Battery info
+   voltage_max:
+      default: 17800
+   voltage_normal:
+      default: 15200
+   voltage_min:
+      default: 12000
+   precharge_current:
+      default: 256
+   start_charging_min_c:
+      default: 0
+   start_charging_max_c:
+      default: 45
+   charging_min_c:
+      default: -3
+   charging_max_c:
+      default: 50
+   discharging_min_c:
+      default: -5
+   discharging_max_c:
+      default: 70
diff --git a/zephyr/dts/bindings/battery/sunwoda,l22d3pg0.yaml b/zephyr/dts/bindings/battery/sunwoda,l22d3pg0.yaml
new file mode 100644
index 0000000000..a0ff640c6b
--- /dev/null
+++ b/zephyr/dts/bindings/battery/sunwoda,l22d3pg0.yaml
@@ -0,0 +1,54 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "SUNWODA L22D3PG0"
+compatible: "sunwoda,l22d3pg0"
+
+include: battery-smart.yaml
+
+properties:
+   enum-name:
+      type: string
+      default: "sunwoda,l22d3pg0"
+
+   # Fuel gauge
+   manuf_name:
+      default: "Sunwoda"
+   device_name:
+      default: "L22D3PG0"
+   ship_mode_reg_addr:
+      default: 0x34
+   ship_mode_reg_data:
+      default: [ 0x0000, 0x1000 ]
+   fet_mfgacc_support:
+      default: 0
+   fet_reg_addr:
+      default: 0x00
+   fet_reg_mask:
+      default: 0x0018
+   fet_disconnect_val:
+      default: 0x0000
+
+   # Battery info
+   voltage_max:
+      default: 13200
+   voltage_normal:
+      default: 11310
+   voltage_min:
+      default: 9000
+   precharge_current:
+      default: 209
+   start_charging_min_c:
+      default: 0
+   start_charging_max_c:
+      default: 50
+   charging_min_c:
+      default: 0
+   charging_max_c:
+      default: 60
+   discharging_min_c:
+      default: -20
+   discharging_max_c:
+      default: 60
+
diff --git a/zephyr/dts/bindings/battery/sunwoda,l22d3pg1.yaml b/zephyr/dts/bindings/battery/sunwoda,l22d3pg1.yaml
new file mode 100644
index 0000000000..84505cffeb
--- /dev/null
+++ b/zephyr/dts/bindings/battery/sunwoda,l22d3pg1.yaml
@@ -0,0 +1,54 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: "SUNWODA L22D3PG1"
+compatible: "sunwoda,l22d3pg1"
+
+include: battery-smart.yaml
+
+properties:
+   enum-name:
+      type: string
+      default: "sunwoda,l22d3pg1"
+
+   # Fuel gauge
+   manuf_name:
+      default: "Sunwoda"
+   device_name:
+      default: "L22D3PG1"
+   ship_mode_reg_addr:
+      default: 0x34
+   ship_mode_reg_data:
+      default: [ 0x0000, 0x1000 ]
+   fet_mfgacc_support:
+      default: 0
+   fet_reg_addr:
+      default: 0x00
+   fet_reg_mask:
+      default: 0x0018
+   fet_disconnect_val:
+      default: 0x0000
+
+   # Battery info
+   voltage_max:
+      default: 13200
+   voltage_normal:
+      default: 11520
+   voltage_min:
+      default: 9000
+   precharge_current:
+      default: 251
+   start_charging_min_c:
+      default: 0
+   start_charging_max_c:
+      default: 50
+   charging_min_c:
+      default: 0
+   charging_max_c:
+      default: 60
+   discharging_min_c:
+      default: -20
+   discharging_max_c:
+      default: 60
+
diff --git a/zephyr/dts/bindings/cbi/cros-ec-cbi-fw-config-value.yaml b/zephyr/dts/bindings/cbi/cros-ec,cbi-fw-config-value.yaml
index facbb086f1..6c45ffbf0b 100644
--- a/zephyr/dts/bindings/cbi/cros-ec-cbi-fw-config-value.yaml
+++ b/zephyr/dts/bindings/cbi/cros-ec,cbi-fw-config-value.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/cbi/cros-ec-cbi-fw-config.yaml b/zephyr/dts/bindings/cbi/cros-ec,cbi-fw-config.yaml
index b19c9632be..b47c511d5e 100644
--- a/zephyr/dts/bindings/cbi/cros-ec-cbi-fw-config.yaml
+++ b/zephyr/dts/bindings/cbi/cros-ec,cbi-fw-config.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/cbi/named-cbi-ssfc-value.yaml b/zephyr/dts/bindings/cbi/named-cbi-ssfc-value.yaml
index f97d688727..7e04afed87 100644
--- a/zephyr/dts/bindings/cbi/named-cbi-ssfc-value.yaml
+++ b/zephyr/dts/bindings/cbi/named-cbi-ssfc-value.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/cbi/named-cbi-ssfc.yaml b/zephyr/dts/bindings/cbi/named-cbi-ssfc.yaml
index bd6c1d535b..2db330079d 100644
--- a/zephyr/dts/bindings/cbi/named-cbi-ssfc.yaml
+++ b/zephyr/dts/bindings/cbi/named-cbi-ssfc.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -20,6 +20,7 @@ child-binding:
             description:
               Enum values used only for description purposes
             enum:
+            - AUDIO_CODEC
             - BASE_SENSOR
             - LID_SENSOR
             - LIGHTBAR
diff --git a/zephyr/dts/bindings/charger/chg-chip.yaml b/zephyr/dts/bindings/charger/chg-chip.yaml
index 50e78756d9..58cc487b1b 100644
--- a/zephyr/dts/bindings/charger/chg-chip.yaml
+++ b/zephyr/dts/bindings/charger/chg-chip.yaml
@@ -1,20 +1,9 @@
-# Copyright (c) 2022 The Chromium OS Authors
+# Copyright 2022 The ChromiumOS Authors
 # SPDX-License-Identifier: Apache-2.0
 
 description: Charger chip
 
-properties:
-  port:
-    type: phandle
-    required: true
-    description: |
-      I2C port used to communicate with charger chip
-
-  i2c-addr-flags:
-    type: string
-    required: false
-    description: |
-      I2C address of charger chip
+include: i2c-device.yaml
 
 # Example
 # The charger chips nodes have to be placed under the USB-C
@@ -30,28 +19,30 @@ properties:
 #		port0@0 {
 #			compatible = "named-usbc-port";
 #			reg = <0>;
-#			bc12 {
-#				compatible = "pericom,pi3usb9201";
-#				port = <&i2c_ec_i2c_usb_c0>;
-#			};
-#			chg {
-#				compatible = "siliconmitus,sm5803";
-#				status = "okay";
-#				port = <&i2c_ec_i2c_usb_c0>;
-#			};
+#			bc12 = <&bc12_port0>;
+#			chg = <&chg_port0>;
 #		};
 #		port1@1 {
 #			compatible = "named-usbc-port";
 #			reg = <1>;
-#			bc12 {
-#				compatible = "pericom,pi3usb9201";
-#				port = <&i2c_ec_i2c_sub_usb_c1>;
-#			};
-#			chg {
-#				compatible = "siliconmitus,sm5803";
-#				status = "okay";
-#				port = <&i2c_ec_i2c_sub_usb_c1>;
-#			};
+#			bc12 = <&bc12_port1>;
+#			chg = <&chg_port1>;
+#		};
+#	};
+#
+#	&i2c5 {
+#		chg_port0: sm5803@32 {
+#			compatible = "siliconmitus,sm5803";
+#			status = "okay";
+#			reg = <0x32>;
+#		};
+#	};
+#
+#	&i2c4 {
+#		chg_port1: sm5803@32 {
+#			compatible = "siliconmitus,sm5803";
+#			status = "okay";
+#			reg = <0x32>;
 #		};
 #	};
 #
@@ -63,23 +54,19 @@ properties:
 #		port0@0 {
 #			compatible = "named-usbc-port";
 #			reg = <0>;
-#			bc12 {
-#				compatible = "pericom,pi3usb9201";
-#				port = <&i2c_ec_i2c_usb_c0>;
-#			};
-#			chg {
-#				compatible = "siliconmitus,sm5803";
-#				status = "okay";
-#				port = <&i2c_ec_i2c_usb_c0>;
-#			};
+#			chg = <&charger>;
 #		};
 #		port1@1 {
 #			compatible = "named-usbc-port";
 #			reg = <1>;
-#			bc12 {
-#				compatible = "pericom,pi3usb9201";
-#				port = <&i2c_ec_i2c_sub_usb_c1>;
-#			};
+#			bc12 = <&bc12_port1>;
+#		};
+#	};
+#
+#	&i2c5 {
+#		charger: sm5803@32 {
+#			compatible = "siliconmitus,sm5803";
+#			status = "okay";
+#			reg = <0x32>;
 #		};
 #	};
-
diff --git a/zephyr/dts/bindings/charger/intersil,isl923x.yaml b/zephyr/dts/bindings/charger/intersil,isl923x.yaml
index 2da947fea8..a9c2e8f814 100644
--- a/zephyr/dts/bindings/charger/intersil,isl923x.yaml
+++ b/zephyr/dts/bindings/charger/intersil,isl923x.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/charger/intersil,isl9241.yaml b/zephyr/dts/bindings/charger/intersil,isl9241.yaml
index 567c2077a6..7423e46a23 100644
--- a/zephyr/dts/bindings/charger/intersil,isl9241.yaml
+++ b/zephyr/dts/bindings/charger/intersil,isl9241.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/charger/richtek,rt9490.yaml b/zephyr/dts/bindings/charger/richtek,rt9490.yaml
index 96d8b81fa0..ecd25696f3 100644
--- a/zephyr/dts/bindings/charger/richtek,rt9490.yaml
+++ b/zephyr/dts/bindings/charger/richtek,rt9490.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -7,3 +7,8 @@ description: Richtek RT9490 Charger
 compatible: "richtek,rt9490"
 
 include: chg-chip.yaml
+
+properties:
+    thermistor:
+      type: phandle
+      description: Underlying thermistor device to measure temperature
diff --git a/zephyr/dts/bindings/charger/siliconmitus,sm5803.yaml b/zephyr/dts/bindings/charger/siliconmitus,sm5803.yaml
index 9aac5f3d8b..20d88d1659 100644
--- a/zephyr/dts/bindings/charger/siliconmitus,sm5803.yaml
+++ b/zephyr/dts/bindings/charger/siliconmitus,sm5803.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/charger/ti,bq25710.yaml b/zephyr/dts/bindings/charger/ti,bq25710.yaml
index 2ebf194b77..d0bc20a015 100644
--- a/zephyr/dts/bindings/charger/ti,bq25710.yaml
+++ b/zephyr/dts/bindings/charger/ti,bq25710.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/console/ec-console.yaml b/zephyr/dts/bindings/console/ec-console.yaml
index f79ddd67b0..0f46524a39 100644
--- a/zephyr/dts/bindings/console/ec-console.yaml
+++ b/zephyr/dts/bindings/console/ec-console.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/cros_bbram/named-bbram-regions.yaml b/zephyr/dts/bindings/cros_bbram/named-bbram-regions.yaml
index 8b12473d0a..a8824c3fb1 100644
--- a/zephyr/dts/bindings/cros_bbram/named-bbram-regions.yaml
+++ b/zephyr/dts/bindings/cros_bbram/named-bbram-regions.yaml
@@ -1,4 +1,4 @@
-# Copyright (c) 2021 Google Inc.
+# Copyright 2021 Google LLC
 # SPDX-License-Identifier: Apache-2.0
 description: Named battery-backed RAM parent node
 
diff --git a/zephyr/dts/bindings/cros_dbg/nuvoton,npcx-cros-dbg.yaml b/zephyr/dts/bindings/cros_dbg/nuvoton,npcx-cros-dbg.yaml
index c3a9937d45..0cdfd41e31 100644
--- a/zephyr/dts/bindings/cros_dbg/nuvoton,npcx-cros-dbg.yaml
+++ b/zephyr/dts/bindings/cros_dbg/nuvoton,npcx-cros-dbg.yaml
@@ -1,4 +1,4 @@
-# Copyright (c) 2021 Google Inc.
+# Copyright 2021 Google LLC
 # SPDX-License-Identifier: Apache-2.0
 
 description: Nuvoton, NPCX Debug Interface
diff --git a/zephyr/dts/bindings/cros_displight/cros-ec,displight.yaml b/zephyr/dts/bindings/cros_displight/cros-ec,displight.yaml
index df51bf19dc..1ce1892fd2 100644
--- a/zephyr/dts/bindings/cros_displight/cros-ec,displight.yaml
+++ b/zephyr/dts/bindings/cros_displight/cros-ec,displight.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -14,11 +14,6 @@ properties:
     required: true
     description: PWM controlling the display backlight level.
 
-  frequency:
-    type: int
-    required: true
-    description: PWM frequency in Hz.
-
   generic-pwm-channel:
     type: int
     required: false
diff --git a/zephyr/dts/bindings/cros_flash/cros-ec,flash-layout.yaml b/zephyr/dts/bindings/cros_flash/cros-ec,flash-layout.yaml
index 991f3c71cf..0ec9bdfbb0 100644
--- a/zephyr/dts/bindings/cros_flash/cros-ec,flash-layout.yaml
+++ b/zephyr/dts/bindings/cros_flash/cros-ec,flash-layout.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/cros_flash/cros-flash-controller.yaml b/zephyr/dts/bindings/cros_flash/cros-flash-controller.yaml
index b9c8a9f149..9469a02004 100644
--- a/zephyr/dts/bindings/cros_flash/cros-flash-controller.yaml
+++ b/zephyr/dts/bindings/cros_flash/cros-flash-controller.yaml
@@ -6,7 +6,3 @@
 include: base.yaml
 
 bus: crosflash
-
-properties:
-    label:
-      required: true
diff --git a/zephyr/dts/bindings/cros_flash/microchip,xec-cros-flash.yaml b/zephyr/dts/bindings/cros_flash/microchip,xec-cros-flash.yaml
index 2b9aea1554..a5c1155b9e 100644
--- a/zephyr/dts/bindings/cros_flash/microchip,xec-cros-flash.yaml
+++ b/zephyr/dts/bindings/cros_flash/microchip,xec-cros-flash.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/cros_kb_raw/cros-kb-raw-controller.yaml b/zephyr/dts/bindings/cros_kb_raw/cros-kb-raw-controller.yaml
deleted file mode 100644
index e8c95419e1..0000000000
--- a/zephyr/dts/bindings/cros_kb_raw/cros-kb-raw-controller.yaml
+++ /dev/null
@@ -1,12 +0,0 @@
-# Copyright 2020 Google LLC
-# SPDX-License-Identifier: Apache-2.0
-
-# Common fields for Chrome OS raw keyboard devices
-
-include: base.yaml
-
-bus: croskb
-
-properties:
-    label:
-      required: true
diff --git a/zephyr/dts/bindings/cros_kb_raw/ite,it8xxx2-cros-kb-raw.yaml b/zephyr/dts/bindings/cros_kb_raw/ite,it8xxx2-cros-kb-raw.yaml
index 9c1d635b61..a03da035b1 100644
--- a/zephyr/dts/bindings/cros_kb_raw/ite,it8xxx2-cros-kb-raw.yaml
+++ b/zephyr/dts/bindings/cros_kb_raw/ite,it8xxx2-cros-kb-raw.yaml
@@ -5,7 +5,7 @@ description: ITE, it8xxx2-cros-kb-raw node
 
 compatible: "ite,it8xxx2-cros-kb-raw"
 
-include: cros-kb-raw-controller.yaml
+include: base.yaml
 
 properties:
     reg:
diff --git a/zephyr/dts/bindings/cros_kb_raw/microchip,xec-cros-kb-raw.yaml b/zephyr/dts/bindings/cros_kb_raw/microchip,xec-cros-kb-raw.yaml
index 79ca1dda4a..9ad5a50bfd 100644
--- a/zephyr/dts/bindings/cros_kb_raw/microchip,xec-cros-kb-raw.yaml
+++ b/zephyr/dts/bindings/cros_kb_raw/microchip,xec-cros-kb-raw.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -6,7 +6,7 @@ description: Microchip, xec-cros-kb-raw node
 
 compatible: "microchip,xec-cros-kb-raw"
 
-include: [cros-kb-raw-controller.yaml, pinctrl-device.yaml]
+include: [base.yaml, pinctrl-device.yaml]
 
 properties:
     reg:
diff --git a/zephyr/dts/bindings/cros_kb_raw/nuvoton,npcx-cros-kb-raw.yaml b/zephyr/dts/bindings/cros_kb_raw/nuvoton,npcx-cros-kb-raw.yaml
index 241cd11cbf..dbecfb0502 100644
--- a/zephyr/dts/bindings/cros_kb_raw/nuvoton,npcx-cros-kb-raw.yaml
+++ b/zephyr/dts/bindings/cros_kb_raw/nuvoton,npcx-cros-kb-raw.yaml
@@ -5,7 +5,7 @@ description: Nuvoton, NPCX-cros-kb-raw node
 
 compatible: "nuvoton,npcx-cros-kb-raw"
 
-include: [cros-kb-raw-controller.yaml, pinctrl-device.yaml]
+include: [base.yaml, pinctrl-device.yaml]
 
 properties:
     reg:
diff --git a/zephyr/dts/bindings/cros_mkbp_event/ec-mkbp-event.yaml b/zephyr/dts/bindings/cros_mkbp_event/ec-wake-mask-event.yaml
index d3ec3c8ff5..04e95ea829 100644
--- a/zephyr/dts/bindings/cros_mkbp_event/ec-mkbp-event.yaml
+++ b/zephyr/dts/bindings/cros_mkbp_event/ec-wake-mask-event.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/cros_rtc/cros-rtc.yaml b/zephyr/dts/bindings/cros_rtc/cros-rtc.yaml
deleted file mode 100644
index f754826404..0000000000
--- a/zephyr/dts/bindings/cros_rtc/cros-rtc.yaml
+++ /dev/null
@@ -1,12 +0,0 @@
-# Copyright 2021 Google LLC
-# SPDX-License-Identifier: Apache-2.0
-
-# Common fields for Chrome OS RTC devices
-
-include: base.yaml
-
-bus: crosrtc
-
-properties:
-    label:
-      required: true
diff --git a/zephyr/dts/bindings/cros_rtc/microchip,xec-cros-rtc.yaml b/zephyr/dts/bindings/cros_rtc/microchip,xec-cros-rtc.yaml
index 6b22559d01..f22b26c2ec 100644
--- a/zephyr/dts/bindings/cros_rtc/microchip,xec-cros-rtc.yaml
+++ b/zephyr/dts/bindings/cros_rtc/microchip,xec-cros-rtc.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/cros_rtc/nuvoton,npcx-cros-mtc.yaml b/zephyr/dts/bindings/cros_rtc/nuvoton,npcx-cros-mtc.yaml
index 547b6897e8..3db0880e75 100644
--- a/zephyr/dts/bindings/cros_rtc/nuvoton,npcx-cros-mtc.yaml
+++ b/zephyr/dts/bindings/cros_rtc/nuvoton,npcx-cros-mtc.yaml
@@ -11,9 +11,6 @@ properties:
     reg:
       required: true
 
-    label:
-      required: true
-
     mtc-alarm:
       type: phandle
       required: true
diff --git a/zephyr/dts/bindings/cros_rtc/nxp,rtc-pcf85063a.yaml b/zephyr/dts/bindings/cros_rtc/nxp,rtc-pcf85063a.yaml
index 8b881d2f2c..db6f3f9685 100644
--- a/zephyr/dts/bindings/cros_rtc/nxp,rtc-pcf85063a.yaml
+++ b/zephyr/dts/bindings/cros_rtc/nxp,rtc-pcf85063a.yaml
@@ -8,9 +8,6 @@ compatible: "nxp,rtc-pcf85063a"
 include: [base.yaml, i2c-device.yaml]
 
 properties:
-    label:
-      required: true
-
     int-pin:
       type: phandle
       required: true
diff --git a/zephyr/dts/bindings/cros_rtc/renesas,rtc-idt1337ag.yaml b/zephyr/dts/bindings/cros_rtc/renesas,rtc-idt1337ag.yaml
index ad4e5ce891..c2643f0e84 100644
--- a/zephyr/dts/bindings/cros_rtc/renesas,rtc-idt1337ag.yaml
+++ b/zephyr/dts/bindings/cros_rtc/renesas,rtc-idt1337ag.yaml
@@ -8,9 +8,6 @@ compatible: "renesas,rtc-idt1337ag"
 include: [base.yaml, i2c-device.yaml]
 
 properties:
-    label:
-      required: true
-
     int-pin:
       type: phandle
       required: true
diff --git a/zephyr/dts/bindings/cros_shi/ite,it8xxx2-cros-shi.yaml b/zephyr/dts/bindings/cros_shi/ite,it8xxx2-cros-shi.yaml
index 0ad49f1487..2e2c6b74a5 100644
--- a/zephyr/dts/bindings/cros_shi/ite,it8xxx2-cros-shi.yaml
+++ b/zephyr/dts/bindings/cros_shi/ite,it8xxx2-cros-shi.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/cros_shi/nuvoton,npcx-cros-shi.yaml b/zephyr/dts/bindings/cros_shi/nuvoton,npcx-cros-shi.yaml
index 0761ba3526..9a5596bd4c 100644
--- a/zephyr/dts/bindings/cros_shi/nuvoton,npcx-cros-shi.yaml
+++ b/zephyr/dts/bindings/cros_shi/nuvoton,npcx-cros-shi.yaml
@@ -1,4 +1,4 @@
-# Copyright (c) 2021 Google Inc.
+# Copyright 2021 Google LLC
 # SPDX-License-Identifier: Apache-2.0
 
 description: Nuvoton, NPCX Serial Host Interface (SHI) node
diff --git a/zephyr/dts/bindings/emul/cros,bb-retimer-emul.yaml b/zephyr/dts/bindings/emul/cros,bb-retimer-emul.yaml
index 007a73b17b..11dd5f5218 100644
--- a/zephyr/dts/bindings/emul/cros,bb-retimer-emul.yaml
+++ b/zephyr/dts/bindings/emul/cros,bb-retimer-emul.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/emul/cros,clock-control-emul.yaml b/zephyr/dts/bindings/emul/cros,clock-control-emul.yaml
index fa632ea2d4..746c883942 100644
--- a/zephyr/dts/bindings/emul/cros,clock-control-emul.yaml
+++ b/zephyr/dts/bindings/emul/cros,clock-control-emul.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/emul/cros,i2c-mock.yaml b/zephyr/dts/bindings/emul/cros,i2c-mock.yaml
index 7da69028bd..11dbb62b45 100644
--- a/zephyr/dts/bindings/emul/cros,i2c-mock.yaml
+++ b/zephyr/dts/bindings/emul/cros,i2c-mock.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -7,6 +7,7 @@ description: A generic I2C mock
 compatible: "cros,i2c-mock"
 
 include: base.yaml
+
 properties:
    reg:
      required: true
diff --git a/zephyr/dts/bindings/emul/cros,isl923x-emul.yaml b/zephyr/dts/bindings/emul/cros,isl923x-emul.yaml
index 81663b5509..10ad8d1ba9 100644
--- a/zephyr/dts/bindings/emul/cros,isl923x-emul.yaml
+++ b/zephyr/dts/bindings/emul/cros,isl923x-emul.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -7,6 +7,7 @@ description: ISL923X Charger emulator
 compatible: "cros,isl923x-emul"
 
 include: base.yaml
+
 properties:
    reg:
      required: true
diff --git a/zephyr/dts/bindings/emul/cros,lis2dw12-emul.yaml b/zephyr/dts/bindings/emul/cros,lis2dw12-emul.yaml
index 44c29fbe56..f0a8632c18 100644
--- a/zephyr/dts/bindings/emul/cros,lis2dw12-emul.yaml
+++ b/zephyr/dts/bindings/emul/cros,lis2dw12-emul.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -7,6 +7,7 @@ description: CROS implementation of the LIS2DW12 emulator
 compatible: "cros,lis2dw12-emul"
 
 include: base.yaml
+
 properties:
   reg:
     required: true
diff --git a/zephyr/dts/bindings/emul/cros,ln9310-emul.yaml b/zephyr/dts/bindings/emul/cros,ln9310-emul.yaml
index ba37836fb5..7f086cd5f2 100644
--- a/zephyr/dts/bindings/emul/cros,ln9310-emul.yaml
+++ b/zephyr/dts/bindings/emul/cros,ln9310-emul.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -16,4 +16,3 @@ properties:
     description:
       GPIO that receives interrupt signal from this device.
     required: true
-
diff --git a/zephyr/dts/bindings/emul/cros,ps8xxx-emul.yaml b/zephyr/dts/bindings/emul/cros,ps8xxx-emul.yaml
index e2d45ca52f..31e53903d2 100644
--- a/zephyr/dts/bindings/emul/cros,ps8xxx-emul.yaml
+++ b/zephyr/dts/bindings/emul/cros,ps8xxx-emul.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -6,15 +6,9 @@ description: Zephyr PS8xxx emulator
 
 compatible: "cros,ps8xxx-emul"
 
-include: base.yaml
+include: tcpci.yaml
 
 properties:
-    tcpci-i2c:
-      type: phandle
-      required: true
-      description:
-        Base TCPCI emulator. Has to be sibling of PS8xxx emulator.
-
     p0-i2c-addr:
       type: int
       required: true
diff --git a/zephyr/dts/bindings/emul/cros,pwm-mock.yaml b/zephyr/dts/bindings/emul/cros,pwm-mock.yaml
new file mode 100644
index 0000000000..3b3a992cd0
--- /dev/null
+++ b/zephyr/dts/bindings/emul/cros,pwm-mock.yaml
@@ -0,0 +1,15 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: A generic PWM mock
+compatible: "cros,pwm-mock"
+include: [pwm-controller.yaml, base.yaml]
+properties:
+   reg:
+     required: true
+
+pwm-cells:
+    - channel
+    - period
+    - flags
diff --git a/zephyr/dts/bindings/emul/cros,sn5s330.yaml b/zephyr/dts/bindings/emul/cros,sn5s330-emul.yaml
index 0cfe3ebe9c..cbdf320bc1 100644
--- a/zephyr/dts/bindings/emul/cros,sn5s330.yaml
+++ b/zephyr/dts/bindings/emul/cros,sn5s330-emul.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/emul/cros,tcpci-generic-emul.yaml b/zephyr/dts/bindings/emul/cros,tcpci-generic-emul.yaml
new file mode 100644
index 0000000000..73d115f5ed
--- /dev/null
+++ b/zephyr/dts/bindings/emul/cros,tcpci-generic-emul.yaml
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Zephyr TCPCI Generic Emulator
+
+compatible: "cros,tcpci-generic-emul"
+
+include: tcpci.yaml
diff --git a/zephyr/dts/bindings/emul/cros-ec,flash-emul.yaml b/zephyr/dts/bindings/emul/cros-ec,flash-emul.yaml
index 490258e8a9..c6a20f9991 100644
--- a/zephyr/dts/bindings/emul/cros-ec,flash-emul.yaml
+++ b/zephyr/dts/bindings/emul/cros-ec,flash-emul.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/emul/cros-ec,kb-raw-emul.yaml b/zephyr/dts/bindings/emul/cros-ec,kb-raw-emul.yaml
index 781f1498d7..f6821dbc2b 100644
--- a/zephyr/dts/bindings/emul/cros-ec,kb-raw-emul.yaml
+++ b/zephyr/dts/bindings/emul/cros-ec,kb-raw-emul.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -6,7 +6,7 @@ description: Emulator for Chromiumos EC raw keyboard driver.
 
 compatible: "cros-ec,kb-raw-emul"
 
-include: cros-kb-raw-controller.yaml
+include: base.yaml
 
 properties:
   rows:
diff --git a/zephyr/dts/bindings/emul/cros-ec,rtc-emul.yaml b/zephyr/dts/bindings/emul/cros-ec,rtc-emul.yaml
new file mode 100644
index 0000000000..d3efd6835f
--- /dev/null
+++ b/zephyr/dts/bindings/emul/cros-ec,rtc-emul.yaml
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Emulator for Chromiumos EC flash driver.
+
+compatible: "cros-ec,rtc-emul"
+
+include: base.yaml
diff --git a/zephyr/dts/bindings/emul/cros,tcpci-emul.yaml b/zephyr/dts/bindings/emul/tcpci.yaml
index 3b218acd62..9f825c5dda 100644
--- a/zephyr/dts/bindings/emul/cros,tcpci-emul.yaml
+++ b/zephyr/dts/bindings/emul/tcpci.yaml
@@ -1,10 +1,8 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
-description: Zephyr TCPCI Emulator
-
-compatible: "cros,tcpci-emul"
+description: Common TCPCI properties
 
 include: base.yaml
 
diff --git a/zephyr/dts/bindings/emul/zephyr,bma255.yaml b/zephyr/dts/bindings/emul/zephyr,bma255.yaml
index 40750196c1..3f504e05a5 100644
--- a/zephyr/dts/bindings/emul/zephyr,bma255.yaml
+++ b/zephyr/dts/bindings/emul/zephyr,bma255.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/emul/zephyr,bmi.yaml b/zephyr/dts/bindings/emul/zephyr,bmi.yaml
index a754287bcc..6280d5cc39 100644
--- a/zephyr/dts/bindings/emul/zephyr,bmi.yaml
+++ b/zephyr/dts/bindings/emul/zephyr,bmi.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/emul/zephyr,pi3usb9201.yaml b/zephyr/dts/bindings/emul/zephyr,pi3usb9201-emul.yaml
index 856703e9d7..1f26a62f73 100644
--- a/zephyr/dts/bindings/emul/zephyr,pi3usb9201.yaml
+++ b/zephyr/dts/bindings/emul/zephyr,pi3usb9201-emul.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/emul/zephyr,smart-battery.yaml b/zephyr/dts/bindings/emul/zephyr,smart-battery.yaml
index cc1d2f368d..4c46fd4f64 100644
--- a/zephyr/dts/bindings/emul/zephyr,smart-battery.yaml
+++ b/zephyr/dts/bindings/emul/zephyr,smart-battery.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -153,3 +153,9 @@ properties:
         required: false
         default: "LION"
         description: Manufacturer data. Length has to be smaller than 32 bytes.
+
+    mf-info:
+       type: string
+       required: false
+       default: "LION"
+       description: Manufacturer info. Length has to be smaller than 32 bytes.
diff --git a/zephyr/dts/bindings/emul/zephyr,syv682x.yaml b/zephyr/dts/bindings/emul/zephyr,syv682x-emul.yaml
index 8652b42b82..2ad9241f96 100644
--- a/zephyr/dts/bindings/emul/zephyr,syv682x.yaml
+++ b/zephyr/dts/bindings/emul/zephyr,syv682x-emul.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/emul/zephyr,tcs3400.yaml b/zephyr/dts/bindings/emul/zephyr,tcs3400.yaml
index a4474ec279..f214a21064 100644
--- a/zephyr/dts/bindings/emul/zephyr,tcs3400.yaml
+++ b/zephyr/dts/bindings/emul/zephyr,tcs3400.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/fan/cros-ec,fans.yaml b/zephyr/dts/bindings/fan/cros-ec,fans.yaml
index ee1d8be891..9aa6317f61 100644
--- a/zephyr/dts/bindings/fan/cros-ec,fans.yaml
+++ b/zephyr/dts/bindings/fan/cros-ec,fans.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -29,10 +29,6 @@ child-binding:
       required: true
       description:
         PWM channel to control the fan
-    pwm-frequency:
-      type: int
-      description:
-        PWM frequency in Hz.
     tach:
       type: phandle
       required: false
diff --git a/zephyr/dts/bindings/gpio/gpio-id.yaml b/zephyr/dts/bindings/gpio/cros-ec,gpio-id.yaml
index 24322b3de8..689171c1d4 100644
--- a/zephyr/dts/bindings/gpio/gpio-id.yaml
+++ b/zephyr/dts/bindings/gpio/cros-ec,gpio-id.yaml
@@ -1,6 +1,6 @@
 description: Defines board version and sku id gpios
 
-compatible: cros-ec,gpio-id
+compatible: "cros-ec,gpio-id"
 
 properties:
   bits:
diff --git a/zephyr/dts/bindings/gpio/cros-ec,gpio-interrupts.yaml b/zephyr/dts/bindings/gpio/cros-ec,gpio-interrupts.yaml
index 56cf17a5a1..bb6b4001f4 100644
--- a/zephyr/dts/bindings/gpio/cros-ec,gpio-interrupts.yaml
+++ b/zephyr/dts/bindings/gpio/cros-ec,gpio-interrupts.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/zephyr/dts/bindings/gpio/hibernate-wake-pins.yaml b/zephyr/dts/bindings/gpio/cros-ec,hibernate-wake-pins.yaml
index 0d79efa79d..a6cb488c48 100644
--- a/zephyr/dts/bindings/gpio/hibernate-wake-pins.yaml
+++ b/zephyr/dts/bindings/gpio/cros-ec,hibernate-wake-pins.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/gpio/cros-ec,usba-port-enable-pins.yaml b/zephyr/dts/bindings/gpio/cros-ec,usba-port-enable-pins.yaml
index 8ee2a380f3..92532c1893 100644
--- a/zephyr/dts/bindings/gpio/cros-ec,usba-port-enable-pins.yaml
+++ b/zephyr/dts/bindings/gpio/cros-ec,usba-port-enable-pins.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/gpio/gpio-enum-name.yaml b/zephyr/dts/bindings/gpio/gpio-enum-name.yaml
index bdfb1fba1c..8252ca75e1 100644
--- a/zephyr/dts/bindings/gpio/gpio-enum-name.yaml
+++ b/zephyr/dts/bindings/gpio/gpio-enum-name.yaml
@@ -4,12 +4,17 @@ properties:
     type: string
     description:
       Enum used in code.
-      These names should only be used for legacy common code.
+      These names MUST ONLY be referenced by legacy code that is
+      included with Zephyr projects.
 
       Some development boards like trogdor, volteer etc. shim in
       the older baseboard/board headers and code, so they
       are also using most of these names. When these
       boards get removed, these names can be removed
+
+      Do not add any more names to this list. Please remove
+      any names that are not referenced by Zephyr projects (or
+      are not in included common legacy code)
     enum:
       - GPIO_AC_PRESENT
       - GPIO_AP_EC_SYSRST_ODL
@@ -42,8 +47,6 @@ properties:
       - GPIO_EN_PP3300_A
       - GPIO_EN_PP5000
       - GPIO_EN_PP5000_A
-      - GPIO_EN_PP5000_USB_A0_VBUS
-      - GPIO_EN_PP5000_USB_A1_VBUS
       - GPIO_EN_PP5000_USBA
       - GPIO_EN_PP5000_USBA_R
       - GPIO_EN_PPVAR_VCCIN
@@ -128,128 +131,37 @@ properties:
       - GPIO_VOLUME_DOWN_L
       - GPIO_VOLUME_UP_L
       - GPIO_WARM_RESET_L
-      - IOEX_5V_DC_DC_MODE_CTRL
-      - IOEX_ATMEL_MISO
-      - IOEX_ATMEL_MOSI
-      - IOEX_ATMEL_RESET_L
-      - IOEX_ATMEL_SCLK
-      - IOEX_ATMEL_SS
-      - IOEX_BAT_LED_AMBER_L
-      - IOEX_BAT_LED_GREEN_FULL_L
-      - IOEX_BAT_LED_RED_L
-      - IOEX_BAT_LED_WHITE_L
-      - IOEX_BOARD_ID_DET0
-      - IOEX_BOARD_ID_DET1
-      - IOEX_BOARD_ID_DET2
-      - IOEX_C1_CHARGER_LED_AMBER_DB
-      - IOEX_C1_CHARGER_LED_WHITE_DB
-      - IOEX_DAC_BUF1_LATCH_FAULT_L
-      - IOEX_DAC_BUF2_LATCH_FAULT_L
-      - IOEX_DONGLE_DET
-      - IOEX_DUT_CHG_EN
-      - IOEX_EN_PP3300_DP
-      - IOEX_EN_PP3300_ETH
-      - IOEX_EN_PP5000_ALT_3P3
-      - IOEX_EN_PP5000_USB_A0_VBUS
-      - IOEX_EN_PP5000_USB_A1_VBUS_DB
-      - IOEX_EN_PWR_HDMI
-      - IOEX_EN_PWR_HDMI_DB
-      - IOEX_EN_USB_A0_5V
-      - IOEX_EN_USB_A1_5V_DB
-      - IOEX_EN_USB_A1_5V_DB_OPT1
-      - IOEX_EN_USB_A1_5V_DB_OPT2
-      - IOEX_EN_VOUT_BUF_CC1
-      - IOEX_EN_VOUT_BUF_CC2
-      - IOEX_FAULT_CLEAR_CC
-      - IOEX_HDMI_DATA_EN
-      - IOEX_HDMI_DATA_EN_DB
-      - IOEX_HDMI_POWER_EN_DB
-      - IOEX_HOST_CHRG_DET
-      - IOEX_HOST_OR_CHG_CTL
-      - IOEX_ID_1_USB_C0_FRS_EN
-      - IOEX_ID_1_USB_C0_OC_ODL
-      - IOEX_ID_1_USB_C0_RT_RST_ODL
-      - IOEX_ID_1_USB_C1_OC_ODL
-      - IOEX_ID_1_USB_C2_FRS_EN
-      - IOEX_ID_1_USB_C2_OC_ODL
-      - IOEX_ID_1_USB_C2_RT_RST_ODL
-      - IOEX_KB_BL_EN
-      - IOEX_LED_BLUE
-      - IOEX_LED_GREEN
-      - IOEX_LED_ORANGE
-      - IOEX_PP3300_DP_FAULT_L
-      - IOEX_PP5000_SRC_SEL
-      - IOEX_PPC_ID
-      - IOEX_PWR_LED_WHITE_L
-      - IOEX_SBU_FLIP_SEL
-      - IOEX_SBU_UART_SEL
-      - IOEX_SYS_PWR_IRQ_ODL
-      - IOEX_TCA_GPIO_DBG_LED_K_ODL
-      - IOEX_UART_18_SEL
-      - IOEX_USB3_A0_FAULT_L
-      - IOEX_USB3_A0_MUX_EN_L
-      - IOEX_USB3_A0_MUX_SEL
-      - IOEX_USB3_A0_PWR_EN
-      - IOEX_USB3_A1_FAULT_L
-      - IOEX_USB3_A1_MUX_SEL
-      - IOEX_USB3_A1_PWR_EN
-      - IOEX_USB_A0_CHARGE_EN_L
-      - IOEX_USB_A0_LIMIT_SDP
-      - IOEX_USB_A0_RETIMER_EN
-      - IOEX_USB_A0_RETIMER_RST
-      - IOEX_USB_A1_CHARGE_EN_DB_L
-      - IOEX_USB_A1_CHARGE_EN_DB_L_OPT1
-      - IOEX_USB_A1_CHARGE_EN_DB_L_OPT2
-      - IOEX_USB_A1_FAULT_DB_ODL
-      - IOEX_USB_A1_LIMIT_SDP_DB
       - IOEX_USB_A1_RETIMER_EN
-      - IOEX_USB_A1_RETIMER_EN_OPT1
-      - IOEX_USB_A1_RETIMER_EN_OPT2
-      - IOEX_USB_A1_RETIMER_RST
-      - IOEX_USB_A1_RETIMER_RST_DB
       - IOEX_USB_C0_BB_RETIMER_LS_EN
       - IOEX_USB_C0_BB_RETIMER_RST
       - IOEX_USB_C0_C1_OC
-      - IOEX_USB_C0_DATA_EN
-      - IOEX_USB_C0_FAULT_ODL
       - IOEX_USB_C0_FRS_EN
-      - IOEX_USB_C0_OC_ODL
-      - IOEX_USB_C0_PPC_EN_L
+      - IOEX_USB_C0_HBR_LS_EN
+      - IOEX_USB_C0_HBR_RST
+      - IOEX_USB_C0_MUX_SBU_SEL_0
+      - IOEX_USB_C0_MUX_SBU_SEL_1
       - IOEX_USB_C0_PPC_ILIM_3A_EN
-      - IOEX_USB_C0_RT_RST_ODL
       - IOEX_USB_C0_SBU_FLIP
       - IOEX_USB_C0_TCPC_FASTSW_CTL_EN
       - IOEX_USB_C0_USB_MUX_CNTRL_0
       - IOEX_USB_C0_USB_MUX_CNTRL_1
       - IOEX_USB_C1_BB_RETIMER_LS_EN
       - IOEX_USB_C1_BB_RETIMER_RST
-      - IOEX_USB_C1_DATA_EN
       - IOEX_USB_C1_FAULT_ODL
-      - IOEX_USB_C1_FRS_EN
+      - IOEX_USB_C1_HBR_LS_EN
+      - IOEX_USB_C1_HBR_RST
       - IOEX_USB_C1_HPD
       - IOEX_USB_C1_HPD_IN_DB
-      - IOEX_USB_C1_IN_HPD
-      - IOEX_USB_C1_MUX_RST_DB
-      - IOEX_USB_C1_OC_ODL
-      - IOEX_USB_C1_POWER_SWITCH_ID
-      - IOEX_USB_C1_PPC_EN_L
       - IOEX_USB_C1_PPC_ILIM_3A_EN
-      - IOEX_USB_C1_RT_RST_ODL
       - IOEX_USB_C1_SBU_FLIP
       - IOEX_USB_C1_TCPC_FASTSW_CTL_EN
       - IOEX_USB_C2_BB_RETIMER_LS_EN
       - IOEX_USB_C2_BB_RETIMER_RST
+      - IOEX_USB_C2_HBR_RST
+      - IOEX_USB_C2_HBR_LS_EN
       - IOEX_USB_C2_C3_OC
       - IOEX_USB_C2_FRS_EN
-      - IOEX_USB_C2_OC_ODL
-      - IOEX_USB_C2_RT_RST_ODL
-      - IOEX_USB_C2_USB_MUX_CNTRL_0
-      - IOEX_USB_C2_USB_MUX_CNTRL_1
       - IOEX_USB_C3_BB_RETIMER_LS_EN
       - IOEX_USB_C3_BB_RETIMER_RST
-      - IOEX_USB_DUTCHG_FLT_ODL
-      - IOEX_USBH_PWRDN_L
-      - IOEX_USERVO_FASTBOOT_MUX_SEL
-      - IOEX_USERVO_FAULT_L
-      - IOEX_USERVO_POWER_EN
-      - IOEX_VBUS_DISCHRG_EN
+      - IOEX_USB_C3_HBR_RST
+      - IOEX_USB_C3_HBR_LS_EN
diff --git a/zephyr/dts/bindings/gpio/named-gpios.yaml b/zephyr/dts/bindings/gpio/named-gpios.yaml
index 59ed404754..bf0ba7237e 100644
--- a/zephyr/dts/bindings/gpio/named-gpios.yaml
+++ b/zephyr/dts/bindings/gpio/named-gpios.yaml
@@ -10,10 +10,11 @@ child-binding:
     # Must name this property [..-]gpios which
     # is treated specially (looks for #gpio-cells
     # in referenced node so that cell properties can
-    # be specified).
+    # be specified). If this property does not exist, treat
+    # this GPIO as unimplemented.
     gpios:
       type: phandle-array
-      required: true
+      required: false
     "#led-pin-cells":
       type: int
       required: false
@@ -27,5 +28,13 @@ child-binding:
         according to the flags in the gpios node.
       type: boolean
       required: false
+    alias:
+      description:
+        When set, defines an alias for this GPIO's enum-name.
+
+        This is to allow common or generic names in legacy code to map
+        to the particular board's GPIO name.
+      type: string
+      required: false
   led-pin-cells:
     - value
diff --git a/zephyr/dts/bindings/i2c/cros-ec-i2c-port-base.yaml b/zephyr/dts/bindings/i2c/cros-ec-i2c-port-base.yaml
index bd24f32620..7d3aad07f7 100644
--- a/zephyr/dts/bindings/i2c/cros-ec-i2c-port-base.yaml
+++ b/zephyr/dts/bindings/i2c/cros-ec-i2c-port-base.yaml
@@ -1,4 +1,4 @@
-# Copyright (c) 2021 The Chromium OS Authors
+# Copyright 2021 The ChromiumOS Authors
 # SPDX-License-Identifier: Apache-2.0
 
 description: I2C port base properties
@@ -13,55 +13,11 @@ properties:
     description:
       A port number used by remote components like Kernel via the I2C_PASSTHRU
       Host Command
-  enum-name:
-    type: string
+  enum-names:
+    type: string-array
     required: true
     description:
       Enum values used in the source code to refer to the i2c port
-    enum:
-    - I2C_PORT_ACCEL
-    - I2C_PORT_BATTERY
-    - I2C_PORT_CHARGER
-    - I2C_PORT_EEPROM
-    - I2C_PORT_EVB_0
-    - I2C_PORT_EVB_1
-    - I2C_PORT_EVB_2
-    - I2C_PORT_EVB_3
-    - I2C_PORT_EVB_7
-    - I2C_PORT_KB_DISCRETE
-    - I2C_PORT_MP2964
-    - I2C_PORT_OPT_4
-    - I2C_PORT_PORT80
-    - I2C_PORT_POWER
-    - I2C_PORT_PPC0
-    - I2C_PORT_PPC1
-    - I2C_PORT_RTC
-    - I2C_PORT_SENSOR
-    - I2C_PORT_TCPC0
-    - I2C_PORT_TCPC1
-    - I2C_PORT_THERMAL_AP
-    - I2C_PORT_TYPEC_0
-    - I2C_PORT_TYPEC_1
-    - I2C_PORT_TYPEC_2
-    - I2C_PORT_TYPEC_3
-    - I2C_PORT_TYPEC_AIC_1
-    - I2C_PORT_TYPEC_AIC_2
-    - I2C_PORT_USB_1_MIX
-    - I2C_PORT_USB_C0
-    - I2C_PORT_USB_C0_TCPC
-    - I2C_PORT_USB_C0_C2_BC12
-    - I2C_PORT_USB_C0_C2_MUX
-    - I2C_PORT_USB_C0_C2_PPC
-    - I2C_PORT_USB_C0_C2_TCPC
-    - I2C_PORT_USB_C1
-    - I2C_PORT_USB_C1_BC12
-    - I2C_PORT_USB_C1_PPC
-    - I2C_PORT_USB_C1_TCPC
-    - I2C_PORT_USB_MUX
-    - I2C_PORT_USB_MUX0
-    - I2C_PORT_USB_MUX1
-    - I2C_PORT_VIRTUAL_BATTERY
-    - I2C_PORT_WLC
   dynamic-speed:
     type: boolean
     required: false
diff --git a/zephyr/dts/bindings/i2c/named-i2c-ports.yaml b/zephyr/dts/bindings/i2c/named-i2c-ports.yaml
index 4fce9c3229..5aa95e5f65 100644
--- a/zephyr/dts/bindings/i2c/named-i2c-ports.yaml
+++ b/zephyr/dts/bindings/i2c/named-i2c-ports.yaml
@@ -1,4 +1,4 @@
-# Copyright (c) 2020 The Chromium OS Authors
+# Copyright 2020 The ChromiumOS Authors
 # SPDX-License-Identifier: Apache-2.0
 
 description: Named I2C ports parent node
diff --git a/zephyr/dts/bindings/intel/intel,rvp-board-id.yaml b/zephyr/dts/bindings/intel/intel,rvp-board-id.yaml
index 6ef25aa6bd..9b4fed524e 100644
--- a/zephyr/dts/bindings/intel/intel,rvp-board-id.yaml
+++ b/zephyr/dts/bindings/intel/intel,rvp-board-id.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/kb_discrete/ite,it8801.yaml b/zephyr/dts/bindings/kb_discrete/ite,it8801.yaml
index 228b3500af..036d3d0e69 100644
--- a/zephyr/dts/bindings/kb_discrete/ite,it8801.yaml
+++ b/zephyr/dts/bindings/kb_discrete/ite,it8801.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -14,6 +14,5 @@ include: i2c-device.yaml
 # kb_not_raw: ite-it8801@38 {
 #         compatible = "ite,it8801";
 #         reg = <0x38>;
-#         label = "KEYBOARD_DISCRETE";
 # };
 #
diff --git a/zephyr/dts/bindings/keyboard/cros-ec,kblight-pwm.yaml b/zephyr/dts/bindings/keyboard/cros-ec,kblight-pwm.yaml
index 33607729cd..9cf862a555 100644
--- a/zephyr/dts/bindings/keyboard/cros-ec,kblight-pwm.yaml
+++ b/zephyr/dts/bindings/keyboard/cros-ec,kblight-pwm.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -14,11 +14,6 @@ properties:
     required: true
     description: PWM controlling the Keyboard backlight level.
 
-  frequency:
-    type: int
-    required: true
-    description: PWM frequency in Hz.
-
   generic-pwm-channel:
     type: int
     required: false
diff --git a/zephyr/dts/bindings/keyboard/cros-keyscan.yaml b/zephyr/dts/bindings/keyboard/cros-keyscan.yaml
index 11caf7fd11..a2ec2afc46 100644
--- a/zephyr/dts/bindings/keyboard/cros-keyscan.yaml
+++ b/zephyr/dts/bindings/keyboard/cros-keyscan.yaml
@@ -1,4 +1,4 @@
- # Copyright 2021 The Chromium OS Authors. All rights reserved.
+ # Copyright 2021 The ChromiumOS Authors
  # Use of this source code is governed by a BSD-style license that can be
  # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/led/cros-ec,pwm-leds.yaml b/zephyr/dts/bindings/led/cros-ec,pwm-leds.yaml
index f854f84d50..1d94ec1b6f 100644
--- a/zephyr/dts/bindings/led/cros-ec,pwm-leds.yaml
+++ b/zephyr/dts/bindings/led/cros-ec,pwm-leds.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -41,7 +41,7 @@ properties:
         pwmleds {
                 compatible = "pwm-leds";
                 pwm_sidesel: pwm_sidesel {
-                        pwms = <&pwm7 0 PWM_HZ(4800) PWM_POLARITY_INVERTED>;
+                        pwms = <&pwm7 0 PWM_HZ(2400) PWM_POLARITY_INVERTED>;
                 };
         };
         cros-pwmleds {
@@ -49,13 +49,6 @@ properties:
                 sidesel = <&pwm_sidesel>;
         };
 
-  frequency:
-    type: int
-    required: true
-    description: |
-      PWM frequency in Hz for LEDs. SIDESEL, if present, uses half the
-      frequency.
-
   color-map-red:
     type: array
     required: false
diff --git a/zephyr/dts/bindings/led/maxim,seven-seg-display.yaml b/zephyr/dts/bindings/led/maxim,seven-seg-display.yaml
index 9307edad34..d66a0cdca2 100644
--- a/zephyr/dts/bindings/led/maxim,seven-seg-display.yaml
+++ b/zephyr/dts/bindings/led/maxim,seven-seg-display.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/leds/cros-ec,gpio-led-pins.yaml b/zephyr/dts/bindings/leds/cros-ec,gpio-led-pins.yaml
index 53688a8172..2e5fe7cff0 100644
--- a/zephyr/dts/bindings/leds/cros-ec,gpio-led-pins.yaml
+++ b/zephyr/dts/bindings/leds/cros-ec,gpio-led-pins.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -7,20 +7,24 @@ description: GPIO LED pins parent node
 compatible: "cros-ec,gpio-led-pins"
 
 child-binding:
-    description: Each child node describes all the GPIO pins that need to be
-                 altered to set a specific color. Eg. for a board supporting
-                 Blue and Amber LEDs - to set LED_AMBER color, amber LED will
-                 need to be set to 1 and blue LED to 0. So a node looks like
-                 color-amber {
-                              led-color = "LED_AMBER";
-                              led-pins = <&gpio_ec_chg_led_y_c1 1>,
-                                         <&gpio_ec_chg_led_b_c1 0>;
-                             };
+    description: |
+      Each child node describes all the GPIO pins that need to be altered to set
+      a specific color.
+      e.g. For a board supporting Blue and Amber LEDs - to set LED_AMBER color,
+      amber LED will need to be set to 1 and blue LED to 0. 1 always turns on
+      the LED and 0 always turns off the LED. So a node looks like
+      color-amber {
+                   led-color = "LED_AMBER";
+                   led-pins = <&gpio_ec_chg_led_y_c1 1>,
+                              <&gpio_ec_chg_led_b_c1 0>;
+                  };
     properties:
         led-color:
             type: string
             required: true
-            description: Used to link the color nodes with the pin nodes
+            description: |
+              This property is used to identify pin nodes based on color enum.
+              It is required by the EC_CMD_LED_CONTROL host command.
             enum:
                 - LED_OFF
                 - LED_RED
@@ -32,10 +36,9 @@ child-binding:
         led-id:
             type: string
             required: true
-            description: Used to link the color nodes with the pin nodes in
-                         case of multiple LEDs. Also required by ectool to
-                         identify led-ids supported. It needs to match the
-                         enum names defined in ec_commands.h
+            description: |
+              This property is required by the EC_CMD_LED_CONTROL host command.
+              It must match the enum names defined in ec_commands.h.
             enum:
                 - EC_LED_ID_BATTERY_LED
                 - EC_LED_ID_POWER_LED
@@ -47,8 +50,9 @@ child-binding:
         br-color:
             type: string
             required: false
-            description: This is used in the ectool brightness range APIs.
-                         It needs to match the enum names defined in ec_commands.h
+            description: |
+              This is used in the ectool brightness range APIs. It must match
+              the enum names defined in ec_commands.h.
             enum:
                 - EC_LED_COLOR_RED
                 - EC_LED_COLOR_GREEN
@@ -58,4 +62,9 @@ child-binding:
                 - EC_LED_COLOR_AMBER
         led-pins:
             type: phandle-array
-            required: false
+            required: true
+            description: |
+              This property is used to specify an array of gpio pins and
+              corresponding values to enable a particular color.
+              e.g. Amber color - led-pins = <&gpio_ec_chg_led_y_c1 1>,
+                                            <&gpio_ec_chg_led_b_c1 0>;
diff --git a/zephyr/dts/bindings/leds/cros-ec,led-colors.yaml b/zephyr/dts/bindings/leds/cros-ec,led-colors.yaml
deleted file mode 100644
index cd10ca9a60..0000000000
--- a/zephyr/dts/bindings/leds/cros-ec,led-colors.yaml
+++ /dev/null
@@ -1,94 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: LED colors parent node
-
-compatible: "cros-ec,led-colors"
-
-child-binding:
-    description: LED Color nodes to describe the policy combination a node
-                 depends on, and the color to set to for that combination.
-                 e.g. If Blue color needs to be set for charge state discharge
-                 in S0, a node looks like
-                 power-state-discharge-s0 {
-                    charge-state = "PWR_STATE_DISCHARGE";
-                    chipset-state = "POWER_S0";
-                    color-0 {
-                      led-color = "LED_BLUE";
-                    };
-                 };
-
-    properties:
-        charge-state:
-            description: If the LED color depends on charge state, this
-                         property is used to describe it.
-            type: string
-            required: false
-            enum:
-                - PWR_STATE_CHARGE
-                - PWR_STATE_DISCHARGE
-                - PWR_STATE_ERROR
-                - PWR_STATE_IDLE
-                - PWR_STATE_CHARGE_NEAR_FULL
-
-        charge-port:
-            description: If the LED color depends on the charging port (left or right)
-            type: int
-            required: false
-
-        chipset-state:
-            description: If the LED color depends on chipset state, this
-                         property is used to describe it.
-            type: string
-            required: false
-            enum:
-                - POWER_S0
-                - POWER_S3
-                - POWER_S5
-
-        batt-lvl:
-            description: If the LED color depends on current battery level, this property
-                         is used to describe the batt_lvl range using closed interval [x,y].
-                         Use the macros defined in dt-bindings/battery.h.
-                         e.g. <BATTERY_LEVEL_EMPTY BATTERY_LEVEL_LOW> describes battery level
-                         range of BATTERY_LEVEL_EMPTY to BATTERY_LEVEL_LOW inclusive.
-            type: array
-            required: false
-
-        extra-flag:
-            description: If the LED color depends on additional factors
-            type: string
-            required: false
-            enum:
-                - NONE
-                - LED_CHFLAG_FORCE_IDLE
-                - LED_CHFLAG_DEFAULT
-
-    child-binding:
-        description: Color enum
-        properties:
-            led-color:
-                description: Handle to LED pins node that describes pins to set
-                             to enable a particular color
-                type: phandle
-                required: true
-            period-ms:
-                description: In case of blinking LEDs, amount of time in msecs
-                             the LED color is active. This value must be a
-                             multiple of HOOK_TICK_INTERVAL_MS
-                             e.g.
-                             power-state-error {
-                                charge-state = "PWR_STATE_ERROR";
-                                /* One sec Amber, one sec Off */
-                                color-0 {
-                                  led-color = "LED_AMBER";
-                                  period-ms = <1000>;
-                                };
-                                color-1 {
-                                  led-color = "LED_OFF";
-                                  period-ms = <1000>;
-                                };
-                             };
-                type: int
-                required: false
diff --git a/zephyr/dts/bindings/leds/cros-ec,led-policy.yaml b/zephyr/dts/bindings/leds/cros-ec,led-policy.yaml
new file mode 100644
index 0000000000..7bdcbd863e
--- /dev/null
+++ b/zephyr/dts/bindings/leds/cros-ec,led-policy.yaml
@@ -0,0 +1,102 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: LED policy parent node
+
+compatible: "cros-ec,led-policy"
+
+child-binding:
+    description: |
+      LED policy nodes to describe the policy combination a node depends on, and
+      the color to set to for that combination.
+      e.g. If Blue color needs to be set for charge state discharge in S0, a
+      node looks like
+      power-state-discharge-s0 {
+         charge-state = "PWR_STATE_DISCHARGE";
+         chipset-state = "POWER_S0";
+         charge-port = <0>;
+         color-0 {
+           led-color = <&color_blue>;
+         };
+      };
+
+    properties:
+        charge-state:
+            description: |
+              If the LED color depends on charge state, this property is used
+              to describe it.
+              PWR_STATE_CHARGE - AC is connected, battery is charging.
+              PWR_STATE_DISCHARGE - AC is not connected, battery is discharging.
+              PWR_STATE_ERROR - Battery is in error state.
+              PWR_STATE_IDLE - AC is connected, battery is not charging.
+              PWR_STATE_FORCED_IDLE - AC is connected, battery is not charging.
+                                      Used during factory testing.
+              PWR_STATE_CHARGE_NEAR_FULL - AC is connected, battery is charging
+                                           and close to fully charged.
+            type: string
+            required: false
+            enum:
+                - PWR_STATE_CHARGE
+                - PWR_STATE_DISCHARGE
+                - PWR_STATE_ERROR
+                - PWR_STATE_IDLE
+                - PWR_STATE_FORCED_IDLE
+                - PWR_STATE_CHARGE_NEAR_FULL
+
+        charge-port:
+            description: |
+              If the LED color depends on the charging port (left or right).
+            type: int
+            required: false
+
+        chipset-state:
+            description: |
+              If the LED color depends on chipset state, this property is used
+              to describe it.
+            type: string
+            required: false
+            enum:
+                - POWER_S0
+                - POWER_S3
+                - POWER_S5
+
+        batt-lvl:
+            description: |
+              If the LED color depends on current battery level, this property
+              is used to describe batt_lvl range using closed interval [x,y].
+              Use the macros defined in dt-bindings/battery.h.
+              e.g. <BATTERY_LEVEL_EMPTY BATTERY_LEVEL_LOW> describes battery level
+                   range of BATTERY_LEVEL_EMPTY to BATTERY_LEVEL_LOW inclusive.
+            type: array
+            required: false
+
+    child-binding:
+        description: Color enum
+        properties:
+            led-color:
+                description: |
+                  Handle to LED pins node that describes pins to set to enable a
+                  particular color.
+                type: phandle
+                required: true
+            period-ms:
+                description: |
+                  In case of blinking LEDs, amount of time in msecs the LED
+                  color is active. This value must be a multiple of
+                  HOOK_TICK_INTERVAL_MS.
+                  e.g.
+                  power-state-error {
+                     charge-state = "PWR_STATE_ERROR";
+                     /* One sec Amber, one sec Off */
+                     color-0 {
+                       led-color = <&color_amber>;
+                       period-ms = <1000>;
+                     };
+                     color-1 {
+                       led-color = <&color_off>;
+                       period-ms = <1000>;
+                     };
+                  };
+                type: int
+                required: false
diff --git a/zephyr/dts/bindings/leds/cros-ec,pwm-led-pins.yaml b/zephyr/dts/bindings/leds/cros-ec,pwm-led-pins.yaml
index dcd06d7b96..19fee69be4 100644
--- a/zephyr/dts/bindings/leds/cros-ec,pwm-led-pins.yaml
+++ b/zephyr/dts/bindings/leds/cros-ec,pwm-led-pins.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -6,27 +6,24 @@ description: PWM LED pins parent node
 
 compatible: "cros-ec,pwm-led-pins"
 
-properties:
-  pwm-frequency:
-    type: int
-    required: true
-    description: PWM frequency in Hz.
-
 child-binding:
-    description: Each child node describes all the PWM pins that need to be
-                 altered to set a specific color. Eg. For blue and amber PWM
-                 channels, in order to set color amber, a node looks like
-                 this where 100 is PWM duty cycle in percentage
-                 color-amber {
-                              led-color = "LED_AMBER";
-                              led-pins = <&pwm_led_y 100>,
-                                         <&pwm_led_b 0>;
-                             };
+    description: |
+      Each child node describes all the PWM pins that need to be altered to set
+      a specific color.
+      e.g. For blue and amber PWM channels, in order to set color amber, a node
+      looks like this where 100 is PWM duty cycle in percentage.
+      color-amber {
+                   led-color = "LED_AMBER";
+                   led-pins = <&pwm_led_y 100>,
+                              <&pwm_led_b 0>;
+                  };
     properties:
         led-color:
             type: string
             required: true
-            description: Used to link the color nodes with the pin nodes
+            description: |
+              This property is used to identify pin nodes based on color enum.
+              It is required by the EC_CMD_LED_CONTROL host command.
             enum:
                 - LED_OFF
                 - LED_RED
@@ -38,10 +35,9 @@ child-binding:
         led-id:
             type: string
             required: true
-            description: Used to link the color nodes with the pin nodes in
-                         case of multiple LEDs. Also required by ectool to
-                         identify led-ids supported. It needs to match the
-                         enum names defined in ec_commands.h
+            description: |
+              This property is required by the EC_CMD_LED_CONTROL host command.
+              It must match the enum names defined in ec_commands.h.
             enum:
                 - EC_LED_ID_BATTERY_LED
                 - EC_LED_ID_POWER_LED
@@ -53,8 +49,9 @@ child-binding:
         br-color:
             type: string
             required: false
-            description: This is used in the ectool brightness range APIs.
-                         It needs to match the enum names defined in ec_commands.h
+            description: |
+              This is used in the ectool brightness range APIs. It must match
+              the enum names defined in ec_commands.h.
             enum:
                 - EC_LED_COLOR_RED
                 - EC_LED_COLOR_GREEN
@@ -64,4 +61,9 @@ child-binding:
                 - EC_LED_COLOR_AMBER
         led-pins:
             type: phandle-array
-            required: false
+            required: true
+            description: |
+              This property is used to specify an array of PWM pins and
+              corresponding values to enable a particular color.
+              e.g. Amber color - led-pins = <&pwm_led_y 100>,
+                                            <&pwm_led_b 0>;
diff --git a/zephyr/dts/bindings/leds/cros-ec,pwm-led-pin-config.yaml b/zephyr/dts/bindings/leds/cros-ec,pwm-pin-config.yaml
index 0813847bba..bdef6b6144 100644
--- a/zephyr/dts/bindings/leds/cros-ec,pwm-led-pin-config.yaml
+++ b/zephyr/dts/bindings/leds/cros-ec,pwm-pin-config.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/motionsense/cros-ec,motionsense-mutex.yaml b/zephyr/dts/bindings/motionsense/cros-ec,motionsense-mutex.yaml
index c988af258d..17c60744c8 100644
--- a/zephyr/dts/bindings/motionsense/cros-ec,motionsense-mutex.yaml
+++ b/zephyr/dts/bindings/motionsense/cros-ec,motionsense-mutex.yaml
@@ -1,4 +1,4 @@
-# Copyright (c) 2021 The Chromium OS Authors
+# Copyright 2021 The ChromiumOS Authors
 # SPDX-License-Identifier: Apache-2.0
 
 description: Motion sense mutex parent node
@@ -9,14 +9,6 @@ child-binding:
   description: A mutex node is used to create an instance of mutex_t.
                A mutex node is referenced by one or more sensor nodes in
                "/motionsense-sensors" node.
-  properties:
-    label:
-      required: true
-      type: string
-      description: Human readable string describing the mutex.
-                   This is a brief explanation about the mutex.
-                   The property is not actually used in code.
-
 
 #
 # examples:
@@ -24,11 +16,9 @@ child-binding:
 # motionsense-mutex {
 #         compatible = "cros-ec,motionsense-mutex";
 #         mutex_bma255: bma255-mutex {
-#                 label = "BMA255_MUTEX";
 #         };
 #
 #         mutex_bmi260: bmi260-mutex {
-#                 label = "BMI260_MUTEX";
 #         };
 # };
 #
diff --git a/zephyr/dts/bindings/motionsense/cros-ec,motionsense-rotation-ref.yaml b/zephyr/dts/bindings/motionsense/cros-ec,motionsense-rotation-ref.yaml
index 7de86ec8db..da2b99e928 100644
--- a/zephyr/dts/bindings/motionsense/cros-ec,motionsense-rotation-ref.yaml
+++ b/zephyr/dts/bindings/motionsense/cros-ec,motionsense-rotation-ref.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/motionsense/cros-ec,motionsense-sensor-config.yaml b/zephyr/dts/bindings/motionsense/cros-ec,motionsense-sensor-config.yaml
index 68cdd15637..cb0fd96d95 100644
--- a/zephyr/dts/bindings/motionsense/cros-ec,motionsense-sensor-config.yaml
+++ b/zephyr/dts/bindings/motionsense/cros-ec,motionsense-sensor-config.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -26,17 +26,10 @@ child-binding:
     and it is used to indicate one of the 4 configurations.
     For example, node name ec-s0 is for SENSOR_CONFIG_EC_S0.
     ec-s0 {
-       label = "SENSOR_CONFIG_EC_S0";
        odr = <1000>;
        ec_rate = <1000>;
     };
   properties:
-    label:
-      type: string
-      required: false
-      description: |
-        Human-readable string describing the config.
-        see the example the above.
     odr:
       type: int
       required: false
@@ -55,11 +48,9 @@ child-binding:
 #         compatible =
 #                 "cros-ec,motionsense-sensor-config";
 #         ec-s0 {
-#                 label = "SENSOR_CONFIG_EC_S0";
 #                 odr = <(10000 | ROUND_UP_FLAG)>;
 #         };
 #         ec-s3 {
-#                 label = "SENSOR_CONFIG_EC_S3";
 #                 odr = <(10000 | ROUND_UP_FLAG)>;
 #         };
 # };
diff --git a/zephyr/dts/bindings/motionsense/cros-ec,motionsense-sensor-info.yaml b/zephyr/dts/bindings/motionsense/cros-ec,motionsense-sensor-info.yaml
index 2f508777e1..b0e960e559 100644
--- a/zephyr/dts/bindings/motionsense/cros-ec,motionsense-sensor-info.yaml
+++ b/zephyr/dts/bindings/motionsense/cros-ec,motionsense-sensor-info.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/motionsense/driver/bmi160.yaml b/zephyr/dts/bindings/motionsense/driver/bmi160.yaml
index 6ca096d87a..e2c4bd6ac7 100644
--- a/zephyr/dts/bindings/motionsense/driver/bmi160.yaml
+++ b/zephyr/dts/bindings/motionsense/driver/bmi160.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/motionsense/driver/bmi260.yaml b/zephyr/dts/bindings/motionsense/driver/bmi260.yaml
index f308472ec3..33fd4356b8 100644
--- a/zephyr/dts/bindings/motionsense/driver/bmi260.yaml
+++ b/zephyr/dts/bindings/motionsense/driver/bmi260.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/motionsense/driver/bmi3xx.yaml b/zephyr/dts/bindings/motionsense/driver/bmi3xx.yaml
index bd99738afe..e9e603fc96 100644
--- a/zephyr/dts/bindings/motionsense/driver/bmi3xx.yaml
+++ b/zephyr/dts/bindings/motionsense/driver/bmi3xx.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,bma255.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,bma255.yaml
index cbd9e82f2d..12a5be2d44 100644
--- a/zephyr/dts/bindings/motionsense/driver/cros-ec,bma255.yaml
+++ b/zephyr/dts/bindings/motionsense/driver/cros-ec,bma255.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,bma4xx.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,bma4xx.yaml
index 6c912c96d4..b17b372af1 100644
--- a/zephyr/dts/bindings/motionsense/driver/cros-ec,bma4xx.yaml
+++ b/zephyr/dts/bindings/motionsense/driver/cros-ec,bma4xx.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi160-accel.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi160-accel.yaml
index 4eabf12cd5..cb574c6c0c 100644
--- a/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi160-accel.yaml
+++ b/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi160-accel.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi160-gyro.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi160-gyro.yaml
index b7a0b38290..8064549e4a 100644
--- a/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi160-gyro.yaml
+++ b/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi160-gyro.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi260-accel.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi260-accel.yaml
index 130600cca2..d18feaa813 100644
--- a/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi260-accel.yaml
+++ b/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi260-accel.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi260-gyro.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi260-gyro.yaml
index 00226d0304..29e87e89ee 100644
--- a/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi260-gyro.yaml
+++ b/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi260-gyro.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi3xx-accel.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi3xx-accel.yaml
index 24d28645ee..7d0f077226 100644
--- a/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi3xx-accel.yaml
+++ b/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi3xx-accel.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi3xx-gyro.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi3xx-gyro.yaml
index e8792492ef..0085dc5648 100644
--- a/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi3xx-gyro.yaml
+++ b/zephyr/dts/bindings/motionsense/driver/cros-ec,bmi3xx-gyro.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,icm42607-accel.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,icm42607-accel.yaml
index ba7fbb3878..7812870aee 100644
--- a/zephyr/dts/bindings/motionsense/driver/cros-ec,icm42607-accel.yaml
+++ b/zephyr/dts/bindings/motionsense/driver/cros-ec,icm42607-accel.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,icm42607-gyro.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,icm42607-gyro.yaml
index 4707f33d6d..fb4739242f 100644
--- a/zephyr/dts/bindings/motionsense/driver/cros-ec,icm42607-gyro.yaml
+++ b/zephyr/dts/bindings/motionsense/driver/cros-ec,icm42607-gyro.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,icm426xx-accel.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,icm426xx-accel.yaml
index fbc9f44051..d41275cdd8 100644
--- a/zephyr/dts/bindings/motionsense/driver/cros-ec,icm426xx-accel.yaml
+++ b/zephyr/dts/bindings/motionsense/driver/cros-ec,icm426xx-accel.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,icm426xx-gyro.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,icm426xx-gyro.yaml
index 1f0ae26ced..bcad871fc7 100644
--- a/zephyr/dts/bindings/motionsense/driver/cros-ec,icm426xx-gyro.yaml
+++ b/zephyr/dts/bindings/motionsense/driver/cros-ec,icm426xx-gyro.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,kx022.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,kx022.yaml
index 8aecc32077..e66988502a 100644
--- a/zephyr/dts/bindings/motionsense/driver/cros-ec,kx022.yaml
+++ b/zephyr/dts/bindings/motionsense/driver/cros-ec,kx022.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,lis2dw12.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,lis2dw12.yaml
index bacf8f2c75..9dd07a7b78 100644
--- a/zephyr/dts/bindings/motionsense/driver/cros-ec,lis2dw12.yaml
+++ b/zephyr/dts/bindings/motionsense/driver/cros-ec,lis2dw12.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,lsm6dsm-accel.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,lsm6dsm-accel.yaml
new file mode 100644
index 0000000000..25bd059906
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/driver/cros-ec,lsm6dsm-accel.yaml
@@ -0,0 +1,13 @@
+# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: motionsense sensor node for LSM6DSM Accelerometer
+
+compatible: "cros-ec,lsm6dsm-accel"
+
+include: lsm6dsm.yaml
+
+properties:
+  default-range:
+    default: 4
diff --git a/zephyr/test/ap_power/BUILD.py b/zephyr/dts/bindings/motionsense/driver/cros-ec,lsm6dsm-gyro.yaml
index e3dac8c77e..737f3a5105 100644
--- a/zephyr/test/ap_power/BUILD.py
+++ b/zephyr/dts/bindings/motionsense/driver/cros-ec,lsm6dsm-gyro.yaml
@@ -2,6 +2,12 @@
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
-"""Register zmake project for ap_power test."""
+description: motionsense sensor node for LSM6DSM Gyro
 
-register_host_test("ap_power", dts_overlays=["overlay.dts"])
+compatible: "cros-ec,lsm6dsm-gyro"
+
+include: lsm6dsm.yaml
+
+properties:
+  default-range:
+    default: 1000
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,lsm6dso-accel.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,lsm6dso-accel.yaml
index 5c3c6172f0..044c187c50 100644
--- a/zephyr/dts/bindings/motionsense/driver/cros-ec,lsm6dso-accel.yaml
+++ b/zephyr/dts/bindings/motionsense/driver/cros-ec,lsm6dso-accel.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,lsm6dso-gyro.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,lsm6dso-gyro.yaml
index a10a98d97f..1a946eab98 100644
--- a/zephyr/dts/bindings/motionsense/driver/cros-ec,lsm6dso-gyro.yaml
+++ b/zephyr/dts/bindings/motionsense/driver/cros-ec,lsm6dso-gyro.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,tcs3400-clear.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,tcs3400-clear.yaml
index 323286c462..05033de35e 100644
--- a/zephyr/dts/bindings/motionsense/driver/cros-ec,tcs3400-clear.yaml
+++ b/zephyr/dts/bindings/motionsense/driver/cros-ec,tcs3400-clear.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/motionsense/driver/cros-ec,tcs3400-rgb.yaml b/zephyr/dts/bindings/motionsense/driver/cros-ec,tcs3400-rgb.yaml
index e2987cf44b..903574a7f3 100644
--- a/zephyr/dts/bindings/motionsense/driver/cros-ec,tcs3400-rgb.yaml
+++ b/zephyr/dts/bindings/motionsense/driver/cros-ec,tcs3400-rgb.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/motionsense/driver/icm42607.yaml b/zephyr/dts/bindings/motionsense/driver/icm42607.yaml
index f47e7a2f97..4052f12fd9 100644
--- a/zephyr/dts/bindings/motionsense/driver/icm42607.yaml
+++ b/zephyr/dts/bindings/motionsense/driver/icm42607.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/motionsense/driver/icm426xx.yaml b/zephyr/dts/bindings/motionsense/driver/icm426xx.yaml
index 5c33931706..7f5e8e164c 100644
--- a/zephyr/dts/bindings/motionsense/driver/icm426xx.yaml
+++ b/zephyr/dts/bindings/motionsense/driver/icm426xx.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/motionsense/driver/lsm6dsm.yaml b/zephyr/dts/bindings/motionsense/driver/lsm6dsm.yaml
new file mode 100644
index 0000000000..efd71fe181
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/driver/lsm6dsm.yaml
@@ -0,0 +1,19 @@
+# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# common fields for both LSM6DSM accel and gyro
+
+# every motionsense sensor node should include motionsense-sensor-base.yaml
+include: motionsense-sensor-base.yaml
+
+properties:
+  i2c-spi-addr-flags:
+    type: string
+    description: i2c address or SPI peripheral logic GPIO
+    # Address is b'0110101x' where x is determined by the
+    # logic level on SA0
+    enum:
+      - "LSM6DSM_ADDR0_FLAGS"
+      - "LSM6DSM_ADDR1_FLAGS"
+    default: "LSM6DSM_ADDR0_FLAGS"
diff --git a/zephyr/dts/bindings/motionsense/driver/lsm6dso.yaml b/zephyr/dts/bindings/motionsense/driver/lsm6dso.yaml
index dd345854be..565c64b1c8 100644
--- a/zephyr/dts/bindings/motionsense/driver/lsm6dso.yaml
+++ b/zephyr/dts/bindings/motionsense/driver/lsm6dso.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
diff --git a/zephyr/dts/bindings/motionsense/driver/tcs3400.yaml b/zephyr/dts/bindings/motionsense/driver/tcs3400.yaml
index ecad7ec1a7..1c2fbeccbc 100644
--- a/zephyr/dts/bindings/motionsense/driver/tcs3400.yaml
+++ b/zephyr/dts/bindings/motionsense/driver/tcs3400.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,accelgyro-als-channel-scale.yaml b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,accelgyro-als-channel-scale.yaml
index 753edc7ea8..39f92c7a50 100644
--- a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,accelgyro-als-channel-scale.yaml
+++ b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,accelgyro-als-channel-scale.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -6,7 +6,7 @@ description: |
   Bindings for als_channel_scale_t in accelgyro.h.
   Each channel has scaling factor for normalization & cover
 
-compatible: cros-ec,accelgyro-als-channel-scale
+compatible: "cros-ec,accelgyro-als-channel-scale"
 
 properties:
   k-channel-scale:
diff --git a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,accelgyro-als-drv-data.yaml b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,accelgyro-als-drv-data.yaml
index 7d64689cf2..13a64bafb0 100644
--- a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,accelgyro-als-drv-data.yaml
+++ b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,accelgyro-als-drv-data.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,accelgyro-rgb-calibration.yaml b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,accelgyro-rgb-calibration.yaml
index 4204a63cff..e0ef479ffd 100644
--- a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,accelgyro-rgb-calibration.yaml
+++ b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,accelgyro-rgb-calibration.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bma255.yaml b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bma255.yaml
index 4cabd620da..8749d96de6 100644
--- a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bma255.yaml
+++ b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bma255.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bma4xx.yaml b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bma4xx.yaml
index 2f00d771b3..5504b3642c 100644
--- a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bma4xx.yaml
+++ b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bma4xx.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bmi160.yaml b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bmi160.yaml
index 52f5c346fc..c4aea99ea1 100644
--- a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bmi160.yaml
+++ b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bmi160.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bmi260.yaml b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bmi260.yaml
index 4d414121d1..a6247c6cd4 100644
--- a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bmi260.yaml
+++ b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bmi260.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bmi3xx.yaml b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bmi3xx.yaml
index d3fa8cc009..5ca2059b3d 100644
--- a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bmi3xx.yaml
+++ b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-bmi3xx.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-icm426xx.yaml b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-icm426xx.yaml
index b88ad7eacd..04ba419d69 100644
--- a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-icm426xx.yaml
+++ b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-icm426xx.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-kionix.yaml b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-kionix.yaml
index 3151412b79..0f86616ae2 100644
--- a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-kionix.yaml
+++ b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-kionix.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-lis2dw12.yaml b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-lis2dw12.yaml
index ecb182a4fd..25f47c7e96 100644
--- a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-lis2dw12.yaml
+++ b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-lis2dw12.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-lsm6dsm.yaml b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-lsm6dsm.yaml
new file mode 100644
index 0000000000..66e6f32f60
--- /dev/null
+++ b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-lsm6dsm.yaml
@@ -0,0 +1,21 @@
+# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: LSM6DSM driver data node. Note this has to be
+  a separate instance for each sensor instance for this device
+  e.g if the device is used for both accel and gyro, then
+  separate instances of this driver data node must be used for each.
+
+compatible: "cros-ec,drvdata-lsm6dsm"
+
+include: drvdata-base.yaml
+
+#
+# examples:
+#
+# lsm6dsm_data: lsm6dsm-drv-data {
+#       compatible = "cros-ec,drvdata-lsm6dsm";
+#       status = "okay";
+# };
+#
diff --git a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-lsm6dso.yaml b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-lsm6dso.yaml
index d3a37da9a1..57f2eedf01 100644
--- a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-lsm6dso.yaml
+++ b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-lsm6dso.yaml
@@ -1,8 +1,11 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
-description: LSM6DSO driver data node
+description: LSM6DSO driver data node. Note this has to be
+  a separate instance for each sensor instance for this device
+  e.g if the device is used for both accel and gyro, then
+  separate instances of this driver data node must be used for each.
 
 compatible: "cros-ec,drvdata-lsm6dso"
 
diff --git a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-tcs3400-clear.yaml b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-tcs3400-clear.yaml
index c1059d40be..6b234d4460 100644
--- a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-tcs3400-clear.yaml
+++ b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-tcs3400-clear.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-tcs3400-rgb.yaml b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-tcs3400-rgb.yaml
index 7ae7bc5983..b81a4d6d49 100644
--- a/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-tcs3400-rgb.yaml
+++ b/zephyr/dts/bindings/motionsense/drvdata/cros-ec,drvdata-tcs3400-rgb.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/motionsense/drvdata/drvdata-base.yaml b/zephyr/dts/bindings/motionsense/drvdata/drvdata-base.yaml
index dc32d69d21..b278f26ba3 100644
--- a/zephyr/dts/bindings/motionsense/drvdata/drvdata-base.yaml
+++ b/zephyr/dts/bindings/motionsense/drvdata/drvdata-base.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/motionsense/motionsense-sensor-base.yaml b/zephyr/dts/bindings/motionsense/motionsense-sensor-base.yaml
index 9e4aa8e3f7..c5ef4ba192 100644
--- a/zephyr/dts/bindings/motionsense/motionsense-sensor-base.yaml
+++ b/zephyr/dts/bindings/motionsense/motionsense-sensor-base.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -9,13 +9,6 @@ include: base.yaml
 properties:
   status:
     required: true
-  label:
-    type: string
-    required: true
-    description: |
-        Human readable string describing the motion sensor.
-        This is used as the name of the motion sensor.
-        e.g) label = "Lid Accel";
   active-mask:
     type: string
     description: indicates system power state for sensor to be active
@@ -53,7 +46,10 @@ properties:
   drv-data:
     type: phandle
     required: false
-    description: phandle to driver data to be used for the motion sensor
+    description: phandle to driver data to be used for the motion sensor.
+      Some drivers require this to be a global shared datas structure
+      used by all instances of this device, others require separate
+      data structures for each instance.
   alternate-for:
     type: phandle
     description: phandle to another sensor that can be swapped with this one
@@ -73,7 +69,6 @@ properties:
 #           compatible = "cros-ec,bma255";
 #           status = "okay";
 #
-#           label = "Lid Accel";
 #           active-mask = "SENSOR_ACTIVE_S0_S3";
 #           location = "MOTIONSENSE_LOC_LID";
 #           mutex = <&mutex_bma255>;
diff --git a/zephyr/dts/bindings/pmic/mps,mp2964.yaml b/zephyr/dts/bindings/pmic/mps,mp2964.yaml
index db35aa07b2..57017992a7 100644
--- a/zephyr/dts/bindings/pmic/mps,mp2964.yaml
+++ b/zephyr/dts/bindings/pmic/mps,mp2964.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/power/intel,ap-pwr-signal-base.yaml b/zephyr/dts/bindings/power/intel,ap-pwr-signal-base.yaml
index 256320f85b..375d51227d 100644
--- a/zephyr/dts/bindings/power/intel,ap-pwr-signal-base.yaml
+++ b/zephyr/dts/bindings/power/intel,ap-pwr-signal-base.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/power/intel,ap-pwrseq-adc.yaml b/zephyr/dts/bindings/power/intel,ap-pwrseq-adc.yaml
index c3a267a19a..3dd6fabf1c 100644
--- a/zephyr/dts/bindings/power/intel,ap-pwrseq-adc.yaml
+++ b/zephyr/dts/bindings/power/intel,ap-pwrseq-adc.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/power/intel,ap-pwrseq-external.yaml b/zephyr/dts/bindings/power/intel,ap-pwrseq-external.yaml
index 2aaf05bf23..e0258b0f7c 100644
--- a/zephyr/dts/bindings/power/intel,ap-pwrseq-external.yaml
+++ b/zephyr/dts/bindings/power/intel,ap-pwrseq-external.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/power/intel,ap-pwrseq-gpio.yaml b/zephyr/dts/bindings/power/intel,ap-pwrseq-gpio.yaml
index bd550eff5e..c72b36f5d2 100644
--- a/zephyr/dts/bindings/power/intel,ap-pwrseq-gpio.yaml
+++ b/zephyr/dts/bindings/power/intel,ap-pwrseq-gpio.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/power/intel,ap-pwrseq-vw.yaml b/zephyr/dts/bindings/power/intel,ap-pwrseq-vw.yaml
index 12b310e383..606dd6c2b4 100644
--- a/zephyr/dts/bindings/power/intel,ap-pwrseq-vw.yaml
+++ b/zephyr/dts/bindings/power/intel,ap-pwrseq-vw.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/power/intel,ap-pwrseq.yaml b/zephyr/dts/bindings/power/intel,ap-pwrseq.yaml
index 64c1fc7d30..b0a0426435 100644
--- a/zephyr/dts/bindings/power/intel,ap-pwrseq.yaml
+++ b/zephyr/dts/bindings/power/intel,ap-pwrseq.yaml
@@ -1,4 +1,4 @@
- # Copyright 2022 The Chromium OS Authors. All rights reserved.
+ # Copyright 2022 The ChromiumOS Authors
  # Use of this source code is governed by a BSD-style license that can be
  # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/switchcap/switchcap-gpio.yaml b/zephyr/dts/bindings/switchcap/switchcap-gpio.yaml
index 5d1a25bf94..0016401835 100644
--- a/zephyr/dts/bindings/switchcap/switchcap-gpio.yaml
+++ b/zephyr/dts/bindings/switchcap/switchcap-gpio.yaml
@@ -14,3 +14,9 @@ properties:
     required: false
     description: |
       GPIO used to read if power is good
+
+  poff-delay-ms:
+    type: int
+    required: false
+    description: |
+      Additional power off delay required for some systems
diff --git a/zephyr/dts/bindings/temp/amd,sb-tsi.yaml b/zephyr/dts/bindings/temp/amd,sb-tsi.yaml
new file mode 100644
index 0000000000..f99c01081a
--- /dev/null
+++ b/zephyr/dts/bindings/temp/amd,sb-tsi.yaml
@@ -0,0 +1,10 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: >
+  Properties for an Side Band Temperature Sensor Interface sensor
+
+compatible: "amd,sb-tsi"
+
+include: i2c-device.yaml
diff --git a/zephyr/dts/bindings/temp/cros_ec_temp_sensor_thermistor.yaml b/zephyr/dts/bindings/temp/cros-ec,temp-sensor-thermistor.yaml
index 34acbebcae..958dbd79e9 100644
--- a/zephyr/dts/bindings/temp/cros_ec_temp_sensor_thermistor.yaml
+++ b/zephyr/dts/bindings/temp/cros-ec,temp-sensor-thermistor.yaml
@@ -1,13 +1,11 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 description: >
   Properties for a thermistor temperature sensor
 
-include: cros_ec_temp_sensor.yaml
-
-compatible: cros-ec,temp-sensor-thermistor
+compatible: "cros-ec,temp-sensor-thermistor"
 
 properties:
     adc:
diff --git a/zephyr/dts/bindings/temp/cros-ec,temp-sensor-tmp112.yaml b/zephyr/dts/bindings/temp/cros-ec,temp-sensor-tmp112.yaml
new file mode 100644
index 0000000000..43ab9386c9
--- /dev/null
+++ b/zephyr/dts/bindings/temp/cros-ec,temp-sensor-tmp112.yaml
@@ -0,0 +1,10 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: >
+  Properties for a TMP112 I2C temperature sensor
+
+compatible: "cros-ec,temp-sensor-tmp112"
+
+include: i2c-device.yaml
diff --git a/zephyr/dts/bindings/temp/cros_ec_temp_sensor.yaml b/zephyr/dts/bindings/temp/cros-ec,temp-sensors.yaml
index 393cb1be78..66c5bc955a 100644
--- a/zephyr/dts/bindings/temp/cros_ec_temp_sensor.yaml
+++ b/zephyr/dts/bindings/temp/cros-ec,temp-sensors.yaml
@@ -1,44 +1,22 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 description: >
-  Common properties for temperature sensors
+  Common properties for temperature sensors that are not handled by drivers.
   Zero values in degrees K(-273 in degrees C)in thermal thresholds will
   be ignored
 
-compatible: cros-ec,temp-sensor
+compatible: "cros-ec,temp-sensors"
 
-properties:
-    label:
-      required: true
-      type: string
-      description:
-        Human-readable string describing the device (used as
-        device_get_binding() argument)
-
-    enum-name:
-      type: string
+child-binding:
+  description: Named temperature sensor node
+  properties:
+    sensor:
+      type: phandle
       required: true
       description:
-        Enum values used in the source code to refer to the temperature sensors
-      enum:
-      - TEMP_SENSOR_1
-      - TEMP_SENSOR_2
-      - TEMP_SENSOR_3
-      - TEMP_SENSOR_4
-      - TEMP_SENSOR_AMB
-      - TEMP_SENSOR_CHARGER
-      - TEMP_SENSOR_CPU
-      - TEMP_SENSOR_DDR_SOC
-      - TEMP_SENSOR_FAN
-      - TEMP_SENSOR_MEMORY
-      - TEMP_SENSOR_PP3300_REGULATOR
-      - TEMP_SENSOR_SOC
-      - TEMP_SENSOR_1_DDR_SOC
-      - TEMP_SENSOR_2_AMBIENT
-      - TEMP_SENSOR_3_CHARGER
-      - TEMP_SENSOR_4_WWAN
+        A pointer to a coresponding temperature sensor node.
 
     power-good-pin:
       type: phandle
diff --git a/zephyr/dts/bindings/temp/cros_ec_thermistor.yaml b/zephyr/dts/bindings/temp/cros-ec,thermistor.yaml
index d4bc32ed3c..3121f8a95f 100644
--- a/zephyr/dts/bindings/temp/cros_ec_thermistor.yaml
+++ b/zephyr/dts/bindings/temp/cros-ec,thermistor.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -7,7 +7,7 @@
 
 description: Common properties for thermistors
 
-compatible: cros-ec,thermistor
+compatible: "cros-ec,thermistor"
 
 properties:
   scaling-factor:
diff --git a/zephyr/dts/bindings/temp/cros_ec_temp_sensor_pct2075.yaml b/zephyr/dts/bindings/temp/cros_ec_temp_sensor_pct2075.yaml
deleted file mode 100644
index a85dc1759e..0000000000
--- a/zephyr/dts/bindings/temp/cros_ec_temp_sensor_pct2075.yaml
+++ /dev/null
@@ -1,39 +0,0 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: >
-  Properties for a PCT2075 I2C temperature sensor
-
-include: cros_ec_temp_sensor.yaml
-
-compatible: cros-ec,temp-sensor-pct2075
-
-properties:
-    pct2075-name:
-      type: string
-      required: true
-      description:
-        Enum value to index into the PCT2075 specific sensors
-      enum:
-      - PCT2075_SOC
-      - PCT2075_AMB
-
-    port:
-      required: true
-      type: phandle
-      description: phandle to the named i2c port
-
-    i2c-addr-flags:
-      required: true
-      type: string
-      description: I2C address of chip
-      enum:
-        - PCT2075_I2C_ADDR_FLAGS0
-        - PCT2075_I2C_ADDR_FLAGS1
-        - PCT2075_I2C_ADDR_FLAGS2
-        - PCT2075_I2C_ADDR_FLAGS3
-        - PCT2075_I2C_ADDR_FLAGS4
-        - PCT2075_I2C_ADDR_FLAGS5
-        - PCT2075_I2C_ADDR_FLAGS6
-        - PCT2075_I2C_ADDR_FLAGS7
diff --git a/zephyr/dts/bindings/temp/cros_ec_temp_sensor_sb_tsi.yaml b/zephyr/dts/bindings/temp/cros_ec_temp_sensor_sb_tsi.yaml
deleted file mode 100644
index a0772281cb..0000000000
--- a/zephyr/dts/bindings/temp/cros_ec_temp_sensor_sb_tsi.yaml
+++ /dev/null
@@ -1,16 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: >
-  Properties for an Side Band Temperature Sensor Interface sensor
-
-include: cros_ec_temp_sensor.yaml
-
-compatible: cros-ec,temp-sensor-sb-tsi
-
-properties:
-    port:
-      required: true
-      type: phandle
-      description: phandle to the sensor's i2c port
diff --git a/zephyr/dts/bindings/temp/cros_ec_temp_sensor_tmp112.yaml b/zephyr/dts/bindings/temp/cros_ec_temp_sensor_tmp112.yaml
deleted file mode 100644
index 0cf05f48a0..0000000000
--- a/zephyr/dts/bindings/temp/cros_ec_temp_sensor_tmp112.yaml
+++ /dev/null
@@ -1,35 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: >
-  Properties for a TMP112 I2C temperature sensor
-
-include: cros_ec_temp_sensor.yaml
-
-compatible: cros-ec,temp-sensor-tmp112
-
-properties:
-    tmp112-name:
-      type: string
-      required: true
-      description:
-        Enum value to index into the TMP112 specific sensors
-      enum:
-      - TMP112_SOC
-      - TMP112_AMB
-
-    port:
-      required: true
-      type: phandle
-      description: phandle to the named i2c port
-
-    i2c-addr-flags:
-      required: true
-      type: string
-      description: I2C address of chip
-      enum:
-        - TMP112_I2C_ADDR_FLAGS0
-        - TMP112_I2C_ADDR_FLAGS1
-        - TMP112_I2C_ADDR_FLAGS2
-        - TMP112_I2C_ADDR_FLAGS3
diff --git a/zephyr/dts/bindings/temp/nxp,pct2075.yaml b/zephyr/dts/bindings/temp/nxp,pct2075.yaml
new file mode 100644
index 0000000000..bca7f7125b
--- /dev/null
+++ b/zephyr/dts/bindings/temp/nxp,pct2075.yaml
@@ -0,0 +1,10 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: >
+  Properties for a PCT2075 I2C temperature sensor
+
+compatible: "nxp,pct2075"
+
+include: i2c-device.yaml
diff --git a/zephyr/dts/bindings/usbc/bc12/pericom,pi3usb9201.yaml b/zephyr/dts/bindings/usbc/bc12/pericom,pi3usb9201.yaml
new file mode 100644
index 0000000000..841c443877
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/bc12/pericom,pi3usb9201.yaml
@@ -0,0 +1,11 @@
+description: USBC BC1.2
+
+compatible: "pericom,pi3usb9201"
+
+include: base.yaml
+
+properties:
+  irq:
+    type: phandles
+    description: |
+        GPIO interrupt from BC1.2
diff --git a/zephyr/dts/bindings/usbc/bc12/richtek,rt1718s-bc12.yaml b/zephyr/dts/bindings/usbc/bc12/richtek,rt1718s-bc12.yaml
new file mode 100644
index 0000000000..6a93e78496
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/bc12/richtek,rt1718s-bc12.yaml
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: USBC RT1718S BC1.2
+
+compatible: "richtek,rt1718s-bc12"
+
+include: base.yaml
diff --git a/zephyr/dts/bindings/usbc/richtek,rt1739-bc12.yaml b/zephyr/dts/bindings/usbc/bc12/richtek,rt1739-bc12.yaml
index b6f44f72db..aef959bea8 100644
--- a/zephyr/dts/bindings/usbc/richtek,rt1739-bc12.yaml
+++ b/zephyr/dts/bindings/usbc/bc12/richtek,rt1739-bc12.yaml
@@ -1,7 +1,9 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 description: USBC BC1.2
 
 compatible: "richtek,rt1739-bc12"
+
+include: base.yaml
diff --git a/zephyr/dts/bindings/usbc/richtek,rt9490-bc12.yaml b/zephyr/dts/bindings/usbc/bc12/richtek,rt9490-bc12.yaml
index 94496455a3..38791d65bf 100644
--- a/zephyr/dts/bindings/usbc/richtek,rt9490-bc12.yaml
+++ b/zephyr/dts/bindings/usbc/bc12/richtek,rt9490-bc12.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -6,6 +6,8 @@ description: USBC BC1.2
 
 compatible: "richtek,rt9490-bc12"
 
+include: base.yaml
+
 properties:
   irq:
     type: phandles
diff --git a/zephyr/dts/bindings/usbc/cros-ec,tcpci.yaml b/zephyr/dts/bindings/usbc/cros-ec,tcpci.yaml
deleted file mode 100644
index a3c36d9ded..0000000000
--- a/zephyr/dts/bindings/usbc/cros-ec,tcpci.yaml
+++ /dev/null
@@ -1,16 +0,0 @@
-description: USBC TCPC
-
-compatible: "cros-ec,tcpci"
-
-properties:
-  port:
-    type: phandle
-    required: true
-    description: |
-      I2C port used to communicate with controller
-
-  i2c-addr-flags:
-    type: int
-    required: true
-    description: |
-      I2C address of controller
diff --git a/zephyr/dts/bindings/usbc/cros-ec,usb-mux-chain.yaml b/zephyr/dts/bindings/usbc/cros-ec,usb-mux-chain.yaml
new file mode 100644
index 0000000000..398d7255ac
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/cros-ec,usb-mux-chain.yaml
@@ -0,0 +1,47 @@
+# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: USB-C muxes chain
+
+compatible: "cros-ec,usb-mux-chain"
+
+properties:
+  usb-muxes:
+    type: phandles
+    required: true
+    description: |
+      List of USB-C muxes and retimers for the USB-C port. The USB-C subsystem
+      traverses this list in the order specified. The phandles are references to
+      cros-ec,usbc-mux nodes. Link this mux chain with a specific USB-C port by
+      adding the "cros-ec,usb-mux-chain" as a child of the "named-usbc-port"
+      node.
+
+  alternative-chain:
+    type: boolean
+    description: |
+      Set if this is alternative USB-C muxes chain. It can be selected in
+      runtime using USB_MUX_ENABLE_ALTERNATIVE macro.
+
+# Example DTS defining USB-C port 0 with main and alternative usb mux chains.
+# The main chain has two muxes: BB retimer and virtual mux.
+# The alternative chain has three muxes: BB retimer, SOC side BB retimer and
+# virtual mux.
+#
+#       usbc_port0: port0@0 {
+#               compatible = "named-usbc-port";
+#               reg = <0>;
+#               ...
+#               usb-mux-chain-0 {
+#                       compatible = "cros-ec,usb-mux-chain";
+#                       usb-muxes = <&usb_c0_bb_retimer
+#                                    &virtual_mux_c0>;
+#               };
+#               usb-mux-chain-0 {
+#                       compatible = "cros-ec,usb-mux-chain";
+#                       alternative-chain;
+#                       usb-muxes = <&usb_c0_bb_retimer
+#                                    &usb_c0_soc_side_bb_retimer
+#                                    &virtual_mux_c0>;
+#               };
+#       };
diff --git a/zephyr/dts/bindings/usbc/cypress,ccgxxf.yaml b/zephyr/dts/bindings/usbc/cypress,ccgxxf.yaml
deleted file mode 100644
index 61f05495ea..0000000000
--- a/zephyr/dts/bindings/usbc/cypress,ccgxxf.yaml
+++ /dev/null
@@ -1,23 +0,0 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: USBC TCPC
-
-compatible: "cypress,ccgxxf"
-
-properties:
-  port:
-    type: phandle
-    required: true
-    description: |
-      I2C port used to communicate with controller
-
-  i2c-addr-flags:
-    type: string
-    default: "CCGXXF_I2C_ADDR1_FLAGS"
-    enum:
-      - "CCGXXF_I2C_ADDR1_FLAGS"
-      - "CCGXXF_I2C_ADDR2_FLAGS"
-    description: |
-      I2C address of controller
diff --git a/zephyr/dts/bindings/usbc/fairchild,fusb302.yaml b/zephyr/dts/bindings/usbc/fairchild,fusb302.yaml
deleted file mode 100644
index 1eba4dedaf..0000000000
--- a/zephyr/dts/bindings/usbc/fairchild,fusb302.yaml
+++ /dev/null
@@ -1,21 +0,0 @@
-description: USBC TCPC
-
-compatible: "fairchild,fusb302"
-
-properties:
-  port:
-    type: phandle
-    required: true
-    description: |
-      I2C port used to communicate with controller
-
-  i2c-addr-flags:
-    type: string
-    default: "FUSB302_I2C_ADDR_FLAGS"
-    enum:
-      - "FUSB302_I2C_ADDR_FLAGS"
-      - "FUSB302_I2C_ADDR_B01_FLAGS"
-      - "FUSB302_I2C_ADDR_B10_FLAGS"
-      - "FUSB302_I2C_ADDR_B11_FLAGS"
-    description: |
-      I2C address of controller
diff --git a/zephyr/dts/bindings/usbc/ite,it8xxx2-tcpc.yaml b/zephyr/dts/bindings/usbc/ite,it8xxx2-tcpc.yaml
deleted file mode 100644
index 846ac5ead7..0000000000
--- a/zephyr/dts/bindings/usbc/ite,it8xxx2-tcpc.yaml
+++ /dev/null
@@ -1,3 +0,0 @@
-description: USBC TCPC
-
-compatible: "ite,it8xxx2-tcpc"
diff --git a/zephyr/dts/bindings/usbc/mux/amd,usbc-mux-amd-fp6.yaml b/zephyr/dts/bindings/usbc/mux/amd,usbc-mux-amd-fp6.yaml
new file mode 100644
index 0000000000..1ce1db82c7
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/mux/amd,usbc-mux-amd-fp6.yaml
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: USB-C AMD-FP6 mux
+
+include: ["i2c-device.yaml", "cros-ec,usbc-mux.yaml"]
+
+compatible: "amd,usbc-mux-amd-fp6"
diff --git a/zephyr/dts/bindings/usbc/mux/analogix,anx7483.yaml b/zephyr/dts/bindings/usbc/mux/analogix,anx7483.yaml
index 9e4716d5d1..c4ac7782f0 100644
--- a/zephyr/dts/bindings/usbc/mux/analogix,anx7483.yaml
+++ b/zephyr/dts/bindings/usbc/mux/analogix,anx7483.yaml
@@ -1,26 +1,10 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 description: |
   Analogix re-timing MUX
 
-include: cros-ec,usbc-mux.yaml
+include: ["i2c-device.yaml", "cros-ec,usbc-mux.yaml"]
 
 compatible: "analogix,anx7483"
-
-properties:
-  port:
-    type: phandle
-    required: true
-    description: phandle to the named i2c port
-
-  i2c-addr-flags:
-    type: string
-    required: true
-    description: I2C address of chip
-    enum:
-      - ANX7483_I2C_ADDR0_FLAGS
-      - ANX7483_I2C_ADDR1_FLAGS
-      - ANX7483_I2C_ADDR2_FLAGS
-      - ANX7483_I2C_ADDR3_FLAGS
diff --git a/zephyr/dts/bindings/usbc/mux/analogix,usbc-mux-anx7447.yaml b/zephyr/dts/bindings/usbc/mux/analogix,usbc-mux-anx7447.yaml
new file mode 100644
index 0000000000..25b042e28c
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/mux/analogix,usbc-mux-anx7447.yaml
@@ -0,0 +1,15 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: USBC ANX7447 USB MUX
+
+include: cros-ec,usbc-mux.yaml
+
+compatible: "analogix,usbc-mux-anx7447"
+
+properties:
+  hpd-update-enable:
+    type: boolean
+    description: |
+      Enable anx7447 hpd update callback
diff --git a/zephyr/dts/bindings/usbc/mux/cros-ec,usbc-mux-tcpci.yaml b/zephyr/dts/bindings/usbc/mux/cros-ec,usbc-mux-tcpci.yaml
index 9b986a5942..548d510630 100644
--- a/zephyr/dts/bindings/usbc/mux/cros-ec,usbc-mux-tcpci.yaml
+++ b/zephyr/dts/bindings/usbc/mux/cros-ec,usbc-mux-tcpci.yaml
@@ -1,10 +1,12 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 description: USBC TCPC USB MUX
 
-include: cros-ec,usbc-mux.yaml
+# Include base.yaml instead of i2c-device.yaml because the reg property is not
+# required for this node.
+include: ["base.yaml", "cros-ec,usbc-mux.yaml"]
 
 compatible: "cros-ec,usbc-mux-tcpci"
 
@@ -14,56 +16,3 @@ properties:
     required: false
     description: |
       Name of function used as hpd_update callback
-    enum:
-      - ps8xxx_tcpc_update_hpd_status
-
-  port:
-    type: phandle
-    required: false
-    description: |
-      If the TCPC in your design is used to manage both the power-delivery
-      interface and configure the mux for the USB superspeed signals, this
-      property, and the i2c-addr-flags should be omitted. The driver uses
-      the I2C configuration specified in the corresponding TCPC node.
-
-      Example below
-
-      port0@0 {
-          compatible = "named-usbc-port";
-          reg = <0>;
-          tcpc {
-              compatible = "parade,ps8xxx";
-              status = "okay";
-              port = <&i2c_tcpc0>;
-              i2c-addr-flags = "PS8XXX_I2C_ADDR1_FLAGS";
-          };
-          usb-muxes = <&usb_mux_0>;
-      };
-      usb_mux_0 usb-mux-0 {
-          compatible = "parade,usbc-mux-ps8xxx";
-          /* I2C configuration provide by TCPC node */
-      };
-
-      If the TCPC in your design only configures the USB superspeed signals,
-      for instance when the EC chip contains an embedded TCPC controller,
-      then port and i2c-addr-flags are required.
-
-      port0@0 {
-          compatible = "named-usbc-port";
-          reg = <0>;
-          tcpc {
-              compatible = "ite,it8xxx2-tcpc";
-          };
-      };
-      usb_mux_0 usb-mux-0 {
-          compatible = "parade,usbc-mux-ps8xxx";
-          port = <i2c_usbc0>;
-          i2c-addr-flags = "PS8XXX_I2C_ADDR1_FLAGS";
-      };
-
-  i2c-addr-flags:
-    type: int
-    required: false
-    description: |
-      I2C address of chip. If provided, port property has to be present too.
-      Please check description of port property for more information.
diff --git a/zephyr/dts/bindings/usbc/mux/cros-ec,usbc-mux-virtual.yaml b/zephyr/dts/bindings/usbc/mux/cros-ec,usbc-mux-virtual.yaml
index cadeb6d35b..7231bc9e2c 100644
--- a/zephyr/dts/bindings/usbc/mux/cros-ec,usbc-mux-virtual.yaml
+++ b/zephyr/dts/bindings/usbc/mux/cros-ec,usbc-mux-virtual.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/usbc/mux/cros-ec,usbc-mux.yaml b/zephyr/dts/bindings/usbc/mux/cros-ec,usbc-mux.yaml
index 21cb8e0a3f..0e76f548a9 100644
--- a/zephyr/dts/bindings/usbc/mux/cros-ec,usbc-mux.yaml
+++ b/zephyr/dts/bindings/usbc/mux/cros-ec,usbc-mux.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/dts/bindings/usbc/mux/intel,jhl804r.yaml b/zephyr/dts/bindings/usbc/mux/intel,jhl8040r.yaml
index 5098080c25..6289d440f1 100644
--- a/zephyr/dts/bindings/usbc/mux/intel,jhl804r.yaml
+++ b/zephyr/dts/bindings/usbc/mux/intel,jhl8040r.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -6,7 +6,7 @@ description: Intel JHL8040R Thunderbolt 4 Retimer
 
 compatible: "intel,jhl8040r"
 
-include: cros-ec,usbc-mux.yaml
+include: ["i2c-device.yaml", "cros-ec,usbc-mux.yaml"]
 
 properties:
     reset-pin:
@@ -20,13 +20,3 @@ properties:
     ls-en-pin:
       type: phandle
       required: false
-
-    port:
-      type: phandle
-      required: true
-      description: phandle to the named i2c port
-
-    i2c-addr-flags:
-      type: int
-      required: true
-      description: I2C address of chip
diff --git a/zephyr/dts/bindings/usbc/mux/ite,it5205.yaml b/zephyr/dts/bindings/usbc/mux/ite,it5205.yaml
index 4d4c360d47..3c9381aee1 100644
--- a/zephyr/dts/bindings/usbc/mux/ite,it5205.yaml
+++ b/zephyr/dts/bindings/usbc/mux/ite,it5205.yaml
@@ -1,23 +1,9 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 description: ITE IT5205 USB Type-C 3:2 alternate mode MUX
 
-include: cros-ec,usbc-mux.yaml
+include: ["i2c-device.yaml", "cros-ec,usbc-mux.yaml"]
 
 compatible: "ite,it5205"
-
-properties:
-  port:
-    type: phandle
-    required: true
-    description: phandle to the named i2c port
-
-  i2c-addr-flags:
-    type: string
-    required: true
-    description: I2C address of chip
-    enum:
-      - IT5205_I2C_ADDR1_FLAGS
-      - IT5205_I2C_ADDR2_FLAGS
diff --git a/zephyr/dts/bindings/usbc/mux/parade,ps8743.yaml b/zephyr/dts/bindings/usbc/mux/parade,ps8743.yaml
new file mode 100644
index 0000000000..1ee0bbaf74
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/mux/parade,ps8743.yaml
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Parade PS8743 USB Type-C alternate mode MUX
+
+include: ["i2c-device.yaml", "cros-ec,usbc-mux.yaml"]
+
+compatible: "parade,ps8743"
diff --git a/zephyr/dts/bindings/usbc/mux/parade,ps8818.yaml b/zephyr/dts/bindings/usbc/mux/parade,ps8818.yaml
new file mode 100644
index 0000000000..aafdf29341
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/mux/parade,ps8818.yaml
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: USBC PS8818 Retimer
+
+include: ["i2c-device.yaml", "cros-ec,usbc-mux.yaml"]
+
+compatible: "parade,ps8818"
diff --git a/zephyr/dts/bindings/usbc/mux/parade,usbc-mux-ps8xxx.yaml b/zephyr/dts/bindings/usbc/mux/parade,usbc-mux-ps8xxx.yaml
index 685544cbf4..4df0b35d76 100644
--- a/zephyr/dts/bindings/usbc/mux/parade,usbc-mux-ps8xxx.yaml
+++ b/zephyr/dts/bindings/usbc/mux/parade,usbc-mux-ps8xxx.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -13,3 +13,5 @@ properties:
     description: |
       PS8xxx USB MUX almost always use this hdp_update callback
     default: "ps8xxx_tcpc_update_hpd_status"
+    enum:
+      - ps8xxx_tcpc_update_hpd_status
diff --git a/zephyr/dts/bindings/usbc/mux/ti,tusb1064.yaml b/zephyr/dts/bindings/usbc/mux/ti,tusb1064.yaml
index 6c625459c1..d5a0b34e6c 100644
--- a/zephyr/dts/bindings/usbc/mux/ti,tusb1064.yaml
+++ b/zephyr/dts/bindings/usbc/mux/ti,tusb1064.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -6,34 +6,6 @@ description: |
   TI TUSB546, TUSB1044, or TUSB1064 USB-C MUX, device variant depends on
   CONFIG_PLATFORM_EC_USB_MUX_TUSB_TYPE Kconfig choice
 
-include: cros-ec,usbc-mux.yaml
+include: ["i2c-device.yaml", "cros-ec,usbc-mux.yaml"]
 
 compatible: "ti,tusb1064"
-
-properties:
-  port:
-    type: phandle
-    required: true
-    description: phandle to the named i2c port
-
-  i2c-addr-flags:
-    type: string
-    required: true
-    description: I2C address of chip
-    enum:
-      - TUSB1064_I2C_ADDR0_FLAGS
-      - TUSB1064_I2C_ADDR1_FLAGS
-      - TUSB1064_I2C_ADDR2_FLAGS
-      - TUSB1064_I2C_ADDR3_FLAGS
-      - TUSB1064_I2C_ADDR4_FLAGS
-      - TUSB1064_I2C_ADDR5_FLAGS
-      - TUSB1064_I2C_ADDR6_FLAGS
-      - TUSB1064_I2C_ADDR7_FLAGS
-      - TUSB1064_I2C_ADDR8_FLAGS
-      - TUSB1064_I2C_ADDR9_FLAGS
-      - TUSB1064_I2C_ADDR10_FLAGS
-      - TUSB1064_I2C_ADDR11_FLAGS
-      - TUSB1064_I2C_ADDR12_FLAGS
-      - TUSB1064_I2C_ADDR13_FLAGS
-      - TUSB1064_I2C_ADDR14_FLAGS
-      - TUSB1064_I2C_ADDR15_FLAGS
diff --git a/zephyr/dts/bindings/usbc/named-usbc-port.yaml b/zephyr/dts/bindings/usbc/named-usbc-port.yaml
index bcd9c7a2b4..1cdcb878b2 100644
--- a/zephyr/dts/bindings/usbc/named-usbc-port.yaml
+++ b/zephyr/dts/bindings/usbc/named-usbc-port.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -9,13 +9,36 @@ compatible: "named-usbc-port"
 include: base.yaml
 
 properties:
-  usb-muxes:
-    type: phandles
+  bc12:
+    type: phandle
     required: false
     description: |
-      List of USB-C muxes and retimers for the USB-C port. The USB-C subsystem
-      traverses this list in the order specified. The phandles are references to
-      cros-ec,usbc-mux nodes.
+      BC1.2 chip for the USB-C port.
+  tcpc:
+    type: phandle
+    required: false
+    description: |
+      TCPC chip for the USB-C port.
+  chg:
+    type: phandle
+    required: false
+    description: |
+      Charger chip for the USB-C port.
+  chg_alt:
+    type: phandle
+    required: false
+    description: |
+      Alternative charger for the USB-C port.
+  ppc:
+    type: phandle
+    required: false
+    description: |
+      PPC for the USB-C port.
+  ppc_alt:
+    type: phandle
+    required: false
+    description: |
+      Alternate PPC for the USB-C port.
 
 
 # Example:
@@ -27,17 +50,11 @@ properties:
 #		port0@0 {
 #			compatible = "named-usbc-port";
 #			reg = <0>;
-#			bc12 {
-#				compatible = "pericom,pi3usb9201";
-#				port = <&i2c_ec_i2c_usb_c0>;
-#			};
+#			bc12 = <&bc12_port0>;
 #		};
 #		port1@1 {
 #			compatible = "named-usbc-port";
 #			reg = <1>;
-#			bc12 {
-#				compatible = "pericom,pi3usb9201";
-#				port = <&i2c_ec_i2c_sub_usb_c1>;
-#			};
+#			bc12 = <&bc12_port1>;
 #		};
 #	};
diff --git a/zephyr/dts/bindings/usbc/nuvoton,nct38xx.yaml b/zephyr/dts/bindings/usbc/nuvoton,nct38xx.yaml
deleted file mode 100644
index ddd307c2a2..0000000000
--- a/zephyr/dts/bindings/usbc/nuvoton,nct38xx.yaml
+++ /dev/null
@@ -1,40 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: Nuvoton NCT38XX USB TCPC binding
-
-compatible: "nuvoton,nct38xx"
-
-properties:
-  gpio-dev:
-    type: phandle
-    description: |
-      Pointer to the NCT38XX GPIO device. This is used to binding the Cros TCPC
-      port index to Zephyr NCT38XX GPIO device.
-
-  port:
-    type: phandle
-    description: |
-      I2C port used to communicate with controller
-
-  i2c-addr-flags:
-    type: string
-    default: "NCT38XX_I2C_ADDR1_1_FLAGS"
-    enum:
-      - "NCT38XX_I2C_ADDR1_1_FLAGS"
-      - "NCT38XX_I2C_ADDR1_2_FLAGS"
-      - "NCT38XX_I2C_ADDR1_3_FLAGS"
-      - "NCT38XX_I2C_ADDR1_4_FLAGS"
-      - "NCT38XX_I2C_ADDR2_1_FLAGS"
-      - "NCT38XX_I2C_ADDR2_2_FLAGS"
-      - "NCT38XX_I2C_ADDR2_3_FLAGS"
-      - "NCT38XX_I2C_ADDR2_4_FLAGS"
-    description: |
-      I2C address of controller
-
-  tcpc-flags:
-    type: int
-    default: 0
-    description: |
-      TCPC configuration flags
diff --git a/zephyr/dts/bindings/usbc/parade,ps8xxx.yaml b/zephyr/dts/bindings/usbc/parade,ps8xxx.yaml
deleted file mode 100644
index 8a65e736c9..0000000000
--- a/zephyr/dts/bindings/usbc/parade,ps8xxx.yaml
+++ /dev/null
@@ -1,29 +0,0 @@
-description: USBC TCPC
-
-compatible: "parade,ps8xxx"
-
-properties:
-  port:
-    type: phandle
-    required: true
-    description: |
-      I2C port used to communicate with controller
-
-  i2c-addr-flags:
-    type: string
-    default: "PS8XXX_I2C_ADDR1_FLAGS"
-    enum:
-      - "PS8XXX_I2C_ADDR1_P1_FLAGS"
-      - "PS8XXX_I2C_ADDR1_P2_FLAGS"
-      - "PS8XXX_I2C_ADDR1_FLAGS"
-      - "PS8XXX_I2C_ADDR2_FLAGS"
-      - "PS8XXX_I2C_ADDR3_FLAGS"
-      - "PS8XXX_I2C_ADDR4_FLAGS"
-    description: |
-      I2C address of controller
-
-  tcpc-flags:
-    type: int
-    default: 0
-    description: |
-      TCPC configuration flags
diff --git a/zephyr/dts/bindings/usbc/pericom,pi3usb9201.yaml b/zephyr/dts/bindings/usbc/pericom,pi3usb9201.yaml
deleted file mode 100644
index 41e1501684..0000000000
--- a/zephyr/dts/bindings/usbc/pericom,pi3usb9201.yaml
+++ /dev/null
@@ -1,26 +0,0 @@
-description: USBC BC1.2
-
-compatible: "pericom,pi3usb9201"
-
-properties:
-  port:
-    type: phandle
-    required: true
-    description: |
-      I2C port used to communicate with controller
-
-  irq:
-    type: phandles
-    description: |
-        GPIO interrupt from BC1.2
-
-  i2c-addr-flags:
-    type: string
-    default: "PI3USB9201_I2C_ADDR_3_FLAGS"
-    enum:
-      - "PI3USB9201_I2C_ADDR_0_FLAGS"
-      - "PI3USB9201_I2C_ADDR_1_FLAGS"
-      - "PI3USB9201_I2C_ADDR_2_FLAGS"
-      - "PI3USB9201_I2C_ADDR_3_FLAGS"
-    description: |
-      I2C address of controller
diff --git a/zephyr/dts/bindings/usbc/ppc-chip.yaml b/zephyr/dts/bindings/usbc/ppc-chip.yaml
index b5b2cedc03..7fe944fe4c 100644
--- a/zephyr/dts/bindings/usbc/ppc-chip.yaml
+++ b/zephyr/dts/bindings/usbc/ppc-chip.yaml
@@ -1,28 +1,14 @@
-# Copyright (c) 2021 The Chromium OS Authors
+# Copyright 2021 The ChromiumOS Authors
 # SPDX-License-Identifier: Apache-2.0
 
 description: Power path chip
 
+include: i2c-device.yaml
+
 properties:
-  port:
-    type: phandle
-    required: true
-    description: |
-      I2C port used to communicate with controller
 
   irq:
     type: phandles
     required: false
     description: |
       GPIO interrupt from PPC
-
-  i2c-addr-flags:
-    type: string
-    description: |
-      I2C address of controller
-
-  alternate-for:
-    type: phandle
-    description: |
-      Pointer to the primary PPC device that can be replaced at runtime
-      by this device.
diff --git a/zephyr/dts/bindings/usbc/ppc/aoz,aoz1380.yaml b/zephyr/dts/bindings/usbc/ppc/aoz,aoz1380.yaml
new file mode 100644
index 0000000000..52144ffc78
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/ppc/aoz,aoz1380.yaml
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: AOZ1380 USBC PPC binding
+
+compatible: "aoz,aoz1380"
+
+include: ppc-chip.yaml
diff --git a/zephyr/dts/bindings/usbc/ppc/nxp,nx20p348x.yaml b/zephyr/dts/bindings/usbc/ppc/nxp,nx20p348x.yaml
new file mode 100644
index 0000000000..b297702356
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/ppc/nxp,nx20p348x.yaml
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: NXP NX20P348X USBC PPC binding
+
+compatible: "nxp,nx20p348x"
+
+include: ppc-chip.yaml
diff --git a/zephyr/dts/bindings/usbc/ppc/richtek,rt1739-ppc.yaml b/zephyr/dts/bindings/usbc/ppc/richtek,rt1739-ppc.yaml
new file mode 100644
index 0000000000..e15322883c
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/ppc/richtek,rt1739-ppc.yaml
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: USBC PPC
+
+compatible: "richtek,rt1739-ppc"
+
+include: ppc-chip.yaml
diff --git a/zephyr/dts/bindings/usbc/silergy,syv682x.yaml b/zephyr/dts/bindings/usbc/ppc/silergy,syv682x.yaml
index 51ab7e89e1..ab45a98ebd 100644
--- a/zephyr/dts/bindings/usbc/silergy,syv682x.yaml
+++ b/zephyr/dts/bindings/usbc/ppc/silergy,syv682x.yaml
@@ -9,11 +9,3 @@ properties:
     type: phandle
     description: The GPIO that controls FRS enable on this device
     required: false
-
-  i2c-addr-flags:
-    default: "SYV682X_ADDR0_FLAGS"
-    enum:
-      - "SYV682X_ADDR0_FLAGS"
-      - "SYV682X_ADDR1_FLAGS"
-      - "SYV682X_ADDR2_FLAGS"
-      - "SYV682X_ADDR3_FLAGS"
diff --git a/zephyr/dts/bindings/usbc/ppc/ti,sn5s330.yaml b/zephyr/dts/bindings/usbc/ppc/ti,sn5s330.yaml
new file mode 100644
index 0000000000..9d92811c03
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/ppc/ti,sn5s330.yaml
@@ -0,0 +1,5 @@
+description: USBC PPC
+
+compatible: "ti,sn5s330"
+
+include: ppc-chip.yaml
diff --git a/zephyr/dts/bindings/usbc/richtek,rt1739-ppc.yaml b/zephyr/dts/bindings/usbc/richtek,rt1739-ppc.yaml
deleted file mode 100644
index a1f2dbdbb0..0000000000
--- a/zephyr/dts/bindings/usbc/richtek,rt1739-ppc.yaml
+++ /dev/null
@@ -1,18 +0,0 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-description: USBC PPC
-
-compatible: "richtek,rt1739-ppc"
-
-include: ppc-chip.yaml
-
-properties:
-  i2c-addr-flags:
-    default: "RT1739_ADDR1_FLAGS"
-    enum:
-      - "RT1739_ADDR1_FLAGS"
-      - "RT1739_ADDR2_FLAGS"
-      - "RT1739_ADDR3_FLAGS"
-      - "RT1739_ADDR4_FLAGS"
diff --git a/zephyr/dts/bindings/usbc/tcpc/anologix,anx7447-tcpc.yaml b/zephyr/dts/bindings/usbc/tcpc/anologix,anx7447-tcpc.yaml
new file mode 100644
index 0000000000..cb10c3ee15
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/tcpc/anologix,anx7447-tcpc.yaml
@@ -0,0 +1,12 @@
+description: Anologix ANX7447 USBC TCPC binding
+
+compatible: "anologix,anx7447-tcpc"
+
+include: i2c-device.yaml
+
+properties:
+  tcpc-flags:
+    type: int
+    default: 0
+    description: |
+      TCPC configuration flags
diff --git a/zephyr/dts/bindings/usbc/tcpc/cros-ec,tcpci.yaml b/zephyr/dts/bindings/usbc/tcpc/cros-ec,tcpci.yaml
new file mode 100644
index 0000000000..10a8f04f55
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/tcpc/cros-ec,tcpci.yaml
@@ -0,0 +1,5 @@
+description: USBC TCPC
+
+compatible: "cros-ec,tcpci"
+
+include: i2c-device.yaml
diff --git a/zephyr/dts/bindings/usbc/tcpc/cypress,ccgxxf.yaml b/zephyr/dts/bindings/usbc/tcpc/cypress,ccgxxf.yaml
new file mode 100644
index 0000000000..f6ad3c3ba6
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/tcpc/cypress,ccgxxf.yaml
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: USBC TCPC
+
+compatible: "cypress,ccgxxf"
+
+include: i2c-device.yaml
diff --git a/zephyr/dts/bindings/usbc/tcpc/fairchild,fusb302.yaml b/zephyr/dts/bindings/usbc/tcpc/fairchild,fusb302.yaml
new file mode 100644
index 0000000000..05b7f9b9ad
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/tcpc/fairchild,fusb302.yaml
@@ -0,0 +1,5 @@
+description: USBC TCPC
+
+compatible: "fairchild,fusb302"
+
+include: i2c-device.yaml
diff --git a/zephyr/dts/bindings/usbc/tcpc/nuvoton,nct38xx.yaml b/zephyr/dts/bindings/usbc/tcpc/nuvoton,nct38xx.yaml
new file mode 100644
index 0000000000..51a69846e0
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/tcpc/nuvoton,nct38xx.yaml
@@ -0,0 +1,22 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: Nuvoton NCT38XX USB TCPC binding
+
+compatible: "nuvoton,nct38xx"
+
+include: i2c-device.yaml
+
+properties:
+  gpio-dev:
+    type: phandle
+    description: |
+      Pointer to the NCT38XX GPIO device. This is used to binding the Cros TCPC
+      port index to Zephyr NCT38XX GPIO device.
+
+  tcpc-flags:
+    type: int
+    default: 0
+    description: |
+      TCPC configuration flags
diff --git a/zephyr/dts/bindings/usbc/tcpc/parade,ps8xxx.yaml b/zephyr/dts/bindings/usbc/tcpc/parade,ps8xxx.yaml
new file mode 100644
index 0000000000..8048e05522
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/tcpc/parade,ps8xxx.yaml
@@ -0,0 +1,12 @@
+description: USBC TCPC
+
+compatible: "parade,ps8xxx"
+
+include: i2c-device.yaml
+
+properties:
+  tcpc-flags:
+    type: int
+    default: 0
+    description: |
+      TCPC configuration flags
diff --git a/zephyr/dts/bindings/usbc/tcpc/richtek,rt1718s-tcpc.yaml b/zephyr/dts/bindings/usbc/tcpc/richtek,rt1718s-tcpc.yaml
new file mode 100644
index 0000000000..fb7dc8a4aa
--- /dev/null
+++ b/zephyr/dts/bindings/usbc/tcpc/richtek,rt1718s-tcpc.yaml
@@ -0,0 +1,17 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+description: USBC RT1718S TCPC
+
+compatible: "richtek,rt1718s-tcpc"
+
+include: i2c-device.yaml
+
+properties:
+  tcpc-flags:
+    type: int
+    default: 0
+    description: |
+      TCPC configuration flags
+
diff --git a/zephyr/dts/bindings/usbc/ti,sn5s330.yaml b/zephyr/dts/bindings/usbc/ti,sn5s330.yaml
deleted file mode 100644
index 664f888805..0000000000
--- a/zephyr/dts/bindings/usbc/ti,sn5s330.yaml
+++ /dev/null
@@ -1,14 +0,0 @@
-description: USBC PPC
-
-compatible: "ti,sn5s330"
-
-include: ppc-chip.yaml
-
-properties:
-  i2c-addr-flags:
-    default: "SN5S330_ADDR0_FLAGS"
-    enum:
-      - "SN5S330_ADDR0_FLAGS"
-      - "SN5S330_ADDR1_FLAGS"
-      - "SN5S330_ADDR2_FLAGS"
-      - "SN5S330_ADDR3_FLAGS"
diff --git a/zephyr/dts/bindings/vendor-prefixes.txt b/zephyr/dts/bindings/vendor-prefixes.txt
index 403b0ba1ea..53dd2d4cfc 100644
--- a/zephyr/dts/bindings/vendor-prefixes.txt
+++ b/zephyr/dts/bindings/vendor-prefixes.txt
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -9,9 +9,14 @@ cros-ec	The Chromium OS Embedded Controller Project
 cros	The Chromium OS Embedded Controller Project
 intersil	Intersil
 lgc	LG Chem
-as3gwrc3ka	Battery vendor
 smp	Battery vendor
 aec	Battery vendor
 powertech	Battery vendor
 getac	Battery vendor
 ganfeng	Battery vendor
+byd	Battery vendor
+celxpert	Battery vendor
+sunwoda	Battery vendor
+cosmx	Battery vendor
+dynapack	Battery vendor
+atl	Battery vendor
\ No newline at end of file
diff --git a/zephyr/dts/board-overlays/native_posix.dts b/zephyr/dts/board-overlays/native_posix.dts
index 7801997553..44a034d73b 100644
--- a/zephyr/dts/board-overlays/native_posix.dts
+++ b/zephyr/dts/board-overlays/native_posix.dts
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,7 +9,7 @@
 	named-gpios {
 		compatible = "named-gpios";
 
-		entering_rw {
+		entering-rw {
 			gpios = <&gpio0 1 GPIO_OUTPUT_LOW>;
 			enum-name = "GPIO_ENTERING_RW";
 		};
diff --git a/zephyr/dts/it8xxx2_emul.dts b/zephyr/dts/it8xxx2_emul.dts
new file mode 100644
index 0000000000..dcb44aebd2
--- /dev/null
+++ b/zephyr/dts/it8xxx2_emul.dts
@@ -0,0 +1,177 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Contains emulators for devices normally found on IT8xxx2 chips.
+ * To use, include this file, then the board's gpio definitions.
+ */
+
+#include <dt-bindings/gpio_defines.h>
+
+/ {
+	gpioa: gpio@f01601 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0xf01601 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpiob: gpio@f01602 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0xf01602 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpioc: gpio@f01603 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0xf01603 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpiod: gpio@f01604 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0xf01604 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpioe: gpio@f01605 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0xf01605 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpiof: gpio@f01606 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0xf01606 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpiog: gpio@f01607 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0xf01607 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpioh: gpio@f01608 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0xf01608 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpioi: gpio@f01609 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0xf01609 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpioj: gpio@f0160a {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0xf0160a 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpiok: gpio@f0160b {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0xf0160b 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpiol: gpio@f0160c {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0xf0160c 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpiom: gpio@f0160d {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0xf0160d 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+
+	i2c_ctrl0: i2c@f01c40 {
+		compatible = "zephyr,i2c-emul-controller";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0xf01c40 0x1000>;
+	};
+};
diff --git a/zephyr/dts/npcx_emul.dts b/zephyr/dts/npcx_emul.dts
new file mode 100644
index 0000000000..20b1a02eeb
--- /dev/null
+++ b/zephyr/dts/npcx_emul.dts
@@ -0,0 +1,266 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Contains emulators for devices normally found on NPCX chips.
+ * To use, include this file, then the board's gpio definitions.
+ */
+
+#include <dt-bindings/gpio_defines.h>
+
+/ {
+	gpio1: gpio@101 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0x101 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpio3: gpio@301 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0x301 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpio4: gpio@400 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0x400 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpio5: gpio@500 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0x500 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpio6: gpio@600 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0x600 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpio7: gpio@700 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0x700 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpio8: gpio@801 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0x801 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpio9: gpio@900 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0x900 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpioa: gpio@a00 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0xa00 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpiob: gpio@b00 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0xb00 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpioc: gpio@c00 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0xc00 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpiod: gpio@d00 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0xd00 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpioe: gpio@e00 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0xe00 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+	gpiof: gpio@f00 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0xf00 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <8>;
+	};
+
+	i2c_ctrl0: i2c@40009000 {
+		status = "okay";
+		compatible = "zephyr,i2c-emul-controller";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x40009000 0x1000>;
+	};
+	i2c_ctrl1: i2c@4000b000 {
+		status = "okay";
+		compatible = "zephyr,i2c-emul-controller";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x4000b000 0x1000>;
+	};
+
+	i2c_ctrl2: i2c@400c0000 {
+		status = "okay";
+		compatible = "zephyr,i2c-emul-controller";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x400c0000 0x1000>;
+	};
+
+	i2c_ctrl3: i2c@400c2000 {
+		status = "okay";
+		compatible = "zephyr,i2c-emul-controller";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x400c2000 0x1000>;
+	};
+
+	i2c_ctrl4: i2c@40008000 {
+		status = "okay";
+		compatible = "zephyr,i2c-emul-controller";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x40008000 0x1000>;
+	};
+
+	i2c_ctrl5: i2c@40017000 {
+		status = "okay";
+		compatible = "zephyr,i2c-emul-controller";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x40017000 0x1000>;
+	};
+
+	i2c_ctrl6: i2c@40018000 {
+		status = "okay";
+		compatible = "zephyr,i2c-emul-controller";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x40018000 0x1000>;
+	};
+
+	i2c_ctrl7: i2c@40019000 {
+		status = "okay";
+		compatible = "zephyr,i2c-emul-controller";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x40019000 0x1000>;
+	};
+	scfg: scfg@400c3000 {
+		compatible = "nuvoton,npcx-scfg";
+		/* First reg region is System Configuration Device */
+		/* Second reg region is System Glue Device */
+		reg = <0x400c3000 0x70
+			0x400a5000 0x2000>;
+		reg-names = "scfg", "glue";
+		#alt-cells = <3>;
+		#lvol-cells = <2>;
+	};
+};
+
+&gpio0 {
+	ngpios = <8>;
+};
diff --git a/zephyr/emul/CMakeLists.txt b/zephyr/emul/CMakeLists.txt
index 4b64e80736..f8e4bae15b 100644
--- a/zephyr/emul/CMakeLists.txt
+++ b/zephyr/emul/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -22,5 +22,8 @@ zephyr_library_sources_ifdef(CONFIG_EMUL_CLOCK_CONTROL	emul_clock_control.c)
 zephyr_library_sources_ifdef(CONFIG_EMUL_SN5S330	emul_sn5s330.c)
 zephyr_library_sources_ifdef(CONFIG_EMUL_KB_RAW		emul_kb_raw.c)
 zephyr_library_sources_ifdef(CONFIG_EMUL_CROS_FLASH	emul_flash.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_RTC		emul_rtc.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_RT9490		emul_rt9490.c)
+zephyr_library_sources_ifdef(CONFIG_PWM_MOCK            pwm_mock.c)
 
 cros_ec_library_include_directories_ifdef(CONFIG_EMUL_CROS_FLASH include)
diff --git a/zephyr/emul/Kconfig b/zephyr/emul/Kconfig
index ffbafd059a..3cabd96b6f 100644
--- a/zephyr/emul/Kconfig
+++ b/zephyr/emul/Kconfig
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -77,9 +77,28 @@ config EMUL_KB_RAW
 config EMUL_CROS_FLASH
 	bool "Emulated flash driver for the Zephyr shim"
 	select PLATFORM_EC_FLASH_CROS
+	imply SYSTEM_FAKE
 	help
 	  This option enables the flash emulator for testing.
 
+config EMUL_RTC
+	bool "Emulated RTC driver for Zephyr shim"
+	help
+	  This options enables the RTC emulator for testing.
+
+config EMUL_RT9490
+	bool "Rt9490 charger emulator"
+	select EMUL_COMMON_I2C
+	help
+	  Enable the RT9490 light sensor emulator. This driver use emulated I2C
+	  bus. Emulators API is available in zephyr/include/emul/emul_rt9490.h.
+
+config PWM_MOCK
+	bool "Mock implementation of an PWM device"
+	help
+	  Enable the PWM mock. This driver is a pure mock and does nothing by
+	  default.
+
 rsource "Kconfig.ln9310"
 rsource "Kconfig.lis2dw12"
 rsource "Kconfig.i2c_mock"
diff --git a/zephyr/emul/Kconfig.clock_control b/zephyr/emul/Kconfig.clock_control
index a4dfbce557..29b38333c9 100644
--- a/zephyr/emul/Kconfig.clock_control
+++ b/zephyr/emul/Kconfig.clock_control
@@ -1,12 +1,11 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
-DT_COMPAT_CLOCK_CONTROL_EMUL := cros,clock-control-emul
-
 config EMUL_CLOCK_CONTROL
 	bool "Emulated clock control"
-	default $(dt_compat_enabled,$(DT_COMPAT_CLOCK_CONTROL_EMUL))
+	default y
+	depends on DT_HAS_CROS_CLOCK_CONTROL_EMUL_ENABLED
 	help
 	  Enable the emulated clock control module. This module introduces a
 	  functioning clock control implementation along with backdoor APIs to
diff --git a/zephyr/emul/Kconfig.i2c_mock b/zephyr/emul/Kconfig.i2c_mock
index 6c98a32739..9bc75d961c 100644
--- a/zephyr/emul/Kconfig.i2c_mock
+++ b/zephyr/emul/Kconfig.i2c_mock
@@ -1,12 +1,11 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
-DT_COMPAT_I2C_MOCK := cros,i2c-mock
-
 menuconfig I2C_MOCK
 	bool "Mock implementation of an I2C device"
-	default $(dt_compat_enabled,$(DT_COMPAT_I2C_MOCK))
+	default y
+	depends on DT_HAS_CROS_I2C_MOCK_ENABLED
 	depends on I2C_EMUL
 	help
 	  Enable the I2C mock. This driver is a pure mock and does nothing by
diff --git a/zephyr/emul/Kconfig.isl923x b/zephyr/emul/Kconfig.isl923x
index bf124ec0a9..d1ad526979 100644
--- a/zephyr/emul/Kconfig.isl923x
+++ b/zephyr/emul/Kconfig.isl923x
@@ -1,12 +1,11 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
-DT_COMPAT_ISL923X_EMUL := cros,isl923x-emul
-
 menuconfig EMUL_ISL923X
 	bool "ISL923X switchcap emulator"
-	default $(dt_compat_enabled,$(DT_COMPAT_ISL923X_EMUL))
+	default y
+	depends on DT_HAS_CROS_ISL923X_EMUL_ENABLED
 	depends on I2C_EMUL
 	help
 	  Enable the ISL923X emulator. This driver uses the emulated I2C bus. It
diff --git a/zephyr/emul/Kconfig.lis2dw12 b/zephyr/emul/Kconfig.lis2dw12
index 2263255418..e74f1f8cf4 100644
--- a/zephyr/emul/Kconfig.lis2dw12
+++ b/zephyr/emul/Kconfig.lis2dw12
@@ -1,12 +1,11 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
-DT_COMPAT_LIS2DW12_EMUL := cros,lis2dw12-emul
-
 menuconfig EMUL_LIS2DW12
 	bool "LIS2DW12 accelerometer emulator"
-	default $(dt_compat_enabled,$(DT_COMPAT_LIS2DW12_EMUL))
+	default y
+	depends on DT_HAS_CROS_LIS2DW12_EMUL_ENABLED
 	depends on I2C_EMUL
 	select PLATFORM_EC_ACCEL_LIS2DW12
 	help
diff --git a/zephyr/emul/Kconfig.ln9310 b/zephyr/emul/Kconfig.ln9310
index c9e3e6fbc9..9cacfbd670 100644
--- a/zephyr/emul/Kconfig.ln9310
+++ b/zephyr/emul/Kconfig.ln9310
@@ -1,12 +1,11 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
-DT_COMPAT_LN9310_EMUL := cros,ln9310-emul
-
 menuconfig EMUL_LN9310
 	bool "LN9310 switchcap emulator"
-	default $(dt_compat_enabled,$(DT_COMPAT_LN9310_EMUL))
+	default y
+	depends on DT_HAS_CROS_LN9310_EMUL_ENABLED
 	depends on I2C_EMUL
 	depends on ASSERT
 	help
diff --git a/zephyr/emul/Kconfig.sn5s330 b/zephyr/emul/Kconfig.sn5s330
index bb3e5eeea8..283bf1fbd7 100644
--- a/zephyr/emul/Kconfig.sn5s330
+++ b/zephyr/emul/Kconfig.sn5s330
@@ -1,12 +1,11 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
-DT_COMPAT_SN5S330_EMUL := cros,sn5s330-emul
-
 menuconfig EMUL_SN5S330
 	bool "sn5s330 emulator"
-	default $(dt_compat_enabled,$(DT_COMPAT_SN5S330_EMUL))
+	default y
+	depends on DT_HAS_CROS_SN5S330_EMUL_ENABLED
 	depends on I2C_EMUL
 	depends on ASSERT
 	help
diff --git a/zephyr/emul/emul_bb_retimer.c b/zephyr/emul/emul_bb_retimer.c
index 9a3e0a7b6e..266fd1a340 100644
--- a/zephyr/emul/emul_bb_retimer.c
+++ b/zephyr/emul/emul_bb_retimer.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,13 +16,10 @@ LOG_MODULE_REGISTER(emul_bb_retimer);
 
 #include "emul/emul_common_i2c.h"
 #include "emul/emul_bb_retimer.h"
+#include "emul/emul_stub_device.h"
 
 #include "driver/retimer/bb_retimer.h"
 
-#define BB_DATA_FROM_I2C_EMUL(_emul)					     \
-	CONTAINER_OF(CONTAINER_OF(_emul, struct i2c_common_emul_data, emul), \
-		     struct bb_emul_data, common)
-
 /** Run-time data used by the emulator */
 struct bb_emul_data {
 	/** Common I2C data */
@@ -44,7 +41,7 @@ struct bb_emul_data {
 };
 
 /** Check description in emul_bb_retimer.h */
-void bb_emul_set_reg(struct i2c_emul *emul, int reg, uint32_t val)
+void bb_emul_set_reg(const struct emul *emul, int reg, uint32_t val)
 {
 	struct bb_emul_data *data;
 
@@ -52,12 +49,12 @@ void bb_emul_set_reg(struct i2c_emul *emul, int reg, uint32_t val)
 		return;
 	}
 
-	data = BB_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 	data->reg[reg] = val;
 }
 
 /** Check description in emul_bb_retimer.h */
-uint32_t bb_emul_get_reg(struct i2c_emul *emul, int reg)
+uint32_t bb_emul_get_reg(const struct emul *emul, int reg)
 {
 	struct bb_emul_data *data;
 
@@ -65,39 +62,39 @@ uint32_t bb_emul_get_reg(struct i2c_emul *emul, int reg)
 		return 0;
 	}
 
-	data = BB_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	return data->reg[reg];
 }
 
 /** Check description in emul_bb_retimer.h */
-void bb_emul_set_err_on_ro_write(struct i2c_emul *emul, bool set)
+void bb_emul_set_err_on_ro_write(const struct emul *emul, bool set)
 {
 	struct bb_emul_data *data;
 
-	data = BB_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 	data->error_on_ro_write = set;
 }
 
 /** Check description in emul_bb_retimer.h */
-void bb_emul_set_err_on_rsvd_write(struct i2c_emul *emul, bool set)
+void bb_emul_set_err_on_rsvd_write(const struct emul *emul, bool set)
 {
 	struct bb_emul_data *data;
 
-	data = BB_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 	data->error_on_rsvd_write = set;
 }
 
 /** Mask reserved bits in each register of BB retimer */
 static const uint32_t bb_emul_rsvd_mask[] = {
-	[BB_RETIMER_REG_VENDOR_ID]		= 0x00000000,
-	[BB_RETIMER_REG_DEVICE_ID]		= 0x00000000,
-	[0x02]					= 0xffffffff, /* Reserved */
-	[0x03]					= 0xffffffff, /* Reserved */
-	[BB_RETIMER_REG_CONNECTION_STATE]	= 0xc0201000,
-	[BB_RETIMER_REG_TBT_CONTROL]		= 0xffffdfff,
-	[0x06]					= 0xffffffff, /* Reserved */
-	[BB_RETIMER_REG_EXT_CONNECTION_MODE]	= 0x08007f00,
+	[BB_RETIMER_REG_VENDOR_ID] = 0x00000000,
+	[BB_RETIMER_REG_DEVICE_ID] = 0x00000000,
+	[0x02] = 0xffffffff, /* Reserved */
+	[0x03] = 0xffffffff, /* Reserved */
+	[BB_RETIMER_REG_CONNECTION_STATE] = 0xc0201000,
+	[BB_RETIMER_REG_TBT_CONTROL] = 0xffffdfff,
+	[0x06] = 0xffffffff, /* Reserved */
+	[BB_RETIMER_REG_EXT_CONNECTION_MODE] = 0x08007f00,
 };
 
 /**
@@ -105,20 +102,20 @@ static const uint32_t bb_emul_rsvd_mask[] = {
  *
  * @param emul Pointer to BB retimer emulator
  */
-static void bb_emul_reset(struct i2c_emul *emul)
+static void bb_emul_reset(const struct emul *emul)
 {
 	struct bb_emul_data *data;
 
-	data = BB_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
-	data->reg[BB_RETIMER_REG_VENDOR_ID]		= data->vendor_id;
-	data->reg[BB_RETIMER_REG_DEVICE_ID]		= BB_RETIMER_DEVICE_ID;
-	data->reg[0x02]					= 0x00; /* Reserved */
-	data->reg[0x03]					= 0x00; /* Reserved */
-	data->reg[BB_RETIMER_REG_CONNECTION_STATE]	= 0x00;
-	data->reg[BB_RETIMER_REG_TBT_CONTROL]		= 0x00;
-	data->reg[0x06]					= 0x00; /* Reserved */
-	data->reg[BB_RETIMER_REG_EXT_CONNECTION_MODE]	= 0x00;
+	data->reg[BB_RETIMER_REG_VENDOR_ID] = data->vendor_id;
+	data->reg[BB_RETIMER_REG_DEVICE_ID] = BB_RETIMER_DEVICE_ID;
+	data->reg[0x02] = 0x00; /* Reserved */
+	data->reg[0x03] = 0x00; /* Reserved */
+	data->reg[BB_RETIMER_REG_CONNECTION_STATE] = 0x00;
+	data->reg[BB_RETIMER_REG_TBT_CONTROL] = 0x00;
+	data->reg[0x06] = 0x00; /* Reserved */
+	data->reg[BB_RETIMER_REG_EXT_CONNECTION_MODE] = 0x00;
 }
 
 /**
@@ -133,12 +130,12 @@ static void bb_emul_reset(struct i2c_emul *emul)
  * @return 0 on success
  * @return -EIO on error
  */
-static int bb_emul_handle_write(struct i2c_emul *emul, int reg, int msg_len)
+static int bb_emul_handle_write(const struct emul *emul, int reg, int msg_len)
 {
 	struct bb_emul_data *data;
 	uint32_t val;
 
-	data = BB_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	/* This write only selected register for I2C read message */
 	if (msg_len < 2) {
@@ -155,8 +152,7 @@ static int bb_emul_handle_write(struct i2c_emul *emul, int reg, int msg_len)
 		LOG_WRN("Got %d bytes of WR data, expected 4", msg_len - 2);
 	}
 
-	if (reg <= BB_RETIMER_REG_DEVICE_ID ||
-	    reg >= BB_RETIMER_REG_COUNT ||
+	if (reg <= BB_RETIMER_REG_DEVICE_ID || reg >= BB_RETIMER_REG_COUNT ||
 	    reg == BB_RETIMER_REG_TBT_CONTROL) {
 		if (data->error_on_ro_write) {
 			LOG_ERR("Writing to reg 0x%x which is RO", reg);
@@ -191,11 +187,11 @@ static int bb_emul_handle_write(struct i2c_emul *emul, int reg, int msg_len)
  * @return 0 on success
  * @return -EIO on error
  */
-static int bb_emul_handle_read(struct i2c_emul *emul, int reg)
+static int bb_emul_handle_read(const struct emul *emul, int reg)
 {
 	struct bb_emul_data *data;
 
-	data = BB_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	if (reg >= BB_RETIMER_REG_COUNT) {
 		LOG_ERR("Read unknown register 0x%x", reg);
@@ -219,12 +215,12 @@ static int bb_emul_handle_read(struct i2c_emul *emul, int reg)
  *
  * @return 0 on success
  */
-static int bb_emul_write_byte(struct i2c_emul *emul, int reg, uint8_t val,
+static int bb_emul_write_byte(const struct emul *emul, int reg, uint8_t val,
 			      int bytes)
 {
 	struct bb_emul_data *data;
 
-	data = BB_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	if (bytes == 1) {
 		data->data_dword = 0;
@@ -249,12 +245,12 @@ static int bb_emul_write_byte(struct i2c_emul *emul, int reg, uint8_t val,
  *
  * @return 0 on success
  */
-static int bb_emul_read_byte(struct i2c_emul *emul, int reg, uint8_t *val,
+static int bb_emul_read_byte(const struct emul *emul, int reg, uint8_t *val,
 			     int bytes)
 {
 	struct bb_emul_data *data;
 
-	data = BB_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	/* First byte of read message is read size which is always 4 */
 	if (bytes == 0) {
@@ -279,7 +275,7 @@ static int bb_emul_read_byte(struct i2c_emul *emul, int reg, uint8_t *val,
  *
  * @return Currently accessed register
  */
-static int bb_emul_access_reg(struct i2c_emul *emul, int reg, int bytes,
+static int bb_emul_access_reg(const struct emul *emul, int reg, int bytes,
 			      bool read)
 {
 	return reg;
@@ -298,27 +294,20 @@ static int bb_emul_access_reg(struct i2c_emul *emul, int reg, int bytes,
  *
  * @return 0 indicating success (always)
  */
-static int bb_emul_init(const struct emul *emul,
-			const struct device *parent)
+static int bb_emul_init(const struct emul *emul, const struct device *parent)
 {
-	const struct i2c_common_emul_cfg *cfg = emul->cfg;
-	struct i2c_common_emul_data *data = cfg->data;
-	int ret;
+	struct bb_emul_data *data = emul->data;
 
-	data->emul.api = &i2c_common_emul_api;
-	data->emul.addr = cfg->addr;
-	data->i2c = parent;
-	data->cfg = cfg;
-	i2c_common_emul_init(data);
+	data->common.i2c = parent;
 
-	ret = i2c_emul_register(parent, emul->dev_label, &data->emul);
+	i2c_common_emul_init(&data->common);
 
-	bb_emul_reset(&data->emul);
+	bb_emul_reset(emul);
 
-	return ret;
+	return 0;
 }
 
-#define BB_RETIMER_EMUL(n)						\
+#define BB_RETIMER_EMUL(n)                                          \
 	static struct bb_emul_data bb_emul_data_##n = {			\
 		.vendor_id = DT_STRING_TOKEN(DT_DRV_INST(n), vendor),	\
 		.error_on_ro_write = DT_INST_PROP(n, error_on_ro_write),\
@@ -333,29 +322,22 @@ static int bb_emul_init(const struct emul *emul,
 			.finish_read = NULL,				\
 			.access_reg = bb_emul_access_reg,		\
 		},							\
-	};								\
-									\
-	static const struct i2c_common_emul_cfg bb_emul_cfg_##n = {	\
-		.i2c_label = DT_INST_BUS_LABEL(n),			\
-		.dev_label = DT_INST_LABEL(n),                          \
-		.data = &bb_emul_data_##n.common,			\
-		.addr = DT_INST_REG_ADDR(n),				\
-	};								\
-	EMUL_DEFINE(bb_emul_init, DT_DRV_INST(n), &bb_emul_cfg_##n,	\
-		    &bb_emul_data_##n)
+	};         \
+                                                                    \
+	static const struct i2c_common_emul_cfg bb_emul_cfg_##n = { \
+		.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)),     \
+		.data = &bb_emul_data_##n.common,                   \
+		.addr = DT_INST_REG_ADDR(n),                        \
+	};                                                          \
+	EMUL_DT_INST_DEFINE(n, bb_emul_init, &bb_emul_data_##n,     \
+			    &bb_emul_cfg_##n, &i2c_common_emul_api)
 
 DT_INST_FOREACH_STATUS_OKAY(BB_RETIMER_EMUL)
 
-#define BB_RETIMER_EMUL_CASE(n)					\
-	case DT_INST_DEP_ORD(n): return &bb_emul_data_##n.common.emul;
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
 
-/** Check description in emul_bb_emulator.h */
-struct i2c_emul *bb_emul_get(int ord)
+struct i2c_common_emul_data *
+emul_bb_retimer_get_i2c_common_data(const struct emul *emul)
 {
-	switch (ord) {
-	DT_INST_FOREACH_STATUS_OKAY(BB_RETIMER_EMUL_CASE)
-
-	default:
-		return NULL;
-	}
+	return emul->data;
 }
diff --git a/zephyr/emul/emul_bma255.c b/zephyr/emul/emul_bma255.c
index cd790dbc99..a57c8fbdbb 100644
--- a/zephyr/emul/emul_bma255.c
+++ b/zephyr/emul/emul_bma255.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,10 +18,7 @@ LOG_MODULE_REGISTER(emul_bma255);
 #include "emul/emul_bma255.h"
 
 #include "driver/accel_bma2x2.h"
-
-#define BMA_DATA_FROM_I2C_EMUL(_emul)					     \
-	CONTAINER_OF(CONTAINER_OF(_emul, struct i2c_common_emul_data, emul), \
-		     struct bma_emul_data, common)
+#include "emul/emul_stub_device.h"
 
 /** Run-time data used by the emulator */
 struct bma_emul_data {
@@ -74,7 +71,7 @@ struct bma_emul_data {
 };
 
 /** Check description in emul_bma255.h */
-void bma_emul_set_reg(struct i2c_emul *emul, int reg, uint8_t val)
+void bma_emul_set_reg(const struct emul *emul, int reg, uint8_t val)
 {
 	struct bma_emul_data *data;
 
@@ -82,12 +79,12 @@ void bma_emul_set_reg(struct i2c_emul *emul, int reg, uint8_t val)
 		return;
 	}
 
-	data = BMA_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 	data->reg[reg] = val;
 }
 
 /** Check description in emul_bma255.h */
-uint8_t bma_emul_get_reg(struct i2c_emul *emul, int reg)
+uint8_t bma_emul_get_reg(const struct emul *emul, int reg)
 {
 	struct bma_emul_data *data;
 
@@ -95,7 +92,7 @@ uint8_t bma_emul_get_reg(struct i2c_emul *emul, int reg)
 		return 0;
 	}
 
-	data = BMA_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	return data->reg[reg];
 }
@@ -182,11 +179,11 @@ static uint8_t bma_emul_off_to_nvm(int16_t off)
 }
 
 /** Check description in emul_bma255.h */
-int16_t bma_emul_get_off(struct i2c_emul *emul, int axis)
+int16_t bma_emul_get_off(const struct emul *emul, int axis)
 {
 	struct bma_emul_data *data;
 
-	data = BMA_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	switch (axis) {
 	case BMA_EMUL_AXIS_X:
@@ -201,37 +198,37 @@ int16_t bma_emul_get_off(struct i2c_emul *emul, int axis)
 }
 
 /** Check description in emul_bma255.h */
-void bma_emul_set_off(struct i2c_emul *emul, int axis, int16_t val)
+void bma_emul_set_off(const struct emul *emul, int axis, int16_t val)
 {
 	struct bma_emul_data *data;
 
-	data = BMA_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	switch (axis) {
 	case BMA_EMUL_AXIS_X:
 		data->off_x = val;
-		data->reg[BMA2x2_OFFSET_X_AXIS_ADDR] = bma_emul_off_to_nvm(
-								data->off_x);
+		data->reg[BMA2x2_OFFSET_X_AXIS_ADDR] =
+			bma_emul_off_to_nvm(data->off_x);
 		break;
 	case BMA_EMUL_AXIS_Y:
 		data->off_y = val;
-		data->reg[BMA2x2_OFFSET_Y_AXIS_ADDR] = bma_emul_off_to_nvm(
-								data->off_y);
+		data->reg[BMA2x2_OFFSET_Y_AXIS_ADDR] =
+			bma_emul_off_to_nvm(data->off_y);
 		break;
 	case BMA_EMUL_AXIS_Z:
 		data->off_z = val;
-		data->reg[BMA2x2_OFFSET_Z_AXIS_ADDR] = bma_emul_off_to_nvm(
-								data->off_z);
+		data->reg[BMA2x2_OFFSET_Z_AXIS_ADDR] =
+			bma_emul_off_to_nvm(data->off_z);
 		break;
 	}
 }
 
 /** Check description in emul_bma255.h */
-int16_t bma_emul_get_acc(struct i2c_emul *emul, int axis)
+int16_t bma_emul_get_acc(const struct emul *emul, int axis)
 {
 	struct bma_emul_data *data;
 
-	data = BMA_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	switch (axis) {
 	case BMA_EMUL_AXIS_X:
@@ -246,11 +243,11 @@ int16_t bma_emul_get_acc(struct i2c_emul *emul, int axis)
 }
 
 /** Check description in emul_bma255.h */
-void bma_emul_set_acc(struct i2c_emul *emul, int axis, int16_t val)
+void bma_emul_set_acc(const struct emul *emul, int axis, int16_t val)
 {
 	struct bma_emul_data *data;
 
-	data = BMA_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	switch (axis) {
 	case BMA_EMUL_AXIS_X:
@@ -266,116 +263,116 @@ void bma_emul_set_acc(struct i2c_emul *emul, int axis, int16_t val)
 }
 
 /** Check description in emul_bma255.h */
-void bma_emul_set_err_on_cal_nrdy(struct i2c_emul *emul, bool set)
+void bma_emul_set_err_on_cal_nrdy(const struct emul *emul, bool set)
 {
 	struct bma_emul_data *data;
 
-	data = BMA_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 	data->error_on_cal_trg_nrdy = set;
 }
 
 /** Check description in emul_bma255.h */
-void bma_emul_set_err_on_cal_bad_range(struct i2c_emul *emul, bool set)
+void bma_emul_set_err_on_cal_bad_range(const struct emul *emul, bool set)
 {
 	struct bma_emul_data *data;
 
-	data = BMA_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 	data->error_on_cal_trg_bad_range = set;
 }
 
 /** Check description in emul_bma255.h */
-void bma_emul_set_err_on_ro_write(struct i2c_emul *emul, bool set)
+void bma_emul_set_err_on_ro_write(const struct emul *emul, bool set)
 {
 	struct bma_emul_data *data;
 
-	data = BMA_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 	data->error_on_ro_write = set;
 }
 
 /** Check description in emul_bma255.h */
-void bma_emul_set_err_on_rsvd_write(struct i2c_emul *emul, bool set)
+void bma_emul_set_err_on_rsvd_write(const struct emul *emul, bool set)
 {
 	struct bma_emul_data *data;
 
-	data = BMA_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 	data->error_on_rsvd_write = set;
 }
 
 /** Check description in emul_bma255.h */
-void bma_emul_set_err_on_msb_first(struct i2c_emul *emul, bool set)
+void bma_emul_set_err_on_msb_first(const struct emul *emul, bool set)
 {
 	struct bma_emul_data *data;
 
-	data = BMA_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 	data->error_on_msb_first = set;
 }
 
 /** Mask reserved bits in each register of BMA255 */
 static const uint8_t bma_emul_rsvd_mask[] = {
-	[BMA2x2_CHIP_ID_ADDR]			= 0x00,
-	[0x01]					= 0xff, /* Reserved */
-	[BMA2x2_X_AXIS_LSB_ADDR]		= 0x0e,
-	[BMA2x2_X_AXIS_MSB_ADDR]		= 0x00,
-	[BMA2x2_Y_AXIS_LSB_ADDR]		= 0x0e,
-	[BMA2x2_Y_AXIS_MSB_ADDR]		= 0x00,
-	[BMA2x2_Z_AXIS_LSB_ADDR]		= 0x0e,
-	[BMA2x2_Z_AXIS_MSB_ADDR]		= 0x00,
-	[BMA2x2_TEMP_ADDR]			= 0x00,
-	[BMA2x2_STAT1_ADDR]			= 0x00,
-	[BMA2x2_STAT2_ADDR]			= 0x1f,
-	[BMA2x2_STAT_TAP_SLOPE_ADDR]		= 0x00,
-	[BMA2x2_STAT_ORIENT_HIGH_ADDR]		= 0x00,
-	[0x0d]					= 0xff, /* Reserved */
-	[BMA2x2_STAT_FIFO_ADDR]			= 0x00,
-	[BMA2x2_RANGE_SELECT_ADDR]		= 0xf0,
-	[BMA2x2_BW_SELECT_ADDR]			= 0xe0,
-	[BMA2x2_MODE_CTRL_ADDR]			= 0x01,
-	[BMA2x2_LOW_NOISE_CTRL_ADDR]		= 0x9f,
-	[BMA2x2_DATA_CTRL_ADDR]			= 0x3f,
-	[BMA2x2_RST_ADDR]			= 0x00,
-	[0x15]					= 0xff, /* Reserved */
-	[BMA2x2_INTR_ENABLE1_ADDR]		= 0x08,
-	[BMA2x2_INTR_ENABLE2_ADDR]		= 0x80,
-	[BMA2x2_INTR_SLOW_NO_MOTION_ADDR]	= 0xf0,
-	[BMA2x2_INTR1_PAD_SELECT_ADDR]		= 0x00,
-	[BMA2x2_INTR_DATA_SELECT_ADDR]		= 0x18,
-	[BMA2x2_INTR2_PAD_SELECT_ADDR]		= 0x00,
-	[0x1c]					= 0xff, /* Reserved */
-	[0x1d]					= 0xff, /* Reserved */
-	[BMA2x2_INTR_SOURCE_ADDR]		= 0xc0,
-	[0x1f]					= 0xff, /* Reserved */
-	[BMA2x2_INTR_SET_ADDR]			= 0xf0,
-	[BMA2x2_INTR_CTRL_ADDR]			= 0x70,
-	[BMA2x2_LOW_DURN_ADDR]			= 0x00,
-	[BMA2x2_LOW_THRES_ADDR]			= 0x00,
-	[BMA2x2_LOW_HIGH_HYST_ADDR]		= 0x38,
-	[BMA2x2_HIGH_DURN_ADDR]			= 0x00,
-	[BMA2x2_HIGH_THRES_ADDR]		= 0x00,
-	[BMA2x2_SLOPE_DURN_ADDR]		= 0x00,
-	[BMA2x2_SLOPE_THRES_ADDR]		= 0x00,
-	[BMA2x2_SLOW_NO_MOTION_THRES_ADDR]	= 0x00,
-	[BMA2x2_TAP_PARAM_ADDR]			= 0x38,
-	[BMA2x2_TAP_THRES_ADDR]			= 0x20,
-	[BMA2x2_ORIENT_PARAM_ADDR]		= 0x80,
-	[BMA2x2_THETA_BLOCK_ADDR]		= 0x80,
-	[BMA2x2_THETA_FLAT_ADDR]		= 0xc0,
-	[BMA2x2_FLAT_HOLD_TIME_ADDR]		= 0xc8,
-	[BMA2x2_FIFO_WML_TRIG]			= 0xc0,
-	[0x31]					= 0xff, /* Reserved */
-	[BMA2x2_SELFTEST_ADDR]			= 0xf8,
-	[BMA2x2_EEPROM_CTRL_ADDR]		= 0x00,
-	[BMA2x2_SERIAL_CTRL_ADDR]		= 0xf8,
-	[0x35]					= 0xff, /* Reserved */
-	[BMA2x2_OFFSET_CTRL_ADDR]		= 0x08,
-	[BMA2x2_OFC_SETTING_ADDR]		= 0x80,
-	[BMA2x2_OFFSET_X_AXIS_ADDR]		= 0x00,
-	[BMA2x2_OFFSET_Y_AXIS_ADDR]		= 0x00,
-	[BMA2x2_OFFSET_Z_AXIS_ADDR]		= 0x00,
-	[BMA2x2_GP0_ADDR]			= 0x00,
-	[BMA2x2_GP1_ADDR]			= 0x00,
-	[0x3d]					= 0xff, /* Reserved */
-	[BMA2x2_FIFO_MODE_ADDR]			= 0x3c,
-	[BMA2x2_FIFO_DATA_OUTPUT_ADDR]		= 0x00,
+	[BMA2x2_CHIP_ID_ADDR] = 0x00,
+	[0x01] = 0xff, /* Reserved */
+	[BMA2x2_X_AXIS_LSB_ADDR] = 0x0e,
+	[BMA2x2_X_AXIS_MSB_ADDR] = 0x00,
+	[BMA2x2_Y_AXIS_LSB_ADDR] = 0x0e,
+	[BMA2x2_Y_AXIS_MSB_ADDR] = 0x00,
+	[BMA2x2_Z_AXIS_LSB_ADDR] = 0x0e,
+	[BMA2x2_Z_AXIS_MSB_ADDR] = 0x00,
+	[BMA2x2_TEMP_ADDR] = 0x00,
+	[BMA2x2_STAT1_ADDR] = 0x00,
+	[BMA2x2_STAT2_ADDR] = 0x1f,
+	[BMA2x2_STAT_TAP_SLOPE_ADDR] = 0x00,
+	[BMA2x2_STAT_ORIENT_HIGH_ADDR] = 0x00,
+	[0x0d] = 0xff, /* Reserved */
+	[BMA2x2_STAT_FIFO_ADDR] = 0x00,
+	[BMA2x2_RANGE_SELECT_ADDR] = 0xf0,
+	[BMA2x2_BW_SELECT_ADDR] = 0xe0,
+	[BMA2x2_MODE_CTRL_ADDR] = 0x01,
+	[BMA2x2_LOW_NOISE_CTRL_ADDR] = 0x9f,
+	[BMA2x2_DATA_CTRL_ADDR] = 0x3f,
+	[BMA2x2_RST_ADDR] = 0x00,
+	[0x15] = 0xff, /* Reserved */
+	[BMA2x2_INTR_ENABLE1_ADDR] = 0x08,
+	[BMA2x2_INTR_ENABLE2_ADDR] = 0x80,
+	[BMA2x2_INTR_SLOW_NO_MOTION_ADDR] = 0xf0,
+	[BMA2x2_INTR1_PAD_SELECT_ADDR] = 0x00,
+	[BMA2x2_INTR_DATA_SELECT_ADDR] = 0x18,
+	[BMA2x2_INTR2_PAD_SELECT_ADDR] = 0x00,
+	[0x1c] = 0xff, /* Reserved */
+	[0x1d] = 0xff, /* Reserved */
+	[BMA2x2_INTR_SOURCE_ADDR] = 0xc0,
+	[0x1f] = 0xff, /* Reserved */
+	[BMA2x2_INTR_SET_ADDR] = 0xf0,
+	[BMA2x2_INTR_CTRL_ADDR] = 0x70,
+	[BMA2x2_LOW_DURN_ADDR] = 0x00,
+	[BMA2x2_LOW_THRES_ADDR] = 0x00,
+	[BMA2x2_LOW_HIGH_HYST_ADDR] = 0x38,
+	[BMA2x2_HIGH_DURN_ADDR] = 0x00,
+	[BMA2x2_HIGH_THRES_ADDR] = 0x00,
+	[BMA2x2_SLOPE_DURN_ADDR] = 0x00,
+	[BMA2x2_SLOPE_THRES_ADDR] = 0x00,
+	[BMA2x2_SLOW_NO_MOTION_THRES_ADDR] = 0x00,
+	[BMA2x2_TAP_PARAM_ADDR] = 0x38,
+	[BMA2x2_TAP_THRES_ADDR] = 0x20,
+	[BMA2x2_ORIENT_PARAM_ADDR] = 0x80,
+	[BMA2x2_THETA_BLOCK_ADDR] = 0x80,
+	[BMA2x2_THETA_FLAT_ADDR] = 0xc0,
+	[BMA2x2_FLAT_HOLD_TIME_ADDR] = 0xc8,
+	[BMA2x2_FIFO_WML_TRIG] = 0xc0,
+	[0x31] = 0xff, /* Reserved */
+	[BMA2x2_SELFTEST_ADDR] = 0xf8,
+	[BMA2x2_EEPROM_CTRL_ADDR] = 0x00,
+	[BMA2x2_SERIAL_CTRL_ADDR] = 0xf8,
+	[0x35] = 0xff, /* Reserved */
+	[BMA2x2_OFFSET_CTRL_ADDR] = 0x08,
+	[BMA2x2_OFC_SETTING_ADDR] = 0x80,
+	[BMA2x2_OFFSET_X_AXIS_ADDR] = 0x00,
+	[BMA2x2_OFFSET_Y_AXIS_ADDR] = 0x00,
+	[BMA2x2_OFFSET_Z_AXIS_ADDR] = 0x00,
+	[BMA2x2_GP0_ADDR] = 0x00,
+	[BMA2x2_GP1_ADDR] = 0x00,
+	[0x3d] = 0xff, /* Reserved */
+	[BMA2x2_FIFO_MODE_ADDR] = 0x3c,
+	[BMA2x2_FIFO_DATA_OUTPUT_ADDR] = 0x00,
 };
 
 /**
@@ -384,11 +381,11 @@ static const uint8_t bma_emul_rsvd_mask[] = {
  *
  * @param emul Pointer to BMA255 emulator
  */
-static void bma_emul_restore_nvm(struct i2c_emul *emul)
+static void bma_emul_restore_nvm(const struct emul *emul)
 {
 	struct bma_emul_data *data;
 
-	data = BMA_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	/* Restore registers values */
 	data->reg[BMA2x2_OFFSET_X_AXIS_ADDR] = data->nvm_x;
@@ -408,71 +405,71 @@ static void bma_emul_restore_nvm(struct i2c_emul *emul)
  *
  * @param emul Pointer to BMA255 emulator
  */
-static void bma_emul_reset(struct i2c_emul *emul)
+static void bma_emul_reset(const struct emul *emul)
 {
 	struct bma_emul_data *data;
 
-	data = BMA_DATA_FROM_I2C_EMUL(emul);
-
-	data->reg[BMA2x2_CHIP_ID_ADDR]			= 0xfa;
-	data->reg[0x01]					= 0x00; /* Reserved */
-	data->reg[BMA2x2_X_AXIS_LSB_ADDR]		= 0x00;
-	data->reg[BMA2x2_X_AXIS_MSB_ADDR]		= 0x00;
-	data->reg[BMA2x2_Y_AXIS_LSB_ADDR]		= 0x00;
-	data->reg[BMA2x2_Y_AXIS_MSB_ADDR]		= 0x00;
-	data->reg[BMA2x2_Z_AXIS_LSB_ADDR]		= 0x00;
-	data->reg[BMA2x2_Z_AXIS_MSB_ADDR]		= 0x00;
-	data->reg[BMA2x2_TEMP_ADDR]			= 0x00;
-	data->reg[BMA2x2_STAT1_ADDR]			= 0x00;
-	data->reg[BMA2x2_STAT2_ADDR]			= 0x00;
-	data->reg[BMA2x2_STAT_TAP_SLOPE_ADDR]		= 0x00;
-	data->reg[BMA2x2_STAT_ORIENT_HIGH_ADDR]		= 0x00;
-	data->reg[0x0d]					= 0xff; /* Reserved */
-	data->reg[BMA2x2_STAT_FIFO_ADDR]		= 0x00;
-	data->reg[BMA2x2_RANGE_SELECT_ADDR]		= 0x03;
-	data->reg[BMA2x2_BW_SELECT_ADDR]		= 0x0f;
-	data->reg[BMA2x2_MODE_CTRL_ADDR]		= 0x00;
-	data->reg[BMA2x2_LOW_NOISE_CTRL_ADDR]		= 0x00;
-	data->reg[BMA2x2_DATA_CTRL_ADDR]		= 0x00;
-	data->reg[BMA2x2_RST_ADDR]			= 0x00;
-	data->reg[0x15]					= 0xff; /* Reserved */
-	data->reg[BMA2x2_INTR_ENABLE1_ADDR]		= 0x00;
-	data->reg[BMA2x2_INTR_ENABLE2_ADDR]		= 0x00;
-	data->reg[BMA2x2_INTR_SLOW_NO_MOTION_ADDR]	= 0x00;
-	data->reg[BMA2x2_INTR1_PAD_SELECT_ADDR]		= 0x00;
-	data->reg[BMA2x2_INTR_DATA_SELECT_ADDR]		= 0x00;
-	data->reg[BMA2x2_INTR2_PAD_SELECT_ADDR]		= 0x00;
-	data->reg[0x1c]					= 0xff; /* Reserved */
-	data->reg[0x1d]					= 0xff; /* Reserved */
-	data->reg[BMA2x2_INTR_SOURCE_ADDR]		= 0x00;
-	data->reg[0x1f]					= 0xff; /* Reserved */
-	data->reg[BMA2x2_INTR_SET_ADDR]			= 0x05;
-	data->reg[BMA2x2_INTR_CTRL_ADDR]		= 0x00;
-	data->reg[BMA2x2_LOW_DURN_ADDR]			= 0x09;
-	data->reg[BMA2x2_LOW_THRES_ADDR]		= 0x30;
-	data->reg[BMA2x2_LOW_HIGH_HYST_ADDR]		= 0x81;
-	data->reg[BMA2x2_HIGH_DURN_ADDR]		= 0x0f;
-	data->reg[BMA2x2_HIGH_THRES_ADDR]		= 0xc0;
-	data->reg[BMA2x2_SLOPE_DURN_ADDR]		= 0x00;
-	data->reg[BMA2x2_SLOPE_THRES_ADDR]		= 0x14;
-	data->reg[BMA2x2_SLOW_NO_MOTION_THRES_ADDR]	= 0x14;
-	data->reg[BMA2x2_TAP_PARAM_ADDR]		= 0x04;
-	data->reg[BMA2x2_TAP_THRES_ADDR]		= 0x0a;
-	data->reg[BMA2x2_ORIENT_PARAM_ADDR]		= 0x18;
-	data->reg[BMA2x2_THETA_BLOCK_ADDR]		= 0x48;
-	data->reg[BMA2x2_THETA_FLAT_ADDR]		= 0x08;
-	data->reg[BMA2x2_FLAT_HOLD_TIME_ADDR]		= 0x11;
-	data->reg[BMA2x2_FIFO_WML_TRIG]			= 0x00;
-	data->reg[0x31]					= 0xff; /* Reserved */
-	data->reg[BMA2x2_SELFTEST_ADDR]			= 0x00;
-	data->reg[BMA2x2_EEPROM_CTRL_ADDR]		= 0xf0;
-	data->reg[BMA2x2_SERIAL_CTRL_ADDR]		= 0x00;
-	data->reg[0x35]					= 0x00; /* Reserved */
-	data->reg[BMA2x2_OFFSET_CTRL_ADDR]		= 0x10;
-	data->reg[BMA2x2_OFC_SETTING_ADDR]		= 0x00;
-	data->reg[0x3d]					= 0xff; /* Reserved */
-	data->reg[BMA2x2_FIFO_MODE_ADDR]		= 0x00;
-	data->reg[BMA2x2_FIFO_DATA_OUTPUT_ADDR]		= 0x00;
+	data = emul->data;
+
+	data->reg[BMA2x2_CHIP_ID_ADDR] = 0xfa;
+	data->reg[0x01] = 0x00; /* Reserved */
+	data->reg[BMA2x2_X_AXIS_LSB_ADDR] = 0x00;
+	data->reg[BMA2x2_X_AXIS_MSB_ADDR] = 0x00;
+	data->reg[BMA2x2_Y_AXIS_LSB_ADDR] = 0x00;
+	data->reg[BMA2x2_Y_AXIS_MSB_ADDR] = 0x00;
+	data->reg[BMA2x2_Z_AXIS_LSB_ADDR] = 0x00;
+	data->reg[BMA2x2_Z_AXIS_MSB_ADDR] = 0x00;
+	data->reg[BMA2x2_TEMP_ADDR] = 0x00;
+	data->reg[BMA2x2_STAT1_ADDR] = 0x00;
+	data->reg[BMA2x2_STAT2_ADDR] = 0x00;
+	data->reg[BMA2x2_STAT_TAP_SLOPE_ADDR] = 0x00;
+	data->reg[BMA2x2_STAT_ORIENT_HIGH_ADDR] = 0x00;
+	data->reg[0x0d] = 0xff; /* Reserved */
+	data->reg[BMA2x2_STAT_FIFO_ADDR] = 0x00;
+	data->reg[BMA2x2_RANGE_SELECT_ADDR] = 0x03;
+	data->reg[BMA2x2_BW_SELECT_ADDR] = 0x0f;
+	data->reg[BMA2x2_MODE_CTRL_ADDR] = 0x00;
+	data->reg[BMA2x2_LOW_NOISE_CTRL_ADDR] = 0x00;
+	data->reg[BMA2x2_DATA_CTRL_ADDR] = 0x00;
+	data->reg[BMA2x2_RST_ADDR] = 0x00;
+	data->reg[0x15] = 0xff; /* Reserved */
+	data->reg[BMA2x2_INTR_ENABLE1_ADDR] = 0x00;
+	data->reg[BMA2x2_INTR_ENABLE2_ADDR] = 0x00;
+	data->reg[BMA2x2_INTR_SLOW_NO_MOTION_ADDR] = 0x00;
+	data->reg[BMA2x2_INTR1_PAD_SELECT_ADDR] = 0x00;
+	data->reg[BMA2x2_INTR_DATA_SELECT_ADDR] = 0x00;
+	data->reg[BMA2x2_INTR2_PAD_SELECT_ADDR] = 0x00;
+	data->reg[0x1c] = 0xff; /* Reserved */
+	data->reg[0x1d] = 0xff; /* Reserved */
+	data->reg[BMA2x2_INTR_SOURCE_ADDR] = 0x00;
+	data->reg[0x1f] = 0xff; /* Reserved */
+	data->reg[BMA2x2_INTR_SET_ADDR] = 0x05;
+	data->reg[BMA2x2_INTR_CTRL_ADDR] = 0x00;
+	data->reg[BMA2x2_LOW_DURN_ADDR] = 0x09;
+	data->reg[BMA2x2_LOW_THRES_ADDR] = 0x30;
+	data->reg[BMA2x2_LOW_HIGH_HYST_ADDR] = 0x81;
+	data->reg[BMA2x2_HIGH_DURN_ADDR] = 0x0f;
+	data->reg[BMA2x2_HIGH_THRES_ADDR] = 0xc0;
+	data->reg[BMA2x2_SLOPE_DURN_ADDR] = 0x00;
+	data->reg[BMA2x2_SLOPE_THRES_ADDR] = 0x14;
+	data->reg[BMA2x2_SLOW_NO_MOTION_THRES_ADDR] = 0x14;
+	data->reg[BMA2x2_TAP_PARAM_ADDR] = 0x04;
+	data->reg[BMA2x2_TAP_THRES_ADDR] = 0x0a;
+	data->reg[BMA2x2_ORIENT_PARAM_ADDR] = 0x18;
+	data->reg[BMA2x2_THETA_BLOCK_ADDR] = 0x48;
+	data->reg[BMA2x2_THETA_FLAT_ADDR] = 0x08;
+	data->reg[BMA2x2_FLAT_HOLD_TIME_ADDR] = 0x11;
+	data->reg[BMA2x2_FIFO_WML_TRIG] = 0x00;
+	data->reg[0x31] = 0xff; /* Reserved */
+	data->reg[BMA2x2_SELFTEST_ADDR] = 0x00;
+	data->reg[BMA2x2_EEPROM_CTRL_ADDR] = 0xf0;
+	data->reg[BMA2x2_SERIAL_CTRL_ADDR] = 0x00;
+	data->reg[0x35] = 0x00; /* Reserved */
+	data->reg[BMA2x2_OFFSET_CTRL_ADDR] = 0x10;
+	data->reg[BMA2x2_OFC_SETTING_ADDR] = 0x00;
+	data->reg[0x3d] = 0xff; /* Reserved */
+	data->reg[BMA2x2_FIFO_MODE_ADDR] = 0x00;
+	data->reg[BMA2x2_FIFO_DATA_OUTPUT_ADDR] = 0x00;
 
 	/* Restore registers backed in NVM */
 	bma_emul_restore_nvm(emul);
@@ -514,12 +511,12 @@ static int bma_emul_range_to_shift(uint8_t range)
  *
  * @return 0 on success
  */
-static int bma_emul_handle_nvm_write(struct i2c_emul *emul, uint8_t val)
+static int bma_emul_handle_nvm_write(const struct emul *emul, uint8_t val)
 {
 	struct bma_emul_data *data;
 	uint8_t writes_rem;
 
-	data = BMA_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	/* NVM not ready, ignore write/load requests */
 	if (!(data->reg[BMA2x2_EEPROM_CTRL_ADDR] & BMA2x2_EEPROM_RDY)) {
@@ -532,7 +529,8 @@ static int bma_emul_handle_nvm_write(struct i2c_emul *emul, uint8_t val)
 	}
 
 	writes_rem = (data->reg[BMA2x2_EEPROM_CTRL_ADDR] &
-		      BMA2x2_EEPROM_REMAIN_MSK) >> BMA2x2_EEPROM_REMAIN_OFF;
+		      BMA2x2_EEPROM_REMAIN_MSK) >>
+		     BMA2x2_EEPROM_REMAIN_OFF;
 	/* Trigger write is set, write is unlocked and writes remaining */
 	if (val & BMA2x2_EEPROM_PROG &&
 	    data->reg[BMA2x2_EEPROM_CTRL_ADDR] & BMA2x2_EEPROM_PROG_EN &&
@@ -544,10 +542,9 @@ static int bma_emul_handle_nvm_write(struct i2c_emul *emul, uint8_t val)
 		data->nvm_gp1 = data->reg[BMA2x2_GP1_ADDR];
 		/* Decrement number of remaining writes and save it in reg */
 		writes_rem--;
-		data->reg[BMA2x2_EEPROM_CTRL_ADDR] &=
-					~BMA2x2_EEPROM_REMAIN_MSK;
+		data->reg[BMA2x2_EEPROM_CTRL_ADDR] &= ~BMA2x2_EEPROM_REMAIN_MSK;
 		data->reg[BMA2x2_EEPROM_CTRL_ADDR] |=
-					writes_rem << BMA2x2_EEPROM_REMAIN_OFF;
+			writes_rem << BMA2x2_EEPROM_REMAIN_OFF;
 	}
 
 	return 0;
@@ -558,16 +555,16 @@ static int bma_emul_handle_nvm_write(struct i2c_emul *emul, uint8_t val)
  *
  * @param emul Pointer to BMA255 emulator
  */
-static void bma_emul_clear_int(struct i2c_emul *emul)
+static void bma_emul_clear_int(const struct emul *emul)
 {
 	struct bma_emul_data *data;
 
-	data = BMA_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
-	data->reg[BMA2x2_STAT1_ADDR]		= 0x00;
-	data->reg[BMA2x2_STAT2_ADDR]		= 0x00;
-	data->reg[BMA2x2_STAT_TAP_SLOPE_ADDR]	= 0x00;
-	data->reg[BMA2x2_STAT_ORIENT_HIGH_ADDR]	= 0x00;
+	data->reg[BMA2x2_STAT1_ADDR] = 0x00;
+	data->reg[BMA2x2_STAT2_ADDR] = 0x00;
+	data->reg[BMA2x2_STAT_TAP_SLOPE_ADDR] = 0x00;
+	data->reg[BMA2x2_STAT_ORIENT_HIGH_ADDR] = 0x00;
 }
 
 /**
@@ -579,12 +576,12 @@ static void bma_emul_clear_int(struct i2c_emul *emul)
  *
  * @return target Value to which offset compensation should be calculated
  */
-static int16_t bma_emul_get_target(struct i2c_emul *emul, int axis)
+static int16_t bma_emul_get_target(const struct emul *emul, int axis)
 {
 	struct bma_emul_data *data;
 	uint8_t target;
 
-	data = BMA_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	target = data->reg[BMA2x2_OFC_SETTING_ADDR] >>
 		 BMA2x2_OFC_TARGET_AXIS(axis);
@@ -614,13 +611,13 @@ static int16_t bma_emul_get_target(struct i2c_emul *emul, int axis)
  * @return 0 on success
  * @return -EIO when trying to start fast compensation in wrong emulator state
  */
-static int bma_emul_handle_off_comp(struct i2c_emul *emul, uint8_t val)
+static int bma_emul_handle_off_comp(const struct emul *emul, uint8_t val)
 {
 	struct bma_emul_data *data;
 	uint8_t trigger;
 	int16_t target;
 
-	data = BMA_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	if (val & BMA2x2_OFFSET_RESET) {
 		data->off_x = 0;
@@ -631,7 +628,6 @@ static int bma_emul_handle_off_comp(struct i2c_emul *emul, uint8_t val)
 		data->reg[BMA2x2_OFFSET_Z_AXIS_ADDR] = 0;
 	}
 
-
 	trigger = (val & BMA2x2_OFFSET_TRIGGER_MASK) >>
 		  BMA2x2_OFFSET_TRIGGER_OFF;
 
@@ -681,13 +677,13 @@ static int bma_emul_handle_off_comp(struct i2c_emul *emul, uint8_t val)
  * @return 0 on success
  * @return -EIO on error
  */
-static int bma_emul_handle_write(struct i2c_emul *emul, int reg, int bytes)
+static int bma_emul_handle_write(const struct emul *emul, int reg, int bytes)
 {
 	struct bma_emul_data *data;
 	uint8_t val;
 	int ret;
 
-	data = BMA_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	val = data->write_byte;
 
@@ -717,7 +713,6 @@ static int bma_emul_handle_write(struct i2c_emul *emul, int reg, int bytes)
 		return -EIO;
 	}
 
-
 	switch (reg) {
 	case BMA2x2_RST_ADDR:
 		if (val == BMA2x2_CMD_SOFT_RESET) {
@@ -745,9 +740,9 @@ static int bma_emul_handle_write(struct i2c_emul *emul, int reg, int bytes)
 		/* Only slow compensation bits are RW */
 		val &= BMA2x2_OFFSET_CAL_SLOW_X | BMA2x2_OFFSET_CAL_SLOW_Y |
 		       BMA2x2_OFFSET_CAL_SLOW_Z;
-		val |= data->reg[reg] & ~(BMA2x2_OFFSET_CAL_SLOW_X |
-					  BMA2x2_OFFSET_CAL_SLOW_Y |
-					  BMA2x2_OFFSET_CAL_SLOW_Z);
+		val |= data->reg[reg] &
+		       ~(BMA2x2_OFFSET_CAL_SLOW_X | BMA2x2_OFFSET_CAL_SLOW_Y |
+			 BMA2x2_OFFSET_CAL_SLOW_Z);
 		break;
 	/* Change internal offset to value set in I2C message */
 	case BMA2x2_OFFSET_X_AXIS_ADDR:
@@ -793,7 +788,7 @@ static int bma_emul_handle_write(struct i2c_emul *emul, int reg, int bytes)
  * @return 0 on success
  * @return -EIO when accessing MSB before LSB with enabled shadowing
  */
-static int bma_emul_get_acc_val(struct i2c_emul *emul, int lsb_reg,
+static int bma_emul_get_acc_val(const struct emul *emul, int lsb_reg,
 				bool *lsb_read, bool lsb, int16_t val)
 {
 	struct bma_emul_data *data;
@@ -802,7 +797,7 @@ static int bma_emul_get_acc_val(struct i2c_emul *emul, int lsb_reg,
 	int msb_reg;
 	int shift;
 
-	data = BMA_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	if (lsb) {
 		*lsb_read = 1;
@@ -837,7 +832,7 @@ static int bma_emul_get_acc_val(struct i2c_emul *emul, int lsb_reg,
 }
 
 /** Check description in emul_bma255.h */
-int bma_emul_access_reg(struct i2c_emul *emul, int reg, int bytes, bool read)
+int bma_emul_access_reg(const struct emul *emul, int reg, int bytes, bool read)
 {
 	/*
 	 * Exclude first byte (select register) from total number of bytes
@@ -868,13 +863,13 @@ int bma_emul_access_reg(struct i2c_emul *emul, int reg, int bytes, bool read)
  * @return 0 on success
  * @return -EIO on error
  */
-static int bma_emul_handle_read(struct i2c_emul *emul, int reg, uint8_t *val,
+static int bma_emul_handle_read(const struct emul *emul, int reg, uint8_t *val,
 				int bytes)
 {
 	struct bma_emul_data *data;
 	int ret;
 
-	data = BMA_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	reg = bma_emul_access_reg(emul, reg, bytes, true /* = read */);
 
@@ -936,12 +931,12 @@ static int bma_emul_handle_read(struct i2c_emul *emul, int reg, uint8_t *val,
  * @return 0 on success
  * @return -EIO on error
  */
-static int bma_emul_write_byte(struct i2c_emul *emul, int reg, uint8_t val,
+static int bma_emul_write_byte(const struct emul *emul, int reg, uint8_t val,
 			       int bytes)
 {
 	struct bma_emul_data *data;
 
-	data = BMA_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	data->write_byte = val;
 
@@ -961,27 +956,20 @@ static int bma_emul_write_byte(struct i2c_emul *emul, int reg, uint8_t val,
  *
  * @return 0 indicating success (always)
  */
-static int bma_emul_init(const struct emul *emul,
-			 const struct device *parent)
+static int bma_emul_init(const struct emul *emul, const struct device *parent)
 {
-	const struct i2c_common_emul_cfg *cfg = emul->cfg;
-	struct i2c_common_emul_data *data = cfg->data;
-	int ret;
+	struct bma_emul_data *data = emul->data;
 
-	data->emul.api = &i2c_common_emul_api;
-	data->emul.addr = cfg->addr;
-	data->i2c = parent;
-	data->cfg = cfg;
-	i2c_common_emul_init(data);
+	data->common.i2c = parent;
 
-	ret = i2c_emul_register(parent, emul->dev_label, &data->emul);
+	i2c_common_emul_init(&data->common);
 
-	bma_emul_reset(&data->emul);
+	bma_emul_reset(emul);
 
-	return ret;
+	return 0;
 }
 
-#define BMA255_EMUL(n)							\
+#define BMA255_EMUL(n)                                               \
 	static struct bma_emul_data bma_emul_data_##n = {		\
 		.nvm_x = DT_INST_PROP(n, nvm_off_x),			\
 		.nvm_y = DT_INST_PROP(n, nvm_off_y),			\
@@ -1010,29 +998,22 @@ static int bma_emul_init(const struct emul *emul,
 			.finish_read = NULL,				\
 			.access_reg = bma_emul_access_reg,		\
 		},							\
-	};								\
-									\
-	static const struct i2c_common_emul_cfg bma_emul_cfg_##n = {	\
-		.i2c_label = DT_INST_BUS_LABEL(n),			\
-		.dev_label = DT_INST_LABEL(n),                          \
-		.data = &bma_emul_data_##n.common,			\
-		.addr = DT_INST_REG_ADDR(n),				\
-	};								\
-	EMUL_DEFINE(bma_emul_init, DT_DRV_INST(n), &bma_emul_cfg_##n,	\
-		    &bma_emul_data_##n)
+	};         \
+                                                                     \
+	static const struct i2c_common_emul_cfg bma_emul_cfg_##n = { \
+		.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)),      \
+		.data = &bma_emul_data_##n.common,                   \
+		.addr = DT_INST_REG_ADDR(n),                         \
+	};                                                           \
+	EMUL_DT_INST_DEFINE(n, bma_emul_init, &bma_emul_data_##n,    \
+			    &bma_emul_cfg_##n, &i2c_common_emul_api)
 
 DT_INST_FOREACH_STATUS_OKAY(BMA255_EMUL)
 
-#define BMA255_EMUL_CASE(n)					\
-	case DT_INST_DEP_ORD(n): return &bma_emul_data_##n.common.emul;
-
-/** Check description in emul_bma255.h */
-struct i2c_emul *bma_emul_get(int ord)
+struct i2c_common_emul_data *
+emul_bma_get_i2c_common_data(const struct emul *emul)
 {
-	switch (ord) {
-	DT_INST_FOREACH_STATUS_OKAY(BMA255_EMUL_CASE)
-
-	default:
-		return NULL;
-	}
+	return emul->data;
 }
+
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
diff --git a/zephyr/emul/emul_bmi.c b/zephyr/emul/emul_bmi.c
index 37dba43e6d..fe46428f01 100644
--- a/zephyr/emul/emul_bmi.c
+++ b/zephyr/emul/emul_bmi.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,18 +13,16 @@ LOG_MODULE_REGISTER(emul_bmi);
 #include <zephyr/drivers/emul.h>
 #include <zephyr/drivers/i2c.h>
 #include <zephyr/drivers/i2c_emul.h>
+#include <zephyr/sys/__assert.h>
 
 #include "emul/emul_common_i2c.h"
 #include "emul/emul_bmi.h"
+#include "emul/emul_stub_device.h"
 
 #include "driver/accelgyro_bmi160.h"
 #include "driver/accelgyro_bmi260.h"
 #include "driver/accelgyro_bmi_common.h"
 
-#define BMI_DATA_FROM_I2C_EMUL(_emul)					     \
-	CONTAINER_OF(CONTAINER_OF(_emul, struct i2c_common_emul_data, emul), \
-		     struct bmi_emul_data, common)
-
 /** Run-time data used by the emulator */
 struct bmi_emul_data {
 	/** Common I2C data */
@@ -87,7 +85,7 @@ struct bmi_emul_data {
 };
 
 /** Check description in emul_bmi.h */
-void bmi_emul_set_reg(struct i2c_emul *emul, int reg, uint8_t val)
+void bmi_emul_set_reg(const struct emul *emul, int reg, uint8_t val)
 {
 	struct bmi_emul_data *data;
 
@@ -95,12 +93,12 @@ void bmi_emul_set_reg(struct i2c_emul *emul, int reg, uint8_t val)
 		return;
 	}
 
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 	data->reg[reg] = val;
 }
 
 /** Check description in emul_bmi.h */
-uint8_t bmi_emul_get_reg(struct i2c_emul *emul, int reg)
+uint8_t bmi_emul_get_reg(const struct emul *emul, int reg)
 {
 	struct bmi_emul_data *data;
 
@@ -108,7 +106,7 @@ uint8_t bmi_emul_get_reg(struct i2c_emul *emul, int reg)
 		return 0;
 	}
 
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	return data->reg[reg];
 }
@@ -258,11 +256,11 @@ static uint16_t bmi_emul_gyr_off_to_nvm(int16_t off)
 }
 
 /** Check description in emul_bmi.h */
-int16_t bmi_emul_get_off(struct i2c_emul *emul, enum bmi_emul_axis axis)
+int16_t bmi_emul_get_off(const struct emul *emul, enum bmi_emul_axis axis)
 {
 	struct bmi_emul_data *data;
 
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	switch (axis) {
 	case BMI_EMUL_ACC_X:
@@ -283,30 +281,30 @@ int16_t bmi_emul_get_off(struct i2c_emul *emul, enum bmi_emul_axis axis)
 }
 
 /** Check description in emul_bmi.h */
-void bmi_emul_set_off(struct i2c_emul *emul, enum bmi_emul_axis axis,
+void bmi_emul_set_off(const struct emul *emul, enum bmi_emul_axis axis,
 		      int16_t val)
 {
 	struct bmi_emul_data *data;
 	uint16_t gyr_off;
 	uint8_t gyr98_shift;
 
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	switch (axis) {
 	case BMI_EMUL_ACC_X:
 		data->off_acc_x = val;
 		data->reg[data->type_data->acc_off_reg] =
-				bmi_emul_acc_off_to_nvm(data->off_acc_x);
+			bmi_emul_acc_off_to_nvm(data->off_acc_x);
 		break;
 	case BMI_EMUL_ACC_Y:
 		data->off_acc_y = val;
 		data->reg[data->type_data->acc_off_reg + 1] =
-				bmi_emul_acc_off_to_nvm(data->off_acc_y);
+			bmi_emul_acc_off_to_nvm(data->off_acc_y);
 		break;
 	case BMI_EMUL_ACC_Z:
 		data->off_acc_z = val;
 		data->reg[data->type_data->acc_off_reg + 2] =
-				bmi_emul_acc_off_to_nvm(data->off_acc_z);
+			bmi_emul_acc_off_to_nvm(data->off_acc_z);
 		break;
 	case BMI_EMUL_GYR_X:
 		data->off_gyr_x = val;
@@ -314,9 +312,9 @@ void bmi_emul_set_off(struct i2c_emul *emul, enum bmi_emul_axis axis,
 		data->reg[data->type_data->gyr_off_reg] = gyr_off & 0xff;
 		gyr98_shift = 0;
 		data->reg[data->type_data->gyr98_off_reg] &=
-				~(0x3 << gyr98_shift);
+			~(0x3 << gyr98_shift);
 		data->reg[data->type_data->gyr98_off_reg] |=
-				(gyr_off & 0x300) >> (8 - gyr98_shift);
+			(gyr_off & 0x300) >> (8 - gyr98_shift);
 		break;
 	case BMI_EMUL_GYR_Y:
 		data->off_gyr_y = val;
@@ -324,9 +322,9 @@ void bmi_emul_set_off(struct i2c_emul *emul, enum bmi_emul_axis axis,
 		data->reg[data->type_data->gyr_off_reg + 1] = gyr_off & 0xff;
 		gyr98_shift = 2;
 		data->reg[data->type_data->gyr98_off_reg] &=
-				~(0x3 << gyr98_shift);
+			~(0x3 << gyr98_shift);
 		data->reg[data->type_data->gyr98_off_reg] |=
-				(gyr_off & 0x300) >> (8 - gyr98_shift);
+			(gyr_off & 0x300) >> (8 - gyr98_shift);
 		break;
 	case BMI_EMUL_GYR_Z:
 		data->off_gyr_z = val;
@@ -334,19 +332,19 @@ void bmi_emul_set_off(struct i2c_emul *emul, enum bmi_emul_axis axis,
 		data->reg[data->type_data->gyr_off_reg + 2] = gyr_off & 0xff;
 		gyr98_shift = 4;
 		data->reg[data->type_data->gyr98_off_reg] &=
-				~(0x3 << gyr98_shift);
+			~(0x3 << gyr98_shift);
 		data->reg[data->type_data->gyr98_off_reg] |=
-				(gyr_off & 0x300) >> (8 - gyr98_shift);
+			(gyr_off & 0x300) >> (8 - gyr98_shift);
 		break;
 	}
 }
 
 /** Check description in emul_bmi.h */
-int32_t bmi_emul_get_value(struct i2c_emul *emul, enum bmi_emul_axis axis)
+int32_t bmi_emul_get_value(const struct emul *emul, enum bmi_emul_axis axis)
 {
 	struct bmi_emul_data *data;
 
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	switch (axis) {
 	case BMI_EMUL_ACC_X:
@@ -367,12 +365,12 @@ int32_t bmi_emul_get_value(struct i2c_emul *emul, enum bmi_emul_axis axis)
 }
 
 /** Check description in emul_bmi.h */
-void bmi_emul_set_value(struct i2c_emul *emul, enum bmi_emul_axis axis,
+void bmi_emul_set_value(const struct emul *emul, enum bmi_emul_axis axis,
 			int32_t val)
 {
 	struct bmi_emul_data *data;
 
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	switch (axis) {
 	case BMI_EMUL_ACC_X:
@@ -397,47 +395,47 @@ void bmi_emul_set_value(struct i2c_emul *emul, enum bmi_emul_axis axis,
 }
 
 /** Check description in emul_bmi.h */
-void bmi_emul_set_err_on_ro_write(struct i2c_emul *emul, bool set)
+void bmi_emul_set_err_on_ro_write(const struct emul *emul, bool set)
 {
 	struct bmi_emul_data *data;
 
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 	data->error_on_ro_write = set;
 }
 
 /** Check description in emul_bmi.h */
-void bmi_emul_set_err_on_rsvd_write(struct i2c_emul *emul, bool set)
+void bmi_emul_set_err_on_rsvd_write(const struct emul *emul, bool set)
 {
 	struct bmi_emul_data *data;
 
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 	data->error_on_rsvd_write = set;
 }
 
 /** Check description in emul_bmi.h */
-void bmi_emul_set_err_on_wo_read(struct i2c_emul *emul, bool set)
+void bmi_emul_set_err_on_wo_read(const struct emul *emul, bool set)
 {
 	struct bmi_emul_data *data;
 
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 	data->error_on_wo_read = set;
 }
 
 /** Check description in emul_bmi.h */
-void bmi_emul_simulate_cmd_exec_time(struct i2c_emul *emul, bool set)
+void bmi_emul_simulate_cmd_exec_time(const struct emul *emul, bool set)
 {
 	struct bmi_emul_data *data;
 
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 	data->simulate_command_exec_time = set;
 }
 
 /** Check description in emul_bmi.h */
-void bmi_emul_set_skipped_frames(struct i2c_emul *emul, uint8_t skip)
+void bmi_emul_set_skipped_frames(const struct emul *emul, uint8_t skip)
 {
 	struct bmi_emul_data *data;
 
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	data->fifo_skip = skip;
 }
@@ -460,13 +458,13 @@ static int64_t bmi_emul_get_sensortime(void)
  * @param reg Pointer to 3 byte array, where current sensor time should be
  *            stored
  */
-static void bmi_emul_set_sensortime_reg(struct i2c_emul *emul, uint8_t *reg)
+static void bmi_emul_set_sensortime_reg(const struct emul *emul, uint8_t *reg)
 {
 	struct bmi_emul_data *data;
 	uint32_t twos_comp_val;
 	int64_t time;
 
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	time = bmi_emul_get_sensortime();
 
@@ -487,13 +485,13 @@ static void bmi_emul_set_sensortime_reg(struct i2c_emul *emul, uint8_t *reg)
  * @param reg Pointer to 2 byte array, where sensor value should be stored
  * @param shift How many bits should be shift to the right
  */
-static void bmi_emul_set_data_reg(struct i2c_emul *emul, int32_t val,
+static void bmi_emul_set_data_reg(const struct emul *emul, int32_t val,
 				  uint8_t *reg, int shift)
 {
 	struct bmi_emul_data *data;
 	uint32_t twos_comp_val;
 
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	twos_comp_val = bmi_emul_val_to_twos_comp(val);
 
@@ -515,14 +513,14 @@ static void bmi_emul_set_data_reg(struct i2c_emul *emul, int32_t val,
  *
  * @return length of frame
  */
-static uint8_t bmi_emul_get_frame_len(struct i2c_emul *emul,
+static uint8_t bmi_emul_get_frame_len(const struct emul *emul,
 				      struct bmi_emul_frame *frame,
 				      bool tag_time, bool header)
 {
 	struct bmi_emul_data *data;
 	int len;
 
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	/* Empty FIFO frame */
 	if (frame == NULL) {
@@ -584,7 +582,7 @@ static uint8_t bmi_emul_get_frame_len(struct i2c_emul *emul,
  *                  data
  * @param gyr_shift How many bits should be right shifted from gyroscope data
  */
-static void bmi_emul_set_current_frame(struct i2c_emul *emul,
+static void bmi_emul_set_current_frame(const struct emul *emul,
 				       struct bmi_emul_frame *frame,
 				       bool tag_time, bool header,
 				       int acc_shift, int gyr_shift)
@@ -592,11 +590,11 @@ static void bmi_emul_set_current_frame(struct i2c_emul *emul,
 	struct bmi_emul_data *data;
 	int i = 0;
 
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	data->fifo_frame_byte = 0;
-	data->fifo_frame_len = bmi_emul_get_frame_len(emul, frame, tag_time,
-						      header);
+	data->fifo_frame_len =
+		bmi_emul_get_frame_len(emul, frame, tag_time, header);
 	/* Empty FIFO frame */
 	if (frame == NULL) {
 		if (tag_time && header) {
@@ -628,11 +626,14 @@ static void bmi_emul_set_current_frame(struct i2c_emul *emul,
 	if (header) {
 		data->fifo[0] = BMI_EMUL_FIFO_HEAD_DATA;
 		data->fifo[0] |= frame->type & BMI_EMUL_FRAME_MAG ?
-						BMI_EMUL_FIFO_HEAD_DATA_MAG : 0;
+					 BMI_EMUL_FIFO_HEAD_DATA_MAG :
+					 0;
 		data->fifo[0] |= frame->type & BMI_EMUL_FRAME_GYR ?
-						BMI_EMUL_FIFO_HEAD_DATA_GYR : 0;
+					 BMI_EMUL_FIFO_HEAD_DATA_GYR :
+					 0;
 		data->fifo[0] |= frame->type & BMI_EMUL_FRAME_ACC ?
-						BMI_EMUL_FIFO_HEAD_DATA_ACC : 0;
+					 BMI_EMUL_FIFO_HEAD_DATA_ACC :
+					 0;
 		data->fifo[0] |= frame->tag & BMI_EMUL_FIFO_HEAD_DATA_TAG_MASK;
 		i = 1;
 	}
@@ -679,20 +680,20 @@ static void bmi_emul_set_current_frame(struct i2c_emul *emul,
  *
  * @param emul Pointer to BMI emulator
  */
-static void bmi_emul_updata_int_off(struct i2c_emul *emul)
+static void bmi_emul_updata_int_off(const struct emul *emul)
 {
 	struct bmi_emul_data *data;
 	uint16_t gyr_nvm;
 	uint8_t gyr98;
 
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	data->off_acc_x = bmi_emul_acc_nvm_to_off(
-				data->reg[data->type_data->acc_off_reg]);
+		data->reg[data->type_data->acc_off_reg]);
 	data->off_acc_y = bmi_emul_acc_nvm_to_off(
-				data->reg[data->type_data->acc_off_reg + 1]);
+		data->reg[data->type_data->acc_off_reg + 1]);
 	data->off_acc_z = bmi_emul_acc_nvm_to_off(
-				data->reg[data->type_data->acc_off_reg + 2]);
+		data->reg[data->type_data->acc_off_reg + 2]);
 
 	gyr98 = data->reg[data->type_data->gyr98_off_reg];
 
@@ -713,14 +714,14 @@ static void bmi_emul_updata_int_off(struct i2c_emul *emul)
  *
  * @param emul Pointer to BMI emulator
  */
-static void bmi_emul_restore_nvm(struct i2c_emul *emul)
+static void bmi_emul_restore_nvm(const struct emul *emul)
 {
 	struct bmi_emul_data *data;
 	int i;
 
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
-	ASSERT(data->type_data->nvm_len <= BMI_EMUL_MAX_NVM_REGS);
+	__ASSERT_NO_MSG(data->type_data->nvm_len <= BMI_EMUL_MAX_NVM_REGS);
 
 	/* Restore registers values */
 	for (i = 0; i < data->type_data->nvm_len; i++) {
@@ -731,11 +732,11 @@ static void bmi_emul_restore_nvm(struct i2c_emul *emul)
 }
 
 /** Check description in emul_bmi.h */
-void bmi_emul_flush_fifo(struct i2c_emul *emul, bool tag_time, bool header)
+void bmi_emul_flush_fifo(const struct emul *emul, bool tag_time, bool header)
 {
 	struct bmi_emul_data *data;
 
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	data->fifo_skip = 0;
 	data->fifo_frame = NULL;
@@ -747,11 +748,11 @@ void bmi_emul_flush_fifo(struct i2c_emul *emul, bool tag_time, bool header)
 }
 
 /** Check description in emul_bmi.h */
-void bmi_emul_reset_common(struct i2c_emul *emul, bool tag_time, bool header)
+void bmi_emul_reset_common(const struct emul *emul, bool tag_time, bool header)
 {
 	struct bmi_emul_data *data;
 
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	/* Restore registers backed in NVM */
 	bmi_emul_restore_nvm(emul);
@@ -764,21 +765,21 @@ void bmi_emul_reset_common(struct i2c_emul *emul, bool tag_time, bool header)
 }
 
 /** Check description in emul_bmi.h */
-void bmi_emul_set_cmd_end_time(struct i2c_emul *emul, int time)
+void bmi_emul_set_cmd_end_time(const struct emul *emul, int time)
 {
 	struct bmi_emul_data *data;
 
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	data->cmd_end_time = k_uptime_get_32() + time;
 }
 
 /** Check description in emul_bmi.h */
-bool bmi_emul_is_cmd_end(struct i2c_emul *emul)
+bool bmi_emul_is_cmd_end(const struct emul *emul)
 {
 	struct bmi_emul_data *data;
 
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	/* We are simulating command execution time and it doesn't expired */
 	if (data->simulate_command_exec_time &&
@@ -803,14 +804,14 @@ bool bmi_emul_is_cmd_end(struct i2c_emul *emul)
  * @return 0 on success
  * @return -EIO on error
  */
-static int bmi_emul_handle_write(struct i2c_emul *emul, int reg, uint8_t val,
+static int bmi_emul_handle_write(const struct emul *emul, int reg, uint8_t val,
 				 int byte)
 {
 	struct bmi_emul_data *data;
 	uint8_t rsvd_mask;
 	int ret;
 
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	ret = data->type_data->handle_write(data->reg, emul, reg, byte, val);
 	reg = data->type_data->access_reg(emul, reg, byte, false /* = read */);
@@ -855,16 +856,15 @@ static int bmi_emul_handle_write(struct i2c_emul *emul, int reg, uint8_t val,
 }
 
 /** Check description in emul_bmi.h */
-void bmi_emul_state_to_reg(struct i2c_emul *emul, int acc_shift,
+void bmi_emul_state_to_reg(const struct emul *emul, int acc_shift,
 			   int gyr_shift, int acc_reg, int gyr_reg,
-			   int sensortime_reg, bool acc_off_en,
-			   bool gyr_off_en)
+			   int sensortime_reg, bool acc_off_en, bool gyr_off_en)
 {
 	struct bmi_emul_data *data;
 	int32_t val[3];
 	int i;
 
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	if (gyr_off_en) {
 		val[0] = data->gyr_x - data->off_gyr_x;
@@ -900,12 +900,13 @@ void bmi_emul_state_to_reg(struct i2c_emul *emul, int acc_shift,
 }
 
 /** Check description in emul_bmi.h */
-void bmi_emul_append_frame(struct i2c_emul *emul, struct bmi_emul_frame *frame)
+void bmi_emul_append_frame(const struct emul *emul,
+			   struct bmi_emul_frame *frame)
 {
 	struct bmi_emul_data *data;
 	struct bmi_emul_frame *tmp_frame;
 
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	if (data->fifo_frame == NULL) {
 		data->fifo_frame = frame;
@@ -919,13 +920,13 @@ void bmi_emul_append_frame(struct i2c_emul *emul, struct bmi_emul_frame *frame)
 }
 
 /** Check description in emul_bmi.h */
-uint16_t bmi_emul_fifo_len(struct i2c_emul *emul, bool tag_time, bool header)
+uint16_t bmi_emul_fifo_len(const struct emul *emul, bool tag_time, bool header)
 {
 	struct bmi_emul_frame *frame;
 	struct bmi_emul_data *data;
 	uint16_t len = 0;
 
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	if (data->fifo_skip != 0 && header) {
 		len += 2;
@@ -945,14 +946,13 @@ uint16_t bmi_emul_fifo_len(struct i2c_emul *emul, bool tag_time, bool header)
 }
 
 /** Check description in emul_bmi.h */
-uint8_t bmi_emul_get_fifo_data(struct i2c_emul *emul, int byte,
-			       bool tag_time, bool header, int acc_shift,
-			       int gyr_shift)
+uint8_t bmi_emul_get_fifo_data(const struct emul *emul, int byte, bool tag_time,
+			       bool header, int acc_shift, int gyr_shift)
 {
 	struct bmi_emul_data *data;
 	int ret;
 
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	if (byte == 0) {
 		/* Repeat uncompleated read of frame */
@@ -967,6 +967,7 @@ uint8_t bmi_emul_get_fifo_data(struct i2c_emul *emul, int byte,
 
 	if (data->fifo_skip != 0 && byte == 1 && header) {
 		/* Return number of skipped frames */
+
 		ret = data->fifo_skip;
 		data->fifo_skip = 0;
 
@@ -999,13 +1000,13 @@ uint8_t bmi_emul_get_fifo_data(struct i2c_emul *emul, int byte,
  * @return 0 on success
  * @return -EIO on error
  */
-static int bmi_emul_handle_read(struct i2c_emul *emul, int reg, uint8_t *buf,
+static int bmi_emul_handle_read(const struct emul *emul, int reg, uint8_t *buf,
 				int byte)
 {
 	struct bmi_emul_data *data;
 	int ret;
 
-	data = BMI_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	ret = data->type_data->handle_read(data->reg, emul, reg, byte, buf);
 	reg = data->type_data->access_reg(emul, reg, byte, true /* = read */);
@@ -1018,6 +1019,31 @@ static int bmi_emul_handle_read(struct i2c_emul *emul, int reg, uint8_t *buf,
 	return 0;
 }
 
+/**
+ * @brief Called at the end of I2C read message.
+ *
+ * @param target Pointer to emulator
+ * @param reg Address which is now accessed by read command (first byte of last
+ *            I2C write message)
+ * @param bytes Number of bytes responeded to the I2C read message
+ *
+ * @return 0 on success
+ * @return -EIO on error
+ */
+static int bmi_emul_finish_read(const struct emul *emul, int reg, int bytes)
+{
+	struct bmi_emul_data *data;
+	int ret;
+
+	data = emul->data;
+
+	if (data->type_data->finish_read == NULL) {
+		return 0;
+	}
+	ret = data->type_data->finish_read(data->reg, emul, reg, bytes);
+	return ret;
+}
+
 /* Device instantiation */
 
 /**
@@ -1031,42 +1057,31 @@ static int bmi_emul_handle_read(struct i2c_emul *emul, int reg, uint8_t *buf,
  *
  * @return 0 indicating success (always)
  */
-static int bmi_emul_init(const struct emul *emul,
-			 const struct device *parent)
+static int bmi_emul_init(const struct emul *emul, const struct device *parent)
 {
-	const struct i2c_common_emul_cfg *cfg = emul->cfg;
-	struct i2c_common_emul_data *data = cfg->data;
-	struct bmi_emul_data *bmi_data;
-	int ret;
-
-	data->emul.api = &i2c_common_emul_api;
-	data->emul.addr = cfg->addr;
-	data->i2c = parent;
-	data->cfg = cfg;
-	i2c_common_emul_init(data);
+	struct bmi_emul_data *data = emul->data;
 
-	bmi_data = CONTAINER_OF(data, struct bmi_emul_data, common);
+	data->common.i2c = parent;
+	i2c_common_emul_init(&data->common);
 
-	switch (bmi_data->type) {
+	switch (data->type) {
 	case BMI_EMUL_160:
-		bmi_data->type_data = get_bmi160_emul_type_data();
+		data->type_data = get_bmi160_emul_type_data();
 		break;
 	case BMI_EMUL_260:
-		bmi_data->type_data = get_bmi260_emul_type_data();
+		data->type_data = get_bmi260_emul_type_data();
 		break;
 	}
 
 	/* Set callback access_reg to type specific function */
-	data->access_reg = bmi_data->type_data->access_reg;
+	data->common.access_reg = data->type_data->access_reg;
 
-	ret = i2c_emul_register(parent, emul->dev_label, &data->emul);
+	data->type_data->reset(data->reg, emul);
 
-	bmi_data->type_data->reset(bmi_data->reg, &data->emul);
-
-	return ret;
+	return 0;
 }
 
-#define BMI_EMUL(n)							\
+#define BMI_EMUL(n)                                                  \
 	static struct bmi_emul_data bmi_emul_data_##n = {		\
 		.error_on_ro_write = DT_INST_PROP(n, error_on_ro_write),\
 		.error_on_wo_read = DT_INST_PROP(n, error_on_wo_read),	\
@@ -1081,32 +1096,24 @@ static int bmi_emul_init(const struct emul *emul,
 			.finish_write = NULL,				\
 			.start_read = NULL,				\
 			.read_byte = bmi_emul_handle_read,		\
-			.finish_read = NULL,				\
+			.finish_read = bmi_emul_finish_read,		\
 			.access_reg = NULL,				\
 		},							\
-	};								\
-									\
-	static const struct i2c_common_emul_cfg bmi_emul_cfg_##n = {	\
-		.i2c_label = DT_INST_BUS_LABEL(n),			\
-		.dev_label = DT_INST_LABEL(n),                          \
-		.data = &bmi_emul_data_##n.common,			\
-		.addr = DT_INST_REG_ADDR(n),				\
-	};								\
-	EMUL_DEFINE(bmi_emul_init, DT_DRV_INST(n), &bmi_emul_cfg_##n,	\
-		    &bmi_emul_data_##n)
+	};         \
+	static const struct i2c_common_emul_cfg bmi_emul_cfg_##n = { \
+		.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)),      \
+		.data = &bmi_emul_data_##n.common,                   \
+		.addr = DT_INST_REG_ADDR(n),                         \
+	};                                                           \
+	EMUL_DT_INST_DEFINE(n, bmi_emul_init, &bmi_emul_data_##n,    \
+			    &bmi_emul_cfg_##n, &i2c_common_emul_api)
 
 DT_INST_FOREACH_STATUS_OKAY(BMI_EMUL)
 
-#define BMI_EMUL_CASE(n)					\
-	case DT_INST_DEP_ORD(n): return &bmi_emul_data_##n.common.emul;
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
 
-/** Check description in emul_bmi.h */
-struct i2c_emul *bmi_emul_get(int ord)
+struct i2c_common_emul_data *
+emul_bmi_get_i2c_common_data(const struct emul *emul)
 {
-	switch (ord) {
-	DT_INST_FOREACH_STATUS_OKAY(BMI_EMUL_CASE)
-
-	default:
-		return NULL;
-	}
+	return emul->data;
 }
diff --git a/zephyr/emul/emul_bmi160.c b/zephyr/emul/emul_bmi160.c
index 9a2f4b5cf1..c1d6b58a8f 100644
--- a/zephyr/emul/emul_bmi160.c
+++ b/zephyr/emul/emul_bmi160.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,105 +21,105 @@ LOG_MODULE_REGISTER(emul_bmi160);
 
 /** Mask reserved bits in each register of BMI160 */
 static const uint8_t bmi_emul_160_rsvd_mask[] = {
-	[BMI160_CHIP_ID]		= 0x00,
-	[0x01]				= 0xff, /* Reserved */
-	[BMI160_ERR_REG]		= 0x00,
-	[BMI160_PMU_STATUS]		= 0xc0,
-	[BMI160_MAG_X_L_G]		= 0x00,
-	[BMI160_MAG_X_H_G]		= 0x00,
-	[BMI160_MAG_Y_L_G]		= 0x00,
-	[BMI160_MAG_Y_H_G]		= 0x00,
-	[BMI160_MAG_Z_L_G]		= 0x00,
-	[BMI160_MAG_Z_H_G]		= 0x00,
-	[BMI160_RHALL_L_G]		= 0x00,
-	[BMI160_RHALL_H_G]		= 0x00,
-	[BMI160_GYR_X_L_G]		= 0x00,
-	[BMI160_GYR_X_H_G]		= 0x00,
-	[BMI160_GYR_Y_L_G]		= 0x00,
-	[BMI160_GYR_Y_H_G]		= 0x00,
-	[BMI160_GYR_Z_L_G]		= 0x00,
-	[BMI160_GYR_Z_H_G]		= 0x00,
-	[BMI160_ACC_X_L_G]		= 0x00,
-	[BMI160_ACC_X_H_G]		= 0x00,
-	[BMI160_ACC_Y_L_G]		= 0x00,
-	[BMI160_ACC_Y_H_G]		= 0x00,
-	[BMI160_ACC_Z_L_G]		= 0x00,
-	[BMI160_ACC_Z_H_G]		= 0x00,
-	[BMI160_SENSORTIME_0]		= 0x00,
-	[BMI160_SENSORTIME_1]		= 0x00,
-	[BMI160_SENSORTIME_2]		= 0x00,
-	[BMI160_STATUS]			= 0x01,
-	[BMI160_INT_STATUS_0]		= 0x00,
-	[BMI160_INT_STATUS_1]		= 0x03,
-	[BMI160_INT_STATUS_2]		= 0x00,
-	[BMI160_INT_STATUS_3]		= 0x00,
-	[BMI160_TEMPERATURE_0]		= 0x00,
-	[BMI160_TEMPERATURE_1]		= 0x00,
-	[BMI160_FIFO_LENGTH_0]		= 0x00,
-	[BMI160_FIFO_LENGTH_1]		= 0xf8,
-	[BMI160_FIFO_DATA]		= 0x00,
-	[0x25 ... 0x3f]			= 0xff, /* Reserved */
-	[BMI160_ACC_CONF]		= 0x00,
-	[BMI160_ACC_RANGE]		= 0xf0,
-	[BMI160_GYR_CONF]		= 0xc0,
-	[BMI160_GYR_RANGE]		= 0xf8,
-	[BMI160_MAG_CONF]		= 0xf0,
-	[BMI160_FIFO_DOWNS]		= 0x00,
-	[BMI160_FIFO_CONFIG_0]		= 0x00,
-	[BMI160_FIFO_CONFIG_1]		= 0x01,
-	[0x48 ... 0x4a]			= 0xff, /* Reserved */
-	[BMI160_MAG_IF_0]		= 0x01,
-	[BMI160_MAG_IF_1]		= 0x40,
-	[BMI160_MAG_IF_2]		= 0x00,
-	[BMI160_MAG_IF_3]		= 0x00,
-	[BMI160_MAG_IF_4]		= 0x00,
-	[BMI160_INT_EN_0]		= 0x08,
-	[BMI160_INT_EN_1]		= 0x80,
-	[BMI160_INT_EN_2]		= 0xf0,
-	[BMI160_INT_OUT_CTRL]		= 0x00,
-	[BMI160_INT_LATCH]		= 0xc0,
-	[BMI160_INT_MAP_0]		= 0x00,
-	[BMI160_INT_MAP_1]		= 0x00,
-	[BMI160_INT_MAP_2]		= 0x00,
-	[BMI160_INT_DATA_0]		= 0x77,
-	[BMI160_INT_DATA_1]		= 0x7f,
-	[BMI160_INT_LOW_HIGH_0]		= 0x00,
-	[BMI160_INT_LOW_HIGH_1]		= 0x00,
-	[BMI160_INT_LOW_HIGH_2]		= 0x3c,
-	[BMI160_INT_LOW_HIGH_3]		= 0x00,
-	[BMI160_INT_LOW_HIGH_4]		= 0x00,
-	[BMI160_INT_MOTION_0]		= 0x00,
-	[BMI160_INT_MOTION_1]		= 0x00,
-	[BMI160_INT_MOTION_2]		= 0x00,
-	[BMI160_INT_MOTION_3]		= 0xc0,
-	[BMI160_INT_TAP_0]		= 0x38,
-	[BMI160_INT_TAP_1]		= 0xe0,
-	[BMI160_INT_ORIENT_0]		= 0x00,
-	[BMI160_INT_ORIENT_1]		= 0x00,
-	[BMI160_INT_FLAT_0]		= 0xc0,
-	[BMI160_INT_FLAT_1]		= 0xc8,
-	[BMI160_FOC_CONF]		= 0x80,
-	[BMI160_CONF]			= 0xfd,
-	[BMI160_IF_CONF]		= 0xce,
-	[BMI160_PMU_TRIGGER]		= 0x80,
-	[BMI160_SELF_TEST]		= 0xe0,
-	[0x6e]				= 0xff, /* Reserved */
-	[0x6f]				= 0xff, /* Reserved */
-	[BMI160_NV_CONF]		= 0xf0,
-	[BMI160_OFFSET_ACC70]		= 0x00,
-	[BMI160_OFFSET_ACC70 + 1]	= 0x00,
-	[BMI160_OFFSET_ACC70 + 2]	= 0x00,
-	[BMI160_OFFSET_GYR70]		= 0x00,
-	[BMI160_OFFSET_GYR70 + 1]	= 0x00,
-	[BMI160_OFFSET_GYR70 + 2]	= 0x00,
-	[BMI160_OFFSET_EN_GYR98]	= 0x00,
-	[BMI160_STEP_CNT_0]		= 0x00,
-	[BMI160_STEP_CNT_1]		= 0x00,
-	[BMI160_STEP_CONF_0]		= 0x00,
-	[BMI160_STEP_CONF_1]		= 0xf0,
-	[0x7c]				= 0xff, /* Reserved */
-	[0x7d]				= 0xff, /* Reserved */
-	[BMI160_CMD_REG]		= 0x00,
+	[BMI160_CHIP_ID] = 0x00,
+	[0x01] = 0xff, /* Reserved */
+	[BMI160_ERR_REG] = 0x00,
+	[BMI160_PMU_STATUS] = 0xc0,
+	[BMI160_MAG_X_L_G] = 0x00,
+	[BMI160_MAG_X_H_G] = 0x00,
+	[BMI160_MAG_Y_L_G] = 0x00,
+	[BMI160_MAG_Y_H_G] = 0x00,
+	[BMI160_MAG_Z_L_G] = 0x00,
+	[BMI160_MAG_Z_H_G] = 0x00,
+	[BMI160_RHALL_L_G] = 0x00,
+	[BMI160_RHALL_H_G] = 0x00,
+	[BMI160_GYR_X_L_G] = 0x00,
+	[BMI160_GYR_X_H_G] = 0x00,
+	[BMI160_GYR_Y_L_G] = 0x00,
+	[BMI160_GYR_Y_H_G] = 0x00,
+	[BMI160_GYR_Z_L_G] = 0x00,
+	[BMI160_GYR_Z_H_G] = 0x00,
+	[BMI160_ACC_X_L_G] = 0x00,
+	[BMI160_ACC_X_H_G] = 0x00,
+	[BMI160_ACC_Y_L_G] = 0x00,
+	[BMI160_ACC_Y_H_G] = 0x00,
+	[BMI160_ACC_Z_L_G] = 0x00,
+	[BMI160_ACC_Z_H_G] = 0x00,
+	[BMI160_SENSORTIME_0] = 0x00,
+	[BMI160_SENSORTIME_1] = 0x00,
+	[BMI160_SENSORTIME_2] = 0x00,
+	[BMI160_STATUS] = 0x01,
+	[BMI160_INT_STATUS_0] = 0x00,
+	[BMI160_INT_STATUS_1] = 0x03,
+	[BMI160_INT_STATUS_2] = 0x00,
+	[BMI160_INT_STATUS_3] = 0x00,
+	[BMI160_TEMPERATURE_0] = 0x00,
+	[BMI160_TEMPERATURE_1] = 0x00,
+	[BMI160_FIFO_LENGTH_0] = 0x00,
+	[BMI160_FIFO_LENGTH_1] = 0xf8,
+	[BMI160_FIFO_DATA] = 0x00,
+	[0x25 ... 0x3f] = 0xff, /* Reserved */
+	[BMI160_ACC_CONF] = 0x00,
+	[BMI160_ACC_RANGE] = 0xf0,
+	[BMI160_GYR_CONF] = 0xc0,
+	[BMI160_GYR_RANGE] = 0xf8,
+	[BMI160_MAG_CONF] = 0xf0,
+	[BMI160_FIFO_DOWNS] = 0x00,
+	[BMI160_FIFO_CONFIG_0] = 0x00,
+	[BMI160_FIFO_CONFIG_1] = 0x01,
+	[0x48 ... 0x4a] = 0xff, /* Reserved */
+	[BMI160_MAG_IF_0] = 0x01,
+	[BMI160_MAG_IF_1] = 0x40,
+	[BMI160_MAG_IF_2] = 0x00,
+	[BMI160_MAG_IF_3] = 0x00,
+	[BMI160_MAG_IF_4] = 0x00,
+	[BMI160_INT_EN_0] = 0x08,
+	[BMI160_INT_EN_1] = 0x80,
+	[BMI160_INT_EN_2] = 0xf0,
+	[BMI160_INT_OUT_CTRL] = 0x00,
+	[BMI160_INT_LATCH] = 0xc0,
+	[BMI160_INT_MAP_0] = 0x00,
+	[BMI160_INT_MAP_1] = 0x00,
+	[BMI160_INT_MAP_2] = 0x00,
+	[BMI160_INT_DATA_0] = 0x77,
+	[BMI160_INT_DATA_1] = 0x7f,
+	[BMI160_INT_LOW_HIGH_0] = 0x00,
+	[BMI160_INT_LOW_HIGH_1] = 0x00,
+	[BMI160_INT_LOW_HIGH_2] = 0x3c,
+	[BMI160_INT_LOW_HIGH_3] = 0x00,
+	[BMI160_INT_LOW_HIGH_4] = 0x00,
+	[BMI160_INT_MOTION_0] = 0x00,
+	[BMI160_INT_MOTION_1] = 0x00,
+	[BMI160_INT_MOTION_2] = 0x00,
+	[BMI160_INT_MOTION_3] = 0xc0,
+	[BMI160_INT_TAP_0] = 0x38,
+	[BMI160_INT_TAP_1] = 0xe0,
+	[BMI160_INT_ORIENT_0] = 0x00,
+	[BMI160_INT_ORIENT_1] = 0x00,
+	[BMI160_INT_FLAT_0] = 0xc0,
+	[BMI160_INT_FLAT_1] = 0xc8,
+	[BMI160_FOC_CONF] = 0x80,
+	[BMI160_CONF] = 0xfd,
+	[BMI160_IF_CONF] = 0xce,
+	[BMI160_PMU_TRIGGER] = 0x80,
+	[BMI160_SELF_TEST] = 0xe0,
+	[0x6e] = 0xff, /* Reserved */
+	[0x6f] = 0xff, /* Reserved */
+	[BMI160_NV_CONF] = 0xf0,
+	[BMI160_OFFSET_ACC70] = 0x00,
+	[BMI160_OFFSET_ACC70 + 1] = 0x00,
+	[BMI160_OFFSET_ACC70 + 2] = 0x00,
+	[BMI160_OFFSET_GYR70] = 0x00,
+	[BMI160_OFFSET_GYR70 + 1] = 0x00,
+	[BMI160_OFFSET_GYR70 + 2] = 0x00,
+	[BMI160_OFFSET_EN_GYR98] = 0x00,
+	[BMI160_STEP_CNT_0] = 0x00,
+	[BMI160_STEP_CNT_1] = 0x00,
+	[BMI160_STEP_CONF_0] = 0x00,
+	[BMI160_STEP_CONF_1] = 0xf0,
+	[0x7c] = 0xff, /* Reserved */
+	[0x7d] = 0xff, /* Reserved */
+	[BMI160_CMD_REG] = 0x00,
 };
 
 /**
@@ -182,95 +182,95 @@ static int bmi160_emul_gyr_range_to_shift(uint8_t range)
  * @param regs Pointer to array of emulator's registers
  * @param emul Pointer to BMI emulator
  */
-static void bmi160_emul_reset(uint8_t *regs, struct i2c_emul *emul)
+static void bmi160_emul_reset(uint8_t *regs, const struct emul *emul)
 {
 	bool tag_time;
 	bool header;
 
-	regs[BMI160_CHIP_ID]		= 0xd1;
-	regs[BMI160_ERR_REG]		= 0x00;
-	regs[BMI160_PMU_STATUS]		= 0x00;
-	regs[BMI160_MAG_X_L_G]		= 0x00;
-	regs[BMI160_MAG_X_H_G]		= 0x00;
-	regs[BMI160_MAG_Y_L_G]		= 0x00;
-	regs[BMI160_MAG_Y_H_G]		= 0x00;
-	regs[BMI160_MAG_Z_L_G]		= 0x00;
-	regs[BMI160_MAG_Z_H_G]		= 0x00;
-	regs[BMI160_RHALL_L_G]		= 0x00;
-	regs[BMI160_RHALL_H_G]		= 0x00;
-	regs[BMI160_GYR_X_L_G]		= 0x00;
-	regs[BMI160_GYR_X_H_G]		= 0x00;
-	regs[BMI160_GYR_Y_L_G]		= 0x00;
-	regs[BMI160_GYR_Y_H_G]		= 0x00;
-	regs[BMI160_GYR_Z_L_G]		= 0x00;
-	regs[BMI160_GYR_Z_H_G]		= 0x00;
-	regs[BMI160_ACC_X_L_G]		= 0x00;
-	regs[BMI160_ACC_X_H_G]		= 0x00;
-	regs[BMI160_ACC_Y_L_G]		= 0x00;
-	regs[BMI160_ACC_Y_H_G]		= 0x00;
-	regs[BMI160_ACC_Z_L_G]		= 0x00;
-	regs[BMI160_ACC_Z_H_G]		= 0x00;
-	regs[BMI160_SENSORTIME_0]	= 0x00;
-	regs[BMI160_SENSORTIME_1]	= 0x00;
-	regs[BMI160_SENSORTIME_2]	= 0x00;
-	regs[BMI160_STATUS]		= 0x01;
-	regs[BMI160_INT_STATUS_0]	= 0x00;
-	regs[BMI160_INT_STATUS_1]	= 0x00;
-	regs[BMI160_INT_STATUS_2]	= 0x00;
-	regs[BMI160_INT_STATUS_3]	= 0x00;
-	regs[BMI160_TEMPERATURE_0]	= 0x00;
-	regs[BMI160_TEMPERATURE_1]	= 0x00;
-	regs[BMI160_FIFO_LENGTH_0]	= 0x00;
-	regs[BMI160_FIFO_LENGTH_1]	= 0x00;
-	regs[BMI160_FIFO_DATA]		= 0x00;
-	regs[BMI160_ACC_CONF]		= 0x28;
-	regs[BMI160_ACC_RANGE]		= 0x03;
-	regs[BMI160_GYR_CONF]		= 0x28;
-	regs[BMI160_GYR_RANGE]		= 0x00;
-	regs[BMI160_MAG_CONF]		= 0x0b;
-	regs[BMI160_FIFO_DOWNS]		= 0x88;
-	regs[BMI160_FIFO_CONFIG_0]	= 0x80;
-	regs[BMI160_FIFO_CONFIG_1]	= 0x10;
-	regs[BMI160_MAG_IF_0]		= 0x20;
-	regs[BMI160_MAG_IF_1]		= 0x80;
-	regs[BMI160_MAG_IF_2]		= 0x42;
-	regs[BMI160_MAG_IF_3]		= 0x4c;
-	regs[BMI160_MAG_IF_4]		= 0x00;
-	regs[BMI160_INT_EN_0]		= 0x00;
-	regs[BMI160_INT_EN_1]		= 0x00;
-	regs[BMI160_INT_EN_2]		= 0x00;
-	regs[BMI160_INT_OUT_CTRL]	= 0x00;
-	regs[BMI160_INT_LATCH]		= 0x00;
-	regs[BMI160_INT_MAP_0]		= 0x00;
-	regs[BMI160_INT_MAP_1]		= 0x00;
-	regs[BMI160_INT_MAP_2]		= 0x00;
-	regs[BMI160_INT_DATA_0]		= 0x00;
-	regs[BMI160_INT_DATA_1]		= 0x00;
-	regs[BMI160_INT_LOW_HIGH_0]	= 0x07;
-	regs[BMI160_INT_LOW_HIGH_1]	= 0x30;
-	regs[BMI160_INT_LOW_HIGH_2]	= 0x81;
-	regs[BMI160_INT_LOW_HIGH_3]	= 0xdb;
-	regs[BMI160_INT_LOW_HIGH_4]	= 0xc0;
-	regs[BMI160_INT_MOTION_0]	= 0x00;
-	regs[BMI160_INT_MOTION_1]	= 0x14;
-	regs[BMI160_INT_MOTION_2]	= 0x14;
-	regs[BMI160_INT_MOTION_3]	= 0x24;
-	regs[BMI160_INT_TAP_0]		= 0x04;
-	regs[BMI160_INT_TAP_1]		= 0xda;
-	regs[BMI160_INT_ORIENT_0]	= 0x18;
-	regs[BMI160_INT_ORIENT_1]	= 0x48;
-	regs[BMI160_INT_FLAT_0]		= 0x08;
-	regs[BMI160_INT_FLAT_1]		= 0x11;
-	regs[BMI160_FOC_CONF]		= 0x00;
-	regs[BMI160_CONF]		= 0x00;
-	regs[BMI160_IF_CONF]		= 0x00;
-	regs[BMI160_PMU_TRIGGER]	= 0x00;
-	regs[BMI160_SELF_TEST]		= 0x00;
-	regs[BMI160_STEP_CNT_0]		= 0x00;
-	regs[BMI160_STEP_CNT_1]		= 0x00;
-	regs[BMI160_STEP_CONF_0]	= 0x00;
-	regs[BMI160_STEP_CONF_1]	= 0x15;
-	regs[BMI160_CMD_REG]		= 0x03;
+	regs[BMI160_CHIP_ID] = 0xd1;
+	regs[BMI160_ERR_REG] = 0x00;
+	regs[BMI160_PMU_STATUS] = 0x00;
+	regs[BMI160_MAG_X_L_G] = 0x00;
+	regs[BMI160_MAG_X_H_G] = 0x00;
+	regs[BMI160_MAG_Y_L_G] = 0x00;
+	regs[BMI160_MAG_Y_H_G] = 0x00;
+	regs[BMI160_MAG_Z_L_G] = 0x00;
+	regs[BMI160_MAG_Z_H_G] = 0x00;
+	regs[BMI160_RHALL_L_G] = 0x00;
+	regs[BMI160_RHALL_H_G] = 0x00;
+	regs[BMI160_GYR_X_L_G] = 0x00;
+	regs[BMI160_GYR_X_H_G] = 0x00;
+	regs[BMI160_GYR_Y_L_G] = 0x00;
+	regs[BMI160_GYR_Y_H_G] = 0x00;
+	regs[BMI160_GYR_Z_L_G] = 0x00;
+	regs[BMI160_GYR_Z_H_G] = 0x00;
+	regs[BMI160_ACC_X_L_G] = 0x00;
+	regs[BMI160_ACC_X_H_G] = 0x00;
+	regs[BMI160_ACC_Y_L_G] = 0x00;
+	regs[BMI160_ACC_Y_H_G] = 0x00;
+	regs[BMI160_ACC_Z_L_G] = 0x00;
+	regs[BMI160_ACC_Z_H_G] = 0x00;
+	regs[BMI160_SENSORTIME_0] = 0x00;
+	regs[BMI160_SENSORTIME_1] = 0x00;
+	regs[BMI160_SENSORTIME_2] = 0x00;
+	regs[BMI160_STATUS] = 0x01;
+	regs[BMI160_INT_STATUS_0] = 0x00;
+	regs[BMI160_INT_STATUS_1] = 0x00;
+	regs[BMI160_INT_STATUS_2] = 0x00;
+	regs[BMI160_INT_STATUS_3] = 0x00;
+	regs[BMI160_TEMPERATURE_0] = 0x00;
+	regs[BMI160_TEMPERATURE_1] = 0x00;
+	regs[BMI160_FIFO_LENGTH_0] = 0x00;
+	regs[BMI160_FIFO_LENGTH_1] = 0x00;
+	regs[BMI160_FIFO_DATA] = 0x00;
+	regs[BMI160_ACC_CONF] = 0x28;
+	regs[BMI160_ACC_RANGE] = 0x03;
+	regs[BMI160_GYR_CONF] = 0x28;
+	regs[BMI160_GYR_RANGE] = 0x00;
+	regs[BMI160_MAG_CONF] = 0x0b;
+	regs[BMI160_FIFO_DOWNS] = 0x88;
+	regs[BMI160_FIFO_CONFIG_0] = 0x80;
+	regs[BMI160_FIFO_CONFIG_1] = 0x10;
+	regs[BMI160_MAG_IF_0] = 0x20;
+	regs[BMI160_MAG_IF_1] = 0x80;
+	regs[BMI160_MAG_IF_2] = 0x42;
+	regs[BMI160_MAG_IF_3] = 0x4c;
+	regs[BMI160_MAG_IF_4] = 0x00;
+	regs[BMI160_INT_EN_0] = 0x00;
+	regs[BMI160_INT_EN_1] = 0x00;
+	regs[BMI160_INT_EN_2] = 0x00;
+	regs[BMI160_INT_OUT_CTRL] = 0x00;
+	regs[BMI160_INT_LATCH] = 0x00;
+	regs[BMI160_INT_MAP_0] = 0x00;
+	regs[BMI160_INT_MAP_1] = 0x00;
+	regs[BMI160_INT_MAP_2] = 0x00;
+	regs[BMI160_INT_DATA_0] = 0x00;
+	regs[BMI160_INT_DATA_1] = 0x00;
+	regs[BMI160_INT_LOW_HIGH_0] = 0x07;
+	regs[BMI160_INT_LOW_HIGH_1] = 0x30;
+	regs[BMI160_INT_LOW_HIGH_2] = 0x81;
+	regs[BMI160_INT_LOW_HIGH_3] = 0xdb;
+	regs[BMI160_INT_LOW_HIGH_4] = 0xc0;
+	regs[BMI160_INT_MOTION_0] = 0x00;
+	regs[BMI160_INT_MOTION_1] = 0x14;
+	regs[BMI160_INT_MOTION_2] = 0x14;
+	regs[BMI160_INT_MOTION_3] = 0x24;
+	regs[BMI160_INT_TAP_0] = 0x04;
+	regs[BMI160_INT_TAP_1] = 0xda;
+	regs[BMI160_INT_ORIENT_0] = 0x18;
+	regs[BMI160_INT_ORIENT_1] = 0x48;
+	regs[BMI160_INT_FLAT_0] = 0x08;
+	regs[BMI160_INT_FLAT_1] = 0x11;
+	regs[BMI160_FOC_CONF] = 0x00;
+	regs[BMI160_CONF] = 0x00;
+	regs[BMI160_IF_CONF] = 0x00;
+	regs[BMI160_PMU_TRIGGER] = 0x00;
+	regs[BMI160_SELF_TEST] = 0x00;
+	regs[BMI160_STEP_CNT_0] = 0x00;
+	regs[BMI160_STEP_CNT_1] = 0x00;
+	regs[BMI160_STEP_CONF_0] = 0x00;
+	regs[BMI160_STEP_CONF_1] = 0x15;
+	regs[BMI160_CMD_REG] = 0x03;
 
 	/* Call generic reset */
 	tag_time = regs[BMI160_FIFO_CONFIG_1] & BMI160_FIFO_TAG_TIME_EN;
@@ -349,7 +349,7 @@ static int16_t bmi160_emul_get_acc_target_off(int32_t acc, uint8_t target)
  * @param regs Pointer to array of emulator's registers
  * @param emul Pointer to BMI emulator
  */
-static void bmi160_emul_handle_off_comp(uint8_t *regs, struct i2c_emul *emul)
+static void bmi160_emul_handle_off_comp(uint8_t *regs, const struct emul *emul)
 {
 	uint8_t target;
 	int16_t off;
@@ -361,6 +361,7 @@ static void bmi160_emul_handle_off_comp(uint8_t *regs, struct i2c_emul *emul)
 		bmi_emul_set_off(emul, BMI_EMUL_GYR_X, off);
 		val = bmi_emul_get_value(emul, BMI_EMUL_GYR_Y);
 		off = bmi160_emul_get_gyr_target_off(val);
+
 		bmi_emul_set_off(emul, BMI_EMUL_GYR_Y, off);
 		val = bmi_emul_get_value(emul, BMI_EMUL_GYR_Z);
 		off = bmi160_emul_get_gyr_target_off(val);
@@ -401,7 +402,8 @@ static void bmi160_emul_handle_off_comp(uint8_t *regs, struct i2c_emul *emul)
  * @return 0 on success
  * @return -EIO on failure
  */
-static int bmi160_emul_start_cmd(uint8_t *regs, struct i2c_emul *emul, int cmd)
+static int bmi160_emul_start_cmd(uint8_t *regs, const struct emul *emul,
+				 int cmd)
 {
 	int time;
 
@@ -470,7 +472,7 @@ static int bmi160_emul_start_cmd(uint8_t *regs, struct i2c_emul *emul, int cmd)
  * @param regs Pointer to array of emulator's registers
  * @param emul Pointer to BMI emulator
  */
-static void bmi160_emul_end_cmd(uint8_t *regs, struct i2c_emul *emul)
+static void bmi160_emul_end_cmd(uint8_t *regs, const struct emul *emul)
 {
 	uint8_t pmu_status;
 	bool tag_time;
@@ -560,7 +562,7 @@ static void bmi160_emul_end_cmd(uint8_t *regs, struct i2c_emul *emul)
  * @return BMI_EMUL_ACCESS_E on RO register access
  * @return -EIO on error
  */
-static int bmi160_emul_handle_write(uint8_t *regs, struct i2c_emul *emul,
+static int bmi160_emul_handle_write(uint8_t *regs, const struct emul *emul,
 				    int reg, int byte, uint8_t val)
 {
 	bool tag_time;
@@ -618,7 +620,7 @@ static int bmi160_emul_handle_write(uint8_t *regs, struct i2c_emul *emul,
  *
  * @return Currently accessed register
  */
-static int bmi160_emul_access_reg(struct i2c_emul *emul, int reg, int byte,
+static int bmi160_emul_access_reg(const struct emul *emul, int reg, int byte,
 				  bool read)
 {
 	if (!read) {
@@ -654,7 +656,7 @@ static int bmi160_emul_access_reg(struct i2c_emul *emul, int reg, int byte,
  * @return BMI_EMUL_ACCESS_E on WO register access
  * @return -EIO on other error
  */
-static int bmi160_emul_handle_read(uint8_t *regs, struct i2c_emul *emul,
+static int bmi160_emul_handle_read(uint8_t *regs, const struct emul *emul,
 				   int reg, int byte, char *buf)
 {
 	uint16_t fifo_len;
@@ -714,8 +716,8 @@ static int bmi160_emul_handle_read(uint8_t *regs, struct i2c_emul *emul,
 			bmi_emul_state_to_reg(emul, acc_shift, gyr_shift,
 					      BMI160_ACC_X_L_G,
 					      BMI160_GYR_X_L_G,
-					      BMI160_SENSORTIME_0,
-					      acc_off_en, gyr_off_en);
+					      BMI160_SENSORTIME_0, acc_off_en,
+					      gyr_off_en);
 		}
 		break;
 	case BMI160_FIFO_LENGTH_0:
@@ -738,21 +740,35 @@ static int bmi160_emul_handle_read(uint8_t *regs, struct i2c_emul *emul,
 	return 0;
 }
 
+static int bmi160_emul_finish_read(uint8_t *regs, const struct emul *emul,
+				   int reg, int bytes)
+{
+	int i;
+
+	switch (reg) {
+	case BMI160_INT_STATUS_0:
+		/* Clear interrupt status after reading. */
+		for (i = 0; i < bytes; ++i) {
+			regs[BMI160_INT_STATUS_0 + i] = 0;
+		}
+		break;
+	}
+	return 0;
+}
+
 /** Registers backed in NVM by BMI160 */
-const int bmi160_nvm_reg[] = {BMI160_NV_CONF,
-			      BMI160_OFFSET_ACC70,
-			      BMI160_OFFSET_ACC70 + 1,
-			      BMI160_OFFSET_ACC70 + 2,
-			      BMI160_OFFSET_GYR70,
-			      BMI160_OFFSET_GYR70 + 1,
-			      BMI160_OFFSET_GYR70 + 2,
-			      BMI160_OFFSET_EN_GYR98};
+const int bmi160_nvm_reg[] = {
+	BMI160_NV_CONF,		 BMI160_OFFSET_ACC70,	BMI160_OFFSET_ACC70 + 1,
+	BMI160_OFFSET_ACC70 + 2, BMI160_OFFSET_GYR70,	BMI160_OFFSET_GYR70 + 1,
+	BMI160_OFFSET_GYR70 + 2, BMI160_OFFSET_EN_GYR98
+};
 
 /** Confguration of BMI160 */
 struct bmi_emul_type_data bmi160_emul = {
 	.sensortime_follow_config_frame = false,
 	.handle_write = bmi160_emul_handle_write,
 	.handle_read = bmi160_emul_handle_read,
+	.finish_read = bmi160_emul_finish_read,
 	.access_reg = bmi160_emul_access_reg,
 	.reset = bmi160_emul_reset,
 	.rsvd_mask = bmi_emul_160_rsvd_mask,
diff --git a/zephyr/emul/emul_bmi260.c b/zephyr/emul/emul_bmi260.c
index 31da71316a..5892a9ae96 100644
--- a/zephyr/emul/emul_bmi260.c
+++ b/zephyr/emul/emul_bmi260.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,100 +21,100 @@ LOG_MODULE_REGISTER(emul_bmi260);
 
 /** Mask reserved bits in each register of BMI260 */
 static const uint8_t bmi_emul_260_rsvd_mask[] = {
-	[BMI260_CHIP_ID]		= 0x00,
-	[0x01]				= 0xff, /* Reserved */
-	[BMI260_ERR_REG]		= 0x20,
-	[BMI260_STATUS]			= 0x0b,
-	[BMI260_AUX_X_L_G]		= 0x00,
-	[BMI260_AUX_X_H_G]		= 0x00,
-	[BMI260_AUX_Y_L_G]		= 0x00,
-	[BMI260_AUX_Y_H_G]		= 0x00,
-	[BMI260_AUX_Z_L_G]		= 0x00,
-	[BMI260_AUX_Z_H_G]		= 0x00,
-	[BMI260_AUX_R_L_G]		= 0x00,
-	[BMI260_AUX_R_H_G]		= 0x00,
-	[BMI260_ACC_X_L_G]		= 0x00,
-	[BMI260_ACC_X_H_G]		= 0x00,
-	[BMI260_ACC_Y_L_G]		= 0x00,
-	[BMI260_ACC_Y_H_G]		= 0x00,
-	[BMI260_ACC_Z_L_G]		= 0x00,
-	[BMI260_ACC_Z_H_G]		= 0x00,
-	[BMI260_GYR_X_L_G]		= 0x00,
-	[BMI260_GYR_X_H_G]		= 0x00,
-	[BMI260_GYR_Y_L_G]		= 0x00,
-	[BMI260_GYR_Y_H_G]		= 0x00,
-	[BMI260_GYR_Z_L_G]		= 0x00,
-	[BMI260_GYR_Z_H_G]		= 0x00,
-	[BMI260_SENSORTIME_0]		= 0x00,
-	[BMI260_SENSORTIME_1]		= 0x00,
-	[BMI260_SENSORTIME_2]		= 0x00,
-	[BMI260_EVENT]			= 0xe2,
-	[BMI260_INT_STATUS_0]		= 0x00,
-	[BMI260_INT_STATUS_1]		= 0x18,
-	[BMI260_SC_OUT_0]		= 0x00,
-	[BMI260_SC_OUT_1]		= 0x00,
-	[BMI260_ORIENT_ACT]		= 0xe0,
-	[BMI260_INTERNAL_STATUS]	= 0x00,
-	[BMI260_TEMPERATURE_0]		= 0x00,
-	[BMI260_TEMPERATURE_1]		= 0x00,
-	[BMI260_FIFO_LENGTH_0]		= 0x00,
-	[BMI260_FIFO_LENGTH_1]		= 0xc0,
-	[BMI160_FIFO_DATA]		= 0x00,
-	[0x27 ... 0x2e]			= 0xff, /* Reserved */
-	[BMI260_FEAT_PAGE]		= 0xf8,
-	[0x30 ... 0x3f]			= 0x00, /* Features */
-	[BMI260_ACC_CONF]		= 0x00,
-	[BMI260_ACC_RANGE]		= 0xfc,
-	[BMI260_GYR_CONF]		= 0x00,
-	[BMI260_GYR_RANGE]		= 0xf0,
-	[BMI260_AUX_CONF]		= 0x00,
-	[BMI260_FIFO_DOWNS]		= 0x00,
-	[BMI260_FIFO_WTM_0]		= 0x00,
-	[BMI260_FIFO_WTM_1]		= 0xe0,
-	[BMI260_FIFO_CONFIG_0]		= 0xfc,
-	[BMI260_FIFO_CONFIG_1]		= 0x00,
-	[BMI260_SATURATION]		= 0xc0,
-	[BMI260_AUX_DEV_ID]		= 0x01,
-	[BMI260_AUX_IF_CONF]		= 0x30,
-	[BMI260_AUX_RD_ADDR]		= 0x00,
-	[BMI260_AUX_WR_ADDR]		= 0x00,
-	[BMI260_AUX_WR_DATA]		= 0x00,
-	[0x50 ... 0x51]			= 0xff, /* Reserved */
-	[BMI260_ERR_REG_MSK]		= 0x20,
-	[BMI260_INT1_IO_CTRL]		= 0xe1,
-	[BMI260_INT2_IO_CTRL]		= 0xe1,
-	[BMI260_INT_LATCH]		= 0xfe,
-	[BMI260_INT1_MAP_FEAT]		= 0x00,
-	[BMI260_INT2_MAP_FEAT]		= 0x00,
-	[BMI260_INT_MAP_DATA]		= 0x00,
-	[BMI260_INIT_CTRL]		= 0x00,
-	[0x5a]				= 0xff, /* Reserved */
-	[BMI260_INIT_ADDR_0]		= 0xf0,
-	[BMI260_INIT_ADDR_1]		= 0x00,
-	[0x5d]				= 0xff, /* Reserved */
-	[BMI260_INIT_DATA]		= 0x00,
-	[BMI260_INTERNAL_ERROR]		= 0xe9,
-	[0x60 ... 0x67]			= 0xff, /* Reserved */
-	[BMI260_AUX_IF_TRIM]		= 0xf8,
-	[BMI260_GYR_CRT_CONF]		= 0xf2,
-	[BMI260_NVM_CONF]		= 0xfd,
-	[BMI260_IF_CONF]		= 0xcc,
-	[BMI260_DRV]			= 0x00,
-	[BMI260_ACC_SELF_TEST]		= 0xf2,
-	[BMI260_GYR_SELF_TEST_AXES]	= 0xf0,
-	[0x6f]				= 0xff, /* Reserved */
-	[BMI260_NV_CONF]		= 0xf0,
-	[BMI260_OFFSET_ACC70]		= 0x00,
-	[BMI260_OFFSET_ACC70 + 1]	= 0x00,
-	[BMI260_OFFSET_ACC70 + 2]	= 0x00,
-	[BMI260_OFFSET_GYR70]		= 0x00,
-	[BMI260_OFFSET_GYR70 + 1]	= 0x00,
-	[BMI260_OFFSET_GYR70 + 2]	= 0x00,
-	[BMI160_OFFSET_EN_GYR98]	= 0x00,
-	[0x78 ... 0x7b]			= 0xff, /* Reserved */
-	[BMI260_PWR_CONF]		= 0xf8,
-	[BMI260_PWR_CTRL]		= 0xf0,
-	[BMI260_CMD_REG]		= 0x00,
+	[BMI260_CHIP_ID] = 0x00,
+	[0x01] = 0xff, /* Reserved */
+	[BMI260_ERR_REG] = 0x20,
+	[BMI260_STATUS] = 0x0b,
+	[BMI260_AUX_X_L_G] = 0x00,
+	[BMI260_AUX_X_H_G] = 0x00,
+	[BMI260_AUX_Y_L_G] = 0x00,
+	[BMI260_AUX_Y_H_G] = 0x00,
+	[BMI260_AUX_Z_L_G] = 0x00,
+	[BMI260_AUX_Z_H_G] = 0x00,
+	[BMI260_AUX_R_L_G] = 0x00,
+	[BMI260_AUX_R_H_G] = 0x00,
+	[BMI260_ACC_X_L_G] = 0x00,
+	[BMI260_ACC_X_H_G] = 0x00,
+	[BMI260_ACC_Y_L_G] = 0x00,
+	[BMI260_ACC_Y_H_G] = 0x00,
+	[BMI260_ACC_Z_L_G] = 0x00,
+	[BMI260_ACC_Z_H_G] = 0x00,
+	[BMI260_GYR_X_L_G] = 0x00,
+	[BMI260_GYR_X_H_G] = 0x00,
+	[BMI260_GYR_Y_L_G] = 0x00,
+	[BMI260_GYR_Y_H_G] = 0x00,
+	[BMI260_GYR_Z_L_G] = 0x00,
+	[BMI260_GYR_Z_H_G] = 0x00,
+	[BMI260_SENSORTIME_0] = 0x00,
+	[BMI260_SENSORTIME_1] = 0x00,
+	[BMI260_SENSORTIME_2] = 0x00,
+	[BMI260_EVENT] = 0xe2,
+	[BMI260_INT_STATUS_0] = 0x00,
+	[BMI260_INT_STATUS_1] = 0x18,
+	[BMI260_SC_OUT_0] = 0x00,
+	[BMI260_SC_OUT_1] = 0x00,
+	[BMI260_ORIENT_ACT] = 0xe0,
+	[BMI260_INTERNAL_STATUS] = 0x00,
+	[BMI260_TEMPERATURE_0] = 0x00,
+	[BMI260_TEMPERATURE_1] = 0x00,
+	[BMI260_FIFO_LENGTH_0] = 0x00,
+	[BMI260_FIFO_LENGTH_1] = 0xc0,
+	[BMI160_FIFO_DATA] = 0x00,
+	[0x27 ... 0x2e] = 0xff, /* Reserved */
+	[BMI260_FEAT_PAGE] = 0xf8,
+	[0x30 ... 0x3f] = 0x00, /* Features */
+	[BMI260_ACC_CONF] = 0x00,
+	[BMI260_ACC_RANGE] = 0xfc,
+	[BMI260_GYR_CONF] = 0x00,
+	[BMI260_GYR_RANGE] = 0xf0,
+	[BMI260_AUX_CONF] = 0x00,
+	[BMI260_FIFO_DOWNS] = 0x00,
+	[BMI260_FIFO_WTM_0] = 0x00,
+	[BMI260_FIFO_WTM_1] = 0xe0,
+	[BMI260_FIFO_CONFIG_0] = 0xfc,
+	[BMI260_FIFO_CONFIG_1] = 0x00,
+	[BMI260_SATURATION] = 0xc0,
+	[BMI260_AUX_DEV_ID] = 0x01,
+	[BMI260_AUX_IF_CONF] = 0x30,
+	[BMI260_AUX_RD_ADDR] = 0x00,
+	[BMI260_AUX_WR_ADDR] = 0x00,
+	[BMI260_AUX_WR_DATA] = 0x00,
+	[0x50 ... 0x51] = 0xff, /* Reserved */
+	[BMI260_ERR_REG_MSK] = 0x20,
+	[BMI260_INT1_IO_CTRL] = 0xe1,
+	[BMI260_INT2_IO_CTRL] = 0xe1,
+	[BMI260_INT_LATCH] = 0xfe,
+	[BMI260_INT1_MAP_FEAT] = 0x00,
+	[BMI260_INT2_MAP_FEAT] = 0x00,
+	[BMI260_INT_MAP_DATA] = 0x00,
+	[BMI260_INIT_CTRL] = 0x00,
+	[0x5a] = 0xff, /* Reserved */
+	[BMI260_INIT_ADDR_0] = 0xf0,
+	[BMI260_INIT_ADDR_1] = 0x00,
+	[0x5d] = 0xff, /* Reserved */
+	[BMI260_INIT_DATA] = 0x00,
+	[BMI260_INTERNAL_ERROR] = 0xe9,
+	[0x60 ... 0x67] = 0xff, /* Reserved */
+	[BMI260_AUX_IF_TRIM] = 0xf8,
+	[BMI260_GYR_CRT_CONF] = 0xf2,
+	[BMI260_NVM_CONF] = 0xfd,
+	[BMI260_IF_CONF] = 0xcc,
+	[BMI260_DRV] = 0x00,
+	[BMI260_ACC_SELF_TEST] = 0xf2,
+	[BMI260_GYR_SELF_TEST_AXES] = 0xf0,
+	[0x6f] = 0xff, /* Reserved */
+	[BMI260_NV_CONF] = 0xf0,
+	[BMI260_OFFSET_ACC70] = 0x00,
+	[BMI260_OFFSET_ACC70 + 1] = 0x00,
+	[BMI260_OFFSET_ACC70 + 2] = 0x00,
+	[BMI260_OFFSET_GYR70] = 0x00,
+	[BMI260_OFFSET_GYR70 + 1] = 0x00,
+	[BMI260_OFFSET_GYR70 + 2] = 0x00,
+	[BMI160_OFFSET_EN_GYR98] = 0x00,
+	[0x78 ... 0x7b] = 0xff, /* Reserved */
+	[BMI260_PWR_CONF] = 0xf8,
+	[BMI260_PWR_CTRL] = 0xf0,
+	[BMI260_CMD_REG] = 0x00,
 };
 
 /**
@@ -123,88 +123,88 @@ static const uint8_t bmi_emul_260_rsvd_mask[] = {
  * @param regs Pointer to array of emulator's registers
  * @param emul Pointer to BMI emulator
  */
-static void bmi260_emul_reset(uint8_t *regs, struct i2c_emul *emul)
+static void bmi260_emul_reset(uint8_t *regs, const struct emul *emul)
 {
 	bool tag_time;
 	bool header;
 
-	regs[BMI260_CHIP_ID]		= 0x27;
-	regs[BMI260_ERR_REG]		= 0x00;
-	regs[BMI260_STATUS]		= 0x10;
-	regs[BMI260_AUX_X_L_G]		= 0x00;
-	regs[BMI260_AUX_X_H_G]		= 0x00;
-	regs[BMI260_AUX_Y_L_G]		= 0x00;
-	regs[BMI260_AUX_Y_H_G]		= 0x00;
-	regs[BMI260_AUX_Z_L_G]		= 0x00;
-	regs[BMI260_AUX_Z_H_G]		= 0x00;
-	regs[BMI260_AUX_R_L_G]		= 0x00;
-	regs[BMI260_AUX_R_H_G]		= 0x00;
-	regs[BMI260_ACC_X_L_G]		= 0x00;
-	regs[BMI260_ACC_X_H_G]		= 0x00;
-	regs[BMI260_ACC_Y_L_G]		= 0x00;
-	regs[BMI260_ACC_Y_H_G]		= 0x00;
-	regs[BMI260_ACC_Z_L_G]		= 0x00;
-	regs[BMI260_ACC_Z_H_G]		= 0x00;
-	regs[BMI260_GYR_X_L_G]		= 0x00;
-	regs[BMI260_GYR_X_H_G]		= 0x00;
-	regs[BMI260_GYR_Y_L_G]		= 0x00;
-	regs[BMI260_GYR_Y_H_G]		= 0x00;
-	regs[BMI260_GYR_Z_L_G]		= 0x00;
-	regs[BMI260_GYR_Z_H_G]		= 0x00;
-	regs[BMI260_SENSORTIME_0]	= 0x00;
-	regs[BMI260_SENSORTIME_1]	= 0x00;
-	regs[BMI260_SENSORTIME_2]	= 0x00;
-	regs[BMI260_EVENT]		= 0x01;
-	regs[BMI260_INT_STATUS_0]	= 0x00;
-	regs[BMI260_INT_STATUS_1]	= 0x00;
-	regs[BMI260_SC_OUT_0]		= 0x00;
-	regs[BMI260_SC_OUT_1]		= 0x00;
-	regs[BMI260_ORIENT_ACT]		= 0x00;
-	regs[BMI260_INTERNAL_STATUS]	= 0x00;
-	regs[BMI260_TEMPERATURE_0]	= 0x00;
-	regs[BMI260_TEMPERATURE_1]	= 0x80;
-	regs[BMI260_FIFO_LENGTH_0]	= 0x00;
-	regs[BMI260_FIFO_LENGTH_1]	= 0x00;
-	regs[BMI160_FIFO_DATA]		= 0x00;
-	regs[BMI260_FEAT_PAGE]		= 0x00;
-	regs[BMI260_ACC_CONF]		= 0xa8;
-	regs[BMI260_ACC_RANGE]		= 0x02;
-	regs[BMI260_GYR_CONF]		= 0xa9;
-	regs[BMI260_GYR_RANGE]		= 0x00;
-	regs[BMI260_AUX_CONF]		= 0x46;
-	regs[BMI260_FIFO_DOWNS]		= 0x88;
-	regs[BMI260_FIFO_WTM_0]		= 0x00;
-	regs[BMI260_FIFO_WTM_1]		= 0x02;
-	regs[BMI260_FIFO_CONFIG_0]	= 0x02;
-	regs[BMI260_FIFO_CONFIG_1]	= 0x10;
-	regs[BMI260_SATURATION]		= 0x00;
-	regs[BMI260_AUX_DEV_ID]		= 0x20;
-	regs[BMI260_AUX_IF_CONF]	= 0x83;
-	regs[BMI260_AUX_RD_ADDR]	= 0x42;
-	regs[BMI260_AUX_WR_ADDR]	= 0x4c;
-	regs[BMI260_AUX_WR_DATA]	= 0x02;
-	regs[BMI260_ERR_REG_MSK]	= 0x00;
-	regs[BMI260_INT1_IO_CTRL]	= 0x00;
-	regs[BMI260_INT2_IO_CTRL]	= 0x00;
-	regs[BMI260_INT_LATCH]		= 0x00;
-	regs[BMI260_INT1_MAP_FEAT]	= 0x00;
-	regs[BMI260_INT2_MAP_FEAT]	= 0x00;
-	regs[BMI260_INT_MAP_DATA]	= 0x00;
-	regs[BMI260_INIT_CTRL]		= 0x00;
-	regs[BMI260_INIT_ADDR_0]	= 0x00;
-	regs[BMI260_INIT_ADDR_1]	= 0x00;
-	regs[BMI260_INIT_DATA]		= 0x00;
-	regs[BMI260_INTERNAL_ERROR]	= 0x00;
-	regs[BMI260_AUX_IF_TRIM]	= 0x01;
-	regs[BMI260_GYR_CRT_CONF]	= 0x00;
-	regs[BMI260_NVM_CONF]		= 0x00;
-	regs[BMI260_IF_CONF]		= 0x00;
-	regs[BMI260_DRV]		= 0xff;
-	regs[BMI260_ACC_SELF_TEST]	= 0x00;
-	regs[BMI260_GYR_SELF_TEST_AXES]	= 0x00;
-	regs[BMI260_PWR_CONF]		= 0x03;
-	regs[BMI260_PWR_CTRL]		= 0x00;
-	regs[BMI260_CMD_REG]		= 0x00;
+	regs[BMI260_CHIP_ID] = 0x27;
+	regs[BMI260_ERR_REG] = 0x00;
+	regs[BMI260_STATUS] = 0x10;
+	regs[BMI260_AUX_X_L_G] = 0x00;
+	regs[BMI260_AUX_X_H_G] = 0x00;
+	regs[BMI260_AUX_Y_L_G] = 0x00;
+	regs[BMI260_AUX_Y_H_G] = 0x00;
+	regs[BMI260_AUX_Z_L_G] = 0x00;
+	regs[BMI260_AUX_Z_H_G] = 0x00;
+	regs[BMI260_AUX_R_L_G] = 0x00;
+	regs[BMI260_AUX_R_H_G] = 0x00;
+	regs[BMI260_ACC_X_L_G] = 0x00;
+	regs[BMI260_ACC_X_H_G] = 0x00;
+	regs[BMI260_ACC_Y_L_G] = 0x00;
+	regs[BMI260_ACC_Y_H_G] = 0x00;
+	regs[BMI260_ACC_Z_L_G] = 0x00;
+	regs[BMI260_ACC_Z_H_G] = 0x00;
+	regs[BMI260_GYR_X_L_G] = 0x00;
+	regs[BMI260_GYR_X_H_G] = 0x00;
+	regs[BMI260_GYR_Y_L_G] = 0x00;
+	regs[BMI260_GYR_Y_H_G] = 0x00;
+	regs[BMI260_GYR_Z_L_G] = 0x00;
+	regs[BMI260_GYR_Z_H_G] = 0x00;
+	regs[BMI260_SENSORTIME_0] = 0x00;
+	regs[BMI260_SENSORTIME_1] = 0x00;
+	regs[BMI260_SENSORTIME_2] = 0x00;
+	regs[BMI260_EVENT] = 0x01;
+	regs[BMI260_INT_STATUS_0] = 0x00;
+	regs[BMI260_INT_STATUS_1] = 0x00;
+	regs[BMI260_SC_OUT_0] = 0x00;
+	regs[BMI260_SC_OUT_1] = 0x00;
+	regs[BMI260_ORIENT_ACT] = 0x00;
+	regs[BMI260_INTERNAL_STATUS] = 0x00;
+	regs[BMI260_TEMPERATURE_0] = 0x00;
+	regs[BMI260_TEMPERATURE_1] = 0x80;
+	regs[BMI260_FIFO_LENGTH_0] = 0x00;
+	regs[BMI260_FIFO_LENGTH_1] = 0x00;
+	regs[BMI160_FIFO_DATA] = 0x00;
+	regs[BMI260_FEAT_PAGE] = 0x00;
+	regs[BMI260_ACC_CONF] = 0xa8;
+	regs[BMI260_ACC_RANGE] = 0x02;
+	regs[BMI260_GYR_CONF] = 0xa9;
+	regs[BMI260_GYR_RANGE] = 0x00;
+	regs[BMI260_AUX_CONF] = 0x46;
+	regs[BMI260_FIFO_DOWNS] = 0x88;
+	regs[BMI260_FIFO_WTM_0] = 0x00;
+	regs[BMI260_FIFO_WTM_1] = 0x02;
+	regs[BMI260_FIFO_CONFIG_0] = 0x02;
+	regs[BMI260_FIFO_CONFIG_1] = 0x10;
+	regs[BMI260_SATURATION] = 0x00;
+	regs[BMI260_AUX_DEV_ID] = 0x20;
+	regs[BMI260_AUX_IF_CONF] = 0x83;
+	regs[BMI260_AUX_RD_ADDR] = 0x42;
+	regs[BMI260_AUX_WR_ADDR] = 0x4c;
+	regs[BMI260_AUX_WR_DATA] = 0x02;
+	regs[BMI260_ERR_REG_MSK] = 0x00;
+	regs[BMI260_INT1_IO_CTRL] = 0x00;
+	regs[BMI260_INT2_IO_CTRL] = 0x00;
+	regs[BMI260_INT_LATCH] = 0x00;
+	regs[BMI260_INT1_MAP_FEAT] = 0x00;
+	regs[BMI260_INT2_MAP_FEAT] = 0x00;
+	regs[BMI260_INT_MAP_DATA] = 0x00;
+	regs[BMI260_INIT_CTRL] = 0x00;
+	regs[BMI260_INIT_ADDR_0] = 0x00;
+	regs[BMI260_INIT_ADDR_1] = 0x00;
+	regs[BMI260_INIT_DATA] = 0x00;
+	regs[BMI260_INTERNAL_ERROR] = 0x00;
+	regs[BMI260_AUX_IF_TRIM] = 0x01;
+	regs[BMI260_GYR_CRT_CONF] = 0x00;
+	regs[BMI260_NVM_CONF] = 0x00;
+	regs[BMI260_IF_CONF] = 0x00;
+	regs[BMI260_DRV] = 0xff;
+	regs[BMI260_ACC_SELF_TEST] = 0x00;
+	regs[BMI260_GYR_SELF_TEST_AXES] = 0x00;
+	regs[BMI260_PWR_CONF] = 0x03;
+	regs[BMI260_PWR_CTRL] = 0x00;
+	regs[BMI260_CMD_REG] = 0x00;
 
 	/* Call generic reset */
 	tag_time = regs[BMI260_FIFO_CONFIG_0] & BMI260_FIFO_TIME_EN;
@@ -278,7 +278,8 @@ static int bmi260_emul_gyr_range_to_shift(uint8_t range)
  * @return 0 on success
  * @return -EIO on failure
  */
-static int bmi260_emul_start_cmd(uint8_t *regs, struct i2c_emul *emul, int cmd)
+static int bmi260_emul_start_cmd(uint8_t *regs, const struct emul *emul,
+				 int cmd)
 {
 	int time;
 
@@ -306,7 +307,7 @@ static int bmi260_emul_start_cmd(uint8_t *regs, struct i2c_emul *emul, int cmd)
  * @param regs Pointer to array of emulator's registers
  * @param emul Pointer to BMI emulator
  */
-static void bmi260_emul_end_cmd(uint8_t *regs, struct i2c_emul *emul)
+static void bmi260_emul_end_cmd(uint8_t *regs, const struct emul *emul)
 {
 	bool tag_time;
 	bool header;
@@ -339,7 +340,7 @@ static void bmi260_emul_end_cmd(uint8_t *regs, struct i2c_emul *emul)
  *
  * @return Currently accessed register
  */
-static int bmi260_emul_access_reg(struct i2c_emul *emul, int reg, int byte,
+static int bmi260_emul_access_reg(const struct emul *emul, int reg, int byte,
 				  bool read)
 {
 	/* Ignore first byte which sets starting register */
@@ -354,8 +355,7 @@ static int bmi260_emul_access_reg(struct i2c_emul *emul, int reg, int byte,
 	 */
 	if (reg <= BMI260_FIFO_DATA && reg + byte >= BMI260_FIFO_DATA) {
 		return BMI260_FIFO_DATA;
-	} else if (reg <= BMI260_INIT_DATA &&
-		   reg + byte >= BMI260_INIT_DATA) {
+	} else if (reg <= BMI260_INIT_DATA && reg + byte >= BMI260_INIT_DATA) {
 		return BMI260_INIT_DATA;
 	}
 
@@ -381,7 +381,7 @@ static int bmi260_emul_access_reg(struct i2c_emul *emul, int reg, int byte,
  * @return BMI_EMUL_ACCESS_E on RO register access
  * @return -EIO on error
  */
-static int bmi260_emul_handle_write(uint8_t *regs, struct i2c_emul *emul,
+static int bmi260_emul_handle_write(uint8_t *regs, const struct emul *emul,
 				    int reg, int byte, uint8_t val)
 {
 	uint8_t mask;
@@ -395,7 +395,6 @@ static int bmi260_emul_handle_write(uint8_t *regs, struct i2c_emul *emul,
 		return BMI_EMUL_ACCESS_E;
 	}
 
-
 	/* Stop on going command if required */
 	if (regs[BMI260_CMD_REG] != 0 && bmi_emul_is_cmd_end(emul)) {
 		bmi260_emul_end_cmd(regs, emul);
@@ -454,7 +453,7 @@ static int bmi260_emul_handle_write(uint8_t *regs, struct i2c_emul *emul,
  * @return BMI_EMUL_ACCESS_E on WO register access
  * @return -EIO on other error
  */
-static int bmi260_emul_handle_read(uint8_t *regs, struct i2c_emul *emul,
+static int bmi260_emul_handle_read(uint8_t *regs, const struct emul *emul,
 				   int reg, int byte, char *buf)
 {
 	uint16_t fifo_len;
@@ -513,8 +512,8 @@ static int bmi260_emul_handle_read(uint8_t *regs, struct i2c_emul *emul,
 			bmi_emul_state_to_reg(emul, acc_shift, gyr_shift,
 					      BMI260_ACC_X_L_G,
 					      BMI260_GYR_X_L_G,
-					      BMI260_SENSORTIME_0,
-					      acc_off_en, gyr_off_en);
+					      BMI260_SENSORTIME_0, acc_off_en,
+					      gyr_off_en);
 		}
 		break;
 	case BMI260_FIFO_LENGTH_0:
@@ -538,16 +537,12 @@ static int bmi260_emul_handle_read(uint8_t *regs, struct i2c_emul *emul,
 }
 
 /** Registers backed in NVM by BMI260 */
-const int bmi260_nvm_reg[] = {BMI260_AUX_IF_TRIM,
-			      BMI260_NV_CONF,
-			      BMI260_DRV,
-			      BMI260_OFFSET_ACC70,
-			      BMI260_OFFSET_ACC70 + 1,
-			      BMI260_OFFSET_ACC70 + 2,
-			      BMI260_OFFSET_GYR70,
-			      BMI260_OFFSET_GYR70 + 1,
-			      BMI260_OFFSET_GYR70 + 2,
-			      BMI260_OFFSET_EN_GYR98};
+const int bmi260_nvm_reg[] = {
+	BMI260_AUX_IF_TRIM,    BMI260_NV_CONF,		BMI260_DRV,
+	BMI260_OFFSET_ACC70,   BMI260_OFFSET_ACC70 + 1, BMI260_OFFSET_ACC70 + 2,
+	BMI260_OFFSET_GYR70,   BMI260_OFFSET_GYR70 + 1, BMI260_OFFSET_GYR70 + 2,
+	BMI260_OFFSET_EN_GYR98
+};
 
 /** Confguration of BMI260 */
 struct bmi_emul_type_data bmi260_emul = {
diff --git a/zephyr/emul/emul_clock_control.c b/zephyr/emul/emul_clock_control.c
index 397c4af32e..561298a705 100644
--- a/zephyr/emul/emul_clock_control.c
+++ b/zephyr/emul/emul_clock_control.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/emul/emul_common_i2c.c b/zephyr/emul/emul_common_i2c.c
index ae603f924a..70bc962c5f 100644
--- a/zephyr/emul/emul_common_i2c.c
+++ b/zephyr/emul/emul_common_i2c.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,63 +15,46 @@ LOG_MODULE_REGISTER(emul_common_i2c);
 #include "emul/emul_common_i2c.h"
 
 /** Check description in emul_common_i2c.h */
-int i2c_common_emul_lock_data(struct i2c_emul *emul, k_timeout_t timeout)
+int i2c_common_emul_lock_data(struct i2c_common_emul_data *common_data,
+			      k_timeout_t timeout)
 {
-	struct i2c_common_emul_data *data;
-
-	data = CONTAINER_OF(emul, struct i2c_common_emul_data, emul);
-
-	return k_mutex_lock(&data->data_mtx, timeout);
+	return k_mutex_lock(&common_data->data_mtx, timeout);
 }
 
 /** Check description in emul_common_i2c.h */
-int i2c_common_emul_unlock_data(struct i2c_emul *emul)
+int i2c_common_emul_unlock_data(struct i2c_common_emul_data *common_data)
 {
-	struct i2c_common_emul_data *data;
-
-	data = CONTAINER_OF(emul, struct i2c_common_emul_data, emul);
-
-	return k_mutex_unlock(&data->data_mtx);
+	return k_mutex_unlock(&common_data->data_mtx);
 }
 
 /** Check description in emul_common_i2c.h */
-void i2c_common_emul_set_write_func(struct i2c_emul *emul,
+void i2c_common_emul_set_write_func(struct i2c_common_emul_data *common_data,
 				    i2c_common_emul_write_func func, void *data)
 {
-	struct i2c_common_emul_data *emul_data;
-
-	emul_data = CONTAINER_OF(emul, struct i2c_common_emul_data, emul);
-	emul_data->write_func = func;
-	emul_data->write_func_data = data;
+	common_data->write_func = func;
+	common_data->write_func_data = data;
 }
 
 /** Check description in emul_common_i2c.h */
-void i2c_common_emul_set_read_func(struct i2c_emul *emul,
+void i2c_common_emul_set_read_func(struct i2c_common_emul_data *common_data,
 				   i2c_common_emul_read_func func, void *data)
 {
-	struct i2c_common_emul_data *emul_data;
-
-	emul_data = CONTAINER_OF(emul, struct i2c_common_emul_data, emul);
-	emul_data->read_func = func;
-	emul_data->read_func_data = data;
+	common_data->read_func = func;
+	common_data->read_func_data = data;
 }
 
 /** Check description in emul_common_i2c.h */
-void i2c_common_emul_set_read_fail_reg(struct i2c_emul *emul, int reg)
+void i2c_common_emul_set_read_fail_reg(struct i2c_common_emul_data *common_data,
+				       int reg)
 {
-	struct i2c_common_emul_data *data;
-
-	data = CONTAINER_OF(emul, struct i2c_common_emul_data, emul);
-	data->read_fail_reg = reg;
+	common_data->read_fail_reg = reg;
 }
 
 /** Check description in emul_common_i2c.h */
-void i2c_common_emul_set_write_fail_reg(struct i2c_emul *emul, int reg)
+void i2c_common_emul_set_write_fail_reg(
+	struct i2c_common_emul_data *common_data, int reg)
 {
-	struct i2c_common_emul_data *data;
-
-	data = CONTAINER_OF(emul, struct i2c_common_emul_data, emul);
-	data->write_fail_reg = reg;
+	common_data->write_fail_reg = reg;
 }
 
 /**
@@ -83,7 +66,7 @@ void i2c_common_emul_set_write_fail_reg(struct i2c_emul *emul, int reg)
  *
  * @retval start_write emulator callback return code
  */
-static int i2c_common_emul_start_write(struct i2c_emul *emul,
+static int i2c_common_emul_start_write(const struct emul *target,
 				       struct i2c_common_emul_data *data)
 {
 	int ret = 0;
@@ -92,7 +75,7 @@ static int i2c_common_emul_start_write(struct i2c_emul *emul,
 
 	if (data->start_write) {
 		k_mutex_lock(&data->data_mtx, K_FOREVER);
-		ret = data->start_write(emul, data->cur_reg);
+		ret = data->start_write(target, data->cur_reg);
 		k_mutex_unlock(&data->data_mtx);
 	}
 
@@ -108,14 +91,14 @@ static int i2c_common_emul_start_write(struct i2c_emul *emul,
  *
  * @retval finish_write emulator callback return code
  */
-static int i2c_common_emul_finish_write(struct i2c_emul *emul,
+static int i2c_common_emul_finish_write(const struct emul *target,
 					struct i2c_common_emul_data *data)
 {
 	int ret = 0;
 
 	if (data->finish_write) {
 		k_mutex_lock(&data->data_mtx, K_FOREVER);
-		ret = data->finish_write(emul, data->cur_reg, data->msg_byte);
+		ret = data->finish_write(target, data->cur_reg, data->msg_byte);
 		k_mutex_unlock(&data->data_mtx);
 	}
 
@@ -131,7 +114,7 @@ static int i2c_common_emul_finish_write(struct i2c_emul *emul,
  *
  * @retval start_read emulator callback return code
  */
-static int i2c_common_emul_start_read(struct i2c_emul *emul,
+static int i2c_common_emul_start_read(const struct emul *target,
 				      struct i2c_common_emul_data *data)
 {
 	int ret = 0;
@@ -140,7 +123,7 @@ static int i2c_common_emul_start_read(struct i2c_emul *emul,
 
 	if (data->start_read) {
 		k_mutex_lock(&data->data_mtx, K_FOREVER);
-		ret = data->start_read(emul, data->cur_reg);
+		ret = data->start_read(target, data->cur_reg);
 		k_mutex_unlock(&data->data_mtx);
 	}
 
@@ -156,14 +139,14 @@ static int i2c_common_emul_start_read(struct i2c_emul *emul,
  *
  * @retval finish_read emulator callback return code
  */
-static int i2c_common_emul_finish_read(struct i2c_emul *emul,
+static int i2c_common_emul_finish_read(const struct emul *target,
 				       struct i2c_common_emul_data *data)
 {
 	int ret = 0;
 
 	if (data->finish_read) {
 		k_mutex_lock(&data->data_mtx, K_FOREVER);
-		ret = data->finish_read(emul, data->cur_reg, data->msg_byte);
+		ret = data->finish_read(target, data->cur_reg, data->msg_byte);
 		k_mutex_unlock(&data->data_mtx);
 	}
 
@@ -183,7 +166,7 @@ static int i2c_common_emul_finish_read(struct i2c_emul *emul,
  * @retval 0 If successful
  * @retval -EIO General input / output error
  */
-static int i2c_common_emul_write_byte(struct i2c_emul *emul,
+static int i2c_common_emul_write_byte(const struct emul *target,
 				      struct i2c_common_emul_data *data,
 				      uint8_t val)
 {
@@ -191,8 +174,8 @@ static int i2c_common_emul_write_byte(struct i2c_emul *emul,
 
 	/* Custom user handler */
 	if (data->write_func) {
-		ret = data->write_func(emul, data->cur_reg, val, data->msg_byte,
-				       data->write_func_data);
+		ret = data->write_func(target, data->cur_reg, val,
+				       data->msg_byte, data->write_func_data);
 		if (ret < 0) {
 			return -EIO;
 		} else if (ret == 0) {
@@ -201,7 +184,7 @@ static int i2c_common_emul_write_byte(struct i2c_emul *emul,
 	}
 	/* Check if user wants to fail on accessed register */
 	if (data->access_reg) {
-		reg = data->access_reg(emul, data->cur_reg, data->msg_byte,
+		reg = data->access_reg(target, data->cur_reg, data->msg_byte,
 				       false /* = read */);
 	} else {
 		/* Ignore first (register address) byte */
@@ -215,7 +198,7 @@ static int i2c_common_emul_write_byte(struct i2c_emul *emul,
 	/* Emulator handler */
 	if (data->write_byte) {
 		k_mutex_lock(&data->data_mtx, K_FOREVER);
-		ret = data->write_byte(emul, data->cur_reg, val,
+		ret = data->write_byte(target, data->cur_reg, val,
 				       data->msg_byte);
 		k_mutex_unlock(&data->data_mtx);
 		if (ret) {
@@ -239,7 +222,7 @@ static int i2c_common_emul_write_byte(struct i2c_emul *emul,
  * @retval 0 If successful
  * @retval -EIO General input / output error
  */
-static int i2c_common_emul_read_byte(struct i2c_emul *emul,
+static int i2c_common_emul_read_byte(const struct emul *target,
 				     struct i2c_common_emul_data *data,
 				     uint8_t *val)
 {
@@ -247,8 +230,8 @@ static int i2c_common_emul_read_byte(struct i2c_emul *emul,
 
 	/* Custom user handler */
 	if (data->read_func) {
-		ret = data->read_func(emul, data->cur_reg, val, data->msg_byte,
-				      data->read_func_data);
+		ret = data->read_func(target, data->cur_reg, val,
+				      data->msg_byte, data->read_func_data);
 		if (ret < 0) {
 			return -EIO;
 		} else if (ret == 0) {
@@ -257,7 +240,7 @@ static int i2c_common_emul_read_byte(struct i2c_emul *emul,
 	}
 	/* Check if user wants to fail on accessed register */
 	if (data->access_reg) {
-		reg = data->access_reg(emul, data->cur_reg, data->msg_byte,
+		reg = data->access_reg(target, data->cur_reg, data->msg_byte,
 				       true /* = read */);
 	} else {
 		reg = data->cur_reg + data->msg_byte;
@@ -270,7 +253,8 @@ static int i2c_common_emul_read_byte(struct i2c_emul *emul,
 	/* Emulator handler */
 	if (data->read_byte) {
 		k_mutex_lock(&data->data_mtx, K_FOREVER);
-		ret = data->read_byte(emul, data->cur_reg, val, data->msg_byte);
+		ret = data->read_byte(target, data->cur_reg, val,
+				      data->msg_byte);
 		k_mutex_unlock(&data->data_mtx);
 		if (ret) {
 			return -EIO;
@@ -281,17 +265,15 @@ static int i2c_common_emul_read_byte(struct i2c_emul *emul,
 }
 
 /** Check description in emul_common_i2c.h */
-int i2c_common_emul_transfer(struct i2c_emul *emul, struct i2c_msg *msgs,
-			     int num_msgs, int addr)
+int i2c_common_emul_transfer_workhorse(const struct emul *target,
+				       struct i2c_common_emul_data *data,
+				       const struct i2c_common_emul_cfg *cfg,
+				       struct i2c_msg *msgs, int num_msgs,
+				       int addr)
 {
-	const struct i2c_common_emul_cfg *cfg;
-	struct i2c_common_emul_data *data;
 	bool read, stop;
 	int ret, i;
 
-	data = CONTAINER_OF(emul, struct i2c_common_emul_data, emul);
-	cfg = data->cfg;
-
 	if (cfg->addr != addr) {
 		LOG_ERR("Address mismatch, expected %02x, got %02x", cfg->addr,
 			addr);
@@ -308,11 +290,12 @@ int i2c_common_emul_transfer(struct i2c_emul *emul, struct i2c_msg *msgs,
 		case I2C_COMMON_EMUL_IN_WRITE:
 			if (read) {
 				data->msg_state = I2C_COMMON_EMUL_NONE_MSG;
-				ret = i2c_common_emul_finish_write(emul, data);
+				ret = i2c_common_emul_finish_write(target,
+								   data);
 				if (ret) {
 					return ret;
 				}
-				ret = i2c_common_emul_start_read(emul, data);
+				ret = i2c_common_emul_start_read(target, data);
 				if (ret) {
 					return ret;
 				}
@@ -321,7 +304,7 @@ int i2c_common_emul_transfer(struct i2c_emul *emul, struct i2c_msg *msgs,
 		case I2C_COMMON_EMUL_IN_READ:
 			if (!read) {
 				data->msg_state = I2C_COMMON_EMUL_NONE_MSG;
-				ret = i2c_common_emul_finish_read(emul, data);
+				ret = i2c_common_emul_finish_read(target, data);
 				if (ret) {
 					return ret;
 				}
@@ -331,7 +314,7 @@ int i2c_common_emul_transfer(struct i2c_emul *emul, struct i2c_msg *msgs,
 				}
 				/* Dispatch command/register address */
 				data->cur_reg = msgs->buf[0];
-				ret = i2c_common_emul_start_write(emul, data);
+				ret = i2c_common_emul_start_write(target, data);
 				if (ret) {
 					return ret;
 				}
@@ -339,7 +322,7 @@ int i2c_common_emul_transfer(struct i2c_emul *emul, struct i2c_msg *msgs,
 			break;
 		case I2C_COMMON_EMUL_NONE_MSG:
 			if (read) {
-				ret = i2c_common_emul_start_read(emul, data);
+				ret = i2c_common_emul_start_read(target, data);
 				if (ret) {
 					return ret;
 				}
@@ -350,15 +333,15 @@ int i2c_common_emul_transfer(struct i2c_emul *emul, struct i2c_msg *msgs,
 				}
 				/* Dispatch command/register address */
 				data->cur_reg = msgs->buf[0];
-				ret = i2c_common_emul_start_write(emul, data);
+				ret = i2c_common_emul_start_write(target, data);
 				if (ret) {
 					return ret;
 				}
 			}
 		}
 
-		data->msg_state = read ? I2C_COMMON_EMUL_IN_READ
-				       : I2C_COMMON_EMUL_IN_WRITE;
+		data->msg_state = read ? I2C_COMMON_EMUL_IN_READ :
+					 I2C_COMMON_EMUL_IN_WRITE;
 
 		if (stop) {
 			data->msg_state = I2C_COMMON_EMUL_NONE_MSG;
@@ -379,7 +362,7 @@ int i2c_common_emul_transfer(struct i2c_emul *emul, struct i2c_msg *msgs,
 			}
 			/* Dispatch write command */
 			for (; i < msgs->len; i++, data->msg_byte++) {
-				ret = i2c_common_emul_write_byte(emul, data,
+				ret = i2c_common_emul_write_byte(target, data,
 								 msgs->buf[i]);
 				if (ret) {
 					return ret;
@@ -387,7 +370,8 @@ int i2c_common_emul_transfer(struct i2c_emul *emul, struct i2c_msg *msgs,
 			}
 			/* Finish write command */
 			if (stop) {
-				ret = i2c_common_emul_finish_write(emul, data);
+				ret = i2c_common_emul_finish_write(target,
+								   data);
 				if (ret) {
 					return ret;
 				}
@@ -395,8 +379,8 @@ int i2c_common_emul_transfer(struct i2c_emul *emul, struct i2c_msg *msgs,
 		} else {
 			/* Dispatch read command */
 			for (i = 0; i < msgs->len; i++, data->msg_byte++) {
-				ret = i2c_common_emul_read_byte(emul, data,
-							       &(msgs->buf[i]));
+				ret = i2c_common_emul_read_byte(
+					target, data, &(msgs->buf[i]));
 				if (ret) {
 					return ret;
 				}
@@ -404,7 +388,7 @@ int i2c_common_emul_transfer(struct i2c_emul *emul, struct i2c_msg *msgs,
 
 			/* Finish read command */
 			if (stop) {
-				ret = i2c_common_emul_finish_read(emul, data);
+				ret = i2c_common_emul_finish_read(target, data);
 				if (ret) {
 					return ret;
 				}
@@ -416,6 +400,20 @@ int i2c_common_emul_transfer(struct i2c_emul *emul, struct i2c_msg *msgs,
 }
 
 /** Check description in emul_common_i2c.h */
+int i2c_common_emul_transfer(const struct emul *target, struct i2c_msg *msgs,
+			     int num_msgs, int addr)
+{
+	const struct i2c_common_emul_cfg *cfg;
+	struct i2c_common_emul_data *data;
+
+	data = target->data;
+	cfg = target->cfg;
+
+	return i2c_common_emul_transfer_workhorse(target, data, cfg, msgs,
+						  num_msgs, addr);
+}
+
+/** Check description in emul_common_i2c.h */
 void i2c_common_emul_init(struct i2c_common_emul_data *data)
 {
 	data->msg_state = I2C_COMMON_EMUL_NONE_MSG;
@@ -434,3 +432,14 @@ void i2c_common_emul_init(struct i2c_common_emul_data *data)
 struct i2c_emul_api i2c_common_emul_api = {
 	.transfer = i2c_common_emul_transfer,
 };
+
+static int i2c_common_emul_transfer_noop(const struct emul *target,
+					 struct i2c_msg *msgs, int num_msgs,
+					 int addr)
+{
+	return 0;
+}
+
+struct i2c_emul_api i2c_common_emul_noop = {
+	.transfer = i2c_common_emul_transfer_noop,
+};
diff --git a/zephyr/emul/emul_flash.c b/zephyr/emul/emul_flash.c
index 2fa88916f3..0efc690fd4 100644
--- a/zephyr/emul/emul_flash.c
+++ b/zephyr/emul/emul_flash.c
@@ -1,10 +1,11 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #define DT_DRV_COMPAT cros_ec_flash_emul
 
+#include <zephyr/drivers/flash.h>
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(emul_flash);
 
@@ -14,74 +15,183 @@ LOG_MODULE_REGISTER(emul_flash);
 #include <drivers/cros_flash.h>
 #include <zephyr/sys/__assert.h>
 
-struct flash_emul_data {};
+#include "flash.h"
+
+struct flash_emul_data {
+	const struct device *flash_dev;
+};
 
 struct flash_emul_cfg {
-	/** Label of the device being emulated */
-	const char *dev_label;
 	/** Pointer to run-time data */
 	struct flash_emul_data *data;
 };
 
-void system_jump_to_booter(void)
-{
-}
+#define FLASH_DEV DT_CHOSEN(zephyr_flash_controller)
 
-uint32_t system_get_lfw_address(void)
-{
-	uint32_t jump_addr = (uint32_t)system_jump_to_booter;
-	return jump_addr;
-}
+#define DRV_DATA(dev) ((struct flash_emul_data *)(dev)->data)
 
-enum ec_image system_get_shrspi_image_copy(void)
-{
-	return EC_IMAGE_RO;
-}
+/* Variables to emulate the protection */
+bool ro_protected, all_protected;
 
-void system_set_image_copy(enum ec_image copy)
+static int cros_flash_emul_init(const struct device *dev)
 {
+	struct flash_emul_data *data = DRV_DATA(dev);
+
+	data->flash_dev = DEVICE_DT_GET(FLASH_DEV);
+	if (!device_is_ready(data->flash_dev)) {
+		LOG_ERR("%s device not ready", data->flash_dev->name);
+		return -ENODEV;
+	}
+
+	return EC_SUCCESS;
 }
 
-static int cros_flash_emul_init(const struct device *dev)
+static int flash_check_writable_range(int offset, int size)
 {
-	return 0;
+	/* Check out of range */
+	if (offset + size > CONFIG_FLASH_SIZE_BYTES) {
+		return EC_ERROR_INVAL;
+	}
+
+	/* Check RO protected and within the RO range */
+	if (ro_protected &&
+	    MAX(CONFIG_WP_STORAGE_OFF, offset) <
+		    MIN(CONFIG_WP_STORAGE_OFF + CONFIG_WP_STORAGE_SIZE,
+			offset + size)) {
+		return EC_ERROR_ACCESS_DENIED;
+	}
+
+	return EC_SUCCESS;
 }
 
 static int cros_flash_emul_write(const struct device *dev, int offset, int size,
 				 const char *src_data)
 {
-	__ASSERT(false, "Not implemented");
-	return -EINVAL;
+	int ret = 0;
+	struct flash_emul_data *data = DRV_DATA(dev);
+
+	/* Check protection */
+	if (all_protected) {
+		return EC_ERROR_ACCESS_DENIED;
+	}
+
+	if (flash_check_writable_range(offset, size)) {
+		return EC_ERROR_ACCESS_DENIED;
+	}
+
+	/* Check invalid data pointer? */
+	if (src_data == 0) {
+		return -EINVAL;
+	}
+
+	/* Lock physical flash operations */
+	crec_flash_lock_mapped_storage(1);
+
+	ret = flash_write(data->flash_dev, offset, src_data, size);
+
+	/* Unlock physical flash operations */
+	crec_flash_lock_mapped_storage(0);
+
+	return ret;
 }
 
 static int cros_flash_emul_erase(const struct device *dev, int offset, int size)
 {
-	__ASSERT(false, "Not implemented");
-	return -EINVAL;
+	int ret = 0;
+	struct flash_emul_data *data = DRV_DATA(dev);
+
+	/* Check protection */
+	if (all_protected) {
+		return EC_ERROR_ACCESS_DENIED;
+	}
+
+	if (flash_check_writable_range(offset, size)) {
+		return EC_ERROR_ACCESS_DENIED;
+	}
+
+	/* Address must be aligned to erase size */
+	if ((offset % CONFIG_FLASH_ERASE_SIZE) != 0) {
+		return -EINVAL;
+	}
+
+	/* Erase size must be a non-zero multiple of sectors */
+	if ((size == 0) || (size % CONFIG_FLASH_ERASE_SIZE) != 0) {
+		return -EINVAL;
+	}
+
+	/* Lock physical flash operations */
+	crec_flash_lock_mapped_storage(1);
+
+	ret = flash_erase(data->flash_dev, offset, size);
+
+	/* Unlock physical flash operations */
+	crec_flash_lock_mapped_storage(0);
+
+	return ret;
 }
 
 static int cros_flash_emul_get_protect(const struct device *dev, int bank)
 {
-	__ASSERT(false, "Not implemented");
-	return -EINVAL;
+	if (all_protected) {
+		return EC_ERROR_ACCESS_DENIED;
+	}
+	if (ro_protected && bank >= WP_BANK_OFFSET &&
+	    bank < WP_BANK_OFFSET + WP_BANK_COUNT) {
+		return EC_ERROR_ACCESS_DENIED;
+	}
+
+	return EC_SUCCESS;
 }
 
 static uint32_t cros_flash_emul_get_protect_flags(const struct device *dev)
 {
-	return EC_FLASH_PROTECT_ERROR_UNKNOWN;
+	uint32_t flags = 0;
+
+	if (ro_protected) {
+		flags |= EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW;
+	}
+	if (all_protected) {
+		flags |= EC_FLASH_PROTECT_ALL_NOW;
+	}
+	return flags;
 }
 
 static int cros_flash_emul_protect_at_boot(const struct device *dev,
 					   uint32_t new_flags)
 {
-	__ASSERT(false, "Not implemented");
-	return -EINVAL;
+	if ((new_flags & (EC_FLASH_PROTECT_RO_AT_BOOT |
+			  EC_FLASH_PROTECT_ALL_AT_BOOT)) == 0) {
+		/* Clear protection if allowed */
+		if (crec_flash_get_protect() & EC_FLASH_PROTECT_GPIO_ASSERTED) {
+			return EC_ERROR_ACCESS_DENIED;
+		}
+
+		ro_protected = all_protected = false;
+		return EC_SUCCESS;
+	}
+
+	ro_protected = true;
+
+	if (new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT) {
+		all_protected = true;
+	}
+
+	return EC_SUCCESS;
 }
 
 static int cros_flash_emul_protect_now(const struct device *dev, int all)
 {
-	__ASSERT(false, "Not implemented");
-	return -EINVAL;
+	/* Emulate ALL_NOW only */
+	if (all) {
+		all_protected = true;
+	}
+
+	return EC_SUCCESS;
+}
+
+void cros_flash_emul_protect_reset(void)
+{
+	ro_protected = all_protected = false;
 }
 
 static int cros_flash_emul_get_jedec_id(const struct device *dev,
@@ -98,7 +208,6 @@ static int cros_flash_emul_get_status(const struct device *dev, uint8_t *sr1,
 	return -EINVAL;
 }
 
-
 static const struct cros_flash_driver_api emul_cros_flash_driver_api = {
 	.init = cros_flash_emul_init,
 	.physical_write = cros_flash_emul_write,
@@ -118,17 +227,14 @@ static int flash_emul_init(const struct device *dev)
 	return 0;
 }
 
-#define FLASH_EMUL(n)                                                      \
-	static struct flash_emul_data flash_emul_data_##n = {              \
-	};                                                                 \
-									   \
-	static const struct flash_emul_cfg flash_emul_cfg_##n = {          \
-		.dev_label = DT_INST_LABEL(n),                             \
-		.data = &flash_emul_data_##n,                              \
-	};                                                                 \
-	DEVICE_DT_INST_DEFINE(n, flash_emul_init, NULL,                    \
-			      &flash_emul_data_##n, &flash_emul_cfg_##n,   \
-			      PRE_KERNEL_1,                                \
-			      CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,         \
+#define FLASH_EMUL(n)                                                         \
+	static struct flash_emul_data flash_emul_data_##n = {};               \
+                                                                              \
+	static const struct flash_emul_cfg flash_emul_cfg_##n = {             \
+		.data = &flash_emul_data_##n,                                 \
+	};                                                                    \
+	DEVICE_DT_INST_DEFINE(n, flash_emul_init, NULL, &flash_emul_data_##n, \
+			      &flash_emul_cfg_##n, PRE_KERNEL_1,              \
+			      CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,            \
 			      &emul_cros_flash_driver_api)
 DT_INST_FOREACH_STATUS_OKAY(FLASH_EMUL);
diff --git a/zephyr/emul/emul_isl923x.c b/zephyr/emul/emul_isl923x.c
index 9896804f7f..1ecb9e79f9 100644
--- a/zephyr/emul/emul_isl923x.c
+++ b/zephyr/emul/emul_isl923x.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,7 +11,7 @@
 #include <zephyr/drivers/emul.h>
 #include <errno.h>
 #include <zephyr/sys/__assert.h>
-#include <ztest.h>
+#include <zephyr/ztest.h>
 
 #include "driver/charger/isl923x.h"
 #include "driver/charger/isl923x_public.h"
@@ -19,14 +19,11 @@
 #include "emul/emul_isl923x.h"
 #include "emul/emul_smart_battery.h"
 #include "i2c.h"
+#include "emul/emul_stub_device.h"
 
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(isl923x_emul, CONFIG_ISL923X_EMUL_LOG_LEVEL);
 
-#define ISL923X_DATA_FROM_I2C_EMUL(_emul)                                    \
-	CONTAINER_OF(CONTAINER_OF(_emul, struct i2c_common_emul_data, emul), \
-		     struct isl923x_emul_data, common)
-
 /** Mask used for the charge current register */
 #define REG_CHG_CURRENT_MASK GENMASK(12, 2)
 
@@ -71,7 +68,7 @@ LOG_MODULE_REGISTER(isl923x_emul, CONFIG_ISL923X_EMUL_LOG_LEVEL);
 
 #define DEFAULT_R_SNS 10
 #define R_SNS CONFIG_CHARGER_SENSE_RESISTOR
-#define REG_TO_CURRENT(REG) ((REG) * DEFAULT_R_SNS / R_SNS)
+#define REG_TO_CURRENT(REG) ((REG)*DEFAULT_R_SNS / R_SNS)
 
 struct isl923x_emul_data {
 	/** Common I2C data */
@@ -113,7 +110,7 @@ struct isl923x_emul_data {
 	/** Emulated input voltage register */
 	uint16_t input_voltage_reg;
 	/** Pointer to battery emulator. */
-	int battery_ord;
+	const struct emul *battery_emul;
 };
 
 struct isl923x_emul_cfg {
@@ -128,11 +125,10 @@ const struct device *isl923x_emul_get_parent(const struct emul *emulator)
 	return data->common.i2c;
 }
 
-struct i2c_emul *isl923x_emul_get_i2c_emul(const struct emul *emulator)
+const struct i2c_common_emul_cfg *
+isl923x_emul_get_cfg(const struct emul *emulator)
 {
-	struct isl923x_emul_data *data = emulator->data;
-
-	return &(data->common.emul);
+	return emulator->cfg;
 }
 
 static void isl923x_emul_reset(struct isl923x_emul_data *data)
@@ -145,11 +141,11 @@ void isl923x_emul_reset_registers(const struct emul *emulator)
 {
 	struct isl923x_emul_data *data = emulator->data;
 	struct i2c_common_emul_data common_backup = data->common;
-	int battery_ord = data->battery_ord;
+	const struct emul *battery_emul = data->battery_emul;
 
 	memset(data, 0, sizeof(struct isl923x_emul_data));
 	data->common = common_backup;
-	data->battery_ord = battery_ord;
+	data->battery_emul = battery_emul;
 }
 
 void isl923x_emul_set_manufacturer_id(const struct emul *emulator,
@@ -160,8 +156,7 @@ void isl923x_emul_set_manufacturer_id(const struct emul *emulator,
 	data->manufacturer_id_reg = manufacturer_id;
 }
 
-void isl923x_emul_set_device_id(const struct emul *emulator,
-				uint16_t device_id)
+void isl923x_emul_set_device_id(const struct emul *emulator, uint16_t device_id)
 {
 	struct isl923x_emul_data *data = emulator->data;
 
@@ -215,10 +210,10 @@ void raa489000_emul_set_acok_pin(const struct emul *emulator, uint16_t value)
 		break;                                           \
 	} while (0)
 
-static int isl923x_emul_read_byte(struct i2c_emul *emul, int reg, uint8_t *val,
-				  int bytes)
+static int isl923x_emul_read_byte(const struct emul *emul, int reg,
+				  uint8_t *val, int bytes)
 {
-	struct isl923x_emul_data *data = ISL923X_DATA_FROM_I2C_EMUL(emul);
+	struct isl923x_emul_data *data = emul->data;
 
 	switch (reg) {
 	case ISL923X_REG_CHG_CURRENT:
@@ -283,12 +278,12 @@ static int isl923x_emul_read_byte(struct i2c_emul *emul, int reg, uint8_t *val,
 	return 0;
 }
 
-uint16_t isl923x_emul_peek_reg(struct i2c_emul *i2c_emul, int reg)
+uint16_t isl923x_emul_peek_reg(const struct emul *emul, int reg)
 {
 	uint8_t bytes[2];
 
-	isl923x_emul_read_byte(i2c_emul, reg, &bytes[0], 0);
-	isl923x_emul_read_byte(i2c_emul, reg, &bytes[1], 1);
+	isl923x_emul_read_byte(emul, reg, &bytes[0], 0);
+	isl923x_emul_read_byte(emul, reg, &bytes[1], 1);
 
 	return bytes[1] << 8 | bytes[0];
 }
@@ -303,10 +298,10 @@ uint16_t isl923x_emul_peek_reg(struct i2c_emul *i2c_emul, int reg)
 			(REG) |= ((VAL) << 8) & (MASK);        \
 	} while (0)
 
-static int isl923x_emul_write_byte(struct i2c_emul *emul, int reg, uint8_t val,
-				   int bytes)
+static int isl923x_emul_write_byte(const struct emul *emul, int reg,
+				   uint8_t val, int bytes)
 {
-	struct isl923x_emul_data *data = ISL923X_DATA_FROM_I2C_EMUL(emul);
+	struct isl923x_emul_data *data = emul->data;
 
 	switch (reg) {
 	case ISL923X_REG_CHG_CURRENT:
@@ -366,38 +361,42 @@ static int isl923x_emul_write_byte(struct i2c_emul *emul, int reg, uint8_t val,
 		break;
 	case ISL9238_REG_INPUT_VOLTAGE:
 		WRITE_REG_16(data->input_voltage_reg, bytes, val,
-					REG_INPUT_VOLTAGE_MASK);
+			     REG_INPUT_VOLTAGE_MASK);
 		break;
 	default:
 		__ASSERT(false, "Attempt to write unimplemented reg 0x%02x",
 			 reg);
 		return -EINVAL;
 	}
+
 	return 0;
 }
 
-static int isl923x_emul_finish_write(struct i2c_emul *emul, int reg, int bytes)
+static int isl923x_emul_finish_write(const struct emul *emul, int reg,
+				     int bytes)
 {
-	struct isl923x_emul_data *data = ISL923X_DATA_FROM_I2C_EMUL(emul);
-	struct i2c_emul *battery_i2c_emul;
+	struct isl923x_emul_data *data = emul->data;
 	struct sbat_emul_bat_data *bat;
 	int16_t current;
 
+	/* This write only selected register for I2C read message */
+	if (bytes < 2) {
+		return 0;
+	}
+
 	switch (reg) {
 	case ISL923X_REG_CHG_CURRENT:
 		/* Write current to battery. */
-		if (data->battery_ord >= 0) {
-			battery_i2c_emul = sbat_emul_get_ptr(data->battery_ord);
-			if (battery_i2c_emul != NULL) {
-				bat = sbat_emul_get_bat_data(battery_i2c_emul);
-				if (bat != NULL) {
-					current = REG_TO_CURRENT(
-						data->current_limit_reg);
-					if (current > 0)
-						bat->cur = current;
-					else
-						bat->cur = -5;
-				}
+		if (data->battery_emul != NULL) {
+			/* We only have a single battery */
+			bat = sbat_emul_get_bat_data(data->battery_emul);
+			if (bat != NULL) {
+				current =
+					REG_TO_CURRENT(data->current_limit_reg);
+				if (current > 0)
+					bat->cur = current;
+				else
+					bat->cur = -5;
 			}
 		}
 		break;
@@ -408,40 +407,34 @@ static int isl923x_emul_finish_write(struct i2c_emul *emul, int reg, int bytes)
 static int emul_isl923x_init(const struct emul *emul,
 			     const struct device *parent)
 {
-	const struct isl923x_emul_cfg *cfg = emul->cfg;
 	struct isl923x_emul_data *data = emul->data;
 
-	data->common.emul.api = &i2c_common_emul_api;
-	data->common.emul.addr = cfg->common.addr;
-	data->common.emul.parent = emul;
 	data->common.i2c = parent;
-	data->common.cfg = &cfg->common;
 	i2c_common_emul_init(&data->common);
 
-	return i2c_emul_register(parent, emul->dev_label, &data->common.emul);
+	return 0;
 }
 
-#define INIT_ISL923X(n)                                                        \
+#define INIT_ISL923X(n)                                                          \
 	static struct isl923x_emul_data isl923x_emul_data_##n = {              \
 		.common = {                                                    \
 			.write_byte = isl923x_emul_write_byte,                 \
 			.read_byte = isl923x_emul_read_byte,                   \
 			.finish_write = isl923x_emul_finish_write,             \
 		},                                                             \
-		.battery_ord = COND_CODE_1(                                    \
+		.battery_emul = COND_CODE_1(                                   \
 			DT_INST_NODE_HAS_PROP(n, battery),                     \
-			(DT_DEP_ORD(DT_INST_PROP(n, battery))),                \
-			(-1)),                                                 \
-	};                                                                     \
+			(EMUL_DT_GET(DT_INST_PROP(n, battery))),               \
+			(NULL)),                                               \
+	}; \
 	static struct isl923x_emul_cfg isl923x_emul_cfg_##n = {                \
 	.common = {                                                            \
-		.i2c_label = DT_INST_BUS_LABEL(n),                             \
-		.dev_label = DT_INST_LABEL(n),                                 \
+		.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)),                \
 		.addr = DT_INST_REG_ADDR(n),                                   \
 		},                                                             \
-	};                                                                     \
-	EMUL_DEFINE(emul_isl923x_init, DT_DRV_INST(n), &isl923x_emul_cfg_##n,  \
-		    &isl923x_emul_data_##n)
+	}; \
+	EMUL_DT_INST_DEFINE(n, emul_isl923x_init, &isl923x_emul_data_##n,        \
+			    &isl923x_emul_cfg_##n, &i2c_common_emul_api)
 
 DT_INST_FOREACH_STATUS_OKAY(INIT_ISL923X)
 
@@ -460,3 +453,11 @@ static void emul_isl923x_reset_before(const struct ztest_unit_test *test,
 }
 ZTEST_RULE(emul_isl923x_reset, emul_isl923x_reset_before, NULL);
 #endif /* CONFIG_ZTEST_NEW_API */
+
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
+
+struct i2c_common_emul_data *
+emul_isl923x_get_i2c_common_data(const struct emul *emul)
+{
+	return emul->data;
+}
diff --git a/zephyr/emul/emul_kb_raw.c b/zephyr/emul/emul_kb_raw.c
index 238c9673bb..1fdd93d1a0 100644
--- a/zephyr/emul/emul_kb_raw.c
+++ b/zephyr/emul/emul_kb_raw.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -97,6 +97,16 @@ int emul_kb_raw_set_kbstate(const struct device *dev, uint8_t row, uint8_t col,
 	return 0;
 }
 
+void emul_kb_raw_reset(const struct device *dev)
+{
+	const struct kb_raw_emul_cfg *cfg = dev->config;
+	struct kb_raw_emul_data *data = dev->data;
+
+	for (int col = 0; col < cfg->cols; col++) {
+		data->matrix[col] = 0;
+	}
+}
+
 static const struct cros_kb_raw_driver_api emul_kb_raw_driver_api = {
 	.init = emul_kb_raw_init,
 	.drive_colum = emul_kb_raw_drive_column,
@@ -109,9 +119,9 @@ static const struct cros_kb_raw_driver_api emul_kb_raw_driver_api = {
 	static struct kb_raw_emul_data kb_raw_emul_data_##n = {            \
 		.matrix = kb_raw_emul_matrix_##n,                          \
 	};                                                                 \
-									   \
+                                                                           \
 	static const struct kb_raw_emul_cfg kb_raw_emul_cfg_##n = {        \
-		.dev_label = DT_INST_LABEL(n),                             \
+		.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)),            \
 		.data = &kb_raw_emul_data_##n,                             \
 		.rows = DT_INST_PROP(n, rows),                             \
 		.cols = DT_INST_PROP(n, cols),                             \
diff --git a/zephyr/emul/emul_lis2dw12.c b/zephyr/emul/emul_lis2dw12.c
index 38bf6572b1..bdc4b50358 100644
--- a/zephyr/emul/emul_lis2dw12.c
+++ b/zephyr/emul/emul_lis2dw12.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,14 +16,11 @@
 #include "emul/emul_common_i2c.h"
 #include "emul/emul_lis2dw12.h"
 #include "i2c.h"
+#include "emul/emul_stub_device.h"
 
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(lis2dw12_emul, CONFIG_LIS2DW12_EMUL_LOG_LEVEL);
 
-#define LIS2DW12_DATA_FROM_I2C_EMUL(_emul)                                   \
-	CONTAINER_OF(CONTAINER_OF(_emul, struct i2c_common_emul_data, emul), \
-		     struct lis2dw12_emul_data, common)
-
 struct lis2dw12_emul_data {
 	/** Common I2C data */
 	struct i2c_common_emul_data common;
@@ -50,24 +47,16 @@ struct lis2dw12_emul_cfg {
 	struct i2c_common_emul_cfg common;
 };
 
-struct i2c_emul *lis2dw12_emul_to_i2c_emul(const struct emul *emul)
-{
-	struct lis2dw12_emul_data *data = emul->data;
-
-	return &(data->common.emul);
-}
-
 void lis2dw12_emul_reset(const struct emul *emul)
 {
 	struct lis2dw12_emul_data *data = emul->data;
-	struct i2c_emul *i2c_emul = lis2dw12_emul_to_i2c_emul(emul);
 
-	i2c_common_emul_set_read_fail_reg(i2c_emul,
+	i2c_common_emul_set_read_fail_reg(&data->common,
 					  I2C_COMMON_EMUL_NO_FAIL_REG);
-	i2c_common_emul_set_write_fail_reg(i2c_emul,
+	i2c_common_emul_set_write_fail_reg(&data->common,
 					   I2C_COMMON_EMUL_NO_FAIL_REG);
-	i2c_common_emul_set_read_func(i2c_emul, NULL, NULL);
-	i2c_common_emul_set_write_func(i2c_emul, NULL, NULL);
+	i2c_common_emul_set_read_func(&data->common, NULL, NULL);
+	i2c_common_emul_set_write_func(&data->common, NULL, NULL);
 	data->who_am_i_reg = LIS2DW12_WHO_AM_I;
 	data->ctrl1_reg = 0;
 	data->ctrl2_reg = 0;
@@ -93,10 +82,10 @@ uint32_t lis2dw12_emul_get_soft_reset_count(const struct emul *emul)
 	return data->soft_reset_count;
 }
 
-static int lis2dw12_emul_read_byte(struct i2c_emul *emul, int reg, uint8_t *val,
-				   int bytes)
+static int lis2dw12_emul_read_byte(const struct emul *emul, int reg,
+				   uint8_t *val, int bytes)
 {
-	struct lis2dw12_emul_data *data = LIS2DW12_DATA_FROM_I2C_EMUL(emul);
+	struct lis2dw12_emul_data *data = emul->data;
 
 	switch (reg) {
 	case LIS2DW12_WHO_AM_I_REG:
@@ -158,7 +147,7 @@ static int lis2dw12_emul_read_byte(struct i2c_emul *emul, int reg, uint8_t *val,
 	return 0;
 }
 
-uint8_t lis2dw12_emul_peek_reg(struct i2c_emul *emul, int reg)
+uint8_t lis2dw12_emul_peek_reg(const struct emul *emul, int reg)
 {
 	__ASSERT(emul, "emul is NULL");
 
@@ -171,7 +160,7 @@ uint8_t lis2dw12_emul_peek_reg(struct i2c_emul *emul, int reg)
 	return val;
 }
 
-uint8_t lis2dw12_emul_peek_odr(struct i2c_emul *emul)
+uint8_t lis2dw12_emul_peek_odr(const struct emul *emul)
 {
 	__ASSERT(emul, "emul is NULL");
 
@@ -181,7 +170,7 @@ uint8_t lis2dw12_emul_peek_odr(struct i2c_emul *emul)
 	       __builtin_ctz(LIS2DW12_ACC_ODR_MASK);
 }
 
-uint8_t lis2dw12_emul_peek_mode(struct i2c_emul *emul)
+uint8_t lis2dw12_emul_peek_mode(const struct emul *emul)
 {
 	__ASSERT(emul, "emul is NULL");
 
@@ -191,7 +180,7 @@ uint8_t lis2dw12_emul_peek_mode(struct i2c_emul *emul)
 	       __builtin_ctz(LIS2DW12_ACC_MODE_MASK);
 }
 
-uint8_t lis2dw12_emul_peek_lpmode(struct i2c_emul *emul)
+uint8_t lis2dw12_emul_peek_lpmode(const struct emul *emul)
 {
 	__ASSERT(emul, "emul is NULL");
 
@@ -200,10 +189,10 @@ uint8_t lis2dw12_emul_peek_lpmode(struct i2c_emul *emul)
 	return (reg & LIS2DW12_ACC_LPMODE_MASK);
 }
 
-static int lis2dw12_emul_write_byte(struct i2c_emul *emul, int reg, uint8_t val,
-				    int bytes)
+static int lis2dw12_emul_write_byte(const struct emul *emul, int reg,
+				    uint8_t val, int bytes)
 {
-	struct lis2dw12_emul_data *data = LIS2DW12_DATA_FROM_I2C_EMUL(emul);
+	struct lis2dw12_emul_data *data = emul->data;
 
 	switch (reg) {
 	case LIS2DW12_WHO_AM_I_REG:
@@ -250,18 +239,12 @@ static int lis2dw12_emul_write_byte(struct i2c_emul *emul, int reg, uint8_t val,
 static int emul_lis2dw12_init(const struct emul *emul,
 			      const struct device *parent)
 {
-	const struct lis2dw12_emul_cfg *lis2dw12_cfg = emul->cfg;
-	const struct i2c_common_emul_cfg *cfg = &(lis2dw12_cfg->common);
 	struct lis2dw12_emul_data *data = emul->data;
 
-	data->common.emul.api = &i2c_common_emul_api;
-	data->common.emul.addr = cfg->addr;
-	data->common.emul.parent = emul;
 	data->common.i2c = parent;
-	data->common.cfg = cfg;
 	i2c_common_emul_init(&data->common);
 
-	return i2c_emul_register(parent, emul->dev_label, &data->common.emul);
+	return 0;
 }
 
 int lis2dw12_emul_set_accel_reading(const struct emul *emul, intv3_t reading)
@@ -295,21 +278,27 @@ void lis2dw12_emul_clear_accel_reading(const struct emul *emul)
 	data->status_reg &= ~LIS2DW12_STS_DRDY_UP;
 }
 
-#define INIT_LIS2DW12(n)                                                  \
+#define INIT_LIS2DW12(n)                                                    \
 	static struct lis2dw12_emul_data lis2dw12_emul_data_##n = {       \
 		.common = {                                               \
 			.write_byte = lis2dw12_emul_write_byte,           \
 			.read_byte = lis2dw12_emul_read_byte,             \
 		},                                                        \
-	};                                                                \
+	}; \
 	static const struct lis2dw12_emul_cfg lis2dw12_emul_cfg_##n = {   \
 		.common = {                                               \
-			.i2c_label = DT_INST_BUS_LABEL(n),                \
-			.dev_label = DT_INST_LABEL(n),                    \
+			.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)),   \
 			.addr = DT_INST_REG_ADDR(n),                      \
 		},                                                        \
-	};                                                                \
-	EMUL_DEFINE(emul_lis2dw12_init, DT_DRV_INST(n),                   \
-		    &lis2dw12_emul_cfg_##n, &lis2dw12_emul_data_##n)
+	}; \
+	EMUL_DT_INST_DEFINE(n, emul_lis2dw12_init, &lis2dw12_emul_data_##n, \
+			    &lis2dw12_emul_cfg_##n, &i2c_common_emul_api)
 
 DT_INST_FOREACH_STATUS_OKAY(INIT_LIS2DW12)
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
+
+struct i2c_common_emul_data *
+emul_lis2dw12_get_i2c_common_data(const struct emul *emul)
+{
+	return emul->data;
+}
diff --git a/zephyr/emul/emul_ln9310.c b/zephyr/emul/emul_ln9310.c
index f2f92154f4..bd6d41bce3 100644
--- a/zephyr/emul/emul_ln9310.c
+++ b/zephyr/emul/emul_ln9310.c
@@ -1,39 +1,36 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #define DT_DRV_COMPAT cros_ln9310_emul
 
+#include <errno.h>
 #include <zephyr/device.h>
 #include <zephyr/devicetree/gpio.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/gpio.h>
 #include <zephyr/drivers/gpio/gpio_emul.h>
 #include <zephyr/drivers/i2c.h>
 #include <zephyr/drivers/i2c_emul.h>
-#include <zephyr/drivers/emul.h>
-#include <errno.h>
 #include <zephyr/sys/__assert.h>
 
 #include "driver/ln9310.h"
 #include "emul/emul_common_i2c.h"
 #include "emul/emul_ln9310.h"
+#include "hooks.h"
 #include "i2c.h"
+#include "emul/emul_stub_device.h"
 
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(ln9310_emul, CONFIG_LN9310_EMUL_LOG_LEVEL);
 
-#define LN9310_DATA_FROM_I2C_EMUL(_emul)                                     \
-	CONTAINER_OF(CONTAINER_OF(_emul, struct i2c_common_emul_data, emul), \
-		     struct ln9310_emul_data, common)
-
 enum functional_mode {
 	/* TODO shutdown_mode, */
 	/* TODO bypass, */
 	FUNCTIONAL_MODE_STANDBY = LN9310_SYS_STANDBY,
-	FUNCTIONAL_MODE_SWITCHING_21 =
-		LN9310_SYS_SWITCHING21_ACTIVE,
-	FUNCTIONAL_MODE_SWITCHING_31 =
-		LN9310_SYS_SWITCHING31_ACTIVE
+	FUNCTIONAL_MODE_SWITCHING_21 = LN9310_SYS_SWITCHING21_ACTIVE,
+	FUNCTIONAL_MODE_SWITCHING_31 = LN9310_SYS_SWITCHING31_ACTIVE
 };
 
 struct ln9310_emul_data {
@@ -251,20 +248,20 @@ enum battery_cell_type board_get_battery_cell_type(void)
 	return data->battery_cell_type;
 }
 
-static int ln9310_emul_start_write(struct i2c_emul *emul, int reg)
+static int ln9310_emul_start_write(const struct emul *emul, int reg)
 {
 	return 0;
 }
 
-static int ln9310_emul_finish_write(struct i2c_emul *emul, int reg, int bytes)
+static int ln9310_emul_finish_write(const struct emul *emul, int reg, int bytes)
 {
 	return 0;
 }
 
-static int ln9310_emul_write_byte(struct i2c_emul *emul, int reg, uint8_t val,
+static int ln9310_emul_write_byte(const struct emul *emul, int reg, uint8_t val,
 				  int bytes)
 {
-	struct ln9310_emul_data *data = LN9310_DATA_FROM_I2C_EMUL(emul);
+	struct ln9310_emul_data *data = emul->data;
 
 	__ASSERT(bytes == 1, "bytes 0x%x != 0x1 on reg 0x%x", bytes, reg);
 
@@ -352,14 +349,14 @@ static int ln9310_emul_write_byte(struct i2c_emul *emul, int reg, uint8_t val,
 	return 0;
 }
 
-static int ln9310_emul_start_read(struct i2c_emul *emul, int reg)
+static int ln9310_emul_start_read(const struct emul *emul, int reg)
 {
 	return 0;
 }
 
-static int ln9310_emul_finish_read(struct i2c_emul *emul, int reg, int bytes)
+static int ln9310_emul_finish_read(const struct emul *emul, int reg, int bytes)
 {
-	struct ln9310_emul_data *data = LN9310_DATA_FROM_I2C_EMUL(emul);
+	struct ln9310_emul_data *data = emul->data;
 
 	switch (reg) {
 	case LN9310_REG_INT1:
@@ -370,10 +367,10 @@ static int ln9310_emul_finish_read(struct i2c_emul *emul, int reg, int bytes)
 	return 0;
 }
 
-static int ln9310_emul_read_byte(struct i2c_emul *emul, int reg, uint8_t *val,
+static int ln9310_emul_read_byte(const struct emul *emul, int reg, uint8_t *val,
 				 int bytes)
 {
-	struct ln9310_emul_data *data = LN9310_DATA_FROM_I2C_EMUL(emul);
+	struct ln9310_emul_data *data = emul->data;
 
 	__ASSERT(bytes == 0, "bytes 0x%x != 0x0 on reg 0x%x", bytes, reg);
 
@@ -459,7 +456,7 @@ static int ln9310_emul_read_byte(struct i2c_emul *emul, int reg, uint8_t *val,
 	return 0;
 }
 
-static int ln9310_emul_access_reg(struct i2c_emul *emul, int reg, int bytes,
+static int ln9310_emul_access_reg(const struct emul *emul, int reg, int bytes,
 				  bool read)
 {
 	return reg;
@@ -468,19 +465,14 @@ static int ln9310_emul_access_reg(struct i2c_emul *emul, int reg, int bytes,
 static int emul_ln9310_init(const struct emul *emul,
 			    const struct device *parent)
 {
-	const struct i2c_common_emul_cfg *cfg = emul->cfg;
 	struct ln9310_emul_data *data = emul->data;
 
-	data->common.emul.api = &i2c_common_emul_api;
-	data->common.emul.addr = cfg->addr;
-	data->common.emul.parent = emul;
 	data->common.i2c = parent;
-	data->common.cfg = cfg;
 	i2c_common_emul_init(&data->common);
 
 	singleton = emul;
 
-	return i2c_emul_register(parent, emul->dev_label, &data->common.emul);
+	return 0;
 }
 
 #define LN9310_GET_GPIO_INT_PORT(n) \
@@ -489,11 +481,11 @@ static int emul_ln9310_init(const struct emul *emul,
 #define LN9310_GET_GPIO_INT_PIN(n) \
 	DT_GPIO_PIN(DT_INST_PROP(n, pg_int_pin), gpios)
 
-#define INIT_LN9310(n)                                                         \
-	const struct ln9310_config_t ln9310_config = {                         \
-		.i2c_port = NAMED_I2C(power),                                  \
-		.i2c_addr_flags = DT_INST_REG_ADDR(n),                         \
-	};                                                                     \
+#define INIT_LN9310(n)                                                           \
+	const struct ln9310_config_t ln9310_config = {                           \
+		.i2c_port = I2C_PORT_NODELABEL(i2c0),                            \
+		.i2c_addr_flags = DT_INST_REG_ADDR(n),                           \
+	};                                                                       \
 	static struct ln9310_emul_data ln9310_emul_data_##n = {                \
 		.common = {                                                    \
 			.start_write = ln9310_emul_start_write,                \
@@ -506,13 +498,19 @@ static int emul_ln9310_init(const struct emul *emul,
 		},                                                             \
 		.gpio_int_port = LN9310_GET_GPIO_INT_PORT(n),		       \
 		.gpio_int_pin = LN9310_GET_GPIO_INT_PIN(n),		       \
-	};                                                                     \
-	static const struct i2c_common_emul_cfg ln9310_emul_cfg_##n = {        \
-		.i2c_label = DT_INST_BUS_LABEL(n),                             \
-		.dev_label = DT_INST_LABEL(n),                                 \
-		.addr = DT_INST_REG_ADDR(n),                                   \
-	};                                                                     \
-	EMUL_DEFINE(emul_ln9310_init, DT_DRV_INST(n), &ln9310_emul_cfg_##n,    \
-		    &ln9310_emul_data_##n)
+	}; \
+	static const struct i2c_common_emul_cfg ln9310_emul_cfg_##n = {          \
+		.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)),                  \
+		.addr = DT_INST_REG_ADDR(n),                                     \
+	};                                                                       \
+	EMUL_DT_INST_DEFINE(n, emul_ln9310_init, &ln9310_emul_data_##n,          \
+			    &ln9310_emul_cfg_##n, &i2c_common_emul_api)
 
 DT_INST_FOREACH_STATUS_OKAY(INIT_LN9310)
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
+
+struct i2c_common_emul_data *
+emul_ln9310_get_i2c_common_data(const struct emul *emul)
+{
+	return emul->data;
+}
diff --git a/zephyr/emul/emul_pi3usb9201.c b/zephyr/emul/emul_pi3usb9201.c
index 9115a84515..3b1193d9b1 100644
--- a/zephyr/emul/emul_pi3usb9201.c
+++ b/zephyr/emul/emul_pi3usb9201.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,6 +11,8 @@
 #include <zephyr/drivers/i2c_emul.h>
 
 #include "emul/emul_pi3usb9201.h"
+#include "emul/emul_stub_device.h"
+#include "emul/emul_common_i2c.h"
 
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(emul_pi3usb9201, LOG_LEVEL_DBG);
@@ -20,6 +22,8 @@ LOG_MODULE_REGISTER(emul_pi3usb9201, LOG_LEVEL_DBG);
 
 /** Run-time data used by the emulator */
 struct pi3usb9201_emul_data {
+	/** Common I2C data */
+	struct i2c_common_emul_data common;
 	/** I2C emulator detail */
 	struct i2c_emul emul;
 	/** pi3usb9201 device being emulated */
@@ -32,50 +36,48 @@ struct pi3usb9201_emul_data {
 
 /** Static configuration for the emulator */
 struct pi3usb9201_emul_cfg {
-	/** Label of the I2C bus this emulator connects to */
-	const char *i2c_label;
 	/** Pointer to run-time data */
 	struct pi3usb9201_emul_data *data;
 	/** Address of pi3usb9201 on i2c bus */
 	uint16_t addr;
 };
 
-int pi3usb9201_emul_set_reg(struct i2c_emul *emul, int reg, uint8_t val)
+int pi3usb9201_emul_set_reg(const struct emul *emul, int reg, uint8_t val)
 {
 	struct pi3usb9201_emul_data *data;
 
 	if (!EMUL_REG_IS_VALID(reg))
 		return -EIO;
 
-	data = CONTAINER_OF(emul, struct pi3usb9201_emul_data, emul);
+	data = emul->data;
 	data->reg[reg] = val;
 
 	return 0;
 }
 
-int pi3usb9201_emul_get_reg(struct i2c_emul *emul, int reg, uint8_t *val)
+int pi3usb9201_emul_get_reg(const struct emul *emul, int reg, uint8_t *val)
 {
 	struct pi3usb9201_emul_data *data;
 
 	if (!EMUL_REG_IS_VALID(reg))
 		return -EIO;
 
-	data = CONTAINER_OF(emul, struct pi3usb9201_emul_data, emul);
+	data = emul->data;
 	*val = data->reg[reg];
 
 	return 0;
 }
 
-static void pi3usb9201_emul_reset(struct i2c_emul *emul)
+static void pi3usb9201_emul_reset(const struct emul *emul)
 {
 	struct pi3usb9201_emul_data *data;
 
-	data = CONTAINER_OF(emul, struct pi3usb9201_emul_data, emul);
+	data = emul->data;
 
-	data->reg[PI3USB9201_REG_CTRL_1]     = 0;
-	data->reg[PI3USB9201_REG_CTRL_2]     = 0;
+	data->reg[PI3USB9201_REG_CTRL_1] = 0;
+	data->reg[PI3USB9201_REG_CTRL_2] = 0;
 	data->reg[PI3USB9201_REG_CLIENT_STS] = 0;
-	data->reg[PI3USB9201_REG_HOST_STS]   = 0;
+	data->reg[PI3USB9201_REG_HOST_STS] = 0;
 }
 
 /**
@@ -91,13 +93,14 @@ static void pi3usb9201_emul_reset(struct i2c_emul *emul)
  * @retval 0 If successful
  * @retval -EIO General input / output error
  */
-static int pi3usb9201_emul_transfer(struct i2c_emul *emul, struct i2c_msg *msgs,
-				    int num_msgs, int addr)
+static int pi3usb9201_emul_transfer(const struct emul *emul,
+				    struct i2c_msg *msgs, int num_msgs,
+				    int addr)
 {
 	const struct pi3usb9201_emul_cfg *cfg;
 	struct pi3usb9201_emul_data *data;
 
-	data = CONTAINER_OF(emul, struct pi3usb9201_emul_data, emul);
+	data = emul->data;
 	cfg = data->cfg;
 
 	if (cfg->addr != addr) {
@@ -109,18 +112,18 @@ static int pi3usb9201_emul_transfer(struct i2c_emul *emul, struct i2c_msg *msgs,
 	i2c_dump_msgs("emul", msgs, num_msgs, addr);
 
 	if (num_msgs == 1) {
-		if (!(((msgs[0].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE)
-		      && (msgs[0].len == 2))) {
+		if (!(((msgs[0].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) &&
+		      (msgs[0].len == 2))) {
 			LOG_ERR("Unexpected write msgs");
 			return -EIO;
 		}
 		return pi3usb9201_emul_set_reg(emul, msgs[0].buf[0],
 					       msgs[0].buf[1]);
 	} else if (num_msgs == 2) {
-		if (!(((msgs[0].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE)
-		      && (msgs[0].len == 1)
-		      && ((msgs[1].flags & I2C_MSG_RW_MASK) == I2C_MSG_READ)
-		      && (msgs[1].len == 1))) {
+		if (!(((msgs[0].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) &&
+		      (msgs[0].len == 1) &&
+		      ((msgs[1].flags & I2C_MSG_RW_MASK) == I2C_MSG_READ) &&
+		      (msgs[1].len == 1))) {
 			LOG_ERR("Unexpected read msgs");
 			return -EIO;
 		}
@@ -130,7 +133,6 @@ static int pi3usb9201_emul_transfer(struct i2c_emul *emul, struct i2c_msg *msgs,
 		LOG_ERR("Unexpected num_msgs");
 		return -EIO;
 	}
-
 }
 
 /* Device instantiation */
@@ -151,45 +153,29 @@ static struct i2c_emul_api pi3usb9201_emul_api = {
  * @return 0 indicating success (always)
  */
 static int pi3usb9201_emul_init(const struct emul *emul,
-			 const struct device *parent)
+				const struct device *parent)
 {
 	const struct pi3usb9201_emul_cfg *cfg = emul->cfg;
 	struct pi3usb9201_emul_data *data = cfg->data;
-	int ret;
 
-	data->emul.api = &pi3usb9201_emul_api;
-	data->emul.addr = cfg->addr;
 	data->i2c = parent;
 	data->cfg = cfg;
 
-	ret = i2c_emul_register(parent, emul->dev_label, &data->emul);
-
-	pi3usb9201_emul_reset(&data->emul);
+	pi3usb9201_emul_reset(emul);
 
-	return ret;
+	return 0;
 }
 
 #define PI3USB9201_EMUL(n)                                                  \
 	static struct pi3usb9201_emul_data pi3usb9201_emul_data_##n = {};   \
 	static const struct pi3usb9201_emul_cfg pi3usb9201_emul_cfg_##n = { \
-		.i2c_label = DT_INST_BUS_LABEL(n),                          \
 		.data = &pi3usb9201_emul_data_##n,                          \
 		.addr = DT_INST_REG_ADDR(n),                                \
 	};                                                                  \
-	EMUL_DEFINE(pi3usb9201_emul_init, DT_DRV_INST(n),                   \
-		    &pi3usb9201_emul_cfg_##n, &pi3usb9201_emul_data_##n)
+	EMUL_DT_INST_DEFINE(n, pi3usb9201_emul_init,                        \
+			    &pi3usb9201_emul_data_##n,                      \
+			    &pi3usb9201_emul_cfg_##n, &pi3usb9201_emul_api)
 
 DT_INST_FOREACH_STATUS_OKAY(PI3USB9201_EMUL)
 
-#define PI3USB9201_EMUL_CASE(n)					\
-	case DT_INST_DEP_ORD(n): return &pi3usb9201_emul_data_##n.emul;
-
-struct i2c_emul *pi3usb9201_emul_get(int ord)
-{
-	switch (ord) {
-	DT_INST_FOREACH_STATUS_OKAY(PI3USB9201_EMUL_CASE)
-
-	default:
-		return NULL;
-	}
-}
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
diff --git a/zephyr/emul/emul_rt9490.c b/zephyr/emul/emul_rt9490.c
new file mode 100644
index 0000000000..dbc2500e90
--- /dev/null
+++ b/zephyr/emul/emul_rt9490.c
@@ -0,0 +1,107 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/device.h>
+
+#include "driver/charger/rt9490.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_rt9490.h"
+#include "emul/emul_stub_device.h"
+#include "util.h"
+
+#define DT_DRV_COMPAT zephyr_rt9490_emul
+
+#define RT9490_REG_MAX 255
+
+struct rt9490_data {
+	struct i2c_common_emul_data common;
+	uint8_t regs[RT9490_REG_MAX + 1];
+};
+
+static const uint8_t default_values[RT9490_REG_MAX + 1] = {
+	[RT9490_REG_SAFETY_TMR_CTRL] = 0x3D,
+	[RT9490_REG_ADD_CTRL0] = 0x76,
+};
+
+void rt9490_emul_reset_regs(const struct emul *emul)
+{
+	struct rt9490_data *data = emul->data;
+
+	memcpy(data->regs, default_values, RT9490_REG_MAX + 1);
+}
+
+int rt9490_emul_peek_reg(const struct emul *emul, int reg)
+{
+	struct rt9490_data *data = emul->data;
+	uint8_t *regs = data->regs;
+
+	if (!IN_RANGE(reg, 0, RT9490_REG_MAX)) {
+		return -1;
+	}
+	return regs[reg];
+}
+
+static int rt9490_emul_read(const struct emul *emul, int reg, uint8_t *val,
+			    int bytes, void *unused_data)
+{
+	struct rt9490_data *data = emul->data;
+	uint8_t *regs = data->regs;
+	int pos = reg + bytes;
+
+	if (!IN_RANGE(pos, 0, RT9490_REG_MAX)) {
+		return -1;
+	}
+	*val = regs[pos];
+
+	return 0;
+}
+
+static int rt9490_emul_write(const struct emul *emul, int reg, uint8_t val,
+			     int bytes, void *unused_data)
+{
+	struct rt9490_data *data = emul->data;
+	uint8_t *regs = data->regs;
+	int pos = reg + bytes - 1;
+
+	if (!IN_RANGE(pos, 0, RT9490_REG_MAX) || !IN_RANGE(val, 0, UINT8_MAX)) {
+		return -1;
+	}
+	regs[pos] = val;
+
+	return 0;
+}
+
+static int rt9490_emul_init(const struct emul *emul,
+			    const struct device *parent)
+{
+	struct rt9490_data *data = (struct rt9490_data *)emul->data;
+	struct i2c_common_emul_data *common_data = &data->common;
+
+	i2c_common_emul_init(common_data);
+	i2c_common_emul_set_read_func(common_data, rt9490_emul_read, NULL);
+	i2c_common_emul_set_write_func(common_data, rt9490_emul_write, NULL);
+
+	rt9490_emul_reset_regs(emul);
+
+	return 0;
+}
+
+#define INIT_RT9490_EMUL(n)                                        \
+	static struct i2c_common_emul_cfg common_cfg_##n;          \
+	static struct rt9490_data rt9490_data_##n;                 \
+	static struct i2c_common_emul_cfg common_cfg_##n = {       \
+		.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)),    \
+		.data = &rt9490_data_##n.common,                   \
+		.addr = DT_INST_REG_ADDR(n)                        \
+	};                                                         \
+	static struct rt9490_data rt9490_data_##n = {              \
+		.common = { .cfg = &common_cfg_##n }               \
+	};                                                         \
+	EMUL_DT_INST_DEFINE(n, rt9490_emul_init, &rt9490_data_##n, \
+			    &common_cfg_##n, &i2c_common_emul_api)
+
+DT_INST_FOREACH_STATUS_OKAY(INIT_RT9490_EMUL)
+
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
diff --git a/zephyr/emul/emul_rtc.c b/zephyr/emul/emul_rtc.c
new file mode 100644
index 0000000000..45741a5277
--- /dev/null
+++ b/zephyr/emul/emul_rtc.c
@@ -0,0 +1,139 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define DT_DRV_COMPAT cros_ec_rtc_emul
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(emul_rtc);
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/emul.h>
+#include <ec_commands.h>
+#include <drivers/cros_rtc.h>
+#include <zephyr/sys/__assert.h>
+
+#include "flash.h"
+
+struct cros_rtc_emul_data {
+	const struct device *rtc_dev;
+	uint32_t alarm_time;
+	cros_rtc_alarm_callback_t alarm_callback;
+	uint32_t value;
+};
+
+struct rtc_emul_cfg {
+	/** Pointer to run-time data */
+	struct cros_rtc_emul_data *data;
+};
+
+#define RTC_DEV DT_CHOSEN(zephyr_rtc_controller)
+
+#define DRV_DATA(dev) ((struct cros_rtc_emul_data *)(dev)->data)
+
+static int cros_rtc_emul_configure(const struct device *dev,
+				   cros_rtc_alarm_callback_t callback)
+{
+	struct cros_rtc_emul_data *data = DRV_DATA(dev);
+
+	if (callback == NULL) {
+		return -EINVAL;
+	}
+
+	data->alarm_callback = callback;
+
+	return EC_SUCCESS;
+}
+
+static int cros_rtc_emul_get_value(const struct device *dev, uint32_t *value)
+{
+	struct cros_rtc_emul_data *data = DRV_DATA(dev);
+
+	*value = data->value;
+
+	return EC_SUCCESS;
+}
+
+static int cros_rtc_emul_set_value(const struct device *dev, uint32_t value)
+{
+	struct cros_rtc_emul_data *data = DRV_DATA(dev);
+
+	data->value = value;
+
+	return EC_SUCCESS;
+}
+
+static int cros_rtc_emul_get_alarm(const struct device *dev, uint32_t *seconds,
+				   uint32_t *microseconds)
+{
+	struct cros_rtc_emul_data *data = DRV_DATA(dev);
+
+	*seconds = data->alarm_time;
+	*microseconds = 0;
+
+	return EC_SUCCESS;
+}
+
+static int cros_rtc_emul_reset_alarm(const struct device *dev)
+{
+	struct cros_rtc_emul_data *data = DRV_DATA(dev);
+
+	data->alarm_time = 0;
+
+	return EC_SUCCESS;
+}
+
+static int cros_rtc_emul_set_alarm(const struct device *dev, uint32_t seconds,
+				   uint32_t microseconds)
+{
+	struct cros_rtc_emul_data *data = DRV_DATA(dev);
+	int ret;
+
+	ARG_UNUSED(microseconds);
+
+	ret = cros_rtc_emul_reset_alarm(dev);
+
+	if (ret < 0) {
+		return ret;
+	}
+
+	data->alarm_time = seconds;
+
+	if (ret < 0) {
+		return ret;
+	}
+
+	return EC_SUCCESS;
+}
+
+static const struct cros_rtc_driver_api emul_cros_rtc_driver_api = {
+	.configure = cros_rtc_emul_configure,
+	.get_value = cros_rtc_emul_get_value,
+	.set_value = cros_rtc_emul_set_value,
+	.get_alarm = cros_rtc_emul_get_alarm,
+	.set_alarm = cros_rtc_emul_set_alarm,
+	.reset_alarm = cros_rtc_emul_reset_alarm,
+};
+
+static int rtc_emul_init(const struct device *dev)
+{
+	struct cros_rtc_emul_data *data = DRV_DATA(dev);
+
+	data->alarm_callback = NULL;
+	data->alarm_time = 0;
+	data->value = 0;
+
+	return EC_SUCCESS;
+}
+
+#define RTC_EMUL(n)                                                            \
+	static struct cros_rtc_emul_data cros_rtc_emul_data_##n = {};          \
+	static const struct rtc_emul_cfg rtc_emul_cfg_##n = {                  \
+		.data = &cros_rtc_emul_data_##n,                               \
+	};                                                                     \
+	DEVICE_DT_INST_DEFINE(n, rtc_emul_init, NULL, &cros_rtc_emul_data_##n, \
+			      &rtc_emul_cfg_##n, PRE_KERNEL_1,                 \
+			      CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,             \
+			      &emul_cros_rtc_driver_api)
+DT_INST_FOREACH_STATUS_OKAY(RTC_EMUL);
diff --git a/zephyr/emul/emul_smart_battery.c b/zephyr/emul/emul_smart_battery.c
index a6abd94054..b3e8d62bcc 100644
--- a/zephyr/emul/emul_smart_battery.c
+++ b/zephyr/emul/emul_smart_battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,16 +13,14 @@ LOG_MODULE_REGISTER(smart_battery);
 #include <zephyr/drivers/emul.h>
 #include <zephyr/drivers/i2c.h>
 #include <zephyr/drivers/i2c_emul.h>
+#include <zephyr/ztest.h>
 
 #include "emul/emul_common_i2c.h"
 #include "emul/emul_smart_battery.h"
 
 #include "crc8.h"
 #include "battery_smart.h"
-
-#define SBAT_DATA_FROM_I2C_EMUL(_emul)					     \
-	CONTAINER_OF(CONTAINER_OF(_emul, struct i2c_common_emul_data, emul), \
-		     struct sbat_emul_data, common)
+#include "emul/emul_stub_device.h"
 
 /** Run-time data used by the emulator */
 struct sbat_emul_data {
@@ -40,11 +38,11 @@ struct sbat_emul_data {
 };
 
 /** Check description in emul_smart_battery.h */
-struct sbat_emul_bat_data *sbat_emul_get_bat_data(struct i2c_emul *emul)
+struct sbat_emul_bat_data *sbat_emul_get_bat_data(const struct emul *emul)
 {
 	struct sbat_emul_data *data;
 
-	data = SBAT_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	return &data->bat;
 }
@@ -53,13 +51,13 @@ struct sbat_emul_bat_data *sbat_emul_get_bat_data(struct i2c_emul *emul)
 uint16_t sbat_emul_date_to_word(unsigned int day, unsigned int month,
 				unsigned int year)
 {
-	year   -= MANUFACTURE_DATE_YEAR_OFFSET;
-	year  <<= MANUFACTURE_DATE_YEAR_SHIFT;
-	year   &= MANUFACTURE_DATE_YEAR_MASK;
+	year -= MANUFACTURE_DATE_YEAR_OFFSET;
+	year <<= MANUFACTURE_DATE_YEAR_SHIFT;
+	year &= MANUFACTURE_DATE_YEAR_MASK;
 	month <<= MANUFACTURE_DATE_MONTH_SHIFT;
-	month  &= MANUFACTURE_DATE_MONTH_MASK;
-	day   <<= MANUFACTURE_DATE_DAY_SHIFT;
-	day    &= MANUFACTURE_DATE_DAY_MASK;
+	month &= MANUFACTURE_DATE_MONTH_MASK;
+	day <<= MANUFACTURE_DATE_DAY_SHIFT;
+	day &= MANUFACTURE_DATE_DAY_MASK;
 
 	return day | month | year;
 }
@@ -105,7 +103,7 @@ static uint16_t sbat_emul_10mw_to_ma(int mw, int mv)
 	/* Smart battery use 10mW units, convert to mW */
 	mw *= 10;
 	/* Multiple by 1000 to get mA instead of A */
-	return 1000 * mw/mv;
+	return 1000 * mw / mv;
 }
 
 /**
@@ -274,14 +272,12 @@ static int sbat_emul_read_at_rate_ok(struct sbat_emul_bat_data *bat,
  *
  * @return value which equals to computed status register
  */
-static uint16_t sbat_emul_read_status(struct i2c_emul *emul)
+static uint16_t sbat_emul_read_status(const struct emul *emul)
 {
 	uint16_t status, cap, rem_time, charge_percent;
 	struct sbat_emul_bat_data *bat;
-	struct sbat_emul_data *data;
 
-	data = SBAT_DATA_FROM_I2C_EMUL(emul);
-	bat = &data->bat;
+	bat = sbat_emul_get_bat_data(emul);
 
 	status = bat->status;
 
@@ -329,15 +325,13 @@ static uint16_t sbat_emul_read_status(struct i2c_emul *emul)
 }
 
 /** Check description in emul_smart_battery.h */
-int sbat_emul_get_word_val(struct i2c_emul *emul, int cmd, uint16_t *val)
+int sbat_emul_get_word_val(const struct emul *emul, int cmd, uint16_t *val)
 {
 	struct sbat_emul_bat_data *bat;
-	struct sbat_emul_data *data;
 	int mode_mw;
 	int rate;
 
-	data = SBAT_DATA_FROM_I2C_EMUL(emul);
-	bat = &data->bat;
+	bat = sbat_emul_get_bat_data(emul);
 	mode_mw = bat->mode & MODE_CAPACITY;
 
 	switch (cmd) {
@@ -466,13 +460,13 @@ int sbat_emul_get_word_val(struct i2c_emul *emul, int cmd, uint16_t *val)
 }
 
 /** Check description in emul_smart_battery.h */
-int sbat_emul_get_block_data(struct i2c_emul *emul, int cmd, uint8_t **blk,
+int sbat_emul_get_block_data(const struct emul *emul, int cmd, uint8_t **blk,
 			     int *len)
 {
 	struct sbat_emul_bat_data *bat;
 	struct sbat_emul_data *data;
 
-	data = SBAT_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 	bat = &data->bat;
 
 	switch (cmd) {
@@ -492,6 +486,10 @@ int sbat_emul_get_block_data(struct i2c_emul *emul, int cmd, uint8_t **blk,
 		*blk = bat->mf_data;
 		*len = bat->mf_data_len;
 		return 0;
+	case SB_MANUFACTURE_INFO:
+		*blk = bat->mf_info;
+		*len = bat->mf_info_len;
+		return 0;
 	default:
 		/* Unknown command or return value is not word */
 		return 1;
@@ -504,13 +502,15 @@ int sbat_emul_get_block_data(struct i2c_emul *emul, int cmd, uint8_t **blk,
  * @param data Pointer to smart battery emulator data
  * @param cmd Command for which PEC is calculated
  */
-static void sbat_emul_append_pec(struct sbat_emul_data *data, int cmd)
+static void sbat_emul_append_pec(const struct emul *emul, int cmd)
 {
 	uint8_t pec;
+	struct sbat_emul_data *data = emul->data;
+	const struct i2c_common_emul_cfg *cfg = emul->cfg;
 
 	if (BATTERY_SPEC_VERSION(data->bat.spec_info) ==
 	    BATTERY_SPEC_VER_1_1_WITH_PEC) {
-		pec = sbat_emul_pec_head(data->common.cfg->addr, 1, cmd);
+		pec = sbat_emul_pec_head(cfg->addr, 1, cmd);
 		pec = cros_crc8_arg(data->msg_buf, data->num_to_read, pec);
 		data->msg_buf[data->num_to_read] = pec;
 		data->num_to_read++;
@@ -518,12 +518,12 @@ static void sbat_emul_append_pec(struct sbat_emul_data *data, int cmd)
 }
 
 /** Check description in emul_smart_battery.h */
-void sbat_emul_set_response(struct i2c_emul *emul, int cmd, uint8_t *buf,
+void sbat_emul_set_response(const struct emul *emul, int cmd, uint8_t *buf,
 			    int len, bool fail)
 {
 	struct sbat_emul_data *data;
 
-	data = SBAT_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	if (fail) {
 		data->bat.error_code = STATUS_CODE_UNKNOWN_ERROR;
@@ -534,7 +534,7 @@ void sbat_emul_set_response(struct i2c_emul *emul, int cmd, uint8_t *buf,
 	data->num_to_read = MIN(len, MSG_BUF_LEN - 1);
 	memcpy(data->msg_buf, buf, data->num_to_read);
 	data->bat.error_code = STATUS_CODE_OK;
-	sbat_emul_append_pec(data, cmd);
+	sbat_emul_append_pec(emul, cmd);
 }
 
 /**
@@ -552,14 +552,14 @@ void sbat_emul_set_response(struct i2c_emul *emul, int cmd, uint8_t *buf,
  * @return 0 on success
  * @return -EIO on error
  */
-static int sbat_emul_handle_read_msg(struct i2c_emul *emul, int reg)
+static int sbat_emul_handle_read_msg(const struct emul *emul, int reg)
 {
 	struct sbat_emul_data *data;
 	uint16_t word;
 	uint8_t *blk;
 	int ret, len;
 
-	data = SBAT_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	if (data->cur_cmd == SBAT_EMUL_NO_CMD) {
 		/* Unexpected read message without preceding command select */
@@ -579,7 +579,7 @@ static int sbat_emul_handle_read_msg(struct i2c_emul *emul, int reg)
 		data->msg_buf[0] = word & 0xff;
 		data->msg_buf[1] = (word >> 8) & 0xff;
 		data->bat.error_code = STATUS_CODE_OK;
-		sbat_emul_append_pec(data, reg);
+		sbat_emul_append_pec(emul, reg);
 
 		return 0;
 	}
@@ -594,7 +594,7 @@ static int sbat_emul_handle_read_msg(struct i2c_emul *emul, int reg)
 		data->msg_buf[0] = len;
 		memcpy(&data->msg_buf[1], blk, len);
 		data->bat.error_code = STATUS_CODE_OK;
-		sbat_emul_append_pec(data, reg);
+		sbat_emul_append_pec(emul, reg);
 
 		return 0;
 	}
@@ -615,7 +615,7 @@ static int sbat_emul_handle_read_msg(struct i2c_emul *emul, int reg)
  * @return 0 on success
  * @return -EIO on error
  */
-static int sbat_emul_finalize_write_msg(struct i2c_emul *emul, int reg,
+static int sbat_emul_finalize_write_msg(const struct emul *emul, int reg,
 					int bytes)
 {
 	struct sbat_emul_bat_data *bat;
@@ -623,7 +623,7 @@ static int sbat_emul_finalize_write_msg(struct i2c_emul *emul, int reg,
 	uint16_t word;
 	uint8_t pec;
 
-	data = SBAT_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 	bat = &data->bat;
 
 	/*
@@ -659,8 +659,8 @@ static int sbat_emul_finalize_write_msg(struct i2c_emul *emul, int reg,
 		pec = cros_crc8_arg(data->msg_buf, 3, pec);
 		if (pec != data->msg_buf[3]) {
 			data->bat.error_code = STATUS_CODE_UNKNOWN_ERROR;
-			LOG_ERR("Wrong PEC 0x%x != 0x%x",
-				pec, data->msg_buf[3]);
+			LOG_ERR("Wrong PEC 0x%x != 0x%x", pec,
+				data->msg_buf[3]);
 
 			return -EIO;
 		}
@@ -709,12 +709,12 @@ static int sbat_emul_finalize_write_msg(struct i2c_emul *emul, int reg,
  *
  * @return 0 on success
  */
-static int sbat_emul_write_byte(struct i2c_emul *emul, int reg, uint8_t val,
+static int sbat_emul_write_byte(const struct emul *emul, int reg, uint8_t val,
 				int bytes)
 {
 	struct sbat_emul_data *data;
 
-	data = SBAT_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	if (bytes < MSG_BUF_LEN) {
 		data->msg_buf[bytes] = val;
@@ -734,12 +734,12 @@ static int sbat_emul_write_byte(struct i2c_emul *emul, int reg, uint8_t val,
  *
  * @return 0 on success
  */
-static int sbat_emul_read_byte(struct i2c_emul *emul, int reg, uint8_t *val,
+static int sbat_emul_read_byte(const struct emul *emul, int reg, uint8_t *val,
 			       int bytes)
 {
 	struct sbat_emul_data *data;
 
-	data = SBAT_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	if (data->num_to_read == 0) {
 		data->bat.error_code = STATUS_CODE_UNSUPPORTED;
@@ -766,7 +766,7 @@ static int sbat_emul_read_byte(struct i2c_emul *emul, int reg, uint8_t *val,
  *
  * @return Currently accessed register
  */
-static int sbat_emul_access_reg(struct i2c_emul *emul, int reg, int bytes,
+static int sbat_emul_access_reg(const struct emul *emul, int reg, int bytes,
 				bool read)
 {
 	return reg;
@@ -785,25 +785,18 @@ static int sbat_emul_access_reg(struct i2c_emul *emul, int reg, int bytes,
  *
  * @return 0 indicating success (always)
  */
-static int sbat_emul_init(const struct emul *emul,
-			  const struct device *parent)
+static int sbat_emul_init(const struct emul *emul, const struct device *parent)
 {
-	const struct i2c_common_emul_cfg *cfg = emul->cfg;
-	struct i2c_common_emul_data *data = cfg->data;
-	int ret;
+	struct sbat_emul_data *data = emul->data;
 
-	data->emul.api = &i2c_common_emul_api;
-	data->emul.addr = cfg->addr;
-	data->i2c = parent;
-	data->cfg = cfg;
-	i2c_common_emul_init(data);
+	data->common.i2c = parent;
 
-	ret = i2c_emul_register(parent, emul->dev_label, &data->emul);
+	i2c_common_emul_init(&data->common);
 
-	return ret;
+	return 0;
 }
 
-#define SMART_BATTERY_EMUL(n)						\
+#define SMART_BATTERY_EMUL(n)                                         \
 	static struct sbat_emul_data sbat_emul_data_##n = {		\
 		.bat = {						\
 			.mf_access = DT_INST_PROP(n, mf_access),	\
@@ -826,6 +819,7 @@ static int sbat_emul_init(const struct emul *emul,
 				(DT_INST_PROP(n, primary_battery) *	\
 				 MODE_PRIMARY_BATTERY_SUPPORT),		\
 			.design_mv = DT_INST_PROP(n, design_mv),	\
+			.default_design_mv = DT_INST_PROP(n, design_mv),\
 			.design_cap = DT_INST_PROP(n, design_cap),	\
 			.temp = DT_INST_PROP(n, temperature),		\
 			.volt = DT_INST_PROP(n, volt),			\
@@ -833,7 +827,9 @@ static int sbat_emul_init(const struct emul *emul,
 			.avg_cur = DT_INST_PROP(n, avg_cur),		\
 			.max_error = DT_INST_PROP(n, max_error),	\
 			.cap = DT_INST_PROP(n, cap),			\
+			.default_cap = DT_INST_PROP(n, cap),		\
 			.full_cap = DT_INST_PROP(n, full_cap),		\
+			.default_full_cap = DT_INST_PROP(n, full_cap),	\
 			.desired_charg_cur = DT_INST_PROP(n,		\
 						desired_charg_cur),	\
 			.desired_charg_volt = DT_INST_PROP(n,		\
@@ -852,6 +848,9 @@ static int sbat_emul_init(const struct emul *emul,
 			.dev_chem = DT_INST_PROP(n, dev_chem),		\
 			.dev_chem_len = sizeof(				\
 					DT_INST_PROP(n, dev_chem)) - 1,	\
+			.mf_info = DT_INST_PROP(n, mf_info),		\
+			.mf_info_len = sizeof(				\
+					DT_INST_PROP(n, mf_info)) - 1,	\
 			.mf_date = 0,					\
 			.cap_alarm = 0,					\
 			.time_alarm = 0,				\
@@ -869,29 +868,47 @@ static int sbat_emul_init(const struct emul *emul,
 			.finish_read = NULL,				\
 			.access_reg = sbat_emul_access_reg,		\
 		},							\
-	};								\
-									\
-	static const struct i2c_common_emul_cfg sbat_emul_cfg_##n = {	\
-		.i2c_label = DT_INST_BUS_LABEL(n),			\
-		.dev_label = DT_INST_LABEL(n),                          \
-		.data = &sbat_emul_data_##n.common,			\
-		.addr = DT_INST_REG_ADDR(n),				\
-	};								\
-	EMUL_DEFINE(sbat_emul_init, DT_DRV_INST(n), &sbat_emul_cfg_##n,	\
-		    &sbat_emul_data_##n)
+	};        \
+                                                                      \
+	static const struct i2c_common_emul_cfg sbat_emul_cfg_##n = { \
+		.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)),       \
+		.data = &sbat_emul_data_##n.common,                   \
+		.addr = DT_INST_REG_ADDR(n),                          \
+	};                                                            \
+	EMUL_DT_INST_DEFINE(n, sbat_emul_init, &sbat_emul_data_##n,   \
+			    &sbat_emul_cfg_##n, &i2c_common_emul_api)
 
 DT_INST_FOREACH_STATUS_OKAY(SMART_BATTERY_EMUL)
 
-#define SMART_BATTERY_EMUL_CASE(n)					\
-	case DT_INST_DEP_ORD(n): return &sbat_emul_data_##n.common.emul;
+#define SMART_BATTERY_EMUL_CASE(n) \
+	case DT_INST_DEP_ORD(n):   \
+		return sbat_emul_data_##n.common.emul.target;
 
-/** Check description in emul_smart_battery.h */
-struct i2c_emul *sbat_emul_get_ptr(int ord)
+static void emul_smart_battery_reset_capacity(const struct emul *emul)
 {
-	switch (ord) {
-	DT_INST_FOREACH_STATUS_OKAY(SMART_BATTERY_EMUL_CASE)
+	struct sbat_emul_data *bat_data = emul->data;
+	bat_data->bat.cap = bat_data->bat.default_cap;
+	bat_data->bat.full_cap = bat_data->bat.default_full_cap;
+	bat_data->bat.design_mv = bat_data->bat.default_design_mv;
+}
 
-	default:
-		return NULL;
-	}
+#define SBAT_EMUL_RESET_RULE_AFTER(n) \
+	emul_smart_battery_reset_capacity(EMUL_DT_GET(DT_DRV_INST(n)))
+
+static void emul_sbat_reset(const struct ztest_unit_test *test, void *data)
+{
+	ARG_UNUSED(test);
+	ARG_UNUSED(data);
+
+	DT_INST_FOREACH_STATUS_OKAY(SBAT_EMUL_RESET_RULE_AFTER);
+}
+
+ZTEST_RULE(emul_smart_battery_reset, NULL, emul_sbat_reset);
+
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
+
+struct i2c_common_emul_data *
+emul_smart_battery_get_i2c_common_data(const struct emul *emul)
+{
+	return emul->data;
 }
diff --git a/zephyr/emul/emul_sn5s330.c b/zephyr/emul/emul_sn5s330.c
index 8f8c3cd852..f957cd9e05 100644
--- a/zephyr/emul/emul_sn5s330.c
+++ b/zephyr/emul/emul_sn5s330.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,14 +19,11 @@
 #include "emul/emul_common_i2c.h"
 #include "emul/emul_sn5s330.h"
 #include "i2c.h"
+#include "emul/emul_stub_device.h"
 
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(sn5s330_emul, CONFIG_SN5S330_EMUL_LOG_LEVEL);
 
-#define SN5S330_DATA_FROM_I2C_EMUL(_emul)                                    \
-	CONTAINER_OF(CONTAINER_OF(_emul, struct i2c_common_emul_data, emul), \
-		     struct sn5s330_emul_data, common)
-
 struct sn5s330_emul_data {
 	/** Common I2C data */
 	struct i2c_common_emul_data common;
@@ -110,13 +107,6 @@ test_mockable_static void sn5s330_emul_interrupt_set_stub(void)
 	/* Stub to be used by fff fakes during test */
 }
 
-struct i2c_emul *sn5s330_emul_to_i2c_emul(const struct emul *emul)
-{
-	struct sn5s330_emul_data *data = emul->data;
-
-	return &(data->common.emul);
-}
-
 /* Workhorse for mapping i2c reg to internal emulator data access */
 static uint8_t *sn5s330_emul_get_reg_ptr(struct sn5s330_emul_data *data,
 					 int reg)
@@ -194,29 +184,29 @@ void sn5s330_emul_peek_reg(const struct emul *emul, uint32_t reg, uint8_t *val)
 	*val = *data_reg;
 }
 
-static void sn5s330_emul_set_int_pin(struct i2c_emul *emul, bool val)
+static void sn5s330_emul_set_int_pin(const struct emul *emul, bool val)
 {
-	struct sn5s330_emul_data *data = SN5S330_DATA_FROM_I2C_EMUL(emul);
+	struct sn5s330_emul_data *data = emul->data;
 	int res = gpio_emul_input_set(data->gpio_int_port, data->gpio_int_pin,
 				      val);
 	__ASSERT_NO_MSG(res == 0);
 }
 
-static void sn5s330_emul_assert_interrupt(struct i2c_emul *emul)
+static void sn5s330_emul_assert_interrupt(const struct emul *emul)
 {
 	sn5s330_emul_interrupt_set_stub();
 	sn5s330_emul_set_int_pin(emul, false);
 }
 
-static void sn5s330_emul_deassert_interrupt(struct i2c_emul *emul)
+static void sn5s330_emul_deassert_interrupt(const struct emul *emul)
 {
 	sn5s330_emul_set_int_pin(emul, true);
 }
 
-static int sn5s330_emul_read_byte(struct i2c_emul *emul, int reg, uint8_t *val,
-				  int bytes)
+static int sn5s330_emul_read_byte(const struct emul *emul, int reg,
+				  uint8_t *val, int bytes)
 {
-	struct sn5s330_emul_data *data = SN5S330_DATA_FROM_I2C_EMUL(emul);
+	struct sn5s330_emul_data *data = emul->data;
 	uint8_t *reg_to_read = sn5s330_emul_get_reg_ptr(data, reg);
 
 	__ASSERT(bytes == 0, "bytes 0x%x != 0x0 on reg 0x%x", bytes, reg);
@@ -225,10 +215,10 @@ static int sn5s330_emul_read_byte(struct i2c_emul *emul, int reg, uint8_t *val,
 	return 0;
 }
 
-static int sn5s330_emul_write_byte(struct i2c_emul *emul, int reg, uint8_t val,
-				   int bytes)
+static int sn5s330_emul_write_byte(const struct emul *emul, int reg,
+				   uint8_t val, int bytes)
 {
-	struct sn5s330_emul_data *data = SN5S330_DATA_FROM_I2C_EMUL(emul);
+	struct sn5s330_emul_data *data = emul->data;
 	uint8_t *reg_to_write;
 	bool deassert_int = false;
 
@@ -278,7 +268,6 @@ static int sn5s330_emul_write_byte(struct i2c_emul *emul, int reg, uint8_t val,
 void sn5s330_emul_make_vbus_overcurrent(const struct emul *emul)
 {
 	struct sn5s330_emul_data *data = emul->data;
-	struct i2c_emul *i2c_emul = &data->common.emul;
 
 	data->int_status_reg1 |= SN5S330_ILIM_PP1_MASK;
 	data->int_trip_rise_reg1 |= SN5S330_ILIM_PP1_MASK;
@@ -287,13 +276,12 @@ void sn5s330_emul_make_vbus_overcurrent(const struct emul *emul)
 	if (data->int_mask_rise_reg1 & SN5S330_ILIM_PP1_MASK)
 		return;
 
-	sn5s330_emul_assert_interrupt(i2c_emul);
+	sn5s330_emul_assert_interrupt(emul);
 }
 
 void sn5s330_emul_lower_vbus_below_minv(const struct emul *emul)
 {
 	struct sn5s330_emul_data *data = emul->data;
-	struct i2c_emul *i2c_emul = &data->common.emul;
 
 	data->int_status_reg4 |= SN5S330_VSAFE0V_STAT;
 
@@ -301,7 +289,7 @@ void sn5s330_emul_lower_vbus_below_minv(const struct emul *emul)
 	if (data->int_status_reg4 & SN5S330_VSAFE0V_MASK)
 		return;
 
-	sn5s330_emul_assert_interrupt(i2c_emul);
+	sn5s330_emul_assert_interrupt(emul);
 }
 
 void sn5s330_emul_reset(const struct emul *emul)
@@ -311,7 +299,7 @@ void sn5s330_emul_reset(const struct emul *emul)
 	const struct device *gpio_int_port = data->gpio_int_port;
 	gpio_pin_t gpio_int_pin = data->gpio_int_pin;
 
-	sn5s330_emul_deassert_interrupt(&data->common.emul);
+	sn5s330_emul_deassert_interrupt(emul);
 
 	/*
 	 * TODO(b/203364783): Some registers reset with set bits; this should be
@@ -328,44 +316,44 @@ void sn5s330_emul_reset(const struct emul *emul)
 static int emul_sn5s330_init(const struct emul *emul,
 			     const struct device *parent)
 {
-	const struct sn5s330_emul_cfg *cfg = emul->cfg;
 	struct sn5s330_emul_data *data = emul->data;
 
-	sn5s330_emul_deassert_interrupt(&data->common.emul);
+	sn5s330_emul_deassert_interrupt(emul);
 
-	data->common.emul.api = &i2c_common_emul_api;
-	data->common.emul.addr = cfg->common.addr;
-	data->common.emul.parent = emul;
 	data->common.i2c = parent;
-	data->common.cfg = &cfg->common;
 	i2c_common_emul_init(&data->common);
 
-	return i2c_emul_register(parent, emul->dev_label, &data->common.emul);
+	return 0;
 }
 
 #define SN5S330_GET_GPIO_INT_PORT(n) \
 	DEVICE_DT_GET(DT_GPIO_CTLR(DT_INST_PROP(n, int_pin), gpios))
 
-#define SN5S330_GET_GPIO_INT_PIN(n) \
-	DT_GPIO_PIN(DT_INST_PROP(n, int_pin), gpios)
+#define SN5S330_GET_GPIO_INT_PIN(n) DT_GPIO_PIN(DT_INST_PROP(n, int_pin), gpios)
 
-#define INIT_SN5S330(n)                                                        \
-	static struct sn5s330_emul_data sn5s330_emul_data_##n = {              \
+#define INIT_SN5S330(n)                                                          \
+	static struct sn5s330_emul_data sn5s330_emul_data_##n = { \
 		.common = {                                                    \
 			.write_byte = sn5s330_emul_write_byte,                 \
 			.read_byte = sn5s330_emul_read_byte,                   \
 		},                                                             \
 		.gpio_int_port = SN5S330_GET_GPIO_INT_PORT(n),		       \
 		.gpio_int_pin = SN5S330_GET_GPIO_INT_PIN(n),		       \
-	};                                                                     \
+	};              \
 	static struct sn5s330_emul_cfg sn5s330_emul_cfg_##n = {                \
 		.common = {                                                    \
-			.i2c_label = DT_INST_BUS_LABEL(n),                     \
-			.dev_label = DT_INST_LABEL(n),                         \
+			.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)),        \
 			.addr = DT_INST_REG_ADDR(n),                           \
 		},                                                             \
-	};                                                                     \
-	EMUL_DEFINE(emul_sn5s330_init, DT_DRV_INST(n), &sn5s330_emul_cfg_##n,  \
-		    &sn5s330_emul_data_##n)
+	}; \
+	EMUL_DT_INST_DEFINE(n, emul_sn5s330_init, &sn5s330_emul_data_##n,        \
+			    &sn5s330_emul_cfg_##n, &i2c_common_emul_api)
 
 DT_INST_FOREACH_STATUS_OKAY(INIT_SN5S330)
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
+
+struct i2c_common_emul_data *
+emul_sn5s330_get_i2c_common_data(const struct emul *emul)
+{
+	return emul->data;
+}
diff --git a/zephyr/emul/emul_syv682x.c b/zephyr/emul/emul_syv682x.c
index 9f5ad865bb..8fb4bfc928 100644
--- a/zephyr/emul/emul_syv682x.c
+++ b/zephyr/emul/emul_syv682x.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,10 +16,11 @@
 LOG_MODULE_REGISTER(syv682x);
 #include <stdint.h>
 #include <string.h>
-#include <ztest.h>
+#include <zephyr/ztest.h>
 
 #include "emul/emul_common_i2c.h"
 #include "emul/emul_syv682x.h"
+#include "emul/emul_stub_device.h"
 
 #define EMUL_REG_COUNT (SYV682X_CONTROL_4_REG + 1)
 #define EMUL_REG_IS_VALID(reg) (reg >= 0 && reg < EMUL_REG_COUNT)
@@ -53,29 +54,18 @@ struct syv682x_emul_cfg {
 	const struct i2c_common_emul_cfg common;
 };
 
-/* Gets the SYV682x data struct that contains an I2C emulator struct. */
-static struct syv682x_emul_data *
-i2c_emul_to_syv682x_emul_data(const struct i2c_emul *emul)
-{
-	struct i2c_common_emul_data *i2c_common_data =
-		CONTAINER_OF(emul, struct i2c_common_emul_data, emul);
-	struct syv682x_emul_data *syv682x_data =
-		CONTAINER_OF(i2c_common_data, struct syv682x_emul_data, common);
-	return syv682x_data;
-}
-
 /* Asserts or deasserts the interrupt signal to the EC. */
 static void syv682x_emul_set_alert(struct syv682x_emul_data *data, bool alert)
 {
 	int res = gpio_emul_input_set(data->alert_gpio_port,
-			/* The signal is inverted. */
-			data->alert_gpio_pin, !alert);
+				      /* The signal is inverted. */
+				      data->alert_gpio_pin, !alert);
 	__ASSERT_NO_MSG(res == 0);
 }
 
-int syv682x_emul_set_reg(struct i2c_emul *emul, int reg, uint8_t val)
+int syv682x_emul_set_reg(const struct emul *emul, int reg, uint8_t val)
 {
-	struct syv682x_emul_data *data = i2c_emul_to_syv682x_emul_data(emul);
+	struct syv682x_emul_data *data = emul->data;
 
 	if (!EMUL_REG_IS_VALID(reg))
 		return -EIO;
@@ -85,13 +75,13 @@ int syv682x_emul_set_reg(struct i2c_emul *emul, int reg, uint8_t val)
 	return 0;
 }
 
-void syv682x_emul_set_condition(struct i2c_emul *emul, uint8_t status,
-		uint8_t control_4)
+void syv682x_emul_set_condition(const struct emul *emul, uint8_t status,
+				uint8_t control_4)
 {
 	uint8_t control_4_interrupt = control_4 & SYV682X_CONTROL_4_INT_MASK;
-	struct syv682x_emul_data *data = i2c_emul_to_syv682x_emul_data(emul);
+	struct syv682x_emul_data *data = emul->data;
 	int frs_en_gpio = gpio_emul_output_get(data->frs_en_gpio_port,
-			data->frs_en_gpio_pin);
+					       data->frs_en_gpio_pin);
 
 	__ASSERT_NO_MSG(frs_en_gpio >= 0);
 
@@ -108,8 +98,8 @@ void syv682x_emul_set_condition(struct i2c_emul *emul, uint8_t status,
 	data->reg[SYV682X_CONTROL_4_REG] |= control_4_interrupt;
 
 	/* These conditions disable the power path. */
-	if (status & (SYV682X_STATUS_TSD | SYV682X_STATUS_OVP |
-				SYV682X_STATUS_OC_HV)) {
+	if (status &
+	    (SYV682X_STATUS_TSD | SYV682X_STATUS_OVP | SYV682X_STATUS_OC_HV)) {
 		data->reg[SYV682X_CONTROL_1_REG] |= SYV682X_CONTROL_1_PWR_ENB;
 	}
 
@@ -123,18 +113,17 @@ void syv682x_emul_set_condition(struct i2c_emul *emul, uint8_t status,
 
 	/* VBAT_OVP disconnects CC and VCONN. */
 	if (control_4_interrupt & SYV682X_CONTROL_4_VBAT_OVP) {
-		data->reg[SYV682X_CONTROL_4_REG] &= ~(SYV682X_CONTROL_4_CC1_BPS
-				| SYV682X_CONTROL_4_CC2_BPS
-				| SYV682X_CONTROL_4_VCONN1
-				| SYV682X_CONTROL_4_VCONN2);
+		data->reg[SYV682X_CONTROL_4_REG] &= ~(
+			SYV682X_CONTROL_4_CC1_BPS | SYV682X_CONTROL_4_CC2_BPS |
+			SYV682X_CONTROL_4_VCONN1 | SYV682X_CONTROL_4_VCONN2);
 	}
 
 	syv682x_emul_set_alert(data, status | control_4_interrupt);
 }
 
-void syv682x_emul_set_busy_reads(struct i2c_emul *emul, int reads)
+void syv682x_emul_set_busy_reads(const struct emul *emul, int reads)
 {
-	struct syv682x_emul_data *data = i2c_emul_to_syv682x_emul_data(emul);
+	struct syv682x_emul_data *data = emul->data;
 	data->busy_read_count = reads;
 	if (reads)
 		data->reg[SYV682X_CONTROL_3_REG] |= SYV682X_BUSY;
@@ -142,9 +131,9 @@ void syv682x_emul_set_busy_reads(struct i2c_emul *emul, int reads)
 		data->reg[SYV682X_CONTROL_3_REG] &= ~SYV682X_BUSY;
 }
 
-int syv682x_emul_get_reg(struct i2c_emul *emul, int reg, uint8_t *val)
+int syv682x_emul_get_reg(const struct emul *emul, int reg, uint8_t *val)
 {
-	struct syv682x_emul_data *data = i2c_emul_to_syv682x_emul_data(emul);
+	struct syv682x_emul_data *data = emul->data;
 
 	if (!EMUL_REG_IS_VALID(reg))
 		return -EIO;
@@ -154,10 +143,10 @@ int syv682x_emul_get_reg(struct i2c_emul *emul, int reg, uint8_t *val)
 	return 0;
 }
 
-static int syv682x_emul_write_byte(struct i2c_emul *emul, int reg, uint8_t val,
-				   int bytes)
+static int syv682x_emul_write_byte(const struct emul *emul, int reg,
+				   uint8_t val, int bytes)
 {
-	struct syv682x_emul_data *data = i2c_emul_to_syv682x_emul_data(emul);
+	struct syv682x_emul_data *data = emul->data;
 
 	zassert_equal(bytes, 1, "Write: bytes == %i at offset 0x%x", bytes,
 		      reg);
@@ -183,10 +172,10 @@ static int syv682x_emul_write_byte(struct i2c_emul *emul, int reg, uint8_t val,
 	return syv682x_emul_set_reg(emul, reg, val);
 }
 
-static int syv682x_emul_read_byte(struct i2c_emul *emul, int reg, uint8_t *val,
-				  int bytes)
+static int syv682x_emul_read_byte(const struct emul *emul, int reg,
+				  uint8_t *val, int bytes)
 {
-	struct syv682x_emul_data *data = i2c_emul_to_syv682x_emul_data(emul);
+	struct syv682x_emul_data *data = emul->data;
 	int ret = syv682x_emul_get_reg(emul, reg, val);
 
 	zassert_equal(bytes, 0, "Read: bytes == %i at offset 0x%x", bytes, reg);
@@ -220,8 +209,10 @@ static int syv682x_emul_read_byte(struct i2c_emul *emul, int reg, uint8_t *val,
 	return ret;
 }
 
-static void syv682x_emul_reset(struct syv682x_emul_data *data)
+static void syv682x_emul_reset(const struct emul *emul)
 {
+	struct syv682x_emul_data *data = emul->data;
+
 	memset(data->reg, 0, sizeof(data->reg));
 
 	syv682x_emul_set_alert(data, false);
@@ -244,26 +235,19 @@ static void syv682x_emul_reset(struct syv682x_emul_data *data)
  * @return 0 on success or an error code on failure
  */
 static int syv682x_emul_init(const struct emul *emul,
-			  const struct device *parent)
+			     const struct device *parent)
 {
-	const struct syv682x_emul_cfg *cfg = emul->cfg;
 	struct syv682x_emul_data *data = emul->data;
 
-	data->cfg = cfg;
-
-	data->common.emul.api = &i2c_common_emul_api;
-	data->common.emul.addr = cfg->common.addr;
-	data->common.emul.parent = emul;
 	data->common.i2c = parent;
-	data->common.cfg = &cfg->common;
 	i2c_common_emul_init(&data->common);
 
-	syv682x_emul_reset(data);
-	return i2c_emul_register(parent, emul->dev_label, &data->common.emul);
+	syv682x_emul_reset(emul);
+	return 0;
 }
 
 /* Device instantiation */
-#define SYV682X_EMUL(n)                                                        \
+#define SYV682X_EMUL(n)                                                          \
 	static struct syv682x_emul_data syv682x_emul_data_##n = {              \
 		.common = {                                                    \
 			.write_byte = syv682x_emul_write_byte,                 \
@@ -277,36 +261,23 @@ static int syv682x_emul_init(const struct emul *emul,
 					DT_INST_PROP(n, alert_gpio), gpios)),  \
 		.alert_gpio_pin = DT_GPIO_PIN(                                 \
 				DT_INST_PROP(n, alert_gpio), gpios),           \
-	};                                                                     \
+	}; \
 	static const struct syv682x_emul_cfg syv682x_emul_cfg_##n = {          \
 		.common = {                                                    \
-			.i2c_label = DT_INST_BUS_LABEL(n),                     \
-			.dev_label = DT_INST_LABEL(n),                         \
+			.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)),        \
 			.addr = DT_INST_REG_ADDR(n),                           \
 		},                                                             \
-	};                                                                     \
-	EMUL_DEFINE(syv682x_emul_init, DT_DRV_INST(n), &syv682x_emul_cfg_##n,  \
-		    &syv682x_emul_data_##n)
+	}; \
+	EMUL_DT_INST_DEFINE(n, syv682x_emul_init, &syv682x_emul_data_##n,        \
+			    &syv682x_emul_cfg_##n, &i2c_common_emul_api)
 
 DT_INST_FOREACH_STATUS_OKAY(SYV682X_EMUL)
 
-#define SYV682X_EMUL_CASE(n) \
-	case DT_INST_DEP_ORD(n): return &syv682x_emul_data_##n.common.emul;
-
-
-struct i2c_emul *syv682x_emul_get(int ord)
-{
-	switch (ord) {
-	DT_INST_FOREACH_STATUS_OKAY(SYV682X_EMUL_CASE)
-
-	default:
-		return NULL;
-	}
-}
-
 #ifdef CONFIG_ZTEST_NEW_API
+
 #define SYV682X_EMUL_RESET_RULE_BEFORE(n) \
-	syv682x_emul_reset(&syv682x_emul_data_##n);
+	syv682x_emul_reset(EMUL_DT_GET(DT_DRV_INST(n)));
+
 static void emul_syv682x_reset_before(const struct ztest_unit_test *test,
 				      void *data)
 {
@@ -316,3 +287,11 @@ static void emul_syv682x_reset_before(const struct ztest_unit_test *test,
 }
 ZTEST_RULE(emul_syv682x_reset, emul_syv682x_reset_before, NULL);
 #endif /* CONFIG_ZTEST_NEW_API */
+
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
+
+struct i2c_common_emul_data *
+emul_syv682x_get_i2c_common_data(const struct emul *emul)
+{
+	return emul->data;
+}
diff --git a/zephyr/emul/emul_tcs3400.c b/zephyr/emul/emul_tcs3400.c
index 15a1bbe9c7..e87deebc35 100644
--- a/zephyr/emul/emul_tcs3400.c
+++ b/zephyr/emul/emul_tcs3400.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,17 +13,14 @@ LOG_MODULE_REGISTER(emul_tcs);
 #include <zephyr/drivers/emul.h>
 #include <zephyr/drivers/i2c.h>
 #include <zephyr/drivers/i2c_emul.h>
-#include <ztest.h>
+#include <zephyr/ztest.h>
 
 #include "emul/emul_common_i2c.h"
 #include "emul/emul_tcs3400.h"
+#include "emul/emul_stub_device.h"
 
 #include "driver/als_tcs3400.h"
 
-#define TCS_DATA_FROM_I2C_EMUL(_emul)					     \
-	CONTAINER_OF(CONTAINER_OF(_emul, struct i2c_common_emul_data, emul), \
-		     struct tcs_emul_data, common)
-
 /** Run-time data used by the emulator */
 struct tcs_emul_data {
 	/** Common I2C data */
@@ -64,7 +61,7 @@ struct tcs_emul_data {
 };
 
 /** Check description in emul_tcs3400.h */
-void tcs_emul_set_reg(struct i2c_emul *emul, int reg, uint8_t val)
+void tcs_emul_set_reg(const struct emul *emul, int reg, uint8_t val)
 {
 	struct tcs_emul_data *data;
 
@@ -73,12 +70,12 @@ void tcs_emul_set_reg(struct i2c_emul *emul, int reg, uint8_t val)
 	}
 
 	reg -= TCS_EMUL_FIRST_REG;
-	data = TCS_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 	data->reg[reg] = val;
 }
 
 /** Check description in emul_tcs3400.h */
-uint8_t tcs_emul_get_reg(struct i2c_emul *emul, int reg)
+uint8_t tcs_emul_get_reg(const struct emul *emul, int reg)
 {
 	struct tcs_emul_data *data;
 
@@ -86,18 +83,18 @@ uint8_t tcs_emul_get_reg(struct i2c_emul *emul, int reg)
 		return 0;
 	}
 
-	data = TCS_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 	reg -= TCS_EMUL_FIRST_REG;
 
 	return data->reg[reg];
 }
 
 /** Check description in emul_tcs3400.h */
-int tcs_emul_get_val(struct i2c_emul *emul, enum tcs_emul_axis axis)
+int tcs_emul_get_val(const struct emul *emul, enum tcs_emul_axis axis)
 {
 	struct tcs_emul_data *data;
 
-	data = TCS_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	switch (axis) {
 	case TCS_EMUL_R:
@@ -116,11 +113,11 @@ int tcs_emul_get_val(struct i2c_emul *emul, enum tcs_emul_axis axis)
 }
 
 /** Check description in emul_tcs3400.h */
-void tcs_emul_set_val(struct i2c_emul *emul, enum tcs_emul_axis axis, int val)
+void tcs_emul_set_val(const struct emul *emul, enum tcs_emul_axis axis, int val)
 {
 	struct tcs_emul_data *data;
 
-	data = TCS_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	switch (axis) {
 	case TCS_EMUL_R:
@@ -142,59 +139,59 @@ void tcs_emul_set_val(struct i2c_emul *emul, enum tcs_emul_axis axis, int val)
 }
 
 /** Check description in emul_tcs3400.h */
-void tcs_emul_set_err_on_ro_write(struct i2c_emul *emul, bool set)
+void tcs_emul_set_err_on_ro_write(const struct emul *emul, bool set)
 {
 	struct tcs_emul_data *data;
 
-	data = TCS_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 	data->error_on_ro_write = set;
 }
 
 /** Check description in emul_tcs3400.h */
-void tcs_emul_set_err_on_rsvd_write(struct i2c_emul *emul, bool set)
+void tcs_emul_set_err_on_rsvd_write(const struct emul *emul, bool set)
 {
 	struct tcs_emul_data *data;
 
-	data = TCS_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 	data->error_on_rsvd_write = set;
 }
 
 /** Check description in emul_tcs3400.h */
-void tcs_emul_set_err_on_msb_first(struct i2c_emul *emul, bool set)
+void tcs_emul_set_err_on_msb_first(const struct emul *emul, bool set)
 {
 	struct tcs_emul_data *data;
 
-	data = TCS_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 	data->error_on_msb_first = set;
 }
 
 /** Mask reserved bits in registers of TCS3400 */
 static const uint8_t tcs_emul_rsvd_mask[] = {
-	[TCS_I2C_ENABLE  - TCS_EMUL_FIRST_REG]	= 0xa4,
-	[TCS_I2C_ATIME   - TCS_EMUL_FIRST_REG]	= 0x00,
-	[0x2]					= 0xff, /* Reserved */
-	[TCS_I2C_WTIME   - TCS_EMUL_FIRST_REG]	= 0x00,
-	[TCS_I2C_AILTL   - TCS_EMUL_FIRST_REG]	= 0x00,
-	[TCS_I2C_AILTH   - TCS_EMUL_FIRST_REG]	= 0x00,
-	[TCS_I2C_AIHTL   - TCS_EMUL_FIRST_REG]	= 0x00,
-	[TCS_I2C_AIHTH   - TCS_EMUL_FIRST_REG]	= 0x00,
-	[0x8 ... 0xb]				= 0xff, /* Reserved */
-	[TCS_I2C_PERS    - TCS_EMUL_FIRST_REG]	= 0xf0,
-	[TCS_I2C_CONFIG  - TCS_EMUL_FIRST_REG]	= 0x81,
-	[0xe]					= 0xff, /* Reserved */
-	[TCS_I2C_CONTROL - TCS_EMUL_FIRST_REG]	= 0xfc,
-	[TCS_I2C_AUX     - TCS_EMUL_FIRST_REG]	= 0xdf,
-	[TCS_I2C_REVID   - TCS_EMUL_FIRST_REG]	= 0xf0,
-	[TCS_I2C_ID      - TCS_EMUL_FIRST_REG]	= 0x00,
-	[TCS_I2C_STATUS  - TCS_EMUL_FIRST_REG]	= 0x6e,
-	[TCS_I2C_CDATAL  - TCS_EMUL_FIRST_REG]	= 0x00,
-	[TCS_I2C_CDATAH  - TCS_EMUL_FIRST_REG]	= 0x00,
-	[TCS_I2C_RDATAL  - TCS_EMUL_FIRST_REG]	= 0x00,
-	[TCS_I2C_RDATAH  - TCS_EMUL_FIRST_REG]	= 0x00,
-	[TCS_I2C_GDATAL  - TCS_EMUL_FIRST_REG]	= 0x00,
-	[TCS_I2C_GDATAH  - TCS_EMUL_FIRST_REG]	= 0x00,
-	[TCS_I2C_BDATAL  - TCS_EMUL_FIRST_REG]	= 0x00,
-	[TCS_I2C_BDATAH  - TCS_EMUL_FIRST_REG]	= 0x00,
+	[TCS_I2C_ENABLE - TCS_EMUL_FIRST_REG] = 0xa4,
+	[TCS_I2C_ATIME - TCS_EMUL_FIRST_REG] = 0x00,
+	[0x2] = 0xff, /* Reserved */
+	[TCS_I2C_WTIME - TCS_EMUL_FIRST_REG] = 0x00,
+	[TCS_I2C_AILTL - TCS_EMUL_FIRST_REG] = 0x00,
+	[TCS_I2C_AILTH - TCS_EMUL_FIRST_REG] = 0x00,
+	[TCS_I2C_AIHTL - TCS_EMUL_FIRST_REG] = 0x00,
+	[TCS_I2C_AIHTH - TCS_EMUL_FIRST_REG] = 0x00,
+	[0x8 ... 0xb] = 0xff, /* Reserved */
+	[TCS_I2C_PERS - TCS_EMUL_FIRST_REG] = 0xf0,
+	[TCS_I2C_CONFIG - TCS_EMUL_FIRST_REG] = 0x81,
+	[0xe] = 0xff, /* Reserved */
+	[TCS_I2C_CONTROL - TCS_EMUL_FIRST_REG] = 0xfc,
+	[TCS_I2C_AUX - TCS_EMUL_FIRST_REG] = 0xdf,
+	[TCS_I2C_REVID - TCS_EMUL_FIRST_REG] = 0xf0,
+	[TCS_I2C_ID - TCS_EMUL_FIRST_REG] = 0x00,
+	[TCS_I2C_STATUS - TCS_EMUL_FIRST_REG] = 0x6e,
+	[TCS_I2C_CDATAL - TCS_EMUL_FIRST_REG] = 0x00,
+	[TCS_I2C_CDATAH - TCS_EMUL_FIRST_REG] = 0x00,
+	[TCS_I2C_RDATAL - TCS_EMUL_FIRST_REG] = 0x00,
+	[TCS_I2C_RDATAH - TCS_EMUL_FIRST_REG] = 0x00,
+	[TCS_I2C_GDATAL - TCS_EMUL_FIRST_REG] = 0x00,
+	[TCS_I2C_GDATAH - TCS_EMUL_FIRST_REG] = 0x00,
+	[TCS_I2C_BDATAL - TCS_EMUL_FIRST_REG] = 0x00,
+	[TCS_I2C_BDATAH - TCS_EMUL_FIRST_REG] = 0x00,
 };
 
 /**
@@ -202,34 +199,34 @@ static const uint8_t tcs_emul_rsvd_mask[] = {
  *
  * @param emul Pointer to TCS3400 emulator
  */
-static void tcs_emul_reset(struct i2c_emul *emul)
+static void tcs_emul_reset(const struct emul *emul)
 {
 	struct tcs_emul_data *data;
 
-	data = TCS_DATA_FROM_I2C_EMUL(emul);
-
-	data->reg[TCS_I2C_ENABLE  - TCS_EMUL_FIRST_REG] = 0x00;
-	data->reg[TCS_I2C_ATIME   - TCS_EMUL_FIRST_REG] = 0xff;
-	data->reg[TCS_I2C_WTIME   - TCS_EMUL_FIRST_REG] = 0xff;
-	data->reg[TCS_I2C_AILTL   - TCS_EMUL_FIRST_REG] = 0x00;
-	data->reg[TCS_I2C_AILTH   - TCS_EMUL_FIRST_REG] = 0x00;
-	data->reg[TCS_I2C_AIHTL   - TCS_EMUL_FIRST_REG] = 0x00;
-	data->reg[TCS_I2C_AIHTH   - TCS_EMUL_FIRST_REG] = 0x00;
-	data->reg[TCS_I2C_PERS    - TCS_EMUL_FIRST_REG] = 0x00;
-	data->reg[TCS_I2C_CONFIG  - TCS_EMUL_FIRST_REG] = 0x40;
+	data = emul->data;
+
+	data->reg[TCS_I2C_ENABLE - TCS_EMUL_FIRST_REG] = 0x00;
+	data->reg[TCS_I2C_ATIME - TCS_EMUL_FIRST_REG] = 0xff;
+	data->reg[TCS_I2C_WTIME - TCS_EMUL_FIRST_REG] = 0xff;
+	data->reg[TCS_I2C_AILTL - TCS_EMUL_FIRST_REG] = 0x00;
+	data->reg[TCS_I2C_AILTH - TCS_EMUL_FIRST_REG] = 0x00;
+	data->reg[TCS_I2C_AIHTL - TCS_EMUL_FIRST_REG] = 0x00;
+	data->reg[TCS_I2C_AIHTH - TCS_EMUL_FIRST_REG] = 0x00;
+	data->reg[TCS_I2C_PERS - TCS_EMUL_FIRST_REG] = 0x00;
+	data->reg[TCS_I2C_CONFIG - TCS_EMUL_FIRST_REG] = 0x40;
 	data->reg[TCS_I2C_CONTROL - TCS_EMUL_FIRST_REG] = 0x00;
-	data->reg[TCS_I2C_AUX     - TCS_EMUL_FIRST_REG] = 0x00;
-	data->reg[TCS_I2C_REVID   - TCS_EMUL_FIRST_REG] = data->revision;
-	data->reg[TCS_I2C_ID      - TCS_EMUL_FIRST_REG] = data->id;
-	data->reg[TCS_I2C_STATUS  - TCS_EMUL_FIRST_REG] = 0x00;
-	data->reg[TCS_I2C_CDATAL  - TCS_EMUL_FIRST_REG] = 0x00;
-	data->reg[TCS_I2C_CDATAH  - TCS_EMUL_FIRST_REG] = 0x00;
-	data->reg[TCS_I2C_RDATAL  - TCS_EMUL_FIRST_REG] = 0x00;
-	data->reg[TCS_I2C_RDATAH  - TCS_EMUL_FIRST_REG] = 0x00;
-	data->reg[TCS_I2C_GDATAL  - TCS_EMUL_FIRST_REG] = 0x00;
-	data->reg[TCS_I2C_GDATAH  - TCS_EMUL_FIRST_REG] = 0x00;
-	data->reg[TCS_I2C_BDATAL  - TCS_EMUL_FIRST_REG] = 0x00;
-	data->reg[TCS_I2C_BDATAH  - TCS_EMUL_FIRST_REG] = 0x00;
+	data->reg[TCS_I2C_AUX - TCS_EMUL_FIRST_REG] = 0x00;
+	data->reg[TCS_I2C_REVID - TCS_EMUL_FIRST_REG] = data->revision;
+	data->reg[TCS_I2C_ID - TCS_EMUL_FIRST_REG] = data->id;
+	data->reg[TCS_I2C_STATUS - TCS_EMUL_FIRST_REG] = 0x00;
+	data->reg[TCS_I2C_CDATAL - TCS_EMUL_FIRST_REG] = 0x00;
+	data->reg[TCS_I2C_CDATAH - TCS_EMUL_FIRST_REG] = 0x00;
+	data->reg[TCS_I2C_RDATAL - TCS_EMUL_FIRST_REG] = 0x00;
+	data->reg[TCS_I2C_RDATAH - TCS_EMUL_FIRST_REG] = 0x00;
+	data->reg[TCS_I2C_GDATAL - TCS_EMUL_FIRST_REG] = 0x00;
+	data->reg[TCS_I2C_GDATAH - TCS_EMUL_FIRST_REG] = 0x00;
+	data->reg[TCS_I2C_BDATAL - TCS_EMUL_FIRST_REG] = 0x00;
+	data->reg[TCS_I2C_BDATAH - TCS_EMUL_FIRST_REG] = 0x00;
 
 	data->ir_select = false;
 }
@@ -274,13 +271,13 @@ static int tcs_emul_get_cycles(uint8_t atime)
  *
  * @param emul Pointer to TCS3400 emulator
  */
-static void tcs_emul_clear_int(struct i2c_emul *emul)
+static void tcs_emul_clear_int(const struct emul *emul)
 {
 	struct tcs_emul_data *data;
 
-	data = TCS_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
-	data->reg[TCS_I2C_STATUS  - TCS_EMUL_FIRST_REG] = 0x00;
+	data->reg[TCS_I2C_STATUS - TCS_EMUL_FIRST_REG] = 0x00;
 }
 
 /**
@@ -296,12 +293,12 @@ static void tcs_emul_clear_int(struct i2c_emul *emul)
  * @return 0 on success
  * @return -EIO on error
  */
-static int tcs_emul_handle_write(struct i2c_emul *emul, int reg, int bytes)
+static int tcs_emul_handle_write(const struct emul *emul, int reg, int bytes)
 {
 	struct tcs_emul_data *data;
 	uint8_t val;
 
-	data = TCS_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	/* This write only selected register for I2C read message */
 	if (bytes < 2) {
@@ -388,7 +385,7 @@ static int tcs_emul_handle_write(struct i2c_emul *emul, int reg, int bytes)
  * @return 0 on success
  * @return -EIO when accessing MSB before LSB
  */
-static int tcs_emul_get_reg_val(struct i2c_emul *emul, int reg,
+static int tcs_emul_get_reg_val(const struct emul *emul, int reg,
 				bool *lsb_read, bool lsb, unsigned int val)
 {
 	struct tcs_emul_data *data;
@@ -398,7 +395,7 @@ static int tcs_emul_get_reg_val(struct i2c_emul *emul, int reg,
 	int cycles;
 	int gain;
 
-	data = TCS_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	if (lsb) {
 		*lsb_read = 1;
@@ -418,10 +415,10 @@ static int tcs_emul_get_reg_val(struct i2c_emul *emul, int reg,
 	lsb_reg = (reg - TCS_EMUL_FIRST_REG) & ~(0x1);
 	msb_reg = (reg - TCS_EMUL_FIRST_REG) | 0x1;
 
-	gain = tcs_emul_get_gain(data->reg[TCS_I2C_CONTROL -
-					   TCS_EMUL_FIRST_REG]);
-	cycles = tcs_emul_get_cycles(data->reg[TCS_I2C_ATIME -
-					       TCS_EMUL_FIRST_REG]);
+	gain = tcs_emul_get_gain(
+		data->reg[TCS_I2C_CONTROL - TCS_EMUL_FIRST_REG]);
+	cycles = tcs_emul_get_cycles(
+		data->reg[TCS_I2C_ATIME - TCS_EMUL_FIRST_REG]);
 	/*
 	 * Internal value is with 256 cycles and x64 gain, so divide it to get
 	 * registers value
@@ -452,14 +449,14 @@ static int tcs_emul_get_reg_val(struct i2c_emul *emul, int reg,
  * @return 0 on success
  * @return -EIO on error
  */
-static int tcs_emul_handle_read(struct i2c_emul *emul, int reg, uint8_t *buf,
+static int tcs_emul_handle_read(const struct emul *emul, int reg, uint8_t *buf,
 				int bytes)
 {
 	struct tcs_emul_data *data;
 	unsigned int c_ir;
 	int ret;
 
-	data = TCS_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	reg += bytes;
 
@@ -487,12 +484,12 @@ static int tcs_emul_handle_read(struct i2c_emul *emul, int reg, uint8_t *buf,
 		break;
 	case TCS_I2C_RDATAL:
 		/* Shouldn't fail for LSB */
-		ret = tcs_emul_get_reg_val(emul, reg, &data->lsb_r_read,
-					   true, data->red);
+		ret = tcs_emul_get_reg_val(emul, reg, &data->lsb_r_read, true,
+					   data->red);
 		break;
 	case TCS_I2C_RDATAH:
-		ret = tcs_emul_get_reg_val(emul, reg, &data->lsb_r_read,
-					   false, data->red);
+		ret = tcs_emul_get_reg_val(emul, reg, &data->lsb_r_read, false,
+					   data->red);
 		if (ret) {
 			LOG_ERR("MSB R read before LSB R");
 			return -EIO;
@@ -500,12 +497,12 @@ static int tcs_emul_handle_read(struct i2c_emul *emul, int reg, uint8_t *buf,
 		break;
 	case TCS_I2C_GDATAL:
 		/* Shouldn't fail for LSB */
-		ret = tcs_emul_get_reg_val(emul, reg, &data->lsb_g_read,
-					   true, data->green);
+		ret = tcs_emul_get_reg_val(emul, reg, &data->lsb_g_read, true,
+					   data->green);
 		break;
 	case TCS_I2C_GDATAH:
-		ret = tcs_emul_get_reg_val(emul, reg, &data->lsb_g_read,
-					   false, data->green);
+		ret = tcs_emul_get_reg_val(emul, reg, &data->lsb_g_read, false,
+					   data->green);
 		if (ret) {
 			LOG_ERR("MSB G read before LSB G");
 			return -EIO;
@@ -513,12 +510,12 @@ static int tcs_emul_handle_read(struct i2c_emul *emul, int reg, uint8_t *buf,
 		break;
 	case TCS_I2C_BDATAL:
 		/* Shouldn't fail for LSB */
-		ret = tcs_emul_get_reg_val(emul, reg, &data->lsb_b_read,
-					   true, data->blue);
+		ret = tcs_emul_get_reg_val(emul, reg, &data->lsb_b_read, true,
+					   data->blue);
 		break;
 	case TCS_I2C_BDATAH:
-		ret = tcs_emul_get_reg_val(emul, reg, &data->lsb_b_read,
-					   false, data->blue);
+		ret = tcs_emul_get_reg_val(emul, reg, &data->lsb_b_read, false,
+					   data->blue);
 		if (ret) {
 			LOG_ERR("MSB B read before LSB B");
 			return -EIO;
@@ -547,12 +544,12 @@ static int tcs_emul_handle_read(struct i2c_emul *emul, int reg, uint8_t *buf,
  * @return 0 on success
  * @return -EIO on error
  */
-static int tcs_emul_write_byte(struct i2c_emul *emul, int reg, uint8_t val,
+static int tcs_emul_write_byte(const struct emul *emul, int reg, uint8_t val,
 			       int bytes)
 {
 	struct tcs_emul_data *data;
 
-	data = TCS_DATA_FROM_I2C_EMUL(emul);
+	data = emul->data;
 
 	if (bytes > 1) {
 		LOG_ERR("Too long write command");
@@ -577,27 +574,20 @@ static int tcs_emul_write_byte(struct i2c_emul *emul, int reg, uint8_t val,
  *
  * @return 0 indicating success (always)
  */
-static int tcs_emul_init(const struct emul *emul,
-			 const struct device *parent)
+static int tcs_emul_init(const struct emul *emul, const struct device *parent)
 {
-	const struct i2c_common_emul_cfg *cfg = emul->cfg;
-	struct i2c_common_emul_data *data = cfg->data;
-	int ret;
+	struct tcs_emul_data *data = emul->data;
 
-	data->emul.api = &i2c_common_emul_api;
-	data->emul.addr = cfg->addr;
-	data->i2c = parent;
-	data->cfg = cfg;
-	i2c_common_emul_init(data);
+	data->common.i2c = parent;
 
-	ret = i2c_emul_register(parent, emul->dev_label, &data->emul);
+	i2c_common_emul_init(&data->common);
 
-	tcs_emul_reset(&data->emul);
+	tcs_emul_reset(emul);
 
-	return ret;
+	return 0;
 }
 
-#define TCS3400_EMUL(n)							\
+#define TCS3400_EMUL(n)                                              \
 	static struct tcs_emul_data tcs_emul_data_##n = {		\
 		.revision = DT_INST_PROP(n, revision),			\
 		.id = DT_STRING_TOKEN(DT_DRV_INST(n), device_id),		\
@@ -619,36 +609,22 @@ static int tcs_emul_init(const struct emul *emul,
 			.finish_read = NULL,				\
 			.access_reg = NULL,				\
 		},							\
-	};								\
-									\
-	static const struct i2c_common_emul_cfg tcs_emul_cfg_##n = {	\
-		.i2c_label = DT_INST_BUS_LABEL(n),			\
-		.dev_label = DT_INST_LABEL(n),                          \
-		.data = &tcs_emul_data_##n.common,			\
-		.addr = DT_INST_REG_ADDR(n),				\
-	};								\
-	EMUL_DEFINE(tcs_emul_init, DT_DRV_INST(n), &tcs_emul_cfg_##n,	\
-		    &tcs_emul_data_##n)
+	};         \
+                                                                     \
+	static const struct i2c_common_emul_cfg tcs_emul_cfg_##n = { \
+		.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)),      \
+		.data = &tcs_emul_data_##n.common,                   \
+		.addr = DT_INST_REG_ADDR(n),                         \
+	};                                                           \
+	EMUL_DT_INST_DEFINE(n, tcs_emul_init, &tcs_emul_data_##n,    \
+			    &tcs_emul_cfg_##n, &i2c_common_emul_api)
 
 DT_INST_FOREACH_STATUS_OKAY(TCS3400_EMUL)
 
-#define TCS3400_EMUL_CASE(n)					\
-	case DT_INST_DEP_ORD(n): return &tcs_emul_data_##n.common.emul;
-
-/** Check description in emul_tcs3400.h */
-struct i2c_emul *tcs_emul_get(int ord)
-{
-	switch (ord) {
-	DT_INST_FOREACH_STATUS_OKAY(TCS3400_EMUL_CASE)
-
-	default:
-		return NULL;
-	}
-}
-
 #ifdef CONFIG_ZTEST_NEW_API
 #define TCS3400_EMUL_RESET_RULE_BEFORE(n) \
-	tcs_emul_reset(&(tcs_emul_data_##n.common.emul));
+	tcs_emul_reset(EMUL_DT_GET(DT_DRV_INST(n)));
+
 static void emul_tcs3400_reset_rule_before(const struct ztest_unit_test *test,
 					   void *data)
 {
@@ -658,3 +634,11 @@ static void emul_tcs3400_reset_rule_before(const struct ztest_unit_test *test,
 }
 ZTEST_RULE(emul_tcs3400_reset, emul_tcs3400_reset_rule_before, NULL);
 #endif /* CONFIG_ZTEST_NEW_API */
+
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
+
+struct i2c_common_emul_data *
+emul_tcs3400_get_i2c_common_data(const struct emul *emul)
+{
+	return emul->data;
+}
diff --git a/zephyr/emul/i2c_mock.c b/zephyr/emul/i2c_mock.c
index e7750d5b72..8601c87ee7 100644
--- a/zephyr/emul/i2c_mock.c
+++ b/zephyr/emul/i2c_mock.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,9 +6,11 @@
 #define DT_DRV_COMPAT cros_i2c_mock
 
 #include <zephyr/device.h>
+#include <zephyr/logging/log.h>
+
 #include "emul/emul_common_i2c.h"
+#include "emul/emul_stub_device.h"
 
-#include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(i2c_mock, CONFIG_I2C_MOCK_LOG_LEVEL);
 
 struct i2c_emul *i2c_mock_to_i2c_emul(const struct emul *emul)
@@ -20,14 +22,12 @@ struct i2c_emul *i2c_mock_to_i2c_emul(const struct emul *emul)
 
 void i2c_mock_reset(const struct emul *emul)
 {
-	struct i2c_emul *i2c_emul = i2c_mock_to_i2c_emul(emul);
-
-	i2c_common_emul_set_read_fail_reg(i2c_emul,
+	i2c_common_emul_set_read_fail_reg(emul->data,
 					  I2C_COMMON_EMUL_NO_FAIL_REG);
-	i2c_common_emul_set_write_fail_reg(i2c_emul,
+	i2c_common_emul_set_write_fail_reg(emul->data,
 					   I2C_COMMON_EMUL_NO_FAIL_REG);
-	i2c_common_emul_set_read_func(i2c_emul, NULL, NULL);
-	i2c_common_emul_set_write_func(i2c_emul, NULL, NULL);
+	i2c_common_emul_set_read_func(emul->data, NULL, NULL);
+	i2c_common_emul_set_write_func(emul->data, NULL, NULL);
 }
 
 uint16_t i2c_mock_get_addr(const struct emul *emul)
@@ -41,30 +41,36 @@ static const struct i2c_emul_api i2c_mock_api = {
 	.transfer = i2c_common_emul_transfer,
 };
 
-static int i2c_mock_init(const struct emul *emul,
-			 const struct device *parent)
+static int i2c_mock_init(const struct emul *emul, const struct device *parent)
 {
 	const struct i2c_common_emul_cfg *cfg = emul->cfg;
 	struct i2c_common_emul_data *data = emul->data;
 
 	data->emul.api = &i2c_mock_api;
 	data->emul.addr = cfg->addr;
-	data->emul.parent = emul;
+	data->emul.target = emul;
 	data->i2c = parent;
 	data->cfg = cfg;
 	i2c_common_emul_init(data);
 
-	return i2c_emul_register(parent, emul->dev_label, &data->emul);
+	return 0;
 }
 
-#define INIT_I2C_MOCK(n)                                              \
-	static const struct i2c_common_emul_cfg i2c_mock_cfg_##n = {  \
-		.i2c_label = DT_INST_BUS_LABEL(n),                    \
-		.dev_label = DT_INST_LABEL(n),                        \
-		.addr = DT_INST_REG_ADDR(n),                          \
-	};                                                            \
-	static struct i2c_common_emul_data i2c_mock_data_##n;         \
-	EMUL_DEFINE(i2c_mock_init, DT_DRV_INST(n), &i2c_mock_cfg_##n, \
-		    &i2c_mock_data_##n)
+#define INIT_I2C_MOCK(n)                                             \
+	static const struct i2c_common_emul_cfg i2c_mock_cfg_##n = { \
+		.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)),      \
+		.addr = DT_INST_REG_ADDR(n),                         \
+	};                                                           \
+	static struct i2c_common_emul_data i2c_mock_data_##n;        \
+	EMUL_DT_INST_DEFINE(n, i2c_mock_init, &i2c_mock_data_##n,    \
+			    &i2c_mock_cfg_##n, &i2c_common_emul_api)
 
 DT_INST_FOREACH_STATUS_OKAY(INIT_I2C_MOCK)
+
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
+
+struct i2c_common_emul_data *
+emul_i2c_mock_get_i2c_common_data(const struct emul *emul)
+{
+	return emul->data;
+}
diff --git a/zephyr/emul/include/flash_chip.h b/zephyr/emul/include/flash_chip.h
index 0060935b98..947246867b 100644
--- a/zephyr/emul/include/flash_chip.h
+++ b/zephyr/emul/include/flash_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,11 +6,11 @@
 #ifndef __EMUL_INCLUDE_FLASH_CHIP_H
 #define __EMUL_INCLUDE_FLASH_CHIP_H
 
-#define CONFIG_RO_STORAGE_OFF           0x0
-#define CONFIG_RW_STORAGE_OFF           0x0
-#define CONFIG_FLASH_WRITE_SIZE		0x1  /* minimum write size */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE	256   /* one page size for write */
-#define CONFIG_FLASH_ERASE_SIZE	0x10000
-#define CONFIG_FLASH_BANK_SIZE		CONFIG_FLASH_ERASE_SIZE
+#define CONFIG_RO_STORAGE_OFF 0x0
+#define CONFIG_RW_STORAGE_OFF 0x0
+#define CONFIG_FLASH_WRITE_SIZE 0x1 /* minimum write size */
+#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* one page size for write */
+#define CONFIG_FLASH_ERASE_SIZE 0x10000
+#define CONFIG_FLASH_BANK_SIZE CONFIG_FLASH_ERASE_SIZE
 
 #endif /* __EMUL_INCLUDE_FLASH_CHIP_H */
diff --git a/zephyr/emul/include/pwm_mock.h b/zephyr/emul/include/pwm_mock.h
new file mode 100644
index 0000000000..7f5eb9eb89
--- /dev/null
+++ b/zephyr/emul/include/pwm_mock.h
@@ -0,0 +1,33 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __EMUL_INCLUDE_PWM_MOCK_H
+#define __EMUL_INCLUDE_PWM_MOCK_H
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/pwm.h>
+
+/*
+ * Get pwm duty cycle
+ *
+ * @param dev		pointer to hte pwm device
+ * @param channel	channel id
+ *
+ * @return duty		duty cycle in range [0, 100] or negative on error.
+ */
+int pwm_mock_get_duty(const struct device *dev, uint32_t channel);
+
+/**
+ * @brief Get the flags the PWM driver was set with. See the following header
+ *        in upstream Zephyr for possible values:
+ *        `include/zephyr/dt-bindings/pwm/pwm.h`
+ *
+ * @param dev Pointer to PWM device
+ * @param channel Unused
+ * @return pwm_flags_t PWM flags
+ */
+pwm_flags_t pwm_mock_get_flags(const struct device *dev, uint32_t channel);
+
+#endif /*__EMUL_INCLUDE_PWM_MOCK_H */
diff --git a/zephyr/emul/pwm_mock.c b/zephyr/emul/pwm_mock.c
new file mode 100644
index 0000000000..0d32155d8f
--- /dev/null
+++ b/zephyr/emul/pwm_mock.c
@@ -0,0 +1,80 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define DT_DRV_COMPAT cros_pwm_mock
+
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/pwm.h>
+
+#include "pwm_mock.h"
+
+#define CYCLES_PER_SEC 1000000
+
+struct pwm_mock_data {
+	uint32_t period_cycles;
+	uint32_t pulse_cycles;
+	pwm_flags_t pwm_flags;
+};
+
+static int pwm_mock_init(const struct device *dev)
+{
+	return 0;
+}
+
+static int pwm_mock_set_cycles(const struct device *dev, uint32_t channel,
+			       uint32_t period_cycles, uint32_t pulse_cycles,
+			       pwm_flags_t flags)
+{
+	struct pwm_mock_data *const data = dev->data;
+
+	data->period_cycles = period_cycles;
+	data->pulse_cycles = pulse_cycles;
+	data->pwm_flags = flags;
+
+	return 0;
+}
+
+static int pwm_mock_get_cycles_per_sec(const struct device *dev,
+				       uint32_t channel, uint64_t *cycles)
+{
+	*cycles = CYCLES_PER_SEC;
+
+	return 0;
+}
+
+int pwm_mock_get_duty(const struct device *dev, uint32_t channel)
+{
+	struct pwm_mock_data *const data = dev->data;
+
+	if (data->period_cycles == 0) {
+		return -EINVAL;
+	}
+
+	return data->pulse_cycles * 100 / data->period_cycles;
+}
+
+pwm_flags_t pwm_mock_get_flags(const struct device *dev, uint32_t channel)
+{
+	ARG_UNUSED(channel);
+
+	struct pwm_mock_data *const data = dev->data;
+
+	return data->pwm_flags;
+}
+
+static const struct pwm_driver_api pwm_mock_api = {
+	.set_cycles = pwm_mock_set_cycles,
+	.get_cycles_per_sec = pwm_mock_get_cycles_per_sec,
+};
+
+#define INIT_PWM_MOCK(inst)                                             \
+	static struct pwm_mock_data pwm_mock_data##inst;                \
+	DEVICE_DT_INST_DEFINE(inst, &pwm_mock_init, NULL,               \
+			      &pwm_mock_data##inst, NULL, PRE_KERNEL_1, \
+			      CONFIG_KERNEL_INIT_PRIORITY_DEVICE,       \
+			      &pwm_mock_api);
+DT_INST_FOREACH_STATUS_OKAY(INIT_PWM_MOCK)
diff --git a/zephyr/emul/tcpc/CMakeLists.txt b/zephyr/emul/tcpc/CMakeLists.txt
index c6200bbfc3..b43d73ead3 100644
--- a/zephyr/emul/tcpc/CMakeLists.txt
+++ b/zephyr/emul/tcpc/CMakeLists.txt
@@ -1,11 +1,12 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 zephyr_library_sources_ifdef(CONFIG_EMUL_PS8XXX		emul_ps8xxx.c)
 zephyr_library_sources_ifdef(CONFIG_EMUL_TCPCI		emul_tcpci.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_TCPCI		emul_tcpci_generic.c)
 zephyr_library_sources_ifdef(CONFIG_EMUL_TCPCI_PARTNER_COMMON	emul_tcpci_partner_common.c)
 zephyr_library_sources_ifdef(CONFIG_EMUL_TCPCI_PARTNER_DRP	emul_tcpci_partner_drp.c)
 zephyr_library_sources_ifdef(CONFIG_EMUL_TCPCI_PARTNER_SNK	emul_tcpci_partner_snk.c)
 zephyr_library_sources_ifdef(CONFIG_EMUL_TCPCI_PARTNER_SRC	emul_tcpci_partner_src.c)
-zephyr_library_sources_ifdef(CONFIG_EMUL_TCPCI_PARTNER_FAULTY_SNK	emul_tcpci_partner_faulty_snk.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_TCPCI_PARTNER_FAULTY_EXT	emul_tcpci_partner_faulty_ext.c)
diff --git a/zephyr/emul/tcpc/Kconfig b/zephyr/emul/tcpc/Kconfig
index 127b12e00f..6866e7bab5 100644
--- a/zephyr/emul/tcpc/Kconfig
+++ b/zephyr/emul/tcpc/Kconfig
@@ -1,12 +1,9 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
-DT_COMPAT_TCPCI_EMUL := cros,tcpci-emul
-
 menuconfig EMUL_TCPCI
-	bool "TCPCI emulator"
-	default $(dt_compat_enabled,$(DT_COMPAT_TCPCI_EMUL))
+	bool "TCPCI common functionality"
 	depends on I2C_EMUL
 	help
 	  Enable the TCPCI emulator. This driver uses the emulated I2C bus.
@@ -63,13 +60,13 @@ config EMUL_TCPCI_PARTNER_DRP
 	  emulator. API of dual role device emulator is available in
 	  zephyr/include/emul/tcpc/emul_tcpci_partner_drp.h
 
-config EMUL_TCPCI_PARTNER_FAULTY_SNK
-	bool "USB-C malfunctioning sink device emulator"
+config EMUL_TCPCI_PARTNER_FAULTY_EXT
+	bool "USB-C malfunctioning device emulator"
 	select EMUL_TCPCI_PARTNER_COMMON
 	select EMUL_TCPCI_PARTNER_SNK
 	help
-	  Enable USB-C malfunctioning sink device emulator which may be attached
-	  to TCPCI emulator. API of malfunctioning sink device emulator is
-	  available in zephyr/include/emul/tcpc/emul_tcpci_partner_faulty_snk.h
+	  Enable USB-C malfunctioning device emulator which may be attached
+	  to TCPCI emulator. API of malfunctioning device emulator is
+	  available in zephyr/include/emul/tcpc/emul_tcpci_partner_faulty_ext.h
 
 endif # EMUL_TCPCI
diff --git a/zephyr/emul/tcpc/emul_ps8xxx.c b/zephyr/emul/tcpc/emul_ps8xxx.c
index 2fc372c9a7..467a487802 100644
--- a/zephyr/emul/tcpc/emul_ps8xxx.c
+++ b/zephyr/emul/tcpc/emul_ps8xxx.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,16 +12,18 @@ LOG_MODULE_REGISTER(ps8xxx_emul, CONFIG_TCPCI_EMUL_LOG_LEVEL);
 #include <zephyr/drivers/emul.h>
 #include <zephyr/drivers/i2c.h>
 #include <zephyr/drivers/i2c_emul.h>
+#include <zephyr/ztest.h>
 
 #include "tcpm/tcpci.h"
 
 #include "emul/emul_common_i2c.h"
 #include "emul/tcpc/emul_ps8xxx.h"
 #include "emul/tcpc/emul_tcpci.h"
+#include "emul/emul_stub_device.h"
 
 #include "driver/tcpm/ps8xxx.h"
 
-#define PS8XXX_REG_MUX_IN_HPD_ASSERTION		MUX_IN_HPD_ASSERTION_REG
+#define PS8XXX_REG_MUX_IN_HPD_ASSERTION MUX_IN_HPD_ASSERTION_REG
 
 /** Run-time data used by the emulator */
 struct ps8xxx_emul_data {
@@ -32,8 +34,6 @@ struct ps8xxx_emul_data {
 
 	/** Product ID of emulated device */
 	int prod_id;
-	/** Pointer to TCPCI emulator that is base for this emulator */
-	const struct emul *tcpci_emul;
 
 	/** Chip revision used by PS8805 */
 	uint8_t chip_rev;
@@ -47,9 +47,6 @@ struct ps8xxx_emul_data {
 
 /** Constant configuration of the emulator */
 struct ps8xxx_emul_cfg {
-	/** Phandle (name) of TCPCI emulator that is base for this emulator */
-	const char *tcpci_emul;
-
 	/** Common I2C configuration used by "hidden" ports */
 	const struct i2c_common_emul_cfg p0_cfg;
 	const struct i2c_common_emul_cfg p1_cfg;
@@ -59,7 +56,8 @@ struct ps8xxx_emul_cfg {
 /** Check description in emul_ps8xxx.h */
 void ps8xxx_emul_set_chip_rev(const struct emul *emul, uint8_t chip_rev)
 {
-	struct ps8xxx_emul_data *data = emul->data;
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct ps8xxx_emul_data *data = tcpc_data->chip_data;
 
 	data->chip_rev = chip_rev;
 }
@@ -67,7 +65,8 @@ void ps8xxx_emul_set_chip_rev(const struct emul *emul, uint8_t chip_rev)
 /** Check description in emul_ps8xxx.h */
 void ps8xxx_emul_set_hw_rev(const struct emul *emul, uint16_t hw_rev)
 {
-	struct ps8xxx_emul_data *data = emul->data;
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct ps8xxx_emul_data *data = tcpc_data->chip_data;
 
 	data->hw_rev = hw_rev;
 }
@@ -75,7 +74,8 @@ void ps8xxx_emul_set_hw_rev(const struct emul *emul, uint16_t hw_rev)
 /** Check description in emul_ps8xxx.h */
 void ps8xxx_emul_set_gpio_ctrl(const struct emul *emul, uint8_t gpio_ctrl)
 {
-	struct ps8xxx_emul_data *data = emul->data;
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct ps8xxx_emul_data *data = tcpc_data->chip_data;
 
 	data->gpio_ctrl = gpio_ctrl;
 }
@@ -83,7 +83,8 @@ void ps8xxx_emul_set_gpio_ctrl(const struct emul *emul, uint8_t gpio_ctrl)
 /** Check description in emul_ps8xxx.h */
 uint8_t ps8xxx_emul_get_gpio_ctrl(const struct emul *emul)
 {
-	struct ps8xxx_emul_data *data = emul->data;
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct ps8xxx_emul_data *data = tcpc_data->chip_data;
 
 	return data->gpio_ctrl;
 }
@@ -91,7 +92,8 @@ uint8_t ps8xxx_emul_get_gpio_ctrl(const struct emul *emul)
 /** Check description in emul_ps8xxx.h */
 uint8_t ps8xxx_emul_get_dci_cfg(const struct emul *emul)
 {
-	struct ps8xxx_emul_data *data = emul->data;
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct ps8xxx_emul_data *data = tcpc_data->chip_data;
 
 	return data->dci_cfg;
 }
@@ -99,7 +101,8 @@ uint8_t ps8xxx_emul_get_dci_cfg(const struct emul *emul)
 /** Check description in emul_ps8xxx.h */
 int ps8xxx_emul_set_product_id(const struct emul *emul, uint16_t product_id)
 {
-	struct ps8xxx_emul_data *data = emul->data;
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct ps8xxx_emul_data *data = tcpc_data->chip_data;
 
 	if (product_id != PS8805_PRODUCT_ID &&
 	    product_id != PS8815_PRODUCT_ID) {
@@ -108,7 +111,7 @@ int ps8xxx_emul_set_product_id(const struct emul *emul, uint16_t product_id)
 	}
 
 	data->prod_id = product_id;
-	tcpci_emul_set_reg(data->tcpci_emul, TCPC_REG_PRODUCT_ID, product_id);
+	tcpci_emul_set_reg(emul, TCPC_REG_PRODUCT_ID, product_id);
 
 	return 0;
 }
@@ -116,33 +119,29 @@ int ps8xxx_emul_set_product_id(const struct emul *emul, uint16_t product_id)
 /** Check description in emul_ps8xxx.h */
 uint16_t ps8xxx_emul_get_product_id(const struct emul *emul)
 {
-	struct ps8xxx_emul_data *data = emul->data;
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct ps8xxx_emul_data *data = tcpc_data->chip_data;
 
 	return data->prod_id;
 }
 
-const struct emul *ps8xxx_emul_get_tcpci(const struct emul *emul)
-{
-	struct ps8xxx_emul_data *data = emul->data;
-
-	return data->tcpci_emul;
-}
-
 /** Check description in emul_ps8xxx.h */
-struct i2c_emul *ps8xxx_emul_get_i2c_emul(const struct emul *emul,
-					  enum ps8xxx_emul_port port)
+struct i2c_common_emul_data *
+ps8xxx_emul_get_i2c_common_data(const struct emul *emul,
+				enum ps8xxx_emul_port port)
 {
 	const struct ps8xxx_emul_cfg *cfg = emul->cfg;
-	struct ps8xxx_emul_data *data = emul->data;
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct ps8xxx_emul_data *data = tcpc_data->chip_data;
 
 	switch (port) {
 	case PS8XXX_EMUL_PORT_0:
-		return &data->p0_data.emul;
+		return &data->p0_data;
 	case PS8XXX_EMUL_PORT_1:
-		return &data->p1_data.emul;
+		return &data->p1_data;
 	case PS8XXX_EMUL_PORT_GPIO:
 		if (cfg->gpio_cfg.addr != 0) {
-			return &data->gpio_data.emul;
+			return &data->gpio_data;
 		} else {
 			return NULL;
 		}
@@ -152,24 +151,23 @@ struct i2c_emul *ps8xxx_emul_get_i2c_emul(const struct emul *emul,
 }
 
 /**
- * @brief Function called for each byte of read message
+ * @brief Function called for each byte of read message from TCPC chip
  *
- * @param emul Pointer to TCPCI emulator
- * @param ops Pointer to device operations structure
+ * @param i2c_emul Pointer to PS8xxx emulator
  * @param reg First byte of last write message
  * @param val Pointer where byte to read should be stored
- * @param bytes Number of bytes already readded
+ * @param bytes Number of bytes already read
  *
- * @return TCPCI_EMUL_CONTINUE to continue with default handler
- * @return TCPCI_EMUL_DONE to immedietly return success
- * @return TCPCI_EMUL_ERROR to immedietly return error
+ * @return 0 on success
+ * @return -EIO on invalid read request
  */
-static enum tcpci_emul_ops_resp ps8xxx_emul_tcpci_read_byte(
-					const struct emul *emul,
-					const struct tcpci_emul_dev_ops *ops,
-					int reg, uint8_t *val, int bytes)
+static int ps8xxx_emul_tcpc_read_byte(const struct emul *emul, int reg,
+				      uint8_t *val, int bytes)
 {
 	uint16_t reg_val;
+	const struct i2c_emul *i2c_emul = emul->bus.i2c;
+
+	LOG_DBG("PS8XXX TCPC 0x%x: read reg 0x%x", i2c_emul->addr, reg);
 
 	switch (reg) {
 	case PS8XXX_REG_FW_REV:
@@ -182,36 +180,37 @@ static enum tcpci_emul_ops_resp ps8xxx_emul_tcpci_read_byte(
 		if (bytes != 0) {
 			LOG_ERR("Reading byte %d from 1 byte register 0x%x",
 				bytes, reg);
-			return TCPCI_EMUL_ERROR;
+			return -EIO;
 		}
 
 		tcpci_emul_get_reg(emul, reg, &reg_val);
 		*val = reg_val & 0xff;
-		return TCPCI_EMUL_DONE;
+		return 0;
 	default:
-		return TCPCI_EMUL_CONTINUE;
+		break;
 	}
+
+	return tcpci_emul_read_byte(emul, reg, val, bytes);
 }
 
 /**
- * @brief Function called for each byte of write message
+ * @brief Function called for each byte of write message to TCPC chip
  *
- * @param emul Pointer to TCPCI emulator
- * @param ops Pointer to device operations structure
+ * @param emul Pointer to PS8xxx emulator
  * @param reg First byte of write message
  * @param val Received byte of write message
  * @param bytes Number of bytes already received
  *
- * @return TCPCI_EMUL_CONTINUE to continue with default handler
- * @return TCPCI_EMUL_DONE to immedietly return success
- * @return TCPCI_EMUL_ERROR to immedietly return error
+ * @return 0 on success
+ * @return -EIO on invalid write request
  */
-static enum tcpci_emul_ops_resp ps8xxx_emul_tcpci_write_byte(
-					const struct emul *emul,
-					const struct tcpci_emul_dev_ops *ops,
-					int reg, uint8_t val, int bytes)
+static int ps8xxx_emul_tcpc_write_byte(const struct emul *emul, int reg,
+				       uint8_t val, int bytes)
 {
 	uint16_t prod_id;
+	struct i2c_emul *i2c_emul = emul->bus.i2c;
+
+	LOG_DBG("PS8XXX TCPC 0x%x: write reg 0x%x", i2c_emul->addr, reg);
 
 	tcpci_emul_get_reg(emul, TCPC_REG_PRODUCT_ID, &prod_id);
 
@@ -219,7 +218,7 @@ static enum tcpci_emul_ops_resp ps8xxx_emul_tcpci_write_byte(
 	case PS8XXX_REG_RP_DETECT_CONTROL:
 		/* This register is present only on PS8815 */
 		if (prod_id != PS8815_PRODUCT_ID) {
-			return TCPCI_EMUL_CONTINUE;
+			break;
 		}
 	case PS8XXX_REG_I2C_DEBUGGING_ENABLE:
 	case PS8XXX_REG_MUX_IN_HPD_ASSERTION:
@@ -230,34 +229,35 @@ static enum tcpci_emul_ops_resp ps8xxx_emul_tcpci_write_byte(
 		if (bytes != 1) {
 			LOG_ERR("Writing byte %d to 1 byte register 0x%x",
 				bytes, reg);
-			return TCPCI_EMUL_ERROR;
+			return -EIO;
 		}
 
 		tcpci_emul_set_reg(emul, reg, val);
-		return TCPCI_EMUL_DONE;
+		return 0;
 	default:
-		return TCPCI_EMUL_CONTINUE;
+		break;
 	}
+
+	return tcpci_emul_write_byte(emul, reg, val, bytes);
 }
 
 /**
- * @brief Function called on the end of write message
+ * @brief Function called on the end of write message to TCPC chip
  *
- * @param emul Pointer to TCPCI emulator
- * @param ops Pointer to device operations structure
+ * @param emul Pointer to PS8xxx emulator
  * @param reg Register which is written
  * @param msg_len Length of handled I2C message
  *
- * @return TCPCI_EMUL_CONTINUE to continue with default handler
- * @return TCPCI_EMUL_DONE to immedietly return success
- * @return TCPCI_EMUL_ERROR to immedietly return error
+ * @return 0 on success
+ * @return -EIO on error
  */
-static enum tcpci_emul_ops_resp ps8xxx_emul_tcpci_handle_write(
-					const struct emul *emul,
-					const struct tcpci_emul_dev_ops *ops,
-					int reg, int msg_len)
+static int ps8xxx_emul_tcpc_finish_write(const struct emul *emul, int reg,
+					 int msg_len)
 {
 	uint16_t prod_id;
+	struct i2c_emul *i2c_emul = emul->bus.i2c;
+
+	LOG_DBG("PS8XXX TCPC 0x%x: finish write reg 0x%x", i2c_emul->addr, reg);
 
 	tcpci_emul_get_reg(emul, TCPC_REG_PRODUCT_ID, &prod_id);
 
@@ -265,7 +265,7 @@ static enum tcpci_emul_ops_resp ps8xxx_emul_tcpci_handle_write(
 	case PS8XXX_REG_RP_DETECT_CONTROL:
 		/* This register is present only on PS8815 */
 		if (prod_id != PS8815_PRODUCT_ID) {
-			return TCPCI_EMUL_CONTINUE;
+			break;
 		}
 	case PS8XXX_REG_I2C_DEBUGGING_ENABLE:
 	case PS8XXX_REG_MUX_IN_HPD_ASSERTION:
@@ -273,99 +273,80 @@ static enum tcpci_emul_ops_resp ps8xxx_emul_tcpci_handle_write(
 	case PS8XXX_REG_BIST_CONT_MODE_BYTE1:
 	case PS8XXX_REG_BIST_CONT_MODE_BYTE2:
 	case PS8XXX_REG_BIST_CONT_MODE_CTR:
-		return TCPCI_EMUL_DONE;
+		return 0;
 	default:
-		return TCPCI_EMUL_CONTINUE;
+		break;
 	}
+
+	return tcpci_emul_handle_write(emul, reg, msg_len);
 }
 
 /**
- * @brief Function called on reset
+ * @brief Get currently accessed register, which always equals to selected
+ *        register from TCPC chip.
  *
  * @param emul Pointer to TCPCI emulator
- * @param ops Pointer to device operations structure
+ * @param reg First byte of last write message
+ * @param bytes Number of bytes already handled from current message
+ * @param read If currently handled is read message
+ *
+ * @return Currently accessed register
  */
-static void ps8xxx_emul_tcpci_reset(const struct emul *emul,
-			     struct tcpci_emul_dev_ops *ops)
+static int ps8xxx_emul_tcpc_access_reg(const struct emul *emul, int reg,
+				       int bytes, bool read)
 {
-	tcpci_emul_set_reg(emul, PS8XXX_REG_I2C_DEBUGGING_ENABLE, 0x31);
-	tcpci_emul_set_reg(emul, PS8XXX_REG_MUX_IN_HPD_ASSERTION, 0x00);
-	tcpci_emul_set_reg(emul, PS8XXX_REG_BIST_CONT_MODE_BYTE0, 0xff);
-	tcpci_emul_set_reg(emul, PS8XXX_REG_BIST_CONT_MODE_BYTE1, 0x0f);
-	tcpci_emul_set_reg(emul, PS8XXX_REG_BIST_CONT_MODE_BYTE2, 0x00);
-	tcpci_emul_set_reg(emul, PS8XXX_REG_BIST_CONT_MODE_CTR, 0x00);
+	return reg;
 }
 
-/** TCPCI PS8xxx operations */
-static struct tcpci_emul_dev_ops ps8xxx_emul_ops = {
-	.read_byte = ps8xxx_emul_tcpci_read_byte,
-	.write_byte = ps8xxx_emul_tcpci_write_byte,
-	.handle_write = ps8xxx_emul_tcpci_handle_write,
-	.reset = ps8xxx_emul_tcpci_reset,
-};
-
 /**
- * @brief Get port associated with given "hidden" I2C device
- *
- * @param i2c_emul Pointer to "hidden" I2C device
+ * @brief Function called on reset
  *
- * @return Port associated with given I2C device
+ * @param emul Pointer to PS8xxx emulator
  */
-static enum ps8xxx_emul_port ps8xxx_emul_get_port(struct i2c_emul *i2c_emul)
+static int ps8xxx_emul_tcpc_reset(const struct emul *emul)
 {
-	const struct ps8xxx_emul_cfg *cfg;
-	const struct emul *emul;
-
-	emul = i2c_emul->parent;
-	cfg = emul->cfg;
-
-	if (cfg->p0_cfg.addr == i2c_emul->addr) {
-		return PS8XXX_EMUL_PORT_0;
-	}
-
-	if (cfg->p1_cfg.addr == i2c_emul->addr) {
-		return PS8XXX_EMUL_PORT_1;
-	}
-
-	if (cfg->gpio_cfg.addr != 0 && cfg->gpio_cfg.addr == i2c_emul->addr) {
-		return PS8XXX_EMUL_PORT_GPIO;
-	}
+	tcpci_emul_set_reg(emul, PS8XXX_REG_I2C_DEBUGGING_ENABLE, 0x31);
+	tcpci_emul_set_reg(emul, PS8XXX_REG_MUX_IN_HPD_ASSERTION, 0x00);
+	tcpci_emul_set_reg(emul, PS8XXX_REG_BIST_CONT_MODE_BYTE0, 0xff);
+	tcpci_emul_set_reg(emul, PS8XXX_REG_BIST_CONT_MODE_BYTE1, 0x0f);
+	tcpci_emul_set_reg(emul, PS8XXX_REG_BIST_CONT_MODE_BYTE2, 0x00);
+	tcpci_emul_set_reg(emul, PS8XXX_REG_BIST_CONT_MODE_CTR, 0x00);
 
-	return PS8XXX_EMUL_PORT_INVAL;
+	return tcpci_emul_reset(emul);
 }
 
 /**
  * @brief Function called for each byte of read message
  *
- * @param i2c_emul Pointer to PS8xxx emulator
+ * @param emul Pointer to PS8xxx emulator
  * @param reg First byte of last write message
  * @param val Pointer where byte to read should be stored
- * @param bytes Number of bytes already readded
+ * @param bytes Number of bytes already read
  *
  * @return 0 on success
  * @return -EIO on invalid read request
  */
-static int ps8xxx_emul_read_byte(struct i2c_emul *i2c_emul, int reg,
-				 uint8_t *val, int bytes)
+static int ps8xxx_emul_read_byte_workhorse(const struct emul *emul, int reg,
+					   uint8_t *val, int bytes,
+					   enum ps8xxx_emul_port port)
 {
+	struct tcpc_emul_data *tcpc_data;
 	struct ps8xxx_emul_data *data;
-	enum ps8xxx_emul_port port;
-	const struct emul *emul;
+	struct i2c_emul *i2c_emul = emul->bus.i2c;
 	uint16_t i2c_dbg_reg;
 
-	emul = i2c_emul->parent;
-	data = emul->data;
+	LOG_DBG("PS8XXX 0x%x: read reg 0x%x", i2c_emul->addr, reg);
+
+	tcpc_data = emul->data;
+	data = tcpc_data->chip_data;
 
-	tcpci_emul_get_reg(data->tcpci_emul, PS8XXX_REG_I2C_DEBUGGING_ENABLE,
-			   &i2c_dbg_reg);
+	tcpci_emul_get_reg(emul, PS8XXX_REG_I2C_DEBUGGING_ENABLE, &i2c_dbg_reg);
 	/* There is no need to enable I2C debug on PS8815 */
 	if (data->prod_id != PS8815_PRODUCT_ID && i2c_dbg_reg & 0x1) {
 		LOG_ERR("Accessing hidden i2c address without enabling debug");
 		return -EIO;
 	}
 
-	port = ps8xxx_emul_get_port(i2c_emul);
-
 	/* This is only 2 bytes register so handle it separately */
 	if (data->prod_id == PS8815_PRODUCT_ID && port == PS8XXX_EMUL_PORT_1 &&
 	    reg == PS8815_P1_REG_HW_REVISION) {
@@ -412,10 +393,31 @@ static int ps8xxx_emul_read_byte(struct i2c_emul *i2c_emul, int reg,
 	return -EIO;
 }
 
+static int ps8xxx_emul_p0_read_byte(const struct emul *emul, int reg,
+				    uint8_t *val, int bytes)
+{
+	return ps8xxx_emul_read_byte_workhorse(emul, reg, val, bytes,
+					       PS8XXX_EMUL_PORT_0);
+}
+
+static int ps8xxx_emul_p1_read_byte(const struct emul *emul, int reg,
+				    uint8_t *val, int bytes)
+{
+	return ps8xxx_emul_read_byte_workhorse(emul, reg, val, bytes,
+					       PS8XXX_EMUL_PORT_1);
+}
+
+static int ps8xxx_emul_gpio_read_byte(const struct emul *emul, int reg,
+				      uint8_t *val, int bytes)
+{
+	return ps8xxx_emul_read_byte_workhorse(emul, reg, val, bytes,
+					       PS8XXX_EMUL_PORT_GPIO);
+}
+
 /**
  * @brief Function called for each byte of write message
  *
- * @param i2c_emul Pointer to PS8xxx emulator
+ * @param emul Pointer to PS8xxx emulator
  * @param reg First byte of write message
  * @param val Received byte of write message
  * @param bytes Number of bytes already received
@@ -423,27 +425,27 @@ static int ps8xxx_emul_read_byte(struct i2c_emul *i2c_emul, int reg,
  * @return 0 on success
  * @return -EIO on invalid write request
  */
-static int ps8xxx_emul_write_byte(struct i2c_emul *i2c_emul, int reg,
-				  uint8_t val, int bytes)
+static int ps8xxx_emul_write_byte_workhorse(const struct emul *emul, int reg,
+					    uint8_t val, int bytes,
+					    enum ps8xxx_emul_port port)
 {
 	struct ps8xxx_emul_data *data;
-	enum ps8xxx_emul_port port;
-	const struct emul *emul;
+	struct tcpc_emul_data *tcpc_data;
+	const struct i2c_emul *i2c_emul = emul->bus.i2c;
 	uint16_t i2c_dbg_reg;
 
-	emul = i2c_emul->parent;
-	data = emul->data;
+	LOG_DBG("PS8XXX 0x%x: write reg 0x%x", i2c_emul->addr, reg);
+
+	tcpc_data = emul->data;
+	data = tcpc_data->chip_data;
 
-	tcpci_emul_get_reg(data->tcpci_emul, PS8XXX_REG_I2C_DEBUGGING_ENABLE,
-			   &i2c_dbg_reg);
+	tcpci_emul_get_reg(emul, PS8XXX_REG_I2C_DEBUGGING_ENABLE, &i2c_dbg_reg);
 	/* There is no need to enable I2C debug on PS8815 */
 	if (data->prod_id != PS8815_PRODUCT_ID && i2c_dbg_reg & 0x1) {
 		LOG_ERR("Accessing hidden i2c address without enabling debug");
 		return -EIO;
 	}
 
-	port = ps8xxx_emul_get_port(i2c_emul);
-
 	if (bytes != 1) {
 		LOG_ERR("Writing more than one byte at once");
 		return -EIO;
@@ -473,6 +475,77 @@ static int ps8xxx_emul_write_byte(struct i2c_emul *i2c_emul, int reg,
 	return -EIO;
 }
 
+static int ps8xxx_emul_p0_write_byte(const struct emul *emul, int reg,
+				     uint8_t val, int bytes)
+{
+	return ps8xxx_emul_write_byte_workhorse(emul, reg, val, bytes,
+						PS8XXX_EMUL_PORT_0);
+}
+
+static int ps8xxx_emul_p1_write_byte(const struct emul *emul, int reg,
+				     uint8_t val, int bytes)
+{
+	return ps8xxx_emul_write_byte_workhorse(emul, reg, val, bytes,
+						PS8XXX_EMUL_PORT_1);
+}
+
+static int ps8xxx_emul_gpio_write_byte(const struct emul *emul, int reg,
+				       uint8_t val, int bytes)
+{
+	return ps8xxx_emul_write_byte_workhorse(emul, reg, val, bytes,
+						PS8XXX_EMUL_PORT_GPIO);
+}
+
+static int i2c_ps8xxx_emul_transfer(const struct emul *target,
+				    struct i2c_msg *msgs, int num_msgs,
+				    int addr)
+{
+	struct tcpc_emul_data *tcpc_data = target->data;
+	struct ps8xxx_emul_data *ps8_xxx_data = tcpc_data->chip_data;
+	const struct ps8xxx_emul_cfg *ps8_xxx_cfg = target->cfg;
+	struct i2c_common_emul_data *common_data;
+
+	/* The chip itself */
+	if (addr == tcpc_data->i2c_cfg.addr) {
+		const struct i2c_common_emul_cfg *common_cfg =
+			&tcpc_data->i2c_cfg;
+		common_data = &tcpc_data->tcpci_ctx->common;
+
+		return i2c_common_emul_transfer_workhorse(
+			target, common_data, common_cfg, msgs, num_msgs, addr);
+	}
+	/* Subchips */
+	else if (addr == ps8_xxx_cfg->gpio_cfg.addr) {
+		const struct i2c_common_emul_cfg *common_cfg =
+			&ps8_xxx_cfg->gpio_cfg;
+		common_data = &ps8_xxx_data->gpio_data;
+
+		return i2c_common_emul_transfer_workhorse(
+			target, common_data, common_cfg, msgs, num_msgs, addr);
+	} else if (addr == ps8_xxx_cfg->p0_cfg.addr) {
+		const struct i2c_common_emul_cfg *common_cfg =
+			&ps8_xxx_cfg->p0_cfg;
+		common_data = &ps8_xxx_data->p0_data;
+
+		return i2c_common_emul_transfer_workhorse(
+			target, common_data, common_cfg, msgs, num_msgs, addr);
+	} else if (addr == ps8_xxx_cfg->p1_cfg.addr) {
+		const struct i2c_common_emul_cfg *common_cfg =
+			&ps8_xxx_cfg->p1_cfg;
+		common_data = &ps8_xxx_data->p1_data;
+
+		return i2c_common_emul_transfer_workhorse(
+			target, common_data, common_cfg, msgs, num_msgs, addr);
+	}
+
+	LOG_ERR("Cannot map address %02x", addr);
+	return -EIO;
+}
+
+struct i2c_emul_api i2c_ps8xxx_emul_api = {
+	.transfer = i2c_ps8xxx_emul_transfer,
+};
+
 /**
  * @brief Set up a new PS8xxx emulator
  *
@@ -488,100 +561,104 @@ static int ps8xxx_emul_write_byte(struct i2c_emul *i2c_emul, int reg,
 static int ps8xxx_emul_init(const struct emul *emul,
 			    const struct device *parent)
 {
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct ps8xxx_emul_data *data = tcpc_data->chip_data;
+	struct tcpci_ctx *tcpci_ctx = tcpc_data->tcpci_ctx;
 	const struct ps8xxx_emul_cfg *cfg = emul->cfg;
-	struct ps8xxx_emul_data *data = emul->data;
 	const struct device *i2c_dev;
-	int ret;
+	int ret = 0;
 
-	data->tcpci_emul = emul_get_binding(cfg->tcpci_emul);
 	i2c_dev = parent;
 
-	data->p0_data.emul.api = &i2c_common_emul_api;
+	tcpci_ctx->common.write_byte = ps8xxx_emul_tcpc_write_byte;
+	tcpci_ctx->common.finish_write = ps8xxx_emul_tcpc_finish_write;
+	tcpci_ctx->common.read_byte = ps8xxx_emul_tcpc_read_byte;
+	tcpci_ctx->common.access_reg = ps8xxx_emul_tcpc_access_reg;
+
+	tcpci_emul_i2c_init(emul, i2c_dev);
+
+	data->p0_data.emul.api = &i2c_ps8xxx_emul_api;
 	data->p0_data.emul.addr = cfg->p0_cfg.addr;
-	data->p0_data.emul.parent = emul;
+	data->p0_data.emul.target = emul;
 	data->p0_data.i2c = i2c_dev;
 	data->p0_data.cfg = &cfg->p0_cfg;
 	i2c_common_emul_init(&data->p0_data);
 
-	data->p1_data.emul.api = &i2c_common_emul_api;
+	data->p1_data.emul.api = &i2c_ps8xxx_emul_api;
 	data->p1_data.emul.addr = cfg->p1_cfg.addr;
-	data->p1_data.emul.parent = emul;
+	data->p1_data.emul.target = emul;
 	data->p1_data.i2c = i2c_dev;
 	data->p1_data.cfg = &cfg->p1_cfg;
 	i2c_common_emul_init(&data->p1_data);
 
-	ret = i2c_emul_register(i2c_dev, emul->dev_label, &data->p0_data.emul);
-	ret |= i2c_emul_register(i2c_dev, emul->dev_label, &data->p1_data.emul);
+	/* Have to manually register "hidden" addressed chips under overarching
+	 * ps8xxx
+	 * TODO(b/240564574): Call EMUL_DEFINE for each "hidden" sub-chip.
+	 */
+	ret |= i2c_emul_register(i2c_dev, &data->p0_data.emul);
+	ret |= i2c_emul_register(i2c_dev, &data->p1_data.emul);
 
 	if (cfg->gpio_cfg.addr != 0) {
-		data->gpio_data.emul.api = &i2c_common_emul_api;
+		data->gpio_data.emul.api = &i2c_ps8xxx_emul_api;
 		data->gpio_data.emul.addr = cfg->gpio_cfg.addr;
-		data->gpio_data.emul.parent = emul;
+		data->gpio_data.emul.target = emul;
 		data->gpio_data.i2c = i2c_dev;
 		data->gpio_data.cfg = &cfg->gpio_cfg;
+		ret |= i2c_emul_register(i2c_dev, &data->gpio_data.emul);
 		i2c_common_emul_init(&data->gpio_data);
-		ret |= i2c_emul_register(i2c_dev, emul->dev_label,
-					 &data->gpio_data.emul);
 	}
 
-	tcpci_emul_set_dev_ops(data->tcpci_emul, &ps8xxx_emul_ops);
-	ps8xxx_emul_tcpci_reset(data->tcpci_emul, &ps8xxx_emul_ops);
+	ret |= ps8xxx_emul_tcpc_reset(emul);
 
-	tcpci_emul_set_reg(data->tcpci_emul, TCPC_REG_PRODUCT_ID,
-			   data->prod_id);
+	tcpci_emul_set_reg(emul, TCPC_REG_PRODUCT_ID, data->prod_id);
 	/* FW rev is never 0 in a working device. Set arbitrary FW rev. */
-	tcpci_emul_set_reg(data->tcpci_emul, PS8XXX_REG_FW_REV, 0x31);
+	tcpci_emul_set_reg(emul, PS8XXX_REG_FW_REV, 0x31);
 
 	return ret;
 }
 
-#define PS8XXX_EMUL(n)							\
+#define PS8XXX_EMUL(n)                                                \
 	static struct ps8xxx_emul_data ps8xxx_emul_data_##n = {		\
 		.prod_id = PS8805_PRODUCT_ID,				\
 		.p0_data = {						\
-			.write_byte = ps8xxx_emul_write_byte,		\
-			.read_byte = ps8xxx_emul_read_byte,		\
+			.write_byte = ps8xxx_emul_p0_write_byte,	\
+			.read_byte = ps8xxx_emul_p0_read_byte,		\
 		},							\
 		.p1_data = {						\
-			.write_byte = ps8xxx_emul_write_byte,		\
-			.read_byte = ps8xxx_emul_read_byte,		\
+			.write_byte = ps8xxx_emul_p1_write_byte,	\
+			.read_byte = ps8xxx_emul_p1_read_byte,		\
 		},							\
 		.gpio_data = {						\
-			.write_byte = ps8xxx_emul_write_byte,		\
-			.read_byte = ps8xxx_emul_read_byte,		\
+			.write_byte = ps8xxx_emul_gpio_write_byte,	\
+			.read_byte = ps8xxx_emul_gpio_read_byte,	\
 		},							\
-	};								\
-									\
+	};    \
+                                                                      \
 	static const struct ps8xxx_emul_cfg ps8xxx_emul_cfg_##n = {	\
-		.tcpci_emul = DT_LABEL(DT_INST_PHANDLE(n, tcpci_i2c)),	\
 		.p0_cfg = {						\
-			.i2c_label = DT_INST_BUS_LABEL(n),		\
-			.dev_label = DT_INST_LABEL(n),			\
+			.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)), \
 			.data = &ps8xxx_emul_data_##n.p0_data,		\
 			.addr = DT_INST_PROP(n, p0_i2c_addr),		\
 		},							\
 		.p1_cfg = {						\
-			.i2c_label = DT_INST_BUS_LABEL(n),		\
-			.dev_label = DT_INST_LABEL(n),			\
+			.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)), \
 			.data = &ps8xxx_emul_data_##n.p1_data,		\
 			.addr = DT_INST_PROP(n, p1_i2c_addr),		\
 		},							\
 		.gpio_cfg = {						\
-			.i2c_label = DT_INST_BUS_LABEL(n),		\
-			.dev_label = DT_INST_LABEL(n),			\
+			.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)), \
 			.data = &ps8xxx_emul_data_##n.gpio_data,	\
 			.addr = DT_INST_PROP(n, gpio_i2c_addr),		\
 		},							\
-	};								\
-	EMUL_DEFINE(ps8xxx_emul_init, DT_DRV_INST(n),			\
-		    &ps8xxx_emul_cfg_##n, &ps8xxx_emul_data_##n)
+	}; \
+	TCPCI_EMUL_DEFINE(n, ps8xxx_emul_init, &ps8xxx_emul_cfg_##n,  \
+			  &ps8xxx_emul_data_##n, &i2c_ps8xxx_emul_api)
 
 DT_INST_FOREACH_STATUS_OKAY(PS8XXX_EMUL)
 
-#ifdef CONFIG_ZMAKE_NEW_API
-
+#ifdef CONFIG_ZTEST_NEW_API
 #define PS8XXX_EMUL_RESET_RULE_BEFORE(n) \
-	ps8xxx_emul_tcpci_reset(&ps8xxx_emul_data_##n, &ps8xxx_emul_ops);
+	ps8xxx_emul_tcpc_reset(EMUL_DT_GET(DT_DRV_INST(n)));
 static void ps8xxx_emul_reset_rule_before(const struct ztest_unit_test *test,
 					  void *data)
 {
@@ -589,5 +666,7 @@ static void ps8xxx_emul_reset_rule_before(const struct ztest_unit_test *test,
 	ARG_UNUSED(data);
 	DT_INST_FOREACH_STATUS_OKAY(PS8XXX_EMUL_RESET_RULE_BEFORE);
 }
-ZTEST_RULE(ps8xxx_emul_reset, ps8xxx_emul_reset_rule_before, NULL);
-#endif /* CONFIG_ZMAKE_NEW_API */
+ZTEST_RULE(PS8XXX_emul_reset, ps8xxx_emul_reset_rule_before, NULL);
+#endif /* CONFIG_ZTEST_NEW_API */
+
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
diff --git a/zephyr/emul/tcpc/emul_tcpci.c b/zephyr/emul/tcpc/emul_tcpci.c
index ac547be3c3..e19f7a2726 100644
--- a/zephyr/emul/tcpc/emul_tcpci.c
+++ b/zephyr/emul/tcpc/emul_tcpci.c
@@ -1,10 +1,8 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#define DT_DRV_COMPAT cros_tcpci_emul
-
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(tcpci_emul, CONFIG_TCPCI_EMUL_LOG_LEVEL);
 
@@ -13,59 +11,14 @@ LOG_MODULE_REGISTER(tcpci_emul, CONFIG_TCPCI_EMUL_LOG_LEVEL);
 #include <zephyr/drivers/i2c.h>
 #include <zephyr/drivers/i2c_emul.h>
 #include <zephyr/drivers/gpio/gpio_emul.h>
-#include <ztest.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/ztest.h>
 
 #include "tcpm/tcpci.h"
 
 #include "emul/emul_common_i2c.h"
 #include "emul/tcpc/emul_tcpci.h"
 
-#define TCPCI_DATA_FROM_I2C_EMUL(_emul)					     \
-	CONTAINER_OF(CONTAINER_OF(_emul, struct i2c_common_emul_data, emul), \
-		     struct tcpci_emul_data, common)
-
-/**
- * Number of emulated register. This include vendor registers defined in TCPCI
- * specification
- */
-#define TCPCI_EMUL_REG_COUNT		0x100
-
-
-/** Run-time data used by the emulator */
-struct tcpci_emul_data {
-	/** Common I2C data */
-	struct i2c_common_emul_data common;
-
-	/** Current state of all emulated TCPCI registers */
-	uint8_t reg[TCPCI_EMUL_REG_COUNT];
-
-	/** Structures representing TX and RX buffers */
-	struct tcpci_emul_msg *rx_msg;
-	struct tcpci_emul_msg *tx_msg;
-
-	/** Data that should be written to register (except TX_BUFFER) */
-	uint16_t write_data;
-
-	/** Return error when trying to write to RO register */
-	bool error_on_ro_write;
-	/** Return error when trying to write 1 to reserved bit */
-	bool error_on_rsvd_write;
-
-	/** User function called when alert line could change */
-	tcpci_emul_alert_state_func alert_callback;
-	/** Data passed to alert_callback */
-	void *alert_callback_data;
-
-	/** Callbacks for specific TCPCI device emulator */
-	struct tcpci_emul_dev_ops *dev_ops;
-	/** Callbacks for TCPCI partner */
-	const struct tcpci_emul_partner_ops *partner;
-
-	/** Reference to Alert# GPIO emulator. */
-	const struct device *alert_gpio_port;
-	gpio_pin_t alert_gpio_pin;
-};
-
 /**
  * @brief Returns number of bytes in specific register
  *
@@ -75,7 +28,6 @@ struct tcpci_emul_data {
  */
 static int tcpci_emul_reg_bytes(int reg)
 {
-
 	switch (reg) {
 	case TCPC_REG_VENDOR_ID:
 	case TCPC_REG_PRODUCT_ID:
@@ -101,10 +53,58 @@ static int tcpci_emul_reg_bytes(int reg)
 	return 1;
 }
 
+/**
+ * @brief Get value of given register of TCPCI
+ *
+ * @param ctx Pointer to TCPCI context
+ * @param reg Register address
+ * @param val Pointer where value should be stored
+ *
+ * @return 0 on success
+ * @return -EINVAL when register is out of range defined in TCPCI specification
+ *                 or val is NULL
+ */
+static int get_reg(const struct tcpci_ctx *ctx, int reg, uint16_t *val)
+{
+	int byte;
+
+	if (reg < 0 || reg > TCPCI_EMUL_REG_COUNT || val == NULL) {
+		return -EINVAL;
+	}
+
+	*val = 0;
+
+	byte = tcpci_emul_reg_bytes(reg);
+	if (byte == 2) {
+		*val = sys_get_le16(&ctx->reg[reg]);
+	} else {
+		*val = ctx->reg[reg];
+	}
+
+	return 0;
+}
+
 /** Check description in emul_tcpci.h */
-int tcpci_emul_set_reg(const struct emul *emul, int reg, uint16_t val)
+int tcpci_emul_get_reg(const struct emul *emul, int reg, uint16_t *val)
+{
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx;
+
+	return get_reg(ctx, reg, val);
+}
+
+/**
+ * @brief Set value of given register of TCPCI
+ *
+ * @param ctx Pointer to TCPCI context
+ * @param reg Register address which value will be changed
+ * @param val New value of the register
+ *
+ * @return 0 on success
+ * @return -EINVAL when register is out of range defined in TCPCI specification
+ */
+static int set_reg(struct tcpci_ctx *ctx, int reg, uint16_t val)
 {
-	struct tcpci_emul_data *data = emul->data;
 	uint16_t update_alert = 0;
 	uint16_t alert;
 	int byte;
@@ -130,82 +130,70 @@ int tcpci_emul_set_reg(const struct emul *emul, int reg, uint16_t val)
 	}
 
 	if (update_alert != 0) {
-		tcpci_emul_get_reg(emul, TCPC_REG_ALERT, &alert);
-		tcpci_emul_set_reg(emul, TCPC_REG_ALERT, alert | update_alert);
+		get_reg(ctx, TCPC_REG_ALERT, &alert);
+		set_reg(ctx, TCPC_REG_ALERT, alert | update_alert);
 	}
 
-	for (byte = tcpci_emul_reg_bytes(reg); byte > 0; byte--) {
-		data->reg[reg] = val & 0xff;
-		val >>= 8;
-		reg++;
+	byte = tcpci_emul_reg_bytes(reg);
+	if (byte == 2) {
+		sys_put_le16(val, &ctx->reg[reg]);
+	} else {
+		ctx->reg[reg] = val;
 	}
 
 	return 0;
 }
 
 /** Check description in emul_tcpci.h */
-int tcpci_emul_get_reg(const struct emul *emul, int reg, uint16_t *val)
+int tcpci_emul_set_reg(const struct emul *emul, int reg, uint16_t val)
 {
-	struct tcpci_emul_data *data = emul->data;
-	int byte;
-
-	if (reg < 0 || reg > TCPCI_EMUL_REG_COUNT || val == NULL) {
-		return -EINVAL;
-	}
-
-	*val = 0;
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx;
 
-	byte = tcpci_emul_reg_bytes(reg);
-	for (byte -= 1; byte >= 0; byte--) {
-		*val <<= 8;
-		*val |= data->reg[reg + byte];
-	}
-
-	return 0;
+	return set_reg(ctx, reg, val);
 }
 
 /**
  * @brief Check if alert line should be active based on alert registers and
  *        masks
  *
- * @param emul Pointer to TCPCI emulator
+ * @param ctx Pointer to TCPCI context
  *
  * @return State of alert line
  */
-static bool tcpci_emul_check_int(const struct emul *emul)
+static bool tcpci_emul_check_int(const struct tcpci_ctx *ctx)
 {
-	struct tcpci_emul_data *data = emul->data;
 	uint16_t alert_mask;
 	uint16_t alert;
 
-	tcpci_emul_get_reg(emul, TCPC_REG_ALERT, &alert);
-	tcpci_emul_get_reg(emul, TCPC_REG_ALERT_MASK, &alert_mask);
+	get_reg(ctx, TCPC_REG_ALERT, &alert);
+	get_reg(ctx, TCPC_REG_ALERT_MASK, &alert_mask);
 
 	/*
 	 * For nested interrupts alert group bit and alert register bit has to
 	 * be unmasked
 	 */
 	if (alert & alert_mask & TCPC_REG_ALERT_ALERT_EXT &&
-	    data->reg[TCPC_REG_ALERT_EXT] &
-	    data->reg[TCPC_REG_ALERT_EXTENDED_MASK]) {
+	    ctx->reg[TCPC_REG_ALERT_EXT] &
+		    ctx->reg[TCPC_REG_ALERT_EXTENDED_MASK]) {
 		return true;
 	}
 
 	if (alert & alert_mask & TCPC_REG_ALERT_EXT_STATUS &&
-	    data->reg[TCPC_REG_EXT_STATUS] &
-	    data->reg[TCPC_REG_EXT_STATUS_MASK]) {
+	    ctx->reg[TCPC_REG_EXT_STATUS] &
+		    ctx->reg[TCPC_REG_EXT_STATUS_MASK]) {
 		return true;
 	}
 
 	if (alert & alert_mask & TCPC_REG_ALERT_FAULT &&
-	    data->reg[TCPC_REG_FAULT_STATUS] &
-	    data->reg[TCPC_REG_FAULT_STATUS_MASK]) {
+	    ctx->reg[TCPC_REG_FAULT_STATUS] &
+		    ctx->reg[TCPC_REG_FAULT_STATUS_MASK]) {
 		return true;
 	}
 
 	if (alert & alert_mask & TCPC_REG_ALERT_POWER_STATUS &&
-	    data->reg[TCPC_REG_POWER_STATUS] &
-	    data->reg[TCPC_REG_POWER_STATUS_MASK]) {
+	    ctx->reg[TCPC_REG_POWER_STATUS] &
+		    ctx->reg[TCPC_REG_POWER_STATUS_MASK]) {
 		return true;
 	}
 
@@ -222,34 +210,34 @@ static bool tcpci_emul_check_int(const struct emul *emul)
 /**
  * @brief If alert callback is provided, call it with current alert line state
  *
- * @param emul Pointer to TCPCI emulator
+ * @param emul Pointer to TCPC emulator
  *
  * @return 0 for success, or non-0 for errors.
  */
 static int tcpci_emul_alert_changed(const struct emul *emul)
 {
-	struct tcpci_emul_data *data = emul->data;
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx;
 	int rc;
-	bool alert_is_active = tcpci_emul_check_int(emul);
+	bool alert_is_active = tcpci_emul_check_int(ctx);
 
 	/** Trigger GPIO. */
-	if (data->alert_gpio_port != NULL) {
+	if (ctx->alert_gpio_port != NULL) {
 		/* Triggers on edge falling, so set to 0 when there is an alert.
 		 */
-		rc = gpio_emul_input_set(data->alert_gpio_port,
-					 data->alert_gpio_pin,
+		rc = gpio_emul_input_set(ctx->alert_gpio_port,
+					 ctx->alert_gpio_pin,
 					 alert_is_active ? 0 : 1);
 		if (rc != 0)
 			return rc;
 	}
 
 	/* Nothing to do */
-	if (data->alert_callback == NULL) {
+	if (ctx->alert_callback == NULL) {
 		return 0;
 	}
 
-	data->alert_callback(emul, alert_is_active,
-			     data->alert_callback_data);
+	ctx->alert_callback(emul, alert_is_active, ctx->alert_callback_data);
 	return 0;
 }
 
@@ -257,31 +245,32 @@ static int tcpci_emul_alert_changed(const struct emul *emul)
  * @brief Load next rx message and inform partner which message was consumed
  *        by TCPC
  *
- * @param emul Pointer to TCPCI emulator
+ * @param emul Pointer to TCPC emulator
  *
  * @return 0 when there is no new message to load
  * @return 1 when new rx message is loaded
  */
 static int tcpci_emul_get_next_rx_msg(const struct emul *emul)
 {
-	struct tcpci_emul_data *data = emul->data;
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx;
 	struct tcpci_emul_msg *consumed_msg;
 
-	if (data->rx_msg == NULL) {
+	if (ctx->rx_msg == NULL) {
 		return 0;
 	}
 
-	consumed_msg = data->rx_msg;
-	data->rx_msg = consumed_msg->next;
+	consumed_msg = ctx->rx_msg;
+	ctx->rx_msg = consumed_msg->next;
 
 	/* Inform partner */
-	if (data->partner && data->partner->rx_consumed) {
-		data->partner->rx_consumed(emul, data->partner, consumed_msg);
+	if (ctx->partner && ctx->partner->rx_consumed) {
+		ctx->partner->rx_consumed(emul, ctx->partner, consumed_msg);
 	}
 
 	/* Prepare new loaded message */
-	if (data->rx_msg) {
-		data->rx_msg->idx = 0;
+	if (ctx->rx_msg) {
+		ctx->rx_msg->idx = 0;
 
 		return 1;
 	}
@@ -293,17 +282,15 @@ static int tcpci_emul_get_next_rx_msg(const struct emul *emul)
  * @brief Reset mask registers that are reset upon receiving or transmitting
  *        Hard Reset message.
  *
- * @param emul Pointer to TCPCI emulator
+ * @param ctx Pointer to TCPCI context
  */
-static void tcpci_emul_reset_mask_regs(const struct emul *emul)
+static void tcpci_emul_reset_mask_regs(struct tcpci_ctx *ctx)
 {
-	struct tcpci_emul_data *data = emul->data;
-
-	data->reg[TCPC_REG_ALERT_MASK]				= 0xff;
-	data->reg[TCPC_REG_ALERT_MASK + 1]			= 0x7f;
-	data->reg[TCPC_REG_POWER_STATUS_MASK]			= 0xff;
-	data->reg[TCPC_REG_EXT_STATUS_MASK]			= 0x01;
-	data->reg[TCPC_REG_ALERT_EXTENDED_MASK]			= 0x07;
+	ctx->reg[TCPC_REG_ALERT_MASK] = 0xff;
+	ctx->reg[TCPC_REG_ALERT_MASK + 1] = 0x7f;
+	ctx->reg[TCPC_REG_POWER_STATUS_MASK] = 0xff;
+	ctx->reg[TCPC_REG_EXT_STATUS_MASK] = 0x01;
+	ctx->reg[TCPC_REG_ALERT_EXTENDED_MASK] = 0x07;
 }
 
 /**
@@ -311,11 +298,14 @@ static void tcpci_emul_reset_mask_regs(const struct emul *emul)
  *        delivery (clear RECEIVE_DETECT register and clear already received
  *        messages in buffer)
  *
- * @param emul Pointer to TCPCI emulator
+ * @param emul Pointer to TCPC emulator
  */
 static void tcpci_emul_disable_pd_msg_delivery(const struct emul *emul)
 {
-	tcpci_emul_set_reg(emul, TCPC_REG_RX_DETECT, 0);
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx;
+
+	set_reg(ctx, TCPC_REG_RX_DETECT, 0);
 	/* Clear received messages */
 	while (tcpci_emul_get_next_rx_msg(emul))
 		;
@@ -325,7 +315,8 @@ static void tcpci_emul_disable_pd_msg_delivery(const struct emul *emul)
 int tcpci_emul_add_rx_msg(const struct emul *emul,
 			  struct tcpci_emul_msg *rx_msg, bool alert)
 {
-	struct tcpci_emul_data *data = emul->data;
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx;
 	uint16_t rx_detect_mask;
 	uint16_t rx_detect;
 	uint16_t dev_cap_2;
@@ -333,13 +324,13 @@ int tcpci_emul_add_rx_msg(const struct emul *emul,
 	int rc;
 
 	/* Acquire lock to prevent race conditions with TCPM accessing I2C */
-	rc = i2c_common_emul_lock_data(&data->common.emul, K_FOREVER);
+	rc = i2c_common_emul_lock_data(&ctx->common, K_FOREVER);
 	if (rc != 0) {
 		LOG_ERR("Failed to acquire TCPCI lock");
 		return rc;
 	}
 
-	switch (rx_msg->type) {
+	switch (rx_msg->sop_type) {
 	case TCPCI_MSG_SOP:
 		rx_detect_mask = TCPC_REG_RX_DETECT_SOP;
 		break;
@@ -362,65 +353,66 @@ int tcpci_emul_add_rx_msg(const struct emul *emul,
 		rx_detect_mask = TCPC_REG_RX_DETECT_CABLE_RST;
 		break;
 	default:
-		i2c_common_emul_unlock_data(&data->common.emul);
+		i2c_common_emul_unlock_data(&ctx->common);
 		return -EINVAL;
 	}
 
-	tcpci_emul_get_reg(emul, TCPC_REG_RX_DETECT, &rx_detect);
+	get_reg(ctx, TCPC_REG_RX_DETECT, &rx_detect);
 	if (!(rx_detect & rx_detect_mask)) {
 		/*
 		 * TCPCI will not respond with GoodCRC, so from partner emulator
 		 * point of view it failed to send message
 		 */
-		i2c_common_emul_unlock_data(&data->common.emul);
+		i2c_common_emul_unlock_data(&ctx->common);
 		return TCPCI_EMUL_TX_FAILED;
 	}
 
-	tcpci_emul_get_reg(emul, TCPC_REG_ALERT, &alert_reg);
+	get_reg(ctx, TCPC_REG_ALERT, &alert_reg);
 
 	/* Handle HardReset */
-	if (rx_msg->type == TCPCI_MSG_TX_HARD_RESET) {
+	if (rx_msg->sop_type == TCPCI_MSG_TX_HARD_RESET) {
 		tcpci_emul_disable_pd_msg_delivery(emul);
-		tcpci_emul_reset_mask_regs(emul);
+		tcpci_emul_reset_mask_regs(ctx);
 
 		alert_reg |= TCPC_REG_ALERT_RX_HARD_RST;
-		tcpci_emul_set_reg(emul, TCPC_REG_ALERT, alert_reg);
+		set_reg(ctx, TCPC_REG_ALERT, alert_reg);
 		rc = tcpci_emul_alert_changed(emul);
 
-		i2c_common_emul_unlock_data(&data->common.emul);
+		i2c_common_emul_unlock_data(&ctx->common);
 		return rc;
 	}
 
 	/* Handle CableReset */
-	if (rx_msg->type == TCPCI_MSG_CABLE_RESET) {
+	if (rx_msg->sop_type == TCPCI_MSG_CABLE_RESET) {
 		tcpci_emul_disable_pd_msg_delivery(emul);
 		/* Rest of CableReset handling is the same as SOP* message */
 	}
 
-	if (data->rx_msg == NULL) {
-		tcpci_emul_get_reg(emul, TCPC_REG_DEV_CAP_2, &dev_cap_2);
+	if (ctx->rx_msg == NULL) {
+		get_reg(ctx, TCPC_REG_DEV_CAP_2, &dev_cap_2);
 		if ((!(dev_cap_2 & TCPC_REG_DEV_CAP_2_LONG_MSG) &&
-		       rx_msg->cnt > 31) || rx_msg->cnt > 265) {
+		     rx_msg->cnt > 31) ||
+		    rx_msg->cnt > 265) {
 			LOG_ERR("Too long first message (%d)", rx_msg->cnt);
-			i2c_common_emul_unlock_data(&data->common.emul);
+			i2c_common_emul_unlock_data(&ctx->common);
 			return -EINVAL;
 		}
 
-		data->rx_msg = rx_msg;
-	} else if (data->rx_msg->next == NULL) {
+		ctx->rx_msg = rx_msg;
+	} else if (ctx->rx_msg->next == NULL) {
 		if (rx_msg->cnt > 31) {
 			LOG_ERR("Too long second message (%d)", rx_msg->cnt);
-			i2c_common_emul_unlock_data(&data->common.emul);
+			i2c_common_emul_unlock_data(&ctx->common);
 			return -EINVAL;
 		}
 
-		data->rx_msg->next = rx_msg;
+		ctx->rx_msg->next = rx_msg;
 		if (alert) {
 			alert_reg |= TCPC_REG_ALERT_RX_BUF_OVF;
 		}
 	} else {
 		LOG_ERR("Cannot setup third message");
-		i2c_common_emul_unlock_data(&data->common.emul);
+		i2c_common_emul_unlock_data(&ctx->common);
 		return -EINVAL;
 	}
 
@@ -430,11 +422,11 @@ int tcpci_emul_add_rx_msg(const struct emul *emul,
 		}
 
 		alert_reg |= TCPC_REG_ALERT_RX_STATUS;
-		tcpci_emul_set_reg(emul, TCPC_REG_ALERT, alert_reg);
+		set_reg(ctx, TCPC_REG_ALERT, alert_reg);
 
 		rc = tcpci_emul_alert_changed(emul);
 		if (rc != 0) {
-			i2c_common_emul_unlock_data(&data->common.emul);
+			i2c_common_emul_unlock_data(&ctx->common);
 			return rc;
 		}
 	}
@@ -442,16 +434,17 @@ int tcpci_emul_add_rx_msg(const struct emul *emul,
 	rx_msg->next = NULL;
 	rx_msg->idx = 0;
 
-	i2c_common_emul_unlock_data(&data->common.emul);
+	i2c_common_emul_unlock_data(&ctx->common);
 	return TCPCI_EMUL_TX_SUCCESS;
 }
 
 /** Check description in emul_tcpci.h */
 struct tcpci_emul_msg *tcpci_emul_get_tx_msg(const struct emul *emul)
 {
-	struct tcpci_emul_data *data = emul->data;
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx;
 
-	return data->tx_msg;
+	return ctx->tx_msg;
 }
 
 /** Check description in emul_tcpci.h */
@@ -461,43 +454,36 @@ void tcpci_emul_set_rev(const struct emul *emul, enum tcpci_emul_rev rev)
 	case TCPCI_EMUL_REV1_0_VER1_0:
 		tcpci_emul_set_reg(emul, TCPC_REG_PD_INT_REV,
 				   (TCPC_REG_PD_INT_REV_REV_1_0 << 8) |
-				    TCPC_REG_PD_INT_REV_VER_1_0);
+					   TCPC_REG_PD_INT_REV_VER_1_0);
 		return;
 	case TCPCI_EMUL_REV2_0_VER1_1:
 		tcpci_emul_set_reg(emul, TCPC_REG_PD_INT_REV,
 				   (TCPC_REG_PD_INT_REV_REV_2_0 << 8) |
-				    TCPC_REG_PD_INT_REV_VER_1_1);
+					   TCPC_REG_PD_INT_REV_VER_1_1);
 		return;
 	}
 }
 
 /** Check description in emul_tcpci.h */
-void tcpci_emul_set_dev_ops(const struct emul *emul,
-			    struct tcpci_emul_dev_ops *dev_ops)
-{
-	struct tcpci_emul_data *data = emul->data;
-
-	data->dev_ops = dev_ops;
-}
-
-/** Check description in emul_tcpci.h */
 void tcpci_emul_set_alert_callback(const struct emul *emul,
 				   tcpci_emul_alert_state_func alert_callback,
 				   void *alert_callback_data)
 {
-	struct tcpci_emul_data *data = emul->data;
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx;
 
-	data->alert_callback = alert_callback;
-	data->alert_callback_data = alert_callback_data;
+	ctx->alert_callback = alert_callback;
+	ctx->alert_callback_data = alert_callback_data;
 }
 
 /** Check description in emul_tcpci.h */
 void tcpci_emul_set_partner_ops(const struct emul *emul,
 				const struct tcpci_emul_partner_ops *partner)
 {
-	struct tcpci_emul_data *data = emul->data;
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx;
 
-	data->partner = partner;
+	ctx->partner = partner;
 }
 
 /**
@@ -508,9 +494,9 @@ void tcpci_emul_set_partner_ops(const struct emul *emul,
  *
  * @return Voltage visible at CC resistor side
  */
-static enum tcpc_cc_voltage_status tcpci_emul_detected_volt_for_res(
-		enum tcpc_cc_pull res,
-		enum tcpc_cc_voltage_status volt)
+static enum tcpc_cc_voltage_status
+tcpci_emul_detected_volt_for_res(enum tcpc_cc_pull res,
+				 enum tcpc_cc_voltage_status volt)
 {
 	switch (res) {
 	case TYPEC_CC_RD:
@@ -545,6 +531,8 @@ int tcpci_emul_connect_partner(const struct emul *emul,
 			       enum tcpc_cc_voltage_status partner_cc2,
 			       enum tcpc_cc_polarity polarity)
 {
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx;
 	uint16_t cc_status, alert, role_ctrl, power_status;
 	enum tcpc_cc_voltage_status cc1_v, cc2_v;
 	enum tcpc_cc_pull cc1_r, cc2_r;
@@ -557,7 +545,7 @@ int tcpci_emul_connect_partner(const struct emul *emul,
 		cc2_v = partner_cc1;
 	}
 
-	tcpci_emul_get_reg(emul, TCPC_REG_CC_STATUS, &cc_status);
+	get_reg(ctx, TCPC_REG_CC_STATUS, &cc_status);
 	if (TCPC_REG_CC_STATUS_LOOK4CONNECTION(cc_status)) {
 		/* Change resistors values in case of DRP toggling */
 		if (partner_power_role == PD_ROLE_SOURCE) {
@@ -571,7 +559,7 @@ int tcpci_emul_connect_partner(const struct emul *emul,
 		}
 	} else {
 		/* Use role control resistors values otherwise */
-		tcpci_emul_get_reg(emul, TCPC_REG_ROLE_CTRL, &role_ctrl);
+		get_reg(ctx, TCPC_REG_ROLE_CTRL, &role_ctrl);
 		cc1_r = TCPC_REG_ROLE_CTRL_CC1(role_ctrl);
 		cc2_r = TCPC_REG_ROLE_CTRL_CC2(role_ctrl);
 	}
@@ -581,23 +569,20 @@ int tcpci_emul_connect_partner(const struct emul *emul,
 
 	/* If CC status is TYPEC_CC_VOLT_RP_*, then BIT(2) is ignored */
 	cc_status = TCPC_REG_CC_STATUS_SET(
-				partner_power_role == PD_ROLE_SOURCE ? 1 : 0,
-				cc2_v, cc1_v);
-	tcpci_emul_set_reg(emul, TCPC_REG_CC_STATUS, cc_status);
-	tcpci_emul_get_reg(emul, TCPC_REG_ALERT, &alert);
-	tcpci_emul_set_reg(emul, TCPC_REG_ALERT,
-			   alert | TCPC_REG_ALERT_CC_STATUS);
+		partner_power_role == PD_ROLE_SOURCE ? 1 : 0, cc2_v, cc1_v);
+	set_reg(ctx, TCPC_REG_CC_STATUS, cc_status);
+	get_reg(ctx, TCPC_REG_ALERT, &alert);
+	set_reg(ctx, TCPC_REG_ALERT, alert | TCPC_REG_ALERT_CC_STATUS);
 
 	if (partner_power_role == PD_ROLE_SOURCE) {
-		tcpci_emul_get_reg(emul, TCPC_REG_POWER_STATUS, &power_status);
+		get_reg(ctx, TCPC_REG_POWER_STATUS, &power_status);
 		if (power_status & TCPC_REG_POWER_STATUS_VBUS_DET) {
 			/*
 			 * Set TCPCI emulator VBUS to present (connected,
 			 * above 4V) only if VBUS detection is enabled
 			 */
-			tcpci_emul_set_reg(emul, TCPC_REG_POWER_STATUS,
-					   TCPC_REG_POWER_STATUS_VBUS_PRES |
-					   power_status);
+			set_reg(ctx, TCPC_REG_POWER_STATUS,
+				TCPC_REG_POWER_STATUS_VBUS_PRES | power_status);
 		}
 	}
 
@@ -609,32 +594,33 @@ int tcpci_emul_connect_partner(const struct emul *emul,
 /** Check description in emul_tcpci.h */
 int tcpci_emul_disconnect_partner(const struct emul *emul)
 {
-	struct tcpci_emul_data *data = emul->data;
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx;
 	uint16_t power_status;
 	uint16_t val;
 	uint16_t term;
 	int rc;
 
 	tcpci_emul_disable_pd_msg_delivery(emul);
-	if (data->partner && data->partner->disconnect) {
-		data->partner->disconnect(emul, data->partner);
+	if (ctx->partner && ctx->partner->disconnect) {
+		ctx->partner->disconnect(emul, ctx->partner);
 	}
-	data->partner = NULL;
+	ctx->partner = NULL;
 
 	/* Set both CC lines to open to indicate disconnect. */
-	rc = tcpci_emul_get_reg(emul, TCPC_REG_CC_STATUS, &val);
+	rc = get_reg(ctx, TCPC_REG_CC_STATUS, &val);
 	if (rc != 0)
 		return rc;
 
 	term = TCPC_REG_CC_STATUS_TERM(val);
 
-	rc = tcpci_emul_set_reg(emul, TCPC_REG_CC_STATUS,
-				TCPC_REG_CC_STATUS_SET(term, TYPEC_CC_VOLT_OPEN,
-						       TYPEC_CC_VOLT_OPEN));
+	rc = set_reg(ctx, TCPC_REG_CC_STATUS,
+		     TCPC_REG_CC_STATUS_SET(term, TYPEC_CC_VOLT_OPEN,
+					    TYPEC_CC_VOLT_OPEN));
 	if (rc != 0)
 		return rc;
 
-	data->reg[TCPC_REG_ALERT] |= TCPC_REG_ALERT_CC_STATUS;
+	ctx->reg[TCPC_REG_ALERT] |= TCPC_REG_ALERT_CC_STATUS;
 	rc = tcpci_emul_alert_changed(emul);
 	if (rc != 0)
 		return rc;
@@ -644,10 +630,10 @@ int tcpci_emul_disconnect_partner(const struct emul *emul)
 	 */
 
 	/* Clear VBUS present in case if source partner is disconnected */
-	tcpci_emul_get_reg(emul, TCPC_REG_POWER_STATUS, &power_status);
+	get_reg(ctx, TCPC_REG_POWER_STATUS, &power_status);
 	if (power_status & TCPC_REG_POWER_STATUS_VBUS_PRES) {
 		power_status &= ~TCPC_REG_POWER_STATUS_VBUS_PRES;
-		tcpci_emul_set_reg(emul, TCPC_REG_POWER_STATUS, power_status);
+		set_reg(ctx, TCPC_REG_POWER_STATUS, power_status);
 	}
 
 	return 0;
@@ -657,6 +643,8 @@ int tcpci_emul_disconnect_partner(const struct emul *emul)
 void tcpci_emul_partner_msg_status(const struct emul *emul,
 				   enum tcpci_emul_tx_status status)
 {
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx;
 	uint16_t alert;
 	uint16_t tx_status_alert;
 
@@ -679,110 +667,108 @@ void tcpci_emul_partner_msg_status(const struct emul *emul,
 		return;
 	}
 
-	tcpci_emul_get_reg(emul, TCPC_REG_ALERT, &alert);
-	tcpci_emul_set_reg(emul, TCPC_REG_ALERT, alert | tx_status_alert);
+	get_reg(ctx, TCPC_REG_ALERT, &alert);
+	set_reg(ctx, TCPC_REG_ALERT, alert | tx_status_alert);
 	tcpci_emul_alert_changed(emul);
 }
 
 /** Mask reserved bits in each register of TCPCI */
 static const uint8_t tcpci_emul_rsvd_mask[] = {
-	[TCPC_REG_VENDOR_ID]				= 0x00,
-	[TCPC_REG_VENDOR_ID + 1]			= 0x00,
-	[TCPC_REG_PRODUCT_ID]				= 0x00,
-	[TCPC_REG_PRODUCT_ID + 1]			= 0x00,
-	[TCPC_REG_BCD_DEV]				= 0x00,
-	[TCPC_REG_BCD_DEV + 1]				= 0xff,
-	[TCPC_REG_TC_REV]				= 0x00,
-	[TCPC_REG_TC_REV + 1]				= 0x00,
-	[TCPC_REG_PD_REV]				= 0x00,
-	[TCPC_REG_PD_REV + 1]				= 0x00,
-	[TCPC_REG_PD_INT_REV]				= 0x00,
-	[TCPC_REG_PD_INT_REV + 1]			= 0x00,
-	[0x0c ... 0x0f]					= 0xff, /* Reserved */
-	[TCPC_REG_ALERT]				= 0x00,
-	[TCPC_REG_ALERT + 1]				= 0x00,
-	[TCPC_REG_ALERT_MASK]				= 0x00,
-	[TCPC_REG_ALERT_MASK + 1]			= 0x00,
-	[TCPC_REG_POWER_STATUS_MASK]			= 0x00,
-	[TCPC_REG_FAULT_STATUS_MASK]			= 0x00,
-	[TCPC_REG_EXT_STATUS_MASK]			= 0xfe,
-	[TCPC_REG_ALERT_EXTENDED_MASK]			= 0xf8,
-	[TCPC_REG_CONFIG_STD_OUTPUT]			= 0x00,
-	[TCPC_REG_TCPC_CTRL]				= 0x00,
-	[TCPC_REG_ROLE_CTRL]				= 0x80,
-	[TCPC_REG_FAULT_CTRL]				= 0x80,
-	[TCPC_REG_POWER_CTRL]				= 0x00,
-	[TCPC_REG_CC_STATUS]				= 0xc0,
-	[TCPC_REG_POWER_STATUS]				= 0x00,
-	[TCPC_REG_FAULT_STATUS]				= 0x00,
-	[TCPC_REG_EXT_STATUS]				= 0xfe,
-	[TCPC_REG_ALERT_EXT]				= 0xf8,
-	[0x22]						= 0xff, /* Reserved */
-	[TCPC_REG_COMMAND]				= 0x00,
-	[TCPC_REG_DEV_CAP_1]				= 0x00,
-	[TCPC_REG_DEV_CAP_1 + 1]			= 0x00,
-	[TCPC_REG_DEV_CAP_2]				= 0x80,
-	[TCPC_REG_DEV_CAP_2 + 1]			= 0x00,
-	[TCPC_REG_STD_INPUT_CAP]			= 0xe0,
-	[TCPC_REG_STD_OUTPUT_CAP]			= 0x00,
-	[TCPC_REG_CONFIG_EXT_1]				= 0xfc,
-	[0x2b]						= 0xff, /* Reserved */
-	[TCPC_REG_GENERIC_TIMER]			= 0x00,
-	[TCPC_REG_GENERIC_TIMER + 1]			= 0x00,
-	[TCPC_REG_MSG_HDR_INFO]				= 0xe0,
-	[TCPC_REG_RX_DETECT]				= 0x00,
-	[TCPC_REG_RX_BUFFER ... 0x4f]			= 0x00,
-	[TCPC_REG_TRANSMIT ... 0x69]			= 0x00,
-	[TCPC_REG_VBUS_VOLTAGE]				= 0xf0,
-	[TCPC_REG_VBUS_VOLTAGE + 1]			= 0x00,
-	[TCPC_REG_VBUS_SINK_DISCONNECT_THRESH]		= 0x00,
-	[TCPC_REG_VBUS_SINK_DISCONNECT_THRESH + 1]	= 0xfc,
-	[TCPC_REG_VBUS_STOP_DISCHARGE_THRESH]		= 0x00,
-	[TCPC_REG_VBUS_STOP_DISCHARGE_THRESH + 1]	= 0xfc,
-	[TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG]		= 0x00,
-	[TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG + 1]	= 0xfc,
-	[TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG]		= 0x00,
-	[TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG + 1]	= 0xfc,
-	[TCPC_REG_VBUS_NONDEFAULT_TARGET]		= 0x00,
-	[TCPC_REG_VBUS_NONDEFAULT_TARGET + 1]		= 0x00,
-	[0x7c ... 0x7f]					= 0xff, /* Reserved */
-	[0x80 ... TCPCI_EMUL_REG_COUNT - 1]		= 0x00,
+	[TCPC_REG_VENDOR_ID] = 0x00,
+	[TCPC_REG_VENDOR_ID + 1] = 0x00,
+	[TCPC_REG_PRODUCT_ID] = 0x00,
+	[TCPC_REG_PRODUCT_ID + 1] = 0x00,
+	[TCPC_REG_BCD_DEV] = 0x00,
+	[TCPC_REG_BCD_DEV + 1] = 0xff,
+	[TCPC_REG_TC_REV] = 0x00,
+	[TCPC_REG_TC_REV + 1] = 0x00,
+	[TCPC_REG_PD_REV] = 0x00,
+	[TCPC_REG_PD_REV + 1] = 0x00,
+	[TCPC_REG_PD_INT_REV] = 0x00,
+	[TCPC_REG_PD_INT_REV + 1] = 0x00,
+	[0x0c ... 0x0f] = 0xff, /* Reserved */
+	[TCPC_REG_ALERT] = 0x00,
+	[TCPC_REG_ALERT + 1] = 0x00,
+	[TCPC_REG_ALERT_MASK] = 0x00,
+	[TCPC_REG_ALERT_MASK + 1] = 0x00,
+	[TCPC_REG_POWER_STATUS_MASK] = 0x00,
+	[TCPC_REG_FAULT_STATUS_MASK] = 0x00,
+	[TCPC_REG_EXT_STATUS_MASK] = 0xfe,
+	[TCPC_REG_ALERT_EXTENDED_MASK] = 0xf8,
+	[TCPC_REG_CONFIG_STD_OUTPUT] = 0x00,
+	[TCPC_REG_TCPC_CTRL] = 0x00,
+	[TCPC_REG_ROLE_CTRL] = 0x80,
+	[TCPC_REG_FAULT_CTRL] = 0x80,
+	[TCPC_REG_POWER_CTRL] = 0x00,
+	[TCPC_REG_CC_STATUS] = 0xc0,
+	[TCPC_REG_POWER_STATUS] = 0x00,
+	[TCPC_REG_FAULT_STATUS] = 0x00,
+	[TCPC_REG_EXT_STATUS] = 0xfe,
+	[TCPC_REG_ALERT_EXT] = 0xf8,
+	[0x22] = 0xff, /* Reserved */
+	[TCPC_REG_COMMAND] = 0x00,
+	[TCPC_REG_DEV_CAP_1] = 0x00,
+	[TCPC_REG_DEV_CAP_1 + 1] = 0x00,
+	[TCPC_REG_DEV_CAP_2] = 0x80,
+	[TCPC_REG_DEV_CAP_2 + 1] = 0x00,
+	[TCPC_REG_STD_INPUT_CAP] = 0xe0,
+	[TCPC_REG_STD_OUTPUT_CAP] = 0x00,
+	[TCPC_REG_CONFIG_EXT_1] = 0xfc,
+	[0x2b] = 0xff, /* Reserved */
+	[TCPC_REG_GENERIC_TIMER] = 0x00,
+	[TCPC_REG_GENERIC_TIMER + 1] = 0x00,
+	[TCPC_REG_MSG_HDR_INFO] = 0xe0,
+	[TCPC_REG_RX_DETECT] = 0x00,
+	[TCPC_REG_RX_BUFFER... 0x4f] = 0x00,
+	[TCPC_REG_TRANSMIT... 0x69] = 0x00,
+	[TCPC_REG_VBUS_VOLTAGE] = 0xf0,
+	[TCPC_REG_VBUS_VOLTAGE + 1] = 0x00,
+	[TCPC_REG_VBUS_SINK_DISCONNECT_THRESH] = 0x00,
+	[TCPC_REG_VBUS_SINK_DISCONNECT_THRESH + 1] = 0xfc,
+	[TCPC_REG_VBUS_STOP_DISCHARGE_THRESH] = 0x00,
+	[TCPC_REG_VBUS_STOP_DISCHARGE_THRESH + 1] = 0xfc,
+	[TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG] = 0x00,
+	[TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG + 1] = 0xfc,
+	[TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG] = 0x00,
+	[TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG + 1] = 0xfc,
+	[TCPC_REG_VBUS_NONDEFAULT_TARGET] = 0x00,
+	[TCPC_REG_VBUS_NONDEFAULT_TARGET + 1] = 0x00,
+	[0x7c ... 0x7f] = 0xff, /* Reserved */
+	[0x80 ... TCPCI_EMUL_REG_COUNT - 1] = 0x00,
 };
 
-
 /**
  * @brief Reset role control and header info registers to default values.
  *
- * @param emul Pointer to TCPCI emulator
+ * @param ctx Pointer to TCPCI context
  */
-static void tcpci_emul_reset_role_ctrl(const struct emul *emul)
+static void tcpci_emul_reset_role_ctrl(struct tcpci_ctx *ctx)
 {
-	struct tcpci_emul_data *data = emul->data;
 	uint16_t dev_cap_1;
 
-	tcpci_emul_get_reg(emul, TCPC_REG_DEV_CAP_1, &dev_cap_1);
+	get_reg(ctx, TCPC_REG_DEV_CAP_1, &dev_cap_1);
 	switch (dev_cap_1 & TCPC_REG_DEV_CAP_1_PWRROLE_MASK) {
 	case TCPC_REG_DEV_CAP_1_PWRROLE_SRC_OR_SNK:
 	case TCPC_REG_DEV_CAP_1_PWRROLE_SNK:
 	case TCPC_REG_DEV_CAP_1_PWRROLE_SNK_ACC:
-		data->reg[TCPC_REG_ROLE_CTRL]			= 0x0a;
-		data->reg[TCPC_REG_MSG_HDR_INFO]		= 0x04;
+		ctx->reg[TCPC_REG_ROLE_CTRL] = 0x0a;
+		ctx->reg[TCPC_REG_MSG_HDR_INFO] = 0x04;
 		break;
 	case TCPC_REG_DEV_CAP_1_PWRROLE_SRC:
 		/* Dead batter */
-		data->reg[TCPC_REG_ROLE_CTRL]			= 0x05;
-		data->reg[TCPC_REG_MSG_HDR_INFO]		= 0x0d;
+		ctx->reg[TCPC_REG_ROLE_CTRL] = 0x05;
+		ctx->reg[TCPC_REG_MSG_HDR_INFO] = 0x0d;
 		break;
 	case TCPC_REG_DEV_CAP_1_PWRROLE_DRP:
 		/* Dead batter and dbg acc ind */
-		data->reg[TCPC_REG_ROLE_CTRL]			= 0x4a;
-		data->reg[TCPC_REG_MSG_HDR_INFO]		= 0x04;
+		ctx->reg[TCPC_REG_ROLE_CTRL] = 0x4a;
+		ctx->reg[TCPC_REG_MSG_HDR_INFO] = 0x04;
 		break;
 	case TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP_ADPT_CBL:
 	case TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP:
 		/* Dead batter and dbg acc ind */
-		data->reg[TCPC_REG_ROLE_CTRL]			= 0x4a;
-		data->reg[TCPC_REG_MSG_HDR_INFO]		= 0x04;
+		ctx->reg[TCPC_REG_ROLE_CTRL] = 0x4a;
+		ctx->reg[TCPC_REG_MSG_HDR_INFO] = 0x04;
 		break;
 	}
 }
@@ -794,46 +780,43 @@ static void tcpci_emul_reset_role_ctrl(const struct emul *emul)
  * @param emul Pointer to TCPCI emulator
  * @return 0 if successful
  */
-static int tcpci_emul_reset(const struct emul *emul)
+int tcpci_emul_reset(const struct emul *emul)
 {
-	struct tcpci_emul_data *data = emul->data;
-
-	data->reg[TCPC_REG_ALERT]				= 0x00;
-	data->reg[TCPC_REG_ALERT + 1]				= 0x00;
-	data->reg[TCPC_REG_FAULT_STATUS_MASK]			= 0xff;
-	data->reg[TCPC_REG_CONFIG_STD_OUTPUT]			= 0x60;
-	data->reg[TCPC_REG_TCPC_CTRL]				= 0x00;
-	data->reg[TCPC_REG_FAULT_CTRL]				= 0x00;
-	data->reg[TCPC_REG_POWER_CTRL]				= 0x60;
-	data->reg[TCPC_REG_CC_STATUS]				= 0x00;
-	data->reg[TCPC_REG_POWER_STATUS]			= 0x08;
-	data->reg[TCPC_REG_FAULT_STATUS]			= 0x80;
-	data->reg[TCPC_REG_EXT_STATUS]				= 0x00;
-	data->reg[TCPC_REG_ALERT_EXT]				= 0x00;
-	data->reg[TCPC_REG_COMMAND]				= 0x00;
-	data->reg[TCPC_REG_CONFIG_EXT_1]			= 0x00;
-	data->reg[TCPC_REG_GENERIC_TIMER]			= 0x00;
-	data->reg[TCPC_REG_GENERIC_TIMER + 1]			= 0x00;
-	data->reg[TCPC_REG_RX_DETECT]				= 0x00;
-	data->reg[TCPC_REG_VBUS_VOLTAGE]			= 0x00;
-	data->reg[TCPC_REG_VBUS_VOLTAGE + 1]			= 0x00;
-	data->reg[TCPC_REG_VBUS_SINK_DISCONNECT_THRESH]		= 0x8c;
-	data->reg[TCPC_REG_VBUS_SINK_DISCONNECT_THRESH + 1]	= 0x00;
-	data->reg[TCPC_REG_VBUS_STOP_DISCHARGE_THRESH]		= 0x20;
-	data->reg[TCPC_REG_VBUS_STOP_DISCHARGE_THRESH + 1]	= 0x00;
-	data->reg[TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG]		= 0x00;
-	data->reg[TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG + 1]	= 0x00;
-	data->reg[TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG]		= 0x00;
-	data->reg[TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG + 1]	= 0x00;
-	data->reg[TCPC_REG_VBUS_NONDEFAULT_TARGET]		= 0x00;
-	data->reg[TCPC_REG_VBUS_NONDEFAULT_TARGET + 1]		= 0x00;
-
-	tcpci_emul_reset_mask_regs(emul);
-	tcpci_emul_reset_role_ctrl(emul);
-
-	if (data->dev_ops && data->dev_ops->reset) {
-		data->dev_ops->reset(emul, data->dev_ops);
-	}
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx;
+
+	ctx->reg[TCPC_REG_ALERT] = 0x00;
+	ctx->reg[TCPC_REG_ALERT + 1] = 0x00;
+	ctx->reg[TCPC_REG_FAULT_STATUS_MASK] = 0xff;
+	ctx->reg[TCPC_REG_CONFIG_STD_OUTPUT] = 0x60;
+	ctx->reg[TCPC_REG_TCPC_CTRL] = 0x00;
+	ctx->reg[TCPC_REG_FAULT_CTRL] = 0x00;
+	ctx->reg[TCPC_REG_POWER_CTRL] = 0x60;
+	ctx->reg[TCPC_REG_CC_STATUS] = 0x00;
+	ctx->reg[TCPC_REG_POWER_STATUS] = 0x08;
+	ctx->reg[TCPC_REG_FAULT_STATUS] = 0x80;
+	ctx->reg[TCPC_REG_EXT_STATUS] = 0x00;
+	ctx->reg[TCPC_REG_ALERT_EXT] = 0x00;
+	ctx->reg[TCPC_REG_COMMAND] = 0x00;
+	ctx->reg[TCPC_REG_CONFIG_EXT_1] = 0x00;
+	ctx->reg[TCPC_REG_GENERIC_TIMER] = 0x00;
+	ctx->reg[TCPC_REG_GENERIC_TIMER + 1] = 0x00;
+	ctx->reg[TCPC_REG_RX_DETECT] = 0x00;
+	ctx->reg[TCPC_REG_VBUS_VOLTAGE] = 0x00;
+	ctx->reg[TCPC_REG_VBUS_VOLTAGE + 1] = 0x00;
+	ctx->reg[TCPC_REG_VBUS_SINK_DISCONNECT_THRESH] = 0x8c;
+	ctx->reg[TCPC_REG_VBUS_SINK_DISCONNECT_THRESH + 1] = 0x00;
+	ctx->reg[TCPC_REG_VBUS_STOP_DISCHARGE_THRESH] = 0x20;
+	ctx->reg[TCPC_REG_VBUS_STOP_DISCHARGE_THRESH + 1] = 0x00;
+	ctx->reg[TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG] = 0x00;
+	ctx->reg[TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG + 1] = 0x00;
+	ctx->reg[TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG] = 0x00;
+	ctx->reg[TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG + 1] = 0x00;
+	ctx->reg[TCPC_REG_VBUS_NONDEFAULT_TARGET] = 0x00;
+	ctx->reg[TCPC_REG_VBUS_NONDEFAULT_TARGET + 1] = 0x00;
+
+	tcpci_emul_reset_mask_regs(ctx);
+	tcpci_emul_reset_role_ctrl(ctx);
 
 	return tcpci_emul_alert_changed(emul);
 }
@@ -841,16 +824,18 @@ static int tcpci_emul_reset(const struct emul *emul)
 /**
  * @brief Set alert and fault registers to indicate i2c interface fault
  *
- * @param emul Pointer to TCPCI emulator
+ * @param emul Pointer to TCPC emulator
  * @return 0 if successful
  */
 static int tcpci_emul_set_i2c_interface_err(const struct emul *emul)
 {
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx;
 	uint16_t fault_status;
 
-	tcpci_emul_get_reg(emul, TCPC_REG_FAULT_STATUS, &fault_status);
+	get_reg(ctx, TCPC_REG_FAULT_STATUS, &fault_status);
 	fault_status |= TCPC_REG_FAULT_STATUS_I2C_INTERFACE_ERR;
-	tcpci_emul_set_reg(emul, TCPC_REG_FAULT_STATUS, fault_status);
+	set_reg(ctx, TCPC_REG_FAULT_STATUS, fault_status);
 
 	return tcpci_emul_alert_changed(emul);
 }
@@ -858,7 +843,7 @@ static int tcpci_emul_set_i2c_interface_err(const struct emul *emul)
 /**
  * @brief Handle read from RX buffer registers for TCPCI rev 1.0 and rev 2.0
  *
- * @param emul Pointer to TCPCI emulator
+ * @param emul Pointer to TCPC emulator
  * @param reg First byte of last i2c write message
  * @param val Pointer where byte to read should be stored
  * @param bytes Number of bytes already readded
@@ -869,10 +854,11 @@ static int tcpci_emul_set_i2c_interface_err(const struct emul *emul)
 static int tcpci_emul_handle_rx_buf(const struct emul *emul, int reg,
 				    uint8_t *val, int bytes)
 {
-	struct tcpci_emul_data *data = emul->data;
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx;
 	int is_rev1;
 
-	is_rev1 = data->reg[TCPC_REG_PD_INT_REV] == TCPC_REG_PD_INT_REV_REV_1_0;
+	is_rev1 = ctx->reg[TCPC_REG_PD_INT_REV] == TCPC_REG_PD_INT_REV_REV_1_0;
 
 	if (!is_rev1 && reg != TCPC_REG_RX_BUFFER) {
 		LOG_ERR("Register 0x%x defined only for revision 1.0", reg);
@@ -882,7 +868,7 @@ static int tcpci_emul_handle_rx_buf(const struct emul *emul, int reg,
 
 	switch (reg) {
 	case TCPC_REG_RX_BUFFER:
-		if (data->rx_msg == NULL) {
+		if (ctx->rx_msg == NULL) {
 			if (bytes < 2) {
 				*val = 0;
 			} else {
@@ -894,16 +880,16 @@ static int tcpci_emul_handle_rx_buf(const struct emul *emul, int reg,
 		}
 		if (bytes == 0) {
 			/* TCPCI message size count include type byte */
-			*val = data->rx_msg->cnt + 1;
+			*val = ctx->rx_msg->cnt + 1;
 		} else if (is_rev1) {
 			LOG_ERR("Revision 1.0 has only byte count at 0x30");
 			tcpci_emul_set_i2c_interface_err(emul);
 			return -EIO;
 		} else if (bytes == 1) {
-			*val = data->rx_msg->type;
-		} else if (data->rx_msg->idx < data->rx_msg->cnt) {
-			*val = data->rx_msg->buf[data->rx_msg->idx];
-			data->rx_msg->idx++;
+			*val = ctx->rx_msg->sop_type;
+		} else if (ctx->rx_msg->idx < ctx->rx_msg->cnt) {
+			*val = ctx->rx_msg->buf[ctx->rx_msg->idx];
+			ctx->rx_msg->idx++;
 		} else {
 			LOG_ERR("Reading past RX buffer");
 			tcpci_emul_set_i2c_interface_err(emul);
@@ -918,10 +904,10 @@ static int tcpci_emul_handle_rx_buf(const struct emul *emul, int reg,
 			tcpci_emul_set_i2c_interface_err(emul);
 			return -EIO;
 		}
-		if (data->rx_msg == NULL) {
+		if (ctx->rx_msg == NULL) {
 			*val = 0;
 		} else {
-			*val = data->rx_msg->type;
+			*val = ctx->rx_msg->sop_type;
 		}
 		break;
 
@@ -932,24 +918,24 @@ static int tcpci_emul_handle_rx_buf(const struct emul *emul, int reg,
 			tcpci_emul_set_i2c_interface_err(emul);
 			return -EIO;
 		}
-		if (data->rx_msg == NULL) {
+		if (ctx->rx_msg == NULL) {
 			LOG_ERR("Accessing RX buffer with no msg");
 			tcpci_emul_set_i2c_interface_err(emul);
 			return -EIO;
 		}
-		*val = data->rx_msg->buf[bytes];
+		*val = ctx->rx_msg->buf[bytes];
 		break;
 
 	case TCPC_REG_RX_DATA:
-		if (data->rx_msg == NULL) {
+		if (ctx->rx_msg == NULL) {
 			LOG_ERR("Accessing RX buffer with no msg");
 			tcpci_emul_set_i2c_interface_err(emul);
 			return -EIO;
 		}
-		if (bytes < data->rx_msg->cnt - 2) {
+		if (bytes < ctx->rx_msg->cnt - 2) {
 			/* rx_msg cnt include two bytes of header */
-			*val = data->rx_msg->buf[bytes + 2];
-			data->rx_msg->idx++;
+			*val = ctx->rx_msg->buf[bytes + 2];
+			ctx->rx_msg->idx++;
 		} else {
 			LOG_ERR("Reading past RX buffer");
 			tcpci_emul_set_i2c_interface_err(emul);
@@ -961,39 +947,12 @@ static int tcpci_emul_handle_rx_buf(const struct emul *emul, int reg,
 	return 0;
 }
 
-/**
- * @brief Function called for each byte of read message
- *
- * @param i2c_emul Pointer to TCPCI emulator
- * @param reg First byte of last write message
- * @param val Pointer where byte to read should be stored
- * @param bytes Number of bytes already readded
- *
- * @return 0 on success
- */
-static int tcpci_emul_read_byte(struct i2c_emul *i2c_emul, int reg,
-				uint8_t *val, int bytes)
+/** Check description in emul_tcpci.h */
+int tcpci_emul_read_byte(const struct emul *emul, int reg, uint8_t *val,
+			 int bytes)
 {
-	struct tcpci_emul_data *data;
-	const struct emul *emul;
-
-	emul = i2c_emul->parent;
-	data = TCPCI_DATA_FROM_I2C_EMUL(i2c_emul);
-
-	LOG_DBG("TCPCI 0x%x: read reg 0x%x", i2c_emul->addr, reg);
-
-	if (data->dev_ops && data->dev_ops->read_byte) {
-		switch (data->dev_ops->read_byte(emul, data->dev_ops, reg, val,
-						 bytes)) {
-		case TCPCI_EMUL_CONTINUE:
-			break;
-		case TCPCI_EMUL_DONE:
-			return 0;
-		case TCPCI_EMUL_ERROR:
-		default:
-			return -EIO;
-		}
-	}
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx;
 
 	switch (reg) {
 	/* 16 bits values */
@@ -1019,7 +978,7 @@ static int tcpci_emul_read_byte(struct i2c_emul *i2c_emul, int reg,
 			tcpci_emul_set_i2c_interface_err(emul);
 			return -EIO;
 		}
-		*val = data->reg[reg + bytes];
+		*val = ctx->reg[reg + bytes];
 		break;
 
 	/* 8 bits values */
@@ -1048,7 +1007,7 @@ static int tcpci_emul_read_byte(struct i2c_emul *i2c_emul, int reg,
 			tcpci_emul_set_i2c_interface_err(emul);
 			return -EIO;
 		}
-		*val = data->reg[reg];
+		*val = ctx->reg[reg];
 		break;
 
 	case TCPC_REG_RX_BUFFER:
@@ -1066,43 +1025,15 @@ static int tcpci_emul_read_byte(struct i2c_emul *i2c_emul, int reg,
 	return 0;
 }
 
-/**
- * @brief Function called for each byte of write message. Data are stored
- *        in write_data field of tcpci_emul_data or in tx_msg in case of
- *        writing to TX buffer.
- *
- * @param i2c_emul Pointer to TCPCI emulator
- * @param reg First byte of write message
- * @param val Received byte of write message
- * @param bytes Number of bytes already received
- *
- * @return 0 on success
- * @return -EIO on invalid write to TX buffer
- */
-static int tcpci_emul_write_byte(struct i2c_emul *i2c_emul, int reg,
-				 uint8_t val, int bytes)
+/** Check description in emul_tcpci.h */
+int tcpci_emul_write_byte(const struct emul *emul, int reg, uint8_t val,
+			  int bytes)
 {
-	struct tcpci_emul_data *data;
-	const struct emul *emul;
 	int is_rev1;
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx;
 
-	emul = i2c_emul->parent;
-	data = TCPCI_DATA_FROM_I2C_EMUL(i2c_emul);
-
-	if (data->dev_ops && data->dev_ops->write_byte) {
-		switch (data->dev_ops->write_byte(emul, data->dev_ops, reg, val,
-						  bytes)) {
-		case TCPCI_EMUL_CONTINUE:
-			break;
-		case TCPCI_EMUL_DONE:
-			return 0;
-		case TCPCI_EMUL_ERROR:
-		default:
-			return -EIO;
-		}
-	}
-
-	is_rev1 = data->reg[TCPC_REG_PD_INT_REV] == TCPC_REG_PD_INT_REV_REV_1_0;
+	is_rev1 = ctx->reg[TCPC_REG_PD_INT_REV] == TCPC_REG_PD_INT_REV_REV_1_0;
 	switch (reg) {
 	case TCPC_REG_TX_BUFFER:
 		if (is_rev1) {
@@ -1111,16 +1042,16 @@ static int tcpci_emul_write_byte(struct i2c_emul *i2c_emul, int reg,
 				tcpci_emul_set_i2c_interface_err(emul);
 				return -EIO;
 			}
-			data->tx_msg->idx = val;
+			ctx->tx_msg->idx = val;
 		}
 
 		if (bytes == 1) {
-			data->tx_msg->cnt = val;
+			ctx->tx_msg->cnt = val;
 		} else {
-			if (data->tx_msg->cnt > 0) {
-				data->tx_msg->cnt--;
-				data->tx_msg->buf[data->tx_msg->idx] = val;
-				data->tx_msg->idx++;
+			if (ctx->tx_msg->cnt > 0) {
+				ctx->tx_msg->cnt--;
+				ctx->tx_msg->buf[ctx->tx_msg->idx] = val;
+				ctx->tx_msg->idx++;
 			} else {
 				LOG_ERR("Writing past TX buffer");
 				tcpci_emul_set_i2c_interface_err(emul);
@@ -1146,7 +1077,7 @@ static int tcpci_emul_write_byte(struct i2c_emul *i2c_emul, int reg,
 			tcpci_emul_set_i2c_interface_err(emul);
 			return -EIO;
 		}
-		data->tx_msg->buf[bytes] = val;
+		ctx->tx_msg->buf[bytes] = val;
 		return 0;
 
 	case TCPC_REG_TX_HDR:
@@ -1162,18 +1093,18 @@ static int tcpci_emul_write_byte(struct i2c_emul *i2c_emul, int reg,
 
 		if (bytes > 1) {
 			LOG_ERR("Writing byte %d to 2 byte register 0x%x",
-				 bytes, reg);
+				bytes, reg);
 			tcpci_emul_set_i2c_interface_err(emul);
 			return -EIO;
 		}
-		data->tx_msg->buf[bytes] = val;
+		ctx->tx_msg->buf[bytes] = val;
 		return 0;
 	}
 
 	if (bytes == 1) {
-		data->write_data = val;
+		ctx->write_data = val;
 	} else if (bytes == 2) {
-		data->write_data |= (uint16_t)val << 8;
+		ctx->write_data |= (uint16_t)val << 8;
 	}
 
 	return 0;
@@ -1182,43 +1113,44 @@ static int tcpci_emul_write_byte(struct i2c_emul *i2c_emul, int reg,
 /**
  * @brief Handle writes to command register
  *
- * @param emul Pointer to TCPCI emulator
+ * @param emul Pointer to TCPC emulator
  *
  * @return 0 on success
  * @return -EIO on unknown command value
  */
 static int tcpci_emul_handle_command(const struct emul *emul)
 {
-	struct tcpci_emul_data *data = emul->data;
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx;
 	uint16_t role_ctrl;
 	uint16_t pwr_ctrl;
 
-	switch (data->write_data & 0xff) {
+	switch (ctx->write_data & 0xff) {
 	case TCPC_REG_COMMAND_RESET_TRANSMIT_BUF:
-		data->tx_msg->idx = 0;
+		ctx->tx_msg->idx = 0;
 		break;
 	case TCPC_REG_COMMAND_RESET_RECEIVE_BUF:
-		if (data->rx_msg) {
-			data->rx_msg->idx = 0;
+		if (ctx->rx_msg) {
+			ctx->rx_msg->idx = 0;
 		}
 		break;
 	case TCPC_REG_COMMAND_LOOK4CONNECTION:
-		tcpci_emul_get_reg(emul, TCPC_REG_ROLE_CTRL, &role_ctrl);
-		tcpci_emul_get_reg(emul, TCPC_REG_POWER_CTRL, &pwr_ctrl);
+		get_reg(ctx, TCPC_REG_ROLE_CTRL, &role_ctrl);
+		get_reg(ctx, TCPC_REG_POWER_CTRL, &pwr_ctrl);
 
 		/*
 		 * Start DRP toggling only if auto discharge is disabled,
 		 * DRP is enabled and CC1/2 are both Rp or Rd
 		 */
-		if (!(pwr_ctrl & TCPC_REG_POWER_CTRL_AUTO_DISCHARGE_DISCONNECT)
-		    && TCPC_REG_ROLE_CTRL_DRP(role_ctrl) &&
+		if (!(pwr_ctrl &
+		      TCPC_REG_POWER_CTRL_AUTO_DISCHARGE_DISCONNECT) &&
+		    TCPC_REG_ROLE_CTRL_DRP(role_ctrl) &&
 		    (TCPC_REG_ROLE_CTRL_CC1(role_ctrl) ==
 		     TCPC_REG_ROLE_CTRL_CC2(role_ctrl)) &&
 		    (TCPC_REG_ROLE_CTRL_CC1(role_ctrl) == TYPEC_CC_RP ||
 		     TCPC_REG_ROLE_CTRL_CC1(role_ctrl) == TYPEC_CC_RD)) {
 			/* Set Look4Connection and clear CC1/2 state */
-			tcpci_emul_set_reg(
-				emul, TCPC_REG_CC_STATUS,
+			set_reg(ctx, TCPC_REG_CC_STATUS,
 				TCPC_REG_CC_STATUS_LOOK4CONNECTION_MASK);
 		}
 		break;
@@ -1238,45 +1170,47 @@ static int tcpci_emul_handle_command(const struct emul *emul)
 	 * Set command register to allow easier inspection of last
 	 * command sent
 	 */
-	tcpci_emul_set_reg(emul, TCPC_REG_COMMAND, data->write_data & 0xff);
+	set_reg(ctx, TCPC_REG_COMMAND, ctx->write_data & 0xff);
 	return 0;
 }
 
 /**
  * @brief Handle write to transmit register
  *
- * @param emul Pointer to TCPCI emulator
+ * @param emul Pointer to TCPC emulator
  *
  * @return 0 on success
  * @return -EIO when sending SOP message with less than 2 bytes in TX buffer
  */
 static int tcpci_emul_handle_transmit(const struct emul *emul)
 {
-	struct tcpci_emul_data *data = emul->data;
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx;
 	enum tcpci_msg_type type;
 
-	data->tx_msg->cnt = data->tx_msg->idx;
-	data->tx_msg->type = TCPC_REG_TRANSMIT_TYPE(data->write_data);
-	data->tx_msg->idx = 0;
+	ctx->tx_msg->cnt = ctx->tx_msg->idx;
+	ctx->tx_msg->sop_type = TCPC_REG_TRANSMIT_TYPE(ctx->write_data);
+	ctx->tx_msg->idx = 0;
 
-	type = TCPC_REG_TRANSMIT_TYPE(data->write_data);
+	type = TCPC_REG_TRANSMIT_TYPE(ctx->write_data);
 
-	if (type < NUM_SOP_STAR_TYPES && data->tx_msg->cnt < 2) {
+	if (type < NUM_SOP_STAR_TYPES && ctx->tx_msg->cnt < 2) {
 		LOG_ERR("Transmitting too short message (%d)",
-			data->tx_msg->cnt);
+			ctx->tx_msg->cnt);
 		tcpci_emul_set_i2c_interface_err(emul);
 		return -EIO;
 	}
 
-	if (data->partner && data->partner->transmit) {
-		data->partner->transmit(emul, data->partner, data->tx_msg, type,
-				TCPC_REG_TRANSMIT_RETRY(data->write_data));
+	if (ctx->partner && ctx->partner->transmit) {
+		ctx->partner->transmit(
+			emul, ctx->partner, ctx->tx_msg, type,
+			TCPC_REG_TRANSMIT_RETRY(ctx->write_data));
 	}
 
 	switch (type) {
 	case TCPCI_MSG_TX_HARD_RESET:
 		tcpci_emul_disable_pd_msg_delivery(emul);
-		tcpci_emul_reset_mask_regs(emul);
+		tcpci_emul_reset_mask_regs(ctx);
 		/* fallthrough */
 	case TCPCI_MSG_CABLE_RESET:
 		/*
@@ -1293,22 +1227,11 @@ static int tcpci_emul_handle_transmit(const struct emul *emul)
 	return 0;
 }
 
-/**
- * @brief Handle I2C write message. It is checked if accessed register isn't RO
- *        and reserved bits are set to 0.
- *
- * @param i2c_emul Pointer to TCPCI emulator
- * @param reg Register which is written
- * @param msg_len Length of handled I2C message
- *
- * @return 0 on success
- * @return -EIO on error
- */
-static int tcpci_emul_handle_write(struct i2c_emul *i2c_emul, int reg,
-				   int msg_len)
+/** Check description in emul_tcpci.h */
+int tcpci_emul_handle_write(const struct emul *emul, int reg, int msg_len)
 {
-	struct tcpci_emul_data *data;
-	const struct emul *emul;
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx;
 	uint16_t rsvd_mask = 0;
 	uint16_t alert_val;
 	bool inform_partner = false;
@@ -1324,43 +1247,24 @@ static int tcpci_emul_handle_write(struct i2c_emul *i2c_emul, int reg,
 	/* Exclude register address byte from message length */
 	msg_len--;
 
-	emul = i2c_emul->parent;
-	data = TCPCI_DATA_FROM_I2C_EMUL(i2c_emul);
-
-	LOG_DBG("TCPCI 0x%x: write reg 0x%x val 0x%x", i2c_emul->addr, reg,
-		data->write_data);
-
-	if (data->dev_ops && data->dev_ops->handle_write) {
-		switch (data->dev_ops->handle_write(emul, data->dev_ops, reg,
-						    msg_len)) {
-		case TCPCI_EMUL_CONTINUE:
-			break;
-		case TCPCI_EMUL_DONE:
-			return 0;
-		case TCPCI_EMUL_ERROR:
-		default:
-			return -EIO;
-		}
-	}
-
 	switch (reg) {
 	/* Alert registers */
 	case TCPC_REG_ALERT:
 		/* Overflow is cleared by Receive SOP message status */
-		data->write_data &= ~TCPC_REG_ALERT_RX_BUF_OVF;
-		if (data->write_data & TCPC_REG_ALERT_RX_STATUS) {
-			data->write_data |= TCPC_REG_ALERT_RX_BUF_OVF;
+		ctx->write_data &= ~TCPC_REG_ALERT_RX_BUF_OVF;
+		if (ctx->write_data & TCPC_REG_ALERT_RX_STATUS) {
+			ctx->write_data |= TCPC_REG_ALERT_RX_BUF_OVF;
 			/* Do not clear RX status if there is new message */
 			if (tcpci_emul_get_next_rx_msg(emul)) {
-				data->write_data &= ~TCPC_REG_ALERT_RX_STATUS;
+				ctx->write_data &= ~TCPC_REG_ALERT_RX_STATUS;
 			}
 		}
 	/* fallthrough */
 	case TCPC_REG_FAULT_STATUS:
 	case TCPC_REG_ALERT_EXT:
 		/* Clear bits where TCPM set 1 */
-		tcpci_emul_get_reg(emul, reg, &alert_val);
-		data->write_data = alert_val & (~data->write_data);
+		get_reg(ctx, reg, &alert_val);
+		ctx->write_data = alert_val & (~ctx->write_data);
 	/* fallthrough */
 	case TCPC_REG_ALERT_MASK:
 	case TCPC_REG_POWER_STATUS_MASK:
@@ -1390,11 +1294,11 @@ static int tcpci_emul_handle_write(struct i2c_emul *i2c_emul, int reg,
 		break;
 
 	case TCPC_REG_CONFIG_EXT_1:
-		if (data->write_data & TCPC_REG_CONFIG_EXT_1_FR_SWAP_SNK_DIR &&
-		    ((data->reg[TCPC_REG_STD_INPUT_CAP] &
+		if (ctx->write_data & TCPC_REG_CONFIG_EXT_1_FR_SWAP_SNK_DIR &&
+		    ((ctx->reg[TCPC_REG_STD_INPUT_CAP] &
 		      TCPC_REG_STD_INPUT_CAP_SRC_FR_SWAP) == BIT(4)) &&
-		    data->reg[TCPC_REG_STD_OUTPUT_CAP] &
-		    TCPC_REG_STD_OUTPUT_CAP_SNK_DISC_DET) {
+		    ctx->reg[TCPC_REG_STD_OUTPUT_CAP] &
+			    TCPC_REG_STD_OUTPUT_CAP_SNK_DISC_DET) {
 			tcpci_emul_set_i2c_interface_err(emul);
 			return 0;
 		}
@@ -1447,23 +1351,23 @@ static int tcpci_emul_handle_write(struct i2c_emul *i2c_emul, int reg,
 	}
 
 	/* Check reserved bits */
-	if (data->error_on_rsvd_write && rsvd_mask & data->write_data) {
+	if (ctx->error_on_rsvd_write && rsvd_mask & ctx->write_data) {
 		tcpci_emul_set_i2c_interface_err(emul);
 		LOG_ERR("Writing 0x%x to reg 0x%x with rsvd bits mask 0x%x",
-			data->write_data, reg, rsvd_mask);
+			ctx->write_data, reg, rsvd_mask);
 		return -EIO;
 	}
 
 	/* Check if I2C write message has correct length */
 	if (msg_len != reg_bytes) {
 		tcpci_emul_set_i2c_interface_err(emul);
-		LOG_ERR("Writing byte %d to %d byte register 0x%x",
-			msg_len, reg_bytes, reg);
+		LOG_ERR("Writing byte %d to %d byte register 0x%x", msg_len,
+			reg_bytes, reg);
 		return -EIO;
 	}
 
 	/* Set new value of register */
-	tcpci_emul_set_reg(emul, reg, data->write_data);
+	set_reg(ctx, reg, ctx->write_data);
 
 	if (alert_changed) {
 		rc = tcpci_emul_alert_changed(emul);
@@ -1471,119 +1375,22 @@ static int tcpci_emul_handle_write(struct i2c_emul *i2c_emul, int reg,
 			return rc;
 	}
 
-	if (inform_partner && data->partner && data->partner->control_change) {
-		data->partner->control_change(emul, data->partner);
+	if (inform_partner && ctx->partner && ctx->partner->control_change) {
+		ctx->partner->control_change(emul, ctx->partner);
 	}
 
 	return 0;
 }
 
-/**
- * @brief Get currently accessed register, which always equals to selected
- *        register.
- *
- * @param i2c_emul Pointer to TCPCI emulator
- * @param reg First byte of last write message
- * @param bytes Number of bytes already handled from current message
- * @param read If currently handled is read message
- *
- * @return Currently accessed register
- */
-static int tcpci_emul_access_reg(struct i2c_emul *i2c_emul, int reg, int bytes,
-				 bool read)
-{
-	return reg;
-}
-
-/* Device instantiation */
-
 /** Check description in emul_tcpci.h */
-struct i2c_emul *tcpci_emul_get_i2c_emul(const struct emul *emul)
+void tcpci_emul_i2c_init(const struct emul *emul, const struct device *i2c_dev)
 {
-	struct tcpci_emul_data *data = emul->data;
-
-	return &data->common.emul;
-}
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx;
 
-/**
- * @brief Set up a new TCPCI emulator
- *
- * This should be called for each TCPCI device that needs to be
- * emulated. It registers it with the I2C emulation controller.
- *
- * @param emul Emulation information
- * @param parent Device to emulate
- *
- * @return 0 indicating success (always)
- */
-static int tcpci_emul_init(const struct emul *emul, const struct device *parent)
-{
-	const struct i2c_common_emul_cfg *cfg = emul->cfg;
-	struct tcpci_emul_data *data = emul->data;
-	int ret;
-
-	data->common.emul.api = &i2c_common_emul_api;
-	data->common.emul.addr = cfg->addr;
-	data->common.emul.parent = emul;
-	data->common.i2c = parent;
-	data->common.cfg = cfg;
-	i2c_common_emul_init(&data->common);
-
-	ret = i2c_emul_register(parent, emul->dev_label, &data->common.emul);
-	if (ret != 0)
-		return ret;
-
-	return tcpci_emul_reset(emul);
-}
+	ctx->common.emul.addr = tcpc_data->i2c_cfg.addr;
+	ctx->common.i2c = i2c_dev;
+	ctx->common.cfg = &tcpc_data->i2c_cfg;
 
-#define TCPCI_EMUL(n)							\
-	uint8_t tcpci_emul_tx_buf_##n[128];				\
-	static struct tcpci_emul_msg tcpci_emul_tx_msg_##n = {		\
-		.buf = tcpci_emul_tx_buf_##n,				\
-	};								\
-									\
-	static struct tcpci_emul_data tcpci_emul_data_##n = {		\
-		.tx_msg = &tcpci_emul_tx_msg_##n,			\
-		.error_on_ro_write = true,				\
-		.error_on_rsvd_write = true,				\
-		.common = {						\
-			.write_byte = tcpci_emul_write_byte,		\
-			.finish_write = tcpci_emul_handle_write,	\
-			.read_byte = tcpci_emul_read_byte,		\
-			.access_reg = tcpci_emul_access_reg,		\
-		},							\
-		.alert_gpio_port = COND_CODE_1(				\
-			DT_INST_NODE_HAS_PROP(n, alert_gpio),		\
-			(DEVICE_DT_GET(DT_GPIO_CTLR(			\
-				DT_INST_PROP(n, alert_gpio), gpios))),	\
-			(NULL)),					\
-		.alert_gpio_pin = COND_CODE_1(				\
-			DT_INST_NODE_HAS_PROP(n, alert_gpio),		\
-			(DT_GPIO_PIN(DT_INST_PROP(n, alert_gpio),	\
-				gpios)),				\
-			(0)),						\
-	};								\
-									\
-	static const struct i2c_common_emul_cfg tcpci_emul_cfg_##n = {	\
-		.i2c_label = DT_INST_BUS_LABEL(n),			\
-		.dev_label = DT_INST_LABEL(n),                          \
-		.data = &tcpci_emul_data_##n.common,			\
-		.addr = DT_INST_REG_ADDR(n),				\
-	};								\
-	EMUL_DEFINE(tcpci_emul_init, DT_DRV_INST(n),			\
-		    &tcpci_emul_cfg_##n, &tcpci_emul_data_##n)
-
-DT_INST_FOREACH_STATUS_OKAY(TCPCI_EMUL)
-
-#ifdef CONFIG_ZTEST_NEW_API
-#define TCPCI_EMUL_RESET_RULE_BEFORE(n) \
-	tcpci_emul_reset(&EMUL_REG_NAME(DT_DRV_INST(n)));
-static void tcpci_emul_reset_rule_before(const struct ztest_unit_test *test,
-					 void *data)
-{
-	ARG_UNUSED(test);
-	ARG_UNUSED(data);
-	DT_INST_FOREACH_STATUS_OKAY(TCPCI_EMUL_RESET_RULE_BEFORE);
+	i2c_common_emul_init(&ctx->common);
 }
-ZTEST_RULE(tcpci_emul_reset, tcpci_emul_reset_rule_before, NULL);
-#endif /* CONFIG_ZTEST_NEW_API */
diff --git a/zephyr/emul/tcpc/emul_tcpci_generic.c b/zephyr/emul/tcpc/emul_tcpci_generic.c
new file mode 100644
index 0000000000..204e040ede
--- /dev/null
+++ b/zephyr/emul/tcpc/emul_tcpci_generic.c
@@ -0,0 +1,185 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#define DT_DRV_COMPAT cros_tcpci_generic_emul
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(tcpci_generic_emul, CONFIG_TCPCI_EMUL_LOG_LEVEL);
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/i2c_emul.h>
+#include <zephyr/ztest.h>
+
+#include "tcpm/tcpci.h"
+#include "emul/emul_stub_device.h"
+
+#include "emul/emul_common_i2c.h"
+#include "emul/tcpc/emul_tcpci.h"
+
+/**
+ * @brief Function called for each byte of read message from TCPCI emulator
+ *
+ * @param emul Pointer to I2C TCPCI emulator
+ * @param reg First byte of last write message
+ * @param val Pointer where byte to read should be stored
+ * @param bytes Number of bytes already read
+ *
+ * @return 0 on success
+ * @return -EIO on invalid read request
+ */
+static int tcpci_generic_emul_read_byte(const struct emul *emul, int reg,
+					uint8_t *val, int bytes)
+{
+	LOG_DBG("TCPCI Generic 0x%x: read reg 0x%x", emul->bus.i2c->addr, reg);
+
+	return tcpci_emul_read_byte(emul, reg, val, bytes);
+}
+
+/**
+ * @brief Function called for each byte of write message to TCPCI emulator
+ *
+ * @param emul Pointer to I2C TCPCI emulator
+ * @param reg First byte of write message
+ * @param val Received byte of write message
+ * @param bytes Number of bytes already received
+ *
+ * @return 0 on success
+ * @return -EIO on invalid write request
+ */
+static int tcpci_generic_emul_write_byte(const struct emul *emul, int reg,
+					 uint8_t val, int bytes)
+{
+	LOG_DBG("TCPCI Generic 0x%x: write reg 0x%x", emul->bus.i2c->addr, reg);
+
+	return tcpci_emul_write_byte(emul, reg, val, bytes);
+}
+
+/**
+ * @brief Function called on the end of write message to TCPCI emulator
+ *
+ * @param emul Pointer to I2C TCPCI emulator
+ * @param reg Register which is written
+ * @param msg_len Length of handled I2C message
+ *
+ * @return 0 on success
+ * @return -EIO on error
+ */
+static int tcpci_generic_emul_finish_write(const struct emul *emul, int reg,
+					   int msg_len)
+{
+	LOG_DBG("TCPCI Generic 0x%x: finish write reg 0x%x",
+		emul->bus.i2c->addr, reg);
+
+	return tcpci_emul_handle_write(emul, reg, msg_len);
+}
+
+/**
+ * @brief Get currently accessed register, which always equals to selected
+ *        register from TCPCI emulator.
+ *
+ * @param emul Pointer to I2C TCPCI emulator
+ * @param reg First byte of last write message
+ * @param bytes Number of bytes already handled from current message
+ * @param read If currently handled is read message
+ *
+ * @return Currently accessed register
+ */
+static int tcpci_generic_emul_access_reg(const struct emul *emul, int reg,
+					 int bytes, bool read)
+{
+	return reg;
+}
+
+/**
+ * @brief Function called on reset
+ *
+ * @param emul Pointer to TCPC emulator
+ */
+static void tcpci_generic_emul_reset(const struct emul *emul)
+{
+	tcpci_emul_reset(emul);
+}
+
+/**
+ * @brief Set up a new TCPCI generic emulator
+ *
+ * This should be called for each TCPCI Generic device that needs to be
+ * emulated.
+ *
+ * @param emul Emulation information
+ * @param parent Device to emulate
+ *
+ * @return 0 indicating success (always)
+ */
+static int tcpci_generic_emul_init(const struct emul *emul,
+				   const struct device *parent)
+{
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *tcpci_ctx = tcpc_data->tcpci_ctx;
+	const struct device *i2c_dev;
+
+	i2c_dev = parent;
+
+	tcpci_ctx->common.write_byte = tcpci_generic_emul_write_byte;
+	tcpci_ctx->common.finish_write = tcpci_generic_emul_finish_write;
+	tcpci_ctx->common.read_byte = tcpci_generic_emul_read_byte;
+	tcpci_ctx->common.access_reg = tcpci_generic_emul_access_reg;
+
+	tcpci_emul_i2c_init(emul, i2c_dev);
+
+	tcpci_generic_emul_reset(emul);
+
+	return 0;
+}
+
+static int i2c_tcpci_generic_emul_transfer(const struct emul *target,
+					   struct i2c_msg *msgs, int num_msgs,
+					   int addr)
+{
+	struct tcpc_emul_data *tcpc_data = target->data;
+	struct tcpci_ctx *tcpci_ctx = tcpc_data->tcpci_ctx;
+
+	return i2c_common_emul_transfer_workhorse(target, &tcpci_ctx->common,
+						  &tcpc_data->i2c_cfg, msgs,
+						  num_msgs, addr);
+}
+
+struct i2c_emul_api i2c_tcpci_generic_emul_api = {
+	.transfer = i2c_tcpci_generic_emul_transfer,
+};
+
+#define TCPCI_GENERIC_EMUL(n)                                     \
+	TCPCI_EMUL_DEFINE(n, tcpci_generic_emul_init, NULL, NULL, \
+			  &i2c_tcpci_generic_emul_api)
+
+DT_INST_FOREACH_STATUS_OKAY(TCPCI_GENERIC_EMUL)
+
+#ifdef CONFIG_ZTEST_NEW_API
+#define TCPCI_GENERIC_EMUL_RESET_RULE_BEFORE(n) \
+	tcpci_generic_emul_reset(EMUL_DT_GET(DT_DRV_INST(n)));
+static void
+tcpci_generic_emul_reset_rule_before(const struct ztest_unit_test *test,
+				     void *data)
+{
+	ARG_UNUSED(test);
+	ARG_UNUSED(data);
+	DT_INST_FOREACH_STATUS_OKAY(TCPCI_GENERIC_EMUL_RESET_RULE_BEFORE);
+}
+ZTEST_RULE(tcpci_generic_emul_reset, tcpci_generic_emul_reset_rule_before,
+	   NULL);
+#endif /* CONFIG_ZTEST_NEW_API */
+
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
+
+struct i2c_common_emul_data *
+emul_tcpci_generic_get_i2c_common_data(const struct emul *emul)
+{
+	struct tcpc_emul_data *tcpc_data = emul->data;
+	struct tcpci_ctx *tcpci_ctx = tcpc_data->tcpci_ctx;
+
+	return &tcpci_ctx->common;
+}
diff --git a/zephyr/emul/tcpc/emul_tcpci_partner_common.c b/zephyr/emul/tcpc/emul_tcpci_partner_common.c
index 49c5278908..4d6467378e 100644
--- a/zephyr/emul/tcpc/emul_tcpci_partner_common.c
+++ b/zephyr/emul/tcpc/emul_tcpci_partner_common.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,18 +8,21 @@ LOG_MODULE_REGISTER(tcpci_partner, CONFIG_TCPCI_EMUL_LOG_LEVEL);
 
 #include <stdlib.h>
 #include <zephyr/sys/byteorder.h>
-#include <zephyr/zephyr.h>
-#include <ztest.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
 
 #include "common.h"
 #include "emul/tcpc/emul_tcpci_partner_common.h"
 #include "emul/tcpc/emul_tcpci.h"
 #include "usb_pd.h"
+#include "util.h"
 
 /** Length of PDO, RDO and BIST request object in SOP message in bytes */
-#define TCPCI_MSG_DO_LEN	4
+#define TCPCI_MSG_DO_LEN 4
 /** Length of header in SOP message in bytes  */
-#define TCPCI_MSG_HEADER_LEN	2
+#define TCPCI_MSG_HEADER_LEN 2
+/** Length of extended header in bytes  */
+#define TCPCI_MSG_EXT_HEADER_LEN 2
 
 void tcpci_partner_common_hard_reset_as_role(struct tcpci_partner_data *data,
 					     enum pd_power_role power_role)
@@ -27,33 +30,104 @@ void tcpci_partner_common_hard_reset_as_role(struct tcpci_partner_data *data,
 	data->power_role = power_role;
 	data->data_role = power_role == PD_ROLE_SOURCE ? PD_ROLE_DFP :
 							 PD_ROLE_UFP;
+	data->displayport_configured = false;
+	data->entered_svid = 0;
+	atomic_clear(&data->mode_enter_attempts);
 }
 
-struct tcpci_partner_msg *tcpci_partner_alloc_msg(int data_objects)
+/**
+ * @brief Allocate space for a PD message. Do not call directly; use
+ *        tcpci_partner_alloc_standard_msg() or
+ * tcpci_partner_alloc_extended_msg() depending on the type of message.
+ *
+ * @param size Size of the message in bytes, including header(s)
+ *
+ * @return Pointer to new message on success
+ * @return NULL on error
+ */
+static struct tcpci_partner_msg *tcpci_partner_alloc_msg_helper(size_t size)
 {
 	struct tcpci_partner_msg *new_msg;
-	size_t size = TCPCI_MSG_HEADER_LEN + TCPCI_MSG_DO_LEN * data_objects;
 
-	new_msg = malloc(sizeof(struct tcpci_partner_msg));
+	new_msg = calloc(1, sizeof(struct tcpci_partner_msg));
 	if (new_msg == NULL) {
 		return NULL;
 	}
 
-	new_msg->msg.buf = malloc(size);
+	new_msg->msg.buf = calloc(1, size);
 	if (new_msg->msg.buf == NULL) {
 		free(new_msg);
 		return NULL;
 	}
 
 	/* Set default message type to SOP */
-	new_msg->msg.type = TCPCI_MSG_SOP;
+	new_msg->msg.sop_type = TCPCI_MSG_SOP;
 	new_msg->msg.cnt = size;
-	new_msg->data_objects = data_objects;
 
 	return new_msg;
 }
 
 /**
+ * @brief Allocate space for a standard (non-extended) message, containing the
+ * specified number of data objects.
+ *
+ * @param num_data_objects Number of 32-bit DOs this message contains, if data
+ * message. Pass 0 if control message.
+ * @return struct tcpci_partner_msg* if successful
+ * @return NULL in case of error
+ */
+static struct tcpci_partner_msg *
+tcpci_partner_alloc_standard_msg(int num_data_objects)
+{
+	struct tcpci_partner_msg *msg = tcpci_partner_alloc_msg_helper(
+		TCPCI_MSG_HEADER_LEN + TCPCI_MSG_DO_LEN * num_data_objects);
+
+	if (msg) {
+		msg->data_objects = num_data_objects;
+	}
+
+	return msg;
+}
+
+/**
+ * @brief Allocate space for an extended message, containing a payload of
+ * specified size
+ *
+ * @param payload_size Size of extended message payload. Do not count either
+ * message header.
+ * @return struct tcpci_partner_msg* if successful
+ * @return NULL in case of error
+ */
+static struct tcpci_partner_msg *
+tcpci_partner_alloc_extended_msg(size_t payload_size)
+{
+	/* Currently, the emulators only support extended messages that can fit
+	 * into a single chunk. Enforce that here.
+	 */
+
+	__ASSERT(payload_size <= PD_MAX_EXTENDED_MSG_CHUNK_LEN,
+		 "Message must fit into a single chunk");
+
+	struct tcpci_partner_msg *msg = tcpci_partner_alloc_msg_helper(
+		TCPCI_MSG_HEADER_LEN + TCPCI_MSG_EXT_HEADER_LEN + payload_size);
+
+	if (msg) {
+		msg->extended = true;
+
+		/* Update the number of data objects with the number of 4-byte
+		 * words in the payload, rounding up. This includes the 2-byte
+		 * Extended Message Header (USB-PD spec Rev 3.0, V1.1,
+		 * section 6.2.1.2.1)
+		 */
+
+		msg->data_objects = DIV_ROUND_UP(
+			payload_size + TCPCI_MSG_EXT_HEADER_LEN, 4);
+	}
+
+	return msg;
+}
+
+/**
  * @brief Alloc and append message to log if collect_msg_log flag is set
  *
  * @param data Pointer to TCPCI partner emulator
@@ -64,10 +138,8 @@ struct tcpci_partner_msg *tcpci_partner_alloc_msg(int data_objects)
  * @return Pointer to message status
  */
 static enum tcpci_emul_tx_status *tcpci_partner_log_msg(
-	struct tcpci_partner_data *data,
-	const struct tcpci_emul_msg *msg,
-	enum tcpci_partner_msg_sender sender,
-	enum tcpci_emul_tx_status status)
+	struct tcpci_partner_data *data, const struct tcpci_emul_msg *msg,
+	enum tcpci_partner_msg_sender sender, enum tcpci_emul_tx_status status)
 {
 	struct tcpci_partner_log_msg *log_msg;
 	int cnt;
@@ -91,7 +163,7 @@ static enum tcpci_emul_tx_status *tcpci_partner_log_msg(
 	}
 
 	log_msg->cnt = cnt;
-	log_msg->sop = msg->type;
+	log_msg->sop = msg->sop_type;
 	log_msg->time = k_uptime_get();
 	log_msg->sender = sender;
 	log_msg->status = status;
@@ -121,12 +193,24 @@ void tcpci_partner_free_msg(struct tcpci_partner_msg *msg)
 void tcpci_partner_set_header(struct tcpci_partner_data *data,
 			      struct tcpci_partner_msg *msg)
 {
+	uint16_t msg_id;
+	uint16_t header;
+
 	/* Header msg id has only 3 bits and wraps around after 8 messages */
-	uint16_t msg_id = data->msg_id & 0x7;
-	uint16_t header = PD_HEADER(msg->type, data->power_role,
-				    data->data_role, msg_id, msg->data_objects,
-				    data->rev, 0 /* ext */);
-	data->msg_id++;
+	if (msg->msg.sop_type == TCPCI_MSG_SOP) {
+		msg_id = data->sop_msg_id & 0x7;
+		header = PD_HEADER(msg->type, data->power_role, data->data_role,
+				   msg_id, msg->data_objects, data->rev,
+				   msg->extended);
+		data->sop_msg_id++;
+	} else if (msg->msg.sop_type == TCPCI_MSG_SOP_PRIME) {
+		msg_id = data->sop_prime_msg_id & 0x7;
+		header = PD_HEADER(msg->type, PD_PLUG_FROM_CABLE, 0, msg_id,
+				   msg->data_objects, data->rev, msg->extended);
+		data->sop_prime_msg_id++;
+	} else {
+		return;
+	}
 
 	msg->msg.buf[1] = (header >> 8) & 0xff;
 	msg->msg.buf[0] = header & 0xff;
@@ -276,8 +360,8 @@ int tcpci_partner_send_msg(struct tcpci_partner_data *data,
 		return ret;
 	}
 
-	prev_msg = SYS_SLIST_PEEK_HEAD_CONTAINER(&data->to_send, prev_msg,
-						 node);
+	prev_msg =
+		SYS_SLIST_PEEK_HEAD_CONTAINER(&data->to_send, prev_msg, node);
 	/* Current message should be sent first */
 	if (prev_msg == NULL || prev_msg->time > msg->time) {
 		sys_slist_prepend(&data->to_send, &msg->node);
@@ -287,7 +371,8 @@ int tcpci_partner_send_msg(struct tcpci_partner_data *data,
 	}
 
 	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&data->to_send, prev_msg, next_msg,
-					  node) {
+					  node)
+	{
 		/*
 		 * If we reach tail or next message should be sent after new
 		 * message, insert new message to the list.
@@ -306,12 +391,11 @@ int tcpci_partner_send_msg(struct tcpci_partner_data *data,
 }
 
 int tcpci_partner_send_control_msg(struct tcpci_partner_data *data,
-				   enum pd_ctrl_msg_type type,
-				   uint64_t delay)
+				   enum pd_ctrl_msg_type type, uint64_t delay)
 {
 	struct tcpci_partner_msg *msg;
 
-	msg = tcpci_partner_alloc_msg(0);
+	msg = tcpci_partner_alloc_standard_msg(0);
 	if (msg == NULL) {
 		return -ENOMEM;
 	}
@@ -329,14 +413,13 @@ int tcpci_partner_send_control_msg(struct tcpci_partner_data *data,
 }
 
 int tcpci_partner_send_data_msg(struct tcpci_partner_data *data,
-				enum pd_data_msg_type type,
-				uint32_t *data_obj, int data_obj_num,
-				uint64_t delay)
+				enum pd_data_msg_type type, uint32_t *data_obj,
+				int data_obj_num, uint64_t delay)
 {
 	struct tcpci_partner_msg *msg;
 	int addr;
 
-	msg = tcpci_partner_alloc_msg(data_obj_num);
+	msg = tcpci_partner_alloc_standard_msg(data_obj_num);
 	if (msg == NULL) {
 		return -ENOMEM;
 	}
@@ -352,6 +435,36 @@ int tcpci_partner_send_data_msg(struct tcpci_partner_data *data,
 	return tcpci_partner_send_msg(data, msg, delay);
 }
 
+/* Note: Cables can send from both SOP' and SOP'', so accept a type argument */
+int tcpci_cable_send_data_msg(struct tcpci_partner_data *data,
+			      enum pd_data_msg_type type, uint32_t *data_obj,
+			      int data_obj_num, enum tcpci_msg_type sop_type,
+			      uint64_t delay)
+{
+	struct tcpci_partner_msg *msg;
+	int addr;
+
+	/* TODO(b/243151272): Add SOP'' support */
+	if (sop_type != TCPCI_MSG_SOP_PRIME)
+		return -EINVAL;
+
+	msg = tcpci_partner_alloc_standard_msg(data_obj_num);
+	if (msg == NULL) {
+		return -ENOMEM;
+	}
+
+	for (int i = 0; i < data_obj_num; i++) {
+		/* Address of given data object in message buffer */
+		addr = TCPCI_MSG_HEADER_LEN + i * TCPCI_MSG_DO_LEN;
+		sys_put_le32(data_obj[i], msg->msg.buf + addr);
+	}
+
+	msg->msg.sop_type = sop_type;
+	msg->type = type;
+
+	return tcpci_partner_send_msg(data, msg, delay);
+}
+
 int tcpci_partner_clear_msg_queue(struct tcpci_partner_data *data)
 {
 	struct tcpci_partner_msg *msg;
@@ -384,8 +497,10 @@ int tcpci_partner_clear_msg_queue(struct tcpci_partner_data *data)
 static void tcpci_partner_common_reset(struct tcpci_partner_data *data)
 {
 	tcpci_partner_clear_msg_queue(data);
-	data->msg_id = 0;
-	data->recv_msg_id = -1;
+	data->sop_msg_id = 0;
+	data->sop_prime_msg_id = 0;
+	data->sop_recv_msg_id = -1;
+	data->sop_prime_recv_msg_id = -1;
 	data->in_soft_reset = false;
 	data->vconn_role = PD_ROLE_VCONN_OFF;
 	tcpci_partner_stop_sender_response_timer(data);
@@ -416,8 +531,8 @@ void tcpci_partner_common_send_hard_reset(struct tcpci_partner_data *data)
 
 	tcpci_partner_common_hard_reset(data);
 
-	msg = tcpci_partner_alloc_msg(0);
-	msg->msg.type = TCPCI_MSG_TX_HARD_RESET;
+	msg = tcpci_partner_alloc_standard_msg(0);
+	msg->msg.sop_type = TCPCI_MSG_TX_HARD_RESET;
 
 	tcpci_partner_send_msg(data, msg, 0);
 }
@@ -425,8 +540,10 @@ void tcpci_partner_common_send_hard_reset(struct tcpci_partner_data *data)
 void tcpci_partner_common_send_soft_reset(struct tcpci_partner_data *data)
 {
 	/* Reset counters */
-	data->msg_id = 0;
-	data->recv_msg_id = -1;
+	data->sop_msg_id = 0;
+	data->sop_prime_msg_id = 0;
+	data->sop_recv_msg_id = -1;
+	data->sop_prime_recv_msg_id = -1;
 
 	tcpci_partner_common_clear_ams_ctrl_msg(data);
 
@@ -437,6 +554,55 @@ void tcpci_partner_common_send_soft_reset(struct tcpci_partner_data *data)
 	tcpci_partner_start_sender_response_timer(data);
 }
 
+int tcpci_partner_send_extended_msg(struct tcpci_partner_data *data,
+				    enum pd_ext_msg_type type, uint64_t delay,
+				    uint8_t *payload, size_t payload_size)
+{
+	struct tcpci_partner_msg *msg;
+
+	msg = tcpci_partner_alloc_extended_msg(payload_size);
+	if (msg == NULL) {
+		return -ENOMEM;
+	}
+
+	msg->type = type;
+
+	/* Apply extended message header. We currently do not support
+	 * multiple chunks.
+	 */
+
+	sys_put_le16(PD_EXT_HEADER(0, 0, payload_size), &msg->msg.buf[2]);
+
+	/* Copy in payload */
+	memcpy(&msg->msg.buf[4], payload, payload_size);
+
+	return tcpci_partner_send_msg(data, msg, delay);
+}
+
+/** Check description in emul_common_tcpci_partner.h */
+void tcpci_partner_common_send_get_battery_capabilities(
+	struct tcpci_partner_data *data, int battery_index)
+{
+	__ASSERT(battery_index >= 0 && battery_index < PD_BATT_MAX,
+		 "Battery index out of range");
+	__ASSERT(data->battery_capabilities.index < 0,
+		 "Get Battery Capabilities request already in progress");
+
+	LOG_INF("Send battery cap request");
+
+	/* Get_Battery_Cap message payload */
+	uint8_t payload[1] = { [0] = battery_index };
+
+	/* Keep track which battery we requested capabilities for */
+	data->battery_capabilities.index = battery_index;
+	int ret = tcpci_partner_send_extended_msg(data, PD_EXT_GET_BATTERY_CAP,
+						  0, payload, sizeof(payload));
+	if (ret) {
+		LOG_ERR("Send battery capacity result: %d", ret);
+	}
+	tcpci_partner_start_sender_response_timer(data);
+}
+
 /**
  * @brief Handler for response timeout
  *
@@ -445,9 +611,8 @@ void tcpci_partner_common_send_soft_reset(struct tcpci_partner_data *data)
 static void tcpci_partner_sender_response_timeout(struct k_work *work)
 {
 	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
-	struct tcpci_partner_data *data =
-		CONTAINER_OF(dwork, struct tcpci_partner_data,
-			     sender_response_timeout);
+	struct tcpci_partner_data *data = CONTAINER_OF(
+		dwork, struct tcpci_partner_data, sender_response_timeout);
 
 	if (k_mutex_lock(&data->transmit_mutex, K_NO_WAIT) != 0) {
 		/*
@@ -520,13 +685,180 @@ tcpci_partner_common_vdm_handler(struct tcpci_partner_data *data,
 						    data->modes_vdos, 0);
 		}
 		return TCPCI_PARTNER_COMMON_MSG_HANDLED;
-	/* TODO(b/219562077): Support DP mode entry. */
+	case CMD_ENTER_MODE:
+		/* Partner emulator only supports entering one mode */
+		if (data->enter_mode_vdos > 0 &&
+		    (PD_VDO_VID(vdm_header) ==
+		     PD_VDO_VID(data->enter_mode_vdm[0]))) {
+			/* Squirrel away the SVID if we're sending ACK */
+			if (PD_VDO_CMDT(data->enter_mode_vdm[0]) ==
+			    CMDT_RSP_ACK)
+				data->entered_svid = PD_VDO_VID(vdm_header);
+
+			tcpci_partner_send_data_msg(data, PD_DATA_VENDOR_DEF,
+						    data->enter_mode_vdm,
+						    data->enter_mode_vdos, 0);
+		}
+		atomic_inc(&data->mode_enter_attempts);
+		return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+	case CMD_EXIT_MODE:
+		/* Only exit a SVID we know we entered */
+		if (PD_VDO_VID(vdm_header) == data->entered_svid) {
+			uint32_t response_vdm_header;
+
+			response_vdm_header =
+				VDO(PD_VDO_VID(vdm_header), true,
+				    VDO_CMDT(CMDT_RSP_ACK) | CMD_EXIT_MODE);
+			tcpci_partner_send_data_msg(data, PD_DATA_VENDOR_DEF,
+						    &response_vdm_header, 1, 0);
+		} else {
+			uint32_t response_vdm_header;
+
+			response_vdm_header =
+				VDO(PD_VDO_VID(vdm_header), true,
+				    VDO_CMDT(CMDT_RSP_NAK) | CMD_EXIT_MODE);
+			tcpci_partner_send_data_msg(data, PD_DATA_VENDOR_DEF,
+						    &response_vdm_header, 1, 0);
+		}
+		data->displayport_configured = false;
+		return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+	case CMD_DP_STATUS:
+		if (data->dp_status_vdos > 0 &&
+		    (PD_VDO_VID(vdm_header) == USB_SID_DISPLAYPORT)) {
+			tcpci_partner_send_data_msg(data, PD_DATA_VENDOR_DEF,
+						    data->dp_status_vdm,
+						    data->dp_status_vdos, 0);
+		}
+		return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+	case CMD_DP_CONFIG:
+		if (data->dp_config_vdos > 0 &&
+		    (PD_VDO_VID(vdm_header) == USB_SID_DISPLAYPORT)) {
+			tcpci_partner_send_data_msg(data, PD_DATA_VENDOR_DEF,
+						    data->dp_config_vdm,
+						    data->dp_config_vdos, 0);
+			data->displayport_configured = true;
+		}
+		return TCPCI_PARTNER_COMMON_MSG_HANDLED;
 	default:
 		/* TCPCI r. 2.0: Ignore unsupported commands. */
 		return TCPCI_PARTNER_COMMON_MSG_HANDLED;
 	}
 }
 
+static enum tcpci_partner_handler_res
+tcpci_partner_common_cable_handler(struct tcpci_partner_data *data,
+				   const struct tcpci_emul_msg *message,
+				   enum tcpci_msg_type sop_type)
+{
+	uint32_t vdm_header = sys_get_le32(message->buf + TCPCI_MSG_HEADER_LEN);
+	uint32_t response_vdm_header;
+	uint16_t header = sys_get_le16(&message->buf[0]);
+
+	/* TODO(b/243151272): Add soft reset support */
+	/* Ensure we are replying to a VDM */
+	if (PD_HEADER_CNT(header) == 0 ||
+	    PD_HEADER_TYPE(header) != PD_DATA_VENDOR_DEF ||
+	    PD_HEADER_EXT(header) != 0)
+		return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED;
+
+	/*
+	 * Ignore any VDMs which are not sent by an initiator.  As a cable, we
+	 * never expect to be the initiator processing ACKs.
+	 * TODO(b/225397796): Validate VDM fields more thoroughly.
+	 */
+	if (PD_VDO_CMDT(vdm_header) != CMDT_INIT || !PD_VDO_SVDM(vdm_header)) {
+		return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+	}
+
+	/* If we have no cable, we must not GoodCRC */
+	if (data->cable == NULL)
+		return TCPCI_PARTNER_COMMON_MSG_NO_GOODCRC;
+
+	/* TODO(b/243151272): Add SOP'' support */
+	if (sop_type == TCPCI_MSG_SOP_PRIME_PRIME) {
+		return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED;
+	}
+
+	switch (PD_VDO_CMD(vdm_header)) {
+	case CMD_DISCOVER_IDENT:
+		if (data->cable->identity_vdos > 0) {
+			tcpci_cable_send_data_msg(data, PD_DATA_VENDOR_DEF,
+						  data->cable->identity_vdm,
+						  data->cable->identity_vdos,
+						  TCPCI_MSG_SOP_PRIME, 0);
+			return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+		}
+		/* A cable with no identity shouldn't GoodCRC */
+		return TCPCI_PARTNER_COMMON_MSG_NO_GOODCRC;
+	default:
+		/*
+		 * Cable must support VDMs, so generate a NAK on unfamiliar
+		 * commands
+		 */
+		response_vdm_header =
+			VDO(PD_VDO_VID(vdm_header), true,
+			    VDO_CMDT(CMDT_RSP_NAK) | PD_VDO_CMD(vdm_header));
+		tcpci_cable_send_data_msg(data, PD_DATA_VENDOR_DEF,
+					  &response_vdm_header, 1, sop_type, 0);
+
+		return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+	}
+}
+
+/**
+ * @brief Handle a received Battery Capability message from the TCPC. Save the
+ *        contents to the emulator data struct for analysis.
+ *
+ * @param data Emulator state
+ * @param message Received PD message
+ * @return enum tcpci_partner_handler_res
+ */
+static enum tcpci_partner_handler_res
+tcpci_partner_common_battery_capability_handler(
+	struct tcpci_partner_data *data, const struct tcpci_emul_msg *message)
+{
+	uint16_t header = sys_get_le16(&message->buf[0]);
+	uint16_t ext_header = sys_get_le16(&message->buf[2]);
+
+	/* Validate message header */
+	__ASSERT(PD_HEADER_TYPE(header) == PD_EXT_BATTERY_CAP,
+		 "wrong message type");
+	__ASSERT(PD_EXT_HEADER_DATA_SIZE(ext_header) == 9,
+		 "Data size mismatch");
+
+	int index = data->battery_capabilities.index;
+
+	data->battery_capabilities.index = -1;
+
+	if (index < 0) {
+		LOG_ERR("Received a Battery Capability message but it was "
+			"never requested");
+		return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED;
+	}
+
+	__ASSERT(index < PD_BATT_MAX, "Battery index out of range");
+
+	data->battery_capabilities.bcdb[index] = (struct pd_bcdb){
+		.vid = sys_get_le16(&message->buf[4]),
+		.pid = sys_get_le16(&message->buf[6]),
+		.design_cap = sys_get_le16(&message->buf[8]),
+		.last_full_charge_cap = sys_get_le16(&message->buf[10]),
+		.battery_type = message->buf[12],
+	};
+
+	data->battery_capabilities.have_response[index] = true;
+
+	LOG_INF("Saved data for battery index (%d): vid=%04x, pid=%04x, "
+		"cap=%u, last_cap=%u, type=%02x",
+		index, data->battery_capabilities.bcdb[index].vid,
+		data->battery_capabilities.bcdb[index].pid,
+		data->battery_capabilities.bcdb[index].design_cap,
+		data->battery_capabilities.bcdb[index].last_full_charge_cap,
+		data->battery_capabilities.bcdb[index].battery_type);
+
+	return TCPCI_PARTNER_COMMON_MSG_HANDLED;
+}
+
 static void tcpci_partner_common_set_vconn(struct tcpci_partner_data *data,
 					   enum pd_vconn_role role)
 {
@@ -641,9 +973,9 @@ tcpi_partner_common_handle_accept(struct tcpci_partner_data *data)
  * @param TCPCI_PARTNER_COMMON_MSG_HARD_RESET Message was handled by sending
  *                                            hard reset
  */
-static enum tcpci_partner_handler_res tcpci_partner_common_sop_msg_handler(
-	struct tcpci_partner_data *data,
-	const struct tcpci_emul_msg *tx_msg)
+static enum tcpci_partner_handler_res
+tcpci_partner_common_sop_msg_handler(struct tcpci_partner_data *data,
+				     const struct tcpci_emul_msg *tx_msg)
 {
 	struct tcpci_partner_extension *ext;
 	uint16_t header;
@@ -655,15 +987,41 @@ static enum tcpci_partner_handler_res tcpci_partner_common_sop_msg_handler(
 	header = sys_get_le16(tx_msg->buf);
 	msg_type = PD_HEADER_TYPE(header);
 
-	if (PD_HEADER_ID(header) == data->recv_msg_id &&
+	if (PD_HEADER_ID(header) == data->sop_recv_msg_id &&
 	    msg_type != PD_CTRL_SOFT_RESET) {
 		/* Repeated message mark as handled */
 		return TCPCI_PARTNER_COMMON_MSG_HANDLED;
 	}
+	data->sop_recv_msg_id = PD_HEADER_ID(header);
+
+	if (PD_HEADER_EXT(header)) {
+		/* Extended message */
+
+		if (PD_HEADER_REV(header) < PD_REV30) {
+			LOG_ERR("Received extended message but current PD rev "
+				"(0x%x) does not support them.",
+				PD_HEADER_REV(header));
+			return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED;
+		}
+
+		switch (PD_HEADER_TYPE(header)) {
+		case PD_EXT_GET_BATTERY_CAP:
+			/* Not implemented */
+			LOG_INF("Got PD_EXT_GET_BATTERY_CAP");
+			return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED;
+		case PD_EXT_BATTERY_CAP:
+			/* Received a Battery Capabilities response */
+			LOG_INF("Got PD_EXT_BATTERY_CAP");
 
-	data->recv_msg_id = PD_HEADER_ID(header);
+			return tcpci_partner_common_battery_capability_handler(
+				data, tx_msg);
+		default:
+			return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED;
+		}
+	}
 
 	if (PD_HEADER_CNT(header)) {
+		/* Data message */
 		switch (PD_HEADER_TYPE(header)) {
 		case PD_DATA_VENDOR_DEF:
 			return tcpci_partner_common_vdm_handler(data, tx_msg);
@@ -681,7 +1039,7 @@ static enum tcpci_partner_handler_res tcpci_partner_common_sop_msg_handler(
 	/* Handle control message */
 	switch (PD_HEADER_TYPE(header)) {
 	case PD_CTRL_SOFT_RESET:
-		data->msg_id = 0;
+		data->sop_msg_id = 0;
 		tcpci_partner_send_control_msg(data, PD_CTRL_ACCEPT, 0);
 
 		for (ext = data->extensions; ext != NULL; ext = ext->next) {
@@ -781,6 +1139,9 @@ void tcpci_partner_common_disconnect(struct tcpci_partner_data *data)
 	tcpci_partner_clear_msg_queue(data);
 	tcpci_partner_stop_sender_response_timer(data);
 	data->tcpci_emul = NULL;
+	data->displayport_configured = false;
+	data->entered_svid = 0;
+	atomic_clear(&data->mode_enter_attempts);
 }
 
 int tcpci_partner_common_enable_pd_logging(struct tcpci_partner_data *data,
@@ -816,8 +1177,10 @@ static char *tcpci_partner_sender_names[] = {
  *
  * @return Number of written bytes
  */
-static __printf_like(4, 5) int tcpci_partner_print_to_buf(
-	char *buf, const int buf_len, int start, const char *fmt, ...)
+static __printf_like(4, 5) int tcpci_partner_print_to_buf(char *buf,
+							  const int buf_len,
+							  int start,
+							  const char *fmt, ...)
 {
 	va_list ap;
 	int ret;
@@ -853,7 +1216,8 @@ void tcpci_partner_common_print_logged_msgs(struct tcpci_partner_data *data)
 	chars_in += tcpci_partner_print_to_buf(buf, buf_len, chars_in,
 					       "===PD messages log:\n");
 
-	SYS_SLIST_FOR_EACH_CONTAINER(&data->msg_log, msg, node) {
+	SYS_SLIST_FOR_EACH_CONTAINER(&data->msg_log, msg, node)
+	{
 		/*
 		 * If there is too many messages to keep them in local buffer,
 		 * accept possibility of lines interleaving on console and print
@@ -863,27 +1227,27 @@ void tcpci_partner_common_print_logged_msgs(struct tcpci_partner_data *data)
 			LOG_PRINTK("%s", buf);
 			chars_in = 0;
 		}
-		chars_in += tcpci_partner_print_to_buf(buf, buf_len, chars_in,
-				"\tAt %lld Msg SOP %d from %s (status 0x%x):\n",
-				msg->time, msg->sop,
-				tcpci_partner_sender_names[msg->sender],
-				msg->status);
+		chars_in += tcpci_partner_print_to_buf(
+			buf, buf_len, chars_in,
+			"\tAt %lld Msg SOP %d from %s (status 0x%x):\n",
+			msg->time, msg->sop,
+			tcpci_partner_sender_names[msg->sender], msg->status);
 		header = sys_get_le16(msg->buf);
+		chars_in += tcpci_partner_print_to_buf(
+			buf, buf_len, chars_in,
+			"\t\text=%d;cnt=%d;id=%d;pr=%d;dr=%d;rev=%d;type=%d\n",
+			PD_HEADER_EXT(header), PD_HEADER_CNT(header),
+			PD_HEADER_ID(header), PD_HEADER_PROLE(header),
+			PD_HEADER_DROLE(header), PD_HEADER_REV(header),
+			PD_HEADER_TYPE(header));
 		chars_in += tcpci_partner_print_to_buf(buf, buf_len, chars_in,
-				"\t\text=%d;cnt=%d;id=%d;pr=%d;dr=%d;rev=%d;type=%d\n",
-				PD_HEADER_EXT(header), PD_HEADER_CNT(header),
-				PD_HEADER_ID(header), PD_HEADER_PROLE(header),
-				PD_HEADER_DROLE(header), PD_HEADER_REV(header),
-				PD_HEADER_TYPE(header));
-		chars_in += tcpci_partner_print_to_buf(buf, buf_len, chars_in,
-				"\t\t");
+						       "\t\t");
 		for (i = 0; i < msg->cnt; i++) {
 			chars_in += tcpci_partner_print_to_buf(
-					buf, buf_len, chars_in,
-					"%02x ", msg->buf[i]);
+				buf, buf_len, chars_in, "%02x ", msg->buf[i]);
 		}
 		chars_in += tcpci_partner_print_to_buf(buf, buf_len, chars_in,
-				"\n");
+						       "\n");
 	}
 	LOG_PRINTK("%s===\n", buf);
 
@@ -920,11 +1284,10 @@ void tcpci_partner_common_set_ams_ctrl_msg(struct tcpci_partner_data *data,
 					   enum pd_ctrl_msg_type msg_type)
 {
 	/* Make sure we handle one CTRL request at a time */
-	zassert_equal(
-		data->cur_ams_ctrl_req, PD_CTRL_INVALID,
-		"More than one CTRL msg handled in parallel"
-		" cur_ams_ctrl_req=%d, msg_type=%d",
-		data->cur_ams_ctrl_req, msg_type);
+	zassert_equal(data->cur_ams_ctrl_req, PD_CTRL_INVALID,
+		      "More than one CTRL msg handled in parallel"
+		      " cur_ams_ctrl_req=%d, msg_type=%d",
+		      data->cur_ams_ctrl_req, msg_type);
 	data->cur_ams_ctrl_req = msg_type;
 }
 
@@ -955,7 +1318,6 @@ void tcpci_partner_received_msg_status(struct tcpci_partner_data *data,
 		LOG_WRN("Changing status of received message more than once");
 	}
 	*data->received_msg_status = status;
-
 }
 
 /**
@@ -971,8 +1333,7 @@ void tcpci_partner_received_msg_status(struct tcpci_partner_data *data,
 static void tcpci_partner_transmit_op(const struct emul *emul,
 				      const struct tcpci_emul_partner_ops *ops,
 				      const struct tcpci_emul_msg *tx_msg,
-				      enum tcpci_msg_type type,
-				      int retry)
+				      enum tcpci_msg_type type, int retry)
 {
 	struct tcpci_partner_data *data =
 		CONTAINER_OF(ops, struct tcpci_partner_data, ops);
@@ -980,9 +1341,8 @@ static void tcpci_partner_transmit_op(const struct emul *emul,
 	struct tcpci_partner_extension *ext;
 	int ret;
 
-	data->received_msg_status =
-		tcpci_partner_log_msg(data, tx_msg, TCPCI_PARTNER_SENDER_TCPM,
-				      TCPCI_EMUL_TX_UNKNOWN);
+	data->received_msg_status = tcpci_partner_log_msg(
+		data, tx_msg, TCPCI_PARTNER_SENDER_TCPM, TCPCI_EMUL_TX_UNKNOWN);
 
 	ret = k_mutex_lock(&data->transmit_mutex, K_FOREVER);
 	if (ret) {
@@ -1002,8 +1362,8 @@ static void tcpci_partner_transmit_op(const struct emul *emul,
 		goto message_handled;
 	}
 
-	/* Skip handling of none SOP messages */
-	if (type != TCPCI_MSG_SOP) {
+	/* Skip handling of non-SOP/SOP'/SOP'' messages */
+	if (type > TCPCI_MSG_SOP_PRIME_PRIME) {
 		/* Never send GoodCRC for cable reset */
 		if (data->send_goodcrc && type != TCPCI_MSG_CABLE_RESET) {
 			tcpci_partner_received_msg_status(
@@ -1013,10 +1373,22 @@ static void tcpci_partner_transmit_op(const struct emul *emul,
 	}
 
 	/* Call common SOP handler */
-	processed = tcpci_partner_common_sop_msg_handler(data, tx_msg);
-	/* Always send GoodCRC for messages handled by common handler */
-	if (data->send_goodcrc ||
-	    processed != TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED) {
+	if (type == TCPCI_MSG_SOP) {
+		processed = tcpci_partner_common_sop_msg_handler(data, tx_msg);
+	} else {
+		processed =
+			tcpci_partner_common_cable_handler(data, tx_msg, type);
+	}
+	if (processed == TCPCI_PARTNER_COMMON_MSG_NO_GOODCRC) {
+		/*
+		 * Fail message send if common handler knows message shouldn't
+		 * transit successfully.
+		 */
+		tcpci_partner_received_msg_status(data, TCPCI_EMUL_TX_FAILED);
+		goto message_handled;
+	} else if (data->send_goodcrc ||
+		   processed != TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED) {
+		/* Always send GoodCRC for messages handled by common handler */
 		tcpci_partner_received_msg_status(data, TCPCI_EMUL_TX_SUCCESS);
 	}
 
@@ -1036,8 +1408,7 @@ static void tcpci_partner_transmit_op(const struct emul *emul,
 	}
 
 	/* Send reject for not handled messages (PD rev 2.0) */
-	tcpci_partner_send_control_msg(data,
-				       PD_CTRL_REJECT, 0);
+	tcpci_partner_send_control_msg(data, PD_CTRL_REJECT, 0);
 
 message_handled:
 	k_mutex_unlock(&data->transmit_mutex);
@@ -1051,14 +1422,13 @@ message_handled:
  * @param ops Pointer to partner operations structure
  * @param rx_msg Message that was consumed by TCPM
  */
-static void tcpci_partner_rx_consumed_op(
-		const struct emul *emul,
-		const struct tcpci_emul_partner_ops *ops,
-		const struct tcpci_emul_msg *rx_msg)
+static void
+tcpci_partner_rx_consumed_op(const struct emul *emul,
+			     const struct tcpci_emul_partner_ops *ops,
+			     const struct tcpci_emul_msg *rx_msg)
 {
-	struct tcpci_partner_msg *msg = CONTAINER_OF(rx_msg,
-						     struct tcpci_partner_msg,
-						     msg);
+	struct tcpci_partner_msg *msg =
+		CONTAINER_OF(rx_msg, struct tcpci_partner_msg, msg);
 
 	tcpci_partner_free_msg(msg);
 }
@@ -1069,9 +1439,9 @@ static void tcpci_partner_rx_consumed_op(
  * @param emul Pointer to TCPCI emulator
  * @param ops Pointer to partner operations structure
  */
-static void tcpci_partner_disconnect_op(
-		const struct emul *emul,
-		const struct tcpci_emul_partner_ops *ops)
+static void
+tcpci_partner_disconnect_op(const struct emul *emul,
+			    const struct tcpci_emul_partner_ops *ops)
 {
 	struct tcpci_partner_data *data =
 		CONTAINER_OF(ops, struct tcpci_partner_data, ops);
@@ -1113,9 +1483,20 @@ int tcpci_partner_connect_to_tcpci(struct tcpci_partner_data *data,
 		data->tcpci_emul = NULL;
 	}
 
+	/* Clear any received battery capability info */
+	tcpci_partner_reset_battery_capability_state(data);
+
 	return ret;
 }
 
+void tcpci_partner_reset_battery_capability_state(
+	struct tcpci_partner_data *data)
+{
+	memset(&data->battery_capabilities, 0,
+	       sizeof(data->battery_capabilities));
+	data->battery_capabilities.index = -1;
+}
+
 void tcpci_partner_init(struct tcpci_partner_data *data, enum pd_rev_type rev)
 {
 	k_timer_init(&data->delayed_send, tcpci_partner_delayed_send_timer,
@@ -1144,4 +1525,13 @@ void tcpci_partner_init(struct tcpci_partner_data *data, enum pd_rev_type rev)
 	data->ops.rx_consumed = tcpci_partner_rx_consumed_op;
 	data->ops.control_change = NULL;
 	data->ops.disconnect = tcpci_partner_disconnect_op;
+	data->displayport_configured = false;
+	data->entered_svid = 0;
+	atomic_clear(&data->mode_enter_attempts);
+
+	/* Reset the data structure used to store battery capability responses
+	 */
+	tcpci_partner_reset_battery_capability_state(data);
+
+	data->cable = NULL;
 }
diff --git a/zephyr/emul/tcpc/emul_tcpci_partner_drp.c b/zephyr/emul/tcpc/emul_tcpci_partner_drp.c
index 6c3abdac78..277957282d 100644
--- a/zephyr/emul/tcpc/emul_tcpci_partner_drp.c
+++ b/zephyr/emul/tcpc/emul_tcpci_partner_drp.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,7 +7,7 @@
 LOG_MODULE_REGISTER(tcpci_drp_emul, CONFIG_TCPCI_EMUL_LOG_LEVEL);
 
 #include <zephyr/sys/byteorder.h>
-#include <zephyr/zephyr.h>
+#include <zephyr/kernel.h>
 
 #include "common.h"
 #include "emul/tcpc/emul_tcpci.h"
@@ -28,10 +28,10 @@ LOG_MODULE_REGISTER(tcpci_drp_emul, CONFIG_TCPCI_EMUL_LOG_LEVEL);
  * @return TCPCI_PARTNER_COMMON_MSG_HANDLED Message was handled
  * @return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED Message wasn't handled
  */
-static enum tcpci_partner_handler_res tcpci_drp_emul_handle_sop_msg(
-	struct tcpci_partner_extension *ext,
-	struct tcpci_partner_data *common_data,
-	const struct tcpci_emul_msg *msg)
+static enum tcpci_partner_handler_res
+tcpci_drp_emul_handle_sop_msg(struct tcpci_partner_extension *ext,
+			      struct tcpci_partner_data *common_data,
+			      const struct tcpci_emul_msg *msg)
 {
 	struct tcpci_drp_emul_data *data =
 		CONTAINER_OF(ext, struct tcpci_drp_emul_data, ext);
@@ -46,9 +46,8 @@ static enum tcpci_partner_handler_res tcpci_drp_emul_handle_sop_msg(
 		case PD_DATA_REQUEST:
 			if (common_data->power_role == PD_ROLE_SINK) {
 				/* As sink we shouldn't accept request */
-				tcpci_partner_send_control_msg(common_data,
-							       PD_CTRL_REJECT,
-							       0);
+				tcpci_partner_send_control_msg(
+					common_data, PD_CTRL_REJECT, 0);
 				return TCPCI_PARTNER_COMMON_MSG_HANDLED;
 			}
 			/* As source, let source handler to handle this */
@@ -66,8 +65,7 @@ static enum tcpci_partner_handler_res tcpci_drp_emul_handle_sop_msg(
 		switch (PD_HEADER_TYPE(header)) {
 		case PD_CTRL_PR_SWAP:
 			tcpci_partner_send_control_msg(common_data,
-						       PD_CTRL_ACCEPT,
-						       0);
+						       PD_CTRL_ACCEPT, 0);
 			data->in_pwr_swap = true;
 			return TCPCI_PARTNER_COMMON_MSG_HANDLED;
 		case PD_CTRL_PS_RDY:
@@ -77,8 +75,8 @@ static enum tcpci_partner_handler_res tcpci_drp_emul_handle_sop_msg(
 			data->in_pwr_swap = false;
 
 			/* Reset counters */
-			common_data->msg_id = 0;
-			common_data->recv_msg_id = -1;
+			common_data->sop_msg_id = 0;
+			common_data->sop_recv_msg_id = -1;
 
 			/* Perform power role swap */
 			if (common_data->power_role == PD_ROLE_SOURCE) {
@@ -140,12 +138,12 @@ struct tcpci_partner_extension_ops tcpci_drp_emul_ops = {
 	.connect = NULL,
 };
 
-struct tcpci_partner_extension *tcpci_drp_emul_init(
-	struct tcpci_drp_emul_data *data,
-	struct tcpci_partner_data *common_data,
-	enum pd_power_role power_role,
-	struct tcpci_partner_extension *src_ext,
-	struct tcpci_partner_extension *snk_ext)
+struct tcpci_partner_extension *
+tcpci_drp_emul_init(struct tcpci_drp_emul_data *data,
+		    struct tcpci_partner_data *common_data,
+		    enum pd_power_role power_role,
+		    struct tcpci_partner_extension *src_ext,
+		    struct tcpci_partner_extension *snk_ext)
 {
 	struct tcpci_partner_extension *drp_ext = &data->ext;
 	struct tcpci_src_emul_data *src_data =
diff --git a/zephyr/emul/tcpc/emul_tcpci_partner_faulty_snk.c b/zephyr/emul/tcpc/emul_tcpci_partner_faulty_ext.c
index c71b4bc833..fc4cd06b82 100644
--- a/zephyr/emul/tcpc/emul_tcpci_partner_faulty_snk.c
+++ b/zephyr/emul/tcpc/emul_tcpci_partner_faulty_ext.c
@@ -1,35 +1,34 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include <zephyr/logging/log.h>
-LOG_MODULE_REGISTER(tcpci_faulty_snk_emul, CONFIG_TCPCI_EMUL_LOG_LEVEL);
+LOG_MODULE_REGISTER(tcpci_faulty_ext, CONFIG_TCPCI_EMUL_LOG_LEVEL);
 
 #include <zephyr/sys/byteorder.h>
-#include <zephyr/zephyr.h>
+#include <zephyr/kernel.h>
 
 #include "common.h"
 #include "emul/tcpc/emul_tcpci.h"
 #include "emul/tcpc/emul_tcpci_partner_common.h"
-#include "emul/tcpc/emul_tcpci_partner_faulty_snk.h"
-#include "emul/tcpc/emul_tcpci_partner_snk.h"
+#include "emul/tcpc/emul_tcpci_partner_faulty_ext.h"
 #include "usb_pd.h"
 
 /**
  * @brief Reduce number of times to repeat action. If count reaches zero, action
  *        is removed from queue.
  *
- * @param data Pointer to USB-C malfunctioning sink device extension data
+ * @param data Pointer to USB-C malfunctioning device extension data
  */
-static void tcpci_faulty_snk_emul_reduce_action_count(
-	struct tcpci_faulty_snk_emul_data *data)
+static void
+tcpci_faulty_ext_reduce_action_count(struct tcpci_faulty_ext_data *data)
 {
-	struct tcpci_faulty_snk_action *action;
+	struct tcpci_faulty_ext_action *action;
 
 	action = k_fifo_peek_head(&data->action_list);
 
-	if (action->count == TCPCI_FAULTY_SNK_INFINITE_ACTION) {
+	if (action->count == TCPCI_FAULTY_EXT_INFINITE_ACTION) {
 		return;
 	}
 
@@ -42,15 +41,13 @@ static void tcpci_faulty_snk_emul_reduce_action_count(
 	k_fifo_get(&data->action_list, K_FOREVER);
 }
 
-void tcpci_faulty_snk_emul_append_action(
-	struct tcpci_faulty_snk_emul_data *data,
-	struct tcpci_faulty_snk_action *action)
+void tcpci_faulty_ext_append_action(struct tcpci_faulty_ext_data *data,
+				    struct tcpci_faulty_ext_action *action)
 {
 	k_fifo_put(&data->action_list, action);
 }
 
-void tcpci_faulty_snk_emul_clear_actions_list(
-	struct tcpci_faulty_snk_emul_data *data)
+void tcpci_faulty_ext_clear_actions_list(struct tcpci_faulty_ext_data *data)
 {
 	while (!k_fifo_is_empty(&data->action_list)) {
 		k_fifo_get(&data->action_list, K_FOREVER);
@@ -60,21 +57,21 @@ void tcpci_faulty_snk_emul_clear_actions_list(
 /**
  * @brief Handle SOP messages as TCPCI malfunctioning device
  *
- * @param ext Pointer to USB-C malfunctioning sink device emulator extension
+ * @param ext Pointer to USB-C malfunctioning device emulator extension
  * @param common_data Pointer to USB-C device emulator common data
  * @param msg Pointer to received message
  *
  * @return TCPCI_PARTNER_COMMON_MSG_HANDLED Message was handled
  * @return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED Message wasn't handled
  */
-static enum tcpci_partner_handler_res tcpci_faulty_snk_emul_handle_sop_msg(
-	struct tcpci_partner_extension *ext,
-	struct tcpci_partner_data *common_data,
-	const struct tcpci_emul_msg *msg)
+static enum tcpci_partner_handler_res
+tcpci_faulty_ext_handle_sop_msg(struct tcpci_partner_extension *ext,
+				struct tcpci_partner_data *common_data,
+				const struct tcpci_emul_msg *msg)
 {
-	struct tcpci_faulty_snk_emul_data *data =
-		CONTAINER_OF(ext, struct tcpci_faulty_snk_emul_data, ext);
-	struct tcpci_faulty_snk_action *action;
+	struct tcpci_faulty_ext_data *data =
+		CONTAINER_OF(ext, struct tcpci_faulty_ext_data, ext);
+	struct tcpci_faulty_ext_action *action;
 	uint16_t header;
 
 	action = k_fifo_peek_head(&data->action_list);
@@ -93,30 +90,29 @@ static enum tcpci_partner_handler_res tcpci_faulty_snk_emul_handle_sop_msg(
 		switch (PD_HEADER_TYPE(header)) {
 		case PD_DATA_SOURCE_CAP:
 			if (action->action_mask &
-			    TCPCI_FAULTY_SNK_FAIL_SRC_CAP) {
+			    TCPCI_FAULTY_EXT_FAIL_SRC_CAP) {
 				/* Fail is not sending GoodCRC from partner */
 				tcpci_partner_received_msg_status(
 					common_data, TCPCI_EMUL_TX_FAILED);
-				tcpci_faulty_snk_emul_reduce_action_count(data);
+				tcpci_faulty_ext_reduce_action_count(data);
 				return TCPCI_PARTNER_COMMON_MSG_HANDLED;
 			}
 			if (action->action_mask &
-			    TCPCI_FAULTY_SNK_DISCARD_SRC_CAP) {
+			    TCPCI_FAULTY_EXT_DISCARD_SRC_CAP) {
 				/* Discard because partner is sending message */
 				tcpci_partner_received_msg_status(
 					common_data, TCPCI_EMUL_TX_DISCARDED);
 				tcpci_partner_send_control_msg(
-						common_data,
-						PD_CTRL_ACCEPT, 0);
-				tcpci_faulty_snk_emul_reduce_action_count(data);
+					common_data, PD_CTRL_ACCEPT, 0);
+				tcpci_faulty_ext_reduce_action_count(data);
 				return TCPCI_PARTNER_COMMON_MSG_HANDLED;
 			}
 			if (action->action_mask &
-			    TCPCI_FAULTY_SNK_IGNORE_SRC_CAP) {
+			    TCPCI_FAULTY_EXT_IGNORE_SRC_CAP) {
 				/* Send only GoodCRC */
 				tcpci_partner_received_msg_status(
 					common_data, TCPCI_EMUL_TX_SUCCESS);
-				tcpci_faulty_snk_emul_reduce_action_count(data);
+				tcpci_faulty_ext_reduce_action_count(data);
 				return TCPCI_PARTNER_COMMON_MSG_HANDLED;
 			}
 		}
@@ -131,27 +127,27 @@ static enum tcpci_partner_handler_res tcpci_faulty_snk_emul_handle_sop_msg(
 	return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED;
 }
 
-/** USB-C malfunctioning sink device extension callbacks */
-struct tcpci_partner_extension_ops tcpci_faulty_snk_emul_ops = {
-	.sop_msg_handler = tcpci_faulty_snk_emul_handle_sop_msg,
+/** USB-C malfunctioning device extension callbacks */
+struct tcpci_partner_extension_ops tcpci_faulty_ext_ops = {
+	.sop_msg_handler = tcpci_faulty_ext_handle_sop_msg,
 	.hard_reset = NULL,
 	.soft_reset = NULL,
 	.disconnect = NULL,
 	.connect = NULL,
 };
 
-struct tcpci_partner_extension *tcpci_faulty_snk_emul_init(
-	struct tcpci_faulty_snk_emul_data *data,
-	struct tcpci_partner_data *common_data,
-	struct tcpci_partner_extension *ext)
+struct tcpci_partner_extension *
+tcpci_faulty_ext_init(struct tcpci_faulty_ext_data *data,
+		      struct tcpci_partner_data *common_data,
+		      struct tcpci_partner_extension *ext)
 {
-	struct tcpci_partner_extension *snk_ext = &data->ext;
+	struct tcpci_partner_extension *faulty_ext = &data->ext;
 
 	k_fifo_init(&data->action_list);
 	common_data->send_goodcrc = false;
 
-	snk_ext->next = ext;
-	snk_ext->ops = &tcpci_faulty_snk_emul_ops;
+	faulty_ext->next = ext;
+	faulty_ext->ops = &tcpci_faulty_ext_ops;
 
-	return snk_ext;
+	return faulty_ext;
 }
diff --git a/zephyr/emul/tcpc/emul_tcpci_partner_snk.c b/zephyr/emul/tcpc/emul_tcpci_partner_snk.c
index 7ae3662170..8d0fe1fa1e 100644
--- a/zephyr/emul/tcpc/emul_tcpci_partner_snk.c
+++ b/zephyr/emul/tcpc/emul_tcpci_partner_snk.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,7 +7,7 @@
 LOG_MODULE_REGISTER(tcpci_snk_emul, CONFIG_TCPCI_EMUL_LOG_LEVEL);
 
 #include <zephyr/sys/byteorder.h>
-#include <zephyr/zephyr.h>
+#include <zephyr/kernel.h>
 
 #include "common.h"
 #include "emul/tcpc/emul_tcpci.h"
@@ -16,9 +16,9 @@ LOG_MODULE_REGISTER(tcpci_snk_emul, CONFIG_TCPCI_EMUL_LOG_LEVEL);
 #include "usb_pd.h"
 
 /** Length of PDO, RDO and BIST request object in SOP message in bytes */
-#define TCPCI_MSG_DO_LEN	4
+#define TCPCI_MSG_DO_LEN 4
 /** Length of header in SOP message in bytes  */
-#define TCPCI_MSG_HEADER_LEN	2
+#define TCPCI_MSG_HEADER_LEN 2
 
 /**
  * @brief Get number of PDOs that will be present in sink capability message
@@ -51,18 +51,17 @@ static int tcpci_snk_emul_num_of_pdos(struct tcpci_snk_emul_data *data)
  * @return -ENOMEM when there is no free memory for message
  * @return -EINVAL on TCPCI emulator add RX message error
  */
-static int tcpci_snk_emul_send_capability_msg(
-	struct tcpci_snk_emul_data *data,
-	struct tcpci_partner_data *common_data,
-	uint64_t delay)
+static int
+tcpci_snk_emul_send_capability_msg(struct tcpci_snk_emul_data *data,
+				   struct tcpci_partner_data *common_data,
+				   uint64_t delay)
 {
 	int pdos;
 
 	/* Find number of PDOs */
 	pdos = tcpci_snk_emul_num_of_pdos(data);
 
-	return tcpci_partner_send_data_msg(common_data,
-					   PD_DATA_SINK_CAP,
+	return tcpci_partner_send_data_msg(common_data, PD_DATA_SINK_CAP,
 					   data->pdo, pdos, delay);
 }
 
@@ -95,8 +94,8 @@ static int tcpci_snk_emul_are_pdos_complementary(uint32_t src_pdo,
 			/* Voltage doesn't match */
 			return -1;
 		}
-		missing_current = PDO_FIXED_CURRENT(snk_pdo) -
-				  PDO_FIXED_CURRENT(src_pdo);
+		missing_current =
+			PDO_FIXED_CURRENT(snk_pdo) - PDO_FIXED_CURRENT(src_pdo);
 		break;
 	case PDO_TYPE_BATTERY:
 		if ((PDO_BATT_MIN_VOLTAGE(snk_pdo) <
@@ -111,8 +110,8 @@ static int tcpci_snk_emul_are_pdos_complementary(uint32_t src_pdo,
 		 * = P / V * 5 [A] = P / V * 500 * 10[mA]
 		 */
 		missing_current = (PDO_BATT_MAX_POWER(snk_pdo) -
-				   PDO_BATT_MAX_POWER(src_pdo)) * 500 /
-				  PDO_BATT_MAX_VOLTAGE(src_pdo);
+				   PDO_BATT_MAX_POWER(src_pdo)) *
+				  500 / PDO_BATT_MAX_VOLTAGE(src_pdo);
 		break;
 	case PDO_TYPE_VARIABLE:
 		if ((PDO_VAR_MIN_VOLTAGE(snk_pdo) <
@@ -147,8 +146,8 @@ static int tcpci_snk_emul_are_pdos_complementary(uint32_t src_pdo,
  * @return PDO on success
  * @return 0 when there is no PDO of given index in message
  */
-static uint32_t tcpci_snk_emul_get_pdo_from_cap(
-			const struct tcpci_emul_msg *msg, int pdo_num)
+static uint32_t
+tcpci_snk_emul_get_pdo_from_cap(const struct tcpci_emul_msg *msg, int pdo_num)
 {
 	int addr;
 
@@ -240,10 +239,10 @@ static uint32_t tcpci_snk_emul_create_rdo(uint32_t src_pdo, uint32_t snk_pdo,
  * @param common_data Pointer to common TCPCI partner data
  * @param msg Source capability message
  */
-static void tcpci_snk_emul_handle_source_cap(
-	struct tcpci_snk_emul_data *data,
-	struct tcpci_partner_data *common_data,
-	const struct tcpci_emul_msg *msg)
+static void
+tcpci_snk_emul_handle_source_cap(struct tcpci_snk_emul_data *data,
+				 struct tcpci_partner_data *common_data,
+				 const struct tcpci_emul_msg *msg)
 {
 	uint32_t rdo = 0;
 	uint32_t pdo;
@@ -263,17 +262,22 @@ static void tcpci_snk_emul_handle_source_cap(
 	snk_pdos = tcpci_snk_emul_num_of_pdos(data);
 	src_pdos = (msg->cnt - TCPCI_MSG_HEADER_LEN) / TCPCI_MSG_DO_LEN;
 
+	/*
+	 * Store the 5V fixed PDO for future reference (required to be index 0
+	 * by spec)
+	 */
+	data->last_5v_source_cap = tcpci_snk_emul_get_pdo_from_cap(msg, 0);
+
 	/* Find if any source PDO satisfy any sink PDO */
 	for (int pdo_num = 0; pdo_num < src_pdos; pdo_num++) {
 		pdo = tcpci_snk_emul_get_pdo_from_cap(msg, pdo_num);
 
 		for (int i = skip_first_pdo; i < snk_pdos; i++) {
 			missing_current = tcpci_snk_emul_are_pdos_complementary(
-						pdo, data->pdo[i]);
+				pdo, data->pdo[i]);
 			if (missing_current == 0) {
-				rdo = tcpci_snk_emul_create_rdo(pdo,
-								data->pdo[i],
-								pdo_num + 1);
+				rdo = tcpci_snk_emul_create_rdo(
+					pdo, data->pdo[i], pdo_num + 1);
 				break;
 			}
 		}
@@ -350,6 +354,11 @@ void tcpci_snk_emul_clear_alert_received(struct tcpci_snk_emul_data *data)
 	data->alert_received = false;
 }
 
+void tcpci_snk_emul_clear_last_5v_cap(struct tcpci_snk_emul_data *data)
+{
+	data->last_5v_source_cap = 0;
+}
+
 /**
  * @brief Handle SOP messages as TCPCI sink device. It handles source cap,
  *        get sink cap and ping messages. Accept, Reject and PS_RDY are handled
@@ -363,10 +372,10 @@ void tcpci_snk_emul_clear_alert_received(struct tcpci_snk_emul_data *data)
  * @param TCPCI_PARTNER_COMMON_MSG_HANDLED Message was handled
  * @param TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED Message wasn't handled
  */
-static enum tcpci_partner_handler_res tcpci_snk_emul_handle_sop_msg(
-	struct tcpci_partner_extension *ext,
-	struct tcpci_partner_data *common_data,
-	const struct tcpci_emul_msg *msg)
+static enum tcpci_partner_handler_res
+tcpci_snk_emul_handle_sop_msg(struct tcpci_partner_extension *ext,
+			      struct tcpci_partner_data *common_data,
+			      const struct tcpci_emul_msg *msg)
 {
 	struct tcpci_snk_emul_data *data =
 		CONTAINER_OF(ext, struct tcpci_snk_emul_data, ext);
@@ -404,20 +413,19 @@ static enum tcpci_partner_handler_res tcpci_snk_emul_handle_sop_msg(
 			__ASSERT(data->wait_for_ps_rdy,
 				 "Unexpected PS RDY message");
 			tcpci_snk_emul_stop_partner_transition_timer(
-							data, common_data);
+				data, common_data);
 			data->pd_completed = true;
 			return TCPCI_PARTNER_COMMON_MSG_HANDLED;
 		case PD_CTRL_REJECT:
 			tcpci_partner_stop_sender_response_timer(common_data);
 			/* Request rejected. Ask for capabilities again. */
-			tcpci_partner_send_control_msg(common_data,
-						       PD_CTRL_GET_SOURCE_CAP,
-						       0);
+			tcpci_partner_send_control_msg(
+				common_data, PD_CTRL_GET_SOURCE_CAP, 0);
 			return TCPCI_PARTNER_COMMON_MSG_HANDLED;
 		case PD_CTRL_ACCEPT:
 			tcpci_partner_stop_sender_response_timer(common_data);
 			tcpci_snk_emul_start_partner_transition_timer(
-							data, common_data);
+				data, common_data);
 			return TCPCI_PARTNER_COMMON_MSG_HANDLED;
 		default:
 			return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED;
@@ -459,9 +467,9 @@ static void tcpci_snk_emul_hard_reset(struct tcpci_partner_extension *ext,
  * @return 0 on success
  * @return negative on TCPCI connect error
  */
-static int tcpci_snk_emul_connect_to_tcpci(
-	struct tcpci_partner_extension *ext,
-	struct tcpci_partner_data *common_data)
+static int
+tcpci_snk_emul_connect_to_tcpci(struct tcpci_partner_extension *ext,
+				struct tcpci_partner_data *common_data)
 {
 	struct tcpci_snk_emul_data *data =
 		CONTAINER_OF(ext, struct tcpci_snk_emul_data, ext);
@@ -489,10 +497,10 @@ struct tcpci_partner_extension_ops tcpci_snk_emul_ops = {
 	.connect = tcpci_snk_emul_connect_to_tcpci,
 };
 
-struct tcpci_partner_extension *tcpci_snk_emul_init(
-	struct tcpci_snk_emul_data *data,
-	struct tcpci_partner_data *common_data,
-	struct tcpci_partner_extension *ext)
+struct tcpci_partner_extension *
+tcpci_snk_emul_init(struct tcpci_snk_emul_data *data,
+		    struct tcpci_partner_data *common_data,
+		    struct tcpci_partner_extension *ext)
 {
 	struct tcpci_partner_extension *snk_ext = &data->ext;
 
diff --git a/zephyr/emul/tcpc/emul_tcpci_partner_src.c b/zephyr/emul/tcpc/emul_tcpci_partner_src.c
index 8efc4327c8..c81d69c25f 100644
--- a/zephyr/emul/tcpc/emul_tcpci_partner_src.c
+++ b/zephyr/emul/tcpc/emul_tcpci_partner_src.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,7 +7,7 @@
 LOG_MODULE_REGISTER(tcpci_src_emul, CONFIG_TCPCI_EMUL_LOG_LEVEL);
 
 #include <zephyr/sys/byteorder.h>
-#include <zephyr/zephyr.h>
+#include <zephyr/kernel.h>
 
 #include "common.h"
 #include "emul/tcpc/emul_tcpci_partner_common.h"
@@ -35,11 +35,11 @@ static void tcpci_src_emul_start_source_capability_custom_time(
  *
  * @param data Pointer to USB-C source device emulator data
  */
-static void tcpci_src_emul_start_source_capability_timer(
-	struct tcpci_src_emul_data *data)
+static void
+tcpci_src_emul_start_source_capability_timer(struct tcpci_src_emul_data *data)
 {
 	tcpci_src_emul_start_source_capability_custom_time(
-			data, TCPCI_SOURCE_CAPABILITY_TIMEOUT);
+		data, TCPCI_SOURCE_CAPABILITY_TIMEOUT);
 }
 
 /**
@@ -47,8 +47,8 @@ static void tcpci_src_emul_start_source_capability_timer(
  *
  * @param data Pointer to USB-C source device emulator data
  */
-static void tcpci_src_emul_stop_source_capability_timer(
-	struct tcpci_src_emul_data *data)
+static void
+tcpci_src_emul_stop_source_capability_timer(struct tcpci_src_emul_data *data)
 {
 	k_work_cancel_delayable(&data->source_capability_timeout);
 }
@@ -66,21 +66,19 @@ int tcpci_src_emul_send_capability_msg(struct tcpci_src_emul_data *data,
 		}
 	}
 
-	return tcpci_partner_send_data_msg(common_data,
-					   PD_DATA_SOURCE_CAP,
+	return tcpci_partner_send_data_msg(common_data, PD_DATA_SOURCE_CAP,
 					   data->pdo, pdos, delay);
 }
 
 int tcpci_src_emul_send_capability_msg_with_timer(
 	struct tcpci_src_emul_data *data,
-	struct tcpci_partner_data *common_data,
-	uint64_t delay)
+	struct tcpci_partner_data *common_data, uint64_t delay)
 {
 	int ret;
 
 	if (delay > 0) {
 		tcpci_src_emul_start_source_capability_custom_time(
-							data, K_MSEC(delay));
+			data, K_MSEC(delay));
 		return TCPCI_EMUL_TX_SUCCESS;
 	}
 
@@ -119,10 +117,10 @@ void tcpci_src_emul_clear_status_received(struct tcpci_src_emul_data *data)
  * @param TCPCI_PARTNER_COMMON_MSG_HANDLED Message was handled
  * @param TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED Message wasn't handled
  */
-static enum tcpci_partner_handler_res tcpci_src_emul_handle_sop_msg(
-	struct tcpci_partner_extension *ext,
-	struct tcpci_partner_data *common_data,
-	const struct tcpci_emul_msg *msg)
+static enum tcpci_partner_handler_res
+tcpci_src_emul_handle_sop_msg(struct tcpci_partner_extension *ext,
+			      struct tcpci_partner_data *common_data,
+			      const struct tcpci_emul_msg *msg)
 {
 	struct tcpci_src_emul_data *data =
 		CONTAINER_OF(ext, struct tcpci_src_emul_data, ext);
@@ -171,9 +169,8 @@ static enum tcpci_partner_handler_res tcpci_src_emul_handle_sop_msg(
 			return TCPCI_PARTNER_COMMON_MSG_HANDLED;
 		case PD_CTRL_GET_REVISION:
 			rmdo = 0x31000000;
-			tcpci_partner_send_data_msg(common_data,
-						    PD_DATA_REVISION,
-						    &rmdo, 1, 0);
+			tcpci_partner_send_data_msg(
+				common_data, PD_DATA_REVISION, &rmdo, 1, 0);
 			return TCPCI_PARTNER_COMMON_MSG_HANDLED;
 		default:
 			return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED;
@@ -189,9 +186,8 @@ static enum tcpci_partner_handler_res tcpci_src_emul_handle_sop_msg(
 static void tcpci_src_emul_source_capability_timeout(struct k_work *work)
 {
 	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
-	struct tcpci_src_emul_data *data =
-		CONTAINER_OF(dwork, struct tcpci_src_emul_data,
-			     source_capability_timeout);
+	struct tcpci_src_emul_data *data = CONTAINER_OF(
+		dwork, struct tcpci_src_emul_data, source_capability_timeout);
 	struct tcpci_partner_data *common_data = data->common_data;
 
 	if (k_mutex_lock(&common_data->transmit_mutex, K_NO_WAIT) != 0) {
@@ -278,9 +274,9 @@ static void tcpci_src_emul_disconnect(struct tcpci_partner_extension *ext,
  * @return 0 on success
  * @return negative on TCPCI connect error
  */
-static int tcpci_src_emul_connect_to_tcpci(
-	struct tcpci_partner_extension *ext,
-	struct tcpci_partner_data *common_data)
+static int
+tcpci_src_emul_connect_to_tcpci(struct tcpci_partner_extension *ext,
+				struct tcpci_partner_data *common_data)
 {
 	struct tcpci_src_emul_data *data =
 		CONTAINER_OF(ext, struct tcpci_src_emul_data, ext);
@@ -298,15 +294,14 @@ static int tcpci_src_emul_connect_to_tcpci(
 	 * capabilities, but it is permit. Timeout is obligatory for power swap.
 	 */
 	tcpci_src_emul_send_capability_msg_with_timer(
-					data, common_data,
-					TCPCI_SWAP_SOURCE_START_TIMEOUT_MS);
+		data, common_data, TCPCI_SWAP_SOURCE_START_TIMEOUT_MS);
 
 	return 0;
 }
 
-#define PDO_FIXED_FLAGS_MASK						\
-	(PDO_FIXED_DUAL_ROLE | PDO_FIXED_UNCONSTRAINED |		\
-	 PDO_FIXED_COMM_CAP | PDO_FIXED_DATA_SWAP)
+#define PDO_FIXED_FLAGS_MASK                                                  \
+	(PDO_FIXED_DUAL_ROLE | PDO_FIXED_UNCONSTRAINED | PDO_FIXED_COMM_CAP | \
+	 PDO_FIXED_DATA_SWAP)
 
 enum check_pdos_res tcpci_src_emul_check_pdos(struct tcpci_src_emul_data *data)
 {
@@ -411,10 +406,10 @@ struct tcpci_partner_extension_ops tcpci_src_emul_ops = {
 	.connect = tcpci_src_emul_connect_to_tcpci,
 };
 
-struct tcpci_partner_extension *tcpci_src_emul_init(
-	struct tcpci_src_emul_data *data,
-	struct tcpci_partner_data *common_data,
-	struct tcpci_partner_extension *ext)
+struct tcpci_partner_extension *
+tcpci_src_emul_init(struct tcpci_src_emul_data *data,
+		    struct tcpci_partner_data *common_data,
+		    struct tcpci_partner_extension *ext)
 {
 	struct tcpci_partner_extension *src_ext = &data->ext;
 
diff --git a/zephyr/fake/CMakeLists.txt b/zephyr/fake/CMakeLists.txt
new file mode 100644
index 0000000000..6b9f16bc20
--- /dev/null
+++ b/zephyr/fake/CMakeLists.txt
@@ -0,0 +1,7 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+zephyr_library_sources_ifdef(CONFIG_SYSTEM_FAKE system_fake.c)
+
+cros_ec_library_include_directories(include)
diff --git a/zephyr/fake/Kconfig b/zephyr/fake/Kconfig
new file mode 100644
index 0000000000..c5f6fef669
--- /dev/null
+++ b/zephyr/fake/Kconfig
@@ -0,0 +1,11 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config SYSTEM_FAKE
+	bool "Use a fake system module"
+	help
+	  This provides a fake implementation of some of the hooks used by
+	  common/system.c so that EC reboots can be faked.
+
+	  It should only be included in tests.
diff --git a/zephyr/fake/include/system_fake.h b/zephyr/fake/include/system_fake.h
new file mode 100644
index 0000000000..b80624e289
--- /dev/null
+++ b/zephyr/fake/include/system_fake.h
@@ -0,0 +1,23 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef ZEPHYR_FAKE_SYSTEM_FAKE_H
+#define ZEPHYR_FAKE_SYSTEM_FAKE_H
+
+#include <setjmp.h>
+
+#include "ec_commands.h"
+
+/**
+ * @brief Set the current image copy.
+ */
+void system_set_shrspi_image_copy(enum ec_image new_image_copy);
+
+/**
+ * @brief Set the fake environment
+ */
+void system_fake_setenv(jmp_buf *env);
+
+#endif /* ZEPHYR_FAKE_SYSTEM_FAKE_H */
diff --git a/zephyr/fake/system_fake.c b/zephyr/fake/system_fake.c
new file mode 100644
index 0000000000..75beb62b23
--- /dev/null
+++ b/zephyr/fake/system_fake.c
@@ -0,0 +1,46 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <setjmp.h>
+
+#include "system.h"
+#include "system_fake.h"
+
+static enum ec_image shrspi_image_copy = EC_IMAGE_RO;
+
+/* setjmp environment to use for reboot (NULL if none) */
+static jmp_buf *jump_env;
+
+void system_fake_setenv(jmp_buf *env)
+{
+	jump_env = env;
+}
+
+void system_jump_to_booter(void)
+{
+	if (jump_env)
+		longjmp(*jump_env, 1);
+}
+
+uint32_t system_get_lfw_address(void)
+{
+	uint32_t jump_addr = (uint32_t)system_jump_to_booter;
+
+	return jump_addr;
+}
+
+enum ec_image system_get_shrspi_image_copy(void)
+{
+	return shrspi_image_copy;
+}
+
+void system_set_shrspi_image_copy(enum ec_image new_image_copy)
+{
+	shrspi_image_copy = new_image_copy;
+}
+
+void system_set_image_copy(enum ec_image copy)
+{
+}
diff --git a/zephyr/firmware_builder.py b/zephyr/firmware_builder.py
index 21767d635a..436760361a 100755
--- a/zephyr/firmware_builder.py
+++ b/zephyr/firmware_builder.py
@@ -1,6 +1,6 @@
 #!/usr/bin/env python3
 # -*- coding: utf-8 -*-
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 """Build and test all of the Zephyr boards.
@@ -12,73 +12,120 @@ import argparse
 import multiprocessing
 import pathlib
 import re
+import shlex
 import subprocess
 import sys
 
-from google.protobuf import json_format  # pylint: disable=import-error
 import zmake.project
-
 from chromite.api.gen_sdk.chromite.api import firmware_pb2
+from google.protobuf import json_format  # pylint: disable=import-error
 
-
-DEFAULT_BUNDLE_DIRECTORY = '/tmp/artifact_bundles'
-DEFAULT_BUNDLE_METADATA_FILE = '/tmp/artifact_bundle_metadata'
+DEFAULT_BUNDLE_DIRECTORY = "/tmp/artifact_bundles"
+DEFAULT_BUNDLE_METADATA_FILE = "/tmp/artifact_bundle_metadata"
+
+# Boards that we want to track the coverage of our own files specifically.
+SPECIAL_BOARDS = ["herobrine"]
+
+
+def log_cmd(cmd):
+    """Log subprocess command."""
+    print(" ".join(shlex.quote(str(x)) for x in cmd))
+    sys.stdout.flush()
+
+
+def run_twister(platform_ec, code_coverage=False, extra_args=None):
+    """Build the tests using twister."""
+    cmd = [
+        platform_ec / "twister",
+        "--outdir",
+        platform_ec / "twister-out",
+        "-v",
+        "-i",
+        "-p",
+        "native_posix",
+        "-p",
+        "unit_testing",
+        "--no-upload-cros-rdb",
+    ]
+
+    if extra_args:
+        cmd.extend(extra_args)
+
+    if code_coverage:
+        # Tell Twister to collect coverage data. We must specify an explicit platform
+        # type in this case, as well.
+        cmd.extend(
+            [
+                "--coverage",
+            ]
+        )
+    log_cmd(cmd)
+    subprocess.run(cmd, check=True, cwd=platform_ec, stdin=subprocess.DEVNULL)
 
 
 def build(opts):
     """Builds all Zephyr firmware targets"""
     metric_list = firmware_pb2.FwBuildMetricList()
 
-    cmd = ['zmake', '-D', 'build', '-a']
+    zephyr_dir = pathlib.Path(__file__).parent.resolve()
+    platform_ec = zephyr_dir.parent
+    subprocess.run(
+        [platform_ec / "util" / "check_clang_format.py"],
+        check=True,
+        cwd=platform_ec,
+        stdin=subprocess.DEVNULL,
+    )
+
+    cmd = ["zmake", "-D", "build", "-a"]
     if opts.code_coverage:
-        cmd.append('--coverage')
-    subprocess.run(cmd, cwd=pathlib.Path(__file__).parent, check=True)
+        cmd.append("--coverage")
+    log_cmd(cmd)
+    subprocess.run(cmd, cwd=zephyr_dir, check=True, stdin=subprocess.DEVNULL)
     if not opts.code_coverage:
-        zephyr_dir = pathlib.Path(__file__).parent
-        platform_ec = zephyr_dir.resolve().parent
         for project in zmake.project.find_projects(zephyr_dir).values():
             if project.config.is_test:
                 continue
             build_dir = (
-                platform_ec / 'build' / 'zephyr' / project.config.project_name
+                platform_ec / "build" / "zephyr" / project.config.project_name
             )
             metric = metric_list.value.add()
             metric.target_name = project.config.project_name
             metric.platform_name = project.config.zephyr_board
             for (variant, _) in project.iter_builds():
-                build_log = build_dir / f'build-{variant}' / 'build.log'
+                build_log = build_dir / f"build-{variant}" / "build.log"
                 parse_buildlog(build_log, metric, variant.upper())
-    with open(opts.metrics, 'w') as file:
+    with open(opts.metrics, "w") as file:
         file.write(json_format.MessageToJson(metric_list))
-    return 0
+
+    run_twister(platform_ec, opts.code_coverage, ["--build-only"])
 
 
 UNITS = {
-    'B': 1,
-    'KB': 1024,
-    'MB': 1024 * 1024,
-    'GB': 1024 * 1024 * 1024,
+    "B": 1,
+    "KB": 1024,
+    "MB": 1024 * 1024,
+    "GB": 1024 * 1024 * 1024,
 }
 
 
 def parse_buildlog(filename, metric, variant):
     """Parse the build.log generated by zmake to find the size of the image."""
-    with open(filename, 'r') as infile:
+    with open(filename, "r") as infile:
         # Skip over all lines until the memory report is found
         while True:
             line = infile.readline()
             if not line:
                 return
-            if line.startswith('Memory region'):
+            if line.startswith("Memory region"):
                 break
 
         for line in infile.readlines():
             # Skip any lines that are not part of the report
-            if not line.startswith(' '):
+            if not line.startswith(" "):
                 continue
             parts = line.split()
             fw_section = metric.fw_section.add()
-            fw_section.region = variant + '_' + parts[0][:-1]
+            fw_section.region = variant + "_" + parts[0][:-1]
             fw_section.used = int(parts[1]) * UNITS[parts[2]]
             fw_section.total = int(parts[3]) * UNITS[parts[4]]
             fw_section.track_on_gerrit = False
@@ -112,7 +159,7 @@ def write_metadata(opts, info):
     bundle_metadata_file = (
         opts.metadata if opts.metadata else DEFAULT_BUNDLE_METADATA_FILE
     )
-    with open(bundle_metadata_file, 'w') as file:
+    with open(bundle_metadata_file, "w") as file:
         file.write(json_format.MessageToJson(info))
 
 
@@ -121,18 +168,29 @@ def bundle_coverage(opts):
     info = firmware_pb2.FirmwareArtifactInfo()
     info.bcs_version_info.version_string = opts.bcs_version
     bundle_dir = get_bundle_dir(opts)
-    zephyr_dir = pathlib.Path(__file__).parent
-    platform_ec = zephyr_dir.resolve().parent
-    build_dir = platform_ec / 'build' / 'zephyr'
-    tarball_name = 'coverage.tbz2'
+    zephyr_dir = pathlib.Path(__file__).parent.resolve()
+    platform_ec = zephyr_dir.parent
+    build_dir = platform_ec / "build" / "zephyr"
+    tarball_name = "coverage.tbz2"
     tarball_path = bundle_dir / tarball_name
-    cmd = ['tar', 'cvfj', tarball_path, 'lcov.info']
-    subprocess.run(cmd, cwd=build_dir, check=True)
+    cmd = ["tar", "cvfj", tarball_path, "lcov.info"]
+    log_cmd(cmd)
+    subprocess.run(cmd, cwd=build_dir, check=True, stdin=subprocess.DEVNULL)
     meta = info.objects.add()
     meta.file_name = tarball_name
     meta.lcov_info.type = (
         firmware_pb2.FirmwareArtifactInfo.LcovTarballInfo.LcovType.LCOV
     )
+    (bundle_dir / "html").mkdir(exist_ok=True)
+    cmd = ["mv", "lcov_rpt"]
+    for board in SPECIAL_BOARDS:
+        cmd.append(board + "_rpt")
+    cmd.append(bundle_dir / "html/")
+    log_cmd(cmd)
+    subprocess.run(cmd, cwd=build_dir, check=True, stdin=subprocess.DEVNULL)
+    meta = info.objects.add()
+    meta.file_name = "html"
+    meta.coverage_html.SetInParent()
 
     write_metadata(opts, info)
 
@@ -142,19 +200,22 @@ def bundle_firmware(opts):
     info = firmware_pb2.FirmwareArtifactInfo()
     info.bcs_version_info.version_string = opts.bcs_version
     bundle_dir = get_bundle_dir(opts)
-    zephyr_dir = pathlib.Path(__file__).parent
-    platform_ec = zephyr_dir.resolve().parent
+    zephyr_dir = pathlib.Path(__file__).parent.resolve()
+    platform_ec = zephyr_dir.parent
     for project in zmake.project.find_projects(zephyr_dir).values():
         if project.config.is_test:
             continue
         build_dir = (
-            platform_ec / 'build' / 'zephyr' / project.config.project_name
+            platform_ec / "build" / "zephyr" / project.config.project_name
         )
-        artifacts_dir = build_dir / 'output'
-        tarball_name = f'{project.config.project_name}.firmware.tbz2'
+        artifacts_dir = build_dir / "output"
+        tarball_name = f"{project.config.project_name}.firmware.tbz2"
         tarball_path = bundle_dir.joinpath(tarball_name)
-        cmd = ['tar', 'cvfj', tarball_path, '.']
-        subprocess.run(cmd, cwd=artifacts_dir, check=True)
+        cmd = ["tar", "cvfj", tarball_path, "."]
+        log_cmd(cmd)
+        subprocess.run(
+            cmd, cwd=artifacts_dir, check=True, stdin=subprocess.DEVNULL
+        )
         meta = info.objects.add()
         meta.file_name = tarball_name
         meta.tarball_info.type = (
@@ -174,50 +235,296 @@ def test(opts):
 
     # Run zmake tests to ensure we have a fully working zmake before
     # proceeding.
-    subprocess.run([zephyr_dir / 'zmake' / 'run_tests.sh'], check=True)
+    subprocess.run(
+        [zephyr_dir / "zmake" / "run_tests.sh"],
+        check=True,
+        cwd=zephyr_dir,
+        stdin=subprocess.DEVNULL,
+    )
 
-    # Run formatting checks on all BUILD.py files.
-    config_files = zephyr_dir.rglob('**/BUILD.py')
-    subprocess.run(['black', '--diff', '--check', *config_files], check=True)
+    # Twister-based tests
+    platform_ec = zephyr_dir.parent
+    third_party = platform_ec.parent.parent / "third_party"
+    run_twister(platform_ec, opts.code_coverage, ["--test-only"])
 
-    cmd = ['zmake', '-D', 'test', '-a', '--no-rebuild']
     if opts.code_coverage:
-        cmd.append('--coverage')
-    ret = subprocess.run(cmd, check=True).returncode
-    if ret:
-        return ret
-    if opts.code_coverage:
-        platform_ec = zephyr_dir.parent
-        build_dir = platform_ec / 'build' / 'zephyr'
+        build_dir = platform_ec / "build" / "zephyr"
         # Merge lcov files here because bundle failures are "infra" failures.
+        output = subprocess.run(
+            [
+                "/usr/bin/lcov",
+                "--summary",
+                platform_ec / "twister-out" / "coverage.info",
+            ],
+            cwd=zephyr_dir,
+            check=True,
+            stdout=subprocess.PIPE,
+            universal_newlines=True,
+            stdin=subprocess.DEVNULL,
+        ).stdout
+        _extract_lcov_summary("EC_ZEPHYR_TESTS", metrics, output)
+
+        cmd = ["make", "test-coverage", f"-j{opts.cpus}"]
+        log_cmd(cmd)
+        subprocess.run(
+            cmd, cwd=platform_ec, check=True, stdin=subprocess.DEVNULL
+        )
+
+        output = subprocess.run(
+            [
+                "/usr/bin/lcov",
+                "--summary",
+                platform_ec / "build/coverage/lcov.info",
+            ],
+            cwd=zephyr_dir,
+            check=True,
+            stdout=subprocess.PIPE,
+            universal_newlines=True,
+            stdin=subprocess.DEVNULL,
+        ).stdout
+        _extract_lcov_summary("EC_LEGACY_TESTS", metrics, output)
+
         cmd = [
-            '/usr/bin/lcov',
-            '-o',
-            build_dir / 'lcov.info',
-            '--rc',
-            'lcov_branch_coverage=1',
-            '-a',
-            build_dir / 'all_tests.info',
-            '-a',
-            build_dir / 'all_builds.info',
+            "/usr/bin/lcov",
+            "-o",
+            build_dir / "all_tests.info",
+            "--rc",
+            "lcov_branch_coverage=1",
+            "-a",
+            platform_ec / "build/coverage/lcov.info",
+            "-a",
+            platform_ec / "twister-out" / "coverage.info",
         ]
+        log_cmd(cmd)
         output = subprocess.run(
-            cmd, cwd=pathlib.Path(__file__).parent, check=True,
-            stdout=subprocess.PIPE, universal_newlines=True).stdout
-        _extract_lcov_summary('EC_ZEPHYR_MERGED', metrics, output)
+            cmd,
+            cwd=zephyr_dir,
+            check=True,
+            stdout=subprocess.PIPE,
+            universal_newlines=True,
+            stdin=subprocess.DEVNULL,
+        ).stdout
+        _extract_lcov_summary("ALL_TESTS", metrics, output)
 
+        cmd = [
+            "/usr/bin/lcov",
+            "-o",
+            build_dir / "zephyr_merged.info",
+            "--rc",
+            "lcov_branch_coverage=1",
+            "-a",
+            build_dir / "all_builds.info",
+            "-a",
+            build_dir / "all_tests.info",
+        ]
+        log_cmd(cmd)
         output = subprocess.run(
-            ['/usr/bin/lcov', '--summary', build_dir / 'all_tests.info'],
-            cwd=pathlib.Path(__file__).parent, check=True,
-            stdout=subprocess.PIPE, universal_newlines=True).stdout
-        _extract_lcov_summary('EC_ZEPHYR_TESTS', metrics, output)
+            cmd,
+            cwd=zephyr_dir,
+            check=True,
+            stdout=subprocess.PIPE,
+            universal_newlines=True,
+            stdin=subprocess.DEVNULL,
+        ).stdout
+        _extract_lcov_summary("EC_ZEPHYR_MERGED", metrics, output)
 
-    with open(opts.metrics, 'w') as file:
-        file.write(json_format.MessageToJson(metrics))
-    return 0
+        cmd = [
+            "/usr/bin/lcov",
+            "-o",
+            build_dir / "lcov_unfiltered.info",
+            "--rc",
+            "lcov_branch_coverage=1",
+            "-a",
+            build_dir / "zephyr_merged.info",
+            "-a",
+            platform_ec / "build/coverage/lcov.info",
+        ]
+        log_cmd(cmd)
+        subprocess.run(
+            cmd,
+            cwd=zephyr_dir,
+            check=True,
+            stdin=subprocess.DEVNULL,
+        )
+
+        test_patterns = [
+            platform_ec / "test/**",
+            platform_ec / "private/fingerprint/google-fpalg/mcutest/**",
+            zephyr_dir / "test/**",
+            zephyr_dir / "emul/**",
+            zephyr_dir / "mock/**",
+            third_party / "zephyr/main/subsys/emul/**",
+            third_party / "zephyr/main/subsys/testsuite/**",
+        ]
+
+        generated_and_system_patterns = [
+            platform_ec / "build/**",
+            platform_ec / "twister-out*/**",
+            "/usr/include/**",
+            "/usr/lib/**",
+        ]
+
+        cmd = [
+            "/usr/bin/lcov",
+            "-o",
+            build_dir / "lcov.info",
+            "--rc",
+            "lcov_branch_coverage=1",
+            "-r",
+            build_dir / "lcov_unfiltered.info",
+        ] + generated_and_system_patterns
+        log_cmd(cmd)
+        output = subprocess.run(
+            cmd,
+            cwd=zephyr_dir,
+            check=True,
+            stdout=subprocess.PIPE,
+            universal_newlines=True,
+            stdin=subprocess.DEVNULL,
+        ).stdout
+        _extract_lcov_summary("ALL_MERGED", metrics, output)
+
+        # Create an info file without any test code, just for the metric.
+        cmd = [
+            "/usr/bin/lcov",
+            "-o",
+            build_dir / "lcov_no_tests.info",
+            "--rc",
+            "lcov_branch_coverage=1",
+            "-r",
+            build_dir / "lcov.info",
+        ] + test_patterns
+        log_cmd(cmd)
+        output = subprocess.run(
+            cmd,
+            cwd=zephyr_dir,
+            check=True,
+            stdout=subprocess.PIPE,
+            universal_newlines=True,
+            stdin=subprocess.DEVNULL,
+        ).stdout
+        _extract_lcov_summary("ALL_FILTERED", metrics, output)
+
+        subprocess.run(
+            [
+                "/usr/bin/genhtml",
+                "--branch-coverage",
+                "-q",
+                "-o",
+                build_dir / "lcov_rpt",
+                "-t",
+                "All boards and tests merged",
+                "-s",
+                build_dir / "lcov.info",
+            ],
+            cwd=zephyr_dir,
+            check=True,
+            stdin=subprocess.DEVNULL,
+        )
+
+        for board in SPECIAL_BOARDS:
+            # Merge board coverage with tests
+            cmd = [
+                "/usr/bin/lcov",
+                "-o",
+                build_dir / (board + "_merged.info"),
+                "--rc",
+                "lcov_branch_coverage=1",
+                "-a",
+                build_dir / "all_tests.info",
+                "-a",
+                build_dir / board / "output/zephyr.info",
+            ]
+            log_cmd(cmd)
+            subprocess.run(
+                cmd,
+                cwd=zephyr_dir,
+                check=True,
+                stdin=subprocess.DEVNULL,
+            )
+            # Exclude file patterns we don't want
+            cmd = (
+                [
+                    "/usr/bin/lcov",
+                    "-o",
+                    build_dir / (board + "_filtered.info"),
+                    "--rc",
+                    "lcov_branch_coverage=1",
+                    "-r",
+                    build_dir / (board + "_merged.info"),
+                    # Exclude third_party code (specifically zephyr)
+                    third_party / "**",
+                    # These are questionable, but they are essentially untestable
+                    zephyr_dir / "drivers/**",
+                    zephyr_dir / "include/drivers/**",
+                    zephyr_dir / "projects/**",
+                    zephyr_dir / "shim/chip/**",
+                    zephyr_dir / "shim/chip/npcx/npcx_monitor/**",
+                    zephyr_dir / "shim/core/**",
+                ]
+                + generated_and_system_patterns
+                + test_patterns
+            )
+            log_cmd(cmd)
+            subprocess.run(
+                cmd,
+                cwd=zephyr_dir,
+                check=True,
+                stdin=subprocess.DEVNULL,
+            )
+            # Then keep only files present in the board build
+            filenames = set()
+            with open(
+                build_dir / board / "output/zephyr.info", "r"
+            ) as board_cov:
+                for line in board_cov.readlines():
+                    if line.startswith("SF:"):
+                        filenames.add(line[3:-1])
+            cmd = [
+                "/usr/bin/lcov",
+                "-o",
+                build_dir / (board + "_final.info"),
+                "--rc",
+                "lcov_branch_coverage=1",
+                "-e",
+                build_dir / (board + "_filtered.info"),
+            ] + list(filenames)
+            log_cmd(cmd)
+            output = subprocess.run(
+                cmd,
+                cwd=zephyr_dir,
+                check=True,
+                stdout=subprocess.PIPE,
+                universal_newlines=True,
+                stdin=subprocess.DEVNULL,
+            ).stdout
+            _extract_lcov_summary(f"BOARD_{board}".upper(), metrics, output)
+            subprocess.run(
+                [
+                    "/usr/bin/genhtml",
+                    "--branch-coverage",
+                    "-q",
+                    "-o",
+                    build_dir / (board + "_rpt"),
+                    "-t",
+                    f"{board} ec code only",
+                    "-s",
+                    build_dir / (board + "_final.info"),
+                ],
+                cwd=zephyr_dir,
+                check=True,
+                stdin=subprocess.DEVNULL,
+            )
+
+    with open(opts.metrics, "w") as file:
+        file.write(json_format.MessageToJson(metrics))  # type: ignore
+
+
+COVERAGE_RE = re.compile(
+    r"lines\.*: *([0-9\.]+)% \(([0-9]+) of ([0-9]+) lines\)"
+)
 
 
-COVERAGE_RE = re.compile(r'lines\.*: *([0-9\.]+)% \(([0-9]+) of ([0-9]+) lines\)')
 def _extract_lcov_summary(name, metrics, output):
     re_match = COVERAGE_RE.search(output)
     if re_match:
@@ -227,16 +534,18 @@ def _extract_lcov_summary(name, metrics, output):
         metric.covered_lines = int(re_match.group(2))
         metric.total_lines = int(re_match.group(3))
 
+
 def main(args):
     """Builds and tests all of the Zephyr targets and reports build metrics"""
     opts = parse_args(args)
 
-    if not hasattr(opts, 'func'):
-        print('Must select a valid sub command!')
+    if not hasattr(opts, "func"):
+        print("Must select a valid sub command!")
         return -1
 
     # Run selected sub command function
-    return opts.func(opts)
+    opts.func(opts)
+    return 0
 
 
 def parse_args(args):
@@ -244,70 +553,70 @@ def parse_args(args):
     parser = argparse.ArgumentParser(description=__doc__)
 
     parser.add_argument(
-        '--cpus',
+        "--cpus",
         default=multiprocessing.cpu_count(),
-        help='The number of cores to use.',
+        help="The number of cores to use.",
     )
 
     parser.add_argument(
-        '--metrics',
-        dest='metrics',
+        "--metrics",
+        dest="metrics",
         required=True,
-        help='File to write the json-encoded MetricsList proto message.',
+        help="File to write the json-encoded MetricsList proto message.",
     )
 
     parser.add_argument(
-        '--metadata',
+        "--metadata",
         required=False,
         help=(
-            'Full pathname for the file in which to write build artifact '
-            'metadata.'
+            "Full pathname for the file in which to write build artifact "
+            "metadata."
         ),
     )
 
     parser.add_argument(
-        '--output-dir',
+        "--output-dir",
         required=False,
         help=(
-            'Full pathname for the directory in which to bundle build '
-            'artifacts.'
+            "Full pathname for the directory in which to bundle build "
+            "artifacts."
         ),
     )
 
     parser.add_argument(
-        '--code-coverage',
+        "--code-coverage",
         required=False,
-        action='store_true',
-        help='Build host-based unit tests for code coverage.',
+        action="store_true",
+        help="Build host-based unit tests for code coverage.",
     )
 
     parser.add_argument(
-        '--bcs-version',
-        dest='bcs_version',
-        default='',
+        "--bcs-version",
+        dest="bcs_version",
+        default="",
         required=False,
         # TODO(b/180008931): make this required=True.
-        help='BCS version to include in metadata.',
+        help="BCS version to include in metadata.",
     )
 
     # Would make this required=True, but not available until 3.7
     sub_cmds = parser.add_subparsers()
 
-    build_cmd = sub_cmds.add_parser('build', help='Builds all firmware targets')
+    build_cmd = sub_cmds.add_parser("build", help="Builds all firmware targets")
     build_cmd.set_defaults(func=build)
 
     build_cmd = sub_cmds.add_parser(
-        'bundle',
-        help='Creates a tarball containing build '
-        'artifacts from all firmware targets',
+        "bundle",
+        help="Creates a tarball containing build "
+        "artifacts from all firmware targets",
     )
     build_cmd.set_defaults(func=bundle)
 
-    test_cmd = sub_cmds.add_parser('test', help='Runs all firmware unit tests')
+    test_cmd = sub_cmds.add_parser("test", help="Runs all firmware unit tests")
     test_cmd.set_defaults(func=test)
 
     return parser.parse_args(args)
 
 
-if __name__ == '__main__':
+if __name__ == "__main__":
     sys.exit(main(sys.argv[1:]))
diff --git a/zephyr/fpu.cmake b/zephyr/fpu.cmake
index 5f1c698b15..4cda364572 100644
--- a/zephyr/fpu.cmake
+++ b/zephyr/fpu.cmake
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/gcov.tmpl.sh b/zephyr/gcov.tmpl.sh
index 96bd82ab51..b9dd0e7865 100755
--- a/zephyr/gcov.tmpl.sh
+++ b/zephyr/gcov.tmpl.sh
@@ -1,6 +1,6 @@
 #!/bin/bash
 #
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/hayato_get_cfg.sh b/zephyr/hayato_get_cfg.sh
index 5ebe3dc364..1ab1be7a4f 100755
--- a/zephyr/hayato_get_cfg.sh
+++ b/zephyr/hayato_get_cfg.sh
@@ -1,5 +1,5 @@
 #!/bin/bash
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/include/ap_power/ap_power.h b/zephyr/include/ap_power/ap_power.h
index 182e81ca4d..05387d8431 100644
--- a/zephyr/include/ap_power/ap_power.h
+++ b/zephyr/include/ap_power/ap_power.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,7 +9,16 @@
  *
  * Defines the API for AP event notification,
  * the API to register and receive notification callbacks when
- * application processor (AP) events happen
+ * application processor (AP) events happen.
+ *
+ * When the Zephyr based AP power sequence config is enabled,
+ * the callbacks are almost all invoked within the context
+ * of the power sequence task, so the state is stable
+ * during the callback. The only exception to this is AP_POWER_RESET, which is
+ * invoked as a result of receiving a PLTRST# virtual wire signal (if enabled).
+ *
+ * When the legacy power sequence config is enabled, the callbacks are invoked
+ * from the HOOK_CHIPSET notifications.
  */
 
 #ifndef __AP_POWER_AP_POWER_H__
@@ -87,6 +96,36 @@ enum ap_power_events {
 	AP_POWER_HARD_OFF = BIT(8),
 	/** Software reset occurred */
 	AP_POWER_RESET = BIT(9),
+	/**
+	 * AP power state is now known.
+	 *
+	 * Prior to this event, the state of the AP is unknown
+	 * and invalid. When this event is sent, the state is known
+	 * and can be queried. Used by clients when their
+	 * initialization depends upon the initial state of the AP.
+	 */
+	AP_POWER_INITIALIZED = BIT(10),
+
+	/**
+	 * S0ix suspend starts.
+	 */
+	AP_POWER_S0IX_SUSPEND_START = BIT(11),
+	/**
+	 * Transitioning from s0 to s0ix.
+	 */
+	AP_POWER_S0IX_SUSPEND = BIT(12),
+	/**
+	 * Transitioning from s0ix to s0.
+	 */
+	AP_POWER_S0IX_RESUME = BIT(13),
+	/**
+	 * si0x resume complete.
+	 */
+	AP_POWER_S0IX_RESUME_COMPLETE = BIT(14),
+	/**
+	 * Reset s0ix tracking.
+	 */
+	AP_POWER_S0IX_RESET_TRACKING = BIT(15),
 };
 
 /**
@@ -113,12 +152,12 @@ typedef void (*ap_power_ev_callback_handler_t)(struct ap_power_ev_callback *cb,
  * are unique pointers of struct ap_power_ev_callback.
  * The storage must be static.
  *
- * ap_power_ev_init_callback can be used to initialise this structure.
+ * ap_power_ev_init_callback can be used to initialize this structure.
  */
 struct ap_power_ev_callback {
-	sys_snode_t node;	/* Only usable by AP power event code */
+	sys_snode_t node; /* Only usable by AP power event code */
 	ap_power_ev_callback_handler_t handler;
-	enum ap_power_events events;	/* Events to listen for */
+	enum ap_power_events events; /* Events to listen for */
 };
 /** @endcond */
 
@@ -129,9 +168,10 @@ struct ap_power_ev_callback {
  * @param handler The function pointer to call.
  * @param events The bitmask of events to be called for.
  */
-static inline void ap_power_ev_init_callback(struct ap_power_ev_callback *cb,
-				ap_power_ev_callback_handler_t handler,
-				enum ap_power_events events)
+static inline void
+ap_power_ev_init_callback(struct ap_power_ev_callback *cb,
+			  ap_power_ev_callback_handler_t handler,
+			  enum ap_power_events events)
 {
 	__ASSERT(cb, "Callback pointer should not be NULL");
 	__ASSERT(handler, "Callback handler pointer should not be NULL");
diff --git a/zephyr/include/ap_power/ap_power_espi.h b/zephyr/include/ap_power/ap_power_espi.h
new file mode 100644
index 0000000000..2c295054f3
--- /dev/null
+++ b/zephyr/include/ap_power/ap_power_espi.h
@@ -0,0 +1,35 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ * @brief API for power signal ESPI callback.
+ */
+
+#ifndef __AP_POWER_AP_POWER_ESPI_H__
+#define __AP_POWER_AP_POWER_ESPI_H__
+
+#include <zephyr/drivers/espi.h>
+
+/**
+ * @brief ESPI callback for power signal handling.
+ *
+ * This callback must be registered for the bus events indicated below
+ * as part of the common ESPI initialisation and configuration.
+ *
+ * @param dev ESPI device
+ * @param cb Callback structure
+ * @param event ESPI event data
+ */
+void power_signal_espi_cb(const struct device *dev, struct espi_callback *cb,
+			  struct espi_event event);
+
+/*
+ * The ESPI bus events required for the power signal ESPI callback.
+ */
+#define POWER_SIGNAL_ESPI_BUS_EVENTS \
+	(ESPI_BUS_EVENT_CHANNEL_READY | ESPI_BUS_EVENT_VWIRE_RECEIVED)
+
+#endif /* __AP_POWER_AP_POWER_ESPI_H__ */
diff --git a/zephyr/include/ap_power/ap_power_events.h b/zephyr/include/ap_power/ap_power_events.h
index 6181deb2bd..8a6a9764de 100644
--- a/zephyr/include/ap_power/ap_power_events.h
+++ b/zephyr/include/ap_power/ap_power_events.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/include/ap_power/ap_power_interface.h b/zephyr/include/ap_power/ap_power_interface.h
index b82ef053f7..d2808f6075 100644
--- a/zephyr/include/ap_power/ap_power_interface.h
+++ b/zephyr/include/ap_power/ap_power_interface.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -34,6 +34,8 @@
  * is hibernated or all the VRs are turned off.
  */
 enum power_states_ndsx {
+	/* Power state machine is not ready; AP state is unknown. */
+	SYS_POWER_STATE_UNINIT,
 	/*
 	 * Actual power states
 	 */
@@ -87,17 +89,17 @@ enum power_states_ndsx {
  * @brief Represents the state of the AP as a mask.
  */
 enum ap_power_state_mask {
-	AP_POWER_STATE_HARD_OFF = BIT(0),   /* Hard off (G3) */
-	AP_POWER_STATE_SOFT_OFF = BIT(1),   /* Soft off (S5, S4) */
-	AP_POWER_STATE_SUSPEND  = BIT(2),   /* Suspend (S3) */
-	AP_POWER_STATE_ON       = BIT(3),   /* On (S0) */
-	AP_POWER_STATE_STANDBY  = BIT(4),   /* Standby (S0ix) */
+	AP_POWER_STATE_HARD_OFF = BIT(0), /* Hard off (G3) */
+	AP_POWER_STATE_SOFT_OFF = BIT(1), /* Soft off (S5, S4) */
+	AP_POWER_STATE_SUSPEND = BIT(2), /* Suspend (S3) */
+	AP_POWER_STATE_ON = BIT(3), /* On (S0) */
+	AP_POWER_STATE_STANDBY = BIT(4), /* Standby (S0ix) */
 	/* Common combinations, any off state */
-	AP_POWER_STATE_ANY_OFF = (AP_POWER_STATE_HARD_OFF |
-				 AP_POWER_STATE_SOFT_OFF),
+	AP_POWER_STATE_ANY_OFF =
+		(AP_POWER_STATE_HARD_OFF | AP_POWER_STATE_SOFT_OFF),
 	/* This combination covers any kind of suspend i.e. S3 or S0ix. */
-	AP_POWER_STATE_ANY_SUSPEND = (AP_POWER_STATE_SUSPEND |
-				     AP_POWER_STATE_STANDBY),
+	AP_POWER_STATE_ANY_SUSPEND =
+		(AP_POWER_STATE_SUSPEND | AP_POWER_STATE_STANDBY),
 };
 
 /**
diff --git a/zephyr/include/ap_power/ap_pwrseq.h b/zephyr/include/ap_power/ap_pwrseq.h
index c83a8b5695..9e1ffd27e8 100644
--- a/zephyr/include/ap_power/ap_pwrseq.h
+++ b/zephyr/include/ap_power/ap_pwrseq.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,4 +9,5 @@
 /** Starts the AP power sequence thread */
 void ap_pwrseq_task_start(void);
 
+void ap_pwrseq_wake(void);
 #endif /* __AP_POWER_AP_PWRSEQ_H__ */
diff --git a/zephyr/include/cros/binman.dtsi b/zephyr/include/cros/binman.dtsi
index d33092ee44..167fd69d1c 100644
--- a/zephyr/include/cros/binman.dtsi
+++ b/zephyr/include/cros/binman.dtsi
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,7 +7,7 @@
 	#address-cells = <1>;
 	#size-cells = <1>;
 	binman {
-		filename = "zephyr.bin";
+		filename = "ec.bin";
 		pad-byte = <0x1d>;
 		wp-ro {
 			compatible = "cros-ec,flash-layout";
diff --git a/zephyr/include/cros/ite/it8xxx2.dtsi b/zephyr/include/cros/ite/it8xxx2.dtsi
index 4631e64f6f..e9ecf9e716 100644
--- a/zephyr/include/cros/ite/it8xxx2.dtsi
+++ b/zephyr/include/cros/ite/it8xxx2.dtsi
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -77,13 +77,11 @@
 		fiu0: cros-flash@80000000 {
 			compatible = "ite,it8xxx2-cros-flash";
 			reg = <0x80000000 0x100000>;
-			label = "FLASH";
 		};
 
 		cros_kb_raw: cros-kb-raw@f01d00 {
 			compatible = "ite,it8xxx2-cros-kb-raw";
 			reg = <0x00f01d00 0x29>;
-			label = "CROS_KB_RAW_0";
 			interrupt-parent = <&intc>;
 			interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
 			wucctrl = <&wuc_wu30   /* KSI[0] */
@@ -108,5 +106,7 @@
 			offset = <0x60000>;
 			size = <0x60000>;
 		};
+		pad-byte = <0xff>;
+		pad-after = <0x40000>;
 	};
 };
diff --git a/zephyr/include/cros/microchip/mec1727.dtsi b/zephyr/include/cros/microchip/mec1727.dtsi
index 340cff1956..5f84a1a99e 100644
--- a/zephyr/include/cros/microchip/mec1727.dtsi
+++ b/zephyr/include/cros/microchip/mec1727.dtsi
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -75,6 +75,5 @@
 
 	fiu0: cros-flash {
 		compatible = "microchip,xec-cros-flash";
-		label = "INTERNAL_FLASH";
 	};
 };
diff --git a/zephyr/include/cros/microchip/mec172x.dtsi b/zephyr/include/cros/microchip/mec172x.dtsi
index 6833fa57d0..e2cb0ff1c2 100644
--- a/zephyr/include/cros/microchip/mec172x.dtsi
+++ b/zephyr/include/cros/microchip/mec172x.dtsi
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -69,9 +69,8 @@
 		};
 	};
 
-	fiu0: cros-flash{
+	fiu0: cros-flash {
 		compatible = "microchip,xec-cros-flash";
-		label = "INTERNAL_FLASH";
 	};
 
 /*
diff --git a/zephyr/include/cros/nuvoton/npcx.dtsi b/zephyr/include/cros/nuvoton/npcx.dtsi
index 094f5ff901..69f29367f5 100644
--- a/zephyr/include/cros/nuvoton/npcx.dtsi
+++ b/zephyr/include/cros/nuvoton/npcx.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021 The Chromium OS Authors
+ * Copyright 2021 The ChromiumOS Authors
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -68,9 +68,8 @@
 		};
 	};
 
-	fiu0: cros-flash{
+	fiu0: cros-flash {
 		compatible = "nuvoton,npcx-cros-flash";
-		label = "INTERNAL_FLASH";
 	};
 
 	soc {
@@ -78,7 +77,6 @@
 		cros_kb_raw: cros-kb-raw@400a3000 {
 			compatible = "nuvoton,npcx-cros-kb-raw";
 			reg = <0x400a3000 0x2000>;
-			label = "CROS_KB_RAW_0";
 			interrupts = <49 4>;
 			clocks = <&pcc NPCX_CLOCK_BUS_APB1 NPCX_PWDWN_CTL1 0>;
 			wui_maps = <&wui_io31 &wui_io30 &wui_io27 &wui_io26
@@ -89,7 +87,6 @@
 			compatible = "nuvoton,npcx-cros-mtc";
 			reg = <0x400b7000 0x2000>;
 			mtc-alarm = <&wui_mtc>;
-			label = "MTC";
 		};
 
 		shi: shi@4000f000 {
diff --git a/zephyr/include/cros/nuvoton/npcx7.dtsi b/zephyr/include/cros/nuvoton/npcx7.dtsi
index 00683fe8ff..ca69343054 100644
--- a/zephyr/include/cros/nuvoton/npcx7.dtsi
+++ b/zephyr/include/cros/nuvoton/npcx7.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021 The Chromium OS Authors
+ * Copyright 2021 The ChromiumOS Authors
  *
  * SPDX-License-Identifier: Apache-2.0
  */
diff --git a/zephyr/include/cros/nuvoton/npcx9.dtsi b/zephyr/include/cros/nuvoton/npcx9.dtsi
index de492d3306..864ce20269 100644
--- a/zephyr/include/cros/nuvoton/npcx9.dtsi
+++ b/zephyr/include/cros/nuvoton/npcx9.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021 The Chromium OS Authors
+ * Copyright 2021 The ChromiumOS Authors
  *
  * SPDX-License-Identifier: Apache-2.0
  */
diff --git a/zephyr/include/cros/thermistor/thermistor.dtsi b/zephyr/include/cros/thermistor/thermistor.dtsi
index 033d5639e2..fb86c4f79a 100644
--- a/zephyr/include/cros/thermistor/thermistor.dtsi
+++ b/zephyr/include/cros/thermistor/thermistor.dtsi
@@ -1,5 +1,5 @@
 / {
-	thermistor_3V3_30K9_47K_4050B: thermistor-3V3-30K9-47K-4050B {
+	/omit-if-no-ref/ thermistor_3V3_30K9_47K_4050B: thermistor-3V3-30K9-47K-4050B {
 		status = "disabled";
 		compatible = "cros-ec,thermistor";
 		scaling-factor = <11>;
@@ -64,8 +64,7 @@
 		};
 	};
 
-
-	thermistor_3V0_22K6_47K_4050B: thermistor-3V0-22K6-47K-4050B {
+	/omit-if-no-ref/ thermistor_3V0_22K6_47K_4050B: thermistor-3V0-22K6-47K-4050B {
 		status = "disabled";
 		compatible = "cros-ec,thermistor";
 		scaling-factor = <11>;
@@ -145,7 +144,7 @@
 		};
 	};
 
-	thermistor_3V3_13K7_47K_4050B: thermistor-3V3-13K7-47K-4050B {
+	/omit-if-no-ref/ thermistor_3V3_13K7_47K_4050B: thermistor-3V3-13K7-47K-4050B {
 		status = "disabled";
 		compatible = "cros-ec,thermistor";
 		scaling-factor = <13>;
@@ -226,7 +225,7 @@
 	};
 
 
-	thermistor_3V3_51K1_47K_4050B: thermistor-3V3-51K1-47K-4050B {
+	/omit-if-no-ref/ thermistor_3V3_51K1_47K_4050B: thermistor-3V3-51K1-47K-4050B {
 		status = "disabled";
 		compatible = "cros-ec,thermistor";
 		scaling-factor = <11>;
@@ -305,4 +304,86 @@
 			sample-index = <12>;
 		};
 	};
+
+	/omit-if-no-ref/ thermistor_3V3_30K9_47K_NCP15WB:
+				thermistor-3V3-30K9-47K-NCP15WB {
+		status = "disabled";
+		compatible = "cros-ec,thermistor";
+		scaling-factor = <11>;
+		num-pairs = <13>;
+		steinhart-reference-mv = <3300>;
+		steinhart-reference-res = <30900>;
+
+		/*
+		 * Data derived from Steinhart-Hart equation in a resistor
+		 * divider circuit with Vdd=3300mV, R = 30.9Kohm,
+		 * and Murata NCP15WB-series thermistor
+		 * (B = 4050, T0 = 298.15 K, nominal resistance (R0) = 47Kohm).
+		 */
+		sample-datum-0 {
+			milivolt = <(2761 / 11)>;
+			temp = <0>;
+			sample-index = <0>;
+		};
+		sample-datum-1 {
+			milivolt = <(2492 / 11)>;
+			temp = <10>;
+			sample-index = <1>;
+		};
+		sample-datum-2 {
+			milivolt = <(2167 / 11)>;
+			temp = <20>;
+			sample-index = <2>;
+		};
+		sample-datum-3 {
+			milivolt = <(1812 / 11)>;
+			temp = <30>;
+			sample-index = <3>;
+		};
+		sample-datum-4 {
+			milivolt = <(1462 / 11)>;
+			temp = <40>;
+			sample-index = <4>;
+		};
+		sample-datum-5 {
+			milivolt = <(1146 / 11)>;
+			temp = <50>;
+			sample-index = <5>;
+		};
+		sample-datum-6 {
+			milivolt = <(878 / 11)>;
+			temp = <60>;
+			sample-index = <6>;
+		};
+		sample-datum-7 {
+			milivolt = <(665 / 11)>;
+			temp = <70>;
+			sample-index = <7>;
+		};
+		sample-datum-8 {
+			milivolt = <(500 / 11)>;
+			temp = <80>;
+			sample-index = <8>;
+		};
+		sample-datum-9 {
+			milivolt = <(434 / 11)>;
+			temp = <85>;
+			sample-index = <9>;
+		};
+		sample-datum-10 {
+			milivolt = <( 376 / 11)>;
+			temp = <90>;
+			sample-index = <10>;
+		};
+		sample-datum-11 {
+			milivolt = <( 326 / 11)>;
+			temp = <95>;
+			sample-index = <11>;
+		};
+		sample-datum-12 {
+			milivolt = <( 283 / 11)>;
+			temp = <100>;
+			sample-index = <12>;
+		};
+	};
 };
diff --git a/zephyr/include/drivers/cros_displight.h b/zephyr/include/drivers/cros_displight.h
index 83c8577c7e..340d51f60d 100644
--- a/zephyr/include/drivers/cros_displight.h
+++ b/zephyr/include/drivers/cros_displight.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/include/drivers/cros_flash.h b/zephyr/include/drivers/cros_flash.h
index 1bad6bb682..267649476b 100644
--- a/zephyr/include/drivers/cros_flash.h
+++ b/zephyr/include/drivers/cros_flash.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -45,8 +45,8 @@ typedef int (*cros_flash_api_physical_erase)(const struct device *dev,
 typedef int (*cros_flash_api_physical_get_protect)(const struct device *dev,
 						   int bank);
 
-typedef uint32_t
-(*cros_flash_api_physical_get_protect_flags)(const struct device *dev);
+typedef uint32_t (*cros_flash_api_physical_get_protect_flags)(
+	const struct device *dev);
 
 typedef int (*cros_flash_api_physical_protect_at_boot)(const struct device *dev,
 						       uint32_t new_flags);
@@ -55,12 +55,11 @@ typedef int (*cros_flash_api_physical_protect_now)(const struct device *dev,
 						   int all);
 
 typedef int (*cros_flash_api_physical_get_jedec_id)(const struct device *dev,
-						   uint8_t *manufacturer,
-						   uint16_t *device);
+						    uint8_t *manufacturer,
+						    uint16_t *device);
 
 typedef int (*cros_flash_api_physical_get_status)(const struct device *dev,
-						   uint8_t *sr1,
-						   uint8_t *sr2);
+						  uint8_t *sr1, uint8_t *sr2);
 
 __subsystem struct cros_flash_driver_api {
 	cros_flash_api_init init;
@@ -183,6 +182,7 @@ z_impl_cros_flash_physical_get_protect(const struct device *dev, int bank)
 	return api->physical_get_protect(dev, bank);
 }
 
+/* clang-format off */
 /**
  * @brief Return flash protect state flags from the physical layer.
  *
@@ -192,6 +192,7 @@ z_impl_cros_flash_physical_get_protect(const struct device *dev, int bank)
  */
 __syscall
 uint32_t cros_flash_physical_get_protect_flags(const struct device *dev);
+/* clang-format on */
 
 static inline uint32_t
 z_impl_cros_flash_physical_get_protect_flags(const struct device *dev)
@@ -269,13 +270,12 @@ z_impl_cros_flash_physical_protect_now(const struct device *dev, int all)
  * @retval -ENOTSUP Not supported api function.
  */
 __syscall int cros_flash_physical_get_jedec_id(const struct device *dev,
-						      uint8_t *manufacturer,
-						      uint16_t *device);
+					       uint8_t *manufacturer,
+					       uint16_t *device);
 
 static inline int
 z_impl_cros_flash_physical_get_jedec_id(const struct device *dev,
-					uint8_t *manufacturer,
-					uint16_t *device)
+					uint8_t *manufacturer, uint16_t *device)
 {
 	const struct cros_flash_driver_api *api =
 		(const struct cros_flash_driver_api *)dev->api;
@@ -297,11 +297,11 @@ z_impl_cros_flash_physical_get_jedec_id(const struct device *dev,
  * @retval -ENOTSUP Not supported api function.
  */
 __syscall int cros_flash_physical_get_status(const struct device *dev,
-		uint8_t *sr1, uint8_t *sr2);
+					     uint8_t *sr1, uint8_t *sr2);
 
 static inline int
-z_impl_cros_flash_physical_get_status(const struct device *dev,
-				      uint8_t *sr1, uint8_t *sr2)
+z_impl_cros_flash_physical_get_status(const struct device *dev, uint8_t *sr1,
+				      uint8_t *sr2)
 {
 	const struct cros_flash_driver_api *api =
 		(const struct cros_flash_driver_api *)dev->api;
diff --git a/zephyr/include/drivers/cros_kb_raw.h b/zephyr/include/drivers/cros_kb_raw.h
index db2d00bf76..d370a3bbde 100644
--- a/zephyr/include/drivers/cros_kb_raw.h
+++ b/zephyr/include/drivers/cros_kb_raw.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/include/drivers/cros_rtc.h b/zephyr/include/drivers/cros_rtc.h
index 343cf0405e..3a0f332b98 100644
--- a/zephyr/include/drivers/cros_rtc.h
+++ b/zephyr/include/drivers/cros_rtc.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/include/drivers/cros_shi.h b/zephyr/include/drivers/cros_shi.h
index 3d14e2c34f..3eb3038a45 100644
--- a/zephyr/include/drivers/cros_shi.h
+++ b/zephyr/include/drivers/cros_shi.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/include/drivers/cros_system.h b/zephyr/include/drivers/cros_system.h
index 5b3d12ea58..5105d97cc9 100644
--- a/zephyr/include/drivers/cros_system.h
+++ b/zephyr/include/drivers/cros_system.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/include/dt-bindings/battery.h b/zephyr/include/dt-bindings/battery.h
index c87de79b45..e6465e2a9b 100644
--- a/zephyr/include/dt-bindings/battery.h
+++ b/zephyr/include/dt-bindings/battery.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2022 The ChromiumOS Authors.
+ * Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,11 +10,11 @@
  * Macros used by LED devicetree files (led.dts) to define battery-level
  * range.
  */
-#define BATTERY_LEVEL_EMPTY		0
-#define BATTERY_LEVEL_SHUTDOWN		3
-#define BATTERY_LEVEL_CRITICAL		5
-#define BATTERY_LEVEL_LOW		10
-#define BATTERY_LEVEL_NEAR_FULL		97
-#define BATTERY_LEVEL_FULL		100
+#define BATTERY_LEVEL_EMPTY 0
+#define BATTERY_LEVEL_SHUTDOWN 3
+#define BATTERY_LEVEL_CRITICAL 5
+#define BATTERY_LEVEL_LOW 10
+#define BATTERY_LEVEL_NEAR_FULL 97
+#define BATTERY_LEVEL_FULL 100
 
 #endif /* DT_BINDINGS_BATTERY_H_ */
diff --git a/zephyr/include/dt-bindings/charger/intersil_isl9241.h b/zephyr/include/dt-bindings/charger/intersil_isl9241.h
index 5a2742570e..cbb550a5dd 100644
--- a/zephyr/include/dt-bindings/charger/intersil_isl9241.h
+++ b/zephyr/include/dt-bindings/charger/intersil_isl9241.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,10 +9,10 @@
 #define SWITCHING_FREQ_1420KHZ 0
 #define SWITCHING_FREQ_1180KHZ 1
 #define SWITCHING_FREQ_1020KHZ 2
-#define SWITCHING_FREQ_890KHZ  3
-#define SWITCHING_FREQ_808KHZ  4
-#define SWITCHING_FREQ_724KHZ  5
-#define SWITCHING_FREQ_656KHZ  6
-#define SWITCHING_FREQ_600KHZ  7
+#define SWITCHING_FREQ_890KHZ 3
+#define SWITCHING_FREQ_808KHZ 4
+#define SWITCHING_FREQ_724KHZ 5
+#define SWITCHING_FREQ_656KHZ 6
+#define SWITCHING_FREQ_600KHZ 7
 
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CHARGER_INTERSIL_ISL9241_H_ */
diff --git a/zephyr/include/dt-bindings/cros-kb-raw/ite_cros_kb_raw.h b/zephyr/include/dt-bindings/cros-kb-raw/ite_cros_kb_raw.h
index f88efed949..53769f5dbf 100644
--- a/zephyr/include/dt-bindings/cros-kb-raw/ite_cros_kb_raw.h
+++ b/zephyr/include/dt-bindings/cros-kb-raw/ite_cros_kb_raw.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/include/dt-bindings/cros-kb-raw/mchp_cros_kb_raw.h b/zephyr/include/dt-bindings/cros-kb-raw/mchp_cros_kb_raw.h
index 41b6c6b3b6..b520e154da 100644
--- a/zephyr/include/dt-bindings/cros-kb-raw/mchp_cros_kb_raw.h
+++ b/zephyr/include/dt-bindings/cros-kb-raw/mchp_cros_kb_raw.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/include/dt-bindings/gpio_defines.h b/zephyr/include/dt-bindings/gpio_defines.h
index fd63b5ac4a..16da598363 100644
--- a/zephyr/include/dt-bindings/gpio_defines.h
+++ b/zephyr/include/dt-bindings/gpio_defines.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2022 The Chromium OS Authors. All rights reserved.
+ * Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,31 +21,31 @@
  */
 
 /** Enables pin as input. */
-#define GPIO_INPUT              (1U << 16)
+#define GPIO_INPUT (1U << 16)
 
 /** Enables pin as output, no change to the output state. */
-#define GPIO_OUTPUT             (1U << 17)
+#define GPIO_OUTPUT (1U << 17)
 
 /* Initializes output to a low state. */
-#define GPIO_OUTPUT_INIT_LOW    (1U << 18)
+#define GPIO_OUTPUT_INIT_LOW (1U << 18)
 
 /* Initializes output to a high state. */
-#define GPIO_OUTPUT_INIT_HIGH   (1U << 19)
+#define GPIO_OUTPUT_INIT_HIGH (1U << 19)
 
 /* Initializes output based on logic level */
 #define GPIO_OUTPUT_INIT_LOGICAL (1U << 20)
 
 /* Configures GPIO pin as output and initializes it to a low state. */
-#define GPIO_OUTPUT_LOW         (GPIO_OUTPUT | GPIO_OUTPUT_INIT_LOW)
+#define GPIO_OUTPUT_LOW (GPIO_OUTPUT | GPIO_OUTPUT_INIT_LOW)
 
 /* Configures GPIO pin as output and initializes it to a high state. */
-#define GPIO_OUTPUT_HIGH        (GPIO_OUTPUT | GPIO_OUTPUT_INIT_HIGH)
+#define GPIO_OUTPUT_HIGH (GPIO_OUTPUT | GPIO_OUTPUT_INIT_HIGH)
 
 /* Configures GPIO pin as input with pull-up. */
-#define GPIO_INPUT_PULL_UP      (GPIO_INPUT | GPIO_PULL_UP)
+#define GPIO_INPUT_PULL_UP (GPIO_INPUT | GPIO_PULL_UP)
 
 /* Configures GPIO pin as input with pull-down. */
-#define GPIO_INPUT_PULL_DOWN    (GPIO_INPUT | GPIO_PULL_DOWN)
+#define GPIO_INPUT_PULL_DOWN (GPIO_INPUT | GPIO_PULL_DOWN)
 
 /** Configures GPIO pin as ODR output and initializes it to a low state. */
 #define GPIO_ODR_LOW (GPIO_OUTPUT_LOW | GPIO_OPEN_DRAIN)
@@ -61,17 +61,17 @@
  */
 
 /** Disables GPIO pin interrupt. */
-#define GPIO_INT_DISABLE               (1U << 21)
+#define GPIO_INT_DISABLE (1U << 21)
 
 /* Enables GPIO pin interrupt. */
-#define GPIO_INT_ENABLE                (1U << 22)
+#define GPIO_INT_ENABLE (1U << 22)
 
 /* GPIO interrupt is sensitive to logical levels.
  *
  * This is a component flag that should be combined with other
  * `GPIO_INT_*` flags to produce a meaningful configuration.
  */
-#define GPIO_INT_LEVELS_LOGICAL        (1U << 23)
+#define GPIO_INT_LEVELS_LOGICAL (1U << 23)
 
 /* GPIO interrupt is edge sensitive.
  *
@@ -80,7 +80,7 @@
  * This is a component flag that should be combined with other
  * `GPIO_INT_*` flags to produce a meaningful configuration.
  */
-#define GPIO_INT_EDGE                  (1U << 24)
+#define GPIO_INT_EDGE (1U << 24)
 
 /* Trigger detection when input state is (or transitions to) physical low or
  * logical 0 level.
@@ -88,7 +88,7 @@
  * This is a component flag that should be combined with other
  * `GPIO_INT_*` flags to produce a meaningful configuration.
  */
-#define GPIO_INT_LOW_0                 (1U << 25)
+#define GPIO_INT_LOW_0 (1U << 25)
 
 /* Trigger detection on input state is (or transitions to) physical high or
  * logical 1 level.
@@ -96,69 +96,57 @@
  * This is a component flag that should be combined with other
  * `GPIO_INT_*` flags to produce a meaningful configuration.
  */
-#define GPIO_INT_HIGH_1                (1U << 26)
+#define GPIO_INT_HIGH_1 (1U << 26)
 
 /** Configures GPIO interrupt to be triggered on pin rising edge and enables it.
  */
-#define GPIO_INT_EDGE_RISING           (GPIO_INT_ENABLE | \
-					GPIO_INT_EDGE | \
-					GPIO_INT_HIGH_1)
+#define GPIO_INT_EDGE_RISING (GPIO_INT_ENABLE | GPIO_INT_EDGE | GPIO_INT_HIGH_1)
 
 /** Configures GPIO interrupt to be triggered on pin falling edge and enables
  * it.
  */
-#define GPIO_INT_EDGE_FALLING          (GPIO_INT_ENABLE | \
-					GPIO_INT_EDGE | \
-					GPIO_INT_LOW_0)
+#define GPIO_INT_EDGE_FALLING (GPIO_INT_ENABLE | GPIO_INT_EDGE | GPIO_INT_LOW_0)
 
 /** Configures GPIO interrupt to be triggered on pin rising or falling edge and
  * enables it.
  */
-#define GPIO_INT_EDGE_BOTH             (GPIO_INT_ENABLE | \
-					GPIO_INT_EDGE | \
-					GPIO_INT_LOW_0 | \
-					GPIO_INT_HIGH_1)
+#define GPIO_INT_EDGE_BOTH \
+	(GPIO_INT_ENABLE | GPIO_INT_EDGE | GPIO_INT_LOW_0 | GPIO_INT_HIGH_1)
 
 /** Configures GPIO interrupt to be triggered on pin physical level low and
  * enables it.
  */
-#define GPIO_INT_LEVEL_LOW             (GPIO_INT_ENABLE | \
-					GPIO_INT_LOW_0)
+#define GPIO_INT_LEVEL_LOW (GPIO_INT_ENABLE | GPIO_INT_LOW_0)
 
 /** Configures GPIO interrupt to be triggered on pin physical level high and
  * enables it.
  */
-#define GPIO_INT_LEVEL_HIGH            (GPIO_INT_ENABLE | \
-					GPIO_INT_HIGH_1)
+#define GPIO_INT_LEVEL_HIGH (GPIO_INT_ENABLE | GPIO_INT_HIGH_1)
 
 /** Configures GPIO interrupt to be triggered on pin state change to logical
  * level 0 and enables it.
  */
-#define GPIO_INT_EDGE_TO_INACTIVE      (GPIO_INT_ENABLE | \
-					GPIO_INT_LEVELS_LOGICAL | \
-					GPIO_INT_EDGE | \
-					GPIO_INT_LOW_0)
+#define GPIO_INT_EDGE_TO_INACTIVE                                    \
+	(GPIO_INT_ENABLE | GPIO_INT_LEVELS_LOGICAL | GPIO_INT_EDGE | \
+	 GPIO_INT_LOW_0)
 
 /** Configures GPIO interrupt to be triggered on pin state change to logical
  * level 1 and enables it.
  */
-#define GPIO_INT_EDGE_TO_ACTIVE        (GPIO_INT_ENABLE | \
-					GPIO_INT_LEVELS_LOGICAL | \
-					GPIO_INT_EDGE | \
-					GPIO_INT_HIGH_1)
+#define GPIO_INT_EDGE_TO_ACTIVE                                      \
+	(GPIO_INT_ENABLE | GPIO_INT_LEVELS_LOGICAL | GPIO_INT_EDGE | \
+	 GPIO_INT_HIGH_1)
 
 /** Configures GPIO interrupt to be triggered on pin logical level 0 and enables
  * it.
  */
-#define GPIO_INT_LEVEL_INACTIVE        (GPIO_INT_ENABLE | \
-					GPIO_INT_LEVELS_LOGICAL | \
-					GPIO_INT_LOW_0)
+#define GPIO_INT_LEVEL_INACTIVE \
+	(GPIO_INT_ENABLE | GPIO_INT_LEVELS_LOGICAL | GPIO_INT_LOW_0)
 
 /** Configures GPIO interrupt to be triggered on pin logical level 1 and enables
  * it.
  */
-#define GPIO_INT_LEVEL_ACTIVE          (GPIO_INT_ENABLE | \
-					GPIO_INT_LEVELS_LOGICAL | \
-					GPIO_INT_HIGH_1)
+#define GPIO_INT_LEVEL_ACTIVE \
+	(GPIO_INT_ENABLE | GPIO_INT_LEVELS_LOGICAL | GPIO_INT_HIGH_1)
 
 #endif /* DT_BINDINGS_GPIO_DEFINES_H_ */
diff --git a/zephyr/include/dt-bindings/motionsense/utils.h b/zephyr/include/dt-bindings/motionsense/utils.h
index 7f0e5f5fc8..f7a3a31927 100644
--- a/zephyr/include/dt-bindings/motionsense/utils.h
+++ b/zephyr/include/dt-bindings/motionsense/utils.h
@@ -7,8 +7,8 @@
 #ifndef DT_BINDINGS_UTILS_H
 #define DT_BINDINGS_UTILS_H
 
-#define BIT(x)			(1U << (x))
-#define ROUND_UP_FLAG		BIT(31)
-#define USEC_PER_MSEC		1000
+#define BIT(x) (1U << (x))
+#define ROUND_UP_FLAG BIT(31)
+#define USEC_PER_MSEC 1000
 
 #endif /* DT_BINDINGS_UTILS_H */
diff --git a/zephyr/include/dt-bindings/usb_pd_tcpm.h b/zephyr/include/dt-bindings/usb_pd_tcpm.h
index 2b0902d097..93e5165140 100644
--- a/zephyr/include/dt-bindings/usb_pd_tcpm.h
+++ b/zephyr/include/dt-bindings/usb_pd_tcpm.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2022 The Chromium OS Authors. All rights reserved.
+ * Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,14 +24,14 @@
  * Bit 7 --> TCPC controls FRS (even when CONFIG_USB_PD_FRS_TCPC is off)
  * Bit 8 --> TCPC enable VBUS monitoring
  */
-#define TCPC_FLAGS_ALERT_ACTIVE_HIGH	BIT(0)
-#define TCPC_FLAGS_ALERT_OD		BIT(1)
-#define TCPC_FLAGS_RESET_ACTIVE_HIGH	BIT(2)
-#define TCPC_FLAGS_TCPCI_REV2_0		BIT(3)
-#define TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V	BIT(4)
-#define TCPC_FLAGS_NO_DEBUG_ACC_CONTROL	BIT(5)
-#define TCPC_FLAGS_CONTROL_VCONN	BIT(6)
-#define TCPC_FLAGS_CONTROL_FRS		BIT(7)
-#define TCPC_FLAGS_VBUS_MONITOR		BIT(8)
+#define TCPC_FLAGS_ALERT_ACTIVE_HIGH BIT(0)
+#define TCPC_FLAGS_ALERT_OD BIT(1)
+#define TCPC_FLAGS_RESET_ACTIVE_HIGH BIT(2)
+#define TCPC_FLAGS_TCPCI_REV2_0 BIT(3)
+#define TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V BIT(4)
+#define TCPC_FLAGS_NO_DEBUG_ACC_CONTROL BIT(5)
+#define TCPC_FLAGS_CONTROL_VCONN BIT(6)
+#define TCPC_FLAGS_CONTROL_FRS BIT(7)
+#define TCPC_FLAGS_VBUS_MONITOR BIT(8)
 
 #endif
diff --git a/zephyr/include/dt-bindings/usbc_mux.h b/zephyr/include/dt-bindings/usbc_mux.h
index 8cfe38340f..1d91542814 100644
--- a/zephyr/include/dt-bindings/usbc_mux.h
+++ b/zephyr/include/dt-bindings/usbc_mux.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2022 The Chromium OS Authors. All rights reserved.
+ * Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,5 +14,6 @@
 #define USB_MUX_FLAG_NOT_TCPC BIT(0) /* TCPC/MUX device used only as MUX */
 #define USB_MUX_FLAG_SET_WITHOUT_FLIP BIT(1) /* SET should not flip */
 #define USB_MUX_FLAG_RESETS_IN_G3 BIT(2) /* Mux chip will reset in G3 */
+#define USB_MUX_FLAG_POLARITY_INVERTED BIT(3) /* Mux polarity is inverted */
 
 #endif /* DT_BINDINGS_USBC_MUX_H_ */
diff --git a/zephyr/include/dt-bindings/wake_mask_event_defines.h b/zephyr/include/dt-bindings/wake_mask_event_defines.h
index 168c8425e5..f9df35701e 100644
--- a/zephyr/include/dt-bindings/wake_mask_event_defines.h
+++ b/zephyr/include/dt-bindings/wake_mask_event_defines.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2022 The Chromium OS Authors. All rights reserved.
+ * Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,52 +19,52 @@
  * defined in this file.
  */
 
-#define MKBP_EVENT_KEY_MATRIX		BIT(0)
-#define MKBP_EVENT_HOST_EVENT		BIT(1)
-#define MKBP_EVENT_SENSOR_FIFO		BIT(2)
-#define MKBP_EVENT_BUTTON		BIT(3)
-#define MKBP_EVENT_SWITCH		BIT(4)
-#define MKBP_EVENT_FINGERPRINT		BIT(5)
-#define MKBP_EVENT_SYSRQ		BIT(6)
-#define MKBP_EVENT_HOST_EVENT64		BIT(7)
-#define MKBP_EVENT_CEC_EVENT		BIT(8)
-#define MKBP_EVENT_CEC_MESSAGE		BIT(9)
-#define MKBP_EVENT_DP_ALT_MODE_ENTERED	BIT(10)
-#define MKBP_EVENT_ONLINE_CALIBRATION	BIT(11)
-#define MKBP_EVENT_PCHG			BIT(12)
+#define MKBP_EVENT_KEY_MATRIX BIT(0)
+#define MKBP_EVENT_HOST_EVENT BIT(1)
+#define MKBP_EVENT_SENSOR_FIFO BIT(2)
+#define MKBP_EVENT_BUTTON BIT(3)
+#define MKBP_EVENT_SWITCH BIT(4)
+#define MKBP_EVENT_FINGERPRINT BIT(5)
+#define MKBP_EVENT_SYSRQ BIT(6)
+#define MKBP_EVENT_HOST_EVENT64 BIT(7)
+#define MKBP_EVENT_CEC_EVENT BIT(8)
+#define MKBP_EVENT_CEC_MESSAGE BIT(9)
+#define MKBP_EVENT_DP_ALT_MODE_ENTERED BIT(10)
+#define MKBP_EVENT_ONLINE_CALIBRATION BIT(11)
+#define MKBP_EVENT_PCHG BIT(12)
 
-#define HOST_EVENT_NONE			0
-#define HOST_EVENT_LID_CLOSED		BIT(0)
-#define HOST_EVENT_LID_OPEN		BIT(1)
-#define HOST_EVENT_POWER_BUTTON		BIT(2)
-#define HOST_EVENT_AC_CONNECTED		BIT(3)
-#define HOST_EVENT_AC_DISCONNECTED	BIT(4)
-#define HOST_EVENT_BATTERY_LOW		BIT(5)
-#define HOST_EVENT_BATTERY_CRITICAL	BIT(6)
-#define HOST_EVENT_BATTERY		BIT(7)
-#define HOST_EVENT_THERMAL_THRESHOLD	BIT(8)
-#define HOST_EVENT_DEVICE		BIT(9)
-#define HOST_EVENT_THERMAL		BIT(10)
-#define HOST_EVENT_USB_CHARGER		BIT(11)
-#define HOST_EVENT_KEY_PRESSED		BIT(12)
-#define HOST_EVENT_INTERFACE_READY	BIT(13)
-#define HOST_EVENT_KEYBOARD_RECOVERY	BIT(14)
-#define HOST_EVENT_THERMAL_SHUTDOWN	BIT(15)
-#define HOST_EVENT_BATTERY_SHUTDOWN	BIT(16)
-#define HOST_EVENT_THROTTLE_START	BIT(17)
-#define HOST_EVENT_THROTTLE_STOP	BIT(18)
-#define HOST_EVENT_HANG_DETECT		BIT(19)
-#define HOST_EVENT_HANG_REBOOT		BIT(20)
-#define HOST_EVENT_PD_MCU		BIT(21)
-#define HOST_EVENT_BATTERY_STATUS	BIT(22)
-#define HOST_EVENT_PANIC		BIT(23)
-#define HOST_EVENT_KEYBOARD_FASTBOOT	BIT(24)
-#define HOST_EVENT_RTC			BIT(25)
-#define HOST_EVENT_MKBP			BIT(26)
-#define HOST_EVENT_USB_MUX		BIT(27)
-#define HOST_EVENT_MODE_CHANGE		BIT(28)
-#define HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT	BIT(29)
-#define HOST_EVENT_WOV			BIT(30)
-#define HOST_EVENT_INVALID		BIT(31)
+#define HOST_EVENT_NONE 0
+#define HOST_EVENT_LID_CLOSED BIT(0)
+#define HOST_EVENT_LID_OPEN BIT(1)
+#define HOST_EVENT_POWER_BUTTON BIT(2)
+#define HOST_EVENT_AC_CONNECTED BIT(3)
+#define HOST_EVENT_AC_DISCONNECTED BIT(4)
+#define HOST_EVENT_BATTERY_LOW BIT(5)
+#define HOST_EVENT_BATTERY_CRITICAL BIT(6)
+#define HOST_EVENT_BATTERY BIT(7)
+#define HOST_EVENT_THERMAL_THRESHOLD BIT(8)
+#define HOST_EVENT_DEVICE BIT(9)
+#define HOST_EVENT_THERMAL BIT(10)
+#define HOST_EVENT_USB_CHARGER BIT(11)
+#define HOST_EVENT_KEY_PRESSED BIT(12)
+#define HOST_EVENT_INTERFACE_READY BIT(13)
+#define HOST_EVENT_KEYBOARD_RECOVERY BIT(14)
+#define HOST_EVENT_THERMAL_SHUTDOWN BIT(15)
+#define HOST_EVENT_BATTERY_SHUTDOWN BIT(16)
+#define HOST_EVENT_THROTTLE_START BIT(17)
+#define HOST_EVENT_THROTTLE_STOP BIT(18)
+#define HOST_EVENT_HANG_DETECT BIT(19)
+#define HOST_EVENT_HANG_REBOOT BIT(20)
+#define HOST_EVENT_PD_MCU BIT(21)
+#define HOST_EVENT_BATTERY_STATUS BIT(22)
+#define HOST_EVENT_PANIC BIT(23)
+#define HOST_EVENT_KEYBOARD_FASTBOOT BIT(24)
+#define HOST_EVENT_RTC BIT(25)
+#define HOST_EVENT_MKBP BIT(26)
+#define HOST_EVENT_USB_MUX BIT(27)
+#define HOST_EVENT_MODE_CHANGE BIT(28)
+#define HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT BIT(29)
+#define HOST_EVENT_WOV BIT(30)
+#define HOST_EVENT_INVALID BIT(31)
 
 #endif /* DT_BINDINGS_WAKE_MASK_EVENT_DEFINES_H_ */
diff --git a/zephyr/include/emul/emul_bb_retimer.h b/zephyr/include/emul/emul_bb_retimer.h
index 9c6a73c3f4..9db2dd565e 100644
--- a/zephyr/include/emul/emul_bb_retimer.h
+++ b/zephyr/include/emul/emul_bb_retimer.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -37,22 +37,13 @@
  */
 
 /**
- * @brief Get pointer to BB retimer emulator using device tree order number.
- *
- * @param ord Device tree order number obtained from DT_DEP_ORD macro
- *
- * @return Pointer to BB retimer emulator
- */
-struct i2c_emul *bb_emul_get(int ord);
-
-/**
  * @brief Set value of given register of BB retimer
  *
  * @param emul Pointer to BB retimer emulator
  * @param reg Register address which value will be changed
  * @param val New value of the register
  */
-void bb_emul_set_reg(struct i2c_emul *emul, int reg, uint32_t val);
+void bb_emul_set_reg(const struct emul *emul, int reg, uint32_t val);
 
 /**
  * @brief Get value of given register of BB retimer
@@ -62,7 +53,7 @@ void bb_emul_set_reg(struct i2c_emul *emul, int reg, uint32_t val);
  *
  * @return Value of the register
  */
-uint32_t bb_emul_get_reg(struct i2c_emul *emul, int reg);
+uint32_t bb_emul_get_reg(const struct emul *emul, int reg);
 
 /**
  * @brief Set if error should be generated when read only register is being
@@ -71,7 +62,7 @@ uint32_t bb_emul_get_reg(struct i2c_emul *emul, int reg);
  * @param emul Pointer to BB retimer emulator
  * @param set Check for this error
  */
-void bb_emul_set_err_on_ro_write(struct i2c_emul *emul, bool set);
+void bb_emul_set_err_on_ro_write(const struct emul *emul, bool set);
 
 /**
  * @brief Set if error should be generated when reserved bits of register are
@@ -80,7 +71,16 @@ void bb_emul_set_err_on_ro_write(struct i2c_emul *emul, bool set);
  * @param emul Pointer to BB retimer emulator
  * @param set Check for this error
  */
-void bb_emul_set_err_on_rsvd_write(struct i2c_emul *emul, bool set);
+void bb_emul_set_err_on_rsvd_write(const struct emul *emul, bool set);
+
+/**
+ * @brief Returns pointer to i2c_common_emul_data for given emul
+ *
+ * @param emul Pointer to bb retimer emulator
+ * @return Pointer to i2c_common_emul_data for emul argument
+ */
+struct i2c_common_emul_data *
+emul_bb_retimer_get_i2c_common_data(const struct emul *emul);
 
 /**
  * @}
diff --git a/zephyr/include/emul/emul_bma255.h b/zephyr/include/emul/emul_bma255.h
index 158d29cf97..44a56a86f7 100644
--- a/zephyr/include/emul/emul_bma255.h
+++ b/zephyr/include/emul/emul_bma255.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -47,25 +47,16 @@
  * Axis argument used in @ref bma_emul_set_acc @ref bma_emul_get_acc
  * @ref bma_emul_set_off and @ref bma_emul_get_off
  */
-#define BMA_EMUL_AXIS_X		0
-#define BMA_EMUL_AXIS_Y		1
-#define BMA_EMUL_AXIS_Z		2
+#define BMA_EMUL_AXIS_X 0
+#define BMA_EMUL_AXIS_Y 1
+#define BMA_EMUL_AXIS_Z 2
 
 /**
  * Acceleration 1g in internal emulator units. It is helpful for using
  * functions @ref bma_emul_set_acc @ref bma_emul_get_acc
  * @ref bma_emul_set_off and @ref bma_emul_get_off
  */
-#define BMA_EMUL_1G		BIT(10)
-
-/**
- * @brief Get pointer to BMA255 emulator using device tree order number.
- *
- * @param ord Device tree order number obtained from DT_DEP_ORD macro
- *
- * @return Pointer to BMA255 emulator
- */
-struct i2c_emul *bma_emul_get(int ord);
+#define BMA_EMUL_1G BIT(10)
 
 /**
  * @brief Set value of given register of BMA255
@@ -74,7 +65,7 @@ struct i2c_emul *bma_emul_get(int ord);
  * @param reg Register address which value will be changed
  * @param val New value of the register
  */
-void bma_emul_set_reg(struct i2c_emul *emul, int reg, uint8_t val);
+void bma_emul_set_reg(const struct emul *emul, int reg, uint8_t val);
 
 /**
  * @brief Get value of given register of BMA255
@@ -84,7 +75,7 @@ void bma_emul_set_reg(struct i2c_emul *emul, int reg, uint8_t val);
  *
  * @return Value of the register
  */
-uint8_t bma_emul_get_reg(struct i2c_emul *emul, int reg);
+uint8_t bma_emul_get_reg(const struct emul *emul, int reg);
 
 /**
  * @brief Get internal value of offset for given axis
@@ -94,7 +85,7 @@ uint8_t bma_emul_get_reg(struct i2c_emul *emul, int reg);
  *
  * @return Offset of given axis. LSB is 0.97mg
  */
-int16_t bma_emul_get_off(struct i2c_emul *emul, int axis);
+int16_t bma_emul_get_off(const struct emul *emul, int axis);
 
 /**
  * @brief Set internal value of offset for given axis
@@ -103,7 +94,7 @@ int16_t bma_emul_get_off(struct i2c_emul *emul, int axis);
  * @param axis Axis to access: 0 - X, 1 - Y, 2 - Z
  * @param val New value of offset. LSB is 0.97mg
  */
-void bma_emul_set_off(struct i2c_emul *emul, int axis, int16_t val);
+void bma_emul_set_off(const struct emul *emul, int axis, int16_t val);
 
 /**
  * @brief Get internal value of accelerometer for given axis
@@ -113,7 +104,7 @@ void bma_emul_set_off(struct i2c_emul *emul, int axis, int16_t val);
  *
  * @return Acceleration of given axis. LSB is 0.97mg
  */
-int16_t bma_emul_get_acc(struct i2c_emul *emul, int axis);
+int16_t bma_emul_get_acc(const struct emul *emul, int axis);
 
 /**
  * @brief Set internal value of accelerometr for given axis
@@ -122,7 +113,7 @@ int16_t bma_emul_get_acc(struct i2c_emul *emul, int axis);
  * @param axis Axis to access: 0 - X, 1 - Y, 2 - Z
  * @param val New value of accelerometer axis. LSB is 0.97mg
  */
-void bma_emul_set_acc(struct i2c_emul *emul, int axis, int16_t val);
+void bma_emul_set_acc(const struct emul *emul, int axis, int16_t val);
 
 /**
  * @brief Set if error should be generated when fast compensation is triggered
@@ -131,7 +122,7 @@ void bma_emul_set_acc(struct i2c_emul *emul, int axis, int16_t val);
  * @param emul Pointer to BMA255 emulator
  * @param set Check for this error
  */
-void bma_emul_set_err_on_cal_nrdy(struct i2c_emul *emul, bool set);
+void bma_emul_set_err_on_cal_nrdy(const struct emul *emul, bool set);
 
 /**
  * @brief Set if error should be generated when fast compensation is triggered
@@ -140,7 +131,7 @@ void bma_emul_set_err_on_cal_nrdy(struct i2c_emul *emul, bool set);
  * @param emul Pointer to BMA255 emulator
  * @param set Check for this error
  */
-void bma_emul_set_err_on_cal_bad_range(struct i2c_emul *emul, bool set);
+void bma_emul_set_err_on_cal_bad_range(const struct emul *emul, bool set);
 
 /**
  * @brief Set if error should be generated when read only register is being
@@ -149,7 +140,7 @@ void bma_emul_set_err_on_cal_bad_range(struct i2c_emul *emul, bool set);
  * @param emul Pointer to BMA255 emulator
  * @param set Check for this error
  */
-void bma_emul_set_err_on_ro_write(struct i2c_emul *emul, bool set);
+void bma_emul_set_err_on_ro_write(const struct emul *emul, bool set);
 
 /**
  * @brief Set if error should be generated when reserved bits of register are
@@ -158,7 +149,7 @@ void bma_emul_set_err_on_ro_write(struct i2c_emul *emul, bool set);
  * @param emul Pointer to BMA255 emulator
  * @param set Check for this error
  */
-void bma_emul_set_err_on_rsvd_write(struct i2c_emul *emul, bool set);
+void bma_emul_set_err_on_rsvd_write(const struct emul *emul, bool set);
 
 /**
  * @brief Set if error should be generated when MSB register is accessed before
@@ -167,7 +158,7 @@ void bma_emul_set_err_on_rsvd_write(struct i2c_emul *emul, bool set);
  * @param emul Pointer to BMA255 emulator
  * @param set Check for this error
  */
-void bma_emul_set_err_on_msb_first(struct i2c_emul *emul, bool set);
+void bma_emul_set_err_on_msb_first(const struct emul *emul, bool set);
 
 /**
  * @brief Function calculate register that should be accessed when I2C message
@@ -182,7 +173,16 @@ void bma_emul_set_err_on_msb_first(struct i2c_emul *emul, bool set);
  *
  * @retval Register address that should be accessed
  */
-int bma_emul_access_reg(struct i2c_emul *emul, int reg, int bytes, bool read);
+int bma_emul_access_reg(const struct emul *emul, int reg, int bytes, bool read);
+
+/**
+ * @brief Returns pointer to i2c_common_emul_data for argument emul
+ *
+ * @param emul Pointer to BMA emulator
+ * @return Pointer to i2c_common_emul_data from argument emul
+ */
+struct i2c_common_emul_data *
+emul_bma_get_i2c_common_data(const struct emul *emul);
 
 /**
  * @}
diff --git a/zephyr/include/emul/emul_bmi.h b/zephyr/include/emul/emul_bmi.h
index b04278bd5e..c7a07ba4bf 100644
--- a/zephyr/include/emul/emul_bmi.h
+++ b/zephyr/include/emul/emul_bmi.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -60,49 +60,49 @@ enum bmi_emul_axis {
 };
 
 /** BMI emulator models */
-#define BMI_EMUL_160		1
-#define BMI_EMUL_260		2
+#define BMI_EMUL_160 1
+#define BMI_EMUL_260 2
 
 /** Last register supported by emulator */
-#define BMI_EMUL_MAX_REG	0x80
+#define BMI_EMUL_MAX_REG 0x80
 /** Maximum number of registers that can be backed in NVM */
-#define BMI_EMUL_MAX_NVM_REGS	10
+#define BMI_EMUL_MAX_NVM_REGS 10
 
 /** Headers used in FIFO frames */
-#define BMI_EMUL_FIFO_HEAD_SKIP			0x40
-#define BMI_EMUL_FIFO_HEAD_TIME			0x44
-#define BMI_EMUL_FIFO_HEAD_CONFIG		0x48
-#define BMI_EMUL_FIFO_HEAD_EMPTY		0x80
-#define BMI_EMUL_FIFO_HEAD_DATA			0x80
-#define BMI_EMUL_FIFO_HEAD_DATA_MAG		BIT(4)
-#define BMI_EMUL_FIFO_HEAD_DATA_GYR		BIT(3)
-#define BMI_EMUL_FIFO_HEAD_DATA_ACC		BIT(2)
-#define BMI_EMUL_FIFO_HEAD_DATA_TAG_MASK	0x03
+#define BMI_EMUL_FIFO_HEAD_SKIP 0x40
+#define BMI_EMUL_FIFO_HEAD_TIME 0x44
+#define BMI_EMUL_FIFO_HEAD_CONFIG 0x48
+#define BMI_EMUL_FIFO_HEAD_EMPTY 0x80
+#define BMI_EMUL_FIFO_HEAD_DATA 0x80
+#define BMI_EMUL_FIFO_HEAD_DATA_MAG BIT(4)
+#define BMI_EMUL_FIFO_HEAD_DATA_GYR BIT(3)
+#define BMI_EMUL_FIFO_HEAD_DATA_ACC BIT(2)
+#define BMI_EMUL_FIFO_HEAD_DATA_TAG_MASK 0x03
 
 /**
  * Acceleration 1g in internal emulator units. It is helpful for using
  * functions @ref bmi_emul_set_value @ref bmi_emul_get_value
  * @ref bmi_emul_set_off and @ref bmi_emul_get_off
  */
-#define BMI_EMUL_1G		BIT(14)
+#define BMI_EMUL_1G BIT(14)
 /**
  * Gyroscope 125°/s in internal emulator units. It is helpful for using
  * functions @ref bmi_emul_set_value @ref bmi_emul_get_value
  * @ref bmi_emul_set_off and @ref bmi_emul_get_off
  */
-#define BMI_EMUL_125_DEG_S	BIT(15)
+#define BMI_EMUL_125_DEG_S BIT(15)
 
 /** Type of frames that can be added to the emulator frames list */
-#define BMI_EMUL_FRAME_CONFIG	BIT(0)
-#define BMI_EMUL_FRAME_ACC	BIT(1)
-#define BMI_EMUL_FRAME_MAG	BIT(2)
-#define BMI_EMUL_FRAME_GYR	BIT(3)
+#define BMI_EMUL_FRAME_CONFIG BIT(0)
+#define BMI_EMUL_FRAME_ACC BIT(1)
+#define BMI_EMUL_FRAME_MAG BIT(2)
+#define BMI_EMUL_FRAME_GYR BIT(3)
 
 /**
  * Code returned by model specific handle_read and handle_write functions, when
  * RO register is accessed on write or WO register is accessed on read
  */
-#define BMI_EMUL_ACCESS_E	1
+#define BMI_EMUL_ACCESS_E 1
 
 /** Structure used to describe single FIFO frame */
 struct bmi_emul_frame {
@@ -147,7 +147,8 @@ struct bmi_emul_type_data {
 	 *
 	 * @return Register address that will be accessed
 	 */
-	int (*access_reg)(struct i2c_emul *emul, int reg, int byte, bool read);
+	int (*access_reg)(const struct emul *emul, int reg, int byte,
+			  bool read);
 
 	/**
 	 * @brief Model specific write function. It should modify state of
@@ -163,7 +164,7 @@ struct bmi_emul_type_data {
 	 * @return BMI_EMUL_ACCESS_E on RO register access
 	 * @return other on error
 	 */
-	int (*handle_write)(uint8_t *regs, struct i2c_emul *emul, int reg,
+	int (*handle_write)(uint8_t *regs, const struct emul *emul, int reg,
 			    int byte, uint8_t val);
 	/**
 	 * @brief Model specific read function. It should modify state of
@@ -179,16 +180,29 @@ struct bmi_emul_type_data {
 	 * @return BMI_EMUL_ACCESS_E on WO register access
 	 * @return other on error
 	 */
-	int (*handle_read)(uint8_t *regs, struct i2c_emul *emul, int reg,
+	int (*handle_read)(uint8_t *regs, const struct emul *emul, int reg,
 			   int byte, char *buf);
 	/**
+	 * @brief Model specific finish read function. It should modify state of
+	 *        emulator if required.
+	 *
+	 * @param regs Pointer to array of emulator's registers
+	 * @param emul Pointer to BMI emulator
+	 * @param reg Selected register
+	 * @param bytes Number of bytes read
+	 *
+	 * @return 0 on success
+	 */
+	int (*finish_read)(uint8_t *regs, const struct emul *emul, int reg,
+			   int bytes);
+	/**
 	 * @brief Model specific reset function. It should modify state of
 	 *        emulator to imitate after reset conditions.
 	 *
 	 * @param regs Pointer to array of emulator's registers
 	 * @param emul Pointer to BMI emulator
 	 */
-	void (*reset)(uint8_t *regs, struct i2c_emul *emul);
+	void (*reset)(uint8_t *regs, const struct emul *emul);
 
 	/** Array of reserved bits mask for each register */
 	const uint8_t *rsvd_mask;
@@ -220,22 +234,13 @@ const struct bmi_emul_type_data *get_bmi160_emul_type_data(void);
 const struct bmi_emul_type_data *get_bmi260_emul_type_data(void);
 
 /**
- * @brief Get pointer to BMI emulator using device tree order number.
- *
- * @param ord Device tree order number obtained from DT_DEP_ORD macro
- *
- * @return Pointer to BMI emulator
- */
-struct i2c_emul *bmi_emul_get(int ord);
-
-/**
  * @brief Set value of given register of BMI
  *
  * @param emul Pointer to BMI emulator
  * @param reg Register address which value will be changed
  * @param val New value of the register
  */
-void bmi_emul_set_reg(struct i2c_emul *emul, int reg, uint8_t val);
+void bmi_emul_set_reg(const struct emul *emul, int reg, uint8_t val);
 
 /**
  * @brief Get value of given register of BMI
@@ -245,7 +250,7 @@ void bmi_emul_set_reg(struct i2c_emul *emul, int reg, uint8_t val);
  *
  * @return Value of the register
  */
-uint8_t bmi_emul_get_reg(struct i2c_emul *emul, int reg);
+uint8_t bmi_emul_get_reg(const struct emul *emul, int reg);
 
 /**
  * @brief Get internal value of offset for given axis and sensor
@@ -256,7 +261,7 @@ uint8_t bmi_emul_get_reg(struct i2c_emul *emul, int reg);
  * @return Offset of given axis. LSB for accelerometer is 0.061mg and for
  *         gyroscope is 0.0037°/s.
  */
-int16_t bmi_emul_get_off(struct i2c_emul *emul, enum bmi_emul_axis axis);
+int16_t bmi_emul_get_off(const struct emul *emul, enum bmi_emul_axis axis);
 
 /**
  * @brief Set internal value of offset for given axis and sensor
@@ -266,7 +271,7 @@ int16_t bmi_emul_get_off(struct i2c_emul *emul, enum bmi_emul_axis axis);
  * @param val New value of given axis. LSB for accelerometer is 0.061mg and for
  *            gyroscope is 0.0037°/s.
  */
-void bmi_emul_set_off(struct i2c_emul *emul, enum bmi_emul_axis axis,
+void bmi_emul_set_off(const struct emul *emul, enum bmi_emul_axis axis,
 		      int16_t val);
 
 /**
@@ -278,7 +283,7 @@ void bmi_emul_set_off(struct i2c_emul *emul, enum bmi_emul_axis axis,
  * @return Sensor value of given axis. LSB for accelerometer is 0.061mg and for
  *         gyroscope is 0.0037°/s.
  */
-int32_t bmi_emul_get_value(struct i2c_emul *emul, enum bmi_emul_axis axis);
+int32_t bmi_emul_get_value(const struct emul *emul, enum bmi_emul_axis axis);
 
 /**
  * @brief Set internal value of sensor for given axis
@@ -288,7 +293,7 @@ int32_t bmi_emul_get_value(struct i2c_emul *emul, enum bmi_emul_axis axis);
  * @param val New value of given axis. LSB for accelerometer is 0.061mg and for
  *            gyroscope is 0.0037°/s.
  */
-void bmi_emul_set_value(struct i2c_emul *emul, enum bmi_emul_axis axis,
+void bmi_emul_set_value(const struct emul *emul, enum bmi_emul_axis axis,
 			int32_t val);
 
 /**
@@ -298,7 +303,7 @@ void bmi_emul_set_value(struct i2c_emul *emul, enum bmi_emul_axis axis,
  * @param emul Pointer to BMI emulator
  * @param set Check for this error
  */
-void bmi_emul_set_err_on_ro_write(struct i2c_emul *emul, bool set);
+void bmi_emul_set_err_on_ro_write(const struct emul *emul, bool set);
 
 /**
  * @brief Set if error should be generated when reserved bits of register are
@@ -307,7 +312,7 @@ void bmi_emul_set_err_on_ro_write(struct i2c_emul *emul, bool set);
  * @param emul Pointer to BMI emulator
  * @param set Check for this error
  */
-void bmi_emul_set_err_on_rsvd_write(struct i2c_emul *emul, bool set);
+void bmi_emul_set_err_on_rsvd_write(const struct emul *emul, bool set);
 
 /**
  * @brief Set if error should be generated when write only register is read
@@ -315,7 +320,7 @@ void bmi_emul_set_err_on_rsvd_write(struct i2c_emul *emul, bool set);
  * @param emul Pointer to BMI emulator
  * @param set Check for this error
  */
-void bmi_emul_set_err_on_wo_read(struct i2c_emul *emul, bool set);
+void bmi_emul_set_err_on_wo_read(const struct emul *emul, bool set);
 
 /**
  * @brief Set if effect of simulated command should take place after simulated
@@ -324,7 +329,7 @@ void bmi_emul_set_err_on_wo_read(struct i2c_emul *emul, bool set);
  * @param emul Pointer to BMI emulator
  * @param set Simulate command execution time
  */
-void bmi_emul_simulate_cmd_exec_time(struct i2c_emul *emul, bool set);
+void bmi_emul_simulate_cmd_exec_time(const struct emul *emul, bool set);
 
 /**
  * @brief Set number of skipped frames. It will generate skip frame on next
@@ -333,7 +338,7 @@ void bmi_emul_simulate_cmd_exec_time(struct i2c_emul *emul, bool set);
  * @param emul Pointer to BMI emulator
  * @param skip Number of skipped frames
  */
-void bmi_emul_set_skipped_frames(struct i2c_emul *emul, uint8_t skip);
+void bmi_emul_set_skipped_frames(const struct emul *emul, uint8_t skip);
 
 /**
  * @brief Clear all FIFO frames, set current frame to empty and reset fifo_skip
@@ -343,14 +348,14 @@ void bmi_emul_set_skipped_frames(struct i2c_emul *emul, uint8_t skip);
  * @param tag_time Indicate if sensor time should be included in empty frame
  * @param header Indicate if header should be included in frame
  */
-void bmi_emul_flush_fifo(struct i2c_emul *emul, bool tag_time, bool header);
+void bmi_emul_flush_fifo(const struct emul *emul, bool tag_time, bool header);
 
 /**
  * @brief Restore registers backed by NVM, reset sensor time and flush FIFO
  *
  * @param emul Pointer to BMI emulator
  */
-void bmi_emul_reset_common(struct i2c_emul *emul, bool tag_time, bool header);
+void bmi_emul_reset_common(const struct emul *emul, bool tag_time, bool header);
 
 /**
  * @brief Set command end time to @p time ms from now
@@ -358,14 +363,14 @@ void bmi_emul_reset_common(struct i2c_emul *emul, bool tag_time, bool header);
  * @param emul Pointer to BMI emulator
  * @param time After this amount of ms command should end
  */
-void bmi_emul_set_cmd_end_time(struct i2c_emul *emul, int time);
+void bmi_emul_set_cmd_end_time(const struct emul *emul, int time);
 
 /**
  * @brief Check if command should end
  *
  * @param emul Pointer to BMI emulator
  */
-bool bmi_emul_is_cmd_end(struct i2c_emul *emul);
+bool bmi_emul_is_cmd_end(const struct emul *emul);
 
 /**
  * @brief Append FIFO @p frame to the emulator list of frames. It can be read
@@ -376,7 +381,8 @@ bool bmi_emul_is_cmd_end(struct i2c_emul *emul);
  *              emulator may use this frame (until flush of FIFO or reading
  *              it out through I2C)
  */
-void bmi_emul_append_frame(struct i2c_emul *emul, struct bmi_emul_frame *frame);
+void bmi_emul_append_frame(const struct emul *emul,
+			   struct bmi_emul_frame *frame);
 
 /**
  * @brief Get length of all frames that are on the emulator list of frames.
@@ -385,7 +391,7 @@ void bmi_emul_append_frame(struct i2c_emul *emul, struct bmi_emul_frame *frame);
  * @param tag_time Indicate if sensor time should be included in empty frame
  * @param header Indicate if header should be included in frame
  */
-uint16_t bmi_emul_fifo_len(struct i2c_emul *emul, bool tag_time, bool header);
+uint16_t bmi_emul_fifo_len(const struct emul *emul, bool tag_time, bool header);
 
 /**
  * @brief Get next byte that should be returned on FIFO data access.
@@ -400,9 +406,8 @@ uint16_t bmi_emul_fifo_len(struct i2c_emul *emul, bool tag_time, bool header);
  *
  * @return FIFO data byte
  */
-uint8_t bmi_emul_get_fifo_data(struct i2c_emul *emul, int byte,
-			       bool tag_time, bool header, int acc_shift,
-			       int gyr_shift);
+uint8_t bmi_emul_get_fifo_data(const struct emul *emul, int byte, bool tag_time,
+			       bool header, int acc_shift, int gyr_shift);
 
 /**
  * @brief Saves current internal state of sensors to emulator's registers.
@@ -419,10 +424,18 @@ uint8_t bmi_emul_get_fifo_data(struct i2c_emul *emul, int byte,
  * @param gyr_off_en Indicate if gyroscope offset should be included to
  *                   sensor data value
  */
-void bmi_emul_state_to_reg(struct i2c_emul *emul, int acc_shift,
+void bmi_emul_state_to_reg(const struct emul *emul, int acc_shift,
 			   int gyr_shift, int acc_reg, int gyr_reg,
 			   int sensortime_reg, bool acc_off_en,
 			   bool gyr_off_en);
+/**
+ * @brief Returns pointer to i2c_common_emul_data for given emul
+ *
+ * @param emul Pointer to BMI emulator
+ * @return Pointer to i2c_common_emul_data for emul argument
+ */
+struct i2c_common_emul_data *
+emul_bmi_get_i2c_common_data(const struct emul *emul);
 
 /**
  * @}
diff --git a/zephyr/include/emul/emul_clock_control.h b/zephyr/include/emul/emul_clock_control.h
index 1b3846b0f1..716bec5655 100644
--- a/zephyr/include/emul/emul_clock_control.h
+++ b/zephyr/include/emul/emul_clock_control.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/include/emul/emul_common_i2c.h b/zephyr/include/emul/emul_common_i2c.h
index 676308b027..1388e9bbcb 100644
--- a/zephyr/include/emul/emul_common_i2c.h
+++ b/zephyr/include/emul/emul_common_i2c.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -49,8 +49,8 @@
  * Special register values used in @ref i2c_common_emul_set_read_fail_reg and
  * @ref i2c_common_emul_set_write_fail_reg
  */
-#define I2C_COMMON_EMUL_FAIL_ALL_REG	(-1)
-#define I2C_COMMON_EMUL_NO_FAIL_REG	(-2)
+#define I2C_COMMON_EMUL_FAIL_ALL_REG (-1)
+#define I2C_COMMON_EMUL_NO_FAIL_REG (-2)
 
 /**
  * Describe if there is no ongoing I2C message or if there is message handled
@@ -67,20 +67,21 @@ enum i2c_common_emul_msg_state {
  * @brief Function type that is used by I2C device emulator for first byte of
  *        I2C write message.
  *
- * @param emul Pointer to emulator
+ * @param target Pointer to emulator
  * @param reg Address which is now accessed by write command (first byte of I2C
  *            write message)
  *
  * @return 0 on success
  * @return -EIO on error
  */
-typedef int (*i2c_common_emul_start_write_func)(struct i2c_emul *emul, int reg);
+typedef int (*i2c_common_emul_start_write_func)(const struct emul *target,
+						int reg);
 
 /**
  * @brief Function type that is used by I2C device emulator at the end of
  *        I2C write message.
  *
- * @param emul Pointer to emulator
+ * @param target Pointer to emulator
  * @param reg Address which is now accessed by write command (first byte of I2C
  *            write message)
  * @param bytes Number of bytes received from the I2C write message
@@ -88,14 +89,14 @@ typedef int (*i2c_common_emul_start_write_func)(struct i2c_emul *emul, int reg);
  * @return 0 on success
  * @return -EIO on error
  */
-typedef int (*i2c_common_emul_finish_write_func)(struct i2c_emul *emul, int reg,
-						 int bytes);
+typedef int (*i2c_common_emul_finish_write_func)(const struct emul *target,
+						 int reg, int bytes);
 
 /**
  * @brief Function type that is used by I2C device emulator on each byte of
  *        I2C write message (except first byte).
  *
- * @param emul Pointer to emulator
+ * @param target Pointer to emulator
  * @param reg Address which is now accessed by write command (first byte of I2C
  *            write message)
  * @param val Value of current byte
@@ -105,27 +106,28 @@ typedef int (*i2c_common_emul_finish_write_func)(struct i2c_emul *emul, int reg,
  * @return 0 on success
  * @return -EIO on error
  */
-typedef int (*i2c_common_emul_write_byte_func)(struct i2c_emul *emul, int reg,
-					       uint8_t val, int bytes);
+typedef int (*i2c_common_emul_write_byte_func)(const struct emul *target,
+					       int reg, uint8_t val, int bytes);
 
 /**
  * @brief Function type that is used by I2C device emulator before first byte of
  *        I2C read message.
  *
- * @param emul Pointer to emulator
+ * @param target Pointer to emulator
  * @param reg Address which is now accessed by read command (first byte of last
  *            I2C write message)
  *
  * @return 0 on success
  * @return -EIO on error
  */
-typedef int (*i2c_common_emul_start_read_func)(struct i2c_emul *emul, int reg);
+typedef int (*i2c_common_emul_start_read_func)(const struct emul *target,
+					       int reg);
 
 /**
  * @brief Function type that is used by I2C device emulator at the end of
  *        I2C read message.
  *
- * @param emul Pointer to emulator
+ * @param target Pointer to emulator
  * @param reg Address which is now accessed by read command (first byte of last
  *            I2C write message)
  * @param bytes Number of bytes responeded to the I2C read message
@@ -133,14 +135,14 @@ typedef int (*i2c_common_emul_start_read_func)(struct i2c_emul *emul, int reg);
  * @return 0 on success
  * @return -EIO on error
  */
-typedef int (*i2c_common_emul_finish_read_func)(struct i2c_emul *emul, int reg,
-						int bytes);
+typedef int (*i2c_common_emul_finish_read_func)(const struct emul *target,
+						int reg, int bytes);
 
 /**
  * @brief Function type that is used by I2C device emulator on each byte of
  *        I2C read message.
  *
- * @param emul Pointer to emulator
+ * @param target Pointer to emulator
  * @param reg Address which is now accessed by read command (first byte of last
  *            I2C write message)
  * @param val Pointer to buffer where current response byte should be stored
@@ -150,8 +152,8 @@ typedef int (*i2c_common_emul_finish_read_func)(struct i2c_emul *emul, int reg,
  * @return 0 on success
  * @return -EIO on error
  */
-typedef int (*i2c_common_emul_read_byte_func)(struct i2c_emul *emul, int reg,
-					      uint8_t *val, int bytes);
+typedef int (*i2c_common_emul_read_byte_func)(const struct emul *target,
+					      int reg, uint8_t *val, int bytes);
 
 /**
  * @brief Function type that is used by I2C device emulator to select register
@@ -159,7 +161,7 @@ typedef int (*i2c_common_emul_read_byte_func)(struct i2c_emul *emul, int reg,
  *        @ref i2c_common_emul_set_read_fail_reg and
  *        @ref i2c_common_emul_set_write_fail_reg
  *
- * @param emul Pointer to emulator
+ * @param target Pointer to emulator
  * @param reg Address which is now accessed by read/write command (first byte
  *            of last I2C write message)
  * @param bytes Number of bytes already processed in the I2C message handler
@@ -169,14 +171,14 @@ typedef int (*i2c_common_emul_read_byte_func)(struct i2c_emul *emul, int reg,
  * @return Register address that should be compared with user-defined fail
  *         register
  */
-typedef int (*i2c_common_emul_access_reg_func)(struct i2c_emul *emul, int reg,
-					       int bytes, bool read);
+typedef int (*i2c_common_emul_access_reg_func)(const struct emul *target,
+					       int reg, int bytes, bool read);
 
 /**
  * @brief Custom function type that is used as user-defined callback in read
  *        I2C messages handling.
  *
- * @param emul Pointer to emulator
+ * @param target Pointer to emulator
  * @param reg Address which is now accessed by read command (first byte of last
  *            I2C write message)
  * @param val Pointer to buffer where current response byte should be stored
@@ -188,14 +190,14 @@ typedef int (*i2c_common_emul_access_reg_func)(struct i2c_emul *emul, int reg,
  * @return 1 continue with normal emulator handler
  * @return negative on error
  */
-typedef int (*i2c_common_emul_read_func)(struct i2c_emul *emul, int reg,
+typedef int (*i2c_common_emul_read_func)(const struct emul *target, int reg,
 					 uint8_t *val, int bytes, void *data);
 
 /**
  * @brief Custom function type that is used as user-defined callback in write
  *        I2C messages handling.
  *
- * @param emul Pointer to emulator
+ * @param target Pointer to emulator
  * @param reg Address which is now accessed by write command (first byte of I2C
  *            write message)
  * @param val Value of current byte
@@ -207,13 +209,11 @@ typedef int (*i2c_common_emul_read_func)(struct i2c_emul *emul, int reg,
  * @return 1 continue with normal emulator handler
  * @return negative on error
  */
-typedef int (*i2c_common_emul_write_func)(struct i2c_emul *emul, int reg,
+typedef int (*i2c_common_emul_write_func)(const struct emul *target, int reg,
 					  uint8_t val, int bytes, void *data);
 
 /** Static configuration, common for all i2c emulators */
 struct i2c_common_emul_cfg {
-	/** Label of the I2C bus this emulator connects to */
-	const char *i2c_label;
 	/** Label of the I2C device being emulated */
 	const char *dev_label;
 	/** Pointer to run-time data */
@@ -283,31 +283,32 @@ extern struct i2c_emul_api i2c_common_emul_api;
  * @brief Lock access to emulator properties. After acquiring lock, user
  *        may change emulator behaviour in multi-thread setup.
  *
- * @param emul Pointer to emulator
+ * @param common_data Pointer to emulator common data
  * @param timeout Timeout in getting lock
  *
  * @return k_mutex_lock return code
  */
-int i2c_common_emul_lock_data(struct i2c_emul *emul, k_timeout_t timeout);
+int i2c_common_emul_lock_data(struct i2c_common_emul_data *common_data,
+			      k_timeout_t timeout);
 
 /**
  * @brief Unlock access to emulator properties.
  *
- * @param emul Pointer to emulator
+ * @param common_data Pointer to emulator common data
  *
  * @return k_mutex_unlock return code
  */
-int i2c_common_emul_unlock_data(struct i2c_emul *emul);
+int i2c_common_emul_unlock_data(struct i2c_common_emul_data *common_data);
 
 /**
  * @brief Set write handler for I2C messages. This function is called before
  *        generic handler.
  *
- * @param emul Pointer to emulator
+ * @param common_data Pointer to emulator common data
  * @param func Pointer to custom function
  * @param data User data passed on call of custom function
  */
-void i2c_common_emul_set_write_func(struct i2c_emul *emul,
+void i2c_common_emul_set_write_func(struct i2c_common_emul_data *common_data,
 				    i2c_common_emul_write_func func,
 				    void *data);
 
@@ -315,30 +316,32 @@ void i2c_common_emul_set_write_func(struct i2c_emul *emul,
  * @brief Set read handler for I2C messages. This function is called before
  *        generic handler.
  *
- * @param emul Pointer to emulator
+ * @param common_data Pointer to emulator common data
  * @param func Pointer to custom function
  * @param data User data passed on call of custom function
  */
-void i2c_common_emul_set_read_func(struct i2c_emul *emul,
+void i2c_common_emul_set_read_func(struct i2c_common_emul_data *common_data,
 				   i2c_common_emul_read_func func, void *data);
 
 /**
  * @brief Setup fail on read of given register of emulator
  *
- * @param emul Pointer to emulator
+ * @param common_data Pointer to emulator common data
  * @param reg Register address or one of special values
  *            (I2C_COMMON_EMUL_FAIL_ALL_REG, I2C_COMMON_EMUL_NO_FAIL_REG)
  */
-void i2c_common_emul_set_read_fail_reg(struct i2c_emul *emul, int reg);
+void i2c_common_emul_set_read_fail_reg(struct i2c_common_emul_data *common_data,
+				       int reg);
 
 /**
  * @brief Setup fail on write of given register of emulator
  *
- * @param emul Pointer to emulator
+ * @param common_data Pointer to emulator common data
  * @param reg Register address or one of special values
  *            (I2C_COMMON_EMUL_FAIL_ALL_REG, I2C_COMMON_EMUL_NO_FAIL_REG)
  */
-void i2c_common_emul_set_write_fail_reg(struct i2c_emul *emul, int reg);
+void i2c_common_emul_set_write_fail_reg(
+	struct i2c_common_emul_data *common_data, int reg);
 
 /**
  * @biref Emulate an I2C transfer to an emulator
@@ -347,7 +350,7 @@ void i2c_common_emul_set_write_fail_reg(struct i2c_emul *emul, int reg);
  * I2C message, calling user custom functions, failing on reading/writing
  * registers selected by user and calling device specific functions.
  *
- * @param emul I2C emulation information
+ * @param target The target peripheral emulated
  * @param msgs List of messages to process
  * @param num_msgs Number of messages to process
  * @param addr Address of the I2C target device
@@ -355,9 +358,15 @@ void i2c_common_emul_set_write_fail_reg(struct i2c_emul *emul, int reg);
  * @retval 0 If successful
  * @retval -EIO General input / output error
  */
-int i2c_common_emul_transfer(struct i2c_emul *emul, struct i2c_msg *msgs,
+int i2c_common_emul_transfer(const struct emul *target, struct i2c_msg *msgs,
 			     int num_msgs, int addr);
 
+int i2c_common_emul_transfer_workhorse(const struct emul *target,
+				       struct i2c_common_emul_data *data,
+				       const struct i2c_common_emul_cfg *cfg,
+				       struct i2c_msg *msgs, int num_msgs,
+				       int addr);
+
 /**
  * @brief Initialize common emulator data structure
  *
diff --git a/zephyr/include/emul/emul_flash.h b/zephyr/include/emul/emul_flash.h
new file mode 100644
index 0000000000..8148d4df96
--- /dev/null
+++ b/zephyr/include/emul/emul_flash.h
@@ -0,0 +1,22 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ *
+ * @brief Backend API for Cros flash emulator
+ */
+
+#ifndef ZEPHYR_INCLUDE_EMUL_EMUL_FLASH_H_
+#define ZEPHYR_INCLUDE_EMUL_EMUL_FLASH_H_
+
+#include <ec_commands.h>
+
+/**
+ * @brief Reset the protection.
+ */
+void cros_flash_emul_protect_reset(void);
+
+#endif /* ZEPHYR_INCLUDE_EMUL_EMUL_FLASH_H_ */
diff --git a/zephyr/include/emul/emul_isl923x.h b/zephyr/include/emul/emul_isl923x.h
index 5842cdcf02..e41cf26f87 100644
--- a/zephyr/include/emul/emul_isl923x.h
+++ b/zephyr/include/emul/emul_isl923x.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,14 +19,13 @@
 const struct device *isl923x_emul_get_parent(const struct emul *emulator);
 
 /**
- * @brief Get the I2C emulator struct
- *
- * This is generally coupled with calls to i2c_common_emul_* functions.
+ * @brief Get pointer to emulator i2c_common_emul_cfg
  *
  * @param emulator The emulator to look-up
- * @return Pointer to the I2C emulator struct
+ * @return Pointer to the i2c_common_emul_cfg struct
  */
-struct i2c_emul *isl923x_emul_get_i2c_emul(const struct emul *emulator);
+const struct i2c_common_emul_cfg *
+isl923x_emul_get_cfg(const struct emul *emulator);
 
 /**
  * @brief Reset all registers
@@ -94,6 +93,15 @@ void raa489000_emul_set_acok_pin(const struct emul *emulator, uint16_t value);
  * @param reg The address of the register to query
  * @return The 16-bit value of the register
  */
-uint16_t isl923x_emul_peek_reg(struct i2c_emul *i2c_emul, int reg);
+uint16_t isl923x_emul_peek_reg(const struct emul *emul, int reg);
+
+/**
+ * @brief Returns pointer to i2c_common_emul_data for argument emul
+ *
+ * @param emul Pointer to ISL923X emulator
+ * @return Pointer to i2c_common_emul_data from argument emul
+ */
+struct i2c_common_emul_data *
+emul_isl923x_get_i2c_common_data(const struct emul *emul);
 
 #endif /* ZEPHYR_INCLUDE_EMUL_EMUL_ISL923X_H_ */
diff --git a/zephyr/include/emul/emul_kb_raw.h b/zephyr/include/emul/emul_kb_raw.h
index ba4ea8e58f..1660ccefd4 100644
--- a/zephyr/include/emul/emul_kb_raw.h
+++ b/zephyr/include/emul/emul_kb_raw.h
@@ -1,8 +1,10 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors.
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include <stdint.h>
+
 /**
  * @file
  *
@@ -36,6 +38,13 @@ int emul_kb_raw_set_kbstate(const struct device *dev, uint8_t row, uint8_t col,
 			    int pressed);
 
 /**
+ * @brief Resets the keyboard to its initial state.
+ *
+ * @param dev Pointer to kb_raw emulator device.
+ */
+void emul_kb_raw_reset(const struct device *dev);
+
+/**
  * @}
  */
 
diff --git a/zephyr/include/emul/emul_lis2dw12.h b/zephyr/include/emul/emul_lis2dw12.h
index c61751183e..5410a54cdd 100644
--- a/zephyr/include/emul/emul_lis2dw12.h
+++ b/zephyr/include/emul/emul_lis2dw12.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,14 +10,6 @@
 #include <zephyr/drivers/i2c_emul.h>
 
 /**
- * @brief The the i2c emulator pointer from the top level emul.
- *
- * @param emul The emulator to query
- * @return Pointer to the i2c emulator struct
- */
-struct i2c_emul *lis2dw12_emul_to_i2c_emul(const struct emul *emul);
-
-/**
  * @brief Reset the state of the lis2dw12 emulator.
  *
  * @param emul The emulator to reset.
@@ -54,7 +46,7 @@ uint32_t lis2dw12_emul_get_soft_reset_count(const struct emul *emul);
  * @param reg The register to access
  * @return The value of the register
  */
-uint8_t lis2dw12_emul_peek_reg(struct i2c_emul *emul, int reg);
+uint8_t lis2dw12_emul_peek_reg(const struct emul *emul, int reg);
 
 /**
  * @brief Retrieves the ODR[3:0] bits from CRTL1 register
@@ -62,7 +54,7 @@ uint8_t lis2dw12_emul_peek_reg(struct i2c_emul *emul, int reg);
  * @param emul The emulator to query
  * @return The ODR bits, right-aligned
  */
-uint8_t lis2dw12_emul_peek_odr(struct i2c_emul *emul);
+uint8_t lis2dw12_emul_peek_odr(const struct emul *emul);
 
 /**
  * @brief Retrieves the MODE[1:0] bits from CRTL1 register
@@ -70,7 +62,7 @@ uint8_t lis2dw12_emul_peek_odr(struct i2c_emul *emul);
  * @param emul The emulator to query
  * @return The MODE bits, right-aligned
  */
-uint8_t lis2dw12_emul_peek_mode(struct i2c_emul *emul);
+uint8_t lis2dw12_emul_peek_mode(const struct emul *emul);
 
 /**
  * @brief Retrieves the LPMODE[1:0] bits from CRTL1 register
@@ -78,7 +70,7 @@ uint8_t lis2dw12_emul_peek_mode(struct i2c_emul *emul);
  * @param emul The emulator to query
  * @return The LPMODE bits, right-aligned
  */
-uint8_t lis2dw12_emul_peek_lpmode(struct i2c_emul *emul);
+uint8_t lis2dw12_emul_peek_lpmode(const struct emul *emul);
 
 /**
  * @brief Updates the current 3-axis acceleromter reading and
@@ -87,8 +79,7 @@ uint8_t lis2dw12_emul_peek_lpmode(struct i2c_emul *emul);
  * @param reading array of int X, Y, and Z readings.
  * @return 0 on success, or -EINVAL if readings are out of bounds.
  */
-int lis2dw12_emul_set_accel_reading(const struct emul *emul,
-				    intv3_t reading);
+int lis2dw12_emul_set_accel_reading(const struct emul *emul, intv3_t reading);
 
 /**
  * @brief Clears the current accelerometer reading and resets the
@@ -97,4 +88,13 @@ int lis2dw12_emul_set_accel_reading(const struct emul *emul,
  */
 void lis2dw12_emul_clear_accel_reading(const struct emul *emul);
 
+/**
+ * @brief Returns pointer to i2c_common_emul_data for argument emul
+ *
+ * @param emul Pointer to LIS2DW12 emulator
+ * @return Pointer to i2c_common_emul_data from argument emul
+ */
+struct i2c_common_emul_data *
+emul_lis2dw12_get_i2c_common_data(const struct emul *emul);
+
 #endif /* ZEPHYR_INCLUDE_EMUL_EMUL_LIS2DW12_H_ */
diff --git a/zephyr/include/emul/emul_ln9310.h b/zephyr/include/emul/emul_ln9310.h
index 6f34a15f93..0c0e61003e 100644
--- a/zephyr/include/emul/emul_ln9310.h
+++ b/zephyr/include/emul/emul_ln9310.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -80,4 +80,13 @@ bool ln9310_emul_is_init(const struct emul *emulator);
  */
 struct i2c_emul *ln9310_emul_get_i2c_emul(const struct emul *emulator);
 
+/**
+ * @brief Returns pointer to i2c_common_emul_data for argument emul
+ *
+ * @param emul Pointer to LN9310 emulator
+ * @return Pointer to i2c_common_emul_data from argument emul
+ */
+struct i2c_common_emul_data *
+emul_ln9310_get_i2c_common_data(const struct emul *emul);
+
 #endif /* ZEPHYR_INCLUDE_EMUL_EMUL_LN9310_H_ */
diff --git a/zephyr/include/emul/emul_pi3usb9201.h b/zephyr/include/emul/emul_pi3usb9201.h
index 93e87c20e0..05feff567f 100644
--- a/zephyr/include/emul/emul_pi3usb9201.h
+++ b/zephyr/include/emul/emul_pi3usb9201.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,15 +22,6 @@
 #define PI3USB9201_REG_HOST_STS 0x3
 
 /**
- * @brief Get pointer to pi3usb9201 emulator using device tree order number.
- *
- * @param ord Device tree order number obtained from DT_DEP_ORD macro
- *
- * @return Pointer to pi3usb9201 emulator
- */
-struct i2c_emul *pi3usb9201_emul_get(int ord);
-
-/**
  * @brief Set value of given register of pi3usb9201
  *
  * @param emul Pointer to pi3usb9201 emulator
@@ -39,7 +30,7 @@ struct i2c_emul *pi3usb9201_emul_get(int ord);
  *
  * @return 0 on success or error
  */
-int pi3usb9201_emul_set_reg(struct i2c_emul *emul, int reg, uint8_t val);
+int pi3usb9201_emul_set_reg(const struct emul *emul, int reg, uint8_t val);
 
 /**
  * @brief Get value of given register of pi3usb9201
@@ -50,6 +41,6 @@ int pi3usb9201_emul_set_reg(struct i2c_emul *emul, int reg, uint8_t val);
  *
  * @return 0 on success or error
  */
-int pi3usb9201_emul_get_reg(struct i2c_emul *emul, int reg, uint8_t *val);
+int pi3usb9201_emul_get_reg(const struct emul *emul, int reg, uint8_t *val);
 
 #endif /* __EMUL_PI3USB9201_H */
diff --git a/zephyr/include/emul/emul_rt9490.h b/zephyr/include/emul/emul_rt9490.h
new file mode 100644
index 0000000000..0cb4f7b076
--- /dev/null
+++ b/zephyr/include/emul/emul_rt9490.h
@@ -0,0 +1,15 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef EMUL_RT9490_H
+#define EMUL_RT9490_H
+
+#include <zephyr/drivers/emul.h>
+
+void rt9490_emul_reset_regs(const struct emul *emul);
+
+int rt9490_emul_peek_reg(const struct emul *emul, int reg);
+
+#endif
diff --git a/zephyr/include/emul/emul_smart_battery.h b/zephyr/include/emul/emul_smart_battery.h
index 034cb6915b..826e817992 100644
--- a/zephyr/include/emul/emul_smart_battery.h
+++ b/zephyr/include/emul/emul_smart_battery.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,6 +17,8 @@
 #include <zephyr/drivers/i2c_emul.h>
 #include <stdint.h>
 
+#include "emul/emul_common_i2c.h"
+
 /**
  * @brief Smart Battery emulator backend API
  * @defgroup sbat_emul Smart Battery emulator
@@ -38,11 +40,11 @@
  */
 
 /* Value used to indicate that no command is selected */
-#define SBAT_EMUL_NO_CMD	-1
+#define SBAT_EMUL_NO_CMD -1
 /* Maximum size of data that can be returned in SMBus block transaction */
-#define MAX_BLOCK_SIZE		32
+#define MAX_BLOCK_SIZE 32
 /* Maximum length of command to send is maximum size of data + len byte + PEC */
-#define MSG_BUF_LEN		(MAX_BLOCK_SIZE + 2)
+#define MSG_BUF_LEN (MAX_BLOCK_SIZE + 2)
 
 /** @brief Emulated smart battery properties */
 struct sbat_emul_bat_data {
@@ -65,6 +67,8 @@ struct sbat_emul_bat_data {
 	uint16_t error_code;
 	/** Design battery voltage in mV */
 	uint16_t design_mv;
+	/** Default Design battery voltage in mV */
+	const uint16_t default_design_mv;
 	/** Battery temperature at the moment in Kelvins */
 	uint16_t temp;
 	/** Battery voltage at the moment in mV */
@@ -77,8 +81,12 @@ struct sbat_emul_bat_data {
 	uint16_t max_error;
 	/** Capacity of the battery at the moment in mAh */
 	uint16_t cap;
+	/** Default capacity of the battery at the moment in mAh */
+	const uint16_t default_cap;
 	/** Full capacity of the battery in mAh */
 	uint16_t full_cap;
+	/** Default full capacity of the battery at the moment in mAh */
+	const uint16_t default_full_cap;
 	/** Design battery capacity in mAh */
 	uint16_t design_cap;
 	/** Charging current requested by battery */
@@ -111,25 +119,20 @@ struct sbat_emul_bat_data {
 	uint8_t mf_data[MAX_BLOCK_SIZE];
 	/** Manufacturer data length */
 	int mf_data_len;
+	/** Manufacture info */
+	uint8_t mf_info[MAX_BLOCK_SIZE];
+	/** Manufacture info length */
+	int mf_info_len;
 };
 
 /**
- * @brief Get pointer to smart battery emulator using device tree order number.
- *
- * @param ord Device tree order number obtained from DT_DEP_ORD macro
- *
- * @return Pointer to smart battery emulator
- */
-struct i2c_emul *sbat_emul_get_ptr(int ord);
-
-/**
  * @brief Function which allows to get properties of emulated smart battery
  *
  * @param emul Pointer to smart battery emulator
  *
  * @return Pointer to smart battery properties
  */
-struct sbat_emul_bat_data *sbat_emul_get_bat_data(struct i2c_emul *emul);
+struct sbat_emul_bat_data *sbat_emul_get_bat_data(const struct emul *emul);
 
 /**
  * @brief Convert date to format used by smart battery
@@ -156,7 +159,7 @@ uint16_t sbat_emul_date_to_word(unsigned int day, unsigned int month,
  * @return 1 if command is unknown or return type different then word
  * @return negative on error while reading value
  */
-int sbat_emul_get_word_val(struct i2c_emul *emul, int cmd, uint16_t *val);
+int sbat_emul_get_word_val(const struct emul *emul, int cmd, uint16_t *val);
 
 /**
  * @brief Function which gets return value for read commands that returns block
@@ -171,7 +174,7 @@ int sbat_emul_get_word_val(struct i2c_emul *emul, int cmd, uint16_t *val);
  * @return 1 if command is unknown or return type different then word
  * @return negative on error while reading value
  */
-int sbat_emul_get_block_data(struct i2c_emul *emul, int cmd, uint8_t **blk,
+int sbat_emul_get_block_data(const struct emul *emul, int cmd, uint8_t **blk,
 			     int *len);
 
 /**
@@ -184,10 +187,19 @@ int sbat_emul_get_block_data(struct i2c_emul *emul, int cmd, uint8_t **blk,
  * @param len Length of the response
  * @param fail If emulator should fail to send response
  */
-void sbat_emul_set_response(struct i2c_emul *emul, int cmd, uint8_t *buf,
+void sbat_emul_set_response(const struct emul *emul, int cmd, uint8_t *buf,
 			    int len, bool fail);
 
 /**
+ * @brief Returns pointer to i2c_common_emul_data for argument emul
+ *
+ * @param emul Pointer to smart_battery emulator
+ * @return Pointer to i2c_common_emul_data from argument emul
+ */
+struct i2c_common_emul_data *
+emul_smart_battery_get_i2c_common_data(const struct emul *emul);
+
+/**
  * @}
  */
 
diff --git a/zephyr/include/emul/emul_sn5s330.h b/zephyr/include/emul/emul_sn5s330.h
index cc5576819e..77141e679b 100644
--- a/zephyr/include/emul/emul_sn5s330.h
+++ b/zephyr/include/emul/emul_sn5s330.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -47,4 +47,13 @@ void sn5s330_emul_make_vbus_overcurrent(const struct emul *emul);
  */
 void sn5s330_emul_lower_vbus_below_minv(const struct emul *emul);
 
+/**
+ * @brief Returns pointer to i2c_common_emul_data for argument emul
+ *
+ * @param emul Pointer to SN5S330 emulator
+ * @return Pointer to i2c_common_emul_data from argument emul
+ */
+struct i2c_common_emul_data *
+emul_sn5s330_get_i2c_common_data(const struct emul *emul);
+
 #endif /* ZEPHYR_INCLUDE_EMUL_EMUL_SN5S330_H_ */
diff --git a/zephyr/include/emul/emul_stub_device.h b/zephyr/include/emul/emul_stub_device.h
new file mode 100644
index 0000000000..8eb8a60a28
--- /dev/null
+++ b/zephyr/include/emul/emul_stub_device.h
@@ -0,0 +1,42 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef ZEPHYR_INCLUDE_EMUL_STUB_DEVICE_H_
+#define ZEPHYR_INCLUDE_EMUL_STUB_DEVICE_H_
+
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+
+/*
+ * Needed for emulators without corresponding DEVICE_DT_DEFINE drivers
+ */
+
+struct emul_stub_dev_data {
+	/* Stub */
+};
+struct emul_stub_dev_config {
+	/* Stub */
+};
+struct emul_stub_dev_api {
+	/* Stub */
+};
+
+/* For every instance of a DT_DRV_COMPAT stub out a device for that instance */
+#define EMUL_STUB_DEVICE(n)                                                    \
+	__maybe_unused static int emul_init_stub_##n(const struct device *dev) \
+	{                                                                      \
+		ARG_UNUSED(dev);                                               \
+		return 0;                                                      \
+	}                                                                      \
+                                                                               \
+	/* Since this is only stub, allocate the structs once. */              \
+	static struct emul_stub_dev_data stub_data_##n;                        \
+	static struct emul_stub_dev_config stub_config_##n;                    \
+	static struct emul_stub_dev_api stub_api_##n;                          \
+	DEVICE_DT_INST_DEFINE(n, &emul_init_stub_##n, NULL, &stub_data_##n,    \
+			      &stub_config_##n, POST_KERNEL, 1,                \
+			      &stub_api_##n);
+
+#endif /* ZEPHYR_INCLUDE_EMUL_STUB_DEVICE_H_ */
diff --git a/zephyr/include/emul/emul_syv682x.h b/zephyr/include/emul/emul_syv682x.h
index f08960ccac..78ee2406eb 100644
--- a/zephyr/include/emul/emul_syv682x.h
+++ b/zephyr/include/emul/emul_syv682x.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,100 +17,91 @@
 /* Register info copied from syv682.h */
 
 /* SYV682x register addresses */
-#define SYV682X_STATUS_REG		0x00
-#define SYV682X_CONTROL_1_REG		0x01
-#define SYV682X_CONTROL_2_REG		0x02
-#define SYV682X_CONTROL_3_REG		0x03
-#define SYV682X_CONTROL_4_REG		0x04
+#define SYV682X_STATUS_REG 0x00
+#define SYV682X_CONTROL_1_REG 0x01
+#define SYV682X_CONTROL_2_REG 0x02
+#define SYV682X_CONTROL_3_REG 0x03
+#define SYV682X_CONTROL_4_REG 0x04
 
 /* Status Register */
-#define SYV682X_STATUS_OC_HV    BIT(7)
-#define SYV682X_STATUS_RVS      BIT(6)
-#define SYV682X_STATUS_OC_5V    BIT(5)
-#define SYV682X_STATUS_OVP      BIT(4)
-#define SYV682X_STATUS_FRS      BIT(3)
-#define SYV682X_STATUS_TSD      BIT(2)
+#define SYV682X_STATUS_OC_HV BIT(7)
+#define SYV682X_STATUS_RVS BIT(6)
+#define SYV682X_STATUS_OC_5V BIT(5)
+#define SYV682X_STATUS_OVP BIT(4)
+#define SYV682X_STATUS_FRS BIT(3)
+#define SYV682X_STATUS_TSD BIT(2)
 #define SYV682X_STATUS_VSAFE_5V BIT(1)
 #define SYV682X_STATUS_VSAFE_0V BIT(0)
 #define SYV682X_STATUS_INT_MASK 0xfc
-#define SYV682X_STATUS_NONE     0
+#define SYV682X_STATUS_NONE 0
 
 /* Control Register 1 */
-#define SYV682X_CONTROL_1_CH_SEL	BIT(1)
-#define SYV682X_CONTROL_1_HV_DR		BIT(2)
-#define SYV682X_CONTROL_1_PWR_ENB	BIT(7)
-
-#define SYV682X_5V_ILIM_MASK		0x18
-#define SYV682X_5V_ILIM_BIT_SHIFT	3
-#define SYV682X_5V_ILIM_1_25		0
-#define SYV682X_5V_ILIM_1_75		1
-#define SYV682X_5V_ILIM_2_25		2
-#define SYV682X_5V_ILIM_3_30		3
-
-#define SYV682X_HV_ILIM_MASK		0x60
-#define SYV682X_HV_ILIM_BIT_SHIFT	5
-#define SYV682X_HV_ILIM_1_25		0
-#define SYV682X_HV_ILIM_1_75		1
-#define SYV682X_HV_ILIM_3_30		2
-#define SYV682X_HV_ILIM_5_50		3
+#define SYV682X_CONTROL_1_CH_SEL BIT(1)
+#define SYV682X_CONTROL_1_HV_DR BIT(2)
+#define SYV682X_CONTROL_1_PWR_ENB BIT(7)
+
+#define SYV682X_5V_ILIM_MASK 0x18
+#define SYV682X_5V_ILIM_BIT_SHIFT 3
+#define SYV682X_5V_ILIM_1_25 0
+#define SYV682X_5V_ILIM_1_75 1
+#define SYV682X_5V_ILIM_2_25 2
+#define SYV682X_5V_ILIM_3_30 3
+
+#define SYV682X_HV_ILIM_MASK 0x60
+#define SYV682X_HV_ILIM_BIT_SHIFT 5
+#define SYV682X_HV_ILIM_1_25 0
+#define SYV682X_HV_ILIM_1_75 1
+#define SYV682X_HV_ILIM_3_30 2
+#define SYV682X_HV_ILIM_5_50 3
 
 /* Control Register 2 */
-#define SYV682X_OC_DELAY_MASK		GENMASK(7, 6)
-#define SYV682X_OC_DELAY_SHIFT		6
-#define SYV682X_OC_DELAY_1MS		0
-#define SYV682X_OC_DELAY_10MS		1
-#define SYV682X_OC_DELAY_50MS		2
-#define SYV682X_OC_DELAY_100MS		3
-#define SYV682X_DSG_TIME_MASK		GENMASK(5, 4)
-#define SYV682X_DSG_TIME_SHIFT		4
-#define SYV682X_DSG_TIME_50MS		0
-#define SYV682X_DSG_TIME_100MS		1
-#define SYV682X_DSG_TIME_200MS		2
-#define SYV682X_DSG_TIME_400MS		3
-#define SYV682X_DSG_RON_MASK		GENMASK(3, 2)
-#define SYV682X_DSG_RON_SHIFT		2
-#define SYV682X_DSG_RON_200_OHM		0
-#define SYV682X_DSG_RON_400_OHM		1
-#define SYV682X_DSG_RON_800_OHM		2
-#define SYV682X_DSG_RON_1600_OHM	3
-#define SYV682X_CONTROL_2_SDSG		BIT(1)
-#define SYV682X_CONTROL_2_FDSG		BIT(0)
+#define SYV682X_OC_DELAY_MASK GENMASK(7, 6)
+#define SYV682X_OC_DELAY_SHIFT 6
+#define SYV682X_OC_DELAY_1MS 0
+#define SYV682X_OC_DELAY_10MS 1
+#define SYV682X_OC_DELAY_50MS 2
+#define SYV682X_OC_DELAY_100MS 3
+#define SYV682X_DSG_TIME_MASK GENMASK(5, 4)
+#define SYV682X_DSG_TIME_SHIFT 4
+#define SYV682X_DSG_TIME_50MS 0
+#define SYV682X_DSG_TIME_100MS 1
+#define SYV682X_DSG_TIME_200MS 2
+#define SYV682X_DSG_TIME_400MS 3
+#define SYV682X_DSG_RON_MASK GENMASK(3, 2)
+#define SYV682X_DSG_RON_SHIFT 2
+#define SYV682X_DSG_RON_200_OHM 0
+#define SYV682X_DSG_RON_400_OHM 1
+#define SYV682X_DSG_RON_800_OHM 2
+#define SYV682X_DSG_RON_1600_OHM 3
+#define SYV682X_CONTROL_2_SDSG BIT(1)
+#define SYV682X_CONTROL_2_FDSG BIT(0)
 
 /* Control Register 3 */
-#define SYV682X_BUSY			BIT(7)
-#define SYV682X_RVS_MASK		BIT(3)
-#define SYV682X_RST_REG			BIT(0)
-#define SYV682X_OVP_MASK		0x70
-#define SYV682X_OVP_BIT_SHIFT		4
-#define SYV682X_OVP_06_0		0
-#define SYV682X_OVP_08_0		1
-#define SYV682X_OVP_11_1		2
-#define SYV682X_OVP_12_1		3
-#define SYV682X_OVP_14_2		4
-#define SYV682X_OVP_17_9		5
-#define SYV682X_OVP_21_6		6
-#define SYV682X_OVP_23_7		7
-#define SYV682X_CONTROL_3_NONE		0
+#define SYV682X_BUSY BIT(7)
+#define SYV682X_RVS_MASK BIT(3)
+#define SYV682X_RST_REG BIT(0)
+#define SYV682X_OVP_MASK 0x70
+#define SYV682X_OVP_BIT_SHIFT 4
+#define SYV682X_OVP_06_0 0
+#define SYV682X_OVP_08_0 1
+#define SYV682X_OVP_11_1 2
+#define SYV682X_OVP_12_1 3
+#define SYV682X_OVP_14_2 4
+#define SYV682X_OVP_17_9 5
+#define SYV682X_OVP_21_6 6
+#define SYV682X_OVP_23_7 7
+#define SYV682X_CONTROL_3_NONE 0
 
 /* Control Register 4 */
-#define SYV682X_CONTROL_4_CC1_BPS	BIT(7)
-#define SYV682X_CONTROL_4_CC2_BPS	BIT(6)
-#define SYV682X_CONTROL_4_VCONN1	BIT(5)
-#define SYV682X_CONTROL_4_VCONN2	BIT(4)
-#define SYV682X_CONTROL_4_VBAT_OVP	BIT(3)
-#define SYV682X_CONTROL_4_VCONN_OCP	BIT(2)
-#define SYV682X_CONTROL_4_CC_FRS	BIT(1)
-#define SYV682X_CONTROL_4_INT_MASK	0x0c
-#define SYV682X_CONTROL_4_NONE      0
-
-/**
- * @brief Get pointer to SYV682x emulator using device tree order number.
- *
- * @param ord Device tree order number obtained from DT_DEP_ORD macro
- *
- * @return Pointer to smart battery emulator
- */
-struct i2c_emul *syv682x_emul_get(int ord);
+#define SYV682X_CONTROL_4_CC1_BPS BIT(7)
+#define SYV682X_CONTROL_4_CC2_BPS BIT(6)
+#define SYV682X_CONTROL_4_VCONN1 BIT(5)
+#define SYV682X_CONTROL_4_VCONN2 BIT(4)
+#define SYV682X_CONTROL_4_VBAT_OVP BIT(3)
+#define SYV682X_CONTROL_4_VCONN_OCP BIT(2)
+#define SYV682X_CONTROL_4_CC_FRS BIT(1)
+#define SYV682X_CONTROL_4_INT_MASK 0x0c
+#define SYV682X_CONTROL_4_NONE 0
 
 /**
  * @brief Set the underlying interrupt conditions affecting the SYV682x
@@ -122,8 +113,8 @@ struct i2c_emul *syv682x_emul_get(int ord);
  *                  conditions; only the bits in SYV682X_CONTROL_4_INT_MASK have
  *                  an effect.
  */
-void syv682x_emul_set_condition(struct i2c_emul *emul, uint8_t status,
-		uint8_t control_4);
+void syv682x_emul_set_condition(const struct emul *emul, uint8_t status,
+				uint8_t control_4);
 
 /**
  * @brief Cause CONTROL_3[BUSY] to be set for a number of reads. This bit
@@ -133,7 +124,7 @@ void syv682x_emul_set_condition(struct i2c_emul *emul, uint8_t status,
  * @param emul  SYV682x emulator
  * @param reads The number of reads of CONTROL_3 to keep BUSY set for
  */
-void syv682x_emul_set_busy_reads(struct i2c_emul *emul, int reads);
+void syv682x_emul_set_busy_reads(const struct emul *emul, int reads);
 
 /**
  * @brief Set value of a register of SYV682x
@@ -144,7 +135,7 @@ void syv682x_emul_set_busy_reads(struct i2c_emul *emul, int reads);
  *
  * @return 0 on success, error code on error
  */
-int syv682x_emul_set_reg(struct i2c_emul *emul, int reg, uint8_t val);
+int syv682x_emul_set_reg(const struct emul *emul, int reg, uint8_t val);
 
 /**
  * @brief Get value of a register of SYV682x
@@ -155,6 +146,15 @@ int syv682x_emul_set_reg(struct i2c_emul *emul, int reg, uint8_t val);
  *
  * @return 0 on success, error code on error
  */
-int syv682x_emul_get_reg(struct i2c_emul *emul, int reg, uint8_t *val);
+int syv682x_emul_get_reg(const struct emul *emul, int reg, uint8_t *val);
+
+/**
+ * @brief Returns pointer to i2c_common_emul_data for given emul
+ *
+ * @param emul Pointer to SYV682X emulator
+ * @return common_data Pointer to i2c_common_emul_data
+ */
+struct i2c_common_emul_data *
+emul_syv682x_get_i2c_common_data(const struct emul *emul);
 
 #endif /* __EMUL_SYV682X_H */
diff --git a/zephyr/include/emul/emul_tcs3400.h b/zephyr/include/emul/emul_tcs3400.h
index a026f2624a..9daf8bce16 100644
--- a/zephyr/include/emul/emul_tcs3400.h
+++ b/zephyr/include/emul/emul_tcs3400.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -43,19 +43,19 @@
  * light, value obtainded with 128 cycles will be two times smaller than value
  * obtained with 256 cycles.
  */
-#define TCS_EMUL_MAX_CYCLES	256
+#define TCS_EMUL_MAX_CYCLES 256
 /**
  * Maximum gain supported by TCS3400. Value read from sensor is multiplied by
  * gain selected in CONTROL register.
  */
-#define TCS_EMUL_MAX_GAIN	64
+#define TCS_EMUL_MAX_GAIN 64
 
 /**
  * Emulator units are value returned with gain x64 and 256 integration cycles.
  * Max value is 1024 returned when gain is x1 and 1 integration cycle. Max value
  * represented in emulator units is 1024 * 64 * 256
  */
-#define TCS_EMUL_MAX_VALUE	(1024 * TCS_EMUL_MAX_GAIN * TCS_EMUL_MAX_CYCLES)
+#define TCS_EMUL_MAX_VALUE (1024 * TCS_EMUL_MAX_GAIN * TCS_EMUL_MAX_CYCLES)
 
 /** Axis argument used in @ref tcs_emul_set_val @ref tcs_emul_get_val */
 enum tcs_emul_axis {
@@ -70,18 +70,9 @@ enum tcs_emul_axis {
  * Emulator saves only those registers in memory. IR select is stored sparately
  * and other registers are write only.
  */
-#define TCS_EMUL_FIRST_REG	TCS_I2C_ENABLE
-#define TCS_EMUL_LAST_REG	TCS_I2C_BDATAH
-#define TCS_EMUL_REG_COUNT	(TCS_EMUL_LAST_REG - TCS_EMUL_FIRST_REG + 1)
-
-/**
- * @brief Get pointer to TCS3400 emulator using device tree order number.
- *
- * @param ord Device tree order number obtained from DT_DEP_ORD macro
- *
- * @return Pointer to TCS3400 emulator
- */
-struct i2c_emul *tcs_emul_get(int ord);
+#define TCS_EMUL_FIRST_REG TCS_I2C_ENABLE
+#define TCS_EMUL_LAST_REG TCS_I2C_BDATAH
+#define TCS_EMUL_REG_COUNT (TCS_EMUL_LAST_REG - TCS_EMUL_FIRST_REG + 1)
 
 /**
  * @brief Set value of given register of TCS3400
@@ -90,7 +81,7 @@ struct i2c_emul *tcs_emul_get(int ord);
  * @param reg Register address which value will be changed
  * @param val New value of the register
  */
-void tcs_emul_set_reg(struct i2c_emul *emul, int reg, uint8_t val);
+void tcs_emul_set_reg(const struct emul *emul, int reg, uint8_t val);
 
 /**
  * @brief Get value of given register of TCS3400
@@ -100,7 +91,7 @@ void tcs_emul_set_reg(struct i2c_emul *emul, int reg, uint8_t val);
  *
  * @return Value of the register
  */
-uint8_t tcs_emul_get_reg(struct i2c_emul *emul, int reg);
+uint8_t tcs_emul_get_reg(const struct emul *emul, int reg);
 
 /**
  * @brief Get internal value of light sensor for given axis
@@ -110,7 +101,7 @@ uint8_t tcs_emul_get_reg(struct i2c_emul *emul, int reg);
  *
  * @return Value of given axis with gain x64 and 256 integration cycles
  */
-int tcs_emul_get_val(struct i2c_emul *emul, enum tcs_emul_axis axis);
+int tcs_emul_get_val(const struct emul *emul, enum tcs_emul_axis axis);
 
 /**
  * @brief Set internal value of light sensor for given axis
@@ -120,7 +111,8 @@ int tcs_emul_get_val(struct i2c_emul *emul, enum tcs_emul_axis axis);
  * @param val New value of light sensor for given axis with gain x64 and
  *            256 integration cycles
  */
-void tcs_emul_set_val(struct i2c_emul *emul, enum tcs_emul_axis axis, int val);
+void tcs_emul_set_val(const struct emul *emul, enum tcs_emul_axis axis,
+		      int val);
 
 /**
  * @brief Set if error should be generated when read only register is being
@@ -129,7 +121,7 @@ void tcs_emul_set_val(struct i2c_emul *emul, enum tcs_emul_axis axis, int val);
  * @param emul Pointer to TCS3400 emulator
  * @param set Check for this error
  */
-void tcs_emul_set_err_on_ro_write(struct i2c_emul *emul, bool set);
+void tcs_emul_set_err_on_ro_write(const struct emul *emul, bool set);
 
 /**
  * @brief Set if error should be generated when reserved bits of register are
@@ -138,7 +130,7 @@ void tcs_emul_set_err_on_ro_write(struct i2c_emul *emul, bool set);
  * @param emul Pointer to TCS3400 emulator
  * @param set Check for this error
  */
-void tcs_emul_set_err_on_rsvd_write(struct i2c_emul *emul, bool set);
+void tcs_emul_set_err_on_rsvd_write(const struct emul *emul, bool set);
 
 /**
  * @brief Set if error should be generated when MSB register is accessed before
@@ -147,7 +139,16 @@ void tcs_emul_set_err_on_rsvd_write(struct i2c_emul *emul, bool set);
  * @param emul Pointer to TCS3400 emulator
  * @param set Check for this error
  */
-void tcs_emul_set_err_on_msb_first(struct i2c_emul *emul, bool set);
+void tcs_emul_set_err_on_msb_first(const struct emul *emul, bool set);
+
+/**
+ * @brief Returns pointer to i2c_common_emul_data for argument emul
+ *
+ * @param emul Pointer to tcs3400 emulator
+ * @return Pointer to i2c_common_emul_data from argument emul
+ */
+struct i2c_common_emul_data *
+emul_tcs3400_get_i2c_common_data(const struct emul *emul);
 
 /**
  * @}
diff --git a/zephyr/include/emul/i2c_mock.h b/zephyr/include/emul/i2c_mock.h
index e52c4e7440..e5c359a3fd 100644
--- a/zephyr/include/emul/i2c_mock.h
+++ b/zephyr/include/emul/i2c_mock.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -32,4 +32,13 @@ struct i2c_emul *i2c_mock_to_i2c_emul(const struct emul *emul);
  */
 uint16_t i2c_mock_get_addr(const struct emul *emul);
 
+/**
+ * @brief Returns pointer to i2c_common_emul_data for argument emul
+ *
+ * @param emul Pointer to i2c_mock emulator
+ * @return Pointer to i2c_common_emul_data from argument emul
+ */
+struct i2c_common_emul_data *
+emul_i2c_mock_get_i2c_common_data(const struct emul *emul);
+
 #endif /* ZEPHYR_INCLUDE_EMUL_I2C_MOCK_H_ */
diff --git a/zephyr/include/emul/tcpc/emul_ps8xxx.h b/zephyr/include/emul/tcpc/emul_ps8xxx.h
index aff21e94c7..6e96af571b 100644
--- a/zephyr/include/emul/tcpc/emul_ps8xxx.h
+++ b/zephyr/include/emul/tcpc/emul_ps8xxx.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -47,19 +47,20 @@ enum ps8xxx_emul_port {
 };
 
 /* For now all devices supported by this emulator has the same FW rev reg */
-#define PS8XXX_REG_FW_REV		0x82
+#define PS8XXX_REG_FW_REV 0x82
 
 /**
- * @brief Get pointer to specific "hidden" I2C device
+ * @brief Get pointer to i2c_common_data for specific "hidden" I2C device
  *
  * @param emul Pointer to PS8xxx emulator
  * @param port Select which "hidden" I2C device should be obtained
  *
  * @return NULL if given "hidden" I2C device cannot be found
- * @return pointer to "hidden" I2C device
+ * @return pointer to "hidden" device i2c_common_emul_data
  */
-struct i2c_emul *ps8xxx_emul_get_i2c_emul(const struct emul *emul,
-					  enum ps8xxx_emul_port port);
+struct i2c_common_emul_data *
+ps8xxx_emul_get_i2c_common_data(const struct emul *emul,
+				enum ps8xxx_emul_port port);
 
 /**
  * @brief Get pointer to TCPCI emulator that is base for PS8xxx emulator
diff --git a/zephyr/include/emul/tcpc/emul_tcpci.h b/zephyr/include/emul/tcpc/emul_tcpci.h
index dd225c5f6e..8175b9ce96 100644
--- a/zephyr/include/emul/tcpc/emul_tcpci.h
+++ b/zephyr/include/emul/tcpc/emul_tcpci.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,27 +17,13 @@
 #include <zephyr/drivers/i2c_emul.h>
 #include <usb_pd_tcpm.h>
 
+#include "emul/emul_common_i2c.h"
+
 /**
- * @brief TCPCI emulator backend API
- * @defgroup tcpci_emul TCPCI emulator
- * @{
- *
- * TCPCI emulator supports access to its registers using I2C messages.
- * It follows Type-C Port Controller Interface Specification. It is possible
- * to use this emulator as base for implementation of specific TCPC emulator
- * which follows TCPCI specification. Emulator allows to set callbacks
- * on change of CC status or transmitting message to implement partner emulator.
- * There is also callback used to inform about alert line state change.
- * Application may alter emulator state:
- *
- * - call @ref tcpci_emul_set_reg and @ref tcpci_emul_get_reg to set and get
- *   value of TCPCI registers
- * - call functions from emul_common_i2c.h to setup custom handlers for I2C
- *   messages
- * - call @ref tcpci_emul_add_rx_msg to setup received SOP messages
- * - call @ref tcpci_emul_get_tx_msg to examine sended message
- * - call @ref tcpci_emul_set_rev to set revision of emulated TCPCI
+ * Number of emulated register. This include vendor registers defined in TCPCI
+ * specification
  */
+#define TCPCI_EMUL_REG_COUNT 0x100
 
 /** SOP message structure */
 struct tcpci_emul_msg {
@@ -46,7 +32,7 @@ struct tcpci_emul_msg {
 	/** Number of bytes in buf */
 	int cnt;
 	/** Type of message (SOP, SOP', etc) */
-	uint8_t type;
+	uint8_t sop_type;
 	/** Index used to mark accessed byte */
 	int idx;
 	/** Pointer to optional second message */
@@ -64,6 +50,80 @@ struct tcpci_emul_msg {
 typedef void (*tcpci_emul_alert_state_func)(const struct emul *emul, bool alert,
 					    void *data);
 
+/** Run-time data used by the emulator */
+struct tcpci_ctx {
+	/** Common I2C data for TCPC */
+	struct i2c_common_emul_data common;
+
+	/** Current state of all emulated TCPCI registers */
+	uint8_t reg[TCPCI_EMUL_REG_COUNT];
+
+	/** Structures representing TX and RX buffers */
+	struct tcpci_emul_msg *rx_msg;
+	struct tcpci_emul_msg *tx_msg;
+
+	/** Data that should be written to register (except TX_BUFFER) */
+	uint16_t write_data;
+
+	/** Return error when trying to write to RO register */
+	bool error_on_ro_write;
+	/** Return error when trying to write 1 to reserved bit */
+	bool error_on_rsvd_write;
+
+	/** User function called when alert line could change */
+	tcpci_emul_alert_state_func alert_callback;
+	/** Data passed to alert_callback */
+	void *alert_callback_data;
+
+	/** Callbacks for TCPCI partner */
+	const struct tcpci_emul_partner_ops *partner;
+
+	/** Reference to Alert# GPIO emulator. */
+	const struct device *alert_gpio_port;
+	gpio_pin_t alert_gpio_pin;
+};
+
+/** Run-time data used by the emulator */
+struct tcpc_emul_data {
+	/** Pointer to the common TCPCI emulator context */
+	struct tcpci_ctx *tcpci_ctx;
+
+	/** Pointer to chip specific data */
+	void *chip_data;
+
+	const struct i2c_common_emul_cfg i2c_cfg;
+};
+
+#define TCPCI_EMUL_DEFINE(n, init, cfg_ptr, chip_data_ptr, bus_api)          \
+	static uint8_t tcpci_emul_tx_buf_##n[128];                           \
+	static struct tcpci_emul_msg tcpci_emul_tx_msg_##n = {               \
+		.buf = tcpci_emul_tx_buf_##n,                                \
+	};                                                                   \
+	static struct tcpci_ctx tcpci_ctx##n = {                             \
+		.tx_msg = &tcpci_emul_tx_msg_##n,                            \
+		.error_on_ro_write = true,                                   \
+		.error_on_rsvd_write = true,                                 \
+		.alert_gpio_port = COND_CODE_1(                              \
+			DT_INST_NODE_HAS_PROP(n, alert_gpio),                \
+			(DEVICE_DT_GET(DT_GPIO_CTLR(                         \
+				DT_INST_PROP(n, alert_gpio), gpios))),       \
+			(NULL)),                                             \
+		.alert_gpio_pin = COND_CODE_1(                               \
+			DT_INST_NODE_HAS_PROP(n, alert_gpio),                \
+			(DT_GPIO_PIN(DT_INST_PROP(n, alert_gpio), gpios)),   \
+			(0)),                                                \
+	};                                                                   \
+	static struct tcpc_emul_data tcpc_emul_data_##n = {                \
+		.tcpci_ctx = &tcpci_ctx##n,                                \
+		.chip_data = chip_data_ptr,                                \
+		.i2c_cfg = {                                               \
+			.dev_label = DT_NODE_FULL_NAME(DT_DRV_INST(n)),    \
+			.data = &tcpci_ctx##n.common,                      \
+			.addr = DT_INST_REG_ADDR(n),                       \
+		},                                                         \
+	}; \
+	EMUL_DT_INST_DEFINE(n, init, &tcpc_emul_data_##n, cfg_ptr, bus_api)
+
 /** Response from TCPCI specific device operations */
 enum tcpci_emul_ops_resp {
 	TCPCI_EMUL_CONTINUE = 0,
@@ -72,10 +132,7 @@ enum tcpci_emul_ops_resp {
 };
 
 /** Revisions supported by TCPCI emaluator */
-enum tcpci_emul_rev {
-	TCPCI_EMUL_REV1_0_VER1_0 = 0,
-	TCPCI_EMUL_REV2_0_VER1_1
-};
+enum tcpci_emul_rev { TCPCI_EMUL_REV1_0_VER1_0 = 0, TCPCI_EMUL_REV2_0_VER1_1 };
 
 /** Status of TX message send to TCPCI emulator partner */
 enum tcpci_emul_tx_status {
@@ -90,67 +147,6 @@ enum tcpci_emul_tx_status {
 	TCPCI_EMUL_TX_UNKNOWN
 };
 
-/** TCPCI specific device operations. Not all of them need to be implemented. */
-struct tcpci_emul_dev_ops {
-	/**
-	 * @brief Function called for each byte of read message
-	 *
-	 * @param emul Pointer to TCPCI emulator
-	 * @param ops Pointer to device operations structure
-	 * @param reg First byte of last write message
-	 * @param val Pointer where byte to read should be stored
-	 * @param bytes Number of bytes already readded
-	 *
-	 * @return TCPCI_EMUL_CONTINUE to continue with default handler
-	 * @return TCPCI_EMUL_DONE to immedietly return success
-	 * @return TCPCI_EMUL_ERROR to immedietly return error
-	 */
-	enum tcpci_emul_ops_resp (*read_byte)(const struct emul *emul,
-					const struct tcpci_emul_dev_ops *ops,
-					int reg, uint8_t *val, int bytes);
-
-	/**
-	 * @brief Function called for each byte of write message
-	 *
-	 * @param emul Pointer to TCPCI emulator
-	 * @param ops Pointer to device operations structure
-	 * @param reg First byte of write message
-	 * @param val Received byte of write message
-	 * @param bytes Number of bytes already received
-	 *
-	 * @return TCPCI_EMUL_CONTINUE to continue with default handler
-	 * @return TCPCI_EMUL_DONE to immedietly return success
-	 * @return TCPCI_EMUL_ERROR to immedietly return error
-	 */
-	enum tcpci_emul_ops_resp (*write_byte)(const struct emul *emul,
-					const struct tcpci_emul_dev_ops *ops,
-					int reg, uint8_t val, int bytes);
-
-	/**
-	 * @brief Function called on the end of write message
-	 *
-	 * @param emul Pointer to TCPCI emulator
-	 * @param ops Pointer to device operations structure
-	 * @param reg Register which is written
-	 * @param msg_len Length of handled I2C message
-	 *
-	 * @return TCPCI_EMUL_CONTINUE to continue with default handler
-	 * @return TCPCI_EMUL_DONE to immedietly return success
-	 * @return TCPCI_EMUL_ERROR to immedietly return error
-	 */
-	enum tcpci_emul_ops_resp (*handle_write)(const struct emul *emul,
-					const struct tcpci_emul_dev_ops *ops,
-					int reg, int msg_len);
-
-	/**
-	 * @brief Function called on reset
-	 *
-	 * @param emul Pointer to TCPCI emulator
-	 * @param ops Pointer to device operations structure
-	 */
-	void (*reset)(const struct emul *emul, struct tcpci_emul_dev_ops *ops);
-};
-
 /** TCPCI partner operations. Not all of them need to be implemented. */
 struct tcpci_emul_partner_ops {
 	/**
@@ -166,8 +162,7 @@ struct tcpci_emul_partner_ops {
 	void (*transmit)(const struct emul *emul,
 			 const struct tcpci_emul_partner_ops *ops,
 			 const struct tcpci_emul_msg *tx_msg,
-			 enum tcpci_msg_type type,
-			 int retry);
+			 enum tcpci_msg_type type, int retry);
 
 	/**
 	 * @brief Function called when control settings change to allow partner
@@ -201,18 +196,9 @@ struct tcpci_emul_partner_ops {
 };
 
 /**
- * @brief Get i2c_emul for TCPCI emulator
- *
- * @param emul Pointer to TCPCI emulator
- *
- * @return Pointer to I2C TCPCI emulator
- */
-struct i2c_emul *tcpci_emul_get_i2c_emul(const struct emul *emul);
-
-/**
  * @brief Set value of given register of TCPCI
  *
- * @param emul Pointer to TCPCI emulator
+ * @param emul Pointer to TCPC emulator
  * @param reg Register address which value will be changed
  * @param val New value of the register
  *
@@ -222,6 +208,68 @@ struct i2c_emul *tcpci_emul_get_i2c_emul(const struct emul *emul);
 int tcpci_emul_set_reg(const struct emul *emul, int reg, uint16_t val);
 
 /**
+ * @brief Function called for each byte of read message from TCPCI
+ *
+ * @param emul Pointer to TCPC emulator
+ * @param reg First byte of last write message
+ * @param val Pointer where byte to read should be stored
+ * @param bytes Number of bytes already readded
+ *
+ * @return 0 on success
+ */
+int tcpci_emul_read_byte(const struct emul *emul, int reg, uint8_t *val,
+			 int bytes);
+
+/**
+ * @brief Function called for each byte of write message from TCPCI.
+ *        Data are stored in write_data field of tcpci_emul_data or in tx_msg
+ *        in case of writing to TX buffer.
+ *
+ * @param emul Pointer to TCPC emulator
+ * @param reg First byte of write message
+ * @param val Received byte of write message
+ * @param bytes Number of bytes already received
+ *
+ * @return 0 on success
+ * @return -EIO on invalid write to TX buffer
+ */
+int tcpci_emul_write_byte(const struct emul *emul, int reg, uint8_t val,
+			  int bytes);
+
+/**
+ * @brief Handle I2C write message. It is checked if accessed register isn't RO
+ *        and reserved bits are set to 0.
+ *
+ * @param emul Pointer to TCPC emulator
+ * @param reg Register which is written
+ * @param msg_len Length of handled I2C message
+ *
+ * @return 0 on success
+ * @return -EIO on error
+ */
+int tcpci_emul_handle_write(const struct emul *emul, int reg, int msg_len);
+
+/**
+ * @brief Set up a new TCPCI emulator
+ *
+ * This should be called for each TCPC device that needs to be
+ * registered on the I2C bus.
+ *
+ * @param emul Pointer to TCPC emulator
+ * @param parent Pointer to emulated I2C bus
+ */
+void tcpci_emul_i2c_init(const struct emul *emul, const struct device *i2c_dev);
+
+/**
+ * @brief Reset registers to default values. Vendor and reserved registers
+ *        are not changed.
+ *
+ * @param emul Pointer to TCPC emulator
+ * @return 0 if successful
+ */
+int tcpci_emul_reset(const struct emul *emul);
+
+/**
  * @brief Get value of given register of TCPCI
  *
  * @param emul Pointer to TCPCI emulator
@@ -237,7 +285,7 @@ int tcpci_emul_get_reg(const struct emul *emul, int reg, uint16_t *val);
 /**
  * @brief Add up to two SOP RX messages
  *
- * @param emul Pointer to TCPCI emulator
+ * @param emul Pointer to TCPC emulator
  * @param rx_msg Pointer to message that is added
  * @param alert Select if alert register should be updated
  *
@@ -255,7 +303,7 @@ int tcpci_emul_add_rx_msg(const struct emul *emul,
 /**
  * @brief Get SOP TX message to examine what was sended by TCPM
  *
- * @param emul Pointer to TCPCI emulator
+ * @param emul Pointer to TCPC emulator
  *
  * @return Pointer to TX message
  */
@@ -264,24 +312,15 @@ struct tcpci_emul_msg *tcpci_emul_get_tx_msg(const struct emul *emul);
 /**
  * @brief Set TCPCI revision in PD_INT_REV register
  *
- * @param emul Pointer to TCPCI emulator
+ * @param emul Pointer to TCPC emulator
  * @param rev Requested revision
  */
 void tcpci_emul_set_rev(const struct emul *emul, enum tcpci_emul_rev rev);
 
 /**
- * @brief Set callbacks for specific TCPC device emulator
- *
- * @param emul Pointer to TCPCI emulator
- * @param dev_ops Pointer to callbacks
- */
-void tcpci_emul_set_dev_ops(const struct emul *emul,
-			    struct tcpci_emul_dev_ops *dev_ops);
-
-/**
  * @brief Set callback which is called when alert register is changed
  *
- * @param emul Pointer to TCPCI emulator
+ * @param emul Pointer to TCPC emulator
  * @param alert_callback Pointer to callback
  * @param alert_callback_data Pointer to data passed to callback as an argument
  */
@@ -292,7 +331,7 @@ void tcpci_emul_set_alert_callback(const struct emul *emul,
 /**
  * @brief Set callbacks for port partner device emulator
  *
- * @param emul Pointer to TCPCI emulator
+ * @param emul Pointer to TCPC emulator
  * @param partner Pointer to callbacks
  */
 void tcpci_emul_set_partner_ops(const struct emul *emul,
@@ -301,7 +340,7 @@ void tcpci_emul_set_partner_ops(const struct emul *emul,
 /**
  * @brief Emulate connection of specific device to emulated TCPCI
  *
- * @param emul Pointer to TCPCI emulator
+ * @param emul Pointer to TCPC emulator
  * @param partner_power_role Power role of connected partner (sink or source)
  * @param partner_cc1 Voltage on partner CC1 line (usually Rd or Rp)
  * @param partner_cc2 Voltage on partner CC2 line (usually open or Ra if active
@@ -321,7 +360,7 @@ int tcpci_emul_connect_partner(const struct emul *emul,
 
 /** @brief Emulate the disconnection of the partner device to emulated TCPCI
  *
- * @param emul Pointer to TCPCI emulator
+ * @param emul Pointer to TCPC emulator
  *
  * @return 0 on success
  */
@@ -330,13 +369,22 @@ int tcpci_emul_disconnect_partner(const struct emul *emul);
 /**
  * @brief Allows port partner to select if message was received correctly
  *
- * @param emul Pointer to TCPCI emulator
+ * @param emul Pointer to TCPC emulator
  * @param status Status of sended message
  */
 void tcpci_emul_partner_msg_status(const struct emul *emul,
 				   enum tcpci_emul_tx_status status);
 
 /**
+ * @brief Gets the common data associated with the tcpci chip overall
+ *
+ * @param emul Pointer to TCPC emulator
+ * @return Pointer to struct i2c_common_emul_data
+ */
+struct i2c_common_emul_data *
+emul_tcpci_generic_get_i2c_common_data(const struct emul *emul);
+
+/**
  * @}
  */
 
diff --git a/zephyr/include/emul/tcpc/emul_tcpci_partner_common.h b/zephyr/include/emul/tcpc/emul_tcpci_partner_common.h
index 4988c48576..fb715a47dc 100644
--- a/zephyr/include/emul/tcpc/emul_tcpci_partner_common.h
+++ b/zephyr/include/emul/tcpc/emul_tcpci_partner_common.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,6 +14,7 @@
 
 #include <zephyr/drivers/emul.h>
 #include <zephyr/kernel.h>
+#include <zephyr/sys/atomic.h>
 #include <stdbool.h>
 #include <stdint.h>
 
@@ -31,21 +32,20 @@
  */
 
 /** Timeout for other side to respond to PD message */
-#define TCPCI_PARTNER_RESPONSE_TIMEOUT_MS	30
-#define TCPCI_PARTNER_RESPONSE_TIMEOUT			\
-		K_MSEC(TCPCI_PARTNER_RESPONSE_TIMEOUT_MS)
+#define TCPCI_PARTNER_RESPONSE_TIMEOUT_MS 30
+#define TCPCI_PARTNER_RESPONSE_TIMEOUT K_MSEC(TCPCI_PARTNER_RESPONSE_TIMEOUT_MS)
 /** Timeout for source to transition to requested state after accept */
-#define TCPCI_PARTNER_TRANSITION_TIMEOUT_MS	550
-#define TCPCI_PARTNER_TRANSITION_TIMEOUT		\
-		K_MSEC(TCPCI_PARTNER_TRANSITION_TIMEOUT_MS)
+#define TCPCI_PARTNER_TRANSITION_TIMEOUT_MS 550
+#define TCPCI_PARTNER_TRANSITION_TIMEOUT \
+	K_MSEC(TCPCI_PARTNER_TRANSITION_TIMEOUT_MS)
 /** Timeout for source to send capability again after failure */
-#define TCPCI_SOURCE_CAPABILITY_TIMEOUT_MS	150
-#define TCPCI_SOURCE_CAPABILITY_TIMEOUT			\
-		K_MSEC(TCPCI_SOURCE_CAPABILITY_TIMEOUT_MS)
+#define TCPCI_SOURCE_CAPABILITY_TIMEOUT_MS 150
+#define TCPCI_SOURCE_CAPABILITY_TIMEOUT \
+	K_MSEC(TCPCI_SOURCE_CAPABILITY_TIMEOUT_MS)
 /** Timeout for source to send capability message after power swap */
-#define TCPCI_SWAP_SOURCE_START_TIMEOUT_MS	20
-#define TCPCI_SWAP_SOURCE_START_TIMEOUT			\
-		K_MSEC(TCPCI_SWAP_SOURCE_START_TIMEOUT_MS)
+#define TCPCI_SWAP_SOURCE_START_TIMEOUT_MS 20
+#define TCPCI_SWAP_SOURCE_START_TIMEOUT \
+	K_MSEC(TCPCI_SWAP_SOURCE_START_TIMEOUT_MS)
 
 /** Common data for TCPCI partner device emulators */
 struct tcpci_partner_data {
@@ -64,9 +64,13 @@ struct tcpci_partner_data {
 	/** Mutex for to_send queue */
 	struct k_mutex to_send_mutex;
 	/** Next SOP message id */
-	int msg_id;
+	int sop_msg_id;
+	/** Next SOP' message id */
+	int sop_prime_msg_id;
 	/** Last received message id */
-	int recv_msg_id;
+	int sop_recv_msg_id;
+	/** Last received SOP' message id */
+	int sop_prime_recv_msg_id;
 	/** Power role (used in message header) */
 	enum pd_power_role power_role;
 	/** Data role (used in message header) */
@@ -100,7 +104,7 @@ struct tcpci_partner_data {
 	 */
 	bool in_soft_reset;
 	/** Current AMS Control request being handled */
-	enum pd_ctrl_msg_type  cur_ams_ctrl_req;
+	enum pd_ctrl_msg_type cur_ams_ctrl_req;
 	/**
 	 * If common code should send GoodCRC for each message. If false,
 	 * then one of extensions should call tcpci_emul_partner_msg_status().
@@ -129,6 +133,15 @@ struct tcpci_partner_data {
 	 * any status to received message.
 	 */
 	enum tcpci_emul_tx_status *received_msg_status;
+	/** Whether port partner is configured in DisplayPort mode */
+	bool displayport_configured;
+	/** The number of Enter Mode REQs received since connection
+	 *  or the last Hard Reset, whichever was more recent.
+	 */
+	atomic_t mode_enter_attempts;
+	/* SVID of entered mode (0 if no mode is entered) */
+	uint16_t entered_svid;
+
 	/* VDMs with which the partner responds to discovery REQs. The VDM
 	 * buffers include the VDM header, and the VDO counts include 1 for the
 	 * VDM header. This structure has space for the mode response for a
@@ -140,6 +153,49 @@ struct tcpci_partner_data {
 	int svids_vdos;
 	uint32_t modes_vdm[VDO_MAX_SIZE];
 	int modes_vdos;
+	/* VDMs sent when responding to a mode entry command */
+	uint32_t enter_mode_vdm[VDO_MAX_SIZE];
+	int enter_mode_vdos;
+	/* VDMs sent when responding to DisplayPort status update command */
+	uint32_t dp_status_vdm[VDO_MAX_SIZE];
+	int dp_status_vdos;
+	/* VDMs sent when responding to DisplayPort config command */
+	uint32_t dp_config_vdm[VDO_MAX_SIZE];
+	int dp_config_vdos;
+	struct {
+		/* Index of the last battery we requested capabilities for. The
+		 * BCDB response does not include the index so we need to track
+		 * it manually. -1 indicates no outstanding request.
+		 */
+		int index;
+		/* Stores Battery Capability Data Blocks (BCDBs) requested and
+		 * received from the TCPM for later analysis. See USB-PD spec
+		 * Rev 3.1, Ver 1.3 section 6.5.5
+		 */
+		struct pd_bcdb bcdb[PD_BATT_MAX];
+		/* Stores a boolean status for each battery index indicating
+		 * whether we have received a BCDB response for that battery.
+		 */
+		bool have_response[PD_BATT_MAX];
+	} battery_capabilities;
+
+	/*
+	 * Cable which is "plugged in" to this port partner
+	 * Note: Much as in real life, cable should be attached before the port
+	 * partner can be plugged in to properly discover its information.
+	 * For tests, this means this poitner should be set before connecting
+	 * the source or sink partner.
+	 */
+	struct tcpci_cable_data *cable;
+};
+
+struct tcpci_cable_data {
+	/*
+	 * Identity VDM ACKs which the cable is expected to send
+	 * These include the VDM header
+	 */
+	uint32_t identity_vdm[VDO_MAX_SIZE];
+	int identity_vdos;
 };
 
 /** Structure of message used by TCPCI partner emulator */
@@ -150,10 +206,17 @@ struct tcpci_partner_msg {
 	struct tcpci_emul_msg msg;
 	/** Time when message should be sent if message is delayed */
 	uint64_t time;
-	/** Type of the message */
+	/** Message type that is placed in the Message Header. Its meaning
+	 *  depends on the class of message:
+	 *   - for Control Messages, see `enum pd_ctrl_msg_type`
+	 *   - for Data Messages, see `enum pd_data_msg_type`
+	 *   - for Extended Messages, see `enum pd_ext_msg_type`
+	 */
 	int type;
 	/** Number of data objects */
 	int data_objects;
+	/** True if this is an extended message */
+	bool extended;
 };
 
 /** Identify sender of logged PD message */
@@ -184,7 +247,8 @@ struct tcpci_partner_log_msg {
 enum tcpci_partner_handler_res {
 	TCPCI_PARTNER_COMMON_MSG_HANDLED,
 	TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED,
-	TCPCI_PARTNER_COMMON_MSG_HARD_RESET
+	TCPCI_PARTNER_COMMON_MSG_HARD_RESET,
+	TCPCI_PARTNER_COMMON_MSG_NO_GOODCRC,
 };
 
 /** Structure of TCPCI partner extension */
@@ -230,9 +294,8 @@ struct tcpci_partner_extension_ops {
 	 * @param ext Pointer to partner extension
 	 * @param common_data Pointer to TCPCI partner emulator
 	 */
-	void (*hard_reset)(
-		struct tcpci_partner_extension *ext,
-		struct tcpci_partner_data *common_data);
+	void (*hard_reset)(struct tcpci_partner_extension *ext,
+			   struct tcpci_partner_data *common_data);
 
 	/**
 	 * @brief Function called when SoftReset message is received
@@ -240,9 +303,8 @@ struct tcpci_partner_extension_ops {
 	 * @param ext Pointer to partner extension
 	 * @param common_data Pointer to TCPCI partner emulator
 	 */
-	void (*soft_reset)(
-		struct tcpci_partner_extension *ext,
-		struct tcpci_partner_data *common_data);
+	void (*soft_reset)(struct tcpci_partner_extension *ext,
+			   struct tcpci_partner_data *common_data);
 
 	/**
 	 * @brief Function called when partner emulator is disconnected from
@@ -251,9 +313,8 @@ struct tcpci_partner_extension_ops {
 	 * @param ext Pointer to partner extension
 	 * @param common_data Pointer to TCPCI partner emulator
 	 */
-	void (*disconnect)(
-		struct tcpci_partner_extension *ext,
-		struct tcpci_partner_data *common_data);
+	void (*disconnect)(struct tcpci_partner_extension *ext,
+			   struct tcpci_partner_data *common_data);
 
 	/**
 	 * @brief Function called when partner emulator is connected to TCPM.
@@ -265,9 +326,8 @@ struct tcpci_partner_extension_ops {
 	 * @return Negative value on error
 	 * @return 0 on success
 	 */
-	int (*connect)(
-		struct tcpci_partner_extension *ext,
-		struct tcpci_partner_data *common_data);
+	int (*connect)(struct tcpci_partner_extension *ext,
+		       struct tcpci_partner_data *common_data);
 };
 
 /**
@@ -280,17 +340,6 @@ struct tcpci_partner_extension_ops {
 void tcpci_partner_init(struct tcpci_partner_data *data, enum pd_rev_type rev);
 
 /**
- * @brief Allocate message with space for header and given number of data
- *        objects. Type of message is set to TCPCI_MSG_SOP by default.
- *
- * @param data_objects Number of data objects in message
- *
- * @return Pointer to new message on success
- * @return NULL on error
- */
-struct tcpci_partner_msg *tcpci_partner_alloc_msg(int data_objects);
-
-/**
  * @brief Free message's memory
  *
  * @param msg Pointer to message
@@ -336,8 +385,7 @@ int tcpci_partner_send_msg(struct tcpci_partner_data *data,
  * @return negative on failure
  */
 int tcpci_partner_send_control_msg(struct tcpci_partner_data *data,
-				   enum pd_ctrl_msg_type type,
-				   uint64_t delay);
+				   enum pd_ctrl_msg_type type, uint64_t delay);
 
 /**
  * @brief Send data message with optional delay. Data objects are copied to
@@ -356,9 +404,22 @@ int tcpci_partner_send_control_msg(struct tcpci_partner_data *data,
  * @return negative on failure
  */
 int tcpci_partner_send_data_msg(struct tcpci_partner_data *data,
-				enum pd_data_msg_type type,
-				uint32_t *data_obj, int data_obj_num,
-				uint64_t delay);
+				enum pd_data_msg_type type, uint32_t *data_obj,
+				int data_obj_num, uint64_t delay);
+
+/**
+ * @brief Send an extended PD message to the port partner
+ *
+ * @param data Pointer to TCPCI partner emulator
+ * @param type Extended message type
+ * @param delay Message send delay in milliseconds, or zero for no delay.
+ * @param payload Pointer to data payload. Does not include any headers.
+ * @param payload_size Number of bytes in above payload
+ * @return negative on failure, 0 on success
+ */
+int tcpci_partner_send_extended_msg(struct tcpci_partner_data *data,
+				    enum pd_ext_msg_type type, uint64_t delay,
+				    uint8_t *payload, size_t payload_size);
 
 /**
  * @brief Remove all messages that are in delayed message queue
@@ -387,6 +448,25 @@ void tcpci_partner_common_send_hard_reset(struct tcpci_partner_data *data);
 void tcpci_partner_common_send_soft_reset(struct tcpci_partner_data *data);
 
 /**
+ * @brief Send a Get Battery Capabilities request to the TCPM
+ *
+ * @param data Pointer to TCPCI partner emulator
+ * @param battery_index Request capability info on this battery. Must
+ *        be (0 <= battery_index < PD_BATT_MAX)
+ */
+void tcpci_partner_common_send_get_battery_capabilities(
+	struct tcpci_partner_data *data, int battery_index);
+
+/**
+ * @brief Resets the data structure used for tracking battery capability
+ *        requests and responses.
+ *
+ * @param data Emulator state
+ */
+void tcpci_partner_reset_battery_capability_state(
+	struct tcpci_partner_data *data);
+
+/**
  * @brief Start sender response timer for TCPCI_PARTNER_RESPONSE_TIMEOUT_MS.
  *        If @ref tcpci_partner_stop_sender_response_timer wasn't called before
  *        timeout, @ref tcpci_partner_sender_response_timeout is called.
diff --git a/zephyr/include/emul/tcpc/emul_tcpci_partner_drp.h b/zephyr/include/emul/tcpc/emul_tcpci_partner_drp.h
index fcc8d6a85a..e4f58fcd37 100644
--- a/zephyr/include/emul/tcpc/emul_tcpci_partner_drp.h
+++ b/zephyr/include/emul/tcpc/emul_tcpci_partner_drp.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -55,12 +55,12 @@ struct tcpci_drp_emul_data {
  *
  * @return Pointer to USB-C DRP extension
  */
-struct tcpci_partner_extension *tcpci_drp_emul_init(
-	struct tcpci_drp_emul_data *data,
-	struct tcpci_partner_data *common_data,
-	enum pd_power_role power_role,
-	struct tcpci_partner_extension *src_ext,
-	struct tcpci_partner_extension *snk_ext);
+struct tcpci_partner_extension *
+tcpci_drp_emul_init(struct tcpci_drp_emul_data *data,
+		    struct tcpci_partner_data *common_data,
+		    enum pd_power_role power_role,
+		    struct tcpci_partner_extension *src_ext,
+		    struct tcpci_partner_extension *snk_ext);
 
 /**
  * @brief Set correct flags for first capabilities PDO to indicate that this
diff --git a/zephyr/include/emul/tcpc/emul_tcpci_partner_faulty_ext.h b/zephyr/include/emul/tcpc/emul_tcpci_partner_faulty_ext.h
new file mode 100644
index 0000000000..f0627c95bd
--- /dev/null
+++ b/zephyr/include/emul/tcpc/emul_tcpci_partner_faulty_ext.h
@@ -0,0 +1,101 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ *
+ * @brief Backend API for USB-C malfunctioning device emulator
+ */
+
+#ifndef __EMUL_TCPCI_PARTNER_FAULTY_EXT_H
+#define __EMUL_TCPCI_PARTNER_FAULTY_EXT_H
+
+#include <zephyr/drivers/emul.h>
+#include "emul/tcpc/emul_tcpci.h"
+#include "emul/tcpc/emul_tcpci_partner_common.h"
+#include "usb_pd.h"
+
+/**
+ * @brief USB-C malfunctioning device extension backend API
+ * @defgroup tcpci_faulty_ext USB-C malfunctioning device extension
+ * @{
+ *
+ * USB-C malfunctioning device extension can be used with TCPCI partner
+ * emulator. It can be configured to not respond to source capability message
+ * (by not sending GoodCRC or Request after GoodCRC).
+ */
+
+/** Structure describing malfunctioning emulator data */
+struct tcpci_faulty_ext_data {
+	struct tcpci_partner_extension ext;
+	/* List of action to perform */
+	struct k_fifo action_list;
+};
+
+/** Actions that can be performed by malfunctioning emulator */
+enum tcpci_faulty_ext_action_type {
+	/**
+	 * Fail to receive SourceCapabilities message. From TCPM point of view,
+	 * GoodCRC message is not received.
+	 */
+	TCPCI_FAULTY_EXT_FAIL_SRC_CAP = BIT(0),
+	/**
+	 * Ignore to respond to SourceCapabilities message with Request message.
+	 * From TCPM point of view, GoodCRC message is received, but Request is
+	 * missing.
+	 */
+	TCPCI_FAULTY_EXT_IGNORE_SRC_CAP = BIT(1),
+	/** Discard SourceCapabilities message and send Accept message */
+	TCPCI_FAULTY_EXT_DISCARD_SRC_CAP = BIT(2),
+};
+
+/** Structure to put in malfunctioning emulator action list */
+struct tcpci_faulty_ext_action {
+	/* Reserved for FIFO */
+	void *fifo_reserved;
+	/* Actions that emulator should perform */
+	uint32_t action_mask;
+	/* Number of times to repeat action */
+	int count;
+};
+
+/* Count of actions which is treated by emulator as infinite */
+#define TCPCI_FAULTY_EXT_INFINITE_ACTION 0
+
+/**
+ * @brief Initialise USB-C malfunctioning device data structure
+ *
+ * @param data Pointer to USB-C malfunctioning device emulator data
+ * @param common_data Pointer to USB-C device emulator common data
+ * @param ext Pointer to next USB-C emulator extension
+ *
+ * @return Pointer to USB-C malfunctioning extension
+ */
+struct tcpci_partner_extension *
+tcpci_faulty_ext_init(struct tcpci_faulty_ext_data *data,
+		      struct tcpci_partner_data *common_data,
+		      struct tcpci_partner_extension *ext);
+
+/**
+ * @brief Add action to perform by USB-C malfunctioning extension
+ *
+ * @param data Pointer to USB-C malfunctioning device extension data
+ * @param action Non standard behavior to perform by emulator
+ */
+void tcpci_faulty_ext_append_action(struct tcpci_faulty_ext_data *data,
+				    struct tcpci_faulty_ext_action *action);
+
+/**
+ * @brief Clear all actions of USB-C malfunctioning extension
+ *
+ * @param data Pointer to USB-C malfunctioning device extension data
+ */
+void tcpci_faulty_ext_clear_actions_list(struct tcpci_faulty_ext_data *data);
+
+/**
+ * @}
+ */
+
+#endif /* __EMUL_TCPCI_PARTNER_FAULTY_EXT_H */
diff --git a/zephyr/include/emul/tcpc/emul_tcpci_partner_faulty_snk.h b/zephyr/include/emul/tcpc/emul_tcpci_partner_faulty_snk.h
deleted file mode 100644
index 8334f5f01d..0000000000
--- a/zephyr/include/emul/tcpc/emul_tcpci_partner_faulty_snk.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * @file
- *
- * @brief Backend API for USB-C malfunctioning sink device emulator
- */
-
-#ifndef __EMUL_TCPCI_PARTNER_FAULTY_SNK_H
-#define __EMUL_TCPCI_PARTNER_FAULTY_SNK_H
-
-#include <zephyr/drivers/emul.h>
-#include "emul/tcpc/emul_tcpci.h"
-#include "emul/tcpc/emul_tcpci_partner_common.h"
-#include "emul/tcpc/emul_tcpci_partner_snk.h"
-#include "usb_pd.h"
-
-/**
- * @brief USB-C malfunctioning sink device extension backend API
- * @defgroup tcpci_faulty_snk_emul USB-C malfunctioning sink device extension
- * @{
- *
- * USB-C malfunctioning sink device extension can be used with TCPCI partner
- * emulator. It can be configured to not respond to source capability message
- * (by not sending GoodCRC or Request after GoodCRC).
- */
-
-/** Structure describing malfunctioning sink emulator data */
-struct tcpci_faulty_snk_emul_data {
-	struct tcpci_partner_extension ext;
-	/* List of action to perform */
-	struct k_fifo action_list;
-};
-
-/** Actions that can be performed by malfunctioning sink emulator */
-enum tcpci_faulty_snk_action_type {
-	/**
-	 * Fail to receive SourceCapabilities message. From TCPM point of view,
-	 * GoodCRC message is not received.
-	 */
-	TCPCI_FAULTY_SNK_FAIL_SRC_CAP = BIT(0),
-	/**
-	 * Ignore to respond to SourceCapabilities message with Request message.
-	 * From TCPM point of view, GoodCRC message is received, but Request is
-	 * missing.
-	 */
-	TCPCI_FAULTY_SNK_IGNORE_SRC_CAP = BIT(1),
-	/** Discard SourceCapabilities message and send Accept message */
-	TCPCI_FAULTY_SNK_DISCARD_SRC_CAP = BIT(2),
-};
-
-/** Structure to put in malfunctioning sink emulator action list */
-struct tcpci_faulty_snk_action {
-	/* Reserved for FIFO */
-	void *fifo_reserved;
-	/* Actions that emulator should perform */
-	uint32_t action_mask;
-	/* Number of times to repeat action */
-	int count;
-};
-
-/* Count of actions which is treated by emulator as infinite */
-#define TCPCI_FAULTY_SNK_INFINITE_ACTION	0
-
-/**
- * @brief Initialise USB-C malfunctioning sink device data structure
- *
- * @param data Pointer to USB-C malfunctioning sink device emulator data
- * @param common_data Pointer to USB-C device emulator common data
- * @param ext Pointer to next USB-C emulator extension
- *
- * @return Pointer to USB-C malfunctioning sink extension
- */
-struct tcpci_partner_extension *tcpci_faulty_snk_emul_init(
-	struct tcpci_faulty_snk_emul_data *data,
-	struct tcpci_partner_data *common_data,
-	struct tcpci_partner_extension *ext);
-
-/**
- * @brief Add action to perform by USB-C malfunctioning sink extension
- *
- * @param data Pointer to USB-C malfunctioning sink device extension data
- * @param action Non standard behavior to perform by emulator
- */
-void tcpci_faulty_snk_emul_append_action(
-	struct tcpci_faulty_snk_emul_data *data,
-	struct tcpci_faulty_snk_action *action);
-
-/**
- * @brief Clear all actions of USB-C malfunctioning sink extension
- *
- * @param data Pointer to USB-C malfunctioning sink device extension data
- */
-void tcpci_faulty_snk_emul_clear_actions_list(
-	struct tcpci_faulty_snk_emul_data *data);
-
-/**
- * @}
- */
-
-#endif /* __EMUL_TCPCI_PARTNER_FAULTY_SNK_H */
diff --git a/zephyr/include/emul/tcpc/emul_tcpci_partner_snk.h b/zephyr/include/emul/tcpc/emul_tcpci_partner_snk.h
index 5e23a770da..584458942b 100644
--- a/zephyr/include/emul/tcpc/emul_tcpci_partner_snk.h
+++ b/zephyr/include/emul/tcpc/emul_tcpci_partner_snk.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -41,6 +41,8 @@ struct tcpci_snk_emul_data {
 	bool ping_received;
 	/** PD_DATA_ALERT message received  */
 	bool alert_received;
+	/** Last received 5V fixed source cap */
+	uint32_t last_5v_source_cap;
 };
 
 /**
@@ -53,10 +55,10 @@ struct tcpci_snk_emul_data {
  *
  * @return Pointer to USB-C sink extension
  */
-struct tcpci_partner_extension *tcpci_snk_emul_init(
-	struct tcpci_snk_emul_data *data,
-	struct tcpci_partner_data *common_data,
-	struct tcpci_partner_extension *ext);
+struct tcpci_partner_extension *
+tcpci_snk_emul_init(struct tcpci_snk_emul_data *data,
+		    struct tcpci_partner_data *common_data,
+		    struct tcpci_partner_extension *ext);
 
 /**
  * @brief Clear the ping received flag.
@@ -73,6 +75,13 @@ void tcpci_snk_emul_clear_ping_received(struct tcpci_snk_emul_data *sink_data);
 void tcpci_snk_emul_clear_alert_received(struct tcpci_snk_emul_data *sink_data);
 
 /**
+ * @brief Clear the last received 5V fixed source cap.
+ *
+ * @param sink_data
+ */
+void tcpci_snk_emul_clear_last_5v_cap(struct tcpci_snk_emul_data *sink_data);
+
+/**
  * @}
  */
 
diff --git a/zephyr/include/emul/tcpc/emul_tcpci_partner_src.h b/zephyr/include/emul/tcpc/emul_tcpci_partner_src.h
index 00f592ae2f..e72d0e4135 100644
--- a/zephyr/include/emul/tcpc/emul_tcpci_partner_src.h
+++ b/zephyr/include/emul/tcpc/emul_tcpci_partner_src.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -95,10 +95,10 @@ enum check_pdos_res tcpci_src_emul_check_pdos(struct tcpci_src_emul_data *data);
  *
  * @return Pointer to USB-C source extension
  */
-struct tcpci_partner_extension *tcpci_src_emul_init(
-	struct tcpci_src_emul_data *data,
-	struct tcpci_partner_data *common_data,
-	struct tcpci_partner_extension *ext);
+struct tcpci_partner_extension *
+tcpci_src_emul_init(struct tcpci_src_emul_data *data,
+		    struct tcpci_partner_data *common_data,
+		    struct tcpci_partner_extension *ext);
 
 /**
  * @brief Send capability message constructed from source device emulator PDOs
@@ -134,9 +134,7 @@ int tcpci_src_emul_send_capability_msg(struct tcpci_src_emul_data *data,
  */
 int tcpci_src_emul_send_capability_msg_with_timer(
 	struct tcpci_src_emul_data *data,
-	struct tcpci_partner_data *common_data,
-	uint64_t delay);
-
+	struct tcpci_partner_data *common_data, uint64_t delay);
 
 /**
  * @brief Clear the alert received flag.
diff --git a/zephyr/include/soc/ite_it8xxx2/reg_def_cros.h b/zephyr/include/soc/ite_it8xxx2/reg_def_cros.h
index f26d3ac69f..418ae39d3a 100644
--- a/zephyr/include/soc/ite_it8xxx2/reg_def_cros.h
+++ b/zephyr/include/soc/ite_it8xxx2/reg_def_cros.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/include/soc/microchip_xec/reg_def_cros.h b/zephyr/include/soc/microchip_xec/reg_def_cros.h
index 4cc66be47d..b4b849a90d 100644
--- a/zephyr/include/soc/microchip_xec/reg_def_cros.h
+++ b/zephyr/include/soc/microchip_xec/reg_def_cros.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,29 +13,29 @@
 
 /* RTC register structure */
 struct rtc_hw {
-__IOM uint8_t   SECV;     /*!< (@ 0x0000) RTC seconds value */
-__IOM uint8_t   SECA;     /*!< (@ 0x0001) RTC seconds alarm */
-__IOM uint8_t   MINV;     /*!< (@ 0x0002) RTC minutes value */
-__IOM uint8_t   MINA;     /*!< (@ 0x0003) RTC minutes alarm */
-__IOM uint8_t   HRSV;     /*!< (@ 0x0004) RTC hours value, AM/PM indicator */
-__IOM uint8_t   HRSA;     /*!< (@ 0x0005) RTC hours alarm */
-__IOM uint8_t   DOWV;     /*!< (@ 0x0006) RTC day of week value */
-__IOM uint8_t   DOMV;     /*!< (@ 0x0007) RTC day of month value */
-__IOM uint8_t   MONV;     /*!< (@ 0x0008) RTC month value */
-__IOM uint8_t   YEARV;    /*!< (@ 0x0009) RTC Year value */
-__IOM uint8_t   REGA;     /*!< (@ 0x000A) RTC register A */
-__IOM uint8_t   REGB;     /*!< (@ 0x000B) RTC register B */
-__IOM uint8_t   REGC;     /*!< (@ 0x000C) RTC register C */
-__IOM uint8_t   REGD;     /*!< (@ 0x000D) RTC register D */
-__IM  uint16_t  RESERVED;
-__IOM uint8_t   CTRL;     /*!< (@ 0x0010) RTC control */
-__IM  uint8_t   RESERVED1;
-__IM  uint16_t  RESERVED2;
-__IOM uint8_t   WKA;      /*!< (@ 0x0014) RTC week alarm */
-__IM  uint8_t   RESERVED3;
-__IM  uint16_t  RESERVED4;
-__IOM uint32_t  DLSF;     /*!< (@ 0x0018) RTC daylight savings forward */
-__IOM uint32_t  DLSB;     /*!< (@ 0x001C) RTC daylight savings backward */
+	__IOM uint8_t SECV; /*!< (@ 0x0000) RTC seconds value */
+	__IOM uint8_t SECA; /*!< (@ 0x0001) RTC seconds alarm */
+	__IOM uint8_t MINV; /*!< (@ 0x0002) RTC minutes value */
+	__IOM uint8_t MINA; /*!< (@ 0x0003) RTC minutes alarm */
+	__IOM uint8_t HRSV; /*!< (@ 0x0004) RTC hours value, AM/PM indicator */
+	__IOM uint8_t HRSA; /*!< (@ 0x0005) RTC hours alarm */
+	__IOM uint8_t DOWV; /*!< (@ 0x0006) RTC day of week value */
+	__IOM uint8_t DOMV; /*!< (@ 0x0007) RTC day of month value */
+	__IOM uint8_t MONV; /*!< (@ 0x0008) RTC month value */
+	__IOM uint8_t YEARV; /*!< (@ 0x0009) RTC Year value */
+	__IOM uint8_t REGA; /*!< (@ 0x000A) RTC register A */
+	__IOM uint8_t REGB; /*!< (@ 0x000B) RTC register B */
+	__IOM uint8_t REGC; /*!< (@ 0x000C) RTC register C */
+	__IOM uint8_t REGD; /*!< (@ 0x000D) RTC register D */
+	__IM uint16_t RESERVED;
+	__IOM uint8_t CTRL; /*!< (@ 0x0010) RTC control */
+	__IM uint8_t RESERVED1;
+	__IM uint16_t RESERVED2;
+	__IOM uint8_t WKA; /*!< (@ 0x0014) RTC week alarm */
+	__IM uint8_t RESERVED3;
+	__IM uint16_t RESERVED4;
+	__IOM uint32_t DLSF; /*!< (@ 0x0018) RTC daylight savings forward */
+	__IOM uint32_t DLSB; /*!< (@ 0x001C) RTC daylight savings backward */
 };
 
 #endif /* _MICROCHIP_XEC_REG_DEF_CROS_H */
diff --git a/zephyr/include/soc/nuvoton_npcx/reg_def_cros.h b/zephyr/include/soc/nuvoton_npcx/reg_def_cros.h
index c4d176851d..180c2e50a3 100644
--- a/zephyr/include/soc/nuvoton_npcx/reg_def_cros.h
+++ b/zephyr/include/soc/nuvoton_npcx/reg_def_cros.h
@@ -40,21 +40,21 @@ struct kbs_reg {
 };
 
 /* KBS register fields */
-#define NPCX_KBSBUFINDX                  0
-#define NPCX_KBSEVT_KBSDONE              0
-#define NPCX_KBSEVT_KBSERR               1
-#define NPCX_KBSCTL_START                0
-#define NPCX_KBSCTL_KBSMODE              1
-#define NPCX_KBSCTL_KBSIEN               2
-#define NPCX_KBSCTL_KBSINC               3
-#define NPCX_KBSCTL_KBHDRV_FIELD         FIELD(6, 2)
-#define NPCX_KBSCFGINDX                  0
+#define NPCX_KBSBUFINDX 0
+#define NPCX_KBSEVT_KBSDONE 0
+#define NPCX_KBSEVT_KBSERR 1
+#define NPCX_KBSCTL_START 0
+#define NPCX_KBSCTL_KBSMODE 1
+#define NPCX_KBSCTL_KBSIEN 2
+#define NPCX_KBSCTL_KBSINC 3
+#define NPCX_KBSCTL_KBHDRV_FIELD FIELD(6, 2)
+#define NPCX_KBSCFGINDX 0
 /* Index of 'Automatic Scan' configuration register */
-#define KBS_CFG_INDX_DLY1                0 /* Keyboard Scan Delay T1 Byte */
-#define KBS_CFG_INDX_DLY2                1 /* Keyboard Scan Delay T2 Byte */
-#define KBS_CFG_INDX_RTYTO               2 /* Keyboard Scan Retry Timeout */
-#define KBS_CFG_INDX_CNUM                3 /* Keyboard Scan Columns Number */
-#define KBS_CFG_INDX_CDIV                4 /* Keyboard Scan Clock Divisor */
+#define KBS_CFG_INDX_DLY1 0 /* Keyboard Scan Delay T1 Byte */
+#define KBS_CFG_INDX_DLY2 1 /* Keyboard Scan Delay T2 Byte */
+#define KBS_CFG_INDX_RTYTO 2 /* Keyboard Scan Retry Timeout */
+#define KBS_CFG_INDX_CNUM 3 /* Keyboard Scan Columns Number */
+#define KBS_CFG_INDX_CDIV 4 /* Keyboard Scan Clock Divisor */
 
 /*
  * Monotonic Counter (MTC) device registers
@@ -67,8 +67,8 @@ struct mtc_reg {
 };
 
 /* MTC register fields */
-#define NPCX_WTC_PTO                     30
-#define NPCX_WTC_WIE                     31
+#define NPCX_WTC_PTO 30
+#define NPCX_WTC_WIE 31
 
 /* SHI (Serial Host Interface) registers */
 struct shi_reg {
@@ -109,48 +109,48 @@ struct shi_reg {
 };
 
 /* SHI register fields */
-#define NPCX_SHICFG1_EN                  0
-#define NPCX_SHICFG1_MODE                1
-#define NPCX_SHICFG1_WEN                 2
-#define NPCX_SHICFG1_AUTIBF              3
-#define NPCX_SHICFG1_AUTOBE              4
-#define NPCX_SHICFG1_DAS                 5
-#define NPCX_SHICFG1_CPOL                6
-#define NPCX_SHICFG1_IWRAP               7
-#define NPCX_SHICFG2_SIMUL               0
-#define NPCX_SHICFG2_BUSY                1
-#define NPCX_SHICFG2_ONESHOT             2
-#define NPCX_SHICFG2_SLWU                3
-#define NPCX_SHICFG2_REEN                4
-#define NPCX_SHICFG2_RESTART             5
-#define NPCX_SHICFG2_REEVEN              6
-#define NPCX_EVENABLE_OBEEN              0
-#define NPCX_EVENABLE_OBHEEN             1
-#define NPCX_EVENABLE_IBFEN              2
-#define NPCX_EVENABLE_IBHFEN             3
-#define NPCX_EVENABLE_EOREN              4
-#define NPCX_EVENABLE_EOWEN              5
-#define NPCX_EVENABLE_STSREN             6
-#define NPCX_EVENABLE_IBOREN             7
-#define NPCX_EVSTAT_OBE                  0
-#define NPCX_EVSTAT_OBHE                 1
-#define NPCX_EVSTAT_IBF                  2
-#define NPCX_EVSTAT_IBHF                 3
-#define NPCX_EVSTAT_EOR                  4
-#define NPCX_EVSTAT_EOW                  5
-#define NPCX_EVSTAT_STSR                 6
-#define NPCX_EVSTAT_IBOR                 7
-#define NPCX_STATUS_OBES                 6
-#define NPCX_STATUS_IBFS                 7
-#define NPCX_SHICFG3_OBUFLVLDIS          7
-#define NPCX_SHICFG4_IBUFLVLDIS          7
-#define NPCX_SHICFG5_IBUFLVL2            FIELD(0, 6)
-#define NPCX_SHICFG5_IBUFLVL2DIS         7
-#define NPCX_EVSTAT2_IBHF2               0
-#define NPCX_EVSTAT2_CSNRE               1
-#define NPCX_EVSTAT2_CSNFE               2
-#define NPCX_EVENABLE2_IBHF2EN           0
-#define NPCX_EVENABLE2_CSNREEN           1
-#define NPCX_EVENABLE2_CSNFEEN           2
+#define NPCX_SHICFG1_EN 0
+#define NPCX_SHICFG1_MODE 1
+#define NPCX_SHICFG1_WEN 2
+#define NPCX_SHICFG1_AUTIBF 3
+#define NPCX_SHICFG1_AUTOBE 4
+#define NPCX_SHICFG1_DAS 5
+#define NPCX_SHICFG1_CPOL 6
+#define NPCX_SHICFG1_IWRAP 7
+#define NPCX_SHICFG2_SIMUL 0
+#define NPCX_SHICFG2_BUSY 1
+#define NPCX_SHICFG2_ONESHOT 2
+#define NPCX_SHICFG2_SLWU 3
+#define NPCX_SHICFG2_REEN 4
+#define NPCX_SHICFG2_RESTART 5
+#define NPCX_SHICFG2_REEVEN 6
+#define NPCX_EVENABLE_OBEEN 0
+#define NPCX_EVENABLE_OBHEEN 1
+#define NPCX_EVENABLE_IBFEN 2
+#define NPCX_EVENABLE_IBHFEN 3
+#define NPCX_EVENABLE_EOREN 4
+#define NPCX_EVENABLE_EOWEN 5
+#define NPCX_EVENABLE_STSREN 6
+#define NPCX_EVENABLE_IBOREN 7
+#define NPCX_EVSTAT_OBE 0
+#define NPCX_EVSTAT_OBHE 1
+#define NPCX_EVSTAT_IBF 2
+#define NPCX_EVSTAT_IBHF 3
+#define NPCX_EVSTAT_EOR 4
+#define NPCX_EVSTAT_EOW 5
+#define NPCX_EVSTAT_STSR 6
+#define NPCX_EVSTAT_IBOR 7
+#define NPCX_STATUS_OBES 6
+#define NPCX_STATUS_IBFS 7
+#define NPCX_SHICFG3_OBUFLVLDIS 7
+#define NPCX_SHICFG4_IBUFLVLDIS 7
+#define NPCX_SHICFG5_IBUFLVL2 FIELD(0, 6)
+#define NPCX_SHICFG5_IBUFLVL2DIS 7
+#define NPCX_EVSTAT2_IBHF2 0
+#define NPCX_EVSTAT2_CSNRE 1
+#define NPCX_EVSTAT2_CSNFE 2
+#define NPCX_EVENABLE2_IBHF2EN 0
+#define NPCX_EVENABLE2_CSNREEN 1
+#define NPCX_EVENABLE2_CSNFEEN 2
 
 #endif /* _NUVOTON_NPCX_REG_DEF_CROS_H */
diff --git a/zephyr/linker/CMakeLists.txt b/zephyr/linker/CMakeLists.txt
index 982e2b0218..94544d454b 100644
--- a/zephyr/linker/CMakeLists.txt
+++ b/zephyr/linker/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/linker/fixed-sections.ld b/zephyr/linker/fixed-sections.ld
index 5046823713..d4dcadcf0d 100644
--- a/zephyr/linker/fixed-sections.ld
+++ b/zephyr/linker/fixed-sections.ld
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/linker/image_size.ld b/zephyr/linker/image_size.ld
index b1e401ae7f..4a0c854f05 100644
--- a/zephyr/linker/image_size.ld
+++ b/zephyr/linker/image_size.ld
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/linker/iram_text.ld b/zephyr/linker/iram_text.ld
index 3ea3f4db7e..f01c3509da 100644
--- a/zephyr/linker/iram_text.ld
+++ b/zephyr/linker/iram_text.ld
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,7 +7,7 @@
 
 /* This code taken from core/cortex-m/ec.lds.S */
 
-#if defined(CONFIG_PLATFORM_EC_MPU)
+#if defined(CONFIG_MPU)
 /* MPU regions must be aligned to a 32-byte boundary */
 #define _IRAM_ALIGN	32
 #else
diff --git a/zephyr/linker/mchp-xec-lfw.ld b/zephyr/linker/mchp-xec-lfw.ld
index 4c28f16bdf..6774c956a5 100644
--- a/zephyr/linker/mchp-xec-lfw.ld
+++ b/zephyr/linker/mchp-xec-lfw.ld
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/linker/npcx-lfw.ld b/zephyr/linker/npcx-lfw.ld
index a6de1df65a..e69c4c2aa5 100644
--- a/zephyr/linker/npcx-lfw.ld
+++ b/zephyr/linker/npcx-lfw.ld
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/mock/CMakeLists.txt b/zephyr/mock/CMakeLists.txt
new file mode 100644
index 0000000000..69add3ae3e
--- /dev/null
+++ b/zephyr/mock/CMakeLists.txt
@@ -0,0 +1,7 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+zephyr_library_sources_ifdef(CONFIG_POWER_SEQUENCE_MOCK power.c)
+
+cros_ec_library_include_directories(include)
diff --git a/zephyr/mock/Kconfig b/zephyr/mock/Kconfig
new file mode 100644
index 0000000000..3d6e3f98dd
--- /dev/null
+++ b/zephyr/mock/Kconfig
@@ -0,0 +1,11 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config POWER_SEQUENCE_MOCK
+	bool "Use a mocked power sequence driver."
+	help
+	  A simplified power sequence driver that invokes startup/shutdown
+	  and suspend/resume hooks in appropriate state transitions. Any
+	  request that comes in mid sequence is pended and ran after final
+	  state is reached.
diff --git a/zephyr/mock/include/mock/power.h b/zephyr/mock/include/mock/power.h
new file mode 100644
index 0000000000..9f04053241
--- /dev/null
+++ b/zephyr/mock/include/mock/power.h
@@ -0,0 +1,26 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef ZEPHYR_TEST_MOCK_POWER_H
+#define ZEPHYR_TEST_MOCK_POWER_H
+
+#include <zephyr/fff.h>
+#include "power.h"
+
+/* Mocks for ec/power/common.c and board specific implementations */
+DECLARE_FAKE_VALUE_FUNC(enum power_state, power_handle_state, enum power_state);
+DECLARE_FAKE_VOID_FUNC(chipset_force_shutdown, enum chipset_shutdown_reason);
+DECLARE_FAKE_VOID_FUNC(chipset_power_on);
+DECLARE_FAKE_VALUE_FUNC(int, command_power, int, const char **);
+
+enum power_state power_handle_state_custom_fake(enum power_state state);
+
+void chipset_force_shutdown_custom_fake(enum chipset_shutdown_reason reason);
+
+void chipset_power_on_custom_fake(void);
+
+int command_power_custom_fake(int argc, const char **argv);
+
+#endif /* ZEPHYR_TEST_MOCK_POWER_H */
diff --git a/zephyr/mock/power.c b/zephyr/mock/power.c
new file mode 100644
index 0000000000..fc82cc7250
--- /dev/null
+++ b/zephyr/mock/power.c
@@ -0,0 +1,264 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/logging/log.h>
+#include <zephyr/ztest.h>
+
+#include "hooks.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "task.h"
+#include "util.h"
+
+#include "mock/power.h"
+
+LOG_MODULE_REGISTER(mock_power);
+
+/* Mocks for ec/power/common.c and board specific implementations */
+DEFINE_FAKE_VALUE_FUNC(enum power_state, power_handle_state, enum power_state);
+DEFINE_FAKE_VOID_FUNC(chipset_force_shutdown, enum chipset_shutdown_reason);
+DEFINE_FAKE_VOID_FUNC(chipset_power_on);
+DEFINE_FAKE_VALUE_FUNC(int, command_power, int, const char **);
+
+#define MOCK_POWER_LIST(FAKE)                 \
+	{                                     \
+		FAKE(power_handle_state);     \
+		FAKE(chipset_force_shutdown); \
+		FAKE(chipset_power_on);       \
+		FAKE(command_power);          \
+	}
+
+/**
+ * @brief Reset all the fakes before each test.
+ */
+static void mock_power_rule_before(const struct ztest_unit_test *test,
+				   void *data)
+{
+	ARG_UNUSED(test);
+	ARG_UNUSED(data);
+
+	MOCK_POWER_LIST(RESET_FAKE);
+
+	FFF_RESET_HISTORY();
+
+	power_handle_state_fake.custom_fake = power_handle_state_custom_fake;
+	chipset_force_shutdown_fake.custom_fake =
+		chipset_force_shutdown_custom_fake;
+	chipset_power_on_fake.custom_fake = chipset_power_on_custom_fake;
+	command_power_fake.custom_fake = command_power_custom_fake;
+}
+
+ZTEST_RULE(mock_power_rule, mock_power_rule_before, NULL);
+
+enum power_request_t {
+	POWER_REQ_NONE,
+	POWER_REQ_OFF,
+	POWER_REQ_ON,
+	POWER_REQ_COUNT,
+};
+
+static const char *power_req_name[POWER_REQ_COUNT] = {
+	"none",
+	"OFF",
+	"ON",
+};
+
+static enum power_request_t current_power_request = POWER_REQ_NONE;
+static enum power_request_t pending_power_request = POWER_REQ_NONE;
+
+void handle_power_request(enum power_request_t req)
+{
+	if (current_power_request == POWER_REQ_NONE) {
+		current_power_request = req;
+	} else if (current_power_request != req) {
+		LOG_INF("MOCK: Handling %s, pend %s request",
+			power_req_name[current_power_request],
+			power_req_name[req]);
+		pending_power_request = req;
+	}
+}
+
+void power_request_complete(void)
+{
+	current_power_request = pending_power_request;
+	pending_power_request = POWER_REQ_NONE;
+}
+
+void chipset_force_shutdown_custom_fake(enum chipset_shutdown_reason reason)
+{
+	LOG_INF("MOCK %s(%d)", __func__, reason);
+	handle_power_request(POWER_REQ_OFF);
+	task_wake(TASK_ID_CHIPSET);
+}
+
+void chipset_power_on_custom_fake(void)
+{
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
+		handle_power_request(POWER_REQ_ON);
+		task_wake(TASK_ID_CHIPSET);
+	}
+}
+
+/* Power states that we can report */
+enum power_state_t {
+	PSTATE_UNKNOWN,
+	PSTATE_OFF,
+	PSTATE_ON,
+	PSTATE_COUNT,
+};
+
+static const char *const state_name[] = {
+	"unknown",
+	"OFF",
+	"ON",
+};
+
+int command_power_custom_fake(int argc, const char **argv)
+{
+	int v, req;
+
+	if (argc < 2) {
+		enum power_state_t state;
+
+		state = PSTATE_UNKNOWN;
+		if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+			state = PSTATE_OFF;
+		if (chipset_in_state(CHIPSET_STATE_ON))
+			state = PSTATE_ON;
+		ccprintf("%s\n", state_name[state]);
+
+		return EC_SUCCESS;
+	}
+
+	if (!parse_bool(argv[1], &v)) {
+		return EC_ERROR_PARAM1;
+	}
+	req = v ? POWER_REQ_ON : POWER_REQ_OFF;
+	handle_power_request(req);
+	LOG_INF("MOCK: Requesting power %s\n", power_req_name[req]);
+	task_wake(TASK_ID_CHIPSET);
+
+	return EC_SUCCESS;
+}
+
+static void mock_lid_event(void)
+{
+	/* Power task only cares about lid-open events */
+	if (!lid_is_open()) {
+		return;
+	}
+
+	LOG_INF("MOCK: lid opened %s\n", power_req_name[POWER_REQ_ON]);
+	handle_power_request(POWER_REQ_ON);
+	task_wake(TASK_ID_CHIPSET);
+}
+DECLARE_HOOK(HOOK_LID_CHANGE, mock_lid_event, HOOK_PRIO_DEFAULT);
+
+enum power_state power_handle_state_custom_fake(enum power_state state)
+{
+	enum power_state new_state = state;
+	enum power_request_t request = current_power_request;
+
+	switch (state) {
+	/* Steady states */
+	case POWER_G3:
+		if (current_power_request == POWER_REQ_ON) {
+			new_state = POWER_G3S5;
+		} else if (current_power_request == POWER_REQ_OFF) {
+			new_state = state;
+			power_request_complete();
+		}
+		break;
+	case POWER_S5: /* System is soft-off */
+		if (current_power_request == POWER_REQ_ON) {
+			new_state = POWER_S5S3;
+		} else if (current_power_request == POWER_REQ_OFF) {
+			/* S5 timeout should transition to G3 */
+		}
+		break;
+	case POWER_S3: /* Suspend; RAM on, processor is asleep */
+		if (current_power_request == POWER_REQ_ON) {
+			new_state = POWER_S3S0;
+		} else if (current_power_request == POWER_REQ_OFF) {
+			new_state = POWER_S3S5;
+		}
+		break;
+	case POWER_S0: /* System is on */
+		if (current_power_request == POWER_REQ_ON) {
+			new_state = state;
+			power_request_complete();
+
+			sleep_notify_transition(SLEEP_NOTIFY_RESUME,
+						HOOK_CHIPSET_RESUME);
+		} else if (current_power_request == POWER_REQ_OFF) {
+			new_state = POWER_S0S3;
+		}
+		break;
+	case POWER_S4: /* System is suspended to disk */
+#ifdef CONFIG_POWER_S0IX
+	case POWER_S0ix:
+#endif
+		new_state = state;
+		break;
+	/* Transitions */
+	case POWER_S3S0: /* S3 -> S0 */
+#ifdef CONFIG_CHIPSET_RESUME_INIT_HOOK
+		hook_notify(HOOK_CHIPSET_RESUME_INIT);
+#endif
+		hook_notify(HOOK_CHIPSET_RESUME);
+		sleep_resume_transition();
+		power_request_complete();
+		disable_sleep(SLEEP_MASK_AP_RUN);
+		new_state = POWER_S0;
+		break;
+	case POWER_S0S3: /* S0 -> S3 */
+		sleep_notify_transition(SLEEP_NOTIFY_SUSPEND,
+					HOOK_CHIPSET_SUSPEND);
+		hook_notify(HOOK_CHIPSET_SUSPEND);
+#ifdef CONFIG_CHIPSET_RESUME_INIT_HOOK
+		hook_notify(HOOK_CHIPSET_SUSPEND_COMPLETE);
+#endif
+		sleep_suspend_transition();
+		enable_sleep(SLEEP_MASK_AP_RUN);
+		new_state = POWER_S3;
+		break;
+	case POWER_S5S3: /* S5 -> S3 (skips S4 on non-Intel systems) */
+		hook_notify(HOOK_CHIPSET_PRE_INIT);
+		hook_notify(HOOK_CHIPSET_STARTUP);
+		sleep_reset_tracking();
+		new_state = POWER_S3;
+		break;
+	case POWER_S3S5: /* S3 -> S5 (skips S4 on non-Intel systems) */
+		hook_notify(HOOK_CHIPSET_SHUTDOWN);
+		hook_notify(HOOK_CHIPSET_SHUTDOWN_COMPLETE);
+		new_state = POWER_S5;
+		break;
+	case POWER_G3S5: /* G3 -> S5 (at system init time) */
+		new_state = POWER_S5;
+		break;
+	case POWER_S5G3: /* S5 -> G3 */
+		new_state = POWER_G3;
+		break;
+#ifdef CONFIG_POWER_S0IX
+	case POWER_S0ixS0: /* S0ix -> S0 */
+		new_state = POWER_S0;
+		break;
+	case POWER_S0S0ix: /* S0 -> S0ix */
+		new_state = POWER_S0ix;
+		break;
+#endif
+	case POWER_S5S4: /* S5 -> S4 */
+	case POWER_S4S3: /* S4 -> S3 */
+	case POWER_S3S4: /* S3 -> S4 */
+	case POWER_S4S5: /* S4 -> S5 */
+	default:
+		break;
+	}
+
+	LOG_INF("MOCK: power request=%u, state=%u -> new_state=%u\n", request,
+		state, new_state);
+
+	return new_state;
+}
diff --git a/zephyr/module.yml b/zephyr/module.yml
index 66bfcd8d9f..7988a425e5 100644
--- a/zephyr/module.yml
+++ b/zephyr/module.yml
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/projects/.pylintrc b/zephyr/projects/.pylintrc
index 9ca0b5f8c9..f4609e3781 100644
--- a/zephyr/projects/.pylintrc
+++ b/zephyr/projects/.pylintrc
@@ -1,15 +1,3 @@
-[MASTER]
-init-hook='import sys; sys.path.append("/usr/lib64/python3.6/site-packages")'
-
-[MESSAGES CONTROL]
-
-disable=bad-continuation,bad-whitespace,format,fixme
-
-[format]
-
-max-line-length=88
-string-quote=double
-
 [BASIC]
 additional-builtins=
     here,
@@ -19,3 +7,21 @@ additional-builtins=
     register_npcx_project,
     register_raw_project,
 good-names=BUILD
+
+# cros lint doesn't inherit the pylintrc from the parent dir.
+# These settings are copied from platform/ec/pylintrc
+[MESSAGES CONTROL]
+
+disable=
+    bad-continuation,
+    bad-whitespace,
+    # These have nothing to do with black, they are just annoying
+    fixme,
+    too-many-arguments,
+    too-many-statements,
+    too-many-branches,
+    too-many-locals
+
+[format]
+
+string-quote=double
diff --git a/zephyr/projects/brya/BUILD.py b/zephyr/projects/brya/BUILD.py
index d044a11ae7..9991335ca7 100644
--- a/zephyr/projects/brya/BUILD.py
+++ b/zephyr/projects/brya/BUILD.py
@@ -1,11 +1,13 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 """Define zmake projects for brya."""
 
 
-def register_npcx9_variant(project_name, extra_dts_overlays=(), extra_kconfig_files=()):
+def register_npcx9_variant(
+    project_name, extra_dts_overlays=(), extra_kconfig_files=()
+):
     """Register a variant of a brya, even though this is not named as such."""
     return register_npcx_project(
         project_name=project_name,
@@ -13,7 +15,6 @@ def register_npcx9_variant(project_name, extra_dts_overlays=(), extra_kconfig_fi
         dts_overlays=[
             "adc.dts",
             "battery.dts",
-            "cbi_eeprom.dts",
             "fan.dts",
             "gpio.dts",
             "i2c.dts",
@@ -40,8 +41,3 @@ brya = register_npcx9_variant(
     extra_dts_overlays=[here / "brya.dts"],
     extra_kconfig_files=[here / "prj_brya.conf"],
 )
-
-ghost = brya.variant(
-    project_name="ghost",
-    kconfig_files=[here / "prj_ghost.conf"],
-)
diff --git a/zephyr/projects/brya/CMakeLists.txt b/zephyr/projects/brya/CMakeLists.txt
index 0cb61eb838..11c1a8386f 100644
--- a/zephyr/projects/brya/CMakeLists.txt
+++ b/zephyr/projects/brya/CMakeLists.txt
@@ -1,10 +1,10 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 cmake_minimum_required(VERSION 3.13.1)
 
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
 project(brya)
 
 set(PLATFORM_EC_BOARD "${PLATFORM_EC}/board/brya" CACHE PATH
diff --git a/zephyr/projects/brya/Kconfig b/zephyr/projects/brya/Kconfig
index 111476eb42..4dd8e23443 100644
--- a/zephyr/projects/brya/Kconfig
+++ b/zephyr/projects/brya/Kconfig
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/projects/brya/adc.dts b/zephyr/projects/brya/adc.dts
index e1502b2389..f3f0d1e064 100644
--- a/zephyr/projects/brya/adc.dts
+++ b/zephyr/projects/brya/adc.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,22 +8,18 @@
 		compatible = "named-adc-channels";
 
 		adc_ddr_soc: ddr_soc {
-			label = "TEMP_DDR_SOC";
 			enum-name = "ADC_TEMP_SENSOR_1_DDR_SOC";
 			io-channels = <&adc0 0>;
 		};
 		adc_ambient: ambient {
-			label = "TEMP_AMBIENT";
 			enum-name = "ADC_TEMP_SENSOR_2_AMBIENT";
 			io-channels = <&adc0 1>;
 		};
 		adc_charger: charger {
-			label = "TEMP_CHARGER";
 			enum-name = "ADC_TEMP_SENSOR_3_CHARGER";
 			io-channels = <&adc0 6>;
 		};
 		adc_wwan: wwan {
-			label = "TEMP_WWAN";
 			enum-name = "ADC_TEMP_SENSOR_4_WWAN";
 			io-channels = <&adc0 7>;
 		};
diff --git a/zephyr/projects/brya/battery.dts b/zephyr/projects/brya/battery.dts
index 1de6b3aa4a..4844d88d92 100644
--- a/zephyr/projects/brya/battery.dts
+++ b/zephyr/projects/brya/battery.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/brya/battery_present.c b/zephyr/projects/brya/battery_present.c
index 5dc587293c..c487a01f36 100644
--- a/zephyr/projects/brya/battery_present.c
+++ b/zephyr/projects/brya/battery_present.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/brya/brya.dts b/zephyr/projects/brya/brya.dts
index 4182da6c32..4b0490afa9 100644
--- a/zephyr/projects/brya/brya.dts
+++ b/zephyr/projects/brya/brya.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/brya/cbi_eeprom.dts b/zephyr/projects/brya/cbi_eeprom.dts
deleted file mode 100644
index 95a6806f31..0000000000
--- a/zephyr/projects/brya/cbi_eeprom.dts
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-&i2c7_0 {
-	cbi_eeprom: eeprom@50 {
-		compatible = "atmel,at24";
-		reg = <0x50>;
-		label = "EEPROM_CBI";
-		size = <2048>;
-		pagesize = <16>;
-		address-width = <8>;
-		timeout = <5>;
-	};
-};
diff --git a/zephyr/projects/brya/fan.dts b/zephyr/projects/brya/fan.dts
index e67845757f..aa6dcfde7d 100644
--- a/zephyr/projects/brya/fan.dts
+++ b/zephyr/projects/brya/fan.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,7 +9,6 @@
 
 		fan_0 {
 			pwms = <&pwm5 0 PWM_KHZ(1) PWM_POLARITY_NORMAL>;
-			pwm-frequency = <1000>;
 			rpm_min = <2200>;
 			rpm_start = <2200>;
 			rpm_max = <4200>;
diff --git a/zephyr/projects/brya/gpio.dts b/zephyr/projects/brya/gpio.dts
index 2b853f4d3b..6c6a2ac054 100644
--- a/zephyr/projects/brya/gpio.dts
+++ b/zephyr/projects/brya/gpio.dts
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -132,10 +132,12 @@
 		gpio_pg_ec_dsw_pwrok: pg_ec_dsw_pwrok {
 			gpios = <&gpioc 7 GPIO_INPUT>;
 			enum-name = "GPIO_PG_EC_DSW_PWROK";
+			alias = "GPIO_SEQ_EC_DSW_PWROK";
 		};
 		en_s5_rails {
 			gpios = <&gpiob 6 GPIO_OUTPUT_LOW>;
 			enum-name = "GPIO_EN_S5_RAILS";
+			alias = "GPIO_TEMP_SENSOR_POWER";
 		};
 		sys_rst_odl {
 			gpios = <&gpioc 5 GPIO_ODR_HIGH>;
@@ -272,116 +274,68 @@
 		};
 		usb_c0_oc_odl {
 			gpios = <&ioex_port1 4 GPIO_ODR_HIGH>;
-			enum-name = "IOEX_USB_C0_OC_ODL";
 			no-auto-init;
 		};
-		usb_c0_frs_en {
+		usb_c0_frs_en: usb_c0_frs_en {
 			gpios = <&ioex_port1 6 GPIO_OUTPUT_LOW>;
 			enum-name = "IOEX_USB_C0_FRS_EN";
 			no-auto-init;
 		};
 		usb_c0_rt_rst_odl: usb_c0_rt_rst_odl {
 			gpios = <&ioex_port1 7 GPIO_ODR_LOW>;
-			enum-name = "IOEX_USB_C0_RT_RST_ODL";
 			no-auto-init;
 		};
 		usb_c2_rt_rst_odl: usb_c2_rt_rst_odl {
 			gpios = <&ioex_port2 2 GPIO_ODR_LOW>;
-			enum-name = "IOEX_USB_C2_RT_RST_ODL";
 			no-auto-init;
 		};
 		usb_c1_oc_odl {
 			gpios = <&ioex_port2 3 GPIO_ODR_HIGH>;
-			enum-name = "IOEX_USB_C1_OC_ODL";
 			no-auto-init;
 		};
 		usb_c2_oc_odl {
 			gpios = <&ioex_port2 4 GPIO_ODR_HIGH>;
-			enum-name = "IOEX_USB_C2_OC_ODL";
 			no-auto-init;
 		};
-		usb_c2_frs_en {
+		usb_c2_frs_en: usb_c2_frs_en {
 			gpios = <&ioex_port2 6 GPIO_OUTPUT_LOW>;
 			enum-name = "IOEX_USB_C2_FRS_EN";
 			no-auto-init;
 		};
+		/* unimplemented GPIOs */
+		entering-rw {
+			enum-name = "GPIO_ENTERING_RW";
+		};
 	};
 
 	usba-port-enable-list {
 		compatible = "cros-ec,usba-port-enable-pins";
 		enable-pins = <&gpio_en_pp5000_usba_r>;
 	};
-
-	vsby-psl-in-list {
-		/* Use PSL_IN1/2/3 as detection pins from hibernate mode */
-		psl-in-pads = <&psl_in1 &psl_in2 &psl_in3>;
-		status = "okay";
-	};
-};
-
-&i2c1_0 {
-	status = "okay";
-	pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>;
-	pinctrl-names = "default";
-
-	nct3808_0_P1: nct3808_0_P1@70 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "nuvoton,nct38xx-gpio";
-		reg = <0x70>;
-		label = "NCT3808_0_P1";
-
-		ioex_port1: gpio@0 {
-			compatible = "nuvoton,nct38xx-gpio-port";
-			reg = <0x0>;
-			label = "NCT3808_0_P1_GPIO0";
-			gpio-controller;
-			#gpio-cells = <2>;
-			ngpios = <8>;
-			pin_mask = <0xdc>;
-			pinmux_mask = <0xff>;
-		};
-	};
-
-	nct3808_0_P2: nct3808_0_P2@74 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "nuvoton,nct38xx-gpio";
-		reg = <0x74>;
-		label = "NCT3808_0_P2";
-
-		ioex_port2: gpio@0 {
-			compatible = "nuvoton,nct38xx-gpio-port";
-			reg = <0x0>;
-			label = "NCT3808_0_P2_GPIO0";
-			gpio-controller;
-			#gpio-cells = <2>;
-			ngpios = <8>;
-			pin_mask = <0xdc>;
-			pinmux_mask = <0xff>;
-		};
-	};
-
-	nct3808_alert_1 {
-		compatible = "nuvoton,nct38xx-gpio-alert";
-		irq-gpios = <&gpioe 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
-		nct38xx-dev = <&nct3808_0_P1 &nct3808_0_P2>;
-		label = "NCT3808_ALERT_1";
-	};
 };
 
 /* Power switch logic input pads */
 /* LID_OPEN_OD */
-&psl_in1 {
-	flag = <NPCX_PSL_RISING_EDGE>;
+&psl_in1_gpd2 {
+	psl-in-mode = "edge";
+	psl-in-pol = "high-rising";
 };
 
 /* ACOK_EC_OD */
-&psl_in2 {
-	flag = <NPCX_PSL_RISING_EDGE>;
+&psl_in2_gp00 {
+	psl-in-mode = "edge";
+	psl-in-pol = "high-rising";
 };
 
 /* GSC_EC_PWR_BTN_ODL */
-&psl_in3 {
-	flag = <NPCX_PSL_FALLING_EDGE>;
+&psl_in3_gp01 {
+	psl-in-mode = "edge";
+	psl-in-pol = "high-rising";
+};
+
+/* Power domain device controlled by PSL (Power Switch Logic) IO pads */
+&power_ctrl_psl {
+	status = "okay";
+	pinctrl-names = "sleep";
+	pinctrl-0 = <&psl_in1_gpd2 &psl_in2_gp00 &psl_in3_gp01>;
 };
diff --git a/zephyr/projects/brya/i2c.dts b/zephyr/projects/brya/i2c.dts
index 6567e27bf0..7284d80870 100644
--- a/zephyr/projects/brya/i2c.dts
+++ b/zephyr/projects/brya/i2c.dts
@@ -1,60 +1,50 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+ #include <dt-bindings/usb_pd_tcpm.h>
+
 / {
 	named-i2c-ports {
 		compatible = "named-i2c-ports";
 		i2c_sensor: sensor {
 			i2c-port = <&i2c0_0>;
-			enum-name = "I2C_PORT_SENSOR";
+			enum-names = "I2C_PORT_SENSOR";
 		};
 		tcpc0_2: tcpc0_2 {
 			i2c-port = <&i2c1_0>;
-			enum-name = "I2C_PORT_USB_C0_C2_TCPC";
+			enum-names = "I2C_PORT_USB_C0_C2_TCPC";
 		};
 		tcpc1: tcpc1 {
 			i2c-port = <&i2c4_1>;
-			enum-name = "I2C_PORT_USB_C1_TCPC";
+			enum-names = "I2C_PORT_USB_C1_TCPC";
 			dynamic-speed;
 		};
-		ppc0_2: ppc0_2 {
+		c0_c2_bc12: c0_c2_bc12 {
 			i2c-port = <&i2c2_0>;
-			enum-name = "I2C_PORT_USB_C0_C2_PPC";
+			enum-names = "I2C_PORT_USB_C0_C2_PPC",
+				"I2C_PORT_USB_C0_C2_BC12";
 		};
-		ppc1: ppc1 {
+		c1_bc12: c1_bc12 {
 			i2c-port = <&i2c6_1>;
-			enum-name = "I2C_PORT_USB_C1_PPC";
+			enum-names = "I2C_PORT_USB_C1_PPC",
+				"I2C_PORT_USB_C1_BC12";
 			dynamic-speed;
 		};
 		retimer0_2: retimer0_2 {
 			i2c-port = <&i2c3_0>;
-			enum-name = "I2C_PORT_USB_C0_C2_MUX";
+			enum-names = "I2C_PORT_USB_C0_C2_MUX";
 		};
 		battery {
 			i2c-port = <&i2c5_0>;
-			enum-name = "I2C_PORT_BATTERY";
-		};
-		eeprom {
-			i2c-port = <&i2c7_0>;
-			enum-name = "I2C_PORT_EEPROM";
+			enum-names = "I2C_PORT_BATTERY";
 		};
 		i2c_charger: charger {
 			i2c-port = <&i2c7_0>;
-			enum-name = "I2C_PORT_CHARGER";
-		};
-		c1_bc12: c1_bc12 {
-			i2c-port = <&i2c6_1>;
-			enum-name = "I2C_PORT_USB_C1_BC12";
-		};
-		c0_c2_bc12: c0_c2_bc12 {
-			i2c-port = <&i2c2_0>;
-			enum-name = "I2C_PORT_USB_C0_C2_BC12";
-		};
-		mp2964 {
-			i2c-port = <&i2c7_0>;
-			enum-name = "I2C_PORT_MP2964";
+			enum-names =  "I2C_PORT_CHARGER",
+				"I2C_PORT_EEPROM",
+				"I2C_PORT_MP2964";
 		};
 	};
 };
@@ -75,6 +65,67 @@
 	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
 	pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>;
 	pinctrl-names = "default";
+
+	tcpc_port0: nct38xx@70 {
+		compatible = "nuvoton,nct38xx";
+		reg = <0x70>;
+		gpio-dev = <&nct3808_0_P1>;
+		tcpc-flags = <(
+			TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_NO_DEBUG_ACC_CONTROL)>;
+	};
+
+	nct3808_0_P1: nct3808_0_P1@70 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nuvoton,nct38xx-gpio";
+		reg = <0x70>;
+		label = "NCT3808_0_P1";
+
+		ioex_port1: gpio@0 {
+			compatible = "nuvoton,nct38xx-gpio-port";
+			reg = <0x0>;
+			label = "NCT3808_0_P1_GPIO0";
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <8>;
+			pin_mask = <0xdc>;
+			pinmux_mask = <0xff>;
+		};
+	};
+
+	tcpc_port2: nct38xx@74 {
+		compatible = "nuvoton,nct38xx";
+		reg = <0x74>;
+		gpio-dev = <&nct3808_0_P2>;
+		tcpc-flags = <(TCPC_FLAGS_TCPCI_REV2_0)>;
+	};
+
+	nct3808_0_P2: nct3808_0_P2@74 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nuvoton,nct38xx-gpio";
+		reg = <0x74>;
+		label = "NCT3808_0_P2";
+
+		ioex_port2: gpio@0 {
+			compatible = "nuvoton,nct38xx-gpio-port";
+			reg = <0x0>;
+			label = "NCT3808_0_P2_GPIO0";
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <8>;
+			pin_mask = <0xdc>;
+			pinmux_mask = <0xff>;
+		};
+	};
+
+	nct3808_alert_1 {
+		compatible = "nuvoton,nct38xx-gpio-alert";
+		irq-gpios = <&gpioe 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+		nct38xx-dev = <&nct3808_0_P1 &nct3808_0_P2>;
+		label = "NCT3808_ALERT_1";
+	};
 };
 
 &i2c_ctrl1 {
@@ -86,6 +137,34 @@
 	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
 	pinctrl-0 = <&i2c2_0_sda_scl_gp91_92>;
 	pinctrl-names = "default";
+
+	ppc_port0: syv682x@40 {
+		compatible = "silergy,syv682x";
+		status = "okay";
+		reg = <0x40>;
+		frs_en_gpio = <&usb_c0_frs_en>;
+	};
+
+	bc12_port0: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+		irq = <&int_usb_c0_bc12>;
+	};
+
+	ppc_port2: syv682x@42 {
+		compatible = "silergy,syv682x";
+		status = "okay";
+		reg = <0x42>;
+		frs_en_gpio = <&usb_c2_frs_en>;
+	};
+
+	bc12_port2: pi3usb9201@5d {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5d>;
+		irq = <&int_usb_c2_bc12>;
+	};
 };
 
 &i2c_ctrl2 {
@@ -97,6 +176,20 @@
 	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
 	pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>;
 	pinctrl-names = "default";
+
+	usb_c0_bb_retimer: jhl8040r-c0@56 {
+		compatible = "intel,jhl8040r";
+		reg = <0x56>;
+		int-pin = <&usb_c0_rt_int_odl>;
+		reset-pin = <&usb_c0_rt_rst_odl>;
+	};
+
+	usb_c2_bb_retimer: jhl8040r-c2@57 {
+		compatible = "intel,jhl8040r";
+		reg = <0x57>;
+		int-pin = <&usb_c2_rt_int_odl>;
+		reset-pin = <&usb_c2_rt_rst_odl>;
+	};
 };
 
 &i2c_ctrl3 {
@@ -108,6 +201,16 @@
 	clock-frequency = <I2C_BITRATE_FAST>;
 	pinctrl-0 = <&i2c4_1_sda_scl_gpf2_f3>;
 	pinctrl-names = "default";
+
+	tcpc_port1: ps8xxx@b {
+		compatible = "parade,ps8xxx";
+		reg = <0xb>;
+		tcpc-flags = <(
+			TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V |
+			TCPC_FLAGS_CONTROL_VCONN |
+			TCPC_FLAGS_CONTROL_FRS)>;
+	};
 };
 
 &i2c_ctrl4 {
@@ -130,6 +233,19 @@
 	clock-frequency = <I2C_BITRATE_FAST>;
 	pinctrl-0 = <&i2c6_1_sda_scl_gpe3_e4>;
 	pinctrl-names = "default";
+
+	ppc_port1: nx20p348x@72 {
+		compatible = "nxp,nx20p348x";
+		status = "okay";
+		reg = <0x72>;
+	};
+
+	bc12_port1: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+		irq = <&int_usb_c1_bc12>;
+	};
 };
 
 &i2c_ctrl6 {
@@ -147,6 +263,21 @@
 		reg = <0x20>;
 		label = "I2C_ADDR_MP2964_FLAGS";
 	};
+
+	charger: bq25710@9 {
+		compatible = "ti,bq25710";
+		status = "okay";
+		reg = <0x9>;
+	};
+
+	cbi_eeprom: eeprom@50 {
+		compatible = "atmel,at24";
+		reg = <0x50>;
+		size = <2048>;
+		pagesize = <16>;
+		address-width = <8>;
+		timeout = <5>;
+	};
 };
 
 &i2c_ctrl7 {
diff --git a/zephyr/projects/brya/include/gpio_map.h b/zephyr/projects/brya/include/gpio_map.h
deleted file mode 100644
index 98f3463132..0000000000
--- a/zephyr/projects/brya/include/gpio_map.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __ZEPHYR_GPIO_MAP_H
-#define __ZEPHYR_GPIO_MAP_H
-
-#include <zephyr/devicetree.h>
-#include <gpio_signal.h>
-
-#define GPIO_ENTERING_RW	GPIO_UNIMPLEMENTED
-
-#define GPIO_SEQ_EC_DSW_PWROK GPIO_PG_EC_DSW_PWROK
-
-/* TODO(fabiobaltieri): make this a named-temp-sensors property, deprecate the
- * Kconfig option.
- */
-#define GPIO_TEMP_SENSOR_POWER GPIO_EN_S5_RAILS
-
-#endif /* __ZEPHYR_GPIO_MAP_H */
diff --git a/zephyr/projects/brya/interrupts.dts b/zephyr/projects/brya/interrupts.dts
index 7132c12f77..1adca3e035 100644
--- a/zephyr/projects/brya/interrupts.dts
+++ b/zephyr/projects/brya/interrupts.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/brya/kblight_hooks.c b/zephyr/projects/brya/kblight_hooks.c
index e00d8953db..d6d795f28e 100644
--- a/zephyr/projects/brya/kblight_hooks.c
+++ b/zephyr/projects/brya/kblight_hooks.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/brya/keyboard.dts b/zephyr/projects/brya/keyboard.dts
index 4f06764810..91fad2db92 100644
--- a/zephyr/projects/brya/keyboard.dts
+++ b/zephyr/projects/brya/keyboard.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,7 +7,6 @@
 	kblight {
 		compatible = "cros-ec,kblight-pwm";
 		pwms = <&pwm3 0 PWM_HZ(2400) PWM_POLARITY_NORMAL>;
-		frequency = <2400>;
 	};
 };
 
@@ -41,6 +40,8 @@
 		&kso10_gp07
 		&kso11_gp06
 		&kso12_gp05
+		&kso13_gp04
+		&kso14_gp82
 	>;
 	pinctrl-names = "default";
 };
diff --git a/zephyr/projects/brya/motionsense.dts b/zephyr/projects/brya/motionsense.dts
index dd3f479042..78b5d2387e 100644
--- a/zephyr/projects/brya/motionsense.dts
+++ b/zephyr/projects/brya/motionsense.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022 The Chromium OS Authors
+ * Copyright 2022 The ChromiumOS Authors
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -29,11 +29,9 @@
 	motionsense-mutex {
 		compatible = "cros-ec,motionsense-mutex";
 		mutex_lis2dw12: lis2dw12-mutex {
-			label = "LIS2DW12_MUTEX";
 		};
 
 		mutex_lsm6dso: lsm6dso-mutex {
-			label = "LSM6DSO_MUTEX";
 		};
 	};
 
@@ -67,7 +65,12 @@
 			status = "okay";
 		};
 
-		lsm6dso_data: lsm6dso-drv-data {
+		lsm6dso_accel_data: lsm6dso-drv-data {
+			compatible = "cros-ec,drvdata-lsm6dso";
+			status = "okay";
+		};
+
+		lsm6dso_gyro_data: lsm6dso-drv-data {
 			compatible = "cros-ec,drvdata-lsm6dso";
 			status = "okay";
 		};
@@ -139,7 +142,7 @@
 
 	/*
 	 * List of motion sensors that creates motion_sensors array.
-	 * The label "lid_accel" and "base_accel" are used to indicate
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
 	 * motion sensor IDs for lid angle calculation.
 	 */
 	motionsense-sensor {
@@ -147,7 +150,6 @@
 			compatible = "cros-ec,lis2dw12";
 			status = "okay";
 
-			label = "Lid Accel";
 			active-mask = "SENSOR_ACTIVE_S0_S3";
 			location = "MOTIONSENSE_LOC_LID";
 			mutex = <&mutex_lis2dw12>;
@@ -160,11 +162,9 @@
 				compatible =
 					"cros-ec,motionsense-sensor-config";
 				ec-s0 {
-					label = "SENSOR_CONFIG_EC_S0";
 					odr = <(10000 | ROUND_UP_FLAG)>;
 				};
 				ec-s3 {
-					label = "SENSOR_CONFIG_EC_S3";
 					odr = <(10000 | ROUND_UP_FLAG)>;
 				};
 			};
@@ -174,25 +174,22 @@
 			compatible = "cros-ec,lsm6dso-accel";
 			status = "okay";
 
-			label = "Base Accel";
 			active-mask = "SENSOR_ACTIVE_S0_S3";
 			location = "MOTIONSENSE_LOC_BASE";
 			mutex = <&mutex_lsm6dso>;
 			port = <&i2c_sensor>;
 			rot-standard-ref = <&base_rot_ref>;
 			default-range = <4>;
-			drv-data = <&lsm6dso_data>;
+			drv-data = <&lsm6dso_accel_data>;
 			i2c-spi-addr-flags = "LSM6DSO_ADDR0_FLAGS";
 			configs {
 				compatible =
 					"cros-ec,motionsense-sensor-config";
 				ec-s0 {
-					label = "SENSOR_CONFIG_EC_S0";
 					odr = <(13000 | ROUND_UP_FLAG)>;
 					ec-rate = <(100 * USEC_PER_MSEC)>;
 				};
 				ec-s3 {
-					label = "SENSOR_CONFIG_EC_S3";
 					odr = <(10000 | ROUND_UP_FLAG)>;
 					ec-rate = <(100 * USEC_PER_MSEC)>;
 				};
@@ -203,14 +200,13 @@
 			compatible = "cros-ec,lsm6dso-gyro";
 			status = "okay";
 
-			label = "Base Gyro";
 			active-mask = "SENSOR_ACTIVE_S0_S3";
 			location = "MOTIONSENSE_LOC_BASE";
 			mutex = <&mutex_lsm6dso>;
 			port = <&i2c_sensor>;
 			rot-standard-ref = <&base_rot_ref>;
 			default-range = <(1000 | ROUND_UP_FLAG)>; /* dps */
-			drv-data = <&lsm6dso_data>;
+			drv-data = <&lsm6dso_gyro_data>;
 			i2c-spi-addr-flags = "LSM6DSO_ADDR0_FLAGS";
 		};
 
@@ -218,7 +214,6 @@
 			compatible = "cros-ec,tcs3400-clear";
 			status = "okay";
 
-			label = "Clear Light";
 			active-mask = "SENSOR_ACTIVE_S0_S3";
 			location = "MOTIONSENSE_LOC_CAMERA";
 			port = <&i2c_sensor>;
@@ -230,7 +225,6 @@
 					"cros-ec,motionsense-sensor-config";
 				ec-s0 {
 					/* Run ALS sensor in S0 */
-					label = "SENSOR_CONFIG_EC_S0";
 					odr = <1000>;
 				};
 			};
@@ -240,7 +234,6 @@
 			compatible = "cros-ec,tcs3400-rgb";
 			status = "okay";
 
-			label = "RGB Light";
 			active-mask = "SENSOR_ACTIVE_S0_S3";
 			location = "MOTIONSENSE_LOC_CAMERA";
 			default-range = <0x10000>; /* scale = 1x, uscale = 0 */
diff --git a/zephyr/projects/brya/prj.conf b/zephyr/projects/brya/prj.conf
index 7ce897ae5f..19b523261b 100644
--- a/zephyr/projects/brya/prj.conf
+++ b/zephyr/projects/brya/prj.conf
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -35,9 +35,9 @@ CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=y
 
 # eSPI
 CONFIG_ESPI=y
-CONFIG_PLATFORM_EC_ESPI_VW_SLP_S4=y
-CONFIG_PLATFORM_EC_ESPI_VW_SLP_S5=y
-CONFIG_PLATFORM_EC_ESPI_DEFAULT_VW_WIDTH_US=150
+CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S4=y
+CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S5=y
+CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US=150
 
 # I2C
 CONFIG_I2C=y
@@ -86,9 +86,6 @@ CONFIG_PLATFORM_EC_TEMP_SENSOR=y
 CONFIG_PLATFORM_EC_THERMISTOR=y
 CONFIG_PLATFORM_EC_TEMP_SENSOR_POWER=y
 
-# Miscellaneous configs
-CONFIG_PLATFORM_EC_HIBERNATE_PSL=y
-
 # MKBP event
 CONFIG_PLATFORM_EC_MKBP_EVENT=y
 CONFIG_PLATFORM_EC_MKBP_INPUT_DEVICES=y
diff --git a/zephyr/projects/brya/prj_brya.conf b/zephyr/projects/brya/prj_brya.conf
index 48f98f479d..5aaf86a8c9 100644
--- a/zephyr/projects/brya/prj_brya.conf
+++ b/zephyr/projects/brya/prj_brya.conf
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/projects/brya/pwm_leds.dts b/zephyr/projects/brya/pwm_leds.dts
index 4f5157317d..4321b4bd34 100644
--- a/zephyr/projects/brya/pwm_leds.dts
+++ b/zephyr/projects/brya/pwm_leds.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,7 +20,6 @@
 		compatible = "cros-ec,pwm-leds";
 
 		leds = <&pwm_led0 &pwm_led1>;
-		frequency = <4800>;
 
 			      /*<amber   white>*/
 		color-map-red    = <0    0>;
diff --git a/zephyr/projects/brya/temp_sensors.dts b/zephyr/projects/brya/temp_sensors.dts
index f4505a3bc1..ae436a2c6b 100644
--- a/zephyr/projects/brya/temp_sensors.dts
+++ b/zephyr/projects/brya/temp_sensors.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,58 +6,66 @@
 #include <cros/thermistor/thermistor.dtsi>
 
 / {
+	temp_ddr_soc: ddr_soc {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_30K9_47K_4050B>;
+		adc = <&adc_ddr_soc>;
+	};
+
+	temp_ambient: ambient {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_30K9_47K_4050B>;
+		adc = <&adc_ambient>;
+	};
+
+	temp_charger: charger {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_30K9_47K_4050B>;
+		adc = <&adc_charger>;
+	};
+
+	temp_wwan: wwan {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_30K9_47K_4050B>;
+		adc = <&adc_wwan>;
+	};
+
 	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
 		ddr_soc {
-			compatible = "cros-ec,temp-sensor-thermistor",
-				     "cros-ec,temp-sensor";
-			thermistor = <&thermistor_3V3_30K9_47K_4050B>;
-			label = "DDR and SOC";
-			enum-name = "TEMP_SENSOR_1_DDR_SOC";
 			temp_fan_off = <35>;
 			temp_fan_max = <60>;
 			temp_host_high = <85>;
 			temp_host_halt = <90>;
 			temp_host_release_high = <80>;
-			adc = <&adc_ddr_soc>;
+			sensor = <&temp_ddr_soc>;
 		};
+
 		ambient {
-			compatible = "cros-ec,temp-sensor-thermistor",
-				     "cros-ec,temp-sensor";
-			thermistor = <&thermistor_3V3_30K9_47K_4050B>;
-			label = "Ambient";
-			enum-name = "TEMP_SENSOR_2_AMBIENT";
 			temp_fan_off = <35>;
 			temp_fan_max = <60>;
 			temp_host_high = <85>;
 			temp_host_halt = <90>;
 			temp_host_release_high = <80>;
-			adc = <&adc_ambient>;
+			sensor = <&temp_ambient>;
 		};
+
 		charger {
-			compatible = "cros-ec,temp-sensor-thermistor",
-				     "cros-ec,temp-sensor";
-			thermistor = <&thermistor_3V3_30K9_47K_4050B>;
-			label = "Charger";
-			enum-name = "TEMP_SENSOR_3_CHARGER";
 			temp_fan_off = <35>;
 			temp_fan_max = <65>;
 			temp_host_high = <105>;
 			temp_host_halt = <120>;
 			temp_host_release_high = <90>;
-			adc = <&adc_charger>;
+			sensor = <&temp_charger>;
 		};
+
 		wwan {
-			compatible = "cros-ec,temp-sensor-thermistor",
-				     "cros-ec,temp-sensor";
-			thermistor = <&thermistor_3V3_30K9_47K_4050B>;
-			label = "WWAN";
-			enum-name = "TEMP_SENSOR_4_WWAN";
 			temp_fan_off = <35>;
 			temp_fan_max = <60>;
 			temp_host_high = <130>;
 			temp_host_halt = <130>;
 			temp_host_release_high = <100>;
-			adc = <&adc_wwan>;
+			sensor = <&temp_wwan>;
 		};
 	};
 };
diff --git a/zephyr/projects/brya/usbc.dts b/zephyr/projects/brya/usbc.dts
index 181acd837e..1be9ac94ac 100644
--- a/zephyr/projects/brya/usbc.dts
+++ b/zephyr/projects/brya/usbc.dts
@@ -1,10 +1,8 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
- #include <dt-bindings/usb_pd_tcpm.h>
-
 / {
 	usbc {
 		#address-cells = <1>;
@@ -13,37 +11,17 @@
 		port0@0 {
 			compatible = "named-usbc-port";
 			reg = <0>;
-			bc12 {
-				compatible = "pericom,pi3usb9201";
-				status = "okay";
-				irq = <&int_usb_c0_bc12>;
-				port = <&c0_c2_bc12>;
-				i2c-addr-flags = "PI3USB9201_I2C_ADDR_3_FLAGS";
-			};
-			tcpc {
-				compatible = "nuvoton,nct38xx";
-				gpio-dev = <&nct3808_0_P1>;
-				port = <&tcpc0_2>;
-				i2c-addr-flags = "NCT38XX_I2C_ADDR1_1_FLAGS";
-				tcpc-flags = <(
-					TCPC_FLAGS_TCPCI_REV2_0 |
-					TCPC_FLAGS_NO_DEBUG_ACC_CONTROL)>;
+			bc12 = <&bc12_port0>;
+			tcpc = <&tcpc_port0>;
+			chg = <&charger>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_c0_bb_retimer
+					     &virtual_mux_c0>;
 			};
-			chg {
-				compatible = "ti,bq25710";
-				status = "okay";
-				port = <&i2c_charger>;
-			};
-			usb-muxes = <&usb_c0_bb_retimer &virtual_mux_c0>;
+			ppc = <&ppc_port0>;
 		};
 		port0-muxes {
-			usb_c0_bb_retimer: jhl8040r-c0 {
-				compatible = "intel,jhl8040r";
-				port = <&retimer0_2>;
-				i2c-addr-flags = <0x56>;
-				int-pin = <&usb_c0_rt_int_odl>;
-				reset-pin = <&usb_c0_rt_rst_odl>;
-			};
 			virtual_mux_c0: virtual-mux-c0 {
 				compatible = "cros-ec,usbc-mux-virtual";
 			};
@@ -52,24 +30,13 @@
 		port1@1 {
 			compatible = "named-usbc-port";
 			reg = <1>;
-			bc12 {
-				compatible = "pericom,pi3usb9201";
-				status = "okay";
-				irq = <&int_usb_c1_bc12>;
-				port = <&c1_bc12>;
-				i2c-addr-flags = "PI3USB9201_I2C_ADDR_3_FLAGS";
+			bc12 = <&bc12_port1>;
+			tcpc = <&tcpc_port1>;
+			usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_c1 &tcpci_mux_c1>;
 			};
-			tcpc {
-				compatible = "parade,ps8xxx";
-				port = <&tcpc1>;
-				i2c-addr-flags = "PS8XXX_I2C_ADDR1_FLAGS";
-				tcpc-flags = <(
-					TCPC_FLAGS_TCPCI_REV2_0 |
-					TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V |
-					TCPC_FLAGS_CONTROL_VCONN |
-					TCPC_FLAGS_CONTROL_FRS)>;
-			};
-			usb-muxes = <&virtual_mux_c1 &tcpci_mux_c1>;
+			ppc = <&ppc_port1>;
 		};
 		port1-muxes {
 			tcpci_mux_c1: tcpci-mux-c1 {
@@ -84,30 +51,16 @@
 		port2@2 {
 			compatible = "named-usbc-port";
 			reg = <2>;
-			bc12 {
-				compatible = "pericom,pi3usb9201";
-				status = "okay";
-				irq = <&int_usb_c2_bc12>;
-				port = <&c0_c2_bc12>;
-				i2c-addr-flags = "PI3USB9201_I2C_ADDR_1_FLAGS";
-			};
-			tcpc {
-				compatible = "nuvoton,nct38xx";
-				gpio-dev = <&nct3808_0_P2>;
-				port = <&tcpc0_2>;
-				i2c-addr-flags = "NCT38XX_I2C_ADDR2_1_FLAGS";
-				tcpc-flags = <(TCPC_FLAGS_TCPCI_REV2_0)>;
+			bc12 = <&bc12_port2>;
+			tcpc = <&tcpc_port2>;
+			usb-mux-chain-2 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_c2_bb_retimer
+					     &virtual_mux_c2>;
 			};
-			usb-muxes = <&usb_c2_bb_retimer &virtual_mux_c2>;
+			ppc = <&ppc_port2>;
 		};
 		port2-muxes {
-			usb_c2_bb_retimer: jhl8040r-c2 {
-				compatible = "intel,jhl8040r";
-				port = <&retimer0_2>;
-				i2c-addr-flags = <0x57>;
-				int-pin = <&usb_c2_rt_int_odl>;
-				reset-pin = <&usb_c2_rt_rst_odl>;
-			};
 			virtual_mux_c2: virtual-mux-c2 {
 				compatible = "cros-ec,usbc-mux-virtual";
 			};
diff --git a/zephyr/projects/corsola/BUILD.py b/zephyr/projects/corsola/BUILD.py
index 83ad865cb1..32ccd9ebf1 100644
--- a/zephyr/projects/corsola/BUILD.py
+++ b/zephyr/projects/corsola/BUILD.py
@@ -1,15 +1,15 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 """Define zmake projects for corsola."""
 
-# Default chip is it8xxx2, some variants will use NPCX9X.
+# Default chip is it81202bx, some variants will use NPCX9X.
 
 
 def register_corsola_project(
     project_name,
-    chip="it8xxx2",
+    chip="it81202bx",
     extra_dts_overlays=(),
     extra_kconfig_files=(),
 ):
@@ -39,12 +39,14 @@ register_corsola_project(
         here / "gpio_krabby.dts",
         here / "i2c_krabby.dts",
         here / "interrupts_krabby.dts",
-        here / "cbi_eeprom.dts",
         here / "led_krabby.dts",
         here / "motionsense_krabby.dts",
         here / "usbc_krabby.dts",
     ],
-    extra_kconfig_files=[here / "prj_krabby.conf"],
+    extra_kconfig_files=[
+        here / "prj_it81202_base.conf",
+        here / "prj_krabby.conf",
+    ],
 )
 
 register_corsola_project(
@@ -56,7 +58,6 @@ register_corsola_project(
         here / "host_interface_npcx.dts",
         here / "i2c_kingler.dts",
         here / "interrupts_kingler.dts",
-        here / "cbi_eeprom.dts",
         here / "gpio_kingler.dts",
         here / "npcx_keyboard.dts",
         here / "led_kingler.dts",
@@ -64,7 +65,10 @@ register_corsola_project(
         here / "usbc_kingler.dts",
         here / "default_gpio_pinctrl_kingler.dts",
     ],
-    extra_kconfig_files=[here / "prj_kingler.conf"],
+    extra_kconfig_files=[
+        here / "prj_npcx993_base.conf",
+        here / "prj_kingler.conf",
+    ],
 )
 
 register_corsola_project(
@@ -76,9 +80,10 @@ register_corsola_project(
         here / "host_interface_npcx.dts",
         here / "i2c_kingler.dts",
         here / "interrupts_kingler.dts",
-        here / "cbi_eeprom.dts",
+        here / "cbi_steelix.dts",
         here / "gpio_steelix.dts",
         here / "npcx_keyboard.dts",
+        here / "keyboard_steelix.dts",
         here / "led_steelix.dts",
         here / "motionsense_kingler.dts",
         here / "motionsense_steelix.dts",
@@ -87,7 +92,47 @@ register_corsola_project(
         here / "default_gpio_pinctrl_kingler.dts",
     ],
     extra_kconfig_files=[
-        here / "prj_kingler.conf",
+        here / "prj_npcx993_base.conf",
         here / "prj_steelix.conf",
     ],
 )
+
+
+register_corsola_project(
+    "tentacruel",
+    extra_dts_overlays=[
+        here / "adc_tentacruel.dts",
+        here / "battery_tentacruel.dts",
+        here / "cbi_tentacruel.dts",
+        here / "gpio_tentacruel.dts",
+        here / "i2c_tentacruel.dts",
+        here / "interrupts_tentacruel.dts",
+        here / "led_tentacruel.dts",
+        here / "motionsense_tentacruel.dts",
+        here / "usbc_tentacruel.dts",
+        here / "thermistor_tentacruel.dts",
+    ],
+    extra_kconfig_files=[
+        here / "prj_it81202_base.conf",
+        here / "prj_tentacruel.conf",
+    ],
+)
+
+register_corsola_project(
+    "magikarp",
+    extra_dts_overlays=[
+        here / "adc_magikarp.dts",
+        here / "battery_magikarp.dts",
+        here / "cbi_magikarp.dts",
+        here / "gpio_magikarp.dts",
+        here / "i2c_magikarp.dts",
+        here / "interrupts_magikarp.dts",
+        here / "led_magikarp.dts",
+        here / "motionsense_magikarp.dts",
+        here / "usbc_magikarp.dts",
+    ],
+    extra_kconfig_files=[
+        here / "prj_it81202_base.conf",
+        here / "prj_magikarp.conf",
+    ],
+)
diff --git a/zephyr/projects/corsola/CMakeLists.txt b/zephyr/projects/corsola/CMakeLists.txt
index 2bd50910ee..f92bb2b702 100644
--- a/zephyr/projects/corsola/CMakeLists.txt
+++ b/zephyr/projects/corsola/CMakeLists.txt
@@ -1,10 +1,10 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 cmake_minimum_required(VERSION 3.13.1)
 
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
 
 cros_ec_library_include_directories(include)
 
@@ -24,8 +24,6 @@ if(DEFINED CONFIG_BOARD_KRABBY)
 	zephyr_library_sources("src/krabby/hooks.c"
 			       "src/krabby/charger_workaround.c")
 	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_I2C "src/krabby/i2c.c")
-	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LED_COMMON
-				     "src/krabby/led.c")
 	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC
 				     "src/krabby/usb_pd_policy.c")
 	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC
@@ -43,6 +41,7 @@ elseif(DEFINED CONFIG_BOARD_KINGLER)
 				     "src/kingler/button.c")
 elseif(DEFINED CONFIG_BOARD_STEELIX)
 	project(steelix)
+	zephyr_library_sources("src/kingler/board_steelix.c")
 	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_I2C "src/kingler/i2c.c")
 	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LED_COMMON
 				     "src/kingler/led_steelix.c")
@@ -50,5 +49,28 @@ elseif(DEFINED CONFIG_BOARD_STEELIX)
 				     "src/kingler/usb_pd_policy.c")
 	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC
 				     "src/kingler/usbc_config.c")
+
+elseif(DEFINED CONFIG_BOARD_TENTACRUEL)
+	project(tentacruel)
+	zephyr_library_sources("src/krabby/hooks.c"
+				"src/krabby/charger_workaround.c"
+				"src/krabby/sensor_tentacruel.c"
+				"src/krabby/temp_tentacruel.c")
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_I2C "src/krabby/i2c.c")
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC
+				"src/krabby/usb_pd_policy.c")
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC
+				"src/krabby/usbc_config_tentacruel.c")
+
+elseif(DEFINED CONFIG_BOARD_MAGIKARP)
+	project(magikarp)
+	zephyr_library_sources("src/krabby/hooks.c"
+				"src/krabby/sensor_magikarp.c")
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_I2C "src/krabby/i2c.c")
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC
+				"src/krabby/usb_pd_policy.c")
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC
+				"src/krabby/usbc_config.c")
+
 endif()
 
diff --git a/zephyr/projects/corsola/Kconfig b/zephyr/projects/corsola/Kconfig
index b05d68acc1..4f66601c20 100644
--- a/zephyr/projects/corsola/Kconfig
+++ b/zephyr/projects/corsola/Kconfig
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -20,6 +20,18 @@ config BOARD_STEELIX
 	  Build Google Steelix variant board. Steelix is a variant of Kingler
 	  and has MediaTek MT8186 SoC with NPCX993FA0BX EC.
 
+config BOARD_TENTACRUEL
+	bool "Google Tentacruel Board"
+	help
+	  Build Google Tentacruel variant board. Tentacruel is a variant of Krabby
+	  and has MediaTek MT8186 SoC with ITE it81202-bx EC.
+
+config BOARD_MAGIKARP
+	bool "Google Magikarp Board"
+	help
+	  Build Google Magikarp variant board. Magikarp is a variant of Krabby
+	  and has MediaTek MT8186 SoC with ITE it81202-bx EC.
+
 config VARIANT_CORSOLA_DB_DETECTION
 	bool "Corsola Platform Runtime Daughter Board Detection"
 	depends on PLATFORM_EC_USB_PD_TCPC_RUNTIME_CONFIG
diff --git a/zephyr/projects/corsola/adc_kingler.dts b/zephyr/projects/corsola/adc_kingler.dts
index e7e70caa70..7b69abe48a 100644
--- a/zephyr/projects/corsola/adc_kingler.dts
+++ b/zephyr/projects/corsola/adc_kingler.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,7 +12,6 @@
 		compatible = "named-adc-channels";
 
 		adc_charger_pmon_r {
-			label = "ADC_CHARGER_PMON_R";
 			enum-name = "ADC_PSYS";
 			io-channels = <&adc0 0>;
 			/*
@@ -21,17 +20,14 @@
 			mul = <21043>;
 		};
 		adc_ec_id0 {
-			label = "ADC_EC_ID0";
 			enum-name = "ADC_ID_0";
 			io-channels = <&adc0 1>;
 		};
 		adc_ec_id1 {
-			label = "ADC_EC_ID1";
 			enum-name = "ADC_ID_1";
 			io-channels = <&adc0 2>;
 		};
 		adc_charger_amon_r {
-			label = "ADC_AMON_R";
 			enum-name = "ADC_AMON_BMON";
 			io-channels = <&adc0 3>;
 			mul = <1000>;
diff --git a/zephyr/projects/corsola/adc_krabby.dts b/zephyr/projects/corsola/adc_krabby.dts
index 68336f0a70..be65e9eea7 100644
--- a/zephyr/projects/corsola/adc_krabby.dts
+++ b/zephyr/projects/corsola/adc_krabby.dts
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,23 +8,19 @@
 		compatible = "named-adc-channels";
 
 		adc_vbus_c0 {
-			label = "VBUS_C0";
 			enum-name = "ADC_VBUS_C0";
 			io-channels = <&adc0 0>;
 			mul = <10>;
 		};
 		adc_board_id0 {
-			label = "BOARD_ID_0";
 			enum-name = "ADC_BOARD_ID_0";
 			io-channels = <&adc0 1>;
 		};
 		adc_board_id1 {
-			label = "BOARD_ID_1";
 			enum-name = "ADC_BOARD_ID_1";
 			io-channels = <&adc0 2>;
 		};
 		adc_vbus_c1 {
-			label = "VBUS_C1";
 			enum-name = "ADC_VBUS_C1";
 			io-channels = <&adc0 7>;
 			mul = <10>;
diff --git a/zephyr/projects/corsola/adc_magikarp.dts b/zephyr/projects/corsola/adc_magikarp.dts
new file mode 100644
index 0000000000..358af6f0f4
--- /dev/null
+++ b/zephyr/projects/corsola/adc_magikarp.dts
@@ -0,0 +1,63 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <cros/thermistor/thermistor.dtsi>
+
+/ {
+	named-adc-channels {
+		compatible = "named-adc-channels";
+		adc_vbus_c0 {
+			enum-name = "ADC_VBUS_C0";
+			io-channels = <&adc0 0>;
+			mul = <10>;
+		};
+		adc_board_id0 {
+			enum-name = "ADC_BOARD_ID_0";
+			io-channels = <&adc0 1>;
+		};
+		adc_board_id1 {
+			enum-name = "ADC_BOARD_ID_1";
+			io-channels = <&adc0 2>;
+		};
+		adc_vbus_c1 {
+			enum-name = "ADC_VBUS_C1";
+			io-channels = <&adc0 7>;
+			mul = <10>;
+		};
+		adc_ambient: ambient {
+			enum-name = "ADC_TEMP_SENSOR_2_AMBIENT";
+			io-channels = <&adc0 5>;
+		};
+	};
+};
+
+&adc0 {
+	status = "okay";
+	pinctrl-0 = <&adc0_ch0_gpi0_default
+		     &adc0_ch1_gpi1_default
+		     &adc0_ch2_gpi2_default
+		     &adc0_ch5_gpi5_default
+		     &adc0_ch7_gpi7_default>;
+	pinctrl-names = "default";
+};
+
+/ {
+	temp_ambient: ambient {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_30K9_47K_NCP15WB>;
+		adc = <&adc_ambient>;
+	};
+
+	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
+		ambient {
+			sensor = <&temp_ambient>;
+		};
+	};
+};
+
+&thermistor_3V3_30K9_47K_NCP15WB {
+	status = "okay";
+};
diff --git a/zephyr/projects/corsola/adc_tentacruel.dts b/zephyr/projects/corsola/adc_tentacruel.dts
new file mode 100644
index 0000000000..1b5e849589
--- /dev/null
+++ b/zephyr/projects/corsola/adc_tentacruel.dts
@@ -0,0 +1,66 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <cros/thermistor/thermistor.dtsi>
+
+/ {
+	named-adc-channels {
+		compatible = "named-adc-channels";
+		adc_vbus_c0 {
+			enum-name = "ADC_VBUS_C0";
+			io-channels = <&adc0 0>;
+			mul = <10>;
+		};
+		adc_board_id0 {
+			enum-name = "ADC_BOARD_ID_0";
+			io-channels = <&adc0 1>;
+		};
+		adc_board_id1 {
+			enum-name = "ADC_BOARD_ID_1";
+			io-channels = <&adc0 2>;
+		};
+		adc_vbus_c1 {
+			enum-name = "ADC_VBUS_C1";
+			io-channels = <&adc0 7>;
+			mul = <10>;
+		};
+		adc_ambient: ambient {
+			enum-name = "ADC_TEMP_SENSOR_2_AMBIENT";
+			io-channels = <&adc0 5>;
+		};
+	};
+};
+
+&adc0 {
+	status = "okay";
+	pinctrl-0 = <&adc0_ch0_gpi0_default
+		     &adc0_ch1_gpi1_default
+		     &adc0_ch2_gpi2_default
+		     &adc0_ch5_gpi5_default
+		     &adc0_ch7_gpi7_default>;
+	pinctrl-names = "default";
+};
+
+/ {
+	temp_ambient: ambient {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_30K9_47K_NCP15WB>;
+		adc = <&adc_ambient>;
+	};
+
+	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
+		ambient {
+			sensor = <&temp_ambient>;
+		};
+		temp_charger: charger {
+			sensor = <&charger>;
+		};
+	};
+};
+
+&thermistor_3V3_30K9_47K_NCP15WB {
+	status = "okay";
+};
diff --git a/zephyr/projects/corsola/battery_kingler.dts b/zephyr/projects/corsola/battery_kingler.dts
index 63d3b7ea21..b01fb8a46d 100644
--- a/zephyr/projects/corsola/battery_kingler.dts
+++ b/zephyr/projects/corsola/battery_kingler.dts
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/corsola/battery_krabby.dts b/zephyr/projects/corsola/battery_krabby.dts
index f80550c76b..ce41859182 100644
--- a/zephyr/projects/corsola/battery_krabby.dts
+++ b/zephyr/projects/corsola/battery_krabby.dts
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,7 @@
 / {
 	batteries {
 		default_battery: c235 {
-			compatible = "as3gwrc3ka,c235-41", "battery-smart";
+			compatible = "celxpert,c235-41", "battery-smart";
 		};
 	};
 };
diff --git a/zephyr/projects/corsola/battery_magikarp.dts b/zephyr/projects/corsola/battery_magikarp.dts
new file mode 100644
index 0000000000..bbdd6ac0c5
--- /dev/null
+++ b/zephyr/projects/corsola/battery_magikarp.dts
@@ -0,0 +1,12 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	batteries {
+		default_battery: smp_c31n1915 {
+			compatible = "smp,c31n1915", "battery-smart";
+		};
+	};
+};
diff --git a/zephyr/projects/corsola/battery_steelix.dts b/zephyr/projects/corsola/battery_steelix.dts
index 63d3b7ea21..594c83478c 100644
--- a/zephyr/projects/corsola/battery_steelix.dts
+++ b/zephyr/projects/corsola/battery_steelix.dts
@@ -1,15 +1,24 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 / {
 	batteries {
-		default_battery: smp_l20m3pg2 {
-			compatible = "smp,l20m3pg2", "battery-smart";
+		default_battery: byd_l22b3pg0 {
+			compatible = "byd,l22b3pg0", "battery-smart";
 		};
-		lgc_l20l3pg2 {
-			compatible = "lgc,l20l3pg2", "battery-smart";
+		celxpert_l22c3pg0 {
+			compatible = "celxpert,l22c3pg0", "battery-smart";
+		};
+		cosmx_l22x3pg0 {
+			compatible = "cosmx,l22x3pg0", "battery-smart";
+		};
+		smp_l22m3pg0 {
+			compatible = "smp,l22m3pg0", "battery-smart";
+		};
+		sunwoda_l22d3pg0 {
+			compatible = "sunwoda,l22d3pg0", "battery-smart";
 		};
 	};
 };
diff --git a/zephyr/projects/corsola/battery_tentacruel.dts b/zephyr/projects/corsola/battery_tentacruel.dts
new file mode 100644
index 0000000000..f116c20a51
--- /dev/null
+++ b/zephyr/projects/corsola/battery_tentacruel.dts
@@ -0,0 +1,12 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	batteries {
+		default_battery: dynapack_c140254 {
+			compatible = "dynapack,c140254", "battery-smart";
+		};
+	};
+};
diff --git a/zephyr/projects/corsola/cbi_eeprom.dts b/zephyr/projects/corsola/cbi_eeprom.dts
deleted file mode 100644
index 7f95e2ed6d..0000000000
--- a/zephyr/projects/corsola/cbi_eeprom.dts
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
- &i2c_pwr_cbi {
-	cbi_eeprom: eeprom@50 {
-		compatible = "atmel,at24";
-		reg = <0x50>;
-		label = "EEPROM_CBI";
-		size = <2048>;
-		pagesize = <16>;
-		address-width = <8>;
-		timeout = <5>;
-	};
-};
diff --git a/zephyr/projects/corsola/cbi_magikarp.dts b/zephyr/projects/corsola/cbi_magikarp.dts
new file mode 100644
index 0000000000..5eac6b82c6
--- /dev/null
+++ b/zephyr/projects/corsola/cbi_magikarp.dts
@@ -0,0 +1,36 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	/* magikarp-specific fw_config fields. */
+	magikarp-fw-config {
+		compatible = "cros-ec,cbi-fw-config";
+		/*
+		 * FW_CONFIG field to describe mainboard orientation in chassis.
+		 */
+		base-gyro {
+			enum-name = "FW_BASE_GYRO";
+			start = <0>;
+			size = <2>;
+
+			None {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_BASE_NONE";
+				value = <0>;
+			};
+			icm42607 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_BASE_ICM42607";
+				value = <1>;
+				default;
+			};
+			bmi323 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_BASE_BMI323";
+				value = <2>;
+			};
+		};
+	};
+};
diff --git a/zephyr/projects/corsola/cbi_steelix.dts b/zephyr/projects/corsola/cbi_steelix.dts
new file mode 100644
index 0000000000..e282eb25ab
--- /dev/null
+++ b/zephyr/projects/corsola/cbi_steelix.dts
@@ -0,0 +1,54 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	steelix-fw-config {
+		compatible = "cros-ec,cbi-fw-config";
+
+		/*
+		 * FW_CONFIG field to indicate the device is clamshell
+		 * or convertible.
+		 */
+		form_factor {
+			enum-name = "FORM_FACTOR";
+			start = <13>;
+			size = <3>;
+
+			convertible {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "CONVERTIBLE";
+				value = <1>;
+			};
+			clamshell {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "CLAMSHELL";
+				value = <0>;
+			};
+		};
+
+		/* FW_CONFIG field to indicate which DB is attached. */
+		db_config: db {
+			enum-name = "DB";
+			start = <0>;
+			size = <4>;
+
+			sub-board-1 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "DB_NONE";
+				value = <0>;
+			};
+			sub-board-2 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "DB_USBA_HDMI";
+				value = <1>;
+			};
+			sub-board-3 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "DB_USBA_HDMI_LTE";
+				value = <2>;
+			};
+		};
+	};
+};
diff --git a/zephyr/projects/corsola/cbi_tentacruel.dts b/zephyr/projects/corsola/cbi_tentacruel.dts
new file mode 100644
index 0000000000..2cd4594417
--- /dev/null
+++ b/zephyr/projects/corsola/cbi_tentacruel.dts
@@ -0,0 +1,36 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	/* tentacruel-specific fw_config fields. */
+	tentacruel-fw-config {
+		compatible = "cros-ec,cbi-fw-config";
+		/*
+		 * FW_CONFIG field to describe mainboard orientation in chassis.
+		 */
+		base-gyro {
+			enum-name = "FW_BASE_GYRO";
+			start = <8>;
+			size = <2>;
+
+			None {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_BASE_NONE";
+				value = <0>;
+			};
+			icm42607 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_BASE_ICM42607";
+				value = <1>;
+				default;
+			};
+			bmi323 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_BASE_BMI323";
+				value = <2>;
+			};
+		};
+	};
+};
diff --git a/zephyr/projects/corsola/common.dts b/zephyr/projects/corsola/common.dts
index 52c8eeddf2..001dcc7ce3 100644
--- a/zephyr/projects/corsola/common.dts
+++ b/zephyr/projects/corsola/common.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/corsola/default_gpio_pinctrl_kingler.dts b/zephyr/projects/corsola/default_gpio_pinctrl_kingler.dts
index d25b388726..604658a145 100644
--- a/zephyr/projects/corsola/default_gpio_pinctrl_kingler.dts
+++ b/zephyr/projects/corsola/default_gpio_pinctrl_kingler.dts
@@ -1,44 +1,44 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Adds the &alt1_no_lpc_espi setting over the NPCX9 default setting. */
 &{/def-io-conf-list} {
-	pinctrl-0 = <&alt0_gpio_no_spip
-		   &alt0_gpio_no_fpip
-		   &alt1_no_pwrgd
-		   &alt1_no_lpc_espi
-		   &alta_no_peci_en
-		   &altd_npsl_in1_sl
-		   &altd_npsl_in2_sl
-		   &altd_psl_in3_sl
-		   &altd_psl_in4_sl
-		   &alt7_no_ksi0_sl
-		   &alt7_no_ksi1_sl
-		   &alt7_no_ksi2_sl
-		   &alt7_no_ksi3_sl
-		   &alt7_no_ksi4_sl
-		   &alt7_no_ksi5_sl
-		   &alt7_no_ksi6_sl
-		   &alt7_no_ksi7_sl
-		   &alt8_no_kso00_sl
-		   &alt8_no_kso01_sl
-		   &alt8_no_kso02_sl
-		   &alt8_no_kso03_sl
-		   &alt8_no_kso04_sl
-		   &alt8_no_kso05_sl
-		   &alt8_no_kso06_sl
-		   &alt8_no_kso07_sl
-		   &alt9_no_kso08_sl
-		   &alt9_no_kso09_sl
-		   &alt9_no_kso10_sl
-		   &alt9_no_kso11_sl
-		   &alt9_no_kso12_sl
-		   &alt9_no_kso13_sl
-		   &alt9_no_kso14_sl
-		   &alt9_no_kso15_sl
-		   &alta_no_kso16_sl
-		   &alta_no_kso17_sl
-		   &altg_psl_gpo_sl>;
+	pinmux = <&alt0_gpio_no_spip
+		  &alt0_gpio_no_fpip
+		  &alt1_no_pwrgd
+		  &alt1_no_lpc_espi
+		  &alta_no_peci_en
+		  &altd_npsl_in1_sl
+		  &altd_npsl_in2_sl
+		  &altd_psl_in3_sl
+		  &altd_psl_in4_sl
+		  &alt7_no_ksi0_sl
+		  &alt7_no_ksi1_sl
+		  &alt7_no_ksi2_sl
+		  &alt7_no_ksi3_sl
+		  &alt7_no_ksi4_sl
+		  &alt7_no_ksi5_sl
+		  &alt7_no_ksi6_sl
+		  &alt7_no_ksi7_sl
+		  &alt8_no_kso00_sl
+		  &alt8_no_kso01_sl
+		  &alt8_no_kso02_sl
+		  &alt8_no_kso03_sl
+		  &alt8_no_kso04_sl
+		  &alt8_no_kso05_sl
+		  &alt8_no_kso06_sl
+		  &alt8_no_kso07_sl
+		  &alt9_no_kso08_sl
+		  &alt9_no_kso09_sl
+		  &alt9_no_kso10_sl
+		  &alt9_no_kso11_sl
+		  &alt9_no_kso12_sl
+		  &alt9_no_kso13_sl
+		  &alt9_no_kso14_sl
+		  &alt9_no_kso15_sl
+		  &alta_no_kso16_sl
+		  &alta_no_kso17_sl
+		  &altg_psl_gpo_sl>;
 };
diff --git a/zephyr/projects/corsola/gpio_kingler.dts b/zephyr/projects/corsola/gpio_kingler.dts
index 0199f985fa..d3a4c1be90 100644
--- a/zephyr/projects/corsola/gpio_kingler.dts
+++ b/zephyr/projects/corsola/gpio_kingler.dts
@@ -1,10 +1,11 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 / {
 	aliases {
+		gpio-cbi-wp = &gpio_ec_cbi_wp;
 		gpio-wp = &gpio_ec_wp_l;
 		gpio-kbd-kso2 = &gpio_ec_kso_02_inv;
 	};
@@ -12,34 +13,36 @@
 	named-gpios {
 		compatible = "named-gpios";
 
+		/*
+		 * In npcx9 series, gpio46, gpio47, and the whole gpio5 port
+		 * belong to VHIF power well. On kingler, it is connencted to
+		 * 1.8V.
+		 */
 		base_imu_int_l: base_imu_int_l {
-			gpios = <&gpio5 6 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+			gpios = <&gpio5 6 GPIO_INPUT>;
 		};
 		spi_ap_clk_ec {
-			gpios = <&gpio5 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+			gpios = <&gpio5 5 GPIO_INPUT>;
 		};
 		spi_ap_cs_ec_l {
-			gpios = <&gpio5 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+			gpios = <&gpio5 3 GPIO_INPUT>;
 		};
 		spi_ap_do_ec_di {
-			gpios = <&gpio4 6 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+			gpios = <&gpio4 6 GPIO_INPUT>;
 		};
 		spi_ap_di_ec_do {
-			gpios = <&gpio4 7 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+			gpios = <&gpio4 7 GPIO_INPUT>;
 		};
 		ap_ec_warm_rst_req: ap_ec_warm_rst_req {
-			gpios = <&gpio5 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8 |
-				 GPIO_ACTIVE_HIGH)>;
+			gpios = <&gpio5 1 (GPIO_INPUT | GPIO_ACTIVE_HIGH)>;
 			enum-name = "GPIO_AP_EC_WARM_RST_REQ";
 		};
 		ap_ec_wdtrst_l: ap_ec_wdtrst_l {
-			gpios = <&gpio5 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8 |
-				 GPIO_ACTIVE_LOW)>;
+			gpios = <&gpio5 2 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
 			enum-name = "GPIO_AP_EC_WDTRST_L";
 		};
 		ap_in_sleep_l: ap_in_sleep_l {
-			gpios = <&gpio5 4 (GPIO_INPUT | GPIO_VOLTAGE_1P8 |
-				 GPIO_ACTIVE_LOW)>;
+			gpios = <&gpio5 4 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
 			enum-name = "GPIO_AP_IN_SLEEP_L";
 		};
 		gpio_en_ulp: en_ulp {
@@ -85,8 +88,12 @@
 		ec_pen_chg_dis_odl {
 			gpios = <&gpioe 4 GPIO_INPUT>;
 		};
+		gpio_ec_cbi_wp: ec_cbi_wp {
+			gpios = <&gpio8 0 GPIO_OUTPUT_LOW>;
+		};
 		gpio_ec_wp_l: ec_wp_odl {
-			gpios = <&gpioe 3 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+			gpios = <&gpioe 3 (GPIO_INPUT | GPIO_ACTIVE_LOW |
+				 GPIO_VOLTAGE_1P8)>;
 		};
 		lid_accel_int_l {
 			gpios = <&gpiob 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
@@ -108,7 +115,6 @@
 		};
 		ec_entering_rw {
 			gpios = <&gpio0 3 GPIO_OUTPUT_LOW>;
-			enum-name = "GPIO_ENTERING_RW";
 		};
 		charger_prochot_odl {
 			gpios = <&gpiob 1 GPIO_INPUT>;
@@ -138,13 +144,17 @@
 		gpio_x_ec_gpio2: x_ec_gpio2 {
 			gpios = <&gpiod 4 GPIO_INPUT>;
 		};
+		/*
+		 * In npcx9 series, gpio93-97, the whole gpioa port, and gpiob0
+		 * belong to VSPI power rail. On kingler, it is connencted to
+		 * 1.8V.
+		 */
 		ap_sysrst_odl_r: ap_sysrst_odl_r {
-			gpios = <&gpioa 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8 |
-				 GPIO_ACTIVE_LOW)>;
+			gpios = <&gpioa 1 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
 			enum-name = "GPIO_AP_EC_SYSRST_ODL";
 		};
 		gpio_ap_xhci_init_done: ap_xhci_init_done {
-			gpios = <&gpioa 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+			gpios = <&gpioa 3 GPIO_INPUT>;
 		};
 		gpio_usb_c0_ppc_int_odl: usb_c0_ppc_int_odl {
 			gpios = <&gpio6 7 GPIO_INPUT>;
@@ -172,9 +182,8 @@
 		gpio_usb_c0_tcpc_rst: usb_c0_tcpc_rst {
 			gpios = <&gpioc 0 GPIO_OUTPUT_LOW>;
 		};
-		en_pp5000_usb_a0_vbus: en_pp5000_usb_a0_vbus_x {
+		en_pp5000_usb_a0_vbus: en_pp5000_usb_a0_vbus {
 			gpios = <&gpio6 0 GPIO_OUTPUT_LOW>;
-			enum-name = "GPIO_EN_PP5000_USB_A0_VBUS";
 		};
 		gpio_hdmi_prsnt_odl: hdmi_prsnt_odl {
 			gpios = <&gpio3 7 GPIO_INPUT>;
@@ -193,7 +202,7 @@
 			gpios = <&gpioc 7 GPIO_INPUT>;
 		};
 		ec_ap_dp_hpd_odl: ec_ap_dp_hpd_odl {
-			gpios = <&gpio6 1 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>;
+			gpios = <&gpio6 1 GPIO_ODR_HIGH>;
 		};
 		ec_pmic_en_odl {
 			gpios = <&gpio7 4 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>;
@@ -211,6 +220,10 @@
 			gpios = <&gpioe 5 GPIO_INPUT>;
 			enum-name = "GPIO_CCD_MODE_ODL";
 		};
+		/* unimplemented GPIOs */
+		entering-rw {
+			enum-name = "GPIO_ENTERING_RW";
+		};
 	};
 
 	/*
@@ -233,12 +246,4 @@
 			&int_lid_open
 		>;
 	};
-
-	def-lvol-io-list {
-		compatible = "nuvoton,npcx-lvolctrl-def";
-		lvol-io-pads = <
-			&lvol_ioe3 /*  GPIOE3 GPIO_EC_WP_L */
-			&lvol_io40 /*  GPIO40 GPIO_EC_BL_EN_OD */
-		>;
-	};
 };
diff --git a/zephyr/projects/corsola/gpio_krabby.dts b/zephyr/projects/corsola/gpio_krabby.dts
index 7246e8a40c..32498ab606 100644
--- a/zephyr/projects/corsola/gpio_krabby.dts
+++ b/zephyr/projects/corsola/gpio_krabby.dts
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,6 +7,7 @@
 
 / {
 	aliases {
+		gpio-cbi-wp = &gpio_ec_cbi_wp;
 		gpio-wp = &ec_flash_wp_odl;
 	};
 
@@ -56,6 +57,9 @@
 			gpios = <&gpioe 5 GPIO_INPUT>;
 			enum-name = "GPIO_AC_PRESENT";
 		};
+		gpio_ec_cbi_wp: ec_cbi_wp {
+			gpios = <&gpioc 3 GPIO_OUTPUT_LOW>;
+		};
 		ec_flash_wp_odl: ec_flash_wp_odl {
 			gpios = <&gpioi 4 (GPIO_INPUT | GPIO_VOLTAGE_1P8 |
 					   GPIO_ACTIVE_LOW)>;
@@ -111,7 +115,6 @@
 		};
 		en_pp5000_usb_a0_vbus: en_pp5000_usb_a0_vbus {
 			gpios = <&gpiob 7 GPIO_OUTPUT_LOW>;
-			enum-name = "GPIO_EN_PP5000_USB_A0_VBUS";
 		};
 		usb_c0_ppc_frsinfo: usb_c0_ppc_frsinfo {
 			gpios = <&gpiof 0 GPIO_INPUT>;
@@ -183,7 +186,6 @@
 			<&gpioa 3 GPIO_INPUT_PULL_DOWN>,
 			<&gpioa 6 GPIO_INPUT_PULL_DOWN>,
 			<&gpioa 7 GPIO_INPUT_PULL_DOWN>,
-			<&gpioc 3 GPIO_INPUT_PULL_DOWN>,
 			<&gpiod 7 GPIO_INPUT_PULL_DOWN>,
 			<&gpiof 1 GPIO_INPUT_PULL_DOWN>,
 			<&gpioh 0 GPIO_INPUT_PULL_DOWN>,
diff --git a/zephyr/projects/corsola/gpio_magikarp.dts b/zephyr/projects/corsola/gpio_magikarp.dts
new file mode 100644
index 0000000000..aeaeab2431
--- /dev/null
+++ b/zephyr/projects/corsola/gpio_magikarp.dts
@@ -0,0 +1,238 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/gpio_defines.h>
+
+/ {
+	aliases {
+		gpio-cbi-wp = &gpio_ec_cbi_wp;
+		gpio-wp = &ec_flash_wp_odl;
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		power_button_l: power_button_l {
+			gpios = <&gpioe 4 GPIO_INPUT>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		lid_open: lid_open {
+			gpios = <&gpioe 2 GPIO_INPUT>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+		tablet_mode_l: tablet_mode_l {
+			gpios = <&gpioj 7 GPIO_INPUT>;
+			enum-name = "GPIO_TABLET_MODE_L";
+		};
+		ap_ec_warm_rst_req: ap_ec_warm_rst_req {
+			gpios = <&gpiod 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8 |
+					   GPIO_ACTIVE_HIGH)>;
+			enum-name = "GPIO_AP_EC_WARM_RST_REQ";
+		};
+		ap_in_sleep_l: ap_in_sleep_l {
+			gpios = <&gpiob 6 (GPIO_INPUT | GPIO_VOLTAGE_1P8 |
+					   GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_AP_IN_SLEEP_L";
+		};
+		base_imu_int_l: base_imu_int_l {
+			gpios = <&gpiom 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		lid_accel_int_l: lid_accel_int_l {
+			gpios = <&gpiom 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		volume_down_l: volume_down_l {
+			gpios = <&gpiod 5 GPIO_INPUT>;
+			enum-name = "GPIO_VOLUME_DOWN_L";
+		};
+		volume_up_l: volume_up_l {
+			gpios = <&gpiod 6 GPIO_INPUT>;
+			enum-name = "GPIO_VOLUME_UP_L";
+		};
+		gpio_ap_xhci_init_done: ap_xhci_init_done {
+			gpios = <&gpioj 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		ac_present: ac_present {
+			gpios = <&gpioe 5 GPIO_INPUT>;
+			enum-name = "GPIO_AC_PRESENT";
+		};
+		gpio_ec_cbi_wp: ec_cbi_wp {
+			gpios = <&gpioc 3 GPIO_OUTPUT_LOW>;
+		};
+		ec_flash_wp_odl: ec_flash_wp_odl {
+			gpios = <&gpioi 4 (GPIO_INPUT | GPIO_VOLTAGE_1P8 |
+					   GPIO_ACTIVE_LOW)>;
+		};
+		spi0_cs: spi0_cs {
+			gpios = <&gpiom 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		gpio_x_ec_gpio2: x_ec_gpio2 {
+			gpios = <&gpiob 2 GPIO_INPUT>;
+		};
+		usb_c0_ppc_bc12_int_odl: usb_c0_ppc_bc12_int_odl {
+			gpios = <&gpiod 1 GPIO_INPUT>;
+		};
+		usb_c1_bc12_charger_int_odl: usb_c1_bc12_charger_int_odl {
+			gpios = <&gpioj 4 GPIO_INPUT>;
+		};
+		ec_pmic_en_odl: ec_pmic_en_odl {
+			gpios = <&gpiod 0 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>;
+			enum-name = "GPIO_EC_PMIC_EN_ODL";
+		};
+		en_pp5000_z2: en_pp5000_z2 {
+			gpios = <&gpioc 6 GPIO_OUTPUT_HIGH>;
+		};
+		gpio_en_ulp: en_ulp {
+			gpios = <&gpioe 3 GPIO_OUTPUT_LOW>;
+		};
+		sys_rst_odl: sys_rst_odl {
+			gpios = <&gpiog 1 GPIO_ODR_LOW>;
+			enum-name = "GPIO_SYS_RST_ODL";
+		};
+		gpio_ec_bl_en_od: ec_bl_en_od {
+			gpios = <&gpiob 5 (GPIO_ODR_LOW | GPIO_VOLTAGE_1P8)>;
+		};
+		ap_sysrst_odl_r: ap_ec_sysrst_odl {
+			gpios = <&gpioj 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8 |
+					   GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_AP_EC_SYSRST_ODL";
+		};
+		ap_ec_wdtrst_l: ap_ec_wdtrst_l {
+			gpios = <&gpioc 7 (GPIO_INPUT | GPIO_VOLTAGE_1P8 |
+					   GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_AP_EC_WDTRST_L";
+		};
+		ec_int_l: ec_int_l {
+			gpios = <&gpioe 6 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>;
+			enum-name = "GPIO_EC_INT_L";
+		};
+		dp_aux_path_sel: dp_aux_path_sel {
+			gpios = <&gpiog 0 GPIO_OUTPUT_HIGH>;
+		};
+		ec_ap_dp_hpd_odl: ec_ap_dp_hpd_odl {
+			gpios = <&gpioj 0 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>;
+		};
+		en_pp5000_usb_a0_vbus: en_pp5000_usb_a0_vbus {
+			gpios = <&gpiob 7 GPIO_OUTPUT_LOW>;
+		};
+		usb_c0_ppc_frsinfo: usb_c0_ppc_frsinfo {
+			gpios = <&gpiof 0 GPIO_INPUT>;
+		};
+		ec_batt_pres_odl: ec_batt_pres_odl {
+			gpios = <&gpioc 0 GPIO_INPUT>;
+			enum-name = "GPIO_BATT_PRES_ODL";
+		};
+		en_ec_id_odl: en_ec_id_odl {
+			gpios = <&gpioh 5 GPIO_ODR_HIGH>;
+		};
+		entering_rw: entering_rw {
+			gpios = <&gpioc 5 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_ENTERING_RW";
+		};
+		gpio_en_5v_usm: en_5v_usm {
+			gpios = <&gpiog 3 GPIO_OUTPUT_LOW>;
+		};
+		usb_a0_fault_odl: usb_a0_fault_odl {
+			gpios = <&gpioj 6 GPIO_INPUT>;
+		};
+		gpio_ec_x_gpio1: ec_x_gpio1 {
+			gpios = <&gpioh 4 GPIO_OUTPUT_LOW>;
+		};
+		gpio_ec_x_gpio3: ec_x_gpio3 {
+			gpios = <&gpioj 1 GPIO_OUTPUT_LOW>;
+		};
+		gpio_hdmi_prsnt_odl: hdmi_prsnt_odl {
+			gpios = <&gpioj 3 GPIO_INPUT>;
+		};
+		gpio_packet_mode_en: packet_mode_en {
+			gpios = <&gpiod 4 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_PACKET_MODE_EN";
+		};
+		ccd_mode_odl {
+			gpios = <&gpioc 4 GPIO_INPUT>;
+			enum-name = "GPIO_CCD_MODE_ODL";
+		};
+	};
+
+	/*
+	 * aliases for sub-board GPIOs
+	 */
+	aliases {
+		gpio-en-hdmi-pwr = &gpio_ec_x_gpio1;
+		gpio-usb-c1-frs-en = &gpio_ec_x_gpio1;
+		gpio-usb-c1-ppc-int-odl = &gpio_x_ec_gpio2;
+		gpio-ps185-ec-dp-hpd = &gpio_x_ec_gpio2;
+		gpio-usb-c1-dp-in-hpd = &gpio_ec_x_gpio3;
+		gpio-ps185-pwrdn-odl = &gpio_ec_x_gpio3;
+	};
+
+	hibernate-wake-pins {
+		compatible = "cros-ec,hibernate-wake-pins";
+		wakeup-irqs = <&int_ac_present
+			       &int_power_button
+			       &int_lid_open>;
+	};
+
+	unused-pins {
+		compatible = "unused-gpios";
+
+		unused-gpios =
+			/* pg_pp5000_z2_od */
+			<&gpiod 2 GPIO_INPUT>,
+			/* pg_mt6315_proc_b_odl */
+			<&gpioe 1 GPIO_INPUT>,
+			/* ec_pen_chg_dis_odl */
+			<&gpioh 3 GPIO_ODR_HIGH>,
+			/* unnamed nc pins */
+			<&gpioa 3 GPIO_INPUT_PULL_DOWN>,
+			<&gpioa 6 GPIO_INPUT_PULL_DOWN>,
+			<&gpioa 7 GPIO_INPUT_PULL_DOWN>,
+			<&gpiof 1 GPIO_INPUT_PULL_DOWN>,
+			/* reserved for b:241345809 */
+			<&gpiod 7 GPIO_OUTPUT_LOW>,
+			<&gpiog 2 GPIO_INPUT_PULL_DOWN>,
+			<&gpioh 0 GPIO_INPUT_PULL_DOWN>,
+			<&gpioh 6 GPIO_INPUT_PULL_DOWN>,
+			<&gpioi 3 GPIO_INPUT_PULL_DOWN>,
+			<&gpioi 6 GPIO_INPUT_PULL_DOWN>,
+			<&gpiom 6 (GPIO_INPUT_PULL_DOWN | GPIO_VOLTAGE_1P8)>,
+			/* spi_clk_gpg6 */
+			<&gpiog 6 GPIO_INPUT_PULL_UP>,
+			/* spi_mosi_gpg4 */
+			<&gpiog 4 GPIO_OUTPUT_LOW>,
+			/* spi_miso_gpg5 */
+			<&gpiog 5 GPIO_OUTPUT_LOW>,
+			/* spi_cs_gpg7 */
+			<&gpiog 7 GPIO_OUTPUT_LOW>;
+	};
+};
+
+&pinctrl {
+	/* I2C property setting */
+	i2c0_clk_gpb3_default: i2c0_clk_gpb3_default {
+		gpio-voltage = "1v8";
+	};
+	i2c0_data_gpb4_default: i2c0_data_gpb4_default {
+		gpio-voltage = "1v8";
+	};
+	i2c3_clk_gpf2_default: i2c3_clk_gpf2_default {
+		gpio-voltage = "1v8";
+	};
+	i2c3_data_gpf3_default: i2c3_data_gpf3_default {
+		gpio-voltage = "1v8";
+	};
+	/* SHI property setting */
+	shi_mosi_gpm0_default: shi_mosi_gpm0_default {
+		gpio-voltage = "1v8";
+	};
+	shi_miso_gpm1_default: shi_miso_gpm1_default {
+		gpio-voltage = "1v8";
+	};
+	shi_clk_gpm4_default: shi_clk_gpm4_default {
+		gpio-voltage = "1v8";
+	};
+	shi_cs_gpm5_default: shi_cs_gpm5_default {
+		gpio-voltage = "1v8";
+	};
+};
diff --git a/zephyr/projects/corsola/gpio_steelix.dts b/zephyr/projects/corsola/gpio_steelix.dts
index 3e0375564f..299d809583 100644
--- a/zephyr/projects/corsola/gpio_steelix.dts
+++ b/zephyr/projects/corsola/gpio_steelix.dts
@@ -1,10 +1,11 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 / {
 	aliases {
+		gpio-cbi-wp = &gpio_ec_cbi_wp;
 		gpio-wp = &gpio_ec_wp_l;
 		gpio-kbd-kso2 = &gpio_ec_kso_02_inv;
 	};
@@ -12,34 +13,36 @@
 	named-gpios {
 		compatible = "named-gpios";
 
+		/*
+		 * In npcx9 series, gpio46, gpio47, and the whole gpio5 port
+		 * belong to VHIF power well. On steelix, it is connencted to
+		 * 1.8V.
+		 */
 		base_imu_int_l: base_imu_int_l {
-			gpios = <&gpio5 6 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+			gpios = <&gpio5 6 GPIO_INPUT>;
 		};
 		spi_ap_clk_ec {
-			gpios = <&gpio5 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+			gpios = <&gpio5 5 GPIO_INPUT>;
 		};
 		spi_ap_cs_ec_l {
-			gpios = <&gpio5 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+			gpios = <&gpio5 3 GPIO_INPUT>;
 		};
 		spi_ap_do_ec_di {
-			gpios = <&gpio4 6 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+			gpios = <&gpio4 6 GPIO_INPUT>;
 		};
 		spi_ap_di_ec_do {
-			gpios = <&gpio4 7 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+			gpios = <&gpio4 7 GPIO_INPUT>;
 		};
 		ap_ec_warm_rst_req: ap_ec_warm_rst_req {
-			gpios = <&gpio5 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8 |
-				 GPIO_ACTIVE_HIGH)>;
+			gpios = <&gpio5 1 (GPIO_INPUT | GPIO_ACTIVE_HIGH)>;
 			enum-name = "GPIO_AP_EC_WARM_RST_REQ";
 		};
 		ap_ec_wdtrst_l: ap_ec_wdtrst_l {
-			gpios = <&gpio5 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8 |
-				 GPIO_ACTIVE_LOW)>;
+			gpios = <&gpio5 2 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
 			enum-name = "GPIO_AP_EC_WDTRST_L";
 		};
 		ap_in_sleep_l: ap_in_sleep_l {
-			gpios = <&gpio5 4 (GPIO_INPUT | GPIO_VOLTAGE_1P8 |
-				 GPIO_ACTIVE_LOW)>;
+			gpios = <&gpio5 4 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
 			enum-name = "GPIO_AP_IN_SLEEP_L";
 		};
 		gpio_en_ulp: en_ulp {
@@ -84,7 +87,6 @@
 		};
 		en_pp5000_usb_a1_vbus: en_pp5000_usb_a1_vbus_x {
 			gpios = <&gpiof 5 GPIO_OUTPUT_LOW>;
-			enum-name = "GPIO_EN_PP5000_USB_A1_VBUS";
 		};
 		usb_a1_fault_odl {
 			gpios = <&gpiof 4 GPIO_INPUT>;
@@ -92,8 +94,12 @@
 		ec_pen_chg_dis_odl {
 			gpios = <&gpioe 4 GPIO_INPUT>;
 		};
+		gpio_ec_cbi_wp: ec_cbi_wp {
+			gpios = <&gpio8 0 GPIO_OUTPUT_LOW>;
+		};
 		gpio_ec_wp_l: ec_wp_odl {
-			gpios = <&gpioe 3 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+			gpios = <&gpioe 3 (GPIO_INPUT | GPIO_ACTIVE_LOW |
+				 GPIO_VOLTAGE_1P8)>;
 		};
 		lid_accel_int_l {
 			gpios = <&gpiob 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
@@ -115,7 +121,6 @@
 		};
 		ec_entering_rw {
 			gpios = <&gpio0 3 GPIO_OUTPUT_LOW>;
-			enum-name = "GPIO_ENTERING_RW";
 		};
 		charger_prochot_odl {
 			gpios = <&gpiob 1 GPIO_INPUT>;
@@ -145,13 +150,17 @@
 		gpio_x_ec_gpio2: x_ec_gpio2 {
 			gpios = <&gpiod 4 GPIO_INPUT>;
 		};
+		/*
+		 * In npcx9 series, gpio93-97, the whole gpioa port, and gpiob0
+		 * belong to VSPI power well. On steelix, it is connencted to
+		 * 1.8V.
+		 */
 		ap_sysrst_odl_r: ap_sysrst_odl_r {
-			gpios = <&gpioa 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8 |
-				 GPIO_ACTIVE_LOW)>;
+			gpios = <&gpioa 1 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
 			enum-name = "GPIO_AP_EC_SYSRST_ODL";
 		};
 		gpio_ap_xhci_init_done: ap_xhci_init_done {
-			gpios = <&gpioa 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+			gpios = <&gpioa 3 GPIO_INPUT>;
 		};
 		gpio_usb_c0_ppc_int_odl: usb_c0_ppc_int_odl {
 			gpios = <&gpio6 7 GPIO_INPUT>;
@@ -179,9 +188,8 @@
 		gpio_usb_c0_tcpc_rst: usb_c0_tcpc_rst {
 			gpios = <&gpioc 0 GPIO_OUTPUT_LOW>;
 		};
-		en_pp5000_usb_a0_vbus: en_pp5000_usb_a0_vbus_x {
+		en_pp5000_usb_a0_vbus: en_pp5000_usb_a0_vbus {
 			gpios = <&gpio6 0 GPIO_OUTPUT_LOW>;
-			enum-name = "GPIO_EN_PP5000_USB_A0_VBUS";
 		};
 		gpio_hdmi_prsnt_odl: hdmi_prsnt_odl {
 			gpios = <&gpio3 7 GPIO_INPUT>;
@@ -200,7 +208,7 @@
 			gpios = <&gpioc 7 GPIO_INPUT>;
 		};
 		ec_ap_dp_hpd_odl: ec_ap_dp_hpd_odl {
-			gpios = <&gpio6 1 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>;
+			gpios = <&gpio6 1 GPIO_ODR_HIGH>;
 		};
 		ec_pmic_en_odl {
 			gpios = <&gpio7 4 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>;
@@ -218,6 +226,10 @@
 			gpios = <&gpioe 5 GPIO_INPUT>;
 			enum-name = "GPIO_CCD_MODE_ODL";
 		};
+		/* unimplemented GPIOs */
+		entering-rw {
+			enum-name = "GPIO_ENTERING_RW";
+		};
 	};
 
 	/*
@@ -240,12 +252,4 @@
 			&int_lid_open
 		>;
 	};
-
-	def-lvol-io-list {
-		compatible = "nuvoton,npcx-lvolctrl-def";
-		lvol-io-pads = <
-			&lvol_ioe3 /*  GPIOE3 GPIO_EC_WP_L */
-			&lvol_io40 /*  GPIO40 GPIO_EC_BL_EN_OD */
-		>;
-	};
 };
diff --git a/zephyr/projects/corsola/gpio_tentacruel.dts b/zephyr/projects/corsola/gpio_tentacruel.dts
new file mode 100644
index 0000000000..75607cb561
--- /dev/null
+++ b/zephyr/projects/corsola/gpio_tentacruel.dts
@@ -0,0 +1,239 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/gpio_defines.h>
+
+/ {
+	aliases {
+		gpio-cbi-wp = &gpio_ec_cbi_wp;
+		gpio-wp = &ec_flash_wp_odl;
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		power_button_l: power_button_l {
+			gpios = <&gpioe 4 GPIO_INPUT>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		lid_open: lid_open {
+			gpios = <&gpioe 2 GPIO_INPUT>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+		tablet_mode_l: tablet_mode_l {
+			gpios = <&gpioj 7 GPIO_INPUT>;
+			enum-name = "GPIO_TABLET_MODE_L";
+		};
+		ap_ec_warm_rst_req: ap_ec_warm_rst_req {
+			gpios = <&gpiod 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8 |
+					   GPIO_ACTIVE_HIGH)>;
+			enum-name = "GPIO_AP_EC_WARM_RST_REQ";
+		};
+		ap_in_sleep_l: ap_in_sleep_l {
+			gpios = <&gpiob 6 (GPIO_INPUT | GPIO_VOLTAGE_1P8 |
+					   GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_AP_IN_SLEEP_L";
+		};
+		base_imu_int_l: base_imu_int_l {
+			gpios = <&gpiom 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		lid_accel_int_l: lid_accel_int_l {
+			gpios = <&gpiom 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		volume_down_l: volume_down_l {
+			gpios = <&gpiod 5 GPIO_INPUT>;
+			enum-name = "GPIO_VOLUME_DOWN_L";
+		};
+		volume_up_l: volume_up_l {
+			gpios = <&gpiod 6 GPIO_INPUT>;
+			enum-name = "GPIO_VOLUME_UP_L";
+		};
+		gpio_ap_xhci_init_done: ap_xhci_init_done {
+			gpios = <&gpioj 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		ac_present: ac_present {
+			gpios = <&gpioe 5 GPIO_INPUT>;
+			enum-name = "GPIO_AC_PRESENT";
+		};
+		gpio_ec_cbi_wp: ec_cbi_wp {
+			gpios = <&gpioc 3 GPIO_OUTPUT_LOW>;
+		};
+		ec_flash_wp_odl: ec_flash_wp_odl {
+			gpios = <&gpioi 4 (GPIO_INPUT | GPIO_VOLTAGE_1P8 |
+					   GPIO_ACTIVE_LOW)>;
+		};
+		spi0_cs: spi0_cs {
+			gpios = <&gpiom 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		gpio_x_ec_gpio2: x_ec_gpio2 {
+			gpios = <&gpiob 2 GPIO_INPUT>;
+		};
+		usb_c0_ppc_int_odl: usb_c0_ppc_int_odl {
+			gpios = <&gpiod 1 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C0_PPC_INT_ODL";
+		};
+		usb_c0_bc12_int_odl: usb_c0_bc12_int_odl {
+			gpios = <&gpiof 1 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C0_BC12_INT_ODL";
+		};
+		usb_c1_bc12_charger_int_odl: usb_c1_bc12_charger_int_odl {
+			gpios = <&gpioj 4 GPIO_INPUT>;
+		};
+		ec_pmic_en_odl: ec_pmic_en_odl {
+			gpios = <&gpiod 0 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>;
+			enum-name = "GPIO_EC_PMIC_EN_ODL";
+		};
+		en_pp5000_z2: en_pp5000_z2 {
+			gpios = <&gpioc 6 GPIO_OUTPUT_HIGH>;
+		};
+		gpio_en_ulp: en_ulp {
+			gpios = <&gpioe 3 GPIO_OUTPUT_LOW>;
+		};
+		sys_rst_odl: sys_rst_odl {
+			gpios = <&gpiog 1 GPIO_ODR_LOW>;
+			enum-name = "GPIO_SYS_RST_ODL";
+		};
+		gpio_ec_bl_en_od: ec_bl_en_od {
+			gpios = <&gpiob 5 (GPIO_ODR_LOW | GPIO_VOLTAGE_1P8)>;
+		};
+		ap_sysrst_odl_r: ap_ec_sysrst_odl {
+			gpios = <&gpioj 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8 |
+					   GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_AP_EC_SYSRST_ODL";
+		};
+		ap_ec_wdtrst_l: ap_ec_wdtrst_l {
+			gpios = <&gpioc 7 (GPIO_INPUT | GPIO_VOLTAGE_1P8 |
+					   GPIO_ACTIVE_LOW)>;
+			enum-name = "GPIO_AP_EC_WDTRST_L";
+		};
+		ec_int_l: ec_int_l {
+			gpios = <&gpioe 6 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>;
+			enum-name = "GPIO_EC_INT_L";
+		};
+		dp_aux_path_sel: dp_aux_path_sel {
+			gpios = <&gpiog 0 GPIO_OUTPUT_HIGH>;
+		};
+		ec_ap_dp_hpd_odl: ec_ap_dp_hpd_odl {
+			gpios = <&gpioj 0 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>;
+		};
+		en_pp5000_usb_a0_vbus: en_pp5000_usb_a0_vbus {
+			gpios = <&gpiob 7 GPIO_OUTPUT_LOW>;
+		};
+		usb_c0_frs_en: usb_c0_frs_en {
+			gpios = <&gpiof 0 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_USB_C0_FRS_EN";
+		};
+		ec_batt_pres_odl: ec_batt_pres_odl {
+			gpios = <&gpioc 0 GPIO_INPUT>;
+			enum-name = "GPIO_BATT_PRES_ODL";
+		};
+		en_ec_id_odl: en_ec_id_odl {
+			gpios = <&gpioh 5 GPIO_ODR_HIGH>;
+		};
+		entering_rw: entering_rw {
+			gpios = <&gpioc 5 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_ENTERING_RW";
+		};
+		gpio_en_5v_usm: en_5v_usm {
+			gpios = <&gpiog 3 GPIO_OUTPUT_LOW>;
+		};
+		usb_a0_fault_odl: usb_a0_fault_odl {
+			gpios = <&gpioj 6 GPIO_INPUT>;
+		};
+		gpio_ec_x_gpio1: ec_x_gpio1 {
+			gpios = <&gpioh 4 GPIO_OUTPUT_LOW>;
+		};
+		gpio_ec_x_gpio3: ec_x_gpio3 {
+			gpios = <&gpioj 1 GPIO_OUTPUT_LOW>;
+		};
+		gpio_hdmi_prsnt_odl: hdmi_prsnt_odl {
+			gpios = <&gpioj 3 GPIO_INPUT>;
+		};
+		gpio_packet_mode_en: packet_mode_en {
+			gpios = <&gpiod 4 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_PACKET_MODE_EN";
+		};
+	};
+
+	/*
+	 * aliases for sub-board GPIOs
+	 */
+	aliases {
+		gpio-en-hdmi-pwr = &gpio_ec_x_gpio1;
+		gpio-usb-c1-frs-en = &gpio_ec_x_gpio1;
+		gpio-usb-c1-ppc-int-odl = &gpio_x_ec_gpio2;
+		gpio-ps185-ec-dp-hpd = &gpio_x_ec_gpio2;
+		gpio-usb-c1-dp-in-hpd = &gpio_ec_x_gpio3;
+		gpio-ps185-pwrdn-odl = &gpio_ec_x_gpio3;
+	};
+
+	hibernate-wake-pins {
+		compatible = "cros-ec,hibernate-wake-pins";
+		wakeup-irqs = <&int_ac_present
+			       &int_power_button
+			       &int_lid_open>;
+	};
+
+	unused-pins {
+		compatible = "unused-gpios";
+
+		unused-gpios =
+			/* pg_pp5000_z2_od */
+			<&gpiod 2 GPIO_INPUT>,
+			/* pg_mt6315_proc_b_odl */
+			<&gpioe 1 GPIO_INPUT>,
+			/* ec_pen_chg_dis_odl */
+			<&gpioh 3 GPIO_ODR_HIGH>,
+			/* ccd_mode_odl */
+			<&gpioc 4 GPIO_INPUT>,
+			/* unnamed nc pins */
+			<&gpioa 3 GPIO_INPUT_PULL_DOWN>,
+			<&gpioa 6 GPIO_INPUT_PULL_DOWN>,
+			<&gpioa 7 GPIO_INPUT_PULL_DOWN>,
+			<&gpiod 7 GPIO_INPUT_PULL_DOWN>,
+			<&gpioh 0 GPIO_INPUT_PULL_DOWN>,
+			<&gpioh 6 GPIO_INPUT_PULL_DOWN>,
+			<&gpioi 3 GPIO_INPUT_PULL_DOWN>,
+			<&gpioi 6 GPIO_INPUT_PULL_DOWN>,
+			<&gpiom 6 (GPIO_INPUT_PULL_DOWN | GPIO_VOLTAGE_1P8)>,
+			/* spi_clk_gpg6 */
+			<&gpiog 6 GPIO_INPUT_PULL_UP>,
+			/* spi_mosi_gpg4 */
+			<&gpiog 4 GPIO_OUTPUT_LOW>,
+			/* spi_miso_gpg5 */
+			<&gpiog 5 GPIO_OUTPUT_LOW>,
+			/* spi_cs_gpg7 */
+			<&gpiog 7 GPIO_OUTPUT_LOW>;
+	};
+};
+
+&pinctrl {
+	/* I2C property setting */
+	i2c0_clk_gpb3_default: i2c0_clk_gpb3_default {
+		gpio-voltage = "1v8";
+	};
+	i2c0_data_gpb4_default: i2c0_data_gpb4_default {
+		gpio-voltage = "1v8";
+	};
+	i2c3_clk_gpf2_default: i2c3_clk_gpf2_default {
+		gpio-voltage = "1v8";
+	};
+	i2c3_data_gpf3_default: i2c3_data_gpf3_default {
+		gpio-voltage = "1v8";
+	};
+	/* SHI property setting */
+	shi_mosi_gpm0_default: shi_mosi_gpm0_default {
+		gpio-voltage = "1v8";
+	};
+	shi_miso_gpm1_default: shi_miso_gpm1_default {
+		gpio-voltage = "1v8";
+	};
+	shi_clk_gpm4_default: shi_clk_gpm4_default {
+		gpio-voltage = "1v8";
+	};
+	shi_cs_gpm5_default: shi_cs_gpm5_default {
+		gpio-voltage = "1v8";
+	};
+};
diff --git a/zephyr/projects/corsola/host_interface_npcx.dts b/zephyr/projects/corsola/host_interface_npcx.dts
index 9c6a498940..14efa3c6b2 100644
--- a/zephyr/projects/corsola/host_interface_npcx.dts
+++ b/zephyr/projects/corsola/host_interface_npcx.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/corsola/i2c_kingler.dts b/zephyr/projects/corsola/i2c_kingler.dts
index c832e55d2e..4bcbeb6950 100644
--- a/zephyr/projects/corsola/i2c_kingler.dts
+++ b/zephyr/projects/corsola/i2c_kingler.dts
@@ -1,8 +1,10 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include <dt-bindings/usb_pd_tcpm.h>
+
 /*
  * Kingler and Steelix use the same dts, take care of this when modify it.
  */
@@ -13,42 +15,29 @@
 
 		i2c_sensor: sensor {
 			i2c-port = <&i2c0_0>;
-			enum-name = "I2C_PORT_SENSOR";
+			enum-names = "I2C_PORT_SENSOR";
 		};
 		i2c_usb_c0: usb-c0 {
 			i2c-port = <&i2c1_0>;
 			remote-port = <7>;
-			enum-name = "I2C_PORT_USB_C0";
+			enum-names = "I2C_PORT_USB_C0";
 		};
 		i2c_usb_c1: usb-c1 {
 			i2c-port = <&i2c2_0>;
-			enum-name = "I2C_PORT_USB_C1";
-		};
-		tcpc1 {
-			i2c-port = <&i2c2_0>;
-			enum-name = "I2C_PORT_USB_C1_TCPC";
-		};
-		ppc1 {
-			i2c-port = <&i2c2_0>;
-			enum-name = "I2C_PORT_USB_C1_PPC";
-		};
-		eeprom {
-			i2c-port = <&i2c3_0>;
-			enum-name = "I2C_PORT_EEPROM";
+			enum-names = "I2C_PORT_USB_C1",
+				"I2C_PORT_USB_C1_TCPC",
+				"I2C_PORT_USB_C1_PPC";
 		};
 		i2c_charger: charger {
 			i2c-port = <&i2c3_0>;
-			enum-name = "I2C_PORT_POWER";
+			enum-names = "I2C_PORT_POWER",
+				"I2C_PORT_EEPROM";
 		};
 		battery {
 			i2c-port = <&i2c5_0>;
 			remote-port = <1>;
-			enum-name = "I2C_PORT_BATTERY";
-		};
-		virtual-battery {
-			i2c-port = <&i2c5_0>;
-			remote-port = <1>;
-			enum-name = "I2C_PORT_VIRTUAL_BATTERY";
+			enum-names = "I2C_PORT_BATTERY",
+				"I2C_PORT_VIRTUAL_BATTERY";
 		};
 	};
 };
@@ -71,6 +60,30 @@
 	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
 	pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>;
 	pinctrl-names = "default";
+
+	bc12_port0: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+		irq = <&int_usb_c0_bc12>;
+	};
+
+	tcpc_port0: anx7447-tcpc@2c {
+		compatible = "anologix,anx7447-tcpc";
+		status = "okay";
+		reg = <0x2c>;
+		tcpc-flags = <(
+			TCPC_FLAGS_VBUS_MONITOR |
+			TCPC_FLAGS_ALERT_OD |
+			TCPC_FLAGS_CONTROL_VCONN |
+			TCPC_FLAGS_CONTROL_FRS)>;
+	};
+
+	ppc_port0: nx20p348x@72 {
+		compatible = "nxp,nx20p348x";
+		status = "okay";
+		reg = <0x72>;
+	};
 };
 
 &i2c_ctrl1 {
@@ -83,18 +96,60 @@
 	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
 	pinctrl-0 = <&i2c2_0_sda_scl_gp91_92>;
 	pinctrl-names = "default";
+
+	bc12_port1: rt1718s-bc12@40 {
+		compatible = "richtek,rt1718s-bc12";
+		status = "okay";
+		reg = <0x40>;
+	};
+
+	tcpc_port1: rt1718s-tcpc@40 {
+		compatible = "richtek,rt1718s-tcpc";
+		reg = <0x40>;
+		tcpc-flags = <(
+			TCPC_FLAGS_ALERT_OD |
+			TCPC_FLAGS_CONTROL_VCONN |
+			TCPC_FLAGS_CONTROL_FRS)>;
+	};
+
+	ppc_port1: nx20p348x@72 {
+		compatible = "nxp,nx20p348x";
+		status = "okay";
+		reg = <0x72>;
+	};
+
+	ps8743_mux_1: ps8743-mux-1@10 {
+		compatible = "parade,ps8743";
+		reg = <0x10>;
+		board-init = "ps8743_mux_1_board_init";
+	};
 };
 
 &i2c_ctrl2 {
 	status = "okay";
 };
 
-i2c_pwr_cbi: &i2c3_0 {
+&i2c3_0 {
 	label = "I2C_PWR_CBI";
 	status = "okay";
 	clock-frequency = <I2C_BITRATE_FAST>;
 	pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>;
 	pinctrl-names = "default";
+
+	charger: isl923x@9 {
+		compatible = "intersil,isl923x";
+		status = "okay";
+		reg = <0x9>;
+	};
+
+	cbi_eeprom: eeprom@50 {
+		compatible = "atmel,at24";
+		reg = <0x50>;
+		size = <2048>;
+		pagesize = <16>;
+		address-width = <8>;
+		timeout = <5>;
+	};
 };
 
 &i2c_ctrl3 {
diff --git a/zephyr/projects/corsola/i2c_krabby.dts b/zephyr/projects/corsola/i2c_krabby.dts
index 75cf3834eb..4b3c46ffe4 100644
--- a/zephyr/projects/corsola/i2c_krabby.dts
+++ b/zephyr/projects/corsola/i2c_krabby.dts
@@ -1,103 +1,21 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-/ {
-	named-i2c-ports {
-		compatible = "named-i2c-ports";
+#include "i2c_krabby_tentacruel.dtsi"
 
-		battery {
-			i2c-port = <&i2c1>;
-			remote-port = <1>;
-			enum-name = "I2C_PORT_BATTERY";
-		};
-		virtual-battery {
-			i2c-port = <&i2c1>;
-			enum-name = "I2C_PORT_VIRTUAL_BATTERY";
-		};
-		eeprom {
-			i2c-port = <&i2c0>;
-			enum-name = "I2C_PORT_EEPROM";
-		};
-		i2c_charger: charger {
-			i2c-port = <&i2c0>;
-			enum-name = "I2C_PORT_CHARGER";
-		};
-		i2c_sensor: sensor {
-			i2c-port = <&i2c3>;
-			enum-name = "I2C_PORT_SENSOR";
-		};
-		i2c_usb_c0: usb-c0 {
-			i2c-port = <&i2c2>;
-			enum-name = "I2C_PORT_USB_C0";
-		};
-		i2c_usb_c1: usb-c1 {
-			i2c-port = <&i2c4>;
-			enum-name = "I2C_PORT_USB_C1";
-		};
-		i2c_usb_mux0: usb-mux0 {
-			i2c-port = <&i2c2>;
-			enum-name = "I2C_PORT_USB_MUX0";
-		};
-		i2c_usb_mux1: usb-mux1 {
-			i2c-port = <&i2c4>;
-			enum-name = "I2C_PORT_USB_MUX1";
-		};
+&i2c0 {
+	charger: rt9490@53 {
+		compatible = "richtek,rt9490";
+		status = "okay";
+		reg = <0x53>;
 	};
-
-};
-
-i2c_pwr_cbi: &i2c0 {
-	/* EC_I2C_PWR_CBI */
-	label = "I2C_PWR_CBI";
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_FAST>;
-	pinctrl-0 = <&i2c0_clk_gpb3_default
-		     &i2c0_data_gpb4_default>;
-	pinctrl-names = "default";
-};
-
-&i2c1 {
-	/* EC_I2C_BATTERY */
-	label = "I2C_BATTERY";
-	status = "okay";
-	clock-frequency = <50000>;
-	pinctrl-0 = <&i2c1_clk_gpc1_default
-		     &i2c1_data_gpc2_default>;
-	pinctrl-names = "default";
-};
-
-&i2c2 {
-	/* EC_I2C_USB_C0 */
-	label = "I2C_USB_C0";
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_FAST>;
-	pinctrl-0 = <&i2c2_clk_gpf6_default
-		     &i2c2_data_gpf7_default>;
-	pinctrl-names = "default";
-};
-
-&i2c3 {
-	/* EC_I2C_SENSOR */
-	label = "I2C_SENSOR";
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_FAST>;
-	scl-gpios = <&gpiof 2 0>;
-	sda-gpios = <&gpiof 3 0>;
-	pinctrl-0 = <&i2c3_clk_gpf2_default
-		     &i2c3_data_gpf3_default>;
-	pinctrl-names = "default";
-	prescale-scl-low = <1>;
 };
 
 &i2c4 {
-	/* EC_I2C_USB_C1 */
-	label = "I2C_USB_C1";
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_FAST>;
-	pinctrl-0 = <&i2c4_clk_gpe0_default
-		     &i2c4_data_gpe7_default>;
-	pinctrl-names = "default";
-	prescale-scl-low = <1>;
+	tusb1064_mux_1: tusb1064-mux-1@44 {
+		compatible = "ti,tusb1064";
+		reg = <0x44>;
+	};
 };
diff --git a/zephyr/projects/corsola/i2c_krabby_tentacruel.dtsi b/zephyr/projects/corsola/i2c_krabby_tentacruel.dtsi
new file mode 100644
index 0000000000..377eaafbca
--- /dev/null
+++ b/zephyr/projects/corsola/i2c_krabby_tentacruel.dtsi
@@ -0,0 +1,136 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		battery {
+			i2c-port = <&i2c1>;
+			remote-port = <1>;
+			enum-names = "I2C_PORT_BATTERY",
+				"I2C_PORT_VIRTUAL_BATTERY";
+		};
+		i2c_charger: charger {
+			i2c-port = <&i2c0>;
+			enum-names = "I2C_PORT_CHARGER",
+				"I2C_PORT_EEPROM";
+		};
+		i2c_sensor: sensor {
+			i2c-port = <&i2c3>;
+			enum-names = "I2C_PORT_SENSOR";
+		};
+		i2c_usb_c0: usb-c0 {
+			i2c-port = <&i2c2>;
+			enum-names = "I2C_PORT_USB_C0",
+				"I2C_PORT_USB_MUX0";
+		};
+		i2c_usb_c1: usb-c1 {
+			i2c-port = <&i2c4>;
+			enum-names = "I2C_PORT_USB_C1",
+				"I2C_PORT_USB_MUX1";
+		};
+	};
+
+};
+
+&pinctrl {
+	i2c3_clk_gpf2_sleep: i2c3_clk_gpf2_sleep {
+		pinmuxs = <&pinctrlf 2 IT8XXX2_ALT_DEFAULT>;
+	};
+	i2c3_data_gpf3_sleep: i2c3_data_gpf3_sleep {
+		pinmuxs = <&pinctrlf 3 IT8XXX2_ALT_DEFAULT>;
+	};
+};
+
+&i2c0 {
+	/* EC_I2C_PWR_CBI */
+	label = "I2C_PWR_CBI";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c0_clk_gpb3_default
+		     &i2c0_data_gpb4_default>;
+	pinctrl-names = "default";
+
+	cbi_eeprom: eeprom@50 {
+		compatible = "atmel,at24";
+		reg = <0x50>;
+		size = <2048>;
+		pagesize = <16>;
+		address-width = <8>;
+		timeout = <5>;
+	};
+
+	bc12_port1: rt9490-bc12@53 {
+		compatible = "richtek,rt9490-bc12";
+		status = "okay";
+		reg = <0x53>;
+		irq = <&int_usb_c1_bc12_charger>;
+	};
+};
+
+&i2c1 {
+	/* EC_I2C_BATTERY */
+	label = "I2C_BATTERY";
+	status = "okay";
+	clock-frequency = <50000>;
+	pinctrl-0 = <&i2c1_clk_gpc1_default
+		     &i2c1_data_gpc2_default>;
+	pinctrl-names = "default";
+};
+
+&i2c2 {
+	/* EC_I2C_USB_C0 */
+	label = "I2C_USB_C0";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c2_clk_gpf6_default
+		     &i2c2_data_gpf7_default>;
+	pinctrl-names = "default";
+
+	bc12_ppc_port0: rt1739@70 {
+		compatible = "richtek,rt1739";
+		status = "okay";
+		reg = <0x70>;
+	};
+
+	it5205_mux_0: it5205-mux-0@48 {
+		compatible = "ite,it5205";
+		reg = <0x48>;
+	};
+};
+
+&i2c3 {
+	/* EC_I2C_SENSOR */
+	label = "I2C_SENSOR";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	scl-gpios = <&gpiof 2 0>;
+	sda-gpios = <&gpiof 3 0>;
+	pinctrl-0 = <&i2c3_clk_gpf2_default
+		     &i2c3_data_gpf3_default>;
+	pinctrl-1 = <&i2c3_clk_gpf2_sleep
+		     &i2c3_data_gpf3_sleep>;
+	pinctrl-names = "default", "sleep";
+	prescale-scl-low = <1>;
+};
+
+&i2c4 {
+	/* EC_I2C_USB_C1 */
+	label = "I2C_USB_C1";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c4_clk_gpe0_default
+		     &i2c4_data_gpe7_default>;
+	pinctrl-names = "default";
+	prescale-scl-low = <1>;
+
+	ppc_port1: syv682x@40 {
+		compatible = "silergy,syv682x";
+		status = "okay";
+		reg = <0x40>;
+		frs_en_gpio = <&gpio_ec_x_gpio1>;
+	};
+};
diff --git a/zephyr/projects/corsola/i2c_magikarp.dts b/zephyr/projects/corsola/i2c_magikarp.dts
new file mode 100644
index 0000000000..2039398974
--- /dev/null
+++ b/zephyr/projects/corsola/i2c_magikarp.dts
@@ -0,0 +1,21 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "i2c_krabby_tentacruel.dtsi"
+
+&i2c0 {
+	charger: rt9490@53 {
+		compatible = "richtek,rt9490";
+		status = "okay";
+		reg = <0x53>;
+	};
+};
+
+&i2c4 {
+	ps8743_mux_1: ps8743-mux-1@10 {
+		compatible = "parade,ps8743";
+		reg = <0x10>;
+	};
+};
diff --git a/zephyr/projects/corsola/i2c_tentacruel.dts b/zephyr/projects/corsola/i2c_tentacruel.dts
new file mode 100644
index 0000000000..e40dc02318
--- /dev/null
+++ b/zephyr/projects/corsola/i2c_tentacruel.dts
@@ -0,0 +1,37 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "i2c_krabby_tentacruel.dtsi"
+
+&i2c0 {
+	charger: rt9490@53 {
+		compatible = "richtek,rt9490";
+		status = "okay";
+		reg = <0x53>;
+		thermistor = <&thermistor_rt9490>;
+	};
+};
+
+&i2c2 {
+	bc12_port0: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+		irq = <&int_usb_c0_bc12>;
+	};
+	ppc_port0: syv682x@40 {
+		compatible = "silergy,syv682x";
+		status = "okay";
+		reg = <0x40>;
+		frs_en_gpio = <&usb_c0_frs_en>;
+	};
+};
+
+&i2c4 {
+	ps8743_mux_1: ps8743-mux-1@10 {
+		compatible = "parade,ps8743";
+		reg = <0x10>;
+	};
+};
diff --git a/zephyr/projects/corsola/include/baseboard_usbc_config.h b/zephyr/projects/corsola/include/baseboard_usbc_config.h
index eb09a86865..a29fd93f54 100644
--- a/zephyr/projects/corsola/include/baseboard_usbc_config.h
+++ b/zephyr/projects/corsola/include/baseboard_usbc_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,20 +8,19 @@
 #ifndef __CROS_EC_BASEBOARD_USBC_CONFIG_H
 #define __CROS_EC_BASEBOARD_USBC_CONFIG_H
 
+#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_RT1718S
+#define GPIO_EN_USB_C1_SINK RT1718S_GPIO1
+#define GPIO_EN_USB_C1_SOURCE RT1718S_GPIO2
+#define GPIO_EN_USB_C1_FRS RT1718S_GPIO3
+#endif
+
 void ppc_interrupt(enum gpio_signal signal);
 
 /* USB-A ports */
-enum usba_port {
-	USBA_PORT_A0 = 0,
-	USBA_PORT_COUNT
-};
+enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_COUNT };
 
 /* USB-C ports */
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 BUILD_ASSERT(USBC_PORT_COUNT == CONFIG_USB_PD_PORT_MAX_COUNT);
 
 /**
diff --git a/zephyr/projects/corsola/include/gpio_map.h b/zephyr/projects/corsola/include/gpio_map.h
deleted file mode 100644
index 562671b685..0000000000
--- a/zephyr/projects/corsola/include/gpio_map.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __ZEPHYR_GPIO_MAP_H
-#define __ZEPHYR_GPIO_MAP_H
-
-
-#include <zephyr/devicetree.h>
-#include <gpio_signal.h>
-
-#define GPIO_ENTERING_RW		GPIO_UNIMPLEMENTED
-
-#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_RT1718S
-#define GPIO_EN_USB_C1_SINK         RT1718S_GPIO1
-#define GPIO_EN_USB_C1_SOURCE       RT1718S_GPIO2
-#define GPIO_EN_USB_C1_FRS          RT1718S_GPIO3
-#endif
-
-#endif /* __ZEPHYR_GPIO_MAP_H */
diff --git a/zephyr/projects/corsola/include/i2c_map.h b/zephyr/projects/corsola/include/i2c_map.h
deleted file mode 100644
index e2f6c53ed2..0000000000
--- a/zephyr/projects/corsola/include/i2c_map.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __ZEPHYR_I2C_MAP_H
-#define __ZEPHYR_I2C_MAP_H
-
-#include <zephyr/devicetree.h>
-
-#include "i2c/i2c.h"
-
-#endif /* __ZEPHYR_I2C_MAP_H */
diff --git a/zephyr/projects/corsola/include/variant_db_detection.h b/zephyr/projects/corsola/include/variant_db_detection.h
index 40853016f8..285ff327f2 100644
--- a/zephyr/projects/corsola/include/variant_db_detection.h
+++ b/zephyr/projects/corsola/include/variant_db_detection.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,7 +9,8 @@
 #define __CROS_EC_CORSOLA_DB_DETECTION_H
 
 enum corsola_db_type {
-	CORSOLA_DB_NONE = -1,
+	CORSOLA_DB_UNINIT = -1,
+	CORSOLA_DB_NONE,
 	CORSOLA_DB_TYPEC,
 	CORSOLA_DB_HDMI,
 	CORSOLA_DB_COUNT,
diff --git a/zephyr/projects/corsola/interrupts_kingler.dts b/zephyr/projects/corsola/interrupts_kingler.dts
index b33251624d..38b8c2e24d 100644
--- a/zephyr/projects/corsola/interrupts_kingler.dts
+++ b/zephyr/projects/corsola/interrupts_kingler.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/corsola/interrupts_krabby.dts b/zephyr/projects/corsola/interrupts_krabby.dts
index 900ce1611e..7f2df00937 100644
--- a/zephyr/projects/corsola/interrupts_krabby.dts
+++ b/zephyr/projects/corsola/interrupts_krabby.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/corsola/interrupts_magikarp.dts b/zephyr/projects/corsola/interrupts_magikarp.dts
new file mode 100644
index 0000000000..06458e1063
--- /dev/null
+++ b/zephyr/projects/corsola/interrupts_magikarp.dts
@@ -0,0 +1,105 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	aliases {
+		int-wp = &int_wp;
+	};
+
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_power_button: power_button {
+			irq-pin = <&power_button_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_button_interrupt";
+		};
+		int_volume_up: volume_up {
+			irq-pin = <&volume_up_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+		int_volume_down: volume_down {
+			irq-pin = <&volume_down_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+		int_lid_open: lid_open {
+			irq-pin = <&lid_open>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "lid_interrupt";
+		};
+		int_warm_rst: warm_rst {
+			irq-pin = <&ap_ec_warm_rst_req>;
+			flags = <GPIO_INT_EDGE_RISING>;
+			handler = "chipset_reset_request_interrupt";
+		};
+		int_ap_in_sleep: ap_in_sleep {
+			irq-pin = <&ap_in_sleep_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_ap_in_rst: ap_in_rst {
+			irq-pin = <&ap_sysrst_odl_r>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_ap_wdtrst: ap_wdtrst {
+			irq-pin = <&ap_ec_wdtrst_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "chipset_watchdog_interrupt";
+		};
+		int_tablet_mode: tablet_mode {
+			irq-pin = <&tablet_mode_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "gmr_tablet_switch_isr";
+		};
+		int_base_imu: base_imu {
+			irq-pin = <&base_imu_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "motion_interrupt";
+		};
+		int_lid_imu: lid_imu {
+			irq-pin = <&lid_accel_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "lis2dw12_interrupt";
+		};
+		int_ac_present: ac_present {
+			irq-pin = <&ac_present>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "extpower_interrupt";
+		};
+		int_usba: usba {
+			irq-pin = <&gpio_ap_xhci_init_done>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "usb_a0_interrupt";
+		};
+		int_wp: wp {
+			irq-pin = <&ec_flash_wp_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "switch_interrupt";
+		};
+		int_spi0_cs: spi0_cs {
+			irq-pin = <&spi0_cs>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "spi_event";
+		};
+		int_x_ec_gpio2: x_ec_gpio2 {
+			irq-pin = <&gpio_x_ec_gpio2>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "x_ec_interrupt";
+		};
+		int_usb_c0_ppc_bc12: usb_c0_ppc_bc12 {
+			irq-pin = <&usb_c0_ppc_bc12_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "c0_bc12_interrupt";
+		};
+		int_usb_c1_bc12_charger: usb_c1_bc12_charger {
+			irq-pin = <&usb_c1_bc12_charger_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "rt9490_bc12_dt_interrupt";
+		};
+	};
+};
diff --git a/zephyr/projects/corsola/interrupts_tentacruel.dts b/zephyr/projects/corsola/interrupts_tentacruel.dts
new file mode 100644
index 0000000000..c35461304e
--- /dev/null
+++ b/zephyr/projects/corsola/interrupts_tentacruel.dts
@@ -0,0 +1,110 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	aliases {
+		int-wp = &int_wp;
+	};
+
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_power_button: power_button {
+			irq-pin = <&power_button_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_button_interrupt";
+		};
+		int_volume_up: volume_up {
+			irq-pin = <&volume_up_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+		int_volume_down: volume_down {
+			irq-pin = <&volume_down_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+		int_lid_open: lid_open {
+			irq-pin = <&lid_open>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "lid_interrupt";
+		};
+		int_warm_rst: warm_rst {
+			irq-pin = <&ap_ec_warm_rst_req>;
+			flags = <GPIO_INT_EDGE_RISING>;
+			handler = "chipset_reset_request_interrupt";
+		};
+		int_ap_in_sleep: ap_in_sleep {
+			irq-pin = <&ap_in_sleep_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_ap_in_rst: ap_in_rst {
+			irq-pin = <&ap_sysrst_odl_r>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_signal_interrupt";
+		};
+		int_ap_wdtrst: ap_wdtrst {
+			irq-pin = <&ap_ec_wdtrst_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "chipset_watchdog_interrupt";
+		};
+		int_tablet_mode: tablet_mode {
+			irq-pin = <&tablet_mode_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "gmr_tablet_switch_isr";
+		};
+		int_base_imu: base_imu {
+			irq-pin = <&base_imu_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "motion_interrupt";
+		};
+		int_lid_imu: lid_imu {
+			irq-pin = <&lid_accel_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "lis2dw12_interrupt";
+		};
+		int_ac_present: ac_present {
+			irq-pin = <&ac_present>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "extpower_interrupt";
+		};
+		int_usba: usba {
+			irq-pin = <&gpio_ap_xhci_init_done>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "usb_a0_interrupt";
+		};
+		int_wp: wp {
+			irq-pin = <&ec_flash_wp_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "switch_interrupt";
+		};
+		int_spi0_cs: spi0_cs {
+			irq-pin = <&spi0_cs>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "spi_event";
+		};
+		int_x_ec_gpio2: x_ec_gpio2 {
+			irq-pin = <&gpio_x_ec_gpio2>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "x_ec_interrupt";
+		};
+		int_usb_c0_ppc: usb_c0_ppc {
+			irq-pin = <&usb_c0_ppc_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "ppc_interrupt";
+		};
+		int_usb_c0_bc12: usb_c0_bc12 {
+			irq-pin = <&usb_c0_bc12_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "bc12_interrupt";
+		};
+		int_usb_c1_bc12_charger: usb_c1_bc12_charger {
+			irq-pin = <&usb_c1_bc12_charger_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "rt9490_bc12_dt_interrupt";
+		};
+	};
+};
diff --git a/zephyr/projects/corsola/keyboard_steelix.dts b/zephyr/projects/corsola/keyboard_steelix.dts
new file mode 100644
index 0000000000..9a0dca3e05
--- /dev/null
+++ b/zephyr/projects/corsola/keyboard_steelix.dts
@@ -0,0 +1,29 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	cros-keyscan {
+		compatible = "cros-keyscan";
+
+		debounce-down = <15000>;
+		debounce-up = <15000>;
+
+		actual-key-mask = <
+			0x1c	/* C0 */
+			0xff	/* C1 */
+			0xff	/* C2 */
+			0xff	/* C3 */
+			0xff	/* C4 */
+			0xf5	/* C5 */
+			0xff	/* C6 */
+			0xa4	/* C7 */
+			0xff	/* C8 */
+			0xfe	/* C9 */
+			0x55	/* C10 */
+			0xfa	/* C11 */
+			0xca	/* C12 */
+			>;
+	};
+};
diff --git a/zephyr/projects/corsola/led_it81202_base.dtsi b/zephyr/projects/corsola/led_it81202_base.dtsi
new file mode 100644
index 0000000000..dce7bb4f95
--- /dev/null
+++ b/zephyr/projects/corsola/led_it81202_base.dtsi
@@ -0,0 +1,184 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include <dt-bindings/battery.h>
+
+/ {
+	led_colors: led-colors {
+		compatible = "cros-ec,led-policy";
+
+		bat-power-state-charge {
+			charge-state = "PWR_STATE_CHARGE";
+
+			color-0 {
+				led-color = <&color_battery_amber>;
+			};
+		};
+
+		bat-power-state-near-full {
+			charge-state = "PWR_STATE_CHARGE_NEAR_FULL";
+
+			color-0 {
+				led-color = <&color_battery_white>;
+			};
+		};
+
+		bat-power-state-discharge {
+			charge-state = "PWR_STATE_DISCHARGE";
+
+			color-0 {
+				led-color = <&color_battery_off>;
+			};
+		};
+
+		bat-power-state-discharge-s0-bat-low {
+			charge-state = "PWR_STATE_DISCHARGE";
+			chipset-state = "POWER_S0";
+			batt-lvl = <BATTERY_LEVEL_EMPTY BATTERY_LEVEL_LOW>;
+
+			color-0 {
+				led-color = <&color_battery_amber>;
+				period-ms = <1000>;
+			};
+
+			color-1 {
+				led-color = <&color_battery_off>;
+				period-ms = <3000>;
+			};
+		};
+
+		bat-power-state-error {
+			charge-state = "PWR_STATE_ERROR";
+
+			color-0 {
+				led-color = <&color_battery_amber>;
+				period-ms = <1000>;
+			};
+
+			color-1 {
+				led-color = <&color_battery_off>;
+				period-ms = <1000>;
+			};
+		};
+
+		pwr-power-state-off {
+			color-0 {
+				led-color = <&color_power_off>;
+			};
+		};
+
+		pwr-power-state-on {
+			chipset-state = "POWER_S0";
+
+			color-0 {
+				led-color = <&color_power_white>;
+			};
+		};
+
+		pwr-power-state-s3 {
+			chipset-state = "POWER_S3";
+
+			color-0 {
+				led-color = <&color_power_white>;
+				period-ms = <1000>;
+			};
+
+			color-1 {
+				led-color = <&color_power_off>;
+				period-ms = <3000>;
+			};
+		};
+	};
+
+	pwmleds {
+		compatible = "cros-ec,pwm-pin-config";
+
+		/* NOTE: &pwm number needs same with channel number */
+		led_power_white: ec_led1_odl {
+			#led-pin-cells = <1>;
+			pwms = <&pwm0
+				PWM_CHANNEL_0
+				PWM_HZ(324)
+				PWM_POLARITY_INVERTED>;
+		};
+		led_battery_amber: ec_led2_odl {
+			#led-pin-cells = <1>;
+			pwms = <&pwm1
+				PWM_CHANNEL_1
+				PWM_HZ(324)
+				PWM_POLARITY_INVERTED>;
+		};
+		led_battery_white: ec_led3_odl {
+			#led-pin-cells = <1>;
+			pwms = <&pwm2
+				PWM_CHANNEL_2
+				PWM_HZ(324)
+				PWM_POLARITY_INVERTED>;
+		};
+	};
+
+	pwm-led-pins {
+		compatible = "cros-ec,pwm-led-pins";
+
+		color_power_off: color-power-off {
+			led-color = "LED_OFF";
+			led-id = "EC_LED_ID_POWER_LED";
+			led-pins = <&led_power_white 0>;
+		};
+
+		color_power_white: color-power-white {
+			led-color = "LED_WHITE";
+			br-color = "EC_LED_COLOR_WHITE";
+			led-id = "EC_LED_ID_POWER_LED";
+			led-pins = <&led_power_white 100>;
+		};
+
+		color_battery_off: color-battery-off {
+			led-color = "LED_OFF";
+			led-id = "EC_LED_ID_BATTERY_LED";
+			led-pins = <&led_battery_amber 0>,
+				   <&led_battery_white 0>;
+		};
+
+		color_battery_amber: color-battery-amber {
+			led-color = "LED_AMBER";
+			br-color = "EC_LED_COLOR_AMBER";
+			led-id = "EC_LED_ID_BATTERY_LED";
+			led-pins = <&led_battery_amber 100>,
+				   <&led_battery_white 0>;
+		};
+
+		color_battery_white: color-battery-white {
+			led-color = "LED_WHITE";
+			br-color = "EC_LED_COLOR_WHITE";
+			led-id = "EC_LED_ID_BATTERY_LED";
+			led-pins = <&led_battery_amber 0>,
+				   <&led_battery_white 100>;
+		};
+	};
+};
+
+/* LED1 */
+&pwm0 {
+	status = "okay";
+	prescaler-cx = <PWM_PRESCALER_C4>;
+	pinctrl-0 = <&pwm0_gpa0_default>;
+	pinctrl-names = "default";
+};
+
+/* LED2 */
+&pwm1 {
+	status = "okay";
+	prescaler-cx = <PWM_PRESCALER_C4>;
+	pinctrl-0 = <&pwm1_gpa1_default>;
+	pinctrl-names = "default";
+};
+
+/* LED3 */
+&pwm2 {
+	status = "okay";
+	prescaler-cx = <PWM_PRESCALER_C4>;
+	pinctrl-0 = <&pwm2_gpa2_default>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/projects/corsola/led_kingler.dts b/zephyr/projects/corsola/led_kingler.dts
index 56a54862e6..92f6c4d4fe 100644
--- a/zephyr/projects/corsola/led_kingler.dts
+++ b/zephyr/projects/corsola/led_kingler.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,7 +17,6 @@
 		compatible = "cros-ec,pwm-leds";
 
 		leds = <&pwm_led0>;
-		frequency = <100>;
 
 		color-map-red    = <100   0   0>;
 		color-map-green  = <  0 100   0>;
diff --git a/zephyr/projects/corsola/led_krabby.dts b/zephyr/projects/corsola/led_krabby.dts
index 9ee879b404..b16bff3cac 100644
--- a/zephyr/projects/corsola/led_krabby.dts
+++ b/zephyr/projects/corsola/led_krabby.dts
@@ -1,44 +1,5 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
-
-/ {
-	pwmleds {
-		compatible = "pwm-leds";
-		/* NOTE: &pwm number needs same with channel number */
-		led_power_white: ec_led1_odl {
-			pwms = <&pwm0 PWM_CHANNEL_0 PWM_HZ(324) PWM_POLARITY_INVERTED>;
-		};
-		led_battery_amber: ec_led2_odl {
-			pwms = <&pwm1 PWM_CHANNEL_1 PWM_HZ(324) PWM_POLARITY_INVERTED>;
-		};
-		led_battery_white: ec_led3_odl {
-			pwms = <&pwm2 PWM_CHANNEL_2 PWM_HZ(324) PWM_POLARITY_INVERTED>;
-		};
-	};
-};
-
-/* LED1 */
-&pwm0 {
-	status = "okay";
-	prescaler-cx = <PWM_PRESCALER_C4>;
-	pinctrl-0 = <&pwm0_gpa0_default>;
-	pinctrl-names = "default";
-};
-
-/* LED2 */
-&pwm1 {
-	status = "okay";
-	prescaler-cx = <PWM_PRESCALER_C4>;
-	pinctrl-0 = <&pwm1_gpa1_default>;
-	pinctrl-names = "default";
-};
-
-/* LED3 */
-&pwm2 {
-	status = "okay";
-	prescaler-cx = <PWM_PRESCALER_C4>;
-	pinctrl-0 = <&pwm2_gpa2_default>;
-	pinctrl-names = "default";
-};
+#include "led_it81202_base.dtsi"
diff --git a/zephyr/projects/corsola/led_magikarp.dts b/zephyr/projects/corsola/led_magikarp.dts
new file mode 100644
index 0000000000..0e2b0aca52
--- /dev/null
+++ b/zephyr/projects/corsola/led_magikarp.dts
@@ -0,0 +1,136 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "led_it81202_base.dtsi"
+
+/ {
+	led_colors: led-colors {
+		compatible = "cros-ec,led-policy";
+
+		/* Magikarp LED bat charge */
+		bat-power-state-charge {
+			charge-state = "PWR_STATE_CHARGE";
+			/* Battery percent range (>= Empty, <= 94%) */
+			batt-lvl = <BATTERY_LEVEL_EMPTY
+				   (BATTERY_LEVEL_NEAR_FULL - 3)>;
+			color-0 {
+				led-color = <&color_battery_amber>;
+			};
+		};
+
+		bat-power-state-charge-near-full {
+			charge-state = "PWR_STATE_CHARGE";
+			/* Battery percent range (>= 95%, <= Full) */
+			batt-lvl = <(BATTERY_LEVEL_NEAR_FULL - 2)
+				     BATTERY_LEVEL_FULL>;
+			color-0 {
+				led-color = <&color_battery_white>;
+			};
+		};
+
+		/* Magikarp LED bat discharge */
+		bat-power-state-discharge-s0 {
+			charge-state = "PWR_STATE_DISCHARGE";
+			chipset-state = "POWER_S0";
+			/* Battery percent range (>= 11%, <= Full) */
+			batt-lvl = <(BATTERY_LEVEL_LOW + 1) BATTERY_LEVEL_FULL>;
+
+			color-0 {
+				led-color = <&color_battery_white>;
+			};
+		};
+
+
+		bat-power-state-discharge-s0-bat-low {
+			charge-state = "PWR_STATE_DISCHARGE";
+			chipset-state = "POWER_S0";
+			/* Battery percent range (>= Empty, <= 10%) */
+			batt-lvl = <BATTERY_LEVEL_EMPTY BATTERY_LEVEL_LOW>;
+
+			color-0 {
+				led-color = <&color_battery_amber>;
+				period-ms = <1000>;
+			};
+
+			color-1 {
+				led-color = <&color_battery_off>;
+				period-ms = <3000>;
+			};
+		};
+
+		bat-power-state-discharge-s3 {
+			charge-state = "PWR_STATE_DISCHARGE";
+			chipset-state = "POWER_S3";
+
+			color-0 {
+				led-color = <&color_battery_white>;
+				period-ms = <1000>;
+			};
+
+			color-1 {
+				led-color = <&color_battery_off>;
+				period-ms = <3000>;
+			};
+		};
+
+		bat-power-state-discharge-s5 {
+			charge-state = "PWR_STATE_DISCHARGE";
+			chipset-state = "POWER_S5";
+			color-0 {
+				led-color = <&color_battery_off>;
+			};
+		};
+
+		/* Magikarp LED bat error */
+		bat-power-state-error {
+			charge-state = "PWR_STATE_ERROR";
+			chipset-state = "POWER_S0";
+
+			color-0 {
+				led-color = <&color_battery_amber>;
+				period-ms = <1000>;
+			};
+
+			color-1 {
+				led-color = <&color_battery_off>;
+				period-ms = <1000>;
+			};
+		};
+
+		bat-power-state-error-s3 {
+			charge-state = "PWR_STATE_ERROR";
+			chipset-state = "POWER_S3";
+
+			color-0 {
+				led-color = <&color_battery_white>;
+				period-ms = <1000>;
+			};
+
+			color-1 {
+				led-color = <&color_battery_off>;
+				period-ms = <3000>;
+			};
+		};
+
+		bat-power-state-error-s5 {
+			charge-state = "PWR_STATE_ERROR";
+			chipset-state = "POWER_S5";
+
+			color-0 {
+				led-color = <&color_battery_off>;
+			};
+		};
+	};
+
+	pwm-led-pins {
+		compatible = "cros-ec,pwm-led-pins";
+
+		/* Overwrite Power LED white to off */
+		color_power_white: color-power-white {
+			led-color = "LED_WHITE";
+			led-id = "EC_LED_ID_POWER_LED";
+			led-pins = <&led_power_white 0>;
+		};
+	};
+};
diff --git a/zephyr/projects/corsola/led_steelix.dts b/zephyr/projects/corsola/led_steelix.dts
index 31d17958d4..6a25929327 100644
--- a/zephyr/projects/corsola/led_steelix.dts
+++ b/zephyr/projects/corsola/led_steelix.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/corsola/led_tentacruel.dts b/zephyr/projects/corsola/led_tentacruel.dts
new file mode 100644
index 0000000000..5569a956f6
--- /dev/null
+++ b/zephyr/projects/corsola/led_tentacruel.dts
@@ -0,0 +1,118 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include "led_it81202_base.dtsi"
+
+/ {
+	led_colors: led-colors {
+		compatible = "cros-ec,led-policy";
+
+		/* Tentacruel LED bat charge */
+		bat-power-state-charge {
+			charge-state = "PWR_STATE_CHARGE";
+			/* Battery percent range (>= Empty, <= 94%) */
+			batt-lvl = <BATTERY_LEVEL_EMPTY
+				   (BATTERY_LEVEL_NEAR_FULL - 3)>;
+			color-0 {
+				led-color = <&color_battery_amber>;
+			};
+		};
+
+		bat-power-state-charge-near-full {
+			charge-state = "PWR_STATE_CHARGE";
+			/* Battery percent range (>= 95%, <= Full) */
+			batt-lvl = <(BATTERY_LEVEL_NEAR_FULL - 2)
+				     BATTERY_LEVEL_FULL>;
+			color-0 {
+				led-color = <&color_battery_white>;
+			};
+		};
+
+		/* Tentacruel LED bat discharge */
+		bat-power-state-discharge {
+			charge-state = "PWR_STATE_DISCHARGE";
+			chipset-state = "POWER_S0";
+			/* Battery percent range (>= 11%, <= Full) */
+			batt-lvl = <(BATTERY_LEVEL_LOW + 1) BATTERY_LEVEL_FULL>;
+
+			color-0 {
+				led-color = <&color_battery_white>;
+			};
+		};
+
+		bat-power-state-discharge-s3 {
+			charge-state = "PWR_STATE_DISCHARGE";
+			chipset-state = "POWER_S3";
+
+			color-0 {
+				led-color = <&color_battery_white>;
+				period-ms = <1000>;
+			};
+
+			color-1 {
+				led-color = <&color_battery_off>;
+				period-ms = <3000>;
+			};
+		};
+
+		bat-power-state-discharge-s5 {
+			charge-state = "PWR_STATE_DISCHARGE";
+			chipset-state = "POWER_S5";
+			color-0 {
+				led-color = <&color_battery_off>;
+			};
+		};
+
+		/* Tentacruel LED bat error */
+		bat-power-state-error {
+			charge-state = "PWR_STATE_ERROR";
+			chipset-state = "POWER_S0";
+
+			color-0 {
+				led-color = <&color_battery_amber>;
+				period-ms = <1000>;
+			};
+
+			color-1 {
+				led-color = <&color_battery_off>;
+				period-ms = <1000>;
+			};
+		};
+
+		bat-power-state-error-s3 {
+			charge-state = "PWR_STATE_ERROR";
+			chipset-state = "POWER_S3";
+
+			color-0 {
+				led-color = <&color_battery_white>;
+				period-ms = <1000>;
+			};
+
+			color-1 {
+				led-color = <&color_battery_off>;
+				period-ms = <3000>;
+			};
+		};
+
+		bat-power-state-error-s5 {
+			charge-state = "PWR_STATE_ERROR";
+			chipset-state = "POWER_S5";
+
+			color-0 {
+				led-color = <&color_battery_off>;
+			};
+		};
+	};
+
+	pwm-led-pins {
+		compatible = "cros-ec,pwm-led-pins";
+
+		/* Overwrite Power LED white to off */
+		color_power_white: color-power-white {
+			led-color = "LED_WHITE";
+			led-id = "EC_LED_ID_POWER_LED";
+			led-pins = <&led_power_white 0>;
+		};
+	};
+};
diff --git a/zephyr/projects/corsola/motionsense_kingler.dts b/zephyr/projects/corsola/motionsense_kingler.dts
index 4667635da0..a7f674e01f 100644
--- a/zephyr/projects/corsola/motionsense_kingler.dts
+++ b/zephyr/projects/corsola/motionsense_kingler.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -29,10 +29,8 @@
 	motionsense-mutex {
 		compatible = "cros-ec,motionsense-mutex";
 		lid_mutex: lid-mutex {
-			label = "LID_MUTEX";
 		};
 		base_mutex: base-mutex {
-			label = "BASE_MUTEX";
 		};
 	};
 
@@ -73,7 +71,7 @@
 
 	/*
 	 * List of motion sensors that creates motion_sensors array.
-	 * The label "lid_accel" and "base_accel" are used to indicate
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
 	 * motion sensor IDs for lid angle calculation.
 	 */
 	motionsense-sensor {
@@ -81,7 +79,6 @@
 			compatible = "cros-ec,bma4xx";
 			status = "okay";
 
-			label = "Lid Accel";
 			active-mask = "SENSOR_ACTIVE_S0_S3";
 			location = "MOTIONSENSE_LOC_LID";
 			mutex = <&lid_mutex>;
@@ -93,11 +90,9 @@
 				compatible =
 					"cros-ec,motionsense-sensor-config";
 				ec-s0 {
-					label = "SENSOR_CONFIG_EC_S0";
 					odr = <(12500 | ROUND_UP_FLAG)>;
 				};
 				ec-s3 {
-					label = "SENSOR_CONFIG_EC_S3";
 					odr = <(12500 | ROUND_UP_FLAG)>;
 				};
 			};
@@ -107,7 +102,6 @@
 			compatible = "cros-ec,bmi3xx-accel";
 			status = "okay";
 
-			label = "Base Accel";
 			active-mask = "SENSOR_ACTIVE_S0_S3";
 			location = "MOTIONSENSE_LOC_BASE";
 			mutex = <&base_mutex>;
@@ -118,12 +112,10 @@
 				compatible =
 					"cros-ec,motionsense-sensor-config";
 				ec-s0 {
-					label = "SENSOR_CONFIG_EC_S0";
 					odr = <(12500 | ROUND_UP_FLAG)>;
 					ec-rate = <(100 * USEC_PER_MSEC)>;
 				};
 				ec-s3 {
-					label = "SENSOR_CONFIG_EC_S3";
 					odr = <(12500 | ROUND_UP_FLAG)>;
 					ec-rate = <0>;
 				};
@@ -134,7 +126,6 @@
 			compatible = "cros-ec,bmi3xx-gyro";
 			status = "okay";
 
-			label = "Base Gyro";
 			active-mask = "SENSOR_ACTIVE_S0_S3";
 			location = "MOTIONSENSE_LOC_BASE";
 			mutex = <&base_mutex>;
diff --git a/zephyr/projects/corsola/motionsense_krabby.dts b/zephyr/projects/corsola/motionsense_krabby.dts
index d369db460a..1c7d5b2df4 100644
--- a/zephyr/projects/corsola/motionsense_krabby.dts
+++ b/zephyr/projects/corsola/motionsense_krabby.dts
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,11 +27,9 @@
 	motionsense-mutex {
 		compatible = "cros-ec,motionsense-mutex";
 		lid_mutex: lid-mutex {
-			label = "LID_MUTEX";
 		};
 
 		base_mutex: icm42607-mutex {
-			label = "ICM42607_MUTEX";
 		};
 	};
 
@@ -74,7 +72,7 @@
 
 	/*
 	 * List of motion sensors that creates motion_sensors array.
-	 * The label "lid_accel" and "base_accel" are used to indicate
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
 	 * motion sensor IDs for lid angle calculation.
 	 */
 	motionsense-sensor {
@@ -82,7 +80,6 @@
 			compatible = "cros-ec,lis2dw12";
 			status = "okay";
 
-			label = "Lid Accel";
 			active-mask = "SENSOR_ACTIVE_S0_S3";
 			location = "MOTIONSENSE_LOC_LID";
 			mutex = <&lid_mutex>;
@@ -94,11 +91,9 @@
 				compatible =
 					"cros-ec,motionsense-sensor-config";
 				ec-s0 {
-					label = "SENSOR_CONFIG_EC_S0";
 					odr = <(10000 | ROUND_UP_FLAG)>;
 				};
 				ec-s3 {
-					label = "SENSOR_CONFIG_EC_S3";
 					odr = <(10000 | ROUND_UP_FLAG)>;
 				};
 			};
@@ -108,7 +103,6 @@
 			compatible = "cros-ec,icm42607-accel";
 			status = "okay";
 
-			label = "Base Accel";
 			active-mask = "SENSOR_ACTIVE_S0_S3";
 			location = "MOTIONSENSE_LOC_BASE";
 			mutex = <&base_mutex>;
@@ -119,11 +113,9 @@
 				compatible =
 					"cros-ec,motionsense-sensor-config";
 				ec-s0 {
-					label = "SENSOR_CONFIG_EC_S0";
 					odr = <(10000 | ROUND_UP_FLAG)>;
 				};
 				ec-s3 {
-					label = "SENSOR_CONFIG_EC_S3";
 					odr = <(10000 | ROUND_UP_FLAG)>;
 				};
 			};
@@ -133,7 +125,6 @@
 			compatible = "cros-ec,icm42607-gyro";
 			status = "okay";
 
-			label = "Base Gyro";
 			active-mask = "SENSOR_ACTIVE_S0_S3";
 			location = "MOTIONSENSE_LOC_BASE";
 			mutex = <&base_mutex>;
diff --git a/zephyr/projects/corsola/motionsense_magikarp.dts b/zephyr/projects/corsola/motionsense_magikarp.dts
new file mode 100644
index 0000000000..92e73bd2c6
--- /dev/null
+++ b/zephyr/projects/corsola/motionsense_magikarp.dts
@@ -0,0 +1,199 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/motionsense/utils.h>
+
+
+/ {
+	aliases {
+		/*
+		 * motion sense's <>_INT_EVENT is handled
+		 * by alias. Using the alias, each driver creates
+		 * its own <>_INT_EVENT.
+		 */
+		icm42607-int = &base_accel;
+		lis2dw12-int = &lid_accel;
+		bmi3xx-int = &base_accel;
+	};
+
+	/*
+	 * Declare mutexes used by sensor drivers.
+	 * A mutex node is used to create an instance of mutex_t.
+	 * A mutex node is referenced by a sensor node if the
+	 * corresponding sensor driver needs to use the
+	 * instance of the mutex.
+	 */
+	motionsense-mutex {
+		compatible = "cros-ec,motionsense-mutex";
+		lid_mutex: lid-mutex {
+		};
+
+		base_mutex: icm42607-mutex {
+		};
+
+		base_mutex_bmi323: bmi323-mutex {
+		};
+	};
+
+	/* Rotation matrix used by drivers. */
+	motionsense-rotation-ref {
+		compatible = "cros-ec,motionsense-rotation-ref";
+		lid_rot_ref: lid-rotation-ref {
+			mat33 = <1 0 0
+				 0 1 0
+				 0 0 (-1)>;
+		};
+
+		base_rot_ref: base-rotation-ref {
+			mat33 = <1 0 0
+				 0 1 0
+				 0 0 1>;
+		};
+
+		base_rot_ref_bmi: base-rotation-ref-bmi {
+			mat33 = <0 1 0
+				 (-1) 0 0
+				 0 0 1>;
+		};
+	};
+
+	/*
+	 * Driver specific data. A driver-specific data can be shared with
+	 * different motion sensors while they are using the same driver.
+	 *
+	 * If a node's compatible starts with "cros-ec,accelgyro-", it is for
+	 * a common structure defined in accelgyro.h.
+	 * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for
+	 * "struct als_drv_data_t" in accelgyro.h
+	 */
+	motionsense-sensor-data {
+		icm42607_data: icm42607-drv-data {
+			compatible = "cros-ec,drvdata-icm42607";
+			status = "okay";
+		};
+
+		lis2dw12_data: lis2dw12-drv-data {
+			compatible = "cros-ec,drvdata-lis2dw12";
+			status = "okay";
+		};
+
+		bmi323_data: bmi323-drv-data {
+			compatible = "cros-ec,drvdata-bmi3xx";
+			status = "okay";
+		};
+	};
+
+	/*
+	 * List of motion sensors that creates motion_sensors array.
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
+	 * motion sensor IDs for lid angle calculation.
+	 */
+	motionsense-sensor {
+		lid_accel: lid-accel {
+			compatible = "cros-ec,lis2dw12";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&lid_mutex>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&lid_rot_ref>;
+			default-range = <2>;
+			drv-data = <&lis2dw12_data>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_accel: base-accel {
+			compatible = "cros-ec,icm42607-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&icm42607_data>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_gyro: base-gyro {
+			compatible = "cros-ec,icm42607-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&icm42607_data>;
+		};
+	};
+
+	motionsense-sensor-alt {
+		alt_base_accel: alt-base-accel {
+			compatible = "cros-ec,bmi3xx-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex_bmi323>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref_bmi>;
+			drv-data = <&bmi323_data>;
+			alternate-for = <&base_accel>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		alt_base_gyro: alt-base-gyro {
+			compatible = "cros-ec,bmi3xx-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex_bmi323>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref_bmi>;
+			drv-data = <&bmi323_data>;
+			alternate-for = <&base_gyro>;
+		};
+	};
+
+	motionsense-sensor-info {
+		compatible = "cros-ec,motionsense-sensor-info";
+
+		/*
+		 * list of GPIO interrupts that have to
+		 * be enabled at initial stage
+		 */
+		sensor-irqs = <&int_base_imu &int_lid_imu>;
+	};
+};
diff --git a/zephyr/projects/corsola/motionsense_steelix.dts b/zephyr/projects/corsola/motionsense_steelix.dts
index 70aa3679fb..c8cbc95e48 100644
--- a/zephyr/projects/corsola/motionsense_steelix.dts
+++ b/zephyr/projects/corsola/motionsense_steelix.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/corsola/motionsense_tentacruel.dts b/zephyr/projects/corsola/motionsense_tentacruel.dts
new file mode 100644
index 0000000000..68b2c023df
--- /dev/null
+++ b/zephyr/projects/corsola/motionsense_tentacruel.dts
@@ -0,0 +1,199 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/motionsense/utils.h>
+
+
+/ {
+	aliases {
+		/*
+		 * motion sense's <>_INT_EVENT is handled
+		 * by alias. Using the alias, each driver creates
+		 * its own <>_INT_EVENT.
+		 */
+		icm42607-int = &base_accel;
+		lis2dw12-int = &lid_accel;
+		bmi3xx-int = &base_accel;
+	};
+
+	/*
+	 * Declare mutexes used by sensor drivers.
+	 * A mutex node is used to create an instance of mutex_t.
+	 * A mutex node is referenced by a sensor node if the
+	 * corresponding sensor driver needs to use the
+	 * instance of the mutex.
+	 */
+	motionsense-mutex {
+		compatible = "cros-ec,motionsense-mutex";
+		lid_mutex: lid-mutex {
+		};
+
+		base_mutex: icm42607-mutex {
+		};
+
+		base_mutex_bmi323: bmi323-mutex {
+		};
+	};
+
+	/* Rotation matrix used by drivers. */
+	motionsense-rotation-ref {
+		compatible = "cros-ec,motionsense-rotation-ref";
+		lid_rot_ref: lid-rotation-ref {
+			mat33 = <1 0 0
+				 0 1 0
+				 0 0 1>;
+		};
+
+		base_rot_ref: base-rotation-ref {
+			mat33 = <1 0 0
+				 0 1 0
+				 0 0 1>;
+		};
+
+		base_rot_ref_bmi: base-rotation-ref-bmi {
+			mat33 = <0 1 0
+				 (-1) 0 0
+				 0 0 1>;
+		};
+	};
+
+	/*
+	 * Driver specific data. A driver-specific data can be shared with
+	 * different motion sensors while they are using the same driver.
+	 *
+	 * If a node's compatible starts with "cros-ec,accelgyro-", it is for
+	 * a common structure defined in accelgyro.h.
+	 * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for
+	 * "struct als_drv_data_t" in accelgyro.h
+	 */
+	motionsense-sensor-data {
+		icm42607_data: icm42607-drv-data {
+			compatible = "cros-ec,drvdata-icm42607";
+			status = "okay";
+		};
+
+		lis2dw12_data: lis2dw12-drv-data {
+			compatible = "cros-ec,drvdata-lis2dw12";
+			status = "okay";
+		};
+
+		bmi323_data: bmi323-drv-data {
+			compatible = "cros-ec,drvdata-bmi3xx";
+			status = "okay";
+		};
+	};
+
+	/*
+	 * List of motion sensors that creates motion_sensors array.
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
+	 * motion sensor IDs for lid angle calculation.
+	 */
+	motionsense-sensor {
+		lid_accel: lid-accel {
+			compatible = "cros-ec,lis2dw12";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&lid_mutex>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&lid_rot_ref>;
+			default-range = <2>;
+			drv-data = <&lis2dw12_data>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_accel: base-accel {
+			compatible = "cros-ec,icm42607-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&icm42607_data>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_gyro: base-gyro {
+			compatible = "cros-ec,icm42607-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&icm42607_data>;
+		};
+	};
+
+	motionsense-sensor-alt {
+		alt_base_accel: alt-base-accel {
+			compatible = "cros-ec,bmi3xx-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex_bmi323>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref_bmi>;
+			drv-data = <&bmi323_data>;
+			alternate-for = <&base_accel>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		alt_base_gyro: alt-base-gyro {
+			compatible = "cros-ec,bmi3xx-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex_bmi323>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref_bmi>;
+			drv-data = <&bmi323_data>;
+			alternate-for = <&base_gyro>;
+		};
+	};
+
+	motionsense-sensor-info {
+		compatible = "cros-ec,motionsense-sensor-info";
+
+		/*
+		 * list of GPIO interrupts that have to
+		 * be enabled at initial stage
+		 */
+		sensor-irqs = <&int_base_imu &int_lid_imu>;
+	};
+};
diff --git a/zephyr/projects/corsola/npcx_keyboard.dts b/zephyr/projects/corsola/npcx_keyboard.dts
index d3fd354b8f..f9e46de1f2 100644
--- a/zephyr/projects/corsola/npcx_keyboard.dts
+++ b/zephyr/projects/corsola/npcx_keyboard.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/corsola/power_signal.dts b/zephyr/projects/corsola/power_signal.dts
index 2603a53bb4..181d7cf96e 100644
--- a/zephyr/projects/corsola/power_signal.dts
+++ b/zephyr/projects/corsola/power_signal.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/corsola/prj.conf b/zephyr/projects/corsola/prj.conf
index b26c01461e..110b91bbbb 100644
--- a/zephyr/projects/corsola/prj.conf
+++ b/zephyr/projects/corsola/prj.conf
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 #
@@ -6,6 +6,33 @@
 # http://google3/hardware/standards/usb/
 CONFIG_PLATFORM_EC_USB_PID=0x505C
 
+# CROS EC
+CONFIG_CROS_EC=y
+CONFIG_PLATFORM_EC=y
+CONFIG_PLATFORM_EC_SWITCH=y
+CONFIG_SHIMMED_TASKS=y
+
+# AP SoC configuration
+CONFIG_AP=y
+CONFIG_AP_ARM_MTK_MT8186=y
+
+# Variant config
+CONFIG_VARIANT_CORSOLA_DB_DETECTION=y
+
+# Shell features
+CONFIG_KERNEL_SHELL=y
+CONFIG_SHELL_HELP=y
+CONFIG_SHELL_HISTORY=y
+CONFIG_SHELL_TAB=y
+CONFIG_SHELL_TAB_AUTOCOMPLETION=y
+
+# CBI
+CONFIG_EEPROM=y
+CONFIG_EEPROM_AT24=y
+CONFIG_EEPROM_SHELL=n
+CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=y
+CONFIG_PLATFORM_EC_CBI_EEPROM=y
+
 # I2C
 CONFIG_I2C=y
 
@@ -24,14 +51,51 @@ CONFIG_PLATFORM_EC_VBOOT_EFS2=y
 
 # USB
 CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=n
+CONFIG_PLATFORM_EC_USB_PD_USB32_DRD=n
 CONFIG_PLATFORM_EC_USB_PD_USB4=n
-# TODO(b/226411332): fix single task USB_CHG for Corsola
-CONFIG_PLATFORM_EC_USB_CHARGER_SINGLE_TASK=n
+CONFIG_PLATFORM_EC_USB_PORT_POWER_DUMB_CUSTOM_HOOK=y
+
+# USB-C
+CONFIG_PLATFORM_EC_USBC=y
+CONFIG_PLATFORM_EC_USBC_SS_MUX_DFP_ONLY=y
+CONFIG_PLATFORM_EC_USB_PD_DPS=y
+CONFIG_PLATFORM_EC_USB_PD_DP_HPD_GPIO=y
+CONFIG_PLATFORM_EC_USB_PD_DP_HPD_GPIO_CUSTOM=y
+CONFIG_PLATFORM_EC_USB_PD_FRS=y
 
 # Power Seq
 CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK=y
+CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y
+CONFIG_PLATFORM_EC_POWERSEQ=y
 CONFIG_PLATFORM_EC_POWERSEQ_HOST_SLEEP=y
+CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n
 CONFIG_PLATFORM_EC_POWER_SLEEP_FAILURE_DETECTION=y
 
 # Optional features
 CONFIG_FLASH_SHELL=n
+
+# EEPROM
+CONFIG_PLATFORM_EC_EEPROM_CBI_WP=y
+
+# Host Commands
+CONFIG_PLATFORM_EC_HOSTCMD=y
+
+# Battery
+CONFIG_PLATFORM_EC_BATTERY=y
+CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y
+CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y
+CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO=y
+CONFIG_PLATFORM_EC_BATTERY_SMART=y
+CONFIG_PLATFORM_EC_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV=9000
+CONFIG_PLATFORM_EC_I2C_PASSTHRU_RESTRICTED=y
+CONFIG_PLATFORM_EC_I2C_VIRTUAL_BATTERY=y
+
+# Charger
+CONFIG_PLATFORM_EC_BC12_CLIENT_MODE_ONLY_PI3USB9201=y
+CONFIG_PLATFORM_EC_CHARGER=y
+CONFIG_PLATFORM_EC_CHARGE_MANAGER=y
+
+# Button
+CONFIG_PLATFORM_EC_CMD_BUTTON=y
+CONFIG_PLATFORM_EC_POWER_BUTTON=y
+CONFIG_PLATFORM_EC_VOLUME_BUTTONS=y
diff --git a/zephyr/projects/corsola/prj_it81202_base.conf b/zephyr/projects/corsola/prj_it81202_base.conf
new file mode 100644
index 0000000000..38e0acd7a8
--- /dev/null
+++ b/zephyr/projects/corsola/prj_it81202_base.conf
@@ -0,0 +1,92 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Bring up options
+CONFIG_SHELL_HISTORY_BUFFER=256
+CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y
+CONFIG_PLATFORM_EC_BRINGUP=y
+
+# Power Sequencing
+CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK=y
+
+# Lid Switch
+CONFIG_PLATFORM_EC_LID_SWITCH=y
+
+# Charger
+CONFIG_PLATFORM_EC_CHARGE_RAMP_HW=y
+CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y
+CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC_CHARGER=y
+CONFIG_PLATFORM_EC_CHARGER_RT9490=y
+CONFIG_PLATFORM_EC_CHARGER_MAINTAIN_VBAT=y
+CONFIG_PLATFORM_EC_CHARGER_OTG=y
+CONFIG_PLATFORM_EC_CHARGER_PSYS=y
+CONFIG_PLATFORM_EC_CHARGER_PSYS_READ=y
+# BOARD_RS2
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10
+# BOARD_RS1
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=20
+CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_DUMP=y
+
+# Host Commands
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_ADC_AMON_BMON=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_SYSINFO=y
+CONFIG_PLATFORM_EC_HOST_COMMAND_STATUS=y
+
+# LED
+CONFIG_PLATFORM_EC_LED_DT=y
+
+# PWM
+CONFIG_PWM=y
+CONFIG_PWM_SHELL=n
+
+# Sensors
+CONFIG_PLATFORM_EC_MOTIONSENSE=y
+CONFIG_PLATFORM_EC_ACCEL_FIFO=y
+CONFIG_PLATFORM_EC_GMR_TABLET_MODE=y
+CONFIG_PLATFORM_EC_LID_ANGLE=y
+CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y
+CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=y
+CONFIG_PLATFORM_EC_TABLET_MODE=y
+CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=y
+CONFIG_PLATFORM_EC_MAX_SENSOR_FREQ_MILLIHZ=100000
+
+# Sensor Drivers
+CONFIG_PLATFORM_EC_ACCEL_LIS2DW12=y
+CONFIG_PLATFORM_EC_ACCELGYRO_ICM42607=y
+CONFIG_PLATFORM_EC_ACCELGYRO_ICM_COMM_I2C=y
+
+# Tasks
+CONFIG_TASK_CHARGER_STACK_SIZE=1024
+CONFIG_TASK_CHIPSET_STACK_SIZE=1440
+CONFIG_TASK_MOTIONSENSE_STACK_SIZE=1024
+CONFIG_TASK_PD_STACK_SIZE=1280
+
+# USB-A
+CONFIG_PLATFORM_EC_USBA=y
+
+# USB-C
+CONFIG_PLATFORM_EC_BC12_SINGLE_DRIVER=n
+CONFIG_PLATFORM_EC_SMBUS_PEC=y
+CONFIG_PLATFORM_EC_USBC_PPC_DEDICATED_INT=y
+CONFIG_PLATFORM_EC_USBC_PPC_RT1739=y
+CONFIG_PLATFORM_EC_USBC_PPC_SYV682C=y
+CONFIG_PLATFORM_EC_USBC_PPC_SYV682X=y
+CONFIG_PLATFORM_EC_USB_MUX_IT5205=y
+CONFIG_PLATFORM_EC_USB_MUX_TUSB546=y
+CONFIG_PLATFORM_EC_USB_MUX_VIRTUAL=y
+CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y
+CONFIG_PLATFORM_EC_USB_PD_FRS_PPC=y
+CONFIG_PLATFORM_EC_USB_PD_LOGGING=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_DRIVER_IT8XXX2=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_ITE_ON_CHIP=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_TCPCI=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_PPC=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_ADC_EACH_PORT=y
+CONFIG_PLATFORM_EC_USB_PD_DUAL_ROLE_AUTO_TOGGLE=n
+
+# TODO(b/180980668): bring these features up
+CONFIG_LTO=n
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
diff --git a/zephyr/projects/corsola/prj_kingler.conf b/zephyr/projects/corsola/prj_kingler.conf
index 525d94a886..d7de991e93 100644
--- a/zephyr/projects/corsola/prj_kingler.conf
+++ b/zephyr/projects/corsola/prj_kingler.conf
@@ -1,139 +1,12 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
-# Cros EC
-CONFIG_CROS_EC=y
-CONFIG_PLATFORM_EC=y
-CONFIG_PLATFORM_EC_BRINGUP=y
-CONFIG_SHIMMED_TASKS=y
-CONFIG_PLATFORM_EC_SWITCH=y
-
 # Variant config
 CONFIG_BOARD_KINGLER=y
-CONFIG_VARIANT_CORSOLA_DB_DETECTION=y
-
-# Shell features
-CONFIG_KERNEL_SHELL=y
-CONFIG_SHELL_HELP=y
-CONFIG_SHELL_TAB=y
-CONFIG_SHELL_TAB_AUTOCOMPLETION=y
-CONFIG_SHELL_HISTORY=y
-
-# Bring up options
-CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y
-
-# ADC
-CONFIG_ADC=y
-CONFIG_PLATFORM_EC_ADC=y
-
-# Battery
-CONFIG_PLATFORM_EC_BATTERY=y
-CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y
-CONFIG_PLATFORM_EC_BATTERY_SMART=y
-CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y
-CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO=y
-CONFIG_PLATFORM_EC_I2C_PASSTHRU_RESTRICTED=y
-CONFIG_PLATFORM_EC_I2C_VIRTUAL_BATTERY=y
-
-# CBI
-CONFIG_EEPROM=y
-CONFIG_EEPROM_AT24=y
-CONFIG_EEPROM_SHELL=n
-CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=y
-CONFIG_PLATFORM_EC_CBI_EEPROM=y
-
-# Charger
-CONFIG_PLATFORM_EC_CHARGER=y
-CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y
-CONFIG_PLATFORM_EC_CHARGER_ISL9238C=y
-CONFIG_PLATFORM_EC_CHARGER_PSYS=y
-CONFIG_PLATFORM_EC_CHARGER_PSYS_READ=y
-CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10
-CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=20
-CONFIG_PLATFORM_EC_CHARGE_MANAGER=y
-CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_ADC_AMON_BMON=y
-CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y
-
-# Host command
-CONFIG_PLATFORM_EC_HOSTCMD=y
-
-# PWM
-CONFIG_PWM=y
-CONFIG_PWM_SHELL=n
 
 # LED
-CONFIG_PLATFORM_EC_LED_COMMON=y
-CONFIG_PLATFORM_EC_LED_ONOFF_STATES=y
 CONFIG_PLATFORM_EC_LED_PWM=y
 
-# Math
-CONFIG_PLATFORM_EC_MATH_UTIL=y
-
-# Power sequencing
-CONFIG_AP=y
-CONFIG_AP_ARM_MTK_MT8186=y
-CONFIG_PLATFORM_EC_POWERSEQ_MT8186=y
-CONFIG_PLATFORM_EC_POWERSEQ=y
-CONFIG_PLATFORM_EC_POWERSEQ_S4=n
-CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n
-
-# Button
-CONFIG_PLATFORM_EC_POWER_BUTTON=y
-CONFIG_PLATFORM_EC_VOLUME_BUTTONS=y
-CONFIG_PLATFORM_EC_BUTTONS_RUNTIME_CONFIG=y
-
-# Sensors
-CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y
-CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y
-CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y
-CONFIG_PLATFORM_EC_ACCEL_FIFO=y
-CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=y
-CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=y
-CONFIG_PLATFORM_EC_GMR_TABLET_MODE=y
-CONFIG_PLATFORM_EC_LID_ANGLE=y
-CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y
-CONFIG_PLATFORM_EC_LID_SWITCH=y
-CONFIG_PLATFORM_EC_MOTIONSENSE=y
-CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=y
-CONFIG_PLATFORM_EC_TABLET_MODE=y
-CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=y
-
-# USBA
-CONFIG_PLATFORM_EC_USBA=y
-
-# USBC
-CONFIG_PLATFORM_EC_BC12_DETECT_PI3USB9201=y
-CONFIG_PLATFORM_EC_BC12_SINGLE_DRIVER=n
-CONFIG_PLATFORM_EC_USBC=y
-CONFIG_PLATFORM_EC_USBC_PPC=y
-CONFIG_PLATFORM_EC_USBC_PPC_NX20P3483=y
-CONFIG_PLATFORM_EC_USBC_PPC_RT1718S=y
-CONFIG_PLATFORM_EC_USBC_SS_MUX_DFP_ONLY=y
-CONFIG_PLATFORM_EC_USB_MUX_PS8743=y
-CONFIG_PLATFORM_EC_USB_MUX_VIRTUAL=y
-CONFIG_PLATFORM_EC_USB_PD_DP_HPD_GPIO=y
-CONFIG_PLATFORM_EC_USB_PD_DP_HPD_GPIO_CUSTOM=y
-CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y
-CONFIG_PLATFORM_EC_USB_PD_FRS=y
-CONFIG_PLATFORM_EC_USB_PD_FRS_TCPC=y
-CONFIG_PLATFORM_EC_USB_PD_LOGGING=y
-CONFIG_PLATFORM_EC_USB_PD_DEBUG_FIXED_LEVEL=y
-CONFIG_PLATFORM_EC_USB_PD_DEBUG_LEVEL=2
-CONFIG_PLATFORM_EC_USB_PD_TCPM_ANX7447=y
-CONFIG_PLATFORM_EC_USB_PD_TCPM_RT1718S=y
-CONFIG_PLATFORM_EC_USB_PD_TCPM_SBU=y
-CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y
-CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_BY_BOARD=y
-
-# External power
-CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
-CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y
-
 # Keyboard
-CONFIG_CROS_KB_RAW_NPCX=y
-CONFIG_CROS_KB_RAW_NPCX_KSO_HIGH_DRIVE=y
-
-CONFIG_SYSCON=y
-
-CONFIG_PLATFORM_EC_BOARD_VERSION_GPIO=n
+CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI2=y
diff --git a/zephyr/projects/corsola/prj_krabby.conf b/zephyr/projects/corsola/prj_krabby.conf
index 741f07b436..c4cde05c16 100644
--- a/zephyr/projects/corsola/prj_krabby.conf
+++ b/zephyr/projects/corsola/prj_krabby.conf
@@ -1,140 +1,9 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
-CONFIG_CROS_EC=y
-CONFIG_PLATFORM_EC=y
-CONFIG_SHIMMED_TASKS=y
-
+# Variant config
 CONFIG_BOARD_KRABBY=y
 
-# AP SoC configuration
-CONFIG_AP=y
-CONFIG_AP_ARM_MTK_MT8186=y
-
-# Bring up options
-CONFIG_KERNEL_SHELL=y
-CONFIG_SHELL_HISTORY_BUFFER=256
-CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y
-CONFIG_PLATFORM_EC_BRINGUP=y
-
-# VARIANT config
-CONFIG_VARIANT_CORSOLA_DB_DETECTION=y
-
-# CBI
-CONFIG_EEPROM=y
-CONFIG_EEPROM_AT24=y
-CONFIG_EEPROM_SHELL=n
-CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=y
-CONFIG_PLATFORM_EC_CBI_EEPROM=y
-
-# Power Sequencing
-CONFIG_PLATFORM_EC_POWERSEQ=y
-CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n
-CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y
-CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK=y
-
-# Lid Switch
-CONFIG_PLATFORM_EC_LID_SWITCH=y
-
-# Battery
-CONFIG_PLATFORM_EC_BATTERY=y
-CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y
-CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y
-CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO=y
-CONFIG_PLATFORM_EC_BATTERY_SMART=y
-CONFIG_PLATFORM_EC_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV=9000
-CONFIG_PLATFORM_EC_I2C_PASSTHRU_RESTRICTED=y
-CONFIG_PLATFORM_EC_I2C_VIRTUAL_BATTERY=y
-
-# Charger
-CONFIG_PLATFORM_EC_CHARGER=y
-CONFIG_PLATFORM_EC_CHARGE_MANAGER=y
-CONFIG_PLATFORM_EC_CHARGE_RAMP_HW=y
-CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y
-CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC_CHARGER=y
-CONFIG_PLATFORM_EC_CHARGER_RT9490=y
-CONFIG_PLATFORM_EC_CHARGER_MAINTAIN_VBAT=y
-CONFIG_PLATFORM_EC_CHARGER_OTG=y
-CONFIG_PLATFORM_EC_CHARGER_PSYS=y
-CONFIG_PLATFORM_EC_CHARGER_PSYS_READ=y
-# BOARD_RS2
-CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10
-# BOARD_RS1
-CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=20
-CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_DUMP=y
-
-# Host Commands
-CONFIG_PLATFORM_EC_HOSTCMD=y
-CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=y
-CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=y
-CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_ADC_AMON_BMON=y
-CONFIG_PLATFORM_EC_CONSOLE_CMD_SYSINFO=y
-CONFIG_PLATFORM_EC_HOST_COMMAND_STATUS=y
-
-# LED
-CONFIG_PLATFORM_EC_LED_COMMON=y
-CONFIG_PLATFORM_EC_LED_ONOFF_STATES=y
-CONFIG_PLATFORM_EC_LED_ONOFF_STATES_BAT_LOW=10
-
 # Keyboard
-CONFIG_PLATFORM_EC_VOLUME_BUTTONS=y
-CONFIG_PLATFORM_EC_CMD_BUTTON=y
-
-# Sensors
-CONFIG_PLATFORM_EC_MOTIONSENSE=y
-CONFIG_PLATFORM_EC_ACCEL_FIFO=y
-CONFIG_PLATFORM_EC_GMR_TABLET_MODE=y
-CONFIG_PLATFORM_EC_LID_ANGLE=y
-CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y
-CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=y
-CONFIG_PLATFORM_EC_SWITCH=y
-CONFIG_PLATFORM_EC_TABLET_MODE=y
-CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=y
-
-# Sensor Drivers
-CONFIG_PLATFORM_EC_ACCEL_LIS2DW12=y
-CONFIG_PLATFORM_EC_ACCELGYRO_ICM42607=y
-CONFIG_PLATFORM_EC_ACCELGYRO_ICM_COMM_I2C=y
-
-# Tasks
-CONFIG_TASK_CHARGER_STACK_SIZE=1024
-CONFIG_TASK_CHIPSET_STACK_SIZE=1440
-CONFIG_TASK_MOTIONSENSE_STACK_SIZE=1024
-CONFIG_TASK_PD_STACK_SIZE=1280
-
-# USB-A
-CONFIG_PLATFORM_EC_USBA=y
-
-# USB-C
-CONFIG_PLATFORM_EC_BC12_SINGLE_DRIVER=n
-CONFIG_PLATFORM_EC_SMBUS_PEC=y
-CONFIG_PLATFORM_EC_USBC=y
-CONFIG_PLATFORM_EC_USBC_PPC_DEDICATED_INT=y
-CONFIG_PLATFORM_EC_USBC_PPC_RT1739=y
-CONFIG_PLATFORM_EC_USBC_PPC_SYV682C=y
-CONFIG_PLATFORM_EC_USBC_PPC_SYV682X=y
-CONFIG_PLATFORM_EC_USB_MUX_IT5205=y
-CONFIG_PLATFORM_EC_USB_MUX_TUSB546=y
-CONFIG_PLATFORM_EC_USB_MUX_VIRTUAL=y
-CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y
-CONFIG_PLATFORM_EC_USB_PD_DP_HPD_GPIO=y
-CONFIG_PLATFORM_EC_USB_PD_DP_HPD_GPIO_CUSTOM=y
-CONFIG_PLATFORM_EC_USB_PD_FRS=y
-CONFIG_PLATFORM_EC_USB_PD_FRS_PPC=y
-CONFIG_PLATFORM_EC_USB_PD_ITE_ACTIVE_PORT_COUNT=2
-CONFIG_PLATFORM_EC_USB_PD_LOGGING=y
-CONFIG_PLATFORM_EC_USB_PD_TCPM_DRIVER_IT8XXX2=y
-CONFIG_PLATFORM_EC_USB_PD_TCPM_ITE_ON_CHIP=y
-CONFIG_PLATFORM_EC_USB_PD_TCPM_TCPCI=y
-CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_PPC=y
-CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_ADC_EACH_PORT=y
-CONFIG_PLATFORM_EC_USB_PORT_POWER_DUMB_CUSTOM_HOOK=y
-CONFIG_PLATFORM_EC_USB_PD_DUAL_ROLE_AUTO_TOGGLE=n
-CONFIG_PLATFORM_EC_USB_PD_USB32_DRD=n
-CONFIG_PLATFORM_EC_USB_PD_USB4=n
-CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=n
-
-# TODO(b/180980668): bring these features up
-CONFIG_LTO=n
-CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
+CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI2=y
diff --git a/zephyr/projects/corsola/prj_magikarp.conf b/zephyr/projects/corsola/prj_magikarp.conf
new file mode 100644
index 0000000000..72d7ea59f7
--- /dev/null
+++ b/zephyr/projects/corsola/prj_magikarp.conf
@@ -0,0 +1,22 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Variant config
+CONFIG_BOARD_MAGIKARP=y
+
+# USB-C
+CONFIG_PLATFORM_EC_USB_MUX_TUSB546=n
+CONFIG_PLATFORM_EC_USB_MUX_PS8743=y
+
+# Keyboard
+CONFIG_PLATFORM_EC_KEYBOARD_REFRESH_ROW3=y
+CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI3=y
+
+# Sensor
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y
+
+# Temperature sensors
+CONFIG_PLATFORM_EC_TEMP_SENSOR=y
+CONFIG_PLATFORM_EC_THERMISTOR=y
diff --git a/zephyr/projects/corsola/prj_npcx993_base.conf b/zephyr/projects/corsola/prj_npcx993_base.conf
new file mode 100644
index 0000000000..f3b220898e
--- /dev/null
+++ b/zephyr/projects/corsola/prj_npcx993_base.conf
@@ -0,0 +1,95 @@
+# Copyright 2022 The ChromiumOS Authors.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+
+# Bring up options
+CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y
+
+# Debug options and features; can be disabled to save memory or once bringup
+# is complete.
+CONFIG_SHELL_MINIMAL=n
+CONFIG_LOG=y
+CONFIG_LOG_MODE_MINIMAL=y
+
+# ADC
+CONFIG_ADC=y
+
+# Charger
+CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y
+CONFIG_PLATFORM_EC_CHARGER_ISL9238C=y
+CONFIG_PLATFORM_EC_CHARGER_PSYS=y
+CONFIG_PLATFORM_EC_CHARGER_PSYS_READ=y
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=20
+CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_ADC_AMON_BMON=y
+
+# PWM
+CONFIG_PWM=y
+CONFIG_PWM_SHELL=n
+
+# LED
+CONFIG_PLATFORM_EC_LED_COMMON=y
+CONFIG_PLATFORM_EC_LED_ONOFF_STATES=y
+
+# Math
+CONFIG_PLATFORM_EC_MATH_UTIL=y
+
+# Power sequencing
+CONFIG_PLATFORM_EC_POWERSEQ_MT8186=y
+CONFIG_PLATFORM_EC_POWERSEQ_S4=n
+
+# Button
+CONFIG_PLATFORM_EC_BUTTONS_RUNTIME_CONFIG=y
+
+# Sensors
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y
+CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y
+CONFIG_PLATFORM_EC_ACCEL_FIFO=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=y
+CONFIG_PLATFORM_EC_GMR_TABLET_MODE=y
+CONFIG_PLATFORM_EC_LID_ANGLE=y
+CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y
+CONFIG_PLATFORM_EC_LID_SWITCH=y
+CONFIG_PLATFORM_EC_MOTIONSENSE=y
+CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=y
+CONFIG_PLATFORM_EC_TABLET_MODE=y
+CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=y
+
+# USBA
+CONFIG_PLATFORM_EC_USBA=y
+
+# USBC
+CONFIG_PLATFORM_EC_BC12_DETECT_PI3USB9201=y
+CONFIG_PLATFORM_EC_BC12_SINGLE_DRIVER=n
+CONFIG_PLATFORM_EC_PD_POWER_SUPPLY_TURN_OFF_DELAY=15000
+CONFIG_PLATFORM_EC_PD_POWER_SUPPLY_TURN_ON_DELAY=15000
+CONFIG_PLATFORM_EC_USBC_PPC=y
+CONFIG_PLATFORM_EC_USBC_PPC_NX20P3483=y
+CONFIG_PLATFORM_EC_USBC_PPC_RT1718S=y
+CONFIG_PLATFORM_EC_USB_MUX_PS8743=y
+CONFIG_PLATFORM_EC_USB_MUX_VIRTUAL=y
+CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y
+CONFIG_PLATFORM_EC_USB_PD_FRS_TCPC=y
+CONFIG_PLATFORM_EC_USB_PD_LOGGING=y
+CONFIG_PLATFORM_EC_USB_PD_DEBUG_FIXED_LEVEL=y
+CONFIG_PLATFORM_EC_USB_PD_DEBUG_LEVEL=2
+CONFIG_PLATFORM_EC_USB_PD_TCPM_ANX7447=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_ANX7447_AUX_PU_PD=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_RT1718S=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_SBU=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_BY_BOARD=y
+
+# External power
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
+
+# Keyboard
+CONFIG_CROS_KB_RAW_NPCX=y
+CONFIG_CROS_KB_RAW_NPCX_KSO_HIGH_DRIVE=y
+
+CONFIG_SYSCON=y
+
+CONFIG_PLATFORM_EC_BOARD_VERSION_GPIO=n
diff --git a/zephyr/projects/corsola/prj_steelix.conf b/zephyr/projects/corsola/prj_steelix.conf
index 48971c9ed4..265a1a4cc4 100644
--- a/zephyr/projects/corsola/prj_steelix.conf
+++ b/zephyr/projects/corsola/prj_steelix.conf
@@ -1,13 +1,21 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 # Variant config
-CONFIG_BOARD_KINGLER=n
 CONFIG_BOARD_STEELIX=y
 
 # steelix only use D2, drop the workaround config for H1
 CONFIG_PLATFORM_EC_BOARD_RESET_AFTER_POWER_ON=n
 
-# LED
-CONFIG_PLATFORM_EC_LED_PWM=n
+# Motion sensor
+CONFIG_PLATFORM_EC_DYNAMIC_MOTION_SENSOR_COUNT=y
+
+# Keyboard
+CONFIG_PLATFORM_EC_KEYBOARD_REFRESH_ROW3=y
+CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI3=y
+CONFIG_PLATFORM_EC_KEYBOARD_STRICT_DEBOUNCE=y
+
+# USBC
+CONFIG_PLATFORM_EC_PD_MAX_CURRENT_MA=3250
+CONFIG_PLATFORM_EC_PD_MAX_POWER_MW=65000
diff --git a/zephyr/projects/corsola/prj_tentacruel.conf b/zephyr/projects/corsola/prj_tentacruel.conf
new file mode 100644
index 0000000000..71cc9d9694
--- /dev/null
+++ b/zephyr/projects/corsola/prj_tentacruel.conf
@@ -0,0 +1,26 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Variant config
+CONFIG_BOARD_TENTACRUEL=y
+
+# USB-C
+CONFIG_PLATFORM_EC_BC12_DETECT_PI3USB9201=y
+CONFIG_PLATFORM_EC_USB_MUX_TUSB546=n
+CONFIG_PLATFORM_EC_USB_MUX_PS8743=y
+
+# Keyboard
+CONFIG_PLATFORM_EC_KEYBOARD_REFRESH_ROW3=y
+CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI3=y
+
+# Sensor
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y
+
+# Temperature sensors
+CONFIG_PLATFORM_EC_TEMP_SENSOR=y
+CONFIG_PLATFORM_EC_THERMISTOR=y
+
+# Battery
+CONFIG_PLATFORM_EC_CHARGER_PROFILE_OVERRIDE=y
diff --git a/zephyr/projects/corsola/src/board_chipset.c b/zephyr/projects/corsola/src/board_chipset.c
index ca8f3b0507..54e96bc631 100644
--- a/zephyr/projects/corsola/src/board_chipset.c
+++ b/zephyr/projects/corsola/src/board_chipset.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/corsola/src/hibernate.c b/zephyr/projects/corsola/src/hibernate.c
index afd22fd3e7..56c085e077 100644
--- a/zephyr/projects/corsola/src/hibernate.c
+++ b/zephyr/projects/corsola/src/hibernate.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/corsola/src/kingler/board_steelix.c b/zephyr/projects/corsola/src/kingler/board_steelix.c
new file mode 100644
index 0000000000..c8ba0e7e74
--- /dev/null
+++ b/zephyr/projects/corsola/src/kingler/board_steelix.c
@@ -0,0 +1,51 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Board re-init for Rusty board
+ * Rusty shares the firmware with Steelix.
+ * Steelix is convertible but Rusty is clamshell
+ * so some functions should be disabled for clamshell.
+ */
+#include <zephyr/logging/log.h>
+#include <zephyr/drivers/gpio.h>
+
+#include "cros_cbi.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "motion_sense.h"
+#include "tablet_mode.h"
+
+LOG_MODULE_REGISTER(board_init, LOG_LEVEL_ERR);
+
+static bool board_is_clamshell;
+
+static void board_setup_init(void)
+{
+	int ret;
+	uint32_t val;
+
+	ret = cros_cbi_get_fw_config(FORM_FACTOR, &val);
+	if (ret != 0) {
+		LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FORM_FACTOR);
+		return;
+	}
+	if (val == CLAMSHELL) {
+		board_is_clamshell = true;
+		motion_sensor_count = 0;
+		gmr_tablet_switch_disable();
+	}
+}
+DECLARE_HOOK(HOOK_INIT, board_setup_init, HOOK_PRIO_PRE_DEFAULT);
+
+static void disable_base_imu_irq(void)
+{
+	if (board_is_clamshell) {
+		gpio_disable_dt_interrupt(
+			GPIO_INT_FROM_NODELABEL(int_base_imu));
+		gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(base_imu_int_l),
+				      GPIO_INPUT | GPIO_PULL_UP);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, disable_base_imu_irq, HOOK_PRIO_POST_DEFAULT);
diff --git a/zephyr/projects/corsola/src/kingler/button.c b/zephyr/projects/corsola/src/kingler/button.c
index d10d771950..920069bef6 100644
--- a/zephyr/projects/corsola/src/kingler/button.c
+++ b/zephyr/projects/corsola/src/kingler/button.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/corsola/src/kingler/i2c.c b/zephyr/projects/corsola/src/kingler/i2c.c
index 6236d42714..f2bbff3749 100644
--- a/zephyr/projects/corsola/src/kingler/i2c.c
+++ b/zephyr/projects/corsola/src/kingler/i2c.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,6 +12,10 @@
 int board_allow_i2c_passthru(const struct i2c_cmd_desc_t *cmd_desc)
 {
 	return (i2c_get_device_for_port(cmd_desc->port) ==
-		i2c_get_device_for_port(I2C_PORT_VIRTUAL_BATTERY));
+			i2c_get_device_for_port(I2C_PORT_VIRTUAL_BATTERY) ||
+		i2c_get_device_for_port(cmd_desc->port) ==
+			i2c_get_device_for_port(I2C_PORT_EEPROM) ||
+		i2c_get_device_for_port(cmd_desc->port) ==
+			i2c_get_device_for_port(I2C_PORT_USB_C0));
 }
 #endif
diff --git a/zephyr/projects/corsola/src/kingler/led.c b/zephyr/projects/corsola/src/kingler/led.c
index 045ddb5be1..4e2c5b12fb 100644
--- a/zephyr/projects/corsola/src/kingler/led.c
+++ b/zephyr/projects/corsola/src/kingler/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -13,20 +13,25 @@
 __override const int led_charge_lvl_1 = 5;
 __override const int led_charge_lvl_2 = 97;
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED,    LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER,  LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
 
 __override void led_set_color_battery(enum ec_led_colors color)
 {
diff --git a/zephyr/projects/corsola/src/kingler/led_steelix.c b/zephyr/projects/corsola/src/kingler/led_steelix.c
index 2d2e1431a1..87b76128e8 100644
--- a/zephyr/projects/corsola/src/kingler/led_steelix.c
+++ b/zephyr/projects/corsola/src/kingler/led_steelix.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -10,6 +10,7 @@
 
 #include "board_led.h"
 #include "common.h"
+#include "cros_cbi.h"
 #include "led_common.h"
 #include "led_onoff_states.h"
 #include "util.h"
@@ -28,29 +29,36 @@ static const struct board_led_pwm_dt_channel board_led_power_white =
 __override const int led_charge_lvl_1 = 5;
 __override const int led_charge_lvl_2 = 97;
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED,    LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER,  LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
 
 __override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-					{LED_OFF,	   0.5 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC},
-					{LED_OFF,	   0.5 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 3 * LED_ONE_SEC },
+					       { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    3 * LED_ONE_SEC },
+						  { LED_OFF,
+						    0.5 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
 
 const enum ec_led_id supported_led_ids[] = {
 	EC_LED_ID_BATTERY_LED,
@@ -72,8 +80,8 @@ static void board_led_pwm_set_duty(const struct board_led_pwm_dt_channel *ch,
 
 	pulse_ns = DIV_ROUND_NEAREST(BOARD_LED_PWM_PERIOD_NS * percent, 100);
 
-	LOG_DBG("Board LED PWM %s set percent (%d), pulse %d",
-		ch->dev->name, percent, pulse_ns);
+	LOG_DBG("Board LED PWM %s set percent (%d), pulse %d", ch->dev->name,
+		percent, pulse_ns);
 
 	rv = pwm_set(ch->dev, ch->channel, BOARD_LED_PWM_PERIOD_NS, pulse_ns,
 		     ch->flags);
@@ -82,6 +90,20 @@ static void board_led_pwm_set_duty(const struct board_led_pwm_dt_channel *ch,
 	}
 }
 
+static bool device_is_clamshell(void)
+{
+	int ret;
+	uint32_t val;
+
+	ret = cros_cbi_get_fw_config(FORM_FACTOR, &val);
+	if (ret != 0) {
+		LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FORM_FACTOR);
+		return false;
+	}
+
+	return val == CLAMSHELL;
+}
+
 __override void led_set_color_battery(enum ec_led_colors color)
 {
 	switch (color) {
@@ -106,13 +128,17 @@ __override void led_set_color_battery(enum ec_led_colors color)
 
 __override void led_set_color_power(enum ec_led_colors color)
 {
-	switch (color) {
-	case EC_LED_COLOR_WHITE:
-		board_led_pwm_set_duty(&board_led_power_white, 100);
-		break;
-	default:
+	if (device_is_clamshell()) {
 		board_led_pwm_set_duty(&board_led_power_white, 0);
-		break;
+	} else {
+		switch (color) {
+		case EC_LED_COLOR_WHITE:
+			board_led_pwm_set_duty(&board_led_power_white, 100);
+			break;
+		default:
+			board_led_pwm_set_duty(&board_led_power_white, 0);
+			break;
+		}
 	}
 }
 
@@ -123,7 +149,11 @@ void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
 		brightness_range[EC_LED_COLOR_GREEN] = 1;
 		brightness_range[EC_LED_COLOR_AMBER] = 1;
 	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		if (device_is_clamshell()) {
+			brightness_range[EC_LED_COLOR_WHITE] = 0;
+		} else {
+			brightness_range[EC_LED_COLOR_WHITE] = 1;
+		}
 	}
 }
 
diff --git a/zephyr/projects/corsola/src/kingler/usb_pd_policy.c b/zephyr/projects/corsola/src/kingler/usb_pd_policy.c
index 51a05598b9..3de2857ad1 100644
--- a/zephyr/projects/corsola/src/kingler/usb_pd_policy.c
+++ b/zephyr/projects/corsola/src/kingler/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,8 +14,8 @@
 
 #include "baseboard_usbc_config.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 void pd_power_supply_reset(int port)
 {
@@ -39,7 +39,6 @@ void pd_power_supply_reset(int port)
 	pd_send_host_event(PD_EVENT_POWER_CHANGE);
 }
 
-
 int pd_set_power_supply_ready(int port)
 {
 	int rv;
diff --git a/zephyr/projects/corsola/src/kingler/usbc_config.c b/zephyr/projects/corsola/src/kingler/usbc_config.c
index 42aa0a31d6..8c0ca86454 100644
--- a/zephyr/projects/corsola/src/kingler/usbc_config.c
+++ b/zephyr/projects/corsola/src/kingler/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -31,57 +31,16 @@
 #endif
 #include "gpio.h"
 
-
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-
-struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = AN7447_TCPC0_I2C_ADDR_FLAGS,
-		},
-		.drv = &anx7447_tcpm_drv,
-		/* Alert is active-low, open-drain */
-		.flags = TCPC_FLAGS_ALERT_OD | TCPC_FLAGS_VBUS_MONITOR |
-			 TCPC_FLAGS_CONTROL_FRS,
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C1,
-			.addr_flags = RT1718S_I2C_ADDR2_FLAGS,
-		},
-		.drv = &rt1718s_tcpm_drv,
-		/* Alert is active-low, open-drain */
-		.flags = TCPC_FLAGS_ALERT_OD | TCPC_FLAGS_VBUS_MONITOR |
-			 TCPC_FLAGS_CONTROL_FRS,
-	}
-};
-
-struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = NX20P3483_ADDR2_FLAGS,
-		.drv = &nx20p348x_drv
-	},
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = NX20P3483_ADDR2_FLAGS,
-		.drv = &nx20p348x_drv
-	}
-};
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
 
 /* USB Mux */
 
 /* USB Mux C1 : board_init of PS8743 */
-static int ps8743_tune_mux(const struct usb_mux *me)
+int ps8743_mux_1_board_init(const struct usb_mux *me)
 {
-	ps8743_tune_usb_eq(me,
-			PS8743_USB_EQ_TX_3_6_DB,
-			PS8743_USB_EQ_RX_16_0_DB);
+	ps8743_tune_usb_eq(me, PS8743_USB_EQ_TX_3_6_DB,
+			   PS8743_USB_EQ_RX_16_0_DB);
 
 	return EC_SUCCESS;
 }
@@ -90,61 +49,13 @@ void board_usb_mux_init(void)
 {
 	if (corsola_get_db_type() == CORSOLA_DB_TYPEC) {
 		/* Disable DCI function. This is not needed for ARM. */
-		ps8743_field_update(&usb_muxes[1],
-				   PS8743_REG_DCI_CONFIG_2,
-				   PS8743_AUTO_DCI_MODE_MASK,
-				   PS8743_AUTO_DCI_MODE_FORCE_USB);
+		ps8743_field_update(usb_muxes[1].mux, PS8743_REG_DCI_CONFIG_2,
+				    PS8743_AUTO_DCI_MODE_MASK,
+				    PS8743_AUTO_DCI_MODE_FORCE_USB);
 	}
 }
 DECLARE_HOOK(HOOK_INIT, board_usb_mux_init, HOOK_PRIO_INIT_I2C + 1);
 
-const struct usb_mux usbc0_virtual_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-
-const struct usb_mux usbc1_virtual_mux = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
-};
-
-struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &anx7447_usb_mux_driver,
-		.hpd_update = &anx7447_tcpc_update_hpd_status,
-		.next_mux = &usbc0_virtual_mux,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = PS8743_I2C_ADDR0_FLAG,
-		.driver = &ps8743_usb_mux_driver,
-		.next_mux = &usbc1_virtual_mux,
-		.board_init = &ps8743_tune_mux,
-	},
-};
-
-struct bc12_config bc12_ports[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USBC_PORT_C0] = {
-		.drv = &pi3usb9201_drv,
-	},
-	[USBC_PORT_C1] = {
-		.drv = &rt1718s_bc12_drv,
-	}
-};
-
-const struct pi3usb9201_config_t
-		pi3usb9201_bc12_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-	[USBC_PORT_C1] = { /* unused */ }
-};
-
 void board_tcpc_init(void)
 {
 	/* Only reset TCPC if not sysjump */
@@ -169,7 +80,7 @@ void board_tcpc_init(void)
 	 */
 	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) {
 		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 	}
 }
 DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_POST_I2C);
@@ -188,20 +99,28 @@ __override int board_rt1718s_init(int port)
 
 	/* gpio1 low, gpio2 output high when receiving frs signal */
 	RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_GPIO1_VBUS_CTRL,
-			RT1718S_GPIO1_VBUS_CTRL_FRS_RX_VBUS, 0));
+					  RT1718S_GPIO1_VBUS_CTRL_FRS_RX_VBUS,
+					  0));
 	RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_GPIO2_VBUS_CTRL,
-			RT1718S_GPIO2_VBUS_CTRL_FRS_RX_VBUS, 0xFF));
+					  RT1718S_GPIO2_VBUS_CTRL_FRS_RX_VBUS,
+					  0xFF));
 
 	/* Trigger GPIO 1/2 change when FRS signal received */
-	RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_FRS_CTRL3,
-			RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO2 |
+	RETURN_ERROR(rt1718s_update_bits8(
+		port, RT1718S_FRS_CTRL3,
+		RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO2 |
 			RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO1,
-			RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO2 |
+		RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO2 |
 			RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO1));
 	/* Set FRS signal detect time to 46.875us */
 	RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_FRS_CTRL1,
-			RT1718S_FRS_CTRL1_FRSWAPRX_MASK,
-			0xFF));
+					  RT1718S_FRS_CTRL1_FRSWAPRX_MASK,
+					  0xFF));
+
+	/* Disable BC1.2 SRC mode */
+	RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_RT2_BC12_SRC_FUNC,
+					  RT1718S_RT2_BC12_SRC_FUNC_BC12_SRC_EN,
+					  0));
 
 	return EC_SUCCESS;
 }
@@ -215,13 +134,12 @@ __override int board_rt1718s_set_frs_enable(int port, int enable)
 		 * FRS path.
 		 */
 		rt1718s_gpio_set_flags(port, GPIO_EN_USB_C1_FRS,
-				enable ? GPIO_OUT_HIGH : GPIO_OUT_LOW);
+				       enable ? GPIO_OUT_HIGH : GPIO_OUT_LOW);
 	return EC_SUCCESS;
 }
 
 void board_reset_pd_mcu(void)
 {
-
 	CPRINTS("Resetting TCPCs...");
 	/* reset C0 ANX3447 */
 	/* Assert reset */
@@ -315,15 +233,15 @@ uint16_t tcpc_get_alert_status(void)
 	uint16_t status = 0;
 
 	if (!gpio_pin_get_dt(
-		GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_int_odl))) {
+		    GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_int_odl))) {
 		if (!gpio_pin_get_dt(
-			GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_rst))) {
+			    GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_rst))) {
 			status |= PD_STATUS_TCPC_ALERT_0;
 		}
 	}
 
 	if (!gpio_pin_get_dt(
-		GPIO_DT_FROM_NODELABEL(gpio_usb_c1_tcpc_int_odl))) {
+		    GPIO_DT_FROM_NODELABEL(gpio_usb_c1_tcpc_int_odl))) {
 		return status |= PD_STATUS_TCPC_ALERT_1;
 	}
 	return status;
diff --git a/zephyr/projects/corsola/src/krabby/battery.c b/zephyr/projects/corsola/src/krabby/battery.c
deleted file mode 100644
index 0c0efc8200..0000000000
--- a/zephyr/projects/corsola/src/krabby/battery.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "battery.h"
-#include "battery_fuel_gauge.h"
-#include "battery_smart.h"
-#include "charge_manager.h"
-#include "chipset.h"
-#include "hooks.h"
-#include "system.h"
-#include "usb_pd.h"
-
-const struct board_batt_params board_battery_info[] = {
-	[BATTERY_C235] = {
-		.fuel_gauge = {
-			.manuf_name = "AS3GWRc3KA",
-			.device_name = "C235-41",
-			.ship_mode = {
-				.reg_addr = 0x0,
-				.reg_data = { 0x10, 0x10 },
-			},
-			.fet = {
-				.reg_addr = 0x99,
-				.reg_mask = 0x0c,
-				.disconnect_val = 0x0c,
-			}
-		},
-		.batt_info = {
-			.voltage_max		= 8800,
-			.voltage_normal		= 7700,
-			.voltage_min		= 6000,
-			.precharge_current	= 256,
-			.start_charging_min_c	= 0,
-			.start_charging_max_c	= 45,
-			.charging_min_c		= 0,
-			.charging_max_c		= 60,
-			.discharging_min_c	= 0,
-			.discharging_max_c	= 60,
-		},
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
-
-const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_C235;
diff --git a/zephyr/projects/corsola/src/krabby/charger_workaround.c b/zephyr/projects/corsola/src/krabby/charger_workaround.c
index 373917db56..dda91fccb5 100644
--- a/zephyr/projects/corsola/src/krabby/charger_workaround.c
+++ b/zephyr/projects/corsola/src/krabby/charger_workaround.c
@@ -1,22 +1,30 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include <zephyr/sys/util.h>
+
 #include "charger.h"
 #include "driver/charger/rt9490.h"
 #include "hooks.h"
 #include "i2c.h"
 #include "system.h"
 
+/*
+ * This workaround and the board id checks only apply to krabby and early
+ * tentacruel devices.
+ * Newer project should have all of these fixed.
+ */
+BUILD_ASSERT(IS_ENABLED(CONFIG_BOARD_KRABBY) ||
+	     IS_ENABLED(CONFIG_BOARD_TENTACRUEL) || IS_ENABLED(CONFIG_TEST));
+
 static void enter_hidden_mode(void)
 {
 	i2c_write8(chg_chips[CHARGER_SOLO].i2c_port,
-		   chg_chips[CHARGER_SOLO].i2c_addr_flags,
-		   0xF1, 0x69);
+		   chg_chips[CHARGER_SOLO].i2c_addr_flags, 0xF1, 0x69);
 	i2c_write8(chg_chips[CHARGER_SOLO].i2c_port,
-		   chg_chips[CHARGER_SOLO].i2c_addr_flags,
-		   0xF2, 0x96);
+		   chg_chips[CHARGER_SOLO].i2c_addr_flags, 0xF2, 0x96);
 }
 
 /* b/194967754#comment5: work around for IBUS ADC unstable issue */
@@ -28,48 +36,33 @@ static void ibus_adc_workaround(void)
 
 	i2c_update8(chg_chips[CHARGER_SOLO].i2c_port,
 		    chg_chips[CHARGER_SOLO].i2c_addr_flags,
-		    RT9490_REG_ADC_CHANNEL0,
-		    RT9490_VSYS_ADC_DIS,
-		    MASK_SET);
+		    RT9490_REG_ADC_CHANNEL0, RT9490_VSYS_ADC_DIS, MASK_SET);
 
 	enter_hidden_mode();
 
 	/* undocumented registers... */
 	i2c_write8(chg_chips[CHARGER_SOLO].i2c_port,
-		   chg_chips[CHARGER_SOLO].i2c_addr_flags,
-		   0x52, 0xC4);
+		   chg_chips[CHARGER_SOLO].i2c_addr_flags, 0x52, 0xC4);
 
 	i2c_update8(chg_chips[CHARGER_SOLO].i2c_port,
 		    chg_chips[CHARGER_SOLO].i2c_addr_flags,
-		    RT9490_REG_ADC_CHANNEL0,
-		    RT9490_VSYS_ADC_DIS,
-		    MASK_CLR);
+		    RT9490_REG_ADC_CHANNEL0, RT9490_VSYS_ADC_DIS, MASK_CLR);
 }
 
 /* b/214880220#comment44: lock i2c at 400khz */
 static void i2c_speed_workaround(void)
 {
-	/*
-	 * This workaround can be applied to all version of RT9490 in our cases
-	 * no need to identify chip version.
-	 */
+	if (system_get_board_version() >= 3) {
+		return;
+	}
+
 	enter_hidden_mode();
 	/* Set to Auto mode, default run at 400kHz */
 	i2c_write8(chg_chips[CHARGER_SOLO].i2c_port,
-		   chg_chips[CHARGER_SOLO].i2c_addr_flags,
-		   0x71, 0x22);
+		   chg_chips[CHARGER_SOLO].i2c_addr_flags, 0x71, 0x22);
 	/* Manually select for 400kHz, valid only when 0x71[7] == 1 */
 	i2c_write8(chg_chips[CHARGER_SOLO].i2c_port,
-		   chg_chips[CHARGER_SOLO].i2c_addr_flags,
-		   0xF7, 0x14);
-}
-
-static void pwm_freq_workaround(void)
-{
-	/* Reduce SW freq from 1.5MHz to 1MHz
-	 * for 10% higher current rating b/215294785
-	 */
-	rt9490_enable_pwm_1mhz(CHARGER_SOLO, true);
+		   chg_chips[CHARGER_SOLO].i2c_addr_flags, 0xF7, 0x14);
 }
 
 static void eoc_deglitch_workaround(void)
@@ -81,16 +74,27 @@ static void eoc_deglitch_workaround(void)
 	/* set end-of-charge deglitch time to 2ms */
 	i2c_update8(chg_chips[CHARGER_SOLO].i2c_port,
 		    chg_chips[CHARGER_SOLO].i2c_addr_flags,
-		    RT9490_REG_ADD_CTRL0,
-		    RT9490_TD_EOC,
-		    MASK_CLR);
+		    RT9490_REG_ADD_CTRL0, RT9490_TD_EOC, MASK_CLR);
+}
+
+static void disable_safety_timer(void)
+{
+	if (system_get_board_version() >= 2) {
+		return;
+	}
+	/* Disable charge timer */
+	i2c_write8(chg_chips[CHARGER_SOLO].i2c_port,
+		   chg_chips[CHARGER_SOLO].i2c_addr_flags,
+		   RT9490_REG_SAFETY_TMR_CTRL,
+		   RT9490_EN_TRICHG_TMR | RT9490_EN_PRECHG_TMR |
+			   RT9490_EN_FASTCHG_TMR);
 }
 
 static void board_rt9490_workaround(void)
 {
 	ibus_adc_workaround();
 	i2c_speed_workaround();
-	pwm_freq_workaround();
 	eoc_deglitch_workaround();
+	disable_safety_timer();
 }
 DECLARE_HOOK(HOOK_INIT, board_rt9490_workaround, HOOK_PRIO_DEFAULT);
diff --git a/zephyr/projects/corsola/src/krabby/hooks.c b/zephyr/projects/corsola/src/krabby/hooks.c
index 9fae7c8bb5..1eb4f600f2 100644
--- a/zephyr/projects/corsola/src/krabby/hooks.c
+++ b/zephyr/projects/corsola/src/krabby/hooks.c
@@ -1,10 +1,11 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include <zephyr/init.h>
 #include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/pinctrl.h>
 
 #include <ap_power/ap_power.h>
 #include "charger.h"
@@ -13,22 +14,21 @@
 #include "gpio.h"
 #include "hooks.h"
 
+#define I2C3_NODE DT_NODELABEL(i2c3)
+PINCTRL_DT_DEFINE(I2C3_NODE);
+
 static void board_i2c3_ctrl(bool enable)
 {
-	if (DEVICE_DT_GET(DT_GPIO_CTLR_BY_IDX(DT_NODELABEL(i2c3),
-	    scl_gpios, 0)) == DEVICE_DT_GET(DT_NODELABEL(gpiof))) {
-		/*
-		 * TODO(b/226296649):
-		 * Use pinctrl APIs to enable/disable an interface.
-		 */
-		struct gctrl_it8xxx2_regs *const gctrl_base =
-			(struct gctrl_it8xxx2_regs *)
-				DT_REG_ADDR(DT_NODELABEL(gctrl));
+	if (DEVICE_DT_GET(
+		    DT_GPIO_CTLR_BY_IDX(DT_NODELABEL(i2c3), scl_gpios, 0)) ==
+	    DEVICE_DT_GET(DT_NODELABEL(gpiof))) {
+		const struct pinctrl_dev_config *pcfg =
+			PINCTRL_DT_DEV_CONFIG_GET(I2C3_NODE);
 
 		if (enable) {
-			gctrl_base->GCTRL_PMER3 |= IT8XXX2_GCTRL_SMB3PSEL;
+			pinctrl_apply_state(pcfg, PINCTRL_STATE_DEFAULT);
 		} else {
-			gctrl_base->GCTRL_PMER3 &= ~IT8XXX2_GCTRL_SMB3PSEL;
+			pinctrl_apply_state(pcfg, PINCTRL_STATE_SLEEP);
 		}
 	}
 }
diff --git a/zephyr/projects/corsola/src/krabby/i2c.c b/zephyr/projects/corsola/src/krabby/i2c.c
index 3b5108e115..a83af77dbd 100644
--- a/zephyr/projects/corsola/src/krabby/i2c.c
+++ b/zephyr/projects/corsola/src/krabby/i2c.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,6 +12,8 @@
 int board_allow_i2c_passthru(const struct i2c_cmd_desc_t *cmd_desc)
 {
 	return (i2c_get_device_for_port(cmd_desc->port) ==
-		i2c_get_device_for_port(I2C_PORT_VIRTUAL_BATTERY));
+			i2c_get_device_for_port(I2C_PORT_VIRTUAL_BATTERY) ||
+		i2c_get_device_for_port(cmd_desc->port) ==
+			i2c_get_device_for_port(I2C_PORT_EEPROM));
 }
 #endif
diff --git a/zephyr/projects/corsola/src/krabby/led.c b/zephyr/projects/corsola/src/krabby/led.c
deleted file mode 100644
index c001615402..0000000000
--- a/zephyr/projects/corsola/src/krabby/led.c
+++ /dev/null
@@ -1,147 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <zephyr/drivers/pwm.h>
-#include <zephyr/logging/log.h>
-
-#include "board_led.h"
-#include "common.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-#include "util.h"
-
-LOG_MODULE_REGISTER(board_led, LOG_LEVEL_ERR);
-
-/*If we need pwm output in ITE chip power saving mode, then we should set
- * frequency <= 324Hz.
- */
-#define BOARD_LED_PWM_PERIOD_NS BOARD_LED_HZ_TO_PERIOD_NS(324)
-
-static const struct board_led_pwm_dt_channel board_led_power_white =
-	BOARD_LED_PWM_DT_CHANNEL_INITIALIZER(DT_NODELABEL(led_power_white));
-static const struct board_led_pwm_dt_channel board_led_battery_amber =
-	BOARD_LED_PWM_DT_CHANNEL_INITIALIZER(DT_NODELABEL(led_battery_amber));
-static const struct board_led_pwm_dt_channel board_led_battery_white =
-	BOARD_LED_PWM_DT_CHANNEL_INITIALIZER(DT_NODELABEL(led_battery_white));
-
-__override const int led_charge_lvl_1 = 5;
-__override const int led_charge_lvl_2 = 95;
-
-__override struct led_descriptor
-		led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_WHITE,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} },
-};
-
-__override const struct led_descriptor
-		led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
-	[PWR_LED_STATE_ON]           = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} },
-	[PWR_LED_STATE_SUSPEND_AC]   = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	     3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC},
-					{LED_OFF,	     3 * LED_ONE_SEC} },
-	[PWR_LED_STATE_OFF]           = {{LED_OFF, LED_INDEFINITE} },
-};
-
-const enum ec_led_id supported_led_ids[] = {
-	EC_LED_ID_BATTERY_LED,
-	EC_LED_ID_POWER_LED,
-};
-
-const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
-
-static void board_led_pwm_set_duty(const struct board_led_pwm_dt_channel *ch,
-				   int percent)
-{
-	uint32_t pulse_ns;
-	int rv;
-
-	if (!device_is_ready(ch->dev)) {
-		LOG_ERR("PWM device %s not ready", ch->dev->name);
-		return;
-	}
-
-	pulse_ns = DIV_ROUND_NEAREST(BOARD_LED_PWM_PERIOD_NS * percent, 100);
-
-	LOG_DBG("Board LED PWM %s set percent (%d), pulse %d",
-		ch->dev->name, percent, pulse_ns);
-
-	rv = pwm_set(ch->dev, ch->channel, BOARD_LED_PWM_PERIOD_NS, pulse_ns,
-		     ch->flags);
-	if (rv) {
-		LOG_ERR("pwm_set() failed %s (%d)", ch->dev->name, rv);
-	}
-}
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_AMBER:
-		board_led_pwm_set_duty(&board_led_battery_amber, 100);
-		board_led_pwm_set_duty(&board_led_battery_white, 0);
-		break;
-	case EC_LED_COLOR_WHITE:
-		board_led_pwm_set_duty(&board_led_battery_amber, 0);
-		board_led_pwm_set_duty(&board_led_battery_white, 100);
-		break;
-	default:
-		board_led_pwm_set_duty(&board_led_battery_amber, 0);
-		board_led_pwm_set_duty(&board_led_battery_white, 0);
-		break;
-	}
-}
-
-__override void led_set_color_power(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_WHITE:
-		board_led_pwm_set_duty(&board_led_power_white, 100);
-		break;
-	default:
-		board_led_pwm_set_duty(&board_led_power_white, 0);
-		break;
-	}
-}
-
-void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		brightness_range[EC_LED_COLOR_AMBER] = 1;
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		brightness_range[EC_LED_COLOR_WHITE] = 1;
-	}
-}
-
-int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
-{
-	if (led_id == EC_LED_ID_BATTERY_LED) {
-		if (brightness[EC_LED_COLOR_AMBER] != 0) {
-			led_set_color_battery(EC_LED_COLOR_AMBER);
-		} else if (brightness[EC_LED_COLOR_WHITE] != 0) {
-			led_set_color_battery(EC_LED_COLOR_WHITE);
-		} else {
-			led_set_color_battery(LED_OFF);
-		}
-	} else if (led_id == EC_LED_ID_POWER_LED) {
-		if (brightness[EC_LED_COLOR_WHITE] != 0) {
-			led_set_color_power(EC_LED_COLOR_WHITE);
-		} else {
-			led_set_color_power(LED_OFF);
-		}
-	}
-
-	return EC_SUCCESS;
-}
diff --git a/zephyr/projects/corsola/src/krabby/sensor_magikarp.c b/zephyr/projects/corsola/src/krabby/sensor_magikarp.c
new file mode 100644
index 0000000000..269bc26fae
--- /dev/null
+++ b/zephyr/projects/corsola/src/krabby/sensor_magikarp.c
@@ -0,0 +1,41 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "accelgyro.h"
+#include "cros_cbi.h"
+#include "driver/accelgyro_bmi323.h"
+#include "driver/accelgyro_icm42607.h"
+#include "hooks.h"
+#include "motionsense_sensors.h"
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	uint32_t val;
+
+	cros_cbi_get_fw_config(FW_BASE_GYRO, &val);
+	if (val == FW_BASE_ICM42607) {
+		icm42607_interrupt(signal);
+	} else if (val == FW_BASE_BMI323) {
+		bmi3xx_interrupt(signal);
+	}
+}
+
+static void motionsense_init(void)
+{
+	uint32_t val;
+
+	cros_cbi_get_fw_config(FW_BASE_GYRO, &val);
+	if (val == FW_BASE_ICM42607) {
+		ccprints("BASE ACCEL is ICM42607");
+	} else if (val == FW_BASE_BMI323) {
+		MOTIONSENSE_ENABLE_ALTERNATE(alt_base_accel);
+		MOTIONSENSE_ENABLE_ALTERNATE(alt_base_gyro);
+		ccprints("BASE ACCEL IS BMI323");
+	} else {
+		ccprints("no motionsense");
+	}
+}
+DECLARE_HOOK(HOOK_INIT, motionsense_init, HOOK_PRIO_DEFAULT);
diff --git a/zephyr/projects/corsola/src/krabby/sensor_tentacruel.c b/zephyr/projects/corsola/src/krabby/sensor_tentacruel.c
new file mode 100644
index 0000000000..269bc26fae
--- /dev/null
+++ b/zephyr/projects/corsola/src/krabby/sensor_tentacruel.c
@@ -0,0 +1,41 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "accelgyro.h"
+#include "cros_cbi.h"
+#include "driver/accelgyro_bmi323.h"
+#include "driver/accelgyro_icm42607.h"
+#include "hooks.h"
+#include "motionsense_sensors.h"
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	uint32_t val;
+
+	cros_cbi_get_fw_config(FW_BASE_GYRO, &val);
+	if (val == FW_BASE_ICM42607) {
+		icm42607_interrupt(signal);
+	} else if (val == FW_BASE_BMI323) {
+		bmi3xx_interrupt(signal);
+	}
+}
+
+static void motionsense_init(void)
+{
+	uint32_t val;
+
+	cros_cbi_get_fw_config(FW_BASE_GYRO, &val);
+	if (val == FW_BASE_ICM42607) {
+		ccprints("BASE ACCEL is ICM42607");
+	} else if (val == FW_BASE_BMI323) {
+		MOTIONSENSE_ENABLE_ALTERNATE(alt_base_accel);
+		MOTIONSENSE_ENABLE_ALTERNATE(alt_base_gyro);
+		ccprints("BASE ACCEL IS BMI323");
+	} else {
+		ccprints("no motionsense");
+	}
+}
+DECLARE_HOOK(HOOK_INIT, motionsense_init, HOOK_PRIO_DEFAULT);
diff --git a/zephyr/projects/corsola/src/krabby/temp_tentacruel.c b/zephyr/projects/corsola/src/krabby/temp_tentacruel.c
new file mode 100644
index 0000000000..53a8312be6
--- /dev/null
+++ b/zephyr/projects/corsola/src/krabby/temp_tentacruel.c
@@ -0,0 +1,126 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charger.h"
+#include "charge_state.h"
+#include "common.h"
+#include "config.h"
+#include "console.h"
+#include "driver/charger/rt9490.h"
+#include "hooks.h"
+#include "temp_sensor/temp_sensor.h"
+#include "thermal.h"
+#include "util.h"
+
+#define NUM_CURRENT_LEVELS ARRAY_SIZE(current_table)
+#define TEMP_THRESHOLD 55
+#define TEMP_BUFF_SIZE 60
+#define KEEP_TIME 5
+
+/* calculate current average temperature */
+static int average_tempature(void)
+{
+	static int temp_history_buffer[TEMP_BUFF_SIZE];
+	static int buff_ptr;
+	static int temp_sum;
+	static int past_temp;
+	static int avg_temp;
+	int cur_temp, t;
+
+	temp_sensor_read(TEMP_SENSOR_ID(DT_NODELABEL(temp_charger)), &t);
+	cur_temp = K_TO_C(t);
+	past_temp = temp_history_buffer[buff_ptr];
+	temp_history_buffer[buff_ptr] = cur_temp;
+	temp_sum = temp_sum + temp_history_buffer[buff_ptr] - past_temp;
+	buff_ptr++;
+	if (buff_ptr >= TEMP_BUFF_SIZE) {
+		buff_ptr = 0;
+	}
+	/* Calculate per minute temperature.
+	 * It's expected low temperature when the first 60 seconds.
+	 */
+	avg_temp = temp_sum / TEMP_BUFF_SIZE;
+	return avg_temp;
+}
+
+static int current_level;
+
+/* Limit charging current table : 3600/3000/2400/1800
+ * note this should be in descending order.
+ */
+static uint16_t current_table[] = {
+	3600,
+	3000,
+	2400,
+	1800,
+};
+
+/* Called by hook task every hook second (1 sec) */
+static void current_update(void)
+{
+	int temp;
+	static uint8_t uptime;
+	static uint8_t dntime;
+
+	temp = average_tempature();
+	if (charge_get_state() == PWR_STATE_DISCHARGE) {
+		current_level = 0;
+		uptime = 0;
+		dntime = 0;
+		return;
+	}
+	if (temp >= TEMP_THRESHOLD) {
+		dntime = 0;
+		if (uptime < KEEP_TIME) {
+			uptime++;
+		} else {
+			uptime = 0;
+			current_level++;
+		}
+	} else if (current_level != 0 && temp < TEMP_THRESHOLD) {
+		uptime = 0;
+		if (dntime < KEEP_TIME) {
+			dntime++;
+		} else {
+			dntime = 0;
+			current_level--;
+		}
+	} else {
+		uptime = 0;
+		dntime = 0;
+	}
+	if (current_level > NUM_CURRENT_LEVELS) {
+		current_level = NUM_CURRENT_LEVELS;
+	}
+}
+DECLARE_HOOK(HOOK_SECOND, current_update, HOOK_PRIO_DEFAULT);
+
+int charger_profile_override(struct charge_state_data *curr)
+{
+	/*
+	 * Precharge must be executed when communication is failed on
+	 * dead battery.
+	 */
+	if (!(curr->batt.flags & BATT_FLAG_RESPONSIVE))
+		return 0;
+	if (current_level != 0) {
+		if (curr->requested_current > current_table[current_level - 1])
+			curr->requested_current =
+				current_table[current_level - 1];
+	}
+	return 0;
+}
+
+enum ec_status charger_profile_override_get_param(uint32_t param,
+						  uint32_t *value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+enum ec_status charger_profile_override_set_param(uint32_t param,
+						  uint32_t value)
+{
+	return EC_RES_INVALID_PARAM;
+}
diff --git a/zephyr/projects/corsola/src/krabby/usb_pd_policy.c b/zephyr/projects/corsola/src/krabby/usb_pd_policy.c
index 5f9ae83a19..8f2a2c3515 100644
--- a/zephyr/projects/corsola/src/krabby/usb_pd_policy.c
+++ b/zephyr/projects/corsola/src/krabby/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/corsola/src/krabby/usbc_config.c b/zephyr/projects/corsola/src/krabby/usbc_config.c
index 73ecd2f7bd..01686119cc 100644
--- a/zephyr/projects/corsola/src/krabby/usbc_config.c
+++ b/zephyr/projects/corsola/src/krabby/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,25 +23,15 @@
 
 #include "variant_db_detection.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
 void c0_bc12_interrupt(enum gpio_signal signal)
 {
 	rt1739_interrupt(0);
 }
 
-static void board_sub_bc12_init(void)
-{
-	if (corsola_get_db_type() == CORSOLA_DB_HDMI) {
-		/* If this is not a Type-C subboard, disable the task. */
-		task_disable_task(TASK_ID_USB_CHG_P1);
-	}
-}
-/* Must be done after I2C and subboard */
-DECLARE_HOOK(HOOK_INIT, board_sub_bc12_init, HOOK_PRIO_POST_I2C);
-
 static void board_usbc_init(void)
 {
 	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_ppc_bc12));
@@ -58,12 +48,12 @@ void ppc_interrupt(enum gpio_signal signal)
 int ppc_get_alert_status(int port)
 {
 	if (port == 0) {
-		return gpio_pin_get_dt(
-			GPIO_DT_FROM_NODELABEL(usb_c0_ppc_bc12_int_odl)) == 0;
+		return gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(
+			       usb_c0_ppc_bc12_int_odl)) == 0;
 	}
 	if (port == 1 && corsola_get_db_type() == CORSOLA_DB_TYPEC) {
-		return gpio_pin_get_dt(
-			GPIO_DT_FROM_ALIAS(gpio_usb_c1_ppc_int_odl)) == 0;
+		return gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(
+			       gpio_usb_c1_ppc_int_odl)) == 0;
 	}
 
 	return 0;
@@ -73,15 +63,19 @@ const struct cc_para_t *board_get_cc_tuning_parameter(enum usbpd_port port)
 {
 	const static struct cc_para_t
 		cc_parameter[CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT] = {
-		{
-			.rising_time = IT83XX_TX_PRE_DRIVING_TIME_1_UNIT,
-			.falling_time = IT83XX_TX_PRE_DRIVING_TIME_2_UNIT,
-		},
-		{
-			.rising_time = IT83XX_TX_PRE_DRIVING_TIME_1_UNIT,
-			.falling_time = IT83XX_TX_PRE_DRIVING_TIME_2_UNIT,
-		},
-	};
+			{
+				.rising_time =
+					IT83XX_TX_PRE_DRIVING_TIME_1_UNIT,
+				.falling_time =
+					IT83XX_TX_PRE_DRIVING_TIME_2_UNIT,
+			},
+			{
+				.rising_time =
+					IT83XX_TX_PRE_DRIVING_TIME_1_UNIT,
+				.falling_time =
+					IT83XX_TX_PRE_DRIVING_TIME_2_UNIT,
+			},
+		};
 
 	return &cc_parameter[port];
 }
@@ -169,10 +163,10 @@ int board_set_active_charge_port(int port)
 enum adc_channel board_get_vbus_adc(int port)
 {
 	if (port == 0) {
-		return  ADC_VBUS_C0;
+		return ADC_VBUS_C0;
 	}
 	if (port == 1) {
-		return  ADC_VBUS_C1;
+		return ADC_VBUS_C1;
 	}
 	CPRINTSUSB("Unknown vbus adc port id: %d", port);
 	return ADC_VBUS_C0;
diff --git a/zephyr/projects/corsola/src/krabby/usbc_config_tentacruel.c b/zephyr/projects/corsola/src/krabby/usbc_config_tentacruel.c
new file mode 100644
index 0000000000..691a28d50f
--- /dev/null
+++ b/zephyr/projects/corsola/src/krabby/usbc_config_tentacruel.c
@@ -0,0 +1,223 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Tentacruel board-specific USB-C configuration */
+
+#include "adc.h"
+#include "baseboard_usbc_config.h"
+#include "bc12/pi3usb9201_public.h"
+#include "charge_manager.h"
+#include "charger.h"
+#include "console.h"
+#include "cros_board_info.h"
+#include "driver/charger/rt9490.h"
+#include "driver/ppc/rt1739.h"
+#include "driver/tcpm/it83xx_pd.h"
+#include "driver/usb_mux/ps8743.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "ppc/syv682x_public.h"
+#include "usb_mux/it5205_public.h"
+#include "usbc_ppc.h"
+#include "usbc/ppc.h"
+
+#include "variant_db_detection.h"
+#include <zephyr/logging/log.h>
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
+
+LOG_MODULE_REGISTER(alt_dev_replacement);
+
+#define BOARD_VERSION_UNKNOWN 0xffffffff
+
+/* Check board version to decide which ppc/bc12 is used. */
+static bool board_has_syv_ppc(void)
+{
+	static uint32_t board_version = BOARD_VERSION_UNKNOWN;
+
+	if (board_version == BOARD_VERSION_UNKNOWN) {
+		if (cbi_get_board_version(&board_version) != EC_SUCCESS) {
+			LOG_ERR("Failed to get board version.");
+			board_version = 0;
+		}
+	}
+
+	return (board_version >= 3);
+}
+
+static void check_alternate_devices(void)
+{
+	/* Configure the PPC driver */
+	if (board_has_syv_ppc())
+		/* Arg is the USB port number */
+		PPC_ENABLE_ALTERNATE(0);
+}
+DECLARE_HOOK(HOOK_INIT, check_alternate_devices, HOOK_PRIO_DEFAULT);
+
+void bc12_interrupt(enum gpio_signal signal)
+{
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+}
+
+static void board_usbc_init(void)
+{
+	if (board_has_syv_ppc()) {
+		/* Enable PPC interrupts. */
+		gpio_enable_dt_interrupt(
+			GPIO_INT_FROM_NODELABEL(int_usb_c0_ppc));
+
+		/* Enable BC1.2 interrupts. */
+		gpio_enable_dt_interrupt(
+			GPIO_INT_FROM_NODELABEL(int_usb_c0_bc12));
+	} else {
+		gpio_enable_dt_interrupt(
+			GPIO_INT_FROM_NODELABEL(int_usb_c0_ppc));
+	}
+}
+DECLARE_HOOK(HOOK_INIT, board_usbc_init, HOOK_PRIO_POST_DEFAULT);
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	if (signal == GPIO_SIGNAL(DT_NODELABEL(usb_c0_ppc_int_odl))) {
+		if (board_has_syv_ppc()) {
+			syv682x_interrupt(0);
+		} else {
+			rt1739_interrupt(0);
+		}
+	}
+	if (signal == GPIO_SIGNAL(DT_ALIAS(gpio_usb_c1_ppc_int_odl))) {
+		syv682x_interrupt(1);
+	}
+}
+
+int ppc_get_alert_status(int port)
+{
+	if (port == 0) {
+		return gpio_pin_get_dt(
+			       GPIO_DT_FROM_NODELABEL(usb_c0_ppc_int_odl)) == 0;
+	}
+	if (port == 1 && corsola_get_db_type() == CORSOLA_DB_TYPEC) {
+		return gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(
+			       gpio_usb_c1_ppc_int_odl)) == 0;
+	}
+
+	return 0;
+}
+
+const struct cc_para_t *board_get_cc_tuning_parameter(enum usbpd_port port)
+{
+	const static struct cc_para_t
+		cc_parameter[CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT] = {
+			{
+				.rising_time =
+					IT83XX_TX_PRE_DRIVING_TIME_1_UNIT,
+				.falling_time =
+					IT83XX_TX_PRE_DRIVING_TIME_2_UNIT,
+			},
+			{
+				.rising_time =
+					IT83XX_TX_PRE_DRIVING_TIME_1_UNIT,
+				.falling_time =
+					IT83XX_TX_PRE_DRIVING_TIME_2_UNIT,
+			},
+		};
+
+	return &cc_parameter[port];
+}
+
+void board_overcurrent_event(int port, int is_overcurrented)
+{
+	/* TODO: check correct operation for Corsola */
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	/*
+	 * C0 & C1: TCPC is embedded in the EC and processes interrupts in the
+	 * chip code (it83xx/intc.c)
+	 */
+	return 0;
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * C0 & C1: TCPC is embedded in the EC and processes interrupts in the
+	 * chip code (it83xx/intc.c)
+	 */
+}
+
+int board_set_active_charge_port(int port)
+{
+	int i;
+	int is_valid_port = (port >= 0 && port < board_get_usb_pd_port_count());
+
+	if (!is_valid_port && port != CHARGE_PORT_NONE) {
+		return EC_ERROR_INVAL;
+	}
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTS("Disabling all charger ports");
+
+		/* Disable all ports. */
+		for (i = 0; i < ppc_cnt; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (ppc_vbus_sink_enable(i, 0)) {
+				CPRINTS("Disabling C%d as sink failed.", i);
+			}
+		}
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (ppc_is_sourcing_vbus(port)) {
+		CPRINTS("Skip enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTS("New charge port: C%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < ppc_cnt; i++) {
+		if (i == port) {
+			continue;
+		}
+
+		if (ppc_vbus_sink_enable(i, 0)) {
+			CPRINTS("C%d: sink path disable failed.", i);
+		}
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTS("C%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+#ifdef CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT
+enum adc_channel board_get_vbus_adc(int port)
+{
+	if (port == 0) {
+		return ADC_VBUS_C0;
+	}
+	if (port == 1) {
+		return ADC_VBUS_C1;
+	}
+	CPRINTSUSB("Unknown vbus adc port id: %d", port);
+	return ADC_VBUS_C0;
+}
+#endif /* CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT */
diff --git a/zephyr/projects/corsola/src/regulator.c b/zephyr/projects/corsola/src/regulator.c
deleted file mode 100644
index 35670bda82..0000000000
--- a/zephyr/projects/corsola/src/regulator.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "bc12/mt6360_public.h"
-
-/* SD Card */
-int board_regulator_get_info(uint32_t index, char *name,
-			     uint16_t *num_voltages, uint16_t *voltages_mv)
-{
-	enum mt6360_regulator_id id = index;
-
-	return mt6360_regulator_get_info(id, name, num_voltages,
-					 voltages_mv);
-}
-
-int board_regulator_enable(uint32_t index, uint8_t enable)
-{
-	enum mt6360_regulator_id id = index;
-
-	return mt6360_regulator_enable(id, enable);
-}
-
-int board_regulator_is_enabled(uint32_t index, uint8_t *enabled)
-{
-	enum mt6360_regulator_id id = index;
-
-	return mt6360_regulator_is_enabled(id, enabled);
-}
-
-int board_regulator_set_voltage(uint32_t index, uint32_t min_mv,
-				uint32_t max_mv)
-{
-	enum mt6360_regulator_id id = index;
-
-	return mt6360_regulator_set_voltage(id, min_mv, max_mv);
-}
-
-int board_regulator_get_voltage(uint32_t index, uint32_t *voltage_mv)
-{
-	enum mt6360_regulator_id id = index;
-
-	return mt6360_regulator_get_voltage(id, voltage_mv);
-}
diff --git a/zephyr/projects/corsola/src/usb_pd_policy.c b/zephyr/projects/corsola/src/usb_pd_policy.c
index c9015de776..6aa1381c1d 100644
--- a/zephyr/projects/corsola/src/usb_pd_policy.c
+++ b/zephyr/projects/corsola/src/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,8 +20,8 @@
 #error Corsola reference must have at least one 3.0 A port
 #endif
 
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
 
 static int active_aux_port = -1;
 
@@ -78,7 +78,6 @@ void svdm_set_hpd_gpio(int port, int en)
 	}
 }
 
-
 __override int svdm_dp_config(int port, uint32_t *payload)
 {
 	int opos = pd_alt_mode(port, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT);
@@ -101,11 +100,11 @@ __override int svdm_dp_config(int port, uint32_t *payload)
 	 *  (3) plug a monitor to the port-1 dongle.
 	 */
 
-	payload[0] = VDO(USB_SID_DISPLAYPORT, 1,
-			 CMD_DP_CONFIG | VDO_OPOS(opos));
-	payload[1] = VDO_DP_CFG(pin_mode,      /* pin mode */
-				1,             /* DPv1.3 signaling */
-				2);            /* UFP connected */
+	payload[0] =
+		VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_CONFIG | VDO_OPOS(opos));
+	payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */
+				1, /* DPv1.3 signaling */
+				2); /* UFP connected */
 	return 2;
 };
 
@@ -122,9 +121,9 @@ __override void svdm_dp_post_config(int port)
 	 */
 	if (port == active_aux_port) {
 		usb_mux_set(port, mux_mode, USB_SWITCH_CONNECT,
-			polarity_rm_dts(pd_get_polarity(port)));
+			    polarity_rm_dts(pd_get_polarity(port)));
 		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 	}
 
 	dp_flags[port] |= DP_FLAGS_DP_ON;
@@ -165,17 +164,14 @@ __override int svdm_dp_attention(int port, uint32_t *payload)
 	if (lvl) {
 		set_dp_aux_path_sel(port);
 
-		usb_mux_set(port, USB_PD_MUX_DOCK,
-			    USB_SWITCH_CONNECT,
+		usb_mux_set(port, USB_PD_MUX_DOCK, USB_SWITCH_CONNECT,
 			    polarity_rm_dts(pd_get_polarity(port)));
 	} else {
-		usb_mux_set(port, USB_PD_MUX_USB_ENABLED,
-			    USB_SWITCH_CONNECT,
+		usb_mux_set(port, USB_PD_MUX_USB_ENABLED, USB_SWITCH_CONNECT,
 			    polarity_rm_dts(pd_get_polarity(port)));
 	}
 
-	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
-	    (irq || lvl)) {
+	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && (irq || lvl)) {
 		/*
 		 * Wake up the AP.  IRQ or level high indicates a DP sink is now
 		 * present.
@@ -185,14 +181,6 @@ __override int svdm_dp_attention(int port, uint32_t *payload)
 		}
 	}
 
-	/* Its initial DP status message prior to config */
-	if (!(dp_flags[port] & DP_FLAGS_DP_ON)) {
-		if (lvl) {
-			dp_flags[port] |= DP_FLAGS_HPD_HI_PENDING;
-		}
-		return 1;
-	}
-
 #ifdef CONFIG_USB_PD_DP_HPD_GPIO
 	if (irq && !lvl) {
 		/*
diff --git a/zephyr/projects/corsola/src/usbc_config.c b/zephyr/projects/corsola/src/usbc_config.c
index 1f927dbc21..daf3e5a5cc 100644
--- a/zephyr/projects/corsola/src/usbc_config.c
+++ b/zephyr/projects/corsola/src/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -32,12 +32,13 @@
 #include "usb_mux.h"
 #include "usb_pd_tcpm.h"
 #include "usb_tc_sm.h"
+#include "usbc/usb_muxes.h"
 #include "usbc_ppc.h"
 
 #include "variant_db_detection.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
 /* a flag for indicating the tasks are inited. */
 static bool tasks_inited;
@@ -59,6 +60,8 @@ __override uint8_t board_get_usb_pd_port_count(void)
 		} else {
 			return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
 		}
+	} else if (corsola_get_db_type() == CORSOLA_DB_NONE) {
+		return CONFIG_USB_PD_PORT_MAX_COUNT - 1;
 	}
 
 	return CONFIG_USB_PD_PORT_MAX_COUNT;
@@ -67,9 +70,10 @@ __override uint8_t board_get_usb_pd_port_count(void)
 /* USB-A */
 void usb_a0_interrupt(enum gpio_signal signal)
 {
-	enum usb_charge_mode mode = gpio_pin_get_dt(
-		GPIO_DT_FROM_NODELABEL(gpio_ap_xhci_init_done)) ?
-		USB_CHARGE_MODE_ENABLED : USB_CHARGE_MODE_DISABLED;
+	enum usb_charge_mode mode = gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(
+					    gpio_ap_xhci_init_done)) ?
+					    USB_CHARGE_MODE_ENABLED :
+					    USB_CHARGE_MODE_DISABLED;
 
 	const int xhci_stat = gpio_get_level(signal);
 
@@ -96,16 +100,15 @@ void usb_a0_interrupt(enum gpio_signal signal)
 
 __override enum pd_dual_role_states pd_get_drp_state_in_s0(void)
 {
-	if (gpio_pin_get_dt(
-		GPIO_DT_FROM_NODELABEL(gpio_ap_xhci_init_done))) {
+	if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_ap_xhci_init_done))) {
 		return PD_DRP_TOGGLE_ON;
 	} else {
 		return PD_DRP_FORCE_SINK;
 	}
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	charge_set_input_current_limit(
 		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
@@ -127,8 +130,8 @@ int debounced_hpd;
 
 static void ps185_hdmi_hpd_deferred(void)
 {
-	const int new_hpd = gpio_pin_get_dt(
-				GPIO_DT_FROM_ALIAS(gpio_ps185_ec_dp_hpd));
+	const int new_hpd =
+		gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_ps185_ec_dp_hpd));
 
 	/* HPD status not changed, probably a glitch, just return. */
 	if (debounced_hpd == new_hpd) {
@@ -155,8 +158,7 @@ static void ps185_hdmi_hpd_deferred(void)
 				      0, /* power low?  ... no */
 				      (!!DP_FLAGS_DP_ON));
 		/* update C1 virtual mux */
-		usb_mux_set(USBC_PORT_C1,
-			    USB_PD_MUX_DP_ENABLED,
+		usb_mux_set(USBC_PORT_C1, USB_PD_MUX_DP_ENABLED,
 			    USB_SWITCH_DISCONNECT,
 			    0 /* polarity, don't care */);
 
@@ -171,8 +173,8 @@ DECLARE_DEFERRED(ps185_hdmi_hpd_deferred);
 
 static void ps185_hdmi_hpd_disconnect_deferred(void)
 {
-	const int new_hpd = gpio_pin_get_dt(
-				GPIO_DT_FROM_ALIAS(gpio_ps185_ec_dp_hpd));
+	const int new_hpd =
+		gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_ps185_ec_dp_hpd));
 
 	if (debounced_hpd == new_hpd && !new_hpd) {
 		dp_status[USBC_PORT_C1] =
@@ -188,7 +190,6 @@ static void ps185_hdmi_hpd_disconnect_deferred(void)
 			    USB_SWITCH_DISCONNECT,
 			    0 /* polarity, don't care */);
 	}
-
 }
 DECLARE_DEFERRED(ps185_hdmi_hpd_disconnect_deferred);
 
@@ -256,6 +257,11 @@ static void baseboard_x_ec_gpio2_init(void)
 	static struct tcpm_drv virtual_tcpc_drv = { 0 };
 	static struct bc12_drv virtual_bc12_drv = { 0 };
 
+	/* no sub board */
+	if (corsola_get_db_type() == CORSOLA_DB_NONE) {
+		return;
+	}
+
 	/* type-c: USB_C1_PPC_INT_ODL / hdmi: PS185_EC_DP_HPD */
 	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_x_ec_gpio2));
 
@@ -281,11 +287,7 @@ static void baseboard_x_ec_gpio2_init(void)
 	bc12_ports[USBC_PORT_C1] =
 		(const struct bc12_config){ .drv = &virtual_bc12_drv };
 	/* Use virtual mux to notify AP the mainlink direction. */
-	usb_muxes[USBC_PORT_C1] = (struct usb_mux){
-		.usb_port = USBC_PORT_C1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-	};
+	USB_MUX_ENABLE_ALTERNATIVE(usb_mux_chain_1_hdmi_db);
 
 	/*
 	 * If a HDMI DB is attached, C1 port tasks will be exiting in that
diff --git a/zephyr/projects/corsola/src/variant_db_detection.c b/zephyr/projects/corsola/src/variant_db_detection.c
index e5058bdcd5..6099d86bdd 100644
--- a/zephyr/projects/corsola/src/variant_db_detection.c
+++ b/zephyr/projects/corsola/src/variant_db_detection.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,13 +7,14 @@
 #include <zephyr/drivers/gpio.h>
 
 #include "console.h"
+#include "cros_cbi.h"
 #include "gpio/gpio_int.h"
 #include "hooks.h"
 
 #include "variant_db_detection.h"
 
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
 
 static void corsola_db_config(enum corsola_db_type type)
 {
@@ -21,7 +22,7 @@ static void corsola_db_config(enum corsola_db_type type)
 	case CORSOLA_DB_HDMI:
 		/* EC_X_GPIO1 */
 		gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_en_hdmi_pwr),
-				   GPIO_OUTPUT_HIGH);
+				      GPIO_OUTPUT_HIGH);
 		/* X_EC_GPIO2 */
 		gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_ps185_ec_dp_hpd),
 				      GPIO_INPUT);
@@ -29,7 +30,7 @@ static void corsola_db_config(enum corsola_db_type type)
 			GPIO_INT_FROM_NODELABEL(int_x_ec_gpio2));
 		/* EC_X_GPIO3 */
 		gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_ps185_pwrdn_odl),
-				     GPIO_OUTPUT_HIGH | GPIO_OPEN_DRAIN);
+				      GPIO_OUTPUT_HIGH | GPIO_OPEN_DRAIN);
 		return;
 	case CORSOLA_DB_TYPEC:
 		/* EC_X_GPIO1 */
@@ -42,9 +43,17 @@ static void corsola_db_config(enum corsola_db_type type)
 		gpio_enable_dt_interrupt(
 			GPIO_INT_FROM_NODELABEL(int_x_ec_gpio2));
 		/* EC_X_GPIO3 */
-		gpio_pin_configure_dt(
-			GPIO_DT_FROM_ALIAS(gpio_usb_c1_dp_in_hpd),
-			GPIO_OUTPUT_LOW);
+		gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_dp_in_hpd),
+				      GPIO_OUTPUT_LOW);
+		return;
+	case CORSOLA_DB_NONE:
+		/* Set floating pins as input with PU to prevent leakage */
+		gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_x_gpio1),
+				      GPIO_INPUT | GPIO_PULL_UP);
+		gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_x_ec_gpio2),
+				      GPIO_INPUT | GPIO_PULL_UP);
+		gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_x_gpio3),
+				      GPIO_INPUT | GPIO_PULL_UP);
 		return;
 	default:
 		break;
@@ -53,9 +62,13 @@ static void corsola_db_config(enum corsola_db_type type)
 
 enum corsola_db_type corsola_get_db_type(void)
 {
-	static enum corsola_db_type db = CORSOLA_DB_NONE;
+#if DT_NODE_EXISTS(DT_NODELABEL(db_config))
+	int ret;
+	uint32_t val;
+#endif
+	static enum corsola_db_type db = CORSOLA_DB_UNINIT;
 
-	if (db != CORSOLA_DB_NONE) {
+	if (db != CORSOLA_DB_UNINIT) {
 		return db;
 	}
 
@@ -65,9 +78,33 @@ enum corsola_db_type corsola_get_db_type(void)
 		db = CORSOLA_DB_TYPEC;
 	}
 
+/* Detect for no sub board case by FW_CONFIG */
+#if DT_NODE_EXISTS(DT_NODELABEL(db_config))
+	ret = cros_cbi_get_fw_config(DB, &val);
+	if (ret != 0) {
+		CPRINTS("Error retrieving CBI FW_CONFIG field %d", DB);
+	} else if (val == DB_NONE) {
+		db = CORSOLA_DB_NONE;
+	}
+#endif
+
 	corsola_db_config(db);
 
-	CPRINTS("Detect %s DB", db == CORSOLA_DB_HDMI ? "HDMI" : "TYPEC");
+	switch (db) {
+	case CORSOLA_DB_NONE:
+		CPRINTS("Detect %s DB", "NONE");
+		break;
+	case CORSOLA_DB_TYPEC:
+		CPRINTS("Detect %s DB", "TYPEC");
+		break;
+	case CORSOLA_DB_HDMI:
+		CPRINTS("Detect %s DB", "HDMI");
+		break;
+	default:
+		CPRINTS("DB UNINIT");
+		break;
+	}
+
 	return db;
 }
 
diff --git a/zephyr/projects/corsola/thermistor_tentacruel.dts b/zephyr/projects/corsola/thermistor_tentacruel.dts
new file mode 100644
index 0000000000..f9e5306f24
--- /dev/null
+++ b/zephyr/projects/corsola/thermistor_tentacruel.dts
@@ -0,0 +1,140 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	thermistor_rt9490: thermistor-rt9490 {
+		status = "okay";
+		compatible = "cros-ec,thermistor";
+		scaling-factor = <3>;
+		num-pairs = <21>;
+		steinhart-reference-mv = <4900>;
+		steinhart-reference-res = <10000>;
+
+		sample-datum-0 {
+			milivolt = <(731 / 3)>;
+			temp = <0>;
+			sample-index = <0>;
+		};
+
+		sample-datum-1 {
+			milivolt = <(708 / 3)>;
+			temp = <5>;
+			sample-index = <1>;
+		};
+
+		sample-datum-2 {
+			milivolt = <(682 / 3)>;
+			temp = <10>;
+			sample-index = <2>;
+		};
+
+		sample-datum-3 {
+			milivolt = <(653 / 3)>;
+			temp = <15>;
+			sample-index = <3>;
+		};
+
+		sample-datum-4 {
+			milivolt = <(622 / 3)>;
+			temp = <20>;
+			sample-index = <4>;
+		};
+
+		sample-datum-5 {
+			milivolt = <(589 / 3)>;
+			temp = <25>;
+			sample-index = <5>;
+		};
+
+		sample-datum-6 {
+			milivolt = <(554 / 3)>;
+			temp = <30>;
+			sample-index = <6>;
+		};
+
+		sample-datum-7 {
+			milivolt = <(519 / 3)>;
+			temp = <35>;
+			sample-index = <7>;
+		};
+
+		sample-datum-8 {
+			milivolt = <(483 / 3)>;
+			temp = <40>;
+			sample-index = <8>;
+		};
+
+		sample-datum-9 {
+			milivolt = <(446 / 3)>;
+			temp = <45>;
+			sample-index = <9>;
+		};
+
+		sample-datum-10 {
+			milivolt = <(411 / 3)>;
+			temp = <50>;
+			sample-index = <10>;
+		};
+		sample-datum-11 {
+			milivolt = <(376 / 3)>;
+			temp = <55>;
+			sample-index = <11>;
+		};
+
+		sample-datum-12 {
+			milivolt = <(343 / 3)>;
+			temp = <60>;
+			sample-index = <12>;
+		};
+
+		sample-datum-13 {
+			milivolt = <(312 / 3)>;
+			temp = <65>;
+			sample-index = <13>;
+		};
+
+		sample-datum-14 {
+			milivolt = <(284 / 3)>;
+			temp = <70>;
+			sample-index = <14>;
+		};
+
+		sample-datum-15 {
+			milivolt = <(257 / 3)>;
+			temp = <75>;
+			sample-index = <15>;
+		};
+
+		sample-datum-16 {
+			milivolt = <(232 / 3)>;
+			temp = <80>;
+			sample-index = <16>;
+		};
+
+		sample-datum-17 {
+			milivolt = <(209 / 3)>;
+			temp = <85>;
+			sample-index = <17>;
+		};
+
+		sample-datum-18 {
+			milivolt = <(188 / 3)>;
+			temp = <90>;
+			sample-index = <18>;
+		};
+
+		sample-datum-19 {
+			milivolt = <(169 / 3)>;
+			temp = <95>;
+			sample-index = <19>;
+		};
+
+		sample-datum-20 {
+			milivolt = <(152 / 3)>;
+			temp = <100>;
+			sample-index = <20>;
+		};
+	};
+};
diff --git a/zephyr/projects/corsola/usba.dts b/zephyr/projects/corsola/usba.dts
index 13c900b1b6..2ecb3b7d5a 100644
--- a/zephyr/projects/corsola/usba.dts
+++ b/zephyr/projects/corsola/usba.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/corsola/usba_steelix.dts b/zephyr/projects/corsola/usba_steelix.dts
index 0671457fe9..0ddd67f664 100644
--- a/zephyr/projects/corsola/usba_steelix.dts
+++ b/zephyr/projects/corsola/usba_steelix.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/corsola/usbc_kingler.dts b/zephyr/projects/corsola/usbc_kingler.dts
index 6703498ad5..18bc6ce303 100644
--- a/zephyr/projects/corsola/usbc_kingler.dts
+++ b/zephyr/projects/corsola/usbc_kingler.dts
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,23 +8,49 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		/* TODO(b/227359727): kingler: convert USB-C configuration to
-		 * devicetree
-		 */
 		port0@0 {
 			compatible = "named-usbc-port";
 			reg = <0>;
+			bc12 = <&bc12_port0>;
+			tcpc = <&tcpc_port0>;
+			ppc = <&ppc_port0>;
+			chg = <&charger>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&anx7447_mux_0 &virtual_mux_0>;
+			};
+		};
 
-			chg {
-				compatible = "intersil,isl923x";
-				status = "okay";
-				port = <&i2c_charger>;
+		port0-muxes {
+			anx7447_mux_0: anx7447-mux-0 {
+				compatible = "analogix,usbc-mux-anx7447";
+			};
+			virtual_mux_0: virtual-mux-0 {
+				compatible = "cros-ec,usbc-mux-virtual";
 			};
 		};
 
 		port1@1 {
 			compatible = "named-usbc-port";
 			reg = <1>;
+			bc12 = <&bc12_port1>;
+			tcpc = <&tcpc_port1>;
+			ppc = <&ppc_port1>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&ps8743_mux_1 &virtual_mux_1>;
+			};
+			usb_mux_chain_1_hdmi_db: usb-mux-chain-1-hdmi-db {
+				compatible = "cros-ec,usb-mux-chain";
+				alternative-chain;
+				usb-muxes = <&virtual_mux_1>;
+			};
+		};
+
+		port1-muxes {
+			virtual_mux_1: virtual-mux-1 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
 		};
 	};
 };
diff --git a/zephyr/projects/corsola/usbc_krabby.dts b/zephyr/projects/corsola/usbc_krabby.dts
index 2156782dbc..a72864da35 100644
--- a/zephyr/projects/corsola/usbc_krabby.dts
+++ b/zephyr/projects/corsola/usbc_krabby.dts
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,32 +11,16 @@
 		port0@0 {
 			compatible = "named-usbc-port";
 			reg = <0>;
-			bc12 {
-				compatible = "richtek,rt1739-bc12";
-				status = "okay";
+			bc12 = <&bc12_ppc_port0>;
+			ppc = <&bc12_ppc_port0>;
+			tcpc = <&usbpd0>;
+			chg = <&charger>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&it5205_mux_0 &virtual_mux_0>;
 			};
-			ppc {
-				compatible = "richtek,rt1739-ppc";
-				status = "okay";
-				port = <&i2c_usb_c0>;
-				i2c-addr-flags = "RT1739_ADDR1_FLAGS";
-			};
-			tcpc {
-				compatible = "ite,it8xxx2-tcpc";
-			};
-			chg {
-				compatible = "richtek,rt9490";
-				status = "okay";
-				port = <&i2c_charger>;
-			};
-			usb-muxes = <&it5205_mux_0 &virtual_mux_0>;
 		};
 		port0-muxes {
-			it5205_mux_0: it5205-mux-0 {
-				compatible = "ite,it5205";
-				port = <&i2c_usb_mux0>;
-				i2c-addr-flags = "IT5205_I2C_ADDR1_FLAGS";
-			};
 			virtual_mux_0: virtual-mux-0 {
 				compatible = "cros-ec,usbc-mux-virtual";
 			};
@@ -45,32 +29,31 @@
 		port1@1 {
 			compatible = "named-usbc-port";
 			reg = <1>;
-			bc12 {
-				compatible = "richtek,rt9490-bc12";
-				status = "okay";
-				irq = <&int_usb_c1_bc12_charger>;
-			};
-			ppc {
-				compatible = "silergy,syv682x";
-				status = "okay";
-				port = <&i2c_usb_c1>;
-				i2c-addr-flags = "SYV682X_ADDR0_FLAGS";
-				frs_en_gpio = <&gpio_ec_x_gpio1>;
-			};
-			tcpc {
-				compatible = "ite,it8xxx2-tcpc";
+			bc12 = <&bc12_port1>;
+			ppc = <&ppc_port1>;
+			tcpc = <&usbpd1>;
+			usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&tusb1064_mux_1 &virtual_mux_1>;
+			};
+			usb_mux_chain_1_hdmi_db: usb-mux-chain-1-hdmi-db {
+				compatible = "cros-ec,usb-mux-chain";
+				alternative-chain;
+				usb-muxes = <&virtual_mux_1>;
 			};
-			usb-muxes = <&tusb1064_mux_1 &virtual_mux_1>;
 		};
 		port1-muxes {
-			tusb1064_mux_1: tusb1064-mux-1 {
-				compatible = "ti,tusb1064";
-				port = <&i2c_usb_mux1>;
-				i2c-addr-flags = "TUSB1064_I2C_ADDR0_FLAGS";
-			};
 			virtual_mux_1: virtual-mux-1 {
 				compatible = "cros-ec,usbc-mux-virtual";
 			};
 		};
 	};
 };
+
+&usbpd0 {
+	status = "okay";
+};
+
+&usbpd1 {
+	status = "okay";
+};
diff --git a/zephyr/projects/corsola/usbc_magikarp.dts b/zephyr/projects/corsola/usbc_magikarp.dts
new file mode 100644
index 0000000000..0e0473cd86
--- /dev/null
+++ b/zephyr/projects/corsola/usbc_magikarp.dts
@@ -0,0 +1,59 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+			bc12 = <&bc12_ppc_port0>;
+			ppc = <&bc12_ppc_port0>;
+			tcpc = <&usbpd0>;
+			chg = <&charger>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&it5205_mux_0 &virtual_mux_0>;
+			};
+		};
+		port0-muxes {
+			virtual_mux_0: virtual-mux-0 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+
+		port1@1 {
+			compatible = "named-usbc-port";
+			reg = <1>;
+			bc12 = <&bc12_port1>;
+			ppc = <&ppc_port1>;
+			tcpc = <&usbpd1>;
+			usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&ps8743_mux_1 &virtual_mux_1>;
+			};
+			usb_mux_chain_1_hdmi_db: usb-mux-chain-1-hdmi-db {
+				compatible = "cros-ec,usb-mux-chain";
+				alternative-chain;
+				usb-muxes = <&virtual_mux_1>;
+			};
+		};
+		port1-muxes {
+			virtual_mux_1: virtual-mux-1 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+	};
+};
+
+&usbpd0 {
+	status = "okay";
+};
+
+&usbpd1 {
+	status = "okay";
+};
diff --git a/zephyr/projects/corsola/usbc_tentacruel.dts b/zephyr/projects/corsola/usbc_tentacruel.dts
new file mode 100644
index 0000000000..bb105a8e08
--- /dev/null
+++ b/zephyr/projects/corsola/usbc_tentacruel.dts
@@ -0,0 +1,60 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+			bc12 = <&bc12_port0>;
+			ppc = <&bc12_ppc_port0>;
+			ppc_alt = <&ppc_port0>;
+			tcpc = <&usbpd0>;
+			chg = <&charger>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&it5205_mux_0 &virtual_mux_0>;
+			};
+		};
+		port0-muxes {
+			virtual_mux_0: virtual-mux-0 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+
+		port1@1 {
+			compatible = "named-usbc-port";
+			reg = <1>;
+			bc12 = <&bc12_port1>;
+			ppc = <&ppc_port1>;
+			tcpc = <&usbpd1>;
+			usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&ps8743_mux_1 &virtual_mux_1>;
+			};
+			usb_mux_chain_1_hdmi_db: usb-mux-chain-1-hdmi-db {
+				compatible = "cros-ec,usb-mux-chain";
+				alternative-chain;
+				usb-muxes = <&virtual_mux_1>;
+			};
+		};
+		port1-muxes {
+			virtual_mux_1: virtual-mux-1 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+	};
+};
+
+&usbpd0 {
+	status = "okay";
+};
+
+&usbpd1 {
+	status = "okay";
+};
diff --git a/zephyr/projects/herobrine/BUILD.py b/zephyr/projects/herobrine/BUILD.py
index 2a15441c55..b8bbdb0ce7 100644
--- a/zephyr/projects/herobrine/BUILD.py
+++ b/zephyr/projects/herobrine/BUILD.py
@@ -1,11 +1,13 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 """Define zmake projects for herobrine."""
 
 
-def register_variant(project_name, extra_dts_overlays=(), extra_kconfig_files=()):
+def register_variant(
+    project_name, extra_dts_overlays=(), extra_kconfig_files=()
+):
     """Register a variant of herobrine."""
     register_npcx_project(
         project_name=project_name,
@@ -14,7 +16,6 @@ def register_variant(project_name, extra_dts_overlays=(), extra_kconfig_files=()
             # Common to all projects.
             here / "adc.dts",
             here / "common.dts",
-            here / "i2c.dts",
             here / "interrupts.dts",
             here / "keyboard.dts",
             here / "default_gpio_pinctrl.dts",
@@ -31,11 +32,28 @@ def register_variant(project_name, extra_dts_overlays=(), extra_kconfig_files=()
 
 
 register_variant(
+    project_name="evoker",
+    extra_dts_overlays=[
+        here / "display.dts",
+        here / "battery_evoker.dts",
+        here / "gpio_evoker.dts",
+        here / "i2c_evoker.dts",
+        here / "led_pins_evoker.dts",
+        here / "led_policy_evoker.dts",
+        here / "motionsense_evoker.dts",
+        here / "switchcap.dts",
+        here / "usbc_evoker.dts",
+    ],
+    extra_kconfig_files=[here / "prj_evoker.conf"],
+)
+
+register_variant(
     project_name="herobrine",
     extra_dts_overlays=[
         here / "display.dts",
         here / "battery_herobrine.dts",
         here / "gpio.dts",
+        here / "i2c_herobrine.dts",
         here / "led_pins_herobrine.dts",
         here / "led_policy_herobrine.dts",
         here / "motionsense.dts",
@@ -45,12 +63,12 @@ register_variant(
     extra_kconfig_files=[here / "prj_herobrine.conf"],
 )
 
-
 register_variant(
     project_name="hoglin",
     extra_dts_overlays=[
         here / "battery_hoglin.dts",
         here / "gpio_hoglin.dts",
+        here / "i2c_hoglin.dts",
         here / "led_pins_hoglin.dts",
         here / "led_policy_hoglin.dts",
         here / "motionsense_hoglin.dts",
@@ -60,12 +78,12 @@ register_variant(
     extra_kconfig_files=[here / "prj_hoglin.conf"],
 )
 
-
 register_variant(
     project_name="villager",
     extra_dts_overlays=[
         here / "battery_villager.dts",
         here / "gpio_villager.dts",
+        here / "i2c_villager.dts",
         here / "led_pins_villager.dts",
         here / "led_policy_villager.dts",
         here / "motionsense_villager.dts",
@@ -74,3 +92,18 @@ register_variant(
     ],
     extra_kconfig_files=[here / "prj_villager.conf"],
 )
+
+register_variant(
+    project_name="zoglin",
+    extra_dts_overlays=[
+        here / "battery_hoglin.dts",
+        here / "gpio_hoglin.dts",
+        here / "i2c_hoglin.dts",
+        here / "led_pins_hoglin.dts",
+        here / "led_policy_hoglin.dts",
+        here / "motionsense_hoglin.dts",
+        here / "switchcap_hoglin.dts",
+        here / "usbc_hoglin.dts",
+    ],
+    extra_kconfig_files=[here / "prj_zoglin.conf"],
+)
diff --git a/zephyr/projects/herobrine/CMakeLists.txt b/zephyr/projects/herobrine/CMakeLists.txt
index 537fa5ef68..75aae3419e 100644
--- a/zephyr/projects/herobrine/CMakeLists.txt
+++ b/zephyr/projects/herobrine/CMakeLists.txt
@@ -1,13 +1,18 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 cmake_minimum_required(VERSION 3.13.1)
 
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
 
 cros_ec_library_include_directories(include)
 
+# Common Herobrine implementation
+zephyr_library_sources(
+  "src/board_chipset.c"
+)
+
 # Board specific implementation
 zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC
   "src/usbc_config.c"
@@ -15,7 +20,9 @@ zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC
 zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_I2C
   "src/i2c.c")
 
-if(DEFINED CONFIG_BOARD_HEROBRINE)
+if(DEFINED CONFIG_BOARD_EVOKER)
+	project(evoker)
+elseif(DEFINED CONFIG_BOARD_HEROBRINE)
 	project(herobrine)
 	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC
 	  "src/herobrine/alt_dev_replacement.c")
@@ -23,4 +30,6 @@ elseif(DEFINED CONFIG_BOARD_HOGLIN)
 	project(hoglin)
 elseif(DEFINED CONFIG_BOARD_VILLAGER)
 	project(villager)
+elseif(DEFINED CONFIG_BOARD_ZOGLIN)
+	project(zoglin)
 endif()
diff --git a/zephyr/projects/herobrine/Kconfig b/zephyr/projects/herobrine/Kconfig
index 902e81a49a..383d5a08ee 100644
--- a/zephyr/projects/herobrine/Kconfig
+++ b/zephyr/projects/herobrine/Kconfig
@@ -1,7 +1,13 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
+config BOARD_EVOKER
+	bool "Evoker Board"
+	help
+	  Build the Evoker board. The board is based on the Herobrine
+	  reference design.
+
 config BOARD_HEROBRINE
 	bool "Google Herobrine Baseboard"
 	help
@@ -20,4 +26,10 @@ config BOARD_VILLAGER
 	  Build the Villager board. The board is based on the Herobrine
 	  reference design.
 
+config BOARD_ZOGLIN
+	bool "Qualcomm Zoglin Baseboard"
+	help
+	  Build Qualcomm Zoglin reference board.  The board uses Nuvoton
+	  NPCX9 chip as the EC.
+
 source "Kconfig.zephyr"
diff --git a/zephyr/projects/herobrine/adc.dts b/zephyr/projects/herobrine/adc.dts
index bbb50cccab..16a5434e9d 100644
--- a/zephyr/projects/herobrine/adc.dts
+++ b/zephyr/projects/herobrine/adc.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,14 +10,12 @@
 		compatible = "named-adc-channels";
 
 		vbus {
-			label = "VBUS";
 			enum-name = "ADC_VBUS";
 			io-channels = <&adc0 1>;
 			/* Measure VBUS through a 1/10 voltage divider */
 			mul = <10>;
 		};
 		amon_bmon {
-			label = "AMON_BMON";
 			enum-name = "ADC_AMON_BMON";
 			io-channels = <&adc0 2>;
 			/*
@@ -29,7 +27,6 @@
 			div = <18>;
 		};
 		psys {
-			label = "PSYS";
 			enum-name = "ADC_PSYS";
 			io-channels = <&adc0 3>;
 			/*
diff --git a/zephyr/projects/herobrine/battery_evoker.dts b/zephyr/projects/herobrine/battery_evoker.dts
new file mode 100644
index 0000000000..0e09616c1d
--- /dev/null
+++ b/zephyr/projects/herobrine/battery_evoker.dts
@@ -0,0 +1,15 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	batteries {
+		default_battery: pc_vp_bp153 {
+			compatible = "smp,pc-vp-bp153", "battery-smart";
+		};
+		ap16l5j {
+			compatible = "panasonic,ap16l5j", "battery-smart";
+		};
+	};
+};
diff --git a/zephyr/projects/herobrine/battery_herobrine.dts b/zephyr/projects/herobrine/battery_herobrine.dts
index 764c3fb5ed..b347ec4c3c 100644
--- a/zephyr/projects/herobrine/battery_herobrine.dts
+++ b/zephyr/projects/herobrine/battery_herobrine.dts
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/herobrine/battery_hoglin.dts b/zephyr/projects/herobrine/battery_hoglin.dts
index 79fc6ca296..11180c3988 100644
--- a/zephyr/projects/herobrine/battery_hoglin.dts
+++ b/zephyr/projects/herobrine/battery_hoglin.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/herobrine/battery_villager.dts b/zephyr/projects/herobrine/battery_villager.dts
index 2fe9a93774..dafd473a6e 100644
--- a/zephyr/projects/herobrine/battery_villager.dts
+++ b/zephyr/projects/herobrine/battery_villager.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/herobrine/common.dts b/zephyr/projects/herobrine/common.dts
index aeb99c5377..a722f1dfa2 100644
--- a/zephyr/projects/herobrine/common.dts
+++ b/zephyr/projects/herobrine/common.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/herobrine/default_gpio_pinctrl.dts b/zephyr/projects/herobrine/default_gpio_pinctrl.dts
index d25b388726..604658a145 100644
--- a/zephyr/projects/herobrine/default_gpio_pinctrl.dts
+++ b/zephyr/projects/herobrine/default_gpio_pinctrl.dts
@@ -1,44 +1,44 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Adds the &alt1_no_lpc_espi setting over the NPCX9 default setting. */
 &{/def-io-conf-list} {
-	pinctrl-0 = <&alt0_gpio_no_spip
-		   &alt0_gpio_no_fpip
-		   &alt1_no_pwrgd
-		   &alt1_no_lpc_espi
-		   &alta_no_peci_en
-		   &altd_npsl_in1_sl
-		   &altd_npsl_in2_sl
-		   &altd_psl_in3_sl
-		   &altd_psl_in4_sl
-		   &alt7_no_ksi0_sl
-		   &alt7_no_ksi1_sl
-		   &alt7_no_ksi2_sl
-		   &alt7_no_ksi3_sl
-		   &alt7_no_ksi4_sl
-		   &alt7_no_ksi5_sl
-		   &alt7_no_ksi6_sl
-		   &alt7_no_ksi7_sl
-		   &alt8_no_kso00_sl
-		   &alt8_no_kso01_sl
-		   &alt8_no_kso02_sl
-		   &alt8_no_kso03_sl
-		   &alt8_no_kso04_sl
-		   &alt8_no_kso05_sl
-		   &alt8_no_kso06_sl
-		   &alt8_no_kso07_sl
-		   &alt9_no_kso08_sl
-		   &alt9_no_kso09_sl
-		   &alt9_no_kso10_sl
-		   &alt9_no_kso11_sl
-		   &alt9_no_kso12_sl
-		   &alt9_no_kso13_sl
-		   &alt9_no_kso14_sl
-		   &alt9_no_kso15_sl
-		   &alta_no_kso16_sl
-		   &alta_no_kso17_sl
-		   &altg_psl_gpo_sl>;
+	pinmux = <&alt0_gpio_no_spip
+		  &alt0_gpio_no_fpip
+		  &alt1_no_pwrgd
+		  &alt1_no_lpc_espi
+		  &alta_no_peci_en
+		  &altd_npsl_in1_sl
+		  &altd_npsl_in2_sl
+		  &altd_psl_in3_sl
+		  &altd_psl_in4_sl
+		  &alt7_no_ksi0_sl
+		  &alt7_no_ksi1_sl
+		  &alt7_no_ksi2_sl
+		  &alt7_no_ksi3_sl
+		  &alt7_no_ksi4_sl
+		  &alt7_no_ksi5_sl
+		  &alt7_no_ksi6_sl
+		  &alt7_no_ksi7_sl
+		  &alt8_no_kso00_sl
+		  &alt8_no_kso01_sl
+		  &alt8_no_kso02_sl
+		  &alt8_no_kso03_sl
+		  &alt8_no_kso04_sl
+		  &alt8_no_kso05_sl
+		  &alt8_no_kso06_sl
+		  &alt8_no_kso07_sl
+		  &alt9_no_kso08_sl
+		  &alt9_no_kso09_sl
+		  &alt9_no_kso10_sl
+		  &alt9_no_kso11_sl
+		  &alt9_no_kso12_sl
+		  &alt9_no_kso13_sl
+		  &alt9_no_kso14_sl
+		  &alt9_no_kso15_sl
+		  &alta_no_kso16_sl
+		  &alta_no_kso17_sl
+		  &altg_psl_gpo_sl>;
 };
diff --git a/zephyr/projects/herobrine/display.dts b/zephyr/projects/herobrine/display.dts
index 6f28e7e81a..65d3a2d91b 100644
--- a/zephyr/projects/herobrine/display.dts
+++ b/zephyr/projects/herobrine/display.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,7 +7,6 @@
 	displight {
 		compatible = "cros-ec,displight";
 		pwms = <&pwm5 0 PWM_HZ(4800) PWM_POLARITY_NORMAL>;
-		frequency = <4800>;
 		generic-pwm-channel = <1>;
 	};
 };
diff --git a/zephyr/projects/herobrine/gpio.dts b/zephyr/projects/herobrine/gpio.dts
index ba958150e0..a355aaf099 100644
--- a/zephyr/projects/herobrine/gpio.dts
+++ b/zephyr/projects/herobrine/gpio.dts
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -227,6 +227,12 @@
 		arm_x86 {
 			gpios = <&gpio6 6 GPIO_OUTPUT_LOW>;
 		};
+		ec-i2c-sensor-scl {
+			gpios = <&gpiob 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		ec-i2c-sensor-sda {
+			gpios = <&gpiob 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
 		gpio_ec_kso_02_inv: ec_kso_02_inv {
 			gpios = <&gpio1 7 (GPIO_OUTPUT_LOW | GPIO_ACTIVE_LOW)>;
 		};
@@ -237,20 +243,6 @@
 		enable-pins = <&gpio_en_usb_a_5v>;
 	};
 
-	def-lvol-io-list {
-		compatible = "nuvoton,npcx-lvolctrl-def";
-		lvol-io-pads = <
-			&lvol_iob3 /* EC_I2C_SENSOR_SCL */
-			&lvol_iob2 /* EC_I2C_SENSOR_SDA */
-		>;
-	};
-
-	vsby-psl-in-list {
-		/* Use PSL_IN1/2/3/4 as detection pins from hibernate mode */
-		psl-in-pads = <&psl_in1 &psl_in2 &psl_in3 &psl_in4>;
-		status = "okay";
-	};
-
 	sku {
 		compatible = "cros-ec,gpio-id";
 
@@ -305,22 +297,33 @@
 };
 
 /* Power switch logic input pads */
-&psl_in1 {
+&psl_in1_gpd2 {
 	/* ACOK_OD */
-	flag = <NPCX_PSL_RISING_EDGE>;
+	psl-in-mode = "edge";
+	psl-in-pol = "high-rising";
 };
 
-&psl_in2 {
+&psl_in2_gp00 {
 	/* EC_PWR_BTN_ODL */
-	flag = <NPCX_PSL_FALLING_EDGE>;
+	psl-in-mode = "edge";
+	psl-in-pol = "low-falling";
 };
 
-&psl_in3 {
+&psl_in3_gp01 {
 	/* LID_OPEN_EC */
-	flag = <NPCX_PSL_RISING_EDGE>;
+	psl-in-mode = "edge";
+	psl-in-pol = "high-rising";
 };
 
-&psl_in4 {
+&psl_in4_gp02 {
 	/* RTC_EC_WAKE_ODL */
-	flag = <NPCX_PSL_FALLING_EDGE>;
+	psl-in-mode = "edge";
+	psl-in-pol = "low-falling";
 };
+
+/* Power domain device controlled by PSL (Power Switch Logic) IO pads */
+&power_ctrl_psl {
+	status = "okay";
+	pinctrl-names = "sleep";
+	pinctrl-0 = <&psl_in1_gpd2 &psl_in2_gp00 &psl_in3_gp01 &psl_in4_gp02>;
+};
\ No newline at end of file
diff --git a/zephyr/projects/herobrine/gpio_evoker.dts b/zephyr/projects/herobrine/gpio_evoker.dts
new file mode 100644
index 0000000000..c27cfba47d
--- /dev/null
+++ b/zephyr/projects/herobrine/gpio_evoker.dts
@@ -0,0 +1,327 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	aliases {
+		gpio-wp = &gpio_ec_wp_odl;
+		gpio-kbd-kso2 = &gpio_ec_kso_02_inv;
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		gpio_usb_c0_pd_int_odl: usb_c0_pd_int_odl {
+			gpios = <&gpioe 0 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C0_PD_INT_ODL";
+		};
+		gpio_usb_c1_pd_int_odl: usb_c1_pd_int_odl {
+			gpios = <&gpiof 5 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C1_PD_INT_ODL";
+		};
+		gpio_usb_c0_swctl_int_odl: usb_c0_swctl_int_odl {
+			gpios = <&gpio0 3 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C0_SWCTL_INT_ODL";
+		};
+		gpio_usb_c1_swctl_int_odl: usb_c1_swctl_int_odl {
+			gpios = <&gpio4 0 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C1_SWCTL_INT_ODL";
+		};
+		gpio_usb_c0_bc12_int_l: usb_c0_bc12_int_l {
+			gpios = <&gpio6 1 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_usb_c1_bc12_int_l: usb_c1_bc12_int_l {
+			gpios = <&gpio8 2 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_usb_a0_oc_odl: usb_a0_oc_odl {
+			gpios = <&gpiof 4 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_chg_acok_od: chg_acok_od {
+			gpios = <&gpiod 2 GPIO_INPUT>;
+			enum-name = "GPIO_AC_PRESENT";
+		};
+		gpio_ec_pwr_btn_odl: ec_pwr_btn_odl {
+			gpios = <&gpio0 0 GPIO_INPUT>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		gpio_ec_voldn_btn_odl: ec_voldn_btn_odl {
+			gpios = <&gpio6 2 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_DOWN_L";
+		};
+		gpio_ec_volup_btn_odl: ec_volup_btn_odl {
+			gpios = <&gpioc 2 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_UP_L";
+		};
+		gpio_ec_wp_odl: ec_wp_odl {
+			gpios = <&gpiod 3 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_lid_open_ec: lid_open_ec {
+			gpios = <&gpio0 1 GPIO_INPUT>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+		gpio_ap_rst_l: ap_rst_l {
+			gpios = <&gpio5 1 GPIO_INPUT>;
+			enum-name = "GPIO_AP_RST_L";
+		};
+		gpio_ps_hold: ps_hold {
+			gpios = <&gpioa 6 GPIO_INPUT_PULL_DOWN>;
+			enum-name = "GPIO_PS_HOLD";
+		};
+		gpio_ap_suspend: ap_suspend {
+			gpios = <&gpio5 7 GPIO_INPUT>;
+			enum-name = "GPIO_AP_SUSPEND";
+		};
+		gpio_mb_power_good: mb_power_good {
+			gpios = <&gpio3 7 GPIO_INPUT_PULL_DOWN>;
+			enum-name = "GPIO_POWER_GOOD";
+		};
+		gpio_warm_reset_l: warm_reset_l {
+			gpios = <&gpiob 0 GPIO_INPUT>;
+			enum-name = "GPIO_WARM_RESET_L";
+		};
+		ap_ec_spi_cs_l {
+			gpios = <&gpio5 3 GPIO_INPUT_PULL_DOWN>;
+		};
+		gpio_tablet_mode_l: tablet_mode_l {
+			gpios = <&gpioc 6 GPIO_INPUT>;
+			enum-name = "GPIO_TABLET_MODE_L";
+		};
+		gpio_accel_gyro_int_l: accel_gyro_int_l {
+			gpios = <&gpioa 3 GPIO_INPUT>;
+		};
+		gpio_rtc_ec_wake_odl: rtc_ec_wake_odl {
+			gpios = <&gpio0 2 GPIO_INPUT>;
+		};
+		ec_entering_rw {
+			gpios = <&gpio7 2 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_ENTERING_RW";
+		};
+		ccd_mode_odl {
+			gpios = <&gpio6 3 GPIO_INPUT>;
+			enum-name = "GPIO_CCD_MODE_ODL";
+		};
+		ec_batt_pres_odl {
+			gpios = <&gpioe 5 GPIO_INPUT>;
+			enum-name = "GPIO_BATT_PRES_ODL";
+		};
+		ec_gsc_packet_mode {
+			gpios = <&gpio8 3 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_PACKET_MODE_EN";
+		};
+		pmic_resin_l {
+			gpios = <&gpioa 0 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_PMIC_RESIN_L";
+		};
+		pmic_kpd_pwr_odl {
+			gpios = <&gpioa 2 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_PMIC_KPD_PWR_ODL";
+		};
+		ap_ec_int_l {
+			gpios = <&gpio5 6 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_EC_INT_L";
+		};
+		gpio_switchcap_on: switchcap_on {
+			gpios = <&gpiod 5 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_SWITCHCAP_ON";
+		};
+		gpio_en_pp5000_s5: en_pp5000_s5 {
+			gpios = <&gpio7 3 GPIO_OUTPUT_HIGH>;
+			enum-name = "GPIO_EN_PP5000";
+		};
+		ec_bl_disable_l {
+			/* Enable EC-controlled backlight;
+			 * disable it initially.
+			 */
+			gpios = <&gpiob 6 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_ENABLE_BACKLIGHT";
+		};
+		lid_accel_int_l {
+			gpios = <&gpioa 1 GPIO_INPUT>;
+		};
+		tp_int_gate {
+			gpios = <&gpio7 4 GPIO_OUTPUT_LOW>;
+		};
+		gpio_usb_c0_pd_rst_l: usb_c0_pd_rst_l {
+			gpios = <&gpiof 1 GPIO_OUTPUT_HIGH>;
+		};
+		gpio_usb_c1_pd_rst_l: usb_c1_pd_rst_l {
+			gpios = <&gpioe 4 GPIO_OUTPUT_HIGH>;
+		};
+		gpio_dp_mux_oe_l: dp_mux_oe_l {
+			gpios = <&gpiob 1 GPIO_ODR_HIGH>;
+		};
+		gpio_dp_mux_sel: dp_mux_sel {
+			gpios = <&gpio4 5 GPIO_OUTPUT_LOW>;
+		};
+		gpio_dp_hot_plug_det_r: dp_hot_plug_det_r {
+			gpios = <&gpio9 5 GPIO_OUTPUT_LOW>;
+		};
+		gpio_en_usb_a_5v: en_usb_a_5v {
+			gpios = <&gpiof 0 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_EN_USB_A_5V";
+		};
+		usb_a_cdp_ilim_en_l {
+			gpios = <&gpio7 5 GPIO_OUTPUT_HIGH>;
+		};
+		gpio_usb_c0_frs_en: usb_c0_frs_en {
+			gpios = <&gpioc 5 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_USB_C0_FRS_EN";
+		};
+		gpio_usb_c1_frs_en: usb_c1_frs_en {
+			gpios = <&gpioc 1 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_USB_C1_FRS_EN";
+		};
+		gpio_ec_chg_led_y_c0: ec_chg_led_y_c0 {
+			#led-pin-cells = <1>;
+			gpios = <&gpio6 0 GPIO_OUTPUT_LOW>;
+		};
+		gpio_ec_chg_led_w_c0: ec_chg_led_w_c0 {
+			#led-pin-cells = <1>;
+			gpios = <&gpioc 0 GPIO_OUTPUT_LOW>;
+		};
+		gpio_ec_chg_led_w_c1: ec_chg_led_w_c1 {
+			#led-pin-cells = <1>;
+			gpios = <&gpioc 3 GPIO_OUTPUT_LOW>;
+		};
+		gpio_ec_chg_led_r_c0: ec_chg_led_r_c0 {
+			#led-pin-cells = <1>;
+			gpios = <&gpioc 4 GPIO_OUTPUT_LOW>;
+		};
+		ap_ec_spi_mosi {
+			gpios = <&gpio4 6 GPIO_INPUT_PULL_DOWN>;
+		};
+		ap_ec_spi_miso {
+			gpios = <&gpio4 7 GPIO_INPUT_PULL_DOWN>;
+		};
+		ap_ec_spi_clk {
+			gpios = <&gpio5 5 GPIO_INPUT_PULL_DOWN>;
+		};
+		gpio_brd_id0: brd_id0 {
+			gpios = <&gpio9 4 GPIO_INPUT>;
+			enum-name = "GPIO_BOARD_VERSION1";
+		};
+		gpio_brd_id1: brd_id1 {
+			gpios = <&gpio9 7 GPIO_INPUT>;
+			enum-name = "GPIO_BOARD_VERSION2";
+		};
+		gpio_brd_id2: brd_id2 {
+			gpios = <&gpioa 5 GPIO_INPUT>;
+			enum-name = "GPIO_BOARD_VERSION3";
+		};
+		gpio_sku_id0: sku_id0 {
+			gpios = <&gpio6 7 GPIO_INPUT>;
+		};
+		gpio_sku_id1: sku_id1 {
+			gpios = <&gpio7 0 GPIO_INPUT>;
+		};
+		gpio_sku_id2: sku_id2 {
+			gpios = <&gpioe 1 GPIO_INPUT>;
+		};
+		gpio_switchcap_pg: src_vph_pwr_pg {
+			gpios = <&gpioe 2 GPIO_INPUT_PULL_DOWN>;
+			enum-name = "GPIO_SWITCHCAP_PG";
+		};
+		arm_x86 {
+			gpios = <&gpio6 6 GPIO_OUTPUT_LOW>;
+		};
+		ec-i2c-sensor-scl {
+			gpios = <&gpiob 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		ec-i2c-sensor-sda {
+			gpios = <&gpiob 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		gpio_ec_kso_02_inv: ec_kso_02_inv {
+			gpios = <&gpio1 7 (GPIO_OUTPUT_LOW | GPIO_ACTIVE_LOW)>;
+		};
+	};
+
+	usba-port-enable-list {
+		compatible = "cros-ec,usba-port-enable-pins";
+		enable-pins = <&gpio_en_usb_a_5v>;
+	};
+
+	sku {
+		compatible = "cros-ec,gpio-id";
+
+		bits  = <
+			&gpio_sku_id0
+			&gpio_sku_id1
+			&gpio_sku_id2
+		>;
+
+		system = "ternary";
+	};
+
+	board {
+		compatible = "cros-ec,gpio-id";
+
+		bits  = <
+			&gpio_brd_id0
+			&gpio_brd_id1
+			&gpio_brd_id2
+		>;
+
+		system = "ternary";
+	};
+
+	unused-pins {
+		compatible = "unused-gpios";
+		unused-gpios =
+			<&gpio5 2 0>,
+			<&gpio5 4 0>,
+			<&gpio7 6 0>,
+			<&gpiod 1 0>,
+			<&gpiod 0 0>,
+			<&gpioe 3 0>,
+			<&gpio0 4 0>,
+			<&gpiod 6 0>,
+			<&gpio3 2 0>,
+			<&gpio3 5 0>,
+			<&gpiod 7 0>,
+			<&gpio8 6 0>,
+			<&gpiod 4 0>,
+			<&gpio4 1 0>,
+			<&gpio3 4 0>,
+			<&gpioc 7 0>,
+			<&gpioa 4 0>,
+			<&gpio9 6 0>,
+			<&gpio9 3 0>,
+			<&gpioa 7 0>,
+			<&gpio5 0 0>,
+			<&gpio8 1 0>,
+			<&gpiob 7 0>;
+	};
+};
+
+/* Power switch logic input pads */
+&psl_in1_gpd2 {
+	/* ACOK_OD */
+	psl-in-mode = "edge";
+	psl-in-pol = "high-rising";
+};
+
+&psl_in2_gp00 {
+	/* EC_PWR_BTN_ODL */
+	psl-in-mode = "edge";
+	psl-in-pol = "low-falling";
+};
+
+&psl_in3_gp01 {
+	/* LID_OPEN_EC */
+	psl-in-mode = "edge";
+	psl-in-pol = "high-rising";
+};
+
+&psl_in4_gp02 {
+	/* RTC_EC_WAKE_ODL */
+	psl-in-mode = "edge";
+	psl-in-pol = "low-falling";
+};
+
+/* Power domain device controlled by PSL (Power Switch Logic) IO pads */
+&power_ctrl_psl {
+	status = "okay";
+	pinctrl-names = "sleep";
+	pinctrl-0 = <&psl_in1_gpd2 &psl_in2_gp00 &psl_in3_gp01 &psl_in4_gp02>;
+};
diff --git a/zephyr/projects/herobrine/gpio_hoglin.dts b/zephyr/projects/herobrine/gpio_hoglin.dts
index f0b8a43586..cb7babc9cf 100644
--- a/zephyr/projects/herobrine/gpio_hoglin.dts
+++ b/zephyr/projects/herobrine/gpio_hoglin.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -225,6 +225,12 @@
 		arm_x86 {
 			gpios = <&gpio6 6 GPIO_OUTPUT_LOW>;
 		};
+		ec-i2c-sensor-scl {
+			gpios = <&gpiob 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		ec-i2c-sensor-sda {
+			gpios = <&gpiob 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
 		gpio_ec_kso_02_inv: ec_kso_02_inv {
 			gpios = <&gpio1 7 (GPIO_OUTPUT_LOW | GPIO_ACTIVE_LOW)>;
 		};
@@ -235,20 +241,6 @@
 		enable-pins = <&gpio_en_usb_a_5v>;
 	};
 
-	def-lvol-io-list {
-		compatible = "nuvoton,npcx-lvolctrl-def";
-		lvol-io-pads = <
-			&lvol_iob3 /* EC_I2C_SENSOR_SCL */
-			&lvol_iob2 /* EC_I2C_SENSOR_SDA */
-		>;
-	};
-
-	vsby-psl-in-list {
-		/* Use PSL_IN1/2/3/4 as detection pins from hibernate mode */
-		psl-in-pads = <&psl_in1 &psl_in2 &psl_in3 &psl_in4>;
-		status = "okay";
-	};
-
 	sku {
 		compatible = "cros-ec,gpio-id";
 
@@ -303,22 +295,33 @@
 };
 
 /* Power switch logic input pads */
-&psl_in1 {
+&psl_in1_gpd2 {
 	/* ACOK_OD */
-	flag = <NPCX_PSL_RISING_EDGE>;
+	psl-in-mode = "edge";
+	psl-in-pol = "high-rising";
 };
 
-&psl_in2 {
+&psl_in2_gp00 {
 	/* EC_PWR_BTN_ODL */
-	flag = <NPCX_PSL_FALLING_EDGE>;
+	psl-in-mode = "edge";
+	psl-in-pol = "low-falling";
 };
 
-&psl_in3 {
+&psl_in3_gp01 {
 	/* LID_OPEN_EC */
-	flag = <NPCX_PSL_RISING_EDGE>;
+	psl-in-mode = "edge";
+	psl-in-pol = "high-rising";
 };
 
-&psl_in4 {
+&psl_in4_gp02 {
 	/* RTC_EC_WAKE_ODL */
-	flag = <NPCX_PSL_FALLING_EDGE>;
+	psl-in-mode = "edge";
+	psl-in-pol = "low-falling";
+};
+
+/* Power domain device controlled by PSL (Power Switch Logic) IO pads */
+&power_ctrl_psl {
+	status = "okay";
+	pinctrl-names = "sleep";
+	pinctrl-0 = <&psl_in1_gpd2 &psl_in2_gp00 &psl_in3_gp01 &psl_in4_gp02>;
 };
diff --git a/zephyr/projects/herobrine/gpio_villager.dts b/zephyr/projects/herobrine/gpio_villager.dts
index 7b8d2adcb5..1e7625ff6a 100644
--- a/zephyr/projects/herobrine/gpio_villager.dts
+++ b/zephyr/projects/herobrine/gpio_villager.dts
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -219,6 +219,12 @@
 		arm_x86 {
 			gpios = <&gpio6 6 GPIO_OUTPUT_LOW>;
 		};
+		ec-i2c-sensor-scl {
+			gpios = <&gpiob 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		ec-i2c-sensor-sda {
+			gpios = <&gpiob 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
 		gpio_ec_kso_02_inv: ec_kso_02_inv {
 			gpios = <&gpio1 7 (GPIO_OUTPUT_LOW | GPIO_ACTIVE_LOW)>;
 		};
@@ -229,20 +235,6 @@
 		enable-pins = <&gpio_en_usb_a_5v>;
 	};
 
-	def-lvol-io-list {
-		compatible = "nuvoton,npcx-lvolctrl-def";
-		lvol-io-pads = <
-			&lvol_iob3 /* EC_I2C_SENSOR_SCL */
-			&lvol_iob2 /* EC_I2C_SENSOR_SDA */
-		>;
-	};
-
-	vsby-psl-in-list {
-		/* Use PSL_IN1/2/3/4 as detection pins from hibernate mode */
-		psl-in-pads = <&psl_in1 &psl_in2 &psl_in3 &psl_in4>;
-		status = "okay";
-	};
-
 	sku {
 		compatible = "cros-ec,gpio-id";
 
@@ -299,22 +291,33 @@
 };
 
 /* Power switch logic input pads */
-&psl_in1 {
+&psl_in1_gpd2 {
 	/* ACOK_OD */
-	flag = <NPCX_PSL_RISING_EDGE>;
+	psl-in-mode = "edge";
+	psl-in-pol = "high-rising";
 };
 
-&psl_in2 {
+&psl_in2_gp00 {
 	/* EC_PWR_BTN_ODL */
-	flag = <NPCX_PSL_FALLING_EDGE>;
+	psl-in-mode = "edge";
+	psl-in-pol = "low-falling";
 };
 
-&psl_in3 {
+&psl_in3_gp01 {
 	/* LID_OPEN_EC */
-	flag = <NPCX_PSL_RISING_EDGE>;
+	psl-in-mode = "edge";
+	psl-in-pol = "high-rising";
 };
 
-&psl_in4 {
+&psl_in4_gp02 {
 	/* RTC_EC_WAKE_ODL */
-	flag = <NPCX_PSL_FALLING_EDGE>;
+	psl-in-mode = "edge";
+	psl-in-pol = "low-falling";
+};
+
+/* Power domain device controlled by PSL (Power Switch Logic) IO pads */
+&power_ctrl_psl {
+	status = "okay";
+	pinctrl-names = "sleep";
+	pinctrl-0 = <&psl_in1_gpd2 &psl_in2_gp00 &psl_in3_gp01 &psl_in4_gp02>;
 };
diff --git a/zephyr/projects/herobrine/i2c.dts b/zephyr/projects/herobrine/i2c_common.dtsi
index 5aed893596..b1ed0242c0 100644
--- a/zephyr/projects/herobrine/i2c.dts
+++ b/zephyr/projects/herobrine/i2c_common.dtsi
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,48 +20,33 @@
 		i2c_power: power {
 			i2c-port = <&i2c0_0>;
 			remote-port = <0>;
-			enum-name = "I2C_PORT_POWER";
-		};
-		battery {
-			i2c-port = <&i2c0_0>;
-			remote-port = <0>;
-			enum-name = "I2C_PORT_BATTERY";
-		};
-		virtual-battery {
-			i2c-port = <&i2c0_0>;
-			remote-port = <0>;
-			enum-name = "I2C_PORT_VIRTUAL_BATTERY";
-		};
-		i2c_charger: charger {
-			i2c-port = <&i2c0_0>;
-			remote-port = <0>;
-			enum-name = "I2C_PORT_CHARGER";
+			enum-names = "I2C_PORT_POWER",
+				"I2C_PORT_BATTERY",
+				"I2C_PORT_VIRTUAL_BATTERY",
+				"I2C_PORT_CHARGER";
 		};
 		i2c_tcpc0: tcpc0 {
 			i2c-port = <&i2c1_0>;
 			dynamic-speed;
-			enum-name = "I2C_PORT_TCPC0";
+			enum-names = "I2C_PORT_TCPC0";
 		};
 		i2c_tcpc1: tcpc1 {
 			i2c-port = <&i2c2_0>;
 			dynamic-speed;
-			enum-name = "I2C_PORT_TCPC1";
+			enum-names = "I2C_PORT_TCPC1";
 		};
 		rtc {
 			i2c-port = <&i2c4_1>;
-			enum-name = "I2C_PORT_RTC";
+			enum-names = "I2C_PORT_RTC";
 		};
 		i2c_eeprom: eeprom {
 			i2c-port = <&i2c5_0>;
-			enum-name = "I2C_PORT_EEPROM";
+			enum-names = "I2C_PORT_EEPROM";
 		};
 		i2c_sensor: sensor {
 			i2c-port = <&i2c7_0>;
-			enum-name = "I2C_PORT_SENSOR";
-		};
-		accel {
-			i2c-port = <&i2c7_0>;
-			enum-name = "I2C_PORT_ACCEL";
+			enum-names = "I2C_PORT_SENSOR",
+				"I2C_PORT_ACCEL";
 		};
 	};
 
@@ -74,6 +59,19 @@
 	clock-frequency = <I2C_BITRATE_STANDARD>;
 	pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>;
 	pinctrl-names = "default";
+
+	bc12_port0: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+		irq = <&int_usb_c0_bc12>;
+	};
+
+	charger: isl923x@9 {
+		compatible = "intersil,isl923x";
+		status = "okay";
+		reg = <0x9>;
+	};
 };
 
 &i2c_ctrl0 {
@@ -119,7 +117,6 @@
 	pcf85063a: pcf85063a@51 {
 		compatible = "nxp,rtc-pcf85063a";
 		reg = <0x51>;
-		label = "RTC_PCF85063A";
 		int-pin = <&gpio_rtc_ec_wake_odl>;
 	};
 };
@@ -134,6 +131,13 @@
 	clock-frequency = <I2C_BITRATE_FAST>;
 	pinctrl-0 = <&i2c5_0_sda_scl_gp33_36>;
 	pinctrl-names = "default";
+
+	bc12_port1: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+		irq = <&int_usb_c1_bc12>;
+	};
 };
 
 &i2c_ctrl5 {
diff --git a/zephyr/projects/herobrine/i2c_evoker.dts b/zephyr/projects/herobrine/i2c_evoker.dts
new file mode 100644
index 0000000000..7023d08c8d
--- /dev/null
+++ b/zephyr/projects/herobrine/i2c_evoker.dts
@@ -0,0 +1,46 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "i2c_common.dtsi"
+
+&i2c1_0 {
+	ppc_port0: syv682x@41 {
+		compatible = "silergy,syv682x";
+		status = "okay";
+		reg = <0x41>;
+		frs_en_gpio = <&gpio_usb_c0_frs_en>;
+	};
+
+	ppc_port0_alt: sn5s330@40 {
+		compatible = "ti,sn5s330";
+		status = "okay";
+		reg = <0x40>;
+	};
+
+	tcpc_port0: ps8xxx@b {
+		compatible = "parade,ps8xxx";
+		reg = <0xb>;
+	};
+};
+
+&i2c2_0 {
+	ppc_port1: syv682x@41 {
+		compatible = "silergy,syv682x";
+		status = "okay";
+		reg = <0x41>;
+		frs_en_gpio = <&gpio_usb_c1_frs_en>;
+	};
+
+	ppc_port1_alt: sn5s330@40 {
+		compatible = "ti,sn5s330";
+		status = "okay";
+		reg = <0x40>;
+	};
+
+	tcpc_port1: ps8xxx@b {
+		compatible = "parade,ps8xxx";
+		reg = <0xb>;
+	};
+};
diff --git a/zephyr/projects/herobrine/i2c_herobrine.dts b/zephyr/projects/herobrine/i2c_herobrine.dts
new file mode 100644
index 0000000000..92c68f4215
--- /dev/null
+++ b/zephyr/projects/herobrine/i2c_herobrine.dts
@@ -0,0 +1,39 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "i2c_common.dtsi"
+
+&i2c1_0 {
+	ppc_port0: sn5s330@40 {
+		compatible = "ti,sn5s330";
+		status = "okay";
+		reg = <0x40>;
+	};
+
+	ppc_port0_alt: syv682x@41 {
+		compatible = "silergy,syv682x";
+		status = "okay";
+		reg = <0x41>;
+		frs_en_gpio = <&gpio_usb_c0_frs_en>;
+	};
+
+	tcpc_port0: ps8xxx@b {
+		compatible = "parade,ps8xxx";
+		reg = <0xb>;
+	};
+};
+
+&i2c2_0 {
+	ppc_port1: sn5s330@40 {
+		compatible = "ti,sn5s330";
+		status = "okay";
+		reg = <0x40>;
+	};
+
+	tcpc_port1: ps8xxx@b {
+		compatible = "parade,ps8xxx";
+		reg = <0xb>;
+	};
+};
diff --git a/zephyr/projects/herobrine/i2c_hoglin.dts b/zephyr/projects/herobrine/i2c_hoglin.dts
new file mode 100644
index 0000000000..504dbb9248
--- /dev/null
+++ b/zephyr/projects/herobrine/i2c_hoglin.dts
@@ -0,0 +1,34 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "i2c_common.dtsi"
+
+&i2c1_0 {
+	ppc_port0: syv682x@41 {
+		compatible = "silergy,syv682x";
+		status = "okay";
+		reg = <0x41>;
+		frs_en_gpio = <&gpio_usb_c0_frs_en>;
+	};
+
+	tcpc_port0: ps8xxx@1b {
+		compatible = "parade,ps8xxx";
+		reg = <0x1b>;
+	};
+};
+
+&i2c2_0 {
+	ppc_port1: syv682x@41 {
+		compatible = "silergy,syv682x";
+		status = "okay";
+		reg = <0x41>;
+		frs_en_gpio = <&gpio_usb_c1_frs_en>;
+	};
+
+	tcpc_port1: ps8xxx@1b {
+		compatible = "parade,ps8xxx";
+		reg = <0x1b>;
+	};
+};
diff --git a/zephyr/projects/herobrine/i2c_villager.dts b/zephyr/projects/herobrine/i2c_villager.dts
new file mode 100644
index 0000000000..efdf88ac38
--- /dev/null
+++ b/zephyr/projects/herobrine/i2c_villager.dts
@@ -0,0 +1,34 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "i2c_common.dtsi"
+
+&i2c1_0 {
+	ppc_port0: syv682x@41 {
+		compatible = "silergy,syv682x";
+		status = "okay";
+		reg = <0x41>;
+		frs_en_gpio = <&gpio_usb_c0_frs_en>;
+	};
+
+	tcpc_port0: ps8xxx@b {
+		compatible = "parade,ps8xxx";
+		reg = <0xb>;
+	};
+};
+
+&i2c2_0 {
+	ppc_port1: syv682x@41 {
+		compatible = "silergy,syv682x";
+		status = "okay";
+		reg = <0x41>;
+		frs_en_gpio = <&gpio_usb_c1_frs_en>;
+	};
+
+	tcpc_port1: ps8xxx@b {
+		compatible = "parade,ps8xxx";
+		reg = <0xb>;
+	};
+};
diff --git a/zephyr/projects/herobrine/include/board_chipset.h b/zephyr/projects/herobrine/include/board_chipset.h
new file mode 100644
index 0000000000..8350ef10ff
--- /dev/null
+++ b/zephyr/projects/herobrine/include/board_chipset.h
@@ -0,0 +1,11 @@
+/* Copyright 2022 The ChromiumOS Authors.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_HEROBRINE_BOARD_CHIPSET_H
+#define __CROS_EC_HEROBRINE_BOARD_CHIPSET_H
+
+__test_only void reset_pp5000_inited(void);
+
+#endif /* __CROS_EC_HEROBRINE_BOARD_CHIPSET_H */
diff --git a/zephyr/projects/herobrine/include/gpio_map.h b/zephyr/projects/herobrine/include/gpio_map.h
deleted file mode 100644
index c2b81fe5c6..0000000000
--- a/zephyr/projects/herobrine/include/gpio_map.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __ZEPHYR_GPIO_MAP_H
-#define __ZEPHYR_GPIO_MAP_H
-
-#endif /* __ZEPHYR_GPIO_MAP_H */
diff --git a/zephyr/projects/herobrine/interrupts.dts b/zephyr/projects/herobrine/interrupts.dts
index 23902a7d05..82650bfc51 100644
--- a/zephyr/projects/herobrine/interrupts.dts
+++ b/zephyr/projects/herobrine/interrupts.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/herobrine/keyboard.dts b/zephyr/projects/herobrine/keyboard.dts
index 202b61bb4f..3b7e830f2f 100644
--- a/zephyr/projects/herobrine/keyboard.dts
+++ b/zephyr/projects/herobrine/keyboard.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,7 +7,6 @@
 	kblight {
 		compatible = "cros-ec,kblight-pwm";
 		pwms = <&pwm3 0 PWM_KHZ(10) PWM_POLARITY_NORMAL>;
-		frequency = <10000>;
 		generic-pwm-channel = <0>;
 	};
 };
diff --git a/zephyr/projects/herobrine/led_pins_evoker.dts b/zephyr/projects/herobrine/led_pins_evoker.dts
new file mode 100644
index 0000000000..ff2dc0e36c
--- /dev/null
+++ b/zephyr/projects/herobrine/led_pins_evoker.dts
@@ -0,0 +1,54 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	gpio-led-pins {
+		compatible = "cros-ec,gpio-led-pins";
+
+		color_power_off: color-power-off {
+			led-color = "LED_OFF";
+			led-id = "EC_LED_ID_POWER_LED";
+			led-pins = <&gpio_ec_chg_led_w_c1 0>;
+		};
+
+		color_power_white: color-power-white {
+			led-color = "LED_WHITE";
+			led-id = "EC_LED_ID_POWER_LED";
+			led-pins = <&gpio_ec_chg_led_w_c1 1>;
+		};
+
+		color_battery_off: color-battery-off {
+			led-color = "LED_OFF";
+			led-id = "EC_LED_ID_BATTERY_LED";
+			led-pins = <&gpio_ec_chg_led_y_c0 0>,
+				   <&gpio_ec_chg_led_w_c0 0>,
+				   <&gpio_ec_chg_led_r_c0 0>;
+		};
+
+		color_battery_amber: color-battery-amber {
+			led-color = "LED_AMBER";
+			led-id = "EC_LED_ID_BATTERY_LED";
+			led-pins = <&gpio_ec_chg_led_y_c0 1>,
+				   <&gpio_ec_chg_led_w_c0 0>,
+				   <&gpio_ec_chg_led_r_c0 0>;
+		};
+
+		color_battery_white: color-battery-white {
+			led-color = "LED_WHITE";
+			led-id = "EC_LED_ID_BATTERY_LED";
+			led-pins = <&gpio_ec_chg_led_y_c0 0>,
+				   <&gpio_ec_chg_led_w_c0 1>,
+				   <&gpio_ec_chg_led_r_c0 0>;
+		};
+
+		color_battery_red: color-battery-red {
+			led-color = "LED_RED";
+			led-id = "EC_LED_ID_BATTERY_LED";
+			led-pins = <&gpio_ec_chg_led_y_c0 0>,
+				   <&gpio_ec_chg_led_w_c0 0>,
+				   <&gpio_ec_chg_led_r_c0 1>;
+		};
+	};
+};
diff --git a/zephyr/projects/herobrine/led_pins_herobrine.dts b/zephyr/projects/herobrine/led_pins_herobrine.dts
index cdc5f03904..c509ab1a64 100644
--- a/zephyr/projects/herobrine/led_pins_herobrine.dts
+++ b/zephyr/projects/herobrine/led_pins_herobrine.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/herobrine/led_pins_hoglin.dts b/zephyr/projects/herobrine/led_pins_hoglin.dts
index 8603b4e61d..7b125c5cac 100644
--- a/zephyr/projects/herobrine/led_pins_hoglin.dts
+++ b/zephyr/projects/herobrine/led_pins_hoglin.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/herobrine/led_pins_villager.dts b/zephyr/projects/herobrine/led_pins_villager.dts
index 67a1d1926c..b0913cdbce 100644
--- a/zephyr/projects/herobrine/led_pins_villager.dts
+++ b/zephyr/projects/herobrine/led_pins_villager.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/herobrine/led_policy_evoker.dts b/zephyr/projects/herobrine/led_policy_evoker.dts
new file mode 100644
index 0000000000..fc17755ede
--- /dev/null
+++ b/zephyr/projects/herobrine/led_policy_evoker.dts
@@ -0,0 +1,86 @@
+#include <dt-bindings/battery.h>
+
+/ {
+	led-colors {
+		compatible = "cros-ec,led-policy";
+
+		battery-state-charge {
+			charge-state = "PWR_STATE_CHARGE";
+
+			color-0 {
+				led-color = <&color_battery_amber>;
+			};
+		};
+
+		battery-state-near-full {
+			charge-state = "PWR_STATE_CHARGE_NEAR_FULL";
+
+			color-0 {
+				led-color = <&color_battery_white>;
+			};
+		};
+
+		battery-state-discharge {
+			charge-state = "PWR_STATE_DISCHARGE";
+
+			color-0 {
+				led-color = <&color_battery_off>;
+			};
+		};
+
+		battery-state-error {
+			charge-state = "PWR_STATE_ERROR";
+
+			color-0 {
+				led-color = <&color_battery_red>;
+			};
+		};
+
+		/* force idle mode */
+		battery-state-forced-idle {
+			charge-state = "PWR_STATE_FORCED_IDLE";
+
+			/* Red 1 sec, White 1 sec */
+			color-0 {
+				led-color = <&color_battery_red>;
+				period-ms = <1000>;
+			};
+
+			color-1 {
+				led-color = <&color_battery_white>;
+				period-ms = <1000>;
+			};
+		};
+
+		pwr-power-state-s0 {
+			chipset-state = "POWER_S0";
+
+			color-0 {
+				led-color = <&color_power_white>;
+			};
+		};
+
+		power-state-s3 {
+			chipset-state = "POWER_S3";
+
+			/* white LED - on 1 sec, off 1 sec */
+			color-0 {
+				led-color = <&color_power_white>;
+				period-ms = <1000>;
+			};
+
+			color-1 {
+				led-color = <&color_power_off>;
+				period-ms = <1000>;
+			};
+		};
+
+		power-state-s5 {
+			chipset-state = "POWER_S5";
+
+			color-0 {
+				led-color = <&color_power_off>;
+			};
+		};
+	};
+};
diff --git a/zephyr/projects/herobrine/led_policy_herobrine.dts b/zephyr/projects/herobrine/led_policy_herobrine.dts
index 7e296e6a3a..13e5306deb 100644
--- a/zephyr/projects/herobrine/led_policy_herobrine.dts
+++ b/zephyr/projects/herobrine/led_policy_herobrine.dts
@@ -2,7 +2,7 @@
 
 / {
 	led-colors {
-		compatible = "cros-ec,led-colors";
+		compatible = "cros-ec,led-policy";
 
 		power-state-charge-left {
 			charge-state = "PWR_STATE_CHARGE";
@@ -133,10 +133,9 @@
 			};
 		};
 
-		power-state-idle-forced-left {
-			charge-state = "PWR_STATE_IDLE";
+		power-state-forced-idle-left {
+			charge-state = "PWR_STATE_FORCED_IDLE";
 			charge-port = <1>; /* Left port */
-			extra-flag = "LED_CHFLAG_FORCE_IDLE";
 
 			/* Turn off the right LED */
 			color-0 {
@@ -153,10 +152,9 @@
 			};
 		};
 
-		power-state-idle-forced-right {
-			charge-state = "PWR_STATE_IDLE";
+		power-state-forced-idle-right {
+			charge-state = "PWR_STATE_FORCED_IDLE";
 			charge-port = <0>; /* Right port */
-			extra-flag = "LED_CHFLAG_FORCE_IDLE";
 
 			/* Turn off the left LED */
 			color-0 {
@@ -173,10 +171,9 @@
 			};
 		};
 
-		power-state-idle-default-left {
+		power-state-idle-left {
 			charge-state = "PWR_STATE_IDLE";
 			charge-port = <1>; /* Left port */
-			extra-flag = "LED_CHFLAG_DEFAULT";
 
 			/* Turn off the right LED */
 			color-0 {
@@ -188,10 +185,9 @@
 			};
 		};
 
-		power-state-idle-default-right {
+		power-state-idle-right {
 			charge-state = "PWR_STATE_IDLE";
 			charge-port = <0>; /* Right port */
-			extra-flag = "LED_CHFLAG_DEFAULT";
 
 			/* Turn off the left LED */
 			color-0 {
diff --git a/zephyr/projects/herobrine/led_policy_hoglin.dts b/zephyr/projects/herobrine/led_policy_hoglin.dts
index 80ee9f7829..043dfbcaa5 100644
--- a/zephyr/projects/herobrine/led_policy_hoglin.dts
+++ b/zephyr/projects/herobrine/led_policy_hoglin.dts
@@ -1,11 +1,11 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 / {
 	led-colors {
-		compatible = "cros-ec,led-colors";
+		compatible = "cros-ec,led-policy";
 
 		power-state-charge {
 			charge-state = "PWR_STATE_CHARGE";
@@ -70,9 +70,8 @@
 			};
 		};
 
-		power-state-idle-forced {
-			charge-state = "PWR_STATE_IDLE";
-			extra-flag = "LED_CHFLAG_FORCE_IDLE";
+		power-state-forced-idle {
+			charge-state = "PWR_STATE_FORCED_IDLE";
 
 			/* Red 2 sec, Blue 2 sec */
 			color-0 {
@@ -87,7 +86,6 @@
 
 		power-state-idle-default {
 			charge-state = "PWR_STATE_IDLE";
-			extra-flag = "LED_CHFLAG_DEFAULT";
 
 			color-0 {
 				led-color = <&color_red>;
diff --git a/zephyr/projects/herobrine/led_policy_villager.dts b/zephyr/projects/herobrine/led_policy_villager.dts
index 46b0193e61..f8996a3f4b 100644
--- a/zephyr/projects/herobrine/led_policy_villager.dts
+++ b/zephyr/projects/herobrine/led_policy_villager.dts
@@ -1,11 +1,11 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 / {
 	led-colors {
-		compatible = "cros-ec,led-colors";
+		compatible = "cros-ec,led-policy";
 
 		power-state-charge {
 			charge-state = "PWR_STATE_CHARGE";
@@ -70,9 +70,8 @@
 			};
 		};
 
-		power-state-idle-forced {
-			charge-state = "PWR_STATE_IDLE";
-			extra-flag = "LED_CHFLAG_FORCE_IDLE";
+		power-state-forced-idle {
+			charge-state = "PWR_STATE_FORCED_IDLE";
 
 			/* Blue 2 sec, Amber 2 sec */
 			color-0 {
@@ -85,9 +84,8 @@
 			};
 		};
 
-		power-state-idle-default {
+		power-state-idle {
 			charge-state = "PWR_STATE_IDLE";
-			extra-flag = "LED_CHFLAG_DEFAULT";
 
 			color-0 {
 				led-color = <&color_blue>;
diff --git a/zephyr/projects/herobrine/motionsense.dts b/zephyr/projects/herobrine/motionsense.dts
index 1d36fcbf47..1955f43284 100644
--- a/zephyr/projects/herobrine/motionsense.dts
+++ b/zephyr/projects/herobrine/motionsense.dts
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,11 +27,9 @@
 	motionsense-mutex {
 		compatible = "cros-ec,motionsense-mutex";
 		lid_mutex: lid-mutex {
-			label = "LID_MUTEX";
 		};
 
 		mutex_bmi260: bmi260-mutex {
-			label = "BMI260_MUTEX";
 		};
 	};
 
@@ -40,8 +38,8 @@
 		compatible = "cros-ec,motionsense-rotation-ref";
 		lid_rot_ref: lid-rotation-ref {
 			mat33 = <0 1 0
-				 (-1) 0 0
-				 0 0 1>;
+				 1 0 0
+				 0 0 (-1)>;
 		};
 
 		base_rot_ref: base-rotation-ref {
@@ -134,7 +132,7 @@
 
 	/*
 	 * List of motion sensors that creates motion_sensors array.
-	 * The label "lid_accel" and "base_accel" are used to indicate
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
 	 * motion sensor IDs for lid angle calculation.
 	 */
 	motionsense-sensor {
@@ -142,7 +140,6 @@
 			compatible = "cros-ec,bma255";
 			status = "okay";
 
-			label = "Lid Accel";
 			active-mask = "SENSOR_ACTIVE_S0_S3";
 			location = "MOTIONSENSE_LOC_LID";
 			mutex = <&lid_mutex>;
@@ -155,11 +152,9 @@
 				compatible =
 					"cros-ec,motionsense-sensor-config";
 				ec-s0 {
-					label = "SENSOR_CONFIG_EC_S0";
 					odr = <(10000 | ROUND_UP_FLAG)>;
 				};
 				ec-s3 {
-					label = "SENSOR_CONFIG_EC_S3";
 					odr = <(10000 | ROUND_UP_FLAG)>;
 				};
 			};
@@ -169,7 +164,6 @@
 			compatible = "cros-ec,bmi260-accel";
 			status = "okay";
 
-			label = "Base Accel";
 			active-mask = "SENSOR_ACTIVE_S0_S3";
 			location = "MOTIONSENSE_LOC_BASE";
 			mutex = <&mutex_bmi260>;
@@ -180,11 +174,9 @@
 				compatible =
 					"cros-ec,motionsense-sensor-config";
 				ec-s0 {
-					label = "SENSOR_CONFIG_EC_S0";
 					odr = <(10000 | ROUND_UP_FLAG)>;
 				};
 				ec-s3 {
-					label = "SENSOR_CONFIG_EC_S3";
 					odr = <(10000 | ROUND_UP_FLAG)>;
 				};
 			};
@@ -194,7 +186,6 @@
 			compatible = "cros-ec,bmi260-gyro";
 			status = "okay";
 
-			label = "Base Gyro";
 			active-mask = "SENSOR_ACTIVE_S0_S3";
 			location = "MOTIONSENSE_LOC_BASE";
 			mutex = <&mutex_bmi260>;
@@ -207,7 +198,6 @@
 			compatible = "cros-ec,tcs3400-clear";
 			status = "okay";
 
-			label = "Clear Light";
 			active-mask = "SENSOR_ACTIVE_S0_S3";
 			location = "MOTIONSENSE_LOC_CAMERA";
 			port = <&i2c_sensor>;
@@ -219,7 +209,6 @@
 					"cros-ec,motionsense-sensor-config";
 				ec-s0 {
 					/* Run ALS sensor in S0 */
-					label = "SENSOR_CONFIG_EC_S0";
 					odr = <1000>;
 				};
 			};
@@ -229,7 +218,6 @@
 			compatible = "cros-ec,tcs3400-rgb";
 			status = "okay";
 
-			label = "RGB Light";
 			active-mask = "SENSOR_ACTIVE_S0_S3";
 			location = "MOTIONSENSE_LOC_CAMERA";
 			default-range = <0x10000>; /* scale = 1x, uscale = 0 */
diff --git a/zephyr/projects/herobrine/motionsense_evoker.dts b/zephyr/projects/herobrine/motionsense_evoker.dts
new file mode 100644
index 0000000000..aa7646e0b3
--- /dev/null
+++ b/zephyr/projects/herobrine/motionsense_evoker.dts
@@ -0,0 +1,148 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/motionsense/utils.h>
+
+
+/ {
+	aliases {
+		/*
+		 * motion sense's <>_INT_EVENT is handled
+		 * by alias. Using the alias, each driver creates
+		 * its own <>_INT_EVENT.
+		 */
+		bmi260-int = &base_accel;
+	};
+
+	/*
+	 * Declare mutexes used by sensor drivers.
+	 * A mutex node is used to create an instance of mutex_t.
+	 * A mutex node is referenced by a sensor node if the
+	 * corresponding sensor driver needs to use the
+	 * instance of the mutex.
+	 */
+	motionsense-mutex {
+		compatible = "cros-ec,motionsense-mutex";
+		lid_mutex: lid-mutex {
+		};
+
+		mutex_bmi260: bmi260-mutex {
+		};
+	};
+
+	/* Rotation matrix used by drivers. */
+	motionsense-rotation-ref {
+		compatible = "cros-ec,motionsense-rotation-ref";
+		lid_rot_ref: lid-rotation-ref {
+			mat33 = <(-1) 0 0
+				 0 (-1) 0
+				 0 0 1>;
+		};
+
+		base_rot_ref: base-rotation-ref {
+			mat33 = <0 1 0
+				 (-1) 0 0
+				 0 0 1>;
+		};
+	};
+
+	/*
+	 * Driver specific data. A driver-specific data can be shared with
+	 * different motion sensors while they are using the same driver.
+	 *
+	 * If a node's compatible starts with "cros-ec,accelgyro-", it is for
+	 * a common structure defined in accelgyro.h.
+	 * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for
+	 * "struct als_drv_data_t" in accelgyro.h
+	 */
+	motionsense-sensor-data {
+		bma4xx_data: bma4xx-drv-data {
+			compatible = "cros-ec,drvdata-bma4xx";
+			status = "okay";
+		};
+
+		bmi260_data: bmi260-drv-data {
+			compatible = "cros-ec,drvdata-bmi260";
+			status = "okay";
+		};
+	};
+
+	/*
+	 * List of motion sensors that creates motion_sensors array.
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
+	 * motion sensor IDs for lid angle calculation.
+	 */
+	motionsense-sensor {
+		lid_accel: lid-accel {
+			compatible = "cros-ec,bma4xx";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&lid_mutex>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&lid_rot_ref>;
+			default-range = <2>;
+			drv-data = <&bma4xx_data>;
+			i2c-spi-addr-flags = "BMA4_I2C_ADDR_PRIMARY";
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_accel: base-accel {
+			compatible = "cros-ec,bmi260-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&mutex_bmi260>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&bmi260_data>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base-gyro {
+			compatible = "cros-ec,bmi260-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&mutex_bmi260>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&bmi260_data>;
+		};
+	};
+
+	motionsense-sensor-info {
+		compatible = "cros-ec,motionsense-sensor-info";
+
+		/*
+		 * list of GPIO interrupts that have to
+		 * be enabled at initial stage
+		 */
+		sensor-irqs = <&int_accel_gyro>;
+		/* list of sensors in force mode */
+		accel-force-mode-sensors = <&lid_accel>;
+	};
+};
diff --git a/zephyr/projects/herobrine/motionsense_hoglin.dts b/zephyr/projects/herobrine/motionsense_hoglin.dts
index 3f67347e10..c3935178ff 100644
--- a/zephyr/projects/herobrine/motionsense_hoglin.dts
+++ b/zephyr/projects/herobrine/motionsense_hoglin.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,11 +27,9 @@
 	motionsense-mutex {
 		compatible = "cros-ec,motionsense-mutex";
 		lid_mutex: lid-mutex {
-			label = "LID_MUTEX";
 		};
 
 		mutex_bmi260: bmi260-mutex {
-			label = "BMI260_MUTEX";
 		};
 	};
 
@@ -134,7 +132,7 @@
 
 	/*
 	 * List of motion sensors that creates motion_sensors array.
-	 * The label "lid_accel" and "base_accel" are used to indicate
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
 	 * motion sensor IDs for lid angle calculation.
 	 */
 	motionsense-sensor {
@@ -142,7 +140,6 @@
 			compatible = "cros-ec,bma4xx";
 			status = "okay";
 
-			label = "Lid Accel";
 			active-mask = "SENSOR_ACTIVE_S0_S3";
 			location = "MOTIONSENSE_LOC_LID";
 			mutex = <&lid_mutex>;
@@ -155,11 +152,9 @@
 				compatible =
 					"cros-ec,motionsense-sensor-config";
 				ec-s0 {
-					label = "SENSOR_CONFIG_EC_S0";
 					odr = <(10000 | ROUND_UP_FLAG)>;
 				};
 				ec-s3 {
-					label = "SENSOR_CONFIG_EC_S3";
 					odr = <(10000 | ROUND_UP_FLAG)>;
 				};
 			};
@@ -169,7 +164,6 @@
 			compatible = "cros-ec,bmi260-accel";
 			status = "okay";
 
-			label = "Base Accel";
 			active-mask = "SENSOR_ACTIVE_S0_S3";
 			location = "MOTIONSENSE_LOC_BASE";
 			mutex = <&mutex_bmi260>;
@@ -180,11 +174,9 @@
 				compatible =
 					"cros-ec,motionsense-sensor-config";
 				ec-s0 {
-					label = "SENSOR_CONFIG_EC_S0";
 					odr = <(10000 | ROUND_UP_FLAG)>;
 				};
 				ec-s3 {
-					label = "SENSOR_CONFIG_EC_S3";
 					odr = <(10000 | ROUND_UP_FLAG)>;
 				};
 			};
@@ -194,7 +186,6 @@
 			compatible = "cros-ec,bmi260-gyro";
 			status = "okay";
 
-			label = "Base Gyro";
 			active-mask = "SENSOR_ACTIVE_S0_S3";
 			location = "MOTIONSENSE_LOC_BASE";
 			mutex = <&mutex_bmi260>;
@@ -207,7 +198,6 @@
 			compatible = "cros-ec,tcs3400-clear";
 			status = "okay";
 
-			label = "Clear Light";
 			active-mask = "SENSOR_ACTIVE_S0_S3";
 			location = "MOTIONSENSE_LOC_CAMERA";
 			port = <&i2c_sensor>;
@@ -219,7 +209,6 @@
 					"cros-ec,motionsense-sensor-config";
 				ec-s0 {
 					/* Run ALS sensor in S0 */
-					label = "SENSOR_CONFIG_EC_S0";
 					odr = <1000>;
 				};
 			};
@@ -229,7 +218,6 @@
 			compatible = "cros-ec,tcs3400-rgb";
 			status = "okay";
 
-			label = "RGB Light";
 			active-mask = "SENSOR_ACTIVE_S0_S3";
 			location = "MOTIONSENSE_LOC_CAMERA";
 			default-range = <0x10000>; /* scale = 1x, uscale = 0 */
diff --git a/zephyr/projects/herobrine/motionsense_villager.dts b/zephyr/projects/herobrine/motionsense_villager.dts
index 92cc051a8e..31d00e04a5 100644
--- a/zephyr/projects/herobrine/motionsense_villager.dts
+++ b/zephyr/projects/herobrine/motionsense_villager.dts
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,11 +26,9 @@
 	motionsense-mutex {
 		compatible = "cros-ec,motionsense-mutex";
 		lid_mutex: lid-mutex {
-			label = "LID_MUTEX";
 		};
 
 		mutex_bmi260: bmi260-mutex {
-			label = "BMI260_MUTEX";
 		};
 	};
 
@@ -73,7 +71,7 @@
 
 	/*
 	 * List of motion sensors that creates motion_sensors array.
-	 * The label "lid_accel" and "base_accel" are used to indicate
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
 	 * motion sensor IDs for lid angle calculation.
 	 */
 	motionsense-sensor {
@@ -81,7 +79,6 @@
 			compatible = "cros-ec,kx022";
 			status = "okay";
 
-			label = "Lid Accel";
 			active-mask = "SENSOR_ACTIVE_S0_S3";
 			location = "MOTIONSENSE_LOC_LID";
 			mutex = <&lid_mutex>;
@@ -94,11 +91,9 @@
 				compatible =
 					"cros-ec,motionsense-sensor-config";
 				ec-s0 {
-					label = "SENSOR_CONFIG_EC_S0";
 					odr = <(10000 | ROUND_UP_FLAG)>;
 				};
 				ec-s3 {
-					label = "SENSOR_CONFIG_EC_S3";
 					odr = <(10000 | ROUND_UP_FLAG)>;
 				};
 			};
@@ -108,7 +103,6 @@
 			compatible = "cros-ec,bmi260-accel";
 			status = "okay";
 
-			label = "Base Accel";
 			active-mask = "SENSOR_ACTIVE_S0_S3";
 			location = "MOTIONSENSE_LOC_BASE";
 			mutex = <&mutex_bmi260>;
@@ -119,11 +113,9 @@
 				compatible =
 					"cros-ec,motionsense-sensor-config";
 				ec-s0 {
-					label = "SENSOR_CONFIG_EC_S0";
 					odr = <(10000 | ROUND_UP_FLAG)>;
 				};
 				ec-s3 {
-					label = "SENSOR_CONFIG_EC_S3";
 					odr = <(10000 | ROUND_UP_FLAG)>;
 				};
 			};
@@ -133,7 +125,6 @@
 			compatible = "cros-ec,bmi260-gyro";
 			status = "okay";
 
-			label = "Base Gyro";
 			active-mask = "SENSOR_ACTIVE_S0_S3";
 			location = "MOTIONSENSE_LOC_BASE";
 			mutex = <&mutex_bmi260>;
diff --git a/zephyr/projects/herobrine/prj.conf b/zephyr/projects/herobrine/prj.conf
index e16d5c7899..2b13023f2d 100644
--- a/zephyr/projects/herobrine/prj.conf
+++ b/zephyr/projects/herobrine/prj.conf
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -26,9 +26,6 @@ CONFIG_SHELL_HISTORY=y
 CONFIG_SHELL_TAB=y
 CONFIG_SHELL_TAB_AUTOCOMPLETION=y
 
-# Miscellaneous configs
-CONFIG_PLATFORM_EC_HIBERNATE_PSL=y
-
 # LED
 CONFIG_PLATFORM_EC_LED_COMMON=n
 CONFIG_PLATFORM_EC_LED_DT=y
@@ -69,7 +66,6 @@ CONFIG_PLATFORM_EC_CMD_BUTTON=y
 CONFIG_CROS_KB_RAW_NPCX=y
 
 # ADC
-CONFIG_PLATFORM_EC_ADC=y
 CONFIG_ADC=y
 CONFIG_ADC_SHELL=n
 
@@ -114,7 +110,10 @@ CONFIG_PLATFORM_EC_USB_DRP_ACC_TRYSRC=y
 CONFIG_PLATFORM_EC_USB_PD_5V_EN_CUSTOM=y
 CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y
 CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y
+CONFIG_PLATFORM_EC_USB_PD_DPS=y
 CONFIG_PLATFORM_EC_USB_PD_REV30=y
+CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=n
+CONFIG_PLATFORM_EC_USB_PD_USB4=n
 CONFIG_PLATFORM_EC_USB_PD_TCPC_LOW_POWER=y
 CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8805=y
 CONFIG_PLATFORM_EC_USB_PD_TCPC_RUNTIME_CONFIG=n
diff --git a/zephyr/projects/herobrine/prj_evoker.conf b/zephyr/projects/herobrine/prj_evoker.conf
new file mode 100644
index 0000000000..6a57333bfd
--- /dev/null
+++ b/zephyr/projects/herobrine/prj_evoker.conf
@@ -0,0 +1,12 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Evoker board-specific Kconfig settings.
+CONFIG_BOARD_EVOKER=y
+
+# Disable type-c port sourcing 3A
+CONFIG_PLATFORM_EC_CONFIG_USB_PD_3A_PORTS=0
+
+CONFIG_PLATFORM_EC_ACCEL_BMA255=n
+CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y
diff --git a/zephyr/projects/herobrine/prj_herobrine.conf b/zephyr/projects/herobrine/prj_herobrine.conf
index 3c7eddbae6..bf39f65692 100644
--- a/zephyr/projects/herobrine/prj_herobrine.conf
+++ b/zephyr/projects/herobrine/prj_herobrine.conf
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/projects/herobrine/prj_hoglin.conf b/zephyr/projects/herobrine/prj_hoglin.conf
index 370e942f45..c6e20937c0 100644
--- a/zephyr/projects/herobrine/prj_hoglin.conf
+++ b/zephyr/projects/herobrine/prj_hoglin.conf
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/projects/herobrine/prj_villager.conf b/zephyr/projects/herobrine/prj_villager.conf
index 34c366a36f..35eebe6d99 100644
--- a/zephyr/projects/herobrine/prj_villager.conf
+++ b/zephyr/projects/herobrine/prj_villager.conf
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/projects/herobrine/prj_zoglin.conf b/zephyr/projects/herobrine/prj_zoglin.conf
new file mode 100644
index 0000000000..7f96cf6c79
--- /dev/null
+++ b/zephyr/projects/herobrine/prj_zoglin.conf
@@ -0,0 +1,15 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Zoglin reference-board-specific Kconfig settings.
+CONFIG_BOARD_ZOGLIN=y
+CONFIG_PLATFORM_EC_ACCEL_BMA255=n
+CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y
+
+# Sensors
+CONFIG_PLATFORM_EC_ALS=y
+
+# Sensor Drivers
+CONFIG_PLATFORM_EC_ALS_TCS3400=y
+CONFIG_PLATFORM_EC_ALS_TCS3400_EMULATED_IRQ_EVENT=y
diff --git a/zephyr/projects/herobrine/src/board_chipset.c b/zephyr/projects/herobrine/src/board_chipset.c
new file mode 100644
index 0000000000..6a58eee99e
--- /dev/null
+++ b/zephyr/projects/herobrine/src/board_chipset.c
@@ -0,0 +1,83 @@
+/* Copyright 2022 The ChromiumOS Authors.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Herobrine chipset-specific configuration */
+
+#include "charger.h"
+#include "common.h"
+#include "console.h"
+#include "battery.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "timer.h"
+#include "usb_pd.h"
+
+#include "board_chipset.h"
+
+#define CPRINTS(format, args...) cprints(CC_HOOK, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_HOOK, format, ##args)
+
+/*
+ * A window of PD negotiation. It starts from the Type-C state reaching
+ * Attached.SNK, and ends when the PD contract is created. The VBUS may be
+ * raised anytime in this window.
+ *
+ * The current implementation is the worst case scenario: every message the PD
+ * negotiation is received at the last moment before timeout. More extra time
+ * is added to compensate the delay internally, like the decision of the DPM.
+ *
+ * TODO(waihong): Cancel this timer when the PD contract is negotiated.
+ */
+#define PD_READY_TIMEOUT                                                    \
+	(PD_T_SINK_WAIT_CAP + PD_T_SENDER_RESPONSE + PD_T_SINK_TRANSITION + \
+	 20 * MSEC)
+
+#define PD_READY_POLL_DELAY (10 * MSEC)
+
+static timestamp_t pd_ready_timeout;
+
+static bool pp5000_inited;
+
+__test_only void reset_pp5000_inited(void)
+{
+	pp5000_inited = false;
+}
+
+/* Called on USB PD connected */
+static void board_usb_pd_connect(void)
+{
+	int soc = -1;
+
+	/* First boot, battery unattached or low SOC */
+	if (!pp5000_inited &&
+	    ((battery_state_of_charge_abs(&soc) != EC_SUCCESS ||
+	      soc < charger_get_min_bat_pct_for_power_on()))) {
+		pd_ready_timeout = get_time();
+		pd_ready_timeout.val += PD_READY_TIMEOUT;
+	}
+}
+DECLARE_HOOK(HOOK_USB_PD_CONNECT, board_usb_pd_connect, HOOK_PRIO_DEFAULT);
+
+static void wait_pd_ready(void)
+{
+	CPRINTS("Wait PD negotiated VBUS transition %u",
+		pd_ready_timeout.le.lo);
+	while (pd_ready_timeout.val && get_time().val < pd_ready_timeout.val)
+		usleep(PD_READY_POLL_DELAY);
+}
+
+/* Called on AP S5 -> S3 transition */
+static void board_chipset_pre_init(void)
+{
+	if (!pp5000_inited) {
+		if (pd_ready_timeout.val) {
+			wait_pd_ready();
+		}
+		CPRINTS("Enable 5V rail");
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pp5000_s5), 1);
+		pp5000_inited = true;
+	}
+}
+DECLARE_HOOK(HOOK_CHIPSET_PRE_INIT, board_chipset_pre_init, HOOK_PRIO_DEFAULT);
diff --git a/zephyr/projects/herobrine/src/herobrine/alt_dev_replacement.c b/zephyr/projects/herobrine/src/herobrine/alt_dev_replacement.c
index 1b5c1e3d92..00acd509f4 100644
--- a/zephyr/projects/herobrine/src/herobrine/alt_dev_replacement.c
+++ b/zephyr/projects/herobrine/src/herobrine/alt_dev_replacement.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,7 +12,7 @@ LOG_MODULE_REGISTER(alt_dev_replacement);
 #define BOARD_VERSION_UNKNOWN 0xffffffff
 
 /* Check board version to decide which ppc is used. */
-static bool board_has_syv_ppc(void)
+static bool board_has_alt_ppc(void)
 {
 	static uint32_t board_version = BOARD_VERSION_UNKNOWN;
 
@@ -29,7 +29,8 @@ static bool board_has_syv_ppc(void)
 static void check_alternate_devices(void)
 {
 	/* Configure the PPC driver */
-	if (board_has_syv_ppc())
-		PPC_ENABLE_ALTERNATE(ppc_port0_syv);
+	if (board_has_alt_ppc())
+		/* Arg is the USB port number */
+		PPC_ENABLE_ALTERNATE(0);
 }
 DECLARE_HOOK(HOOK_INIT, check_alternate_devices, HOOK_PRIO_DEFAULT);
diff --git a/zephyr/projects/herobrine/src/i2c.c b/zephyr/projects/herobrine/src/i2c.c
index 3f9abe4674..88b722c42d 100644
--- a/zephyr/projects/herobrine/src/i2c.c
+++ b/zephyr/projects/herobrine/src/i2c.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/herobrine/src/usb_pd_policy.c b/zephyr/projects/herobrine/src/usb_pd_policy.c
index a2e353d7d4..adc517d3cb 100644
--- a/zephyr/projects/herobrine/src/usb_pd_policy.c
+++ b/zephyr/projects/herobrine/src/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,8 +13,8 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
@@ -94,11 +94,11 @@ __override int svdm_dp_config(int port, uint32_t *payload)
 	 *  (3) plug a monitor to the port-1 dongle.
 	 */
 
-	payload[0] = VDO(USB_SID_DISPLAYPORT, 1,
-			 CMD_DP_CONFIG | VDO_OPOS(opos));
-	payload[1] = VDO_DP_CFG(pin_mode,      /* pin mode */
-				1,             /* DPv1.3 signaling */
-				2);            /* UFP connected */
+	payload[0] =
+		VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_CONFIG | VDO_OPOS(opos));
+	payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */
+				1, /* DPv1.3 signaling */
+				2); /* UFP connected */
 	return 2;
 };
 
@@ -176,8 +176,7 @@ __override int svdm_dp_attention(int port, uint32_t *payload)
 		 * because of the board USB-C topology (limited to 2
 		 * lanes DP).
 		 */
-		usb_mux_set(port, USB_PD_MUX_DOCK,
-			    USB_SWITCH_CONNECT,
+		usb_mux_set(port, USB_PD_MUX_DOCK, USB_SWITCH_CONNECT,
 			    polarity_rm_dts(pd_get_polarity(port)));
 	} else {
 		/* Disconnect the DP port selection mux. */
@@ -189,13 +188,11 @@ __override int svdm_dp_attention(int port, uint32_t *payload)
 			ppc_set_sbu(port, 0);
 
 		/* Disconnect the DP but keep the USB SS lines in TCPC chip. */
-		usb_mux_set(port, USB_PD_MUX_USB_ENABLED,
-			    USB_SWITCH_CONNECT,
+		usb_mux_set(port, USB_PD_MUX_USB_ENABLED, USB_SWITCH_CONNECT,
 			    polarity_rm_dts(pd_get_polarity(port)));
 	}
 
-	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
-	    (irq || lvl))
+	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && (irq || lvl))
 		/*
 		 * Wake up the AP.  IRQ or level high indicates a DP sink is now
 		 * present.
@@ -222,8 +219,8 @@ __override int svdm_dp_attention(int port, uint32_t *payload)
 		CPRINTS("C%d: Recv IRQ. HPD->1", port);
 
 		/* Set the minimum time delay (2ms) for the next HPD IRQ */
-		svdm_hpd_deadline[port] = get_time().val +
-			HPD_USTREAM_DEBOUNCE_LVL;
+		svdm_hpd_deadline[port] =
+			get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
 	} else if (irq & !lvl) {
 		CPRINTF("ERR:HPD:IRQ&LOW\n");
 		return 0;
@@ -231,8 +228,8 @@ __override int svdm_dp_attention(int port, uint32_t *payload)
 		CPRINTS("C%d: Recv lvl. HPD->%d", port, lvl);
 		gpio_pin_set_dt(hpd, lvl);
 		/* Set the minimum time delay (2ms) for the next HPD IRQ */
-		svdm_hpd_deadline[port] = get_time().val +
-			HPD_USTREAM_DEBOUNCE_LVL;
+		svdm_hpd_deadline[port] =
+			get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
 	}
 
 	return 1;
@@ -248,10 +245,10 @@ __override void svdm_exit_dp_mode(int port)
 
 		/* Signal AP for the HPD low event */
 		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 		CPRINTS("C%d: DP exit. HPD->0", port);
-		gpio_pin_set_dt(
-			GPIO_DT_FROM_NODELABEL(gpio_dp_hot_plug_det_r), 0);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_dp_hot_plug_det_r),
+				0);
 	}
 }
 #endif /* CONFIG_USB_PD_ALT_MODE_DFP */
diff --git a/zephyr/projects/herobrine/src/usbc_config.c b/zephyr/projects/herobrine/src/usbc_config.c
index 41319a75e9..f040ab12cb 100644
--- a/zephyr/projects/herobrine/src/usbc_config.c
+++ b/zephyr/projects/herobrine/src/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -28,9 +28,8 @@
 #include "usbc_ppc.h"
 #include "usbc/ppc.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* GPIO Interrupt Handlers */
 void tcpc_alert_event(enum gpio_signal signal)
@@ -54,9 +53,9 @@ void tcpc_alert_event(enum gpio_signal signal)
 static void usba_oc_deferred(void)
 {
 	/* Use next number after all USB-C ports to indicate the USB-A port */
-	board_overcurrent_event(CONFIG_USB_PD_PORT_MAX_COUNT,
-				!gpio_pin_get_dt(
-				 GPIO_DT_FROM_NODELABEL(gpio_usb_a0_oc_odl)));
+	board_overcurrent_event(
+		CONFIG_USB_PD_PORT_MAX_COUNT,
+		!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_a0_oc_odl)));
 }
 DECLARE_DEFERRED(usba_oc_deferred);
 
@@ -148,7 +147,7 @@ void board_tcpc_init(void)
 	 */
 	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
 		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
 DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_POST_I2C);
 
@@ -194,8 +193,7 @@ void board_overcurrent_event(int port, int is_overcurrented)
 
 int board_set_active_charge_port(int port)
 {
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	int i;
 
 	if (!is_real_port && port != CHARGE_PORT_NONE)
@@ -223,7 +221,6 @@ int board_set_active_charge_port(int port)
 		return EC_ERROR_INVAL;
 	}
 
-
 	CPRINTS("New charge port: p%d", port);
 
 	/*
@@ -247,23 +244,21 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	/*
 	 * Ignore lower charge ceiling on PD transition if our battery is
 	 * critical, as we may brownout.
 	 */
-	if (supplier == CHARGE_SUPPLIER_PD &&
-	    charge_ma < 1500 &&
+	if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 &&
 	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
 		CPRINTS("Using max ilim %d", max_ma);
 		charge_ma = max_ma;
 	}
 
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 uint16_t tcpc_get_alert_status(void)
@@ -272,11 +267,11 @@ uint16_t tcpc_get_alert_status(void)
 
 	if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_pd_int_odl)))
 		if (gpio_pin_get_dt(
-			GPIO_DT_FROM_NODELABEL(gpio_usb_c0_pd_rst_l)))
+			    GPIO_DT_FROM_NODELABEL(gpio_usb_c0_pd_rst_l)))
 			status |= PD_STATUS_TCPC_ALERT_0;
 	if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_pd_int_odl)))
 		if (gpio_pin_get_dt(
-			GPIO_DT_FROM_NODELABEL(gpio_usb_c1_pd_rst_l)))
+			    GPIO_DT_FROM_NODELABEL(gpio_usb_c1_pd_rst_l)))
 			status |= PD_STATUS_TCPC_ALERT_1;
 
 	return status;
diff --git a/zephyr/projects/herobrine/switchcap.dts b/zephyr/projects/herobrine/switchcap.dts
index b246274a7a..ed200a0c6f 100644
--- a/zephyr/projects/herobrine/switchcap.dts
+++ b/zephyr/projects/herobrine/switchcap.dts
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/herobrine/switchcap_hoglin.dts b/zephyr/projects/herobrine/switchcap_hoglin.dts
index 37e1a27e2c..7c083667a1 100644
--- a/zephyr/projects/herobrine/switchcap_hoglin.dts
+++ b/zephyr/projects/herobrine/switchcap_hoglin.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,5 +7,6 @@
 	switchcap {
 		compatible = "switchcap-gpio";
 		enable-pin = <&gpio_switchcap_on>;
+		poff-delay-ms = <550>;
 	};
 };
diff --git a/zephyr/projects/herobrine/usbc_evoker.dts b/zephyr/projects/herobrine/usbc_evoker.dts
new file mode 100644
index 0000000000..20bd48382f
--- /dev/null
+++ b/zephyr/projects/herobrine/usbc_evoker.dts
@@ -0,0 +1,42 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+			bc12 = <&bc12_port0>;
+			ppc = <&ppc_port0>;
+			tcpc = <&tcpc_port0>;
+			chg = <&charger>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_mux_0>;
+			};
+		};
+		usb_mux_0: usb-mux-0 {
+			compatible = "parade,usbc-mux-ps8xxx";
+		};
+
+		port1@1 {
+			compatible = "named-usbc-port";
+			reg = <1>;
+			bc12 = <&bc12_port1>;
+			ppc = <&ppc_port1>;
+			tcpc = <&tcpc_port1>;
+			usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_mux_1>;
+			};
+		};
+		usb_mux_1: usb-mux-1 {
+			compatible = "parade,usbc-mux-ps8xxx";
+		};
+	};
+};
diff --git a/zephyr/projects/herobrine/usbc_herobrine.dts b/zephyr/projects/herobrine/usbc_herobrine.dts
index 153dc44f89..675286ecd7 100644
--- a/zephyr/projects/herobrine/usbc_herobrine.dts
+++ b/zephyr/projects/herobrine/usbc_herobrine.dts
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,31 +11,15 @@
 		port0@0 {
 			compatible = "named-usbc-port";
 			reg = <0>;
-			bc12 {
-				compatible = "pericom,pi3usb9201";
-				status = "okay";
-				irq = <&int_usb_c0_bc12>;
-				port = <&i2c_power>;
-				i2c-addr-flags = "PI3USB9201_I2C_ADDR_3_FLAGS";
+			bc12 = <&bc12_port0>;
+			ppc = <&ppc_port0>;
+			ppc_alt = <&ppc_port0_alt>;
+			tcpc = <&tcpc_port0>;
+			chg = <&charger>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_mux_0>;
 			};
-			ppc_port0: ppc {
-				compatible = "ti,sn5s330";
-				status = "okay";
-				port = <&i2c_tcpc0>;
-				i2c-addr-flags = "SN5S330_ADDR0_FLAGS";
-			};
-			tcpc {
-				compatible = "parade,ps8xxx";
-				status = "okay";
-				port = <&i2c_tcpc0>;
-				i2c-addr-flags = "PS8XXX_I2C_ADDR1_FLAGS";
-			};
-			chg {
-				compatible = "intersil,isl923x";
-				status = "okay";
-				port = <&i2c_charger>;
-			};
-			usb-muxes = <&usb_mux_0>;
 		};
 		usb_mux_0: usb-mux-0 {
 			compatible = "parade,usbc-mux-ps8xxx";
@@ -44,39 +28,16 @@
 		port1@1 {
 			compatible = "named-usbc-port";
 			reg = <1>;
-			bc12 {
-				compatible = "pericom,pi3usb9201";
-				status = "okay";
-				irq = <&int_usb_c1_bc12>;
-				port = <&i2c_eeprom>;
-				i2c-addr-flags = "PI3USB9201_I2C_ADDR_3_FLAGS";
-			};
-			ppc {
-				compatible = "ti,sn5s330";
-				status = "okay";
-				port = <&i2c_tcpc1>;
-				i2c-addr-flags = "SN5S330_ADDR0_FLAGS";
+			bc12 = <&bc12_port1>;
+			ppc = <&ppc_port1>;
+			tcpc = <&tcpc_port1>;
+			usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_mux_1>;
 			};
-			tcpc {
-				compatible = "parade,ps8xxx";
-				status = "okay";
-				port = <&i2c_tcpc1>;
-				i2c-addr-flags = "PS8XXX_I2C_ADDR1_FLAGS";
-			};
-			usb-muxes = <&usb_mux_1>;
 		};
 		usb_mux_1: usb-mux-1 {
 			compatible = "parade,usbc-mux-ps8xxx";
 		};
 	};
-	usbc-alt-chips {
-		ppc_port0_syv: ppc-port0 {
-			compatible = "silergy,syv682x";
-			status = "okay";
-			port = <&i2c_tcpc0>;
-			i2c-addr-flags = "SYV682X_ADDR1_FLAGS";
-			frs_en_gpio = <&gpio_usb_c0_frs_en>;
-			alternate-for = <&ppc_port0>;
-		};
-	};
 };
diff --git a/zephyr/projects/herobrine/usbc_hoglin.dts b/zephyr/projects/herobrine/usbc_hoglin.dts
index 68b262f8ef..20bd48382f 100644
--- a/zephyr/projects/herobrine/usbc_hoglin.dts
+++ b/zephyr/projects/herobrine/usbc_hoglin.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,32 +11,14 @@
 		port0@0 {
 			compatible = "named-usbc-port";
 			reg = <0>;
-			bc12 {
-				compatible = "pericom,pi3usb9201";
-				status = "okay";
-				irq = <&int_usb_c0_bc12>;
-				port = <&i2c_power>;
-				i2c-addr-flags = "PI3USB9201_I2C_ADDR_3_FLAGS";
+			bc12 = <&bc12_port0>;
+			ppc = <&ppc_port0>;
+			tcpc = <&tcpc_port0>;
+			chg = <&charger>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_mux_0>;
 			};
-			ppc_port0: ppc {
-				compatible = "silergy,syv682x";
-				status = "okay";
-				port = <&i2c_tcpc0>;
-				i2c-addr-flags = "SYV682X_ADDR1_FLAGS";
-				frs_en_gpio = <&gpio_usb_c0_frs_en>;
-			};
-			tcpc {
-				compatible = "parade,ps8xxx";
-				status = "okay";
-				port = <&i2c_tcpc0>;
-				i2c-addr-flags = "PS8XXX_I2C_ADDR2_FLAGS";
-			};
-			chg {
-				compatible = "intersil,isl923x";
-				status = "okay";
-				port = <&i2c_charger>;
-			};
-			usb-muxes = <&usb_mux_0>;
 		};
 		usb_mux_0: usb-mux-0 {
 			compatible = "parade,usbc-mux-ps8xxx";
@@ -45,27 +27,13 @@
 		port1@1 {
 			compatible = "named-usbc-port";
 			reg = <1>;
-			bc12 {
-				compatible = "pericom,pi3usb9201";
-				status = "okay";
-				irq = <&int_usb_c1_bc12>;
-				port = <&i2c_eeprom>;
-				i2c-addr-flags = "PI3USB9201_I2C_ADDR_2_FLAGS";
-			};
-			ppc_port1: ppc {
-				compatible = "silergy,syv682x";
-				status = "okay";
-				port = <&i2c_tcpc1>;
-				i2c-addr-flags = "SYV682X_ADDR1_FLAGS";
-				frs_en_gpio = <&gpio_usb_c1_frs_en>;
-			};
-			tcpc {
-				compatible = "parade,ps8xxx";
-				status = "okay";
-				port = <&i2c_tcpc1>;
-				i2c-addr-flags = "PS8XXX_I2C_ADDR2_FLAGS";
+			bc12 = <&bc12_port1>;
+			ppc = <&ppc_port1>;
+			tcpc = <&tcpc_port1>;
+			usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_mux_1>;
 			};
-			usb-muxes = <&usb_mux_1>;
 		};
 		usb_mux_1: usb-mux-1 {
 			compatible = "parade,usbc-mux-ps8xxx";
diff --git a/zephyr/projects/herobrine/usbc_villager.dts b/zephyr/projects/herobrine/usbc_villager.dts
index 90dd88412c..20bd48382f 100644
--- a/zephyr/projects/herobrine/usbc_villager.dts
+++ b/zephyr/projects/herobrine/usbc_villager.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,32 +11,14 @@
 		port0@0 {
 			compatible = "named-usbc-port";
 			reg = <0>;
-			bc12 {
-				compatible = "pericom,pi3usb9201";
-				status = "okay";
-				irq = <&int_usb_c0_bc12>;
-				port = <&i2c_power>;
-				i2c-addr-flags = "PI3USB9201_I2C_ADDR_3_FLAGS";
+			bc12 = <&bc12_port0>;
+			ppc = <&ppc_port0>;
+			tcpc = <&tcpc_port0>;
+			chg = <&charger>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_mux_0>;
 			};
-			ppc {
-				compatible = "silergy,syv682x";
-				status = "okay";
-				port = <&i2c_tcpc0>;
-				i2c-addr-flags = "SYV682X_ADDR1_FLAGS";
-				frs_en_gpio = <&gpio_usb_c0_frs_en>;
-			};
-			tcpc {
-				compatible = "parade,ps8xxx";
-				status = "okay";
-				port = <&i2c_tcpc0>;
-				i2c-addr-flags = "PS8XXX_I2C_ADDR1_FLAGS";
-			};
-			chg {
-				compatible = "intersil,isl923x";
-				status = "okay";
-				port = <&i2c_charger>;
-			};
-			usb-muxes = <&usb_mux_0>;
 		};
 		usb_mux_0: usb-mux-0 {
 			compatible = "parade,usbc-mux-ps8xxx";
@@ -45,27 +27,13 @@
 		port1@1 {
 			compatible = "named-usbc-port";
 			reg = <1>;
-			bc12 {
-				compatible = "pericom,pi3usb9201";
-				status = "okay";
-				irq = <&int_usb_c1_bc12>;
-				port = <&i2c_eeprom>;
-				i2c-addr-flags = "PI3USB9201_I2C_ADDR_3_FLAGS";
-			};
-			ppc {
-				compatible = "silergy,syv682x";
-				status = "okay";
-				port = <&i2c_tcpc1>;
-				i2c-addr-flags = "SYV682X_ADDR1_FLAGS";
-				frs_en_gpio = <&gpio_usb_c1_frs_en>;
-			};
-			tcpc {
-				compatible = "parade,ps8xxx";
-				status = "okay";
-				port = <&i2c_tcpc1>;
-				i2c-addr-flags = "PS8XXX_I2C_ADDR1_FLAGS";
+			bc12 = <&bc12_port1>;
+			ppc = <&ppc_port1>;
+			tcpc = <&tcpc_port1>;
+			usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_mux_1>;
 			};
-			usb-muxes = <&usb_mux_1>;
 		};
 		usb_mux_1: usb-mux-1 {
 			compatible = "parade,usbc-mux-ps8xxx";
diff --git a/zephyr/projects/intelrvp/BUILD.py b/zephyr/projects/intelrvp/BUILD.py
index 755b6479a6..e6e617ea23 100644
--- a/zephyr/projects/intelrvp/BUILD.py
+++ b/zephyr/projects/intelrvp/BUILD.py
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -43,7 +43,6 @@ register_intelrvp_project(
     chip="npcx9m7f",
     extra_dts_overlays=[
         here / "adlrvp/adlrvp_npcx/adlrvp_npcx.dts",
-        here / "adlrvp/adlrvp_npcx/cbi_eeprom.dts",
         here / "adlrvp/adlrvp_npcx/fan.dts",
         here / "adlrvp/adlrvp_npcx/gpio.dts",
         here / "adlrvp/adlrvp_npcx/interrupts.dts",
@@ -62,17 +61,18 @@ register_intelrvp_project(
     project_name="mtlrvpp_npcx",
     chip="npcx9m3f",
     extra_dts_overlays=[
-        here / "adlrvp/adlrvp_npcx/cbi_eeprom.dts",
         here / "mtlrvp/mtlrvpp_npcx/fan.dts",
         here / "mtlrvp/mtlrvpp_npcx/gpio.dts",
         here / "mtlrvp/mtlrvpp_npcx/keyboard.dts",
         here / "mtlrvp/mtlrvpp_npcx/interrupts.dts",
         here / "mtlrvp/ioex.dts",
         here / "mtlrvp/mtlrvpp_npcx/mtlrvp_npcx.dts",
+        here / "mtlrvp/mtlrvpp_npcx/mtlrvp_npcx_power_signals.dts",
         here / "adlrvp/adlrvp_npcx/temp_sensor.dts",
+        here / "mtlrvp/usbc.dts",
     ],
     extra_kconfig_files=[
-        here / "legacy_ec_pwrseq.conf",
+        here / "zephyr_ap_pwrseq.conf",
         here / "mtlrvp/mtlrvpp_npcx/prj.conf",
     ],
 )
diff --git a/zephyr/projects/intelrvp/CMakeLists.txt b/zephyr/projects/intelrvp/CMakeLists.txt
index f8a76be55d..25b3af3931 100644
--- a/zephyr/projects/intelrvp/CMakeLists.txt
+++ b/zephyr/projects/intelrvp/CMakeLists.txt
@@ -1,10 +1,10 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 cmake_minimum_required(VERSION 3.13.1)
 
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
 project(intelrvp)
 
 cros_ec_library_include_directories(include)
@@ -26,4 +26,7 @@ endif()
 if(DEFINED CONFIG_BOARD_MTLRVP_NPCX)
   add_subdirectory(mtlrvp)
   zephyr_library_sources("src/intelrvp.c")
+  zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/usb_pd_policy_mecc_1_1.c")
+  zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/chg_usb_pd_mecc_1_1.c")
+  zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/chg_usb_pd.c")
 endif()
diff --git a/zephyr/projects/intelrvp/Kconfig b/zephyr/projects/intelrvp/Kconfig
index 1c8ec22073..c51c54847b 100644
--- a/zephyr/projects/intelrvp/Kconfig
+++ b/zephyr/projects/intelrvp/Kconfig
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/projects/intelrvp/adlrvp/CMakeLists.txt b/zephyr/projects/intelrvp/adlrvp/CMakeLists.txt
index bd961ff89d..71dee29552 100644
--- a/zephyr/projects/intelrvp/adlrvp/CMakeLists.txt
+++ b/zephyr/projects/intelrvp/adlrvp/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/adlrvp_npcx.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/adlrvp_npcx.dts
index 418b68a8d7..79723beabd 100644
--- a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/adlrvp_npcx.dts
+++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/adlrvp_npcx.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,37 +20,28 @@
 	named-i2c-ports {
 		compatible = "named-i2c-ports";
 
-		battery {
-			i2c-port = <&i2c7_0>;
-			enum-name = "I2C_PORT_BATTERY";
-		};
 		i2c_charger: charger {
 			i2c-port = <&i2c7_0>;
-			enum-name = "I2C_PORT_CHARGER";
-		};
-		eeprom {
-			i2c-port = <&i2c7_0>;
-			enum-name = "I2C_PORT_EEPROM";
-		};
-		port80 {
-			i2c-port = <&i2c7_0>;
-			enum-name = "I2C_PORT_PORT80";
+			enum-names = "I2C_PORT_BATTERY",
+				"I2C_PORT_CHARGER",
+				"I2C_PORT_EEPROM",
+				"I2C_PORT_PORT80";
 		};
 		typec_0: typec-0 {
 			i2c-port = <&i2c0_0>;
-			enum-name = "I2C_PORT_TYPEC_0";
+			enum-names = "I2C_PORT_TYPEC_0";
 		};
 		typec_1: typec-1 {
 			i2c-port = <&i2c2_0>;
-			enum-name = "I2C_PORT_TYPEC_1";
+			enum-names = "I2C_PORT_TYPEC_1";
 		};
 		typec_2: typec-2 {
 			i2c-port = <&i2c1_0>;
-			enum-name = "I2C_PORT_TYPEC_2";
+			enum-names = "I2C_PORT_TYPEC_2";
 		};
 		typec_3: typec-3 {
 			i2c-port = <&i2c3_0>;
-			enum-name = "I2C_PORT_TYPEC_3";
+			enum-names = "I2C_PORT_TYPEC_3";
 		};
 	};
 
@@ -58,22 +49,18 @@
 		compatible = "named-adc-channels";
 
 		adc_ambient: ambient {
-			label = "ADC_TEMP_SNS_AMBIENT";
 			enum-name = "ADC_TEMP_SENSOR_1";
 			io-channels = <&adc0 3>;
 		};
 		adc_ddr: ddr {
-			label = "ADC_TEMP_SNS_DDR";
 			enum-name = "ADC_TEMP_SENSOR_2";
 			io-channels = <&adc0 4>;
 		};
 		adc_skin: skin {
-			label = "ADC_TEMP_SNS_SKIN";
 			enum-name = "ADC_TEMP_SENSOR_3";
 			io-channels = <&adc0 2>;
 		};
 		adc_vr: vr {
-			label = "ADC_TEMP_SNS_VR";
 			enum-name = "ADC_TEMP_SENSOR_4";
 			io-channels = <&adc0 1>;
 		};
@@ -130,6 +117,21 @@
 		reg = <0x38>;
 		label = "MAX695X_SEVEN_SEG_DISPLAY";
 	};
+
+	charger: isl9241@9 {
+		compatible = "intersil,isl9241";
+		status = "okay";
+		reg = <0x9>;
+	};
+
+	cbi_eeprom: eeprom@50 {
+		compatible = "atmel,at24";
+		reg = <0x50>;
+		size = <2048>;
+		pagesize = <16>;
+		address-width = <8>;
+		timeout = <5>;
+	};
 };
 
 &i2c_ctrl7 {
@@ -142,6 +144,25 @@
 	clock-frequency = <I2C_BITRATE_FAST>;
 	pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>;
 	pinctrl-names = "default";
+
+	tcpc_port0: fusb302@22 {
+		compatible = "fairchild,fusb302";
+		reg = <0x22>;
+	};
+
+	usb_c0_soc_side_bb_retimer: jhl8040r-c0-soc-side@54 {
+		compatible = "intel,jhl8040r";
+		reg = <0x54>;
+		reset-pin = <&usb_c0_bb_retimer_rst>;
+		ls-en-pin = <&usb_c0_bb_retimer_ls_en>;
+	};
+
+	usb_c0_bb_retimer: jhl8040r-c0@56 {
+		compatible = "intel,jhl8040r";
+		reg = <0x56>;
+		reset-pin = <&usb_c0_bb_retimer_rst>;
+		ls-en-pin = <&usb_c0_bb_retimer_ls_en>;
+	};
 };
 
 &i2c_ctrl0 {
@@ -154,6 +175,25 @@
 	clock-frequency = <I2C_BITRATE_FAST>;
 	pinctrl-0 = <&i2c2_0_sda_scl_gp91_92>;
 	pinctrl-names = "default";
+
+	tcpc_port1: fusb302@22 {
+		compatible = "fairchild,fusb302";
+		reg = <0x22>;
+	};
+
+	usb_c1_soc_side_bb_retimer: jhl8040r-c1-soc-side@55 {
+		compatible = "intel,jhl8040r";
+		reg = <0x55>;
+		reset-pin = <&usb_c1_bb_retimer_rst>;
+		ls-en-pin = <&usb_c1_bb_retimer_ls_en>;
+	};
+
+	usb_c1_bb_retimer: jhl8040r-c1@57 {
+		compatible = "intel,jhl8040r";
+		reg = <0x57>;
+		reset-pin = <&usb_c1_bb_retimer_rst>;
+		ls-en-pin = <&usb_c1_bb_retimer_ls_en>;
+	};
 };
 
 &i2c_ctrl2 {
@@ -166,6 +206,18 @@
 	clock-frequency = <I2C_BITRATE_FAST>;
 	pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>;
 	pinctrl-names = "default";
+
+	tcpc_port2: fusb302@22 {
+		compatible = "fairchild,fusb302";
+		reg = <0x22>;
+	};
+
+	usb_c2_bb_retimer: jhl8040r-c2@58 {
+		compatible = "intel,jhl8040r";
+		reg = <0x58>;
+		reset-pin = <&usb_c2_bb_retimer_rst>;
+		ls-en-pin = <&usb_c2_bb_retimer_ls_en>;
+	};
 };
 
 &i2c_ctrl1 {
@@ -178,6 +230,18 @@
 	clock-frequency = <I2C_BITRATE_FAST>;
 	pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>;
 	pinctrl-names = "default";
+
+	tcpc_port3: fusb302@22 {
+		compatible = "fairchild,fusb302";
+		reg = <0x22>;
+	};
+
+	usb_c3_bb_retimer: jhl8040r-c3@59 {
+		compatible = "intel,jhl8040r";
+		reg = <0x59>;
+		reset-pin = <&usb_c3_bb_retimer_rst>;
+		ls-en-pin = <&usb_c3_bb_retimer_ls_en>;
+	};
 };
 
 &i2c_ctrl3 {
diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/cbi_eeprom.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/cbi_eeprom.dts
deleted file mode 100644
index efded14c3e..0000000000
--- a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/cbi_eeprom.dts
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-&i2c7_0 {
-	cbi_eeprom: eeprom@50 {
-		compatible = "atmel,at24";
-		reg = <0x50>;
-		label = "EEPROM_CBI";
-		size = <2048>;
-		pagesize = <16>;
-		address-width = <8>;
-		timeout = <5>;
-	};
-};
diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/fan.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/fan.dts
index 23f72dde94..8babe53903 100644
--- a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/fan.dts
+++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/fan.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,7 +9,6 @@
 
 		fan_0 {
 			pwms = <&pwm3 0 PWM_KHZ(30) PWM_POLARITY_NORMAL>;
-			pwm-frequency = <30000>;
 			rpm_min = <3000>;
 			rpm_start = <3000>;
 			rpm_max = <10000>;
diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/gpio.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/gpio.dts
index 7e1cb9c704..1d38fc877c 100644
--- a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/gpio.dts
+++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/gpio.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -124,6 +124,7 @@
 		ec-ds3 {
 			gpios = <&gpioc 4 GPIO_OUTPUT_LOW>;
 			enum-name = "GPIO_EN_PP3300_A";
+			alias = "GPIO_TEMP_SENSOR_POWER";
 		};
 		pch-pwrok-ec {
 			gpios = <&gpioa 0 GPIO_INPUT>;
@@ -319,11 +320,9 @@
 		};
 		usb-c2-usb-mux-cntrl-1 {
 			gpios = <&ioex_c2_port 4 GPIO_OUTPUT_LOW>;
-			enum-name = "IOEX_USB_C2_USB_MUX_CNTRL_1";
 		};
 		usb-c2-usb-mux-cntrl-0 {
 			gpios = <&ioex_c2_port 5 GPIO_OUTPUT_LOW>;
-			enum-name = "IOEX_USB_C2_USB_MUX_CNTRL_0";
 		};
 		usb_c3_bb_retimer_rst: usb-c3-bb-retimer-rst {
 			gpios = <&ioex_c3_port 0 GPIO_OUTPUT_LOW>;
@@ -337,5 +336,9 @@
 			gpios = <&ioex_c3_port 8 GPIO_OUTPUT_HIGH>;
 			enum-name = "IOEX_USB_C2_C3_OC";
 		};
+		/* unimplemented GPIOs */
+		en-pp5000 {
+			enum-name = "GPIO_EN_PP5000";
+		};
 	};
 };
diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/interrupts.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/interrupts.dts
index e0992ef3b3..d7bb40fad2 100644
--- a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/interrupts.dts
+++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/interrupts.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/keyboard.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/keyboard.dts
index e735234128..81d6e82f48 100644
--- a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/keyboard.dts
+++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/keyboard.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/prj.conf b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/prj.conf
index 32919ea399..2c98fd9330 100644
--- a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/prj.conf
+++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/prj.conf
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/pwm_leds.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/pwm_leds.dts
index 50a08a300e..eb1576dbff 100644
--- a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/pwm_leds.dts
+++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/pwm_leds.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,10 +7,10 @@
 	pwmleds {
 		compatible = "pwm-leds";
 		pwm_led0: pwm_led_0 {
-			pwms = <&pwm4 0 0 PWM_POLARITY_INVERTED>;
+			pwms = <&pwm4 0 PWM_HZ(4800) PWM_POLARITY_INVERTED>;
 		};
 		pwm_led1: pwm_led_1 {
-			pwms = <&pwm5 0 0 PWM_POLARITY_INVERTED>;
+			pwms = <&pwm5 0 PWM_HZ(4800) PWM_POLARITY_INVERTED>;
 		};
 	};
 
@@ -18,7 +18,6 @@
 		compatible = "cros-ec,pwm-leds";
 
 		leds = <&pwm_led0 &pwm_led1>;
-		frequency = <4800>;
 
 		color-map-green  = <100>;
 
diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/temp_sensor.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/temp_sensor.dts
index a2fcacc1e1..93ecaa02f6 100644
--- a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/temp_sensor.dts
+++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/temp_sensor.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,19 +6,36 @@
 #include <cros/thermistor/thermistor.dtsi>
 
 / {
+	temp_ambient: ambient {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V0_22K6_47K_4050B>;
+		adc = <&adc_ambient>;
+	};
+	temp_ddr: ddr {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V0_22K6_47K_4050B>;
+		adc = <&adc_ddr>;
+	};
+	temp_skin: skin {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V0_22K6_47K_4050B>;
+		adc = <&adc_skin>;
+	};
+	temp_vr: vr {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V0_22K6_47K_4050B>;
+		adc = <&adc_vr>;
+	};
+
 	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
 		ambient {
-			compatible = "cros-ec,temp-sensor-thermistor",
-				     "cros-ec,temp-sensor";
-			thermistor = <&thermistor_3V0_22K6_47K_4050B>;
-			label = "Ambient";
-			enum-name = "TEMP_SENSOR_1";
 			temp_fan_off = <15>;
 			temp_fan_max = <50>;
 			temp_host_high = <75>;
 			temp_host_halt = <80>;
 			temp_host_release_high = <65>;
-			adc = <&adc_ambient>;
+			sensor = <&temp_ambient>;
 		};
 
 		/*
@@ -30,7 +47,6 @@
 		 *	compatible = "cros-ec,temp-sensor-thermistor",
 		 *		     "cros-ec,temp-sensor";
 		 *	thermistor = < >;
-		 *	label = "Battery";
 		 *	enum-name = "";
 		 *	temp_fan_off = <15>;
 		 *	temp_fan_max = <50>;
@@ -42,43 +58,28 @@
 		 */
 
 		ddr {
-			compatible = "cros-ec,temp-sensor-thermistor",
-				     "cros-ec,temp-sensor";
-			thermistor = <&thermistor_3V0_22K6_47K_4050B>;
-			label = "DDR";
-			enum-name = "TEMP_SENSOR_2";
 			temp_fan_off = <15>;
 			temp_fan_max = <50>;
 			temp_host_high = <75>;
 			temp_host_halt = <80>;
 			temp_host_release_high = <65>;
-			adc = <&adc_ddr>;
+			sensor = <&temp_ddr>;
 		};
 		skin {
-			compatible = "cros-ec,temp-sensor-thermistor",
-				     "cros-ec,temp-sensor";
-			thermistor = <&thermistor_3V0_22K6_47K_4050B>;
-			label = "Skin";
-			enum-name = "TEMP_SENSOR_3";
 			temp_fan_off = <15>;
 			temp_fan_max = <50>;
 			temp_host_high = <75>;
 			temp_host_halt = <80>;
 			temp_host_release_high = <65>;
-			adc = <&adc_skin>;
+			sensor = <&temp_skin>;
 		};
 		vr {
-			compatible = "cros-ec,temp-sensor-thermistor",
-				     "cros-ec,temp-sensor";
-			thermistor = <&thermistor_3V0_22K6_47K_4050B>;
-			label = "VR";
-			enum-name = "TEMP_SENSOR_4";
 			temp_fan_off = <15>;
 			temp_fan_max = <50>;
 			temp_host_high = <75>;
 			temp_host_halt = <80>;
 			temp_host_release_high = <65>;
-			adc = <&adc_vr>;
+			sensor = <&temp_vr>;
 		};
 	};
 };
diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/usbc.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/usbc.dts
index cd7c2b050f..471a1f52e9 100644
--- a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/usbc.dts
+++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/usbc.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,27 +10,22 @@
 		usbc_port0: port0@0 {
 			compatible = "named-usbc-port";
 			reg = <0>;
-			tcpc {
-				compatible = "fairchild,fusb302";
-				status = "okay";
-				port = <&typec_0>;
-				i2c-addr-flags = "FUSB302_I2C_ADDR_FLAGS";
+			tcpc = <&tcpc_port0>;
+			chg = <&charger>;
+			usb_mux_chain_0: usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_c0_bb_retimer
+					     &virtual_mux_c0>;
 			};
-			chg {
-				compatible = "intersil,isl9241";
-				status = "okay";
-				port = <&i2c_charger>;
+			usb_mux_alt_chain_0: usb-mux-alt-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				alternative-chain;
+				usb-muxes = <&usb_c0_bb_retimer
+					     &usb_c0_soc_side_bb_retimer
+					     &virtual_mux_c0>;
 			};
-			usb-muxes = <&usb_c0_bb_retimer &virtual_mux_c0>;
 		};
 		port0-muxes {
-			usb_c0_bb_retimer: jhl8040r-c0 {
-				compatible = "intel,jhl8040r";
-				port = <&typec_0>;
-				i2c-addr-flags = <0x56>;
-				reset-pin = <&usb_c0_bb_retimer_rst>;
-				ls-en-pin = <&usb_c0_bb_retimer_ls_en>;
-			};
 			virtual_mux_c0: virtual-mux-c0 {
 				compatible = "cros-ec,usbc-mux-virtual";
 			};
@@ -39,22 +34,21 @@
 		usbc_port1: port1@1 {
 			compatible = "named-usbc-port";
 			reg = <1>;
-			tcpc {
-				compatible = "fairchild,fusb302";
-				status = "okay";
-				port = <&typec_1>;
-				i2c-addr-flags = "FUSB302_I2C_ADDR_FLAGS";
+			tcpc = <&tcpc_port1>;
+			usb_mux_chain_1: usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_c1_bb_retimer
+					     &virtual_mux_c1>;
+			};
+			usb_mux_alt_chain_1: usb-mux-alt-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				alternative-chain;
+				usb-muxes = <&usb_c1_bb_retimer
+					     &usb_c1_soc_side_bb_retimer
+					     &virtual_mux_c1>;
 			};
-			usb-muxes = <&usb_c1_bb_retimer &virtual_mux_c1>;
 		};
 		port1-muxes {
-			usb_c1_bb_retimer: jhl8040r-c1 {
-				compatible = "intel,jhl8040r";
-				port = <&typec_1>;
-				i2c-addr-flags = <0x57>;
-				reset-pin = <&usb_c1_bb_retimer_rst>;
-				ls-en-pin = <&usb_c1_bb_retimer_ls_en>;
-			};
 			virtual_mux_c1: virtual-mux-c1 {
 				compatible = "cros-ec,usbc-mux-virtual";
 			};
@@ -63,22 +57,14 @@
 		port2@2 {
 			compatible = "named-usbc-port";
 			reg = <2>;
-			tcpc {
-				compatible = "fairchild,fusb302";
-				status = "okay";
-				port = <&typec_2>;
-				i2c-addr-flags = "FUSB302_I2C_ADDR_FLAGS";
+			tcpc = <&tcpc_port2>;
+			usb_mux_chain_2: usb-mux-chain-2 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_c2_bb_retimer
+					     &virtual_mux_c2>;
 			};
-			usb-muxes = <&usb_c2_bb_retimer &virtual_mux_c2>;
 		};
 		port2-muxes {
-			usb_c2_bb_retimer: jhl8040r-c2 {
-				compatible = "intel,jhl8040r";
-				port = <&typec_2>;
-				i2c-addr-flags = <0x58>;
-				reset-pin = <&usb_c2_bb_retimer_rst>;
-				ls-en-pin = <&usb_c2_bb_retimer_ls_en>;
-			};
 			virtual_mux_c2: virtual-mux-c2 {
 				compatible = "cros-ec,usbc-mux-virtual";
 			};
@@ -87,22 +73,14 @@
 		port3@3 {
 			compatible = "named-usbc-port";
 			reg = <3>;
-			tcpc {
-				compatible = "fairchild,fusb302";
-				status = "okay";
-				port = <&typec_3>;
-				i2c-addr-flags = "FUSB302_I2C_ADDR_FLAGS";
+			tcpc = <&tcpc_port3>;
+			usb_mux_chain_3: usb-mux-chain-3 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_c3_bb_retimer
+					     &virtual_mux_c3>;
 			};
-			usb-muxes = <&usb_c3_bb_retimer &virtual_mux_c3>;
 		};
 		port3-muxes {
-			usb_c3_bb_retimer: jhl8040r-c3 {
-				compatible = "intel,jhl8040r";
-				port = <&typec_3>;
-				i2c-addr-flags = <0x59>;
-				reset-pin = <&usb_c3_bb_retimer_rst>;
-				ls-en-pin = <&usb_c3_bb_retimer_ls_en>;
-			};
 			virtual_mux_c3: virtual-mux-c3 {
 				compatible = "cros-ec,usbc-mux-virtual";
 			};
diff --git a/zephyr/projects/intelrvp/adlrvp/battery.dts b/zephyr/projects/intelrvp/adlrvp/battery.dts
index 10b43d6baa..1de4111791 100644
--- a/zephyr/projects/intelrvp/adlrvp/battery.dts
+++ b/zephyr/projects/intelrvp/adlrvp/battery.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/intelrvp/adlrvp/include/adlrvp_zephyr.h b/zephyr/projects/intelrvp/adlrvp/include/adlrvp_zephyr.h
index 0061b11110..135fd4ef4f 100644
--- a/zephyr/projects/intelrvp/adlrvp/include/adlrvp_zephyr.h
+++ b/zephyr/projects/intelrvp/adlrvp/include/adlrvp_zephyr.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,27 +10,25 @@
 
 #include "config.h"
 
+#define I2C_ADDR_FUSB302_TCPC_AIC 0x22
+#define I2C_ADDR_SN5S330_TCPC_AIC_PPC 0x40
 
-#define I2C_ADDR_FUSB302_TCPC_AIC       0x22
-#define I2C_ADDR_SN5S330_TCPC_AIC_PPC   0x40
-
-#define I2C_ADDR_PCA9675_TCPC_AIC_IOEX  0x21
-
+#define I2C_ADDR_PCA9675_TCPC_AIC_IOEX 0x21
 
 /* SOC side BB retimers (dual retimer config) */
-#define I2C_PORT0_BB_RETIMER_SOC_ADDR   0x54
+#define I2C_PORT0_BB_RETIMER_SOC_ADDR 0x54
 #if defined(HAS_TASK_PD_C1)
-#define I2C_PORT1_BB_RETIMER_SOC_ADDR   0x55
+#define I2C_PORT1_BB_RETIMER_SOC_ADDR 0x55
 #endif
 
-#define ADLM_LP4_RVP1_SKU_BOARD_ID      0x01
-#define ADLM_LP5_RVP2_SKU_BOARD_ID      0x02
-#define ADLM_LP5_RVP3_SKU_BOARD_ID      0x03
-#define ADLN_LP5_ERB_SKU_BOARD_ID       0x06
-#define ADLN_LP5_RVP_SKU_BOARD_ID       0x07
-#define ADLP_DDR5_RVP_SKU_BOARD_ID      0x12
-#define ADLP_LP5_T4_RVP_SKU_BOARD_ID    0x13
-#define ADL_RVP_BOARD_ID(id)            ((id) & 0x3F)
+#define ADLM_LP4_RVP1_SKU_BOARD_ID 0x01
+#define ADLM_LP5_RVP2_SKU_BOARD_ID 0x02
+#define ADLM_LP5_RVP3_SKU_BOARD_ID 0x03
+#define ADLN_LP5_ERB_SKU_BOARD_ID 0x06
+#define ADLN_LP5_RVP_SKU_BOARD_ID 0x07
+#define ADLP_DDR5_RVP_SKU_BOARD_ID 0x12
+#define ADLP_LP5_T4_RVP_SKU_BOARD_ID 0x13
+#define ADL_RVP_BOARD_ID(id) ((id)&0x3F)
 
 #define CONFIG_BATTERY_TYPE_NO_AUTO_DETECT
 
diff --git a/zephyr/projects/intelrvp/adlrvp/ioex.dts b/zephyr/projects/intelrvp/adlrvp/ioex.dts
index 93117de943..3e2227dacb 100644
--- a/zephyr/projects/intelrvp/adlrvp/ioex.dts
+++ b/zephyr/projects/intelrvp/adlrvp/ioex.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/intelrvp/adlrvp/prj.conf b/zephyr/projects/intelrvp/adlrvp/prj.conf
index 357b0bee66..1314277bc8 100644
--- a/zephyr/projects/intelrvp/adlrvp/prj.conf
+++ b/zephyr/projects/intelrvp/adlrvp/prj.conf
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -71,4 +71,4 @@ CONFIG_GPIO_PCA95XX=y
 CONFIG_PLATFORM_EC_MAX695X_SEVEN_SEGMENT_DISPLAY=y
 
 # eSPI
-CONFIG_PLATFORM_EC_ESPI_DEFAULT_VW_WIDTH_US=150
+CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US=150
diff --git a/zephyr/projects/intelrvp/adlrvp/src/adlrvp.c b/zephyr/projects/intelrvp/adlrvp/src/adlrvp.c
index bcb9bba1a8..ce5196c60d 100644
--- a/zephyr/projects/intelrvp/adlrvp/src/adlrvp.c
+++ b/zephyr/projects/intelrvp/adlrvp/src/adlrvp.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -29,9 +29,8 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-
-#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ##args)
 
 /* TCPC AIC GPIO Configuration */
 const struct tcpc_aic_gpio_config_t tcpc_aic_gpios[] = {
@@ -96,27 +95,6 @@ struct ppc_config_t ppc_chips[] = {
 BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == CONFIG_USB_PD_PORT_MAX_COUNT);
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
-/* USB Mux Configuration for Soc side BB-Retimers for Dual retimer config */
-static struct usb_mux soc_side_bb_retimer0_usb_mux = {
-	.usb_port = TYPE_C_PORT_0,
-	.next_mux = USB_MUX_NEXT_POINTER(DT_NODELABEL(usbc_port0), 0),
-	.driver = &bb_usb_retimer,
-	.hpd_update = bb_retimer_hpd_update,
-	.i2c_port = I2C_PORT_TYPEC_0,
-	.i2c_addr_flags = I2C_PORT0_BB_RETIMER_SOC_ADDR,
-};
-
-#if defined(HAS_TASK_PD_C1)
-static struct usb_mux soc_side_bb_retimer1_usb_mux = {
-	.usb_port = TYPE_C_PORT_1,
-	.next_mux = USB_MUX_NEXT_POINTER(DT_NODELABEL(usbc_port1), 0),
-	.driver = &bb_usb_retimer,
-	.hpd_update = bb_retimer_hpd_update,
-	.i2c_port = I2C_PORT_TYPEC_1,
-	.i2c_addr_flags = I2C_PORT1_BB_RETIMER_SOC_ADDR,
-};
-#endif
-
 /* Cache BB retimer power state */
 static bool cache_bb_enable[CONFIG_USB_PD_PORT_MAX_COUNT];
 
@@ -124,8 +102,8 @@ void board_overcurrent_event(int port, int is_overcurrented)
 {
 	/* Port 0 & 1 and 2 & 3 share same line for over current indication */
 #if defined(HAS_TASK_PD_C2)
-	enum ioex_signal oc_signal = port < TYPE_C_PORT_2 ?
-				IOEX_USB_C0_C1_OC : IOEX_USB_C2_C3_OC;
+	enum ioex_signal oc_signal = port < TYPE_C_PORT_2 ? IOEX_USB_C0_C1_OC :
+							    IOEX_USB_C2_C3_OC;
 #else
 	enum ioex_signal oc_signal = IOEX_USB_C0_C1_OC;
 #endif
@@ -211,11 +189,11 @@ void set_charger_system_voltage(void)
 		 * on AC or AC+battery
 		 */
 		if (extpower_is_present() && battery_is_present()) {
-			bq25710_set_min_system_voltage(CHARGER_SOLO,
-				battery_get_info()->voltage_min);
+			bq25710_set_min_system_voltage(
+				CHARGER_SOLO, battery_get_info()->voltage_min);
 		} else {
-			bq25710_set_min_system_voltage(CHARGER_SOLO,
-				battery_get_info()->voltage_max);
+			bq25710_set_min_system_voltage(
+				CHARGER_SOLO, battery_get_info()->voltage_max);
 		}
 		break;
 
@@ -224,8 +202,7 @@ void set_charger_system_voltage(void)
 		break;
 	}
 }
-DECLARE_HOOK(HOOK_AC_CHANGE, set_charger_system_voltage,
-		HOOK_PRIO_DEFAULT);
+DECLARE_HOOK(HOOK_AC_CHANGE, set_charger_system_voltage, HOOK_PRIO_DEFAULT);
 
 static void configure_charger(void)
 {
@@ -246,26 +223,29 @@ static void configure_charger(void)
 
 static void configure_retimer_usbmux(void)
 {
+	struct usb_mux *mux;
+
 	switch (ADL_RVP_BOARD_ID(board_get_version())) {
 	case ADLN_LP5_ERB_SKU_BOARD_ID:
 	case ADLN_LP5_RVP_SKU_BOARD_ID:
 		/* enable TUSB1044RNQR redriver on Port0  */
-		usb_muxes[TYPE_C_PORT_0].i2c_addr_flags =
-					TUSB1064_I2C_ADDR14_FLAGS;
-		usb_muxes[TYPE_C_PORT_0].driver =
-					&tusb1064_usb_mux_driver;
-		usb_muxes[TYPE_C_PORT_0].hpd_update = tusb1044_hpd_update;
+		mux = USB_MUX_POINTER(DT_NODELABEL(usb_mux_chain_0), 0);
+		mux->i2c_addr_flags = TUSB1064_I2C_ADDR14_FLAGS;
+		mux->driver = &tusb1064_usb_mux_driver;
+		mux->hpd_update = tusb1044_hpd_update;
 
 #if defined(HAS_TASK_PD_C1)
-		usb_muxes[TYPE_C_PORT_1].driver = NULL;
-		usb_muxes[TYPE_C_PORT_1].hpd_update = NULL;
+		mux = USB_MUX_POINTER(DT_NODELABEL(usb_mux_chain_1), 0);
+		mux->driver = NULL;
+		mux->hpd_update = NULL;
 #endif
 		break;
 
 	case ADLP_LP5_T4_RVP_SKU_BOARD_ID:
 		/* No retimer on Port-2 */
 #if defined(HAS_TASK_PD_C2)
-		usb_muxes[TYPE_C_PORT_2].driver = NULL;
+		mux = USB_MUX_POINTER(DT_NODELABEL(usb_mux_chain_2), 0);
+		mux->driver = NULL;
 #endif
 		break;
 
@@ -275,15 +255,13 @@ static void configure_retimer_usbmux(void)
 		 * Change the default usb mux config on runtime to support
 		 * dual retimer topology.
 		 */
-		usb_muxes[TYPE_C_PORT_0].next_mux
-			= &soc_side_bb_retimer0_usb_mux;
+		USB_MUX_ENABLE_ALTERNATIVE(usb_mux_alt_chain_0);
 #if defined(HAS_TASK_PD_C1)
-		usb_muxes[TYPE_C_PORT_1].next_mux
-			= &soc_side_bb_retimer1_usb_mux;
+		USB_MUX_ENABLE_ALTERNATIVE(usb_mux_alt_chain_1);
 #endif
 		break;
 
-	/* Add additional board SKUs */
+		/* Add additional board SKUs */
 
 	default:
 		break;
@@ -357,8 +335,7 @@ __override int board_get_version(void)
 	 * This loop retries to ensure rail is settled and read is successful
 	 */
 	for (i = 0; i < RVP_VERSION_READ_RETRY_CNT; i++) {
-
-		rv  = gpio_pin_get_dt(&bom_id_config[0]);
+		rv = gpio_pin_get_dt(&bom_id_config[0]);
 
 		if (rv >= 0)
 			break;
@@ -374,21 +351,21 @@ __override int board_get_version(void)
 	 * BOM ID [2]   : IOEX[0]
 	 * BOM ID [1:0] : IOEX[15:14]
 	 */
-	bom_id  = gpio_pin_get_dt(&bom_id_config[0]) << 2;
+	bom_id = gpio_pin_get_dt(&bom_id_config[0]) << 2;
 	bom_id |= gpio_pin_get_dt(&bom_id_config[1]) << 1;
 	bom_id |= gpio_pin_get_dt(&bom_id_config[2]);
 
 	/*
 	 * FAB ID [1:0] : IOEX[2:1] + 1
 	 */
-	fab_id  = gpio_pin_get_dt(&fab_id_config[0]) << 1;
+	fab_id = gpio_pin_get_dt(&fab_id_config[0]) << 1;
 	fab_id |= gpio_pin_get_dt(&fab_id_config[1]);
 	fab_id += 1;
 
 	/*
 	 * BOARD ID[5:0] : IOEX[13:8]
 	 */
-	board_id  = gpio_pin_get_dt(&board_id_config[0]) << 5;
+	board_id = gpio_pin_get_dt(&board_id_config[0]) << 5;
 	board_id |= gpio_pin_get_dt(&board_id_config[1]) << 4;
 	board_id |= gpio_pin_get_dt(&board_id_config[2]) << 3;
 	board_id |= gpio_pin_get_dt(&board_id_config[3]) << 2;
@@ -450,4 +427,4 @@ static int board_pre_task_peripheral_init(const struct device *unused)
 	return 0;
 }
 SYS_INIT(board_pre_task_peripheral_init, APPLICATION,
-			CONFIG_APPLICATION_INIT_PRIORITY);
+	 CONFIG_APPLICATION_INIT_PRIORITY);
diff --git a/zephyr/projects/intelrvp/include/gpio_map.h b/zephyr/projects/intelrvp/include/gpio_map.h
deleted file mode 100644
index 3263007880..0000000000
--- a/zephyr/projects/intelrvp/include/gpio_map.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __ZEPHYR_GPIO_MAP_H
-#define __ZEPHYR_GPIO_MAP_H
-
-#define GPIO_EN_PP5000                  GPIO_UNIMPLEMENTED
-#define GPIO_TEMP_SENSOR_POWER          GPIO_EN_PP3300_A
-
-/* TODO: Implement GPIO_ENTERING_RW in IOEX */
-#ifdef CONFIG_BOARD_MTLRVP_NPCX
-#define GPIO_ENTERING_RW		GPIO_UNIMPLEMENTED
-#endif /* CONFIG_BOARD_MTLRVP_NPCK */
-
-#endif /* __ZEPHYR_GPIO_MAP_H */
diff --git a/zephyr/projects/intelrvp/include/intel_rvp_board_id.h b/zephyr/projects/intelrvp/include/intel_rvp_board_id.h
index a527b19364..7825b272e3 100644
--- a/zephyr/projects/intelrvp/include/intel_rvp_board_id.h
+++ b/zephyr/projects/intelrvp/include/intel_rvp_board_id.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/intelrvp/include/intelrvp.h b/zephyr/projects/intelrvp/include/intelrvp.h
index ad6d12ae6f..9b6dc98485 100644
--- a/zephyr/projects/intelrvp/include/intelrvp.h
+++ b/zephyr/projects/intelrvp/include/intelrvp.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,7 +10,7 @@
 #include "stdbool.h"
 
 /* RVP ID read retry count */
-#define RVP_VERSION_READ_RETRY_CNT	2
+#define RVP_VERSION_READ_RETRY_CNT 2
 
 #define DC_JACK_MAX_VOLTAGE_MV 19000
 
diff --git a/zephyr/projects/intelrvp/legacy_ec_pwrseq.conf b/zephyr/projects/intelrvp/legacy_ec_pwrseq.conf
index cdcfbc2b13..331afb637d 100644
--- a/zephyr/projects/intelrvp/legacy_ec_pwrseq.conf
+++ b/zephyr/projects/intelrvp/legacy_ec_pwrseq.conf
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -9,5 +9,4 @@ CONFIG_PLATFORM_EC_POWERSEQ_INTEL=y
 CONFIG_PLATFORM_EC_POWERSEQ_RSMRST_DELAY=y
 CONFIG_PLATFORM_EC_POWERSEQ_S0IX=y
 CONFIG_PLATFORM_EC_POWERSEQ_S4=y
-CONFIG_PLATFORM_EC_BOARD_RESET_AFTER_POWER_ON=y
 CONFIG_PLATFORM_EC_THROTTLE_AP=y
diff --git a/zephyr/projects/intelrvp/mtlrvp/CMakeLists.txt b/zephyr/projects/intelrvp/mtlrvp/CMakeLists.txt
index 75015a1068..c6729af776 100644
--- a/zephyr/projects/intelrvp/mtlrvp/CMakeLists.txt
+++ b/zephyr/projects/intelrvp/mtlrvp/CMakeLists.txt
@@ -1,5 +1,6 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 zephyr_library_sources("src/mtlrvp.c")
+zephyr_library_sources("src/board_power.c")
diff --git a/zephyr/projects/intelrvp/mtlrvp/ioex.dts b/zephyr/projects/intelrvp/mtlrvp/ioex.dts
index bf79b12570..7d2f4b5820 100644
--- a/zephyr/projects/intelrvp/mtlrvp/ioex.dts
+++ b/zephyr/projects/intelrvp/mtlrvp/ioex.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,7 +7,7 @@
 	/* IOEX_KBD_GPIO IT8801 */
 	ioex-kbd-gpio {
 		compatible = "cros,ioex-chip";
-		i2c-port = <&battery>;
+		i2c-port = <&i2c_charger>;
 		i2c-addr = <0x39>;
 		drv = "it8801_ioexpander_drv";
 		flags = <0x00>;
@@ -30,4 +30,42 @@
 			ngpios = <8>;
 		};
 	};
+	/* IOEX_C2_CCGXXF */
+	ioex-c2 {
+		compatible = "cros,ioex-chip";
+		i2c-port = <&typec_aic2>;
+		i2c-addr = <0x0B>;
+		drv = "ccgxxf_ioexpander_drv";
+		flags = <0x00>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		ioex_c2_port0: ioex-c2-port@0 {
+			compatible = "cros,ioex-port";
+			reg = <0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <8>;
+		};
+		ioex_c2_port1: ioex-c2-port@1 {
+			compatible = "cros,ioex-port";
+			reg = <1>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <8>;
+		};
+		ioex_c2_port2: ioex-c2-port@2 {
+			compatible = "cros,ioex-port";
+			reg = <2>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <8>;
+		};
+		ioex_c2_port3: ioex-c2-port@3 {
+			compatible = "cros,ioex-port";
+			reg = <3>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <8>;
+		};
+	};
 };
diff --git a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/fan.dts b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/fan.dts
index 99c2cf10d0..cf85dd3413 100644
--- a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/fan.dts
+++ b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/fan.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,7 +9,6 @@
 
 		fan_0 {
 			pwms = <&pwm3 0 PWM_KHZ(30) PWM_POLARITY_NORMAL>;
-			pwm-frequency = <30000>;
 			rpm_min = <3200>;
 			rpm_start = <2200>;
 			rpm_max = <6600>;
diff --git a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/gpio.dts b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/gpio.dts
index 49a40c6a54..77b4cf0573 100644
--- a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/gpio.dts
+++ b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/gpio.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,7 +20,7 @@
 			enum-name = "GPIO_PG_EC_ALL_SYS_PWRGD";
 		};
 		rsmrst_pwrgd: rsmrst-pwrgd {
-			gpios = <&gpio6 6 GPIO_INPUT>; /* 1.8V */
+			gpios = <&gpio6 6 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
 			enum-name = "GPIO_PG_EC_RSMRST_ODL";
 		};
 		pch_slp_s0_n: pch-slp-s0-n-ec {
@@ -53,32 +53,33 @@
 		gpio_wp: wp-l {
 			gpios = <&gpiod 5 GPIO_INPUT>;
 		};
-		std-adp-prsnt {
+		std_adp_prsnt: std-adp-prsnt {
 			gpios = <&gpioc 6 GPIO_INPUT>;
+			enum-name = "GPIO_DC_JACK_PRESENT";
 		};
 		bc_acok: bc-acok-ec {
 			gpios = <&gpio0 2 GPIO_INPUT>;
 			enum-name = "GPIO_AC_PRESENT";
 		};
-		usbc-tcpc-alrt-p0 {
+		usbc_tcpc_alrt_p0: usbc-tcpc-alrt-p0 {
 			gpios = <&gpio4 0 GPIO_INPUT>;
 		};
 		/* NOTE: Netname is USBC_TCPC_PPC_ALRT_P0 */
-		usb-c0-c1-tcpc-rst-odl {
+		usb_c0_c1_tcpc_rst_odl: usb-c0-c1-tcpc-rst-odl {
 			gpios = <&gpiod 0 GPIO_ODR_HIGH>;
 		};
 		/* NOTE: Netname is USBC_TCPC_ALRT_P1 */
-		usbc-tcpc-ppc-alrt-p0 {
+		usbc_tcpc_ppc_alrt_p0: usbc-tcpc-ppc-alrt-p0 {
 			gpios = <&gpiod 1 GPIO_INPUT>;
 		};
-		usbc-tcpc-ppc-alrt-p1 {
+		usbc_tcpc_ppc_alrt_p1: usbc-tcpc-ppc-alrt-p1 {
 			gpios = <&gpioe 4 GPIO_INPUT>;
 		};
-		usbc-tcpc-alrt-p2 {
+		usbc_tcpc_alrt_p2: usbc-tcpc-alrt-p2 {
 			gpios = <&gpio9 1 GPIO_INPUT>;
 		};
 		/* NOTE: Netname is USBC_TCPC_PPC_ALRT_P3 */
-		usbc-tcpc-ppc-alrt-p3 {
+		usbc_tcpc_alrt_p3: usbc-tcpc-alrt-p3 {
 			gpios = <&gpiof 3 GPIO_INPUT>;
 		};
 		gpio_ec_pch_wake_odl: pch-wake-n {
@@ -97,11 +98,11 @@
 			gpios = <&gpio6 0 GPIO_INPUT>;
 			enum-name = "GPIO_CPU_PROCHOT";
 		};
-		sys-rst-odl-ec {
+		sys_rst_odl: sys-rst-odl-ec {
 			gpios = <&gpioc 5 GPIO_ODR_HIGH>;
 			enum-name = "GPIO_SYS_RESET_L";
 		};
-		pm-rsmrst-r-n {
+		ec_pch_rsmrst_l: pm-rsmrst-r-n {
 			gpios = <&gpioa 4 GPIO_OUTPUT_LOW>; /* 1.8V */
 			enum-name = "GPIO_PCH_RSMRST_L";
 		};
@@ -112,11 +113,12 @@
 		ec_spi_oe_mecc: ec-spi-oe-mecc-r {
 			gpios = <&gpioa 7 GPIO_OUTPUT_LOW>; /* 1.8V */
 		};
-		ec-ds3-r {
+		en_pp3300_a: ec-ds3-r {
 			gpios = <&gpioc 4 GPIO_OUTPUT_LOW>;
 			enum-name = "GPIO_EN_PP3300_A";
+			alias = "GPIO_TEMP_SENSOR_POWER";
 		};
-		pch-pwrok-ec-r {
+		ec_pch_pwrok_od: pch-pwrok-ec-r {
 			gpios = <&gpiod 3 GPIO_ODR_LOW>;
 			enum-name = "GPIO_PCH_PWROK";
 		};
@@ -142,8 +144,9 @@
 			gpios = <&gpioc 0 GPIO_OUTPUT_LOW>;
 		};
 		/* NOTE: Netname is USBC_TCPC_ALRT_P3 */
-		ccd-mode-odl {
+		ccd_mode_odl: ccd-mode-odl {
 			gpios = <&gpio9 2 GPIO_INPUT>;
+			enum-name = "GPIO_CCD_MODE_ODL";
 		};
 		smb-bs-clk {
 			gpios = <&gpiob 3 GPIO_INPUT>;
@@ -158,10 +161,10 @@
 			gpios = <&gpiob 4 GPIO_INPUT>;
 		};
 		usbc-tcpc-i2c-clk-aic2 {
-			gpios = <&gpio9 0 GPIO_INPUT>;
+			gpios = <&gpio9 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
 		};
 		usbc-tcpc-i2c-data-aic2 {
-			gpios = <&gpio8 7 GPIO_INPUT>;
+			gpios = <&gpio8 7 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
 		};
 		/* Unused 1.8V pins */
 		i3c-1-sda-r {
@@ -189,22 +192,22 @@
 			gpios = <&gpioa 6 GPIO_INPUT>;
 		};
 		sml1-clk-mecc {
-			gpios = <&gpio3 3 GPIO_INPUT>;
+			gpios = <&gpio3 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
 		};
 		sml1-data-mecc {
-			gpios = <&gpio3 6 GPIO_INPUT>;
+			gpios = <&gpio3 6 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
 		};
 		sml1-alert {
-			gpios = <&gpioc 7 GPIO_INPUT>;
+			gpios = <&gpioc 7 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
 		};
 		smb-pch-alrt {
 			gpios = <&gpioa 3 GPIO_INPUT>;
 		};
 		smb-pch-data {
-			gpios = <&gpioc 1 GPIO_INPUT>;
+			gpios = <&gpioc 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
 		};
 		smb-pch-clk {
-			gpios = <&gpioc 2 GPIO_INPUT>;
+			gpios = <&gpioc 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
 		};
 		/* Unused 3.3V pins */
 		cpu-cat-err-mecc {
@@ -255,7 +258,7 @@
 		tp-gpiof1 {
 			gpios = <&gpiof 1 GPIO_INPUT>;
 		};
-		usbc-tcpc-ppc-alrt-p2 {
+		usbc_tcpc_ppc_alrt_p2: usbc-tcpc-ppc-alrt-p2 {
 			gpios = <&gpiof 2 GPIO_INPUT>;
 		};
 		tp-gpiof4 {
@@ -285,80 +288,79 @@
 		};
 
 		/* USB C IOEX configuration */
-		usb-c0-hbr-ls-en {
+		usb_c0_hb_retimer_ls_en: usb-c0-hbr-ls-en {
 			gpios = <&ioex_c0 2 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C0_HBR_LS_EN";
+			no-auto-init;
 		};
-		usb-c0-hbr-rst {
+		usb_c0_hb_retimer_rst: usb-c0-hbr-rst {
 			gpios = <&ioex_c0 3 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C0_HBR_RST";
+			no-auto-init;
 		};
-		usb-c1-hbr-ls-en {
+		usb_c1_hb_retimer_ls_en: usb-c1-hbr-ls-en {
 			gpios = <&ioex_c1 2 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C1_HBR_LS_EN";
+			no-auto-init;
 		};
-		usb-c1-hbr-rst {
+		usb_c1_hb_retimer_rst: usb-c1-hbr-rst {
 			gpios = <&ioex_c1 3 GPIO_OUTPUT_LOW>;
+			enum-name = "IOEX_USB_C1_HBR_RST";
+			no-auto-init;
 		};
 		usb-c0-mux-oe-n {
 			gpios = <&ioex_c0 4 GPIO_OUTPUT_LOW>;
+			no-auto-init;
 		};
 		usb-c0-mux-sbu-sel-0 {
 			gpios = <&ioex_c0 6 GPIO_OUTPUT_HIGH>;
+			enum-name = "IOEX_USB_C0_MUX_SBU_SEL_0";
+			no-auto-init;
 		};
 		usb-c0-mux-sbu-sel-1 {
 			gpios = <&ioex_c1 4 GPIO_OUTPUT_LOW>;
-		};
-	};
-
-	def-lvol-io-list {
-		compatible = "nuvoton,npcx-lvolctrl-def";
-		lvol-io-pads = <
-			&lvol_io66 /* RSMRET_PWRGD */
-			&lvol_io90 /* I2C1_SCL0 */
-			&lvol_io87 /* I2C1_SDA0 */
-			&lvol_io33 /* SML1_CLK_MECC */
-			&lvol_io36 /* SML1_DATA_MECC */
-			&lvol_ioc7 /* SML1_ALERT */
-			&lvol_ioc1 /* SMB_PCH_DATA */
-			&lvol_ioc2 /* SMB_PCH_CLK */
-		>;
-	};
-};
-
-&i2c0_0 {
-	nct38xx_C0:nct38xx_C0@70 {
-	#address-cells = <1>;
-	#size-cells = <0>;
-	compatible = "nuvoton,nct38xx-gpio";
-	reg = <0x70>;
-	label = "NCT38XX_C0";
-
-	ioex_c0:gpio@0 {
-			compatible = "nuvoton,nct38xx-gpio-port";
-			reg = <0x0>;
-			label = "NCT38XX_C0_GPIO0";
-			gpio-controller;
-			#gpio-cells = <2>;
-			ngpios = <8>;
-			pin_mask = <0xff>;
-			pinmux_mask = <0xf7>;
-		};
-	};
-
-	nct38xx_C1:nct38xx_C1@70 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "nuvoton,nct38xx-gpio";
-		reg = <0x70>;
-		label = "NCT38XX_C1";
-
-		ioex_c1:gpio@0 {
-			compatible = "nuvoton,nct38xx-gpio-port";
-			reg = <0x0>;
-			label = "NCT38XX_C1_GPIO0";
-			gpio-controller;
-			#gpio-cells = <2>;
-			ngpios = <8>;
-			pin_mask = <0xff>;
-			pinmux_mask = <0xf7>;
+			enum-name = "IOEX_USB_C0_MUX_SBU_SEL_1";
+			no-auto-init;
+		};
+		usb-c0-c1-prochot-n {
+			gpios = <&ioex_c1 6 GPIO_INPUT>;
+			no-auto-init;
+		};
+		dg-bssb-sbu-sel {
+			gpios = <&ioex_c2_port1 4 GPIO_INPUT>;
+			no-auto-init;
+		};
+		usb_c2_hb_retimer_rst: usb-c2-hbr-rst {
+			gpios = <&ioex_c2_port1 1 (GPIO_ODR_LOW | \
+				GPIO_VOLTAGE_1P8)>;
+			enum-name = "IOEX_USB_C2_HBR_RST";
+			no-auto-init;
+		};
+		usb_c2_hb_retimer_ls_en: usb-c2-hbr-ls-en {
+			gpios = <&ioex_c2_port2 0 (GPIO_ODR_LOW | \
+				GPIO_VOLTAGE_1P8)>;
+			enum-name = "IOEX_USB_C2_HBR_LS_EN";
+			no-auto-init;
+		};
+		usb_c3_hb_retimer_rst: usb-c3-hbr-rst {
+			gpios = <&ioex_c2_port1 3 (GPIO_ODR_LOW | \
+				GPIO_VOLTAGE_1P8)>;
+			enum-name = "IOEX_USB_C3_HBR_RST";
+			no-auto-init;
+		};
+		usb_c3_hb_retimer_ls_en: usb-c3-hbr-ls-en {
+			gpios = <&ioex_c2_port3 3 (GPIO_ODR_LOW | \
+				GPIO_VOLTAGE_1P8)>;
+			enum-name = "IOEX_USB_C3_HBR_LS_EN";
+			no-auto-init;
+		};
+		usb-c2-c3-prochot-n {
+			gpios = <&ioex_c2_port0 0 GPIO_INPUT>;
+			no-auto-init;
+		};
+		/* unimplemented GPIOs */
+		en-pp5000 {
+			enum-name = "GPIO_EN_PP5000";
 		};
 	};
 };
diff --git a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/interrupts.dts b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/interrupts.dts
index 234acb3447..b120f6c05e 100644
--- a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/interrupts.dts
+++ b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/interrupts.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,25 +21,40 @@
 			flags = <GPIO_INT_EDGE_BOTH>;
 			handler = "extpower_interrupt";
 		};
-		int_slp_s0: slp_s0 {
-			irq-pin = <&pch_slp_s0_n>;
-			flags = <GPIO_INT_EDGE_BOTH>;
-			handler = "power_signal_interrupt";
-		};
-		int_rsmrst_pwrgd: rsmrst_pwrgd {
-			irq-pin = <&rsmrst_pwrgd>;
-			flags = <GPIO_INT_EDGE_BOTH>;
-			handler = "power_signal_interrupt";
-		};
-		int_all_sys_pwrgd: all_sys_pwrgd {
-			irq-pin = <&all_sys_pwrgd>;
-			flags = <GPIO_INT_EDGE_BOTH>;
-			handler = "power_signal_interrupt";
-		};
 		int_ioex_kbd_intr_n: ioex_kbd_intr_n {
 			irq-pin = <&ioex_kbd_intr_n>;
 			flags = <GPIO_INT_EDGE_FALLING>;
 			handler = "io_expander_it8801_interrupt";
 		};
+		int_usb_c0_c1_tcpc: usb_c0_tcpc {
+			irq-pin = <&usbc_tcpc_alrt_p0>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "tcpc_alert_event";
+		};
+		int_usb_c0_ppc: usb_c0_ppc {
+			irq-pin = <&usbc_tcpc_ppc_alrt_p0>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "ppc_interrupt";
+		};
+		int_usb_c1_ppc: usb_c1_ppc {
+			irq-pin = <&usbc_tcpc_ppc_alrt_p1>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "ppc_interrupt";
+		};
+		int_usb_c2_tcpc: usb_c2_tcpc {
+			irq-pin = <&usbc_tcpc_alrt_p2>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "tcpc_alert_event";
+		};
+		int_usb_c3_tcpc: usb_c3_tcpc {
+			irq-pin = <&usbc_tcpc_alrt_p3>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "tcpc_alert_event";
+		};
+		int_ccd_mode: ccd_mode {
+			irq-pin = <&ccd_mode_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "board_connect_c0_sbu";
+		};
 	};
 };
diff --git a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/keyboard.dts b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/keyboard.dts
index e735234128..81d6e82f48 100644
--- a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/keyboard.dts
+++ b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/keyboard.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx.dts b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx.dts
index 8ff2efd460..86a46e3e7a 100644
--- a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx.dts
+++ b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx.dts
@@ -1,8 +1,10 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+ #include <dt-bindings/usb_pd_tcpm.h>
+
 / {
 	chosen {
 		cros,rtc = &mtc;
@@ -20,33 +22,21 @@
 	named-i2c-ports {
 		compatible = "named-i2c-ports";
 
-		battery: battery {
-			i2c-port = <&i2c7_0>;
-			enum-name = "I2C_PORT_BATTERY";
-		};
-		charger {
-			i2c-port = <&i2c7_0>;
-			enum-name = "I2C_PORT_CHARGER";
-		};
-		eeprom {
+		i2c_charger: charger {
 			i2c-port = <&i2c7_0>;
-			enum-name = "I2C_PORT_EEPROM";
-		};
-		keyboard {
-			i2c-port = <&i2c7_0>;
-			enum-name = "I2C_PORT_KB_DISCRETE";
-		};
-		port80 {
-			i2c-port = <&i2c7_0>;
-			enum-name = "I2C_PORT_PORT80";
+			enum-names = "I2C_PORT_CHARGER",
+				"I2C_PORT_BATTERY",
+				"I2C_PORT_EEPROM",
+				"I2C_PORT_KB_DISCRETE",
+				"I2C_PORT_PORT80";
 		};
 		typec_aic1: typec-aic1{
 			i2c-port = <&i2c0_0>;
-			enum-name = "I2C_PORT_TYPEC_AIC_1";
+			enum-names = "I2C_PORT_TYPEC_AIC_1";
 		};
 		typec_aic2: typec-aic2{
-			i2c-port = <&i2c2_0>;
-			enum-name = "I2C_PORT_TYPEC_AIC_2";
+			i2c-port = <&i2c1_0>;
+			enum-names = "I2C_PORT_TYPEC_AIC_2";
 		};
 	};
 
@@ -54,22 +44,18 @@
 		compatible = "named-adc-channels";
 
 		adc_ambient: ambient {
-			label = "ADC_TEMP_SNS_AMBIENT";
 			enum-name = "ADC_TEMP_SENSOR_1";
 			io-channels = <&adc0 3>;
 		};
 		adc_ddr: ddr {
-			label = "ADC_TEMP_SNS_DDR";
 			enum-name = "ADC_TEMP_SENSOR_2";
 			io-channels = <&adc0 4>;
 		};
 		adc_skin: skin {
-			label = "ADC_TEMP_SNS_SKIN";
 			enum-name = "ADC_TEMP_SENSOR_3";
 			io-channels = <&adc0 2>;
 		};
 		adc_vr: vr {
-			label = "ADC_TEMP_SNS_VR";
 			enum-name = "ADC_TEMP_SENSOR_4";
 			io-channels = <&adc0 1>;
 		};
@@ -78,6 +64,7 @@
 
 /* charger */
 &i2c7_0 {
+	label = "I2C_CHARGER";
 	status = "okay";
 	clock-frequency = <I2C_BITRATE_STANDARD>;
 	pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>;
@@ -116,7 +103,6 @@
 	kb_discrete: ite-it8801@39 {
 		compatible = "ite,it8801";
 		reg = <0x39>;
-		label = "KEYBOARD_DISCRETE";
 	};
 
 	seven_seg_display: max695x-seven-seg-display@38 {
@@ -124,6 +110,21 @@
 		reg = <0x38>;
 		label = "MAX695X_SEVEN_SEG_DISPLAY";
 	};
+
+	charger: isl9241@9 {
+		compatible = "intersil,isl9241";
+		status = "okay";
+		reg = <0x9>;
+	};
+
+	cbi_eeprom: eeprom@50 {
+		compatible = "atmel,at24";
+		reg = <0x50>;
+		size = <2048>;
+		pagesize = <16>;
+		address-width = <8>;
+		timeout = <5>;
+	};
 };
 
 /* host interface */
@@ -139,10 +140,86 @@
 
 /* typec_aic1 */
 &i2c0_0 {
+	label = "I2C_USB_C0_C1_TCPC";
 	status = "okay";
 	clock-frequency = <I2C_BITRATE_FAST>;
 	pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>;
 	pinctrl-names = "default";
+
+	tcpc_port0: nct38xx@73 {
+		compatible = "nuvoton,nct38xx";
+		reg = <0x73>;
+		gpio-dev = <&nct38xx_c0>;
+		tcpc-flags = <(
+			TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_NO_DEBUG_ACC_CONTROL)>;
+	};
+
+	nct38xx_c0: nct38xx_c0@73 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nuvoton,nct38xx-gpio";
+		reg = <0x73>;
+		label = "NCT38XX_C0";
+
+		ioex_c0:gpio@0 {
+			compatible = "nuvoton,nct38xx-gpio-port";
+			reg = <0x0>;
+			label = "NCT38XX_C0_GPIO0";
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <8>;
+			pin_mask = <0xdc>;
+			pinmux_mask = <0xff>;
+		};
+	};
+
+	tcpc_port1: nct38xx@77 {
+		compatible = "nuvoton,nct38xx";
+		reg = <0x77>;
+		gpio-dev = <&nct38xx_c1>;
+		tcpc-flags = <(TCPC_FLAGS_TCPCI_REV2_0)>;
+	};
+
+	nct38xx_c1: nct38xx_c1@77 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nuvoton,nct38xx-gpio";
+		reg = <0x77>;
+		label = "NCT38XX_C1";
+
+		ioex_c1:gpio@0 {
+			compatible = "nuvoton,nct38xx-gpio-port";
+			reg = <0x0>;
+			label = "NCT38XX_C1_GPIO0";
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <8>;
+			pin_mask = <0xdc>;
+			pinmux_mask = <0xff>;
+		};
+	};
+
+	nct38xx_alert_0 {
+		compatible = "nuvoton,nct38xx-gpio-alert";
+		irq-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
+		nct38xx-dev = <&nct38xx_c0 &nct38xx_c1>;
+		label = "NCT38XX_ALERT_1";
+	};
+
+	usb_c0_hb_retimer: jhl8040r-c0@56 {
+		compatible = "intel,jhl8040r";
+		reg = <0x56>;
+		reset-pin = <&usb_c0_hb_retimer_rst>;
+		ls-en-pin = <&usb_c0_hb_retimer_ls_en>;
+	};
+
+	usb_c1_hb_retimer: jhl8040r-c1@57 {
+		compatible = "intel,jhl8040r";
+		reg = <0x57>;
+		reset-pin = <&usb_c1_hb_retimer_rst>;
+		ls-en-pin = <&usb_c1_hb_retimer_ls_en>;
+	};
 };
 
 &i2c_ctrl0 {
@@ -150,14 +227,39 @@
 };
 
 /* typec_aic2 */
-&i2c2_0 {
+&i2c1_0 {
+	label = "I2C_USB_C2_C3_TCPC";
 	status = "okay";
 	clock-frequency = <I2C_BITRATE_FAST>;
-	pinctrl-0 = <&i2c2_0_sda_scl_gp91_92>;
+	pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>;
 	pinctrl-names = "default";
+
+	tcpc_port2: ccgxxf@b {
+		compatible = "cypress,ccgxxf";
+		reg = <0xb>;
+	};
+
+	tcpc_port3: ccgxxf@1b {
+		compatible = "cypress,ccgxxf";
+		reg = <0x1b>;
+	};
+
+	usb_c2_hb_retimer: jhl8040r-c2@58 {
+		compatible = "intel,jhl8040r";
+		reg = <0x58>;
+		reset-pin = <&usb_c2_hb_retimer_rst>;
+		ls-en-pin = <&usb_c2_hb_retimer_ls_en>;
+	};
+
+	usb_c3_hb_retimer: jhl8040r-c3@59 {
+		compatible = "intel,jhl8040r";
+		reg = <0x59>;
+		reset-pin = <&usb_c3_hb_retimer_rst>;
+		ls-en-pin = <&usb_c3_hb_retimer_ls_en>;
+	};
 };
 
-&i2c_ctrl2 {
+&i2c_ctrl1 {
 	status = "okay";
 };
 
diff --git a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx_power_signals.dts b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx_power_signals.dts
index 57b41bd9d2..42745d328b 100644
--- a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx_power_signals.dts
+++ b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx_power_signals.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -98,15 +98,27 @@
  * Because the power signals directly reference the GPIOs,
  * the correspinding named-gpios need to have no-auto-init set.
  */
-&sys_pwrok_ec {
+&en_pp3300_a {
 	no-auto-init;
 };
 &rsmrst_pwrgd {
 	no-auto-init;
 };
-&all_sys_pwrgd {
+&ec_pch_rsmrst_l {
 	no-auto-init;
 };
 &pch_slp_s0_n {
 	no-auto-init;
 };
+&ec_pch_pwrok_od {
+	no-auto-init;
+};
+&sys_pwrok_ec {
+	no-auto-init;
+};
+&sys_rst_odl {
+	no-auto-init;
+};
+&all_sys_pwrgd {
+	no-auto-init;
+};
diff --git a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/prj.conf b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/prj.conf
index 9a90e99a38..45b101a7ac 100644
--- a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/prj.conf
+++ b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/prj.conf
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/projects/intelrvp/mtlrvp/prj.conf b/zephyr/projects/intelrvp/mtlrvp/prj.conf
index 607bf3a9d1..5781a274c5 100644
--- a/zephyr/projects/intelrvp/mtlrvp/prj.conf
+++ b/zephyr/projects/intelrvp/mtlrvp/prj.conf
@@ -1,30 +1,40 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 # Power Sequencing
 CONFIG_AP_X86_INTEL_MTL=y
+CONFIG_X86_NON_DSX_PWRSEQ_MTL=y
 CONFIG_PLATFORM_EC_POWERSEQ_SLP_S3_L_OVERRIDE=n
 CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n
-CONFIG_PLATFORM_EC_POWERSEQ_METEORLAKE=y
 
 # Battery
 CONFIG_PLATFORM_EC_BATTERY_TYPE_NO_AUTO_DETECT=y
+CONFIG_PLATFORM_EC_BATTERY_V2=y
 
 # CBI
 CONFIG_EEPROM=y
 CONFIG_EEPROM_AT24=y
 CONFIG_EEPROM_SHELL=n
 CONFIG_PLATFORM_EC_CBI_EEPROM=y
+CONFIG_PLATFORM_EC_BYPASS_CBI_EEPROM_WP_CHECK=y
+CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y
 
-# USB-C and charging
-# Below config are disabled to successfully compile battery conf
-# This will be enabled in upcoming CL
-CONFIG_PLATFORM_EC_USBC=n
-CONFIG_PLATFORM_EC_CHARGER=n
+# Disable BC1.2
+CONFIG_PLATFORM_EC_USB_CHARGER=n
+
+# Charger
+CONFIG_PLATFORM_EC_CHARGER=y
+CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=5
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=10
+CONFIG_PLATFORM_EC_CHARGE_RAMP_HW=n
+CONFIG_PLATFORM_EC_CHARGER_ISL9241=y
+CONFIG_PLATFORM_EC_DEDICATED_CHARGE_PORT=y
 
 # IOEX
 CONFIG_PLATFORM_EC_IOEX_CROS_DRV=y
+CONFIG_PLATFORM_EC_IOEX_CCGXXF=y
 CONFIG_GPIO_PCA95XX=y
 CONFIG_GPIO_NCT38XX=y
 CONFIG_PLATFORM_EC_IOEX_IT8801=y
@@ -39,8 +49,31 @@ CONFIG_PLATFORM_EC_THERMISTOR=y
 CONFIG_PLATFORM_EC_TEMP_SENSOR_POWER=y
 
 # USB CONFIG
+CONFIG_PLATFORM_EC_USB_DRP_ACC_TRYSRC=y
+CONFIG_PLATFORM_EC_USB_MUX_VIRTUAL=y
+CONFIG_PLATFORM_EC_USB_MUX_TASK=y
+CONFIG_PLATFORM_EC_USBC_PPC_SN5S330=y
+CONFIG_PLATFORM_EC_USBC_PPC=y
+CONFIG_PLATFORM_EC_USB_PD_PPC=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_PPC=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y
+CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y
+CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_TCPC=y
+CONFIG_PLATFORM_EC_USB_PD_TCPC_LOW_POWER=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_TCPCI=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_CCGXXF=y
 CONFIG_PLATFORM_EC_USB_PD_TCPM_NCT38XX=y
 CONFIG_PLATFORM_EC_USB_PD_TCPM_MUX=y
+CONFIG_PLATFORM_EC_USB_PD_TRY_SRC=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_SBU=y
+CONFIG_PLATFORM_EC_USB_PD_DUAL_ROLE_AUTO_TOGGLE=y
+CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_HB=y
+CONFIG_PLATFORM_EC_USBC_VCONN=y
+CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=y
+CONFIG_PLATFORM_EC_USB_PD_USB4=y
+CONFIG_PLATFORM_EC_USB_PD_INT_SHARED=y
+CONFIG_PLATFORM_EC_USB_PD_PORT_0_SHARED=y
+CONFIG_PLATFORM_EC_USB_PD_PORT_1_SHARED=y
 
 # 7-Segment Display
 CONFIG_PLATFORM_EC_MAX695X_SEVEN_SEGMENT_DISPLAY=y
diff --git a/zephyr/projects/intelrvp/mtlrvp/src/board_power.c b/zephyr/projects/intelrvp/mtlrvp/src/board_power.c
index 6e5253ac55..301402bf0f 100644
--- a/zephyr/projects/intelrvp/mtlrvp/src/board_power.c
+++ b/zephyr/projects/intelrvp/mtlrvp/src/board_power.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -47,8 +47,9 @@ void board_ap_power_action_g3_s5(void)
 	/* Turn on the PP3300_PRIM rail. */
 	power_signal_set(PWR_EN_PP3300_A, 1);
 
-	if (!power_wait_signals_timeout(IN_PGOOD_ALL_CORE,
-		AP_PWRSEQ_DT_VALUE(wait_signal_timeout))) {
+	if (!power_wait_signals_timeout(
+		    IN_PGOOD_ALL_CORE,
+		    AP_PWRSEQ_DT_VALUE(wait_signal_timeout))) {
 		ap_power_ev_send_callbacks(AP_POWER_PRE_INIT);
 	}
 }
diff --git a/zephyr/projects/intelrvp/mtlrvp/src/mtlrvp.c b/zephyr/projects/intelrvp/mtlrvp/src/mtlrvp.c
index 0839f453b5..9d96a08712 100644
--- a/zephyr/projects/intelrvp/mtlrvp/src/mtlrvp.c
+++ b/zephyr/projects/intelrvp/mtlrvp/src/mtlrvp.c
@@ -1,19 +1,172 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include "battery.h"
+#include "battery_fuel_gauge.h"
+#include "charger.h"
 #include "common.h"
 #include "console.h"
+#include "driver/retimer/bb_retimer_public.h"
+#include "driver/tcpm/ccgxxf.h"
+#include "driver/tcpm/nct38xx.h"
+#include "driver/tcpm/tcpci.h"
+#include "extpower.h"
 #include "gpio.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
 #include "i2c.h"
 #include "intelrvp.h"
 #include "intel_rvp_board_id.h"
+#include "ioexpander.h"
+#include "isl9241.h"
 #include "keyboard_raw.h"
 #include "power/meteorlake.h"
+#include "sn5s330.h"
+#include "system.h"
+#include "task.h"
+#include "tusb1064.h"
+#include "usb_mux.h"
+#include "usbc_ppc.h"
+#include "util.h"
 
-#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ##args)
+
+/*******************************************************************/
+/* USB-C Configuration Start */
+
+/* PPC */
+#define I2C_ADDR_SN5S330_P0 0x40
+#define I2C_ADDR_SN5S330_P1 0x41
+
+/* IOEX ports */
+enum ioex_port {
+	IOEX_KBD = 0,
+#if defined(HAS_TASK_PD_C2)
+	IOEX_C2_CCGXXF,
+#endif
+	IOEX_COUNT
+};
+
+/* USB-C ports */
+enum usbc_port {
+	USBC_PORT_C0 = 0,
+	USBC_PORT_C1,
+#if defined(HAS_TASK_PD_C2)
+	USBC_PORT_C2,
+	USBC_PORT_C3,
+#endif
+	USBC_PORT_COUNT
+};
+BUILD_ASSERT(USBC_PORT_COUNT == CONFIG_USB_PD_PORT_MAX_COUNT);
+
+/* USB-C PPC configuration */
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_TYPEC_AIC_1,
+		.i2c_addr_flags = I2C_ADDR_SN5S330_P0,
+		.drv = &sn5s330_drv,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_TYPEC_AIC_1,
+		.i2c_addr_flags = I2C_ADDR_SN5S330_P1,
+		.drv = &sn5s330_drv,
+	},
+};
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/* TCPC AIC GPIO Configuration */
+const struct tcpc_aic_gpio_config_t tcpc_aic_gpios[] = {
+	[USBC_PORT_C0] = {
+		.tcpc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_alrt_p0)),
+		.ppc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_ppc_alrt_p0)),
+		.ppc_intr_handler = sn5s330_interrupt,
+	},
+	[USBC_PORT_C1] = {
+		.tcpc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_alrt_p0)),
+		.ppc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_ppc_alrt_p1)),
+		.ppc_intr_handler = sn5s330_interrupt,
+	},
+#if defined(HAS_TASK_PD_C2)
+	[USBC_PORT_C2] = {
+		.tcpc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_alrt_p2)),
+		/* No PPC alert for CCGXXF */
+	},
+	[USBC_PORT_C3] = {
+		.tcpc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_alrt_p3)),
+		/* No PPC alert for CCGXXF */
+	},
+#endif
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_aic_gpios) == CONFIG_USB_PD_PORT_MAX_COUNT);
+
+static void board_connect_c0_sbu_deferred(void)
+{
+	enum pd_power_role prole;
+
+	if (gpio_get_level(GPIO_CCD_MODE_ODL)) {
+		CPRINTS("Default AUX line connected");
+		/* Default set the SBU lines to AUX mode */
+		ioex_set_level(IOEX_USB_C0_MUX_SBU_SEL_1, 0);
+		ioex_set_level(IOEX_USB_C0_MUX_SBU_SEL_0, 1);
+	} else {
+		prole = pd_get_power_role(USBC_PORT_C0);
+		CPRINTS("%s debug device is attached",
+			prole == PD_ROLE_SINK ? "Servo V4C/SuzyQ" : "Intel");
+
+		if (prole == PD_ROLE_SINK) {
+			/* Set the SBU lines to Google CCD mode */
+			ioex_set_level(IOEX_USB_C0_MUX_SBU_SEL_1, 1);
+			ioex_set_level(IOEX_USB_C0_MUX_SBU_SEL_0, 1);
+		} else {
+			/* Set the SBU lines to Intel CCD mode */
+			ioex_set_level(IOEX_USB_C0_MUX_SBU_SEL_1, 0);
+			ioex_set_level(IOEX_USB_C0_MUX_SBU_SEL_0, 0);
+		}
+	}
+}
+DECLARE_DEFERRED(board_connect_c0_sbu_deferred);
+
+void board_overcurrent_event(int port, int is_overcurrented)
+{
+	/*
+	 * TODO: Meteorlake PCH does not use Physical GPIO for over current
+	 * error, hence Send 'Over Current Virtual Wire' eSPI signal.
+	 */
+}
+
+void board_reset_pd_mcu(void)
+{
+	/* Reset NCT38XX TCPC */
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(usb_c0_c1_tcpc_rst_odl), 0);
+	msleep(NCT38XX_RESET_HOLD_DELAY_MS);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(usb_c0_c1_tcpc_rst_odl), 1);
+	nct38xx_reset_notify(0);
+	nct38xx_reset_notify(1);
+
+	if (NCT3807_RESET_POST_DELAY_MS != 0) {
+		msleep(NCT3807_RESET_POST_DELAY_MS);
+	}
+
+	/* NCT38XX chip uses gpio ioex */
+	gpio_reset_port(DEVICE_DT_GET(DT_NODELABEL(ioex_c0)));
+	gpio_reset_port(DEVICE_DT_GET(DT_NODELABEL(ioex_c1)));
+
+#if defined(HAS_TASK_PD_C2)
+	/* Reset the ccgxxf ports only resetting 1 is required */
+	ccgxxf_reset(USBC_PORT_C2);
+
+	/* CCGXXF has ioex on port 2 */
+	ioex_init(IOEX_C2_CCGXXF);
+#endif
+}
+
+void board_connect_c0_sbu(enum gpio_signal signal)
+{
+	hook_call_deferred(&board_connect_c0_sbu_deferred_data, 0);
+}
 
 /******************************************************************************/
 /* KSO mapping for discrete keyboard */
@@ -65,8 +218,7 @@ __override int board_get_version(void)
 	 * This loop retries to ensure rail is settled and read is successful
 	 */
 	for (i = 0; i < RVP_VERSION_READ_RETRY_CNT; i++) {
-
-		rv  = gpio_pin_get_dt(&bom_id_config[0]);
+		rv = gpio_pin_get_dt(&bom_id_config[0]);
 
 		if (rv >= 0)
 			break;
@@ -82,20 +234,20 @@ __override int board_get_version(void)
 	 * BOM ID [2]   : IOEX[0]
 	 * BOM ID [1:0] : IOEX[15:14]
 	 */
-	bom_id  = gpio_pin_get_dt(&bom_id_config[0]) << 2;
+	bom_id = gpio_pin_get_dt(&bom_id_config[0]) << 2;
 	bom_id |= gpio_pin_get_dt(&bom_id_config[1]) << 1;
 	bom_id |= gpio_pin_get_dt(&bom_id_config[2]);
 	/*
 	 * FAB ID [1:0] : IOEX[2:1] + 1
 	 */
-	fab_id  = gpio_pin_get_dt(&fab_id_config[0]) << 1;
+	fab_id = gpio_pin_get_dt(&fab_id_config[0]) << 1;
 	fab_id |= gpio_pin_get_dt(&fab_id_config[1]);
 	fab_id += 1;
 
 	/*
 	 * BOARD ID[5:0] : IOEX[13:8]
 	 */
-	board_id  = gpio_pin_get_dt(&board_id_config[0]) << 5;
+	board_id = gpio_pin_get_dt(&board_id_config[0]) << 5;
 	board_id |= gpio_pin_get_dt(&board_id_config[1]) << 4;
 	board_id |= gpio_pin_get_dt(&board_id_config[2]) << 3;
 	board_id |= gpio_pin_get_dt(&board_id_config[3]) << 2;
@@ -107,3 +259,73 @@ __override int board_get_version(void)
 	mtlrvp_board_id = board_id | (fab_id << 8);
 	return mtlrvp_board_id;
 }
+
+static void board_int_init(void)
+{
+	/* Enable PPC interrupts. */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_ppc));
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_ppc));
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_c1_tcpc));
+#if defined(HAS_TASK_PD_C2)
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c2_tcpc));
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c3_tcpc));
+#endif
+
+	/* Enable CCD Mode interrupt */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_ccd_mode));
+}
+
+static int board_pre_task_peripheral_init(const struct device *unused)
+{
+	ARG_UNUSED(unused);
+
+	/* Only reset tcpc/pd if not sysjump */
+	if (!system_jumped_late()) {
+		/* Initialize tcpc and all ioex */
+		board_reset_pd_mcu();
+	}
+
+	/* Initialize all interrupts */
+	board_int_init();
+
+	/* Make sure SBU are routed to CCD or AUX based on CCD status at init */
+	board_connect_c0_sbu_deferred();
+
+	return 0;
+}
+SYS_INIT(board_pre_task_peripheral_init, APPLICATION,
+	 CONFIG_APPLICATION_INIT_PRIORITY);
+
+/*
+ * Since MTLRVP has both PPC and TCPC ports override to check if the port
+ * is a PPC or non PPC port
+ */
+__override bool pd_check_vbus_level(int port, enum vbus_level level)
+{
+	if (!board_port_has_ppc(port)) {
+		return tcpm_check_vbus_level(port, level);
+	} else if (level == VBUS_PRESENT) {
+		return pd_snk_is_vbus_provided(port);
+	} else {
+		return !pd_snk_is_vbus_provided(port);
+	}
+}
+
+__override bool board_port_has_ppc(int port)
+{
+	bool ppc_port;
+
+	switch (port) {
+	case USBC_PORT_C0:
+	case USBC_PORT_C1:
+		ppc_port = true;
+		break;
+	default:
+		ppc_port = false;
+		break;
+	}
+
+	return ppc_port;
+}
diff --git a/zephyr/projects/intelrvp/mtlrvp/usbc.dts b/zephyr/projects/intelrvp/mtlrvp/usbc.dts
new file mode 100644
index 0000000000..e4f3bdc465
--- /dev/null
+++ b/zephyr/projects/intelrvp/mtlrvp/usbc.dts
@@ -0,0 +1,76 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		usbc_port0: port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+			tcpc = <&tcpc_port0>;
+			chg = <&charger>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_c0_hb_retimer
+					     &virtual_mux_c0>;
+			};
+		};
+		port0-muxes {
+			virtual_mux_c0: virtual-mux-c0 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+
+		usbc_port1: port1@1 {
+			compatible = "named-usbc-port";
+			reg = <1>;
+			tcpc = <&tcpc_port1>;
+			usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_c1_hb_retimer
+					     &virtual_mux_c1>;
+			};
+		};
+		port1-muxes {
+			virtual_mux_c1: virtual-mux-c1 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+
+		usbc_port2: port2@2 {
+			compatible = "named-usbc-port";
+			reg = <2>;
+			tcpc = <&tcpc_port2>;
+			usb-mux-chain-2 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_c2_hb_retimer
+					     &virtual_mux_c2>;
+			};
+		};
+		port2-muxes {
+			virtual_mux_c2: virtual-mux-c2 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+
+		usbc_port3: port3@3 {
+			compatible = "named-usbc-port";
+			reg = <3>;
+			tcpc = <&tcpc_port3>;
+			usb-mux-chain-3 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_c3_hb_retimer
+					     &virtual_mux_c3>;
+			};
+		};
+		port3-muxes {
+			virtual_mux_c3: virtual-mux-c3 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+	};
+};
diff --git a/zephyr/projects/intelrvp/prj.conf b/zephyr/projects/intelrvp/prj.conf
index 51b9245200..a7dcdc77dd 100644
--- a/zephyr/projects/intelrvp/prj.conf
+++ b/zephyr/projects/intelrvp/prj.conf
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -22,6 +22,9 @@ CONFIG_PLATFORM_EC_BATTERY_TYPE_NO_AUTO_DETECT=y
 CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT=15000
 CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON=15001
 
+#Power Sequencing
+CONFIG_PLATFORM_EC_BOARD_RESET_AFTER_POWER_ON=y
+
 # Host command
 CONFIG_PLATFORM_EC_HOSTCMD_AP_RESET=y
 
@@ -34,9 +37,9 @@ CONFIG_I2C=y
 
 # eSPI
 CONFIG_ESPI=y
-CONFIG_PLATFORM_EC_ESPI_VW_SLP_S3=y
-CONFIG_PLATFORM_EC_ESPI_VW_SLP_S4=y
-CONFIG_PLATFORM_EC_ESPI_VW_SLP_S5=y
+CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S3=y
+CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S4=y
+CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S5=y
 
 # Keyboard
 CONFIG_PLATFORM_EC_KEYBOARD=y
@@ -50,6 +53,17 @@ CONFIG_PLATFORM_EC_CMD_BUTTON=n
 CONFIG_SENSOR=y
 CONFIG_SENSOR_SHELL=n
 
+# Shell Commands
+CONFIG_SHELL_HELP=y
+CONFIG_SHELL_HISTORY=y
+CONFIG_SHELL_TAB=y
+CONFIG_SHELL_TAB_AUTOCOMPLETION=y
+CONFIG_KERNEL_SHELL=y
+
+# Logging
+CONFIG_LOG=y
+CONFIG_LOG_MODE_MINIMAL=y
+
 # TODO
 # Below conf are disabled to compile successfully
 # These will be enabled in upcoming CLs
diff --git a/zephyr/projects/intelrvp/src/chg_usb_pd.c b/zephyr/projects/intelrvp/src/chg_usb_pd.c
new file mode 100644
index 0000000000..63a1853b4d
--- /dev/null
+++ b/zephyr/projects/intelrvp/src/chg_usb_pd.c
@@ -0,0 +1,129 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Common USB PD charge configuration */
+
+#include "charge_manager.h"
+#include "charge_state_v2.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "intelrvp.h"
+#include "tcpm/tcpci.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+bool is_typec_port(int port)
+{
+#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
+	return !(port == DEDICATED_CHARGE_PORT || port == CHARGE_PORT_NONE);
+#else
+	return !(port == CHARGE_PORT_NONE);
+#endif /* CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 */
+}
+
+static inline int board_dc_jack_present(void)
+{
+#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
+	return gpio_get_level(GPIO_DC_JACK_PRESENT);
+#else
+	return 0;
+#endif /* CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 */
+}
+
+static void board_dc_jack_handle(void)
+{
+#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
+	struct charge_port_info charge_dc_jack;
+
+	/* System is booted from DC Jack */
+	if (board_dc_jack_present()) {
+		charge_dc_jack.current =
+			(PD_MAX_POWER_MW * 1000) / DC_JACK_MAX_VOLTAGE_MV;
+		charge_dc_jack.voltage = DC_JACK_MAX_VOLTAGE_MV;
+	} else {
+		charge_dc_jack.current = 0;
+		charge_dc_jack.voltage = USB_CHARGER_VOLTAGE_MV;
+	}
+
+	charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED,
+				     DEDICATED_CHARGE_PORT, &charge_dc_jack);
+#endif /* CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 */
+}
+
+void board_dc_jack_interrupt(enum gpio_signal signal)
+{
+	board_dc_jack_handle();
+}
+
+static void board_charge_init(void)
+{
+	int port, supplier;
+	struct charge_port_info charge_init = {
+		.current = 0,
+		.voltage = USB_CHARGER_VOLTAGE_MV,
+	};
+
+	/* Initialize all charge suppliers to seed the charge manager */
+	for (port = 0; port < CHARGE_PORT_COUNT; port++) {
+		for (supplier = 0; supplier < CHARGE_SUPPLIER_COUNT;
+		     supplier++) {
+			charge_manager_update_charge(supplier, port,
+						     &charge_init);
+		}
+	}
+
+	board_dc_jack_handle();
+}
+DECLARE_HOOK(HOOK_INIT, board_charge_init, HOOK_PRIO_DEFAULT);
+
+int board_set_active_charge_port(int port)
+{
+	int i;
+	/* charge port is a realy physical port */
+	int is_real_port = (port >= 0 && port < CHARGE_PORT_COUNT);
+	/* check if we are source vbus on that port */
+	int source = board_vbus_source_enabled(port);
+
+	if (is_real_port && source) {
+		CPRINTS("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
+	/*
+	 * Do not enable Type-C port if the DC Jack is present.
+	 * When the Type-C is active port, hardware circuit will
+	 * block DC jack from enabling +VADP_OUT.
+	 */
+	if (port != DEDICATED_CHARGE_PORT && board_dc_jack_present()) {
+		CPRINTS("DC Jack present, Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+#endif /* CONFIG_DEDICATED_CHARGE_PORT_COUNT */
+
+	/* Make sure non-charging ports are disabled */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		if (i != port) {
+			board_charging_enable(i, 0);
+		}
+	}
+
+	/* Enable charging port */
+	if (is_typec_port(port)) {
+		board_charging_enable(port, 1);
+	}
+
+	CPRINTS("New chg p%d", port);
+
+	return EC_SUCCESS;
+}
+
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
+{
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+}
diff --git a/zephyr/projects/intelrvp/src/chg_usb_pd_mecc_1_1.c b/zephyr/projects/intelrvp/src/chg_usb_pd_mecc_1_1.c
new file mode 100644
index 0000000000..45fbbc6f65
--- /dev/null
+++ b/zephyr/projects/intelrvp/src/chg_usb_pd_mecc_1_1.c
@@ -0,0 +1,92 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel-RVP family-specific configuration */
+
+#include "console.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "include/gpio.h"
+#include "intelrvp.h"
+#include "ioexpander.h"
+#include "system.h"
+#include "tcpm/tcpci.h"
+#include "usbc_ppc.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		/* No alerts for embedded TCPC */
+		if (tcpc_config[i].bus_type == EC_BUS_TYPE_EMBEDDED) {
+			continue;
+		}
+
+		if (signal == tcpc_aic_gpios[i].tcpc_alert) {
+			schedule_deferred_pd_interrupt(i);
+			break;
+		}
+	}
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+	int i;
+
+	/* Check which port has the ALERT line set */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		/* No alerts for embdeded TCPC */
+		if (tcpc_config[i].bus_type == EC_BUS_TYPE_EMBEDDED) {
+			continue;
+		}
+
+		if (!gpio_get_level(tcpc_aic_gpios[i].tcpc_alert)) {
+			status |= PD_STATUS_TCPC_ALERT_0 << i;
+		}
+	}
+
+	return status;
+}
+
+int ppc_get_alert_status(int port)
+{
+	return tcpc_aic_gpios[port].ppc_intr_handler &&
+	       !gpio_get_level(tcpc_aic_gpios[port].ppc_alert);
+}
+
+/* PPC support routines */
+void ppc_interrupt(enum gpio_signal signal)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		if (tcpc_aic_gpios[i].ppc_intr_handler &&
+		    signal == tcpc_aic_gpios[i].ppc_alert) {
+			tcpc_aic_gpios[i].ppc_intr_handler(i);
+			break;
+		}
+	}
+}
+
+void board_charging_enable(int port, int enable)
+{
+	int rv;
+
+	if (tcpc_aic_gpios[port].ppc_intr_handler) {
+		rv = ppc_vbus_sink_enable(port, enable);
+	} else {
+		rv = tcpc_config[port].drv->set_snk_ctrl(port, enable);
+	}
+
+	if (rv) {
+		CPRINTS("C%d: sink path %s failed", port,
+			enable ? "en" : "dis");
+	}
+}
diff --git a/zephyr/projects/intelrvp/src/intel_rvp_board_id.c b/zephyr/projects/intelrvp/src/intel_rvp_board_id.c
index d4172a468e..77d4e93afd 100644
--- a/zephyr/projects/intelrvp/src/intel_rvp_board_id.c
+++ b/zephyr/projects/intelrvp/src/intel_rvp_board_id.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,25 +9,22 @@
 #define DT_DRV_COMPAT intel_rvp_board_id
 
 BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) <= 1,
-	"Unsupported RVP Board ID instance");
+	     "Unsupported RVP Board ID instance");
 
 #define RVP_ID_GPIO_DT_SPEC_GET(idx, node_id, prop) \
 	GPIO_DT_SPEC_GET_BY_IDX(node_id, prop, idx),
 
-#define RVP_ID_CONFIG_LIST(node_id, prop)           \
-	LISTIFY(DT_PROP_LEN(node_id, prop),         \
-	RVP_ID_GPIO_DT_SPEC_GET, (), node_id, prop)
+#define RVP_ID_CONFIG_LIST(node_id, prop)                                \
+	LISTIFY(DT_PROP_LEN(node_id, prop), RVP_ID_GPIO_DT_SPEC_GET, (), \
+		node_id, prop)
 
 #if DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT)
-const struct gpio_dt_spec bom_id_config[] = {
-	RVP_ID_CONFIG_LIST(DT_DRV_INST(0), bom_gpios)
-};
+const struct gpio_dt_spec bom_id_config[] = { RVP_ID_CONFIG_LIST(DT_DRV_INST(0),
+								 bom_gpios) };
 
-const struct gpio_dt_spec fab_id_config[] = {
-	RVP_ID_CONFIG_LIST(DT_DRV_INST(0), fab_gpios)
-};
+const struct gpio_dt_spec fab_id_config[] = { RVP_ID_CONFIG_LIST(DT_DRV_INST(0),
+								 fab_gpios) };
 
-const struct gpio_dt_spec board_id_config[] = {
-	RVP_ID_CONFIG_LIST(DT_DRV_INST(0), board_gpios)
-};
+const struct gpio_dt_spec board_id_config[] = { RVP_ID_CONFIG_LIST(
+	DT_DRV_INST(0), board_gpios) };
 #endif /* #if DT_HAS_COMPAT_STATUS_OKAY */
diff --git a/zephyr/projects/intelrvp/src/intel_rvp_led.c b/zephyr/projects/intelrvp/src/intel_rvp_led.c
index b382dcc485..0e4d872963 100644
--- a/zephyr/projects/intelrvp/src/intel_rvp_led.c
+++ b/zephyr/projects/intelrvp/src/intel_rvp_led.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,8 +26,8 @@
 
 #define LED_PULSE_TICK (125 * MSEC)
 
-#define LED_FAST_PULSE_PERIOD  (250 / 125)		/* 250 ms */
-#define LED_SLOW_PULSE_PERIOD  ((2 * MSEC) / 125)	/* 2 sec  */
+#define LED_FAST_PULSE_PERIOD (250 / 125) /* 250 ms */
+#define LED_SLOW_PULSE_PERIOD ((2 * MSEC) / 125) /* 2 sec  */
 
 struct led_pulse_data {
 	bool led_is_pulsing;
@@ -56,13 +56,13 @@ static void pulse_led_deferred(void)
 		 * and in OFF state in second half of the pulse period.
 		 */
 		if (rvp_led[i].led_tick_count <
-					(rvp_led[i].led_pulse_period >> 1))
+		    (rvp_led[i].led_pulse_period >> 1))
 			set_pwm_led_color(i, EC_LED_COLOR_GREEN);
 		else
 			set_pwm_led_color(i, LED_OFF);
 
 		rvp_led[i].led_tick_count = (rvp_led[i].led_tick_count + 1) %
-						rvp_led[i].led_pulse_period;
+					    rvp_led[i].led_pulse_period;
 		call_deferred = true;
 	}
 
@@ -73,7 +73,7 @@ static void pulse_led_deferred(void)
 static void pulse_leds(enum pwm_led_id id, int period)
 {
 	rvp_led[id].led_pulse_period = period;
-	rvp_led[id].led_is_pulsing   = true;
+	rvp_led[id].led_is_pulsing = true;
 
 	pulse_led_deferred();
 }
@@ -96,7 +96,7 @@ static void update_charger_led(enum pwm_led_id id)
 		rvp_led[id].led_is_pulsing = false;
 		set_pwm_led_color(id, EC_LED_COLOR_GREEN);
 	} else if (chg_st == PWR_STATE_DISCHARGE ||
-		  chg_st == PWR_STATE_DISCHARGE_FULL) {
+		   chg_st == PWR_STATE_DISCHARGE_FULL) {
 		if (extpower_is_present()) {
 			/* Discharging:
 			 * Flash slower (2 second period, 100% duty cycle)
diff --git a/zephyr/projects/intelrvp/src/intelrvp.c b/zephyr/projects/intelrvp/src/intelrvp.c
index fd0514f438..7098f26cbf 100644
--- a/zephyr/projects/intelrvp/src/intelrvp.c
+++ b/zephyr/projects/intelrvp/src/intelrvp.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/intelrvp/src/usb_pd_policy_mecc_1_1.c b/zephyr/projects/intelrvp/src/usb_pd_policy_mecc_1_1.c
new file mode 100644
index 0000000000..a194b358f1
--- /dev/null
+++ b/zephyr/projects/intelrvp/src/usb_pd_policy_mecc_1_1.c
@@ -0,0 +1,106 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "console.h"
+#include "gpio.h"
+#include "intelrvp.h"
+#include "usb_mux.h"
+#include "usbc_ppc.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args)
+
+static inline void board_pd_set_vbus_discharge(int port, bool enable)
+{
+	if (tcpc_aic_gpios[port].ppc_intr_handler) {
+		ppc_discharge_vbus(port, enable);
+	} else {
+		tcpc_discharge_vbus(port, enable);
+	}
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	/* Disable charging. */
+	if (tcpc_aic_gpios[port].ppc_intr_handler) {
+		rv = ppc_vbus_sink_enable(port, 0);
+	} else {
+		rv = tcpc_config[port].drv->set_snk_ctrl(port, 0);
+	}
+
+	if (rv) {
+		return rv;
+	}
+
+	board_pd_set_vbus_discharge(port, false);
+
+	/* Provide Vbus. */
+	if (tcpc_aic_gpios[port].ppc_intr_handler) {
+		rv = ppc_vbus_source_enable(port, 1);
+	} else {
+		tcpc_config[port].drv->set_src_ctrl(port, 1);
+	}
+
+	if (rv) {
+		return rv;
+	}
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+void pd_power_supply_reset(int port)
+{
+	int prev_en;
+
+	prev_en = board_vbus_source_enabled(port);
+
+	/* Disable VBUS. */
+	if (tcpc_aic_gpios[port].ppc_intr_handler) {
+		ppc_vbus_source_enable(port, 0);
+	} else {
+		tcpc_config[port].drv->set_src_ctrl(port, 0);
+	}
+
+	/* Enable discharge if we were previously sourcing 5V */
+	if (prev_en) {
+		board_pd_set_vbus_discharge(port, true);
+	}
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_check_vconn_swap(int port)
+{
+	/* Only allow vconn swap if PP3300 rail is enabled */
+	return gpio_get_level(GPIO_EN_PP3300_A);
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	if (tcpc_aic_gpios[port].ppc_intr_handler) {
+		return ppc_is_vbus_present(port);
+	} else {
+		return tcpc_config[port].drv->check_vbus_level(port,
+							       VBUS_PRESENT);
+	}
+}
+
+int board_vbus_source_enabled(int port)
+{
+	if (is_typec_port(port)) {
+		if (tcpc_aic_gpios[port].ppc_intr_handler) {
+			return ppc_is_sourcing_vbus(port);
+		} else {
+			return tcpc_config[port].drv->get_src_ctrl(port);
+		}
+	}
+	return 0;
+}
diff --git a/zephyr/projects/intelrvp/zephyr_ap_pwrseq.conf b/zephyr/projects/intelrvp/zephyr_ap_pwrseq.conf
new file mode 100644
index 0000000000..1ef365a8fa
--- /dev/null
+++ b/zephyr/projects/intelrvp/zephyr_ap_pwrseq.conf
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Zephyr Inbuilt AP Power Sequencing Config
+CONFIG_AP_PWRSEQ=y
+CONFIG_X86_NON_DSX_PWRSEQ_CONSOLE=y
+CONFIG_X86_NON_DSX_PWRSEQ_HOST_CMD=y
+CONFIG_AP_PWRSEQ_S0IX=y
diff --git a/zephyr/projects/it8xxx2_evb/BUILD.py b/zephyr/projects/it8xxx2_evb/BUILD.py
index 2f4b87886b..ee89c75390 100644
--- a/zephyr/projects/it8xxx2_evb/BUILD.py
+++ b/zephyr/projects/it8xxx2_evb/BUILD.py
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -6,7 +6,7 @@
 
 register_raw_project(
     project_name="it8xxx2_evb",
-    zephyr_board="it8xxx2",
+    zephyr_board="it81302bx",
     dts_overlays=[
         "adc.dts",
         "fan.dts",
diff --git a/zephyr/projects/it8xxx2_evb/CMakeLists.txt b/zephyr/projects/it8xxx2_evb/CMakeLists.txt
index dc2eb449b0..170606a52d 100644
--- a/zephyr/projects/it8xxx2_evb/CMakeLists.txt
+++ b/zephyr/projects/it8xxx2_evb/CMakeLists.txt
@@ -1,10 +1,10 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 cmake_minimum_required(VERSION 3.13.1)
 
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
 project(it8xxx2_evb)
 
 # Include board specific header files
diff --git a/zephyr/projects/it8xxx2_evb/adc.dts b/zephyr/projects/it8xxx2_evb/adc.dts
index b72a38b110..509c9b9daf 100644
--- a/zephyr/projects/it8xxx2_evb/adc.dts
+++ b/zephyr/projects/it8xxx2_evb/adc.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,32 +8,26 @@
 		compatible = "named-adc-channels";
 
 		adc_vbussa: vbussa {
-			label = "ADC_VBUSSA";
 			enum-name = "ADC_VBUS";
 			io-channels = <&adc0 0>;
 		};
 		adc_vbussb: vbussb {
-			label = "ADC_VBUSSB";
 			enum-name = "ADC_PSYS";
 			io-channels = <&adc0 1>;
 		};
 		adc_evb_ch_13: evb_ch_13 {
-			label = "ADC_EVB_CH_13";
 			enum-name = "ADC_AMON_BMON";
 			io-channels = <&adc0 2>;
 		};
 		adc_evb_ch_14: evb_ch_14 {
-			label = "ADC_EVB_CH_14";
 			enum-name = "ADC_TEMP_SENSOR_FAN";
 			io-channels = <&adc0 3>;
 		};
 		adc_evb_ch_15: evb_ch_15 {
-			label = "ADC_EVB_CH_15";
 			enum-name = "ADC_TEMP_SENSOR_DDR_SOC";
 			io-channels = <&adc0 4>;
 		};
 		adc_evb_ch_16: evb_ch_16 {
-			label = "ADC_EVB_CH_16";
 			enum-name = "ADC_TEMP_SENSOR_CHARGER";
 			io-channels = <&adc0 5>;
 		};
diff --git a/zephyr/projects/it8xxx2_evb/fan.dts b/zephyr/projects/it8xxx2_evb/fan.dts
index faa659e6ad..2551507ec3 100644
--- a/zephyr/projects/it8xxx2_evb/fan.dts
+++ b/zephyr/projects/it8xxx2_evb/fan.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,7 +9,6 @@
 
 		fan_0 {
 			pwms = <&pwm7 PWM_CHANNEL_7 PWM_KHZ(30) PWM_POLARITY_NORMAL>;
-			pwm-frequency = <30000>;
 			tach = <&tach0>;
 			rpm_min = <1500>;
 			rpm_start = <1500>;
diff --git a/zephyr/projects/it8xxx2_evb/gpio.dts b/zephyr/projects/it8xxx2_evb/gpio.dts
index 51c6a45ca9..85bb45d7a0 100644
--- a/zephyr/projects/it8xxx2_evb/gpio.dts
+++ b/zephyr/projects/it8xxx2_evb/gpio.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -39,6 +39,10 @@
 		spi0_cs: spi0_cs {
 			gpios = <&gpiom 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
 		};
+		/* unimplemented GPIOs */
+		entering-rw {
+			enum-name = "GPIO_ENTERING_RW";
+		};
 	};
 
 	hibernate-wake-pins {
diff --git a/zephyr/projects/it8xxx2_evb/i2c.dts b/zephyr/projects/it8xxx2_evb/i2c.dts
index 753755f449..c08c543e44 100644
--- a/zephyr/projects/it8xxx2_evb/i2c.dts
+++ b/zephyr/projects/it8xxx2_evb/i2c.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,19 +9,19 @@
 
 		battery {
 			i2c-port = <&i2c2>;
-			enum-name = "I2C_PORT_BATTERY";
+			enum-names = "I2C_PORT_BATTERY";
 		};
 		evb-1 {
 			i2c-port = <&i2c0>;
-			enum-name = "I2C_PORT_EVB_1";
+			enum-names = "I2C_PORT_EVB_1";
 		};
 		evb-2 {
 			i2c-port = <&i2c1>;
-			enum-name = "I2C_PORT_EVB_2";
+			enum-names = "I2C_PORT_EVB_2";
 		};
 		opt-4 {
 			i2c-port = <&i2c4>;
-			enum-name = "I2C_PORT_OPT_4";
+			enum-names = "I2C_PORT_OPT_4";
 		};
 	};
 };
diff --git a/zephyr/projects/it8xxx2_evb/include/gpio_map.h b/zephyr/projects/it8xxx2_evb/include/gpio_map.h
deleted file mode 100644
index b9d9026892..0000000000
--- a/zephyr/projects/it8xxx2_evb/include/gpio_map.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __ZEPHYR_GPIO_MAP_H
-#define __ZEPHYR_GPIO_MAP_H
-
-#include <zephyr/devicetree.h>
-#include <gpio_signal.h>
-
-#define GPIO_ENTERING_RW	GPIO_UNIMPLEMENTED
-
-#endif /* __ZEPHYR_GPIO_MAP_H */
diff --git a/zephyr/projects/it8xxx2_evb/include/i2c_map.h b/zephyr/projects/it8xxx2_evb/include/i2c_map.h
index 49c492f6ba..e83a238d3a 100644
--- a/zephyr/projects/it8xxx2_evb/include/i2c_map.h
+++ b/zephyr/projects/it8xxx2_evb/include/i2c_map.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/it8xxx2_evb/interrupts.dts b/zephyr/projects/it8xxx2_evb/interrupts.dts
index d52a86ce43..07fc0ed339 100644
--- a/zephyr/projects/it8xxx2_evb/interrupts.dts
+++ b/zephyr/projects/it8xxx2_evb/interrupts.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/it8xxx2_evb/prj.conf b/zephyr/projects/it8xxx2_evb/prj.conf
index bb9fb95d8f..d6d422e490 100644
--- a/zephyr/projects/it8xxx2_evb/prj.conf
+++ b/zephyr/projects/it8xxx2_evb/prj.conf
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -19,6 +19,16 @@ CONFIG_LOG=y
 # Fan
 CONFIG_SENSOR=y
 
+# I2C
+CONFIG_I2C=y
+
+# PWM
+CONFIG_PWM=y
+CONFIG_PWM_SHELL=n
+
+# Power Button
+CONFIG_PLATFORM_EC_POWER_BUTTON=y
+
 # TODO(b:185202623): bring these features up
 CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
 CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=n
@@ -28,3 +38,7 @@ CONFIG_CROS_KB_RAW_ITE=n
 CONFIG_PLATFORM_EC_SWITCH=n
 CONFIG_PLATFORM_EC_VBOOT_EFS2=n
 CONFIG_PLATFORM_EC_VBOOT_HASH=n
+
+# USB-C
+CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=n
+CONFIG_PLATFORM_EC_USB_PD_USB4=n
diff --git a/zephyr/projects/it8xxx2_evb/pwm.dts b/zephyr/projects/it8xxx2_evb/pwm.dts
index bac40fc722..c566e5c029 100644
--- a/zephyr/projects/it8xxx2_evb/pwm.dts
+++ b/zephyr/projects/it8xxx2_evb/pwm.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/minimal/BUILD.py b/zephyr/projects/minimal/BUILD.py
new file mode 100644
index 0000000000..5e892aa2d7
--- /dev/null
+++ b/zephyr/projects/minimal/BUILD.py
@@ -0,0 +1,22 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Minimal example project."""
+
+register_host_project(
+    project_name="minimal-posix",
+    zephyr_board="native_posix",
+)
+
+register_npcx_project(
+    project_name="minimal-npcx9",
+    zephyr_board="npcx9m3f",
+    dts_overlays=[here / "npcx9.dts"],
+)
+
+register_binman_project(
+    project_name="minimal-it8xxx2",
+    zephyr_board="it81302bx",
+    dts_overlays=[here / "it8xxx2.dts"],
+)
diff --git a/zephyr/projects/minimal/CMakeLists.txt b/zephyr/projects/minimal/CMakeLists.txt
new file mode 100644
index 0000000000..de3bec9428
--- /dev/null
+++ b/zephyr/projects/minimal/CMakeLists.txt
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.20.5)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(ec)
+
+zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}/include")
diff --git a/zephyr/projects/minimal/README.md b/zephyr/projects/minimal/README.md
new file mode 100644
index 0000000000..72c092dfce
--- /dev/null
+++ b/zephyr/projects/minimal/README.md
@@ -0,0 +1,32 @@
+# Minimal Example Zephyr EC Project
+
+This directory is intended to be an extremely minimal example of a
+project.  Should you like, you can use it as a bring up a new program,
+or as reference as you require.
+
+If you're bringing up a new variant of a program, you don't need a
+whole project directory with a `BUILD.py` and all, and this example is
+likely not of use to you.  Check out the [project config
+documentation] for instructions on adding a new variant.
+
+[project config documentation]: ../../../docs/zephyr/project_config.md
+
+# Building
+
+To build the `native_posix` example, run:
+
+``` shellsession
+(chroot) $ zmake build minimal-posix
+```
+
+To build the NPCX9 example, run:
+
+``` shellsession
+(chroot) $ zmake build minimal-npcx9
+```
+
+For the IT8XXX2 example, run:
+
+``` shellsession
+(chroot) $ zmake build minimal-it8xxx2
+```
diff --git a/zephyr/projects/minimal/it8xxx2.dts b/zephyr/projects/minimal/it8xxx2.dts
new file mode 100644
index 0000000000..3d2028afb2
--- /dev/null
+++ b/zephyr/projects/minimal/it8xxx2.dts
@@ -0,0 +1,22 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	aliases {
+		gpio-wp = &ec_wp_l;
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		ec_wp_l: write-protect {
+			gpios = <&gpioa 0 GPIO_INPUT>;
+		};
+		/* unimplemented GPIOs */
+		entering-rw {
+			enum-name = "GPIO_ENTERING_RW";
+		};
+	};
+};
diff --git a/zephyr/projects/minimal/npcx9.dts b/zephyr/projects/minimal/npcx9.dts
new file mode 100644
index 0000000000..3a9f3b26e4
--- /dev/null
+++ b/zephyr/projects/minimal/npcx9.dts
@@ -0,0 +1,28 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	aliases {
+		gpio-wp = &ec_wp_l;
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		ec_wp_l: write-protect {
+			gpios = <&gpioa 0 GPIO_INPUT>;
+		};
+		/* unimplemented GPIOs */
+		entering-rw {
+			enum-name = "GPIO_ENTERING_RW";
+		};
+	};
+};
+
+&cros_kb_raw {
+	status = "okay";
+	pinctrl-0 = <>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/projects/minimal/prj.conf b/zephyr/projects/minimal/prj.conf
new file mode 100644
index 0000000000..db7cac0cef
--- /dev/null
+++ b/zephyr/projects/minimal/prj.conf
@@ -0,0 +1,18 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_PLATFORM_EC=y
+CONFIG_CROS_EC=y
+CONFIG_SHIMMED_TASKS=y
+CONFIG_SYSCON=y
+
+# Disable default features we don't want in a minimal example.
+CONFIG_ADC=n
+CONFIG_I2C=n
+CONFIG_PWM=n
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
+CONFIG_PLATFORM_EC_KEYBOARD=n
+CONFIG_PLATFORM_EC_POWER_BUTTON=n
+CONFIG_PLATFORM_EC_SWITCH=n
+CONFIG_PLATFORM_EC_VBOOT_EFS2=n
diff --git a/zephyr/projects/nissa/BUILD.py b/zephyr/projects/nissa/BUILD.py
index a620e7b9ae..e162bc2b96 100644
--- a/zephyr/projects/nissa/BUILD.py
+++ b/zephyr/projects/nissa/BUILD.py
@@ -1,28 +1,34 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 """Define zmake projects for nissa."""
 
-# Nivviks and Craask, Pujjo has NPCX993F, Nereid has ITE81302
+# Nivviks and Craask, Pujjo, Xivu has NPCX993F, Nereid and Joxer, Yaviks has ITE81302
 
 
 def register_nissa_project(
     project_name,
-    chip="it8xxx2",
+    chip="it81302bx",
     extra_dts_overlays=(),
-    extra_kconfig_files=(),
 ):
     """Register a variant of nissa."""
     register_func = register_binman_project
     if chip.startswith("npcx"):
         register_func = register_npcx_project
 
+    chip_kconfig = {"it81302bx": "it8xxx2", "npcx9m3f": "npcx"}[chip]
+
     return register_func(
         project_name=project_name,
         zephyr_board=chip,
-        dts_overlays=["cbi.dts", *extra_dts_overlays],
-        kconfig_files=[here / "prj.conf", *extra_kconfig_files],
+        dts_overlays=["cbi.dts"]
+        + [here / project_name / filename for filename in extra_dts_overlays],
+        kconfig_files=[
+            here / "prj.conf",
+            here / f"prj_{chip_kconfig}.conf",
+            here / project_name / "prj.conf",
+        ],
     )
 
 
@@ -30,55 +36,92 @@ nivviks = register_nissa_project(
     project_name="nivviks",
     chip="npcx9m3f",
     extra_dts_overlays=[
-        here / "nivviks_generated.dts",
-        here / "nivviks_cbi.dts",
-        here / "nivviks_overlay.dts",
-        here / "nivviks_motionsense.dts",
-        here / "nivviks_keyboard.dts",
-        here / "nivviks_power_signals.dts",
-        here / "nivviks_pwm_leds.dts",
+        "generated.dts",
+        "cbi.dts",
+        "overlay.dts",
+        "motionsense.dts",
+        "keyboard.dts",
+        "power_signals.dts",
+        "pwm_leds.dts",
     ],
-    extra_kconfig_files=[here / "prj_nivviks.conf"],
 )
 
 nereid = register_nissa_project(
     project_name="nereid",
-    chip="it8xxx2",
+    chip="it81302bx",
     extra_dts_overlays=[
-        here / "nereid_generated.dts",
-        here / "nereid_overlay.dts",
-        here / "nereid_motionsense.dts",
-        here / "nereid_keyboard.dts",
-        here / "nereid_power_signals.dts",
-        here / "nereid_pwm_leds.dts",
+        "generated.dts",
+        "overlay.dts",
+        "motionsense.dts",
+        "keyboard.dts",
+        "power_signals.dts",
+        "pwm_leds.dts",
     ],
-    extra_kconfig_files=[here / "prj_nereid.conf"],
 )
 
 craask = register_nissa_project(
     project_name="craask",
     chip="npcx9m3f",
     extra_dts_overlays=[
-        here / "craask_generated.dts",
-        here / "craask_overlay.dts",
-        here / "craask_motionsense.dts",
-        here / "craask_keyboard.dts",
-        here / "craask_power_signals.dts",
-        here / "craask_pwm_leds.dts",
+        "generated.dts",
+        "cbi.dts",
+        "overlay.dts",
+        "motionsense.dts",
+        "keyboard.dts",
+        "power_signals.dts",
+        "pwm_leds.dts",
     ],
-    extra_kconfig_files=[here / "prj_craask.conf"],
 )
 
 pujjo = register_nissa_project(
     project_name="pujjo",
     chip="npcx9m3f",
     extra_dts_overlays=[
-        here / "pujjo_generated.dts",
-        here / "pujjo_overlay.dts",
-        here / "pujjo_motionsense.dts",
-        here / "pujjo_keyboard.dts",
-        here / "pujjo_power_signals.dts",
-        here / "pujjo_pwm_leds.dts",
+        "generated.dts",
+        "cbi.dts",
+        "overlay.dts",
+        "motionsense.dts",
+        "keyboard.dts",
+        "power_signals.dts",
+    ],
+)
+
+xivu = register_nissa_project(
+    project_name="xivu",
+    chip="npcx9m3f",
+    extra_dts_overlays=[
+        "generated.dts",
+        "cbi.dts",
+        "overlay.dts",
+        "motionsense.dts",
+        "keyboard.dts",
+        "power_signals.dts",
+        "led_pins.dts",
+        "led_policy.dts",
+    ],
+)
+
+joxer = register_nissa_project(
+    project_name="joxer",
+    chip="it81302bx",
+    extra_dts_overlays=[
+        "generated.dts",
+        "cbi.dts",
+        "overlay.dts",
+        "motionsense.dts",
+        "keyboard.dts",
+        "power_signals.dts",
+        "pwm_leds.dts",
+    ],
+)
+
+yaviks = register_nissa_project(
+    project_name="yaviks",
+    chip="it81302bx",
+    extra_dts_overlays=[
+        "gpio.dts",
+        "overlay.dts",
+        "keyboard.dts",
+        "power_signals.dts",
     ],
-    extra_kconfig_files=[here / "prj_pujjo.conf"],
 )
diff --git a/zephyr/projects/nissa/CMakeLists.txt b/zephyr/projects/nissa/CMakeLists.txt
index afc96e924f..30d574096b 100644
--- a/zephyr/projects/nissa/CMakeLists.txt
+++ b/zephyr/projects/nissa/CMakeLists.txt
@@ -1,10 +1,10 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 cmake_minimum_required(VERSION 3.13.1)
 
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
 
 zephyr_include_directories(include)
 zephyr_library_sources("src/common.c")
@@ -14,38 +14,71 @@ zephyr_library_sources_ifdef(CONFIG_AP_PWRSEQ "src/board_power.c")
 if(DEFINED CONFIG_BOARD_NIVVIKS)
 	project(nivviks)
 	zephyr_library_sources(
-			"src/led.c"
-			"src/nivviks/form_factor.c"
-			"src/nivviks/keyboard.c"
+			"nivviks/src/led.c"
+			"nivviks/src/form_factor.c"
+			"nivviks/src/keyboard.c"
 	)
-	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FAN "src/nivviks/fan.c")
-	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/nivviks/usbc.c")
-	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "src/nivviks/charger.c")
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FAN "nivviks/src/fan.c")
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "nivviks/src/usbc.c")
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "nivviks/src/charger.c")
 endif()
 if(DEFINED CONFIG_BOARD_NEREID)
 	project(nereid)
 	zephyr_library_sources(
 			"src/led.c"
-			"src/nereid/keyboard.c"
+			"nereid/src/keyboard.c"
+			"nereid/src/hdmi.c"
 	)
-	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/nereid/usbc.c")
-	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "src/nereid/charger.c")
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "nereid/src/usbc.c")
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "nereid/src/charger.c")
 endif()
 if(DEFINED CONFIG_BOARD_CRAASK)
 	zephyr_library_sources(
-			"src/craask/led.c"
+			"craask/src/form_factor.c"
+			"craask/src/keyboard.c"
+			"craask/src/led.c"
 	)
 	project(craask)
-	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/craask/usbc.c")
-	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "src/craask/charger.c")
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "craask/src/usbc.c")
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "craask/src/charger.c")
 endif()
 if(DEFINED CONFIG_BOARD_PUJJO)
 	project(pujjo)
 	zephyr_library_sources(
-			"src/led.c"
-			"src/pujjo/keyboard.c"
+			"pujjo/src/led.c"
+			"pujjo/src/keyboard.c"
+			"pujjo/src/hdmi.c"
+			"pujjo/src/form_factor.c"
+	)
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FAN "pujjo/src/fan.c")
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "pujjo/src/usbc.c")
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "pujjo/src/charger.c")
+endif()
+if(DEFINED CONFIG_BOARD_XIVU)
+	project(xivu)
+	zephyr_library_sources(
+			"xivu/src/keyboard.c"
 	)
-	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FAN "src/pujjo/fan.c")
-	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/pujjo/usbc.c")
-	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "src/pujjo/charger.c")
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "xivu/src/usbc.c")
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "xivu/src/charger.c")
 endif()
+if(DEFINED CONFIG_BOARD_JOXER)
+	project(joxer)
+	zephyr_library_sources(
+			"joxer/src/led.c"
+			"joxer/src/keyboard.c"
+	)
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "joxer/src/usbc.c")
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "joxer/src/charger.c")
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FAN "joxer/src/fan.c")
+endif()
+if(DEFINED CONFIG_BOARD_YAVIKS)
+	project(yaviks)
+	zephyr_library_sources(
+			"yaviks/src/led.c"
+			"yaviks/src/keyboard.c"
+			"yaviks/src/hdmi.c"
+	)
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "yaviks/src/usbc.c")
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "yaviks/src/charger.c")
+endif()
\ No newline at end of file
diff --git a/zephyr/projects/nissa/Kconfig b/zephyr/projects/nissa/Kconfig
index 87d7bca977..9e9ffc2528 100644
--- a/zephyr/projects/nissa/Kconfig
+++ b/zephyr/projects/nissa/Kconfig
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -26,6 +26,25 @@ config BOARD_PUJJO
 	  Build Google Pujjo board. Pujjo has Intel ADL-N SoC
 	  with NPCX993FA0BX EC.
 
+config BOARD_XIVU
+        bool "Google Xivu Board"
+        help
+          Build Google Xivu board. Xivu has Intel ADL-N SoC
+          with NPCX993FA0BX EC.
+
+config BOARD_JOXER
+	bool "Google Joxer Board"
+	help
+	  Build Google Joxer reference board. Joxer has Intel ADL-N SoC
+	  with IT81302 EC.
+
+config BOARD_YAVIKS
+	bool "Google Yaviks Board"
+	help
+	  Build Google Yaviks board. Yaviks has Intel ADL-N SoC
+	  with IT81302 EC.
+
+
 module = NISSA
 module-str = Nissa board-specific code
 source "subsys/logging/Kconfig.template.log_config"
diff --git a/zephyr/projects/nissa/cbi.dts b/zephyr/projects/nissa/cbi.dts
index ec6d8ea608..d841be1624 100644
--- a/zephyr/projects/nissa/cbi.dts
+++ b/zephyr/projects/nissa/cbi.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/nissa/craask/cbi.dts b/zephyr/projects/nissa/craask/cbi.dts
new file mode 100644
index 0000000000..4c2e052f4d
--- /dev/null
+++ b/zephyr/projects/nissa/craask/cbi.dts
@@ -0,0 +1,107 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	/* Craask-specific fw_config fields. */
+	nissa-fw-config {
+		/*
+		 * FW_CONFIG field to describe Lid sensor orientation.
+		 */
+		lid-inversion {
+			enum-name = "FW_LID_INVERSION";
+			start = <8>;
+			size = <1>;
+
+			/*
+			 * 0: regular placement of the lid sensor
+			 * 1: rotate 180' of xy plane.
+			 */
+			regular {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_LID_REGULAR";
+				value = <0>;
+				default;
+			};
+			xy_rotate_180 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_LID_XY_ROT_180";
+				value = <1>;
+			};
+		};
+		/*
+		 * FW_CONFIG field to describe Clamshell/Convertible.
+		 */
+		form_factor {
+			enum-name = "FORM_FACTOR";
+			start = <9>;
+			size = <1>;
+
+			/*
+			 * 0: convertible, 1: clamshell
+			 */
+			convertible {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "CONVERTIBLE";
+				value = <0>;
+			};
+			clamshell {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "CLAMSHELL";
+				value = <1>;
+			};
+		};
+	};
+	/* Craask-specific ssfc fields. */
+	cbi-ssfc {
+		compatible = "named-cbi-ssfc";
+		/*
+		 * SSFC bit0-1 was defined for AUDIO CODEC.
+		 * 0: ALC5682I_VS
+		 * 1: NAU8825
+		 */
+		audio_codec {
+			enum-name = "AUDIO_CODEC";
+			size = <2>;
+		};
+		/*
+		 * SSFC field to identify LID motion sensor.
+		 */
+		lid-sensor {
+			enum-name = "LID_SENSOR";
+			size = <2>;
+
+			lid_sensor_0: lis2dw12 {
+				compatible = "named-cbi-ssfc-value";
+				status = "okay";
+				value = <0>;
+				default;
+			};
+			lid_sensor_1: bma422 {
+				compatible = "named-cbi-ssfc-value";
+				status = "okay";
+				value = <1>;
+			};
+		};
+		/*
+		 * SSFC field to identify BASE motion sensor.
+		 */
+		base-sensor {
+			enum-name = "BASE_SENSOR";
+			size = <2>;
+
+			base_sensor_0: lsm6dso {
+				compatible = "named-cbi-ssfc-value";
+				status = "okay";
+				value = <0>;
+				default;
+			};
+			base_sensor_1: bmi323 {
+				compatible = "named-cbi-ssfc-value";
+				status = "okay";
+				value = <1>;
+			};
+		};
+	};
+};
diff --git a/zephyr/projects/nissa/craask_generated.dts b/zephyr/projects/nissa/craask/generated.dts
index 1a4d5f044f..4303bbd4c5 100644
--- a/zephyr/projects/nissa/craask_generated.dts
+++ b/zephyr/projects/nissa/craask/generated.dts
@@ -1,8 +1,6 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
- *
- * This file is auto-generated - do not edit!
  */
 
 / {
@@ -11,25 +9,25 @@
 		compatible = "named-adc-channels";
 
 		adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc {
-			label = "EC_VSENSE_PP1050_PROC";
 			enum-name = "ADC_PP1050_PROC";
 			io-channels = <&adc0 4>;
 		};
 		adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 {
-			label = "EC_VSENSE_PP3300_S5";
 			enum-name = "ADC_PP3300_S5";
 			io-channels = <&adc0 6>;
 		};
 		adc_temp_sensor_1: temp_sensor_1 {
-			label = "TEMP_SENSOR_1";
 			enum-name = "ADC_TEMP_SENSOR_1";
 			io-channels = <&adc0 0>;
 		};
 		adc_temp_sensor_2: temp_sensor_2 {
-			label = "TEMP_SENSOR_2";
 			enum-name = "ADC_TEMP_SENSOR_2";
 			io-channels = <&adc0 1>;
 		};
+		adc_temp_sensor_3: temp_sensor_3 {
+			enum-name = "ADC_TEMP_SENSOR_3";
+			io-channels = <&adc0 10>;
+		};
 	};
 
 	named-gpios {
@@ -188,17 +186,17 @@
 			gpios = <&gpio0 1 GPIO_INPUT_PULL_UP>;
 		};
 		gpio_vccin_aux_vid0: vccin_aux_vid0 {
-			gpios = <&gpio9 2 GPIO_INPUT>;
+			gpios = <&gpio9 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
 		};
 		gpio_vccin_aux_vid1: vccin_aux_vid1 {
-			gpios = <&gpioe 3 GPIO_INPUT>;
+			gpios = <&gpioe 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
 		};
 		gpio_voldn_btn_odl: voldn_btn_odl {
-			gpios = <&gpioa 2 GPIO_INPUT_PULL_UP>;
+			gpios = <&gpio9 3 GPIO_INPUT_PULL_UP>;
 			enum-name = "GPIO_VOLUME_DOWN_L";
 		};
 		gpio_volup_btn_odl: volup_btn_odl {
-			gpios = <&gpio9 3 GPIO_INPUT_PULL_UP>;
+			gpios = <&gpioa 2 GPIO_INPUT_PULL_UP>;
 			enum-name = "GPIO_VOLUME_UP_L";
 		};
 	};
@@ -208,23 +206,23 @@
 
 		i2c_ec_i2c_eeprom: ec_i2c_eeprom {
 			i2c-port = <&i2c0_0>;
-			enum-name = "I2C_PORT_EEPROM";
+			enum-names = "I2C_PORT_EEPROM";
 		};
 		i2c_ec_i2c_sensor: ec_i2c_sensor {
 			i2c-port = <&i2c1_0>;
-			enum-name = "I2C_PORT_SENSOR";
+			enum-names = "I2C_PORT_SENSOR";
 		};
 		i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 {
 			i2c-port = <&i2c3_0>;
-			enum-name = "I2C_PORT_USB_C0_TCPC";
+			enum-names = "I2C_PORT_USB_C0_TCPC";
 		};
 		i2c_ec_i2c_sub_usb_c1: ec_i2c_sub_usb_c1 {
 			i2c-port = <&i2c5_1>;
-			enum-name = "I2C_PORT_USB_C1_TCPC";
+			enum-names = "I2C_PORT_USB_C1_TCPC";
 		};
 		i2c_ec_i2c_batt: ec_i2c_batt {
 			i2c-port = <&i2c7_0>;
-			enum-name = "I2C_PORT_BATTERY";
+			enum-names = "I2C_PORT_BATTERY";
 		};
 	};
 };
@@ -234,7 +232,8 @@
 	pinctrl-0 = <&adc0_chan0_gp45
 		     &adc0_chan1_gp44
 		     &adc0_chan4_gp41
-		     &adc0_chan6_gp34>;
+		     &adc0_chan6_gp34
+		     &adc0_chan10_gpe0>;
 	pinctrl-names = "default";
 };
 
diff --git a/zephyr/projects/nissa/craask_keyboard.dts b/zephyr/projects/nissa/craask/keyboard.dts
index d3fd354b8f..f9e46de1f2 100644
--- a/zephyr/projects/nissa/craask_keyboard.dts
+++ b/zephyr/projects/nissa/craask/keyboard.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/nissa/craask/motionsense.dts b/zephyr/projects/nissa/craask/motionsense.dts
new file mode 100644
index 0000000000..448aed6991
--- /dev/null
+++ b/zephyr/projects/nissa/craask/motionsense.dts
@@ -0,0 +1,257 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/motionsense/utils.h>
+
+
+/ {
+	aliases {
+		/*
+		 * Interrupt bindings for sensor devices.
+		 */
+		lsm6dso-int = &base_accel;
+		lis2dw12-int = &lid_accel;
+		bmi3xx-int = &base_accel;
+	};
+
+	/*
+	 * Declare mutexes used by sensor drivers.
+	 * A mutex node is used to create an instance of mutex_t.
+	 * A mutex node is referenced by a sensor node if the
+	 * corresponding sensor driver needs to use the
+	 * instance of the mutex.
+	 */
+	motionsense-mutex {
+		compatible = "cros-ec,motionsense-mutex";
+		lid_mutex: lis2dw12-mutex {
+		};
+
+		lid_mutex_bma422: bma422-mutex {
+		};
+
+		base_mutex: base-mutex {
+		};
+
+		base_mutex_bmi323: bmi323-mutex {
+		};
+	};
+
+	/* Rotation matrix used by drivers. */
+	motionsense-rotation-ref {
+		compatible = "cros-ec,motionsense-rotation-ref";
+		lid_rot_ref: lid-rotation-ref {
+			mat33 = <(-1) 0 0
+				 0 1 0
+				 0 0 (-1)>;
+		};
+
+		base_rot_ref: base-rotation-ref {
+			mat33 = <1 0 0
+				 0 (-1) 0
+				 0 0 (-1)>;
+		};
+
+		base_rot_ver1: base-rotation-ver1 {
+			mat33 = <(-1) 0 0
+				 0 (-1) 0
+				 0 0 1>;
+		};
+
+		lid_rot_bma422: lid-rotation-bma {
+			mat33 = <1 0 0
+				 0 (-1) 0
+				 0 0 (-1)>;
+		};
+
+		base_rot_bmi323: base-rotation-bmi323 {
+			mat33 = <1 0 0
+				 0 (-1) 0
+				 0 0 (-1)>;
+		};
+	};
+
+	/*
+	 * Driver specific data. A driver-specific data can be shared with
+	 * different motion sensors while they are using the same driver.
+	 *
+	 * If a node's compatible starts with "cros-ec,accelgyro-", it is for
+	 * a common structure defined in accelgyro.h.
+	 * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for
+	 * "struct als_drv_data_t" in accelgyro.h
+	 */
+	motionsense-sensor-data {
+		lsm6dso_accel_data: lsm6dso-accel-drv-data {
+			compatible = "cros-ec,drvdata-lsm6dso";
+			status = "okay";
+		};
+
+		lsm6dso_gyro_data: lsm6dso-gyro-drv-data {
+			compatible = "cros-ec,drvdata-lsm6dso";
+			status = "okay";
+		};
+
+		lis2dw12_data: lis2dw12-drv-data {
+			compatible = "cros-ec,drvdata-lis2dw12";
+			status = "okay";
+		};
+
+		bma422_data: bma4xx-drv-data {
+			compatible = "cros-ec,drvdata-bma4xx";
+			status = "okay";
+		};
+
+		bmi323_data: bmi323-drv-data {
+			compatible = "cros-ec,drvdata-bmi3xx";
+			status = "okay";
+		};
+	};
+
+	/*
+	 * List of motion sensors that creates motion_sensors array.
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
+	 * motion sensor IDs for lid angle calculation.
+	 * TODO(b/238139272): The first entries of the array must be
+	 * accelerometers,then gyroscope. Fix this dependency in the DTS
+	 * processing which makes the devicetree entries independent.
+	 */
+	motionsense-sensor {
+		lid_accel: lid-accel {
+			compatible = "cros-ec,lis2dw12";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&lid_mutex>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&lid_rot_ref>;
+			default-range = <2>;
+			drv-data = <&lis2dw12_data>;
+			i2c-spi-addr-flags = "LIS2DWL_ADDR0_FLAGS";
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_accel: base-accel {
+			compatible = "cros-ec,lsm6dso-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&lsm6dso_accel_data>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_gyro: base-gyro {
+			compatible = "cros-ec,lsm6dso-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			default-range = <(1000 | ROUND_UP_FLAG)>; /* dps */
+			drv-data = <&lsm6dso_gyro_data>;
+		};
+	};
+
+	motionsense-sensor-alt {
+		alt_lid_accel: alt-lid-accel {
+			compatible = "cros-ec,bma4xx";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&lid_mutex_bma422>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&lid_rot_bma422>;
+			default-range = <2>;
+			drv-data = <&bma422_data>;
+			i2c-spi-addr-flags = "BMA4_I2C_ADDR_PRIMARY";
+			alternate-for = <&lid_accel>;
+			alternate-ssfc-indicator = <&lid_sensor_1>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		alt_base_accel: alt-base-accel {
+			compatible = "cros-ec,bmi3xx-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex_bmi323>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&base_rot_bmi323>;
+			drv-data = <&bmi323_data>;
+			alternate-for = <&base_accel>;
+			alternate-ssfc-indicator = <&base_sensor_1>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		alt_base_gyro: alt-base-gyro {
+			compatible = "cros-ec,bmi3xx-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex_bmi323>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&base_rot_bmi323>;
+			drv-data = <&bmi323_data>;
+			alternate-for = <&base_gyro>;
+			alternate-ssfc-indicator = <&base_sensor_1>;
+		};
+	};
+
+	motionsense-sensor-info {
+		compatible = "cros-ec,motionsense-sensor-info";
+
+		/*
+		 * list of GPIO interrupts that have to
+		 * be enabled at initial stage
+		 */
+		sensor-irqs = <&int_imu>;
+		/* list of sensors in force mode */
+		accel-force-mode-sensors = <&lid_accel>;
+	};
+};
diff --git a/zephyr/projects/nissa/craask_overlay.dts b/zephyr/projects/nissa/craask/overlay.dts
index 1ff3022124..b3a510c111 100644
--- a/zephyr/projects/nissa/craask_overlay.dts
+++ b/zephyr/projects/nissa/craask/overlay.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,6 +22,12 @@
 		default_battery: lgc {
 			compatible = "lgc,ap18c8k", "battery-smart";
 		};
+		cosmx {
+			compatible = "cosmx,ap20cbl", "battery-smart";
+		};
+		cosmx-2 {
+			compatible = "cosmx,ap20cbl-2", "battery-smart";
+		};
 	};
 
 	hibernate-wake-pins {
@@ -58,7 +64,7 @@
 		int_imu: ec_imu {
 			irq-pin = <&gpio_imu_int_l>;
 			flags = <GPIO_INT_EDGE_FALLING>;
-			handler = "lsm6dso_interrupt";
+			handler = "motion_interrupt";
 		};
 		int_vol_down: vol_down {
 			irq-pin = <&gpio_voldn_btn_odl>;
@@ -83,24 +89,36 @@
 	};
 
 	named-gpios {
-		gpio_sb_1: sb_1 {
+		gpio_sb_1: sb-1 {
 			gpios = <&gpio0 2 GPIO_PULL_UP>;
 			no-auto-init;
 		};
 
-		gpio_sb_2: sb_2 {
+		gpio_sb_2: sb-2 {
 			gpios = <&gpiod 4 GPIO_OUTPUT>;
 			no-auto-init;
 		};
 
-		gpio_sb_3: sb_3 {
-			gpios = <&gpiof 4 GPIO_OPEN_DRAIN>;
+		/*
+		 * Set I2C pins for type C sub-board to be low voltage (I2C5_1).
+		 * We do this for all boards, since the pins are 3.3V tolerant,
+		 * and the only 2 types of sub-boards used on nivviks both have
+		 * type-C ports on them.
+		 */
+		gpio_sb_3: sb-3 {
+			gpios = <&gpiof 4 (GPIO_OPEN_DRAIN | GPIO_VOLTAGE_1P8)>;
 			no-auto-init;
 		};
-		gpio_sb_4: sb_4 {
-			gpios = <&gpiof 5 GPIO_INPUT>;
+		gpio_sb_4: sb-4 {
+			gpios = <&gpiof 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
 			no-auto-init;
 		};
+		ec-i2c-sensor-scl {
+			gpios = <&gpio9 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		ec-i2c-sensor-sda {
+			gpios = <&gpio8 7 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
 	};
 
 	/*
@@ -128,32 +146,50 @@
 		gpio-en-sub-s5-rails = &gpio_sb_2;
 	};
 
+	temp_memory: memory {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_1>;
+	};
+	temp_charger: charger {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_2>;
+	};
+	temp_ambient: ambient {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_3>;
+	};
+
 	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
 		memory {
-			compatible = "cros-ec,temp-sensor-thermistor",
-				     "cros-ec,temp-sensor";
-			thermistor = <&thermistor_3V3_51K1_47K_4050B>;
-			label = "DDR and SOC";
-			enum-name = "TEMP_SENSOR_1";
 			temp_fan_off = <35>;
 			temp_fan_max = <60>;
 			temp_host_high = <85>;
 			temp_host_halt = <90>;
 			temp_host_release_high = <80>;
-			adc = <&adc_temp_sensor_1>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_memory>;
 		};
 		charger {
-			compatible = "cros-ec,temp-sensor-thermistor",
-				     "cros-ec,temp-sensor";
-			thermistor = <&thermistor_3V3_51K1_47K_4050B>;
-			label = "Charger";
-			enum-name = "TEMP_SENSOR_2";
 			temp_fan_off = <35>;
 			temp_fan_max = <60>;
 			temp_host_high = <85>;
 			temp_host_halt = <90>;
 			temp_host_release_high = <80>;
-			adc = <&adc_temp_sensor_2>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_charger>;
+		};
+		ambient {
+			temp_fan_off = <35>;
+			temp_fan_max = <60>;
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_ambient>;
 		};
 	};
 
@@ -179,21 +215,12 @@
 		port0@0 {
 			compatible = "named-usbc-port";
 			reg = <0>;
-			bc12 {
-				compatible = "pericom,pi3usb9201";
-				port = <&i2c_ec_i2c_usb_c0>;
-				/*
-				 * BC1.2 interrupt is shared with TCPC, so
-				 * IRQ is not specified here and handled by
-				 * usb_c0_interrupt.
-				 */
-			};
-			chg {
-				compatible = "intersil,isl923x";
-				status = "okay";
-				port = <&i2c_ec_i2c_usb_c0>;
+			bc12 = <&bc12_port0>;
+			chg = <&chg_port0>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_0>;
 			};
-			usb-muxes = <&virtual_mux_0>;
 		};
 		port0-muxes {
 			virtual_mux_0: virtual-mux-0 {
@@ -207,50 +234,29 @@
 		port1@1 {
 			compatible = "named-usbc-port";
 			reg = <1>;
-			bc12 {
-				compatible = "pericom,pi3usb9201";
-				port = <&i2c_ec_i2c_sub_usb_c1>;
+			bc12 = <&bc12_port1>;
+			chg = <&chg_port1>;
+			usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_1 &anx7483_mux_1>;
 			};
-			chg {
-				compatible = "intersil,isl923x";
-				status = "okay";
-				port = <&i2c_ec_i2c_sub_usb_c1>;
+			usb_mux_chain_1_no_mux: usb-mux-chain-1-no-mux {
+				compatible = "cros-ec,usb-mux-chain";
+				alternative-chain;
+				usb-muxes = <&virtual_mux_1>;
 			};
-			/*
-			 * Some sub-boards may disable all usb muxes in chain
-			 * except virtual_mux_1
-			 */
-			usb-muxes = <&virtual_mux_1 &anx7483_mux_1>;
 		};
 		port1-muxes {
 			virtual_mux_1: virtual-mux-1 {
 				compatible = "cros-ec,usbc-mux-virtual";
 			};
-			anx7483_mux_1: anx7483-mux-1 {
-				compatible = "analogix,anx7483";
-				port = <&i2c_ec_i2c_sub_usb_c1>;
-				i2c-addr-flags = "ANX7483_I2C_ADDR0_FLAGS";
-			};
 		};
 	};
 
 	kblight {
 		compatible = "cros-ec,kblight-pwm";
-		pwms = <&pwm6 6 0 PWM_POLARITY_NORMAL>;
-		frequency = <10000>;
+		pwms = <&pwm6 6 PWM_HZ(2400) PWM_POLARITY_NORMAL>;
 	};
-
-	/*
-	 * Set I2C pins for type C sub-board to be
-	 * low voltage (I2C5_1).
-	 * We do this for all boards, since the pins are
-	 * 3.3V tolerant, and the only 2 types of sub-boards
-	 * used on nivviks both have type-C ports on them.
-	 */
-	 def-lvol-io-list {
-		compatible = "nuvoton,npcx-lvolctrl-def";
-		lvol-io-pads = <&lvol_iof5 &lvol_iof4>;
-	 };
 };
 
 &thermistor_3V3_51K1_47K_4050B {
@@ -277,7 +283,6 @@
 	cbi_eeprom: eeprom@50 {
 		compatible = "atmel,at24";
 		reg = <0x50>;
-		label = "EEPROM_CBI";
 		size = <2048>;
 		pagesize = <16>;
 		address-width = <8>;
@@ -293,11 +298,46 @@
 &i2c3_0 {
 	label = "I2C_USB_C0_TCPC";
 	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+
+	bc12_port0: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+		/*
+		 * BC1.2 interrupt is shared with TCPC, so
+		 * IRQ is not specified here and handled by
+		 * usb_c0_interrupt.
+		 */
+	};
+
+	chg_port0: isl923x@9 {
+		compatible = "intersil,isl923x";
+		status = "okay";
+		reg = <0x9>;
+	};
 };
 
 &i2c5_1 {
 	label = "I2C_SUB_C1_TCPC";
 	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+
+	bc12_port1: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+	};
+
+	chg_port1: isl923x@9 {
+		compatible = "intersil,isl923x";
+		status = "okay";
+		reg = <0x9>;
+	};
+
+	anx7483_mux_1: anx7483-mux-1@3e {
+		compatible = "analogix,anx7483";
+		reg = <0x3e>;
+		board-set = "anx7483_set_default_tuning";
+	};
 };
 
 &i2c7_0 {
@@ -307,6 +347,7 @@
 
 &pwm6 {
 	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
 	pinctrl-0 = <&pwm6_gpc0>;
 	pinctrl-names = "default";
 };
diff --git a/zephyr/projects/nissa/nivviks_power_signals.dts b/zephyr/projects/nissa/craask/power_signals.dts
index 91876f0402..1d2b23069d 100644
--- a/zephyr/projects/nissa/nivviks_power_signals.dts
+++ b/zephyr/projects/nissa/craask/power_signals.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/nissa/craask/prj.conf b/zephyr/projects/nissa/craask/prj.conf
new file mode 100644
index 0000000000..b7f31cee63
--- /dev/null
+++ b/zephyr/projects/nissa/craask/prj.conf
@@ -0,0 +1,15 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_BOARD_CRAASK=y
+CONFIG_PLATFORM_EC_OCPC=y
+
+# Sensor drivers
+CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSO=y
+CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y
+CONFIG_PLATFORM_EC_DYNAMIC_MOTION_SENSOR_COUNT=y
+
+CONFIG_PLATFORM_EC_BUTTONS_RUNTIME_CONFIG=y
diff --git a/zephyr/projects/nissa/nivviks_pwm_leds.dts b/zephyr/projects/nissa/craask/pwm_leds.dts
index b6f657fb03..e55aa1c9ef 100644
--- a/zephyr/projects/nissa/nivviks_pwm_leds.dts
+++ b/zephyr/projects/nissa/craask/pwm_leds.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,7 +17,6 @@
 		compatible = "cros-ec,pwm-leds";
 
 		leds = <&pwm_led0>;
-		frequency = <324>;
 
 				/*<red green blue>*/
 		color-map-red    = <100   0    0>;
@@ -25,7 +24,7 @@
 		color-map-blue   = <  0   0  100>;
 		color-map-yellow = <  0  50   50>;
 		color-map-white  = <100 100  100>;
-		color-map-amber  = <100  20  100>;
+		color-map-amber  = < 90  10    0>;
 
 		brightness-range = <100 100 100 0 0 0>;
 
diff --git a/zephyr/projects/nissa/src/craask/charger.c b/zephyr/projects/nissa/craask/src/charger.c
index 3fbbabec6b..d4723e4a0a 100644
--- a/zephyr/projects/nissa/src/craask/charger.c
+++ b/zephyr/projects/nissa/craask/src/charger.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/nissa/craask/src/form_factor.c b/zephyr/projects/nissa/craask/src/form_factor.c
new file mode 100644
index 0000000000..59869eaa2f
--- /dev/null
+++ b/zephyr/projects/nissa/craask/src/form_factor.c
@@ -0,0 +1,121 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/devicetree.h>
+#include <zephyr/logging/log.h>
+
+#include "accelgyro.h"
+#include "button.h"
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+#include "driver/accelgyro_bmi323.h"
+#include "driver/accelgyro_lsm6dso.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "motionsense_sensors.h"
+#include "motion_sense.h"
+#include "tablet_mode.h"
+
+#include "nissa_common.h"
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+/*
+ * Mainboard orientation support.
+ */
+
+#define LIS_ALT_MAT SENSOR_ROT_STD_REF_NAME(DT_NODELABEL(lid_rot_bma422))
+#define BMA_ALT_MAT SENSOR_ROT_STD_REF_NAME(DT_NODELABEL(lid_rot_ref))
+#define ALT_MAT SENSOR_ROT_STD_REF_NAME(DT_NODELABEL(base_rot_ver1))
+#define LID_SENSOR SENSOR_ID(DT_NODELABEL(lid_accel))
+#define BASE_SENSOR SENSOR_ID(DT_NODELABEL(base_accel))
+#define BASE_GYRO SENSOR_ID(DT_NODELABEL(base_gyro))
+#define ALT_LID_S SENSOR_ID(DT_NODELABEL(alt_lid_accel))
+
+static bool use_alt_sensor;
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	if (use_alt_sensor)
+		bmi3xx_interrupt(signal);
+	else
+		lsm6dso_interrupt(signal);
+}
+
+static void form_factor_init(void)
+{
+	int ret;
+	uint32_t val;
+	enum nissa_sub_board_type sb = nissa_get_sb_type();
+
+	ret = cbi_get_board_version(&val);
+	if (ret != EC_SUCCESS) {
+		LOG_ERR("Error retrieving CBI BOARD_VER.");
+		return;
+	}
+	/*
+	 * The volume up/down button are exchanged on ver3 USB
+	 * sub board.
+	 *
+	 * LTE:
+	 *   volup -> gpioa2, voldn -> gpio93
+	 * USB:
+	 *   volup -> gpio93, voldn -> gpioa2
+	 */
+	if (val == 3 && sb == NISSA_SB_C_A) {
+		LOG_INF("Volume up/down btn exchanged on ver3 USB sku");
+		buttons[BUTTON_VOLUME_UP].gpio = GPIO_VOLUME_DOWN_L;
+		buttons[BUTTON_VOLUME_DOWN].gpio = GPIO_VOLUME_UP_L;
+	}
+
+	/*
+	 * If the board version is 1
+	 * use ver1 rotation matrix.
+	 */
+	if (val == 1) {
+		LOG_INF("Switching to ver1 base");
+		motion_sensors[BASE_SENSOR].rot_standard_ref = &ALT_MAT;
+		motion_sensors[BASE_GYRO].rot_standard_ref = &ALT_MAT;
+	}
+
+	/*
+	 * If the firmware config indicates
+	 * an craaskbowl form factor, use the alternative
+	 * rotation matrix.
+	 */
+	ret = cros_cbi_get_fw_config(FW_LID_INVERSION, &val);
+	if (ret != 0) {
+		LOG_ERR("Error retrieving CBI FW_CONFIG field %d",
+			FW_LID_INVERSION);
+		return;
+	}
+	if (val == FW_LID_XY_ROT_180) {
+		LOG_INF("Lid sensor placement rotate 180 on xy plane");
+		motion_sensors[LID_SENSOR].rot_standard_ref = &LIS_ALT_MAT;
+		motion_sensors_alt[ALT_LID_S].rot_standard_ref = &BMA_ALT_MAT;
+	}
+
+	/* check which base sensor is used for motion_interrupt */
+	use_alt_sensor = cros_cbi_ssfc_check_match(
+		CBI_SSFC_VALUE_ID(DT_NODELABEL(base_sensor_1)));
+
+	motion_sensors_check_ssfc();
+
+	/* Check if it's clamshell or convertible */
+	ret = cros_cbi_get_fw_config(FORM_FACTOR, &val);
+	if (ret != 0) {
+		LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FORM_FACTOR);
+		return;
+	}
+	if (val == CLAMSHELL) {
+		LOG_INF("Clamshell: disable motionsense function.");
+		motion_sensor_count = 0;
+		gmr_tablet_switch_disable();
+		gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_imu));
+		gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_imu_int_l),
+				      GPIO_DISCONNECTED);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, form_factor_init, HOOK_PRIO_POST_I2C);
diff --git a/zephyr/projects/nissa/src/pujjo/keyboard.c b/zephyr/projects/nissa/craask/src/keyboard.c
index e6d819e348..65229eb43f 100644
--- a/zephyr/projects/nissa/src/pujjo/keyboard.c
+++ b/zephyr/projects/nissa/craask/src/keyboard.c
@@ -1,11 +1,11 @@
-/* Copyright 2022 The ChromiumOS Authors.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "ec_commands.h"
 
-static const struct ec_response_keybd_config pujjo_kb = {
+static const struct ec_response_keybd_config craask_kb = {
 	.num_top_row_keys = 10,
 	.action_keys = {
 		TK_BACK,		/* T1 */
@@ -22,8 +22,8 @@ static const struct ec_response_keybd_config pujjo_kb = {
 	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
 };
 
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
-	return &pujjo_kb;
+	return &craask_kb;
 }
diff --git a/zephyr/projects/nissa/craask/src/led.c b/zephyr/projects/nissa/craask/src/led.c
new file mode 100644
index 0000000000..0af0202cf4
--- /dev/null
+++ b/zephyr/projects/nissa/craask/src/led.c
@@ -0,0 +1,56 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery LED control for nissa
+ */
+#include "common.h"
+#include "ec_commands.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+#include "led_pwm.h"
+
+__override const int led_charge_lvl_1 = 5;
+__override const int led_charge_lvl_2 = 97;
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_BLUE,
+					   2 * LED_ONE_SEC } },
+	};
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_RED:
+		set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_RED);
+		break;
+	case EC_LED_COLOR_BLUE:
+		set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_BLUE);
+		break;
+	case EC_LED_COLOR_AMBER:
+		set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_AMBER);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		set_pwm_led_color(EC_LED_ID_BATTERY_LED, -1);
+		break;
+	}
+}
diff --git a/zephyr/projects/nissa/src/pujjo/usbc.c b/zephyr/projects/nissa/craask/src/usbc.c
index 020f78dbdd..a15460a212 100644
--- a/zephyr/projects/nissa/src/pujjo/usbc.c
+++ b/zephyr/projects/nissa/craask/src/usbc.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The ChromiumOS Authors.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -54,8 +54,7 @@ int board_is_sourcing_vbus(int port)
 
 int board_set_active_charge_port(int port)
 {
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	int i;
 	int old_port;
 
@@ -233,8 +232,7 @@ static void usbc_interrupt_trigger(int port)
 	usb_charger_task_set_event(port, USB_CHG_EVENT_BC12);
 }
 
-static inline void poll_usb_gpio(int port,
-				 const struct gpio_dt_spec *gpio,
+static inline void poll_usb_gpio(int port, const struct gpio_dt_spec *gpio,
 				 const struct deferred_data *ud)
 {
 	if (!gpio_pin_get_dt(gpio)) {
@@ -243,17 +241,15 @@ static inline void poll_usb_gpio(int port,
 	}
 }
 
-static void poll_c0_int (void)
+static void poll_c0_int(void)
 {
-	poll_usb_gpio(0,
-		      GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl),
+	poll_usb_gpio(0, GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl),
 		      &poll_c0_int_data);
 }
 
-static void poll_c1_int (void)
+static void poll_c1_int(void)
 {
-	poll_usb_gpio(1,
-		      GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl),
+	poll_usb_gpio(1, GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl),
 		      &poll_c1_int_data);
 }
 
diff --git a/zephyr/projects/nissa/include/nissa_common.h b/zephyr/projects/nissa/include/nissa_common.h
index 7ee9056a71..7cdaba2e50 100644
--- a/zephyr/projects/nissa/include/nissa_common.h
+++ b/zephyr/projects/nissa/include/nissa_common.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,15 +11,13 @@
 #include "usb_mux.h"
 
 enum nissa_sub_board_type {
-	NISSA_SB_UNKNOWN = -1,	/* Uninitialised */
-	NISSA_SB_NONE = 0,	/* No board defined */
-	NISSA_SB_C_A = 1,	/* USB type C, USB type A */
-	NISSA_SB_C_LTE = 2,	/* USB type C, WWAN LTE */
-	NISSA_SB_HDMI_A = 3,	/* HDMI, USB type A */
+	NISSA_SB_UNKNOWN = -1, /* Uninitialised */
+	NISSA_SB_NONE = 0, /* No board defined */
+	NISSA_SB_C_A = 1, /* USB type C, USB type A */
+	NISSA_SB_C_LTE = 2, /* USB type C, WWAN LTE */
+	NISSA_SB_HDMI_A = 3, /* HDMI, USB type A */
 };
 
-extern struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT];
-
 enum nissa_sub_board_type nissa_get_sb_type(void);
 
 #endif /* __CROS_EC_NISSA_NISSA_COMMON_H__ */
diff --git a/zephyr/projects/nissa/include/nissa_hdmi.h b/zephyr/projects/nissa/include/nissa_hdmi.h
new file mode 100644
index 0000000000..9f2f533ba7
--- /dev/null
+++ b/zephyr/projects/nissa/include/nissa_hdmi.h
@@ -0,0 +1,55 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Nissa shared HDMI sub-board functionality */
+
+#ifndef __CROS_EC_NISSA_NISSA_HDMI_H__
+#define __CROS_EC_NISSA_NISSA_HDMI_H__
+
+#include "common.h"
+
+/** True if the board supports an HDMI sub-board. */
+#define NISSA_BOARD_HAS_HDMI_SUPPORT DT_NODE_EXISTS(DT_NODELABEL(gpio_hdmi_sel))
+
+/**
+ * Configure the GPIO that controls core rails on the HDMI sub-board.
+ *
+ * This is the gpio_en_rails_odl pin, which is configured as active-low
+ * open-drain output to enable power to the HDMI sub-board (typically when the
+ * AP is in S5 or above).
+ *
+ * This function must be called if the pin is connected to the HDMI board and
+ * power is not enabled by default.
+ */
+void nissa_configure_hdmi_rails(void);
+
+/**
+ * Configure the GPIO that controls the HDMI VCC pin on the HDMI sub-board.
+ *
+ * This is the gpio_hdmi_en_odl pin, which is configured as active-low
+ * open-drain output to enable the VCC pin on the HDMI connector (typically when
+ * the AP is on, in S0 or S0ix).
+ *
+ * This function must be called if the pin is connected to the HDMI board and
+ * VCC is not enabled by default.
+ */
+void nissa_configure_hdmi_vcc(void);
+
+/**
+ * Configure the GPIOS controlling HDMI sub-board power (core rails and VCC).
+ *
+ * This function is called from shared code while configuring sub-boards, and
+ * used if an HDMI sub-board is present. The default implementation enables the
+ * core rails control pin (nissa_configure_hdmi_rails) but not VCC
+ * (nissa_configure_hdmi_vcc), assuming that the pin for VCC is not connected
+ * connected on most boards (and that VCC will be turned on whenever the core
+ * rails are turned on).
+ *
+ * A board should override this function if it needs to enable more IOs for
+ * HDMI, or if some pins need to be conditionally enabled.
+ */
+__override_proto void nissa_configure_hdmi_power_gpios(void);
+
+#endif /* __CROS_EC_NISSA_NISSA_HDMI_H__ */
diff --git a/zephyr/projects/nissa/joxer/cbi.dts b/zephyr/projects/nissa/joxer/cbi.dts
new file mode 100644
index 0000000000..afbd125b32
--- /dev/null
+++ b/zephyr/projects/nissa/joxer/cbi.dts
@@ -0,0 +1,32 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	nissa-fw-config {
+		compatible = "cros-ec,cbi-fw-config";
+
+		/*
+		 * FW_CONFIG field to indicate which keyboard layout
+		 * should be used.
+		 */
+		keyboard {
+			enum-name = "FW_KB_LAYOUT";
+			start = <3>;
+			size = <2>;
+
+			layout-1 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_KB_LAYOUT_DEFAULT";
+				value = <0>;
+				default;
+			};
+			layout-2 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_KB_LAYOUT_US2";
+				value = <1>;
+			};
+		};
+	};
+};
diff --git a/zephyr/projects/nissa/joxer/generated.dts b/zephyr/projects/nissa/joxer/generated.dts
new file mode 100644
index 0000000000..22214b9726
--- /dev/null
+++ b/zephyr/projects/nissa/joxer/generated.dts
@@ -0,0 +1,260 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * This file is auto-generated - do not edit!
+ */
+
+/ {
+
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc {
+			enum-name = "ADC_PP1050_PROC";
+			io-channels = <&adc0 14>;
+		};
+		adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 {
+			enum-name = "ADC_PP3300_S5";
+			io-channels = <&adc0 0>;
+		};
+		adc_temp_sensor_1: temp_sensor_1 {
+			enum-name = "ADC_TEMP_SENSOR_1";
+			io-channels = <&adc0 2>;
+		};
+		adc_temp_sensor_2: temp_sensor_2 {
+			enum-name = "ADC_TEMP_SENSOR_2";
+			io-channels = <&adc0 3>;
+		};
+		adc_temp_sensor_3: temp_sensor_3 {
+			enum-name = "ADC_TEMP_SENSOR_3";
+			io-channels = <&adc0 13>;
+		};
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		gpio_acc_int_l: acc_int_l {
+			gpios = <&gpioc 0 GPIO_INPUT>;
+		};
+		gpio_all_sys_pwrgd: all_sys_pwrgd {
+			gpios = <&gpiob 7 GPIO_INPUT>;
+		};
+		gpio_ccd_mode_odl: ccd_mode_odl {
+			gpios = <&gpioh 5 GPIO_INPUT>;
+			enum-name = "GPIO_CCD_MODE_ODL";
+		};
+		gpio_cpu_c10_gate_l: cpu_c10_gate_l {
+			gpios = <&gpiog 1 GPIO_INPUT>;
+		};
+		gpio_ec_battery_pres_odl: ec_battery_pres_odl {
+			gpios = <&gpioi 4 GPIO_INPUT>;
+			enum-name = "GPIO_BATT_PRES_ODL";
+		};
+		gpio_ec_cbi_wp: ec_cbi_wp {
+			gpios = <&gpioj 5 GPIO_OUTPUT>;
+		};
+		gpio_ec_edp_bl_en_od: ec_edp_bl_en_od {
+			gpios = <&gpiok 4 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_ENABLE_BACKLIGHT";
+		};
+		gpio_ec_entering_rw: ec_entering_rw {
+			gpios = <&gpioc 7 GPIO_OUTPUT>;
+			enum-name = "GPIO_ENTERING_RW";
+		};
+		gpio_ec_gsc_packet_mode: ec_gsc_packet_mode {
+			gpios = <&gpioh 1 GPIO_OUTPUT>;
+			enum-name = "GPIO_PACKET_MODE_EN";
+		};
+		gpio_ec_pch_wake_odl: ec_pch_wake_odl {
+			gpios = <&gpiob 2 GPIO_ODR_LOW>;
+		};
+		gpio_ec_prochot_odl: ec_prochot_odl {
+			gpios = <&gpioi 1 GPIO_ODR_HIGH>;
+		};
+		gpio_ec_soc_dsw_pwrok: ec_soc_dsw_pwrok {
+			gpios = <&gpiol 7 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_hdmi_hpd: ec_soc_hdmi_hpd {
+			gpios = <&gpiok 7 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_int_odl: ec_soc_int_odl {
+			gpios = <&gpiod 5 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_EC_INT_L";
+		};
+		gpio_ec_soc_pch_pwrok_od: ec_soc_pch_pwrok_od {
+			gpios = <&gpiod 6 GPIO_ODR_HIGH>;
+		};
+		gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl {
+			gpios = <&gpiob 6 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_PCH_PWRBTN_L";
+		};
+		gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l {
+			gpios = <&gpioh 0 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_rtcrst: ec_soc_rtcrst {
+			gpios = <&gpiok 2 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_sys_pwrok: ec_soc_sys_pwrok {
+			gpios = <&gpiof 2 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_vccst_pwrgd_od: ec_soc_vccst_pwrgd_od {
+			gpios = <&gpioe 5 GPIO_ODR_HIGH>;
+		};
+		gpio_ec_wp_odl: ec_wp_odl {
+			gpios = <&gpioa 6 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_en_kb_bl: en_kb_bl {
+			gpios = <&gpioj 3 GPIO_OUTPUT>;
+			enum-name = "GPIO_EN_KEYBOARD_BACKLIGHT";
+		};
+		gpio_en_pp3300_s5: en_pp3300_s5 {
+			gpios = <&gpioc 5 GPIO_OUTPUT>;
+			enum-name = "GPIO_TEMP_SENSOR_POWER";
+		};
+		gpio_en_pp5000_pen_x: en_pp5000_pen_x {
+			gpios = <&gpiob 5 GPIO_OUTPUT>;
+		};
+		gpio_en_pp5000_s5: en_pp5000_s5 {
+			gpios = <&gpiok 5 GPIO_OUTPUT>;
+		};
+		gpio_en_slp_z: en_slp_z {
+			gpios = <&gpiok 3 GPIO_OUTPUT>;
+		};
+		gpio_en_usb_a0_vbus: en_usb_a0_vbus {
+			gpios = <&gpiol 6 GPIO_OUTPUT>;
+		};
+		gpio_en_usb_c0_cc1_vconn: en_usb_c0_cc1_vconn {
+			gpios = <&gpioh 4 GPIO_OUTPUT>;
+		};
+		gpio_en_usb_c0_cc2_vconn: en_usb_c0_cc2_vconn {
+			gpios = <&gpioh 6 GPIO_OUTPUT>;
+		};
+		gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl {
+			gpios = <&gpioe 2 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		gpio_hdmi_sel: hdmi_sel {
+			gpios = <&gpioc 6 GPIO_OUTPUT>;
+		};
+		gpio_imu_int_l: imu_int_l {
+			gpios = <&gpioj 0 GPIO_INPUT>;
+		};
+		gpio_imvp91_vrrdy_od: imvp91_vrrdy_od {
+			gpios = <&gpioj 4 GPIO_INPUT>;
+		};
+		gpio_lid_open: lid_open {
+			gpios = <&gpiof 3 GPIO_INPUT>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+		gpio_pen_detect_odl: pen_detect_odl {
+			gpios = <&gpioj 1 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_pg_pp1050_mem_s3_od: pg_pp1050_mem_s3_od {
+			gpios = <&gpiod 3 GPIO_INPUT>;
+		};
+		gpio_pg_pp5000_s5_od: pg_pp5000_s5_od {
+			gpios = <&gpioe 3 GPIO_INPUT>;
+		};
+		gpio_rsmrst_pwrgd_l: rsmrst_pwrgd_l {
+			gpios = <&gpioe 1 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_slp_s0_l: slp_s0_l {
+			gpios = <&gpioe 4 GPIO_INPUT>;
+		};
+		gpio_slp_s3_l: slp_s3_l {
+			gpios = <&gpioh 3 GPIO_INPUT>;
+		};
+		gpio_slp_s4_l: slp_s4_l {
+			gpios = <&gpioi 5 GPIO_INPUT>;
+		};
+		gpio_slp_sus_l: slp_sus_l {
+			gpios = <&gpiog 2 GPIO_INPUT>;
+		};
+		gpio_sub_usb_a1_ilimit_sdp: sub_usb_a1_ilimit_sdp {
+			gpios = <&gpiof 1 GPIO_OUTPUT>;
+			enum-name = "GPIO_USB2_ILIM_SEL";
+		};
+		gpio_sys_rst_odl: sys_rst_odl {
+			gpios = <&gpiod 1 GPIO_ODR_HIGH>;
+		};
+		gpio_tablet_mode_l: tablet_mode_l {
+			gpios = <&gpioj 7 GPIO_INPUT>;
+			enum-name = "GPIO_TABLET_MODE_L";
+		};
+		gpio_usb_a0_ilimit_sdp: usb_a0_ilimit_sdp {
+			gpios = <&gpiol 5 GPIO_OUTPUT>;
+			enum-name = "GPIO_USB1_ILIM_SEL";
+		};
+		gpio_usb_c0_frs: usb_c0_frs {
+			gpios = <&gpioc 4 GPIO_OUTPUT>;
+		};
+		gpio_usb_c0_int_odl: usb_c0_int_odl {
+			gpios = <&gpiok 0 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_vccin_aux_vid0: vccin_aux_vid0 {
+			gpios = <&gpiod 0 GPIO_INPUT>;
+		};
+		gpio_vccin_aux_vid1: vccin_aux_vid1 {
+			gpios = <&gpiok 1 GPIO_INPUT>;
+		};
+		gpio_voldn_btn_odl: voldn_btn_odl {
+			gpios = <&gpioi 6 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_DOWN_L";
+		};
+		gpio_volup_btn_odl: volup_btn_odl {
+			gpios = <&gpioi 7 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_UP_L";
+		};
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		i2c_ec_i2c_eeprom: ec_i2c_eeprom {
+			i2c-port = <&i2c0>;
+			enum-names = "I2C_PORT_EEPROM";
+		};
+		i2c_ec_i2c_batt: ec_i2c_batt {
+			i2c-port = <&i2c1>;
+			enum-names = "I2C_PORT_BATTERY";
+		};
+		i2c_ec_i2c_sensor: ec_i2c_sensor {
+			i2c-port = <&i2c2>;
+			enum-names = "I2C_PORT_SENSOR";
+		};
+		i2c_ec_i2c_sub_usb_c1: ec_i2c_sub_usb_c1 {
+			i2c-port = <&i2c4>;
+			enum-names = "I2C_PORT_USB_C1_TCPC";
+		};
+		i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 {
+			i2c-port = <&i2c5>;
+			enum-names = "I2C_PORT_USB_C0_TCPC";
+		};
+	};
+};
+
+&adc0 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+};
+
+&i2c2 {
+	status = "okay";
+};
+
+&i2c4 {
+	status = "okay";
+};
+
+&i2c5 {
+	status = "okay";
+};
diff --git a/zephyr/projects/nissa/joxer/joxer_vif.xml b/zephyr/projects/nissa/joxer/joxer_vif.xml
new file mode 100644
index 0000000000..0b1f397981
--- /dev/null
+++ b/zephyr/projects/nissa/joxer/joxer_vif.xml
@@ -0,0 +1,346 @@
+<?xml version="1.0" encoding="utf-8"?>
+<vif:VIF xmlns:opt="http://usb.org/VendorInfoFileOptionalContent.xsd" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:vif="http://usb.org/VendorInfoFile.xsd">
+  <vif:VIF_Specification>3.20</vif:VIF_Specification>
+  <vif:VIF_App>
+    <vif:Vendor>USB-IF</vif:Vendor>
+    <vif:Name>VIF Editor</vif:Name>
+    <vif:Version>3.3.0.0</vif:Version>
+  </vif:VIF_App>
+  <vif:Vendor_Name>Google</vif:Vendor_Name>
+  <vif:Model_Part_Number>Joxer</vif:Model_Part_Number>
+  <vif:Product_Revision>1</vif:Product_Revision>
+  <vif:TID>0</vif:TID>
+  <vif:VIF_Product_Type value="0">Port Product</vif:VIF_Product_Type>
+  <vif:Certification_Type value="1">Reference Platform</vif:Certification_Type>
+  <vif:Product>
+    <!--Product Level Content:-->
+  </vif:Product>
+  <vif:Component>
+    <!--Component 0: Port 0-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Component-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Port_Label>0</vif:Port_Label>
+    <vif:Connector_Type value="2">Type-C®</vif:Connector_Type>
+    <vif:USB4_Supported value="false" />
+    <vif:USB_PD_Support value="true" />
+    <vif:PD_Port_Type value="4">DRP</vif:PD_Port_Type>
+    <vif:Type_C_State_Machine value="2">DRP</vif:Type_C_State_Machine>
+    <vif:Port_Battery_Powered value="true" />
+    <vif:BC_1_2_Support value="3">Both</vif:BC_1_2_Support>
+    <vif:Captive_Cable value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;General PD-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Spec_Revision_Major value="3" />
+    <vif:PD_Spec_Revision_Minor value="1" />
+    <vif:PD_Spec_Version_Major value="1" />
+    <vif:PD_Spec_Version_Minor value="3" />
+    <vif:PD_Specification_Revision value="2">Revision 3</vif:PD_Specification_Revision>
+    <vif:SOP_Capable value="true" />
+    <vif:SOP_P_Capable value="true" />
+    <vif:SOP_PP_Capable value="true" />
+    <vif:SOP_P_Debug_Capable value="false" />
+    <vif:SOP_PP_Debug_Capable value="false" />
+    <vif:Manufacturer_Info_Supported_Port value="false" />
+    <vif:Chunking_Implemented_SOP value="true" />
+    <vif:Unchunked_Extended_Messages_Supported value="false" />
+    <vif:Security_Msgs_Supported_SOP value="false" />
+    <vif:Unconstrained_Power value="false" />
+    <vif:Num_Fixed_Batteries value="1" />
+    <vif:Num_Swappable_Battery_Slots value="1" />
+    <vif:ID_Header_Connector_Type_SOP value="2">USB Type-C® Receptacle</vif:ID_Header_Connector_Type_SOP>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Capabilities-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:USB_Comms_Capable value="true" />
+    <vif:DR_Swap_To_DFP_Supported value="true" />
+    <vif:DR_Swap_To_UFP_Supported value="false" />
+    <vif:VCONN_Swap_To_On_Supported value="true" />
+    <vif:VCONN_Swap_To_Off_Supported value="true" />
+    <vif:Responds_To_Discov_SOP_UFP value="false" />
+    <vif:Responds_To_Discov_SOP_DFP value="true" />
+    <vif:Attempts_Discov_SOP value="true" />
+    <vif:Power_Interruption_Available value="0">No Interruption Possible</vif:Power_Interruption_Available>
+    <vif:Data_Reset_Supported value="false" />
+    <vif:Enter_USB_Supported value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;USB Type-C®-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Type_C_Can_Act_As_Host value="true" />
+    <vif:Type_C_Can_Act_As_Device value="false" />
+    <vif:Type_C_Implements_Try_SRC value="true" />
+    <vif:Type_C_Implements_Try_SNK value="false" />
+    <vif:Type_C_Supports_Audio_Accessory value="false" />
+    <vif:Type_C_Is_VCONN_Powered_Accessory value="false" />
+    <vif:Type_C_Is_Debug_Target_SRC value="true" />
+    <vif:Type_C_Is_Debug_Target_SNK value="true" />
+    <vif:RP_Value value="1">1.5A</vif:RP_Value>
+    <vif:Type_C_Port_On_Hub value="false" />
+    <vif:Type_C_Power_Source value="2">Both</vif:Type_C_Power_Source>
+    <vif:Type_C_Sources_VCONN value="true" />
+    <vif:Type_C_Is_Alt_Mode_Controller value="true" />
+    <vif:Type_C_Is_Alt_Mode_Adapter value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Product Power-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Product_Total_Source_Power_mW value="15000">15000 mW</vif:Product_Total_Source_Power_mW>
+    <vif:Port_Source_Power_Type value="0">Assured</vif:Port_Source_Power_Type>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;USB Host-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Host_Supports_USB_Data value="true" />
+    <vif:Host_Speed value="1">USB 3.2 Gen 1x1</vif:Host_Speed>
+    <vif:Host_Contains_Captive_Retimer value="false" />
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:Host_Is_Embedded value="false" />
+    <vif:Host_Suspend_Supported value="true" />
+    <vif:Is_DFP_On_Hub value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Battery Charging 1.2-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:BC_1_2_Charging_Port_Type value="1">CDP</vif:BC_1_2_Charging_Port_Type>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Source-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Power_As_Source value="15000">15000 mW</vif:PD_Power_As_Source>
+    <vif:EPR_Supported_As_Src value="false" />
+    <vif:USB_Suspend_May_Be_Cleared value="false" />
+    <vif:Sends_Pings value="false" />
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="0">FR_Swap not supported</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <vif:Master_Port value="false" />
+    <vif:Num_Src_PDOs value="1" />
+    <vif:PD_OC_Protection value="true" />
+    <vif:PD_OCP_Method value="0">Over-Current Response</vif:PD_OCP_Method>
+    <!--Bundle: SrcPdoList-->
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!--Source PDO 1-->
+        <vif:Src_PDO_Supply_Type value="0">Fixed</vif:Src_PDO_Supply_Type>
+        <vif:Src_PDO_Peak_Current value="0">100% IOC</vif:Src_PDO_Peak_Current>
+        <vif:Src_PDO_Voltage value="100">5000 mV</vif:Src_PDO_Voltage>
+        <vif:Src_PDO_Max_Current value="300">3000 mA</vif:Src_PDO_Max_Current>
+        <vif:Src_PD_OCP_OC_Debounce value="0">0 msec</vif:Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="300">3000 mA</vif:Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Sink-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Power_As_Sink value="45000">45000 mW</vif:PD_Power_As_Sink>
+    <vif:EPR_Supported_As_Snk value="false" />
+    <vif:No_USB_Suspend_May_Be_Set value="true" />
+    <vif:GiveBack_May_Be_Set value="false" />
+    <vif:Higher_Capability_Set value="false" />
+    <vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source value="0">FR_Swap not supported</vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source>
+    <vif:Num_Snk_PDOs value="3" />
+    <!--Bundle: SnkPdoList-->
+    <vif:SnkPdoList>
+      <vif:SnkPDO>
+        <!--Sink PDO 1-->
+        <vif:Snk_PDO_Supply_Type value="0">Fixed</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Voltage value="100">5000 mV</vif:Snk_PDO_Voltage>
+        <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>
+      </vif:SnkPDO>
+      <vif:SnkPDO>
+        <!--Sink PDO 2-->
+        <vif:Snk_PDO_Supply_Type value="1">Battery</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Op_Power value="60">15000 mW</vif:Snk_PDO_Op_Power>
+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>
+        <vif:Snk_PDO_Max_Voltage value="300">15000 mV</vif:Snk_PDO_Max_Voltage>
+      </vif:SnkPDO>
+      <vif:SnkPDO>
+        <!--Sink PDO 3-->
+        <vif:Snk_PDO_Supply_Type value="2">Variable</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>
+        <vif:Snk_PDO_Max_Voltage value="300">15000 mV</vif:Snk_PDO_Max_Voltage>
+        <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>
+      </vif:SnkPDO>
+    </vif:SnkPdoList>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Dual Role-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Accepts_PR_Swap_As_Src value="true" />
+    <vif:Accepts_PR_Swap_As_Snk value="true" />
+    <vif:Requests_PR_Swap_As_Src value="true" />
+    <vif:Requests_PR_Swap_As_Snk value="true" />
+    <vif:FR_Swap_Supported_As_Initial_Sink value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;SOP Discover ID-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:XID_SOP value="0" />
+    <vif:Data_Capable_As_USB_Host_SOP value="true" />
+    <vif:Data_Capable_As_USB_Device_SOP value="false" />
+    <vif:Product_Type_UFP_SOP value="0">Undefined</vif:Product_Type_UFP_SOP>
+    <vif:Product_Type_DFP_SOP value="0">Undefined</vif:Product_Type_DFP_SOP>
+    <vif:DFP_VDO_Port_Number value="0" />
+    <vif:Modal_Operation_Supported_SOP value="false" />
+    <vif:USB_VID_SOP value="6353">18D1</vif:USB_VID_SOP>
+    <vif:PID_SOP value="20570">505A</vif:PID_SOP>
+    <vif:bcdDevice_SOP value="0">0000</vif:bcdDevice_SOP>
+  </vif:Component>
+  <vif:Component>
+    <!--Component 1: Port 1-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Component-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Port_Label>1</vif:Port_Label>
+    <vif:Connector_Type value="2">Type-C®</vif:Connector_Type>
+    <vif:USB4_Supported value="false" />
+    <vif:USB_PD_Support value="true" />
+    <vif:PD_Port_Type value="4">DRP</vif:PD_Port_Type>
+    <vif:Type_C_State_Machine value="2">DRP</vif:Type_C_State_Machine>
+    <vif:Port_Battery_Powered value="true" />
+    <vif:BC_1_2_Support value="3">Both</vif:BC_1_2_Support>
+    <vif:Captive_Cable value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;General PD-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Spec_Revision_Major value="3" />
+    <vif:PD_Spec_Revision_Minor value="1" />
+    <vif:PD_Spec_Version_Major value="1" />
+    <vif:PD_Spec_Version_Minor value="3" />
+    <vif:PD_Specification_Revision value="2">Revision 3</vif:PD_Specification_Revision>
+    <vif:SOP_Capable value="true" />
+    <vif:SOP_P_Capable value="true" />
+    <vif:SOP_PP_Capable value="true" />
+    <vif:SOP_P_Debug_Capable value="false" />
+    <vif:SOP_PP_Debug_Capable value="false" />
+    <vif:Manufacturer_Info_Supported_Port value="false" />
+    <vif:Chunking_Implemented_SOP value="true" />
+    <vif:Unchunked_Extended_Messages_Supported value="false" />
+    <vif:Security_Msgs_Supported_SOP value="false" />
+    <vif:Unconstrained_Power value="false" />
+    <vif:Num_Fixed_Batteries value="1" />
+    <vif:Num_Swappable_Battery_Slots value="1" />
+    <vif:ID_Header_Connector_Type_SOP value="2">USB Type-C® Receptacle</vif:ID_Header_Connector_Type_SOP>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Capabilities-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:USB_Comms_Capable value="true" />
+    <vif:DR_Swap_To_DFP_Supported value="true" />
+    <vif:DR_Swap_To_UFP_Supported value="false" />
+    <vif:VCONN_Swap_To_On_Supported value="true" />
+    <vif:VCONN_Swap_To_Off_Supported value="true" />
+    <vif:Responds_To_Discov_SOP_UFP value="false" />
+    <vif:Responds_To_Discov_SOP_DFP value="true" />
+    <vif:Attempts_Discov_SOP value="true" />
+    <vif:Power_Interruption_Available value="0">No Interruption Possible</vif:Power_Interruption_Available>
+    <vif:Data_Reset_Supported value="false" />
+    <vif:Enter_USB_Supported value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;USB Type-C®-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Type_C_Can_Act_As_Host value="true" />
+    <vif:Type_C_Can_Act_As_Device value="false" />
+    <vif:Type_C_Implements_Try_SRC value="true" />
+    <vif:Type_C_Implements_Try_SNK value="false" />
+    <vif:Type_C_Supports_Audio_Accessory value="false" />
+    <vif:Type_C_Is_VCONN_Powered_Accessory value="false" />
+    <vif:Type_C_Is_Debug_Target_SRC value="true" />
+    <vif:Type_C_Is_Debug_Target_SNK value="true" />
+    <vif:RP_Value value="1">1.5A</vif:RP_Value>
+    <vif:Type_C_Port_On_Hub value="false" />
+    <vif:Type_C_Power_Source value="2">Both</vif:Type_C_Power_Source>
+    <vif:Type_C_Sources_VCONN value="true" />
+    <vif:Type_C_Is_Alt_Mode_Controller value="true" />
+    <vif:Type_C_Is_Alt_Mode_Adapter value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Product Power-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Product_Total_Source_Power_mW value="15000">15000 mW</vif:Product_Total_Source_Power_mW>
+    <vif:Port_Source_Power_Type value="0">Assured</vif:Port_Source_Power_Type>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;USB Host-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Host_Supports_USB_Data value="true" />
+    <vif:Host_Speed value="1">USB 3.2 Gen 1x1</vif:Host_Speed>
+    <vif:Host_Contains_Captive_Retimer value="true" />
+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />
+    <vif:Host_Is_Embedded value="false" />
+    <vif:Host_Suspend_Supported value="true" />
+    <vif:Is_DFP_On_Hub value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Battery Charging 1.2-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:BC_1_2_Charging_Port_Type value="1">CDP</vif:BC_1_2_Charging_Port_Type>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Source-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Power_As_Source value="15000">15000 mW</vif:PD_Power_As_Source>
+    <vif:EPR_Supported_As_Src value="false" />
+    <vif:USB_Suspend_May_Be_Cleared value="false" />
+    <vif:Sends_Pings value="false" />
+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="0">FR_Swap not supported</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>
+    <vif:Master_Port value="false" />
+    <vif:Num_Src_PDOs value="1" />
+    <vif:PD_OC_Protection value="true" />
+    <vif:PD_OCP_Method value="0">Over-Current Response</vif:PD_OCP_Method>
+    <!--Bundle: SrcPdoList-->
+    <vif:SrcPdoList>
+      <vif:SrcPDO>
+        <!--Source PDO 1-->
+        <vif:Src_PDO_Supply_Type value="0">Fixed</vif:Src_PDO_Supply_Type>
+        <vif:Src_PDO_Peak_Current value="0">100% IOC</vif:Src_PDO_Peak_Current>
+        <vif:Src_PDO_Voltage value="100">5000 mV</vif:Src_PDO_Voltage>
+        <vif:Src_PDO_Max_Current value="300">3000 mA</vif:Src_PDO_Max_Current>
+        <vif:Src_PD_OCP_OC_Debounce value="0">0 msec</vif:Src_PD_OCP_OC_Debounce>
+        <vif:Src_PD_OCP_OC_Threshold value="300">3000 mA</vif:Src_PD_OCP_OC_Threshold>
+      </vif:SrcPDO>
+    </vif:SrcPdoList>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;PD Sink-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:PD_Power_As_Sink value="45000">45000 mW</vif:PD_Power_As_Sink>
+    <vif:EPR_Supported_As_Snk value="false" />
+    <vif:No_USB_Suspend_May_Be_Set value="true" />
+    <vif:GiveBack_May_Be_Set value="false" />
+    <vif:Higher_Capability_Set value="false" />
+    <vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source value="0">FR_Swap not supported</vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source>
+    <vif:Num_Snk_PDOs value="3" />
+    <!--Bundle: SnkPdoList-->
+    <vif:SnkPdoList>
+      <vif:SnkPDO>
+        <!--Sink PDO 1-->
+        <vif:Snk_PDO_Supply_Type value="0">Fixed</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Voltage value="100">5000 mV</vif:Snk_PDO_Voltage>
+        <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>
+      </vif:SnkPDO>
+      <vif:SnkPDO>
+        <!--Sink PDO 2-->
+        <vif:Snk_PDO_Supply_Type value="1">Battery</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Op_Power value="60">15000 mW</vif:Snk_PDO_Op_Power>
+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>
+        <vif:Snk_PDO_Max_Voltage value="300">15000 mV</vif:Snk_PDO_Max_Voltage>
+      </vif:SnkPDO>
+      <vif:SnkPDO>
+        <!--Sink PDO 3-->
+        <vif:Snk_PDO_Supply_Type value="2">Variable</vif:Snk_PDO_Supply_Type>
+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>
+        <vif:Snk_PDO_Max_Voltage value="300">15000 mV</vif:Snk_PDO_Max_Voltage>
+        <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>
+      </vif:SnkPDO>
+    </vif:SnkPdoList>
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;Dual Role-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:Accepts_PR_Swap_As_Src value="true" />
+    <vif:Accepts_PR_Swap_As_Snk value="true" />
+    <vif:Requests_PR_Swap_As_Src value="true" />
+    <vif:Requests_PR_Swap_As_Snk value="true" />
+    <vif:FR_Swap_Supported_As_Initial_Sink value="false" />
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <!--;SOP Discover ID-->
+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->
+    <vif:XID_SOP value="0" />
+    <vif:Data_Capable_As_USB_Host_SOP value="true" />
+    <vif:Data_Capable_As_USB_Device_SOP value="false" />
+    <vif:Product_Type_UFP_SOP value="0">Undefined</vif:Product_Type_UFP_SOP>
+    <vif:Product_Type_DFP_SOP value="0">Undefined</vif:Product_Type_DFP_SOP>
+    <vif:DFP_VDO_Port_Number value="1" />
+    <vif:Modal_Operation_Supported_SOP value="false" />
+    <vif:USB_VID_SOP value="6353">18D1</vif:USB_VID_SOP>
+    <vif:PID_SOP value="20570">505A</vif:PID_SOP>
+    <vif:bcdDevice_SOP value="0">0000</vif:bcdDevice_SOP>
+  </vif:Component>
+</vif:VIF>
\ No newline at end of file
diff --git a/zephyr/projects/nissa/nereid_keyboard.dts b/zephyr/projects/nissa/joxer/keyboard.dts
index ae104b1ead..04a620767a 100644
--- a/zephyr/projects/nissa/nereid_keyboard.dts
+++ b/zephyr/projects/nissa/joxer/keyboard.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,8 +6,11 @@
 / {
 	kblight {
 		compatible = "cros-ec,kblight-pwm";
-		pwms = <&pwm0 0 PWM_KHZ(10) PWM_POLARITY_NORMAL>;
-		frequency = <10000>;
+		/*
+		 * Use 324 Hz so that 32Khz clock source is used,
+		 * which is not gated in power saving mode.
+		 */
+		pwms = <&pwm0 0 PWM_HZ(324) PWM_POLARITY_NORMAL>;
 	};
 };
 
diff --git a/zephyr/projects/nissa/pujjo_motionsense.dts b/zephyr/projects/nissa/joxer/motionsense.dts
index 69ebf04c59..537cc34451 100644
--- a/zephyr/projects/nissa/pujjo_motionsense.dts
+++ b/zephyr/projects/nissa/joxer/motionsense.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,7 @@
 		/*
 		 * Interrupt bindings for sensor devices.
 		 */
-		lsm6dso-int = &base_accel;
-		lis2dw12-int = &lid_accel;
+		bmi3xx-int = &base_accel;
 	};
 
 	/*
@@ -25,11 +24,9 @@
 	motionsense-mutex {
 		compatible = "cros-ec,motionsense-mutex";
 		lid_mutex: lid-mutex {
-			label = "LID_MUTEX";
 		};
 
 		base_mutex: base-mutex {
-			label = "BASE_MUTEX";
 		};
 	};
 
@@ -37,14 +34,14 @@
 	motionsense-rotation-ref {
 		compatible = "cros-ec,motionsense-rotation-ref";
 		lid_rot_ref: lid-rotation-ref {
-			mat33 = <(-1) 0 0
-				 0 1 0
+			mat33 = <0 (-1) 0
+				 (-1) 0 0
 				 0 0 (-1)>;
 		};
 
-		base_rot_ref: base-rot-ref {
-			mat33 = <(-1) 0 0
-				 0 (-1) 0
+		base_rot_ref: base-rotation-ref {
+			mat33 = <1 0 0
+				 0 1 0
 				 0 0 1>;
 		};
 	};
@@ -59,93 +56,82 @@
 	 * "struct als_drv_data_t" in accelgyro.h
 	 */
 	motionsense-sensor-data {
-		lsm6dso_data: lsm6dso-drv-data {
-			compatible = "cros-ec,drvdata-lsm6dso";
+		bmi323_data: bmi323-drv-data {
+			compatible = "cros-ec,drvdata-bmi3xx";
 			status = "okay";
 		};
 
-		lis2dw12_data: lis2dw12-drv-data {
-			compatible = "cros-ec,drvdata-lis2dw12";
+		bma422_data: bma422-drv-data {
+			compatible = "cros-ec,drvdata-bma4xx";
 			status = "okay";
 		};
 	};
 
 	/*
 	 * List of motion sensors that creates motion_sensors array.
-	 * The label "lid_accel" and "base_accel" are used to indicate
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
 	 * motion sensor IDs for lid angle calculation.
-	 * TODO:(b/229577857) The first entries of the array must be
+	 * TODO(b/238139272): The first entries of the array must be
 	 * accelerometers,then gyroscope. Fix this dependency in the DTS
 	 * processing which makes the devicetree entries independent.
 	 */
 	motionsense-sensor {
 		lid_accel: lid-accel {
-			compatible = "cros-ec,lis2dw12";
+			compatible = "cros-ec,bma4xx";
 			status = "okay";
 
-			label = "Lid Accel";
 			active-mask = "SENSOR_ACTIVE_S0_S3";
 			location = "MOTIONSENSE_LOC_LID";
 			mutex = <&lid_mutex>;
 			port = <&i2c_ec_i2c_sensor>;
 			rot-standard-ref = <&lid_rot_ref>;
 			default-range = <2>;
-			drv-data = <&lis2dw12_data>;
-			i2c-spi-addr-flags = "LIS2DWL_ADDR0_FLAGS";
+			drv-data = <&bma422_data>;
+			i2c-spi-addr-flags = "BMA4_I2C_ADDR_SECONDARY";
 			configs {
 				compatible =
 					"cros-ec,motionsense-sensor-config";
 				ec-s0 {
-					label = "SENSOR_CONFIG_EC_S0";
 					odr = <(10000 | ROUND_UP_FLAG)>;
 				};
 				ec-s3 {
-					label = "SENSOR_CONFIG_EC_S3";
 					odr = <(10000 | ROUND_UP_FLAG)>;
 				};
 			};
 		};
 
 		base_accel: base-accel {
-			compatible = "cros-ec,lsm6dso-accel";
+			compatible = "cros-ec,bmi3xx-accel";
 			status = "okay";
 
-			label = "Base Accel";
 			active-mask = "SENSOR_ACTIVE_S0_S3";
 			location = "MOTIONSENSE_LOC_BASE";
 			mutex = <&base_mutex>;
 			port = <&i2c_ec_i2c_sensor>;
-			/*
-			 * May be replaced by alternate depending
-			 * on board config.
-			 */
 			rot-standard-ref = <&base_rot_ref>;
-			drv-data = <&lsm6dso_data>;
+			drv-data = <&bmi323_data>;
 			configs {
 				compatible =
 					"cros-ec,motionsense-sensor-config";
 				ec-s0 {
-					label = "SENSOR_CONFIG_EC_S0";
 					odr = <(10000 | ROUND_UP_FLAG)>;
 				};
 				ec-s3 {
-					label = "SENSOR_CONFIG_EC_S3";
 					odr = <(10000 | ROUND_UP_FLAG)>;
 				};
 			};
 		};
 
 		base_gyro: base-gyro {
-			compatible = "cros-ec,lsm6dso-gyro";
+			compatible = "cros-ec,bmi3xx-gyro";
 			status = "okay";
 
-			label = "Base Gyro";
 			active-mask = "SENSOR_ACTIVE_S0_S3";
 			location = "MOTIONSENSE_LOC_BASE";
 			mutex = <&base_mutex>;
 			port = <&i2c_ec_i2c_sensor>;
 			rot-standard-ref = <&base_rot_ref>;
-			drv-data = <&lsm6dso_data>;
+			drv-data = <&bmi323_data>;
 		};
 	};
 
diff --git a/zephyr/projects/nissa/joxer/overlay.dts b/zephyr/projects/nissa/joxer/overlay.dts
new file mode 100644
index 0000000000..a72072b5a3
--- /dev/null
+++ b/zephyr/projects/nissa/joxer/overlay.dts
@@ -0,0 +1,448 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <cros/thermistor/thermistor.dtsi>
+
+/ {
+	aliases {
+		gpio-cbi-wp = &gpio_ec_cbi_wp;
+		gpio-wp = &gpio_ec_wp_odl;
+		int-wp = &int_wp_l;
+	};
+
+	ec-console {
+		compatible = "ec-console";
+		disabled = "events", "lpc", "hostcmd";
+	};
+
+	batteries {
+		default_battery: cosmx {
+			compatible = "cosmx,gh02047xl", "battery-smart";
+		};
+		dynapack_atl_gh02047xl {
+			compatible = "dynapack,atl_gh02047xl", "battery-smart";
+		};
+		dynapack_cosmx_gh02047xl {
+			compatible = "dynapack,cosmx_gh02047xl", "battery-smart";
+		};
+		smp_coslight_gh02047xl {
+			compatible = "smp,coslight_gh02047xl", "battery-smart";
+		};
+		smp_highpower_gh02047xl {
+			compatible = "smp,highpower_gh02047xl", "battery-smart";
+		};
+	};
+
+	hibernate-wake-pins {
+		compatible = "cros-ec,hibernate-wake-pins";
+		wakeup-irqs = <
+			&int_power_button
+			&int_lid_open
+		>;
+	};
+
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_power_button: power_button {
+			irq-pin = <&gpio_gsc_ec_pwr_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_button_interrupt";
+		};
+		int_vol_down: vol_down {
+			irq-pin = <&gpio_voldn_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+		int_vol_up: vol_up {
+			irq-pin = <&gpio_volup_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+		int_wp_l: wp_l {
+			irq-pin = <&gpio_ec_wp_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "switch_interrupt";
+		};
+		int_lid_open: lid_open {
+			irq-pin = <&gpio_lid_open>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "lid_interrupt";
+		};
+		int_tablet_mode: tablet_mode {
+			irq-pin = <&gpio_tablet_mode_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "gmr_tablet_switch_isr";
+		};
+		int_imu: ec_imu {
+		  irq-pin = <&gpio_imu_int_l>;
+		  flags = <GPIO_INT_EDGE_FALLING>;
+		  handler = "bmi3xx_interrupt";
+		};
+		int_usb_c0: usb_c0 {
+			irq-pin = <&gpio_usb_c0_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "usb_c0_interrupt";
+		};
+		int_usb_c1: usb_c1 {
+			irq-pin = <&gpio_sb_1>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "usb_c1_interrupt";
+		};
+	};
+
+	unused-pins {
+		compatible = "unused-gpios";
+		unused-gpios = <&gpioc 3 0>,
+			       <&gpiod 4 0>,
+			       <&gpioh 2 0>,
+			       <&gpiol 4 0>;
+	};
+
+	named-gpios {
+		/*
+		 * EC doesn't take any specific action on CC/SBU disconnect due to
+		 * fault, but this definition is useful for hardware testing.
+		 */
+		gpio_usb_c0_prot_fault_odl: usb_c0_prot_fault_odl {
+			gpios = <&gpiok 6 GPIO_INPUT_PULL_UP>;
+		};
+
+		gpio_sb_1: sb_1 {
+			gpios = <&gpioe 6 0>;
+			no-auto-init;
+		};
+		gpio_sb_2: sb_2 {
+			gpios = <&gpiof 0 0>;
+			no-auto-init;
+		};
+
+		gpio_sb_3: sb_3 {
+			gpios = <&gpioe 7 0>;
+			no-auto-init;
+		};
+		gpio_sb_4: sb_4 {
+			gpios = <&gpioe 0 0>;
+			no-auto-init;
+		};
+		gpio_fan_enable: fan-enable {
+			gpios = <&gpiol 4 GPIO_OUTPUT>;
+			no-auto-init;
+		};
+		gpio_power_led_gate: power_led_gate {
+			gpios = <&gpiof 1 GPIO_OUTPUT_LOW>;
+		};
+		gpio_led_1_odl: led_1_odl {
+			gpios = <&gpioa 1 GPIO_OUTPUT_HIGH>;
+		};
+		gpio_led_2_odl: led_2_odl {
+			gpios = <&gpioa 2 GPIO_OUTPUT_HIGH>;
+		};
+		gpio_led_3_l: led_3_l {
+			gpios = <&gpiol 2 GPIO_OUTPUT_HIGH>;
+		};
+		gpio_led_4_l: led_4_l {
+			gpios = <&gpiol 3 GPIO_OUTPUT_HIGH>;
+		};
+	};
+
+	/*
+	 * Aliases used for sub-board GPIOs.
+	 */
+	aliases {
+	  /* USB-C: interrupt input. I2C pins are on i2c_ec_i2c_sub_usb_c1 */
+		gpio-usb-c1-int-odl = &gpio_sb_1;
+		/*
+		 * USB-A: VBUS enable output
+		 * LTE: power enable output
+		 */
+		gpio-en-usb-a1-vbus = &gpio_sb_2;
+		/*
+		 * HDMI: power enable output, HDMI enable output,
+		 * and HPD input
+		 */
+		gpio-en-rails-odl = &gpio_sb_1;
+		gpio-hdmi-en-odl = &gpio_sb_4;
+		gpio-hpd-odl = &gpio_sb_3;
+		/*
+		 * Enable S5 rails for LTE sub-board
+		 */
+		gpio-en-sub-s5-rails = &gpio_sb_2;
+	};
+
+	temp_memory: memory {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_1>;
+	};
+	temp_charger: charger {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_2>;
+	};
+	temp_ambient: ambient {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_3>;
+	};
+
+	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
+		memory {
+			temp_fan_off = <35>;
+			temp_fan_max = <60>;
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_memory>;
+		};
+		charger {
+			temp_fan_off = <35>;
+			temp_fan_max = <60>;
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_charger>;
+		};
+		ambient {
+			temp_fan_off = <35>;
+			temp_fan_max = <60>;
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_ambient>;
+		};
+	};
+
+	usba {
+		compatible = "cros-ec,usba-port-enable-pins";
+		/*
+		 * sb_2 is only configured as GPIO when USB-A1 is present,
+		 * but it's still safe to control when disabled.
+		 *
+		 * ILIM_SEL pins are referred to by legacy enum name,
+		 * GPIO_USB*_ILIM_SEL. The one for port A1 is unused on
+		 * sub-boards that don't have USB-A so is safe to control
+		 * regardless of system configuration.
+		 */
+		enable-pins = <&gpio_en_usb_a0_vbus &gpio_sb_2>;
+		status = "okay";
+	};
+
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+			bc12 = <&bc12_port0>;
+			chg = <&chg_port0>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_0>;
+			};
+		};
+		port0-muxes {
+			virtual_mux_0: virtual-mux-0 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+		port1@1 {
+			compatible = "named-usbc-port";
+			reg = <1>;
+			bc12 = <&bc12_port1>;
+			chg = <&chg_port1>;
+			usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_1 &tcpci_mux_1>;
+			};
+			usb_mux_chain_1_no_mux: usb-mux-chain-1-no-mux {
+				compatible = "cros-ec,usb-mux-chain";
+				alternative-chain;
+				usb-muxes = <&virtual_mux_1>;
+			};
+		};
+		port1-muxes {
+			virtual_mux_1: virtual-mux-1 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+			tcpci_mux_1: tcpci-mux-1 {
+				compatible = "parade,usbc-mux-ps8xxx";
+			};
+		};
+	};
+	fans {
+		compatible = "cros-ec,fans";
+
+		fan_0 {
+			pwms = <&pwm7 PWM_CHANNEL_7 PWM_KHZ(30) PWM_POLARITY_NORMAL>;
+			tach = <&tach1>;
+			rpm_min = <1500>;
+			rpm_start = <1500>;
+			rpm_max = <6500>;
+			enable_gpio = <&gpio_fan_enable>;
+		};
+	};
+};
+
+&gpio_acc_int_l {
+	gpios = <&gpioc 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+};
+&gpio_imu_int_l {
+	gpios = <&gpioj 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+};
+&gpio_vccin_aux_vid0 {
+	gpios = <&gpiod 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+};
+&gpio_vccin_aux_vid1 {
+	gpios = <&gpiok 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+};
+
+&gpio_ec_prochot_odl {
+	gpios = <&gpioi 1 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>;
+};
+
+&thermistor_3V3_51K1_47K_4050B {
+	status = "okay";
+};
+
+&adc_ec_vsense_pp3300_s5 {
+	/*
+	 * Voltage divider on input has 47k upper and 220k lower legs with 3 V
+	 * full-scale reading on the ADC. Apply the largest possible multiplier
+	 * (without overflowing int32) to get the best possible approximation
+	 * of the actual ratio, but derate by a factor of two to ensure
+	 * unexpectedly high values won't overflow.
+	 */
+	mul = <(715828 / 2)>;
+	div = <(589820 / 2)>;
+};
+
+&adc0 {
+	pinctrl-0 = <&adc0_ch0_gpi0_default
+		     &adc0_ch2_gpi2_default
+		     &adc0_ch3_gpi3_default
+		     &adc0_ch13_gpl0_default
+		     &adc0_ch14_gpl1_default>;
+	pinctrl-names = "default";
+};
+
+&pinctrl {
+	i2c2_clk_gpf6_default: i2c2_clk_gpf6_default {
+		gpio-voltage = "1v8";
+	};
+	i2c2_data_gpf7_default: i2c2_data_gpf7_default {
+		gpio-voltage = "1v8";
+	};
+};
+
+
+&i2c0 {
+	label = "I2C_EEPROM";
+	clock-frequency = <I2C_BITRATE_FAST>;
+
+	cbi_eeprom: eeprom@50 {
+		compatible = "atmel,at24";
+		reg = <0x50>;
+		size = <2048>;
+		pagesize = <16>;
+		address-width = <8>;
+		timeout = <5>;
+	};
+	pinctrl-0 = <&i2c0_clk_gpb3_default
+		     &i2c0_data_gpb4_default>;
+	pinctrl-names = "default";
+};
+
+&i2c1 {
+	label = "I2C_BATTERY";
+	clock-frequency = <50000>;
+	pinctrl-0 = <&i2c1_clk_gpc1_default
+		     &i2c1_data_gpc2_default>;
+	pinctrl-names = "default";
+};
+
+&i2c2 {
+	label = "I2C_SENSOR";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c2_clk_gpf6_default
+		     &i2c2_data_gpf7_default>;
+	pinctrl-names = "default";
+};
+
+&i2c4 {
+	label = "I2C_SUB_C1_TCPC";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+	pinctrl-0 = <&i2c4_clk_gpe0_default
+		     &i2c4_data_gpe7_default>;
+	pinctrl-names = "default";
+
+	bc12_port1: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+	};
+
+	chg_port1: sm5803@32 {
+		compatible = "siliconmitus,sm5803";
+		status = "okay";
+		reg = <0x32>;
+	};
+};
+
+&i2c_ec_i2c_sub_usb_c1 {
+	/*
+	 * Dynamic speed setting is used for AP-controlled firmware update
+	 * of PS8745 TCPC/redriver: the AP lowers speed to 400 kHz in order
+	 * to use more efficient window programming, then sets it back when
+	 * done.
+	 */
+	dynamic-speed;
+};
+
+&i2c5 {
+	label = "I2C_USB_C0_TCPC";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+	pinctrl-0 = <&i2c5_clk_gpa4_default
+		     &i2c5_data_gpa5_default>;
+	pinctrl-names = "default";
+
+	bc12_port0: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+	};
+
+	chg_port0: sm5803@32 {
+		compatible = "siliconmitus,sm5803";
+		status = "okay";
+		reg = <0x32>;
+	};
+};
+
+/* pwm for fan */
+&pwm7 {
+	status = "okay";
+	prescaler-cx = <PWM_PRESCALER_C4>;
+	pinctrl-0 = <&pwm7_gpa7_default>;
+	pinctrl-names = "default";
+};
+
+/* fan tachometer sensor */
+&tach1 {
+	status = "okay";
+	channel = <IT8XXX2_TACH_CHANNEL_A>;
+	pulses-per-round = <2>;
+	pinctrl-0 = <&tach1a_gpd7_default>;
+	pinctrl-names = "default";
+};
+
+&usbpd0 {
+	status = "okay";
+};
diff --git a/zephyr/projects/nissa/nereid_power_signals.dts b/zephyr/projects/nissa/joxer/power_signals.dts
index 0a3ead778b..8affae03b1 100644
--- a/zephyr/projects/nissa/nereid_power_signals.dts
+++ b/zephyr/projects/nissa/joxer/power_signals.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -75,7 +75,7 @@
 		compatible = "intel,ap-pwrseq-gpio";
 		dbg-label = "VCCST_PWRGD output to PCH";
 		enum-name = "PWR_VCCST_PWRGD";
-		gpios = <&gpioe 5 GPIO_OPEN_DRAIN>;
+		gpios = <&gpioe 5 (GPIO_OPEN_DRAIN | GPIO_VOLTAGE_1P8)>;
 		output;
 	};
 	pwr-imvp9-vrrdy-od {
diff --git a/zephyr/projects/nissa/joxer/prj.conf b/zephyr/projects/nissa/joxer/prj.conf
new file mode 100644
index 0000000000..a0de72294c
--- /dev/null
+++ b/zephyr/projects/nissa/joxer/prj.conf
@@ -0,0 +1,19 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_BOARD_JOXER=y
+
+# Ensure recovery key combination (esc+refresh+power) is reliable: b/236580049
+CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI3=y
+CONFIG_PLATFORM_EC_KEYBOARD_REFRESH_ROW3=y
+
+# Sensor drivers
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y
+CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y
+CONFIG_PLATFORM_EC_MAX_SENSOR_FREQ_MILLIHZ=100000
+
+# LED
+CONFIG_PLATFORM_EC_LED_PWM=n
+CONFIG_PLATFORM_EC_LED_COMMON=y
diff --git a/zephyr/projects/nissa/nereid_pwm_leds.dts b/zephyr/projects/nissa/joxer/pwm_leds.dts
index 9a981b7071..aa4a76b271 100644
--- a/zephyr/projects/nissa/nereid_pwm_leds.dts
+++ b/zephyr/projects/nissa/joxer/pwm_leds.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,9 +7,9 @@
 	pwmleds {
 		compatible = "pwm-leds";
 		pwm_led0: pwm_led_0 {
-			pwms = <&pwm1 1 PWM_HZ(324) PWM_POLARITY_INVERTED>,
-			       <&pwm2 2 PWM_HZ(324) PWM_POLARITY_INVERTED>,
-			       <&pwm3 3 PWM_HZ(324) PWM_POLARITY_INVERTED>;
+			pwms = <&pwm1 1 PWM_HZ(1296) PWM_POLARITY_INVERTED>,
+			       <&pwm2 2 PWM_HZ(1296) PWM_POLARITY_INVERTED>,
+			       <&pwm3 3 PWM_HZ(1296) PWM_POLARITY_INVERTED>;
 		};
 	};
 
@@ -17,7 +17,6 @@
 		compatible = "cros-ec,pwm-leds";
 
 		leds = <&pwm_led0>;
-		frequency = <1296>;
 
 				/*<red green blue>*/
 		color-map-red    = <100   0    0>;
diff --git a/zephyr/projects/nissa/joxer/src/charger.c b/zephyr/projects/nissa/joxer/src/charger.c
new file mode 100644
index 0000000000..b9454d8b80
--- /dev/null
+++ b/zephyr/projects/nissa/joxer/src/charger.c
@@ -0,0 +1,56 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/logging/log.h>
+
+#include "battery.h"
+#include "charger.h"
+#include "console.h"
+#include "driver/charger/sm5803.h"
+#include "extpower.h"
+#include "usb_pd.h"
+#include "nissa_common.h"
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+int extpower_is_present(void)
+{
+	int port;
+	int rv;
+	bool acok;
+
+	for (port = 0; port < board_get_usb_pd_port_count(); port++) {
+		rv = sm5803_is_acok(port, &acok);
+		if ((rv == EC_SUCCESS) && acok)
+			return 1;
+	}
+
+	return 0;
+}
+
+/*
+ * Joxer not have a GPIO indicating whether extpower is present,
+ * so detect using the charger(s).
+ */
+__override void board_check_extpower(void)
+{
+	static int last_extpower_present;
+	int extpower_present = extpower_is_present();
+
+	if (last_extpower_present ^ extpower_present)
+		extpower_handle_update(extpower_present);
+
+	last_extpower_present = extpower_present;
+}
+
+__override void board_hibernate(void)
+{
+	/* Shut down the chargers */
+	if (board_get_usb_pd_port_count() == 2)
+		sm5803_hibernate(CHARGER_SECONDARY);
+	sm5803_hibernate(CHARGER_PRIMARY);
+	LOG_INF("Charger(s) hibernated");
+	cflush();
+}
diff --git a/zephyr/projects/nissa/joxer/src/fan.c b/zephyr/projects/nissa/joxer/src/fan.c
new file mode 100644
index 0000000000..6d234b2fc3
--- /dev/null
+++ b/zephyr/projects/nissa/joxer/src/fan.c
@@ -0,0 +1,43 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/logging/log.h>
+
+#include "cros_cbi.h"
+#include "fan.h"
+#include "gpio/gpio.h"
+#include "hooks.h"
+
+#include "nissa_common.h"
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+/*
+ * Joxer fan support
+ */
+static void fan_init(void)
+{
+	int ret;
+	uint32_t val;
+	/*
+	 * Retrieve the fan config.
+	 */
+	ret = cros_cbi_get_fw_config(FW_FAN, &val);
+	if (ret != 0) {
+		LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_FAN);
+		return;
+	}
+	if (val != FW_FAN_PRESENT) {
+		/* Disable the fan */
+		fan_set_count(0);
+	} else {
+		/* Configure the fan enable GPIO */
+		gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_fan_enable),
+				      GPIO_OUTPUT);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, fan_init, HOOK_PRIO_POST_FIRST);
diff --git a/zephyr/projects/nissa/joxer/src/keyboard.c b/zephyr/projects/nissa/joxer/src/keyboard.c
new file mode 100644
index 0000000000..48db40f53f
--- /dev/null
+++ b/zephyr/projects/nissa/joxer/src/keyboard.c
@@ -0,0 +1,68 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/logging/log.h>
+
+#include "cros_cbi.h"
+#include "ec_commands.h"
+#include "gpio/gpio.h"
+#include "hooks.h"
+#include "keyboard_8042_sharedlib.h"
+#include "nissa_common.h"
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+static const struct ec_response_keybd_config joxer_kb_legacy = {
+	.num_top_row_keys = 13,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_KBD_BKLIGHT_TOGGLE,	/* T8 */
+		TK_PLAY_PAUSE,		/* T9 */
+		TK_MICMUTE,		/* T10 */
+		TK_VOL_MUTE,		/* T11 */
+		TK_VOL_DOWN,		/* T12 */
+		TK_VOL_UP,		/* T13 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &joxer_kb_legacy;
+}
+
+/*
+ * Keyboard layout decided by FW config.
+ */
+static void kb_layout_init(void)
+{
+	int ret;
+	uint32_t val;
+	/*
+	 * Retrieve the kb layout config.
+	 */
+	ret = cros_cbi_get_fw_config(FW_KB_LAYOUT, &val);
+	if (ret != 0) {
+		LOG_ERR("Error retrieving CBI FW_CONFIG field %d",
+			FW_KB_LAYOUT);
+		return;
+	}
+	/*
+	 * If keyboard is US2(FW_KB_LAYOUT_US2), we need translate right ctrl
+	 * to backslash(\|) key.
+	 */
+	if (val == FW_KB_LAYOUT_US2)
+		set_scancode_set2(4, 0, get_scancode_set2(2, 7));
+}
+DECLARE_HOOK(HOOK_INIT, kb_layout_init, HOOK_PRIO_POST_FIRST);
diff --git a/zephyr/projects/nissa/joxer/src/led.c b/zephyr/projects/nissa/joxer/src/led.c
new file mode 100644
index 0000000000..d66e5b27a6
--- /dev/null
+++ b/zephyr/projects/nissa/joxer/src/led.c
@@ -0,0 +1,181 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery LED control for nissa
+ */
+#include <stdint.h>
+
+#include "charge_manager.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+#include "pwm.h"
+#include "util.h"
+
+#define BAT_LED_ON_LVL 0
+#define BAT_LED_OFF_LVL 1
+
+#define PWR_LED_ON_LVL 1
+#define PWR_LED_OFF_LVL 0
+
+#define LED_SIDESEL_MB_PORT 0
+#define LED_SIDESEL_DB_PORT 1
+
+__override const int led_charge_lvl_1 = 5;
+__override const int led_charge_lvl_2 = 95;
+
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    0.5 * LED_ONE_SEC },
+					  { LED_OFF, 0.5 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 1 * LED_ONE_SEC } },
+	};
+
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 1 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    1 * LED_ONE_SEC },
+						  { LED_OFF,
+						    1 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_BATTERY_LED,
+	EC_LED_ID_POWER_LED,
+};
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	int port;
+
+	/* There are four battery leds, LED1/LED2 are on MB side and
+	 * LED3/LED4 are on DB side. All leds are OFF by default.
+	 */
+	int led1, led2, led3, led4;
+
+	led1 = led2 = led3 = led4 = BAT_LED_OFF_LVL;
+
+	/* Check which port is the charging port,
+	 * and turn on the corresponding led.
+	 */
+	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) {
+		port = charge_manager_get_active_charge_port();
+		switch (port) {
+		case LED_SIDESEL_MB_PORT:
+			switch (color) {
+			case EC_LED_COLOR_AMBER:
+				led1 = BAT_LED_ON_LVL;
+				break;
+			case EC_LED_COLOR_WHITE:
+				led2 = BAT_LED_ON_LVL;
+				break;
+			default: /* LED_OFF and other unsupported colors */
+				break;
+			}
+			break;
+		case LED_SIDESEL_DB_PORT:
+			switch (color) {
+			case EC_LED_COLOR_AMBER:
+				led3 = BAT_LED_ON_LVL;
+				break;
+			case EC_LED_COLOR_WHITE:
+				led4 = BAT_LED_ON_LVL;
+				break;
+			default: /* LED_OFF and other unsupported colors */
+				break;
+			}
+			break;
+		default: /* Unknown charging port */
+			break;
+		}
+	} else {
+		switch (color) {
+		case EC_LED_COLOR_AMBER:
+			led1 = BAT_LED_ON_LVL;
+			led3 = BAT_LED_ON_LVL;
+			break;
+		case EC_LED_COLOR_WHITE:
+			led2 = BAT_LED_ON_LVL;
+			led4 = BAT_LED_ON_LVL;
+			break;
+		default: /* LED_OFF and other unsupported colors */
+			break;
+		}
+	}
+
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_led_1_odl), led1);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_led_2_odl), led2);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_led_3_l), led3);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_led_4_l), led4);
+}
+
+__override void led_set_color_power(enum ec_led_colors color)
+{
+	if (color == EC_LED_COLOR_WHITE)
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_power_led_gate),
+				PWR_LED_ON_LVL);
+	else
+		/* LED_OFF and unsupported colors */
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_power_led_gate),
+				PWR_LED_OFF_LVL);
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		led_auto_control(led_id, 0);
+		if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(EC_LED_COLOR_AMBER);
+		else if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_battery(EC_LED_COLOR_WHITE);
+		else if (brightness[LED_OFF] != 0)
+			led_set_color_battery(LED_OFF);
+		else {
+			led_auto_control(led_id, 1);
+			led_set_color_battery(LED_OFF);
+		}
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_power(EC_LED_COLOR_WHITE);
+		else
+			led_set_color_power(LED_OFF);
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/zephyr/projects/nissa/src/nereid/usbc.c b/zephyr/projects/nissa/joxer/src/usbc.c
index eeab449c32..5fec9ab544 100644
--- a/zephyr/projects/nissa/src/nereid/usbc.c
+++ b/zephyr/projects/nissa/joxer/src/usbc.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -63,19 +63,7 @@ void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
 
 __override bool pd_check_vbus_level(int port, enum vbus_level level)
 {
-	int vbus_voltage;
-
-	/* If we're unable to speak to the charger, best to guess false */
-	if (charger_get_vbus_voltage(port, &vbus_voltage)) {
-		return false;
-	}
-
-	if (level == VBUS_SAFE0V)
-		return vbus_voltage < PD_V_SAFE0V_MAX;
-	else if (level == VBUS_PRESENT)
-		return vbus_voltage > PD_V_SAFE5V_MIN;
-	else
-		return vbus_voltage < PD_V_SINK_DISCONNECT_MAX;
+	return sm5803_check_vbus_level(port, level);
 }
 
 /*
@@ -103,8 +91,8 @@ static void board_chargers_suspend(struct ap_power_ev_callback *const cb,
 		fn = sm5803_disable_low_power_mode;
 		break;
 	default:
-		LOG_WRN("%s: power event %d is not recognized",
-			__func__, data.event);
+		LOG_WRN("%s: power event %d is not recognized", __func__,
+			data.event);
 		return;
 	}
 
@@ -157,7 +145,7 @@ int board_set_active_charge_port(int port)
 	}
 
 	/* Don't enable anything (stop here) if no ports were requested */
-	if (port == CHARGE_PORT_NONE)
+	if ((port == CHARGE_PORT_NONE) || (old_port == port))
 		return EC_SUCCESS;
 
 	/*
@@ -281,7 +269,7 @@ void board_reset_pd_mcu(void)
 	 */
 }
 
-#define INT_RECHECK_US	5000
+#define INT_RECHECK_US 5000
 
 /* C0 interrupt line shared by BC 1.2 and charger */
 
diff --git a/zephyr/projects/nissa/nereid_generated.dts b/zephyr/projects/nissa/nereid/generated.dts
index a588937f3c..bca58c478e 100644
--- a/zephyr/projects/nissa/nereid_generated.dts
+++ b/zephyr/projects/nissa/nereid/generated.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,27 +11,22 @@
 		compatible = "named-adc-channels";
 
 		adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc {
-			label = "EC_VSENSE_PP1050_PROC";
 			enum-name = "ADC_PP1050_PROC";
 			io-channels = <&adc0 14>;
 		};
 		adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 {
-			label = "EC_VSENSE_PP3300_S5";
 			enum-name = "ADC_PP3300_S5";
 			io-channels = <&adc0 0>;
 		};
 		adc_temp_sensor_1: temp_sensor_1 {
-			label = "TEMP_SENSOR_1";
 			enum-name = "ADC_TEMP_SENSOR_1";
 			io-channels = <&adc0 2>;
 		};
 		adc_temp_sensor_2: temp_sensor_2 {
-			label = "TEMP_SENSOR_2";
 			enum-name = "ADC_TEMP_SENSOR_2";
 			io-channels = <&adc0 3>;
 		};
 		adc_temp_sensor_3: temp_sensor_3 {
-			label = "TEMP_SENSOR_3";
 			enum-name = "ADC_TEMP_SENSOR_3";
 			io-channels = <&adc0 13>;
 		};
@@ -219,23 +214,23 @@
 
 		i2c_ec_i2c_eeprom: ec_i2c_eeprom {
 			i2c-port = <&i2c0>;
-			enum-name = "I2C_PORT_EEPROM";
+			enum-names = "I2C_PORT_EEPROM";
 		};
 		i2c_ec_i2c_batt: ec_i2c_batt {
 			i2c-port = <&i2c1>;
-			enum-name = "I2C_PORT_BATTERY";
+			enum-names = "I2C_PORT_BATTERY";
 		};
 		i2c_ec_i2c_sensor: ec_i2c_sensor {
 			i2c-port = <&i2c2>;
-			enum-name = "I2C_PORT_SENSOR";
+			enum-names = "I2C_PORT_SENSOR";
 		};
 		i2c_ec_i2c_sub_usb_c1: ec_i2c_sub_usb_c1 {
 			i2c-port = <&i2c4>;
-			enum-name = "I2C_PORT_USB_C1_TCPC";
+			enum-names = "I2C_PORT_USB_C1_TCPC";
 		};
 		i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 {
 			i2c-port = <&i2c5>;
-			enum-name = "I2C_PORT_USB_C0_TCPC";
+			enum-names = "I2C_PORT_USB_C0_TCPC";
 		};
 	};
 };
diff --git a/zephyr/projects/nissa/nereid/keyboard.dts b/zephyr/projects/nissa/nereid/keyboard.dts
new file mode 100644
index 0000000000..04a620767a
--- /dev/null
+++ b/zephyr/projects/nissa/nereid/keyboard.dts
@@ -0,0 +1,22 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	kblight {
+		compatible = "cros-ec,kblight-pwm";
+		/*
+		 * Use 324 Hz so that 32Khz clock source is used,
+		 * which is not gated in power saving mode.
+		 */
+		pwms = <&pwm0 0 PWM_HZ(324) PWM_POLARITY_NORMAL>;
+	};
+};
+
+&pwm0 {
+	status = "okay";
+	prescaler-cx = <PWM_PRESCALER_C4>;
+	pinctrl-0 = <&pwm0_gpa0_default>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/projects/nissa/nereid_motionsense.dts b/zephyr/projects/nissa/nereid/motionsense.dts
index 596b3eb148..3a560d512a 100644
--- a/zephyr/projects/nissa/nereid_motionsense.dts
+++ b/zephyr/projects/nissa/nereid/motionsense.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,11 +24,9 @@
 	motionsense-mutex {
 		compatible = "cros-ec,motionsense-mutex";
 		lid_mutex: lid-mutex {
-			label = "LID_MUTEX";
 		};
 
 		base_mutex: base-mutex {
-			label = "BASE_MUTEX";
 		};
 	};
 
@@ -71,9 +69,9 @@
 
 	/*
 	 * List of motion sensors that creates motion_sensors array.
-	 * The label "lid_accel" and "base_accel" are used to indicate
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
 	 * motion sensor IDs for lid angle calculation.
-	 * TODO:(b/229577857) The first entries of the array must be
+	 * TODO(b/238139272): The first entries of the array must be
 	 * accelerometers,then gyroscope. Fix this dependency in the DTS
 	 * processing which makes the devicetree entries independent.
 	 */
@@ -82,7 +80,6 @@
 			compatible = "cros-ec,bma4xx";
 			status = "okay";
 
-			label = "Lid Accel";
 			active-mask = "SENSOR_ACTIVE_S0_S3";
 			location = "MOTIONSENSE_LOC_LID";
 			mutex = <&lid_mutex>;
@@ -94,11 +91,9 @@
 				compatible =
 					"cros-ec,motionsense-sensor-config";
 				ec-s0 {
-					label = "SENSOR_CONFIG_EC_S0";
 					odr = <(10000 | ROUND_UP_FLAG)>;
 				};
 				ec-s3 {
-					label = "SENSOR_CONFIG_EC_S3";
 					odr = <(10000 | ROUND_UP_FLAG)>;
 				};
 			};
@@ -108,7 +103,6 @@
 			compatible = "cros-ec,bmi3xx-accel";
 			status = "okay";
 
-			label = "Base Accel";
 			active-mask = "SENSOR_ACTIVE_S0_S3";
 			location = "MOTIONSENSE_LOC_BASE";
 			mutex = <&base_mutex>;
@@ -119,11 +113,9 @@
 				compatible =
 					"cros-ec,motionsense-sensor-config";
 				ec-s0 {
-					label = "SENSOR_CONFIG_EC_S0";
 					odr = <(10000 | ROUND_UP_FLAG)>;
 				};
 				ec-s3 {
-					label = "SENSOR_CONFIG_EC_S3";
 					odr = <(10000 | ROUND_UP_FLAG)>;
 				};
 			};
@@ -133,7 +125,6 @@
 			compatible = "cros-ec,bmi3xx-gyro";
 			status = "okay";
 
-			label = "Base Gyro";
 			active-mask = "SENSOR_ACTIVE_S0_S3";
 			location = "MOTIONSENSE_LOC_BASE";
 			mutex = <&base_mutex>;
diff --git a/zephyr/projects/nissa/nereid/nereid_vif.xml b/zephyr/projects/nissa/nereid/nereid_vif.xml
new file mode 100644
index 0000000000..5cdbac739d
--- /dev/null
+++ b/zephyr/projects/nissa/nereid/nereid_vif.xml
@@ -0,0 +1,350 @@
+<?xml version="1.0" encoding="utf-8"?>

+<vif:VIF xmlns:opt="http://usb.org/VendorInfoFileOptionalContent.xsd" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:vif="http://usb.org/VendorInfoFile.xsd">

+  <vif:VIF_Specification>3.19</vif:VIF_Specification>

+  <vif:VIF_App>

+    <vif:Vendor>USB-IF</vif:Vendor>

+    <vif:Name>VIF Editor</vif:Name>

+    <vif:Version>3.2.4.0</vif:Version>

+  </vif:VIF_App>

+  <vif:Vendor_Name>Google</vif:Vendor_Name>

+  <vif:Model_Part_Number>Nereid</vif:Model_Part_Number>

+  <vif:Product_Revision>1</vif:Product_Revision>

+  <vif:TID>0</vif:TID>

+  <vif:VIF_Product_Type value="0">Port Product</vif:VIF_Product_Type>

+  <vif:Certification_Type value="1">Reference Platform</vif:Certification_Type>

+  <vif:Product>

+    <!--Product Level Content:-->

+  </vif:Product>

+  <vif:Component>

+    <!--Component 0: Port 0-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;Component-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:Port_Label>0</vif:Port_Label>

+    <vif:Connector_Type value="2">Type-C®</vif:Connector_Type>

+    <vif:USB4_Supported value="false" />

+    <vif:USB_PD_Support value="true" />

+    <vif:PD_Port_Type value="4">DRP</vif:PD_Port_Type>

+    <vif:Type_C_State_Machine value="2">DRP</vif:Type_C_State_Machine>

+    <vif:Port_Battery_Powered value="true" />

+    <vif:BC_1_2_Support value="2">Charging Port</vif:BC_1_2_Support>

+    <vif:Captive_Cable value="false" />

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;General PD-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:PD_Spec_Revision_Major value="3" />

+    <vif:PD_Spec_Revision_Minor value="1" />

+    <vif:PD_Spec_Version_Major value="1" />

+    <vif:PD_Spec_Version_Minor value="3" />

+    <vif:PD_Specification_Revision value="2">Revision 3</vif:PD_Specification_Revision>

+    <vif:SOP_Capable value="true" />

+    <vif:SOP_P_Capable value="true" />

+    <vif:SOP_PP_Capable value="true" />

+    <vif:SOP_P_Debug_Capable value="false" />

+    <vif:SOP_PP_Debug_Capable value="false" />

+    <vif:Manufacturer_Info_Supported_Port value="true" />

+    <vif:Manufacturer_Info_VID_Port value="6353">18D1</vif:Manufacturer_Info_VID_Port>

+    <vif:Manufacturer_Info_PID_Port value="20570">505A</vif:Manufacturer_Info_PID_Port>

+    <vif:Chunking_Implemented_SOP value="true" />

+    <vif:Unchunked_Extended_Messages_Supported value="false" />

+    <vif:Security_Msgs_Supported_SOP value="false" />

+    <vif:Unconstrained_Power value="false" />

+    <vif:Num_Fixed_Batteries value="1" />

+    <vif:Num_Swappable_Battery_Slots value="0" />

+    <vif:ID_Header_Connector_Type_SOP value="2">USB Type-C® Receptacle</vif:ID_Header_Connector_Type_SOP>

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;PD Capabilities-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:USB_Comms_Capable value="true" />

+    <vif:DR_Swap_To_DFP_Supported value="true" />

+    <vif:DR_Swap_To_UFP_Supported value="false" />

+    <vif:VCONN_Swap_To_On_Supported value="true" />

+    <vif:VCONN_Swap_To_Off_Supported value="true" />

+    <vif:Responds_To_Discov_SOP_UFP value="false" />

+    <vif:Responds_To_Discov_SOP_DFP value="true" />

+    <vif:Attempts_Discov_SOP value="true" />

+    <vif:Power_Interruption_Available value="0">No Interruption Possible</vif:Power_Interruption_Available>

+    <vif:Data_Reset_Supported value="false" />

+    <vif:Enter_USB_Supported value="false" />

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;USB Type-C®-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:Type_C_Can_Act_As_Host value="true" />

+    <vif:Type_C_Can_Act_As_Device value="false" />

+    <vif:Type_C_Implements_Try_SRC value="true" />

+    <vif:Type_C_Implements_Try_SNK value="false" />

+    <vif:Type_C_Supports_Audio_Accessory value="false" />

+    <vif:Type_C_Is_VCONN_Powered_Accessory value="false" />

+    <vif:Type_C_Is_Debug_Target_SRC value="true" />

+    <vif:Type_C_Is_Debug_Target_SNK value="true" />

+    <vif:RP_Value value="1">1.5A</vif:RP_Value>

+    <vif:Type_C_Port_On_Hub value="false" />

+    <vif:Type_C_Power_Source value="2">Both</vif:Type_C_Power_Source>

+    <vif:Type_C_Sources_VCONN value="true" />

+    <vif:Type_C_Is_Alt_Mode_Controller value="true" />

+    <vif:Type_C_Is_Alt_Mode_Adapter value="false" />

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;Product Power-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:Product_Total_Source_Power_mW value="15000">15000 mW</vif:Product_Total_Source_Power_mW>

+    <vif:Port_Source_Power_Type value="0">Assured</vif:Port_Source_Power_Type>

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;USB Host-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:Host_Supports_USB_Data value="true" />

+    <vif:Host_Speed value="1">USB 3.2 Gen 1x1</vif:Host_Speed>

+    <vif:Host_Contains_Captive_Retimer value="false" />

+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />

+    <vif:Host_Is_Embedded value="false" />

+    <vif:Host_Suspend_Supported value="true" />

+    <vif:Is_DFP_On_Hub value="false" />

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;Battery Charging 1.2-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:BC_1_2_Charging_Port_Type value="1">CDP</vif:BC_1_2_Charging_Port_Type>

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;PD Source-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:PD_Power_As_Source value="15000">15000 mW</vif:PD_Power_As_Source>

+    <vif:EPR_Supported_As_Src value="false" />

+    <vif:USB_Suspend_May_Be_Cleared value="false" />

+    <vif:Sends_Pings value="false" />

+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="0">FR_Swap not supported</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>

+    <vif:Master_Port value="false" />

+    <vif:Num_Src_PDOs value="1" />

+    <vif:PD_OC_Protection value="true" />

+    <vif:PD_OCP_Method value="0">Over-Current Response</vif:PD_OCP_Method>

+    <!--Bundle: SrcPdoList-->

+    <vif:SrcPdoList>

+      <vif:SrcPDO>

+        <!--Source PDO 1-->

+        <vif:Src_PDO_Supply_Type value="0">Fixed</vif:Src_PDO_Supply_Type>

+        <vif:Src_PDO_Peak_Current value="0">100% IOC</vif:Src_PDO_Peak_Current>

+        <vif:Src_PDO_Voltage value="100">5000 mV</vif:Src_PDO_Voltage>

+        <vif:Src_PDO_Max_Current value="300">3000 mA</vif:Src_PDO_Max_Current>

+        <vif:Src_PD_OCP_OC_Debounce value="0">0 msec</vif:Src_PD_OCP_OC_Debounce>

+        <vif:Src_PD_OCP_OC_Threshold value="300">3000 mA</vif:Src_PD_OCP_OC_Threshold>

+      </vif:SrcPDO>

+    </vif:SrcPdoList>

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;PD Sink-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:PD_Power_As_Sink value="45000">45000 mW</vif:PD_Power_As_Sink>

+    <vif:EPR_Supported_As_Snk value="false" />

+    <vif:No_USB_Suspend_May_Be_Set value="true" />

+    <vif:GiveBack_May_Be_Set value="false" />

+    <vif:Higher_Capability_Set value="false" />

+    <vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source value="0">FR_Swap not supported</vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source>

+    <vif:Num_Snk_PDOs value="3" />

+    <!--Bundle: SnkPdoList-->

+    <vif:SnkPdoList>

+      <vif:SnkPDO>

+        <!--Sink PDO 1-->

+        <vif:Snk_PDO_Supply_Type value="0">Fixed</vif:Snk_PDO_Supply_Type>

+        <vif:Snk_PDO_Voltage value="100">5000 mV</vif:Snk_PDO_Voltage>

+        <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>

+      </vif:SnkPDO>

+      <vif:SnkPDO>

+        <!--Sink PDO 2-->

+        <vif:Snk_PDO_Supply_Type value="1">Battery</vif:Snk_PDO_Supply_Type>

+        <vif:Snk_PDO_Op_Power value="60">15000 mW</vif:Snk_PDO_Op_Power>

+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>

+        <vif:Snk_PDO_Max_Voltage value="300">15000 mV</vif:Snk_PDO_Max_Voltage>

+      </vif:SnkPDO>

+      <vif:SnkPDO>

+        <!--Sink PDO 3-->

+        <vif:Snk_PDO_Supply_Type value="2">Variable</vif:Snk_PDO_Supply_Type>

+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>

+        <vif:Snk_PDO_Max_Voltage value="300">15000 mV</vif:Snk_PDO_Max_Voltage>

+        <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>

+      </vif:SnkPDO>

+    </vif:SnkPdoList>

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;Dual Role-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:Accepts_PR_Swap_As_Src value="true" />

+    <vif:Accepts_PR_Swap_As_Snk value="true" />

+    <vif:Requests_PR_Swap_As_Src value="true" />

+    <vif:Requests_PR_Swap_As_Snk value="true" />

+    <vif:FR_Swap_Supported_As_Initial_Sink value="false" />

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;SOP Discover ID-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:XID_SOP value="0" />

+    <vif:Data_Capable_As_USB_Host_SOP value="true" />

+    <vif:Data_Capable_As_USB_Device_SOP value="false" />

+    <vif:Product_Type_UFP_SOP value="0">Undefined</vif:Product_Type_UFP_SOP>

+    <vif:Product_Type_DFP_SOP value="0">Undefined</vif:Product_Type_DFP_SOP>

+    <vif:DFP_VDO_Port_Number value="0" />

+    <vif:Modal_Operation_Supported_SOP value="false" />

+    <vif:USB_VID_SOP value="6353">18D1</vif:USB_VID_SOP>

+    <vif:PID_SOP value="20570">505A</vif:PID_SOP>

+    <vif:bcdDevice_SOP value="0">0000</vif:bcdDevice_SOP>

+  </vif:Component>

+  <vif:Component>

+    <!--Component 1: Port 1-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;Component-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:Port_Label>1</vif:Port_Label>

+    <vif:Connector_Type value="2">Type-C®</vif:Connector_Type>

+    <vif:USB4_Supported value="false" />

+    <vif:USB_PD_Support value="true" />

+    <vif:PD_Port_Type value="4">DRP</vif:PD_Port_Type>

+    <vif:Type_C_State_Machine value="2">DRP</vif:Type_C_State_Machine>

+    <vif:Port_Battery_Powered value="true" />

+    <vif:BC_1_2_Support value="2">Charging Port</vif:BC_1_2_Support>

+    <vif:Captive_Cable value="false" />

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;General PD-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:PD_Spec_Revision_Major value="3" />

+    <vif:PD_Spec_Revision_Minor value="1" />

+    <vif:PD_Spec_Version_Major value="1" />

+    <vif:PD_Spec_Version_Minor value="3" />

+    <vif:PD_Specification_Revision value="2">Revision 3</vif:PD_Specification_Revision>

+    <vif:SOP_Capable value="true" />

+    <vif:SOP_P_Capable value="true" />

+    <vif:SOP_PP_Capable value="true" />

+    <vif:SOP_P_Debug_Capable value="false" />

+    <vif:SOP_PP_Debug_Capable value="false" />

+    <vif:Manufacturer_Info_Supported_Port value="true" />

+    <vif:Manufacturer_Info_VID_Port value="6353">18D1</vif:Manufacturer_Info_VID_Port>

+    <vif:Manufacturer_Info_PID_Port value="20570">505A</vif:Manufacturer_Info_PID_Port>

+    <vif:Chunking_Implemented_SOP value="true" />

+    <vif:Unchunked_Extended_Messages_Supported value="false" />

+    <vif:Security_Msgs_Supported_SOP value="false" />

+    <vif:Unconstrained_Power value="false" />

+    <vif:Num_Fixed_Batteries value="1" />

+    <vif:Num_Swappable_Battery_Slots value="0" />

+    <vif:ID_Header_Connector_Type_SOP value="2">USB Type-C® Receptacle</vif:ID_Header_Connector_Type_SOP>

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;PD Capabilities-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:USB_Comms_Capable value="true" />

+    <vif:DR_Swap_To_DFP_Supported value="true" />

+    <vif:DR_Swap_To_UFP_Supported value="false" />

+    <vif:VCONN_Swap_To_On_Supported value="true" />

+    <vif:VCONN_Swap_To_Off_Supported value="true" />

+    <vif:Responds_To_Discov_SOP_UFP value="false" />

+    <vif:Responds_To_Discov_SOP_DFP value="true" />

+    <vif:Attempts_Discov_SOP value="true" />

+    <vif:Power_Interruption_Available value="0">No Interruption Possible</vif:Power_Interruption_Available>

+    <vif:Data_Reset_Supported value="false" />

+    <vif:Enter_USB_Supported value="false" />

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;USB Type-C®-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:Type_C_Can_Act_As_Host value="true" />

+    <vif:Type_C_Can_Act_As_Device value="false" />

+    <vif:Type_C_Implements_Try_SRC value="true" />

+    <vif:Type_C_Implements_Try_SNK value="false" />

+    <vif:Type_C_Supports_Audio_Accessory value="false" />

+    <vif:Type_C_Is_VCONN_Powered_Accessory value="false" />

+    <vif:Type_C_Is_Debug_Target_SRC value="true" />

+    <vif:Type_C_Is_Debug_Target_SNK value="true" />

+    <vif:RP_Value value="1">1.5A</vif:RP_Value>

+    <vif:Type_C_Port_On_Hub value="false" />

+    <vif:Type_C_Power_Source value="2">Both</vif:Type_C_Power_Source>

+    <vif:Type_C_Sources_VCONN value="true" />

+    <vif:Type_C_Is_Alt_Mode_Controller value="true" />

+    <vif:Type_C_Is_Alt_Mode_Adapter value="false" />

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;Product Power-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:Product_Total_Source_Power_mW value="15000">15000 mW</vif:Product_Total_Source_Power_mW>

+    <vif:Port_Source_Power_Type value="0">Assured</vif:Port_Source_Power_Type>

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;USB Host-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:Host_Supports_USB_Data value="true" />

+    <vif:Host_Speed value="1">USB 3.2 Gen 1x1</vif:Host_Speed>

+    <vif:Host_Contains_Captive_Retimer value="true" />

+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />

+    <vif:Host_Is_Embedded value="false" />

+    <vif:Host_Suspend_Supported value="true" />

+    <vif:Is_DFP_On_Hub value="false" />

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;Battery Charging 1.2-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:BC_1_2_Charging_Port_Type value="1">CDP</vif:BC_1_2_Charging_Port_Type>

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;PD Source-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:PD_Power_As_Source value="15000">15000 mW</vif:PD_Power_As_Source>

+    <vif:EPR_Supported_As_Src value="false" />

+    <vif:USB_Suspend_May_Be_Cleared value="false" />

+    <vif:Sends_Pings value="false" />

+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="0">FR_Swap not supported</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>

+    <vif:Master_Port value="false" />

+    <vif:Num_Src_PDOs value="1" />

+    <vif:PD_OC_Protection value="true" />

+    <vif:PD_OCP_Method value="0">Over-Current Response</vif:PD_OCP_Method>

+    <!--Bundle: SrcPdoList-->

+    <vif:SrcPdoList>

+      <vif:SrcPDO>

+        <!--Source PDO 1-->

+        <vif:Src_PDO_Supply_Type value="0">Fixed</vif:Src_PDO_Supply_Type>

+        <vif:Src_PDO_Peak_Current value="0">100% IOC</vif:Src_PDO_Peak_Current>

+        <vif:Src_PDO_Voltage value="100">5000 mV</vif:Src_PDO_Voltage>

+        <vif:Src_PDO_Max_Current value="300">3000 mA</vif:Src_PDO_Max_Current>

+        <vif:Src_PD_OCP_OC_Debounce value="0">0 msec</vif:Src_PD_OCP_OC_Debounce>

+        <vif:Src_PD_OCP_OC_Threshold value="300">3000 mA</vif:Src_PD_OCP_OC_Threshold>

+      </vif:SrcPDO>

+    </vif:SrcPdoList>

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;PD Sink-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:PD_Power_As_Sink value="45000">45000 mW</vif:PD_Power_As_Sink>

+    <vif:EPR_Supported_As_Snk value="false" />

+    <vif:No_USB_Suspend_May_Be_Set value="true" />

+    <vif:GiveBack_May_Be_Set value="false" />

+    <vif:Higher_Capability_Set value="false" />

+    <vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source value="0">FR_Swap not supported</vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source>

+    <vif:Num_Snk_PDOs value="3" />

+    <!--Bundle: SnkPdoList-->

+    <vif:SnkPdoList>

+      <vif:SnkPDO>

+        <!--Sink PDO 1-->

+        <vif:Snk_PDO_Supply_Type value="0">Fixed</vif:Snk_PDO_Supply_Type>

+        <vif:Snk_PDO_Voltage value="100">5000 mV</vif:Snk_PDO_Voltage>

+        <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>

+      </vif:SnkPDO>

+      <vif:SnkPDO>

+        <!--Sink PDO 2-->

+        <vif:Snk_PDO_Supply_Type value="1">Battery</vif:Snk_PDO_Supply_Type>

+        <vif:Snk_PDO_Op_Power value="60">15000 mW</vif:Snk_PDO_Op_Power>

+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>

+        <vif:Snk_PDO_Max_Voltage value="300">15000 mV</vif:Snk_PDO_Max_Voltage>

+      </vif:SnkPDO>

+      <vif:SnkPDO>

+        <!--Sink PDO 3-->

+        <vif:Snk_PDO_Supply_Type value="2">Variable</vif:Snk_PDO_Supply_Type>

+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>

+        <vif:Snk_PDO_Max_Voltage value="300">15000 mV</vif:Snk_PDO_Max_Voltage>

+        <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>

+      </vif:SnkPDO>

+    </vif:SnkPdoList>

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;Dual Role-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:Accepts_PR_Swap_As_Src value="true" />

+    <vif:Accepts_PR_Swap_As_Snk value="true" />

+    <vif:Requests_PR_Swap_As_Src value="true" />

+    <vif:Requests_PR_Swap_As_Snk value="true" />

+    <vif:FR_Swap_Supported_As_Initial_Sink value="false" />

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;SOP Discover ID-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:XID_SOP value="0" />

+    <vif:Data_Capable_As_USB_Host_SOP value="true" />

+    <vif:Data_Capable_As_USB_Device_SOP value="false" />

+    <vif:Product_Type_UFP_SOP value="0">Undefined</vif:Product_Type_UFP_SOP>

+    <vif:Product_Type_DFP_SOP value="0">Undefined</vif:Product_Type_DFP_SOP>

+    <vif:DFP_VDO_Port_Number value="1" />

+    <vif:Modal_Operation_Supported_SOP value="false" />

+    <vif:USB_VID_SOP value="6353">18D1</vif:USB_VID_SOP>

+    <vif:PID_SOP value="20570">505A</vif:PID_SOP>

+    <vif:bcdDevice_SOP value="0">0000</vif:bcdDevice_SOP>

+  </vif:Component>

+</vif:VIF>
\ No newline at end of file
diff --git a/zephyr/projects/nissa/nereid_overlay.dts b/zephyr/projects/nissa/nereid/overlay.dts
index 158629b1e9..76f6b197be 100644
--- a/zephyr/projects/nissa/nereid_overlay.dts
+++ b/zephyr/projects/nissa/nereid/overlay.dts
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -143,45 +143,50 @@
 		gpio-en-sub-s5-rails = &gpio_sb_2;
 	};
 
+	temp_memory: memory {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_1>;
+	};
+	temp_charger: charger {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_2>;
+	};
+	temp_ambient: ambient {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_3>;
+	};
+
 	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
 		memory {
-			compatible = "cros-ec,temp-sensor-thermistor",
-				     "cros-ec,temp-sensor";
-			thermistor = <&thermistor_3V3_51K1_47K_4050B>;
-			label = "DDR and SOC";
-			enum-name = "TEMP_SENSOR_1";
 			temp_fan_off = <35>;
 			temp_fan_max = <60>;
 			temp_host_high = <85>;
 			temp_host_halt = <90>;
 			temp_host_release_high = <80>;
-			adc = <&adc_temp_sensor_1>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_memory>;
 		};
 		charger {
-			compatible = "cros-ec,temp-sensor-thermistor",
-				     "cros-ec,temp-sensor";
-			thermistor = <&thermistor_3V3_51K1_47K_4050B>;
-			label = "Charger";
-			enum-name = "TEMP_SENSOR_CHARGER";
 			temp_fan_off = <35>;
 			temp_fan_max = <60>;
 			temp_host_high = <85>;
 			temp_host_halt = <90>;
 			temp_host_release_high = <80>;
-			adc = <&adc_temp_sensor_2>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_charger>;
 		};
 		ambient {
-			compatible = "cros-ec,temp-sensor-thermistor",
-				     "cros-ec,temp-sensor";
-			thermistor = <&thermistor_3V3_51K1_47K_4050B>;
-			label = "Ambient";
-			enum-name = "TEMP_SENSOR_AMB";
 			temp_fan_off = <35>;
 			temp_fan_max = <60>;
 			temp_host_high = <85>;
 			temp_host_halt = <90>;
 			temp_host_release_high = <80>;
-			adc = <&adc_temp_sensor_3>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_ambient>;
 		};
 	};
 
@@ -207,16 +212,12 @@
 		port0@0 {
 			compatible = "named-usbc-port";
 			reg = <0>;
-			bc12 {
-				compatible = "pericom,pi3usb9201";
-				port = <&i2c_ec_i2c_usb_c0>;
-			};
-			chg {
-				compatible = "siliconmitus,sm5803";
-				status = "okay";
-				port = <&i2c_ec_i2c_usb_c0>;
+			bc12 = <&bc12_port0>;
+			chg = <&chg_port0>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_0>;
 			};
-			usb-muxes = <&virtual_mux_0>;
 		};
 		port0-muxes {
 			virtual_mux_0: virtual-mux-0 {
@@ -226,20 +227,17 @@
 		port1@1 {
 			compatible = "named-usbc-port";
 			reg = <1>;
-			bc12 {
-				compatible = "pericom,pi3usb9201";
-				port = <&i2c_ec_i2c_sub_usb_c1>;
+			bc12 = <&bc12_port1>;
+			chg = <&chg_port1>;
+			usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_1 &tcpci_mux_1>;
 			};
-			chg {
-				compatible = "siliconmitus,sm5803";
-				status = "okay";
-				port = <&i2c_ec_i2c_sub_usb_c1>;
+			usb_mux_chain_1_no_mux: usb-mux-chain-1-no-mux {
+				compatible = "cros-ec,usb-mux-chain";
+				alternative-chain;
+				usb-muxes = <&virtual_mux_1>;
 			};
-			/*
-			 * Some sub-boards may disable all usb muxes in chain
-			 * except virtual_mux_1
-			 */
-			usb-muxes = <&virtual_mux_1 &tcpci_mux_1>;
 		};
 		port1-muxes {
 			virtual_mux_1: virtual-mux-1 {
@@ -252,6 +250,23 @@
 	};
 };
 
+&gpio_acc_int_l {
+	gpios = <&gpioc 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+};
+&gpio_imu_int_l {
+	gpios = <&gpioj 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+};
+&gpio_vccin_aux_vid0 {
+	gpios = <&gpiod 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+};
+&gpio_vccin_aux_vid1 {
+	gpios = <&gpiok 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+};
+
+&gpio_ec_prochot_odl {
+	gpios = <&gpioi 1 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>;
+};
+
 &thermistor_3V3_51K1_47K_4050B {
 	status = "okay";
 };
@@ -277,6 +292,21 @@
 	pinctrl-names = "default";
 };
 
+&pinctrl {
+	i2c4_clk_gpe0_sleep: i2c4_clk_gpe0_sleep {
+		pinmuxs = <&pinctrle 0 IT8XXX2_ALT_DEFAULT>;
+	};
+	i2c4_data_gpe7_sleep: i2c4_data_gpe7_sleep {
+		pinmuxs = <&pinctrle 7 IT8XXX2_ALT_DEFAULT>;
+	};
+	i2c2_clk_gpf6_default: i2c2_clk_gpf6_default {
+		gpio-voltage = "1v8";
+	};
+	i2c2_data_gpf7_default: i2c2_data_gpf7_default {
+		gpio-voltage = "1v8";
+	};
+};
+
 &i2c0 {
 	label = "I2C_EEPROM";
 	clock-frequency = <I2C_BITRATE_FAST>;
@@ -284,7 +314,6 @@
 	cbi_eeprom: eeprom@50 {
 		compatible = "atmel,at24";
 		reg = <0x50>;
-		label = "EEPROM_CBI";
 		size = <2048>;
 		pagesize = <16>;
 		address-width = <8>;
@@ -297,7 +326,7 @@
 
 &i2c1 {
 	label = "I2C_BATTERY";
-	clock-frequency = <I2C_BITRATE_STANDARD>;
+	clock-frequency = <50000>;
 	pinctrl-0 = <&i2c1_clk_gpc1_default
 		     &i2c1_data_gpc2_default>;
 	pinctrl-names = "default";
@@ -316,7 +345,31 @@
 	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
 	pinctrl-0 = <&i2c4_clk_gpe0_default
 		     &i2c4_data_gpe7_default>;
-	pinctrl-names = "default";
+	pinctrl-1 = <&i2c4_clk_gpe0_sleep
+		     &i2c4_data_gpe7_sleep>;
+	pinctrl-names = "default", "sleep";
+
+	bc12_port1: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+	};
+
+	chg_port1: sm5803@32 {
+		compatible = "siliconmitus,sm5803";
+		status = "okay";
+		reg = <0x32>;
+	};
+};
+
+&i2c_ec_i2c_sub_usb_c1 {
+	/*
+	 * Dynamic speed setting is used for AP-controlled firmware update
+	 * of PS8745 TCPC/redriver: the AP lowers speed to 400 kHz in order
+	 * to use more efficient window programming, then sets it back when
+	 * done.
+	 */
+	dynamic-speed;
 };
 
 &i2c5 {
@@ -325,4 +378,20 @@
 	pinctrl-0 = <&i2c5_clk_gpa4_default
 		     &i2c5_data_gpa5_default>;
 	pinctrl-names = "default";
+
+	bc12_port0: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+	};
+
+	chg_port0: sm5803@32 {
+		compatible = "siliconmitus,sm5803";
+		status = "okay";
+		reg = <0x32>;
+	};
+};
+
+&usbpd0 {
+	status = "okay";
 };
diff --git a/zephyr/projects/nissa/nereid/power_signals.dts b/zephyr/projects/nissa/nereid/power_signals.dts
new file mode 100644
index 0000000000..8affae03b1
--- /dev/null
+++ b/zephyr/projects/nissa/nereid/power_signals.dts
@@ -0,0 +1,223 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	chosen {
+		intel-ap-pwrseq,espi = &espi0;
+	};
+
+	common-pwrseq {
+		compatible = "intel,ap-pwrseq";
+
+		sys-pwrok-delay = <10>;
+		all-sys-pwrgd-timeout = <20>;
+	};
+
+	pwr-en-pp5000-s5 {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PP5000_S5 enable output to regulator";
+		enum-name = "PWR_EN_PP5000_A";
+		gpios = <&gpiok 5 0>;
+		output;
+	};
+	pwr-en-pp3300-s5 {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PP3300_S5 enable output to LS";
+		enum-name = "PWR_EN_PP3300_A";
+		gpios = <&gpioc 5 0>;
+		output;
+	};
+	pwr-pg-ec-rsmrst-odl {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST power good from regulator";
+		enum-name = "PWR_RSMRST";
+		gpios = <&gpioe 1 0>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-ec-pch-rsmrst-odl {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST output to PCH";
+		enum-name = "PWR_EC_PCH_RSMRST";
+		gpios = <&gpioh 0 0>;
+		output;
+	};
+	pwr-slp-s0-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_S0_L input from PCH";
+		enum-name = "PWR_SLP_S0";
+		gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-slp-s3-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_S3_L input from PCH";
+		enum-name = "PWR_SLP_S3";
+		gpios = <&gpioh 3 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-slp-sus-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_SUS_L input from PCH";
+		enum-name = "PWR_SLP_SUS";
+		gpios = <&gpiog 2 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-ec-soc-dsw-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "DSW_PWROK output to PCH";
+		enum-name = "PWR_EC_SOC_DSW_PWROK";
+		gpios = <&gpiol 7 0>;
+		output;
+	};
+	pwr-vccst-pwrgd-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "VCCST_PWRGD output to PCH";
+		enum-name = "PWR_VCCST_PWRGD";
+		gpios = <&gpioe 5 (GPIO_OPEN_DRAIN | GPIO_VOLTAGE_1P8)>;
+		output;
+	};
+	pwr-imvp9-vrrdy-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "VRRDY input from IMVP9";
+		enum-name = "PWR_IMVP9_VRRDY";
+		gpios = <&gpioj 4 0>;
+	};
+	pwr-pch-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PCH_PWROK output to PCH";
+		enum-name = "PWR_PCH_PWROK";
+		gpios = <&gpiod 6 GPIO_OPEN_DRAIN>;
+		output;
+	};
+	pwr-ec-pch-sys-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_PWROK output to PCH";
+		enum-name = "PWR_EC_PCH_SYS_PWROK";
+		gpios = <&gpiof 2 0>;
+		output;
+	};
+	pwr-sys-rst-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_RESET# output to PCH";
+		enum-name = "PWR_SYS_RST";
+		gpios = <&gpiod 1 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>;
+		output;
+	};
+	pwr-slp-s4 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S4 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S4";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4";
+		vw-invert;
+	};
+	pwr-slp-s5 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S5 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S5";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5";
+		vw-invert;
+	};
+	pwr-all-sys-pwrgd {
+		/*
+		 * This is a board level signal, since this
+		 * signal needs some special processing.
+		 */
+		compatible = "intel,ap-pwrseq-external";
+		dbg-label = "Combined all power good";
+		enum-name = "PWR_ALL_SYS_PWRGD";
+	};
+	pwr-adc-pp3300 {
+		compatible = "intel,ap-pwrseq-adc";
+		dbg-label = "PP3300_PROC";
+		enum-name = "PWR_DSW_PWROK";
+		trigger-high = <&vcmp0>;
+		trigger-low = <&vcmp1>;
+	};
+	pwr-adc-pp1p05 {
+		compatible = "intel,ap-pwrseq-adc";
+		dbg-label = "PP1P05_PROC";
+		enum-name = "PWR_PG_PP1P05";
+		trigger-high = <&vcmp2>;
+		trigger-low = <&vcmp3>;
+	};
+
+};
+
+/*
+ * Because the power signals directly reference the GPIOs,
+ * the correspinding named-gpios need to have no-auto-init set.
+ */
+&gpio_ec_soc_dsw_pwrok {
+	no-auto-init;
+};
+&gpio_ec_soc_pch_pwrok_od {
+	no-auto-init;
+};
+&gpio_ec_soc_rsmrst_l {
+	no-auto-init;
+};
+&gpio_ec_soc_sys_pwrok {
+	no-auto-init;
+};
+&gpio_ec_soc_vccst_pwrgd_od {
+	no-auto-init;
+};
+&gpio_en_pp3300_s5 {
+	no-auto-init;
+};
+&gpio_en_pp5000_s5 {
+	no-auto-init;
+};
+&gpio_imvp91_vrrdy_od {
+	no-auto-init;
+};
+&gpio_rsmrst_pwrgd_l {
+	no-auto-init;
+};
+&gpio_slp_s0_l {
+	no-auto-init;
+};
+&gpio_slp_s3_l {
+	no-auto-init;
+};
+&gpio_slp_sus_l {
+	no-auto-init;
+};
+&gpio_sys_rst_odl {
+	no-auto-init;
+};
+&vcmp0 {
+	status = "okay";
+	scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>;
+	comparison = <IT8XXX2_VCMP_GREATER>;
+	/*
+	 * This is 90% of nominal voltage considering voltage
+	 * divider on ADC input.
+	 */
+	threshold-mv = <2448>;
+	io-channels = <&adc0 0>;
+};
+&vcmp1 {
+	status = "okay";
+	scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>;
+	comparison = <IT8XXX2_VCMP_LESS_OR_EQUAL>;
+	threshold-mv = <2448>;
+	io-channels = <&adc0 0>;
+};
+&vcmp2 {
+	status = "okay";
+	scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>;
+	comparison = <IT8XXX2_VCMP_GREATER>;
+	/* Setting at 90% of nominal voltage */
+	threshold-mv = <945>;
+	io-channels = <&adc0 14>;
+};
+&vcmp3 {
+	status = "okay";
+	scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>;
+	comparison = <IT8XXX2_VCMP_LESS_OR_EQUAL>;
+	threshold-mv = <945>;
+	io-channels = <&adc0 14>;
+};
diff --git a/zephyr/projects/nissa/nereid/prj.conf b/zephyr/projects/nissa/nereid/prj.conf
new file mode 100644
index 0000000000..75a5faba5d
--- /dev/null
+++ b/zephyr/projects/nissa/nereid/prj.conf
@@ -0,0 +1,17 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_BOARD_NEREID=y
+
+# Ensure recovery key combination (esc+refresh+power) is reliable: b/236580049
+CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI2=y
+
+# Sensor drivers
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y
+CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y
+CONFIG_PLATFORM_EC_MAX_SENSOR_FREQ_MILLIHZ=100000
+
+# No fan supported, and tach is default-enabled
+CONFIG_TACH_IT8XXX2=n
diff --git a/zephyr/projects/nissa/craask_pwm_leds.dts b/zephyr/projects/nissa/nereid/pwm_leds.dts
index 592275ff71..aa4a76b271 100644
--- a/zephyr/projects/nissa/craask_pwm_leds.dts
+++ b/zephyr/projects/nissa/nereid/pwm_leds.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,9 +7,9 @@
 	pwmleds {
 		compatible = "pwm-leds";
 		pwm_led0: pwm_led_0 {
-			pwms = <&pwm2 2 0 PWM_POLARITY_INVERTED>,
-			       <&pwm0 0 0 PWM_POLARITY_INVERTED>,
-			       <&pwm1 1 0 PWM_POLARITY_INVERTED>;
+			pwms = <&pwm1 1 PWM_HZ(1296) PWM_POLARITY_INVERTED>,
+			       <&pwm2 2 PWM_HZ(1296) PWM_POLARITY_INVERTED>,
+			       <&pwm3 3 PWM_HZ(1296) PWM_POLARITY_INVERTED>;
 		};
 	};
 
@@ -17,7 +17,6 @@
 		compatible = "cros-ec,pwm-leds";
 
 		leds = <&pwm_led0>;
-		frequency = <324>;
 
 				/*<red green blue>*/
 		color-map-red    = <100   0    0>;
@@ -25,7 +24,7 @@
 		color-map-blue   = <  0   0  100>;
 		color-map-yellow = <  0  50   50>;
 		color-map-white  = <100 100  100>;
-		color-map-amber  = <100   5    0>;
+		color-map-amber  = <100  15    0>;
 
 		brightness-range = <100 100 100 0 0 0>;
 
@@ -39,25 +38,23 @@
 	};
 };
 
-/* Enable LEDs to work while CPU suspended */
-
-&pwm0 {
+&pwm1 {
 	status = "okay";
-	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
-	pinctrl-0 = <&pwm0_gpc3>;
+	prescaler-cx = <PWM_PRESCALER_C4>;
+	pinctrl-0 = <&pwm1_gpa1_default>;
 	pinctrl-names = "default";
 };
 
-&pwm1 {
+&pwm2 {
 	status = "okay";
-	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
-	pinctrl-0 = <&pwm1_gpc2>;
+	prescaler-cx = <PWM_PRESCALER_C4>;
+	pinctrl-0 = <&pwm2_gpa2_default>;
 	pinctrl-names = "default";
 };
 
-&pwm2 {
+&pwm3 {
 	status = "okay";
-	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
-	pinctrl-0 = <&pwm2_gpc4>;
+	prescaler-cx = <PWM_PRESCALER_C4>;
+	pinctrl-0 = <&pwm3_gpa3_default>;
 	pinctrl-names = "default";
 };
diff --git a/zephyr/projects/nissa/src/nereid/charger.c b/zephyr/projects/nissa/nereid/src/charger.c
index a494988951..181e9a61fd 100644
--- a/zephyr/projects/nissa/src/nereid/charger.c
+++ b/zephyr/projects/nissa/nereid/src/charger.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/nissa/nereid/src/hdmi.c b/zephyr/projects/nissa/nereid/src/hdmi.c
new file mode 100644
index 0000000000..7e5708c6eb
--- /dev/null
+++ b/zephyr/projects/nissa/nereid/src/hdmi.c
@@ -0,0 +1,28 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <cros_board_info.h>
+#include "nissa_hdmi.h"
+
+__override void nissa_configure_hdmi_power_gpios(void)
+{
+	/*
+	 * Nereid versions before 2 need hdmi-en-odl to be
+	 * pulled down to enable VCC on the HDMI port, but later
+	 * versions (and other boards) disconnect this so
+	 * the port's VCC directly follows en-rails-odl. Only
+	 * configure the GPIO if needed, to save power.
+	 */
+	uint32_t board_version = 0;
+
+	/* CBI errors ignored, will configure the pin */
+	cbi_get_board_version(&board_version);
+	if (board_version < 2) {
+		nissa_configure_hdmi_vcc();
+	}
+
+	/* Still always need core rails controlled */
+	nissa_configure_hdmi_rails();
+}
diff --git a/zephyr/projects/nissa/src/nereid/keyboard.c b/zephyr/projects/nissa/nereid/src/keyboard.c
index d0d1406307..b69bb4da33 100644
--- a/zephyr/projects/nissa/src/nereid/keyboard.c
+++ b/zephyr/projects/nissa/nereid/src/keyboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,8 +22,8 @@ static const struct ec_response_keybd_config nereid_kb_legacy = {
 	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
 };
 
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	return &nereid_kb_legacy;
 }
diff --git a/zephyr/projects/nissa/nereid/src/usbc.c b/zephyr/projects/nissa/nereid/src/usbc.c
new file mode 100644
index 0000000000..48f7cfd9cb
--- /dev/null
+++ b/zephyr/projects/nissa/nereid/src/usbc.c
@@ -0,0 +1,393 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/logging/log.h>
+#include <ap_power/ap_power.h>
+
+#include "charge_state_v2.h"
+#include "chipset.h"
+#include "hooks.h"
+#include "usb_mux.h"
+#include "system.h"
+#include "driver/charger/sm5803.h"
+#include "driver/tcpm/it83xx_pd.h"
+#include "driver/tcpm/ps8xxx_public.h"
+#include "driver/tcpm/tcpci.h"
+
+#include "nissa_common.h"
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_EMBEDDED,
+		/* TCPC is embedded within EC so no i2c config needed */
+		.drv = &it8xxx2_tcpm_drv,
+		/* Alert is active-low, push-pull */
+		.flags = 0,
+	},
+	{
+		/*
+		 * Sub-board: optional PS8745 TCPC+redriver. Behaves the same
+		 * as PS8815.
+		 */
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C1_TCPC,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+		/* PS8745 implements TCPCI 2.0 */
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+	},
+};
+
+/* Vconn control for integrated ITE TCPC */
+void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
+{
+	/* Vconn control is only for port 0 */
+	if (port)
+		return;
+
+	if (cc_pin == USBPD_CC_PIN_1)
+		gpio_pin_set_dt(
+			GPIO_DT_FROM_NODELABEL(gpio_en_usb_c0_cc1_vconn),
+			!!enabled);
+	else
+		gpio_pin_set_dt(
+			GPIO_DT_FROM_NODELABEL(gpio_en_usb_c0_cc2_vconn),
+			!!enabled);
+}
+
+__override bool pd_check_vbus_level(int port, enum vbus_level level)
+{
+	return sm5803_check_vbus_level(port, level);
+}
+
+/*
+ * Putting chargers into LPM when in suspend reduces power draw by about 8mW
+ * per charger, but also seems critical to correct operation in source mode:
+ * if chargers are not in LPM when a sink is first connected, VBUS sourcing
+ * works even if the partner is later removed (causing LPM entry) and
+ * reconnected (causing LPM exit). If in LPM initially, sourcing VBUS
+ * consistently causes the charger to report (apparently spurious) overcurrent
+ * failures.
+ *
+ * In short, this is important to making things work correctly but we don't
+ * understand why.
+ */
+static void board_chargers_suspend(struct ap_power_ev_callback *const cb,
+				   const struct ap_power_ev_data data)
+{
+	void (*fn)(int chgnum);
+
+	switch (data.event) {
+	case AP_POWER_SUSPEND:
+		fn = sm5803_enable_low_power_mode;
+		break;
+	case AP_POWER_RESUME:
+		fn = sm5803_disable_low_power_mode;
+		break;
+	default:
+		LOG_WRN("%s: power event %d is not recognized", __func__,
+			data.event);
+		return;
+	}
+
+	fn(CHARGER_PRIMARY);
+	if (board_get_charger_chip_count() > 1)
+		fn(CHARGER_SECONDARY);
+}
+
+static int board_chargers_suspend_init(const struct device *unused)
+{
+	static struct ap_power_ev_callback cb = {
+		.handler = board_chargers_suspend,
+		.events = AP_POWER_SUSPEND | AP_POWER_RESUME,
+	};
+	ap_power_ev_add_callback(&cb);
+	return 0;
+}
+SYS_INIT(board_chargers_suspend_init, APPLICATION, 0);
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count());
+	int i;
+	int old_port;
+	int rv;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	old_port = charge_manager_get_active_charge_port();
+	LOG_INF("Charge update: p%d -> p%d", old_port, port);
+
+	/* Check if port is sourcing VBUS. */
+	if (port != CHARGE_PORT_NONE && charger_is_sourcing_otg_power(port)) {
+		LOG_WRN("Skip enable p%d: already sourcing", port);
+		return EC_ERROR_INVAL;
+	}
+
+	/* Disable sinking on all ports except the desired one */
+	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+		if (i == port)
+			continue;
+
+		if (sm5803_vbus_sink_enable(i, 0))
+			/*
+			 * Do not early-return because this can fail during
+			 * power-on which would put us into a loop.
+			 */
+			LOG_WRN("p%d: sink path disable failed.", i);
+	}
+
+	/* Don't enable anything (stop here) if no ports were requested */
+	if ((port == CHARGE_PORT_NONE) || (old_port == port))
+		return EC_SUCCESS;
+
+	/*
+	 * Stop the charger IC from switching while changing ports.  Otherwise,
+	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
+	 */
+	if (old_port != CHARGE_PORT_NONE)
+		charger_discharge_on_ac(1);
+
+	/* Enable requested charge port. */
+	rv = sm5803_vbus_sink_enable(port, 1);
+	if (rv)
+		LOG_WRN("p%d: sink path enable failed: code %d", port, rv);
+
+	/* Allow the charger IC to begin/continue switching. */
+	charger_discharge_on_ac(0);
+
+	return rv;
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	/*
+	 * TCPC 0 is embedded in the EC and processes interrupts in the chip
+	 * code (it83xx/intc.c). This function only needs to poll port C1 if
+	 * present.
+	 */
+	uint16_t status = 0;
+	int regval;
+
+	/* Is the C1 port present and its IRQ line asserted? */
+	if (board_get_usb_pd_port_count() == 2 &&
+	    !gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) {
+		/*
+		 * C1 IRQ is shared between BC1.2 and TCPC; poll TCPC to see if
+		 * it asserted the IRQ.
+		 */
+		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
+			if (regval)
+				status = PD_STATUS_TCPC_ALERT_1;
+		}
+	}
+
+	return status;
+}
+
+void pd_power_supply_reset(int port)
+{
+	int prev_en;
+
+	if (port < 0 || port >= board_get_usb_pd_port_count())
+		return;
+
+	prev_en = charger_is_sourcing_otg_power(port);
+
+	/* Disable Vbus */
+	charger_enable_otg_power(port, 0);
+
+	/* Discharge Vbus if previously enabled */
+	if (prev_en)
+		sm5803_set_vbus_disch(port, 1);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	enum ec_error_list rv;
+
+	if (port < 0 || port > board_get_usb_pd_port_count()) {
+		LOG_WRN("Port C%d does not exist, cannot enable VBUS", port);
+		return EC_ERROR_INVAL;
+	}
+
+	/* Disable sinking */
+	rv = sm5803_vbus_sink_enable(port, 0);
+	if (rv) {
+		LOG_WRN("C%d failed to disable sinking: %d", port, rv);
+		return rv;
+	}
+
+	/* Disable Vbus discharge */
+	rv = sm5803_set_vbus_disch(port, 0);
+	if (rv) {
+		LOG_WRN("C%d failed to clear VBUS discharge: %d", port, rv);
+		return rv;
+	}
+
+	/* Provide Vbus */
+	rv = charger_enable_otg_power(port, 1);
+	if (rv) {
+		LOG_WRN("C%d failed to enable VBUS sourcing: %d", port, rv);
+		return rv;
+	}
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	int rv;
+	const int current = rp == TYPEC_RP_3A0 ? 3000 : 1500;
+
+	rv = charger_set_otg_current_voltage(port, current, 5000);
+	if (rv != EC_SUCCESS) {
+		LOG_WRN("Failed to set source ilimit on port %d to %d: %d",
+			port, current, rv);
+	}
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * Do nothing. The integrated TCPC for C0 lacks a dedicated reset
+	 * command, and C1 (if present) doesn't have a reset pin connected
+	 * to the EC.
+	 */
+}
+
+#define INT_RECHECK_US 5000
+
+/* C0 interrupt line shared by BC 1.2 and charger */
+
+static void check_c0_line(void);
+DECLARE_DEFERRED(check_c0_line);
+
+static void notify_c0_chips(void)
+{
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+	sm5803_interrupt(0);
+}
+
+static void check_c0_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips
+	 */
+	if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl))) {
+		notify_c0_chips();
+		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+	}
+}
+
+void usb_c0_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c0_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c0_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+}
+
+/* C1 interrupt line shared by BC 1.2, TCPC, and charger */
+static void check_c1_line(void);
+DECLARE_DEFERRED(check_c1_line);
+
+static void notify_c1_chips(void)
+{
+	schedule_deferred_pd_interrupt(1);
+	usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+	/* Charger is handled in board_process_pd_alert */
+}
+
+static void check_c1_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips.
+	 */
+	if (!gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) {
+		notify_c1_chips();
+		hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
+	}
+}
+
+void usb_c1_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c1_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c1_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
+}
+
+/*
+ * Check state of IRQ lines at startup, ensuring an IRQ that happened before
+ * the EC started up won't get lost (leaving the IRQ line asserted and blocking
+ * any further interrupts on the port).
+ *
+ * Although the PD task will check for pending TCPC interrupts on startup,
+ * the charger sharing the IRQ will not be polled automatically.
+ */
+void board_handle_initial_typec_irq(void)
+{
+	check_c0_line();
+	if (board_get_usb_pd_port_count() == 2)
+		check_c1_line();
+}
+/*
+ * This must run after sub-board detection (which happens in EC main()),
+ * but isn't depended on by anything else either.
+ */
+DECLARE_HOOK(HOOK_INIT, board_handle_initial_typec_irq, HOOK_PRIO_LAST);
+
+/*
+ * Handle charger interrupts in the PD task. Not doing so can lead to a priority
+ * inversion where we fail to respond to TCPC alerts quickly enough because we
+ * don't get another edge on a shared IRQ until the charger interrupt is cleared
+ * (or the IRQ is polled again), which happens in the low-priority charger task:
+ * the high-priority type-C handler is thus blocked on the lower-priority
+ * charger.
+ *
+ * To avoid that, we run charger interrupts at the same priority.
+ */
+void board_process_pd_alert(int port)
+{
+	/*
+	 * Port 0 doesn't use an external TCPC, so its interrupts don't need
+	 * this special handling.
+	 */
+	if (port == 1 &&
+	    !gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) {
+		sm5803_handle_interrupt(port);
+	}
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	int chg_det = 0;
+
+	sm5803_get_chg_det(port, &chg_det);
+
+	return chg_det;
+}
diff --git a/zephyr/projects/nissa/nivviks_cbi.dts b/zephyr/projects/nissa/nivviks/cbi.dts
index d8cc34ce77..112a2a885c 100644
--- a/zephyr/projects/nissa/nivviks_cbi.dts
+++ b/zephyr/projects/nissa/nivviks/cbi.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/nissa/pujjo_generated.dts b/zephyr/projects/nissa/nivviks/generated.dts
index 1c429ae32c..91718302b4 100644
--- a/zephyr/projects/nissa/pujjo_generated.dts
+++ b/zephyr/projects/nissa/nivviks/generated.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,25 +11,25 @@
 		compatible = "named-adc-channels";
 
 		adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc {
-			label = "EC_VSENSE_PP1050_PROC";
 			enum-name = "ADC_PP1050_PROC";
 			io-channels = <&adc0 4>;
 		};
 		adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 {
-			label = "EC_VSENSE_PP3300_S5";
 			enum-name = "ADC_PP3300_S5";
 			io-channels = <&adc0 6>;
 		};
 		adc_temp_sensor_1: temp_sensor_1 {
-			label = "TEMP_SENSOR_1";
 			enum-name = "ADC_TEMP_SENSOR_1";
 			io-channels = <&adc0 0>;
 		};
 		adc_temp_sensor_2: temp_sensor_2 {
-			label = "TEMP_SENSOR_2";
 			enum-name = "ADC_TEMP_SENSOR_2";
 			io-channels = <&adc0 1>;
 		};
+		adc_temp_sensor_3: temp_sensor_3 {
+			enum-name = "ADC_TEMP_SENSOR_3";
+			io-channels = <&adc0 10>;
+		};
 	};
 
 	named-gpios {
@@ -188,10 +188,10 @@
 			gpios = <&gpio0 1 GPIO_INPUT_PULL_UP>;
 		};
 		gpio_vccin_aux_vid0: vccin_aux_vid0 {
-			gpios = <&gpio9 2 GPIO_INPUT>;
+			gpios = <&gpio9 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
 		};
 		gpio_vccin_aux_vid1: vccin_aux_vid1 {
-			gpios = <&gpioe 3 GPIO_INPUT>;
+			gpios = <&gpioe 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
 		};
 		gpio_voldn_btn_odl: voldn_btn_odl {
 			gpios = <&gpioa 2 GPIO_INPUT_PULL_UP>;
@@ -208,23 +208,23 @@
 
 		i2c_ec_i2c_eeprom: ec_i2c_eeprom {
 			i2c-port = <&i2c0_0>;
-			enum-name = "I2C_PORT_EEPROM";
+			enum-names = "I2C_PORT_EEPROM";
 		};
 		i2c_ec_i2c_sensor: ec_i2c_sensor {
 			i2c-port = <&i2c1_0>;
-			enum-name = "I2C_PORT_SENSOR";
+			enum-names = "I2C_PORT_SENSOR";
 		};
 		i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 {
 			i2c-port = <&i2c3_0>;
-			enum-name = "I2C_PORT_USB_C0_TCPC";
+			enum-names = "I2C_PORT_USB_C0_TCPC";
 		};
 		i2c_ec_i2c_sub_usb_c1: ec_i2c_sub_usb_c1 {
 			i2c-port = <&i2c5_1>;
-			enum-name = "I2C_PORT_USB_C1_TCPC";
+			enum-names = "I2C_PORT_USB_C1_TCPC";
 		};
 		i2c_ec_i2c_batt: ec_i2c_batt {
 			i2c-port = <&i2c7_0>;
-			enum-name = "I2C_PORT_BATTERY";
+			enum-names = "I2C_PORT_BATTERY";
 		};
 	};
 };
@@ -234,7 +234,8 @@
 	pinctrl-0 = <&adc0_chan0_gp45
 		     &adc0_chan1_gp44
 		     &adc0_chan4_gp41
-		     &adc0_chan6_gp34>;
+		     &adc0_chan6_gp34
+		     &adc0_chan10_gpe0>;
 	pinctrl-names = "default";
 };
 
diff --git a/zephyr/projects/nissa/pujjo_keyboard.dts b/zephyr/projects/nissa/nivviks/keyboard.dts
index 71cb49ce65..00610e4e18 100644
--- a/zephyr/projects/nissa/pujjo_keyboard.dts
+++ b/zephyr/projects/nissa/nivviks/keyboard.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,13 +6,13 @@
 / {
 	kblight {
 		compatible = "cros-ec,kblight-pwm";
-		pwms = <&pwm6 6 PWM_KHZ(10) PWM_POLARITY_NORMAL>;
-		frequency = <10000>;
+		pwms = <&pwm6 6 PWM_HZ(2400) PWM_POLARITY_NORMAL>;
 	};
 };
 
 &pwm6 {
 	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
 	pinctrl-0 = <&pwm6_gpc0>;
 	pinctrl-names = "default";
 };
diff --git a/zephyr/projects/nissa/nivviks_motionsense.dts b/zephyr/projects/nissa/nivviks/motionsense.dts
index f42526db32..6297a07bf5 100644
--- a/zephyr/projects/nissa/nivviks_motionsense.dts
+++ b/zephyr/projects/nissa/nivviks/motionsense.dts
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,11 +25,9 @@
 	motionsense-mutex {
 		compatible = "cros-ec,motionsense-mutex";
 		lid_mutex: lid-mutex {
-			label = "LID_MUTEX";
 		};
 
 		base_mutex: base-mutex {
-			label = "BASE_MUTEX";
 		};
 	};
 
@@ -65,7 +63,12 @@
 	 * "struct als_drv_data_t" in accelgyro.h
 	 */
 	motionsense-sensor-data {
-		lsm6dso_data: lsm6dso-drv-data {
+		lsm6dso_accel_data: lsm6dso-accel-drv-data {
+			compatible = "cros-ec,drvdata-lsm6dso";
+			status = "okay";
+		};
+
+		lsm6dso_gyro_data: lsm6dso-gyro-drv-data {
 			compatible = "cros-ec,drvdata-lsm6dso";
 			status = "okay";
 		};
@@ -78,9 +81,9 @@
 
 	/*
 	 * List of motion sensors that creates motion_sensors array.
-	 * The label "lid_accel" and "base_accel" are used to indicate
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
 	 * motion sensor IDs for lid angle calculation.
-	 * TODO:(b/229577857) The first entries of the array must be
+	 * TODO(b/238139272): The first entries of the array must be
 	 * accelerometers,then gyroscope. Fix this dependency in the DTS
 	 * processing which makes the devicetree entries independent.
 	 */
@@ -89,7 +92,6 @@
 			compatible = "cros-ec,lis2dw12";
 			status = "okay";
 
-			label = "Lid Accel";
 			active-mask = "SENSOR_ACTIVE_S0_S3";
 			location = "MOTIONSENSE_LOC_LID";
 			mutex = <&lid_mutex>;
@@ -102,11 +104,9 @@
 				compatible =
 					"cros-ec,motionsense-sensor-config";
 				ec-s0 {
-					label = "SENSOR_CONFIG_EC_S0";
 					odr = <(10000 | ROUND_UP_FLAG)>;
 				};
 				ec-s3 {
-					label = "SENSOR_CONFIG_EC_S3";
 					odr = <(10000 | ROUND_UP_FLAG)>;
 				};
 			};
@@ -116,7 +116,6 @@
 			compatible = "cros-ec,lsm6dso-accel";
 			status = "okay";
 
-			label = "Base Accel";
 			active-mask = "SENSOR_ACTIVE_S0_S3";
 			location = "MOTIONSENSE_LOC_BASE";
 			mutex = <&base_mutex>;
@@ -126,16 +125,14 @@
 			 * on board config.
 			 */
 			rot-standard-ref = <&base_rot_ref>;
-			drv-data = <&lsm6dso_data>;
+			drv-data = <&lsm6dso_accel_data>;
 			configs {
 				compatible =
 					"cros-ec,motionsense-sensor-config";
 				ec-s0 {
-					label = "SENSOR_CONFIG_EC_S0";
 					odr = <(10000 | ROUND_UP_FLAG)>;
 				};
 				ec-s3 {
-					label = "SENSOR_CONFIG_EC_S3";
 					odr = <(10000 | ROUND_UP_FLAG)>;
 				};
 			};
@@ -145,13 +142,13 @@
 			compatible = "cros-ec,lsm6dso-gyro";
 			status = "okay";
 
-			label = "Base Gyro";
 			active-mask = "SENSOR_ACTIVE_S0_S3";
 			location = "MOTIONSENSE_LOC_BASE";
 			mutex = <&base_mutex>;
 			port = <&i2c_ec_i2c_sensor>;
 			rot-standard-ref = <&base_rot_ref>;
-			drv-data = <&lsm6dso_data>;
+			default-range = <(1000 | ROUND_UP_FLAG)>; /* dps */
+			drv-data = <&lsm6dso_gyro_data>;
 		};
 	};
 
diff --git a/zephyr/projects/nissa/nivviks_overlay.dts b/zephyr/projects/nissa/nivviks/overlay.dts
index bc10f510a5..c2d5e3f24b 100644
--- a/zephyr/projects/nissa/nivviks_overlay.dts
+++ b/zephyr/projects/nissa/nivviks/overlay.dts
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,6 +22,9 @@
 		default_battery: lgc {
 			compatible = "lgc,ap18c8k", "battery-smart";
 		};
+		lgc_ap19b8m {
+			compatible = "lgc,ap19b8m", "battery-smart";
+		};
 	};
 
 	hibernate-wake-pins {
@@ -83,28 +86,40 @@
 	};
 
 	named-gpios {
-		gpio_sb_1: sb_1 {
+		gpio_sb_1: sb-1 {
 			gpios = <&gpio0 2 GPIO_PULL_UP>;
 			no-auto-init;
 		};
 
-		gpio_sb_2: sb_2 {
+		gpio_sb_2: sb-2 {
 			gpios = <&gpiod 4 GPIO_OUTPUT>;
 			no-auto-init;
 		};
 
-		gpio_sb_3: sb_3 {
-			gpios = <&gpiof 4 GPIO_OPEN_DRAIN>;
+		/*
+		 * Set I2C pins for type C sub-board to be low voltage (I2C5_1).
+		 * We do this for all boards, since the pins are 3.3V tolerant,
+		 * and the only 2 types of sub-boards used on nivviks both have
+		 * type-C ports on them.
+		 */
+		gpio_sb_3: sb-3 {
+			gpios = <&gpiof 4 (GPIO_OPEN_DRAIN | GPIO_VOLTAGE_1P8)>;
 			no-auto-init;
 		};
-		gpio_sb_4: sb_4 {
-			gpios = <&gpiof 5 GPIO_INPUT>;
+		gpio_sb_4: sb-4 {
+			gpios = <&gpiof 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
 			no-auto-init;
 		};
 		gpio_fan_enable: fan-enable {
 			gpios = <&gpio6 3 GPIO_OUTPUT>;
 			no-auto-init;
 		};
+		ec-i2c-sensor-scl {
+			gpios = <&gpio9 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		ec-i2c-sensor-sda {
+			gpios = <&gpio8 7 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
 	};
 
 	/*
@@ -132,32 +147,50 @@
 		gpio-en-sub-s5-rails = &gpio_sb_2;
 	};
 
+	temp_memory: memory {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_1>;
+	};
+	temp_charger: charger {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_2>;
+	};
+	temp_ambient: ambient {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_3>;
+	};
+
 	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
 		memory {
-			compatible = "cros-ec,temp-sensor-thermistor",
-				     "cros-ec,temp-sensor";
-			thermistor = <&thermistor_3V3_51K1_47K_4050B>;
-			label = "DDR and SOC";
-			enum-name = "TEMP_SENSOR_1";
 			temp_fan_off = <35>;
 			temp_fan_max = <60>;
 			temp_host_high = <85>;
 			temp_host_halt = <90>;
 			temp_host_release_high = <80>;
-			adc = <&adc_temp_sensor_1>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_memory>;
 		};
 		charger {
-			compatible = "cros-ec,temp-sensor-thermistor",
-				     "cros-ec,temp-sensor";
-			thermistor = <&thermistor_3V3_51K1_47K_4050B>;
-			label = "Charger";
-			enum-name = "TEMP_SENSOR_2";
 			temp_fan_off = <35>;
 			temp_fan_max = <60>;
 			temp_host_high = <85>;
 			temp_host_halt = <90>;
 			temp_host_release_high = <80>;
-			adc = <&adc_temp_sensor_2>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_charger>;
+		};
+		ambient {
+			temp_fan_off = <35>;
+			temp_fan_max = <60>;
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_ambient>;
 		};
 	};
 
@@ -183,21 +216,12 @@
 		port0@0 {
 			compatible = "named-usbc-port";
 			reg = <0>;
-			bc12 {
-				compatible = "pericom,pi3usb9201";
-				port = <&i2c_ec_i2c_usb_c0>;
-				/*
-				 * BC1.2 interrupt is shared with TCPC, so
-				 * IRQ is not specified here and handled by
-				 * usb_c0_interrupt.
-				 */
+			bc12 = <&bc12_port0>;
+			chg = <&chg_port0>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_0>;
 			};
-			chg {
-				compatible = "intersil,isl923x";
-				status = "okay";
-				port = <&i2c_ec_i2c_usb_c0>;
-			};
-			usb-muxes = <&virtual_mux_0>;
 		};
 		port0-muxes {
 			virtual_mux_0: virtual-mux-0 {
@@ -211,30 +235,22 @@
 		port1@1 {
 			compatible = "named-usbc-port";
 			reg = <1>;
-			bc12 {
-				compatible = "pericom,pi3usb9201";
-				port = <&i2c_ec_i2c_sub_usb_c1>;
+			bc12 = <&bc12_port1>;
+			chg = <&chg_port1>;
+			usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_1 &anx7483_mux_1>;
 			};
-			chg {
-				compatible = "intersil,isl923x";
-				status = "okay";
-				port = <&i2c_ec_i2c_sub_usb_c1>;
+			usb_mux_chain_1_no_mux: usb-mux-chain-1-no-mux {
+				compatible = "cros-ec,usb-mux-chain";
+				alternative-chain;
+				usb-muxes = <&virtual_mux_1>;
 			};
-			/*
-			 * Some sub-boards may disable all usb muxes in chain
-			 * except virtual_mux_1
-			 */
-			usb-muxes = <&virtual_mux_1 &anx7483_mux_1>;
 		};
 		port1-muxes {
 			virtual_mux_1: virtual-mux-1 {
 				compatible = "cros-ec,usbc-mux-virtual";
 			};
-			anx7483_mux_1: anx7483-mux-1 {
-				compatible = "analogix,anx7483";
-				port = <&i2c_ec_i2c_sub_usb_c1>;
-				i2c-addr-flags = "ANX7483_I2C_ADDR0_FLAGS";
-			};
 		};
 	};
 
@@ -243,7 +259,6 @@
 
 		fan_0 {
 			pwms = <&pwm5 5 PWM_KHZ(1) PWM_POLARITY_NORMAL>;
-			pwm-frequency = <1000>;
 			rpm_min = <2200>;
 			rpm_start = <2200>;
 			rpm_max = <4200>;
@@ -252,24 +267,6 @@
 		};
 	};
 
-	/*
-	 * Set I2C pins for type C sub-board to be
-	 * low voltage (I2C5_1).
-	 * We do this for all boards, since the pins are
-	 * 3.3V tolerant, and the only 2 types of sub-boards
-	 * used on nivviks both have type-C ports on them.
-	 */
-	 def-lvol-io-list {
-		compatible = "nuvoton,npcx-lvolctrl-def";
-		lvol-io-pads = <
-			&lvol_iof5
-			&lvol_iof4
-			&lvol_io90 /* EC_I2C_SENSOR_SCL */
-			&lvol_io87 /* EC_I2C_SENSOR_SDA */
-			&lvol_ioe3 /* VCCIN_AUX_VID1 */
-			&lvol_io92 /* VCCIN_AUX_VID0 */
-		>;
-	 };
 	 /*
 	  * Declare unused GPIOs so that they are shut down
 	  * and use minimal power
@@ -320,7 +317,6 @@
 	cbi_eeprom: eeprom@50 {
 		compatible = "atmel,at24";
 		reg = <0x50>;
-		label = "EEPROM_CBI";
 		size = <2048>;
 		pagesize = <16>;
 		address-width = <8>;
@@ -336,11 +332,46 @@
 &i2c3_0 {
 	label = "I2C_USB_C0_TCPC";
 	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+
+	bc12_port0: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+		/*
+		 * BC1.2 interrupt is shared with TCPC, so
+		 * IRQ is not specified here and handled by
+		 * usb_c0_interrupt.
+		 */
+	};
+
+	chg_port0: isl923x@9 {
+		compatible = "intersil,isl923x";
+		status = "okay";
+		reg = <0x9>;
+	};
 };
 
 &i2c5_1 {
 	label = "I2C_SUB_C1_TCPC";
 	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+
+	bc12_port1: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+	};
+
+	chg_port1: isl923x@9 {
+		compatible = "intersil,isl923x";
+		status = "okay";
+		reg = <0x9>;
+	};
+
+	anx7483_mux_1: anx7483-mux-1@3e {
+		compatible = "analogix,anx7483";
+		reg = <0x3e>;
+		board-set = "anx7483_set_default_tuning";
+	};
 };
 
 &i2c7_0 {
@@ -354,6 +385,7 @@
 
 &pwm5 {
 	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
 	pinctrl-0 = <&pwm5_gpb7>;
 	pinctrl-names = "default";
 };
@@ -374,3 +406,13 @@
 	pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>;
 	pinctrl-names = "default";
 };
+
+/*
+ * Declare GPIOs that have leakage current caused by board issues here. NPCX ec
+ * will disable their input buffers before entering deep sleep and restore them
+ * after waking up automatically for better power consumption.
+ */
+&power_leakage_io {
+	leak-gpios = <&gpioa 4 0
+		      &gpiof 1 0>;
+};
diff --git a/zephyr/projects/nissa/craask_power_signals.dts b/zephyr/projects/nissa/nivviks/power_signals.dts
index 91876f0402..1d2b23069d 100644
--- a/zephyr/projects/nissa/craask_power_signals.dts
+++ b/zephyr/projects/nissa/nivviks/power_signals.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/nissa/nivviks/prj.conf b/zephyr/projects/nissa/nivviks/prj.conf
new file mode 100644
index 0000000000..af9e4e2586
--- /dev/null
+++ b/zephyr/projects/nissa/nivviks/prj.conf
@@ -0,0 +1,8 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_BOARD_NIVVIKS=y
+CONFIG_PLATFORM_EC_OCPC=y
+
+CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSO=y
diff --git a/zephyr/projects/nissa/pujjo_pwm_leds.dts b/zephyr/projects/nissa/nivviks/pwm_leds.dts
index b6f657fb03..a265a5929e 100644
--- a/zephyr/projects/nissa/pujjo_pwm_leds.dts
+++ b/zephyr/projects/nissa/nivviks/pwm_leds.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,7 +17,6 @@
 		compatible = "cros-ec,pwm-leds";
 
 		leds = <&pwm_led0>;
-		frequency = <324>;
 
 				/*<red green blue>*/
 		color-map-red    = <100   0    0>;
@@ -25,9 +24,9 @@
 		color-map-blue   = <  0   0  100>;
 		color-map-yellow = <  0  50   50>;
 		color-map-white  = <100 100  100>;
-		color-map-amber  = <100  20  100>;
+		color-map-amber  = <100   0    0>;
 
-		brightness-range = <100 100 100 0 0 0>;
+		brightness-range = <0 0 100 0 0 100>;
 
 		#address-cells = <1>;
 		#size-cells = <0>;
diff --git a/zephyr/projects/nissa/src/nivviks/charger.c b/zephyr/projects/nissa/nivviks/src/charger.c
index 5a8bbe0e7a..e2f9f966e7 100644
--- a/zephyr/projects/nissa/src/nivviks/charger.c
+++ b/zephyr/projects/nissa/nivviks/src/charger.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/nissa/src/nivviks/fan.c b/zephyr/projects/nissa/nivviks/src/fan.c
index b177c6eab1..840049722c 100644
--- a/zephyr/projects/nissa/src/nivviks/fan.c
+++ b/zephyr/projects/nissa/nivviks/src/fan.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -28,8 +28,7 @@ static void fan_init(void)
 	 */
 	ret = cros_cbi_get_fw_config(FW_FAN, &val);
 	if (ret != 0) {
-		LOG_ERR("Error retrieving CBI FW_CONFIG field %d",
-			FW_FAN);
+		LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_FAN);
 		return;
 	}
 	if (val != FW_FAN_PRESENT) {
@@ -37,9 +36,8 @@ static void fan_init(void)
 		fan_set_count(0);
 	} else {
 		/* Configure the fan enable GPIO */
-		gpio_pin_configure_dt(
-			GPIO_DT_FROM_NODELABEL(gpio_fan_enable),
-			GPIO_OUTPUT);
+		gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_fan_enable),
+				      GPIO_OUTPUT);
 	}
 }
 DECLARE_HOOK(HOOK_INIT, fan_init, HOOK_PRIO_POST_FIRST);
diff --git a/zephyr/projects/nissa/src/nivviks/form_factor.c b/zephyr/projects/nissa/nivviks/src/form_factor.c
index 16132e4a6c..602b22baff 100644
--- a/zephyr/projects/nissa/src/nivviks/form_factor.c
+++ b/zephyr/projects/nissa/nivviks/src/form_factor.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,9 +19,9 @@ LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
  * Mainboard orientation support.
  */
 
-#define ALT_MAT		SENSOR_ROT_STD_REF_NAME(DT_NODELABEL(base_rot_inverted))
-#define BASE_SENSOR	SENSOR_ID(DT_NODELABEL(base_accel))
-#define BASE_GYRO	SENSOR_ID(DT_NODELABEL(base_gyro))
+#define ALT_MAT SENSOR_ROT_STD_REF_NAME(DT_NODELABEL(base_rot_inverted))
+#define BASE_SENSOR SENSOR_ID(DT_NODELABEL(base_accel))
+#define BASE_GYRO SENSOR_ID(DT_NODELABEL(base_gyro))
 
 static void form_factor_init(void)
 {
diff --git a/zephyr/projects/nissa/src/nivviks/keyboard.c b/zephyr/projects/nissa/nivviks/src/keyboard.c
index dc5c42e33a..f13d5bf78c 100644
--- a/zephyr/projects/nissa/src/nivviks/keyboard.c
+++ b/zephyr/projects/nissa/nivviks/src/keyboard.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,8 +22,8 @@ static const struct ec_response_keybd_config nivviks_kb = {
 	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
 };
 
-__override const struct ec_response_keybd_config
-*board_vivaldi_keybd_config(void)
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
 {
 	return &nivviks_kb;
 }
diff --git a/zephyr/projects/nissa/nivviks/src/led.c b/zephyr/projects/nissa/nivviks/src/led.c
new file mode 100644
index 0000000000..c0e4645326
--- /dev/null
+++ b/zephyr/projects/nissa/nivviks/src/led.c
@@ -0,0 +1,53 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery LED control for nissa
+ */
+#include "common.h"
+#include "ec_commands.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+#include "led_pwm.h"
+
+__override const int led_charge_lvl_1 = 5;
+__override const int led_charge_lvl_2 = 97;
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE,
+					   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER,
+					   1 * LED_ONE_SEC },
+					 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER,
+					    1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_AMBER,
+					   2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_BLUE,
+					   2 * LED_ONE_SEC } },
+	};
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_BLUE:
+		set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_BLUE);
+		break;
+	case EC_LED_COLOR_AMBER:
+		set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_AMBER);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		set_pwm_led_color(EC_LED_ID_BATTERY_LED, -1);
+		break;
+	}
+}
diff --git a/zephyr/projects/nissa/src/nivviks/usbc.c b/zephyr/projects/nissa/nivviks/src/usbc.c
index c068eba6f4..14fc5a071d 100644
--- a/zephyr/projects/nissa/src/nivviks/usbc.c
+++ b/zephyr/projects/nissa/nivviks/src/usbc.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -54,8 +54,7 @@ int board_is_sourcing_vbus(int port)
 
 int board_set_active_charge_port(int port)
 {
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	int i;
 	int old_port;
 
@@ -233,8 +232,7 @@ static void usbc_interrupt_trigger(int port)
 	usb_charger_task_set_event(port, USB_CHG_EVENT_BC12);
 }
 
-static inline void poll_usb_gpio(int port,
-				 const struct gpio_dt_spec *gpio,
+static inline void poll_usb_gpio(int port, const struct gpio_dt_spec *gpio,
 				 const struct deferred_data *ud)
 {
 	if (!gpio_pin_get_dt(gpio)) {
@@ -243,17 +241,15 @@ static inline void poll_usb_gpio(int port,
 	}
 }
 
-static void poll_c0_int (void)
+static void poll_c0_int(void)
 {
-	poll_usb_gpio(0,
-		      GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl),
+	poll_usb_gpio(0, GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl),
 		      &poll_c0_int_data);
 }
 
-static void poll_c1_int (void)
+static void poll_c1_int(void)
 {
-	poll_usb_gpio(1,
-		      GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl),
+	poll_usb_gpio(1, GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl),
 		      &poll_c1_int_data);
 }
 
diff --git a/zephyr/projects/nissa/prj.conf b/zephyr/projects/nissa/prj.conf
index df988de149..7a46a14076 100644
--- a/zephyr/projects/nissa/prj.conf
+++ b/zephyr/projects/nissa/prj.conf
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -38,13 +38,13 @@ CONFIG_PLATFORM_EC_VBOOT_HASH=y
 CONFIG_AP=y
 CONFIG_AP_X86_INTEL_ADL=y
 CONFIG_ESPI=y
-CONFIG_ESPI_LOG_LEVEL_ERR=y
-CONFIG_PLATFORM_EC_ESPI_VW_SLP_S4=y
-CONFIG_PLATFORM_EC_ESPI_VW_SLP_S5=y
+CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S4=y
+CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S5=y
 CONFIG_PLATFORM_EC_HOSTCMD=y
 CONFIG_HCDEBUG_OFF=y
 CONFIG_PLATFORM_EC_THROTTLE_AP=y
 CONFIG_PLATFORM_EC_PORT80=y
+CONFIG_PLATFORM_EC_PORT80_QUIET=y
 
 # AP Power Sequencing
 CONFIG_AP_PWRSEQ=y
@@ -52,6 +52,7 @@ CONFIG_X86_NON_DSX_PWRSEQ_ADL=y
 CONFIG_X86_NON_DSX_PWRSEQ_CONSOLE=y
 CONFIG_X86_NON_DSX_PWRSEQ_HOST_CMD=y
 CONFIG_AP_PWRSEQ_S0IX=y
+CONFIG_AP_PWRSEQ_S0IX_ERROR_RECOVERY=y
 
 # I2C
 CONFIG_I2C=y
@@ -79,7 +80,6 @@ CONFIG_PLATFORM_EC_MKBP_USE_GPIO_AND_HOST_EVENT=y
 # Temperature sensor support
 CONFIG_PLATFORM_EC_TEMP_SENSOR=y
 CONFIG_PLATFORM_EC_THERMISTOR=y
-CONFIG_PLATFORM_EC_TEMP_SENSOR_POWER=y
 CONFIG_PLATFORM_EC_TEMP_SENSOR_FIRST_READ_DELAY=y
 
 # CBI EEPROM support
@@ -115,14 +115,11 @@ CONFIG_PLATFORM_EC_USB_PID=0x505a
 CONFIG_PLATFORM_EC_USB_PD_USB4=n
 CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=n
 
-# TODO(b/216085548): configure USB retimers
 CONFIG_PLATFORM_EC_USB_MUX_RUNTIME_CONFIG=y
 CONFIG_PLATFORM_EC_USB_MUX_VIRTUAL=y
 # ADL integrated muxes are slow: unblock PD
 CONFIG_PLATFORM_EC_USB_MUX_TASK=y
 CONFIG_PLATFORM_EC_BC12_DETECT_PI3USB9201=y
-# TODO(b/226411332): fix single task USB_CHG for Nissa
-CONFIG_PLATFORM_EC_USB_CHARGER_SINGLE_TASK=n
 
 # USB-C TCPC and PPC standard options
 CONFIG_PLATFORM_EC_USB_PD_TCPC_LOW_POWER=y
@@ -135,6 +132,8 @@ CONFIG_PLATFORM_EC_USB_PORT_ENABLE_DYNAMIC=y
 # either SLGC55545 or PI5USB2546.
 CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART=y
 CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_CDP_SDP_ONLY=y
+CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_DEFAULT_CDP=y
+CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_INVERTED=y
 
 # Battery support
 CONFIG_PLATFORM_EC_BATTERY=y
@@ -146,8 +145,13 @@ CONFIG_PLATFORM_EC_BATTERY_REVIVE_DISCONNECT=y
 
 # Charger support
 CONFIG_PLATFORM_EC_CHARGER=y
-CONFIG_PLATFORM_EC_OCPC=y
 CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10
 CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=10
 CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y
 CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC_CHARGER=y
+
+# Dynamically select PD voltage to maximize charger efficiency
+CONFIG_PLATFORM_EC_USB_PD_DPS=y
+# Reduce logging so that state transitions do not cause protocol issues
+# pd dump [1-3] can be used to increase the debugging level
+CONFIG_PLATFORM_EC_USB_PD_INITIAL_DEBUG_LEVEL=0
diff --git a/zephyr/projects/nissa/prj_craask.conf b/zephyr/projects/nissa/prj_craask.conf
deleted file mode 100644
index bc0ac84307..0000000000
--- a/zephyr/projects/nissa/prj_craask.conf
+++ /dev/null
@@ -1,39 +0,0 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# EC chip configuration: NPCX993
-CONFIG_BOARD_CRAASK=y
-CONFIG_CROS_FLASH_NPCX=y
-CONFIG_CROS_SYSTEM_NPCX=y
-CONFIG_SOC_SERIES_NPCX9=y
-CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API=y
-CONFIG_SYSCON=y
-CONFIG_TACH_NPCX=n
-
-# Sensor drivers
-CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSO=y
-CONFIG_PLATFORM_EC_ACCEL_LIS2DW12=y
-
-# Keyboard
-CONFIG_CROS_KB_RAW_NPCX=y
-CONFIG_PLATFORM_EC_KBLIGHT_ENABLE_PIN=y
-
-# TCPC+PPC: both C0 and C1 (if present) are RAA489000
-CONFIG_PLATFORM_EC_USB_PD_TCPM_RAA489000=y
-CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_TCPC=y
-CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y
-CONFIG_PLATFORM_EC_USB_PD_TCPC_LPM_EXIT_DEBOUNCE_US=100000
-# RAA489000 uses TCPCI but not a separate PPC, so custom function is required
-CONFIG_PLATFORM_EC_USB_PD_5V_EN_CUSTOM=y
-# type C port 1 redriver
-CONFIG_PLATFORM_EC_USBC_RETIMER_ANX7483=y
-
-# Charger driver and configuration
-CONFIG_PLATFORM_EC_CHARGER_RAA489000=y
-CONFIG_PLATFORM_EC_OCPC_DEF_RBATT_MOHMS=22
-
-# VSENSE: PP3300_S5 & PP1050_PROC
-CONFIG_ADC_CMP_NPCX=y
-CONFIG_SENSOR=y
-CONFIG_SENSOR_SHELL=n
diff --git a/zephyr/projects/nissa/prj_nereid.conf b/zephyr/projects/nissa/prj_it8xxx2.conf
index 4b0db30556..4d026a447f 100644
--- a/zephyr/projects/nissa/prj_nereid.conf
+++ b/zephyr/projects/nissa/prj_it8xxx2.conf
@@ -1,12 +1,17 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
-# EC chip configuration: IT83102
-CONFIG_BOARD_NEREID=y
 CONFIG_CROS_FLASH_IT8XXX2=y
 CONFIG_CROS_SYSTEM_IT8XXX2=y
 CONFIG_ESPI_IT8XXX2=y
+CONFIG_FPU=y
+# rv32iafc/ilp32f is not supported by the toolchain, so use soft-float
+CONFIG_FLOAT_HARD=n
+
+# EC performance is bad; limiting sensor data rate helps keep it from degrading
+# so much that it causes problems. b/240485526, b/230818312
+CONFIG_PLATFORM_EC_MAX_SENSOR_FREQ_MILLIHZ=100000
 
 # Allow more time for the charger to stabilise
 CONFIG_PLATFORM_EC_POWER_BUTTON_INIT_TIMEOUT=5
@@ -24,15 +29,10 @@ CONFIG_TASK_HOSTCMD_STACK_SIZE=1280
 CONFIG_TASK_MOTIONSENSE_STACK_SIZE=1280
 CONFIG_TASK_PD_INT_STACK_SIZE=1280
 
-# Sensor drivers
-CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y
-CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y
-CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y
-
 # TCPC+PPC: ITE on-chip for C0, PS8745 for optional C1
 CONFIG_PLATFORM_EC_USB_PD_TCPM_ITE_ON_CHIP=y
 CONFIG_PLATFORM_EC_USB_PD_TCPM_DRIVER_IT8XXX2=y
-CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8815=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8745=y
 CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_CHARGER=y
 # SM5803 controls power path on both ports
 CONFIG_PLATFORM_EC_USB_PD_5V_CHARGER_CTRL=y
@@ -48,11 +48,12 @@ CONFIG_PLATFORM_EC_USB_PD_DISCHARGE=n
 CONFIG_PLATFORM_EC_USB_PD_STARTUP_DELAY_MS=2000
 
 # Charger driver and configuration
+CONFIG_PLATFORM_EC_OCPC=y
 CONFIG_PLATFORM_EC_CHARGER_SM5803=y
 CONFIG_PLATFORM_EC_OCPC_DEF_RBATT_MOHMS=21
+CONFIG_PLATFORM_EC_PD_MAX_VOLTAGE_MV=15000
 
 # VSENSE: PP3300_S5 & PP1050_PROC
 CONFIG_VCMP_IT8XXX2=y
 CONFIG_SENSOR=y
 CONFIG_SENSOR_SHELL=n
-CONFIG_TACH_IT8XXX2=n
diff --git a/zephyr/projects/nissa/prj_nivviks.conf b/zephyr/projects/nissa/prj_nivviks.conf
deleted file mode 100644
index 1c474823d9..0000000000
--- a/zephyr/projects/nissa/prj_nivviks.conf
+++ /dev/null
@@ -1,40 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# EC chip configuration: NPCX993
-CONFIG_BOARD_NIVVIKS=y
-CONFIG_CROS_FLASH_NPCX=y
-CONFIG_CROS_SYSTEM_NPCX=y
-CONFIG_SOC_SERIES_NPCX9=y
-CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API=y
-CONFIG_SYSCON=y
-CONFIG_TACH_NPCX=y
-CONFIG_SHELL_BACKEND_SERIAL_RX_RING_BUFFER_SIZE=256
-
-# Sensor drivers
-CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSO=y
-CONFIG_PLATFORM_EC_ACCEL_LIS2DW12=y
-
-# Keyboard
-CONFIG_CROS_KB_RAW_NPCX=y
-CONFIG_PLATFORM_EC_KBLIGHT_ENABLE_PIN=y
-
-# TCPC+PPC: both C0 and C1 (if present) are RAA489000
-CONFIG_PLATFORM_EC_USB_PD_TCPM_RAA489000=y
-CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_TCPC=y
-CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y
-CONFIG_PLATFORM_EC_USB_PD_TCPC_LPM_EXIT_DEBOUNCE_US=100000
-# RAA489000 uses TCPCI but not a separate PPC, so custom function is required
-CONFIG_PLATFORM_EC_USB_PD_5V_EN_CUSTOM=y
-# type C port 1 redriver
-CONFIG_PLATFORM_EC_USBC_RETIMER_ANX7483=y
-
-# Charger driver and configuration
-CONFIG_PLATFORM_EC_CHARGER_RAA489000=y
-CONFIG_PLATFORM_EC_OCPC_DEF_RBATT_MOHMS=22
-
-# VSENSE: PP3300_S5 & PP1050_PROC
-CONFIG_ADC_CMP_NPCX=y
-CONFIG_SENSOR=y
-CONFIG_SENSOR_SHELL=n
diff --git a/zephyr/projects/nissa/prj_pujjo.conf b/zephyr/projects/nissa/prj_npcx.conf
index e7e9cbd357..4e76fbbbe1 100644
--- a/zephyr/projects/nissa/prj_pujjo.conf
+++ b/zephyr/projects/nissa/prj_npcx.conf
@@ -1,9 +1,8 @@
-# Copyright 2022 The ChromiumOS Authors.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 # EC chip configuration: NPCX993
-CONFIG_BOARD_PUJJO=y
 CONFIG_CROS_FLASH_NPCX=y
 CONFIG_CROS_SYSTEM_NPCX=y
 CONFIG_SOC_SERIES_NPCX9=y
@@ -12,13 +11,15 @@ CONFIG_SYSCON=y
 CONFIG_TACH_NPCX=y
 CONFIG_SHELL_BACKEND_SERIAL_RX_RING_BUFFER_SIZE=256
 
-# Sensor drivers
-CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSO=y
+# Common sensor drivers
 CONFIG_PLATFORM_EC_ACCEL_LIS2DW12=y
 
 # Keyboard
 CONFIG_CROS_KB_RAW_NPCX=y
 CONFIG_PLATFORM_EC_KBLIGHT_ENABLE_PIN=y
+# Ensure recovery key combination (esc+refresh+power) is reliable
+CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI3=y
+CONFIG_PLATFORM_EC_KEYBOARD_REFRESH_ROW3=y
 
 # TCPC+PPC: both C0 and C1 (if present) are RAA489000
 CONFIG_PLATFORM_EC_USB_PD_TCPM_RAA489000=y
@@ -30,6 +31,10 @@ CONFIG_PLATFORM_EC_USB_PD_5V_EN_CUSTOM=y
 # type C port 1 redriver
 CONFIG_PLATFORM_EC_USBC_RETIMER_ANX7483=y
 
+# FRS enable
+CONFIG_PLATFORM_EC_USB_PD_FRS=y
+CONFIG_PLATFORM_EC_USB_PD_FRS_TCPC=y
+
 # Charger driver and configuration
 CONFIG_PLATFORM_EC_CHARGER_RAA489000=y
 CONFIG_PLATFORM_EC_OCPC_DEF_RBATT_MOHMS=22
diff --git a/zephyr/projects/nissa/pujjo/cbi.dts b/zephyr/projects/nissa/pujjo/cbi.dts
new file mode 100644
index 0000000000..b5ba92bd9e
--- /dev/null
+++ b/zephyr/projects/nissa/pujjo/cbi.dts
@@ -0,0 +1,190 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	/* Pujjo-specific fw_config fields. */
+	nissa-fw-config {
+		/*
+		 * FW_CONFIG field to enable KB back light or not.
+		 */
+		kb-bl {
+			enum-name = "FW_KB_BL";
+			start = <3>;
+			size = <1>;
+
+			no-kb-bl {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_KB_BL_NOT_PRESENT";
+				value = <0>;
+			};
+			kb-bl-present {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_KB_BL_PRESENT";
+				value = <1>;
+			};
+		};
+
+		/*
+		 * FW_CONFIG field for KB PWB present or not.
+		 */
+		kb-pwb {
+			enum-name = "FW_KB_PWB";
+			start = <4>;
+			size = <1>;
+
+			no-kb-pwb {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_KB_PWB_NOT_PRESENT";
+				value = <0>;
+			};
+			kb-pwb-present {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_KB_PWB_PRESENT";
+				value = <1>;
+			};
+		};
+
+		/*
+		 * FW_CONFIG field for tablet present or not.
+		 */
+		tablet {
+			enum-name = "FW_TABLET";
+			start = <5>;
+			size = <1>;
+
+			no-tablet {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_TABLET_NOT_PRESENT";
+				value = <0>;
+			};
+			tablet-present {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_TABLET_PRESENT";
+				value = <1>;
+			};
+		};
+
+		/*
+		 * FW_CONFIG field for LTE board present or not.
+		 *
+		 *	start = <6>;
+		 *	size = <1>;
+		 */
+
+		/*
+		 * FW_CONFIG field for SD card present or not.
+		 *
+		 *	start = <7>;
+		 *	size = <1>;
+		 */
+
+		/*
+		 * FW_CONFIG field for pen present or not.
+		 */
+		pen {
+			enum-name = "FW_PEN";
+			start = <8>;
+			size = <1>;
+
+			no-pen {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_PEN_NOT_PRESENT";
+				value = <0>;
+			};
+			pen-present {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_PEN_PRESENT";
+				value = <1>;
+			};
+		};
+
+		/*
+		 * FW_CONFIG field for WF camera present or not.
+		 *
+		 *	start = <9>;
+		 *	size = <1>;
+		 */
+
+		/*
+		 * FW_CONFIG field for multiple thermal table.
+		 */
+		therm-table {
+			enum-name = "THERM_TABLE";
+			start = <10>;
+			size = <2>;
+
+			therm-table-1 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "THERM_TABLE_1";
+				value = <1>;
+			};
+		};
+
+		/*
+		 * FW_CONFIG field for multiple audio module.
+		 *
+		 *	start = <12>;
+		 *	size = <3>;
+		 */
+
+		/*
+		 * FW_CONFIG field for EXT_VR.
+		 *
+		 *	start = <15>;
+		 *	size = <1>;
+		 */
+
+		/*
+		 * FW_CONFIG field for multiple wi-fi SAR.
+		 *
+		 *	start = <16>;
+		 *	size = <2>;
+		 */
+	};
+
+	/* Pujjo-specific ssfc fields. */
+	cbi-ssfc {
+		compatible = "named-cbi-ssfc";
+		/*
+		 * SSFC field to identify BASE motion sensor.
+		 */
+		base-sensor {
+			enum-name = "BASE_SENSOR";
+			size = <2>;
+
+			base_sensor_0: bmi323 {
+				compatible = "named-cbi-ssfc-value";
+				status = "okay";
+				value = <0>;
+				default;
+			};
+			base_sensor_1: lsm6dsm {
+				compatible = "named-cbi-ssfc-value";
+				status = "okay";
+				value = <1>;
+			};
+		};
+
+		/*
+		 * SSFC field to identify LID motion sensor.
+		 */
+		lid-sensor {
+			enum-name = "LID_SENSOR";
+			size = <2>;
+
+			lid_sensor_0: bma422 {
+				compatible = "named-cbi-ssfc-value";
+				status = "okay";
+				value = <0>;
+				default;
+			};
+			lid_sensor_1: lis2dw12 {
+				compatible = "named-cbi-ssfc-value";
+				status = "okay";
+				value = <1>;
+			};
+		};
+	};
+};
diff --git a/zephyr/projects/nissa/nivviks_generated.dts b/zephyr/projects/nissa/pujjo/generated.dts
index 1c429ae32c..e6dd7bf5a3 100644
--- a/zephyr/projects/nissa/nivviks_generated.dts
+++ b/zephyr/projects/nissa/pujjo/generated.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -11,25 +11,25 @@
 		compatible = "named-adc-channels";
 
 		adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc {
-			label = "EC_VSENSE_PP1050_PROC";
 			enum-name = "ADC_PP1050_PROC";
 			io-channels = <&adc0 4>;
 		};
 		adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 {
-			label = "EC_VSENSE_PP3300_S5";
 			enum-name = "ADC_PP3300_S5";
 			io-channels = <&adc0 6>;
 		};
 		adc_temp_sensor_1: temp_sensor_1 {
-			label = "TEMP_SENSOR_1";
 			enum-name = "ADC_TEMP_SENSOR_1";
 			io-channels = <&adc0 0>;
 		};
 		adc_temp_sensor_2: temp_sensor_2 {
-			label = "TEMP_SENSOR_2";
 			enum-name = "ADC_TEMP_SENSOR_2";
 			io-channels = <&adc0 1>;
 		};
+		adc_temp_sensor_3: temp_sensor_3 {
+			enum-name = "ADC_TEMP_SENSOR_3";
+			io-channels = <&adc0 10>;
+		};
 	};
 
 	named-gpios {
@@ -71,7 +71,7 @@
 			gpios = <&gpio1 7 (GPIO_OUTPUT_LOW | GPIO_ACTIVE_LOW)>;
 		};
 		gpio_ec_pch_wake_odl: ec_pch_wake_odl {
-			gpios = <&gpiob 0 GPIO_ODR_LOW>;
+			gpios = <&gpio8 0 GPIO_ODR_LOW>;
 		};
 		gpio_ec_prochot_odl: ec_prochot_odl {
 			gpios = <&gpiof 1 GPIO_ODR_HIGH>;
@@ -83,7 +83,7 @@
 			gpios = <&gpioe 4 GPIO_OUTPUT>;
 		};
 		gpio_ec_soc_int_odl: ec_soc_int_odl {
-			gpios = <&gpio8 0 GPIO_ODR_HIGH>;
+			gpios = <&gpiob 0 GPIO_ODR_HIGH>;
 			enum-name = "GPIO_EC_INT_L";
 		};
 		gpio_ec_soc_pch_pwrok_od: ec_soc_pch_pwrok_od {
@@ -194,11 +194,11 @@
 			gpios = <&gpioe 3 GPIO_INPUT>;
 		};
 		gpio_voldn_btn_odl: voldn_btn_odl {
-			gpios = <&gpioa 2 GPIO_INPUT_PULL_UP>;
+			gpios = <&gpio9 3 GPIO_INPUT_PULL_UP>;
 			enum-name = "GPIO_VOLUME_DOWN_L";
 		};
 		gpio_volup_btn_odl: volup_btn_odl {
-			gpios = <&gpio9 3 GPIO_INPUT_PULL_UP>;
+			gpios = <&gpioa 2 GPIO_INPUT_PULL_UP>;
 			enum-name = "GPIO_VOLUME_UP_L";
 		};
 	};
@@ -208,23 +208,19 @@
 
 		i2c_ec_i2c_eeprom: ec_i2c_eeprom {
 			i2c-port = <&i2c0_0>;
-			enum-name = "I2C_PORT_EEPROM";
+			enum-names = "I2C_PORT_EEPROM";
 		};
 		i2c_ec_i2c_sensor: ec_i2c_sensor {
 			i2c-port = <&i2c1_0>;
-			enum-name = "I2C_PORT_SENSOR";
+			enum-names = "I2C_PORT_SENSOR";
 		};
 		i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 {
 			i2c-port = <&i2c3_0>;
-			enum-name = "I2C_PORT_USB_C0_TCPC";
-		};
-		i2c_ec_i2c_sub_usb_c1: ec_i2c_sub_usb_c1 {
-			i2c-port = <&i2c5_1>;
-			enum-name = "I2C_PORT_USB_C1_TCPC";
+			enum-names = "I2C_PORT_USB_C0_TCPC";
 		};
 		i2c_ec_i2c_batt: ec_i2c_batt {
 			i2c-port = <&i2c7_0>;
-			enum-name = "I2C_PORT_BATTERY";
+			enum-names = "I2C_PORT_BATTERY";
 		};
 	};
 };
@@ -234,7 +230,8 @@
 	pinctrl-0 = <&adc0_chan0_gp45
 		     &adc0_chan1_gp44
 		     &adc0_chan4_gp41
-		     &adc0_chan6_gp34>;
+		     &adc0_chan6_gp34
+		     &adc0_chan10_gpe0>;
 	pinctrl-names = "default";
 };
 
@@ -257,12 +254,6 @@
 	pinctrl-names = "default";
 };
 
-&i2c5_1 {
-	status = "okay";
-	pinctrl-0 = <&i2c5_1_sda_scl_gpf4_f5>;
-	pinctrl-names = "default";
-};
-
 &i2c7_0 {
 	status = "okay";
 	pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>;
@@ -281,10 +272,6 @@
 	status = "okay";
 };
 
-&i2c_ctrl5 {
-	status = "okay";
-};
-
 &i2c_ctrl7 {
 	status = "okay";
 };
diff --git a/zephyr/projects/nissa/nivviks_keyboard.dts b/zephyr/projects/nissa/pujjo/keyboard.dts
index 71cb49ce65..00610e4e18 100644
--- a/zephyr/projects/nissa/nivviks_keyboard.dts
+++ b/zephyr/projects/nissa/pujjo/keyboard.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,13 +6,13 @@
 / {
 	kblight {
 		compatible = "cros-ec,kblight-pwm";
-		pwms = <&pwm6 6 PWM_KHZ(10) PWM_POLARITY_NORMAL>;
-		frequency = <10000>;
+		pwms = <&pwm6 6 PWM_HZ(2400) PWM_POLARITY_NORMAL>;
 	};
 };
 
 &pwm6 {
 	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
 	pinctrl-0 = <&pwm6_gpc0>;
 	pinctrl-names = "default";
 };
diff --git a/zephyr/projects/nissa/pujjo/motionsense.dts b/zephyr/projects/nissa/pujjo/motionsense.dts
new file mode 100644
index 0000000000..d5719ef08f
--- /dev/null
+++ b/zephyr/projects/nissa/pujjo/motionsense.dts
@@ -0,0 +1,233 @@
+/* Copyright 2022 The ChromiumOS Authors.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/motionsense/utils.h>
+
+
+/ {
+	aliases {
+		/*
+		 * Interrupt bindings for sensor devices.
+		 */
+		bmi3xx-int = &base_accel;
+		lsm6dsm-int = &base_accel;
+		lis2dw12-int = &lid_accel;
+	};
+
+	/*
+	 * Declare mutexes used by sensor drivers.
+	 * A mutex node is used to create an instance of mutex_t.
+	 * A mutex node is referenced by a sensor node if the
+	 * corresponding sensor driver needs to use the
+	 * instance of the mutex.
+	 */
+	motionsense-mutex {
+		compatible = "cros-ec,motionsense-mutex";
+		lid_mutex: lid-mutex {
+		};
+
+		base_mutex: base-mutex {
+		};
+	};
+
+	/* Rotation matrix used by drivers. */
+	motionsense-rotation-ref {
+		compatible = "cros-ec,motionsense-rotation-ref";
+		lid_rot_ref: lid-rotation-ref {
+			mat33 = <0 (-1) 0
+				 (-1) 0 0
+				 0 0 (-1)>;
+		};
+
+		base_rot_ref: base-rotation-ref {
+			mat33 = <0 1 0
+				 (-1) 0 0
+				 0 0 1>;
+		};
+	};
+
+	/*
+	 * Driver specific data. A driver-specific data can be shared with
+	 * different motion sensors while they are using the same driver.
+	 *
+	 * If a node's compatible starts with "cros-ec,accelgyro-", it is for
+	 * a common structure defined in accelgyro.h.
+	 * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for
+	 * "struct als_drv_data_t" in accelgyro.h
+	 */
+	motionsense-sensor-data {
+		bmi323_data: bmi323-drv-data {
+			compatible = "cros-ec,drvdata-bmi3xx";
+			status = "okay";
+		};
+
+		lsm6dsm_data_accel: lsm6dsm-accel-drv-data {
+			compatible = "cros-ec,drvdata-lsm6dsm";
+			status = "okay";
+		};
+
+		lsm6dsm_data_gyro: lsm6dsm-gyro-drv-data {
+			compatible = "cros-ec,drvdata-lsm6dsm";
+			status = "okay";
+		};
+
+		bma422_data: bma422-drv-data {
+			compatible = "cros-ec,drvdata-bma4xx";
+			status = "okay";
+		};
+
+		lis2dw12_data: lis2dw12-drv-data {
+			compatible = "cros-ec,drvdata-lis2dw12";
+			status = "okay";
+		};
+	};
+
+	/*
+	 * List of motion sensors that creates motion_sensors array.
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
+	 * motion sensor IDs for lid angle calculation.
+	 * TODO(b/238139272): The first entries of the array must be
+	 * accelerometers,then gyroscope. Fix this dependency in the DTS
+	 * processing which makes the devicetree entries independent.
+	 */
+	motionsense-sensor {
+		lid_accel: lid-accel {
+			compatible = "cros-ec,bma4xx";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&lid_mutex>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&lid_rot_ref>;
+			default-range = <2>;
+			drv-data = <&bma422_data>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_accel: base-accel {
+			compatible = "cros-ec,bmi3xx-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&bmi323_data>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_gyro: base-gyro {
+			compatible = "cros-ec,bmi3xx-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&bmi323_data>;
+		};
+	};
+
+	motionsense-sensor-alt {
+		alt_lid_accel: alt-lid-accel {
+			compatible = "cros-ec,lis2dw12";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&lid_mutex>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&lid_rot_ref>;
+			default-range = <2>;
+			drv-data = <&lis2dw12_data>;
+			i2c-spi-addr-flags = "LIS2DWL_ADDR1_FLAGS";
+			alternate-for = <&lid_accel>;
+			alternate-ssfc-indicator = <&lid_sensor_1>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		alt_base_accel: alt-base-accel {
+			compatible = "cros-ec,lsm6dsm-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&lsm6dsm_data_accel>;
+			alternate-for = <&base_accel>;
+			alternate-ssfc-indicator = <&base_sensor_1>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+					ec-rate = <(100 * USEC_PER_MSEC)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+					ec-rate = <0>;
+				};
+			};
+		};
+
+		alt_base_gyro: alt-base-gyro {
+			compatible = "cros-ec,lsm6dsm-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&lsm6dsm_data_gyro>;
+			alternate-for = <&base_gyro>;
+			alternate-ssfc-indicator = <&base_sensor_1>;
+		};
+	};
+
+	motionsense-sensor-info {
+		compatible = "cros-ec,motionsense-sensor-info";
+
+		/*
+		 * list of GPIO interrupts that have to
+		 * be enabled at initial stage
+		 */
+		sensor-irqs = <&int_imu>;
+		/* list of sensors in force mode */
+		accel-force-mode-sensors = <&lid_accel>;
+	};
+};
diff --git a/zephyr/projects/nissa/pujjo_overlay.dts b/zephyr/projects/nissa/pujjo/overlay.dts
index c185d46e11..60b3b60003 100644
--- a/zephyr/projects/nissa/pujjo_overlay.dts
+++ b/zephyr/projects/nissa/pujjo/overlay.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,8 +19,20 @@
 	};
 
 	batteries {
-		default_battery: lgc {
-			compatible = "lgc,ap18c8k", "battery-smart";
+		default_battery: smp {
+			compatible = "smp,l22m3pg0", "battery-smart";
+		};
+		smp_l22m3pg1 {
+			compatible = "smp,l22m3pg1", "battery-smart";
+		};
+		sunwoda_l22d3pg0 {
+			compatible = "sunwoda,l22d3pg0", "battery-smart";
+		};
+		sunwoda_l22d3pg1 {
+			compatible = "sunwoda,l22d3pg1", "battery-smart";
+		};
+		celxpert_l22c3pg0 {
+			compatible = "celxpert,l22c3pg0", "battery-smart";
 		};
 	};
 
@@ -58,7 +70,7 @@
 		int_imu: ec_imu {
 			irq-pin = <&gpio_imu_int_l>;
 			flags = <GPIO_INT_EDGE_FALLING>;
-			handler = "lsm6dso_interrupt";
+			handler = "motion_interrupt";
 		};
 		int_vol_down: vol_down {
 			irq-pin = <&gpio_voldn_btn_odl>;
@@ -75,36 +87,35 @@
 			flags = <GPIO_INT_EDGE_FALLING>;
 			handler = "usb_interrupt";
 		};
-		int_usb_c1: usb_c1 {
-			irq-pin = <&gpio_sb_1>;
-			flags = <GPIO_INT_EDGE_FALLING>;
-			handler = "usb_interrupt";
-		};
 	};
 
 	named-gpios {
-		gpio_sb_1: sb_1 {
-			gpios = <&gpio0 2 GPIO_PULL_UP>;
-			no-auto-init;
-		};
-
 		gpio_sb_2: sb_2 {
 			gpios = <&gpiod 4 GPIO_OUTPUT>;
 			no-auto-init;
 		};
 
 		gpio_sb_3: sb_3 {
-			gpios = <&gpiof 4 GPIO_OPEN_DRAIN>;
+			gpios = <&gpiof 5 GPIO_OPEN_DRAIN>;
 			no-auto-init;
 		};
 		gpio_sb_4: sb_4 {
-			gpios = <&gpiof 5 GPIO_INPUT>;
+			gpios = <&gpiof 4 GPIO_INPUT>;
 			no-auto-init;
 		};
 		gpio_fan_enable: fan-enable {
 			gpios = <&gpio6 3 GPIO_OUTPUT>;
 			no-auto-init;
 		};
+		gpio_power_led: power_led {
+			gpios = <&gpioc 2 GPIO_OUTPUT_LOW>;
+		};
+		gpio_led_1_odl: led_1_odl {
+			gpios = <&gpioc 4 GPIO_OUTPUT_LOW>;
+		};
+		gpio_led_2_odl: led_2_odl {
+			gpios = <&gpioc 3 GPIO_OUTPUT_LOW>;
+		};
 	};
 
 	/*
@@ -112,12 +123,6 @@
 	 */
 	aliases {
 		/*
-		 * Input GPIO when used with type-C port 1
-		 * Output when used with HDMI sub-board
-		 */
-		gpio-usb-c1-int-odl = &gpio_sb_1;
-		gpio-en-rails-odl = &gpio_sb_1;
-		/*
 		 * Sub-board with type A USB, enable.
 		 */
 		gpio-en-usb-a1-vbus = &gpio_sb_2;
@@ -132,32 +137,50 @@
 		gpio-en-sub-s5-rails = &gpio_sb_2;
 	};
 
+	temp_cpu: cpu {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_1>;
+	};
+	temp_ddr: ddr {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_2>;
+	};
+	temp_ambient: ambient {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_3>;
+	};
+
 	named-temp-sensors {
-		memory {
-			compatible = "cros-ec,temp-sensor-thermistor",
-				     "cros-ec,temp-sensor";
-			thermistor = <&thermistor_3V3_51K1_47K_4050B>;
-			label = "DDR and SOC";
-			enum-name = "TEMP_SENSOR_1";
+		compatible = "cros-ec,temp-sensors";
+		cpu {
 			temp_fan_off = <35>;
 			temp_fan_max = <60>;
-			temp_host_high = <85>;
-			temp_host_halt = <90>;
-			temp_host_release_high = <80>;
-			adc = <&adc_temp_sensor_1>;
+			temp_host_high = <90>;
+			temp_host_halt = <100>;
+			temp_host_release_high = <85>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_cpu>;
 		};
-		charger {
-			compatible = "cros-ec,temp-sensor-thermistor",
-				     "cros-ec,temp-sensor";
-			thermistor = <&thermistor_3V3_51K1_47K_4050B>;
-			label = "Charger";
-			enum-name = "TEMP_SENSOR_2";
+		ddr {
 			temp_fan_off = <35>;
 			temp_fan_max = <60>;
-			temp_host_high = <85>;
-			temp_host_halt = <90>;
-			temp_host_release_high = <80>;
-			adc = <&adc_temp_sensor_2>;
+			temp_host_high = <90>;
+			temp_host_halt = <100>;
+			temp_host_release_high = <85>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_ddr>;
+		};
+		ambient {
+			temp_fan_off = <35>;
+			temp_fan_max = <60>;
+			temp_host_high = <90>;
+			temp_host_halt = <100>;
+			temp_host_release_high = <85>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_ambient>;
 		};
 	};
 
@@ -183,59 +206,18 @@
 		port0@0 {
 			compatible = "named-usbc-port";
 			reg = <0>;
-			bc12 {
-				compatible = "pericom,pi3usb9201";
-				port = <&i2c_ec_i2c_usb_c0>;
-				/*
-				 * BC1.2 interrupt is shared with TCPC, so
-				 * IRQ is not specified here and handled by
-				 * usb_c0_interrupt.
-				 */
-			};
-			chg {
-				compatible = "intersil,isl923x";
-				status = "okay";
-				port = <&i2c_ec_i2c_usb_c0>;
+			bc12 = <&bc12_port0>;
+			chg = <&chg_port0>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_0>;
 			};
-			usb-muxes = <&virtual_mux_0>;
 		};
 		port0-muxes {
 			virtual_mux_0: virtual-mux-0 {
 				compatible = "cros-ec,usbc-mux-virtual";
 			};
 		};
-		/*
-		 * TODO(b:211693800): port1 may not be present on some
-		 * sub-boards.
-		 */
-		port1@1 {
-			compatible = "named-usbc-port";
-			reg = <1>;
-			bc12 {
-				compatible = "pericom,pi3usb9201";
-				port = <&i2c_ec_i2c_sub_usb_c1>;
-			};
-			chg {
-				compatible = "intersil,isl923x";
-				status = "okay";
-				port = <&i2c_ec_i2c_sub_usb_c1>;
-			};
-			/*
-			 * Some sub-boards may disable all usb muxes in chain
-			 * except virtual_mux_1
-			 */
-			usb-muxes = <&virtual_mux_1 &anx7483_mux_1>;
-		};
-		port1-muxes {
-			virtual_mux_1: virtual-mux-1 {
-				compatible = "cros-ec,usbc-mux-virtual";
-			};
-			anx7483_mux_1: anx7483-mux-1 {
-				compatible = "analogix,anx7483";
-				port = <&i2c_ec_i2c_sub_usb_c1>;
-				i2c-addr-flags = "ANX7483_I2C_ADDR0_FLAGS";
-			};
-		};
 	};
 
 	fans {
@@ -243,7 +225,6 @@
 
 		fan_0 {
 			pwms = <&pwm5 5 PWM_KHZ(1) PWM_POLARITY_NORMAL>;
-			pwm-frequency = <1000>;
 			rpm_min = <2200>;
 			rpm_start = <2200>;
 			rpm_max = <4200>;
@@ -291,7 +272,6 @@
 	cbi_eeprom: eeprom@50 {
 		compatible = "atmel,at24";
 		reg = <0x50>;
-		label = "EEPROM_CBI";
 		size = <2048>;
 		pagesize = <16>;
 		address-width = <8>;
@@ -307,11 +287,23 @@
 &i2c3_0 {
 	label = "I2C_USB_C0_TCPC";
 	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
-};
 
-&i2c5_1 {
-	label = "I2C_SUB_C1_TCPC";
-	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+	bc12_port0: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+		/*
+		 * BC1.2 interrupt is shared with TCPC, so
+		 * IRQ is not specified here and handled by
+		 * usb_c0_interrupt.
+		 */
+	};
+
+	chg_port0: isl923x@9 {
+		compatible = "intersil,isl923x";
+		status = "okay";
+		reg = <0x9>;
+	};
 };
 
 &i2c7_0 {
@@ -325,6 +317,7 @@
 
 &pwm5 {
 	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
 	pinctrl-0 = <&pwm5_gpb7>;
 	pinctrl-names = "default";
 };
@@ -345,3 +338,13 @@
 	pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>;
 	pinctrl-names = "default";
 };
+
+/*
+ * Declare GPIOs that have leakage current caused by board issues here. NPCX ec
+ * will disable their input buffers before entering deep sleep and restore them
+ * after waking up automatically for better power consumption.
+ */
+&power_leakage_io {
+	leak-gpios = <&gpioa 4 0
+		      &gpiof 1 0>;
+};
diff --git a/zephyr/projects/nissa/pujjo_power_signals.dts b/zephyr/projects/nissa/pujjo/power_signals.dts
index 91876f0402..1d2b23069d 100644
--- a/zephyr/projects/nissa/pujjo_power_signals.dts
+++ b/zephyr/projects/nissa/pujjo/power_signals.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/nissa/pujjo/prj.conf b/zephyr/projects/nissa/pujjo/prj.conf
new file mode 100644
index 0000000000..691b75a5d7
--- /dev/null
+++ b/zephyr/projects/nissa/pujjo/prj.conf
@@ -0,0 +1,23 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_BOARD_PUJJO=y
+
+# Sensor drivers
+CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSM=y
+CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y
+
+# Increase PD max power from default
+CONFIG_PLATFORM_EC_PD_MAX_POWER_MW=65000
+CONFIG_PLATFORM_EC_PD_MAX_CURRENT_MA=3250
+
+# LED
+CONFIG_PLATFORM_EC_LED_PWM=n
+CONFIG_PLATFORM_EC_LED_COMMON=y
+
+# CBI
+CONFIG_PLATFORM_EC_BYPASS_CBI_EEPROM_WP_CHECK=y
+CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y
\ No newline at end of file
diff --git a/zephyr/projects/nissa/pujjo/pujjo_vif.xml b/zephyr/projects/nissa/pujjo/pujjo_vif.xml
new file mode 100644
index 0000000000..8e8f791c0c
--- /dev/null
+++ b/zephyr/projects/nissa/pujjo/pujjo_vif.xml
@@ -0,0 +1,350 @@
+<?xml version="1.0" encoding="utf-8"?>

+<vif:VIF xmlns:opt="http://usb.org/VendorInfoFileOptionalContent.xsd" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:vif="http://usb.org/VendorInfoFile.xsd">

+  <vif:VIF_Specification>3.19</vif:VIF_Specification>

+  <vif:VIF_App>

+    <vif:Vendor>USB-IF</vif:Vendor>

+    <vif:Name>VIF Editor</vif:Name>

+    <vif:Version>3.2.4.0</vif:Version>

+  </vif:VIF_App>

+  <vif:Vendor_Name>Google</vif:Vendor_Name>

+  <vif:Model_Part_Number>Pujjo</vif:Model_Part_Number>

+  <vif:Product_Revision>1</vif:Product_Revision>

+  <vif:TID>0</vif:TID>

+  <vif:VIF_Product_Type value="0">Port Product</vif:VIF_Product_Type>

+  <vif:Certification_Type value="0">End Product</vif:Certification_Type>

+  <vif:Product>

+    <!--Product Level Content:-->

+  </vif:Product>

+  <vif:Component>

+    <!--Component 0: Port 0-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;Component-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:Port_Label>0</vif:Port_Label>

+    <vif:Connector_Type value="2">Type-C®</vif:Connector_Type>

+    <vif:USB4_Supported value="false" />

+    <vif:USB_PD_Support value="true" />

+    <vif:PD_Port_Type value="4">DRP</vif:PD_Port_Type>

+    <vif:Type_C_State_Machine value="2">DRP</vif:Type_C_State_Machine>

+    <vif:Port_Battery_Powered value="true" />

+    <vif:BC_1_2_Support value="2">Charging Port</vif:BC_1_2_Support>

+    <vif:Captive_Cable value="false" />

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;General PD-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:PD_Spec_Revision_Major value="3" />

+    <vif:PD_Spec_Revision_Minor value="1" />

+    <vif:PD_Spec_Version_Major value="1" />

+    <vif:PD_Spec_Version_Minor value="3" />

+    <vif:PD_Specification_Revision value="2">Revision 3</vif:PD_Specification_Revision>

+    <vif:SOP_Capable value="true" />

+    <vif:SOP_P_Capable value="true" />

+    <vif:SOP_PP_Capable value="true" />

+    <vif:SOP_P_Debug_Capable value="false" />

+    <vif:SOP_PP_Debug_Capable value="false" />

+    <vif:Manufacturer_Info_Supported_Port value="true" />

+    <vif:Manufacturer_Info_VID_Port value="6353">18D1</vif:Manufacturer_Info_VID_Port>

+    <vif:Manufacturer_Info_PID_Port value="20570">505A</vif:Manufacturer_Info_PID_Port>

+    <vif:Chunking_Implemented_SOP value="true" />

+    <vif:Unchunked_Extended_Messages_Supported value="false" />

+    <vif:Security_Msgs_Supported_SOP value="false" />

+    <vif:Unconstrained_Power value="false" />

+    <vif:Num_Fixed_Batteries value="1" />

+    <vif:Num_Swappable_Battery_Slots value="0" />

+    <vif:ID_Header_Connector_Type_SOP value="2">USB Type-C® Receptacle</vif:ID_Header_Connector_Type_SOP>

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;PD Capabilities-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:USB_Comms_Capable value="true" />

+    <vif:DR_Swap_To_DFP_Supported value="true" />

+    <vif:DR_Swap_To_UFP_Supported value="false" />

+    <vif:VCONN_Swap_To_On_Supported value="true" />

+    <vif:VCONN_Swap_To_Off_Supported value="true" />

+    <vif:Responds_To_Discov_SOP_UFP value="false" />

+    <vif:Responds_To_Discov_SOP_DFP value="true" />

+    <vif:Attempts_Discov_SOP value="true" />

+    <vif:Power_Interruption_Available value="0">No Interruption Possible</vif:Power_Interruption_Available>

+    <vif:Data_Reset_Supported value="false" />

+    <vif:Enter_USB_Supported value="false" />

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;USB Type-C®-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:Type_C_Can_Act_As_Host value="true" />

+    <vif:Type_C_Can_Act_As_Device value="false" />

+    <vif:Type_C_Implements_Try_SRC value="true" />

+    <vif:Type_C_Implements_Try_SNK value="false" />

+    <vif:Type_C_Supports_Audio_Accessory value="false" />

+    <vif:Type_C_Is_VCONN_Powered_Accessory value="false" />

+    <vif:Type_C_Is_Debug_Target_SRC value="true" />

+    <vif:Type_C_Is_Debug_Target_SNK value="true" />

+    <vif:RP_Value value="1">1.5A</vif:RP_Value>

+    <vif:Type_C_Port_On_Hub value="false" />

+    <vif:Type_C_Power_Source value="2">Both</vif:Type_C_Power_Source>

+    <vif:Type_C_Sources_VCONN value="true" />

+    <vif:Type_C_Is_Alt_Mode_Controller value="true" />

+    <vif:Type_C_Is_Alt_Mode_Adapter value="false" />

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;Product Power-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:Product_Total_Source_Power_mW value="15000">15000 mW</vif:Product_Total_Source_Power_mW>

+    <vif:Port_Source_Power_Type value="0">Assured</vif:Port_Source_Power_Type>

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;USB Host-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:Host_Supports_USB_Data value="true" />

+    <vif:Host_Speed value="1">USB 3.2 Gen 1x1</vif:Host_Speed>

+    <vif:Host_Contains_Captive_Retimer value="false" />

+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />

+    <vif:Host_Is_Embedded value="false" />

+    <vif:Host_Suspend_Supported value="true" />

+    <vif:Is_DFP_On_Hub value="false" />

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;Battery Charging 1.2-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:BC_1_2_Charging_Port_Type value="1">CDP</vif:BC_1_2_Charging_Port_Type>

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;PD Source-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:PD_Power_As_Source value="15000">15000 mW</vif:PD_Power_As_Source>

+    <vif:EPR_Supported_As_Src value="false" />

+    <vif:USB_Suspend_May_Be_Cleared value="false" />

+    <vif:Sends_Pings value="false" />

+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="0">FR_Swap not supported</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>

+    <vif:Master_Port value="false" />

+    <vif:Num_Src_PDOs value="1" />

+    <vif:PD_OC_Protection value="true" />

+    <vif:PD_OCP_Method value="0">Over-Current Response</vif:PD_OCP_Method>

+    <!--Bundle: SrcPdoList-->

+    <vif:SrcPdoList>

+      <vif:SrcPDO>

+        <!--Source PDO 1-->

+        <vif:Src_PDO_Supply_Type value="0">Fixed</vif:Src_PDO_Supply_Type>

+        <vif:Src_PDO_Peak_Current value="0">100% IOC</vif:Src_PDO_Peak_Current>

+        <vif:Src_PDO_Voltage value="100">5000 mV</vif:Src_PDO_Voltage>

+        <vif:Src_PDO_Max_Current value="300">3000 mA</vif:Src_PDO_Max_Current>

+        <vif:Src_PD_OCP_OC_Debounce value="0">0 msec</vif:Src_PD_OCP_OC_Debounce>

+        <vif:Src_PD_OCP_OC_Threshold value="300">3000 mA</vif:Src_PD_OCP_OC_Threshold>

+      </vif:SrcPDO>

+    </vif:SrcPdoList>

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;PD Sink-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:PD_Power_As_Sink value="60000">60000 mW</vif:PD_Power_As_Sink>

+    <vif:EPR_Supported_As_Snk value="false" />

+    <vif:No_USB_Suspend_May_Be_Set value="true" />

+    <vif:GiveBack_May_Be_Set value="false" />

+    <vif:Higher_Capability_Set value="false" />

+    <vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source value="0">FR_Swap not supported</vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source>

+    <vif:Num_Snk_PDOs value="3" />

+    <!--Bundle: SnkPdoList-->

+    <vif:SnkPdoList>

+      <vif:SnkPDO>

+        <!--Sink PDO 1-->

+        <vif:Snk_PDO_Supply_Type value="0">Fixed</vif:Snk_PDO_Supply_Type>

+        <vif:Snk_PDO_Voltage value="100">5000 mV</vif:Snk_PDO_Voltage>

+        <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>

+      </vif:SnkPDO>

+      <vif:SnkPDO>

+        <!--Sink PDO 2-->

+        <vif:Snk_PDO_Supply_Type value="1">Battery</vif:Snk_PDO_Supply_Type>

+        <vif:Snk_PDO_Op_Power value="60">15000 mW</vif:Snk_PDO_Op_Power>

+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>

+        <vif:Snk_PDO_Max_Voltage value="400">20000 mV</vif:Snk_PDO_Max_Voltage>

+      </vif:SnkPDO>

+      <vif:SnkPDO>

+        <!--Sink PDO 3-->

+        <vif:Snk_PDO_Supply_Type value="2">Variable</vif:Snk_PDO_Supply_Type>

+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>

+        <vif:Snk_PDO_Max_Voltage value="400">20000 mV</vif:Snk_PDO_Max_Voltage>

+        <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>

+      </vif:SnkPDO>

+    </vif:SnkPdoList>

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;Dual Role-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:Accepts_PR_Swap_As_Src value="true" />

+    <vif:Accepts_PR_Swap_As_Snk value="true" />

+    <vif:Requests_PR_Swap_As_Src value="true" />

+    <vif:Requests_PR_Swap_As_Snk value="true" />

+    <vif:FR_Swap_Supported_As_Initial_Sink value="false" />

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;SOP Discover ID-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:XID_SOP value="0" />

+    <vif:Data_Capable_As_USB_Host_SOP value="true" />

+    <vif:Data_Capable_As_USB_Device_SOP value="false" />

+    <vif:Product_Type_UFP_SOP value="0">Undefined</vif:Product_Type_UFP_SOP>

+    <vif:Product_Type_DFP_SOP value="0">Undefined</vif:Product_Type_DFP_SOP>

+    <vif:DFP_VDO_Port_Number value="0" />

+    <vif:Modal_Operation_Supported_SOP value="false" />

+    <vif:USB_VID_SOP value="6353">18D1</vif:USB_VID_SOP>

+    <vif:PID_SOP value="20570">505A</vif:PID_SOP>

+    <vif:bcdDevice_SOP value="0">0000</vif:bcdDevice_SOP>

+  </vif:Component>

+  <vif:Component>

+    <!--Component 1: Port 1-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;Component-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:Port_Label>1</vif:Port_Label>

+    <vif:Connector_Type value="2">Type-C®</vif:Connector_Type>

+    <vif:USB4_Supported value="false" />

+    <vif:USB_PD_Support value="true" />

+    <vif:PD_Port_Type value="4">DRP</vif:PD_Port_Type>

+    <vif:Type_C_State_Machine value="2">DRP</vif:Type_C_State_Machine>

+    <vif:Port_Battery_Powered value="true" />

+    <vif:BC_1_2_Support value="2">Charging Port</vif:BC_1_2_Support>

+    <vif:Captive_Cable value="false" />

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;General PD-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:PD_Spec_Revision_Major value="3" />

+    <vif:PD_Spec_Revision_Minor value="1" />

+    <vif:PD_Spec_Version_Major value="1" />

+    <vif:PD_Spec_Version_Minor value="3" />

+    <vif:PD_Specification_Revision value="2">Revision 3</vif:PD_Specification_Revision>

+    <vif:SOP_Capable value="true" />

+    <vif:SOP_P_Capable value="true" />

+    <vif:SOP_PP_Capable value="true" />

+    <vif:SOP_P_Debug_Capable value="false" />

+    <vif:SOP_PP_Debug_Capable value="false" />

+    <vif:Manufacturer_Info_Supported_Port value="true" />

+    <vif:Manufacturer_Info_VID_Port value="6353">18D1</vif:Manufacturer_Info_VID_Port>

+    <vif:Manufacturer_Info_PID_Port value="20570">505A</vif:Manufacturer_Info_PID_Port>

+    <vif:Chunking_Implemented_SOP value="true" />

+    <vif:Unchunked_Extended_Messages_Supported value="false" />

+    <vif:Security_Msgs_Supported_SOP value="false" />

+    <vif:Unconstrained_Power value="false" />

+    <vif:Num_Fixed_Batteries value="1" />

+    <vif:Num_Swappable_Battery_Slots value="0" />

+    <vif:ID_Header_Connector_Type_SOP value="2">USB Type-C® Receptacle</vif:ID_Header_Connector_Type_SOP>

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;PD Capabilities-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:USB_Comms_Capable value="true" />

+    <vif:DR_Swap_To_DFP_Supported value="true" />

+    <vif:DR_Swap_To_UFP_Supported value="false" />

+    <vif:VCONN_Swap_To_On_Supported value="true" />

+    <vif:VCONN_Swap_To_Off_Supported value="true" />

+    <vif:Responds_To_Discov_SOP_UFP value="false" />

+    <vif:Responds_To_Discov_SOP_DFP value="true" />

+    <vif:Attempts_Discov_SOP value="true" />

+    <vif:Power_Interruption_Available value="0">No Interruption Possible</vif:Power_Interruption_Available>

+    <vif:Data_Reset_Supported value="false" />

+    <vif:Enter_USB_Supported value="false" />

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;USB Type-C®-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:Type_C_Can_Act_As_Host value="true" />

+    <vif:Type_C_Can_Act_As_Device value="false" />

+    <vif:Type_C_Implements_Try_SRC value="true" />

+    <vif:Type_C_Implements_Try_SNK value="false" />

+    <vif:Type_C_Supports_Audio_Accessory value="false" />

+    <vif:Type_C_Is_VCONN_Powered_Accessory value="false" />

+    <vif:Type_C_Is_Debug_Target_SRC value="true" />

+    <vif:Type_C_Is_Debug_Target_SNK value="true" />

+    <vif:RP_Value value="1">1.5A</vif:RP_Value>

+    <vif:Type_C_Port_On_Hub value="false" />

+    <vif:Type_C_Power_Source value="2">Both</vif:Type_C_Power_Source>

+    <vif:Type_C_Sources_VCONN value="true" />

+    <vif:Type_C_Is_Alt_Mode_Controller value="true" />

+    <vif:Type_C_Is_Alt_Mode_Adapter value="false" />

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;Product Power-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:Product_Total_Source_Power_mW value="15000">15000 mW</vif:Product_Total_Source_Power_mW>

+    <vif:Port_Source_Power_Type value="0">Assured</vif:Port_Source_Power_Type>

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;USB Host-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:Host_Supports_USB_Data value="true" />

+    <vif:Host_Speed value="1">USB 3.2 Gen 1x1</vif:Host_Speed>

+    <vif:Host_Contains_Captive_Retimer value="true" />

+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />

+    <vif:Host_Is_Embedded value="false" />

+    <vif:Host_Suspend_Supported value="true" />

+    <vif:Is_DFP_On_Hub value="false" />

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;Battery Charging 1.2-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:BC_1_2_Charging_Port_Type value="1">CDP</vif:BC_1_2_Charging_Port_Type>

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;PD Source-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:PD_Power_As_Source value="15000">15000 mW</vif:PD_Power_As_Source>

+    <vif:EPR_Supported_As_Src value="false" />

+    <vif:USB_Suspend_May_Be_Cleared value="false" />

+    <vif:Sends_Pings value="false" />

+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="0">FR_Swap not supported</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>

+    <vif:Master_Port value="false" />

+    <vif:Num_Src_PDOs value="1" />

+    <vif:PD_OC_Protection value="true" />

+    <vif:PD_OCP_Method value="0">Over-Current Response</vif:PD_OCP_Method>

+    <!--Bundle: SrcPdoList-->

+    <vif:SrcPdoList>

+      <vif:SrcPDO>

+        <!--Source PDO 1-->

+        <vif:Src_PDO_Supply_Type value="0">Fixed</vif:Src_PDO_Supply_Type>

+        <vif:Src_PDO_Peak_Current value="0">100% IOC</vif:Src_PDO_Peak_Current>

+        <vif:Src_PDO_Voltage value="100">5000 mV</vif:Src_PDO_Voltage>

+        <vif:Src_PDO_Max_Current value="300">3000 mA</vif:Src_PDO_Max_Current>

+        <vif:Src_PD_OCP_OC_Debounce value="0">0 msec</vif:Src_PD_OCP_OC_Debounce>

+        <vif:Src_PD_OCP_OC_Threshold value="300">3000 mA</vif:Src_PD_OCP_OC_Threshold>

+      </vif:SrcPDO>

+    </vif:SrcPdoList>

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;PD Sink-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:PD_Power_As_Sink value="60000">60000 mW</vif:PD_Power_As_Sink>

+    <vif:EPR_Supported_As_Snk value="false" />

+    <vif:No_USB_Suspend_May_Be_Set value="true" />

+    <vif:GiveBack_May_Be_Set value="false" />

+    <vif:Higher_Capability_Set value="false" />

+    <vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source value="0">FR_Swap not supported</vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source>

+    <vif:Num_Snk_PDOs value="3" />

+    <!--Bundle: SnkPdoList-->

+    <vif:SnkPdoList>

+      <vif:SnkPDO>

+        <!--Sink PDO 1-->

+        <vif:Snk_PDO_Supply_Type value="0">Fixed</vif:Snk_PDO_Supply_Type>

+        <vif:Snk_PDO_Voltage value="100">5000 mV</vif:Snk_PDO_Voltage>

+        <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>

+      </vif:SnkPDO>

+      <vif:SnkPDO>

+        <!--Sink PDO 2-->

+        <vif:Snk_PDO_Supply_Type value="1">Battery</vif:Snk_PDO_Supply_Type>

+        <vif:Snk_PDO_Op_Power value="60">15000 mW</vif:Snk_PDO_Op_Power>

+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>

+        <vif:Snk_PDO_Max_Voltage value="400">20000 mV</vif:Snk_PDO_Max_Voltage>

+      </vif:SnkPDO>

+      <vif:SnkPDO>

+        <!--Sink PDO 3-->

+        <vif:Snk_PDO_Supply_Type value="2">Variable</vif:Snk_PDO_Supply_Type>

+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>

+        <vif:Snk_PDO_Max_Voltage value="400">20000 mV</vif:Snk_PDO_Max_Voltage>

+        <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>

+      </vif:SnkPDO>

+    </vif:SnkPdoList>

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;Dual Role-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:Accepts_PR_Swap_As_Src value="true" />

+    <vif:Accepts_PR_Swap_As_Snk value="true" />

+    <vif:Requests_PR_Swap_As_Src value="true" />

+    <vif:Requests_PR_Swap_As_Snk value="true" />

+    <vif:FR_Swap_Supported_As_Initial_Sink value="false" />

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;SOP Discover ID-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:XID_SOP value="0" />

+    <vif:Data_Capable_As_USB_Host_SOP value="true" />

+    <vif:Data_Capable_As_USB_Device_SOP value="false" />

+    <vif:Product_Type_UFP_SOP value="0">Undefined</vif:Product_Type_UFP_SOP>

+    <vif:Product_Type_DFP_SOP value="0">Undefined</vif:Product_Type_DFP_SOP>

+    <vif:DFP_VDO_Port_Number value="1" />

+    <vif:Modal_Operation_Supported_SOP value="false" />

+    <vif:USB_VID_SOP value="6353">18D1</vif:USB_VID_SOP>

+    <vif:PID_SOP value="20570">505A</vif:PID_SOP>

+    <vif:bcdDevice_SOP value="0">0000</vif:bcdDevice_SOP>

+  </vif:Component>

+</vif:VIF>
\ No newline at end of file
diff --git a/zephyr/projects/nissa/src/pujjo/charger.c b/zephyr/projects/nissa/pujjo/src/charger.c
index c6209bdf75..c091e8cf42 100644
--- a/zephyr/projects/nissa/src/pujjo/charger.c
+++ b/zephyr/projects/nissa/pujjo/src/charger.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The ChromiumOS Authors.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -48,9 +48,7 @@ __override void board_check_extpower(void)
 __override void board_hibernate(void)
 {
 	/* Shut down the chargers */
-	if (board_get_usb_pd_port_count() == 2)
-		raa489000_hibernate(CHARGER_SECONDARY, true);
-	raa489000_hibernate(CHARGER_PRIMARY, true);
+	raa489000_hibernate(0, true);
 	LOG_INF("Charger(s) hibernated");
 	cflush();
 }
diff --git a/zephyr/projects/nissa/src/pujjo/fan.c b/zephyr/projects/nissa/pujjo/src/fan.c
index 8914774452..97323a7edf 100644
--- a/zephyr/projects/nissa/src/pujjo/fan.c
+++ b/zephyr/projects/nissa/pujjo/src/fan.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The ChromiumOS Authors.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -28,8 +28,7 @@ static void fan_init(void)
 	 */
 	ret = cros_cbi_get_fw_config(FW_FAN, &val);
 	if (ret != 0) {
-		LOG_ERR("Error retrieving CBI FW_CONFIG field %d",
-			FW_FAN);
+		LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_FAN);
 		return;
 	}
 	if (val != FW_FAN_PRESENT) {
@@ -37,9 +36,8 @@ static void fan_init(void)
 		fan_set_count(0);
 	} else {
 		/* Configure the fan enable GPIO */
-		gpio_pin_configure_dt(
-			GPIO_DT_FROM_NODELABEL(gpio_fan_enable),
-			GPIO_OUTPUT);
+		gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_fan_enable),
+				      GPIO_OUTPUT);
 	}
 }
 DECLARE_HOOK(HOOK_INIT, fan_init, HOOK_PRIO_POST_FIRST);
diff --git a/zephyr/projects/nissa/pujjo/src/form_factor.c b/zephyr/projects/nissa/pujjo/src/form_factor.c
new file mode 100644
index 0000000000..ff3d64fe3e
--- /dev/null
+++ b/zephyr/projects/nissa/pujjo/src/form_factor.c
@@ -0,0 +1,39 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/devicetree.h>
+#include <zephyr/logging/log.h>
+
+#include "accelgyro.h"
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+#include "driver/accelgyro_bmi323.h"
+#include "driver/accelgyro_lsm6dsm.h"
+#include "hooks.h"
+#include "motionsense_sensors.h"
+
+#include "nissa_common.h"
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+static bool use_alt_sensor;
+
+void motion_interrupt(enum gpio_signal signal)
+{
+	if (use_alt_sensor)
+		lsm6dsm_interrupt(signal);
+	else
+		bmi3xx_interrupt(signal);
+}
+
+static void sensor_init(void)
+{
+	/* check which base sensor is used for motion_interrupt */
+	use_alt_sensor = cros_cbi_ssfc_check_match(
+		CBI_SSFC_VALUE_ID(DT_NODELABEL(base_sensor_1)));
+
+	motion_sensors_check_ssfc();
+}
+DECLARE_HOOK(HOOK_INIT, sensor_init, HOOK_PRIO_POST_I2C);
diff --git a/zephyr/projects/nissa/pujjo/src/hdmi.c b/zephyr/projects/nissa/pujjo/src/hdmi.c
new file mode 100644
index 0000000000..9461e7c53e
--- /dev/null
+++ b/zephyr/projects/nissa/pujjo/src/hdmi.c
@@ -0,0 +1,12 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "nissa_hdmi.h"
+
+__override void nissa_configure_hdmi_power_gpios(void)
+{
+	/* Pujjo needs to drive VCC enable but not core rails */
+	nissa_configure_hdmi_vcc();
+}
diff --git a/zephyr/projects/nissa/pujjo/src/keyboard.c b/zephyr/projects/nissa/pujjo/src/keyboard.c
new file mode 100644
index 0000000000..1587030080
--- /dev/null
+++ b/zephyr/projects/nissa/pujjo/src/keyboard.c
@@ -0,0 +1,29 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+
+static const struct ec_response_keybd_config pujjo_kb = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_BRIGHTNESS_DOWN,	/* T5 */
+		TK_BRIGHTNESS_UP,	/* T6 */
+		TK_MICMUTE,		/* T7 */
+		TK_VOL_MUTE,		/* T8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &pujjo_kb;
+}
diff --git a/zephyr/projects/nissa/pujjo/src/led.c b/zephyr/projects/nissa/pujjo/src/led.c
new file mode 100644
index 0000000000..0ff36b7d97
--- /dev/null
+++ b/zephyr/projects/nissa/pujjo/src/led.c
@@ -0,0 +1,134 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Pujjo specific PWM LED settings: there are 2 LEDs on each side of the board,
+ * each one can be controlled separately. The LED colors are white or amber,
+ * and the default behavior is tied to the charging process: both sides are
+ * amber while charging the battery and white when the battery is charged.
+ */
+
+#include "common.h"
+#include "led_onoff_states.h"
+#include "led_common.h"
+#include "gpio.h"
+
+#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args)
+
+#define LED_OFF_LVL 1
+#define LED_ON_LVL 0
+
+__override const int led_charge_lvl_1 = 5;
+
+__override const int led_charge_lvl_2 = 97;
+
+__override struct led_descriptor
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
+
+__override const struct led_descriptor
+	led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = {
+		[PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } },
+		[PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE,
+						 1 * LED_ONE_SEC },
+					       { LED_OFF, 3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE,
+						    1 * LED_ONE_SEC },
+						  { LED_OFF,
+						    3 * LED_ONE_SEC } },
+		[PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } },
+	};
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED,
+					     EC_LED_ID_POWER_LED };
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+__override void led_set_color_power(enum ec_led_colors color)
+{
+	if (color == EC_LED_COLOR_WHITE)
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_power_led),
+				LED_ON_LVL);
+	else
+		/* LED_OFF and unsupported colors */
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_power_led),
+				LED_OFF_LVL);
+}
+
+__override void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_AMBER:
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_led_1_odl),
+				LED_ON_LVL);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_led_2_odl),
+				LED_ON_LVL);
+		break;
+	case EC_LED_COLOR_RED:
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_led_1_odl),
+				LED_ON_LVL);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_led_2_odl),
+				LED_OFF_LVL);
+		break;
+	case EC_LED_COLOR_GREEN:
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_led_1_odl),
+				LED_OFF_LVL);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_led_2_odl),
+				LED_ON_LVL);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_led_1_odl),
+				LED_OFF_LVL);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_led_2_odl),
+				LED_OFF_LVL);
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		brightness_range[EC_LED_COLOR_RED] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		brightness_range[EC_LED_COLOR_GREEN] = 1;
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (led_id == EC_LED_ID_BATTERY_LED) {
+		if (brightness[EC_LED_COLOR_RED] != 0)
+			led_set_color_battery(EC_LED_COLOR_RED);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(EC_LED_COLOR_AMBER);
+		else if (brightness[EC_LED_COLOR_GREEN] != 0)
+			led_set_color_battery(EC_LED_COLOR_GREEN);
+		else
+			led_set_color_battery(LED_OFF);
+	} else if (led_id == EC_LED_ID_POWER_LED) {
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_power(EC_LED_COLOR_WHITE);
+		else
+			led_set_color_power(LED_OFF);
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/zephyr/projects/nissa/pujjo/src/usbc.c b/zephyr/projects/nissa/pujjo/src/usbc.c
new file mode 100644
index 0000000000..5d3d94c243
--- /dev/null
+++ b/zephyr/projects/nissa/pujjo/src/usbc.c
@@ -0,0 +1,242 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/logging/log.h>
+
+#include "charge_state_v2.h"
+#include "chipset.h"
+#include "hooks.h"
+#include "usb_mux.h"
+#include "system.h"
+#include "driver/charger/isl923x_public.h"
+#include "driver/retimer/anx7483_public.h"
+#include "driver/tcpm/tcpci.h"
+#include "driver/tcpm/raa489000.h"
+
+#include "nissa_common.h"
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C0_TCPC,
+			.addr_flags = RAA489000_TCPC0_I2C_FLAGS,
+		},
+		.drv = &raa489000_tcpm_drv,
+		/* RAA489000 implements TCPCI 2.0 */
+		.flags = TCPC_FLAGS_TCPCI_REV2_0 |
+			TCPC_FLAGS_VBUS_MONITOR,
+	},
+};
+
+int board_is_sourcing_vbus(int port)
+{
+	int regval;
+
+	tcpc_read(port, TCPC_REG_POWER_STATUS, &regval);
+	return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS);
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int i;
+	int old_port;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	old_port = charge_manager_get_active_charge_port();
+
+	LOG_INF("New chg p%d", port);
+
+	/* Disable all ports. */
+	if (port == CHARGE_PORT_NONE) {
+		for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+			tcpc_write(i, TCPC_REG_COMMAND,
+				   TCPC_REG_COMMAND_SNK_CTRL_LOW);
+			raa489000_enable_asgate(i, false);
+		}
+
+		return EC_SUCCESS;
+	}
+
+	/* Check if port is sourcing VBUS. */
+	if (board_is_sourcing_vbus(port)) {
+		LOG_WRN("Skip enable p%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		if (i == port)
+			continue;
+
+		if (tcpc_write(i, TCPC_REG_COMMAND,
+			       TCPC_REG_COMMAND_SNK_CTRL_LOW))
+			LOG_WRN("p%d: sink path disable failed.", i);
+		raa489000_enable_asgate(i, false);
+	}
+
+	/*
+	 * Stop the charger IC from switching while changing ports.  Otherwise,
+	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
+	 */
+	if (old_port != CHARGE_PORT_NONE)
+		charger_discharge_on_ac(1);
+
+	/* Enable requested charge port. */
+	if (raa489000_enable_asgate(port, true) ||
+	    tcpc_write(port, TCPC_REG_COMMAND,
+		       TCPC_REG_COMMAND_SNK_CTRL_HIGH)) {
+		LOG_WRN("p%d: sink path enable failed.", port);
+		charger_discharge_on_ac(0);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	/* Allow the charger IC to begin/continue switching. */
+	charger_discharge_on_ac(0);
+
+	return EC_SUCCESS;
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+	int regval;
+
+	/*
+	 * The interrupt line is shared between the TCPC and BC1.2 detector IC.
+	 * Therefore, go out and actually read the alert registers to report the
+	 * alert status.
+	 */
+	if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl))) {
+		if (!tcpc_read16(0, TCPC_REG_ALERT, &regval)) {
+			/* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */
+			if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0))
+				regval &= ~((1 << 14) | (1 << 13) | (1 << 12));
+
+			if (regval)
+				status |= PD_STATUS_TCPC_ALERT_0;
+		}
+	}
+	return status;
+}
+
+void pd_power_supply_reset(int port)
+{
+	/* Disable VBUS */
+	tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	if (port < 0 || port >= CONFIG_USB_PD_PORT_MAX_COUNT)
+		return;
+
+	raa489000_set_output_current(port, rp);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	if (port >= CONFIG_USB_PD_PORT_MAX_COUNT)
+		return EC_ERROR_INVAL;
+
+	/* Disable charging. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW);
+	if (rv)
+		return rv;
+
+	/* Our policy is not to source VBUS when the AP is off. */
+	if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	/* Provide Vbus. */
+	rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH);
+	if (rv)
+		return rv;
+
+	rv = raa489000_enable_asgate(port, true);
+	if (rv)
+		return rv;
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * TODO(b:147316511): could send a reset command to the TCPC here
+	 * if needed.
+	 */
+}
+
+/*
+ * Because the TCPCs and BC1.2 chips share interrupt lines, it's possible
+ * for an interrupt to be lost if one asserts the IRQ, the other does the same
+ * then the first releases it: there will only be one falling edge to trigger
+ * the interrupt, and the line will be held low. We handle this by running a
+ * deferred check after a falling edge to see whether the IRQ is still being
+ * asserted. If it is, we assume an interrupt may have been lost and we need
+ * to poll each chip for events again.
+ */
+#define USBC_INT_POLL_DELAY_US 5000
+
+static void poll_c0_int(void);
+DECLARE_DEFERRED(poll_c0_int);
+
+static void usbc_interrupt_trigger(int port)
+{
+	schedule_deferred_pd_interrupt(port);
+	usb_charger_task_set_event(port, USB_CHG_EVENT_BC12);
+}
+
+static inline void poll_usb_gpio(int port, const struct gpio_dt_spec *gpio,
+				 const struct deferred_data *ud)
+{
+	if (!gpio_pin_get_dt(gpio)) {
+		usbc_interrupt_trigger(port);
+		hook_call_deferred(ud, USBC_INT_POLL_DELAY_US);
+	}
+}
+
+static void poll_c0_int(void)
+{
+	poll_usb_gpio(0, GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl),
+		      &poll_c0_int_data);
+}
+
+void usb_interrupt(enum gpio_signal signal)
+{
+	int port;
+	const struct deferred_data *ud;
+
+	if (signal == GPIO_SIGNAL(DT_NODELABEL(gpio_usb_c0_int_odl))) {
+		port = 0;
+		ud = &poll_c0_int_data;
+	}
+	/*
+	 * We've just been called from a falling edge, so there's definitely
+	 * no lost IRQ right now. Cancel any pending check.
+	 */
+	hook_call_deferred(ud, -1);
+	/* Trigger polling of TCPC and BC1.2 in respective tasks */
+	usbc_interrupt_trigger(port);
+	/* Check for lost interrupts in a bit */
+	hook_call_deferred(ud, USBC_INT_POLL_DELAY_US);
+}
diff --git a/zephyr/projects/nissa/src/board_power.c b/zephyr/projects/nissa/src/board_power.c
index 8180b2c8af..d7fb4aeffe 100644
--- a/zephyr/projects/nissa/src/board_power.c
+++ b/zephyr/projects/nissa/src/board_power.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,7 +19,7 @@
 
 LOG_MODULE_DECLARE(ap_pwrseq, LOG_LEVEL_INF);
 
-#define  X86_NON_DSX_ADLP_NONPWRSEQ_FORCE_SHUTDOWN_TO_MS	5
+#define X86_NON_DSX_ADLP_NONPWRSEQ_FORCE_SHUTDOWN_TO_MS 5
 
 static bool s0_stable;
 
@@ -44,11 +44,11 @@ void board_ap_power_force_shutdown(void)
 		power_signal_enable(PWR_PG_PP1P05);
 	}
 
-	power_signal_set(PWR_EC_PCH_RSMRST, 0);
 	power_signal_set(PWR_EC_SOC_DSW_PWROK, 0);
+	power_signal_set(PWR_EC_PCH_RSMRST, 0);
 
 	while (power_signal_get(PWR_RSMRST) == 0 &&
-	      power_signal_get(PWR_SLP_SUS) == 0 && timeout_ms > 0) {
+	       power_signal_get(PWR_SLP_SUS) == 0 && timeout_ms > 0) {
 		k_msleep(1);
 		timeout_ms--;
 	}
@@ -88,10 +88,9 @@ void board_ap_power_action_g3_s5(void)
 	power_signal_set(PWR_EN_PP3300_A, 1);
 
 	power_wait_signals_timeout(IN_PGOOD_ALL_CORE,
-		AP_PWRSEQ_DT_VALUE(wait_signal_timeout));
+				   AP_PWRSEQ_DT_VALUE(wait_signal_timeout));
 
-	generate_ec_soc_dsw_pwrok_handler(
-		AP_PWRSEQ_DT_VALUE(dsw_pwrok_delay));
+	generate_ec_soc_dsw_pwrok_handler(AP_PWRSEQ_DT_VALUE(dsw_pwrok_delay));
 	s0_stable = false;
 }
 
@@ -132,8 +131,8 @@ int board_ap_power_assert_pch_power_ok(void)
 bool board_ap_power_check_power_rails_enabled(void)
 {
 	return power_signal_get(PWR_EN_PP3300_A) &&
-			power_signal_get(PWR_EN_PP5000_A) &&
-			power_signal_get(PWR_EC_SOC_DSW_PWROK);
+	       power_signal_get(PWR_EN_PP5000_A) &&
+	       power_signal_get(PWR_EC_SOC_DSW_PWROK);
 }
 
 int board_power_signal_get(enum power_signal signal)
@@ -154,7 +153,7 @@ int board_power_signal_get(enum power_signal signal)
 			return 0;
 		}
 		if (!gpio_pin_get_dt(
-		     GPIO_DT_FROM_NODELABEL(gpio_all_sys_pwrgd))) {
+			    GPIO_DT_FROM_NODELABEL(gpio_all_sys_pwrgd))) {
 			return 0;
 		}
 		if (!power_signal_get(PWR_PG_PP1P05)) {
diff --git a/zephyr/projects/nissa/src/common.c b/zephyr/projects/nissa/src/common.c
index e1e7aaf7e9..fe25d1374d 100644
--- a/zephyr/projects/nissa/src/common.c
+++ b/zephyr/projects/nissa/src/common.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -81,8 +81,8 @@ static void board_setup_init(void)
  */
 DECLARE_HOOK(HOOK_INIT, board_setup_init, HOOK_PRIO_INIT_I2C);
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT);
 
@@ -124,7 +124,7 @@ enum nissa_sub_board_type nissa_get_sb_type(void)
 	if (sb != NISSA_SB_UNKNOWN)
 		return sb;
 
-	sb = NISSA_SB_NONE;	/* Defaults to none */
+	sb = NISSA_SB_NONE; /* Defaults to none */
 	ret = cros_cbi_get_fw_config(FW_SUB_BOARD, &val);
 	if (ret != 0) {
 		LOG_WRN("Error retrieving CBI FW_CONFIG field %d",
diff --git a/zephyr/projects/nissa/src/craask/led.c b/zephyr/projects/nissa/src/craask/led.c
deleted file mode 100644
index a0c0447419..0000000000
--- a/zephyr/projects/nissa/src/craask/led.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/* Copyright 2022 The ChromiumOS Authors.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery LED control for nissa
- */
-#include "common.h"
-#include "ec_commands.h"
-#include "led_common.h"
-#include "led_onoff_states.h"
-#include "led_pwm.h"
-
-__override const int led_charge_lvl_1 = 5;
-__override const int led_charge_lvl_2 = 97;
-__override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_BLUE,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} },
-	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,            3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,	     1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC},
-					{EC_LED_COLOR_BLUE,  2 * LED_ONE_SEC} },
-};
-
-__override void led_set_color_battery(enum ec_led_colors color)
-{
-	switch (color) {
-	case EC_LED_COLOR_RED:
-		set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_RED);
-		break;
-	case EC_LED_COLOR_BLUE:
-		set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_BLUE);
-		break;
-	case EC_LED_COLOR_AMBER:
-		set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_AMBER);
-		break;
-	default: /* LED_OFF and other unsupported colors */
-		set_pwm_led_color(EC_LED_ID_BATTERY_LED, -1);
-		break;
-	}
-}
diff --git a/zephyr/projects/nissa/src/led.c b/zephyr/projects/nissa/src/led.c
index 27c78f8051..2617d0092d 100644
--- a/zephyr/projects/nissa/src/led.c
+++ b/zephyr/projects/nissa/src/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -13,20 +13,25 @@
 __override const int led_charge_lvl_1 = 5;
 __override const int led_charge_lvl_2 = 97;
 __override struct led_descriptor
-			led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
-	[STATE_CHARGING_LVL_1]	     = {{EC_LED_COLOR_RED,    LED_INDEFINITE} },
-	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_AMBER,  LED_INDEFINITE} },
-	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC},
-					{LED_OFF,	     3 * LED_ONE_SEC} },
-	[STATE_DISCHARGE_S3]	     = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_DISCHARGE_S5]         = {{LED_OFF,  LED_INDEFINITE} },
-	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_RED,  1 * LED_ONE_SEC},
-					{LED_OFF,	    1 * LED_ONE_SEC} },
-	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_RED,   2 * LED_ONE_SEC},
-					{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} },
-};
+	led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+		[STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER,
+					     LED_INDEFINITE } },
+		[STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN,
+						   LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER,
+						   1 * LED_ONE_SEC },
+						 { LED_OFF, 3 * LED_ONE_SEC } },
+		[STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } },
+		[STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC },
+					  { LED_OFF, 1 * LED_ONE_SEC } },
+		[STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC },
+					 { EC_LED_COLOR_GREEN,
+					   2 * LED_ONE_SEC } },
+	};
 
 __override void led_set_color_battery(enum ec_led_colors color)
 {
diff --git a/zephyr/projects/nissa/src/sub_board.c b/zephyr/projects/nissa/src/sub_board.c
index 2a3333bab9..89a9954037 100644
--- a/zephyr/projects/nissa/src/sub_board.c
+++ b/zephyr/projects/nissa/src/sub_board.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,25 +7,30 @@
 
 #include <ap_power/ap_power.h>
 #include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/pinctrl.h>
 #include <zephyr/init.h>
 #include <zephyr/kernel.h>
 #include <zephyr/sys/printk.h>
 
+#include "cros_board_info.h"
 #include "driver/tcpm/tcpci.h"
 #include "gpio/gpio_int.h"
 #include "hooks.h"
 #include "usb_charge.h"
 #include "usb_pd.h"
+#include "usbc/usb_muxes.h"
 #include "task.h"
 
 #include "nissa_common.h"
+#include "nissa_hdmi.h"
 
 LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
 
+#if NISSA_BOARD_HAS_HDMI_SUPPORT
 static void hdmi_power_handler(struct ap_power_ev_callback *cb,
 			       struct ap_power_ev_data data)
 {
-	/* Enable rails for S3 */
+	/* Enable VCC on the HDMI port. */
 	const struct gpio_dt_spec *s3_rail =
 		GPIO_DT_FROM_ALIAS(gpio_hdmi_en_odl);
 	/* Connect AP's DDC to sub-board (default is USB-C aux) */
@@ -65,8 +70,54 @@ static void hdmi_hpd_interrupt(const struct device *device,
 	LOG_DBG("HDMI HPD changed state to %d", state);
 }
 
+void nissa_configure_hdmi_rails(void)
+{
+#if DT_NODE_EXISTS(GPIO_DT_FROM_ALIAS(gpio_en_rails_odl))
+	gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_en_rails_odl),
+			      GPIO_OUTPUT_INACTIVE | GPIO_OPEN_DRAIN |
+				      GPIO_PULL_UP | GPIO_ACTIVE_LOW);
+#endif
+}
+
+void nissa_configure_hdmi_vcc(void)
+{
+	gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_hdmi_en_odl),
+			      GPIO_OUTPUT_INACTIVE | GPIO_OPEN_DRAIN |
+				      GPIO_ACTIVE_LOW);
+}
+
+__overridable void nissa_configure_hdmi_power_gpios(void)
+{
+	nissa_configure_hdmi_rails();
+}
+
+#ifdef CONFIG_SOC_IT8XXX2
+/*
+ * On it8xxx2, the below condition will break the EC to enter deep doze mode
+ * (b:237717730):
+ * Enhance i2c (GPE0/E7, GPH1/GPH2 or GPA4/GPA5) is enabled and its clock and
+ * data pins aren't both at high level.
+ *
+ * Since HDMI+type A SKU doesn't use i2c4, disable it for better power number.
+ */
+#define I2C4_NODE DT_NODELABEL(i2c4)
+#if DT_NODE_EXISTS(I2C4_NODE)
+PINCTRL_DT_DEFINE(I2C4_NODE);
+
+/* disable i2c4 alternate function  */
+static void soc_it8xxx2_disable_i2c4_alt(void)
+{
+	const struct pinctrl_dev_config *pcfg =
+		PINCTRL_DT_DEV_CONFIG_GET(I2C4_NODE);
+
+	pinctrl_apply_state(pcfg, PINCTRL_STATE_SLEEP);
+}
+#endif /* DT_NODE_EXISTS(I2C4_NODE) */
+#endif /* CONFIG_SOC_IT8XXX2 */
+#endif /* NISSA_BOARD_HAS_HDMI_SUPPORT */
+
 static void lte_power_handler(struct ap_power_ev_callback *cb,
-			       struct ap_power_ev_data data)
+			      struct ap_power_ev_data data)
 {
 	/* Enable rails for S5 */
 	const struct gpio_dt_spec *s5_rail =
@@ -76,7 +127,7 @@ static void lte_power_handler(struct ap_power_ev_callback *cb,
 		LOG_DBG("Enabling LTE sub-board power rails");
 		gpio_pin_set_dt(s5_rail, 1);
 		break;
-	case AP_POWER_SHUTDOWN:
+	case AP_POWER_HARD_OFF:
 		LOG_DBG("Disabling LTE sub-board power rails");
 		gpio_pin_set_dt(s5_rail, 0);
 		break;
@@ -105,38 +156,37 @@ static void nereid_subboard_config(void)
 	 */
 	if (sb == NISSA_SB_C_A || sb == NISSA_SB_HDMI_A) {
 		/* Configure VBUS enable, default off */
-		gpio_pin_configure_dt(
-			GPIO_DT_FROM_ALIAS(gpio_en_usb_a1_vbus),
-			GPIO_OUTPUT_LOW);
+		gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_en_usb_a1_vbus),
+				      GPIO_OUTPUT_LOW);
 	} else {
 		/* Turn off unused pins */
 		gpio_pin_configure_dt(
 			GPIO_DT_FROM_NODELABEL(gpio_sub_usb_a1_ilimit_sdp),
 			GPIO_DISCONNECTED);
-		gpio_pin_configure_dt(
-			GPIO_DT_FROM_ALIAS(gpio_en_usb_a1_vbus),
-			GPIO_DISCONNECTED);
+		gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_en_usb_a1_vbus),
+				      GPIO_DISCONNECTED);
 		/* Disable second USB-A port enable GPIO */
 		__ASSERT(USB_PORT_ENABLE_COUNT == 2,
-		       "USB A port count != 2 (%d)", USB_PORT_ENABLE_COUNT);
+			 "USB A port count != 2 (%d)", USB_PORT_ENABLE_COUNT);
 		usb_port_enable[1] = -1;
 	}
 	/*
 	 * USB-C port: the default configuration has I2C on the I2C pins,
 	 * but the interrupt line needs to be configured.
 	 */
+#if CONFIG_USB_PD_PORT_MAX_COUNT > 1
 	if (sb == NISSA_SB_C_A || sb == NISSA_SB_C_LTE) {
 		/* Configure interrupt input */
-		gpio_pin_configure_dt(
-			GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl),
-			GPIO_INPUT | GPIO_PULL_UP);
+		gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl),
+				      GPIO_INPUT | GPIO_PULL_UP);
 	} else {
-		/* Disable the port 1 charger task */
-		task_disable_task(TASK_ID_USB_CHG_P1);
-		usb_muxes[1].next_mux = NULL;
+		/* Port doesn't exist, doesn't need muxing */
+		USB_MUX_ENABLE_ALTERNATIVE(usb_mux_chain_1_no_mux);
 	}
+#endif
 
 	switch (sb) {
+#if NISSA_BOARD_HAS_HDMI_SUPPORT
 	case NISSA_SB_HDMI_A: {
 		/*
 		 * HDMI: two outputs control power which must be configured to
@@ -148,14 +198,18 @@ static void nereid_subboard_config(void)
 		static struct gpio_callback hdmi_hpd_cb;
 		int rv, irq_key;
 
-		/* HDMI power enable outputs */
-		gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_en_rails_odl),
-				      GPIO_OUTPUT_INACTIVE | GPIO_OPEN_DRAIN |
-					      GPIO_PULL_UP | GPIO_ACTIVE_LOW);
-		gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_hdmi_en_odl),
-				      GPIO_OUTPUT_INACTIVE | GPIO_OPEN_DRAIN |
-					      GPIO_ACTIVE_LOW);
-		/* Control HDMI power in concert with AP */
+		nissa_configure_hdmi_power_gpios();
+
+#if CONFIG_SOC_IT8XXX2 && DT_NODE_EXISTS(I2C4_NODE)
+		/* disable i2c4 alternate function for better power number */
+		soc_it8xxx2_disable_i2c4_alt();
+#endif
+
+		/*
+		 * Control HDMI power according to AP power state. Some events
+		 * won't do anything if the corresponding pin isn't configured,
+		 * but that's okay.
+		 */
 		ap_power_ev_init_callback(
 			&power_cb, hdmi_power_handler,
 			AP_POWER_PRE_INIT | AP_POWER_HARD_OFF |
@@ -187,6 +241,7 @@ static void nereid_subboard_config(void)
 		irq_unlock(irq_key);
 		break;
 	}
+#endif
 	case NISSA_SB_C_LTE:
 		/*
 		 * LTE: Set up callbacks for enabling/disabling
@@ -197,9 +252,9 @@ static void nereid_subboard_config(void)
 		/* Control LTE power when CPU entering or
 		 * exiting S5 state.
 		 */
-		ap_power_ev_init_callback(
-			&power_cb, lte_power_handler,
-			AP_POWER_SHUTDOWN | AP_POWER_PRE_INIT);
+		ap_power_ev_init_callback(&power_cb, lte_power_handler,
+					  AP_POWER_HARD_OFF |
+						  AP_POWER_PRE_INIT);
 		ap_power_ev_add_callback(&power_cb);
 		break;
 
@@ -218,8 +273,10 @@ static void board_init(void)
 	 * Enable USB-C interrupts.
 	 */
 	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0));
+#if CONFIG_USB_PD_PORT_MAX_COUNT > 1
 	if (board_get_usb_pd_port_count() == 2)
 		gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1));
+#endif
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
 
diff --git a/zephyr/projects/nissa/xivu/cbi.dts b/zephyr/projects/nissa/xivu/cbi.dts
new file mode 100644
index 0000000000..4149ea291c
--- /dev/null
+++ b/zephyr/projects/nissa/xivu/cbi.dts
@@ -0,0 +1,77 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	/* Xivu-specific fw_config fields. */
+	nissa-fw-config {
+		/*
+		 * FW_CONFIG field to enable WFC or not.
+		 */
+		 wfc {
+			enum-name = "FW_WFC";
+			start = <0>;
+			size = <1>;
+
+			wfc-mipi {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_WFC_MIPI";
+				value = <0>;
+			};
+			wfc-absent {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_WFC_ABSENT";
+				value = <1>;
+			};
+		 };
+
+		/*
+		 * FW_CONFIG field to enable stylus or not.
+		 */
+		 stylus {
+			enum-name = "FW_STYLUS";
+			start = <1>;
+			size = <1>;
+
+			stylus-present {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_STYLUS_PRESENT";
+				value = <0>;
+			};
+			stylus-absent {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_STYLUS_ABSENT";
+				value = <1>;
+			};
+		 };
+		/*
+		 * FW_CONFIG field to indicate which sub-board
+		 * is attached.
+		 */
+		sub-board {
+			enum-name = "FW_SUB_BOARD";
+			start = <2>;
+			size = <2>;
+
+			sub-board-1 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_SUB_BOARD_1";
+				value = <0>;
+			};
+			sub-board-2 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_SUB_BOARD_2";
+				value = <1>;
+			};
+			sub-board-3 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_SUB_BOARD_3";
+				value = <2>;
+			};
+		};
+
+/delete-node/ fan;
+	};
+
+};
diff --git a/zephyr/projects/nissa/xivu/generated.dts b/zephyr/projects/nissa/xivu/generated.dts
new file mode 100644
index 0000000000..383054adf8
--- /dev/null
+++ b/zephyr/projects/nissa/xivu/generated.dts
@@ -0,0 +1,291 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * This file is auto-generated - do not edit!
+ */
+
+/ {
+
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc {
+			enum-name = "ADC_PP1050_PROC";
+			io-channels = <&adc0 4>;
+		};
+		adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 {
+			enum-name = "ADC_PP3300_S5";
+			io-channels = <&adc0 6>;
+		};
+		adc_temp_sensor_1: temp_sensor_1 {
+			enum-name = "ADC_TEMP_SENSOR_1";
+			io-channels = <&adc0 0>;
+		};
+		adc_temp_sensor_2: temp_sensor_2 {
+			enum-name = "ADC_TEMP_SENSOR_2";
+			io-channels = <&adc0 1>;
+		};
+		adc_temp_sensor_3: temp_sensor_3 {
+			enum-name = "ADC_TEMP_SENSOR_3";
+			io-channels = <&adc0 10>;
+		};
+		adc_temp_sensor_4: temp_sensor_4 {
+			enum-name = "ADC_TEMP_SENSOR_4";
+			io-channels = <&adc0 11>;
+		};
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		gpio_acc_int_l: acc_int_l {
+			gpios = <&gpio5 0 GPIO_INPUT>;
+		};
+		gpio_all_sys_pwrgd: all_sys_pwrgd {
+			gpios = <&gpioa 7 GPIO_INPUT>;
+		};
+		gpio_ccd_mode_odl: ccd_mode_odl {
+			gpios = <&gpioe 5 GPIO_INPUT>;
+			enum-name = "GPIO_CCD_MODE_ODL";
+		};
+		gpio_cpu_c10_gate_l: cpu_c10_gate_l {
+			gpios = <&gpio6 7 GPIO_INPUT>;
+		};
+		gpio_ec_battery_pres_odl: ec_battery_pres_odl {
+			gpios = <&gpioa 3 GPIO_INPUT>;
+			enum-name = "GPIO_BATT_PRES_ODL";
+		};
+		gpio_ec_cbi_wp: ec_cbi_wp {
+			gpios = <&gpio7 4 GPIO_OUTPUT>;
+		};
+		gpio_ec_edp_bl_en_od: ec_edp_bl_en_od {
+			gpios = <&gpiod 3 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_ENABLE_BACKLIGHT";
+		};
+		gpio_ec_entering_rw: ec_entering_rw {
+			gpios = <&gpio0 3 GPIO_OUTPUT>;
+			enum-name = "GPIO_ENTERING_RW";
+		};
+		gpio_ec_gsc_packet_mode: ec_gsc_packet_mode {
+			gpios = <&gpio7 5 GPIO_OUTPUT>;
+			enum-name = "GPIO_PACKET_MODE_EN";
+		};
+		gpio_ec_kso_02_inv: ec_kso_02_inv {
+			gpios = <&gpio1 7 (GPIO_OUTPUT | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_ec_pch_wake_odl: ec_pch_wake_odl {
+			gpios = <&gpiob 0 GPIO_ODR_LOW>;
+		};
+		gpio_ec_prochot_odl: ec_prochot_odl {
+			gpios = <&gpiof 1 GPIO_ODR_HIGH>;
+		};
+		gpio_ec_soc_dsw_pwrok: ec_soc_dsw_pwrok {
+			gpios = <&gpio6 1 GPIO_OUTPUT>;
+		};
+		gpio_ec_acok_otg_c1: ec_acok_otg_c1 {
+			gpios = <&gpioe 4 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_int_odl: ec_soc_int_odl {
+			gpios = <&gpio8 0 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_EC_INT_L";
+		};
+		gpio_ec_soc_pch_pwrok_od: ec_soc_pch_pwrok_od {
+			gpios = <&gpio7 2 GPIO_ODR_HIGH>;
+		};
+		gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl {
+			gpios = <&gpioc 1 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_PCH_PWRBTN_L";
+		};
+		gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l {
+			gpios = <&gpioa 6 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_rtcrst: ec_soc_rtcrst {
+			gpios = <&gpio7 6 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_sys_pwrok: ec_soc_sys_pwrok {
+			gpios = <&gpio3 7 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_vccst_pwrgd_od: ec_soc_vccst_pwrgd_od {
+			gpios = <&gpioa 4 GPIO_ODR_HIGH>;
+		};
+		gpio_ec_wp_odl: ec_wp_odl {
+			gpios = <&gpioa 1 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_en_pp3300_s5: en_pp3300_s5 {
+			gpios = <&gpiob 6 GPIO_OUTPUT>;
+			enum-name = "GPIO_TEMP_SENSOR_POWER";
+		};
+		gpio_en_pp5000_pen_x: en_pp5000_pen_x {
+			gpios = <&gpioe 2 GPIO_OUTPUT>;
+		};
+		gpio_en_pp5000_s5: en_pp5000_s5 {
+			gpios = <&gpio4 0 GPIO_OUTPUT>;
+		};
+		gpio_en_slp_z: en_slp_z {
+			gpios = <&gpioe 1 GPIO_OUTPUT>;
+		};
+		gpio_en_usb_a0_vbus: en_usb_a0_vbus {
+			gpios = <&gpio9 1 GPIO_OUTPUT>;
+		};
+		gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl {
+			gpios = <&gpio0 0 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		gpio_ec_acok_otg_c0: ec_acok_otg_c0 {
+			gpios = <&gpioc 6 GPIO_OUTPUT>;
+		};
+		gpio_imu_int_l: imu_int_l {
+			gpios = <&gpio5 6 GPIO_INPUT>;
+		};
+		gpio_imvp91_vrrdy_od: imvp91_vrrdy_od {
+			gpios = <&gpio4 3 GPIO_INPUT>;
+		};
+		gpio_lid_open: lid_open {
+			gpios = <&gpiod 2 GPIO_INPUT>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+		gpio_pen_detect_odl: pen_detect_odl {
+			gpios = <&gpio9 6 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_pg_pp1050_mem_s3_od: pg_pp1050_mem_s3_od {
+			gpios = <&gpiof 0 GPIO_INPUT>;
+		};
+		gpio_pg_pp5000_s5_od: pg_pp5000_s5_od {
+			gpios = <&gpio4 2 GPIO_INPUT>;
+		};
+		gpio_rsmrst_pwrgd_l: rsmrst_pwrgd_l {
+			gpios = <&gpio9 4 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_slp_s0_l: slp_s0_l {
+			gpios = <&gpio9 7 GPIO_INPUT>;
+		};
+		gpio_slp_s3_l: slp_s3_l {
+			gpios = <&gpioa 5 GPIO_INPUT>;
+		};
+		gpio_slp_s4_l: slp_s4_l {
+			gpios = <&gpio7 0 GPIO_INPUT>;
+		};
+		gpio_slp_sus_l: slp_sus_l {
+			gpios = <&gpio6 2 GPIO_INPUT>;
+		};
+		gpio_sub_usb_a1_ilimit_sdp: sub_usb_a1_ilimit_sdp {
+			gpios = <&gpiod 5 GPIO_OUTPUT>;
+			enum-name = "GPIO_USB2_ILIM_SEL";
+		};
+		gpio_sys_rst_odl: sys_rst_odl {
+			gpios = <&gpioc 5 GPIO_ODR_HIGH>;
+		};
+		gpio_tablet_mode_l: tablet_mode_l {
+			gpios = <&gpio9 5 GPIO_INPUT>;
+			enum-name = "GPIO_TABLET_MODE_L";
+		};
+		gpio_usb_a0_ilimit_sdp: usb_a0_ilimit_sdp {
+			gpios = <&gpio3 3 GPIO_OUTPUT>;
+			enum-name = "GPIO_USB1_ILIM_SEL";
+		};
+		gpio_usb_c0_int_odl: usb_c0_int_odl {
+			gpios = <&gpio0 1 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_vccin_aux_vid0: vccin_aux_vid0 {
+			gpios = <&gpio9 2 GPIO_INPUT>;
+		};
+		gpio_vccin_aux_vid1: vccin_aux_vid1 {
+			gpios = <&gpioe 3 GPIO_INPUT>;
+		};
+		gpio_voldn_btn_odl: voldn_btn_odl {
+			gpios = <&gpioa 2 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_DOWN_L";
+		};
+		gpio_volup_btn_odl: volup_btn_odl {
+			gpios = <&gpio9 3 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_UP_L";
+		};
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		i2c_ec_i2c_eeprom: ec_i2c_eeprom {
+			i2c-port = <&i2c0_0>;
+			enum-names = "I2C_PORT_EEPROM";
+		};
+		i2c_ec_i2c_sensor: ec_i2c_sensor {
+			i2c-port = <&i2c1_0>;
+			enum-names = "I2C_PORT_SENSOR";
+		};
+		i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 {
+			i2c-port = <&i2c3_0>;
+			enum-names = "I2C_PORT_USB_C0_TCPC";
+		};
+		i2c_ec_i2c_sub_usb_c1: ec_i2c_sub_usb_c1 {
+			i2c-port = <&i2c5_1>;
+			enum-names = "I2C_PORT_USB_C1_TCPC";
+		};
+		i2c_ec_i2c_batt: ec_i2c_batt {
+			i2c-port = <&i2c7_0>;
+			enum-names = "I2C_PORT_BATTERY";
+		};
+	};
+};
+
+&adc0 {
+	status = "okay";
+	pinctrl-0 = <&adc0_chan0_gp45
+		     &adc0_chan1_gp44
+		     &adc0_chan4_gp41
+		     &adc0_chan6_gp34
+		     &adc0_chan10_gpe0
+		     &adc0_chan11_gpc7>;
+	pinctrl-names = "default";
+};
+
+&i2c0_0 {
+	status = "okay";
+	pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>;
+	pinctrl-names = "default";
+};
+
+&i2c1_0 {
+	status = "okay";
+	pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>;
+	pinctrl-names = "default";
+};
+
+&i2c3_0 {
+	status = "okay";
+	pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>;
+	pinctrl-names = "default";
+};
+
+&i2c5_1 {
+	status = "okay";
+	pinctrl-0 = <&i2c5_1_sda_scl_gpf4_f5>;
+	pinctrl-names = "default";
+};
+
+&i2c7_0 {
+	status = "okay";
+	pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>;
+	pinctrl-names = "default";
+};
+
+&i2c_ctrl0 {
+	status = "okay";
+};
+
+&i2c_ctrl1 {
+	status = "okay";
+};
+
+&i2c_ctrl3 {
+	status = "okay";
+};
+
+&i2c_ctrl5 {
+	status = "okay";
+};
+
+&i2c_ctrl7 {
+	status = "okay";
+};
diff --git a/zephyr/projects/nissa/xivu/keyboard.dts b/zephyr/projects/nissa/xivu/keyboard.dts
new file mode 100644
index 0000000000..5248c4aaff
--- /dev/null
+++ b/zephyr/projects/nissa/xivu/keyboard.dts
@@ -0,0 +1,34 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+&cros_kb_raw {
+	status = "okay";
+	/* No KSO2 (it's inverted and implemented by GPIO) */
+	pinctrl-0 = <
+		&ksi0_gp31
+		&ksi1_gp30
+		&ksi2_gp27
+		&ksi3_gp26
+		&ksi4_gp25
+		&ksi5_gp24
+		&ksi6_gp23
+		&ksi7_gp22
+		&kso00_gp21
+		&kso01_gp20
+		&kso03_gp16
+		&kso04_gp15
+		&kso05_gp14
+		&kso06_gp13
+		&kso07_gp12
+		&kso08_gp11
+		&kso09_gp10
+		&kso10_gp07
+		&kso11_gp06
+		&kso12_gp05
+		&kso13_gp04
+		&kso14_gp82
+	>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/projects/nissa/xivu/led_pins.dts b/zephyr/projects/nissa/xivu/led_pins.dts
new file mode 100644
index 0000000000..d85004a0c9
--- /dev/null
+++ b/zephyr/projects/nissa/xivu/led_pins.dts
@@ -0,0 +1,94 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	pwm_pins {
+		compatible = "cros-ec,pwm-pin-config";
+		pwm_led_y_c0: pwm_led_y_c0 {
+			#led-pin-cells = <1>;
+			pwms = <&pwm2 0 PWM_HZ(324) PWM_POLARITY_INVERTED>;
+		};
+
+		pwm_led_w_c0: pwm_led_w_c0 {
+			#led-pin-cells = <1>;
+			pwms = <&pwm0 0 PWM_HZ(324) PWM_POLARITY_INVERTED>;
+		};
+
+		pwm_led_y_c1: pwm_led_y_c1 {
+			#led-pin-cells = <1>;
+			pwms = <&pwm6 0 PWM_HZ(324) PWM_POLARITY_INVERTED>;
+		};
+
+		pwm_led_w_c1: pwm_led_w_c1 {
+			#led-pin-cells = <1>;
+			pwms = <&pwm1 0 PWM_HZ(324) PWM_POLARITY_INVERTED>;
+		};
+	};
+
+	pwm-led-pins {
+		compatible = "cros-ec,pwm-led-pins";
+
+		color_off: color-off {
+			led-color = "LED_OFF";
+			led-id = "EC_LED_ID_BATTERY_LED";
+			led-pins = <&pwm_led_y_c0 0>,
+				   <&pwm_led_y_c1 0>,
+				   <&pwm_led_w_c0 0>,
+				   <&pwm_led_w_c1 0>;
+		};
+
+		color_amber: color-amber {
+			led-color = "LED_AMBER";
+			led-id = "EC_LED_ID_BATTERY_LED";
+			br-color = "EC_LED_COLOR_AMBER";
+			led-pins = <&pwm_led_y_c0 1>,
+				   <&pwm_led_y_c1 1>,
+				   <&pwm_led_w_c0 0>,
+				   <&pwm_led_w_c1 0>;
+		};
+
+		color_white: color-white {
+			led-color = "LED_WHITE";
+			led-id = "EC_LED_ID_BATTERY_LED";
+			br-color = "EC_LED_COLOR_WHITE";
+			led-pins = <&pwm_led_y_c0 0>,
+				   <&pwm_led_y_c1 0>,
+				   <&pwm_led_w_c0 1>,
+				   <&pwm_led_w_c1 1>;
+		};
+	};
+};
+
+/* LED2 */
+&pwm0 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm0_gpc3>;
+	pinctrl-names = "default";
+};
+
+/* LED3 */
+&pwm1 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm1_gpc2>;
+	pinctrl-names = "default";
+};
+
+/* LED1 */
+&pwm2 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm2_gpc4>;
+	pinctrl-names = "default";
+};
+
+/* LED0 */
+&pwm6 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm6_gpc0>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/projects/nissa/xivu/led_policy.dts b/zephyr/projects/nissa/xivu/led_policy.dts
new file mode 100644
index 0000000000..3f7efcf1bf
--- /dev/null
+++ b/zephyr/projects/nissa/xivu/led_policy.dts
@@ -0,0 +1,114 @@
+/ {
+	led-colors {
+		compatible = "cros-ec,led-policy";
+
+		power-state-charge {
+			charge-state = "PWR_STATE_CHARGE";
+			/* Battery percent range (>= Empty, <= 94%) */
+			batt-lvl = <0 94>;
+
+			color-0 {
+				led-color = <&color_amber>;
+			};
+		};
+
+		power-state-near-full {
+			charge-state = "PWR_STATE_CHARGE";
+			/* Battery percent range (>= 95%, <= Full) */
+			batt-lvl = <95 100>;
+
+			color-0 {
+				led-color = <&color_white>;
+			};
+		};
+
+		power-state-discharge-s0 {
+			charge-state = "PWR_STATE_DISCHARGE";
+			chipset-state = "POWER_S0";
+			/* Battery percent range (>= 11%, <= Full) */
+			batt-lvl = <11 100>;
+
+			color-0 {
+				led-color = <&color_white>;
+			};
+		};
+
+		power-state-discharge-s3 {
+			charge-state = "PWR_STATE_DISCHARGE";
+			chipset-state = "POWER_S3";
+
+			/* White 1 sec, off 3 sec */
+			color-0 {
+				led-color = <&color_white>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <3000>;
+			};
+		};
+
+		power-state-discharge-s5 {
+			charge-state = "PWR_STATE_DISCHARGE";
+			chipset-state = "POWER_S5";
+
+			color-0 {
+				led-color = <&color_off>;
+			};
+		};
+
+		power-state-discharge-s0-batt-low {
+			charge-state = "PWR_STATE_DISCHARGE";
+			chipset-state = "POWER_S0";
+			/* Battery percent range (>= Empty, <= 10%) */
+			batt-lvl = <0 10>;
+
+			/* Amber 1 sec, off 3 sec */
+			color-0 {
+				led-color = <&color_amber>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <3000>;
+			};
+		};
+
+		power-state-error-s0 {
+			charge-state = "PWR_STATE_ERROR";
+			chipset-state = "POWER_S0";
+			/* Amber 1 sec, off 1 sec */
+			color-0 {
+				led-color = <&color_amber>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <1000>;
+			};
+		};
+
+		power-state-error-s3 {
+			charge-state = "PWR_STATE_ERROR";
+			chipset-state = "POWER_S3";
+			/* White 1 sec, off 3 sec */
+			color-0 {
+				led-color = <&color_white>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <3000>;
+			};
+		};
+
+		power-state-error-s5 {
+			charge-state = "PWR_STATE_ERROR";
+			chipset-state = "POWER_S5";
+
+			color-0 {
+				led-color = <&color_off>;
+			};
+		};
+	};
+};
diff --git a/zephyr/projects/nissa/craask_motionsense.dts b/zephyr/projects/nissa/xivu/motionsense.dts
index 8870f2e94f..332252c4ef 100644
--- a/zephyr/projects/nissa/craask_motionsense.dts
+++ b/zephyr/projects/nissa/xivu/motionsense.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,11 +25,9 @@
 	motionsense-mutex {
 		compatible = "cros-ec,motionsense-mutex";
 		lid_mutex: lid-mutex {
-			label = "LID_MUTEX";
 		};
 
 		base_mutex: base-mutex {
-			label = "BASE_MUTEX";
 		};
 	};
 
@@ -37,14 +35,14 @@
 	motionsense-rotation-ref {
 		compatible = "cros-ec,motionsense-rotation-ref";
 		lid_rot_ref: lid-rotation-ref {
-			mat33 = <(-1) 0 0
-				 0 1 0
+			mat33 = <0 1 0
+				 1 0 0
 				 0 0 (-1)>;
 		};
 
 		base_rot_ref: base-rotation-ref {
-			mat33 = <(-1) 0 0
-				 0 (-1) 0
+			mat33 = <0 (-1) 0
+				 1 0 0
 				 0 0 1>;
 		};
 	};
@@ -59,7 +57,12 @@
 	 * "struct als_drv_data_t" in accelgyro.h
 	 */
 	motionsense-sensor-data {
-		lsm6dso_data: lsm6dso-drv-data {
+		lsm6dso_accel_data: lsm6dso-accel-drv-data {
+			compatible = "cros-ec,drvdata-lsm6dso";
+			status = "okay";
+		};
+
+		lsm6dso_gyro_data: lsm6dso-gyro-drv-data {
 			compatible = "cros-ec,drvdata-lsm6dso";
 			status = "okay";
 		};
@@ -72,74 +75,71 @@
 
 	/*
 	 * List of motion sensors that creates motion_sensors array.
-	 * The label "lid_accel" and "base_accel" are used to indicate
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
 	 * motion sensor IDs for lid angle calculation.
+	 * TODO(b/238139272): The first entries of the array must be
+	 * accelerometers,then gyroscope. Fix this dependency in the DTS
+	 * processing which makes the devicetree entries independent.
 	 */
 	motionsense-sensor {
-		base_accel: base-accel {
-			compatible = "cros-ec,lsm6dso-accel";
+		lid_accel: lid-accel {
+			compatible = "cros-ec,lis2dw12";
 			status = "okay";
 
-			label = "Base Accel";
 			active-mask = "SENSOR_ACTIVE_S0_S3";
-			location = "MOTIONSENSE_LOC_BASE";
-			mutex = <&base_mutex>;
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&lid_mutex>;
 			port = <&i2c_ec_i2c_sensor>;
-			rot-standard-ref = <&base_rot_ref>;
-			drv-data = <&lsm6dso_data>;
+			rot-standard-ref = <&lid_rot_ref>;
+			default-range = <2>;
+			drv-data = <&lis2dw12_data>;
+			i2c-spi-addr-flags = "LIS2DWL_ADDR0_FLAGS";
 			configs {
 				compatible =
 					"cros-ec,motionsense-sensor-config";
 				ec-s0 {
-					label = "SENSOR_CONFIG_EC_S0";
 					odr = <(10000 | ROUND_UP_FLAG)>;
 				};
 				ec-s3 {
-					label = "SENSOR_CONFIG_EC_S3";
 					odr = <(10000 | ROUND_UP_FLAG)>;
 				};
 			};
 		};
 
-		base_gyro: base-gyro {
-			compatible = "cros-ec,lsm6dso-gyro";
+		base_accel: base-accel {
+			compatible = "cros-ec,lsm6dso-accel";
 			status = "okay";
 
-			label = "Base Gyro";
 			active-mask = "SENSOR_ACTIVE_S0_S3";
 			location = "MOTIONSENSE_LOC_BASE";
 			mutex = <&base_mutex>;
 			port = <&i2c_ec_i2c_sensor>;
 			rot-standard-ref = <&base_rot_ref>;
-			drv-data = <&lsm6dso_data>;
-		};
-
-		lid_accel: lid-accel {
-			compatible = "cros-ec,lis2dw12";
-			status = "okay";
-
-			label = "Lid Accel";
-			active-mask = "SENSOR_ACTIVE_S0_S3";
-			location = "MOTIONSENSE_LOC_LID";
-			mutex = <&lid_mutex>;
-			port = <&i2c_ec_i2c_sensor>;
-			rot-standard-ref = <&lid_rot_ref>;
-			default-range = <2>;
-			drv-data = <&lis2dw12_data>;
-			i2c-spi-addr-flags = "LIS2DWL_ADDR0_FLAGS";
+			drv-data = <&lsm6dso_accel_data>;
 			configs {
 				compatible =
 					"cros-ec,motionsense-sensor-config";
 				ec-s0 {
-					label = "SENSOR_CONFIG_EC_S0";
 					odr = <(10000 | ROUND_UP_FLAG)>;
 				};
 				ec-s3 {
-					label = "SENSOR_CONFIG_EC_S3";
 					odr = <(10000 | ROUND_UP_FLAG)>;
 				};
 			};
 		};
+
+		base_gyro: base-gyro {
+			compatible = "cros-ec,lsm6dso-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&base_mutex>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			default-range = <(1000 | ROUND_UP_FLAG)>; /* dps */
+			drv-data = <&lsm6dso_gyro_data>;
+		};
 	};
 
 	motionsense-sensor-info {
diff --git a/zephyr/projects/nissa/xivu/overlay.dts b/zephyr/projects/nissa/xivu/overlay.dts
new file mode 100644
index 0000000000..de45db75e7
--- /dev/null
+++ b/zephyr/projects/nissa/xivu/overlay.dts
@@ -0,0 +1,357 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <cros/thermistor/thermistor.dtsi>
+
+/ {
+	aliases {
+		gpio-cbi-wp = &gpio_ec_cbi_wp;
+		gpio-wp = &gpio_ec_wp_odl;
+		int-wp = &int_wp_l;
+		gpio-kbd-kso2 = &gpio_ec_kso_02_inv;
+	};
+
+	ec-console {
+		compatible = "ec-console";
+		disabled = "events", "lpc", "hostcmd";
+	};
+
+	batteries {
+		default_battery: smp_c31n2005 {
+			compatible = "smp,c31n2005", "battery-smart";
+		};
+	};
+
+	hibernate-wake-pins {
+		compatible = "cros-ec,hibernate-wake-pins";
+		wakeup-irqs = <
+			&int_power_button
+			&int_lid_open
+		>;
+	};
+
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_power_button: power_button {
+			irq-pin = <&gpio_gsc_ec_pwr_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_button_interrupt";
+		};
+		int_wp_l: wp_l {
+			irq-pin = <&gpio_ec_wp_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "switch_interrupt";
+		};
+		int_lid_open: lid_open {
+			irq-pin = <&gpio_lid_open>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "lid_interrupt";
+		};
+		int_tablet_mode: tablet_mode {
+			irq-pin = <&gpio_tablet_mode_l>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "gmr_tablet_switch_isr";
+		};
+		int_imu: ec_imu {
+			irq-pin = <&gpio_imu_int_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "lsm6dso_interrupt";
+		};
+		int_vol_down: vol_down {
+			irq-pin = <&gpio_voldn_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+		int_vol_up: vol_up {
+			irq-pin = <&gpio_volup_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "button_interrupt";
+		};
+		int_usb_c0: usb_c0 {
+			irq-pin = <&gpio_usb_c0_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "usb_interrupt";
+		};
+		int_usb_c1: usb_c1 {
+			irq-pin = <&gpio_sb_1>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "usb_interrupt";
+		};
+	};
+
+	named-gpios {
+		gpio_sb_1: sb-1 {
+			gpios = <&gpio0 2 GPIO_PULL_UP>;
+			no-auto-init;
+		};
+
+		gpio_sb_2: sb-2 {
+			gpios = <&gpiod 4 GPIO_OUTPUT>;
+			no-auto-init;
+		};
+
+		/*
+		 * Set I2C pins for type C sub-board to be low voltage (I2C5_1).
+		 * We do this for all boards, since the pins are 3.3V tolerant,
+		 * and the only 2 types of sub-boards used on nivviks both have
+		 * type-C ports on them.
+		 */
+		gpio_sb_3: sb-3 {
+			gpios = <&gpiof 4 (GPIO_OPEN_DRAIN | GPIO_VOLTAGE_1P8)>;
+			no-auto-init;
+		};
+		gpio_sb_4: sb-4 {
+			gpios = <&gpiof 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+			no-auto-init;
+		};
+	};
+
+	/*
+	 * Aliases used for sub-board GPIOs.
+	 */
+	aliases {
+		/*
+		 * Input GPIO when used with type-C port 1
+		 */
+		gpio-usb-c1-int-odl = &gpio_sb_1;
+		gpio-en-rails-odl = &gpio_sb_1;
+		/*
+		 * Sub-board with type A USB, enable.
+		 */
+		gpio-en-usb-a1-vbus = &gpio_sb_2;
+		/*
+		 * Enable S5 rails for LTE sub-board
+		 */
+		gpio-en-sub-s5-rails = &gpio_sb_2;
+	};
+
+	temp_memory: memory {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_1>;
+	};
+	temp_ambient: ambient {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_2>;
+	};
+	temp_charger1: charger1 {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_3>;
+	};
+	temp_charger2: charger2 {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_4>;
+	};
+
+	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
+		memory {
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			temp_host_release_halt = <80>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_memory>;
+		};
+		ambient {
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			temp_host_release_halt = <80>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_ambient>;
+		};
+		charger1 {
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			temp_host_release_halt = <80>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_charger1>;
+		};
+		charger2 {
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			temp_host_release_halt = <80>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_charger2>;
+		};
+	};
+
+	usba {
+		compatible = "cros-ec,usba-port-enable-pins";
+		/*
+		 * sb_2 is only configured as GPIO when USB-A1 is present,
+		 * but it's still safe to control when disabled.
+		 *
+		 * ILIM_SEL pins are referred to by legacy enum name,
+		 * GPIO_USB*_ILIM_SEL. The one for port A1 is unused on
+		 * sub-boards that don't have USB-A so is safe to control
+		 * regardless of system configuration.
+		 */
+		enable-pins = <&gpio_en_usb_a0_vbus &gpio_sb_2>;
+		status = "okay";
+	};
+
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+			bc12 = <&bc12_port0>;
+			chg = <&chg_port0>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_0>;
+			};
+		};
+		port0-muxes {
+			virtual_mux_0: virtual-mux-0 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+		/*
+		 * TODO(b:211693800): port1 may not be present on some
+		 * sub-boards.
+		 */
+		port1@1 {
+			compatible = "named-usbc-port";
+			reg = <1>;
+			bc12 = <&bc12_port1>;
+			chg = <&chg_port1>;
+			usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_1 &anx7483_mux_1>;
+			};
+			usb_mux_chain_1_no_mux: usb-mux-chain-1-no-mux {
+				compatible = "cros-ec,usb-mux-chain";
+				alternative-chain;
+				usb-muxes = <&virtual_mux_1>;
+			};
+		};
+		port1-muxes {
+			virtual_mux_1: virtual-mux-1 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+	};
+
+	unused-pins {
+		compatible = "unused-gpios";
+		unused-gpios =
+			<&gpio8 5 0>,
+			<&gpio3 6 0>,
+			<&gpiod 7 0>,
+			<&gpio6 0 0>,
+			<&gpiof 2 0>,
+			<&gpiof 3 0>;
+	 };
+};
+
+&thermistor_3V3_51K1_47K_4050B {
+	status = "okay";
+};
+
+&adc_ec_vsense_pp3300_s5 {
+	/*
+	 * Voltage divider on input has 47k upper and 220k lower legs with
+	 * 2714 mV full-scale reading on the ADC. Apply the largest possible
+	 * multiplier (without overflowing int32) to get the best possible
+	 * approximation of the actual ratio, but derate by a factor of two to
+	 * ensure unexpectedly high values won't overflow.
+	 */
+	mul = <(791261 / 2)>;
+	div = <(651975 / 2)>;
+};
+
+/* Set bus speeds for I2C */
+&i2c0_0 {
+	label = "I2C_EEPROM";
+	clock-frequency = <I2C_BITRATE_FAST>;
+
+	cbi_eeprom: eeprom@50 {
+		compatible = "atmel,at24";
+		reg = <0x50>;
+		size = <2048>;
+		pagesize = <16>;
+		address-width = <8>;
+		timeout = <5>;
+	};
+};
+
+&i2c1_0 {
+	label = "I2C_SENSOR";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&i2c3_0 {
+	label = "I2C_USB_C0_TCPC";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+
+	bc12_port0: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+		/*
+		 * BC1.2 interrupt is shared with TCPC, so
+		 * IRQ is not specified here and handled by
+		 * usb_c0_interrupt.
+		 */
+	};
+
+	chg_port0: isl923x@9 {
+		compatible = "intersil,isl923x";
+		status = "okay";
+		reg = <0x9>;
+	};
+};
+
+&i2c5_1 {
+	label = "I2C_SUB_C1_TCPC";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+
+	bc12_port1: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+	};
+
+	chg_port1: isl923x@9 {
+		compatible = "intersil,isl923x";
+		status = "okay";
+		reg = <0x9>;
+	};
+
+	anx7483_mux_1: anx7483-mux-1@3e {
+		compatible = "analogix,anx7483";
+		reg = <0x3e>;
+		board-set = "anx7483_set_default_tuning";
+	};
+};
+
+&i2c7_0 {
+	label = "I2C_BATTERY";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+};
+
+&pwm6 {
+	status = "okay";
+	pinctrl-0 = <&pwm6_gpc0>;
+	pinctrl-names = "default";
+};
+
+/* host interface */
+&espi0 {
+	status = "okay";
+	pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/projects/nissa/xivu/power_signals.dts b/zephyr/projects/nissa/xivu/power_signals.dts
new file mode 100644
index 0000000000..1d2b23069d
--- /dev/null
+++ b/zephyr/projects/nissa/xivu/power_signals.dts
@@ -0,0 +1,220 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	chosen {
+		intel-ap-pwrseq,espi = &espi0;
+	};
+
+	common-pwrseq {
+		compatible = "intel,ap-pwrseq";
+
+		sys-pwrok-delay = <10>;
+		all-sys-pwrgd-timeout = <20>;
+	};
+
+	pwr-en-pp5000-s5 {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PP5000_S5 enable output to regulator";
+		enum-name = "PWR_EN_PP5000_A";
+		gpios = <&gpio4 0 0>;
+		output;
+	};
+	pwr-en-pp3300-s5 {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PP3300_S5 enable output to LS";
+		enum-name = "PWR_EN_PP3300_A";
+		gpios = <&gpiob 6 0>;
+		output;
+	};
+	pwr-pg-ec-rsmrst-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST power good from regulator";
+		enum-name = "PWR_RSMRST";
+		gpios = <&gpio9 4 0>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-ec-pch-rsmrst-odl {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST output to PCH";
+		enum-name = "PWR_EC_PCH_RSMRST";
+		gpios = <&gpioa 6 0>;
+		output;
+	};
+	pwr-slp-s0-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_S0_L input from PCH";
+		enum-name = "PWR_SLP_S0";
+		gpios = <&gpio9 7 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-slp-s3-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_S3_L input from PCH";
+		enum-name = "PWR_SLP_S3";
+		gpios = <&gpioa 5 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-slp-sus-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_SUS_L input from PCH";
+		enum-name = "PWR_SLP_SUS";
+		gpios = <&gpio6 2 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-ec-soc-dsw-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "DSW_PWROK output to PCH";
+		enum-name = "PWR_EC_SOC_DSW_PWROK";
+		gpios = <&gpio6 1 0>;
+		output;
+	};
+	pwr-vccst-pwrgd-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "VCCST_PWRGD output to PCH";
+		enum-name = "PWR_VCCST_PWRGD";
+		gpios = <&gpioa 4 GPIO_OPEN_DRAIN>;
+		output;
+	};
+	pwr-imvp9-vrrdy-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "VRRDY input from IMVP9";
+		enum-name = "PWR_IMVP9_VRRDY";
+		gpios = <&gpio4 3 0>;
+	};
+	pwr-pch-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PCH_PWROK output to PCH";
+		enum-name = "PWR_PCH_PWROK";
+		gpios = <&gpio7 2 GPIO_OPEN_DRAIN>;
+		output;
+	};
+	pwr-ec-pch-sys-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_PWROK output to PCH";
+		enum-name = "PWR_EC_PCH_SYS_PWROK";
+		gpios = <&gpio3 7 0>;
+		output;
+	};
+	pwr-sys-rst-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_RESET# output to PCH";
+		enum-name = "PWR_SYS_RST";
+		gpios = <&gpioc 5 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>;
+		output;
+	};
+	pwr-slp-s4 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S4 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S4";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4";
+		vw-invert;
+	};
+	pwr-slp-s5 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S5 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S5";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5";
+		vw-invert;
+	};
+	pwr-all-sys-pwrgd {
+		compatible = "intel,ap-pwrseq-external";
+		dbg-label = "Combined all power good";
+		enum-name = "PWR_ALL_SYS_PWRGD";
+	};
+	pwr-adc-pp3300 {
+		compatible = "intel,ap-pwrseq-adc";
+		dbg-label = "PP3300 PWROK (from ADC)";
+		enum-name = "PWR_DSW_PWROK";
+		trigger-high = <&cmp_pp3300_s5_high>;
+		trigger-low = <&cmp_pp3300_s5_low>;
+	};
+	pwr-adc-pp1p05 {
+		compatible = "intel,ap-pwrseq-adc";
+		dbg-label = "PP1P05 PWROK (from ADC)";
+		enum-name = "PWR_PG_PP1P05";
+		trigger-high = <&cmp_pp1p05_high>;
+		trigger-low = <&cmp_pp1p05_low>;
+	};
+
+	adc-cmp {
+		cmp_pp3300_s5_high: pp3300_high {
+			compatible = "nuvoton,adc-cmp";
+			io-channels = <&adc0 6>;
+			comparison = "ADC_CMP_NPCX_GREATER";
+			/*
+			 * This is 90% of nominal voltage considering voltage
+			 * divider on ADC input.
+			 */
+			threshold-mv = <2448>;
+		};
+		cmp_pp3300_s5_low: pp3300_low {
+			compatible = "nuvoton,adc-cmp";
+			io-channels = <&adc0 6>;
+			comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL";
+			threshold-mv = <2448>;
+		};
+		cmp_pp1p05_high: pp1p05_high {
+			compatible = "nuvoton,adc-cmp";
+			io-channels = <&adc0 4>;
+			comparison = "ADC_CMP_NPCX_GREATER";
+			/* Setting at 90% of nominal voltage */
+			threshold-mv = <945>;
+		};
+		cmp_pp1p05_low: pp1p05_low {
+			compatible = "nuvoton,adc-cmp";
+			io-channels = <&adc0 4>;
+			comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL";
+			threshold-mv = <945>;
+		};
+	};
+};
+
+/*
+ * Because the power signals directly reference the GPIOs,
+ * the correspinding named-gpios need to have no-auto-init set.
+ */
+&gpio_ec_soc_dsw_pwrok {
+	no-auto-init;
+};
+&gpio_ec_soc_pch_pwrok_od {
+	no-auto-init;
+};
+&gpio_ec_soc_rsmrst_l {
+	no-auto-init;
+};
+&gpio_ec_soc_sys_pwrok {
+	no-auto-init;
+};
+&gpio_ec_soc_vccst_pwrgd_od {
+	no-auto-init;
+};
+&gpio_en_pp3300_s5 {
+	no-auto-init;
+};
+&gpio_en_pp5000_s5 {
+	no-auto-init;
+};
+&gpio_imvp91_vrrdy_od {
+	no-auto-init;
+};
+&gpio_rsmrst_pwrgd_l {
+	no-auto-init;
+};
+&gpio_slp_s0_l {
+	no-auto-init;
+};
+&gpio_slp_s3_l {
+	no-auto-init;
+};
+&gpio_slp_s4_l {
+	no-auto-init;
+};
+&gpio_slp_sus_l {
+	no-auto-init;
+};
+&gpio_sys_rst_odl {
+	no-auto-init;
+};
diff --git a/zephyr/projects/nissa/xivu/prj.conf b/zephyr/projects/nissa/xivu/prj.conf
new file mode 100644
index 0000000000..ab3bb044e2
--- /dev/null
+++ b/zephyr/projects/nissa/xivu/prj.conf
@@ -0,0 +1,11 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_BOARD_XIVU=y
+CONFIG_PLATFORM_EC_OCPC=y
+CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSO=y
+
+# LED
+CONFIG_PLATFORM_EC_LED_COMMON=n
+CONFIG_PLATFORM_EC_LED_DT=y
diff --git a/zephyr/projects/nissa/xivu/src/charger.c b/zephyr/projects/nissa/xivu/src/charger.c
new file mode 100644
index 0000000000..5021a55758
--- /dev/null
+++ b/zephyr/projects/nissa/xivu/src/charger.c
@@ -0,0 +1,69 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/logging/log.h>
+
+#include "battery.h"
+#include "charger.h"
+#include "charger/isl923x_public.h"
+#include "console.h"
+#include "extpower.h"
+#include "usb_pd.h"
+#include "nissa_common.h"
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+int extpower_is_present(void)
+{
+	int port;
+	int rv;
+	bool acok;
+
+	for (port = 0; port < board_get_usb_pd_port_count(); port++) {
+		rv = raa489000_is_acok(port, &acok);
+		if ((rv == EC_SUCCESS) && acok)
+			return 1;
+	}
+
+	return 0;
+}
+
+/*
+ * Xivu does not have a GPIO indicating whether extpower is present,
+ * so detect using the charger(s).
+ */
+__override void board_check_extpower(void)
+{
+	static int last_extpower_present;
+	int extpower_present_p0 = 0;
+	int extpower_present_p1 = 0;
+
+	int extpower_present = extpower_is_present();
+
+	if (last_extpower_present ^ extpower_present)
+		extpower_handle_update(extpower_present);
+
+	last_extpower_present = extpower_present;
+
+	if (pd_is_connected(0))
+		extpower_present_p0 = extpower_is_present();
+	else if (pd_is_connected(1))
+		extpower_present_p1 = extpower_is_present();
+
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_acok_otg_c0),
+			extpower_present_p0);
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_acok_otg_c1),
+			extpower_present_p1);
+}
+
+__override void board_hibernate(void)
+{
+	/* Shut down the chargers */
+	if (board_get_usb_pd_port_count() == 2)
+		raa489000_hibernate(CHARGER_SECONDARY, true);
+	raa489000_hibernate(CHARGER_PRIMARY, true);
+	LOG_INF("Charger(s) hibernated");
+	cflush();
+}
diff --git a/zephyr/projects/nissa/xivu/src/keyboard.c b/zephyr/projects/nissa/xivu/src/keyboard.c
new file mode 100644
index 0000000000..ef799fb1d2
--- /dev/null
+++ b/zephyr/projects/nissa/xivu/src/keyboard.c
@@ -0,0 +1,29 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+
+static const struct ec_response_keybd_config xivu_kb_legacy = {
+	.num_top_row_keys = 10,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_VOL_MUTE,		/* 8 */
+		TK_VOL_DOWN,		/* T9 */
+		TK_VOL_UP,		/* T10 */
+	},
+	.capabilities = KEYBD_CAP_SCRNLOCK_KEY,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &xivu_kb_legacy;
+}
diff --git a/zephyr/projects/nissa/src/craask/usbc.c b/zephyr/projects/nissa/xivu/src/usbc.c
index 32a390e502..a15460a212 100644
--- a/zephyr/projects/nissa/src/craask/usbc.c
+++ b/zephyr/projects/nissa/xivu/src/usbc.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -54,8 +54,7 @@ int board_is_sourcing_vbus(int port)
 
 int board_set_active_charge_port(int port)
 {
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	int i;
 	int old_port;
 
@@ -233,8 +232,7 @@ static void usbc_interrupt_trigger(int port)
 	usb_charger_task_set_event(port, USB_CHG_EVENT_BC12);
 }
 
-static inline void poll_usb_gpio(int port,
-				 const struct gpio_dt_spec *gpio,
+static inline void poll_usb_gpio(int port, const struct gpio_dt_spec *gpio,
 				 const struct deferred_data *ud)
 {
 	if (!gpio_pin_get_dt(gpio)) {
@@ -243,17 +241,15 @@ static inline void poll_usb_gpio(int port,
 	}
 }
 
-static void poll_c0_int (void)
+static void poll_c0_int(void)
 {
-	poll_usb_gpio(0,
-		      GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl),
+	poll_usb_gpio(0, GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl),
 		      &poll_c0_int_data);
 }
 
-static void poll_c1_int (void)
+static void poll_c1_int(void)
 {
-	poll_usb_gpio(1,
-		      GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl),
+	poll_usb_gpio(1, GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl),
 		      &poll_c1_int_data);
 }
 
diff --git a/zephyr/projects/nissa/yaviks/gpio.dts b/zephyr/projects/nissa/yaviks/gpio.dts
new file mode 100644
index 0000000000..0158d5b19b
--- /dev/null
+++ b/zephyr/projects/nissa/yaviks/gpio.dts
@@ -0,0 +1,242 @@
+/*
+ * Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc {
+			enum-name = "ADC_PP1050_PROC";
+			io-channels = <&adc0 14>;
+		};
+		adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 {
+			enum-name = "ADC_PP3300_S5";
+			io-channels = <&adc0 0>;
+		};
+		adc_temp_sensor_1: temp_sensor_1 {
+			enum-name = "ADC_TEMP_SENSOR_1";
+			io-channels = <&adc0 2>;
+		};
+		adc_temp_sensor_2: temp_sensor_2 {
+			enum-name = "ADC_TEMP_SENSOR_2";
+			io-channels = <&adc0 3>;
+		};
+		adc_temp_sensor_3: temp_sensor_3 {
+			enum-name = "ADC_TEMP_SENSOR_3";
+			io-channels = <&adc0 13>;
+		};
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		gpio_all_sys_pwrgd: all_sys_pwrgd {
+			gpios = <&gpiob 7 GPIO_INPUT>;
+		};
+		gpio_ccd_mode_odl: ccd_mode_odl {
+			gpios = <&gpioh 5 GPIO_INPUT>;
+			enum-name = "GPIO_CCD_MODE_ODL";
+		};
+		gpio_cpu_c10_gate_l: cpu_c10_gate_l {
+			gpios = <&gpiog 1 GPIO_INPUT>;
+		};
+		gpio_ec_battery_pres_odl: ec_battery_pres_odl {
+			gpios = <&gpioi 4 GPIO_INPUT>;
+			enum-name = "GPIO_BATT_PRES_ODL";
+		};
+		gpio_ec_cbi_wp: ec_cbi_wp {
+			gpios = <&gpioj 5 GPIO_OUTPUT>;
+		};
+		gpio_ec_edp_bl_en_od: ec_edp_bl_en_od {
+			gpios = <&gpiok 4 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_ENABLE_BACKLIGHT";
+		};
+		gpio_ec_entering_rw: ec_entering_rw {
+			gpios = <&gpioc 7 GPIO_OUTPUT>;
+			enum-name = "GPIO_ENTERING_RW";
+		};
+		gpio_ec_gsc_packet_mode: ec_gsc_packet_mode {
+			gpios = <&gpioh 1 GPIO_OUTPUT>;
+			enum-name = "GPIO_PACKET_MODE_EN";
+		};
+		gpio_ec_pch_wake_odl: ec_pch_wake_odl {
+			gpios = <&gpiob 2 GPIO_ODR_LOW>;
+		};
+		gpio_ec_prochot_odl: ec_prochot_odl {
+			gpios = <&gpioi 1 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>;
+		};
+		gpio_ec_soc_dsw_pwrok: ec_soc_dsw_pwrok {
+			gpios = <&gpiol 7 GPIO_OUTPUT>;
+			no-auto-init;
+		};
+		gpio_ec_soc_hdmi_hpd: ec_soc_hdmi_hpd {
+			gpios = <&gpiok 7 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_int_odl: ec_soc_int_odl {
+			gpios = <&gpiod 5 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_EC_INT_L";
+		};
+		gpio_ec_soc_pch_pwrok_od: ec_soc_pch_pwrok_od {
+			gpios = <&gpiod 6 GPIO_ODR_HIGH>;
+			no-auto-init;
+		};
+		gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl {
+			gpios = <&gpiob 6 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_PCH_PWRBTN_L";
+		};
+		gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l {
+			gpios = <&gpioh 0 GPIO_OUTPUT>;
+			no-auto-init;
+		};
+		gpio_ec_soc_rtcrst: ec_soc_rtcrst {
+			gpios = <&gpiok 2 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_sys_pwrok: ec_soc_sys_pwrok {
+			gpios = <&gpiof 2 GPIO_OUTPUT>;
+			no-auto-init;
+		};
+		gpio_ec_soc_vccst_pwrgd_od: ec_soc_vccst_pwrgd_od {
+			gpios = <&gpioe 5 GPIO_ODR_HIGH>;
+			no-auto-init;
+		};
+		gpio_ec_wp_odl: ec_wp_odl {
+			gpios = <&gpioa 6 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_en_kb_bl: en_kb_bl {
+			gpios = <&gpioj 3 GPIO_OUTPUT>;
+			enum-name = "GPIO_EN_KEYBOARD_BACKLIGHT";
+		};
+		gpio_en_pp3300_s5: en_pp3300_s5 {
+			gpios = <&gpioc 5 GPIO_OUTPUT>;
+			enum-name = "GPIO_TEMP_SENSOR_POWER";
+			no-auto-init;
+		};
+		gpio_en_pp5000_pen_x: en_pp5000_pen_x {
+			gpios = <&gpiob 5 GPIO_OUTPUT>;
+		};
+		gpio_en_pp5000_s5: en_pp5000_s5 {
+			gpios = <&gpiok 5 GPIO_OUTPUT>;
+			no-auto-init;
+		};
+		gpio_en_slp_z: en_slp_z {
+			gpios = <&gpiok 3 GPIO_OUTPUT>;
+		};
+		gpio_en_usb_a0_vbus: en_usb_a0_vbus {
+			gpios = <&gpiol 6 GPIO_OUTPUT>;
+		};
+		gpio_en_usb_c0_cc1_vconn: en_usb_c0_cc1_vconn {
+			gpios = <&gpioh 4 GPIO_OUTPUT>;
+		};
+		gpio_en_usb_c0_cc2_vconn: en_usb_c0_cc2_vconn {
+			gpios = <&gpioh 6 GPIO_OUTPUT>;
+		};
+		gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl {
+			gpios = <&gpioe 2 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		gpio_hdmi_sel: hdmi_sel {
+			gpios = <&gpioc 6 GPIO_OUTPUT>;
+		};
+		gpio_imvp91_vrrdy_od: imvp91_vrrdy_od {
+			gpios = <&gpioj 4 GPIO_INPUT>;
+			no-auto-init;
+		};
+		gpio_lid_open: lid_open {
+			gpios = <&gpiof 3 GPIO_INPUT>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+		gpio_pen_detect_odl: pen_detect_odl {
+			gpios = <&gpioj 1 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_pg_pp1050_mem_s3_od: pg_pp1050_mem_s3_od {
+			gpios = <&gpiod 3 GPIO_INPUT>;
+		};
+		gpio_pg_pp5000_s5_od: pg_pp5000_s5_od {
+			gpios = <&gpioe 3 GPIO_INPUT>;
+		};
+		gpio_rsmrst_pwrgd_l: rsmrst_pwrgd_l {
+			gpios = <&gpioe 1 GPIO_INPUT_PULL_UP>;
+			no-auto-init;
+		};
+		gpio_slp_s0_l: slp_s0_l {
+			gpios = <&gpioe 4 GPIO_INPUT>;
+			no-auto-init;
+		};
+		gpio_slp_s3_l: slp_s3_l {
+			gpios = <&gpioh 3 GPIO_INPUT>;
+			no-auto-init;
+		};
+		gpio_slp_s4_l: slp_s4_l {
+			gpios = <&gpioi 5 GPIO_INPUT>;
+		};
+		gpio_slp_sus_l: slp_sus_l {
+			gpios = <&gpiog 2 GPIO_INPUT>;
+			no-auto-init;
+		};
+		gpio_sub_usb_a1_ilimit_sdp: sub_usb_a1_ilimit_sdp {
+			gpios = <&gpiof 1 GPIO_OUTPUT>;
+			enum-name = "GPIO_USB2_ILIM_SEL";
+		};
+		gpio_sys_rst_odl: sys_rst_odl {
+			gpios = <&gpiod 1 GPIO_ODR_HIGH>;
+			no-auto-init;
+		};
+		gpio_usb_a0_ilimit_sdp: usb_a0_ilimit_sdp {
+			gpios = <&gpiol 5 GPIO_OUTPUT>;
+			enum-name = "GPIO_USB1_ILIM_SEL";
+		};
+		gpio_usb_c0_frs: usb_c0_frs {
+			gpios = <&gpioc 4 GPIO_OUTPUT>;
+		};
+		gpio_usb_c0_int_odl: usb_c0_int_odl {
+			gpios = <&gpiok 0 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_vccin_aux_vid0: vccin_aux_vid0 {
+			gpios = <&gpiod 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		gpio_vccin_aux_vid1: vccin_aux_vid1 {
+			gpios = <&gpiok 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		gpio_c1_charger_led_white_l: c1_charger_led_white_l {
+			gpios = <&gpiol 4 GPIO_OUTPUT_HIGH>;
+		};
+		gpio_c1_charger_led_amber_l: c1_charger_led_amber_l {
+			gpios = <&gpiod 4 GPIO_OUTPUT_HIGH>;
+		};
+		gpio_c0_charger_led_white_l: c0_charger_led_white_l {
+			gpios = <&gpioc 3 GPIO_OUTPUT_HIGH>;
+		};
+		gpio_c0_charger_led_amber_l: c0_charger_led_amber_l {
+			gpios = <&gpioj 7 GPIO_OUTPUT_HIGH>;
+		};
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		i2c_ec_i2c_eeprom: ec_i2c_eeprom {
+			i2c-port = <&i2c0>;
+			enum-names = "I2C_PORT_EEPROM";
+		};
+		i2c_ec_i2c_batt: ec_i2c_batt {
+			i2c-port = <&i2c1>;
+			enum-names = "I2C_PORT_BATTERY";
+		};
+		i2c_ec_i2c_sensor: ec_i2c_sensor {
+			i2c-port = <&i2c2>;
+			enum-names = "I2C_PORT_SENSOR";
+		};
+		i2c_ec_i2c_sub_usb_c1: ec_i2c_sub_usb_c1 {
+			i2c-port = <&i2c4>;
+			enum-names = "I2C_PORT_USB_C1_TCPC";
+		};
+		i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 {
+			i2c-port = <&i2c5>;
+			enum-names = "I2C_PORT_USB_C0_TCPC";
+		};
+	};
+};
diff --git a/zephyr/projects/nissa/yaviks/keyboard.dts b/zephyr/projects/nissa/yaviks/keyboard.dts
new file mode 100644
index 0000000000..04a620767a
--- /dev/null
+++ b/zephyr/projects/nissa/yaviks/keyboard.dts
@@ -0,0 +1,22 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	kblight {
+		compatible = "cros-ec,kblight-pwm";
+		/*
+		 * Use 324 Hz so that 32Khz clock source is used,
+		 * which is not gated in power saving mode.
+		 */
+		pwms = <&pwm0 0 PWM_HZ(324) PWM_POLARITY_NORMAL>;
+	};
+};
+
+&pwm0 {
+	status = "okay";
+	prescaler-cx = <PWM_PRESCALER_C4>;
+	pinctrl-0 = <&pwm0_gpa0_default>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/projects/nissa/yaviks/overlay.dts b/zephyr/projects/nissa/yaviks/overlay.dts
new file mode 100644
index 0000000000..301aaaa020
--- /dev/null
+++ b/zephyr/projects/nissa/yaviks/overlay.dts
@@ -0,0 +1,380 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <cros/thermistor/thermistor.dtsi>
+
+/ {
+	aliases {
+		gpio-cbi-wp = &gpio_ec_cbi_wp;
+		gpio-wp = &gpio_ec_wp_odl;
+		int-wp = &int_wp_l;
+	};
+
+	ec-console {
+		compatible = "ec-console";
+		disabled = "events", "lpc", "hostcmd";
+	};
+
+	batteries {
+		default_battery: cosmx {
+			compatible = "cosmx,gh02047xl", "battery-smart";
+		};
+		dynapack_atl_gh02047xl {
+			compatible = "dynapack,atl_gh02047xl", "battery-smart";
+		};
+		dynapack_cosmx_gh02047xl {
+			compatible = "dynapack,cosmx_gh02047xl", "battery-smart";
+		};
+		smp_coslight_gh02047xl {
+			compatible = "smp,coslight_gh02047xl", "battery-smart";
+		};
+		smp_highpower_gh02047xl {
+			compatible = "smp,highpower_gh02047xl", "battery-smart";
+		};
+	};
+
+	hibernate-wake-pins {
+		compatible = "cros-ec,hibernate-wake-pins";
+		wakeup-irqs = <
+			&int_power_button
+			&int_lid_open
+		>;
+	};
+
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_power_button: power_button {
+			irq-pin = <&gpio_gsc_ec_pwr_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_button_interrupt";
+		};
+		int_wp_l: wp_l {
+			irq-pin = <&gpio_ec_wp_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "switch_interrupt";
+		};
+		int_lid_open: lid_open {
+			irq-pin = <&gpio_lid_open>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "lid_interrupt";
+		};
+		int_usb_c0: usb_c0 {
+			irq-pin = <&gpio_usb_c0_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "usb_c0_interrupt";
+		};
+		int_usb_c1: usb_c1 {
+			irq-pin = <&gpio_sb_1>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "usb_c1_interrupt";
+		};
+	};
+
+	unused-pins {
+		compatible = "unused-gpios";
+		unused-gpios = <&gpioa 7 0>,
+			       <&gpioc 0 0>,
+			       <&gpiod 7 0>,
+			       <&gpioh 2 0>,
+			       <&gpioi 6 0>,
+			       <&gpioi 7 0>,
+			       <&gpioj 0 0>;
+	};
+
+	named-gpios {
+		/*
+		 * EC doesn't take any specific action on CC/SBU disconnect due to
+		 * fault, but this definition is useful for hardware testing.
+		 */
+		gpio_usb_c0_prot_fault_odl: usb_c0_prot_fault_odl {
+			gpios = <&gpiok 6 GPIO_INPUT_PULL_UP>;
+		};
+
+		gpio_sb_1: sb_1 {
+			gpios = <&gpioe 6 0>;
+			no-auto-init;
+		};
+		gpio_sb_2: sb_2 {
+			gpios = <&gpiof 0 0>;
+			no-auto-init;
+		};
+
+		gpio_sb_3: sb_3 {
+			gpios = <&gpioe 7 0>;
+			no-auto-init;
+		};
+		gpio_sb_4: sb_4 {
+			gpios = <&gpioe 0 0>;
+			no-auto-init;
+		};
+	};
+
+	/*
+	 * Aliases used for sub-board GPIOs.
+	 */
+	aliases {
+	  /* USB-C: interrupt input. I2C pins are on i2c_ec_i2c_sub_usb_c1 */
+		gpio-usb-c1-int-odl = &gpio_sb_1;
+		/*
+		 * USB-A: VBUS enable output
+		 * LTE: power enable output
+		 */
+		gpio-en-usb-a1-vbus = &gpio_sb_2;
+		/*
+		 * HDMI: power enable output, HDMI enable output,
+		 * and HPD input
+		 */
+		gpio-en-rails-odl = &gpio_sb_1;
+		gpio-hdmi-en-odl = &gpio_sb_4;
+		gpio-hpd-odl = &gpio_sb_3;
+		/*
+		 * Enable S5 rails for LTE sub-board
+		 */
+		gpio-en-sub-s5-rails = &gpio_sb_2;
+	};
+
+	temp_cpu: cpu {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_1>;
+	};
+	temp_5v_regulator: 5v_regulator {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_2>;
+	};
+	temp_charger: charger {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_temp_sensor_3>;
+	};
+
+	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
+		cpu {
+			temp_fan_off = <35>;
+			temp_fan_max = <60>;
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_cpu>;
+		};
+		5v_regulator {
+			temp_fan_off = <35>;
+			temp_fan_max = <60>;
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_5v_regulator>;
+		};
+		charger {
+			temp_fan_off = <35>;
+			temp_fan_max = <60>;
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			power-good-pin = <&gpio_ec_soc_dsw_pwrok>;
+			sensor = <&temp_charger>;
+		};
+	};
+
+	usba {
+		compatible = "cros-ec,usba-port-enable-pins";
+		/*
+		 * sb_2 is only configured as GPIO when USB-A1 is present,
+		 * but it's still safe to control when disabled.
+		 *
+		 * ILIM_SEL pins are referred to by legacy enum name,
+		 * GPIO_USB*_ILIM_SEL. The one for port A1 is unused on
+		 * sub-boards that don't have USB-A so is safe to control
+		 * regardless of system configuration.
+		 */
+		enable-pins = <&gpio_en_usb_a0_vbus &gpio_sb_2>;
+		status = "okay";
+	};
+
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+			bc12 = <&bc12_port0>;
+			chg = <&chg_port0>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_0>;
+			};
+		};
+		port0-muxes {
+			virtual_mux_0: virtual-mux-0 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+		port1@1 {
+			compatible = "named-usbc-port";
+			reg = <1>;
+			bc12 = <&bc12_port1>;
+			chg = <&chg_port1>;
+			usb-mux-chain-1 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&virtual_mux_1 &tcpci_mux_1>;
+			};
+			usb_mux_chain_1_no_mux: usb-mux-chain-1-no-mux {
+				compatible = "cros-ec,usb-mux-chain";
+				alternative-chain;
+				usb-muxes = <&virtual_mux_1>;
+			};
+		};
+		port1-muxes {
+			virtual_mux_1: virtual-mux-1 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+			tcpci_mux_1: tcpci-mux-1 {
+				compatible = "parade,usbc-mux-ps8xxx";
+			};
+		};
+	};
+};
+
+&thermistor_3V3_51K1_47K_4050B {
+	status = "okay";
+};
+
+&adc_ec_vsense_pp3300_s5 {
+	/*
+	 * Voltage divider on input has 47k upper and 220k lower legs with 3 V
+	 * full-scale reading on the ADC. Apply the largest possible multiplier
+	 * (without overflowing int32) to get the best possible approximation
+	 * of the actual ratio, but derate by a factor of two to ensure
+	 * unexpectedly high values won't overflow.
+	 */
+	mul = <(715828 / 2)>;
+	div = <(589820 / 2)>;
+};
+
+&adc0 {
+	pinctrl-0 = <&adc0_ch0_gpi0_default
+		     &adc0_ch2_gpi2_default
+		     &adc0_ch3_gpi3_default
+		     &adc0_ch13_gpl0_default
+		     &adc0_ch14_gpl1_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&pinctrl {
+	i2c4_clk_gpe0_sleep: i2c4_clk_gpe0_sleep {
+		pinmuxs = <&pinctrle 0 IT8XXX2_ALT_DEFAULT>;
+	};
+	i2c4_data_gpe7_sleep: i2c4_data_gpe7_sleep {
+		pinmuxs = <&pinctrle 7 IT8XXX2_ALT_DEFAULT>;
+	};
+	i2c2_clk_gpf6_default: i2c2_clk_gpf6_default {
+		gpio-voltage = "1v8";
+	};
+	i2c2_data_gpf7_default: i2c2_data_gpf7_default {
+		gpio-voltage = "1v8";
+	};
+};
+
+&i2c0 {
+	label = "I2C_EEPROM";
+	clock-frequency = <I2C_BITRATE_FAST>;
+
+	cbi_eeprom: eeprom@50 {
+		compatible = "atmel,at24";
+		reg = <0x50>;
+		label = "EEPROM_CBI";
+		size = <2048>;
+		pagesize = <16>;
+		address-width = <8>;
+		timeout = <5>;
+	};
+	pinctrl-0 = <&i2c0_clk_gpb3_default
+		     &i2c0_data_gpb4_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&i2c1 {
+	label = "I2C_BATTERY";
+	clock-frequency = <50000>;
+	pinctrl-0 = <&i2c1_clk_gpc1_default
+		     &i2c1_data_gpc2_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&i2c2 {
+	label = "I2C_SENSOR";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c2_clk_gpf6_default
+		     &i2c2_data_gpf7_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&i2c4 {
+	label = "I2C_SUB_C1_TCPC";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+	pinctrl-0 = <&i2c4_clk_gpe0_default
+		     &i2c4_data_gpe7_default>;
+	pinctrl-1 = <&i2c4_clk_gpe0_sleep
+		     &i2c4_data_gpe7_sleep>;
+	pinctrl-names = "default", "sleep";
+	status = "okay";
+
+	bc12_port1: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+	};
+
+	chg_port1: sm5803@32 {
+		compatible = "siliconmitus,sm5803";
+		status = "okay";
+		reg = <0x32>;
+	};
+};
+
+&i2c_ec_i2c_sub_usb_c1 {
+	/*
+	 * Dynamic speed setting is used for AP-controlled firmware update
+	 * of PS8745 TCPC/redriver: the AP lowers speed to 400 kHz in order
+	 * to use more efficient window programming, then sets it back when
+	 * done.
+	 */
+	dynamic-speed;
+};
+
+&i2c5 {
+	label = "I2C_USB_C0_TCPC";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+	pinctrl-0 = <&i2c5_clk_gpa4_default
+		     &i2c5_data_gpa5_default>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	bc12_port0: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+	};
+
+	chg_port0: sm5803@32 {
+		compatible = "siliconmitus,sm5803";
+		status = "okay";
+		reg = <0x32>;
+	};
+};
+
+&usbpd0 {
+	status = "okay";
+};
diff --git a/zephyr/projects/nissa/yaviks/power_signals.dts b/zephyr/projects/nissa/yaviks/power_signals.dts
new file mode 100644
index 0000000000..d64ac83150
--- /dev/null
+++ b/zephyr/projects/nissa/yaviks/power_signals.dts
@@ -0,0 +1,180 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	chosen {
+		intel-ap-pwrseq,espi = &espi0;
+	};
+
+	common-pwrseq {
+		compatible = "intel,ap-pwrseq";
+
+		sys-pwrok-delay = <10>;
+		all-sys-pwrgd-timeout = <20>;
+	};
+
+	pwr-en-pp5000-s5 {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PP5000_S5 enable output to regulator";
+		enum-name = "PWR_EN_PP5000_A";
+		gpios = <&gpiok 5 0>;
+		output;
+	};
+	pwr-en-pp3300-s5 {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PP3300_S5 enable output to LS";
+		enum-name = "PWR_EN_PP3300_A";
+		gpios = <&gpioc 5 0>;
+		output;
+	};
+	pwr-pg-ec-rsmrst-odl {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST power good from regulator";
+		enum-name = "PWR_RSMRST";
+		gpios = <&gpioe 1 0>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-ec-pch-rsmrst-odl {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST output to PCH";
+		enum-name = "PWR_EC_PCH_RSMRST";
+		gpios = <&gpioh 0 0>;
+		output;
+	};
+	pwr-slp-s0-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_S0_L input from PCH";
+		enum-name = "PWR_SLP_S0";
+		gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-slp-s3-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_S3_L input from PCH";
+		enum-name = "PWR_SLP_S3";
+		gpios = <&gpioh 3 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-slp-sus-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_SUS_L input from PCH";
+		enum-name = "PWR_SLP_SUS";
+		gpios = <&gpiog 2 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-ec-soc-dsw-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "DSW_PWROK output to PCH";
+		enum-name = "PWR_EC_SOC_DSW_PWROK";
+		gpios = <&gpiol 7 0>;
+		output;
+	};
+	pwr-vccst-pwrgd-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "VCCST_PWRGD output to PCH";
+		enum-name = "PWR_VCCST_PWRGD";
+		gpios = <&gpioe 5 (GPIO_OPEN_DRAIN | GPIO_VOLTAGE_1P8)>;
+		output;
+	};
+	pwr-imvp9-vrrdy-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "VRRDY input from IMVP9";
+		enum-name = "PWR_IMVP9_VRRDY";
+		gpios = <&gpioj 4 0>;
+	};
+	pwr-pch-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PCH_PWROK output to PCH";
+		enum-name = "PWR_PCH_PWROK";
+		gpios = <&gpiod 6 GPIO_OPEN_DRAIN>;
+		output;
+	};
+	pwr-ec-pch-sys-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_PWROK output to PCH";
+		enum-name = "PWR_EC_PCH_SYS_PWROK";
+		gpios = <&gpiof 2 0>;
+		output;
+	};
+	pwr-sys-rst-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_RESET# output to PCH";
+		enum-name = "PWR_SYS_RST";
+		gpios = <&gpiod 1 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>;
+		output;
+	};
+	pwr-slp-s4 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S4 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S4";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4";
+		vw-invert;
+	};
+	pwr-slp-s5 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S5 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S5";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5";
+		vw-invert;
+	};
+	pwr-all-sys-pwrgd {
+		/*
+		 * This is a board level signal, since this
+		 * signal needs some special processing.
+		 */
+		compatible = "intel,ap-pwrseq-external";
+		dbg-label = "Combined all power good";
+		enum-name = "PWR_ALL_SYS_PWRGD";
+	};
+	pwr-adc-pp3300 {
+		compatible = "intel,ap-pwrseq-adc";
+		dbg-label = "PP3300_PROC";
+		enum-name = "PWR_DSW_PWROK";
+		trigger-high = <&vcmp0>;
+		trigger-low = <&vcmp1>;
+	};
+	pwr-adc-pp1p05 {
+		compatible = "intel,ap-pwrseq-adc";
+		dbg-label = "PP1P05_PROC";
+		enum-name = "PWR_PG_PP1P05";
+		trigger-high = <&vcmp2>;
+		trigger-low = <&vcmp3>;
+	};
+
+};
+
+&vcmp0 {
+	status = "okay";
+	scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>;
+	comparison = <IT8XXX2_VCMP_GREATER>;
+	/*
+	 * This is 90% of nominal voltage considering voltage
+	 * divider on ADC input.
+	 */
+	threshold-mv = <2448>;
+	io-channels = <&adc0 0>;
+};
+&vcmp1 {
+	status = "okay";
+	scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>;
+	comparison = <IT8XXX2_VCMP_LESS_OR_EQUAL>;
+	threshold-mv = <2448>;
+	io-channels = <&adc0 0>;
+};
+&vcmp2 {
+	status = "okay";
+	scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>;
+	comparison = <IT8XXX2_VCMP_GREATER>;
+	/* Setting at 90% of nominal voltage */
+	threshold-mv = <945>;
+	io-channels = <&adc0 14>;
+};
+&vcmp3 {
+	status = "okay";
+	scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>;
+	comparison = <IT8XXX2_VCMP_LESS_OR_EQUAL>;
+	threshold-mv = <945>;
+	io-channels = <&adc0 14>;
+};
diff --git a/zephyr/projects/nissa/yaviks/prj.conf b/zephyr/projects/nissa/yaviks/prj.conf
new file mode 100644
index 0000000000..a3c0d05000
--- /dev/null
+++ b/zephyr/projects/nissa/yaviks/prj.conf
@@ -0,0 +1,31 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_BOARD_YAVIKS=y
+
+# Ensure recovery key combination (esc+refresh+power) is reliable: b/236580049
+CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI3=y
+CONFIG_PLATFORM_EC_KEYBOARD_REFRESH_ROW3=y
+
+# Sensors: disabled; yaviks is clamshell-only
+CONFIG_PLATFORM_EC_LID_ANGLE=n
+CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=n
+CONFIG_PLATFORM_EC_MOTIONSENSE=n
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=n
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=n
+CONFIG_PLATFORM_EC_ACCEL_FIFO=n
+CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=n
+CONFIG_PLATFORM_EC_GMR_TABLET_MODE=n
+CONFIG_PLATFORM_EC_TABLET_MODE=n
+CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=n
+CONFIG_PLATFORM_EC_VOLUME_BUTTONS=n
+CONFIG_PLATFORM_EC_MAX_SENSOR_FREQ_MILLIHZ=100000
+
+CONFIG_PLATFORM_EC_KEYBOARD_KEYPAD=y
+
+# No fan supported, and tach is default-enabled
+CONFIG_TACH_IT8XXX2=n
+
+# LED
+CONFIG_PLATFORM_EC_LED_PWM=n
diff --git a/zephyr/projects/nissa/yaviks/src/charger.c b/zephyr/projects/nissa/yaviks/src/charger.c
new file mode 100644
index 0000000000..786bb1bd3c
--- /dev/null
+++ b/zephyr/projects/nissa/yaviks/src/charger.c
@@ -0,0 +1,56 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/logging/log.h>
+
+#include "battery.h"
+#include "charger.h"
+#include "console.h"
+#include "driver/charger/sm5803.h"
+#include "extpower.h"
+#include "usb_pd.h"
+#include "nissa_common.h"
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+int extpower_is_present(void)
+{
+	int port;
+	int rv;
+	bool acok;
+
+	for (port = 0; port < board_get_usb_pd_port_count(); port++) {
+		rv = sm5803_is_acok(port, &acok);
+		if ((rv == EC_SUCCESS) && acok)
+			return 1;
+	}
+
+	return 0;
+}
+
+/*
+ * Yaviks does not have a GPIO indicating whether extpower is present,
+ * so detect using the charger(s).
+ */
+__override void board_check_extpower(void)
+{
+	static int last_extpower_present;
+	int extpower_present = extpower_is_present();
+
+	if (last_extpower_present ^ extpower_present)
+		extpower_handle_update(extpower_present);
+
+	last_extpower_present = extpower_present;
+}
+
+__override void board_hibernate(void)
+{
+	/* Shut down the chargers */
+	if (board_get_usb_pd_port_count() == 2)
+		sm5803_hibernate(CHARGER_SECONDARY);
+	sm5803_hibernate(CHARGER_PRIMARY);
+	LOG_INF("Charger(s) hibernated");
+	cflush();
+}
diff --git a/zephyr/projects/nissa/yaviks/src/hdmi.c b/zephyr/projects/nissa/yaviks/src/hdmi.c
new file mode 100644
index 0000000000..d15e9fb034
--- /dev/null
+++ b/zephyr/projects/nissa/yaviks/src/hdmi.c
@@ -0,0 +1,28 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <cros_board_info.h>
+#include "nissa_hdmi.h"
+
+__override void nissa_configure_hdmi_power_gpios(void)
+{
+	/*
+	 * Yaviks versions before 2 need hdmi-en-odl to be
+	 * pulled down to enable VCC on the HDMI port, but later
+	 * versions (and other boards) disconnect this so
+	 * the port's VCC directly follows en-rails-odl. Only
+	 * configure the GPIO if needed, to save power.
+	 */
+	uint32_t board_version = 0;
+
+	/* CBI errors ignored, will configure the pin */
+	cbi_get_board_version(&board_version);
+	if (board_version < 2) {
+		nissa_configure_hdmi_vcc();
+	}
+
+	/* Still always need core rails controlled */
+	nissa_configure_hdmi_rails();
+}
diff --git a/zephyr/projects/nissa/yaviks/src/keyboard.c b/zephyr/projects/nissa/yaviks/src/keyboard.c
new file mode 100644
index 0000000000..1e5ac7a953
--- /dev/null
+++ b/zephyr/projects/nissa/yaviks/src/keyboard.c
@@ -0,0 +1,50 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+#include "keyboard_scan.h"
+#include "timer.h"
+
+/* Keyboard scan setting */
+__override struct keyboard_scan_config keyscan_config = {
+	/* Increase from 50 us, because KSO_02 passes through the H1. */
+	.output_settle_us = 80,
+	/* Other values should be the same as the default configuration. */
+	.debounce_down_us = 9 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x1c, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xa4, 0xff, 0xf6, 0x55, 0xfe, 0xff, 0xff, 0xff, /* full set */
+	},
+};
+
+static const struct ec_response_keybd_config yaviks_kb_legacy = {
+	.num_top_row_keys = 13,
+	.action_keys = {
+		TK_BACK,		/* T1 */
+		TK_REFRESH,		/* T2 */
+		TK_FULLSCREEN,		/* T3 */
+		TK_OVERVIEW,		/* T4 */
+		TK_SNAPSHOT,		/* T5 */
+		TK_BRIGHTNESS_DOWN,	/* T6 */
+		TK_BRIGHTNESS_UP,	/* T7 */
+		TK_KBD_BKLIGHT_TOGGLE,	/* T8 */
+		TK_PLAY_PAUSE,		/* T9 */
+		TK_MICMUTE,		/* T10 */
+		TK_VOL_MUTE,		/* T11 */
+		TK_VOL_DOWN,		/* T12 */
+		TK_VOL_UP,		/* T13 */
+	},
+	.capabilities = KEYBD_CAP_NUMERIC_KEYPAD,
+};
+
+__override const struct ec_response_keybd_config *
+board_vivaldi_keybd_config(void)
+{
+	return &yaviks_kb_legacy;
+}
diff --git a/zephyr/projects/nissa/yaviks/src/led.c b/zephyr/projects/nissa/yaviks/src/led.c
new file mode 100644
index 0000000000..e4f49dc9ad
--- /dev/null
+++ b/zephyr/projects/nissa/yaviks/src/led.c
@@ -0,0 +1,231 @@
+/* Copyright 2022 The ChromiumOS Authors.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <stdint.h>
+
+#include "battery.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "chipset.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "host_command.h"
+#include "led_common.h"
+#include "hooks.h"
+
+#define BAT_LED_ON 0
+#define BAT_LED_OFF 1
+
+#define BATT_LOW_BCT 10
+
+#define LED_TICKS_PER_CYCLE 4
+#define LED_TICKS_PER_CYCLE_S3 4
+#define LED_ON_TICKS 2
+#define POWER_LED_ON_S3_TICKS 2
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_LEFT_LED,
+					     EC_LED_ID_RIGHT_LED };
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+enum led_color {
+	LED_OFF = 0,
+	LED_AMBER,
+	LED_WHITE,
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
+};
+
+enum led_port { LEFT_PORT = 0, RIGHT_PORT };
+
+static void led_set_color_battery(int port, enum led_color color)
+{
+	const struct gpio_dt_spec *amber_led, *white_led;
+
+	if (port == LEFT_PORT) {
+		amber_led = GPIO_DT_FROM_NODELABEL(gpio_c0_charger_led_amber_l);
+		white_led = GPIO_DT_FROM_NODELABEL(gpio_c0_charger_led_white_l);
+	} else if (port == RIGHT_PORT) {
+		amber_led = GPIO_DT_FROM_NODELABEL(gpio_c1_charger_led_amber_l);
+		white_led = GPIO_DT_FROM_NODELABEL(gpio_c1_charger_led_white_l);
+	}
+
+	switch (color) {
+	case LED_WHITE:
+		gpio_pin_set_dt(white_led, BAT_LED_ON);
+		gpio_pin_set_dt(amber_led, BAT_LED_OFF);
+		break;
+	case LED_AMBER:
+		gpio_pin_set_dt(white_led, BAT_LED_OFF);
+		gpio_pin_set_dt(amber_led, BAT_LED_ON);
+		break;
+	case LED_OFF:
+		gpio_pin_set_dt(white_led, BAT_LED_OFF);
+		gpio_pin_set_dt(amber_led, BAT_LED_OFF);
+		break;
+	default:
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	switch (led_id) {
+	case EC_LED_ID_LEFT_LED:
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		break;
+	case EC_LED_ID_RIGHT_LED:
+		brightness_range[EC_LED_COLOR_WHITE] = 1;
+		brightness_range[EC_LED_COLOR_AMBER] = 1;
+		break;
+	default:
+		break;
+	}
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	switch (led_id) {
+	case EC_LED_ID_LEFT_LED:
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_battery(LEFT_PORT, LED_WHITE);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(LEFT_PORT, LED_AMBER);
+		else
+			led_set_color_battery(LEFT_PORT, LED_OFF);
+		break;
+	case EC_LED_ID_RIGHT_LED:
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			led_set_color_battery(RIGHT_PORT, LED_WHITE);
+		else if (brightness[EC_LED_COLOR_AMBER] != 0)
+			led_set_color_battery(RIGHT_PORT, LED_AMBER);
+		else
+			led_set_color_battery(RIGHT_PORT, LED_OFF);
+		break;
+	default:
+		return EC_ERROR_PARAM1;
+	}
+
+	return EC_SUCCESS;
+}
+
+/*
+ * Set active charge port color to the parameter, turn off all others.
+ * If no port is active (-1), turn off all LEDs.
+ */
+static void set_active_port_color(enum led_color color)
+{
+	int port = charge_manager_get_active_charge_port();
+
+	if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED))
+		led_set_color_battery(RIGHT_PORT,
+				      (port == RIGHT_PORT) ? color : LED_OFF);
+	if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED))
+		led_set_color_battery(LEFT_PORT,
+				      (port == LEFT_PORT) ? color : LED_OFF);
+}
+
+static void led_set_battery(void)
+{
+	static unsigned int battery_ticks;
+	static int suspend_ticks;
+
+	battery_ticks++;
+
+	/*
+	 * Override battery LEDs for Yaviks, Yaviks is non-power LED
+	 * design, blinking both two side battery white LEDs to indicate
+	 * system suspend with non-charging state.
+	 */
+	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
+	    charge_get_state() != PWR_STATE_CHARGE) {
+		suspend_ticks++;
+
+		led_set_color_battery(RIGHT_PORT,
+				      suspend_ticks % LED_TICKS_PER_CYCLE_S3 <
+						      POWER_LED_ON_S3_TICKS ?
+					      LED_WHITE :
+					      LED_OFF);
+		led_set_color_battery(LEFT_PORT,
+				      suspend_ticks % LED_TICKS_PER_CYCLE_S3 <
+						      POWER_LED_ON_S3_TICKS ?
+					      LED_WHITE :
+					      LED_OFF);
+		return;
+	}
+
+	suspend_ticks = 0;
+
+	switch (charge_get_state()) {
+	case PWR_STATE_CHARGE:
+		/* Always indicate when charging, even in suspend. */
+		set_active_port_color(LED_AMBER);
+		break;
+	case PWR_STATE_DISCHARGE:
+		/*
+		 * Blinking amber LEDs slowly if battery is lower 10
+		 * percentage.
+		 */
+		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
+			if (charge_get_percent() < BATT_LOW_BCT)
+				led_set_color_battery(
+					RIGHT_PORT,
+					(battery_ticks % LED_TICKS_PER_CYCLE <
+					 LED_ON_TICKS) ?
+						LED_AMBER :
+						LED_OFF);
+			else
+				led_set_color_battery(RIGHT_PORT, LED_OFF);
+		}
+
+		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) {
+			if (charge_get_percent() < BATT_LOW_BCT)
+				led_set_color_battery(
+					LEFT_PORT,
+					(battery_ticks % LED_TICKS_PER_CYCLE <
+					 LED_ON_TICKS) ?
+						LED_AMBER :
+						LED_OFF);
+			else
+				led_set_color_battery(LEFT_PORT, LED_OFF);
+		}
+		break;
+	case PWR_STATE_ERROR:
+		if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) {
+			led_set_color_battery(
+				RIGHT_PORT,
+				(battery_ticks & 0x1) ? LED_AMBER : LED_OFF);
+		}
+
+		if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) {
+			led_set_color_battery(LEFT_PORT, (battery_ticks & 0x1) ?
+								 LED_AMBER :
+								 LED_OFF);
+		}
+		break;
+	case PWR_STATE_CHARGE_NEAR_FULL:
+		set_active_port_color(LED_WHITE);
+		break;
+	case PWR_STATE_IDLE: /* External power connected in IDLE */
+		set_active_port_color(LED_WHITE);
+		break;
+	case PWR_STATE_FORCED_IDLE:
+		set_active_port_color(
+			(battery_ticks % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ?
+				LED_AMBER :
+				LED_OFF);
+		break;
+	default:
+		/* Other states don't alter LED behavior */
+		break;
+	}
+}
+
+/* Called by hook task every TICK(IT83xx 500ms) */
+static void led_tick(void)
+{
+	led_set_battery();
+}
+DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
diff --git a/zephyr/projects/nissa/yaviks/src/usbc.c b/zephyr/projects/nissa/yaviks/src/usbc.c
new file mode 100644
index 0000000000..48f7cfd9cb
--- /dev/null
+++ b/zephyr/projects/nissa/yaviks/src/usbc.c
@@ -0,0 +1,393 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/logging/log.h>
+#include <ap_power/ap_power.h>
+
+#include "charge_state_v2.h"
+#include "chipset.h"
+#include "hooks.h"
+#include "usb_mux.h"
+#include "system.h"
+#include "driver/charger/sm5803.h"
+#include "driver/tcpm/it83xx_pd.h"
+#include "driver/tcpm/ps8xxx_public.h"
+#include "driver/tcpm/tcpci.h"
+
+#include "nissa_common.h"
+
+LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL);
+
+struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_EMBEDDED,
+		/* TCPC is embedded within EC so no i2c config needed */
+		.drv = &it8xxx2_tcpm_drv,
+		/* Alert is active-low, push-pull */
+		.flags = 0,
+	},
+	{
+		/*
+		 * Sub-board: optional PS8745 TCPC+redriver. Behaves the same
+		 * as PS8815.
+		 */
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_USB_C1_TCPC,
+			.addr_flags = PS8XXX_I2C_ADDR1_FLAGS,
+		},
+		.drv = &ps8xxx_tcpm_drv,
+		/* PS8745 implements TCPCI 2.0 */
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+	},
+};
+
+/* Vconn control for integrated ITE TCPC */
+void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
+{
+	/* Vconn control is only for port 0 */
+	if (port)
+		return;
+
+	if (cc_pin == USBPD_CC_PIN_1)
+		gpio_pin_set_dt(
+			GPIO_DT_FROM_NODELABEL(gpio_en_usb_c0_cc1_vconn),
+			!!enabled);
+	else
+		gpio_pin_set_dt(
+			GPIO_DT_FROM_NODELABEL(gpio_en_usb_c0_cc2_vconn),
+			!!enabled);
+}
+
+__override bool pd_check_vbus_level(int port, enum vbus_level level)
+{
+	return sm5803_check_vbus_level(port, level);
+}
+
+/*
+ * Putting chargers into LPM when in suspend reduces power draw by about 8mW
+ * per charger, but also seems critical to correct operation in source mode:
+ * if chargers are not in LPM when a sink is first connected, VBUS sourcing
+ * works even if the partner is later removed (causing LPM entry) and
+ * reconnected (causing LPM exit). If in LPM initially, sourcing VBUS
+ * consistently causes the charger to report (apparently spurious) overcurrent
+ * failures.
+ *
+ * In short, this is important to making things work correctly but we don't
+ * understand why.
+ */
+static void board_chargers_suspend(struct ap_power_ev_callback *const cb,
+				   const struct ap_power_ev_data data)
+{
+	void (*fn)(int chgnum);
+
+	switch (data.event) {
+	case AP_POWER_SUSPEND:
+		fn = sm5803_enable_low_power_mode;
+		break;
+	case AP_POWER_RESUME:
+		fn = sm5803_disable_low_power_mode;
+		break;
+	default:
+		LOG_WRN("%s: power event %d is not recognized", __func__,
+			data.event);
+		return;
+	}
+
+	fn(CHARGER_PRIMARY);
+	if (board_get_charger_chip_count() > 1)
+		fn(CHARGER_SECONDARY);
+}
+
+static int board_chargers_suspend_init(const struct device *unused)
+{
+	static struct ap_power_ev_callback cb = {
+		.handler = board_chargers_suspend,
+		.events = AP_POWER_SUSPEND | AP_POWER_RESUME,
+	};
+	ap_power_ev_add_callback(&cb);
+	return 0;
+}
+SYS_INIT(board_chargers_suspend_init, APPLICATION, 0);
+
+int board_set_active_charge_port(int port)
+{
+	int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count());
+	int i;
+	int old_port;
+	int rv;
+
+	if (!is_real_port && port != CHARGE_PORT_NONE)
+		return EC_ERROR_INVAL;
+
+	old_port = charge_manager_get_active_charge_port();
+	LOG_INF("Charge update: p%d -> p%d", old_port, port);
+
+	/* Check if port is sourcing VBUS. */
+	if (port != CHARGE_PORT_NONE && charger_is_sourcing_otg_power(port)) {
+		LOG_WRN("Skip enable p%d: already sourcing", port);
+		return EC_ERROR_INVAL;
+	}
+
+	/* Disable sinking on all ports except the desired one */
+	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+		if (i == port)
+			continue;
+
+		if (sm5803_vbus_sink_enable(i, 0))
+			/*
+			 * Do not early-return because this can fail during
+			 * power-on which would put us into a loop.
+			 */
+			LOG_WRN("p%d: sink path disable failed.", i);
+	}
+
+	/* Don't enable anything (stop here) if no ports were requested */
+	if ((port == CHARGE_PORT_NONE) || (old_port == port))
+		return EC_SUCCESS;
+
+	/*
+	 * Stop the charger IC from switching while changing ports.  Otherwise,
+	 * we can overcurrent the adapter we're switching to. (crbug.com/926056)
+	 */
+	if (old_port != CHARGE_PORT_NONE)
+		charger_discharge_on_ac(1);
+
+	/* Enable requested charge port. */
+	rv = sm5803_vbus_sink_enable(port, 1);
+	if (rv)
+		LOG_WRN("p%d: sink path enable failed: code %d", port, rv);
+
+	/* Allow the charger IC to begin/continue switching. */
+	charger_discharge_on_ac(0);
+
+	return rv;
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	/*
+	 * TCPC 0 is embedded in the EC and processes interrupts in the chip
+	 * code (it83xx/intc.c). This function only needs to poll port C1 if
+	 * present.
+	 */
+	uint16_t status = 0;
+	int regval;
+
+	/* Is the C1 port present and its IRQ line asserted? */
+	if (board_get_usb_pd_port_count() == 2 &&
+	    !gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) {
+		/*
+		 * C1 IRQ is shared between BC1.2 and TCPC; poll TCPC to see if
+		 * it asserted the IRQ.
+		 */
+		if (!tcpc_read16(1, TCPC_REG_ALERT, &regval)) {
+			if (regval)
+				status = PD_STATUS_TCPC_ALERT_1;
+		}
+	}
+
+	return status;
+}
+
+void pd_power_supply_reset(int port)
+{
+	int prev_en;
+
+	if (port < 0 || port >= board_get_usb_pd_port_count())
+		return;
+
+	prev_en = charger_is_sourcing_otg_power(port);
+
+	/* Disable Vbus */
+	charger_enable_otg_power(port, 0);
+
+	/* Discharge Vbus if previously enabled */
+	if (prev_en)
+		sm5803_set_vbus_disch(port, 1);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	enum ec_error_list rv;
+
+	if (port < 0 || port > board_get_usb_pd_port_count()) {
+		LOG_WRN("Port C%d does not exist, cannot enable VBUS", port);
+		return EC_ERROR_INVAL;
+	}
+
+	/* Disable sinking */
+	rv = sm5803_vbus_sink_enable(port, 0);
+	if (rv) {
+		LOG_WRN("C%d failed to disable sinking: %d", port, rv);
+		return rv;
+	}
+
+	/* Disable Vbus discharge */
+	rv = sm5803_set_vbus_disch(port, 0);
+	if (rv) {
+		LOG_WRN("C%d failed to clear VBUS discharge: %d", port, rv);
+		return rv;
+	}
+
+	/* Provide Vbus */
+	rv = charger_enable_otg_power(port, 1);
+	if (rv) {
+		LOG_WRN("C%d failed to enable VBUS sourcing: %d", port, rv);
+		return rv;
+	}
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	int rv;
+	const int current = rp == TYPEC_RP_3A0 ? 3000 : 1500;
+
+	rv = charger_set_otg_current_voltage(port, current, 5000);
+	if (rv != EC_SUCCESS) {
+		LOG_WRN("Failed to set source ilimit on port %d to %d: %d",
+			port, current, rv);
+	}
+}
+
+void board_reset_pd_mcu(void)
+{
+	/*
+	 * Do nothing. The integrated TCPC for C0 lacks a dedicated reset
+	 * command, and C1 (if present) doesn't have a reset pin connected
+	 * to the EC.
+	 */
+}
+
+#define INT_RECHECK_US 5000
+
+/* C0 interrupt line shared by BC 1.2 and charger */
+
+static void check_c0_line(void);
+DECLARE_DEFERRED(check_c0_line);
+
+static void notify_c0_chips(void)
+{
+	usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+	sm5803_interrupt(0);
+}
+
+static void check_c0_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips
+	 */
+	if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl))) {
+		notify_c0_chips();
+		hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+	}
+}
+
+void usb_c0_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c0_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c0_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c0_line_data, INT_RECHECK_US);
+}
+
+/* C1 interrupt line shared by BC 1.2, TCPC, and charger */
+static void check_c1_line(void);
+DECLARE_DEFERRED(check_c1_line);
+
+static void notify_c1_chips(void)
+{
+	schedule_deferred_pd_interrupt(1);
+	usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
+	/* Charger is handled in board_process_pd_alert */
+}
+
+static void check_c1_line(void)
+{
+	/*
+	 * If line is still being held low, see if there's more to process from
+	 * one of the chips.
+	 */
+	if (!gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) {
+		notify_c1_chips();
+		hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
+	}
+}
+
+void usb_c1_interrupt(enum gpio_signal s)
+{
+	/* Cancel any previous calls to check the interrupt line */
+	hook_call_deferred(&check_c1_line_data, -1);
+
+	/* Notify all chips using this line that an interrupt came in */
+	notify_c1_chips();
+
+	/* Check the line again in 5ms */
+	hook_call_deferred(&check_c1_line_data, INT_RECHECK_US);
+}
+
+/*
+ * Check state of IRQ lines at startup, ensuring an IRQ that happened before
+ * the EC started up won't get lost (leaving the IRQ line asserted and blocking
+ * any further interrupts on the port).
+ *
+ * Although the PD task will check for pending TCPC interrupts on startup,
+ * the charger sharing the IRQ will not be polled automatically.
+ */
+void board_handle_initial_typec_irq(void)
+{
+	check_c0_line();
+	if (board_get_usb_pd_port_count() == 2)
+		check_c1_line();
+}
+/*
+ * This must run after sub-board detection (which happens in EC main()),
+ * but isn't depended on by anything else either.
+ */
+DECLARE_HOOK(HOOK_INIT, board_handle_initial_typec_irq, HOOK_PRIO_LAST);
+
+/*
+ * Handle charger interrupts in the PD task. Not doing so can lead to a priority
+ * inversion where we fail to respond to TCPC alerts quickly enough because we
+ * don't get another edge on a shared IRQ until the charger interrupt is cleared
+ * (or the IRQ is polled again), which happens in the low-priority charger task:
+ * the high-priority type-C handler is thus blocked on the lower-priority
+ * charger.
+ *
+ * To avoid that, we run charger interrupts at the same priority.
+ */
+void board_process_pd_alert(int port)
+{
+	/*
+	 * Port 0 doesn't use an external TCPC, so its interrupts don't need
+	 * this special handling.
+	 */
+	if (port == 1 &&
+	    !gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) {
+		sm5803_handle_interrupt(port);
+	}
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	int chg_det = 0;
+
+	sm5803_get_chg_det(port, &chg_det);
+
+	return chg_det;
+}
diff --git a/zephyr/projects/nissa/yaviks/yaviks_vif.xml b/zephyr/projects/nissa/yaviks/yaviks_vif.xml
new file mode 100644
index 0000000000..966ac9db57
--- /dev/null
+++ b/zephyr/projects/nissa/yaviks/yaviks_vif.xml
@@ -0,0 +1,350 @@
+<?xml version="1.0" encoding="utf-8"?>

+<vif:VIF xmlns:opt="http://usb.org/VendorInfoFileOptionalContent.xsd" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:vif="http://usb.org/VendorInfoFile.xsd">

+  <vif:VIF_Specification>3.19</vif:VIF_Specification>

+  <vif:VIF_App>

+    <vif:Vendor>USB-IF</vif:Vendor>

+    <vif:Name>VIF Editor</vif:Name>

+    <vif:Version>3.2.4.0</vif:Version>

+  </vif:VIF_App>

+  <vif:Vendor_Name>Google</vif:Vendor_Name>

+  <vif:Model_Part_Number>Yaviks</vif:Model_Part_Number>

+  <vif:Product_Revision>1</vif:Product_Revision>

+  <vif:TID>0</vif:TID>

+  <vif:VIF_Product_Type value="0">Port Product</vif:VIF_Product_Type>

+  <vif:Certification_Type value="1">Reference Platform</vif:Certification_Type>

+  <vif:Product>

+    <!--Product Level Content:-->

+  </vif:Product>

+  <vif:Component>

+    <!--Component 0: Port 0-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;Component-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:Port_Label>0</vif:Port_Label>

+    <vif:Connector_Type value="2">Type-C®</vif:Connector_Type>

+    <vif:USB4_Supported value="false" />

+    <vif:USB_PD_Support value="true" />

+    <vif:PD_Port_Type value="4">DRP</vif:PD_Port_Type>

+    <vif:Type_C_State_Machine value="2">DRP</vif:Type_C_State_Machine>

+    <vif:Port_Battery_Powered value="true" />

+    <vif:BC_1_2_Support value="2">Charging Port</vif:BC_1_2_Support>

+    <vif:Captive_Cable value="false" />

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;General PD-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:PD_Spec_Revision_Major value="3" />

+    <vif:PD_Spec_Revision_Minor value="1" />

+    <vif:PD_Spec_Version_Major value="1" />

+    <vif:PD_Spec_Version_Minor value="3" />

+    <vif:PD_Specification_Revision value="2">Revision 3</vif:PD_Specification_Revision>

+    <vif:SOP_Capable value="true" />

+    <vif:SOP_P_Capable value="true" />

+    <vif:SOP_PP_Capable value="true" />

+    <vif:SOP_P_Debug_Capable value="false" />

+    <vif:SOP_PP_Debug_Capable value="false" />

+    <vif:Manufacturer_Info_Supported_Port value="true" />

+    <vif:Manufacturer_Info_VID_Port value="6353">18D1</vif:Manufacturer_Info_VID_Port>

+    <vif:Manufacturer_Info_PID_Port value="20570">505A</vif:Manufacturer_Info_PID_Port>

+    <vif:Chunking_Implemented_SOP value="true" />

+    <vif:Unchunked_Extended_Messages_Supported value="false" />

+    <vif:Security_Msgs_Supported_SOP value="false" />

+    <vif:Unconstrained_Power value="false" />

+    <vif:Num_Fixed_Batteries value="1" />

+    <vif:Num_Swappable_Battery_Slots value="0" />

+    <vif:ID_Header_Connector_Type_SOP value="2">USB Type-C® Receptacle</vif:ID_Header_Connector_Type_SOP>

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;PD Capabilities-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:USB_Comms_Capable value="true" />

+    <vif:DR_Swap_To_DFP_Supported value="true" />

+    <vif:DR_Swap_To_UFP_Supported value="false" />

+    <vif:VCONN_Swap_To_On_Supported value="true" />

+    <vif:VCONN_Swap_To_Off_Supported value="true" />

+    <vif:Responds_To_Discov_SOP_UFP value="false" />

+    <vif:Responds_To_Discov_SOP_DFP value="true" />

+    <vif:Attempts_Discov_SOP value="true" />

+    <vif:Power_Interruption_Available value="0">No Interruption Possible</vif:Power_Interruption_Available>

+    <vif:Data_Reset_Supported value="false" />

+    <vif:Enter_USB_Supported value="false" />

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;USB Type-C®-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:Type_C_Can_Act_As_Host value="true" />

+    <vif:Type_C_Can_Act_As_Device value="false" />

+    <vif:Type_C_Implements_Try_SRC value="true" />

+    <vif:Type_C_Implements_Try_SNK value="false" />

+    <vif:Type_C_Supports_Audio_Accessory value="false" />

+    <vif:Type_C_Is_VCONN_Powered_Accessory value="false" />

+    <vif:Type_C_Is_Debug_Target_SRC value="true" />

+    <vif:Type_C_Is_Debug_Target_SNK value="true" />

+    <vif:RP_Value value="1">1.5A</vif:RP_Value>

+    <vif:Type_C_Port_On_Hub value="false" />

+    <vif:Type_C_Power_Source value="2">Both</vif:Type_C_Power_Source>

+    <vif:Type_C_Sources_VCONN value="true" />

+    <vif:Type_C_Is_Alt_Mode_Controller value="true" />

+    <vif:Type_C_Is_Alt_Mode_Adapter value="false" />

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;Product Power-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:Product_Total_Source_Power_mW value="15000">15000 mW</vif:Product_Total_Source_Power_mW>

+    <vif:Port_Source_Power_Type value="0">Assured</vif:Port_Source_Power_Type>

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;USB Host-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:Host_Supports_USB_Data value="true" />

+    <vif:Host_Speed value="1">USB 3.2 Gen 1x1</vif:Host_Speed>

+    <vif:Host_Contains_Captive_Retimer value="false" />

+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />

+    <vif:Host_Is_Embedded value="false" />

+    <vif:Host_Suspend_Supported value="true" />

+    <vif:Is_DFP_On_Hub value="false" />

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;Battery Charging 1.2-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:BC_1_2_Charging_Port_Type value="1">CDP</vif:BC_1_2_Charging_Port_Type>

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;PD Source-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:PD_Power_As_Source value="15000">15000 mW</vif:PD_Power_As_Source>

+    <vif:EPR_Supported_As_Src value="false" />

+    <vif:USB_Suspend_May_Be_Cleared value="false" />

+    <vif:Sends_Pings value="false" />

+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="0">FR_Swap not supported</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>

+    <vif:Master_Port value="false" />

+    <vif:Num_Src_PDOs value="1" />

+    <vif:PD_OC_Protection value="true" />

+    <vif:PD_OCP_Method value="0">Over-Current Response</vif:PD_OCP_Method>

+    <!--Bundle: SrcPdoList-->

+    <vif:SrcPdoList>

+      <vif:SrcPDO>

+        <!--Source PDO 1-->

+        <vif:Src_PDO_Supply_Type value="0">Fixed</vif:Src_PDO_Supply_Type>

+        <vif:Src_PDO_Peak_Current value="0">100% IOC</vif:Src_PDO_Peak_Current>

+        <vif:Src_PDO_Voltage value="100">5000 mV</vif:Src_PDO_Voltage>

+        <vif:Src_PDO_Max_Current value="300">3000 mA</vif:Src_PDO_Max_Current>

+        <vif:Src_PD_OCP_OC_Debounce value="0">0 msec</vif:Src_PD_OCP_OC_Debounce>

+        <vif:Src_PD_OCP_OC_Threshold value="300">3000 mA</vif:Src_PD_OCP_OC_Threshold>

+      </vif:SrcPDO>

+    </vif:SrcPdoList>

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;PD Sink-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:PD_Power_As_Sink value="45000">45000 mW</vif:PD_Power_As_Sink>

+    <vif:EPR_Supported_As_Snk value="false" />

+    <vif:No_USB_Suspend_May_Be_Set value="true" />

+    <vif:GiveBack_May_Be_Set value="false" />

+    <vif:Higher_Capability_Set value="false" />

+    <vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source value="0">FR_Swap not supported</vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source>

+    <vif:Num_Snk_PDOs value="3" />

+    <!--Bundle: SnkPdoList-->

+    <vif:SnkPdoList>

+      <vif:SnkPDO>

+        <!--Sink PDO 1-->

+        <vif:Snk_PDO_Supply_Type value="0">Fixed</vif:Snk_PDO_Supply_Type>

+        <vif:Snk_PDO_Voltage value="100">5000 mV</vif:Snk_PDO_Voltage>

+        <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>

+      </vif:SnkPDO>

+      <vif:SnkPDO>

+        <!--Sink PDO 2-->

+        <vif:Snk_PDO_Supply_Type value="1">Battery</vif:Snk_PDO_Supply_Type>

+        <vif:Snk_PDO_Op_Power value="60">15000 mW</vif:Snk_PDO_Op_Power>

+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>

+        <vif:Snk_PDO_Max_Voltage value="300">15000 mV</vif:Snk_PDO_Max_Voltage>

+      </vif:SnkPDO>

+      <vif:SnkPDO>

+        <!--Sink PDO 3-->

+        <vif:Snk_PDO_Supply_Type value="2">Variable</vif:Snk_PDO_Supply_Type>

+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>

+        <vif:Snk_PDO_Max_Voltage value="300">15000 mV</vif:Snk_PDO_Max_Voltage>

+        <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>

+      </vif:SnkPDO>

+    </vif:SnkPdoList>

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;Dual Role-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:Accepts_PR_Swap_As_Src value="true" />

+    <vif:Accepts_PR_Swap_As_Snk value="true" />

+    <vif:Requests_PR_Swap_As_Src value="true" />

+    <vif:Requests_PR_Swap_As_Snk value="true" />

+    <vif:FR_Swap_Supported_As_Initial_Sink value="false" />

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;SOP Discover ID-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:XID_SOP value="0" />

+    <vif:Data_Capable_As_USB_Host_SOP value="true" />

+    <vif:Data_Capable_As_USB_Device_SOP value="false" />

+    <vif:Product_Type_UFP_SOP value="0">Undefined</vif:Product_Type_UFP_SOP>

+    <vif:Product_Type_DFP_SOP value="0">Undefined</vif:Product_Type_DFP_SOP>

+    <vif:DFP_VDO_Port_Number value="0" />

+    <vif:Modal_Operation_Supported_SOP value="false" />

+    <vif:USB_VID_SOP value="6353">18D1</vif:USB_VID_SOP>

+    <vif:PID_SOP value="20570">505A</vif:PID_SOP>

+    <vif:bcdDevice_SOP value="0">0000</vif:bcdDevice_SOP>

+  </vif:Component>

+  <vif:Component>

+    <!--Component 1: Port 1-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;Component-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:Port_Label>1</vif:Port_Label>

+    <vif:Connector_Type value="2">Type-C®</vif:Connector_Type>

+    <vif:USB4_Supported value="false" />

+    <vif:USB_PD_Support value="true" />

+    <vif:PD_Port_Type value="4">DRP</vif:PD_Port_Type>

+    <vif:Type_C_State_Machine value="2">DRP</vif:Type_C_State_Machine>

+    <vif:Port_Battery_Powered value="true" />

+    <vif:BC_1_2_Support value="2">Charging Port</vif:BC_1_2_Support>

+    <vif:Captive_Cable value="false" />

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;General PD-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:PD_Spec_Revision_Major value="3" />

+    <vif:PD_Spec_Revision_Minor value="1" />

+    <vif:PD_Spec_Version_Major value="1" />

+    <vif:PD_Spec_Version_Minor value="3" />

+    <vif:PD_Specification_Revision value="2">Revision 3</vif:PD_Specification_Revision>

+    <vif:SOP_Capable value="true" />

+    <vif:SOP_P_Capable value="true" />

+    <vif:SOP_PP_Capable value="true" />

+    <vif:SOP_P_Debug_Capable value="false" />

+    <vif:SOP_PP_Debug_Capable value="false" />

+    <vif:Manufacturer_Info_Supported_Port value="true" />

+    <vif:Manufacturer_Info_VID_Port value="6353">18D1</vif:Manufacturer_Info_VID_Port>

+    <vif:Manufacturer_Info_PID_Port value="20570">505A</vif:Manufacturer_Info_PID_Port>

+    <vif:Chunking_Implemented_SOP value="true" />

+    <vif:Unchunked_Extended_Messages_Supported value="false" />

+    <vif:Security_Msgs_Supported_SOP value="false" />

+    <vif:Unconstrained_Power value="false" />

+    <vif:Num_Fixed_Batteries value="1" />

+    <vif:Num_Swappable_Battery_Slots value="0" />

+    <vif:ID_Header_Connector_Type_SOP value="2">USB Type-C® Receptacle</vif:ID_Header_Connector_Type_SOP>

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;PD Capabilities-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:USB_Comms_Capable value="true" />

+    <vif:DR_Swap_To_DFP_Supported value="true" />

+    <vif:DR_Swap_To_UFP_Supported value="false" />

+    <vif:VCONN_Swap_To_On_Supported value="true" />

+    <vif:VCONN_Swap_To_Off_Supported value="true" />

+    <vif:Responds_To_Discov_SOP_UFP value="false" />

+    <vif:Responds_To_Discov_SOP_DFP value="true" />

+    <vif:Attempts_Discov_SOP value="true" />

+    <vif:Power_Interruption_Available value="0">No Interruption Possible</vif:Power_Interruption_Available>

+    <vif:Data_Reset_Supported value="false" />

+    <vif:Enter_USB_Supported value="false" />

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;USB Type-C®-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:Type_C_Can_Act_As_Host value="true" />

+    <vif:Type_C_Can_Act_As_Device value="false" />

+    <vif:Type_C_Implements_Try_SRC value="true" />

+    <vif:Type_C_Implements_Try_SNK value="false" />

+    <vif:Type_C_Supports_Audio_Accessory value="false" />

+    <vif:Type_C_Is_VCONN_Powered_Accessory value="false" />

+    <vif:Type_C_Is_Debug_Target_SRC value="true" />

+    <vif:Type_C_Is_Debug_Target_SNK value="true" />

+    <vif:RP_Value value="1">1.5A</vif:RP_Value>

+    <vif:Type_C_Port_On_Hub value="false" />

+    <vif:Type_C_Power_Source value="2">Both</vif:Type_C_Power_Source>

+    <vif:Type_C_Sources_VCONN value="true" />

+    <vif:Type_C_Is_Alt_Mode_Controller value="true" />

+    <vif:Type_C_Is_Alt_Mode_Adapter value="false" />

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;Product Power-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:Product_Total_Source_Power_mW value="15000">15000 mW</vif:Product_Total_Source_Power_mW>

+    <vif:Port_Source_Power_Type value="0">Assured</vif:Port_Source_Power_Type>

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;USB Host-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:Host_Supports_USB_Data value="true" />

+    <vif:Host_Speed value="1">USB 3.2 Gen 1x1</vif:Host_Speed>

+    <vif:Host_Contains_Captive_Retimer value="true" />

+    <vif:Host_Truncates_DP_For_tDHPResponse value="false" />

+    <vif:Host_Is_Embedded value="false" />

+    <vif:Host_Suspend_Supported value="true" />

+    <vif:Is_DFP_On_Hub value="false" />

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;Battery Charging 1.2-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:BC_1_2_Charging_Port_Type value="1">CDP</vif:BC_1_2_Charging_Port_Type>

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;PD Source-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:PD_Power_As_Source value="15000">15000 mW</vif:PD_Power_As_Source>

+    <vif:EPR_Supported_As_Src value="false" />

+    <vif:USB_Suspend_May_Be_Cleared value="false" />

+    <vif:Sends_Pings value="false" />

+    <vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink value="0">FR_Swap not supported</vif:FR_Swap_Type_C_Current_Capability_As_Initial_Sink>

+    <vif:Master_Port value="false" />

+    <vif:Num_Src_PDOs value="1" />

+    <vif:PD_OC_Protection value="true" />

+    <vif:PD_OCP_Method value="0">Over-Current Response</vif:PD_OCP_Method>

+    <!--Bundle: SrcPdoList-->

+    <vif:SrcPdoList>

+      <vif:SrcPDO>

+        <!--Source PDO 1-->

+        <vif:Src_PDO_Supply_Type value="0">Fixed</vif:Src_PDO_Supply_Type>

+        <vif:Src_PDO_Peak_Current value="0">100% IOC</vif:Src_PDO_Peak_Current>

+        <vif:Src_PDO_Voltage value="100">5000 mV</vif:Src_PDO_Voltage>

+        <vif:Src_PDO_Max_Current value="300">3000 mA</vif:Src_PDO_Max_Current>

+        <vif:Src_PD_OCP_OC_Debounce value="0">0 msec</vif:Src_PD_OCP_OC_Debounce>

+        <vif:Src_PD_OCP_OC_Threshold value="300">3000 mA</vif:Src_PD_OCP_OC_Threshold>

+      </vif:SrcPDO>

+    </vif:SrcPdoList>

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;PD Sink-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:PD_Power_As_Sink value="45000">45000 mW</vif:PD_Power_As_Sink>

+    <vif:EPR_Supported_As_Snk value="false" />

+    <vif:No_USB_Suspend_May_Be_Set value="true" />

+    <vif:GiveBack_May_Be_Set value="false" />

+    <vif:Higher_Capability_Set value="false" />

+    <vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source value="0">FR_Swap not supported</vif:FR_Swap_Reqd_Type_C_Current_As_Initial_Source>

+    <vif:Num_Snk_PDOs value="3" />

+    <!--Bundle: SnkPdoList-->

+    <vif:SnkPdoList>

+      <vif:SnkPDO>

+        <!--Sink PDO 1-->

+        <vif:Snk_PDO_Supply_Type value="0">Fixed</vif:Snk_PDO_Supply_Type>

+        <vif:Snk_PDO_Voltage value="100">5000 mV</vif:Snk_PDO_Voltage>

+        <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>

+      </vif:SnkPDO>

+      <vif:SnkPDO>

+        <!--Sink PDO 2-->

+        <vif:Snk_PDO_Supply_Type value="1">Battery</vif:Snk_PDO_Supply_Type>

+        <vif:Snk_PDO_Op_Power value="60">15000 mW</vif:Snk_PDO_Op_Power>

+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>

+        <vif:Snk_PDO_Max_Voltage value="300">15000 mV</vif:Snk_PDO_Max_Voltage>

+      </vif:SnkPDO>

+      <vif:SnkPDO>

+        <!--Sink PDO 3-->

+        <vif:Snk_PDO_Supply_Type value="2">Variable</vif:Snk_PDO_Supply_Type>

+        <vif:Snk_PDO_Min_Voltage value="95">4750 mV</vif:Snk_PDO_Min_Voltage>

+        <vif:Snk_PDO_Max_Voltage value="300">15000 mV</vif:Snk_PDO_Max_Voltage>

+        <vif:Snk_PDO_Op_Current value="300">3000 mA</vif:Snk_PDO_Op_Current>

+      </vif:SnkPDO>

+    </vif:SnkPdoList>

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;Dual Role-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:Accepts_PR_Swap_As_Src value="true" />

+    <vif:Accepts_PR_Swap_As_Snk value="true" />

+    <vif:Requests_PR_Swap_As_Src value="true" />

+    <vif:Requests_PR_Swap_As_Snk value="true" />

+    <vif:FR_Swap_Supported_As_Initial_Sink value="false" />

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <!--;SOP Discover ID-->

+    <!--;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;-->

+    <vif:XID_SOP value="0" />

+    <vif:Data_Capable_As_USB_Host_SOP value="true" />

+    <vif:Data_Capable_As_USB_Device_SOP value="false" />

+    <vif:Product_Type_UFP_SOP value="0">Undefined</vif:Product_Type_UFP_SOP>

+    <vif:Product_Type_DFP_SOP value="0">Undefined</vif:Product_Type_DFP_SOP>

+    <vif:DFP_VDO_Port_Number value="1" />

+    <vif:Modal_Operation_Supported_SOP value="false" />

+    <vif:USB_VID_SOP value="6353">18D1</vif:USB_VID_SOP>

+    <vif:PID_SOP value="20570">505A</vif:PID_SOP>

+    <vif:bcdDevice_SOP value="0">0000</vif:bcdDevice_SOP>

+  </vif:Component>

+</vif:VIF>
\ No newline at end of file
diff --git a/zephyr/projects/npcx_evb/npcx7/BUILD.py b/zephyr/projects/npcx_evb/npcx7/BUILD.py
index 89afed0fc1..baa6774595 100644
--- a/zephyr/projects/npcx_evb/npcx7/BUILD.py
+++ b/zephyr/projects/npcx_evb/npcx7/BUILD.py
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/projects/npcx_evb/npcx7/CMakeLists.txt b/zephyr/projects/npcx_evb/npcx7/CMakeLists.txt
index a61ddf6755..64429d586e 100644
--- a/zephyr/projects/npcx_evb/npcx7/CMakeLists.txt
+++ b/zephyr/projects/npcx_evb/npcx7/CMakeLists.txt
@@ -1,10 +1,10 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 cmake_minimum_required(VERSION 3.13.1)
 
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
 project(npcx7)
 
 zephyr_include_directories(include)
diff --git a/zephyr/projects/npcx_evb/npcx7/fan.dts b/zephyr/projects/npcx_evb/npcx7/fan.dts
index adfd71c95d..dc4debdcb9 100644
--- a/zephyr/projects/npcx_evb/npcx7/fan.dts
+++ b/zephyr/projects/npcx_evb/npcx7/fan.dts
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,7 +9,6 @@
 
 		fan_0 {
 			pwms = <&pwm0 0 PWM_KHZ(25) PWM_POLARITY_NORMAL>;
-			pwm-frequency = <25000>;
 			rpm_min = <1000>;
 			rpm_start = <1000>;
 			rpm_max = <5200>;
diff --git a/zephyr/projects/npcx_evb/npcx7/gpio.dts b/zephyr/projects/npcx_evb/npcx7/gpio.dts
index d0aa642673..d44927609d 100644
--- a/zephyr/projects/npcx_evb/npcx7/gpio.dts
+++ b/zephyr/projects/npcx_evb/npcx7/gpio.dts
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/npcx_evb/npcx7/include/gpio_map.h b/zephyr/projects/npcx_evb/npcx7/include/gpio_map.h
deleted file mode 100644
index c2b81fe5c6..0000000000
--- a/zephyr/projects/npcx_evb/npcx7/include/gpio_map.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __ZEPHYR_GPIO_MAP_H
-#define __ZEPHYR_GPIO_MAP_H
-
-#endif /* __ZEPHYR_GPIO_MAP_H */
diff --git a/zephyr/projects/npcx_evb/npcx7/interrupts.dts b/zephyr/projects/npcx_evb/npcx7/interrupts.dts
index dfa4a321ef..3e92428ef4 100644
--- a/zephyr/projects/npcx_evb/npcx7/interrupts.dts
+++ b/zephyr/projects/npcx_evb/npcx7/interrupts.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/npcx_evb/npcx7/keyboard.dts b/zephyr/projects/npcx_evb/npcx7/keyboard.dts
index e2a5010952..3fb6986f1a 100644
--- a/zephyr/projects/npcx_evb/npcx7/keyboard.dts
+++ b/zephyr/projects/npcx_evb/npcx7/keyboard.dts
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -32,7 +32,6 @@
 	kblight {
 		compatible = "cros-ec,kblight-pwm";
 		pwms = <&pwm2 0 PWM_KHZ(10) PWM_POLARITY_NORMAL>;
-		frequency = <10000>;
 	};
 };
 
diff --git a/zephyr/projects/npcx_evb/npcx7/prj.conf b/zephyr/projects/npcx_evb/npcx7/prj.conf
index 39d082e363..5f1fc03f88 100644
--- a/zephyr/projects/npcx_evb/npcx7/prj.conf
+++ b/zephyr/projects/npcx_evb/npcx7/prj.conf
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -35,8 +35,8 @@ CONFIG_PLATFORM_EC_CONSOLE_CMD_IRQ=y
 
 # eSPI
 CONFIG_ESPI=y
-CONFIG_PLATFORM_EC_ESPI_VW_SLP_S3=y
-CONFIG_PLATFORM_EC_ESPI_VW_SLP_S4=y
+CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S3=y
+CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S4=y
 
 # Keyboard
 CONFIG_CROS_KB_RAW_NPCX_KSO_HIGH_DRIVE=y
@@ -45,6 +45,10 @@ CONFIG_CROS_KB_RAW_NPCX_KSO_HIGH_DRIVE=y
 CONFIG_PLATFORM_EC_RTC=y
 CONFIG_PLATFORM_EC_CONSOLE_CMD_RTC=y
 
+# USB-C
+CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=n
+CONFIG_PLATFORM_EC_USB_PD_USB4=n
+
 # Zephyr feature
 CONFIG_ASSERT=y
 CONFIG_SHELL_MINIMAL=n
diff --git a/zephyr/projects/npcx_evb/npcx9/BUILD.py b/zephyr/projects/npcx_evb/npcx9/BUILD.py
index efd96c9020..335f410d9b 100644
--- a/zephyr/projects/npcx_evb/npcx9/BUILD.py
+++ b/zephyr/projects/npcx_evb/npcx9/BUILD.py
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/projects/npcx_evb/npcx9/CMakeLists.txt b/zephyr/projects/npcx_evb/npcx9/CMakeLists.txt
index a81ae87820..ef734c06f6 100644
--- a/zephyr/projects/npcx_evb/npcx9/CMakeLists.txt
+++ b/zephyr/projects/npcx_evb/npcx9/CMakeLists.txt
@@ -1,10 +1,10 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 cmake_minimum_required(VERSION 3.13.1)
 
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
 project(npcx9)
 
 zephyr_include_directories(include)
diff --git a/zephyr/projects/npcx_evb/npcx9/fan.dts b/zephyr/projects/npcx_evb/npcx9/fan.dts
index adfd71c95d..dc4debdcb9 100644
--- a/zephyr/projects/npcx_evb/npcx9/fan.dts
+++ b/zephyr/projects/npcx_evb/npcx9/fan.dts
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,7 +9,6 @@
 
 		fan_0 {
 			pwms = <&pwm0 0 PWM_KHZ(25) PWM_POLARITY_NORMAL>;
-			pwm-frequency = <25000>;
 			rpm_min = <1000>;
 			rpm_start = <1000>;
 			rpm_max = <5200>;
diff --git a/zephyr/projects/npcx_evb/npcx9/gpio.dts b/zephyr/projects/npcx_evb/npcx9/gpio.dts
index d0aa642673..9a32112471 100644
--- a/zephyr/projects/npcx_evb/npcx9/gpio.dts
+++ b/zephyr/projects/npcx_evb/npcx9/gpio.dts
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -56,13 +56,17 @@
 			enum-name = "GPIO_BOARD_VERSION3";
 		};
 	};
+};
 
-	hibernate-wake-pins {
-		compatible = "cros-ec,hibernate-wake-pins";
-		wakeup-irqs = <
-			&int_ac_present
-			&int_power_button
-			&int_lid_open
-		>;
-	};
+/* A falling edge detection type for PSL_IN2 */
+&psl_in2_gp00 {
+	psl-in-mode = "edge";
+	psl-in-pol = "low-falling";
+};
+
+/* Power domain device controlled by PSL (Power Switch Logic) IO pads */
+&power_ctrl_psl {
+	status = "okay";
+	pinctrl-names = "sleep";
+	pinctrl-0 = <&psl_in2_gp00>;
 };
diff --git a/zephyr/projects/npcx_evb/npcx9/include/gpio_map.h b/zephyr/projects/npcx_evb/npcx9/include/gpio_map.h
deleted file mode 100644
index c2b81fe5c6..0000000000
--- a/zephyr/projects/npcx_evb/npcx9/include/gpio_map.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __ZEPHYR_GPIO_MAP_H
-#define __ZEPHYR_GPIO_MAP_H
-
-#endif /* __ZEPHYR_GPIO_MAP_H */
diff --git a/zephyr/projects/npcx_evb/npcx9/interrupts.dts b/zephyr/projects/npcx_evb/npcx9/interrupts.dts
index dfa4a321ef..3e92428ef4 100644
--- a/zephyr/projects/npcx_evb/npcx9/interrupts.dts
+++ b/zephyr/projects/npcx_evb/npcx9/interrupts.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/npcx_evb/npcx9/keyboard.dts b/zephyr/projects/npcx_evb/npcx9/keyboard.dts
index e3ce1b1e20..3fb6986f1a 100644
--- a/zephyr/projects/npcx_evb/npcx9/keyboard.dts
+++ b/zephyr/projects/npcx_evb/npcx9/keyboard.dts
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -32,7 +32,6 @@
 	kblight {
 		compatible = "cros-ec,kblight-pwm";
 		pwms = <&pwm2 0 PWM_KHZ(10) PWM_POLARITY_NORMAL>;
-		frequency = <10000>;
 	};
 };
 
@@ -41,31 +40,3 @@
 	pinctrl-0 = <&pwm2_gpc4>;
 	pinctrl-names = "default";
 };
-
-&cros_kb_raw {
-	status = "okay";
-	/* No KSO2 (it's inverted and implemented by GPIO) */
-	pinctrl-0 = <
-		&alt7_no_ksi0_sl
-		&alt7_no_ksi1_sl
-		&alt7_no_ksi2_sl
-		&alt7_no_ksi3_sl
-		&alt7_no_ksi4_sl
-		&alt7_no_ksi5_sl
-		&alt7_no_ksi6_sl
-		&alt7_no_ksi7_sl
-		&alt8_no_kso00_sl
-		&alt8_no_kso01_sl
-		&alt8_no_kso03_sl
-		&alt8_no_kso04_sl
-		&alt8_no_kso05_sl
-		&alt8_no_kso06_sl
-		&alt8_no_kso07_sl
-		&alt9_no_kso08_sl
-		&alt9_no_kso09_sl
-		&alt9_no_kso10_sl
-		&alt9_no_kso11_sl
-		&alt9_no_kso12_sl
-	>;
-	pinctrl-names = "default";
-};
diff --git a/zephyr/projects/npcx_evb/npcx9/prj.conf b/zephyr/projects/npcx_evb/npcx9/prj.conf
index aa7e36a7a6..827b6366c6 100644
--- a/zephyr/projects/npcx_evb/npcx9/prj.conf
+++ b/zephyr/projects/npcx_evb/npcx9/prj.conf
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -39,8 +39,8 @@ CONFIG_PLATFORM_EC_CONSOLE_CMD_IRQ=y
 
 # eSPI
 CONFIG_ESPI=y
-CONFIG_PLATFORM_EC_ESPI_VW_SLP_S3=y
-CONFIG_PLATFORM_EC_ESPI_VW_SLP_S4=y
+CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S3=y
+CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S4=y
 
 # Keyboard
 CONFIG_CROS_KB_RAW_NPCX_KSO_HIGH_DRIVE=y
@@ -49,6 +49,10 @@ CONFIG_CROS_KB_RAW_NPCX_KSO_HIGH_DRIVE=y
 CONFIG_PLATFORM_EC_RTC=y
 CONFIG_PLATFORM_EC_CONSOLE_CMD_RTC=y
 
+# USB-C
+CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=n
+CONFIG_PLATFORM_EC_USB_PD_USB4=n
+
 # Zephyr feature
 CONFIG_ASSERT=y
 CONFIG_SHELL_MINIMAL=n
diff --git a/zephyr/projects/posix-ec/BUILD.py b/zephyr/projects/posix-ec/BUILD.py
deleted file mode 100644
index a324f2ad39..0000000000
--- a/zephyr/projects/posix-ec/BUILD.py
+++ /dev/null
@@ -1,7 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-"""Define zmake projects for posix-ec."""
-
-register_host_project(project_name="posix-ec")
diff --git a/zephyr/projects/posix-ec/CMakeLists.txt b/zephyr/projects/posix-ec/CMakeLists.txt
deleted file mode 100644
index 165de682a8..0000000000
--- a/zephyr/projects/posix-ec/CMakeLists.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-# SPDX-License-Identifier: Apache-2.0
-
-cmake_minimum_required(VERSION 3.13.1)
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-project(posix-ec)
-
-zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}/include")
diff --git a/zephyr/projects/posix-ec/prj.conf b/zephyr/projects/posix-ec/prj.conf
deleted file mode 100644
index f6549c7839..0000000000
--- a/zephyr/projects/posix-ec/prj.conf
+++ /dev/null
@@ -1,11 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-CONFIG_CROS_EC=y
-CONFIG_PLATFORM_EC=y
-
-# Disable shimmed code. Can enabled selectively later
-CONFIG_SHIMMED_TASKS=n
-CONFIG_PLATFORM_EC_KEYBOARD=n
-CONFIG_PLATFORM_EC_HOSTCMD=n
diff --git a/zephyr/projects/rex/BUILD.py b/zephyr/projects/rex/BUILD.py
new file mode 100644
index 0000000000..2537f61226
--- /dev/null
+++ b/zephyr/projects/rex/BUILD.py
@@ -0,0 +1,45 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Rex Projects."""
+
+
+def register_variant(
+    project_name, extra_dts_overlays=(), extra_kconfig_files=()
+):
+    """Register a variant of rex."""
+    register_npcx_project(
+        project_name=project_name,
+        zephyr_board="npcx9m7f",
+        dts_overlays=[
+            # Common to all projects.
+            here / "rex.dts",
+            # Project-specific DTS customization.
+            *extra_dts_overlays,
+        ],
+        kconfig_files=[
+            # Common to all projects.
+            here / "prj.conf",
+            # Project-specific KConfig customization.
+            *extra_kconfig_files,
+        ],
+    )
+
+
+register_variant(
+    project_name="rex",
+    extra_dts_overlays=[
+        here / "generated.dts",
+        here / "interrupts.dts",
+        here / "power_signals.dts",
+        here / "battery.dts",
+        here / "usbc.dts",
+        here / "keyboard.dts",
+        here / "led.dts",
+        here / "fan.dts",
+        here / "temp_sensors.dts",
+        here / "motionsense.dts",
+    ],
+    extra_kconfig_files=[here / "prj_rex.conf"],
+)
diff --git a/zephyr/projects/rex/CMakeLists.txt b/zephyr/projects/rex/CMakeLists.txt
new file mode 100644
index 0000000000..27d7dff068
--- /dev/null
+++ b/zephyr/projects/rex/CMakeLists.txt
@@ -0,0 +1,12 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.20.5)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(rex)
+
+zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}/include")
+zephyr_library_sources_ifdef(CONFIG_AP_PWRSEQ "src/board_power.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/usbc_config.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/usb_pd_policy.c")
diff --git a/zephyr/projects/rex/Kconfig b/zephyr/projects/rex/Kconfig
new file mode 100644
index 0000000000..7d17c27815
--- /dev/null
+++ b/zephyr/projects/rex/Kconfig
@@ -0,0 +1,11 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config BOARD_REX
+	bool "Google Rex Baseboard"
+	help
+	  Build Google Rex reference board.  The board uses Nuvoton
+	  NPCX9 chip as the EC.
+
+source "Kconfig.zephyr"
diff --git a/zephyr/projects/rex/battery.dts b/zephyr/projects/rex/battery.dts
new file mode 100644
index 0000000000..e11346f48d
--- /dev/null
+++ b/zephyr/projects/rex/battery.dts
@@ -0,0 +1,12 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	batteries {
+		default_battery: batgqa05l22 {
+			compatible = "powertech,batgqa05l22", "battery-smart";
+		};
+	};
+};
diff --git a/zephyr/projects/rex/fan.dts b/zephyr/projects/rex/fan.dts
new file mode 100644
index 0000000000..aa6dcfde7d
--- /dev/null
+++ b/zephyr/projects/rex/fan.dts
@@ -0,0 +1,39 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	fans {
+		compatible = "cros-ec,fans";
+
+		fan_0 {
+			pwms = <&pwm5 0 PWM_KHZ(1) PWM_POLARITY_NORMAL>;
+			rpm_min = <2200>;
+			rpm_start = <2200>;
+			rpm_max = <4200>;
+			tach = <&tach1>;
+			enable_gpio = <&gpio_en_pp5000_fan>;
+		};
+	};
+};
+
+/* Tachemeter for fan speed measurement */
+&tach1 {
+	status = "okay";
+	pinctrl-0 = <&ta1_1_in_gp40>;
+	pinctrl-names = "default";
+	port = <NPCX_TACH_PORT_A>; /* port-A is selected */
+	sample-clk = <NPCX_TACH_FREQ_LFCLK>; /* Use LFCLK as sampling clock */
+	pulses-per-round = <2>; /* number of pulses per round of encoder */
+};
+
+&pwm5_gpb7 {
+	drive-open-drain;
+};
+
+&pwm5 {
+	status = "okay";
+	pinctrl-0 = <&pwm5_gpb7>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/projects/rex/generated.dts b/zephyr/projects/rex/generated.dts
new file mode 100644
index 0000000000..549f0e5fde
--- /dev/null
+++ b/zephyr/projects/rex/generated.dts
@@ -0,0 +1,362 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * This file is auto-generated - do not edit!
+ *
+ * TODO(b:/244441996): There are some errors in the main Rex EC GPIO spreadsheet
+ * which is used as input to create this device tree file. Until that issue is
+ * resolved, there are some edits required to this file to support EC
+ * functionality.
+ */
+
+/ {
+
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		adc_ddr_soc: ddr_soc {
+			enum-name = "ADC_TEMP_SENSOR_1_DDR_SOC";
+			io-channels = <&adc0 0>;
+		};
+		adc_ambient: ambient {
+			enum-name = "ADC_TEMP_SENSOR_2";
+			io-channels = <&adc0 1>;
+		};
+		adc_charger: charger {
+			enum-name = "ADC_TEMP_SENSOR_3";
+			io-channels = <&adc0 8>;
+		};
+		adc_wwan: wwan {
+			enum-name = "ADC_TEMP_SENSOR_4";
+			io-channels = <&adc0 7>;
+		};
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		gpio_acok_od: acok_od {
+			gpios = <&gpio0 0 GPIO_INPUT>;
+			enum-name = "GPIO_AC_PRESENT";
+		};
+		gpio_ccd_mode_odl: ccd_mode_odl {
+			gpios = <&gpioe 5 GPIO_ODR_LOW>;
+			enum-name = "GPIO_CCD_MODE_ODL";
+		};
+		gpio_cpu_c10_gate_l: cpu_c10_gate_l {
+			gpios = <&gpioa 7 GPIO_INPUT>;
+		};
+		gpio_ec_accel_int_r_l: ec_accel_int_r_l {
+			gpios = <&gpio8 1 GPIO_INPUT>;
+		};
+		gpio_ec_als_rgb_int_r_l: ec_als_rgb_int_r_l {
+			gpios = <&gpiod 4 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_ec_batt_pres_odl: ec_batt_pres_odl {
+			gpios = <&gpioa 3 GPIO_INPUT>;
+			enum-name = "GPIO_BATT_PRES_ODL";
+		};
+		gpio_ec_cbi_wp: ec_cbi_wp {
+			gpios = <&gpio7 3 GPIO_OUTPUT>;
+		};
+		gpio_ec_edp_bl_en: ec_edp_bl_en {
+			gpios = <&gpiod 3 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_ENABLE_BACKLIGHT";
+		};
+		gpio_ec_gsc_packet_mode: ec_gsc_packet_mode {
+			gpios = <&gpio7 5 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_PACKET_MODE_EN";
+		};
+		gpio_ec_imu_int_r_l: ec_imu_int_r_l {
+			gpios = <&gpio5 6 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_ec_imvp92_en_smb: ec_imvp92_en_smb {
+			gpios = <&gpiob 1 GPIO_OUTPUT>;
+		};
+		gpio_ec_kb_bl_en_l: ec_kb_bl_en_l {
+			gpios = <&gpio8 6 GPIO_OUTPUT>;
+		};
+		gpio_ec_kso_02_inv: ec_kso_02_inv {
+			gpios = <&gpio1 7 (GPIO_OUTPUT | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_ec_prochot_in_l: ec_prochot_in_l {
+			gpios = <&gpiof 0 GPIO_INPUT>;
+		};
+		gpio_ec_prochot_odl: ec_prochot_odl {
+			gpios = <&gpio6 3 GPIO_ODR_HIGH>;
+		};
+		gpio_ec_rst_r_odl: ec_rst_r_odl {
+			gpios = <&gpio7 7 GPIO_INPUT>;
+		};
+		gpio_ec_soc_int_odl: ec_soc_int_odl {
+			gpios = <&gpio7 0 GPIO_ODR_LOW>;
+			enum-name = "GPIO_EC_INT_L";
+		};
+		gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl {
+			gpios = <&gpioc 1 GPIO_ODR_LOW>;
+			enum-name = "GPIO_PCH_PWRBTN_L";
+		};
+		gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l {
+			gpios = <&gpioa 6 GPIO_OUTPUT>;
+		};
+		gpio_ec_soc_rtcrst: ec_soc_rtcrst {
+			gpios = <&gpio7 6 GPIO_ODR_HIGH>;
+		};
+		gpio_ec_soc_wake_r_odl: ec_soc_wake_r_odl {
+			gpios = <&gpioc 0 GPIO_ODR_LOW>;
+		};
+		gpio_ec_spare_gpio42: ec_spare_gpio42 {
+			gpios = <&gpio4 2 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpio66: ec_spare_gpio66 {
+			gpios = <&gpio6 6 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpio94: ec_spare_gpio94 {
+			gpios = <&gpio9 4 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpioa2: ec_spare_gpioa2 {
+			gpios = <&gpioa 2 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpioa4: ec_spare_gpioa4 {
+			gpios = <&gpioa 4 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpioc7: ec_spare_gpioc7 {
+			gpios = <&gpioc 7 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpo32: ec_spare_gpo32 {
+			gpios = <&gpio3 2 GPIO_OUTPUT>;
+		};
+		gpio_ec_spare_gpo35: ec_spare_gpo35 {
+			gpios = <&gpio3 5 GPIO_OUTPUT>;
+		};
+		gpio_ec_voldn_btn_odl: ec_voldn_btn_odl {
+			gpios = <&gpio9 3 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_DOWN_L";
+		};
+		gpio_ec_volup_btn_odl: ec_volup_btn_odl {
+			gpios = <&gpio9 7 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_UP_L";
+		};
+		gpio_ec_wp_l: ec_wp_l {
+			gpios = <&gpioa 1 GPIO_INPUT>;
+		};
+		gpio_en_pp5000_fan: en_pp5000_fan {
+			gpios = <&gpio6 1 GPIO_OUTPUT_LOW>;
+		};
+		gpio_en_pp5000_usba_r: en_pp5000_usba_r {
+			gpios = <&gpiod 7 GPIO_OUTPUT>;
+		};
+		gpio_en_s5_rails: en_s5_rails {
+			gpios = <&gpiob 6 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_TEMP_SENSOR_POWER";
+		};
+		gpio_en_z1_rails: en_z1_rails {
+			gpios = <&gpio8 5 GPIO_OUTPUT>;
+		};
+		gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl {
+			gpios = <&gpio0 1 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_imvp92_vrrdy_od: imvp92_vrrdy_od {
+			gpios = <&gpio4 3 GPIO_INPUT>;
+		};
+		gpio_led_1_l: led_1_l {
+			gpios = <&gpioc 4 GPIO_OUTPUT>;
+		};
+		gpio_led_2_l: led_2_l {
+			gpios = <&gpioc 3 GPIO_OUTPUT>;
+		};
+		gpio_led_3_l: led_3_l {
+			gpios = <&gpioc 2 GPIO_OUTPUT>;
+		};
+		gpio_led_4_l: led_4_l {
+			gpios = <&gpio6 0 GPIO_OUTPUT>;
+		};
+		gpio_lid_open: lid_open {
+			gpios = <&gpiod 2 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_LID_OPEN";
+		};
+		gpio_mech_pwr_btn_odl: mech_pwr_btn_odl {
+			gpios = <&gpio0 2 GPIO_INPUT>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+		};
+		gpio_seq_ec_all_sys_pg: seq_ec_all_sys_pg {
+			gpios = <&gpiof 4 GPIO_INPUT>;
+		};
+		gpio_seq_ec_rsmrst_odl: seq_ec_rsmrst_odl {
+			gpios = <&gpioe 2 GPIO_INPUT>;
+		};
+		gpio_slp_s3_ls_l: slp_s3_ls_l {
+			gpios = <&gpio4 1 GPIO_INPUT>;
+		};
+		gpio_sochot_odl: sochot_odl {
+			gpios = <&gpio9 6 GPIO_INPUT>;
+		};
+		gpio_soc_pwrok: soc_pwrok {
+			gpios = <&gpioa 5 GPIO_OUTPUT>;
+		};
+		gpio_sys_pwrok: sys_pwrok {
+			gpios = <&gpiob 0 GPIO_OUTPUT>;
+		};
+		gpio_sys_rst_odl: sys_rst_odl {
+			gpios = <&gpioc 5 GPIO_INPUT>;
+		};
+		gpio_sys_slp_s0ix_3v3_l: sys_slp_s0ix_3v3_l {
+			gpios = <&gpiod 5 GPIO_INPUT>;
+		};
+		gpio_tablet_mode_l: tablet_mode_l {
+			gpios = <&gpio9 5 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_TABLET_MODE_L";
+		};
+		gpio_usb_c0_bc12_int_odl: usb_c0_bc12_int_odl {
+			gpios = <&gpioc 6 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C0_BC12_INT_ODL";
+		};
+		gpio_usb_c0_ppc_int_odl: usb_c0_ppc_int_odl {
+			gpios = <&gpio6 2 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C0_PPC_INT_ODL";
+		};
+		gpio_usb_c0_rt_3p3_sx_en: usb_c0_rt_3p3_sx_en {
+			gpios = <&gpio0 3 GPIO_OUTPUT_LOW>;
+		};
+		gpio_usb_c0_rt_int_odl: usb_c0_rt_int_odl {
+			gpios = <&gpioa 0 GPIO_INPUT>;
+		};
+		gpio_usb_c0_tcpc_int_odl: usb_c0_tcpc_int_odl {
+			gpios = <&gpioe 0 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C0_TCPC_INT_ODL";
+		};
+		gpio_usb_c0_tcpc_rst_odl: usb_c0_tcpc_rst_odl {
+			gpios = <&gpio6 7 GPIO_ODR_HIGH>;
+		};
+		gpio_usb_c1_bc12_int_odl: usb_c1_bc12_int_odl {
+			gpios = <&gpio5 0 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C1_BC12_INT_ODL";
+		};
+		gpio_usb_c1_frs_en: usb_c1_frs_en {
+			gpios = <&gpio8 3 GPIO_ODR_HIGH>;
+		};
+		gpio_usb_c1_ppc_int_odl: usb_c1_ppc_int_odl {
+			gpios = <&gpiof 5 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C1_PPC_INT_ODL";
+		};
+		gpio_usb_c1_rst_odl: usb_c1_rst_odl {
+			gpios = <&gpio3 7 GPIO_ODR_LOW>;
+		};
+		gpio_usb_c1_rt_int_odl: usb_c1_rt_int_odl {
+			gpios = <&gpio7 2 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_usb_c1_rt_rst_r_odl: usb_c1_rt_rst_r_odl {
+			gpios = <&gpio7 4 GPIO_ODR_HIGH>;
+		};
+		gpio_usb_c1_tcpc_int_odl: usb_c1_tcpc_int_odl {
+			gpios = <&gpio3 4 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C1_TCPC_INT_ODL";
+		};
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		i2c_ec_i2c_sensor: ec_i2c_sensor {
+			i2c-port = <&i2c0_0>;
+			enum-names = "I2C_PORT_SENSOR";
+		};
+		i2c_ec_i2c_usb_c0_tcp: ec_i2c_usb_c0_tcp {
+			i2c-port = <&i2c1_0>;
+			enum-names = "I2C_PORT_USB_C0_TCPC";
+		};
+		i2c_ec_i2c_usb_c0_ppc_b: ec_i2c_usb_c0_ppc_b {
+			i2c-port = <&i2c2_0>;
+			enum-names = "I2C_PORT_PPC0";
+		};
+		i2c_ec_i2c_usb_c0_rt: ec_i2c_usb_c0_rt {
+			i2c-port = <&i2c3_0>;
+			enum-names = "I2C_PORT_USB_C0_RT";
+		};
+		i2c_ec_i2c_usb_c1_tcp: ec_i2c_usb_c1_tcp {
+			i2c-port = <&i2c4_1>;
+			enum-names = "I2C_PORT_USB_C1_TCPC";
+		};
+		i2c_ec_i2c_bat: ec_i2c_bat {
+			i2c-port = <&i2c5_0>;
+			enum-names = "I2C_PORT_BATTERY";
+		};
+		i2c_ec_i2c_usb_c1_mix: ec_i2c_usb_c1_mix {
+			i2c-port = <&i2c6_1>;
+			enum-names = "I2C_PORT_USB_1_MIX";
+		};
+		i2c_ec_i2c_mi: ec_i2c_mi {
+			i2c-port = <&i2c7_0>;
+			enum-names = "I2C_PORT_EEPROM";
+		};
+	};
+};
+
+&adc0 {
+	status = "okay";
+};
+
+&i2c0_0 {
+	status = "okay";
+};
+
+&i2c1_0 {
+	status = "okay";
+};
+
+&i2c2_0 {
+	status = "okay";
+};
+
+&i2c3_0 {
+	status = "okay";
+};
+
+&i2c4_1 {
+	status = "okay";
+};
+
+&i2c5_0 {
+	status = "okay";
+};
+
+&i2c6_1 {
+	status = "okay";
+};
+
+&i2c7_0 {
+	status = "okay";
+};
+
+&i2c_ctrl0 {
+	status = "okay";
+};
+
+&i2c_ctrl1 {
+	status = "okay";
+};
+
+&i2c_ctrl2 {
+	status = "okay";
+};
+
+&i2c_ctrl3 {
+	status = "okay";
+};
+
+&i2c_ctrl4 {
+	status = "okay";
+};
+
+&i2c_ctrl5 {
+	status = "okay";
+};
+
+&i2c_ctrl6 {
+	status = "okay";
+};
+
+&i2c_ctrl7 {
+	status = "okay";
+};
diff --git a/zephyr/projects/trogdor/lazor/include/gpio_map.h b/zephyr/projects/rex/include/gpio_map.h
index c2b81fe5c6..01cbc44396 100644
--- a/zephyr/projects/trogdor/lazor/include/gpio_map.h
+++ b/zephyr/projects/rex/include/gpio_map.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/rex/interrupts.dts b/zephyr/projects/rex/interrupts.dts
new file mode 100644
index 0000000000..7c4e6bca58
--- /dev/null
+++ b/zephyr/projects/rex/interrupts.dts
@@ -0,0 +1,65 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	gpio-interrupts {
+		compatible = "cros-ec,gpio-interrupts";
+
+		int_ac_present: ac_present {
+			irq-pin = <&gpio_acok_od>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "extpower_interrupt";
+		};
+		int_power_button: power_button {
+			irq-pin = <&gpio_mech_pwr_btn_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "power_button_interrupt";
+		};
+		int_lid_open: lid_open {
+			irq-pin = <&gpio_lid_open>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "lid_interrupt";
+		};
+		int_usb_c0_sbu_fault: c0_sbu_fault {
+			irq-pin = <&ioex_usb_c0_sbu_fault_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "sbu_fault_interrupt";
+		};
+		int_usb_c0_tcpc: usb_c0_tcpc {
+			irq-pin = <&gpio_usb_c0_tcpc_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "tcpc_alert_event";
+		};
+		int_usb_c0_ppc: usb_c0_ppc {
+			irq-pin = <&gpio_usb_c0_ppc_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "ppc_interrupt";
+		};
+		int_usb_c0_bc12: usb_c0_bc12 {
+			irq-pin = <&gpio_usb_c0_bc12_int_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "bc12_interrupt";
+		};
+		int_imu: ec_imu {
+			irq-pin = <&gpio_ec_imu_int_r_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "lsm6dso_interrupt";
+		};
+		int_als_rgb: ec_als_rgb {
+			irq-pin = <&gpio_ec_als_rgb_int_r_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "tcs3400_interrupt";
+		};
+		int_accel: ec_accel {
+			irq-pin = <&gpio_ec_accel_int_r_l>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "lis2dw12_interrupt";
+		};
+	};
+};
+
+/* Required node label that doesn't is named differently on Rex */
+gpio_ec_pch_wake_odl: &gpio_ec_soc_wake_r_odl {};
+
diff --git a/zephyr/projects/rex/keyboard.dts b/zephyr/projects/rex/keyboard.dts
new file mode 100644
index 0000000000..5248c4aaff
--- /dev/null
+++ b/zephyr/projects/rex/keyboard.dts
@@ -0,0 +1,34 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+&cros_kb_raw {
+	status = "okay";
+	/* No KSO2 (it's inverted and implemented by GPIO) */
+	pinctrl-0 = <
+		&ksi0_gp31
+		&ksi1_gp30
+		&ksi2_gp27
+		&ksi3_gp26
+		&ksi4_gp25
+		&ksi5_gp24
+		&ksi6_gp23
+		&ksi7_gp22
+		&kso00_gp21
+		&kso01_gp20
+		&kso03_gp16
+		&kso04_gp15
+		&kso05_gp14
+		&kso06_gp13
+		&kso07_gp12
+		&kso08_gp11
+		&kso09_gp10
+		&kso10_gp07
+		&kso11_gp06
+		&kso12_gp05
+		&kso13_gp04
+		&kso14_gp82
+	>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/projects/rex/led.dts b/zephyr/projects/rex/led.dts
new file mode 100644
index 0000000000..94acb6da5c
--- /dev/null
+++ b/zephyr/projects/rex/led.dts
@@ -0,0 +1,138 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	gpio-led-pins {
+		compatible = "cros-ec,gpio-led-pins";
+
+		color_off: color-off {
+			led-color = "LED_OFF";
+			led-id = "EC_LED_ID_BATTERY_LED";
+			led-pins = <&gpio_led_1_l 1>,
+				   <&gpio_led_2_l 1>;
+		};
+
+		color_white: color-white {
+			led-color = "LED_WHITE";
+			led-id = "EC_LED_ID_BATTERY_LED";
+			br-color = "EC_LED_COLOR_WHITE";
+			led-pins = <&gpio_led_1_l 1>,
+				   <&gpio_led_2_l 0>;
+		};
+
+		color_amber: color-amber {
+			led-color = "LED_AMBER";
+			led-id = "EC_LED_ID_BATTERY_LED";
+			br-color = "EC_LED_COLOR_AMBER";
+			led-pins = <&gpio_led_1_l 0>,
+				   <&gpio_led_2_l 1>;
+		};
+	};
+
+	led-colors {
+		compatible = "cros-ec,led-policy";
+
+		power-state-charge {
+			charge-state = "PWR_STATE_CHARGE";
+
+			color-0 {
+				led-color = <&color_amber>;
+			};
+		};
+
+		power-state-discharge-s0 {
+			charge-state = "PWR_STATE_DISCHARGE";
+			chipset-state = "POWER_S0";
+
+			color-0 {
+				led-color = <&color_off>;
+			};
+		};
+
+		power-state-discharge-s3 {
+			charge-state = "PWR_STATE_DISCHARGE";
+			chipset-state = "POWER_S3";
+
+			/* Blue 1 sec, off 3 sec */
+			color-0 {
+				led-color = <&color_white>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <3000>;
+			};
+		};
+
+		power-state-discharge-s5 {
+			charge-state = "PWR_STATE_DISCHARGE";
+			chipset-state = "POWER_S5";
+
+			color-0 {
+				led-color = <&color_off>;
+			};
+		};
+
+		power-state-error {
+			charge-state = "PWR_STATE_ERROR";
+
+			/* Red 1 sec, off 1 sec */
+			color-0 {
+				led-color = <&color_white>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <1000>;
+			};
+		};
+
+		power-state-near-full {
+			charge-state = "PWR_STATE_CHARGE_NEAR_FULL";
+
+			color-0 {
+				led-color = <&color_amber>;
+			};
+		};
+
+		power-state-forced-idle {
+			charge-state = "PWR_STATE_FORCED_IDLE";
+
+			/* White 2 sec, Amber 2 sec */
+			color-0 {
+				led-color = <&color_white>;
+				period-ms = <2000>;
+			};
+			color-1 {
+				led-color = <&color_amber>;
+				period-ms = <2000>;
+			};
+		};
+
+		power-state-idle-default {
+			charge-state = "PWR_STATE_IDLE";
+
+			color-0 {
+				led-color = <&color_white>;
+			};
+		};
+	};
+};
+
+&gpio_led_1_l {
+	#led-pin-cells = <1>;
+};
+
+&gpio_led_2_l {
+	#led-pin-cells = <1>;
+};
+
+&gpio_led_3_l {
+	#led-pin-cells = <1>;
+};
+
+&gpio_led_4_l {
+	#led-pin-cells = <1>;
+};
diff --git a/zephyr/projects/rex/motionsense.dts b/zephyr/projects/rex/motionsense.dts
new file mode 100644
index 0000000000..8b1c80921b
--- /dev/null
+++ b/zephyr/projects/rex/motionsense.dts
@@ -0,0 +1,257 @@
+/*
+ * Copyright 2022 The ChromiumOS Authors
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <dt-bindings/motionsense/utils.h>
+
+
+/ {
+	aliases {
+		/*
+		 * motion sense's <>_INT_EVENT is handled
+		 * by alias. Using the alias, each driver creates
+		 * its own <>_INT_EVENT.
+		 */
+		lsm6dso-int = &base_accel;
+		lis2dw12-int = &lid_accel;
+		tcs3400-int = &als_clear;
+	};
+
+	/*
+	 * Declare mutexes used by sensor drivers.
+	 * A mutex node is used to create an instance of mutex_t.
+	 * A mutex node is referenced by a sensor node if the
+	 * corresponding sensor driver needs to use the
+	 * instance of the mutex.
+	 */
+	motionsense-mutex {
+		compatible = "cros-ec,motionsense-mutex";
+		mutex_lis2dw12: lis2dw12-mutex {
+		};
+
+		mutex_lsm6dso: lsm6dso-mutex {
+		};
+	};
+
+	/* Rotation matrix used by drivers. */
+	motionsense-rotation-ref {
+		compatible = "cros-ec,motionsense-rotation-ref";
+		lid_rot_ref: lid-rotation-ref {
+			mat33 = <0 1 0
+				 1 0 0
+				 0 0 (-1)>;
+		};
+		base_rot_ref: base-rotation-ref {
+			mat33 = <1 0 0
+				 0 (-1) 0
+				 0 0 (-1)>;
+		};
+	};
+
+	/*
+	 * Driver specific data. A driver-specific data can be shared with
+	 * different motion sensors while they are using the same driver.
+	 *
+	 * If a node's compatible starts with "cros-ec,accelgyro-", it is for
+	 * a common structure defined in accelgyro.h.
+	 * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for
+	 * "struct als_drv_data_t" in accelgyro.h
+	 */
+	motionsense-sensor-data {
+		lis2dw12_data: lis2dw12-drv-data {
+			compatible = "cros-ec,drvdata-lis2dw12";
+			status = "okay";
+		};
+
+		lsm6dso_accel_data: lsm6dso-drv-data {
+			compatible = "cros-ec,drvdata-lsm6dso";
+			status = "okay";
+		};
+
+		lsm6dso_gyro_data: lsm6dso-drv-data {
+			compatible = "cros-ec,drvdata-lsm6dso";
+			status = "okay";
+		};
+
+		tcs_clear_data: tcs3400-clear-drv-data {
+			compatible = "cros-ec,drvdata-tcs3400-clear";
+			status = "okay";
+
+			als-drv-data {
+				compatible = "cros-ec,accelgyro-als-drv-data";
+				als-cal {
+					scale = <1>;
+					uscale = <0>;
+					offset = <0>;
+					als-channel-scale {
+					compatible =
+					"cros-ec,accelgyro-als-channel-scale";
+						k-channel-scale = <1>;
+						cover-scale = <1>;
+					};
+				};
+			};
+		};
+
+		tcs_rgb_data: tcs3400-rgb-drv-data {
+			compatible = "cros-ec,drvdata-tcs3400-rgb";
+			status = "okay";
+
+			/* node for rgb_calibration_t defined in accelgyro.h */
+			rgb_calibration {
+				compatible =
+					"cros-ec,accelgyro-rgb-calibration";
+
+				irt = <1>;
+
+				rgb-cal-x {
+					offset = <0>;
+					coeff = <0 0 0 1>;
+					als-channel-scale {
+					compatible =
+					"cros-ec,accelgyro-als-channel-scale";
+						k-channel-scale = <1>;
+						cover-scale = <1>;
+					};
+				};
+				rgb-cal-y {
+					offset = <0>;
+					coeff = <0 0 0 1>;
+					als-channel-scale {
+					compatible =
+					"cros-ec,accelgyro-als-channel-scale";
+						k-channel-scale = <1>;
+						cover-scale = <1>;
+					};
+				};
+				rgb-cal-z {
+					offset = <0>;
+					coeff = <0 0 0 1>;
+					als-channel-scale {
+					compatible =
+					"cros-ec,accelgyro-als-channel-scale";
+						k-channel-scale = <1>;
+						cover-scale = <1>;
+					};
+				};
+			};
+		};
+	};
+
+	/*
+	 * List of motion sensors that creates motion_sensors array.
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
+	 * motion sensor IDs for lid angle calculation.
+	 */
+	motionsense-sensor {
+		lid_accel: lid-accel {
+			compatible = "cros-ec,lis2dw12";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&mutex_lis2dw12>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&lid_rot_ref>;
+			default-range = <2>;
+			drv-data = <&lis2dw12_data>;
+			i2c-spi-addr-flags = "LIS2DWL_ADDR0_FLAGS";
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_accel: base-accel {
+			compatible = "cros-ec,lsm6dso-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&mutex_lsm6dso>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			default-range = <4>;
+			drv-data = <&lsm6dso_accel_data>;
+			i2c-spi-addr-flags = "LSM6DSO_ADDR0_FLAGS";
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+					ec-rate = <(100 * USEC_PER_MSEC)>;
+				};
+				ec-s3 {
+					odr = <(10000 | ROUND_UP_FLAG)>;
+					ec-rate = <(100 * USEC_PER_MSEC)>;
+				};
+			};
+		};
+
+		base-gyro {
+			compatible = "cros-ec,lsm6dso-gyro";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&mutex_lsm6dso>;
+			port = <&i2c_ec_i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			default-range = <(1000 | ROUND_UP_FLAG)>; /* dps */
+			drv-data = <&lsm6dso_gyro_data>;
+			i2c-spi-addr-flags = "LSM6DSO_ADDR0_FLAGS";
+		};
+
+		als_clear: base-als-clear {
+			compatible = "cros-ec,tcs3400-clear";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_CAMERA";
+			port = <&i2c_ec_i2c_sensor>;
+			default-range = <0x10000>;
+			drv-data = <&tcs_clear_data>;
+			i2c-spi-addr-flags = "TCS3400_I2C_ADDR_FLAGS";
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					/* Run ALS sensor in S0 */
+					odr = <1000>;
+				};
+			};
+		};
+
+		base-als-rgb {
+			compatible = "cros-ec,tcs3400-rgb";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_CAMERA";
+			default-range = <0x10000>; /* scale = 1x, uscale = 0 */
+			drv-data = <&tcs_rgb_data>;
+		};
+	};
+
+	motionsense-sensor-info {
+		compatible = "cros-ec,motionsense-sensor-info";
+
+		/* list of entries for motion_als_sensors */
+		als-sensors = <&als_clear>;
+		/*
+		 * list of GPIO interrupts that have to
+		 * be enabled at initial stage
+		 */
+		sensor-irqs = <&int_imu &int_als_rgb &int_accel>;
+		/* list of sensors in force mode */
+		accel-force-mode-sensors = <&lid_accel &als_clear>;
+	};
+};
diff --git a/zephyr/projects/rex/power_signals.dts b/zephyr/projects/rex/power_signals.dts
new file mode 100644
index 0000000000..860c316795
--- /dev/null
+++ b/zephyr/projects/rex/power_signals.dts
@@ -0,0 +1,152 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	chosen {
+		intel-ap-pwrseq,espi = &espi0;
+	};
+
+	common-pwrseq {
+		compatible = "intel,ap-pwrseq";
+
+		sys-pwrok-delay = <3>;
+		all-sys-pwrgd-timeout = <20>;
+	};
+
+	pwr-en-pp3300-s5 {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PP1800_S5/PP3300_S5 enable output to LS";
+		enum-name = "PWR_EN_PP3300_A";
+		gpios = <&gpiob 6 GPIO_ACTIVE_HIGH>;
+		output;
+	};
+	pwr-pg-ec-rsmrst-od {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST power good from regulator";
+		enum-name = "PWR_RSMRST";
+		gpios = <&gpioe 2 GPIO_ACTIVE_HIGH>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-ec-pch-rsmrst-odl {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "RSMRST output to PCH";
+		enum-name = "PWR_EC_PCH_RSMRST";
+		gpios = <&gpioa 6 GPIO_ACTIVE_HIGH>;
+		output;
+	};
+	pwr-pch-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "PCH_PWROK output to PCH";
+		enum-name = "PWR_PCH_PWROK";
+		gpios = <&gpioa 5 GPIO_ACTIVE_HIGH>;
+		output;
+	};
+	pwr-ec-pch-sys-pwrok {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_PWROK output to PCH";
+		enum-name = "PWR_EC_PCH_SYS_PWROK";
+		gpios = <&gpiob 0 GPIO_ACTIVE_HIGH>;
+		output;
+	};
+	pwr-sys-rst-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SYS_RESET# output to PCH";
+		enum-name = "PWR_SYS_RST";
+		gpios = <&gpioc 5 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+		output;
+	};
+	pwr-slp-s0-l {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "SLP_S0_L input from PCH";
+		enum-name = "PWR_SLP_S0";
+		gpios = <&gpiod 5 GPIO_ACTIVE_LOW>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+	pwr-slp-s3-l {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S3_L input from PCH";
+		enum-name = "PWR_SLP_S3";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4";
+		vw-invert;
+/*
+ * TODO: Initially, use virtual wire for sleep S3 signal instead of
+ * of the GPIO signal which also exists.
+ *		compatible = "intel,ap-pwrseq-gpio";
+ *		gpios = <&gpio4 1 GPIO_ACTIVE_LOW>;
+ *		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+ */
+	};
+	pwr-slp-s4 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S4 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S4";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4";
+		vw-invert;
+	};
+	pwr-slp-s5 {
+		compatible = "intel,ap-pwrseq-vw";
+		dbg-label = "SLP_S5 virtual wire input from PCH";
+		enum-name = "PWR_SLP_S5";
+		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5";
+		vw-invert;
+	};
+	pwr-all-sys-pwrgd {
+		compatible = "intel,ap-pwrseq-gpio";
+		dbg-label = "all power good";
+		enum-name = "PWR_ALL_SYS_PWRGD";
+		gpios = <&gpiof 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>;
+		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
+	};
+};
+
+/*
+ * Because the power signals directly reference the GPIOs,
+ * the corresponding named-gpios need to have no-auto-init set.
+ */
+ /* pwr-en-pp3300-s5 */
+&gpio_en_s5_rails {
+	no-auto-init;
+};
+
+/* pwr-pg-ec-rsmrst-od */
+&gpio_seq_ec_rsmrst_odl{
+	no-auto-init;
+};
+
+/* pwr-ec-pch-rsmrst-odl */
+&gpio_ec_soc_rsmrst_l{
+	no-auto-init;
+};
+
+/* pwr-pch-pwrok */
+&gpio_soc_pwrok{
+	no-auto-init;
+};
+
+/* pwr-ec-pch-sys-pwrok */
+&gpio_sys_pwrok{
+	no-auto-init;
+};
+
+/* pwr-sys-rst-l */
+&gpio_sys_rst_odl{
+	no-auto-init;
+};
+
+/* pwr-slp-s0-l */
+&gpio_sys_slp_s0ix_3v3_l{
+	no-auto-init;
+};
+
+/* pwr-slp-s3-l */
+&gpio_slp_s3_ls_l{
+	no-auto-init;
+};
+
+/* pwr-all-sys-pwrgd */
+&gpio_seq_ec_all_sys_pg{
+	no-auto-init;
+};
+
diff --git a/zephyr/projects/rex/prj.conf b/zephyr/projects/rex/prj.conf
new file mode 100644
index 0000000000..96f407b903
--- /dev/null
+++ b/zephyr/projects/rex/prj.conf
@@ -0,0 +1,172 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_PLATFORM_EC=y
+CONFIG_CROS_EC=y
+CONFIG_SHIMMED_TASKS=y
+CONFIG_SYSCON=y
+# Enable during development
+CONFIG_LTO=n
+CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y
+
+# Shell Commands
+CONFIG_SHELL_HELP=y
+CONFIG_SHELL_HISTORY=y
+CONFIG_SHELL_TAB=y
+CONFIG_SHELL_TAB_AUTOCOMPLETION=y
+CONFIG_KERNEL_SHELL=y
+
+# Logging
+CONFIG_LOG=y
+CONFIG_LOG_MODE_MINIMAL=y
+
+# Disable default features we don't want in a minimal example.
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=y
+CONFIG_PLATFORM_EC_SWITCH=y
+CONFIG_PLATFORM_EC_VBOOT_EFS2=n
+
+# Application processor; communicates with EC via eSPI
+CONFIG_AP=y
+CONFIG_ESPI=y
+CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S3=y
+CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S4=y
+CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S5=y
+CONFIG_PLATFORM_EC_HOSTCMD=y
+# Disabling this until temp sensor support is in
+CONFIG_PLATFORM_EC_THROTTLE_AP=n
+CONFIG_PLATFORM_EC_PORT80=y
+
+# Power Sequecing
+CONFIG_AP_X86_INTEL_MTL=y
+CONFIG_X86_NON_DSX_PWRSEQ_MTL=y
+CONFIG_X86_NON_DSX_PWRSEQ_HOST_CMD=y
+# TODO (b/240434243): This may be needed, but using eSPI VW for now
+CONFIG_PLATFORM_EC_POWERSEQ_SLP_S3_L_OVERRIDE=n
+CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n
+
+# Zephyr Inbuilt AP Power Sequencing Config
+CONFIG_AP_PWRSEQ=y
+CONFIG_X86_NON_DSX_PWRSEQ_CONSOLE=y
+CONFIG_AP_PWRSEQ_S0IX=y
+
+# ADC
+CONFIG_ADC=y
+
+# I2C
+CONFIG_I2C=y
+
+# PWM
+CONFIG_PWM=y
+
+# Fan
+CONFIG_TACH_NPCX=y
+
+# Temperature sensors
+CONFIG_SENSOR=y
+CONFIG_PLATFORM_EC_TEMP_SENSOR=y
+CONFIG_PLATFORM_EC_THERMISTOR=y
+CONFIG_PLATFORM_EC_TEMP_SENSOR_POWER=y
+
+# CBI EEPROM support
+CONFIG_EEPROM=y
+CONFIG_EEPROM_AT24=y
+CONFIG_EEPROM_SHELL=n
+CONFIG_PLATFORM_EC_CBI_EEPROM=y
+CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=y
+CONFIG_PLATFORM_EC_BYPASS_CBI_EEPROM_WP_CHECK=y
+
+# LED
+CONFIG_PLATFORM_EC_LED_DT=y
+
+# Battery
+CONFIG_PLATFORM_EC_BATTERY=y
+CONFIG_PLATFORM_EC_BATTERY_SMART=y
+CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y
+CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y
+CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO=y
+CONFIG_PLATFORM_EC_BATTERY_REVIVE_DISCONNECT=y
+
+# Charger
+CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y
+CONFIG_PLATFORM_EC_CHARGER_INPUT_CURRENT=512
+CONFIG_PLATFORM_EC_CHARGER_ISL9241=y
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=5
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=10
+CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON=30000
+CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT=15000
+
+# USB-A
+CONFIG_PLATFORM_EC_USBA=y
+
+# USBC
+CONFIG_PLATFORM_EC_USBC_PPC=y
+CONFIG_PLATFORM_EC_USBC_PPC_SYV682X=y
+CONFIG_PLATFORM_EC_USBC_PPC_SYV682C=y
+CONFIG_PLATFORM_EC_USBC_PPC_SYV682X_SMART_DISCHARGE=y
+
+CONFIG_PLATFORM_EC_USB_DRP_ACC_TRYSRC=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y
+CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y
+CONFIG_PLATFORM_EC_USB_PD_FRS=y
+CONFIG_PLATFORM_EC_USB_PD_FRS_PPC=y
+CONFIG_PLATFORM_EC_USB_PD_TCPC_LOW_POWER=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_TCPCI=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_NCT38XX=y
+CONFIG_PLATFORM_EC_USB_PD_TRY_SRC=y
+CONFIG_PLATFORM_EC_USB_PD_DUAL_ROLE_AUTO_TOGGLE=y
+CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_HB=y
+CONFIG_PLATFORM_EC_USBC_VCONN=y
+CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_CHARGER=y
+CONFIG_PLATFORM_EC_USB_PID=0x504D
+
+# IOEX
+CONFIG_GPIO_NCT38XX=y
+
+# BC 1.2
+CONFIG_PLATFORM_EC_BC12_DETECT_PI3USB9201=y
+
+#USB Mux
+CONFIG_PLATFORM_EC_USB_MUX_VIRTUAL=y
+CONFIG_PLATFORM_EC_USB_MUX_TASK=y
+
+# External power
+CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y
+
+# Standard shimmed features
+CONFIG_PLATFORM_EC_POWER_BUTTON=y
+CONFIG_PLATFORM_EC_LID_SWITCH=y
+
+# Keyboard support
+CONFIG_PLATFORM_EC_KEYBOARD=y
+CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_8042=y
+# Column 2 is driven through the GSC, which inverts the signal going through it
+CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED=y
+
+# MKBP event
+CONFIG_PLATFORM_EC_MKBP_EVENT=y
+CONFIG_PLATFORM_EC_MKBP_INPUT_DEVICES=y
+CONFIG_PLATFORM_EC_MKBP_USE_GPIO_AND_HOST_EVENT=y
+
+# Sensors console command
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=y
+
+# Sensors
+CONFIG_SENSOR=y
+CONFIG_SENSOR_SHELL=n
+CONFIG_PLATFORM_EC_MOTIONSENSE=y
+CONFIG_PLATFORM_EC_ACCEL_FIFO=y
+CONFIG_PLATFORM_EC_DYNAMIC_MOTION_SENSOR_COUNT=y
+CONFIG_PLATFORM_EC_GMR_TABLET_MODE=y
+CONFIG_PLATFORM_EC_LID_ANGLE=y
+CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y
+CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=y
+CONFIG_PLATFORM_EC_TABLET_MODE=y
+CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=y
+
+# Sensor Drivers
+CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSO=y
+CONFIG_PLATFORM_EC_ACCEL_LIS2DW12=y
+CONFIG_PLATFORM_EC_ALS_TCS3400=y
diff --git a/zephyr/projects/rex/prj_rex.conf b/zephyr/projects/rex/prj_rex.conf
new file mode 100644
index 0000000000..0f204b9669
--- /dev/null
+++ b/zephyr/projects/rex/prj_rex.conf
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Rex reference-board-specific Kconfig settings.
+CONFIG_BOARD_REX=y
+
+# Keyboard
+CONFIG_CROS_KB_RAW_NPCX=y
diff --git a/zephyr/projects/rex/rex.dts b/zephyr/projects/rex/rex.dts
new file mode 100644
index 0000000000..259cd6ff4c
--- /dev/null
+++ b/zephyr/projects/rex/rex.dts
@@ -0,0 +1,239 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+ #include <dt-bindings/usb_pd_tcpm.h>
+
+/ {
+	aliases {
+		gpio-wp = &ec_wp_l;
+		gpio-kbd-kso2 = &gpio_ec_kso_02_inv;
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+
+		ec_wp_l: write-protect {
+			gpios = <&gpioa 0 GPIO_INPUT>;
+		};
+		gpio_ec_entering_rw: ec_entering_rw {
+			enum-name = "GPIO_ENTERING_RW";
+		};
+
+		ioex_usb_c0_sbu_fault_odl: usb_c0_sbu_fault_odl {
+			gpios = <&ioex_c0_port1 2 GPIO_INPUT>;
+		};
+		ioex_usb_c0_rt_rst_ls_l: usb_c0_rt_rst_ls_l {
+			gpios = <&ioex_c0_port0 7 GPIO_OUTPUT>;
+		};
+
+		ioex_usb_c0_frs_en: usb_c0_frs_en {
+			gpios = <&ioex_c0_port0 6 GPIO_OUTPUT_LOW>;
+		};
+
+		/* Need to designate 1.8V for I2C buses on the 1800mV rail */
+		ec-i2c-sensor-scl {
+			gpios = <&gpiob 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		ec-i2c-sensor-sda {
+			gpios = <&gpiob 4 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		ec-i2c-c0-rt-scl {
+			gpios = <&gpiod 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		ec-i2c-c0-rt-sda {
+			gpios = <&gpiod 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+	};
+
+	usba-port-enable-list {
+		compatible = "cros-ec,usba-port-enable-pins";
+		enable-pins = <&gpio_en_pp5000_usba_r>;
+	};
+};
+
+/* host interface */
+&espi0 {
+	status = "okay";
+	pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>;
+	pinctrl-names = "default";
+};
+
+/* Power switch logic input pads */
+&psl_in1_gpd2 {
+	/* LID_OPEN */
+	psl-in-mode = "edge";
+	psl-in-pol = "high-rising";
+};
+
+&psl_in2_gp00 {
+	/* ACOK_OD */
+	psl-in-mode = "edge";
+	psl-in-pol = "high-rising";
+};
+
+&psl_in4_gp02 {
+	/* MECH_PWR_BTN_ODL */
+	psl-in-mode = "edge";
+	psl-in-pol = "low-falling";
+};
+
+/* Power domain device controlled by PSL (Power Switch Logic) IO pads */
+&power_ctrl_psl {
+	status = "okay";
+	pinctrl-names = "sleep";
+	pinctrl-0 = <&psl_in1_gpd2 &psl_in2_gp00 &psl_in3_gp01 &psl_in4_gp02>;
+};
+
+/* ADC and GPIO alt-function specifications */
+&adc0 {
+	pinctrl-0 = <&adc0_chan0_gp45
+		     &adc0_chan1_gp44
+		     &adc0_chan8_gpf1
+		     &adc0_chan7_gpe1>;
+	pinctrl-names = "default";
+};
+
+&i2c0_0 {
+	label = "I2C_SENSOR";
+	clock-frequency = <I2C_BITRATE_FAST>;
+
+	pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>;
+	pinctrl-names = "default";
+};
+
+&i2c1_0 {
+	label = "I2C_USB_C0_TCPC";
+	clock-frequency = <I2C_BITRATE_FAST>;
+
+	pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>;
+	pinctrl-names = "default";
+
+	tcpc_port0: nct38xx@70 {
+		compatible = "nuvoton,nct38xx";
+		gpio-dev = <&nct3807_C0>;
+		reg = <0x70>;
+		tcpc-flags = <(TCPC_FLAGS_TCPCI_REV2_0)>;
+	};
+
+	nct3807_C0:nct3807_C0@70 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nuvoton,nct38xx-gpio";
+		reg = <0x70>;
+		label = "NCT3807_C0";
+
+		ioex_c0_port0:gpio@0 {
+			compatible = "nuvoton,nct38xx-gpio-port";
+			reg = <0x0>;
+			label = "NCT3807_C0_GPIO0";
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <8>;
+			pin_mask = <0xff>;
+			pinmux_mask = <0xf7>;
+		};
+		ioex_c0_port1:gpio@1 {
+			compatible = "nuvoton,nct38xx-gpio-port";
+			reg = <0x1>;
+			label = "NCT3807_C0_GPIO1";
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <8>;
+			pin_mask = <0xff>;
+		};
+	};
+
+	nct3808_alert_0 {
+		compatible = "nuvoton,nct38xx-gpio-alert";
+		irq-gpios = <&gpioe 0 GPIO_ACTIVE_LOW>;
+		nct38xx-dev = <&nct3807_C0>;
+		label = "NCT3807_ALERT_0";
+	};
+};
+
+&i2c2_0 {
+	label = "I2C_PPC0";
+	clock-frequency = <I2C_BITRATE_FAST>;
+
+	pinctrl-0 = <&i2c2_0_sda_scl_gp91_92>;
+	pinctrl-names = "default";
+
+	bc12_port0: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+		irq = <&int_usb_c0_bc12>;
+	};
+
+	ppc_port0_syv: ppc_syv@40 {
+		compatible = "silergy,syv682x";
+		status = "okay";
+		reg = <0x40>;
+		frs_en_gpio = <&ioex_usb_c0_frs_en>;
+	};
+};
+
+&i2c3_0 {
+	label = "I2C_USB_C0_RT";
+	clock-frequency = <I2C_BITRATE_FAST>;
+
+	pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>;
+	pinctrl-names = "default";
+
+	usb_c0_hb_retimer: jhl8040r-c0@56 {
+		compatible = "intel,jhl8040r";
+		reg = <0x56>;
+		ls-en-pin = <&gpio_usb_c0_rt_3p3_sx_en>;
+		int-pin = <&gpio_usb_c0_rt_int_odl>;
+		reset-pin = <&ioex_usb_c0_rt_rst_ls_l>;
+	};
+};
+
+&i2c4_1 {
+	label = "I2_USB_C1_TCPC";
+	clock-frequency = <I2C_BITRATE_FAST>;
+
+	pinctrl-0 = <&i2c4_1_sda_scl_gpf2_f3>;
+	pinctrl-names = "default";
+};
+
+&i2c5_0 {
+	label = "I2C__BATTERY";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+
+	pinctrl-0 = <&i2c5_0_sda_scl_gp33_36>;
+	pinctrl-names = "default";
+};
+
+&i2c6_1 {
+	label = "I2C_USB_1_MIX";
+	clock-frequency = <I2C_BITRATE_FAST>;
+
+	pinctrl-0 = <&i2c6_1_sda_scl_gpe3_e4>;
+	pinctrl-names = "default";
+};
+
+&i2c7_0 {
+	label = "I2C_CHARGER";
+	clock-frequency = <I2C_BITRATE_FAST>;
+
+	pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>;
+	pinctrl-names = "default";
+
+	cbi_eeprom: eeprom@50 {
+		compatible = "atmel,at24";
+		reg = <0x50>;
+		size = <2048>;
+		pagesize = <16>;
+		address-width = <8>;
+		timeout = <5>;
+	};
+
+	charger: isl9241@9 {
+		compatible = "intersil,isl9241";
+		status = "okay";
+		reg = <0x09>;
+	};
+};
diff --git a/zephyr/projects/rex/rex0_gpio.csv b/zephyr/projects/rex/rex0_gpio.csv
new file mode 100644
index 0000000000..5c20f6fb00
--- /dev/null
+++ b/zephyr/projects/rex/rex0_gpio.csv
@@ -0,0 +1,122 @@
+Signal Name,Pin Number,Type,Enum
+USB_C1_BC12_INT_ODL,G10,INPUT,GPIO_USB_C1_BC12_INT_ODL
+ESPI_SOC_CS0_L,L2,OTHER,
+ESPI_SOC_RESET_L,K3,OTHER,
+ESPI_SOC_CLK,M1,OTHER,
+EC_IMU_INT_R_L,M2,INPUT_PU,
+ESPI_SOC_IO0,H1,OTHER,
+ESPI_SOC_IO1,J1,OTHER,
+ESPI_SOC_IO2,K1,OTHER,
+ESPI_SOC_IO3,L1,OTHER,
+ESPI_SOC_ALERT_L_R,L3,OTHER,
+EC_VOLDN_BTN_ODL,E11,INPUT_PU,GPIO_VOLUME_DOWN_L
+TABLET_MODE_L,M12,INPUT_PU,GPIO_TABLET_MODE_L
+SOCHOT_ODL,G12,INPUT,
+EC_VOLUP_BTN_ODL,L10,INPUT_PU,GPIO_VOLUME_UP_L
+USB_C0_RT_INT_ODL,G11,INPUT,
+EC_WP_L,L12,INPUT,
+EC_BATT_PRES_ODL,K12,INPUT,GPIO_BATT_PRES_ODL
+CPU_C10_GATE_L,J11,INPUT,
+SOC_PWROK,K11,OUTPUT,
+EC_SOC_RSMRST_L,F11,OUTPUT,
+SYS_PWROK,L11,OUTPUT,
+EC_SPARE_GPIO94,M11,OUTPUT,
+EC_SPARE_GPIOA2,F12,OUTPUT,
+EC_SPARE_GPIOA4,H11,OUTPUT,
+EC_ACCEL_INT_R_L,M7,INPUT,
+SLP_S3_LS_L,C2,INPUT,
+IMVP92_VRRDY_OD,E2,INPUT,
+EC_PROCHOT_IN_L,D2,INPUT,
+EC_SPARE_GPIO42,D3,OUTPUT,
+TEMP_SENSOR_2,E3,ADC,ADC_TEMP_SENSOR_2
+TEMP_SENSOR_1,F2,ADC,ADC_TEMP_SENSOR_1
+TEMP_SENSOR_4,F3,ADC,ADC_TEMP_SENSOR_4
+TEMP_SENSOR_3,G3,ADC,ADC_TEMP_SENSOR_3
+SYS_RST_ODL,H7,INPUT,
+EC_SOC_WAKE_R_ODL,H8,OUTPUT_ODL,
+EC_PROCHOT_ODL,J2,OUTPUT_ODR,
+EC_SOC_INT_ODL,J4,OUTPUT_ODL,GPIO_EC_INT_L
+EC_SOC_RTCRST,J5,OUTPUT_ODR,
+EC_SOC_PWR_BTN_ODL,H9,OUTPUT_ODL,GPIO_PCH_PWRBTN_L
+USB_C0_RT_3P3_SX_EN,D9,OUTPUT_ODR,
+KSO_13,D11,OTHER,
+KSO_12,C11,OTHER,
+KSO_11,B10,OTHER,
+KSO_10,B11,OTHER,
+KSO_09,C10,OTHER,
+KSO_08,C9,OTHER,
+KSO_05,C6,OTHER,
+KSO_04,C7,OTHER,
+KSO_03,B8,OTHER,
+EC_KSO_02_INV,B7,OUTPUT_L,
+KSO_01,B6,OTHER,
+KSO_00,B5,OTHER,
+KSI_07,C5,OTHER,
+KSI_06,C4,OTHER,
+KSI_05,C3,OTHER,
+KSI_04,B4,OTHER,
+EC_KSI_03,B3,OTHER,
+EC_KSI_02,A4,OTHER,
+KSI_01,A3,OTHER,
+EC_KSI_00,A2,OTHER,
+EC_I2C_BAT_SCL,D5,I2C_CLOCK,I2C_PORT_BATTERY
+USB_C1_TCPC_INT_ODL,B2,INPUT,GPIO_USB_C1_TCPC_INT_ODL
+EC_I2C_BAT_SDA,D4,I2C_DATA,
+USB_C1_RST_ODL,C1,OUTPUT_ODL,
+EC_FAN_TACH,E5,TACH,
+LED_4_L,G6,OUTPUT,
+EN_PP5000_FAN,K4,OUTPUT_ODR,
+USB_C0_PPC_INT_ODL,H2,INPUT,GPIO_USB_C0_PPC_INT_ODL
+UART_GSC_DBG_TX_EC_RX_R,G4,OTHER,
+EC_SPARE_GPIO66,G2,OUTPUT,
+USB_C0_TCPC_RST_ODL,J3,OUTPUT_ODL,
+USB_C1_RT_INT_ODL,M4,INPUT_PU,
+EC_CBI_WP,G5,OUTPUT,
+USB_C1_RT_RST_R_ODL,H5,OUTPUT_ODL,
+EC_GSC_PACKET_MODE,J6,OUTPUT_ODR,GPIO_PACKET_MODE_EN
+EC_KB_BL_PWM,K5,PWM,GPIO_EN_KEYBOARD_BACKLIGHT
+KSO_14,D6,OTHER,
+USB_C1_FRS_EN,D7,OUTPUT_ODR,
+EC_I2C_USB_C0_TCPC_SDA,K7,I2C_DATA,
+EC_I2C_USB_C0_TCPC_SCL,K8,I2C_CLOCK,I2C_PORT_USB_C0_TCPC
+EC_I2C_USB_C0_PPC_BC_SDA,K9,I2C_DATA,
+EC_I2C_USB_C0_PPC_BC_SCL,L8,I2C_CLOCK,I2C_PORT_PPC0
+EC_IMVP92_EN_SMB,D8,OUTPUT,
+EC_I2C_MISC_SDA,K10,I2C_DATA,
+EC_I2C_MISC_SCL,J10,I2C_CLOCK,I2C_PORT_EEPROM
+EC_I2C_SENSOR_SDA,B12,I2C_DATA,
+EC_I2C_SENSOR_SCL,C12,I2C_CLOCK,I2C_PORT_SENSOR
+EN_S5_RAILS,L9,OUTPUT_ODR,
+FAN_PWM,J7,PWM,
+LED_3_L,H10,OUTPUT,
+LED_2_L,G9,OUTPUT,
+LED_1_L,G8,OUTPUT,
+USB_C0_BC12_INT_ODL,D10,INPUT,GPIO_USB_C0_BC12_INT_ODL
+EC_SPARE_GPIOC7,F10,OUTPUT,
+EC_I2C_USB_C0_RT_SDA,F9,I2C_DATA,
+EC_I2C_USB_C0_RT_SCL,F8,I2C_CLOCK,I2C_PORT_USB_C0_RT
+EC_EDP_BL_EN,E10,OUTPUT_ODR,GPIO_ENABLE_BACKLIGHT
+EC_ALS_RGB_INT_R_L,A9,INPUT_PU,
+SYS_SLP_S0IX_3V3_L,A10,INPUT,
+USB_C0_TCPC_INT_ODL,F4,INPUT,GPIO_USB_C0_TCPC_INT_ODL
+SEQ_EC_RSMRST_ODL,A11,INPUT,
+EC_I2C_USB_C1_MIX_SDA,L7,I2C_DATA,
+EC_I2C_USB_C1_MIX_SCL,L6,I2C_CLOCK,I2C_PORT_USB_1_MIX
+CCD_MODE_ODL,A12,OUTPUT_ODL,GPIO_CCD_MODE_ODL
+EC_I2C_USB_C1_TCPC_SDA,F6,I2C_DATA,
+EC_I2C_USB_C1_TCPC_SCL,F5,I2C_CLOCK,I2C_PORT_USB_C1_TCPC
+SEQ_EC_ALL_SYS_PG,E9,INPUT,
+USB_C1_PPC_INT_ODL,E8,INPUT,GPIO_USB_C1_PPC_INT_ODL
+EC_KSO_07_JEN_L,B9,OTHER,
+EC_KSO_06_GP_SEL_L,C8,OTHER,
+EC_SPARE_GPO32,E4,OUTPUT,
+EC_SPARE_GPO35,K2,OUTPUT,
+UART_GSC_DBG_RX_EC_TX_R,H4,OTHER,
+EC_RST_R_ODL,K6,INPUT,
+EC_KB_BL_EN_L,J9,OUTPUT,
+ACOK_OD,E7,INPUT,GPIO_AC_PRESENT
+GSC_EC_PWR_BTN_ODL,E6,INPUT_PU,GPIO_POWER_BUTTON_L
+MECH_PWR_BTN_ODL,F7,INPUT,
+LID_OPEN,G7,INPUT_PU,GPIO_LID_OPEN
+EN_Z1_RAILS,J8,OUTPUT,
+EN_PP5000_USBA_R,H6,OUTPUT,
diff --git a/zephyr/projects/rex/src/board_power.c b/zephyr/projects/rex/src/board_power.c
new file mode 100644
index 0000000000..c7f12d024e
--- /dev/null
+++ b/zephyr/projects/rex/src/board_power.c
@@ -0,0 +1,61 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/logging/log.h>
+#include <zephyr/drivers/gpio.h>
+
+#include <ap_power/ap_power.h>
+#include <ap_power/ap_power_events.h>
+#include <ap_power/ap_power_interface.h>
+#include <ap_power_override_functions.h>
+#include <power_signals.h>
+#include <x86_power_signals.h>
+
+#include "gpio_signal.h"
+#include "gpio/gpio.h"
+
+LOG_MODULE_DECLARE(ap_pwrseq, LOG_LEVEL_INF);
+
+#if CONFIG_X86_NON_DSX_PWRSEQ_MTL
+#define X86_NON_DSX_MTL_FORCE_SHUTDOWN_TO_MS 50
+
+void board_ap_power_force_shutdown(void)
+{
+	int timeout_ms = X86_NON_DSX_MTL_FORCE_SHUTDOWN_TO_MS;
+
+	/* Turn off PCH_RMSRST to meet tPCH12 */
+	power_signal_set(PWR_EC_PCH_RSMRST, 0);
+
+	/* Turn off PRIM load switch. */
+	power_signal_set(PWR_EN_PP3300_A, 0);
+
+	/* Wait RSMRST to be off. */
+	while (power_signal_get(PWR_RSMRST) && (timeout_ms > 0)) {
+		k_msleep(1);
+		timeout_ms--;
+	};
+
+	if (power_signal_get(PWR_RSMRST)) {
+		LOG_WRN("RSMRST_ODL didn't go low!  Assuming G3.");
+	}
+}
+
+void board_ap_power_action_g3_s5(void)
+{
+	/* Turn on the PP3300_PRIM rail. */
+	power_signal_set(PWR_EN_PP3300_A, 1);
+
+	if (!power_wait_signals_timeout(
+		    IN_PGOOD_ALL_CORE,
+		    AP_PWRSEQ_DT_VALUE(wait_signal_timeout))) {
+		ap_power_ev_send_callbacks(AP_POWER_PRE_INIT);
+	}
+}
+
+bool board_ap_power_check_power_rails_enabled(void)
+{
+	return power_signal_get(PWR_EN_PP3300_A);
+}
+#endif /* CONFIG_X86_NON_DSX_PWRSEQ_MTL */
diff --git a/zephyr/projects/rex/src/usb_pd_policy.c b/zephyr/projects/rex/src/usb_pd_policy.c
new file mode 100644
index 0000000000..7e9876f9c1
--- /dev/null
+++ b/zephyr/projects/rex/src/usb_pd_policy.c
@@ -0,0 +1,77 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Shared USB-C policy for Rex boards */
+
+#include <zephyr/drivers/gpio.h>
+
+#include "charge_manager.h"
+#include "chipset.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "ioexpander.h"
+#include "system.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+int pd_check_vconn_swap(int port)
+{
+	/* Allow VCONN swaps if the AP is on. */
+	return chipset_in_state(CHIPSET_STATE_ANY_SUSPEND | CHIPSET_STATE_ON);
+}
+
+void pd_power_supply_reset(int port)
+{
+	/* Disable VBUS. */
+	ppc_vbus_source_enable(port, 0);
+
+	/* Enable discharge if we were previously sourcing 5V */
+	if (IS_ENABLED(CONFIG_USB_PD_DISCHARGE))
+		pd_set_vbus_discharge(port, 1);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	/* Disable charging. */
+	rv = ppc_vbus_sink_enable(port, 0);
+	if (rv)
+		return rv;
+
+	if (IS_ENABLED(CONFIG_USB_PD_DISCHARGE)) {
+		pd_set_vbus_discharge(port, 0);
+	}
+
+	/* Provide Vbus. */
+	rv = ppc_vbus_source_enable(port, 1);
+	if (rv) {
+		return rv;
+	}
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+/* Used by Vbus discharge common code with CONFIG_USB_PD_DISCHARGE */
+int board_vbus_source_enabled(int port)
+{
+	return tcpm_get_src_ctrl(port);
+}
+
+/* Used by USB charger task with CONFIG_USB_PD_5V_EN_CUSTOM */
+int board_is_sourcing_vbus(int port)
+{
+	return board_vbus_source_enabled(port);
+}
diff --git a/zephyr/projects/rex/src/usbc_config.c b/zephyr/projects/rex/src/usbc_config.c
new file mode 100644
index 0000000000..3aeaac8977
--- /dev/null
+++ b/zephyr/projects/rex/src/usbc_config.c
@@ -0,0 +1,288 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/drivers/gpio.h>
+
+#include "battery_fuel_gauge.h"
+#include "charger.h"
+#include "charge_manager.h"
+#include "charge_ramp.h"
+#include "charge_state_v2.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "driver/charger/isl9241.h"
+#include "driver/retimer/bb_retimer_public.h"
+#include "driver/tcpm/nct38xx.h"
+#include "driver/tcpm/tcpci.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "ioexpander.h"
+#include "ppc/syv682x_public.h"
+#include "system.h"
+#include "task.h"
+#include "usb_mux.h"
+#include "usbc_ppc.h"
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/*******************************************************************/
+/* USB-C Configuration Start */
+
+/* USB-C ports */
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_COUNT };
+BUILD_ASSERT(USBC_PORT_COUNT == CONFIG_USB_PD_PORT_MAX_COUNT);
+
+static void usbc_interrupt_init(void)
+{
+	/* Enable PPC interrupts. */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_ppc));
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_tcpc));
+
+	/* Enable BC 1.2 interrupts */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_bc12));
+
+	/* Enable SBU fault interrupts */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_sbu_fault));
+}
+DECLARE_HOOK(HOOK_INIT, usbc_interrupt_init, HOOK_PRIO_POST_I2C);
+
+void board_overcurrent_event(int port, int is_overcurrented)
+{
+	/*
+	 * TODO: Meteorlake PCH does not use Physical GPIO for over current
+	 * error, hence Send 'Over Current Virtual Wire' eSPI signal.
+	 */
+}
+
+void sbu_fault_interrupt(enum gpio_signal signal)
+{
+	int port = USBC_PORT_C0;
+
+	CPRINTSUSB("C%d: SBU fault", port);
+	pd_handle_overcurrent(port);
+}
+
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	int port;
+
+	switch (signal) {
+	case GPIO_USB_C0_TCPC_INT_ODL:
+		port = 0;
+		break;
+	default:
+		return;
+	}
+
+	schedule_deferred_pd_interrupt(port);
+}
+
+static void reset_nct38xx_port(int port)
+{
+	const struct gpio_dt_spec *reset_gpio_l;
+	const struct device *ioex_port0, *ioex_port1;
+
+	/* TODO(b/225189538): Save and restore ioex signals */
+	if (port == USBC_PORT_C0) {
+		reset_gpio_l = GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_rst_odl);
+		ioex_port0 = DEVICE_DT_GET(DT_NODELABEL(ioex_c0_port0));
+		ioex_port1 = DEVICE_DT_GET(DT_NODELABEL(ioex_c0_port1));
+	} else {
+		/* Invalid port: do nothing */
+		return;
+	}
+
+	gpio_pin_set_dt(reset_gpio_l, 0);
+	msleep(NCT38XX_RESET_HOLD_DELAY_MS);
+	gpio_pin_set_dt(reset_gpio_l, 1);
+	nct38xx_reset_notify(port);
+	if (NCT3807_RESET_POST_DELAY_MS != 0) {
+		msleep(NCT3807_RESET_POST_DELAY_MS);
+	}
+
+	/* Re-enable the IO expander pins */
+	gpio_reset_port(ioex_port0);
+	gpio_reset_port(ioex_port1);
+}
+
+void board_reset_pd_mcu(void)
+{
+	/* Reset TCPC0 */
+	reset_nct38xx_port(USBC_PORT_C0);
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+	const struct gpio_dt_spec *tcpc_c0_rst_l;
+	const struct gpio_dt_spec *tcpc_c0_int_l;
+
+	tcpc_c0_rst_l = GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_rst_odl);
+	tcpc_c0_int_l = GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_int_odl);
+
+	/*
+	 * Check which port has the ALERT line set and ignore if that TCPC has
+	 * its reset line active.
+	 */
+	if (!gpio_pin_get_dt(tcpc_c0_int_l) && gpio_pin_get_dt(tcpc_c0_rst_l)) {
+		status |= PD_STATUS_TCPC_ALERT_0;
+	}
+
+	return status;
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		syv682x_interrupt(USBC_PORT_C0);
+		break;
+
+	default:
+		break;
+	}
+}
+
+void bc12_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_BC12_INT_ODL:
+		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
+		break;
+
+	default:
+		break;
+	}
+}
+
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
+{
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+}
+
+static void board_disable_charger_ports(void)
+{
+	int i;
+
+	CPRINTSUSB("Disabling all charger ports");
+
+	/* Disable all ports. */
+	for (i = 0; i < ppc_cnt; i++) {
+		/*
+		 * If this port had booted in dead battery mode, go
+		 * ahead and reset it so EN_SNK responds properly.
+		 */
+		if (nct38xx_get_boot_type(i) == NCT38XX_BOOT_DEAD_BATTERY) {
+			reset_nct38xx_port(i);
+			pd_set_error_recovery(i);
+		}
+
+		/*
+		 * Do not return early if one fails otherwise we can
+		 * get into a boot loop assertion failure.
+		 */
+		if (ppc_vbus_sink_enable(i, 0)) {
+			CPRINTSUSB("Disabling C%d as sink failed.", i);
+		}
+	}
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int i;
+	int rv;
+
+	if (port == CHARGE_PORT_NONE) {
+		board_disable_charger_ports();
+		return EC_SUCCESS;
+	} else if (!is_valid_port) {
+		return EC_ERROR_INVAL;
+	}
+
+	/*
+	 * Check if we can reset any ports in dead battery mode
+	 *
+	 * The NCT3807 may continue to keep EN_SNK low on the dead battery port
+	 * and allow a dangerous level of voltage to pass through to the initial
+	 * charge port (see b/183660105).  We must reset the ports if we have
+	 * sufficient battery to do so, which will bring EN_SNK back under
+	 * normal control.
+	 */
+	rv = EC_SUCCESS;
+	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
+		if (nct38xx_get_boot_type(i) != NCT38XX_BOOT_DEAD_BATTERY) {
+			continue;
+		}
+
+		/* Handle dead battery boot case */
+		CPRINTSUSB("Found dead battery on %d", i);
+		/*
+		 * If we have battery, get this port reset ASAP.
+		 * This means temporarily rejecting charge manager
+		 * sets to it.
+		 */
+		if (pd_is_battery_capable()) {
+			reset_nct38xx_port(i);
+			pd_set_error_recovery(i);
+
+			if (port == i) {
+				rv = EC_ERROR_INVAL;
+			}
+		} else if (port != i) {
+			/*
+			 * If other port is selected and in dead battery
+			 * mode, reset this port.  Otherwise, reject
+			 * change because we'll brown out.
+			 */
+			if (nct38xx_get_boot_type(port) ==
+			    NCT38XX_BOOT_DEAD_BATTERY) {
+				reset_nct38xx_port(i);
+				pd_set_error_recovery(i);
+			} else {
+				rv = EC_ERROR_INVAL;
+			}
+		}
+	}
+
+	if (rv != EC_SUCCESS) {
+		return rv;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (tcpm_get_src_ctrl(port)) {
+		CPRINTSUSB("Skip enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTSUSB("New charge port: C%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < ppc_cnt; i++) {
+		if (i == port) {
+			continue;
+		}
+		if (ppc_vbus_sink_enable(i, 0)) {
+			CPRINTSUSB("C%d: sink path disable failed.", i);
+		}
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTSUSB("C%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
diff --git a/zephyr/projects/rex/temp_sensors.dts b/zephyr/projects/rex/temp_sensors.dts
new file mode 100644
index 0000000000..680ebc8954
--- /dev/null
+++ b/zephyr/projects/rex/temp_sensors.dts
@@ -0,0 +1,69 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <cros/thermistor/thermistor.dtsi>
+
+/ {
+	temp_ddr_soc: ddr_soc {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_30K9_47K_4050B>;
+		adc = <&adc_ddr_soc>;
+	};
+	temp_ambient: ambient {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_30K9_47K_4050B>;
+		adc = <&adc_ambient>;
+	};
+	temp_charger: charger {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_30K9_47K_4050B>;
+		adc = <&adc_charger>;
+	};
+	temp_wwan: wwan {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_30K9_47K_4050B>;
+		adc = <&adc_wwan>;
+	};
+
+	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
+		ddr_soc {
+			temp_fan_off = <35>;
+			temp_fan_max = <60>;
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			sensor = <&temp_ddr_soc>;
+		};
+		ambient {
+			temp_fan_off = <35>;
+			temp_fan_max = <60>;
+			temp_host_high = <85>;
+			temp_host_halt = <90>;
+			temp_host_release_high = <80>;
+			sensor = <&temp_ambient>;
+		};
+		charger {
+			temp_fan_off = <35>;
+			temp_fan_max = <65>;
+			temp_host_high = <105>;
+			temp_host_halt = <120>;
+			temp_host_release_high = <90>;
+			sensor = <&temp_charger>;
+		};
+		wwan {
+			temp_fan_off = <35>;
+			temp_fan_max = <60>;
+			temp_host_high = <130>;
+			temp_host_halt = <130>;
+			temp_host_release_high = <100>;
+			sensor = <&temp_wwan>;
+		};
+	};
+};
+
+&thermistor_3V3_30K9_47K_4050B {
+	status = "okay";
+};
diff --git a/zephyr/projects/rex/usbc.dts b/zephyr/projects/rex/usbc.dts
new file mode 100644
index 0000000000..8b3d0aa316
--- /dev/null
+++ b/zephyr/projects/rex/usbc.dts
@@ -0,0 +1,30 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		usbc_port0: port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+			bc12 = <&i2c_ec_i2c_usb_c0_ppc_b>;
+			ppc = <&ppc_port0_syv>;
+			tcpc = <&tcpc_port0>;
+			chg = <&charger>;
+			usb-mux-chain-0 {
+				compatible = "cros-ec,usb-mux-chain";
+				usb-muxes = <&usb_c0_hb_retimer
+					     &virtual_mux_c0>;
+			};
+		};
+		port0-muxes {
+			virtual_mux_c0: virtual-mux-c0 {
+				compatible = "cros-ec,usbc-mux-virtual";
+			};
+		};
+	};
+};
diff --git a/zephyr/projects/skyrim/BUILD.py b/zephyr/projects/skyrim/BUILD.py
index 3d43b3676b..ff53aeefda 100644
--- a/zephyr/projects/skyrim/BUILD.py
+++ b/zephyr/projects/skyrim/BUILD.py
@@ -1,11 +1,15 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 """Define zmake projects for skyrim."""
 
 
-def register_variant(project_name):
+def register_skyrim_project(
+    project_name,
+    extra_dts_overlays=(),
+    extra_kconfig_files=(),
+):
     """Register a variant of skyrim."""
     register_npcx_project(
         project_name=project_name,
@@ -13,26 +17,56 @@ def register_variant(project_name):
         dts_overlays=[
             # Common to all projects.
             here / "adc.dts",
-            here / "battery.dts",
             here / "fan.dts",
             here / "gpio.dts",
-            here / "i2c.dts",
             here / "interrupts.dts",
             here / "keyboard.dts",
-            here / "led_pins_skyrim.dts",
-            here / "led_policy_skyrim.dts",
             here / "motionsense.dts",
             here / "usbc.dts",
             # Project-specific DTS customizations.
-            here / f"{project_name}.dts",
-        ],
-        kconfig_files=[
-            here / f"prj_{project_name}.conf",
+            *extra_dts_overlays,
         ],
+        kconfig_files=[here / "prj.conf", *extra_kconfig_files],
     )
 
 
-register_variant(project_name="skyrim")
+register_skyrim_project(
+    project_name="morthal",
+    extra_dts_overlays=[
+        here / "morthal.dts",
+        here / "battery_morthal.dts",
+        here / "led_pins_morthal.dts",
+        here / "led_policy_morthal.dts",
+    ],
+    extra_kconfig_files=[
+        here / "prj_morthal.conf",
+    ],
+)
+
+
+register_skyrim_project(
+    project_name="skyrim",
+    extra_dts_overlays=[
+        here / "skyrim.dts",
+        here / "battery_skyrim.dts",
+        here / "led_pins_skyrim.dts",
+        here / "led_policy_skyrim.dts",
+    ],
+    extra_kconfig_files=[
+        here / "prj_skyrim.conf",
+    ],
+)
+
 
-# TODO: Deprecate guybrush build after skyrim hardware is readily available.
-# register_variant(project_name="guybrush")
+register_skyrim_project(
+    project_name="winterhold",
+    extra_dts_overlays=[
+        here / "winterhold.dts",
+        here / "battery_winterhold.dts",
+        here / "led_pins_winterhold.dts",
+        here / "led_policy_winterhold.dts",
+    ],
+    extra_kconfig_files=[
+        here / "prj_winterhold.conf",
+    ],
+)
diff --git a/zephyr/projects/skyrim/CMakeLists.txt b/zephyr/projects/skyrim/CMakeLists.txt
index b364421eb4..5c466e87e8 100644
--- a/zephyr/projects/skyrim/CMakeLists.txt
+++ b/zephyr/projects/skyrim/CMakeLists.txt
@@ -1,23 +1,46 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 cmake_minimum_required(VERSION 3.13.1)
 
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-project(guybrush)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
 
-cros_ec_library_include_directories_ifdef(CONFIG_BOARD_SKYRIM include)
-cros_ec_library_include_directories_ifdef(CONFIG_BOARD_GUYBRUSH include_guybrush)
+zephyr_library_sources("src/common.c")
+zephyr_library_sources("src/power_signals.c")
 
-zephyr_library_sources_ifdef(CONFIG_BOARD_SKYRIM "power_signals.c")
-zephyr_library_sources_ifdef(CONFIG_BOARD_GUYBRUSH "power_signals_guybrush.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC
+	"src/usb_pd_policy.c"
+	"src/usbc_config.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LED_COMMON
+	"src/led.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_AMD_STT
+	"src/stt.c")
 
-zephyr_library_sources_ifdef(CONFIG_BOARD_SKYRIM "usbc_config.c")
-zephyr_library_sources_ifdef(CONFIG_BOARD_GUYBRUSH "usbc_config_guybrush.c")
+if(DEFINED CONFIG_BOARD_MORTHAL)
+	project(morthal)
+	zephyr_library_sources(
+		"src/morthal/ppc_config.c"
+		"src/morthal/usb_mux_config.c"
+)
+endif()
 
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC
-	"usb_pd_policy.c")
+if(DEFINED CONFIG_BOARD_SKYRIM)
+	project(skyrim)
+	cros_ec_library_include_directories_ifdef(CONFIG_BOARD_SKYRIM include)
+	zephyr_library_sources(
+			"src/skyrim/usb_mux_config.c"
+			"src/skyrim/ppc_config.c"
+			"src/skyrim/form_factor.c"
+			"src/skyrim/alt_charger.c"
+	)
+	zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FAN "src/skyrim/fan.c")
+endif()
 
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LED_COMMON
-	"led.c")
+if(DEFINED CONFIG_BOARD_WINTERHOLD)
+	project(winterhold)
+	zephyr_library_sources(
+		"src/winterhold/usb_mux_config.c"
+		"src/winterhold/ppc_config.c"
+    )
+endif()
diff --git a/zephyr/projects/skyrim/Kconfig b/zephyr/projects/skyrim/Kconfig
index ea68baf71b..d2ef60fa52 100644
--- a/zephyr/projects/skyrim/Kconfig
+++ b/zephyr/projects/skyrim/Kconfig
@@ -1,12 +1,12 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
-config BOARD_GUYBRUSH
-	bool "Google Guybrush Board"
+config BOARD_MORTHAL
+	bool "Google Morthal Board"
 	help
-	  Build Google Guybrush reference board.  This board build is a
-	  prototype rather than a releasing product.
+	  Build Google Morthal reference board.  This board uses an AMD SoC
+	  and NPCX9 EC
 
 config BOARD_SKYRIM
 	bool "Google Skyrim Board"
@@ -14,4 +14,14 @@ config BOARD_SKYRIM
 	  Build Google Skyrim reference board.  This board uses an AMD SoC
 	  and NPCX9 EC
 
+config BOARD_WINTERHOLD
+	bool "Google Winterhold Board"
+	help
+	  Build Google Winterhold reference board.  This board uses an AMD SoC
+	  and NPCX9 EC
+
+module = SKYRIM
+module-str = Skyrim board-specific code
+source "subsys/logging/Kconfig.template.log_config"
+
 source "Kconfig.zephyr"
diff --git a/zephyr/projects/skyrim/adc.dts b/zephyr/projects/skyrim/adc.dts
index 40fe146a06..0f2ffd6436 100644
--- a/zephyr/projects/skyrim/adc.dts
+++ b/zephyr/projects/skyrim/adc.dts
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,63 +10,60 @@
 		compatible = "named-adc-channels";
 
 		adc_temp_charger: temp-charger {
-			label = "CHARGER";
 			enum-name = "ADC_TEMP_SENSOR_CHARGER";
 			io-channels = <&adc0 1>;
 		};
 		adc_temp_memory: temp-memory {
-			label = "MEMORY";
 			enum-name = "ADC_TEMP_SENSOR_MEMORY";
 			io-channels = <&adc0 2>;
 		};
 		adc_core_imon1: core-imon1 {
-			label = "CORE_I";
 			enum-name = "ADC_CORE_IMON1";
 			io-channels = <&adc0 3>;
 		};
 		adc_core_imon2: core-imon2 {
-			label = "SOC_I";
 			enum-name = "ADC_SOC_IMON2";
 			io-channels = <&adc0 4>;
 		};
 	};
 
+	temp_charger_thermistor: charger-thermistor {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_30K9_47K_4050B>;
+		adc = <&adc_temp_charger>;
+	};
+
+	temp_memory_thermistor: memory-thermistor {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_30K9_47K_4050B>;
+		adc = <&adc_temp_memory>;
+	};
+
 	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
 		charger-thermistor {
-			compatible = "cros-ec,temp-sensor-thermistor",
-				     "cros-ec,temp-sensor";
-			thermistor = <&thermistor_3V3_30K9_47K_4050B>;
-			label = "Charger";
-			enum-name = "TEMP_SENSOR_CHARGER";
 			temp_host_high = <100>;
 			temp_host_halt = <105>;
 			temp_host_release_high = <80>;
-			adc = <&adc_temp_charger>;
+			sensor = <&temp_charger_thermistor>;
 		};
+
 		memory-thermistor {
-			compatible = "cros-ec,temp-sensor-thermistor",
-				     "cros-ec,temp-sensor";
-			thermistor = <&thermistor_3V3_30K9_47K_4050B>;
-			label = "Memory";
-			enum-name = "TEMP_SENSOR_MEMORY";
 			temp_host_high = <100>;
 			temp_host_halt = <105>;
 			temp_host_release_high = <80>;
-			adc = <&adc_temp_memory>;
 			power-good-pin = <&gpio_pg_pwr_s5>;
+			sensor = <&temp_memory_thermistor>;
 		};
-		sb-tsi-sensor {
-			compatible = "cros-ec,temp-sensor-sb-tsi",
-				     "cros-ec,temp-sensor";
-			label = "CPU";
-			enum-name = "TEMP_SENSOR_CPU";
-			port = <&i2c_soc_thermal>;
+
+		cpu {
 			temp_host_high = <100>;
 			temp_host_halt = <105>;
 			temp_host_release_high = <80>;
 			temp_fan_off = <60>;
 			temp_fan_max = <90>;
 			power-good-pin = <&gpio_s0_pgood>;
+			sensor = <&temp_cpu>;
 		};
 	};
 };
diff --git a/zephyr/projects/skyrim/battery.dts b/zephyr/projects/skyrim/battery_morthal.dts
index b9fc0d1090..8c87cef7f9 100644
--- a/zephyr/projects/skyrim/battery.dts
+++ b/zephyr/projects/skyrim/battery_morthal.dts
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/skyrim/battery_skyrim.dts b/zephyr/projects/skyrim/battery_skyrim.dts
new file mode 100644
index 0000000000..8c87cef7f9
--- /dev/null
+++ b/zephyr/projects/skyrim/battery_skyrim.dts
@@ -0,0 +1,15 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	batteries {
+		default_battery: aec_5477109 {
+			compatible = "aec,5477109", "battery-smart";
+		};
+		smp_l20m3pg1 {
+			compatible = "smp,l20m3pg1", "battery-smart";
+		};
+	};
+};
diff --git a/zephyr/projects/skyrim/battery_winterhold.dts b/zephyr/projects/skyrim/battery_winterhold.dts
new file mode 100644
index 0000000000..776d74cdff
--- /dev/null
+++ b/zephyr/projects/skyrim/battery_winterhold.dts
@@ -0,0 +1,33 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	batteries {
+		default_battery: lgc_xphx8 {
+			compatible = "lgc,xphx8", "battery-smart";
+		};
+		smp_atlxdy9k {
+			compatible = "smp,atlxdy9k", "battery-smart";
+		};
+		smp_cosxdy9k{
+			compatible = "smp,cosxdy9k", "battery-smart";
+		};
+		byd_wv3k8{
+			compatible = "byd,wv3k8", "battery-smart";
+		};
+		cosmx_mvk11{
+			compatible = "cosmx,mvk11", "battery-smart";
+		};
+		sunwoda_atl3rr09{
+			compatible = "sunwoda,atl3rr09", "battery-smart";
+		};
+		sunwoda_cos3rr09{
+			compatible = "sunwoda,cos3rr09", "battery-smart";
+		};
+		atl_cfd72{
+			compatible = "atl,cfd72", "battery-smart";
+		};
+	};
+};
diff --git a/zephyr/projects/skyrim/fan.dts b/zephyr/projects/skyrim/fan.dts
index 042b9399dc..f0bc28cb7e 100644
--- a/zephyr/projects/skyrim/fan.dts
+++ b/zephyr/projects/skyrim/fan.dts
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,7 +9,6 @@
 
 		fan_0 {
 			pwms = <&pwm0 0 PWM_KHZ(25) PWM_POLARITY_NORMAL>;
-			pwm-frequency = <25000>;
 			rpm_min = <3100>;
 			rpm_start = <3100>;
 			rpm_max = <8000>;
diff --git a/zephyr/projects/skyrim/gpio.dts b/zephyr/projects/skyrim/gpio.dts
index a06bb070ab..4c935320b2 100644
--- a/zephyr/projects/skyrim/gpio.dts
+++ b/zephyr/projects/skyrim/gpio.dts
@@ -1,9 +1,15 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 / {
+	aliases {
+		gpio-wp = &gpio_wp;
+		gpio-cbi-wp = &gpio_cbi_wp;
+		gpio-kbd-kso2 = &gpio_ec_kso_02_inv;
+	};
+
 	/* GPIOs shared by all boards */
 	named-gpios {
 		compatible = "named-gpios";
@@ -22,6 +28,7 @@
 		gpio_slp_s3_l: slp_s3_l {
 			gpios = <&gpio6 1 GPIO_INPUT>;
 			enum-name = "GPIO_PCH_SLP_S3_L";
+			alias = "GPIO_PCH_SLP_S0_L";
 		};
 		gpio_slp_s5_l: slp_s5_l {
 			gpios = <&gpio7 2 GPIO_INPUT>;
@@ -119,6 +126,81 @@
 			gpios = <&gpioa 6 GPIO_OUTPUT_HIGH>;
 			enum-name = "GPIO_ENABLE_BACKLIGHT_L";
 		};
+		gpio_usb_fault_odl: usb_fault_odl {
+			gpios = <&gpio5 0 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>;
+		};
+		gpio_en_pwr_s3: en_pwr_s3 {
+			gpios = <&gpio7 4 GPIO_OUTPUT_LOW>;
+		};
+		gpio_pg_groupc_s0_od: pg_groupc_s0_od {
+			gpios = <&gpiof 0 GPIO_INPUT>;
+		};
+		gpio_ec_i2c_usbc_pd_int: ec_i2c_usbc_pd_int {
+			gpios = <&gpioa 3 GPIO_INPUT>;
+		};
+		gpio_soc_thermtrip_odl: soc_thermtrip_odl {
+			gpios = <&gpio9 5 GPIO_INPUT>;
+		};
+		gpio_hub_rst: hub_rst {
+			gpios = <&gpio6 6 GPIO_OUTPUT_HIGH>;
+		};
+		ec_soc_int_l {
+			gpios = <&gpioa 1 GPIO_OUTPUT_HIGH>;
+			enum-name = "GPIO_EC_INT_L";
+		};
+		gpio_ec_soc_pwr_good: ec_soc_pwr_good {
+			gpios = <&gpiod 3 GPIO_OUTPUT_LOW>;
+		};
+		/* TODO: Add interrupt handler to shut down */
+		pcore_ocp_r_l {
+			gpios = <&gpioa 5 GPIO_INPUT>;
+		};
+		gpio_usb_hub_fault_q_odl: usb_hub_fault_q_odl {
+			gpios = <&gpioe 5 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_pg_lpddr5_s3_od: pg_lpddr5_s3_od {
+			gpios = <&gpio7 3 GPIO_INPUT>;
+		};
+		3axis_int_l {
+			gpios = <&gpioa 2 GPIO_INPUT_PULL_UP>;
+		};
+		gpio_ec_soc_pwr_btn_l: ec_soc_pwr_btn_l {
+			gpios = <&gpioa 7 GPIO_OUTPUT_HIGH>;
+			enum-name = "GPIO_PCH_PWRBTN_L";
+		};
+		gpio_volup_btn_odl: volup_btn_odl {
+			gpios = <&gpio6 7 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_UP_L";
+		};
+		gpio_voldn_btn_odl: voldn_btn_odl {
+			gpios = <&gpio7 0 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_DOWN_L";
+		};
+		ec_sc_rst {
+			gpios = <&gpiob 0 GPIO_OUTPUT_LOW>;
+		};
+		gpio_cbi_wp: ec_cbi_wp {
+			gpios = <&gpio8 1 GPIO_OUTPUT_LOW>;
+		};
+		gpio_wp: ec_wp_l {
+			gpios = <&gpiod 7 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		gpio_pg_lpddr5_s0_od: pg_lpddr5_s0_od {
+			gpios = <&gpio6 0 GPIO_INPUT>;
+		};
+		ec_espi_rst_l {
+			gpios = <&gpio5 4 GPIO_PULL_DOWN>;
+		};
+		gpio_accel_gyro_int_l: accel_gyro_int_l {
+			gpios = <&gpioa 0 GPIO_INPUT>;
+		};
+		/* unimplemented GPIOs */
+		entering-rw {
+			enum-name = "GPIO_ENTERING_RW";
+		};
+		pch-sys-prwok {
+			enum-name = "GPIO_PCH_SYS_PWROK";
+		};
 		ec_i2c_usb_a0_c0_scl {
 			gpios = <&gpiob 5 GPIO_INPUT>;
 		};
@@ -132,10 +214,10 @@
 			gpios = <&gpio8 7 GPIO_INPUT>;
 		};
 		ec_i2c_batt_scl {
-			gpios = <&gpio9 2 GPIO_INPUT>;
+			gpios = <&gpio9 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
 		};
 		ec_i2c_batt_sda {
-			gpios = <&gpio9 1 GPIO_INPUT>;
+			gpios = <&gpio9 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
 		};
 		ec_i2c_usbc_mux_scl {
 			gpios = <&gpiod 1 GPIO_INPUT>;
@@ -156,16 +238,16 @@
 			gpios = <&gpio3 6 GPIO_INPUT>;
 		};
 		ec_i2c_sensor_scl {
-			gpios = <&gpioe 4 GPIO_INPUT>;
+			gpios = <&gpioe 4 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
 		};
 		ec_i2c_sensor_sda {
-			gpios = <&gpioe 3 GPIO_INPUT>;
+			gpios = <&gpioe 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
 		};
 		ec_i2c_soc_sic {
-			gpios = <&gpiob 3 GPIO_INPUT>;
+			gpios = <&gpiob 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
 		};
 		ec_i2c_soc_sid {
-			gpios = <&gpiob 2 GPIO_INPUT>;
+			gpios = <&gpiob 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
 		};
 		en_kb_bl {
 			gpios = <&gpio9 7 GPIO_OUTPUT_HIGH>;
@@ -191,27 +273,21 @@
 		};
 		usb_c0_ppc_en_l {
 			gpios = <&ioex_c0_port1 0 GPIO_OUTPUT_LOW>;
-			enum-name = "IOEX_USB_C0_PPC_EN_L";
 		};
-		usb_c0_ppc_ilim_3a_en {
+		ioex_usb_c0_ilim_3a_en: usb_c0_ppc_ilim_3a_en {
 			gpios = <&ioex_c0_port1 1 GPIO_OUTPUT_LOW>;
 			enum-name = "IOEX_USB_C0_PPC_ILIM_3A_EN";
 		};
-		/* TODO: figure out interrupts */
-		usb_c0_sbu_fault_odl {
+		ioex_usb_c0_sbu_fault_odl: usb_c0_sbu_fault_odl {
 			gpios = <&ioex_c0_port1 2 GPIO_INPUT>;
-			enum-name = "IOEX_USB_C0_FAULT_ODL";
 		};
 		ioex_en_pp5000_usb_a0_vbus: en_pp5000_usb_a0_vbus {
 			gpios = <&ioex_c0_port1 5 GPIO_OUTPUT_LOW>;
-			enum-name = "IOEX_EN_PP5000_USB_A0_VBUS";
 		};
-		/* TODO: figure out interrupts */
-		usb_a0_fault_odl {
+		ioex_usb_a0_fault_odl: usb_a0_fault_odl {
 			gpios = <&ioex_c0_port1 6 GPIO_INPUT>;
-			enum-name = "IOEX_USB3_A0_FAULT_L";
 		};
-		usb_c0_sbu_flip {
+		ioex_usb_c0_sbu_flip: usb_c0_sbu_flip {
 			gpios = <&ioex_c0_port1 7 GPIO_OUTPUT_LOW>;
 			enum-name = "IOEX_USB_C0_SBU_FLIP";
 		};
@@ -222,7 +298,6 @@
 		};
 		usb_a1_retimer_rst {
 			gpios = <&ioex_c1_port0 1 GPIO_OUTPUT_LOW>;
-			enum-name = "IOEX_USB_A1_RETIMER_RST";
 		};
 		usb_c1_in_hpd {
 			gpios = <&ioex_c1_port0 3 GPIO_OUTPUT_LOW>;
@@ -234,27 +309,22 @@
 		};
 		usb_c1_ppc_en_l {
 			gpios = <&ioex_c1_port1 0 GPIO_OUTPUT_LOW>;
-			enum-name = "IOEX_USB_C1_PPC_EN_L";
 		};
 		usb_c1_ppc_ilim_3a_en {
 			gpios = <&ioex_c1_port1 1 GPIO_OUTPUT_LOW>;
 			enum-name = "IOEX_USB_C1_PPC_ILIM_3A_EN";
 		};
-		/* TODO: figure out interrupts */
-		usb_c1_sbu_fault_odl {
+		ioex_usb_c1_sbu_fault_odl: usb_c1_sbu_fault_odl {
 			gpios = <&ioex_c1_port1 2 GPIO_INPUT>;
 			enum-name = "IOEX_USB_C1_FAULT_ODL";
 		};
 		ioex_en_pp5000_usb_a1_vbus: en_pp5000_usb_a1_vbus {
 			gpios = <&ioex_c1_port1 5 GPIO_OUTPUT_LOW>;
-			enum-name = "IOEX_EN_PP5000_USB_A1_VBUS_DB";
 		};
-		/* TODO: figure out interrupts */
-		usb_a1_fault_db_odl {
+		ioex_usb_a1_fault_db_odl: usb_a1_fault_db_odl {
 			gpios = <&ioex_c1_port1 6 GPIO_INPUT>;
-			enum-name = "IOEX_USB_A1_FAULT_DB_ODL";
 		};
-		usb_c1_sbu_flip {
+		ioex_usb_c1_sbu_flip: usb_c1_sbu_flip {
 			gpios = <&ioex_c1_port1 7 GPIO_OUTPUT_LOW>;
 			enum-name = "IOEX_USB_C1_SBU_FLIP";
 		};
@@ -265,100 +335,37 @@
 		enable-pins = <&ioex_en_pp5000_usb_a0_vbus
 			       &ioex_en_pp5000_usb_a1_vbus>;
 	};
-
-	vsby-psl-in-list {
-		/* PSL_IN1/2/4 are used to wake */
-		psl-in-pads = <&psl_in1 &psl_in2 &psl_in4>;
-		status = "okay";
-	};
 };
 
 /* PSL input pads*/
-&psl_in1 {
+&psl_in1_gpd2 {
 	/* MECH_PWR_BTN_ODL */
-	flag = <NPCX_PSL_FALLING_EDGE>;
+	psl-in-mode = "edge";
+	psl-in-pol = "low-falling";
 };
 
-&psl_in2 {
+&psl_in2_gp00 {
 	/* ACOK_OD */
-	flag = <NPCX_PSL_RISING_EDGE>;
+	psl-in-mode = "edge";
+	psl-in-pol = "high-rising";
 };
 
-&psl_in4 {
+&psl_in4_gp02 {
 	/* LID_OPEN */
-	flag = <NPCX_PSL_RISING_EDGE>;
+	psl-in-mode = "edge";
+	psl-in-pol = "high-rising";
 };
 
-&i2c0_0 {
-	nct3807_C0:nct3807_C0@70 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "nuvoton,nct38xx-gpio";
-		reg = <0x70>;
-		label = "NCT3807_C0";
-
-		ioex_c0_port0:gpio@0 {
-			compatible = "nuvoton,nct38xx-gpio-port";
-			reg = <0x0>;
-			label = "NCT3807_C0_GPIO0";
-			gpio-controller;
-			#gpio-cells = <2>;
-			ngpios = <8>;
-			pin_mask = <0xff>;
-			pinmux_mask = <0xf7>;
-		};
-		ioex_c0_port1:gpio@1 {
-			compatible = "nuvoton,nct38xx-gpio-port";
-			reg = <0x1>;
-			label = "NCT3807_C0_GPIO1";
-			gpio-controller;
-			#gpio-cells = <2>;
-			ngpios = <8>;
-			pin_mask = <0xff>;
-		};
-	};
-
-	nct3808_alert_0 {
-		compatible = "nuvoton,nct38xx-gpio-alert";
-		irq-gpios = <&gpioe 0 GPIO_ACTIVE_LOW>;
-		nct38xx-dev = <&nct3807_C0>;
-		label = "NCT3807_ALERT_0";
-	};
+/* Power domain device controlled by PSL (Power Switch Logic) IO pads */
+&power_ctrl_psl {
+	status = "okay";
+	pinctrl-names = "sleep";
+	pinctrl-0 = <&psl_in1_gpd2 &psl_in2_gp00 &psl_in4_gp02>;
 };
 
-&i2c1_0 {
-	nct3807_C1:nct3807_C1@70 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "nuvoton,nct38xx-gpio";
-		reg = <0x70>;
-		label = "NCT3807_C1";
-
-		ioex_c1_port0:gpio@0 {
-			compatible = "nuvoton,nct38xx-gpio-port";
-			reg = <0x0>;
-			label = "NCT3807_C1_GPIO0";
-			gpio-controller;
-			#gpio-cells = <2>;
-			ngpios = <8>;
-			pin_mask = <0xff>;
-			pinmux_mask = <0xf7>;
-		};
-		ioex_c1_port1:gpio@1 {
-			compatible = "nuvoton,nct38xx-gpio-port";
-			reg = <0x1>;
-			label = "NCT3807_C1_GPIO1";
-			gpio-controller;
-			#gpio-cells = <2>;
-			ngpios = <8>;
-			pin_mask = <0xff>;
-		};
-	};
-
-	nct3808_alert_1 {
-		compatible = "nuvoton,nct38xx-gpio-alert";
-		irq-gpios = <&gpioc 7 GPIO_ACTIVE_LOW>;
-		nct38xx-dev = <&nct3807_C1>;
-		label = "NCT3807_ALERT_1";
-	};
+/* host interface */
+&espi0 {
+	status = "okay";
+	pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>;
+	pinctrl-names = "default";
 };
diff --git a/zephyr/projects/skyrim/guybrush.dts b/zephyr/projects/skyrim/guybrush.dts
deleted file mode 100644
index 6c5c72d061..0000000000
--- a/zephyr/projects/skyrim/guybrush.dts
+++ /dev/null
@@ -1,198 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/ {
-	aliases {
-		gpio-wp = &gpio_wp;
-		gpio-kbd-kso2 = &gpio_ec_kso_02_inv;
-	};
-
-	named-gpios {
-		/* Guybrush-specific GPIO customizations */
-		gpio_wp: ec_wp_l {
-			gpios = <&gpio5 0 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
-		};
-		gpio_ec_pwr_btn_odl: ec_pwr_btn_odl {
-			gpios = <&gpio0 1 GPIO_INPUT>;
-		};
-		gpio_slp_s3_s0i3_l: slp_s3_s0i3_l {
-			gpios = <&gpio7 4 GPIO_INPUT>;
-			enum-name = "GPIO_PCH_SLP_S0_L";
-		};
-		gpio_ec_pcore_int_odl: ec_pcore_int_odl {
-			gpios = <&gpiof 0 GPIO_INPUT_PULL_UP>;
-		};
-		gpio_pg_groupc_s0_od: pg_groupc_s0_od {
-			gpios = <&gpioa 3 GPIO_INPUT>;
-		};
-		gpio_pg_lpddr4x_s3_od: pg_lpddr4x_s3_od {
-			gpios = <&gpio9 5 GPIO_INPUT>;
-		};
-		ec_soc_pwr_good {
-			gpios = <&gpiod 3 GPIO_OUTPUT_LOW>;
-			enum-name = "GPIO_PCH_SYS_PWROK";
-		};
-		ec_entering_rw {
-			gpios = <&gpio6 6 GPIO_OUTPUT_LOW>;
-			enum-name = "GPIO_ENTERING_RW";
-		};
-		ec_clr_cmos {
-			gpios = <&gpioa 1 GPIO_OUTPUT_LOW>;
-		};
-		ec_mem_event {
-			gpios = <&gpioa 5 GPIO_OUTPUT_LOW>;
-		};
-		gpio_ec_soc_pwr_btn_l: ec_soc_pwr_btn_l {
-			gpios = <&gpio6 3 GPIO_OUTPUT_HIGH>;
-			enum-name = "GPIO_PCH_PWRBTN_L";
-		};
-		ec_soc_int_l {
-			gpios = <&gpio8 3 GPIO_OUTPUT_HIGH>;
-			enum-name = "GPIO_EC_INT_L";
-		};
-		soc_thermtrip_odl {
-			gpios = <&gpioe 5 GPIO_INPUT>;
-		};
-		gpio_usb_c0_c1_fault_odl: usb_c0_c1_fault_odl {
-			gpios = <&gpio7 3 GPIO_ODR_HIGH>;
-		};
-		3axis_int_l {
-			gpios = <&gpioa 2 GPIO_INPUT_PULL_DOWN>;
-		};
-		gpio_voldn_btn_odl: voldn_btn_odl {
-			gpios = <&gpioa 7 GPIO_INPUT_PULL_UP>;
-			enum-name = "GPIO_VOLUME_DOWN_L";
-		};
-		gpio_volup_btn_odl: volup_btn_odl {
-			gpios = <&gpio9 3 GPIO_INPUT_PULL_UP>;
-			enum-name = "GPIO_VOLUME_UP_L";
-		};
-		ec_ps2_clk {
-			gpios = <&gpio6 7 GPIO_INPUT_PULL_UP>;
-		};
-		ec_ps2_dat {
-			gpios = <&gpio7 0 GPIO_INPUT_PULL_UP>;
-		};
-		ec_ps2_rst {
-			gpios = <&gpio6 2 GPIO_INPUT_PULL_UP>;
-		};
-		ec_gpiob0 {
-			gpios = <&gpiob 0 GPIO_INPUT_PULL_UP>;
-		};
-		ec_gpio81 {
-			gpios = <&gpio8 1 GPIO_INPUT_PULL_UP>;
-		};
-		ec_psl_gpo {
-			gpios = <&gpiod 7 GPIO_INPUT_PULL_UP>;
-		};
-		ec_pwm7 {
-			gpios = <&gpio6 0 GPIO_INPUT_PULL_UP>;
-		};
-		gpio_accel_gyro_int_l: accel_gyro_int_l {
-			gpios = <&gpioa 0 GPIO_INPUT_PULL_UP>;
-		};
-	};
-
-	def-lvol-io-list {
-		compatible = "nuvoton,npcx-lvolctrl-def";
-
-		/* Low voltage on I2C6_1 */
-		lvol-io-pads = <&lvol_ioe4 &lvol_ioe3>;
-	};
-
-	named-adc-channels {
-		compatible = "named-adc-channels";
-
-		adc_temp_soc: temp-soc {
-			label = "SOC";
-			enum-name = "ADC_TEMP_SENSOR_SOC";
-			io-channels = <&adc0 0>;
-		};
-	};
-
-	named-temp-sensors {
-		soc-tmp112 {
-			compatible = "cros-ec,temp-sensor-tmp112",
-				     "cros-ec,temp-sensor";
-			label = "SOC";
-			enum-name = "TEMP_SENSOR_SOC";
-			tmp112-name = "TMP112_SOC";
-			port = <&i2c_sensor>;
-			i2c-addr-flags = "TMP112_I2C_ADDR_FLAGS0";
-			temp_host_high = <100>;
-			temp_host_halt = <105>;
-			temp_host_release_high = <80>;
-			temp_fan_off = <0>;
-			temp_fan_max = <70>;
-		};
-		amb-tmp112 {
-			compatible = "cros-ec,temp-sensor-tmp112",
-				     "cros-ec,temp-sensor";
-			label = "Ambient";
-			enum-name = "TEMP_SENSOR_AMB";
-			tmp112-name = "TMP112_AMB";
-			port = <&i2c_sensor>;
-			i2c-addr-flags = "TMP112_I2C_ADDR_FLAGS1";
-		};
-	};
-
-	gpio-interrupts {
-		compatible = "cros-ec,gpio-interrupts";
-
-		int_pg_lpddr4x_s3: pg_lpddr4x_s3 {
-			irq-pin = <&gpio_pg_lpddr4x_s3_od>;
-			flags = <GPIO_INT_EDGE_BOTH>;
-			handler = "baseboard_en_pwr_pcore_s0";
-		};
-		int_slp_s3_s0i3: slp_s3_s0i3 {
-			irq-pin = <&gpio_slp_s3_s0i3_l>;
-			flags = <GPIO_INT_EDGE_BOTH>;
-			handler = "power_signal_interrupt";
-		};
-		int_ec_pwr_btn: ec_pwr_btn {
-			irq-pin = <&gpio_ec_pwr_btn_odl>;
-			flags = <GPIO_INT_EDGE_BOTH>;
-			handler = "power_signal_interrupt";
-		};
-		int_ec_pcore: ec_pcore {
-			irq-pin = <&gpio_ec_pcore_int_odl>;
-			flags = <GPIO_INT_EDGE_BOTH>;
-			handler = "power_signal_interrupt";
-		};
-		int_pg_groupc_s0: pg_groupc_s0 {
-			irq-pin = <&gpio_pg_groupc_s0_od>;
-			flags = <GPIO_INT_EDGE_BOTH>;
-			handler = "baseboard_en_pwr_pcore_s0";
-		};
-		int_s0_pgood: s0_pgood {
-			irq-pin = <&gpio_s0_pgood>;
-			flags = <GPIO_INT_EDGE_BOTH>;
-			handler = "power_signal_interrupt";
-		};
-	};
-
-	/* Rotation matrices for motion sensors. */
-	motionsense-rotation-ref {
-		compatible = "cros-ec,motionsense-rotation-ref";
-		lid_rot_ref: lid-rotation-ref {
-			mat33 = <0 (-1) 0
-				 (-1) 0 0
-				 0 0 (-1)>;
-		};
-
-		base_rot_ref: base-rotation-ref {
-			mat33 = <(-1) 0 0
-				 0 1 0
-				 0 0 (-1)>;
-		};
-	};
-};
-
-/* host interface */
-&espi0 {
-	status = "okay";
-	pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>;
-	pinctrl-names = "default";
-};
diff --git a/zephyr/projects/skyrim/i2c.dts b/zephyr/projects/skyrim/i2c.dts
deleted file mode 100644
index 3ac516eb46..0000000000
--- a/zephyr/projects/skyrim/i2c.dts
+++ /dev/null
@@ -1,169 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/ {
-	aliases {
-		i2c-0 = &i2c0_0;
-		i2c-1 = &i2c1_0;
-		i2c-2 = &i2c2_0;
-		i2c-3 = &i2c3_0;
-		i2c-4 = &i2c4_1;
-		i2c-5 = &i2c5_0;
-		i2c-7 = &i2c7_0;
-	};
-
-	named-i2c-ports {
-		compatible = "named-i2c-ports";
-
-		i2c_tcpc0: tcpc0 {
-			i2c-port = <&i2c0_0>;
-			enum-name = "I2C_PORT_TCPC0";
-		};
-
-		i2c_tcpc1: tcpc1 {
-			i2c-port = <&i2c1_0>;
-			enum-name = "I2C_PORT_TCPC1";
-		};
-
-		battery {
-			i2c-port = <&i2c2_0>;
-			remote-port = <0>;
-			enum-name = "I2C_PORT_BATTERY";
-		};
-
-		usb-mux {
-			i2c-port = <&i2c3_0>;
-			enum-name = "I2C_PORT_USB_MUX";
-		};
-
-		i2c_charger: charger {
-			i2c-port = <&i2c4_1>;
-			enum-name = "I2C_PORT_CHARGER";
-		};
-
-		eeprom {
-			i2c-port = <&i2c5_0>;
-			enum-name = "I2C_PORT_EEPROM";
-		};
-
-		i2c_sensor: sensor {
-			i2c-port = <&i2c6_1>;
-			enum-name = "I2C_PORT_SENSOR";
-		};
-
-		i2c_soc_thermal: soc-thermal {
-			i2c-port = <&i2c7_0>;
-			enum-name = "I2C_PORT_THERMAL_AP";
-		};
-	};
-
-
-};
-
-&i2c0_0 {
-	status = "okay";
-	label = "I2C_TCPC0";
-	clock-frequency = <I2C_BITRATE_FAST>;
-	pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>;
-	pinctrl-names = "default";
-};
-
-&i2c_ctrl0 {
-	status = "okay";
-};
-
-&i2c1_0 {
-	status = "okay";
-	label = "I2C_TCPC1";
-	clock-frequency = <I2C_BITRATE_FAST>;
-	pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>;
-	pinctrl-names = "default";
-};
-
-&i2c_ctrl1 {
-	status = "okay";
-};
-
-&i2c2_0 {
-	status = "okay";
-	label = "I2C_BATTERY";
-	clock-frequency = <I2C_BITRATE_STANDARD>;
-	pinctrl-0 = <&i2c2_0_sda_scl_gp91_92>;
-	pinctrl-names = "default";
-};
-
-&i2c_ctrl2 {
-	status = "okay";
-};
-
-&i2c3_0 {
-	status = "okay";
-	label = "I2C_USB_MUX";
-	clock-frequency = <I2C_BITRATE_FAST>;
-	pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>;
-	pinctrl-names = "default";
-};
-
-&i2c_ctrl3 {
-	status = "okay";
-};
-
-&i2c4_1 {
-	status = "okay";
-	label = "I2C_CHARGER";
-	clock-frequency = <I2C_BITRATE_FAST>;
-	pinctrl-0 = <&i2c4_1_sda_scl_gpf2_f3>;
-	pinctrl-names = "default";
-};
-
-&i2c_ctrl4 {
-	status = "okay";
-};
-
-&i2c5_0 {
-	status = "okay";
-	label = "I2C_EEPROM";
-	clock-frequency = <I2C_BITRATE_FAST>;
-	pinctrl-0 = <&i2c5_0_sda_scl_gp33_36>;
-	pinctrl-names = "default";
-
-	cbi_eeprom: eeprom@50 {
-		compatible = "atmel,at24";
-		reg = <0x50>;
-		label = "EEPROM_CBI";
-		size = <2048>;
-		pagesize = <16>;
-		address-width = <8>;
-		timeout = <5>;
-	};
-};
-
-&i2c_ctrl5 {
-	status = "okay";
-};
-
-&i2c6_1 {
-	status = "okay";
-	label = "I2C_SENSOR";
-	clock-frequency = <I2C_BITRATE_FAST>;
-	pinctrl-0 = <&i2c6_1_sda_scl_gpe3_e4>;
-	pinctrl-names = "default";
-};
-
-&i2c_ctrl6 {
-	status = "okay";
-};
-
-&i2c7_0 {
-	status = "okay";
-	label = "I2C_THERMAL_AP";
-	clock-frequency = <I2C_BITRATE_FAST>;
-	pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>;
-	pinctrl-names = "default";
-};
-
-&i2c_ctrl7 {
-	status = "okay";
-};
diff --git a/zephyr/projects/skyrim/i2c_common.dtsi b/zephyr/projects/skyrim/i2c_common.dtsi
new file mode 100644
index 0000000000..8358b1c296
--- /dev/null
+++ b/zephyr/projects/skyrim/i2c_common.dtsi
@@ -0,0 +1,300 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+ #include <dt-bindings/usb_pd_tcpm.h>
+
+/ {
+	aliases {
+		i2c-0 = &i2c0_0;
+		i2c-1 = &i2c1_0;
+		i2c-2 = &i2c2_0;
+		i2c-3 = &i2c3_0;
+		i2c-4 = &i2c4_1;
+		i2c-5 = &i2c5_0;
+		i2c-7 = &i2c7_0;
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		i2c_tcpc0: tcpc0 {
+			i2c-port = <&i2c0_0>;
+			enum-names = "I2C_PORT_TCPC0";
+		};
+
+		i2c_tcpc1: tcpc1 {
+			i2c-port = <&i2c1_0>;
+			enum-names = "I2C_PORT_TCPC1";
+		};
+
+		battery {
+			i2c-port = <&i2c2_0>;
+			remote-port = <0>;
+			enum-names = "I2C_PORT_BATTERY";
+		};
+
+		usb-mux {
+			i2c-port = <&i2c3_0>;
+			enum-names = "I2C_PORT_USB_MUX";
+		};
+
+		i2c_charger: charger {
+			i2c-port = <&i2c4_1>;
+			enum-names = "I2C_PORT_CHARGER";
+		};
+
+		eeprom {
+			i2c-port = <&i2c5_0>;
+			enum-names = "I2C_PORT_EEPROM";
+		};
+
+		i2c_sensor: sensor {
+			i2c-port = <&i2c6_1>;
+			enum-names = "I2C_PORT_SENSOR";
+		};
+
+		i2c_soc_thermal: soc-thermal {
+			i2c-port = <&i2c7_0>;
+			enum-names = "I2C_PORT_THERMAL_AP";
+		};
+	};
+
+
+};
+
+&i2c0_0 {
+	status = "okay";
+	label = "I2C_TCPC0";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>;
+	pinctrl-names = "default";
+
+	bc12_port0: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+		irq = <&int_usb_c0_bc12>;
+	};
+
+	tcpc_port0: nct38xx@70 {
+		compatible = "nuvoton,nct38xx";
+		reg = <0x70>;
+		gpio-dev = <&nct3807_C0>;
+		tcpc-flags = <(TCPC_FLAGS_TCPCI_REV2_0)>;
+	};
+
+	nct3807_C0:nct3807_C0@70 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nuvoton,nct38xx-gpio";
+		reg = <0x70>;
+		label = "NCT3807_C0";
+
+		ioex_c0_port0:gpio@0 {
+			compatible = "nuvoton,nct38xx-gpio-port";
+			reg = <0x0>;
+			label = "NCT3807_C0_GPIO0";
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <8>;
+			pin_mask = <0xff>;
+			pinmux_mask = <0xf7>;
+		};
+		ioex_c0_port1:gpio@1 {
+			compatible = "nuvoton,nct38xx-gpio-port";
+			reg = <0x1>;
+			label = "NCT3807_C0_GPIO1";
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <8>;
+			pin_mask = <0xff>;
+		};
+	};
+
+	nct3808_alert_0 {
+		compatible = "nuvoton,nct38xx-gpio-alert";
+		irq-gpios = <&gpioe 0 GPIO_ACTIVE_LOW>;
+		nct38xx-dev = <&nct3807_C0>;
+		label = "NCT3807_ALERT_0";
+	};
+};
+
+&i2c_ctrl0 {
+	status = "okay";
+};
+
+&i2c1_0 {
+	status = "okay";
+	label = "I2C_TCPC1";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>;
+	pinctrl-names = "default";
+
+	bc12_port1: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+		irq = <&int_usb_c1_bc12>;
+	};
+
+	tcpc_port1: nct38xx@70 {
+		compatible = "nuvoton,nct38xx";
+		reg = <0x70>;
+		gpio-dev = <&nct3807_C1>;
+		tcpc-flags = <(TCPC_FLAGS_TCPCI_REV2_0)>;
+	};
+
+	nct3807_C1:nct3807_C1@70 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nuvoton,nct38xx-gpio";
+		reg = <0x70>;
+		label = "NCT3807_C1";
+
+		ioex_c1_port0:gpio@0 {
+			compatible = "nuvoton,nct38xx-gpio-port";
+			reg = <0x0>;
+			label = "NCT3807_C1_GPIO0";
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <8>;
+			pin_mask = <0xff>;
+			pinmux_mask = <0xf7>;
+		};
+		ioex_c1_port1:gpio@1 {
+			compatible = "nuvoton,nct38xx-gpio-port";
+			reg = <0x1>;
+			label = "NCT3807_C1_GPIO1";
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <8>;
+			pin_mask = <0xff>;
+		};
+	};
+
+	nct3808_alert_1 {
+		compatible = "nuvoton,nct38xx-gpio-alert";
+		irq-gpios = <&gpioc 7 GPIO_ACTIVE_LOW>;
+		nct38xx-dev = <&nct3807_C1>;
+		label = "NCT3807_ALERT_1";
+	};
+};
+
+&i2c_ctrl1 {
+	status = "okay";
+};
+
+&i2c2_0 {
+	status = "okay";
+	label = "I2C_BATTERY";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	pinctrl-0 = <&i2c2_0_sda_scl_gp91_92>;
+	pinctrl-names = "default";
+};
+
+&i2c_ctrl2 {
+	status = "okay";
+};
+
+&i2c3_0 {
+	status = "okay";
+	label = "I2C_USB_MUX";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>;
+	pinctrl-names = "default";
+
+	amd_fp6_port0: amd_fp6@5c {
+		compatible = "amd,usbc-mux-amd-fp6";
+		status = "okay";
+		reg = <0x5c>;
+	};
+	amd_fp6_port1: amd_fp6@52 {
+		compatible = "amd,usbc-mux-amd-fp6";
+		status = "okay";
+		reg = <0x52>;
+	};
+};
+
+&i2c_ctrl3 {
+	status = "okay";
+};
+
+&i2c4_1 {
+	status = "okay";
+	label = "I2C_CHARGER";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c4_1_sda_scl_gpf2_f3>;
+	pinctrl-names = "default";
+
+	charger: isl9241@9 {
+		compatible = "intersil,isl9241";
+		status = "okay";
+		reg = <0x9>;
+	};
+};
+
+&i2c_ctrl4 {
+	status = "okay";
+};
+
+&i2c5_0 {
+	status = "okay";
+	label = "I2C_EEPROM";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c5_0_sda_scl_gp33_36>;
+	pinctrl-names = "default";
+
+	cbi_eeprom: eeprom@50 {
+		compatible = "atmel,at24";
+		reg = <0x50>;
+		size = <2048>;
+		pagesize = <16>;
+		address-width = <8>;
+		timeout = <5>;
+	};
+};
+
+&i2c_ctrl5 {
+	status = "okay";
+};
+
+&i2c6_1 {
+	status = "okay";
+	label = "I2C_SENSOR";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c6_1_sda_scl_gpe3_e4>;
+	pinctrl-names = "default";
+
+	soc_pct2075: soc-pct2075@48 {
+		compatible = "nxp,pct2075";
+		reg = <0x48>;
+	};
+
+	amb_pct2075: amb-pct2075@4f {
+		compatible = "nxp,pct2075";
+		reg = <0x4f>;
+	};
+};
+
+&i2c_ctrl6 {
+	status = "okay";
+};
+
+&i2c7_0 {
+	status = "okay";
+	label = "I2C_THERMAL_AP";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>;
+	pinctrl-names = "default";
+
+	temp_cpu: cpu@4c {
+		compatible = "amd,sb-tsi";
+		reg = <0x4c>;
+	};
+};
+
+&i2c_ctrl7 {
+	status = "okay";
+};
diff --git a/zephyr/projects/skyrim/include_guybrush/gpio_map.h b/zephyr/projects/skyrim/include_guybrush/gpio_map.h
deleted file mode 100644
index 22d0eb602e..0000000000
--- a/zephyr/projects/skyrim/include_guybrush/gpio_map.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __ZEPHYR_GPIO_MAP_H
-#define __ZEPHYR_GPIO_MAP_H
-
-#include <zephyr/devicetree.h>
-#include <gpio_signal.h>
-
-/* Power input signals */
-enum power_signal {
-	X86_SLP_S0_N, /* SOC  -> SLP_S3_S0I3_L */
-	X86_SLP_S3_N, /* SOC  -> SLP_S3_L */
-	X86_SLP_S5_N, /* SOC  -> SLP_S5_L */
-
-	X86_S0_PGOOD, /* PMIC -> S0_PWROK_OD */
-	X86_S5_PGOOD, /* PMIC -> S5_PWROK */
-
-	/* Number of X86 signals */
-	POWER_SIGNAL_COUNT,
-};
-
-#endif /* __ZEPHYR_GPIO_MAP_H */
diff --git a/zephyr/projects/skyrim/interrupts.dts b/zephyr/projects/skyrim/interrupts.dts
index 59507f8081..0749b72078 100644
--- a/zephyr/projects/skyrim/interrupts.dts
+++ b/zephyr/projects/skyrim/interrupts.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -42,6 +42,26 @@
 			flags = <GPIO_INT_EDGE_BOTH>;
 			handler = "baseboard_set_en_pwr_pcore";
 		};
+		int_pg_lpddr_s3: pg_lpddr_s3 {
+			irq-pin = <&gpio_pg_lpddr5_s3_od>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "baseboard_set_en_pwr_pcore";
+		};
+		int_pg_lpddr_s0: pg_lpddr_s0 {
+			irq-pin = <&gpio_pg_lpddr5_s0_od>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "baseboard_set_soc_pwr_pgood";
+		};
+		int_s0_pgood: s0_pgood {
+			irq-pin = <&gpio_s0_pgood>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "baseboard_s0_pgood";
+		};
+		int_soc_thermtrip: soc_thermtrip {
+			irq-pin = <&gpio_soc_thermtrip_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "baseboard_soc_thermtrip";
+		};
 		int_volume_up: volume_up {
 			irq-pin = <&gpio_volup_btn_odl>;
 			flags = <GPIO_INT_EDGE_BOTH>;
@@ -52,6 +72,26 @@
 			flags = <GPIO_INT_EDGE_BOTH>;
 			handler = "button_interrupt";
 		};
+		int_usb_a0_fault: a0_fault {
+			irq-pin = <&ioex_usb_a0_fault_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "usb_fault_interrupt";
+		};
+		int_usb_a1_fault: a1_fault {
+			irq-pin = <&ioex_usb_a1_fault_db_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "usb_fault_interrupt";
+		};
+		int_usb_c0_sbu_fault: c0_sbu_fault {
+			irq-pin = <&ioex_usb_c0_sbu_fault_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "sbu_fault_interrupt";
+		};
+		int_usb_c1_sbu_fault: c1_sbu_fault {
+			irq-pin = <&ioex_usb_c1_sbu_fault_odl>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "sbu_fault_interrupt";
+		};
 		int_usb_c0_tcpc: usb_c0_tcpc {
 			irq-pin = <&gpio_usb_c0_tcpc_int_odl>;
 			flags = <GPIO_INT_EDGE_FALLING>;
@@ -82,6 +122,16 @@
 			flags = <GPIO_INT_EDGE_FALLING>;
 			handler = "bc12_interrupt";
 		};
+		int_usb_hub_fault: hub_fault {
+			irq-pin = <&gpio_usb_hub_fault_q_odl>;
+			flags = <GPIO_INT_EDGE_BOTH>;
+			handler = "usb_fault_interrupt";
+		};
+		int_usb_pd_soc: usb_pd_soc {
+			irq-pin = <&gpio_ec_i2c_usbc_pd_int>;
+			flags = <GPIO_INT_EDGE_FALLING>;
+			handler = "usb_pd_soc_interrupt";
+		};
 		int_accel_gyro: accel_gyro {
 			irq-pin = <&gpio_accel_gyro_int_l>;
 			flags = <GPIO_INT_EDGE_FALLING>;
diff --git a/zephyr/projects/skyrim/keyboard.dts b/zephyr/projects/skyrim/keyboard.dts
index 216ea97045..df334ba54c 100644
--- a/zephyr/projects/skyrim/keyboard.dts
+++ b/zephyr/projects/skyrim/keyboard.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,7 +7,6 @@
 	kblight {
 		compatible = "cros-ec,kblight-pwm";
 		pwms = <&pwm1 0 PWM_HZ(100) PWM_POLARITY_NORMAL>;
-		frequency = <100>;
 	};
 };
 
diff --git a/zephyr/projects/skyrim/led_pins_morthal.dts b/zephyr/projects/skyrim/led_pins_morthal.dts
new file mode 100644
index 0000000000..33a66c0756
--- /dev/null
+++ b/zephyr/projects/skyrim/led_pins_morthal.dts
@@ -0,0 +1,63 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	pwm_pins {
+		compatible = "cros-ec,pwm-pin-config";
+
+		pwm_y: pwm_y {
+			#led-pin-cells = <1>;
+			pwms = <&pwm2 0 PWM_HZ(100) PWM_POLARITY_INVERTED>;
+		};
+
+		pwm_w: pwm_w {
+			#led-pin-cells = <1>;
+			pwms = <&pwm3 0 PWM_HZ(100) PWM_POLARITY_INVERTED>;
+		};
+	};
+
+	pwm-led-pins {
+		compatible = "cros-ec,pwm-led-pins";
+
+		color_off: color-off {
+			led-color = "LED_OFF";
+			led-id = "EC_LED_ID_BATTERY_LED";
+			led-pins = <&pwm_y 0>,
+				   <&pwm_w 0>;
+		};
+
+		color_amber: color-amber {
+			led-color = "LED_AMBER";
+			led-id = "EC_LED_ID_BATTERY_LED";
+			br-color = "EC_LED_COLOR_AMBER";
+			led-pins = <&pwm_y 100>,
+				   <&pwm_w 0>;
+		};
+
+		color_white: color-white {
+			led-color = "LED_WHITE";
+			led-id = "EC_LED_ID_BATTERY_LED";
+			br-color = "EC_LED_COLOR_BLUE";
+			led-pins = <&pwm_y 0>,
+				   <&pwm_w 100>;
+		};
+	};
+};
+
+/* Amber "battery charging" LED */
+&pwm2 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm2_gpc4>;
+	pinctrl-names = "default";
+};
+
+/* White "battery full" LED */
+&pwm3 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm3_gp80>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/projects/skyrim/led_pins_skyrim.dts b/zephyr/projects/skyrim/led_pins_skyrim.dts
index 3ff966bcf6..33a66c0756 100644
--- a/zephyr/projects/skyrim/led_pins_skyrim.dts
+++ b/zephyr/projects/skyrim/led_pins_skyrim.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,7 +20,6 @@
 
 	pwm-led-pins {
 		compatible = "cros-ec,pwm-led-pins";
-		pwm-frequency = <100>;
 
 		color_off: color-off {
 			led-color = "LED_OFF";
diff --git a/zephyr/projects/skyrim/led_pins_winterhold.dts b/zephyr/projects/skyrim/led_pins_winterhold.dts
new file mode 100644
index 0000000000..33a66c0756
--- /dev/null
+++ b/zephyr/projects/skyrim/led_pins_winterhold.dts
@@ -0,0 +1,63 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	pwm_pins {
+		compatible = "cros-ec,pwm-pin-config";
+
+		pwm_y: pwm_y {
+			#led-pin-cells = <1>;
+			pwms = <&pwm2 0 PWM_HZ(100) PWM_POLARITY_INVERTED>;
+		};
+
+		pwm_w: pwm_w {
+			#led-pin-cells = <1>;
+			pwms = <&pwm3 0 PWM_HZ(100) PWM_POLARITY_INVERTED>;
+		};
+	};
+
+	pwm-led-pins {
+		compatible = "cros-ec,pwm-led-pins";
+
+		color_off: color-off {
+			led-color = "LED_OFF";
+			led-id = "EC_LED_ID_BATTERY_LED";
+			led-pins = <&pwm_y 0>,
+				   <&pwm_w 0>;
+		};
+
+		color_amber: color-amber {
+			led-color = "LED_AMBER";
+			led-id = "EC_LED_ID_BATTERY_LED";
+			br-color = "EC_LED_COLOR_AMBER";
+			led-pins = <&pwm_y 100>,
+				   <&pwm_w 0>;
+		};
+
+		color_white: color-white {
+			led-color = "LED_WHITE";
+			led-id = "EC_LED_ID_BATTERY_LED";
+			br-color = "EC_LED_COLOR_BLUE";
+			led-pins = <&pwm_y 0>,
+				   <&pwm_w 100>;
+		};
+	};
+};
+
+/* Amber "battery charging" LED */
+&pwm2 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm2_gpc4>;
+	pinctrl-names = "default";
+};
+
+/* White "battery full" LED */
+&pwm3 {
+	status = "okay";
+	clock-bus = "NPCX_CLOCK_BUS_LFCLK";
+	pinctrl-0 = <&pwm3_gp80>;
+	pinctrl-names = "default";
+};
diff --git a/zephyr/projects/skyrim/led_policy_morthal.dts b/zephyr/projects/skyrim/led_policy_morthal.dts
new file mode 100644
index 0000000000..a075c6b0d2
--- /dev/null
+++ b/zephyr/projects/skyrim/led_policy_morthal.dts
@@ -0,0 +1,103 @@
+#include <dt-bindings/battery.h>
+
+/ {
+	led-colors {
+		compatible = "cros-ec,led-policy";
+
+		power-state-charge {
+			charge-state = "PWR_STATE_CHARGE";
+
+			color-0 {
+				led-color = <&color_amber>;
+			};
+		};
+
+		power-state-discharge-s0 {
+			charge-state = "PWR_STATE_DISCHARGE";
+			chipset-state = "POWER_S0";
+			/* Battery percent range (> Low, <= Full) */
+			batt-lvl = <(BATTERY_LEVEL_LOW + 1) BATTERY_LEVEL_FULL>;
+
+			color-0 {
+				led-color = <&color_white>;
+			};
+		};
+
+		power-state-discharge-s0-batt-low {
+			charge-state = "PWR_STATE_DISCHARGE";
+			chipset-state = "POWER_S0";
+			/* Battery percent range (>= Empty, <= Low) */
+			batt-lvl = <BATTERY_LEVEL_EMPTY BATTERY_LEVEL_LOW>;
+
+			/* White 2 sec, off 1 sec */
+			color-0 {
+				led-color = <&color_white>;
+				period-ms = <2000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <1000>;
+			};
+		};
+
+		power-state-discharge-s3 {
+			charge-state = "PWR_STATE_DISCHARGE";
+			chipset-state = "POWER_S3";
+
+			/* White 1 sec, off 1 sec */
+			color-0 {
+				led-color = <&color_white>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <1000>;
+			};
+		};
+
+		power-state-discharge-s5 {
+			charge-state = "PWR_STATE_DISCHARGE";
+			chipset-state = "POWER_S5";
+
+			color-0 {
+				led-color = <&color_off>;
+			};
+		};
+
+		power-state-error {
+			charge-state = "PWR_STATE_ERROR";
+
+			/* Amber 1 sec, off 1 sec */
+			color-0 {
+				led-color = <&color_amber>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <1000>;
+			};
+		};
+
+		power-state-near-full {
+			charge-state = "PWR_STATE_CHARGE_NEAR_FULL";
+
+			color-0 {
+				led-color = <&color_white>;
+			};
+		};
+
+		power-state-forced-idle {
+			charge-state = "PWR_STATE_FORCED_IDLE";
+
+			/* Amber 2 sec, White 2 sec */
+			color-0 {
+				led-color = <&color_amber>;
+				period-ms = <2000>;
+			};
+			color-1 {
+				led-color = <&color_white>;
+				period-ms = <2000>;
+			};
+		};
+	};
+};
diff --git a/zephyr/projects/skyrim/led_policy_skyrim.dts b/zephyr/projects/skyrim/led_policy_skyrim.dts
index da3d817925..a075c6b0d2 100644
--- a/zephyr/projects/skyrim/led_policy_skyrim.dts
+++ b/zephyr/projects/skyrim/led_policy_skyrim.dts
@@ -2,7 +2,7 @@
 
 / {
 	led-colors {
-		compatible = "cros-ec,led-colors";
+		compatible = "cros-ec,led-policy";
 
 		power-state-charge {
 			charge-state = "PWR_STATE_CHARGE";
@@ -86,9 +86,8 @@
 			};
 		};
 
-		power-state-idle-forced {
-			charge-state = "PWR_STATE_IDLE";
-			extra-flag = "LED_CHFLAG_FORCE_IDLE";
+		power-state-forced-idle {
+			charge-state = "PWR_STATE_FORCED_IDLE";
 
 			/* Amber 2 sec, White 2 sec */
 			color-0 {
diff --git a/zephyr/projects/skyrim/led_policy_winterhold.dts b/zephyr/projects/skyrim/led_policy_winterhold.dts
new file mode 100644
index 0000000000..f1f8aa31ed
--- /dev/null
+++ b/zephyr/projects/skyrim/led_policy_winterhold.dts
@@ -0,0 +1,103 @@
+#include <dt-bindings/battery.h>
+
+/ {
+	led-colors {
+		compatible = "cros-ec,led-policy";
+
+		power-state-charge {
+			charge-state = "PWR_STATE_CHARGE";
+			color-0 {
+				led-color = <&color_white>;
+			};
+		};
+
+		power-state-discharge-s0 {
+			charge-state = "PWR_STATE_DISCHARGE";
+			chipset-state = "POWER_S0";
+			/* Battery percent range (> Low, <= Full) */
+			batt-lvl = <(BATTERY_LEVEL_LOW + 1) BATTERY_LEVEL_FULL>;
+
+			color-0 {
+				led-color = <&color_off>;
+			};
+		};
+
+		power-state-discharge-s0-batt-low {
+			charge-state = "PWR_STATE_DISCHARGE";
+			chipset-state = "POWER_S0";
+			/* Battery percent range (>= Empty, <= Low) */
+			batt-lvl = <BATTERY_LEVEL_EMPTY BATTERY_LEVEL_LOW>;
+
+			color-0 {
+				led-color = <&color_amber>;
+			};
+		};
+
+		power-state-discharge-s3 {
+			charge-state = "PWR_STATE_DISCHARGE";
+			chipset-state = "POWER_S3";
+			/* Battery percent range (> Low, <= Full) */
+			batt-lvl = <(BATTERY_LEVEL_LOW + 1) BATTERY_LEVEL_FULL>;
+
+			color-0 {
+				led-color = <&color_off>;
+			};
+		};
+
+		power-state-discharge-s3-batt-low {
+			charge-state = "PWR_STATE_DISCHARGE";
+			chipset-state = "POWER_S3";
+			/* Battery percent range (>= Empty, <= Low) */
+			batt-lvl = <BATTERY_LEVEL_EMPTY BATTERY_LEVEL_LOW>;
+
+			color-0 {
+				led-color = <&color_amber>;
+			};
+		};
+
+		power-state-discharge-s5 {
+			charge-state = "PWR_STATE_DISCHARGE";
+			chipset-state = "POWER_S5";
+
+			color-0 {
+				led-color = <&color_off>;
+			};
+		};
+
+		power-state-error {
+			charge-state = "PWR_STATE_ERROR";
+
+			/* Amber 1 sec, off 1 sec */
+			color-0 {
+				led-color = <&color_amber>;
+				period-ms = <1000>;
+			};
+			color-1 {
+				led-color = <&color_off>;
+				period-ms = <1000>;
+			};
+		};
+
+		power-state-near-full {
+			charge-state = "PWR_STATE_CHARGE_NEAR_FULL";
+
+			color-0 {
+				led-color = <&color_off>;
+			};
+		};
+
+		power-state-forced-idle {
+			charge-state = "PWR_STATE_FORCED_IDLE";
+
+			/* Amber 2 sec, White 2 sec */
+			color-0 {
+				led-color = <&color_amber>;
+				period-ms = <2000>;
+			};
+			color-1 {
+				led-color = <&color_white>;
+				period-ms = <2000>;
+			};
+		};
+	};
+};
diff --git a/zephyr/projects/skyrim/morthal.dts b/zephyr/projects/skyrim/morthal.dts
new file mode 100644
index 0000000000..bb1e45aa87
--- /dev/null
+++ b/zephyr/projects/skyrim/morthal.dts
@@ -0,0 +1,175 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/usbc_mux.h>
+
+#include "i2c_common.dtsi"
+
+/ {
+	named-gpios {
+		/* Morthal-specific GPIO customizations */
+	};
+
+	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
+		soc-pct2075 {
+			temp_host_high = <100>;
+			temp_host_halt = <105>;
+			temp_host_release_high = <80>;
+			temp_host_release_halt = <80>;
+			temp_fan_off = <0>;
+			temp_fan_max = <70>;
+			power-good-pin = <&gpio_pg_pwr_s5>;
+			sensor = <&soc_pct2075>;
+		};
+		amb-pct2075 {
+			power-good-pin = <&gpio_pg_pwr_s5>;
+			sensor = <&amb_pct2075>;
+		};
+	};
+
+	/*
+	 * Note this is expected to vary per-board, so we keep it in the board
+	 * dts files.
+	 */
+	morthal-fw-config {
+		compatible = "cros-ec,cbi-fw-config";
+
+		form-factor {
+			enum-name = "FW_FORM_FACTOR";
+			start = <0>;
+			size = <1>;
+
+			ff-clamshell {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FF_CLAMSHELL";
+				value = <0>;
+			};
+			ff-convertible {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FF_CONVERTIBLE";
+				value = <1>;
+				default;
+			};
+		};
+		io-db {
+			enum-name = "FW_IO_DB";
+			start = <6>;
+			size = <2>;
+
+			io-db-ps8811-ps8818 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_IO_DB_PS8811_PS8818";
+				value = <0>;
+			};
+			io-db-none-anx7483 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_IO_DB_NONE_ANX7483";
+				value = <1>;
+				default;
+			};
+		};
+
+		/*
+		 * FW_CONFIG field to enable fan or not.
+		 */
+		fan {
+			enum-name = "FW_FAN";
+			start = <10>;
+			size = <1>;
+
+			no-fan {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FAN_NOT_PRESENT";
+				value = <0>;
+			};
+			fan-present {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FAN_PRESENT";
+				value = <1>;
+				/*
+				 * Set as default so that unprovisioned
+				 * configs will run the fan regardless.
+				 */
+				default;
+			};
+		};
+	};
+
+	/* Rotation matrices for motion sensors. */
+	motionsense-rotation-ref {
+		compatible = "cros-ec,motionsense-rotation-ref";
+		lid_rot_ref: lid-rotation-ref {
+			mat33 = <0 (-1) 0
+				 1 0 0
+				 0 0 1>;
+		};
+
+		lid_rot_ref1: lid-rotation-ref1 {
+			mat33 = <0 1 0
+				 (-1) 0 0
+				 0 0 1>;
+		};
+
+		base_rot_ref: base-rotation-ref {
+			mat33 = <0 1 0
+				 (-1) 0 0
+				 0 0 1>;
+		};
+	};
+
+	ppc_port0: aoz1380 {
+		compatible = "aoz,aoz1380";
+		status = "okay";
+	};
+};
+
+&i2c0_0 {
+	anx7483_port0: anx7483@3e {
+		compatible = "analogix,anx7483";
+		reg = <0x3e>;
+		board-set = "board_anx7483_c0_mux_set";
+	};
+};
+
+&i2c1_0 {
+	anx7483_port1: anx7483@3e {
+		compatible = "analogix,anx7483";
+		reg = <0x3e>;
+		board-set = "board_anx7483_c1_mux_set";
+	};
+	ppc_port1: nx20p348x@71 {
+		compatible = "nxp,nx20p348x";
+		status = "okay";
+		reg = <0x71>;
+	};
+	ps8818_port1: ps8818@28 {
+		compatible = "parade,ps8818";
+		reg = <0x28>;
+		flags = <(USB_MUX_FLAG_RESETS_IN_G3)>;
+		board-set = "board_c1_ps8818_mux_set";
+	};
+};
+
+&usbc_port0 {
+	ppc = <&ppc_port0>;
+	usb-mux-chain-0 {
+		compatible = "cros-ec,usb-mux-chain";
+		usb-muxes = <&amd_fp6_port0 &anx7483_port0>;
+	};
+};
+
+&usbc_port1 {
+	ppc = <&ppc_port1>;
+	usb-mux-chain-1-anx {
+		compatible = "cros-ec,usb-mux-chain";
+		usb-muxes = <&amd_fp6_port1 &anx7483_port1>;
+	};
+	usb_mux_chain_ps8818_port1: usb-mux-chain-1-ps {
+		compatible = "cros-ec,usb-mux-chain";
+		usb-muxes = <&amd_fp6_port1 &ps8818_port1>;
+		alternative-chain;
+	};
+};
diff --git a/zephyr/projects/skyrim/motionsense.dts b/zephyr/projects/skyrim/motionsense.dts
index 642a1cddf8..f943bea4c8 100644
--- a/zephyr/projects/skyrim/motionsense.dts
+++ b/zephyr/projects/skyrim/motionsense.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,11 +26,9 @@
 	motionsense-mutex {
 		compatible = "cros-ec,motionsense-mutex";
 		lid_mutex: lid-mutex {
-			label = "LID_MUTEX";
 		};
 
 		mutex_bmi3xx: bmi3xx-mutex {
-			label = "BMI3XX_MUTEX";
 		};
 	};
 
@@ -57,7 +55,7 @@
 
 	/*
 	 * List of motion sensors that creates motion_sensors array.
-	 * The label "lid_accel" and "base_accel" are used to indicate
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
 	 * motion sensor IDs for lid angle calculation.
 	 */
 	motionsense-sensor {
@@ -65,7 +63,6 @@
 			compatible = "cros-ec,bma4xx";
 			status = "okay";
 
-			label = "Lid Accel";
 			active-mask = "SENSOR_ACTIVE_S0_S3";
 			location = "MOTIONSENSE_LOC_LID";
 			mutex = <&lid_mutex>;
@@ -77,12 +74,10 @@
 				compatible =
 					"cros-ec,motionsense-sensor-config";
 				ec-s0 {
-					label = "SENSOR_CONFIG_EC_S0";
 					odr = <(12500 | ROUND_UP_FLAG)>;
 					ec-rate = <100>;
 				};
 				ec-s3 {
-					label = "SENSOR_CONFIG_EC_S3";
 					odr = <(12500 | ROUND_UP_FLAG)>;
 				};
 			};
@@ -92,7 +87,6 @@
 			compatible = "cros-ec,bmi3xx-accel";
 			status = "okay";
 
-			label = "Base Accel";
 			active-mask = "SENSOR_ACTIVE_S0_S3";
 			location = "MOTIONSENSE_LOC_BASE";
 			mutex = <&mutex_bmi3xx>;
@@ -104,12 +98,10 @@
 				compatible =
 					"cros-ec,motionsense-sensor-config";
 				ec-s0 {
-					label = "SENSOR_CONFIG_EC_S0";
 					odr = <(12500 | ROUND_UP_FLAG)>;
 					ec-rate = <100>;
 				};
 				ec-s3 {
-					label = "SENSOR_CONFIG_EC_S3";
 					odr = <(12500 | ROUND_UP_FLAG)>;
 				};
 			};
@@ -119,7 +111,6 @@
 			compatible = "cros-ec,bmi3xx-gyro";
 			status = "okay";
 
-			label = "Base Gyro";
 			active-mask = "SENSOR_ACTIVE_S0_S3";
 			location = "MOTIONSENSE_LOC_BASE";
 			mutex = <&mutex_bmi3xx>;
diff --git a/zephyr/projects/skyrim/power_signals_guybrush.c b/zephyr/projects/skyrim/power_signals_guybrush.c
deleted file mode 100644
index 11110886f2..0000000000
--- a/zephyr/projects/skyrim/power_signals_guybrush.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <zephyr/drivers/gpio.h>
-
-#include "chipset.h"
-#include "config.h"
-#include "gpio_signal.h"
-#include "gpio/gpio_int.h"
-#include "hooks.h"
-#include "power.h"
-#include "timer.h"
-
-/* Wake Sources */
-/* TODO: b/218904113: Convert to using Zephyr GPIOs */
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_LID_OPEN,
-	GPIO_AC_PRESENT,
-	GPIO_POWER_BUTTON_L,
-};
-const int hibernate_wake_pins_used =  ARRAY_SIZE(hibernate_wake_pins);
-
-/* Power Signal Input List */
-/* TODO: b/218904113: Convert to using Zephyr GPIOs */
-const struct power_signal_info power_signal_list[] = {
-	[X86_SLP_S0_N] = {
-		.gpio = GPIO_PCH_SLP_S0_L,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "SLP_S0_DEASSERTED",
-	},
-	[X86_SLP_S3_N] = {
-		.gpio = GPIO_PCH_SLP_S3_L,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "SLP_S3_DEASSERTED",
-	},
-	[X86_SLP_S5_N] = {
-		.gpio = GPIO_PCH_SLP_S5_L,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "SLP_S5_DEASSERTED",
-	},
-	[X86_S0_PGOOD] = {
-		.gpio = GPIO_S0_PGOOD,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "S0_PGOOD",
-	},
-	[X86_S5_PGOOD] = {
-		.gpio = GPIO_S5_PGOOD,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "S5_PGOOD",
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-static void baseboard_interrupt_init(void)
-{
-	/* Enable Power Group interrupts. */
-	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pg_groupc_s0));
-	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pg_lpddr4x_s3));
-}
-DECLARE_HOOK(HOOK_INIT, baseboard_interrupt_init, HOOK_PRIO_POST_I2C);
-
-/**
- * b/175324615: On G3->S5, wait for RSMRST_L to be deasserted before asserting
- * PCH_PWRBTN_L.
- */
-void board_pwrbtn_to_pch(int level)
-{
-	timestamp_t start;
-	const uint32_t timeout_rsmrst_rise_us = 30 * MSEC;
-
-	/* Add delay for G3 exit if asserting PWRBTN_L and RSMRST_L is low. */
-	if (!level &&
-	    !gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_soc_rsmrst_l))) {
-		start = get_time();
-		do {
-			usleep(200);
-			if (gpio_pin_get_dt(
-				GPIO_DT_FROM_NODELABEL(gpio_ec_soc_rsmrst_l)))
-				break;
-		} while (time_since32(start) < timeout_rsmrst_rise_us);
-
-		if (!gpio_pin_get_dt(
-		    GPIO_DT_FROM_NODELABEL(gpio_ec_soc_rsmrst_l)))
-			ccprints("Error pwrbtn: RSMRST_L still low");
-
-		msleep(16);
-	}
-	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_soc_pwr_btn_l), level);
-}
-
-void baseboard_en_pwr_pcore_s0(enum gpio_signal signal)
-{
-
-	/* EC must AND signals PG_LPDDR4X_S3_OD and PG_GROUPC_S0_OD */
-	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pwr_pcore_s0_r),
-	    gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_pg_lpddr4x_s3_od)) &&
-	    gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_pg_groupc_s0_od)));
-}
-
-void baseboard_en_pwr_s0(enum gpio_signal signal)
-{
-
-	/* EC must AND signals SLP_S3_L and PG_PWR_S5 */
-	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pwr_s0_r),
-		       gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_slp_s3_l)) &&
-		       gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_pg_pwr_s5)));
-
-	/* Now chain off to the normal power signal interrupt handler. */
-	power_signal_interrupt(signal);
-}
-
-void baseboard_s5_pgood(enum gpio_signal signal)
-{
-	baseboard_en_pwr_s0(signal);
-}
-
-void baseboard_set_en_pwr_s3(enum gpio_signal signal)
-{
-	/* EC has no EN_PWR_S3 on this board */
-
-	/* Chain off the normal power signal interrupt handler */
-	power_signal_interrupt(signal);
-}
diff --git a/zephyr/projects/skyrim/prj.conf b/zephyr/projects/skyrim/prj.conf
index 47e9c1d096..135b5713e4 100644
--- a/zephyr/projects/skyrim/prj.conf
+++ b/zephyr/projects/skyrim/prj.conf
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -28,7 +28,7 @@ CONFIG_PLATFORM_EC_PORT80=y
 CONFIG_PLATFORM_EC_POWER_BUTTON=y
 
 # ADC
-CONFIG_PLATFORM_EC_ADC=y
+CONFIG_ADC=y
 
 # I2C
 CONFIG_I2C=y
@@ -41,6 +41,8 @@ CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=y
 CONFIG_PLATFORM_EC_CBI_EEPROM=y
 
 # Temperature Sensors
+CONFIG_PLATFORM_EC_AMD_SB_RMI=y
+CONFIG_PLATFORM_EC_AMD_STT=y
 CONFIG_PLATFORM_EC_TEMP_SENSOR=y
 CONFIG_PLATFORM_EC_TEMP_SENSOR_SB_TSI=y
 CONFIG_PLATFORM_EC_THERMISTOR=y
@@ -59,11 +61,6 @@ CONFIG_SENSOR_SHELL=n
 # Fan
 CONFIG_TACH_NPCX=y
 
-# LEDs
-CONFIG_PLATFORM_EC_LED_COMMON=y
-CONFIG_PLATFORM_EC_LED_ONOFF_STATES=y
-CONFIG_PLATFORM_EC_LED_PWM=y
-
 # Lid switch
 CONFIG_PLATFORM_EC_LID_ANGLE=y
 CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y
@@ -74,6 +71,8 @@ CONFIG_PLATFORM_EC_KBLIGHT_ENABLE_PIN=y
 CONFIG_PLATFORM_EC_KEYBOARD=y
 CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED=y
 CONFIG_PLATFORM_EC_VOLUME_BUTTONS=y
+CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI3=y
+CONFIG_PLATFORM_EC_KEYBOARD_REFRESH_ROW3=y
 
 # PWM
 CONFIG_PWM=y
@@ -133,7 +132,6 @@ CONFIG_GPIO_NCT38XX=y
 
 # Hibernate and wake
 CONFIG_PLATFORM_EC_BOARD_RESET_AFTER_POWER_ON=y
-CONFIG_PLATFORM_EC_HIBERNATE_PSL=y
 
 # Motion sense
 CONFIG_PLATFORM_EC_MOTIONSENSE=y
@@ -159,3 +157,13 @@ CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y
 # Misc.
 CONFIG_PLATFORM_EC_I2C_DEBUG=y
 CONFIG_PLATFORM_EC_PORT80_4_BYTE=y
+
+# These are debug options that happen to be expensive in terms of flash space.
+# Turn on as needed based on demand.
+CONFIG_FLASH_PAGE_LAYOUT=n # 1876 bytes
+CONFIG_FLASH_SHELL=n # 1852 bytes
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=n # 656 bytes
+CONFIG_PLATFORM_EC_CONSOLE_CMD_MEM=n # 896 bytes
+# CONFIG_PLATFORM_EC_CONSOLE_CMD_TCPC_DUMP=n # 1180 bytes
+CONFIG_PLATFORM_EC_CONSOLE_CMD_USB_PD_CABLE=n # 1104 bytes
+CONFIG_THREAD_MONITOR=n # 1548 bytes
diff --git a/zephyr/projects/skyrim/prj_guybrush.conf b/zephyr/projects/skyrim/prj_guybrush.conf
deleted file mode 100644
index 0ca57174a4..0000000000
--- a/zephyr/projects/skyrim/prj_guybrush.conf
+++ /dev/null
@@ -1,9 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# Guybrush board-specific Kconfig settings.
-CONFIG_BOARD_GUYBRUSH=y
-
-# Only Guybrush has TMP112
-CONFIG_PLATFORM_EC_TEMP_SENSOR_TMP112=y
\ No newline at end of file
diff --git a/zephyr/projects/skyrim/prj_morthal.conf b/zephyr/projects/skyrim/prj_morthal.conf
new file mode 100644
index 0000000000..3d2b3fddb7
--- /dev/null
+++ b/zephyr/projects/skyrim/prj_morthal.conf
@@ -0,0 +1,23 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Morthal reference-board-specific Kconfig settings.
+CONFIG_BOARD_MORTHAL=y
+
+# TODO(b/215404321): Remove later in board development
+CONFIG_PLATFORM_EC_EEPROM_CBI_WP=y
+CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y
+
+# LED
+CONFIG_PLATFORM_EC_LED_DT=y
+
+# Morthal is capable of sinking 100W
+CONFIG_PLATFORM_EC_PD_MAX_POWER_MW=100000
+CONFIG_PLATFORM_EC_PD_MAX_CURRENT_MA=5000
+CONFIG_PLATFORM_EC_PD_MAX_VOLTAGE_MV=20000
+
+# Only Morthal has the PCT2075
+CONFIG_PLATFORM_EC_TEMP_SENSOR_PCT2075=y
+
+CONFIG_PLATFORM_EC_USBC_RETIMER_ANX7483=y
diff --git a/zephyr/projects/skyrim/prj_skyrim.conf b/zephyr/projects/skyrim/prj_skyrim.conf
index 2a524cf442..6a0ced86dd 100644
--- a/zephyr/projects/skyrim/prj_skyrim.conf
+++ b/zephyr/projects/skyrim/prj_skyrim.conf
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -8,14 +8,20 @@ CONFIG_BOARD_SKYRIM=y
 # TODO(b/215404321): Remove later in board development
 CONFIG_PLATFORM_EC_EEPROM_CBI_WP=y
 CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y
-CONFIG_PLATFORM_EC_KEYBOARD_DEBUG=y
-CONFIG_PLATFORM_EC_POWERSEQ_FAKE_CONTROL=y
 
 # LED
-CONFIG_PLATFORM_EC_LED_COMMON=n
 CONFIG_PLATFORM_EC_LED_DT=y
 
+# Skyrim is capable of sinking 100W
+CONFIG_PLATFORM_EC_PD_MAX_POWER_MW=100000
+CONFIG_PLATFORM_EC_PD_MAX_CURRENT_MA=5000
+CONFIG_PLATFORM_EC_PD_MAX_VOLTAGE_MV=20000
+
 # Only Skyrim has the PCT2075
 CONFIG_PLATFORM_EC_TEMP_SENSOR_PCT2075=y
 
 CONFIG_PLATFORM_EC_USBC_RETIMER_ANX7483=y
+
+# Enable alternative charger chip
+CONFIG_PLATFORM_EC_CHARGER_RUNTIME_CONFIG=y
+CONFIG_PLATFORM_EC_CHARGER_ISL9238C=y
diff --git a/zephyr/projects/skyrim/prj_winterhold.conf b/zephyr/projects/skyrim/prj_winterhold.conf
new file mode 100644
index 0000000000..3e6c967c6d
--- /dev/null
+++ b/zephyr/projects/skyrim/prj_winterhold.conf
@@ -0,0 +1,18 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Winterhold reference-board-specific Kconfig settings.
+CONFIG_BOARD_WINTERHOLD=y
+
+# TODO(b/215404321): Remove later in board development
+CONFIG_PLATFORM_EC_EEPROM_CBI_WP=y
+CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y
+
+# LED
+CONFIG_PLATFORM_EC_LED_DT=y
+
+# Only Winterhold has the PCT2075
+CONFIG_PLATFORM_EC_TEMP_SENSOR_PCT2075=y
+
+CONFIG_PLATFORM_EC_USBC_RETIMER_ANX7483=y
diff --git a/zephyr/projects/skyrim/skyrim.dts b/zephyr/projects/skyrim/skyrim.dts
index 8b4b5505ad..02308e4390 100644
--- a/zephyr/projects/skyrim/skyrim.dts
+++ b/zephyr/projects/skyrim/skyrim.dts
@@ -1,150 +1,32 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-/ {
-	aliases {
-		gpio-wp = &gpio_wp;
-		gpio-cbi-wp = &gpio_cbi_wp;
-		gpio-kbd-kso2 = &gpio_ec_kso_02_inv;
-	};
+#include <dt-bindings/usbc_mux.h>
+
+#include "i2c_common.dtsi"
 
+/ {
 	named-gpios {
 		/* Skyrim-specific GPIO customizations */
-		usb_fault_odl {
-			gpios = <&gpio5 0 GPIO_ODR_HIGH>;
-		};
-		gpio_en_pwr_s3: en_pwr_s3 {
-			gpios = <&gpio7 4 GPIO_OUTPUT_LOW>;
-		};
-		gpio_pg_groupc_s0_od: pg_groupc_s0_od {
-			gpios = <&gpiof 0 GPIO_INPUT>;
-		};
-		/* TODO: Add interrupt handler */
-		ec_i2c_usbc_pd_int {
-			gpios = <&gpioa 3 GPIO_INPUT>;
-		};
-		/* TODO: Add interrupt handler */
-		soc_thermtrip_odl {
-			gpios = <&gpio9 5 GPIO_INPUT>;
-		};
-		gpio_hub_rst: hub_rst {
-			gpios = <&gpio6 6 GPIO_OUTPUT_HIGH>;
-		};
-		ec_soc_int_l {
-			gpios = <&gpioa 1 GPIO_OUTPUT_HIGH>;
-			enum-name = "GPIO_EC_INT_L";
-		};
-		gpio_ec_soc_pwr_good: ec_soc_pwr_good {
-			gpios = <&gpiod 3 GPIO_OUTPUT_LOW>;
-		};
-		/* TODO: Add interrupt handler to shut down */
-		pcore_ocp_r_l {
-			gpios = <&gpioa 5 GPIO_INPUT>;
-		};
-		/* TODO: Add interrupt handler */
-		sc_0_int_l {
-			gpios = <&gpio6 3 GPIO_INPUT_PULL_UP>;
-		};
-		/* TODO: Add interrupt handler */
-		usb_hub_fault_q_odl {
-			gpios = <&gpioe 5 GPIO_INPUT_PULL_UP>;
-		};
-		gpio_pg_lpddr5_s3_od: pg_lpddr5_s3_od {
-			gpios = <&gpio7 3 GPIO_INPUT>;
-		};
-		3axis_int_l {
-			gpios = <&gpioa 2 GPIO_INPUT_PULL_UP>;
-		};
-		gpio_ec_soc_pwr_btn_l: ec_soc_pwr_btn_l {
-			gpios = <&gpioa 7 GPIO_OUTPUT_HIGH>;
-			enum-name = "GPIO_PCH_PWRBTN_L";
-		};
-		gpio_volup_btn_odl: volup_btn_odl {
-			gpios = <&gpio6 7 GPIO_INPUT_PULL_UP>;
-			enum-name = "GPIO_VOLUME_UP_L";
-		};
-		gpio_voldn_btn_odl: voldn_btn_odl {
-			gpios = <&gpio7 0 GPIO_INPUT_PULL_UP>;
-			enum-name = "GPIO_VOLUME_DOWN_L";
-		};
-		ec_sc_rst {
-			gpios = <&gpiob 0 GPIO_OUTPUT_LOW>;
-		};
-		gpio_cbi_wp: ec_cbi_wp {
-			gpios = <&gpio8 1 GPIO_OUTPUT_LOW>;
-		};
-		gpio_wp: ec_wp_l {
-			gpios = <&gpiod 7 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
-		};
-		gpio_pg_lpddr5_s0_od: pg_lpddr5_s0_od {
-			gpios = <&gpio6 0 GPIO_INPUT>;
-		};
-		ec_espi_rst_l {
-			gpios = <&gpio5 4 GPIO_PULL_DOWN>;
-		};
-		gpio_accel_gyro_int_l: accel_gyro_int_l {
-			gpios = <&gpioa 0 GPIO_INPUT>;
-		};
-	};
-
-	def-lvol-io-list {
-		compatible = "nuvoton,npcx-lvolctrl-def";
-
-		/*
-		 * Low voltage on I2C2_0, I2C6_1, I2C7_0, USB_FAUT_ODL
-		 */
-		lvol-io-pads = <&lvol_io92 &lvol_io91 &lvol_ioe4 &lvol_ioe3
-				&lvol_iob3 &lvol_iob2 &lvol_io50>;
 	};
 
 	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
 		soc-pct2075 {
-			compatible = "cros-ec,temp-sensor-pct2075",
-				     "cros-ec,temp-sensor";
-			label = "SOC";
-			enum-name = "TEMP_SENSOR_SOC";
-			pct2075-name = "PCT2075_SOC";
-			port = <&i2c_sensor>;
-			i2c-addr-flags = "PCT2075_I2C_ADDR_FLAGS0";
 			temp_host_high = <100>;
 			temp_host_halt = <105>;
 			temp_host_release_high = <80>;
 			temp_host_release_halt = <80>;
-			temp_fan_off = <0>;
+			temp_fan_off = <35>;
 			temp_fan_max = <70>;
 			power-good-pin = <&gpio_pg_pwr_s5>;
+			sensor = <&soc_pct2075>;
 		};
 		amb-pct2075 {
-			compatible = "cros-ec,temp-sensor-pct2075",
-				     "cros-ec,temp-sensor";
-			label = "Ambient";
-			enum-name = "TEMP_SENSOR_AMB";
-			pct2075-name = "PCT2075_AMB";
-			port = <&i2c_sensor>;
-			i2c-addr-flags = "PCT2075_I2C_ADDR_FLAGS7";
 			power-good-pin = <&gpio_pg_pwr_s5>;
-		};
-	};
-
-	gpio-interrupts {
-		compatible = "cros-ec,gpio-interrupts";
-
-		int_pg_lpddr_s3: pg_lpddr_s3 {
-			irq-pin = <&gpio_pg_lpddr5_s3_od>;
-			flags = <GPIO_INT_EDGE_BOTH>;
-			handler = "baseboard_set_en_pwr_pcore";
-		};
-		int_pg_lpddr_s0: pg_lpddr_s0 {
-			irq-pin = <&gpio_pg_lpddr5_s0_od>;
-			flags = <GPIO_INT_EDGE_BOTH>;
-			handler = "baseboard_set_soc_pwr_pgood";
-		};
-		int_s0_pgood: s0_pgood {
-			irq-pin = <&gpio_s0_pgood>;
-			flags = <GPIO_INT_EDGE_BOTH>;
-			handler = "baseboard_s0_pgood";
+			sensor = <&amb_pct2075>;
 		};
 	};
 
@@ -189,6 +71,49 @@
 				default;
 			};
 		};
+
+		/*
+		 * FW_CONFIG field to enable fan or not.
+		 */
+		fan {
+			enum-name = "FW_FAN";
+			start = <10>;
+			size = <1>;
+
+			no-fan {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FAN_NOT_PRESENT";
+				value = <0>;
+			};
+			fan-present {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FAN_PRESENT";
+				value = <1>;
+				/*
+				 * Set as default so that unprovisioned
+				 * configs will run the fan regardless.
+				 */
+				default;
+			};
+		};
+
+		charger-option {
+			enum-name = "FW_CHARGER";
+			start = <11>;
+			size = <2>;
+
+			charger-option-isl9241 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_CHARGER_ISL9241";
+				value = <0>;
+				default;
+			};
+			charger-option-isl9538 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_CHARGER_ISL9538";
+				value = <1>;
+			};
+		};
 	};
 
 	/* Rotation matrices for motion sensors. */
@@ -200,17 +125,78 @@
 				 0 0 1>;
 		};
 
+		lid_rot_ref1: lid-rotation-ref1 {
+			mat33 = <0 1 0
+				 (-1) 0 0
+				 0 0 1>;
+		};
+
 		base_rot_ref: base-rotation-ref {
 			mat33 = <0 1 0
 				 (-1) 0 0
 				 0 0 1>;
 		};
 	};
+
+	ppc_port0: aoz1380 {
+		compatible = "aoz,aoz1380";
+		status = "okay";
+	};
 };
 
-/* host interface */
-&espi0 {
-	status = "okay";
-	pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>;
-	pinctrl-names = "default";
+&i2c0_0 {
+	anx7483_port0: anx7483@3e {
+		compatible = "analogix,anx7483";
+		reg = <0x3e>;
+		board-set = "board_anx7483_c0_mux_set";
+	};
+};
+
+&i2c1_0 {
+	anx7483_port1: anx7483@3e {
+		compatible = "analogix,anx7483";
+		reg = <0x3e>;
+		board-set = "board_anx7483_c1_mux_set";
+	};
+	ppc_port1: nx20p348x@71 {
+		compatible = "nxp,nx20p348x";
+		status = "okay";
+		reg = <0x71>;
+	};
+	ps8818_port1: ps8818@28 {
+		compatible = "parade,ps8818";
+		reg = <0x28>;
+		flags = <(USB_MUX_FLAG_RESETS_IN_G3)>;
+		board-set = "board_c1_ps8818_mux_set";
+	};
+};
+
+&i2c4_1 {
+	alt_charger: isl9538@9 {
+		compatible = "intersil,isl923x";
+		status = "okay";
+		reg = <0x9>;
+	};
+};
+
+&usbc_port0 {
+	chg_alt = <&alt_charger>;
+	ppc = <&ppc_port0>;
+	usb-mux-chain-0 {
+		compatible = "cros-ec,usb-mux-chain";
+		usb-muxes = <&amd_fp6_port0 &anx7483_port0>;
+	};
+};
+
+&usbc_port1 {
+	ppc = <&ppc_port1>;
+	usb-mux-chain-1-anx {
+		compatible = "cros-ec,usb-mux-chain";
+		usb-muxes = <&amd_fp6_port1 &anx7483_port1>;
+	};
+	usb_mux_chain_ps8818_port1: usb-mux-chain-1-ps {
+		compatible = "cros-ec,usb-mux-chain";
+		usb-muxes = <&amd_fp6_port1 &ps8818_port1>;
+		alternative-chain;
+	};
 };
diff --git a/zephyr/projects/skyrim/src/common.c b/zephyr/projects/skyrim/src/common.c
new file mode 100644
index 0000000000..af82139c1b
--- /dev/null
+++ b/zephyr/projects/skyrim/src/common.c
@@ -0,0 +1,8 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(skyrim, CONFIG_SKYRIM_LOG_LEVEL);
diff --git a/zephyr/projects/skyrim/src/morthal/ppc_config.c b/zephyr/projects/skyrim/src/morthal/ppc_config.c
new file mode 100644
index 0000000000..f3ec1d312e
--- /dev/null
+++ b/zephyr/projects/skyrim/src/morthal/ppc_config.c
@@ -0,0 +1,46 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Morthal board-specific PPC code */
+
+#include <zephyr/drivers/gpio.h>
+
+#include "driver/ppc/nx20p348x.h"
+#include "driver/ppc/aoz1380_public.h"
+#include "usbc_ppc.h"
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/*
+ * In the AOZ1380 PPC, there are no programmable features.  We use
+ * the attached NCT3807 to control a GPIO to indicate 1A5 or 3A0
+ * current limits.
+ */
+int board_aoz1380_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	int rv = EC_SUCCESS;
+
+	rv = gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(ioex_usb_c0_ilim_3a_en),
+			     (rp == TYPEC_RP_3A0) ? 1 : 0);
+
+	return rv;
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		aoz1380_interrupt(0);
+		break;
+
+	case GPIO_USB_C1_PPC_INT_ODL:
+		nx20p348x_interrupt(1);
+		break;
+
+	default:
+		break;
+	}
+}
diff --git a/zephyr/projects/skyrim/src/morthal/usb_mux_config.c b/zephyr/projects/skyrim/src/morthal/usb_mux_config.c
new file mode 100644
index 0000000000..8fe76233e2
--- /dev/null
+++ b/zephyr/projects/skyrim/src/morthal/usb_mux_config.c
@@ -0,0 +1,142 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Morthal board-specific USB-C mux configuration */
+
+#include <zephyr/drivers/gpio.h>
+
+#include "console.h"
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+#include "driver/retimer/anx7483_public.h"
+#include "hooks.h"
+#include "ioexpander.h"
+#include "usb_mux.h"
+#include "usbc/usb_muxes.h"
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/*
+ * USB C0 (general) and C1 (just ANX DB) use IOEX pins to
+ * indicate flipped polarity to a protection switch.
+ */
+static int ioex_set_flip(int port, mux_state_t mux_state)
+{
+	if (port == 0) {
+		if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
+			gpio_pin_set_dt(
+				GPIO_DT_FROM_NODELABEL(ioex_usb_c0_sbu_flip),
+				1);
+		else
+			gpio_pin_set_dt(
+				GPIO_DT_FROM_NODELABEL(ioex_usb_c0_sbu_flip),
+				0);
+	} else {
+		if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
+			gpio_pin_set_dt(
+				GPIO_DT_FROM_NODELABEL(ioex_usb_c1_sbu_flip),
+				1);
+		else
+			gpio_pin_set_dt(
+				GPIO_DT_FROM_NODELABEL(ioex_usb_c1_sbu_flip),
+				0);
+	}
+
+	return EC_SUCCESS;
+}
+
+int board_anx7483_c0_mux_set(const struct usb_mux *me, mux_state_t mux_state)
+{
+	/* Set the SBU polarity mux */
+	RETURN_ERROR(ioex_set_flip(me->usb_port, mux_state));
+
+	return anx7483_set_default_tuning(me, mux_state);
+}
+
+int board_anx7483_c1_mux_set(const struct usb_mux *me, mux_state_t mux_state)
+{
+	bool flipped = mux_state & USB_PD_MUX_POLARITY_INVERTED;
+
+	/* Set the SBU polarity mux */
+	RETURN_ERROR(ioex_set_flip(me->usb_port, mux_state));
+
+	/* Remove flipped from the state for easier compraisons */
+	mux_state = mux_state & ~USB_PD_MUX_POLARITY_INVERTED;
+
+	RETURN_ERROR(anx7483_set_default_tuning(me, mux_state));
+
+	if (mux_state == USB_PD_MUX_USB_ENABLED) {
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX1,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX2,
+					    ANX7483_EQ_SETTING_12_5DB));
+	} else if (mux_state == USB_PD_MUX_DP_ENABLED) {
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX1,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX2,
+					    ANX7483_EQ_SETTING_12_5DB));
+	} else if (mux_state == USB_PD_MUX_DOCK && !flipped) {
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX1,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX2,
+					    ANX7483_EQ_SETTING_12_5DB));
+	} else if (mux_state == USB_PD_MUX_DOCK && flipped) {
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX1,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX2,
+					    ANX7483_EQ_SETTING_12_5DB));
+	}
+
+	return EC_SUCCESS;
+}
+
+int board_c1_ps8818_mux_set(const struct usb_mux *me, mux_state_t mux_state)
+{
+	CPRINTSUSB("C1: PS8818 mux using default tuning");
+
+	/* Once a DP connection is established, we need to set IN_HPD */
+	if (mux_state & USB_PD_MUX_DP_ENABLED)
+		ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 1);
+	else
+		ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 0);
+
+	return 0;
+}
+
+static void setup_mux(void)
+{
+	uint32_t val;
+
+	if (cros_cbi_get_fw_config(FW_IO_DB, &val) != 0)
+		CPRINTSUSB("Error finding FW_DB_IO in CBI FW_CONFIG");
+	/* Val will have our dts default on error, so continue setup */
+
+	if (val == FW_IO_DB_PS8811_PS8818) {
+		CPRINTSUSB("C1: Setting PS8818 mux");
+		USB_MUX_ENABLE_ALTERNATIVE(usb_mux_chain_ps8818_port1);
+	} else if (val == FW_IO_DB_NONE_ANX7483) {
+		CPRINTSUSB("C1: Setting ANX7483 mux");
+	} else {
+		CPRINTSUSB("Unexpected DB_IO board: %d", val);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, setup_mux, HOOK_PRIO_INIT_I2C);
diff --git a/zephyr/projects/skyrim/power_signals.c b/zephyr/projects/skyrim/src/power_signals.c
index e85cea1f04..3c56e51ddc 100644
--- a/zephyr/projects/skyrim/power_signals.c
+++ b/zephyr/projects/skyrim/src/power_signals.c
@@ -1,16 +1,20 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "ap_power/ap_power.h"
+#include "charger.h"
 #include "chipset.h"
 #include "config.h"
+#include "cros_board_info.h"
 #include "gpio_signal.h"
 #include "gpio/gpio_int.h"
 #include "hooks.h"
+#include "i2c.h"
 #include "ioexpander.h"
 #include "power.h"
+#include "power/amd_x86.h"
 #include "timer.h"
 
 /* Power Signal Input List */
@@ -49,15 +53,15 @@ static void baseboard_suspend_change(struct ap_power_ev_callback *cb,
 
 	case AP_POWER_SUSPEND:
 		/* Disable display backlight and retimer */
-		gpio_pin_set_dt(
-			GPIO_DT_FROM_NODELABEL(gpio_ec_disable_disp_bl), 1);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_disable_disp_bl),
+				1);
 		ioex_set_level(IOEX_USB_A1_RETIMER_EN, 0);
 		break;
 
 	case AP_POWER_RESUME:
 		/* Enable retimer and display backlight */
-		gpio_pin_set_dt(
-			GPIO_DT_FROM_NODELABEL(gpio_ec_disable_disp_bl), 0);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_disable_disp_bl),
+				0);
 		ioex_set_level(IOEX_USB_A1_RETIMER_EN, 1);
 		/* Any retimer tuning can be done after the retimer turns on */
 		break;
@@ -76,6 +80,9 @@ static void baseboard_init(void)
 	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pg_groupc_s0));
 	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pg_lpddr_s0));
 	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pg_lpddr_s3));
+
+	/* Enable thermtrip interrupt */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_soc_thermtrip));
 }
 DECLARE_HOOK(HOOK_INIT, baseboard_init, HOOK_PRIO_POST_I2C);
 
@@ -84,7 +91,7 @@ DECLARE_HOOK(HOOK_INIT, baseboard_init, HOOK_PRIO_POST_I2C);
  * PCH_PWRBTN_L.  This can be as long as ~65ms after cold boot.  Then wait an
  * additional delay of T1a defined in the EDS before changing the power button.
  */
-#define RSMRST_WAIT_DELAY	     70
+#define RSMRST_WAIT_DELAY 70
 #define EDS_PWR_BTN_RSMRST_T1A_DELAY 16
 void board_pwrbtn_to_pch(int level)
 {
@@ -96,13 +103,13 @@ void board_pwrbtn_to_pch(int level)
 		start = get_time();
 		do {
 			usleep(500);
-			if (gpio_pin_get_dt(
-				GPIO_DT_FROM_NODELABEL(gpio_ec_soc_rsmrst_l)))
+			if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(
+				    gpio_ec_soc_rsmrst_l)))
 				break;
 		} while (time_since32(start) < (RSMRST_WAIT_DELAY * MSEC));
 
 		if (!gpio_pin_get_dt(
-			GPIO_DT_FROM_NODELABEL(gpio_ec_soc_rsmrst_l)))
+			    GPIO_DT_FROM_NODELABEL(gpio_ec_soc_rsmrst_l)))
 			ccprints("Error pwrbtn: RSMRST_L still low");
 
 		msleep(EDS_PWR_BTN_RSMRST_T1A_DELAY);
@@ -113,11 +120,34 @@ void board_pwrbtn_to_pch(int level)
 /* Note: signal parameter unused */
 void baseboard_set_soc_pwr_pgood(enum gpio_signal unused)
 {
-	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_soc_pwr_good),
-	    gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pwr_pcore_s0_r)) &&
-	    gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_pg_lpddr5_s0_od)) &&
-	    gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_s0_pgood)));
+	gpio_pin_set_dt(
+		GPIO_DT_FROM_NODELABEL(gpio_ec_soc_pwr_good),
+		gpio_pin_get_dt(
+			GPIO_DT_FROM_NODELABEL(gpio_en_pwr_pcore_s0_r)) &&
+			gpio_pin_get_dt(
+				GPIO_DT_FROM_NODELABEL(gpio_pg_lpddr5_s0_od)) &&
+			gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_s0_pgood)));
+}
+
+/* TODO: Remove when board versions are no longer supported */
+#define MP2845A_I2C_ADDR_FLAGS 0x20
+#define MP2854A_MFR_VOUT_CMPS_MAX_REG 0x69
+#define MP2854A_MFR_LOW_PWR_SEL BIT(12)
+
+static void setup_mp2845(void)
+{
+	int version;
+
+	/* TODO: Remove when board versions are no longer supported */
+	if ((cbi_get_board_version(&version) == EC_SUCCESS) && version > 3)
+		return;
+
+	if (i2c_update16(chg_chips[CHARGER_SOLO].i2c_port,
+			 MP2845A_I2C_ADDR_FLAGS, MP2854A_MFR_VOUT_CMPS_MAX_REG,
+			 MP2854A_MFR_LOW_PWR_SEL, MASK_CLR))
+		ccprints("Failed to send mp2845 workaround");
 }
+DECLARE_DEFERRED(setup_mp2845);
 
 void baseboard_s0_pgood(enum gpio_signal signal)
 {
@@ -125,6 +155,10 @@ void baseboard_s0_pgood(enum gpio_signal signal)
 
 	/* Chain off power signal interrupt handler for PG_PCORE_S0_R_OD */
 	power_signal_interrupt(signal);
+
+	/* Set up the MP2845, which is powered in S0 */
+	if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_s0_pgood)))
+		hook_call_deferred(&setup_mp2845_data, 50 * MSEC);
 }
 
 /* Note: signal parameter unused */
@@ -134,10 +168,13 @@ void baseboard_set_en_pwr_pcore(enum gpio_signal unused)
 	 * EC must AND signals PG_LPDDR5_S3_OD, PG_GROUPC_S0_OD, and
 	 * EN_PWR_S0_R
 	 */
-	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pwr_pcore_s0_r),
-	    gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_pg_lpddr5_s3_od)) &&
-	    gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_pg_groupc_s0_od)) &&
-	    gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pwr_s0_r)));
+	gpio_pin_set_dt(
+		GPIO_DT_FROM_NODELABEL(gpio_en_pwr_pcore_s0_r),
+		gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_pg_lpddr5_s3_od)) &&
+			gpio_pin_get_dt(
+				GPIO_DT_FROM_NODELABEL(gpio_pg_groupc_s0_od)) &&
+			gpio_pin_get_dt(
+				GPIO_DT_FROM_NODELABEL(gpio_en_pwr_s0_r)));
 
 	/* Update EC_SOC_PWR_GOOD based on our results */
 	baseboard_set_soc_pwr_pgood(unused);
@@ -146,9 +183,11 @@ void baseboard_set_en_pwr_pcore(enum gpio_signal unused)
 void baseboard_en_pwr_s0(enum gpio_signal signal)
 {
 	/* EC must AND signals SLP_S3_L and PG_PWR_S5 */
-	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pwr_s0_r),
-	    gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_slp_s3_l)) &&
-	    gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_pg_pwr_s5)));
+	gpio_pin_set_dt(
+		GPIO_DT_FROM_NODELABEL(gpio_en_pwr_s0_r),
+		gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_slp_s3_l)) &&
+			gpio_pin_get_dt(
+				GPIO_DT_FROM_NODELABEL(gpio_pg_pwr_s5)));
 
 	/* Change EN_PWR_PCORE_S0_R if needed*/
 	baseboard_set_en_pwr_pcore(signal);
@@ -179,8 +218,14 @@ void baseboard_set_en_pwr_s3(enum gpio_signal signal)
 {
 	/* EC must enable PWR_S3 when SLP_S5_L goes high, disable on low */
 	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pwr_s3),
-	    gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_slp_s5_l)));
+			gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_slp_s5_l)));
 
 	/* Chain off the normal power signal interrupt handler */
 	power_signal_interrupt(signal);
 }
+
+void baseboard_soc_thermtrip(enum gpio_signal signal)
+{
+	ccprints("SoC thermtrip reported, shutting down");
+	chipset_force_shutdown(CHIPSET_SHUTDOWN_THERMAL);
+}
diff --git a/zephyr/projects/skyrim/src/skyrim/alt_charger.c b/zephyr/projects/skyrim/src/skyrim/alt_charger.c
new file mode 100644
index 0000000000..4b717901cd
--- /dev/null
+++ b/zephyr/projects/skyrim/src/skyrim/alt_charger.c
@@ -0,0 +1,31 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/devicetree.h>
+#include <zephyr/logging/log.h>
+
+#include "charger_chips.h"
+#include "common.h"
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+#include "hooks.h"
+
+LOG_MODULE_DECLARE(skyrim, CONFIG_SKYRIM_LOG_LEVEL);
+
+static void alt_charger_init(void)
+{
+	int ret;
+	uint32_t val;
+
+	ret = cros_cbi_get_fw_config(FW_CHARGER, &val);
+	if (ret != 0) {
+		LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_CHARGER);
+		return;
+	}
+
+	if (val == FW_CHARGER_ISL9538)
+		CHG_ENABLE_ALTERNATE(0);
+}
+DECLARE_HOOK(HOOK_INIT, alt_charger_init, HOOK_PRIO_POST_FIRST);
diff --git a/zephyr/projects/skyrim/src/skyrim/fan.c b/zephyr/projects/skyrim/src/skyrim/fan.c
new file mode 100644
index 0000000000..70d512bb78
--- /dev/null
+++ b/zephyr/projects/skyrim/src/skyrim/fan.c
@@ -0,0 +1,46 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/logging/log.h>
+
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+#include "fan.h"
+#include "gpio/gpio.h"
+#include "hooks.h"
+
+LOG_MODULE_DECLARE(skyrim, CONFIG_SKYRIM_LOG_LEVEL);
+
+/*
+ * Skyrim fan support
+ */
+static void fan_init(void)
+{
+	int ret;
+	uint32_t val;
+	uint32_t board_version;
+	/*
+	 * Retrieve the fan config.
+	 */
+	ret = cros_cbi_get_fw_config(FW_FAN, &val);
+	if (ret != 0) {
+		LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_FAN);
+		return;
+	}
+
+	ret = cbi_get_board_version(&board_version);
+	if (ret != EC_SUCCESS) {
+		LOG_ERR("Error retrieving CBI board version");
+		return;
+	}
+
+	if ((board_version >= 3) && (val != FW_FAN_PRESENT)) {
+		/* Disable the fan */
+		fan_set_count(0);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, fan_init, HOOK_PRIO_POST_FIRST);
diff --git a/zephyr/projects/skyrim/src/skyrim/form_factor.c b/zephyr/projects/skyrim/src/skyrim/form_factor.c
new file mode 100644
index 0000000000..f137c6db31
--- /dev/null
+++ b/zephyr/projects/skyrim/src/skyrim/form_factor.c
@@ -0,0 +1,37 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/devicetree.h>
+#include <zephyr/logging/log.h>
+#include "common.h"
+#include "accelgyro.h"
+#include "cros_board_info.h"
+#include "hooks.h"
+#include "motionsense_sensors.h"
+
+LOG_MODULE_DECLARE(skyrim, CONFIG_SKYRIM_LOG_LEVEL);
+
+/*
+ * Mainboard orientation support.
+ */
+
+#define ALT_MAT SENSOR_ROT_STD_REF_NAME(DT_NODELABEL(lid_rot_ref1))
+#define LID_ACCEL SENSOR_ID(DT_NODELABEL(lid_accel))
+
+static void form_factor_init(void)
+{
+	int ret;
+	uint32_t val;
+	/*
+	 * If the board version >=4
+	 * use ver1 rotation matrix.
+	 */
+	ret = cbi_get_board_version(&val);
+	if (ret == EC_SUCCESS && val >= 4) {
+		LOG_INF("Switching to ver1 lid");
+		motion_sensors[LID_ACCEL].rot_standard_ref = &ALT_MAT;
+	}
+}
+DECLARE_HOOK(HOOK_INIT, form_factor_init, HOOK_PRIO_POST_I2C);
diff --git a/zephyr/projects/skyrim/src/skyrim/ppc_config.c b/zephyr/projects/skyrim/src/skyrim/ppc_config.c
new file mode 100644
index 0000000000..bebc8adcc7
--- /dev/null
+++ b/zephyr/projects/skyrim/src/skyrim/ppc_config.c
@@ -0,0 +1,46 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Skyrim board-specific PPC code */
+
+#include <zephyr/drivers/gpio.h>
+
+#include "driver/ppc/nx20p348x.h"
+#include "driver/ppc/aoz1380_public.h"
+#include "usbc_ppc.h"
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/*
+ * In the AOZ1380 PPC, there are no programmable features.  We use
+ * the attached NCT3807 to control a GPIO to indicate 1A5 or 3A0
+ * current limits.
+ */
+int board_aoz1380_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	int rv = EC_SUCCESS;
+
+	rv = gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(ioex_usb_c0_ilim_3a_en),
+			     (rp == TYPEC_RP_3A0) ? 1 : 0);
+
+	return rv;
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		aoz1380_interrupt(0);
+		break;
+
+	case GPIO_USB_C1_PPC_INT_ODL:
+		nx20p348x_interrupt(1);
+		break;
+
+	default:
+		break;
+	}
+}
diff --git a/zephyr/projects/skyrim/src/skyrim/usb_mux_config.c b/zephyr/projects/skyrim/src/skyrim/usb_mux_config.c
new file mode 100644
index 0000000000..6c65e56d9e
--- /dev/null
+++ b/zephyr/projects/skyrim/src/skyrim/usb_mux_config.c
@@ -0,0 +1,142 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Skyrim board-specific USB-C mux configuration */
+
+#include <zephyr/drivers/gpio.h>
+
+#include "console.h"
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+#include "driver/retimer/anx7483_public.h"
+#include "hooks.h"
+#include "ioexpander.h"
+#include "usb_mux.h"
+#include "usbc/usb_muxes.h"
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/*
+ * USB C0 (general) and C1 (just ANX DB) use IOEX pins to
+ * indicate flipped polarity to a protection switch.
+ */
+static int ioex_set_flip(int port, mux_state_t mux_state)
+{
+	if (port == 0) {
+		if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
+			gpio_pin_set_dt(
+				GPIO_DT_FROM_NODELABEL(ioex_usb_c0_sbu_flip),
+				1);
+		else
+			gpio_pin_set_dt(
+				GPIO_DT_FROM_NODELABEL(ioex_usb_c0_sbu_flip),
+				0);
+	} else {
+		if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
+			gpio_pin_set_dt(
+				GPIO_DT_FROM_NODELABEL(ioex_usb_c1_sbu_flip),
+				1);
+		else
+			gpio_pin_set_dt(
+				GPIO_DT_FROM_NODELABEL(ioex_usb_c1_sbu_flip),
+				0);
+	}
+
+	return EC_SUCCESS;
+}
+
+int board_anx7483_c0_mux_set(const struct usb_mux *me, mux_state_t mux_state)
+{
+	/* Set the SBU polarity mux */
+	RETURN_ERROR(ioex_set_flip(me->usb_port, mux_state));
+
+	return anx7483_set_default_tuning(me, mux_state);
+}
+
+int board_anx7483_c1_mux_set(const struct usb_mux *me, mux_state_t mux_state)
+{
+	bool flipped = mux_state & USB_PD_MUX_POLARITY_INVERTED;
+
+	/* Set the SBU polarity mux */
+	RETURN_ERROR(ioex_set_flip(me->usb_port, mux_state));
+
+	/* Remove flipped from the state for easier compraisons */
+	mux_state = mux_state & ~USB_PD_MUX_POLARITY_INVERTED;
+
+	RETURN_ERROR(anx7483_set_default_tuning(me, mux_state));
+
+	if (mux_state == USB_PD_MUX_USB_ENABLED) {
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX1,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX2,
+					    ANX7483_EQ_SETTING_12_5DB));
+	} else if (mux_state == USB_PD_MUX_DP_ENABLED) {
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX1,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX2,
+					    ANX7483_EQ_SETTING_12_5DB));
+	} else if (mux_state == USB_PD_MUX_DOCK && !flipped) {
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX1,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX2,
+					    ANX7483_EQ_SETTING_12_5DB));
+	} else if (mux_state == USB_PD_MUX_DOCK && flipped) {
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX1,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX2,
+					    ANX7483_EQ_SETTING_12_5DB));
+	}
+
+	return EC_SUCCESS;
+}
+
+int board_c1_ps8818_mux_set(const struct usb_mux *me, mux_state_t mux_state)
+{
+	CPRINTSUSB("C1: PS8818 mux using default tuning");
+
+	/* Once a DP connection is established, we need to set IN_HPD */
+	if (mux_state & USB_PD_MUX_DP_ENABLED)
+		ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 1);
+	else
+		ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 0);
+
+	return 0;
+}
+
+static void setup_mux(void)
+{
+	uint32_t val;
+
+	if (cros_cbi_get_fw_config(FW_IO_DB, &val) != 0)
+		CPRINTSUSB("Error finding FW_DB_IO in CBI FW_CONFIG");
+	/* Val will have our dts default on error, so continue setup */
+
+	if (val == FW_IO_DB_PS8811_PS8818) {
+		CPRINTSUSB("C1: Setting PS8818 mux");
+		USB_MUX_ENABLE_ALTERNATIVE(usb_mux_chain_ps8818_port1);
+	} else if (val == FW_IO_DB_NONE_ANX7483) {
+		CPRINTSUSB("C1: Setting ANX7483 mux");
+	} else {
+		CPRINTSUSB("Unexpected DB_IO board: %d", val);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, setup_mux, HOOK_PRIO_INIT_I2C);
diff --git a/zephyr/projects/skyrim/src/stt.c b/zephyr/projects/skyrim/src/stt.c
new file mode 100644
index 0000000000..40743fbc68
--- /dev/null
+++ b/zephyr/projects/skyrim/src/stt.c
@@ -0,0 +1,28 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Support code for STT temperature reporting */
+
+#include "chipset.h"
+#include "temp_sensor/pct2075.h"
+#include "temp_sensor/temp_sensor.h"
+
+int board_get_soc_temp_mk(int *temp_mk)
+{
+	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	return pct2075_get_val_mk(PCT2075_SENSOR_ID(DT_NODELABEL(soc_pct2075)),
+				  temp_mk);
+}
+
+int board_get_ambient_temp_mk(int *temp_mk)
+{
+	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+	return pct2075_get_val_mk(PCT2075_SENSOR_ID(DT_NODELABEL(amb_pct2075)),
+				  temp_mk);
+}
diff --git a/zephyr/projects/skyrim/usb_pd_policy.c b/zephyr/projects/skyrim/src/usb_pd_policy.c
index 1d6457278a..ec9f873863 100644
--- a/zephyr/projects/skyrim/usb_pd_policy.c
+++ b/zephyr/projects/skyrim/src/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/skyrim/usbc_config.c b/zephyr/projects/skyrim/src/usbc_config.c
index fe60db2a69..0ca421deca 100644
--- a/zephyr/projects/skyrim/usbc_config.c
+++ b/zephyr/projects/skyrim/src/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,11 +17,10 @@
 #include "charger.h"
 #include "driver/bc12/pi3usb9201.h"
 #include "driver/charger/isl9241.h"
-#include "driver/ppc/aoz1380.h"
 #include "driver/ppc/nx20p348x.h"
 #include "driver/retimer/anx7483_public.h"
 #include "driver/retimer/ps8811.h"
-#include "driver/retimer/ps8818.h"
+#include "driver/retimer/ps8818_public.h"
 #include "driver/tcpm/nct38xx.h"
 #include "driver/usb_mux/amd_fp6.h"
 #include "gpio/gpio_int.h"
@@ -31,23 +30,16 @@
 #include "usb_mux.h"
 #include "usb_pd_tcpm.h"
 #include "usbc_ppc.h"
+#include "usbc/usb_muxes.h"
 
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* USB-A ports */
-enum usba_port {
-	USBA_PORT_A0 = 0,
-	USBA_PORT_A1,
-	USBA_PORT_COUNT
-};
+enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT };
 
 /* USB-C ports */
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 BUILD_ASSERT(USBC_PORT_COUNT == CONFIG_USB_PD_PORT_MAX_COUNT);
 
 static void reset_nct38xx_port(int port);
@@ -66,215 +58,34 @@ static void usbc_interrupt_init(void)
 	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_bc12));
 	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_bc12));
 
-	/* TODO: Enable SBU fault interrupts (io expander )*/
+	/* Enable SBU fault interrupts */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_sbu_fault));
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_sbu_fault));
 }
 DECLARE_HOOK(HOOK_INIT, usbc_interrupt_init, HOOK_PRIO_POST_I2C);
 
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		/* Device does not talk I2C */
-		.drv = &aoz1380_drv
-	},
-
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = NX20P3483_ADDR1_FLAGS,
-		.drv = &nx20p348x_drv
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == CONFIG_USB_PD_PORT_MAX_COUNT);
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/*
- * .init is not necessary here because it has nothing
- * to do. Primary mux will handle mux state so .get is
- * not needed as well. usb_mux.c can handle the situation
- * properly.
- */
-static int ioex_set_flip(const struct usb_mux*, mux_state_t, bool *);
-struct usb_mux_driver ioex_sbu_mux_driver = {
-	.set = ioex_set_flip,
-};
-
-/*
- * Since NX3DV221GM is not a i2c device, .i2c_port and
- * .i2c_addr_flags are not required here.
- */
-struct usb_mux usbc0_sbu_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &ioex_sbu_mux_driver,
-};
-
-struct usb_mux usbc1_sbu_mux = {
-	.usb_port = USBC_PORT_C1,
-	.driver = &ioex_sbu_mux_driver,
-};
-
-int baseboard_anx7483_c0_mux_set(const struct usb_mux *me,
-			      mux_state_t mux_state)
-{
-	return anx7483_set_default_tuning(me, mux_state);
-}
-
-int baseboard_anx7483_c1_mux_set(const struct usb_mux *me,
-			      mux_state_t mux_state)
-{
-	bool flipped = mux_state & USB_PD_MUX_POLARITY_INVERTED;
-
-	/* Remove flipped from the state for easier compraisons */
-	mux_state = mux_state & ~USB_PD_MUX_POLARITY_INVERTED;
-
-	RETURN_ERROR(anx7483_set_default_tuning(me, mux_state));
-
-	if (mux_state == USB_PD_MUX_USB_ENABLED) {
-		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1,
-					    ANX7483_EQ_SETTING_12_5DB));
-		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2,
-					    ANX7483_EQ_SETTING_12_5DB));
-		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX1,
-					    ANX7483_EQ_SETTING_12_5DB));
-		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX2,
-					    ANX7483_EQ_SETTING_12_5DB));
-	} else if (mux_state == USB_PD_MUX_DP_ENABLED) {
-		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1,
-					    ANX7483_EQ_SETTING_12_5DB));
-		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2,
-					    ANX7483_EQ_SETTING_12_5DB));
-		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX1,
-					    ANX7483_EQ_SETTING_12_5DB));
-		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX2,
-					    ANX7483_EQ_SETTING_12_5DB));
-	} else if (mux_state == USB_PD_MUX_DOCK && !flipped) {
-		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1,
-					    ANX7483_EQ_SETTING_12_5DB));
-		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2,
-					    ANX7483_EQ_SETTING_12_5DB));
-		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX1,
-					    ANX7483_EQ_SETTING_12_5DB));
-		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX2,
-					    ANX7483_EQ_SETTING_12_5DB));
-	} else if (mux_state == USB_PD_MUX_DOCK && flipped) {
-		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1,
-					    ANX7483_EQ_SETTING_12_5DB));
-		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2,
-					    ANX7483_EQ_SETTING_12_5DB));
-		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX1,
-					    ANX7483_EQ_SETTING_12_5DB));
-		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX2,
-					    ANX7483_EQ_SETTING_12_5DB));
-	}
-
-	return EC_SUCCESS;
-}
-
-struct usb_mux usbc0_anx7483 = {
-	.usb_port = USBC_PORT_C0,
-	.i2c_port = I2C_PORT_TCPC0,
-	.i2c_addr_flags = ANX7483_I2C_ADDR0_FLAGS,
-	.driver = &anx7483_usb_retimer_driver,
-	.board_set = &baseboard_anx7483_c0_mux_set,
-	.next_mux = &usbc0_sbu_mux,
-};
-
-__overridable int board_c1_ps8818_mux_set(const struct usb_mux *me,
-					  mux_state_t mux_state)
+static void usb_fault_interrupt_init(void)
 {
-	CPRINTSUSB("C1: PS8818 mux using default tuning");
-
-	/* Once a DP connection is established, we need to set IN_HPD */
-	if (mux_state & USB_PD_MUX_DP_ENABLED)
-		ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 1);
-	else
-		ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 0);
-
-	return 0;
-}
-
-struct usb_mux usbc1_ps8818 = {
-	.usb_port = USBC_PORT_C1,
-	.i2c_port = I2C_PORT_TCPC1,
-	.flags = USB_MUX_FLAG_RESETS_IN_G3,
-	.i2c_addr_flags = PS8818_I2C_ADDR_FLAGS,
-	.driver = &ps8818_usb_retimer_driver,
-	.board_set = &board_c1_ps8818_mux_set,
-};
-
-struct usb_mux usbc1_anx7483 = {
-	.usb_port = USBC_PORT_C1,
-	.i2c_port = I2C_PORT_TCPC1,
-	.i2c_addr_flags = ANX7483_I2C_ADDR0_FLAGS,
-	.driver = &anx7483_usb_retimer_driver,
-	.board_set = &baseboard_anx7483_c1_mux_set,
-	.next_mux = &usbc1_sbu_mux,
-};
-
-struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = AMD_FP6_C0_MUX_I2C_ADDR,
-		.driver = &amd_fp6_usb_mux_driver,
-		.next_mux = &usbc0_anx7483,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = AMD_FP6_C4_MUX_I2C_ADDR,
-		.driver = &amd_fp6_usb_mux_driver,
-		/* .next_mux = filled in by setup_mux based on fw_config */
-	}
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == CONFIG_USB_PD_PORT_MAX_COUNT);
-
-/*
- * USB C0 (general) and C1 (just ANX DB) use IOEX pins to
- * indicate flipped polarity to a protection switch.
- */
-static int ioex_set_flip(const struct usb_mux *me, mux_state_t mux_state,
-			 bool *ack_required)
-{
-	/* This driver does not use host command ACKs */
-	*ack_required = false;
-
-	if (me->usb_port == USBC_PORT_C0) {
-		if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-			ioex_set_level(IOEX_USB_C0_SBU_FLIP, 1);
-		else
-			ioex_set_level(IOEX_USB_C0_SBU_FLIP, 0);
-	} else {
-		if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-			ioex_set_level(IOEX_USB_C1_SBU_FLIP, 1);
-		else
-			ioex_set_level(IOEX_USB_C1_SBU_FLIP, 0);
-	}
-
-	return EC_SUCCESS;
+	/* Enable USB fault interrupts when we hit S5 */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_hub_fault));
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_a0_fault));
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_a1_fault));
 }
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, usb_fault_interrupt_init, HOOK_PRIO_DEFAULT);
 
-static void setup_mux(void)
+static void usb_fault_interrupt_disable(void)
 {
-	uint32_t val;
-
-	if (cros_cbi_get_fw_config(FW_IO_DB, &val) != 0)
-		CPRINTSUSB("Error finding FW_DB_IO in CBI FW_CONFIG");
-		/* Val will have our dts default on error, so continue setup */
-
-	if (val == FW_IO_DB_PS8811_PS8818) {
-		CPRINTSUSB("C1: Setting PS8818 mux");
-		usb_muxes[USBC_PORT_C1].next_mux = &usbc1_ps8818;
-	} else if (val == FW_IO_DB_NONE_ANX7483) {
-		CPRINTSUSB("C1: Setting ANX7483 mux");
-		usb_muxes[USBC_PORT_C1].next_mux = &usbc1_anx7483;
-	} else {
-		CPRINTSUSB("Unexpected DB_IO board: %d", val);
-	}
+	/* Disable USB fault interrupts leaving S5 */
+	gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_hub_fault));
+	gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_a0_fault));
+	gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_a1_fault));
 }
-DECLARE_HOOK(HOOK_INIT, setup_mux, HOOK_PRIO_INIT_I2C);
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, usb_fault_interrupt_disable,
+	     HOOK_PRIO_DEFAULT);
 
 int board_set_active_charge_port(int port)
 {
-	int is_valid_port = (port >= 0 &&
-			     port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	int i;
 	int rv;
 
@@ -288,7 +99,7 @@ int board_set_active_charge_port(int port)
 			 * ahead and reset it so EN_SNK responds properly.
 			 */
 			if (nct38xx_get_boot_type(i) ==
-						NCT38XX_BOOT_DEAD_BATTERY) {
+			    NCT38XX_BOOT_DEAD_BATTERY) {
 				reset_nct38xx_port(i);
 				pd_set_error_recovery(i);
 			}
@@ -337,7 +148,7 @@ int board_set_active_charge_port(int port)
 				 * change because we'll brown out.
 				 */
 				if (nct38xx_get_boot_type(port) ==
-						NCT38XX_BOOT_DEAD_BATTERY) {
+				    NCT38XX_BOOT_DEAD_BATTERY) {
 					reset_nct38xx_port(i);
 					pd_set_error_recovery(i);
 				} else {
@@ -379,31 +190,42 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-/*
- * In the AOZ1380 PPC, there are no programmable features.  We use
- * the attached NCT3807 to control a GPIO to indicate 1A5 or 3A0
- * current limits.
- */
-int board_aoz1380_set_vbus_source_current_limit(int port,
-						enum tcpc_rp_value rp)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
-	int rv = EC_SUCCESS;
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+}
 
-	rv = ioex_set_level(IOEX_USB_C0_PPC_ILIM_3A_EN,
-			    (rp == TYPEC_RP_3A0) ? 1 : 0);
+void sbu_fault_interrupt(enum gpio_signal signal)
+{
+	int port = signal == IOEX_USB_C1_FAULT_ODL ? 1 : 0;
 
-	return rv;
+	CPRINTSUSB("C%d: SBU fault", port);
+	pd_handle_overcurrent(port);
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void usb_fault_interrupt(enum gpio_signal signal)
 {
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
+	int out;
+
+	CPRINTSUSB("USB fault(%d), alerting the SoC", signal);
+	out = gpio_pin_get_dt(
+		      GPIO_DT_FROM_NODELABEL(gpio_usb_hub_fault_q_odl)) &&
+	      gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(ioex_usb_a0_fault_odl)) &&
+	      gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(ioex_usb_a1_fault_db_odl));
+
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_fault_odl), out);
 }
 
-/* TODO: sbu_fault_interrupt from io expander */
+void usb_pd_soc_interrupt(enum gpio_signal signal)
+{
+	/*
+	 * This interrupt is unexpected with our use of the SoC mux, so just log
+	 * it as a point of interest.
+	 */
+	CPRINTSUSB("SOC PD Interrupt");
+}
 
 /* Round up 3250 max current to multiple of 128mA for ISL9241 AC prochot. */
 #define SKYRIM_AC_PROCHOT_CURRENT_MA 3328
@@ -462,7 +284,6 @@ static void reset_nct38xx_port(int port)
 	gpio_reset_port(ioex_port1);
 }
 
-
 void board_reset_pd_mcu(void)
 {
 	/* Reset TCPC0 */
@@ -481,38 +302,22 @@ uint16_t tcpc_get_alert_status(void)
 	 * its reset line active.
 	 */
 	if (!gpio_pin_get_dt(
-	     GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_int_odl))) {
-		if (gpio_pin_get_dt(
-		    GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_rst_l)) != 0)
+		    GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_int_odl))) {
+		if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(
+			    gpio_usb_c0_tcpc_rst_l)) != 0)
 			status |= PD_STATUS_TCPC_ALERT_0;
 	}
 
 	if (!gpio_pin_get_dt(
-	     GPIO_DT_FROM_NODELABEL(gpio_usb_c1_tcpc_int_odl))) {
-		if (gpio_pin_get_dt(
-		    GPIO_DT_FROM_NODELABEL(gpio_usb_c1_tcpc_rst_l)) != 0)
+		    GPIO_DT_FROM_NODELABEL(gpio_usb_c1_tcpc_int_odl))) {
+		if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(
+			    gpio_usb_c1_tcpc_rst_l)) != 0)
 			status |= PD_STATUS_TCPC_ALERT_1;
 	}
 
 	return status;
 }
 
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		aoz1380_interrupt(USBC_PORT_C0);
-		break;
-
-	case GPIO_USB_C1_PPC_INT_ODL:
-		nx20p348x_interrupt(USBC_PORT_C1);
-		break;
-
-	default:
-		break;
-	}
-}
-
 void bc12_interrupt(enum gpio_signal signal)
 {
 	switch (signal) {
diff --git a/zephyr/projects/skyrim/src/winterhold/ppc_config.c b/zephyr/projects/skyrim/src/winterhold/ppc_config.c
new file mode 100644
index 0000000000..72ddb6ce6c
--- /dev/null
+++ b/zephyr/projects/skyrim/src/winterhold/ppc_config.c
@@ -0,0 +1,27 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Winterhold board-specific PPC code */
+
+#include <zephyr/drivers/gpio.h>
+
+#include "driver/ppc/nx20p348x.h"
+#include "usbc_ppc.h"
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		nx20p348x_interrupt(0);
+		break;
+
+	case GPIO_USB_C1_PPC_INT_ODL:
+		nx20p348x_interrupt(1);
+		break;
+
+	default:
+		break;
+	}
+}
diff --git a/zephyr/projects/skyrim/src/winterhold/usb_mux_config.c b/zephyr/projects/skyrim/src/winterhold/usb_mux_config.c
new file mode 100644
index 0000000000..ca7b604d10
--- /dev/null
+++ b/zephyr/projects/skyrim/src/winterhold/usb_mux_config.c
@@ -0,0 +1,142 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Winterhold board-specific USB-C mux configuration */
+
+#include <zephyr/drivers/gpio.h>
+
+#include "console.h"
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+#include "driver/retimer/anx7483_public.h"
+#include "hooks.h"
+#include "ioexpander.h"
+#include "usb_mux.h"
+#include "usbc/usb_muxes.h"
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/*
+ * USB C0 (general) and C1 (just ANX DB) use IOEX pins to
+ * indicate flipped polarity to a protection switch.
+ */
+static int ioex_set_flip(int port, mux_state_t mux_state)
+{
+	if (port == 0) {
+		if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
+			gpio_pin_set_dt(
+				GPIO_DT_FROM_NODELABEL(ioex_usb_c0_sbu_flip),
+				1);
+		else
+			gpio_pin_set_dt(
+				GPIO_DT_FROM_NODELABEL(ioex_usb_c0_sbu_flip),
+				0);
+	} else {
+		if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
+			gpio_pin_set_dt(
+				GPIO_DT_FROM_NODELABEL(ioex_usb_c1_sbu_flip),
+				1);
+		else
+			gpio_pin_set_dt(
+				GPIO_DT_FROM_NODELABEL(ioex_usb_c1_sbu_flip),
+				0);
+	}
+
+	return EC_SUCCESS;
+}
+
+int board_anx7483_c0_mux_set(const struct usb_mux *me, mux_state_t mux_state)
+{
+	/* Set the SBU polarity mux */
+	RETURN_ERROR(ioex_set_flip(me->usb_port, mux_state));
+
+	return anx7483_set_default_tuning(me, mux_state);
+}
+
+int board_anx7483_c1_mux_set(const struct usb_mux *me, mux_state_t mux_state)
+{
+	bool flipped = mux_state & USB_PD_MUX_POLARITY_INVERTED;
+
+	/* Set the SBU polarity mux */
+	RETURN_ERROR(ioex_set_flip(me->usb_port, mux_state));
+
+	/* Remove flipped from the state for easier compraisons */
+	mux_state = mux_state & ~USB_PD_MUX_POLARITY_INVERTED;
+
+	RETURN_ERROR(anx7483_set_default_tuning(me, mux_state));
+
+	if (mux_state == USB_PD_MUX_USB_ENABLED) {
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX1,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX2,
+					    ANX7483_EQ_SETTING_12_5DB));
+	} else if (mux_state == USB_PD_MUX_DP_ENABLED) {
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX1,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX2,
+					    ANX7483_EQ_SETTING_12_5DB));
+	} else if (mux_state == USB_PD_MUX_DOCK && !flipped) {
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX1,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX2,
+					    ANX7483_EQ_SETTING_12_5DB));
+	} else if (mux_state == USB_PD_MUX_DOCK && flipped) {
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX1,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_URX2,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_UTX1,
+					    ANX7483_EQ_SETTING_12_5DB));
+		RETURN_ERROR(anx7483_set_eq(me, ANX7483_PIN_DRX2,
+					    ANX7483_EQ_SETTING_12_5DB));
+	}
+
+	return EC_SUCCESS;
+}
+
+int board_c1_ps8818_mux_set(const struct usb_mux *me, mux_state_t mux_state)
+{
+	CPRINTSUSB("C1: PS8818 mux using default tuning");
+
+	/* Once a DP connection is established, we need to set IN_HPD */
+	if (mux_state & USB_PD_MUX_DP_ENABLED)
+		ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 1);
+	else
+		ioex_set_level(IOEX_USB_C1_HPD_IN_DB, 0);
+
+	return 0;
+}
+
+static void setup_mux(void)
+{
+	uint32_t val;
+
+	if (cros_cbi_get_fw_config(FW_IO_DB, &val) != 0)
+		CPRINTSUSB("Error finding FW_DB_IO in CBI FW_CONFIG");
+	/* Val will have our dts default on error, so continue setup */
+
+	if (val == FW_IO_DB_PS8811_PS8818) {
+		CPRINTSUSB("C1: Setting PS8818 mux");
+		USB_MUX_ENABLE_ALTERNATIVE(usb_mux_chain_ps8818_port1);
+	} else if (val == FW_IO_DB_NONE_ANX7483) {
+		CPRINTSUSB("C1: Setting ANX7483 mux");
+	} else {
+		CPRINTSUSB("Unexpected DB_IO board: %d", val);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, setup_mux, HOOK_PRIO_INIT_I2C);
diff --git a/zephyr/projects/skyrim/usbc.dts b/zephyr/projects/skyrim/usbc.dts
index c7e85ceb5f..8486927e8d 100644
--- a/zephyr/projects/skyrim/usbc.dts
+++ b/zephyr/projects/skyrim/usbc.dts
@@ -1,56 +1,26 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
- #include <dt-bindings/usb_pd_tcpm.h>
-
 / {
 	usbc {
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		port0@0 {
+		usbc_port0: port0@0 {
 			compatible = "named-usbc-port";
 			reg = <0>;
-			bc12 {
-				compatible = "pericom,pi3usb9201";
-				status = "okay";
-				irq = <&int_usb_c0_bc12>;
-				port = <&i2c_tcpc0>;
-				i2c-addr-flags = "PI3USB9201_I2C_ADDR_3_FLAGS";
-			};
-			tcpc {
-				compatible = "nuvoton,nct38xx";
-				gpio-dev = <&nct3807_C0>;
-				port = <&i2c_tcpc0>;
-				i2c-addr-flags = "NCT38XX_I2C_ADDR1_1_FLAGS";
-				tcpc-flags = <(TCPC_FLAGS_TCPCI_REV2_0)>;
-			};
-			chg {
-				compatible = "intersil,isl9241";
-				status = "okay";
-				port = <&i2c_charger>;
-			};
+			bc12 = <&bc12_port0>;
+			tcpc = <&tcpc_port0>;
+			chg = <&charger>;
 		};
 
-		port1@1 {
+		usbc_port1: port1@1 {
 			compatible = "named-usbc-port";
 			reg = <1>;
-			bc12 {
-				compatible = "pericom,pi3usb9201";
-				status = "okay";
-				irq = <&int_usb_c1_bc12>;
-				port = <&i2c_tcpc1>;
-				i2c-addr-flags = "PI3USB9201_I2C_ADDR_3_FLAGS";
-			};
-			tcpc {
-				compatible = "nuvoton,nct38xx";
-				gpio-dev = <&nct3807_C1>;
-				port = <&i2c_tcpc1>;
-				i2c-addr-flags = "NCT38XX_I2C_ADDR1_1_FLAGS";
-				tcpc-flags = <(TCPC_FLAGS_TCPCI_REV2_0)>;
-			};
+			bc12 = <&bc12_port1>;
+			tcpc = <&tcpc_port1>;
 		};
 	};
 };
diff --git a/zephyr/projects/skyrim/usbc_config_guybrush.c b/zephyr/projects/skyrim/usbc_config_guybrush.c
deleted file mode 100644
index 1d7afcbbb4..0000000000
--- a/zephyr/projects/skyrim/usbc_config_guybrush.c
+++ /dev/null
@@ -1,611 +0,0 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Guybrush family-specific USB-C configuration */
-
-#include "cros_board_info.h"
-#include "battery_fuel_gauge.h"
-#include "charge_manager.h"
-#include "charge_ramp.h"
-#include "charge_state_v2.h"
-#include "charge_state.h"
-#include "charger.h"
-#include "driver/bc12/pi3usb9201.h"
-#include "driver/charger/isl9241.h"
-#include "driver/ppc/aoz1380.h"
-#include "driver/ppc/nx20p348x.h"
-#include "driver/retimer/anx7491.h"
-#include "driver/retimer/ps8811.h"
-#include "driver/retimer/ps8818.h"
-#include "driver/tcpm/nct38xx.h"
-#include "driver/usb_mux/anx7451.h"
-#include "driver/usb_mux/amd_fp6.h"
-#include "gpio.h"
-#include "gpio/gpio_int.h"
-#include "hooks.h"
-#include "ioexpander.h"
-#include "power.h"
-#include "usb_mux.h"
-#include "usb_pd_tcpm.h"
-#include "usbc_ppc.h"
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-/* USB-A ports */
-enum usba_port {
-	USBA_PORT_A0 = 0,
-	USBA_PORT_A1,
-	USBA_PORT_COUNT
-};
-
-/* USB-C ports */
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
-BUILD_ASSERT(USBC_PORT_COUNT == CONFIG_USB_PD_PORT_MAX_COUNT);
-
-static void reset_nct38xx_port(int port);
-
-static void usbc_interrupt_init(void)
-{
-	/* Enable PPC interrupts. */
-	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_ppc));
-	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_ppc));
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_tcpc));
-	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_tcpc));
-
-	/* Enable BC 1.2 interrupts */
-	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_bc12));
-	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_bc12));
-
-	/* TODO: Enable SBU fault interrupts (io expander )*/
-}
-DECLARE_HOOK(HOOK_INIT, usbc_interrupt_init, HOOK_PRIO_POST_I2C);
-
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		/* Device does not talk I2C */
-		.drv = &aoz1380_drv
-	},
-
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = NX20P3483_ADDR1_FLAGS,
-		.drv = &nx20p348x_drv
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == CONFIG_USB_PD_PORT_MAX_COUNT);
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-/*
- * .init is not necessary here because it has nothing
- * to do. Primary mux will handle mux state so .get is
- * not needed as well. usb_mux.c can handle the situation
- * properly.
- */
-static int fsusb42umx_set_mux(const struct usb_mux*, mux_state_t, bool *);
-struct usb_mux_driver usbc0_sbu_mux_driver = {
-	.set = fsusb42umx_set_mux,
-};
-
-/*
- * Since FSUSB42UMX is not a i2c device, .i2c_port and
- * .i2c_addr_flags are not required here.
- */
-struct usb_mux usbc0_sbu_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &usbc0_sbu_mux_driver,
-};
-
-__overridable int board_c1_ps8818_mux_set(const struct usb_mux *me,
-					  mux_state_t mux_state)
-{
-	CPRINTSUSB("C1: PS8818 mux using default tuning");
-	return 0;
-}
-
-struct usb_mux usbc1_ps8818 = {
-	.usb_port = USBC_PORT_C1,
-	.i2c_port = I2C_PORT_TCPC1,
-	.flags = USB_MUX_FLAG_RESETS_IN_G3,
-	.i2c_addr_flags = PS8818_I2C_ADDR_FLAGS,
-	.driver = &ps8818_usb_retimer_driver,
-	.board_set = &board_c1_ps8818_mux_set,
-};
-
-/*
- * ANX7491(A1) and ANX7451(C1) are on the same i2c bus. Both default
- * to 0x29 for the USB i2c address. This moves ANX7451(C1) USB i2c
- * address to 0x2A. ANX7491(A1) will stay at the default 0x29.
- */
-uint16_t board_anx7451_get_usb_i2c_addr(const struct usb_mux *me)
-{
-	ASSERT(me->usb_port == USBC_PORT_C1);
-	return 0x2a;
-}
-
-__overridable int board_c1_anx7451_mux_set(const struct usb_mux *me,
-					   mux_state_t mux_state)
-{
-	CPRINTSUSB("C1: ANX7451 mux using default tuning");
-	return 0;
-}
-
-struct usb_mux usbc1_anx7451 = {
-	.usb_port = USBC_PORT_C1,
-	.i2c_port = I2C_PORT_TCPC1,
-	.flags = USB_MUX_FLAG_RESETS_IN_G3,
-	.i2c_addr_flags = ANX7491_I2C_ADDR3_FLAGS,
-	.driver = &anx7451_usb_mux_driver,
-	.board_set = &board_c1_anx7451_mux_set,
-};
-
-struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = AMD_FP6_C0_MUX_I2C_ADDR,
-		.driver = &amd_fp6_usb_mux_driver,
-		.next_mux = &usbc0_sbu_mux,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = AMD_FP6_C4_MUX_I2C_ADDR,
-		.driver = &amd_fp6_usb_mux_driver,
-		/* .next_mux = filled in by setup_mux based on fw_config */
-	}
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == CONFIG_USB_PD_PORT_MAX_COUNT);
-
-/*
- * USB C0 port SBU mux use standalone FSUSB42UMX
- * chip and it needs a board specific driver.
- * Overall, it will use chained mux framework.
- */
-static int fsusb42umx_set_mux(const struct usb_mux *me, mux_state_t mux_state,
-			      bool *ack_required)
-{
-	/* This driver does not use host command ACKs */
-	*ack_required = false;
-
-	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-		ioex_set_level(IOEX_USB_C0_SBU_FLIP, 1);
-	else
-		ioex_set_level(IOEX_USB_C0_SBU_FLIP, 0);
-
-	return EC_SUCCESS;
-}
-
-static void setup_mux(void)
-{
-	/* TODO: Fill in C1 mux based on CBI */
-	CPRINTSUSB("C1: Setting ANX7451 mux");
-	usb_muxes[USBC_PORT_C1].next_mux = &usbc1_anx7451;
-}
-DECLARE_HOOK(HOOK_INIT, setup_mux, HOOK_PRIO_INIT_I2C);
-
-int board_set_active_charge_port(int port)
-{
-	int is_valid_port = (port >= 0 &&
-			     port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	int i;
-	int rv;
-
-	if (port == CHARGE_PORT_NONE) {
-		CPRINTSUSB("Disabling all charger ports");
-
-		/* Disable all ports. */
-		for (i = 0; i < ppc_cnt; i++) {
-			/*
-			 * If this port had booted in dead battery mode, go
-			 * ahead and reset it so EN_SNK responds properly.
-			 */
-			if (nct38xx_get_boot_type(i) ==
-						NCT38XX_BOOT_DEAD_BATTERY) {
-				reset_nct38xx_port(i);
-				pd_set_error_recovery(i);
-			}
-
-			/*
-			 * Do not return early if one fails otherwise we can
-			 * get into a boot loop assertion failure.
-			 */
-			if (ppc_vbus_sink_enable(i, 0))
-				CPRINTSUSB("Disabling C%d as sink failed.", i);
-		}
-
-		return EC_SUCCESS;
-	} else if (!is_valid_port) {
-		return EC_ERROR_INVAL;
-	}
-
-	/*
-	 * Check if we can reset any ports in dead battery mode
-	 *
-	 * The NCT3807 may continue to keep EN_SNK low on the dead battery port
-	 * and allow a dangerous level of voltage to pass through to the initial
-	 * charge port (see b/183660105).  We must reset the ports if we have
-	 * sufficient battery to do so, which will bring EN_SNK back under
-	 * normal control.
-	 */
-	rv = EC_SUCCESS;
-	for (i = 0; i < board_get_usb_pd_port_count(); i++) {
-		if (nct38xx_get_boot_type(i) == NCT38XX_BOOT_DEAD_BATTERY) {
-			CPRINTSUSB("Found dead battery on %d", i);
-			/*
-			 * If we have battery, get this port reset ASAP.
-			 * This means temporarily rejecting charge manager
-			 * sets to it.
-			 */
-			if (pd_is_battery_capable()) {
-				reset_nct38xx_port(i);
-				pd_set_error_recovery(i);
-
-				if (port == i)
-					rv = EC_ERROR_INVAL;
-			} else if (port != i) {
-				/*
-				 * If other port is selected and in dead battery
-				 * mode, reset this port.  Otherwise, reject
-				 * change because we'll brown out.
-				 */
-				if (nct38xx_get_boot_type(port) ==
-						NCT38XX_BOOT_DEAD_BATTERY) {
-					reset_nct38xx_port(i);
-					pd_set_error_recovery(i);
-				} else {
-					rv = EC_ERROR_INVAL;
-				}
-			}
-		}
-	}
-
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	/* Check if the port is sourcing VBUS. */
-	if (tcpm_get_src_ctrl(port)) {
-		CPRINTSUSB("Skip enable C%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	CPRINTSUSB("New charge port: C%d", port);
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < ppc_cnt; i++) {
-		if (i == port)
-			continue;
-
-		if (ppc_vbus_sink_enable(i, 0))
-			CPRINTSUSB("C%d: sink path disable failed.", i);
-	}
-
-	/* Enable requested charge port. */
-	if (ppc_vbus_sink_enable(port, 1)) {
-		CPRINTSUSB("C%d: sink path enable failed.", port);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-/*
- * In the AOZ1380 PPC, there are no programmable features.  We use
- * the attached NCT3807 to control a GPIO to indicate 1A5 or 3A0
- * current limits.
- */
-int board_aoz1380_set_vbus_source_current_limit(int port,
-						enum tcpc_rp_value rp)
-{
-	int rv = EC_SUCCESS;
-
-	rv = ioex_set_level(IOEX_USB_C0_PPC_ILIM_3A_EN,
-			    (rp == TYPEC_RP_3A0) ? 1 : 0);
-
-	return rv;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
-}
-
-/* TODO: sbu_fault_interrupt from io expander */
-
-/* Round up 3250 max current to multiple of 128mA for ISL9241 AC prochot. */
-#define GUYBRUSH_AC_PROCHOT_CURRENT_MA 3328
-static void set_ac_prochot(void)
-{
-	isl9241_set_ac_prochot(CHARGER_SOLO, GUYBRUSH_AC_PROCHOT_CURRENT_MA);
-}
-DECLARE_HOOK(HOOK_INIT, set_ac_prochot, HOOK_PRIO_DEFAULT);
-
-void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port;
-
-	switch (signal) {
-	case GPIO_USB_C0_TCPC_INT_ODL:
-		port = 0;
-		break;
-	case GPIO_USB_C1_TCPC_INT_ODL:
-		port = 1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-static void reset_nct38xx_port(int port)
-{
-	const struct gpio_dt_spec *reset_gpio_l;
-
-	/* TODO: Save and restore ioex signals */
-	if (port == USBC_PORT_C0)
-		reset_gpio_l = GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_rst_l);
-	else if (port == USBC_PORT_C1)
-		reset_gpio_l = GPIO_DT_FROM_NODELABEL(gpio_usb_c1_tcpc_rst_l);
-	else
-		/* Invalid port: do nothing */
-		return;
-
-	gpio_pin_set_dt(reset_gpio_l, 0);
-	msleep(NCT38XX_RESET_HOLD_DELAY_MS);
-	gpio_pin_set_dt(reset_gpio_l, 1);
-	nct38xx_reset_notify(port);
-	if (NCT3807_RESET_POST_DELAY_MS != 0)
-		msleep(NCT3807_RESET_POST_DELAY_MS);
-}
-
-
-void board_reset_pd_mcu(void)
-{
-	/* Reset TCPC0 */
-	reset_nct38xx_port(USBC_PORT_C0);
-
-	/* Reset TCPC1 */
-	reset_nct38xx_port(USBC_PORT_C1);
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	/*
-	 * Check which port has the ALERT line set and ignore if that TCPC has
-	 * its reset line active.
-	 */
-	if (!gpio_pin_get_dt(
-	     GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_int_odl))) {
-		if (gpio_pin_get_dt(
-		    GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_rst_l)) != 0)
-			status |= PD_STATUS_TCPC_ALERT_0;
-	}
-
-	if (!gpio_pin_get_dt(
-	     GPIO_DT_FROM_NODELABEL(gpio_usb_c1_tcpc_int_odl))) {
-		if (gpio_pin_get_dt(
-		    GPIO_DT_FROM_NODELABEL(gpio_usb_c1_tcpc_rst_l)) != 0)
-			status |= PD_STATUS_TCPC_ALERT_1;
-	}
-
-	return status;
-}
-
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		aoz1380_interrupt(USBC_PORT_C0);
-		break;
-
-	case GPIO_USB_C1_PPC_INT_ODL:
-		nx20p348x_interrupt(USBC_PORT_C1);
-		break;
-
-	default:
-		break;
-	}
-}
-
-void bc12_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_BC12_INT_ODL:
-		usb_charger_task_set_event(0, USB_CHG_EVENT_BC12);
-		break;
-
-	case GPIO_USB_C1_BC12_INT_ODL:
-		usb_charger_task_set_event(1, USB_CHG_EVENT_BC12);
-		break;
-
-	default:
-		break;
-	}
-}
-
-/**
- * Return if VBUS is sagging too low
- *
- * For legacy BC1.2 charging with CONFIG_CHARGE_RAMP_SW, ramp up input current
- * until voltage drops to 4.5V. Don't go lower than this to be kind to the
- * charger (see b/67964166).
- */
-#define BC12_MIN_VOLTAGE 4500
-int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
-{
-	int voltage = 0;
-	int rv;
-
-	rv = charger_get_vbus_voltage(port, &voltage);
-
-	if (rv) {
-		CPRINTSUSB("%s rv=%d", __func__, rv);
-		return 0;
-	}
-
-	/*
-	 * b/168569046: The ISL9241 sometimes incorrectly reports 0 for unknown
-	 * reason, causing ramp to stop at 0.5A. Workaround this by ignoring 0.
-	 * This partly defeats the point of ramping, but will still catch
-	 * VBUS below 4.5V and above 0V.
-	 */
-	if (voltage == 0) {
-		CPRINTSUSB("%s vbus=0", __func__);
-		return 0;
-	}
-
-	if (voltage < BC12_MIN_VOLTAGE)
-		CPRINTSUSB("%s vbus=%d", __func__, voltage);
-
-	return voltage < BC12_MIN_VOLTAGE;
-}
-
-#define SAFE_RESET_VBUS_DELAY_MS 900
-#define SAFE_RESET_VBUS_MV 5000
-void board_hibernate(void)
-{
-	int port;
-	enum ec_error_list ret;
-
-	/*
-	 * If we are charging, then drop the Vbus level down to 5V to ensure
-	 * that we don't get locked out of the 6.8V OVLO for our PPCs in
-	 * dead-battery mode. This is needed when the TCPC/PPC rails go away.
-	 * (b/79218851, b/143778351, b/147007265)
-	 */
-	port = charge_manager_get_active_charge_port();
-	if (port != CHARGE_PORT_NONE) {
-		pd_request_source_voltage(port, SAFE_RESET_VBUS_MV);
-
-		/* Give PD task and PPC chip time to get to 5V */
-		msleep(SAFE_RESET_VBUS_DELAY_MS);
-	}
-
-	/* Try to put our battery fuel gauge into sleep mode */
-	ret = battery_sleep_fuel_gauge();
-	if ((ret != EC_SUCCESS) && (ret != EC_ERROR_UNIMPLEMENTED))
-		cprints(CC_SYSTEM, "Failed to send battery sleep command");
-}
-
-__overridable enum ec_error_list
-board_a1_ps8811_retimer_init(const struct usb_mux *me)
-{
-	return EC_SUCCESS;
-}
-
-static int baseboard_a1_ps8811_retimer_init(const struct usb_mux *me)
-{
-	int rv;
-	int tries = 2;
-
-	do {
-		int val;
-
-		rv = ps8811_i2c_read(me, PS8811_REG_PAGE1,
-				     PS8811_REG1_USB_BEQ_LEVEL, &val);
-	} while (rv && --tries);
-
-	if (rv) {
-		CPRINTSUSB("A1: PS8811 retimer not detected!");
-		return rv;
-	}
-	CPRINTSUSB("A1: PS8811 retimer detected");
-	rv = board_a1_ps8811_retimer_init(me);
-	if (rv)
-		CPRINTSUSB("A1: Error during PS8811 setup rv:%d", rv);
-	return rv;
-}
-
-/*
- * PS8811 is just a type-A USB retimer, reusing mux structure for
- * convenience.
- */
-const struct usb_mux usba1_ps8811 = {
-	.usb_port = USBA_PORT_A1,
-	.i2c_port = I2C_PORT_TCPC1,
-	.i2c_addr_flags = PS8811_I2C_ADDR_FLAGS3,
-	.board_init = &baseboard_a1_ps8811_retimer_init,
-};
-
-__overridable enum ec_error_list
-board_a1_anx7491_retimer_init(const struct usb_mux *me)
-{
-	return EC_SUCCESS;
-}
-
-static int baseboard_a1_anx7491_retimer_init(const struct usb_mux *me)
-{
-	int rv;
-	int tries = 2;
-
-	do {
-		int val;
-
-		rv = i2c_read8(me->i2c_port, me->i2c_addr_flags, 0, &val);
-	} while (rv && --tries);
-	if (rv) {
-		CPRINTSUSB("A1: ANX7491 retimer not detected!");
-		return rv;
-	}
-	CPRINTSUSB("A1: ANX7491 retimer detected");
-	rv = board_a1_anx7491_retimer_init(me);
-	if (rv)
-		CPRINTSUSB("A1: Error during ANX7491 setup rv:%d", rv);
-	return rv;
-}
-
-/*
- * ANX7491 is just a type-A USB retimer, reusing mux structure for
- * convenience.
- */
-const struct usb_mux usba1_anx7491 = {
-	.usb_port = USBA_PORT_A1,
-	.i2c_port = I2C_PORT_TCPC1,
-	.i2c_addr_flags = ANX7491_I2C_ADDR0_FLAGS,
-	.board_init = &baseboard_a1_anx7491_retimer_init,
-};
-
-void baseboard_a1_retimer_setup(void)
-{
-	struct usb_mux a1_retimer;
-
-	/* TODO: Support PS8811 retimer through CBI */
-	a1_retimer = usba1_anx7491;
-	a1_retimer.board_init(&a1_retimer);
-}
-DECLARE_DEFERRED(baseboard_a1_retimer_setup);
-
-/* TODO: Remove when guybrush is no longer supported */
-#ifdef CONFIG_BOARD_GUYBRUSH
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	switch (port) {
-	case USBC_PORT_C0:
-	case USBC_PORT_C1:
-		gpio_pin_set_dt(
-			GPIO_DT_FROM_NODELABEL(gpio_usb_c0_c1_fault_odl),
-			!is_overcurrented);
-		break;
-
-	default:
-		break;
-	}
-}
-#endif
diff --git a/zephyr/projects/skyrim/winterhold.dts b/zephyr/projects/skyrim/winterhold.dts
new file mode 100644
index 0000000000..1b2a89999f
--- /dev/null
+++ b/zephyr/projects/skyrim/winterhold.dts
@@ -0,0 +1,169 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/usbc_mux.h>
+
+#include "i2c_common.dtsi"
+
+/ {
+	named-gpios {
+		/* Winterhold-specific GPIO customizations */
+	};
+
+	named-temp-sensors {
+		compatible = "cros-ec,temp-sensors";
+		soc-pct2075 {
+			temp_host_high = <100>;
+			temp_host_halt = <105>;
+			temp_host_release_high = <80>;
+			temp_host_release_halt = <80>;
+			temp_fan_off = <0>;
+			temp_fan_max = <70>;
+			power-good-pin = <&gpio_pg_pwr_s5>;
+			sensor = <&soc_pct2075>;
+		};
+		amb-pct2075 {
+			power-good-pin = <&gpio_pg_pwr_s5>;
+			sensor = <&amb_pct2075>;
+		};
+	};
+
+	/*
+	 * Note this is expected to vary per-board, so we keep it in the board
+	 * dts files.
+	 */
+	Winterhold-fw-config {
+		compatible = "cros-ec,cbi-fw-config";
+
+		form-factor {
+			enum-name = "FW_FORM_FACTOR";
+			start = <0>;
+			size = <1>;
+
+			ff-clamshell {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FF_CLAMSHELL";
+				value = <0>;
+			};
+			ff-convertible {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FF_CONVERTIBLE";
+				value = <1>;
+				default;
+			};
+		};
+		io-db {
+			enum-name = "FW_IO_DB";
+			start = <6>;
+			size = <2>;
+
+			io-db-ps8811-ps8818 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_IO_DB_PS8811_PS8818";
+				value = <0>;
+			};
+			io-db-none-anx7483 {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_IO_DB_NONE_ANX7483";
+				value = <1>;
+				default;
+			};
+		};
+
+		/*
+		 * FW_CONFIG field to enable fan or not.
+		 */
+		fan {
+			enum-name = "FW_FAN";
+			start = <10>;
+			size = <1>;
+
+			no-fan {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FAN_NOT_PRESENT";
+				value = <0>;
+			};
+			fan-present {
+				compatible = "cros-ec,cbi-fw-config-value";
+				enum-name = "FW_FAN_PRESENT";
+				value = <1>;
+				/*
+				 * Set as default so that unprovisioned
+				 * configs will run the fan regardless.
+				 */
+				default;
+			};
+		};
+	};
+
+	/* Rotation matrices for motion sensors. */
+	motionsense-rotation-ref {
+		compatible = "cros-ec,motionsense-rotation-ref";
+		lid_rot_ref: lid-rotation-ref {
+			mat33 = <0 (-1) 0
+				 1 0 0
+				 0 0 1>;
+		};
+
+		base_rot_ref: base-rotation-ref {
+			mat33 = <0 1 0
+				 (-1) 0 0
+				 0 0 1>;
+		};
+	};
+};
+
+&i2c0_0 {
+	anx7483_port0: anx7483@3e {
+		compatible = "analogix,anx7483";
+		reg = <0x3e>;
+		board-set = "board_anx7483_c0_mux_set";
+	};
+	ppc_port0: nx20p348x@71 {
+		compatible = "nxp,nx20p348x";
+		status = "okay";
+		reg = <0x71>;
+	};
+};
+
+&i2c1_0 {
+	anx7483_port1: anx7483@3e {
+		compatible = "analogix,anx7483";
+		reg = <0x3e>;
+		board-set = "board_anx7483_c1_mux_set";
+	};
+	ppc_port1: nx20p348x@71 {
+		compatible = "nxp,nx20p348x";
+		status = "okay";
+		reg = <0x71>;
+	};
+	ps8818_port1: ps8818@28 {
+		compatible = "parade,ps8818";
+		reg = <0x28>;
+		flags = <(USB_MUX_FLAG_RESETS_IN_G3)>;
+		board-set = "board_c1_ps8818_mux_set";
+	};
+};
+
+&usbc_port0 {
+	ppc = <&ppc_port0>;
+	usb-mux-chain-0 {
+		compatible = "cros-ec,usb-mux-chain";
+		usb-muxes = <&amd_fp6_port0 &anx7483_port0>;
+	};
+};
+
+&usbc_port1 {
+	ppc = <&ppc_port1>;
+	usb-mux-chain-1-anx {
+		compatible = "cros-ec,usb-mux-chain";
+		usb-muxes = <&amd_fp6_port1 &anx7483_port1>;
+	};
+	usb_mux_chain_ps8818_port1: usb-mux-chain-1-ps {
+		compatible = "cros-ec,usb-mux-chain";
+		usb-muxes = <&amd_fp6_port1 &ps8818_port1>;
+		alternative-chain;
+	};
+};
diff --git a/zephyr/projects/trogdor/lazor/BUILD.py b/zephyr/projects/trogdor/lazor/BUILD.py
index 8e7936f12f..ca1a26bdcf 100644
--- a/zephyr/projects/trogdor/lazor/BUILD.py
+++ b/zephyr/projects/trogdor/lazor/BUILD.py
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/projects/trogdor/lazor/CMakeLists.txt b/zephyr/projects/trogdor/lazor/CMakeLists.txt
index 47285c66eb..b6d5024707 100644
--- a/zephyr/projects/trogdor/lazor/CMakeLists.txt
+++ b/zephyr/projects/trogdor/lazor/CMakeLists.txt
@@ -1,10 +1,10 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 cmake_minimum_required(VERSION 3.13.1)
 
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
 project(lazor)
 
 cros_ec_library_include_directories(include)
diff --git a/zephyr/projects/trogdor/lazor/adc.dts b/zephyr/projects/trogdor/lazor/adc.dts
index 6f0208a1bd..b834001587 100644
--- a/zephyr/projects/trogdor/lazor/adc.dts
+++ b/zephyr/projects/trogdor/lazor/adc.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,14 +10,12 @@
 		compatible = "named-adc-channels";
 
 		vbus {
-			label = "VBUS";
 			enum-name = "ADC_VBUS";
 			io-channels = <&adc0 1>;
 			/* Measure VBUS through a 1/10 voltage divider */
 			mul = <10>;
 		};
 		amon_bmon {
-			label = "AMON_BMON";
 			enum-name = "ADC_AMON_BMON";
 			io-channels = <&adc0 2>;
 			/*
@@ -29,7 +27,6 @@
 			div = <18>;
 		};
 		psys {
-			label = "PSYS";
 			enum-name = "ADC_PSYS";
 			io-channels = <&adc0 3>;
 			/*
diff --git a/zephyr/projects/trogdor/lazor/battery.dts b/zephyr/projects/trogdor/lazor/battery.dts
index 0fbb1bf359..2b17dd4761 100644
--- a/zephyr/projects/trogdor/lazor/battery.dts
+++ b/zephyr/projects/trogdor/lazor/battery.dts
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/trogdor/lazor/default_gpio_pinctrl.dts b/zephyr/projects/trogdor/lazor/default_gpio_pinctrl.dts
index 64da26a672..1819bdbc3e 100644
--- a/zephyr/projects/trogdor/lazor/default_gpio_pinctrl.dts
+++ b/zephyr/projects/trogdor/lazor/default_gpio_pinctrl.dts
@@ -1,43 +1,43 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* Adds the &alt1_no_lpc_espi setting over the NPCX7 default setting. */
 &{/def-io-conf-list} {
-	pinctrl-0 = <&alt0_gpio_no_spip
-		   &alt0_gpio_no_fpip
-		   &alt1_no_pwrgd
-		   &alt1_no_lpc_espi
-		   &alta_no_peci_en
-		   &altd_npsl_in1_sl
-		   &altd_npsl_in2_sl
-		   &altd_psl_in3_sl
-		   &altd_psl_in4_sl
-		   &alt7_no_ksi0_sl
-		   &alt7_no_ksi1_sl
-		   &alt7_no_ksi2_sl
-		   &alt7_no_ksi3_sl
-		   &alt7_no_ksi4_sl
-		   &alt7_no_ksi5_sl
-		   &alt7_no_ksi6_sl
-		   &alt7_no_ksi7_sl
-		   &alt8_no_kso00_sl
-		   &alt8_no_kso01_sl
-		   &alt8_no_kso02_sl
-		   &alt8_no_kso03_sl
-		   &alt8_no_kso04_sl
-		   &alt8_no_kso05_sl
-		   &alt8_no_kso06_sl
-		   &alt8_no_kso07_sl
-		   &alt9_no_kso08_sl
-		   &alt9_no_kso09_sl
-		   &alt9_no_kso10_sl
-		   &alt9_no_kso11_sl
-		   &alt9_no_kso12_sl
-		   &alt9_no_kso13_sl
-		   &alt9_no_kso14_sl
-		   &alt9_no_kso15_sl
-		   &alta_no_kso16_sl
-		   &alta_no_kso17_sl >;
+	pinmux = <&alt0_gpio_no_spip
+		  &alt0_gpio_no_fpip
+		  &alt1_no_pwrgd
+		  &alt1_no_lpc_espi
+		  &alta_no_peci_en
+		  &altd_npsl_in1_sl
+		  &altd_npsl_in2_sl
+		  &altd_psl_in3_sl
+		  &altd_psl_in4_sl
+		  &alt7_no_ksi0_sl
+		  &alt7_no_ksi1_sl
+		  &alt7_no_ksi2_sl
+		  &alt7_no_ksi3_sl
+		  &alt7_no_ksi4_sl
+		  &alt7_no_ksi5_sl
+		  &alt7_no_ksi6_sl
+		  &alt7_no_ksi7_sl
+		  &alt8_no_kso00_sl
+		  &alt8_no_kso01_sl
+		  &alt8_no_kso02_sl
+		  &alt8_no_kso03_sl
+		  &alt8_no_kso04_sl
+		  &alt8_no_kso05_sl
+		  &alt8_no_kso06_sl
+		  &alt8_no_kso07_sl
+		  &alt9_no_kso08_sl
+		  &alt9_no_kso09_sl
+		  &alt9_no_kso10_sl
+		  &alt9_no_kso11_sl
+		  &alt9_no_kso12_sl
+		  &alt9_no_kso13_sl
+		  &alt9_no_kso14_sl
+		  &alt9_no_kso15_sl
+		  &alta_no_kso16_sl
+		  &alta_no_kso17_sl >;
 };
diff --git a/zephyr/projects/trogdor/lazor/display.dts b/zephyr/projects/trogdor/lazor/display.dts
index 6f28e7e81a..65d3a2d91b 100644
--- a/zephyr/projects/trogdor/lazor/display.dts
+++ b/zephyr/projects/trogdor/lazor/display.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,7 +7,6 @@
 	displight {
 		compatible = "cros-ec,displight";
 		pwms = <&pwm5 0 PWM_HZ(4800) PWM_POLARITY_NORMAL>;
-		frequency = <4800>;
 		generic-pwm-channel = <1>;
 	};
 };
diff --git a/zephyr/projects/trogdor/lazor/gpio.dts b/zephyr/projects/trogdor/lazor/gpio.dts
index 3a20dc865f..a047d7e2f2 100644
--- a/zephyr/projects/trogdor/lazor/gpio.dts
+++ b/zephyr/projects/trogdor/lazor/gpio.dts
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -67,7 +67,7 @@
 			enum-name = "GPIO_LID_OPEN";
 		};
 		gpio_ap_rst_l: ap_rst_l {
-			gpios = <&gpioc 1 GPIO_INPUT>;
+			gpios = <&gpioc 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
 			enum-name = "GPIO_AP_RST_L";
 		};
 		gpio_ps_hold: ps_hold {
@@ -79,7 +79,7 @@
 			enum-name = "GPIO_AP_SUSPEND";
 		};
 		gpio_deprecated_ap_rst_req: deprecated_ap_rst_req {
-			gpios = <&gpioc 2 GPIO_INPUT_PULL_DOWN>;
+			gpios = <&gpioc 2 (GPIO_INPUT_PULL_DOWN | GPIO_VOLTAGE_1P8)>;
 			enum-name = "GPIO_DEPRECATED_AP_RST_REQ";
 		};
 		gpio_power_good: power_good {
@@ -87,7 +87,7 @@
 			enum-name = "GPIO_POWER_GOOD";
 		};
 		gpio_warm_reset_l: warm_reset_l {
-			gpios = <&gpiof 4 GPIO_INPUT>;
+			gpios = <&gpiof 4 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
 			enum-name = "GPIO_WARM_RESET_L";
 		};
 		ap_ec_spi_cs_l {
@@ -219,6 +219,12 @@
 		arm_x86 {
 			gpios = <&gpio6 6 GPIO_OUTPUT_LOW>;
 		};
+		ec-i2c-sensor-scl {
+			gpios = <&gpiob 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
+		ec-i2c-sensor-sda {
+			gpios = <&gpiob 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
+		};
 		gpio_ec_kso_02_inv: ec_kso_02_inv {
 			gpios = <&gpio1 7 (GPIO_OUTPUT_LOW | GPIO_ACTIVE_LOW)>;
 		};
@@ -229,17 +235,6 @@
 		enable-pins = <&gpio_en_usb_a_5v>;
 	};
 
-	def-lvol-io-list {
-		compatible = "nuvoton,npcx-lvolctrl-def";
-		lvol-io-pads = <
-			&lvol_ioc1 /* AP_RST_L */
-			&lvol_ioc2 /* DEPRECATED_AP_RST_REQ */
-			&lvol_iof4 /* WARM_RESET_L */
-			&lvol_iob3 /* EC_I2C_SENSOR_SCL */
-			&lvol_iob2 /* EC_I2C_SENSOR_SDA */
-		>;
-	};
-
 	hibernate-wake-pins {
 		compatible = "cros-ec,hibernate-wake-pins";
 		wakeup-irqs = <
diff --git a/zephyr/projects/trogdor/lazor/gpio_led.dts b/zephyr/projects/trogdor/lazor/gpio_led.dts
index d85c6dd1df..c8c026506b 100644
--- a/zephyr/projects/trogdor/lazor/gpio_led.dts
+++ b/zephyr/projects/trogdor/lazor/gpio_led.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/trogdor/lazor/host_interface_npcx.dts b/zephyr/projects/trogdor/lazor/host_interface_npcx.dts
index 9c6a498940..14efa3c6b2 100644
--- a/zephyr/projects/trogdor/lazor/host_interface_npcx.dts
+++ b/zephyr/projects/trogdor/lazor/host_interface_npcx.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/trogdor/lazor/i2c.dts b/zephyr/projects/trogdor/lazor/i2c.dts
index aedc254105..e19ad224a9 100644
--- a/zephyr/projects/trogdor/lazor/i2c.dts
+++ b/zephyr/projects/trogdor/lazor/i2c.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,40 +9,28 @@
 
 		i2c_power: power {
 			i2c-port = <&i2c0_0>;
-			enum-name = "I2C_PORT_POWER";
-		};
-		battery {
-			i2c-port = <&i2c0_0>;
 			remote-port = <0>;
-			enum-name = "I2C_PORT_BATTERY";
-		};
-		virtual-battery {
-			i2c-port = <&i2c0_0>;
-			enum-name = "I2C_PORT_VIRTUAL_BATTERY";
-		};
-		i2c_charger: charger {
-			i2c-port = <&i2c0_0>;
-			enum-name = "I2C_PORT_CHARGER";
+			enum-names = "I2C_PORT_POWER",
+				"I2C_PORT_BATTERY",
+				"I2C_PORT_VIRTUAL_BATTERY",
+				"I2C_PORT_CHARGER";
 		};
 		i2c_tcpc0: tcpc0 {
 			i2c-port = <&i2c1_0>;
-			enum-name = "I2C_PORT_TCPC0";
+			enum-names = "I2C_PORT_TCPC0";
 		};
 		i2c_tcpc1: tcpc1 {
 			i2c-port = <&i2c2_0>;
-			enum-name = "I2C_PORT_TCPC1";
+			enum-names = "I2C_PORT_TCPC1";
 		};
 		i2c_eeprom: eeprom {
 			i2c-port = <&i2c5_0>;
-			enum-name = "I2C_PORT_EEPROM";
+			enum-names = "I2C_PORT_EEPROM";
 		};
 		i2c_sensor: sensor {
 			i2c-port = <&i2c7_0>;
-			enum-name = "I2C_PORT_SENSOR";
-		};
-		accel {
-			i2c-port = <&i2c7_0>;
-			enum-name = "I2C_PORT_ACCEL";
+			enum-names = "I2C_PORT_SENSOR",
+				"I2C_PORT_ACCEL";
 		};
 	};
 
@@ -53,6 +41,19 @@
 	clock-frequency = <I2C_BITRATE_STANDARD>;
 	pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>;
 	pinctrl-names = "default";
+
+	bc12_port0: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+		irq = <&int_usb_c0_bc12>;
+	};
+
+	charger: isl923x@9 {
+		compatible = "intersil,isl923x";
+		status = "okay";
+		reg = <0x9>;
+	};
 };
 
 &i2c_ctrl0 {
@@ -64,6 +65,18 @@
 	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
 	pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>;
 	pinctrl-names = "default";
+
+	ppc_port0: sn5s330@40 {
+		compatible = "ti,sn5s330";
+		status = "okay";
+		reg = <0x40>;
+	};
+
+	tcpc_port0: ps8xxx@b {
+		compatible = "parade,ps8xxx";
+		status = "okay";
+		reg = <0xb>;
+	};
 };
 
 &i2c_ctrl1 {
@@ -75,6 +88,18 @@
 	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
 	pinctrl-0 = <&i2c2_0_sda_scl_gp91_92>;
 	pinctrl-names = "default";
+
+	ppc_port1: sn5s330@40{
+		compatible = "ti,sn5s330";
+		status = "okay";
+		reg = <0x40>;
+	};
+
+	tcpc_port1: ps8xxx@b {
+		compatible = "parade,ps8xxx";
+		status = "okay";
+		reg = <0xb>;
+	};
 };
 
 &i2c_ctrl2 {
@@ -95,6 +120,13 @@
 	clock-frequency = <I2C_BITRATE_FAST>;
 	pinctrl-0 = <&i2c5_0_sda_scl_gp33_36>;
 	pinctrl-names = "default";
+
+	bc12_port1: pi3usb9201@5f {
+		compatible = "pericom,pi3usb9201";
+		status = "okay";
+		reg = <0x5f>;
+		irq = <&int_usb_c1_bc12>;
+	};
 };
 
 &i2c_ctrl5 {
diff --git a/zephyr/projects/trogdor/lazor/include/sku.h b/zephyr/projects/trogdor/lazor/include/sku.h
index 492d1623dd..76825bbba1 100644
--- a/zephyr/projects/trogdor/lazor/include/sku.h
+++ b/zephyr/projects/trogdor/lazor/include/sku.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/trogdor/lazor/interrupts.dts b/zephyr/projects/trogdor/lazor/interrupts.dts
index da9b5297ef..5c2ed35e90 100644
--- a/zephyr/projects/trogdor/lazor/interrupts.dts
+++ b/zephyr/projects/trogdor/lazor/interrupts.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/trogdor/lazor/keyboard.dts b/zephyr/projects/trogdor/lazor/keyboard.dts
index 83cd6bced4..b8689b883c 100644
--- a/zephyr/projects/trogdor/lazor/keyboard.dts
+++ b/zephyr/projects/trogdor/lazor/keyboard.dts
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,7 +27,6 @@
 	kblight {
 		compatible = "cros-ec,kblight-pwm";
 		pwms = <&pwm3 0 PWM_KHZ(10) PWM_POLARITY_NORMAL>;
-		frequency = <10000>;
 		generic-pwm-channel = <0>;
 	};
 };
diff --git a/zephyr/projects/trogdor/lazor/led.dts b/zephyr/projects/trogdor/lazor/led.dts
index 3bdf0147d7..4527afd34c 100644
--- a/zephyr/projects/trogdor/lazor/led.dts
+++ b/zephyr/projects/trogdor/lazor/led.dts
@@ -1,6 +1,6 @@
 / {
 	led-colors {
-		compatible = "cros-ec,led-colors";
+		compatible = "cros-ec,led-policy";
 
 		power-state-charge {
 			charge-state = "PWR_STATE_CHARGE";
@@ -65,9 +65,8 @@
 			};
 		};
 
-		power-state-idle-forced {
-			charge-state = "PWR_STATE_IDLE";
-			extra-flag = "LED_CHFLAG_FORCE_IDLE";
+		power-state-forced-idle {
+			charge-state = "PWR_STATE_FORCED_IDLE";
 
 			/* Blue 2 sec, Amber 2 sec */
 			color-0 {
@@ -80,9 +79,8 @@
 			};
 		};
 
-		power-state-idle-default {
+		power-state-idle {
 			charge-state = "PWR_STATE_IDLE";
-			extra-flag = "LED_CHFLAG_DEFAULT";
 
 			color-0 {
 				led-color = <&color_blue>;
diff --git a/zephyr/projects/trogdor/lazor/motionsense.dts b/zephyr/projects/trogdor/lazor/motionsense.dts
index adae7a736b..75fe31b997 100644
--- a/zephyr/projects/trogdor/lazor/motionsense.dts
+++ b/zephyr/projects/trogdor/lazor/motionsense.dts
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,11 +26,9 @@
 	motionsense-mutex {
 		compatible = "cros-ec,motionsense-mutex";
 		lid_mutex: lid-mutex {
-			label = "LID_MUTEX";
 		};
 
 		mutex_bmi160: bmi160-mutex {
-			label = "BMI160_MUTEX";
 		};
 	};
 
@@ -78,7 +76,7 @@
 
 	/*
 	 * List of motion sensors that creates motion_sensors array.
-	 * The label "lid_accel" and "base_accel" are used to indicate
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
 	 * motion sensor IDs for lid angle calculation.
 	 */
 	motionsense-sensor {
@@ -86,7 +84,6 @@
 			compatible = "cros-ec,bma255";
 			status = "okay";
 
-			label = "Lid Accel";
 			active-mask = "SENSOR_ACTIVE_S0_S3_S5";
 			location = "MOTIONSENSE_LOC_LID";
 			mutex = <&lid_mutex>;
@@ -99,11 +96,9 @@
 				compatible =
 					"cros-ec,motionsense-sensor-config";
 				ec-s0 {
-					label = "SENSOR_CONFIG_EC_S0";
 					odr = <(10000 | ROUND_UP_FLAG)>;
 				};
 				ec-s3 {
-					label = "SENSOR_CONFIG_EC_S3";
 					odr = <(10000 | ROUND_UP_FLAG)>;
 				};
 			};
@@ -113,7 +108,6 @@
 			compatible = "cros-ec,bmi160-accel";
 			status = "okay";
 
-			label = "Base Accel";
 			active-mask = "SENSOR_ACTIVE_S0_S3_S5";
 			location = "MOTIONSENSE_LOC_BASE";
 			mutex = <&mutex_bmi160>;
@@ -124,11 +118,9 @@
 				compatible =
 					"cros-ec,motionsense-sensor-config";
 				ec-s0 {
-					label = "SENSOR_CONFIG_EC_S0";
 					odr = <(10000 | ROUND_UP_FLAG)>;
 				};
 				ec-s3 {
-					label = "SENSOR_CONFIG_EC_S3";
 					odr = <(10000 | ROUND_UP_FLAG)>;
 				};
 			};
@@ -138,7 +130,6 @@
 			compatible = "cros-ec,bmi160-gyro";
 			status = "okay";
 
-			label = "Base Gyro";
 			active-mask = "SENSOR_ACTIVE_S0_S3_S5";
 			location = "MOTIONSENSE_LOC_BASE";
 			mutex = <&mutex_bmi160>;
@@ -156,7 +147,6 @@
 		alt_lid_accel {
 			compatible = "cros-ec,kx022";
 			status = "okay";
-			label = "Lid Accel";
 			active-mask = "SENSOR_ACTIVE_S0_S3_S5";
 			location = "MOTIONSENSE_LOC_LID";
 			mutex = <&lid_mutex>;
@@ -168,11 +158,9 @@
 				compatible =
 					"cros-ec,motionsense-sensor-config";
 				ec-s0 {
-					label = "SENSOR_CONFIG_EC_S0";
 					odr = <(10000 | ROUND_UP_FLAG)>;
 				};
 				ec-s3 {
-					label = "SENSOR_CONFIG_EC_S3";
 					odr = <(10000 | ROUND_UP_FLAG)>;
 				};
 			};
diff --git a/zephyr/projects/trogdor/lazor/prj.conf b/zephyr/projects/trogdor/lazor/prj.conf
index 44affef2ac..358de69d68 100644
--- a/zephyr/projects/trogdor/lazor/prj.conf
+++ b/zephyr/projects/trogdor/lazor/prj.conf
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -64,7 +64,6 @@ CONFIG_PLATFORM_EC_CMD_BUTTON=y
 CONFIG_CROS_KB_RAW_NPCX=y
 
 # ADC
-CONFIG_PLATFORM_EC_ADC=y
 CONFIG_ADC=y
 CONFIG_ADC_SHELL=n
 
@@ -106,6 +105,8 @@ CONFIG_PLATFORM_EC_USB_PD_5V_EN_CUSTOM=y
 CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y
 CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y
 CONFIG_PLATFORM_EC_USB_PD_REV30=n
+CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=n
+CONFIG_PLATFORM_EC_USB_PD_USB4=n
 CONFIG_PLATFORM_EC_USB_PD_TCPC_LOW_POWER=y
 CONFIG_PLATFORM_EC_USB_PD_TCPM_MULTI_PS8XXX=y
 CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8751=y
diff --git a/zephyr/projects/trogdor/lazor/pwm_led.dts b/zephyr/projects/trogdor/lazor/pwm_led.dts
index ee21c60c85..0582966d6a 100644
--- a/zephyr/projects/trogdor/lazor/pwm_led.dts
+++ b/zephyr/projects/trogdor/lazor/pwm_led.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,7 +20,6 @@
 
 	pwm-led-pins {
 		compatible = "cros-ec,pwm-led-pins";
-		pwm-frequency = <324>;
 
 		color_off: color-off {
 			led-color = "LED_OFF";
diff --git a/zephyr/projects/trogdor/lazor/src/hibernate.c b/zephyr/projects/trogdor/lazor/src/hibernate.c
index 5ad97a8c48..388ff1b087 100644
--- a/zephyr/projects/trogdor/lazor/src/hibernate.c
+++ b/zephyr/projects/trogdor/lazor/src/hibernate.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,12 +17,12 @@ void board_hibernate(void)
 		 * Sensors are unpowered in hibernate. Apply PD to the
 		 * interrupt lines such that they don't float.
 		 */
-		gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(
-				      gpio_accel_gyro_int_l),
-				      GPIO_DISCONNECTED);
-		gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(
-				      gpio_lid_accel_int_l),
-				      GPIO_DISCONNECTED);
+		gpio_pin_configure_dt(
+			GPIO_DT_FROM_NODELABEL(gpio_accel_gyro_int_l),
+			GPIO_DISCONNECTED);
+		gpio_pin_configure_dt(
+			GPIO_DT_FROM_NODELABEL(gpio_lid_accel_int_l),
+			GPIO_DISCONNECTED);
 	}
 
 	/*
diff --git a/zephyr/projects/trogdor/lazor/src/i2c.c b/zephyr/projects/trogdor/lazor/src/i2c.c
index 89e576f81a..6d737b410f 100644
--- a/zephyr/projects/trogdor/lazor/src/i2c.c
+++ b/zephyr/projects/trogdor/lazor/src/i2c.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/projects/trogdor/lazor/src/power.c b/zephyr/projects/trogdor/lazor/src/power.c
index ee4e1b3b8f..96f9bc43c5 100644
--- a/zephyr/projects/trogdor/lazor/src/power.c
+++ b/zephyr/projects/trogdor/lazor/src/power.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -51,7 +51,7 @@ static int board_power_handler_init(const struct device *unused)
 	/* Setup a suspend/resume callback */
 	ap_power_ev_init_callback(&cb, board_power_change,
 				  AP_POWER_PRE_INIT |
-				  AP_POWER_SHUTDOWN_COMPLETE);
+					  AP_POWER_SHUTDOWN_COMPLETE);
 	ap_power_ev_add_callback(&cb);
 	return 0;
 }
diff --git a/zephyr/projects/trogdor/lazor/src/sku.c b/zephyr/projects/trogdor/lazor/src/sku.c
index dde0549805..1d88437031 100644
--- a/zephyr/projects/trogdor/lazor/src/sku.c
+++ b/zephyr/projects/trogdor/lazor/src/sku.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,8 +13,8 @@
 #include "system.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 static uint8_t sku_id;
 
diff --git a/zephyr/projects/trogdor/lazor/src/switchcap.c b/zephyr/projects/trogdor/lazor/src/switchcap.c
index 6dc7c3fbab..d8205cbcfc 100644
--- a/zephyr/projects/trogdor/lazor/src/switchcap.c
+++ b/zephyr/projects/trogdor/lazor/src/switchcap.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,8 +16,8 @@
 #include "system.h"
 #include "sku.h"
 
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args)
 
 /* LN9310 switchcap */
 const struct ln9310_config_t ln9310_config = {
@@ -34,18 +34,16 @@ static void switchcap_init(void)
 		 * When the chip in power down mode, it outputs high-Z.
 		 * Set pull-down to avoid floating.
 		 */
-		gpio_pin_configure_dt(
-			GPIO_DT_FROM_NODELABEL(gpio_da9313_gpio0),
-			GPIO_INPUT | GPIO_PULL_DOWN);
+		gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_da9313_gpio0),
+				      GPIO_INPUT | GPIO_PULL_DOWN);
 
 		/*
 		 * Configure DA9313 enable, push-pull output. Don't set the
 		 * level here; otherwise, it will override its value and
 		 * shutdown the switchcap when sysjump to RW.
 		 */
-		gpio_pin_configure_dt(
-			GPIO_DT_FROM_NODELABEL(gpio_switchcap_on),
-			GPIO_OUTPUT);
+		gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_switchcap_on),
+				      GPIO_OUTPUT);
 	} else if (board_has_ln9310()) {
 		CPRINTS("Use switchcap: LN9310");
 
@@ -71,9 +69,8 @@ static void switchcap_init(void)
 		 * (6) GPIO init according to gpio.inc -> push-pull LOW
 		 * (7) This function configures it -> open-drain LOW
 		 */
-		gpio_pin_configure_dt(
-			GPIO_DT_FROM_NODELABEL(gpio_switchcap_on),
-			GPIO_OUTPUT | GPIO_OPEN_DRAIN);
+		gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_switchcap_on),
+				      GPIO_OUTPUT | GPIO_OPEN_DRAIN);
 
 		/* Only configure the switchcap if not sysjump */
 		if (!system_jumped_late()) {
@@ -83,8 +80,7 @@ static void switchcap_init(void)
 			 * configured from standby mode to switching mode.
 			 */
 			gpio_pin_set_dt(
-				GPIO_DT_FROM_NODELABEL(gpio_switchcap_on),
-				0);
+				GPIO_DT_FROM_NODELABEL(gpio_switchcap_on), 0);
 			ln9310_init();
 		}
 	} else if (board_has_buck_ic()) {
@@ -98,18 +94,14 @@ DECLARE_HOOK(HOOK_INIT, switchcap_init, HOOK_PRIO_DEFAULT);
 void board_set_switchcap_power(int enable)
 {
 	if (board_has_da9313()) {
-		gpio_pin_set_dt(
-			GPIO_DT_FROM_NODELABEL(gpio_switchcap_on),
-			enable);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_switchcap_on),
+				enable);
 	} else if (board_has_ln9310()) {
-		gpio_pin_set_dt(
-			GPIO_DT_FROM_NODELABEL(gpio_switchcap_on),
-			enable);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_switchcap_on),
+				enable);
 		ln9310_software_enable(enable);
 	} else if (board_has_buck_ic()) {
-		gpio_pin_set_dt(
-			GPIO_DT_FROM_NODELABEL(gpio_vbob_en),
-			enable);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_vbob_en), enable);
 	}
 }
 
@@ -117,18 +109,17 @@ int board_is_switchcap_enabled(void)
 {
 	if (board_has_da9313() || board_has_ln9310())
 		return gpio_pin_get_dt(
-				GPIO_DT_FROM_NODELABEL(gpio_switchcap_on));
+			GPIO_DT_FROM_NODELABEL(gpio_switchcap_on));
 
 	/* Board has buck ic*/
-	return gpio_pin_get_dt(
-			GPIO_DT_FROM_NODELABEL(gpio_vbob_en));
+	return gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_vbob_en));
 }
 
 int board_is_switchcap_power_good(void)
 {
 	if (board_has_da9313())
 		return gpio_pin_get_dt(
-				GPIO_DT_FROM_NODELABEL(gpio_da9313_gpio0));
+			GPIO_DT_FROM_NODELABEL(gpio_da9313_gpio0));
 	else if (board_has_ln9310())
 		return ln9310_power_good();
 
diff --git a/zephyr/projects/trogdor/lazor/src/usb_pd_policy.c b/zephyr/projects/trogdor/lazor/src/usb_pd_policy.c
index b94a65005a..8d046826f9 100644
--- a/zephyr/projects/trogdor/lazor/src/usb_pd_policy.c
+++ b/zephyr/projects/trogdor/lazor/src/usb_pd_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,8 +13,8 @@
 #include "usbc_ppc.h"
 #include "util.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 int pd_check_vconn_swap(int port)
 {
@@ -24,10 +24,10 @@ int pd_check_vconn_swap(int port)
 
 static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT];
 #if CONFIG_USB_PD_PORT_MAX_COUNT == 1
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5};
+static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5 };
 #else
-static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5,
-							TYPEC_RP_1A5};
+static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5,
+							 TYPEC_RP_1A5 };
 #endif
 
 static void board_vbus_update_source_current(int port)
@@ -108,11 +108,11 @@ __override int svdm_dp_config(int port, uint32_t *payload)
 	 *  (3) plug a monitor to the port-1 dongle.
 	 */
 
-	payload[0] = VDO(USB_SID_DISPLAYPORT, 1,
-			 CMD_DP_CONFIG | VDO_OPOS(opos));
-	payload[1] = VDO_DP_CFG(pin_mode,      /* pin mode */
-				1,             /* DPv1.3 signaling */
-				2);            /* UFP connected */
+	payload[0] =
+		VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_CONFIG | VDO_OPOS(opos));
+	payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */
+				1, /* DPv1.3 signaling */
+				2); /* UFP connected */
 	return 2;
 };
 
@@ -175,8 +175,8 @@ __override int svdm_dp_attention(int port, uint32_t *payload)
 		 * TODO(waihong): Better to move switching DP mux to
 		 * the usb_mux abstraction.
 		 */
-		gpio_pin_set_dt(
-			GPIO_DT_FROM_NODELABEL(gpio_dp_mux_sel), port == 1);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_dp_mux_sel),
+				port == 1);
 		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_dp_mux_oe_l), 0);
 
 		/* Connect the SBU lines in PPC chip. */
@@ -190,8 +190,7 @@ __override int svdm_dp_attention(int port, uint32_t *payload)
 		 * because of the board USB-C topology (limited to 2
 		 * lanes DP).
 		 */
-		usb_mux_set(port, USB_PD_MUX_DOCK,
-			    USB_SWITCH_CONNECT,
+		usb_mux_set(port, USB_PD_MUX_DOCK, USB_SWITCH_CONNECT,
 			    polarity_rm_dts(pd_get_polarity(port)));
 	} else {
 		/* Disconnect the DP port selection mux. */
@@ -203,13 +202,11 @@ __override int svdm_dp_attention(int port, uint32_t *payload)
 			ppc_set_sbu(port, 0);
 
 		/* Disconnect the DP but keep the USB SS lines in TCPC chip. */
-		usb_mux_set(port, USB_PD_MUX_USB_ENABLED,
-			    USB_SWITCH_CONNECT,
+		usb_mux_set(port, USB_PD_MUX_USB_ENABLED, USB_SWITCH_CONNECT,
 			    polarity_rm_dts(pd_get_polarity(port)));
 	}
 
-	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) &&
-	    (irq || lvl))
+	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && (irq || lvl))
 		/*
 		 * Wake up the AP.  IRQ or level high indicates a DP sink is now
 		 * present.
@@ -234,8 +231,8 @@ __override int svdm_dp_attention(int port, uint32_t *payload)
 		gpio_pin_set_dt(hpd, 1);
 
 		/* Set the minimum time delay (2ms) for the next HPD IRQ */
-		svdm_hpd_deadline[port] = get_time().val +
-			HPD_USTREAM_DEBOUNCE_LVL;
+		svdm_hpd_deadline[port] =
+			get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
 	} else if (irq & !lvl) {
 		CPRINTF("ERR:HPD:IRQ&LOW\n");
 		return 0;
@@ -256,9 +253,9 @@ __override void svdm_exit_dp_mode(int port)
 
 		/* Signal AP for the HPD low event */
 		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
-		gpio_pin_set_dt(
-			GPIO_DT_FROM_NODELABEL(gpio_dp_hot_plug_det), 0);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_dp_hot_plug_det),
+				0);
 	}
 }
 #endif /* CONFIG_USB_PD_ALT_MODE_DFP */
diff --git a/zephyr/projects/trogdor/lazor/src/usbc_config.c b/zephyr/projects/trogdor/lazor/src/usbc_config.c
index 59dbeb6fc6..f6bfdfb186 100644
--- a/zephyr/projects/trogdor/lazor/src/usbc_config.c
+++ b/zephyr/projects/trogdor/lazor/src/usbc_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,8 +27,8 @@
 #include "usbc_ocp.h"
 #include "usbc_ppc.h"
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 int charger_profile_override(struct charge_state_data *curr)
 {
@@ -71,9 +71,9 @@ enum ec_status charger_profile_override_set_param(uint32_t param,
 static void usba_oc_deferred(void)
 {
 	/* Use next number after all USB-C ports to indicate the USB-A port */
-	board_overcurrent_event(CONFIG_USB_PD_PORT_MAX_COUNT,
-				!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(
-					gpio_usb_a0_oc_odl)));
+	board_overcurrent_event(
+		CONFIG_USB_PD_PORT_MAX_COUNT,
+		!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_a0_oc_odl)));
 }
 DECLARE_DEFERRED(usba_oc_deferred);
 
@@ -137,16 +137,22 @@ void tcpc_alert_event(enum gpio_signal signal)
  * to AP. But the TCPC chip is also needed to know the HPD status; otherwise,
  * the mux misbehaves.
  */
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+const struct usb_mux_chain usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 	{
-		.usb_port = 0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 0,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	},
 	{
-		.usb_port = 1,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+		.mux =
+			&(const struct usb_mux){
+				.usb_port = 1,
+				.driver = &tcpci_tcpm_usb_mux_driver,
+				.hpd_update = &ps8xxx_tcpc_update_hpd_status,
+			},
 	}
 };
 
@@ -199,7 +205,7 @@ void board_tcpc_init(void)
 	 */
 	for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port)
 		usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED |
-					 USB_PD_MUX_HPD_IRQ_DEASSERTED);
+						 USB_PD_MUX_HPD_IRQ_DEASSERTED);
 }
 DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_POST_I2C);
 
@@ -244,8 +250,7 @@ void board_overcurrent_event(int port, int is_overcurrented)
 
 int board_set_active_charge_port(int port)
 {
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	int i;
 
 	if (!is_real_port && port != CHARGE_PORT_NONE)
@@ -273,7 +278,6 @@ int board_set_active_charge_port(int port)
 		return EC_ERROR_INVAL;
 	}
 
-
 	CPRINTS("New charge port: p%d", port);
 
 	/*
@@ -297,23 +301,21 @@ int board_set_active_charge_port(int port)
 	return EC_SUCCESS;
 }
 
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
 {
 	/*
 	 * Ignore lower charge ceiling on PD transition if our battery is
 	 * critical, as we may brownout.
 	 */
-	if (supplier == CHARGE_SUPPLIER_PD &&
-	    charge_ma < 1500 &&
+	if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 &&
 	    charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) {
 		CPRINTS("Using max ilim %d", max_ma);
 		charge_ma = max_ma;
 	}
 
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
+	charge_set_input_current_limit(
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
 uint16_t tcpc_get_alert_status(void)
@@ -322,11 +324,11 @@ uint16_t tcpc_get_alert_status(void)
 
 	if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_pd_int_odl)))
 		if (gpio_pin_get_dt(
-			GPIO_DT_FROM_NODELABEL(gpio_usb_c0_pd_rst_l)))
+			    GPIO_DT_FROM_NODELABEL(gpio_usb_c0_pd_rst_l)))
 			status |= PD_STATUS_TCPC_ALERT_0;
 	if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_pd_int_odl)))
 		if (gpio_pin_get_dt(
-			GPIO_DT_FROM_NODELABEL(gpio_usb_c1_pd_rst_l)))
+			    GPIO_DT_FROM_NODELABEL(gpio_usb_c1_pd_rst_l)))
 			status |= PD_STATUS_TCPC_ALERT_1;
 
 	return status;
diff --git a/zephyr/projects/trogdor/lazor/usbc.dts b/zephyr/projects/trogdor/lazor/usbc.dts
index 051efb09e3..7864c2716b 100644
--- a/zephyr/projects/trogdor/lazor/usbc.dts
+++ b/zephyr/projects/trogdor/lazor/usbc.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,60 +15,22 @@
 			compatible = "named-usbc-port";
 			reg = <0>;
 
-			bc12 {
-				compatible = "pericom,pi3usb9201";
-				status = "okay";
-				irq = <&int_usb_c0_bc12>;
-				port = <&i2c_power>;
-				i2c-addr-flags = "PI3USB9201_I2C_ADDR_3_FLAGS";
-			};
+			bc12 = <&bc12_port0>;
+			tcpc = <&tcpc_port0>;
 
-			tcpc {
-				compatible = "parade,ps8xxx";
-				status = "okay";
-				port = <&i2c_tcpc0>;
-				i2c-addr-flags = "PS8XXX_I2C_ADDR1_FLAGS";
-			};
+			ppc = <&ppc_port0>;
 
-			ppc {
-				compatible = "ti,sn5s330";
-				status = "okay";
-				port = <&i2c_tcpc0>;
-				i2c-addr-flags = "SN5S330_ADDR0_FLAGS";
-			};
-
-			chg {
-				compatible = "intersil,isl923x";
-				status = "okay";
-				port = <&i2c_charger>;
-			};
+			chg = <&charger>;
 		};
 
 		port1@1 {
 			compatible = "named-usbc-port";
 			reg = <1>;
 
-			bc12 {
-				compatible = "pericom,pi3usb9201";
-				status = "okay";
-				irq = <&int_usb_c1_bc12>;
-				port = <&i2c_eeprom>;
-				i2c-addr-flags = "PI3USB9201_I2C_ADDR_3_FLAGS";
-			};
-
-			tcpc {
-				compatible = "parade,ps8xxx";
-				status = "okay";
-				port = <&i2c_tcpc1>;
-				i2c-addr-flags = "PS8XXX_I2C_ADDR1_FLAGS";
-			};
+			bc12 = <&bc12_port1>;
+			tcpc = <&tcpc_port1>;
 
-			ppc {
-				compatible = "ti,sn5s330";
-				status = "okay";
-				port = <&i2c_tcpc1>;
-				i2c-addr-flags = "SN5S330_ADDR0_FLAGS";
-			};
+			ppc = <&ppc_port1>;
 		};
 	};
 };
diff --git a/zephyr/shim/CMakeLists.txt b/zephyr/shim/CMakeLists.txt
index e36101756a..5b8c815ae1 100644
--- a/zephyr/shim/CMakeLists.txt
+++ b/zephyr/shim/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/shim/chip/CMakeLists.txt b/zephyr/shim/chip/CMakeLists.txt
index 54281508aa..1d58857c11 100644
--- a/zephyr/shim/chip/CMakeLists.txt
+++ b/zephyr/shim/chip/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/shim/chip/it8xxx2/CMakeLists.txt b/zephyr/shim/chip/it8xxx2/CMakeLists.txt
index 539fd9f029..2a1c9d5909 100644
--- a/zephyr/shim/chip/it8xxx2/CMakeLists.txt
+++ b/zephyr/shim/chip/it8xxx2/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/shim/chip/it8xxx2/clock.c b/zephyr/shim/chip/it8xxx2/clock.c
index 0e7b7cb39e..14dbc0e7eb 100644
--- a/zephyr/shim/chip/it8xxx2/clock.c
+++ b/zephyr/shim/chip/it8xxx2/clock.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,7 +8,6 @@
 #include <zephyr/kernel.h>
 #include <zephyr/logging/log.h>
 #include <soc.h>
-#include <zephyr/zephyr.h>
 #include <soc/ite_it8xxx2/reg_def_cros.h>
 #include <zephyr/sys/util.h>
 
@@ -16,21 +15,13 @@
 
 LOG_MODULE_REGISTER(shim_clock, LOG_LEVEL_ERR);
 
-#define ECPM_NODE		DT_INST(0, ite_it8xxx2_ecpm)
-#define HAL_ECPM_REG_BASE_ADDR	\
-			((struct ecpm_reg *)DT_REG_ADDR_BY_IDX(ECPM_NODE, 0))
-#define PLLFREQ_MASK		0xf
+#define ECPM_NODE DT_INST(0, ite_it8xxx2_ecpm)
+#define HAL_ECPM_REG_BASE_ADDR \
+	((struct ecpm_reg *)DT_REG_ADDR_BY_IDX(ECPM_NODE, 0))
+#define PLLFREQ_MASK 0xf
 
-static const int pll_reg_to_freq[8] = {
-	MHZ(8),
-	MHZ(16),
-	MHZ(24),
-	MHZ(32),
-	MHZ(48),
-	MHZ(64),
-	MHZ(72),
-	MHZ(96)
-};
+static const int pll_reg_to_freq[8] = { MHZ(8),	 MHZ(16), MHZ(24), MHZ(32),
+					MHZ(48), MHZ(64), MHZ(72), MHZ(96) };
 
 int clock_get_freq(void)
 {
diff --git a/zephyr/shim/chip/it8xxx2/gpio.c b/zephyr/shim/chip/it8xxx2/gpio.c
index 3baf128eab..7106b2a294 100644
--- a/zephyr/shim/chip/it8xxx2/gpio.c
+++ b/zephyr/shim/chip/it8xxx2/gpio.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/shim/chip/it8xxx2/include/flash_chip.h b/zephyr/shim/chip/it8xxx2/include/flash_chip.h
index 692eaa9db0..00aaba05fd 100644
--- a/zephyr/shim/chip/it8xxx2/include/flash_chip.h
+++ b/zephyr/shim/chip/it8xxx2/include/flash_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,25 +9,25 @@
  * One page program instruction allows maximum 256 bytes (a page) of data
  * to be programmed.
  */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE   256
+#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256
 /* Minimum write size */
-#define CONFIG_FLASH_WRITE_SIZE         DT_PROP(DT_INST(0, soc_nv_flash), \
-						write_block_size)
+#define CONFIG_FLASH_WRITE_SIZE \
+	DT_PROP(DT_INST(0, soc_nv_flash), write_block_size)
 /* Erase bank size */
-#define CONFIG_FLASH_ERASE_SIZE         DT_PROP(DT_INST(0, soc_nv_flash), \
-						erase_block_size)
+#define CONFIG_FLASH_ERASE_SIZE \
+	DT_PROP(DT_INST(0, soc_nv_flash), erase_block_size)
 /* Protect bank size */
-#define CONFIG_FLASH_BANK_SIZE          CONFIG_FLASH_ERASE_SIZE
+#define CONFIG_FLASH_BANK_SIZE CONFIG_FLASH_ERASE_SIZE
 
-#define CONFIG_RO_STORAGE_OFF           0x0
-#define CONFIG_RW_STORAGE_OFF           0x0
+#define CONFIG_RO_STORAGE_OFF 0x0
+#define CONFIG_RW_STORAGE_OFF 0x0
 
 /*
  * The EC uses the one bank of flash to emulate a SPI-like write protect
  * register with persistent state.
  */
-#define CONFIG_FW_PSTATE_SIZE           CONFIG_FLASH_BANK_SIZE
-#define CONFIG_FW_PSTATE_OFF            (CONFIG_FLASH_SIZE_BYTES / 2 - \
-						CONFIG_FW_PSTATE_SIZE)
+#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE
+#define CONFIG_FW_PSTATE_OFF \
+	(CONFIG_RO_STORAGE_OFF + CONFIG_RO_SIZE - CONFIG_FW_PSTATE_SIZE)
 
 #endif /* __CROS_EC_FLASH_CHIP_H */
diff --git a/zephyr/shim/chip/it8xxx2/keyboard_raw.c b/zephyr/shim/chip/it8xxx2/keyboard_raw.c
index 480d528e41..0a117cda14 100644
--- a/zephyr/shim/chip/it8xxx2/keyboard_raw.c
+++ b/zephyr/shim/chip/it8xxx2/keyboard_raw.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,7 +8,7 @@
 #include <zephyr/device.h>
 #include <zephyr/logging/log.h>
 #include <soc.h>
-#include <zephyr/zephyr.h>
+#include <zephyr/kernel.h>
 
 #include "drivers/cros_kb_raw.h"
 #include "keyboard_raw.h"
diff --git a/zephyr/shim/chip/it8xxx2/power_policy.c b/zephyr/shim/chip/it8xxx2/power_policy.c
index 7c2e02e258..c8efb0ca96 100644
--- a/zephyr/shim/chip/it8xxx2/power_policy.c
+++ b/zephyr/shim/chip/it8xxx2/power_policy.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,7 @@
 #include <zephyr/pm/pm.h>
 #include <zephyr/pm/policy.h>
 #include <soc.h>
-#include <zephyr/zephyr.h>
+#include <zephyr/kernel.h>
 
 #include "system.h"
 
@@ -29,8 +29,8 @@ const struct pm_state_info *pm_policy_next_state(uint8_t cpu, int32_t ticks)
 			 * To check if given power state is enabled and
 			 * could be used.
 			 */
-			if (pm_policy_state_lock_is_active(
-				    pm_states[i].state, PM_ALL_SUBSTATES)) {
+			if (pm_policy_state_lock_is_active(pm_states[i].state,
+							   PM_ALL_SUBSTATES)) {
 				continue;
 			}
 
diff --git a/zephyr/shim/chip/it8xxx2/system.c b/zephyr/shim/chip/it8xxx2/system.c
index d9dcd7ccfb..e5f9cc5cf0 100644
--- a/zephyr/shim/chip/it8xxx2/system.c
+++ b/zephyr/shim/chip/it8xxx2/system.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/shim/chip/mchp/CMakeLists.txt b/zephyr/shim/chip/mchp/CMakeLists.txt
index 0948424275..f59a1be2b1 100644
--- a/zephyr/shim/chip/mchp/CMakeLists.txt
+++ b/zephyr/shim/chip/mchp/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/shim/chip/mchp/Kconfig.xec b/zephyr/shim/chip/mchp/Kconfig.xec
index 3b18b1c192..28a6b3ea3c 100644
--- a/zephyr/shim/chip/mchp/Kconfig.xec
+++ b/zephyr/shim/chip/mchp/Kconfig.xec
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/shim/chip/mchp/clock.c b/zephyr/shim/chip/mchp/clock.c
index 3bdb6e4f99..6ee4cd931c 100644
--- a/zephyr/shim/chip/mchp/clock.c
+++ b/zephyr/shim/chip/mchp/clock.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,16 +9,15 @@
 #include <zephyr/kernel.h>
 #include <zephyr/logging/log.h>
 #include <soc.h>
-#include <zephyr/zephyr.h>
 
 #include "clock_chip.h"
 #include "module_id.h"
 
 LOG_MODULE_REGISTER(shim_clock, LOG_LEVEL_ERR);
 
-#define PCR_NODE		DT_INST(0, microchip_xec_pcr)
+#define PCR_NODE DT_INST(0, microchip_xec_pcr)
 #define HAL_PCR_REG_BASE_ADDR \
-			((struct pcr_regs *)DT_REG_ADDR_BY_IDX(PCR_NODE, 0))
+	((struct pcr_regs *)DT_REG_ADDR_BY_IDX(PCR_NODE, 0))
 
 int clock_get_freq(void)
 {
diff --git a/zephyr/shim/chip/mchp/gpio.c b/zephyr/shim/chip/mchp/gpio.c
index 3a16b9639d..7801c6f7cc 100644
--- a/zephyr/shim/chip/mchp/gpio.c
+++ b/zephyr/shim/chip/mchp/gpio.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/shim/chip/mchp/include/clock_chip.h b/zephyr/shim/chip/mchp/include/clock_chip.h
index c317ccb415..4c14d60ff9 100644
--- a/zephyr/shim/chip/mchp/include/clock_chip.h
+++ b/zephyr/shim/chip/mchp/include/clock_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/shim/chip/mchp/include/flash_chip.h b/zephyr/shim/chip/mchp/include/flash_chip.h
index b3677fb45c..de8138614c 100644
--- a/zephyr/shim/chip/mchp/include/flash_chip.h
+++ b/zephyr/shim/chip/mchp/include/flash_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,10 +11,10 @@
  * Similar to W25X40, both only have one status reg
  */
 #define CONFIG_SPI_FLASH_W25X40 /* Internal SPI flash type. */
-#define CONFIG_FLASH_WRITE_SIZE		0x1  /* minimum write size */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE	256   /* one page size for write */
-#define CONFIG_FLASH_ERASE_SIZE		0x1000
-#define CONFIG_FLASH_BANK_SIZE		CONFIG_FLASH_ERASE_SIZE
+#define CONFIG_FLASH_WRITE_SIZE 0x1 /* minimum write size */
+#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* one page size for write */
+#define CONFIG_FLASH_ERASE_SIZE 0x1000
+#define CONFIG_FLASH_BANK_SIZE CONFIG_FLASH_ERASE_SIZE
 
 /* RO image resides at 4KB offset in protected region
  * The first 4KB in the protected region starting at offset 0 contains
@@ -23,7 +23,7 @@
  * RW image is never loaded by the Boot-ROM therefore no TAG or Header
  * is needed. RW starts at offset 0 in RW storage region.
  */
-#define CONFIG_RO_STORAGE_OFF		0x1000
-#define CONFIG_RW_STORAGE_OFF		0
+#define CONFIG_RO_STORAGE_OFF 0x1000
+#define CONFIG_RW_STORAGE_OFF 0
 
 #endif /* __CROS_EC_FLASH_CHIP_H */
diff --git a/zephyr/shim/chip/mchp/include/system_chip.h b/zephyr/shim/chip/mchp/include/system_chip.h
index a62ea4a525..01cd1e7391 100644
--- a/zephyr/shim/chip/mchp/include/system_chip.h
+++ b/zephyr/shim/chip/mchp/include/system_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,18 +6,18 @@
 #ifndef __CROS_EC_SYSTEM_CHIP_H_
 #define __CROS_EC_SYSTEM_CHIP_H_
 
-#define SET_BIT(reg, bit)           ((reg) |= (0x1 << (bit)))
-#define CLEAR_BIT(reg, bit)         ((reg) &= (~(0x1 << (bit))))
+#define SET_BIT(reg, bit) ((reg) |= (0x1 << (bit)))
+#define CLEAR_BIT(reg, bit) ((reg) &= (~(0x1 << (bit))))
 
 #undef IS_BIT_SET
-#define IS_BIT_SET(reg, bit)        (((reg) >> (bit)) & (0x1))
+#define IS_BIT_SET(reg, bit) (((reg) >> (bit)) & (0x1))
 
 /******************************************************************************/
 /* Optional M4 Registers */
-#define CPU_MPU_CTRL		REG32(0xE000ED94)
-#define CPU_MPU_RNR		REG32(0xE000ED98)
-#define CPU_MPU_RBAR		REG32(0xE000ED9C)
-#define CPU_MPU_RASR		REG32(0xE000EDA0)
+#define CPU_MPU_CTRL REG32(0xE000ED94)
+#define CPU_MPU_RNR REG32(0xE000ED98)
+#define CPU_MPU_RBAR REG32(0xE000ED9C)
+#define CPU_MPU_RASR REG32(0xE000EDA0)
 
 void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr,
 				uint32_t size, uint32_t exeAddr);
diff --git a/zephyr/shim/chip/mchp/keyboard_raw.c b/zephyr/shim/chip/mchp/keyboard_raw.c
index 0b9280aa41..95ad642d12 100644
--- a/zephyr/shim/chip/mchp/keyboard_raw.c
+++ b/zephyr/shim/chip/mchp/keyboard_raw.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,7 +8,7 @@
 #include <zephyr/device.h>
 #include <zephyr/logging/log.h>
 #include <soc.h>
-#include <zephyr/zephyr.h>
+#include <zephyr/kernel.h>
 
 #include "drivers/cros_kb_raw.h"
 #include "keyboard_raw.h"
diff --git a/zephyr/shim/chip/mchp/system.c b/zephyr/shim/chip/mchp/system.c
index 25fdfc9897..35ba806533 100644
--- a/zephyr/shim/chip/mchp/system.c
+++ b/zephyr/shim/chip/mchp/system.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,7 @@
 
 LOG_MODULE_REGISTER(shim_xec_system, LOG_LEVEL_ERR);
 
-#define GET_BBRAM_OFS(node) \
-	DT_PROP(DT_PATH(named_bbram_regions, node), offset)
+#define GET_BBRAM_OFS(node) DT_PROP(DT_PATH(named_bbram_regions, node), offset)
 #define GET_BBRAM_SZ(node) DT_PROP(DT_PATH(named_bbram_regions, node), size)
 
 /*
diff --git a/zephyr/shim/chip/mchp/system_download_from_flash.c b/zephyr/shim/chip/mchp/system_download_from_flash.c
index 99026fe822..ced7f4d89c 100644
--- a/zephyr/shim/chip/mchp/system_download_from_flash.c
+++ b/zephyr/shim/chip/mchp/system_download_from_flash.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,30 +10,28 @@
 #include "system_chip.h"
 
 /* Modules Map */
-#define WDT_NODE		DT_INST(0, microchip_xec_watchdog)
-#define STRUCT_WDT_REG_BASE_ADDR \
-			((struct wdt_regs *)(DT_REG_ADDR(WDT_NODE)))
+#define WDT_NODE DT_INST(0, microchip_xec_watchdog)
+#define STRUCT_WDT_REG_BASE_ADDR ((struct wdt_regs *)(DT_REG_ADDR(WDT_NODE)))
 
-#define PCR_NODE		DT_INST(0, microchip_xec_pcr)
+#define PCR_NODE DT_INST(0, microchip_xec_pcr)
 #define STRUCT_PCR_REG_BASE_ADDR \
-			((struct pcr_regs *)DT_REG_ADDR_BY_IDX(PCR_NODE, 0))
+	((struct pcr_regs *)DT_REG_ADDR_BY_IDX(PCR_NODE, 0))
 
-#define QSPI_NODE		DT_INST(0, microchip_xec_qmspi_ldma)
+#define QSPI_NODE DT_INST(0, microchip_xec_qmspi_ldma)
 #define STRUCT_QSPI_REG_BASE_ADDR \
-			((struct qmspi_regs *)(DT_REG_ADDR(QSPI_NODE)))
+	((struct qmspi_regs *)(DT_REG_ADDR(QSPI_NODE)))
 
-#define SPI_READ_111		0x03
-#define SPI_READ_111_FAST	0x0b
-#define SPI_READ_112_FAST	0x3b
+#define SPI_READ_111 0x03
+#define SPI_READ_111_FAST 0x0b
+#define SPI_READ_112_FAST 0x3b
 
-#define QSPI_STATUS_DONE						\
-	(MCHP_QMSPI_STS_DONE | MCHP_QMSPI_STS_DMA_DONE)
+#define QSPI_STATUS_DONE (MCHP_QMSPI_STS_DONE | MCHP_QMSPI_STS_DMA_DONE)
 
-#define QSPI_STATUS_ERR							\
-	(MCHP_QMSPI_STS_TXB_ERR | MCHP_QMSPI_STS_RXB_ERR |	\
+#define QSPI_STATUS_ERR                                    \
+	(MCHP_QMSPI_STS_TXB_ERR | MCHP_QMSPI_STS_RXB_ERR | \
 	 MCHP_QMSPI_STS_PROG_ERR | MCHP_QMSPI_STS_LDMA_RX_ERR)
 
-noreturn void __keep __attribute__ ((section(".code_in_sram2")))
+noreturn void __keep __attribute__((section(".code_in_sram2")))
 __start_qspi(uint32_t resetVectAddr)
 {
 	struct pcr_regs *pcr = STRUCT_PCR_REG_BASE_ADDR;
@@ -79,7 +77,7 @@ uintptr_t __lfw_sram_start = CONFIG_CROS_EC_RAM_BASE + CONFIG_CROS_EC_RAM_SIZE;
 typedef void (*START_QSPI_IN_SRAM_FP)(uint32_t);
 
 void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr,
-		uint32_t size, uint32_t resetVectAddr)
+				uint32_t size, uint32_t resetVectAddr)
 {
 	struct pcr_regs *pcr = STRUCT_PCR_REG_BASE_ADDR;
 	struct qmspi_regs *qspi = STRUCT_QSPI_REG_BASE_ADDR;
@@ -102,16 +100,16 @@ void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr,
 	qspi->CTRL = BIT(MCHP_QMSPI_C_DESCR_EN_POS);
 
 	/* Transmit 4 bytes(opcode + 24-bit address) on IO0 */
-	qspi->DESCR[0] = (MCHP_QMSPI_C_IFM_1X | MCHP_QMSPI_C_TX_DATA |
-			  MCHP_QMSPI_C_XFR_UNITS_1 |
-			  MCHP_QMSPI_C_XFR_NUNITS(4) |
-			  MCHP_QMSPI_C_NEXT_DESCR(1));
+	qspi->DESCR[0] =
+		(MCHP_QMSPI_C_IFM_1X | MCHP_QMSPI_C_TX_DATA |
+		 MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(4) |
+		 MCHP_QMSPI_C_NEXT_DESCR(1));
 
 	/* Transmit 8 clocks with IO0 and IO1 tri-stated */
-	qspi->DESCR[1] = (MCHP_QMSPI_C_IFM_2X | MCHP_QMSPI_C_TX_DIS |
-			  MCHP_QMSPI_C_XFR_UNITS_1 |
-			  MCHP_QMSPI_C_XFR_NUNITS(2) |
-			  MCHP_QMSPI_C_NEXT_DESCR(2));
+	qspi->DESCR[1] =
+		(MCHP_QMSPI_C_IFM_2X | MCHP_QMSPI_C_TX_DIS |
+		 MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(2) |
+		 MCHP_QMSPI_C_NEXT_DESCR(2));
 
 	/* Read using LDMA RX Chan 0, IFM=2x, Last Descriptor, close */
 	qspi->DESCR[2] = (MCHP_QMSPI_C_IFM_2X | MCHP_QMSPI_C_TX_DIS |
@@ -147,7 +145,7 @@ void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr,
 	/* Copy the __start_gdma_in_lpram instructions to LPRAM */
 	for (i = 0; i < &__flash_lplfw_end - &__flash_lplfw_start; i++) {
 		*((uint32_t *)__lfw_sram_start + i) =
-				*(&__flash_lplfw_start + i);
+			*(&__flash_lplfw_start + i);
 	}
 
 	/* Call into SRAM routine to start QSPI */
diff --git a/zephyr/shim/chip/mchp/system_external_storage.c b/zephyr/shim/chip/mchp/system_external_storage.c
index c326a07328..4250b05fe3 100644
--- a/zephyr/shim/chip/mchp/system_external_storage.c
+++ b/zephyr/shim/chip/mchp/system_external_storage.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,12 +13,11 @@
 #include "system_chip.h"
 #include "config_chip.h"
 
-#define MCHP_ECRO_WORD		0x4F524345u /* ASCII ECRO */
-#define MCHP_ECRW_WORD		0x57524345u /* ASCII ECRW */
-#define MCHP_PCR_NODE		DT_INST(0, microchip_xec_pcr)
+#define MCHP_ECRO_WORD 0x4F524345u /* ASCII ECRO */
+#define MCHP_ECRW_WORD 0x57524345u /* ASCII ECRW */
+#define MCHP_PCR_NODE DT_INST(0, microchip_xec_pcr)
 
-#define GET_BBRAM_OFS(node) \
-	DT_PROP(DT_PATH(named_bbram_regions, node), offset)
+#define GET_BBRAM_OFS(node) DT_PROP(DT_PATH(named_bbram_regions, node), offset)
 #define GET_BBRAM_SZ(node) DT_PROP(DT_PATH(named_bbram_regions, node), size)
 
 static const struct device *const bbram_dev =
@@ -49,8 +48,8 @@ void system_jump_to_booter(void)
 	 */
 	switch (system_get_shrspi_image_copy()) {
 	case EC_IMAGE_RW:
-		flash_offset = CONFIG_EC_WRITABLE_STORAGE_OFF +
-				CONFIG_RW_STORAGE_OFF;
+		flash_offset =
+			CONFIG_EC_WRITABLE_STORAGE_OFF + CONFIG_RW_STORAGE_OFF;
 		flash_used = CONFIG_CROS_EC_RW_SIZE;
 		break;
 	case EC_IMAGE_RO:
diff --git a/zephyr/shim/chip/npcx/CMakeLists.txt b/zephyr/shim/chip/npcx/CMakeLists.txt
index 3019118cf4..79b8cf2a62 100644
--- a/zephyr/shim/chip/npcx/CMakeLists.txt
+++ b/zephyr/shim/chip/npcx/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/shim/chip/npcx/Kconfig.npcx b/zephyr/shim/chip/npcx/Kconfig.npcx
index b044912ae1..5202d14448 100644
--- a/zephyr/shim/chip/npcx/Kconfig.npcx
+++ b/zephyr/shim/chip/npcx/Kconfig.npcx
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -15,4 +15,52 @@ config CROS_SYSTEM_NPCX_PRE_INIT_PRIORITY
 	  must be a lower priority than CONFIG_BBRAM_INIT_PRIORITY and
 	  must be a higher priority than PLATFORM_EC_SYSTEM_PRE_INIT.
 
+config PLATFORM_EC_CONSOLE_CMD_GPIODBG
+	bool "Console command: gpiodbg"
+	depends on SOC_FAMILY_NPCX
+	help
+	  Enable the "gpiodbg" command. This lists all IO pads used on platform
+	  and turns on/off specific pad's input buffer to observe leakage
+	  current through it.
+
+	  Example:
+	     gpiodbg list
+
+	     IDX|ON| GPIO | Name
+	     ---+--+------+----------
+	     00 |* | io03 | recovery_l
+	     01 |* | io93 | wp_l
+	     02 |* | iod2 | ac_present
+	     03 |* | io00 | power_button_l
+	     04 |* | io01 | lid_open
+	     05 |* | io36 | entering_rw
+	     06 |* | io50 | pch_wake_l
+	     07 |* | ioc7 | pgood_fan
+	     08 |* | ioa5 | spi_cs_l
+	     09 |* | io64 | board_version1
+	     10 |* | io65 | board_version2
+	     11 |* | io66 | board_version3
+	     12 |* | io52 | unused pin
+	     13 |* | io54 | unused pin
+
+	     gpiodbg off 11
+	     gpiodbg list
+
+	     IDX|ON| GPIO | Name
+	     ---+--+------+----------
+	     00 |* | io03 | recovery_l
+	     01 |* | io93 | wp_l
+	     02 |* | iod2 | ac_present
+	     03 |* | io00 | power_button_l
+	     04 |* | io01 | lid_open
+	     05 |* | io36 | entering_rw
+	     06 |* | io50 | pch_wake_l
+	     07 |* | ioc7 | pgood_fan
+	     08 |* | ioa5 | spi_cs_l
+	     09 |* | io64 | board_version1
+	     10 |* | io65 | board_version2
+	     11 |  | io66 | board_version3
+	     12 |* | io52 | unused pin
+	     13 |* | io54 | unused pin
+
 endif # PLATFORM_EC
diff --git a/zephyr/shim/chip/npcx/clock.c b/zephyr/shim/chip/npcx/clock.c
index 4fc9bd12c0..fc483ef775 100644
--- a/zephyr/shim/chip/npcx/clock.c
+++ b/zephyr/shim/chip/npcx/clock.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,16 +9,15 @@
 #include <zephyr/kernel.h>
 #include <zephyr/logging/log.h>
 #include <soc.h>
-#include <zephyr/zephyr.h>
 
 #include "clock_chip.h"
 #include "module_id.h"
 
 LOG_MODULE_REGISTER(shim_clock, LOG_LEVEL_ERR);
 
-#define CDCG_NODE		DT_INST(0, nuvoton_npcx_pcc)
+#define CDCG_NODE DT_INST(0, nuvoton_npcx_pcc)
 #define HAL_CDCG_REG_BASE_ADDR \
-			((struct cdcg_reg *)DT_REG_ADDR_BY_IDX(CDCG_NODE, 1))
+	((struct cdcg_reg *)DT_REG_ADDR_BY_IDX(CDCG_NODE, 1))
 
 int clock_get_freq(void)
 {
@@ -63,7 +62,7 @@ void clock_normal(void)
 	struct cdcg_reg *const cdcg_base = HAL_CDCG_REG_BASE_ADDR;
 
 	cdcg_base->HFCGP = ((FPRED_VAL << 4) | AHB6DIV_VAL);
-	cdcg_base->HFCBCD  = (FIUDIV_VAL << 4);
+	cdcg_base->HFCBCD = (FIUDIV_VAL << 4);
 }
 
 void clock_enable_module(enum module_id module, int enable)
diff --git a/zephyr/shim/chip/npcx/gpio.c b/zephyr/shim/chip/npcx/gpio.c
index 3baf128eab..e8bf3dfdf5 100644
--- a/zephyr/shim/chip/npcx/gpio.c
+++ b/zephyr/shim/chip/npcx/gpio.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,10 +6,13 @@
 #include <zephyr/device.h>
 #include <zephyr/drivers/gpio.h>
 #include <zephyr/kernel.h>
+#include <zephyr/shell/shell.h>
 
 #include <zephyr/logging/log.h>
 
 #include "gpio/gpio.h"
+#include "soc_gpio.h"
+#include "util.h"
 
 LOG_MODULE_REGISTER(shim_cros_gpio, LOG_LEVEL_ERR);
 
@@ -53,3 +56,142 @@ int gpio_config_unused_pins(void)
 
 	return 0;
 }
+
+#ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_GPIODBG
+/*
+ * IO information about each GPIO that is configured in the `named_gpios` and
+ *` unused_pins` device tree nodes.
+ */
+struct npcx_io_info {
+	/* A npcx gpio port device */
+	const struct device *dev;
+	/* A npcx gpio port number */
+	int port;
+	/* Bit number of pin within a npcx gpio port */
+	gpio_pin_t pin;
+	/* GPIO net name */
+	const char *name;
+	/* Enable flag of npcx gpio input buffer */
+	bool enable;
+};
+
+#define NAMED_GPIO_INFO(node)                                      \
+	{                                                          \
+		.dev = DEVICE_DT_GET(DT_GPIO_CTLR(node, gpios)),   \
+		.port = DT_PROP(DT_GPIO_CTLR(node, gpios), index), \
+		.pin = DT_GPIO_PIN(node, gpios),                   \
+		.name = DT_NODE_FULL_NAME(node),                   \
+		.enable = true,                                    \
+	},
+
+#define UNUSED_GPIO_INFO(node, prop, idx)                                     \
+	{                                                                     \
+		.dev = DEVICE_DT_GET(DT_GPIO_CTLR_BY_IDX(node, prop, idx)),   \
+		.port = DT_PROP(DT_GPIO_CTLR_BY_IDX(node, prop, idx), index), \
+		.pin = DT_GPIO_PIN_BY_IDX(node, prop, idx),                   \
+		.name = "unused pin",                                         \
+		.enable = true,                                               \
+	},
+
+#define NAMED_GPIO_INIT(node) \
+	COND_CODE_1(DT_NODE_HAS_PROP(node, gpios), (NAMED_GPIO_INFO(node)), ())
+
+static struct npcx_io_info gpio_info[] = {
+#if DT_NODE_EXISTS(DT_PATH(named_gpios))
+	DT_FOREACH_CHILD(DT_PATH(named_gpios), NAMED_GPIO_INIT)
+#endif
+#if DT_NODE_EXISTS(DT_PATH(unused_pins))
+		DT_FOREACH_PROP_ELEM(DT_PATH(unused_pins), unused_gpios,
+				     UNUSED_GPIO_INFO)
+#endif
+};
+
+static int get_index_from_arg(const struct shell *sh, char **argv, int *index)
+{
+	char *end_ptr;
+	int num = strtol(argv[1], &end_ptr, 0);
+	const int gpio_cnt = ARRAY_SIZE(gpio_info);
+
+	if (*end_ptr != '\0') {
+		shell_error(sh, "Failed to parse %s", argv[1]);
+		return -EINVAL;
+	}
+
+	if (num >= gpio_cnt) {
+		shell_error(sh, "Index shall be less than %u, was %u", gpio_cnt,
+			    num);
+		return -EINVAL;
+	}
+
+	*index = num;
+
+	return 0;
+}
+
+static int cmd_gpio_list_all(const struct shell *sh, size_t argc, char **argv)
+{
+	ARG_UNUSED(argc);
+	ARG_UNUSED(argv);
+
+	/* Print header */
+	shell_print(sh, "IDX|ON| GPIO | Name");
+	shell_print(sh, "---+--+------+----------");
+
+	/* List all GPIOs in 'named-gpios' and 'unused_pins' DT nodes */
+	for (int i = 0; i < ARRAY_SIZE(gpio_info); i++) {
+		shell_print(sh, "%02d |%s | io%x%x | %s", i,
+			    gpio_info[i].enable ? "*" : " ", gpio_info[i].port,
+			    gpio_info[i].pin, gpio_info[i].name);
+	}
+
+	return 0;
+}
+
+static int cmd_gpio_turn_on(const struct shell *sh, size_t argc, char **argv)
+{
+	int index;
+	int res = get_index_from_arg(sh, argv, &index);
+
+	if (res < 0) {
+		return res;
+	}
+
+	/* Turn on GPIO's input buffer by index */
+	gpio_info[index].enable = true;
+	npcx_gpio_enable_io_pads(gpio_info[index].dev, gpio_info[index].pin);
+
+	return 0;
+}
+
+static int cmd_gpio_turn_off(const struct shell *sh, size_t argc, char **argv)
+{
+	int index;
+	int res = get_index_from_arg(sh, argv, &index);
+
+	if (res < 0) {
+		return res;
+	}
+
+	/* Turn off GPIO's input buffer by index */
+	gpio_info[index].enable = false;
+	npcx_gpio_disable_io_pads(gpio_info[index].dev, gpio_info[index].pin);
+
+	return 0;
+}
+
+SHELL_STATIC_SUBCMD_SET_CREATE(
+	sub_gpiodbg,
+	SHELL_CMD_ARG(list, NULL, "List all GPIOs used on platform by index",
+		      cmd_gpio_list_all, 1, 0),
+	SHELL_CMD_ARG(on, NULL, "<index_in_list> Turn on GPIO's input buffer",
+		      cmd_gpio_turn_on, 2, 0),
+	SHELL_CMD_ARG(off, NULL, "<index_in_list> Turn off GPIO's input buffer",
+		      cmd_gpio_turn_off, 2, 0),
+	SHELL_SUBCMD_SET_END /* Array terminated. */
+);
+
+SHELL_CMD_ARG_REGISTER(gpiodbg, &sub_gpiodbg,
+		       "Commands for power consumption "
+		       "investigation",
+		       NULL, 2, 0);
+#endif /* CONFIG_PLATFORM_EC_CONSOLE_CMD_GPIODBG */
diff --git a/zephyr/shim/chip/npcx/include/clock_chip.h b/zephyr/shim/chip/npcx/include/clock_chip.h
index 0c39ed8174..6ecca330b6 100644
--- a/zephyr/shim/chip/npcx/include/clock_chip.h
+++ b/zephyr/shim/chip/npcx/include/clock_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/shim/chip/npcx/include/flash_chip.h b/zephyr/shim/chip/npcx/include/flash_chip.h
index 1d7a76f1da..362d8b2414 100644
--- a/zephyr/shim/chip/npcx/include/flash_chip.h
+++ b/zephyr/shim/chip/npcx/include/flash_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,17 +8,17 @@
 
 #define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
 
-#define CONFIG_FLASH_WRITE_SIZE		0x1  /* minimum write size */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE	256   /* one page size for write */
-#define CONFIG_FLASH_ERASE_SIZE	0x10000
-#define CONFIG_FLASH_BANK_SIZE		CONFIG_FLASH_ERASE_SIZE
+#define CONFIG_FLASH_WRITE_SIZE 0x1 /* minimum write size */
+#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* one page size for write */
+#define CONFIG_FLASH_ERASE_SIZE 0x10000
+#define CONFIG_FLASH_BANK_SIZE CONFIG_FLASH_ERASE_SIZE
 
 /* RO image resides at start of protected region, right after header */
-#define CONFIG_RO_STORAGE_OFF	CONFIG_RO_HDR_SIZE
+#define CONFIG_RO_STORAGE_OFF CONFIG_RO_HDR_SIZE
 
 #define CONFIG_RW_STORAGE_OFF 0
 
 /* Use 4k sector erase for NPCX monitor flash erase operations. */
-#define NPCX_MONITOR_FLASH_ERASE_SIZE	0x1000
+#define NPCX_MONITOR_FLASH_ERASE_SIZE 0x1000
 
 #endif /* __CROS_EC_FLASH_CHIP_H */
diff --git a/zephyr/shim/chip/npcx/include/rom_chip.h b/zephyr/shim/chip/npcx/include/rom_chip.h
index aab166e6f1..d59a649c7b 100644
--- a/zephyr/shim/chip/npcx/include/rom_chip.h
+++ b/zephyr/shim/chip/npcx/include/rom_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -38,17 +38,17 @@ enum API_RETURN_STATUS_T {
 };
 
 /* Macro functions of ROM api functions */
-#define ADDR_DOWNLOAD_FROM_FLASH (*(volatile uint32_t *) 0x40)
+#define ADDR_DOWNLOAD_FROM_FLASH (*(volatile uint32_t *)0x40)
 #define download_from_flash(src_offset, dest_addr, size, sign, exe_addr, \
-	status) \
-	(((download_from_flash_ptr) ADDR_DOWNLOAD_FROM_FLASH) \
-	(src_offset, dest_addr, size, sign, exe_addr, status))
+			    status)                                      \
+	(((download_from_flash_ptr)ADDR_DOWNLOAD_FROM_FLASH)(            \
+		src_offset, dest_addr, size, sign, exe_addr, status))
 
 /* Declarations of ROM api functions */
-typedef void (*download_from_flash_ptr) (
+typedef void (*download_from_flash_ptr)(
 	uint32_t src_offset, /* The offset of the data to be downloaded */
-	uint32_t dest_addr,  /* The address of the downloaded data in the RAM*/
-	uint32_t size,       /* Number of bytes to download */
+	uint32_t dest_addr, /* The address of the downloaded data in the RAM*/
+	uint32_t size, /* Number of bytes to download */
 	enum API_SIGN_OPTIONS_T sign, /* Need CRC check or not */
 	uint32_t exe_addr, /* jump to this address after download if not zero */
 	enum API_RETURN_STATUS_T *status /* Status fo download */
diff --git a/zephyr/shim/chip/npcx/include/system_chip.h b/zephyr/shim/chip/npcx/include/system_chip.h
index c77c2a8338..2f59ad4627 100644
--- a/zephyr/shim/chip/npcx/include/system_chip.h
+++ b/zephyr/shim/chip/npcx/include/system_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,24 +6,24 @@
 #ifndef __CROS_EC_SYSTEM_CHIP_H_
 #define __CROS_EC_SYSTEM_CHIP_H_
 
-#define SET_BIT(reg, bit)           ((reg) |= (0x1 << (bit)))
-#define CLEAR_BIT(reg, bit)         ((reg) &= (~(0x1 << (bit))))
+#define SET_BIT(reg, bit) ((reg) |= (0x1 << (bit)))
+#define CLEAR_BIT(reg, bit) ((reg) &= (~(0x1 << (bit))))
 
 /* TODO(b:179900857) Clean this up too */
 #undef IS_BIT_SET
-#define IS_BIT_SET(reg, bit)        (((reg) >> (bit)) & (0x1))
+#define IS_BIT_SET(reg, bit) (((reg) >> (bit)) & (0x1))
 
 /*****************************************************************************/
 /* Memory mapping */
-#define CONFIG_LPRAM_BASE	0x40001400 /* memory address of lpwr ram */
-#define CONFIG_LPRAM_SIZE	0x00000620 /* 1568B low power ram */
+#define CONFIG_LPRAM_BASE 0x40001400 /* memory address of lpwr ram */
+#define CONFIG_LPRAM_SIZE 0x00000620 /* 1568B low power ram */
 
 /******************************************************************************/
 /* Optional M4 Registers */
-#define CPU_MPU_CTRL		REG32(0xE000ED94)
-#define CPU_MPU_RNR		REG32(0xE000ED98)
-#define CPU_MPU_RBAR		REG32(0xE000ED9C)
-#define CPU_MPU_RASR		REG32(0xE000EDA0)
+#define CPU_MPU_CTRL REG32(0xE000ED94)
+#define CPU_MPU_RNR REG32(0xE000ED98)
+#define CPU_MPU_RBAR REG32(0xE000ED9C)
+#define CPU_MPU_RASR REG32(0xE000EDA0)
 
 /*
  * Region assignment. 7 as the highest, a higher index has a higher priority.
@@ -35,18 +35,18 @@
  * made mutually exclusive.
  */
 enum mpu_region {
-	REGION_DATA_RAM = 0,		/* For internal data RAM */
-	REGION_DATA_RAM2 = 1,		/* Second region for unaligned size */
-	REGION_CODE_RAM = 2,		/* For internal code RAM */
-	REGION_CODE_RAM2 = 3,		/* Second region for unaligned size */
-	REGION_STORAGE = 4,		/* For mapped internal storage */
-	REGION_STORAGE2 = 5,		/* Second region for unaligned size */
-	REGION_DATA_RAM_TEXT = 6,	/* Exempt region of data RAM */
-	REGION_CHIP_RESERVED = 7,	/* Reserved for use in chip/ */
+	REGION_DATA_RAM = 0, /* For internal data RAM */
+	REGION_DATA_RAM2 = 1, /* Second region for unaligned size */
+	REGION_CODE_RAM = 2, /* For internal code RAM */
+	REGION_CODE_RAM2 = 3, /* Second region for unaligned size */
+	REGION_STORAGE = 4, /* For mapped internal storage */
+	REGION_STORAGE2 = 5, /* Second region for unaligned size */
+	REGION_DATA_RAM_TEXT = 6, /* Exempt region of data RAM */
+	REGION_CHIP_RESERVED = 7, /* Reserved for use in chip/ */
 	/* only for chips with MPU supporting 16 regions */
-	REGION_UNCACHED_RAM = 8,        /* For uncached data RAM */
-	REGION_UNCACHED_RAM2 = 9,       /* Second region for unaligned size */
-	REGION_ROLLBACK = 10,           /* For rollback */
+	REGION_UNCACHED_RAM = 8, /* For uncached data RAM */
+	REGION_UNCACHED_RAM2 = 9, /* Second region for unaligned size */
+	REGION_ROLLBACK = 10, /* For rollback */
 };
 
 /*
diff --git a/zephyr/shim/chip/npcx/keyboard_raw.c b/zephyr/shim/chip/npcx/keyboard_raw.c
index 86d6af068b..4d43134482 100644
--- a/zephyr/shim/chip/npcx/keyboard_raw.c
+++ b/zephyr/shim/chip/npcx/keyboard_raw.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,7 +10,7 @@
 #include <zephyr/logging/log.h>
 #include <soc.h>
 #include <soc_gpio.h>
-#include <zephyr/zephyr.h>
+#include <zephyr/kernel.h>
 
 #include "drivers/cros_kb_raw.h"
 #include "keyboard_raw.h"
diff --git a/zephyr/shim/chip/npcx/npcx_monitor/CMakeLists.txt b/zephyr/shim/chip/npcx/npcx_monitor/CMakeLists.txt
index 661eb86e91..d74881b2d9 100644
--- a/zephyr/shim/chip/npcx/npcx_monitor/CMakeLists.txt
+++ b/zephyr/shim/chip/npcx/npcx_monitor/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.c b/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.c
index c5ffd40fb5..e3fecc0cbd 100644
--- a/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.c
+++ b/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -54,7 +54,7 @@ void sspi_flash_execute_cmd(uint8_t code, uint8_t cts)
 	/* set UMA_CODE */
 	NPCX_UMA_CODE = code;
 	/* execute UMA flash transaction */
-	NPCX_UMA_CTS  = cts;
+	NPCX_UMA_CTS = cts;
 	while (IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE))
 		;
 }
@@ -81,7 +81,7 @@ void sspi_flash_wait_ready(void)
 	sspi_flash_execute_cmd(CMD_READ_STATUS_REG, MASK_CMD_ONLY);
 	do {
 		/* Read status register */
-		NPCX_UMA_CTS  = MASK_RD_1BYTE;
+		NPCX_UMA_CTS = MASK_RD_1BYTE;
 		while (IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE))
 			;
 	} while (NPCX_UMA_DB0 & mask); /* Wait for Busy clear */
@@ -113,7 +113,7 @@ void sspi_flash_set_address(uint32_t dest_addr)
 }
 
 void sspi_flash_burst_write(unsigned int dest_addr, unsigned int bytes,
-		const char *data)
+			    const char *data)
 {
 	unsigned int i;
 	/* Chip Select down. */
@@ -202,7 +202,7 @@ void sspi_flash_physical_erase(int offset, int size)
 
 	/* Alignment has been checked in upper layer */
 	for (; size > 0; size -= NPCX_MONITOR_FLASH_ERASE_SIZE,
-		offset += NPCX_MONITOR_FLASH_ERASE_SIZE) {
+			 offset += NPCX_MONITOR_FLASH_ERASE_SIZE) {
 		/* Enable write */
 		sspi_flash_write_enable();
 		/* Set erase address */
@@ -226,7 +226,7 @@ int sspi_flash_verify(int offset, int size, const char *data)
 	uint8_t cmp_data;
 
 	ptr_flash = (uint8_t *)(CONFIG_MAPPED_STORAGE_BASE + offset);
-	ptr_mram  = (uint8_t *)data;
+	ptr_mram = (uint8_t *)data;
 	result = 1;
 
 	/* Disable tri-state */
@@ -260,12 +260,11 @@ int sspi_flash_get_image_used(const char *fw_base)
 	for (size--; size > 0 && image[size] != 0xea; size--)
 		;
 
-	return size ? size + 1 : 0;  /* 0xea byte IS part of the image */
-
+	return size ? size + 1 : 0; /* 0xea byte IS part of the image */
 }
 
 /* Entry function of spi upload function */
-uint32_t  __attribute__ ((section(".startup_text")))
+uint32_t __attribute__((section(".startup_text")))
 sspi_flash_upload(int spi_offset, int spi_size)
 {
 	/*
@@ -320,7 +319,7 @@ sspi_flash_upload(int spi_offset, int spi_size)
 		/* Start to write */
 		if (image_base != NULL)
 			sspi_flash_physical_write(spi_offset, sz_image,
-						image_base);
+						  image_base);
 		/* Verify data */
 		if (sspi_flash_verify(spi_offset, sz_image, image_base))
 			*flag_upload |= 0x02;
diff --git a/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.h b/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.h
index c5415d94db..80e605eea0 100644
--- a/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.h
+++ b/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,11 +7,11 @@
 
 #include <stdint.h>
 
-#define NPCX_MONITOR_UUT_TAG      0xA5075001
-#define NPCX_MONITOR_HEADER_ADDR  0x200C3000
+#define NPCX_MONITOR_UUT_TAG 0xA5075001
+#define NPCX_MONITOR_HEADER_ADDR 0x200C3000
 
 /* Flag to record the progress of programming SPI flash */
-#define SPI_PROGRAMMING_FLAG     0x200C4000
+#define SPI_PROGRAMMING_FLAG 0x200C4000
 
 struct monitor_header_tag {
 	/* offset 0x00: TAG NPCX_MONITOR_TAG */
@@ -23,9 +23,9 @@ struct monitor_header_tag {
 	/* offset 0x0C: The Flash address to be programmed (Absolute address) */
 	uint32_t dest_addr;
 	/* offset 0x10: Maximum allowable flash clock frequency */
-	uint8_t  max_clock;
+	uint8_t max_clock;
 	/* offset 0x11: SPI Flash read mode */
-	uint8_t  read_mode;
+	uint8_t read_mode;
 	/* offset 0x12: Reserved */
 	uint16_t reserved;
 } __packed;
diff --git a/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.ld b/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.ld
index 03e38b0609..98892babc6 100644
--- a/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.ld
+++ b/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.ld
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/zephyr/shim/chip/npcx/npcx_monitor/registers.h b/zephyr/shim/chip/npcx/npcx_monitor/registers.h
index cc0a6b96fe..85ab3b2389 100644
--- a/zephyr/shim/chip/npcx/npcx_monitor/registers.h
+++ b/zephyr/shim/chip/npcx/npcx_monitor/registers.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -21,32 +21,32 @@
 #define REG64_ADDR(addr) ((volatile uint64_t *)(addr))
 #define REG32_ADDR(addr) ((volatile uint32_t *)(addr))
 #define REG16_ADDR(addr) ((volatile uint16_t *)(addr))
-#define REG8_ADDR(addr)  ((volatile uint8_t  *)(addr))
+#define REG8_ADDR(addr) ((volatile uint8_t *)(addr))
 
 #define REG64(addr) (*REG64_ADDR(addr))
 #define REG32(addr) (*REG32_ADDR(addr))
 #define REG16(addr) (*REG16_ADDR(addr))
-#define REG8(addr)  (*REG8_ADDR(addr))
+#define REG8(addr) (*REG8_ADDR(addr))
 
 /* Standard macros / definitions */
 #define GENERIC_MAX(x, y) ((x) > (y) ? (x) : (y))
 #define GENERIC_MIN(x, y) ((x) < (y) ? (x) : (y))
 #ifndef MAX
-#define MAX(a, b)					\
-	({						\
-		__typeof__(a) temp_a = (a);		\
-		__typeof__(b) temp_b = (b);		\
-							\
-		GENERIC_MAX(temp_a, temp_b);		\
+#define MAX(a, b)                            \
+	({                                   \
+		__typeof__(a) temp_a = (a);  \
+		__typeof__(b) temp_b = (b);  \
+                                             \
+		GENERIC_MAX(temp_a, temp_b); \
 	})
 #endif
 #ifndef MIN
-#define MIN(a, b)					\
-	({						\
-		__typeof__(a) temp_a = (a);		\
-		__typeof__(b) temp_b = (b);		\
-							\
-		GENERIC_MIN(temp_a, temp_b);		\
+#define MIN(a, b)                            \
+	({                                   \
+		__typeof__(a) temp_a = (a);  \
+		__typeof__(b) temp_b = (b);  \
+                                             \
+		GENERIC_MIN(temp_a, temp_b); \
 	})
 #endif
 #ifndef NULL
@@ -58,32 +58,35 @@
  * Macro Functions
  */
 /* Bit functions */
-#define SET_BIT(reg, bit)           ((reg) |= (0x1 << (bit)))
-#define CLEAR_BIT(reg, bit)         ((reg) &= (~(0x1 << (bit))))
-#define IS_BIT_SET(reg, bit)        (((reg) >> (bit)) & (0x1))
-#define UPDATE_BIT(reg, bit, cond)  {	if (cond) \
-						SET_BIT(reg, bit); \
-					else \
-						CLEAR_BIT(reg, bit); }
+#define SET_BIT(reg, bit) ((reg) |= (0x1 << (bit)))
+#define CLEAR_BIT(reg, bit) ((reg) &= (~(0x1 << (bit))))
+#define IS_BIT_SET(reg, bit) (((reg) >> (bit)) & (0x1))
+#define UPDATE_BIT(reg, bit, cond)           \
+	{                                    \
+		if (cond)                    \
+			SET_BIT(reg, bit);   \
+		else                         \
+			CLEAR_BIT(reg, bit); \
+	}
 /* Field functions */
-#define GET_POS_FIELD(pos, size)    pos
-#define GET_SIZE_FIELD(pos, size)   size
-#define FIELD_POS(field)            GET_POS_##field
-#define FIELD_SIZE(field)           GET_SIZE_##field
+#define GET_POS_FIELD(pos, size) pos
+#define GET_SIZE_FIELD(pos, size) size
+#define FIELD_POS(field) GET_POS_##field
+#define FIELD_SIZE(field) GET_SIZE_##field
 /* Read field functions */
 #define GET_FIELD(reg, field) \
 	_GET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field))
-#define _GET_FIELD_(reg, f_pos, f_size) (((reg)>>(f_pos)) & ((1<<(f_size))-1))
+#define _GET_FIELD_(reg, f_pos, f_size) \
+	(((reg) >> (f_pos)) & ((1 << (f_size)) - 1))
 /* Write field functions */
 #define SET_FIELD(reg, field, value) \
 	_SET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field), value)
-#define _SET_FIELD_(reg, f_pos, f_size, value) \
-	((reg) = ((reg) & (~(((1 << (f_size))-1) << (f_pos)))) \
-			| ((value) << (f_pos)))
-
+#define _SET_FIELD_(reg, f_pos, f_size, value)                     \
+	((reg) = ((reg) & (~(((1 << (f_size)) - 1) << (f_pos)))) | \
+		 ((value) << (f_pos)))
 
 /* NPCX7 & NPCX9 */
-#define NPCX_DEVALT(n)			REG8(NPCX_SCFG_BASE_ADDR + 0x010 + (n))
+#define NPCX_DEVALT(n) REG8(NPCX_SCFG_BASE_ADDR + 0x010 + (n))
 
 /******************************************************************************/
 /*
@@ -91,270 +94,267 @@
  */
 
 /* Modules Map */
-#define NPCX_ESPI_BASE_ADDR              0x4000A000
-#define NPCX_MDC_BASE_ADDR               0x4000C000
-#define NPCX_PMC_BASE_ADDR               0x4000D000
-#define NPCX_SIB_BASE_ADDR               0x4000E000
-#define NPCX_SHI_BASE_ADDR               0x4000F000
-#define NPCX_SHM_BASE_ADDR               0x40010000
-#define NPCX_GDMA_BASE_ADDR              0x40011000
-#define NPCX_FIU_BASE_ADDR               0x40020000
-#define NPCX_KBSCAN_REGS_BASE            0x400A3000
-#define NPCX_WOV_BASE_ADDR               0x400A4000
-#define NPCX_APM_BASE_ADDR               0x400A4800
-#define NPCX_GLUE_REGS_BASE              0x400A5000
-#define NPCX_BBRAM_BASE_ADDR             0x400AF000
-#define NPCX_PS2_BASE_ADDR               0x400B1000
-#define NPCX_HFCG_BASE_ADDR              0x400B5000
-#define NPCX_LFCG_BASE_ADDR              0x400B5100
-#define NPCX_FMUL2_BASE_ADDR             0x400B5200
-#define NPCX_MTC_BASE_ADDR               0x400B7000
-#define NPCX_MSWC_BASE_ADDR              0x400C1000
-#define NPCX_SCFG_BASE_ADDR              0x400C3000
-#define NPCX_KBC_BASE_ADDR               0x400C7000
-#define NPCX_ADC_BASE_ADDR               0x400D1000
-#define NPCX_SPI_BASE_ADDR               0x400D2000
-#define NPCX_PECI_BASE_ADDR              0x400D4000
-#define NPCX_TWD_BASE_ADDR               0x400D8000
+#define NPCX_ESPI_BASE_ADDR 0x4000A000
+#define NPCX_MDC_BASE_ADDR 0x4000C000
+#define NPCX_PMC_BASE_ADDR 0x4000D000
+#define NPCX_SIB_BASE_ADDR 0x4000E000
+#define NPCX_SHI_BASE_ADDR 0x4000F000
+#define NPCX_SHM_BASE_ADDR 0x40010000
+#define NPCX_GDMA_BASE_ADDR 0x40011000
+#define NPCX_FIU_BASE_ADDR 0x40020000
+#define NPCX_KBSCAN_REGS_BASE 0x400A3000
+#define NPCX_WOV_BASE_ADDR 0x400A4000
+#define NPCX_APM_BASE_ADDR 0x400A4800
+#define NPCX_GLUE_REGS_BASE 0x400A5000
+#define NPCX_BBRAM_BASE_ADDR 0x400AF000
+#define NPCX_PS2_BASE_ADDR 0x400B1000
+#define NPCX_HFCG_BASE_ADDR 0x400B5000
+#define NPCX_LFCG_BASE_ADDR 0x400B5100
+#define NPCX_FMUL2_BASE_ADDR 0x400B5200
+#define NPCX_MTC_BASE_ADDR 0x400B7000
+#define NPCX_MSWC_BASE_ADDR 0x400C1000
+#define NPCX_SCFG_BASE_ADDR 0x400C3000
+#define NPCX_KBC_BASE_ADDR 0x400C7000
+#define NPCX_ADC_BASE_ADDR 0x400D1000
+#define NPCX_SPI_BASE_ADDR 0x400D2000
+#define NPCX_PECI_BASE_ADDR 0x400D4000
+#define NPCX_TWD_BASE_ADDR 0x400D8000
 
 /* Multi-Modules Map */
-#define NPCX_PWM_BASE_ADDR(mdl)          (0x40080000 + ((mdl) * 0x2000L))
-#define NPCX_GPIO_BASE_ADDR(mdl)         (0x40081000 + ((mdl) * 0x2000L))
-#define NPCX_ITIM_BASE_ADDR(mdl)         (0x400B0000 + ((mdl) * 0x2000L))
-#define NPCX_MIWU_BASE_ADDR(mdl)         (0x400BB000 + ((mdl) * 0x2000L))
-#define NPCX_MFT_BASE_ADDR(mdl)          (0x400E1000 + ((mdl) * 0x2000L))
-#define NPCX_PM_CH_BASE_ADDR(mdl)        (0x400C9000 + ((mdl) * 0x2000L))
-
+#define NPCX_PWM_BASE_ADDR(mdl) (0x40080000 + ((mdl)*0x2000L))
+#define NPCX_GPIO_BASE_ADDR(mdl) (0x40081000 + ((mdl)*0x2000L))
+#define NPCX_ITIM_BASE_ADDR(mdl) (0x400B0000 + ((mdl)*0x2000L))
+#define NPCX_MIWU_BASE_ADDR(mdl) (0x400BB000 + ((mdl)*0x2000L))
+#define NPCX_MFT_BASE_ADDR(mdl) (0x400E1000 + ((mdl)*0x2000L))
+#define NPCX_PM_CH_BASE_ADDR(mdl) (0x400C9000 + ((mdl)*0x2000L))
 
 /******************************************************************************/
 /* System Configuration (SCFG) Registers */
-#define NPCX_DEVCNT                       REG8(NPCX_SCFG_BASE_ADDR + 0x000)
-#define NPCX_STRPST                       REG8(NPCX_SCFG_BASE_ADDR + 0x001)
-#define NPCX_RSTCTL                       REG8(NPCX_SCFG_BASE_ADDR + 0x002)
-#define NPCX_DEV_CTL4                     REG8(NPCX_SCFG_BASE_ADDR + 0x006)
-#define NPCX_LFCGCALCNT                   REG8(NPCX_SCFG_BASE_ADDR + 0x021)
-#define NPCX_PUPD_EN0                     REG8(NPCX_SCFG_BASE_ADDR + 0x028)
-#define NPCX_PUPD_EN1                     REG8(NPCX_SCFG_BASE_ADDR + 0x029)
-#define NPCX_SCFG_VER                     REG8(NPCX_SCFG_BASE_ADDR + 0x02F)
-
-#define TEST_BKSL                         REG8(NPCX_SCFG_BASE_ADDR + 0x037)
-#define TEST0                             REG8(NPCX_SCFG_BASE_ADDR + 0x038)
-#define BLKSEL                           0
+#define NPCX_DEVCNT REG8(NPCX_SCFG_BASE_ADDR + 0x000)
+#define NPCX_STRPST REG8(NPCX_SCFG_BASE_ADDR + 0x001)
+#define NPCX_RSTCTL REG8(NPCX_SCFG_BASE_ADDR + 0x002)
+#define NPCX_DEV_CTL4 REG8(NPCX_SCFG_BASE_ADDR + 0x006)
+#define NPCX_LFCGCALCNT REG8(NPCX_SCFG_BASE_ADDR + 0x021)
+#define NPCX_PUPD_EN0 REG8(NPCX_SCFG_BASE_ADDR + 0x028)
+#define NPCX_PUPD_EN1 REG8(NPCX_SCFG_BASE_ADDR + 0x029)
+#define NPCX_SCFG_VER REG8(NPCX_SCFG_BASE_ADDR + 0x02F)
+
+#define TEST_BKSL REG8(NPCX_SCFG_BASE_ADDR + 0x037)
+#define TEST0 REG8(NPCX_SCFG_BASE_ADDR + 0x038)
+#define BLKSEL 0
 
 /* SCFG register fields */
-#define NPCX_DEVCNT_F_SPI_TRIS           6
-#define NPCX_DEVCNT_HIF_TYP_SEL_FIELD    FIELD(2, 2)
-#define NPCX_DEVCNT_JEN1_HEN             5
-#define NPCX_DEVCNT_JEN0_HEN             4
-#define NPCX_STRPST_TRIST                1
-#define NPCX_STRPST_TEST                 2
-#define NPCX_STRPST_JEN1                 4
-#define NPCX_STRPST_JEN0                 5
-#define NPCX_STRPST_SPI_COMP             7
-#define NPCX_RSTCTL_VCC1_RST_STS         0
-#define NPCX_RSTCTL_DBGRST_STS           1
-#define NPCX_RSTCTL_VCC1_RST_SCRATCH     3
-#define NPCX_RSTCTL_LRESET_PLTRST_MODE   5
-#define NPCX_RSTCTL_HIPRST_MODE          6
-#define NPCX_DEV_CTL4_F_SPI_SLLK         2
-#define NPCX_DEV_CTL4_SPI_SP_SEL         4
-#define NPCX_DEV_CTL4_WP_IF              5
-#define NPCX_DEV_CTL4_VCC1_RST_LK        6
-#define NPCX_DEVPU0_I2C0_0_PUE           0
-#define NPCX_DEVPU0_I2C0_1_PUE           1
-#define NPCX_DEVPU0_I2C1_0_PUE           2
-#define NPCX_DEVPU0_I2C2_0_PUE           4
-#define NPCX_DEVPU0_I2C3_0_PUE           6
-#define NPCX_DEVPU1_F_SPI_PUD_EN         7
+#define NPCX_DEVCNT_F_SPI_TRIS 6
+#define NPCX_DEVCNT_HIF_TYP_SEL_FIELD FIELD(2, 2)
+#define NPCX_DEVCNT_JEN1_HEN 5
+#define NPCX_DEVCNT_JEN0_HEN 4
+#define NPCX_STRPST_TRIST 1
+#define NPCX_STRPST_TEST 2
+#define NPCX_STRPST_JEN1 4
+#define NPCX_STRPST_JEN0 5
+#define NPCX_STRPST_SPI_COMP 7
+#define NPCX_RSTCTL_VCC1_RST_STS 0
+#define NPCX_RSTCTL_DBGRST_STS 1
+#define NPCX_RSTCTL_VCC1_RST_SCRATCH 3
+#define NPCX_RSTCTL_LRESET_PLTRST_MODE 5
+#define NPCX_RSTCTL_HIPRST_MODE 6
+#define NPCX_DEV_CTL4_F_SPI_SLLK 2
+#define NPCX_DEV_CTL4_SPI_SP_SEL 4
+#define NPCX_DEV_CTL4_WP_IF 5
+#define NPCX_DEV_CTL4_VCC1_RST_LK 6
+#define NPCX_DEVPU0_I2C0_0_PUE 0
+#define NPCX_DEVPU0_I2C0_1_PUE 1
+#define NPCX_DEVPU0_I2C1_0_PUE 2
+#define NPCX_DEVPU0_I2C2_0_PUE 4
+#define NPCX_DEVPU0_I2C3_0_PUE 6
+#define NPCX_DEVPU1_F_SPI_PUD_EN 7
 
 /* DEVALT */
 /* pin-mux for SPI/FIU */
-#define NPCX_DEVALT0_SPIP_SL             0
-#define NPCX_DEVALT0_GPIO_NO_SPIP        3
-#define NPCX_DEVALT0_F_SPI_CS1_2         4
-#define NPCX_DEVALT0_F_SPI_CS1_1         5
-#define NPCX_DEVALT0_F_SPI_QUAD          6
-#define NPCX_DEVALT0_NO_F_SPI            7
+#define NPCX_DEVALT0_SPIP_SL 0
+#define NPCX_DEVALT0_GPIO_NO_SPIP 3
+#define NPCX_DEVALT0_F_SPI_CS1_2 4
+#define NPCX_DEVALT0_F_SPI_CS1_1 5
+#define NPCX_DEVALT0_F_SPI_QUAD 6
+#define NPCX_DEVALT0_NO_F_SPI 7
 
 /******************************************************************************/
 /* Flash Interface Unit (FIU) Registers */
-#define NPCX_FIU_CFG                      REG8(NPCX_FIU_BASE_ADDR + 0x000)
-#define NPCX_BURST_CFG                    REG8(NPCX_FIU_BASE_ADDR + 0x001)
-#define NPCX_RESP_CFG                     REG8(NPCX_FIU_BASE_ADDR + 0x002)
-#define NPCX_SPI_FL_CFG                   REG8(NPCX_FIU_BASE_ADDR + 0x014)
-#define NPCX_UMA_CODE                     REG8(NPCX_FIU_BASE_ADDR + 0x016)
-#define NPCX_UMA_AB0                      REG8(NPCX_FIU_BASE_ADDR + 0x017)
-#define NPCX_UMA_AB1                      REG8(NPCX_FIU_BASE_ADDR + 0x018)
-#define NPCX_UMA_AB2                      REG8(NPCX_FIU_BASE_ADDR + 0x019)
-#define NPCX_UMA_DB0                      REG8(NPCX_FIU_BASE_ADDR + 0x01A)
-#define NPCX_UMA_DB1                      REG8(NPCX_FIU_BASE_ADDR + 0x01B)
-#define NPCX_UMA_DB2                      REG8(NPCX_FIU_BASE_ADDR + 0x01C)
-#define NPCX_UMA_DB3                      REG8(NPCX_FIU_BASE_ADDR + 0x01D)
-#define NPCX_UMA_CTS                      REG8(NPCX_FIU_BASE_ADDR + 0x01E)
-#define NPCX_UMA_ECTS                     REG8(NPCX_FIU_BASE_ADDR + 0x01F)
-#define NPCX_UMA_DB0_3                   REG32(NPCX_FIU_BASE_ADDR + 0x020)
-#define NPCX_FIU_RD_CMD                   REG8(NPCX_FIU_BASE_ADDR + 0x030)
-#define NPCX_FIU_DMM_CYC                  REG8(NPCX_FIU_BASE_ADDR + 0x032)
-#define NPCX_FIU_EXT_CFG                  REG8(NPCX_FIU_BASE_ADDR + 0x033)
-#define NPCX_FIU_UMA_AB0_3               REG32(NPCX_FIU_BASE_ADDR + 0x034)
+#define NPCX_FIU_CFG REG8(NPCX_FIU_BASE_ADDR + 0x000)
+#define NPCX_BURST_CFG REG8(NPCX_FIU_BASE_ADDR + 0x001)
+#define NPCX_RESP_CFG REG8(NPCX_FIU_BASE_ADDR + 0x002)
+#define NPCX_SPI_FL_CFG REG8(NPCX_FIU_BASE_ADDR + 0x014)
+#define NPCX_UMA_CODE REG8(NPCX_FIU_BASE_ADDR + 0x016)
+#define NPCX_UMA_AB0 REG8(NPCX_FIU_BASE_ADDR + 0x017)
+#define NPCX_UMA_AB1 REG8(NPCX_FIU_BASE_ADDR + 0x018)
+#define NPCX_UMA_AB2 REG8(NPCX_FIU_BASE_ADDR + 0x019)
+#define NPCX_UMA_DB0 REG8(NPCX_FIU_BASE_ADDR + 0x01A)
+#define NPCX_UMA_DB1 REG8(NPCX_FIU_BASE_ADDR + 0x01B)
+#define NPCX_UMA_DB2 REG8(NPCX_FIU_BASE_ADDR + 0x01C)
+#define NPCX_UMA_DB3 REG8(NPCX_FIU_BASE_ADDR + 0x01D)
+#define NPCX_UMA_CTS REG8(NPCX_FIU_BASE_ADDR + 0x01E)
+#define NPCX_UMA_ECTS REG8(NPCX_FIU_BASE_ADDR + 0x01F)
+#define NPCX_UMA_DB0_3 REG32(NPCX_FIU_BASE_ADDR + 0x020)
+#define NPCX_FIU_RD_CMD REG8(NPCX_FIU_BASE_ADDR + 0x030)
+#define NPCX_FIU_DMM_CYC REG8(NPCX_FIU_BASE_ADDR + 0x032)
+#define NPCX_FIU_EXT_CFG REG8(NPCX_FIU_BASE_ADDR + 0x033)
+#define NPCX_FIU_UMA_AB0_3 REG32(NPCX_FIU_BASE_ADDR + 0x034)
 
 /* FIU register fields */
-#define NPCX_RESP_CFG_IAD_EN             0
-#define NPCX_RESP_CFG_DEV_SIZE_EX        2
-#define NPCX_UMA_CTS_A_SIZE              3
-#define NPCX_UMA_CTS_C_SIZE              4
-#define NPCX_UMA_CTS_RD_WR               5
-#define NPCX_UMA_CTS_DEV_NUM             6
-#define NPCX_UMA_CTS_EXEC_DONE           7
-#define NPCX_UMA_ECTS_SW_CS0             0
-#define NPCX_UMA_ECTS_SW_CS1             1
-#define NPCX_UMA_ECTS_SEC_CS             2
-#define NPCX_UMA_ECTS_UMA_LOCK           3
+#define NPCX_RESP_CFG_IAD_EN 0
+#define NPCX_RESP_CFG_DEV_SIZE_EX 2
+#define NPCX_UMA_CTS_A_SIZE 3
+#define NPCX_UMA_CTS_C_SIZE 4
+#define NPCX_UMA_CTS_RD_WR 5
+#define NPCX_UMA_CTS_DEV_NUM 6
+#define NPCX_UMA_CTS_EXEC_DONE 7
+#define NPCX_UMA_ECTS_SW_CS0 0
+#define NPCX_UMA_ECTS_SW_CS1 1
+#define NPCX_UMA_ECTS_SEC_CS 2
+#define NPCX_UMA_ECTS_UMA_LOCK 3
 
 /******************************************************************************/
 /* KBC Registers */
-#define NPCX_HICTRL                       REG8(NPCX_KBC_BASE_ADDR + 0x000)
-#define NPCX_HIIRQC                       REG8(NPCX_KBC_BASE_ADDR + 0x002)
-#define NPCX_HIKMST                       REG8(NPCX_KBC_BASE_ADDR + 0x004)
-#define NPCX_HIKDO                        REG8(NPCX_KBC_BASE_ADDR + 0x006)
-#define NPCX_HIMDO                        REG8(NPCX_KBC_BASE_ADDR + 0x008)
-#define NPCX_KBCVER                       REG8(NPCX_KBC_BASE_ADDR + 0x009)
-#define NPCX_HIKMDI                       REG8(NPCX_KBC_BASE_ADDR + 0x00A)
-#define NPCX_SHIKMDI                      REG8(NPCX_KBC_BASE_ADDR + 0x00B)
+#define NPCX_HICTRL REG8(NPCX_KBC_BASE_ADDR + 0x000)
+#define NPCX_HIIRQC REG8(NPCX_KBC_BASE_ADDR + 0x002)
+#define NPCX_HIKMST REG8(NPCX_KBC_BASE_ADDR + 0x004)
+#define NPCX_HIKDO REG8(NPCX_KBC_BASE_ADDR + 0x006)
+#define NPCX_HIMDO REG8(NPCX_KBC_BASE_ADDR + 0x008)
+#define NPCX_KBCVER REG8(NPCX_KBC_BASE_ADDR + 0x009)
+#define NPCX_HIKMDI REG8(NPCX_KBC_BASE_ADDR + 0x00A)
+#define NPCX_SHIKMDI REG8(NPCX_KBC_BASE_ADDR + 0x00B)
 
 /* KBC register field */
-#define NPCX_HICTRL_OBFKIE               0 /* Automatic Serial IRQ1 for KBC */
-#define NPCX_HICTRL_OBFMIE               1 /* Automatic Serial IRQ12 for Mouse*/
-#define NPCX_HICTRL_OBECIE               2 /* KBC OBE interrupt enable */
-#define NPCX_HICTRL_IBFCIE               3 /* KBC IBF interrupt enable */
-#define NPCX_HICTRL_PMIHIE               4 /* Automatic Serial IRQ11 for PMC1 */
-#define NPCX_HICTRL_PMIOCIE              5 /* PMC1 OBE interrupt enable */
-#define NPCX_HICTRL_PMICIE               6 /* PMC1 IBF interrupt enable */
-#define NPCX_HICTRL_FW_OBF               7 /* Firmware control over OBF */
+#define NPCX_HICTRL_OBFKIE 0 /* Automatic Serial IRQ1 for KBC */
+#define NPCX_HICTRL_OBFMIE 1 /* Automatic Serial IRQ12 for Mouse*/
+#define NPCX_HICTRL_OBECIE 2 /* KBC OBE interrupt enable */
+#define NPCX_HICTRL_IBFCIE 3 /* KBC IBF interrupt enable */
+#define NPCX_HICTRL_PMIHIE 4 /* Automatic Serial IRQ11 for PMC1 */
+#define NPCX_HICTRL_PMIOCIE 5 /* PMC1 OBE interrupt enable */
+#define NPCX_HICTRL_PMICIE 6 /* PMC1 IBF interrupt enable */
+#define NPCX_HICTRL_FW_OBF 7 /* Firmware control over OBF */
 
-#define NPCX_HIKMST_OBF                  0 /* KB output buffer is full */
+#define NPCX_HIKMST_OBF 0 /* KB output buffer is full */
 
 /******************************************************************************/
 /* Timer Watch Dog (TWD) Registers */
-#define NPCX_TWCFG                        REG8(NPCX_TWD_BASE_ADDR + 0x000)
-#define NPCX_TWCP                         REG8(NPCX_TWD_BASE_ADDR + 0x002)
-#define NPCX_TWDT0                       REG16(NPCX_TWD_BASE_ADDR + 0x004)
-#define NPCX_T0CSR                        REG8(NPCX_TWD_BASE_ADDR + 0x006)
-#define NPCX_WDCNT                        REG8(NPCX_TWD_BASE_ADDR + 0x008)
-#define NPCX_WDSDM                        REG8(NPCX_TWD_BASE_ADDR + 0x00A)
-#define NPCX_TWMT0                       REG16(NPCX_TWD_BASE_ADDR + 0x00C)
-#define NPCX_TWMWD                        REG8(NPCX_TWD_BASE_ADDR + 0x00E)
-#define NPCX_WDCP                         REG8(NPCX_TWD_BASE_ADDR + 0x010)
+#define NPCX_TWCFG REG8(NPCX_TWD_BASE_ADDR + 0x000)
+#define NPCX_TWCP REG8(NPCX_TWD_BASE_ADDR + 0x002)
+#define NPCX_TWDT0 REG16(NPCX_TWD_BASE_ADDR + 0x004)
+#define NPCX_T0CSR REG8(NPCX_TWD_BASE_ADDR + 0x006)
+#define NPCX_WDCNT REG8(NPCX_TWD_BASE_ADDR + 0x008)
+#define NPCX_WDSDM REG8(NPCX_TWD_BASE_ADDR + 0x00A)
+#define NPCX_TWMT0 REG16(NPCX_TWD_BASE_ADDR + 0x00C)
+#define NPCX_TWMWD REG8(NPCX_TWD_BASE_ADDR + 0x00E)
+#define NPCX_WDCP REG8(NPCX_TWD_BASE_ADDR + 0x010)
 
 /* TWD register fields */
-#define NPCX_TWCFG_LTWCFG                0
-#define NPCX_TWCFG_LTWCP                 1
-#define NPCX_TWCFG_LTWDT0                2
-#define NPCX_TWCFG_LWDCNT                3
-#define NPCX_TWCFG_WDCT0I                4
-#define NPCX_TWCFG_WDSDME                5
-#define NPCX_TWCFG_WDRST_MODE            6
-#define NPCX_TWCFG_WDC2POR               7
-#define NPCX_T0CSR_RST                   0
-#define NPCX_T0CSR_TC                    1
-#define NPCX_T0CSR_WDLTD                 3
-#define NPCX_T0CSR_WDRST_STS             4
-#define NPCX_T0CSR_WD_RUN                5
-#define NPCX_T0CSR_TESDIS                7
+#define NPCX_TWCFG_LTWCFG 0
+#define NPCX_TWCFG_LTWCP 1
+#define NPCX_TWCFG_LTWDT0 2
+#define NPCX_TWCFG_LWDCNT 3
+#define NPCX_TWCFG_WDCT0I 4
+#define NPCX_TWCFG_WDSDME 5
+#define NPCX_TWCFG_WDRST_MODE 6
+#define NPCX_TWCFG_WDC2POR 7
+#define NPCX_T0CSR_RST 0
+#define NPCX_T0CSR_TC 1
+#define NPCX_T0CSR_WDLTD 3
+#define NPCX_T0CSR_WDRST_STS 4
+#define NPCX_T0CSR_WD_RUN 5
+#define NPCX_T0CSR_TESDIS 7
 
 /******************************************************************************/
 /* SPI Register */
-#define NPCX_SPI_DATA                    REG16(NPCX_SPI_BASE_ADDR + 0x00)
-#define NPCX_SPI_CTL1                    REG16(NPCX_SPI_BASE_ADDR + 0x02)
-#define NPCX_SPI_STAT                     REG8(NPCX_SPI_BASE_ADDR + 0x04)
+#define NPCX_SPI_DATA REG16(NPCX_SPI_BASE_ADDR + 0x00)
+#define NPCX_SPI_CTL1 REG16(NPCX_SPI_BASE_ADDR + 0x02)
+#define NPCX_SPI_STAT REG8(NPCX_SPI_BASE_ADDR + 0x04)
 
 /* SPI register fields */
-#define NPCX_SPI_CTL1_SPIEN              0
-#define NPCX_SPI_CTL1_SNM                1
-#define NPCX_SPI_CTL1_MOD                2
-#define NPCX_SPI_CTL1_EIR                5
-#define NPCX_SPI_CTL1_EIW                6
-#define NPCX_SPI_CTL1_SCM                7
-#define NPCX_SPI_CTL1_SCIDL              8
-#define NPCX_SPI_CTL1_SCDV               9
-#define NPCX_SPI_STAT_BSY                0
-#define NPCX_SPI_STAT_RBF                1
+#define NPCX_SPI_CTL1_SPIEN 0
+#define NPCX_SPI_CTL1_SNM 1
+#define NPCX_SPI_CTL1_MOD 2
+#define NPCX_SPI_CTL1_EIR 5
+#define NPCX_SPI_CTL1_EIW 6
+#define NPCX_SPI_CTL1_SCM 7
+#define NPCX_SPI_CTL1_SCIDL 8
+#define NPCX_SPI_CTL1_SCDV 9
+#define NPCX_SPI_STAT_BSY 0
+#define NPCX_SPI_STAT_RBF 1
 
 /******************************************************************************/
 /* Flash Utiltiy definition */
 /*
  *  Flash commands for the W25Q16CV SPI flash
  */
-#define CMD_READ_ID                      0x9F
-#define CMD_READ_MAN_DEV_ID              0x90
-#define CMD_WRITE_EN                     0x06
-#define CMD_WRITE_STATUS                 0x50
-#define CMD_READ_STATUS_REG              0x05
-#define CMD_READ_STATUS_REG2             0x35
-#define CMD_WRITE_STATUS_REG             0x01
-#define CMD_FLASH_PROGRAM                0x02
-#define CMD_SECTOR_ERASE                 0x20
-#define CMD_BLOCK_32K_ERASE              0x52
-#define CMD_BLOCK_64K_ERASE              0xd8
-#define CMD_PROGRAM_UINT_SIZE            0x08
-#define CMD_PAGE_SIZE                    0x00
-#define CMD_READ_ID_TYPE                 0x47
-#define CMD_FAST_READ                    0x0B
+#define CMD_READ_ID 0x9F
+#define CMD_READ_MAN_DEV_ID 0x90
+#define CMD_WRITE_EN 0x06
+#define CMD_WRITE_STATUS 0x50
+#define CMD_READ_STATUS_REG 0x05
+#define CMD_READ_STATUS_REG2 0x35
+#define CMD_WRITE_STATUS_REG 0x01
+#define CMD_FLASH_PROGRAM 0x02
+#define CMD_SECTOR_ERASE 0x20
+#define CMD_BLOCK_32K_ERASE 0x52
+#define CMD_BLOCK_64K_ERASE 0xd8
+#define CMD_PROGRAM_UINT_SIZE 0x08
+#define CMD_PAGE_SIZE 0x00
+#define CMD_READ_ID_TYPE 0x47
+#define CMD_FAST_READ 0x0B
 
 /*
  * Status registers for the W25Q16CV SPI flash
  */
-#define SPI_FLASH_SR2_SUS               BIT(7)
-#define SPI_FLASH_SR2_CMP               BIT(6)
-#define SPI_FLASH_SR2_LB3               BIT(5)
-#define SPI_FLASH_SR2_LB2               BIT(4)
-#define SPI_FLASH_SR2_LB1               BIT(3)
-#define SPI_FLASH_SR2_QE                BIT(1)
-#define SPI_FLASH_SR2_SRP1              BIT(0)
-#define SPI_FLASH_SR1_SRP0              BIT(7)
-#define SPI_FLASH_SR1_SEC               BIT(6)
-#define SPI_FLASH_SR1_TB                BIT(5)
-#define SPI_FLASH_SR1_BP2               BIT(4)
-#define SPI_FLASH_SR1_BP1               BIT(3)
-#define SPI_FLASH_SR1_BP0               BIT(2)
-#define SPI_FLASH_SR1_WEL               BIT(1)
-#define SPI_FLASH_SR1_BUSY              BIT(0)
-
+#define SPI_FLASH_SR2_SUS BIT(7)
+#define SPI_FLASH_SR2_CMP BIT(6)
+#define SPI_FLASH_SR2_LB3 BIT(5)
+#define SPI_FLASH_SR2_LB2 BIT(4)
+#define SPI_FLASH_SR2_LB1 BIT(3)
+#define SPI_FLASH_SR2_QE BIT(1)
+#define SPI_FLASH_SR2_SRP1 BIT(0)
+#define SPI_FLASH_SR1_SRP0 BIT(7)
+#define SPI_FLASH_SR1_SEC BIT(6)
+#define SPI_FLASH_SR1_TB BIT(5)
+#define SPI_FLASH_SR1_BP2 BIT(4)
+#define SPI_FLASH_SR1_BP1 BIT(3)
+#define SPI_FLASH_SR1_BP0 BIT(2)
+#define SPI_FLASH_SR1_WEL BIT(1)
+#define SPI_FLASH_SR1_BUSY BIT(0)
 
 /* 0: F_CS0 1: F_CS1_1(GPIO86) 2:F_CS1_2(GPIOA6) */
-#define FIU_CHIP_SELECT		0
+#define FIU_CHIP_SELECT 0
 /* Create UMA control mask */
-#define MASK(bit)       (0x1 << (bit))
-#define A_SIZE          0x03	/* 0: No ADR field 1: 3-bytes ADR field */
-#define C_SIZE          0x04	/* 0: 1-Byte CMD field 1:No CMD field */
-#define RD_WR           0x05	/* 0: Read 1: Write */
-#define DEV_NUM         0x06	/* 0: PVT is used 1: SHD is used */
-#define EXEC_DONE       0x07
-#define D_SIZE_1        0x01
-#define D_SIZE_2        0x02
-#define D_SIZE_3        0x03
-#define D_SIZE_4        0x04
-#define FLASH_SEL       MASK(DEV_NUM)
-
-#define MASK_CMD_ONLY   (MASK(EXEC_DONE) | FLASH_SEL)
-#define MASK_CMD_ADR    (MASK(EXEC_DONE) | FLASH_SEL | MASK(A_SIZE))
-#define MASK_CMD_ADR_WR (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR)  \
-			|MASK(A_SIZE) | D_SIZE_1)
-#define MASK_RD_1BYTE   (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_1)
-#define MASK_RD_2BYTE   (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_2)
-#define MASK_RD_3BYTE   (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_3)
-#define MASK_RD_4BYTE   (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_4)
-#define MASK_CMD_RD_1BYTE       (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_1)
-#define MASK_CMD_RD_2BYTE       (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_2)
-#define MASK_CMD_RD_3BYTE       (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_3)
-#define MASK_CMD_RD_4BYTE       (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_4)
-#define MASK_CMD_WR_ONLY        (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR))
-#define MASK_CMD_WR_1BYTE       (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) \
-				| MASK(C_SIZE) | D_SIZE_1)
-#define MASK_CMD_WR_2BYTE       (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) \
-				| MASK(C_SIZE) | D_SIZE_2)
-#define MASK_CMD_WR_ADR         (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) \
-				| MASK(A_SIZE))
-
+#define MASK(bit) (0x1 << (bit))
+#define A_SIZE 0x03 /* 0: No ADR field 1: 3-bytes ADR field */
+#define C_SIZE 0x04 /* 0: 1-Byte CMD field 1:No CMD field */
+#define RD_WR 0x05 /* 0: Read 1: Write */
+#define DEV_NUM 0x06 /* 0: PVT is used 1: SHD is used */
+#define EXEC_DONE 0x07
+#define D_SIZE_1 0x01
+#define D_SIZE_2 0x02
+#define D_SIZE_3 0x03
+#define D_SIZE_4 0x04
+#define FLASH_SEL MASK(DEV_NUM)
+
+#define MASK_CMD_ONLY (MASK(EXEC_DONE) | FLASH_SEL)
+#define MASK_CMD_ADR (MASK(EXEC_DONE) | FLASH_SEL | MASK(A_SIZE))
+#define MASK_CMD_ADR_WR \
+	(MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) | MASK(A_SIZE) | D_SIZE_1)
+#define MASK_RD_1BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_1)
+#define MASK_RD_2BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_2)
+#define MASK_RD_3BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_3)
+#define MASK_RD_4BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_4)
+#define MASK_CMD_RD_1BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_1)
+#define MASK_CMD_RD_2BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_2)
+#define MASK_CMD_RD_3BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_3)
+#define MASK_CMD_RD_4BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_4)
+#define MASK_CMD_WR_ONLY (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR))
+#define MASK_CMD_WR_1BYTE \
+	(MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) | MASK(C_SIZE) | D_SIZE_1)
+#define MASK_CMD_WR_2BYTE \
+	(MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) | MASK(C_SIZE) | D_SIZE_2)
+#define MASK_CMD_WR_ADR \
+	(MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) | MASK(A_SIZE))
 
 #endif /* __CROS_EC_REGISTERS_H */
diff --git a/zephyr/shim/chip/npcx/power_policy.c b/zephyr/shim/chip/npcx/power_policy.c
index 1e5a7b15ce..aea6e62d30 100644
--- a/zephyr/shim/chip/npcx/power_policy.c
+++ b/zephyr/shim/chip/npcx/power_policy.c
@@ -1,9 +1,9 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <zephyr/zephyr.h>
+#include <zephyr/kernel.h>
 #include <zephyr/pm/pm.h>
 #include <zephyr/pm/policy.h>
 #include <soc.h>
diff --git a/zephyr/shim/chip/npcx/shi.c b/zephyr/shim/chip/npcx/shi.c
index 9e52228e37..8bec57252d 100644
--- a/zephyr/shim/chip/npcx/shi.c
+++ b/zephyr/shim/chip/npcx/shi.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,7 +9,7 @@
 #include <zephyr/dt-bindings/clock/npcx_clock.h>
 #include <zephyr/logging/log.h>
 #include <soc.h>
-#include <zephyr/zephyr.h>
+#include <zephyr/kernel.h>
 
 #include <ap_power/ap_power.h>
 #include "chipset.h"
@@ -83,12 +83,11 @@ static void shi_init(void)
 	ap_power_ev_init_callback(&cb, shi_power_change,
 #if CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK
 				  AP_POWER_RESUME_INIT |
-				  AP_POWER_SUSPEND_COMPLETE
+					  AP_POWER_SUSPEND_COMPLETE
 #else
-				  AP_POWER_RESUME |
-				  AP_POWER_SUSPEND
+				  AP_POWER_RESUME | AP_POWER_SUSPEND
 #endif
-				  );
+	);
 	ap_power_ev_add_callback(&cb);
 
 	if (IS_ENABLED(CONFIG_CROS_SHI_NPCX_DEBUG) ||
diff --git a/zephyr/shim/chip/npcx/system.c b/zephyr/shim/chip/npcx/system.c
index ae28749ec0..2240acea54 100644
--- a/zephyr/shim/chip/npcx/system.c
+++ b/zephyr/shim/chip/npcx/system.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -54,9 +54,9 @@ void system_mpu_config(void)
 	CPU_MPU_CTRL = 0x7;
 
 	/* Create a new MPU Region to allow execution from low-power ram */
-	CPU_MPU_RNR  = REGION_CHIP_RESERVED;
+	CPU_MPU_RNR = REGION_CHIP_RESERVED;
 	CPU_MPU_RASR = CPU_MPU_RASR & 0xFFFFFFFE; /* Disable region */
-	CPU_MPU_RBAR = CONFIG_LPRAM_BASE;         /* Set region base address */
+	CPU_MPU_RBAR = CONFIG_LPRAM_BASE; /* Set region base address */
 	/*
 	 * Set region size & attribute and enable region
 	 * [31:29] - Reserved.
diff --git a/zephyr/shim/chip/npcx/system_download_from_flash.c b/zephyr/shim/chip/npcx/system_download_from_flash.c
index f616dc6603..1aef9560d1 100644
--- a/zephyr/shim/chip/npcx/system_download_from_flash.c
+++ b/zephyr/shim/chip/npcx/system_download_from_flash.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,40 +11,40 @@
 #include "system_chip.h"
 
 /* Modules Map */
-#define NPCX_PMC_BASE_ADDR	0x4000D000
-#define NPCX_GDMA_BASE_ADDR	0x40011000
+#define NPCX_PMC_BASE_ADDR 0x4000D000
+#define NPCX_GDMA_BASE_ADDR 0x40011000
 
 /******************************************************************************/
 /* GDMA (General DMA) Registers */
-#define NPCX_GDMA_CTL		REG32(NPCX_GDMA_BASE_ADDR + 0x000)
-#define NPCX_GDMA_SRCB		REG32(NPCX_GDMA_BASE_ADDR + 0x004)
-#define NPCX_GDMA_DSTB		REG32(NPCX_GDMA_BASE_ADDR + 0x008)
-#define NPCX_GDMA_TCNT		REG32(NPCX_GDMA_BASE_ADDR + 0x00C)
+#define NPCX_GDMA_CTL REG32(NPCX_GDMA_BASE_ADDR + 0x000)
+#define NPCX_GDMA_SRCB REG32(NPCX_GDMA_BASE_ADDR + 0x004)
+#define NPCX_GDMA_DSTB REG32(NPCX_GDMA_BASE_ADDR + 0x008)
+#define NPCX_GDMA_TCNT REG32(NPCX_GDMA_BASE_ADDR + 0x00C)
 
 /******************************************************************************/
 /* GDMA register fields */
-#define NPCX_GDMA_CTL_GDMAEN                         0
-#define NPCX_GDMA_CTL_GDMAMS                         FIELD(2,   2)
-#define NPCX_GDMA_CTL_DADIR                          4
-#define NPCX_GDMA_CTL_SADIR                          5
-#define NPCX_GDMA_CTL_SAFIX                          7
-#define NPCX_GDMA_CTL_SIEN                           8
-#define NPCX_GDMA_CTL_BME                            9
-#define NPCX_GDMA_CTL_SBMS                           11
-#define NPCX_GDMA_CTL_TWS                            FIELD(12,  2)
-#define NPCX_GDMA_CTL_DM                             15
-#define NPCX_GDMA_CTL_SOFTREQ                        16
-#define NPCX_GDMA_CTL_TC                             18
-#define NPCX_GDMA_CTL_GDMAERR                        20
-#define NPCX_GDMA_CTL_BLOCK_BUG_CORRECTION_DISABLE   26
+#define NPCX_GDMA_CTL_GDMAEN 0
+#define NPCX_GDMA_CTL_GDMAMS FIELD(2, 2)
+#define NPCX_GDMA_CTL_DADIR 4
+#define NPCX_GDMA_CTL_SADIR 5
+#define NPCX_GDMA_CTL_SAFIX 7
+#define NPCX_GDMA_CTL_SIEN 8
+#define NPCX_GDMA_CTL_BME 9
+#define NPCX_GDMA_CTL_SBMS 11
+#define NPCX_GDMA_CTL_TWS FIELD(12, 2)
+#define NPCX_GDMA_CTL_DM 15
+#define NPCX_GDMA_CTL_SOFTREQ 16
+#define NPCX_GDMA_CTL_TC 18
+#define NPCX_GDMA_CTL_GDMAERR 20
+#define NPCX_GDMA_CTL_BLOCK_BUG_CORRECTION_DISABLE 26
 
 /******************************************************************************/
 /* Low Power RAM definitions */
-#define NPCX_LPRAM_CTRL		REG32(0x40001044)
+#define NPCX_LPRAM_CTRL REG32(0x40001044)
 
 /******************************************************************************/
 /* Sysjump utilities in low power ram for npcx series. */
-noreturn void __keep __attribute__ ((section(".lowpower_ram2")))
+noreturn void __keep __attribute__((section(".lowpower_ram2")))
 __start_gdma(uint32_t exeAddr)
 {
 	/* Enable GDMA now */
@@ -55,7 +55,7 @@ __start_gdma(uint32_t exeAddr)
 
 	/* Wait for transfer to complete/fail */
 	while (!IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_TC) &&
-			!IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAERR))
+	       !IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAERR))
 		;
 
 	/* Disable GDMA now */
@@ -81,11 +81,11 @@ __start_gdma(uint32_t exeAddr)
 }
 
 /* Begin address of Suspend RAM for little FW (GDMA utilities). */
-#define LFW_OFFSET		0x160
+#define LFW_OFFSET 0x160
 uintptr_t __lpram_lfw_start = CONFIG_LPRAM_BASE + LFW_OFFSET;
 
 void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr,
-		uint32_t size, uint32_t exeAddr)
+				uint32_t size, uint32_t exeAddr)
 {
 	int i;
 	uint8_t chunkSize = 16; /* 4 data burst mode. ie.16 bytes */
@@ -94,7 +94,7 @@ void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr,
 	 * it's a thumb branch for cortex-m series CPU.
 	 */
 	void (*__start_gdma_in_lpram)(uint32_t) =
-			(void(*)(uint32_t))(__lpram_lfw_start | 0x01);
+		(void (*)(uint32_t))(__lpram_lfw_start | 0x01);
 
 	/*
 	 * Before enabling burst mode for better performance of GDMA, it's
@@ -152,7 +152,7 @@ void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr,
 	/* Copy the __start_gdma_in_lpram instructions to LPRAM */
 	for (i = 0; i < &__flash_lplfw_end - &__flash_lplfw_start; i++)
 		*((uint32_t *)__lpram_lfw_start + i) =
-				*(&__flash_lplfw_start + i);
+			*(&__flash_lplfw_start + i);
 
 	/* Start GDMA in Suspend RAM */
 	__start_gdma_in_lpram(exeAddr);
diff --git a/zephyr/shim/chip/npcx/system_external_storage.c b/zephyr/shim/chip/npcx/system_external_storage.c
index 96d13fd94e..81e1968cf4 100644
--- a/zephyr/shim/chip/npcx/system_external_storage.c
+++ b/zephyr/shim/chip/npcx/system_external_storage.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -26,13 +26,13 @@ static const struct device *mdc_dev = DEVICE_DT_GET(DT_NODELABEL(mdc));
 static uint32_t fwctrl_cached = 0xFFFFFFFF;
 
 #ifdef CONFIG_SOC_SERIES_NPCX7
-#define NPCX_FWCTRL                       0x007
-#define NPCX_FWCTRL_RO_REGION             0
-#define NPCX_FWCTRL_FW_SLOT               1
+#define NPCX_FWCTRL 0x007
+#define NPCX_FWCTRL_RO_REGION 0
+#define NPCX_FWCTRL_FW_SLOT 1
 #elif defined(CONFIG_SOC_SERIES_NPCX9)
-#define NPCX_FWCTRL                       0x009
-#define NPCX_FWCTRL_RO_REGION             6
-#define NPCX_FWCTRL_FW_SLOT               7
+#define NPCX_FWCTRL 0x009
+#define NPCX_FWCTRL_RO_REGION 6
+#define NPCX_FWCTRL_FW_SLOT 7
 #else
 #error "Unsupported NPCX SoC series."
 #endif
@@ -66,28 +66,28 @@ void system_jump_to_booter(void)
 	 */
 	switch (system_get_shrspi_image_copy()) {
 	case EC_IMAGE_RW:
-		flash_offset = CONFIG_EC_WRITABLE_STORAGE_OFF +
-				CONFIG_RW_STORAGE_OFF;
+		flash_offset =
+			CONFIG_EC_WRITABLE_STORAGE_OFF + CONFIG_RW_STORAGE_OFF;
 		flash_used = CONFIG_RW_SIZE;
 		break;
 #ifdef CONFIG_RW_B
 	case EC_IMAGE_RW_B:
 		flash_offset = CONFIG_EC_WRITABLE_STORAGE_OFF +
-				CONFIG_RW_B_STORAGE_OFF;
+			       CONFIG_RW_B_STORAGE_OFF;
 		flash_used = CONFIG_RW_SIZE;
 		break;
 #endif
 	case EC_IMAGE_RO:
 	default: /* Jump to RO by default */
-		flash_offset = CONFIG_EC_PROTECTED_STORAGE_OFF +
-				CONFIG_RO_STORAGE_OFF;
+		flash_offset =
+			CONFIG_EC_PROTECTED_STORAGE_OFF + CONFIG_RO_STORAGE_OFF;
 		flash_used = CONFIG_RO_SIZE;
 		break;
 	}
 
 	/* Make sure the reset vector is inside the destination image */
-	addr_entry = *(uintptr_t *)(flash_offset +
-				    CONFIG_MAPPED_STORAGE_BASE + 4);
+	addr_entry =
+		*(uintptr_t *)(flash_offset + CONFIG_MAPPED_STORAGE_BASE + 4);
 
 	/*
 	 * Speed up FW download time by increasing clock freq of EC. It will
@@ -95,29 +95,34 @@ void system_jump_to_booter(void)
 	 */
 	clock_turbo();
 
-/*
- * npcx9 Rev.1 has the problem for download_from_flash API.
- * Workwaroud it by executing the system_download_from_flash function
- * in the suspend RAM like npcx5.
- * TODO: Removing npcx9 when Rev.2 is available.
- */
+	/*
+	 * npcx9 Rev.1 has the problem for download_from_flash API.
+	 * Workwaroud it by executing the system_download_from_flash function
+	 * in the suspend RAM like npcx5.
+	 * TODO: Removing npcx9 when Rev.2 is available.
+	 */
 	/* Bypass for GMDA issue of ROM api utilities */
 #if defined(CONFIG_SOC_SERIES_NPCX5) || \
 	defined(CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API)
-	system_download_from_flash(
-		flash_offset,      /* The offset of the data in spi flash */
-		CONFIG_PROGRAM_MEMORY_BASE, /* RAM Addr of downloaded data */
-		flash_used,        /* Number of bytes to download      */
-		addr_entry         /* jump to this address after download */
+	system_download_from_flash(flash_offset, /* The offset of the data in
+						    spi flash */
+				   CONFIG_PROGRAM_MEMORY_BASE, /* RAM Addr of
+								  downloaded
+								  data */
+				   flash_used, /* Number of bytes to download */
+				   addr_entry /* jump to this address after
+						 download */
 	);
 #else
-	download_from_flash(
-		flash_offset,      /* The offset of the data in spi flash */
-		CONFIG_PROGRAM_MEMORY_BASE, /* RAM Addr of downloaded data */
-		flash_used,        /* Number of bytes to download      */
-		SIGN_NO_CHECK,     /* Need CRC check or not               */
-		addr_entry,        /* jump to this address after download */
-		&status            /* Status fo download */
+	download_from_flash(flash_offset, /* The offset of the data in spi flash
+					   */
+			    CONFIG_PROGRAM_MEMORY_BASE, /* RAM Addr of
+							   downloaded data */
+			    flash_used, /* Number of bytes to download      */
+			    SIGN_NO_CHECK, /* Need CRC check or not */
+			    addr_entry, /* jump to this address after download
+					 */
+			    &status /* Status fo download */
 	);
 #endif
 }
diff --git a/zephyr/shim/core/CMakeLists.txt b/zephyr/shim/core/CMakeLists.txt
index e1b13f21f4..ef116e376a 100644
--- a/zephyr/shim/core/CMakeLists.txt
+++ b/zephyr/shim/core/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/shim/core/cortex-m/CMakeLists.txt b/zephyr/shim/core/cortex-m/CMakeLists.txt
index dd975787dc..030512552a 100644
--- a/zephyr/shim/core/cortex-m/CMakeLists.txt
+++ b/zephyr/shim/core/cortex-m/CMakeLists.txt
@@ -1,6 +1,6 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CONSOLE_CMD_IRQ irq_command.c)
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_MPU mpu.c)
+zephyr_library_sources_ifdef(CONFIG_MPU mpu.c)
diff --git a/zephyr/shim/core/cortex-m/irq_command.c b/zephyr/shim/core/cortex-m/irq_command.c
index 911aeae946..1cf1a213e4 100644
--- a/zephyr/shim/core/cortex-m/irq_command.c
+++ b/zephyr/shim/core/cortex-m/irq_command.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,7 +21,7 @@ void sys_trace_isr_enter_user(int nested_interrupts)
 	irq_count[irq]++;
 }
 
-static int command_irq(int argc, char **argv)
+static int command_irq(int argc, const char **argv)
 {
 	ARG_UNUSED(argc);
 	ARG_UNUSED(argv);
diff --git a/zephyr/shim/core/cortex-m/mpu.c b/zephyr/shim/core/cortex-m/mpu.c
index c798a2a446..8025227700 100644
--- a/zephyr/shim/core/cortex-m/mpu.c
+++ b/zephyr/shim/core/cortex-m/mpu.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/shim/include/adc_chip.h b/zephyr/shim/include/adc_chip.h
index c51cdfbb30..f5580a52ab 100644
--- a/zephyr/shim/include/adc_chip.h
+++ b/zephyr/shim/include/adc_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/shim/include/atomic.h b/zephyr/shim/include/atomic.h
index 6b44bf02a5..beb8b111ed 100644
--- a/zephyr/shim/include/atomic.h
+++ b/zephyr/shim/include/atomic.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,4 +13,4 @@ static inline atomic_val_t atomic_clear_bits(atomic_t *addr, atomic_val_t bits)
 	return atomic_and(addr, ~bits);
 }
 
-#endif  /* __CROS_EC_ATOMIC_H */
+#endif /* __CROS_EC_ATOMIC_H */
diff --git a/zephyr/shim/include/battery_enum.h b/zephyr/shim/include/battery_enum.h
index 7497edea0b..c0d10a6ed5 100644
--- a/zephyr/shim/include/battery_enum.h
+++ b/zephyr/shim/include/battery_enum.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,16 +8,16 @@
 	"included in all zephyr builds automatically"
 #endif
 
-#define BATTERY_ENUM(val)	DT_CAT(BATTERY_, val)
+#define BATTERY_ENUM(val) DT_CAT(BATTERY_, val)
 #define BATTERY_TYPE(id) BATTERY_ENUM(DT_STRING_UPPER_TOKEN(id, enum_name))
-#define BATTERY_TYPE_WITH_COMMA(id)	BATTERY_TYPE(id),
+#define BATTERY_TYPE_WITH_COMMA(id) BATTERY_TYPE(id),
 
 /* This produces a list of BATTERY_<ENUM_NAME> identifiers */
 enum battery_type {
 #if DT_HAS_COMPAT_STATUS_OKAY(battery_smart)
 	DT_FOREACH_STATUS_OKAY(battery_smart, BATTERY_TYPE_WITH_COMMA)
 #endif
-	BATTERY_TYPE_COUNT,
+		BATTERY_TYPE_COUNT,
 };
 
 #undef BATTERY_TYPE_WITH_COMMA
diff --git a/zephyr/shim/include/board.h b/zephyr/shim/include/board.h
index 1c8da8b209..3e12568155 100644
--- a/zephyr/shim/include/board.h
+++ b/zephyr/shim/include/board.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,11 +15,6 @@
 /* Include shimmed version of power signal */
 #include "power/power.h"
 
-/* Include board specific gpio mapping/aliases if named_pgios node exists */
-#if !defined(TEST_BUILD) && DT_NODE_EXISTS(DT_PATH(named_gpios))
-#include "gpio_map.h"
-#endif
-
 /* Include board specific i2c mapping if I2C is enabled. */
 #if defined(CONFIG_I2C)
 #include "i2c/i2c.h"
@@ -37,4 +32,4 @@
 #include "charger_enum.h"
 #endif
 
-#endif  /* __BOARD_H */
+#endif /* __BOARD_H */
diff --git a/zephyr/shim/include/board_led.h b/zephyr/shim/include/board_led.h
index 205c96c4c3..074ffa0256 100644
--- a/zephyr/shim/include/board_led.h
+++ b/zephyr/shim/include/board_led.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,13 +12,13 @@ struct board_led_pwm_dt_channel {
 	pwm_flags_t flags;
 };
 
-#define BOARD_LED_PWM_DT_CHANNEL_INITIALIZER(node_id) \
-	{ \
+#define BOARD_LED_PWM_DT_CHANNEL_INITIALIZER(node_id)        \
+	{                                                    \
 		.dev = DEVICE_DT_GET(DT_PWMS_CTLR(node_id)), \
-		.channel = DT_PWMS_CHANNEL(node_id), \
-		.flags = DT_PWMS_FLAGS(node_id), \
+		.channel = DT_PWMS_CHANNEL(node_id),         \
+		.flags = DT_PWMS_FLAGS(node_id),             \
 	}
 
 #define BOARD_LED_HZ_TO_PERIOD_NS(freq_hz) (NSEC_PER_SEC / freq_hz)
 
-#endif  /* __BOARD_LED_H */
+#endif /* __BOARD_LED_H */
diff --git a/zephyr/shim/include/builtin/assert.h b/zephyr/shim/include/builtin/assert.h
index c3c43f2ba1..27dce8f2c4 100644
--- a/zephyr/shim/include/builtin/assert.h
+++ b/zephyr/shim/include/builtin/assert.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/shim/include/charger/chg_bq25710.h b/zephyr/shim/include/charger/chg_bq25710.h
index 6458545946..91d100a7de 100644
--- a/zephyr/shim/include/charger/chg_bq25710.h
+++ b/zephyr/shim/include/charger/chg_bq25710.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,10 +10,10 @@
 
 #define BQ25710_CHG_COMPAT ti_bq25710
 
-#define CHG_CONFIG_BQ25710(id)                               \
-	{                                                    \
-		.i2c_port = I2C_PORT(DT_PHANDLE(id, port)),  \
-		.i2c_addr_flags = BQ25710_SMBUS_ADDR1_FLAGS, \
-		.drv = &bq25710_drv,                         \
+#define CHG_CONFIG_BQ25710(id)                     \
+	{                                          \
+		.i2c_port = I2C_PORT_BY_DEV(id),   \
+		.i2c_addr_flags = DT_REG_ADDR(id), \
+		.drv = &bq25710_drv,               \
 	},
 #endif
diff --git a/zephyr/shim/include/charger/chg_isl923x.h b/zephyr/shim/include/charger/chg_isl923x.h
index fea25e7391..b0323cd1b8 100644
--- a/zephyr/shim/include/charger/chg_isl923x.h
+++ b/zephyr/shim/include/charger/chg_isl923x.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,10 +7,11 @@
 #include "driver/charger/isl923x_public.h"
 
 #define ISL923X_CHG_COMPAT intersil_isl923x
+#define ISL923X_EMUL_COMPAT cros_isl923x_emul
 
-#define CHG_CONFIG_ISL923X(id)                              \
-	{                                                   \
-		.i2c_port = I2C_PORT(DT_PHANDLE(id, port)), \
-		.i2c_addr_flags = ISL923X_ADDR_FLAGS,       \
-		.drv = &isl923x_drv,                        \
+#define CHG_CONFIG_ISL923X(id)                     \
+	{                                          \
+		.i2c_port = I2C_PORT_BY_DEV(id),   \
+		.i2c_addr_flags = DT_REG_ADDR(id), \
+		.drv = &isl923x_drv,               \
 	},
diff --git a/zephyr/shim/include/charger/chg_isl9241.h b/zephyr/shim/include/charger/chg_isl9241.h
index 8e19e2643e..711a581c2f 100644
--- a/zephyr/shim/include/charger/chg_isl9241.h
+++ b/zephyr/shim/include/charger/chg_isl9241.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,9 +8,9 @@
 
 #define ISL9241_CHG_COMPAT intersil_isl9241
 
-#define CHG_CONFIG_ISL9241(id)                              \
-	{                                                   \
-		.i2c_port = I2C_PORT(DT_PHANDLE(id, port)), \
-		.i2c_addr_flags = ISL9241_ADDR_FLAGS,       \
-		.drv = &isl9241_drv,                        \
+#define CHG_CONFIG_ISL9241(id)                     \
+	{                                          \
+		.i2c_port = I2C_PORT_BY_DEV(id),   \
+		.i2c_addr_flags = DT_REG_ADDR(id), \
+		.drv = &isl9241_drv,               \
 	},
diff --git a/zephyr/shim/include/charger/chg_rt9490.h b/zephyr/shim/include/charger/chg_rt9490.h
index 03059078e9..3ac596d482 100644
--- a/zephyr/shim/include/charger/chg_rt9490.h
+++ b/zephyr/shim/include/charger/chg_rt9490.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,10 +7,11 @@
 #include "driver/charger/rt9490.h"
 
 #define RT9490_CHG_COMPAT richtek_rt9490
+#define RT9490_EMUL_COMPAT zephyr_rt9490_emul
 
-#define CHG_CONFIG_RT9490(id)                               \
-	{                                                   \
-		.i2c_port = I2C_PORT(DT_PHANDLE(id, port)), \
-		.i2c_addr_flags = RT9490_ADDR_FLAGS,        \
-		.drv = &rt9490_drv,                         \
+#define CHG_CONFIG_RT9490(id)                      \
+	{                                          \
+		.i2c_port = I2C_PORT_BY_DEV(id),   \
+		.i2c_addr_flags = DT_REG_ADDR(id), \
+		.drv = &rt9490_drv,                \
 	},
diff --git a/zephyr/shim/include/charger/chg_sm5803.h b/zephyr/shim/include/charger/chg_sm5803.h
index 7e18a5554b..65ef066970 100644
--- a/zephyr/shim/include/charger/chg_sm5803.h
+++ b/zephyr/shim/include/charger/chg_sm5803.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,9 +8,9 @@
 
 #define SM5803_CHG_COMPAT siliconmitus_sm5803
 
-#define CHG_CONFIG_SM5803(id)                                \
-	{                                                    \
-		.i2c_port = I2C_PORT(DT_PHANDLE(id, port)),  \
-		.i2c_addr_flags = SM5803_ADDR_CHARGER_FLAGS, \
-		.drv = &sm5803_drv,                          \
+#define CHG_CONFIG_SM5803(id)                      \
+	{                                          \
+		.i2c_port = I2C_PORT_BY_DEV(id),   \
+		.i2c_addr_flags = DT_REG_ADDR(id), \
+		.drv = &sm5803_drv,                \
 	},
diff --git a/zephyr/shim/include/charger_chips.h b/zephyr/shim/include/charger_chips.h
new file mode 100644
index 0000000000..b24fa246bf
--- /dev/null
+++ b/zephyr/shim/include/charger_chips.h
@@ -0,0 +1,32 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_CHARGER_CHIPS_H
+#define __CROS_EC_CHARGER_CHIPS_H
+
+#include "charger.h"
+#include <zephyr/devicetree.h>
+
+extern const struct charger_config_t chg_chips_alt[];
+
+#define ALT_CHG_CHIP_CHK(usbc_id, usb_port_num)                              \
+	COND_CODE_1(DT_REG_HAS_IDX(usbc_id, usb_port_num),                   \
+		    (COND_CODE_1(DT_NODE_HAS_PROP(usbc_id, chg_alt), (|| 1), \
+				 (|| 0))),                                   \
+		    (|| 0))
+
+#define CHG_ENABLE_ALTERNATE(usb_port_num)                                     \
+	do {                                                                   \
+		BUILD_ASSERT(                                                  \
+			(0 DT_FOREACH_STATUS_OKAY_VARGS(named_usbc_port,       \
+							ALT_CHG_CHIP_CHK,      \
+							usb_port_num)),        \
+			"Selected USB node does not exist or does not specify" \
+			"a charger alternate chip");                           \
+		memcpy(&chg_chips[usb_port_num], &chg_chips_alt[usb_port_num], \
+		       sizeof(struct charger_config_t));                       \
+	} while (0)
+
+#endif /* __CROS_EC_CHARGER_CHIPS_H */
diff --git a/zephyr/shim/include/charger_enum.h b/zephyr/shim/include/charger_enum.h
index a2acc3e000..a10a274e28 100644
--- a/zephyr/shim/include/charger_enum.h
+++ b/zephyr/shim/include/charger_enum.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/shim/include/config_chip.h b/zephyr/shim/include/config_chip.h
index 73f38a72f4..75c27dd32d 100644
--- a/zephyr/shim/include/config_chip.h
+++ b/zephyr/shim/include/config_chip.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,9 +9,9 @@
 #include <zephyr/devicetree.h>
 #include <autoconf.h>
 
-#define SENSOR_NODE			DT_PATH(motionsense_sensor)
-#define SENSOR_INFO_NODE		DT_PATH(motionsense_sensor_info)
-#define SENSOR_ALT_NODE			DT_PATH(motionsense_sensor_alt)
+#define SENSOR_NODE DT_PATH(motionsense_sensor)
+#define SENSOR_INFO_NODE DT_PATH(motionsense_sensor_info)
+#define SENSOR_ALT_NODE DT_PATH(motionsense_sensor_alt)
 
 /*
  * The battery enum is used in various drivers and these assume that it is
@@ -66,14 +66,16 @@
 #undef CONFIG_CONSOLE_UART /* Only used by the Chromium EC chip drivers */
 #undef CONFIG_I2C_MULTI_PORT_CONTROLLER /* Not required by I2C shim */
 #undef CONFIG_IRQ_COUNT /* Only used by Chromium EC core drivers */
-#undef CONFIG_KEYBOARD_KSO_HIGH_DRIVE /* Used by the Chromium EC chip drivers */
+#undef CONFIG_KEYBOARD_KSO_HIGH_DRIVE /* Used by the Chromium EC chip drivers \
+				       */
 #undef CONFIG_LTO /* Link time optimization enabled by Zephyr build system */
 #undef CONFIG_STACK_SIZE /* Only used in Chromium EC core init code */
 #ifndef CONFIG_FPU
 #undef CONFIG_FPU /* Used in Zephyr as well, enabled in Kconfig directly */
 #endif
 #ifndef CONFIG_WATCHDOG
-#undef CONFIG_WATCHDOG /* Used in Zephyr as well, enabled in Kconfig directly */
+#undef CONFIG_WATCHDOG /* Used in Zephyr as well, enabled in Kconfig directly \
+			*/
 #endif
 
 /*
@@ -103,8 +105,8 @@
 #endif
 
 /* EC chipset configuration */
-#define HOOK_TICK_INTERVAL	CONFIG_CROS_EC_HOOK_TICK_INTERVAL
-#define HOOK_TICK_INTERVAL_MS	(HOOK_TICK_INTERVAL / 1000)
+#define HOOK_TICK_INTERVAL CONFIG_CROS_EC_HOOK_TICK_INTERVAL
+#define HOOK_TICK_INTERVAL_MS (HOOK_TICK_INTERVAL / 1000)
 
 /* Chipset and power configuration */
 #ifdef CONFIG_AP_ARM_QUALCOMM_SC7180
@@ -242,7 +244,7 @@
 #undef CONFIG_BATTERY_PRESENT_GPIO
 #ifdef CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO
 /* This is always GPIO_BATT_PRES_ODL with Zephyr */
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_BATT_PRES_ODL
+#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BATT_PRES_ODL
 #endif
 
 #undef CONFIG_BATTERY_CRITICAL_SHUTDOWN_CUT_OFF
@@ -283,9 +285,9 @@
 
 #undef CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV
 #if defined(CONFIG_PLATFORM_EC_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV) && \
-    (CONFIG_PLATFORM_EC_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV > 0)
+	(CONFIG_PLATFORM_EC_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV > 0)
 #define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV \
-    CONFIG_PLATFORM_EC_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV
+	CONFIG_PLATFORM_EC_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV
 #endif
 
 #undef CONFIG_BOARD_RESET_AFTER_POWER_ON
@@ -428,29 +430,30 @@
 #endif
 
 /* eSPI signals */
-#undef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#ifdef CONFIG_PLATFORM_EC_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+#undef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
+#ifdef CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S3
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3
 #endif
 
-#undef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-#ifdef CONFIG_PLATFORM_EC_ESPI_VW_SLP_S4
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+#undef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
+#ifdef CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S4
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4
 #endif
 
-#undef CONFIG_HOSTCMD_ESPI_VW_SLP_S5
-#ifdef CONFIG_PLATFORM_EC_ESPI_VW_SLP_S5
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S5
+#undef CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S5
+#ifdef CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S5
+#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S5
 #endif
 
-#undef CONFIG_HOSTCMD_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST
-#ifdef CONFIG_PLATFORM_EC_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST
-#define CONFIG_HOSTCMD_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST
+#undef CONFIG_HOST_INTERFACE_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST
+#ifdef CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST
+#define CONFIG_HOST_INTERFACE_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST
 #endif
 
-#undef CONFIG_ESPI_DEFAULT_VW_WIDTH_US
+#undef CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US
 #ifdef CONFIG_PLATFORM_EC_DEFAULT_SCI_WIDTH_US
-#define CONFIG_ESPI_DEFAULT_VW_WIDTH_US CONFIG_PLATFORM_EC_DEFAULT_SCI_WIDTH_US
+#define CONFIG_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US \
+	CONFIG_PLATFORM_EC_DEFAULT_SCI_WIDTH_US
 #endif
 
 #if DT_HAS_CHOSEN(zephyr_flash)
@@ -466,10 +469,11 @@
 /* The jump data goes at the end of data ram, so for posix, the end of ram is
  * wherever the jump data ended up.
  */
-extern struct jump_data mock_jump_data;
+#include "sysjump.h"
+extern char mock_jump_data[sizeof(struct jump_data) + 256];
 #define CONFIG_RAM_BASE 0x0
 #define CONFIG_DATA_RAM_SIZE \
-	(((uintptr_t)&mock_jump_data) + sizeof(struct jump_data))
+	(((uintptr_t)&mock_jump_data) + sizeof(mock_jump_data))
 #else
 #error "A zephyr,sram device must be chosen in the device tree"
 #endif
@@ -479,16 +483,16 @@ extern struct jump_data mock_jump_data;
 #define CONFIG_RW_MEM_OFF CONFIG_CROS_EC_RW_MEM_OFF
 #define CONFIG_RW_MEM_SIZE CONFIG_CROS_EC_RW_MEM_SIZE
 
-#define CONFIG_WP_STORAGE_OFF	CONFIG_EC_PROTECTED_STORAGE_OFF
-#define CONFIG_WP_STORAGE_SIZE	CONFIG_EC_PROTECTED_STORAGE_SIZE
-#define CONFIG_RO_SIZE		CONFIG_CROS_EC_RO_SIZE
-#define CONFIG_RW_SIZE		CONFIG_CROS_EC_RW_SIZE
+#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
+#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
+#define CONFIG_RO_SIZE CONFIG_CROS_EC_RO_SIZE
+#define CONFIG_RW_SIZE CONFIG_CROS_EC_RW_SIZE
 
 /*
  * ROM resident area in flash used to store data objects that are not copied
  * into code RAM. Enable using the CONFIG_CHIP_INIT_ROM_REGION option.
  */
-#define CONFIG_RO_ROM_RESIDENT_MEM_OFF	CONFIG_RO_SIZE
+#define CONFIG_RO_ROM_RESIDENT_MEM_OFF CONFIG_RO_SIZE
 #define CONFIG_RO_ROM_RESIDENT_SIZE \
 	(CONFIG_EC_PROTECTED_STORAGE_SIZE - CONFIG_RO_SIZE)
 
@@ -496,7 +500,7 @@ extern struct jump_data mock_jump_data;
  * RW firmware in program memory - Identical to RO, only one image loaded at
  * a time.
  */
-#define CONFIG_RW_ROM_RESIDENT_MEM_OFF	CONFIG_RW_SIZE
+#define CONFIG_RW_ROM_RESIDENT_MEM_OFF CONFIG_RW_SIZE
 #define CONFIG_RW_ROM_RESIDENT_SIZE \
 	(CONFIG_EC_WRITABLE_STORAGE_SIZE - CONFIG_RW_SIZE)
 
@@ -560,22 +564,9 @@ extern struct jump_data mock_jump_data;
 
 #undef CONFIG_FLASH_SIZE_BYTES
 #ifdef CONFIG_PLATFORM_EC_FLASH_SIZE_BYTES
-/*
- * Flash size of IT81202 is 1MB.
- * We use only 3/4 space of flash to save time of erasing RW image from flash.
- */
-#ifdef CONFIG_SOC_IT8XXX2
-#define CONFIG_FLASH_SIZE_BYTES (CONFIG_PLATFORM_EC_FLASH_SIZE_BYTES * 3 / 4)
-#else
 #define CONFIG_FLASH_SIZE_BYTES CONFIG_PLATFORM_EC_FLASH_SIZE_BYTES
-#endif
 #endif /* CONFIG_PLATFORM_EC_FLASH_SIZE_BYTES */
 
-#undef CONFIG_ADC
-#ifdef CONFIG_PLATFORM_EC_ADC
-#define CONFIG_ADC
-#endif
-
 #undef CONFIG_ADC_CHANNELS_RUNTIME_CONFIG
 #ifdef CONFIG_PLATFORM_EC_ADC_CHANNELS_RUNTIME_CONFIG
 #define CONFIG_ADC_CHANNELS_RUNTIME_CONFIG
@@ -621,6 +612,11 @@ extern struct jump_data mock_jump_data;
 #define CONFIG_FANS CONFIG_PLATFORM_EC_NUM_FANS
 #endif
 
+#undef CONFIG_FAN_BYPASS_SLOW_RESPONSE
+#ifdef PLATFORM_EC_FAN_BYPASS_SLOW_RESPONSE
+#define CONFIG_FAN_BYPASS_SLOW_RESPONSE
+#endif
+
 #ifdef CONFIG_PLATFORM_EC_I2C
 /* Also see shim/include/i2c/i2c.h which defines the ports enum */
 #define CONFIG_I2C_CONTROLLER
@@ -659,7 +655,7 @@ extern struct jump_data mock_jump_data;
 #undef CONFIG_KEYBOARD_DISCRETE
 #ifdef CONFIG_PLATFORM_EC_KEYBOARD_DISCRETE
 #define CONFIG_KEYBOARD_DISCRETE
-#define KB_DISCRETE_I2C_ADDR_FLAGS	DT_REG_ADDR(DT_NODELABEL(kb_discrete))
+#define KB_DISCRETE_I2C_ADDR_FLAGS DT_REG_ADDR(DT_NODELABEL(kb_discrete))
 #endif
 
 #undef CONFIG_MKBP_INPUT_DEVICES
@@ -669,16 +665,16 @@ extern struct jump_data mock_jump_data;
 
 #undef CONFIG_MKBP_EVENT_WAKEUP_MASK
 #if defined(CONFIG_PLATFORM_EC_MKBP_EVENT_WAKEUP_MASK) && \
-			DT_NODE_EXISTS(DT_PATH(ec_mkbp_event_wakeup_mask))
+	DT_NODE_EXISTS(DT_PATH(ec_mkbp_event_wakeup_mask))
 #define CONFIG_MKBP_EVENT_WAKEUP_MASK \
-		DT_PROP(DT_PATH(ec_mkbp_event_wakeup_mask), wakeup_mask)
+	DT_PROP(DT_PATH(ec_mkbp_event_wakeup_mask), wakeup_mask)
 #endif
 
 #undef CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK
 #if defined(CONFIG_PLATFORM_EC_MKBP_HOST_EVENT_WAKEUP_MASK) && \
-			DT_NODE_EXISTS(DT_PATH(ec_mkbp_host_event_wakeup_mask))
+	DT_NODE_EXISTS(DT_PATH(ec_mkbp_host_event_wakeup_mask))
 #define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \
-		DT_PROP(DT_PATH(ec_mkbp_host_event_wakeup_mask), wakeup_mask)
+	DT_PROP(DT_PATH(ec_mkbp_host_event_wakeup_mask), wakeup_mask)
 #endif
 
 #undef CONFIG_CMD_KEYBOARD
@@ -689,12 +685,12 @@ extern struct jump_data mock_jump_data;
 #undef CONFIG_KEYBOARD_COL2_INVERTED
 #ifdef CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED
 #define CONFIG_KEYBOARD_COL2_INVERTED
-#endif  /* CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED */
+#endif /* CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED */
 
 #undef CONFIG_KEYBOARD_REFRESH_ROW3
 #ifdef CONFIG_PLATFORM_EC_KEYBOARD_REFRESH_ROW3
 #define CONFIG_KEYBOARD_REFRESH_ROW3
-#endif  /* CONFIG_PLATFORM_EC_KEYBOARD_REFRESH_ROW3 */
+#endif /* CONFIG_PLATFORM_EC_KEYBOARD_REFRESH_ROW3 */
 
 #undef CONFIG_KEYBOARD_KEYPAD
 #ifdef CONFIG_PLATFORM_EC_KEYBOARD_KEYPAD
@@ -743,6 +739,11 @@ extern struct jump_data mock_jump_data;
 #define CONFIG_KBLIGHT_ENABLE_PIN
 #endif
 
+#undef CONFIG_KEYBOARD_STRICT_DEBOUNCE
+#ifdef CONFIG_PLATFORM_EC_KEYBOARD_STRICT_DEBOUNCE
+#define CONFIG_KEYBOARD_STRICT_DEBOUNCE
+#endif
+
 #undef CONFIG_LED_COMMON
 #ifdef CONFIG_PLATFORM_EC_LED_COMMON
 #define CONFIG_LED_COMMON
@@ -765,8 +766,7 @@ extern struct jump_data mock_jump_data;
 
 #ifdef CONFIG_PLATFORM_EC_LED_PWM_CHARGE_COLOR
 #undef CONFIG_LED_PWM_CHARGE_COLOR
-#define CONFIG_LED_PWM_CHARGE_COLOR \
-	CONFIG_PLATFORM_EC_LED_PWM_CHARGE_COLOR
+#define CONFIG_LED_PWM_CHARGE_COLOR CONFIG_PLATFORM_EC_LED_PWM_CHARGE_COLOR
 #endif
 
 #ifdef CONFIG_PLATFORM_EC_LED_PWM_NEAR_FULL_COLOR
@@ -783,8 +783,7 @@ extern struct jump_data mock_jump_data;
 
 #ifdef CONFIG_PLATFORM_EC_LED_PWM_SOC_ON_COLOR
 #undef CONFIG_LED_PWM_SOC_ON_COLOR
-#define CONFIG_LED_PWM_SOC_ON_COLOR \
-	CONFIG_PLATFORM_EC_LED_PWM_SOC_ON_COLOR
+#define CONFIG_LED_PWM_SOC_ON_COLOR CONFIG_PLATFORM_EC_LED_PWM_SOC_ON_COLOR
 #endif
 
 #ifdef CONFIG_PLATFORM_EC_LED_PWM_SOC_SUSPEND_COLOR
@@ -795,8 +794,7 @@ extern struct jump_data mock_jump_data;
 
 #ifdef CONFIG_PLATFORM_EC_LED_PWM_LOW_BATT_COLOR
 #undef CONFIG_LED_PWM_LOW_BATT_COLOR
-#define CONFIG_LED_PWM_LOW_BATT_COLOR \
-	CONFIG_PLATFORM_EC_LED_PWM_LOW_BATT_COLOR
+#define CONFIG_LED_PWM_LOW_BATT_COLOR CONFIG_PLATFORM_EC_LED_PWM_LOW_BATT_COLOR
 #endif
 
 #undef CONFIG_CMD_LEDTEST
@@ -812,7 +810,7 @@ extern struct jump_data mock_jump_data;
 #undef CONFIG_LED_ONOFF_STATES_BAT_LOW
 #ifdef CONFIG_PLATFORM_EC_LED_ONOFF_STATES_BAT_LOW
 #define CONFIG_LED_ONOFF_STATES_BAT_LOW \
-		CONFIG_PLATFORM_EC_LED_ONOFF_STATES_BAT_LOW
+	CONFIG_PLATFORM_EC_LED_ONOFF_STATES_BAT_LOW
 #endif
 
 #undef CONFIG_PWM_DISPLIGHT
@@ -872,8 +870,7 @@ extern struct jump_data mock_jump_data;
 #endif
 
 #undef CONFIG_POWER_S0IX
-#if defined(CONFIG_PLATFORM_EC_POWERSEQ_S0IX) || \
-	defined(CONFIG_AP_PWRSEQ_S0IX)
+#if defined(CONFIG_PLATFORM_EC_POWERSEQ_S0IX) || defined(CONFIG_AP_PWRSEQ_S0IX)
 #define CONFIG_POWER_S0IX
 #endif
 
@@ -898,7 +895,6 @@ extern struct jump_data mock_jump_data;
 	CONFIG_PLATFORM_EC_POWER_BUTTON_INIT_TIMEOUT
 #endif
 
-
 #undef CONFIG_POWERSEQ_FAKE_CONTROL
 #ifdef CONFIG_PLATFORM_EC_POWERSEQ_FAKE_CONTROL
 #define CONFIG_POWERSEQ_FAKE_CONTROL
@@ -931,19 +927,19 @@ extern struct jump_data mock_jump_data;
 #undef CONFIG_CMD_GETTIME
 #ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_GETTIME
 #define CONFIG_CMD_GETTIME
-#endif  /* CONFIG_PLATFORM_EC_CONSOLE_CMD_GETTIME */
+#endif /* CONFIG_PLATFORM_EC_CONSOLE_CMD_GETTIME */
 
 #undef CONFIG_CMD_TIMERINFO
 #ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_TIMERINFO
 #define CONFIG_CMD_TIMERINFO
-#endif  /* CONFIG_PLATFORM_EC_CONSOLE_CMD_TIMERINFO */
+#endif /* CONFIG_PLATFORM_EC_CONSOLE_CMD_TIMERINFO */
 
 #undef CONFIG_CMD_WAITMS
 #ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_WAITMS
 #define CONFIG_CMD_WAITMS
-#endif  /* CONFIG_PLATFORM_EC_CONSOLE_CMD_TIMERINFO */
+#endif /* CONFIG_PLATFORM_EC_CONSOLE_CMD_TIMERINFO */
 
-#endif  /* CONFIG_PLATFORM_EC_TIMER */
+#endif /* CONFIG_PLATFORM_EC_TIMER */
 
 /* USB-C things */
 #ifdef CONFIG_PLATFORM_EC_USBC
@@ -954,18 +950,21 @@ extern struct jump_data mock_jump_data;
 /*
  * Define these here for now. They are not actually CONFIG options in the EC
  * code base. Ideally they would be defined in the devicetree (perhaps for a
- * 'board' driver if not in the USB chip driver itself).
+ * 'board' driver if not in the USB chip driver itself). Use Kconfig to allow
+ * projects to overwrite the power configurations.
  *
  * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C
  * cables only support up to 60W.
  */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		60000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
+#define PD_OPERATING_POWER_MW CONFIG_PLATFORM_EC_PD_OPERATING_POWER_MW
+#define PD_MAX_POWER_MW CONFIG_PLATFORM_EC_PD_MAX_POWER_MW
+#define PD_MAX_CURRENT_MA CONFIG_PLATFORM_EC_PD_MAX_CURRENT_MA
+#define PD_MAX_VOLTAGE_MV CONFIG_PLATFORM_EC_PD_MAX_VOLTAGE_MV
 
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY \
+	CONFIG_PLATFORM_EC_PD_POWER_SUPPLY_TURN_ON_DELAY
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY \
+	CONFIG_PLATFORM_EC_PD_POWER_SUPPLY_TURN_OFF_DELAY
 #endif
 
 #undef CONFIG_CMD_PPC_DUMP
@@ -973,6 +972,11 @@ extern struct jump_data mock_jump_data;
 #define CONFIG_CMD_PPC_DUMP
 #endif
 
+#undef CONFIG_USBC_PPC_LOGGING
+#ifdef CONFIG_PLATFORM_EC_USBC_PPC_LOGGING
+#define CONFIG_USBC_PPC_LOGGING
+#endif
+
 #undef CONFIG_CMD_TCPC_DUMP
 #ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_TCPC_DUMP
 #define CONFIG_CMD_TCPC_DUMP
@@ -990,8 +994,8 @@ extern struct jump_data mock_jump_data;
 #define CONFIG_CHARGER
 
 /* TODO: Put these charger defines in the devicetree? */
-#define CONFIG_CHARGER_SENSE_RESISTOR		10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	10
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
 
 #endif
 
@@ -1013,31 +1017,31 @@ extern struct jump_data mock_jump_data;
 
 #undef CONFIG_CHARGER_INPUT_CURRENT
 #ifdef CONFIG_PLATFORM_EC_CHARGER_INPUT_CURRENT
-#define CONFIG_CHARGER_INPUT_CURRENT	CONFIG_PLATFORM_EC_CHARGER_INPUT_CURRENT
+#define CONFIG_CHARGER_INPUT_CURRENT CONFIG_PLATFORM_EC_CHARGER_INPUT_CURRENT
 #endif
 
 #undef CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON
 #ifdef CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON
 #define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON \
-		CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON
+	CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON
 #endif
 
 #undef CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC
 #ifdef CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC
 #define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC \
-		CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC
+	CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC
 #endif
 
 #undef CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT
 #ifdef CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT
 #define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT \
-		CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT
+	CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT
 #endif
 
 #undef CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
 #ifdef CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON
 #define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON \
-		CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON
+	CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON
 #endif
 
 #undef CONFIG_CHARGE_RAMP_SW
@@ -1062,22 +1066,22 @@ extern struct jump_data mock_jump_data;
 
 #undef CONFIG_USB_PID
 #ifdef CONFIG_PLATFORM_EC_USB_PID
-#define CONFIG_USB_PID		CONFIG_PLATFORM_EC_USB_PID
+#define CONFIG_USB_PID CONFIG_PLATFORM_EC_USB_PID
 #endif
 
 #undef CONFIG_USB_BCD_DEV
 #ifdef CONFIG_PLATFORM_EC_USB_BCD_DEV
-#define CONFIG_USB_BCD_DEV	CONFIG_PLATFORM_EC_USB_BCD_DEV
+#define CONFIG_USB_BCD_DEV CONFIG_PLATFORM_EC_USB_BCD_DEV
 #endif
 
 #undef CONFIG_USB_VID
 #ifdef CONFIG_PLATFORM_EC_USB_VID
-#define CONFIG_USB_VID	CONFIG_PLATFORM_EC_USB_VID
+#define CONFIG_USB_VID CONFIG_PLATFORM_EC_USB_VID
 #endif
 
 #undef CONFIG_USB_MS_EXTENDED_COMPAT_ID_DESCRIPTOR
 #ifdef CONFIG_PLATFORM_EC_USB_MS_EXTENDED_COMPAT_ID_DESCRIPTOR
-#define CONFIG_USB_MS_EXTENDED_COMPAT_ID_DESCRIPTOR	\
+#define CONFIG_USB_MS_EXTENDED_COMPAT_ID_DESCRIPTOR \
 	CONFIG_PLATFORM_EC_USB_MS_EXTENDED_COMPAT_ID_DESCRIPTOR
 #endif
 
@@ -1145,11 +1149,25 @@ extern struct jump_data mock_jump_data;
 #define CONFIG_USB_PORT_POWER_SMART_SIMPLE
 #endif
 
+#undef CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE
+#ifdef CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_DEFAULT_DISABLED
+#define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_DISABLED
+#elif defined(CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_DEFAULT_SDP)
+#define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_SDP2
+#elif defined(CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_DEFAULT_CDP)
+#define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_CDP
+#endif
+
 #undef CONFIG_USB_PORT_POWER_SMART_INVERTED
 #ifdef CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_INVERTED
 #define CONFIG_USB_PORT_POWER_SMART_INVERTED
 #endif
 
+#undef CONFIG_BC12_CLIENT_MODE_ONLY_PI3USB9201
+#ifdef CONFIG_PLATFORM_EC_BC12_CLIENT_MODE_ONLY_PI3USB9201
+#define CONFIG_BC12_CLIENT_MODE_ONLY_PI3USB9201
+#endif
+
 #undef CONFIG_BC12_DETECT_PI3USB9201
 #ifdef CONFIG_PLATFORM_EC_BC12_DETECT_PI3USB9201
 #define CONFIG_BC12_DETECT_PI3USB9201
@@ -1310,6 +1328,16 @@ extern struct jump_data mock_jump_data;
 #define CONFIG_USB_PD_TCPM_NCT38XX
 #endif
 
+#undef CONFIG_USB_PD_TCPM_PS8745
+#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8745
+#define CONFIG_USB_PD_TCPM_PS8745
+#endif
+
+#undef CONFIG_USB_PD_TCPM_PS8745_FORCE_ID
+#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8745_FORCE_ID
+#define CONFIG_USB_PD_TCPM_PS8745_FORCE_ID
+#endif
+
 #undef CONFIG_USB_PD_TCPM_PS8751
 #ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8751
 #define CONFIG_USB_PD_TCPM_PS8751
@@ -1364,8 +1392,11 @@ extern struct jump_data mock_jump_data;
 #ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_ITE_ON_CHIP
 #define CONFIG_USB_PD_TCPM_ITE_ON_CHIP
 
-/* TODO(b:189855648): hard-code a few things here; move to zephyr? */
-#define IT83XX_USBPD_PHY_PORT_COUNT    2
+#define IT83XX_USBPD_PHY_PORT_COUNT \
+	COND_CODE_1(DT_NODE_EXISTS(DT_INST(1, ite_it8xxx2_usbpd)), (2), (1))
+
+#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT \
+	DT_NUM_INST_STATUS_OKAY(ite_it8xxx2_usbpd)
 #endif
 
 #undef CONFIG_USB_PD_TCPM_DRIVER_IT8XXX2
@@ -1446,31 +1477,6 @@ extern struct jump_data mock_jump_data;
 
 #endif /* CONFIG_PLATFORM_EC_USB_POWER_DELIVERY */
 
-#ifdef CONFIG_PLATFORM_EC_USB_CHARGER
-#ifndef CONFIG_PLATFORM_EC_USB_CHARGER_SINGLE_TASK
-#define HAS_TASK_USB_CHG_P0 1
-
-#if CONFIG_USB_PD_PORT_MAX_COUNT > 1
-#define HAS_TASK_USB_CHG_P1 1
-#endif /* CONFIG_USB_PD_PORT_MAX_COUNT > 1 */
-
-#if CONFIG_USB_PD_PORT_MAX_COUNT > 2
-#define HAS_TASK_USB_CHG_P2 1
-#endif /* CONFIG_USB_PD_PORT_MAX_COUNT > 2 */
-
-#if CONFIG_USB_PD_PORT_MAX_COUNT > 3
-#define HAS_TASK_USB_CHG_P3 1
-#endif /* CONFIG_USB_PD_PORT_MAX_COUNT > 3 */
-
-#endif /* !PLATFORM_EC_USB_CHARGER_SINGLE_TASK */
-#endif /* CONFIG_PLATFORM_EC_USB_CHARGER */
-
-#undef CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT
-#ifdef CONFIG_PLATFORM_EC_USB_PD_ITE_ACTIVE_PORT_COUNT
-#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT \
-	CONFIG_PLATFORM_EC_USB_PD_ITE_ACTIVE_PORT_COUNT
-#endif
-
 /* Remove PD_INT_C* task for ports managed by ITE embedded TCPC */
 #ifdef CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT
 #if CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT >= 1
@@ -1512,6 +1518,11 @@ extern struct jump_data mock_jump_data;
 #define CONFIG_USBC_PPC_NX20P3483
 #endif
 
+#undef CONFIG_USBC_NX20P348X_RCP_5VSRC_MASK_ENABLE
+#ifdef CONFIG_PLATFORM_EC_USBC_NX20P348X_RCP_5VSRC_MASK_ENABLE
+#define CONFIG_USBC_NX20P348X_RCP_5VSRC_MASK_ENABLE
+#endif
+
 #undef CONFIG_USBC_PPC_RT1718S
 #ifdef CONFIG_PLATFORM_EC_USBC_PPC_RT1718S
 #define CONFIG_USBC_PPC_RT1718S
@@ -1594,13 +1605,13 @@ extern struct jump_data mock_jump_data;
 #ifdef CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_HB
 
 #define USBC_PORT_C0_HB_RETIMER_I2C_ADDR \
-        DT_REG_ADDR(DT_NODELABEL(usb_c0_hb_retimer))
+	DT_REG_ADDR(DT_NODELABEL(usb_c0_hb_retimer))
 #define USBC_PORT_C1_HB_RETIMER_I2C_ADDR \
-        DT_REG_ADDR(DT_NODELABEL(usb_c1_hb_retimer))
+	DT_REG_ADDR(DT_NODELABEL(usb_c1_hb_retimer))
 #define USBC_PORT_C2_HB_RETIMER_I2C_ADDR \
-        DT_REG_ADDR(DT_NODELABEL(usb_c2_hb_retimer))
+	DT_REG_ADDR(DT_NODELABEL(usb_c2_hb_retimer))
 #define USBC_PORT_C3_HB_RETIMER_I2C_ADDR \
-        DT_REG_ADDR(DT_NODELABEL(usb_c3_hb_retimer))
+	DT_REG_ADDR(DT_NODELABEL(usb_c3_hb_retimer))
 #define CONFIG_USBC_RETIMER_INTEL_HB
 #endif
 
@@ -1731,18 +1742,24 @@ extern struct jump_data mock_jump_data;
 #ifdef CONFIG_PLATFORM_EC_USB_PD_TCPC_LOW_POWER
 #define CONFIG_USB_PD_TCPC_LOW_POWER
 #define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE \
-		CONFIG_PLATFORM_EC_USB_PD_TCPC_LPM_EXIT_DEBOUNCE_US
+	CONFIG_PLATFORM_EC_USB_PD_TCPC_LPM_EXIT_DEBOUNCE_US
 #endif /* CONFIG_PLATFORM_EC_USB_PD_TCPC_LOW_POWER */
 
 #undef CONFIG_USB_PD_DEBUG_LEVEL
 #ifdef CONFIG_PLATFORM_EC_USB_PD_DEBUG_FIXED_LEVEL
-#define CONFIG_USB_PD_DEBUG_LEVEL	CONFIG_PLATFORM_EC_USB_PD_DEBUG_LEVEL
+#define CONFIG_USB_PD_DEBUG_LEVEL CONFIG_PLATFORM_EC_USB_PD_DEBUG_LEVEL
+#endif
+
+#undef CONFIG_USB_PD_INITIAL_DEBUG_LEVEL
+#ifdef CONFIG_PLATFORM_EC_USB_PD_INITIAL_DEBUG_LEVEL
+#define CONFIG_USB_PD_INITIAL_DEBUG_LEVEL \
+	CONFIG_PLATFORM_EC_USB_PD_INITIAL_DEBUG_LEVEL
 #endif
 
 #undef CONFIG_USB_PD_STARTUP_DELAY_MS
 #ifdef CONFIG_PLATFORM_EC_USB_PD_STARTUP_DELAY_MS
-#define CONFIG_USB_PD_STARTUP_DELAY_MS	\
-		CONFIG_PLATFORM_EC_USB_PD_STARTUP_DELAY_MS
+#define CONFIG_USB_PD_STARTUP_DELAY_MS \
+	CONFIG_PLATFORM_EC_USB_PD_STARTUP_DELAY_MS
 #endif
 
 #undef CONFIG_USB_PD_3A_PORTS
@@ -1755,6 +1772,18 @@ extern struct jump_data mock_jump_data;
 #define CONFIG_USB_PD_TEMP_SENSOR CONFIG_PLATFORM_EC_USB_PD_TEMP_SENSOR
 #endif
 
+#undef CONFIG_USB_PD_SHORT_PRESS_MAX_MS
+#ifdef CONFIG_PLATFORM_EC_USB_PD_SHORT_PRESS_MAX_MS
+#define CONFIG_USB_PD_SHORT_PRESS_MAX_MS \
+	CONFIG_PLATFORM_EC_USB_PD_SHORT_PRESS_MAX_MS
+#endif
+
+#undef CONFIG_USB_PD_LONG_PRESS_MAX_MS
+#ifdef CONFIG_PLATFORM_EC_USB_PD_LONG_PRESS_MAX_MS
+#define CONFIG_USB_PD_LONG_PRESS_MAX_MS \
+	CONFIG_PLATFORM_EC_USB_PD_LONG_PRESS_MAX_MS
+#endif
+
 #undef CONFIG_USBC_VCONN
 #ifdef CONFIG_PLATFORM_EC_USBC_VCONN
 #define CONFIG_USBC_VCONN
@@ -1818,6 +1847,11 @@ extern struct jump_data mock_jump_data;
 #define CONFIG_USB_PD_USB4
 #endif
 
+#undef CONFIG_USB_PD_DATA_RESET_MSG
+#ifdef CONFIG_PLATFORM_EC_USB_PD_DATA_RESET_MSG
+#define CONFIG_USB_PD_DATA_RESET_MSG
+#endif
+
 #undef CONFIG_USB_PD_FRS
 #ifdef CONFIG_PLATFORM_EC_USB_PD_FRS
 #define CONFIG_USB_PD_FRS
@@ -1837,7 +1871,7 @@ extern struct jump_data mock_jump_data;
 #undef VSTORE_SLOT_COUNT
 #ifdef CONFIG_PLATFORM_EC_VSTORE
 #define CONFIG_VSTORE
-#define CONFIG_VSTORE_SLOT_COUNT	CONFIG_PLATFORM_EC_VSTORE_SLOT_COUNT
+#define CONFIG_VSTORE_SLOT_COUNT CONFIG_PLATFORM_EC_VSTORE_SLOT_COUNT
 #endif
 
 /* motion sense */
@@ -1871,7 +1905,8 @@ extern struct jump_data mock_jump_data;
 
 #undef CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ
 #ifdef CONFIG_PLATFORM_EC_MAX_SENSOR_FREQ_MILLIHZ
-#define CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ CONFIG_PLATFORM_EC_MAX_SENSOR_FREQ_MILLIHZ
+#define CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ \
+	CONFIG_PLATFORM_EC_MAX_SENSOR_FREQ_MILLIHZ
 #endif
 
 #undef CONFIG_CMD_ACCEL_SPOOF
@@ -1984,6 +2019,11 @@ extern struct jump_data mock_jump_data;
 #define CONFIG_ACCELGYRO_LSM6DSO
 #endif
 
+#undef CONFIG_ACCELGYRO_LSM6DSM
+#ifdef CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSM
+#define CONFIG_ACCELGYRO_LSM6DSM
+#endif
+
 #endif /* CONFIG_PLATFORM_EC_MOTIONSENSE */
 
 #undef CONFIG_MATH_UTIL
@@ -2027,6 +2067,11 @@ extern struct jump_data mock_jump_data;
 #define CONFIG_SOFTWARE_PANIC
 #endif
 
+#undef CONFIG_DEBUG_ASSSERT_BRIEF
+#ifdef CONFIG_PLATFORM_EC_DEBUG_ASSERT_BRIEF
+#define CONFIG_DEBUG_ASSSERT_BRIEF
+#endif
+
 #undef CONFIG_PANIC_CONSOLE_OUTPUT
 #ifdef CONFIG_PLATFORM_EC_PANIC_CONSOLE_OUTPUT
 #define CONFIG_PANIC_CONSOLE_OUTPUT
@@ -2108,6 +2153,11 @@ extern struct jump_data mock_jump_data;
 #define I2C_ADDR_EEPROM_FLAGS DT_REG_ADDR(DT_NODELABEL(cbi_eeprom))
 #endif
 
+#undef CONFIG_EEPROM_CBI_WP
+#ifdef CONFIG_PLATFORM_EC_EEPROM_CBI_WP
+#define CONFIG_EEPROM_CBI_WP
+#endif
+
 #undef CONFIG_CBI_GPIO
 #ifdef CONFIG_PLATFORM_EC_CBI_GPIO
 #define CONFIG_CBI_GPIO
@@ -2125,14 +2175,14 @@ extern struct jump_data mock_jump_data;
 
 #undef CONFIG_RO_HDR_MEM_OFF
 #ifdef CONFIG_PLATFORM_EC_RO_HEADER_OFFSET
-#define CONFIG_RO_HDR_MEM_OFF	CONFIG_PLATFORM_EC_RO_HEADER_OFFSET
+#define CONFIG_RO_HDR_MEM_OFF CONFIG_PLATFORM_EC_RO_HEADER_OFFSET
 #else
 #define CONFIG_RO_HDR_MEM_OFF 0
 #endif
 
 #undef CONFIG_RO_HDR_SIZE
 #ifdef CONFIG_PLATFORM_EC_RO_HEADER_SIZE
-#define CONFIG_RO_HDR_SIZE	CONFIG_PLATFORM_EC_RO_HEADER_SIZE
+#define CONFIG_RO_HDR_SIZE CONFIG_PLATFORM_EC_RO_HEADER_SIZE
 #else
 #define CONFIG_RO_HDR_SIZE 0
 #endif
@@ -2172,11 +2222,6 @@ extern struct jump_data mock_jump_data;
 #define CONFIG_DEBUG_ASSERT_REBOOTS
 #endif
 
-#undef CONFIG_MPU
-#ifdef CONFIG_PLATFORM_EC_MPU
-#define CONFIG_MPU
-#endif
-
 #undef CONFIG_CMD_SYSINFO
 #ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_SYSINFO
 #define CONFIG_CMD_SYSINFO
@@ -2199,7 +2244,7 @@ extern struct jump_data mock_jump_data;
 
 #undef CONFIG_WATCHDOG_WARNING_LEADING_TIME_MS
 #if defined(CONFIG_PLATFORM_EC_WATCHDOG_WARNING_LEADING_TIME_MS) || \
-	defined(CONFIG_WDT_NPCX_DELAY_CYCLES) || \
+	defined(CONFIG_WDT_NPCX_DELAY_CYCLES) ||                    \
 	defined(CONFIG_WDT_ITE_WARNING_LEADING_TIME_MS)
 /*
  * Note:
@@ -2319,7 +2364,7 @@ extern struct jump_data mock_jump_data;
 
 #undef CONFIG_BATTERY_DEVICE_CHEMISTRY
 #ifdef CONFIG_PLATFORM_EC_USE_BATTERY_DEVICE_CHEMISTRY
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY	\
+#define CONFIG_BATTERY_DEVICE_CHEMISTRY \
 	CONFIG_PLATFORM_EC_BATTERY_DEVICE_CHEMISTRY
 #endif
 
@@ -2366,13 +2411,13 @@ extern struct jump_data mock_jump_data;
 
 #undef CONFIG_CHARGER_BQ25710_SENSE_RESISTOR
 #ifdef CONFIG_PLATFORM_EC_CHARGER_BQ25710_SENSE_RESISTOR
-#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR	\
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR \
 	CONFIG_PLATFORM_EC_CHARGER_BQ25710_SENSE_RESISTOR
 #endif
 
 #undef CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC
 #ifdef CONFIG_PLATFORM_EC_CHARGER_BQ25710_SENSE_RESISTOR_AC
-#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC	\
+#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC \
 	CONFIG_PLATFORM_EC_CHARGER_BQ25710_SENSE_RESISTOR_AC
 #endif
 
@@ -2413,13 +2458,12 @@ extern struct jump_data mock_jump_data;
 
 #undef CONFIG_CHARGER_SENSE_RESISTOR
 #ifdef CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR
-#define CONFIG_CHARGER_SENSE_RESISTOR	\
-	CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR
+#define CONFIG_CHARGER_SENSE_RESISTOR CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR
 #endif
 
 #undef CONFIG_CHARGER_SENSE_RESISTOR_AC
 #ifdef CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC	\
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC \
 	CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC
 #endif
 
@@ -2454,8 +2498,7 @@ extern struct jump_data mock_jump_data;
 #undef CONFIG_MP2964
 #ifdef CONFIG_PLATFORM_EC_MP2964
 #define CONFIG_MP2964
-#define I2C_ADDR_MP2964_FLAGS \
-	DT_REG_ADDR(DT_NODELABEL(pmic_mp2964))
+#define I2C_ADDR_MP2964_FLAGS DT_REG_ADDR(DT_NODELABEL(pmic_mp2964))
 #endif
 
 #undef CONFIG_ACCELGYRO_ICM_COMM_SPI
@@ -2503,6 +2546,11 @@ extern struct jump_data mock_jump_data;
 #define CONFIG_PORT80_4_BYTE
 #endif
 
+#undef CONFIG_PORT80_QUIET
+#ifdef CONFIG_PLATFORM_EC_PORT80_QUIET
+#define CONFIG_PORT80_QUIET
+#endif
+
 #undef CONFIG_ASSERT_CCD_MODE_ON_DTS_CONNECT
 #ifdef CONFIG_PLATFORM_EC_ASSERT_CCD_MODE_ON_DTS_CONNECT
 #define CONFIG_ASSERT_CCD_MODE_ON_DTS_CONNECT
@@ -2597,4 +2645,14 @@ extern struct jump_data mock_jump_data;
 #define CONFIG_IO_EXPANDER_CCGXXF
 #endif
 
-#endif  /* __CROS_EC_CONFIG_CHIP_H */
+#undef CONFIG_PERIPHERAL_CHARGER
+#ifdef CONFIG_PLATFORM_EC_PERIPHERAL_CHARGER
+#define CONFIG_PERIPHERAL_CHARGER
+#endif
+
+#undef CONFIG_CPS8100
+#ifdef CONFIG_PLATFORM_EC_CPS8100
+#define CONFIG_CPS8100
+#endif
+
+#endif /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/zephyr/shim/include/cpu.h b/zephyr/shim/include/cpu.h
index 617f644fa9..3e65aa0061 100644
--- a/zephyr/shim/include/cpu.h
+++ b/zephyr/shim/include/cpu.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/shim/include/cros_cbi.h b/zephyr/shim/include/cros_cbi.h
index 40a2b9d8ec..1f8a1b3dfa 100644
--- a/zephyr/shim/include/cros_cbi.h
+++ b/zephyr/shim/include/cros_cbi.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,18 +14,17 @@
  * Macros are _INST_ types, so require DT_DRV_COMPAT to be defined.
  */
 #define DT_DRV_COMPAT named_cbi_ssfc_value
-#define CROS_CBI_LABEL				"cros_cbi"
+#define CROS_CBI_LABEL "cros_cbi"
 
-#define CBI_SSFC_VALUE_COMPAT			named_cbi_ssfc_value
-#define CBI_SSFC_VALUE_ID(id)			DT_CAT(CBI_SSFC_VALUE_, id)
-#define CBI_SSFC_VALUE_ID_WITH_COMMA(id)	CBI_SSFC_VALUE_ID(id),
+#define CBI_SSFC_VALUE_COMPAT named_cbi_ssfc_value
+#define CBI_SSFC_VALUE_ID(id) DT_CAT(CBI_SSFC_VALUE_, id)
+#define CBI_SSFC_VALUE_ID_WITH_COMMA(id) CBI_SSFC_VALUE_ID(id),
 #define CBI_SSFC_VALUE_INST_ENUM(inst, _) \
 	CBI_SSFC_VALUE_ID_WITH_COMMA(DT_INST(inst, CBI_SSFC_VALUE_COMPAT))
 
 enum cbi_ssfc_value_id {
 	LISTIFY(DT_NUM_INST_STATUS_OKAY(CBI_SSFC_VALUE_COMPAT),
-		     CBI_SSFC_VALUE_INST_ENUM, ())
-	CBI_SSFC_VALUE_COUNT
+		CBI_SSFC_VALUE_INST_ENUM, ()) CBI_SSFC_VALUE_COUNT
 };
 
 #undef DT_DRV_COMPAT
@@ -34,19 +33,18 @@ enum cbi_ssfc_value_id {
  * Macros to help generate the enum list of field and value names
  * for the FW_CONFIG CBI data.
  */
-#define CBI_FW_CONFIG_COMPAT		cros_ec_cbi_fw_config
-#define CBI_FW_CONFIG_VALUE_COMPAT	cros_ec_cbi_fw_config_value
+#define CBI_FW_CONFIG_COMPAT cros_ec_cbi_fw_config
+#define CBI_FW_CONFIG_VALUE_COMPAT cros_ec_cbi_fw_config_value
 
 /*
  * Retrieve the enum-name property for this node.
  */
-#define CBI_FW_CONFIG_ENUM(node)	DT_STRING_TOKEN(node, enum_name)
+#define CBI_FW_CONFIG_ENUM(node) DT_STRING_TOKEN(node, enum_name)
 
 /*
  * Create an enum entry without a value (an enum with a following comma).
  */
-#define CBI_FW_CONFIG_ENUM_WITH_COMMA(node)	\
-	CBI_FW_CONFIG_ENUM(node),
+#define CBI_FW_CONFIG_ENUM_WITH_COMMA(node) CBI_FW_CONFIG_ENUM(node),
 
 /*
  * Create a single enum entry with assignment to the node's value,
@@ -67,7 +65,7 @@ enum cbi_ssfc_value_id {
 enum cbi_fw_config_field_id {
 	DT_FOREACH_STATUS_OKAY(CBI_FW_CONFIG_COMPAT,
 			       CBI_FW_CONFIG_CHILD_ENUM_LIST)
-	CBI_FW_CONFIG_FIELDS_COUNT
+		CBI_FW_CONFIG_FIELDS_COUNT
 };
 
 /*
@@ -76,7 +74,8 @@ enum cbi_fw_config_field_id {
 enum cbi_fw_config_value_id {
 	DT_FOREACH_STATUS_OKAY(CBI_FW_CONFIG_VALUE_COMPAT,
 			       CBI_FW_CONFIG_ENUM_WITH_VALUE)
-	CBI_FW_CONFIG_VALUES_LAST /* added to ensure at least one entry */
+		CBI_FW_CONFIG_VALUES_LAST /* added to ensure at least one entry
+					   */
 };
 
 /**
diff --git a/zephyr/shim/include/ec_tasks.h b/zephyr/shim/include/ec_tasks.h
index 9b2998b64a..793beb25ae 100644
--- a/zephyr/shim/include/ec_tasks.h
+++ b/zephyr/shim/include/ec_tasks.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/shim/include/fpu.h b/zephyr/shim/include/fpu.h
index 8f78fb587d..d1e4460827 100644
--- a/zephyr/shim/include/fpu.h
+++ b/zephyr/shim/include/fpu.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,11 +25,7 @@ static inline float sqrtf(float v)
 	float root;
 
 	/* Use the CPU instruction */
-	__asm__ volatile(
-		"fsqrts %0, %1"
-		: "=w" (root)
-		: "w" (v)
-	);
+	__asm__ volatile("fsqrts %0, %1" : "=w"(root) : "w"(v));
 
 	return root;
 }
@@ -39,11 +35,7 @@ static inline float fabsf(float v)
 	float root;
 
 	/* Use the CPU instruction */
-	__asm__ volatile(
-		"fabss %0, %1"
-		: "=w" (root)
-		: "w" (v)
-	);
+	__asm__ volatile("fabss %0, %1" : "=w"(root) : "w"(v));
 
 	return root;
 }
@@ -67,6 +59,6 @@ static inline float fabsf(float v)
 #error "Unsupported core: please add an implementation"
 #endif
 
-#endif  /* CONFIG_PLATFORM_EC_FPU */
+#endif /* CONFIG_PLATFORM_EC_FPU */
 
-#endif  /* __CROS_EC_MATH_H */
+#endif /* __CROS_EC_MATH_H */
diff --git a/zephyr/shim/include/gpio/gpio.h b/zephyr/shim/include/gpio/gpio.h
index 6f92ed5795..3f95bdbbe0 100644
--- a/zephyr/shim/include/gpio/gpio.h
+++ b/zephyr/shim/include/gpio/gpio.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -74,8 +74,8 @@ int gpio_config_unused_pins(void) __attribute__((weak));
  */
 #define UNUSED_GPIO_CONFIG_BY_IDX(i, _)                                       \
 	{                                                                     \
-		.dev_name = DT_GPIO_LABEL_BY_IDX(UNUSED_PINS_LIST,            \
-						 unused_gpios, i),            \
+		.dev_name = DEVICE_DT_NAME(DT_GPIO_CTLR_BY_IDX(               \
+			UNUSED_PINS_LIST, unused_gpios, i)),                  \
 		.pin = DT_GPIO_PIN_BY_IDX(UNUSED_PINS_LIST, unused_gpios, i), \
 		.flags = DT_GPIO_FLAGS_BY_IDX(UNUSED_PINS_LIST, unused_gpios, \
 					      i),                             \
diff --git a/zephyr/shim/include/gpio/gpio_int.h b/zephyr/shim/include/gpio/gpio_int.h
index 5cbddf76ca..835c5503ba 100644
--- a/zephyr/shim/include/gpio/gpio_int.h
+++ b/zephyr/shim/include/gpio/gpio_int.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,8 +23,7 @@
 /*
  * Maps nodelabel of interrupt node to internal configuration block.
  */
-#define GPIO_INT_FROM_NODELABEL(lbl) \
-	(GPIO_INT_FROM_NODE(DT_NODELABEL(lbl)))
+#define GPIO_INT_FROM_NODELABEL(lbl) (GPIO_INT_FROM_NODE(DT_NODELABEL(lbl)))
 
 /*
  * Unique enum name for the interrupt.
@@ -34,17 +33,15 @@
 /*
  * Create an enum list of the interrupts
  */
-#define GPIO_INT_ENUM_WITH_COMMA(id) GPIO_INT_ENUM(id),
 enum gpio_interrupts {
 #if DT_HAS_COMPAT_STATUS_OKAY(cros_ec_gpio_interrupts)
-	DT_FOREACH_CHILD(DT_COMPAT_GET_ANY_STATUS_OKAY(cros_ec_gpio_interrupts),
-		GPIO_INT_ENUM_WITH_COMMA)
+	DT_FOREACH_CHILD_SEP(
+		DT_COMPAT_GET_ANY_STATUS_OKAY(cros_ec_gpio_interrupts),
+		GPIO_INT_ENUM, (, )),
 #endif
-		GPIO_INT_COUNT
+	GPIO_INT_COUNT
 };
 
-#undef GPIO_INT_ENUM_WITH_COMMA
-
 /*
  * Forward reference to avoiding exposing internal structure
  * defined in gpio_int.c
@@ -60,24 +57,24 @@ struct gpio_int_config;
  *   ... // set up device
  *   gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(my_interrupt_node));
  */
-int gpio_enable_dt_interrupt(const struct gpio_int_config * const ic);
+int gpio_enable_dt_interrupt(const struct gpio_int_config *const ic);
 
 /*
  * Disable the interrupt.
  */
-int gpio_disable_dt_interrupt(const struct gpio_int_config * const ic);
+int gpio_disable_dt_interrupt(const struct gpio_int_config *const ic);
 
 /*
  * Get the interrupt config for this interrupt.
  */
 const struct gpio_int_config *
-	gpio_interrupt_get_config(enum gpio_interrupts intr);
+gpio_interrupt_get_config(enum gpio_interrupts intr);
 
 /*
  * Declare interrupt configuration data structures.
  */
-#define GPIO_INT_DECLARE(id)	\
-	extern const struct gpio_int_config * const GPIO_INT_FROM_NODE(id);
+#define GPIO_INT_DECLARE(id) \
+	extern const struct gpio_int_config *const GPIO_INT_FROM_NODE(id);
 
 #if DT_HAS_COMPAT_STATUS_OKAY(cros_ec_gpio_interrupts)
 DT_FOREACH_CHILD(DT_COMPAT_GET_ANY_STATUS_OKAY(cros_ec_gpio_interrupts),
diff --git a/zephyr/shim/include/hook_types.h b/zephyr/shim/include/hook_types.h
index bcd1d0119c..004e5a52db 100644
--- a/zephyr/shim/include/hook_types.h
+++ b/zephyr/shim/include/hook_types.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -47,6 +47,6 @@
 		HOOK_POWER_BUTTON_CHANGE, HOOK_BATTERY_SOC_CHANGE,         \
 		HOOK_TYPES_USB_SUSPEND, HOOK_TICK, HOOK_SECOND,            \
 		HOOK_USB_PD_DISCONNECT, HOOK_USB_PD_CONNECT,               \
-		HOOK_TYPES_TEST_BUILD)
+		HOOK_POWER_SUPPLY_CHANGE, HOOK_TYPES_TEST_BUILD)
 
 #endif
diff --git a/zephyr/shim/include/i2c/i2c.h b/zephyr/shim/include/i2c/i2c.h
index c7e29e79e5..3e95fbc9d3 100644
--- a/zephyr/shim/include/i2c/i2c.h
+++ b/zephyr/shim/include/i2c/i2c.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,36 +12,170 @@
 #ifdef CONFIG_PLATFORM_EC_I2C
 #if DT_NODE_EXISTS(DT_PATH(named_i2c_ports))
 
-#define I2C_PORT(id) DT_STRING_UPPER_TOKEN(id, enum_name)
-#define I2C_PORT_WITH_COMMA(id) I2C_PORT(id),
+#define NPCX_PORT_COMPAT nuvoton_npcx_i2c_port
+#define ITE_IT8XXX2_PORT_COMPAT ite_it8xxx2_i2c
+#define ITE_ENHANCE_PORT_COMPAT ite_enhance_i2c
+#define MICROCHIP_XEC_COMPAT microchip_xec_i2c_v2
+#define I2C_EMUL_COMPAT zephyr_i2c_emul_controller
+#define I2C_FOREACH_PORT(fn)                                \
+	DT_FOREACH_STATUS_OKAY(NPCX_PORT_COMPAT, fn)        \
+	DT_FOREACH_STATUS_OKAY(ITE_IT8XXX2_PORT_COMPAT, fn) \
+	DT_FOREACH_STATUS_OKAY(ITE_ENHANCE_PORT_COMPAT, fn) \
+	DT_FOREACH_STATUS_OKAY(MICROCHIP_XEC_COMPAT, fn)    \
+	DT_FOREACH_STATUS_OKAY(I2C_EMUL_COMPAT, fn)
 
+/*
+ * Get the legacy I2C port enum value from the I2C bus node identifier.
+ * The value returned by this macro is passed as the 'int port' parameter to all
+ * the legacy APIs provided by i2c_controller.h
+ *
+ * Example devicetree fragment:
+ *
+ *     / {
+ *         soc-if {
+ *             i2c2_0: io_i2c_ctrl2_port0 {
+ *                 compatible = "nuvoton,npcx-i2c-port";
+ *                 #address-cells = <1>;
+ *                 #size-cells = <0>;
+ *                 port = <0x20>;
+ *                 controller = <&i2c_ctrl2>;
+ *                 label = "I2C_2_PORT_0";
+ *                 status = "disabled";
+ *             };
+ *         }.
+ *     };
+ *
+ * Example usage to get the I2C port enum value for i2c2_0:
+ *
+ *     I2C_PORT_BUS(DT_NODELABEL(i2c2_0))
+ *     // I2C_BUS_DT_N_S_soc_if_S_io_i2c_ctrl2_port0
+ *
+ * @param i2c_port_id: node id of a I2C port device
+ */
+#define I2C_PORT_BUS(i2c_port_id) DT_CAT(I2C_BUS_, i2c_port_id)
+#define I2C_PORT_BUS_WITH_COMMA(i2c_port_id) I2C_PORT_BUS(i2c_port_id),
+
+/*
+ * Get the legacy I2C port enum value from a named-i2c-ports child node.
+ *
+ * Example devicetree fragment:
+ *
+ *     i2c0_0: io_i2c_ctrl0_port0 {
+ *         compatible = "nuvoton,npcx-i2c-port";
+ *         #address-cells = <1>;
+ *         #size-cells = <0>;
+ *         port = <0x00>;
+ *         controller = <&i2c_ctrl0>;
+ *         label = "I2C_0_PORT_0";
+ *         status = "disabled";
+ *     };
+ *
+ *     named-i2c-ports {
+ *         compatible = "named-i2c-ports";
+ *         i2c_sensor: sensor {
+ *             i2c-port = <&i2c0_0>;
+ *             enum-names = "I2C_PORT_SENSOR";
+ *         };
+ *     };
+ *
+ * Example usage to get the I2C port enum value for i2c_sensor:
+ *
+ *     I2C_PORT(DT_NODELABEL(i2c_sensor))
+ *
+ * which equals:
+ *
+ *     I2C_PORT_BUS(DT_NODELABEL(i2c0_0))
+ *
+ * @param i2c_named_id: node id of a child of the named-i2c-ports node
+ */
+#define I2C_PORT(i2c_named_id) I2C_PORT_BUS(DT_PHANDLE(i2c_named_id, i2c_port))
+
+/*
+ * Get the legacy I2C port enum from the I2C bus nodelabel. This macro should be
+ * used with the I2C port device node, not the named-i2c-port child node.
+ *
+ *     / {
+ *         soc-if {
+ *             i2c2_0: io_i2c_ctrl2_port0 {
+ *                 compatible = "nuvoton,npcx-i2c-port";
+ *                 #address-cells = <1>;
+ *                 #size-cells = <0>;
+ *                 port = <0x20>;
+ *                 controller = <&i2c_ctrl2>;
+ *                 label = "I2C_2_PORT_0";
+ *                 status = "disabled";
+ *             };
+ *         }.
+ *     };
+ *
+ * Example usage to get the I2C port enum value for i2c2_0:
+ *
+ *     I2C_PORT_NODELABEL(i2c2_0)
+ *     // I2C_BUS_DT_N_S_soc_if_S_io_i2c_ctrl2_port0
+ *
+ * @param label: nodelabel of a I2C port device
+ */
+#define I2C_PORT_NODELABEL(label) I2C_PORT_BUS(DT_NODELABEL(label))
+
+/*
+ * Get the legacy I2C port enum for a child device on an I2C bus.
+ *
+ * Example devicetree fragment:
+ *
+ *     i2c2_0: io_i2c_ctrl2_port0 {
+ *         compatible = "nuvoton,npcx-i2c-port";
+ *         #address-cells = <1>;
+ *         #size-cells = <0>;
+ *         port = <0x20>;
+ *         controller = <&i2c_ctrl2>;
+ *         label = "I2C_2_PORT_0";
+ *         status = "disabled";
+ *     };
+ *
+ *     &i2c2_0 {
+ *         bc12_port0: pi3usb9201@5f {
+ *             compatible = "pericom,pi3usb9201";
+ *             status = "okay";
+ *             reg = <0x5f>;
+ *             irq = <&int_usb_c0_bc12>;
+ *         };
+ *     };
+ *
+ * Example usage to get the I2C port enum value for bc12_port0:
+ *
+ *     I2C_PORT_BY_DEV(DT_NODELABEL(bc12_port0))
+ *
+ *  * which equals:
+ *
+ *     I2C_PORT_BUS(DT_NODELABEL(i2c2_0))
+ *
+ * @param dev_id: node id of a device on the I2C bus
+ */
+#define I2C_PORT_BY_DEV(dev_id) I2C_PORT_BUS(DT_BUS(dev_id))
+
+enum i2c_ports_chip {
+	I2C_FOREACH_PORT(I2C_PORT_BUS_WITH_COMMA) I2C_PORT_COUNT
+};
+
+BUILD_ASSERT(I2C_PORT_COUNT != 0, "No I2C devices defined");
+
+#define I2C_PORT_ENUM_IDX_COMMA(i2c_named_id, prop, idx)        \
+	DT_STRING_UPPER_TOKEN_BY_IDX(i2c_named_id, prop, idx) = \
+		I2C_PORT(i2c_named_id),
+#define NAMED_I2C_PORT_COMMA(i2c_named_id) \
+	DT_FOREACH_PROP_ELEM(i2c_named_id, enum_names, I2C_PORT_ENUM_IDX_COMMA)
+
+/*
+ * The enum i2c_ports maps the hard-coded I2C port names (such as
+ * I2C_PORT_BATTERY or I2C_PORT_SENSOR) to the unique port numbers created by
+ * enum i2c_ports_chip above for every I2C port devicetree node.
+ */
 enum i2c_ports {
-	DT_FOREACH_CHILD(DT_PATH(named_i2c_ports), I2C_PORT_WITH_COMMA)
-	I2C_PORT_COUNT
+	DT_FOREACH_CHILD(DT_PATH(named_i2c_ports), NAMED_I2C_PORT_COMMA)
 };
-#define NAMED_I2C(name) I2C_PORT(DT_PATH(named_i2c_ports, name))
 #endif /* named_i2c_ports */
 #endif /* CONFIG_PLATFORM_EC_I2C */
 
-#ifdef CONFIG_I2C_NPCX
-#define I2C_COMPAT nuvoton_npcx_i2c_port
-#elif CONFIG_I2C_ITE_IT8XXX2
-#define I2C_COMPAT ite_it8xxx2_i2c
-#elif CONFIG_I2C_XEC_V2
-#define I2C_COMPAT microchip_xec_i2c_v2
-#elif CONFIG_I2C_EMUL
-#define I2C_COMPAT zephyr_i2c_emul_controller
-#else
-#error An undefined I2C driver is used.
-#endif
-
-#if defined(CONFIG_I2C_ITE_IT8XXX2) && defined(CONFIG_I2C_ITE_ENHANCE)
-#define I2C_DEVICE_COUNT DT_NUM_INST_STATUS_OKAY(ite_it8xxx2_i2c) +            \
-			 DT_NUM_INST_STATUS_OKAY(ite_enhance_i2c)
-#else
-#define I2C_DEVICE_COUNT DT_NUM_INST_STATUS_OKAY(I2C_COMPAT)
-#endif
-
 /**
  * @brief Adaptation of platform/ec's port IDs which map a port/bus to a device.
  *
diff --git a/zephyr/shim/include/linker.h b/zephyr/shim/include/linker.h
index 335f4f0f19..92dc8f5981 100644
--- a/zephyr/shim/include/linker.h
+++ b/zephyr/shim/include/linker.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,6 +7,6 @@
 #define __CROS_EC_LINKER_H
 
 /* Put the start of shared memory after all allocated RAM symbols */
-#define __shared_mem_buf	_image_ram_end
+#define __shared_mem_buf _image_ram_end
 
 #endif
diff --git a/zephyr/shim/include/motionsense_sensors.h b/zephyr/shim/include/motionsense_sensors.h
index f3bd6befe0..e00eae426e 100644
--- a/zephyr/shim/include/motionsense_sensors.h
+++ b/zephyr/shim/include/motionsense_sensors.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,14 +14,14 @@ extern struct motion_sensor_t motion_sensors_alt[];
 /*
  * Common macros.
  */
-#define SENSOR_ROT_STD_REF_NAME(id)	DT_CAT(ROT_REF_, id)
-#define SENSOR_ROT_REF_NODE		DT_PATH(motionsense_rotation_ref)
+#define SENSOR_ROT_STD_REF_NAME(id) DT_CAT(ROT_REF_, id)
+#define SENSOR_ROT_REF_NODE DT_PATH(motionsense_rotation_ref)
 
 /*
  * Declare rotation parameters, since they may be
  * dynamically selected.
  */
-#define DECLARE_EXTERN_SENSOR_ROT_REF(id)				\
+#define DECLARE_EXTERN_SENSOR_ROT_REF(id) \
 	extern const mat33_fp_t SENSOR_ROT_STD_REF_NAME(id);
 
 #if DT_NODE_EXISTS(SENSOR_ROT_REF_NODE)
@@ -45,18 +45,18 @@ int motion_sense_probe(enum sensor_alt_id alt_idx);
  */
 void motion_sensors_check_ssfc(void);
 
-#define ENABLE_ALT_MOTION_SENSOR(alt_id) \
+#define ENABLE_ALT_MOTION_SENSOR(alt_id)                               \
 	motion_sensors[SENSOR_ID(DT_PHANDLE(alt_id, alternate_for))] = \
 		motion_sensors_alt[SENSOR_ID(alt_id)];
 
 /*
  * Replaces a default motion sensor with an alternate one pointed by nodelabel.
  */
-#define MOTIONSENSE_ENABLE_ALTERNATE(nodelabel)                              \
-	do {                                                                 \
-		BUILD_ASSERT(DT_NODE_EXISTS(DT_NODELABEL(nodelabel)),        \
-			     "Motionsense alternate node does not exist");   \
-		ENABLE_ALT_MOTION_SENSOR(DT_NODELABEL(nodelabel));           \
+#define MOTIONSENSE_ENABLE_ALTERNATE(nodelabel)                            \
+	do {                                                               \
+		BUILD_ASSERT(DT_NODE_EXISTS(DT_NODELABEL(nodelabel)),      \
+			     "Motionsense alternate node does not exist"); \
+		ENABLE_ALT_MOTION_SENSOR(DT_NODELABEL(nodelabel));         \
 	} while (0)
 
 /*
diff --git a/zephyr/shim/include/motionsense_sensors_defs.h b/zephyr/shim/include/motionsense_sensors_defs.h
index a9535d3b5d..ac0fc6bf56 100644
--- a/zephyr/shim/include/motionsense_sensors_defs.h
+++ b/zephyr/shim/include/motionsense_sensors_defs.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,7 +10,7 @@
 
 #include "common.h"
 
-#define SENSOR_ID(id)			DT_CAT(SENSOR_, id)
+#define SENSOR_ID(id) DT_CAT(SENSOR_, id)
 
 /* Define the SENSOR_ID if:
  * DT_NODE_HAS_STATUS(id, okay) && !DT_NODE_HAS_PROP(id, alternate_for)
@@ -24,7 +24,7 @@ enum sensor_id {
 #if DT_NODE_EXISTS(SENSOR_NODE)
 	DT_FOREACH_CHILD(SENSOR_NODE, SENSOR_ID_WITH_COMMA)
 #endif
-	SENSOR_COUNT,
+		SENSOR_COUNT,
 };
 
 #undef SENSOR_ID_WITH_COMMA
@@ -39,7 +39,7 @@ enum sensor_alt_id {
 #if DT_NODE_EXISTS(SENSOR_ALT_NODE)
 	DT_FOREACH_CHILD(SENSOR_ALT_NODE, SENSOR_ID_WITH_COMMA)
 #endif
-	SENSOR_ALT_COUNT,
+		SENSOR_ALT_COUNT,
 };
 
 /*
@@ -73,8 +73,8 @@ enum sensor_alt_id {
  * };
  */
 #ifdef CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_SENSOR_LID	SENSOR_ID(DT_NODELABEL(lid_accel))
-#define CONFIG_LID_ANGLE_SENSOR_BASE	SENSOR_ID(DT_NODELABEL(base_accel))
+#define CONFIG_LID_ANGLE_SENSOR_LID SENSOR_ID(DT_NODELABEL(lid_accel))
+#define CONFIG_LID_ANGLE_SENSOR_BASE SENSOR_ID(DT_NODELABEL(base_accel))
 #endif
 
 /*
@@ -90,12 +90,11 @@ enum sensor_alt_id {
  * };
  */
 #if DT_NODE_HAS_PROP(SENSOR_INFO_NODE, accel_force_mode_sensors)
-#define SENSOR_IN_FORCE_MODE(i, id)					\
+#define SENSOR_IN_FORCE_MODE(i, id) \
 	| BIT(SENSOR_ID(DT_PHANDLE_BY_IDX(id, accel_force_mode_sensors, i)))
-#define CONFIG_ACCEL_FORCE_MODE_MASK					\
-	(0 LISTIFY(DT_PROP_LEN(SENSOR_INFO_NODE,			\
-		accel_force_mode_sensors), SENSOR_IN_FORCE_MODE, (),	\
-		SENSOR_INFO_NODE))
+#define CONFIG_ACCEL_FORCE_MODE_MASK                                        \
+	(0 LISTIFY(DT_PROP_LEN(SENSOR_INFO_NODE, accel_force_mode_sensors), \
+		   SENSOR_IN_FORCE_MODE, (), SENSOR_INFO_NODE))
 #endif
 
 #endif /* __CROS_EC_MOTIONSENSE_SENSORS_DEFS_H */
diff --git a/zephyr/shim/include/mpu.h b/zephyr/shim/include/mpu.h
index 3555ef0db1..29771c9fe0 100644
--- a/zephyr/shim/include/mpu.h
+++ b/zephyr/shim/include/mpu.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/shim/include/power/power.h b/zephyr/shim/include/power/power.h
index 6ea2444705..1e780646af 100644
--- a/zephyr/shim/include/power/power.h
+++ b/zephyr/shim/include/power/power.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,63 +9,36 @@
 #include <zephyr/devicetree.h>
 #include <zephyr/drivers/gpio.h>
 
-#define POWER_SIGNAL_LIST_NODE                                                \
-	DT_NODELABEL(power_signal_list)
+#define POWER_SIGNAL_LIST_NODE DT_NODELABEL(power_signal_list)
 
-#define SYSTEM_DT_POWER_SIGNAL_CONFIG                                         \
-	DT_NODE_EXISTS(POWER_SIGNAL_LIST_NODE)
+#define SYSTEM_DT_POWER_SIGNAL_CONFIG DT_NODE_EXISTS(POWER_SIGNAL_LIST_NODE)
 
 #if (SYSTEM_DT_POWER_SIGNAL_CONFIG)
 
-#define GEN_POWER_SIGNAL_STRUCT_ENTRY_GPIO(cid)                               \
-	DT_STRING_UPPER_TOKEN(                                                \
-		DT_PROP(                                                      \
-			cid,                                                  \
-			power_gpio_pin                                        \
-		),                                                            \
-		enum_name                                                     \
-	)
-#define GEN_POWER_SIGNAL_STRUCT_ENTRY_FLAGS(cid)                              \
-(                                                                             \
-	DT_GPIO_FLAGS(                                                        \
-		DT_PROP(                                                      \
-			cid,                                                  \
-			power_gpio_pin                                        \
-		),                                                            \
-		gpios                                                         \
-	) & GPIO_ACTIVE_LOW                                                   \
-		? POWER_SIGNAL_ACTIVE_LOW                                     \
-		: POWER_SIGNAL_ACTIVE_HIGH                                    \
-)
-#define GEN_POWER_SIGNAL_STRUCT_ENTRY_NAME(cid)                               \
-	DT_PROP(                                                              \
-		cid,                                                          \
-		power_enum_name                                               \
-	)
-
-#define GEN_POWER_SIGNAL_STRUCT_ENTRY(cid)                                    \
-{                                                                             \
-	.gpio = GEN_POWER_SIGNAL_STRUCT_ENTRY_GPIO(cid),                      \
-	.flags = GEN_POWER_SIGNAL_STRUCT_ENTRY_FLAGS(cid),                    \
-	.name = GEN_POWER_SIGNAL_STRUCT_ENTRY_NAME(cid)                       \
-}
-#define GEN_POWER_SIGNAL_STRUCT(cid)                                          \
-	[GEN_POWER_SIGNAL_ENUM_ENTRY(cid)] =                                  \
-		GEN_POWER_SIGNAL_STRUCT_ENTRY(cid),
-
-
-#define GEN_POWER_SIGNAL_ENUM_ENTRY(cid)                                      \
-	DT_STRING_UPPER_TOKEN(                                                \
-		cid,                                                          \
-		power_enum_name                                               \
-	)
-#define GEN_POWER_SIGNAL_ENUM_ENTRY_COMMA(cid)                                \
-	GEN_POWER_SIGNAL_ENUM_ENTRY(cid),
+#define GEN_POWER_SIGNAL_STRUCT_ENTRY_GPIO(cid) \
+	DT_STRING_UPPER_TOKEN(DT_PROP(cid, power_gpio_pin), enum_name)
+#define GEN_POWER_SIGNAL_STRUCT_ENTRY_FLAGS(cid)              \
+	(DT_GPIO_FLAGS(DT_PROP(cid, power_gpio_pin), gpios) & \
+			 GPIO_ACTIVE_LOW ?                    \
+		 POWER_SIGNAL_ACTIVE_LOW :                    \
+		 POWER_SIGNAL_ACTIVE_HIGH)
+#define GEN_POWER_SIGNAL_STRUCT_ENTRY_NAME(cid) DT_PROP(cid, power_enum_name)
+
+#define GEN_POWER_SIGNAL_STRUCT_ENTRY(cid)                         \
+	{                                                          \
+		.gpio = GEN_POWER_SIGNAL_STRUCT_ENTRY_GPIO(cid),   \
+		.flags = GEN_POWER_SIGNAL_STRUCT_ENTRY_FLAGS(cid), \
+		.name = GEN_POWER_SIGNAL_STRUCT_ENTRY_NAME(cid)    \
+	}
+#define GEN_POWER_SIGNAL_STRUCT(cid) \
+	[GEN_POWER_SIGNAL_ENUM_ENTRY(cid)] = GEN_POWER_SIGNAL_STRUCT_ENTRY(cid),
+
+#define GEN_POWER_SIGNAL_ENUM_ENTRY(cid) \
+	DT_STRING_UPPER_TOKEN(cid, power_enum_name)
 
 enum power_signal {
-	DT_FOREACH_CHILD(
-		POWER_SIGNAL_LIST_NODE,
-		GEN_POWER_SIGNAL_ENUM_ENTRY_COMMA)
+	DT_FOREACH_CHILD_SEP(POWER_SIGNAL_LIST_NODE,
+			     GEN_POWER_SIGNAL_ENUM_ENTRY, (, )),
 	POWER_SIGNAL_COUNT
 };
 
@@ -73,11 +46,8 @@ enum power_signal {
  * Verify the number of required power-signals are specified in
  * the DeviceTree
  */
-#define POWER_SIGNALS_REQUIRED                                                \
-	DT_PROP(                                                              \
-		POWER_SIGNAL_LIST_NODE,                                       \
-		power_signals_required                                        \
-	)
+#define POWER_SIGNALS_REQUIRED \
+	DT_PROP(POWER_SIGNAL_LIST_NODE, power_signals_required)
 BUILD_ASSERT(POWER_SIGNALS_REQUIRED == POWER_SIGNAL_COUNT);
 
 #endif /* SYSTEM_DT_POWER_SIGNAL_CONFIG */
diff --git a/zephyr/shim/include/power_host_sleep.h b/zephyr/shim/include/power_host_sleep.h
index cc7fe04847..8bc23fc785 100644
--- a/zephyr/shim/include/power_host_sleep.h
+++ b/zephyr/shim/include/power_host_sleep.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,31 +24,31 @@
 /* power.h */
 enum power_state {
 	/* Steady states */
-	POWER_G3 = 0,	/*
-			 * System is off (not technically all the way into G3,
-			 * which means totally unpowered...)
-			 */
-	POWER_S5,		/* System is soft-off */
-	POWER_S4,		/* System is suspended to disk */
-	POWER_S3,		/* Suspend; RAM on, processor is asleep */
-	POWER_S0,		/* System is on */
+	POWER_G3 = 0, /*
+		       * System is off (not technically all the way into G3,
+		       * which means totally unpowered...)
+		       */
+	POWER_S5, /* System is soft-off */
+	POWER_S4, /* System is suspended to disk */
+	POWER_S3, /* Suspend; RAM on, processor is asleep */
+	POWER_S0, /* System is on */
 #if CONFIG_AP_PWRSEQ_S0IX
 	POWER_S0ix,
 #endif
 	/* Transitions */
-	POWER_G3S5,	/* G3 -> S5 (at system init time) */
-	POWER_S5S3,	/* S5 -> S3 (skips S4 on non-Intel systems) */
-	POWER_S3S0,	/* S3 -> S0 */
-	POWER_S0S3,	/* S0 -> S3 */
-	POWER_S3S5,	/* S3 -> S5 (skips S4 on non-Intel systems) */
-	POWER_S5G3,	/* S5 -> G3 */
-	POWER_S3S4,	/* S3 -> S4 */
-	POWER_S4S3,	/* S4 -> S3 */
-	POWER_S4S5,	/* S4 -> S5 */
-	POWER_S5S4,	/* S5 -> S4 */
+	POWER_G3S5, /* G3 -> S5 (at system init time) */
+	POWER_S5S3, /* S5 -> S3 (skips S4 on non-Intel systems) */
+	POWER_S3S0, /* S3 -> S0 */
+	POWER_S0S3, /* S0 -> S3 */
+	POWER_S3S5, /* S3 -> S5 (skips S4 on non-Intel systems) */
+	POWER_S5G3, /* S5 -> G3 */
+	POWER_S3S4, /* S3 -> S4 */
+	POWER_S4S3, /* S4 -> S3 */
+	POWER_S4S5, /* S4 -> S5 */
+	POWER_S5S4, /* S5 -> S4 */
 #if CONFIG_AP_PWRSEQ_S0IX
-	POWER_S0ixS0,   /* S0ix -> S0 */
-	POWER_S0S0ix,   /* S0 -> S0ix */
+	POWER_S0ixS0, /* S0ix -> S0 */
+	POWER_S0S0ix, /* S0 -> S0ix */
 #endif
 };
 
@@ -56,12 +56,11 @@ enum power_state {
 /* Context to pass to a host sleep command handler. */
 struct host_sleep_event_context {
 	uint32_t sleep_transitions; /* Number of sleep transitions observed */
-	uint16_t sleep_timeout_ms;  /* Timeout in milliseconds */
+	uint16_t sleep_timeout_ms; /* Timeout in milliseconds */
 };
 
 void ap_power_chipset_handle_host_sleep_event(
-		enum host_sleep_event state,
-		struct host_sleep_event_context *ctx);
+	enum host_sleep_event state, struct host_sleep_event_context *ctx);
 void power_set_host_sleep_state(enum host_sleep_event state);
 #endif /* CONFIG_AP_PWRSEQ_HOST_SLEEP */
 
diff --git a/zephyr/shim/include/registers.h b/zephyr/shim/include/registers.h
index b693733a21..f17b05f5f8 100644
--- a/zephyr/shim/include/registers.h
+++ b/zephyr/shim/include/registers.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/shim/include/shimmed_task_id.h b/zephyr/shim/include/shimmed_task_id.h
index 31df4daece..1a29acafdf 100644
--- a/zephyr/shim/include/shimmed_task_id.h
+++ b/zephyr/shim/include/shimmed_task_id.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,14 +14,13 @@ typedef uint8_t task_id_t;
 /*
  * Bitmask of port enable bits, expanding to a value like `BIT(0) | BIT(2) | 0`.
  */
-#define PD_INT_SHARED_PORT_MASK ( \
-	FOR_EACH_NONEMPTY_TERM(BIT, (|),		\
-		IF_ENABLED(CONFIG_PLATFORM_EC_USB_PD_PORT_0_SHARED, (0)),	\
-		IF_ENABLED(CONFIG_PLATFORM_EC_USB_PD_PORT_1_SHARED, (1)),	\
-		IF_ENABLED(CONFIG_PLATFORM_EC_USB_PD_PORT_2_SHARED, (2)),	\
-		IF_ENABLED(CONFIG_PLATFORM_EC_USB_PD_PORT_3_SHARED, (3)),	\
-	) 0 \
-)
+#define PD_INT_SHARED_PORT_MASK                                           \
+	(FOR_EACH_NONEMPTY_TERM(                                          \
+		BIT, (|),                                                 \
+		IF_ENABLED(CONFIG_PLATFORM_EC_USB_PD_PORT_0_SHARED, (0)), \
+		IF_ENABLED(CONFIG_PLATFORM_EC_USB_PD_PORT_1_SHARED, (1)), \
+		IF_ENABLED(CONFIG_PLATFORM_EC_USB_PD_PORT_2_SHARED, (2)), \
+		IF_ENABLED(CONFIG_PLATFORM_EC_USB_PD_PORT_3_SHARED, (3)), ) 0)
 
 /* Highest priority on bottom -- same as in platform/ec. */
 enum {
@@ -29,10 +28,6 @@ enum {
 	EC_SYSWORKQ_PRIO = EC_TASK_PRIO_LOWEST,
 	EC_TASK_CHG_RAMP_PRIO,
 	EC_TASK_USB_CHG_PRIO,
-	EC_TASK_USB_CHG_P0_PRIO,
-	EC_TASK_USB_CHG_P1_PRIO,
-	EC_TASK_USB_CHG_P2_PRIO,
-	EC_TASK_USB_CHG_P3_PRIO,
 	EC_TASK_DPS_PRIO,
 	EC_TASK_CHARGER_PRIO,
 	EC_TASK_CHIPSET_PRIO,
@@ -64,104 +59,106 @@ enum {
  * CONFIG_HAS_TEST_TASKS and not CONFIG_SHIMMED_TASKS.
  */
 #ifdef CONFIG_SHIMMED_TASKS
-#define CROS_EC_TASK_LIST                                                 \
-	COND_CODE_1(HAS_TASK_CHG_RAMP,                                    \
-		     (CROS_EC_TASK(CHG_RAMP, chg_ramp_task, 0,            \
-				   CONFIG_TASK_CHG_RAMP_STACK_SIZE,       \
-				   EC_TASK_CHG_RAMP_PRIO)), ())           \
-	COND_CODE_1(CONFIG_PLATFORM_EC_USB_CHARGER_SINGLE_TASK,           \
-		     (CROS_EC_TASK(USB_CHG, usb_charger_task_shared, 0,   \
-				   CONFIG_TASK_USB_CHG_STACK_SIZE,        \
-				   EC_TASK_USB_CHG_PRIO)), ())            \
-	COND_CODE_1(HAS_TASK_USB_CHG_P0,                                  \
-		     (CROS_EC_TASK(USB_CHG_P0, usb_charger_task, 0,       \
-				   CONFIG_TASK_USB_CHG_STACK_SIZE,        \
-				   EC_TASK_USB_CHG_P0_PRIO)), ())         \
-	COND_CODE_1(HAS_TASK_USB_CHG_P1,                                  \
-		     (CROS_EC_TASK(USB_CHG_P1, usb_charger_task, 0,       \
-				   CONFIG_TASK_USB_CHG_STACK_SIZE,        \
-				   EC_TASK_USB_CHG_P1_PRIO)), ())         \
-	COND_CODE_1(HAS_TASK_USB_CHG_P2,                                  \
-		     (CROS_EC_TASK(USB_CHG_P2, usb_charger_task, 0,       \
-				   CONFIG_TASK_USB_CHG_STACK_SIZE,        \
-				   EC_TASK_USB_CHG_P2_PRIO)), ())         \
-	COND_CODE_1(HAS_TASK_USB_CHG_P3,                                  \
-		     (CROS_EC_TASK(USB_CHG_P3, usb_charger_task, 0,       \
-				   CONFIG_TASK_USB_CHG_STACK_SIZE,        \
-				   EC_TASK_USB_CHG_P3_PRIO)), ())         \
-	COND_CODE_1(HAS_TASK_DPS,                                         \
-		     (CROS_EC_TASK(DPS, dps_task, 0,                      \
-				   CONFIG_TASK_DPS_STACK_SIZE,            \
-				   EC_TASK_DPS_PRIO)), ())                \
-	COND_CODE_1(HAS_TASK_CHARGER,                                     \
-		     (CROS_EC_TASK(CHARGER, charger_task, 0,              \
-				   CONFIG_TASK_CHARGER_STACK_SIZE,        \
-				   EC_TASK_CHARGER_PRIO)), ())            \
-	COND_CODE_1(HAS_TASK_CHIPSET,                                     \
-		     (CROS_EC_TASK(CHIPSET, chipset_task, 0,              \
-				   CONFIG_TASK_CHIPSET_STACK_SIZE,        \
-				   EC_TASK_CHIPSET_PRIO)), ())            \
-	COND_CODE_1(HAS_TASK_MOTIONSENSE,                                 \
-		     (CROS_EC_TASK(MOTIONSENSE, motion_sense_task, 0,     \
-				   CONFIG_TASK_MOTIONSENSE_STACK_SIZE,    \
-				   EC_TASK_MOTIONSENSE_PRIO)), ())        \
-	IF_ENABLED(HAS_TASK_USB_MUX,					  \
-		   (CROS_EC_TASK(USB_MUX, usb_mux_task, 0,		  \
-				 CONFIG_TASK_USB_MUX_STACK_SIZE,          \
-				 EC_TASK_USB_MUX_PRIO)))		  \
-	COND_CODE_1(CONFIG_TASK_HOSTCMD_THREAD_DEDICATED,                 \
-		     (CROS_EC_TASK(HOSTCMD, host_command_task, 0,         \
-				   CONFIG_TASK_HOSTCMD_STACK_SIZE,        \
-				   EC_TASK_HOSTCMD_PRIO)), ())            \
-	COND_CODE_1(HAS_TASK_KEYPROTO,                                    \
-		     (CROS_EC_TASK(KEYPROTO, keyboard_protocol_task, 0,   \
-				   CONFIG_TASK_KEYPROTO_STACK_SIZE,       \
-				   EC_TASK_KEYPROTO_PRIO)), ())           \
-	COND_CODE_1(HAS_TASK_POWERBTN,                                    \
-		     (CROS_EC_TASK(POWERBTN, power_button_task, 0,        \
-				   CONFIG_TASK_POWERBTN_STACK_SIZE,       \
-				   EC_TASK_POWERBTN_PRIO)), ())           \
-	COND_CODE_1(HAS_TASK_KEYSCAN,                                     \
-		     (CROS_EC_TASK(KEYSCAN, keyboard_scan_task, 0,        \
-				   CONFIG_TASK_KEYSCAN_STACK_SIZE,        \
-				   EC_TASK_KEYSCAN_PRIO)), ())            \
-	COND_CODE_1(HAS_TASK_PD_C0,                                       \
-		     (CROS_EC_TASK(PD_C0, pd_task, 0,                     \
-				   CONFIG_TASK_PD_STACK_SIZE,             \
-				   EC_TASK_PD_C0_PRIO)), ())              \
-	COND_CODE_1(HAS_TASK_PD_C1,                                       \
-		     (CROS_EC_TASK(PD_C1, pd_task, 0,                     \
-				   CONFIG_TASK_PD_STACK_SIZE,             \
-				   EC_TASK_PD_C1_PRIO)), ())              \
-	COND_CODE_1(HAS_TASK_PD_C2,                                       \
-		     (CROS_EC_TASK(PD_C2, pd_task, 0,                     \
-				   CONFIG_TASK_PD_STACK_SIZE,             \
-				   EC_TASK_PD_C2_PRIO)), ())              \
-	COND_CODE_1(HAS_TASK_PD_C3,                                       \
-		     (CROS_EC_TASK(PD_C3, pd_task, 0,                     \
-				   CONFIG_TASK_PD_STACK_SIZE,             \
-				   EC_TASK_PD_C3_PRIO)), ())              \
-	IF_ENABLED(CONFIG_HAS_TASK_PD_INT_SHARED,			  \
-		   (CROS_EC_TASK(PD_INT_SHARED, pd_shared_alert_task,	  \
-				 PD_INT_SHARED_PORT_MASK,		  \
-				 CONFIG_TASK_PD_INT_STACK_SIZE,           \
-				 EC_TASK_PD_INT_SHARED_PRIO)))	          \
-	COND_CODE_1(HAS_TASK_PD_INT_C0,                                   \
-		     (CROS_EC_TASK(PD_INT_C0, pd_interrupt_handler_task, 0, \
-				   CONFIG_TASK_PD_INT_STACK_SIZE,         \
-				   EC_TASK_PD_INT_C0_PRIO)), ())          \
-	COND_CODE_1(HAS_TASK_PD_INT_C1,                                   \
-		     (CROS_EC_TASK(PD_INT_C1, pd_interrupt_handler_task, 1, \
-				   CONFIG_TASK_PD_INT_STACK_SIZE,         \
-				   EC_TASK_PD_INT_C1_PRIO)), ())          \
-	COND_CODE_1(HAS_TASK_PD_INT_C2,                                   \
-		     (CROS_EC_TASK(PD_INT_C2, pd_interrupt_handler_task, 2, \
-				   CONFIG_TASK_PD_INT_STACK_SIZE,         \
-				   EC_TASK_PD_INT_C2_PRIO)), ())          \
-	COND_CODE_1(HAS_TASK_PD_INT_C3,                                   \
-		     (CROS_EC_TASK(PD_INT_C3, pd_interrupt_handler_task, 3, \
-				   CONFIG_TASK_PD_INT_STACK_SIZE,         \
-				   EC_TASK_PD_INT_C3_PRIO)), ())
+#define CROS_EC_TASK_LIST                                                  \
+	COND_CODE_1(HAS_TASK_CHG_RAMP,                                     \
+		    (CROS_EC_TASK(CHG_RAMP, chg_ramp_task, 0,              \
+				  CONFIG_TASK_CHG_RAMP_STACK_SIZE,         \
+				  EC_TASK_CHG_RAMP_PRIO)),                 \
+		    ())                                                    \
+	COND_CODE_1(CONFIG_PLATFORM_EC_USB_CHARGER,                        \
+		    (CROS_EC_TASK(USB_CHG, usb_charger_task_shared, 0,     \
+				  CONFIG_TASK_USB_CHG_STACK_SIZE,          \
+				  EC_TASK_USB_CHG_PRIO)),                  \
+		    ())                                                    \
+	COND_CODE_1(HAS_TASK_DPS,                                          \
+		    (CROS_EC_TASK(DPS, dps_task, 0,                        \
+				  CONFIG_TASK_DPS_STACK_SIZE,              \
+				  EC_TASK_DPS_PRIO)),                      \
+		    ())                                                    \
+	COND_CODE_1(HAS_TASK_CHARGER,                                      \
+		    (CROS_EC_TASK(CHARGER, charger_task, 0,                \
+				  CONFIG_TASK_CHARGER_STACK_SIZE,          \
+				  EC_TASK_CHARGER_PRIO)),                  \
+		    ())                                                    \
+	COND_CODE_1(HAS_TASK_CHIPSET,                                      \
+		    (CROS_EC_TASK(CHIPSET, chipset_task, 0,                \
+				  CONFIG_TASK_CHIPSET_STACK_SIZE,          \
+				  EC_TASK_CHIPSET_PRIO)),                  \
+		    ())                                                    \
+	COND_CODE_1(HAS_TASK_MOTIONSENSE,                                  \
+		    (CROS_EC_TASK(MOTIONSENSE, motion_sense_task, 0,       \
+				  CONFIG_TASK_MOTIONSENSE_STACK_SIZE,      \
+				  EC_TASK_MOTIONSENSE_PRIO)),              \
+		    ())                                                    \
+	IF_ENABLED(HAS_TASK_USB_MUX,                                       \
+		   (CROS_EC_TASK(USB_MUX, usb_mux_task, 0,                 \
+				 CONFIG_TASK_USB_MUX_STACK_SIZE,           \
+				 EC_TASK_USB_MUX_PRIO)))                   \
+	COND_CODE_1(CONFIG_TASK_HOSTCMD_THREAD_DEDICATED,                  \
+		    (CROS_EC_TASK(HOSTCMD, host_command_task, 0,           \
+				  CONFIG_TASK_HOSTCMD_STACK_SIZE,          \
+				  EC_TASK_HOSTCMD_PRIO)),                  \
+		    ())                                                    \
+	COND_CODE_1(HAS_TASK_KEYPROTO,                                     \
+		    (CROS_EC_TASK(KEYPROTO, keyboard_protocol_task, 0,     \
+				  CONFIG_TASK_KEYPROTO_STACK_SIZE,         \
+				  EC_TASK_KEYPROTO_PRIO)),                 \
+		    ())                                                    \
+	COND_CODE_1(HAS_TASK_POWERBTN,                                     \
+		    (CROS_EC_TASK(POWERBTN, power_button_task, 0,          \
+				  CONFIG_TASK_POWERBTN_STACK_SIZE,         \
+				  EC_TASK_POWERBTN_PRIO)),                 \
+		    ())                                                    \
+	COND_CODE_1(HAS_TASK_KEYSCAN,                                      \
+		    (CROS_EC_TASK(KEYSCAN, keyboard_scan_task, 0,          \
+				  CONFIG_TASK_KEYSCAN_STACK_SIZE,          \
+				  EC_TASK_KEYSCAN_PRIO)),                  \
+		    ())                                                    \
+	COND_CODE_1(HAS_TASK_PD_C0,                                        \
+		    (CROS_EC_TASK(PD_C0, pd_task, 0,                       \
+				  CONFIG_TASK_PD_STACK_SIZE,               \
+				  EC_TASK_PD_C0_PRIO)),                    \
+		    ())                                                    \
+	COND_CODE_1(HAS_TASK_PD_C1,                                        \
+		    (CROS_EC_TASK(PD_C1, pd_task, 0,                       \
+				  CONFIG_TASK_PD_STACK_SIZE,               \
+				  EC_TASK_PD_C1_PRIO)),                    \
+		    ())                                                    \
+	COND_CODE_1(HAS_TASK_PD_C2,                                        \
+		    (CROS_EC_TASK(PD_C2, pd_task, 0,                       \
+				  CONFIG_TASK_PD_STACK_SIZE,               \
+				  EC_TASK_PD_C2_PRIO)),                    \
+		    ())                                                    \
+	COND_CODE_1(HAS_TASK_PD_C3,                                        \
+		    (CROS_EC_TASK(PD_C3, pd_task, 0,                       \
+				  CONFIG_TASK_PD_STACK_SIZE,               \
+				  EC_TASK_PD_C3_PRIO)),                    \
+		    ())                                                    \
+	IF_ENABLED(CONFIG_HAS_TASK_PD_INT_SHARED,                          \
+		   (CROS_EC_TASK(PD_INT_SHARED, pd_shared_alert_task,      \
+				 PD_INT_SHARED_PORT_MASK,                  \
+				 CONFIG_TASK_PD_INT_STACK_SIZE,            \
+				 EC_TASK_PD_INT_SHARED_PRIO)))             \
+	COND_CODE_1(HAS_TASK_PD_INT_C0,                                    \
+		    (CROS_EC_TASK(PD_INT_C0, pd_interrupt_handler_task, 0, \
+				  CONFIG_TASK_PD_INT_STACK_SIZE,           \
+				  EC_TASK_PD_INT_C0_PRIO)),                \
+		    ())                                                    \
+	COND_CODE_1(HAS_TASK_PD_INT_C1,                                    \
+		    (CROS_EC_TASK(PD_INT_C1, pd_interrupt_handler_task, 1, \
+				  CONFIG_TASK_PD_INT_STACK_SIZE,           \
+				  EC_TASK_PD_INT_C1_PRIO)),                \
+		    ())                                                    \
+	COND_CODE_1(HAS_TASK_PD_INT_C2,                                    \
+		    (CROS_EC_TASK(PD_INT_C2, pd_interrupt_handler_task, 2, \
+				  CONFIG_TASK_PD_INT_STACK_SIZE,           \
+				  EC_TASK_PD_INT_C2_PRIO)),                \
+		    ())                                                    \
+	COND_CODE_1(HAS_TASK_PD_INT_C3,                                    \
+		    (CROS_EC_TASK(PD_INT_C3, pd_interrupt_handler_task, 3, \
+				  CONFIG_TASK_PD_INT_STACK_SIZE,           \
+				  EC_TASK_PD_INT_C3_PRIO)),                \
+		    ())
 #elif defined(CONFIG_HAS_TEST_TASKS)
 #include "shimmed_test_tasks.h"
 /*
@@ -191,7 +188,7 @@ enum {
 	TASK_ID_IDLE = -1, /* We don't shim the idle task */
 	CROS_EC_TASK_LIST
 #ifdef TEST_BUILD
-	TASK_ID_TEST_RUNNER,
+		TASK_ID_TEST_RUNNER,
 #endif
 	TASK_ID_COUNT,
 	TASK_ID_INVALID = 0xff, /* Unable to find the task */
@@ -203,20 +200,17 @@ enum {
  * Additional task IDs for features that runs on non shimmed threads,
  * task_get_current() needs to be updated to identify these ones.
  */
-#define CROS_EC_EXTRA_TASKS(fn) \
+#define CROS_EC_EXTRA_TASKS(fn)                                         \
 	COND_CODE_1(CONFIG_TASK_HOSTCMD_THREAD_MAIN, (fn(HOSTCMD)), ()) \
 	fn(SYSWORKQ)
 
 #define EXTRA_TASK_INTERNAL_ID(name) EXTRA_TASK_##name,
 enum {
-	CROS_EC_EXTRA_TASKS(EXTRA_TASK_INTERNAL_ID)
-	EXTRA_TASK_COUNT,
+	CROS_EC_EXTRA_TASKS(EXTRA_TASK_INTERNAL_ID) EXTRA_TASK_COUNT,
 };
 
 #define EXTRA_TASK_ID(name) \
 	TASK_ID_##name = (TASK_ID_COUNT + EXTRA_TASK_##name),
-enum {
-	CROS_EC_EXTRA_TASKS(EXTRA_TASK_ID)
-};
+enum { CROS_EC_EXTRA_TASKS(EXTRA_TASK_ID) };
 
 #endif /* __CROS_EC_SHIMMED_TASK_ID_H */
diff --git a/zephyr/shim/include/shimmed_tasks.h b/zephyr/shim/include/shimmed_tasks.h
index d1fb6129d3..75be968f4a 100644
--- a/zephyr/shim/include/shimmed_tasks.h
+++ b/zephyr/shim/include/shimmed_tasks.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/shim/include/temp_sensor/temp_sensor.h b/zephyr/shim/include/temp_sensor/temp_sensor.h
index 2c6eabe485..9be18987eb 100644
--- a/zephyr/shim/include/temp_sensor/temp_sensor.h
+++ b/zephyr/shim/include/temp_sensor/temp_sensor.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,53 +8,134 @@
 
 #include <zephyr/devicetree.h>
 #include "include/temp_sensor.h"
+#include "charger/chg_rt9490.h"
 
 #ifdef CONFIG_PLATFORM_EC_TEMP_SENSOR
 
-#define ZSHIM_TEMP_SENSOR_ID(node_id) DT_STRING_UPPER_TOKEN(node_id, enum_name)
-#define TEMP_SENSOR_ID_WITH_COMMA(node_id) ZSHIM_TEMP_SENSOR_ID(node_id),
+#define PCT2075_COMPAT nxp_pct2075
+#define TMP112_COMPAT cros_ec_temp_sensor_tmp112
+#define SB_TSI_COMPAT amd_sb_tsi
+#define THERMISTOR_COMPAT cros_ec_temp_sensor_thermistor
+#define TEMP_SENSORS_COMPAT cros_ec_temp_sensors
+
+#define TEMP_SENSORS_NODEID DT_INST(0, TEMP_SENSORS_COMPAT)
+
+#define TEMP_RT9490_FN(node_id, fn) \
+	COND_CODE_1(DT_NODE_HAS_PROP(node_id, thermistor), (fn(node_id)), ())
+
+#define FOREACH_TEMP_SENSOR(fn)                                             \
+	DT_FOREACH_STATUS_OKAY(PCT2075_COMPAT, fn)                          \
+	DT_FOREACH_STATUS_OKAY(TMP112_COMPAT, fn)                           \
+	DT_FOREACH_STATUS_OKAY_VARGS(RT9490_CHG_COMPAT, TEMP_RT9490_FN, fn) \
+	DT_FOREACH_STATUS_OKAY(SB_TSI_COMPAT, fn)                           \
+	DT_FOREACH_STATUS_OKAY(THERMISTOR_COMPAT, fn)
 
 #define HAS_POWER_GOOD_PIN(node_id) DT_NODE_HAS_PROP(node_id, power_good_pin) ||
-#define ANY_INST_HAS_POWER_GOOD_PIN					 \
-	(DT_FOREACH_STATUS_OKAY(cros_ec_temp_sensor, HAS_POWER_GOOD_PIN) \
-	0)
+
+#define ANY_INST_HAS_POWER_GOOD_PIN \
+	(DT_FOREACH_CHILD(TEMP_SENSORS_NODEID, HAS_POWER_GOOD_PIN) 0)
+
+/*
+ * Get the enum temp_sensor_id value from a child node under
+ * "cros-ec,temp-sensors".
+ *
+ * Example devicetree fragment:
+ *
+ *     temp_charger_thermistor: charger-thermistor {
+ *         compatible = "cros-ec,temp-sensor-thermistor";
+ *         thermistor = <&thermistor_3V3_30K9_47K_4050B>;
+ *         adc = <&adc_temp_charger>;
+ *     };
+ *
+ *     named-temp-sensors {
+ *         compatible = "cros-ec,temp-sensors";
+ *         temp_charger: charger-thermistor {
+ *             temp_host_high = <100>;
+ *             temp_host_halt = <105>;
+ *             temp_host_release_high = <80>;
+ *             sensor = <&temp_charger_thermistor>;
+ *         };
+ *     };
+ *
+ * Example usage to get the temperature sensor ID:
+ *
+ *     TEMP_SENSOR_ID(DT_NODELABEL(temp_charger))
+ *
+ * @param node_id: node id of a child of "cros-ec,temp-sensors" node
+ */
+#define TEMP_SENSOR_ID(node_id) DT_CAT(TEMP_SENSOR_, node_id)
+
+/*
+ * Get the enum temp_sensor_id value from a hardware device node.
+ *
+ * Example devicetree fragment:
+ *
+ *     temp_charger_thermistor: charger-thermistor {
+ *         compatible = "cros-ec,temp-sensor-thermistor";
+ *         thermistor = <&thermistor_3V3_30K9_47K_4050B>;
+ *         adc = <&adc_temp_charger>;
+ *     };
+ *
+ *     named-temp-sensors {
+ *         compatible = "cros-ec,temp-sensors";
+ *         temp_charger: charger-thermistor {
+ *             temp_host_high = <100>;
+ *             temp_host_halt = <105>;
+ *             temp_host_release_high = <80>;
+ *             sensor = <&temp_charger_thermistor>;
+ *         };
+ *     };
+ *
+ * Example usage to get the temperature sensor ID:
+ *
+ *     TEMP_SENSOR_ID_BY_DEV(DT_NODELABEL(temp_charger_thermistor))
+ *
+ * which equals:
+ *
+ *     TEMP_SENSOR_ID(DT_NODELABEL(temp_charger))
+ *
+ * @param node_id: node id of a hardware device node
+ */
+#define TEMP_SENSOR_ID_BY_DEV(node_id) DT_CAT(TEMP_SENSOR_DEV, node_id)
+
+#define TEMP_SENSOR_ID_DEV(named_id)                          \
+	TEMP_SENSOR_ID_BY_DEV(DT_PHANDLE(named_id, sensor)) = \
+		TEMP_SENSOR_ID(named_id)
 
 enum temp_sensor_id {
-#if DT_NODE_EXISTS(DT_PATH(named_temp_sensors))
-	DT_FOREACH_CHILD(DT_PATH(named_temp_sensors),
-			 TEMP_SENSOR_ID_WITH_COMMA)
-#endif /* named_temp_sensors */
-	TEMP_SENSOR_COUNT
+	DT_FOREACH_CHILD_SEP(TEMP_SENSORS_NODEID, TEMP_SENSOR_ID, (, )),
+	DT_FOREACH_CHILD_SEP(TEMP_SENSORS_NODEID, TEMP_SENSOR_ID_DEV, (, )),
+	TEMP_SENSOR_COUNT,
 };
 
-#undef TEMP_SENSOR_ID_WITH_COMMA
-
 /* PCT2075 access array */
-#define ZSHIM_PCT2075_SENSOR_ID(node_id) DT_STRING_UPPER_TOKEN(node_id, \
-							       pct2075_name)
-#define PCT2075_SENSOR_ID_WITH_COMMA(node_id) ZSHIM_PCT2075_SENSOR_ID(node_id),
+/*
+ * Get the PCT2075 sensor ID from a hardware device node.
+ *
+ * @param node_id: node id of a hardware PCT2075 sensor node
+ */
+#define PCT2075_SENSOR_ID(node_id) DT_CAT(PCT2075_, node_id)
+#define PCT2075_SENSOR_ID_WITH_COMMA(node_id) PCT2075_SENSOR_ID(node_id),
 
 enum pct2075_sensor {
-#if DT_HAS_COMPAT_STATUS_OKAY(cros_ec_temp_sensor_pct2075)
-	DT_FOREACH_STATUS_OKAY(cros_ec_temp_sensor_pct2075,
-			       PCT2075_SENSOR_ID_WITH_COMMA)
-#endif
-	PCT2075_COUNT,
+	DT_FOREACH_STATUS_OKAY(PCT2075_COMPAT, PCT2075_SENSOR_ID_WITH_COMMA)
+		PCT2075_COUNT,
 };
 
 #undef PCT2075_SENSOR_ID_WITH_COMMA
 
 /* TMP112 access array */
-#define ZSHIM_TMP112_SENSOR_ID(node_id) DT_STRING_UPPER_TOKEN(node_id, \
-							      tmp112_name)
-#define TMP112_SENSOR_ID_WITH_COMMA(node_id) ZSHIM_TMP112_SENSOR_ID(node_id),
+/*
+ * Get the TMP112 sensor ID from a hardware device node.
+ *
+ * @param node_id: node id of a hardware TMP112 sensor node
+ */
+#define TMP112_SENSOR_ID(node_id) DT_CAT(TMP112_, node_id)
+#define TMP112_SENSOR_ID_WITH_COMMA(node_id) TMP112_SENSOR_ID(node_id),
 
 enum tmp112_sensor {
-#if DT_HAS_COMPAT_STATUS_OKAY(cros_ec_temp_sensor_tmp112)
-	DT_FOREACH_STATUS_OKAY(cros_ec_temp_sensor_tmp112,
-			       TMP112_SENSOR_ID_WITH_COMMA)
-#endif
-	TMP112_COUNT,
+	DT_FOREACH_STATUS_OKAY(TMP112_COMPAT, TMP112_SENSOR_ID_WITH_COMMA)
+		TMP112_COUNT,
 };
 
 #undef TMP112_SENSOR_ID_WITH_COMMA
@@ -62,11 +143,11 @@ enum tmp112_sensor {
 struct zephyr_temp_sensor {
 	/* Read sensor value in K into temp_ptr; return non-zero if error. */
 	int (*read)(const struct temp_sensor_t *sensor, int *temp_ptr);
-	struct thermistor_info *thermistor;
+	const struct thermistor_info *thermistor;
 #if ANY_INST_HAS_POWER_GOOD_PIN
 	const struct device *power_good_dev;
 	gpio_pin_t power_good_pin;
-#endif
+#endif /* ANY_INST_HAS_POWER_GOOD_PIN */
 };
 
 #endif /* CONFIG_PLATFORM_EC_TEMP_SENSOR */
diff --git a/zephyr/shim/include/usbc/amd_fp6_usb_mux.h b/zephyr/shim/include/usbc/amd_fp6_usb_mux.h
new file mode 100644
index 0000000000..a474a4eee4
--- /dev/null
+++ b/zephyr/shim/include/usbc/amd_fp6_usb_mux.h
@@ -0,0 +1,21 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __ZEPHYR_SHIM_AMD_FP6_USB_MUX_H
+#define __ZEPHYR_SHIM_AMD_FP6_USB_MUX_H
+
+#include "usb_mux.h"
+
+#define AMD_FP6_USB_MUX_COMPAT amd_usbc_mux_amd_fp6
+
+#define USB_MUX_CONFIG_AMD_FP6(mux_id)                         \
+	{                                                      \
+		USB_MUX_COMMON_FIELDS(mux_id),                 \
+			.driver = &amd_fp6_usb_mux_driver,     \
+			.i2c_port = I2C_PORT_BY_DEV(mux_id),   \
+			.i2c_addr_flags = DT_REG_ADDR(mux_id), \
+	}
+
+#endif /* __ZEPHYR_SHIM_AMD_FP6_USB_MUX_H */
diff --git a/zephyr/shim/include/usbc/anx7447_usb_mux.h b/zephyr/shim/include/usbc/anx7447_usb_mux.h
new file mode 100644
index 0000000000..874958c04c
--- /dev/null
+++ b/zephyr/shim/include/usbc/anx7447_usb_mux.h
@@ -0,0 +1,22 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __ZEPHYR_SHIM_ANX7447_USB_MUX_H
+#define __ZEPHYR_SHIM_ANX7447_USB_MUX_H
+
+#include "tcpm/anx7447_public.h"
+
+#define ANX7447_USB_MUX_COMPAT analogix_usbc_mux_anx7447
+
+#define USB_MUX_CONFIG_ANX7447(mux_id)                                      \
+	{                                                                   \
+		USB_MUX_COMMON_FIELDS(mux_id),                              \
+			.driver = &anx7447_usb_mux_driver,                  \
+			.hpd_update = COND_CODE_1(                          \
+				DT_PROP(mux_id, hpd_update_enable),         \
+				(&anx7447_tcpc_update_hpd_status), (NULL)), \
+	}
+
+#endif /* __ZEPHYR_SHIM_ANX7447_USB_MUX_H */
diff --git a/zephyr/shim/include/usbc/anx7483_usb_mux.h b/zephyr/shim/include/usbc/anx7483_usb_mux.h
index 606928b016..5e56837e3a 100644
--- a/zephyr/shim/include/usbc/anx7483_usb_mux.h
+++ b/zephyr/shim/include/usbc/anx7483_usb_mux.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,15 +8,14 @@
 
 #include "driver/retimer/anx7483_public.h"
 
-#define ANX7483_USB_MUX_COMPAT	analogix_anx7483
+#define ANX7483_USB_MUX_COMPAT analogix_anx7483
 
-#define USB_MUX_CONFIG_ANX7483(mux_id, port_id, idx)			\
-	{								\
-		USB_MUX_COMMON_FIELDS(mux_id, port_id, idx),		\
-		.driver = &anx7483_usb_retimer_driver,			\
-		.i2c_port = I2C_PORT(DT_PHANDLE(mux_id, port)),		\
-		.i2c_addr_flags =					\
-			DT_STRING_UPPER_TOKEN(mux_id, i2c_addr_flags),	\
+#define USB_MUX_CONFIG_ANX7483(mux_id)                         \
+	{                                                      \
+		USB_MUX_COMMON_FIELDS(mux_id),                 \
+			.driver = &anx7483_usb_retimer_driver, \
+			.i2c_port = I2C_PORT_BY_DEV(mux_id),   \
+			.i2c_addr_flags = DT_REG_ADDR(mux_id), \
 	}
 
 #endif /* __ZEPHYR_SHIM_ANX7483_USB_MUX_H */
diff --git a/zephyr/shim/include/usbc/bb_retimer_usb_mux.h b/zephyr/shim/include/usbc/bb_retimer_usb_mux.h
index 611c52e081..64e1e2693d 100644
--- a/zephyr/shim/include/usbc/bb_retimer_usb_mux.h
+++ b/zephyr/shim/include/usbc/bb_retimer_usb_mux.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,23 +10,100 @@
 
 #define BB_RETIMER_USB_MUX_COMPAT intel_jhl8040r
 
-#define USB_MUX_CONFIG_BB_RETIMER(mux_id, port_id, idx)            \
-	{                                                          \
-		USB_MUX_COMMON_FIELDS(mux_id, port_id, idx),       \
-		.driver = &bb_usb_retimer,                         \
-		.hpd_update = bb_retimer_hpd_update,               \
-		.i2c_port = I2C_PORT(DT_PHANDLE(mux_id, port)),    \
-		.i2c_addr_flags = DT_PROP(mux_id, i2c_addr_flags), \
+#define USB_MUX_CONFIG_BB_RETIMER(mux_id)                      \
+	{                                                      \
+		USB_MUX_COMMON_FIELDS(mux_id),                 \
+			.driver = &bb_usb_retimer,             \
+			.hpd_update = bb_retimer_hpd_update,   \
+			.i2c_port = I2C_PORT_BY_DEV(mux_id),   \
+			.i2c_addr_flags = DT_REG_ADDR(mux_id), \
 	}
 
-#define BB_RETIMER_CONTROLS_CONFIG(mux_id, port_id, idx)              \
-	{                                                             \
-		.retimer_rst_gpio =                                   \
-			GPIO_SIGNAL(DT_PHANDLE(mux_id, reset_pin)),   \
-		.usb_ls_en_gpio = COND_CODE_1(                        \
-			DT_NODE_HAS_PROP(mux_id, ls_en_pin),          \
-			(GPIO_SIGNAL(DT_PHANDLE(mux_id, ls_en_pin))), \
-			(GPIO_UNIMPLEMENTED)),                        \
+/**
+ * @brief Get reset gpio for @p mux_id retimer
+ *
+ * @param mux_id BB retimer DTS node
+ */
+#define BB_RETIMER_RESET_GPIO(mux_id) GPIO_SIGNAL(DT_PHANDLE(mux_id, reset_pin))
+
+/**
+ * @brief Get LS_EN gpio for @p mux_id retimer
+ *
+ * @param mux_id BB retimer DTS node
+ */
+#define BB_RETIMER_LS_EN_GPIO(mux_id)                             \
+	COND_CODE_1(DT_NODE_HAS_PROP(mux_id, ls_en_pin),          \
+		    (GPIO_SIGNAL(DT_PHANDLE(mux_id, ls_en_pin))), \
+		    (GPIO_UNIMPLEMENTED))
+
+#define BB_RETIMER_CONTROLS_CONFIG(mux_id)                         \
+	{                                                          \
+		.retimer_rst_gpio = BB_RETIMER_RESET_GPIO(mux_id), \
+		.usb_ls_en_gpio = BB_RETIMER_LS_EN_GPIO(mux_id),   \
 	}
 
+/**
+ * @brief Set entry in bb_controls array
+ *
+ * @param mux_id BB retimer node ID
+ */
+#define USB_MUX_BB_RETIMER_CONTROL_ARRAY(mux_id) \
+	[USB_MUX_PORT(mux_id)] = BB_RETIMER_CONTROLS_CONFIG(mux_id),
+
+/**
+ * @brief Call USB_MUX_BB_RETIMER_CONTROL_ARRAY for every BB retimer in DTS
+ */
+#define USB_MUX_BB_RETIMERS_CONTROLS_ARRAY                \
+	DT_FOREACH_STATUS_OKAY(BB_RETIMER_USB_MUX_COMPAT, \
+			       USB_MUX_BB_RETIMER_CONTROL_ARRAY)
+
+/**
+ * @brief Check if BB retimers @p id_1 and @p id_2 has matching configuration
+ *        Configuration match if reset and ls_en pins are the same for muxes
+ *        which are on the same USB-C port.
+ *
+ * @param id_1 First BB retimer DTS node
+ * @param id_2 Second BB retimer DTS node
+ */
+#define BB_RETIMER_CHECK_PAIR(id_1, id_2)                                      \
+	BUILD_ASSERT(USB_MUX_PORT(id_1) != USB_MUX_PORT(id_2) ||               \
+			     (BB_RETIMER_RESET_GPIO(id_1) ==                   \
+				      BB_RETIMER_RESET_GPIO(id_2) &&           \
+			      BB_RETIMER_LS_EN_GPIO(id_1) ==                   \
+				      BB_RETIMER_LS_EN_GPIO(id_2)),            \
+		     "BB retimers " #id_1 " and " #id_2 " have different pin " \
+		     "configuration and same USB-C port")
+
+/**
+ * @brief Check if BB retimers with @p inst instance number has matching
+ *        configuration with muxes of higher instance number on @p bb_list list.
+ *        Configuration match if reset and ls_en pins are the same for muxes
+ *        which are on the same USB-C port.
+ *
+ * @param inst Instance number of BB retimer mux
+ * @param bb_list List of BB retimers in instance number order
+ */
+#define BB_RETIMER_CHECK_INSTANCE_WITH_LIST(inst, bb_list)           \
+	FOR_EACH_FIXED_ARG(BB_RETIMER_CHECK_PAIR, (;),               \
+			   DT_INST(inst, BB_RETIMER_USB_MUX_COMPAT), \
+			   GET_ARGS_LESS_N(inst, __DEBRACKET bb_list))
+
+/**
+ * @brief Check if BB retimers on the @p bb_list list have matching
+ *        configurations (i.e. reset and ls_en pins are the same for muxes
+ *        which are on the same USB-C port). This check is required, because
+ *        USB_MUX_ENABLE_ALTERNATE() doesn't update bb_control[] array, so all
+ *        BB retimers needs to use the same GPIO pins.
+ *
+ * @param bb_list List of BB retimers in instance number order
+ */
+#define BB_RETIMER_CHECK_SAME_CONTROLS(bb_list)                     \
+	LISTIFY(DT_NUM_INST_STATUS_OKAY(BB_RETIMER_USB_MUX_COMPAT), \
+		BB_RETIMER_CHECK_INSTANCE_WITH_LIST, (;), bb_list);
+
+/** List of all BB retimers in DTS in instance number order */
+#define BB_RETIMER_INSTANCES_LIST                                             \
+	(LISTIFY(DT_NUM_INST_STATUS_OKAY(BB_RETIMER_USB_MUX_COMPAT), DT_INST, \
+		 (, ), BB_RETIMER_USB_MUX_COMPAT))
+
 #endif /* __ZEPHYR_SHIM_BB_RETIMER_USB_MUX_H */
diff --git a/zephyr/shim/include/usbc/bc12_pi3usb9201.h b/zephyr/shim/include/usbc/bc12_pi3usb9201.h
index 59b84cd868..701090133f 100644
--- a/zephyr/shim/include/usbc/bc12_pi3usb9201.h
+++ b/zephyr/shim/include/usbc/bc12_pi3usb9201.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,4 +7,7 @@
 
 #define PI3USB9201_COMPAT pericom_pi3usb9201
 
-#define BC12_CHIP_PI3USB9201(id) { .drv = &pi3usb9201_drv, },
+#define BC12_CHIP_PI3USB9201(id)        \
+	{                               \
+		.drv = &pi3usb9201_drv, \
+	},
diff --git a/zephyr/shim/include/usbc/bc12_rt1718s.h b/zephyr/shim/include/usbc/bc12_rt1718s.h
new file mode 100644
index 0000000000..e34f21c9e0
--- /dev/null
+++ b/zephyr/shim/include/usbc/bc12_rt1718s.h
@@ -0,0 +1,13 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "tcpm/rt1718s_public.h"
+
+#define RT1718S_BC12_COMPAT richtek_rt1718s_bc12
+
+#define BC12_CHIP_RT1718S(id)             \
+	{                                 \
+		.drv = &rt1718s_bc12_drv, \
+	},
diff --git a/zephyr/shim/include/usbc/bc12_rt1739.h b/zephyr/shim/include/usbc/bc12_rt1739.h
index 3347d7d717..8d7427b271 100644
--- a/zephyr/shim/include/usbc/bc12_rt1739.h
+++ b/zephyr/shim/include/usbc/bc12_rt1739.h
@@ -1,10 +1,13 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "driver/ppc/rt1739.h"
 
-#define RT1739_BC12_COMPAT richtek_rt1739_bc12
+#define RT1739_BC12_COMPAT richtek_rt1739
 
-#define BC12_CHIP_RT1739(id) { .drv = &rt1739_bc12_drv, },
+#define BC12_CHIP_RT1739(id)             \
+	{                                \
+		.drv = &rt1739_bc12_drv, \
+	},
diff --git a/zephyr/shim/include/usbc/bc12_rt9490.h b/zephyr/shim/include/usbc/bc12_rt9490.h
index f9bc82f292..a9371ddeea 100644
--- a/zephyr/shim/include/usbc/bc12_rt9490.h
+++ b/zephyr/shim/include/usbc/bc12_rt9490.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,4 +7,7 @@
 
 #define RT9490_BC12_COMPAT richtek_rt9490_bc12
 
-#define BC12_CHIP_RT9490(id) { .drv = &rt9490_bc12_drv, },
+#define BC12_CHIP_RT9490(id)             \
+	{                                \
+		.drv = &rt9490_bc12_drv, \
+	},
diff --git a/zephyr/shim/include/usbc/it5205_usb_mux.h b/zephyr/shim/include/usbc/it5205_usb_mux.h
index 58412e0bd3..983248f3e2 100644
--- a/zephyr/shim/include/usbc/it5205_usb_mux.h
+++ b/zephyr/shim/include/usbc/it5205_usb_mux.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,15 +8,14 @@
 
 #include "usb_mux/it5205_public.h"
 
-#define IT5205_USB_MUX_COMPAT	ite_it5205
+#define IT5205_USB_MUX_COMPAT ite_it5205
 
-#define USB_MUX_CONFIG_IT5205(mux_id, port_id, idx)			\
-	{								\
-		USB_MUX_COMMON_FIELDS(mux_id, port_id, idx),		\
-		.driver = &it5205_usb_mux_driver,			\
-		.i2c_port = I2C_PORT(DT_PHANDLE(mux_id, port)),		\
-		.i2c_addr_flags =					\
-			DT_STRING_UPPER_TOKEN(mux_id, i2c_addr_flags),	\
+#define USB_MUX_CONFIG_IT5205(mux_id)                          \
+	{                                                      \
+		USB_MUX_COMMON_FIELDS(mux_id),                 \
+			.driver = &it5205_usb_mux_driver,      \
+			.i2c_port = I2C_PORT_BY_DEV(mux_id),   \
+			.i2c_addr_flags = DT_REG_ADDR(mux_id), \
 	}
 
 #endif /* __ZEPHYR_SHIM_IT5205_USB_MUX_H */
diff --git a/zephyr/shim/include/usbc/ppc.h b/zephyr/shim/include/usbc/ppc.h
index 94aee49f36..28e518a3ef 100644
--- a/zephyr/shim/include/usbc/ppc.h
+++ b/zephyr/shim/include/usbc/ppc.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,35 +9,30 @@
 #include <zephyr/device.h>
 #include <zephyr/devicetree.h>
 #include "usbc/ppc_rt1739.h"
+#include "usbc/ppc_nx20p348x.h"
 #include "usbc/ppc_sn5s330.h"
 #include "usbc/ppc_syv682x.h"
 #include "usbc/utils.h"
 #include "usbc_ppc.h"
 
-#define PPC_ID(id) DT_CAT(PPC_, id)
-#define PPC_ID_WITH_COMMA(id) PPC_ID(id),
-#define PPC_ALT_FOR(alt_id) USBC_PORT(DT_PHANDLE(alt_id, alternate_for))
-
-#define PPC_ALT_ENUM(id)                                 \
-	COND_CODE_1(DT_NODE_HAS_PROP(id, alternate_for), \
-		    (PPC_ID_WITH_COMMA(id)), ())
-
-enum ppc_chips_alt_id {
-	DT_FOREACH_STATUS_OKAY(RT1739_PPC_COMPAT, PPC_ALT_ENUM)
-	DT_FOREACH_STATUS_OKAY(SN5S330_COMPAT, PPC_ALT_ENUM)
-	DT_FOREACH_STATUS_OKAY(SYV682X_COMPAT, PPC_ALT_ENUM)
-	PPC_CHIP_ALT_COUNT
-};
-
 extern struct ppc_config_t ppc_chips_alt[];
 
-#define PPC_ENABLE_ALTERNATE(nodelabel)                                  \
-	do {                                                             \
-		BUILD_ASSERT(DT_NODE_EXISTS(DT_NODELABEL(nodelabel)),    \
-			     "PPC alternate node does not exist");       \
-		memcpy(&ppc_chips[PPC_ALT_FOR(DT_NODELABEL(nodelabel))], \
-		       &ppc_chips_alt[PPC_ID(DT_NODELABEL(nodelabel))],  \
-		       sizeof(struct ppc_config_t));                     \
+#define ALT_PPC_CHIP_CHK(usbc_id, usb_port_num)                              \
+	COND_CODE_1(DT_REG_HAS_IDX(usbc_id, usb_port_num),                   \
+		    (COND_CODE_1(DT_NODE_HAS_PROP(usbc_id, ppc_alt), (|| 1), \
+				 (|| 0))),                                   \
+		    (|| 0))
+
+#define PPC_ENABLE_ALTERNATE(usb_port_num)                                            \
+	do {                                                                          \
+		BUILD_ASSERT(                                                         \
+			(0 DT_FOREACH_STATUS_OKAY_VARGS(named_usbc_port,              \
+							ALT_PPC_CHIP_CHK,             \
+							usb_port_num)),               \
+			"Selected USB node does not exist or does not specify a PPC " \
+			"alternate chip");                                            \
+		memcpy(&ppc_chips[usb_port_num], &ppc_chips_alt[usb_port_num],        \
+		       sizeof(struct ppc_config_t));                                  \
 	} while (0)
 
 #endif /* ZEPHYR_CHROME_USBC_PPC_H */
diff --git a/zephyr/shim/include/usbc/ppc_aoz1380.h b/zephyr/shim/include/usbc/ppc_aoz1380.h
new file mode 100644
index 0000000000..1ff20b802f
--- /dev/null
+++ b/zephyr/shim/include/usbc/ppc_aoz1380.h
@@ -0,0 +1,11 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ppc/aoz1380_public.h"
+
+#define AOZ1380_COMPAT aoz_aoz1380
+
+/* Note: This chip has no i2c interface */
+#define PPC_CHIP_AOZ1380(id) { .drv = &aoz1380_drv },
diff --git a/zephyr/shim/include/usbc/ppc_nx20p348x.h b/zephyr/shim/include/usbc/ppc_nx20p348x.h
new file mode 100644
index 0000000000..2d36ab09f6
--- /dev/null
+++ b/zephyr/shim/include/usbc/ppc_nx20p348x.h
@@ -0,0 +1,13 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ppc/nx20p348x_public.h"
+
+#define NX20P348X_COMPAT nxp_nx20p348x
+
+#define PPC_CHIP_NX20P348X(id)               \
+	{ .i2c_port = I2C_PORT_BY_DEV(id),   \
+	  .i2c_addr_flags = DT_REG_ADDR(id), \
+	  .drv = &nx20p348x_drv },
diff --git a/zephyr/shim/include/usbc/ppc_rt1739.h b/zephyr/shim/include/usbc/ppc_rt1739.h
index 19e169a436..5b71b9ff9c 100644
--- a/zephyr/shim/include/usbc/ppc_rt1739.h
+++ b/zephyr/shim/include/usbc/ppc_rt1739.h
@@ -1,18 +1,18 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "driver/ppc/rt1739.h"
 
-#define RT1739_PPC_COMPAT richtek_rt1739_ppc
+#define RT1739_PPC_COMPAT richtek_rt1739
 
-#define PPC_CHIP_RT1739(id)                                                  \
-	{                                                                    \
-		.i2c_port = I2C_PORT(DT_PHANDLE(id, port)),                  \
-		.i2c_addr_flags = DT_STRING_UPPER_TOKEN(id, i2c_addr_flags), \
-		.drv = &rt1739_ppc_drv,                                      \
-		.frs_en = COND_CODE_1(DT_NODE_HAS_PROP(id, irq),             \
-				      (GPIO_SIGNAL(DT_PHANDLE(id, irq))),    \
-				      (0)),                                  \
+#define PPC_CHIP_RT1739(id)                                               \
+	{                                                                 \
+		.i2c_port = I2C_PORT_BY_DEV(id),                          \
+		.i2c_addr_flags = DT_REG_ADDR(id),                        \
+		.drv = &rt1739_ppc_drv,                                   \
+		.frs_en = COND_CODE_1(DT_NODE_HAS_PROP(id, irq),          \
+				      (GPIO_SIGNAL(DT_PHANDLE(id, irq))), \
+				      (0)),                               \
 	},
diff --git a/zephyr/shim/include/usbc/ppc_sn5s330.h b/zephyr/shim/include/usbc/ppc_sn5s330.h
index 1c48777107..ecbcb53deb 100644
--- a/zephyr/shim/include/usbc/ppc_sn5s330.h
+++ b/zephyr/shim/include/usbc/ppc_sn5s330.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,9 +7,7 @@
 
 #define SN5S330_COMPAT ti_sn5s330
 
-#define PPC_CHIP_SN5S330(id)                                                 \
-	{			                                             \
-		.i2c_port = I2C_PORT(DT_PHANDLE(id, port)),                  \
-		.i2c_addr_flags = DT_STRING_UPPER_TOKEN(id, i2c_addr_flags), \
-		.drv = &sn5s330_drv                                          \
-	},
+#define PPC_CHIP_SN5S330(id)                 \
+	{ .i2c_port = I2C_PORT_BY_DEV(id),   \
+	  .i2c_addr_flags = DT_REG_ADDR(id), \
+	  .drv = &sn5s330_drv },
diff --git a/zephyr/shim/include/usbc/ppc_syv682x.h b/zephyr/shim/include/usbc/ppc_syv682x.h
index 1c2691f684..33813a5256 100644
--- a/zephyr/shim/include/usbc/ppc_syv682x.h
+++ b/zephyr/shim/include/usbc/ppc_syv682x.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,12 +7,12 @@
 
 #define SYV682X_COMPAT silergy_syv682x
 
-#define PPC_CHIP_SYV682X(id)                                                \
-	{                                                                   \
-		.i2c_port = I2C_PORT(DT_PHANDLE(id, port)),                 \
-		.i2c_addr_flags = DT_STRING_UPPER_TOKEN(id, i2c_addr_flags),\
-		.drv = &syv682x_drv,                                        \
-		.frs_en = COND_CODE_1(DT_NODE_HAS_PROP(id, frs_en_gpio),    \
-				(GPIO_SIGNAL(DT_PHANDLE(id, frs_en_gpio))), \
-				(0)),                                       \
+#define PPC_CHIP_SYV682X(id)                                              \
+	{                                                                 \
+		.i2c_port = I2C_PORT_BY_DEV(id),                          \
+		.i2c_addr_flags = DT_REG_ADDR(id),                        \
+		.drv = &syv682x_drv,                                      \
+		.frs_en = COND_CODE_1(                                    \
+			DT_NODE_HAS_PROP(id, frs_en_gpio),                \
+			(GPIO_SIGNAL(DT_PHANDLE(id, frs_en_gpio))), (0)), \
 	},
diff --git a/zephyr/shim/include/usbc/ps8743_usb_mux.h b/zephyr/shim/include/usbc/ps8743_usb_mux.h
new file mode 100644
index 0000000000..75ce778bac
--- /dev/null
+++ b/zephyr/shim/include/usbc/ps8743_usb_mux.h
@@ -0,0 +1,21 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __ZEPHYR_SHIM_PS8743_USB_MUX_H
+#define __ZEPHYR_SHIM_PS8743_USB_MUX_H
+
+#include "usb_mux/ps8743_public.h"
+
+#define PS8743_USB_MUX_COMPAT parade_ps8743
+
+#define USB_MUX_CONFIG_PS8743(mux_id)                          \
+	{                                                      \
+		USB_MUX_COMMON_FIELDS(mux_id),                 \
+			.driver = &ps8743_usb_mux_driver,      \
+			.i2c_port = I2C_PORT_BY_DEV(mux_id),   \
+			.i2c_addr_flags = DT_REG_ADDR(mux_id), \
+	}
+
+#endif /* __ZEPHYR_SHIM_PS8743_USB_MUX_H */
diff --git a/zephyr/shim/include/usbc/ps8818_usb_mux.h b/zephyr/shim/include/usbc/ps8818_usb_mux.h
new file mode 100644
index 0000000000..c45e69aee3
--- /dev/null
+++ b/zephyr/shim/include/usbc/ps8818_usb_mux.h
@@ -0,0 +1,21 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __ZEPHYR_SHIM_PS8818_USB_MUX_H
+#define __ZEPHYR_SHIM_PS8818_USB_MUX_H
+
+#include "driver/retimer/ps8818_public.h"
+
+#define PS8818_USB_MUX_COMPAT parade_ps8818
+
+#define USB_MUX_CONFIG_PS8818(mux_id)                          \
+	{                                                      \
+		USB_MUX_COMMON_FIELDS(mux_id),                 \
+			.driver = &ps8818_usb_retimer_driver,  \
+			.i2c_port = I2C_PORT_BY_DEV(mux_id),   \
+			.i2c_addr_flags = DT_REG_ADDR(mux_id), \
+	}
+
+#endif /* __ZEPHYR_SHIM_PS8818_USB_MUX_H */
diff --git a/zephyr/shim/include/usbc/tcpc_anx7447.h b/zephyr/shim/include/usbc/tcpc_anx7447.h
new file mode 100644
index 0000000000..7a59296e74
--- /dev/null
+++ b/zephyr/shim/include/usbc/tcpc_anx7447.h
@@ -0,0 +1,20 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/devicetree.h>
+#include "tcpm/anx7447_public.h"
+
+#define ANX7447_TCPC_COMPAT anologix_anx7447_tcpc
+
+#define TCPC_CONFIG_ANX7447(id) \
+	{                                              \
+		.bus_type = EC_BUS_TYPE_I2C,           \
+		.i2c_info = {                          \
+			.port = I2C_PORT_BY_DEV(id),   \
+			.addr_flags = DT_REG_ADDR(id), \
+		},                                     \
+		.drv = &anx7447_tcpm_drv,              \
+		.flags = DT_PROP(id, tcpc_flags),      \
+	},
diff --git a/zephyr/shim/include/usbc/tcpc_ccgxxf.h b/zephyr/shim/include/usbc/tcpc_ccgxxf.h
index 566fed03d6..0c02cf6846 100644
--- a/zephyr/shim/include/usbc/tcpc_ccgxxf.h
+++ b/zephyr/shim/include/usbc/tcpc_ccgxxf.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,14 +8,13 @@
 
 #define CCGXXF_TCPC_COMPAT cypress_ccgxxf
 
-#define TCPC_CONFIG_CCGXXF(id)                                                \
-	{                                                                     \
-		.bus_type = EC_BUS_TYPE_I2C,                                  \
-		.i2c_info = {                                                 \
-			.port = I2C_PORT(DT_PHANDLE(id, port)),               \
-			.addr_flags = DT_STRING_UPPER_TOKEN(                  \
-					id, i2c_addr_flags),                  \
-		},                                                            \
-		.drv = &ccgxxf_tcpm_drv,                                      \
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,                             \
+#define TCPC_CONFIG_CCGXXF(id) \
+	{                                              \
+		.bus_type = EC_BUS_TYPE_I2C,           \
+		.i2c_info = {                          \
+			.port = I2C_PORT_BY_DEV(id),   \
+			.addr_flags = DT_REG_ADDR(id), \
+		},                                     \
+		.drv = &ccgxxf_tcpm_drv,               \
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,      \
 	},
diff --git a/zephyr/shim/include/usbc/tcpc_fusb302.h b/zephyr/shim/include/usbc/tcpc_fusb302.h
index fefb54af7d..a2e512d938 100644
--- a/zephyr/shim/include/usbc/tcpc_fusb302.h
+++ b/zephyr/shim/include/usbc/tcpc_fusb302.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,13 +8,12 @@
 
 #define FUSB302_TCPC_COMPAT fairchild_fusb302
 
-#define TCPC_CONFIG_FUSB302(id)                                               \
-	{                                                                     \
-		.bus_type = EC_BUS_TYPE_I2C,                                  \
-		.i2c_info = {                                                 \
-			.port = I2C_PORT(DT_PHANDLE(id, port)),               \
-			.addr_flags = DT_STRING_UPPER_TOKEN(                  \
-					id, i2c_addr_flags),                  \
-		},                                                            \
-		.drv = &fusb302_tcpm_drv,                                      \
+#define TCPC_CONFIG_FUSB302(id) \
+	{                                              \
+		.bus_type = EC_BUS_TYPE_I2C,           \
+		.i2c_info = {                          \
+			.port = I2C_PORT_BY_DEV(id),   \
+			.addr_flags = DT_REG_ADDR(id), \
+		},                                     \
+		.drv = &fusb302_tcpm_drv,              \
 	},
diff --git a/zephyr/shim/include/usbc/tcpc_generic_emul.h b/zephyr/shim/include/usbc/tcpc_generic_emul.h
new file mode 100644
index 0000000000..7dc46c51ba
--- /dev/null
+++ b/zephyr/shim/include/usbc/tcpc_generic_emul.h
@@ -0,0 +1,20 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/devicetree.h>
+
+#include "driver/tcpm/tcpci.h"
+
+#define TCPCI_EMUL_COMPAT cros_tcpci_generic_emul
+
+#define TCPC_CONFIG_TCPCI_EMUL(id) \
+	{                                              \
+		.bus_type = EC_BUS_TYPE_I2C,           \
+		.i2c_info = {                          \
+			.port = I2C_PORT_BY_DEV(id),   \
+			.addr_flags = DT_REG_ADDR(id), \
+		},                                     \
+		.drv = &tcpci_tcpm_drv,                \
+	},
diff --git a/zephyr/shim/include/usbc/tcpc_it8xxx2.h b/zephyr/shim/include/usbc/tcpc_it8xxx2.h
index be275441d8..c619656667 100644
--- a/zephyr/shim/include/usbc/tcpc_it8xxx2.h
+++ b/zephyr/shim/include/usbc/tcpc_it8xxx2.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,11 +6,11 @@
 #include <zephyr/devicetree.h>
 #include "driver/tcpm/it8xxx2_pd_public.h"
 
-#define IT8XXX2_TCPC_COMPAT ite_it8xxx2_tcpc
+#define IT8XXX2_TCPC_COMPAT ite_it8xxx2_usbpd
 
-#define TCPC_CONFIG_IT8XXX2(id)                                               \
-	{                                                                     \
-		.bus_type = EC_BUS_TYPE_EMBEDDED,                             \
-		.drv = &it8xxx2_tcpm_drv,                                     \
-		.flags = 0,                                                   \
+#define TCPC_CONFIG_IT8XXX2(id)                   \
+	{                                         \
+		.bus_type = EC_BUS_TYPE_EMBEDDED, \
+		.drv = &it8xxx2_tcpm_drv,         \
+		.flags = 0,                       \
 	},
diff --git a/zephyr/shim/include/usbc/tcpc_nct38xx.h b/zephyr/shim/include/usbc/tcpc_nct38xx.h
index 87b222c794..87ba3379c8 100644
--- a/zephyr/shim/include/usbc/tcpc_nct38xx.h
+++ b/zephyr/shim/include/usbc/tcpc_nct38xx.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,16 +11,15 @@
 
 #define NCT38XX_TCPC_COMPAT nuvoton_nct38xx
 
-#define TCPC_CONFIG_NCT38XX(id)                                               \
-	{                                                                     \
-		.bus_type = EC_BUS_TYPE_I2C,                                  \
-		.i2c_info = {                                                 \
-			.port = I2C_PORT(DT_PHANDLE(id, port)),               \
-			.addr_flags = DT_STRING_UPPER_TOKEN(                  \
-					id, i2c_addr_flags),                  \
-		},                                                            \
-		.drv = &nct38xx_tcpm_drv,                                     \
-		.flags = DT_PROP(id, tcpc_flags),                             \
+#define TCPC_CONFIG_NCT38XX(id) \
+	{                                              \
+		.bus_type = EC_BUS_TYPE_I2C,           \
+		.i2c_info = {                          \
+			.port = I2C_PORT_BY_DEV(id),   \
+			.addr_flags = DT_REG_ADDR(id), \
+		},                                     \
+		.drv = &nct38xx_tcpm_drv,              \
+		.flags = DT_PROP(id, tcpc_flags),      \
 	},
 
 /**
diff --git a/zephyr/shim/include/usbc/tcpc_ps8xxx.h b/zephyr/shim/include/usbc/tcpc_ps8xxx.h
index d47f6cc9df..1a457af09b 100644
--- a/zephyr/shim/include/usbc/tcpc_ps8xxx.h
+++ b/zephyr/shim/include/usbc/tcpc_ps8xxx.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,14 +8,13 @@
 
 #define PS8XXX_COMPAT parade_ps8xxx
 
-#define TCPC_CONFIG_PS8XXX(id)                                                \
-	{                                                                     \
-		.bus_type = EC_BUS_TYPE_I2C,                                  \
-		.i2c_info = {                                                 \
-			.port = I2C_PORT(DT_PHANDLE(id, port)),               \
-			.addr_flags = DT_STRING_UPPER_TOKEN(                  \
-					id, i2c_addr_flags),                  \
-		},                                                            \
-		.drv = &ps8xxx_tcpm_drv,                                      \
-		.flags = DT_PROP(id, tcpc_flags),                             \
+#define TCPC_CONFIG_PS8XXX(id) \
+	{                                              \
+		.bus_type = EC_BUS_TYPE_I2C,           \
+		.i2c_info = {                          \
+			.port = I2C_PORT_BY_DEV(id),   \
+			.addr_flags = DT_REG_ADDR(id), \
+		},                                     \
+		.drv = &ps8xxx_tcpm_drv,               \
+		.flags = DT_PROP(id, tcpc_flags),      \
 	},
diff --git a/zephyr/shim/include/usbc/tcpc_ps8xxx_emul.h b/zephyr/shim/include/usbc/tcpc_ps8xxx_emul.h
new file mode 100644
index 0000000000..fbd2e4bfd1
--- /dev/null
+++ b/zephyr/shim/include/usbc/tcpc_ps8xxx_emul.h
@@ -0,0 +1,19 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/devicetree.h>
+#include "driver/tcpm/ps8xxx_public.h"
+
+#define PS8XXX_EMUL_COMPAT cros_ps8xxx_emul
+
+#define TCPC_CONFIG_PS8XXX_EMUL(id) \
+	{                                              \
+		.bus_type = EC_BUS_TYPE_I2C,           \
+		.i2c_info = {                          \
+			.port = I2C_PORT_BY_DEV(id),   \
+			.addr_flags = DT_REG_ADDR(id), \
+		},                                     \
+		.drv = &ps8xxx_tcpm_drv,               \
+	},
diff --git a/zephyr/shim/include/usbc/tcpc_rt1718s.h b/zephyr/shim/include/usbc/tcpc_rt1718s.h
new file mode 100644
index 0000000000..794fb99480
--- /dev/null
+++ b/zephyr/shim/include/usbc/tcpc_rt1718s.h
@@ -0,0 +1,20 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/devicetree.h>
+#include "tcpm/rt1718s_public.h"
+
+#define RT1718S_TCPC_COMPAT richtek_rt1718s_tcpc
+
+#define TCPC_CONFIG_RT1718S(id) \
+	{                                              \
+		.bus_type = EC_BUS_TYPE_I2C,           \
+		.i2c_info = {                          \
+			.port = I2C_PORT_BY_DEV(id),   \
+			.addr_flags = DT_REG_ADDR(id), \
+		},                                     \
+		.drv = &rt1718s_tcpm_drv,              \
+		.flags = DT_PROP(id, tcpc_flags),      \
+	},
diff --git a/zephyr/shim/include/usbc/tcpci.h b/zephyr/shim/include/usbc/tcpci.h
index 35f706d09b..67138dbe99 100644
--- a/zephyr/shim/include/usbc/tcpci.h
+++ b/zephyr/shim/include/usbc/tcpci.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,12 +9,12 @@
 
 #define TCPCI_COMPAT cros_ec_tcpci
 
-#define TCPC_CONFIG_TCPCI(id)                                                 \
-	{                                                                     \
-		.bus_type = EC_BUS_TYPE_I2C,                                  \
-		.i2c_info = {                                                 \
-			.port = I2C_PORT(DT_PHANDLE(id, port)),               \
-			.addr_flags = DT_PROP(id, i2c_addr_flags),            \
-		},                                                            \
-		.drv = &tcpci_tcpm_drv,                                       \
+#define TCPC_CONFIG_TCPCI(id) \
+	{                                              \
+		.bus_type = EC_BUS_TYPE_I2C,           \
+		.i2c_info = {                          \
+			.port = I2C_PORT_BY_DEV(id),   \
+			.addr_flags = DT_REG_ADDR(id), \
+		},                                     \
+		.drv = &tcpci_tcpm_drv,                \
 	},
diff --git a/zephyr/shim/include/usbc/tcpci_usb_mux.h b/zephyr/shim/include/usbc/tcpci_usb_mux.h
index 9fa29c7c85..1a5dd38241 100644
--- a/zephyr/shim/include/usbc/tcpci_usb_mux.h
+++ b/zephyr/shim/include/usbc/tcpci_usb_mux.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,41 +10,36 @@
 #include "tcpm/ps8xxx_public.h"
 #include "tcpm/tcpci.h"
 
-#define TCPCI_TCPM_USB_MUX_COMPAT	cros_ec_usbc_mux_tcpci
-#define PS8XXX_USB_MUX_COMPAT		parade_usbc_mux_ps8xxx
+#define TCPCI_TCPM_USB_MUX_COMPAT cros_ec_usbc_mux_tcpci
+#define PS8XXX_USB_MUX_COMPAT parade_usbc_mux_ps8xxx
 
 /**
  * Add I2C configuration and USB_MUX_FLAG_NOT_TCPC to enforce it when
  * mux_read()/mux_write() functions are used.
  */
-#define USB_MUX_CONFIG_TCPCI_TCPM_WITH_I2C(mux_id, port_id, idx)	\
-	{								\
-		USB_MUX_COMMON_FIELDS_WITH_FLAGS(mux_id, port_id, idx,	\
-						 USB_MUX_FLAG_NOT_TCPC,	\
-						 USB_MUX_FLAG_NOT_TCPC),\
-		.driver = &tcpci_tcpm_usb_mux_driver,			\
-		.hpd_update = USB_MUX_CALLBACK_OR_NULL(mux_id,		\
-						       hpd_update),	\
-		.i2c_port = I2C_PORT(DT_PHANDLE(mux_id, port)),		\
-		.i2c_addr_flags = DT_PROP(mux_id, i2c_addr_flags),	\
+#define USB_MUX_CONFIG_TCPCI_TCPM_WITH_I2C(mux_id)                             \
+	{                                                                      \
+		USB_MUX_COMMON_FIELDS_WITH_FLAGS(                              \
+			mux_id, USB_MUX_FLAG_NOT_TCPC, USB_MUX_FLAG_NOT_TCPC), \
+			.driver = &tcpci_tcpm_usb_mux_driver,                  \
+			.hpd_update =                                          \
+				USB_MUX_CALLBACK_OR_NULL(mux_id, hpd_update),  \
+			.i2c_port = I2C_PORT_BY_DEV(mux_id),                   \
+			.i2c_addr_flags = DT_REG_ADDR(mux_id),                 \
 	}
 
 /** Use I2C configuration from TCPC */
-#define USB_MUX_CONFIG_TCPCI_TCPM_WO_I2C(mux_id, port_id, idx)		\
-	{								\
-		USB_MUX_COMMON_FIELDS(mux_id, port_id, idx),		\
-		.driver = &tcpci_tcpm_usb_mux_driver,			\
-		.hpd_update = USB_MUX_CALLBACK_OR_NULL(mux_id,		\
-						       hpd_update),	\
+#define USB_MUX_CONFIG_TCPCI_TCPM_WO_I2C(mux_id)                              \
+	{                                                                     \
+		USB_MUX_COMMON_FIELDS(mux_id),                                \
+			.driver = &tcpci_tcpm_usb_mux_driver,                 \
+			.hpd_update =                                         \
+				USB_MUX_CALLBACK_OR_NULL(mux_id, hpd_update), \
 	}
 
-/** This macro will fail if only port or i2c_addr_flags property is present */
-#define USB_MUX_CONFIG_TCPCI_TCPM(mux_id, port_id, idx)			\
-	COND_CODE_1(UTIL_OR(DT_NODE_HAS_PROP(mux_id, port),		\
-			    DT_NODE_HAS_PROP(mux_id, i2c_addr_flags)),	\
-		    (USB_MUX_CONFIG_TCPCI_TCPM_WITH_I2C(mux_id, port_id,\
-							idx)),		\
-		    (USB_MUX_CONFIG_TCPCI_TCPM_WO_I2C(mux_id, port_id,	\
-						      idx)))
+#define USB_MUX_CONFIG_TCPCI_TCPM(mux_id)                         \
+	COND_CODE_1(DT_NODE_HAS_PROP(mux_id, reg),                \
+		    (USB_MUX_CONFIG_TCPCI_TCPM_WITH_I2C(mux_id)), \
+		    (USB_MUX_CONFIG_TCPCI_TCPM_WO_I2C(mux_id)))
 
 #endif /* __ZEPHYR_SHIM_TCPCI_USB_MUX_H */
diff --git a/zephyr/shim/include/usbc/tusb1064_usb_mux.h b/zephyr/shim/include/usbc/tusb1064_usb_mux.h
index 159f42c500..55dc8d4645 100644
--- a/zephyr/shim/include/usbc/tusb1064_usb_mux.h
+++ b/zephyr/shim/include/usbc/tusb1064_usb_mux.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,35 +8,32 @@
 
 #include "driver/usb_mux/tusb1064.h"
 
-#define TUSB1064_USB_MUX_COMPAT	ti_tusb1064
+#define TUSB1064_USB_MUX_COMPAT ti_tusb1064
 
 #if defined(CONFIG_USB_MUX_TUSB1044)
-#define USB_MUX_CONFIG_TUSB1064(mux_id, port_id, idx)			\
-	{								\
-		USB_MUX_COMMON_FIELDS(mux_id, port_id, idx),		\
-		.driver = &tusb1064_usb_mux_driver,			\
-		.i2c_port = I2C_PORT(DT_PHANDLE(mux_id, port)),		\
-		.i2c_addr_flags =					\
-			DT_STRING_UPPER_TOKEN(mux_id, i2c_addr_flags),	\
-		.hpd_update = &tusb1044_hpd_update,			\
+#define USB_MUX_CONFIG_TUSB1064(mux_id)                        \
+	{                                                      \
+		USB_MUX_COMMON_FIELDS(mux_id),                 \
+			.driver = &tusb1064_usb_mux_driver,    \
+			.i2c_port = I2C_PORT_BY_DEV(mux_id),   \
+			.i2c_addr_flags = DT_REG_ADDR(mux_id), \
+			.hpd_update = &tusb1044_hpd_update,    \
 	}
 #elif defined(CONFIG_USB_MUX_TUSB546)
-#define USB_MUX_CONFIG_TUSB1064(mux_id, port_id, idx)			\
-	{								\
-		USB_MUX_COMMON_FIELDS(mux_id, port_id, idx),		\
-		.driver = &tusb1064_usb_mux_driver,			\
-		.i2c_port = I2C_PORT(DT_PHANDLE(mux_id, port)),		\
-		.i2c_addr_flags =					\
-			DT_STRING_UPPER_TOKEN(mux_id, i2c_addr_flags),	\
+#define USB_MUX_CONFIG_TUSB1064(mux_id)                        \
+	{                                                      \
+		USB_MUX_COMMON_FIELDS(mux_id),                 \
+			.driver = &tusb1064_usb_mux_driver,    \
+			.i2c_port = I2C_PORT_BY_DEV(mux_id),   \
+			.i2c_addr_flags = DT_REG_ADDR(mux_id), \
 	}
 #else
-#define USB_MUX_CONFIG_TUSB1064(mux_id, port_id, idx)			\
-	{								\
-		USB_MUX_COMMON_FIELDS(mux_id, port_id, idx),		\
-		.driver = &tusb1064_usb_mux_driver,			\
-		.i2c_port = I2C_PORT(DT_PHANDLE(mux_id, port)),		\
-		.i2c_addr_flags =					\
-			DT_STRING_UPPER_TOKEN(mux_id, i2c_addr_flags),	\
+#define USB_MUX_CONFIG_TUSB1064(mux_id)                        \
+	{                                                      \
+		USB_MUX_COMMON_FIELDS(mux_id),                 \
+			.driver = &tusb1064_usb_mux_driver,    \
+			.i2c_port = I2C_PORT_BY_DEV(mux_id),   \
+			.i2c_addr_flags = DT_REG_ADDR(mux_id), \
 	}
 #endif /* defined(CONFIG_USB_MUX_TUSB1044) */
 
diff --git a/zephyr/shim/include/usbc/usb_muxes.h b/zephyr/shim/include/usbc/usb_muxes.h
index 9422d4008d..d161b72b08 100644
--- a/zephyr/shim/include/usbc/usb_muxes.h
+++ b/zephyr/shim/include/usbc/usb_muxes.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,108 +9,158 @@
 #include <zephyr/devicetree.h>
 #include <zephyr/sys/util_macro.h>
 #include "usb_mux.h"
+#include "usbc/amd_fp6_usb_mux.h"
+#include "usbc/anx7447_usb_mux.h"
 #include "usbc/anx7483_usb_mux.h"
 #include "usbc/bb_retimer_usb_mux.h"
 #include "usbc/it5205_usb_mux.h"
+#include "usbc/ps8743_usb_mux.h"
+#include "usbc/ps8818_usb_mux.h"
 #include "usbc/tcpci_usb_mux.h"
 #include "usbc/tusb1064_usb_mux.h"
+#include "usbc/utils.h"
 #include "usbc/virtual_usb_mux.h"
 
 /**
  * @brief List of USB mux drivers compatibles and their configurations. Each
  *        element of list has to have (compatible, config) format.
  */
-#define USB_MUX_DRIVERS						\
-	(ANX7483_USB_MUX_COMPAT, USB_MUX_CONFIG_ANX7483),	\
-	(BB_RETIMER_USB_MUX_COMPAT, USB_MUX_CONFIG_BB_RETIMER),	\
-	(IT5205_USB_MUX_COMPAT, USB_MUX_CONFIG_IT5205),		\
-	(PS8XXX_USB_MUX_COMPAT, USB_MUX_CONFIG_TCPCI_TCPM),	\
-	(TCPCI_TCPM_USB_MUX_COMPAT, USB_MUX_CONFIG_TCPCI_TCPM),	\
-	(TUSB1064_USB_MUX_COMPAT, USB_MUX_CONFIG_TUSB1064),	\
-	(VIRTUAL_USB_MUX_COMPAT, USB_MUX_CONFIG_VIRTUAL)
+#define USB_MUX_DRIVERS                                                 \
+	(AMD_FP6_USB_MUX_COMPAT, USB_MUX_CONFIG_AMD_FP6),               \
+		(ANX7447_USB_MUX_COMPAT, USB_MUX_CONFIG_ANX7447),       \
+		(ANX7483_USB_MUX_COMPAT, USB_MUX_CONFIG_ANX7483),       \
+		(BB_RETIMER_USB_MUX_COMPAT, USB_MUX_CONFIG_BB_RETIMER), \
+		(IT5205_USB_MUX_COMPAT, USB_MUX_CONFIG_IT5205),         \
+		(PS8743_USB_MUX_COMPAT, USB_MUX_CONFIG_PS8743),         \
+		(PS8818_USB_MUX_COMPAT, USB_MUX_CONFIG_PS8818),         \
+		(PS8XXX_USB_MUX_COMPAT, USB_MUX_CONFIG_TCPCI_TCPM),     \
+		(TCPCI_TCPM_USB_MUX_COMPAT, USB_MUX_CONFIG_TCPCI_TCPM), \
+		(TUSB1064_USB_MUX_COMPAT, USB_MUX_CONFIG_TUSB1064),     \
+		(VIRTUAL_USB_MUX_COMPAT, USB_MUX_CONFIG_VIRTUAL)
 
 /**
  * @brief Get compatible from @p driver
  *
  * @param driver USB mux driver description in format (compatible, config)
  */
-#define USB_MUX_DRIVER_GET_COMPAT(driver)	GET_ARG_N(1, __DEBRACKET driver)
+#define USB_MUX_DRIVER_GET_COMPAT(driver) GET_ARG_N(1, __DEBRACKET driver)
 
 /**
  * @brief Get configuration from @p driver
  *
  * @param driver USB mux driver description in format (compatible, config)
  */
-#define USB_MUX_DRIVER_GET_CONFIG(driver)	GET_ARG_N(2, __DEBRACKET driver)
+#define USB_MUX_DRIVER_GET_CONFIG(driver) GET_ARG_N(2, __DEBRACKET driver)
 
 /**
- * @brief USB mux port number based on parent node in DTS
+ * @brief Name of USB mux chain structure for given port and place in chain.
+ *        Note, that root of chain is not referred by this name, but
+ *        usb_muxes[@p port_id].
  *
- * @param port_id USBC node ID
+ * @param idx Place in chain
+ * @param port_id USBC port id
  */
-#define USB_MUX_PORT(port_id)		DT_REG_ADDR(port_id)
+#define USB_MUX_CHAIN_STRUCT_NAME(idx, port_id) \
+	DT_CAT4(USB_MUX_chain_port_, port_id, _mux_, idx)
 
 /**
- * @brief Name of USB mux structure if node is not EMPTY. Note, that root of
- *        chain is not referred by this name, but usb_muxes[USB_MUX_PORT(id)].
+ * @brief Declaration of USB mux chain structure for @p idx mux in @p port_id
+ *        USB-C port's chain
+ *
+ * @param port_id USBC port ID (number)
+ * @param idx Place in chain
+ */
+#define USB_MUX_CHAIN_STRUCT_DECLARE(port_id, idx) \
+	MAYBE_CONST struct usb_mux_chain USB_MUX_CHAIN_STRUCT_NAME(idx, port_id)
+
+/**
+ * @brief Name of USB mux structure if node @p mux_id is not EMPTY.
  *
  * @param mux_id USB mux node ID
  */
-#define USB_MUX_STRUCT_NAME(mux_id)					\
+#define USB_MUX_STRUCT_NAME(mux_id) \
 	COND_CODE_0(IS_EMPTY(mux_id), (DT_CAT(USB_MUX_NODE_, mux_id)), (EMPTY))
 
 /**
  * @brief USB muxes in chain should be constant only if configuration
  *        cannot change in runtime
  */
-#define MAYBE_CONST COND_CODE_1(CONFIG_PLATFORM_EC_USB_MUX_RUNTIME_CONFIG, \
-				(), (const))
+#define MAYBE_CONST \
+	COND_CODE_1(CONFIG_PLATFORM_EC_USB_MUX_RUNTIME_CONFIG, (), (const))
 
 /**
  * @brief Declaration of USB mux structure
  *
  * @param mux_id USB mux node ID
  */
-#define USB_MUX_STRUCT_DECLARE(mux_id)					\
+#define USB_MUX_STRUCT_DECLARE(mux_id) \
 	MAYBE_CONST struct usb_mux USB_MUX_STRUCT_NAME(mux_id)
 
 /**
+ * @brief Declaration of USB mux board_init function
+ *
+ * @param mux_id USB mux node ID
+ */
+#define USB_MUX_CB_BOARD_INIT_DECLARE(mux_id) \
+	int DT_STRING_TOKEN(mux_id, board_init)(const struct usb_mux *);
+
+/**
+ * @brief Declaration of USB mux board_set function
+ *
+ * @param mux_id USB mux node ID
+ */
+#define USB_MUX_CB_BOARD_SET_DECLARE(mux_id)                           \
+	int DT_STRING_TOKEN(mux_id, board_set)(const struct usb_mux *, \
+					       mux_state_t);
+
+/**
  * @brief Get pointer by referencing @p name or NULL if @p name is EMPTY
  *
  * @param name Identifier to reference
  */
-#define USB_MUX_POINTER_OR_NULL(name)					\
+#define USB_MUX_POINTER_OR_NULL(name) \
 	COND_CODE_0(IS_EMPTY(name), (&name), (NULL))
 
 /**
  * @brief Get node id of @p idx USB mux in chain
  *
+ * @param chain_id USB mux chain node ID
  * @param idx Position of USB mux in chain
- * @param port_id USBC node ID
  */
-#define USB_MUX_GET_CHAIN_N(idx, port_id)				\
-	DT_PHANDLE_BY_IDX(port_id, usb_muxes, idx)
+#define USB_MUX_GET_CHAIN_N(chain_id, idx) \
+	DT_PHANDLE_BY_IDX(chain_id, usb_muxes, idx)
 
 /**
- * @brief Get node id of next USB mux in chain or EMPTY if it is last mux
+ * @brief Get next USB mux chain structure name or EMPTY if it is last mux
  *
- * @param port_id USBC node ID
+ * @param chain_id USB mux chain node ID
  * @param idx Position of USB mux in chain
  */
-#define USB_MUX_NEXT(port_id, idx)					\
-	GET_ARG_N(2, GET_ARGS_LESS_N(idx,				\
-			LISTIFY(DT_PROP_LEN(port_id, usb_muxes),	\
-				USB_MUX_GET_CHAIN_N, (,), port_id)),	\
+#define USB_MUX_CHAIN_NEXT_NAME(chain_id, idx)                              \
+	GET_ARG_N(2,                                                        \
+		  GET_ARGS_LESS_N(idx,                                      \
+				  LISTIFY(DT_PROP_LEN(chain_id, usb_muxes), \
+					  USB_MUX_CHAIN_STRUCT_NAME, (, ),  \
+					  USBC_PORT(chain_id))),            \
 		  EMPTY)
 
 /**
  * @brief Get pointer to next USB mux in chain or NULL if it is last mux
  *
- * @param port_id USBC node ID
+ * @param chain_id USB mux chain node ID
  * @param idx Position of USB mux in chain
  */
-#define USB_MUX_NEXT_POINTER(port_id, idx)				\
-	USB_MUX_POINTER_OR_NULL(USB_MUX_STRUCT_NAME(USB_MUX_NEXT(port_id, idx)))
+#define USB_MUX_CHAIN_NEXT_POINTER(chain_id, idx) \
+	USB_MUX_POINTER_OR_NULL(USB_MUX_CHAIN_NEXT_NAME(chain_id, idx))
+
+/**
+ * @brief Get pointer to USB mux that is @p idx in chain @p chain_id
+ *
+ * @param chain_id USB mux chain node ID
+ * @param idx Position of USB mux in chain
+ */
+#define USB_MUX_POINTER(chain_id, idx) \
+	&USB_MUX_STRUCT_NAME(USB_MUX_GET_CHAIN_N(chain_id, idx))
 
 /**
  * @brief Generate pointer to function from @p cb_name property or NULL
@@ -119,217 +169,335 @@
  * @param mux_id USB mux node ID
  * @param cb_name Name of property with callback function
  */
-#define USB_MUX_CALLBACK_OR_NULL(mux_id, cb_name)			\
+#define USB_MUX_CALLBACK_OR_NULL(mux_id, cb_name) \
 	USB_MUX_POINTER_OR_NULL(DT_STRING_TOKEN_OR(mux_id, cb_name, EMPTY))
 
 /**
  * @brief Set struct usb_mux fields common for all USB muxes and alter flags
  *
  * @param mux_id USB mux node ID
- * @param port_id USBC node ID
- * @param idx Position of USB mux in chain
  * @param flags_mask Mask for bits that should be igonred in flags property
  * @param flags_val Value that should be used instead for masked bits
  */
-#define USB_MUX_COMMON_FIELDS_WITH_FLAGS(mux_id, port_id, idx,		\
-					 flags_mask, flags_val)		\
-	.usb_port = USB_MUX_PORT(port_id),				\
-	.next_mux = USB_MUX_NEXT_POINTER(port_id, idx),			\
-	.board_init = USB_MUX_CALLBACK_OR_NULL(mux_id, board_init),	\
-	.board_set = USB_MUX_CALLBACK_OR_NULL(mux_id, board_set),	\
+#define USB_MUX_COMMON_FIELDS_WITH_FLAGS(mux_id, flags_mask, flags_val) \
+	.usb_port = USB_MUX_PORT(mux_id),                               \
+	.board_init = USB_MUX_CALLBACK_OR_NULL(mux_id, board_init),     \
+	.board_set = USB_MUX_CALLBACK_OR_NULL(mux_id, board_set),       \
 	.flags = (DT_PROP(mux_id, flags) & ~(flags_mask)) | (flags_val)
 
 /**
  * @brief Set struct usb_mux fields common for all USB muxes
  *
  * @param mux_id USB mux node ID
- * @param port_id USBC node ID
- * @param idx Position of USB mux in chain
  */
-#define USB_MUX_COMMON_FIELDS(mux_id, port_id, idx)			\
-	USB_MUX_COMMON_FIELDS_WITH_FLAGS(mux_id, port_id, idx, 0, 0)
+#define USB_MUX_COMMON_FIELDS(mux_id) \
+	USB_MUX_COMMON_FIELDS_WITH_FLAGS(mux_id, 0, 0)
 
 /**
- * @brief Expands to 1 if @p mux_id has @p compat compatible. It is required
- *        to makes sure that @p compat is expanded before DT_NODE_HAS_COMPAT
+ * @brief Declare USB mux structure
  *
  * @param mux_id USB mux node ID
- * @param compat USB mux driver compatible
+ * @param conf Driver configuration function
  */
-#define USB_MUX_IS_COMPATIBLE(mux_id, compat)	\
-	DT_NODE_HAS_COMPAT(mux_id, compat)
+#define USB_MUX_DECLARE(mux_id, conf) extern USB_MUX_STRUCT_DECLARE(mux_id);
 
 /**
- * @brief Expands to @p driver config if @p mux_id is compatible with @p driver
+ * @brief Define USB mux structure using driver USB_MUX_CONFIG_* macro
  *
- * @param driver USB mux driver description in format (compatible, config)
  * @param mux_id USB mux node ID
+ * @param conf Driver configuration function
  */
-#define USB_MUX_DRIVER_CONFIG_IF_COMPAT(driver, mux_id)			\
-	COND_CODE_1(USB_MUX_IS_COMPATIBLE(				\
-			mux_id, USB_MUX_DRIVER_GET_COMPAT(driver)),	\
-		   (USB_MUX_DRIVER_GET_CONFIG(driver)), ())
+#define USB_MUX_DEFINE(mux_id, conf) \
+	USB_MUX_STRUCT_DECLARE(mux_id) = conf(mux_id);
 
 /**
- * @brief Find driver from USB_MUX_DRIVERS that is compatible with @p mux_id
+ * @brief Call @p cb_op if @p mux_id has @p cb_prop property
  *
  * @param mux_id USB mux node ID
+ * @param cb_prop The callback property name
+ * @param cb_op Operation to perform on USB muxes
  */
-#define USB_MUX_FIND_DRIVER_CONFIG(mux_id)				\
-	FOR_EACH_FIXED_ARG(USB_MUX_DRIVER_CONFIG_IF_COMPAT, (), mux_id,	\
-			   USB_MUX_DRIVERS)
+#define USB_MUX_CB_DECLARE_IF_EXIST(mux_id, cb_prop, cb_op) \
+	COND_CODE_1(DT_NODE_HAS_PROP(mux_id, cb_prop), (cb_op(mux_id)), ())
 
 /**
- * @brief Get driver configuration macro for @p mux_id and call @p op
+ * @brief Declare USB mux board_set function @p mux_id has board_set property
  *
  * @param mux_id USB mux node ID
- * @param port_id USBC node ID
- * @param idx Position of USB mux in chain
- * @param op Operation to perform on USB muxes
+ * @param conf Driver configuration function
  */
-#define USB_MUX_CALL_OP(mux_id, port_id, idx, op)			\
-	op(mux_id, port_id, idx, USB_MUX_FIND_DRIVER_CONFIG(mux_id))
+#define USB_MUX_CB_BOARD_SET_DECLARE_IF_EXISTS(mux_id, conf) \
+	USB_MUX_CB_DECLARE_IF_EXIST(mux_id, board_set,       \
+				    USB_MUX_CB_BOARD_SET_DECLARE)
 
 /**
- * @brief Get USB mux node ID and call USB_MUX_CALL_OP
+ * @brief Declare USB mux board_init function @p mux_id has board_init property
  *
- * @param port_id USBC node ID
- * @param idx Position of USB mux in chain
- * @param op Operation to perform on USB muxes
+ * @param mux_id USB mux node ID
+ * @param conf Driver configuration function
  */
-#define USB_MUX_DO(port_id, idx, op)					\
-	USB_MUX_CALL_OP(USB_MUX_GET_CHAIN_N(idx, port_id), port_id, idx, op)
+#define USB_MUX_CB_BOARD_INIT_DECLARE_IF_EXISTS(mux_id, conf) \
+	USB_MUX_CB_DECLARE_IF_EXIST(mux_id, board_init,       \
+				    USB_MUX_CB_BOARD_INIT_DECLARE)
 
 /**
- * @brief Declare USB mux structure
+ * @brief Call @p op operation for each node that is compatible with @p driver
  *
- * @param mux_id USB mux node ID
- * @param port_id USBC node ID
- * @param idx Position of USB mux in chain
- * @param conf Driver configuration function
+ * @param driver USB mux driver description in format (compatible, config)
+ * @param op Operation to perform on each USB mux. Should accept mux node ID and
+ *           driver config as arguments.
  */
-#define USB_MUX_DECLARE(mux_id, port_id, idx, conf)			\
-	extern USB_MUX_STRUCT_DECLARE(mux_id);
+#define USB_MUX_DRIVER_CONFIG(driver, op)                                   \
+	DT_FOREACH_STATUS_OKAY_VARGS(USB_MUX_DRIVER_GET_COMPAT(driver), op, \
+				     USB_MUX_DRIVER_GET_CONFIG(driver))
 
 /**
- * @brief Define USB mux structure using driver USB_MUX_CONFIG_* macro
+ * @brief Call @p op operation for each USB mux node that is compatible with
+ *        any driver from the USB_MUX_DRIVERS list.
+ *        DT_FOREACH_STATUS_OKAY_VARGS() macro can not be used in @p op
  *
- * @param mux_id USB mux node ID
- * @param port_id USBC node ID
- * @param idx Position of USB mux in chain
- * @param conf Driver configuration function
+ * @param op Operation to perform on each USB mux. Should accept mux node ID and
+ *           driver config as arguments.
  */
-#define USB_MUX_DEFINE(mux_id, port_id, idx, conf)			\
-	USB_MUX_STRUCT_DECLARE(mux_id) = conf(mux_id, port_id, idx);
+#define USB_MUX_FOREACH_MUX_DT_VARGS(op) \
+	FOR_EACH_FIXED_ARG(USB_MUX_DRIVER_CONFIG, (), op, USB_MUX_DRIVERS)
 
 /**
- * @brief Define entry of usb_muxes array using driver USB_MUX_CONFIG_* macro
+ * @brief Convert @p mux_id and @p conf pair into USB_MUX_LIST entry
  *
  * @param mux_id USB mux node ID
- * @param port_id USBC node ID
- * @param idx Position of USB mux in chain
  * @param conf Driver configuration function
  */
-#define USB_MUX_ARRAY(mux_id, port_id, idx, conf)			\
-	[USB_MUX_PORT(port_id)] = conf(mux_id, port_id, idx),
+#define USB_MUX_TO_LIST(mux_id, conf) , (mux_id, conf)
+
+/**
+ * @brief List of all USB muxes with config matched by compatible. List is in
+ *        format (mux1_id, conf1) , (mux2_id, conf2) ...
+ */
+#define USB_MUX_LIST \
+	LIST_DROP_EMPTY(USB_MUX_FOREACH_MUX_DT_VARGS(USB_MUX_TO_LIST))
+
+/**
+ * @brief Call @p op with @p args arguments
+ *
+ * @param op Operation to perform on USB mux. Should accept mux node ID and
+ *           driver config as arguments.
+ * @param args Arguments for @p op. Should be in format (mux_id, conf).
+ */
+#define USB_MUX_CALL_OP(args, op) op args
 
 /**
- * @brief Call @p op with first mux in chain
+ * @brief Call @p op operation for each USB mux node from USB_MUX_LIST. This is
+ *        like USB_MUX_FOREACH_MUX_DT_VARGS(), except
+ *        DT_FOREACH_STATUS_OKAY_VARGS() macro can be used in @p op
  *
- * @param port_id USBC node ID
- * @param op Operation to perform on USB mux first in chain. Needs to accept
- *           USB mux node ID, USBC port node ID, position in chain, and driver
- *           config as arguments.
+ * @param op Operation to perform on each USB mux. Should accept mux node ID and
+ *           driver config as arguments.
  */
-#define USB_MUX_FIRST(port_id, op)					\
-	USB_MUX_DO(port_id, 0, op)
+#define USB_MUX_FOREACH_MUX(op)                                              \
+	COND_CODE_0(                                                         \
+		IS_EMPTY(USB_MUX_LIST),                                      \
+		(FOR_EACH_FIXED_ARG(USB_MUX_CALL_OP, (), op, USB_MUX_LIST)), \
+		(EMPTY))
 
 /**
- * @brief Call USB_MUX_DO if @p idx is not 0 (is not first mux in chain)
+ * @brief Initialise chain structure for @p idx mux
  *
- * @param port_id USBC node ID
+ * @param chain_id Chain DTS node ID
+ * @param idx USB mux index
+ */
+#define USB_MUX_CHAIN_STRUCT_INIT(chain_id, idx)                   \
+	{                                                          \
+		.mux = USB_MUX_POINTER(chain_id, idx),             \
+		.next = USB_MUX_CHAIN_NEXT_POINTER(chain_id, idx), \
+	}
+
+/**
+ * @brief Helper macro to set chain structure value for @p idx mux
+ *
+ * @param chain_id Chain DTS node ID
+ * @param idx USB mux index
+ */
+#define USB_MUX_CHAIN_STRUCT_SET(chain_id, idx) \
+	(struct usb_mux_chain) USB_MUX_CHAIN_STRUCT_INIT(chain_id, idx)
+
+/**
+ * @brief Declaration of USB mux chain extern structure for @p idx mux in
+ *        @p chain_id chain
+ *
+ * @param chain_id USB mux chain node ID
+ * @param idx Place in chain
+ */
+#define USB_MUX_CHAIN_STRUCT_DECLARE_EXTERN_OP(chain_id, idx) \
+	extern USB_MUX_CHAIN_STRUCT_DECLARE(USBC_PORT(chain_id), idx);
+
+/**
+ * @brief Declaration of USB mux chain structure for @p idx mux in @p chain_id
+ *        chain
+ *
+ * @param chain_id USB mux chain node ID
+ * @param idx Place in chain
+ */
+#define USB_MUX_CHAIN_STRUCT_DECLARE_OP(chain_id, idx) \
+	USB_MUX_CHAIN_STRUCT_DECLARE(USBC_PORT(chain_id), idx);
+
+/**
+ * @brief Definition of USB mux chain structure for @p idx mux in @p chain_id
+ *        chain
+ *
+ * @param chain_id USB mux chain node ID
+ * @param idx Place in chain
+ */
+#define USB_MUX_CHAIN_STRUCT_DEFINE_OP(chain_id, idx)            \
+	USB_MUX_CHAIN_STRUCT_DECLARE(USBC_PORT(chain_id), idx) = \
+		USB_MUX_CHAIN_STRUCT_INIT(chain_id, idx);
+
+/**
+ * @brief Call @p op if @p idx is not 0 (is not the root mux of chain)
+ *
+ * @param chain_id Chain DTS node ID
  * @param unused2 This argument is expected by DT_FOREACH_PROP_ELEM_VARGS
  * @param idx Position of USB mux in chain
  * @param op Operation to perform on USB muxes
  */
-#define USB_MUX_DO_SKIP_FIRST(port_id, unused2, idx, op)		\
-	COND_CODE_1(UTIL_BOOL(idx), (USB_MUX_DO(port_id, idx, op)), ())
+#define USB_MUX_SKIP_ROOT(chain_id, unused2, idx, op) \
+	COND_CODE_1(UTIL_BOOL(idx), (op(chain_id, idx)), ())
+
+/**
+ * @brief Call @p op for each mux in @p chain_id chain except the root mux
+ *
+ * @param chain_id Chain DTS node ID
+ * @param op Operation to perform on USB muxes
+ */
+#define USB_MUX_FOREACH_NO_ROOT_MUX(chain_id, op) \
+	DT_FOREACH_PROP_ELEM_VARGS(chain_id, usb_muxes, USB_MUX_SKIP_ROOT, op)
+
+/**
+ * @brief Create usb_muxes array entry for @p chain_id chain
+ *
+ * @param chain_id Chain DTS node ID
+ */
+#define USB_MUX_DEFINE_ROOT_MUX(chain_id) \
+	[USBC_PORT(chain_id)] = USB_MUX_CHAIN_STRUCT_INIT(chain_id, 0),
+
+/**
+ * @brief Call @p op only if chain @p chain_id is not alternative
+ *
+ * @param chain_id Chain DTS node ID
+ * @param op Operation to perform on main USB mux chain
+ * @param ... Arguments to pass to the @p op operation
+ */
+#define USB_MUX_FOR_MAIN_CHAIN(chain_id, op, ...)         \
+	COND_CODE_0(DT_PROP(chain_id, alternative_chain), \
+		    (op(chain_id, ##__VA_ARGS__)), ())
 
 /**
- * @brief Call @p op with every mux in chain expect the first one
+ * @brief Call @p op for each USB mux chain
  *
- * @param port_id USBC node ID
- * @param op Operation to perform on USB muxes. Needs to accept USB mux node
- *           ID, USBC port node ID, position in chain, and driver config as
- *           arguments.
+ * @param op Operation to perform on USB mux chain
  */
-#define USB_MUX_NO_FIRST(port_id, op)					\
-	DT_FOREACH_PROP_ELEM_VARGS(port_id, usb_muxes,			\
-				   USB_MUX_DO_SKIP_FIRST, op)
+#define USB_MUX_FOREACH_CHAIN(op) \
+	DT_FOREACH_STATUS_OKAY(cros_ec_usb_mux_chain, op)
 
 /**
- * @brief Call @p op if @p idx mux in chain has BB retimer compatible
+ * @brief Call @p op for each USB mux chain with arguments
  *
- * @param port_id USBC node ID
+ * @param op Operation to perform on USB mux chain
+ * @param ... Arguments to pass to the @p op operation
+ */
+#define USB_MUX_FOREACH_CHAIN_VARGS(op, ...) \
+	DT_FOREACH_STATUS_OKAY_VARGS(cros_ec_usb_mux_chain, op, __VA_ARGS__)
+
+/**
+ * @brief Construct first half of conditional expression (?:) that evaluates to
+ *        @p chain_id USB port if @p idx mux in @p chain_id is the same as
+ *        @p mux_id
+ *
+ * @param chain_id USB mux chain node ID
  * @param unused2 This argument is expected by DT_FOREACH_PROP_ELEM_VARGS
  * @param idx Position of USB mux in chain
- * @param op Operation to perform on BB retimer
+ * @param mux_id USB mux node ID to compare with @p idx mux
  */
-#define USB_MUX_ONLY_BB_RETIMER(port_id, unused2, idx, op)		\
-	COND_CODE_1(USB_MUX_IS_COMPATIBLE(				\
-			USB_MUX_GET_CHAIN_N(idx, port_id),		\
-			BB_RETIMER_USB_MUX_COMPAT),			\
-			(op(USB_MUX_GET_CHAIN_N(idx, port_id), port_id, \
-			    idx, BB_RETIMER_CONTROLS_CONFIG)), ())
+#define USB_MUX_PORT_IF_SAME_NODES(chain_id, unused2, idx, mux_id) \
+	DT_SAME_NODE(mux_id, USB_MUX_GET_CHAIN_N(chain_id, idx)) ? \
+		USBC_PORT(chain_id):
 
 /**
- * @brief Call @p op with every BB retimer in chain
+ * @brief Compare @p mux_id with all muxes in @p chain_id
  *
- * @param port_id USBC node ID
- * @param op Operation to perform on BB retimers. Needs to accept USB mux node
- *           ID, USBC port node ID, position in chain, and driver config as
- *           arguments.
+ * @param chain_id USB mux chain node ID
+ * @param mux_id USB mux node ID
  */
-#define USB_MUX_BB_RETIMERS(port_id, op)				\
-	DT_FOREACH_PROP_ELEM_VARGS(port_id, usb_muxes,			\
-				   USB_MUX_ONLY_BB_RETIMER, op)
+#define USB_MUX_FIND_PORT(chain_id, mux_id)             \
+	DT_FOREACH_PROP_ELEM_VARGS(chain_id, usb_muxes, \
+				   USB_MUX_PORT_IF_SAME_NODES, mux_id)
 
 /**
- * @brief If @p port_id has usb_muxes property, call @p op with every mux in
- *        chain that passes @p filter
+ * @brief Get port for @p mux_id by looking for an usb mux chain where @p mux_id
+ *        is present. If the mux is not present in any chain, this macro
+ *        evaluate to -1.
+ *
+ * This expands to:
+ *     (DT_DEP_ORD(mux_id) == DT_DEP_ORD(USB_MUX_GET_CHAIN_N(chain1_id, 0))) ?
+ *         USBC_PORT(chain1_id) :
+ *     (DT_DEP_ORD(mux_id) == DT_DEP_ORD(USB_MUX_GET_CHAIN_N(chain1_id, 1))) ?
+ *         USBC_PORT(chain1_id) :
+ *         ...
+ *     (DT_DEP_ORD(mux_id) == DT_DEP_ORD(USB_MUX_GET_CHAIN_N(chain1_id, n))) ?
+ *         USBC_PORT(chain1_id) :
+ *     (DT_DEP_ORD(mux_id) == DT_DEP_ORD(USB_MUX_GET_CHAIN_N(chain2_id, 0))) ?
+ *         USBC_PORT(chain2_id) :
+ *         ...
+ *     (DT_DEP_ORD(mux_id) == DT_DEP_ORD(USB_MUX_GET_CHAIN_N(chainm_id, k))) ?
+ *         USBC_PORT(chainm_id) : (-1)
  *
- * @param port_id USBC node ID
- * @param filter Macro that should filter USB muxes and call @p op on them.
- *               It has @p port_id and @p op as arguments. It is called
- *               only for @p port_id that has usb_muxes property.
- * @param op Operation to perform on USB muxes. Needs to accept USB mux node
- *           ID, USBC port node ID, position in chain, and driver config as
- *           arguments.
+ * @param mux_id USB mux node ID
+ */
+#define USB_MUX_PORT(mux_id) \
+	(USB_MUX_FOREACH_CHAIN_VARGS(USB_MUX_FIND_PORT, mux_id)(-1))
+
+/**
+ * @brief Set usb_mux_chain structure for mux @p idx in chain @p chain_id
+ *
+ * @param chain_id Alternative USB mux chain node ID
+ * @param idx Position of the mux in chain
+ */
+#define USB_MUX_SET_ALTERNATIVE(chain_id, idx)                \
+	USB_MUX_CHAIN_STRUCT_NAME(idx, USBC_PORT(chain_id)) = \
+		USB_MUX_CHAIN_STRUCT_SET(chain_id, idx);
+
+/**
+ * @brief Enable alternative USB mux chain
+ *
+ * @param chain_id Alternative USB mux chain node ID
  */
-#define USB_MUX_USBC_PORT_HAS_MUXES(port_id, filter, op)		\
-	COND_CODE_1(DT_NODE_HAS_PROP(port_id, usb_muxes),		\
-		    (filter(port_id, op)), ())
+#define USB_MUX_ENABLE_ALTERNATIVE_NODE(chain_id)                              \
+	do {                                                                   \
+		usb_muxes[USBC_PORT(chain_id)] =                               \
+			USB_MUX_CHAIN_STRUCT_SET(chain_id, 0);                 \
+		USB_MUX_FOREACH_NO_ROOT_MUX(chain_id, USB_MUX_SET_ALTERNATIVE) \
+	} while (0)
 
 /**
- * @brief For every USBC port that has muxes, call @p op with every mux in chain
- *        that passes @p filter
+ * @brief Enable alternative USB mux chain
  *
- * @param filter Macro that should filter USB muxes and call @p op on them.
- *               It has USBC port node ID and @p op as arguments. It is called
- *               only for USBC ports that have usb_muxes property.
- * @param op Operation to perform on USB muxes. Needs to accept USB mux node
- *           ID, USBC port node ID, position in chain, and driver config as
- *           arguments.
+ * @param nodelabel Label of alternative USB mux chain
  */
-#define USB_MUX_FOREACH_USBC_PORT(filter, op)				\
-	DT_FOREACH_STATUS_OKAY_VARGS(named_usbc_port,			\
-				     USB_MUX_USBC_PORT_HAS_MUXES,	\
-				     filter, op)
+#define USB_MUX_ENABLE_ALTERNATIVE(nodelabel) \
+	USB_MUX_ENABLE_ALTERNATIVE_NODE(DT_NODELABEL(nodelabel))
 
 /**
  * Forward declare all usb_mux structures e.g.
  * MAYBE_CONST struct usb_mux USB_MUX_NODE_<node_id>;
  */
-USB_MUX_FOREACH_USBC_PORT(USB_MUX_NO_FIRST, USB_MUX_DECLARE)
+USB_MUX_FOREACH_MUX(USB_MUX_DECLARE)
+
+/**
+ * Forward declare all usb_mux_chain structures e.g.
+ * extern MAYBE_CONST struct usb_mux_chain
+ * USB_MUX_chain_port_<node_id>_mux_<position_id>;
+ */
+USB_MUX_FOREACH_CHAIN_VARGS(USB_MUX_FOREACH_NO_ROOT_MUX,
+			    USB_MUX_CHAIN_STRUCT_DECLARE_EXTERN_OP)
 
 #endif /* ZEPHYR_CHROME_USBC_USB_MUXES_H */
diff --git a/zephyr/shim/include/usbc/utils.h b/zephyr/shim/include/usbc/utils.h
index 49b9aa4b71..53e9a34856 100644
--- a/zephyr/shim/include/usbc/utils.h
+++ b/zephyr/shim/include/usbc/utils.h
@@ -1,22 +1,19 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #ifndef __CROS_EC_ZEPHYR_SHIM_USBC_UTIL
 
-
 /*
  * Enable interrupt from the `irq` property of an instance's node.
  *
  * @param inst: instance number
  */
-#define BC12_GPIO_ENABLE_INTERRUPT(inst)				\
-	IF_ENABLED(DT_INST_NODE_HAS_PROP(inst, irq),			\
-		   (gpio_enable_dt_interrupt(				\
-			GPIO_INT_FROM_NODE(DT_INST_PHANDLE(inst, irq)));\
-		   ) \
-		  )
+#define BC12_GPIO_ENABLE_INTERRUPT(inst)             \
+	IF_ENABLED(DT_INST_NODE_HAS_PROP(inst, irq), \
+		   (gpio_enable_dt_interrupt(        \
+			    GPIO_INT_FROM_NODE(DT_INST_PHANDLE(inst, irq)));))
 
 /*
  * Get the port number from a child of `named-usbc-port` node.
@@ -26,11 +23,17 @@
 #define USBC_PORT(id) DT_REG_ADDR(DT_PARENT(id))
 
 /*
+ * Get the port number from a `named-usbc-port` node.
+ *
+ * @param id: `named-usbc-port` node id
+ */
+#define USBC_PORT_NEW(id) DT_REG_ADDR(id)
+
+/*
  * Get the port number from a child of `named-usbc-port` node.
  *
  * @param inst: instance number of the node
  */
 #define USBC_PORT_FROM_INST(inst) USBC_PORT(DT_DRV_INST(inst))
 
-
 #endif /* __CROS_EC_ZEPHYR_SHIM_USBC_UTIL */
diff --git a/zephyr/shim/include/usbc/virtual_usb_mux.h b/zephyr/shim/include/usbc/virtual_usb_mux.h
index 5f4c2fb466..bbb2d8730e 100644
--- a/zephyr/shim/include/usbc/virtual_usb_mux.h
+++ b/zephyr/shim/include/usbc/virtual_usb_mux.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,13 +8,13 @@
 
 #include "usb_mux.h"
 
-#define VIRTUAL_USB_MUX_COMPAT	cros_ec_usbc_mux_virtual
+#define VIRTUAL_USB_MUX_COMPAT cros_ec_usbc_mux_virtual
 
-#define USB_MUX_CONFIG_VIRTUAL(mux_id, port_id, idx)			\
-	{								\
-		USB_MUX_COMMON_FIELDS(mux_id, port_id, idx),		\
-		.driver = &virtual_usb_mux_driver,			\
-		.hpd_update = &virtual_hpd_update,			\
+#define USB_MUX_CONFIG_VIRTUAL(mux_id)                     \
+	{                                                  \
+		USB_MUX_COMMON_FIELDS(mux_id),             \
+			.driver = &virtual_usb_mux_driver, \
+			.hpd_update = &virtual_hpd_update, \
 	}
 
 #endif /* __ZEPHYR_SHIM_VIRTUAL_USB_MUX_H */
diff --git a/zephyr/shim/include/zephyr_adc.h b/zephyr/shim/include/zephyr_adc.h
index aff6d7a5b6..d4139692f7 100644
--- a/zephyr/shim/include/zephyr_adc.h
+++ b/zephyr/shim/include/zephyr_adc.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,20 +8,18 @@
 
 #include <zephyr/drivers/adc.h>
 
-#ifdef CONFIG_PLATFORM_EC_ADC
+#ifdef CONFIG_ADC
 
 #define ZSHIM_ADC_ID(node_id) DT_STRING_UPPER_TOKEN(node_id, enum_name)
-#define ADC_ID_WITH_COMMA(node_id)    ZSHIM_ADC_ID(node_id),
 
 enum adc_channel {
 #if DT_NODE_EXISTS(DT_INST(0, named_adc_channels))
-	DT_FOREACH_CHILD(DT_INST(0, named_adc_channels), ADC_ID_WITH_COMMA)
+	DT_FOREACH_CHILD_SEP(DT_INST(0, named_adc_channels), ZSHIM_ADC_ID,
+			     (, )),
 #endif /* named_adc_channels */
 	ADC_CH_COUNT
 };
 
-#undef ADC_ID_WITH_COMMA
-
 struct adc_t {
 	const char *name;
 	const struct device *dev;
@@ -38,9 +36,7 @@ extern struct adc_t adc_channels[];
 #endif /* CONFIG_ADC_CHANNELS_RUNTIME_CONFIG */
 #else
 /* Empty declaration to avoid warnings if adc.h is included */
-enum adc_channel {
-	ADC_CH_COUNT
-};
-#endif /* CONFIG_PLATFORM_EC_ADC */
+enum adc_channel { ADC_CH_COUNT };
+#endif /* CONFIG_ADC */
 
 #endif /* __CROS_EC_ZEPHYR_ADC_H */
diff --git a/zephyr/shim/include/zephyr_console_shim.h b/zephyr/shim/include/zephyr_console_shim.h
index 5880c3f400..42ac3e693b 100644
--- a/zephyr/shim/include/zephyr_console_shim.h
+++ b/zephyr/shim/include/zephyr_console_shim.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,7 +10,7 @@
 
 struct zephyr_console_command {
 	/* Handler for the command.  argv[0] will be the command name. */
-	int (*handler)(int argc, char **argv);
+	int (*handler)(int argc, const char **argv);
 #ifdef CONFIG_SHELL_HELP
 	/* Description of args */
 	const char *argdesc;
@@ -20,9 +20,7 @@ struct zephyr_console_command {
 };
 
 #ifdef CONFIG_SHELL_HELP
-#define _HELP_ARGS(A, H) \
-	.argdesc = A,     \
-	.help = H,
+#define _HELP_ARGS(A, H) .argdesc = A, .help = H,
 #else
 #define _HELP_ARGS(A, H)
 #endif
@@ -38,17 +36,16 @@ struct zephyr_console_command {
  * Return: the return value from the handler.
  */
 int zshim_run_ec_console_command(const struct zephyr_console_command *command,
-				 size_t argc, char **argv);
+				 size_t argc, const char **argv);
 
 /* Internal wrappers for DECLARE_CONSOLE_COMMAND_* macros. */
 #define _ZEPHYR_SHELL_COMMAND_SHIM_2(NAME, ROUTINE_ID, ARGDESC, HELP,       \
 				     WRAPPER_ID, ENTRY_ID)                  \
 	static const struct zephyr_console_command ENTRY_ID = {             \
-		.handler = ROUTINE_ID,                                      \
-		_HELP_ARGS(ARGDESC, HELP)                                   \
+		.handler = ROUTINE_ID, _HELP_ARGS(ARGDESC, HELP)            \
 	};                                                                  \
 	static int WRAPPER_ID(const struct shell *shell, size_t argc,       \
-			      char **argv)                                  \
+			      const char **argv)                            \
 	{                                                                   \
 		return zshim_run_ec_console_command(&ENTRY_ID, argc, argv); \
 	}                                                                   \
@@ -79,7 +76,9 @@ int zshim_run_ec_console_command(const struct zephyr_console_command *command,
  *
  * @s:			The pointer to the string.
  * @len:		The size of the string.
+ *
+ * Return: the number of bytes consumed.
  */
-void console_buf_notify_chars(const char *s, size_t len);
+size_t console_buf_notify_chars(const char *s, size_t len);
 
 #endif /* __CROS_EC_ZEPHYR_CONSOLE_SHIM_H */
diff --git a/zephyr/shim/include/zephyr_espi_shim.h b/zephyr/shim/include/zephyr_espi_shim.h
index 4f147752d7..ddc4da075c 100644
--- a/zephyr/shim/include/zephyr_espi_shim.h
+++ b/zephyr/shim/include/zephyr_espi_shim.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/shim/include/zephyr_gpio_signal.h b/zephyr/shim/include/zephyr_gpio_signal.h
index 8949826987..1a98071d6d 100644
--- a/zephyr/shim/include/zephyr_gpio_signal.h
+++ b/zephyr/shim/include/zephyr_gpio_signal.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -34,27 +34,48 @@
  * a GPIO signal name from either the enum-name or a
  * unique name generated using the DTS ordinal.
  */
-#define GPIO_SIGNAL_NAME(id)					\
-	COND_CODE_1(DT_NODE_HAS_PROP(id, enum_name),		\
-		(GPIO_SIGNAL_NAME_FROM_ENUM(id)),		\
-		(GPIO_SIGNAL_NAME_FROM_ORD(id ## _ORD)))
-
-#define GPIO_SIGNAL(id)		GPIO_SIGNAL_NAME(id)
-#define GPIO_SIGNAL_WITH_COMMA(id) \
-	GPIO_SIGNAL(id),
+#define GPIO_SIGNAL_NAME(id)                          \
+	COND_CODE_1(DT_NODE_HAS_PROP(id, enum_name),  \
+		    (GPIO_SIGNAL_NAME_FROM_ENUM(id)), \
+		    (GPIO_SIGNAL_NAME_FROM_ORD(id##_ORD)))
+
+#define GPIO_SIGNAL(id) GPIO_SIGNAL_NAME(id)
+
+#define GPIO_IMPL_SIGNAL(id) \
+	COND_CODE_1(DT_NODE_HAS_PROP(id, gpios), (GPIO_SIGNAL(id), ), ())
+
+#define GPIO_UNIMPL_SIGNAL(id)                       \
+	COND_CODE_1(DT_NODE_HAS_PROP(id, gpios), (), \
+		    (GPIO_SIGNAL_NAME(id) = GPIO_UNIMPLEMENTED, ))
+/*
+ * Create a list of aliases to allow remapping of aliased names.
+ */
+#define GPIO_DT_MK_ALIAS(id) \
+	DT_STRING_UPPER_TOKEN(id, alias) = DT_STRING_UPPER_TOKEN(id, enum_name),
+
+#define GPIO_DT_ALIAS_LIST(id) \
+	COND_CODE_1(DT_NODE_HAS_PROP(id, alias), (GPIO_DT_MK_ALIAS(id)), ())
+
 enum gpio_signal {
 	GPIO_UNIMPLEMENTED = -1,
 #if DT_NODE_EXISTS(DT_PATH(named_gpios))
-	DT_FOREACH_CHILD(DT_PATH(named_gpios), GPIO_SIGNAL_WITH_COMMA)
+	DT_FOREACH_CHILD(DT_PATH(named_gpios), GPIO_IMPL_SIGNAL)
 #endif
-	GPIO_COUNT,
-	GPIO_LIMIT = 0x0FFF,
+		GPIO_COUNT,
+#if DT_NODE_EXISTS(DT_PATH(named_gpios))
+	DT_FOREACH_CHILD(DT_PATH(named_gpios), GPIO_UNIMPL_SIGNAL)
+		DT_FOREACH_CHILD(DT_PATH(named_gpios), GPIO_DT_ALIAS_LIST)
+#endif
+			GPIO_LIMIT = 0x0FFF,
 
 	IOEX_SIGNAL_START = GPIO_LIMIT + 1,
 	IOEX_SIGNAL_END = IOEX_SIGNAL_START,
 	IOEX_LIMIT = 0x1FFF,
 };
-#undef GPIO_SIGNAL_WITH_COMMA
+#undef GPIO_DT_ALIAS_LIST
+#undef GPIO_DT_MK_ALIAS
+#undef GPIO_IMPL_SIGNAL
+#undef GPIO_UNIMPL_SIGNAL
 
 BUILD_ASSERT(GPIO_COUNT < GPIO_LIMIT);
 
@@ -118,8 +139,8 @@ BUILD_ASSERT(GPIO_COUNT < GPIO_LIMIT);
  */
 struct gpio_dt_spec;
 
-#define GPIO_DT_PTR_DECL(id) extern const struct gpio_dt_spec * const \
-	GPIO_DT_NAME(GPIO_SIGNAL(id));
+#define GPIO_DT_PTR_DECL(id) \
+	extern const struct gpio_dt_spec *const GPIO_DT_NAME(GPIO_SIGNAL(id));
 
 DT_FOREACH_CHILD(DT_PATH(named_gpios), GPIO_DT_PTR_DECL)
 
@@ -127,14 +148,13 @@ DT_FOREACH_CHILD(DT_PATH(named_gpios), GPIO_DT_PTR_DECL)
 
 #endif /* DT_NODE_EXISTS(DT_PATH(named_gpios)) */
 
-
 #define IOEXPANDER_ID_EXPAND(id) ioex_chip_##id
 #define IOEXPANDER_ID(id) IOEXPANDER_ID_EXPAND(id)
 #define IOEXPANDER_ID_FROM_INST_WITH_COMMA(id) IOEXPANDER_ID(id),
 enum ioexpander_id {
 	DT_FOREACH_STATUS_OKAY(cros_ioex_chip,
-		IOEXPANDER_ID_FROM_INST_WITH_COMMA)
-	CONFIG_IO_EXPANDER_PORT_COUNT
+			       IOEXPANDER_ID_FROM_INST_WITH_COMMA)
+		CONFIG_IO_EXPANDER_PORT_COUNT
 };
 
 /**
diff --git a/zephyr/shim/include/zephyr_hooks_shim.h b/zephyr/shim/include/zephyr_hooks_shim.h
index 1798a42aeb..f3949787bd 100644
--- a/zephyr/shim/include/zephyr_hooks_shim.h
+++ b/zephyr/shim/include/zephyr_hooks_shim.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,7 +10,6 @@
 
 #include <zephyr/init.h>
 #include <zephyr/kernel.h>
-#include <zephyr/zephyr.h>
 
 #include "common.h"
 #include "cros_version.h"
@@ -31,7 +30,7 @@ int hook_call_deferred(const struct deferred_data *data, int us);
 	K_WORK_DELAYABLE_DEFINE(routine##_work_data,                 \
 				(void (*)(struct k_work *))routine); \
 	__maybe_unused const struct deferred_data routine##_data = { \
-		.work = &routine##_work_data,                \
+		.work = &routine##_work_data,                        \
 	}
 
 /**
diff --git a/zephyr/shim/include/zephyr_host_command.h b/zephyr/shim/include/zephyr_host_command.h
index cc67049614..e2f0a7c296 100644
--- a/zephyr/shim/include/zephyr_host_command.h
+++ b/zephyr/shim/include/zephyr_host_command.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -27,24 +27,19 @@ bool in_host_command_main(void);
 /**
  * See include/host_command.h for documentation.
  */
-#define DECLARE_HOST_COMMAND(_command, _routine, _version_mask)            \
-	STRUCT_SECTION_ITERABLE(host_command, _cros_hcmd_##_command) = {   \
-		.command = _command,                                       \
-		.handler = _routine,                                       \
-		.version_mask = _version_mask,                             \
+#define DECLARE_HOST_COMMAND(_command, _routine, _version_mask)          \
+	STRUCT_SECTION_ITERABLE(host_command, _cros_hcmd_##_command) = { \
+		.command = _command,                                     \
+		.handler = _routine,                                     \
+		.version_mask = _version_mask,                           \
 	}
 #else /* !CONFIG_PLATFORM_EC_HOSTCMD */
 
 /*
- * Create a fake routine to call the function. The linker should
- * garbage-collect it since it is behind 'if (0)'
+ * Create a global var to reference the host command. The linker should remove
+ * it since it is never referenced.
  */
-#define DECLARE_HOST_COMMAND(command, routine, version_mask)		\
-	int __remove_ ## command(void)					\
-	{								\
-		if (0)							\
-			routine(NULL);					\
-		return 0;						\
-	}
+#define DECLARE_HOST_COMMAND(command, routine, version_mask) \
+	int __remove_##command = ((int)(routine))
 
 #endif /* CONFIG_PLATFORM_EC_HOSTCMD */
diff --git a/zephyr/shim/include/zephyr_mkbp_event.h b/zephyr/shim/include/zephyr_mkbp_event.h
index 159aebc8e1..b8cb88029d 100644
--- a/zephyr/shim/include/zephyr_mkbp_event.h
+++ b/zephyr/shim/include/zephyr_mkbp_event.h
@@ -1,23 +1,22 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#if !defined(__CROS_EC_MKBP_EVENT_H) || \
-	defined(__CROS_EC_ZEPHYR_MKBP_EVENT_H)
+#if !defined(__CROS_EC_MKBP_EVENT_H) || defined(__CROS_EC_ZEPHYR_MKBP_EVENT_H)
 #error "This file must only be included from mkbp_event.h. " \
 	"Include mkbp_event.h directly"
 #endif
 #define __CROS_EC_ZEPHYR_MKBP_EVENT_H
 
-const struct mkbp_event_source *zephyr_find_mkbp_event_source(
-		uint8_t event_type);
+const struct mkbp_event_source *
+zephyr_find_mkbp_event_source(uint8_t event_type);
 
 /**
  * See include/mkbp_event.h for documentation.
  */
-#define DECLARE_EVENT_SOURCE(_type, _func)                                     \
-	STRUCT_SECTION_ITERABLE(mkbp_event_source, _cros_evtsrc_##_func) = {   \
-		.event_type = _type,                                           \
-		.get_data = _func,                                             \
+#define DECLARE_EVENT_SOURCE(_type, _func)                                   \
+	STRUCT_SECTION_ITERABLE(mkbp_event_source, _cros_evtsrc_##_func) = { \
+		.event_type = _type,                                         \
+		.get_data = _func,                                           \
 	}
diff --git a/zephyr/shim/include/zephyr_write_protect.h b/zephyr/shim/include/zephyr_write_protect.h
index 3af2fb3576..227af16bd0 100644
--- a/zephyr/shim/include/zephyr_write_protect.h
+++ b/zephyr/shim/include/zephyr_write_protect.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/shim/src/CMakeLists.txt b/zephyr/shim/src/CMakeLists.txt
index dee8d0af71..97968e8a52 100644
--- a/zephyr/shim/src/CMakeLists.txt
+++ b/zephyr/shim/src/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -20,7 +20,7 @@ endif()
 
 zephyr_library_sources_ifdef(no_libgcc                  libgcc_${ARCH}.S)
 
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ADC         adc.c)
+zephyr_library_sources_ifdef(CONFIG_ADC                     adc.c)
 zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_BATTERY
                                                             battery.c)
 zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER_RT9490
@@ -43,6 +43,8 @@ if (NOT DEFINED CONFIG_PLATFORM_EC_KEYBOARD_DISCRETE)
                                                             keyboard_raw.c)
 endif()
 zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_KEYBOARD    keyscan.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LOG_BACKEND_CONSOLE_BUFFER
+                             log_backend_console_buffer.c)
 zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_MKBP_EVENT  mkbp_event.c)
 zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_MOTIONSENSE
                                                             motionsense_sensors.c)
@@ -73,3 +75,7 @@ zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_TCPM_TCPCI
 zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBA        usba.c)
 zephyr_library_sources_ifdef(CONFIG_AP_PWRSEQ power_host_sleep_api.c)
 zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_MUX     usb_muxes.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_BB
+                                                            bb_retimer_usb_mux.c)
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_HB
+                                                            bb_retimer_usb_mux.c)
diff --git a/zephyr/shim/src/adc.c b/zephyr/shim/src/adc.c
index 80cf60391d..e14ef9f20f 100644
--- a/zephyr/shim/src/adc.c
+++ b/zephyr/shim/src/adc.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,10 +18,10 @@ LOG_MODULE_REGISTER(shim_adc, LOG_LEVEL_ERR);
 #define HAS_NAMED_ADC_CHANNELS DT_NODE_EXISTS(DT_INST(0, named_adc_channels))
 
 #if HAS_NAMED_ADC_CHANNELS
-#define ADC_CHANNEL_COMMA(node_id)                                        \
+#define ADC_CHANNEL_INIT(node_id) \
 	[ZSHIM_ADC_ID(node_id)] = {                                       \
-		.name = DT_LABEL(node_id),                                \
-		.dev = DEVICE_DT_GET(DT_IO_CHANNELS_CTLR(node_id)),        \
+		.name = DT_NODE_FULL_NAME(node_id),                       \
+		.dev = DEVICE_DT_GET(DT_IO_CHANNELS_CTLR(node_id)),       \
 		.input_ch = DT_IO_CHANNELS_INPUT(node_id),                \
 		.factor_mul = DT_PROP(node_id, mul),                      \
 		.factor_div = DT_PROP(node_id, div),                      \
@@ -35,11 +35,11 @@ LOG_MODULE_REGISTER(shim_adc, LOG_LEVEL_ERR);
 		},                                                        \
 	},
 #ifdef CONFIG_ADC_CHANNELS_RUNTIME_CONFIG
-struct adc_t adc_channels[] = { DT_FOREACH_CHILD(
-	DT_INST(0, named_adc_channels), ADC_CHANNEL_COMMA) };
+struct adc_t adc_channels[] = { DT_FOREACH_CHILD(DT_INST(0, named_adc_channels),
+						 ADC_CHANNEL_INIT) };
 #else
 const struct adc_t adc_channels[] = { DT_FOREACH_CHILD(
-	DT_INST(0, named_adc_channels), ADC_CHANNEL_COMMA) };
+	DT_INST(0, named_adc_channels), ADC_CHANNEL_INIT) };
 #endif
 #endif /* named_adc_channels */
 
diff --git a/zephyr/shim/src/battery.c b/zephyr/shim/src/battery.c
index 73f72f2e81..cdf6e6d894 100644
--- a/zephyr/shim/src/battery.c
+++ b/zephyr/shim/src/battery.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,7 +8,7 @@
 #include "battery_fuel_gauge.h"
 
 #define NODE_FUEL_GAUGE(node) \
-{ \
+	{ \
 	.manuf_name = DT_PROP(node, manuf_name), \
 	.device_name = DT_PROP(node, device_name), \
 	.ship_mode = { \
@@ -22,7 +22,7 @@
 		.reg_data = DT_PROP_OR(node, sleep_mode_reg_data, 0), \
 	}, \
 	.fet = { \
-		.mfgacc_support = DT_PROP_OR(node, fet_mgfacc_support, 0), \
+		.mfgacc_support = DT_PROP_OR(node, fet_mfgacc_support, 0), \
 		.reg_addr = DT_PROP_OR(node, fet_reg_addr, 0), \
 		.reg_mask = DT_PROP(node, fet_reg_mask), \
 		.disconnect_val = DT_PROP(node, fet_disconnect_val), \
@@ -34,32 +34,29 @@
 		(.imbalance_mv = DT_STRING_TOKEN(node, imbalance_mv),), ()) \
 },
 
-#define NODE_BATT_INFO(node) \
-{ \
-	.voltage_max = DT_PROP(node, voltage_max), \
-	.voltage_normal = DT_PROP(node, voltage_normal), \
-	.voltage_min = DT_PROP(node, voltage_min), \
-	.precharge_voltage = DT_PROP_OR(node, precharge_voltage, 0), \
-	.precharge_current = DT_PROP_OR(node, precharge_current, 0), \
-	.start_charging_min_c = DT_PROP(node, start_charging_min_c), \
-	.start_charging_max_c = DT_PROP(node, start_charging_max_c), \
-	.charging_min_c = DT_PROP(node, charging_min_c), \
-	.charging_max_c = DT_PROP(node, charging_max_c), \
-	.discharging_min_c = DT_PROP(node, discharging_min_c), \
-	.discharging_max_c = DT_PROP(node, discharging_max_c), \
-},
+#define NODE_BATT_INFO(node)                                                 \
+	{                                                                    \
+		.voltage_max = DT_PROP(node, voltage_max),                   \
+		.voltage_normal = DT_PROP(node, voltage_normal),             \
+		.voltage_min = DT_PROP(node, voltage_min),                   \
+		.precharge_voltage = DT_PROP_OR(node, precharge_voltage, 0), \
+		.precharge_current = DT_PROP_OR(node, precharge_current, 0), \
+		.start_charging_min_c = DT_PROP(node, start_charging_min_c), \
+		.start_charging_max_c = DT_PROP(node, start_charging_max_c), \
+		.charging_min_c = DT_PROP(node, charging_min_c),             \
+		.charging_max_c = DT_PROP(node, charging_max_c),             \
+		.discharging_min_c = DT_PROP(node, discharging_min_c),       \
+		.discharging_max_c = DT_PROP(node, discharging_max_c),       \
+	},
 
-#define NODE_BATT_PARAMS(node) \
-{ \
-	.fuel_gauge = NODE_FUEL_GAUGE(node) \
-	.batt_info = NODE_BATT_INFO(node) \
-},
+#define NODE_BATT_PARAMS(node)                            \
+	{ .fuel_gauge = NODE_FUEL_GAUGE(node).batt_info = \
+		  NODE_BATT_INFO(node) },
 
 #if DT_HAS_COMPAT_STATUS_OKAY(battery_smart)
 
-const struct board_batt_params board_battery_info[] = {
-	DT_FOREACH_STATUS_OKAY(battery_smart, NODE_BATT_PARAMS)
-};
+const struct board_batt_params board_battery_info[] = { DT_FOREACH_STATUS_OKAY(
+	battery_smart, NODE_BATT_PARAMS) };
 
 #if DT_NODE_EXISTS(DT_NODELABEL(default_battery))
 #define BAT_ENUM(node) DT_CAT(BATTERY_, node)
diff --git a/zephyr/shim/src/bb_retimer_usb_mux.c b/zephyr/shim/src/bb_retimer_usb_mux.c
new file mode 100644
index 0000000000..c40068211e
--- /dev/null
+++ b/zephyr/shim/src/bb_retimer_usb_mux.c
@@ -0,0 +1,39 @@
+/* Copyright 2022 The ChromiumOS Authors.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/devicetree.h>
+#include <zephyr/sys/util_macro.h>
+#include "usb_mux.h"
+#include "usbc/usb_muxes.h"
+
+/**
+ * This prevents creating struct usb_mux bb_controls[] for platforms that didn't
+ * migrate USB mux configuration to DTS yet.
+ */
+#if DT_HAS_COMPAT_STATUS_OKAY(cros_ec_usb_mux_chain)
+
+BB_RETIMER_CHECK_SAME_CONTROLS(BB_RETIMER_INSTANCES_LIST)
+
+/**
+ * @brief bb_controls array should be constant only if configuration cannot
+ *        change in runtime
+ */
+#define BB_CONTROLS_CONST                                                    \
+	COND_CODE_1(CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_BB_RUNTIME_CONFIG, \
+		    (), (const))
+
+/**
+ * Define bb_controls for BB retimers in USB muxes chain e.g.
+ * [0] = {
+ *         .retimer_rst_gpio = IOEX_USB_C0_BB_RETIMER_RST,
+ *         .usb_ls_en_gpio = IOEX_USB_C0_BB_RETIMER_LS_EN,
+ * },
+ * [1] = { ... },
+ */
+BB_CONTROLS_CONST struct bb_usb_control bb_controls[] = {
+	USB_MUX_BB_RETIMERS_CONTROLS_ARRAY
+};
+
+#endif /* #if DT_HAS_COMPAT_STATUS_OKAY(cros_ec_usb_mux_chain) */
diff --git a/zephyr/shim/src/bc12.c b/zephyr/shim/src/bc12.c
index 3bdab5f16e..6542a166eb 100644
--- a/zephyr/shim/src/bc12.c
+++ b/zephyr/shim/src/bc12.c
@@ -1,29 +1,46 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include <zephyr/devicetree.h>
 #include "usbc/bc12_pi3usb9201.h"
+#include "usbc/bc12_rt1718s.h"
 #include "usbc/bc12_rt1739.h"
 #include "usbc/bc12_rt9490.h"
+#include "usbc/tcpc_rt1718s.h"
 #include "usbc/utils.h"
 #include "usb_charge.h"
 
-#if DT_HAS_COMPAT_STATUS_OKAY(RT1739_BC12_COMPAT) || \
+#if DT_HAS_COMPAT_STATUS_OKAY(RT1718S_BC12_COMPAT) ||    \
+	DT_HAS_COMPAT_STATUS_OKAY(RT1739_BC12_COMPAT) || \
 	DT_HAS_COMPAT_STATUS_OKAY(RT9490_BC12_COMPAT) || \
 	DT_HAS_COMPAT_STATUS_OKAY(PI3USB9201_COMPAT)
 
-#define BC12_CHIP(id, fn) [USBC_PORT(id)] = fn(id)
-
-/* Power Path Controller */
-struct bc12_config bc12_ports[CHARGE_PORT_COUNT] = {
-	DT_FOREACH_STATUS_OKAY_VARGS(RT1739_BC12_COMPAT, BC12_CHIP,
-				     BC12_CHIP_RT1739)
-	DT_FOREACH_STATUS_OKAY_VARGS(RT9490_BC12_COMPAT, BC12_CHIP,
-				     BC12_CHIP_RT9490)
-	DT_FOREACH_STATUS_OKAY_VARGS(PI3USB9201_COMPAT, BC12_CHIP,
-				     BC12_CHIP_PI3USB9201)
-};
+/* Check RT1718S dependency. BC12 node must be dependent on TCPC node. */
+#if DT_HAS_COMPAT_STATUS_OKAY(RT1718S_BC12_COMPAT)
+BUILD_ASSERT(DT_HAS_COMPAT_STATUS_OKAY(RT1718S_TCPC_COMPAT));
+#endif
+
+#define BC12_CHIP_ENTRY(usbc_id, bc12_id, chip_fn) \
+	[USBC_PORT_NEW(usbc_id)] = chip_fn(bc12_id)
+
+#define CHECK_COMPAT(compat, usbc_id, bc12_id, config)   \
+	COND_CODE_1(DT_NODE_HAS_COMPAT(bc12_id, compat), \
+		    (BC12_CHIP_ENTRY(usbc_id, bc12_id, config)), ())
+
+#define BC12_CHIP_FIND(usbc_id, bc12_id)                                       \
+	CHECK_COMPAT(RT1718S_BC12_COMPAT, usbc_id, bc12_id, BC12_CHIP_RT1718S) \
+	CHECK_COMPAT(RT1739_BC12_COMPAT, usbc_id, bc12_id, BC12_CHIP_RT1739)   \
+	CHECK_COMPAT(RT9490_BC12_COMPAT, usbc_id, bc12_id, BC12_CHIP_RT9490)   \
+	CHECK_COMPAT(PI3USB9201_COMPAT, usbc_id, bc12_id, BC12_CHIP_PI3USB9201)
+
+#define BC12_CHIP(usbc_id)                           \
+	COND_CODE_1(DT_NODE_HAS_PROP(usbc_id, bc12), \
+		    (BC12_CHIP_FIND(usbc_id, DT_PHANDLE(usbc_id, bc12))), ())
+
+/* BC1.2 controllers */
+struct bc12_config bc12_ports[CHARGE_PORT_COUNT] = { DT_FOREACH_STATUS_OKAY(
+	named_usbc_port, BC12_CHIP) };
 
 #endif /* #if DT_HAS_COMPAT_STATUS_OKAY */
diff --git a/zephyr/shim/src/bc12_pi3usb9201.c b/zephyr/shim/src/bc12_pi3usb9201.c
index 3322e0770c..25d1962ff2 100644
--- a/zephyr/shim/src/bc12_pi3usb9201.c
+++ b/zephyr/shim/src/bc12_pi3usb9201.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,29 +13,35 @@
 #include "usb_charge.h"
 #include "usb_pd.h"
 #include "usbc/utils.h"
-
+#include "i2c/i2c.h"
 
 #if DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT)
 
 BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 0,
-		"No compatible BC1.2 instance found");
+	     "No compatible BC1.2 instance found");
 
-#define USBC_PORT_BC12(inst)                                                  \
-	{                                                                     \
-		.i2c_port = I2C_PORT(DT_PHANDLE(DT_DRV_INST(inst), port)),    \
-		.i2c_addr_flags = DT_STRING_UPPER_TOKEN(                      \
-					DT_DRV_INST(inst), i2c_addr_flags),   \
+#define USBC_PORT_BC12(usbc_id, bc12_id)                \
+	[USBC_PORT_NEW(usbc_id)] = {                    \
+		.i2c_port = I2C_PORT_BY_DEV(bc12_id),   \
+		.i2c_addr_flags = DT_REG_ADDR(bc12_id), \
 	},
 
+#define PI3SUSB9201_CHECK(usbc_id, bc12_id)                          \
+	COND_CODE_1(DT_NODE_HAS_COMPAT(bc12_id, pericom_pi3usb9201), \
+		    (USBC_PORT_BC12(usbc_id, bc12_id)), ())
+
+#define BC12_CHIP(usbc_id)                                                   \
+	COND_CODE_1(DT_NODE_HAS_PROP(usbc_id, bc12),                         \
+		    (PI3SUSB9201_CHECK(usbc_id, DT_PHANDLE(usbc_id, bc12))), \
+		    ())
+
 const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	DT_INST_FOREACH_STATUS_OKAY(USBC_PORT_BC12)
+	DT_FOREACH_STATUS_OKAY(named_usbc_port, BC12_CHIP)
 };
 
-static void bc12_enable_irqs(void)
-{
+static void bc12_enable_irqs(void){
 	DT_INST_FOREACH_STATUS_OKAY(BC12_GPIO_ENABLE_INTERRUPT)
-}
-DECLARE_HOOK(HOOK_INIT, bc12_enable_irqs, HOOK_PRIO_DEFAULT);
+} DECLARE_HOOK(HOOK_INIT, bc12_enable_irqs, HOOK_PRIO_DEFAULT);
 
 #if DT_INST_NODE_HAS_PROP(0, irq)
 void usb0_evt(enum gpio_signal signal)
diff --git a/zephyr/shim/src/bc12_rt9490.c b/zephyr/shim/src/bc12_rt9490.c
index abecfcfa3a..df10fb5570 100644
--- a/zephyr/shim/src/bc12_rt9490.c
+++ b/zephyr/shim/src/bc12_rt9490.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,20 +19,25 @@ static void rt9490_bc12_enable_irqs(void)
 }
 DECLARE_HOOK(HOOK_INIT, rt9490_bc12_enable_irqs, HOOK_PRIO_DEFAULT);
 
-#define GPIO_SIGNAL_FROM_INST(inst)					\
-	GPIO_SIGNAL(DT_PHANDLE(DT_INST_PHANDLE(inst, irq), irq_pin))
+#define RT9490_DISPATCH_INTERRUPT(usbc_id, bc12_id)                        \
+	IF_ENABLED(DT_NODE_HAS_PROP(bc12_id, irq),                         \
+		   (case GPIO_SIGNAL(                                      \
+			    DT_PHANDLE(DT_PHANDLE(bc12_id, irq), irq_pin)) \
+		    : rt9490_interrupt(USBC_PORT_NEW(usbc_id));            \
+		    break;))
 
-#define RT9490_DISPATCH_INTERRUPT(inst)					\
-	IF_ENABLED(DT_INST_NODE_HAS_PROP(inst, irq),			\
-		   (case GPIO_SIGNAL_FROM_INST(inst):			\
-			rt9490_interrupt(USBC_PORT_FROM_INST(inst));	\
-			break;						\
-		   ))
+#define RT9490_CHECK(usbc_id, bc12_id)                                \
+	COND_CODE_1(DT_NODE_HAS_COMPAT(bc12_id, richtek_rt9490_bc12), \
+		    (RT9490_DISPATCH_INTERRUPT(usbc_id, bc12_id)), ())
+
+#define RT9490_INTERRUPT(usbc_id)                    \
+	COND_CODE_1(DT_NODE_HAS_PROP(usbc_id, bc12), \
+		    (RT9490_CHECK(usbc_id, DT_PHANDLE(usbc_id, bc12))), ())
 
 void rt9490_bc12_dt_interrupt(enum gpio_signal signal)
 {
 	switch (signal) {
-		DT_INST_FOREACH_STATUS_OKAY(RT9490_DISPATCH_INTERRUPT);
+		DT_FOREACH_STATUS_OKAY(named_usbc_port, RT9490_INTERRUPT)
 	default:
 		break;
 	}
diff --git a/zephyr/shim/src/cbi/cbi_eeprom.c b/zephyr/shim/src/cbi/cbi_eeprom.c
index 4b9d718ef0..aa6c4e0fa1 100644
--- a/zephyr/shim/src/cbi/cbi_eeprom.c
+++ b/zephyr/shim/src/cbi/cbi_eeprom.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/shim/src/cbi/cros_cbi.c b/zephyr/shim/src/cbi/cros_cbi.c
index 7ae1fbc098..5b90f9442d 100644
--- a/zephyr/shim/src/cbi/cros_cbi.c
+++ b/zephyr/shim/src/cbi/cros_cbi.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/shim/src/cbi/cros_cbi_fw_config.c b/zephyr/shim/src/cbi/cros_cbi_fw_config.c
index e94c950a0f..6710a30726 100644
--- a/zephyr/shim/src/cbi/cros_cbi_fw_config.c
+++ b/zephyr/shim/src/cbi/cros_cbi_fw_config.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,15 +20,15 @@ LOG_MODULE_REGISTER(cros_cbi_fw_config, LOG_LEVEL_ERR);
  * Statically count the number of bits set in a 32 bit constant expression.
  */
 #define BIT_SET(v, b) ((v >> b) & 1)
-#define BIT_COUNT(v) \
+#define BIT_COUNT(v)                                                         \
 	(BIT_SET(v, 31) + BIT_SET(v, 30) + BIT_SET(v, 29) + BIT_SET(v, 28) + \
 	 BIT_SET(v, 27) + BIT_SET(v, 26) + BIT_SET(v, 25) + BIT_SET(v, 24) + \
 	 BIT_SET(v, 23) + BIT_SET(v, 22) + BIT_SET(v, 21) + BIT_SET(v, 20) + \
 	 BIT_SET(v, 19) + BIT_SET(v, 18) + BIT_SET(v, 17) + BIT_SET(v, 16) + \
 	 BIT_SET(v, 15) + BIT_SET(v, 14) + BIT_SET(v, 13) + BIT_SET(v, 12) + \
-	 BIT_SET(v, 11) + BIT_SET(v, 10) + BIT_SET(v,  9) + BIT_SET(v,  8) + \
-	 BIT_SET(v,  7) + BIT_SET(v,  6) + BIT_SET(v,  5) + BIT_SET(v,  4) + \
-	 BIT_SET(v,  3) + BIT_SET(v,  2) + BIT_SET(v,  1) + BIT_SET(v,  0))
+	 BIT_SET(v, 11) + BIT_SET(v, 10) + BIT_SET(v, 9) + BIT_SET(v, 8) +   \
+	 BIT_SET(v, 7) + BIT_SET(v, 6) + BIT_SET(v, 5) + BIT_SET(v, 4) +     \
+	 BIT_SET(v, 3) + BIT_SET(v, 2) + BIT_SET(v, 1) + BIT_SET(v, 0))
 
 /*
  * Shorthand macros to access properties on the field node.
@@ -64,7 +64,7 @@ LOG_MODULE_REGISTER(cros_cbi_fw_config, LOG_LEVEL_ERR);
  * fw_config nodes, and another for the child field nodes in each
  * of the fw_config nodes.
  */
-#define PLUS_FIELD_SIZE(inst) + DT_PROP(inst, size)
+#define PLUS_FIELD_SIZE(inst) +DT_PROP(inst, size)
 #define FIELDS_ALL_SIZE(inst) \
 	DT_FOREACH_CHILD_STATUS_OKAY(inst, PLUS_FIELD_SIZE)
 
@@ -83,23 +83,21 @@ BUILD_ASSERT(TOTAL_FW_CONFIG_NODES_SIZE <= 32,
  * total of the sizes. They should match.
  */
 #define OR_FIELD_SHIFT_MASK(id) | FW_SHIFT_MASK(id)
-#define FIELDS_ALL_BITS_SET(inst)		\
+#define FIELDS_ALL_BITS_SET(inst) \
 	DT_FOREACH_CHILD_STATUS_OKAY(inst, OR_FIELD_SHIFT_MASK)
 
 #define TOTAL_BITS_SET \
-	(0 DT_FOREACH_STATUS_OKAY(CBI_FW_CONFIG_COMPAT, \
-				  FIELDS_ALL_BITS_SET))
+	(0 DT_FOREACH_STATUS_OKAY(CBI_FW_CONFIG_COMPAT, FIELDS_ALL_BITS_SET))
 
 BUILD_ASSERT(BIT_COUNT(TOTAL_BITS_SET) == TOTAL_FW_CONFIG_NODES_SIZE,
-		       "CBI FW Config has overlapping fields");
+	     "CBI FW Config has overlapping fields");
 
 /*
  * Validation for each assigned field values.
  * The value must fit within the parent's defined size.
  */
-#define FW_VALUE_BUILD_ASSERT(inst)			\
-	BUILD_ASSERT(DT_PROP(inst, value) <		\
-		     (1 << FW_PARENT_SIZE(inst)),	\
+#define FW_VALUE_BUILD_ASSERT(inst)                                      \
+	BUILD_ASSERT(DT_PROP(inst, value) < (1 << FW_PARENT_SIZE(inst)), \
 		     "CBI FW Config value too big");
 
 DT_FOREACH_STATUS_OKAY(CBI_FW_CONFIG_VALUE_COMPAT, FW_VALUE_BUILD_ASSERT)
@@ -144,9 +142,9 @@ DT_FOREACH_STATUS_OKAY(CBI_FW_CONFIG_VALUE_COMPAT, FW_VALUE_BUILD_ASSERT)
  * The per-field case statement.
  * Extract the field value using the start and size.
  */
-#define FW_FIELD_CASE(id, cached, value)	\
-	case CBI_FW_CONFIG_ENUM(id):				\
-		*value = (cached >> FW_START(id)) & FW_MASK(id);	\
+#define FW_FIELD_CASE(id, cached, value)                         \
+	case CBI_FW_CONFIG_ENUM(id):                             \
+		*value = (cached >> FW_START(id)) & FW_MASK(id); \
 		break;
 
 /*
@@ -173,10 +171,9 @@ void cros_cbi_fw_config_init(void)
 	LOG_INF("Read CBI FW Config : 0x%08X\n", cached_fw_config);
 }
 
-static int cros_cbi_fw_config_get_field(
-				uint32_t cached_fw_config,
-				enum cbi_fw_config_field_id field_id,
-				uint32_t *value)
+static int cros_cbi_fw_config_get_field(uint32_t cached_fw_config,
+					enum cbi_fw_config_field_id field_id,
+					uint32_t *value)
 {
 	switch (field_id) {
 		/*
@@ -184,8 +181,7 @@ static int cros_cbi_fw_config_get_field(
 		 * and create cases for all of their child nodes.
 		 */
 		DT_FOREACH_STATUS_OKAY_VARGS(CBI_FW_CONFIG_COMPAT,
-					     FW_FIELD_NODES,
-					     cached_fw_config,
+					     FW_FIELD_NODES, cached_fw_config,
 					     value)
 	default:
 		return -EINVAL;
diff --git a/zephyr/shim/src/cbi/cros_cbi_ssfc.c b/zephyr/shim/src/cbi/cros_cbi_ssfc.c
index a2dc3ccf0a..eb0f69b1cb 100644
--- a/zephyr/shim/src/cbi/cros_cbi_ssfc.c
+++ b/zephyr/shim/src/cbi/cros_cbi_ssfc.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -129,9 +129,8 @@ BUILD_ASSERT(sizeof(union cbi_ssfc) == sizeof(uint32_t),
 
 DT_INST_FOREACH_STATUS_OKAY(CBI_SSFC_VALUE_BUILD_ASSERT)
 
-static const uint8_t ssfc_values[] = {
-	DT_INST_FOREACH_STATUS_OKAY(CBI_SSFC_VALUE_ARRAY)
-};
+static const uint8_t ssfc_values[] = { DT_INST_FOREACH_STATUS_OKAY(
+	CBI_SSFC_VALUE_ARRAY) };
 
 static union cbi_ssfc cached_ssfc;
 
diff --git a/zephyr/shim/src/charger.c b/zephyr/shim/src/charger.c
index 08aa121a19..35ede5a8f7 100644
--- a/zephyr/shim/src/charger.c
+++ b/zephyr/shim/src/charger.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,33 +10,51 @@
 #include "charger/chg_isl9241.h"
 #include "charger/chg_rt9490.h"
 #include "charger/chg_sm5803.h"
+#include "usbc/utils.h"
 
-#define CHG_CHIP(id, fn) [DT_REG_ADDR(DT_PARENT(id))] = fn(id)
+#define CHG_CHIP_ENTRY(usbc_id, chg_id, config_fn) \
+	[USBC_PORT_NEW(usbc_id)] = config_fn(chg_id)
+
+#define CHECK_COMPAT(compat, usbc_id, chg_id, config_fn) \
+	COND_CODE_1(DT_NODE_HAS_COMPAT(chg_id, compat),  \
+		    (CHG_CHIP_ENTRY(usbc_id, chg_id, config_fn)), ())
+
+#define CHG_CHIP_FIND(usbc_id, chg_id)                                         \
+	CHECK_COMPAT(BQ25710_CHG_COMPAT, usbc_id, chg_id, CHG_CONFIG_BQ25710)  \
+	CHECK_COMPAT(ISL923X_CHG_COMPAT, usbc_id, chg_id, CHG_CONFIG_ISL923X)  \
+	CHECK_COMPAT(ISL923X_EMUL_COMPAT, usbc_id, chg_id, CHG_CONFIG_ISL923X) \
+	CHECK_COMPAT(ISL9241_CHG_COMPAT, usbc_id, chg_id, CHG_CONFIG_ISL9241)  \
+	CHECK_COMPAT(RT9490_CHG_COMPAT, usbc_id, chg_id, CHG_CONFIG_RT9490)    \
+	CHECK_COMPAT(RT9490_EMUL_COMPAT, usbc_id, chg_id, CHG_CONFIG_RT9490)   \
+	CHECK_COMPAT(SM5803_CHG_COMPAT, usbc_id, chg_id, CHG_CONFIG_SM5803)
+
+#define CHG_CHIP(usbc_id)                           \
+	COND_CODE_1(DT_NODE_HAS_PROP(usbc_id, chg), \
+		    (CHG_CHIP_FIND(usbc_id, DT_PHANDLE(usbc_id, chg))), ())
+
+#define CHG_CHIP_ALT(usbc_id)                                               \
+	COND_CODE_1(DT_NODE_HAS_PROP(usbc_id, chg_alt),                     \
+		    (CHG_CHIP_FIND(usbc_id, DT_PHANDLE(usbc_id, chg_alt))), \
+		    ())
+
+#define MAYBE_CONST \
+	COND_CODE_1(CONFIG_PLATFORM_EC_CHARGER_RUNTIME_CONFIG, (), (const))
 
 /* Charger chips */
-#ifndef CONFIG_PLATFORM_EC_CHARGER_RUNTIME_CONFIG
-const struct charger_config_t chg_chips[] = {
-#else
-struct charger_config_t chg_chips[] = {
-#endif
-	DT_FOREACH_STATUS_OKAY_VARGS(BQ25710_CHG_COMPAT, CHG_CHIP,
-				     CHG_CONFIG_BQ25710)
-	DT_FOREACH_STATUS_OKAY_VARGS(ISL923X_CHG_COMPAT, CHG_CHIP,
-				     CHG_CONFIG_ISL923X)
-	DT_FOREACH_STATUS_OKAY_VARGS(ISL9241_CHG_COMPAT, CHG_CHIP,
-				     CHG_CONFIG_ISL9241)
-	DT_FOREACH_STATUS_OKAY_VARGS(RT9490_CHG_COMPAT, CHG_CHIP,
-				     CHG_CONFIG_RT9490)
-	DT_FOREACH_STATUS_OKAY_VARGS(SM5803_CHG_COMPAT, CHG_CHIP,
-				     CHG_CONFIG_SM5803)
-};
+MAYBE_CONST struct charger_config_t chg_chips[] = { DT_FOREACH_STATUS_OKAY(
+	named_usbc_port, CHG_CHIP) };
+
+/* Alternate options */
+const struct charger_config_t chg_chips_alt[] = { DT_FOREACH_STATUS_OKAY(
+	named_usbc_port, CHG_CHIP_ALT) };
 
 #ifdef CONFIG_PLATFORM_EC_CHARGER_SINGLE_CHIP
 BUILD_ASSERT(ARRAY_SIZE(chg_chips) == 1,
-	"For the CHARGER_SINGLE_CHIP config, the number of defined charger "
-	"chips must equal 1.");
+	     "For the CHARGER_SINGLE_CHIP config, the number of defined charger "
+	     "chips must equal 1.");
 #else
-BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CONFIG_USB_PD_PORT_MAX_COUNT,
+BUILD_ASSERT(
+	ARRAY_SIZE(chg_chips) == CONFIG_USB_PD_PORT_MAX_COUNT,
 	"For the OCPC config, the number of defined charger chips must equal "
 	"the number of USB-C ports.");
 #endif
diff --git a/zephyr/shim/src/chipset_api.c b/zephyr/shim/src/chipset_api.c
index 3bfa420980..6c48719a7f 100644
--- a/zephyr/shim/src/chipset_api.c
+++ b/zephyr/shim/src/chipset_api.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -38,7 +38,9 @@ void chipset_reset(enum chipset_shutdown_reason reason)
 /* TODO: b/214509787
  * To be added later when this functionality is implemented in ap_pwrseq.
  */
-void chipset_throttle_cpu(int throttle) { }
+void chipset_throttle_cpu(int throttle)
+{
+}
 
 void init_reset_log(void)
 {
diff --git a/zephyr/shim/src/chipset_state_check.h b/zephyr/shim/src/chipset_state_check.h
index 879f700d89..2d10b2ce4a 100644
--- a/zephyr/shim/src/chipset_state_check.h
+++ b/zephyr/shim/src/chipset_state_check.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,19 +9,12 @@
 #include "chipset.h"
 #include "ap_power/ap_power_interface.h"
 
-BUILD_ASSERT((int)AP_POWER_STATE_HARD_OFF ==
-				(int)CHIPSET_STATE_HARD_OFF);
-BUILD_ASSERT((int)AP_POWER_STATE_SOFT_OFF ==
-				(int)CHIPSET_STATE_SOFT_OFF);
-BUILD_ASSERT((int)AP_POWER_STATE_SUSPEND ==
-				(int)CHIPSET_STATE_SUSPEND);
-BUILD_ASSERT((int)AP_POWER_STATE_ON ==
-				(int)CHIPSET_STATE_ON);
-BUILD_ASSERT((int)AP_POWER_STATE_STANDBY ==
-				(int)CHIPSET_STATE_STANDBY);
-BUILD_ASSERT((int)AP_POWER_STATE_ANY_OFF ==
-				(int)CHIPSET_STATE_ANY_OFF);
-BUILD_ASSERT((int)AP_POWER_STATE_ANY_SUSPEND ==
-				(int)CHIPSET_STATE_ANY_SUSPEND);
+BUILD_ASSERT((int)AP_POWER_STATE_HARD_OFF == (int)CHIPSET_STATE_HARD_OFF);
+BUILD_ASSERT((int)AP_POWER_STATE_SOFT_OFF == (int)CHIPSET_STATE_SOFT_OFF);
+BUILD_ASSERT((int)AP_POWER_STATE_SUSPEND == (int)CHIPSET_STATE_SUSPEND);
+BUILD_ASSERT((int)AP_POWER_STATE_ON == (int)CHIPSET_STATE_ON);
+BUILD_ASSERT((int)AP_POWER_STATE_STANDBY == (int)CHIPSET_STATE_STANDBY);
+BUILD_ASSERT((int)AP_POWER_STATE_ANY_OFF == (int)CHIPSET_STATE_ANY_OFF);
+BUILD_ASSERT((int)AP_POWER_STATE_ANY_SUSPEND == (int)CHIPSET_STATE_ANY_SUSPEND);
 
 #endif /* __CHIPSET_STATE_CHECK_H__ */
diff --git a/zephyr/shim/src/console.c b/zephyr/shim/src/console.c
index f8051d8638..2d0476149c 100644
--- a/zephyr/shim/src/console.c
+++ b/zephyr/shim/src/console.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,9 +14,15 @@
 #include <string.h>
 #include <zephyr/sys/printk.h>
 #include <zephyr/sys/ring_buffer.h>
-#include <zephyr/zephyr.h>
+#include <zephyr/kernel.h>
 #include <zephyr/logging/log.h>
 
+/*
+ * TODO(b/238433667): Include EC printf functions
+ * (crec_vsnprintf/crec_snprintf) until we switch to the standard
+ * vsnprintf/snprintf.
+ */
+#include "builtin/stdio.h"
 #include "console.h"
 #include "printf.h"
 #include "task.h"
@@ -34,6 +40,9 @@
 #error Must select only one shell backend
 #endif
 
+BUILD_ASSERT(EC_TASK_PRIORITY(EC_SHELL_PRIO) == CONFIG_SHELL_THREAD_PRIORITY,
+	     "EC_SHELL_PRIO does not match CONFIG_SHELL_THREAD_PRIORITY.");
+
 LOG_MODULE_REGISTER(shim_console, LOG_LEVEL_ERR);
 
 static const struct device *uart_shell_dev =
@@ -47,6 +56,8 @@ static struct k_poll_signal shell_init_signal;
  * (which requires locking the shell).
  */
 static bool shell_stopped;
+
+#if defined(CONFIG_UART_INTERRUPT_DRIVEN)
 RING_BUF_DECLARE(rx_buffer, CONFIG_UART_RX_BUF_SIZE);
 
 static void uart_rx_handle(const struct device *dev)
@@ -81,10 +92,12 @@ static void uart_callback(const struct device *dev, void *user_data)
 	if (uart_irq_rx_ready(dev))
 		uart_rx_handle(dev);
 }
+#endif
 
 static void shell_uninit_callback(const struct shell *shell, int res)
 {
 	if (!res) {
+#if defined(CONFIG_UART_INTERRUPT_DRIVEN)
 		/* Set the new callback */
 		uart_irq_callback_user_data_set(uart_shell_dev, uart_callback,
 						NULL);
@@ -97,6 +110,7 @@ static void shell_uninit_callback(const struct shell *shell, int res)
 
 		/* Enable RX interrupts */
 		uart_irq_rx_enable(uart_shell_dev);
+#endif
 	}
 
 	/* Notify the uninit signal that we finished */
@@ -117,9 +131,11 @@ int uart_shell_stop(void)
 	/* Clear all pending input */
 	uart_clear_input();
 
+#if defined(CONFIG_UART_INTERRUPT_DRIVEN)
 	/* Disable RX and TX interrupts */
 	uart_irq_rx_disable(uart_shell_dev);
 	uart_irq_tx_disable(uart_shell_dev);
+#endif
 
 	/* Initialize the uninit signal */
 	k_poll_signal_init(&shell_uninit_signal);
@@ -150,8 +166,8 @@ static void shell_init_from_work(struct k_work *work)
 #endif
 
 	/* Initialize the shell and re-enable both RX and TX */
-	shell_init(shell_zephyr, uart_shell_dev,
-		   shell_cfg_flags, log_backend, level);
+	shell_init(shell_zephyr, uart_shell_dev, shell_cfg_flags, log_backend,
+		   level);
 
 	/*
 	 * shell_init() always resets the priority back to the default.
@@ -160,8 +176,10 @@ static void shell_init_from_work(struct k_work *work)
 	k_thread_priority_set(shell_zephyr->ctx->tid,
 			      EC_TASK_PRIORITY(EC_SHELL_PRIO));
 
+#if defined(CONFIG_UART_INTERRUPT_DRIVEN)
 	uart_irq_rx_enable(uart_shell_dev);
 	uart_irq_tx_enable(uart_shell_dev);
+#endif
 
 	/* Notify the init signal that initialization is complete */
 	k_poll_signal_raise(&shell_init_signal, 0);
@@ -174,9 +192,11 @@ void uart_shell_start(void)
 		K_POLL_TYPE_SIGNAL, K_POLL_MODE_NOTIFY_ONLY,
 		&shell_init_signal);
 
+#if defined(CONFIG_UART_INTERRUPT_DRIVEN)
 	/* Disable RX and TX interrupts */
 	uart_irq_rx_disable(uart_shell_dev);
 	uart_irq_tx_disable(uart_shell_dev);
+#endif
 
 	/* Initialize k_work to call shell init (this makes it thread safe) */
 	k_work_init(&shell_init_work, shell_init_from_work);
@@ -193,7 +213,7 @@ void uart_shell_start(void)
 }
 
 #ifdef CONFIG_SHELL_HELP
-static void print_console_help(char *name,
+static void print_console_help(const char *name,
 			       const struct zephyr_console_command *command)
 {
 	if (command->help)
@@ -204,7 +224,7 @@ static void print_console_help(char *name,
 #endif
 
 int zshim_run_ec_console_command(const struct zephyr_console_command *command,
-				 size_t argc, char **argv)
+				 size_t argc, const char **argv)
 {
 	int ret;
 
@@ -245,7 +265,7 @@ int zshim_run_ec_console_command(const struct zephyr_console_command *command,
 #if defined(CONFIG_CONSOLE_CHANNEL) && DT_NODE_EXISTS(DT_PATH(ec_console))
 #define EC_CONSOLE DT_PATH(ec_console)
 
-static const char * const disabled_channels[] = DT_PROP(EC_CONSOLE, disabled);
+static const char *const disabled_channels[] = DT_PROP(EC_CONSOLE, disabled);
 static const size_t disabled_channel_count = DT_PROP_LEN(EC_CONSOLE, disabled);
 static int init_ec_console(const struct device *unused)
 {
@@ -253,20 +273,22 @@ static int init_ec_console(const struct device *unused)
 		console_channel_disable(disabled_channels[i]);
 
 	return 0;
-} SYS_INIT(init_ec_console, PRE_KERNEL_1, 50);
+}
+SYS_INIT(init_ec_console, PRE_KERNEL_1, 50);
 #endif /* CONFIG_CONSOLE_CHANNEL && DT_NODE_EXISTS(DT_PATH(ec_console)) */
 
 static int init_ec_shell(const struct device *unused)
 {
 #if defined(CONFIG_SHELL_BACKEND_SERIAL)
-		shell_zephyr = shell_backend_uart_get_ptr();
+	shell_zephyr = shell_backend_uart_get_ptr();
 #elif defined(CONFIG_SHELL_BACKEND_DUMMY) /* nocheck */
-		shell_zephyr = shell_backend_dummy_get_ptr(); /* nocheck */
+	shell_zephyr = shell_backend_dummy_get_ptr(); /* nocheck */
 #else
 #error A shell backend must be enabled
 #endif
 	return 0;
-} SYS_INIT(init_ec_shell, PRE_KERNEL_1, 50);
+}
+SYS_INIT(init_ec_shell, PRE_KERNEL_1, 50);
 
 #ifdef TEST_BUILD
 const struct shell *get_ec_shell(void)
@@ -305,24 +327,39 @@ void uart_flush_output(void)
 
 void uart_tx_flush(void)
 {
+#if defined(CONFIG_UART_INTERRUPT_DRIVEN)
 	while (!uart_irq_tx_complete(uart_shell_dev))
 		;
+#endif
 }
 
 int uart_getc(void)
 {
+#if defined(CONFIG_UART_INTERRUPT_DRIVEN)
 	uint8_t c;
 
 	if (ring_buf_get(&rx_buffer, &c, 1)) {
 		return c;
 	}
 	return -1;
+#else
+	uint8_t c;
+	int rv;
+
+	rv = uart_poll_in(uart_shell_dev, &c);
+	if (rv) {
+		return rv;
+	}
+	return c;
+#endif
 }
 
 void uart_clear_input(void)
 {
+#if defined(CONFIG_UART_INTERRUPT_DRIVEN)
 	/* Reset the input ring buffer */
 	ring_buf_reset(&rx_buffer);
+#endif
 }
 
 static void handle_sprintf_rv(int rv, size_t *len)
@@ -345,7 +382,7 @@ static void zephyr_print(const char *buff, size_t size)
 	 * locked in ISRs.
 	 */
 	if (k_is_in_isr() || shell_stopped ||
-			shell_zephyr->ctx->state != SHELL_STATE_ACTIVE) {
+	    shell_zephyr->ctx->state != SHELL_STATE_ACTIVE) {
 		printk("%s", buff);
 	} else {
 		shell_fprintf(shell_zephyr, SHELL_NORMAL, "%s", buff);
@@ -403,18 +440,24 @@ int cprints(enum console_channel channel, const char *format, ...)
 	if (console_channel_is_disabled(channel))
 		return EC_SUCCESS;
 
-	rv = crec_snprintf(buff, CONFIG_SHELL_PRINTF_BUFF_SIZE, "[%pT ",
-			 PRINTF_TIMESTAMP_NOW);
+	buff[0] = '[';
+	len = 1;
+
+	rv = snprintf_timestamp_now(buff + len, sizeof(buff) - len);
+	handle_sprintf_rv(rv, &len);
+
+	rv = crec_snprintf(buff + len, CONFIG_SHELL_PRINTF_BUFF_SIZE - len,
+			   " ");
 	handle_sprintf_rv(rv, &len);
 
 	va_start(args, format);
 	rv = crec_vsnprintf(buff + len, CONFIG_SHELL_PRINTF_BUFF_SIZE - len,
-			  format, args);
+			    format, args);
 	va_end(args);
 	handle_sprintf_rv(rv, &len);
 
 	rv = crec_snprintf(buff + len, CONFIG_SHELL_PRINTF_BUFF_SIZE - len,
-			 "]\n");
+			   "]\n");
 	handle_sprintf_rv(rv, &len);
 
 	zephyr_print(buff, len);
diff --git a/zephyr/shim/src/console_buffer.c b/zephyr/shim/src/console_buffer.c
index aaeb6dae68..dad0031267 100644
--- a/zephyr/shim/src/console_buffer.c
+++ b/zephyr/shim/src/console_buffer.c
@@ -1,10 +1,9 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include <zephyr/kernel.h>
-#include <zephyr/zephyr.h>
 
 #include "common.h"
 #include "console.h"
@@ -24,7 +23,7 @@ static inline uint32_t next_idx(uint32_t cur_idx)
 
 K_MUTEX_DEFINE(console_write_lock);
 
-void console_buf_notify_chars(const char *s, size_t len)
+size_t console_buf_notify_chars(const char *s, size_t len)
 {
 	/*
 	 * This is just notifying of console characters for debugging
@@ -32,12 +31,14 @@ void console_buf_notify_chars(const char *s, size_t len)
 	 * then just drop the string.
 	 */
 	if (k_mutex_lock(&console_write_lock, K_NO_WAIT))
-		return;
+		return 0;
 	/* We got the mutex. */
-	while (len--) {
+	for (size_t i = 0; i < len; i++) {
 		/* Don't copy null byte into buffer */
-		if (!(*s))
+		if (!(*s)) {
+			s++;
 			continue;
+		}
 
 		uint32_t new_tail = next_idx(tail_idx);
 
@@ -47,11 +48,9 @@ void console_buf_notify_chars(const char *s, size_t len)
 		if (new_tail == head_idx)
 			head_idx = next_idx(head_idx);
 		if (new_tail == previous_snapshot_idx)
-			previous_snapshot_idx =
-				next_idx(previous_snapshot_idx);
+			previous_snapshot_idx = next_idx(previous_snapshot_idx);
 		if (new_tail == current_snapshot_idx)
-			current_snapshot_idx =
-				next_idx(current_snapshot_idx);
+			current_snapshot_idx = next_idx(current_snapshot_idx);
 		if (new_tail == read_next_idx)
 			read_next_idx = next_idx(read_next_idx);
 
@@ -59,6 +58,7 @@ void console_buf_notify_chars(const char *s, size_t len)
 		tail_idx = new_tail;
 	}
 	k_mutex_unlock(&console_write_lock);
+	return len;
 }
 
 enum ec_status uart_console_read_buffer_init(void)
@@ -118,6 +118,7 @@ int uart_console_read_buffer(uint8_t type, char *dest, uint16_t dest_size,
 	if (*head == current_snapshot_idx) {
 		/* No new data, return empty response */
 		k_mutex_unlock(&console_write_lock);
+		*write_count_out = 0;
 		return EC_RES_SUCCESS;
 	}
 
diff --git a/zephyr/shim/src/crc.c b/zephyr/shim/src/crc.c
index 0c5a81a4dd..f8ce335029 100644
--- a/zephyr/shim/src/crc.c
+++ b/zephyr/shim/src/crc.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/shim/src/espi.c b/zephyr/shim/src/espi.c
index 74f6b70f42..d6f6bed314 100644
--- a/zephyr/shim/src/espi.c
+++ b/zephyr/shim/src/espi.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,10 +10,10 @@
 #include <zephyr/logging/log.h>
 #include <zephyr/kernel.h>
 #include <stdint.h>
-#include <zephyr/zephyr.h>
 
 #include <ap_power/ap_power.h>
 #include <ap_power/ap_power_events.h>
+#include <ap_power/ap_power_espi.h>
 #include "acpi.h"
 #include "chipset.h"
 #include "common.h"
@@ -28,10 +28,29 @@
 #include "timer.h"
 #include "zephyr_espi_shim.h"
 
-#define VWIRE_PULSE_TRIGGER_TIME CONFIG_PLATFORM_EC_ESPI_DEFAULT_VW_WIDTH_US
+#define VWIRE_PULSE_TRIGGER_TIME \
+	CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US
 
 LOG_MODULE_REGISTER(espi_shim, CONFIG_ESPI_LOG_LEVEL);
 
+/*
+ * Some functions are compiled depending on combinations of
+ * CONFIG_PLATFORM_EC_POWERSEQ, CONFIG_AP_PWRSEQ and
+ * CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK.
+ *
+ * Tests are compiled without CONFIG_PLATFORM_EC_POWERSEQ and
+ * CONFIG_AP_PWRSEQ defined, but use the lpc functions.
+ *
+ * Legacy vwire power signal handling is required
+ * by CONFIG_PLATFORM_EC_POWERSEQ.
+ *
+ * CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK is used to handle
+ * the PLTRST# vwire signal separate to the legacy power signal handling.
+ *
+ * Where !defined(CONFIG_AP_PWRSEQ) is used, the code is required either
+ * by the tests, or by the legacy power signal handling.
+ */
+
 /* host command packet handler structure */
 static struct host_packet lpc_packet;
 /*
@@ -95,6 +114,7 @@ static enum espi_vwire_signal signal_to_zephyr_vwire(enum espi_vw_signal signal)
 	}
 }
 
+#if defined(CONFIG_PLATFORM_EC_POWERSEQ)
 /* Translate a Zephyr vwire to a platform/ec signal */
 static enum espi_vw_signal zephyr_vwire_to_signal(enum espi_vwire_signal vwire)
 {
@@ -105,6 +125,7 @@ static enum espi_vw_signal zephyr_vwire_to_signal(enum espi_vwire_signal vwire)
 		return -1;
 	}
 }
+#endif /* defined(CONFIG_PLATFORM_EC_POWERSEQ) */
 
 /*
  * Bit field for each signal which can have an interrupt enabled.
@@ -126,22 +147,12 @@ static uint32_t signal_to_interrupt_bit(enum espi_vw_signal signal)
 	}
 }
 
-/* Callback for vwire received */
-static void espi_vwire_handler(const struct device *dev,
-			       struct espi_callback *cb,
-			       struct espi_event event)
-{
-	int ec_signal = zephyr_vwire_to_signal(event.evt_details);
-
-	if (IS_ENABLED(CONFIG_PLATFORM_EC_POWERSEQ) &&
-	    (signal_interrupt_enabled & signal_to_interrupt_bit(ec_signal))) {
-		power_signal_interrupt(ec_signal);
-	}
-}
-
 #endif /* !defined(CONFIG_AP_PWRSEQ) */
 
 #ifdef CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK
+/*
+ * Deferred handler for PLTRST processing.
+ */
 static void espi_chipset_reset(void)
 {
 	if (IS_ENABLED(CONFIG_AP_PWRSEQ)) {
@@ -151,16 +162,35 @@ static void espi_chipset_reset(void)
 	}
 }
 DECLARE_DEFERRED(espi_chipset_reset);
+#endif /* CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK */
 
-/* Callback for reset */
-static void espi_reset_handler(const struct device *dev,
+/*
+ * Callback for vwire received.
+ * PLTRST (platform reset) is handled specially by
+ * invoking HOOK_CHIPSET_RESET.
+ */
+#if defined(CONFIG_PLATFORM_EC_POWERSEQ) || \
+	defined(CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK)
+static void espi_vwire_handler(const struct device *dev,
 			       struct espi_callback *cb,
 			       struct espi_event event)
 {
-	hook_call_deferred(&espi_chipset_reset_data, MSEC);
+#if defined(CONFIG_PLATFORM_EC_POWERSEQ)
+	int ec_signal = zephyr_vwire_to_signal(event.evt_details);
 
+	if (signal_interrupt_enabled & signal_to_interrupt_bit(ec_signal)) {
+		power_signal_interrupt(ec_signal);
+	}
+#endif
+#if defined(CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK)
+	/* If PLTRST# asserted (low) then send reset hook */
+	if (event.evt_details == ESPI_VWIRE_SIGNAL_PLTRST &&
+	    event.evt_data == 0) {
+		hook_call_deferred(&espi_chipset_reset_data, MSEC);
+	}
+#endif
 }
-#endif /* CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK */
+#endif
 
 #define espi_dev DEVICE_DT_GET(DT_CHOSEN(cros_ec_espi))
 
@@ -289,46 +319,76 @@ void lpc_update_host_event_status(void)
 	uint32_t status;
 	int need_sci = 0;
 	int need_smi = 0;
+	int rv;
 
 	if (!init_done)
 		return;
 
 	/* Disable PMC1 interrupt while updating status register */
 	enable = 0;
-	espi_write_lpc_request(espi_dev, ECUSTOM_HOST_SUBS_INTERRUPT_EN,
-			       &enable);
-
-	espi_read_lpc_request(espi_dev, EACPI_READ_STS, &status);
-	if (lpc_get_host_events_by_type(LPC_HOST_EVENT_SMI)) {
-		/* Only generate SMI for first event */
-		if (!(status & EC_LPC_STATUS_SMI_PENDING))
-			need_smi = 1;
+	rv = espi_write_lpc_request(espi_dev, ECUSTOM_HOST_SUBS_INTERRUPT_EN,
+				    &enable);
+	if (rv) {
+		LOG_ERR("ESPI write failed: "
+			"ECUSTOM_HOST_SUBS_INTERRUPT_EN = %d",
+			rv);
+		return;
+	}
 
-		status |= EC_LPC_STATUS_SMI_PENDING;
-		espi_write_lpc_request(espi_dev, EACPI_WRITE_STS, &status);
+	rv = espi_read_lpc_request(espi_dev, EACPI_READ_STS, &status);
+	if (rv) {
+		LOG_ERR("ESPI read failed: EACPI_READ_STS = %d", rv);
 	} else {
-		status &= ~EC_LPC_STATUS_SMI_PENDING;
-		espi_write_lpc_request(espi_dev, EACPI_WRITE_STS, &status);
+		if (lpc_get_host_events_by_type(LPC_HOST_EVENT_SMI)) {
+			/* Only generate SMI for first event */
+			if (!(status & EC_LPC_STATUS_SMI_PENDING))
+				need_smi = 1;
+
+			status |= EC_LPC_STATUS_SMI_PENDING;
+			rv = espi_write_lpc_request(espi_dev, EACPI_WRITE_STS,
+						    &status);
+		} else {
+			status &= ~EC_LPC_STATUS_SMI_PENDING;
+			rv = espi_write_lpc_request(espi_dev, EACPI_WRITE_STS,
+						    &status);
+		}
+		if (rv) {
+			LOG_ERR("ESPI write failed: EACPI_WRITE_STS = %d", rv);
+		}
 	}
 
-	espi_read_lpc_request(espi_dev, EACPI_READ_STS, &status);
-	if (lpc_get_host_events_by_type(LPC_HOST_EVENT_SCI)) {
-		/* Generate SCI for every event */
-		need_sci = 1;
-
-		status |= EC_LPC_STATUS_SCI_PENDING;
-		espi_write_lpc_request(espi_dev, EACPI_WRITE_STS, &status);
+	rv = espi_read_lpc_request(espi_dev, EACPI_READ_STS, &status);
+	if (rv) {
+		LOG_ERR("ESPI read failed: EACPI_READ_STS = %d", rv);
 	} else {
-		status &= ~EC_LPC_STATUS_SCI_PENDING;
-		espi_write_lpc_request(espi_dev, EACPI_WRITE_STS, &status);
+		if (lpc_get_host_events_by_type(LPC_HOST_EVENT_SCI)) {
+			/* Generate SCI for every event */
+			need_sci = 1;
+
+			status |= EC_LPC_STATUS_SCI_PENDING;
+			rv = espi_write_lpc_request(espi_dev, EACPI_WRITE_STS,
+						    &status);
+		} else {
+			status &= ~EC_LPC_STATUS_SCI_PENDING;
+			rv = espi_write_lpc_request(espi_dev, EACPI_WRITE_STS,
+						    &status);
+		}
+		if (rv) {
+			LOG_ERR("ESPI write failed: EACPI_WRITE_STS = %d", rv);
+		}
 	}
 
 	*(host_event_t *)host_get_memmap(EC_MEMMAP_HOST_EVENTS) =
 		lpc_get_host_events();
 
 	enable = 1;
-	espi_write_lpc_request(espi_dev, ECUSTOM_HOST_SUBS_INTERRUPT_EN,
-			       &enable);
+	rv = espi_write_lpc_request(espi_dev, ECUSTOM_HOST_SUBS_INTERRUPT_EN,
+				    &enable);
+	if (rv) {
+		LOG_ERR("ESPI write failed: "
+			"ECUSTOM_HOST_SUBS_INTERRUPT_EN = %d",
+			rv);
+	}
 
 	/* Process the wake events. */
 	lpc_update_wake(lpc_get_host_events_by_type(LPC_HOST_EVENT_WAKE));
@@ -362,19 +422,30 @@ static void handle_acpi_write(uint32_t data)
 	uint8_t value, result;
 	uint8_t is_cmd = is_acpi_command(data);
 	uint32_t status;
+	int rv;
 
 	value = get_acpi_value(data);
 
 	/* Handle whatever this was. */
 	if (acpi_ap_to_ec(is_cmd, value, &result)) {
 		data = result;
-		espi_write_lpc_request(espi_dev, EACPI_WRITE_CHAR, &data);
+		rv = espi_write_lpc_request(espi_dev, EACPI_WRITE_CHAR, &data);
+		if (rv) {
+			LOG_ERR("ESPI write failed: EACPI_WRITE_CHAR = %d", rv);
+		}
 	}
 
 	/* Clear processing flag */
-	espi_read_lpc_request(espi_dev, EACPI_READ_STS, &status);
-	status &= ~EC_LPC_STATUS_PROCESSING;
-	espi_write_lpc_request(espi_dev, EACPI_WRITE_STS, &status);
+	rv = espi_read_lpc_request(espi_dev, EACPI_READ_STS, &status);
+	if (rv) {
+		LOG_ERR("ESPI read failed: EACPI_READ_STS = %d", rv);
+	} else {
+		status &= ~EC_LPC_STATUS_PROCESSING;
+		rv = espi_write_lpc_request(espi_dev, EACPI_WRITE_STS, &status);
+		if (rv) {
+			LOG_ERR("ESPI write failed: EACPI_WRITE_STS = %d", rv);
+		}
+	}
 
 	/*
 	 * ACPI 5.0-12.6.1: Generate SCI for Input Buffer Empty / Output Buffer
@@ -386,17 +457,24 @@ static void handle_acpi_write(uint32_t data)
 static void lpc_send_response_packet(struct host_packet *pkt)
 {
 	uint32_t data;
+	int rv;
 
 	/* TODO(b/176523211): check whether add EC_RES_IN_PROGRESS handle */
 
 	/* Write result to the data byte.  This sets the TOH status bit. */
 	data = pkt->driver_result;
-	espi_write_lpc_request(espi_dev, ECUSTOM_HOST_CMD_SEND_RESULT, &data);
+	rv = espi_write_lpc_request(espi_dev, ECUSTOM_HOST_CMD_SEND_RESULT,
+				    &data);
+	if (rv) {
+		LOG_ERR("ESPI write failed: ECUSTOM_HOST_CMD_SEND_RESULT = %d",
+			rv);
+	}
 }
 
 static void handle_host_write(uint32_t data)
 {
 	uint32_t shm_mem_host_cmd;
+	int rv;
 
 	if (EC_COMMAND_PROTOCOL_3 != (data & 0xff)) {
 		LOG_ERR("Don't support this version of the host command");
@@ -404,9 +482,12 @@ static void handle_host_write(uint32_t data)
 		return;
 	}
 
-	espi_read_lpc_request(espi_dev, ECUSTOM_HOST_CMD_GET_PARAM_MEMORY,
-			      &shm_mem_host_cmd);
-
+	rv = espi_read_lpc_request(espi_dev, ECUSTOM_HOST_CMD_GET_PARAM_MEMORY,
+				   &shm_mem_host_cmd);
+	if (rv) {
+		LOG_ERR("ESPI read failed: EACPI_READ_STS = %d", rv);
+		return;
+	}
 	lpc_packet.send_response = lpc_send_response_packet;
 
 	lpc_packet.request = (const void *)shm_mem_host_cmd;
@@ -428,17 +509,35 @@ static void handle_host_write(uint32_t data)
 void lpc_set_acpi_status_mask(uint8_t mask)
 {
 	uint32_t status;
-	espi_read_lpc_request(espi_dev, EACPI_READ_STS, &status);
+	int rv;
+
+	rv = espi_read_lpc_request(espi_dev, EACPI_READ_STS, &status);
+	if (rv) {
+		LOG_ERR("ESPI read failed: EACPI_READ_STS = %d", rv);
+		return;
+	}
 	status |= mask;
-	espi_write_lpc_request(espi_dev, EACPI_WRITE_STS, &status);
+	rv = espi_write_lpc_request(espi_dev, EACPI_WRITE_STS, &status);
+	if (rv) {
+		LOG_ERR("ESPI write failed: EACPI_WRITE_STS = %d", rv);
+	}
 }
 
 void lpc_clear_acpi_status_mask(uint8_t mask)
 {
 	uint32_t status;
-	espi_read_lpc_request(espi_dev, EACPI_READ_STS, &status);
+	int rv;
+
+	rv = espi_read_lpc_request(espi_dev, EACPI_READ_STS, &status);
+	if (rv) {
+		LOG_ERR("ESPI read failed: EACPI_READ_STS = %d", rv);
+		return;
+	}
 	status &= ~mask;
-	espi_write_lpc_request(espi_dev, EACPI_WRITE_STS, &status);
+	rv = espi_write_lpc_request(espi_dev, EACPI_WRITE_STS, &status);
+	if (rv) {
+		LOG_ERR("ESPI write failed: EACPI_WRITE_STS = %d", rv);
+	}
 }
 
 /* Get protocol information */
@@ -463,27 +562,44 @@ DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, lpc_get_protocol_info,
  * This function is needed only for the obsolete platform which uses the GPIO
  * for KBC's IRQ.
  */
-void lpc_keyboard_resume_irq(void) {}
+void lpc_keyboard_resume_irq(void)
+{
+}
 
 void lpc_keyboard_clear_buffer(void)
 {
+	int rv;
 	/* Clear OBF flag in host STATUS and HIKMST regs */
-	espi_write_lpc_request(espi_dev, E8042_CLEAR_OBF, 0);
+	rv = espi_write_lpc_request(espi_dev, E8042_CLEAR_OBF, 0);
+	if (rv) {
+		LOG_ERR("ESPI write failed: E8042_CLEAR_OBF = %d", rv);
+	}
 }
+
 int lpc_keyboard_has_char(void)
 {
 	uint32_t status;
+	int rv;
 
 	/* if OBF bit is '1', that mean still have a data in DBBOUT */
-	espi_read_lpc_request(espi_dev, E8042_OBF_HAS_CHAR, &status);
+	rv = espi_read_lpc_request(espi_dev, E8042_OBF_HAS_CHAR, &status);
+	if (rv) {
+		LOG_ERR("ESPI read failed: E8042_OBF_HAS_CHAR = %d", rv);
+		return 0;
+	}
 	return status;
 }
 
 void lpc_keyboard_put_char(uint8_t chr, int send_irq)
 {
 	uint32_t kb_char = chr;
+	int rv;
 
-	espi_write_lpc_request(espi_dev, E8042_WRITE_KB_CHAR, &kb_char);
+	rv = espi_write_lpc_request(espi_dev, E8042_WRITE_KB_CHAR, &kb_char);
+	if (rv) {
+		LOG_ERR("ESPI write failed: E8042_WRITE_KB_CHAR = %d", rv);
+		return;
+	}
 	LOG_INF("KB put %02x", kb_char);
 }
 
@@ -492,9 +608,16 @@ void lpc_aux_put_char(uint8_t chr, int send_irq)
 {
 	uint32_t kb_char = chr;
 	uint32_t status = I8042_AUX_DATA;
+	int rv;
 
-	espi_write_lpc_request(espi_dev, E8042_SET_FLAG, &status);
-	espi_write_lpc_request(espi_dev, E8042_WRITE_KB_CHAR, &kb_char);
+	rv = espi_write_lpc_request(espi_dev, E8042_SET_FLAG, &status);
+	if (rv) {
+		LOG_ERR("ESPI write failed: E8042_SET_FLAG = %d", rv);
+	}
+	rv = espi_write_lpc_request(espi_dev, E8042_WRITE_KB_CHAR, &kb_char);
+	if (rv) {
+		LOG_ERR("ESPI write failed: E8042_WRITE_KB_CHAR = %d", rv);
+	}
 	LOG_INF("AUX put %02x", kb_char);
 }
 
@@ -503,12 +626,16 @@ static void kbc_ibf_obe_handler(uint32_t data)
 #ifdef HAS_TASK_KEYPROTO
 	uint8_t is_ibf = is_8042_ibf(data);
 	uint32_t status = I8042_AUX_DATA;
+	int rv;
 
 	if (is_ibf) {
-		keyboard_host_write(get_8042_data(data),
-				    get_8042_type(data));
+		keyboard_host_write(get_8042_data(data), get_8042_type(data));
 	} else if (IS_ENABLED(CONFIG_8042_AUX)) {
-		espi_write_lpc_request(espi_dev, E8042_CLEAR_FLAG, &status);
+		rv = espi_write_lpc_request(espi_dev, E8042_CLEAR_FLAG,
+					    &status);
+		if (rv) {
+			LOG_ERR("ESPI write failed: E8042_CLEAR_FLAG = %d", rv);
+		}
 	}
 	task_wake(TASK_ID_KEYPROTO);
 #endif
@@ -517,9 +644,14 @@ static void kbc_ibf_obe_handler(uint32_t data)
 int lpc_keyboard_input_pending(void)
 {
 	uint32_t status;
+	int rv;
 
 	/* if IBF bit is '1', that mean still have a data in DBBIN */
-	espi_read_lpc_request(espi_dev, E8042_IBF_HAS_CHAR, &status);
+	rv = espi_read_lpc_request(espi_dev, E8042_IBF_HAS_CHAR, &status);
+	if (rv) {
+		LOG_ERR("ESPI read failed: E8042_IBF_HAS_CHAR = %d", rv);
+		return 0;
+	}
 	return status;
 }
 
@@ -553,12 +685,12 @@ static void espi_peripheral_handler(const struct device *dev,
 
 static int zephyr_shim_setup_espi(const struct device *unused)
 {
-	static struct {
-		struct espi_callback cb;
+	static const struct {
 		espi_callback_handler_t handler;
 		enum espi_bus_event event_type;
 	} callbacks[] = {
-#if !defined(CONFIG_AP_PWRSEQ)
+#if defined(CONFIG_PLATFORM_EC_POWERSEQ) || \
+	defined(CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK)
 		{
 			.handler = espi_vwire_handler,
 			.event_type = ESPI_BUS_EVENT_VWIRE_RECEIVED,
@@ -568,13 +700,14 @@ static int zephyr_shim_setup_espi(const struct device *unused)
 			.handler = espi_peripheral_handler,
 			.event_type = ESPI_BUS_PERIPHERAL_NOTIFICATION,
 		},
-#ifdef CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK
+#if defined(CONFIG_AP_PWRSEQ) && DT_HAS_COMPAT_STATUS_OKAY(intel_ap_pwrseq_vw)
 		{
-			.handler = espi_reset_handler,
-			.event_type = ESPI_BUS_RESET,
+			.handler = power_signal_espi_cb,
+			.event_type = POWER_SIGNAL_ESPI_BUS_EVENTS,
 		},
 #endif
 	};
+	static struct espi_callback cb[ARRAY_SIZE(callbacks)];
 
 	struct espi_cfg cfg = {
 		.io_caps = ESPI_IO_MODE_QUAD_LINES,
@@ -586,17 +719,17 @@ static int zephyr_shim_setup_espi(const struct device *unused)
 	if (!device_is_ready(espi_dev))
 		k_oops();
 
-	/* Configure eSPI */
-	if (espi_config(espi_dev, &cfg)) {
-		LOG_ERR("Failed to configure eSPI device");
-		return -1;
-	}
-
 	/* Setup callbacks */
 	for (size_t i = 0; i < ARRAY_SIZE(callbacks); i++) {
-		espi_init_callback(&callbacks[i].cb, callbacks[i].handler,
+		espi_init_callback(&cb[i], callbacks[i].handler,
 				   callbacks[i].event_type);
-		espi_add_callback(espi_dev, &callbacks[i].cb);
+		espi_add_callback(espi_dev, &cb[i]);
+	}
+
+	/* Configure eSPI after callbacks are registered */
+	if (espi_config(espi_dev, &cfg)) {
+		LOG_ERR("Failed to configure eSPI device");
+		return -1;
 	}
 
 	return 0;
diff --git a/zephyr/shim/src/fan.c b/zephyr/shim/src/fan.c
index 3531941a08..c7074b0c4d 100644
--- a/zephyr/shim/src/fan.c
+++ b/zephyr/shim/src/fan.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -25,8 +25,8 @@ BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
 
 #define FAN_CONFIGS(node_id)                                                   \
 	const struct fan_conf node_id##_conf = {                               \
-		.flags = (COND_CODE_1(DT_PROP(node_id, not_use_rpm_mode),      \
-				      (0), (FAN_USE_RPM_MODE))) |              \
+		.flags = (COND_CODE_1(DT_PROP(node_id, not_use_rpm_mode), (0), \
+				      (FAN_USE_RPM_MODE))) |                   \
 			 (COND_CODE_1(DT_PROP(node_id, use_fast_start),        \
 				      (FAN_USE_FAST_START), (0))),             \
 		.ch = node_id,                                                 \
@@ -45,26 +45,21 @@ BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
 		.rpm_max = DT_PROP(node_id, rpm_max),                          \
 	};
 
-#define FAN_INST(node_id)              \
-	[node_id] = {                  \
+#define FAN_INST(node_id)                \
+	[node_id] = {                    \
 		.conf = &node_id##_conf, \
 		.rpm = &node_id##_rpm,   \
 	},
 
-#define FAN_CONTROL_INST(node_id)                                            \
-	[node_id] = {                                                        \
-		.pwm = DEVICE_DT_GET(DT_PWMS_CTLR(node_id)),                 \
-		.channel = DT_PWMS_CHANNEL(node_id),                         \
-		.flags = DT_PWMS_FLAGS(node_id),                             \
-		.period_ns = (NSEC_PER_SEC/DT_PROP(node_id, pwm_frequency)), \
-		.tach = DEVICE_DT_GET(DT_PHANDLE(node_id, tach)),            \
+#define FAN_CONTROL_INST(node_id)                                 \
+	[node_id] = {                                             \
+		.pwm = PWM_DT_SPEC_GET(node_id),                  \
+		.tach = DEVICE_DT_GET(DT_PHANDLE(node_id, tach)), \
 	},
 
 DT_INST_FOREACH_CHILD(0, FAN_CONFIGS)
 
-const struct fan_t fans[FAN_CH_COUNT] = {
-	DT_INST_FOREACH_CHILD(0, FAN_INST)
-};
+const struct fan_t fans[FAN_CH_COUNT] = { DT_INST_FOREACH_CHILD(0, FAN_INST) };
 
 /* Rpm deviation (Unit:percent) */
 #ifndef RPM_DEVIATION
@@ -104,10 +99,7 @@ struct fan_data {
 
 /* Data structure to define PWM and tachometer. */
 struct fan_config {
-	const struct device *pwm;
-	uint32_t channel;
-	pwm_flags_t flags;
-	uint32_t period_ns;
+	struct pwm_dt_spec pwm;
 
 	const struct device *tach;
 };
@@ -121,28 +113,28 @@ static void fan_pwm_update(int ch)
 {
 	const struct fan_config *cfg = &fan_config[ch];
 	struct fan_data *data = &fan_data[ch];
+	const struct device *pwm_dev = cfg->pwm.dev;
 	uint32_t pulse_ns;
 	int ret;
 
-	if (!device_is_ready(cfg->pwm)) {
-		LOG_ERR("PWM device %s not ready", cfg->pwm->name);
+	if (!device_is_ready(pwm_dev)) {
+		LOG_ERR("PWM device %s not ready", pwm_dev->name);
 		return;
 	}
 
 	if (data->pwm_enabled) {
 		pulse_ns = DIV_ROUND_NEAREST(
-				cfg->period_ns * data->pwm_percent, 100);
+			cfg->pwm.period * data->pwm_percent, 100);
 	} else {
 		pulse_ns = 0;
 	}
 
-	LOG_DBG("FAN PWM %s set percent (%d), pulse %d", cfg->pwm->name,
+	LOG_DBG("FAN PWM %s set percent (%d), pulse %d", pwm_dev->name,
 		data->pwm_percent, pulse_ns);
 
-	ret = pwm_set(cfg->pwm, cfg->channel, cfg->period_ns, pulse_ns,
-		      cfg->flags);
+	ret = pwm_set_dt(&cfg->pwm, cfg->pwm.period, pulse_ns);
 	if (ret) {
-		LOG_ERR("pwm_set() failed %s (%d)", cfg->pwm->name, ret);
+		LOG_ERR("pwm_set() failed %s (%d)", pwm_dev->name, ret);
 	}
 }
 
@@ -320,8 +312,8 @@ void fan_tick_func(void)
 			fan_tick_func_duty(ch);
 			break;
 		default:
-			LOG_ERR("Invalid fan %d mode: %d",
-				ch, fan_data[ch].current_fan_mode);
+			LOG_ERR("Invalid fan %d mode: %d", ch,
+				fan_data[ch].current_fan_mode);
 		}
 	}
 }
diff --git a/zephyr/shim/src/flash.c b/zephyr/shim/src/flash.c
index 9802b39c3a..8aa7deecf5 100644
--- a/zephyr/shim/src/flash.c
+++ b/zephyr/shim/src/flash.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -167,8 +167,7 @@ uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags)
 }
 
 #if IS_ENABLED(CONFIG_SHELL)
-static int command_flashchip(const struct shell *shell,
-			     size_t argc,
+static int command_flashchip(const struct shell *shell, size_t argc,
 			     char **argv)
 {
 	uint8_t manufacturer;
@@ -177,23 +176,19 @@ static int command_flashchip(const struct shell *shell,
 	uint8_t status2;
 	int res;
 
-	res = cros_flash_physical_get_status(cros_flash_dev,
-					     &status1,
+	res = cros_flash_physical_get_status(cros_flash_dev, &status1,
 					     &status2);
 
 	if (!res)
-		shell_fprintf(shell,
-			      SHELL_NORMAL,
-			      "Status 1: 0x%02x, Status 2: 0x%02x\n",
-			      status1, status2);
+		shell_fprintf(shell, SHELL_NORMAL,
+			      "Status 1: 0x%02x, Status 2: 0x%02x\n", status1,
+			      status2);
 
-	res = cros_flash_physical_get_jedec_id(cros_flash_dev,
-					       &manufacturer,
+	res = cros_flash_physical_get_jedec_id(cros_flash_dev, &manufacturer,
 					       &device);
 
 	if (!res)
-		shell_fprintf(shell,
-			      SHELL_NORMAL,
+		shell_fprintf(shell, SHELL_NORMAL,
 			      "Manufacturer: 0x%02x, DID: 0x%04x\n",
 			      manufacturer, device);
 
diff --git a/zephyr/shim/src/gpio.c b/zephyr/shim/src/gpio.c
index eb395813c8..9738bf3de2 100644
--- a/zephyr/shim/src/gpio.c
+++ b/zephyr/shim/src/gpio.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -41,26 +41,30 @@ struct gpio_config {
  * whereas the standard macros assume that only 8 bits of initial flags
  * will be needed.
  */
-#define OUR_DT_SPEC(id)						\
-	{							\
-		.port = DEVICE_DT_GET(DT_GPIO_CTLR(id, gpios)),	\
-		.pin = DT_GPIO_PIN(id, gpios),			\
-		.dt_flags = 0xFF & (DT_GPIO_FLAGS(id, gpios)),	\
+#define OUR_DT_SPEC(id)                                         \
+	{                                                       \
+		.port = DEVICE_DT_GET(DT_GPIO_CTLR(id, gpios)), \
+		.pin = DT_GPIO_PIN(id, gpios),                  \
+		.dt_flags = 0xFF & (DT_GPIO_FLAGS(id, gpios)),  \
 	}
 
-#define GPIO_CONFIG(id)                                      \
-	{                                                    \
-		.spec = OUR_DT_SPEC(id),		     \
-		.name = DT_NODE_FULL_NAME(id),               \
-		.init_flags = DT_GPIO_FLAGS(id, gpios),      \
-		.no_auto_init = DT_PROP(id, no_auto_init),   \
+#define GPIO_CONFIG(id)                                    \
+	{                                                  \
+		.spec = OUR_DT_SPEC(id),                   \
+		.name = DT_NODE_FULL_NAME(id),             \
+		.init_flags = DT_GPIO_FLAGS(id, gpios),    \
+		.no_auto_init = DT_PROP(id, no_auto_init), \
 	},
+#define GPIO_IMPL_CONFIG(id) \
+	COND_CODE_1(DT_NODE_HAS_PROP(id, gpios), (GPIO_CONFIG(id)), ())
+
 static const struct gpio_config configs[] = {
 #if DT_NODE_EXISTS(DT_PATH(named_gpios))
-	DT_FOREACH_CHILD(DT_PATH(named_gpios), GPIO_CONFIG)
+	DT_FOREACH_CHILD(DT_PATH(named_gpios), GPIO_IMPL_CONFIG)
 #endif
 };
 
+#undef GPIO_IMPL_CONFIG
 #undef GPIO_CONFIG
 #undef OUR_DT_SPEC
 
@@ -73,9 +77,9 @@ static const struct gpio_config configs[] = {
  * point directly into the table by exposing the gpio_config struct.
  */
 
-#define GPIO_PTRS(id) const struct gpio_dt_spec * const	\
-	GPIO_DT_NAME(GPIO_SIGNAL(id)) =			\
-	&configs[GPIO_SIGNAL(id)].spec;
+#define GPIO_PTRS(id)                                                    \
+	const struct gpio_dt_spec *const GPIO_DT_NAME(GPIO_SIGNAL(id)) = \
+		&configs[GPIO_SIGNAL(id)].spec;
 
 #if DT_NODE_EXISTS(DT_PATH(named_gpios))
 DT_FOREACH_CHILD(DT_PATH(named_gpios), GPIO_PTRS)
@@ -91,6 +95,30 @@ int gpio_get_level(enum gpio_signal signal)
 	if (!gpio_is_implemented(signal))
 		return 0;
 
+	/*
+	 * If an output GPIO, get the configured value of the output
+	 * rather than the raw value of the pin.
+	 */
+	if (IS_ENABLED(CONFIG_GPIO_GET_CONFIG) &&
+	    configs[signal].init_flags & GPIO_OUTPUT) {
+		int rv;
+		gpio_flags_t flags;
+
+		rv = gpio_pin_get_config_dt(&configs[signal].spec, &flags);
+		if (rv == 0) {
+			return (flags & GPIO_OUTPUT_INIT_HIGH) ? 1 : 0;
+		}
+		/*
+		 * -ENOSYS is returned when this API call is not supported,
+		 *  so drop into the default method of returning the pin value.
+		 */
+		if (rv != -ENOSYS) {
+			LOG_ERR("Cannot get config for %s (%d)",
+				configs[signal].name, rv);
+			return 0;
+		}
+	}
+
 	const int l = gpio_pin_get_raw(configs[signal].spec.port,
 				       configs[signal].spec.pin);
 
@@ -137,8 +165,7 @@ void gpio_set_level(enum gpio_signal signal, int value)
 		return;
 
 	int rv = gpio_pin_set_raw(configs[signal].spec.port,
-				  configs[signal].spec.pin,
-				  value);
+				  configs[signal].spec.pin, value);
 
 	if (rv < 0) {
 		LOG_ERR("Cannot write %s (%d)", configs[signal].name, rv);
@@ -167,15 +194,15 @@ int gpio_or_ioex_get_level(int signal, int *value)
 #define GPIO_CONVERSION_SAME_BITS                                             \
 	(GPIO_OPEN_DRAIN | GPIO_PULL_UP | GPIO_PULL_DOWN | GPIO_VOLTAGE_1P8 | \
 	 GPIO_INPUT | GPIO_OUTPUT | GPIO_OUTPUT_INIT_LOW |                    \
-	GPIO_OUTPUT_INIT_HIGH)
+	 GPIO_OUTPUT_INIT_HIGH)
 
 #define FLAGS_HANDLED_FROM_ZEPHYR                                      \
 	(GPIO_CONVERSION_SAME_BITS | GPIO_INT_ENABLE | GPIO_INT_EDGE | \
-	GPIO_INT_HIGH_1 | GPIO_INT_LOW_0)
+	 GPIO_INT_HIGH_1 | GPIO_INT_LOW_0)
 
 #define FLAGS_HANDLED_TO_ZEPHYR                                               \
 	(GPIO_CONVERSION_SAME_BITS | GPIO_INT_F_RISING | GPIO_INT_F_FALLING | \
-	GPIO_INT_F_LOW | GPIO_INT_F_HIGH)
+	 GPIO_INT_F_LOW | GPIO_INT_F_HIGH)
 
 int convert_from_zephyr_flags(const gpio_flags_t zephyr)
 {
@@ -219,11 +246,11 @@ gpio_flags_t convert_to_zephyr_flags(int ec_flags)
 	}
 
 	if (ec_flags & GPIO_INT_F_RISING)
-		zephyr_flags |= GPIO_INT_ENABLE
-			| GPIO_INT_EDGE | GPIO_INT_HIGH_1;
+		zephyr_flags |= GPIO_INT_ENABLE | GPIO_INT_EDGE |
+				GPIO_INT_HIGH_1;
 	if (ec_flags & GPIO_INT_F_FALLING)
-		zephyr_flags |= GPIO_INT_ENABLE
-			| GPIO_INT_EDGE | GPIO_INT_LOW_0;
+		zephyr_flags |= GPIO_INT_ENABLE | GPIO_INT_EDGE |
+				GPIO_INT_LOW_0;
 	if (ec_flags & GPIO_INT_F_LOW)
 		zephyr_flags |= GPIO_INT_ENABLE | GPIO_INT_LOW_0;
 	if (ec_flags & GPIO_INT_F_HIGH)
@@ -276,7 +303,7 @@ static int init_gpios(const struct device *unused)
 		 */
 		if (is_sys_jumped && (flags & GPIO_OUTPUT)) {
 			flags &=
-			    ~(GPIO_OUTPUT_INIT_LOW | GPIO_OUTPUT_INIT_HIGH);
+				~(GPIO_OUTPUT_INIT_LOW | GPIO_OUTPUT_INIT_HIGH);
 		}
 
 		rv = gpio_pin_configure_dt(&configs[i].spec, flags);
diff --git a/zephyr/shim/src/gpio_id.c b/zephyr/shim/src/gpio_id.c
index b562f405bc..b994154cd1 100644
--- a/zephyr/shim/src/gpio_id.c
+++ b/zephyr/shim/src/gpio_id.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,10 +11,8 @@
 #include "gpio.h"
 #include "util.h"
 
-#define IS_BOARD_COMPATIBLE \
-	DT_NODE_HAS_COMPAT(DT_PATH(board), cros_ec_gpio_id)
-#define IS_SKU_COMPATIBLE \
-	DT_NODE_HAS_COMPAT(DT_PATH(sku), cros_ec_gpio_id)
+#define IS_BOARD_COMPATIBLE DT_NODE_HAS_COMPAT(DT_PATH(board), cros_ec_gpio_id)
+#define IS_SKU_COMPATIBLE DT_NODE_HAS_COMPAT(DT_PATH(sku), cros_ec_gpio_id)
 
 #define CONVERT_NUMERAL_SYSTEM_EVAL(system, bits, nbits) \
 	system##_from_bits(bits, nbits)
@@ -32,11 +30,8 @@ __override uint32_t board_get_sku_id(void)
 	static uint32_t sku_id = (uint32_t)-1;
 
 	if (sku_id == (uint32_t)-1) {
-		int bits[] = {
-			DT_FOREACH_PROP_ELEM(DT_PATH(sku),
-					bits,
-					READ_PIN_FROM_PHANDLE)
-		};
+		int bits[] = { DT_FOREACH_PROP_ELEM(DT_PATH(sku), bits,
+						    READ_PIN_FROM_PHANDLE) };
 
 		if (sizeof(bits) == 0)
 			return (uint32_t)-1;
@@ -58,11 +53,8 @@ __override int board_get_version(void)
 	static int board_version = -1;
 
 	if (board_version == -1) {
-		int bits[] = {
-			DT_FOREACH_PROP_ELEM(DT_PATH(board),
-					bits,
-					READ_PIN_FROM_PHANDLE)
-		};
+		int bits[] = { DT_FOREACH_PROP_ELEM(DT_PATH(board), bits,
+						    READ_PIN_FROM_PHANDLE) };
 
 		if (sizeof(bits) == 0)
 			return -1;
diff --git a/zephyr/shim/src/gpio_int.c b/zephyr/shim/src/gpio_int.c
index 6f13976acc..8406f3abe8 100644
--- a/zephyr/shim/src/gpio_int.c
+++ b/zephyr/shim/src/gpio_int.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -174,7 +174,7 @@ int gpio_enable_dt_interrupt(const struct gpio_int_config *conf)
 }
 
 const struct gpio_int_config *
-	gpio_interrupt_get_config(enum gpio_interrupts intr)
+gpio_interrupt_get_config(enum gpio_interrupts intr)
 {
 	return &gpio_int_data[intr];
 }
diff --git a/zephyr/shim/src/hooks.c b/zephyr/shim/src/hooks.c
index 07bf27f3b0..da981dea6b 100644
--- a/zephyr/shim/src/hooks.c
+++ b/zephyr/shim/src/hooks.c
@@ -1,10 +1,9 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include <zephyr/kernel.h>
-#include <zephyr/zephyr.h>
 
 #include <ap_power/ap_power.h>
 #include <ap_power/ap_power_events.h>
@@ -23,21 +22,20 @@
  * this code must manually generate references to the symbols generated by
  * STRUCT_SECTION_ITERABLE_ALTERNATE in zephyr_hooks_shim.h.
  */
-#define HOOK_LIST_EXTERNS(type)                              \
-	extern const struct zephyr_shim_hook_info            \
+#define HOOK_LIST_EXTERNS(type)                          \
+	extern const struct zephyr_shim_hook_info        \
 		_zephyr_shim_hook_##type##_list_start[]; \
-	extern const struct zephyr_shim_hook_info            \
+	extern const struct zephyr_shim_hook_info        \
 		_zephyr_shim_hook_##type##_list_end[];
 FOR_EACH(HOOK_LIST_EXTERNS, (), HOOK_TYPES_LIST)
 
-#define HOOK_LIST_ENTRY(type)                                       \
-	[type] = {                                                  \
+#define HOOK_LIST_ENTRY(type)                                   \
+	[type] = {                                              \
 		.start = _zephyr_shim_hook_##type##_list_start, \
 		.end = _zephyr_shim_hook_##type##_list_end,     \
 	}
-static const struct zephyr_shim_hook_list hook_registry[] = {
-	FOR_EACH(HOOK_LIST_ENTRY, (,), HOOK_TYPES_LIST)
-};
+static const struct zephyr_shim_hook_list hook_registry[] = { FOR_EACH(
+	HOOK_LIST_ENTRY, (, ), HOOK_TYPES_LIST) };
 BUILD_ASSERT(ARRAY_SIZE(hook_registry) == HOOK_TYPE_COUNT,
 	     "All defined hook types must be represented in hook_registry");
 BUILD_ASSERT(NUM_VA_ARGS_LESS_1(HOOK_TYPES_LIST) + 1 == HOOK_TYPE_COUNT,
@@ -53,7 +51,7 @@ static void work_queue_error(const void *data, int rv)
 {
 	cprints(CC_HOOK,
 		"Warning: deferred call not submitted, "
-		"deferred_data=0x%pP, err=%d",
+		"deferred_data=0x%p, err=%d",
 		data, rv);
 }
 
diff --git a/zephyr/shim/src/host_command.c b/zephyr/shim/src/host_command.c
index 7bf61ee551..c5a51332a1 100644
--- a/zephyr/shim/src/host_command.c
+++ b/zephyr/shim/src/host_command.c
@@ -1,16 +1,17 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <zephyr/zephyr.h>
+#include <zephyr/kernel.h>
 
 #include "host_command.h"
 #include "task.h"
 
 struct host_command *zephyr_find_host_command(int command)
 {
-	STRUCT_SECTION_FOREACH(host_command, cmd) {
+	STRUCT_SECTION_FOREACH(host_command, cmd)
+	{
 		if (cmd->command == command)
 			return cmd;
 	}
diff --git a/zephyr/shim/src/hwtimer.c b/zephyr/shim/src/hwtimer.c
index aaaf051d80..d99f7a826b 100644
--- a/zephyr/shim/src/hwtimer.c
+++ b/zephyr/shim/src/hwtimer.c
@@ -1,11 +1,10 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include <zephyr/kernel.h>
 #include <stdint.h>
-#include <zephyr/zephyr.h>
 
 #include "hwtimer.h"
 
diff --git a/zephyr/shim/src/i2c.c b/zephyr/shim/src/i2c.c
index 8d55876629..0074327826 100644
--- a/zephyr/shim/src/i2c.c
+++ b/zephyr/shim/src/i2c.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -21,11 +21,10 @@
  * Initialize device bindings in i2c_devices.
  * This macro should be called from within DT_FOREACH_CHILD.
  */
-#define INIT_DEV_BINDING(id) \
-	[I2C_PORT(id)] = DEVICE_DT_GET(DT_PHANDLE(id, i2c_port)),
+#define INIT_DEV_BINDING(i2c_port_id) \
+	[I2C_PORT_BUS(i2c_port_id)] = DEVICE_DT_GET(i2c_port_id),
 
-#define INIT_REMOTE_PORTS(id) \
-	[I2C_PORT(id)] = DT_PROP_OR(id, remote_port, -1),
+#define INIT_REMOTE_PORTS(id) [I2C_PORT(id)] = DT_PROP_OR(id, remote_port, -1),
 
 #define I2C_PORT_FLAGS(id)                                                     \
 	COND_CODE_1(DT_PROP(id, dynamic_speed), (I2C_PORT_FLAG_DYNAMIC_SPEED), \
@@ -44,49 +43,14 @@
  * Since all the ports will eventually be handled by device tree. This will
  * be removed at that point.
  */
-const struct i2c_port_t i2c_ports[] = {
-	DT_FOREACH_CHILD(DT_PATH(named_i2c_ports), I2C_PORT_INIT)
-};
+const struct i2c_port_t i2c_ports[] = { DT_FOREACH_CHILD(
+	DT_PATH(named_i2c_ports), I2C_PORT_INIT) };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-static const int i2c_remote_ports[I2C_PORT_COUNT] = {
-	DT_FOREACH_CHILD(DT_PATH(named_i2c_ports), INIT_REMOTE_PORTS)
-};
-static int i2c_physical_ports[I2C_PORT_COUNT];
+static const int i2c_remote_ports[I2C_PORT_COUNT] = { DT_FOREACH_CHILD(
+	DT_PATH(named_i2c_ports), INIT_REMOTE_PORTS) };
 
-static const struct device *i2c_devices[I2C_PORT_COUNT] = {
-	DT_FOREACH_CHILD(DT_PATH(named_i2c_ports), INIT_DEV_BINDING)
-};
-
-static int init_device_bindings(const struct device *device)
-{
-	ARG_UNUSED(device);
-
-	/*
-	 * The EC application may lock the I2C bus for more than a single
-	 * I2C transaction. Initialize the i2c_physical_ports[] array to map
-	 * each named-i2c-ports child to the physical bus assignment.
-	 */
-	int i;
-	int physical_port = 0;
-
-	i2c_physical_ports[0] = physical_port;
-	for (int child = 1; child < I2C_PORT_COUNT; child++) {
-		for (i = 0; i < child; i++) {
-			if (i2c_devices[child] == i2c_devices[i]) {
-				i2c_physical_ports[child] =
-					i2c_physical_ports[i];
-				break;
-			}
-		}
-		if (i == child)
-			i2c_physical_ports[child] = ++physical_port;
-	}
-	__ASSERT(I2C_DEVICE_COUNT == 0 ||
-			 physical_port == (I2C_DEVICE_COUNT - 1),
-		 "I2C_DEVICE_COUNT is invalid");
-	return 0;
-}
-SYS_INIT(init_device_bindings, POST_KERNEL, 51);
+static const struct device *i2c_devices[I2C_PORT_COUNT] = { I2C_FOREACH_PORT(
+	INIT_DEV_BINDING) };
 
 const struct device *i2c_get_device_for_port(const int port)
 {
@@ -110,31 +74,15 @@ int i2c_get_port_from_remote_port(int remote_port)
 	return remote_port;
 }
 
-int i2c_get_physical_port(int enum_port)
-{
-	int i2c_port;
-
-	if (enum_port < 0 || enum_port >= I2C_PORT_COUNT)
-		return -1;
-
-	i2c_port = i2c_physical_ports[enum_port];
-	/*
-	 * Return -1 for caller if physical port is not defined or the
-	 * port number is out of port_mutex space.
-	 * Please ensure the caller won't change anything if -1 received.
-	 */
-	return (i2c_port < I2C_DEVICE_COUNT) ? i2c_port : -1;
-}
-
 #ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_I2C_PORTMAP
-static int command_i2c_portmap(int argc, char **argv)
+static int command_i2c_portmap(int argc, const char **argv)
 {
 	int i;
 
-	ccprintf("Zephyr physical I2C ports (%d):\n", I2C_PORT_COUNT);
-	for (i = 0; i < I2C_PORT_COUNT; i++) {
-		ccprintf("  %d : %d\n", i, i2c_physical_ports[i]);
+	if (argc > 1) {
+		return EC_ERROR_PARAM_COUNT;
 	}
+
 	ccprintf("Zephyr remote I2C ports (%d):\n", I2C_PORT_COUNT);
 	for (i = 0; i < I2C_PORT_COUNT; i++) {
 		ccprintf("  %d : %d\n", i, i2c_remote_ports[i]);
diff --git a/zephyr/shim/src/ioex.c b/zephyr/shim/src/ioex.c
index 56b10d1f48..a5d685bc48 100644
--- a/zephyr/shim/src/ioex.c
+++ b/zephyr/shim/src/ioex.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -42,8 +42,8 @@ static int ioex_init_default(const struct device *unused)
 
 	for (i = 0; i < CONFIG_IO_EXPANDER_PORT_COUNT; i++) {
 		/* IO Expander has been initialized, skip re-initializing */
-		if (ioex_config[i].flags & (IOEX_FLAGS_INITIALIZED |
-					IOEX_FLAGS_DEFAULT_INIT_DISABLED))
+		if (ioex_config[i].flags &
+		    (IOEX_FLAGS_INITIALIZED | IOEX_FLAGS_DEFAULT_INIT_DISABLED))
 			continue;
 
 		ret = ioex_init(i);
diff --git a/zephyr/shim/src/ioex_drv.c b/zephyr/shim/src/ioex_drv.c
index ccf142576d..96a0dd3a8e 100644
--- a/zephyr/shim/src/ioex_drv.c
+++ b/zephyr/shim/src/ioex_drv.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/shim/src/keyboard_raw.c b/zephyr/shim/src/keyboard_raw.c
index ef2dadb29c..c9f465d06d 100644
--- a/zephyr/shim/src/keyboard_raw.c
+++ b/zephyr/shim/src/keyboard_raw.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,7 +8,7 @@
 #include <zephyr/device.h>
 #include <zephyr/logging/log.h>
 #include <soc.h>
-#include <zephyr/zephyr.h>
+#include <zephyr/kernel.h>
 
 #include "drivers/cros_kb_raw.h"
 #include "keyboard_raw.h"
diff --git a/zephyr/shim/src/keyscan.c b/zephyr/shim/src/keyscan.c
index a5503ecb48..514885379b 100644
--- a/zephyr/shim/src/keyscan.c
+++ b/zephyr/shim/src/keyscan.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/shim/src/led_driver/CMakeLists.txt b/zephyr/shim/src/led_driver/CMakeLists.txt
index 7c21d6827e..179f540fe1 100644
--- a/zephyr/shim/src/led_driver/CMakeLists.txt
+++ b/zephyr/shim/src/led_driver/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/shim/src/led_driver/led.c b/zephyr/shim/src/led_driver/led.c
index 127c786ddf..011632ac83 100644
--- a/zephyr/shim/src/led_driver/led.c
+++ b/zephyr/shim/src/led_driver/led.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -24,21 +24,14 @@
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(led, LOG_LEVEL_ERR);
 
-#define LED_COLOR_NODE  DT_PATH(led_colors)
+#define LED_COLOR_NODE DT_PATH(led_colors)
 
 struct led_color_node_t {
 	struct led_pins_node_t *pins_node;
 	int acc_period;
 };
 
-enum led_extra_flag_t {
-	NONE = 0,
-	LED_CHFLAG_FORCE_IDLE,
-	LED_CHFLAG_DEFAULT,
-};
-
-#define DECLARE_PINS_NODE(id)						\
-extern struct led_pins_node_t PINS_NODE(id);
+#define DECLARE_PINS_NODE(id) extern struct led_pins_node_t PINS_NODE(id);
 
 #if DT_HAS_COMPAT_STATUS_OKAY(COMPAT_PWM_LED)
 DT_FOREACH_CHILD(PWM_LED_PINS_NODE, DECLARE_PINS_NODE)
@@ -59,12 +52,11 @@ DT_FOREACH_CHILD(GPIO_LED_PINS_NODE, DECLARE_PINS_NODE)
  * 3, 4, 5 < period_3 -> LED_COLOR_3 for 3 secs
  * 6, 7, 8 < period_4 -> LED_COLOR_4 for 3 secs
  */
-#define MAX_COLOR	4
+#define MAX_COLOR 4
 
 struct node_prop_t {
 	enum charge_state pwr_state;
 	enum power_state chipset_state;
-	enum led_extra_flag_t led_extra_flag;
 	int8_t batt_lvl[2];
 	int8_t charge_port;
 	struct led_color_node_t led_colors[MAX_COLOR];
@@ -80,55 +72,51 @@ struct node_prop_t {
  * HOOT_TICK_INTERVAL_MS
  */
 
-#define PERIOD_VAL(id) COND_CODE_1(DT_NODE_HAS_PROP(id, period_ms),	\
-		(DT_PROP(id, period_ms) / HOOK_TICK_INTERVAL_MS), (0))
+#define PERIOD_VAL(id)                               \
+	COND_CODE_1(DT_NODE_HAS_PROP(id, period_ms), \
+		    (DT_PROP(id, period_ms) / HOOK_TICK_INTERVAL_MS), (0))
 
-#define LED_PERIOD(color_num, state_id)					\
+#define LED_PERIOD(color_num, state_id) \
 	PERIOD_VAL(DT_CHILD(state_id, color_##color_num))
 
-#define LED_PLUS_PERIOD(color_num, state_id)				\
-	+ LED_PERIOD(color_num, state_id)
+#define LED_PLUS_PERIOD(color_num, state_id) +LED_PERIOD(color_num, state_id)
 
-#define ACC_PERIOD(color_num, state_id)					\
+#define ACC_PERIOD(color_num, state_id) \
 	(0 LISTIFY(color_num, LED_PLUS_PERIOD, (), state_id))
 
-#define PINS_NODE_ADDR(id)	DT_PHANDLE(id, led_color)
-#define LED_COLOR_INIT(color_num, color_num_plus_one, state_id)		\
-{									\
-	.pins_node = COND_CODE_1(					\
-		DT_NODE_EXISTS(DT_CHILD(state_id, color_##color_num)),	\
-		(&PINS_NODE(PINS_NODE_ADDR(				\
-			DT_CHILD(state_id, color_##color_num)))),	\
-		(NULL)),						\
-	.acc_period = ACC_PERIOD(color_num_plus_one, state_id)		\
-}
+#define PINS_NODE_ADDR(id) DT_PHANDLE(id, led_color)
+#define LED_COLOR_INIT(color_num, color_num_plus_one, state_id)                \
+	{                                                                      \
+		.pins_node = COND_CODE_1(                                      \
+			DT_NODE_EXISTS(DT_CHILD(state_id, color_##color_num)), \
+			(&PINS_NODE(PINS_NODE_ADDR(                            \
+				DT_CHILD(state_id, color_##color_num)))),      \
+			(NULL)),                                               \
+		.acc_period = ACC_PERIOD(color_num_plus_one, state_id)         \
+	}
 
 /*
  * Initialize node_array struct with prop listed in dts
  */
-#define SET_LED_VALUES(state_id)					\
-{									\
-	.pwr_state = GET_PROP(state_id, charge_state),			\
-	.chipset_state = GET_PROP(state_id, chipset_state),		\
-	.led_extra_flag = GET_PROP(state_id, extra_flag),		\
-	.batt_lvl = COND_CODE_1(					\
-			DT_NODE_HAS_PROP(state_id, batt_lvl),		\
-			(DT_PROP(state_id, batt_lvl)), ({-1, -1})),	\
-	.charge_port = COND_CODE_1(					\
-			DT_NODE_HAS_PROP(state_id, charge_port),	\
-			(DT_PROP(state_id, charge_port)), (-1)),	\
-	.led_colors = {LED_COLOR_INIT(0, 1, state_id),			\
-		       LED_COLOR_INIT(1, 2, state_id),			\
-		       LED_COLOR_INIT(2, 3, state_id),			\
-		       LED_COLOR_INIT(3, 4, state_id),			\
-		      }							\
-},
-
-static const struct node_prop_t node_array[] = {
-	DT_FOREACH_CHILD(LED_COLOR_NODE, SET_LED_VALUES)
-};
-
-static enum power_state get_chipset_state(void)
+#define SET_LED_VALUES(state_id)                                              \
+	{ .pwr_state = GET_PROP(state_id, charge_state),                      \
+	  .chipset_state = GET_PROP(state_id, chipset_state),                 \
+	  .batt_lvl = COND_CODE_1(DT_NODE_HAS_PROP(state_id, batt_lvl),       \
+				  (DT_PROP(state_id, batt_lvl)),              \
+				  ({ -1, -1 })),                              \
+	  .charge_port = COND_CODE_1(DT_NODE_HAS_PROP(state_id, charge_port), \
+				     (DT_PROP(state_id, charge_port)), (-1)), \
+	  .led_colors = {                                                     \
+		  LED_COLOR_INIT(0, 1, state_id),                             \
+		  LED_COLOR_INIT(1, 2, state_id),                             \
+		  LED_COLOR_INIT(2, 3, state_id),                             \
+		  LED_COLOR_INIT(3, 4, state_id),                             \
+	  } },
+
+static const struct node_prop_t node_array[] = { DT_FOREACH_CHILD(
+	LED_COLOR_NODE, SET_LED_VALUES) };
+
+test_export_static enum power_state get_chipset_state(void)
 {
 	enum power_state chipset_state = 0;
 
@@ -149,33 +137,7 @@ static enum power_state get_chipset_state(void)
 	return chipset_state;
 }
 
-static bool find_node_with_extra_flag(int i)
-{
-	uint32_t chflags = charge_get_flags();
-	bool found_node = false;
-
-	switch (node_array[i].led_extra_flag) {
-	case LED_CHFLAG_FORCE_IDLE:
-	case LED_CHFLAG_DEFAULT:
-		if (chflags & CHARGE_FLAG_FORCE_IDLE) {
-			if (node_array[i].led_extra_flag ==
-					LED_CHFLAG_FORCE_IDLE)
-				found_node = true;
-		} else {
-			if (node_array[i].led_extra_flag == LED_CHFLAG_DEFAULT)
-				found_node = true;
-		}
-		break;
-	default:
-		LOG_ERR("Invalid led extra flag %d",
-				node_array[i].led_extra_flag);
-		break;
-	}
-
-	return found_node;
-}
-
-#define GET_PERIOD(n_idx, c_idx)  node_array[n_idx].led_colors[c_idx].acc_period
+#define GET_PERIOD(n_idx, c_idx) node_array[n_idx].led_colors[c_idx].acc_period
 #define GET_PIN_NODE(n_idx, c_idx) node_array[n_idx].led_colors[c_idx].pins_node
 
 static void set_color(int node_idx, uint32_t ticks)
@@ -258,11 +220,6 @@ static int match_node(int node_idx)
 			return -1;
 	}
 
-	/* Check if the node depends on any special flags */
-	if (node_array[node_idx].led_extra_flag != NONE)
-		if (!find_node_with_extra_flag(node_idx))
-			return -1;
-
 	/* We found the node that matches the current system state */
 	return node_idx;
 }
diff --git a/zephyr/shim/src/led_driver/led.h b/zephyr/shim/src/led_driver/led.h
index 8c4e7654d5..b8cedf5af7 100644
--- a/zephyr/shim/src/led_driver/led.h
+++ b/zephyr/shim/src/led_driver/led.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,34 +11,32 @@
 #include <zephyr/drivers/pwm.h>
 
 #define COMPAT_GPIO_LED cros_ec_gpio_led_pins
-#define COMPAT_PWM_LED  cros_ec_pwm_led_pins
+#define COMPAT_PWM_LED cros_ec_pwm_led_pins
 
-#define PINS_NODE(id)	DT_CAT(PIN_NODE_, id)
-#define PINS_ARRAY(id)	DT_CAT(PINS_ARRAY_, id)
+#define PINS_NODE(id) DT_CAT(PIN_NODE_, id)
+#define PINS_ARRAY(id) DT_CAT(PINS_ARRAY_, id)
 
 /*
  * Return string-token if the property exists, otherwise return 0
  */
-#define GET_PROP(id, prop)						\
-	COND_CODE_1(DT_NODE_HAS_PROP(id, prop),				\
-		    (DT_STRING_UPPER_TOKEN(id, prop)),			\
-		    (0))
+#define GET_PROP(id, prop)                      \
+	COND_CODE_1(DT_NODE_HAS_PROP(id, prop), \
+		    (DT_STRING_UPPER_TOKEN(id, prop)), (0))
 
 /*
  * Return string-token if the property exists, otherwise return -1
  */
-#define GET_PROP_NVE(id, prop)						\
-	COND_CODE_1(DT_NODE_HAS_PROP(id, prop),				\
-		    (DT_STRING_UPPER_TOKEN(id, prop)),			\
-		    (-1))
+#define GET_PROP_NVE(id, prop)                  \
+	COND_CODE_1(DT_NODE_HAS_PROP(id, prop), \
+		    (DT_STRING_UPPER_TOKEN(id, prop)), (-1))
 
-#define LED_ENUM(id, enum_name)	 DT_STRING_TOKEN(id, enum_name)
-#define LED_ENUM_WITH_COMMA(id, enum_name)				\
-	COND_CODE_1(DT_NODE_HAS_PROP(id, enum_name),			\
-		    (LED_ENUM(id, enum_name),), ())
+#define LED_ENUM(id, enum_name) DT_STRING_TOKEN(id, enum_name)
+#define LED_ENUM_WITH_COMMA(id, enum_name)           \
+	COND_CODE_1(DT_NODE_HAS_PROP(id, enum_name), \
+		    (LED_ENUM(id, enum_name), ), ())
 
 #define GPIO_LED_PINS_NODE DT_PATH(gpio_led_pins)
-#define PWM_LED_PINS_NODE  DT_PATH(pwm_led_pins)
+#define PWM_LED_PINS_NODE DT_PATH(pwm_led_pins)
 
 enum led_color {
 	LED_OFF,
@@ -48,7 +46,7 @@ enum led_color {
 	LED_YELLOW,
 	LED_WHITE,
 	LED_AMBER,
-	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+	LED_COLOR_COUNT /* Number of colors, not a color itself */
 };
 
 /*
@@ -63,9 +61,7 @@ struct gpio_pin_t {
  * Struct defining LED PWM pin and duty cycle to set.
  */
 struct pwm_pin_t {
-	const struct device *pwm;
-	uint8_t channel;
-	pwm_flags_t flags;
+	struct pwm_dt_spec pwm;
 	uint32_t pulse_ns; /* PWM Duty cycle ns */
 };
 
@@ -122,6 +118,8 @@ void led_set_color_with_node(const struct led_pins_node_t *pins_node);
 #ifdef TEST_BUILD
 const struct led_pins_node_t *led_get_node(enum led_color color,
 					   enum ec_led_id led_id);
+
+enum power_state get_chipset_state(void);
 #endif /* TEST_BUILD */
 
 #endif /* __CROS_EC_LED_H__ */
diff --git a/zephyr/shim/src/led_driver/led_gpio.c b/zephyr/shim/src/led_driver/led_gpio.c
index 5a4735a162..122794dc82 100644
--- a/zephyr/shim/src/led_driver/led_gpio.c
+++ b/zephyr/shim/src/led_driver/led_gpio.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -17,46 +17,38 @@
 
 LOG_MODULE_REGISTER(gpio_led, LOG_LEVEL_ERR);
 
-#define SET_PIN(node_id, prop, i)					\
-{									\
-	.signal = GPIO_SIGNAL(DT_PHANDLE_BY_IDX(node_id, prop, i)),	\
-	.val = DT_PHA_BY_IDX(node_id, prop, i, value)			\
-},
+#define SET_PIN(node_id, prop, i)                                     \
+	{ .signal = GPIO_SIGNAL(DT_PHANDLE_BY_IDX(node_id, prop, i)), \
+	  .val = DT_PHA_BY_IDX(node_id, prop, i, value) },
 
-#define SET_GPIO_PIN(node_id)						\
-{									\
-	DT_FOREACH_PROP_ELEM(node_id, led_pins, SET_PIN)		\
-};
+#define SET_GPIO_PIN(node_id) \
+	{ DT_FOREACH_PROP_ELEM(node_id, led_pins, SET_PIN) };
 
-#define GEN_PINS_ARRAY(id)						\
-struct gpio_pin_t PINS_ARRAY(id)[] = SET_GPIO_PIN(id)
+#define GEN_PINS_ARRAY(id) struct gpio_pin_t PINS_ARRAY(id)[] = SET_GPIO_PIN(id)
 
 DT_FOREACH_CHILD(GPIO_LED_PINS_NODE, GEN_PINS_ARRAY)
 
-#define SET_PIN_NODE(node_id)						\
-{									\
-	.led_color = GET_PROP(node_id, led_color),			\
-	.led_id = GET_PROP(node_id, led_id),				\
-	.br_color = GET_PROP_NVE(node_id, br_color),			\
-	.gpio_pins = PINS_ARRAY(node_id),				\
-	.pins_count = DT_PROP_LEN(node_id, led_pins)			\
-};
+#define SET_PIN_NODE(node_id)                          \
+	{ .led_color = GET_PROP(node_id, led_color),   \
+	  .led_id = GET_PROP(node_id, led_id),         \
+	  .br_color = GET_PROP_NVE(node_id, br_color), \
+	  .gpio_pins = PINS_ARRAY(node_id),            \
+	  .pins_count = DT_PROP_LEN(node_id, led_pins) };
 
 /*
  * Initialize led_pins_node_t struct for each pin node defined
  */
-#define GEN_PINS_NODES(id)						\
-const struct led_pins_node_t PINS_NODE(id) = SET_PIN_NODE(id)
+#define GEN_PINS_NODES(id) \
+	const struct led_pins_node_t PINS_NODE(id) = SET_PIN_NODE(id)
 
 DT_FOREACH_CHILD(GPIO_LED_PINS_NODE, GEN_PINS_NODES)
 
 /*
  * Array of pointers to each pin node
  */
-#define PINS_NODE_PTR(id)	&PINS_NODE(id),
-const struct led_pins_node_t *pins_node[] = {
-	DT_FOREACH_CHILD(GPIO_LED_PINS_NODE, PINS_NODE_PTR)
-};
+#define PINS_NODE_PTR(id) &PINS_NODE(id),
+const struct led_pins_node_t *pins_node[] = { DT_FOREACH_CHILD(
+	GPIO_LED_PINS_NODE, PINS_NODE_PTR) };
 
 /*
  * Set all the GPIO pins defined in the node to the defined value,
@@ -65,8 +57,8 @@ const struct led_pins_node_t *pins_node[] = {
 void led_set_color_with_node(const struct led_pins_node_t *pins_node)
 {
 	for (int j = 0; j < pins_node->pins_count; j++) {
-		gpio_pin_set_dt(gpio_get_dt_spec(
-			pins_node->gpio_pins[j].signal),
+		gpio_pin_set_dt(
+			gpio_get_dt_spec(pins_node->gpio_pins[j].signal),
 			pins_node->gpio_pins[j].val);
 	}
 }
diff --git a/zephyr/shim/src/led_driver/led_pwm.c b/zephyr/shim/src/led_driver/led_pwm.c
index 7935bc0d8a..00002fc32e 100644
--- a/zephyr/shim/src/led_driver/led_pwm.c
+++ b/zephyr/shim/src/led_driver/led_pwm.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
@@ -27,54 +27,44 @@ LOG_MODULE_REGISTER(pwm_led, LOG_LEVEL_ERR);
  * e.g. freq = 500 Hz, period_ns = 1000000000/500 = 2000000ns
  * duty_cycle = 50 %, pulse_ns  = (2000000*50)/100 = 1000000ns
  */
-const uint32_t period_ns =
-		(NSEC_PER_SEC / DT_PROP(PWM_LED_PINS_NODE, pwm_frequency));
-
-#define SET_PIN(node_id, prop, i)					\
-{									\
-	.pwm = DEVICE_DT_GET(						\
-		DT_PWMS_CTLR(DT_PHANDLE_BY_IDX(node_id, prop, i))),	\
-	.channel = DT_PWMS_CHANNEL(					\
-			DT_PHANDLE_BY_IDX(node_id, prop, i)),		\
-	.flags = DT_PWMS_FLAGS(DT_PHANDLE_BY_IDX(node_id, prop, i)),	\
-	.pulse_ns = DIV_ROUND_NEAREST(					\
-	   period_ns * DT_PHA_BY_IDX(node_id, prop, i, value), 100),	\
-},
-
-#define SET_PWM_PIN(node_id)						\
-{									\
-	DT_FOREACH_PROP_ELEM(node_id, led_pins, SET_PIN)		\
-};
-
-#define GEN_PINS_ARRAY(id)						\
-struct pwm_pin_t PINS_ARRAY(id)[] = SET_PWM_PIN(id)
+
+#define SET_PIN(node_id, prop, i)                                             \
+	{                                                                     \
+		.pwm = PWM_DT_SPEC_GET(DT_PHANDLE_BY_IDX(node_id, prop, i)),  \
+		.pulse_ns = DIV_ROUND_NEAREST(                                \
+			DT_PWMS_PERIOD(DT_PHANDLE_BY_IDX(node_id, prop, i)) * \
+				DT_PHA_BY_IDX(node_id, prop, i, value),       \
+			100),                                                 \
+	},
+
+#define SET_PWM_PIN(node_id) \
+	{ DT_FOREACH_PROP_ELEM(node_id, led_pins, SET_PIN) };
+
+#define GEN_PINS_ARRAY(id) struct pwm_pin_t PINS_ARRAY(id)[] = SET_PWM_PIN(id)
 
 DT_FOREACH_CHILD(PWM_LED_PINS_NODE, GEN_PINS_ARRAY)
 
-#define SET_PIN_NODE(node_id)						\
-{									\
-	.led_color = GET_PROP(node_id, led_color),			\
-	.led_id = GET_PROP(node_id, led_id),				\
-	.br_color = GET_PROP_NVE(node_id, br_color),			\
-	.pwm_pins = PINS_ARRAY(node_id),				\
-	.pins_count = DT_PROP_LEN(node_id, led_pins)			\
-};
+#define SET_PIN_NODE(node_id)                          \
+	{ .led_color = GET_PROP(node_id, led_color),   \
+	  .led_id = GET_PROP(node_id, led_id),         \
+	  .br_color = GET_PROP_NVE(node_id, br_color), \
+	  .pwm_pins = PINS_ARRAY(node_id),             \
+	  .pins_count = DT_PROP_LEN(node_id, led_pins) };
 
 /*
  * Initialize led_pins_node_t struct for each pin node defined
  */
-#define GEN_PINS_NODES(id)						\
-const struct led_pins_node_t PINS_NODE(id) = SET_PIN_NODE(id)
+#define GEN_PINS_NODES(id) \
+	const struct led_pins_node_t PINS_NODE(id) = SET_PIN_NODE(id)
 
 DT_FOREACH_CHILD(PWM_LED_PINS_NODE, GEN_PINS_NODES)
 
 /*
  * Array of pointers to each pin node
  */
-#define PINS_NODE_PTR(id)	&PINS_NODE(id),
-const struct led_pins_node_t *pins_node[] = {
-	DT_FOREACH_CHILD(PWM_LED_PINS_NODE, PINS_NODE_PTR)
-};
+#define PINS_NODE_PTR(id) &PINS_NODE(id),
+const struct led_pins_node_t *pins_node[] = { DT_FOREACH_CHILD(
+	PWM_LED_PINS_NODE, PINS_NODE_PTR) };
 
 /*
  * Set all the PWM channels defined in the node to the defined value,
@@ -83,13 +73,9 @@ const struct led_pins_node_t *pins_node[] = {
  */
 void led_set_color_with_node(const struct led_pins_node_t *pins_node)
 {
+	struct pwm_pin_t *pwm_pins = pins_node->pwm_pins;
 	for (int j = 0; j < pins_node->pins_count; j++) {
-		pwm_set(
-			pins_node->pwm_pins[j].pwm,
-			pins_node->pwm_pins[j].channel,
-			period_ns,
-			pins_node->pwm_pins[j].pulse_ns,
-			pins_node->pwm_pins[j].flags);
+		pwm_set_pulse_dt(&pwm_pins[j].pwm, pwm_pins[j].pulse_ns);
 	}
 }
 
@@ -109,11 +95,18 @@ void led_set_color(enum led_color color, enum ec_led_id led_id)
 
 void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
 {
+	memset(brightness_range, 0, EC_LED_COLOR_COUNT);
+
 	for (int i = 0; i < ARRAY_SIZE(pins_node); i++) {
 		int br_color = pins_node[i]->br_color;
 
-		if (br_color != -1)
+		if (pins_node[i]->led_id != led_id) {
+			continue;
+		}
+
+		if (br_color != -1) {
 			brightness_range[br_color] = 100;
+		}
 	}
 }
 
@@ -124,6 +117,10 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 	for (int i = 0; i < ARRAY_SIZE(pins_node); i++) {
 		int br_color = pins_node[i]->br_color;
 
+		if (pins_node[i]->led_id != led_id) {
+			continue;
+		}
+
 		if ((br_color != -1) && (brightness[br_color] != 0)) {
 			color_set = true;
 			led_set_color(pins_node[i]->led_color, led_id);
diff --git a/zephyr/shim/src/libgcc_arm.S b/zephyr/shim/src/libgcc_arm.S
index ffdbefc675..9e087ecf5f 100644
--- a/zephyr/shim/src/libgcc_arm.S
+++ b/zephyr/shim/src/libgcc_arm.S
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/shim/src/log_backend_console_buffer.c b/zephyr/shim/src/log_backend_console_buffer.c
new file mode 100644
index 0000000000..cafb690b87
--- /dev/null
+++ b/zephyr/shim/src/log_backend_console_buffer.c
@@ -0,0 +1,56 @@
+/* Copyright 2022 The ChromiumOS Authors.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/logging/log_backend.h>
+#include <zephyr/logging/log_output.h>
+#include <zephyr/logging/log_backend_std.h>
+
+#include "console.h"
+
+static uint8_t
+	char_out_buf[CONFIG_PLATFORM_EC_LOG_BACKEND_CONSOLE_BUFFER_TMP_BUF_SIZE];
+
+static int char_out(uint8_t *data, size_t length, void *ctx)
+{
+	/*
+	 * console_buf_notify_chars uses a mutex, which may not be
+	 * locked in ISRs.
+	 */
+	if (k_is_in_isr())
+		return 0;
+	return console_buf_notify_chars(data, length);
+}
+LOG_OUTPUT_DEFINE(log_output_console_buffer, char_out, char_out_buf,
+		  sizeof(char_out_buf));
+
+static void process(const struct log_backend *const backend,
+		    union log_msg_generic *msg)
+{
+	uint32_t flags = log_backend_std_get_flags();
+	log_format_func_t log_output_func =
+		log_format_func_t_get(LOG_OUTPUT_TEXT);
+	log_output_func(&log_output_console_buffer, &msg->log, flags);
+}
+
+static void panic(struct log_backend const *const backend)
+{
+	log_backend_std_panic(&log_output_console_buffer);
+}
+
+static void dropped(const struct log_backend *const backend, uint32_t cnt)
+{
+	log_backend_std_dropped(&log_output_console_buffer, cnt);
+}
+
+const struct log_backend_api log_backend_console_buffer_api = {
+	.process = process,
+	.panic = panic,
+	.dropped = IS_ENABLED(CONFIG_LOG_MODE_DEFERRED) ? dropped : NULL,
+	/* TODO(b/244170593): Support switching output formats */
+	.format_set = NULL,
+};
+
+LOG_BACKEND_DEFINE(log_backend_console_buffer, log_backend_console_buffer_api,
+		   true);
diff --git a/zephyr/shim/src/mkbp_event.c b/zephyr/shim/src/mkbp_event.c
index 39bcb001b8..ac39d14120 100644
--- a/zephyr/shim/src/mkbp_event.c
+++ b/zephyr/shim/src/mkbp_event.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,7 +7,8 @@
 
 const struct mkbp_event_source *zephyr_find_mkbp_event_source(uint8_t type)
 {
-	STRUCT_SECTION_FOREACH(mkbp_event_source, evtsrc) {
+	STRUCT_SECTION_FOREACH(mkbp_event_source, evtsrc)
+	{
 		if (evtsrc->event_type == type)
 			return evtsrc;
 	}
diff --git a/zephyr/shim/src/motionsense_driver/bma255-drvinfo.inc b/zephyr/shim/src/motionsense_driver/bma255-drvinfo.inc
index 7db46811ad..a16c4f0fbc 100644
--- a/zephyr/shim/src/motionsense_driver/bma255-drvinfo.inc
+++ b/zephyr/shim/src/motionsense_driver/bma255-drvinfo.inc
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/shim/src/motionsense_driver/bma4xx-drvinfo.inc b/zephyr/shim/src/motionsense_driver/bma4xx-drvinfo.inc
index 2d40c55de7..3d02e5db70 100644
--- a/zephyr/shim/src/motionsense_driver/bma4xx-drvinfo.inc
+++ b/zephyr/shim/src/motionsense_driver/bma4xx-drvinfo.inc
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/shim/src/motionsense_driver/bmi160-drvinfo.inc b/zephyr/shim/src/motionsense_driver/bmi160-drvinfo.inc
index dd7b21641b..36d20db7be 100644
--- a/zephyr/shim/src/motionsense_driver/bmi160-drvinfo.inc
+++ b/zephyr/shim/src/motionsense_driver/bmi160-drvinfo.inc
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/shim/src/motionsense_driver/bmi260-drvinfo.inc b/zephyr/shim/src/motionsense_driver/bmi260-drvinfo.inc
index 2457fca31a..72bfc5b4b3 100644
--- a/zephyr/shim/src/motionsense_driver/bmi260-drvinfo.inc
+++ b/zephyr/shim/src/motionsense_driver/bmi260-drvinfo.inc
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/shim/src/motionsense_driver/bmi3xx-drvinfo.inc b/zephyr/shim/src/motionsense_driver/bmi3xx-drvinfo.inc
index ce6f686cc2..c28f5c1786 100644
--- a/zephyr/shim/src/motionsense_driver/bmi3xx-drvinfo.inc
+++ b/zephyr/shim/src/motionsense_driver/bmi3xx-drvinfo.inc
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/shim/src/motionsense_driver/drvdata-accelgyro.h b/zephyr/shim/src/motionsense_driver/drvdata-accelgyro.h
index 069587f90f..ab2f08a496 100644
--- a/zephyr/shim/src/motionsense_driver/drvdata-accelgyro.h
+++ b/zephyr/shim/src/motionsense_driver/drvdata-accelgyro.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -23,28 +23,27 @@
  *		cover-scale = <1>;
  *	};
  */
-#define ACCELGYRO_ALS_CHANNEL_SCALE(id)					\
-	{								\
-		.k_channel_scale =					\
-			ALS_CHANNEL_SCALE(DT_PROP(id, k_channel_scale)),\
-		.cover_scale =						\
-			ALS_CHANNEL_SCALE(DT_PROP(id, cover_scale)),	\
+#define ACCELGYRO_ALS_CHANNEL_SCALE(id)                                     \
+	{                                                                   \
+		.k_channel_scale =                                          \
+			ALS_CHANNEL_SCALE(DT_PROP(id, k_channel_scale)),    \
+		.cover_scale = ALS_CHANNEL_SCALE(DT_PROP(id, cover_scale)), \
 	}
 
-#define ALS_CALIBRATION_CHANNEL_SCALE(id)				\
+#define ALS_CALIBRATION_CHANNEL_SCALE(id) \
 	.als_cal.channel_scale = ACCELGYRO_ALS_CHANNEL_SCALE(id),
 
-#define ALS_CALIBRATION_SET(id)					\
-	.als_cal.scale = DT_PROP(id, scale),			\
-	.als_cal.uscale = DT_PROP(id, uscale),			\
-	.als_cal.offset = DT_PROP(id, offset),			\
+#define ALS_CALIBRATION_SET(id)                \
+	.als_cal.scale = DT_PROP(id, scale),   \
+	.als_cal.uscale = DT_PROP(id, uscale), \
+	.als_cal.offset = DT_PROP(id, offset), \
 	ALS_CALIBRATION_CHANNEL_SCALE(DT_CHILD(id, als_channel_scale))
 
 /*
  * compatible = "cros-ec,accelgyro-als-drv-data"
  * als_drv_data_t in accelgyro.h
  *
- * e.g) The following is the example in DT for als_drv_data_t 
+ * e.g) The following is the example in DT for als_drv_data_t
  * als-drv-data {
  *	compatible = "cros-ec,accelgyro-als-drv-data";
  *	als-cal {
@@ -59,22 +58,21 @@
  *	};
  * };
  */
-#define ACCELGYRO_ALS_DRV_DATA(id)					\
-	{								\
-		ALS_CALIBRATION_SET(DT_CHILD(id, als_cal))		\
+#define ACCELGYRO_ALS_DRV_DATA(id)                         \
+	{                                                  \
+		ALS_CALIBRATION_SET(DT_CHILD(id, als_cal)) \
 	}
 
-#define RGB_CAL_RGB_SET_SCALE(id)			\
-	.scale = ACCELGYRO_ALS_CHANNEL_SCALE(id),
+#define RGB_CAL_RGB_SET_SCALE(id) .scale = ACCELGYRO_ALS_CHANNEL_SCALE(id),
 
-#define RGB_CAL_RGB_SET_ONE(id, suffix)					\
-	.rgb_cal[suffix] = {						\
-	    .offset = DT_PROP(id, offset),				\
-	    .coeff[0] = FLOAT_TO_FP(DT_PROP_BY_IDX(id, coeff, 0)),	\
-	    .coeff[1] = FLOAT_TO_FP(DT_PROP_BY_IDX(id, coeff, 1)),	\
-	    .coeff[2] = FLOAT_TO_FP(DT_PROP_BY_IDX(id, coeff, 2)),	\
-	    .coeff[3] = FLOAT_TO_FP(DT_PROP_BY_IDX(id, coeff, 3)),	\
-	    RGB_CAL_RGB_SET_SCALE(DT_CHILD(id, als_channel_scale))	\
+#define RGB_CAL_RGB_SET_ONE(id, suffix)                                \
+	.rgb_cal[suffix] = {                                           \
+		.offset = DT_PROP(id, offset),                         \
+		.coeff[0] = FLOAT_TO_FP(DT_PROP_BY_IDX(id, coeff, 0)), \
+		.coeff[1] = FLOAT_TO_FP(DT_PROP_BY_IDX(id, coeff, 1)), \
+		.coeff[2] = FLOAT_TO_FP(DT_PROP_BY_IDX(id, coeff, 2)), \
+		.coeff[3] = FLOAT_TO_FP(DT_PROP_BY_IDX(id, coeff, 3)), \
+		RGB_CAL_RGB_SET_SCALE(DT_CHILD(id, als_channel_scale)) \
 	},
 
 /*
@@ -116,12 +114,12 @@
  *	};
  * };
  */
-#define ACCELGYRO_RGB_CALIBRATION(id)				\
-	{							\
-		RGB_CAL_RGB_SET_ONE(DT_CHILD(id, rgb_cal_x), X)	\
-		RGB_CAL_RGB_SET_ONE(DT_CHILD(id, rgb_cal_y), Y)	\
-		RGB_CAL_RGB_SET_ONE(DT_CHILD(id, rgb_cal_z), Z)	\
-		.irt = INT_TO_FP(DT_PROP(id, irt)),		\
+#define ACCELGYRO_RGB_CALIBRATION(id)                                 \
+	{                                                             \
+		RGB_CAL_RGB_SET_ONE(DT_CHILD(id, rgb_cal_x), X)       \
+		RGB_CAL_RGB_SET_ONE(DT_CHILD(id, rgb_cal_y), Y)       \
+		RGB_CAL_RGB_SET_ONE(DT_CHILD(id, rgb_cal_z), Z).irt = \
+			INT_TO_FP(DT_PROP(id, irt)),                  \
 	}
 
 #endif /* __ZEPHYR_SHIM_SRC_MOTIONSENSE_DRIVER_DRVDATA_ACCELGYRO_H */
diff --git a/zephyr/shim/src/motionsense_driver/icm42607-drvinfo.inc b/zephyr/shim/src/motionsense_driver/icm42607-drvinfo.inc
index e8199eaacf..ede16342ea 100644
--- a/zephyr/shim/src/motionsense_driver/icm42607-drvinfo.inc
+++ b/zephyr/shim/src/motionsense_driver/icm42607-drvinfo.inc
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/shim/src/motionsense_driver/icm426xx-drvinfo.inc b/zephyr/shim/src/motionsense_driver/icm426xx-drvinfo.inc
index 5513ff934c..d949829750 100644
--- a/zephyr/shim/src/motionsense_driver/icm426xx-drvinfo.inc
+++ b/zephyr/shim/src/motionsense_driver/icm426xx-drvinfo.inc
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/shim/src/motionsense_driver/kx022-drvinfo.inc b/zephyr/shim/src/motionsense_driver/kx022-drvinfo.inc
index 800a9a1543..26885230e1 100644
--- a/zephyr/shim/src/motionsense_driver/kx022-drvinfo.inc
+++ b/zephyr/shim/src/motionsense_driver/kx022-drvinfo.inc
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/shim/src/motionsense_driver/lis2dw12-drvinfo.inc b/zephyr/shim/src/motionsense_driver/lis2dw12-drvinfo.inc
index 433a9d4192..4605fcd749 100644
--- a/zephyr/shim/src/motionsense_driver/lis2dw12-drvinfo.inc
+++ b/zephyr/shim/src/motionsense_driver/lis2dw12-drvinfo.inc
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/shim/src/motionsense_driver/lsm6dsm-drvinfo.inc b/zephyr/shim/src/motionsense_driver/lsm6dsm-drvinfo.inc
new file mode 100644
index 0000000000..32faaa087f
--- /dev/null
+++ b/zephyr/shim/src/motionsense_driver/lsm6dsm-drvinfo.inc
@@ -0,0 +1,57 @@
+/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/accelgyro_lsm6dsm.h"
+#include "driver/stm_mems_common.h"
+
+/*
+ * CREATE_SENSOR_DATA which is defined in motionsense_sensors.c is
+ * the helper to create sensor driver specific data.
+ *
+ * CREATE_SENSOR_DATA gets two arguments. One is the compatible
+ * property value specified in device tree and the other one is the macro
+ * that actually creates sensor driver specific data. The macro gets
+ * node id and the name to be used for the sensor driver data.
+ */
+
+/*
+ * Create driver data. This must be a separate instance for
+ * each entry of the lsm6dsm device in the motion_sensors array.
+ */
+#define CREATE_SENSOR_DATA_LSM6DSM(id, drvdata_name) \
+	static struct lsm6dsm_data drvdata_name = LSM6DSM_DATA;
+
+/*
+ * Create driver data for each lsm6dsm drvinfo instance in device tree.
+ * (compatible = "cros-ec,drvdata-lsm6dsm")
+ */
+CREATE_SENSOR_DATA(cros_ec_drvdata_lsm6dsm, CREATE_SENSOR_DATA_LSM6DSM)
+/*
+ * CREATE_MOTION_SENSOR which is defined in motionsense_sensors.c is
+ * the macro to create an entry in motion_sensors array.
+ * The macro gets value of compatible property of
+ * the sensor in device tree and sensor specific values like chip ID,
+ * type of sensor, name of driver, default min/max frequency.
+ * Then using the values, it creates the corresponding motion_sense_t entry
+ * in motion_sensors array.
+ */
+
+/*
+ * Here, we call CREATE_MOTION_SENSOR to create a motion_sensor_t entry
+ * for each lsm6dsm accel instance(compatible = "cros-ec,lsm6dsm-accel")
+ * in device tree.
+ */
+CREATE_MOTION_SENSOR(cros_ec_lsm6dsm_accel, MOTIONSENSE_CHIP_LSM6DSM, \
+		MOTIONSENSE_TYPE_ACCEL,	lsm6dsm_drv, \
+		LSM6DSM_ODR_MIN_VAL, LSM6DSM_ODR_MAX_VAL)
+
+/*
+ * Here, we call CREATE_MOTION_SENSOR to create a motion_sensor_t entry
+ * for each lsm6dsm gyro instance (compatible = "cros-ec,lsm6dsm-gyro")
+ * in device tree.
+ */
+CREATE_MOTION_SENSOR(cros_ec_lsm6dsm_gyro, MOTIONSENSE_CHIP_LSM6DSM, \
+		MOTIONSENSE_TYPE_GYRO, lsm6dsm_drv, \
+		LSM6DSM_ODR_MIN_VAL, LSM6DSM_ODR_MAX_VAL)
diff --git a/zephyr/shim/src/motionsense_driver/lsm6dso-drvinfo.inc b/zephyr/shim/src/motionsense_driver/lsm6dso-drvinfo.inc
index a759993ba4..dfffa2fe2a 100644
--- a/zephyr/shim/src/motionsense_driver/lsm6dso-drvinfo.inc
+++ b/zephyr/shim/src/motionsense_driver/lsm6dso-drvinfo.inc
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,8 +17,8 @@
  */
 
 /*
- * Create driver data. It can be shared among the entries in
- * motion_sensors array which are using the same lsm6dso driver.
+ * Create driver data. This must be a separate instance for
+ * each entry of the lsm6dso device in the motion_sensors array.
  */
 #define CREATE_SENSOR_DATA_LSM6DSO(id, drvdata_name) \
 	static struct stprivate_data drvdata_name;
diff --git a/zephyr/shim/src/motionsense_driver/sensor_drv_list.inc b/zephyr/shim/src/motionsense_driver/sensor_drv_list.inc
index 2b70a6ec16..1ea1ba2a2d 100644
--- a/zephyr/shim/src/motionsense_driver/sensor_drv_list.inc
+++ b/zephyr/shim/src/motionsense_driver/sensor_drv_list.inc
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -52,3 +52,6 @@
 #ifdef CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSO
 #include "lsm6dso-drvinfo.inc"
 #endif
+#ifdef CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSM
+#include "lsm6dsm-drvinfo.inc"
+#endif
diff --git a/zephyr/shim/src/motionsense_driver/tcs3400-drvinfo.inc b/zephyr/shim/src/motionsense_driver/tcs3400-drvinfo.inc
index 346688d646..9d42860ac7 100644
--- a/zephyr/shim/src/motionsense_driver/tcs3400-drvinfo.inc
+++ b/zephyr/shim/src/motionsense_driver/tcs3400-drvinfo.inc
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/shim/src/motionsense_sensors.c b/zephyr/shim/src/motionsense_sensors.c
index f0b76adf33..8d886192ac 100644
--- a/zephyr/shim/src/motionsense_sensors.c
+++ b/zephyr/shim/src/motionsense_sensors.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -13,11 +13,11 @@
 
 LOG_MODULE_REGISTER(shim_cros_motionsense_sensors);
 
-#define SENSOR_MUTEX_NODE		DT_PATH(motionsense_mutex)
-#define SENSOR_MUTEX_NAME(id)		DT_CAT(MUTEX_, id)
+#define SENSOR_MUTEX_NODE DT_PATH(motionsense_mutex)
+#define SENSOR_MUTEX_NAME(id) DT_CAT(MUTEX_, id)
 
 #if DT_NODE_EXISTS(SENSOR_MUTEX_NODE)
-#define DECLARE_SENSOR_MUTEX(id)	K_MUTEX_DEFINE(SENSOR_MUTEX_NAME(id));
+#define DECLARE_SENSOR_MUTEX(id) K_MUTEX_DEFINE(SENSOR_MUTEX_NAME(id));
 
 /*
  * Declare mutex for
@@ -28,18 +28,12 @@ LOG_MODULE_REGISTER(shim_cros_motionsense_sensors);
 DT_FOREACH_CHILD(SENSOR_MUTEX_NODE, DECLARE_SENSOR_MUTEX)
 #endif /* DT_NODE_EXISTS(SENSOR_MUTEX_NODE) */
 
-#define MAT_ITEM(i, id)	FLOAT_TO_FP((int32_t)(DT_PROP_BY_IDX(id, mat33, i)))
-#define DECLARE_SENSOR_ROT_REF(id)					\
-	const mat33_fp_t SENSOR_ROT_STD_REF_NAME(id) = {	\
-		{							\
-			FOR_EACH_FIXED_ARG(MAT_ITEM, (,), id, 0, 1, 2)	\
-		},							\
-		{							\
-			FOR_EACH_FIXED_ARG(MAT_ITEM, (,), id, 3, 4, 5)	\
-		},							\
-		{							\
-			FOR_EACH_FIXED_ARG(MAT_ITEM, (,), id, 6, 7, 8)	\
-		},							\
+#define MAT_ITEM(i, id) FLOAT_TO_FP((int32_t)(DT_PROP_BY_IDX(id, mat33, i)))
+#define DECLARE_SENSOR_ROT_REF(id)                                   \
+	const mat33_fp_t SENSOR_ROT_STD_REF_NAME(id) = {             \
+		{ FOR_EACH_FIXED_ARG(MAT_ITEM, (, ), id, 0, 1, 2) }, \
+		{ FOR_EACH_FIXED_ARG(MAT_ITEM, (, ), id, 3, 4, 5) }, \
+		{ FOR_EACH_FIXED_ARG(MAT_ITEM, (, ), id, 6, 7, 8) }, \
 	};
 
 /*
@@ -59,12 +53,12 @@ DT_FOREACH_CHILD(SENSOR_ROT_REF_NODE, DECLARE_SENSOR_ROT_REF)
  *
  * A driver data can be shared among the motion sensors.
  */
-#define SENSOR_DATA_NAME(id)		DT_CAT(SENSOR_DAT_, id)
-#define SENSOR_DATA_NODE		DT_PATH(motionsense_sensor_data)
+#define SENSOR_DATA_NAME(id) DT_CAT(SENSOR_DAT_, id)
+#define SENSOR_DATA_NODE DT_PATH(motionsense_sensor_data)
 
-#define SENSOR_DATA(inst, compat, create_data_macro)			\
-	create_data_macro(DT_INST(inst, compat),			\
-		SENSOR_DATA_NAME(DT_INST(inst, compat)))
+#define SENSOR_DATA(inst, compat, create_data_macro) \
+	create_data_macro(DT_INST(inst, compat),     \
+			  SENSOR_DATA_NAME(DT_INST(inst, compat)))
 
 /*
  * CREATE_SENSOR_DATA is a helper macro that gets
@@ -93,17 +87,17 @@ DT_FOREACH_CHILD(SENSOR_ROT_REF_NODE, DECLARE_SENSOR_ROT_REF)
  * CREATE_SENSOR_DATA(cros_ec_drvdata_tcs3400_clear,   \
  *                    CREATE_SENSOR_DATA_TCS3400_CLEAR)
  */
-#define CREATE_SENSOR_DATA(compat, create_data_macro)			\
-	LISTIFY(DT_NUM_INST_STATUS_OKAY(compat), SENSOR_DATA, (),	\
-		compat, create_data_macro)
+#define CREATE_SENSOR_DATA(compat, create_data_macro)                     \
+	LISTIFY(DT_NUM_INST_STATUS_OKAY(compat), SENSOR_DATA, (), compat, \
+		create_data_macro)
 
 /*
  * sensor_drv_list.inc is included three times in this file. This is the first
  * time and it is for creating sensor driver-specific data. So we ignore
  * CREATE_MOTION_SENSOR() that creates motion sensor at this time.
  */
-#define CREATE_MOTION_SENSOR(s_compat, s_chip, s_type, s_drv,		\
-		s_min_freq, s_max_freq)
+#define CREATE_MOTION_SENSOR(s_compat, s_chip, s_type, s_drv, s_min_freq, \
+			     s_max_freq)
 
 /*
  * Here, we declare all sensor driver data. How to create the data is
@@ -119,33 +113,31 @@ DT_FOREACH_CHILD(SENSOR_ROT_REF_NODE, DECLARE_SENSOR_ROT_REF)
  * See motionsense-sensor-base.yaml and cros-ec,motionsense-mutex.yaml
  * for DT example and details.
  */
-#define SENSOR_MUTEX(id)						\
-	IF_ENABLED(DT_NODE_HAS_PROP(id, mutex),				\
-		(.mutex = &SENSOR_MUTEX_NAME(DT_PHANDLE(id, mutex)),))
+#define SENSOR_MUTEX(id)                        \
+	IF_ENABLED(DT_NODE_HAS_PROP(id, mutex), \
+		   (.mutex = &SENSOR_MUTEX_NAME(DT_PHANDLE(id, mutex)), ))
 
 /*
  * Set the interrupt pin which is referred by the phandle.
  */
-#define SENSOR_INT_SIGNAL(id)						\
-	IF_ENABLED(DT_NODE_HAS_PROP(id, int_signal),			\
-		(.int_signal = GPIO_SIGNAL(DT_PHANDLE(id, int_signal)),))
+#define SENSOR_INT_SIGNAL(id)                        \
+	IF_ENABLED(DT_NODE_HAS_PROP(id, int_signal), \
+		   (.int_signal = GPIO_SIGNAL(DT_PHANDLE(id, int_signal)), ))
 
 /*
  * Set flags based on values defined in the node.
  */
-#define SENSOR_FLAGS(id)						\
-	.flags = 0							\
-	IF_ENABLED(DT_NODE_HAS_PROP(id, int_signal),			\
-		(|MOTIONSENSE_FLAG_INT_SIGNAL))			\
-	,
+#define SENSOR_FLAGS(id)                                        \
+	.flags = 0 IF_ENABLED(DT_NODE_HAS_PROP(id, int_signal), \
+			      (| MOTIONSENSE_FLAG_INT_SIGNAL)),
 
 /*
  * Get I2C port number which is referred by phandle.
  * See motionsense-sensor-base.yaml for DT example and details.
  */
-#define SENSOR_I2C_PORT(id)						\
-	IF_ENABLED(DT_NODE_HAS_PROP(id, port),				\
-		(.port = I2C_PORT(DT_PHANDLE(id, port)),))
+#define SENSOR_I2C_PORT(id)                    \
+	IF_ENABLED(DT_NODE_HAS_PROP(id, port), \
+		   (.port = I2C_PORT(DT_PHANDLE(id, port)), ))
 
 /*
  * Get I2C or SPI address.
@@ -161,75 +153,74 @@ DT_FOREACH_CHILD(SENSOR_ROT_REF_NODE, DECLARE_SENSOR_ROT_REF)
  * See motionsense-sensor-base.yaml and cros-ec,motionsense-rotation-ref.yaml
  * for DT example and details.
  */
-#define SENSOR_ROT_STD_REF(id)						\
-	IF_ENABLED(DT_NODE_HAS_PROP(id, rot_standard_ref),		\
-		(.rot_standard_ref =					\
-		 &SENSOR_ROT_STD_REF_NAME(DT_PHANDLE(id, rot_standard_ref)),))
+#define SENSOR_ROT_STD_REF(id)                                    \
+	IF_ENABLED(DT_NODE_HAS_PROP(id, rot_standard_ref),        \
+		   (.rot_standard_ref = &SENSOR_ROT_STD_REF_NAME( \
+			    DT_PHANDLE(id, rot_standard_ref)), ))
 
 /*
  * Get the address of driver-specific data which is referred by phandle.
  * See motionsense-sensor-base.yaml for DT example and details.
  */
-#define SENSOR_DRV_DATA(id)						\
-	IF_ENABLED(DT_NODE_HAS_PROP(id, drv_data),			\
-		   (.drv_data = &SENSOR_DATA_NAME(DT_PHANDLE(id, drv_data)),))
+#define SENSOR_DRV_DATA(id)                        \
+	IF_ENABLED(DT_NODE_HAS_PROP(id, drv_data), \
+		   (.drv_data =                    \
+			    &SENSOR_DATA_NAME(DT_PHANDLE(id, drv_data)), ))
 
 /*
  * Get odr and ec_rate for the motion sensor.
  * See motionsense-sensor-base.yaml and cros-ec,motionsense-sensor-config.yaml
  * for DT example and details.
  */
-#define SET_CONFIG_EC(cfg_id, cfg_suffix)				\
-	[SENSOR_CONFIG_##cfg_suffix] = {				\
-		IF_ENABLED(DT_NODE_HAS_PROP(cfg_id, odr),		\
-		   (.odr = DT_PROP(cfg_id, odr),))			\
-		IF_ENABLED(DT_NODE_HAS_PROP(cfg_id, ec_rate),		\
-		   (.ec_rate = DT_PROP(cfg_id, ec_rate),))		\
+#define SET_CONFIG_EC(cfg_id, cfg_suffix)                                   \
+	[SENSOR_CONFIG_##cfg_suffix] = {                                    \
+		IF_ENABLED(DT_NODE_HAS_PROP(cfg_id, odr),                   \
+			   (.odr = DT_PROP(cfg_id, odr), ))                 \
+			IF_ENABLED(DT_NODE_HAS_PROP(cfg_id, ec_rate),       \
+				   (.ec_rate = DT_PROP(cfg_id, ec_rate), )) \
 	}
 
 /* Get configs */
-#define CREATE_SENSOR_CONFIG(cfgs_id)					      \
-	.config = {							      \
-		IF_ENABLED(DT_NODE_EXISTS(DT_CHILD(cfgs_id, ap)),	      \
-			   (SET_CONFIG_EC(DT_CHILD(cfgs_id, ap), AP),))       \
-		IF_ENABLED(DT_NODE_EXISTS(DT_CHILD(cfgs_id, ec_s0)),	      \
-			   (SET_CONFIG_EC(DT_CHILD(cfgs_id, ec_s0), EC_S0),)) \
-		IF_ENABLED(DT_NODE_EXISTS(DT_CHILD(cfgs_id, ec_s3)),	      \
-			   (SET_CONFIG_EC(DT_CHILD(cfgs_id, ec_s3), EC_S3),)) \
-		IF_ENABLED(DT_NODE_EXISTS(DT_CHILD(cfgs_id, ec_s5)),	      \
-			   (SET_CONFIG_EC(DT_CHILD(cfgs_id, ec_s5), EC_S5),)) \
+#define CREATE_SENSOR_CONFIG(cfgs_id)                                         \
+	.config = {                                                           \
+		IF_ENABLED(DT_NODE_EXISTS(DT_CHILD(cfgs_id, ap)),             \
+			   (SET_CONFIG_EC(DT_CHILD(cfgs_id, ap), AP), ))      \
+			IF_ENABLED(DT_NODE_EXISTS(DT_CHILD(cfgs_id, ec_s0)),  \
+				   (SET_CONFIG_EC(DT_CHILD(cfgs_id, ec_s0),   \
+						  EC_S0), ))                  \
+				IF_ENABLED(DT_NODE_EXISTS(                    \
+						   DT_CHILD(cfgs_id, ec_s3)), \
+					   (SET_CONFIG_EC(DT_CHILD(cfgs_id,   \
+								   ec_s3),    \
+							  EC_S3), ))          \
+					IF_ENABLED(DT_NODE_EXISTS(DT_CHILD(   \
+							   cfgs_id, ec_s5)),  \
+						   (SET_CONFIG_EC(            \
+							    DT_CHILD(cfgs_id, \
+								     ec_s5),  \
+							    EC_S5), ))        \
 	}
 
-#define SENSOR_CONFIG(id)						\
-	IF_ENABLED(DT_NODE_EXISTS(DT_CHILD(id, configs)),		\
-		   (CREATE_SENSOR_CONFIG(DT_CHILD(id, configs)),))
+#define SENSOR_CONFIG(id)                                 \
+	IF_ENABLED(DT_NODE_EXISTS(DT_CHILD(id, configs)), \
+		   (CREATE_SENSOR_CONFIG(DT_CHILD(id, configs)), ))
 
 /* Get and assign the basic information for a motion sensor */
-#define SENSOR_BASIC_INFO(id)						\
-	.name = DT_LABEL(id),						\
-	.active_mask = DT_STRING_TOKEN(id, active_mask),		\
-	.location = DT_STRING_TOKEN(id, location),			\
-	.default_range = DT_PROP(id, default_range),			\
-	SENSOR_I2C_SPI_ADDR_FLAGS(id)					\
-	SENSOR_MUTEX(id)						\
-	SENSOR_I2C_PORT(id)						\
-	SENSOR_ROT_STD_REF(id)						\
-	SENSOR_DRV_DATA(id)						\
-	SENSOR_CONFIG(id)						\
-	SENSOR_INT_SIGNAL(id)						\
-	SENSOR_FLAGS(id)
+#define SENSOR_BASIC_INFO(id)                                                \
+	.name = DT_NODE_FULL_NAME(id),                                       \
+	.active_mask = DT_STRING_TOKEN(id, active_mask),                     \
+	.location = DT_STRING_TOKEN(id, location),                           \
+	.default_range = DT_PROP(id, default_range),                         \
+	SENSOR_I2C_SPI_ADDR_FLAGS(id) SENSOR_MUTEX(id) SENSOR_I2C_PORT(id)   \
+		SENSOR_ROT_STD_REF(id) SENSOR_DRV_DATA(id) SENSOR_CONFIG(id) \
+			SENSOR_INT_SIGNAL(id) SENSOR_FLAGS(id)
 
 /* Create motion sensor node with node ID */
-#define DO_MK_SENSOR_ENTRY(						\
-		id, s_chip, s_type, s_drv, s_min_freq, s_max_freq)	\
-	[SENSOR_ID(id)] = {						\
-		SENSOR_BASIC_INFO(id)					\
-		.chip = s_chip,						\
-		.type = s_type,						\
-		.drv = &s_drv,						\
-		.min_frequency = s_min_freq,				\
-		.max_frequency = s_max_freq				\
-	},
+#define DO_MK_SENSOR_ENTRY(id, s_chip, s_type, s_drv, s_min_freq, s_max_freq) \
+	[SENSOR_ID(id)] = { SENSOR_BASIC_INFO(id).chip = s_chip,              \
+			    .type = s_type, .drv = &s_drv,                    \
+			    .min_frequency = s_min_freq,                      \
+			    .max_frequency = s_max_freq },
 
 /* Construct an entry iff the alternate_for property is missing. */
 #define MK_SENSOR_ENTRY(inst, s_compat, s_chip, s_type, s_drv, s_min_freq,    \
@@ -289,9 +280,9 @@ DT_FOREACH_CHILD(SENSOR_ROT_REF_NODE, DECLARE_SENSOR_ROT_REF)
  *       MOTIONSENSE_TYPE_LIGHT_RGB, tcs3400_rgb_drv, 0, 0)
  * -----------------------------------------------
  */
-#define CREATE_MOTION_SENSOR(s_compat, s_chip, s_type, s_drv,		\
-		s_min_freq, s_max_freq)					\
-	LISTIFY(DT_NUM_INST_STATUS_OKAY(s_compat), MK_SENSOR_ENTRY, (),\
+#define CREATE_MOTION_SENSOR(s_compat, s_chip, s_type, s_drv, s_min_freq, \
+			     s_max_freq)                                  \
+	LISTIFY(DT_NUM_INST_STATUS_OKAY(s_compat), MK_SENSOR_ENTRY, (),   \
 		s_compat, s_chip, s_type, s_drv, s_min_freq, s_max_freq)
 
 /*
@@ -309,10 +300,10 @@ struct motion_sensor_t motion_sensors[] = {
  * of alternate sensors that will be used at runtime.
  */
 #undef CREATE_MOTION_SENSOR
-#define CREATE_MOTION_SENSOR(s_compat, s_chip, s_type, s_drv, s_min_freq,    \
-			     s_max_freq)                                     \
-	LISTIFY(DT_NUM_INST_STATUS_OKAY(s_compat), MK_SENSOR_ALT_ENTRY, (),\
-		     s_compat, s_chip, s_type, s_drv, s_min_freq, s_max_freq)
+#define CREATE_MOTION_SENSOR(s_compat, s_chip, s_type, s_drv, s_min_freq,   \
+			     s_max_freq)                                    \
+	LISTIFY(DT_NUM_INST_STATUS_OKAY(s_compat), MK_SENSOR_ALT_ENTRY, (), \
+		s_compat, s_chip, s_type, s_drv, s_min_freq, s_max_freq)
 
 /*
  * The list of alternate motion sensors that may be used at runtime to replace
@@ -356,12 +347,11 @@ const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
  * };
  */
 #if DT_NODE_HAS_PROP(SENSOR_INFO_NODE, als_sensors)
-#define ALS_SENSOR_ENTRY_WITH_COMMA(i, id)		\
+#define ALS_SENSOR_ENTRY_WITH_COMMA(i, id) \
 	&motion_sensors[SENSOR_ID(DT_PHANDLE_BY_IDX(id, als_sensors, i))],
-const struct motion_sensor_t *motion_als_sensors[] = {
-	LISTIFY(DT_PROP_LEN(SENSOR_INFO_NODE, als_sensors),
-		     ALS_SENSOR_ENTRY_WITH_COMMA, (), SENSOR_INFO_NODE)
-};
+const struct motion_sensor_t *motion_als_sensors[] = { LISTIFY(
+	DT_PROP_LEN(SENSOR_INFO_NODE, als_sensors), ALS_SENSOR_ENTRY_WITH_COMMA,
+	(), SENSOR_INFO_NODE) };
 BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
 #endif
 
@@ -378,28 +368,27 @@ BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT);
  * };
  */
 #if DT_NODE_HAS_PROP(SENSOR_INFO_NODE, sensor_irqs)
-#define SENSOR_GPIO_ENABLE_INTERRUPT(i, id)		\
-	gpio_enable_dt_interrupt(				\
+#define SENSOR_GPIO_ENABLE_INTERRUPT(i, id) \
+	gpio_enable_dt_interrupt(           \
 		GPIO_INT_FROM_NODE(DT_PHANDLE_BY_IDX(id, sensor_irqs, i)));
-static void sensor_enable_irqs(void)
-{
+static void sensor_enable_irqs(void){
 	LISTIFY(DT_PROP_LEN(SENSOR_INFO_NODE, sensor_irqs),
-		     SENSOR_GPIO_ENABLE_INTERRUPT, (), SENSOR_INFO_NODE)
-}
-DECLARE_HOOK(HOOK_INIT, sensor_enable_irqs, HOOK_PRIO_DEFAULT);
+		SENSOR_GPIO_ENABLE_INTERRUPT, (), SENSOR_INFO_NODE)
+} DECLARE_HOOK(HOOK_INIT, sensor_enable_irqs, HOOK_PRIO_DEFAULT);
 #endif
 
 /* Handle the alternative motion sensors */
-#define CHECK_SSFC_AND_ENABLE_ALT_SENSOR(id)                                  \
-	do {                                                                  \
-		if (cros_cbi_ssfc_check_match(CBI_SSFC_VALUE_ID(              \
-				DT_PHANDLE(id, alternate_ssfc_indicator)))) { \
-			LOG_INF("Replacing \"%s\" for \"%s\" based on SSFC",  \
-				motion_sensors[SENSOR_ID(DT_PHANDLE(id,       \
-					alternate_for))].name,                \
-				motion_sensors_alt[SENSOR_ID(id)].name);      \
-			ENABLE_ALT_MOTION_SENSOR(id);                         \
-		}                                                             \
+#define CHECK_SSFC_AND_ENABLE_ALT_SENSOR(id)                                 \
+	do {                                                                 \
+		if (cros_cbi_ssfc_check_match(CBI_SSFC_VALUE_ID(             \
+			    DT_PHANDLE(id, alternate_ssfc_indicator)))) {    \
+			LOG_INF("Replacing \"%s\" for \"%s\" based on SSFC", \
+				motion_sensors[SENSOR_ID(DT_PHANDLE(         \
+						       id, alternate_for))]  \
+					.name,                               \
+				motion_sensors_alt[SENSOR_ID(id)].name);     \
+			ENABLE_ALT_MOTION_SENSOR(id);                        \
+		}                                                            \
 	} while (0)
 
 #define ALT_SENSOR_CHECK_SSFC_ID(id)                                          \
@@ -428,8 +417,7 @@ int motion_sense_probe(enum sensor_alt_id alt_idx)
 	return res;
 }
 
-void motion_sensors_check_ssfc(void)
-{
+void motion_sensors_check_ssfc(void){
 	DT_FOREACH_CHILD(SENSOR_ALT_NODE, ALT_SENSOR_CHECK_SSFC_ID)
 }
 #endif /* DT_NODE_EXISTS(SENSOR_ALT_NODE) */
@@ -440,13 +428,13 @@ void motion_sensors_check_ssfc(void)
 #define DEF_MOTION_ISR_NAME(id) \
 	DEF_MOTION_ISR_NAME_ENUM_WITH_SUFFIX(DEF_MOTION_ISR_NAME_ENUM(id))
 
-#define DEF_MOTION_ISR(id) \
-void DEF_MOTION_ISR_NAME(id)(enum gpio_signal signal)		\
-{								\
-	__ASSERT(motion_sensors[SENSOR_ID(id)].drv->interrupt,	\
-		"No interrupt handler for signal: %x", signal);	\
-	motion_sensors[SENSOR_ID(id)].drv->interrupt(signal);	\
-}
+#define DEF_MOTION_ISR(id)                                               \
+	void DEF_MOTION_ISR_NAME(id)(enum gpio_signal signal)            \
+	{                                                                \
+		__ASSERT(motion_sensors[SENSOR_ID(id)].drv->interrupt,   \
+			 "No interrupt handler for signal: %x", signal); \
+		motion_sensors[SENSOR_ID(id)].drv->interrupt(signal);    \
+	}
 
 #define DEF_MOTION_CHECK_ISR(id) \
 	COND_CODE_1(DT_NODE_HAS_PROP(id, int_signal), (DEF_MOTION_ISR(id)), ())
diff --git a/zephyr/shim/src/panic.c b/zephyr/shim/src/panic.c
index 0685f52ede..20f0e9977e 100644
--- a/zephyr/shim/src/panic.c
+++ b/zephyr/shim/src/panic.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,7 +7,7 @@
 #include <zephyr/fatal.h>
 #include <zephyr/logging/log.h>
 #include <zephyr/logging/log_ctrl.h>
-#include <zephyr/zephyr.h>
+#include <zephyr/kernel.h>
 
 #include "common.h"
 #include "panic.h"
@@ -27,15 +27,37 @@
 
 #if defined(CONFIG_ARM)
 #define PANIC_ARCH PANIC_ARCH_CORTEX_M
-#define PANIC_REG_LIST(M)             \
-	M(basic.r0, cm.frame[0], a1)  \
-	M(basic.r1, cm.frame[1], a2)  \
-	M(basic.r2, cm.frame[2], a3)  \
-	M(basic.r3, cm.frame[3], a4)  \
-	M(basic.r12, cm.frame[4], ip) \
-	M(basic.lr, cm.frame[5], lr)  \
-	M(basic.pc, cm.frame[6], pc)  \
-	M(basic.xpsr, cm.frame[7], xpsr)
+#if defined(CONFIG_EXTRA_EXCEPTION_INFO)
+#define EXTRA_PANIC_REG_LIST(M)                                              \
+	M(extra_info.callee->v1, cm.regs[CORTEX_PANIC_REGISTER_R4], v1)      \
+	M(extra_info.callee->v2, cm.regs[CORTEX_PANIC_REGISTER_R5], v2)      \
+	M(extra_info.callee->v3, cm.regs[CORTEX_PANIC_REGISTER_R6], v3)      \
+	M(extra_info.callee->v4, cm.regs[CORTEX_PANIC_REGISTER_R7], v4)      \
+	M(extra_info.callee->v5, cm.regs[CORTEX_PANIC_REGISTER_R8], v5)      \
+	M(extra_info.callee->v6, cm.regs[CORTEX_PANIC_REGISTER_R9], v6)      \
+	M(extra_info.callee->v7, cm.regs[CORTEX_PANIC_REGISTER_R10], v7)     \
+	M(extra_info.callee->v8, cm.regs[CORTEX_PANIC_REGISTER_R11], v8)     \
+	M(extra_info.callee->psp, cm.regs[CORTEX_PANIC_REGISTER_PSP], psp)   \
+	M(extra_info.exc_return, cm.regs[CORTEX_PANIC_REGISTER_LR], exc_rtn) \
+	M(extra_info.msp, cm.regs[CORTEX_PANIC_REGISTER_MSP], msp)
+/*
+ * IPSR is not copied. IPSR is a subset of xPSR, which is already
+ * captured in PANIC_REG_LIST.
+ */
+#else
+#define EXTRA_PANIC_REG_LIST(M)
+#endif
+/* TODO(b/245423691): Copy other status registers (e.g. CFSR) when available. */
+#define PANIC_REG_LIST(M)                \
+	M(basic.r0, cm.frame[0], a1)     \
+	M(basic.r1, cm.frame[1], a2)     \
+	M(basic.r2, cm.frame[2], a3)     \
+	M(basic.r3, cm.frame[3], a4)     \
+	M(basic.r12, cm.frame[4], ip)    \
+	M(basic.lr, cm.frame[5], lr)     \
+	M(basic.pc, cm.frame[6], pc)     \
+	M(basic.xpsr, cm.frame[7], xpsr) \
+	EXTRA_PANIC_REG_LIST(M)
 #define PANIC_REG_EXCEPTION(pdata) pdata->cm.regs[1]
 #define PANIC_REG_REASON(pdata) pdata->cm.regs[3]
 #define PANIC_REG_INFO(pdata) pdata->cm.regs[4]
@@ -48,13 +70,13 @@
  */
 #define PANIC_ARCH PANIC_ARCH_RISCV_RV32I
 #define PANIC_REG_LIST(M)         \
-	M(ra, riscv.regs[29], ra)  \
-	M(a0, riscv.regs[26], a0)  \
-	M(a1, riscv.regs[25], a1)  \
-	M(a2, riscv.regs[24], a2)  \
-	M(a3, riscv.regs[23], a3)  \
-	M(a4, riscv.regs[22], a4)  \
-	M(a5, riscv.regs[21], a5)  \
+	M(ra, riscv.regs[29], ra) \
+	M(a0, riscv.regs[26], a0) \
+	M(a1, riscv.regs[25], a1) \
+	M(a2, riscv.regs[24], a2) \
+	M(a3, riscv.regs[23], a3) \
+	M(a4, riscv.regs[22], a4) \
+	M(a5, riscv.regs[21], a5) \
 	M(a6, riscv.regs[20], a6) \
 	M(a7, riscv.regs[19], a7) \
 	M(t0, riscv.regs[18], t0) \
@@ -99,8 +121,9 @@ static void copy_esf_to_panic_data(const z_arch_esf_t *esf,
 {
 	pdata->arch = PANIC_ARCH;
 	pdata->struct_version = 2;
-	pdata->flags = (PANIC_ARCH == PANIC_ARCH_CORTEX_M)
-		? PANIC_DATA_FLAG_FRAME_VALID : 0;
+	pdata->flags = (PANIC_ARCH == PANIC_ARCH_CORTEX_M) ?
+			       PANIC_DATA_FLAG_FRAME_VALID :
+			       0;
 	pdata->reserved = 0;
 	pdata->struct_size = sizeof(*pdata);
 	pdata->magic = PANIC_DATA_MAGIC;
@@ -137,7 +160,7 @@ void k_sys_fatal_error_handler(unsigned int reason, const z_arch_esf_t *esf)
 #ifdef CONFIG_PLATFORM_EC_SOFTWARE_PANIC
 void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
 {
-	struct panic_data * const pdata = get_panic_data_write();
+	struct panic_data *const pdata = get_panic_data_write();
 
 	/* Setup panic data structure */
 	memset(pdata, 0, CONFIG_PANIC_DATA_SIZE);
@@ -157,7 +180,7 @@ void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)
 
 void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception)
 {
-	struct panic_data * const pdata = panic_get_data();
+	struct panic_data *const pdata = panic_get_data();
 
 	if (pdata && pdata->struct_version == 2) {
 		*exception = PANIC_REG_EXCEPTION(pdata);
diff --git a/zephyr/shim/src/power.c b/zephyr/shim/src/power.c
index 49f820e567..007c40ab71 100644
--- a/zephyr/shim/src/power.c
+++ b/zephyr/shim/src/power.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,11 +11,8 @@
 
 #if (SYSTEM_DT_POWER_SIGNAL_CONFIG)
 
-const struct power_signal_info power_signal_list[] = {
-	DT_FOREACH_CHILD(
-		POWER_SIGNAL_LIST_NODE,
-		GEN_POWER_SIGNAL_STRUCT)
-};
+const struct power_signal_info power_signal_list[] = { DT_FOREACH_CHILD(
+	POWER_SIGNAL_LIST_NODE, GEN_POWER_SIGNAL_STRUCT) };
 BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
 
 #endif /* SYSTEM_DT_POWER_SIGNAL_CONFIG */
diff --git a/zephyr/shim/src/power_host_sleep_api.c b/zephyr/shim/src/power_host_sleep_api.c
index 1d283e1c3c..99d535bdff 100644
--- a/zephyr/shim/src/power_host_sleep_api.c
+++ b/zephyr/shim/src/power_host_sleep_api.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,8 +7,8 @@
 #include <ap_power/ap_power_interface.h>
 #include <power_host_sleep.h>
 
-static enum power_state translate_ap_power_state(
-	enum power_states_ndsx ap_power_state)
+static enum power_state
+translate_ap_power_state(enum power_states_ndsx ap_power_state)
 {
 	switch (ap_power_state) {
 	case SYS_POWER_STATE_S5:
@@ -24,8 +24,8 @@ static enum power_state translate_ap_power_state(
 	}
 }
 
-int ap_power_get_lazy_wake_mask(
-	enum power_states_ndsx state, host_event_t *mask)
+int ap_power_get_lazy_wake_mask(enum power_states_ndsx state,
+				host_event_t *mask)
 {
 	enum power_state st;
 
@@ -36,9 +36,8 @@ int ap_power_get_lazy_wake_mask(
 }
 
 #if CONFIG_AP_PWRSEQ_HOST_SLEEP
-void power_chipset_handle_host_sleep_event(
-		enum host_sleep_event state,
-		struct host_sleep_event_context *ctx)
+void power_chipset_handle_host_sleep_event(enum host_sleep_event state,
+					   struct host_sleep_event_context *ctx)
 {
 	ap_power_chipset_handle_host_sleep_event(state, ctx);
 }
diff --git a/zephyr/shim/src/ppc.c b/zephyr/shim/src/ppc.c
index c1bf3cb0fd..87161407ae 100644
--- a/zephyr/shim/src/ppc.c
+++ b/zephyr/shim/src/ppc.c
@@ -1,50 +1,52 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include <zephyr/devicetree.h>
 #include "usbc_ppc.h"
+#include "usbc/ppc_aoz1380.h"
+#include "usbc/ppc_nx20p348x.h"
 #include "usbc/ppc_rt1739.h"
 #include "usbc/ppc_sn5s330.h"
 #include "usbc/ppc_syv682x.h"
 #include "usbc/ppc.h"
 
-#if DT_HAS_COMPAT_STATUS_OKAY(RT1739_PPC_COMPAT) || \
-	DT_HAS_COMPAT_STATUS_OKAY(SN5S330_COMPAT) || \
+#if DT_HAS_COMPAT_STATUS_OKAY(AOZ1380_COMPAT) ||        \
+	DT_HAS_COMPAT_STATUS_OKAY(NX20P348X_COMPAT) ||  \
+	DT_HAS_COMPAT_STATUS_OKAY(RT1739_PPC_COMPAT) || \
+	DT_HAS_COMPAT_STATUS_OKAY(SN5S330_COMPAT) ||    \
 	DT_HAS_COMPAT_STATUS_OKAY(SYV682X_COMPAT)
 
-#define PPC_CHIP_PRIM(id, fn)                                \
-	COND_CODE_1(DT_NODE_HAS_PROP(id, alternate_for), (), \
-		    (PPC_CHIP_ELE_PRIM(id, fn)))
+#define PPC_CHIP_ENTRY(usbc_id, ppc_id, config_fn) \
+	[USBC_PORT_NEW(usbc_id)] = config_fn(ppc_id)
 
-#define PPC_CHIP_ALT(id, fn)                             \
-	COND_CODE_1(DT_NODE_HAS_PROP(id, alternate_for), \
-		    (PPC_CHIP_ELE_ALT(id, fn)), ())
+#define CHECK_COMPAT(compat, usbc_id, ppc_id, config_fn) \
+	COND_CODE_1(DT_NODE_HAS_COMPAT(ppc_id, compat),  \
+		    (PPC_CHIP_ENTRY(usbc_id, ppc_id, config_fn)), ())
 
-#define PPC_CHIP_ELE_PRIM(id, fn) [USBC_PORT(id)] = fn(id)
+#define PPC_CHIP_FIND(usbc_id, ppc_id)                                      \
+	CHECK_COMPAT(AOZ1380_COMPAT, usbc_id, ppc_id, PPC_CHIP_AOZ1380)     \
+	CHECK_COMPAT(NX20P348X_COMPAT, usbc_id, ppc_id, PPC_CHIP_NX20P348X) \
+	CHECK_COMPAT(RT1739_PPC_COMPAT, usbc_id, ppc_id, PPC_CHIP_RT1739)   \
+	CHECK_COMPAT(SN5S330_COMPAT, usbc_id, ppc_id, PPC_CHIP_SN5S330)     \
+	CHECK_COMPAT(SYV682X_COMPAT, usbc_id, ppc_id, PPC_CHIP_SYV682X)
 
-#define PPC_CHIP_ELE_ALT(id, fn) [PPC_ID(id)] = fn(id)
+#define PPC_CHIP(usbc_id)                           \
+	COND_CODE_1(DT_NODE_HAS_PROP(usbc_id, ppc), \
+		    (PPC_CHIP_FIND(usbc_id, DT_PHANDLE(usbc_id, ppc))), ())
+
+#define PPC_CHIP_ALT(usbc_id)                                               \
+	COND_CODE_1(DT_NODE_HAS_PROP(usbc_id, ppc_alt),                     \
+		    (PPC_CHIP_FIND(usbc_id, DT_PHANDLE(usbc_id, ppc_alt))), \
+		    ())
+
+struct ppc_config_t ppc_chips[] = { DT_FOREACH_STATUS_OKAY(named_usbc_port,
+							   PPC_CHIP) };
 
-/* Power Path Controller */
-struct ppc_config_t ppc_chips[] = {
-	DT_FOREACH_STATUS_OKAY_VARGS(RT1739_PPC_COMPAT, PPC_CHIP_PRIM,
-				     PPC_CHIP_RT1739)
-	DT_FOREACH_STATUS_OKAY_VARGS(SN5S330_COMPAT, PPC_CHIP_PRIM,
-				     PPC_CHIP_SN5S330)
-	DT_FOREACH_STATUS_OKAY_VARGS(SYV682X_COMPAT, PPC_CHIP_PRIM,
-				     PPC_CHIP_SYV682X)
-};
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
-/* Alt Power Path Controllers */
-struct ppc_config_t ppc_chips_alt[] = {
-	DT_FOREACH_STATUS_OKAY_VARGS(RT1739_PPC_COMPAT, PPC_CHIP_ALT,
-				     PPC_CHIP_RT1739)
-	DT_FOREACH_STATUS_OKAY_VARGS(SN5S330_COMPAT, PPC_CHIP_ALT,
-				     PPC_CHIP_SN5S330)
-	DT_FOREACH_STATUS_OKAY_VARGS(SYV682X_COMPAT, PPC_CHIP_ALT,
-				     PPC_CHIP_SYV682X)
-};
+struct ppc_config_t ppc_chips_alt[] = { DT_FOREACH_STATUS_OKAY(named_usbc_port,
+							       PPC_CHIP_ALT) };
 
 #endif /* #if DT_HAS_COMPAT_STATUS_OKAY */
diff --git a/zephyr/shim/src/pwm_hc.c b/zephyr/shim/src/pwm_hc.c
index 00c8ddf69b..3b1a98f651 100644
--- a/zephyr/shim/src/pwm_hc.c
+++ b/zephyr/shim/src/pwm_hc.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -19,17 +19,15 @@
 
 LOG_MODULE_REGISTER(pwm_shim, LOG_LEVEL_ERR);
 
-#define PWM_RAW_TO_PERCENT(v) \
-	DIV_ROUND_NEAREST((uint32_t)(v) * 100, UINT16_MAX)
-#define PWM_PERCENT_TO_RAW(v) ((uint32_t)(v) * UINT16_MAX / 100)
+#define PWM_RAW_TO_PERCENT(v) DIV_ROUND_NEAREST((uint32_t)(v)*100, UINT16_MAX)
+#define PWM_PERCENT_TO_RAW(v) ((uint32_t)(v)*UINT16_MAX / 100)
 
-#define HAS_PWM_GENERIC_CHANNEL(compat) \
+#define HAS_PWM_GENERIC_CHANNEL(compat)                         \
 	DT_NODE_HAS_PROP(DT_COMPAT_GET_ANY_STATUS_OKAY(compat), \
 			 generic_pwm_channel)
 
 #define PWM_GENERIC_CHANNEL_ID(compat) \
-	DT_PROP(DT_COMPAT_GET_ANY_STATUS_OKAY(compat), \
-		generic_pwm_channel)
+	DT_PROP(DT_COMPAT_GET_ANY_STATUS_OKAY(compat), generic_pwm_channel)
 
 #ifdef CONFIG_PWM_KBLIGHT
 static bool pwm_is_kblight(int type, int index)
@@ -63,9 +61,8 @@ static bool pwm_is_displight(int type, int index)
 }
 #endif /* CONFIG_PLATFORM_EC_PWM_DISPLIGHT */
 
-
-static enum ec_status host_command_pwm_set_duty(
-		struct host_cmd_handler_args *args)
+static enum ec_status
+host_command_pwm_set_duty(struct host_cmd_handler_args *args)
 {
 	__maybe_unused const struct ec_params_pwm_set_duty *p = args->params;
 
@@ -85,12 +82,11 @@ static enum ec_status host_command_pwm_set_duty(
 
 	return EC_RES_INVALID_PARAM;
 }
-DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_DUTY,
-		     host_command_pwm_set_duty,
+DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_DUTY, host_command_pwm_set_duty,
 		     EC_VER_MASK(0));
 
-static enum ec_status host_command_pwm_get_duty(
-		struct host_cmd_handler_args *args)
+static enum ec_status
+host_command_pwm_get_duty(struct host_cmd_handler_args *args)
 {
 	__maybe_unused const struct ec_params_pwm_get_duty *p = args->params;
 	__maybe_unused struct ec_response_pwm_get_duty *r = args->response;
@@ -112,6 +108,5 @@ static enum ec_status host_command_pwm_get_duty(
 
 	return EC_RES_INVALID_PARAM;
 }
-DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_DUTY,
-		     host_command_pwm_get_duty,
+DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_DUTY, host_command_pwm_get_duty,
 		     EC_VER_MASK(0));
diff --git a/zephyr/shim/src/pwm_led.c b/zephyr/shim/src/pwm_led.c
index 09fbd009b4..498c543ffb 100644
--- a/zephyr/shim/src/pwm_led.c
+++ b/zephyr/shim/src/pwm_led.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,111 +22,112 @@ LOG_MODULE_REGISTER(pwm_led, LOG_LEVEL_ERR);
 
 BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) <= 1,
 	     "Multiple CrOS EC PWM LED instances defined");
-BUILD_ASSERT(DT_INST_PROP_LEN(0, leds) <= 2,
+
+#define PWM_LEDS_LEN DT_INST_PROP_LEN(0, leds)
+BUILD_ASSERT((PWM_LEDS_LEN > 0) && (PWM_LEDS_LEN <= 2),
 	     "Unsupported number of LEDs defined");
 
-#define PWM_LED_PERIOD_NS (NSEC_PER_SEC/DT_INST_PROP(0, frequency))
-#define PWM_SIDESEL_PERIOD_NS (PWM_LED_PERIOD_NS * 2)
+#define PWM_LED_0_0_PERIOD \
+	DT_PWMS_PERIOD_BY_IDX(DT_INST_PHANDLE_BY_IDX(0, leds, 0), 0)
+#define PWM_LED_PERIOD_BUILD_ASSERT(node_id, prop, idx, ...)      \
+	BUILD_ASSERT(PWM_LED_0_0_PERIOD ==                        \
+			     DT_PWMS_PERIOD_BY_IDX(node_id, idx), \
+		     "PWM LED period mismatch");
+#define PWM_LEDS_BUILD_ASSERT(node_id, prop, idx)                         \
+	DT_FOREACH_PROP_ELEM_VARGS(DT_PHANDLE_BY_IDX(node_id, prop, idx), \
+				   pwms, PWM_LED_PERIOD_BUILD_ASSERT)
+
+DT_INST_FOREACH_PROP_ELEM(0, leds, PWM_LEDS_BUILD_ASSERT)
 
 #define PWM_LED_NAME(node_id) DT_STRING_UPPER_TOKEN(node_id, ec_led_name)
-#define PWM_LED_NAME_WITH_COMMA(node_id) PWM_LED_NAME(node_id),
 
-const enum ec_led_id supported_led_ids[] = {
-	DT_INST_FOREACH_CHILD(0, PWM_LED_NAME_WITH_COMMA)
-};
+const enum ec_led_id supported_led_ids[] = { DT_INST_FOREACH_CHILD_SEP(
+	0, PWM_LED_NAME, (, )) };
 const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
 
 BUILD_ASSERT(ARRAY_SIZE(supported_led_ids) == DT_INST_PROP_LEN(0, leds),
 	     "Mismatch count of LED device phandles and LED name map entries.");
 
-static void pwm_led_set_duty(const struct pwm_led_dt_channel *ch, int percent)
+static void pwm_led_set_duty(const struct pwm_dt_spec *pwm, int percent)
 {
 	uint32_t pulse_ns;
 	int rv;
 
-	if (!device_is_ready(ch->dev)) {
-		LOG_ERR("PWM device %s not ready", ch->dev->name);
+	if (!device_is_ready(pwm->dev)) {
+		LOG_ERR("PWM device %s not ready", pwm->dev->name);
 		return;
 	}
 
-	pulse_ns = DIV_ROUND_NEAREST(ch->period_ns * percent, 100);
+	pulse_ns = DIV_ROUND_NEAREST(pwm->period * percent, 100);
 
-	LOG_DBG("LED PWM %s set percent (%d), pulse %d", ch->dev->name, percent,
-		pulse_ns);
+	LOG_DBG("LED PWM %s set percent (%d), pulse %d", pwm->dev->name,
+		percent, pulse_ns);
 
-	rv = pwm_set(ch->dev, ch->channel, ch->period_ns, pulse_ns, ch->flags);
+	rv = pwm_set_pulse_dt(pwm, pulse_ns);
 	if (rv) {
-		LOG_ERR("pwm_set() failed %s (%d)", ch->dev->name, rv);
+		LOG_ERR("pwm_set_pulse_dt() failed %s (%d)", pwm->dev->name,
+			rv);
 	}
 }
 
-#define PWM_CHANNEL_DT_BY_IDX_INIT(node_id, led_ch, _period_ns)             \
-	{                                                                   \
-		.dev = DEVICE_DT_GET(DT_PWMS_CTLR_BY_IDX(node_id, led_ch)), \
-		.channel = DT_PWMS_CHANNEL_BY_IDX(node_id, led_ch),         \
-		.flags = DT_PWMS_FLAGS_BY_IDX(node_id, led_ch),             \
-		.period_ns = _period_ns, \
-	}
-
-#define PWM_CHANNEL_DT_BY_IDX(node_id, prop, idx, led_ch)                      \
-	static const struct pwm_led_dt_channel _pwm_led_dt_##idx##_ch_##led_ch = \
-		PWM_CHANNEL_DT_BY_IDX_INIT(                                    \
-			DT_PHANDLE_BY_IDX(node_id, prop, idx), led_ch,         \
-			PWM_LED_PERIOD_NS);
+#define PWM_CHANNEL_DT_BY_IDX(node_id, prop, idx, led_ch)                     \
+	static const struct pwm_dt_spec _pwm_dt_spec_##idx##_ch_##led_ch =    \
+		PWM_DT_SPEC_GET_BY_IDX(DT_PHANDLE_BY_IDX(node_id, prop, idx), \
+				       led_ch);
 
-#define PWM_CHANNEL_DT_BY_IDX_COND(node_id, prop, idx, led_ch)        \
-	IF_ENABLED(DT_PROP_HAS_IDX(                                   \
-		DT_PHANDLE_BY_IDX(node_id, prop, idx), pwms, led_ch), \
-		(PWM_CHANNEL_DT_BY_IDX(node_id, prop, idx, led_ch))   \
-		)
+#define PWM_CHANNEL_DT_BY_IDX_COND(node_id, prop, idx, led_ch)            \
+	IF_ENABLED(DT_PROP_HAS_IDX(DT_PHANDLE_BY_IDX(node_id, prop, idx), \
+				   pwms, led_ch),                         \
+		   (PWM_CHANNEL_DT_BY_IDX(node_id, prop, idx, led_ch)))
 
-#define PWM_LED_DT_INIT(node_id, prop, idx) \
+#define PWM_LED_DT_INIT(node_id, prop, idx)               \
 	PWM_CHANNEL_DT_BY_IDX_COND(node_id, prop, idx, 0) \
 	PWM_CHANNEL_DT_BY_IDX_COND(node_id, prop, idx, 1) \
 	PWM_CHANNEL_DT_BY_IDX_COND(node_id, prop, idx, 2)
 
 DT_INST_FOREACH_PROP_ELEM(0, leds, PWM_LED_DT_INIT)
 
-#define PWM_CHANNEL_BY_IDX_COND(node_id, prop, idx, led_ch)           \
-	COND_CODE_1(DT_PROP_HAS_IDX(                                  \
-		DT_PHANDLE_BY_IDX(node_id, prop, idx), pwms, led_ch), \
-		(&_pwm_led_dt_##idx##_ch_##led_ch), \
-		(PWM_LED_NO_CHANNEL))
+#define PWM_CHANNEL_BY_IDX_COND(node_id, prop, idx, led_ch)                \
+	COND_CODE_1(DT_PROP_HAS_IDX(DT_PHANDLE_BY_IDX(node_id, prop, idx), \
+				    pwms, led_ch),                         \
+		    (&_pwm_dt_spec_##idx##_ch_##led_ch), (PWM_LED_NO_CHANNEL))
 
-#define PWM_LED_INIT(node_id, prop, idx) \
-	[PWM_LED##idx] = { \
+#define PWM_LED_INIT(node_id, prop, idx)                               \
+	[PWM_LED##idx] = {                                             \
 		.ch0 = PWM_CHANNEL_BY_IDX_COND(node_id, prop, idx, 0), \
 		.ch1 = PWM_CHANNEL_BY_IDX_COND(node_id, prop, idx, 1), \
 		.ch2 = PWM_CHANNEL_BY_IDX_COND(node_id, prop, idx, 2), \
-		.set_duty = &pwm_led_set_duty, \
+		.set_duty = &pwm_led_set_duty,                         \
 	},
 
-struct pwm_led pwm_leds[] = {
-	DT_INST_FOREACH_PROP_ELEM(0, leds, PWM_LED_INIT)
-};
+struct pwm_led pwm_leds[] = { DT_INST_FOREACH_PROP_ELEM(0, leds,
+							PWM_LED_INIT) };
 
-#define EC_LED_COLOR_BLANK {0}
+#define EC_LED_COLOR_BLANK \
+	{                  \
+		0          \
+	}
 
 struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = {
-	[EC_LED_COLOR_RED]    = DT_INST_PROP_OR(0, color_map_red,
-						EC_LED_COLOR_BLANK),
-	[EC_LED_COLOR_GREEN]  = DT_INST_PROP_OR(0, color_map_green,
-						EC_LED_COLOR_BLANK),
-	[EC_LED_COLOR_BLUE]   = DT_INST_PROP_OR(0, color_map_blue,
-						EC_LED_COLOR_BLANK),
-	[EC_LED_COLOR_YELLOW] = DT_INST_PROP_OR(0, color_map_yellow,
-						EC_LED_COLOR_BLANK),
-	[EC_LED_COLOR_WHITE]  = DT_INST_PROP_OR(0, color_map_white,
-						EC_LED_COLOR_BLANK),
-	[EC_LED_COLOR_AMBER]  = DT_INST_PROP_OR(0, color_map_amber,
-						EC_LED_COLOR_BLANK),
+	[EC_LED_COLOR_RED] =
+		DT_INST_PROP_OR(0, color_map_red, EC_LED_COLOR_BLANK),
+	[EC_LED_COLOR_GREEN] =
+		DT_INST_PROP_OR(0, color_map_green, EC_LED_COLOR_BLANK),
+	[EC_LED_COLOR_BLUE] =
+		DT_INST_PROP_OR(0, color_map_blue, EC_LED_COLOR_BLANK),
+	[EC_LED_COLOR_YELLOW] =
+		DT_INST_PROP_OR(0, color_map_yellow, EC_LED_COLOR_BLANK),
+	[EC_LED_COLOR_WHITE] =
+		DT_INST_PROP_OR(0, color_map_white, EC_LED_COLOR_BLANK),
+	[EC_LED_COLOR_AMBER] =
+		DT_INST_PROP_OR(0, color_map_amber, EC_LED_COLOR_BLANK),
 };
 
 BUILD_ASSERT(DT_INST_PROP_LEN(0, brightness_range) == EC_LED_COLOR_COUNT,
 	     "brightness_range must have exactly EC_LED_COLOR_COUNT values");
 
-static const uint8_t dt_brigthness_range[EC_LED_COLOR_COUNT] = DT_INST_PROP(
-		0, brightness_range);
+static const uint8_t dt_brigthness_range[EC_LED_COLOR_COUNT] =
+	DT_INST_PROP(0, brightness_range);
 
 void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
 {
@@ -135,8 +136,8 @@ void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
 	       sizeof(dt_brigthness_range));
 }
 
-#define PWM_NAME_TO_ID(node_id) \
-	case PWM_LED_NAME(node_id): \
+#define PWM_NAME_TO_ID(node_id)                \
+	case PWM_LED_NAME(node_id):            \
 		pwm_id = DT_REG_ADDR(node_id); \
 		break;
 
@@ -145,7 +146,7 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 	enum pwm_led_id pwm_id;
 
 	switch (led_id) {
-	DT_INST_FOREACH_CHILD(0, PWM_NAME_TO_ID)
+		DT_INST_FOREACH_CHILD(0, PWM_NAME_TO_ID)
 	default:
 		return EC_ERROR_UNKNOWN;
 	}
@@ -154,19 +155,19 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 	    brightness[EC_LED_COLOR_RED]) {
 		set_pwm_led_color(pwm_id, EC_LED_COLOR_RED);
 	} else if (DT_INST_NODE_HAS_PROP(0, color_map_green) &&
-		 brightness[EC_LED_COLOR_GREEN]) {
+		   brightness[EC_LED_COLOR_GREEN]) {
 		set_pwm_led_color(pwm_id, EC_LED_COLOR_GREEN);
 	} else if (DT_INST_NODE_HAS_PROP(0, color_map_blue) &&
-			brightness[EC_LED_COLOR_BLUE]) {
+		   brightness[EC_LED_COLOR_BLUE]) {
 		set_pwm_led_color(pwm_id, EC_LED_COLOR_BLUE);
 	} else if (DT_INST_NODE_HAS_PROP(0, color_map_yellow) &&
-			brightness[EC_LED_COLOR_YELLOW]) {
+		   brightness[EC_LED_COLOR_YELLOW]) {
 		set_pwm_led_color(pwm_id, EC_LED_COLOR_YELLOW);
 	} else if (DT_INST_NODE_HAS_PROP(0, color_map_white) &&
-			brightness[EC_LED_COLOR_WHITE]) {
+		   brightness[EC_LED_COLOR_WHITE]) {
 		set_pwm_led_color(pwm_id, EC_LED_COLOR_WHITE);
 	} else if (DT_INST_NODE_HAS_PROP(0, color_map_amber) &&
-			brightness[EC_LED_COLOR_AMBER]) {
+		   brightness[EC_LED_COLOR_AMBER]) {
 		set_pwm_led_color(pwm_id, EC_LED_COLOR_AMBER);
 	} else {
 		/* Otherwise, the "color" is "off". */
@@ -178,9 +179,12 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
 
 #if DT_INST_NODE_HAS_PROP(0, sidesel)
 
-static const struct pwm_led_dt_channel _pwm_led_dt_sidesel =
-	PWM_CHANNEL_DT_BY_IDX_INIT(DT_INST_PROP(0, sidesel), 0,
-				   PWM_SIDESEL_PERIOD_NS);
+BUILD_ASSERT((PWM_LED_0_0_PERIOD * 2) ==
+		     DT_PWMS_PERIOD(DT_INST_PROP(0, sidesel)),
+	     "Sidesel PWM period not properly set");
+
+static const struct pwm_dt_spec _pwm_dt_spec_sidesel =
+	PWM_DT_SPEC_GET_BY_IDX(DT_INST_PROP(0, sidesel), 0);
 
 /* Illuminates the LED on the side of the active charging port. If not charging,
  * illuminates both LEDs.
@@ -203,14 +207,14 @@ static void led_set_charge_port_tick(void)
 	}
 
 	if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
-		pwm_led_set_duty(&_pwm_led_dt_sidesel, side_select_duty);
+		pwm_led_set_duty(&_pwm_dt_spec_sidesel, side_select_duty);
 }
 DECLARE_HOOK(HOOK_TICK, led_set_charge_port_tick, HOOK_PRIO_DEFAULT);
 
 static void board_led_init(void)
 {
 	/* Illuminate motherboard and daughter board LEDs equally to start. */
-	pwm_led_set_duty(&_pwm_led_dt_sidesel, 50);
+	pwm_led_set_duty(&_pwm_dt_spec_sidesel, 50);
 }
 DECLARE_HOOK(HOOK_INIT, board_led_init, HOOK_PRIO_DEFAULT);
 
diff --git a/zephyr/shim/src/rtc.c b/zephyr/shim/src/rtc.c
index 9627089f2e..c8a0511c95 100644
--- a/zephyr/shim/src/rtc.c
+++ b/zephyr/shim/src/rtc.c
@@ -1,16 +1,16 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include <zephyr/logging/log.h>
 #include <zephyr/kernel.h>
-#include <zephyr/zephyr.h>
 
 #include "console.h"
 #include "drivers/cros_rtc.h"
 #include "hooks.h"
 #include "host_command.h"
+#include "system.h"
 #include "util.h"
 
 LOG_MODULE_REGISTER(shim_cros_rtc, LOG_LEVEL_ERR);
@@ -135,7 +135,7 @@ void print_system_rtc(enum console_channel ch)
  * chip-specific code. We should factor out the common parts.
  */
 #ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_RTC
-static int command_system_rtc(int argc, char **argv)
+static int command_system_rtc(int argc, const char **argv)
 {
 	if (argc == 3 && !strcasecmp(argv[1], "set")) {
 		char *e;
@@ -160,7 +160,7 @@ DECLARE_CONSOLE_COMMAND(rtc, command_system_rtc, "[set <seconds>]",
 /**
  * Test the RTC alarm by setting an interrupt on RTC match.
  */
-static int command_rtc_alarm_test(int argc, char **argv)
+static int command_rtc_alarm_test(int argc, const char **argv)
 {
 	int s = 1, us = 0;
 	char *e;
diff --git a/zephyr/shim/src/switchcap_gpio.c b/zephyr/shim/src/switchcap_gpio.c
index 18f8344943..91d9de942f 100644
--- a/zephyr/shim/src/switchcap_gpio.c
+++ b/zephyr/shim/src/switchcap_gpio.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -17,19 +17,24 @@
 
 #define SC_PIN_ENABLE_PHANDLE \
 	DT_PHANDLE_BY_IDX(DT_PATH(switchcap), enable_pin, 0)
-#define SC_PIN_ENABLE \
-	GPIO_DT_FROM_NODE(SC_PIN_ENABLE_PHANDLE)
+#define SC_PIN_ENABLE GPIO_DT_FROM_NODE(SC_PIN_ENABLE_PHANDLE)
 
 #define SC_PIN_POWER_GOOD_PHANDLE \
 	DT_PHANDLE_BY_IDX(DT_PATH(switchcap), power_good_pin, 0)
-#define SC_PIN_POWER_GOOD_EXISTS \
-	DT_NODE_EXISTS(SC_PIN_POWER_GOOD_PHANDLE)
-#define SC_PIN_POWER_GOOD \
-	GPIO_DT_FROM_NODE(SC_PIN_POWER_GOOD_PHANDLE)
+#define SC_PIN_POWER_GOOD_EXISTS DT_NODE_EXISTS(SC_PIN_POWER_GOOD_PHANDLE)
+#define SC_PIN_POWER_GOOD GPIO_DT_FROM_NODE(SC_PIN_POWER_GOOD_PHANDLE)
+
+#if DT_NODE_HAS_PROP(DT_PATH(switchcap), poff_delay_ms)
+static const int32_t poff_delay_ms = DT_PROP(DT_PATH(switchcap), poff_delay_ms);
+#else
+static const int32_t poff_delay_ms;
+#endif
 
 void board_set_switchcap_power(int enable)
 {
 	gpio_pin_set_dt(SC_PIN_ENABLE, enable);
+	if (!enable && poff_delay_ms > 0)
+		k_msleep(poff_delay_ms);
 }
 
 int board_is_switchcap_enabled(void)
diff --git a/zephyr/shim/src/switchcap_ln9310.c b/zephyr/shim/src/switchcap_ln9310.c
index bd8612fb2e..ae62617895 100644
--- a/zephyr/shim/src/switchcap_ln9310.c
+++ b/zephyr/shim/src/switchcap_ln9310.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,11 +18,9 @@
 
 #define SC_PIN_ENABLE_PHANDLE \
 	DT_PHANDLE_BY_IDX(DT_PATH(switchcap), enable_pin, 0)
-#define SC_PIN_ENABLE \
-	GPIO_DT_FROM_NODE(SC_PIN_ENABLE_PHANDLE)
+#define SC_PIN_ENABLE GPIO_DT_FROM_NODE(SC_PIN_ENABLE_PHANDLE)
 
-#define SC_PORT_PHANDLE \
-	DT_PHANDLE(DT_PATH(switchcap), port)
+#define SC_PORT_PHANDLE DT_PHANDLE(DT_PATH(switchcap), port)
 #define SC_PORT DT_STRING_UPPER_TOKEN(SC_PORT_PHANDLE, enum_name)
 
 #define SC_ADDR_FLAGS DT_STRING_UPPER_TOKEN(DT_PATH(switchcap), addr_flags)
diff --git a/zephyr/shim/src/system.c b/zephyr/shim/src/system.c
index 807bbd50b0..a9cf544b97 100644
--- a/zephyr/shim/src/system.c
+++ b/zephyr/shim/src/system.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,10 +14,10 @@
 #include "system.h"
 #include "watchdog.h"
 
-#define BBRAM_REGION_PD0	DT_PATH(named_bbram_regions, pd0)
-#define BBRAM_REGION_PD1	DT_PATH(named_bbram_regions, pd1)
-#define BBRAM_REGION_PD2	DT_PATH(named_bbram_regions, pd2)
-#define BBRAM_REGION_TRY_SLOT	DT_PATH(named_bbram_regions, try_slot)
+#define BBRAM_REGION_PD0 DT_PATH(named_bbram_regions, pd0)
+#define BBRAM_REGION_PD1 DT_PATH(named_bbram_regions, pd1)
+#define BBRAM_REGION_PD2 DT_PATH(named_bbram_regions, pd2)
+#define BBRAM_REGION_TRY_SLOT DT_PATH(named_bbram_regions, try_slot)
 
 #define GET_BBRAM_OFFSET(node) \
 	DT_PROP(DT_PATH(named_bbram_regions, node), offset)
@@ -160,7 +160,7 @@ void system_hibernate(uint32_t seconds, uint32_t microseconds)
 /**
  * Print low power idle statistics
  */
-static int command_idle_stats(int argc, char **argv)
+static int command_idle_stats(int argc, const char **argv)
 {
 	const struct device *sys_dev = device_get_binding("CROS_SYSTEM");
 
@@ -172,9 +172,8 @@ static int command_idle_stats(int argc, char **argv)
 	ccprintf("Total time on:                       %.6llds\n", ts.val);
 	return EC_SUCCESS;
 }
-DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats,
-		"",
-		"Print last idle stats");
+DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, "",
+			"Print last idle stats");
 #endif
 
 const char *system_get_chip_vendor(void)
@@ -198,7 +197,7 @@ const char *system_get_chip_revision(void)
 	return cros_system_chip_revision(sys_dev);
 }
 
-void system_reset(int flags)
+test_mockable void system_reset(int flags)
 {
 	int err;
 	uint32_t save_flags;
diff --git a/zephyr/shim/src/tasks.c b/zephyr/shim/src/tasks.c
index 248d5e9607..4143215442 100644
--- a/zephyr/shim/src/tasks.c
+++ b/zephyr/shim/src/tasks.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,9 +15,8 @@
 
 /* Ensure that the idle task is at lower priority than lowest priority task. */
 BUILD_ASSERT(EC_TASK_PRIORITY(EC_TASK_PRIO_LOWEST) < K_IDLE_PRIO,
-	"CONFIG_NUM_PREEMPT_PRIORITIES too small, some tasks would run at "
-	"idle priority");
-
+	     "CONFIG_NUM_PREEMPT_PRIORITIES too small, some tasks would run at "
+	     "idle priority");
 
 /* Declare all task stacks here */
 #define CROS_EC_TASK(name, e, p, size, pr) \
@@ -68,21 +67,19 @@ struct task_ctx_data {
 	struct task_ctx_base_data base;
 };
 
-#define CROS_EC_TASK(_name, _entry, _parameter, _size, _prio)          \
-	{                                                              \
-		.entry = _entry,                                       \
-		.parameter = _parameter,                               \
-		.stack = _name##_STACK,                                \
-		.stack_size = _size,                                   \
-		.priority = EC_TASK_PRIORITY(_prio),                   \
-		COND_CODE_1(CONFIG_THREAD_NAME, (.name = #_name,), ()) \
-	},
+#define CROS_EC_TASK(_name, _entry, _parameter, _size, _prio) \
+	{ .entry = _entry,                                    \
+	  .parameter = _parameter,                            \
+	  .stack = _name##_STACK,                             \
+	  .stack_size = _size,                                \
+	  .priority = EC_TASK_PRIORITY(_prio),                \
+	  COND_CODE_1(CONFIG_THREAD_NAME, (.name = #_name, ), ()) },
 #define TASK_TEST(_name, _entry, _parameter, _size) \
 	CROS_EC_TASK(_name, _entry, _parameter, _size)
 const static struct task_ctx_cfg shimmed_tasks_cfg[TASK_ID_COUNT] = {
 	CROS_EC_TASK_LIST
 #ifdef TEST_BUILD
-	[TASK_ID_TEST_RUNNER] = {},
+		[TASK_ID_TEST_RUNNER] = {},
 #endif
 };
 
@@ -238,8 +235,7 @@ uint32_t task_wait_event_mask(uint32_t event_mask, int timeout_us)
 	return events & event_mask;
 }
 
-static void task_entry(void *task_context_cfg,
-		       void *task_context_data,
+static void task_entry(void *task_context_cfg, void *task_context_data,
 		       void *unused1)
 {
 	ARG_UNUSED(task_context_data);
@@ -299,7 +295,7 @@ void set_test_runner_tid(void)
 }
 
 #ifdef CONFIG_TASKS_SET_TEST_RUNNER_TID_RULE
-#include <ztest.h>
+#include <zephyr/ztest.h>
 static void set_test_runner_tid_rule_before(const struct ztest_unit_test *test,
 					    void *data)
 {
@@ -335,17 +331,11 @@ void start_ec_tasks(void)
 		 * comment in config.h for CONFIG_TASK_LIST for existing flags
 		 * implementation.
 		 */
-		data->zephyr_tid = k_thread_create(
-			&data->zephyr_thread,
-			cfg->stack,
-			cfg->stack_size,
-			task_entry,
-			(void *)cfg,
-			data,
-			NULL,
-			cfg->priority,
-			0,
-			K_NO_WAIT);
+		data->zephyr_tid = k_thread_create(&data->zephyr_thread,
+						   cfg->stack, cfg->stack_size,
+						   task_entry, (void *)cfg,
+						   data, NULL, cfg->priority, 0,
+						   K_NO_WAIT);
 
 #ifdef CONFIG_THREAD_NAME
 		/* Name thread for debugging */
diff --git a/zephyr/shim/src/tcpc.c b/zephyr/shim/src/tcpc.c
index 0f96beff15..cdeeb4771b 100644
--- a/zephyr/shim/src/tcpc.c
+++ b/zephyr/shim/src/tcpc.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,39 +7,67 @@
 #include <zephyr/sys/util.h>
 #include "usb_pd_tcpm.h"
 #include "usb_pd.h"
+#include "usbc/tcpc_anx7447.h"
 #include "usbc/tcpc_ccgxxf.h"
 #include "usbc/tcpc_fusb302.h"
+#include "usbc/tcpc_generic_emul.h"
 #include "usbc/tcpc_it8xxx2.h"
 #include "usbc/tcpc_nct38xx.h"
 #include "usbc/tcpc_ps8xxx.h"
+#include "usbc/tcpc_ps8xxx_emul.h"
+#include "usbc/tcpc_rt1718s.h"
 #include "usbc/tcpci.h"
 #include "usbc/utils.h"
 
-#if DT_HAS_COMPAT_STATUS_OKAY(CCGXXF_TCPC_COMPAT) ||                           \
-	DT_HAS_COMPAT_STATUS_OKAY(FUSB302_TCPC_COMPAT) ||                      \
-	DT_HAS_COMPAT_STATUS_OKAY(IT8XXX2_TCPC_COMPAT) ||                      \
-	DT_HAS_COMPAT_STATUS_OKAY(PS8XXX_COMPAT) ||                            \
-	DT_HAS_COMPAT_STATUS_OKAY(NCT38XX_TCPC_COMPAT) ||                      \
-	DT_HAS_COMPAT_STATUS_OKAY(TCPCI_COMPAT)                                \
-
-#define TCPC_CONFIG(id, fn) [USBC_PORT(id)] = fn(id)
-
-#define MAYBE_CONST COND_CODE_1(CONFIG_PLATFORM_EC_USB_PD_TCPC_RUNTIME_CONFIG, \
-				(), (const))
-
-MAYBE_CONST struct tcpc_config_t tcpc_config[] = {
-	DT_FOREACH_STATUS_OKAY_VARGS(CCGXXF_TCPC_COMPAT, TCPC_CONFIG,
-				     TCPC_CONFIG_CCGXXF)
-	DT_FOREACH_STATUS_OKAY_VARGS(FUSB302_TCPC_COMPAT, TCPC_CONFIG,
-				     TCPC_CONFIG_FUSB302)
-	DT_FOREACH_STATUS_OKAY_VARGS(IT8XXX2_TCPC_COMPAT, TCPC_CONFIG,
-				     TCPC_CONFIG_IT8XXX2)
-	DT_FOREACH_STATUS_OKAY_VARGS(PS8XXX_COMPAT, TCPC_CONFIG,
-				     TCPC_CONFIG_PS8XXX)
-	DT_FOREACH_STATUS_OKAY_VARGS(NCT38XX_TCPC_COMPAT, TCPC_CONFIG,
-				     TCPC_CONFIG_NCT38XX)
-	DT_FOREACH_STATUS_OKAY_VARGS(TCPCI_COMPAT, TCPC_CONFIG,
-				     TCPC_CONFIG_TCPCI)
-};
+#define HAS_TCPC_PROP(usbc_id) \
+	COND_CODE_1(DT_NODE_HAS_PROP(usbc_id, tcpc), (|| 1), ())
+
+#define DT_HAS_TCPC (0 DT_FOREACH_STATUS_OKAY(named_usbc_port, HAS_TCPC_PROP))
+
+#if DT_HAS_TCPC
+
+#define TCPC_CHIP_ENTRY(usbc_id, tcpc_id, config_fn) \
+	[USBC_PORT_NEW(usbc_id)] = config_fn(tcpc_id)
+
+#define CHECK_COMPAT(compat, usbc_id, tcpc_id, config_fn) \
+	COND_CODE_1(DT_NODE_HAS_COMPAT(tcpc_id, compat),  \
+		    (TCPC_CHIP_ENTRY(usbc_id, tcpc_id, config_fn)), ())
+
+#ifdef TEST_BUILD
+#define TCPC_CHIP_FIND_EMUL(usbc_id, tcpc_id)              \
+	CHECK_COMPAT(TCPCI_EMUL_COMPAT, usbc_id, tcpc_id,  \
+		     TCPC_CONFIG_TCPCI_EMUL)               \
+	CHECK_COMPAT(PS8XXX_EMUL_COMPAT, usbc_id, tcpc_id, \
+		     TCPC_CONFIG_PS8XXX_EMUL)
+#else
+#define TCPC_CHIP_FIND_EMUL(...)
+#endif /* TEST_BUILD */
+
+#define TCPC_CHIP_FIND(usbc_id, tcpc_id)                                       \
+	CHECK_COMPAT(ANX7447_TCPC_COMPAT, usbc_id, tcpc_id,                    \
+		     TCPC_CONFIG_ANX7447)                                      \
+	CHECK_COMPAT(CCGXXF_TCPC_COMPAT, usbc_id, tcpc_id, TCPC_CONFIG_CCGXXF) \
+	CHECK_COMPAT(FUSB302_TCPC_COMPAT, usbc_id, tcpc_id,                    \
+		     TCPC_CONFIG_FUSB302)                                      \
+	CHECK_COMPAT(IT8XXX2_TCPC_COMPAT, usbc_id, tcpc_id,                    \
+		     TCPC_CONFIG_IT8XXX2)                                      \
+	CHECK_COMPAT(PS8XXX_COMPAT, usbc_id, tcpc_id, TCPC_CONFIG_PS8XXX)      \
+	CHECK_COMPAT(NCT38XX_TCPC_COMPAT, usbc_id, tcpc_id,                    \
+		     TCPC_CONFIG_NCT38XX)                                      \
+	CHECK_COMPAT(RT1718S_TCPC_COMPAT, usbc_id, tcpc_id,                    \
+		     TCPC_CONFIG_RT1718S)                                      \
+	CHECK_COMPAT(TCPCI_COMPAT, usbc_id, tcpc_id, TCPC_CONFIG_TCPCI)        \
+	TCPC_CHIP_FIND_EMUL(usbc_id, tcpc_id)
+
+#define TCPC_CHIP(usbc_id)                           \
+	COND_CODE_1(DT_NODE_HAS_PROP(usbc_id, tcpc), \
+		    (TCPC_CHIP_FIND(usbc_id, DT_PHANDLE(usbc_id, tcpc))), ())
+
+#define MAYBE_CONST \
+	COND_CODE_1(CONFIG_PLATFORM_EC_USB_PD_TCPC_RUNTIME_CONFIG, (), (const))
+
+/* Type C Port Controllers */
+MAYBE_CONST struct tcpc_config_t tcpc_config[] = { DT_FOREACH_STATUS_OKAY(
+	named_usbc_port, TCPC_CHIP) };
 
 #endif /* DT_HAS_COMPAT_STATUS_OKAY */
diff --git a/zephyr/shim/src/tcpc_nct38xx.c b/zephyr/shim/src/tcpc_nct38xx.c
index f8c73d1aa0..9580759a6c 100644
--- a/zephyr/shim/src/tcpc_nct38xx.c
+++ b/zephyr/shim/src/tcpc_nct38xx.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,20 +8,27 @@
 
 #include "config.h"
 #include "usbc/tcpc_nct38xx.h"
-
-#define TCPC_PORT(id) DT_REG_ADDR(DT_PARENT(id))
+#include "usbc/utils.h"
 
 #define GPIO_DEV_WITH_COMMA(id) DEVICE_DT_GET(DT_PHANDLE(id, gpio_dev)),
 
-#define GPIO_DEV_BINDING(id)                        \
-	COND_CODE_1(DT_NODE_HAS_PROP(id, gpio_dev), \
-		    ([TCPC_PORT(id)] = GPIO_DEV_WITH_COMMA(id)), ())
+#define GPIO_DEV_BINDING(usbc_id, tcpc_id)                                     \
+	COND_CODE_1(DT_NODE_HAS_PROP(tcpc_id, gpio_dev),                       \
+		    ([USBC_PORT_NEW(usbc_id)] = GPIO_DEV_WITH_COMMA(tcpc_id)), \
+		    ())
+
+#define NCT38XX_CHECK(usbc_id, tcpc_id)                           \
+	COND_CODE_1(DT_NODE_HAS_COMPAT(tcpc_id, nuvoton_nct38xx), \
+		    (GPIO_DEV_BINDING(usbc_id, tcpc_id)), ())
+
+#define NCT38XX_GPIO(usbc_id)                        \
+	COND_CODE_1(DT_NODE_HAS_PROP(usbc_id, tcpc), \
+		    (NCT38XX_CHECK(usbc_id, DT_PHANDLE(usbc_id, tcpc))), ())
 
 /* NCT38XX GPIO device pool for binding the TCPC port and NCT38XX GPIO device */
-static const struct device
-	*nct38xx_gpio_devices[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-		DT_FOREACH_STATUS_OKAY(nuvoton_nct38xx, GPIO_DEV_BINDING)
-	};
+static const struct device *nct38xx_gpio_devices[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	DT_FOREACH_STATUS_OKAY(named_usbc_port, NCT38XX_GPIO)
+};
 
 const struct device *nct38xx_get_gpio_device_from_port(const int port)
 {
diff --git a/zephyr/shim/src/temp_sensors.c b/zephyr/shim/src/temp_sensors.c
index 4d8ff28945..371d7d7fc9 100644
--- a/zephyr/shim/src/temp_sensors.c
+++ b/zephyr/shim/src/temp_sensors.c
@@ -1,9 +1,11 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include "adc.h"
+#include "charger/chg_rt9490.h"
+#include "driver/charger/rt9490.h"
 #include "temp_sensor.h"
 #include "temp_sensor/pct2075.h"
 #include "temp_sensor/sb_tsi.h"
@@ -11,24 +13,38 @@
 #include "temp_sensor/thermistor.h"
 #include "temp_sensor/tmp112.h"
 
-#if DT_NODE_EXISTS(DT_PATH(named_temp_sensors))
+#if DT_HAS_COMPAT_STATUS_OKAY(TEMP_SENSORS_COMPAT)
+
+BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(TEMP_SENSORS_COMPAT) == 1,
+	     "Only one temperature sensors node is allowed");
 
 #define GET_POWER_GOOD_PROP(node_id) DT_PROP(node_id, power_good_pin)
 
-#define GET_POWER_GOOD_DEV(node_id)					       \
-		DEVICE_DT_GET(DT_GPIO_CTLR(GET_POWER_GOOD_PROP(node_id),       \
-					   gpios))
+#define GET_POWER_GOOD_DEV(node_id) \
+	DEVICE_DT_GET(DT_GPIO_CTLR(GET_POWER_GOOD_PROP(node_id), gpios))
+
+#define GET_POWER_GOOD_PIN(node_id) \
+	DT_GPIO_PIN(GET_POWER_GOOD_PROP(node_id), gpios)
+
+#define POWER_GOOD_ENTRY(node_id)                      \
+	.power_good_dev = GET_POWER_GOOD_DEV(node_id), \
+	.power_good_pin = GET_POWER_GOOD_PIN(node_id),
 
-#define GET_POWER_GOOD_PIN(node_id) DT_GPIO_PIN(GET_POWER_GOOD_PROP(node_id),  \
-						gpios)
+#define POWER_GOOD_ENTRY_NULL(node_id) \
+	.power_good_dev = NULL, .power_good_pin = 0,
+
+#define POWER_GOOD(node_id)                                \
+	[TEMP_SENSOR_ID(node_id)] = { COND_CODE_1(         \
+		DT_NODE_HAS_PROP(node_id, power_good_pin), \
+		(POWER_GOOD_ENTRY(node_id)),               \
+		(POWER_GOOD_ENTRY_NULL(node_id))) }
 
 #if ANY_INST_HAS_POWER_GOOD_PIN
-#define FILL_POWER_GOOD(node_id) \
-COND_CODE_1(DT_NODE_HAS_PROP(node_id, power_good_pin),			      \
-		(.power_good_dev = GET_POWER_GOOD_DEV(node_id),		      \
-		 .power_good_pin = GET_POWER_GOOD_PIN(node_id), ),	      \
-		(.power_good_dev = NULL,				      \
-		 .power_good_pin = 0, ))
+#define FILL_POWER_GOOD(node_id)                                       \
+	COND_CODE_1(DT_NODE_HAS_PROP(node_id, power_good_pin),         \
+		    (.power_good_dev = GET_POWER_GOOD_DEV(node_id),    \
+		     .power_good_pin = GET_POWER_GOOD_PIN(node_id), ), \
+		    (.power_good_dev = NULL, .power_good_pin = 0, ))
 #else
 #define FILL_POWER_GOOD(node_id)
 #endif /* ANY_INST_HAS_POWER_GOOD_PIN */
@@ -43,137 +59,181 @@ static int thermistor_get_temp(const struct temp_sensor_t *sensor,
 #define GET_THERMISTOR_DATUM(node_sample_id)                                 \
 	[DT_PROP(node_sample_id,                                             \
 		 sample_index)] = { .mv = DT_PROP(node_sample_id, milivolt), \
-				    .temp = DT_PROP(node_sample_id, temp) },
+				    .temp = DT_PROP(node_sample_id, temp) }
 
-#define DEFINE_THERMISTOR_DATA(node_id)                         \
-	static const struct thermistor_data_pair DT_CAT(        \
-		node_id, _thermistor_data)[] = {                \
-		DT_FOREACH_CHILD(node_id, GET_THERMISTOR_DATUM) \
+#define DEFINE_THERMISTOR_DATA(node_id)                                   \
+	static const struct thermistor_data_pair DT_CAT(                  \
+		node_id, _thermistor_data)[] = {                          \
+		DT_FOREACH_CHILD_SEP(node_id, GET_THERMISTOR_DATUM, (, )) \
 	};
 
 #define GET_THERMISTOR_INFO(node_id)                                \
-	(&(struct thermistor_info){                                 \
+	(&(const struct thermistor_info){                           \
 		.scaling_factor = DT_PROP(node_id, scaling_factor), \
 		.num_pairs = DT_PROP(node_id, num_pairs),           \
 		.data = DT_CAT(node_id, _thermistor_data),          \
 	})
 
-#define GET_ZEPHYR_TEMP_SENSOR_THERMISTOR(node_id)			      \
-	(&(struct zephyr_temp_sensor){					      \
-		.read = &thermistor_get_temp,				      \
-		.thermistor =                                                 \
-			GET_THERMISTOR_INFO(DT_PHANDLE(node_id, thermistor)), \
-		FILL_POWER_GOOD(node_id)				      \
-	})
-
-#define TEMP_THERMISTOR(node_id)                                              \
-	[ZSHIM_TEMP_SENSOR_ID(node_id)] = {                                   \
-		.name = DT_LABEL(node_id),                                    \
-		.idx = ZSHIM_ADC_ID(DT_PHANDLE(node_id, adc)),                \
-		.type = TEMP_SENSOR_TYPE_BOARD,                               \
-		.zephyr_info = GET_ZEPHYR_TEMP_SENSOR_THERMISTOR(node_id),    \
-	},
+#define GET_ZEPHYR_TEMP_SENSOR_THERMISTOR(named_id, sensor_id) \
+	(&(const struct zephyr_temp_sensor){                   \
+		.read = &thermistor_get_temp,                  \
+		.thermistor = GET_THERMISTOR_INFO(             \
+			DT_PHANDLE(sensor_id, thermistor)),    \
+		FILL_POWER_GOOD(named_id) })
+
+#define TEMP_THERMISTOR(named_id, sensor_id)                                 \
+	[TEMP_SENSOR_ID(named_id)] = {                                       \
+		.name = DT_NODE_FULL_NAME(sensor_id),                        \
+		.idx = ZSHIM_ADC_ID(DT_PHANDLE(sensor_id, adc)),             \
+		.type = TEMP_SENSOR_TYPE_BOARD,                              \
+		.zephyr_info = GET_ZEPHYR_TEMP_SENSOR_THERMISTOR(named_id,   \
+								 sensor_id), \
+	}
 
 DT_FOREACH_STATUS_OKAY(cros_ec_thermistor, DEFINE_THERMISTOR_DATA)
 
-#if DT_HAS_COMPAT_STATUS_OKAY(cros_ec_temp_sensor_pct2075)
-static int pct2075_get_temp(const struct temp_sensor_t *sensor, int *temp_ptr)
+#if DT_HAS_COMPAT_STATUS_OKAY(PCT2075_COMPAT)
+/* The function maybe unused because a temperature sensor can be added to dts
+ * without a reference in the cros_ec_temp_sensors node.
+ */
+__maybe_unused static int pct2075_get_temp(const struct temp_sensor_t *sensor,
+					   int *temp_ptr)
 {
 	return pct2075_get_val_k(sensor->idx, temp_ptr);
 }
-#endif /* cros_ec_temp_sensor_pct2075 */
+#endif /* PCT2075_COMPAT */
 
-#define DEFINE_PCT2075_DATA(node_id)                                        \
-	[ZSHIM_PCT2075_SENSOR_ID(node_id)] = {                              \
-		.i2c_port = I2C_PORT(DT_PHANDLE(node_id, port)),            \
-		.i2c_addr_flags = DT_STRING_TOKEN(node_id, i2c_addr_flags), \
+#define DEFINE_PCT2075_DATA(node_id)                                  \
+	[PCT2075_SENSOR_ID(node_id)] = {                              \
+		.i2c_port = I2C_PORT_BY_DEV(node_id),                 \
+		.i2c_addr_flags =                                     \
+			(DT_REG_ADDR(node_id) | I2C_FLAG_BIG_ENDIAN), \
 	},
 
-#define GET_ZEPHYR_TEMP_SENSOR_PCT2075(node_id)				      \
-	(&(struct zephyr_temp_sensor){					      \
-		.read = &pct2075_get_temp,				      \
-		.thermistor = NULL,                                           \
-		FILL_POWER_GOOD(node_id)				      \
-	})
-
-#define TEMP_PCT2075(node_id)						\
-	[ZSHIM_TEMP_SENSOR_ID(node_id)] = {				\
-		.name = DT_LABEL(node_id),				\
-		.idx = ZSHIM_PCT2075_SENSOR_ID(node_id),		\
-		.type = TEMP_SENSOR_TYPE_BOARD,				\
-		.zephyr_info = GET_ZEPHYR_TEMP_SENSOR_PCT2075(node_id),	\
-	},
+#define GET_ZEPHYR_TEMP_SENSOR_PCT2075(named_id)                        \
+	(&(const struct zephyr_temp_sensor){ .read = &pct2075_get_temp, \
+					     .thermistor = NULL,        \
+					     FILL_POWER_GOOD(named_id) })
+
+#define TEMP_PCT2075(named_id, sensor_id)                                \
+	[TEMP_SENSOR_ID(named_id)] = {                                   \
+		.name = DT_NODE_FULL_NAME(sensor_id),                    \
+		.idx = PCT2075_SENSOR_ID(sensor_id),                     \
+		.type = TEMP_SENSOR_TYPE_BOARD,                          \
+		.zephyr_info = GET_ZEPHYR_TEMP_SENSOR_PCT2075(named_id), \
+	}
 
 const struct pct2075_sensor_t pct2075_sensors[PCT2075_COUNT] = {
-	DT_FOREACH_STATUS_OKAY(cros_ec_temp_sensor_pct2075, DEFINE_PCT2075_DATA)
+	DT_FOREACH_STATUS_OKAY(PCT2075_COMPAT, DEFINE_PCT2075_DATA)
 };
 
-#if DT_HAS_COMPAT_STATUS_OKAY(cros_ec_temp_sensor_sb_tsi)
-static int sb_tsi_get_temp(const struct temp_sensor_t *sensor, int *temp_ptr)
+#if DT_HAS_COMPAT_STATUS_OKAY(SB_TSI_COMPAT)
+/* The function maybe unused because a temperature sensor can be added to dts
+ * without a reference in the cros_ec_temp_sensors node.
+ */
+__maybe_unused static int sb_tsi_get_temp(const struct temp_sensor_t *sensor,
+					  int *temp_ptr)
 {
 	return sb_tsi_get_val(sensor->idx, temp_ptr);
 }
 
 /* There can be only one SB TSI sensor with current driver */
-#if DT_NUM_INST_STATUS_OKAY(cros_ec_temp_sensor_sb_tsi) > 1
+#if DT_NUM_INST_STATUS_OKAY(SB_TSI_COMPAT) > 1
 #error "Unsupported number of SB TSI sensors"
 #endif
 
-#endif /* cros_ec_temp_sensor_sb_tsi */
+#endif /* SB_TSI_COMPAT */
 
-#define GET_ZEPHYR_TEMP_SENSOR_SB_TSI(node_id)				      \
-	(&(struct zephyr_temp_sensor){					      \
-		.read = &sb_tsi_get_temp,				      \
-		.thermistor = NULL,                                           \
-		FILL_POWER_GOOD(node_id)				      \
-	})
+#define GET_ZEPHYR_TEMP_SENSOR_SB_TSI(named_id)                        \
+	(&(const struct zephyr_temp_sensor){ .read = &sb_tsi_get_temp, \
+					     .thermistor = NULL,       \
+					     FILL_POWER_GOOD(named_id) })
 
-#define TEMP_SB_TSI(node_id)						\
-	[ZSHIM_TEMP_SENSOR_ID(node_id)] = {				\
-		.name = DT_LABEL(node_id),				\
-		.idx = 0,						\
-		.type = TEMP_SENSOR_TYPE_CPU,				\
-		.zephyr_info = GET_ZEPHYR_TEMP_SENSOR_SB_TSI(node_id),	\
-	},
+#define TEMP_SB_TSI(named_id, sensor_id)                                \
+	[TEMP_SENSOR_ID(named_id)] = {                                  \
+		.name = DT_NODE_FULL_NAME(sensor_id),                   \
+		.idx = 0,                                               \
+		.type = TEMP_SENSOR_TYPE_CPU,                           \
+		.zephyr_info = GET_ZEPHYR_TEMP_SENSOR_SB_TSI(named_id), \
+	}
 
-#if DT_HAS_COMPAT_STATUS_OKAY(cros_ec_temp_sensor_tmp112)
-static int tmp112_get_temp(const struct temp_sensor_t *sensor, int *temp_ptr)
+#if DT_HAS_COMPAT_STATUS_OKAY(TMP112_COMPAT)
+/* The function maybe unused because a temperature sensor can be added to dts
+ * without a reference in the cros_ec_temp_sensors node.
+ */
+__maybe_unused static int tmp112_get_temp(const struct temp_sensor_t *sensor,
+					  int *temp_ptr)
 {
 	return tmp112_get_val_k(sensor->idx, temp_ptr);
 }
-#endif /* cros_ec_temp_sensor_tmp112 */
+#endif /* TMP112_COMPAT */
 
-#define DEFINE_TMP112_DATA(node_id)                                         \
-	[ZSHIM_TMP112_SENSOR_ID(node_id)] = {                               \
-		.i2c_port = I2C_PORT(DT_PHANDLE(node_id, port)),            \
-		.i2c_addr_flags = DT_STRING_TOKEN(node_id, i2c_addr_flags), \
+#define DEFINE_TMP112_DATA(node_id)                     \
+	[TMP112_SENSOR_ID(node_id)] = {                 \
+		.i2c_port = I2C_PORT_BY_DEV(node_id),   \
+		.i2c_addr_flags = DT_REG_ADDR(node_id), \
 	},
 
-#define GET_ZEPHYR_TEMP_SENSOR_TMP112(node_id)				      \
-	(&(struct zephyr_temp_sensor){					      \
-		.read = &tmp112_get_temp,				      \
-		.thermistor = NULL,                                           \
-		FILL_POWER_GOOD(node_id)				      \
-	})
-
-#define TEMP_TMP112(node_id)						\
-	[ZSHIM_TEMP_SENSOR_ID(node_id)] = {				\
-		.name = DT_LABEL(node_id),				\
-		.idx = ZSHIM_TMP112_SENSOR_ID(node_id),			\
-		.type = TEMP_SENSOR_TYPE_BOARD,				\
-		.zephyr_info = GET_ZEPHYR_TEMP_SENSOR_TMP112(node_id),	\
-	},
+#define GET_ZEPHYR_TEMP_SENSOR_TMP112(named_id)                        \
+	(&(const struct zephyr_temp_sensor){ .read = &tmp112_get_temp, \
+					     .thermistor = NULL,       \
+					     FILL_POWER_GOOD(named_id) })
+
+#define TEMP_TMP112(named_id, sensor_id)                                \
+	[TEMP_SENSOR_ID(named_id)] = {                                  \
+		.name = DT_NODE_FULL_NAME(sensor_id),                   \
+		.idx = TMP112_SENSOR_ID(sensor_id),                     \
+		.type = TEMP_SENSOR_TYPE_BOARD,                         \
+		.zephyr_info = GET_ZEPHYR_TEMP_SENSOR_TMP112(named_id), \
+	}
 
 const struct tmp112_sensor_t tmp112_sensors[TMP112_COUNT] = {
-	DT_FOREACH_STATUS_OKAY(cros_ec_temp_sensor_tmp112, DEFINE_TMP112_DATA)
+	DT_FOREACH_STATUS_OKAY(TMP112_COMPAT, DEFINE_TMP112_DATA)
 };
 
-const struct temp_sensor_t temp_sensors[] = {
-	DT_FOREACH_STATUS_OKAY(cros_ec_temp_sensor_thermistor, TEMP_THERMISTOR)
-	DT_FOREACH_STATUS_OKAY(cros_ec_temp_sensor_pct2075, TEMP_PCT2075)
-	DT_FOREACH_STATUS_OKAY(cros_ec_temp_sensor_sb_tsi, TEMP_SB_TSI)
-	DT_FOREACH_STATUS_OKAY(cros_ec_temp_sensor_tmp112, TEMP_TMP112)
-};
+/* There can be only one thermistor on RT9490 with current driver */
+#define ADD_ONE(node_id) 1 +
+#if DT_FOREACH_STATUS_OKAY_VARGS(RT9490_CHG_COMPAT, TEMP_RT9490_FN, \
+				 ADD_ONE) 0 > 1
+#error "Unsupported number of thermistor on RT9490"
+#endif
+#undef ADD_ONE
+
+#define GET_ZEPHYR_TEMP_SENSOR_RT9490(named_id, sensor_id)  \
+	(&(const struct zephyr_temp_sensor){                \
+		.read = &rt9490_get_thermistor_val,         \
+		.thermistor = GET_THERMISTOR_INFO(          \
+			DT_PHANDLE(sensor_id, thermistor)), \
+		FILL_POWER_GOOD(named_id) })
+
+#define TEMP_RT9490(named_id, sensor_id) \
+	COND_CODE_1(DT_NODE_HAS_PROP(sensor_id, thermistor), (                 \
+		[TEMP_SENSOR_ID(named_id)] = {                                 \
+			.name = DT_NODE_FULL_NAME(sensor_id),                  \
+			.idx = 0,                                              \
+			.type = TEMP_SENSOR_TYPE_BOARD,                        \
+			.zephyr_info = GET_ZEPHYR_TEMP_SENSOR_RT9490(named_id, \
+				       sensor_id),                             \
+		} ), ())
+
+#define DT_DRV_COMPAT TEMP_SENSORS_COMPAT
+
+#define CHECK_COMPAT(compat, named_id, sensor_id, config_fn) \
+	COND_CODE_1(DT_NODE_HAS_COMPAT(sensor_id, compat),   \
+		    (config_fn(named_id, sensor_id)), ())
+
+#define TEMP_SENSOR_FIND(named_id, sensor_id)                                 \
+	CHECK_COMPAT(THERMISTOR_COMPAT, named_id, sensor_id, TEMP_THERMISTOR) \
+	CHECK_COMPAT(PCT2075_COMPAT, named_id, sensor_id, TEMP_PCT2075)       \
+	CHECK_COMPAT(SB_TSI_COMPAT, named_id, sensor_id, TEMP_SB_TSI)         \
+	CHECK_COMPAT(TMP112_COMPAT, named_id, sensor_id, TEMP_TMP112)         \
+	CHECK_COMPAT(RT9490_CHG_COMPAT, named_id, sensor_id, TEMP_RT9490)
+
+#define TEMP_SENSOR_ENTRY(named_id) \
+	TEMP_SENSOR_FIND(named_id, DT_PHANDLE(named_id, sensor))
+
+const struct temp_sensor_t temp_sensors[] = { DT_FOREACH_CHILD_SEP(
+	TEMP_SENSORS_NODEID, TEMP_SENSOR_ENTRY, (, )) };
 
 int temp_sensor_read(enum temp_sensor_id id, int *temp_ptr)
 {
@@ -194,4 +254,4 @@ int temp_sensor_read(enum temp_sensor_id id, int *temp_ptr)
 	return sensor->zephyr_info->read(sensor, temp_ptr);
 }
 
-#endif /* named_temp_sensors */
+#endif /* DT_HAS_COMPAT_STATUS_OKAY(TEMP_SENSORS_COMPAT) */
diff --git a/zephyr/shim/src/test_util.c b/zephyr/shim/src/test_util.c
index 28be596043..e999772fc6 100644
--- a/zephyr/shim/src/test_util.c
+++ b/zephyr/shim/src/test_util.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
diff --git a/zephyr/shim/src/thermal.c b/zephyr/shim/src/thermal.c
index c31e2bfcc6..abe6b7da9e 100644
--- a/zephyr/shim/src/thermal.c
+++ b/zephyr/shim/src/thermal.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,8 +7,8 @@
 #include "temp_sensor/temp_sensor.h"
 #include "ec_commands.h"
 
-#define THERMAL_CONFIG(node_id)					\
-	[ZSHIM_TEMP_SENSOR_ID(node_id)] = {				\
+#define THERMAL_CONFIG(node_id) \
+	[TEMP_SENSOR_ID(node_id)] = {				\
 		.temp_host = {						\
 			[EC_TEMP_THRESH_WARN] =			\
 			C_TO_K(DT_PROP_OR(node_id,			\
@@ -43,10 +43,10 @@
 		.temp_fan_max = C_TO_K(DT_PROP_OR(node_id,		\
 						  temp_fan_max,	\
 						  -273)),		\
-	},
+	}
 
 struct ec_thermal_config thermal_params[] = {
-#if DT_NODE_EXISTS(DT_PATH(named_temp_sensors))
-	DT_FOREACH_CHILD(DT_PATH(named_temp_sensors), THERMAL_CONFIG)
-#endif /* named_temp_sensors */
+#if DT_HAS_COMPAT_STATUS_OKAY(TEMP_SENSORS_COMPAT)
+	DT_FOREACH_CHILD_SEP(TEMP_SENSORS_NODEID, THERMAL_CONFIG, (, ))
+#endif /* DT_HAS_COMPAT_STATUS_OKAY(TEMP_SENSORS_COMPAT) */
 };
diff --git a/zephyr/shim/src/usb_muxes.c b/zephyr/shim/src/usb_muxes.c
index f96146258a..3f81e97787 100644
--- a/zephyr/shim/src/usb_muxes.c
+++ b/zephyr/shim/src/usb_muxes.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,45 +9,83 @@
 #include "usbc/usb_muxes.h"
 
 /**
- * @brief Macro that can be used in USB_MUX_FOREACH_USBC_PORT as filter
- *        argument. It allows to evaluate to "1 ||" for each named USBC port
- *        that has usb-muxes property.
+ * This prevents creating struct usb_mux usb_muxes[] for platforms that didn't
+ * migrate USB mux configuration to DTS yet.
  */
-#define USB_MUX_PORT_HAS_MUX(unused1, unused2)		1 ||
+#if DT_HAS_COMPAT_STATUS_OKAY(cros_ec_usb_mux_chain)
 
 /**
- * Check if there is any named USBC port with usb-muxes property. It evaluates
- * to "1 || 1 || ... 1 || 0" when there are multiple named USBC ports with
- * usb-muxes property and to "0" when any named USBC port has usb-muxes
- * property.
+ * @brief Check if @p mux_id is not part of @p chain_id or if @p chain_id USBC
+ *        port is the same as @p mux_port. Result ends with && to construct
+ *        logical expression using FOREACH macro.
  *
- * This prevents creating struct usb_mux usb_muxes[] for platforms that didn't
- * migrate USB mux configuration to DTS yet.
+ * @param chain_id Chain DTS node ID
+ * @param mux_id USB mux node ID
+ * @param mux_port Port which should be associated with @p mux_id
  */
-#if USB_MUX_FOREACH_USBC_PORT(USB_MUX_PORT_HAS_MUX, _) 0
+#define USB_MUX_NOT_IN_CHAIN_OR_PORT_EQ(chain_id, mux_id, mux_port) \
+	((USB_MUX_FIND_PORT(chain_id, mux_id)(-1)) == -1 ||         \
+	 USBC_PORT(chain_id) == mux_port) &&
+
+/**
+ * @brief Check if all chains that contains @p mux_id have the same USB-C port
+ *
+ * @param mux_id USB mux node ID
+ * @param unused_conf Unused argument required by USB_MUX_FOREACH_MUX()
+ */
+#define USB_MUX_CHECK_ALL_PORTS_ARE_SAME(mux_id, unused_conf)                \
+	BUILD_ASSERT(                                                        \
+		USB_MUX_FOREACH_CHAIN_VARGS(USB_MUX_NOT_IN_CHAIN_OR_PORT_EQ, \
+					    mux_id, USB_MUX_PORT(mux_id)) 1, \
+		"USB mux  " #mux_id " is in chains for different ports");
+
+/** Check if for every mux, chains where mux is present have the same port */
+USB_MUX_FOREACH_MUX(USB_MUX_CHECK_ALL_PORTS_ARE_SAME)
+
+/**
+ * Declare all usb_mux_chain structures e.g.
+ * MAYBE_CONST struct usb_mux_chain
+ * USB_MUX_chain_port_<port_id>_mux_<position_id>;
+ */
+USB_MUX_FOREACH_CHAIN_VARGS(USB_MUX_FOREACH_NO_ROOT_MUX,
+			    USB_MUX_CHAIN_STRUCT_DECLARE_OP)
+
+/**
+ * Define usb_mux_chain structures for main chain e.g.
+ *
+ * MAYBE_CONST struct usb_mux_chain
+ * USB_MUX_chain_port_<port_id>_mux_<position_id> = {
+ *         .mux = &USB_MUX_NODE_DT_N_S_usbc_S_port0_0_S_virtual_mux_0,
+ *         .next = &USB_MUX_chain_port_0_mux_1,
+ * }
+ */
+USB_MUX_FOREACH_CHAIN_VARGS(USB_MUX_FOR_MAIN_CHAIN, USB_MUX_FOREACH_NO_ROOT_MUX,
+			    USB_MUX_CHAIN_STRUCT_DEFINE_OP)
+
+/**
+ * Forward declarations for board_init and board_set callbacks. e.g.
+ * int c0_mux0_board_init(const struct usb_mux *);
+ * int c1_mux0_board_set(const struct usb_mux *, mux_state_t);
+ */
+USB_MUX_FOREACH_MUX(USB_MUX_CB_BOARD_INIT_DECLARE_IF_EXISTS)
+USB_MUX_FOREACH_MUX(USB_MUX_CB_BOARD_SET_DECLARE_IF_EXISTS)
 
 /**
  * Define root of each USB muxes chain e.g.
  * [0] = {
- *         .usb_port = 0,
- *         .next_mux = &USB_MUX_NODE_DT_N_S_usbc_S_port0_0_S_it5205_mux_0,
- *         .board_init = &board_init,
- *         .board_set = NULL,
- *         .flags = 0,
- *         .driver = &virtual_usb_mux_driver,
- *         .hpd_update = &virtual_hpd_update,
+ *         .mux = &USB_MUX_NODE_DT_N_S_usbc_S_port0_0_S_virtual_mux_0,
+ *         .next = &USB_MUX_chain_port_0_mux_1,
  * },
  * [1] = { ... },
  */
-MAYBE_CONST struct usb_mux usb_muxes[] = {
-	USB_MUX_FOREACH_USBC_PORT(USB_MUX_FIRST, USB_MUX_ARRAY)
-};
+MAYBE_CONST struct usb_mux_chain usb_muxes[] = { USB_MUX_FOREACH_CHAIN_VARGS(
+	USB_MUX_FOR_MAIN_CHAIN, USB_MUX_DEFINE_ROOT_MUX) };
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == CONFIG_USB_PD_PORT_MAX_COUNT);
 
 /**
- * Define all USB muxes except roots e.g.
+ * Define all USB muxes e.g.
  * MAYBE_CONST struct usb_mux USB_MUX_NODE_DT_N_S_usbc_S_port0_0_S_mux_0 = {
  *         .usb_port = 0,
- *         .next_mux = NULL,
  *         .board_init = NULL,
  *         .board_set = NULL,
  *         .flags = 0,
@@ -56,30 +94,6 @@ MAYBE_CONST struct usb_mux usb_muxes[] = {
  * };
  * MAYBE_CONST struct usb_mux USB_MUX_NODE_<node_id> = { ... };
  */
-USB_MUX_FOREACH_USBC_PORT(USB_MUX_NO_FIRST, USB_MUX_DEFINE)
-
-/* Create bb_controls only if BB retimer driver is enabled */
-#ifdef CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_BB
-/**
- * @brief bb_controls array should be constant only if configuration cannot
- *        change in runtime
- */
-#define BB_CONTROLS_CONST						\
-	COND_CODE_1(							\
-		CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_BB_RUNTIME_CONFIG,\
-		(), (const))
-
-/**
- * Define bb_controls for BB retimers in USB muxes chain e.g.
- * [0] = {
- *         .retimer_rst_gpio = IOEX_USB_C0_BB_RETIMER_RST,
- *         .usb_ls_en_gpio = IOEX_USB_C0_BB_RETIMER_LS_EN,
- * },
- * [1] = { ... },
- */
-BB_CONTROLS_CONST struct bb_usb_control bb_controls[] = {
-	USB_MUX_FOREACH_USBC_PORT(USB_MUX_BB_RETIMERS, USB_MUX_ARRAY)
-};
-#endif /* CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_BB */
+USB_MUX_FOREACH_MUX(USB_MUX_DEFINE)
 
-#endif /* #if USB_MUX_FOREACH_USBC_PORT(USB_MUX_PORT_HAS_MUX, _) */
+#endif /* #if DT_HAS_COMPAT_STATUS_OKAY(cros_ec_usb_mux_chain) */
diff --git a/zephyr/shim/src/usba.c b/zephyr/shim/src/usba.c
index e8e1ca373a..4db8c31e6a 100644
--- a/zephyr/shim/src/usba.c
+++ b/zephyr/shim/src/usba.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,18 +10,18 @@
 
 #if DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT)
 
-#define PIN(node_id, prop, idx) GPIO_SIGNAL(DT_PHANDLE_BY_IDX(node_id, prop, idx)),
+#define PIN(node_id, prop, idx) \
+	GPIO_SIGNAL(DT_PHANDLE_BY_IDX(node_id, prop, idx)),
 
 BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 0,
-		"No compatible USBA Port Enable instance found");
+	     "No compatible USBA Port Enable instance found");
 
 #define USBA_ENABLE_PINS(inst) DT_INST_FOREACH_PROP_ELEM(inst, enable_pins, PIN)
 
 #if !IS_ENABLED(CONFIG_PLATFORM_EC_USB_PORT_ENABLE_DYNAMIC)
 const
 #endif
-int usb_port_enable[] = {
-	DT_INST_FOREACH_STATUS_OKAY(USBA_ENABLE_PINS)
-};
+	int usb_port_enable[] = { DT_INST_FOREACH_STATUS_OKAY(
+		USBA_ENABLE_PINS) };
 
 #endif /* DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT) */
diff --git a/zephyr/shim/src/watchdog.c b/zephyr/shim/src/watchdog.c
index 00cd5c4c30..eb82f228d5 100644
--- a/zephyr/shim/src/watchdog.c
+++ b/zephyr/shim/src/watchdog.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,7 @@
 #include <zephyr/device.h>
 #include <zephyr/drivers/watchdog.h>
 #include <zephyr/logging/log.h>
-#include <zephyr/zephyr.h>
+#include <zephyr/kernel.h>
 
 #include "config.h"
 #include "hooks.h"
@@ -24,12 +24,12 @@ static void wdt_warning_handler(const struct device *wdt_dev, int channel_id)
 {
 	/* TODO(b/176523207): watchdog warning message */
 	printk("Watchdog deadline is close!\n");
-	#ifdef TEST_BUILD
+#ifdef TEST_BUILD
 	wdt_warning_triggered = true;
-	#endif
+#endif
 #ifdef CONFIG_SOC_SERIES_MEC172X
 	extern void cros_chip_wdt_handler(const struct device *wdt_dev,
-				int channel_id);
+					  int channel_id);
 	cros_chip_wdt_handler(wdt_dev, channel_id);
 #endif
 }
diff --git a/zephyr/shim/src/ztest_system.c b/zephyr/shim/src/ztest_system.c
index 18b172a341..5933f18f05 100644
--- a/zephyr/shim/src/ztest_system.c
+++ b/zephyr/shim/src/ztest_system.c
@@ -1,23 +1,24 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include "system.h"
-#include "cros_version.h"
 #include "battery.h"
 #include "charge_manager.h"
+#include "common.h"
+#include "cros_version.h"
 #include "sysjump.h"
+#include "system.h"
 
 #define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
 
-struct jump_data mock_jump_data = {};
+char mock_jump_data[sizeof(struct jump_data) + 256];
 
 /* When CONFIG_RAM_SIZE is defined, this is provided by common/system.c */
 #ifndef CONFIG_RAM_SIZE
 struct jump_data *get_jump_data(void)
 {
-	return &mock_jump_data;
+	return (struct jump_data *)&mock_jump_data;
 }
 #endif
 
@@ -26,6 +27,11 @@ __attribute__((weak)) void system_reset(int flags)
 	__builtin_unreachable();
 }
 
+__attribute__((weak)) void software_panic(uint32_t reason, uint32_t info)
+{
+	__builtin_unreachable();
+}
+
 static uint8_t bbram[SYSTEM_BBRAM_IDX_TRY_SLOT + 1];
 
 test_mockable int system_get_bbram(enum system_bbram_idx idx, uint8_t *value)
@@ -86,7 +92,7 @@ test_mockable const char *system_get_chip_revision(void)
 	return "";
 }
 
-void board_reset_pd_mcu(void)
+test_mockable void board_reset_pd_mcu(void)
 {
 }
 
diff --git a/zephyr/subsys/Kconfig b/zephyr/subsys/Kconfig
index f35a942afc..48011312d5 100644
--- a/zephyr/subsys/Kconfig
+++ b/zephyr/subsys/Kconfig
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/subsys/ap_pwrseq/CMakeLists.txt b/zephyr/subsys/ap_pwrseq/CMakeLists.txt
index 30edfae4dd..0a77bc821d 100644
--- a/zephyr/subsys/ap_pwrseq/CMakeLists.txt
+++ b/zephyr/subsys/ap_pwrseq/CMakeLists.txt
@@ -13,9 +13,10 @@ zephyr_library_sources_ifdef(CONFIG_AP_PWRSEQ
 	signal_adc.c
 	)
 zephyr_library_sources_ifdef(CONFIG_X86_NON_DSX_PWRSEQ
-	x86_non_dsx_common_pwrseq_sm_handler.c)
-zephyr_library_sources_ifdef(CONFIG_X86_NON_DSX_PWRSEQ
+	x86_non_dsx_common_pwrseq_sm_handler.c
 	x86_non_dsx_chipset_power_state.c)
+zephyr_library_sources_ifdef(CONFIG_AP_PWRSEQ_S0IX_ERROR_RECOVERY
+	x86_non_dsx_common_pwrseq_host_sleep.c)
 zephyr_library_sources_ifdef(CONFIG_X86_NON_DSX_PWRSEQ_CONSOLE
 	x86_non_dsx_common_pwrseq_console.c)
 zephyr_library_sources_ifdef(CONFIG_X86_NON_DSX_PWRSEQ_HOST_CMD
diff --git a/zephyr/subsys/ap_pwrseq/Kconfig b/zephyr/subsys/ap_pwrseq/Kconfig
index 6f39906bf2..677bca7c6d 100644
--- a/zephyr/subsys/ap_pwrseq/Kconfig
+++ b/zephyr/subsys/ap_pwrseq/Kconfig
@@ -1,16 +1,19 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 menuconfig AP_PWRSEQ
 	bool "AP Power sequencing support"
 	select HAS_TASK_POWERBTN
+	select GPIO_GET_CONFIG
 	help
 	  Enables AP power sequencing support with
 	  embedded controller. This includes normal shutdown, critical
 	  shutdown and reset handling.
 	  Enabling this automatically enables HAS_TASK_POWERBTN since this task
 	  is required to handle power button pressed/released by user.
+	  Enabling this also enables retrieving the GPIO config feature
+	  so that the value of output GPIOs can be determined.
 
 if AP_PWRSEQ
 
@@ -104,4 +107,14 @@ config AP_PWRSEQ_S0IX
 	  required, AP_PWRSEQ_HOST_SLEEP for host sleep event handling is
 	  enabled.
 
+config AP_PWRSEQ_S0IX_ERROR_RECOVERY
+	bool "Detect failure to enter or exit Sleep state"
+	depends on AP_PWRSEQ_HOST_SLEEP
+	help
+	  Enables detection of the AP failing to go to sleep, perhaps due to a
+	  bug in the internal SoC periodic housekeeping code.
+
+	  Failure information is reported via the EC_CMD_HOST_SLEEP_EVENT host
+	  command.
+
 endif
diff --git a/zephyr/subsys/ap_pwrseq/ap_events.c b/zephyr/subsys/ap_pwrseq/ap_events.c
index d5b78c2c33..0d99c0fe36 100644
--- a/zephyr/subsys/ap_pwrseq/ap_events.c
+++ b/zephyr/subsys/ap_pwrseq/ap_events.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -71,7 +71,8 @@ void ap_power_ev_send_callbacks(enum ap_power_events event)
 		return;
 	}
 	data.event = event;
-	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&callbacks, cb, tmp, node) {
+	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&callbacks, cb, tmp, node)
+	{
 		if (cb->events & event) {
 			cb->handler(cb, data);
 		}
diff --git a/zephyr/subsys/ap_pwrseq/ap_power_interface.c b/zephyr/subsys/ap_pwrseq/ap_power_interface.c
index d6dc352033..1461ed139b 100644
--- a/zephyr/subsys/ap_pwrseq/ap_power_interface.c
+++ b/zephyr/subsys/ap_pwrseq/ap_power_interface.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,12 +6,17 @@
 #include <ap_power/ap_power_interface.h>
 #include <x86_non_dsx_common_pwrseq_sm_handler.h>
 
-bool ap_power_in_state(
-		enum ap_power_state_mask state_mask)
+LOG_MODULE_DECLARE(ap_pwrseq, CONFIG_AP_PWRSEQ_LOG_LEVEL);
+
+bool ap_power_in_state(enum ap_power_state_mask state_mask)
 {
 	int need_mask = 0;
 
 	switch (pwr_sm_get_state()) {
+	case SYS_POWER_STATE_UNINIT:
+		LOG_WRN("%s: init not yet complete; AP state is unknown",
+			__func__);
+		return false;
 	case SYS_POWER_STATE_G3:
 		need_mask = AP_POWER_STATE_HARD_OFF;
 		break;
@@ -21,16 +26,14 @@ bool ap_power_in_state(
 		 * In between hard and soft off states.  Match only if caller
 		 * will accept both.
 		 */
-		need_mask = AP_POWER_STATE_HARD_OFF |
-			AP_POWER_STATE_SOFT_OFF;
+		need_mask = AP_POWER_STATE_HARD_OFF | AP_POWER_STATE_SOFT_OFF;
 		break;
 	case SYS_POWER_STATE_S5:
 		need_mask = AP_POWER_STATE_SOFT_OFF;
 		break;
 	case SYS_POWER_STATE_S5S4:
 	case SYS_POWER_STATE_S4S5:
-		need_mask = AP_POWER_STATE_SOFT_OFF |
-			AP_POWER_STATE_SUSPEND;
+		need_mask = AP_POWER_STATE_SOFT_OFF | AP_POWER_STATE_SUSPEND;
 		break;
 	case SYS_POWER_STATE_S4:
 	case SYS_POWER_STATE_S4S3:
@@ -40,8 +43,7 @@ bool ap_power_in_state(
 		break;
 	case SYS_POWER_STATE_S3S0:
 	case SYS_POWER_STATE_S0S3:
-		need_mask = AP_POWER_STATE_SUSPEND |
-			AP_POWER_STATE_ON;
+		need_mask = AP_POWER_STATE_SUSPEND | AP_POWER_STATE_ON;
 		break;
 	case SYS_POWER_STATE_S0:
 		need_mask = AP_POWER_STATE_ON;
@@ -60,10 +62,13 @@ bool ap_power_in_state(
 	return (state_mask & need_mask) == need_mask;
 }
 
-bool ap_power_in_or_transitioning_to_state(
-		enum ap_power_state_mask state_mask)
+bool ap_power_in_or_transitioning_to_state(enum ap_power_state_mask state_mask)
 {
 	switch (pwr_sm_get_state()) {
+	case SYS_POWER_STATE_UNINIT:
+		LOG_WRN("%s: init not yet complete; AP state is unknown",
+			__func__);
+		return 0;
 	case SYS_POWER_STATE_G3:
 	case SYS_POWER_STATE_S5G3:
 		return state_mask & AP_POWER_STATE_HARD_OFF;
@@ -107,7 +112,7 @@ void ap_power_exit_hardoff(void)
 	    power_state != SYS_POWER_STATE_S5G3 &&
 	    power_state != SYS_POWER_STATE_S5)
 		return;
-	request_exit_hardoff(true);
+	request_start_from_g3();
 }
 
 void ap_power_init_reset_log(void)
diff --git a/zephyr/subsys/ap_pwrseq/include/ap_power_host_sleep.h b/zephyr/subsys/ap_pwrseq/include/ap_power_host_sleep.h
index 9bee8af826..7251f96b76 100644
--- a/zephyr/subsys/ap_pwrseq/include/ap_power_host_sleep.h
+++ b/zephyr/subsys/ap_pwrseq/include/ap_power_host_sleep.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -22,8 +22,8 @@ void ap_power_set_active_wake_mask(void);
  *
  * @return 0 for success; -EINVAL if power state is not S3/S5/S0ix
  */
-int ap_power_get_lazy_wake_mask(
-	enum power_states_ndsx state, host_event_t *mask);
+int ap_power_get_lazy_wake_mask(enum power_states_ndsx state,
+				host_event_t *mask);
 
 #if CONFIG_AP_PWRSEQ_S0IX
 /* For S0ix path, flag to notify sleep change */
@@ -56,4 +56,17 @@ enum ap_power_sleep_type ap_power_sleep_get_notify(void);
 void ap_power_sleep_notify_transition(enum ap_power_sleep_type check_state);
 #endif /* CONFIG_AP_PWRSEQ_S0IX */
 
+/*
+ * Get sleep timeout from host command context
+ */
+uint16_t host_get_sleep_timeout(void);
+
+/*
+ * Set sleep transitions for host command response
+ *
+ * @param val sleep transitions
+ *
+ */
+void host_set_sleep_transitions(uint32_t val);
+
 #endif /* __AP_PWRSEQ_HOST_SLEEP_H */
diff --git a/zephyr/subsys/ap_pwrseq/include/ap_power_override_functions.h b/zephyr/subsys/ap_pwrseq/include/ap_power_override_functions.h
index 229bfb7e60..0d9195e5f2 100644
--- a/zephyr/subsys/ap_pwrseq/include/ap_power_override_functions.h
+++ b/zephyr/subsys/ap_pwrseq/include/ap_power_override_functions.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -75,7 +75,7 @@ bool board_ap_power_check_power_rails_enabled(void);
 /**
  * @brief macro to access configuration properties from DTS
  */
-#define AP_PWRSEQ_DT_VALUE(p)					\
-	DT_PROP(DT_COMPAT_GET_ANY_STATUS_OKAY(intel_ap_pwrseq), p)	\
+#define AP_PWRSEQ_DT_VALUE(p) \
+	DT_PROP(DT_COMPAT_GET_ANY_STATUS_OKAY(intel_ap_pwrseq), p)
 
 #endif /* __AP_PWRSEQ_AP_POWER_BOARD_FUNCTIONS_H__ */
diff --git a/zephyr/subsys/ap_pwrseq/include/power_signals.h b/zephyr/subsys/ap_pwrseq/include/power_signals.h
index 8755f1005a..5d3e97a52e 100644
--- a/zephyr/subsys/ap_pwrseq/include/power_signals.h
+++ b/zephyr/subsys/ap_pwrseq/include/power_signals.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -48,10 +48,10 @@
  * included if that signal source is configured in the
  * devicetree.
  */
-#define	HAS_GPIO_SIGNALS  DT_HAS_COMPAT_STATUS_OKAY(intel_ap_pwrseq_gpio)
-#define	HAS_VW_SIGNALS	  DT_HAS_COMPAT_STATUS_OKAY(intel_ap_pwrseq_vw)
-#define	HAS_EXT_SIGNALS   DT_HAS_COMPAT_STATUS_OKAY(intel_ap_pwrseq_external)
-#define	HAS_ADC_SIGNALS   DT_HAS_COMPAT_STATUS_OKAY(intel_ap_pwrseq_adc)
+#define HAS_GPIO_SIGNALS DT_HAS_COMPAT_STATUS_OKAY(intel_ap_pwrseq_gpio)
+#define HAS_VW_SIGNALS DT_HAS_COMPAT_STATUS_OKAY(intel_ap_pwrseq_vw)
+#define HAS_EXT_SIGNALS DT_HAS_COMPAT_STATUS_OKAY(intel_ap_pwrseq_external)
+#define HAS_ADC_SIGNALS DT_HAS_COMPAT_STATUS_OKAY(intel_ap_pwrseq_adc)
 
 /**
  * @brief Definitions for AP power sequence signals.
@@ -62,11 +62,9 @@
 /**
  * @brief Generate the enum for this power signal.
  */
-#define PWR_SIGNAL_ENUM(id) \
-	 DT_STRING_UPPER_TOKEN(id, enum_name)
+#define PWR_SIGNAL_ENUM(id) DT_STRING_UPPER_TOKEN(id, enum_name)
 
-#define PWR_SIGNAL_ENUM_COMMA(id) \
-	 PWR_SIGNAL_ENUM(id),
+#define PWR_SIGNAL_ENUM_COMMA(id) PWR_SIGNAL_ENUM(id),
 /**
  * @brief Enum of all power signals.
  *
@@ -78,11 +76,14 @@
  * must be the same as in power_signals.c
  */
 enum power_signal {
-DT_FOREACH_STATUS_OKAY(intel_ap_pwrseq_gpio, PWR_SIGNAL_ENUM_COMMA)
-DT_FOREACH_STATUS_OKAY(intel_ap_pwrseq_vw, PWR_SIGNAL_ENUM_COMMA)
-DT_FOREACH_STATUS_OKAY(intel_ap_pwrseq_external, PWR_SIGNAL_ENUM_COMMA)
-DT_FOREACH_STATUS_OKAY(intel_ap_pwrseq_adc, PWR_SIGNAL_ENUM_COMMA)
-	POWER_SIGNAL_COUNT,
+	DT_FOREACH_STATUS_OKAY(intel_ap_pwrseq_gpio, PWR_SIGNAL_ENUM_COMMA)
+		DT_FOREACH_STATUS_OKAY(intel_ap_pwrseq_vw,
+				       PWR_SIGNAL_ENUM_COMMA)
+			DT_FOREACH_STATUS_OKAY(intel_ap_pwrseq_external,
+					       PWR_SIGNAL_ENUM_COMMA)
+				DT_FOREACH_STATUS_OKAY(intel_ap_pwrseq_adc,
+						       PWR_SIGNAL_ENUM_COMMA)
+					POWER_SIGNAL_COUNT,
 };
 
 #undef PWR_SIGNAL_ENUM_COMMA
@@ -301,8 +302,7 @@ static inline bool power_signals_off(power_signal_mask_t want)
  * @return negative If the signals did not match before the timeout.
  */
 int power_wait_mask_signals_timeout(power_signal_mask_t want,
-				    power_signal_mask_t mask,
-				    int timeout);
+				    power_signal_mask_t mask, int timeout);
 
 /**
  * @brief Wait until the selected power signals match, with timeout
diff --git a/zephyr/subsys/ap_pwrseq/include/signal_adc.h b/zephyr/subsys/ap_pwrseq/include/signal_adc.h
index e43e73e1a7..81c6a1edd4 100644
--- a/zephyr/subsys/ap_pwrseq/include/signal_adc.h
+++ b/zephyr/subsys/ap_pwrseq/include/signal_adc.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,7 @@
 #ifndef __AP_PWRSEQ_SIGNAL_ADC_H__
 #define __AP_PWRSEQ_SIGNAL_ADC_H__
 
-#define PWR_SIG_TAG_ADC	PWR_ADC_
+#define PWR_SIG_TAG_ADC PWR_ADC_
 
 /*
  * Generate enums for the analogue converters.
@@ -21,13 +21,13 @@
 
 enum pwr_sig_adc {
 #if HAS_ADC_SIGNALS
-DT_FOREACH_STATUS_OKAY(intel_ap_pwrseq_adc, PWR_ADC_ENUM)
+	DT_FOREACH_STATUS_OKAY(intel_ap_pwrseq_adc, PWR_ADC_ENUM)
 #endif
-	PWR_SIG_ADC_COUNT
+		PWR_SIG_ADC_COUNT
 };
 
-#undef	PWR_ADC_ENUM
-#undef	TAG_ADC
+#undef PWR_ADC_ENUM
+#undef TAG_ADC
 
 /**
  * @brief Get the value of the ADC power signal.
diff --git a/zephyr/subsys/ap_pwrseq/include/signal_gpio.h b/zephyr/subsys/ap_pwrseq/include/signal_gpio.h
index e797f0c21f..7cdd4ec316 100644
--- a/zephyr/subsys/ap_pwrseq/include/signal_gpio.h
+++ b/zephyr/subsys/ap_pwrseq/include/signal_gpio.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,7 @@
 #ifndef __AP_PWRSEQ_SIGNAL_GPIO_H__
 #define __AP_PWRSEQ_SIGNAL_GPIO_H__
 
-#define PWR_SIG_TAG_GPIO	PWR_GPIO_
+#define PWR_SIG_TAG_GPIO PWR_GPIO_
 
 /*
  * Generate enums for the GPIOs.
@@ -21,13 +21,13 @@
 
 enum pwr_sig_gpio {
 #if HAS_GPIO_SIGNALS
-DT_FOREACH_STATUS_OKAY(intel_ap_pwrseq_gpio, PWR_GPIO_ENUM)
+	DT_FOREACH_STATUS_OKAY(intel_ap_pwrseq_gpio, PWR_GPIO_ENUM)
 #endif
-	PWR_SIG_GPIO_COUNT
+		PWR_SIG_GPIO_COUNT
 };
 
-#undef	PWR_GPIO_ENUM
-#undef	TAG_GPIO
+#undef PWR_GPIO_ENUM
+#undef TAG_GPIO
 
 /**
  * @brief Get the value of the GPIO power signal.
diff --git a/zephyr/subsys/ap_pwrseq/include/signal_vw.h b/zephyr/subsys/ap_pwrseq/include/signal_vw.h
index d005daaa40..55ecc73e99 100644
--- a/zephyr/subsys/ap_pwrseq/include/signal_vw.h
+++ b/zephyr/subsys/ap_pwrseq/include/signal_vw.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,7 @@
 #ifndef __AP_PWRSEQ_SIGNAL_VW_H__
 #define __AP_PWRSEQ_SIGNAL_VW_H__
 
-#define PWR_SIG_TAG_VW	PWR_VW_
+#define PWR_SIG_TAG_VW PWR_VW_
 
 /*
  * Generate enums for the virtual wire signals.
@@ -21,13 +21,13 @@
 
 enum pwr_sig_vw {
 #if HAS_VW_SIGNALS
-DT_FOREACH_STATUS_OKAY(intel_ap_pwrseq_vw, PWR_VW_ENUM)
+	DT_FOREACH_STATUS_OKAY(intel_ap_pwrseq_vw, PWR_VW_ENUM)
 #endif
-	PWR_SIG_VW_COUNT
+		PWR_SIG_VW_COUNT
 };
 
-#undef	PWR_VW_ENUM
-#undef	TAG_VW
+#undef PWR_VW_ENUM
+#undef TAG_VW
 
 /**
  * @brief Get the value of the virtual wire signal.
diff --git a/zephyr/subsys/ap_pwrseq/include/x86_common_pwrseq.h b/zephyr/subsys/ap_pwrseq/include/x86_common_pwrseq.h
index 526b0b6ca6..dcb2b3b968 100644
--- a/zephyr/subsys/ap_pwrseq/include/x86_common_pwrseq.h
+++ b/zephyr/subsys/ap_pwrseq/include/x86_common_pwrseq.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,11 +16,6 @@
 struct pwrseq_context {
 	/* On power-on start boot up sequence */
 	enum power_states_ndsx power_state;
-	/* Indicate should exit G3 power state or not */
-	bool want_g3_exit;
-	/* Indicate to exit G3 state or not with delay in ms*/
-	uint32_t reboot_ap_at_g3_delay_ms;
-
 };
 
 #endif /* __X86_COMMON_PWRSEQ_H__ */
diff --git a/zephyr/subsys/ap_pwrseq/include/x86_non_dsx_common_pwrseq_sm_handler.h b/zephyr/subsys/ap_pwrseq/include/x86_non_dsx_common_pwrseq_sm_handler.h
index f874879f04..2320e61965 100644
--- a/zephyr/subsys/ap_pwrseq/include/x86_non_dsx_common_pwrseq_sm_handler.h
+++ b/zephyr/subsys/ap_pwrseq/include/x86_non_dsx_common_pwrseq_sm_handler.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -15,7 +15,7 @@
 #include <ap_power_host_sleep.h>
 #include <x86_common_pwrseq.h>
 
-#define DT_DRV_COMPAT	intel_ap_pwrseq
+#define DT_DRV_COMPAT intel_ap_pwrseq
 
 /* The wait time is ~150 msec, allow for safety margin. */
 #define IN_PCH_SLP_SUS_WAIT_TIME_MS 250
@@ -23,11 +23,11 @@
 enum power_states_ndsx chipset_pwr_sm_run(enum power_states_ndsx curr_state);
 void init_chipset_pwr_seq_state(void);
 enum power_states_ndsx chipset_pwr_seq_get_state(void);
-void request_exit_hardoff(bool should_exit);
+void request_start_from_g3(void);
 enum power_states_ndsx pwr_sm_get_state(void);
-const char * const pwr_sm_get_state_name(enum power_states_ndsx state);
+const char *const pwr_sm_get_state_name(enum power_states_ndsx state);
 void apshutdown(void);
 void ap_pwrseq_handle_chipset_reset(void);
-void set_reboot_ap_at_g3_delay_seconds(uint32_t d_time);
+void set_start_from_g3_delay_seconds(uint32_t d_time);
 
 #endif /* __X86_NON_DSX_COMMON_PWRSEQ_SM_HANDLER_H__ */
diff --git a/zephyr/subsys/ap_pwrseq/include/x86_power_signals.h b/zephyr/subsys/ap_pwrseq/include/x86_power_signals.h
index 4e1277dce7..7c7e25d951 100644
--- a/zephyr/subsys/ap_pwrseq/include/x86_power_signals.h
+++ b/zephyr/subsys/ap_pwrseq/include/x86_power_signals.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,11 +8,15 @@
 #ifndef __X86_POWER_SIGNALS_H__
 #define __X86_POWER_SIGNALS_H__
 
-#define IN_PCH_SLP_S0  POWER_SIGNAL_MASK(PWR_SLP_S0)
-#define IN_PCH_SLP_S3  POWER_SIGNAL_MASK(PWR_SLP_S3)
-#define IN_PCH_SLP_S4  POWER_SIGNAL_MASK(PWR_SLP_S4)
-#define IN_PCH_SLP_S5  POWER_SIGNAL_MASK(PWR_SLP_S5)
+#define IN_PCH_SLP_S0 POWER_SIGNAL_MASK(PWR_SLP_S0)
+#define IN_PCH_SLP_S3 POWER_SIGNAL_MASK(PWR_SLP_S3)
+#define IN_PCH_SLP_S4 POWER_SIGNAL_MASK(PWR_SLP_S4)
+#define IN_PCH_SLP_S5 POWER_SIGNAL_MASK(PWR_SLP_S5)
 
+/*
+ * Define the chipset specific power signal masks and values
+ * matching the AP state.
+ */
 #if defined(CONFIG_AP_X86_INTEL_ADL)
 
 /* Input state flags */
@@ -21,18 +25,31 @@
 #define PWRSEQ_G3S5_UP_SIGNAL IN_PCH_SLP_SUS
 #define PWRSEQ_G3S5_UP_VALUE 0
 
-#define MASK_ALL_POWER_GOOD \
-		(POWER_SIGNAL_MASK(PWR_RSMRST) |	\
-		 POWER_SIGNAL_MASK(PWR_ALL_SYS_PWRGD) |	\
-		 POWER_SIGNAL_MASK(PWR_DSW_PWROK) |	\
-		 POWER_SIGNAL_MASK(PWR_PG_PP1P05))
-#define MASK_S0	\
-	(MASK_ALL_POWER_GOOD |			\
-	 POWER_SIGNAL_MASK(PWR_SLP_S0) |	\
-	 POWER_SIGNAL_MASK(PWR_SLP_S3) |	\
-	 POWER_SIGNAL_MASK(PWR_SLP_SUS) |	\
-	 POWER_SIGNAL_MASK(PWR_SLP_S4) |	\
+#define MASK_ALL_POWER_GOOD                     \
+	(POWER_SIGNAL_MASK(PWR_RSMRST) |        \
+	 POWER_SIGNAL_MASK(PWR_ALL_SYS_PWRGD) | \
+	 POWER_SIGNAL_MASK(PWR_DSW_PWROK) | POWER_SIGNAL_MASK(PWR_PG_PP1P05))
+
+#define MASK_VW_POWER                                                       \
+	(POWER_SIGNAL_MASK(PWR_RSMRST) | POWER_SIGNAL_MASK(PWR_DSW_PWROK) | \
+	 POWER_SIGNAL_MASK(PWR_SLP_SUS))
+#define VALUE_VW_POWER \
+	(POWER_SIGNAL_MASK(PWR_RSMRST) | POWER_SIGNAL_MASK(PWR_DSW_PWROK))
+
+#define MASK_S0                                                           \
+	(MASK_ALL_POWER_GOOD | POWER_SIGNAL_MASK(PWR_SLP_S0) |            \
+	 POWER_SIGNAL_MASK(PWR_SLP_S3) | POWER_SIGNAL_MASK(PWR_SLP_SUS) | \
+	 POWER_SIGNAL_MASK(PWR_SLP_S4) | POWER_SIGNAL_MASK(PWR_SLP_S5))
+#define VALUE_S0 MASK_ALL_POWER_GOOD
+
+#define MASK_S3 MASK_S0
+#define VALUE_S3 (MASK_ALL_POWER_GOOD | POWER_SIGNAL_MASK(PWR_SLP_S3))
+
+#define MASK_S5                                                             \
+	(POWER_SIGNAL_MASK(PWR_RSMRST) | POWER_SIGNAL_MASK(PWR_DSW_PWROK) | \
+	 POWER_SIGNAL_MASK(PWR_SLP_S3) | POWER_SIGNAL_MASK(PWR_SLP_S4) |    \
 	 POWER_SIGNAL_MASK(PWR_SLP_S5))
+#define VALUE_S5 MASK_S5
 
 #elif defined(CONFIG_AP_X86_INTEL_MTL)
 
@@ -41,21 +58,27 @@
 #define PWRSEQ_G3S5_UP_VALUE IN_PGOOD_ALL_CORE
 
 #define MASK_ALL_POWER_GOOD \
-		(POWER_SIGNAL_MASK(PWR_RSMRST) |	\
-		 POWER_SIGNAL_MASK(PWR_ALL_SYS_PWRGD))
-#define MASK_S0	\
-	(MASK_ALL_POWER_GOOD |			\
-	 POWER_SIGNAL_MASK(PWR_SLP_S0) |	\
-	 POWER_SIGNAL_MASK(PWR_SLP_S3) |	\
-	 POWER_SIGNAL_MASK(PWR_SLP_S4) |	\
+	(POWER_SIGNAL_MASK(PWR_RSMRST) | POWER_SIGNAL_MASK(PWR_ALL_SYS_PWRGD))
+
+#define MASK_VW_POWER POWER_SIGNAL_MASK(PWR_RSMRST)
+#define VALUE_VW_POWER POWER_SIGNAL_MASK(PWR_RSMRST)
+
+#define MASK_S0                                                          \
+	(MASK_ALL_POWER_GOOD | POWER_SIGNAL_MASK(PWR_SLP_S0) |           \
+	 POWER_SIGNAL_MASK(PWR_SLP_S3) | POWER_SIGNAL_MASK(PWR_SLP_S4) | \
 	 POWER_SIGNAL_MASK(PWR_SLP_S5))
+#define VALUE_S0 MASK_ALL_POWER_GOOD
+
+#define MASK_S3 MASK_S0
+#define VALUE_S3 (MASK_ALL_POWER_GOOD | POWER_SIGNAL_MASK(PWR_SLP_S3))
+
+#define MASK_S5                                                          \
+	(POWER_SIGNAL_MASK(PWR_RSMRST) | POWER_SIGNAL_MASK(PWR_SLP_S3) | \
+	 POWER_SIGNAL_MASK(PWR_SLP_S4) | POWER_SIGNAL_MASK(PWR_SLP_S5))
+#define VALUE_S5 MASK_S5
 
 #else
 #warning("Input power signals state flags not defined");
 #endif
 
-#define MASK_S5 \
-	(MASK_ALL_POWER_GOOD |			\
-	 POWER_SIGNAL_MASK(PWR_SLP_S5))
-
 #endif /* __X86_POWER_SIGNALS_H__ */
diff --git a/zephyr/subsys/ap_pwrseq/power_host_sleep.c b/zephyr/subsys/ap_pwrseq/power_host_sleep.c
index ff512fa941..30025d21ea 100644
--- a/zephyr/subsys/ap_pwrseq/power_host_sleep.c
+++ b/zephyr/subsys/ap_pwrseq/power_host_sleep.c
@@ -1,9 +1,10 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include <ap_power/ap_power_interface.h>
+#include <ap_power/ap_pwrseq.h>
 #include <x86_non_dsx_common_pwrseq_sm_handler.h>
 
 LOG_MODULE_DECLARE(ap_pwrseq, CONFIG_AP_PWRSEQ_LOG_LEVEL);
@@ -11,8 +12,9 @@ LOG_MODULE_DECLARE(ap_pwrseq, CONFIG_AP_PWRSEQ_LOG_LEVEL);
 #if CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI
 
 /* If host doesn't program S0ix lazy wake mask, use default S0ix mask */
-#define DEFAULT_WAKE_MASK_S0IX  (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \
-				EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
+#define DEFAULT_WAKE_MASK_S0IX                        \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
 
 /*
  * Set the wake mask according to the current power state:
@@ -33,7 +35,7 @@ void power_update_wake_mask(void)
 	if (state == SYS_POWER_STATE_S0)
 		wake_mask = 0;
 	else if (lpc_is_active_wm_set_by_host() ||
-		ap_power_get_lazy_wake_mask(state, &wake_mask))
+		 ap_power_get_lazy_wake_mask(state, &wake_mask))
 		return;
 #if CONFIG_AP_PWRSEQ_S0IX
 	if ((state == SYS_POWER_STATE_S0ix) && (wake_mask == 0))
@@ -48,8 +50,8 @@ static void power_update_wake_mask_deferred(struct k_work *work)
 	power_update_wake_mask();
 }
 
-static K_WORK_DELAYABLE_DEFINE(
-	power_update_wake_mask_deferred_data, power_update_wake_mask_deferred);
+static K_WORK_DELAYABLE_DEFINE(power_update_wake_mask_deferred_data,
+			       power_update_wake_mask_deferred);
 
 void ap_power_set_active_wake_mask(void)
 {
@@ -74,14 +76,16 @@ void ap_power_set_active_wake_mask(void)
 		 * has changed again and the work is not processed, we should
 		 * reschedule it.
 		 */
-		rv = k_work_reschedule(
-			&power_update_wake_mask_deferred_data, K_MSEC(5));
+		rv = k_work_reschedule(&power_update_wake_mask_deferred_data,
+				       K_MSEC(5));
 	}
 	__ASSERT(rv >= 0, "Set wake mask work queue error");
 }
 
 #else /* CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI */
-static void ap_power_set_active_wake_mask(void) { }
+static void ap_power_set_active_wake_mask(void)
+{
+}
 #endif /* CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI */
 
 #if CONFIG_AP_PWRSEQ_S0IX
@@ -180,11 +184,14 @@ void ap_power_sleep_notify_transition(enum ap_power_sleep_type check_state)
 #if CONFIG_AP_PWRSEQ_HOST_SLEEP
 #define HOST_SLEEP_EVENT_DEFAULT_RESET 0
 
+static struct host_sleep_event_context *g_ctx;
+
 void ap_power_reset_host_sleep_state(void)
 {
 	power_set_host_sleep_state(HOST_SLEEP_EVENT_DEFAULT_RESET);
-	ap_power_chipset_handle_host_sleep_event(
-			HOST_SLEEP_EVENT_DEFAULT_RESET, NULL);
+	ap_power_ev_send_callbacks(AP_POWER_S0IX_RESET_TRACKING);
+	ap_power_chipset_handle_host_sleep_event(HOST_SLEEP_EVENT_DEFAULT_RESET,
+						 NULL);
 }
 
 /* TODO: hook to reset event */
@@ -195,19 +202,21 @@ void ap_power_handle_chipset_reset(void)
 }
 
 void ap_power_chipset_handle_host_sleep_event(
-		enum host_sleep_event state,
-		struct host_sleep_event_context *ctx)
+	enum host_sleep_event state, struct host_sleep_event_context *ctx)
 {
 	LOG_DBG("host sleep event = %d!", state);
+
+	g_ctx = ctx;
+
 #if CONFIG_AP_PWRSEQ_S0IX
 	if (state == HOST_SLEEP_EVENT_S0IX_SUSPEND) {
-
 		/*
 		 * Indicate to power state machine that a new host event for
 		 * s0ix/s3 suspend has been received and so chipset suspend
 		 * notification needs to be sent to listeners.
 		 */
 		ap_power_sleep_set_notify(AP_POWER_SLEEP_SUSPEND);
+		ap_power_ev_send_callbacks(AP_POWER_S0IX_SUSPEND_START);
 		power_signal_enable(PWR_SLP_S0);
 
 	} else if (state == HOST_SLEEP_EVENT_S0IX_RESUME) {
@@ -218,6 +227,7 @@ void ap_power_chipset_handle_host_sleep_event(
 		ap_power_sleep_set_notify(AP_POWER_SLEEP_RESUME);
 		power_s0ix_resume_restore_masks();
 		power_signal_disable(PWR_SLP_S0);
+		ap_power_ev_send_callbacks(AP_POWER_S0IX_RESUME_COMPLETE);
 
 		/*
 		 * If the sleep signal timed out and never transitioned, then
@@ -231,6 +241,17 @@ void ap_power_chipset_handle_host_sleep_event(
 		power_signal_disable(PWR_SLP_S0);
 	}
 #endif /* CONFIG_AP_PWRSEQ_S0IX */
+	ap_pwrseq_wake();
+}
+
+uint16_t host_get_sleep_timeout(void)
+{
+	return g_ctx->sleep_timeout_ms;
+}
+
+void host_set_sleep_transitions(uint32_t val)
+{
+	g_ctx->sleep_transitions = val;
 }
 
 #endif /* CONFIG_AP_PWRSEQ_HOST_SLEEP */
diff --git a/zephyr/subsys/ap_pwrseq/power_signals.c b/zephyr/subsys/ap_pwrseq/power_signals.c
index 135a0d9ac1..a02eef6e6b 100644
--- a/zephyr/subsys/ap_pwrseq/power_signals.c
+++ b/zephyr/subsys/ap_pwrseq/power_signals.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,6 +8,7 @@
 #include <zephyr/logging/log.h>
 #include <zephyr/sys/atomic.h>
 
+#include <ap_power/ap_pwrseq.h>
 #include <power_signals.h>
 
 #include "signal_gpio.h"
@@ -18,7 +19,7 @@ LOG_MODULE_DECLARE(ap_pwrseq, CONFIG_AP_PWRSEQ_LOG_LEVEL);
 
 #if DT_HAS_COMPAT_STATUS_OKAY(intel_ap_pwrseq)
 BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(intel_ap_pwrseq) == 1,
-	"Only one node for intel_ap_pwrseq is allowed");
+	     "Only one node for intel_ap_pwrseq is allowed");
 #endif
 
 BUILD_ASSERT(POWER_SIGNAL_COUNT <= 32, "Too many power signals");
@@ -41,49 +42,46 @@ struct ps_config {
 
 #define TAG_PWR_ENUM(tag, name) DT_CAT(tag, name)
 
-#define PWR_ENUM(id, tag)			\
-	TAG_PWR_ENUM(tag, PWR_SIGNAL_ENUM(id))
+#define PWR_ENUM(id, tag) TAG_PWR_ENUM(tag, PWR_SIGNAL_ENUM(id))
 
-#define DBGNAME(id) \
-	"(" DT_PROP(id, enum_name) ") " \
-	    DT_PROP(id, dbg_label)
+#define DBGNAME(id) "(" DT_PROP(id, enum_name) ") " DT_PROP(id, dbg_label)
 
-#define GEN_PS_ENTRY(id, src, tag)		\
-{						\
-	.debug_name = DBGNAME(id),	\
-	.source = src,				\
-	.src_enum = PWR_ENUM(id, tag),		\
-},
-
-#define GEN_PS_ENTRY_NO_ENUM(id, src)		\
-{						\
-	.debug_name = DBGNAME(id),	\
-	.source = src,				\
-},
+#define GEN_PS_ENTRY(id, src, tag)             \
+	{                                      \
+		.debug_name = DBGNAME(id),     \
+		.source = src,                 \
+		.src_enum = PWR_ENUM(id, tag), \
+	},
 
+#define GEN_PS_ENTRY_NO_ENUM(id, src)      \
+	{                                  \
+		.debug_name = DBGNAME(id), \
+		.source = src,             \
+	},
 
 /*
  * Generate the power signal configuration array.
  */
 static const struct ps_config sig_config[] = {
-DT_FOREACH_STATUS_OKAY_VARGS(intel_ap_pwrseq_gpio, GEN_PS_ENTRY,
-			     PWR_SIG_SRC_GPIO, PWR_SIG_TAG_GPIO)
-DT_FOREACH_STATUS_OKAY_VARGS(intel_ap_pwrseq_vw, GEN_PS_ENTRY,
-			     PWR_SIG_SRC_VW, PWR_SIG_TAG_VW)
-DT_FOREACH_STATUS_OKAY_VARGS(intel_ap_pwrseq_external, GEN_PS_ENTRY_NO_ENUM,
-			     PWR_SIG_SRC_EXT)
-DT_FOREACH_STATUS_OKAY_VARGS(intel_ap_pwrseq_adc, GEN_PS_ENTRY,
-			     PWR_SIG_SRC_ADC, PWR_SIG_TAG_ADC)
+	DT_FOREACH_STATUS_OKAY_VARGS(intel_ap_pwrseq_gpio, GEN_PS_ENTRY,
+				     PWR_SIG_SRC_GPIO, PWR_SIG_TAG_GPIO)
+		DT_FOREACH_STATUS_OKAY_VARGS(intel_ap_pwrseq_vw, GEN_PS_ENTRY,
+					     PWR_SIG_SRC_VW, PWR_SIG_TAG_VW)
+			DT_FOREACH_STATUS_OKAY_VARGS(intel_ap_pwrseq_external,
+						     GEN_PS_ENTRY_NO_ENUM,
+						     PWR_SIG_SRC_EXT)
+				DT_FOREACH_STATUS_OKAY_VARGS(
+					intel_ap_pwrseq_adc, GEN_PS_ENTRY,
+					PWR_SIG_SRC_ADC, PWR_SIG_TAG_ADC)
 };
 
-#define PWR_SIGNAL_POLLED(id)	PWR_SIGNAL_ENUM(id),
+#define PWR_SIGNAL_POLLED(id) PWR_SIGNAL_ENUM(id),
 
 /*
  * List of power signals that need to be polled.
  */
-static const uint8_t polled_signals[] = {
-DT_FOREACH_STATUS_OKAY(intel_ap_pwrseq_external, PWR_SIGNAL_POLLED)
-};
+static const uint8_t polled_signals[] = { DT_FOREACH_STATUS_OKAY(
+	intel_ap_pwrseq_external, PWR_SIGNAL_POLLED) };
 
 /*
  * Bitmasks of power signals. A previous copy is held so that
@@ -112,7 +110,7 @@ static inline void check_debug(enum power_signal signal)
 	 */
 	if ((CONFIG_AP_PWRSEQ_LOG_LEVEL >= LOG_LEVEL_INF) &&
 	    (debug_signals & POWER_SIGNAL_MASK(signal))) {
-		bool value =  atomic_test_bit(&power_signals, signal);
+		bool value = atomic_test_bit(&power_signals, signal);
 
 		if (value != atomic_test_bit(&prev_power_signals, signal)) {
 			LOG_INF("%s -> %d", power_signal_name(signal), value);
@@ -137,11 +135,11 @@ void power_signal_interrupt(enum power_signal signal, int value)
 {
 	atomic_set_bit_to(&power_signals, signal, value);
 	check_debug(signal);
+	ap_pwrseq_wake();
 }
 
 int power_wait_mask_signals_timeout(power_signal_mask_t mask,
-				    power_signal_mask_t want,
-				    int timeout)
+				    power_signal_mask_t want, int timeout)
 {
 	if (mask == 0) {
 		return 0;
@@ -166,7 +164,7 @@ int power_signal_get(enum power_signal signal)
 	cp = &sig_config[signal];
 	switch (cp->source) {
 	default:
-		return -EINVAL;  /* should never happen */
+		return -EINVAL; /* should never happen */
 
 #if HAS_GPIO_SIGNALS
 	case PWR_SIG_SRC_GPIO:
diff --git a/zephyr/subsys/ap_pwrseq/signal_adc.c b/zephyr/subsys/ap_pwrseq/signal_adc.c
index 4b8f0e0366..c23cd0d30a 100644
--- a/zephyr/subsys/ap_pwrseq/signal_adc.c
+++ b/zephyr/subsys/ap_pwrseq/signal_adc.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,7 +11,7 @@
 #include <power_signals.h>
 #include <signal_adc.h>
 
-#define MY_COMPAT	intel_ap_pwrseq_adc
+#define MY_COMPAT intel_ap_pwrseq_adc
 
 #if HAS_ADC_SIGNALS
 
@@ -26,74 +26,59 @@ struct adc_config {
 	enum power_signal signal;
 };
 
-#define	ADC_HIGH_DEV(id)	DEVICE_DT_GET(DT_IO_CHANNELS_CTLR(id))
+#define ADC_HIGH_DEV(id) DEVICE_DT_GET(DT_IO_CHANNELS_CTLR(id))
 
-#define	ADC_HIGH_CHAN(id)	DT_IO_CHANNELS_INPUT(id)
+#define ADC_HIGH_CHAN(id) DT_IO_CHANNELS_INPUT(id)
 
-#define	ADC_THRESH(id)	DT_PROP(id, threshold_mv)
+#define ADC_THRESH(id) DT_PROP(id, threshold_mv)
 
-#define INIT_ADC_CONFIG(id)	\
-{									\
-	.dev_trig_high = DEVICE_DT_GET(DT_PHANDLE(id, trigger_high)),	\
-	.dev_trig_low = DEVICE_DT_GET(DT_PHANDLE(id, trigger_low)),	\
-	.adc_dev = ADC_HIGH_DEV(DT_PHANDLE(id, trigger_high)),		\
-	.adc_ch = ADC_HIGH_CHAN(DT_PHANDLE(id, trigger_high)),	\
-	.threshold = ADC_THRESH(DT_PHANDLE(id, trigger_high)),		\
-	.signal = PWR_SIGNAL_ENUM(id),					\
-},
+#define INIT_ADC_CONFIG(id)                                                   \
+	{                                                                     \
+		.dev_trig_high = DEVICE_DT_GET(DT_PHANDLE(id, trigger_high)), \
+		.dev_trig_low = DEVICE_DT_GET(DT_PHANDLE(id, trigger_low)),   \
+		.adc_dev = ADC_HIGH_DEV(DT_PHANDLE(id, trigger_high)),        \
+		.adc_ch = ADC_HIGH_CHAN(DT_PHANDLE(id, trigger_high)),        \
+		.threshold = ADC_THRESH(DT_PHANDLE(id, trigger_high)),        \
+		.signal = PWR_SIGNAL_ENUM(id),                                \
+	},
 
-static const struct adc_config config[] = {
-DT_FOREACH_STATUS_OKAY(MY_COMPAT, INIT_ADC_CONFIG)
-};
+static const struct adc_config config[] = { DT_FOREACH_STATUS_OKAY(
+	MY_COMPAT, INIT_ADC_CONFIG) };
 
 /*
  * Bit allocations for atomic state
  */
-enum {
-	ADC_BIT_VALUE = 0,
-	ADC_BIT_LOW_ENABLED = 1,
-	ADC_BIT_HIGH_ENABLED = 2
-};
+enum { ADC_BIT_VALUE = 0, ADC_BIT_LOW_ENABLED = 1, ADC_BIT_HIGH_ENABLED = 2 };
 
 atomic_t adc_state[ARRAY_SIZE(config)];
 
-static void set_trigger(const struct device *dev,
-			atomic_t *state,
-			int bit,
+static void set_trigger(const struct device *dev, atomic_t *state, int bit,
 			bool enable)
 {
 	/*
 	 * Only enable or disable if the trigger is not
 	 * already enabled or disabled.
 	 */
-	if (enable
-		? !atomic_test_and_set_bit(state, bit)
-		: atomic_test_and_clear_bit(state, bit)) {
+	if (enable ? !atomic_test_and_set_bit(state, bit) :
+		     atomic_test_and_clear_bit(state, bit)) {
 		struct sensor_value val;
 
 		val.val1 = enable;
-		sensor_attr_set(dev,
-				SENSOR_CHAN_VOLTAGE,
-				SENSOR_ATTR_ALERT,
+		sensor_attr_set(dev, SENSOR_CHAN_VOLTAGE, SENSOR_ATTR_ALERT,
 				&val);
 	}
 }
 
 static void set_low_trigger(enum pwr_sig_adc adc, bool enable)
 {
-	set_trigger(config[adc].dev_trig_low,
-		    &adc_state[adc],
-		    ADC_BIT_LOW_ENABLED,
-		    enable);
-
+	set_trigger(config[adc].dev_trig_low, &adc_state[adc],
+		    ADC_BIT_LOW_ENABLED, enable);
 }
 
 static void set_high_trigger(enum pwr_sig_adc adc, bool enable)
 {
-	set_trigger(config[adc].dev_trig_high,
-		    &adc_state[adc],
-		    ADC_BIT_HIGH_ENABLED,
-		    enable);
+	set_trigger(config[adc].dev_trig_high, &adc_state[adc],
+		    ADC_BIT_HIGH_ENABLED, enable);
 }
 
 static void trigger_high(enum pwr_sig_adc adc)
@@ -156,34 +141,30 @@ int power_signal_adc_disable(enum pwr_sig_adc adc)
 
 #define PWR_ADC_ENUM(id) TAG_ADC(PWR_SIG_TAG_ADC, PWR_SIGNAL_ENUM(id))
 
-#define ADC_CB(id, lev)	cb_##lev##_##id
+#define ADC_CB(id, lev) cb_##lev##_##id
 
-#define ADC_CB_DEFINE(id, lev)					\
-static void ADC_CB(id, lev)(const struct device *dev,		\
-		       const struct sensor_trigger *trigger)	\
-{								\
-	trigger_##lev(PWR_ADC_ENUM(id));			\
-}
+#define ADC_CB_DEFINE(id, lev)                                            \
+	static void ADC_CB(id, lev)(const struct device *dev,             \
+				    const struct sensor_trigger *trigger) \
+	{                                                                 \
+		trigger_##lev(PWR_ADC_ENUM(id));                          \
+	}
 
 DT_FOREACH_STATUS_OKAY_VARGS(MY_COMPAT, ADC_CB_DEFINE, high)
 DT_FOREACH_STATUS_OKAY_VARGS(MY_COMPAT, ADC_CB_DEFINE, low)
 
-#define ADC_CB_COMMA(id, lev)	ADC_CB(id, lev),
+#define ADC_CB_COMMA(id, lev) ADC_CB(id, lev),
 
 void power_signal_adc_init(void)
 {
-	struct sensor_trigger trig = {
-		.type = SENSOR_TRIG_THRESHOLD,
-		.chan = SENSOR_CHAN_VOLTAGE
-	};
-	sensor_trigger_handler_t low_cb[] = {
-		DT_FOREACH_STATUS_OKAY_VARGS(MY_COMPAT, ADC_CB_COMMA, low)
-	};
-	sensor_trigger_handler_t high_cb[] = {
-		DT_FOREACH_STATUS_OKAY_VARGS(MY_COMPAT, ADC_CB_COMMA, high)
-	};
+	struct sensor_trigger trig = { .type = SENSOR_TRIG_THRESHOLD,
+				       .chan = SENSOR_CHAN_VOLTAGE };
+	sensor_trigger_handler_t low_cb[] = { DT_FOREACH_STATUS_OKAY_VARGS(
+		MY_COMPAT, ADC_CB_COMMA, low) };
+	sensor_trigger_handler_t high_cb[] = { DT_FOREACH_STATUS_OKAY_VARGS(
+		MY_COMPAT, ADC_CB_COMMA, high) };
 	int i, rv;
-	int32_t val;
+	int32_t val = 0;
 
 	for (i = 0; i < ARRAY_SIZE(low_cb); i++) {
 		/*
@@ -202,11 +183,10 @@ void power_signal_adc_init(void)
 
 		rv = adc_read(dev, &seq);
 		if (rv) {
-			LOG_ERR("ADC %s:%d initial read failed",
-				dev->name, config[i].adc_ch);
+			LOG_ERR("ADC %s:%d initial read failed", dev->name,
+				config[i].adc_ch);
 		} else {
-			adc_raw_to_millivolts(adc_ref_internal(dev),
-					      ADC_GAIN_1,
+			adc_raw_to_millivolts(adc_ref_internal(dev), ADC_GAIN_1,
 					      CONFIG_PLATFORM_EC_ADC_RESOLUTION,
 					      &val);
 			if (val >= config[i].threshold) {
diff --git a/zephyr/subsys/ap_pwrseq/signal_gpio.c b/zephyr/subsys/ap_pwrseq/signal_gpio.c
index 9f8c3adb48..1dbd430bef 100644
--- a/zephyr/subsys/ap_pwrseq/signal_gpio.c
+++ b/zephyr/subsys/ap_pwrseq/signal_gpio.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,16 +8,14 @@
 #include <zephyr/drivers/gpio.h>
 #include "system.h"
 
-#define MY_COMPAT	intel_ap_pwrseq_gpio
+#define MY_COMPAT intel_ap_pwrseq_gpio
 
 #if HAS_GPIO_SIGNALS
 
-#define INIT_GPIO_SPEC(id)	\
-	GPIO_DT_SPEC_GET(id, gpios),
+#define INIT_GPIO_SPEC(id) GPIO_DT_SPEC_GET(id, gpios),
 
-const static struct gpio_dt_spec spec[] = {
-DT_FOREACH_STATUS_OKAY(MY_COMPAT, INIT_GPIO_SPEC)
-};
+const static struct gpio_dt_spec spec[] = { DT_FOREACH_STATUS_OKAY(
+	MY_COMPAT, INIT_GPIO_SPEC) };
 
 /*
  * Configuration for GPIO inputs.
@@ -29,17 +27,16 @@ struct ps_gpio_int {
 	unsigned no_enable : 1;
 };
 
-#define INIT_GPIO_CONFIG(id)					\
-	{							\
-		.flags = DT_PROP_OR(id, interrupt_flags, 0),	\
-		.signal = PWR_SIGNAL_ENUM(id),			\
-		.no_enable = DT_PROP(id, no_enable),		\
-		.output = DT_PROP(id, output),			\
-	 },
+#define INIT_GPIO_CONFIG(id)                                 \
+	{                                                    \
+		.flags = DT_PROP_OR(id, interrupt_flags, 0), \
+		.signal = PWR_SIGNAL_ENUM(id),               \
+		.no_enable = DT_PROP(id, no_enable),         \
+		.output = DT_PROP(id, output),               \
+	},
 
-const static struct ps_gpio_int gpio_config[] = {
-DT_FOREACH_STATUS_OKAY(MY_COMPAT, INIT_GPIO_CONFIG)
-};
+const static struct ps_gpio_int gpio_config[] = { DT_FOREACH_STATUS_OKAY(
+	MY_COMPAT, INIT_GPIO_CONFIG) };
 
 static struct gpio_callback int_cb[ARRAY_SIZE(gpio_config)];
 
@@ -103,6 +100,34 @@ int power_signal_gpio_get(enum pwr_sig_gpio index)
 	if (index < 0 || index >= ARRAY_SIZE(gpio_config)) {
 		return -EINVAL;
 	}
+	/*
+	 * Getting the current value of an output is
+	 * done by retrieving the config and checking what the
+	 * output state has been set to, not by reading the
+	 * physical level of the pin (open drain outputs
+	 * may have a low voltage).
+	 */
+	if (IS_ENABLED(CONFIG_GPIO_GET_CONFIG) && gpio_config[index].output) {
+		int rv;
+		gpio_flags_t flags;
+
+		rv = gpio_pin_get_config_dt(&spec[index], &flags);
+		if (rv == 0) {
+			int pin = (flags & GPIO_OUTPUT_INIT_HIGH) ? 1 : 0;
+			/* If active low signal, invert it */
+			if (spec[index].dt_flags & GPIO_ACTIVE_LOW) {
+				pin = !pin;
+			}
+			return pin;
+		}
+		/*
+		 * -ENOSYS is returned when this API call is not supported,
+		 *  so drop into the default method of returning the pin value.
+		 */
+		if (rv != -ENOSYS) {
+			return rv;
+		}
+	}
 	return gpio_pin_get_dt(&spec[index]);
 }
 
@@ -123,7 +148,8 @@ void power_signal_gpio_init(void)
 	 * to the deasserted state.
 	 */
 	gpio_flags_t out_flags = system_jumped_to_this_image() ?
-				 GPIO_OUTPUT : GPIO_OUTPUT_INACTIVE;
+					 GPIO_OUTPUT :
+					 GPIO_OUTPUT_INACTIVE;
 
 	for (int i = 0; i < ARRAY_SIZE(gpio_config); i++) {
 		if (gpio_config[i].output) {
@@ -133,8 +159,8 @@ void power_signal_gpio_init(void)
 			/* If interrupt, initialise it */
 			if (gpio_config[i].flags) {
 				gpio_init_callback(&int_cb[i],
-					   power_signal_gpio_interrupt,
-					   BIT(spec[i].pin));
+						   power_signal_gpio_interrupt,
+						   BIT(spec[i].pin));
 				gpio_add_callback(spec[i].port, &int_cb[i]);
 				/*
 				 * If the interrupt is to be enabled at
diff --git a/zephyr/subsys/ap_pwrseq/signal_vw.c b/zephyr/subsys/ap_pwrseq/signal_vw.c
index de2756c137..0e9e4affff 100644
--- a/zephyr/subsys/ap_pwrseq/signal_vw.c
+++ b/zephyr/subsys/ap_pwrseq/signal_vw.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,40 +9,47 @@
 
 #include "signal_vw.h"
 
-#define MY_COMPAT	intel_ap_pwrseq_vw
+#define MY_COMPAT intel_ap_pwrseq_vw
 
 #if HAS_VW_SIGNALS
 
+/*
+ * A callback must be registered on the ESPI device (for the
+ * bus events that are required to be handled) that calls
+ * power_signal_espi_cb().
+ *
+ * This registration is done in a common ESPI initialisation module so
+ * that there is no possibility of missing events.
+ */
+
 LOG_MODULE_DECLARE(ap_pwrseq, CONFIG_AP_PWRSEQ_LOG_LEVEL);
 
-#define INIT_ESPI_SIGNAL(id)					\
-{								\
-	.espi_signal = DT_STRING_UPPER_TOKEN(id, virtual_wire),	\
-	.signal = PWR_SIGNAL_ENUM(id),				\
-	.invert = DT_PROP(id, vw_invert),			\
-},
+#define INIT_ESPI_SIGNAL(id)                                            \
+	{                                                               \
+		.espi_signal = DT_STRING_UPPER_TOKEN(id, virtual_wire), \
+		.signal = PWR_SIGNAL_ENUM(id),                          \
+		.invert = DT_PROP(id, vw_invert),                       \
+	},
 
 /*
  * Struct containing the eSPI virtual wire config.
  */
 struct vw_config {
-	uint8_t espi_signal;	/* associated VW signal */
-	uint8_t signal;		/* power signal */
-	bool invert;		/* Invert the signal value */
+	uint8_t espi_signal; /* associated VW signal */
+	uint8_t signal; /* power signal */
+	bool invert; /* Invert the signal value */
 };
 
-const static struct vw_config vw_config[] = {
-DT_FOREACH_STATUS_OKAY(MY_COMPAT, INIT_ESPI_SIGNAL)
-};
+const static struct vw_config vw_config[] = { DT_FOREACH_STATUS_OKAY(
+	MY_COMPAT, INIT_ESPI_SIGNAL) };
 
 /*
  * Current signal value.
  */
 static atomic_t signal_data;
 /*
- * Mask of valid signals. If the bus is reset, this is cleared,
- * and when a signal is updated the associated bit is set to indicate
- * the signal is valid.
+ * Mask of valid signals. A signal is considered valid once an
+ * initial value has been received for it.
  */
 static atomic_t signal_valid;
 
@@ -50,36 +57,63 @@ static atomic_t signal_valid;
 
 BUILD_ASSERT(ARRAY_SIZE(vw_config) <= (sizeof(atomic_t) * 8));
 
-static void espi_handler(const struct device *dev,
-			 struct espi_callback *cb,
-			 struct espi_event event)
+/*
+ * Set the value of the VW signal, and optionally
+ * call the power signal interrupt handling.
+ */
+static void vw_set(int index, int data, bool notify)
+{
+	bool value = vw_config[index].invert ? !data : !!data;
+
+	atomic_set_bit_to(&signal_data, index, value);
+	atomic_set_bit(&signal_valid, index);
+	if (notify) {
+		power_signal_interrupt(vw_config[index].signal, value);
+	}
+}
+
+/*
+ * Update all the VW signals.
+ */
+static void vw_update_all(bool notify)
+{
+	for (int i = 0; i < ARRAY_SIZE(vw_config); i++) {
+		uint8_t vw_value;
+
+		if (espi_receive_vwire(espi_dev, vw_config[i].espi_signal,
+				       &vw_value) == 0) {
+			vw_set(i, vw_value, notify);
+		}
+	}
+}
+
+void power_signal_espi_cb(const struct device *dev, struct espi_callback *cb,
+			  struct espi_event event)
 {
-	LOG_DBG("ESPI event type 0x%x %d:%d", event.evt_type,
-		event.evt_details, event.evt_data);
+	LOG_DBG("ESPI event type 0x%x %d:%d", event.evt_type, event.evt_details,
+		event.evt_data);
 	switch (event.evt_type) {
 	default:
-		__ASSERT(0, "ESPI unknown event type: %d",
-			 event.evt_type);
+		__ASSERT(0, "ESPI unknown event type: %d", event.evt_type);
 		break;
 
-	case ESPI_BUS_RESET:
-		/*
-		 * Clear the signal valid mask.
-		 */
-		atomic_clear(&signal_valid);
+	case ESPI_BUS_EVENT_CHANNEL_READY:
+		/* Virtual wire channel status change */
+		if (event.evt_details == ESPI_CHANNEL_VWIRE) {
+			if (event.evt_data) {
+				/* If now ready, update all the signals */
+				vw_update_all(true);
+			} else {
+				/* If not ready, invalidate the signals */
+				atomic_clear(&signal_valid);
+			}
+		}
 		break;
 
 	case ESPI_BUS_EVENT_VWIRE_RECEIVED:
 		for (int i = 0; i < ARRAY_SIZE(vw_config); i++) {
 			if (event.evt_details == vw_config[i].espi_signal) {
-				bool value = vw_config[i].invert
-						? !event.evt_data
-						: !!event.evt_data;
-
-				atomic_set_bit_to(&signal_data, i, value);
-				atomic_set_bit(&signal_valid, i);
-				power_signal_interrupt(vw_config[i].signal,
-						       value);
+				vw_set(i, event.evt_data, true);
 			}
 		}
 		break;
@@ -97,34 +131,12 @@ int power_signal_vw_get(enum pwr_sig_vw vw)
 
 void power_signal_vw_init(void)
 {
-	static struct espi_callback espi_cb;
-
-	/* Assumes ESPI device is already configured. */
-
-	/* Configure handler for eSPI events */
-	espi_init_callback(&espi_cb, espi_handler,
-			   ESPI_BUS_RESET |
-			   ESPI_BUS_EVENT_VWIRE_RECEIVED);
-	espi_add_callback(espi_dev, &espi_cb);
 	/*
 	 * Check whether the bus is ready, and if so,
 	 * initialise the current values of the signals.
 	 */
 	if (espi_get_channel_status(espi_dev, ESPI_CHANNEL_VWIRE)) {
-		for (int i = 0; i < ARRAY_SIZE(vw_config); i++) {
-			uint8_t vw_value;
-
-			if (espi_receive_vwire(espi_dev,
-					   vw_config[i].espi_signal,
-					   &vw_value) == 0) {
-				atomic_set_bit_to(&signal_data, i,
-					vw_config[i].invert
-						? !vw_value
-						: !!vw_value);
-				atomic_set_bit(&signal_valid, i);
-
-			}
-		}
+		vw_update_all(false);
 	}
 }
 
diff --git a/zephyr/subsys/ap_pwrseq/x86_non_dsx_adlp_pwrseq_sm.c b/zephyr/subsys/ap_pwrseq/x86_non_dsx_adlp_pwrseq_sm.c
index 375e93c74f..9ef482b712 100644
--- a/zephyr/subsys/ap_pwrseq/x86_non_dsx_adlp_pwrseq_sm.c
+++ b/zephyr/subsys/ap_pwrseq/x86_non_dsx_adlp_pwrseq_sm.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -20,8 +20,7 @@ static int check_pch_out_of_suspend(void)
 	/*
 	 * Wait for SLP_SUS deasserted.
 	 */
-	ret = power_wait_mask_signals_timeout(IN_PCH_SLP_SUS,
-					      0,
+	ret = power_wait_mask_signals_timeout(IN_PCH_SLP_SUS, 0,
 					      IN_PCH_SLP_SUS_WAIT_TIME_MS);
 	if (ret == 0) {
 		LOG_DBG("SLP_SUS now %d", power_signal_get(PWR_SLP_SUS));
@@ -38,14 +37,21 @@ int all_sys_pwrgd_handler(void)
 {
 	int retry = 0;
 
+	/* SLP_S3 is off */
+	if (power_signal_get(PWR_SLP_S3) == 1) {
+		ap_off();
+		return 1;
+	}
+
 	/* TODO: Add condition for no power sequencer */
-	k_msleep(AP_PWRSEQ_DT_VALUE(all_sys_pwrgd_timeout));
+	power_wait_signals_timeout(POWER_SIGNAL_MASK(PWR_ALL_SYS_PWRGD),
+				   AP_PWRSEQ_DT_VALUE(all_sys_pwrgd_timeout));
 
 	if (power_signal_get(PWR_DSW_PWROK) == 0) {
-	/* Todo: Remove workaround for the retry
-	 * without this change the system hits G3 as it detects
-	 * ALL_SYS_PWRGD as 0 and then 1 as a glitch
-	 */
+		/* Todo: Remove workaround for the retry
+		 * without this change the system hits G3 as it detects
+		 * ALL_SYS_PWRGD as 0 and then 1 as a glitch
+		 */
 		while (power_signal_get(PWR_ALL_SYS_PWRGD) == 0) {
 			if (++retry > 2) {
 				LOG_ERR("PG_EC_ALL_SYS_PWRGD not ok");
@@ -58,7 +64,7 @@ int all_sys_pwrgd_handler(void)
 
 	/* PG_EC_ALL_SYS_PWRGD is asserted, enable VCCST_PWRGD_OD. */
 
-	if (power_signal_get(PWR_VCCST_PWRGD) == 0) {
+	if (!power_signals_on(POWER_SIGNAL_MASK(PWR_VCCST_PWRGD))) {
 		k_msleep(AP_PWRSEQ_DT_VALUE(vccst_pwrgd_delay));
 		power_signal_set(PWR_VCCST_PWRGD, 1);
 	}
diff --git a/zephyr/subsys/ap_pwrseq/x86_non_dsx_chipset_power_state.c b/zephyr/subsys/ap_pwrseq/x86_non_dsx_chipset_power_state.c
index 97268e8fe6..e4ce364cb1 100644
--- a/zephyr/subsys/ap_pwrseq/x86_non_dsx_chipset_power_state.c
+++ b/zephyr/subsys/ap_pwrseq/x86_non_dsx_chipset_power_state.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,39 +14,41 @@ LOG_MODULE_DECLARE(ap_pwrseq, CONFIG_AP_PWRSEQ_LOG_LEVEL);
  */
 enum power_states_ndsx chipset_pwr_seq_get_state(void)
 {
+	power_signal_mask_t sig = power_get_signals();
+
 	/*
-	 * Chip is shut down.
+	 * Chip is shut down, G3 state.
 	 */
-	if ((power_get_signals() & MASK_ALL_POWER_GOOD) == 0) {
-		LOG_DBG("Power rails off, G3 state");
+	if ((sig & MASK_ALL_POWER_GOOD) == 0) {
+		LOG_DBG("All power rails off, G3 state");
 		return SYS_POWER_STATE_G3;
 	}
 	/*
-	 * If not all the power rails are available,
-	 * then force shutdown to G3 to get to known state.
+	 * Not enough power rails up to read VW signals.
+	 * Force a shutdown.
 	 */
-	if ((power_get_signals() & MASK_ALL_POWER_GOOD)
-			!= MASK_ALL_POWER_GOOD) {
+	if ((sig & MASK_VW_POWER) != VALUE_VW_POWER) {
+		LOG_ERR("Not enough power signals on (%#x), forcing shutdown",
+			sig);
 		ap_power_force_shutdown(AP_POWER_SHUTDOWN_G3);
-		LOG_INF("Not all power rails up, forcing shutdown");
 		return SYS_POWER_STATE_G3;
 	}
 
 	/*
-	 * All the power rails are good, so
+	 * Enough power signals are up, so
 	 * wait for virtual wire signals to become available.
 	 * Not sure how long to wait? 5 seconds total.
 	 */
 	for (int delay = 0; delay < 500; k_msleep(10), delay++) {
-#if defined(CONFIG_PLATFORM_EC_ESPI_VW_SLP_S3)
+#if defined(CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S3)
 		if (power_signal_get(PWR_SLP_S3) < 0)
 			continue;
 #endif
-#if defined(CONFIG_PLATFORM_EC_ESPI_VW_SLP_S4)
+#if defined(CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S4)
 		if (power_signal_get(PWR_SLP_S4) < 0)
 			continue;
 #endif
-#if defined(CONFIG_PLATFORM_EC_ESPI_VW_SLP_S5)
+#if defined(CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S5)
 		if (power_signal_get(PWR_SLP_S5) < 0)
 			continue;
 #endif
@@ -56,32 +58,34 @@ enum power_states_ndsx chipset_pwr_seq_get_state(void)
 		LOG_DBG("All VW signals valid after %d ms", delay * 10);
 		break;
 	}
+	/* Re-read the power signals */
+	sig = power_get_signals();
+
 	/*
 	 * S0, all power OK, no suspend or sleep on.
 	 */
-	if ((power_get_signals() & MASK_S0) == MASK_ALL_POWER_GOOD) {
+	if ((sig & MASK_S0) == VALUE_S0) {
 		LOG_DBG("CPU in S0 state");
 		return SYS_POWER_STATE_S0;
 	}
 	/*
 	 * S3, all power OK, PWR_SLP_S3 on.
 	 */
-	if ((power_get_signals() & MASK_S0) ==
-		(MASK_ALL_POWER_GOOD | POWER_SIGNAL_MASK(PWR_SLP_S3))) {
+	if ((sig & MASK_S3) == VALUE_S3) {
 		LOG_DBG("CPU in S3 state");
 		return SYS_POWER_STATE_S3;
 	}
 	/*
-	 * S5, all power OK, PWR_SLP_S5 on.
+	 * S5, some power signals on, PWR_SLP_S5 on.
 	 */
-	if ((power_get_signals() & MASK_S5) == MASK_S5) {
+	if ((sig & MASK_S5) == VALUE_S5) {
 		LOG_DBG("CPU in S5 state");
 		return SYS_POWER_STATE_S5;
 	}
 	/*
 	 * Unable to determine state, force to G3.
 	 */
+	LOG_INF("Unable to determine CPU state (%#x), forcing shutdown", sig);
 	ap_power_force_shutdown(AP_POWER_SHUTDOWN_G3);
-	LOG_INF("Unable to determine CPU state, forcing shutdown");
 	return SYS_POWER_STATE_G3;
 }
diff --git a/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_console.c b/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_console.c
index e671e46113..dbceeacc85 100644
--- a/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_console.c
+++ b/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_console.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,20 +11,19 @@ LOG_MODULE_DECLARE(ap_pwrseq, CONFIG_AP_PWRSEQ_LOG_LEVEL);
 
 /* Console commands */
 static int powerinfo_handler(const struct shell *shell, size_t argc,
-							char **argv)
+			     char **argv)
 {
 	enum power_states_ndsx state = pwr_sm_get_state();
 
 	shell_fprintf(shell, SHELL_INFO, "power state %d = %s, in 0x%04x\n",
-		      state, pwr_sm_get_state_name(state),
-		      power_get_signals());
+		      state, pwr_sm_get_state_name(state), power_get_signals());
 	return 0;
 }
 
 SHELL_CMD_REGISTER(powerinfo, NULL, NULL, powerinfo_handler);
 
 static int powerindebug_handler(const struct shell *shell, size_t argc,
-							char **argv)
+				char **argv)
 {
 	int i;
 	char *e;
@@ -42,29 +41,29 @@ static int powerindebug_handler(const struct shell *shell, size_t argc,
 
 	/* Print the mask */
 	current = power_get_signals();
-	shell_fprintf(shell, SHELL_INFO, "power in:   0x%04x\n", current);
-	shell_fprintf(shell, SHELL_INFO, "debug mask: 0x%04x\n",
-						power_get_debug());
+	shell_fprintf(shell, SHELL_INFO, "power in:   0x%05x\n", current);
+	shell_fprintf(shell, SHELL_INFO, "debug mask: 0x%05x\n",
+		      power_get_debug());
 
 	/* Print the decode */
 	shell_fprintf(shell, SHELL_INFO, "bit meanings:\n");
 	for (i = 0; i < POWER_SIGNAL_COUNT; i++) {
 		power_signal_mask_t mask = POWER_SIGNAL_MASK(i);
+		bool valid = (power_signal_get(i) >= 0);
 
-		shell_fprintf(shell, SHELL_INFO, "  0x%04x %d %s\n",
-			mask, (current & mask) ? 1 : 0,
-			power_signal_name(i));
+		shell_fprintf(shell, SHELL_INFO, "  0x%05x %d%s %s\n", mask,
+			      (current & mask) ? 1 : 0, valid ? " " : "!",
+			      power_signal_name(i));
 	}
 
 	return 0;
 };
 
-SHELL_CMD_REGISTER(powerindebug, NULL,
-	"[mask] Get/set power input debug mask", powerindebug_handler);
-
+SHELL_CMD_REGISTER(powerindebug, NULL, "[mask] Get/set power input debug mask",
+		   powerindebug_handler);
 
 static int apshutdown_handler(const struct shell *shell, size_t argc,
-							char **argv)
+			      char **argv)
 {
 	ap_power_force_shutdown(AP_POWER_SHUTDOWN_CONSOLE_CMD);
 	return 0;
@@ -72,8 +71,7 @@ static int apshutdown_handler(const struct shell *shell, size_t argc,
 
 SHELL_CMD_REGISTER(apshutdown, NULL, NULL, apshutdown_handler);
 
-static int apreset_handler(const struct shell *shell, size_t argc,
-							char **argv)
+static int apreset_handler(const struct shell *shell, size_t argc, char **argv)
 {
 	ap_power_reset(AP_POWER_SHUTDOWN_CONSOLE_CMD);
 	return 0;
diff --git a/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_host_command.c b/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_host_command.c
index 7bacbcd8cd..ee6e2cf41e 100644
--- a/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_host_command.c
+++ b/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_host_command.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,14 +12,14 @@ host_command_reboot_ap_on_g3(struct host_cmd_handler_args *args)
 	const struct ec_params_reboot_ap_on_g3_v1 *cmd = args->params;
 
 	/* Store request for processing at g3 */
-	request_exit_hardoff(true);
+	request_start_from_g3();
 
 	switch (args->version) {
 	case 0:
 		break;
 	case 1:
 		/* Store user specified delay to wait in G3 state */
-		set_reboot_ap_at_g3_delay_seconds(cmd->reboot_ap_at_g3_delay);
+		set_start_from_g3_delay_seconds(cmd->reboot_ap_at_g3_delay);
 		break;
 	default:
 		return EC_RES_INVALID_PARAM;
@@ -27,8 +27,66 @@ host_command_reboot_ap_on_g3(struct host_cmd_handler_args *args)
 
 	return EC_RES_SUCCESS;
 }
-DECLARE_HOST_COMMAND(EC_CMD_REBOOT_AP_ON_G3,
-		     host_command_reboot_ap_on_g3,
+DECLARE_HOST_COMMAND(EC_CMD_REBOOT_AP_ON_G3, host_command_reboot_ap_on_g3,
 		     EC_VER_MASK(0) | EC_VER_MASK(1));
 
+#if CONFIG_AP_PWRSEQ_HOST_SLEEP
+/* Track last reported sleep event */
+static enum host_sleep_event host_sleep_state;
+
+static enum ec_status
+host_command_host_sleep_event(struct host_cmd_handler_args *args)
+{
+	const struct ec_params_host_sleep_event_v1 *p = args->params;
+	struct ec_response_host_sleep_event_v1 *r = args->response;
+	struct host_sleep_event_context ctx;
+	enum host_sleep_event state = p->sleep_event;
+
+	host_sleep_state = state;
+	ctx.sleep_transitions = 0;
+	switch (state) {
+	case HOST_SLEEP_EVENT_S0IX_SUSPEND:
+	case HOST_SLEEP_EVENT_S3_SUSPEND:
+	case HOST_SLEEP_EVENT_S3_WAKEABLE_SUSPEND:
+		ctx.sleep_timeout_ms = EC_HOST_SLEEP_TIMEOUT_DEFAULT;
+
+		/* The original version contained only state. */
+		if (args->version >= 1)
+			ctx.sleep_timeout_ms =
+				p->suspend_params.sleep_timeout_ms;
+
+		break;
+
+	default:
+		break;
+	}
+
+	ap_power_chipset_handle_host_sleep_event(host_sleep_state, &ctx);
+	switch (state) {
+	case HOST_SLEEP_EVENT_S0IX_RESUME:
+	case HOST_SLEEP_EVENT_S3_RESUME:
+		if (args->version >= 1) {
+			r->resume_response.sleep_transitions =
+				ctx.sleep_transitions;
+
+			args->response_size = sizeof(*r);
+		}
+
+		break;
+
+	default:
+		break;
+	}
+
+	return EC_RES_SUCCESS;
+}
+DECLARE_HOST_COMMAND(EC_CMD_HOST_SLEEP_EVENT, host_command_host_sleep_event,
+		     EC_VER_MASK(0) | EC_VER_MASK(1));
+
+void power_set_host_sleep_state(enum host_sleep_event state)
+{
+	host_sleep_state = state;
+}
+#endif /* CONFIG_AP_PWRSEQ_HOST_SLEEP */
+
 /* End of host commands */
diff --git a/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_host_sleep.c b/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_host_sleep.c
new file mode 100644
index 0000000000..015cecb502
--- /dev/null
+++ b/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_host_sleep.c
@@ -0,0 +1,179 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <ap_power_host_sleep.h>
+#include <x86_non_dsx_common_pwrseq_sm_handler.h>
+
+static uint16_t sleep_signal_timeout;
+static uint16_t host_sleep_timeout_default = CONFIG_SLEEP_TIMEOUT_MS;
+static uint32_t sleep_signal_transitions;
+static enum sleep_hang_type timeout_hang_type;
+
+static void sleep_transition_timeout(struct k_work *work);
+
+static K_WORK_DELAYABLE_DEFINE(sleep_transition_timeout_data,
+			       sleep_transition_timeout);
+
+/**
+ * Type of sleep hang detected
+ */
+enum sleep_hang_type {
+	SLEEP_HANG_NONE,
+	SLEEP_HANG_S0IX_SUSPEND,
+	SLEEP_HANG_S0IX_RESUME
+};
+
+void power_chipset_handle_sleep_hang(enum sleep_hang_type hang_type)
+{
+	/*
+	 * Wake up the AP so they don't just chill in a non-suspended state and
+	 * burn power. Overload a vaguely related event bit since event bits are
+	 * at a premium. If the system never entered S0ix, then manually set the
+	 * wake mask to pretend it did, so that the hang detect event wakes the
+	 * system.
+	 */
+	if (pwr_sm_get_state() == SYS_POWER_STATE_S0) {
+		host_event_t sleep_wake_mask;
+
+		ap_power_get_lazy_wake_mask(SYS_POWER_STATE_S0ix,
+					    &sleep_wake_mask);
+		lpc_set_host_event_mask(LPC_HOST_EVENT_WAKE, sleep_wake_mask);
+	}
+
+	ccprintf("Warning: Detected sleep hang! Waking host up!");
+	host_set_single_event(EC_HOST_EVENT_HANG_DETECT);
+}
+
+static void sleep_transition_timeout(struct k_work *work)
+{
+	/* Mark the timeout. */
+	sleep_signal_transitions |= EC_HOST_RESUME_SLEEP_TIMEOUT;
+	k_work_cancel_delayable(&sleep_transition_timeout_data);
+
+	if (timeout_hang_type != SLEEP_HANG_NONE) {
+		power_chipset_handle_sleep_hang(timeout_hang_type);
+	}
+}
+
+static void sleep_increment_transition(void)
+{
+	if ((sleep_signal_transitions & EC_HOST_RESUME_SLEEP_TRANSITIONS_MASK) <
+	    EC_HOST_RESUME_SLEEP_TRANSITIONS_MASK)
+		sleep_signal_transitions += 1;
+}
+
+void sleep_suspend_transition(void)
+{
+	sleep_increment_transition();
+	k_work_cancel_delayable(&sleep_transition_timeout_data);
+}
+
+void sleep_resume_transition(void)
+{
+	sleep_increment_transition();
+
+	/*
+	 * Start the timer again to ensure the AP doesn't get itself stuck in
+	 * a state where it's no longer in a sleep state (S0ix/S3), but from
+	 * the Linux perspective is still suspended. Perhaps a bug in the SoC-
+	 * internal periodic housekeeping code might result in a situation
+	 * like this.
+	 */
+	if (sleep_signal_timeout) {
+		timeout_hang_type = SLEEP_HANG_S0IX_RESUME;
+		k_work_schedule(&sleep_transition_timeout_data,
+				K_MSEC(sleep_signal_timeout));
+	}
+}
+
+void sleep_start_suspend(void)
+{
+	uint16_t timeout = host_get_sleep_timeout();
+
+	sleep_signal_transitions = 0;
+
+	/* Use 0xFFFF to disable the timeout */
+	if (timeout == EC_HOST_SLEEP_TIMEOUT_INFINITE) {
+		sleep_signal_timeout = 0;
+		return;
+	}
+
+	/* Use zero internally to indicate host doesn't set timeout value;
+	 * we will use default timeout.
+	 */
+	if (timeout == EC_HOST_SLEEP_TIMEOUT_DEFAULT) {
+		timeout = host_sleep_timeout_default;
+	}
+
+	sleep_signal_timeout = timeout;
+	timeout_hang_type = SLEEP_HANG_S0IX_SUSPEND;
+	k_work_schedule(&sleep_transition_timeout_data, K_MSEC(timeout));
+}
+
+void sleep_complete_resume(void)
+{
+	/*
+	 * Ensure we don't schedule another sleep_transition_timeout
+	 * if the the HOST_SLEEP_EVENT_S0IX_RESUME message arrives before
+	 * the CHIPSET task transitions to the POWER_S0ixS0 state.
+	 */
+	sleep_signal_timeout = 0;
+	k_work_cancel_delayable(&sleep_transition_timeout_data);
+	host_set_sleep_transitions(sleep_signal_transitions);
+}
+
+void sleep_reset_tracking(void)
+{
+	sleep_signal_transitions = 0;
+	sleep_signal_timeout = 0;
+	timeout_hang_type = SLEEP_HANG_NONE;
+}
+
+/*
+ * s0ix event handler.
+ */
+static void ap_power_sleep_event_handler(struct ap_power_ev_callback *cb,
+					 struct ap_power_ev_data data)
+{
+	switch (data.event) {
+	case AP_POWER_S0IX_SUSPEND_START:
+		sleep_start_suspend();
+		break;
+	case AP_POWER_S0IX_SUSPEND:
+		sleep_suspend_transition();
+		break;
+	case AP_POWER_S0IX_RESUME:
+		sleep_resume_transition();
+		break;
+	case AP_POWER_S0IX_RESUME_COMPLETE:
+		sleep_complete_resume();
+		break;
+	case AP_POWER_S0IX_RESET_TRACKING:
+		sleep_reset_tracking();
+		break;
+	default:
+		break;
+	}
+}
+
+/*
+ * Registers callback for s0ix events.
+ */
+static int ap_power_sleep_s0ix_event(const struct device *unused)
+{
+	static struct ap_power_ev_callback cb;
+
+	/*
+	 * Register for all events.
+	 */
+	ap_power_ev_init_callback(
+		&cb, ap_power_sleep_event_handler,
+		AP_POWER_S0IX_SUSPEND_START | AP_POWER_S0IX_SUSPEND |
+			AP_POWER_S0IX_RESUME | AP_POWER_S0IX_RESUME_COMPLETE |
+			AP_POWER_S0IX_RESET_TRACKING);
+	ap_power_ev_add_callback(&cb);
+	return 0;
+}
+SYS_INIT(ap_power_sleep_s0ix_event, APPLICATION, 1);
diff --git a/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c b/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c
index 2f38c36684..48cab7f6e7 100644
--- a/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c
+++ b/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c
@@ -1,25 +1,42 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include <atomic.h>
 #include <zephyr/init.h>
 
 #include <x86_non_dsx_common_pwrseq_sm_handler.h>
 
-static K_KERNEL_STACK_DEFINE(pwrseq_thread_stack,
-			CONFIG_AP_PWRSEQ_STACK_SIZE);
+static K_KERNEL_STACK_DEFINE(pwrseq_thread_stack, CONFIG_AP_PWRSEQ_STACK_SIZE);
 static struct k_thread pwrseq_thread_data;
-static struct pwrseq_context pwrseq_ctx;
+static struct pwrseq_context pwrseq_ctx = {
+	.power_state = SYS_POWER_STATE_UNINIT,
+};
+static struct k_sem pwrseq_sem;
+
+static void s5_inactive_timer_handler(struct k_timer *timer);
 /* S5 inactive timer*/
-K_TIMER_DEFINE(s5_inactive_timer, NULL, NULL);
+K_TIMER_DEFINE(s5_inactive_timer, s5_inactive_timer_handler, NULL);
+/*
+ * Flags, may be set/cleared from other threads.
+ */
+enum {
+	S5_INACTIVE_TIMER_RUNNING,
+	START_FROM_G3,
+	FLAGS_MAX,
+};
+static ATOMIC_DEFINE(flags, FLAGS_MAX);
+/* Delay in ms when starting from G3 */
+static uint32_t start_from_g3_delay_ms;
 
 LOG_MODULE_REGISTER(ap_pwrseq, CONFIG_AP_PWRSEQ_LOG_LEVEL);
 
 /**
  * @brief power_state names for debug
  */
-static const char * const pwrsm_dbg[] = {
+static const char *const pwrsm_dbg[] = {
+	[SYS_POWER_STATE_UNINIT] = "Unknown",
 	[SYS_POWER_STATE_G3] = "G3",
 	[SYS_POWER_STATE_S5] = "S5",
 	[SYS_POWER_STATE_S4] = "S4",
@@ -48,17 +65,17 @@ static const char * const pwrsm_dbg[] = {
  */
 static inline bool signals_valid(power_signal_mask_t signals)
 {
-#if defined(CONFIG_PLATFORM_EC_ESPI_VW_SLP_S3)
+#if defined(CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S3)
 	if ((signals & POWER_SIGNAL_MASK(PWR_SLP_S3)) &&
 	    power_signal_get(PWR_SLP_S3) < 0)
 		return false;
 #endif
-#if defined(CONFIG_PLATFORM_EC_ESPI_VW_SLP_S4)
+#if defined(CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S4)
 	if ((signals & POWER_SIGNAL_MASK(PWR_SLP_S4)) &&
 	    power_signal_get(PWR_SLP_S4) < 0)
 		return false;
 #endif
-#if defined(CONFIG_PLATFORM_EC_ESPI_VW_SLP_S5)
+#if defined(CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S5)
 	if ((signals & POWER_SIGNAL_MASK(PWR_SLP_S5)) &&
 	    power_signal_get(PWR_SLP_S5) < 0)
 		return false;
@@ -81,7 +98,7 @@ enum power_states_ndsx pwr_sm_get_state(void)
 	return pwrseq_ctx.power_state;
 }
 
-const char * const pwr_sm_get_state_name(enum power_states_ndsx state)
+const char *const pwr_sm_get_state_name(enum power_states_ndsx state)
 {
 	return pwrsm_dbg[state];
 }
@@ -95,14 +112,34 @@ void pwr_sm_set_state(enum power_states_ndsx new_state)
 	pwrseq_ctx.power_state = new_state;
 }
 
-void request_exit_hardoff(bool should_exit)
+void ap_pwrseq_wake(void)
 {
-	pwrseq_ctx.want_g3_exit = should_exit;
+	k_sem_give(&pwrseq_sem);
 }
 
-static bool chipset_is_exit_hardoff(void)
+/*
+ * Set a flag to enable starting the AP once it is in G3.
+ * This is called from ap_power_exit_hardoff() which checks
+ * to ensure that the AP is in S5 or G3 state before calling
+ * this function.
+ * It can also be called via a hostcmd, which allows the flag
+ * to be set in any AP state.
+ */
+void request_start_from_g3(void)
 {
-	return pwrseq_ctx.want_g3_exit;
+	LOG_INF("Request start from G3");
+	atomic_set_bit(flags, START_FROM_G3);
+	/*
+	 * If in S5, restart the timer to give the CPU more time
+	 * to respond to a power button press (which is presumably
+	 * why we are being called). This avoids having the S5
+	 * inactivity timer expiring before the AP can process
+	 * the power button press and start up.
+	 */
+	if (pwr_sm_get_state() == SYS_POWER_STATE_S5) {
+		atomic_clear_bit(flags, S5_INACTIVE_TIMER_RUNNING);
+	}
+	ap_pwrseq_wake();
 }
 
 void ap_power_force_shutdown(enum ap_power_shutdown_reason reason)
@@ -110,6 +147,11 @@ void ap_power_force_shutdown(enum ap_power_shutdown_reason reason)
 	board_ap_power_force_shutdown();
 }
 
+static void s5_inactive_timer_handler(struct k_timer *timer)
+{
+	ap_pwrseq_wake();
+}
+
 static void shutdown_and_notify(enum ap_power_shutdown_reason reason)
 {
 	ap_power_force_shutdown(reason);
@@ -117,9 +159,9 @@ static void shutdown_and_notify(enum ap_power_shutdown_reason reason)
 	ap_power_ev_send_callbacks(AP_POWER_SHUTDOWN_COMPLETE);
 }
 
-void set_reboot_ap_at_g3_delay_seconds(uint32_t d_time)
+void set_start_from_g3_delay_seconds(uint32_t d_time)
 {
-	pwrseq_ctx.reboot_ap_at_g3_delay_ms = d_time * MSEC;
+	start_from_g3_delay_ms = d_time * MSEC;
 }
 
 void apshutdown(void)
@@ -190,15 +232,16 @@ static int common_pwr_sm_run(int state)
 {
 	switch (state) {
 	case SYS_POWER_STATE_G3:
-		if (chipset_is_exit_hardoff()) {
-			request_exit_hardoff(false);
-			/*
-			 * G3->S0 transition should happen only after the
-			 * user specified delay. Hence, wait until the
-			 * user specified delay times out.
-			 */
-			k_msleep(pwrseq_ctx.reboot_ap_at_g3_delay_ms);
-			pwrseq_ctx.reboot_ap_at_g3_delay_ms = 0;
+		/*
+		 * If the START_FROM_G3 flag is set, begin starting
+		 * the AP. There may be a delay set, so only start
+		 * after that delay.
+		 */
+		if (atomic_test_and_clear_bit(flags, START_FROM_G3)) {
+			LOG_INF("Starting from G3, delay %d ms",
+				start_from_g3_delay_ms);
+			k_msleep(start_from_g3_delay_ms);
+			start_from_g3_delay_ms = 0;
 
 			return SYS_POWER_STATE_G3S5;
 		}
@@ -207,7 +250,7 @@ static int common_pwr_sm_run(int state)
 
 	case SYS_POWER_STATE_G3S5:
 		if ((power_get_signals() & PWRSEQ_G3S5_UP_SIGNAL) ==
-				PWRSEQ_G3S5_UP_VALUE)
+		    PWRSEQ_G3S5_UP_VALUE)
 			return SYS_POWER_STATE_S5;
 		else
 			return SYS_POWER_STATE_S5G3;
@@ -215,29 +258,56 @@ static int common_pwr_sm_run(int state)
 	case SYS_POWER_STATE_S5:
 		/* In S5 make sure no more signal lost */
 		/* If A-rails are stable then move to higher state */
-		if (board_ap_power_check_power_rails_enabled()
-					&& rsmrst_power_is_good()) {
+		if (board_ap_power_check_power_rails_enabled() &&
+		    rsmrst_power_is_good()) {
 			/* rsmrst is intact */
 			rsmrst_pass_thru_handler();
 			if (signals_valid_and_off(IN_PCH_SLP_S5)) {
 				k_timer_stop(&s5_inactive_timer);
+				/* Clear the timer running flag */
+				atomic_clear_bit(flags,
+						 S5_INACTIVE_TIMER_RUNNING);
+				/* Clear any request to exit hard-off */
+				atomic_clear_bit(flags, START_FROM_G3);
+				LOG_INF("Clearing request to exit G3");
 				return SYS_POWER_STATE_S5S4;
 			}
 		}
-		/* S5 inactivity timeout, go to S5G3 */
+		/*
+		 * S5 state has an inactivity timer, so moving
+		 * to S5G3 (where the power rails are turned off) is
+		 * delayed for some time, usually ~10 seconds or so.
+		 * The purpose of this delay is:
+		 *  - to handle AP initiated cold boot, where the AP
+		 *    will go to S5 for a short time and then restart.
+		 *  - give time for the power button to be pressed,
+		 *    which may set the START_FROM_G3 flag.
+		 */
 		if (AP_PWRSEQ_DT_VALUE(s5_inactivity_timeout) == 0)
 			return SYS_POWER_STATE_S5G3;
 		else if (AP_PWRSEQ_DT_VALUE(s5_inactivity_timeout) > 0) {
-			if (k_timer_status_get(&s5_inactive_timer) > 0)
+			/*
+			 * Test and set timer running flag.
+			 * If it was 0, then the timer wasn't running
+			 * and it is started (and the flag is set),
+			 * otherwise it is already set, so no change.
+			 */
+			if (!atomic_test_and_set_bit(
+				    flags, S5_INACTIVE_TIMER_RUNNING)) {
+				/*
+				 * Timer is not started, or needs
+				 * restarting.
+				 */
+				k_timer_start(&s5_inactive_timer,
+					      K_SECONDS(AP_PWRSEQ_DT_VALUE(
+						      s5_inactivity_timeout)),
+					      K_NO_WAIT);
+			} else if (k_timer_status_get(&s5_inactive_timer) > 0) {
 				/* Timer is expired */
+				atomic_clear_bit(flags,
+						 S5_INACTIVE_TIMER_RUNNING);
 				return SYS_POWER_STATE_S5G3;
-			else if (k_timer_remaining_get(
-						&s5_inactive_timer) == 0)
-				/* Timer is not started or stopped */
-				k_timer_start(&s5_inactive_timer,
-					K_SECONDS(AP_PWRSEQ_DT_VALUE(
-						s5_inactivity_timeout)),
-					K_NO_WAIT);
+			}
 		}
 		break;
 
@@ -318,7 +388,7 @@ static int common_pwr_sm_run(int state)
 	case SYS_POWER_STATE_S0ix:
 		/* System in S0 only if SLP_S0 and SLP_S3 are de-asserted */
 		if (power_signals_off(IN_PCH_SLP_S0) &&
-			signals_valid_and_off(IN_PCH_SLP_S3)) {
+		    signals_valid_and_off(IN_PCH_SLP_S3)) {
 			/* TODO: Make sure ap reset handling is done
 			 * before leaving S0ix.
 			 */
@@ -334,6 +404,7 @@ static int common_pwr_sm_run(int state)
 		 * HC already set sleep suspend state.
 		 */
 		ap_power_sleep_notify_transition(AP_POWER_SLEEP_SUSPEND);
+		ap_power_ev_send_callbacks(AP_POWER_S0IX_SUSPEND);
 
 		/*
 		 * Enable idle task deep sleep. Allow the low power idle task
@@ -354,9 +425,11 @@ static int common_pwr_sm_run(int state)
 		 */
 		disable_sleep(SLEEP_MASK_AP_RUN);
 
+		ap_power_ev_send_callbacks(AP_POWER_S0IX_RESUME
 #if CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK
-		ap_power_ev_send_callbacks(AP_POWER_RESUME_INIT);
+					   | AP_POWER_RESUME_INIT
 #endif
+		);
 
 		return SYS_POWER_STATE_S0;
 
@@ -370,19 +443,19 @@ static int common_pwr_sm_run(int state)
 			return SYS_POWER_STATE_S0S3;
 
 #if CONFIG_AP_PWRSEQ_S0IX
-		/*
-		 * SLP_S0 may assert in system idle scenario without a kernel
-		 * freeze call. This may cause interrupt storm since there is
-		 * no freeze/unfreeze of threads/process in the idle scenario.
-		 * Ignore the SLP_S0 assertions in idle scenario by checking
-		 * the host sleep state.
-		 */
+			/*
+			 * SLP_S0 may assert in system idle scenario without a
+			 * kernel freeze call. This may cause interrupt storm
+			 * since there is no freeze/unfreeze of threads/process
+			 * in the idle scenario. Ignore the SLP_S0 assertions in
+			 * idle scenario by checking the host sleep state.
+			 */
 		} else if (ap_power_sleep_get_notify() ==
-					AP_POWER_SLEEP_SUSPEND &&
-					power_signals_on(IN_PCH_SLP_S0)) {
+				   AP_POWER_SLEEP_SUSPEND &&
+			   power_signals_on(IN_PCH_SLP_S0)) {
 			return SYS_POWER_STATE_S0S0ix;
 		} else if (ap_power_sleep_get_notify() ==
-					AP_POWER_SLEEP_RESUME) {
+			   AP_POWER_SLEEP_RESUME) {
 			ap_power_sleep_notify_transition(AP_POWER_SLEEP_RESUME);
 #endif /* CONFIG_AP_PWRSEQ_S0IX */
 		}
@@ -464,12 +537,16 @@ static void pwr_seq_set_initial_state(void)
 
 static void pwrseq_loop_thread(void *p1, void *p2, void *p3)
 {
-	int32_t t_wait_ms = 10;
 	enum power_states_ndsx curr_state, new_state;
 	power_signal_mask_t this_in_signals;
 	power_signal_mask_t last_in_signals = 0;
 	enum power_states_ndsx last_state = -1;
 
+	/*
+	 * Let clients know that the AP power state is now
+	 * initialized and ready.
+	 */
+	ap_power_ev_send_callbacks(AP_POWER_INITIALIZED);
 	while (1) {
 		curr_state = pwr_sm_get_state();
 
@@ -482,9 +559,8 @@ static void pwrseq_loop_thread(void *p1, void *p2, void *p3)
 		this_in_signals = power_get_signals();
 
 		if (this_in_signals != last_in_signals ||
-				curr_state != last_state) {
-			LOG_INF("power state %d = %s, in 0x%04x",
-				curr_state,
+		    curr_state != last_state) {
+			LOG_INF("power state %d = %s, in 0x%04x", curr_state,
 				pwr_sm_get_state_name(curr_state),
 				this_in_signals);
 			last_in_signals = this_in_signals;
@@ -506,22 +582,24 @@ static void pwrseq_loop_thread(void *p1, void *p2, void *p3)
 		if (curr_state != new_state) {
 			pwr_sm_set_state(new_state);
 			ap_power_set_active_wake_mask();
+		} else {
+			/*
+			 * No state transition, we can go to sleep and wait
+			 * for any event to wake us up.
+			 */
+			k_sem_take(&pwrseq_sem, K_FOREVER);
 		}
-
-		k_msleep(t_wait_ms);
 	}
 }
 
 static inline void create_pwrseq_thread(void)
 {
-	k_thread_create(&pwrseq_thread_data,
-			pwrseq_thread_stack,
+	k_thread_create(&pwrseq_thread_data, pwrseq_thread_stack,
 			K_KERNEL_STACK_SIZEOF(pwrseq_thread_stack),
-			(k_thread_entry_t)pwrseq_loop_thread,
-			NULL, NULL, NULL,
+			(k_thread_entry_t)pwrseq_loop_thread, NULL, NULL, NULL,
 			CONFIG_AP_PWRSEQ_THREAD_PRIORITY, 0,
-			IS_ENABLED(CONFIG_AP_PWRSEQ_AUTOSTART) ? K_NO_WAIT
-							       : K_FOREVER);
+			IS_ENABLED(CONFIG_AP_PWRSEQ_AUTOSTART) ? K_NO_WAIT :
+								 K_FOREVER);
 
 	k_thread_name_set(&pwrseq_thread_data, "pwrseq_task");
 }
@@ -535,7 +613,7 @@ void ap_pwrseq_task_start(void)
 
 static void init_pwr_seq_state(void)
 {
-	request_exit_hardoff(false);
+	atomic_clear_bit(flags, START_FROM_G3);
 	/*
 	 * The state of the CPU needs to be determined now
 	 * so that init routines can check the state of
@@ -549,6 +627,7 @@ static int pwrseq_init(const struct device *dev)
 {
 	LOG_INF("Pwrseq Init");
 
+	k_sem_init(&pwrseq_sem, 0, 1);
 	/* Initialize signal handlers */
 	power_signal_init();
 	LOG_DBG("Init pwr seq state");
@@ -559,7 +638,7 @@ static int pwrseq_init(const struct device *dev)
 }
 
 /*
- * The initialisation must occur after system I/O initialisation that
+ * The initialization must occur after system I/O initialization that
  * the signals depend upon, such as GPIO, ADC etc.
  */
 SYS_INIT(pwrseq_init, APPLICATION, CONFIG_APPLICATION_INIT_PRIORITY);
diff --git a/zephyr/subsys/ap_pwrseq/x86_non_dsx_mtl_pwrseq_sm.c b/zephyr/subsys/ap_pwrseq/x86_non_dsx_mtl_pwrseq_sm.c
index 5183824117..80fa06e454 100644
--- a/zephyr/subsys/ap_pwrseq/x86_non_dsx_mtl_pwrseq_sm.c
+++ b/zephyr/subsys/ap_pwrseq/x86_non_dsx_mtl_pwrseq_sm.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -33,8 +33,8 @@ static void generate_pwrok_handler(void)
 
 	power_signal_set(PWR_EC_PCH_SYS_PWROK, all_sys_pwrgd_in);
 	/* PCH_PWROK is set to combined result of ALL_SYS_PWRGD and SLP_S3 */
-	power_signal_set(PWR_PCH_PWROK, all_sys_pwrgd_in &&
-					!power_signal_get(PWR_SLP_S3));
+	power_signal_set(PWR_PCH_PWROK,
+			 all_sys_pwrgd_in && !power_signal_get(PWR_SLP_S3));
 }
 
 /* Chipset specific power state machine handler */
diff --git a/zephyr/test/.pylintrc b/zephyr/test/.pylintrc
index 9ca0b5f8c9..f4609e3781 100644
--- a/zephyr/test/.pylintrc
+++ b/zephyr/test/.pylintrc
@@ -1,15 +1,3 @@
-[MASTER]
-init-hook='import sys; sys.path.append("/usr/lib64/python3.6/site-packages")'
-
-[MESSAGES CONTROL]
-
-disable=bad-continuation,bad-whitespace,format,fixme
-
-[format]
-
-max-line-length=88
-string-quote=double
-
 [BASIC]
 additional-builtins=
     here,
@@ -19,3 +7,21 @@ additional-builtins=
     register_npcx_project,
     register_raw_project,
 good-names=BUILD
+
+# cros lint doesn't inherit the pylintrc from the parent dir.
+# These settings are copied from platform/ec/pylintrc
+[MESSAGES CONTROL]
+
+disable=
+    bad-continuation,
+    bad-whitespace,
+    # These have nothing to do with black, they are just annoying
+    fixme,
+    too-many-arguments,
+    too-many-statements,
+    too-many-branches,
+    too-many-locals
+
+[format]
+
+string-quote=double
diff --git a/zephyr/test/accel_cal/BUILD.py b/zephyr/test/accel_cal/BUILD.py
deleted file mode 100644
index 8c743bf48b..0000000000
--- a/zephyr/test/accel_cal/BUILD.py
+++ /dev/null
@@ -1,7 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-"""Register zmake project for accel_cal test."""
-
-register_host_test("accel_cal")
diff --git a/zephyr/test/accel_cal/CMakeLists.txt b/zephyr/test/accel_cal/CMakeLists.txt
index 14fd70e01a..07c9ed8599 100644
--- a/zephyr/test/accel_cal/CMakeLists.txt
+++ b/zephyr/test/accel_cal/CMakeLists.txt
@@ -1,9 +1,9 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 cmake_minimum_required(VERSION 3.13.1)
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
 project(accel_cal)
 
 # Ensure that we get the definitions from test_config.h
diff --git a/zephyr/test/accel_cal/boards/native_posix.overlay b/zephyr/test/accel_cal/boards/native_posix.overlay
new file mode 100644
index 0000000000..c4d4413ad7
--- /dev/null
+++ b/zephyr/test/accel_cal/boards/native_posix.overlay
@@ -0,0 +1,6 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <board-overlays/native_posix.dts>
diff --git a/zephyr/test/accel_cal/prj.conf b/zephyr/test/accel_cal/prj.conf
index 5efe3ec6b7..20e6ee59bf 100644
--- a/zephyr/test/accel_cal/prj.conf
+++ b/zephyr/test/accel_cal/prj.conf
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/test/accel_cal/shimmed_test_tasks.h b/zephyr/test/accel_cal/shimmed_test_tasks.h
index ff221a5ba3..12f4c8dc22 100644
--- a/zephyr/test/accel_cal/shimmed_test_tasks.h
+++ b/zephyr/test/accel_cal/shimmed_test_tasks.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/test/accel_cal/testcase.yaml b/zephyr/test/accel_cal/testcase.yaml
new file mode 100644
index 0000000000..21e63e4ed4
--- /dev/null
+++ b/zephyr/test/accel_cal/testcase.yaml
@@ -0,0 +1,5 @@
+common:
+  platform_allow: native_posix
+tests:
+  accel_cal.default: {}
+
diff --git a/zephyr/test/ap_power/CMakeLists.txt b/zephyr/test/ap_power/CMakeLists.txt
index 523db95ede..7b44013961 100644
--- a/zephyr/test/ap_power/CMakeLists.txt
+++ b/zephyr/test/ap_power/CMakeLists.txt
@@ -1,9 +1,9 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 cmake_minimum_required(VERSION 3.13.1)
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
 project(ap_power)
 
 # Include the local test directory for shimmed_test_tasks.h
diff --git a/zephyr/test/ap_power/Kconfig b/zephyr/test/ap_power/Kconfig
index 6faf452ac6..ac7b264855 100644
--- a/zephyr/test/ap_power/Kconfig
+++ b/zephyr/test/ap_power/Kconfig
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/test/ap_power/overlay.dts b/zephyr/test/ap_power/boards/native_posix.overlay
index d961788c7a..c6cd8c3790 100644
--- a/zephyr/test/ap_power/overlay.dts
+++ b/zephyr/test/ap_power/boards/native_posix.overlay
@@ -1,8 +1,9 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include <board-overlays/native_posix.dts>
 #include <cros/binman.dtsi>
 #include <dt-bindings/gpio_defines.h>
 #include <freq.h>
@@ -187,7 +188,6 @@
 		status = "okay";
 		compatible = "zephyr,espi-emul-espi-host";
 		reg = <0x0>;
-		label = "ESPI_HOST";
 	};
 };
 
diff --git a/zephyr/test/ap_power/include/test_state.h b/zephyr/test/ap_power/include/test_state.h
index c993fe8ff0..cb91f2b7c7 100644
--- a/zephyr/test/ap_power/include/test_state.h
+++ b/zephyr/test/ap_power/include/test_state.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/test/ap_power/prj.conf b/zephyr/test/ap_power/prj.conf
index 86c3f5082d..4dd31085bd 100644
--- a/zephyr/test/ap_power/prj.conf
+++ b/zephyr/test/ap_power/prj.conf
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -43,8 +43,8 @@ CONFIG_HEAP_MEM_POOL_SIZE=1024
 CONFIG_AP_PWRSEQ=y
 CONFIG_X86_NON_DSX_PWRSEQ_ADL=y
 CONFIG_AP_X86_INTEL_ADL=y
-CONFIG_PLATFORM_EC_ESPI_VW_SLP_S4=y
-CONFIG_PLATFORM_EC_ESPI_VW_SLP_S5=y
+CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S4=y
+CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S5=y
 CONFIG_AP_PWRSEQ_STACK_SIZE=1024
 
 CONFIG_ESPI=y
@@ -54,6 +54,7 @@ CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION=y
 CONFIG_ESPI_PERIPHERAL_CUSTOM_OPCODE=y
 CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD=y
 CONFIG_PLATFORM_EC_HOSTCMD=y
+CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK=y
 
 # These items are not required.
 CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
diff --git a/zephyr/test/ap_power/src/board.c b/zephyr/test/ap_power/src/board.c
index 96b30d21d3..26c9448396 100644
--- a/zephyr/test/ap_power/src/board.c
+++ b/zephyr/test/ap_power/src/board.c
@@ -1,10 +1,10 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <zephyr/zephyr.h>
-#include <ztest.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
 
 #include <ap_power_override_functions.h>
 #include <ap_power/ap_power_interface.h>
diff --git a/zephyr/test/ap_power/src/events.c b/zephyr/test/ap_power/src/events.c
index de695e945f..ae7d2b870f 100644
--- a/zephyr/test/ap_power/src/events.c
+++ b/zephyr/test/ap_power/src/events.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -10,9 +10,11 @@
 
 #include <zephyr/device.h>
 
+#include <zephyr/drivers/espi.h>
+#include <zephyr/drivers/espi_emul.h>
 #include <zephyr/logging/log.h>
-#include <zephyr/zephyr.h>
-#include <ztest.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
 
 #include "ap_power/ap_power.h"
 #include "ap_power/ap_power_events.h"
@@ -66,7 +68,7 @@ ZTEST(events, test_registration)
 	ap_power_ev_remove_callback(&cb.cb);
 	ap_power_ev_send_callbacks(AP_POWER_RESET);
 	zassert_equal(1, cb.count, "Callback called");
-	cb.count = 0;	/* Reset to make it clear */
+	cb.count = 0; /* Reset to make it clear */
 	cb.event = 0;
 	/* Add it twice */
 	ap_power_ev_add_callback(&cb.cb);
@@ -80,6 +82,36 @@ ZTEST(events, test_registration)
 }
 
 /**
+ * @brief TestPurpose: Verify reset callback from ESPI
+ *
+ * @details
+ * Validate that the reset callback is sent with ESPI PLTRST#
+ *
+ * Expected Results
+ *  - The AP_POWER_RESET event is sent
+ */
+ZTEST(events, test_pltrst)
+{
+	static struct events cb;
+	const struct device *espi =
+		DEVICE_DT_GET_ANY(zephyr_espi_emul_controller);
+
+	zassert_not_null(espi, "Cannot get ESPI device");
+
+	ap_power_ev_init_callback(&cb.cb, ev_handler, AP_POWER_RESET);
+	ap_power_ev_add_callback(&cb.cb);
+
+	emul_espi_host_send_vw(espi, ESPI_VWIRE_SIGNAL_PLTRST, 0);
+	/*
+	 * Since the event is being sent via a deferred function,
+	 * wait for the deferral time.
+	 */
+	k_usleep(2 * 1000);
+	zassert_equal(1, cb.count, "Callback not called");
+	zassert_equal(AP_POWER_RESET, cb.event, "Wrong event");
+}
+
+/**
  * @brief TestPurpose: Check event mask changes
  *
  * @details
@@ -145,9 +177,9 @@ ZTEST(events, test_hooks)
 	zassert_equal(0, count_hook_shutdown, "shutdown hook called");
 	zassert_equal(1, count_hook_startup, "startup hook not called");
 	zassert_equal(0, count_hook_shutdown,
-		"reset event, shutdown hook called");
+		      "reset event, shutdown hook called");
 	zassert_equal(1, count_hook_startup,
-		"reset event, startup hook called");
+		      "reset event, startup hook called");
 	ap_power_ev_send_callbacks(AP_POWER_SHUTDOWN);
 	zassert_equal(1, count_hook_shutdown, "shutdown hook not called");
 	zassert_equal(1, count_hook_startup, "startup hook called");
@@ -156,5 +188,4 @@ ZTEST(events, test_hooks)
 /**
  * @brief Test Suite: Verifies AP power notification functionality.
  */
-ZTEST_SUITE(events, ap_power_predicate_post_main,
-	    NULL, NULL, NULL, NULL);
+ZTEST_SUITE(events, ap_power_predicate_post_main, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/ap_power/src/main.c b/zephyr/test/ap_power/src/main.c
index 761fcfd997..d653b51164 100644
--- a/zephyr/test/ap_power/src/main.c
+++ b/zephyr/test/ap_power/src/main.c
@@ -1,10 +1,10 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <zephyr/zephyr.h>
-#include <ztest.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
 #include "ec_app_main.h"
 #include "test_state.h"
 
diff --git a/zephyr/test/ap_power/src/signals.c b/zephyr/test/ap_power/src/signals.c
index c2ccffb8c9..e8bc6e426c 100644
--- a/zephyr/test/ap_power/src/signals.c
+++ b/zephyr/test/ap_power/src/signals.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,12 +14,13 @@
 #include <zephyr/drivers/espi_emul.h>
 #include <zephyr/drivers/gpio/gpio_emul.h>
 #include <zephyr/logging/log.h>
-#include <zephyr/zephyr.h>
-#include <ztest.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
 
 #include "power_signals.h"
 
 #include "ec_tasks.h"
+#include "emul/emul_stub_device.h"
 #include "gpio.h"
 #include "gpio/gpio.h"
 #include "gpio/gpio_int.h"
@@ -37,19 +38,13 @@ static struct {
 	enum power_signal signal;
 	int pin;
 } signal_to_pin_table[] = {
-{	PWR_EN_PP5000_A, 10},
-{	PWR_EN_PP3300_A, 11},
-{	PWR_RSMRST, 12},
-{	PWR_EC_PCH_RSMRST, 13},
-{	PWR_SLP_S0, 14},
-{	PWR_SLP_S3, 15},
-{	PWR_SLP_SUS, 16},
-{	PWR_EC_SOC_DSW_PWROK, 17},
-{	PWR_VCCST_PWRGD, 18},
-{	PWR_IMVP9_VRRDY, 19},
-{	PWR_PCH_PWROK, 20},
-{	PWR_EC_PCH_SYS_PWROK, 21},
-{	PWR_SYS_RST, 22},
+	{ PWR_EN_PP5000_A, 10 }, { PWR_EN_PP3300_A, 11 },
+	{ PWR_RSMRST, 12 },	 { PWR_EC_PCH_RSMRST, 13 },
+	{ PWR_SLP_S0, 14 },	 { PWR_SLP_S3, 15 },
+	{ PWR_SLP_SUS, 16 },	 { PWR_EC_SOC_DSW_PWROK, 17 },
+	{ PWR_VCCST_PWRGD, 18 }, { PWR_IMVP9_VRRDY, 19 },
+	{ PWR_PCH_PWROK, 20 },	 { PWR_EC_PCH_SYS_PWROK, 21 },
+	{ PWR_SYS_RST, 22 },
 };
 
 /*
@@ -106,9 +101,9 @@ ZTEST(signals, test_validate_request)
 	zassert_equal(-EINVAL, power_signal_enable(PWR_IMVP9_VRRDY),
 		      "enable interrupt on input pin without interrupt config");
 	/* Can't disable interrupt on input with no interrupt flags */
-	zassert_equal(-EINVAL,
-		      power_signal_disable(PWR_IMVP9_VRRDY),
-		      "disable interrupt on input pin without interrupt config");
+	zassert_equal(
+		-EINVAL, power_signal_disable(PWR_IMVP9_VRRDY),
+		"disable interrupt on input pin without interrupt config");
 	/* Invalid signal - should be rejectde */
 	zassert_equal(-EINVAL, power_signal_get(-1),
 		      "power_signal_get with -1 signal should fail");
@@ -135,7 +130,7 @@ ZTEST(signals, test_board_signals)
 	 * Check that the board level signals get correctly invoked.
 	 */
 	zassert_ok(power_signal_set(PWR_ALL_SYS_PWRGD, 1),
-		      "power_signal_set on board signal failed");
+		   "power_signal_set on board signal failed");
 	zassert_equal(1, power_signal_get(PWR_ALL_SYS_PWRGD),
 		      "power_signal_get on board signal should return 1");
 }
@@ -153,12 +148,13 @@ ZTEST(signals, test_signal_name)
 {
 	for (int signal = 0; signal < POWER_SIGNAL_COUNT; signal++) {
 		zassert_not_null(power_signal_name(signal),
-			"Signal name for %d should be not null", signal);
+				 "Signal name for %d should be not null",
+				 signal);
 	}
 	zassert_is_null(power_signal_name(-1),
-		"Out of bounds signal name should be null");
+			"Out of bounds signal name should be null");
 	zassert_is_null(power_signal_name(POWER_SIGNAL_COUNT),
-		"Out of bounds signal name should be null");
+			"Out of bounds signal name should be null");
 }
 
 /**
@@ -180,18 +176,19 @@ ZTEST(signals, test_init_outputs)
 	static const enum power_signal active_high[] = {
 		PWR_EN_PP5000_A, PWR_EN_PP3300_A, PWR_EC_PCH_RSMRST,
 		PWR_EC_SOC_DSW_PWROK, PWR_PCH_PWROK
-		};
+	};
 	static const enum power_signal active_low[] = { PWR_SYS_RST };
 
 	for (int i = 0; i < ARRAY_SIZE(active_high); i++) {
 		zassert_equal(0, emul_get(active_high[i]),
-			"Signal %d (%s) init to de-asserted state failed",
-			active_high[i], power_signal_name(active_high[i]));
+			      "Signal %d (%s) init to de-asserted state failed",
+			      active_high[i],
+			      power_signal_name(active_high[i]));
 	}
 	for (int i = 0; i < ARRAY_SIZE(active_low); i++) {
 		zassert_equal(1, emul_get(active_low[i]),
-			"Signal %d (%s) init to de-asserted state failed",
-			active_low[i], power_signal_name(active_low[i]));
+			      "Signal %d (%s) init to de-asserted state failed",
+			      active_low[i], power_signal_name(active_low[i]));
 	}
 }
 
@@ -212,14 +209,15 @@ ZTEST(signals, test_gpio_input)
 		      "power_signal_get of PWR_RSMRST should be 1");
 	emul_set(PWR_RSMRST, 0);
 	zassert_equal(0, power_signal_get(PWR_RSMRST),
-	      "power_signal_get of PWR_RSMRST should be 0");
+		      "power_signal_get of PWR_RSMRST should be 0");
 	/* ACTIVE_LOW input */
 	emul_set(PWR_SLP_S0, 0);
-	zassert_equal(1, power_signal_get(PWR_SLP_S0),
-	      "power_signal_get of active-low signal PWR_SLP_S0 should be 1");
+	zassert_equal(
+		1, power_signal_get(PWR_SLP_S0),
+		"power_signal_get of active-low signal PWR_SLP_S0 should be 1");
 	emul_set(PWR_SLP_S0, 1);
 	zassert_equal(0, power_signal_get(PWR_SLP_S0),
-	      "power_signal_get of active-low PWR_SLP_S0 should be 0");
+		      "power_signal_get of active-low PWR_SLP_S0 should be 0");
 }
 
 /**
@@ -235,17 +233,17 @@ ZTEST(signals, test_gpio_output)
 {
 	power_signal_set(PWR_PCH_PWROK, 1);
 	zassert_equal(1, emul_get(PWR_PCH_PWROK),
-		"power_signal_set of PWR_PCH_PWROK should be 1");
+		      "power_signal_set of PWR_PCH_PWROK should be 1");
 	power_signal_set(PWR_PCH_PWROK, 0);
 	zassert_equal(0, emul_get(PWR_PCH_PWROK),
-		"power_signal_set of PWR_PCH_PWROK should be 0");
+		      "power_signal_set of PWR_PCH_PWROK should be 0");
 	/* ACTIVE_LOW output */
 	power_signal_set(PWR_SYS_RST, 0);
 	zassert_equal(1, emul_get(PWR_SYS_RST),
-		"power_signal_set of PWR_SYS_RST should be 1");
+		      "power_signal_set of PWR_SYS_RST should be 1");
 	power_signal_set(PWR_SYS_RST, 1);
 	zassert_equal(0, emul_get(PWR_SYS_RST),
-		"power_signal_set of PWR_SYS_RST should be 0");
+		      "power_signal_set of PWR_SYS_RST should be 0");
 }
 
 /**
@@ -269,7 +267,8 @@ ZTEST(signals, test_signal_mask)
 	 * Set board level (polled) signal.
 	 */
 	power_signal_set(PWR_ALL_SYS_PWRGD, 1);
-	zassert_equal(bm, (power_get_signals() & bm),
+	zassert_equal(
+		bm, (power_get_signals() & bm),
 		"Expected PWR_ALL_SYS_PWRGD signal to be present in mask");
 	/*
 	 * Use GPIO that does not interrupt to confirm that a pin change
@@ -281,11 +280,11 @@ ZTEST(signals, test_signal_mask)
 	emul_set(PWR_IMVP9_VRRDY, 1);
 	zassert_equal(0, (power_get_signals() & vm), "Expected mask to be 0");
 	zassert_equal(true, power_signals_match(bm, bm),
-		"Expected match of mask to signal match");
+		      "Expected match of mask to signal match");
 	zassert_equal(-ETIMEDOUT, power_wait_mask_signals_timeout(bm, 0, 5),
-		"Expected timeout waiting for mask to be 0");
+		      "Expected timeout waiting for mask to be 0");
 	zassert_ok(power_wait_mask_signals_timeout(0, vm, 5),
-		"expected match with a 0 mask (always true)");
+		   "expected match with a 0 mask (always true)");
 }
 
 /**
@@ -305,7 +304,7 @@ ZTEST(signals, test_debug_mask)
 	old = power_get_debug();
 	power_set_debug(dm);
 	zassert_equal(dm, power_get_debug(),
-		"Debug mask does not match set value");
+		      "Debug mask does not match set value");
 	/*
 	 * Reset back to default.
 	 */
@@ -332,10 +331,10 @@ ZTEST(signals, test_gpio_interrupts)
 	/* Check that GPIO pin changes update the signal mask. */
 	emul_set(PWR_RSMRST, 1);
 	zassert_equal(true, power_signals_on(rsm),
-		"PWR_RSMRST not updated in mask");
+		      "PWR_RSMRST not updated in mask");
 	emul_set(PWR_RSMRST, 0);
 	zassert_equal(true, power_signals_off(rsm),
-		"PWR_RSMRST not updated in mask");
+		      "PWR_RSMRST not updated in mask");
 
 	/*
 	 * Check that an ACTIVE_LOW signal gets asserted in
@@ -343,10 +342,10 @@ ZTEST(signals, test_gpio_interrupts)
 	 */
 	emul_set(PWR_SLP_S3, 0);
 	zassert_equal(true, power_signals_on(s3),
-		"SLP_S3 signal should be on in mask");
+		      "SLP_S3 signal should be on in mask");
 	emul_set(PWR_SLP_S3, 1);
 	zassert_equal(true, power_signals_off(s3),
-		"SLP_S3 should be off in mask");
+		      "SLP_S3 should be off in mask");
 
 	/*
 	 * Check that disabled interrupt on the GPIO does not trigger
@@ -354,18 +353,18 @@ ZTEST(signals, test_gpio_interrupts)
 	 */
 	emul_set(PWR_SLP_S0, 0);
 	zassert_equal(false, power_signals_on(s0),
-		"SLP_S0 should not have updated");
+		      "SLP_S0 should not have updated");
 	emul_set(PWR_SLP_S0, 1);
 	zassert_equal(false, power_signals_on(s0),
-		"SLP_S0 should not have updated");
+		      "SLP_S0 should not have updated");
 
 	power_signal_enable(PWR_SLP_S0);
 	emul_set(PWR_SLP_S0, 0);
 	zassert_equal(true, power_signals_on(s0),
-		"SLP_S0 should have updated the mask");
+		      "SLP_S0 should have updated the mask");
 	emul_set(PWR_SLP_S0, 1);
 	zassert_equal(true, power_signals_off(s0),
-		"SLP_S0 should have updated the mask");
+		      "SLP_S0 should have updated the mask");
 
 	/*
 	 * Disable the GPIO interrupt again.
@@ -373,10 +372,10 @@ ZTEST(signals, test_gpio_interrupts)
 	power_signal_disable(PWR_SLP_S0);
 	emul_set(PWR_SLP_S0, 0);
 	zassert_equal(false, power_signals_on(s0),
-		"SLP_S0 should not have updated the mask");
+		      "SLP_S0 should not have updated the mask");
 	emul_set(PWR_SLP_S0, 1);
 	zassert_equal(true, power_signals_off(s0),
-		"SLP_S0 should not have updated the mask");
+		      "SLP_S0 should not have updated the mask");
 }
 
 /**
@@ -400,16 +399,14 @@ ZTEST(signals, test_espi_vw)
 	 * so sending a 0 value should be received as a signal.
 	 */
 	emul_espi_host_send_vw(espi, ESPI_VWIRE_SIGNAL_SLP_S5, 0);
-	zassert_equal(1, power_signal_get(PWR_SLP_S5),
-		"VW SLP_S5 should be 1");
+	zassert_equal(1, power_signal_get(PWR_SLP_S5), "VW SLP_S5 should be 1");
 	emul_espi_host_send_vw(espi, ESPI_VWIRE_SIGNAL_SLP_S5, 1);
-	zassert_equal(0, power_signal_get(PWR_SLP_S5),
-		"VW SLP_S5 should be 0");
+	zassert_equal(0, power_signal_get(PWR_SLP_S5), "VW SLP_S5 should be 0");
 }
 
 static void *init_dev(void)
 {
-	emul_port = device_get_binding("GPIO_0");
+	emul_port = DEVICE_DT_GET(DT_NODELABEL(gpio0));
 
 	return NULL;
 }
@@ -422,5 +419,9 @@ static void init_signals(void *data)
 /**
  * @brief Test Suite: Verifies power signal functionality.
  */
-ZTEST_SUITE(signals, ap_power_predicate_post_main,
-	    init_dev, init_signals, NULL, NULL);
+ZTEST_SUITE(signals, ap_power_predicate_post_main, init_dev, init_signals, NULL,
+	    NULL);
+
+/* These 2 lines are needed because we don't define an espi host driver */
+#define DT_DRV_COMPAT zephyr_espi_emul_espi_host
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
diff --git a/zephyr/test/ap_power/testcase.yaml b/zephyr/test/ap_power/testcase.yaml
new file mode 100644
index 0000000000..aaf8a530a6
--- /dev/null
+++ b/zephyr/test/ap_power/testcase.yaml
@@ -0,0 +1,4 @@
+common:
+  platform_allow: native_posix
+tests:
+  ap_power.default: {}
diff --git a/zephyr/test/base32/BUILD.py b/zephyr/test/base32/BUILD.py
deleted file mode 100644
index 28023ccdc9..0000000000
--- a/zephyr/test/base32/BUILD.py
+++ /dev/null
@@ -1,7 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-"""Register zmake project for base32 test."""
-
-register_host_test("base32")
diff --git a/zephyr/test/base32/CMakeLists.txt b/zephyr/test/base32/CMakeLists.txt
index 674ad0d244..97e01b0ab7 100644
--- a/zephyr/test/base32/CMakeLists.txt
+++ b/zephyr/test/base32/CMakeLists.txt
@@ -1,9 +1,9 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 cmake_minimum_required(VERSION 3.13.1)
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
 project(base32)
 
 target_sources(app PRIVATE "${PLATFORM_EC}/test/base32.c")
diff --git a/zephyr/test/base32/boards/native_posix.overlay b/zephyr/test/base32/boards/native_posix.overlay
new file mode 100644
index 0000000000..c4d4413ad7
--- /dev/null
+++ b/zephyr/test/base32/boards/native_posix.overlay
@@ -0,0 +1,6 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <board-overlays/native_posix.dts>
diff --git a/zephyr/test/base32/prj.conf b/zephyr/test/base32/prj.conf
index ec8c5035f5..2962b8f42f 100644
--- a/zephyr/test/base32/prj.conf
+++ b/zephyr/test/base32/prj.conf
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/test/base32/testcase.yaml b/zephyr/test/base32/testcase.yaml
new file mode 100644
index 0000000000..ea0374bbd0
--- /dev/null
+++ b/zephyr/test/base32/testcase.yaml
@@ -0,0 +1,5 @@
+common:
+  platform_allow: native_posix
+tests:
+  base32.default: {}
+
diff --git a/zephyr/test/crc/BUILD.py b/zephyr/test/crc/BUILD.py
deleted file mode 100644
index 8ca9c04936..0000000000
--- a/zephyr/test/crc/BUILD.py
+++ /dev/null
@@ -1,7 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-"""Register zmake project for crc test."""
-
-register_host_test("crc")
diff --git a/zephyr/test/crc/CMakeLists.txt b/zephyr/test/crc/CMakeLists.txt
index 0b46729578..b0b0996312 100644
--- a/zephyr/test/crc/CMakeLists.txt
+++ b/zephyr/test/crc/CMakeLists.txt
@@ -1,9 +1,9 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 cmake_minimum_required(VERSION 3.13.1)
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
 project(crc)
 
 # Include the test source and the file under test
diff --git a/zephyr/test/crc/boards/native_posix.overlay b/zephyr/test/crc/boards/native_posix.overlay
new file mode 100644
index 0000000000..90c864d2fd
--- /dev/null
+++ b/zephyr/test/crc/boards/native_posix.overlay
@@ -0,0 +1,6 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <board-overlays/native_posix.dts>
diff --git a/zephyr/test/crc/main.c b/zephyr/test/crc/main.c
index 50f7be79a0..0b13970d83 100644
--- a/zephyr/test/crc/main.c
+++ b/zephyr/test/crc/main.c
@@ -1,15 +1,16 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <zephyr/kernel.h>
-#include <ztest.h>
+#include <zephyr/ztest_assert.h>
+#include <zephyr/ztest_test_new.h>
 
 #include "crc8.h"
 
-/* Note this test makes the pure platform/ec test that uses the same value */
-static void test_crc8_known_data(void)
+ZTEST_SUITE(crc_driver, NULL, NULL, NULL, NULL, NULL);
+
+ZTEST(crc_driver, test_crc8_known_data)
 {
 	uint8_t buffer[10] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 8 };
 
@@ -18,10 +19,3 @@ static void test_crc8_known_data(void)
 	/* Verifies polynomial values of 0x07 representing x^8 + x^2 + x + 1 */
 	zassert_equal(crc, 170, "CRC8 hash did not match");
 }
-
-void test_main(void)
-{
-	ztest_test_suite(test_task_shim,
-			 ztest_unit_test(test_crc8_known_data));
-	ztest_run_test_suite(test_task_shim);
-}
diff --git a/zephyr/test/crc/prj.conf b/zephyr/test/crc/prj.conf
index ec8c5035f5..89fdcc1efe 100644
--- a/zephyr/test/crc/prj.conf
+++ b/zephyr/test/crc/prj.conf
@@ -1,7 +1,8 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 CONFIG_ZTEST=y
+CONFIG_ZTEST_NEW_API=y
 CONFIG_PLATFORM_EC=y
 CONFIG_CROS_EC=y
diff --git a/zephyr/test/crc/testcase.yaml b/zephyr/test/crc/testcase.yaml
new file mode 100644
index 0000000000..2a7787979d
--- /dev/null
+++ b/zephyr/test/crc/testcase.yaml
@@ -0,0 +1,4 @@
+common:
+  platform_allow: native_posix
+tests:
+  crc.default: {}
diff --git a/zephyr/test/drivers/BUILD.py b/zephyr/test/drivers/BUILD.py
deleted file mode 100644
index c43579da2e..0000000000
--- a/zephyr/test/drivers/BUILD.py
+++ /dev/null
@@ -1,18 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-"""Register zmake project for drivers test."""
-
-register_host_test(
-    "drivers",
-    dts_overlays=[
-        "overlay.dts",
-        here / "led_driver/led_pins.dts",
-        here / "led_driver/led_policy.dts",
-    ],
-    kconfig_files=[
-        here / "led_driver/prj.conf",
-    ],
-    test_args=["-flash={test_temp_dir}/flash.bin"],
-)
diff --git a/zephyr/test/drivers/CMakeLists.txt b/zephyr/test/drivers/CMakeLists.txt
index 33163427b5..9e51295d4d 100644
--- a/zephyr/test/drivers/CMakeLists.txt
+++ b/zephyr/test/drivers/CMakeLists.txt
@@ -1,79 +1,69 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 cmake_minimum_required(VERSION 3.13.1)
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
 project(drivers)
 
-# Include the local test directory for shimmed_test_tasks.h
-zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}")
-zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}/include")
-zephyr_include_directories("${PLATFORM_EC}/driver/ppc/")
+add_subdirectory(common)
 
-target_sources(app PRIVATE
-  src/battery.c
-  src/bb_retimer.c
-  src/bc12.c
-  src/bma2x2.c
-  src/bmi160.c
-  src/bmi260.c
-  src/charge_manager.c
-  src/chargesplash.c
-  src/console_cmd/charge_manager.c
-  src/console_cmd/charge_state.c
-  src/console_cmd/accelinit.c
-  src/console_cmd/accelinfo.c
-  src/console_cmd/accelspoof.c
-  src/console_cmd/accelrate.c
-  src/console_cmd/accelrange.c
-  src/console_cmd/accelread.c
-  src/console_cmd/accelres.c
-  src/console_cmd/usb_pd_console.c
-  src/cros_cbi.c
-  src/espi.c
-  src/gpio.c
-  src/host_cmd/motion_sense.c
-  src/integration/usbc/usb.c
-  src/integration/usbc/usb_20v_3a_pd_charger.c
-  src/integration/usbc/usb_5v_3a_pd_sink.c
-  src/integration/usbc/usb_5v_3a_pd_source.c
-  src/integration/usbc/usb_alt_mode.c
-  src/integration/usbc/usb_attach_src_snk.c
-  src/integration/usbc/usb_pd_ctrl_msg.c
-  src/integration/usbc/usb_malfunction_sink.c
-  src/i2c_passthru.c
-  src/isl923x.c
-  src/keyboard_scan.c
-  src/lid_switch.c
-  src/lis2dw12.c
-  src/ln9310.c
-  src/main.c
-  src/motion_sense/motion_sense.c
-  src/panic.c
-  src/power_common.c
-  src/ppc_sn5s330.c
-  src/ppc_syv682x.c
-  src/ps8xxx.c
-  src/smart.c
-  src/stm_mems_common.c
-  src/stubs.c
-  src/tcpci.c
-  src/tcpci_test_common.c
-  src/tcs3400.c
-  src/temp_sensor.c
-  src/test_mocks.c
-  src/test_rules.c
-  src/thermistor.c
-  src/uart_hostcmd.c
-  src/usb_mux.c
-  src/usb_pd_host_cmd.c
-  src/utils.c
-  src/vboot_hash.c
-  src/watchdog.c
-)
+get_target_property(TEST_SOURCES app SOURCES)
 
-add_subdirectory(isl923x)
-add_subdirectory(led_driver)
+# Support zmake for now
+if("${ZMAKE_PROJECT_NAME}" STREQUAL "test-drivers")
+  set(CONFIG_LINK_TEST_SUITE_DEFAULT TRUE)
+  set(CONFIG_LINK_TEST_SUITE_USB_MALFUNCTION_SINK TRUE)
+  add_compile_definitions(CONFIG_LINK_TEST_SUITE_DEFAULT=1)
+  add_compile_definitions(CONFIG_LINK_TEST_SUITE_USB_MALFUNCTION_SINK=1)
+elseif("${ZMAKE_PROJECT_NAME}" STREQUAL "test-drivers-ap_mux_control")
+  set(CONFIG_LINK_TEST_SUITE_AP_MUX_CONTROL TRUE)
+  add_compile_definitions(CONFIG_LINK_TEST_SUITE_AP_MUX_CONTROL=1)
+elseif("${ZMAKE_PROJECT_NAME}" STREQUAL "test-drivers-usb_retimer_fw_update")
+  set(CONFIG_LINK_TEST_SUITE_USB_RETIMER_FW_UPDATE TRUE)
+  add_compile_definitions(CONFIG_LINK_TEST_SUITE_USB_RETIMER_FW_UPDATE=1)
+elseif("${ZMAKE_PROJECT_NAME}" STREQUAL "test-drivers-chargesplash")
+  set(CONFIG_LINK_TEST_SUITE_CHARGESPLASH TRUE)
+  add_compile_definitions(CONFIG_LINK_TEST_SUITE_CHARGESPLASH=1)
+elseif("${ZMAKE_PROJECT_NAME}" STREQUAL "test-drivers-isl923x")
+  set(CONFIG_LINK_TEST_SUITE_ISL923X TRUE)
+  add_compile_definitions(CONFIG_LINK_TEST_SUITE_ISL923X=1)
+elseif("${ZMAKE_PROJECT_NAME}" STREQUAL "test-drivers-led_driver")
+  set(CONFIG_LINK_TEST_SUITE_LED_DRIVER TRUE)
+  add_compile_definitions(CONFIG_LINK_TEST_SUITE_LED_DRIVER=1)
+elseif("${ZMAKE_PROJECT_NAME}" STREQUAL "test-drivers-dps")
+  set(CONFIG_LINK_TEST_SUITE_USB_PD_DPS TRUE)
+  add_compile_definitions(CONFIG_LINK_TEST_SUITE_USB_PD_DPS=1)
+elseif("${ZMAKE_PROJECT_NAME}" STREQUAL "test-drivers-usbc_alt_mode")
+  set(CONFIG_LINK_TEST_SUITE_USBC_ALT_MODE TRUE)
+  add_compile_definitions(CONFIG_LINK_TEST_SUITE_USBC_ALT_MODE=1)
+elseif("${ZMAKE_PROJECT_NAME}" STREQUAL "test-drivers-usbc_tbt_mode")
+  set(CONFIG_LINK_TEST_SUITE_USBC_TBT_MODE TRUE)
+  add_compile_definitions(CONFIG_LINK_TEST_SUITE_USBC_TBT_MODE=1)
+endif()
+
+# Add linked suites here
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_DEFAULT default)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_AP_MUX_CONTROL ap_mux_control)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_CHARGESPLASH chargesplash)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_ISL923X isl923x)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_KEYBOARD_SCAN keyboard_scan)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_LED_DRIVER led_driver)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_MKBP mkbp)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_USB_MALFUNCTION_SINK usb_malfunction_sink)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_USB_PD_DPS dps)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_USB_RETIMER_FW_UPDATE usb_retimer_fw_update)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_USBC_ALT_MODE usbc_alt_mode)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_USBC_TBT_MODE usbc_tbt_mode)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_USBC_OCP usbc_ocp)
+add_subdirectory_ifdef(CONFIG_LINK_TEST_SUITE_HOST_COMMANDS host_cmd)
+
+get_target_property(TEST_SOURCES_NEW app SOURCES)
+
+# Check to make sure at least one suite was added
+list(REMOVE_ITEM TEST_SOURCES_NEW ${TEST_SOURCES})
+if(NOT TEST_SOURCES_NEW)
+  message(FATAL_ERROR "Invalid configuration, must add test sources")
+endif()
 
 set_compiler_property(APPEND PROPERTY coverage -O0)
diff --git a/zephyr/test/drivers/Kconfig b/zephyr/test/drivers/Kconfig
index 6e57a22c1f..cf877607ce 100644
--- a/zephyr/test/drivers/Kconfig
+++ b/zephyr/test/drivers/Kconfig
@@ -1,11 +1,47 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
-config BUG209907615
-	bool "Enable tests for b:209907615"
-	help
-	This flag may change as we protoype integration tests.
-	TODO(b/209907615): Remove when test finished.
+config LINK_TEST_SUITE_DEFAULT
+	bool "Link and test the default test suite"
+
+config LINK_TEST_SUITE_AP_MUX_CONTROL
+	bool "Link and test the ap_mux_control tests"
+
+config LINK_TEST_SUITE_CHARGESPLASH
+	bool "Link and test the chargesplash tests"
+
+config LINK_TEST_SUITE_ISL923X
+	bool "Link and test the isl923x tests"
+
+config LINK_TEST_SUITE_KEYBOARD_SCAN
+	bool "Link and test the keyboard_scan tests"
+
+config LINK_TEST_SUITE_LED_DRIVER
+	bool "Link and test the led_driver tests"
+
+config LINK_TEST_SUITE_MKBP
+	bool "Link and test the mkbp tests"
+
+config LINK_TEST_SUITE_USB_MALFUNCTION_SINK
+	bool "Link and test the usb_malfunction_sink tests"
+
+config LINK_TEST_SUITE_USB_PD_DPS
+	bool "Link and test the dps tests"
+
+config LINK_TEST_SUITE_USB_RETIMER_FW_UPDATE
+	bool "Link and test the usb_retimer_fw_update tests"
+
+config LINK_TEST_SUITE_USBC_ALT_MODE
+	bool "Link and test the usbc_alt_mode tests"
+
+config LINK_TEST_SUITE_USBC_TBT_MODE
+	bool "Link and test the usbc_tbt_mode tests"
+
+config LINK_TEST_SUITE_HOST_COMMANDS
+	bool "Link and test the host command tests"
+
+config LINK_TEST_SUITE_USBC_OCP
+	bool "Link tests for common USBC OCP code"
 
 source "Kconfig.zephyr"
diff --git a/zephyr/test/drivers/README.md b/zephyr/test/drivers/README.md
index 11c913baa8..7dfc5c51e5 100644
--- a/zephyr/test/drivers/README.md
+++ b/zephyr/test/drivers/README.md
@@ -1,31 +1,22 @@
-This is the combined driver test. The goal is to have many driver test suites
-in one binary, so that compile time will be faster than many small tests, and
+This is the drivers test directory. The goal is to have many driver test suites
+in few binaries, so that compile time will be faster than many small tests, and
 so we can test interactions between different subsystems easily.
 
 ## Run all the test suites
 
 ```bash
-(chroot) zmake test test-drivers
+(chroot) ec $ ./twister -T zephyr/test/drivers
 ```
 
-To see all the output of zmake (for example if the build fails)
+To see all the output of twister in stdout (for example if the build fails)
 
 ```bash
-(chroot) zmake -l DEBUG -j 1 test test-drivers
+(chroot) ec $ ./twister -v -i -T zephyr/test/drivers
 ```
 
 ## Code coverage
 
-To calculate code coverage for this test only
-
-```bash
-(chroot) zmake test --coverage test-drivers
-(chroot) genhtml --branch-coverage -q \
-        -o build/zephyr/test-drivers/output/coverage_rpt \
-        build/zephyr/test-drivers/output/zephyr.info
-```
-
-The report will be in build/zephyr/test-drivers/output/coverage_rpt/index.html
+See the [EC code coverage] doc.
 
 ## Debugging
 
@@ -35,15 +26,24 @@ You need the host version of gdb:
 (chroot) sudo emerge -j sys-devel/gdb
 ```
 
-Build the test
+Build all the drivers tests
 ```bash
-(chroot) zmake build test-drivers
+(chroot) ec $ ./twister -b -T zephyr/test/drivers
 ```
 
 Then run gdb
 
+Example of running gdb on the `drivers.default` test binary:
+
 ```
-(chroot) gdb build/zephyr/test-drivers/build-singleimage/zephyr/zephyr.exe
+(chroot) ec $ gdb twister-out/native_posix/drivers.default/zephyr/zephyr.exe
 # Set breakpoints, run, etc.
 ```
 
+Another of running gdb now on the `drivers.chargesplash` test binary:
+
+```
+(chroot) ec $ gdb twister-out/native_posix/drivers.chargesplash/zephyr/zephyr.exe
+```
+
+[EC code coverage]: ../../../docs/code_coverage.md#zephyr-ztest-code-coverage
diff --git a/zephyr/test/drivers/ap_mux_control/CMakeLists.txt b/zephyr/test/drivers/ap_mux_control/CMakeLists.txt
new file mode 100644
index 0000000000..005e72e714
--- /dev/null
+++ b/zephyr/test/drivers/ap_mux_control/CMakeLists.txt
@@ -0,0 +1,19 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Create library name based on current directory
+zephyr_library_get_current_dir_lib_name(${ZEPHYR_BASE} lib_name)
+
+# Create interface library
+zephyr_interface_library_named(${lib_name})
+
+# Add include paths
+zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}")
+zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}/include")
+
+# Add source files
+zephyr_library_sources("${CMAKE_CURRENT_SOURCE_DIR}/src/ap_mux_control.c")
+
+# Link in the library
+zephyr_library_link_libraries(${lib_name})
diff --git a/zephyr/test/drivers/ap_mux_control/prj.conf b/zephyr/test/drivers/ap_mux_control/prj.conf
new file mode 100644
index 0000000000..75b05bce0b
--- /dev/null
+++ b/zephyr/test/drivers/ap_mux_control/prj.conf
@@ -0,0 +1,6 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_PLATFORM_EC_USB_MUX_AP_CONTROL=y
+CONFIG_PLATFORM_EC_USB_MUX_TASK=y
diff --git a/zephyr/test/drivers/ap_mux_control/src/ap_mux_control.c b/zephyr/test/drivers/ap_mux_control/src/ap_mux_control.c
new file mode 100644
index 0000000000..49c695b830
--- /dev/null
+++ b/zephyr/test/drivers/ap_mux_control/src/ap_mux_control.c
@@ -0,0 +1,87 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/ztest.h>
+
+#include "usb_mux.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+static void ap_mux_control_before(void *data)
+{
+	/* Set chipset on to ensure muxes are "powered" */
+	test_set_chipset_to_s0();
+
+	/*
+	 * Set all muxes to NONE to begin with and give time for the USB_MUX
+	 * task to process them.
+	 */
+	usb_mux_set(USBC_PORT_C0, USB_PD_MUX_NONE, USB_SWITCH_CONNECT, 0);
+	k_sleep(K_SECONDS(1));
+
+	/* And test the assumption that setting NONE worked */
+	zassume_equal(usb_mux_get(USBC_PORT_C0), USB_PD_MUX_NONE,
+		      "Failed to set mux to initial state");
+}
+
+static void ap_mux_control_after(void *data)
+{
+	/*
+	 * Set all muxes to NONE now that we're done and give time for the
+	 * USB_MUX task to process them.
+	 */
+	usb_mux_set(USBC_PORT_C0, USB_PD_MUX_NONE, USB_SWITCH_CONNECT, 0);
+	k_sleep(K_SECONDS(1));
+}
+
+ZTEST_SUITE(ap_mux_control, drivers_predicate_post_main, NULL,
+	    ap_mux_control_before, ap_mux_control_after, NULL);
+
+ZTEST(ap_mux_control, test_set_muxes)
+{
+	struct ec_response_typec_status status;
+	struct typec_usb_mux_set mux_set;
+	uint32_t port_events;
+	int index;
+	uint8_t set_mode = USB_PD_MUX_DOCK;
+
+	/* Test setting both mux indexes and receiving their events */
+	/* TODO(b/239457738): Loop counter should come from device tree */
+	for (index = 0; index < 2; index++) {
+		mux_set.mux_index = index;
+		mux_set.mux_flags = set_mode;
+
+		host_cmd_typec_control_usb_mux_set(USBC_PORT_C0, mux_set);
+
+		/* Give the task processing time */
+		k_sleep(K_SECONDS(1));
+
+		/*
+		 * TODO(b/239460181): The "AP" should receive
+		 * EC_HOST_EVENT_PD_MCU
+		 */
+
+		/* We should see the right index's event set on the port */
+		status = host_cmd_typec_status(USBC_PORT_C0);
+		port_events = index ? PD_STATUS_EVENT_MUX_1_SET_DONE :
+				      PD_STATUS_EVENT_MUX_0_SET_DONE;
+		zassert_true(status.events & port_events, "Port event missing");
+
+		/* Clear this mux's event */
+		host_cmd_typec_control_clear_events(USBC_PORT_C0, port_events);
+	}
+
+	/*
+	 * Verify our mux mode is reported as set, and that our mux events are
+	 * cleared out
+	 */
+	status = host_cmd_typec_status(USBC_PORT_C0);
+	port_events = PD_STATUS_EVENT_MUX_0_SET_DONE |
+		      PD_STATUS_EVENT_MUX_1_SET_DONE;
+	zassert_false(status.events & port_events, "Port events still set");
+	zassert_equal(status.mux_state, set_mode,
+		      "Mux set to unexpected state");
+}
diff --git a/zephyr/test/drivers/overlay.dts b/zephyr/test/drivers/boards/native_posix.overlay
index d8c92a53ef..03b59c8ac7 100644
--- a/zephyr/test/drivers/overlay.dts
+++ b/zephyr/test/drivers/boards/native_posix.overlay
@@ -1,11 +1,13 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include <board-overlays/native_posix.dts>
 #include <cros/binman.dtsi>
 #include <cros/thermistor/thermistor.dtsi>
 #include <dt-bindings/gpio_defines.h>
+#include <dt-bindings/pwm/pwm.h>
 #include <freq.h>
 
 / {
@@ -13,7 +15,9 @@
 		cros-ec,espi = &espi0;
 		cros-ec,watchdog = &wdt_counter;
 		cros-ec,raw-kb = &cros_kb_raw;
+		cros-ec,flash = &flash0;
 		cros-ec,flash-controller = &cros_flash;
+		cros,rtc = &cros_rtc;
 	};
 
 	aliases {
@@ -31,17 +35,14 @@
 		port0@0 {
 			compatible = "named-usbc-port";
 			reg = <0>;
-
-			chg {
-				compatible = "intersil,isl923x";
-				status = "okay";
-				port = <&i2c_charger>;
-			};
+			chg = <&isl923x_emul>;
+			tcpc = <&tcpci_emul>;
 		};
 
 		port1@1 {
 			compatible = "named-usbc-port";
 			reg = <1>;
+			tcpc = <&ps8xxx_emul>;
 		};
 	};
 
@@ -54,19 +55,24 @@
 		compatible = "named-gpios";
 
 		gpio_acok_od: acok_od {
-			gpios = <&gpio0 2 GPIO_INPUT>;
+			gpios = <&gpio0 0 GPIO_INPUT>;
 			enum-name = "GPIO_AC_PRESENT";
 		};
+
+		/* <&gpio0 1 x> is reserved as 'entering-rw' in
+		 * src/platform/ec/zephyr/dts/board-overlays/native_posix.dts
+		 */
+
 		/* In test WP is output because CBI use it, but it is also
 		 * input, because test_all_tags set it to enable write
 		 * protection.
 		 */
 		gpio_wp_l: wp_l {
-			gpios = <&gpio0 3 (GPIO_INPUT | GPIO_OUTPUT |
+			gpios = <&gpio0 2 (GPIO_INPUT | GPIO_OUTPUT |
 					   GPIO_ACTIVE_LOW)>;
 		};
 		gpio_ec_kso_02_inv: ec_kso_02_inv {
-			gpios = <&gpio0 4 (GPIO_INPUT | GPIO_OUTPUT_LOW)>;
+			gpios = <&gpio0 3 (GPIO_INPUT | GPIO_OUTPUT_LOW)>;
 		};
 		pg_ec_dsw_pwrok {
 			gpios = <&gpio0 4 GPIO_INPUT>;
@@ -125,11 +131,11 @@
 			enum-name = "GPIO_AP_SUSPEND";
 		};
 		gpio_pmic_kpd_pwr_odl: pmic_kpd_pwr_odl {
-			gpios = <&gpio0 20 GPIO_ODR_HIGH>;
+			gpios = <&gpio0 20 GPIO_OUTPUT_HIGH>;
 			enum-name = "GPIO_PMIC_KPD_PWR_ODL";
 		};
 		gpio_pmic_resin_l: pmic_resin_l {
-			gpios = <&gpio0 21 GPIO_ODR_HIGH>;
+			gpios = <&gpio0 21 GPIO_OUTPUT_HIGH>;
 			enum-name = "GPIO_PMIC_RESIN_L";
 		};
 		gpio_warm_reset_l: warm_reset_l {
@@ -174,14 +180,43 @@
 			#led-pin-cells = <1>;
 			gpios = <&gpio0 31 (GPIO_INPUT | GPIO_OUTPUT_LOW)>;
 		};
+		/* gpio1 */
 		gpio_ec_chg_led_y_c1: ec_chg_led_y_c1 {
 			#led-pin-cells = <1>;
-			gpios = <&gpio0 32 (GPIO_INPUT | GPIO_OUTPUT_LOW)>;
+			gpios = <&gpio1 0 (GPIO_INPUT | GPIO_OUTPUT_LOW)>;
 		};
 		gpio_ec_chg_led_w_c1: ec_chg_led_w_c1 {
 			#led-pin-cells = <1>;
-			gpios = <&gpio0 33 (GPIO_INPUT | GPIO_OUTPUT_LOW)>;
+			gpios = <&gpio1 1 (GPIO_INPUT | GPIO_OUTPUT_LOW)>;
+		};
+		gpio_ap_ec_int_l: ap_ec_int_l {
+			gpios = <&gpio1 2 GPIO_OUTPUT_HIGH>;
+			enum-name = "GPIO_EC_INT_L";
+		};
+		gpio_ec_voldn_btn_odl: ec_voldn_btn_odl {
+			gpios = <&gpio1 3 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_DOWN_L";
+		};
+		gpio_ec_volup_btn_odl: ec_volup_btn_odl {
+			gpios = <&gpio1 4 GPIO_INPUT_PULL_UP>;
+			enum-name = "GPIO_VOLUME_UP_L";
 		};
+		gpio_ec_pg_pin_temp: ec_pg_pin_temp {
+			gpios = <&gpio0 4 GPIO_INPUT>;
+		};
+	};
+
+	gpio1: gpio@101 {
+		status = "okay";
+		compatible = "zephyr,gpio-emul";
+		reg = <0x101 0x4>;
+		rising-edge;
+		falling-edge;
+		high-level;
+		low-level;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <5>;
 	};
 
 	gpio-interrupts {
@@ -237,41 +272,28 @@
 	named-i2c-ports {
 		compatible = "named-i2c-ports";
 
-		usb-c0 {
+		named_i2c0: i2c0 {
 			i2c-port = <&i2c0>;
-			enum-name = "I2C_PORT_USB_C0";
-		};
-		usb-c1 {
+			enum-names = "I2C_PORT_BATTERY",
+				"I2C_PORT_POWER",
+				"I2C_PORT_CHARGER",
+				"I2C_PORT_EEPROM",
+				"I2C_PORT_ACCEL",
+				"I2C_PORT_VIRTUAL_BATTERY";
+		};
+		named_i2c1: i2c1 {
 			i2c-port = <&i2c1>;
-			enum-name = "I2C_PORT_USB_C1";
+			enum-names = "I2C_PORT_SENSOR";
 		};
-		battery {
-			i2c-port = <&i2c0>;
-			enum-name = "I2C_PORT_BATTERY";
+		named_i2c2: i2c2 {
+			i2c-port = <&i2c2>;
+			dynamic-speed;
+			enum-names = "I2C_PORT_USB_C0";
 		};
-		power {
-			i2c-port = <&i2c0>;
-			enum-name = "I2C_PORT_POWER";
-		};
-		i2c_charger: charger {
-			i2c-port = <&i2c0>;
-			enum-name = "I2C_PORT_CHARGER";
-		};
-		eeprom {
-			i2c-port = <&i2c0>;
-			enum-name = "I2C_PORT_EEPROM";
-		};
-		i2c_accel: accel {
-			i2c-port = <&i2c0>;
-			enum-name = "I2C_PORT_ACCEL";
-		};
-		i2c_sensor: sensor {
-			i2c-port = <&i2c1>;
-			enum-name = "I2C_PORT_SENSOR";
-		};
-		virtual-battery {
-			i2c-port = <&i2c0>;
-			enum-name = "I2C_PORT_VIRTUAL_BATTERY";
+		named_i2c3: i2c3 {
+			i2c-port = <&i2c3>;
+			dynamic-speed;
+			enum-names = "I2C_PORT_USB_C1";
 		};
 	};
 
@@ -335,7 +357,6 @@
 		nchannels = <6>;
 		ref-internal-mv = <3300>;
 		#io-channel-cells = <1>;
-		label = "ADC_0";
 		status = "okay";
 	};
 
@@ -343,96 +364,96 @@
 		compatible = "named-adc-channels";
 
 		adc_charger: charger {
-			label = "ADC_TEMP_SENSOR_CHARGER";
 			enum-name = "ADC_TEMP_SENSOR_CHARGER";
 			io-channels = <&adc0 0>;
 		};
 		adc_pp3300_regulator: pp3300-regulator {
-			label = "ADC_TEMP_SENSOR_PP3300_REGULATOR";
 			enum-name = "ADC_TEMP_SENSOR_PP3300_REGULATOR";
 			io-channels = <&adc0 1>;
 		};
 		adc_ddr_soc: ddr-soc {
-			label = "ADC_TEMP_SENSOR_DDR_SOC";
 			enum-name = "ADC_TEMP_SENSOR_DDR_SOC";
 			io-channels = <&adc0 2>;
 		};
 		adc_fan: fan {
-			label = "ADC_TEMP_SENSOR_FAN";
 			enum-name = "ADC_TEMP_SENSOR_FAN";
 			io-channels = <&adc0 3>;
 		};
 		amon_bmon {
-			label = "AMON_BMON";
 			enum-name = "ADC_AMON_BMON";
 			io-channels = <&adc0 4>;
 			mul = <1000>;
 			div = <20>;
 		};
 		psys {
-			label = "PSYS";
 			enum-name = "ADC_PSYS";
 			io-channels = <&adc0 5>;
 			mul = <124000>;
 		};
 	};
 
+	temp_charger: charger {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_13K7_47K_4050B>;
+		adc = <&adc_charger>;
+	};
+	temp_pp3300_regulator: pp3300-regulator {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_30K9_47K_4050B>;
+		adc = <&adc_pp3300_regulator>;
+	};
+	temp_ddr_soc: ddr-soc {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		adc = <&adc_ddr_soc>;
+	};
+	temp_fan: fan {
+		compatible = "cros-ec,temp-sensor-thermistor";
+		thermistor = <&thermistor_3V0_22K6_47K_4050B>;
+		adc = <&adc_fan>;
+	};
+
 	named-temp-sensors {
-		charger {
-			thermistor = <&thermistor_3V3_13K7_47K_4050B>;
+		compatible = "cros-ec,temp-sensors";
+		named_temp_charger: charger {
 			status = "okay";
-			compatible = "cros-ec,temp-sensor-thermistor",
-				     "cros-ec,temp-sensor";
-			label = "TEMP_SENSOR_CHARGER";
-			enum-name = "TEMP_SENSOR_CHARGER";
 			temp_fan_off = <40>;
 			temp_fan_max = <55>;
 			temp_host_high = <75>;
 			temp_host_halt = <80>;
 			temp_host_release_high = <65>;
-			adc = <&adc_charger>;
+			power-good-pin = <&gpio_ec_pg_pin_temp>;
+			sensor = <&temp_charger>;
 		};
-		pp3300-regulator {
-			thermistor = <&thermistor_3V3_30K9_47K_4050B>;
+		named_temp_pp3300_regulator: pp3300-regulator {
 			status = "okay";
-			compatible = "cros-ec,temp-sensor-thermistor",
-				     "cros-ec,temp-sensor";
-			label = "TEMP_SENSOR_PP3300_REGULATOR";
-			enum-name = "TEMP_SENSOR_PP3300_REGULATOR";
 			temp_fan_off = <40>;
 			temp_fan_max = <55>;
 			temp_host_high = <75>;
 			temp_host_halt = <80>;
 			temp_host_release_high = <65>;
-			adc = <&adc_pp3300_regulator>;
+			power-good-pin = <&gpio_ec_pg_pin_temp>;
+			sensor = <&temp_pp3300_regulator>;
 		};
-		ddr-soc {
-			thermistor = <&thermistor_3V3_51K1_47K_4050B>;
+		named_temp_ddr_soc: ddr-soc {
 			status = "okay";
-			compatible = "cros-ec,temp-sensor-thermistor",
-				     "cros-ec,temp-sensor";
-			label = "TEMP_SENSOR_DDR_SOC";
-			enum-name = "TEMP_SENSOR_DDR_SOC";
 			temp_fan_off = <35>;
 			temp_fan_max = <50>;
 			temp_host_high = <70>;
 			temp_host_halt = <80>;
 			temp_host_release_high = <65>;
-			adc = <&adc_ddr_soc>;
+			power-good-pin = <&gpio_ec_pg_pin_temp>;
+			sensor = <&temp_ddr_soc>;
 		};
-		fan {
-			thermistor = <&thermistor_3V0_22K6_47K_4050B>;
+		named_temp_fan: fan {
 			status = "okay";
-			compatible = "cros-ec,temp-sensor-thermistor",
-				     "cros-ec,temp-sensor";
-			label = "TEMP_SENSOR_FAN";
-			enum-name = "TEMP_SENSOR_FAN";
 			temp_fan_off = <35>;
 			temp_fan_max = <50>;
 			temp_host_high = <70>;
 			temp_host_halt = <80>;
 			temp_host_release_high = <65>;
-			adc = <&adc_fan>;
+			power-good-pin = <&gpio_ec_pg_pin_temp>;
+			sensor = <&temp_fan>;
 		};
 	};
 
@@ -446,19 +467,15 @@
 	motionsense-mutex {
 		compatible = "cros-ec,motionsense-mutex";
 		mutex_bma255: bma255-mutex {
-			label = "BMA255_MUTEX";
 		};
 
 		mutex_bmi260: bmi260-mutex {
-			label = "BMI260_MUTEX";
 		};
 
 		mutex_bmi160: bmi160-mutex {
-			label = "BMI160_MUTEX";
 		};
 
 		mutex_lis2dw12: lis2dw12-mutex {
-			label = "LIS2DW12_MUTEX";
 		};
 	};
 
@@ -554,18 +571,18 @@
 
 	/*
 	 * List of motion sensors that creates motion_sensors array.
-	 * The label "lid_accel" and "base_accel" are used to indicate
+	 * The nodelabel "lid_accel" and "base_accel" are used to indicate
 	 * motion sensor IDs for lid angle calculation.
 	 */
 	motionsense-sensor {
-		ms_bma255: ms-bma255 {
+		base_accel: ms_bma255: ms-bma255 {
 			compatible = "cros-ec,bma255";
 			status = "okay";
 
-			label = "BMA255";
+			active-mask = "SENSOR_ACTIVE_S0_S3_S5";
 			location = "MOTIONSENSE_LOC_LID";
 			mutex = <&mutex_bma255>;
-			port = <&i2c_accel>;
+			port = <&named_i2c0>;
 			default-range = <2>;
 			drv-data = <&bma255_data>;
 			i2c-spi-addr-flags = "BMA2x2_I2C_ADDR1_FLAGS";
@@ -574,27 +591,23 @@
 					"cros-ec,motionsense-sensor-config";
 				ec-s0 {
 					/* Run ALS sensor in S0 */
-					label = "SENSOR_CONFIG_EC_S0";
 					odr = <1000>;
 				};
 				ec-s3 {
-					label = "SENSOR_CONFIG_EC_S3";
 					odr = <10000>;
 				};
 				ec-s5 {
-					label = "SENSOR_CONFIG_EC_S5";
 					odr = <10000>;
 				};
 			};
 		};
-		ms_bmi260_accel: ms-bmi260-accel {
+		lid_accel: ms_bmi260_accel: ms-bmi260-accel {
 			compatible = "cros-ec,bmi260-accel";
 			status = "okay";
 
-			label = "BMI260 emul accel";
 			location = "MOTIONSENSE_LOC_BASE";
 			mutex = <&mutex_bmi260>;
-			port = <&i2c_accel>;
+			port = <&named_i2c0>;
 			drv-data = <&bmi260_data>;
 			default-range = <4>;
 			i2c-spi-addr-flags = "BMI260_ADDR0_FLAGS";
@@ -604,10 +617,9 @@
 			compatible = "cros-ec,bmi260-gyro";
 			status = "okay";
 
-			label = "BMI260 emul gyro";
 			location = "MOTIONSENSE_LOC_BASE";
 			mutex = <&mutex_bmi260>;
-			port = <&i2c_accel>;
+			port = <&named_i2c0>;
 			drv-data = <&bmi260_data>;
 			default-range = <1000>; /* dps */
 			i2c-spi-addr-flags = "BMI260_ADDR0_FLAGS";
@@ -617,11 +629,10 @@
 			compatible = "cros-ec,bmi160-accel";
 			status = "okay";
 
-			label = "BMI160 emul accel";
 			active-mask = "SENSOR_ACTIVE_S0_S3_S5";
 			location = "MOTIONSENSE_LOC_BASE";
 			mutex = <&mutex_bmi160>;
-			port = <&i2c_sensor>;
+			port = <&named_i2c1>;
 			drv-data = <&bmi160_data>;
 			default-range = <4>;
 			i2c-spi-addr-flags = "BMI160_ADDR0_FLAGS";
@@ -631,10 +642,9 @@
 			compatible = "cros-ec,bmi160-gyro";
 			status = "okay";
 
-			label = "BMI160 emul gyro";
 			location = "MOTIONSENSE_LOC_BASE";
 			mutex = <&mutex_bmi160>;
-			port = <&i2c_sensor>;
+			port = <&named_i2c1>;
 			drv-data = <&bmi160_data>;
 			default-range = <1000>; /* dps */
 			i2c-spi-addr-flags = "BMI160_ADDR0_FLAGS";
@@ -644,10 +654,9 @@
 			compatible = "cros-ec,lis2dw12";
 			status = "okay";
 
-			label = "LIS2DW12";
 			location = "MOTIONSENSE_LOC_BASE";
 			mutex = <&mutex_lis2dw12>;
-			port = <&i2c_accel>;
+			port = <&named_i2c0>;
 			drv-data = <&lis2dw12_data>;
 			default-range = <2>;
 			i2c-spi-addr-flags = "LIS2DWL_ADDR1_FLAGS";
@@ -657,9 +666,8 @@
 			compatible = "cros-ec,tcs3400-clear";
 			status = "okay";
 
-			label = "Clear Light";
 			location = "MOTIONSENSE_LOC_BASE";
-			port = <&i2c_sensor>;
+			port = <&named_i2c1>;
 			default-range = <0x10000>;
 			drv-data = <&tcs_clear_data>;
 			i2c-spi-addr-flags = "TCS3400_I2C_ADDR_FLAGS";
@@ -668,7 +676,6 @@
 					"cros-ec,motionsense-sensor-config";
 				ec-s0 {
 					/* Run ALS sensor in S0 */
-					label = "SENSOR_CONFIG_EC_S0";
 					odr = <1000>;
 				};
 			};
@@ -678,7 +685,6 @@
 			compatible = "cros-ec,tcs3400-rgb";
 			status = "okay";
 
-			label = "RGB Light";
 			location = "MOTIONSENSE_LOC_BASE";
 			default-range = <0x10000>; /* scale = 1x, uscale = 0 */
 			drv-data = <&tcs_rgb_data>;
@@ -691,8 +697,8 @@
 	};
 
 	/*
-	 * Second i2c bus is required, because there are already devices with
-	 * addresses 0x68, 0xb and 0x9 on the first bus
+	 * Add extra i2c buses to test the I2C passthrough: 1 for sensor and
+	 * 2 dedicated for TCPC.
 	 */
 	i2c1: i2c@400 {
 		status = "okay";
@@ -701,39 +707,64 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		reg = <0x400 4>;
-		label = "I2C_1";
-
-		tcpci_ps8xxx_emul: tcpci_ps8xxx_emul@b {
-			compatible = "cros,tcpci-emul";
-			status = "okay";
-			reg = <0xb>;
-			label = "TCPCI_PS8XXX_EMUL";
-			alert_gpio = <&usb_c1_tcpc_int_odl>;
-		};
-
-		ps8xxx_emul: ps8xxx_emul@b1 {
-			compatible = "cros,ps8xxx-emul";
-			reg = <0xb1>;
-			tcpci-i2c = <&tcpci_ps8xxx_emul>;
-			p0-i2c-addr = <0x8>;
-			p1-i2c-addr = <0x9>;
-			gpio-i2c-addr = <0x1a>;
-			label = "PS8XXX_EMUL";
-		};
 
 		tcs_emul: tcs@39 {
 			compatible = "zephyr,tcs3400";
 			reg = <0x39>;
-			label = "TCS_EMUL";
 			error-on-ro-write;
 			error-on-reserved-bit-write;
 			error-on-msb-first-access;
 		};
 
+		accel_bmi160: bmi160@68 {
+			compatible = "zephyr,bmi";
+			reg = <0x68>;
+			device-model = "BMI_EMUL_160";
+			error-on-ro-write;
+			error-on-wo-read;
+			error-on-reserved-bit-write;
+			simulate-command-exec-time;
+		};
+	};
+
+	i2c2: i2c@500 {
+		status = "okay";
+		compatible = "zephyr,i2c-emul-controller";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x500 4>;
+
+		pi3usb9201_emul: pi3usb9201@5f {
+			compatible = "zephyr,pi3usb9201-emul";
+			reg = <0x5f>;
+		};
+
+		sn5s330_emul: sn5s330@40 {
+			compatible = "cros,sn5s330-emul";
+			reg = <0x40>;
+			int-pin = <&gpio_usb_c0_ppc_int>;
+		};
+
+		tcpci_emul: tcpci_emul@82 {
+			compatible = "cros,tcpci-generic-emul";
+			status = "okay";
+			reg = <0x82>;
+			alert_gpio = <&usb_c0_tcpc_int_odl>;
+		};
+	};
+
+	i2c3: i2c@600 {
+		status = "okay";
+		compatible = "zephyr,i2c-emul-controller";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x600 4>;
+
 		syv682x_emul: syv682x@41 {
 			compatible = "zephyr,syv682x-emul";
 			reg = <0x41>;
-			label = "SYV682X_EMUL";
 			frs_en_gpio = <&gpio_usb_c1_frs_en>;
 			alert_gpio = <&gpio_usb_c1_ppc_int>;
 		};
@@ -741,21 +772,18 @@
 		usb_c1_bb_retimer_emul: bbretimer@42 {
 			compatible = "cros,bb-retimer-emul";
 			reg = <0x42>;
-			label = "USB_C1_BB_RETIMER";
 			vendor = "BB_RETIMER_VENDOR_ID_1";
 			error-on-ro-write;
 			error-on-reserved-bit-write;
 		};
 
-		accel_bmi160: bmi160@68 {
-			compatible = "zephyr,bmi";
-			reg = <0x68>;
-			label = "BMI160";
-			device-model = "BMI_EMUL_160";
-			error-on-ro-write;
-			error-on-wo-read;
-			error-on-reserved-bit-write;
-			simulate-command-exec-time;
+		ps8xxx_emul: ps8xxx_emul@b {
+			compatible = "cros,ps8xxx-emul";
+			reg = <0xb>;
+			alert_gpio = <&usb_c1_tcpc_int_odl>;
+			p0-i2c-addr = <0x8>;
+			p1-i2c-addr = <0x9>;
+			gpio-i2c-addr = <0x1a>;
 		};
 	};
 
@@ -768,17 +796,130 @@
 		compatible = "zephyr,counter-watchdog";
 		status = "okay";
 		counter = <&counter0>;
-		label = "WDT_COUNTER";
 	};
 
 	cros_kb_raw: kb-raw-emul {
 		compatible = "cros-ec,kb-raw-emul";
-		label = "KB_RAW";
 	};
 
 	cros_flash: cros-flash {
 		compatible = "cros-ec,flash-emul";
-		label = "FLASH";
+	};
+
+	cros_rtc: cros-rtc {
+		compatible = "cros-ec,rtc-emul";
+	};
+
+	pwms {
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		pwm_blue_left: pwm@0 {
+			compatible = "cros,pwm-mock";
+			reg = <0 1>;
+			#pwm-cells = <3>;
+			status = "okay";
+		};
+		pwm_white_left: pwm@1 {
+			compatible = "cros,pwm-mock";
+			reg = <1 1>;
+			#pwm-cells = <3>;
+			status = "okay";
+		};
+		pwm_amber_right: pwm@2 {
+			compatible = "cros,pwm-mock";
+			reg = <2 1>;
+			#pwm-cells = <3>;
+			status = "okay";
+		};
+		pwm_white_right: pwm@3 {
+			compatible = "cros,pwm-mock";
+			reg = <3 1>;
+			#pwm-cells = <3>;
+			status = "okay";
+		};
+		pwm_kblight: pwm@4 {
+			compatible = "cros,pwm-mock";
+			reg = <4 1>;
+			#pwm-cells = <3>;
+			status = "okay";
+		};
+	};
+
+	pwmleds {
+		compatible = "cros-ec,pwm-pin-config";
+
+		pwmled_blue_left: pwmled_b_left {
+			#led-pin-cells = <1>;
+			pwms = <&pwm_blue_left 0 1000000 PWM_POLARITY_NORMAL>;
+		};
+		pwmled_white_left: pwmled_w_left {
+			#led-pin-cells = <1>;
+			pwms = <&pwm_white_left 0 1000000 PWM_POLARITY_NORMAL>;
+		};
+		pwmled_amber_right: pwmled_y_right {
+			#led-pin-cells = <1>;
+			pwms = <&pwm_amber_right 0 1000000 PWM_POLARITY_NORMAL>;
+		};
+		pwmled_white_right: pwmled_w_right {
+			#led-pin-cells = <1>;
+			pwms = <&pwm_white_right 0 1000000 PWM_POLARITY_NORMAL>;
+		};
+	};
+
+	pwm-led-pins {
+		compatible = "cros-ec,pwm-led-pins";
+
+		color-off-left {
+			led-color = "LED_OFF";
+			led-id = "EC_LED_ID_LEFT_LED";
+			led-pins = <&pwmled_blue_left 0>,
+				   <&pwmled_white_left 0>;
+		};
+		color-off-right {
+			led-color = "LED_OFF";
+			led-id = "EC_LED_ID_RIGHT_LED";
+			led-pins = <&pwmled_amber_right 0>,
+				   <&pwmled_white_right 0>;
+		};
+		color-blue-left {
+			led-color = "LED_BLUE";
+			led-id = "EC_LED_ID_LEFT_LED";
+			br-color = "EC_LED_COLOR_BLUE";
+			led-pins = <&pwmled_blue_left 100>,
+				   <&pwmled_white_left 0>;
+		};
+		color-amber-right {
+			led-color = "LED_AMBER";
+			led-id = "EC_LED_ID_RIGHT_LED";
+			br-color = "EC_LED_COLOR_AMBER";
+			led-pins = <&pwmled_amber_right 100>,
+				   <&pwmled_white_right 0>;
+		};
+		color-white-left {
+			led-color = "LED_WHITE";
+			led-id = "EC_LED_ID_LEFT_LED";
+			br-color = "EC_LED_COLOR_WHITE";
+			led-pins = <&pwmled_blue_left 0>,
+				   <&pwmled_white_left 100>;
+		};
+		color-white-right {
+			led-color = "LED_WHITE";
+			led-id = "EC_LED_ID_RIGHT_LED";
+			br-color = "EC_LED_COLOR_WHITE";
+			led-pins = <&pwmled_amber_right 0>,
+				   <&pwmled_white_right 100>;
+		};
+	};
+
+	led-colors {
+		compatible = "cros-ec,led-policy";
+	};
+
+	kblight {
+		compatible = "cros-ec,kblight-pwm";
+		pwms = <&pwm_kblight 0 PWM_KHZ(10) PWM_POLARITY_NORMAL>;
+		generic-pwm-channel = <0>;
 	};
 };
 
@@ -787,19 +928,17 @@
 		status = "okay";
 		compatible = "zephyr,espi-emul-espi-host";
 		reg = <0x0>;
-		label = "ESPI_HOST";
 	};
 };
 
 &gpio0 {
-	ngpios = <34>;
+	ngpios = <32>;
 };
 
 &i2c0 {
 	cbi_eeprom: eeprom@56 {
 		compatible = "atmel,at24";
 		reg = <0x56>;
-		label = "EEPROM_CBI";
 		size = <512>;
 		pagesize = <8>;
 		address-width = <8>;
@@ -809,41 +948,27 @@
 	battery: sb@b {
 		compatible = "zephyr,smart-battery";
 		reg = <0xb>;
-		label = "BATTERY";
 		cycle-count = <99>;
 		version = "BATTERY_SPEC_VER_1_1_WITH_PEC";
 		/* Real battery voltages are multiples of 4.4V. */
 		desired-charg-volt = <5000>;
 		desired-charg-cur = <1000>;
+		mf-name = "LGC";
+		dev-name = "AC17A8M";
 	};
 
 	bma_emul: bma@18 {
 		compatible = "zephyr,bma255";
 		reg = <0x18>;
-		label = "BMA_EMUL";
 		error-on-compensation-not-ready;
 		error-on-ro-write;
 		error-on-reserved-bit-write;
 		error-on-msb-first-access;
 	};
 
-	pi3usb9201_emul: pi3usb9201@5f {
-		compatible = "zephyr,pi3usb9201-emul";
-		reg = <0x5f>;
-		label = "PI3USB9201_EMUL";
-	};
-
-	sn5s330_emul: sn5s330@40 {
-		compatible = "cros,sn5s330-emul";
-		reg = <0x40>;
-		label = "SN5S330_EMUL";
-		int-pin = <&gpio_usb_c0_ppc_int>;
-	};
-
 	accel_bmi260: bmi260@68 {
 		compatible = "zephyr,bmi";
 		reg = <0x68>;
-		label = "BMI260";
 		device-model = "BMI_EMUL_260";
 		error-on-ro-write;
 		error-on-wo-read;
@@ -851,11 +976,10 @@
 		simulate-command-exec-time;
 	};
 
-	ln9310: ln9310@80 {
+	ln9310: ln9310@72 {
 		compatible = "cros,ln9310-emul";
 		status = "okay";
-		reg = <0x80>;
-		label = "LN9310";
+		reg = <0x72>;
 		pg-int-pin = <&gpio_switchcap_pg_int_l>;
 	};
 
@@ -863,31 +987,22 @@
 		compatible = "cros,lis2dw12-emul";
 		status = "okay";
 		reg = <0x19>;
-		label = "LIS2DW12_EMUL";
 	};
 
 	i2c_mock: i2c_mock@84 {
 		compatible = "cros,i2c-mock";
 		status = "okay";
 		reg = <0x84>;
-		label = "I2C_MOCK";
 	};
 
 	isl923x_emul: isl923x@9 {
 		compatible = "cros,isl923x-emul";
 		status = "okay";
 		reg = <0x9>;
-		label = "ISL923X_EMUL";
 		battery = <&battery>;
 	};
 
-	tcpci_emul: tcpci_emul@82 {
-		compatible = "cros,tcpci-emul";
-		status = "okay";
-		reg = <0x82>;
-		label = "TCPCI_EMUL";
-		alert_gpio = <&usb_c0_tcpc_int_odl>;
-	};
+
 };
 
 /* Enable all thermistors for testing */
@@ -906,3 +1021,9 @@
 &thermistor_3V3_51K1_47K_4050B  {
 	status = "okay";
 };
+
+&flash0 {
+        erase-block-size = <0x10000>;
+        write-block-size = <1>;
+        reg = <0x00000000 DT_SIZE_K(512)>;
+};
diff --git a/zephyr/test/drivers/chargesplash/CMakeLists.txt b/zephyr/test/drivers/chargesplash/CMakeLists.txt
new file mode 100644
index 0000000000..f0746a4cdd
--- /dev/null
+++ b/zephyr/test/drivers/chargesplash/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Add source files
+target_sources(app PRIVATE src/chargesplash.c)
diff --git a/zephyr/test/drivers/src/chargesplash.c b/zephyr/test/drivers/chargesplash/src/chargesplash.c
index 3eec11bbe4..1b89262ce4 100644
--- a/zephyr/test/drivers/src/chargesplash.c
+++ b/zephyr/test/drivers/chargesplash/src/chargesplash.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -9,7 +9,7 @@
 #include <zephyr/shell/shell.h>
 #include <zephyr/shell/shell_uart.h>
 #include <zephyr/sys/__assert.h>
-#include <ztest.h>
+#include <zephyr/ztest.h>
 
 #include "chipset.h"
 #include "config.h"
@@ -44,35 +44,6 @@ static bool is_chargesplash_requested(void)
 	return response.requested;
 }
 
-static struct k_poll_signal shutdown_complete_signal =
-	K_POLL_SIGNAL_INITIALIZER(shutdown_complete_signal);
-static struct k_poll_event shutdown_complete_event = K_POLL_EVENT_INITIALIZER(
-	K_POLL_TYPE_SIGNAL, K_POLL_MODE_NOTIFY_ONLY, &shutdown_complete_signal);
-
-static void handle_chipset_shutdown_complete_event(void)
-{
-	k_poll_signal_raise(&shutdown_complete_signal, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN_COMPLETE,
-	     handle_chipset_shutdown_complete_event, HOOK_PRIO_LAST);
-
-static void force_chipset_off(void)
-{
-	if (!chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
-		k_poll_signal_reset(&shutdown_complete_signal);
-		chipset_force_shutdown(CHIPSET_RESET_INIT);
-		k_poll(&shutdown_complete_event, 1, K_MSEC(1000));
-	}
-
-	/*
-	 * Signal will trigger during S3->S5, but we want to wait until we're
-	 * actually at S5.  Give it a quick sleep if required.
-	 */
-	while (!chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
-		msleep(5);
-	}
-}
-
 static struct k_poll_signal s0_signal = K_POLL_SIGNAL_INITIALIZER(s0_signal);
 static struct k_poll_event s0_event = K_POLL_EVENT_INITIALIZER(
 	K_POLL_TYPE_SIGNAL, K_POLL_MODE_NOTIFY_ONLY, &s0_signal);
@@ -124,7 +95,7 @@ static void set_lid(bool open, bool inhibit_boot)
 
 	if (inhibit_boot) {
 		wait_for_chipset_startup();
-		force_chipset_off();
+		test_set_chipset_to_g3();
 	}
 }
 
@@ -136,7 +107,13 @@ static void pulse_power_button(void)
 
 static void reset_state(void *unused)
 {
-	force_chipset_off();
+	test_set_chipset_to_g3();
+
+	/*
+	 * Prevent critical low battery from moving us back to G3 when
+	 * lid is opened.
+	 */
+	test_set_battery_level(75);
 
 	if (lid_is_open()) {
 		set_lid(false, false);
@@ -213,7 +190,7 @@ ZTEST_USER(chargesplash, test_lockout)
 		wait_for_chipset_startup();
 
 		set_ac_enabled(false);
-		force_chipset_off();
+		test_set_chipset_to_g3();
 	}
 
 	set_ac_enabled(true);
@@ -260,7 +237,7 @@ ZTEST_USER(chargesplash, test_manual_lockout_via_console)
 	zassert_true(is_chargesplash_requested(),
 		     "chargesplash should be requested");
 	wait_for_chipset_startup();
-	force_chipset_off();
+	test_set_chipset_to_g3();
 
 	zassert_ok(shell_execute_cmd(get_ec_shell(), "chargesplash lockout"),
 		   NULL);
@@ -288,7 +265,7 @@ ZTEST_USER(chargesplash, test_manual_lockout_via_hostcmd)
 	zassert_true(is_chargesplash_requested(),
 		     "chargesplash should be requested");
 	wait_for_chipset_startup();
-	force_chipset_off();
+	test_set_chipset_to_g3();
 
 	zassert_ok(chargesplash_hostcmd(EC_CHARGESPLASH_LOCKOUT, &response),
 		   NULL);
diff --git a/zephyr/test/drivers/common/CMakeLists.txt b/zephyr/test/drivers/common/CMakeLists.txt
new file mode 100644
index 0000000000..854294ab11
--- /dev/null
+++ b/zephyr/test/drivers/common/CMakeLists.txt
@@ -0,0 +1,13 @@
+# Common sources
+target_sources(app PRIVATE
+  src/main.c
+  src/test_mocks.c
+  src/test_rules.c
+  src/utils.c
+  src/stubs.c
+)
+target_include_directories(app PRIVATE
+    ${CMAKE_CURRENT_SOURCE_DIR}/include
+    ${PLATFORM_EC}/driver/ppc/
+    ${PLATFORM_EC}/zephyr/shim/src/led_driver
+)
diff --git a/zephyr/test/drivers/include/test/drivers/charger_utils.h b/zephyr/test/drivers/common/include/test/drivers/charger_utils.h
index 1712a5a384..22331c8575 100644
--- a/zephyr/test/drivers/include/test/drivers/charger_utils.h
+++ b/zephyr/test/drivers/common/include/test/drivers/charger_utils.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/test/drivers/include/test/drivers/stubs.h b/zephyr/test/drivers/common/include/test/drivers/stubs.h
index 2e03142d72..98f3fa1d15 100644
--- a/zephyr/test/drivers/include/test/drivers/stubs.h
+++ b/zephyr/test/drivers/common/include/test/drivers/stubs.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,13 +6,14 @@
 #ifndef __TEST_DRIVERS_STUBS_H
 #define __TEST_DRIVERS_STUBS_H
 
-#include "fff.h"
+#include <zephyr/fff.h>
 #include "power.h"
 
 enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 /* Structure used by usb_mux test. It is part of usb_muxes chain. */
 extern struct usb_mux usbc1_virtual_usb_mux;
+extern struct usb_mux usbc0_mux0;
 
 /**
  * @brief Set product ID that should be returned by board_get_ps8xxx_product_id
@@ -24,6 +25,8 @@ void board_set_ps8xxx_product_id(uint16_t product_id);
 /* Declare fake function to allow tests to examine calls to this function */
 DECLARE_FAKE_VOID_FUNC(system_hibernate, uint32_t, uint32_t);
 
+DECLARE_FAKE_VOID_FUNC(board_reset_pd_mcu);
+
 void sys_arch_reboot(int type);
 
 /* Declare GPIO_TEST interrupt handler */
diff --git a/zephyr/test/drivers/include/test/drivers/tcpci_test_common.h b/zephyr/test/drivers/common/include/test/drivers/tcpci_test_common.h
index e39738a9d5..08d75cccf7 100644
--- a/zephyr/test/drivers/include/test/drivers/tcpci_test_common.h
+++ b/zephyr/test/drivers/common/include/test/drivers/tcpci_test_common.h
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -18,7 +18,7 @@
  */
 void check_tcpci_reg_f(const struct emul *emul, int reg, uint16_t exp_val,
 		       int line);
-#define check_tcpci_reg(emul, reg, exp_val)			\
+#define check_tcpci_reg(emul, reg, exp_val) \
 	check_tcpci_reg_f((emul), (reg), (exp_val), __LINE__)
 
 /**
@@ -32,80 +32,104 @@ void check_tcpci_reg_f(const struct emul *emul, int reg, uint16_t exp_val,
  */
 void check_tcpci_reg_with_mask_f(const struct emul *emul, int reg,
 				 uint16_t exp_val, uint16_t mask, int line);
-#define check_tcpci_reg_with_mask(emul, reg, exp_val, mask)		\
+#define check_tcpci_reg_with_mask(emul, reg, exp_val, mask) \
 	check_tcpci_reg_with_mask_f((emul), (reg), (exp_val), (mask), __LINE__)
 
 /**
  * @brief Test TCPCI init and vbus level callback
  *
  * @param emul Pointer to TCPCI emulator
+ * @param common_data Pointer to argument emul's i2c_common_emul_data
  * @param port Select USBC port that will be used to obtain tcpm_drv from
  *             tcpc_config
  */
-void test_tcpci_init(const struct emul *emul, enum usbc_port port);
+void test_tcpci_init(const struct emul *emul,
+		     struct i2c_common_emul_data *common_data,
+		     enum usbc_port port);
 
 /**
  * @brief Test TCPCI release callback
  *
  * @param emul Pointer to TCPCI emulator
+ * @param common_data Pointer to argument emul's i2c_common_emul_data
  * @param port Select USBC port that will be used to obtain tcpm_drv from
  *             tcpc_config
  */
-void test_tcpci_release(const struct emul *emul, enum usbc_port port);
+void test_tcpci_release(const struct emul *emul,
+			struct i2c_common_emul_data *common_data,
+			enum usbc_port port);
 
 /**
  * @brief Test TCPCI get cc callback
  *
  * @param emul Pointer to TCPCI emulator
+ * @param common_data Pointer to argument emul's i2c_common_emul_data
  * @param port Select USBC port that will be used to obtain tcpm_drv from
  *             tcpc_config
  */
-void test_tcpci_get_cc(const struct emul *emul, enum usbc_port port);
+void test_tcpci_get_cc(const struct emul *emul,
+		       struct i2c_common_emul_data *common_data,
+		       enum usbc_port port);
 
 /**
  * @brief Test TCPCI set cc callback
  *
  * @param emul Pointer to TCPCI emulator
+ * @param common_data Pointer to argument emul's i2c_common_emul_data
  * @param port Select USBC port that will be used to obtain tcpm_drv from
  *             tcpc_config
  */
-void test_tcpci_set_cc(const struct emul *emul, enum usbc_port port);
+void test_tcpci_set_cc(const struct emul *emul,
+		       struct i2c_common_emul_data *common_data,
+		       enum usbc_port port);
 
 /**
  * @brief Test TCPCI set polarity callback
  *
  * @param emul Pointer to TCPCI emulator
+ * @param common_data Pointer to argument emul's i2c_common_emul_data
  * @param port Select USBC port that will be used to obtain tcpm_drv from
  *             tcpc_config
  */
-void test_tcpci_set_polarity(const struct emul *emul, enum usbc_port port);
+void test_tcpci_set_polarity(const struct emul *emul,
+			     struct i2c_common_emul_data *common_data,
+			     enum usbc_port port);
 
 /**
  * @brief Test TCPCI set vconn callback
  *
  * @param emul Pointer to TCPCI emulator
+ * @param common_data Pointer to argument emul's i2c_common_emul_data
  * @param port Select USBC port that will be used to obtain tcpm_drv from
  *             tcpc_config
  */
-void test_tcpci_set_vconn(const struct emul *emul, enum usbc_port port);
+void test_tcpci_set_vconn(const struct emul *emul,
+			  struct i2c_common_emul_data *common_data,
+			  enum usbc_port port);
 
 /**
  * @brief Test TCPCI set msg header callback
  *
  * @param emul Pointer to TCPCI emulator
+ * @param common_data Pointer to argument emul's i2c_common_emul_data
  * @param port Select USBC port that will be used to obtain tcpm_drv from
  *             tcpc_config
  */
-void test_tcpci_set_msg_header(const struct emul *emul, enum usbc_port port);
+void test_tcpci_set_msg_header(const struct emul *emul,
+			       struct i2c_common_emul_data *common_data,
+			       enum usbc_port port);
 
 /**
  * @brief Test TCPCI rx and sop prime enable callback
  *
  * @param emul Pointer to TCPCI emulator
+ * @param common_data Pointer to argument emul's i2c_common_emul_data
  * @param port Select USBC port that will be used to obtain tcpm_drv from
  *             tcpc_config
  */
-void test_tcpci_set_rx_detect(const struct emul *emul, enum usbc_port port);
+void test_tcpci_set_rx_detect(const struct emul *emul,
+			      struct i2c_common_emul_data *common_data,
+			      enum usbc_port port);
 
 /**
  * @brief Test TCPCI get raw message from TCPC callback
@@ -115,78 +139,115 @@ void test_tcpci_set_rx_detect(const struct emul *emul, enum usbc_port port);
  *             tcpc_config
  */
 void test_tcpci_get_rx_message_raw(const struct emul *emul,
+				   struct i2c_common_emul_data *common_data,
 				   enum usbc_port port);
 
 /**
  * @brief Test TCPCI transmitting message from TCPC callback
  *
  * @param emul Pointer to TCPCI emulator
+ * @param common_data Pointer to argument emul's i2c_common_emul_data
  * @param port Select USBC port that will be used to obtain tcpm_drv from
  *             tcpc_config
  */
-void test_tcpci_transmit(const struct emul *emul, enum usbc_port port);
+void test_tcpci_transmit(const struct emul *emul,
+			 struct i2c_common_emul_data *common_data,
+			 enum usbc_port port);
 
 /**
  * @brief Test TCPCI alert callback
  *
  * @param emul Pointer to TCPCI emulator
+ * @param common_data Pointer to argument emul's i2c_common_emul_data
  * @param port Select USBC port that will be used to obtain tcpm_drv from
  *             tcpc_config
  */
-void test_tcpci_alert(const struct emul *emul, enum usbc_port port);
+void test_tcpci_alert(const struct emul *emul,
+		      struct i2c_common_emul_data *common_data,
+		      enum usbc_port port);
 
 /**
  * @brief Test TCPCI alert RX message callback
  *
  * @param emul Pointer to TCPCI emulator
+ * @param common_data Pointer to argument emul's i2c_common_emul_data
  * @param port Select USBC port that will be used to obtain tcpm_drv from
  *             tcpc_config
  */
-void test_tcpci_alert_rx_message(const struct emul *emul, enum usbc_port port);
+void test_tcpci_alert_rx_message(const struct emul *emul,
+				 struct i2c_common_emul_data *common_data,
+				 enum usbc_port port);
 
 /**
  * @brief Test TCPCI auto discharge on disconnect callback
  *
  * @param emul Pointer to TCPCI emulator
+ * @param common_data Pointer to argument emul's i2c_common_emul_data
  * @param port Select USBC port that will be used to obtain tcpm_drv from
  *             tcpc_config
  */
-void test_tcpci_auto_discharge(const struct emul *emul, enum usbc_port port);
+void test_tcpci_auto_discharge(const struct emul *emul,
+			       struct i2c_common_emul_data *common_data,
+			       enum usbc_port port);
 
 /**
  * @brief Test TCPCI drp toggle callback
  *
  * @param emul Pointer to TCPCI emulator
+ * @param common_data Pointer to argument emul's i2c_common_emul_data
  * @param port Select USBC port that will be used to obtain tcpm_drv from
  *             tcpc_config
  */
-void test_tcpci_drp_toggle(const struct emul *emul, enum usbc_port port);
+void test_tcpci_drp_toggle(const struct emul *emul,
+			   struct i2c_common_emul_data *common_data,
+			   enum usbc_port port);
 
 /**
  * @brief Test TCPCI get chip info callback
  *
  * @param emul Pointer to TCPCI emulator
+ * @param common_data Pointer to argument emul's i2c_common_emul_data
  * @param port Select USBC port that will be used to obtain tcpm_drv from
  *             tcpc_config
  */
-void test_tcpci_get_chip_info(const struct emul *emul, enum usbc_port port);
+void test_tcpci_get_chip_info(const struct emul *emul,
+			      struct i2c_common_emul_data *common_data,
+			      enum usbc_port port);
 
 /**
  * @brief Test TCPCI enter low power mode callback
  *
  * @param emul Pointer to TCPCI emulator
+ * @param common_data Pointer to argument emul's i2c_common_emul_data
  * @param port Select USBC port that will be used to obtain tcpm_drv from
  *             tcpc_config
  */
-void test_tcpci_low_power_mode(const struct emul *emul, enum usbc_port port);
+void test_tcpci_low_power_mode(const struct emul *emul,
+			       struct i2c_common_emul_data *common_data,
+			       enum usbc_port port);
 
 /**
  * @brief Test TCPCI set bist test mode callback
  *
  * @param emul Pointer to TCPCI emulator
+ * @param common_data Pointer to argument emul's i2c_common_emul_data
  * @param port Select USBC port that will be used to obtain tcpm_drv from
  *             tcpc_config
  */
-void test_tcpci_set_bist_mode(const struct emul *emul, enum usbc_port port);
+void test_tcpci_set_bist_mode(const struct emul *emul,
+			      struct i2c_common_emul_data *common_data,
+			      enum usbc_port port);
+
+/**
+ * @brief Test TCPCI hard reset re-init callback
+ *
+ * @param emul Pointer to TCPCI emulator
+ * @param common_data Pointer to emulated I2C bus
+ * @param port Select USBC port that will be used to obtain tcpm_drv from
+ *             tcpc_config
+ */
+void test_tcpci_hard_reset_reinit(const struct emul *emul,
+				  struct i2c_common_emul_data *common_data,
+				  enum usbc_port port);
 
 #endif /* __TCPCI_TEST_COMMON_H */
diff --git a/zephyr/test/drivers/include/test/drivers/test_mocks.h b/zephyr/test/drivers/common/include/test/drivers/test_mocks.h
index f29cce97cc..8e481edef8 100644
--- a/zephyr/test/drivers/include/test/drivers/test_mocks.h
+++ b/zephyr/test/drivers/common/include/test/drivers/test_mocks.h
@@ -1,9 +1,9 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <fff.h>
+#include <zephyr/fff.h>
 
 /*
  * Convenience macros
@@ -42,27 +42,27 @@
  * @param  EXPECTED_VAL - The 8-bit value that was supposed to be written, or
  *          `MOCK_IGNORE_VALUE` to suppress this check.
  */
-#define MOCK_ASSERT_I2C_WRITE(FAKE, CALL_NUM, EXPECTED_REG, EXPECTED_VAL)     \
-	do {                                                                  \
-		zassert_true((CALL_NUM) < FAKE##_fake.call_count,             \
-			     "Call #%d did not occur (%d I2C writes total)",  \
-			     (CALL_NUM), FAKE##_fake.call_count);             \
-		zassert_equal(                                                \
-			FAKE##_fake.arg1_history[(CALL_NUM)], (EXPECTED_REG), \
-			"Expected I2C write #%d to register 0x%02x ("         \
-			#EXPECTED_REG ") but wrote to reg 0x%02x",            \
-			(CALL_NUM), (EXPECTED_REG),                           \
-			FAKE##_fake.arg1_history[(CALL_NUM)]);                \
-		if ((EXPECTED_VAL) != MOCK_IGNORE_VALUE) {                    \
-			zassert_equal(                                        \
-				FAKE##_fake.arg2_history[(CALL_NUM)],         \
-				(EXPECTED_VAL),                               \
-				"Expected I2C write #%d to register 0x%02x (" \
-				#EXPECTED_REG ") to write 0x%02x ("           \
-				#EXPECTED_VAL ") but wrote 0x%02x",           \
-				(CALL_NUM), (EXPECTED_REG), (EXPECTED_VAL),   \
-				FAKE##_fake.arg2_history[(CALL_NUM)]);        \
-		}                                                             \
+#define MOCK_ASSERT_I2C_WRITE(FAKE, CALL_NUM, EXPECTED_REG, EXPECTED_VAL)                   \
+	do {                                                                                \
+		zassert_true((CALL_NUM) < FAKE##_fake.call_count,                           \
+			     "Call #%d did not occur (%d I2C writes total)",                \
+			     (CALL_NUM), FAKE##_fake.call_count);                           \
+		zassert_equal(                                                              \
+			FAKE##_fake.arg1_history[(CALL_NUM)], (EXPECTED_REG),               \
+			"Expected I2C write #%d to register 0x%02x (" #EXPECTED_REG         \
+			") but wrote to reg 0x%02x",                                        \
+			(CALL_NUM), (EXPECTED_REG),                                         \
+			FAKE##_fake.arg1_history[(CALL_NUM)]);                              \
+		if ((EXPECTED_VAL) != MOCK_IGNORE_VALUE) {                                  \
+			zassert_equal(                                                      \
+				FAKE##_fake.arg2_history[(CALL_NUM)],                       \
+				(EXPECTED_VAL),                                             \
+				"Expected I2C write #%d to register 0x%02x (" #EXPECTED_REG \
+				") to write 0x%02x (" #EXPECTED_VAL                         \
+				") but wrote 0x%02x",                                       \
+				(CALL_NUM), (EXPECTED_REG), (EXPECTED_VAL),                 \
+				FAKE##_fake.arg2_history[(CALL_NUM)]);                      \
+		}                                                                           \
 	} while (0)
 
 /** @brief Value to pass to MOCK_ASSERT_I2C_WRITE to ignore the actual value
@@ -81,17 +81,17 @@
  * @param  EXPECTED_REG - The register address that was supposed to be read
  *          from.
  */
-#define MOCK_ASSERT_I2C_READ(FAKE, CALL_NUM, EXPECTED_REG)                    \
-	do {                                                                  \
-		zassert_true((CALL_NUM) < FAKE##_fake.call_count,             \
-			     "Call #%d did not occur (%d I2C reads total)",   \
-			     (CALL_NUM), FAKE##_fake.call_count);             \
-		zassert_equal(                                                \
-			FAKE##_fake.arg1_history[(CALL_NUM)], (EXPECTED_REG), \
-			"Expected I2C read #%d from register 0x%02x ("        \
-			#EXPECTED_REG ") but read from reg 0x%02x",           \
-			(CALL_NUM), (EXPECTED_REG),                           \
-			FAKE##_fake.arg1_history[(CALL_NUM)]);                \
+#define MOCK_ASSERT_I2C_READ(FAKE, CALL_NUM, EXPECTED_REG)                           \
+	do {                                                                         \
+		zassert_true((CALL_NUM) < FAKE##_fake.call_count,                    \
+			     "Call #%d did not occur (%d I2C reads total)",          \
+			     (CALL_NUM), FAKE##_fake.call_count);                    \
+		zassert_equal(                                                       \
+			FAKE##_fake.arg1_history[(CALL_NUM)], (EXPECTED_REG),        \
+			"Expected I2C read #%d from register 0x%02x (" #EXPECTED_REG \
+			") but read from reg 0x%02x",                                \
+			(CALL_NUM), (EXPECTED_REG),                                  \
+			FAKE##_fake.arg1_history[(CALL_NUM)]);                       \
 	} while (0)
 
 /*
@@ -105,3 +105,10 @@ DECLARE_FAKE_VALUE_FUNC(int, init_rom_copy, int, int, int);
 
 /* Mocks for common/system.c */
 DECLARE_FAKE_VALUE_FUNC(int, system_jumped_late);
+DECLARE_FAKE_VALUE_FUNC(int, system_is_locked);
+DECLARE_FAKE_VOID_FUNC(system_reset, int);
+DECLARE_FAKE_VOID_FUNC(software_panic, uint32_t, uint32_t);
+DECLARE_FAKE_VOID_FUNC(assert_post_action, const char *, unsigned int);
+
+/* Mocks for common/lid_angle.c */
+DECLARE_FAKE_VOID_FUNC(lid_angle_peripheral_enable, int);
diff --git a/zephyr/test/drivers/include/test/drivers/test_state.h b/zephyr/test/drivers/common/include/test/drivers/test_state.h
index fe8b3e8ffc..bea56224fc 100644
--- a/zephyr/test/drivers/include/test/drivers/test_state.h
+++ b/zephyr/test/drivers/common/include/test/drivers/test_state.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
diff --git a/zephyr/test/drivers/include/test/drivers/utils.h b/zephyr/test/drivers/common/include/test/drivers/utils.h
index 17ea860dfd..306f2894d4 100644
--- a/zephyr/test/drivers/include/test/drivers/utils.h
+++ b/zephyr/test/drivers/common/include/test/drivers/utils.h
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -8,123 +8,100 @@
 
 #include <zephyr/drivers/emul.h>
 #include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/ztest.h>
+#include <stddef.h>
 #include <string.h>
 
 #include "charger.h"
+#include "lpc.h"
 #include "emul/tcpc/emul_tcpci_partner_src.h"
 #include "extpower.h"
 #include "host_command.h"
-
-/** @brief Set chipset to S0 state. Call all necessary hooks. */
-void test_set_chipset_to_s0(void);
-
-/** @brief Set chipset to G3 state. Call all necessary hooks. */
-void test_set_chipset_to_g3(void);
-
-/*
- * TODO(b/217755888): Implement ztest assume API upstream
- */
+#include "power.h"
+#include "usbc/utils.h"
 
 /**
- * @brief Assume that this function call won't be reached
- * @param msg Optional message to print if the assumption fails
- */
-#define zassume_unreachable(msg, ...) zassert_unreachable(msg, ##__VA_ARGS__)
-
-/**
- * @brief Assume that @a cond is true
- * @param cond Condition to check
- * @param msg Optional message to print if the assumption fails
- */
-#define zassume_true(cond, msg, ...) zassert_true(cond, msg, ##__VA_ARGS__)
-
-/**
- * @brief Assume that @a cond is false
- * @param cond Condition to check
- * @param msg Optional message to print if the assumption fails
+ * @brief Helper macro for EMUL_GET_USBC_BINDING. If @p usbc_id has the same
+ *        port number as @p port, then struct emul* for @p chip phandle is
+ *        returned.
+ *
+ * @param usbc_id Named usbc port ID
+ * @param port Port number to match with named usbc port
+ * @param chip Name of chip phandle property
  */
-#define zassume_false(cond, msg, ...) zassert_false(cond, msg, ##__VA_ARGS__)
+#define EMUL_GET_USBC_BINDING_IF_PORT_MATCH(usbc_id, port, chip) \
+	COND_CODE_1(IS_EQ(USBC_PORT_NEW(usbc_id), port),         \
+		    (EMUL_DT_GET(DT_PHANDLE(usbc_id, chip))), ())
 
 /**
- * @brief Assume that @a cond is 0 (success)
- * @param cond Condition to check
- * @param msg Optional message to print if the assumption fails
+ * @brief Get struct emul from phandle @p chip property of USBC @p port
+ *
+ * @param port Named usbc port number. The value has to be integer literal.
+ * @param chip Name of chip property that is phandle to required emulator.
  */
-#define zassume_ok(cond, msg, ...) zassert_ok(cond, msg, ##__VA_ARGS__)
+#define EMUL_GET_USBC_BINDING(port, chip)                                 \
+	DT_FOREACH_STATUS_OKAY_VARGS(named_usbc_port,                     \
+				     EMUL_GET_USBC_BINDING_IF_PORT_MATCH, \
+				     port, chip)
 
-/**
- * @brief Assume that @a ptr is NULL
- * @param ptr Pointer to compare
- * @param msg Optional message to print if the assumption fails
- */
-#define zassume_is_null(ptr, msg, ...) zassert_is_null(ptr, msg, ##__VA_ARGS__)
+/** @brief Set emulated battery level. Call all necessary hooks. */
+void test_set_battery_level(int percentage);
 
-/**
- * @brief Assume that @a ptr is not NULL
- * @param ptr Pointer to compare
- * @param msg Optional message to print if the assumption fails
- */
-#define zassume_not_null(ptr, msg, ...) \
-	zassert_not_null(ptr, msg, ##__VA_ARGS__)
+/** @brief Set chipset to S0 state. Call all necessary hooks. */
+void test_set_chipset_to_s0(void);
 
 /**
- * @brief Assume that @a a equals @a b
+ * @brief Set the chipset to any stable state. Call all necessary hooks.
  *
- * @a a and @a b won't be converted and will be compared directly.
+ * Supported states are:
+ * <ul>
+ *   <li>POWER_G3 (same as calling test_set_chipset_to_g3())</li>
+ *   <li>POWER_S5</li>
+ *   <li>POWER_S4</li>
+ *   <li>POWER_S3</li>
+ *   <li>POWER_S0 (same as calling test_set_chipset_to_s0()</li>
+ *   <li>POWER_S0ix (if either CONFIG_PLATFORM_EC_POWERSEQ_S0IX or
+ *       CONFIG_AP_PWRSEQ_S0IX are enabled)</li>
+ * </ul>
  *
- * @param a Value to compare
- * @param b Value to compare
- * @param msg Optional message to print if the assumption fails
+ * @param new_state The new state. Must be a steady state (see above).
  */
-#define zassume_equal(a, b, msg, ...) zassert_equal(a, b, msg, ##__VA_ARGS__)
+void test_set_chipset_to_power_level(enum power_state new_state);
 
-/**
- * @brief Assume that @a a does not equal @a b
- *
- * @a a and @a b won't be converted and will be compared directly.
- *
- * @param a Value to compare
- * @param b Value to compare
- * @param msg Optional message to print if the assumption fails
+/** @brief Set chipset to G3 state. Call all necessary hooks. */
+void test_set_chipset_to_g3(void);
+
+/*
+ * TODO(b/217755888): Implement ztest assume API upstream
  */
-#define zassume_not_equal(a, b, msg, ...) \
-	zassert_not_equal(a, b, msg, ##__VA_ARGS__)
 
 /**
- * @brief Assume that @a a equals @a b
- *
- * @a a and @a b will be converted to `void *` before comparing.
- *
- * @param a Value to compare
- * @param b Value to compare
+ * @brief Assume that this function call won't be reached
  * @param msg Optional message to print if the assumption fails
  */
-#define zassume_equal_ptr(a, b, msg, ...) \
-	zassert_equal_ptr(a, b, msg, ##__VA_ARGS__)
+#define zassume_unreachable(msg, ...) zassert_unreachable(msg, ##__VA_ARGS__)
 
 /**
- * @brief Assume that @a a is within @a b with delta @a d
+ * Run an ACPI read to the specified address.
  *
- * @param a Value to compare
- * @param b Value to compare
- * @param d Delta
- * @param msg Optional message to print if the assumption fails
+ * This function assumes a successful ACPI read process and will make a
+ * call to the zassume_* API. A failure here will skip the calling test.
+ *
+ * @param acpi_addr Address to query
+ * @return Byte read
  */
-#define zassume_within(a, b, d, msg, ...) \
-	zassert_within(a, b, d, msg, ##__VA_ARGS__)
+uint8_t acpi_read(uint8_t acpi_addr);
 
 /**
- * @brief Assume that 2 memory buffers have the same contents
+ * Run an ACPI write to the specified address.
  *
- * This macro calls the final memory comparison assumption macro.
- * Using double expansion allows providing some arguments by macros that
- * would expand to more than one values (ANSI-C99 defines that all the macro
- * arguments have to be expanded before macro call).
+ * This function assumes a successful ACPI write process and will make a
+ * call to the zassume_* API. A failure here will skip the calling test.
  *
- * @param ... Arguments, see @ref zassume_mem_equal__
- *            for real arguments accepted.
+ * @param acpi_addr Address to write
+ * @param write_byte Byte to write to address
  */
-#define zassume_mem_equal(...) zassert_mem_equal(##__VA_ARGS__)
+void acpi_write(uint8_t acpi_addr, uint8_t write_byte);
 
 /**
  * Run the host command to get the charge state for a given charger number.
@@ -207,16 +184,40 @@ host_cmd_usb_pd_control(int port, enum usb_pd_control_swap swap)
 }
 
 /**
- * Run the host command to get the charge state.
+ * Run the host command to suspend/resume PD ports
+ *
+ * This function assumes a successful host command processing and will make a
+ * call to the zassume_* API. A failure here will skip the calling test.
+ *
+ * @param port The USB port to operate on
+ * @param cmd The sub-command to run
+ */
+static inline void host_cmd_pd_control(int port, enum ec_pd_control_cmd cmd)
+{
+	struct ec_params_pd_control params = { .chip = port, .subcmd = cmd };
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_PARAMS(EC_CMD_PD_CONTROL, 0, params);
+
+	zassume_ok(host_command_process(&args),
+		   "Failed to process pd_control for port %d, cmd %d", port,
+		   cmd);
+}
+
+/**
+ * Run the host command to control or query the charge state
  *
  * @return The result of the query.
  */
 static inline struct ec_response_charge_control
-host_cmd_get_charge_control(void)
+host_cmd_charge_control(enum ec_charge_control_mode mode,
+			enum ec_charge_control_cmd cmd)
 {
-	struct ec_params_charge_control params = {
-		.cmd = EC_CHARGE_CONTROL_CMD_GET
-	};
+	struct ec_params_charge_control params = { .cmd = cmd,
+						   .mode = mode,
+						   .sustain_soc = {
+							   .lower = -1,
+							   .upper = -1,
+						   } };
 	struct ec_response_charge_control response;
 	struct host_cmd_handler_args args =
 		BUILD_HOST_COMMAND(EC_CMD_CHARGE_CONTROL, 2, response, params);
@@ -228,6 +229,17 @@ host_cmd_get_charge_control(void)
 }
 
 /**
+ * @brief Call the host command HOST_EVENT with the user supplied action.
+ *
+ * @param action    - HOST_EVENT action parameter.
+ * @param mask_type - Event mask type to apply to the HOST_EVENT action.
+ * @param r         - Pointer to the response object to fill.
+ */
+enum ec_status host_cmd_host_event(enum ec_host_event_action action,
+				   enum ec_host_event_mask_type mask_type,
+				   struct ec_response_host_event *r);
+
+/**
  * @brief Call the host command MOTION_SENSE with the dump sub-command
  *
  * Note: this function uses the zassume_ API. It will skip the test if the host
@@ -431,9 +443,79 @@ int host_cmd_motion_sense_spoof(uint8_t sensor_num, uint8_t enable,
  */
 void host_cmd_typec_discovery(int port, enum typec_partner_type partner_type,
 			      void *response, size_t response_size);
+/**
+ * @brief Run the host command to get the PD alternative mode response.
+ *
+ * @param port          The USB-C port number
+ * @param response      Destination for command response.
+ * @param response_size Destination of response size from request params.
+ */
+void host_cmd_usb_pd_get_amode(
+	uint8_t port, uint16_t svid_idx,
+	struct ec_params_usb_pd_get_mode_response *response,
+	int *response_size);
+
+/**
+ * Run the host command to control PD port behavior, with the sub-command of
+ * TYPEC_CONTROL_COMMAND_ENTER_MODE
+ *
+ * @param port	The USB-C port number
+ * @param mode	Mode to enter
+ */
+void host_cmd_typec_control_enter_mode(int port, enum typec_mode mode);
+
+/**
+ * Run the host command to control PD port behavior, with the sub-command of
+ * TYPEC_CONTROL_COMMAND_EXIT_MODES
+ *
+ * @param port      The USB-C port number
+ */
+void host_cmd_typec_control_exit_modes(int port);
+
+/**
+ * Run the host command to control PD port behavior, with the sub-command of
+ * TYPEC_CONTROL_COMMAND_USB_MUX_SET
+ *
+ * @param port		The USB-C port number
+ * @param mux_set	Mode and mux index to set
+ */
+void host_cmd_typec_control_usb_mux_set(int port,
+					struct typec_usb_mux_set mux_set);
+
+/**
+ * Run the host command to control PD port behavior, with the sub-command of
+ * TYPEC_CONTROL_COMMAND_CLEAR_EVENTS
+ *
+ * @param port		The USB-C port number
+ * @param events	Events to clear for the port (see PD_STATUS_EVENT_*
+ *			definitions for options)
+ */
+void host_cmd_typec_control_clear_events(int port, uint32_t events);
+
+struct host_events_ctx {
+	host_event_t lpc_host_events;
+	host_event_t lpc_host_event_mask[LPC_HOST_EVENT_COUNT];
+};
+
+/**
+ * Save all host events. This should be run as part of the "before" action for
+ * any test suite that manipulates the host events.
+ *
+ * @param host_events_ctx	Caller allocated storage to save the host
+ *				events.
+ */
+void host_events_save(struct host_events_ctx *host_events_ctx);
+
+/**
+ * Restore all host events. This should be run as part of the "after" action for
+ * any test suite that manipulates the host events.
+ *
+ * @param host_events_ctx	Saved host events context information.
+ */
+void host_events_restore(struct host_events_ctx *host_events_ctx);
 
 #define GPIO_ACOK_OD_NODE DT_NODELABEL(gpio_acok_od)
-#define GPIO_ACOK_OD_PIN  DT_GPIO_PIN(GPIO_ACOK_OD_NODE, gpios)
+#define GPIO_ACOK_OD_PIN DT_GPIO_PIN(GPIO_ACOK_OD_NODE, gpios)
 
 /**
  * Set whether or not AC is enabled.
@@ -486,6 +568,26 @@ void disconnect_source_from_port(const struct emul *tcpci_emul,
 				 const struct emul *charger_emul);
 
 /**
+ * @brief Connect a power sink to a given port.
+ *
+ * Note: this is function currently only supports an ISL923X charger chip.
+ *
+ * @param partner Pointer to the emulated TCPCI partner device
+ * @param tcpci_emul The TCPCI emulator that the source will connect to
+ * @param charger_emul The charger chip emulator
+ */
+void connect_sink_to_port(struct tcpci_partner_data *partner,
+			  const struct emul *tcpci_emul,
+			  const struct emul *charger_emul);
+
+/**
+ * @brief Disconnect a power sink from a given port.
+ *
+ * @param tcpci_emul The TCPCI emulator that will be disconnected
+ */
+void disconnect_sink_from_port(const struct emul *tcpci_emul);
+
+/**
  * @brief Allocate memory for a test pourpose
  *
  * @param bytes Number of bytes to allocate
@@ -501,4 +603,21 @@ void *test_malloc(size_t bytes);
  */
 void test_free(void *mem);
 
+/**
+ * @brief Force the chipset to state G3 and then transition to S3 and finally
+ * S5.
+ *
+ */
+void test_set_chipset_to_g3_then_transition_to_s5(void);
+
+/**
+ * @brief Checks console command with expected console output and expected
+ * return value
+ *
+ */
+#define CHECK_CONSOLE_CMD(cmd, expected_output, expected_rv)                 \
+	check_console_cmd((cmd), (expected_output), (expected_rv), __FILE__, \
+			  __LINE__)
+void check_console_cmd(const char *cmd, const char *expected_output,
+		       const int expected_rv, const char *file, const int line);
 #endif /* ZEPHYR_TEST_DRIVERS_INCLUDE_UTILS_H_ */
diff --git a/zephyr/test/drivers/common/src/main.c b/zephyr/test/drivers/common/src/main.c
new file mode 100644
index 0000000000..1c8497ab3f
--- /dev/null
+++ b/zephyr/test/drivers/common/src/main.c
@@ -0,0 +1,63 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+#include "ec_app_main.h"
+#include "hooks.h"
+#include "test/drivers/test_state.h"
+
+/**
+ * @brief Semaphore that signals when hooks have completed
+ */
+static struct k_sem init_hooks_completed;
+
+/**
+ * @brief Hook callback function. Gets registered with the lowest priority so
+ *        that we know all actual hooks have finished. Increments the semaphore.
+ */
+static void hook_completed_callback(void)
+{
+	/* Signal that hooks are completed */
+	k_sem_give(&init_hooks_completed);
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, hook_completed_callback, HOOK_PRIO_LAST);
+
+bool drivers_predicate_pre_main(const void *state)
+{
+	return ((struct test_state *)state)->ec_app_main_run == false;
+}
+
+bool drivers_predicate_post_main(const void *state)
+{
+	return !drivers_predicate_pre_main(state);
+}
+
+void test_main(void)
+{
+	k_sem_init(&init_hooks_completed, 0, 1);
+
+	struct test_state state = {
+		.ec_app_main_run = false,
+	};
+
+	/* Run all the suites that depend on main not being called yet */
+	ztest_run_all(&state);
+
+	ec_app_main();
+	state.ec_app_main_run = true;
+
+/* Delay the post-main tests until hooks finish. Allow a generous
+ * timeout before failing. Tests with mocked power states interfere
+ * with this mechanism, so proceed normally in this case.
+ */
+#if !IS_ENABLED(CONFIG_POWER_SEQUENCE_MOCK)
+	zassert_ok(k_sem_take(&init_hooks_completed, K_SECONDS(10)),
+		   "Timed out waiting for hooks to finish");
+#endif /* !IS_ENABLED(CONFIG_POWER_SEQUENCE_MOCK) */
+
+	/* Run all the suites that depend on main being called */
+	ztest_run_all(&state);
+}
diff --git a/zephyr/test/drivers/src/stubs.c b/zephyr/test/drivers/common/src/stubs.c
index 84ae387fb4..2683b326a8 100644
--- a/zephyr/test/drivers/src/stubs.c
+++ b/zephyr/test/drivers/common/src/stubs.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,7 +11,7 @@
 #include "charger/isl923x_public.h"
 #include "charger/isl9241_public.h"
 #include "config.h"
-#include "fff.h"
+#include <zephyr/fff.h>
 #include "gpio/gpio_int.h"
 #include "hooks.h"
 #include "i2c/i2c.h"
@@ -30,8 +30,8 @@
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(stubs);
 
-#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
 
 /* All of these definitions are just to get the test to link. None of these
  * functions are useful or behave as they should. Please remove them once the
@@ -55,8 +55,7 @@ BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
 
 int board_set_active_charge_port(int port)
 {
-	int is_real_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
 	int i;
 
 	if (!is_real_port && port != CHARGE_PORT_NONE)
@@ -84,7 +83,6 @@ int board_set_active_charge_port(int port)
 		return EC_ERROR_INVAL;
 	}
 
-
 	CPRINTS("New charge port: p%d", port);
 
 	/*
@@ -117,29 +115,9 @@ void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
 			    int charge_mv)
 {
 	charge_set_input_current_limit(
-	MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+		MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
 }
 
-struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C0,
-			.addr_flags = DT_REG_ADDR(DT_NODELABEL(tcpci_emul)),
-		},
-		.drv = &tcpci_tcpm_drv,
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USB_C1,
-			.addr_flags = DT_REG_ADDR(DT_NODELABEL(
-							tcpci_ps8xxx_emul)),
-		},
-		.drv = &ps8xxx_tcpm_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
 BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
 
 static uint16_t ps8xxx_product_id = PS8805_PRODUCT_ID;
@@ -170,10 +148,14 @@ int board_is_sourcing_vbus(int port)
 	return ppc_is_sourcing_vbus(port);
 }
 
-struct usb_mux usbc0_virtual_usb_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &virtual_usb_mux_driver,
-	.hpd_update = &virtual_hpd_update,
+/* TODO(b/239457738): Move to dts */
+struct usb_mux_chain usbc0_virtual_usb_mux_chain = {
+	.mux =
+		&(const struct usb_mux){
+			.usb_port = USBC_PORT_C0,
+			.driver = &virtual_usb_mux_driver,
+			.hpd_update = &virtual_hpd_update,
+		},
 };
 
 struct usb_mux usbc1_virtual_usb_mux = {
@@ -182,22 +164,32 @@ struct usb_mux usbc1_virtual_usb_mux = {
 	.hpd_update = &virtual_hpd_update,
 };
 
-struct usb_mux usb_muxes[] = {
+struct usb_mux_chain usbc1_virtual_usb_mux_chain = {
+	.mux = &usbc1_virtual_usb_mux,
+};
+
+struct usb_mux usbc0_mux0 = {
+	.usb_port = USBC_PORT_C0,
+	.driver = &tcpci_tcpm_usb_mux_driver,
+	.i2c_port = I2C_PORT_USB_C0,
+	.i2c_addr_flags = DT_REG_ADDR(DT_NODELABEL(tcpci_emul)),
+};
+
+struct usb_mux_chain usb_muxes[] = {
 	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.driver = &tcpci_tcpm_usb_mux_driver,
-		.next_mux = &usbc0_virtual_usb_mux,
-		.i2c_port = I2C_PORT_USB_C0,
-		.i2c_addr_flags = DT_REG_ADDR(DT_NODELABEL(tcpci_emul)),
+		.mux = &usbc0_mux0,
+		.next = &usbc0_virtual_usb_mux_chain,
 	},
 	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.driver = &bb_usb_retimer,
-		.hpd_update = bb_retimer_hpd_update,
-		.next_mux = &usbc1_virtual_usb_mux,
-		.i2c_port = I2C_PORT_USB_C1,
-		.i2c_addr_flags = DT_REG_ADDR(DT_NODELABEL(
-					usb_c1_bb_retimer_emul)),
+		.mux = &(const struct usb_mux){
+			.usb_port = USBC_PORT_C1,
+			.driver = &bb_usb_retimer,
+			.hpd_update = bb_retimer_hpd_update,
+			.i2c_port = I2C_PORT_USB_C1,
+			.i2c_addr_flags = DT_REG_ADDR(DT_NODELABEL(
+						usb_c1_bb_retimer_emul)),
+		},
+		.next = &usbc1_virtual_usb_mux_chain,
 	},
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
@@ -247,6 +239,8 @@ unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
 
 DEFINE_FAKE_VOID_FUNC(system_hibernate, uint32_t, uint32_t);
 
+DEFINE_FAKE_VOID_FUNC(board_reset_pd_mcu);
+
 uint16_t tcpc_get_alert_status(void)
 {
 	uint16_t status = 0;
@@ -257,13 +251,13 @@ uint16_t tcpc_get_alert_status(void)
 	 */
 	if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(usb_c0_tcpc_int_odl))) {
 		if (gpio_pin_get_dt(
-		GPIO_DT_FROM_NODELABEL(usb_c0_tcpc_rst_l)) != 0)
+			    GPIO_DT_FROM_NODELABEL(usb_c0_tcpc_rst_l)) != 0)
 			status |= PD_STATUS_TCPC_ALERT_0;
 	}
 
 	if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(usb_c1_tcpc_int_odl))) {
 		if (gpio_pin_get_dt(
-		GPIO_DT_FROM_NODELABEL(usb_c1_tcpc_rst_l)) != 0)
+			    GPIO_DT_FROM_NODELABEL(usb_c1_tcpc_rst_l)) != 0)
 			status |= PD_STATUS_TCPC_ALERT_1;
 	}
 
diff --git a/zephyr/test/drivers/src/test_mocks.c b/zephyr/test/drivers/common/src/test_mocks.c
index f8bbb1a6c1..11887f7cb9 100644
--- a/zephyr/test/drivers/src/test_mocks.c
+++ b/zephyr/test/drivers/common/src/test_mocks.c
@@ -1,9 +1,9 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <ztest.h>
+#include <zephyr/ztest.h>
 
 #include "test/drivers/test_mocks.h"
 
@@ -16,6 +16,13 @@ DEFINE_FAKE_VALUE_FUNC(int, init_rom_copy, int, int, int);
 
 /* Mocks for common/system.c */
 DEFINE_FAKE_VALUE_FUNC(int, system_jumped_late);
+DEFINE_FAKE_VALUE_FUNC(int, system_is_locked);
+DEFINE_FAKE_VOID_FUNC(system_reset, int);
+DEFINE_FAKE_VOID_FUNC(software_panic, uint32_t, uint32_t);
+DEFINE_FAKE_VOID_FUNC(assert_post_action, const char *, unsigned int);
+
+/* Mocks for common/lid_angle.c */
+DEFINE_FAKE_VOID_FUNC(lid_angle_peripheral_enable, int);
 
 /**
  * @brief Reset all the fakes before each test.
@@ -30,6 +37,10 @@ static void fff_reset_rule_before(const struct ztest_unit_test *test,
 	RESET_FAKE(init_rom_unmap);
 	RESET_FAKE(init_rom_copy);
 	RESET_FAKE(system_jumped_late);
+	RESET_FAKE(system_reset);
+	RESET_FAKE(software_panic);
+	RESET_FAKE(assert_post_action);
+	RESET_FAKE(lid_angle_peripheral_enable);
 }
 
 ZTEST_RULE(fff_reset_rule, fff_reset_rule_before, NULL);
diff --git a/zephyr/test/drivers/common/src/test_rules.c b/zephyr/test/drivers/common/src/test_rules.c
new file mode 100644
index 0000000000..e1b1d59480
--- /dev/null
+++ b/zephyr/test/drivers/common/src/test_rules.c
@@ -0,0 +1,38 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/ztest.h>
+
+#include "emul/tcpc/emul_tcpci.h"
+#include "motion_sense_fifo.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/utils.h"
+#include "usb_pd_tcpm.h"
+
+static void motion_sense_fifo_reset_before(const struct ztest_unit_test *test,
+					   void *data)
+{
+	ARG_UNUSED(test);
+	ARG_UNUSED(data);
+	motion_sense_fifo_reset();
+}
+ZTEST_RULE(motion_sense_fifo_reset, motion_sense_fifo_reset_before, NULL);
+
+static void tcpci_revision_reset_before(const struct ztest_unit_test *test,
+					void *data)
+{
+	ARG_UNUSED(test);
+	ARG_UNUSED(data);
+	const struct emul *tcpc_c0_emul = EMUL_GET_USBC_BINDING(0, tcpc);
+	const struct emul *tcpc_c1_emul = EMUL_GET_USBC_BINDING(1, tcpc);
+
+	/* Set TCPCI to revision 2 for both emulators */
+	tcpc_config[USBC_PORT_C0].flags |= TCPC_FLAGS_TCPCI_REV2_0;
+	tcpci_emul_set_rev(tcpc_c0_emul, TCPCI_EMUL_REV2_0_VER1_1);
+
+	tcpc_config[USBC_PORT_C1].flags |= TCPC_FLAGS_TCPCI_REV2_0;
+	tcpci_emul_set_rev(tcpc_c1_emul, TCPCI_EMUL_REV2_0_VER1_1);
+}
+ZTEST_RULE(tcpci_revision_reset, tcpci_revision_reset_before, NULL);
diff --git a/zephyr/test/drivers/src/utils.c b/zephyr/test/drivers/common/src/utils.c
index 5ba78043b1..f083300886 100644
--- a/zephyr/test/drivers/src/utils.c
+++ b/zephyr/test/drivers/common/src/utils.c
@@ -1,47 +1,45 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <zephyr/zephyr.h>
-#include <ztest.h>
-#include <zephyr/shell/shell_uart.h>
 #include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/shell/shell.h>
+#include <zephyr/shell/shell_dummy.h> /* nocheck */
+#include <zephyr/shell/shell_uart.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
 
+#include "acpi.h"
 #include "battery.h"
 #include "battery_smart.h"
+#include "charge_state.h"
+#include "chipset.h"
+#include "lpc.h"
 #include "emul/emul_isl923x.h"
 #include "emul/emul_smart_battery.h"
+#include "emul/emul_stub_device.h"
 #include "emul/tcpc/emul_tcpci_partner_src.h"
 #include "hooks.h"
 #include "power.h"
+#include "task.h"
+#include "tcpm/tcpci.h"
 #include "test/drivers/stubs.h"
-#include "chipset.h"
 #include "test/drivers/utils.h"
 
-#define BATTERY_ORD DT_DEP_ORD(DT_NODELABEL(battery))
+#define BATTERY_NODE DT_NODELABEL(battery)
 #define GPIO_BATT_PRES_ODL_PATH DT_PATH(named_gpios, ec_batt_pres_odl)
 #define GPIO_BATT_PRES_ODL_PORT DT_GPIO_PIN(GPIO_BATT_PRES_ODL_PATH, gpios)
 
-void test_set_chipset_to_s0(void)
+void test_set_battery_level(int percentage)
 {
 	struct sbat_emul_bat_data *bat;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BATTERY_NODE);
 	const struct device *battery_gpio_dev =
 		DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_BATT_PRES_ODL_PATH, gpios));
-
-	printk("%s: Forcing power on\n", __func__);
-	emul = sbat_emul_get_ptr(BATTERY_ORD);
 	bat = sbat_emul_get_bat_data(emul);
 
-	/*
-	 * Make sure that battery is in good condition to
-	 * not trigger hibernate in charge_state_v2.c
-	 * Set battery voltage to expected value and capacity to 75%. Battery
-	 * will not be full and accepts charging, but will not trigger
-	 * hibernate. Charge level is chosen arbitrary.
-	 */
-	bat->cap = bat->full_cap * 3 / 4;
+	bat->cap = bat->full_cap * percentage / 100;
 	bat->volt = battery_get_info()->voltage_normal;
 	bat->design_mv = bat->volt;
 
@@ -50,6 +48,28 @@ void test_set_chipset_to_s0(void)
 				       GPIO_BATT_PRES_ODL_PORT, 0),
 		   NULL);
 
+	/* We need to wait for the charge task to re-read battery parameters */
+	WAIT_FOR(!charge_want_shutdown(), CHARGE_MAX_SLEEP_USEC + 1,
+		 k_sleep(K_SECONDS(1)));
+}
+
+void test_set_chipset_to_s0(void)
+{
+	printk("%s: Forcing power on\n", __func__);
+
+	task_wake(TASK_ID_CHIPSET);
+	k_sleep(K_SECONDS(1));
+
+	/*
+	 * Make sure that battery is in good condition to
+	 * not trigger hibernate in charge_state_v2.c
+	 * Set battery voltage to expected value and capacity to 50%. Battery
+	 * will not be full and accepts charging, but will not trigger
+	 * hibernate. Charge level is set to the default value of an emulator
+	 * (emul/emul_smart_battery.c). b/244366201.
+	 */
+	test_set_battery_level(50);
+
 	/* The easiest way to power on seems to be the shell command. */
 	zassert_equal(EC_SUCCESS, shell_execute_cmd(get_ec_shell(), "power on"),
 		      NULL);
@@ -61,8 +81,41 @@ void test_set_chipset_to_s0(void)
 		      power_get_state());
 }
 
+void test_set_chipset_to_power_level(enum power_state new_state)
+{
+	zassert_true(new_state == POWER_G3 || new_state == POWER_S5 ||
+			     new_state == POWER_S4 || new_state == POWER_S3 ||
+			     new_state == POWER_S0
+#ifdef CONFIG_POWER_S0IX
+			     || new_state == POWER_S0ix
+#endif
+		     ,
+		     "Power state must be one of the steady states");
+	task_wake(TASK_ID_CHIPSET);
+	k_sleep(K_SECONDS(1));
+
+	if (new_state == POWER_G3) {
+		test_set_chipset_to_g3();
+		return;
+	}
+
+	test_set_chipset_to_s0();
+
+	power_set_state(new_state);
+
+	k_sleep(K_SECONDS(1));
+
+	/* Check if chipset is in correct state */
+	zassert_equal(new_state, power_get_state(), "Expected %d, got %d",
+		      new_state, power_get_state());
+}
+
 void test_set_chipset_to_g3(void)
 {
+	/* Let power code to settle on a particular state first. */
+	task_wake(TASK_ID_CHIPSET);
+	k_sleep(K_SECONDS(1));
+
 	printk("%s: Forcing shutdown\n", __func__);
 	chipset_force_shutdown(CHIPSET_RESET_KB_SYSRESET);
 	k_sleep(K_SECONDS(20));
@@ -94,6 +147,94 @@ void disconnect_source_from_port(const struct emul *tcpci_emul,
 	k_sleep(K_SECONDS(1));
 }
 
+void connect_sink_to_port(struct tcpci_partner_data *partner,
+			  const struct emul *tcpci_emul,
+			  const struct emul *charger_emul)
+{
+	/*
+	 * TODO(b/221439302) Updating the TCPCI emulator registers, updating the
+	 *   vbus, as well as alerting should all be a part of the connect
+	 *   function.
+	 */
+	/* Enforce that we only support the isl923x emulator for now */
+	__ASSERT_NO_MSG(EMUL_DT_GET(DT_NODELABEL(isl923x_emul)) ==
+			charger_emul);
+	isl923x_emul_set_adc_vbus(charger_emul, 0);
+	tcpci_emul_set_reg(tcpci_emul, TCPC_REG_POWER_STATUS,
+			   TCPC_REG_POWER_STATUS_VBUS_DET);
+	tcpci_emul_set_reg(tcpci_emul, TCPC_REG_EXT_STATUS,
+			   TCPC_REG_EXT_STATUS_SAFE0V);
+
+	tcpci_tcpc_alert(0);
+	k_sleep(K_SECONDS(1));
+
+	zassume_ok(tcpci_partner_connect_to_tcpci(partner, tcpci_emul), NULL);
+
+	/* Wait for PD negotiation and current ramp.
+	 * TODO(b/213906889): Check message timing and contents.
+	 */
+	k_sleep(K_SECONDS(10));
+}
+
+void disconnect_sink_from_port(const struct emul *tcpci_emul)
+{
+	zassume_ok(tcpci_emul_disconnect_partner(tcpci_emul), NULL);
+	k_sleep(K_SECONDS(1));
+}
+
+uint8_t acpi_read(uint8_t acpi_addr)
+{
+	uint8_t readval;
+	/*
+	 * See ec_commands.h for details on the required process
+	 * First, send the read command, which should populate no data
+	 */
+	zassume_ok(acpi_ap_to_ec(true, EC_CMD_ACPI_READ, &readval),
+		   "Failed to send read command");
+
+	/* Next, time for the address which should populate our result */
+	zassume_equal(acpi_ap_to_ec(false, acpi_addr, &readval), 1,
+		      "Failed to read value");
+	return readval;
+}
+
+void acpi_write(uint8_t acpi_addr, uint8_t write_byte)
+{
+	uint8_t readval;
+	/*
+	 * See ec_commands.h for details on the required process
+	 * First, send the read command, which should populate no data
+	 */
+	zassume_ok(acpi_ap_to_ec(true, EC_CMD_ACPI_WRITE, &readval),
+		   "Failed to send read command");
+
+	/* Next, time for the address we want to write */
+	zassume_ok(acpi_ap_to_ec(false, acpi_addr, &readval),
+		   "Failed to write address");
+
+	/* Finally, time to write the data */
+	zassume_ok(acpi_ap_to_ec(false, write_byte, &readval),
+		   "Failed to write value");
+}
+
+enum ec_status host_cmd_host_event(enum ec_host_event_action action,
+				   enum ec_host_event_mask_type mask_type,
+				   struct ec_response_host_event *r)
+{
+	enum ec_status ret_val;
+
+	struct ec_params_host_event params = {
+		.action = action,
+		.mask_type = mask_type,
+	};
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_HOST_EVENT, 0, *r, params);
+
+	ret_val = host_command_process(&args);
+
+	return ret_val;
+}
+
 void host_cmd_motion_sense_dump(int max_sensor_count,
 				struct ec_response_motion_sense *response)
 {
@@ -340,6 +481,98 @@ void host_cmd_typec_discovery(int port, enum typec_partner_type partner_type,
 		   "Failed to get Type-C state for port %d", port);
 }
 
+void host_cmd_typec_control_enter_mode(int port, enum typec_mode mode)
+{
+	struct ec_params_typec_control params = {
+		.port = port,
+		.command = TYPEC_CONTROL_COMMAND_ENTER_MODE,
+		.mode_to_enter = mode
+	};
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_PARAMS(EC_CMD_TYPEC_CONTROL, 0, params);
+
+	zassume_ok(host_command_process(&args),
+		   "Failed to send Type-C control for port %d", port);
+}
+
+void host_cmd_typec_control_exit_modes(int port)
+{
+	struct ec_params_typec_control params = {
+		.port = port, .command = TYPEC_CONTROL_COMMAND_EXIT_MODES
+	};
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_PARAMS(EC_CMD_TYPEC_CONTROL, 0, params);
+
+	zassume_ok(host_command_process(&args),
+		   "Failed to send Type-C control for port %d", port);
+}
+
+void host_cmd_typec_control_usb_mux_set(int port,
+					struct typec_usb_mux_set mux_set)
+{
+	struct ec_params_typec_control params = {
+		.port = port,
+		.command = TYPEC_CONTROL_COMMAND_USB_MUX_SET,
+		.mux_params = mux_set,
+	};
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_PARAMS(EC_CMD_TYPEC_CONTROL, 0, params);
+
+	zassume_ok(host_command_process(&args),
+		   "Failed to send Type-C control for port %d", port);
+}
+
+void host_cmd_typec_control_clear_events(int port, uint32_t events)
+{
+	struct ec_params_typec_control params = {
+		.port = port,
+		.command = TYPEC_CONTROL_COMMAND_CLEAR_EVENTS,
+		.clear_events_mask = events,
+	};
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_PARAMS(EC_CMD_TYPEC_CONTROL, 0, params);
+
+	zassume_ok(host_command_process(&args),
+		   "Failed to send Type-C control for port %d", port);
+}
+
+void host_cmd_usb_pd_get_amode(
+	uint8_t port, uint16_t svid_idx,
+	struct ec_params_usb_pd_get_mode_response *response, int *response_size)
+{
+	struct ec_params_usb_pd_get_mode_request params = {
+		.port = port,
+		.svid_idx = svid_idx,
+	};
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_PARAMS(EC_CMD_USB_PD_GET_AMODE, 0, params);
+	args.response = response;
+
+	zassume_ok(host_command_process(&args),
+		   "Failed to get alternate-mode info for port %d", port);
+	*response_size = args.response_size;
+}
+
+void host_events_save(struct host_events_ctx *host_events_ctx)
+{
+	host_events_ctx->lpc_host_events = lpc_get_host_events();
+
+	for (int i = 0; i < LPC_HOST_EVENT_COUNT; i++) {
+		host_events_ctx->lpc_host_event_mask[i] =
+			lpc_get_host_events_by_type(i);
+	}
+}
+
+void host_events_restore(struct host_events_ctx *host_events_ctx)
+{
+	lpc_set_host_event_state(host_events_ctx->lpc_host_events);
+
+	for (int i = 0; i < LPC_HOST_EVENT_COUNT; i++) {
+		lpc_set_host_event_mask(
+			i, host_events_ctx->lpc_host_event_mask[i]);
+	}
+}
+
 K_HEAP_DEFINE(test_heap, 2048);
 
 void *test_malloc(size_t bytes)
@@ -359,3 +592,36 @@ void test_free(void *mem)
 {
 	k_heap_free(&test_heap, mem);
 }
+
+int emul_init_stub(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	return 0;
+}
+
+/* These 2 lines are needed because we don't define an espi host driver */
+#define DT_DRV_COMPAT zephyr_espi_emul_espi_host
+DT_INST_FOREACH_STATUS_OKAY(EMUL_STUB_DEVICE);
+
+void check_console_cmd(const char *cmd, const char *expected_output,
+		       const int expected_rv, const char *file, const int line)
+{
+	const char *buffer;
+	size_t buffer_size;
+	int rv;
+
+	shell_backend_dummy_clear_output(get_ec_shell());
+	rv = shell_execute_cmd(get_ec_shell(), cmd);
+
+	zassert_equal(expected_rv, rv,
+		      "%s:%u \'%s\' - Expected %d, returned %d", file, line,
+		      cmd, expected_rv, rv);
+
+	if (expected_output) {
+		buffer = shell_backend_dummy_get_output(get_ec_shell(),
+							&buffer_size);
+		zassert_true(strstr(buffer, expected_output),
+			     "Invalid console output %s", buffer);
+	}
+}
diff --git a/zephyr/test/drivers/default/CMakeLists.txt b/zephyr/test/drivers/default/CMakeLists.txt
new file mode 100644
index 0000000000..8f5a33cfa1
--- /dev/null
+++ b/zephyr/test/drivers/default/CMakeLists.txt
@@ -0,0 +1,90 @@
+target_sources(app PRIVATE
+    src/battery.c
+    src/bb_retimer.c
+    src/bc12.c
+    src/bma2x2.c
+    src/bmi160.c
+    src/bmi260.c
+    src/charge_manager.c
+    src/console.c
+    src/console_cmd/adc.c
+    src/console_cmd/battery.c
+    src/console_cmd/cbi.c
+    src/console_cmd/charge_manager.c
+    src/console_cmd/charge_state.c
+    src/console_cmd/charger.c
+    src/console_cmd/accelinit.c
+    src/console_cmd/accelinfo.c
+    src/console_cmd/accelspoof.c
+    src/console_cmd/accelrate.c
+    src/console_cmd/accelrange.c
+    src/console_cmd/accelread.c
+    src/console_cmd/accelres.c
+    src/console_cmd/button.c
+    src/console_cmd/crash.c
+    src/console_cmd/cutoff.c
+    src/console_cmd/gpio.c
+    src/console_cmd/i2c_portmap.c
+    src/console_cmd/md.c
+    src/console_cmd/hcdebug.c
+    src/console_cmd/hibdelay.c
+    src/console_cmd/hostevent.c
+    src/console_cmd/panic_output.c
+    src/console_cmd/port80.c
+    src/console_cmd/powerindebug.c
+    src/console_cmd/power_button.c
+    src/console_cmd/rtc.c
+    src/console_cmd/rw.c
+    src/console_cmd/sleepmask.c
+    src/console_cmd/sleeptimeout.c
+    src/console_cmd/sysinfo.c
+    src/console_cmd/tcpci_dump.c
+    src/console_cmd/usb_pd_console.c
+    src/console_cmd/version.c
+    src/console_cmd/waitms.c
+    src/cros_cbi.c
+    src/espi.c
+    src/flash.c
+    src/gpio.c
+    src/integration/usbc/usb.c
+    src/integration/usbc/usb_20v_3a_pd_charger.c
+    src/integration/usbc/usb_5v_3a_pd_sink.c
+    src/integration/usbc/usb_5v_3a_pd_source.c
+    src/integration/usbc/usb_attach_src_snk.c
+    src/integration/usbc/usb_pd_bist_shared.c
+    src/integration/usbc/usb_pd_ctrl_msg.c
+    src/integration/usbc/usb_pd_rev3.c
+    src/i2c.c
+    src/i2c_passthru.c
+    src/isl923x.c
+    src/led.c
+    src/lid_angle.c
+    src/lid_switch.c
+    src/lis2dw12.c
+    src/ln9310.c
+    src/locate_chip.c
+    src/motion_sense/motion_sense.c
+    src/panic.c
+    src/panic_output.c
+    src/port80.c
+    src/power_common.c
+    src/ppc_sn5s330.c
+    src/ppc_syv682x.c
+    src/ps8xxx.c
+    src/smart.c
+    src/stm_mems_common.c
+    src/system.c
+    src/tablet_mode.c
+    src/tcpci.c
+    src/tcpci_test_common.c
+    src/tcs3400.c
+    src/temp_sensor.c
+    src/thermistor.c
+    src/uart_hostcmd.c
+    src/usb_mux.c
+    src/usb_pd_host_cmd.c
+    src/vboot_hash.c
+    src/virtual_battery.c
+    src/vstore.c
+    src/watchdog.c
+)
diff --git a/zephyr/test/drivers/default/prj.conf b/zephyr/test/drivers/default/prj.conf
new file mode 100644
index 0000000000..a9981f31d2
--- /dev/null
+++ b/zephyr/test/drivers/default/prj.conf
@@ -0,0 +1,12 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_PLATFORM_EC_CMD_BUTTON=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_RTC=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_RTC_ALARM=y
+CONFIG_PLATFORM_EC_LED_DT=y
+CONFIG_PLATFORM_EC_RTC=y
+CONFIG_PLATFORM_EC_VOLUME_BUTTONS=y
+
+CONFIG_SYSTEM_FAKE=y
diff --git a/zephyr/test/drivers/src/battery.c b/zephyr/test/drivers/default/src/battery.c
index e454262aa2..6b01a5ca39 100644
--- a/zephyr/test/drivers/src/battery.c
+++ b/zephyr/test/drivers/default/src/battery.c
@@ -1,10 +1,10 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <zephyr/zephyr.h>
-#include <ztest.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
 #include <zephyr/drivers/gpio.h>
 #include <zephyr/drivers/gpio/gpio_emul.h>
 
@@ -14,6 +14,15 @@
 #define GPIO_BATT_PRES_ODL_PATH DT_PATH(named_gpios, ec_batt_pres_odl)
 #define GPIO_BATT_PRES_ODL_PORT DT_GPIO_PIN(GPIO_BATT_PRES_ODL_PATH, gpios)
 
+static void battery_after(void *data)
+{
+	const struct device *dev =
+		DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_BATT_PRES_ODL_PATH, gpios));
+
+	/* Set default state (battery is present) */
+	gpio_emul_input_set(dev, GPIO_BATT_PRES_ODL_PORT, 0);
+}
+
 ZTEST_USER(battery, test_battery_is_present_gpio)
 {
 	const struct device *dev =
@@ -28,4 +37,5 @@ ZTEST_USER(battery, test_battery_is_present_gpio)
 	zassert_equal(BP_NO, battery_is_present(), NULL);
 }
 
-ZTEST_SUITE(battery, drivers_predicate_post_main, NULL, NULL, NULL, NULL);
+ZTEST_SUITE(battery, drivers_predicate_post_main, NULL, NULL, battery_after,
+	    NULL);
diff --git a/zephyr/test/drivers/src/bb_retimer.c b/zephyr/test/drivers/default/src/bb_retimer.c
index dbe4d3143f..74d8fa86a2 100644
--- a/zephyr/test/drivers/src/bb_retimer.c
+++ b/zephyr/test/drivers/default/src/bb_retimer.c
@@ -1,10 +1,10 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <zephyr/zephyr.h>
-#include <ztest.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
 #include <zephyr/drivers/gpio.h>
 #include <zephyr/drivers/gpio/gpio_emul.h>
 
@@ -26,11 +26,9 @@
 #define GPIO_USB_C1_LS_EN_PATH DT_PATH(named_gpios, usb_c1_ls_en)
 #define GPIO_USB_C1_LS_EN_PORT DT_GPIO_PIN(GPIO_USB_C1_LS_EN_PATH, gpios)
 #define GPIO_USB_C1_RT_RST_ODL_PATH DT_PATH(named_gpios, usb_c1_rt_rst_odl)
-#define GPIO_USB_C1_RT_RST_ODL_PORT	\
-		DT_GPIO_PIN(GPIO_USB_C1_RT_RST_ODL_PATH, gpios)
-#define EMUL_LABEL DT_NODELABEL(usb_c1_bb_retimer_emul)
-
-#define BB_RETIMER_ORD DT_DEP_ORD(EMUL_LABEL)
+#define GPIO_USB_C1_RT_RST_ODL_PORT \
+	DT_GPIO_PIN(GPIO_USB_C1_RT_RST_ODL_PATH, gpios)
+#define BB_RETIMER_NODE DT_NODELABEL(usb_c1_bb_retimer_emul)
 
 /** Test is retimer fw update capable function. */
 ZTEST_USER(bb_retimer, test_bb_is_fw_update_capable)
@@ -40,39 +38,42 @@ ZTEST_USER(bb_retimer, test_bb_is_fw_update_capable)
 }
 
 /** Test is retimer fw update capable function. */
-ZTEST_USER(bb_retimer, test_bb_set_state)
+ZTEST_USER(bb_retimer_no_tasks, test_bb_set_state)
 {
 	struct pd_discovery *disc;
 	uint32_t conn, exp_conn;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BB_RETIMER_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bb_retimer_get_i2c_common_data(emul);
 	bool ack_required;
 
-	emul = bb_emul_get(BB_RETIMER_ORD);
-
 	set_test_runner_tid();
 
 	/* Setup emulator fail on write */
-	i2c_common_emul_set_write_fail_reg(emul,
+	i2c_common_emul_set_write_fail_reg(common_data,
 					   BB_RETIMER_REG_CONNECTION_STATE);
 
 	/* Test fail on reset register write */
 	zassert_equal(EC_ERROR_INVAL,
-		      bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
 					 USB_PD_MUX_NONE, &ack_required),
 		      NULL);
 	zassert_false(ack_required, "ACK is never required for BB retimer");
 
 	/* Do not fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Set UFP role for whole test */
 	tc_set_data_role(USBC_PORT_C1, PD_ROLE_UFP);
+	zassume_equal(PD_ROLE_UFP, pd_get_data_role(USBC_PORT_C1), NULL);
 
 	/* Test none mode */
 	bb_emul_set_reg(emul, BB_RETIMER_REG_CONNECTION_STATE, 0x12144678);
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						     USB_PD_MUX_NONE,
-						     &ack_required), NULL);
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_NONE, &ack_required),
+		      NULL);
 	zassert_false(ack_required, "ACK is never required for BB retimer");
 	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
 	/* Only UFP mode is set */
@@ -82,9 +83,10 @@ ZTEST_USER(bb_retimer, test_bb_set_state)
 
 	/* Test USB3 gen1 mode */
 	prl_set_rev(USBC_PORT_C1, TCPCI_MSG_SOP_PRIME, PD_REV10);
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						     USB_PD_MUX_USB_ENABLED,
-						     &ack_required), NULL);
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_USB_ENABLED, &ack_required),
+		      NULL);
 	zassert_false(ack_required, "ACK is never required for BB retimer");
 	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
 	exp_conn = BB_RETIMER_USB_DATA_ROLE |
@@ -94,26 +96,28 @@ ZTEST_USER(bb_retimer, test_bb_set_state)
 		      exp_conn, conn);
 
 	/* Test USB3 gen2 mode */
-	disc = pd_get_am_discovery_and_notify_access(
-					USBC_PORT_C1, TCPCI_MSG_SOP_PRIME);
+	disc = pd_get_am_discovery_and_notify_access(USBC_PORT_C1,
+						     TCPCI_MSG_SOP_PRIME);
 	disc->identity.product_t1.p_rev30.ss = USB_R30_SS_U32_U40_GEN2;
 	prl_set_rev(USBC_PORT_C1, TCPCI_MSG_SOP_PRIME, PD_REV30);
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						     USB_PD_MUX_USB_ENABLED,
-						     &ack_required), NULL);
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_USB_ENABLED, &ack_required),
+		      NULL);
 	zassert_false(ack_required, "ACK is never required for BB retimer");
 	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
 	exp_conn = BB_RETIMER_USB_DATA_ROLE |
 		   BB_RETIMER_DATA_CONNECTION_PRESENT |
-		   BB_RETIMER_USB_3_CONNECTION |
-		   BB_RETIMER_USB_3_SPEED;
+		   BB_RETIMER_USB_3_CONNECTION | BB_RETIMER_USB_3_SPEED;
 	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
 		      exp_conn, conn);
 
 	/* Test TBT mode */
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						USB_PD_MUX_TBT_COMPAT_ENABLED,
-						&ack_required), NULL);
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_TBT_COMPAT_ENABLED,
+					 &ack_required),
+		      NULL);
 	zassert_false(ack_required, "ACK is never required for BB retimer");
 	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
 	exp_conn = BB_RETIMER_USB_DATA_ROLE |
@@ -123,91 +127,93 @@ ZTEST_USER(bb_retimer, test_bb_set_state)
 		      exp_conn, conn);
 
 	/* Test USB4 mode */
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						     USB_PD_MUX_USB4_ENABLED,
-						     &ack_required), NULL);
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_USB4_ENABLED,
+					 &ack_required),
+		      NULL);
 	zassert_false(ack_required, "ACK is never required for BB retimer");
 	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
 	exp_conn = BB_RETIMER_USB_DATA_ROLE |
-		   BB_RETIMER_DATA_CONNECTION_PRESENT |
-		   BB_RETIMER_USB4_ENABLED;
+		   BB_RETIMER_DATA_CONNECTION_PRESENT | BB_RETIMER_USB4_ENABLED;
 	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
 		      exp_conn, conn);
 
 	/* Test USB4 mode with polarity inverted */
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						USB_PD_MUX_USB4_ENABLED |
-						USB_PD_MUX_POLARITY_INVERTED,
-						&ack_required), NULL);
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_USB4_ENABLED |
+						 USB_PD_MUX_POLARITY_INVERTED,
+					 &ack_required),
+		      NULL);
 	zassert_false(ack_required, "ACK is never required for BB retimer");
 	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
 	exp_conn = BB_RETIMER_USB_DATA_ROLE |
 		   BB_RETIMER_DATA_CONNECTION_PRESENT |
-		   BB_RETIMER_CONNECTION_ORIENTATION |
-		   BB_RETIMER_USB4_ENABLED;
+		   BB_RETIMER_CONNECTION_ORIENTATION | BB_RETIMER_USB4_ENABLED;
 	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
 		      exp_conn, conn);
 
 	/* Test DP mode */
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						     USB_PD_MUX_DP_ENABLED,
-						     &ack_required), NULL);
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_DP_ENABLED, &ack_required),
+		      NULL);
 	zassert_false(ack_required, "ACK is never required for BB retimer");
 	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
 	exp_conn = BB_RETIMER_USB_DATA_ROLE |
-		   BB_RETIMER_DATA_CONNECTION_PRESENT |
-		   BB_RETIMER_DP_CONNECTION;
+		   BB_RETIMER_DATA_CONNECTION_PRESENT;
 	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
 		      exp_conn, conn);
 
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						     USB_PD_MUX_DP_ENABLED |
-						     USB_PD_MUX_HPD_IRQ,
-						     &ack_required), NULL);
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_DP_ENABLED |
+						 USB_PD_MUX_HPD_IRQ,
+					 &ack_required),
+		      NULL);
 	zassert_false(ack_required, "ACK is never required for BB retimer");
 	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
 	exp_conn = BB_RETIMER_USB_DATA_ROLE |
-		   BB_RETIMER_DATA_CONNECTION_PRESENT |
-		   BB_RETIMER_DP_CONNECTION |
-		   BB_RETIMER_IRQ_HPD;
+		   BB_RETIMER_DATA_CONNECTION_PRESENT | BB_RETIMER_IRQ_HPD;
 	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
 		      exp_conn, conn);
 
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						     USB_PD_MUX_DP_ENABLED |
-						     USB_PD_MUX_HPD_LVL,
-						     &ack_required), NULL);
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_DP_ENABLED |
+						 USB_PD_MUX_HPD_LVL,
+					 &ack_required),
+		      NULL);
 	zassert_false(ack_required, "ACK is never required for BB retimer");
 	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
 	exp_conn = BB_RETIMER_USB_DATA_ROLE |
-		   BB_RETIMER_DATA_CONNECTION_PRESENT |
-		   BB_RETIMER_DP_CONNECTION |
-		   BB_RETIMER_HPD_LVL;
+		   BB_RETIMER_DATA_CONNECTION_PRESENT | BB_RETIMER_HPD_LVL;
 	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
 		      exp_conn, conn);
 }
 
 /** Test setting different options for DFP role */
-ZTEST_USER(bb_retimer, test_bb_set_dfp_state)
+ZTEST_USER(bb_retimer_no_tasks, test_bb_set_dfp_state)
 {
 	union tbt_mode_resp_device device_resp;
 	union tbt_mode_resp_cable cable_resp;
 	struct pd_discovery *disc, *dev_disc;
 	uint32_t conn, exp_conn;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BB_RETIMER_NODE);
 	bool ack_required;
 
-	emul = bb_emul_get(BB_RETIMER_ORD);
-
 	set_test_runner_tid();
 
 	tc_set_data_role(USBC_PORT_C1, PD_ROLE_DFP);
+	zassume_equal(PD_ROLE_DFP, pd_get_data_role(USBC_PORT_C1), NULL);
 
 	/* Test PD mux none mode with DFP should clear all bits in state */
 	bb_emul_set_reg(emul, BB_RETIMER_REG_CONNECTION_STATE, 0x12144678);
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						     USB_PD_MUX_NONE,
-						     &ack_required), NULL);
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_NONE, &ack_required),
+		      NULL);
 	zassert_false(ack_required, "ACK is never required for BB retimer");
 	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
 	exp_conn = 0;
@@ -215,8 +221,8 @@ ZTEST_USER(bb_retimer, test_bb_set_dfp_state)
 		      exp_conn, conn);
 
 	/* Set active cable type */
-	disc = pd_get_am_discovery_and_notify_access(
-					USBC_PORT_C1, TCPCI_MSG_SOP_PRIME);
+	disc = pd_get_am_discovery_and_notify_access(USBC_PORT_C1,
+						     TCPCI_MSG_SOP_PRIME);
 	disc->identity.idh.product_type = IDH_PTYPE_ACABLE;
 	disc->identity.product_t2.a2_rev30.active_elem = ACTIVE_RETIMER;
 	disc->identity.product_t1.p_rev30.ss = USB_R30_SS_U32_U40_GEN2;
@@ -237,8 +243,8 @@ ZTEST_USER(bb_retimer, test_bb_set_dfp_state)
 	disc->svids[0].mode_vdo[0] = cable_resp.raw_value;
 
 	/* Set device VDO */
-	dev_disc = pd_get_am_discovery_and_notify_access(
-						USBC_PORT_C1, TCPCI_MSG_SOP);
+	dev_disc = pd_get_am_discovery_and_notify_access(USBC_PORT_C1,
+							 TCPCI_MSG_SOP);
 	dev_disc->svid_cnt = 1;
 	dev_disc->svids[0].svid = USB_VID_INTEL;
 	dev_disc->svids[0].discovery = PD_DISC_COMPLETE;
@@ -251,42 +257,43 @@ ZTEST_USER(bb_retimer, test_bb_set_dfp_state)
 	dev_disc->svids[0].mode_vdo[0] = device_resp.raw_value;
 
 	/* Test USB mode with active cable */
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						     USB_PD_MUX_USB_ENABLED,
-						     &ack_required), NULL);
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_USB_ENABLED, &ack_required),
+		      NULL);
 	zassert_false(ack_required, "ACK is never required for BB retimer");
 	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
 	exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT |
-		   BB_RETIMER_USB_3_CONNECTION |
-		   BB_RETIMER_USB_3_SPEED |
-		   BB_RETIMER_RE_TIMER_DRIVER |
-		   BB_RETIMER_ACTIVE_PASSIVE;
+		   BB_RETIMER_USB_3_CONNECTION | BB_RETIMER_USB_3_SPEED |
+		   BB_RETIMER_RE_TIMER_DRIVER | BB_RETIMER_ACTIVE_PASSIVE;
 	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
 		      exp_conn, conn);
 
 	/* Test TBT mode with active cable */
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						USB_PD_MUX_TBT_COMPAT_ENABLED,
-						&ack_required), NULL);
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_TBT_COMPAT_ENABLED,
+					 &ack_required),
+		      NULL);
 	zassert_false(ack_required, "ACK is never required for BB retimer");
 	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
 	exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT |
-		   BB_RETIMER_TBT_CONNECTION |
-		   BB_RETIMER_ACTIVE_PASSIVE;
+		   BB_RETIMER_TBT_CONNECTION | BB_RETIMER_ACTIVE_PASSIVE;
 	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
 		      exp_conn, conn);
 
 	/* Test TBT mode with retimer */
 	cable_resp.retimer_type = USB_RETIMER;
 	disc->svids[0].mode_vdo[0] = cable_resp.raw_value;
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						USB_PD_MUX_TBT_COMPAT_ENABLED,
-						&ack_required), NULL);
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_TBT_COMPAT_ENABLED,
+					 &ack_required),
+		      NULL);
 	zassert_false(ack_required, "ACK is never required for BB retimer");
 	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
 	exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT |
-		   BB_RETIMER_TBT_CONNECTION |
-		   BB_RETIMER_RE_TIMER_DRIVER |
+		   BB_RETIMER_TBT_CONNECTION | BB_RETIMER_RE_TIMER_DRIVER |
 		   BB_RETIMER_ACTIVE_PASSIVE;
 	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
 		      exp_conn, conn);
@@ -295,14 +302,15 @@ ZTEST_USER(bb_retimer, test_bb_set_dfp_state)
 	cable_resp.retimer_type = USB_NOT_RETIMER;
 	cable_resp.tbt_cable = TBT_CABLE_OPTICAL;
 	disc->svids[0].mode_vdo[0] = cable_resp.raw_value;
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						USB_PD_MUX_TBT_COMPAT_ENABLED,
-						&ack_required), NULL);
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_TBT_COMPAT_ENABLED,
+					 &ack_required),
+		      NULL);
 	zassert_false(ack_required, "ACK is never required for BB retimer");
 	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
 	exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT |
-		   BB_RETIMER_TBT_CONNECTION |
-		   BB_RETIMER_TBT_CABLE_TYPE |
+		   BB_RETIMER_TBT_CONNECTION | BB_RETIMER_TBT_CABLE_TYPE |
 		   BB_RETIMER_ACTIVE_PASSIVE;
 	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
 		      exp_conn, conn);
@@ -311,15 +319,16 @@ ZTEST_USER(bb_retimer, test_bb_set_dfp_state)
 	cable_resp.tbt_cable = TBT_CABLE_NON_OPTICAL;
 	cable_resp.lsrx_comm = UNIDIR_LSRX_COMM;
 	disc->svids[0].mode_vdo[0] = cable_resp.raw_value;
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						USB_PD_MUX_TBT_COMPAT_ENABLED,
-						&ack_required), NULL);
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_TBT_COMPAT_ENABLED,
+					 &ack_required),
+		      NULL);
 	zassert_false(ack_required, "ACK is never required for BB retimer");
 	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
-	exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT |
-		   BB_RETIMER_TBT_CONNECTION |
-		   BB_RETIMER_TBT_ACTIVE_LINK_TRAINING |
-		   BB_RETIMER_ACTIVE_PASSIVE;
+	exp_conn =
+		BB_RETIMER_DATA_CONNECTION_PRESENT | BB_RETIMER_TBT_CONNECTION |
+		BB_RETIMER_TBT_ACTIVE_LINK_TRAINING | BB_RETIMER_ACTIVE_PASSIVE;
 	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
 		      exp_conn, conn);
 
@@ -327,9 +336,11 @@ ZTEST_USER(bb_retimer, test_bb_set_dfp_state)
 	cable_resp.lsrx_comm = BIDIR_LSRX_COMM;
 	cable_resp.tbt_cable_speed = TBT_SS_U31_GEN1;
 	disc->svids[0].mode_vdo[0] = cable_resp.raw_value;
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						USB_PD_MUX_TBT_COMPAT_ENABLED,
-						&ack_required), NULL);
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_TBT_COMPAT_ENABLED,
+					 &ack_required),
+		      NULL);
 	zassert_false(ack_required, "ACK is never required for BB retimer");
 	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
 	exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT |
@@ -341,9 +352,11 @@ ZTEST_USER(bb_retimer, test_bb_set_dfp_state)
 
 	cable_resp.tbt_cable_speed = TBT_SS_U32_GEN1_GEN2;
 	disc->svids[0].mode_vdo[0] = cable_resp.raw_value;
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						USB_PD_MUX_TBT_COMPAT_ENABLED,
-						&ack_required), NULL);
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_TBT_COMPAT_ENABLED,
+					 &ack_required),
+		      NULL);
 	zassert_false(ack_required, "ACK is never required for BB retimer");
 	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
 	exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT |
@@ -355,9 +368,11 @@ ZTEST_USER(bb_retimer, test_bb_set_dfp_state)
 
 	cable_resp.tbt_cable_speed = TBT_SS_TBT_GEN3;
 	disc->svids[0].mode_vdo[0] = cable_resp.raw_value;
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						USB_PD_MUX_TBT_COMPAT_ENABLED,
-						&ack_required), NULL);
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_TBT_COMPAT_ENABLED,
+					 &ack_required),
+		      NULL);
 	zassert_false(ack_required, "ACK is never required for BB retimer");
 	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
 	exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT |
@@ -371,15 +386,16 @@ ZTEST_USER(bb_retimer, test_bb_set_dfp_state)
 	cable_resp.tbt_cable_speed = TBT_SS_RES_0;
 	cable_resp.tbt_rounded = TBT_GEN3_GEN4_ROUNDED_NON_ROUNDED;
 	disc->svids[0].mode_vdo[0] = cable_resp.raw_value;
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						USB_PD_MUX_TBT_COMPAT_ENABLED,
-						&ack_required), NULL);
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_TBT_COMPAT_ENABLED,
+					 &ack_required),
+		      NULL);
 	zassert_false(ack_required, "ACK is never required for BB retimer");
 	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
-	exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT |
-		   BB_RETIMER_TBT_CONNECTION |
-		   BB_RETIMER_TBT_CABLE_GENERATION(1) |
-		   BB_RETIMER_ACTIVE_PASSIVE;
+	exp_conn =
+		BB_RETIMER_DATA_CONNECTION_PRESENT | BB_RETIMER_TBT_CONNECTION |
+		BB_RETIMER_TBT_CABLE_GENERATION(1) | BB_RETIMER_ACTIVE_PASSIVE;
 	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
 		      exp_conn, conn);
 
@@ -388,14 +404,15 @@ ZTEST_USER(bb_retimer, test_bb_set_dfp_state)
 	disc->svids[0].mode_vdo[0] = cable_resp.raw_value;
 	device_resp.tbt_adapter = TBT_ADAPTER_TBT2_LEGACY;
 	dev_disc->svids[0].mode_vdo[0] = device_resp.raw_value;
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						USB_PD_MUX_TBT_COMPAT_ENABLED,
-						&ack_required), NULL);
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_TBT_COMPAT_ENABLED,
+					 &ack_required),
+		      NULL);
 	zassert_false(ack_required, "ACK is never required for BB retimer");
 	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
 	exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT |
-		   BB_RETIMER_TBT_CONNECTION |
-		   BB_RETIMER_TBT_TYPE |
+		   BB_RETIMER_TBT_CONNECTION | BB_RETIMER_TBT_TYPE |
 		   BB_RETIMER_ACTIVE_PASSIVE;
 	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
 		      exp_conn, conn);
@@ -404,14 +421,15 @@ ZTEST_USER(bb_retimer, test_bb_set_dfp_state)
 	device_resp.tbt_adapter = TBT_ADAPTER_TBT3;
 	device_resp.intel_spec_b0 = VENDOR_SPECIFIC_SUPPORTED;
 	dev_disc->svids[0].mode_vdo[0] = device_resp.raw_value;
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						USB_PD_MUX_TBT_COMPAT_ENABLED,
-						&ack_required), NULL);
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_TBT_COMPAT_ENABLED,
+					 &ack_required),
+		      NULL);
 	zassert_false(ack_required, "ACK is never required for BB retimer");
 	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
 	exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT |
-		   BB_RETIMER_TBT_CONNECTION |
-		   BB_RETIMER_ACTIVE_PASSIVE;
+		   BB_RETIMER_TBT_CONNECTION | BB_RETIMER_ACTIVE_PASSIVE;
 
 	if (IS_ENABLED(CONFIG_USBC_RETIMER_INTEL_BB_VPRO_CAPABLE))
 		exp_conn |= BB_RETIMER_VPRO_DOCK_DP_OVERDRIVE;
@@ -423,15 +441,16 @@ ZTEST_USER(bb_retimer, test_bb_set_dfp_state)
 	device_resp.intel_spec_b0 = VENDOR_SPECIFIC_NOT_SUPPORTED;
 	device_resp.vendor_spec_b1 = VENDOR_SPECIFIC_SUPPORTED;
 	dev_disc->svids[0].mode_vdo[0] = device_resp.raw_value;
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1],
-						USB_PD_MUX_TBT_COMPAT_ENABLED,
-						&ack_required), NULL);
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.set(usb_muxes[USBC_PORT_C1].mux,
+					 USB_PD_MUX_TBT_COMPAT_ENABLED,
+					 &ack_required),
+		      NULL);
 	zassert_false(ack_required, "ACK is never required for BB retimer");
 	conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE);
-	exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT |
-		   BB_RETIMER_TBT_CONNECTION |
-		   BB_RETIMER_VPRO_DOCK_DP_OVERDRIVE |
-		   BB_RETIMER_ACTIVE_PASSIVE;
+	exp_conn =
+		BB_RETIMER_DATA_CONNECTION_PRESENT | BB_RETIMER_TBT_CONNECTION |
+		BB_RETIMER_VPRO_DOCK_DP_OVERDRIVE | BB_RETIMER_ACTIVE_PASSIVE;
 	zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx",
 		      exp_conn, conn);
 }
@@ -441,86 +460,90 @@ ZTEST_USER(bb_retimer, test_bb_init)
 {
 	const struct device *gpio_dev =
 		DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_USB_C1_LS_EN_PATH, gpios));
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BB_RETIMER_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bb_retimer_get_i2c_common_data(emul);
 
 	zassert_not_null(gpio_dev, "Cannot get GPIO device");
 
-	emul = bb_emul_get(BB_RETIMER_ORD);
-
 	/* Set AP to normal state and wait for chipset task */
 	test_set_chipset_to_s0();
 
 	/* Setup emulator fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, BB_RETIMER_REG_VENDOR_ID);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  BB_RETIMER_REG_VENDOR_ID);
 	/* Test fail on vendor ID read */
 	zassert_equal(EC_ERROR_INVAL,
-		      bb_usb_retimer.init(&usb_muxes[USBC_PORT_C1]), NULL);
+		      bb_usb_retimer.init(usb_muxes[USBC_PORT_C1].mux), NULL);
 	/* Enable pins should be set always after init, when AP is on */
 	zassert_equal(1, gpio_emul_output_get(gpio_dev, GPIO_USB_C1_LS_EN_PORT),
 		      NULL);
-	zassert_equal(1, gpio_emul_output_get(gpio_dev,
-					      GPIO_USB_C1_RT_RST_ODL_PORT),
-		      NULL);
+	zassert_equal(
+		1, gpio_emul_output_get(gpio_dev, GPIO_USB_C1_RT_RST_ODL_PORT),
+		NULL);
 
 	/* Setup wrong vendor ID */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 	bb_emul_set_reg(emul, BB_RETIMER_REG_VENDOR_ID, 0x12144678);
 	/* Test fail on wrong vendor ID */
 	zassert_equal(EC_ERROR_INVAL,
-		      bb_usb_retimer.init(&usb_muxes[USBC_PORT_C1]), NULL);
+		      bb_usb_retimer.init(usb_muxes[USBC_PORT_C1].mux), NULL);
 	zassert_equal(1, gpio_emul_output_get(gpio_dev, GPIO_USB_C1_LS_EN_PORT),
 		      NULL);
-	zassert_equal(1, gpio_emul_output_get(gpio_dev,
-					      GPIO_USB_C1_RT_RST_ODL_PORT),
-		      NULL);
+	zassert_equal(
+		1, gpio_emul_output_get(gpio_dev, GPIO_USB_C1_RT_RST_ODL_PORT),
+		NULL);
 
 	/* Setup emulator fail on device ID read */
-	i2c_common_emul_set_read_fail_reg(emul, BB_RETIMER_REG_DEVICE_ID);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  BB_RETIMER_REG_DEVICE_ID);
 	bb_emul_set_reg(emul, BB_RETIMER_REG_VENDOR_ID, BB_RETIMER_VENDOR_ID_1);
 	/* Test fail on device ID read */
 	zassert_equal(EC_ERROR_INVAL,
-		      bb_usb_retimer.init(&usb_muxes[USBC_PORT_C1]), NULL);
+		      bb_usb_retimer.init(usb_muxes[USBC_PORT_C1].mux), NULL);
 	zassert_equal(1, gpio_emul_output_get(gpio_dev, GPIO_USB_C1_LS_EN_PORT),
 		      NULL);
-	zassert_equal(1, gpio_emul_output_get(gpio_dev,
-					      GPIO_USB_C1_RT_RST_ODL_PORT),
-		      NULL);
+	zassert_equal(
+		1, gpio_emul_output_get(gpio_dev, GPIO_USB_C1_RT_RST_ODL_PORT),
+		NULL);
 
 	/* Setup wrong device ID */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 	bb_emul_set_reg(emul, BB_RETIMER_REG_DEVICE_ID, 0x12144678);
 	/* Test fail on wrong device ID */
 	zassert_equal(EC_ERROR_INVAL,
-		      bb_usb_retimer.init(&usb_muxes[USBC_PORT_C1]), NULL);
+		      bb_usb_retimer.init(usb_muxes[USBC_PORT_C1].mux), NULL);
 	zassert_equal(1, gpio_emul_output_get(gpio_dev, GPIO_USB_C1_LS_EN_PORT),
 		      NULL);
-	zassert_equal(1, gpio_emul_output_get(gpio_dev,
-					      GPIO_USB_C1_RT_RST_ODL_PORT),
-		      NULL);
+	zassert_equal(
+		1, gpio_emul_output_get(gpio_dev, GPIO_USB_C1_RT_RST_ODL_PORT),
+		NULL);
 
 	/* Test successful init */
 	bb_emul_set_reg(emul, BB_RETIMER_REG_DEVICE_ID, BB_RETIMER_DEVICE_ID);
-	zassert_equal(EC_SUCCESS, bb_usb_retimer.init(&usb_muxes[USBC_PORT_C1]),
-		      NULL);
+	zassert_equal(EC_SUCCESS,
+		      bb_usb_retimer.init(usb_muxes[USBC_PORT_C1].mux), NULL);
 	zassert_equal(1, gpio_emul_output_get(gpio_dev, GPIO_USB_C1_LS_EN_PORT),
 		      NULL);
-	zassert_equal(1, gpio_emul_output_get(gpio_dev,
-					      GPIO_USB_C1_RT_RST_ODL_PORT),
-		      NULL);
+	zassert_equal(
+		1, gpio_emul_output_get(gpio_dev, GPIO_USB_C1_RT_RST_ODL_PORT),
+		NULL);
 
 	/* Set AP to off state and wait for chipset task */
 	test_set_chipset_to_g3();
 
 	/* With AP off, init should fail and pins should be unset */
 	zassert_equal(EC_ERROR_NOT_POWERED,
-		      bb_usb_retimer.init(&usb_muxes[USBC_PORT_C1]), NULL);
+		      bb_usb_retimer.init(usb_muxes[USBC_PORT_C1].mux), NULL);
 	zassert_equal(0, gpio_emul_output_get(gpio_dev, GPIO_USB_C1_LS_EN_PORT),
 		      NULL);
 
 	msleep(1);
-	zassert_equal(0, gpio_emul_output_get(gpio_dev,
-					      GPIO_USB_C1_RT_RST_ODL_PORT),
-		      NULL);
+	zassert_equal(
+		0, gpio_emul_output_get(gpio_dev, GPIO_USB_C1_RT_RST_ODL_PORT),
+		NULL);
 }
 
 /** Test BB retimer console command */
@@ -549,4 +572,7 @@ ZTEST_USER(bb_retimer, test_bb_console_cmd)
 	zassert_equal(EC_ERROR_PARAM4, rv, "rv=%d", rv);
 }
 
+ZTEST_SUITE(bb_retimer_no_tasks, drivers_predicate_pre_main, NULL, NULL, NULL,
+	    NULL);
+
 ZTEST_SUITE(bb_retimer, drivers_predicate_post_main, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/drivers/src/bc12.c b/zephyr/test/drivers/default/src/bc12.c
index d1a96131c1..a8d23e73ce 100644
--- a/zephyr/test/drivers/src/bc12.c
+++ b/zephyr/test/drivers/default/src/bc12.c
@@ -1,10 +1,10 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <zephyr/zephyr.h>
-#include <ztest.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
 #include <zephyr/drivers/gpio.h>
 #include <zephyr/drivers/gpio/gpio_emul.h>
 
@@ -16,19 +16,18 @@
 #include "extpower.h"
 #include "test/drivers/stubs.h"
 #include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
 
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(test_drivers_bc12, LOG_LEVEL_DBG);
 
-#define EMUL_LABEL DT_NODELABEL(pi3usb9201_emul)
-
-#define PI3USB9201_ORD DT_DEP_ORD(EMUL_LABEL)
+#define EMUL_NODE DT_NODELABEL(pi3usb9201_emul)
 
 /* Control_1 register bit definitions */
 #define PI3USB9201_REG_CTRL_1_INT_MASK BIT(0)
 #define PI3USB9201_REG_CTRL_1_MODE_SHIFT 1
-#define PI3USB9201_REG_CTRL_1_MODE_MASK (0x7 << \
-					 PI3USB9201_REG_CTRL_1_MODE_SHIFT)
+#define PI3USB9201_REG_CTRL_1_MODE_MASK \
+	(0x7 << PI3USB9201_REG_CTRL_1_MODE_SHIFT)
 
 /* Control_2 register bit definitions */
 #define PI3USB9201_REG_CTRL_2_AUTO_SW BIT(1)
@@ -67,38 +66,35 @@ struct bc12_status {
 };
 
 static const struct bc12_status bc12_chg_limits[] = {
-	[CHG_OTHER]    = { .supplier = CHARGE_SUPPLIER_OTHER,
-			   .current_limit = 500 },
-	[CHG_2_4A]     = { .supplier = CHARGE_SUPPLIER_PROPRIETARY,
-			   .current_limit = USB_CHARGER_MAX_CURR_MA },
-	[CHG_2_0A]     = { .supplier = CHARGE_SUPPLIER_PROPRIETARY,
-			   .current_limit = USB_CHARGER_MAX_CURR_MA },
-	[CHG_1_0A]     = { .supplier = CHARGE_SUPPLIER_PROPRIETARY,
-			   .current_limit = 1000 },
+	[CHG_OTHER] = { .supplier = CHARGE_SUPPLIER_OTHER,
+			.current_limit = 500 },
+	[CHG_2_4A] = { .supplier = CHARGE_SUPPLIER_PROPRIETARY,
+		       .current_limit = USB_CHARGER_MAX_CURR_MA },
+	[CHG_2_0A] = { .supplier = CHARGE_SUPPLIER_PROPRIETARY,
+		       .current_limit = USB_CHARGER_MAX_CURR_MA },
+	[CHG_1_0A] = { .supplier = CHARGE_SUPPLIER_PROPRIETARY,
+		       .current_limit = 1000 },
 	[CHG_RESERVED] = { .supplier = CHARGE_SUPPLIER_NONE,
 			   .current_limit = 0 },
-	[CHG_CDP]      = { .supplier = CHARGE_SUPPLIER_BC12_CDP,
-			   .current_limit = USB_CHARGER_MAX_CURR_MA },
-	[CHG_SDP]      = { .supplier = CHARGE_SUPPLIER_BC12_SDP,
-			   .current_limit = 500 },
+	[CHG_CDP] = { .supplier = CHARGE_SUPPLIER_BC12_CDP,
+		      .current_limit = USB_CHARGER_MAX_CURR_MA },
+	[CHG_SDP] = { .supplier = CHARGE_SUPPLIER_BC12_SDP,
+		      .current_limit = 500 },
 #if defined(CONFIG_CHARGE_RAMP_SW) || defined(CONFIG_CHARGE_RAMP_HW)
-	[CHG_DCP]      = { .supplier = CHARGE_SUPPLIER_BC12_DCP,
-			   .current_limit = USB_CHARGER_MAX_CURR_MA },
+	[CHG_DCP] = { .supplier = CHARGE_SUPPLIER_BC12_DCP,
+		      .current_limit = USB_CHARGER_MAX_CURR_MA },
 #else
-	[CHG_DCP]      = { .supplier = CHARGE_SUPPLIER_BC12_DCP,
-			   .current_limit = 500 },
+	[CHG_DCP] = { .supplier = CHARGE_SUPPLIER_BC12_DCP,
+		      .current_limit = 500 },
 #endif
 };
 
 #define GPIO_BATT_PRES_ODL_PATH DT_PATH(named_gpios, ec_batt_pres_odl)
 #define GPIO_BATT_PRES_ODL_PORT DT_GPIO_PIN(GPIO_BATT_PRES_ODL_PATH, gpios)
 
-#define GPIO_ACOK_OD_PATH DT_PATH(named_gpios, acok_od)
-#define GPIO_ACOK_OD_PORT DT_GPIO_PIN(GPIO_ACOK_OD_PATH, gpios)
-
 static void test_bc12_pi3usb9201_host_mode(void)
 {
-	struct i2c_emul *emul = pi3usb9201_emul_get(PI3USB9201_ORD);
+	const struct emul *emul = EMUL_DT_GET(EMUL_NODE);
 	uint8_t a, b;
 
 	/*
@@ -140,11 +136,12 @@ static void test_bc12_pi3usb9201_host_mode(void)
 	pi3usb9201_emul_set_reg(emul, PI3USB9201_REG_HOST_STS, 0);
 }
 
-static void test_bc12_pi3usb9201_client_mode(
-			enum pi3usb9201_client_sts detect_result,
-			enum charge_supplier supplier, int current_limit)
+static void
+test_bc12_pi3usb9201_client_mode(enum pi3usb9201_client_sts detect_result,
+				 enum charge_supplier supplier,
+				 int current_limit)
 {
-	struct i2c_emul *emul = pi3usb9201_emul_get(PI3USB9201_ORD);
+	const struct emul *emul = EMUL_DT_GET(EMUL_NODE);
 	uint8_t a, b;
 	int port, voltage;
 
@@ -188,14 +185,11 @@ static void test_bc12_pi3usb9201_client_mode(
 	}
 	/* Wait for the charge port to update. */
 	msleep(500);
-	zassert_equal(charge_manager_get_active_charge_port(),
-		      port, NULL);
-	zassert_equal(charge_manager_get_supplier(),
-		      supplier, NULL);
-	zassert_equal(charge_manager_get_charger_current(),
-		      current_limit, NULL);
-	zassert_equal(charge_manager_get_charger_voltage(),
-		      voltage, NULL);
+	zassert_equal(charge_manager_get_active_charge_port(), port, NULL);
+	zassert_equal(charge_manager_get_supplier(), supplier, NULL);
+	zassert_equal(charge_manager_get_charger_current(), current_limit,
+		      NULL);
+	zassert_equal(charge_manager_get_charger_voltage(), voltage, NULL);
 
 	/*
 	 * Pretend that the USB-C Port Manager (TCPMv2) has set the port data
@@ -213,10 +207,10 @@ static void test_bc12_pi3usb9201_client_mode(
 	b |= PI3USB9201_REG_CTRL_1_INT_MASK;
 	zassert_equal(a, b, NULL);
 	/* Expect the charge manager to have no active supplier. */
-	zassert_equal(charge_manager_get_active_charge_port(),
-		      CHARGE_PORT_NONE, NULL);
-	zassert_equal(charge_manager_get_supplier(),
-		      CHARGE_SUPPLIER_NONE, NULL);
+	zassert_equal(charge_manager_get_active_charge_port(), CHARGE_PORT_NONE,
+		      NULL);
+	zassert_equal(charge_manager_get_supplier(), CHARGE_SUPPLIER_NONE,
+		      NULL);
 	zassert_equal(charge_manager_get_charger_current(), 0, NULL);
 	zassert_equal(charge_manager_get_charger_voltage(), 0, NULL);
 }
@@ -234,18 +228,15 @@ ZTEST_USER(bc12, test_bc12_pi3usb9201)
 {
 	const struct device *batt_pres_dev =
 		DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_BATT_PRES_ODL_PATH, gpios));
-	const struct device *acok_dev =
-		DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_ACOK_OD_PATH, gpios));
-	struct i2c_emul *emul = pi3usb9201_emul_get(PI3USB9201_ORD);
+	const struct emul *emul = EMUL_DT_GET(EMUL_NODE);
 	uint8_t a, b;
 
 	/* Pretend we have battery and AC so charging works normally. */
-	zassert_ok(gpio_emul_input_set(batt_pres_dev,
-				       GPIO_BATT_PRES_ODL_PORT, 0), NULL);
+	zassert_ok(gpio_emul_input_set(batt_pres_dev, GPIO_BATT_PRES_ODL_PORT,
+				       0),
+		   NULL);
 	zassert_equal(BP_YES, battery_is_present(), NULL);
-	zassert_ok(gpio_emul_input_set(acok_dev, GPIO_ACOK_OD_PORT, 1), NULL);
-	msleep(CONFIG_EXTPOWER_DEBOUNCE_MS + 1);
-	zassert_equal(1, extpower_is_present(), NULL);
+	set_ac_enabled(true);
 
 	/* Wait long enough for TCPMv2 to be idle. */
 	msleep(2000);
@@ -269,14 +260,18 @@ ZTEST_USER(bc12, test_bc12_pi3usb9201)
 	test_bc12_pi3usb9201_host_mode();
 
 	for (int c = CHG_OTHER; c <= CHG_DCP; c++) {
-		test_bc12_pi3usb9201_client_mode(c,
-					bc12_chg_limits[c].supplier,
-					bc12_chg_limits[c].current_limit);
+		test_bc12_pi3usb9201_client_mode(
+			c, bc12_chg_limits[c].supplier,
+			bc12_chg_limits[c].current_limit);
 	}
 }
 
 /*
  * TODO(b/216660795): Cleanup state using a teardown_fn
  */
+static void bc12_after(void *unused)
+{
+	set_ac_enabled(false);
+}
 
-ZTEST_SUITE(bc12, drivers_predicate_post_main, NULL, NULL, NULL, NULL);
+ZTEST_SUITE(bc12, drivers_predicate_post_main, NULL, NULL, bc12_after, NULL);
diff --git a/zephyr/test/drivers/src/bma2x2.c b/zephyr/test/drivers/default/src/bma2x2.c
index 1995adc571..e848a265fd 100644
--- a/zephyr/test/drivers/src/bma2x2.c
+++ b/zephyr/test/drivers/default/src/bma2x2.c
@@ -1,10 +1,10 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <zephyr/zephyr.h>
-#include <ztest.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
 
 #include "common.h"
 #include "i2c.h"
@@ -19,19 +19,15 @@
 /** How accurate comparision of vectors should be. */
 #define V_EPS 8
 
-#define EMUL_LABEL DT_NODELABEL(bma_emul)
-
-#define BMA_ORD DT_DEP_ORD(EMUL_LABEL)
+#define BMA_NODE DT_NODELABEL(bma_emul)
 
 /** Mutex for test motion sensor  */
 static mutex_t sensor_mutex;
 
 /** Rotation used in some tests */
-static const mat33_fp_t test_rotation = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t test_rotation = { { 0, FLOAT_TO_FP(1), 0 },
+					  { FLOAT_TO_FP(-1), 0, 0 },
+					  { 0, 0, FLOAT_TO_FP(-1) } };
 
 /** Rotate given vector by test rotation */
 void rotate_int3v_by_test_rotation(int16_t *v)
@@ -53,14 +49,14 @@ static struct motion_sensor_t ms = {
 	.drv = &bma2x2_accel_drv,
 	.mutex = &sensor_mutex,
 	.drv_data = &acc_data,
-	.port = NAMED_I2C(accel),
-	.i2c_spi_addr_flags = DT_REG_ADDR(EMUL_LABEL),
+	.port = I2C_PORT_NODELABEL(i2c0),
+	.i2c_spi_addr_flags = DT_REG_ADDR(BMA_NODE),
 	.rot_standard_ref = NULL,
 	.current_range = 0,
 };
 
 /** Set emulator offset values to vector of three int16_t */
-static void set_emul_offset(struct i2c_emul *emul, int16_t *offset)
+static void set_emul_offset(const struct emul *emul, int16_t *offset)
 {
 	bma_emul_set_off(emul, BMA_EMUL_AXIS_X, offset[0]);
 	bma_emul_set_off(emul, BMA_EMUL_AXIS_Y, offset[1]);
@@ -68,7 +64,7 @@ static void set_emul_offset(struct i2c_emul *emul, int16_t *offset)
 }
 
 /** Save emulator offset values to vector of three int16_t */
-static void get_emul_offset(struct i2c_emul *emul, int16_t *offset)
+static void get_emul_offset(const struct emul *emul, int16_t *offset)
 {
 	offset[0] = bma_emul_get_off(emul, BMA_EMUL_AXIS_X);
 	offset[1] = bma_emul_get_off(emul, BMA_EMUL_AXIS_Y);
@@ -76,7 +72,7 @@ static void get_emul_offset(struct i2c_emul *emul, int16_t *offset)
 }
 
 /** Set emulator accelerometer values to vector of three int16_t */
-static void set_emul_acc(struct i2c_emul *emul, int16_t *acc)
+static void set_emul_acc(const struct emul *emul, int16_t *acc)
 {
 	bma_emul_set_acc(emul, BMA_EMUL_AXIS_X, acc[0]);
 	bma_emul_set_acc(emul, BMA_EMUL_AXIS_Y, acc[1]);
@@ -99,7 +95,8 @@ static void compare_int3v_f(int16_t *exp_v, int16_t *v, int line)
 	int i;
 
 	for (i = 0; i < 3; i++) {
-		zassert_within(exp_v[i], v[i], V_EPS,
+		zassert_within(
+			exp_v[i], v[i], V_EPS,
 			"Expected [%d; %d; %d], got [%d; %d; %d]; line: %d",
 			exp_v[0], exp_v[1], exp_v[2], v[0], v[1], v[2], line);
 	}
@@ -122,7 +119,7 @@ struct reset_func_data {
  * accessing register data.ok_before_fail times. Error is returned during next
  * data.fail_attempts times.
  */
-static int emul_read_reset(struct i2c_emul *emul, int reg, uint8_t *buf,
+static int emul_read_reset(const struct emul *emul, int reg, uint8_t *buf,
 			   int bytes, void *data)
 {
 	struct reset_func_data *d = data;
@@ -157,26 +154,30 @@ static int emul_read_reset(struct i2c_emul *emul, int reg, uint8_t *buf,
  */
 ZTEST_USER(bma2x2, test_bma_get_offset)
 {
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BMA_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bma_get_i2c_common_data(emul);
 	int16_t ret_offset[3];
 	int16_t exp_offset[3];
 	int16_t temp;
 
-	emul = bma_emul_get(BMA_ORD);
-
 	/* Test fail on each axis */
-	i2c_common_emul_set_read_fail_reg(emul, BMA2x2_OFFSET_X_AXIS_ADDR);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  BMA2x2_OFFSET_X_AXIS_ADDR);
 	zassert_equal(EC_ERROR_INVAL,
 		      ms.drv->get_offset(&ms, ret_offset, &temp), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMA2x2_OFFSET_Y_AXIS_ADDR);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  BMA2x2_OFFSET_Y_AXIS_ADDR);
 	zassert_equal(EC_ERROR_INVAL,
 		      ms.drv->get_offset(&ms, ret_offset, &temp), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMA2x2_OFFSET_Z_AXIS_ADDR);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  BMA2x2_OFFSET_Z_AXIS_ADDR);
 	zassert_equal(EC_ERROR_INVAL,
 		      ms.drv->get_offset(&ms, ret_offset, &temp), NULL);
 
 	/* Do not fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Set emulator offset */
 	exp_offset[0] = BMA_EMUL_1G / 10;
@@ -208,26 +209,30 @@ ZTEST_USER(bma2x2, test_bma_get_offset)
  */
 ZTEST_USER(bma2x2, test_bma_set_offset)
 {
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BMA_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bma_get_i2c_common_data(emul);
 	int16_t ret_offset[3];
-	int16_t exp_offset[3];
+	int16_t exp_offset[3] = { 0, 0, 0 };
 	int16_t temp = 0;
 
-	emul = bma_emul_get(BMA_ORD);
-
 	/* Test fail on each axis */
-	i2c_common_emul_set_write_fail_reg(emul, BMA2x2_OFFSET_X_AXIS_ADDR);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   BMA2x2_OFFSET_X_AXIS_ADDR);
 	zassert_equal(EC_ERROR_INVAL, ms.drv->set_offset(&ms, exp_offset, temp),
 		      NULL);
-	i2c_common_emul_set_write_fail_reg(emul, BMA2x2_OFFSET_Y_AXIS_ADDR);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   BMA2x2_OFFSET_Y_AXIS_ADDR);
 	zassert_equal(EC_ERROR_INVAL, ms.drv->set_offset(&ms, exp_offset, temp),
 		      NULL);
-	i2c_common_emul_set_write_fail_reg(emul, BMA2x2_OFFSET_Z_AXIS_ADDR);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   BMA2x2_OFFSET_Z_AXIS_ADDR);
 	zassert_equal(EC_ERROR_INVAL, ms.drv->set_offset(&ms, exp_offset, temp),
 		      NULL);
 
 	/* Do not fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Set input offset */
 	exp_offset[0] = BMA_EMUL_1G / 10;
@@ -260,7 +265,7 @@ ZTEST_USER(bma2x2, test_bma_set_offset)
  * Try to set range and check if expected range was set in driver and in
  * emulator.
  */
-static void check_set_range_f(struct i2c_emul *emul, int range, int rnd,
+static void check_set_range_f(const struct emul *emul, int range, int rnd,
 			      int exp_range, int line)
 {
 	uint8_t exp_range_reg;
@@ -269,8 +274,8 @@ static void check_set_range_f(struct i2c_emul *emul, int range, int rnd,
 	zassert_equal(EC_SUCCESS, ms.drv->set_range(&ms, range, rnd),
 		      "set_range failed; line: %d", line);
 	zassert_equal(exp_range, ms.current_range,
-		      "Expected range %d, got %d; line %d",
-		      exp_range, ms.current_range, line);
+		      "Expected range %d, got %d; line %d", exp_range,
+		      ms.current_range, line);
 	range_reg = bma_emul_get_reg(emul, BMA2x2_RANGE_SELECT_ADDR);
 	range_reg &= BMA2x2_RANGE_SELECT_MSK;
 
@@ -299,23 +304,24 @@ static void check_set_range_f(struct i2c_emul *emul, int range, int rnd,
 		      "Expected range reg 0x%x, got 0x%x; line %d",
 		      exp_range_reg, range_reg, line);
 }
-#define check_set_range(emul, range, rnd, exp_range)	\
+#define check_set_range(emul, range, rnd, exp_range) \
 	check_set_range_f(emul, range, rnd, exp_range, __LINE__)
 
 /** Test set range with and without I2C errors. */
 ZTEST_USER(bma2x2, test_bma_set_range)
 {
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BMA_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bma_get_i2c_common_data(emul);
 	int start_range;
 
-	emul = bma_emul_get(BMA_ORD);
-
 	/* Setup starting range, shouldn't be changed on error */
 	start_range = 2;
 	ms.current_range = start_range;
 	bma_emul_set_reg(emul, BMA2x2_RANGE_SELECT_ADDR, BMA2x2_RANGE_2G);
 	/* Setup emulator fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, BMA2x2_RANGE_SELECT_ADDR);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  BMA2x2_RANGE_SELECT_ADDR);
 
 	/* Test fail on read */
 	zassert_equal(EC_ERROR_INVAL, ms.drv->set_range(&ms, 12, 0), NULL);
@@ -328,10 +334,12 @@ ZTEST_USER(bma2x2, test_bma_set_range)
 		      bma_emul_get_reg(emul, BMA2x2_RANGE_SELECT_ADDR), NULL);
 
 	/* Do not fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Setup emulator fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, BMA2x2_RANGE_SELECT_ADDR);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   BMA2x2_RANGE_SELECT_ADDR);
 
 	/* Test fail on write */
 	zassert_equal(EC_ERROR_INVAL, ms.drv->set_range(&ms, 12, 0), NULL);
@@ -344,7 +352,8 @@ ZTEST_USER(bma2x2, test_bma_set_range)
 		      bma_emul_get_reg(emul, BMA2x2_RANGE_SELECT_ADDR), NULL);
 
 	/* Do not fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test setting range with rounding down */
 	check_set_range(emul, 1, 0, 2);
@@ -379,47 +388,51 @@ ZTEST_USER(bma2x2, test_bma_set_range)
 ZTEST_USER(bma2x2, test_bma_init)
 {
 	struct reset_func_data reset_func_data;
-	struct i2c_emul *emul;
-
-	emul = bma_emul_get(BMA_ORD);
+	const struct emul *emul = EMUL_DT_GET(BMA_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bma_get_i2c_common_data(emul);
 
 	/* Setup emulator fail read function */
-	i2c_common_emul_set_read_fail_reg(emul, BMA2x2_CHIP_ID_ADDR);
+	i2c_common_emul_set_read_fail_reg(common_data, BMA2x2_CHIP_ID_ADDR);
 
 	/* Test fail on chip id read */
 	zassert_equal(EC_ERROR_UNKNOWN, ms.drv->init(&ms), NULL);
 
 	/* Disable failing on chip id read, but set wrong value */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 	bma_emul_set_reg(emul, BMA2x2_CHIP_ID_ADDR, 23);
 
 	/* Test wrong chip id */
 	zassert_equal(EC_ERROR_ACCESS_DENIED, ms.drv->init(&ms), NULL);
 
 	/* Set correct chip id, but fail on reset reg read */
-	i2c_common_emul_set_read_fail_reg(emul, BMA2x2_RST_ADDR);
+	i2c_common_emul_set_read_fail_reg(common_data, BMA2x2_RST_ADDR);
 	bma_emul_set_reg(emul, BMA2x2_CHIP_ID_ADDR, BMA255_CHIP_ID_MAJOR);
 
 	/* Test fail on reset register read */
 	zassert_equal(EC_ERROR_INVAL, ms.drv->init(&ms), NULL);
 
 	/* Do not fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Setup emulator fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, BMA2x2_RST_ADDR);
+	i2c_common_emul_set_write_fail_reg(common_data, BMA2x2_RST_ADDR);
 
 	/* Test fail on reset register write */
 	zassert_equal(EC_ERROR_INVAL, ms.drv->init(&ms), NULL);
 
 	/* Do not fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Setup emulator fail reset read function */
 	reset_func_data.ok_before_fail = 1;
 	reset_func_data.fail_attempts = 100;
 	reset_func_data.reset_value = 0;
-	i2c_common_emul_set_read_func(emul, emul_read_reset, &reset_func_data);
+	i2c_common_emul_set_read_func(common_data, emul_read_reset,
+				      &reset_func_data);
 
 	/* Test fail on too many reset read errors */
 	zassert_equal(EC_ERROR_TIMEOUT, ms.drv->init(&ms), NULL);
@@ -444,14 +457,14 @@ ZTEST_USER(bma2x2, test_bma_init)
 	zassert_equal(EC_RES_SUCCESS, ms.drv->init(&ms), NULL);
 
 	/* Remove custom emulator read function */
-	i2c_common_emul_set_read_func(emul, NULL, NULL);
+	i2c_common_emul_set_read_func(common_data, NULL, NULL);
 }
 
 /*
  * Try to set data rate and check if expected rate was set in driver and in
  * emulator.
  */
-static void check_set_rate_f(struct i2c_emul *emul, int rate, int rnd,
+static void check_set_rate_f(const struct emul *emul, int rate, int rnd,
 			     int exp_rate, int line)
 {
 	uint8_t exp_rate_reg;
@@ -500,21 +513,21 @@ static void check_set_rate_f(struct i2c_emul *emul, int rate, int rnd,
 	}
 
 	zassert_equal(exp_rate_reg, rate_reg,
-		      "Expected rate reg 0x%x, got 0x%x; line %d",
-		      exp_rate_reg, rate_reg, line);
+		      "Expected rate reg 0x%x, got 0x%x; line %d", exp_rate_reg,
+		      rate_reg, line);
 }
-#define check_set_rate(emul, rate, rnd, exp_rate)	\
+#define check_set_rate(emul, rate, rnd, exp_rate) \
 	check_set_rate_f(emul, rate, rnd, exp_rate, __LINE__)
 
 /** Test set and get rate with and without I2C errors. */
 ZTEST_USER(bma2x2, test_bma_rate)
 {
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BMA_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bma_get_i2c_common_data(emul);
 	uint8_t reg_rate;
 	int drv_rate;
 
-	emul = bma_emul_get(BMA_ORD);
-
 	/* Test setting rate with rounding down */
 	check_set_rate(emul, 1, 0, 7812);
 	check_set_rate(emul, 1, 0, 7812);
@@ -578,7 +591,7 @@ ZTEST_USER(bma2x2, test_bma_rate)
 	reg_rate = bma_emul_get_reg(emul, BMA2x2_BW_SELECT_ADDR);
 
 	/* Setup emulator fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, BMA2x2_BW_SELECT_ADDR);
+	i2c_common_emul_set_read_fail_reg(common_data, BMA2x2_BW_SELECT_ADDR);
 
 	/* Test fail on read */
 	zassert_equal(EC_ERROR_INVAL, ms.drv->set_data_rate(&ms, 15625, 0),
@@ -589,14 +602,15 @@ ZTEST_USER(bma2x2, test_bma_rate)
 	zassert_equal(EC_ERROR_INVAL, ms.drv->set_data_rate(&ms, 15625, 1),
 		      NULL);
 	zassert_equal(drv_rate, ms.drv->get_data_rate(&ms), NULL);
-	zassert_equal(reg_rate,
-		      bma_emul_get_reg(emul, BMA2x2_BW_SELECT_ADDR), NULL);
+	zassert_equal(reg_rate, bma_emul_get_reg(emul, BMA2x2_BW_SELECT_ADDR),
+		      NULL);
 
 	/* Do not fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Setup emulator fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, BMA2x2_BW_SELECT_ADDR);
+	i2c_common_emul_set_write_fail_reg(common_data, BMA2x2_BW_SELECT_ADDR);
 
 	/* Test fail on write */
 	zassert_equal(EC_ERROR_INVAL, ms.drv->set_data_rate(&ms, 15625, 0),
@@ -611,40 +625,42 @@ ZTEST_USER(bma2x2, test_bma_rate)
 		      NULL);
 
 	/* Do not fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
 }
 
 /** Test read with and without I2C errors. */
 ZTEST_USER(bma2x2, test_bma_read)
 {
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BMA_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bma_get_i2c_common_data(emul);
 	int16_t ret_acc[3];
 	int16_t exp_acc[3];
 	intv3_t ret_acc_v;
 
-	emul = bma_emul_get(BMA_ORD);
-
 	/* Set offset 0 to simplify test */
 	bma_emul_set_off(emul, BMA_EMUL_AXIS_X, 0);
 	bma_emul_set_off(emul, BMA_EMUL_AXIS_Y, 0);
 	bma_emul_set_off(emul, BMA_EMUL_AXIS_Z, 0);
 
 	/* Test fail on each axis */
-	i2c_common_emul_set_read_fail_reg(emul, BMA2x2_X_AXIS_LSB_ADDR);
+	i2c_common_emul_set_read_fail_reg(common_data, BMA2x2_X_AXIS_LSB_ADDR);
 	zassert_equal(EC_ERROR_INVAL, ms.drv->read(&ms, ret_acc_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMA2x2_X_AXIS_MSB_ADDR);
+	i2c_common_emul_set_read_fail_reg(common_data, BMA2x2_X_AXIS_MSB_ADDR);
 	zassert_equal(EC_ERROR_INVAL, ms.drv->read(&ms, ret_acc_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMA2x2_Y_AXIS_LSB_ADDR);
+	i2c_common_emul_set_read_fail_reg(common_data, BMA2x2_Y_AXIS_LSB_ADDR);
 	zassert_equal(EC_ERROR_INVAL, ms.drv->read(&ms, ret_acc_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMA2x2_Y_AXIS_MSB_ADDR);
+	i2c_common_emul_set_read_fail_reg(common_data, BMA2x2_Y_AXIS_MSB_ADDR);
 	zassert_equal(EC_ERROR_INVAL, ms.drv->read(&ms, ret_acc_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMA2x2_Z_AXIS_LSB_ADDR);
+	i2c_common_emul_set_read_fail_reg(common_data, BMA2x2_Z_AXIS_LSB_ADDR);
 	zassert_equal(EC_ERROR_INVAL, ms.drv->read(&ms, ret_acc_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMA2x2_Z_AXIS_MSB_ADDR);
+	i2c_common_emul_set_read_fail_reg(common_data, BMA2x2_Z_AXIS_MSB_ADDR);
 	zassert_equal(EC_ERROR_INVAL, ms.drv->read(&ms, ret_acc_v), NULL);
 
 	/* Do not fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Set input accelerometer values */
 	exp_acc[0] = BMA_EMUL_1G / 10;
@@ -706,7 +722,7 @@ struct calib_func_data {
  * error when offset control register is accessed when cal ready bit is not set
  * and data.read_fail is not zero.
  */
-static int emul_read_calib_func(struct i2c_emul *emul, int reg, uint8_t *val,
+static int emul_read_calib_func(const struct emul *emul, int reg, uint8_t *val,
 				int bytes, void *data)
 {
 	struct calib_func_data *d = data;
@@ -738,7 +754,7 @@ static int emul_read_calib_func(struct i2c_emul *emul, int reg, uint8_t *val,
  * calib_start field in data with time when offset compensation process was
  * triggerd.
  */
-static int emul_write_calib_func(struct i2c_emul *emul, int reg, uint8_t val,
+static int emul_write_calib_func(const struct emul *emul, int reg, uint8_t val,
 				 int bytes, void *data)
 {
 	struct calib_func_data *d = data;
@@ -759,19 +775,17 @@ static int emul_write_calib_func(struct i2c_emul *emul, int reg, uint8_t val,
 ZTEST_USER(bma2x2, test_bma_perform_calib)
 {
 	struct calib_func_data func_data;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BMA_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bma_get_i2c_common_data(emul);
 	int16_t start_off[3];
 	int16_t exp_off[3];
 	int16_t ret_off[3];
 	int range;
 	int rate;
-	mat33_fp_t rot = {
-		{ FLOAT_TO_FP(1), 0, 0},
-		{ 0, FLOAT_TO_FP(1), 0},
-		{ 0, 0, FLOAT_TO_FP(-1)}
-	};
-
-	emul = bma_emul_get(BMA_ORD);
+	mat33_fp_t rot = { { FLOAT_TO_FP(1), 0, 0 },
+			   { 0, FLOAT_TO_FP(1), 0 },
+			   { 0, 0, FLOAT_TO_FP(-1) } };
 
 	/* Range and rate cannot change after calibration */
 	range = 4;
@@ -800,8 +814,10 @@ ZTEST_USER(bma2x2, test_bma_perform_calib)
 	exp_off[2] = BMA_EMUL_1G - exp_off[2];
 
 	/* Setup emulator calibration functions */
-	i2c_common_emul_set_read_func(emul, emul_read_calib_func, &func_data);
-	i2c_common_emul_set_write_func(emul, emul_write_calib_func, &func_data);
+	i2c_common_emul_set_read_func(common_data, emul_read_calib_func,
+				      &func_data);
+	i2c_common_emul_set_write_func(common_data, emul_write_calib_func,
+				       &func_data);
 
 	/* Setup emulator to fail on first access to offset control register */
 	func_data.calib_start = k_uptime_get_32();
@@ -875,8 +891,8 @@ ZTEST_USER(bma2x2, test_bma_perform_calib)
 	/* Enable rotation with negative value on Z axis */
 	ms.rot_standard_ref = &rot;
 	/* Expected offset -1G - accelerometer[Z] */
-	exp_off[2] = -((int)BMA_EMUL_1G) - bma_emul_get_acc(emul,
-							    BMA_EMUL_AXIS_Z);
+	exp_off[2] =
+		-((int)BMA_EMUL_1G) - bma_emul_get_acc(emul, BMA_EMUL_AXIS_Z);
 
 	/* Test successful offset compenastion with negative Z rotation */
 	zassert_equal(EC_SUCCESS, ms.drv->perform_calib(&ms, 1), NULL);
@@ -899,8 +915,8 @@ ZTEST_USER(bma2x2, test_bma_perform_calib)
 	compare_int3v(exp_off, ret_off);
 
 	/* Remove custom emulator functions */
-	i2c_common_emul_set_read_func(emul, NULL, NULL);
-	i2c_common_emul_set_write_func(emul, NULL, NULL);
+	i2c_common_emul_set_read_func(common_data, NULL, NULL);
+	i2c_common_emul_set_write_func(common_data, NULL, NULL);
 }
 
 /** Test get resolution. */
@@ -917,5 +933,10 @@ static void *bma2x2_setup(void)
 	return NULL;
 }
 
-ZTEST_SUITE(bma2x2, drivers_predicate_post_main, bma2x2_setup, NULL, NULL,
-	    NULL);
+static void bma2x2_after(void *data)
+{
+	ms.rot_standard_ref = NULL;
+}
+
+ZTEST_SUITE(bma2x2, drivers_predicate_post_main, bma2x2_setup, NULL,
+	    bma2x2_after, NULL);
diff --git a/zephyr/test/drivers/src/bmi160.c b/zephyr/test/drivers/default/src/bmi160.c
index 56e38e6f9a..3f06e7f0fd 100644
--- a/zephyr/test/drivers/src/bmi160.c
+++ b/zephyr/test/drivers/default/src/bmi160.c
@@ -1,10 +1,10 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <zephyr/zephyr.h>
-#include <ztest.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
 
 #include "common.h"
 #include "i2c.h"
@@ -17,28 +17,27 @@
 #include "driver/accelgyro_bmi_common.h"
 #include "test/drivers/test_state.h"
 
-#define BMI_ORD			DT_DEP_ORD(DT_NODELABEL(accel_bmi160))
-#define BMI_ACC_SENSOR_ID	SENSOR_ID(DT_NODELABEL(ms_bmi160_accel))
-#define BMI_GYR_SENSOR_ID	SENSOR_ID(DT_NODELABEL(ms_bmi160_gyro))
-#define BMI_INT_EVENT		\
+#define BMI_NODE DT_NODELABEL(accel_bmi160)
+#define BMI_ACC_SENSOR_ID SENSOR_ID(DT_NODELABEL(ms_bmi160_accel))
+#define BMI_GYR_SENSOR_ID SENSOR_ID(DT_NODELABEL(ms_bmi160_gyro))
+#define BMI_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(SENSOR_ID(DT_ALIAS(bmi160_int)))
 
 /** How accurate comparision of vectors should be */
-#define V_EPS		8
+#define V_EPS 8
 
 /** Convert from one type of vector to another */
-#define convert_int3v_int16(v, r) do {	\
-		r[0] = v[0];		\
-		r[1] = v[1];		\
-		r[2] = v[2];		\
+#define convert_int3v_int16(v, r) \
+	do {                      \
+		r[0] = v[0];      \
+		r[1] = v[1];      \
+		r[2] = v[2];      \
 	} while (0)
 
 /** Rotation used in some tests */
-static const mat33_fp_t test_rotation = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t test_rotation = { { 0, FLOAT_TO_FP(1), 0 },
+					  { FLOAT_TO_FP(-1), 0, 0 },
+					  { 0, 0, FLOAT_TO_FP(-1) } };
 /** Rotate given vector by test rotation */
 static void rotate_int3v_by_test_rotation(intv3_t v)
 {
@@ -51,7 +50,7 @@ static void rotate_int3v_by_test_rotation(intv3_t v)
 }
 
 /** Set emulator accelerometer offset values to intv3_t vector */
-static void set_emul_acc_offset(struct i2c_emul *emul, intv3_t offset)
+static void set_emul_acc_offset(const struct emul *emul, intv3_t offset)
 {
 	bmi_emul_set_off(emul, BMI_EMUL_ACC_X, offset[0]);
 	bmi_emul_set_off(emul, BMI_EMUL_ACC_Y, offset[1]);
@@ -59,7 +58,7 @@ static void set_emul_acc_offset(struct i2c_emul *emul, intv3_t offset)
 }
 
 /** Save emulator accelerometer offset values to intv3_t vector */
-static void get_emul_acc_offset(struct i2c_emul *emul, intv3_t offset)
+static void get_emul_acc_offset(const struct emul *emul, intv3_t offset)
 {
 	offset[0] = bmi_emul_get_off(emul, BMI_EMUL_ACC_X);
 	offset[1] = bmi_emul_get_off(emul, BMI_EMUL_ACC_Y);
@@ -67,7 +66,7 @@ static void get_emul_acc_offset(struct i2c_emul *emul, intv3_t offset)
 }
 
 /** Set emulator accelerometer values to intv3_t vector */
-static void set_emul_acc(struct i2c_emul *emul, intv3_t acc)
+static void set_emul_acc(const struct emul *emul, intv3_t acc)
 {
 	bmi_emul_set_value(emul, BMI_EMUL_ACC_X, acc[0]);
 	bmi_emul_set_value(emul, BMI_EMUL_ACC_Y, acc[1]);
@@ -75,7 +74,7 @@ static void set_emul_acc(struct i2c_emul *emul, intv3_t acc)
 }
 
 /** Set emulator gyroscope offset values to intv3_t vector */
-static void set_emul_gyr_offset(struct i2c_emul *emul, intv3_t offset)
+static void set_emul_gyr_offset(const struct emul *emul, intv3_t offset)
 {
 	bmi_emul_set_off(emul, BMI_EMUL_GYR_X, offset[0]);
 	bmi_emul_set_off(emul, BMI_EMUL_GYR_Y, offset[1]);
@@ -83,7 +82,7 @@ static void set_emul_gyr_offset(struct i2c_emul *emul, intv3_t offset)
 }
 
 /** Save emulator gyroscope offset values to intv3_t vector */
-static void get_emul_gyr_offset(struct i2c_emul *emul, intv3_t offset)
+static void get_emul_gyr_offset(const struct emul *emul, intv3_t offset)
 {
 	offset[0] = bmi_emul_get_off(emul, BMI_EMUL_GYR_X);
 	offset[1] = bmi_emul_get_off(emul, BMI_EMUL_GYR_Y);
@@ -91,7 +90,7 @@ static void get_emul_gyr_offset(struct i2c_emul *emul, intv3_t offset)
 }
 
 /** Set emulator gyroscope values to vector of three int16_t */
-static void set_emul_gyr(struct i2c_emul *emul, intv3_t gyr)
+static void set_emul_gyr(const struct emul *emul, intv3_t gyr)
 {
 	bmi_emul_set_value(emul, BMI_EMUL_GYR_X, gyr[0]);
 	bmi_emul_set_value(emul, BMI_EMUL_GYR_Y, gyr[1]);
@@ -125,7 +124,8 @@ static void compare_int3v_f(intv3_t exp_v, intv3_t v, int eps, int line)
 	int i;
 
 	for (i = 0; i < 3; i++) {
-		zassert_within(exp_v[i], v[i], eps,
+		zassert_within(
+			exp_v[i], v[i], eps,
 			"Expected [%d; %d; %d], got [%d; %d; %d]; line: %d",
 			exp_v[0], exp_v[1], exp_v[2], v[0], v[1], v[2], line);
 	}
@@ -137,13 +137,14 @@ static void compare_int3v_f(intv3_t exp_v, intv3_t v, int eps, int line)
 ZTEST_USER(bmi160, test_bmi_acc_get_offset)
 {
 	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bmi_get_i2c_common_data(emul);
 	int16_t ret[3];
 	intv3_t ret_v;
 	intv3_t exp_v;
 	int16_t temp;
 
-	emul = bmi_emul_get(BMI_ORD);
 	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
 
 	/* Set emulator offset */
@@ -157,23 +158,23 @@ ZTEST_USER(bmi160, test_bmi_acc_get_offset)
 	exp_v[2] = -1000 / 30;
 
 	/* Test fail on offset read */
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_OFFSET_ACC70);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_OFFSET_ACC70);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->get_offset(ms, ret, &temp),
 		      NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_OFFSET_ACC70 + 1);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_OFFSET_ACC70 + 1);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->get_offset(ms, ret, &temp),
 		      NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_OFFSET_ACC70 + 2);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_OFFSET_ACC70 + 2);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->get_offset(ms, ret, &temp),
 		      NULL);
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Disable rotation */
 	ms->rot_standard_ref = NULL;
 
 	/* Test get offset without rotation */
-	zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp),
-		      NULL);
+	zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp), NULL);
 	zassert_equal(temp, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP, NULL);
 	convert_int3v_int16(ret, ret_v);
 	compare_int3v(exp_v, ret_v);
@@ -183,8 +184,7 @@ ZTEST_USER(bmi160, test_bmi_acc_get_offset)
 	rotate_int3v_by_test_rotation(exp_v);
 
 	/* Test get offset with rotation */
-	zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp),
-		      NULL);
+	zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp), NULL);
 	zassert_equal(temp, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP, NULL);
 	convert_int3v_int16(ret, ret_v);
 	compare_int3v(exp_v, ret_v);
@@ -194,17 +194,19 @@ ZTEST_USER(bmi160, test_bmi_acc_get_offset)
 ZTEST_USER(bmi160, test_bmi_gyr_get_offset)
 {
 	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bmi_get_i2c_common_data(emul);
 	int16_t ret[3];
 	intv3_t ret_v;
 	intv3_t exp_v;
 	int16_t temp;
 
-	emul = bmi_emul_get(BMI_ORD);
 	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
 
 	/* Do not fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Set emulator offset */
 	exp_v[0] = BMI_EMUL_125_DEG_S / 100;
@@ -217,26 +219,26 @@ ZTEST_USER(bmi160, test_bmi_gyr_get_offset)
 	exp_v[2] = -125000 / 300;
 
 	/* Test fail on offset read */
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_OFFSET_GYR70);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_OFFSET_GYR70);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->get_offset(ms, ret, &temp),
 		      NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_OFFSET_GYR70 + 1);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_OFFSET_GYR70 + 1);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->get_offset(ms, ret, &temp),
 		      NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_OFFSET_GYR70 + 2);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_OFFSET_GYR70 + 2);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->get_offset(ms, ret, &temp),
 		      NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_OFFSET_EN_GYR98);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_OFFSET_EN_GYR98);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->get_offset(ms, ret, &temp),
 		      NULL);
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Disable rotation */
 	ms->rot_standard_ref = NULL;
 
 	/* Test get offset without rotation */
-	zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp),
-		      NULL);
+	zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp), NULL);
 	zassert_equal(temp, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP, NULL);
 	convert_int3v_int16(ret, ret_v);
 	compare_int3v_eps(exp_v, ret_v, 64);
@@ -246,8 +248,7 @@ ZTEST_USER(bmi160, test_bmi_gyr_get_offset)
 	rotate_int3v_by_test_rotation(exp_v);
 
 	/* Test get offset with rotation */
-	zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp),
-		      NULL);
+	zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp), NULL);
 	zassert_equal(temp, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP, NULL);
 	convert_int3v_int16(ret, ret_v);
 	compare_int3v_eps(exp_v, ret_v, 64);
@@ -260,36 +261,42 @@ ZTEST_USER(bmi160, test_bmi_gyr_get_offset)
 ZTEST_USER(bmi160, test_bmi_acc_set_offset)
 {
 	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bmi_get_i2c_common_data(emul);
 	int16_t input_v[3];
 	int16_t temp = 0;
 	intv3_t ret_v;
 	intv3_t exp_v;
 
-	emul = bmi_emul_get(BMI_ORD);
 	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
 
 	/* Test fail on OFFSET EN GYR98 register read and write */
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_OFFSET_EN_GYR98);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_OFFSET_EN_GYR98);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
 		      NULL);
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-	i2c_common_emul_set_write_fail_reg(emul, BMI160_OFFSET_EN_GYR98);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(common_data, BMI160_OFFSET_EN_GYR98);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
 		      NULL);
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test fail on offset write */
-	i2c_common_emul_set_write_fail_reg(emul, BMI160_OFFSET_ACC70);
+	i2c_common_emul_set_write_fail_reg(common_data, BMI160_OFFSET_ACC70);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
 		      NULL);
-	i2c_common_emul_set_write_fail_reg(emul, BMI160_OFFSET_ACC70 + 1);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   BMI160_OFFSET_ACC70 + 1);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
 		      NULL);
-	i2c_common_emul_set_write_fail_reg(emul, BMI160_OFFSET_ACC70 + 2);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   BMI160_OFFSET_ACC70 + 2);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
 		      NULL);
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Set input offset */
 	exp_v[0] = BMI_EMUL_1G / 10;
@@ -312,7 +319,8 @@ ZTEST_USER(bmi160, test_bmi_acc_set_offset)
 	compare_int3v_eps(exp_v, ret_v, 64);
 	/* Accelerometer offset should be enabled */
 	zassert_true(bmi_emul_get_reg(emul, BMI160_OFFSET_EN_GYR98) &
-		     BMI160_OFFSET_ACC_EN, NULL);
+			     BMI160_OFFSET_ACC_EN,
+		     NULL);
 
 	/* Setup rotation and rotate input for set_offset function */
 	ms->rot_standard_ref = &test_rotation;
@@ -326,7 +334,8 @@ ZTEST_USER(bmi160, test_bmi_acc_set_offset)
 	compare_int3v_eps(exp_v, ret_v, 64);
 	/* Accelerometer offset should be enabled */
 	zassert_true(bmi_emul_get_reg(emul, BMI160_OFFSET_EN_GYR98) &
-		     BMI160_OFFSET_ACC_EN, NULL);
+			     BMI160_OFFSET_ACC_EN,
+		     NULL);
 }
 
 /**
@@ -336,36 +345,42 @@ ZTEST_USER(bmi160, test_bmi_acc_set_offset)
 ZTEST_USER(bmi160, test_bmi_gyr_set_offset)
 {
 	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bmi_get_i2c_common_data(emul);
 	int16_t input_v[3];
 	int16_t temp = 0;
 	intv3_t ret_v;
 	intv3_t exp_v;
 
-	emul = bmi_emul_get(BMI_ORD);
 	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
 
 	/* Test fail on OFFSET EN GYR98 register read and write */
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_OFFSET_EN_GYR98);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_OFFSET_EN_GYR98);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
 		      NULL);
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-	i2c_common_emul_set_write_fail_reg(emul, BMI160_OFFSET_EN_GYR98);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(common_data, BMI160_OFFSET_EN_GYR98);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
 		      NULL);
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test fail on offset write */
-	i2c_common_emul_set_write_fail_reg(emul, BMI160_OFFSET_GYR70);
+	i2c_common_emul_set_write_fail_reg(common_data, BMI160_OFFSET_GYR70);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
 		      NULL);
-	i2c_common_emul_set_write_fail_reg(emul, BMI160_OFFSET_GYR70 + 1);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   BMI160_OFFSET_GYR70 + 1);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
 		      NULL);
-	i2c_common_emul_set_write_fail_reg(emul, BMI160_OFFSET_GYR70 + 2);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   BMI160_OFFSET_GYR70 + 2);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
 		      NULL);
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Set input offset */
 	exp_v[0] = BMI_EMUL_125_DEG_S / 100;
@@ -384,7 +399,8 @@ ZTEST_USER(bmi160, test_bmi_gyr_set_offset)
 	compare_int3v(exp_v, ret_v);
 	/* Gyroscope offset should be enabled */
 	zassert_true(bmi_emul_get_reg(emul, BMI160_OFFSET_EN_GYR98) &
-		     BMI160_OFFSET_GYRO_EN, NULL);
+			     BMI160_OFFSET_GYRO_EN,
+		     NULL);
 
 	/* Setup rotation and rotate input for set_offset function */
 	ms->rot_standard_ref = &test_rotation;
@@ -397,14 +413,15 @@ ZTEST_USER(bmi160, test_bmi_gyr_set_offset)
 	get_emul_gyr_offset(emul, ret_v);
 	compare_int3v(exp_v, ret_v);
 	zassert_true(bmi_emul_get_reg(emul, BMI160_OFFSET_EN_GYR98) &
-		     BMI160_OFFSET_GYRO_EN, NULL);
+			     BMI160_OFFSET_GYRO_EN,
+		     NULL);
 }
 
 /**
  * Try to set accelerometer range and check if expected range was set
  * in driver and in emulator.
  */
-static void check_set_acc_range_f(struct i2c_emul *emul,
+static void check_set_acc_range_f(const struct emul *emul,
 				  struct motion_sensor_t *ms, int range,
 				  int rnd, int exp_range, int line)
 {
@@ -414,8 +431,8 @@ static void check_set_acc_range_f(struct i2c_emul *emul,
 	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, range, rnd),
 		      "set_range failed; line: %d", line);
 	zassert_equal(exp_range, ms->current_range,
-		      "Expected range %d, got %d; line %d",
-		      exp_range, ms->current_range, line);
+		      "Expected range %d, got %d; line %d", exp_range,
+		      ms->current_range, line);
 	range_reg = bmi_emul_get_reg(emul, BMI160_ACC_RANGE);
 
 	switch (exp_range) {
@@ -443,17 +460,18 @@ static void check_set_acc_range_f(struct i2c_emul *emul,
 		      "Expected range reg 0x%x, got 0x%x; line %d",
 		      exp_range_reg, range_reg, line);
 }
-#define check_set_acc_range(emul, ms, range, rnd, exp_range)	\
+#define check_set_acc_range(emul, ms, range, rnd, exp_range) \
 	check_set_acc_range_f(emul, ms, range, rnd, exp_range, __LINE__)
 
 /** Test set accelerometer range with and without I2C errors */
 ZTEST_USER(bmi160, test_bmi_acc_set_range)
 {
 	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bmi_get_i2c_common_data(emul);
 	int start_range;
 
-	emul = bmi_emul_get(BMI_ORD);
 	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
 
 	/* Setup starting range, shouldn't be changed on error */
@@ -461,20 +479,21 @@ ZTEST_USER(bmi160, test_bmi_acc_set_range)
 	ms->current_range = start_range;
 	bmi_emul_set_reg(emul, BMI160_ACC_RANGE, BMI160_GSEL_2G);
 	/* Setup emulator fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, BMI160_ACC_RANGE);
+	i2c_common_emul_set_write_fail_reg(common_data, BMI160_ACC_RANGE);
 
 	/* Test fail on write */
 	zassert_equal(EC_ERROR_INVAL, ms->drv->set_range(ms, 12, 0), NULL);
 	zassert_equal(start_range, ms->current_range, NULL);
-	zassert_equal(BMI160_GSEL_2G,
-		      bmi_emul_get_reg(emul, BMI160_ACC_RANGE), NULL);
+	zassert_equal(BMI160_GSEL_2G, bmi_emul_get_reg(emul, BMI160_ACC_RANGE),
+		      NULL);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->set_range(ms, 12, 1), NULL);
 	zassert_equal(start_range, ms->current_range, NULL);
-	zassert_equal(BMI160_GSEL_2G,
-		      bmi_emul_get_reg(emul, BMI160_ACC_RANGE), NULL);
+	zassert_equal(BMI160_GSEL_2G, bmi_emul_get_reg(emul, BMI160_ACC_RANGE),
+		      NULL);
 
 	/* Do not fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test setting range with rounding down */
 	check_set_acc_range(emul, ms, 1, 0, 2);
@@ -509,7 +528,7 @@ ZTEST_USER(bmi160, test_bmi_acc_set_range)
  * Try to set gyroscope range and check if expected range was set in driver and
  * in emulator.
  */
-static void check_set_gyr_range_f(struct i2c_emul *emul,
+static void check_set_gyr_range_f(const struct emul *emul,
 				  struct motion_sensor_t *ms, int range,
 				  int rnd, int exp_range, int line)
 {
@@ -519,8 +538,8 @@ static void check_set_gyr_range_f(struct i2c_emul *emul,
 	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, range, rnd),
 		      "set_range failed; line: %d", line);
 	zassert_equal(exp_range, ms->current_range,
-		      "Expected range %d, got %d; line %d",
-		      exp_range, ms->current_range, line);
+		      "Expected range %d, got %d; line %d", exp_range,
+		      ms->current_range, line);
 	range_reg = bmi_emul_get_reg(emul, BMI160_GYR_RANGE);
 
 	switch (exp_range) {
@@ -551,17 +570,18 @@ static void check_set_gyr_range_f(struct i2c_emul *emul,
 		      "Expected range reg 0x%x, got 0x%x; line %d",
 		      exp_range_reg, range_reg, line);
 }
-#define check_set_gyr_range(emul, ms, range, rnd, exp_range)	\
+#define check_set_gyr_range(emul, ms, range, rnd, exp_range) \
 	check_set_gyr_range_f(emul, ms, range, rnd, exp_range, __LINE__)
 
 /** Test set gyroscope range with and without I2C errors */
 ZTEST_USER(bmi160, test_bmi_gyr_set_range)
 {
 	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bmi_get_i2c_common_data(emul);
 	int start_range;
 
-	emul = bmi_emul_get(BMI_ORD);
 	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
 
 	/* Setup starting range, shouldn't be changed on error */
@@ -569,7 +589,7 @@ ZTEST_USER(bmi160, test_bmi_gyr_set_range)
 	ms->current_range = start_range;
 	bmi_emul_set_reg(emul, BMI160_GYR_RANGE, BMI160_DPS_SEL_250);
 	/* Setup emulator fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, BMI160_GYR_RANGE);
+	i2c_common_emul_set_write_fail_reg(common_data, BMI160_GYR_RANGE);
 
 	/* Test fail on write */
 	zassert_equal(EC_ERROR_INVAL, ms->drv->set_range(ms, 125, 0), NULL);
@@ -582,7 +602,8 @@ ZTEST_USER(bmi160, test_bmi_gyr_set_range)
 		      bmi_emul_get_reg(emul, BMI160_GYR_RANGE), NULL);
 
 	/* Do not fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test setting range with rounding down */
 	check_set_gyr_range(emul, ms, 1, 0, 125);
@@ -643,7 +664,7 @@ ZTEST_USER(bmi160, test_bmi_get_resolution)
  * Try to set accelerometer data rate and check if expected rate was set
  * in driver and in emulator.
  */
-static void check_set_acc_rate_f(struct i2c_emul *emul,
+static void check_set_acc_rate_f(const struct emul *emul,
 				 struct motion_sensor_t *ms, int rate, int rnd,
 				 int exp_rate, int line)
 {
@@ -693,22 +714,23 @@ static void check_set_acc_rate_f(struct i2c_emul *emul,
 	}
 
 	zassert_equal(exp_rate_reg, rate_reg,
-		      "Expected rate reg 0x%x, got 0x%x; line %d",
-		      exp_rate_reg, rate_reg, line);
+		      "Expected rate reg 0x%x, got 0x%x; line %d", exp_rate_reg,
+		      rate_reg, line);
 }
-#define check_set_acc_rate(emul, ms, rate, rnd, exp_rate)	\
+#define check_set_acc_rate(emul, ms, rate, rnd, exp_rate) \
 	check_set_acc_rate_f(emul, ms, rate, rnd, exp_rate, __LINE__)
 
 /** Test set and get accelerometer rate with and without I2C errors */
 ZTEST_USER(bmi160, test_bmi_acc_rate)
 {
 	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bmi_get_i2c_common_data(emul);
 	uint8_t reg_rate;
 	int pmu_status;
 	int drv_rate;
 
-	emul = bmi_emul_get(BMI_ORD);
 	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
 
 	/* Test setting rate with rounding down */
@@ -750,8 +772,8 @@ ZTEST_USER(bmi160, test_bmi_acc_rate)
 	check_set_acc_rate(emul, ms, 200000, 1, 200000);
 
 	/* Test out of range rate with rounding down */
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 1, 0), NULL);
+	zassert_equal(EC_RES_INVALID_PARAM, ms->drv->set_data_rate(ms, 1, 0),
+		      NULL);
 	zassert_equal(EC_RES_INVALID_PARAM,
 		      ms->drv->set_data_rate(ms, 12499, 0), NULL);
 	zassert_equal(EC_RES_INVALID_PARAM,
@@ -760,10 +782,10 @@ ZTEST_USER(bmi160, test_bmi_acc_rate)
 		      ms->drv->set_data_rate(ms, 2000000, 0), NULL);
 
 	/* Test out of range rate with rounding up */
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 1, 1), NULL);
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 6250, 1), NULL);
+	zassert_equal(EC_RES_INVALID_PARAM, ms->drv->set_data_rate(ms, 1, 1),
+		      NULL);
+	zassert_equal(EC_RES_INVALID_PARAM, ms->drv->set_data_rate(ms, 6250, 1),
+		      NULL);
 	zassert_equal(EC_RES_INVALID_PARAM,
 		      ms->drv->set_data_rate(ms, 200001, 1), NULL);
 	zassert_equal(EC_RES_INVALID_PARAM,
@@ -776,7 +798,7 @@ ZTEST_USER(bmi160, test_bmi_acc_rate)
 	reg_rate = bmi_emul_get_reg(emul, BMI160_ACC_CONF);
 
 	/* Setup emulator fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_ACC_CONF);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_ACC_CONF);
 
 	/* Test fail on read */
 	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 50000, 0),
@@ -789,10 +811,11 @@ ZTEST_USER(bmi160, test_bmi_acc_rate)
 	zassert_equal(reg_rate, bmi_emul_get_reg(emul, BMI160_ACC_CONF), NULL);
 
 	/* Do not fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Setup emulator fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, BMI160_ACC_CONF);
+	i2c_common_emul_set_write_fail_reg(common_data, BMI160_ACC_CONF);
 
 	/* Test fail on write */
 	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 50000, 0),
@@ -805,7 +828,8 @@ ZTEST_USER(bmi160, test_bmi_acc_rate)
 	zassert_equal(reg_rate, bmi_emul_get_reg(emul, BMI160_ACC_CONF), NULL);
 
 	/* Do not fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test disabling sensor */
 	pmu_status = BMI160_PMU_NORMAL << BMI160_PMU_ACC_OFFSET;
@@ -832,7 +856,7 @@ ZTEST_USER(bmi160, test_bmi_acc_rate)
  * Try to set gyroscope data rate and check if expected rate was set
  * in driver and in emulator.
  */
-static void check_set_gyr_rate_f(struct i2c_emul *emul,
+static void check_set_gyr_rate_f(const struct emul *emul,
 				 struct motion_sensor_t *ms, int rate, int rnd,
 				 int exp_rate, int line)
 {
@@ -882,22 +906,23 @@ static void check_set_gyr_rate_f(struct i2c_emul *emul,
 	}
 
 	zassert_equal(exp_rate_reg, rate_reg,
-		      "Expected rate reg 0x%x, got 0x%x; line %d",
-		      exp_rate_reg, rate_reg, line);
+		      "Expected rate reg 0x%x, got 0x%x; line %d", exp_rate_reg,
+		      rate_reg, line);
 }
-#define check_set_gyr_rate(emul, ms, rate, rnd, exp_rate)	\
+#define check_set_gyr_rate(emul, ms, rate, rnd, exp_rate) \
 	check_set_gyr_rate_f(emul, ms, rate, rnd, exp_rate, __LINE__)
 
 /** Test set and get gyroscope rate with and without I2C errors */
 ZTEST_USER(bmi160, test_bmi_gyr_rate)
 {
 	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bmi_get_i2c_common_data(emul);
 	uint8_t reg_rate;
 	int pmu_status;
 	int drv_rate;
 
-	emul = bmi_emul_get(BMI_ORD);
 	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
 
 	/* Test setting rate with rounding down */
@@ -933,8 +958,8 @@ ZTEST_USER(bmi160, test_bmi_gyr_rate)
 	check_set_gyr_rate(emul, ms, 200000, 1, 200000);
 
 	/* Test out of range rate with rounding down */
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 1, 0), NULL);
+	zassert_equal(EC_RES_INVALID_PARAM, ms->drv->set_data_rate(ms, 1, 0),
+		      NULL);
 	zassert_equal(EC_RES_INVALID_PARAM,
 		      ms->drv->set_data_rate(ms, 24999, 0), NULL);
 	zassert_equal(EC_RES_INVALID_PARAM,
@@ -943,8 +968,8 @@ ZTEST_USER(bmi160, test_bmi_gyr_rate)
 		      ms->drv->set_data_rate(ms, 4000000, 0), NULL);
 
 	/* Test out of range rate with rounding up */
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 1, 1), NULL);
+	zassert_equal(EC_RES_INVALID_PARAM, ms->drv->set_data_rate(ms, 1, 1),
+		      NULL);
 	zassert_equal(EC_RES_INVALID_PARAM,
 		      ms->drv->set_data_rate(ms, 12499, 1), NULL);
 	zassert_equal(EC_RES_INVALID_PARAM,
@@ -959,7 +984,7 @@ ZTEST_USER(bmi160, test_bmi_gyr_rate)
 	reg_rate = bmi_emul_get_reg(emul, BMI160_GYR_CONF);
 
 	/* Setup emulator fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_GYR_CONF);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_GYR_CONF);
 
 	/* Test fail on read */
 	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 50000, 0),
@@ -972,10 +997,11 @@ ZTEST_USER(bmi160, test_bmi_gyr_rate)
 	zassert_equal(reg_rate, bmi_emul_get_reg(emul, BMI160_GYR_CONF), NULL);
 
 	/* Do not fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Setup emulator fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, BMI160_GYR_CONF);
+	i2c_common_emul_set_write_fail_reg(common_data, BMI160_GYR_CONF);
 
 	/* Test fail on write */
 	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 50000, 0),
@@ -988,7 +1014,8 @@ ZTEST_USER(bmi160, test_bmi_gyr_rate)
 	zassert_equal(reg_rate, bmi_emul_get_reg(emul, BMI160_GYR_CONF), NULL);
 
 	/* Do not fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test disabling sensor */
 	pmu_status = BMI160_PMU_NORMAL << BMI160_PMU_ACC_OFFSET;
@@ -1019,7 +1046,7 @@ ZTEST_USER(bmi160, test_bmi_scale)
 {
 	struct motion_sensor_t *ms;
 	int16_t ret_scale[3];
-	int16_t exp_scale[3] = {100, 231, 421};
+	int16_t exp_scale[3] = { 100, 231, 421 };
 	int16_t t;
 
 	/* Test accelerometer */
@@ -1049,27 +1076,29 @@ ZTEST_USER(bmi160, test_bmi_scale)
 ZTEST_USER(bmi160, test_bmi_read_temp)
 {
 	struct motion_sensor_t *ms_acc, *ms_gyr;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bmi_get_i2c_common_data(emul);
 	int ret_temp;
 	int exp_temp;
 
-	emul = bmi_emul_get(BMI_ORD);
 	ms_acc = &motion_sensors[BMI_ACC_SENSOR_ID];
 	ms_gyr = &motion_sensors[BMI_GYR_SENSOR_ID];
 
 	/* Setup emulator fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_TEMPERATURE_0);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_TEMPERATURE_0);
 	zassert_equal(EC_ERROR_NOT_POWERED,
 		      ms_acc->drv->read_temp(ms_acc, &ret_temp), NULL);
 	zassert_equal(EC_ERROR_NOT_POWERED,
 		      ms_gyr->drv->read_temp(ms_gyr, &ret_temp), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_TEMPERATURE_1);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_TEMPERATURE_1);
 	zassert_equal(EC_ERROR_NOT_POWERED,
 		      ms_acc->drv->read_temp(ms_acc, &ret_temp), NULL);
 	zassert_equal(EC_ERROR_NOT_POWERED,
 		      ms_gyr->drv->read_temp(ms_gyr, &ret_temp), NULL);
 	/* Do not fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Fail on invalid temperature */
 	bmi_emul_set_reg(emul, BMI160_TEMPERATURE_0, 0x00);
@@ -1128,14 +1157,15 @@ ZTEST_USER(bmi160, test_bmi_read_temp)
 ZTEST_USER(bmi160, test_bmi_acc_read)
 {
 	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bmi_get_i2c_common_data(emul);
 	intv3_t ret_v;
 	intv3_t exp_v;
-	int16_t scale[3] = {MOTION_SENSE_DEFAULT_SCALE,
-			    MOTION_SENSE_DEFAULT_SCALE,
-			    MOTION_SENSE_DEFAULT_SCALE};
+	int16_t scale[3] = { MOTION_SENSE_DEFAULT_SCALE,
+			     MOTION_SENSE_DEFAULT_SCALE,
+			     MOTION_SENSE_DEFAULT_SCALE };
 
-	emul = bmi_emul_get(BMI_ORD);
 	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
 
 	/* Set offset 0 to simplify test */
@@ -1144,10 +1174,11 @@ ZTEST_USER(bmi160, test_bmi_acc_read)
 	bmi_emul_set_off(emul, BMI_EMUL_ACC_Z, 0);
 
 	/* Fail on read status */
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_STATUS);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_STATUS);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
 
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* When not ready, driver should return saved raw value */
 	exp_v[0] = 100;
@@ -1215,20 +1246,21 @@ ZTEST_USER(bmi160, test_bmi_acc_read)
 	compare_int3v(exp_v, ret_v);
 
 	/* Fail on read of data registers */
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_ACC_X_L_G);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_ACC_X_L_G);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_ACC_X_H_G);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_ACC_X_H_G);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_ACC_Y_L_G);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_ACC_Y_L_G);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_ACC_Y_H_G);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_ACC_Y_H_G);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_ACC_Z_L_G);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_ACC_Z_L_G);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_ACC_Z_H_G);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_ACC_Z_H_G);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
 
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 	ms->rot_standard_ref = NULL;
 }
 
@@ -1236,14 +1268,15 @@ ZTEST_USER(bmi160, test_bmi_acc_read)
 ZTEST_USER(bmi160, test_bmi_gyr_read)
 {
 	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bmi_get_i2c_common_data(emul);
 	intv3_t ret_v;
 	intv3_t exp_v;
-	int16_t scale[3] = {MOTION_SENSE_DEFAULT_SCALE,
-			    MOTION_SENSE_DEFAULT_SCALE,
-			    MOTION_SENSE_DEFAULT_SCALE};
+	int16_t scale[3] = { MOTION_SENSE_DEFAULT_SCALE,
+			     MOTION_SENSE_DEFAULT_SCALE,
+			     MOTION_SENSE_DEFAULT_SCALE };
 
-	emul = bmi_emul_get(BMI_ORD);
 	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
 
 	/* Set offset 0 to simplify test */
@@ -1252,10 +1285,11 @@ ZTEST_USER(bmi160, test_bmi_gyr_read)
 	bmi_emul_set_off(emul, BMI_EMUL_GYR_Z, 0);
 
 	/* Fail on read status */
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_STATUS);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_STATUS);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
 
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* When not ready, driver should return saved raw value */
 	exp_v[0] = 100;
@@ -1323,20 +1357,21 @@ ZTEST_USER(bmi160, test_bmi_gyr_read)
 	compare_int3v(exp_v, ret_v);
 
 	/* Fail on read of data registers */
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_GYR_X_L_G);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_GYR_X_L_G);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_GYR_X_H_G);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_GYR_X_H_G);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_GYR_Y_L_G);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_GYR_Y_L_G);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_GYR_Y_H_G);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_GYR_Y_H_G);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_GYR_Z_L_G);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_GYR_Z_L_G);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_GYR_Z_H_G);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_GYR_Z_H_G);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
 
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 	ms->rot_standard_ref = NULL;
 }
 
@@ -1344,7 +1379,7 @@ ZTEST_USER(bmi160, test_bmi_gyr_read)
  * Custom emulatro read function which always return not ready STATUS register.
  * Used in calibration test.
  */
-static int emul_nrdy(struct i2c_emul *emul, int reg, uint8_t *val, int byte,
+static int emul_nrdy(const struct emul *emul, int reg, uint8_t *val, int byte,
 		     void *data)
 {
 	if (reg == BMI160_STATUS) {
@@ -1361,20 +1396,19 @@ static int emul_nrdy(struct i2c_emul *emul, int reg, uint8_t *val, int byte,
 ZTEST_USER(bmi160, test_bmi_acc_perform_calib)
 {
 	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bmi_get_i2c_common_data(emul);
 	uint8_t pmu_status;
 	intv3_t start_off;
 	intv3_t exp_off;
 	intv3_t ret_off;
 	int range;
 	int rate;
-	mat33_fp_t rot = {
-		{ FLOAT_TO_FP(1), 0, 0},
-		{ 0, FLOAT_TO_FP(1), 0},
-		{ 0, 0, FLOAT_TO_FP(-1)}
-	};
+	mat33_fp_t rot = { { FLOAT_TO_FP(1), 0, 0 },
+			   { 0, FLOAT_TO_FP(1), 0 },
+			   { 0, 0, FLOAT_TO_FP(-1) } };
 
-	emul = bmi_emul_get(BMI_ORD);
 	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
 
 	/* Enable sensors */
@@ -1409,13 +1443,13 @@ ZTEST_USER(bmi160, test_bmi_acc_perform_calib)
 	exp_off[2] = BMI_EMUL_1G - exp_off[2];
 
 	/* Test fail on rate set */
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_ACC_CONF);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_ACC_CONF);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->perform_calib(ms, 1), NULL);
 	zassert_equal(range, ms->current_range, NULL);
 	zassert_equal(rate, ms->drv->get_data_rate(ms), NULL);
 
 	/* Test fail on status read */
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_STATUS);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_STATUS);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->perform_calib(ms, 1), NULL);
 	zassert_equal(range, ms->current_range, NULL);
 	zassert_equal(rate, ms->drv->get_data_rate(ms), NULL);
@@ -1423,13 +1457,14 @@ ZTEST_USER(bmi160, test_bmi_acc_perform_calib)
 	bmi_emul_set_reg(emul, BMI160_CMD_REG, BMI160_CMD_NOOP);
 
 	/* Test fail on data not ready */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-	i2c_common_emul_set_read_func(emul, emul_nrdy, NULL);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_func(common_data, emul_nrdy, NULL);
 	zassert_equal(EC_RES_TIMEOUT, ms->drv->perform_calib(ms, 1), NULL);
 	zassert_equal(range, ms->current_range, NULL);
 	zassert_equal(rate, ms->drv->get_data_rate(ms), NULL);
 	/* Remove custom emulator read function */
-	i2c_common_emul_set_read_func(emul, NULL, NULL);
+	i2c_common_emul_set_read_func(common_data, NULL, NULL);
 	/* Stop fast offset compensation before next test */
 	bmi_emul_set_reg(emul, BMI160_CMD_REG, BMI160_CMD_NOOP);
 
@@ -1447,7 +1482,8 @@ ZTEST_USER(bmi160, test_bmi_acc_perform_calib)
 	compare_int3v_eps(exp_off, ret_off, 64);
 	/* Acelerometer offset should be enabled */
 	zassert_true(bmi_emul_get_reg(emul, BMI160_OFFSET_EN_GYR98) &
-		     BMI160_OFFSET_ACC_EN, NULL);
+			     BMI160_OFFSET_ACC_EN,
+		     NULL);
 
 	/* Enable rotation with negative value on Z axis */
 	ms->rot_standard_ref = &rot;
@@ -1463,7 +1499,8 @@ ZTEST_USER(bmi160, test_bmi_acc_perform_calib)
 	compare_int3v_eps(exp_off, ret_off, 64);
 	/* Acelerometer offset should be enabled */
 	zassert_true(bmi_emul_get_reg(emul, BMI160_OFFSET_EN_GYR98) &
-		     BMI160_OFFSET_ACC_EN, NULL);
+			     BMI160_OFFSET_ACC_EN,
+		     NULL);
 
 	/* Set positive rotation on Z axis */
 	rot[2][2] = FLOAT_TO_FP(1);
@@ -1479,7 +1516,8 @@ ZTEST_USER(bmi160, test_bmi_acc_perform_calib)
 	compare_int3v_eps(exp_off, ret_off, 64);
 	/* Acelerometer offset should be enabled */
 	zassert_true(bmi_emul_get_reg(emul, BMI160_OFFSET_EN_GYR98) &
-		     BMI160_OFFSET_ACC_EN, NULL);
+			     BMI160_OFFSET_ACC_EN,
+		     NULL);
 	/* Disable rotation */
 	ms->rot_standard_ref = NULL;
 }
@@ -1488,7 +1526,9 @@ ZTEST_USER(bmi160, test_bmi_acc_perform_calib)
 ZTEST_USER(bmi160, test_bmi_gyr_perform_calib)
 {
 	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bmi_get_i2c_common_data(emul);
 	uint8_t pmu_status;
 	intv3_t start_off;
 	intv3_t exp_off;
@@ -1496,7 +1536,6 @@ ZTEST_USER(bmi160, test_bmi_gyr_perform_calib)
 	int range;
 	int rate;
 
-	emul = bmi_emul_get(BMI_ORD);
 	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
 
 	/* Enable sensors */
@@ -1533,13 +1572,13 @@ ZTEST_USER(bmi160, test_bmi_gyr_perform_calib)
 	zassert_equal(rate, ms->drv->get_data_rate(ms), NULL);
 
 	/* Test fail on rate set */
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_GYR_CONF);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_GYR_CONF);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->perform_calib(ms, 1), NULL);
 	zassert_equal(range, ms->current_range, NULL);
 	zassert_equal(rate, ms->drv->get_data_rate(ms), NULL);
 
 	/* Test fail on status read */
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_STATUS);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_STATUS);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->perform_calib(ms, 1), NULL);
 	zassert_equal(range, ms->current_range, NULL);
 	zassert_equal(rate, ms->drv->get_data_rate(ms), NULL);
@@ -1547,13 +1586,14 @@ ZTEST_USER(bmi160, test_bmi_gyr_perform_calib)
 	bmi_emul_set_reg(emul, BMI160_CMD_REG, BMI160_CMD_NOOP);
 
 	/* Test fail on data not ready */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-	i2c_common_emul_set_read_func(emul, emul_nrdy, NULL);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_func(common_data, emul_nrdy, NULL);
 	zassert_equal(EC_RES_TIMEOUT, ms->drv->perform_calib(ms, 1), NULL);
 	zassert_equal(range, ms->current_range, NULL);
 	zassert_equal(rate, ms->drv->get_data_rate(ms), NULL);
 	/* Remove custom emulator read function */
-	i2c_common_emul_set_read_func(emul, NULL, NULL);
+	i2c_common_emul_set_read_func(common_data, NULL, NULL);
 	/* Stop fast offset compensation before next test */
 	bmi_emul_set_reg(emul, BMI160_CMD_REG, BMI160_CMD_NOOP);
 
@@ -1569,16 +1609,15 @@ ZTEST_USER(bmi160, test_bmi_gyr_perform_calib)
 	compare_int3v_eps(exp_off, ret_off, 32);
 	/* Gyroscope offset should be enabled */
 	zassert_true(bmi_emul_get_reg(emul, BMI160_OFFSET_EN_GYR98) &
-		     BMI160_OFFSET_GYRO_EN, NULL);
+			     BMI160_OFFSET_GYRO_EN,
+		     NULL);
 }
 
 /** Test init function of BMI160 accelerometer and gyroscope sensors */
 ZTEST_USER(bmi160, test_bmi_init)
 {
 	struct motion_sensor_t *ms_acc, *ms_gyr;
-	struct i2c_emul *emul;
 
-	emul = bmi_emul_get(BMI_ORD);
 	ms_acc = &motion_sensors[BMI_ACC_SENSOR_ID];
 	ms_gyr = &motion_sensors[BMI_GYR_SENSOR_ID];
 
@@ -1598,7 +1637,7 @@ struct fifo_func_data {
  * to value passed as additional data. It sets interrupt registers to 0 after
  * access.
  */
-static int emul_fifo_func(struct i2c_emul *emul, int reg, uint8_t *val,
+static int emul_fifo_func(const struct emul *emul, int reg, uint8_t *val,
 			  int byte, void *data)
 {
 	struct fifo_func_data *d = data;
@@ -1622,9 +1661,8 @@ static int emul_fifo_func(struct i2c_emul *emul, int reg, uint8_t *val,
  */
 static void check_fifo_f(struct motion_sensor_t *ms_acc,
 			 struct motion_sensor_t *ms_gyr,
-			 struct bmi_emul_frame *frame,
-			 int acc_range, int gyr_range,
-			 int line)
+			 struct bmi_emul_frame *frame, int acc_range,
+			 int gyr_range, int line)
 {
 	struct ec_response_motion_sensor_data vector;
 	struct bmi_emul_frame *f_acc, *f_gyr;
@@ -1705,7 +1743,7 @@ static void check_fifo_f(struct motion_sensor_t *ms_acc,
 	zassert_is_null(f_gyr, "Not all gyroscope frames are read, line %d",
 			line);
 }
-#define check_fifo(ms_acc, ms_gyr, frame, acc_range, gyr_range)		\
+#define check_fifo(ms_acc, ms_gyr, frame, acc_range, gyr_range) \
 	check_fifo_f(ms_acc, ms_gyr, frame, acc_range, gyr_range, __LINE__)
 
 /** Test irq handler of accelerometer sensor */
@@ -1714,12 +1752,13 @@ ZTEST_USER(bmi160, test_bmi_acc_fifo)
 	struct motion_sensor_t *ms, *ms_gyr;
 	struct fifo_func_data func_data;
 	struct bmi_emul_frame f[3];
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bmi_get_i2c_common_data(emul);
 	int gyr_range = 125;
 	int acc_range = 2;
 	int event;
 
-	emul = bmi_emul_get(BMI_ORD);
 	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
 	ms_gyr = &motion_sensors[BMI_GYR_SENSOR_ID];
 
@@ -1738,11 +1777,12 @@ ZTEST_USER(bmi160, test_bmi_acc_fifo)
 	event = BMI_INT_EVENT;
 
 	/* Test fail to read interrupt status registers */
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_INT_STATUS_0);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_INT_STATUS_0);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->irq_handler(ms, &event), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_INT_STATUS_1);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_INT_STATUS_1);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->irq_handler(ms, &event), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test no interrupt */
 	bmi_emul_set_reg(emul, BMI160_INT_STATUS_0, 0);
@@ -1755,7 +1795,7 @@ ZTEST_USER(bmi160, test_bmi_acc_fifo)
 	check_fifo(ms, ms_gyr, NULL, acc_range, gyr_range);
 
 	/* Set custom function for FIFO test */
-	i2c_common_emul_set_read_func(emul, emul_fifo_func, &func_data);
+	i2c_common_emul_set_read_func(common_data, emul_fifo_func, &func_data);
 	/* Set range */
 	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, acc_range, 0), NULL);
 	zassert_equal(EC_SUCCESS, ms_gyr->drv->set_range(ms_gyr, gyr_range, 0),
@@ -1838,7 +1878,7 @@ ZTEST_USER(bmi160, test_bmi_acc_fifo)
 	check_fifo(ms, ms_gyr, f, acc_range, gyr_range);
 
 	/* Remove custom emulator read function */
-	i2c_common_emul_set_read_func(emul, NULL, NULL);
+	i2c_common_emul_set_read_func(common_data, NULL, NULL);
 }
 
 /** Test irq handler of gyroscope sensor */
@@ -1859,8 +1899,7 @@ ZTEST_USER(bmi160, test_bmi_gyr_fifo)
 ZTEST_USER(bmi160, test_bmi_sec_raw_read8)
 {
 	struct motion_sensor_t *ms = &motion_sensors[BMI_ACC_SENSOR_ID];
-	struct i2c_emul *emul = bmi_emul_get(BMI_ORD);
-
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
 	uint8_t expected_read_value = 0xAA;
 	uint8_t requested_reg_addr = 0x55;
 	uint8_t actual_reg_addr;
@@ -1892,8 +1931,7 @@ ZTEST_USER(bmi160, test_bmi_sec_raw_read8)
 ZTEST_USER(bmi160, test_bmi_sec_raw_write8)
 {
 	struct motion_sensor_t *ms = &motion_sensors[BMI_ACC_SENSOR_ID];
-	struct i2c_emul *emul = bmi_emul_get(BMI_ORD);
-
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
 	uint8_t expected_write_value = 0xAB;
 	uint8_t requested_reg_addr = 0x56;
 	uint8_t actual_reg_addr;
@@ -1926,8 +1964,7 @@ ZTEST_USER(bmi160, test_bmi_set_offset_invalid_type)
 {
 	struct motion_sensor_t ms_fake;
 	int ret;
-
-	int16_t unused_offset;
+	int16_t unused_offset = 0;
 	int16_t temp = 0;
 
 	/* make a copy of the accel motion sensor so we modify its type */
@@ -1961,7 +1998,7 @@ ZTEST_USER(bmi160, test_bmi_perform_calib_invalid_type)
 /** Test reading the onboard temperature sensor */
 ZTEST_USER(bmi160, test_bmi_temp_sensor)
 {
-	struct i2c_emul *emul = bmi_emul_get(BMI_ORD);
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
 	int ret;
 
 	/* Part 1:
@@ -2022,24 +2059,27 @@ ZTEST_USER(bmi160, test_bmi_interrupt_handler)
 
 /* Make an I2C emulator mock wrapped in FFF for use with test_bmi_init_chip_id()
  */
-FAKE_VALUE_FUNC(int, bmi_init_chip_id_mock_write_fn, struct i2c_emul *, int,
+FAKE_VALUE_FUNC(int, bmi_init_chip_id_mock_write_fn, const struct emul *, int,
 		uint8_t, int, void *);
 
 /** Test handling of invalid or unreadable chip IDs in init() */
 ZTEST_USER(bmi160, test_bmi_init_chip_id)
 {
 	struct motion_sensor_t *ms = &motion_sensors[BMI_ACC_SENSOR_ID];
-	struct i2c_emul *emul = bmi_emul_get(BMI_ORD);
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bmi_get_i2c_common_data(emul);
 	int ret;
 
 	/* Part 1: Cannot read the Chip ID register */
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_CHIP_ID);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_CHIP_ID);
 	ret = ms->drv->init(ms);
 
 	zassert_equal(ret, EC_ERROR_UNKNOWN, "Expected %d but got %d",
 		      EC_ERROR_UNKNOWN, ret);
 
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Part 2: Incorrect chip ID - this triggers a series of writes in an
 	 * attempt to 'unlock' the chip.
@@ -2052,8 +2092,8 @@ ZTEST_USER(bmi160, test_bmi_init_chip_id)
 
 	RESET_FAKE(bmi_init_chip_id_mock_write_fn);
 	bmi_init_chip_id_mock_write_fn_fake.return_val = 1;
-	i2c_common_emul_set_write_func(emul, bmi_init_chip_id_mock_write_fn,
-				       NULL);
+	i2c_common_emul_set_write_func(common_data,
+				       bmi_init_chip_id_mock_write_fn, NULL);
 
 	/* Return a phony chip ID */
 	bmi_emul_set_reg(emul, BMI160_CHIP_ID, 0xFF);
@@ -2076,7 +2116,73 @@ ZTEST_USER(bmi160, test_bmi_init_chip_id)
 	MOCK_ASSERT_I2C_WRITE(bmi_init_chip_id_mock_write_fn, 4,
 			      BMI160_CMD_EXT_MODE_ADDR, 0);
 
-	i2c_common_emul_set_write_func(emul, NULL, NULL);
+	i2c_common_emul_set_write_func(common_data, NULL, NULL);
+}
+
+static void bmi160_before(void *fixture)
+{
+	ARG_UNUSED(fixture);
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bmi_get_i2c_common_data(emul);
+	struct motion_sensor_t *acc_ms;
+	struct motion_sensor_t *gyr_ms;
+
+	acc_ms = &motion_sensors[BMI_ACC_SENSOR_ID];
+	gyr_ms = &motion_sensors[BMI_GYR_SENSOR_ID];
+
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	bmi_emul_set_reg(emul, BMI160_CHIP_ID, 0xd1);
+
+	/* Disable rotation */
+	gyr_ms->rot_standard_ref = NULL;
+	acc_ms->rot_standard_ref = NULL;
+
+	zassume_equal(EC_SUCCESS, acc_ms->drv->set_data_rate(acc_ms, 50000, 0),
+		      NULL);
+	zassume_equal(EC_SUCCESS, gyr_ms->drv->set_data_rate(gyr_ms, 50000, 0),
+		      NULL);
+}
+
+static void bmi160_after(void *state)
+{
+	ARG_UNUSED(state);
+	struct motion_sensor_t *acc_ms, *gyr_ms;
+
+	acc_ms = &motion_sensors[BMI_ACC_SENSOR_ID];
+	gyr_ms = &motion_sensors[BMI_GYR_SENSOR_ID];
+
+	acc_ms->drv->set_data_rate(acc_ms, 0, 0);
+	gyr_ms->drv->set_data_rate(gyr_ms, 0, 0);
+}
+
+ZTEST_SUITE(bmi160, drivers_predicate_pre_main, NULL, bmi160_before,
+	    bmi160_after, NULL);
+
+/** Cause an interrupt and verify the motion_sense task handled it. */
+ZTEST_USER(bmi160_tasks, test_irq_handling)
+{
+	struct bmi_emul_frame f[3];
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+
+	f[0].type = BMI_EMUL_FRAME_ACC;
+	f[0].acc_x = BMI_EMUL_1G / 10;
+	f[0].acc_y = BMI_EMUL_1G / 20;
+	f[0].acc_z = -(int)BMI_EMUL_1G / 30;
+	f[0].next = NULL;
+	bmi_emul_append_frame(emul, f);
+	bmi_emul_set_reg(emul, BMI160_INT_STATUS_0, BMI160_FWM_INT & 0xff);
+	bmi_emul_set_reg(emul, BMI160_INT_STATUS_1,
+			 (BMI160_FWM_INT >> 8) & 0xff);
+
+	bmi160_interrupt(0);
+	k_sleep(K_SECONDS(10));
+
+	/* Verify that the motion_sense_task read it. */
+	zassert_equal(bmi_emul_get_reg(emul, BMI160_INT_STATUS_0), 0, NULL);
+	zassert_equal(bmi_emul_get_reg(emul, BMI160_INT_STATUS_1), 0, NULL);
 }
 
-ZTEST_SUITE(bmi160, drivers_predicate_post_main, NULL, NULL, NULL, NULL);
+ZTEST_SUITE(bmi160_tasks, drivers_predicate_post_main, NULL, bmi160_before,
+	    bmi160_after, NULL);
diff --git a/zephyr/test/drivers/src/bmi260.c b/zephyr/test/drivers/default/src/bmi260.c
index abcab72898..9295d631ca 100644
--- a/zephyr/test/drivers/src/bmi260.c
+++ b/zephyr/test/drivers/default/src/bmi260.c
@@ -1,11 +1,11 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <fff.h>
-#include <zephyr/zephyr.h>
-#include <ztest.h>
+#include <zephyr/fff.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
 
 #include "common.h"
 #include "i2c.h"
@@ -18,28 +18,27 @@
 #include "test/drivers/test_mocks.h"
 #include "test/drivers/test_state.h"
 
-#define BMI_ORD			DT_DEP_ORD(DT_NODELABEL(accel_bmi260))
-#define BMI_ACC_SENSOR_ID	SENSOR_ID(DT_NODELABEL(ms_bmi260_accel))
-#define BMI_GYR_SENSOR_ID	SENSOR_ID(DT_NODELABEL(ms_bmi260_gyro))
-#define BMI_INT_EVENT		\
+#define BMI_NODE DT_NODELABEL(accel_bmi260)
+#define BMI_ACC_SENSOR_ID SENSOR_ID(DT_NODELABEL(ms_bmi260_accel))
+#define BMI_GYR_SENSOR_ID SENSOR_ID(DT_NODELABEL(ms_bmi260_gyro))
+#define BMI_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(SENSOR_ID(DT_ALIAS(bmi260_int)))
 
 /** How accurate comparision of vectors should be */
-#define V_EPS		8
+#define V_EPS 8
 
 /** Convert from one type of vector to another */
-#define convert_int3v_int16(v, r) do {	\
-		r[0] = v[0];		\
-		r[1] = v[1];		\
-		r[2] = v[2];		\
+#define convert_int3v_int16(v, r) \
+	do {                      \
+		r[0] = v[0];      \
+		r[1] = v[1];      \
+		r[2] = v[2];      \
 	} while (0)
 
 /** Rotation used in some tests */
-static const mat33_fp_t test_rotation = {
-	{ 0, FLOAT_TO_FP(1), 0},
-	{ FLOAT_TO_FP(-1), 0, 0},
-	{ 0, 0, FLOAT_TO_FP(-1)}
-};
+static const mat33_fp_t test_rotation = { { 0, FLOAT_TO_FP(1), 0 },
+					  { FLOAT_TO_FP(-1), 0, 0 },
+					  { 0, 0, FLOAT_TO_FP(-1) } };
 /** Rotate given vector by test rotation */
 static void rotate_int3v_by_test_rotation(intv3_t v)
 {
@@ -52,7 +51,7 @@ static void rotate_int3v_by_test_rotation(intv3_t v)
 }
 
 /** Set emulator accelerometer offset values to intv3_t vector */
-static void set_emul_acc_offset(struct i2c_emul *emul, intv3_t offset)
+static void set_emul_acc_offset(const struct emul *emul, intv3_t offset)
 {
 	bmi_emul_set_off(emul, BMI_EMUL_ACC_X, offset[0]);
 	bmi_emul_set_off(emul, BMI_EMUL_ACC_Y, offset[1]);
@@ -60,7 +59,7 @@ static void set_emul_acc_offset(struct i2c_emul *emul, intv3_t offset)
 }
 
 /** Save emulator accelerometer offset values to intv3_t vector */
-static void get_emul_acc_offset(struct i2c_emul *emul, intv3_t offset)
+static void get_emul_acc_offset(const struct emul *emul, intv3_t offset)
 {
 	offset[0] = bmi_emul_get_off(emul, BMI_EMUL_ACC_X);
 	offset[1] = bmi_emul_get_off(emul, BMI_EMUL_ACC_Y);
@@ -68,7 +67,7 @@ static void get_emul_acc_offset(struct i2c_emul *emul, intv3_t offset)
 }
 
 /** Set emulator accelerometer values to intv3_t vector */
-static void set_emul_acc(struct i2c_emul *emul, intv3_t acc)
+static void set_emul_acc(const struct emul *emul, intv3_t acc)
 {
 	bmi_emul_set_value(emul, BMI_EMUL_ACC_X, acc[0]);
 	bmi_emul_set_value(emul, BMI_EMUL_ACC_Y, acc[1]);
@@ -76,7 +75,7 @@ static void set_emul_acc(struct i2c_emul *emul, intv3_t acc)
 }
 
 /** Set emulator gyroscope offset values to intv3_t vector */
-static void set_emul_gyr_offset(struct i2c_emul *emul, intv3_t offset)
+static void set_emul_gyr_offset(const struct emul *emul, intv3_t offset)
 {
 	bmi_emul_set_off(emul, BMI_EMUL_GYR_X, offset[0]);
 	bmi_emul_set_off(emul, BMI_EMUL_GYR_Y, offset[1]);
@@ -84,7 +83,7 @@ static void set_emul_gyr_offset(struct i2c_emul *emul, intv3_t offset)
 }
 
 /** Save emulator gyroscope offset values to intv3_t vector */
-static void get_emul_gyr_offset(struct i2c_emul *emul, intv3_t offset)
+static void get_emul_gyr_offset(const struct emul *emul, intv3_t offset)
 {
 	offset[0] = bmi_emul_get_off(emul, BMI_EMUL_GYR_X);
 	offset[1] = bmi_emul_get_off(emul, BMI_EMUL_GYR_Y);
@@ -92,7 +91,7 @@ static void get_emul_gyr_offset(struct i2c_emul *emul, intv3_t offset)
 }
 
 /** Set emulator gyroscope values to vector of three int16_t */
-static void set_emul_gyr(struct i2c_emul *emul, intv3_t gyr)
+static void set_emul_gyr(const struct emul *emul, intv3_t gyr)
 {
 	bmi_emul_set_value(emul, BMI_EMUL_GYR_X, gyr[0]);
 	bmi_emul_set_value(emul, BMI_EMUL_GYR_Y, gyr[1]);
@@ -126,7 +125,8 @@ static void compare_int3v_f(intv3_t exp_v, intv3_t v, int eps, int line)
 	int i;
 
 	for (i = 0; i < 3; i++) {
-		zassert_within(exp_v[i], v[i], eps,
+		zassert_within(
+			exp_v[i], v[i], eps,
 			"Expected [%d; %d; %d], got [%d; %d; %d]; line: %d",
 			exp_v[0], exp_v[1], exp_v[2], v[0], v[1], v[2], line);
 	}
@@ -138,8 +138,8 @@ static void compare_int3v_f(intv3_t exp_v, intv3_t v, int eps, int line)
  * Custom emulator read function which always return INIT OK status in
  * INTERNAL STATUS register. Used in init test.
  */
-static int emul_init_ok(struct i2c_emul *emul, int reg, uint8_t *val, int byte,
-			void *data)
+static int emul_init_ok(const struct emul *emul, int reg, uint8_t *val,
+			int byte, void *data)
 {
 	bmi_emul_set_reg(emul, BMI260_INTERNAL_STATUS, BMI260_INIT_OK);
 
@@ -151,9 +151,11 @@ static void bmi_init_emul(void)
 {
 	struct motion_sensor_t *ms_acc;
 	struct motion_sensor_t *ms_gyr;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data;
+	int ret;
 
-	emul = bmi_emul_get(BMI_ORD);
+	common_data = emul_bmi_get_i2c_common_data(emul);
 	ms_acc = &motion_sensors[BMI_ACC_SENSOR_ID];
 	ms_gyr = &motion_sensors[BMI_GYR_SENSOR_ID];
 
@@ -162,24 +164,30 @@ static void bmi_init_emul(void)
 	 * BMI260_INTERNAL_STATUS register, because init function triggers reset
 	 * which clears value set in this register before test.
 	 */
-	i2c_common_emul_set_read_func(emul, emul_init_ok, NULL);
-	zassert_equal(EC_RES_SUCCESS, ms_acc->drv->init(ms_acc), NULL);
-	zassert_equal(EC_RES_SUCCESS, ms_gyr->drv->init(ms_gyr), NULL);
+	i2c_common_emul_set_read_func(common_data, emul_init_ok, NULL);
+
+	ret = ms_acc->drv->init(ms_acc);
+	zassert_equal(EC_RES_SUCCESS, ret, "Got accel init error %d", ret);
+
+	ret = ms_gyr->drv->init(ms_gyr);
+	zassert_equal(EC_RES_SUCCESS, ret, "Got gyro init error %d", ret);
+
 	/* Remove custom emulator read function */
-	i2c_common_emul_set_read_func(emul, NULL, NULL);
+	i2c_common_emul_set_read_func(common_data, NULL, NULL);
 }
 
 /** Test get accelerometer offset with and without rotation */
 ZTEST_USER(bmi260, test_bmi_acc_get_offset)
 {
 	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data;
 	int16_t ret[3];
 	intv3_t ret_v;
 	intv3_t exp_v;
 	int16_t temp;
 
-	emul = bmi_emul_get(BMI_ORD);
+	common_data = emul_bmi_get_i2c_common_data(emul);
 	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
 
 	/* Set emulator offset */
@@ -193,23 +201,23 @@ ZTEST_USER(bmi260, test_bmi_acc_get_offset)
 	exp_v[2] = -1000 / 30;
 
 	/* Test fail on offset read */
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_OFFSET_ACC70);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_OFFSET_ACC70);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->get_offset(ms, ret, &temp),
 		      NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_OFFSET_ACC70 + 1);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_OFFSET_ACC70 + 1);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->get_offset(ms, ret, &temp),
 		      NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_OFFSET_ACC70 + 2);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_OFFSET_ACC70 + 2);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->get_offset(ms, ret, &temp),
 		      NULL);
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Disable rotation */
 	ms->rot_standard_ref = NULL;
 
 	/* Test get offset without rotation */
-	zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp),
-		      NULL);
+	zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp), NULL);
 	zassert_equal(temp, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP, NULL);
 	convert_int3v_int16(ret, ret_v);
 	compare_int3v(exp_v, ret_v);
@@ -219,8 +227,7 @@ ZTEST_USER(bmi260, test_bmi_acc_get_offset)
 	rotate_int3v_by_test_rotation(exp_v);
 
 	/* Test get offset with rotation */
-	zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp),
-		      NULL);
+	zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp), NULL);
 	zassert_equal(temp, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP, NULL);
 	convert_int3v_int16(ret, ret_v);
 	compare_int3v(exp_v, ret_v);
@@ -230,17 +237,19 @@ ZTEST_USER(bmi260, test_bmi_acc_get_offset)
 ZTEST_USER(bmi260, test_bmi_gyr_get_offset)
 {
 	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data;
 	int16_t ret[3];
 	intv3_t ret_v;
 	intv3_t exp_v;
 	int16_t temp;
 
-	emul = bmi_emul_get(BMI_ORD);
+	common_data = emul_bmi_get_i2c_common_data(emul);
 	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
 
 	/* Do not fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Set emulator offset */
 	exp_v[0] = BMI_EMUL_125_DEG_S / 100;
@@ -253,26 +262,26 @@ ZTEST_USER(bmi260, test_bmi_gyr_get_offset)
 	exp_v[2] = -125000 / 300;
 
 	/* Test fail on offset read */
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_OFFSET_GYR70);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_OFFSET_GYR70);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->get_offset(ms, ret, &temp),
 		      NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_OFFSET_GYR70 + 1);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_OFFSET_GYR70 + 1);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->get_offset(ms, ret, &temp),
 		      NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_OFFSET_GYR70 + 2);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_OFFSET_GYR70 + 2);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->get_offset(ms, ret, &temp),
 		      NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI160_OFFSET_EN_GYR98);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI160_OFFSET_EN_GYR98);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->get_offset(ms, ret, &temp),
 		      NULL);
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Disable rotation */
 	ms->rot_standard_ref = NULL;
 
 	/* Test get offset without rotation */
-	zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp),
-		      NULL);
+	zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp), NULL);
 	zassert_equal(temp, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP, NULL);
 	convert_int3v_int16(ret, ret_v);
 	compare_int3v_eps(exp_v, ret_v, 64);
@@ -282,8 +291,7 @@ ZTEST_USER(bmi260, test_bmi_gyr_get_offset)
 	rotate_int3v_by_test_rotation(exp_v);
 
 	/* Test get offset with rotation */
-	zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp),
-		      NULL);
+	zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp), NULL);
 	zassert_equal(temp, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP, NULL);
 	convert_int3v_int16(ret, ret_v);
 	compare_int3v_eps(exp_v, ret_v, 64);
@@ -296,37 +304,43 @@ ZTEST_USER(bmi260, test_bmi_gyr_get_offset)
 ZTEST_USER(bmi260, test_bmi_acc_set_offset)
 {
 	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
-	int16_t input_v[3];
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data;
+	int16_t input_v[3] = { 0, 0, 0 };
 	int16_t temp = 0;
 	intv3_t ret_v;
 	intv3_t exp_v;
 	uint8_t nv_c;
 
-	emul = bmi_emul_get(BMI_ORD);
+	common_data = emul_bmi_get_i2c_common_data(emul);
 	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
 
 	/* Test fail on NV CONF register read and write */
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_NV_CONF);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_NV_CONF);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
 		      NULL);
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-	i2c_common_emul_set_write_fail_reg(emul, BMI260_NV_CONF);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(common_data, BMI260_NV_CONF);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
 		      NULL);
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test fail on offset write */
-	i2c_common_emul_set_write_fail_reg(emul, BMI160_OFFSET_ACC70);
+	i2c_common_emul_set_write_fail_reg(common_data, BMI160_OFFSET_ACC70);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
 		      NULL);
-	i2c_common_emul_set_write_fail_reg(emul, BMI160_OFFSET_ACC70 + 1);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   BMI160_OFFSET_ACC70 + 1);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
 		      NULL);
-	i2c_common_emul_set_write_fail_reg(emul, BMI160_OFFSET_ACC70 + 2);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   BMI160_OFFSET_ACC70 + 2);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
 		      NULL);
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Setup NV_CONF register value */
 	bmi_emul_set_reg(emul, BMI260_NV_CONF, 0x7);
@@ -352,8 +366,8 @@ ZTEST_USER(bmi260, test_bmi_acc_set_offset)
 	nv_c = bmi_emul_get_reg(emul, BMI260_NV_CONF);
 	/* Only ACC_OFFSET_EN bit should be changed */
 	zassert_equal(0x7 | BMI260_ACC_OFFSET_EN, nv_c,
-		      "Expected 0x%x, got 0x%x",
-		      0x7 | BMI260_ACC_OFFSET_EN, nv_c);
+		      "Expected 0x%x, got 0x%x", 0x7 | BMI260_ACC_OFFSET_EN,
+		      nv_c);
 
 	/* Setup NV_CONF register value */
 	bmi_emul_set_reg(emul, BMI260_NV_CONF, 0);
@@ -380,36 +394,42 @@ ZTEST_USER(bmi260, test_bmi_acc_set_offset)
 ZTEST_USER(bmi260, test_bmi_gyr_set_offset)
 {
 	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data;
 	int16_t input_v[3];
 	int16_t temp = 0;
 	intv3_t ret_v;
 	intv3_t exp_v;
 
-	emul = bmi_emul_get(BMI_ORD);
+	common_data = emul_bmi_get_i2c_common_data(emul);
 	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
 
 	/* Test fail on OFFSET EN GYR98 register read and write */
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_OFFSET_EN_GYR98);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_OFFSET_EN_GYR98);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
 		      NULL);
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-	i2c_common_emul_set_write_fail_reg(emul, BMI260_OFFSET_EN_GYR98);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(common_data, BMI260_OFFSET_EN_GYR98);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
 		      NULL);
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test fail on offset write */
-	i2c_common_emul_set_write_fail_reg(emul, BMI260_OFFSET_GYR70);
+	i2c_common_emul_set_write_fail_reg(common_data, BMI260_OFFSET_GYR70);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
 		      NULL);
-	i2c_common_emul_set_write_fail_reg(emul, BMI260_OFFSET_GYR70 + 1);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   BMI260_OFFSET_GYR70 + 1);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
 		      NULL);
-	i2c_common_emul_set_write_fail_reg(emul, BMI260_OFFSET_GYR70 + 2);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   BMI260_OFFSET_GYR70 + 2);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->set_offset(ms, input_v, temp),
 		      NULL);
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Set input offset */
 	exp_v[0] = BMI_EMUL_125_DEG_S / 100;
@@ -432,7 +452,8 @@ ZTEST_USER(bmi260, test_bmi_gyr_set_offset)
 	compare_int3v_eps(exp_v, ret_v, 32);
 	/* Gyroscope offset should be enabled */
 	zassert_true(bmi_emul_get_reg(emul, BMI260_OFFSET_EN_GYR98) &
-		     BMI260_OFFSET_GYRO_EN, NULL);
+			     BMI260_OFFSET_GYRO_EN,
+		     NULL);
 
 	/* Setup rotation and rotate input for set_offset function */
 	ms->rot_standard_ref = &test_rotation;
@@ -445,14 +466,15 @@ ZTEST_USER(bmi260, test_bmi_gyr_set_offset)
 	get_emul_gyr_offset(emul, ret_v);
 	compare_int3v_eps(exp_v, ret_v, 32);
 	zassert_true(bmi_emul_get_reg(emul, BMI260_OFFSET_EN_GYR98) &
-		     BMI260_OFFSET_GYRO_EN, NULL);
+			     BMI260_OFFSET_GYRO_EN,
+		     NULL);
 }
 
 /**
  * Try to set accelerometer range and check if expected range was set
  * in driver and in emulator.
  */
-static void check_set_acc_range_f(struct i2c_emul *emul,
+static void check_set_acc_range_f(const struct emul *emul,
 				  struct motion_sensor_t *ms, int range,
 				  int rnd, int exp_range, int line)
 {
@@ -462,8 +484,8 @@ static void check_set_acc_range_f(struct i2c_emul *emul,
 	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, range, rnd),
 		      "set_range failed; line: %d", line);
 	zassert_equal(exp_range, ms->current_range,
-		      "Expected range %d, got %d; line %d",
-		      exp_range, ms->current_range, line);
+		      "Expected range %d, got %d; line %d", exp_range,
+		      ms->current_range, line);
 	range_reg = bmi_emul_get_reg(emul, BMI260_ACC_RANGE);
 
 	switch (exp_range) {
@@ -491,17 +513,18 @@ static void check_set_acc_range_f(struct i2c_emul *emul,
 		      "Expected range reg 0x%x, got 0x%x; line %d",
 		      exp_range_reg, range_reg, line);
 }
-#define check_set_acc_range(emul, ms, range, rnd, exp_range)	\
+#define check_set_acc_range(emul, ms, range, rnd, exp_range) \
 	check_set_acc_range_f(emul, ms, range, rnd, exp_range, __LINE__)
 
 /** Test set accelerometer range with and without I2C errors */
 ZTEST_USER(bmi260, test_bmi_acc_set_range)
 {
 	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data;
 	int start_range;
 
-	emul = bmi_emul_get(BMI_ORD);
+	common_data = emul_bmi_get_i2c_common_data(emul);
 	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
 
 	/* Setup starting range, shouldn't be changed on error */
@@ -509,20 +532,21 @@ ZTEST_USER(bmi260, test_bmi_acc_set_range)
 	ms->current_range = start_range;
 	bmi_emul_set_reg(emul, BMI260_ACC_RANGE, BMI260_GSEL_2G);
 	/* Setup emulator fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, BMI260_ACC_RANGE);
+	i2c_common_emul_set_write_fail_reg(common_data, BMI260_ACC_RANGE);
 
 	/* Test fail on write */
 	zassert_equal(EC_ERROR_INVAL, ms->drv->set_range(ms, 12, 0), NULL);
 	zassert_equal(start_range, ms->current_range, NULL);
-	zassert_equal(BMI260_GSEL_2G,
-		      bmi_emul_get_reg(emul, BMI260_ACC_RANGE), NULL);
+	zassert_equal(BMI260_GSEL_2G, bmi_emul_get_reg(emul, BMI260_ACC_RANGE),
+		      NULL);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->set_range(ms, 12, 1), NULL);
 	zassert_equal(start_range, ms->current_range, NULL);
-	zassert_equal(BMI260_GSEL_2G,
-		      bmi_emul_get_reg(emul, BMI260_ACC_RANGE), NULL);
+	zassert_equal(BMI260_GSEL_2G, bmi_emul_get_reg(emul, BMI260_ACC_RANGE),
+		      NULL);
 
 	/* Do not fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test setting range with rounding down */
 	check_set_acc_range(emul, ms, 1, 0, 2);
@@ -557,7 +581,7 @@ ZTEST_USER(bmi260, test_bmi_acc_set_range)
  * Try to set gyroscope range and check if expected range was set in driver and
  * in emulator.
  */
-static void check_set_gyr_range_f(struct i2c_emul *emul,
+static void check_set_gyr_range_f(const struct emul *emul,
 				  struct motion_sensor_t *ms, int range,
 				  int rnd, int exp_range, int line)
 {
@@ -567,8 +591,8 @@ static void check_set_gyr_range_f(struct i2c_emul *emul,
 	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, range, rnd),
 		      "set_range failed; line: %d", line);
 	zassert_equal(exp_range, ms->current_range,
-		      "Expected range %d, got %d; line %d",
-		      exp_range, ms->current_range, line);
+		      "Expected range %d, got %d; line %d", exp_range,
+		      ms->current_range, line);
 	range_reg = bmi_emul_get_reg(emul, BMI260_GYR_RANGE);
 
 	switch (exp_range) {
@@ -599,17 +623,18 @@ static void check_set_gyr_range_f(struct i2c_emul *emul,
 		      "Expected range reg 0x%x, got 0x%x; line %d",
 		      exp_range_reg, range_reg, line);
 }
-#define check_set_gyr_range(emul, ms, range, rnd, exp_range)	\
+#define check_set_gyr_range(emul, ms, range, rnd, exp_range) \
 	check_set_gyr_range_f(emul, ms, range, rnd, exp_range, __LINE__)
 
 /** Test set gyroscope range with and without I2C errors */
 ZTEST_USER(bmi260, test_bmi_gyr_set_range)
 {
 	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data;
 	int start_range;
 
-	emul = bmi_emul_get(BMI_ORD);
+	common_data = emul_bmi_get_i2c_common_data(emul);
 	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
 
 	/* Setup starting range, shouldn't be changed on error */
@@ -617,7 +642,7 @@ ZTEST_USER(bmi260, test_bmi_gyr_set_range)
 	ms->current_range = start_range;
 	bmi_emul_set_reg(emul, BMI260_GYR_RANGE, BMI260_DPS_SEL_250);
 	/* Setup emulator fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, BMI260_GYR_RANGE);
+	i2c_common_emul_set_write_fail_reg(common_data, BMI260_GYR_RANGE);
 
 	/* Test fail on write */
 	zassert_equal(EC_ERROR_INVAL, ms->drv->set_range(ms, 125, 0), NULL);
@@ -630,7 +655,8 @@ ZTEST_USER(bmi260, test_bmi_gyr_set_range)
 		      bmi_emul_get_reg(emul, BMI260_GYR_RANGE), NULL);
 
 	/* Do not fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test setting range with rounding down */
 	check_set_gyr_range(emul, ms, 1, 0, 125);
@@ -691,7 +717,7 @@ ZTEST_USER(bmi260, test_bmi_get_resolution)
  * Try to set accelerometer data rate and check if expected rate was set
  * in driver and in emulator.
  */
-static void check_set_acc_rate_f(struct i2c_emul *emul,
+static void check_set_acc_rate_f(const struct emul *emul,
 				 struct motion_sensor_t *ms, int rate, int rnd,
 				 int exp_rate, int line)
 {
@@ -741,22 +767,23 @@ static void check_set_acc_rate_f(struct i2c_emul *emul,
 	}
 
 	zassert_equal(exp_rate_reg, rate_reg,
-		      "Expected rate reg 0x%x, got 0x%x; line %d",
-		      exp_rate_reg, rate_reg, line);
+		      "Expected rate reg 0x%x, got 0x%x; line %d", exp_rate_reg,
+		      rate_reg, line);
 }
-#define check_set_acc_rate(emul, ms, rate, rnd, exp_rate)	\
+#define check_set_acc_rate(emul, ms, rate, rnd, exp_rate) \
 	check_set_acc_rate_f(emul, ms, rate, rnd, exp_rate, __LINE__)
 
 /** Test set and get accelerometer rate with and without I2C errors */
 ZTEST_USER(bmi260, test_bmi_acc_rate)
 {
 	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data;
 	uint8_t reg_rate;
 	uint8_t pwr_ctrl;
 	int drv_rate;
 
-	emul = bmi_emul_get(BMI_ORD);
+	common_data = emul_bmi_get_i2c_common_data(emul);
 	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
 
 	/* Test setting rate with rounding down */
@@ -798,8 +825,8 @@ ZTEST_USER(bmi260, test_bmi_acc_rate)
 	check_set_acc_rate(emul, ms, 200000, 1, 200000);
 
 	/* Test out of range rate with rounding down */
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 1, 0), NULL);
+	zassert_equal(EC_RES_INVALID_PARAM, ms->drv->set_data_rate(ms, 1, 0),
+		      NULL);
 	zassert_equal(EC_RES_INVALID_PARAM,
 		      ms->drv->set_data_rate(ms, 12499, 0), NULL);
 	zassert_equal(EC_RES_INVALID_PARAM,
@@ -808,10 +835,10 @@ ZTEST_USER(bmi260, test_bmi_acc_rate)
 		      ms->drv->set_data_rate(ms, 2000000, 0), NULL);
 
 	/* Test out of range rate with rounding up */
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 1, 1), NULL);
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 6250, 1), NULL);
+	zassert_equal(EC_RES_INVALID_PARAM, ms->drv->set_data_rate(ms, 1, 1),
+		      NULL);
+	zassert_equal(EC_RES_INVALID_PARAM, ms->drv->set_data_rate(ms, 6250, 1),
+		      NULL);
 	zassert_equal(EC_RES_INVALID_PARAM,
 		      ms->drv->set_data_rate(ms, 200001, 1), NULL);
 	zassert_equal(EC_RES_INVALID_PARAM,
@@ -824,7 +851,7 @@ ZTEST_USER(bmi260, test_bmi_acc_rate)
 	reg_rate = bmi_emul_get_reg(emul, BMI260_ACC_CONF);
 
 	/* Setup emulator fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_ACC_CONF);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_ACC_CONF);
 
 	/* Test fail on read */
 	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 50000, 0),
@@ -837,10 +864,11 @@ ZTEST_USER(bmi260, test_bmi_acc_rate)
 	zassert_equal(reg_rate, bmi_emul_get_reg(emul, BMI260_ACC_CONF), NULL);
 
 	/* Do not fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Setup emulator fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, BMI260_ACC_CONF);
+	i2c_common_emul_set_write_fail_reg(common_data, BMI260_ACC_CONF);
 
 	/* Test fail on write */
 	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 50000, 0),
@@ -853,7 +881,8 @@ ZTEST_USER(bmi260, test_bmi_acc_rate)
 	zassert_equal(reg_rate, bmi_emul_get_reg(emul, BMI260_ACC_CONF), NULL);
 
 	/* Do not fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test disabling sensor */
 	bmi_emul_set_reg(emul, BMI260_PWR_CTRL,
@@ -877,25 +906,27 @@ ZTEST_USER(bmi260, test_bmi_acc_rate)
 	zassert_true(reg_rate & BMI260_FILTER_PERF, NULL);
 
 	/* Test disabling sensor (by setting rate to 0) but failing. */
-	i2c_common_emul_set_write_fail_reg(emul, BMI260_PWR_CTRL);
+	i2c_common_emul_set_write_fail_reg(common_data, BMI260_PWR_CTRL);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 0, 0),
 		      "Did not properly handle failed power down.");
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test enabling sensor but failing. (after first disabling it) */
 	ms->drv->set_data_rate(ms, 0, 0);
 
-	i2c_common_emul_set_write_fail_reg(emul, BMI260_PWR_CTRL);
+	i2c_common_emul_set_write_fail_reg(common_data, BMI260_PWR_CTRL);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 50000, 0),
 		      "Did not properly handle failed power up.");
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
 }
 
 /**
  * Try to set gyroscope data rate and check if expected rate was set
  * in driver and in emulator.
  */
-static void check_set_gyr_rate_f(struct i2c_emul *emul,
+static void check_set_gyr_rate_f(const struct emul *emul,
 				 struct motion_sensor_t *ms, int rate, int rnd,
 				 int exp_rate, int line)
 {
@@ -945,22 +976,23 @@ static void check_set_gyr_rate_f(struct i2c_emul *emul,
 	}
 
 	zassert_equal(exp_rate_reg, rate_reg,
-		      "Expected rate reg 0x%x, got 0x%x; line %d",
-		      exp_rate_reg, rate_reg, line);
+		      "Expected rate reg 0x%x, got 0x%x; line %d", exp_rate_reg,
+		      rate_reg, line);
 }
-#define check_set_gyr_rate(emul, ms, rate, rnd, exp_rate)	\
+#define check_set_gyr_rate(emul, ms, rate, rnd, exp_rate) \
 	check_set_gyr_rate_f(emul, ms, rate, rnd, exp_rate, __LINE__)
 
 /** Test set and get gyroscope rate with and without I2C errors */
 ZTEST_USER(bmi260, test_bmi_gyr_rate)
 {
 	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data;
 	uint8_t reg_rate;
 	uint8_t pwr_ctrl;
 	int drv_rate;
 
-	emul = bmi_emul_get(BMI_ORD);
+	common_data = emul_bmi_get_i2c_common_data(emul);
 	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
 
 	/* Test setting rate with rounding down */
@@ -996,8 +1028,8 @@ ZTEST_USER(bmi260, test_bmi_gyr_rate)
 	check_set_gyr_rate(emul, ms, 200000, 1, 200000);
 
 	/* Test out of range rate with rounding down */
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 1, 0), NULL);
+	zassert_equal(EC_RES_INVALID_PARAM, ms->drv->set_data_rate(ms, 1, 0),
+		      NULL);
 	zassert_equal(EC_RES_INVALID_PARAM,
 		      ms->drv->set_data_rate(ms, 24999, 0), NULL);
 	zassert_equal(EC_RES_INVALID_PARAM,
@@ -1006,8 +1038,8 @@ ZTEST_USER(bmi260, test_bmi_gyr_rate)
 		      ms->drv->set_data_rate(ms, 4000000, 0), NULL);
 
 	/* Test out of range rate with rounding up */
-	zassert_equal(EC_RES_INVALID_PARAM,
-		      ms->drv->set_data_rate(ms, 1, 1), NULL);
+	zassert_equal(EC_RES_INVALID_PARAM, ms->drv->set_data_rate(ms, 1, 1),
+		      NULL);
 	zassert_equal(EC_RES_INVALID_PARAM,
 		      ms->drv->set_data_rate(ms, 12499, 1), NULL);
 	zassert_equal(EC_RES_INVALID_PARAM,
@@ -1022,7 +1054,7 @@ ZTEST_USER(bmi260, test_bmi_gyr_rate)
 	reg_rate = bmi_emul_get_reg(emul, BMI260_GYR_CONF);
 
 	/* Setup emulator fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_GYR_CONF);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_GYR_CONF);
 
 	/* Test fail on read */
 	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 50000, 0),
@@ -1035,10 +1067,11 @@ ZTEST_USER(bmi260, test_bmi_gyr_rate)
 	zassert_equal(reg_rate, bmi_emul_get_reg(emul, BMI260_GYR_CONF), NULL);
 
 	/* Do not fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Setup emulator fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, BMI260_GYR_CONF);
+	i2c_common_emul_set_write_fail_reg(common_data, BMI260_GYR_CONF);
 
 	/* Test fail on write */
 	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 50000, 0),
@@ -1051,7 +1084,8 @@ ZTEST_USER(bmi260, test_bmi_gyr_rate)
 	zassert_equal(reg_rate, bmi_emul_get_reg(emul, BMI260_GYR_CONF), NULL);
 
 	/* Do not fail on write */
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test disabling sensor */
 	bmi_emul_set_reg(emul, BMI260_PWR_CTRL,
@@ -1086,7 +1120,7 @@ ZTEST_USER(bmi260, test_bmi_scale)
 {
 	struct motion_sensor_t *ms;
 	int16_t ret_scale[3];
-	int16_t exp_scale[3] = {100, 231, 421};
+	int16_t exp_scale[3] = { 100, 231, 421 };
 	int16_t t;
 
 	/* Test accelerometer */
@@ -1116,27 +1150,29 @@ ZTEST_USER(bmi260, test_bmi_scale)
 ZTEST_USER(bmi260, test_bmi_read_temp)
 {
 	struct motion_sensor_t *ms_acc, *ms_gyr;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data;
 	int ret_temp;
 	int exp_temp;
 
-	emul = bmi_emul_get(BMI_ORD);
+	common_data = emul_bmi_get_i2c_common_data(emul);
 	ms_acc = &motion_sensors[BMI_ACC_SENSOR_ID];
 	ms_gyr = &motion_sensors[BMI_GYR_SENSOR_ID];
 
 	/* Setup emulator fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_TEMPERATURE_0);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_TEMPERATURE_0);
 	zassert_equal(EC_ERROR_NOT_POWERED,
 		      ms_acc->drv->read_temp(ms_acc, &ret_temp), NULL);
 	zassert_equal(EC_ERROR_NOT_POWERED,
 		      ms_gyr->drv->read_temp(ms_gyr, &ret_temp), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_TEMPERATURE_1);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_TEMPERATURE_1);
 	zassert_equal(EC_ERROR_NOT_POWERED,
 		      ms_acc->drv->read_temp(ms_acc, &ret_temp), NULL);
 	zassert_equal(EC_ERROR_NOT_POWERED,
 		      ms_gyr->drv->read_temp(ms_gyr, &ret_temp), NULL);
 	/* Do not fail on read */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Fail on invalid temperature */
 	bmi_emul_set_reg(emul, BMI260_TEMPERATURE_0, 0x00);
@@ -1195,14 +1231,15 @@ ZTEST_USER(bmi260, test_bmi_read_temp)
 ZTEST_USER(bmi260, test_bmi_acc_read)
 {
 	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data;
 	intv3_t ret_v;
 	intv3_t exp_v;
-	int16_t scale[3] = {MOTION_SENSE_DEFAULT_SCALE,
-			    MOTION_SENSE_DEFAULT_SCALE,
-			    MOTION_SENSE_DEFAULT_SCALE};
+	int16_t scale[3] = { MOTION_SENSE_DEFAULT_SCALE,
+			     MOTION_SENSE_DEFAULT_SCALE,
+			     MOTION_SENSE_DEFAULT_SCALE };
 
-	emul = bmi_emul_get(BMI_ORD);
+	common_data = emul_bmi_get_i2c_common_data(emul);
 	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
 
 	/* Set offset 0 to simplify test */
@@ -1211,10 +1248,11 @@ ZTEST_USER(bmi260, test_bmi_acc_read)
 	bmi_emul_set_off(emul, BMI_EMUL_ACC_Z, 0);
 
 	/* Fail on read status */
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_STATUS);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_STATUS);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
 
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* When not ready, driver should return saved raw value */
 	exp_v[0] = 100;
@@ -1282,20 +1320,21 @@ ZTEST_USER(bmi260, test_bmi_acc_read)
 	compare_int3v(exp_v, ret_v);
 
 	/* Fail on read of data registers */
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_ACC_X_L_G);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_ACC_X_L_G);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_ACC_X_H_G);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_ACC_X_H_G);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_ACC_Y_L_G);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_ACC_Y_L_G);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_ACC_Y_H_G);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_ACC_Y_H_G);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_ACC_Z_L_G);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_ACC_Z_L_G);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_ACC_Z_H_G);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_ACC_Z_H_G);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
 
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 	ms->rot_standard_ref = NULL;
 }
 
@@ -1303,14 +1342,15 @@ ZTEST_USER(bmi260, test_bmi_acc_read)
 ZTEST_USER(bmi260, test_bmi_gyr_read)
 {
 	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data;
 	intv3_t ret_v;
 	intv3_t exp_v;
-	int16_t scale[3] = {MOTION_SENSE_DEFAULT_SCALE,
-			    MOTION_SENSE_DEFAULT_SCALE,
-			    MOTION_SENSE_DEFAULT_SCALE};
+	int16_t scale[3] = { MOTION_SENSE_DEFAULT_SCALE,
+			     MOTION_SENSE_DEFAULT_SCALE,
+			     MOTION_SENSE_DEFAULT_SCALE };
 
-	emul = bmi_emul_get(BMI_ORD);
+	common_data = emul_bmi_get_i2c_common_data(emul);
 	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
 
 	/* Set offset 0 to simplify test */
@@ -1319,10 +1359,11 @@ ZTEST_USER(bmi260, test_bmi_gyr_read)
 	bmi_emul_set_off(emul, BMI_EMUL_GYR_Z, 0);
 
 	/* Fail on read status */
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_STATUS);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_STATUS);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
 
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* When not ready, driver should return saved raw value */
 	exp_v[0] = 100;
@@ -1390,35 +1431,37 @@ ZTEST_USER(bmi260, test_bmi_gyr_read)
 	compare_int3v(exp_v, ret_v);
 
 	/* Fail on read of data registers */
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_GYR_X_L_G);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_GYR_X_L_G);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_GYR_X_H_G);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_GYR_X_H_G);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_GYR_Y_L_G);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_GYR_Y_L_G);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_GYR_Y_H_G);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_GYR_Y_H_G);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_GYR_Z_L_G);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_GYR_Z_L_G);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_GYR_Z_H_G);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_GYR_Z_H_G);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, ret_v), NULL);
 
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 	ms->rot_standard_ref = NULL;
 }
 
-/** Test acceleromtere calibration */
+/** Test accelerometer calibration */
 ZTEST_USER(bmi260, test_bmi_acc_perform_calib)
 {
 	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data;
 	intv3_t start_off;
 	intv3_t exp_off;
 	intv3_t ret_off;
 	int range;
 	int rate;
 
-	emul = bmi_emul_get(BMI_ORD);
+	common_data = emul_bmi_get_i2c_common_data(emul);
 	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
 
 	bmi_init_emul();
@@ -1455,20 +1498,22 @@ ZTEST_USER(bmi260, test_bmi_acc_perform_calib)
 	zassert_equal(rate, ms->drv->get_data_rate(ms), NULL);
 
 	/* Test fail on rate read */
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_ACC_CONF);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_ACC_CONF);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->perform_calib(ms, 1), NULL);
 	zassert_equal(range, ms->current_range, NULL);
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 	zassert_equal(rate, ms->drv->get_data_rate(ms), NULL);
 
 	/* Test fail on status read */
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_STATUS);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_STATUS);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->perform_calib(ms, 1), NULL);
 	zassert_equal(range, ms->current_range, NULL);
 	zassert_equal(rate, ms->drv->get_data_rate(ms), NULL);
 
 	/* Test fail on data not ready */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 	bmi_emul_set_reg(emul, BMI260_STATUS, 0);
 	zassert_equal(EC_ERROR_TIMEOUT, ms->drv->perform_calib(ms, 1), NULL);
 	zassert_equal(range, ms->current_range, NULL);
@@ -1478,18 +1523,19 @@ ZTEST_USER(bmi260, test_bmi_acc_perform_calib)
 	bmi_emul_set_reg(emul, BMI260_STATUS, BMI260_DRDY_ACC);
 
 	/* Test fail on data read */
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_ACC_X_L_G);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_ACC_X_L_G);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->perform_calib(ms, 1), NULL);
 	zassert_equal(range, ms->current_range, NULL);
 	zassert_equal(rate, ms->drv->get_data_rate(ms), NULL);
 
 	/* Test fail on setting offset */
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_NV_CONF);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_NV_CONF);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->perform_calib(ms, 1), NULL);
 	zassert_equal(range, ms->current_range, NULL);
 	zassert_equal(rate, ms->drv->get_data_rate(ms), NULL);
 
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test successful offset compenastion */
 	zassert_equal(EC_SUCCESS, ms->drv->perform_calib(ms, 1), NULL);
@@ -1507,16 +1553,19 @@ ZTEST_USER(bmi260, test_bmi_acc_perform_calib)
 ZTEST_USER(bmi260, test_bmi_gyr_perform_calib)
 {
 	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data;
 	intv3_t start_off;
 	intv3_t exp_off;
 	intv3_t ret_off;
 	int range;
 	int rate;
 
-	emul = bmi_emul_get(BMI_ORD);
+	common_data = emul_bmi_get_i2c_common_data(emul);
 	ms = &motion_sensors[BMI_GYR_SENSOR_ID];
 
+	bmi_init_emul();
+
 	/* Range and rate cannot change after calibration */
 	range = 125;
 	rate = 50000;
@@ -1546,20 +1595,22 @@ ZTEST_USER(bmi260, test_bmi_gyr_perform_calib)
 	zassert_equal(rate, ms->drv->get_data_rate(ms), NULL);
 
 	/* Test fail on rate read */
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_GYR_CONF);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_GYR_CONF);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->perform_calib(ms, 1), NULL);
 	zassert_equal(range, ms->current_range, NULL);
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 	zassert_equal(rate, ms->drv->get_data_rate(ms), NULL);
 
 	/* Test fail on status read */
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_STATUS);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_STATUS);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->perform_calib(ms, 1), NULL);
 	zassert_equal(range, ms->current_range, NULL);
 	zassert_equal(rate, ms->drv->get_data_rate(ms), NULL);
 
 	/* Test fail on data not ready */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 	bmi_emul_set_reg(emul, BMI260_STATUS, 0);
 	zassert_equal(EC_ERROR_TIMEOUT, ms->drv->perform_calib(ms, 1), NULL);
 	zassert_equal(range, ms->current_range, NULL);
@@ -1573,18 +1624,19 @@ ZTEST_USER(bmi260, test_bmi_gyr_perform_calib)
 			 BMI260_DRDY_ACC | BMI260_DRDY_GYR);
 
 	/* Test fail on data read */
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_GYR_X_L_G);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_GYR_X_L_G);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->perform_calib(ms, 1), NULL);
 	zassert_equal(range, ms->current_range, NULL);
 	zassert_equal(rate, ms->drv->get_data_rate(ms), NULL);
 
 	/* Test fail on setting offset */
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_OFFSET_EN_GYR98);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_OFFSET_EN_GYR98);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->perform_calib(ms, 1), NULL);
 	zassert_equal(range, ms->current_range, NULL);
 	zassert_equal(rate, ms->drv->get_data_rate(ms), NULL);
 
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test successful offset compenastion */
 	zassert_equal(EC_SUCCESS, ms->drv->perform_calib(ms, 1), NULL);
@@ -1611,9 +1663,10 @@ static const void *init_rom_map_addr_passthru(const void *addr, int size)
 ZTEST_USER(bmi260, test_bmi_init)
 {
 	struct motion_sensor_t *ms_acc, *ms_gyr;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data;
 
-	emul = bmi_emul_get(BMI_ORD);
+	common_data = emul_bmi_get_i2c_common_data(emul);
 	ms_acc = &motion_sensors[BMI_ACC_SENSOR_ID];
 	ms_gyr = &motion_sensors[BMI_GYR_SENSOR_ID];
 
@@ -1634,7 +1687,7 @@ struct fifo_func_data {
  * to value passed as additional data. It sets interrupt registers to 0 after
  * access.
  */
-static int emul_fifo_func(struct i2c_emul *emul, int reg, uint8_t *val,
+static int emul_fifo_func(const struct emul *emul, int reg, uint8_t *val,
 			  int byte, void *data)
 {
 	struct fifo_func_data *d = data;
@@ -1658,9 +1711,8 @@ static int emul_fifo_func(struct i2c_emul *emul, int reg, uint8_t *val,
  */
 static void check_fifo_f(struct motion_sensor_t *ms_acc,
 			 struct motion_sensor_t *ms_gyr,
-			 struct bmi_emul_frame *frame,
-			 int acc_range, int gyr_range,
-			 int line)
+			 struct bmi_emul_frame *frame, int acc_range,
+			 int gyr_range, int line)
 {
 	struct ec_response_motion_sensor_data vector;
 	struct bmi_emul_frame *f_acc, *f_gyr;
@@ -1741,7 +1793,7 @@ static void check_fifo_f(struct motion_sensor_t *ms_acc,
 	zassert_is_null(f_gyr, "Not all gyroscope frames are read, line %d",
 			line);
 }
-#define check_fifo(ms_acc, ms_gyr, frame, acc_range, gyr_range)		\
+#define check_fifo(ms_acc, ms_gyr, frame, acc_range, gyr_range) \
 	check_fifo_f(ms_acc, ms_gyr, frame, acc_range, gyr_range, __LINE__)
 
 /** Test irq handler of accelerometer sensor */
@@ -1750,12 +1802,13 @@ ZTEST_USER(bmi260, test_bmi_acc_fifo)
 	struct motion_sensor_t *ms, *ms_gyr;
 	struct fifo_func_data func_data;
 	struct bmi_emul_frame f[3];
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data;
 	int gyr_range = 125;
 	int acc_range = 2;
 	int event;
 
-	emul = bmi_emul_get(BMI_ORD);
+	common_data = emul_bmi_get_i2c_common_data(emul);
 	ms = &motion_sensors[BMI_ACC_SENSOR_ID];
 	ms_gyr = &motion_sensors[BMI_GYR_SENSOR_ID];
 
@@ -1772,11 +1825,12 @@ ZTEST_USER(bmi260, test_bmi_acc_fifo)
 	event = BMI_INT_EVENT;
 
 	/* Test fail to read interrupt status registers */
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_INT_STATUS_0);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_INT_STATUS_0);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->irq_handler(ms, &event), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_INT_STATUS_1);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_INT_STATUS_1);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->irq_handler(ms, &event), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test no interrupt */
 	bmi_emul_set_reg(emul, BMI260_INT_STATUS_0, 0);
@@ -1789,7 +1843,7 @@ ZTEST_USER(bmi260, test_bmi_acc_fifo)
 	check_fifo(ms, ms_gyr, NULL, acc_range, gyr_range);
 
 	/* Set custom function for FIFO test */
-	i2c_common_emul_set_read_func(emul, emul_fifo_func, &func_data);
+	i2c_common_emul_set_read_func(common_data, emul_fifo_func, &func_data);
 	/* Set range */
 	zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, acc_range, 0), NULL);
 	zassert_equal(EC_SUCCESS, ms_gyr->drv->set_range(ms_gyr, gyr_range, 0),
@@ -1872,7 +1926,7 @@ ZTEST_USER(bmi260, test_bmi_acc_fifo)
 	check_fifo(ms, ms_gyr, f, acc_range, gyr_range);
 
 	/* Remove custom emulator read function */
-	i2c_common_emul_set_read_func(emul, NULL, NULL);
+	i2c_common_emul_set_read_func(common_data, NULL, NULL);
 }
 
 /** Test irq handler of gyroscope sensor */
@@ -1906,7 +1960,7 @@ ZTEST_USER(bmi260, test_unsupported_configs)
 	memcpy(&ms_fake, &motion_sensors[BMI_ACC_SENSOR_ID], sizeof(ms_fake));
 	ms_fake.type = MOTIONSENSE_TYPE_MAG;
 
-	int16_t offset[3];
+	int16_t offset[3] = { 0 };
 	int ret =
 		ms_fake.drv->set_offset(&ms_fake, (const int16_t *)&offset, 0);
 	zassert_equal(
@@ -1953,19 +2007,22 @@ ZTEST_USER(bmi260, test_interrupt_handler)
 
 ZTEST_USER(bmi260, test_bmi_init_chip_id)
 {
-	struct i2c_emul *emul = bmi_emul_get(BMI_ORD);
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bmi_get_i2c_common_data(emul);
 	struct motion_sensor_t *ms_acc = &motion_sensors[BMI_ACC_SENSOR_ID];
 
 	/* Part 1:
 	 * Error occurs while reading the chip ID
 	 */
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_CHIP_ID);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_CHIP_ID);
 	int ret = ms_acc->drv->init(ms_acc);
 
 	zassert_equal(ret, EC_ERROR_UNKNOWN,
 		      "Expected %d (EC_ERROR_UNKNOWN) but got %d",
 		      EC_ERROR_UNKNOWN, ret);
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Part 2:
 	 * Test cases where the returned chip ID does not match what is
@@ -2007,9 +2064,10 @@ ZTEST_USER(bmi260, test_bmi_init_chip_id)
 
 /* Make an I2C emulator mock wrapped in FFF */
 FAKE_VALUE_FUNC(int, bmi_config_load_no_mapped_flash_mock_read_fn,
-		struct i2c_emul *, int, uint8_t *, int, void *);
+		const struct emul *, int, uint8_t *, int, void *);
+struct i2c_common_emul_data *common_data;
 static int bmi_config_load_no_mapped_flash_mock_read_fn_helper(
-	struct i2c_emul *emul, int reg, uint8_t *val, int bytes, void *data)
+	const struct emul *emul, int reg, uint8_t *val, int bytes, void *data)
 {
 	if (reg == BMI260_INTERNAL_STATUS && val) {
 		/* We want to force-return a status of 'initialized' when this
@@ -2029,10 +2087,13 @@ ZTEST_USER(bmi260, test_bmi_config_load_no_mapped_flash)
 	 * `bmi_config_load()` returns NULL)
 	 */
 
-	struct i2c_emul *emul = bmi_emul_get(BMI_ORD);
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data;
 	struct motion_sensor_t *ms_acc = &motion_sensors[BMI_ACC_SENSOR_ID];
 	int ret, num_status_reg_reads;
 
+	common_data = emul_bmi_get_i2c_common_data(emul);
+
 	/* Force bmi_config_load() to have to manually copy from memory */
 	RESET_FAKE(init_rom_map);
 	init_rom_map_fake.return_val = NULL;
@@ -2046,7 +2107,8 @@ ZTEST_USER(bmi260, test_bmi_config_load_no_mapped_flash)
 	 */
 	bmi_emul_set_reg(emul, BMI260_CHIP_ID, BMI260_CHIP_ID_MAJOR);
 	i2c_common_emul_set_read_func(
-		emul, bmi_config_load_no_mapped_flash_mock_read_fn, NULL);
+		common_data, bmi_config_load_no_mapped_flash_mock_read_fn,
+		NULL);
 	RESET_FAKE(bmi_config_load_no_mapped_flash_mock_read_fn);
 	bmi_config_load_no_mapped_flash_mock_read_fn_fake.custom_fake =
 		bmi_config_load_no_mapped_flash_mock_read_fn_helper;
@@ -2066,13 +2128,14 @@ ZTEST_USER(bmi260, test_bmi_config_load_no_mapped_flash)
 		      num_status_reg_reads, 1);
 
 	/* Part 2: write to `BMI260_INIT_ADDR_0` fails */
-	i2c_common_emul_set_write_fail_reg(emul, BMI260_INIT_ADDR_0);
+	i2c_common_emul_set_write_fail_reg(common_data, BMI260_INIT_ADDR_0);
 
 	ret = ms_acc->drv->init(ms_acc);
 	zassert_equal(ret, EC_ERROR_INVALID_CONFIG, "Got %d but expected %d",
 		      ret, EC_ERROR_INVALID_CONFIG);
 
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Part 3: init_rom_copy() fails w/ a non-zero return code of 255. */
 	init_rom_copy_fake.return_val = 255;
@@ -2084,16 +2147,17 @@ ZTEST_USER(bmi260, test_bmi_config_load_no_mapped_flash)
 	init_rom_copy_fake.return_val = 0;
 
 	/* Part 4: write to `BMI260_INIT_DATA` fails */
-	i2c_common_emul_set_write_fail_reg(emul, BMI260_INIT_DATA);
+	i2c_common_emul_set_write_fail_reg(common_data, BMI260_INIT_DATA);
 
 	ret = ms_acc->drv->init(ms_acc);
 	zassert_equal(ret, EC_ERROR_INVALID_CONFIG, "Got %d but expected %d",
 		      ret, EC_ERROR_INVALID_CONFIG);
 
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Cleanup */
-	i2c_common_emul_set_read_func(emul, NULL, NULL);
+	i2c_common_emul_set_read_func(common_data, NULL, NULL);
 }
 
 ZTEST_USER(bmi260, test_bmi_config_unsupported_chip)
@@ -2108,9 +2172,12 @@ ZTEST_USER(bmi260, test_bmi_config_unsupported_chip)
 	"CONFIG_ACCELGYRO_BMI220 defined."
 #endif
 
-	struct i2c_emul *emul = bmi_emul_get(BMI_ORD);
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data;
 	struct motion_sensor_t ms_fake;
 
+	common_data = emul_bmi_get_i2c_common_data(emul);
+
 	/* Set up struct and emaulator to be a BMI220 chip, which
 	 * `bmi_config_load()` does not support in the current configuration
 	 */
@@ -2131,13 +2198,16 @@ ZTEST_USER(bmi260, test_init_config_read_failure)
 	 * BMI260_INTERNAL_STATUS.
 	 */
 
-	struct i2c_emul *emul = bmi_emul_get(BMI_ORD);
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data;
 	struct motion_sensor_t *ms_acc = &motion_sensors[BMI_ACC_SENSOR_ID];
 	int ret;
 
+	common_data = emul_bmi_get_i2c_common_data(emul);
+
 	/* Set up i2c emulator and mocks */
 	bmi_emul_set_reg(emul, BMI260_CHIP_ID, BMI260_CHIP_ID_MAJOR);
-	i2c_common_emul_set_read_fail_reg(emul, BMI260_INTERNAL_STATUS);
+	i2c_common_emul_set_read_fail_reg(common_data, BMI260_INTERNAL_STATUS);
 	RESET_FAKE(init_rom_map);
 	init_rom_map_fake.custom_fake = init_rom_map_addr_passthru;
 
@@ -2151,7 +2221,7 @@ ZTEST_USER(bmi260, test_init_config_read_failure)
  * waiting for the chip to initialize
  */
 static int timeout_test_status_reg_access_count;
-static int status_timeout_mock_read_fn(struct i2c_emul *emul, int reg,
+static int status_timeout_mock_read_fn(const struct emul *emul, int reg,
 				       uint8_t *val, int bytes, void *data)
 {
 	if (reg == BMI260_INTERNAL_STATUS && val) {
@@ -2172,14 +2242,18 @@ ZTEST_USER(bmi260, test_init_config_status_timeout)
 	 * before the timeout.
 	 */
 
-	struct i2c_emul *emul = bmi_emul_get(BMI_ORD);
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data;
 	struct motion_sensor_t *ms_acc = &motion_sensors[BMI_ACC_SENSOR_ID];
 	int ret;
 
+	common_data = emul_bmi_get_i2c_common_data(emul);
+
 	/* Set up i2c emulator and mocks */
 	bmi_emul_set_reg(emul, BMI260_CHIP_ID, BMI260_CHIP_ID_MAJOR);
 	timeout_test_status_reg_access_count = 0;
-	i2c_common_emul_set_read_func(emul, status_timeout_mock_read_fn, NULL);
+	i2c_common_emul_set_read_func(common_data, status_timeout_mock_read_fn,
+				      NULL);
 	RESET_FAKE(init_rom_map);
 	init_rom_map_fake.custom_fake = init_rom_map_addr_passthru;
 
@@ -2192,4 +2266,40 @@ ZTEST_USER(bmi260, test_init_config_status_timeout)
 		      EC_ERROR_INVALID_CONFIG, ret);
 }
 
-ZTEST_SUITE(bmi260, drivers_predicate_post_main, NULL, NULL, NULL, NULL);
+/**
+ * @brief Put the driver and emulator in to a consistent state before each test.
+ *
+ * @param arg Test fixture (unused)
+ */
+static void bmi260_test_before(void *arg)
+{
+	ARG_UNUSED(arg);
+
+	const struct emul *emul = EMUL_DT_GET(BMI_NODE);
+	struct i2c_common_emul_data *common_data;
+	struct motion_sensor_t *ms_acc = &motion_sensors[BMI_ACC_SENSOR_ID];
+	struct motion_sensor_t *ms_gyr = &motion_sensors[BMI_GYR_SENSOR_ID];
+
+	common_data = emul_bmi_get_i2c_common_data(emul);
+
+	/* Reset I2C */
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_func(common_data, NULL, NULL);
+	i2c_common_emul_set_write_func(common_data, NULL, NULL);
+
+	/* Reset local fakes(s) */
+	RESET_FAKE(bmi_config_load_no_mapped_flash_mock_read_fn);
+
+	/* Clear rotation matrices */
+	ms_acc->rot_standard_ref = NULL;
+	ms_gyr->rot_standard_ref = NULL;
+
+	/* Set Chip ID register to BMI260 (required for init() to succeed) */
+	bmi_emul_set_reg(emul, BMI260_CHIP_ID, BMI260_CHIP_ID_MAJOR);
+}
+
+ZTEST_SUITE(bmi260, drivers_predicate_pre_main, NULL, bmi260_test_before, NULL,
+	    NULL);
diff --git a/zephyr/test/drivers/src/charge_manager.c b/zephyr/test/drivers/default/src/charge_manager.c
index 13668924fd..85048178ae 100644
--- a/zephyr/test/drivers/src/charge_manager.c
+++ b/zephyr/test/drivers/default/src/charge_manager.c
@@ -1,9 +1,9 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <ztest.h>
+#include <zephyr/ztest.h>
 
 #include "charge_manager.h"
 #include "ec_commands.h"
diff --git a/zephyr/test/drivers/default/src/console.c b/zephyr/test/drivers/default/src/console.c
new file mode 100644
index 0000000000..c74fd3ea1c
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console.c
@@ -0,0 +1,88 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+#include <zephyr/shell/shell_dummy.h>
+
+#include "builtin/stdio.h"
+#include "test/drivers/test_state.h"
+#include "console.h"
+#include "uart.h"
+#include "ec_commands.h"
+
+ZTEST_USER(console, printf_overflow)
+{
+	char buffer[10];
+
+	zassert_equal(-EC_ERROR_OVERFLOW,
+		      crec_snprintf(buffer, 4, "1234567890"), NULL);
+	zassert_equal(0, strcmp(buffer, "123"), "got '%s'", buffer);
+	zassert_equal(-EC_ERROR_OVERFLOW,
+		      crec_snprintf(buffer, 4, "%%%%%%%%%%"), NULL);
+	zassert_equal(0, strcmp(buffer, "%%%"), "got '%s'", buffer);
+}
+
+/* This test is identical to test_buf_notify_null in
+ * test/console_edit.c. Please keep them in sync to verify that
+ * uart_console_read_buffer works identically in legacy EC and zephyr.
+ */
+ZTEST_USER(console, buf_notify_null)
+{
+	char buffer[100];
+	uint16_t write_count;
+	size_t consumed_count;
+
+	/* Flush the console buffer before we start. */
+	zassert_ok(uart_console_read_buffer_init(), NULL);
+
+	/* Write a nul char to the buffer. */
+	consumed_count = console_buf_notify_chars("ab\0c", 4);
+
+	/* Check if all bytes were consumed by console buffer */
+	zassert_equal(consumed_count, 4, "got %d", consumed_count);
+
+	/* Check if the nul is present in the buffer. */
+	zassert_ok(uart_console_read_buffer_init(), NULL);
+	zassert_ok(uart_console_read_buffer(CONSOLE_READ_RECENT, buffer,
+					    sizeof(buffer), &write_count),
+		   NULL);
+	zassert_equal(0, strncmp(buffer, "abc", 4), "got '%s'", buffer);
+	zassert_equal(write_count, 4, "got %d", write_count);
+}
+
+static const char *large_string =
+	"This is a very long string, it will cause a buffer flush at "
+	"some point while printing to the shell. Long long text. Blah "
+	"blah. Long long text. Blah blah. Long long text. Blah blah.";
+ZTEST_USER(console, shell_fprintf_full)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+	const char *outbuffer;
+	size_t buffer_size;
+
+	zassert_true(strlen(large_string) >=
+			     shell_zephyr->fprintf_ctx->buffer_size,
+		     "large_string is too short, fix test.");
+
+	shell_backend_dummy_clear_output(shell_zephyr);
+	shell_fprintf(shell_zephyr, SHELL_NORMAL, "%s", large_string);
+
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+	zassert_true(strncmp(outbuffer, large_string, strlen(large_string)) ==
+			     0,
+		     "Invalid console output %s", outbuffer);
+}
+
+ZTEST_USER(console, cprint_too_big)
+{
+	zassert_true(strlen(large_string) >= CONFIG_SHELL_PRINTF_BUFF_SIZE,
+		     "buffer is too short, fix test.");
+
+	zassert_equal(cprintf(CC_COMMAND, "%s", large_string),
+		      -EC_ERROR_OVERFLOW, NULL);
+}
+
+ZTEST_SUITE(console, drivers_predicate_post_main, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/drivers/src/console_cmd/accelinfo.c b/zephyr/test/drivers/default/src/console_cmd/accelinfo.c
index e60d00b596..11638fcc70 100644
--- a/zephyr/test/drivers/src/console_cmd/accelinfo.c
+++ b/zephyr/test/drivers/default/src/console_cmd/accelinfo.c
@@ -1,10 +1,10 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include <zephyr/shell/shell.h>
-#include <ztest.h>
+#include <zephyr/ztest.h>
 
 #include "config.h"
 #include "console.h"
diff --git a/zephyr/test/drivers/src/console_cmd/accelinit.c b/zephyr/test/drivers/default/src/console_cmd/accelinit.c
index 24538ef648..c440faebba 100644
--- a/zephyr/test/drivers/src/console_cmd/accelinit.c
+++ b/zephyr/test/drivers/default/src/console_cmd/accelinit.c
@@ -1,11 +1,11 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <fff.h>
+#include <zephyr/fff.h>
 #include <zephyr/shell/shell.h>
-#include <ztest.h>
+#include <zephyr/ztest.h>
 
 #include "accelgyro.h"
 #include "console.h"
@@ -80,7 +80,7 @@ ZTEST_USER(console_cmd_accelinit, test_state_was_set)
 ZTEST_USER_F(console_cmd_accelinit, test_fail_3_times)
 {
 	mock_init_fake.return_val = 1;
-	motion_sensors[0].drv = &this->mock_drv;
+	motion_sensors[0].drv = &fixture->mock_drv;
 	motion_sensors[0].state = SENSOR_INITIALIZED;
 
 	zassert_ok(shell_execute_cmd(get_ec_shell(), "accelinit 0"), NULL);
diff --git a/zephyr/test/drivers/src/console_cmd/accelrange.c b/zephyr/test/drivers/default/src/console_cmd/accelrange.c
index b78702e486..ff9d03bfe2 100644
--- a/zephyr/test/drivers/src/console_cmd/accelrange.c
+++ b/zephyr/test/drivers/default/src/console_cmd/accelrange.c
@@ -1,11 +1,11 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include <zephyr/shell/shell.h>
 #include <zephyr/devicetree.h>
-#include <ztest.h>
+#include <zephyr/ztest.h>
 
 #include "console.h"
 #include "driver/accel_bma2x2.h"
@@ -16,17 +16,20 @@
 #include "motion_sense.h"
 #include "test/drivers/test_state.h"
 
-#define EMUL_LABEL DT_NODELABEL(bma_emul)
+#define EMUL_NODE DT_NODELABEL(bma_emul)
 
 #define BMA_ORD DT_DEP_ORD(EMUL_LABEL)
 
 static void console_cmd_accelrange_after(void *fixture)
 {
-	struct i2c_emul *emul = bma_emul_get(BMA_ORD);
+	const struct emul *emul = EMUL_DT_GET(EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bma_get_i2c_common_data(emul);
 
 	ARG_UNUSED(fixture);
 	shell_execute_cmd(get_ec_shell(), "accelrange 0 2");
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 }
 
 ZTEST_SUITE(console_cmd_accelrange, drivers_predicate_post_main, NULL, NULL,
@@ -101,10 +104,13 @@ ZTEST_USER(console_cmd_accelrange, test_set_range_round_down)
 
 ZTEST_USER(console_cmd_accelrange, test_i2c_error)
 {
-	struct i2c_emul *emul = bma_emul_get(BMA_ORD);
+	const struct emul *emul = EMUL_DT_GET(EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_bma_get_i2c_common_data(emul);
 	int rv;
 
-	i2c_common_emul_set_read_fail_reg(emul, BMA2x2_RANGE_SELECT_ADDR);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  BMA2x2_RANGE_SELECT_ADDR);
 
 	rv = shell_execute_cmd(get_ec_shell(), "accelrange 0 3");
 	zassert_equal(rv, EC_ERROR_PARAM2, "Expected %d, but got %d",
diff --git a/zephyr/test/drivers/src/console_cmd/accelrate.c b/zephyr/test/drivers/default/src/console_cmd/accelrate.c
index 6ae4b96343..59482ed866 100644
--- a/zephyr/test/drivers/src/console_cmd/accelrate.c
+++ b/zephyr/test/drivers/default/src/console_cmd/accelrate.c
@@ -1,10 +1,10 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include <zephyr/shell/shell.h>
-#include <ztest.h>
+#include <zephyr/ztest.h>
 
 #include "console.h"
 #include "ec_commands.h"
diff --git a/zephyr/test/drivers/src/console_cmd/accelread.c b/zephyr/test/drivers/default/src/console_cmd/accelread.c
index 8ab9407dfe..81ebf87e55 100644
--- a/zephyr/test/drivers/src/console_cmd/accelread.c
+++ b/zephyr/test/drivers/default/src/console_cmd/accelread.c
@@ -1,11 +1,11 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <fff.h>
+#include <zephyr/fff.h>
 #include <zephyr/shell/shell.h>
-#include <ztest.h>
+#include <zephyr/ztest.h>
 
 #include "accelgyro.h"
 #include "console.h"
@@ -58,7 +58,7 @@ static void console_cmd_accelread_after(void *fixture)
 	motion_sensors[0].drv = this->sensor_0_drv;
 }
 
-ZTEST_SUITE(console_cmd_accelread, drivers_predicate_post_main,
+ZTEST_SUITE(console_cmd_accelread, drivers_predicate_pre_main,
 	    console_cmd_accelread_setup, console_cmd_accelread_before,
 	    console_cmd_accelread_after, NULL);
 
@@ -96,9 +96,10 @@ int mock_read_call_super(const struct motion_sensor_t *s, int *v)
 
 ZTEST_USER_F(console_cmd_accelread, test_read)
 {
-	current_fixture = this;
+	current_fixture = fixture;
 	mock_read_fake.custom_fake = mock_read_call_super;
-	motion_sensors[0].drv = &this->mock_drv;
+	mock_get_data_rate_fake.return_val = 100;
+	motion_sensors[0].drv = &fixture->mock_drv;
 
 	zassert_ok(shell_execute_cmd(get_ec_shell(), "accelread 0"), NULL);
 	zassert_equal(1, mock_read_fake.call_count,
@@ -114,7 +115,7 @@ ZTEST_USER_F(console_cmd_accelread, test_read)
 ZTEST_USER_F(console_cmd_accelread, test_read_fail)
 {
 	mock_read_fake.return_val = 1;
-	motion_sensors[0].drv = &this->mock_drv;
+	motion_sensors[0].drv = &fixture->mock_drv;
 
 	zassert_ok(shell_execute_cmd(get_ec_shell(), "accelread 0"), NULL);
 	zassert_equal(1, mock_read_fake.call_count,
diff --git a/zephyr/test/drivers/src/console_cmd/accelres.c b/zephyr/test/drivers/default/src/console_cmd/accelres.c
index 72b52b1c58..5e29a0572d 100644
--- a/zephyr/test/drivers/src/console_cmd/accelres.c
+++ b/zephyr/test/drivers/default/src/console_cmd/accelres.c
@@ -1,11 +1,11 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <fff.h>
+#include <zephyr/fff.h>
 #include <zephyr/shell/shell.h>
-#include <ztest.h>
+#include <zephyr/ztest.h>
 
 #include "accelgyro.h"
 #include "console.h"
@@ -112,7 +112,7 @@ ZTEST_USER_F(console_cmd_accelres, test_set_res__bad_res_value)
 	int rv;
 
 	set_resolution_fake.return_val = EC_ERROR_INVAL;
-	motion_sensors[0].drv = &this->mock_drv;
+	motion_sensors[0].drv = &fixture->mock_drv;
 	rv = shell_execute_cmd(get_ec_shell(), "accelres 0 0");
 	zassert_equal(EC_ERROR_PARAM2, rv, "Expected %d, but got %d",
 		      EC_ERROR_PARAM2, rv);
diff --git a/zephyr/test/drivers/src/console_cmd/accelspoof.c b/zephyr/test/drivers/default/src/console_cmd/accelspoof.c
index 2d9887a2ab..3e183ca296 100644
--- a/zephyr/test/drivers/src/console_cmd/accelspoof.c
+++ b/zephyr/test/drivers/default/src/console_cmd/accelspoof.c
@@ -1,10 +1,10 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include <zephyr/shell/shell.h>
-#include <ztest.h>
+#include <zephyr/ztest.h>
 
 #include "console.h"
 #include "ec_commands.h"
diff --git a/zephyr/test/drivers/default/src/console_cmd/adc.c b/zephyr/test/drivers/default/src/console_cmd/adc.c
new file mode 100644
index 0000000000..85dfda939a
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/adc.c
@@ -0,0 +1,43 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+#include "console.h"
+#include "ec_commands.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+/* Default adc command, lists out channels */
+ZTEST_USER(console_cmd_adc, test_adc_noname)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "adc"),
+		   "Failed default print");
+}
+
+/* adc with named channels */
+ZTEST_USER(console_cmd_adc, test_adc_named_channels)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "adc charger"),
+		   "Failed to get charger adc channel.");
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "adc ddr-soc"),
+		   "Failed to get ddr-soc adc channel.");
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "adc fan"),
+		   "Failed to get fan adc channel.");
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "adc psys"),
+		   "Failed to get psys adc channel.");
+}
+
+/* adc with unknown channel */
+ZTEST_USER(console_cmd_adc, test_adc_wrong_name)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "adc fish");
+
+	zassert_equal(rv, EC_ERROR_PARAM1, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+}
+
+ZTEST_SUITE(console_cmd_adc, NULL, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/drivers/default/src/console_cmd/battery.c b/zephyr/test/drivers/default/src/console_cmd/battery.c
new file mode 100644
index 0000000000..9c3e21fcf1
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/battery.c
@@ -0,0 +1,90 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+#include "battery_smart.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_smart_battery.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+struct console_cmd_battery_fixture {
+	const struct emul *emul;
+	struct i2c_common_emul_data *i2c_emul;
+};
+
+static void *console_cmd_battery_setup(void)
+{
+	static struct console_cmd_battery_fixture fixture = {
+		.emul = EMUL_DT_GET(DT_NODELABEL(battery)),
+	};
+
+	fixture.i2c_emul = emul_smart_battery_get_i2c_common_data(fixture.emul);
+
+	return &fixture;
+}
+
+static void console_cmd_battery_after(void *f)
+{
+	struct console_cmd_battery_fixture *fixture = f;
+
+	i2c_common_emul_set_read_fail_reg(fixture->i2c_emul,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+}
+
+/* Default battery command */
+ZTEST_USER(console_cmd_battery, test_battery_default)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "battery"),
+		   "Failed default print");
+}
+
+ZTEST_USER_F(console_cmd_battery, test_battery_status_i2c_error)
+{
+	/* Force a failure on the battery i2c write to SB_BATTERY_STATUS */
+	i2c_common_emul_set_read_fail_reg(fixture->i2c_emul, SB_BATTERY_STATUS);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "battery"),
+		   "Failed default print");
+}
+
+/* Battery command with repeat */
+ZTEST_USER(console_cmd_battery, test_battery_repeat)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "battery 2"),
+		   "Failed default print");
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "battery 8"),
+		   "Failed default print");
+}
+
+/* Battery command with repeat and sleep */
+ZTEST_USER(console_cmd_battery, test_battery_repeat_sleep)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "battery 2 400"),
+		   "Failed default print");
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "battery 8 200"),
+		   "Failed default print");
+}
+
+/* Battery command with invalid repeat and sleep */
+ZTEST_USER(console_cmd_battery, test_battery_bad_repeat_sleep)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "battery fish 400");
+
+	zassert_equal(rv, EC_ERROR_INVAL, "Expected %d, but got %d",
+		      EC_ERROR_INVAL, rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "battery 2 fish");
+
+	zassert_equal(rv, EC_ERROR_INVAL, "Expected %d, but got %d",
+		      EC_ERROR_INVAL, rv);
+}
+
+ZTEST_SUITE(console_cmd_battery, drivers_predicate_post_main,
+	    console_cmd_battery_setup, NULL, console_cmd_battery_after, NULL);
diff --git a/zephyr/test/drivers/default/src/console_cmd/button.c b/zephyr/test/drivers/default/src/console_cmd/button.c
new file mode 100644
index 0000000000..9272b2ce2d
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/button.c
@@ -0,0 +1,67 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+#include "console.h"
+#include "ec_commands.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+ZTEST_USER(console_cmd_button, test_button_no_arg)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "button");
+
+	zassert_equal(EC_ERROR_PARAM_COUNT, rv, "Expected %d, returned %d",
+		      EC_ERROR_PARAM_COUNT, rv);
+}
+
+ZTEST_USER(console_cmd_button, test_button_vup)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "button vup a");
+
+	zassert_equal(EC_ERROR_PARAM2, rv, "Expected %d, returned %d",
+		      EC_ERROR_PARAM2, rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "button vup 50");
+
+	zassert_ok(rv, "Expected %d, returned %d", EC_SUCCESS, rv);
+}
+
+ZTEST_USER(console_cmd_button, test_button_vdown)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "button vdown a");
+
+	zassert_equal(EC_ERROR_PARAM2, rv, "Expected %d, returned %d",
+		      EC_ERROR_PARAM2, rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "button vdown 50");
+
+	zassert_ok(rv, "Expected %d, returned %d", EC_SUCCESS, rv);
+}
+
+ZTEST_USER(console_cmd_button, test_button_rec)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "button rec 50");
+
+	if (IS_ENABLED(CONFIG_DEDICATED_RECOVERY_BUTTON)) {
+		zassert_ok(rv, "Expected %d, returned %d", EC_SUCCESS, rv);
+	} else {
+		/* Recovery button does not exist */
+		zassert_equal(EC_ERROR_PARAM1, rv, "Expected %d, returned %d",
+			      EC_ERROR_PARAM1, rv);
+	}
+}
+
+ZTEST_SUITE(console_cmd_button, NULL, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/drivers/default/src/console_cmd/cbi.c b/zephyr/test/drivers/default/src/console_cmd/cbi.c
new file mode 100644
index 0000000000..495ffd7e4c
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/cbi.c
@@ -0,0 +1,81 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+#include "console.h"
+#include "test/drivers/test_state.h"
+
+static void set_wp(bool value)
+{
+	const struct gpio_dt_spec *wp = GPIO_DT_FROM_NODELABEL(gpio_wp_l);
+
+	gpio_pin_set_dt(wp, value);
+}
+
+static void before(void *unused)
+{
+	/* Ensure eeprom is ready */
+	set_wp(false);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "cbi remove 42 init"),
+		   NULL);
+}
+
+static void after(void *unused)
+{
+	/* re-enable WP */
+	set_wp(true);
+}
+
+ZTEST_SUITE(console_cmd_cbi, drivers_predicate_post_main, NULL, before, after,
+	    NULL);
+
+ZTEST_USER(console_cmd_cbi, test_base)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "cbi"), NULL);
+}
+
+ZTEST_USER(console_cmd_cbi, test_wp)
+{
+	set_wp(true);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "cbi remove 42"), NULL);
+}
+
+ZTEST_USER(console_cmd_cbi, test_remove)
+{
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "cbi remove"), NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "cbi remove 42"), NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "cbi remove abc"), NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "cbi remove 42 1"), NULL);
+}
+
+ZTEST_USER(console_cmd_cbi, test_set)
+{
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "cbi set"), NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "cbi set 10"), NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "cbi set 11 1"), NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "cbi set 12 1 4"), NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "cbi set 13 1 4 4"),
+		   NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "cbi set 14 1 10"), NULL);
+}
+
+ZTEST_USER(console_cmd_cbi, test_extra)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(),
+				     "cbi remove 42 skip_write"),
+		   NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "cbi remove 42 init"),
+		   NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(),
+				     "cbi remove 42 init skip_write"),
+		   NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(),
+				     "cbi remove 42 skip_write init"),
+		   NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "cbi remove 42 extra"),
+		   NULL);
+}
diff --git a/zephyr/test/drivers/src/console_cmd/charge_manager.c b/zephyr/test/drivers/default/src/console_cmd/charge_manager.c
index c6e4821623..f6ee049ea1 100644
--- a/zephyr/test/drivers/src/console_cmd/charge_manager.c
+++ b/zephyr/test/drivers/default/src/console_cmd/charge_manager.c
@@ -1,44 +1,20 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include <zephyr/shell/shell.h>
-#include <ztest.h>
+#include <zephyr/ztest.h>
 
 #include "charge_manager.h"
 #include "console.h"
 #include "emul/emul_isl923x.h"
+#include "emul/tcpc/emul_tcpci.h"
 #include "emul/tcpc/emul_tcpci_partner_snk.h"
 #include "tcpm/tcpci.h"
 #include "test/drivers/test_state.h"
 #include "test/drivers/utils.h"
 
-static void connect_sink_to_port(const struct emul *charger_emul,
-				 const struct emul *tcpci_emul,
-				 struct tcpci_partner_data *partner)
-{
-	isl923x_emul_set_adc_vbus(charger_emul, 0);
-	tcpci_emul_set_reg(tcpci_emul, TCPC_REG_POWER_STATUS,
-			   TCPC_REG_POWER_STATUS_VBUS_DET);
-	tcpci_emul_set_reg(tcpci_emul, TCPC_REG_EXT_STATUS,
-			   TCPC_REG_EXT_STATUS_SAFE0V);
-	tcpci_tcpc_alert(0);
-	zassume_ok(tcpci_partner_connect_to_tcpci(partner, tcpci_emul),
-		   NULL);
-
-	/* Wait for PD negotiation and current ramp.
-	 * TODO(b/213906889): Check message timing and contents.
-	 */
-	k_sleep(K_SECONDS(10));
-}
-
-static inline void disconnect_sink_from_port(const struct emul *tcpci_emul)
-{
-	zassume_ok(tcpci_emul_disconnect_partner(tcpci_emul), NULL);
-	k_sleep(K_SECONDS(1));
-}
-
 struct console_cmd_charge_manager_fixture {
 	struct tcpci_partner_data sink_5v_3a;
 	struct tcpci_snk_emul_data sink_ext;
@@ -51,17 +27,13 @@ static void *console_cmd_charge_manager_setup(void)
 	static struct console_cmd_charge_manager_fixture test_fixture;
 
 	/* Get references for the emulators */
-	test_fixture.tcpci_emul =
-		emul_get_binding(DT_LABEL(DT_NODELABEL(tcpci_emul)));
-	test_fixture.charger_emul =
-		emul_get_binding(DT_LABEL(DT_NODELABEL(isl923x_emul)));
-	tcpci_emul_set_rev(test_fixture.tcpci_emul, TCPCI_EMUL_REV2_0_VER1_1);
+	test_fixture.tcpci_emul = EMUL_GET_USBC_BINDING(0, tcpc);
+	test_fixture.charger_emul = EMUL_GET_USBC_BINDING(0, chg);
 
 	/* Initialized the sink to request 5V and 3A */
 	tcpci_partner_init(&test_fixture.sink_5v_3a, PD_REV20);
-	test_fixture.sink_5v_3a.extensions =
-		tcpci_snk_emul_init(&test_fixture.sink_ext,
-				    &test_fixture.sink_5v_3a, NULL);
+	test_fixture.sink_5v_3a.extensions = tcpci_snk_emul_init(
+		&test_fixture.sink_ext, &test_fixture.sink_5v_3a, NULL);
 	test_fixture.sink_ext.pdo[1] =
 		PDO_FIXED(5000, 3000, PDO_FIXED_UNCONSTRAINED);
 
@@ -129,8 +101,8 @@ ZTEST_USER_F(console_cmd_charge_manager, test_chgoverride_0_from_sink)
 	/* TODO(b/214401892): Check why need to give time TCPM to spin */
 	k_sleep(K_SECONDS(1));
 
-	connect_sink_to_port(this->charger_emul, this->tcpci_emul,
-			     &this->sink_5v_3a);
+	connect_sink_to_port(&fixture->sink_5v_3a, fixture->tcpci_emul,
+			     fixture->charger_emul);
 	zassert_equal(shell_execute_cmd(get_ec_shell(), "chgoverride 0"),
 		      EC_ERROR_INVAL, NULL);
 }
diff --git a/zephyr/test/drivers/src/console_cmd/charge_state.c b/zephyr/test/drivers/default/src/console_cmd/charge_state.c
index 25c03928d4..d5dc9fe415 100644
--- a/zephyr/test/drivers/src/console_cmd/charge_state.c
+++ b/zephyr/test/drivers/default/src/console_cmd/charge_state.c
@@ -1,10 +1,10 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include <zephyr/shell/shell.h>
-#include <ztest.h>
+#include <zephyr/ztest.h>
 
 #include "charge_state.h"
 #include "charge_state_v2.h"
@@ -173,16 +173,13 @@ static void *console_cmd_charge_state_setup(void)
 	static struct console_cmd_charge_state_fixture fixture;
 
 	/* Get references for the emulators */
-	fixture.tcpci_emul =
-		emul_get_binding(DT_LABEL(DT_NODELABEL(tcpci_emul)));
-	fixture.charger_emul =
-		emul_get_binding(DT_LABEL(DT_NODELABEL(isl923x_emul)));
+	fixture.tcpci_emul = EMUL_GET_USBC_BINDING(0, tcpc);
+	fixture.charger_emul = EMUL_GET_USBC_BINDING(0, chg);
 
 	/* Initialized the source to supply 5V and 3A */
 	tcpci_partner_init(&fixture.source_5v_3a, PD_REV20);
-	fixture.source_5v_3a.extensions =
-		tcpci_src_emul_init(&fixture.source_ext,
-				    &fixture.source_5v_3a, NULL);
+	fixture.source_5v_3a.extensions = tcpci_src_emul_init(
+		&fixture.source_ext, &fixture.source_5v_3a, NULL);
 	fixture.source_ext.pdo[1] =
 		PDO_FIXED(5000, 3000, PDO_FIXED_UNCONSTRAINED);
 
@@ -205,8 +202,8 @@ ZTEST_SUITE(console_cmd_charge_state, drivers_predicate_post_main,
 ZTEST_USER_F(console_cmd_charge_state, test_idle_on_from_normal)
 {
 	/* Connect a source so we start charging */
-	connect_source_to_port(&this->source_5v_3a, &this->source_ext, 1,
-			       this->tcpci_emul, this->charger_emul);
+	connect_source_to_port(&fixture->source_5v_3a, &fixture->source_ext, 1,
+			       fixture->tcpci_emul, fixture->charger_emul);
 
 	/* Verify that we're in "normal" mode */
 	zassume_equal(get_chg_ctrl_mode(), CHARGE_CONTROL_NORMAL, NULL);
@@ -219,8 +216,8 @@ ZTEST_USER_F(console_cmd_charge_state, test_idle_on_from_normal)
 ZTEST_USER_F(console_cmd_charge_state, test_normal_from_idle)
 {
 	/* Connect a source so we start charging */
-	connect_source_to_port(&this->source_5v_3a, &this->source_ext, 1,
-			       this->tcpci_emul, this->charger_emul);
+	connect_source_to_port(&fixture->source_5v_3a, &fixture->source_ext, 1,
+			       fixture->tcpci_emul, fixture->charger_emul);
 
 	/* Verify that we're in "normal" mode */
 	zassume_equal(get_chg_ctrl_mode(), CHARGE_CONTROL_NORMAL, NULL);
@@ -238,8 +235,8 @@ ZTEST_USER_F(console_cmd_charge_state, test_normal_from_idle)
 ZTEST_USER_F(console_cmd_charge_state, test_discharge_on)
 {
 	/* Connect a source so we start charging */
-	connect_source_to_port(&this->source_5v_3a, &this->source_ext, 1,
-			       this->tcpci_emul, this->charger_emul);
+	connect_source_to_port(&fixture->source_5v_3a, &fixture->source_ext, 1,
+			       fixture->tcpci_emul, fixture->charger_emul);
 
 	/* Verify that we're in "normal" mode */
 	zassume_equal(get_chg_ctrl_mode(), CHARGE_CONTROL_NORMAL, NULL);
@@ -253,8 +250,8 @@ ZTEST_USER_F(console_cmd_charge_state, test_discharge_on)
 ZTEST_USER_F(console_cmd_charge_state, test_discharge_off)
 {
 	/* Connect a source so we start charging */
-	connect_source_to_port(&this->source_5v_3a, &this->source_ext, 1,
-			       this->tcpci_emul, this->charger_emul);
+	connect_source_to_port(&fixture->source_5v_3a, &fixture->source_ext, 1,
+			       fixture->tcpci_emul, fixture->charger_emul);
 
 	/* Verify that we're in "normal" mode */
 	zassume_equal(get_chg_ctrl_mode(), CHARGE_CONTROL_NORMAL, NULL);
@@ -278,7 +275,8 @@ ZTEST_USER(console_cmd_charge_state, test_sustain)
 	zassert_ok(shell_execute_cmd(get_ec_shell(), "chgstate sustain 30 50"),
 		   NULL);
 
-	charge_control_values = host_cmd_get_charge_control();
+	charge_control_values = host_cmd_charge_control(
+		CHARGE_CONTROL_NORMAL, EC_CHARGE_CONTROL_CMD_GET);
 	zassert_equal(charge_control_values.sustain_soc.lower, 30, NULL);
 	zassert_equal(charge_control_values.sustain_soc.upper, 50, NULL);
 }
diff --git a/zephyr/test/drivers/default/src/console_cmd/charger.c b/zephyr/test/drivers/default/src/console_cmd/charger.c
new file mode 100644
index 0000000000..9adda29a8d
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/charger.c
@@ -0,0 +1,184 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+#include "console.h"
+#include "dptf.h"
+#include "ec_commands.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+/* Tests which need no fixture */
+ZTEST_USER(console_cmd_charger, test_default_dump)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "charger"),
+		   "Failed default print");
+}
+
+ZTEST_USER(console_cmd_charger, test_good_index)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "charger 0"),
+		   "Failed index 0 print");
+}
+
+/* Bad parameter tests */
+ZTEST_USER(console_cmd_charger, test_bad_index)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "charger 55");
+
+	zassert_equal(rv, EC_ERROR_PARAM1, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+}
+
+ZTEST_USER(console_cmd_charger, test_bad_command)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "charger fish");
+
+	zassert_equal(rv, EC_ERROR_PARAM1, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+}
+
+ZTEST_USER(console_cmd_charger, test_bad_input_current)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "charger input fish");
+
+	zassert_equal(rv, EC_ERROR_PARAM2, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+}
+
+ZTEST_USER(console_cmd_charger, test_bad_current)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "charger current fish");
+
+	zassert_equal(rv, EC_ERROR_PARAM2, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+}
+
+ZTEST_USER(console_cmd_charger, test_bad_voltage)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "charger voltage fish");
+
+	zassert_equal(rv, EC_ERROR_PARAM2, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+}
+
+ZTEST_USER(console_cmd_charger, test_bad_dptf_current)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "charger dptf fish");
+
+	zassert_equal(rv, EC_ERROR_PARAM2, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+}
+
+/* Good parameter sub-command tests */
+ZTEST_USER(console_cmd_charger, test_good_input_current)
+{
+	int input_current;
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "charger input 1000"),
+		   "Failed to set input current");
+	zassume_ok(charger_get_input_current_limit(0, &input_current),
+		   "Failed to get input current");
+	zassert_equal(input_current, 1000,
+		      "Input current not set in charger: %d", input_current);
+}
+
+ZTEST_USER(console_cmd_charger, test_good_dptf)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "charger dptf 1000"),
+		   "Failed to set dptf current");
+	zassert_equal(dptf_get_charging_current_limit(), 1000,
+		      "Unexpected dptf current");
+}
+
+ZTEST_USER(console_cmd_charger, test_unsupported_dump)
+{
+	/* Must define CONFIG_CMD_CHARGER_DUMP for this sub-command */
+	int rv = shell_execute_cmd(get_ec_shell(), "charger dump");
+
+	zassert_equal(rv, EC_ERROR_PARAM1, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+}
+
+/* Fixture needed to supply AC for manual current/voltage set */
+struct console_cmd_charger_fixture {
+	struct tcpci_partner_data source_5v_3a;
+	struct tcpci_src_emul_data source_ext;
+	const struct emul *tcpci_emul;
+	const struct emul *charger_emul;
+};
+
+static void *console_cmd_charger_setup(void)
+{
+	static struct console_cmd_charger_fixture fixture;
+
+	/* Assume we have one charger at index 0 */
+	zassume_true(board_get_charger_chip_count() > 0,
+		     "Insufficient chargers found");
+
+	/* Get references for the emulators */
+	fixture.tcpci_emul = EMUL_DT_GET(DT_NODELABEL(tcpci_emul));
+	fixture.charger_emul = EMUL_DT_GET(DT_NODELABEL(isl923x_emul));
+
+	/* Initialized the source to supply 5V and 3A */
+	tcpci_partner_init(&fixture.source_5v_3a, PD_REV20);
+	fixture.source_5v_3a.extensions = tcpci_src_emul_init(
+		&fixture.source_ext, &fixture.source_5v_3a, NULL);
+	fixture.source_ext.pdo[1] =
+		PDO_FIXED(5000, 3000, PDO_FIXED_UNCONSTRAINED);
+
+	return &fixture;
+}
+
+static void console_cmd_charger_after(void *data)
+{
+	struct console_cmd_charger_fixture *fixture = data;
+
+	/* Disconnect the source, and ensure we reset charge params */
+	disconnect_source_from_port(fixture->tcpci_emul, fixture->charger_emul);
+	host_cmd_charge_control(CHARGE_CONTROL_NORMAL,
+				EC_CHARGE_CONTROL_CMD_SET);
+}
+
+/* Tests that need the fixture */
+ZTEST_USER_F(console_cmd_charger, test_good_current)
+{
+	int current;
+
+	/* Connect a source so we start charging */
+	connect_source_to_port(&fixture->source_5v_3a, &fixture->source_ext, 1,
+			       fixture->tcpci_emul, fixture->charger_emul);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "charger current 1000"),
+		   "Failed to set current");
+
+	/* Give the charger task time to pick up the manual current */
+	k_sleep(K_SECONDS(1));
+
+	zassume_ok(charger_get_current(0, &current), "Failed to get current");
+	zassert_equal(current, 1000, "Current not set in charger: %d", current);
+}
+
+ZTEST_USER_F(console_cmd_charger, test_good_voltage)
+{
+	int voltage;
+
+	/* Connect a source so we start charging */
+	connect_source_to_port(&fixture->source_5v_3a, &fixture->source_ext, 1,
+			       fixture->tcpci_emul, fixture->charger_emul);
+	/* Note: select a fake voltage larger than the charger's minimum */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "charger voltage 3000"),
+		   "Failed to set voltage");
+
+	/* Give the charger task time to pick up the manual voltage */
+	k_sleep(K_SECONDS(1));
+
+	zassume_ok(charger_get_voltage(0, &voltage), "Failed to get voltage");
+	zassert_equal(voltage, 3000, "Voltage not set in charger: %d", voltage);
+}
+
+ZTEST_SUITE(console_cmd_charger, drivers_predicate_post_main,
+	    console_cmd_charger_setup, NULL, console_cmd_charger_after, NULL);
diff --git a/zephyr/test/drivers/default/src/console_cmd/crash.c b/zephyr/test/drivers/default/src/console_cmd/crash.c
new file mode 100644
index 0000000000..bc0b5d0254
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/crash.c
@@ -0,0 +1,34 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+#include "builtin/assert.h"
+#include "console.h"
+#include "test/drivers/test_mocks.h"
+#include "test/drivers/test_state.h"
+
+ZTEST_SUITE(console_cmd_crash, drivers_predicate_post_main, NULL, NULL, NULL,
+	    NULL);
+
+ZTEST_USER(console_cmd_crash, test_wrong_num_args)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "crash");
+
+	zassert_equal(EC_ERROR_PARAM1, rv, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+}
+
+ZTEST_USER(console_cmd_crash, test_assert)
+{
+	int rv;
+
+	RESET_FAKE(assert_post_action);
+	rv = shell_execute_cmd(get_ec_shell(), "crash assert");
+
+	zassert_equal(EC_ERROR_UNKNOWN, rv, NULL);
+	zassert_equal(1, assert_post_action_fake.call_count, NULL);
+}
diff --git a/zephyr/test/drivers/default/src/console_cmd/cutoff.c b/zephyr/test/drivers/default/src/console_cmd/cutoff.c
new file mode 100644
index 0000000000..00ce40660f
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/cutoff.c
@@ -0,0 +1,86 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+#include "battery.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "hooks.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+static void console_cmd_cutoff_after(void *unused)
+{
+	ARG_UNUSED(unused);
+	set_ac_enabled(true);
+	hook_notify(HOOK_AC_CHANGE);
+	k_msleep(500);
+}
+
+ZTEST_SUITE(console_cmd_cutoff, drivers_predicate_post_main, NULL, NULL,
+	    console_cmd_cutoff_after, NULL);
+
+ZTEST_USER(console_cmd_cutoff, test_sb_cutoff)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "cutoff");
+
+	zassert_equal(EC_RES_SUCCESS, rv, "Expected %d, but got %d",
+		      EC_RES_SUCCESS, rv);
+	zassert_true(battery_is_cut_off(), NULL);
+}
+
+ZTEST_USER(console_cmd_cutoff, test_invalid_arg1)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "cutoff bad_arg");
+
+	zassert_equal(EC_ERROR_INVAL, rv, "Expected %d, but got %d",
+		      EC_ERROR_INVAL, rv);
+	zassert_false(battery_is_cut_off(), NULL);
+}
+
+ZTEST_USER(console_cmd_cutoff, test_at_shutdown)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "cutoff at-shutdown");
+
+	zassert_equal(EC_RES_SUCCESS, rv, "Expected %d, but got %d",
+		      EC_RES_SUCCESS, rv);
+	zassert_false(battery_is_cut_off(), NULL);
+	hook_notify(HOOK_CHIPSET_SHUTDOWN);
+	zassert_true(WAIT_FOR(battery_is_cut_off(), 1500000, k_msleep(250)),
+		     NULL);
+}
+
+ZTEST_USER(console_cmd_cutoff, test_clear_pending_shutdown)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "cutoff at-shutdown");
+
+	zassume_true(extpower_is_present(), NULL);
+	zassert_equal(EC_RES_SUCCESS, rv, "Expected %d, but got %d",
+		      EC_RES_SUCCESS, rv);
+
+	/* Triggering the AC_CHANGE hook will cancel the pending cutoff */
+	hook_notify(HOOK_AC_CHANGE);
+
+	/* The shutdown will no longer cutoff the battery */
+	hook_notify(HOOK_CHIPSET_SHUTDOWN);
+	zassert_false(WAIT_FOR(battery_is_cut_off(), 1500000, k_msleep(250)),
+		      NULL);
+}
+
+ZTEST_USER(console_cmd_cutoff, test_ac_change_exits_cutoff)
+{
+	int rv;
+
+	set_ac_enabled(false);
+
+	rv = shell_execute_cmd(get_ec_shell(), "cutoff");
+	zassert_equal(EC_RES_SUCCESS, rv, "Expected %d, but got %d",
+		      EC_RES_SUCCESS, rv);
+
+	set_ac_enabled(true);
+	zassert_false(battery_is_cut_off(), NULL);
+}
diff --git a/zephyr/test/drivers/default/src/console_cmd/gpio.c b/zephyr/test/drivers/default/src/console_cmd/gpio.c
new file mode 100644
index 0000000000..164f272e27
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/gpio.c
@@ -0,0 +1,37 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+#include "console.h"
+#include "ec_commands.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+ZTEST_USER(console_cmd_gpio, test_read_invoke_success)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "gpioget test"), NULL);
+}
+
+ZTEST_USER(console_cmd_gpio, test_read_invoke_fail)
+{
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "gpioget DOES_NOT_EXIST"),
+		   NULL);
+}
+
+ZTEST_USER(console_cmd_gpio, test_set_gpio)
+{
+	const struct gpio_dt_spec *gp = GPIO_DT_FROM_NODELABEL(gpio_test);
+
+	zassert_ok(gpio_pin_set_dt(gp, 0), NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "gpioset test 1"), NULL);
+	zassert_equal(gpio_pin_get_dt(gp), 1, NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "gpioset test 0"), NULL);
+	zassert_equal(gpio_pin_get_dt(gp), 0, NULL);
+}
+
+ZTEST_SUITE(console_cmd_gpio, drivers_predicate_post_main, NULL, NULL, NULL,
+	    NULL);
diff --git a/zephyr/test/drivers/default/src/console_cmd/hcdebug.c b/zephyr/test/drivers/default/src/console_cmd/hcdebug.c
new file mode 100644
index 0000000000..71adb02690
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/hcdebug.c
@@ -0,0 +1,49 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+#include "console.h"
+#include "ec_commands.h"
+#include "test/drivers/test_state.h"
+
+static void console_cmd_hcdebug_after(void *fixture)
+{
+	ARG_UNUSED(fixture);
+	shell_execute_cmd(get_ec_shell(), "hcdebug off");
+}
+
+ZTEST_SUITE(console_cmd_hcdebug, drivers_predicate_post_main, NULL, NULL,
+	    console_cmd_hcdebug_after, NULL);
+
+ZTEST_USER(console_cmd_hcdebug, test_too_many_args)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "hcdebug arg1 arg2");
+
+	zassert_not_equal(rv, EC_SUCCESS, "Expected %d, but got %d",
+			  EC_ERROR_PARAM_COUNT, rv);
+}
+
+ZTEST_USER(console_cmd_hcdebug, test_no_args)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "hcdebug"), NULL);
+}
+
+ZTEST_USER(console_cmd_hcdebug, test_invalid_arg)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "hcdebug bar");
+
+	zassert_equal(rv, EC_ERROR_PARAM1, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+}
+
+ZTEST_USER(console_cmd_hcdebug, test_valid_args)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "hcdebug off"), NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "hcdebug normal"), NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "hcdebug every"), NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "hcdebug params"), NULL);
+}
diff --git a/zephyr/test/drivers/default/src/console_cmd/hibdelay.c b/zephyr/test/drivers/default/src/console_cmd/hibdelay.c
new file mode 100644
index 0000000000..c72a2bf66a
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/hibdelay.c
@@ -0,0 +1,37 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+#include "console.h"
+#include "ec_commands.h"
+#include "test/drivers/test_state.h"
+
+ZTEST_SUITE(console_cmd_hibdelay, drivers_predicate_post_main, NULL, NULL, NULL,
+	    NULL);
+
+ZTEST_USER(console_cmd_hibdelay, test_too_many_args)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "hibdelay 1 2"), NULL);
+}
+
+ZTEST_USER(console_cmd_hibdelay, test_no_args)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "hibdelay"), NULL);
+}
+
+ZTEST_USER(console_cmd_hibdelay, test_invalid_arg)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "hibdelay 3.4");
+
+	zassert_equal(rv, EC_ERROR_PARAM1, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+}
+
+ZTEST_USER(console_cmd_hibdelay, test_valid_args)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "hibdelay 5"), NULL);
+}
diff --git a/zephyr/test/drivers/default/src/console_cmd/hostevent.c b/zephyr/test/drivers/default/src/console_cmd/hostevent.c
new file mode 100644
index 0000000000..af9b37edd1
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/hostevent.c
@@ -0,0 +1,193 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+#include "console.h"
+#include "ec_commands.h"
+#include "include/lpc.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#ifdef CONFIG_HOST_EVENT64
+#define HOSTEVENT_PRINT_FORMAT "016" PRIx64
+#else
+#define HOSTEVENT_PRINT_FORMAT "08" PRIx32
+#endif
+
+struct console_cmd_hostevent_fixture {
+	struct host_events_ctx ctx;
+};
+
+static void *console_cmd_hostevent_setup(void)
+{
+	static struct console_cmd_hostevent_fixture fixture = { 0 };
+
+	return &fixture;
+}
+
+static void console_cmd_hostevent_before(void *fixture)
+{
+	struct console_cmd_hostevent_fixture *f = fixture;
+
+	host_events_save(&f->ctx);
+}
+
+static void console_cmd_hostevent_after(void *fixture)
+{
+	struct console_cmd_hostevent_fixture *f = fixture;
+
+	host_events_restore(&f->ctx);
+}
+
+static int console_cmd_hostevent(const char *subcommand, host_event_t mask)
+{
+	int rv;
+	char cmd_buf[CONFIG_SHELL_CMD_BUFF_SIZE];
+
+	rv = snprintf(cmd_buf, CONFIG_SHELL_CMD_BUFF_SIZE,
+		      "hostevent %s 0x%" HOSTEVENT_PRINT_FORMAT, subcommand,
+		      mask);
+
+	zassume_between_inclusive(rv, 0, CONFIG_SHELL_CMD_BUFF_SIZE,
+				  "hostevent console command too long");
+
+	return shell_execute_cmd(get_ec_shell(), cmd_buf);
+}
+
+/* hostevent with no arguments */
+ZTEST_USER(console_cmd_hostevent, test_hostevent)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "hostevent"),
+		   "Failed default print");
+}
+
+/* hostevent with invalid arguments */
+ZTEST_USER(console_cmd_hostevent, test_hostevent_invalid)
+{
+	int rv;
+	host_event_t mask = 0;
+
+	/* Test invalid sub-command */
+	rv = console_cmd_hostevent("invalid", mask);
+	zassert_equal(rv, EC_ERROR_PARAM1, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+
+	/* Test invalid mask */
+	rv = shell_execute_cmd(get_ec_shell(), "hostevent set invalid-mask");
+	zassert_equal(rv, EC_ERROR_PARAM2, "Expected %d, but got %d",
+		      EC_ERROR_PARAM2, rv);
+}
+
+/* hostevent with sub-commands and verification */
+ZTEST_USER(console_cmd_hostevent, test_hostevent_sub_commands)
+{
+	int rv;
+	enum ec_status ret_val;
+	host_event_t event_mask;
+	host_event_t all_events = 0;
+	host_event_t set_events;
+	struct ec_response_host_event result = { 0 };
+	struct {
+		enum lpc_host_event_type type;
+		const char *name;
+		host_event_t mask;
+	} subcommand[] = {
+		{
+			.type = LPC_HOST_EVENT_SMI,
+			.name = "SMI",
+			.mask = EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED),
+		},
+		{
+			.type = LPC_HOST_EVENT_SCI,
+			.name = "SCI",
+			.mask = EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN),
+		},
+		{
+			.type = LPC_HOST_EVENT_WAKE,
+			.name = "WAKE",
+			.mask = EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON),
+		},
+		{
+			.type = LPC_HOST_EVENT_ALWAYS_REPORT,
+			.name = "ALWAYS_REPORT",
+			.mask = EC_HOST_EVENT_MASK(
+				EC_HOST_EVENT_AC_DISCONNECTED),
+		},
+	};
+
+	for (int i = 0; i < ARRAY_SIZE(subcommand); i++) {
+		event_mask = lpc_get_host_event_mask(subcommand[i].type);
+		zassert_false(event_mask & subcommand[i].mask,
+			      "%s mask is set before test started",
+			      subcommand[i].name);
+		/*
+		 * Setting mask value overwrites existing setting, so OR in
+		 * the test bit.
+		 */
+		event_mask |= subcommand[i].mask;
+		rv = console_cmd_hostevent(subcommand[i].name, event_mask);
+		zassert_ok(rv, "Subcommand %s failed", subcommand[i].name);
+		zassert_true(lpc_get_host_event_mask(subcommand[i].type) &
+				     subcommand[i].mask,
+			     "Failed to set %s event mask", subcommand[i].name);
+
+		/*
+		 * It is only valid to set host events, once at least one mask
+		 * value includes the event.  Setting host events preserves
+		 * existing events.
+		 */
+		zassert_false(host_get_events() & subcommand[i].mask,
+			      "Host event is set before test started");
+		rv = console_cmd_hostevent("set", subcommand[i].mask);
+		zassert_ok(rv, "Subcommand SET failed");
+
+		all_events |= subcommand[i].mask;
+	}
+
+	/* Verify all host events were set, and none were lost */
+	zassert_true((host_get_events() & all_events) == all_events,
+		     "Failed to set host events");
+
+	/* Test clearing of host events */
+	set_events = all_events;
+	for (int i = 0; i < ARRAY_SIZE(subcommand); i++) {
+		set_events &= ~subcommand[i].mask;
+		rv = console_cmd_hostevent("clear", subcommand[i].mask);
+		zassert_ok(rv, "Subcommand CLEAR failed");
+
+		zassert_true((host_get_events() & set_events) == set_events,
+			     "Failed to clear host event");
+	}
+
+	/* Verify the backup host events were set, and none were cleared */
+	ret_val = host_cmd_host_event(EC_HOST_EVENT_GET, EC_HOST_EVENT_B,
+				      &result);
+	zassert_equal(ret_val, EC_RES_SUCCESS, "Expected=%d, returned=%d",
+		      EC_RES_SUCCESS, ret_val);
+	zassert_true((result.value & all_events) == all_events,
+		     "Failed to set host events backup");
+
+	/* Test clearing of backup host events */
+	set_events = all_events;
+	for (int i = 0; i < ARRAY_SIZE(subcommand); i++) {
+		set_events &= ~subcommand[i].mask;
+		rv = console_cmd_hostevent("clearb", subcommand[i].mask);
+		zassert_ok(rv, "Subcommand CLEAR failed");
+
+		ret_val = host_cmd_host_event(EC_HOST_EVENT_GET,
+					      EC_HOST_EVENT_B, &result);
+		zassert_equal(ret_val, EC_RES_SUCCESS,
+			      "Expected=%d, returned=%d", EC_RES_SUCCESS,
+			      ret_val);
+		zassert_true((result.value & set_events) == set_events,
+			     "Failed to clear host events backup");
+	}
+}
+
+ZTEST_SUITE(console_cmd_hostevent, drivers_predicate_post_main,
+	    console_cmd_hostevent_setup, console_cmd_hostevent_before,
+	    console_cmd_hostevent_after, NULL);
diff --git a/zephyr/test/drivers/default/src/console_cmd/i2c_portmap.c b/zephyr/test/drivers/default/src/console_cmd/i2c_portmap.c
new file mode 100644
index 0000000000..4b2ec548a2
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/i2c_portmap.c
@@ -0,0 +1,27 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+#include "console.h"
+#include "ec_commands.h"
+#include "test/drivers/test_state.h"
+
+ZTEST_SUITE(console_cmd_i2c_portmap, drivers_predicate_post_main, NULL, NULL,
+	    NULL, NULL);
+
+ZTEST_USER(console_cmd_i2c_portmap, test_too_many_args)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "i2c_portmap arg1");
+
+	zassert_equal(rv, EC_ERROR_PARAM_COUNT, "Expected %d, but got %d",
+		      EC_ERROR_PARAM_COUNT, rv);
+}
+
+ZTEST_USER(console_cmd_i2c_portmap, test_get_i2c_portmap)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "i2c_portmap"), NULL);
+}
diff --git a/zephyr/test/drivers/default/src/console_cmd/md.c b/zephyr/test/drivers/default/src/console_cmd/md.c
new file mode 100644
index 0000000000..c8c3e2c130
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/md.c
@@ -0,0 +1,83 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+#include "console.h"
+#include "test/drivers/test_state.h"
+
+ZTEST_SUITE(console_cmd_md, drivers_predicate_post_main, NULL, NULL, NULL,
+	    NULL);
+
+ZTEST_USER(console_cmd_md, test_too_few_args)
+{
+	zassert_equal(EC_ERROR_PARAM_COUNT,
+		      shell_execute_cmd(get_ec_shell(), "md"), NULL);
+}
+
+ZTEST_USER(console_cmd_md, test_error_param1)
+{
+	zassert_equal(EC_ERROR_PARAM1,
+		      shell_execute_cmd(get_ec_shell(), "md .j"), NULL);
+}
+
+ZTEST_USER(console_cmd_md, test_error_bad_address)
+{
+	zassert_equal(EC_ERROR_PARAM1,
+		      shell_execute_cmd(get_ec_shell(), "md not_an_address"),
+		      NULL);
+}
+
+ZTEST_USER(console_cmd_md, test_default_count)
+{
+	uint8_t memory[] = { 0x01, 0x02, 0x03, 0x04 };
+	char cmd[128] = { 0 };
+
+	zassume_true(sprintf(cmd, "md %" PRIuPTR, (uintptr_t)memory) != 0,
+		     NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), cmd), NULL);
+}
+
+ZTEST_USER(console_cmd_md, test_count_arg)
+{
+	uint8_t memory[] = { 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08 };
+	char cmd[128] = { 0 };
+
+	zassume_true(sprintf(cmd, "md %" PRIuPTR " 2", (uintptr_t)memory) != 0,
+		     NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), cmd), NULL);
+}
+
+ZTEST_USER(console_cmd_md, test_byte_format)
+{
+	uint8_t memory[] = { 0x01, 0x02, 0x03, 0x04 };
+	char cmd[128] = { 0 };
+
+	zassume_true(sprintf(cmd, "md .b %" PRIuPTR, (uintptr_t)memory) != 0,
+		     NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), cmd), NULL);
+}
+
+ZTEST_USER(console_cmd_md, test_half_format)
+{
+	uint8_t memory[] = { 0x01, 0x02, 0x03, 0x04 };
+	char cmd[128] = { 0 };
+
+	zassume_true(sprintf(cmd, "md .h %" PRIuPTR, (uintptr_t)memory) != 0,
+		     NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), cmd), NULL);
+}
+
+ZTEST_USER(console_cmd_md, test_string_format)
+{
+	char memory[] = "hello world";
+	char cmd[128] = { 0 };
+
+	zassume_true(sprintf(cmd, "md .s %" PRIuPTR " 12", (uintptr_t)memory) !=
+			     0,
+		     NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), cmd), NULL);
+}
diff --git a/zephyr/test/drivers/default/src/console_cmd/panic_output.c b/zephyr/test/drivers/default/src/console_cmd/panic_output.c
new file mode 100644
index 0000000000..7cc809e835
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/panic_output.c
@@ -0,0 +1,71 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+#include "console.h"
+#include "ec_commands.h"
+#include "panic.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+/* Test panicinfo when a panic hasn't occurred */
+ZTEST_USER(console_cmd_panic_output, test_panicinfo)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "panicinfo"),
+		   "Failed default print");
+}
+
+/* Test panicinfo when a panic hasn't occurred with an extra arg. */
+/* Should return successfully. */
+ZTEST_USER(console_cmd_panic_output, test_panicinfo_bad_arg)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "panicinfo fish"),
+		   "Failed default print with a bad argument");
+}
+
+/* Fixture needed to save panic data state */
+struct console_cmd_panic_output_fixture {
+	struct panic_data *p_data;
+	struct panic_data cpy_data;
+};
+
+static void *console_cmd_panic_setup(void)
+{
+	static struct console_cmd_panic_output_fixture fixture;
+
+	return &fixture;
+}
+
+static void console_cmd_panic_before(void *data)
+{
+	struct console_cmd_panic_output_fixture *fixture = data;
+
+	fixture->p_data = get_panic_data_write();
+	fixture->cpy_data = *fixture->p_data;
+}
+
+static void console_cmd_panic_after(void *data)
+{
+	struct console_cmd_panic_output_fixture *fixture = data;
+
+	struct panic_data *p_data = fixture->p_data;
+
+	*p_data = fixture->cpy_data;
+}
+
+/* Tests that need the fixture */
+ZTEST_USER_F(console_cmd_panic_output, test_panicinfo_with_panic)
+{
+	fixture->p_data->flags = 0x1;
+	fixture->p_data->struct_size = CONFIG_PANIC_DATA_SIZE;
+	fixture->p_data->magic = PANIC_DATA_MAGIC;
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "panicinfo"),
+		   "Failed to print details about panic.");
+}
+
+ZTEST_SUITE(console_cmd_panic_output, NULL, console_cmd_panic_setup,
+	    console_cmd_panic_before, console_cmd_panic_after, NULL);
diff --git a/zephyr/test/drivers/default/src/console_cmd/port80.c b/zephyr/test/drivers/default/src/console_cmd/port80.c
new file mode 100644
index 0000000000..792895eb27
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/port80.c
@@ -0,0 +1,46 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ * @brief Unit Tests for ESPI port 80 console command
+ */
+
+#include <zephyr/logging/log.h>
+#include <zephyr/shell/shell.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+#include "console.h"
+#include "ec_commands.h"
+#include "port80.h"
+
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+/**
+ * @brief TestPurpose: Verify port 80 console commands
+ *
+ * @details
+ * Validate that the port 80 console commands work.
+ *
+ * Expected Results
+ *  - The port 80 console commands return the appropriate result
+ */
+ZTEST(port80, test_port80_console)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "port80"), NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "port80 flush"), NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "port80 scroll"), NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "port80 intprint"), NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "port80 unknown_param"),
+		   NULL);
+}
+
+/**
+ * @brief Test Suite: Verifies port 80 console commands.
+ */
+ZTEST_SUITE(console_cmd_port80, drivers_predicate_post_main, NULL, NULL, NULL,
+	    NULL);
diff --git a/zephyr/test/drivers/default/src/console_cmd/power_button.c b/zephyr/test/drivers/default/src/console_cmd/power_button.c
new file mode 100644
index 0000000000..92d0aeaf78
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/power_button.c
@@ -0,0 +1,34 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/ztest.h>
+#include <console.h>
+
+ZTEST_SUITE(console_cmd_power_button, NULL, NULL, NULL, NULL, NULL);
+
+ZTEST_USER(console_cmd_power_button, test_return_ok)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "powerbtn"), NULL);
+}
+
+ZTEST_USER(console_cmd_power_button, test_negative_delay)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "powerbtn -1");
+
+	zassert_not_equal(rv, EC_SUCCESS,
+			  "Command should error on negative delay");
+}
+
+ZTEST_USER(console_cmd_power_button, test_invalid_arg)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "powerbtn foo");
+
+	zassert_equal(rv, EC_ERROR_PARAM1, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+}
diff --git a/zephyr/test/drivers/default/src/console_cmd/powerindebug.c b/zephyr/test/drivers/default/src/console_cmd/powerindebug.c
new file mode 100644
index 0000000000..9f52a9b569
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/powerindebug.c
@@ -0,0 +1,36 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+#include "console.h"
+#include "ec_commands.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+ZTEST_USER(console_cmd_powerindebug, test_no_params)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "powerindebug"),
+		   "Failed to get debug mask");
+}
+
+ZTEST_USER(console_cmd_powerindebug, test_good_params)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "powerindebug 0x10"),
+		   "Failed to set debug mask");
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "powerindebug 0"),
+		   "Failed to set debug mask");
+}
+
+ZTEST_USER(console_cmd_powerindebug, test_bad_params)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "powerindebug fish");
+
+	zassert_equal(rv, EC_ERROR_PARAM1, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+}
+
+ZTEST_SUITE(console_cmd_powerindebug, NULL, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/drivers/default/src/console_cmd/rtc.c b/zephyr/test/drivers/default/src/console_cmd/rtc.c
new file mode 100644
index 0000000000..80530129af
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/rtc.c
@@ -0,0 +1,73 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/ztest.h>
+
+#include "console.h"
+#include "ec_commands.h"
+#include "system.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+ZTEST_USER(console_cmd_rtc, test_rtc_no_arg)
+{
+	char expected_buffer[32];
+	uint32_t sec = 7;
+
+	snprintf(expected_buffer, sizeof(expected_buffer),
+		 "RTC: 0x%08x (%d.00 s)", sec, sec);
+
+	system_set_rtc(sec);
+
+	CHECK_CONSOLE_CMD("rtc", expected_buffer, EC_SUCCESS);
+}
+
+ZTEST_USER(console_cmd_rtc, test_rtc_invalid)
+{
+	CHECK_CONSOLE_CMD("rtc set", NULL, EC_ERROR_INVAL);
+}
+
+ZTEST_USER(console_cmd_rtc, test_rtc_set)
+{
+	char command[32];
+	char expected_buffer[32];
+	uint32_t sec = 48879;
+
+	snprintf(expected_buffer, sizeof(expected_buffer),
+		 "RTC: 0x%08x (%d.00 s)", sec, sec);
+	snprintf(command, sizeof(command), "rtc set %d", sec);
+
+	CHECK_CONSOLE_CMD(command, expected_buffer, EC_SUCCESS);
+}
+
+ZTEST_USER(console_cmd_rtc, test_rtc_set_bad)
+{
+	CHECK_CONSOLE_CMD("rtc set t", NULL, EC_ERROR_PARAM2);
+}
+
+ZTEST_USER(console_cmd_rtc, test_rtc_alarm_no_args)
+{
+	CHECK_CONSOLE_CMD("rtc_alarm", "Setting RTC alarm", EC_SUCCESS);
+}
+
+ZTEST_USER(console_cmd_rtc, test_rtc_alarm_good_args)
+{
+	CHECK_CONSOLE_CMD("rtc_alarm 1", "Setting RTC alarm", EC_SUCCESS);
+	CHECK_CONSOLE_CMD("rtc_alarm 1 5", "Setting RTC alarm", EC_SUCCESS);
+}
+
+ZTEST_USER(console_cmd_rtc, test_rtc_alarm_bad_args)
+{
+	CHECK_CONSOLE_CMD("rtc_alarm t", NULL, EC_ERROR_PARAM1);
+	CHECK_CONSOLE_CMD("rtc_alarm 1 t", NULL, EC_ERROR_PARAM2);
+}
+
+ZTEST_USER(console_cmd_rtc, test_rtc_alarm_reset)
+{
+	CHECK_CONSOLE_CMD("rtc_alarm 0", "Setting RTC alarm", EC_SUCCESS);
+	CHECK_CONSOLE_CMD("rtc_alarm 0 0", "Setting RTC alarm", EC_SUCCESS);
+}
+
+ZTEST_SUITE(console_cmd_rtc, NULL, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/drivers/default/src/console_cmd/rw.c b/zephyr/test/drivers/default/src/console_cmd/rw.c
new file mode 100644
index 0000000000..2bf59b30d5
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/rw.c
@@ -0,0 +1,98 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+#include "console.h"
+#include "test/drivers/test_state.h"
+
+ZTEST_SUITE(console_cmd_rw, drivers_predicate_post_main, NULL, NULL, NULL,
+	    NULL);
+
+ZTEST_USER(console_cmd_rw, test_too_few_args)
+{
+	zassert_equal(EC_ERROR_PARAM_COUNT,
+		      shell_execute_cmd(get_ec_shell(), "rw"), NULL);
+}
+
+ZTEST_USER(console_cmd_rw, test_error_param1)
+{
+	zassert_equal(EC_ERROR_PARAM1,
+		      shell_execute_cmd(get_ec_shell(), "rw .j"), NULL);
+}
+
+ZTEST_USER(console_cmd_rw, test_error_bad_address)
+{
+	zassert_equal(EC_ERROR_PARAM1,
+		      shell_execute_cmd(get_ec_shell(), "rw not_an_address"),
+		      NULL);
+	zassert_equal(EC_ERROR_PARAM2,
+		      shell_execute_cmd(get_ec_shell(), "rw .b not_an_address"),
+		      NULL);
+}
+
+ZTEST_USER(console_cmd_rw, test_read)
+{
+	uint8_t memory[] = { 0x01, 0x02, 0x03, 0x04 };
+	char cmd[128] = { 0 };
+
+	zassume_true(sprintf(cmd, "rw .b %" PRIuPTR, (uintptr_t)memory) != 0,
+		     NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), cmd), NULL);
+
+	zassume_true(sprintf(cmd, "rw .h %" PRIuPTR, (uintptr_t)memory) != 0,
+		     NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), cmd), NULL);
+
+	zassume_true(sprintf(cmd, "rw %" PRIuPTR, (uintptr_t)memory) != 0,
+		     NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), cmd), NULL);
+}
+
+ZTEST_USER(console_cmd_rw, test_write_invalid_value)
+{
+	zassert_equal(EC_ERROR_PARAM2,
+		      shell_execute_cmd(get_ec_shell(), "rw 0 not-a-value"),
+		      NULL);
+	zassert_equal(EC_ERROR_PARAM3,
+		      shell_execute_cmd(get_ec_shell(), "rw .b 0 not-a-value"),
+		      NULL);
+}
+
+ZTEST_USER(console_cmd_rw, test_write)
+{
+	uint8_t memory[4] = { 0 };
+	char cmd[128] = { 0 };
+
+	zassume_true(sprintf(cmd, "rw .b %" PRIuPTR " 1", (uintptr_t)memory) !=
+			     0,
+		     NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), cmd), NULL);
+	zassert_equal(1, memory[0], "memory[0] was %u", memory[0]);
+	zassert_equal(0, memory[1], "memory[1] was %u", memory[1]);
+	zassert_equal(0, memory[2], "memory[2] was %u", memory[2]);
+	zassert_equal(0, memory[3], "memory[3] was %u", memory[3]);
+
+	memset(memory, 0, 4);
+	zassume_true(sprintf(cmd, "rw .h %" PRIuPTR " 258",
+			     (uintptr_t)memory) != 0,
+		     NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), cmd), NULL);
+	zassert_equal(2, memory[0], "memory[0] was %u", memory[0]);
+	zassert_equal(1, memory[1], "memory[1] was %u", memory[1]);
+	zassert_equal(0, memory[2], "memory[2] was %u", memory[2]);
+	zassert_equal(0, memory[3], "memory[3] was %u", memory[3]);
+
+	memset(memory, 0, 4);
+	zassume_true(sprintf(cmd, "rw %" PRIuPTR " 16909060",
+			     (uintptr_t)memory) != 0,
+		     NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), cmd), NULL);
+	zassert_equal(4, memory[0], "memory[0] was %u", memory[0]);
+	zassert_equal(3, memory[1], "memory[1] was %u", memory[1]);
+	zassert_equal(2, memory[2], "memory[2] was %u", memory[2]);
+	zassert_equal(1, memory[3], "memory[3] was %u", memory[3]);
+}
diff --git a/zephyr/test/drivers/default/src/console_cmd/sleepmask.c b/zephyr/test/drivers/default/src/console_cmd/sleepmask.c
new file mode 100644
index 0000000000..6ae017dc66
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/sleepmask.c
@@ -0,0 +1,100 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/shell/shell_dummy.h>
+#include <zephyr/ztest.h>
+
+#include "console.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "system.h"
+
+ZTEST_USER(console_cmd_sleepmask, test_no_args)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+	const char *outbuffer;
+	size_t buffer_size;
+
+	shell_backend_dummy_clear_output(shell_zephyr);
+
+	zassert_ok(shell_execute_cmd(shell_zephyr, "sleepmask"), NULL);
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+
+	zassert_true(buffer_size > 0, NULL);
+	zassert_not_null(strstr(outbuffer, "sleep mask"), NULL);
+}
+
+ZTEST_USER(console_cmd_sleepmask, test_bad_args)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+
+	zassert_equal(EC_ERROR_PARAM1,
+		      shell_execute_cmd(shell_zephyr, "sleepmask whoopsie"),
+		      NULL);
+}
+
+ZTEST_USER(console_cmd_sleepmask, test_set_sleep_mask_directly)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+	const char *outbuffer;
+	size_t buffer_size;
+
+	shell_backend_dummy_clear_output(shell_zephyr);
+
+	/* Set mask as 0 */
+	zassert_ok(shell_execute_cmd(shell_zephyr, "sleepmask 0"), NULL);
+	shell_backend_dummy_clear_output(shell_zephyr);
+
+	/* Get mask and weakly verify mask is 0 */
+	zassert_ok(shell_execute_cmd(shell_zephyr, "sleepmask"), NULL);
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+
+	zassert_not_null(strstr(outbuffer, "0"), NULL);
+	zassert_is_null(strstr(outbuffer, "1"), NULL);
+
+	/* Set mask as 1 */
+	zassert_ok(shell_execute_cmd(shell_zephyr, "sleepmask 1"), NULL);
+	shell_backend_dummy_clear_output(shell_zephyr);
+
+	/* Get mask and weakly verify mask is 1 */
+	zassert_ok(shell_execute_cmd(shell_zephyr, "sleepmask"), NULL);
+	zassert_not_null(strstr(outbuffer, "1"), NULL);
+}
+
+ZTEST_USER(console_cmd_sleepmask, test_enable_disable_force_sleepmask)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+
+	/* Verifying enabled to disabled */
+
+	zassert_ok(shell_execute_cmd(shell_zephyr, "sleepmask on"), NULL);
+
+	int enabled_bits = sleep_mask & SLEEP_MASK_FORCE_NO_DSLEEP;
+
+	zassert_ok(shell_execute_cmd(shell_zephyr, "sleepmask off"), NULL);
+
+	int disabled_bits = sleep_mask & SLEEP_MASK_FORCE_NO_DSLEEP;
+
+	zassert_false(enabled_bits & disabled_bits, NULL);
+
+	/* Verifying disabled to enabled */
+
+	zassert_ok(shell_execute_cmd(shell_zephyr, "sleepmask on"), NULL);
+
+	enabled_bits = sleep_mask & SLEEP_MASK_FORCE_NO_DSLEEP;
+	zassert_false(enabled_bits & disabled_bits, NULL);
+}
+
+static void console_cmd_sleepmask_before_after(void *test_data)
+{
+	ARG_UNUSED(test_data);
+
+	enable_sleep(-1);
+}
+
+ZTEST_SUITE(console_cmd_sleepmask, drivers_predicate_post_main, NULL,
+	    console_cmd_sleepmask_before_after,
+	    console_cmd_sleepmask_before_after, NULL);
diff --git a/zephyr/test/drivers/default/src/console_cmd/sleeptimeout.c b/zephyr/test/drivers/default/src/console_cmd/sleeptimeout.c
new file mode 100644
index 0000000000..d802eb5948
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/sleeptimeout.c
@@ -0,0 +1,44 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+#include "console.h"
+#include "ec_commands.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+ZTEST_USER(console_cmd_sleeptimeout, test_no_params)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "sleeptimeout"),
+		   "Failed default print");
+}
+
+ZTEST_USER(console_cmd_sleeptimeout, test_good_params)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "sleeptimeout default"),
+		   "Failed to set default sleep timeout");
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "sleeptimeout infinite"),
+		   "Failed to disable sleep timeout");
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "sleeptimeout 1500"),
+		   "Failed to set sleep timeout to a custom value");
+}
+
+ZTEST_USER(console_cmd_sleeptimeout, test_bad_params)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "sleeptimeout 0");
+
+	zassert_equal(rv, EC_ERROR_PARAM1, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+
+	rv = shell_execute_cmd(get_ec_shell(),
+			       "sleeptimeout EC_HOST_SLEEP_TIMEOUT_INFINITE");
+
+	zassert_equal(rv, EC_ERROR_PARAM1, "Expected %d, but got %d",
+		      EC_ERROR_PARAM1, rv);
+}
+
+ZTEST_SUITE(console_cmd_sleeptimeout, NULL, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/drivers/default/src/console_cmd/sysinfo.c b/zephyr/test/drivers/default/src/console_cmd/sysinfo.c
new file mode 100644
index 0000000000..3aeef6510c
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/sysinfo.c
@@ -0,0 +1,84 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/fff.h>
+#include <zephyr/shell/shell_dummy.h>
+#include <zephyr/ztest.h>
+
+#include "console.h"
+#include "test/drivers/test_mocks.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "system.h"
+
+ZTEST_USER(console_cmd_sysinfo, test_no_args)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+	const char *outbuffer;
+	size_t buffer_size;
+
+	shell_backend_dummy_clear_output(shell_zephyr);
+
+	zassert_ok(shell_execute_cmd(shell_zephyr, "sysinfo"), NULL);
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+
+	zassert_true(buffer_size > 0, NULL);
+
+	/* Weakly verify some contents */
+	zassert_not_null(strstr(outbuffer, "Reset flags:"), NULL);
+	zassert_not_null(strstr(outbuffer, "Copy:"), NULL);
+	zassert_not_null(strstr(outbuffer, "Jumped:"), NULL);
+	zassert_not_null(strstr(outbuffer, "Recovery:"), NULL);
+	zassert_not_null(strstr(outbuffer, "Flags:"), NULL);
+}
+
+ZTEST_USER(console_cmd_sysinfo, test_no_args__sys_locked)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+	const char *outbuffer;
+	size_t buffer_size;
+
+	/* System unlocked */
+	shell_backend_dummy_clear_output(shell_zephyr);
+	system_is_locked_fake.return_val = false;
+
+	zassert_ok(shell_execute_cmd(shell_zephyr, "sysinfo"), NULL);
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+
+	zassert_true(buffer_size > 0, NULL);
+	zassert_not_null(strstr(outbuffer, "unlocked"), NULL);
+
+	/* System locked */
+	shell_backend_dummy_clear_output(shell_zephyr);
+	system_is_locked_fake.return_val = true;
+
+	zassert_true(buffer_size > 0, NULL);
+	zassert_ok(shell_execute_cmd(shell_zephyr, "sysinfo"), NULL);
+
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+	zassert_not_null(strstr(outbuffer, "locked"), NULL);
+
+	/* Verify system_is_locked in sysinfo cmd response remains */
+	shell_backend_dummy_clear_output(shell_zephyr);
+	system_is_locked_fake.return_val = false;
+
+	zassert_ok(shell_execute_cmd(shell_zephyr, "sysinfo"), NULL);
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+
+	zassert_true(buffer_size > 0, NULL);
+	zassert_not_null(strstr(outbuffer, "locked"), NULL);
+}
+
+static void console_cmd_sysinfo_before_after(void *test_data)
+{
+	ARG_UNUSED(test_data);
+
+	system_common_reset_state();
+}
+
+ZTEST_SUITE(console_cmd_sysinfo, drivers_predicate_post_main, NULL,
+	    console_cmd_sysinfo_before_after, console_cmd_sysinfo_before_after,
+	    NULL);
diff --git a/zephyr/test/drivers/default/src/console_cmd/tcpci_dump.c b/zephyr/test/drivers/default/src/console_cmd/tcpci_dump.c
new file mode 100644
index 0000000000..9652519cab
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/tcpci_dump.c
@@ -0,0 +1,46 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+#include "console.h"
+#include "ec_commands.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+ZTEST_USER(console_cmd_tcpci_dump, test_no_params)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "tcpci_dump");
+
+	zassert_equal(rv, EC_ERROR_PARAM_COUNT, "Expected %d, but got %d",
+		      EC_ERROR_PARAM_COUNT, rv);
+}
+
+ZTEST_USER(console_cmd_tcpci_dump, test_good_index)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "tcpci_dump 0"),
+		   "Failed index 0 print");
+}
+
+ZTEST_USER(console_cmd_tcpci_dump, test_bad_index)
+{
+	int rv = shell_execute_cmd(get_ec_shell(), "tcpci_dump 84");
+
+	zassert_equal(rv, EC_ERROR_INVAL, "Expected %d, but got %d",
+		      EC_ERROR_INVAL, rv);
+}
+
+static void console_cmd_tcpci_dump_begin(void *data)
+{
+	ARG_UNUSED(data);
+
+	/* Assume we have at least one TCPC */
+	zassume_true(board_get_charger_chip_count() > 0,
+		     "Insufficient TCPCs found");
+}
+
+ZTEST_SUITE(console_cmd_tcpci_dump, drivers_predicate_post_main, NULL,
+	    console_cmd_tcpci_dump_begin, NULL, NULL);
diff --git a/zephyr/test/drivers/src/console_cmd/usb_pd_console.c b/zephyr/test/drivers/default/src/console_cmd/usb_pd_console.c
index 4902591c67..21056056d4 100644
--- a/zephyr/test/drivers/src/console_cmd/usb_pd_console.c
+++ b/zephyr/test/drivers/default/src/console_cmd/usb_pd_console.c
@@ -1,15 +1,16 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include <zephyr/shell/shell.h>
-#include <ztest.h>
+#include <zephyr/ztest.h>
 
 #include "console.h"
 #include "ec_commands.h"
 #include "test/drivers/test_state.h"
 #include "test/drivers/utils.h"
+#include "usb_prl_sm.h"
 
 static void console_cmd_usb_pd_after(void *fixture)
 {
@@ -20,6 +21,10 @@ static void console_cmd_usb_pd_after(void *fixture)
 	k_sleep(K_SECONDS(1));
 	test_set_chipset_to_s0();
 	k_sleep(K_SECONDS(10));
+
+	/* Keep port used by testsuite enabled (default state) */
+	pd_comm_enable(0, 1);
+	pd_set_suspend(0, 0);
 }
 
 ZTEST_SUITE(console_cmd_usb_pd, drivers_predicate_post_main, NULL, NULL,
@@ -151,6 +156,24 @@ ZTEST_USER(console_cmd_usb_pd, test_enable)
 		      rv);
 }
 
+ZTEST_USER(console_cmd_usb_pd, test_suspend)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "pd 0 suspend");
+	zassert_equal(rv, EC_SUCCESS, "Expected %d, but got %d", EC_SUCCESS,
+		      rv);
+}
+
+ZTEST_USER(console_cmd_usb_pd, test_resume)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "pd 0 resume");
+	zassert_equal(rv, EC_SUCCESS, "Expected %d, but got %d", EC_SUCCESS,
+		      rv);
+}
+
 ZTEST_USER(console_cmd_usb_pd, test_hard)
 {
 	int rv;
@@ -253,3 +276,83 @@ ZTEST_USER(console_cmd_usb_pd, test_timer)
 	zassert_equal(rv, EC_SUCCESS, "Expected %d, but got %d", EC_SUCCESS,
 		      rv);
 }
+
+static void set_device_vdo(int port, enum tcpci_msg_type type)
+{
+	union tbt_mode_resp_device device_resp;
+	struct pd_discovery *dev_disc;
+
+	dev_disc = pd_get_am_discovery_and_notify_access(port, type);
+	dev_disc->svid_cnt = 1;
+	dev_disc->svids[0].svid = USB_VID_INTEL;
+	dev_disc->svids[0].discovery = PD_DISC_COMPLETE;
+	dev_disc->svids[0].mode_cnt = 1;
+	device_resp.tbt_alt_mode = TBT_ALTERNATE_MODE;
+	device_resp.tbt_adapter = TBT_ADAPTER_TBT3;
+	device_resp.intel_spec_b0 = VENDOR_SPECIFIC_NOT_SUPPORTED;
+	device_resp.vendor_spec_b0 = VENDOR_SPECIFIC_NOT_SUPPORTED;
+	device_resp.vendor_spec_b1 = VENDOR_SPECIFIC_NOT_SUPPORTED;
+	dev_disc->svids[0].mode_vdo[0] = device_resp.raw_value;
+}
+
+static void set_active_cable_type(int port, enum tcpci_msg_type type,
+				  enum idh_ptype ptype)
+{
+	struct pd_discovery *dev_disc;
+
+	dev_disc = pd_get_am_discovery_and_notify_access(port, type);
+	dev_disc->identity.idh.product_type = ptype;
+	prl_set_rev(port, type, PD_REV30);
+}
+
+ZTEST_USER(console_cmd_usb_pd, test_pe)
+{
+	int rv;
+
+	pd_set_identity_discovery(0, TCPCI_MSG_SOP, PD_DISC_COMPLETE);
+
+	rv = shell_execute_cmd(get_ec_shell(), "pe 0 dump");
+	zassert_ok(rv, "Expected %d, but got %d", EC_SUCCESS, rv);
+
+	set_device_vdo(0, TCPCI_MSG_SOP);
+	rv = shell_execute_cmd(get_ec_shell(), "pe 0 dump");
+	zassert_ok(rv, "Expected %d, but got %d", EC_SUCCESS, rv);
+
+	/* Handle error scenarios */
+	rv = shell_execute_cmd(get_ec_shell(), "pe 0");
+	zassert_equal(rv, EC_ERROR_PARAM_COUNT, "Expected %d, but got %d",
+		      EC_ERROR_PARAM_COUNT, rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "pe x dump");
+	zassert_equal(rv, EC_ERROR_PARAM2, "Expected %d, but got %d",
+		      EC_ERROR_PARAM2, rv);
+}
+
+ZTEST_USER(console_cmd_usb_pd, test_pdcable)
+{
+	int rv;
+
+	rv = shell_execute_cmd(get_ec_shell(), "pdcable 0");
+	zassert_ok(rv, "Expected %d, but got %d", EC_SUCCESS, rv);
+
+	set_device_vdo(0, TCPCI_MSG_SOP_PRIME);
+
+	/* Set active cable type IDH_PTYPE_ACABLE */
+	set_active_cable_type(0, TCPCI_MSG_SOP_PRIME, IDH_PTYPE_ACABLE);
+	rv = shell_execute_cmd(get_ec_shell(), "pdcable 0");
+	zassert_ok(rv, "Expected %d, but got %d", EC_SUCCESS, rv);
+
+	/* Set active cable type IDH_PTYPE_PCABLE */
+	set_active_cable_type(0, TCPCI_MSG_SOP_PRIME, IDH_PTYPE_PCABLE);
+	rv = shell_execute_cmd(get_ec_shell(), "pdcable 0");
+	zassert_ok(rv, "Expected %d, but got %d", EC_SUCCESS, rv);
+
+	/* Handle error scenarios */
+	rv = shell_execute_cmd(get_ec_shell(), "pdcable");
+	zassert_equal(rv, EC_ERROR_PARAM_COUNT, "Expected %d, but got %d",
+		      EC_ERROR_PARAM_COUNT, rv);
+
+	rv = shell_execute_cmd(get_ec_shell(), "pdcable t");
+	zassert_equal(rv, EC_ERROR_PARAM2, "Expected %d, but got %d",
+		      EC_ERROR_PARAM2, rv);
+}
diff --git a/zephyr/test/drivers/default/src/console_cmd/version.c b/zephyr/test/drivers/default/src/console_cmd/version.c
new file mode 100644
index 0000000000..932cc51449
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/version.c
@@ -0,0 +1,37 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/shell/shell_dummy.h>
+#include <zephyr/ztest.h>
+
+#include "console.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "system.h"
+
+ZTEST_USER(console_cmd_version, test_no_args)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+	const char *outbuffer;
+	size_t buffer_size;
+
+	shell_backend_dummy_clear_output(shell_zephyr);
+
+	zassert_ok(shell_execute_cmd(shell_zephyr, "version"), NULL);
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+
+	zassert_true(buffer_size > 0, NULL);
+
+	/* Weakly verify some contents */
+	zassert_not_null(strstr(outbuffer, "Chip:"), NULL);
+	zassert_not_null(strstr(outbuffer, "Board:"), NULL);
+	zassert_not_null(strstr(outbuffer, "RO:"), NULL);
+	zassert_not_null(strstr(outbuffer, "RW:"), NULL);
+	zassert_not_null(strstr(outbuffer, "Build:"), NULL);
+}
+
+ZTEST_SUITE(console_cmd_version, drivers_predicate_post_main, NULL, NULL, NULL,
+	    NULL);
diff --git a/zephyr/test/drivers/default/src/console_cmd/waitms.c b/zephyr/test/drivers/default/src/console_cmd/waitms.c
new file mode 100644
index 0000000000..0d03ee7414
--- /dev/null
+++ b/zephyr/test/drivers/default/src/console_cmd/waitms.c
@@ -0,0 +1,51 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <stdio.h>
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+#include "console.h"
+#include "timer.h"
+
+static void test_int(int ms)
+{
+	char cmd[32];
+	unsigned long measured;
+	timestamp_t start;
+	timestamp_t end;
+
+	sprintf(cmd, "waitms %d", ms);
+	start = get_time();
+	zassert_ok(shell_execute_cmd(get_ec_shell(), cmd),
+		   "Failed to execute 'waitms' command");
+	end = get_time();
+	measured = (end.val - start.val) / 1000;
+	zassert_equal(measured, ms, "'waitms %d' failed, took %ld ms", ms,
+		      measured);
+}
+
+ZTEST_SUITE(console_cmd_waitms, NULL, NULL, NULL, NULL, NULL);
+
+ZTEST_USER(console_cmd_waitms, test_waitms)
+{
+	/*
+	 * Test across three orders of magnitude. Beyond ~3s the watchdog will
+	 * trigger so don't need to bother testing 10s of seconds or greater.
+	 */
+	test_int(0);
+	test_int(5);
+	test_int(75);
+	test_int(250);
+	test_int(1000);
+
+	/* A plain string should fail. */
+	zassert_true(shell_execute_cmd(get_ec_shell(), "waitms string"), NULL);
+
+	/* Floats and negative ints should fail. */
+	zassert_true(shell_execute_cmd(get_ec_shell(), "waitms 123.456"), NULL);
+	zassert_true(shell_execute_cmd(get_ec_shell(), "waitms -67.3"), NULL);
+	zassert_true(shell_execute_cmd(get_ec_shell(), "waitms -7"), NULL);
+}
diff --git a/zephyr/test/drivers/src/cros_cbi.c b/zephyr/test/drivers/default/src/cros_cbi.c
index d0afdaecdb..e92765cb52 100644
--- a/zephyr/test/drivers/src/cros_cbi.c
+++ b/zephyr/test/drivers/default/src/cros_cbi.c
@@ -1,10 +1,10 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include <zephyr/device.h>
-#include <ztest.h>
+#include <zephyr/ztest.h>
 
 #include "cros_cbi.h"
 #include "test/drivers/test_state.h"
diff --git a/zephyr/test/drivers/default/src/espi.c b/zephyr/test/drivers/default/src/espi.c
new file mode 100644
index 0000000000..9843471ae7
--- /dev/null
+++ b/zephyr/test/drivers/default/src/espi.c
@@ -0,0 +1,326 @@
+/* Copyright 2021 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <string.h>
+#include <zephyr/fff.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+#include "ec_commands.h"
+#include "gpio.h"
+#include "host_command.h"
+#include "system.h"
+#include "test/drivers/test_mocks.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#define PORT 0
+
+#define AC_OK_OD_GPIO_NAME "acok_od"
+
+static void espi_before(void *state)
+{
+	ARG_UNUSED(state);
+	RESET_FAKE(system_is_locked);
+}
+
+static void espi_after(void *state)
+{
+	ARG_UNUSED(state);
+	RESET_FAKE(system_is_locked);
+}
+
+ZTEST_USER(espi, test_host_command_get_protocol_info)
+{
+	struct ec_response_get_protocol_info response;
+	struct host_cmd_handler_args args = BUILD_HOST_COMMAND_RESPONSE(
+		EC_CMD_GET_PROTOCOL_INFO, 0, response);
+
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_ok(args.result, NULL);
+	zassert_equal(args.response_size, sizeof(response), NULL);
+	zassert_equal(response.protocol_versions, BIT(3), NULL);
+	zassert_equal(response.max_request_packet_size, EC_LPC_HOST_PACKET_SIZE,
+		      NULL);
+	zassert_equal(response.max_response_packet_size,
+		      EC_LPC_HOST_PACKET_SIZE, NULL);
+	zassert_equal(response.flags, 0, NULL);
+}
+
+ZTEST_USER(espi, test_host_command_usb_pd_power_info)
+{
+	/* Only test we've enabled the command */
+	struct ec_response_usb_pd_power_info response;
+	struct ec_params_usb_pd_power_info params = { .port = PORT };
+	struct host_cmd_handler_args args = BUILD_HOST_COMMAND(
+		EC_CMD_USB_PD_POWER_INFO, 0, response, params);
+
+	args.params = &params;
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_ok(args.result, NULL);
+	zassert_equal(args.response_size, sizeof(response), NULL);
+}
+
+ZTEST_USER(espi, test_host_command_typec_status)
+{
+	/* Only test we've enabled the command */
+	struct ec_params_typec_status params = { .port = PORT };
+	struct ec_response_typec_status response;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_TYPEC_STATUS, 0, response, params);
+
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_ok(args.result, NULL);
+	zassert_equal(args.response_size, sizeof(response), NULL);
+}
+
+ZTEST_USER(espi, test_host_command_usb_pd_get_amode)
+{
+	/* Only test we've enabled the command */
+	struct ec_params_usb_pd_get_mode_request params = {
+		.port = PORT,
+		.svid_idx = 0,
+	};
+	struct ec_params_usb_pd_get_mode_response response;
+	struct host_cmd_handler_args args = BUILD_HOST_COMMAND(
+		EC_CMD_USB_PD_GET_AMODE, 0, response, params);
+
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_ok(args.result, NULL);
+	/* Note: with no SVIDs the response size is the size of the svid field.
+	 * See the usb alt mode test for verifying larger struct sizes
+	 */
+	zassert_equal(args.response_size, sizeof(response.svid), NULL);
+}
+
+ZTEST_USER(espi, test_host_command_gpio_get_v0)
+{
+	struct ec_params_gpio_get p = {
+		/* Checking for AC enabled */
+		.name = AC_OK_OD_GPIO_NAME,
+	};
+	struct ec_response_gpio_get response;
+
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_GPIO_GET, 0, response, p);
+
+	set_ac_enabled(true);
+
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_ok(args.result, NULL);
+	zassert_equal(args.response_size, sizeof(response), NULL);
+	zassert_true(response.val, NULL);
+
+	set_ac_enabled(false);
+
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_ok(args.result, NULL);
+	zassert_equal(args.response_size, sizeof(response), NULL);
+	zassert_false(response.val, NULL);
+}
+
+ZTEST_USER(espi, test_host_command_gpio_get_v1_get_by_name)
+{
+	struct ec_params_gpio_get_v1 p = {
+		.subcmd = EC_GPIO_GET_BY_NAME,
+		/* Checking for AC enabled */
+		.get_value_by_name = {
+			   AC_OK_OD_GPIO_NAME,
+		},
+	};
+	struct ec_response_gpio_get_v1 response;
+
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_GPIO_GET, 1, response, p);
+
+	set_ac_enabled(true);
+
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_ok(args.result, NULL);
+	zassert_equal(args.response_size, sizeof(response.get_value_by_name),
+		      NULL);
+	zassert_true(response.get_info.val, NULL);
+
+	set_ac_enabled(false);
+
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_ok(args.result, NULL);
+	zassert_equal(args.response_size, sizeof(response.get_value_by_name),
+		      NULL);
+	zassert_false(response.get_info.val, NULL);
+}
+
+ZTEST_USER(espi, test_host_command_gpio_get_v1_get_count)
+{
+	struct ec_params_gpio_get_v1 p = {
+		.subcmd = EC_GPIO_GET_COUNT,
+	};
+	struct ec_response_gpio_get_v1 response;
+
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_GPIO_GET, 1, response, p);
+
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_ok(args.result, NULL);
+	zassert_equal(args.response_size, sizeof(response.get_count), NULL);
+	zassert_equal(response.get_count.val, GPIO_COUNT, NULL);
+}
+
+ZTEST_USER(espi, test_host_command_gpio_get_v1_get_info)
+{
+	const enum gpio_signal signal = GPIO_SIGNAL(DT_NODELABEL(gpio_acok_od));
+	struct ec_params_gpio_get_v1 p = {
+		.subcmd = EC_GPIO_GET_INFO,
+		.get_info = {
+			.index = signal,
+		},
+	};
+	struct ec_response_gpio_get_v1 response;
+
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_GPIO_GET, 1, response, p);
+
+	set_ac_enabled(true);
+
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_ok(args.result, NULL);
+	zassert_equal(args.response_size, sizeof(response), NULL);
+	zassert_ok(strcmp(response.get_info.name, AC_OK_OD_GPIO_NAME), NULL);
+	zassert_true(response.get_info.val, NULL);
+
+	set_ac_enabled(false);
+
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_ok(args.result, NULL);
+	zassert_equal(args.response_size, sizeof(response), NULL);
+	zassert_ok(strcmp(response.get_info.name, AC_OK_OD_GPIO_NAME), NULL);
+	zassert_false(response.get_info.val, NULL);
+}
+
+ZTEST_USER(espi, test_host_command_gpio_set)
+{
+	struct nothing {
+		int place_holder;
+	};
+	const struct gpio_dt_spec *gp = GPIO_DT_FROM_NODELABEL(gpio_test);
+	struct ec_params_gpio_set p = {
+		.name = "test",
+		.val = 0,
+	};
+
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_PARAMS(EC_CMD_GPIO_SET, 0, p);
+
+	/* Force value to 1 to see change */
+	zassume_ok(gpio_pin_set_dt(gp, 1), NULL);
+
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_equal(gpio_pin_get_dt(gp), p.val, NULL);
+
+	p.val = 1;
+
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_equal(gpio_pin_get_dt(gp), p.val, NULL);
+}
+
+ZTEST(espi, test_hc_gpio_get_v0_invalid_name)
+{
+	struct ec_response_gpio_get response;
+	struct ec_params_gpio_get params = { .name = "INVALID_GPIO_NAME" };
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_GPIO_GET, 0, response, params);
+
+	zassert_equal(EC_RES_ERROR, host_command_process(&args), NULL);
+}
+
+ZTEST(espi, test_hc_gpio_get_v1_get_by_name_invalid_name)
+{
+	struct ec_response_gpio_get_v1 response;
+	struct ec_params_gpio_get_v1 params = {
+		.subcmd = EC_GPIO_GET_BY_NAME,
+		.get_value_by_name.name = "INVALID_GPIO_NAME",
+	};
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_GPIO_GET, 1, response, params);
+
+	zassert_equal(EC_RES_ERROR, host_command_process(&args), NULL);
+}
+
+ZTEST(espi, test_hc_gpio_get_v1_get_info_invalid_index)
+{
+	struct ec_response_gpio_get_v1 response;
+	struct ec_params_gpio_get_v1 params = {
+		.subcmd = EC_GPIO_GET_INFO,
+		.get_info.index = GPIO_COUNT,
+	};
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_GPIO_GET, 1, response, params);
+
+	zassert_equal(EC_RES_ERROR, host_command_process(&args), NULL);
+}
+
+ZTEST(espi, test_hc_gpio_get_v1_invalid_subcmd)
+{
+	struct ec_response_gpio_get_v1 response;
+	struct ec_params_gpio_get_v1 params = {
+		.subcmd = EC_CMD_GPIO_GET,
+	};
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_GPIO_GET, 1, response, params);
+
+	zassert_equal(EC_RES_INVALID_PARAM, host_command_process(&args), NULL);
+}
+
+/* EC_CMD_GET_FEATURES */
+ZTEST_USER(espi, test_host_command_ec_cmd_get_features)
+{
+	struct ec_response_get_features response;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_RESPONSE(EC_CMD_GET_FEATURES, 0, response);
+
+	int rv = host_command_process(&args);
+
+	zassert_equal(rv, EC_RES_SUCCESS, "Expected %d, but got %d",
+		      EC_RES_SUCCESS, rv);
+
+	/* Check features returned */
+	uint32_t feature_mask;
+
+	feature_mask = EC_FEATURE_MASK_0(EC_FEATURE_FLASH);
+	feature_mask |= EC_FEATURE_MASK_0(EC_FEATURE_MOTION_SENSE);
+	feature_mask |= EC_FEATURE_MASK_0(EC_FEATURE_KEYB);
+	zassert_true((response.flags[0] & feature_mask),
+		     "Known features were not returned.");
+	feature_mask = EC_FEATURE_MASK_1(EC_FEATURE_UNIFIED_WAKE_MASKS);
+	feature_mask |= EC_FEATURE_MASK_1(EC_FEATURE_HOST_EVENT64);
+	feature_mask |= EC_FEATURE_MASK_1(EC_FEATURE_EXEC_IN_RAM);
+	zassert_true((response.flags[1] & feature_mask),
+		     "Known features were not returned.");
+}
+
+ZTEST(espi, test_hc_gpio_set_system_is_locked)
+{
+	struct ec_params_gpio_set params;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_PARAMS(EC_CMD_GPIO_SET, 0, params);
+
+	system_is_locked_fake.return_val = 1;
+	zassert_equal(EC_RES_ACCESS_DENIED, host_command_process(&args), NULL);
+}
+
+ZTEST(espi, test_hc_gpio_set_invalid_gpio_name)
+{
+	struct ec_params_gpio_set params = {
+		.name = "",
+		.val = 0,
+	};
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_PARAMS(EC_CMD_GPIO_SET, 0, params);
+
+	zassert_equal(EC_RES_ERROR, host_command_process(&args), NULL);
+}
+
+ZTEST_SUITE(espi, drivers_predicate_post_main, NULL, espi_before, espi_after,
+	    NULL);
diff --git a/zephyr/test/drivers/default/src/flash.c b/zephyr/test/drivers/default/src/flash.c
new file mode 100644
index 0000000000..b49d21b997
--- /dev/null
+++ b/zephyr/test/drivers/default/src/flash.c
@@ -0,0 +1,444 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+#include "ec_commands.h"
+#include "emul/emul_flash.h"
+#include "flash.h"
+#include "host_command.h"
+#include "system.h"
+#include "test/drivers/test_state.h"
+
+#define WP_L_GPIO_PATH DT_PATH(named_gpios, wp_l)
+
+static int gpio_wp_l_set(int value)
+{
+	const struct device *wp_l_gpio_dev =
+		DEVICE_DT_GET(DT_GPIO_CTLR(WP_L_GPIO_PATH, gpios));
+
+	return gpio_emul_input_set(wp_l_gpio_dev,
+				   DT_GPIO_PIN(WP_L_GPIO_PATH, gpios), value);
+}
+
+ZTEST_USER(flash, test_hostcmd_flash_protect_wp_asserted)
+{
+	struct ec_response_flash_protect response;
+	struct ec_params_flash_protect params = {
+		.mask = 0,
+		.flags = 0,
+	};
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_FLASH_PROTECT, 0, response, params);
+	/* The original flags not 0 as GPIO WP_L asserted */
+	uint32_t expected_flags = EC_FLASH_PROTECT_GPIO_ASSERTED;
+
+	/* Get the flash protect */
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_equal(response.flags, expected_flags, "response.flags = %d",
+		      response.flags);
+
+	/* Enable RO_AT_BOOT */
+	params.mask = EC_FLASH_PROTECT_RO_AT_BOOT;
+	params.flags = EC_FLASH_PROTECT_RO_AT_BOOT;
+	expected_flags |= EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW;
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_equal(response.flags, expected_flags, "response.flags = %d",
+		      response.flags);
+
+	/* Disable RO_AT_BOOT; should change nothing as GPIO WP_L is asserted */
+	params.mask = EC_FLASH_PROTECT_RO_AT_BOOT;
+	params.flags = 0;
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_equal(response.flags, expected_flags, "response.flags = %d",
+		      response.flags);
+
+	/* Enable ALL_NOW */
+	params.mask = EC_FLASH_PROTECT_ALL_NOW;
+	params.flags = EC_FLASH_PROTECT_ALL_NOW;
+	expected_flags |= EC_FLASH_PROTECT_ALL_NOW;
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_equal(response.flags, expected_flags, "response.flags = %d",
+		      response.flags);
+
+	/* Disable ALL_NOW; should change nothing as GPIO WP_L is asserted */
+	params.mask = EC_FLASH_PROTECT_ALL_NOW;
+	params.flags = 0;
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_equal(response.flags, expected_flags, "response.flags = %d",
+		      response.flags);
+
+	/* Disable RO_AT_BOOT; should change nothing as GPIO WP_L is asserted */
+	params.mask = EC_FLASH_PROTECT_RO_AT_BOOT;
+	params.flags = 0;
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_equal(response.flags, expected_flags, "response.flags = %d",
+		      response.flags);
+}
+
+ZTEST_USER(flash, test_hostcmd_flash_protect_wp_deasserted)
+{
+	struct ec_response_flash_protect response;
+	struct ec_params_flash_protect params = {
+		.mask = 0,
+		.flags = 0,
+	};
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_FLASH_PROTECT, 0, response, params);
+	/* The original flags 0 as GPIO WP_L deasserted */
+	uint32_t expected_flags = 0;
+
+	zassert_ok(gpio_wp_l_set(1), NULL);
+
+	/* Get the flash protect */
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_equal(response.flags, expected_flags, "response.flags = %d",
+		      response.flags);
+
+	/* Enable RO_AT_BOOT */
+	params.mask = EC_FLASH_PROTECT_RO_AT_BOOT;
+	params.flags = EC_FLASH_PROTECT_RO_AT_BOOT;
+	expected_flags |= EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW;
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_equal(response.flags, expected_flags, "response.flags = %d",
+		      response.flags);
+
+	/* Disable RO_AT_BOOT */
+	params.mask = EC_FLASH_PROTECT_RO_AT_BOOT;
+	params.flags = 0;
+	expected_flags &=
+		~(EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW);
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_equal(response.flags, expected_flags, "response.flags = %d",
+		      response.flags);
+
+	/* Enable RO_AT_BOOT */
+	params.mask = EC_FLASH_PROTECT_RO_AT_BOOT;
+	params.flags = EC_FLASH_PROTECT_RO_AT_BOOT;
+	expected_flags |= EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW;
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_equal(response.flags, expected_flags, "response.flags = %d",
+		      response.flags);
+
+	/* Enable ALL_NOW; should change nothing as GPIO WP_L is deasserted */
+	params.mask = EC_FLASH_PROTECT_ALL_NOW;
+	params.flags = EC_FLASH_PROTECT_ALL_NOW;
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_equal(response.flags, expected_flags, "response.flags = %d",
+		      response.flags);
+}
+
+#define TEST_BUF_SIZE 0x100
+
+ZTEST_USER(flash, test_hostcmd_flash_write_and_erase)
+{
+	uint8_t in_buf[TEST_BUF_SIZE];
+	uint8_t out_buf[sizeof(struct ec_params_flash_write) + TEST_BUF_SIZE];
+
+	struct ec_params_flash_read read_params = {
+		.offset = 0x10000,
+		.size = TEST_BUF_SIZE,
+	};
+	struct host_cmd_handler_args read_args =
+		BUILD_HOST_COMMAND(EC_CMD_FLASH_READ, 0, in_buf, read_params);
+
+	struct ec_params_flash_erase erase_params = {
+		.offset = 0x10000,
+		.size = 0x10000,
+	};
+	struct host_cmd_handler_args erase_args =
+		BUILD_HOST_COMMAND_PARAMS(EC_CMD_FLASH_ERASE, 0, erase_params);
+
+	/* The write host command structs need to be filled run-time */
+	struct ec_params_flash_write *write_params =
+		(struct ec_params_flash_write *)out_buf;
+	struct host_cmd_handler_args write_args =
+		BUILD_HOST_COMMAND_SIMPLE(EC_CMD_FLASH_WRITE, 0);
+
+	write_params->offset = 0x10000;
+	write_params->size = TEST_BUF_SIZE;
+	write_args.params = write_params;
+	write_args.params_size = sizeof(*write_params) + TEST_BUF_SIZE;
+
+	/* Flash write to all 0xec */
+	memset(write_params + 1, 0xec, TEST_BUF_SIZE);
+	zassert_ok(host_command_process(&write_args), NULL);
+
+	/* Flash read and compare the readback data */
+	zassert_ok(host_command_process(&read_args), NULL);
+	zassert_equal(read_args.response_size, TEST_BUF_SIZE, NULL);
+	zassert_equal(in_buf[0], 0xec, "readback data not expected: 0x%x",
+		      in_buf[0]);
+	zassert_equal(in_buf[TEST_BUF_SIZE - 1], 0xec,
+		      "readback data not expected: 0x%x", in_buf[0]);
+
+	/* Flash erase */
+	zassert_ok(host_command_process(&erase_args), NULL);
+
+	/* Flash read and compare the readback data */
+	zassert_ok(host_command_process(&read_args), NULL);
+	zassert_equal(in_buf[0], 0xff, "readback data not expected: 0x%x",
+		      in_buf[0]);
+	zassert_equal(in_buf[TEST_BUF_SIZE - 1], 0xff,
+		      "readback data not expected: 0x%x", in_buf[0]);
+}
+
+#define EC_FLASH_REGION_START \
+	MIN(CONFIG_EC_PROTECTED_STORAGE_OFF, CONFIG_EC_WRITABLE_STORAGE_OFF)
+
+static void test_region_info(uint32_t region, uint32_t expected_offset,
+			     uint32_t expected_size)
+{
+	struct ec_response_flash_region_info response;
+	struct ec_params_flash_region_info params = {
+		.region = region,
+	};
+	struct host_cmd_handler_args args = BUILD_HOST_COMMAND(
+		EC_CMD_FLASH_REGION_INFO, 1, response, params);
+
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_equal(response.offset, expected_offset, NULL);
+	zassert_equal(response.size, expected_size, NULL);
+}
+
+ZTEST_USER(flash, test_hostcmd_flash_region_info_ro)
+{
+	test_region_info(EC_FLASH_REGION_RO,
+			 CONFIG_EC_PROTECTED_STORAGE_OFF +
+				 CONFIG_RO_STORAGE_OFF - EC_FLASH_REGION_START,
+			 EC_FLASH_REGION_RO_SIZE);
+}
+
+ZTEST_USER(flash, test_hostcmd_flash_region_info_active)
+{
+	test_region_info(EC_FLASH_REGION_ACTIVE,
+			 flash_get_rw_offset(system_get_active_copy()) -
+				 EC_FLASH_REGION_START,
+			 CONFIG_EC_WRITABLE_STORAGE_SIZE);
+}
+
+ZTEST_USER(flash, test_hostcmd_flash_region_info_active_wp_ro)
+{
+	test_region_info(EC_FLASH_REGION_WP_RO,
+			 CONFIG_WP_STORAGE_OFF - EC_FLASH_REGION_START,
+			 CONFIG_WP_STORAGE_SIZE);
+}
+
+ZTEST_USER(flash, test_hostcmd_flash_region_info_active_update)
+{
+	test_region_info(EC_FLASH_REGION_UPDATE,
+			 flash_get_rw_offset(system_get_update_copy()) -
+				 EC_FLASH_REGION_START,
+			 CONFIG_EC_WRITABLE_STORAGE_SIZE);
+}
+
+ZTEST_USER(flash, test_hostcmd_flash_region_info_active_invalid)
+{
+	struct ec_response_flash_region_info response;
+	struct ec_params_flash_region_info params = {
+		/* Get an invalid region */
+		.region = 10,
+	};
+	struct host_cmd_handler_args args = BUILD_HOST_COMMAND(
+		EC_CMD_FLASH_REGION_INFO, 1, response, params);
+
+	zassert_equal(host_command_process(&args), EC_RES_INVALID_PARAM, NULL);
+}
+
+ZTEST_USER(flash, test_hostcmd_flash_info)
+{
+	struct ec_response_flash_info_1 response;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_RESPONSE(EC_CMD_FLASH_INFO, 1, response);
+
+	/* Get the flash info. */
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_equal(response.flash_size,
+		      CONFIG_FLASH_SIZE_BYTES - EC_FLASH_REGION_START,
+		      "response.flash_size = %d", response.flash_size);
+	zassert_equal(response.flags, 0, "response.flags = %d", response.flags);
+	zassert_equal(response.write_block_size, CONFIG_FLASH_WRITE_SIZE,
+		      "response.write_block_size = %d",
+		      response.write_block_size);
+	zassert_equal(response.erase_block_size, CONFIG_FLASH_ERASE_SIZE,
+		      "response.erase_block_size = %d",
+		      response.erase_block_size);
+	zassert_equal(response.protect_block_size, CONFIG_FLASH_BANK_SIZE,
+		      "response.protect_block_size = %d",
+		      response.protect_block_size);
+	zassert_equal(
+		response.write_ideal_size,
+		(args.response_max - sizeof(struct ec_params_flash_write)) &
+			~(CONFIG_FLASH_WRITE_SIZE - 1),
+		"response.write_ideal_size = %d", response.write_ideal_size);
+}
+
+ZTEST_USER(flash, test_console_cmd_flashwp__invalid)
+{
+	/* Command requires a 2nd CLI arg */
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "flashwp"), NULL);
+}
+
+ZTEST_USER(flash, test_console_cmd_flashwp__now)
+{
+	uint32_t current;
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "flashwp true"), NULL);
+
+	current = crec_flash_get_protect();
+	zassert_true(EC_FLASH_PROTECT_GPIO_ASSERTED & current, "current = %08x",
+		     current);
+	zassert_true(EC_FLASH_PROTECT_RO_AT_BOOT & current, "current = %08x",
+		     current);
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "flashwp now"), NULL);
+
+	current = crec_flash_get_protect();
+	zassert_true(current & EC_FLASH_PROTECT_ALL_NOW, "current = %08x",
+		     current);
+}
+
+ZTEST_USER(flash, test_console_cmd_flashwp__all)
+{
+	uint32_t current;
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "flashwp true"), NULL);
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "flashwp all"), NULL);
+
+	current = crec_flash_get_protect();
+	zassert_true(EC_FLASH_PROTECT_ALL_NOW & current, "current = %08x",
+		     current);
+}
+
+ZTEST_USER(flash, test_console_cmd_flashwp__bool_false)
+{
+	uint32_t current;
+
+	/* Set RO_AT_BOOT and verify */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "flashwp true"), NULL);
+
+	current = crec_flash_get_protect();
+	zassert_true(current & EC_FLASH_PROTECT_RO_AT_BOOT, "current = %08x",
+		     current);
+
+	gpio_wp_l_set(1);
+
+	/* Now clear it */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "flashwp false"), NULL);
+
+	current = crec_flash_get_protect();
+	zassert_false(current & EC_FLASH_PROTECT_RO_AT_BOOT, "current = %08x",
+		      current);
+}
+
+ZTEST_USER(flash, test_console_cmd_flashwp__bool_true)
+{
+	uint32_t current;
+
+	gpio_wp_l_set(1);
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "flashwp true"), NULL);
+
+	current = crec_flash_get_protect();
+	zassert_equal(EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW,
+		      current, "current = %08x", current);
+}
+
+ZTEST_USER(flash, test_console_cmd_flashwp__bad_param)
+{
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "flashwp xyz"), NULL);
+}
+
+/**
+ * @brief Prepare a region of flash for the test_crec_flash_is_erased* tests
+ *
+ * @param offset Offset to write bytes at.
+ * @param size Number of bytes to erase.
+ * @param make_write If true, write an arbitrary byte after erase so the region
+ *                   is no longer fully erased.
+ */
+static void setup_flash_region_helper(uint32_t offset, uint32_t size,
+				      bool make_write)
+{
+	struct ec_params_flash_erase erase_params = {
+		.offset = offset,
+		.size = size,
+	};
+	struct host_cmd_handler_args erase_args =
+		BUILD_HOST_COMMAND_PARAMS(EC_CMD_FLASH_ERASE, 0, erase_params);
+
+	zassume_ok(host_command_process(&erase_args), NULL);
+
+	if (make_write) {
+		/* Sized for flash_write header plus one byte of data */
+		uint8_t out_buf[sizeof(struct ec_params_flash_write) +
+				sizeof(uint8_t)];
+
+		struct ec_params_flash_write *write_params =
+			(struct ec_params_flash_write *)out_buf;
+		struct host_cmd_handler_args write_args =
+			BUILD_HOST_COMMAND_SIMPLE(EC_CMD_FLASH_WRITE, 0);
+
+		write_params->offset = offset;
+		write_params->size = 1;
+		write_args.params = write_params;
+		write_args.params_size = sizeof(out_buf);
+
+		/* Write one byte at start of region */
+		out_buf[sizeof(*write_params)] = 0xec;
+
+		zassume_ok(host_command_process(&write_args), NULL);
+	}
+}
+
+ZTEST_USER(flash, test_crec_flash_is_erased__happy)
+{
+	uint32_t offset = 0x10000;
+
+	setup_flash_region_helper(offset, TEST_BUF_SIZE, false);
+
+	zassert_true(crec_flash_is_erased(offset, TEST_BUF_SIZE), NULL);
+}
+
+ZTEST_USER(flash, test_crec_flash_is_erased__not_erased)
+{
+	uint32_t offset = 0x10000;
+
+	setup_flash_region_helper(offset, TEST_BUF_SIZE, true);
+
+	zassert_true(!crec_flash_is_erased(offset, TEST_BUF_SIZE), NULL);
+}
+
+static void flash_reset(void)
+{
+	/* Set the GPIO WP_L to default */
+	gpio_wp_l_set(0);
+
+	/* Reset the protection flags */
+	cros_flash_emul_protect_reset();
+}
+
+static void flash_before(void *data)
+{
+	ARG_UNUSED(data);
+	flash_reset();
+}
+
+static void flash_after(void *data)
+{
+	ARG_UNUSED(data);
+	flash_reset();
+
+	/* The test modifies this bank. Erase it in case of failure. */
+	crec_flash_erase(0x10000, 0x10000);
+}
+
+ZTEST_SUITE(flash, drivers_predicate_post_main, NULL, flash_before, flash_after,
+	    NULL);
diff --git a/zephyr/test/drivers/src/gpio.c b/zephyr/test/drivers/default/src/gpio.c
index e49222f08f..acfa0de26e 100644
--- a/zephyr/test/drivers/src/gpio.c
+++ b/zephyr/test/drivers/default/src/gpio.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,8 +12,8 @@
 
 #include <zephyr/drivers/gpio/gpio_emul.h>
 #include <zephyr/logging/log.h>
-#include <zephyr/zephyr.h>
-#include <ztest.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
 
 #include "common.h"
 #include "ec_tasks.h"
@@ -116,8 +116,8 @@ ZTEST(gpio, test_convert_to_zephyr_flags)
  */
 ZTEST(gpio, test_signal_is_gpio)
 {
-	zassert_true(signal_is_gpio(
-		GPIO_SIGNAL(DT_NODELABEL(gpio_test))), "Expected true");
+	zassert_true(signal_is_gpio(GPIO_SIGNAL(DT_NODELABEL(gpio_test))),
+		     "Expected true");
 }
 
 /**
@@ -301,7 +301,6 @@ ZTEST(gpio, test_gpio_get_default_flags)
 	zassert_equal(flags, GPIO_OUTPUT, "Flags set 0x%x", flags);
 }
 
-
 /**
  * @brief TestPurpose: Verify GPIO no-auto-init.
  *
@@ -319,16 +318,13 @@ ZTEST(gpio, test_gpio_no_auto_init)
 	gpio_flags_t flags;
 
 	flags = gpio_helper_get_flags(signal);
-	zassert_equal(0, flags,
-		      "Expected 0x%08x, returned 0x%08X",
-		      0, flags);
+	zassert_equal(0, flags, "Expected 0x%08x, returned 0x%08X", 0, flags);
 
 	/* Configure pin. */
 	gpio_pin_configure_dt(gp, GPIO_INPUT | GPIO_OUTPUT);
 	flags = gpio_helper_get_flags(signal);
-	zassert_equal(flags,
-		      (GPIO_ACTIVE_LOW | GPIO_OUTPUT | GPIO_INPUT),
-		       "Flags set 0x%x", flags);
+	zassert_equal(flags, (GPIO_ACTIVE_LOW | GPIO_OUTPUT | GPIO_INPUT),
+		      "Flags set 0x%x", flags);
 }
 
 /**
diff --git a/zephyr/test/drivers/default/src/i2c.c b/zephyr/test/drivers/default/src/i2c.c
new file mode 100644
index 0000000000..caced4aedf
--- /dev/null
+++ b/zephyr/test/drivers/default/src/i2c.c
@@ -0,0 +1,145 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+#include "ec_commands.h"
+#include "host_command.h"
+#include "i2c.h"
+#include "test/drivers/test_state.h"
+
+ZTEST_USER(i2c, test_i2c_set_speed_success)
+{
+	struct ec_response_i2c_control response;
+	struct ec_params_i2c_control get_params = {
+		.port = I2C_PORT_USB_C0,
+		.cmd = EC_I2C_CONTROL_GET_SPEED,
+	};
+	struct host_cmd_handler_args get_args =
+		BUILD_HOST_COMMAND(EC_CMD_I2C_CONTROL, 0, response, get_params);
+	struct ec_params_i2c_control set_params = {
+		.port = I2C_PORT_USB_C0,
+		.cmd = EC_I2C_CONTROL_SET_SPEED,
+	};
+	struct host_cmd_handler_args set_args =
+		BUILD_HOST_COMMAND(EC_CMD_I2C_CONTROL, 0, response, set_params);
+
+	/* Get the speed: 100. */
+	zassert_ok(host_command_process(&get_args), NULL);
+	zassert_ok(get_args.result, NULL);
+	zassert_equal(get_args.response_size, sizeof(response), NULL);
+	zassert_equal(response.cmd_response.speed_khz, 100,
+		      "response.cmd_response.speed_khz = %d",
+		      response.cmd_response.speed_khz);
+
+	/* Set the speed to 400. */
+	set_params.cmd_params.speed_khz = 400;
+	zassert_ok(host_command_process(&set_args), NULL);
+	zassert_ok(set_args.result, NULL);
+	zassert_equal(set_args.response_size, sizeof(response), NULL);
+	zassert_equal(response.cmd_response.speed_khz, 100,
+		      "response.cmd_response.speed_khz = %d",
+		      response.cmd_response.speed_khz);
+
+	/* Get the speed to verify. */
+	zassert_ok(host_command_process(&get_args), NULL);
+	zassert_ok(get_args.result, NULL);
+	zassert_equal(get_args.response_size, sizeof(response), NULL);
+	zassert_equal(response.cmd_response.speed_khz, 400,
+		      "response.cmd_response.speed_khz = %d",
+		      response.cmd_response.speed_khz);
+
+	/* Set the speed back to 100. */
+	set_params.cmd_params.speed_khz = 100;
+	zassert_ok(host_command_process(&set_args), NULL);
+	zassert_ok(set_args.result, NULL);
+	zassert_equal(set_args.response_size, sizeof(response), NULL);
+	zassert_equal(response.cmd_response.speed_khz, 400,
+		      "response.cmd_response.speed_khz = %d",
+		      response.cmd_response.speed_khz);
+}
+
+ZTEST_USER(i2c, test_i2c_set_speed_not_dynamic)
+{
+	struct ec_response_i2c_control response;
+	struct ec_params_i2c_control set_params = {
+		.port = I2C_PORT_POWER,
+		.cmd = EC_I2C_CONTROL_SET_SPEED,
+		.cmd_params.speed_khz = 400,
+	};
+	struct host_cmd_handler_args set_args =
+		BUILD_HOST_COMMAND(EC_CMD_I2C_CONTROL, 0, response, set_params);
+
+	/* Set the speed to 400 on a bus which doesn't support dynamic-speed. */
+	zassert_equal(EC_RES_ERROR, host_command_process(&set_args), NULL);
+}
+
+ZTEST_USER(i2c, test_i2c_control_wrong_port)
+{
+	struct ec_response_i2c_control response;
+	struct ec_params_i2c_control get_params = {
+		.port = 10,
+		.cmd = EC_I2C_CONTROL_GET_SPEED,
+	};
+	struct host_cmd_handler_args get_args =
+		BUILD_HOST_COMMAND(EC_CMD_I2C_CONTROL, 0, response, get_params);
+
+	/* Set the .port=10, which is not defined. */
+	zassert_equal(EC_RES_INVALID_PARAM, host_command_process(&get_args),
+		      NULL);
+}
+
+ZTEST_USER(i2c, test_i2c_control_wrong_cmd)
+{
+	struct ec_response_i2c_control response;
+	struct ec_params_i2c_control params = {
+		.port = I2C_PORT_USB_C0,
+		.cmd = 10,
+	};
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_I2C_CONTROL, 0, response, params);
+
+	/* Call the .cmd=10, which is not defined. */
+	zassert_equal(EC_RES_INVALID_COMMAND, host_command_process(&args),
+		      NULL);
+}
+
+ZTEST_USER(i2c, test_i2c_set_speed_wrong_freq)
+{
+	struct ec_response_i2c_control response;
+	struct ec_params_i2c_control set_params = {
+		.port = I2C_PORT_USB_C0,
+		.cmd = EC_I2C_CONTROL_SET_SPEED,
+		.cmd_params.speed_khz = 123,
+	};
+	struct host_cmd_handler_args set_args =
+		BUILD_HOST_COMMAND(EC_CMD_I2C_CONTROL, 0, response, set_params);
+
+	/* Set the speed to 123 KHz (an invalid speed). */
+	zassert_equal(EC_RES_INVALID_PARAM, host_command_process(&set_args),
+		      NULL);
+}
+
+static void i2c_freq_reset(void)
+{
+	/* The test modifies this port. Reset it to the DTS defined. */
+	zassert_ok(i2c_set_freq(I2C_PORT_USB_C0, I2C_FREQ_100KHZ), NULL);
+}
+
+static void *i2c_setup(void)
+{
+	i2c_freq_reset();
+	return NULL;
+}
+
+static void i2c_teardown(void *state)
+{
+	ARG_UNUSED(state);
+	i2c_freq_reset();
+}
+
+ZTEST_SUITE(i2c, drivers_predicate_post_main, i2c_setup, NULL, NULL,
+	    i2c_teardown);
diff --git a/zephyr/test/drivers/default/src/i2c_passthru.c b/zephyr/test/drivers/default/src/i2c_passthru.c
new file mode 100644
index 0000000000..aea81fc198
--- /dev/null
+++ b/zephyr/test/drivers/default/src/i2c_passthru.c
@@ -0,0 +1,123 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+#include "driver/ln9310.h"
+#include "ec_commands.h"
+#include "host_command.h"
+#include "i2c.h"
+#include "test/drivers/test_state.h"
+
+ZTEST_USER(i2c_passthru, test_read_without_write)
+{
+	uint8_t param_buf[sizeof(struct ec_params_i2c_passthru) +
+			  sizeof(struct ec_params_i2c_passthru_msg)];
+	uint8_t response_buf[sizeof(struct ec_response_i2c_passthru) + 2];
+	struct ec_params_i2c_passthru *params =
+		(struct ec_params_i2c_passthru *)&param_buf;
+	struct ec_response_i2c_passthru *response =
+		(struct ec_response_i2c_passthru *)&response_buf;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_SIMPLE(EC_CMD_I2C_PASSTHRU, 0);
+
+	params->port = I2C_PORT_POWER;
+	params->num_msgs = 1;
+	params->msg[0].addr_flags = LN9310_I2C_ADDR_0_FLAGS | EC_I2C_FLAG_READ;
+	params->msg[0].len = 1;
+	args.params = &param_buf;
+	args.params_size = sizeof(param_buf);
+	args.response = &response_buf;
+	args.response_max = sizeof(response_buf);
+
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_ok(args.result, NULL);
+	zassert_equal(response->i2c_status, EC_I2C_STATUS_NAK, NULL);
+	zassert_equal(args.response_size,
+		      sizeof(struct ec_response_i2c_passthru), NULL);
+}
+
+ZTEST_USER(i2c_passthru, test_passthru_protect)
+{
+	struct ec_response_i2c_passthru_protect response;
+	struct ec_params_i2c_passthru_protect status_params = {
+		.port = I2C_PORT_SENSOR,
+		.subcmd = EC_CMD_I2C_PASSTHRU_PROTECT_STATUS,
+	};
+	struct host_cmd_handler_args status_args = BUILD_HOST_COMMAND(
+		EC_CMD_I2C_PASSTHRU_PROTECT, 0, response, status_params);
+	struct ec_params_i2c_passthru_protect enable_params = {
+		.port = I2C_PORT_SENSOR,
+		.subcmd = EC_CMD_I2C_PASSTHRU_PROTECT_ENABLE,
+	};
+	struct host_cmd_handler_args enable_args = BUILD_HOST_COMMAND_PARAMS(
+		EC_CMD_I2C_PASSTHRU_PROTECT, 0, enable_params);
+
+	/* Check the protect status: 0 (unprotected) */
+	zassert_ok(host_command_process(&status_args), NULL);
+	zassert_ok(status_args.result, NULL);
+	zassert_equal(status_args.response_size, sizeof(response), NULL);
+	zassert_equal(response.status, 0, "response.status = %d",
+		      response.status);
+
+	/* Protect the bus */
+	zassert_ok(host_command_process(&enable_args), NULL);
+	zassert_ok(enable_args.result, NULL);
+
+	/* Check the protect status: 1 (protected) */
+	zassert_ok(host_command_process(&status_args), NULL);
+	zassert_ok(status_args.result, NULL);
+	zassert_equal(status_args.response_size, sizeof(response), NULL);
+	zassert_equal(response.status, 1, "response.status = %d",
+		      response.status);
+
+	/* Error case: wrong subcmd */
+	status_params.subcmd = 10;
+	zassert_equal(host_command_process(&status_args),
+		      EC_RES_INVALID_COMMAND, NULL);
+	status_params.subcmd = EC_CMD_I2C_PASSTHRU_PROTECT_STATUS;
+
+	/* Error case: wrong port */
+	status_params.port = 10;
+	zassert_equal(host_command_process(&status_args), EC_RES_INVALID_PARAM,
+		      NULL);
+	status_params.port = I2C_PORT_SENSOR;
+
+	/* Error case: response size not enough */
+	status_args.response_max = 0;
+	zassert_equal(host_command_process(&status_args), EC_RES_INVALID_PARAM,
+		      NULL);
+	status_args.response_max = sizeof(response);
+
+	/* Error case: params size not enough */
+	status_args.params_size = 0;
+	zassert_equal(host_command_process(&status_args), EC_RES_INVALID_PARAM,
+		      NULL);
+	status_args.params_size = sizeof(status_params);
+}
+
+ZTEST_USER(i2c_passthru, test_passthru_protect_tcpcs)
+{
+	struct ec_params_i2c_passthru_protect enable_params = {
+		.port = I2C_PORT_SENSOR,
+		.subcmd = EC_CMD_I2C_PASSTHRU_PROTECT_ENABLE_TCPCS,
+	};
+	struct host_cmd_handler_args enable_args = BUILD_HOST_COMMAND_PARAMS(
+		EC_CMD_I2C_PASSTHRU_PROTECT, 0, enable_params);
+
+	/* Protect the all TCPC buses */
+	zassert_ok(host_command_process(&enable_args), NULL);
+	zassert_ok(enable_args.result, NULL);
+}
+
+static void i2c_passthru_after(void *state)
+{
+	ARG_UNUSED(state);
+	i2c_passthru_protect_reset();
+}
+
+ZTEST_SUITE(i2c_passthru, drivers_predicate_post_main, NULL, NULL,
+	    i2c_passthru_after, NULL);
diff --git a/zephyr/test/drivers/src/integration/usbc/usb.c b/zephyr/test/drivers/default/src/integration/usbc/usb.c
index 0a6443ded9..0436f55e93 100644
--- a/zephyr/test/drivers/src/integration/usbc/usb.c
+++ b/zephyr/test/drivers/default/src/integration/usbc/usb.c
@@ -1,10 +1,10 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <zephyr/zephyr.h>
-#include <ztest.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
 #include <zephyr/drivers/gpio/gpio_emul.h>
 
 #include "battery_smart.h"
@@ -25,10 +25,7 @@
 #include "test/drivers/utils.h"
 #include "test/drivers/test_state.h"
 
-#define TCPCI_EMUL_LABEL DT_NODELABEL(tcpci_emul)
-#define TCPCI_EMUL_LABEL2 DT_NODELABEL(tcpci_ps8xxx_emul)
-
-#define BATTERY_ORD DT_DEP_ORD(DT_NODELABEL(battery))
+#define BATTERY_NODE DT_NODELABEL(battery)
 
 #define GPIO_AC_OK_PATH DT_PATH(named_gpios, acok_od)
 #define GPIO_AC_OK_PIN DT_GPIO_PIN(GPIO_AC_OK_PATH, gpios)
@@ -38,16 +35,13 @@
 
 static void integration_usb_before(void *state)
 {
-	const struct emul *tcpci_emul =
-		emul_get_binding(DT_LABEL(TCPCI_EMUL_LABEL));
-	const struct emul *tcpci_emul2 =
-		emul_get_binding(DT_LABEL(TCPCI_EMUL_LABEL2));
-	const struct emul *charger_emul =
-		emul_get_binding(DT_LABEL(DT_NODELABEL(isl923x_emul)));
+	const struct emul *tcpci_emul = EMUL_GET_USBC_BINDING(0, tcpc);
+	const struct emul *tcpci_emul2 = EMUL_GET_USBC_BINDING(1, tcpc);
+	const struct emul *charger_emul = EMUL_GET_USBC_BINDING(0, chg);
 	/* Reset vbus to 0mV */
 	/* TODO(b/217610871): Remove redundant test state cleanup */
 	isl923x_emul_set_adc_vbus(charger_emul, 0);
-	struct i2c_emul *i2c_emul;
+	const struct emul *battery_emul = EMUL_DT_GET(BATTERY_NODE);
 	struct sbat_emul_bat_data *bat;
 	const struct device *gpio_dev =
 		DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_AC_OK_PATH, gpios));
@@ -58,6 +52,7 @@ static void integration_usb_before(void *state)
 	 */
 	zassert_ok(tcpc_config[0].drv->init(0), NULL);
 	zassert_ok(tcpc_config[1].drv->init(1), NULL);
+	tcpc_config[USBC_PORT_C0].flags &= ~TCPC_FLAGS_TCPCI_REV2_0;
 	tcpci_emul_set_rev(tcpci_emul, TCPCI_EMUL_REV1_0_VER1_0);
 	pd_set_suspend(0, 0);
 	pd_set_suspend(1, 0);
@@ -69,8 +64,7 @@ static void integration_usb_before(void *state)
 	zassert_ok(tcpci_emul_disconnect_partner(tcpci_emul2), NULL);
 
 	/* Battery defaults to charging, so reset to not charging. */
-	i2c_emul = sbat_emul_get_ptr(BATTERY_ORD);
-	bat = sbat_emul_get_bat_data(i2c_emul);
+	bat = sbat_emul_get_bat_data(battery_emul);
 	bat->cur = -5;
 
 	/*
@@ -81,12 +75,9 @@ static void integration_usb_before(void *state)
 
 static void integration_usb_after(void *state)
 {
-	const struct emul *tcpci_emul =
-		emul_get_binding(DT_LABEL(TCPCI_EMUL_LABEL));
-	const struct emul *tcpci_emul2 =
-		emul_get_binding(DT_LABEL(TCPCI_EMUL_LABEL2));
-	const struct emul *charger_emul =
-		emul_get_binding(DT_LABEL(DT_NODELABEL(isl923x_emul)));
+	const struct emul *tcpci_emul = EMUL_GET_USBC_BINDING(0, tcpc);
+	const struct emul *tcpci_emul2 = EMUL_GET_USBC_BINDING(1, tcpc);
+	const struct emul *charger_emul = EMUL_GET_USBC_BINDING(0, chg);
 	ARG_UNUSED(state);
 
 	/* TODO: This function should trigger gpios to signal there is nothing
@@ -106,8 +97,7 @@ static void integration_usb_after(void *state)
 
 ZTEST(integration_usb, test_attach_drp)
 {
-	const struct emul *tcpci_emul =
-		emul_get_binding(DT_LABEL(TCPCI_EMUL_LABEL));
+	const struct emul *tcpci_emul = EMUL_GET_USBC_BINDING(0, tcpc);
 	struct tcpci_partner_data my_drp;
 	struct tcpci_drp_emul_data drp_ext;
 	struct tcpci_src_emul_data src_ext;
@@ -121,14 +111,12 @@ ZTEST(integration_usb, test_attach_drp)
 
 	/* Attach emulated sink */
 	tcpci_partner_init(&my_drp, PD_REV20);
-	my_drp.extensions =
-		tcpci_drp_emul_init(
-			&drp_ext, &my_drp, PD_ROLE_SINK,
-			tcpci_src_emul_init(&src_ext, &my_drp, NULL),
-			tcpci_snk_emul_init(&snk_ext, &my_drp, NULL));
-
-	zassert_ok(tcpci_partner_connect_to_tcpci(&my_drp, tcpci_emul),
-		   NULL);
+	my_drp.extensions = tcpci_drp_emul_init(
+		&drp_ext, &my_drp, PD_ROLE_SINK,
+		tcpci_src_emul_init(&src_ext, &my_drp, NULL),
+		tcpci_snk_emul_init(&snk_ext, &my_drp, NULL));
+
+	zassert_ok(tcpci_partner_connect_to_tcpci(&my_drp, tcpci_emul), NULL);
 
 	/* Wait for PD negotiation */
 	k_sleep(K_SECONDS(10));
diff --git a/zephyr/test/drivers/src/integration/usbc/usb_20v_3a_pd_charger.c b/zephyr/test/drivers/default/src/integration/usbc/usb_20v_3a_pd_charger.c
index 79cbb21b96..3fc73337b9 100644
--- a/zephyr/test/drivers/src/integration/usbc/usb_20v_3a_pd_charger.c
+++ b/zephyr/test/drivers/default/src/integration/usbc/usb_20v_3a_pd_charger.c
@@ -1,9 +1,9 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <ztest.h>
+#include <zephyr/ztest.h>
 
 #include "battery_smart.h"
 #include "emul/emul_isl923x.h"
@@ -13,7 +13,7 @@
 #include "test/drivers/utils.h"
 #include "usb_pd.h"
 
-#define BATTERY_ORD DT_DEP_ORD(DT_NODELABEL(battery))
+#define BATTERY_NODE DT_NODELABEL(battery)
 
 struct usb_attach_20v_3a_pd_charger_fixture {
 	struct tcpci_partner_data charger_20v;
@@ -26,13 +26,12 @@ static inline void
 connect_charger_to_port(struct usb_attach_20v_3a_pd_charger_fixture *fixture)
 {
 	set_ac_enabled(true);
-	zassume_ok(tcpci_partner_connect_to_tcpci(
-			   &fixture->charger_20v, fixture->tcpci_emul),
+	zassume_ok(tcpci_partner_connect_to_tcpci(&fixture->charger_20v,
+						  fixture->tcpci_emul),
 		   NULL);
 
-	isl923x_emul_set_adc_vbus(
-		fixture->charger_emul,
-		PDO_FIXED_GET_VOLT(fixture->src_ext.pdo[1]));
+	isl923x_emul_set_adc_vbus(fixture->charger_emul,
+				  PDO_FIXED_GET_VOLT(fixture->src_ext.pdo[1]));
 
 	/* Wait for PD negotiation and current ramp.
 	 * TODO(b/213906889): Check message timing and contents.
@@ -54,16 +53,13 @@ static void *usb_attach_20v_3a_pd_charger_setup(void)
 	static struct usb_attach_20v_3a_pd_charger_fixture test_fixture;
 
 	/* Get references for the emulators */
-	test_fixture.tcpci_emul =
-		emul_get_binding(DT_LABEL(DT_NODELABEL(tcpci_emul)));
-	test_fixture.charger_emul =
-		emul_get_binding(DT_LABEL(DT_NODELABEL(isl923x_emul)));
+	test_fixture.tcpci_emul = EMUL_GET_USBC_BINDING(0, tcpc);
+	test_fixture.charger_emul = EMUL_GET_USBC_BINDING(0, chg);
 
 	/* Initialized the charger to supply 20V and 3A */
 	tcpci_partner_init(&test_fixture.charger_20v, PD_REV20);
-	test_fixture.charger_20v.extensions =
-		tcpci_src_emul_init(&test_fixture.src_ext,
-				    &test_fixture.charger_20v, NULL);
+	test_fixture.charger_20v.extensions = tcpci_src_emul_init(
+		&test_fixture.src_ext, &test_fixture.charger_20v, NULL);
 	test_fixture.src_ext.pdo[1] =
 		PDO_FIXED(20000, 3000, PDO_FIXED_UNCONSTRAINED);
 
@@ -89,10 +85,10 @@ ZTEST_SUITE(usb_attach_20v_3a_pd_charger, drivers_predicate_post_main,
 
 ZTEST(usb_attach_20v_3a_pd_charger, test_battery_is_charging)
 {
-	struct i2c_emul *i2c_emul = sbat_emul_get_ptr(BATTERY_ORD);
+	const struct emul *emul = EMUL_DT_GET(BATTERY_NODE);
 	uint16_t battery_status;
 
-	zassume_ok(sbat_emul_get_word_val(i2c_emul, SB_BATTERY_STATUS,
+	zassume_ok(sbat_emul_get_word_val(emul, SB_BATTERY_STATUS,
 					  &battery_status),
 		   NULL);
 	zassert_equal(battery_status & STATUS_DISCHARGING, 0,
@@ -157,11 +153,11 @@ ZTEST(usb_attach_20v_3a_pd_charger, test_power_info)
 
 ZTEST_F(usb_attach_20v_3a_pd_charger, test_disconnect_battery_not_charging)
 {
-	struct i2c_emul *i2c_emul = sbat_emul_get_ptr(BATTERY_ORD);
+	const struct emul *emul = EMUL_DT_GET(BATTERY_NODE);
 	uint16_t battery_status;
 
-	disconnect_charger_from_port(this);
-	zassert_ok(sbat_emul_get_word_val(i2c_emul, SB_BATTERY_STATUS,
+	disconnect_charger_from_port(fixture);
+	zassert_ok(sbat_emul_get_word_val(emul, SB_BATTERY_STATUS,
 					  &battery_status),
 		   NULL);
 	zassert_equal(battery_status & STATUS_DISCHARGING, STATUS_DISCHARGING,
@@ -172,7 +168,7 @@ ZTEST_F(usb_attach_20v_3a_pd_charger, test_disconnect_charge_state)
 {
 	struct ec_response_charge_state charge_state;
 
-	disconnect_charger_from_port(this);
+	disconnect_charger_from_port(fixture);
 	charge_state = host_cmd_charge_state(0);
 
 	zassert_false(charge_state.get_state.ac, "AC_OK not triggered");
@@ -190,7 +186,7 @@ ZTEST_F(usb_attach_20v_3a_pd_charger, test_disconnect_typec_status)
 {
 	struct ec_response_typec_status typec_status;
 
-	disconnect_charger_from_port(this);
+	disconnect_charger_from_port(fixture);
 	typec_status = host_cmd_typec_status(0);
 
 	zassert_false(typec_status.pd_enabled, NULL);
@@ -208,7 +204,7 @@ ZTEST_F(usb_attach_20v_3a_pd_charger, test_disconnect_power_info)
 {
 	struct ec_response_usb_pd_power_info power_info;
 
-	disconnect_charger_from_port(this);
+	disconnect_charger_from_port(fixture);
 	power_info = host_cmd_power_info(0);
 
 	zassert_equal(power_info.role, USB_PD_PORT_POWER_DISCONNECTED,
diff --git a/zephyr/test/drivers/src/integration/usbc/usb_5v_3a_pd_sink.c b/zephyr/test/drivers/default/src/integration/usbc/usb_5v_3a_pd_sink.c
index 1cbdda49b0..5654754838 100644
--- a/zephyr/test/drivers/src/integration/usbc/usb_5v_3a_pd_sink.c
+++ b/zephyr/test/drivers/default/src/integration/usbc/usb_5v_3a_pd_sink.c
@@ -1,10 +1,10 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include <stdint.h>
-#include <ztest.h>
+#include <zephyr/ztest.h>
 
 #include "battery_smart.h"
 #include "emul/emul_isl923x.h"
@@ -14,7 +14,6 @@
 #include "test/drivers/test_state.h"
 #include "test/drivers/utils.h"
 #include "timer.h"
-#include "usb_common.h"
 #include "usb_pd.h"
 
 struct usb_attach_5v_3a_pd_sink_fixture {
@@ -33,51 +32,13 @@ struct usb_attach_5v_3a_pd_sink_fixture {
 /* Only used to verify sink capabilities being received by SRC port */
 #define TEST_ADDITIONAL_SINK_CAP PDO_FIXED(TEST_SRC_PORT_VBUS_MV, 5000, 0)
 
-static void
-connect_sink_to_port(struct usb_attach_5v_3a_pd_sink_fixture *fixture)
-{
-	/*
-	 * TODO(b/221439302) Updating the TCPCI emulator registers, updating the
-	 *   vbus, as well as alerting should all be a part of the connect
-	 *   function.
-	 */
-	isl923x_emul_set_adc_vbus(fixture->charger_emul, 0);
-	tcpci_emul_set_reg(fixture->tcpci_emul, TCPC_REG_POWER_STATUS,
-			   TCPC_REG_POWER_STATUS_VBUS_DET);
-	tcpci_emul_set_reg(fixture->tcpci_emul, TCPC_REG_EXT_STATUS,
-			   TCPC_REG_EXT_STATUS_SAFE0V);
-
-	tcpci_tcpc_alert(0);
-	k_sleep(K_SECONDS(1));
-
-	zassume_ok(tcpci_partner_connect_to_tcpci(
-			   &fixture->sink_5v_3a,
-			   fixture->tcpci_emul),
-		   NULL);
-
-	/* Wait for PD negotiation and current ramp.
-	 * TODO(b/213906889): Check message timing and contents.
-	 */
-	k_sleep(K_SECONDS(10));
-}
-
-static inline void disconnect_sink_from_port(
-	struct usb_attach_5v_3a_pd_sink_fixture *fixture)
-{
-	zassume_ok(tcpci_emul_disconnect_partner(fixture->tcpci_emul), NULL);
-	k_sleep(K_SECONDS(1));
-}
-
 static void *usb_attach_5v_3a_pd_sink_setup(void)
 {
 	static struct usb_attach_5v_3a_pd_sink_fixture test_fixture;
 
 	/* Get references for the emulators */
-	test_fixture.tcpci_emul =
-		emul_get_binding(DT_LABEL(DT_NODELABEL(tcpci_emul)));
-	test_fixture.charger_emul =
-		emul_get_binding(DT_LABEL(DT_NODELABEL(isl923x_emul)));
-	tcpci_emul_set_rev(test_fixture.tcpci_emul, TCPCI_EMUL_REV2_0_VER1_1);
+	test_fixture.tcpci_emul = EMUL_GET_USBC_BINDING(0, tcpc);
+	test_fixture.charger_emul = EMUL_GET_USBC_BINDING(0, chg);
 
 	return &test_fixture;
 }
@@ -94,37 +55,37 @@ static void usb_attach_5v_3a_pd_sink_before(void *data)
 
 	/* Initialized the sink to request 5V and 3A */
 	tcpci_partner_init(&test_fixture->sink_5v_3a, PD_REV20);
-	test_fixture->sink_5v_3a.extensions =
-		tcpci_snk_emul_init(&test_fixture->snk_ext,
-				    &test_fixture->sink_5v_3a, NULL);
+	test_fixture->sink_5v_3a.extensions = tcpci_snk_emul_init(
+		&test_fixture->snk_ext, &test_fixture->sink_5v_3a, NULL);
 	test_fixture->snk_ext.pdo[0] = TEST_INITIAL_SINK_CAP;
 	test_fixture->snk_ext.pdo[1] = TEST_ADDITIONAL_SINK_CAP;
-	connect_sink_to_port(test_fixture);
+	connect_sink_to_port(&test_fixture->sink_5v_3a,
+			     test_fixture->tcpci_emul,
+			     test_fixture->charger_emul);
 }
 
 static void usb_attach_5v_3a_pd_sink_after(void *data)
 {
-	disconnect_sink_from_port(
-		(struct usb_attach_5v_3a_pd_sink_fixture *)data);
+	struct usb_attach_5v_3a_pd_sink_fixture *test_fixture = data;
+
+	disconnect_sink_from_port(test_fixture->tcpci_emul);
 }
 
 ZTEST_SUITE(usb_attach_5v_3a_pd_sink, drivers_predicate_post_main,
-	    usb_attach_5v_3a_pd_sink_setup,
-	    usb_attach_5v_3a_pd_sink_before,
+	    usb_attach_5v_3a_pd_sink_setup, usb_attach_5v_3a_pd_sink_before,
 	    usb_attach_5v_3a_pd_sink_after, NULL);
 
 ZTEST_F(usb_attach_5v_3a_pd_sink, test_partner_pd_completed)
 {
-	zassert_true(this->snk_ext.pd_completed, NULL);
+	zassert_true(fixture->snk_ext.pd_completed, NULL);
 }
 
 ZTEST(usb_attach_5v_3a_pd_sink, test_battery_is_discharging)
 {
-	struct i2c_emul *i2c_emul =
-		sbat_emul_get_ptr(DT_DEP_ORD(DT_NODELABEL(battery)));
+	const struct emul *emul = EMUL_DT_GET(DT_NODELABEL(battery));
 	uint16_t battery_status;
 
-	zassume_ok(sbat_emul_get_word_val(i2c_emul, SB_BATTERY_STATUS,
+	zassume_ok(sbat_emul_get_word_val(emul, SB_BATTERY_STATUS,
 					  &battery_status),
 		   NULL);
 	zassert_equal(battery_status & STATUS_DISCHARGING, STATUS_DISCHARGING,
@@ -167,21 +128,20 @@ ZTEST(usb_attach_5v_3a_pd_sink, test_power_info)
 		      "Current max expected to be 1500mV, but was %dmV",
 		      info.meas.current_max);
 	zassert_equal(info.meas.current_lim, 0,
-		     "VBUS max is set to 0mA, but PD is reporting %dmA",
-		     info.meas.current_lim);
+		      "VBUS max is set to 0mA, but PD is reporting %dmA",
+		      info.meas.current_lim);
 	zassert_equal(info.max_power, 0,
-		      "Charging expected to be at %duW, but PD max is %duW",
-		      0, info.max_power);
+		      "Charging expected to be at %duW, but PD max is %duW", 0,
+		      info.max_power);
 }
 
 ZTEST_F(usb_attach_5v_3a_pd_sink, test_disconnect_battery_discharging)
 {
-	struct i2c_emul *i2c_emul =
-		sbat_emul_get_ptr(DT_DEP_ORD(DT_NODELABEL(battery)));
+	const struct emul *emul = EMUL_DT_GET(DT_NODELABEL(battery));
 	uint16_t battery_status;
 
-	disconnect_sink_from_port(this);
-	zassert_ok(sbat_emul_get_word_val(i2c_emul, SB_BATTERY_STATUS,
+	disconnect_sink_from_port(fixture->tcpci_emul);
+	zassert_ok(sbat_emul_get_word_val(emul, SB_BATTERY_STATUS,
 					  &battery_status),
 		   NULL);
 	zassert_equal(battery_status & STATUS_DISCHARGING, STATUS_DISCHARGING,
@@ -192,7 +152,7 @@ ZTEST_F(usb_attach_5v_3a_pd_sink, test_disconnect_charge_state)
 {
 	struct ec_response_charge_state charge_state;
 
-	disconnect_sink_from_port(this);
+	disconnect_sink_from_port(fixture->tcpci_emul);
 	charge_state = host_cmd_charge_state(0);
 
 	zassert_false(charge_state.get_state.ac, "AC_OK not triggered");
@@ -210,7 +170,7 @@ ZTEST_F(usb_attach_5v_3a_pd_sink, test_disconnect_typec_status)
 {
 	struct ec_response_typec_status typec_status;
 
-	disconnect_sink_from_port(this);
+	disconnect_sink_from_port(fixture->tcpci_emul);
 	typec_status = host_cmd_typec_status(0);
 
 	zassert_false(typec_status.pd_enabled, NULL);
@@ -228,7 +188,7 @@ ZTEST_F(usb_attach_5v_3a_pd_sink, test_disconnect_power_info)
 {
 	struct ec_response_usb_pd_power_info power_info;
 
-	disconnect_sink_from_port(this);
+	disconnect_sink_from_port(fixture->tcpci_emul);
 	power_info = host_cmd_power_info(0);
 
 	zassert_equal(power_info.role, USB_PD_PORT_POWER_DISCONNECTED,
@@ -270,7 +230,7 @@ ZTEST_F(usb_attach_5v_3a_pd_sink, verify_goto_min)
 	pd_dpm_request(0, DPM_REQUEST_GOTO_MIN);
 	k_sleep(K_SECONDS(1));
 
-	zassert_true(this->snk_ext.pd_completed, NULL);
+	zassert_true(fixture->snk_ext.pd_completed, NULL);
 }
 
 /**
@@ -286,33 +246,10 @@ ZTEST_F(usb_attach_5v_3a_pd_sink, verify_goto_min)
  */
 ZTEST_F(usb_attach_5v_3a_pd_sink, verify_ping_msg)
 {
-	tcpci_snk_emul_clear_ping_received(&this->snk_ext);
+	tcpci_snk_emul_clear_ping_received(&fixture->snk_ext);
 
 	pd_dpm_request(0, DPM_REQUEST_SEND_PING);
 	k_sleep(K_USEC(PD_T_SOURCE_ACTIVITY));
 
-	zassert_true(this->snk_ext.ping_received, NULL);
-}
-
-/**
- * @brief TestPurpose: Verify Alert message.
- *
- * @details
- *  - Clear alert_received in emulated partner
- *  - Broadcast PD Alert
- *  - Check pd_broadcast_alert_msg can set the ADO and run pd_dpm_request
- *  - Check that emulated partner received a PD_DATA_ALERT message
- *
- * Expected Results
- *  - EC_SUCCESS returned from pd_broadcast_alert_msg
- *  - sink_5v_3a.data.alert_received is true
- */
-ZTEST_F(usb_attach_5v_3a_pd_sink, verify_alert_msg)
-{
-	tcpci_snk_emul_clear_alert_received(&this->snk_ext);
-	zassert_false(this->snk_ext.alert_received, NULL);
-	zassert_equal(pd_broadcast_alert_msg(ADO_OTP_EVENT), EC_SUCCESS, NULL);
-
-	k_sleep(K_SECONDS(2));
-	zassert_true(this->snk_ext.alert_received, NULL);
+	zassert_true(fixture->snk_ext.ping_received, NULL);
 }
diff --git a/zephyr/test/drivers/src/integration/usbc/usb_5v_3a_pd_source.c b/zephyr/test/drivers/default/src/integration/usbc/usb_5v_3a_pd_source.c
index 39745dd70b..4d89e8c0d3 100644
--- a/zephyr/test/drivers/src/integration/usbc/usb_5v_3a_pd_source.c
+++ b/zephyr/test/drivers/default/src/integration/usbc/usb_5v_3a_pd_source.c
@@ -1,24 +1,20 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <ztest.h>
+#include <zephyr/ztest.h>
 
 #include "battery_smart.h"
 #include "emul/emul_isl923x.h"
 #include "emul/emul_smart_battery.h"
 #include "emul/tcpc/emul_tcpci_partner_src.h"
-#include "hooks.h"
-#include "test/drivers/stubs.h"
+#include "system.h"
 #include "test/drivers/test_state.h"
 #include "test/drivers/utils.h"
 #include "usb_pd.h"
-#include "usb_prl_sm.h"
 
-#define BATTERY_ORD DT_DEP_ORD(DT_NODELABEL(battery))
-
-#define TEST_USB_PORT USBC_PORT_C0
+#define BATTERY_NODE DT_NODELABEL(battery)
 
 struct usb_attach_5v_3a_pd_source_fixture {
 	struct tcpci_partner_data source_5v_3a;
@@ -32,20 +28,13 @@ static void *usb_attach_5v_3a_pd_source_setup(void)
 	static struct usb_attach_5v_3a_pd_source_fixture test_fixture;
 
 	/* Get references for the emulators */
-	test_fixture.tcpci_emul =
-		emul_get_binding(DT_LABEL(DT_NODELABEL(tcpci_emul)));
-	test_fixture.charger_emul =
-		emul_get_binding(DT_LABEL(DT_NODELABEL(isl923x_emul)));
-
-	/* Configure TCPCI revision in board config and emulator */
-	tcpc_config[0].flags |= TCPC_FLAGS_TCPCI_REV2_0;
-	tcpci_emul_set_rev(test_fixture.tcpci_emul, TCPCI_EMUL_REV2_0_VER1_1);
+	test_fixture.tcpci_emul = EMUL_GET_USBC_BINDING(0, tcpc);
+	test_fixture.charger_emul = EMUL_GET_USBC_BINDING(0, chg);
 
 	/* Initialized the charger to supply 5V and 3A */
 	tcpci_partner_init(&test_fixture.source_5v_3a, PD_REV20);
-	test_fixture.source_5v_3a.extensions =
-		tcpci_src_emul_init(&test_fixture.src_ext,
-				    &test_fixture.source_5v_3a, NULL);
+	test_fixture.source_5v_3a.extensions = tcpci_src_emul_init(
+		&test_fixture.src_ext, &test_fixture.source_5v_3a, NULL);
 	test_fixture.src_ext.pdo[1] =
 		PDO_FIXED(5000, 3000, PDO_FIXED_UNCONSTRAINED);
 
@@ -68,16 +57,15 @@ static void usb_attach_5v_3a_pd_source_after(void *data)
 }
 
 ZTEST_SUITE(usb_attach_5v_3a_pd_source, drivers_predicate_post_main,
-	    usb_attach_5v_3a_pd_source_setup,
-	    usb_attach_5v_3a_pd_source_before,
+	    usb_attach_5v_3a_pd_source_setup, usb_attach_5v_3a_pd_source_before,
 	    usb_attach_5v_3a_pd_source_after, NULL);
 
 ZTEST(usb_attach_5v_3a_pd_source, test_battery_is_charging)
 {
-	struct i2c_emul *i2c_emul = sbat_emul_get_ptr(BATTERY_ORD);
+	const struct emul *emul = EMUL_DT_GET(BATTERY_NODE);
 	uint16_t battery_status;
 
-	zassume_ok(sbat_emul_get_word_val(i2c_emul, SB_BATTERY_STATUS,
+	zassume_ok(sbat_emul_get_word_val(emul, SB_BATTERY_STATUS,
 					  &battery_status),
 		   NULL);
 	zassert_equal(battery_status & STATUS_DISCHARGING, 0,
@@ -142,11 +130,11 @@ ZTEST(usb_attach_5v_3a_pd_source, test_power_info)
 
 ZTEST_F(usb_attach_5v_3a_pd_source, test_disconnect_battery_not_charging)
 {
-	struct i2c_emul *i2c_emul = sbat_emul_get_ptr(BATTERY_ORD);
+	const struct emul *emul = EMUL_DT_GET(BATTERY_NODE);
 	uint16_t battery_status;
 
-	disconnect_source_from_port(this->tcpci_emul, this->charger_emul);
-	zassert_ok(sbat_emul_get_word_val(i2c_emul, SB_BATTERY_STATUS,
+	disconnect_source_from_port(fixture->tcpci_emul, fixture->charger_emul);
+	zassert_ok(sbat_emul_get_word_val(emul, SB_BATTERY_STATUS,
 					  &battery_status),
 		   NULL);
 	zassert_equal(battery_status & STATUS_DISCHARGING, STATUS_DISCHARGING,
@@ -157,7 +145,7 @@ ZTEST_F(usb_attach_5v_3a_pd_source, test_disconnect_charge_state)
 {
 	struct ec_response_charge_state charge_state;
 
-	disconnect_source_from_port(this->tcpci_emul, this->charger_emul);
+	disconnect_source_from_port(fixture->tcpci_emul, fixture->charger_emul);
 	charge_state = host_cmd_charge_state(0);
 
 	zassert_false(charge_state.get_state.ac, "AC_OK not triggered");
@@ -175,7 +163,7 @@ ZTEST_F(usb_attach_5v_3a_pd_source, test_disconnect_typec_status)
 {
 	struct ec_response_typec_status typec_status;
 
-	disconnect_source_from_port(this->tcpci_emul, this->charger_emul);
+	disconnect_source_from_port(fixture->tcpci_emul, fixture->charger_emul);
 	typec_status = host_cmd_typec_status(0);
 
 	zassert_false(typec_status.pd_enabled, NULL);
@@ -193,7 +181,7 @@ ZTEST_F(usb_attach_5v_3a_pd_source, test_disconnect_power_info)
 {
 	struct ec_response_usb_pd_power_info power_info;
 
-	disconnect_source_from_port(this->tcpci_emul, this->charger_emul);
+	disconnect_source_from_port(fixture->tcpci_emul, fixture->charger_emul);
 	power_info = host_cmd_power_info(0);
 
 	zassert_equal(power_info.role, USB_PD_PORT_POWER_DISCONNECTED,
@@ -219,57 +207,42 @@ ZTEST_F(usb_attach_5v_3a_pd_source, test_disconnect_power_info)
 		     power_info.meas.current_lim);
 }
 
-ZTEST_F(usb_attach_5v_3a_pd_source, verify_dock_with_power_button)
+ZTEST(usb_attach_5v_3a_pd_source,
+      test_ap_can_boot_on_low_battery_while_charging)
 {
-	/* Clear Alert and Status receive checks */
-	tcpci_src_emul_clear_alert_received(&this->src_ext);
-	tcpci_src_emul_clear_status_received(&this->src_ext);
-	zassert_false(this->src_ext.alert_received, NULL);
-	zassert_false(this->src_ext.status_received, NULL);
-
-	/* Setting up revision for the full Status message */
-	prl_set_rev(TEST_USB_PORT, TCPCI_MSG_SOP, PD_REV30);
-	k_sleep(K_MSEC(10));
-	pd_dpm_request(TEST_USB_PORT, DPM_REQUEST_GET_REVISION);
-	k_sleep(K_MSEC(10));
-
-	/* Suspend and check partner received Alert and Status messages */
-	hook_notify(HOOK_CHIPSET_SUSPEND);
-	k_sleep(K_SECONDS(2));
-	zassert_true(this->src_ext.alert_received, NULL);
-	zassert_true(this->src_ext.status_received, NULL);
-	tcpci_src_emul_clear_alert_received(&this->src_ext);
-	tcpci_src_emul_clear_status_received(&this->src_ext);
-	zassert_false(this->src_ext.alert_received, NULL);
-	zassert_false(this->src_ext.status_received, NULL);
-
-	/* Shutdown and check partner received Alert and Status messages */
-	hook_notify(HOOK_CHIPSET_SHUTDOWN);
-	k_sleep(K_SECONDS(2));
-	zassert_true(this->src_ext.alert_received, NULL);
-	zassert_true(this->src_ext.status_received, NULL);
-	tcpci_src_emul_clear_alert_received(&this->src_ext);
-	tcpci_src_emul_clear_status_received(&this->src_ext);
-	zassert_false(this->src_ext.alert_received, NULL);
-	zassert_false(this->src_ext.status_received, NULL);
-
-	/* Startup and check partner received Alert and Status messages */
-	hook_notify(HOOK_CHIPSET_STARTUP);
-	k_sleep(K_SECONDS(2));
-	zassert_true(this->src_ext.alert_received, NULL);
-	zassert_true(this->src_ext.status_received, NULL);
-	tcpci_src_emul_clear_alert_received(&this->src_ext);
-	tcpci_src_emul_clear_status_received(&this->src_ext);
-	zassert_false(this->src_ext.alert_received, NULL);
-	zassert_false(this->src_ext.status_received, NULL);
-
-	/* Resume and check partner received Alert and Status messages */
-	hook_notify(HOOK_CHIPSET_RESUME);
-	k_sleep(K_SECONDS(2));
-	zassert_true(this->src_ext.alert_received, NULL);
-	zassert_true(this->src_ext.status_received, NULL);
-	tcpci_src_emul_clear_alert_received(&this->src_ext);
-	tcpci_src_emul_clear_status_received(&this->src_ext);
-	zassert_false(this->src_ext.alert_received, NULL);
-	zassert_false(this->src_ext.status_received, NULL);
+	const struct emul *smart_batt_emul = EMUL_DT_GET(DT_NODELABEL(battery));
+	struct sbat_emul_bat_data *batt_data =
+		sbat_emul_get_bat_data(smart_batt_emul);
+
+	/* Set capacity to what gives a charge percentage less than required
+	 * for booting the AP
+	 *
+	 * Capacaity is reset by emulator's ZTEST_RULE
+	 */
+	batt_data->cap = (CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON *
+			  batt_data->design_cap / 100) -
+			 1;
+
+	zassert_true(system_can_boot_ap(), NULL);
+}
+
+ZTEST_F(usb_attach_5v_3a_pd_source,
+	test_ap_fails_to_boot_on_low_battery_while_not_charging)
+{
+	const struct emul *smart_batt_emul = EMUL_DT_GET(DT_NODELABEL(battery));
+	struct sbat_emul_bat_data *batt_data =
+		sbat_emul_get_bat_data(smart_batt_emul);
+
+	/* Set capacity to what gives a charge percentage less than required
+	 * for booting the AP
+	 *
+	 * Capacaity is reset by emulator's ZTEST_RULE
+	 */
+	batt_data->cap = (CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON *
+			  batt_data->design_cap / 100) -
+			 1;
+
+	disconnect_source_from_port(fixture->tcpci_emul, fixture->charger_emul);
+
+	zassert_false(system_can_boot_ap(), NULL);
 }
diff --git a/zephyr/test/drivers/src/integration/usbc/usb_attach_src_snk.c b/zephyr/test/drivers/default/src/integration/usbc/usb_attach_src_snk.c
index 31d5c329b1..761bb9daf1 100644
--- a/zephyr/test/drivers/src/integration/usbc/usb_attach_src_snk.c
+++ b/zephyr/test/drivers/default/src/integration/usbc/usb_attach_src_snk.c
@@ -1,10 +1,10 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <zephyr/zephyr.h>
-#include <ztest.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
 #include <zephyr/drivers/gpio/gpio_emul.h>
 
 #include "ec_commands.h"
@@ -25,9 +25,6 @@
 #define SNK_PORT USBC_PORT_C0
 #define SRC_PORT USBC_PORT_C1
 
-#define TCPCI_EMUL_LABEL DT_NODELABEL(tcpci_emul)
-#define TCPCI_PS8XXX_EMUL_LABEL DT_NODELABEL(tcpci_ps8xxx_emul)
-
 #define DEFAULT_VBUS_MV 5000
 
 /* Determined by CONFIG_PLATFORM_EC_USB_PD_PULLUP */
@@ -60,12 +57,9 @@ struct integration_usb_attach_snk_then_src_fixture {
 
 static void integration_usb_setup(struct emul_state *fixture)
 {
-	const struct emul *tcpci_emul =
-		emul_get_binding(DT_LABEL(TCPCI_EMUL_LABEL));
-	const struct emul *tcpci_emul2 =
-		emul_get_binding(DT_LABEL(TCPCI_PS8XXX_EMUL_LABEL));
-	const struct emul *charger_emul =
-		emul_get_binding(DT_LABEL(DT_NODELABEL(isl923x_emul)));
+	const struct emul *tcpci_emul = EMUL_GET_USBC_BINDING(0, tcpc);
+	const struct emul *tcpci_emul2 = EMUL_GET_USBC_BINDING(1, tcpc);
+	const struct emul *charger_emul = EMUL_GET_USBC_BINDING(0, chg);
 
 	/* Setting these are required because compiler believes these values are
 	 * not compile time constants.
@@ -167,9 +161,6 @@ static void attach_emulated_snk(struct emul_state *my_emul_state)
 	struct tcpci_partner_data *my_snk = &my_emul_state->my_snk;
 	uint16_t power_reg_val;
 
-	/* Attach emulated sink */
-	tcpci_emul_set_rev(tcpci_emul_snk, TCPCI_EMUL_REV2_0_VER1_1);
-
 	/* Turn on VBUS detection */
 	/*
 	 * TODO(b/223901282): integration tests should not be setting vbus
@@ -200,9 +191,6 @@ static void attach_emulated_src(struct emul_state *my_emul_state)
 	struct tcpci_partner_data *my_src = &my_emul_state->my_src;
 	uint16_t power_reg_val;
 
-	/* Attach emulated charger. */
-	tcpci_emul_set_rev(tcpci_emul_src, TCPCI_EMUL_REV2_0_VER1_1);
-
 	/* Turn on VBUS detection */
 	/*
 	 * TODO(b/223901282): integration tests should not be setting vbus
@@ -605,15 +593,15 @@ static void usb_detach_test_after(void *state)
 
 ZTEST_F(usb_detach_test, verify_detach_src_snk)
 {
-	struct emul_state *fixture = &this->fixture;
+	struct emul_state *emul_state = &fixture->fixture;
 	struct ec_response_usb_pd_power_info src_power_info = { 0 };
 	struct ec_response_usb_pd_power_info snk_power_info = { 0 };
 
-	integration_usb_test_source_detach(fixture);
-	integration_usb_test_sink_detach(fixture);
+	integration_usb_test_source_detach(emul_state);
+	integration_usb_test_sink_detach(emul_state);
 
 	k_sleep(K_SECONDS(10));
-	isl923x_emul_set_adc_vbus(fixture->charger_isl923x_emul, 0);
+	isl923x_emul_set_adc_vbus(emul_state->charger_isl923x_emul, 0);
 
 	snk_power_info = host_cmd_power_info(SNK_PORT);
 	src_power_info = host_cmd_power_info(SRC_PORT);
@@ -667,15 +655,15 @@ ZTEST_F(usb_detach_test, verify_detach_src_snk)
 
 ZTEST_F(usb_detach_test, verify_detach_snk_src)
 {
-	struct emul_state *fixture = &this->fixture;
+	struct emul_state *emul_state = &fixture->fixture;
 	struct ec_response_usb_pd_power_info src_power_info = { 0 };
 	struct ec_response_usb_pd_power_info snk_power_info = { 0 };
 
-	integration_usb_test_sink_detach(fixture);
-	integration_usb_test_source_detach(fixture);
+	integration_usb_test_sink_detach(emul_state);
+	integration_usb_test_source_detach(emul_state);
 
 	k_sleep(K_SECONDS(10));
-	isl923x_emul_set_adc_vbus(fixture->charger_isl923x_emul, 0);
+	isl923x_emul_set_adc_vbus(emul_state->charger_isl923x_emul, 0);
 
 	snk_power_info = host_cmd_power_info(SNK_PORT);
 	src_power_info = host_cmd_power_info(SRC_PORT);
@@ -729,12 +717,12 @@ ZTEST_F(usb_detach_test, verify_detach_snk_src)
 
 ZTEST_F(usb_detach_test, verify_detach_sink)
 {
-	struct emul_state *fixture = &this->fixture;
+	struct emul_state *emul_state = &fixture->fixture;
 	struct ec_response_usb_pd_power_info pd_power_info = { 0 };
 
-	integration_usb_test_sink_detach(fixture);
+	integration_usb_test_sink_detach(emul_state);
 	k_sleep(K_SECONDS(10));
-	isl923x_emul_set_adc_vbus(fixture->charger_isl923x_emul, 0);
+	isl923x_emul_set_adc_vbus(emul_state->charger_isl923x_emul, 0);
 
 	pd_power_info = host_cmd_power_info(SNK_PORT);
 
@@ -771,12 +759,12 @@ ZTEST_F(usb_detach_test, verify_detach_sink)
 
 ZTEST_F(usb_detach_test, verify_detach_source)
 {
-	struct emul_state *fixture = &this->fixture;
+	struct emul_state *emul_state = &fixture->fixture;
 	struct ec_response_usb_pd_power_info pd_power_info = { SNK_PORT };
 
-	integration_usb_test_source_detach(fixture);
+	integration_usb_test_source_detach(emul_state);
 	k_sleep(K_SECONDS(10));
-	isl923x_emul_set_adc_vbus(fixture->charger_isl923x_emul, 0);
+	isl923x_emul_set_adc_vbus(emul_state->charger_isl923x_emul, 0);
 
 	pd_power_info = host_cmd_power_info(SNK_PORT);
 
diff --git a/zephyr/test/drivers/default/src/integration/usbc/usb_pd_bist_shared.c b/zephyr/test/drivers/default/src/integration/usbc/usb_pd_bist_shared.c
new file mode 100644
index 0000000000..9c76f862f8
--- /dev/null
+++ b/zephyr/test/drivers/default/src/integration/usbc/usb_pd_bist_shared.c
@@ -0,0 +1,193 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/ztest.h>
+
+#include "emul/emul_isl923x.h"
+#include "emul/emul_smart_battery.h"
+#include "emul/tcpc/emul_tcpci_partner_snk.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "usb_common.h"
+#include "usb_pd.h"
+#include "util.h"
+
+struct usb_pd_bist_shared_fixture {
+	struct tcpci_partner_data sink_5v_500ma;
+	struct tcpci_snk_emul_data snk_ext_500ma;
+	struct tcpci_partner_data src;
+	struct tcpci_src_emul_data src_ext;
+	const struct emul *tcpci_emul; /* USBC_PORT_C0 in dts */
+	const struct emul *tcpci_ps8xxx_emul; /* USBC_PORT_C1 in dts */
+	const struct emul *charger_emul;
+};
+
+static void *usb_pd_bist_shared_setup(void)
+{
+	static struct usb_pd_bist_shared_fixture test_fixture;
+
+	/* Get references for the emulators */
+	test_fixture.tcpci_emul = EMUL_GET_USBC_BINDING(0, tcpc);
+	test_fixture.charger_emul = EMUL_GET_USBC_BINDING(0, chg);
+	test_fixture.tcpci_ps8xxx_emul = EMUL_GET_USBC_BINDING(1, tcpc);
+
+	return &test_fixture;
+}
+
+static void usb_pd_bist_shared_before(void *data)
+{
+	struct usb_pd_bist_shared_fixture *test_fixture = data;
+
+	/* Set chipset to ON, this will set TCPM to DRP */
+	test_set_chipset_to_s0();
+
+	/* TODO(b/214401892): Check why need to give time TCPM to spin */
+	k_sleep(K_SECONDS(1));
+
+	/* Initialized the sink to request 5V and 500mA */
+	tcpci_partner_init(&test_fixture->sink_5v_500ma, PD_REV30);
+	test_fixture->sink_5v_500ma.extensions =
+		tcpci_snk_emul_init(&test_fixture->snk_ext_500ma,
+				    &test_fixture->sink_5v_500ma, NULL);
+	test_fixture->snk_ext_500ma.pdo[0] = PDO_FIXED(5000, 500, 0);
+
+	/* Initialized the source */
+	tcpci_partner_init(&test_fixture->src, PD_REV30);
+	test_fixture->src.extensions = tcpci_src_emul_init(
+		&test_fixture->src_ext, &test_fixture->src, NULL);
+
+	/* Initially connect the 5V 500mA partner to C0 */
+	connect_sink_to_port(&test_fixture->sink_5v_500ma,
+			     test_fixture->tcpci_emul,
+			     test_fixture->charger_emul);
+}
+
+static void usb_pd_bist_shared_after(void *data)
+{
+	struct usb_pd_bist_shared_fixture *test_fixture = data;
+
+	/* Disocnnect C0 as sink, C1 as source */
+	disconnect_sink_from_port(test_fixture->tcpci_emul);
+	disconnect_source_from_port(test_fixture->tcpci_ps8xxx_emul,
+				    test_fixture->charger_emul);
+}
+
+ZTEST_SUITE(usb_pd_bist_shared, drivers_predicate_post_main,
+	    usb_pd_bist_shared_setup, usb_pd_bist_shared_before,
+	    usb_pd_bist_shared_after, NULL);
+
+ZTEST_F(usb_pd_bist_shared, verify_bist_shared_mode)
+{
+	uint32_t bist_data;
+	uint32_t f5v_cap;
+
+	/*
+	 * Verify we were offered the 1.5A source cap because of our low current
+	 * needs initially
+	 */
+	f5v_cap = fixture->snk_ext_500ma.last_5v_source_cap;
+	/* Capability should be 5V fixed, 1.5 A */
+	zassert_equal((f5v_cap & PDO_TYPE_MASK), PDO_TYPE_FIXED,
+		      "PDO type wrong");
+	zassert_equal(PDO_FIXED_VOLTAGE(f5v_cap), 5000, "PDO voltage wrong");
+	zassert_equal(PDO_FIXED_CURRENT(f5v_cap), 1500,
+		      "PDO initial current wrong");
+
+	/* Start up BIST shared test mode */
+	bist_data = BDO(BDO_MODE_SHARED_ENTER, 0);
+	zassume_ok(tcpci_partner_send_data_msg(&fixture->sink_5v_500ma,
+					       PD_DATA_BIST, &bist_data, 1, 0),
+		   "Failed to send BIST enter message");
+
+	/* The DUT has tBISTSharedTestMode (1 second) to offer us 3A now */
+	k_sleep(K_SECONDS(1));
+
+	f5v_cap = fixture->snk_ext_500ma.last_5v_source_cap;
+	/* Capability should be 5V fixed, 3.0 A */
+	zassert_equal((f5v_cap & PDO_TYPE_MASK), PDO_TYPE_FIXED,
+		      "PDO type wrong");
+	zassert_equal(PDO_FIXED_VOLTAGE(f5v_cap), 5000, "PDO voltage wrong");
+	zassert_equal(PDO_FIXED_CURRENT(f5v_cap), 3000,
+		      "PDO current didn't increase in BIST mode");
+
+	/* Leave BIST shared test mode */
+	bist_data = BDO(BDO_MODE_SHARED_EXIT, 0);
+	zassume_ok(tcpci_partner_send_data_msg(&fixture->sink_5v_500ma,
+					       PD_DATA_BIST, &bist_data, 1, 0),
+		   "Failed to send BIST exit message");
+
+	/*
+	 * The DUT may now execute ErrorRecovery or simply send a new
+	 * Source_Cap.  Either way, we should go back to 1.5 A
+	 */
+	k_sleep(K_SECONDS(5));
+
+	f5v_cap = fixture->snk_ext_500ma.last_5v_source_cap;
+	/* Capability should be 5V fixed, 1.5 A */
+	zassert_equal((f5v_cap & PDO_TYPE_MASK), PDO_TYPE_FIXED,
+		      "PDO type wrong");
+	zassert_equal(PDO_FIXED_VOLTAGE(f5v_cap), 5000, "PDO voltage wrong");
+	zassert_equal(PDO_FIXED_CURRENT(f5v_cap), 1500,
+		      "PDO current didn't decrease after BIST exit");
+}
+
+ZTEST_F(usb_pd_bist_shared, verify_bist_shared_no_snk_entry)
+{
+	uint32_t bist_data;
+	uint32_t f5v_cap;
+
+	/*
+	 * Ensure we only enter BIST shared mode when acting as a source.  We
+	 * must not enter shared mode from PE_SNK_Ready.
+	 */
+
+	/* Attach a new source */
+	connect_source_to_port(&fixture->src, &fixture->src_ext, 1,
+			       fixture->tcpci_ps8xxx_emul,
+			       fixture->charger_emul);
+
+	/* Have the source send the BIST Enter Mode */
+	bist_data = BDO(BDO_MODE_SHARED_ENTER, 0);
+	zassume_ok(tcpci_partner_send_data_msg(&fixture->src, PD_DATA_BIST,
+					       &bist_data, 1, 0),
+		   "Failed to send BIST enter message");
+
+	/* Wait tBISTSharedTestMode (1 second) */
+	k_sleep(K_SECONDS(1));
+
+	/* Verify our low power sink on C0 still only has 1.5 A */
+	f5v_cap = fixture->snk_ext_500ma.last_5v_source_cap;
+	/* Capability should be 5V fixed, 1.5 A */
+	zassert_equal((f5v_cap & PDO_TYPE_MASK), PDO_TYPE_FIXED,
+		      "PDO type wrong");
+	zassert_equal(PDO_FIXED_VOLTAGE(f5v_cap), 5000, "PDO voltage wrong");
+	zassert_equal(PDO_FIXED_CURRENT(f5v_cap), 1500,
+		      "PDO current incorrect after bad BIST entry");
+}
+
+ZTEST_F(usb_pd_bist_shared, verify_bist_shared_exit_no_action)
+{
+	uint32_t bist_data;
+	uint32_t f5v_cap;
+
+	/*
+	 * Verify that if we receive a BIST shared mode exit with no entry, we
+	 * take no action on the port.
+	 */
+	tcpci_snk_emul_clear_last_5v_cap(&fixture->snk_ext_500ma);
+
+	bist_data = BDO(BDO_MODE_SHARED_EXIT, 0);
+	zassume_ok(tcpci_partner_send_data_msg(&fixture->sink_5v_500ma,
+					       PD_DATA_BIST, &bist_data, 1, 0),
+		   "Failed to send BIST exit message");
+
+	/* Wait for the time it would take to settle out exit */
+	k_sleep(K_SECONDS(5));
+
+	/* Verify we didn't receive any new source caps due to the mode exit */
+	f5v_cap = fixture->snk_ext_500ma.last_5v_source_cap;
+	zassert_equal(f5v_cap, 0, "Received unexpected source cap");
+}
diff --git a/zephyr/test/drivers/src/integration/usbc/usb_pd_ctrl_msg.c b/zephyr/test/drivers/default/src/integration/usbc/usb_pd_ctrl_msg.c
index dd4c805590..894deaed13 100644
--- a/zephyr/test/drivers/src/integration/usbc/usb_pd_ctrl_msg.c
+++ b/zephyr/test/drivers/default/src/integration/usbc/usb_pd_ctrl_msg.c
@@ -1,10 +1,10 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include <stdint.h>
-#include <ztest.h>
+#include <zephyr/ztest.h>
 
 #include "common.h"
 #include "ec_tasks.h"
@@ -17,9 +17,8 @@
 #include "test/usb_pe.h"
 #include "usb_pd.h"
 
-#define TEST_USB_PORT USBC_PORT_C0
-
-#define TCPCI_EMUL_LABEL DT_NODELABEL(tcpci_emul)
+#define TEST_USB_PORT 0
+BUILD_ASSERT(TEST_USB_PORT == USBC_PORT_C0);
 
 #define TEST_ADDED_PDO PDO_FIXED(10000, 3000, PDO_FIXED_UNCONSTRAINED)
 
@@ -41,10 +40,10 @@ struct usb_pd_ctrl_msg_test_source_fixture {
 	struct usb_pd_ctrl_msg_test_fixture fixture;
 };
 
-static void tcpci_drp_emul_connect_partner(
-	struct tcpci_partner_data *partner_emul,
-	const struct emul *tcpci_emul,
-	const struct emul *charger_emul)
+static void
+tcpci_drp_emul_connect_partner(struct tcpci_partner_data *partner_emul,
+			       const struct emul *tcpci_emul,
+			       const struct emul *charger_emul)
 {
 	/*
 	 * TODO(b/221439302) Updating the TCPCI emulator registers, updating the
@@ -75,12 +74,8 @@ static void *usb_pd_ctrl_msg_setup_emul(void)
 	static struct usb_pd_ctrl_msg_test_fixture fixture;
 
 	/* Get references for the emulators */
-	fixture.tcpci_emul =
-		emul_get_binding(DT_LABEL(DT_NODELABEL(tcpci_emul)));
-	fixture.charger_emul =
-		emul_get_binding(DT_LABEL(DT_NODELABEL(isl923x_emul)));
-
-	tcpci_emul_set_rev(fixture.tcpci_emul, TCPCI_EMUL_REV2_0_VER1_1);
+	fixture.tcpci_emul = EMUL_GET_USBC_BINDING(TEST_USB_PORT, tcpc);
+	fixture.charger_emul = EMUL_GET_USBC_BINDING(TEST_USB_PORT, chg);
 
 	return &fixture;
 }
@@ -122,15 +117,13 @@ static void usb_pd_ctrl_msg_before(void *data)
 
 	/* Initialized DRP */
 	tcpci_partner_init(&fixture->partner_emul, PD_REV20);
-	fixture->partner_emul.extensions =
-		tcpci_drp_emul_init(&fixture->drp_ext, &fixture->partner_emul,
-				    fixture->drp_partner_pd_role,
-				    tcpci_src_emul_init(&fixture->src_ext,
-							&fixture->partner_emul,
-							NULL),
-				    tcpci_snk_emul_init(&fixture->snk_ext,
-							&fixture->partner_emul,
-							NULL));
+	fixture->partner_emul.extensions = tcpci_drp_emul_init(
+		&fixture->drp_ext, &fixture->partner_emul,
+		fixture->drp_partner_pd_role,
+		tcpci_src_emul_init(&fixture->src_ext, &fixture->partner_emul,
+				    NULL),
+		tcpci_snk_emul_init(&fixture->snk_ext, &fixture->partner_emul,
+				    NULL));
 	/* Add additional Sink PDO to partner to verify
 	 * PE_DR_SNK_Get_Sink_Cap/PE_SRC_Get_Sink_Cap (these are shared PE
 	 * states) state was reached
@@ -166,7 +159,7 @@ ZTEST_SUITE(usb_pd_ctrl_msg_test_source, drivers_predicate_post_main,
 
 ZTEST_F(usb_pd_ctrl_msg_test_sink, verify_vconn_swap)
 {
-	struct usb_pd_ctrl_msg_test_fixture *fixture = &this->fixture;
+	struct usb_pd_ctrl_msg_test_fixture *super_fixture = &fixture->fixture;
 	struct ec_response_typec_status snk_resp = { 0 };
 	int rv = 0;
 
@@ -176,7 +169,7 @@ ZTEST_F(usb_pd_ctrl_msg_test_sink, verify_vconn_swap)
 		      "SNK Returned vconn_role=%u", snk_resp.vconn_role);
 
 	/* Send VCONN_SWAP request */
-	rv = tcpci_partner_send_control_msg(&fixture->partner_emul,
+	rv = tcpci_partner_send_control_msg(&super_fixture->partner_emul,
 					    PD_CTRL_VCONN_SWAP, 0);
 	zassert_ok(rv, "Failed to send VCONN_SWAP request, rv=%d", rv);
 
@@ -189,7 +182,7 @@ ZTEST_F(usb_pd_ctrl_msg_test_sink, verify_vconn_swap)
 
 ZTEST_F(usb_pd_ctrl_msg_test_sink, verify_pr_swap)
 {
-	struct usb_pd_ctrl_msg_test_fixture *fixture = &this->fixture;
+	struct usb_pd_ctrl_msg_test_fixture *super_fixture = &fixture->fixture;
 	struct ec_response_typec_status snk_resp = { 0 };
 	int rv = 0;
 
@@ -201,16 +194,16 @@ ZTEST_F(usb_pd_ctrl_msg_test_sink, verify_pr_swap)
 	/* Ignore ACCEPT in common handler for PR Swap request,
 	 * causes soft reset
 	 */
-	tcpci_partner_common_handler_mask_msg(&fixture->partner_emul,
+	tcpci_partner_common_handler_mask_msg(&super_fixture->partner_emul,
 					      PD_CTRL_ACCEPT, true);
 
 	/* Send PR_SWAP request */
-	rv = tcpci_partner_send_control_msg(&fixture->partner_emul,
+	rv = tcpci_partner_send_control_msg(&super_fixture->partner_emul,
 					    PD_CTRL_PR_SWAP, 0);
 	zassert_ok(rv, "Failed to send PR_SWAP request, rv=%d", rv);
 
 	/* Send PS_RDY request */
-	rv = tcpci_partner_send_control_msg(&fixture->partner_emul,
+	rv = tcpci_partner_send_control_msg(&super_fixture->partner_emul,
 					    PD_CTRL_PS_RDY, 15);
 	zassert_ok(rv, "Failed to send PS_RDY request, rv=%d", rv);
 
@@ -255,7 +248,7 @@ ZTEST_F(usb_pd_ctrl_msg_test_sink, verify_dr_swap)
  */
 ZTEST_F(usb_pd_ctrl_msg_test_source, verify_dr_swap_rejected)
 {
-	struct usb_pd_ctrl_msg_test_fixture *fixture = &this->fixture;
+	struct usb_pd_ctrl_msg_test_fixture *super_fixture = &fixture->fixture;
 	struct ec_response_typec_status typec_status = { 0 };
 	int rv = 0;
 
@@ -264,7 +257,7 @@ ZTEST_F(usb_pd_ctrl_msg_test_source, verify_dr_swap_rejected)
 		      "Returned data_role=%u", typec_status.data_role);
 
 	/* Send DR_SWAP request */
-	rv = tcpci_partner_send_control_msg(&fixture->partner_emul,
+	rv = tcpci_partner_send_control_msg(&super_fixture->partner_emul,
 					    PD_CTRL_DR_SWAP, 0);
 	zassert_ok(rv, "Failed to send DR_SWAP request, rv=%d", rv);
 
@@ -359,11 +352,11 @@ ZTEST(usb_pd_ctrl_msg_test_sink, verify_get_sink_cap)
  */
 ZTEST_F(usb_pd_ctrl_msg_test_source, verify_bist_tx_mode2)
 {
-	struct usb_pd_ctrl_msg_test_fixture *fixture = &this->fixture;
+	struct usb_pd_ctrl_msg_test_fixture *super_fixture = &fixture->fixture;
 	uint32_t bdo = BDO(BDO_MODE_CARRIER2, 0);
 
-	tcpci_partner_send_data_msg(&fixture->partner_emul,
-				    PD_DATA_BIST, &bdo, 1, 0);
+	tcpci_partner_send_data_msg(&super_fixture->partner_emul, PD_DATA_BIST,
+				    &bdo, 1, 0);
 
 	pd_dpm_request(TEST_USB_PORT, DPM_REQUEST_BIST_TX);
 	k_sleep(K_MSEC(10));
@@ -386,17 +379,17 @@ ZTEST_F(usb_pd_ctrl_msg_test_source, verify_bist_tx_mode2)
  */
 ZTEST_F(usb_pd_ctrl_msg_test_source, verify_bist_tx_test_data)
 {
-	struct usb_pd_ctrl_msg_test_fixture *fixture = &this->fixture;
+	struct usb_pd_ctrl_msg_test_fixture *super_fixture = &fixture->fixture;
 	uint32_t bdo = BDO(BDO_MODE_TEST_DATA, 0);
 
-	tcpci_partner_send_data_msg(&fixture->partner_emul,
-				    PD_DATA_BIST, &bdo, 1, 0);
+	tcpci_partner_send_data_msg(&super_fixture->partner_emul, PD_DATA_BIST,
+				    &bdo, 1, 0);
 
 	pd_dpm_request(TEST_USB_PORT, DPM_REQUEST_BIST_TX);
 	k_sleep(K_SECONDS(5));
 	zassert_equal(get_state_pe(TEST_USB_PORT), PE_BIST_TX, NULL);
 
-	tcpci_partner_common_send_hard_reset(&fixture->partner_emul);
+	tcpci_partner_common_send_hard_reset(&super_fixture->partner_emul);
 	k_sleep(K_SECONDS(1));
 	zassert_equal(get_state_pe(TEST_USB_PORT), PE_SNK_READY, NULL);
 }
diff --git a/zephyr/test/drivers/default/src/integration/usbc/usb_pd_rev3.c b/zephyr/test/drivers/default/src/integration/usbc/usb_pd_rev3.c
new file mode 100644
index 0000000000..fbe634a838
--- /dev/null
+++ b/zephyr/test/drivers/default/src/integration/usbc/usb_pd_rev3.c
@@ -0,0 +1,358 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/ztest.h>
+
+#include "battery.h"
+#include "battery_smart.h"
+#include "chipset.h"
+#include "emul/emul_isl923x.h"
+#include "emul/emul_smart_battery.h"
+#include "emul/tcpc/emul_tcpci_partner_src.h"
+#include "hooks.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "usb_common.h"
+#include "usb_pd.h"
+#include "util.h"
+
+struct usb_attach_5v_3a_pd_source_rev3_fixture {
+	struct tcpci_partner_data source_5v_3a;
+	struct tcpci_src_emul_data src_ext;
+	const struct emul *tcpci_emul;
+	const struct emul *charger_emul;
+};
+
+static void *usb_attach_5v_3a_pd_source_setup(void)
+{
+	static struct usb_attach_5v_3a_pd_source_rev3_fixture test_fixture;
+
+	/* Get references for the emulators */
+	test_fixture.tcpci_emul = EMUL_GET_USBC_BINDING(0, tcpc);
+	test_fixture.charger_emul = EMUL_GET_USBC_BINDING(0, chg);
+
+	/* Initialized the charger to supply 5V and 3A */
+	tcpci_partner_init(&test_fixture.source_5v_3a, PD_REV30);
+	test_fixture.source_5v_3a.extensions = tcpci_src_emul_init(
+		&test_fixture.src_ext, &test_fixture.source_5v_3a, NULL);
+	test_fixture.src_ext.pdo[1] =
+		PDO_FIXED(5000, 3000, PDO_FIXED_UNCONSTRAINED);
+
+	return &test_fixture;
+}
+
+static void usb_attach_5v_3a_pd_source_before(void *data)
+{
+	struct usb_attach_5v_3a_pd_source_rev3_fixture *fixture = data;
+
+	connect_source_to_port(&fixture->source_5v_3a, &fixture->src_ext, 1,
+			       fixture->tcpci_emul, fixture->charger_emul);
+
+	/* Clear Alert and Status receive checks */
+	tcpci_src_emul_clear_alert_received(&fixture->src_ext);
+	tcpci_src_emul_clear_status_received(&fixture->src_ext);
+	zassume_false(fixture->src_ext.alert_received, NULL);
+	zassume_false(fixture->src_ext.status_received, NULL);
+
+	/* Initial check on power state */
+	zassume_true(chipset_in_state(CHIPSET_STATE_ON), NULL);
+}
+
+static void usb_attach_5v_3a_pd_source_after(void *data)
+{
+	struct usb_attach_5v_3a_pd_source_rev3_fixture *fixture = data;
+
+	disconnect_source_from_port(fixture->tcpci_emul, fixture->charger_emul);
+}
+
+ZTEST_SUITE(usb_attach_5v_3a_pd_source_rev3, drivers_predicate_post_main,
+	    usb_attach_5v_3a_pd_source_setup, usb_attach_5v_3a_pd_source_before,
+	    usb_attach_5v_3a_pd_source_after, NULL);
+
+ZTEST_F(usb_attach_5v_3a_pd_source_rev3, test_batt_cap)
+{
+	int battery_index = 0;
+
+	tcpci_partner_common_send_get_battery_capabilities(
+		&fixture->source_5v_3a, battery_index);
+
+	/* Allow some time for TCPC to process and respond */
+	k_sleep(K_SECONDS(1));
+
+	zassert_true(fixture->source_5v_3a.battery_capabilities
+			     .have_response[battery_index],
+		     "No battery capabilities response stored.");
+
+	/* The response */
+	struct pd_bcdb *bcdb =
+		&fixture->source_5v_3a.battery_capabilities.bcdb[battery_index];
+
+	zassert_equal(USB_VID_GOOGLE, bcdb->vid, "Incorrect battery VID");
+	zassert_equal(CONFIG_USB_PID, bcdb->pid, "Incorrect battery PID");
+	zassert_false((bcdb->battery_type) & BIT(0),
+		      "Invalid battery ref bit should not be set");
+
+	/* Verify the battery capacity and last full charge capacity. These
+	 * fields require that the battery is present and that we can
+	 * access information about the nominal voltage and capacity.
+	 *
+	 * TODO(b/237427945): Add test for case when battery is not present
+	 */
+
+	/* See pe_give_battery_cap_entry() in common/usbc/usb_pe_drp_sm.c */
+
+	zassume_true(battery_is_present(), "Battery must be present");
+	zassume_true(IS_ENABLED(HAS_TASK_HOSTCMD) &&
+			     *host_get_memmap(EC_MEMMAP_BATTERY_VERSION) != 0,
+		     "Cannot access battery data");
+
+	/* Millivolts */
+	int design_volt = *(int *)host_get_memmap(EC_MEMMAP_BATT_DVLT);
+
+	/* Milliamphours */
+	int design_cap = *(int *)host_get_memmap(EC_MEMMAP_BATT_DCAP);
+	int full_cap = *(int *)host_get_memmap(EC_MEMMAP_BATT_LFCC);
+
+	/* Multiply millivolts by milliamphours and scale to deciwatthours
+	 * (0.1 Wh), the unit of energy used in the PD messages.
+	 */
+
+	int expected_design_cap =
+		DIV_ROUND_NEAREST((design_cap * design_volt), 1000 * 1000 / 10);
+
+	int expected_last_charge_cap =
+		DIV_ROUND_NEAREST((design_cap * full_cap), 1000 * 1000 / 10);
+
+	zassert_equal(expected_design_cap, bcdb->design_cap,
+		      "Design capacity not correct. Expected %d but got %d",
+		      expected_design_cap, bcdb->design_cap);
+	zassert_equal(
+		expected_last_charge_cap, bcdb->last_full_charge_cap,
+		"Last full charge capacity not correct. Expected %d but got %d",
+		expected_last_charge_cap, bcdb->last_full_charge_cap);
+}
+
+ZTEST_F(usb_attach_5v_3a_pd_source_rev3, test_batt_cap_invalid)
+{
+	/* Request data on a battery that does not exist. The PD stack only
+	 * supports battery 0.
+	 */
+
+	int battery_index = 5;
+
+	tcpci_partner_common_send_get_battery_capabilities(
+		&fixture->source_5v_3a, battery_index);
+
+	/* Allow some time for TCPC to process and respond */
+	k_sleep(K_SECONDS(1));
+
+	/* Ensure we get a response that says our battery index was invalid */
+
+	zassert_true(fixture->source_5v_3a.battery_capabilities
+			     .have_response[battery_index],
+		     "No battery capabilities response stored.");
+	zassert_true(
+		(fixture->source_5v_3a.battery_capabilities.bcdb[battery_index]
+			 .battery_type) &
+			BIT(0),
+		"Invalid battery ref bit should be set");
+}
+
+ZTEST_F(usb_attach_5v_3a_pd_source_rev3, verify_alert_msg)
+{
+	zassume_equal(pd_broadcast_alert_msg(ADO_OTP_EVENT), EC_SUCCESS, NULL);
+
+	k_sleep(K_SECONDS(2));
+	zassert_true(fixture->src_ext.alert_received, NULL);
+}
+
+ZTEST_F(usb_attach_5v_3a_pd_source_rev3, verify_alert_on_power_state_change)
+{
+	/* Suspend and check partner received Alert and Status messages */
+	hook_notify(HOOK_CHIPSET_SUSPEND);
+	k_sleep(K_SECONDS(2));
+	zassert_true(fixture->src_ext.alert_received, NULL);
+	zassert_true(fixture->src_ext.status_received, NULL);
+	tcpci_src_emul_clear_alert_received(&fixture->src_ext);
+	tcpci_src_emul_clear_status_received(&fixture->src_ext);
+	zassume_false(fixture->src_ext.alert_received, NULL);
+	zassume_false(fixture->src_ext.status_received, NULL);
+
+	/* Shutdown and check partner received Alert and Status messages */
+	hook_notify(HOOK_CHIPSET_SHUTDOWN);
+	k_sleep(K_SECONDS(2));
+	zassert_true(fixture->src_ext.alert_received, NULL);
+	zassert_true(fixture->src_ext.status_received, NULL);
+	tcpci_src_emul_clear_alert_received(&fixture->src_ext);
+	tcpci_src_emul_clear_status_received(&fixture->src_ext);
+	zassume_false(fixture->src_ext.alert_received, NULL);
+	zassume_false(fixture->src_ext.status_received, NULL);
+
+	/* Startup and check partner received Alert and Status messages */
+	hook_notify(HOOK_CHIPSET_STARTUP);
+	k_sleep(K_SECONDS(2));
+	zassert_true(fixture->src_ext.alert_received, NULL);
+	zassert_true(fixture->src_ext.status_received, NULL);
+	tcpci_src_emul_clear_alert_received(&fixture->src_ext);
+	tcpci_src_emul_clear_status_received(&fixture->src_ext);
+	zassume_false(fixture->src_ext.alert_received, NULL);
+	zassume_false(fixture->src_ext.status_received, NULL);
+
+	/* Resume and check partner received Alert and Status messages */
+	hook_notify(HOOK_CHIPSET_RESUME);
+	k_sleep(K_SECONDS(2));
+	zassert_true(fixture->src_ext.alert_received, NULL);
+	zassert_true(fixture->src_ext.status_received, NULL);
+}
+
+ZTEST_F(usb_attach_5v_3a_pd_source_rev3,
+	verify_inaction_on_pd_button_press_while_awake)
+{
+	uint32_t ado;
+
+	/* While awake expect nothing on valid press */
+	ado = ADO_EXTENDED_ALERT_EVENT | ADO_POWER_BUTTON_PRESS;
+	tcpci_partner_send_data_msg(&fixture->source_5v_3a, PD_DATA_ALERT, &ado,
+				    1, 0);
+	k_sleep(K_SECONDS(2));
+	ado = ADO_EXTENDED_ALERT_EVENT | ADO_POWER_BUTTON_RELEASE;
+	tcpci_partner_send_data_msg(&fixture->source_5v_3a, PD_DATA_ALERT, &ado,
+				    1, 0);
+	k_sleep(K_SECONDS(2));
+	zassert_false(fixture->src_ext.alert_received, NULL);
+	zassert_false(fixture->src_ext.status_received, NULL);
+	zassert_true(chipset_in_state(CHIPSET_STATE_ON), NULL);
+}
+
+ZTEST_F(usb_attach_5v_3a_pd_source_rev3,
+	verify_inaction_on_invalid_pd_button_press)
+{
+	uint32_t ado;
+
+	/* Shutdown device to test wake from USB PD power button */
+	chipset_force_shutdown(CHIPSET_SHUTDOWN_BUTTON);
+	k_sleep(K_SECONDS(10));
+
+	/* Clear alert and status flags set during shutdown */
+	tcpci_src_emul_clear_alert_received(&fixture->src_ext);
+	tcpci_src_emul_clear_status_received(&fixture->src_ext);
+	zassume_false(fixture->src_ext.alert_received, NULL);
+	zassume_false(fixture->src_ext.status_received, NULL);
+	zassume_true(chipset_in_state(CHIPSET_STATE_ANY_OFF), NULL);
+
+	/* While in S5/G3 expect nothing on invalid (too long) press */
+	ado = ADO_EXTENDED_ALERT_EVENT | ADO_POWER_BUTTON_PRESS;
+	tcpci_partner_send_data_msg(&fixture->source_5v_3a, PD_DATA_ALERT, &ado,
+				    1, 0);
+	k_sleep(K_SECONDS(10));
+	ado = ADO_EXTENDED_ALERT_EVENT | ADO_POWER_BUTTON_RELEASE;
+	tcpci_partner_send_data_msg(&fixture->source_5v_3a, PD_DATA_ALERT, &ado,
+				    1, 0);
+	k_sleep(K_SECONDS(2));
+	zassert_false(fixture->src_ext.alert_received, NULL);
+	zassert_false(fixture->src_ext.status_received, NULL);
+	zassert_true(chipset_in_state(CHIPSET_STATE_ANY_OFF), NULL);
+
+	/* Wake device to setup for subsequent tests */
+	chipset_power_on();
+	k_sleep(K_SECONDS(10));
+}
+
+ZTEST_F(usb_attach_5v_3a_pd_source_rev3, verify_startup_on_pd_button_press)
+{
+	uint32_t ado;
+
+	/* Shutdown device to test wake from USB PD power button */
+	chipset_force_shutdown(CHIPSET_SHUTDOWN_BUTTON);
+	k_sleep(K_SECONDS(10));
+
+	/* Clear alert and status flags set during shutdown */
+	tcpci_src_emul_clear_alert_received(&fixture->src_ext);
+	tcpci_src_emul_clear_status_received(&fixture->src_ext);
+	zassume_false(fixture->src_ext.alert_received, NULL);
+	zassume_false(fixture->src_ext.status_received, NULL);
+	zassume_true(chipset_in_state(CHIPSET_STATE_ANY_OFF), NULL);
+
+	/* While in S5/G3 expect Alert->Get_Status->Status on valid press */
+	ado = ADO_EXTENDED_ALERT_EVENT | ADO_POWER_BUTTON_PRESS;
+	tcpci_partner_send_data_msg(&fixture->source_5v_3a, PD_DATA_ALERT, &ado,
+				    1, 0);
+	k_sleep(K_SECONDS(2));
+	ado = ADO_EXTENDED_ALERT_EVENT | ADO_POWER_BUTTON_RELEASE;
+	tcpci_partner_send_data_msg(&fixture->source_5v_3a, PD_DATA_ALERT, &ado,
+				    1, 0);
+	k_sleep(K_SECONDS(2));
+	zassert_true(fixture->src_ext.alert_received, NULL);
+	zassert_true(fixture->src_ext.status_received, NULL);
+	zassert_true(chipset_in_state(CHIPSET_STATE_ON), NULL);
+}
+
+ZTEST_F(usb_attach_5v_3a_pd_source_rev3, verify_chipset_on_pd_button_behavior)
+{
+	uint32_t ado;
+
+	/* Expect no power state change on short press */
+	ado = ADO_EXTENDED_ALERT_EVENT | ADO_POWER_BUTTON_PRESS;
+	tcpci_partner_send_data_msg(&fixture->source_5v_3a, PD_DATA_ALERT, &ado,
+				    1, 0);
+	k_sleep(K_SECONDS(2));
+	ado = ADO_EXTENDED_ALERT_EVENT | ADO_POWER_BUTTON_RELEASE;
+	tcpci_partner_send_data_msg(&fixture->source_5v_3a, PD_DATA_ALERT, &ado,
+				    1, 0);
+	k_sleep(K_SECONDS(2));
+	zassert_false(fixture->src_ext.alert_received, NULL);
+	zassert_false(fixture->src_ext.status_received, NULL);
+	zassert_true(chipset_in_state(CHIPSET_STATE_ON), NULL);
+
+	/* Expect no change on invalid button press while chipset is on */
+	ado = ADO_EXTENDED_ALERT_EVENT | ADO_POWER_BUTTON_PRESS;
+	tcpci_partner_send_data_msg(&fixture->source_5v_3a, PD_DATA_ALERT, &ado,
+				    1, 0);
+	k_sleep(K_SECONDS(10));
+	ado = ADO_EXTENDED_ALERT_EVENT | ADO_POWER_BUTTON_RELEASE;
+	tcpci_partner_send_data_msg(&fixture->source_5v_3a, PD_DATA_ALERT, &ado,
+				    1, 0);
+	k_sleep(K_SECONDS(2));
+	zassert_false(fixture->src_ext.alert_received, NULL);
+	zassert_false(fixture->src_ext.status_received, NULL);
+	zassert_true(chipset_in_state(CHIPSET_STATE_ON), NULL);
+
+	/*
+	 * Expect no power state change on 6 second press->press->release due
+	 * to the timers resetting on the second press.
+	 */
+	ado = ADO_EXTENDED_ALERT_EVENT | ADO_POWER_BUTTON_PRESS;
+	tcpci_partner_send_data_msg(&fixture->source_5v_3a, PD_DATA_ALERT, &ado,
+				    1, 0);
+	k_sleep(K_SECONDS(3));
+	tcpci_partner_send_data_msg(&fixture->source_5v_3a, PD_DATA_ALERT, &ado,
+				    1, 0);
+	k_sleep(K_SECONDS(3));
+	ado = ADO_EXTENDED_ALERT_EVENT | ADO_POWER_BUTTON_RELEASE;
+	tcpci_partner_send_data_msg(&fixture->source_5v_3a, PD_DATA_ALERT, &ado,
+				    1, 0);
+	k_sleep(K_SECONDS(2));
+	zassert_false(fixture->src_ext.alert_received, NULL);
+	zassert_false(fixture->src_ext.status_received, NULL);
+	zassert_true(chipset_in_state(CHIPSET_STATE_ON), NULL);
+
+	/* Expect power state change on long press */
+	ado = ADO_EXTENDED_ALERT_EVENT | ADO_POWER_BUTTON_PRESS;
+	tcpci_partner_send_data_msg(&fixture->source_5v_3a, PD_DATA_ALERT, &ado,
+				    1, 0);
+	k_sleep(K_SECONDS(6));
+	ado = ADO_EXTENDED_ALERT_EVENT | ADO_POWER_BUTTON_RELEASE;
+	tcpci_partner_send_data_msg(&fixture->source_5v_3a, PD_DATA_ALERT, &ado,
+				    1, 0);
+	k_sleep(K_SECONDS(2));
+	zassert_true(fixture->src_ext.alert_received, NULL);
+	zassert_true(fixture->src_ext.status_received, NULL);
+	zassert_true(chipset_in_state(CHIPSET_STATE_ANY_OFF), NULL);
+
+	/* Wake device to setup for subsequent tests */
+	chipset_power_on();
+	k_sleep(K_SECONDS(10));
+}
diff --git a/zephyr/test/drivers/src/isl923x.c b/zephyr/test/drivers/default/src/isl923x.c
index 203a2ed979..9144730887 100644
--- a/zephyr/test/drivers/src/isl923x.c
+++ b/zephyr/test/drivers/default/src/isl923x.c
@@ -1,11 +1,11 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <ztest.h>
+#include <zephyr/ztest.h>
 #include <zephyr/drivers/emul.h>
-#include <fff.h>
+#include <zephyr/fff.h>
 
 #include "battery.h"
 #include "battery_smart.h"
@@ -45,9 +45,10 @@ BUILD_ASSERT(IS_ENABLED(CONFIG_CHARGER_ISL9238),
 #endif
 
 #define CHARGER_NUM get_charger_num(&isl923x_drv)
-#define ISL923X_EMUL emul_get_binding(DT_LABEL(DT_NODELABEL(isl923x_emul)))
+#define ISL923X_EMUL EMUL_DT_GET(DT_NODELABEL(isl923x_emul))
+#define COMMON_DATA emul_isl923x_get_i2c_common_data(ISL923X_EMUL)
 
-static int mock_write_fn_always_fail(struct i2c_emul *emul, int reg,
+static int mock_write_fn_always_fail(const struct emul *emul, int reg,
 				     uint8_t val, int bytes, void *data)
 {
 	ztest_test_fail();
@@ -56,8 +57,6 @@ static int mock_write_fn_always_fail(struct i2c_emul *emul, int reg,
 
 ZTEST(isl923x, test_isl923x_set_current)
 {
-	const struct emul *isl923x_emul = ISL923X_EMUL;
-	struct i2c_emul *i2c_emul = isl923x_emul_get_i2c_emul(isl923x_emul);
 	int expected_current_milli_amps[] = {
 		EXPECTED_CURRENT_MA(0),	   EXPECTED_CURRENT_MA(4),
 		EXPECTED_CURRENT_MA(8),	   EXPECTED_CURRENT_MA(16),
@@ -69,13 +68,13 @@ ZTEST(isl923x, test_isl923x_set_current)
 	int current_milli_amps;
 
 	/* Test I2C failure when reading charge current */
-	i2c_common_emul_set_read_fail_reg(i2c_emul, ISL923X_REG_CHG_CURRENT);
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, ISL923X_REG_CHG_CURRENT);
 	zassert_equal(EC_ERROR_INVAL,
 		      isl923x_drv.get_current(CHARGER_NUM, &current_milli_amps),
 		      NULL);
 
 	/* Reset fail register */
-	i2c_common_emul_set_read_fail_reg(i2c_emul,
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA,
 					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	for (int i = 0; i < ARRAY_SIZE(expected_current_milli_amps); ++i) {
@@ -129,43 +128,40 @@ ZTEST(isl923x, test_isl923x_set_voltage)
 
 ZTEST(isl923x, test_isl923x_set_input_current_limit)
 {
-	const struct emul *isl923x_emul = ISL923X_EMUL;
-	struct i2c_emul *i2c_emul = isl923x_emul_get_i2c_emul(isl923x_emul);
-	int expected_current_milli_amps[] = {
-		EXPECTED_INPUT_CURRENT_MA(0),
-		EXPECTED_INPUT_CURRENT_MA(4),
-		EXPECTED_INPUT_CURRENT_MA(8),
-		EXPECTED_INPUT_CURRENT_MA(16),
-		EXPECTED_INPUT_CURRENT_MA(32),
-		EXPECTED_INPUT_CURRENT_MA(64),
-		EXPECTED_INPUT_CURRENT_MA(128),
-		EXPECTED_INPUT_CURRENT_MA(256),
-		EXPECTED_INPUT_CURRENT_MA(512),
-		EXPECTED_INPUT_CURRENT_MA(1024),
-		EXPECTED_INPUT_CURRENT_MA(2048),
-		EXPECTED_INPUT_CURRENT_MA(4096) };
+	int expected_current_milli_amps[] = { EXPECTED_INPUT_CURRENT_MA(0),
+					      EXPECTED_INPUT_CURRENT_MA(4),
+					      EXPECTED_INPUT_CURRENT_MA(8),
+					      EXPECTED_INPUT_CURRENT_MA(16),
+					      EXPECTED_INPUT_CURRENT_MA(32),
+					      EXPECTED_INPUT_CURRENT_MA(64),
+					      EXPECTED_INPUT_CURRENT_MA(128),
+					      EXPECTED_INPUT_CURRENT_MA(256),
+					      EXPECTED_INPUT_CURRENT_MA(512),
+					      EXPECTED_INPUT_CURRENT_MA(1024),
+					      EXPECTED_INPUT_CURRENT_MA(2048),
+					      EXPECTED_INPUT_CURRENT_MA(4096) };
 	int current_milli_amps;
 
 	/* Test failing to write to current limit 1 reg */
-	i2c_common_emul_set_write_fail_reg(i2c_emul,
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA,
 					   ISL923X_REG_ADAPTER_CURRENT_LIMIT1);
 	zassert_equal(EC_ERROR_INVAL,
 		      isl923x_drv.set_input_current_limit(CHARGER_NUM, 0),
 		      NULL);
 
 	/* Test failing to write to current limit 2 reg */
-	i2c_common_emul_set_write_fail_reg(i2c_emul,
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA,
 					   ISL923X_REG_ADAPTER_CURRENT_LIMIT2);
 	zassert_equal(EC_ERROR_INVAL,
 		      isl923x_drv.set_input_current_limit(CHARGER_NUM, 0),
 		      NULL);
 
 	/* Reset fail register */
-	i2c_common_emul_set_write_fail_reg(i2c_emul,
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA,
 					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test failing to read current limit 1 reg */
-	i2c_common_emul_set_read_fail_reg(i2c_emul,
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA,
 					  ISL923X_REG_ADAPTER_CURRENT_LIMIT1);
 	zassert_equal(EC_ERROR_INVAL,
 		      isl923x_drv.get_input_current_limit(CHARGER_NUM,
@@ -173,7 +169,7 @@ ZTEST(isl923x, test_isl923x_set_input_current_limit)
 		      NULL);
 
 	/* Reset fail register */
-	i2c_common_emul_set_read_fail_reg(i2c_emul,
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA,
 					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test normal code path */
@@ -201,7 +197,6 @@ ZTEST(isl923x, test_isl923x_psys)
 ZTEST(isl923x, test_manufacturer_id)
 {
 	const struct emul *isl923x_emul = ISL923X_EMUL;
-	struct i2c_emul *i2c_emul = isl923x_emul_get_i2c_emul(isl923x_emul);
 	int id;
 
 	isl923x_emul_set_manufacturer_id(isl923x_emul, 0x1234);
@@ -209,20 +204,19 @@ ZTEST(isl923x, test_manufacturer_id)
 	zassert_equal(0x1234, id, NULL);
 
 	/* Test read error */
-	i2c_common_emul_set_read_fail_reg(i2c_emul,
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA,
 					  ISL923X_REG_MANUFACTURER_ID);
 	zassert_equal(EC_ERROR_INVAL,
 		      isl923x_drv.manufacturer_id(CHARGER_NUM, &id), NULL);
 
 	/* Reset fail register */
-	i2c_common_emul_set_read_fail_reg(i2c_emul,
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA,
 					  I2C_COMMON_EMUL_NO_FAIL_REG);
 }
 
 ZTEST(isl923x, test_device_id)
 {
 	const struct emul *isl923x_emul = ISL923X_EMUL;
-	struct i2c_emul *i2c_emul = isl923x_emul_get_i2c_emul(isl923x_emul);
 	int id;
 
 	isl923x_emul_set_device_id(isl923x_emul, 0x5678);
@@ -230,48 +224,45 @@ ZTEST(isl923x, test_device_id)
 	zassert_equal(0x5678, id, NULL);
 
 	/* Test read error */
-	i2c_common_emul_set_read_fail_reg(i2c_emul,
-					  ISL923X_REG_DEVICE_ID);
-	zassert_equal(EC_ERROR_INVAL,
-		      isl923x_drv.device_id(CHARGER_NUM, &id), NULL);
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, ISL923X_REG_DEVICE_ID);
+	zassert_equal(EC_ERROR_INVAL, isl923x_drv.device_id(CHARGER_NUM, &id),
+		      NULL);
 
 	/* Reset fail register */
-	i2c_common_emul_set_read_fail_reg(i2c_emul,
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA,
 					  I2C_COMMON_EMUL_NO_FAIL_REG);
 }
 
 ZTEST(isl923x, test_options)
 {
-	const struct emul *isl923x_emul = ISL923X_EMUL;
-	struct i2c_emul *i2c_emul = isl923x_emul_get_i2c_emul(isl923x_emul);
 	uint32_t option;
 
 	/* Test failed control 0 read */
-	i2c_common_emul_set_read_fail_reg(i2c_emul, ISL923X_REG_CONTROL0);
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, ISL923X_REG_CONTROL0);
 	zassert_equal(EC_ERROR_INVAL,
 		      isl923x_drv.get_option(CHARGER_NUM, &option), NULL);
 
 	/* Test failed control 1 read */
-	i2c_common_emul_set_read_fail_reg(i2c_emul, ISL923X_REG_CONTROL1);
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, ISL923X_REG_CONTROL1);
 	zassert_equal(EC_ERROR_INVAL,
 		      isl923x_drv.get_option(CHARGER_NUM, &option), NULL);
 
 	/* Reset failed read */
-	i2c_common_emul_set_read_fail_reg(i2c_emul,
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA,
 					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test failed control 0 write */
-	i2c_common_emul_set_write_fail_reg(i2c_emul, ISL923X_REG_CONTROL0);
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA, ISL923X_REG_CONTROL0);
 	zassert_equal(EC_ERROR_INVAL,
 		      isl923x_drv.set_option(CHARGER_NUM, option), NULL);
 
 	/* Test failed control 1 write */
-	i2c_common_emul_set_write_fail_reg(i2c_emul, ISL923X_REG_CONTROL1);
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA, ISL923X_REG_CONTROL1);
 	zassert_equal(EC_ERROR_INVAL,
 		      isl923x_drv.set_option(CHARGER_NUM, option), NULL);
 
 	/* Reset failed write */
-	i2c_common_emul_set_write_fail_reg(i2c_emul,
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA,
 					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test normal write/read, note that bits 23 and 0 are always 0 */
@@ -335,7 +326,6 @@ ZTEST(isl923x, test_set_ac_prochot)
 {
 	const struct emul *isl923x_emul = ISL923X_EMUL;
 	const struct device *i2c_dev = isl923x_emul_get_parent(isl923x_emul);
-	struct i2c_emul *i2c_emul = isl923x_emul_get_i2c_emul(isl923x_emul);
 	uint16_t expected_current_milli_amps[] = {
 		EXPECTED_INPUT_CURRENT_MA(0),
 		EXPECTED_INPUT_CURRENT_MA(128),
@@ -354,12 +344,12 @@ ZTEST(isl923x, test_set_ac_prochot)
 		      NULL);
 
 	/* Test failed I2C write to prochot register */
-	i2c_common_emul_set_write_fail_reg(i2c_emul, ISL923X_REG_PROCHOT_AC);
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA, ISL923X_REG_PROCHOT_AC);
 	zassert_equal(EC_ERROR_INVAL, isl923x_set_ac_prochot(CHARGER_NUM, 0),
 		      NULL);
 
 	/* Clear write fail reg */
-	i2c_common_emul_set_write_fail_reg(i2c_emul,
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA,
 					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	for (int i = 0; i < ARRAY_SIZE(expected_current_milli_amps); ++i) {
@@ -379,8 +369,9 @@ ZTEST(isl923x, test_set_ac_prochot)
 				   CHARGER_NUM, expected_current_milli_amps[i]),
 			   "Failed to set AC prochot to %dmA",
 			   expected_current_milli_amps[i]);
-		zassert_ok(i2c_write_read(i2c_dev, i2c_emul->addr, &reg_addr,
-					  sizeof(reg_addr), &current_milli_amps,
+		zassert_ok(i2c_write_read(i2c_dev, isl923x_emul->bus.i2c->addr,
+					  &reg_addr, sizeof(reg_addr),
+					  &current_milli_amps,
 					  sizeof(current_milli_amps)),
 			   "Failed to read AC prochot register");
 		zassert_equal(EXPECTED_INPUT_CURRENT_REG(
@@ -396,7 +387,6 @@ ZTEST(isl923x, test_set_dc_prochot)
 {
 	const struct emul *isl923x_emul = ISL923X_EMUL;
 	const struct device *i2c_dev = isl923x_emul_get_parent(isl923x_emul);
-	struct i2c_emul *i2c_emul = isl923x_emul_get_i2c_emul(isl923x_emul);
 	uint16_t expected_current_milli_amps[] = {
 		EXPECTED_CURRENT_MA(256),  EXPECTED_CURRENT_MA(512),
 		EXPECTED_CURRENT_MA(1024), EXPECTED_CURRENT_MA(2048),
@@ -411,12 +401,12 @@ ZTEST(isl923x, test_set_dc_prochot)
 		      NULL);
 
 	/* Test failed I2C write to prochot register */
-	i2c_common_emul_set_write_fail_reg(i2c_emul, ISL923X_REG_PROCHOT_DC);
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA, ISL923X_REG_PROCHOT_DC);
 	zassert_equal(EC_ERROR_INVAL, isl923x_set_dc_prochot(CHARGER_NUM, 0),
 		      NULL);
 
 	/* Clear write fail reg */
-	i2c_common_emul_set_write_fail_reg(i2c_emul,
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA,
 					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	for (int i = 0; i < ARRAY_SIZE(expected_current_milli_amps); ++i) {
@@ -435,8 +425,9 @@ ZTEST(isl923x, test_set_dc_prochot)
 				   CHARGER_NUM, expected_current_milli_amps[i]),
 			   "Failed to set DC prochot to %dmA",
 			   expected_current_milli_amps[i]);
-		zassert_ok(i2c_write_read(i2c_dev, i2c_emul->addr, &reg_addr,
-					  sizeof(reg_addr), &current_milli_amps,
+		zassert_ok(i2c_write_read(i2c_dev, isl923x_emul->bus.i2c->addr,
+					  &reg_addr, sizeof(reg_addr),
+					  &current_milli_amps,
 					  sizeof(current_milli_amps)),
 			   "Failed to read DC prochot register");
 		zassert_equal(
@@ -452,44 +443,44 @@ ZTEST(isl923x, test_comparator_inversion)
 {
 	const struct emul *isl923x_emul = ISL923X_EMUL;
 	const struct device *i2c_dev = isl923x_emul_get_parent(isl923x_emul);
-	struct i2c_emul *i2c_emul = isl923x_emul_get_i2c_emul(isl923x_emul);
 	uint8_t reg_addr = ISL923X_REG_CONTROL2;
 	uint16_t reg_value;
 	uint8_t tx_buf[] = { reg_addr, 0, 0 };
 
 	/* Test failed read, should not write */
-	i2c_common_emul_set_read_fail_reg(i2c_emul, ISL923X_REG_CONTROL2);
-	i2c_common_emul_set_write_func(i2c_emul, mock_write_fn_always_fail,
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, ISL923X_REG_CONTROL2);
+	i2c_common_emul_set_write_func(COMMON_DATA, mock_write_fn_always_fail,
 				       NULL);
 	zassert_equal(EC_ERROR_INVAL,
 		      isl923x_set_comparator_inversion(CHARGER_NUM, false),
 		      NULL);
-	i2c_common_emul_set_read_fail_reg(i2c_emul,
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA,
 					  I2C_COMMON_EMUL_NO_FAIL_REG);
-	i2c_common_emul_set_write_func(i2c_emul, NULL, NULL);
+	i2c_common_emul_set_write_func(COMMON_DATA, NULL, NULL);
 
 	/* Test failed write */
-	zassert_ok(i2c_write(i2c_dev, tx_buf, sizeof(tx_buf), i2c_emul->addr),
+	zassert_ok(i2c_write(i2c_dev, tx_buf, sizeof(tx_buf),
+			     isl923x_emul->bus.i2c->addr),
 		   "Failed to clear CTRL2 register");
-	i2c_common_emul_set_write_fail_reg(i2c_emul, ISL923X_REG_CONTROL2);
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA, ISL923X_REG_CONTROL2);
 	zassert_equal(EC_ERROR_INVAL,
 		      isl923x_set_comparator_inversion(CHARGER_NUM, true),
 		      NULL);
-	i2c_common_emul_set_write_fail_reg(i2c_emul,
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA,
 					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test enable comparator inversion */
 	zassert_ok(isl923x_set_comparator_inversion(CHARGER_NUM, true), NULL);
-	zassert_ok(i2c_write_read(i2c_dev, i2c_emul->addr, &reg_addr,
-				  sizeof(reg_addr), &reg_value,
+	zassert_ok(i2c_write_read(i2c_dev, isl923x_emul->bus.i2c->addr,
+				  &reg_addr, sizeof(reg_addr), &reg_value,
 				  sizeof(reg_value)),
 		   "Failed to read CTRL 2 register");
 	zassert_true((reg_value & ISL923X_C2_INVERT_CMOUT) != 0, NULL);
 
 	/* Test disable comparator inversion */
 	zassert_ok(isl923x_set_comparator_inversion(CHARGER_NUM, false), NULL);
-	zassert_ok(i2c_write_read(i2c_dev, i2c_emul->addr, &reg_addr,
-				  sizeof(reg_addr), &reg_value,
+	zassert_ok(i2c_write_read(i2c_dev, isl923x_emul->bus.i2c->addr,
+				  &reg_addr, sizeof(reg_addr), &reg_value,
 				  sizeof(reg_value)),
 		   "Failed to read CTRL 2 register");
 	zassert_true((reg_value & ISL923X_C2_INVERT_CMOUT) == 0, NULL);
@@ -499,39 +490,39 @@ ZTEST(isl923x, test_discharge_on_ac)
 {
 	const struct emul *isl923x_emul = ISL923X_EMUL;
 	const struct device *i2c_dev = isl923x_emul_get_parent(isl923x_emul);
-	struct i2c_emul *i2c_emul = isl923x_emul_get_i2c_emul(isl923x_emul);
+	const struct i2c_common_emul_cfg *cfg =
+		isl923x_emul_get_cfg(isl923x_emul);
 	uint8_t reg_addr = ISL923X_REG_CONTROL1;
 	uint8_t tx_buf[] = { reg_addr, 0, 0 };
 	uint16_t reg_value;
 
 	/* Test failure to read CTRL1 register */
-	i2c_common_emul_set_read_fail_reg(i2c_emul, ISL923X_REG_CONTROL1);
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, ISL923X_REG_CONTROL1);
 	zassert_equal(EC_ERROR_INVAL,
 		      isl923x_drv.discharge_on_ac(CHARGER_NUM, true), NULL);
-	i2c_common_emul_set_read_fail_reg(i2c_emul,
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA,
 					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Set CTRL1 register to 0 */
-	zassert_ok(i2c_write(i2c_dev, tx_buf, sizeof(tx_buf), i2c_emul->addr),
-		   NULL);
+	zassert_ok(i2c_write(i2c_dev, tx_buf, sizeof(tx_buf), cfg->addr), NULL);
 
 	/* Test failure to write CTRL1 register */
-	i2c_common_emul_set_write_fail_reg(i2c_emul, ISL923X_REG_CONTROL1);
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA, ISL923X_REG_CONTROL1);
 	zassert_equal(EC_ERROR_INVAL,
 		      isl923x_drv.discharge_on_ac(CHARGER_NUM, true), NULL);
-	zassert_ok(i2c_write_read(i2c_dev, i2c_emul->addr, &reg_addr,
-				  sizeof(reg_addr), &reg_value,
+	zassert_ok(i2c_write_read(i2c_dev, isl923x_emul->bus.i2c->addr,
+				  &reg_addr, sizeof(reg_addr), &reg_value,
 				  sizeof(reg_value)),
 		   NULL);
 	zassert_equal(0, reg_value, NULL);
-	i2c_common_emul_set_write_fail_reg(i2c_emul,
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA,
 					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test enabling discharge on AC */
 	zassert_ok(isl923x_drv.discharge_on_ac(CHARGER_NUM, true), NULL);
 
-	zassert_ok(i2c_write_read(i2c_dev, i2c_emul->addr, &reg_addr,
-				  sizeof(reg_addr), &reg_value,
+	zassert_ok(i2c_write_read(i2c_dev, isl923x_emul->bus.i2c->addr,
+				  &reg_addr, sizeof(reg_addr), &reg_value,
 				  sizeof(reg_value)),
 		   NULL);
 	zassert_true((reg_value & ISL923X_C1_LEARN_MODE_ENABLE) != 0, NULL);
@@ -539,8 +530,8 @@ ZTEST(isl923x, test_discharge_on_ac)
 	/* Test disabling discharge on AC */
 	zassert_ok(isl923x_drv.discharge_on_ac(CHARGER_NUM, false), NULL);
 
-	zassert_ok(i2c_write_read(i2c_dev, i2c_emul->addr, &reg_addr,
-				  sizeof(reg_addr), &reg_value,
+	zassert_ok(i2c_write_read(i2c_dev, isl923x_emul->bus.i2c->addr,
+				  &reg_addr, sizeof(reg_addr), &reg_value,
 				  sizeof(reg_value)),
 		   NULL);
 	zassert_true((reg_value & ISL923X_C1_LEARN_MODE_ENABLE) == 0, NULL);
@@ -549,17 +540,16 @@ ZTEST(isl923x, test_discharge_on_ac)
 ZTEST(isl923x, test_get_vbus_voltage)
 {
 	const struct emul *isl923x_emul = ISL923X_EMUL;
-	struct i2c_emul *i2c_emul = isl923x_emul_get_i2c_emul(isl923x_emul);
 	/* Standard fixed-power PD source voltages. */
 	int test_voltage_mv[] = { 5000, 9000, 15000, 20000 };
 	int voltage;
 
 	/* Test fail to read the ADC vbus register */
-	i2c_common_emul_set_read_fail_reg(i2c_emul, RAA489000_REG_ADC_VBUS);
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, RAA489000_REG_ADC_VBUS);
 	zassert_equal(EC_ERROR_INVAL,
 		      isl923x_drv.get_vbus_voltage(CHARGER_NUM, 0, &voltage),
 		      NULL);
-	i2c_common_emul_set_read_fail_reg(i2c_emul,
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA,
 					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	for (int i = 0; i < ARRAY_SIZE(test_voltage_mv); ++i) {
@@ -576,22 +566,21 @@ ZTEST(isl923x, test_get_vbus_voltage)
 		 * VBUS.
 		 */
 		zassert_within(expected_voltage_mv, voltage, 100,
-			      "Expected %dmV but got %dmV", expected_voltage_mv,
-			      voltage);
+			       "Expected %dmV but got %dmV",
+			       expected_voltage_mv, voltage);
 	}
 }
 
 ZTEST(isl923x, test_init)
 {
 	const struct emul *isl923x_emul = ISL923X_EMUL;
-	struct i2c_emul *i2c_emul = isl923x_emul_get_i2c_emul(isl923x_emul);
 	int input_current;
 
 	/* Test failed CTRL2 register read (prochot debounce) */
 	isl923x_emul_reset_registers(isl923x_emul);
-	i2c_common_emul_set_read_fail_reg(i2c_emul, ISL923X_REG_CONTROL2);
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, ISL923X_REG_CONTROL2);
 	isl923x_drv.init(CHARGER_NUM);
-	i2c_common_emul_set_read_fail_reg(i2c_emul,
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA,
 					  I2C_COMMON_EMUL_NO_FAIL_REG);
 	zassert_ok(isl923x_drv.get_input_current_limit(CHARGER_NUM,
 						       &input_current),
@@ -601,9 +590,9 @@ ZTEST(isl923x, test_init)
 
 	/* Test failed CTRL2 register write */
 	isl923x_emul_reset_registers(isl923x_emul);
-	i2c_common_emul_set_write_fail_reg(i2c_emul, ISL923X_REG_CONTROL2);
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA, ISL923X_REG_CONTROL2);
 	isl923x_drv.init(CHARGER_NUM);
-	i2c_common_emul_set_write_fail_reg(i2c_emul,
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA,
 					   I2C_COMMON_EMUL_NO_FAIL_REG);
 	zassert_ok(isl923x_drv.get_input_current_limit(CHARGER_NUM,
 						       &input_current),
@@ -613,37 +602,35 @@ ZTEST(isl923x, test_init)
 
 	/* Test failed CTRL 0 read */
 	isl923x_emul_reset_registers(isl923x_emul);
-	i2c_common_emul_set_read_fail_reg(i2c_emul, ISL923X_REG_CONTROL0);
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, ISL923X_REG_CONTROL0);
 	isl923x_drv.init(CHARGER_NUM);
-	i2c_common_emul_set_read_fail_reg(i2c_emul,
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA,
 					  I2C_COMMON_EMUL_NO_FAIL_REG);
 	zassert_ok(isl923x_drv.get_input_current_limit(CHARGER_NUM,
 						       &input_current),
 		   NULL);
 
 	zassert_equal(0, input_current,
-			      "Expected input current 0mA but got %dmA",
-			      input_current);
+		      "Expected input current 0mA but got %dmA", input_current);
 
 	/* Test failed CTRL 0 write */
 	isl923x_emul_reset_registers(isl923x_emul);
-	i2c_common_emul_set_write_fail_reg(i2c_emul, ISL923X_REG_CONTROL0);
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA, ISL923X_REG_CONTROL0);
 	isl923x_drv.init(CHARGER_NUM);
-	i2c_common_emul_set_write_fail_reg(i2c_emul,
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA,
 					   I2C_COMMON_EMUL_NO_FAIL_REG);
 	zassert_ok(isl923x_drv.get_input_current_limit(CHARGER_NUM,
 						       &input_current),
 		   NULL);
 
 	zassert_equal(0, input_current,
-			      "Expected input current 0mA but got %dmA",
-			      input_current);
+		      "Expected input current 0mA but got %dmA", input_current);
 
 	/* Test failed CTRL 3 read */
 	isl923x_emul_reset_registers(isl923x_emul);
-	i2c_common_emul_set_read_fail_reg(i2c_emul, ISL9238_REG_CONTROL3);
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, ISL9238_REG_CONTROL3);
 	isl923x_drv.init(CHARGER_NUM);
-	i2c_common_emul_set_read_fail_reg(i2c_emul,
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA,
 					  I2C_COMMON_EMUL_NO_FAIL_REG);
 	zassert_ok(isl923x_drv.get_input_current_limit(CHARGER_NUM,
 						       &input_current),
@@ -653,9 +640,9 @@ ZTEST(isl923x, test_init)
 
 	/* Test failed CTRL 3 write */
 	isl923x_emul_reset_registers(isl923x_emul);
-	i2c_common_emul_set_write_fail_reg(i2c_emul, ISL9238_REG_CONTROL3);
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA, ISL9238_REG_CONTROL3);
 	isl923x_drv.init(CHARGER_NUM);
-	i2c_common_emul_set_write_fail_reg(i2c_emul,
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA,
 					   I2C_COMMON_EMUL_NO_FAIL_REG);
 	zassert_ok(isl923x_drv.get_input_current_limit(CHARGER_NUM,
 						       &input_current),
@@ -665,10 +652,10 @@ ZTEST(isl923x, test_init)
 
 	/* Test failed write adapter current limit */
 	isl923x_emul_reset_registers(isl923x_emul);
-	i2c_common_emul_set_write_fail_reg(i2c_emul,
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA,
 					   ISL923X_REG_ADAPTER_CURRENT_LIMIT1);
 	isl923x_drv.init(CHARGER_NUM);
-	i2c_common_emul_set_write_fail_reg(i2c_emul,
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA,
 					   I2C_COMMON_EMUL_NO_FAIL_REG);
 	zassert_ok(isl923x_drv.get_input_current_limit(CHARGER_NUM,
 						       &input_current),
@@ -702,7 +689,6 @@ ZTEST(isl923x, test_init_late_jump)
 ZTEST(isl923x, test_isl923x_is_acok)
 {
 	const struct emul *isl923x_emul = ISL923X_EMUL;
-	struct i2c_emul *i2c_emul = isl923x_emul_get_i2c_emul(isl923x_emul);
 	enum ec_error_list rv;
 	bool acok;
 
@@ -712,13 +698,13 @@ ZTEST(isl923x, test_isl923x_is_acok)
 		      "Invalid charger num, but AC OK check succeeded");
 
 	/* Part 2: error accessing register */
-	i2c_common_emul_set_read_fail_reg(i2c_emul, ISL9238_REG_INFO2);
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, ISL9238_REG_INFO2);
 
 	rv = raa489000_is_acok(CHARGER_NUM, &acok);
 	zassert_equal(EC_ERROR_INVAL, rv,
 		      "Register read failure, but AC OK check succeeded");
 
-	i2c_common_emul_set_read_fail_reg(i2c_emul,
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA,
 					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Part 3: successful path - ACOK is true */
@@ -739,7 +725,6 @@ ZTEST(isl923x, test_isl923x_is_acok)
 ZTEST(isl923x, test_isl923x_enable_asgate)
 {
 	const struct emul *isl923x_emul = ISL923X_EMUL;
-	struct i2c_emul *i2c_emul = isl923x_emul_get_i2c_emul(isl923x_emul);
 	int rv;
 
 	/* Part 1: Try enabling the ASGATE */
@@ -748,7 +733,7 @@ ZTEST(isl923x, test_isl923x_enable_asgate)
 	zassert_equal(EC_SUCCESS, rv, "Expected return code of %d but got %d",
 		      EC_SUCCESS, rv);
 	zassert_true(
-		isl923x_emul_peek_reg(i2c_emul, RAA489000_REG_CONTROL8) &
+		isl923x_emul_peek_reg(isl923x_emul, RAA489000_REG_CONTROL8) &
 			RAA489000_C8_ASGATE_ON_READY,
 		"RAA489000_C8_ASGATE_ON_READY bit not set in Control Reg 8");
 
@@ -757,15 +742,16 @@ ZTEST(isl923x, test_isl923x_enable_asgate)
 
 	zassert_equal(EC_SUCCESS, rv, "Expected return code of %d but got %d",
 		      EC_SUCCESS, rv);
-	zassert_false(isl923x_emul_peek_reg(i2c_emul, RAA489000_REG_CONTROL8) &
+	zassert_false(isl923x_emul_peek_reg(isl923x_emul,
+					    RAA489000_REG_CONTROL8) &
 			      RAA489000_C8_ASGATE_ON_READY,
 		      "RAA489000_C8_ASGATE_ON_READY bit set in Control Reg 8");
 }
 
 /* Mock read and write functions to use in the hibernation test */
-FAKE_VALUE_FUNC(int, hibernate_mock_read_fn, struct i2c_emul *, int, uint8_t *,
-		int, void *);
-FAKE_VALUE_FUNC(int, hibernate_mock_write_fn, struct i2c_emul *, int, uint8_t,
+FAKE_VALUE_FUNC(int, hibernate_mock_read_fn, const struct emul *, int,
+		uint8_t *, int, void *);
+FAKE_VALUE_FUNC(int, hibernate_mock_write_fn, const struct emul *, int, uint8_t,
 		int, void *);
 
 /**
@@ -773,8 +759,6 @@ FAKE_VALUE_FUNC(int, hibernate_mock_write_fn, struct i2c_emul *, int, uint8_t,
  */
 static void isl923x_hibernate_before(void *state)
 {
-	const struct emul *isl923x_emul = ISL923X_EMUL;
-	struct i2c_emul *i2c_emul = isl923x_emul_get_i2c_emul(isl923x_emul);
 	ARG_UNUSED(state);
 
 	/* Reset mocks and make the read/write mocks pass all data through */
@@ -783,13 +767,15 @@ static void isl923x_hibernate_before(void *state)
 	hibernate_mock_read_fn_fake.return_val = 1;
 	hibernate_mock_write_fn_fake.return_val = 1;
 
-	i2c_common_emul_set_read_func(i2c_emul, hibernate_mock_read_fn, NULL);
-	i2c_common_emul_set_write_func(i2c_emul, hibernate_mock_write_fn, NULL);
+	i2c_common_emul_set_read_func(COMMON_DATA, hibernate_mock_read_fn,
+				      NULL);
+	i2c_common_emul_set_write_func(COMMON_DATA, hibernate_mock_write_fn,
+				       NULL);
 
 	/* Don't fail on any register access */
-	i2c_common_emul_set_read_fail_reg(i2c_emul,
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA,
 					  I2C_COMMON_EMUL_NO_FAIL_REG);
-	i2c_common_emul_set_write_fail_reg(i2c_emul,
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA,
 					   I2C_COMMON_EMUL_NO_FAIL_REG);
 }
 
@@ -798,31 +784,28 @@ static void isl923x_hibernate_before(void *state)
  */
 static void isl923x_hibernate_after(void *state)
 {
-	const struct emul *isl923x_emul = ISL923X_EMUL;
-	struct i2c_emul *i2c_emul = isl923x_emul_get_i2c_emul(isl923x_emul);
 	ARG_UNUSED(state);
 
 	/* Clear the mock read/write functions */
-	i2c_common_emul_set_read_func(i2c_emul, NULL, NULL);
-	i2c_common_emul_set_write_func(i2c_emul, NULL, NULL);
+	i2c_common_emul_set_read_func(COMMON_DATA, NULL, NULL);
+	i2c_common_emul_set_write_func(COMMON_DATA, NULL, NULL);
 
 	/* Don't fail on any register access */
-	i2c_common_emul_set_read_fail_reg(i2c_emul,
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA,
 					  I2C_COMMON_EMUL_NO_FAIL_REG);
-	i2c_common_emul_set_write_fail_reg(i2c_emul,
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA,
 					   I2C_COMMON_EMUL_NO_FAIL_REG);
 }
 
 ZTEST(isl923x_hibernate, test_isl923x_hibernate__happy_path)
 {
 	const struct emul *isl923x_emul = ISL923X_EMUL;
-	struct i2c_emul *i2c_emul = isl923x_emul_get_i2c_emul(isl923x_emul);
 	uint16_t actual;
 
 	raa489000_hibernate(CHARGER_NUM, false);
 
 	/* Check ISL923X_REG_CONTROL0 */
-	actual = isl923x_emul_peek_reg(i2c_emul, ISL923X_REG_CONTROL0);
+	actual = isl923x_emul_peek_reg(isl923x_emul, ISL923X_REG_CONTROL0);
 
 	zassert_false(actual & RAA489000_C0_EN_CHG_PUMPS_TO_100PCT,
 		      "RAA489000_C0_EN_CHG_PUMPS_TO_100PCT should not be set");
@@ -830,10 +813,11 @@ ZTEST(isl923x_hibernate, test_isl923x_hibernate__happy_path)
 		      "RAA489000_C0_BGATE_FORCE_ON should not be set");
 
 	/* Check ISL923X_REG_CONTROL1 */
-	actual = isl923x_emul_peek_reg(i2c_emul, ISL923X_REG_CONTROL1);
+	actual = isl923x_emul_peek_reg(isl923x_emul, ISL923X_REG_CONTROL1);
 
-	zassert_false(actual & RAA489000_C1_ENABLE_SUPP_SUPPORT_MODE,
-		      "RAA489000_C1_ENABLE_SUPP_SUPPORT_MODE should not be set");
+	zassert_false(
+		actual & RAA489000_C1_ENABLE_SUPP_SUPPORT_MODE,
+		"RAA489000_C1_ENABLE_SUPP_SUPPORT_MODE should not be set");
 	zassert_false(actual & ISL923X_C1_ENABLE_PSYS,
 		      "ISL923X_C1_ENABLE_PSYS should not be set");
 	zassert_true(actual & RAA489000_C1_BGATE_FORCE_OFF,
@@ -842,13 +826,13 @@ ZTEST(isl923x_hibernate, test_isl923x_hibernate__happy_path)
 		     "ISL923X_C1_DISABLE_MON should be set");
 
 	/* Check ISL9238_REG_CONTROL3 (disable_adc = false) */
-	actual = isl923x_emul_peek_reg(i2c_emul, ISL9238_REG_CONTROL3);
+	actual = isl923x_emul_peek_reg(isl923x_emul, ISL9238_REG_CONTROL3);
 
 	zassert_true(actual & RAA489000_ENABLE_ADC,
 		     "RAA489000_ENABLE_ADC should be set");
 
 	/* Check ISL9238_REG_CONTROL4 */
-	actual = isl923x_emul_peek_reg(i2c_emul, ISL9238_REG_CONTROL4);
+	actual = isl923x_emul_peek_reg(isl923x_emul, ISL9238_REG_CONTROL4);
 
 	zassert_true(actual & RAA489000_C4_DISABLE_GP_CMP,
 		     "RAA489000_C4_DISABLE_GP_CMP should be set");
@@ -889,10 +873,7 @@ ZTEST(isl923x_hibernate, test_isl923x_hibernate__invalid_charger_number)
 
 ZTEST(isl923x_hibernate, test_isl923x_hibernate__fail_at_ISL923X_REG_CONTROL0)
 {
-	const struct emul *isl923x_emul = ISL923X_EMUL;
-	struct i2c_emul *i2c_emul = isl923x_emul_get_i2c_emul(isl923x_emul);
-
-	i2c_common_emul_set_read_fail_reg(i2c_emul, ISL923X_REG_CONTROL0);
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, ISL923X_REG_CONTROL0);
 
 	raa489000_hibernate(CHARGER_NUM, false);
 
@@ -907,10 +888,7 @@ ZTEST(isl923x_hibernate, test_isl923x_hibernate__fail_at_ISL923X_REG_CONTROL0)
 
 ZTEST(isl923x_hibernate, test_isl923x_hibernate__fail_at_ISL923X_REG_CONTROL1)
 {
-	const struct emul *isl923x_emul = ISL923X_EMUL;
-	struct i2c_emul *i2c_emul = isl923x_emul_get_i2c_emul(isl923x_emul);
-
-	i2c_common_emul_set_read_fail_reg(i2c_emul, ISL923X_REG_CONTROL1);
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, ISL923X_REG_CONTROL1);
 
 	raa489000_hibernate(CHARGER_NUM, false);
 
@@ -931,10 +909,7 @@ ZTEST(isl923x_hibernate, test_isl923x_hibernate__fail_at_ISL923X_REG_CONTROL1)
 
 ZTEST(isl923x_hibernate, test_isl923x_hibernate__fail_at_ISL9238_REG_CONTROL3)
 {
-	const struct emul *isl923x_emul = ISL923X_EMUL;
-	struct i2c_emul *i2c_emul = isl923x_emul_get_i2c_emul(isl923x_emul);
-
-	i2c_common_emul_set_read_fail_reg(i2c_emul, ISL9238_REG_CONTROL3);
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, ISL9238_REG_CONTROL3);
 
 	raa489000_hibernate(CHARGER_NUM, false);
 
@@ -955,10 +930,7 @@ ZTEST(isl923x_hibernate, test_isl923x_hibernate__fail_at_ISL9238_REG_CONTROL3)
 
 ZTEST(isl923x_hibernate, test_isl923x_hibernate__fail_at_ISL9238_REG_CONTROL4)
 {
-	const struct emul *isl923x_emul = ISL923X_EMUL;
-	struct i2c_emul *i2c_emul = isl923x_emul_get_i2c_emul(isl923x_emul);
-
-	i2c_common_emul_set_read_fail_reg(i2c_emul, ISL9238_REG_CONTROL4);
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, ISL9238_REG_CONTROL4);
 
 	raa489000_hibernate(CHARGER_NUM, false);
 
@@ -977,13 +949,12 @@ ZTEST(isl923x_hibernate, test_isl923x_hibernate__fail_at_ISL9238_REG_CONTROL4)
 ZTEST(isl923x_hibernate, test_isl923x_hibernate__adc_disable)
 {
 	const struct emul *isl923x_emul = ISL923X_EMUL;
-	struct i2c_emul *i2c_emul = isl923x_emul_get_i2c_emul(isl923x_emul);
 	uint16_t expected;
 
 	raa489000_hibernate(CHARGER_NUM, true);
 
 	/* Check ISL9238_REG_CONTROL3 (disable_adc = true) */
-	expected = isl923x_emul_peek_reg(i2c_emul, ISL9238_REG_CONTROL3);
+	expected = isl923x_emul_peek_reg(isl923x_emul, ISL9238_REG_CONTROL3);
 	expected &= ~RAA489000_ENABLE_ADC;
 
 	MOCK_ASSERT_I2C_READ(hibernate_mock_read_fn, 4, ISL9238_REG_CONTROL3);
@@ -997,40 +968,39 @@ ZTEST(isl923x_hibernate, test_isl923x_hibernate__adc_disable)
 ZTEST(isl923x_hibernate, test_isl9238c_hibernate)
 {
 	const struct emul *isl923x_emul = ISL923X_EMUL;
-	struct i2c_emul *i2c_emul = isl923x_emul_get_i2c_emul(isl923x_emul);
 	uint16_t control1_expected, control2_expected, control3_expected;
 	int rv;
 
 	/* Part 1: Happy path */
 	control1_expected =
-		(isl923x_emul_peek_reg(i2c_emul, ISL923X_REG_CONTROL1) &
-			~ISL923X_C1_ENABLE_PSYS) |
+		(isl923x_emul_peek_reg(isl923x_emul, ISL923X_REG_CONTROL1) &
+		 ~ISL923X_C1_ENABLE_PSYS) |
 		ISL923X_C1_DISABLE_MON;
 	control2_expected =
-		isl923x_emul_peek_reg(i2c_emul, ISL923X_REG_CONTROL2) |
+		isl923x_emul_peek_reg(isl923x_emul, ISL923X_REG_CONTROL2) |
 		ISL923X_C2_COMPARATOR;
 	control3_expected =
-		isl923x_emul_peek_reg(i2c_emul, ISL9238_REG_CONTROL3) |
+		isl923x_emul_peek_reg(isl923x_emul, ISL9238_REG_CONTROL3) |
 		ISL9238_C3_BGATE_OFF;
 
 	rv = isl9238c_hibernate(CHARGER_NUM);
 
 	zassert_equal(EC_SUCCESS, rv, "Expected return code %d but got %d",
 		      EC_SUCCESS, rv);
-	zassert_equal(isl923x_emul_peek_reg(i2c_emul, ISL923X_REG_CONTROL1),
+	zassert_equal(isl923x_emul_peek_reg(isl923x_emul, ISL923X_REG_CONTROL1),
 		      control1_expected,
 		      "Unexpected register value 0x%02x. Should be 0x%02x",
-		      isl923x_emul_peek_reg(i2c_emul, ISL923X_REG_CONTROL1),
+		      isl923x_emul_peek_reg(isl923x_emul, ISL923X_REG_CONTROL1),
 		      control1_expected);
-	zassert_equal(isl923x_emul_peek_reg(i2c_emul, ISL923X_REG_CONTROL2),
+	zassert_equal(isl923x_emul_peek_reg(isl923x_emul, ISL923X_REG_CONTROL2),
 		      control2_expected,
 		      "Unexpected register value 0x%02x. Should be 0x%02x",
-		      isl923x_emul_peek_reg(i2c_emul, ISL923X_REG_CONTROL2),
+		      isl923x_emul_peek_reg(isl923x_emul, ISL923X_REG_CONTROL2),
 		      control2_expected);
-	zassert_equal(isl923x_emul_peek_reg(i2c_emul, ISL9238_REG_CONTROL3),
+	zassert_equal(isl923x_emul_peek_reg(isl923x_emul, ISL9238_REG_CONTROL3),
 		      control3_expected,
 		      "Unexpected register value 0x%02x. Should be 0x%02x",
-		      isl923x_emul_peek_reg(i2c_emul, ISL9238_REG_CONTROL3),
+		      isl923x_emul_peek_reg(isl923x_emul, ISL9238_REG_CONTROL3),
 		      control3_expected);
 
 	/* Part 2: Fail reading each register and check for error code */
@@ -1038,7 +1008,7 @@ ZTEST(isl923x_hibernate, test_isl9238c_hibernate)
 			    ISL9238_REG_CONTROL3 };
 
 	for (int i = 0; i < ARRAY_SIZE(registers); i++) {
-		i2c_common_emul_set_read_fail_reg(i2c_emul, registers[i]);
+		i2c_common_emul_set_read_fail_reg(COMMON_DATA, registers[i]);
 
 		rv = isl9238c_hibernate(CHARGER_NUM);
 
@@ -1051,39 +1021,38 @@ ZTEST(isl923x_hibernate, test_isl9238c_hibernate)
 ZTEST(isl923x_hibernate, test_isl9238c_resume)
 {
 	const struct emul *isl923x_emul = ISL923X_EMUL;
-	struct i2c_emul *i2c_emul = isl923x_emul_get_i2c_emul(isl923x_emul);
 	uint16_t control1_expected, control2_expected, control3_expected;
 	int rv;
 
 	/* Part 1: Happy path */
 	control1_expected =
-		isl923x_emul_peek_reg(i2c_emul, ISL923X_REG_CONTROL1) |
+		isl923x_emul_peek_reg(isl923x_emul, ISL923X_REG_CONTROL1) |
 		ISL923X_C1_ENABLE_PSYS;
 	control2_expected =
-		isl923x_emul_peek_reg(i2c_emul, ISL923X_REG_CONTROL2) &
+		isl923x_emul_peek_reg(isl923x_emul, ISL923X_REG_CONTROL2) &
 		~ISL923X_C2_COMPARATOR;
 	control3_expected =
-		isl923x_emul_peek_reg(i2c_emul, ISL9238_REG_CONTROL3) &
+		isl923x_emul_peek_reg(isl923x_emul, ISL9238_REG_CONTROL3) &
 		~ISL9238_C3_BGATE_OFF;
 
 	rv = isl9238c_resume(CHARGER_NUM);
 
 	zassert_equal(EC_SUCCESS, rv, "Expected return code %d but got %d",
 		      EC_SUCCESS, rv);
-	zassert_equal(isl923x_emul_peek_reg(i2c_emul, ISL923X_REG_CONTROL1),
+	zassert_equal(isl923x_emul_peek_reg(isl923x_emul, ISL923X_REG_CONTROL1),
 		      control1_expected,
 		      "Unexpected register value 0x%02x. Should be 0x%02x",
-		      isl923x_emul_peek_reg(i2c_emul, ISL923X_REG_CONTROL1),
+		      isl923x_emul_peek_reg(isl923x_emul, ISL923X_REG_CONTROL1),
 		      control1_expected);
-	zassert_equal(isl923x_emul_peek_reg(i2c_emul, ISL923X_REG_CONTROL2),
+	zassert_equal(isl923x_emul_peek_reg(isl923x_emul, ISL923X_REG_CONTROL2),
 		      control2_expected,
 		      "Unexpected register value 0x%02x. Should be 0x%02x",
-		      isl923x_emul_peek_reg(i2c_emul, ISL923X_REG_CONTROL2),
+		      isl923x_emul_peek_reg(isl923x_emul, ISL923X_REG_CONTROL2),
 		      control2_expected);
-	zassert_equal(isl923x_emul_peek_reg(i2c_emul, ISL9238_REG_CONTROL3),
+	zassert_equal(isl923x_emul_peek_reg(isl923x_emul, ISL9238_REG_CONTROL3),
 		      control3_expected,
 		      "Unexpected register value 0x%02x. Should be 0x%02x",
-		      isl923x_emul_peek_reg(i2c_emul, ISL9238_REG_CONTROL3),
+		      isl923x_emul_peek_reg(isl923x_emul, ISL9238_REG_CONTROL3),
 		      control3_expected);
 
 	/* Part 2: Fail reading each register and check for error code */
@@ -1091,7 +1060,7 @@ ZTEST(isl923x_hibernate, test_isl9238c_resume)
 			    ISL9238_REG_CONTROL3 };
 
 	for (int i = 0; i < ARRAY_SIZE(registers); i++) {
-		i2c_common_emul_set_read_fail_reg(i2c_emul, registers[i]);
+		i2c_common_emul_set_read_fail_reg(COMMON_DATA, registers[i]);
 
 		rv = isl9238c_resume(CHARGER_NUM);
 
@@ -1101,7 +1070,7 @@ ZTEST(isl923x_hibernate, test_isl9238c_resume)
 	}
 }
 
-ZTEST_SUITE(isl923x, drivers_predicate_post_main, NULL, NULL, NULL, NULL);
+ZTEST_SUITE(isl923x, drivers_predicate_pre_main, NULL, NULL, NULL, NULL);
 
 ZTEST_SUITE(isl923x_hibernate, drivers_predicate_post_main, NULL,
 	    isl923x_hibernate_before, isl923x_hibernate_after, NULL);
diff --git a/zephyr/test/drivers/default/src/led.c b/zephyr/test/drivers/default/src/led.c
new file mode 100644
index 0000000000..e89a3d8b66
--- /dev/null
+++ b/zephyr/test/drivers/default/src/led.c
@@ -0,0 +1,92 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/ztest.h>
+#include <zephyr/ztest_assert.h>
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/pwm.h>
+
+#include "ec_commands.h"
+#include "led.h"
+#include "led_common.h"
+#include "pwm_mock.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+ZTEST_SUITE(pwm_led_driver, drivers_predicate_post_main, NULL, NULL, NULL,
+	    NULL);
+
+ZTEST(pwm_led_driver, test_led_set_brightness)
+{
+	const uint8_t brightness_off[EC_LED_COLOR_COUNT] = {};
+	const uint8_t brightness_white[EC_LED_COLOR_COUNT] = {
+		[EC_LED_COLOR_WHITE] = 1
+	};
+	const uint8_t brightness_amber[EC_LED_COLOR_COUNT] = {
+		[EC_LED_COLOR_AMBER] = 1
+	};
+	const struct device *pwm_blue_left =
+		DEVICE_DT_GET(DT_NODELABEL(pwm_blue_left));
+	const struct device *pwm_white_left =
+		DEVICE_DT_GET(DT_NODELABEL(pwm_white_left));
+	const struct device *pwm_amber_right =
+		DEVICE_DT_GET(DT_NODELABEL(pwm_amber_right));
+	const struct device *pwm_white_right =
+		DEVICE_DT_GET(DT_NODELABEL(pwm_white_right));
+
+	/* Turn off all LEDs */
+	led_set_brightness(EC_LED_ID_LEFT_LED, brightness_off);
+	led_set_brightness(EC_LED_ID_RIGHT_LED, brightness_off);
+	zassert_equal(pwm_mock_get_duty(pwm_blue_left, 0), 0, NULL);
+	zassert_equal(pwm_mock_get_duty(pwm_white_left, 0), 0, NULL);
+	zassert_equal(pwm_mock_get_duty(pwm_amber_right, 0), 0, NULL);
+	zassert_equal(pwm_mock_get_duty(pwm_white_right, 0), 0, NULL);
+
+	/* Call led_set_color(LED_WHITE, LEFT_LED) */
+	led_set_brightness(EC_LED_ID_LEFT_LED, brightness_white);
+	zassert_equal(pwm_mock_get_duty(pwm_blue_left, 0), 0, NULL);
+	zassert_equal(pwm_mock_get_duty(pwm_white_left, 0), 100, NULL);
+	zassert_equal(pwm_mock_get_duty(pwm_amber_right, 0), 0, NULL);
+	zassert_equal(pwm_mock_get_duty(pwm_white_right, 0), 0, NULL);
+
+	/* Unsupporte, call led_set_color(LED_OFF, LEFT_LED) */
+	led_set_brightness(EC_LED_ID_LEFT_LED, brightness_amber);
+	zassert_equal(pwm_mock_get_duty(pwm_blue_left, 0), 0, NULL);
+	zassert_equal(pwm_mock_get_duty(pwm_white_left, 0), 0, NULL);
+	zassert_equal(pwm_mock_get_duty(pwm_amber_right, 0), 0, NULL);
+	zassert_equal(pwm_mock_get_duty(pwm_white_right, 0), 0, NULL);
+
+	/* Call led_set_color(AMBER, RIGHT_LED) */
+	led_set_brightness(EC_LED_ID_RIGHT_LED, brightness_amber);
+	zassert_equal(pwm_mock_get_duty(pwm_blue_left, 0), 0, NULL);
+	zassert_equal(pwm_mock_get_duty(pwm_white_left, 0), 0, NULL);
+	zassert_equal(pwm_mock_get_duty(pwm_amber_right, 0), 100, NULL);
+	zassert_equal(pwm_mock_get_duty(pwm_white_right, 0), 0, NULL);
+}
+
+ZTEST(pwm_led_driver, test_led_get_brightness)
+{
+	uint8_t brightness[EC_LED_COLOR_COUNT];
+	const uint8_t expected_left[EC_LED_COLOR_COUNT] = {
+		[EC_LED_COLOR_BLUE] = 100,
+		[EC_LED_COLOR_WHITE] = 100,
+	};
+	const uint8_t expected_right[EC_LED_COLOR_COUNT] = {
+		[EC_LED_COLOR_WHITE] = 100,
+		[EC_LED_COLOR_AMBER] = 100,
+	};
+
+	/* Verify LED colors defined in device tree are reflected in the
+	 * brightness array.
+	 */
+	memset(brightness, 255, sizeof(brightness));
+	led_get_brightness_range(EC_LED_ID_LEFT_LED, brightness);
+	zassert_mem_equal(brightness, expected_left, sizeof(brightness), NULL);
+
+	memset(brightness, 255, sizeof(brightness));
+	led_get_brightness_range(EC_LED_ID_RIGHT_LED, brightness);
+	zassert_mem_equal(brightness, expected_right, sizeof(brightness), NULL);
+}
diff --git a/zephyr/test/drivers/default/src/lid_angle.c b/zephyr/test/drivers/default/src/lid_angle.c
new file mode 100644
index 0000000000..568057d95a
--- /dev/null
+++ b/zephyr/test/drivers/default/src/lid_angle.c
@@ -0,0 +1,70 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/ztest.h>
+
+#include "ec_commands.h"
+#include "lid_angle.h"
+#include "test/drivers/test_mocks.h"
+#include "test/drivers/test_state.h"
+
+#define LID_ANGLE_MIN_LARGE_ANGLE 0
+#define LID_ANGLE_MAX_LARGE_ANGLE 360
+
+static void lid_angle_after(void *f)
+{
+	ARG_UNUSED(f);
+	/* Reset the wake angle */
+	lid_angle_set_wake_angle(180);
+	/* Flush the buffer */
+	lid_angle_update(LID_ANGLE_UNRELIABLE);
+	lid_angle_update(LID_ANGLE_UNRELIABLE);
+	lid_angle_update(LID_ANGLE_UNRELIABLE);
+	lid_angle_update(LID_ANGLE_UNRELIABLE);
+}
+
+ZTEST_SUITE(lid_angle, drivers_predicate_post_main, NULL, NULL, lid_angle_after,
+	    NULL);
+
+ZTEST(lid_angle, test_get_set_wake_angle)
+{
+	lid_angle_set_wake_angle(LID_ANGLE_MIN_LARGE_ANGLE - 1);
+	zassert_equal(LID_ANGLE_MIN_LARGE_ANGLE, lid_angle_get_wake_angle(),
+		      NULL);
+
+	lid_angle_set_wake_angle(LID_ANGLE_MAX_LARGE_ANGLE + 1);
+	zassert_equal(LID_ANGLE_MAX_LARGE_ANGLE, lid_angle_get_wake_angle(),
+		      NULL);
+
+	lid_angle_set_wake_angle(
+		(LID_ANGLE_MIN_LARGE_ANGLE + LID_ANGLE_MAX_LARGE_ANGLE) / 2);
+	zassert_equal((LID_ANGLE_MIN_LARGE_ANGLE + LID_ANGLE_MAX_LARGE_ANGLE) /
+			      2,
+		      lid_angle_get_wake_angle(), NULL);
+}
+
+ZTEST(lid_angle, test_no_wake_min_large_angle)
+{
+	lid_angle_set_wake_angle(LID_ANGLE_MIN_LARGE_ANGLE);
+	lid_angle_update(45);
+	lid_angle_update(45);
+	lid_angle_update(45);
+	lid_angle_update(45);
+
+	zassert_equal(1, lid_angle_peripheral_enable_fake.call_count, NULL);
+	zassert_equal(0, lid_angle_peripheral_enable_fake.arg0_val, NULL);
+}
+
+ZTEST(lid_angle, test_wake_max_large_angle)
+{
+	lid_angle_set_wake_angle(LID_ANGLE_MAX_LARGE_ANGLE);
+	lid_angle_update(45);
+	lid_angle_update(45);
+	lid_angle_update(45);
+	lid_angle_update(45);
+
+	zassert_equal(1, lid_angle_peripheral_enable_fake.call_count, NULL);
+	zassert_equal(1, lid_angle_peripheral_enable_fake.arg0_val, NULL);
+}
diff --git a/zephyr/test/drivers/src/lid_switch.c b/zephyr/test/drivers/default/src/lid_switch.c
index 42d91495f4..1647f73e00 100644
--- a/zephyr/test/drivers/src/lid_switch.c
+++ b/zephyr/test/drivers/default/src/lid_switch.c
@@ -1,9 +1,9 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <ztest.h>
+#include <zephyr/ztest.h>
 #include <zephyr/drivers/emul.h>
 #include <zephyr/drivers/gpio.h>
 #include <zephyr/drivers/gpio/gpio_emul.h>
@@ -12,6 +12,7 @@
 #include <console.h>
 
 #include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
 #include "ec_commands.h"
 #include "host_command.h"
 
@@ -34,18 +35,44 @@ int emul_lid_close(void)
 	return gpio_emul_input_set(lid_gpio_dev, LID_GPIO_PIN, 0);
 }
 
-static void cleanup(void *unused)
+static void *lid_switch_setup(void)
+{
+	/**
+	 * Set chipset to S0 as chipset power on after opening lid may disturb
+	 * test
+	 */
+	test_set_chipset_to_s0();
+
+	return NULL;
+}
+
+static void lid_switch_before(void *unused)
+{
+	/* Make sure that interrupt fire at the next lid open/close */
+	zassume_ok(emul_lid_close(), NULL);
+	zassume_ok(emul_lid_open(), NULL);
+	k_sleep(K_MSEC(100));
+}
+
+static void lid_switch_after(void *unused)
 {
 	struct ec_params_force_lid_open params = {
 		.enabled = 0,
 	};
 	struct host_cmd_handler_args args =
 		BUILD_HOST_COMMAND_PARAMS(EC_CMD_FORCE_LID_OPEN, 0, params);
+	int res;
 
-	zassert_ok(host_command_process(&args), NULL);
-	zassert_ok(args.result, NULL);
+	res = host_command_process(&args);
+	if (res)
+		TC_ERROR("host_command_process() failed (%d)\n", res);
 
-	zassert_ok(emul_lid_open(), NULL);
+	if (args.result)
+		TC_ERROR("args.result != 0 (%d != 0)\n", args.result);
+
+	res = emul_lid_open();
+	if (res)
+		TC_ERROR("emul_lid_open() failed (%d)\n", res);
 	k_sleep(K_MSEC(100));
 }
 
@@ -246,5 +273,5 @@ ZTEST(lid_switch, test_hc_force_lid_open)
 	zassert_equal(lid_is_open(), 1, NULL);
 }
 
-ZTEST_SUITE(lid_switch, drivers_predicate_post_main, NULL, NULL, &cleanup,
-	    NULL);
+ZTEST_SUITE(lid_switch, drivers_predicate_post_main, lid_switch_setup,
+	    lid_switch_before, lid_switch_after, NULL);
diff --git a/zephyr/test/drivers/src/lis2dw12.c b/zephyr/test/drivers/default/src/lis2dw12.c
index 56f71cc406..4cb29796f8 100644
--- a/zephyr/test/drivers/src/lis2dw12.c
+++ b/zephyr/test/drivers/default/src/lis2dw12.c
@@ -1,9 +1,9 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <ztest.h>
+#include <zephyr/ztest.h>
 #include <zephyr/drivers/emul.h>
 #include "driver/accel_lis2dw12.h"
 #include "emul/emul_common_i2c.h"
@@ -12,7 +12,7 @@
 
 #define LIS2DW12_NODELABEL DT_NODELABEL(ms_lis2dw12_accel)
 #define LIS2DW12_SENSOR_ID SENSOR_ID(LIS2DW12_NODELABEL)
-#define EMUL_LABEL DT_LABEL(DT_NODELABEL(lis2dw12_emul))
+#define LIS2DW12_EMUL_NODE DT_NODELABEL(lis2dw12_emul)
 
 #include <stdio.h>
 
@@ -37,7 +37,7 @@ enum lis2dw12_round_mode {
 
 static inline void lis2dw12_setup(void)
 {
-	lis2dw12_emul_reset(emul_get_binding(EMUL_LABEL));
+	lis2dw12_emul_reset(EMUL_DT_GET(LIS2DW12_EMUL_NODE));
 
 	/* Reset certain sensor struct values */
 	struct motion_sensor_t *ms = &motion_sensors[LIS2DW12_SENSOR_ID];
@@ -59,19 +59,20 @@ static void lis2dw12_after(void *state)
 
 ZTEST(lis2dw12, test_lis2dw12_init__fail_read_who_am_i)
 {
-	const struct emul *emul = emul_get_binding(EMUL_LABEL);
+	const struct emul *emul = EMUL_DT_GET(LIS2DW12_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_lis2dw12_get_i2c_common_data(emul);
 	struct motion_sensor_t *ms = &motion_sensors[LIS2DW12_SENSOR_ID];
 	int rv;
 
-	i2c_common_emul_set_read_fail_reg(lis2dw12_emul_to_i2c_emul(emul),
-					  LIS2DW12_WHO_AM_I_REG);
+	i2c_common_emul_set_read_fail_reg(common_data, LIS2DW12_WHO_AM_I_REG);
 	rv = ms->drv->init(ms);
 	zassert_equal(EC_ERROR_INVAL, rv, NULL);
 }
 
 ZTEST(lis2dw12, test_lis2dw12_init__fail_who_am_i)
 {
-	const struct emul *emul = emul_get_binding(EMUL_LABEL);
+	const struct emul *emul = EMUL_DT_GET(LIS2DW12_EMUL_NODE);
 	struct motion_sensor_t *ms = &motion_sensors[LIS2DW12_SENSOR_ID];
 	int rv;
 
@@ -85,11 +86,13 @@ ZTEST(lis2dw12, test_lis2dw12_init__fail_who_am_i)
 
 ZTEST(lis2dw12, test_lis2dw12_init__fail_write_soft_reset)
 {
-	const struct emul *emul = emul_get_binding(EMUL_LABEL);
+	const struct emul *emul = EMUL_DT_GET(LIS2DW12_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_lis2dw12_get_i2c_common_data(emul);
 	struct motion_sensor_t *ms = &motion_sensors[LIS2DW12_SENSOR_ID];
 	int rv;
 
-	i2c_common_emul_set_write_fail_reg(lis2dw12_emul_to_i2c_emul(emul),
+	i2c_common_emul_set_write_fail_reg(common_data,
 					   LIS2DW12_SOFT_RESET_ADDR);
 	rv = ms->drv->init(ms);
 	zassert_equal(EC_ERROR_INVAL, rv, NULL);
@@ -97,20 +100,22 @@ ZTEST(lis2dw12, test_lis2dw12_init__fail_write_soft_reset)
 
 ZTEST(lis2dw12, test_lis2dw12_init__timeout_read_soft_reset)
 {
-	const struct emul *emul = emul_get_binding(EMUL_LABEL);
+	const struct emul *emul = EMUL_DT_GET(LIS2DW12_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_lis2dw12_get_i2c_common_data(emul);
 	struct motion_sensor_t *ms = &motion_sensors[LIS2DW12_SENSOR_ID];
 	int rv;
 
-	i2c_common_emul_set_read_fail_reg(lis2dw12_emul_to_i2c_emul(emul),
+	i2c_common_emul_set_read_fail_reg(common_data,
 					  LIS2DW12_SOFT_RESET_ADDR);
 	rv = ms->drv->init(ms);
 	zassert_equal(EC_ERROR_TIMEOUT, rv, "init returned %d but expected %d",
 		      rv, EC_ERROR_TIMEOUT);
 }
 
-static int lis2dw12_test_mock_write_fail_set_bdu(struct i2c_emul *emul, int reg,
-						uint8_t val, int bytes,
-						void *data)
+static int lis2dw12_test_mock_write_fail_set_bdu(const struct emul *emul,
+						 int reg, uint8_t val,
+						 int bytes, void *data)
 {
 	if (reg == LIS2DW12_BDU_ADDR && bytes == 1 &&
 	    (val & LIS2DW12_BDU_MASK) != 0) {
@@ -121,28 +126,30 @@ static int lis2dw12_test_mock_write_fail_set_bdu(struct i2c_emul *emul, int reg,
 
 ZTEST(lis2dw12, test_lis2dw12_init__fail_set_bdu)
 {
-	const struct emul *emul = emul_get_binding(EMUL_LABEL);
+	const struct emul *emul = EMUL_DT_GET(LIS2DW12_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_lis2dw12_get_i2c_common_data(emul);
 	struct motion_sensor_t *ms = &motion_sensors[LIS2DW12_SENSOR_ID];
 	int rv;
 
-	i2c_common_emul_set_write_func(lis2dw12_emul_to_i2c_emul(emul),
-				      lis2dw12_test_mock_write_fail_set_bdu,
-				      NULL);
+	i2c_common_emul_set_write_func(
+		common_data, lis2dw12_test_mock_write_fail_set_bdu, NULL);
 	rv = ms->drv->init(ms);
 	zassert_equal(EC_ERROR_INVAL, rv, "init returned %d but expected %d",
 		      rv, EC_ERROR_INVAL);
 	zassert_true(lis2dw12_emul_get_soft_reset_count(emul) > 0,
-		      "expected at least one soft reset");
+		     "expected at least one soft reset");
 }
 
 ZTEST(lis2dw12, test_lis2dw12_init__fail_set_lir)
 {
-	const struct emul *emul = emul_get_binding(EMUL_LABEL);
+	const struct emul *emul = EMUL_DT_GET(LIS2DW12_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_lis2dw12_get_i2c_common_data(emul);
 	struct motion_sensor_t *ms = &motion_sensors[LIS2DW12_SENSOR_ID];
 	int rv;
 
-	i2c_common_emul_set_read_fail_reg(lis2dw12_emul_to_i2c_emul(emul),
-					  LIS2DW12_LIR_ADDR);
+	i2c_common_emul_set_read_fail_reg(common_data, LIS2DW12_LIR_ADDR);
 
 	rv = ms->drv->init(ms);
 	zassert_equal(EC_ERROR_INVAL, rv, "init returned %d but expected %d",
@@ -151,7 +158,7 @@ ZTEST(lis2dw12, test_lis2dw12_init__fail_set_lir)
 		     "expected at least one soft reset");
 }
 
-static int lis2dw12_test_mock_write_fail_set_power_mode(struct i2c_emul *emul,
+static int lis2dw12_test_mock_write_fail_set_power_mode(const struct emul *emul,
 							int reg, uint8_t val,
 							int bytes, void *data)
 {
@@ -165,13 +172,15 @@ static int lis2dw12_test_mock_write_fail_set_power_mode(struct i2c_emul *emul,
 
 ZTEST(lis2dw12, test_lis2dw12_init__fail_set_power_mode)
 {
-	const struct emul *emul = emul_get_binding(EMUL_LABEL);
+	const struct emul *emul = EMUL_DT_GET(LIS2DW12_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_lis2dw12_get_i2c_common_data(emul);
 	struct motion_sensor_t *ms = &motion_sensors[LIS2DW12_SENSOR_ID];
 	int rv;
 
 	i2c_common_emul_set_write_func(
-		lis2dw12_emul_to_i2c_emul(emul),
-		lis2dw12_test_mock_write_fail_set_power_mode, NULL);
+		common_data, lis2dw12_test_mock_write_fail_set_power_mode,
+		NULL);
 
 	rv = ms->drv->init(ms);
 	zassert_equal(EC_ERROR_INVAL, rv, "init returned %d but expected %d",
@@ -182,7 +191,7 @@ ZTEST(lis2dw12, test_lis2dw12_init__fail_set_power_mode)
 
 ZTEST(lis2dw12, test_lis2dw12_init__success)
 {
-	const struct emul *emul = emul_get_binding(EMUL_LABEL);
+	const struct emul *emul = EMUL_DT_GET(LIS2DW12_EMUL_NODE);
 	struct motion_sensor_t *ms = &motion_sensors[LIS2DW12_SENSOR_ID];
 	struct stprivate_data *drvdata = ms->drv_data;
 
@@ -200,7 +209,9 @@ ZTEST(lis2dw12, test_lis2dw12_init__success)
 
 ZTEST(lis2dw12, test_lis2dw12_set_power_mode)
 {
-	const struct emul *emul = emul_get_binding(EMUL_LABEL);
+	const struct emul *emul = EMUL_DT_GET(LIS2DW12_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_lis2dw12_get_i2c_common_data(emul);
 	struct motion_sensor_t *ms = &motion_sensors[LIS2DW12_SENSOR_ID];
 	int rv;
 
@@ -216,8 +227,7 @@ ZTEST(lis2dw12, test_lis2dw12_set_power_mode)
 		      EC_ERROR_UNIMPLEMENTED, rv);
 
 	/* Part 3: attempt to set mode but cannot modify reg. */
-	i2c_common_emul_set_read_fail_reg(lis2dw12_emul_to_i2c_emul(emul),
-					  LIS2DW12_ACC_MODE_ADDR);
+	i2c_common_emul_set_read_fail_reg(common_data, LIS2DW12_ACC_MODE_ADDR);
 	rv = lis2dw12_set_power_mode(ms, LIS2DW12_LOW_POWER,
 				     LIS2DW12_LOW_POWER_MODE_2);
 	zassert_equal(rv, EC_ERROR_INVAL, "Expected %d but got %d",
@@ -226,7 +236,9 @@ ZTEST(lis2dw12, test_lis2dw12_set_power_mode)
 
 ZTEST(lis2dw12, test_lis2dw12_set_range)
 {
-	const struct emul *emul = emul_get_binding(EMUL_LABEL);
+	const struct emul *emul = EMUL_DT_GET(LIS2DW12_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_lis2dw12_get_i2c_common_data(emul);
 	struct motion_sensor_t *ms = &motion_sensors[LIS2DW12_SENSOR_ID];
 	int rv;
 
@@ -241,8 +253,7 @@ ZTEST(lis2dw12, test_lis2dw12_set_range)
 		      ms->current_range);
 
 	/* Part 2: Error accessing register */
-	i2c_common_emul_set_read_fail_reg(lis2dw12_emul_to_i2c_emul(emul),
-					  LIS2DW12_FS_ADDR);
+	i2c_common_emul_set_read_fail_reg(common_data, LIS2DW12_FS_ADDR);
 	rv = ms->drv->set_range(ms, LIS2DW12_ACCEL_FS_MAX_VAL, 0);
 	zassert_equal(rv, EC_ERROR_INVAL, "Expected %d but got %d",
 		      EC_ERROR_INVAL, rv);
@@ -250,8 +261,7 @@ ZTEST(lis2dw12, test_lis2dw12_set_range)
 
 ZTEST(lis2dw12, test_lis2dw12_set_rate)
 {
-	const struct emul *emul = emul_get_binding(EMUL_LABEL);
-	struct i2c_emul *i2c_emul = lis2dw12_emul_to_i2c_emul(emul);
+	const struct emul *emul = EMUL_DT_GET(LIS2DW12_EMUL_NODE);
 	struct motion_sensor_t *ms = &motion_sensors[LIS2DW12_SENSOR_ID];
 	struct stprivate_data *drv_data = ms->drv_data;
 	int rv;
@@ -259,11 +269,9 @@ ZTEST(lis2dw12, test_lis2dw12_set_rate)
 	/* Part 1: Turn off sensor with rate=0 */
 	rv = ms->drv->set_data_rate(ms, 0, 0);
 
-	zassert_equal(lis2dw12_emul_peek_odr(i2c_emul),
-		      LIS2DW12_ODR_POWER_OFF_VAL,
+	zassert_equal(lis2dw12_emul_peek_odr(emul), LIS2DW12_ODR_POWER_OFF_VAL,
 		      "Output data rate should be %d but got %d",
-		      LIS2DW12_ODR_POWER_OFF_VAL,
-		      lis2dw12_emul_peek_odr(i2c_emul));
+		      LIS2DW12_ODR_POWER_OFF_VAL, lis2dw12_emul_peek_odr(emul));
 	zassert_equal(drv_data->base.odr, LIS2DW12_ODR_POWER_OFF_VAL,
 		      "Output data rate should be %d but got %d",
 		      LIS2DW12_ODR_POWER_OFF_VAL, drv_data->base.odr);
@@ -319,7 +327,7 @@ ZTEST(lis2dw12, test_lis2dw12_set_rate)
 			test_params[i].expected_norm_rate, drv_data->base.odr);
 
 		/* Read ODR and mode bits back from CTRL1 register */
-		uint8_t odr_bits = lis2dw12_emul_peek_odr(i2c_emul);
+		uint8_t odr_bits = lis2dw12_emul_peek_odr(emul);
 
 		zassert_equal(
 			odr_bits, test_params[i].expected_reg_val,
@@ -332,8 +340,8 @@ ZTEST(lis2dw12, test_lis2dw12_set_rate)
 		 * 200,000mHz
 		 */
 
-		uint8_t mode_bits = lis2dw12_emul_peek_mode(i2c_emul);
-		uint8_t lpmode_bits = lis2dw12_emul_peek_lpmode(i2c_emul);
+		uint8_t mode_bits = lis2dw12_emul_peek_mode(emul);
+		uint8_t lpmode_bits = lis2dw12_emul_peek_lpmode(emul);
 
 		if (odr_bits > LIS2DW12_ODR_200HZ_VAL) {
 			/* High performance mode, LP mode immaterial */
@@ -357,8 +365,10 @@ ZTEST(lis2dw12, test_lis2dw12_set_rate)
 
 ZTEST(lis2dw12, test_lis2dw12_read)
 {
-	const struct emul *emul = emul_get_binding(EMUL_LABEL);
-	struct i2c_emul *i2c_emul = lis2dw12_emul_to_i2c_emul(emul);
+	const struct emul *emul = EMUL_DT_GET(LIS2DW12_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_lis2dw12_get_i2c_common_data(emul);
+
 	struct motion_sensor_t *ms = &motion_sensors[LIS2DW12_SENSOR_ID];
 	struct stprivate_data *drvdata = ms->drv_data;
 	intv3_t sample = { 0, 0, 0 };
@@ -376,7 +386,7 @@ ZTEST(lis2dw12, test_lis2dw12_read)
 	 * ready bit
 	 */
 
-	i2c_common_emul_set_read_fail_reg(i2c_emul, LIS2DW12_STATUS_REG);
+	i2c_common_emul_set_read_fail_reg(common_data, LIS2DW12_STATUS_REG);
 
 	rv = ms->drv->read(ms, sample);
 
@@ -388,7 +398,7 @@ ZTEST(lis2dw12, test_lis2dw12_read)
 	 * case, the driver should return the reading in from `ms->raw_xyz`
 	 */
 
-	i2c_common_emul_set_read_fail_reg(i2c_emul,
+	i2c_common_emul_set_read_fail_reg(common_data,
 					  I2C_COMMON_EMUL_NO_FAIL_REG);
 	lis2dw12_emul_clear_accel_reading(emul);
 	ms->raw_xyz[X] = 123;
@@ -406,7 +416,7 @@ ZTEST(lis2dw12, test_lis2dw12_read)
 	 */
 	intv3_t fake_sample = { 100, 200, 300 };
 
-	i2c_common_emul_set_read_fail_reg(i2c_emul, LIS2DW12_OUT_X_L_ADDR);
+	i2c_common_emul_set_read_fail_reg(common_data, LIS2DW12_OUT_X_L_ADDR);
 	lis2dw12_emul_set_accel_reading(emul, fake_sample);
 
 	rv = ms->drv->read(ms, sample);
@@ -425,11 +435,11 @@ ZTEST(lis2dw12, test_lis2dw12_read)
 		 * output
 		 */
 
-		expected_sample[i] = fake_sample[i] *
-				    (1 << (16 - LIS2DW12_RESOLUTION));
+		expected_sample[i] =
+			fake_sample[i] * (1 << (16 - LIS2DW12_RESOLUTION));
 	}
 
-	i2c_common_emul_set_read_fail_reg(i2c_emul,
+	i2c_common_emul_set_read_fail_reg(common_data,
 					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	lis2dw12_emul_set_accel_reading(emul, fake_sample);
diff --git a/zephyr/test/drivers/src/ln9310.c b/zephyr/test/drivers/default/src/ln9310.c
index e4bf37c4bd..326e8480ef 100644
--- a/zephyr/test/drivers/src/ln9310.c
+++ b/zephyr/test/drivers/default/src/ln9310.c
@@ -1,12 +1,12 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <ztest.h>
+#include <zephyr/ztest.h>
 #include <zephyr/drivers/emul.h>
 #include <zephyr/kernel.h>
-#include <ztest_assert.h>
+#include <zephyr/ztest_assert.h>
 #include <zephyr/drivers/i2c_emul.h>
 
 #include "driver/ln9310.h"
@@ -21,6 +21,8 @@
  */
 #define TEST_DELAY_MS 50
 
+#define EMUL_LN9310_NODE DT_NODELABEL(ln9310)
+
 /*
  * Chip revisions below LN9310_BC_STS_C_CHIP_REV_FIXED require an alternative
  * software startup to properly initialize and power up.
@@ -30,12 +32,11 @@
 
 ZTEST(ln9310, test_ln9310_read_chip_fails)
 {
-	const struct emul *emulator =
-		emul_get_binding(DT_LABEL(DT_NODELABEL(ln9310)));
-	struct i2c_emul *i2c_emul = ln9310_emul_get_i2c_emul(emulator);
+	const struct emul *emulator = EMUL_DT_GET(EMUL_LN9310_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_ln9310_get_i2c_common_data(emulator);
 
 	zassert_not_null(emulator, NULL);
-	zassert_not_null(i2c_emul, NULL);
 
 	ln9310_emul_set_context(emulator);
 	ln9310_emul_reset(emulator);
@@ -43,7 +44,7 @@ ZTEST(ln9310, test_ln9310_read_chip_fails)
 	ln9310_emul_set_battery_cell_type(emulator, BATTERY_CELL_TYPE_2S);
 	ln9310_emul_set_version(emulator, LN9310_BC_STS_C_CHIP_REV_FIXED);
 
-	i2c_common_emul_set_read_fail_reg(i2c_emul, LN9310_REG_BC_STS_C);
+	i2c_common_emul_set_read_fail_reg(common_data, LN9310_REG_BC_STS_C);
 
 	zassert_true(ln9310_init() != 0, NULL);
 	zassert_false(ln9310_emul_is_init(emulator), NULL);
@@ -52,14 +53,13 @@ ZTEST(ln9310, test_ln9310_read_chip_fails)
 	k_msleep(TEST_DELAY_MS);
 	zassert_false(ln9310_power_good(), NULL);
 
-	i2c_common_emul_set_read_fail_reg(i2c_emul,
+	i2c_common_emul_set_read_fail_reg(common_data,
 					  I2C_COMMON_EMUL_NO_FAIL_REG);
 }
 
 ZTEST(ln9310, test_ln9310_2s_powers_up)
 {
-	const struct emul *emulator =
-		emul_get_binding(DT_LABEL(DT_NODELABEL(ln9310)));
+	const struct emul *emulator = EMUL_DT_GET(EMUL_LN9310_NODE);
 
 	zassert_not_null(emulator, NULL);
 
@@ -83,8 +83,7 @@ ZTEST(ln9310, test_ln9310_2s_powers_up)
 
 ZTEST(ln9310, test_ln9310_3s_powers_up)
 {
-	const struct emul *emulator =
-		emul_get_binding(DT_LABEL(DT_NODELABEL(ln9310)));
+	const struct emul *emulator = EMUL_DT_GET(EMUL_LN9310_NODE);
 
 	zassert_not_null(emulator, NULL);
 
@@ -111,7 +110,7 @@ struct startup_workaround_data {
 	bool startup_workaround_should_fail;
 };
 
-static int mock_write_fn_intercept_startup_workaround(struct i2c_emul *emul,
+static int mock_write_fn_intercept_startup_workaround(const struct emul *emul,
 						      int reg, uint8_t val,
 						      int bytes, void *data)
 {
@@ -134,10 +133,9 @@ static int mock_write_fn_intercept_startup_workaround(struct i2c_emul *emul,
 
 ZTEST(ln9310, test_ln9310_2s_cfly_precharge_startup)
 {
-	const struct emul *emulator =
-		emul_get_binding(DT_LABEL(DT_NODELABEL(ln9310)));
-
-	struct i2c_emul *emul = ln9310_emul_get_i2c_emul(emulator);
+	const struct emul *emulator = EMUL_DT_GET(EMUL_LN9310_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_ln9310_get_i2c_common_data(emulator);
 
 	struct startup_workaround_data test_data = {
 		.startup_workaround_attempted = false,
@@ -160,7 +158,8 @@ ZTEST(ln9310, test_ln9310_2s_cfly_precharge_startup)
 	zassert_false(ln9310_power_good(), NULL);
 
 	i2c_common_emul_set_write_func(
-		emul, mock_write_fn_intercept_startup_workaround, &test_data);
+		common_data, mock_write_fn_intercept_startup_workaround,
+		&test_data);
 
 	ln9310_software_enable(true);
 	zassert_true(test_data.startup_workaround_attempted, NULL);
@@ -175,14 +174,14 @@ ZTEST(ln9310, test_ln9310_2s_cfly_precharge_startup)
 	k_msleep(TEST_DELAY_MS);
 	zassert_false(ln9310_power_good(), NULL);
 
-	i2c_common_emul_set_write_func(emul, NULL, NULL);
+	i2c_common_emul_set_write_func(common_data, NULL, NULL);
 }
 
 ZTEST(ln9310, test_ln9310_3s_cfly_precharge_startup)
 {
-	const struct emul *emulator =
-		emul_get_binding(DT_LABEL(DT_NODELABEL(ln9310)));
-	struct i2c_emul *emul = ln9310_emul_get_i2c_emul(emulator);
+	const struct emul *emulator = EMUL_DT_GET(EMUL_LN9310_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_ln9310_get_i2c_common_data(emulator);
 
 	struct startup_workaround_data test_data = {
 		.startup_workaround_attempted = false,
@@ -205,7 +204,8 @@ ZTEST(ln9310, test_ln9310_3s_cfly_precharge_startup)
 	zassert_false(ln9310_power_good(), NULL);
 
 	i2c_common_emul_set_write_func(
-		emul, mock_write_fn_intercept_startup_workaround, &test_data);
+		common_data, mock_write_fn_intercept_startup_workaround,
+		&test_data);
 
 	ln9310_software_enable(true);
 	zassert_true(test_data.startup_workaround_attempted, NULL);
@@ -220,15 +220,14 @@ ZTEST(ln9310, test_ln9310_3s_cfly_precharge_startup)
 	k_msleep(TEST_DELAY_MS);
 	zassert_false(ln9310_power_good(), NULL);
 
-	i2c_common_emul_set_write_func(emul, NULL, NULL);
+	i2c_common_emul_set_write_func(common_data, NULL, NULL);
 }
 
 ZTEST(ln9310, test_ln9310_cfly_precharge_exceeds_retries)
 {
-	const struct emul *emulator =
-		emul_get_binding(DT_LABEL(DT_NODELABEL(ln9310)));
-
-	struct i2c_emul *emul = ln9310_emul_get_i2c_emul(emulator);
+	const struct emul *emulator = EMUL_DT_GET(EMUL_LN9310_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_ln9310_get_i2c_common_data(emulator);
 
 	struct startup_workaround_data test_data = {
 		.startup_workaround_attempted = false,
@@ -255,7 +254,8 @@ ZTEST(ln9310, test_ln9310_cfly_precharge_exceeds_retries)
 	zassert_false(ln9310_power_good(), NULL);
 
 	i2c_common_emul_set_write_func(
-		emul, mock_write_fn_intercept_startup_workaround, &test_data);
+		common_data, mock_write_fn_intercept_startup_workaround,
+		&test_data);
 
 	ln9310_software_enable(true);
 	zassert_true(test_data.startup_workaround_attempted, NULL);
@@ -264,13 +264,12 @@ ZTEST(ln9310, test_ln9310_cfly_precharge_exceeds_retries)
 	k_msleep(TEST_DELAY_MS);
 	zassert_false(ln9310_power_good(), NULL);
 
-	i2c_common_emul_set_write_func(emul, NULL, NULL);
+	i2c_common_emul_set_write_func(common_data, NULL, NULL);
 }
 
 ZTEST(ln9310, test_ln9310_battery_unknown)
 {
-	const struct emul *emulator =
-		emul_get_binding(DT_LABEL(DT_NODELABEL(ln9310)));
+	const struct emul *emulator = EMUL_DT_GET(EMUL_LN9310_NODE);
 
 	zassert_not_null(emulator, NULL);
 
@@ -299,12 +298,11 @@ ZTEST(ln9310, test_ln9310_battery_unknown)
 
 ZTEST(ln9310, test_ln9310_2s_battery_read_fails)
 {
-	const struct emul *emulator =
-		emul_get_binding(DT_LABEL(DT_NODELABEL(ln9310)));
-	struct i2c_emul *i2c_emul = ln9310_emul_get_i2c_emul(emulator);
+	const struct emul *emulator = EMUL_DT_GET(EMUL_LN9310_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_ln9310_get_i2c_common_data(emulator);
 
 	zassert_not_null(emulator, NULL);
-	zassert_not_null(i2c_emul, NULL);
 
 	ln9310_emul_set_context(emulator);
 	ln9310_emul_reset(emulator);
@@ -312,7 +310,7 @@ ZTEST(ln9310, test_ln9310_2s_battery_read_fails)
 	ln9310_emul_set_battery_cell_type(emulator, BATTERY_CELL_TYPE_2S);
 	ln9310_emul_set_version(emulator, LN9310_BC_STS_C_CHIP_REV_FIXED);
 
-	i2c_common_emul_set_read_fail_reg(i2c_emul, LN9310_REG_BC_STS_B);
+	i2c_common_emul_set_read_fail_reg(common_data, LN9310_REG_BC_STS_B);
 
 	zassert_true(ln9310_init() != 0, NULL);
 	zassert_false(ln9310_emul_is_init(emulator), NULL);
@@ -326,21 +324,20 @@ ZTEST(ln9310, test_ln9310_2s_battery_read_fails)
 	ln9310_emul_set_battery_cell_type(emulator, BATTERY_CELL_TYPE_2S);
 	ln9310_emul_set_version(emulator, LN9310_BC_STS_C_CHIP_REV_FIXED);
 
-	i2c_common_emul_set_read_fail_reg(i2c_emul, LN9310_REG_TRACK_CTRL);
+	i2c_common_emul_set_read_fail_reg(common_data, LN9310_REG_TRACK_CTRL);
 
 	zassert_false(ln9310_init() == 0, NULL);
-	i2c_common_emul_set_read_fail_reg(i2c_emul,
+	i2c_common_emul_set_read_fail_reg(common_data,
 					  I2C_COMMON_EMUL_NO_FAIL_REG);
 }
 
 ZTEST(ln9310, test_ln9310_lion_ctrl_reg_fails)
 {
-	const struct emul *emulator =
-		emul_get_binding(DT_LABEL(DT_NODELABEL(ln9310)));
-	struct i2c_emul *i2c_emul = ln9310_emul_get_i2c_emul(emulator);
+	const struct emul *emulator = EMUL_DT_GET(EMUL_LN9310_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_ln9310_get_i2c_common_data(emulator);
 
 	zassert_not_null(emulator, NULL);
-	zassert_not_null(i2c_emul, NULL);
 
 	ln9310_emul_set_context(emulator);
 	ln9310_emul_reset(emulator);
@@ -348,7 +345,7 @@ ZTEST(ln9310, test_ln9310_lion_ctrl_reg_fails)
 	ln9310_emul_set_battery_cell_type(emulator, BATTERY_CELL_TYPE_2S);
 	ln9310_emul_set_version(emulator, LN9310_BC_STS_C_CHIP_REV_FIXED);
 
-	i2c_common_emul_set_read_fail_reg(i2c_emul, LN9310_REG_LION_CTRL);
+	i2c_common_emul_set_read_fail_reg(common_data, LN9310_REG_LION_CTRL);
 
 	zassert_true(ln9310_init() != 0, NULL);
 	zassert_false(ln9310_emul_is_init(emulator), NULL);
@@ -362,17 +359,16 @@ ZTEST(ln9310, test_ln9310_lion_ctrl_reg_fails)
 	ln9310_software_enable(true);
 	zassert_false(ln9310_power_good(), NULL);
 
-	i2c_common_emul_set_read_fail_reg(i2c_emul,
+	i2c_common_emul_set_read_fail_reg(common_data,
 					  I2C_COMMON_EMUL_NO_FAIL_REG);
 }
 
-
 struct precharge_timeout_data {
 	timestamp_t time_to_mock;
 	bool handled_clearing_standby_en_bit_timeout;
 };
 
-static int mock_intercept_startup_ctrl_reg(struct i2c_emul *emul, int reg,
+static int mock_intercept_startup_ctrl_reg(const struct emul *emulator, int reg,
 					   uint8_t val, int bytes, void *data)
 {
 	struct precharge_timeout_data *test_data = data;
@@ -397,9 +393,9 @@ static int mock_intercept_startup_ctrl_reg(struct i2c_emul *emul, int reg,
 
 ZTEST(ln9310, test_ln9310_cfly_precharge_timesout)
 {
-	const struct emul *emulator =
-		emul_get_binding(DT_LABEL(DT_NODELABEL(ln9310)));
-	struct i2c_emul *i2c_emul = ln9310_emul_get_i2c_emul(emulator);
+	const struct emul *emulator = EMUL_DT_GET(EMUL_LN9310_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_ln9310_get_i2c_common_data(emulator);
 	struct precharge_timeout_data test_data = {
 		.time_to_mock = {
 			.val = -1,
@@ -412,7 +408,6 @@ ZTEST(ln9310, test_ln9310_cfly_precharge_timesout)
 	};
 
 	zassert_not_null(emulator, NULL);
-	zassert_not_null(i2c_emul, NULL);
 
 	ln9310_emul_set_context(emulator);
 	ln9310_emul_reset(emulator);
@@ -429,7 +424,7 @@ ZTEST(ln9310, test_ln9310_cfly_precharge_timesout)
 	zassert_false(ln9310_power_good(), NULL);
 
 	i2c_common_emul_set_write_func(
-		i2c_emul, mock_intercept_startup_ctrl_reg, &test_data);
+		common_data, mock_intercept_startup_ctrl_reg, &test_data);
 
 	ln9310_software_enable(true);
 	/* TODO(b/201420132) */
@@ -438,7 +433,7 @@ ZTEST(ln9310, test_ln9310_cfly_precharge_timesout)
 	/* It only times out on one attempt, it should subsequently startup */
 	zassert_true(ln9310_power_good(), NULL);
 
-	i2c_common_emul_set_write_func(i2c_emul, NULL, NULL);
+	i2c_common_emul_set_write_func(common_data, NULL, NULL);
 }
 
 struct reg_to_fail_data {
@@ -446,7 +441,7 @@ struct reg_to_fail_data {
 	int reg_access_fail_countdown;
 };
 
-static int mock_read_intercept_reg_to_fail(struct i2c_emul *emul, int reg,
+static int mock_read_intercept_reg_to_fail(const struct emul *emul, int reg,
 					   uint8_t *val, int bytes, void *data)
 {
 	struct reg_to_fail_data *test_data = data;
@@ -461,16 +456,15 @@ static int mock_read_intercept_reg_to_fail(struct i2c_emul *emul, int reg,
 
 ZTEST(ln9310, test_ln9310_interrupt_reg_fail)
 {
-	const struct emul *emulator =
-		emul_get_binding(DT_LABEL(DT_NODELABEL(ln9310)));
-	struct i2c_emul *i2c_emul = ln9310_emul_get_i2c_emul(emulator);
+	const struct emul *emulator = EMUL_DT_GET(EMUL_LN9310_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_ln9310_get_i2c_common_data(emulator);
 	struct reg_to_fail_data test_data = {
 		.reg_access_to_fail = 0,
 		.reg_access_fail_countdown = 0,
 	};
 
 	zassert_not_null(emulator, NULL);
-	zassert_not_null(i2c_emul, NULL);
 
 	ln9310_emul_set_context(emulator);
 	ln9310_emul_reset(emulator);
@@ -482,7 +476,7 @@ ZTEST(ln9310, test_ln9310_interrupt_reg_fail)
 	zassert_true(ln9310_emul_is_init(emulator), NULL);
 
 	i2c_common_emul_set_read_func(
-		i2c_emul, mock_read_intercept_reg_to_fail, &test_data);
+		common_data, mock_read_intercept_reg_to_fail, &test_data);
 
 	/* Fail in beginning of software enable */
 	test_data.reg_access_to_fail = LN9310_REG_INT1;
@@ -504,21 +498,20 @@ ZTEST(ln9310, test_ln9310_interrupt_reg_fail)
 	zassert_false(ln9310_power_good(), NULL);
 	zassert_true(test_data.reg_access_fail_countdown <= 0, NULL);
 
-	i2c_common_emul_set_read_func(i2c_emul, NULL, NULL);
+	i2c_common_emul_set_read_func(common_data, NULL, NULL);
 }
 
 ZTEST(ln9310, test_ln9310_sys_sts_reg_fail)
 {
-	const struct emul *emulator =
-		emul_get_binding(DT_LABEL(DT_NODELABEL(ln9310)));
-	struct i2c_emul *i2c_emul = ln9310_emul_get_i2c_emul(emulator);
+	const struct emul *emulator = EMUL_DT_GET(EMUL_LN9310_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_ln9310_get_i2c_common_data(emulator);
 	struct reg_to_fail_data test_data = {
 		.reg_access_to_fail = 0,
 		.reg_access_fail_countdown = 0,
 	};
 
 	zassert_not_null(emulator, NULL);
-	zassert_not_null(i2c_emul, NULL);
 
 	ln9310_emul_set_context(emulator);
 	ln9310_emul_reset(emulator);
@@ -530,7 +523,7 @@ ZTEST(ln9310, test_ln9310_sys_sts_reg_fail)
 	zassert_true(ln9310_emul_is_init(emulator), NULL);
 
 	i2c_common_emul_set_read_func(
-		i2c_emul, &mock_read_intercept_reg_to_fail, &test_data);
+		common_data, &mock_read_intercept_reg_to_fail, &test_data);
 
 	/* Register only read once and in the interrupt handler */
 	test_data.reg_access_to_fail = LN9310_REG_SYS_STS;
@@ -544,7 +537,7 @@ ZTEST(ln9310, test_ln9310_sys_sts_reg_fail)
 	zassert_false(ln9310_power_good(), NULL);
 	zassert_true(test_data.reg_access_fail_countdown <= 0, NULL);
 
-	i2c_common_emul_set_read_func(i2c_emul, NULL, NULL);
+	i2c_common_emul_set_read_func(common_data, NULL, NULL);
 }
 
 struct reg_to_intercept {
@@ -552,7 +545,7 @@ struct reg_to_intercept {
 	uint8_t replace_val;
 };
 
-static int mock_read_interceptor(struct i2c_emul *emul, int reg, uint8_t *val,
+static int mock_read_interceptor(const struct emul *emul, int reg, uint8_t *val,
 				 int bytes, void *data)
 {
 	struct reg_to_intercept *test_data = data;
@@ -567,16 +560,15 @@ static int mock_read_interceptor(struct i2c_emul *emul, int reg, uint8_t *val,
 
 ZTEST(ln9310, test_ln9310_reset_explicit_detected_startup)
 {
-	const struct emul *emulator =
-		emul_get_binding(DT_LABEL(DT_NODELABEL(ln9310)));
-	struct i2c_emul *i2c_emul = ln9310_emul_get_i2c_emul(emulator);
+	const struct emul *emulator = EMUL_DT_GET(EMUL_LN9310_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_ln9310_get_i2c_common_data(emulator);
 	struct reg_to_intercept test_data = {
 		.reg = LN9310_REG_LION_CTRL,
 		.replace_val = 0,
 	};
 
 	zassert_not_null(emulator, NULL);
-	zassert_not_null(i2c_emul, NULL);
 
 	ln9310_emul_set_context(emulator);
 	ln9310_emul_reset(emulator);
@@ -587,7 +579,7 @@ ZTEST(ln9310, test_ln9310_reset_explicit_detected_startup)
 	zassert_ok(ln9310_init(), NULL);
 	zassert_true(ln9310_emul_is_init(emulator), NULL);
 
-	i2c_common_emul_set_read_func(i2c_emul, &mock_read_interceptor,
+	i2c_common_emul_set_read_func(common_data, &mock_read_interceptor,
 				      &test_data);
 
 	ln9310_software_enable(true);
@@ -597,21 +589,20 @@ ZTEST(ln9310, test_ln9310_reset_explicit_detected_startup)
 
 	zassert_true(ln9310_power_good(), NULL);
 
-	i2c_common_emul_set_read_func(i2c_emul, NULL, NULL);
+	i2c_common_emul_set_read_func(common_data, NULL, NULL);
 }
 
 ZTEST(ln9310, test_ln9310_update_startup_seq_fails)
 {
-	const struct emul *emulator =
-		emul_get_binding(DT_LABEL(DT_NODELABEL(ln9310)));
-	struct i2c_emul *i2c_emul = ln9310_emul_get_i2c_emul(emulator);
+	const struct emul *emulator = EMUL_DT_GET(EMUL_LN9310_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_ln9310_get_i2c_common_data(emulator);
 	struct reg_to_fail_data test_data = {
 		.reg_access_to_fail = LN9310_REG_CFG_4,
 		.reg_access_fail_countdown = 1,
 	};
 
 	zassert_not_null(emulator, NULL);
-	zassert_not_null(i2c_emul, NULL);
 
 	ln9310_emul_set_context(emulator);
 	ln9310_emul_reset(emulator);
@@ -622,7 +613,7 @@ ZTEST(ln9310, test_ln9310_update_startup_seq_fails)
 				REQUIRES_CFLY_PRECHARGE_STARTUP_CHIP_REV);
 
 	i2c_common_emul_set_read_func(
-		i2c_emul, &mock_read_intercept_reg_to_fail, &test_data);
+		common_data, &mock_read_intercept_reg_to_fail, &test_data);
 
 	zassert_false(ln9310_init() == 0, NULL);
 	zassert_false(ln9310_emul_is_init(emulator), NULL);
@@ -635,21 +626,20 @@ ZTEST(ln9310, test_ln9310_update_startup_seq_fails)
 	zassert_false(ln9310_power_good(), NULL);
 	zassert_true(test_data.reg_access_fail_countdown <= 0, NULL);
 
-	i2c_common_emul_set_read_func(i2c_emul, NULL, NULL);
+	i2c_common_emul_set_read_func(common_data, NULL, NULL);
 }
 
 ZTEST(ln9310, test_ln9310_state_change_only_on_mode_change_interrupt)
 {
-	const struct emul *emulator =
-		emul_get_binding(DT_LABEL(DT_NODELABEL(ln9310)));
-	struct i2c_emul *i2c_emul = ln9310_emul_get_i2c_emul(emulator);
+	const struct emul *emulator = EMUL_DT_GET(EMUL_LN9310_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_ln9310_get_i2c_common_data(emulator);
 	struct reg_to_intercept test_data = {
 		.reg = LN9310_REG_INT1,
 		.replace_val = 0,
 	};
 
 	zassert_not_null(emulator, NULL);
-	zassert_not_null(i2c_emul, NULL);
 
 	ln9310_emul_set_context(emulator);
 	ln9310_emul_reset(emulator);
@@ -660,7 +650,7 @@ ZTEST(ln9310, test_ln9310_state_change_only_on_mode_change_interrupt)
 	zassert_ok(ln9310_init(), NULL);
 	zassert_true(ln9310_emul_is_init(emulator), NULL);
 
-	i2c_common_emul_set_read_func(i2c_emul, &mock_read_interceptor,
+	i2c_common_emul_set_read_func(common_data, &mock_read_interceptor,
 				      &test_data);
 
 	ln9310_software_enable(true);
@@ -670,7 +660,7 @@ ZTEST(ln9310, test_ln9310_state_change_only_on_mode_change_interrupt)
 
 	zassert_false(ln9310_power_good(), NULL);
 
-	i2c_common_emul_set_read_func(i2c_emul, NULL, NULL);
+	i2c_common_emul_set_read_func(common_data, NULL, NULL);
 }
 
 static inline void reset_ln9310_state(void)
diff --git a/zephyr/test/drivers/default/src/locate_chip.c b/zephyr/test/drivers/default/src/locate_chip.c
new file mode 100644
index 0000000000..6842543971
--- /dev/null
+++ b/zephyr/test/drivers/default/src/locate_chip.c
@@ -0,0 +1,134 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/fff.h>
+#include <zephyr/shell/shell.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "host_command.h"
+
+/**
+ * @brief TestPurpose: test the TCPC locate valid case.
+ */
+ZTEST_USER(locate_chip, test_hc_locate_chip_tcpc)
+{
+	int ret;
+	struct ec_params_locate_chip p;
+	struct ec_response_locate_chip r;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_LOCATE_CHIP, 0, r, p);
+
+	p.type = EC_CHIP_TYPE_TCPC;
+	p.index = 0;
+
+	ret = host_command_process(&args);
+
+	zassert_equal(ret, EC_RES_SUCCESS, "Unexpected return value: %d", ret);
+	zassert_equal(r.bus_type, EC_BUS_TYPE_I2C, "Unexpected bus_type: %d",
+		      r.bus_type);
+	zassert_equal(r.i2c_info.port, 2, "Unexpected port: %d",
+		      r.i2c_info.port);
+	zassert_equal(r.i2c_info.addr_flags, 0x82, "Unexpected addr_flags: %d",
+		      r.i2c_info.addr_flags);
+
+	p.type = EC_CHIP_TYPE_TCPC;
+	p.index = 1;
+
+	ret = host_command_process(&args);
+
+	zassert_equal(ret, EC_RES_SUCCESS, "Unexpected return value: %d", ret);
+	zassert_equal(r.bus_type, EC_BUS_TYPE_I2C, "Unexpected bus_type: %d",
+		      r.bus_type);
+	zassert_equal(r.i2c_info.port, 3, "Unexpected port: %d",
+		      r.i2c_info.port);
+	zassert_equal(r.i2c_info.addr_flags, 0x0b, "Unexpected addr_flags: %d",
+		      r.i2c_info.addr_flags);
+}
+
+/**
+ * @brief TestPurpose: test the TCPC index overflow case.
+ */
+ZTEST_USER(locate_chip, test_hc_locate_chip_tcpc_overflow)
+{
+	int ret;
+	struct ec_params_locate_chip p;
+	struct ec_response_locate_chip r;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_LOCATE_CHIP, 0, r, p);
+
+	p.type = EC_CHIP_TYPE_TCPC;
+	p.index = 10;
+
+	ret = host_command_process(&args);
+
+	zassert_equal(ret, EC_RES_OVERFLOW, "Unexpected return value: %d", ret);
+}
+
+/**
+ * @brief TestPurpose: test the EEPROM locate valid case.
+ */
+ZTEST_USER(locate_chip, test_hc_locate_chip_eeprom)
+{
+	int ret;
+	struct ec_params_locate_chip p;
+	struct ec_response_locate_chip r;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_LOCATE_CHIP, 0, r, p);
+
+	p.type = EC_CHIP_TYPE_CBI_EEPROM;
+	p.index = 0;
+
+	ret = host_command_process(&args);
+
+	zassert_equal(ret, EC_RES_SUCCESS, "Unexpected return value: %d", ret);
+	zassert_equal(r.bus_type, EC_BUS_TYPE_I2C, "Unexpected bus_type: %d",
+		      r.bus_type);
+	zassert_equal(r.i2c_info.port, I2C_PORT_EEPROM, "Unexpected port: %d",
+		      r.i2c_info.port);
+	zassert_equal(r.i2c_info.addr_flags, I2C_ADDR_EEPROM_FLAGS,
+		      "Unexpected addr_flags: %d", r.i2c_info.addr_flags);
+}
+
+/**
+ * @brief TestPurpose: test the EEPROM index overflow case.
+ */
+ZTEST_USER(locate_chip, test_hc_locate_chip_eeprom_overflow)
+{
+	int ret;
+	struct ec_params_locate_chip p;
+	struct ec_response_locate_chip r;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_LOCATE_CHIP, 0, r, p);
+
+	p.type = EC_CHIP_TYPE_CBI_EEPROM;
+	p.index = 1;
+
+	ret = host_command_process(&args);
+
+	zassert_equal(ret, EC_RES_OVERFLOW, "Unexpected return value: %d", ret);
+}
+
+/**
+ * @brief TestPurpose: test the invalid parameter case.
+ */
+ZTEST_USER(locate_chip, test_hc_locate_chip_invalid)
+{
+	int ret;
+	struct ec_params_locate_chip p;
+	struct ec_response_locate_chip r;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_LOCATE_CHIP, 0, r, p);
+
+	p.type = EC_CHIP_TYPE_COUNT;
+	ret = host_command_process(&args);
+
+	zassert_equal(ret, EC_RES_INVALID_PARAM, "Unexpected return value: %d",
+		      ret);
+}
+
+ZTEST_SUITE(locate_chip, drivers_predicate_post_main, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/drivers/src/motion_sense/motion_sense.c b/zephyr/test/drivers/default/src/motion_sense/motion_sense.c
index 5b6839bbae..d39c3ce335 100644
--- a/zephyr/test/drivers/src/motion_sense/motion_sense.c
+++ b/zephyr/test/drivers/default/src/motion_sense/motion_sense.c
@@ -1,9 +1,9 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <ztest.h>
+#include <zephyr/ztest.h>
 
 #include "motion_sense.h"
 #include "test/drivers/test_state.h"
diff --git a/zephyr/test/drivers/src/panic.c b/zephyr/test/drivers/default/src/panic.c
index 2615c22156..4b97ed63d9 100644
--- a/zephyr/test/drivers/src/panic.c
+++ b/zephyr/test/drivers/default/src/panic.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,8 @@
 #include <zephyr/device.h>
 
 #include <zephyr/logging/log.h>
-#include <zephyr/zephyr.h>
-#include <ztest.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
 
 #include "common.h"
 #include "ec_tasks.h"
@@ -20,10 +20,42 @@
 #include "test/drivers/stubs.h"
 #include "test/drivers/test_state.h"
 
+struct panic_test_fixture {
+	struct panic_data saved_pdata;
+};
+
+static void *panic_test_setup(void)
+{
+	static struct panic_test_fixture panic_fixture = { 0 };
+
+	return &panic_fixture;
+}
+
+static void panic_before(void *state)
+{
+	struct panic_test_fixture *fixture = state;
+	struct panic_data *pdata = get_panic_data_write();
+
+	ARG_UNUSED(state);
+
+	fixture->saved_pdata = *pdata;
+}
+
+static void panic_after(void *state)
+{
+	struct panic_test_fixture *fixture = state;
+	struct panic_data *pdata = get_panic_data_write();
+
+	ARG_UNUSED(state);
+
+	*pdata = fixture->saved_pdata;
+}
+
 /**
  * @brief Test Suite: Verifies panic functionality.
  */
-ZTEST_SUITE(panic, drivers_predicate_post_main, NULL, NULL, NULL, NULL);
+ZTEST_SUITE(panic, drivers_predicate_post_main, panic_test_setup, panic_before,
+	    panic_after, NULL);
 
 /**
  * @brief TestPurpose: Verify panic set/get reason.
@@ -58,3 +90,19 @@ ZTEST(panic, test_panic_reason)
 
 	panic_data_print(pdata);
 }
+
+ZTEST(panic, test_panic_data_start_bad_magic)
+{
+	struct panic_data *pdata = get_panic_data_write();
+
+	pdata->magic = PANIC_DATA_MAGIC + 1;
+	zassert_equal(0, get_panic_data_start(), NULL);
+}
+
+ZTEST(panic, test_get_panic_data_start)
+{
+	struct panic_data *pdata = get_panic_data_write();
+
+	pdata->magic = PANIC_DATA_MAGIC;
+	zassert_equal((uintptr_t)pdata, get_panic_data_start(), NULL);
+}
diff --git a/zephyr/test/drivers/default/src/panic_output.c b/zephyr/test/drivers/default/src/panic_output.c
new file mode 100644
index 0000000000..210c862901
--- /dev/null
+++ b/zephyr/test/drivers/default/src/panic_output.c
@@ -0,0 +1,74 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/ztest.h>
+
+#include "panic.h"
+#include "test/drivers/test_mocks.h"
+#include "test/drivers/test_state.h"
+
+ZTEST_SUITE(panic_output, drivers_predicate_post_main, NULL, NULL, NULL, NULL);
+
+ZTEST(panic_output, test_panic_printf)
+{
+	panic_printf("test output string from %s\n", __func__);
+}
+
+ZTEST(panic_output, test_panic_puts)
+{
+	panic_puts("test output string\n");
+}
+
+ZTEST(panic_output, test_panic_sw_reason_is_valid)
+{
+	zassert_false(panic_sw_reason_is_valid(PANIC_SW_BASE - 1), NULL);
+	/* PANIC_SW_DIV_ZERO */
+	zassert_true(panic_sw_reason_is_valid(PANIC_SW_BASE), NULL);
+	/* PANIC_SW_STACK_OVERFLOW */
+	zassert_true(panic_sw_reason_is_valid(PANIC_SW_BASE + 1), NULL);
+	/* PANIC_SW_PD_CRASH */
+	zassert_true(panic_sw_reason_is_valid(PANIC_SW_BASE + 2), NULL);
+	/* PANIC_SW_ASSERT */
+	zassert_true(panic_sw_reason_is_valid(PANIC_SW_BASE + 3), NULL);
+	/* PANIC_SW_WATCHDOG */
+	zassert_true(panic_sw_reason_is_valid(PANIC_SW_BASE + 4), NULL);
+	/* PANIC_SW_RNG */
+	zassert_true(panic_sw_reason_is_valid(PANIC_SW_BASE + 5), NULL);
+	/* PANIC_SW_PMIC_FAULT */
+	zassert_true(panic_sw_reason_is_valid(PANIC_SW_BASE + 6), NULL);
+	zassert_false(panic_sw_reason_is_valid(PANIC_SW_BASE + 7), NULL);
+}
+
+ZTEST(panic_output, test_panic)
+{
+	panic(__func__);
+	zassert_equal(1, system_reset_fake.call_count,
+		      "Expected system_reset() to be called once, but was "
+		      "called %d times",
+		      system_reset_fake.call_count);
+	zassert_equal(0, system_reset_fake.arg0_val,
+		      "Expected system_reset() to be called with flags=0, but "
+		      "got flags=%d",
+		      system_reset_fake.arg0_val);
+}
+
+ZTEST(panic_output, test_panic_assert_fail)
+{
+	int line_num = __LINE__;
+
+	panic_assert_fail("Test panic message", __func__, __FILE__, line_num);
+	zassert_equal(1, software_panic_fake.call_count,
+		      "Expected sofware_panic() to be called once, but was "
+		      "called %d times",
+		      software_panic_fake.call_count);
+	zassert_equal(PANIC_SW_ASSERT, software_panic_fake.arg0_val,
+		      "Expected software_panic() to be called with "
+		      "reason=%d (PANIC_SW_ASSERT) but got %d",
+		      PANIC_SW_ASSERT, software_panic_fake.arg0_val);
+	zassert_equal(line_num, software_panic_fake.arg1_val,
+		      "Expected software_panic() to be called with "
+		      "line=%d but got %d",
+		      line_num, software_panic_fake.arg1_val);
+}
diff --git a/zephyr/test/drivers/default/src/port80.c b/zephyr/test/drivers/default/src/port80.c
new file mode 100644
index 0000000000..8563c2e478
--- /dev/null
+++ b/zephyr/test/drivers/default/src/port80.c
@@ -0,0 +1,191 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @file
+ * @brief Unit Tests for ESPI port 80 writes
+ */
+
+#include <zephyr/logging/log.h>
+#include <zephyr/shell/shell.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+#include "console.h"
+#include "ec_commands.h"
+#include "host_command.h"
+#include "port80.h"
+
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+/*
+ * Flush any existing writes.
+ */
+static void port80_flush(void)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "port80 flush"), NULL);
+}
+
+/**
+ * @brief TestPurpose: Verify port 80 writes
+ *
+ * @details
+ * Validate that the port 80 writes are processed correctly.
+ *
+ * Expected Results
+ *  - The port 80 writes are received
+ */
+ZTEST(port80, test_port80_write)
+{
+	struct ec_response_port80_read response;
+	struct ec_params_port80_read params;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_PORT80_READ, 1, response, params);
+
+	port80_flush();
+	port_80_write(0x12);
+	port_80_write(0x34);
+	/* Check the buffer using the host cmd */
+
+	/* Get the buffer info */
+	params.subcmd = EC_PORT80_GET_INFO;
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_ok(args.result, NULL);
+	zassert_equal(args.response_size, sizeof(response.get_info), NULL);
+	zassert_equal(response.get_info.writes, 2, NULL);
+	/* Read the buffer */
+	params.subcmd = EC_PORT80_READ_BUFFER;
+	params.read_buffer.offset = 0;
+	params.read_buffer.num_entries = 2;
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_ok(args.result, NULL);
+	zassert_equal(args.response_size, sizeof(uint16_t) * 2, NULL);
+	zassert_equal(response.data.codes[0], 0x12, NULL);
+	zassert_equal(response.data.codes[1], 0x34, NULL);
+}
+
+/**
+ * @brief TestPurpose: Verify port 80 read parameters
+ *
+ * @details
+ * Validate that the port 80 read parameters are checked
+ *
+ * Expected Results
+ *  - The port 80 parameters are verified
+ */
+ZTEST(port80, test_port80_offset)
+{
+	struct ec_response_port80_read response;
+	struct ec_params_port80_read params;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_PORT80_READ, 1, response, params);
+
+	port80_flush();
+
+	params.subcmd = EC_PORT80_READ_BUFFER;
+	params.read_buffer.offset = 0;
+	params.read_buffer.num_entries = 0;
+	zassert_equal(host_command_process(&args), EC_RES_INVALID_PARAM, NULL);
+	params.read_buffer.offset = 0xFFFF;
+	params.read_buffer.num_entries = 2;
+	zassert_equal(host_command_process(&args), EC_RES_INVALID_PARAM, NULL);
+	params.read_buffer.offset = 0;
+	params.read_buffer.num_entries = 0xFFFF;
+	zassert_equal(host_command_process(&args), EC_RES_INVALID_PARAM, NULL);
+}
+
+/**
+ * @brief TestPurpose: Verify port 80 reset event
+ *
+ * @details
+ * Validate that the port 80 handling works for the reset event
+ *
+ * Expected Results
+ *  - The port 80 handling detects the reset event.
+ */
+ZTEST(port80, test_port80_special)
+{
+	struct ec_params_port80_read params;
+	struct ec_response_port80_last_boot response;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_PORT80_READ, 0, response, params);
+
+	port80_flush();
+	port_80_write(0xDEAD);
+	port_80_write(0xAA); /* must be < 0x100 */
+	port_80_write(PORT_80_EVENT_RESET);
+	/* Check the buffer using the host cmd version 0*/
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_ok(args.result, NULL);
+	zassert_equal(args.response_size, sizeof(response), NULL);
+	zassert_equal(response.code, 0xAA, NULL);
+}
+
+/**
+ * @brief TestPurpose: Verify port 80 subcommand
+ *
+ * @details
+ * Validate that the port 80 host subcommand is checked.
+ *
+ * Expected Results
+ *  - The port 80 handling detects an invalid subcommand.
+ */
+ZTEST(port80, test_port80_subcmd)
+{
+	struct ec_params_port80_read params;
+	struct ec_response_port80_last_boot response;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_PORT80_READ, 1, response, params);
+
+	params.subcmd = 0xFFFF;
+	zassert_ok(!host_command_process(&args), NULL);
+}
+
+/**
+ * @brief TestPurpose: Verify port 80 write wrap
+ *
+ * @details
+ * Validate that the port 80 host writes wrap around.
+ *
+ * Expected Results
+ *  - The port 80 writes overwrites the history array.
+ */
+ZTEST(port80, test_port80_wrap)
+{
+	struct ec_params_port80_read params;
+	struct ec_response_port80_read response;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_PORT80_READ, 1, response, params);
+	uint32_t size, count;
+
+	port80_flush();
+	/* Get the history array size */
+	params.subcmd = EC_PORT80_GET_INFO;
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_ok(args.result, NULL);
+	zassert_equal(args.response_size, sizeof(response.get_info), NULL);
+	size = response.get_info.history_size;
+	count = size + size / 2; /* Ensure write will wrap the history */
+	for (uint32_t i = 0; i < count; i++) {
+		port_80_write(i);
+	}
+	/*
+	 * Retrieve the first entry in the history array.
+	 * It should equal the size of the array.
+	 */
+	params.subcmd = EC_PORT80_READ_BUFFER;
+	params.read_buffer.offset = 0;
+	params.read_buffer.num_entries = 1;
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_ok(args.result, NULL);
+	zassert_equal(args.response_size, sizeof(uint16_t), NULL);
+	zassert_equal(response.data.codes[0], size, NULL);
+}
+
+/**
+ * @brief Test Suite: Verifies port 80 writes.
+ */
+ZTEST_SUITE(port80, drivers_predicate_post_main, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/drivers/src/power_common.c b/zephyr/test/drivers/default/src/power_common.c
index 03832b6c0c..3579cb7b3c 100644
--- a/zephyr/test/drivers/src/power_common.c
+++ b/zephyr/test/drivers/default/src/power_common.c
@@ -1,12 +1,14 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <ztest.h>
+#include <string.h>
+#include <zephyr/ztest.h>
 #include <zephyr/drivers/gpio.h>
 #include <zephyr/drivers/gpio/gpio_emul.h>
 #include <zephyr/shell/shell.h>
+#include <zephyr/shell/shell_dummy.h>
 #include <zephyr/shell/shell_uart.h>
 
 #include "chipset.h"
@@ -27,7 +29,7 @@
 #include "battery_smart.h"
 #include "test/drivers/utils.h"
 
-#define BATTERY_ORD DT_DEP_ORD(DT_NODELABEL(battery))
+#define BATTERY_NODE DT_NODELABEL(battery)
 
 /* Description of all power states with chipset state masks */
 static struct {
@@ -296,22 +298,23 @@ ZTEST(power_common, test_power_hc_smart_discharge)
 	struct ec_params_smart_discharge params;
 	struct host_cmd_handler_args args =
 		BUILD_HOST_COMMAND(EC_CMD_SMART_DISCHARGE, 0, response, params);
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BATTERY_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_smart_battery_get_i2c_common_data(emul);
 	int hours_to_zero;
 	int hibern_drate;
 	int cutoff_drate;
 	int stayup_cap;
 	int cutoff_cap;
 
-	emul = sbat_emul_get_ptr(BATTERY_ORD);
-
 	/* Set up host command parameters */
 	params.flags = EC_SMART_DISCHARGE_FLAGS_SET;
 
 	/* Test fail when battery capacity is not available */
-	i2c_common_emul_set_read_fail_reg(emul, SB_FULL_CHARGE_CAPACITY);
+	i2c_common_emul_set_read_fail_reg(common_data, SB_FULL_CHARGE_CAPACITY);
 	zassert_equal(EC_RES_UNAVAILABLE, host_command_process(&args), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Setup discharge rates */
 	params.drate.hibern = 10;
@@ -391,12 +394,13 @@ ZTEST(power_common, test_power_board_system_is_idle)
 	struct host_cmd_handler_args args =
 		BUILD_HOST_COMMAND(EC_CMD_SMART_DISCHARGE, 0, response, params);
 	struct sbat_emul_bat_data *bat;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BATTERY_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_smart_battery_get_i2c_common_data(emul);
 	uint64_t last_shutdown_time = 0;
 	uint64_t target;
 	uint64_t now;
 
-	emul = sbat_emul_get_ptr(BATTERY_ORD);
 	bat = sbat_emul_get_bat_data(emul);
 
 	/* Set up host command parameters */
@@ -421,11 +425,12 @@ ZTEST(power_common, test_power_board_system_is_idle)
 	 * Test hibernation is requested when battery remaining capacity
 	 * is not available
 	 */
-	i2c_common_emul_set_read_fail_reg(emul, SB_REMAINING_CAPACITY);
+	i2c_common_emul_set_read_fail_reg(common_data, SB_REMAINING_CAPACITY);
 	zassert_equal(CRITICAL_SHUTDOWN_HIBERNATE,
 		      board_system_is_idle(last_shutdown_time, &target, now),
 		      NULL);
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Setup remaining capacity to trigger cutoff */
 	bat->cap = response.dzone.cutoff - 5;
@@ -447,6 +452,42 @@ ZTEST(power_common, test_power_board_system_is_idle)
 }
 
 /**
+ * Test power console command
+ */
+ZTEST(power_common, power_console_cmd)
+{
+	const char *buffer;
+	size_t buffer_size;
+
+	test_set_chipset_to_g3();
+	shell_backend_dummy_clear_output(get_ec_shell());
+	zassert_equal(EC_SUCCESS, shell_execute_cmd(get_ec_shell(), "power"),
+		      NULL);
+	buffer = shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+	zassert_true(strcmp(buffer, "\r\noff\r\n") == 0 ||
+			     strcmp(buffer, "\r\nOFF\r\n") == 0,
+		     "Invalid console output %s", buffer);
+
+	test_set_chipset_to_s0();
+	shell_backend_dummy_clear_output(get_ec_shell());
+	zassert_equal(EC_SUCCESS, shell_execute_cmd(get_ec_shell(), "power"),
+		      NULL);
+	buffer = shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+	zassert_true(strcmp(buffer, "\r\non\r\n") == 0 ||
+			     strcmp(buffer, "\r\nON\r\n") == 0,
+		     "Invalid console output %s", buffer);
+
+	zassert_equal(EC_ERROR_PARAM1,
+		      shell_execute_cmd(get_ec_shell(), "power x"), NULL);
+
+	zassert_equal(EC_SUCCESS, shell_execute_cmd(get_ec_shell(), "power on"),
+		      NULL);
+
+	zassert_equal(EC_SUCCESS,
+		      shell_execute_cmd(get_ec_shell(), "power off"), NULL);
+}
+
+/**
  * Common setup for hibernation delay tests. Smart discharge zone is setup,
  * battery is set in safe zone (which trigger hibernation), power state is
  * set to G3 and AC is disabled. system_hibernate mock is reset.
@@ -458,10 +499,9 @@ static void setup_hibernation_delay(void *state)
 	struct host_cmd_handler_args args =
 		BUILD_HOST_COMMAND(EC_CMD_SMART_DISCHARGE, 0, response, params);
 	struct sbat_emul_bat_data *bat;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BATTERY_NODE);
 	ARG_UNUSED(state);
 
-	emul = sbat_emul_get_ptr(BATTERY_ORD);
 	bat = sbat_emul_get_bat_data(emul);
 
 	/* Setup smart discharge zone and set capacity to safe zone */
@@ -500,7 +540,7 @@ ZTEST(power_common_hibernation, test_power_hc_hibernation_delay)
 	zassert_ok(shell_execute_cmd(get_ec_shell(), "lidclose"), NULL);
 
 	zassert_equal(power_get_state(), POWER_G3,
-		"Power state is %d, expected G3", power_get_state());
+		      "Power state is %d, expected G3", power_get_state());
 	/* This is a no-op, but it will reset the last_shutdown_time. */
 	power_set_state(POWER_G3);
 
@@ -612,28 +652,23 @@ ZTEST(power_common_hibernation, test_power_cmd_hibernation_delay)
 	int sleep_time;
 
 	zassert_equal(power_get_state(), POWER_G3,
-		"Power state is %d, expected G3", power_get_state());
+		      "Power state is %d, expected G3", power_get_state());
 	/* This is a no-op, but it will reset the last_shutdown_time. */
 	power_set_state(POWER_G3);
 
 	/* Test success on call without argument */
-	zassert_equal(EC_SUCCESS,
-		      shell_execute_cmd(get_ec_shell(),
-					"hibdelay"),
+	zassert_equal(EC_SUCCESS, shell_execute_cmd(get_ec_shell(), "hibdelay"),
 		      NULL);
 
 	/* Test error on hibernation delay argument that is not a number */
 	zassert_equal(EC_ERROR_PARAM1,
-		      shell_execute_cmd(get_ec_shell(),
-					"hibdelay test1"),
+		      shell_execute_cmd(get_ec_shell(), "hibdelay test1"),
 		      NULL);
 
 	/* Set hibernate delay */
 	h_delay = 3;
 	zassert_equal(EC_SUCCESS,
-		      shell_execute_cmd(get_ec_shell(),
-					"hibdelay 3"),
-		      NULL);
+		      shell_execute_cmd(get_ec_shell(), "hibdelay 3"), NULL);
 
 	/* Kick chipset task to process new hibernation delay */
 	task_wake(TASK_ID_CHIPSET);
diff --git a/zephyr/test/drivers/src/ppc_sn5s330.c b/zephyr/test/drivers/default/src/ppc_sn5s330.c
index bd38f874f7..c9ba62cf20 100644
--- a/zephyr/test/drivers/src/ppc_sn5s330.c
+++ b/zephyr/test/drivers/default/src/ppc_sn5s330.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,8 +7,8 @@
 #include <zephyr/device.h>
 #include <zephyr/devicetree.h>
 #include <zephyr/drivers/emul.h>
-#include <ztest.h>
-#include <fff.h>
+#include <zephyr/ztest.h>
+#include <zephyr/fff.h>
 
 #include "driver/ppc/sn5s330.h"
 #include "driver/ppc/sn5s330_public.h"
@@ -20,7 +20,8 @@
 
 /** This must match the index of the sn5s330 in ppc_chips[] */
 #define SN5S330_PORT 0
-#define EMUL emul_get_binding(DT_LABEL(DT_NODELABEL(sn5s330_emul)))
+#define EMUL EMUL_DT_GET(DT_NODELABEL(sn5s330_emul))
+#define COMMON_DATA emul_sn5s330_get_i2c_common_data(EMUL)
 #define FUNC_SET1_ILIMPP1_MSK 0x1F
 #define SN5S330_INTERRUPT_DELAYMS 15
 
@@ -42,7 +43,7 @@ struct intercept_read_data {
 	uint8_t replacement_val;
 };
 
-static int intercept_read_func(struct i2c_emul *emul, int reg, uint8_t *val,
+static int intercept_read_func(const struct emul *emul, int reg, uint8_t *val,
 			       int bytes, void *data)
 {
 	struct intercept_read_data *test_data = data;
@@ -53,7 +54,7 @@ static int intercept_read_func(struct i2c_emul *emul, int reg, uint8_t *val,
 	return EC_SUCCESS;
 }
 
-static int intercept_write_func(struct i2c_emul *emul, int reg, uint8_t val,
+static int intercept_write_func(const struct emul *emul, int reg, uint8_t val,
 				int bytes, void *data)
 {
 	struct intercept_write_data *test_data = data;
@@ -64,7 +65,7 @@ static int intercept_write_func(struct i2c_emul *emul, int reg, uint8_t val,
 	return 1;
 }
 
-static int fail_until_write_func(struct i2c_emul *emul, int reg, uint8_t val,
+static int fail_until_write_func(const struct emul *emul, int reg, uint8_t val,
 				 int bytes, void *data)
 {
 	uint32_t *count = data;
@@ -79,23 +80,21 @@ static int fail_until_write_func(struct i2c_emul *emul, int reg, uint8_t val,
 ZTEST(ppc_sn5s330, test_fail_once_func_set1)
 {
 	const struct emul *emul = EMUL;
-	struct i2c_emul *i2c_emul = sn5s330_emul_to_i2c_emul(emul);
 	uint32_t count = 1;
 	uint8_t func_set1_value;
 
-	i2c_common_emul_set_write_func(i2c_emul, fail_until_write_func, &count);
+	i2c_common_emul_set_write_func(COMMON_DATA, fail_until_write_func,
+				       &count);
 
 	zassert_ok(sn5s330_drv.init(SN5S330_PORT), NULL);
 	zassert_equal(count, 0, NULL);
 	sn5s330_emul_peek_reg(emul, SN5S330_FUNC_SET1, &func_set1_value);
 	zassert_true((func_set1_value & SN5S330_ILIM_1_62) != 0, NULL);
-	i2c_common_emul_set_write_func(i2c_emul, NULL, NULL);
+	i2c_common_emul_set_write_func(COMMON_DATA, NULL, NULL);
 }
 
 ZTEST(ppc_sn5s330, test_dead_battery_boot_force_pp2_fets_set)
 {
-	const struct emul *emul = EMUL;
-	struct i2c_emul *i2c_emul = sn5s330_emul_to_i2c_emul(emul);
 	struct intercept_write_data test_write_data = {
 		.reg_to_intercept = SN5S330_FUNC_SET3,
 		.val_intercepted = 0,
@@ -106,9 +105,9 @@ ZTEST(ppc_sn5s330, test_dead_battery_boot_force_pp2_fets_set)
 		.replacement_val = SN5S330_DB_BOOT,
 	};
 
-	i2c_common_emul_set_write_func(i2c_emul, intercept_write_func,
+	i2c_common_emul_set_write_func(COMMON_DATA, intercept_write_func,
 				       &test_write_data);
-	i2c_common_emul_set_read_func(i2c_emul, intercept_read_func,
+	i2c_common_emul_set_read_func(COMMON_DATA, intercept_read_func,
 				      &test_read_data);
 
 	zassert_ok(sn5s330_drv.init(SN5S330_PORT), NULL);
@@ -194,9 +193,8 @@ ZTEST(ppc_sn5s330, test_vbus_source_sink_enable)
 }
 
 /* This test depends on EC GIPO initialization happening before I2C */
-BUILD_ASSERT(
-	CONFIG_PLATFORM_EC_GPIO_INIT_PRIORITY < CONFIG_I2C_INIT_PRIORITY,
-	"GPIO initialization must happen before I2C");
+BUILD_ASSERT(CONFIG_PLATFORM_EC_GPIO_INIT_PRIORITY < CONFIG_I2C_INIT_PRIORITY,
+	     "GPIO initialization must happen before I2C");
 ZTEST(ppc_sn5s330, test_vbus_discharge)
 {
 	const struct emul *emul = EMUL;
@@ -385,18 +383,17 @@ ZTEST(ppc_sn5s330, test_sn5s330_set_vconn_fet)
 }
 
 /* Make an I2C emulator mock read func wrapped in FFF */
-FAKE_VALUE_FUNC(int, dump_read_fn, struct i2c_emul *, int, uint8_t *, int,
+FAKE_VALUE_FUNC(int, dump_read_fn, const struct emul *, int, uint8_t *, int,
 		void *);
 
 ZTEST(ppc_sn5s330, test_dump)
 {
 	int ret;
-	struct i2c_emul *i2c_emul = sn5s330_emul_to_i2c_emul(EMUL);
 
 	/* Set up our fake read function to pass through to the real emul */
 	RESET_FAKE(dump_read_fn);
 	dump_read_fn_fake.return_val = 1;
-	i2c_common_emul_set_read_func(i2c_emul, dump_read_fn, NULL);
+	i2c_common_emul_set_read_func(COMMON_DATA, dump_read_fn, NULL);
 
 	ret = sn5s330_drv.reg_dump(SN5S330_PORT);
 
@@ -438,74 +435,85 @@ enum i2c_operation {
 	I2C_READ,
 };
 
-#define INIT_I2C_FAIL_HELPER(EMUL, RW, REG)                                \
-	do {                                                               \
-		if ((RW) == I2C_READ) {                                    \
-			i2c_common_emul_set_read_fail_reg((EMUL), (REG));  \
-			i2c_common_emul_set_write_fail_reg(                \
-				(EMUL), I2C_COMMON_EMUL_NO_FAIL_REG);      \
-		} else if ((RW) == I2C_WRITE) {                            \
-			i2c_common_emul_set_read_fail_reg(                 \
-				(EMUL), I2C_COMMON_EMUL_NO_FAIL_REG);      \
-			i2c_common_emul_set_write_fail_reg((EMUL), (REG)); \
-		} else {                                                   \
-			zassert_true(false, "Invalid I2C operation");      \
-		}                                                          \
-		zassert_equal(                                             \
-			EC_ERROR_INVAL, sn5s330_drv.init(SN5S330_PORT),    \
-			"Did not get EC_ERROR_INVAL when reg %s (0x%02x)"  \
-			"could not be %s",                                 \
-			#REG, (REG),                                       \
-			((RW) == I2C_READ) ? "read" : "written");          \
+#define INIT_I2C_FAIL_HELPER(COMMON_DATA, RW, REG)                             \
+	do {                                                                   \
+		if ((RW) == I2C_READ) {                                        \
+			i2c_common_emul_set_read_fail_reg((COMMON_DATA),       \
+							  (REG));              \
+			i2c_common_emul_set_write_fail_reg(                    \
+				(COMMON_DATA), I2C_COMMON_EMUL_NO_FAIL_REG);   \
+		} else if ((RW) == I2C_WRITE) {                                \
+			i2c_common_emul_set_read_fail_reg(                     \
+				(COMMON_DATA), I2C_COMMON_EMUL_NO_FAIL_REG);   \
+			i2c_common_emul_set_write_fail_reg((COMMON_DATA),      \
+							   (REG));             \
+		} else {                                                       \
+			zassert_true(false, "Invalid I2C operation");          \
+		}                                                              \
+		zassert_equal(                                                 \
+			EC_ERROR_INVAL, sn5s330_drv.init(SN5S330_PORT),        \
+			"Did not get EC_ERROR_INVAL when reg %s (0x%02x)"      \
+			"could not be %s",                                     \
+			#REG, (REG), ((RW) == I2C_READ) ? "read" : "written"); \
 	} while (0)
 
 ZTEST(ppc_sn5s330, test_init_reg_fails)
 {
-	struct i2c_emul *i2c_emul = sn5s330_emul_to_i2c_emul(EMUL);
-
 	/* Fail on each of the I2C operations the init function does to ensure
 	 * we get the correct return value. This includes operations made by
 	 * clr_flags() and set_flags().
 	 */
 
-	INIT_I2C_FAIL_HELPER(i2c_emul, I2C_WRITE, SN5S330_FUNC_SET5);
-	INIT_I2C_FAIL_HELPER(i2c_emul, I2C_READ, SN5S330_FUNC_SET6);
-	INIT_I2C_FAIL_HELPER(i2c_emul, I2C_WRITE, SN5S330_FUNC_SET6);
-	INIT_I2C_FAIL_HELPER(i2c_emul, I2C_WRITE, SN5S330_FUNC_SET2);
-	INIT_I2C_FAIL_HELPER(i2c_emul, I2C_WRITE, SN5S330_FUNC_SET9);
-	INIT_I2C_FAIL_HELPER(i2c_emul, I2C_WRITE, SN5S330_FUNC_SET11);
-	INIT_I2C_FAIL_HELPER(i2c_emul, I2C_READ, SN5S330_FUNC_SET8);
-	INIT_I2C_FAIL_HELPER(i2c_emul, I2C_WRITE, SN5S330_FUNC_SET8);
-
-	INIT_I2C_FAIL_HELPER(i2c_emul, I2C_READ, SN5S330_FUNC_SET4);
-	INIT_I2C_FAIL_HELPER(i2c_emul, I2C_WRITE, SN5S330_FUNC_SET4);
-
-	INIT_I2C_FAIL_HELPER(i2c_emul, I2C_READ, SN5S330_FUNC_SET3);
-	INIT_I2C_FAIL_HELPER(i2c_emul, I2C_WRITE, SN5S330_FUNC_SET3);
-
-	INIT_I2C_FAIL_HELPER(i2c_emul, I2C_READ, SN5S330_FUNC_SET10);
-	INIT_I2C_FAIL_HELPER(i2c_emul, I2C_WRITE, SN5S330_FUNC_SET10);
-
-	INIT_I2C_FAIL_HELPER(i2c_emul, I2C_WRITE, SN5S330_INT_STATUS_REG4);
-
-	INIT_I2C_FAIL_HELPER(i2c_emul, I2C_WRITE, SN5S330_INT_MASK_RISE_REG1);
-	INIT_I2C_FAIL_HELPER(i2c_emul, I2C_WRITE, SN5S330_INT_MASK_FALL_REG1);
-	INIT_I2C_FAIL_HELPER(i2c_emul, I2C_WRITE, SN5S330_INT_MASK_RISE_REG2);
-	INIT_I2C_FAIL_HELPER(i2c_emul, I2C_WRITE, SN5S330_INT_MASK_FALL_REG2);
-	INIT_I2C_FAIL_HELPER(i2c_emul, I2C_WRITE, SN5S330_INT_MASK_RISE_REG3);
-	INIT_I2C_FAIL_HELPER(i2c_emul, I2C_WRITE, SN5S330_INT_MASK_FALL_REG3);
-
-	INIT_I2C_FAIL_HELPER(i2c_emul, I2C_READ, SN5S330_INT_STATUS_REG4);
-
-	INIT_I2C_FAIL_HELPER(i2c_emul, I2C_WRITE, SN5S330_INT_TRIP_RISE_REG1);
-	INIT_I2C_FAIL_HELPER(i2c_emul, I2C_WRITE, SN5S330_INT_TRIP_RISE_REG2);
-	INIT_I2C_FAIL_HELPER(i2c_emul, I2C_WRITE, SN5S330_INT_TRIP_RISE_REG3);
-	INIT_I2C_FAIL_HELPER(i2c_emul, I2C_WRITE, SN5S330_INT_TRIP_FALL_REG1);
-	INIT_I2C_FAIL_HELPER(i2c_emul, I2C_WRITE, SN5S330_INT_TRIP_FALL_REG2);
-	INIT_I2C_FAIL_HELPER(i2c_emul, I2C_WRITE, SN5S330_INT_TRIP_FALL_REG3);
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE, SN5S330_FUNC_SET5);
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_READ, SN5S330_FUNC_SET6);
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE, SN5S330_FUNC_SET6);
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE, SN5S330_FUNC_SET2);
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE, SN5S330_FUNC_SET9);
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE, SN5S330_FUNC_SET11);
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_READ, SN5S330_FUNC_SET8);
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE, SN5S330_FUNC_SET8);
+
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_READ, SN5S330_FUNC_SET4);
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE, SN5S330_FUNC_SET4);
+
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_READ, SN5S330_FUNC_SET3);
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE, SN5S330_FUNC_SET3);
+
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_READ, SN5S330_FUNC_SET10);
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE, SN5S330_FUNC_SET10);
+
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE, SN5S330_INT_STATUS_REG4);
+
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE,
+			     SN5S330_INT_MASK_RISE_REG1);
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE,
+			     SN5S330_INT_MASK_FALL_REG1);
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE,
+			     SN5S330_INT_MASK_RISE_REG2);
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE,
+			     SN5S330_INT_MASK_FALL_REG2);
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE,
+			     SN5S330_INT_MASK_RISE_REG3);
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE,
+			     SN5S330_INT_MASK_FALL_REG3);
+
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_READ, SN5S330_INT_STATUS_REG4);
+
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE,
+			     SN5S330_INT_TRIP_RISE_REG1);
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE,
+			     SN5S330_INT_TRIP_RISE_REG2);
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE,
+			     SN5S330_INT_TRIP_RISE_REG3);
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE,
+			     SN5S330_INT_TRIP_FALL_REG1);
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE,
+			     SN5S330_INT_TRIP_FALL_REG2);
+	INIT_I2C_FAIL_HELPER(COMMON_DATA, I2C_WRITE,
+			     SN5S330_INT_TRIP_FALL_REG3);
 }
 
-static int pp_fet_test_mock_read_fn(struct i2c_emul *emul, int reg,
+static int pp_fet_test_mock_read_fn(const struct emul *emul, int reg,
 				    uint8_t *val, int bytes, void *data)
 {
 	int *counter = data;
@@ -537,11 +545,10 @@ ZTEST(ppc_sn5s330, test_pp_fet_enable_fail)
 	 * battery mode, which we take care of in the mock read function.
 	 */
 
-	struct i2c_emul *i2c_emul = sn5s330_emul_to_i2c_emul(EMUL);
 	int counter;
 	int ret;
 
-	i2c_common_emul_set_read_func(i2c_emul, pp_fet_test_mock_read_fn,
+	i2c_common_emul_set_read_func(COMMON_DATA, pp_fet_test_mock_read_fn,
 				      &counter);
 
 	/* Allow only the first access to the reg to succeed. This tests the
@@ -594,10 +601,9 @@ ZTEST(ppc_sn5s330, test_set_polarity)
 
 ZTEST(ppc_sn5s330, test_set_vbus_source_current_limit_fail)
 {
-	struct i2c_emul *i2c_emul = sn5s330_emul_to_i2c_emul(EMUL);
 	int ret;
 
-	i2c_common_emul_set_read_fail_reg(i2c_emul, SN5S330_FUNC_SET1);
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, SN5S330_FUNC_SET1);
 
 	ret = sn5s330_drv.set_vbus_source_current_limit(SN5S330_PORT,
 							TYPEC_RP_3A0);
@@ -607,10 +613,9 @@ ZTEST(ppc_sn5s330, test_set_vbus_source_current_limit_fail)
 
 ZTEST(ppc_sn5s330, test_sn5s330_discharge_vbus_fail)
 {
-	struct i2c_emul *i2c_emul = sn5s330_emul_to_i2c_emul(EMUL);
 	int ret;
 
-	i2c_common_emul_set_read_fail_reg(i2c_emul, SN5S330_FUNC_SET3);
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, SN5S330_FUNC_SET3);
 
 	ret = sn5s330_drv.discharge_vbus(SN5S330_PORT, false);
 	zassert_equal(EC_ERROR_INVAL, ret, "Expected EC_ERROR_INVAL but got %d",
@@ -621,25 +626,24 @@ ZTEST(ppc_sn5s330, test_low_power_mode_fail)
 {
 	/* Test failed I2C operations in the enter low power mode function */
 
-	struct i2c_emul *i2c_emul = sn5s330_emul_to_i2c_emul(EMUL);
 	int ret;
 
-	i2c_common_emul_set_read_fail_reg(i2c_emul, SN5S330_FUNC_SET3);
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, SN5S330_FUNC_SET3);
 	ret = sn5s330_drv.enter_low_power_mode(SN5S330_PORT);
 	zassert_equal(EC_ERROR_INVAL, ret, "Expected EC_ERROR_INVAL but got %d",
 		      ret);
 
-	i2c_common_emul_set_read_fail_reg(i2c_emul, SN5S330_FUNC_SET4);
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, SN5S330_FUNC_SET4);
 	ret = sn5s330_drv.enter_low_power_mode(SN5S330_PORT);
 	zassert_equal(EC_ERROR_INVAL, ret, "Expected EC_ERROR_INVAL but got %d",
 		      ret);
 
-	i2c_common_emul_set_read_fail_reg(i2c_emul, SN5S330_FUNC_SET2);
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, SN5S330_FUNC_SET2);
 	ret = sn5s330_drv.enter_low_power_mode(SN5S330_PORT);
 	zassert_equal(EC_ERROR_INVAL, ret, "Expected EC_ERROR_INVAL but got %d",
 		      ret);
 
-	i2c_common_emul_set_read_fail_reg(i2c_emul, SN5S330_FUNC_SET9);
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, SN5S330_FUNC_SET9);
 	ret = sn5s330_drv.enter_low_power_mode(SN5S330_PORT);
 	zassert_equal(EC_ERROR_INVAL, ret, "Expected EC_ERROR_INVAL but got %d",
 		      ret);
@@ -649,10 +653,9 @@ ZTEST(ppc_sn5s330, test_sn5s330_set_vconn_fail)
 {
 	/* Test failed I2C operations in the set Vconn function */
 
-	struct i2c_emul *i2c_emul = sn5s330_emul_to_i2c_emul(EMUL);
 	int ret;
 
-	i2c_common_emul_set_read_fail_reg(i2c_emul, SN5S330_FUNC_SET4);
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA, SN5S330_FUNC_SET4);
 	ret = sn5s330_drv.set_vconn(SN5S330_PORT, 0);
 	zassert_equal(EC_ERROR_INVAL, ret, "Expected EC_ERROR_INVAL but got %d",
 		      ret);
@@ -660,14 +663,12 @@ ZTEST(ppc_sn5s330, test_sn5s330_set_vconn_fail)
 
 static inline void reset_sn5s330_state(void)
 {
-	struct i2c_emul *i2c_emul = sn5s330_emul_to_i2c_emul(EMUL);
-
-	i2c_common_emul_set_write_func(i2c_emul, NULL, NULL);
-	i2c_common_emul_set_read_func(i2c_emul, NULL, NULL);
-	i2c_common_emul_set_write_fail_reg(i2c_emul,
-		I2C_COMMON_EMUL_NO_FAIL_REG);
-	i2c_common_emul_set_read_fail_reg(i2c_emul,
-		I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_func(COMMON_DATA, NULL, NULL);
+	i2c_common_emul_set_read_func(COMMON_DATA, NULL, NULL);
+	i2c_common_emul_set_write_fail_reg(COMMON_DATA,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(COMMON_DATA,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 	sn5s330_emul_reset(EMUL);
 	RESET_FAKE(sn5s330_emul_interrupt_set_stub);
 }
diff --git a/zephyr/test/drivers/src/ppc_syv682x.c b/zephyr/test/drivers/default/src/ppc_syv682x.c
index aa08c26745..edfbd45171 100644
--- a/zephyr/test/drivers/src/ppc_syv682x.c
+++ b/zephyr/test/drivers/default/src/ppc_syv682x.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,10 +7,10 @@
 #include <zephyr/devicetree/gpio.h>
 #include <zephyr/drivers/gpio/gpio_emul.h>
 #include <zephyr/drivers/gpio.h>
-#include <fff.h>
-#include <zephyr/zephyr.h>
-#include <ztest.h>
-#include <ztest_assert.h>
+#include <zephyr/fff.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+#include <zephyr/ztest_assert.h>
 
 #include "emul/emul_common_i2c.h"
 #include "emul/emul_syv682x.h"
@@ -21,11 +21,12 @@
 #include "test/drivers/utils.h"
 #include "usbc_ppc.h"
 
-#define SYV682X_ORD DT_DEP_ORD(DT_NODELABEL(syv682x_emul))
+#define SYV682X_NODE DT_NODELABEL(syv682x_emul)
 #define GPIO_USB_C1_FRS_EN_PATH DT_PATH(named_gpios, usb_c1_frs_en)
 
 struct ppc_syv682x_fixture {
-	struct i2c_emul *ppc_emul;
+	const struct emul *ppc_emul;
+	struct i2c_common_emul_data *common_data;
 	const struct device *frs_en_gpio_port;
 	int frs_en_gpio_pin;
 };
@@ -42,7 +43,9 @@ static void *syv682x_test_setup(void)
 {
 	static struct ppc_syv682x_fixture fixture;
 
-	fixture.ppc_emul = syv682x_emul_get(SYV682X_ORD);
+	fixture.ppc_emul = EMUL_DT_GET(SYV682X_NODE);
+	fixture.common_data =
+		emul_syv682x_get_i2c_common_data(fixture.ppc_emul);
 	zassume_not_null(fixture.ppc_emul, NULL);
 	fixture.frs_en_gpio_port =
 		DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_USB_C1_FRS_EN_PATH, gpios));
@@ -55,7 +58,8 @@ static void *syv682x_test_setup(void)
 static void syv682x_test_after(void *data)
 {
 	struct ppc_syv682x_fixture *fixture = data;
-	struct i2c_emul *emul = fixture->ppc_emul;
+	const struct emul *emul = fixture->ppc_emul;
+	struct i2c_common_emul_data *common_data = fixture->common_data;
 
 	/* Disable the power path and clear interrupt conditions. */
 	zassume_ok(syv682x_emul_set_reg(emul, SYV682X_CONTROL_1_REG,
@@ -65,12 +69,14 @@ static void syv682x_test_after(void *data)
 				   SYV682X_CONTROL_4_NONE);
 
 	/* Clear the mock read/write functions */
-	i2c_common_emul_set_read_func(emul, NULL, NULL);
-	i2c_common_emul_set_write_func(emul, NULL, NULL);
+	i2c_common_emul_set_read_func(common_data, NULL, NULL);
+	i2c_common_emul_set_write_func(common_data, NULL, NULL);
 
 	/* Don't fail on any register access */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
 }
 
 ZTEST_SUITE(ppc_syv682x, drivers_predicate_post_main, syv682x_test_setup, NULL,
@@ -114,14 +120,15 @@ ZTEST_F(ppc_syv682x, test_syv682x_init_dead_battery)
 	 * With a dead battery, the device powers up sinking VBUS, and the
 	 * driver should keep that going.
 	 */
-	zassume_ok(syv682x_emul_set_reg(this->ppc_emul, SYV682X_CONTROL_1_REG,
+	zassume_ok(syv682x_emul_set_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_1_REG,
 					SYV682X_CONTROL_1_CH_SEL),
 		   NULL);
-	syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_VSAFE_5V,
+	syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_VSAFE_5V,
 				   SYV682X_CONTROL_4_NONE);
 	zassert_ok(ppc_init(syv682x_port), "PPC init failed");
-	zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_1_REG,
-					&reg),
+	zassume_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_1_REG, &reg),
 		   NULL);
 	zassert_true(reg & SYV682X_CONTROL_1_CH_SEL,
 		     "Dead battery init, but CH_SEL set to 5V power path");
@@ -137,14 +144,15 @@ ZTEST_F(ppc_syv682x, test_syv682x_init_vsafe0v)
 	uint8_t reg;
 
 	/* With VBUS at vSafe0V, init should set the default configuration. */
-	zassume_ok(syv682x_emul_set_reg(this->ppc_emul, SYV682X_CONTROL_1_REG,
+	zassume_ok(syv682x_emul_set_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_1_REG,
 					SYV682X_CONTROL_1_PWR_ENB),
 		   NULL);
-	syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_VSAFE_0V,
+	syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_VSAFE_0V,
 				   SYV682X_CONTROL_4_NONE);
 	zassert_ok(ppc_init(syv682x_port), "PPC init failed");
-	zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_1_REG,
-					&reg),
+	zassume_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_1_REG, &reg),
 		   NULL);
 	check_control_1_default_init(reg);
 }
@@ -154,14 +162,15 @@ ZTEST_F(ppc_syv682x, test_syv682x_init_sink_disabled)
 	uint8_t reg;
 
 	/* With sink disabled, init should do the same thing. */
-	zassume_ok(syv682x_emul_set_reg(this->ppc_emul, SYV682X_CONTROL_1_REG,
+	zassume_ok(syv682x_emul_set_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_1_REG,
 					SYV682X_CONTROL_1_CH_SEL),
 		   NULL);
-	syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_VSAFE_0V,
+	syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_VSAFE_0V,
 				   SYV682X_CONTROL_4_NONE);
 	zassert_ok(ppc_init(syv682x_port), "PPC init failed");
-	zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_1_REG,
-					&reg),
+	zassume_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_1_REG, &reg),
 		   NULL);
 	check_control_1_default_init(reg);
 }
@@ -172,8 +181,8 @@ ZTEST_F(ppc_syv682x, test_syv682x_init_common)
 	int ilim;
 
 	zassert_ok(ppc_init(syv682x_port), "PPC init failed");
-	zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_1_REG,
-					&reg),
+	zassume_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_1_REG, &reg),
 		   NULL);
 
 	/*
@@ -181,14 +190,14 @@ ZTEST_F(ppc_syv682x, test_syv682x_init_common)
 	 * current limit according to configuration, set over-current, over-
 	 * voltage, and discharge parameters appropriately, and enable CC lines.
 	 */
-	zassert_equal(gpio_emul_output_get(this->frs_en_gpio_port,
-					   this->frs_en_gpio_pin),
+	zassert_equal(gpio_emul_output_get(fixture->frs_en_gpio_port,
+					   fixture->frs_en_gpio_pin),
 		      0, "FRS enabled, but FRS GPIO not asserted");
 	ilim = (reg & SYV682X_5V_ILIM_MASK) >> SYV682X_5V_ILIM_BIT_SHIFT;
 	zassert_equal(ilim, CONFIG_PLATFORM_EC_USB_PD_PULLUP,
 		      "Default init, but 5V current limit set to %d", ilim);
-	zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_2_REG,
-					&reg),
+	zassume_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_2_REG, &reg),
 		   NULL);
 	zassert_equal(reg,
 		      (SYV682X_OC_DELAY_10MS << SYV682X_OC_DELAY_SHIFT) |
@@ -196,15 +205,15 @@ ZTEST_F(ppc_syv682x, test_syv682x_init_common)
 			       << SYV682X_DSG_RON_SHIFT) |
 			      (SYV682X_DSG_TIME_50MS << SYV682X_DSG_TIME_SHIFT),
 		      "Default init, but CONTROL_2 is 0x%x", reg);
-	zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_3_REG,
-					&reg),
+	zassume_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_3_REG, &reg),
 		   NULL);
 	zassert_equal(reg,
 		      (SYV682X_OVP_23_7 << SYV682X_OVP_BIT_SHIFT) |
 			      SYV682X_RVS_MASK,
 		      "Default init, but CONTROL_3 is 0x%x", reg);
-	zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_4_REG,
-					&reg),
+	zassume_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_4_REG, &reg),
 		   NULL);
 	zassert_equal(reg & ~SYV682X_CONTROL_4_INT_MASK,
 		      SYV682X_CONTROL_4_CC1_BPS | SYV682X_CONTROL_4_CC2_BPS,
@@ -217,8 +226,8 @@ ZTEST_F(ppc_syv682x, test_syv682x_vbus_source_enable)
 
 	zassert_ok(ppc_vbus_source_enable(syv682x_port, true),
 		   "VBUS enable failed");
-	zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_1_REG,
-					&reg),
+	zassume_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_1_REG, &reg),
 		   "Reading CONTROL_1 failed");
 	zassert_equal(reg & SYV682X_CONTROL_1_PWR_ENB, 0,
 		      "VBUS sourcing enabled but power path disabled");
@@ -239,7 +248,7 @@ ZTEST_F(ppc_syv682x, test_syv682x_interrupt_source_oc)
 	zassume_ok(ppc_vbus_source_enable(syv682x_port, true),
 		   "VBUS enable failed");
 	/* An OC event less than 100 ms should not cause VBUS to turn off. */
-	syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_OC_5V,
+	syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_OC_5V,
 				   SYV682X_CONTROL_4_NONE);
 	msleep(50);
 	zassert_true(ppc_is_sourcing_vbus(syv682x_port),
@@ -259,7 +268,7 @@ ZTEST_F(ppc_syv682x, test_syv682x_interrupt_tsd)
 	 */
 	zassume_ok(ppc_vbus_source_enable(syv682x_port, true),
 		   "Source enable failed");
-	syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_TSD,
+	syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_TSD,
 				   SYV682X_CONTROL_4_NONE);
 	msleep(1);
 	zassert_false(ppc_is_sourcing_vbus(syv682x_port),
@@ -271,7 +280,7 @@ ZTEST_F(ppc_syv682x, test_syv682x_interrupt_vbus_ovp)
 	/* An OVP event should cause the driver to disable the source path. */
 	zassume_ok(ppc_vbus_source_enable(syv682x_port, true),
 		   "Source enable failed");
-	syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_OVP,
+	syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_OVP,
 				   SYV682X_CONTROL_4_NONE);
 	msleep(1);
 	zassert_false(ppc_is_sourcing_vbus(syv682x_port),
@@ -289,29 +298,29 @@ ZTEST_F(ppc_syv682x, test_syv682x_interrupt_vbus_hv_oc)
 	 */
 	zassume_ok(ppc_vbus_sink_enable(syv682x_port, true),
 		   "Sink enable failed");
-	syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_OC_HV,
+	syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_OC_HV,
 				   SYV682X_CONTROL_4_NONE);
 	msleep(1);
-	zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_1_REG,
-					&reg),
+	zassume_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_1_REG, &reg),
 		   "Reading CONTROL_1 failed");
 	zassert_equal(reg & SYV682X_CONTROL_1_PWR_ENB, 0,
 		      "Power path disabled after HV_OC handled");
-	syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_OC_HV,
+	syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_OC_HV,
 				   SYV682X_CONTROL_4_NONE);
 	/* Alert GPIO doesn't change so wait for delayed syv682x interrupt */
 	msleep(15);
-	zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_1_REG,
-					&reg),
+	zassume_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_1_REG, &reg),
 		   "Reading CONTROL_1 failed");
 	zassert_equal(reg & SYV682X_CONTROL_1_PWR_ENB, 0,
 		      "Power path disabled after HV_OC handled");
-	syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_OC_HV,
+	syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_OC_HV,
 				   SYV682X_CONTROL_4_NONE);
 	/* Alert GPIO doesn't change so wait for delayed syv682x interrupt */
 	msleep(15);
-	zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_1_REG,
-					&reg),
+	zassume_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_1_REG, &reg),
 		   "Reading CONTROL_1 failed");
 	zassert_equal(reg & SYV682X_CONTROL_1_PWR_ENB,
 		      SYV682X_CONTROL_1_PWR_ENB,
@@ -327,18 +336,18 @@ ZTEST_F(ppc_syv682x, test_syv682x_interrupt_vconn_oc)
 	 * VCONN off.
 	 */
 	ppc_set_vconn(syv682x_port, true);
-	syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_NONE,
+	syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_NONE,
 				   SYV682X_CONTROL_4_VCONN_OCP);
 	msleep(1);
-	zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_4_REG,
-					&reg),
+	zassume_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_4_REG, &reg),
 		   "Reading CONTROL_4 failed");
 	zassert_true(reg & (SYV682X_CONTROL_4_VCONN1 |
 			    SYV682X_CONTROL_4_VCONN2),
 		     "VCONN disabled after initial VCONN OC");
 	msleep(50);
-	zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_4_REG,
-					&reg),
+	zassume_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_4_REG, &reg),
 		   "Reading CONTROL_4 failed");
 	zassert_true(reg & (SYV682X_CONTROL_4_VCONN1 |
 			    SYV682X_CONTROL_4_VCONN2),
@@ -348,8 +357,8 @@ ZTEST_F(ppc_syv682x, test_syv682x_interrupt_vconn_oc)
 	 * should turn VCONN off.
 	 */
 	msleep(60);
-	zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_4_REG,
-					&reg),
+	zassume_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_4_REG, &reg),
 		   "Reading CONTROL_4 failed");
 	zassert_false(reg & (SYV682X_CONTROL_4_VCONN1 |
 			     SYV682X_CONTROL_4_VCONN2),
@@ -367,11 +376,11 @@ ZTEST_F(ppc_syv682x, test_syv682x_interrupt_vconn_ov)
 	 * driver should then run generic CC over-voltage handling.
 	 */
 	ppc_set_vconn(syv682x_port, true);
-	syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_NONE,
+	syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_NONE,
 				   SYV682X_CONTROL_4_VBAT_OVP);
 	msleep(1);
-	zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_4_REG,
-					&reg),
+	zassume_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_4_REG, &reg),
 		   "Reading CONTROL_4 failed");
 	zassert_true(reg & SYV682X_CONTROL_4_CC1_BPS,
 		     "CC1 disabled after handling VBAT_OVP");
@@ -397,10 +406,10 @@ ZTEST_F(ppc_syv682x, test_syv682x_frs_enable)
 		      "PPC is sourcing VBUS after sink enabled");
 	ppc_set_polarity(syv682x_port, 0 /* CC1 */);
 	ppc_set_frs_enable(syv682x_port, true);
-	zassert_equal(gpio_emul_output_get(gpio_dev, this->frs_en_gpio_pin), 1,
-		      "FRS enabled, but FRS GPIO not asserted");
-	zassert_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_4_REG,
-					&reg),
+	zassert_equal(gpio_emul_output_get(gpio_dev, fixture->frs_en_gpio_pin),
+		      1, "FRS enabled, but FRS GPIO not asserted");
+	zassert_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_4_REG, &reg),
 		   "Reading CONTROL_4 failed");
 	zassert_equal(
 		reg & (SYV682X_CONTROL_4_CC1_BPS | SYV682X_CONTROL_4_CC2_BPS),
@@ -420,10 +429,10 @@ ZTEST_F(ppc_syv682x, test_syv682x_frs_disable)
 	ppc_set_polarity(syv682x_port, 0 /* CC1 */);
 
 	ppc_set_frs_enable(syv682x_port, false);
-	zassert_equal(gpio_emul_output_get(gpio_dev, this->frs_en_gpio_pin), 0,
-		      "FRS disabled, but FRS GPIO not deasserted");
-	zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_4_REG,
-					&reg),
+	zassert_equal(gpio_emul_output_get(gpio_dev, fixture->frs_en_gpio_pin),
+		      0, "FRS disabled, but FRS GPIO not deasserted");
+	zassume_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_4_REG, &reg),
 		   "Reading CONTROL_4 failed");
 	zassert_equal(
 		reg & (SYV682X_CONTROL_4_CC1_BPS | SYV682X_CONTROL_4_CC2_BPS),
@@ -437,12 +446,12 @@ ZTEST_F(ppc_syv682x, test_syv682x_frs_trigger)
 	 * An FRS event when the PPC is Sink should cause the PPC to switch from
 	 * Sink to Source.
 	 */
-	syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_FRS,
+	syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_FRS,
 				   SYV682X_CONTROL_4_NONE);
 	msleep(1);
 	zassert_true(ppc_is_sourcing_vbus(syv682x_port),
 		     "PPC is not sourcing VBUS after FRS signal handled");
-	syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_NONE,
+	syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_NONE,
 				   SYV682X_CONTROL_4_NONE);
 }
 
@@ -454,8 +463,8 @@ ZTEST_F(ppc_syv682x, test_syv682x_source_current_limit_usb_default)
 	zassert_ok(ppc_set_vbus_source_current_limit(syv682x_port,
 						     TYPEC_RP_USB),
 		   "Could not set source current limit");
-	zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_1_REG,
-					&reg),
+	zassume_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_1_REG, &reg),
 		   "Reading CONTROL_1 failed");
 	ilim_val = (reg & SYV682X_5V_ILIM_MASK) >> SYV682X_5V_ILIM_BIT_SHIFT;
 	zassert_equal(reg & SYV682X_5V_ILIM_MASK, SYV682X_5V_ILIM_1_25,
@@ -470,8 +479,8 @@ ZTEST_F(ppc_syv682x, test_syv682x_source_current_limit_1500ma)
 	zassert_ok(ppc_set_vbus_source_current_limit(syv682x_port,
 						     TYPEC_RP_1A5),
 		   "Could not set source current limit");
-	zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_1_REG,
-					&reg),
+	zassume_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_1_REG, &reg),
 		   "Reading CONTROL_1 failed");
 	ilim_val = (reg & SYV682X_5V_ILIM_MASK) >> SYV682X_5V_ILIM_BIT_SHIFT;
 	zassert_equal(ilim_val, SYV682X_5V_ILIM_1_75,
@@ -486,8 +495,8 @@ ZTEST_F(ppc_syv682x, test_syv682x_source_current_limit_3000ma)
 	zassert_ok(ppc_set_vbus_source_current_limit(syv682x_port,
 						     TYPEC_RP_3A0),
 		   "Could not set source current limit");
-	zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_1_REG,
-					&reg),
+	zassume_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_1_REG, &reg),
 		   "Reading CONTROL_1 failed");
 	ilim_val = (reg & SYV682X_5V_ILIM_MASK) >> SYV682X_5V_ILIM_BIT_SHIFT;
 	zassert_equal(ilim_val, SYV682X_5V_ILIM_3_30,
@@ -503,7 +512,7 @@ ZTEST_F(ppc_syv682x, test_syv682x_write_busy)
 	 * timeout. It is not a goal of this test to verify the frequency of
 	 * polling or the exact value of the timeout.
 	 */
-	syv682x_emul_set_busy_reads(this->ppc_emul, 1000);
+	syv682x_emul_set_busy_reads(fixture->ppc_emul, 1000);
 	zassert_equal(ppc_set_vbus_source_current_limit(syv682x_port,
 							TYPEC_RP_USB),
 		      EC_ERROR_TIMEOUT, "SYV682 busy, but write completed");
@@ -514,12 +523,12 @@ ZTEST_F(ppc_syv682x, test_syv682x_write_busy)
 	 * If the busy bit clears before the driver reaches its timeout, the
 	 * write should succeed.
 	 */
-	syv682x_emul_set_busy_reads(this->ppc_emul, 1);
+	syv682x_emul_set_busy_reads(fixture->ppc_emul, 1);
 	zassert_equal(ppc_set_vbus_source_current_limit(syv682x_port,
 							TYPEC_RP_USB),
 		      0, "SYV682 not busy, but write failed");
 
-	syv682x_emul_set_busy_reads(this->ppc_emul, 0);
+	syv682x_emul_set_busy_reads(fixture->ppc_emul, 0);
 }
 
 ZTEST_F(ppc_syv682x, test_syv682x_dev_is_connected)
@@ -528,16 +537,16 @@ ZTEST_F(ppc_syv682x, test_syv682x_dev_is_connected)
 
 	zassert_ok(ppc_dev_is_connected(syv682x_port, PPC_DEV_SRC),
 		   "Could not connect device as source");
-	zassert_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_2_REG,
-					&reg),
+	zassert_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_2_REG, &reg),
 		   "Reading CONTROL_2 failed");
 	zassert_false(reg & SYV682X_CONTROL_2_FDSG,
 		      "Connected as source, but force discharge enabled");
 
 	zassert_ok(ppc_dev_is_connected(syv682x_port, PPC_DEV_DISCONNECTED),
 		   "Could not disconnect device");
-	zassert_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_2_REG,
-					&reg),
+	zassert_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_2_REG, &reg),
 		   "Reading CONTROL_2 failed");
 	zassert_true(reg & SYV682X_CONTROL_2_FDSG,
 		     "Disconnected, but force discharge disabled");
@@ -571,8 +580,8 @@ ZTEST_F(ppc_syv682x, test_syv682x_vbus_sink_enable_power_path)
 		   "VBUS enable failed");
 	zassert_ok(ppc_vbus_sink_enable(syv682x_port, true),
 		   "Sink disable failed");
-	zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_1_REG,
-					&reg),
+	zassume_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_1_REG, &reg),
 		   NULL);
 	zassert_true(reg & SYV682X_CONTROL_1_CH_SEL,
 		     "Sink enabled, but CH_SEL set to 5V power path");
@@ -596,8 +605,8 @@ ZTEST_F(ppc_syv682x, test_syv682x_vbus_sink_disable)
 
 	zassert_ok(ppc_vbus_sink_enable(syv682x_port, false),
 		   "Sink disable failed");
-	zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_1_REG,
-					&reg),
+	zassume_ok(syv682x_emul_get_reg(fixture->ppc_emul,
+					SYV682X_CONTROL_1_REG, &reg),
 		   NULL);
 	zassert_true(reg & SYV682X_CONTROL_1_PWR_ENB,
 		     "Sink disabled, but power path enabled");
@@ -613,11 +622,12 @@ ZTEST_F(ppc_syv682x, test_syv682x_vbus_sink_oc_limit)
 	 * cleared by sink disable.
 	 */
 	for (int i = 0; i < 4; ++i) {
-		syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_OC_HV,
+		syv682x_emul_set_condition(fixture->ppc_emul,
+					   SYV682X_STATUS_OC_HV,
 					   SYV682X_CONTROL_4_NONE);
 		msleep(15);
 	}
-	syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_NONE,
+	syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_NONE,
 				   SYV682X_CONTROL_4_NONE);
 
 	zassert_not_equal(ppc_vbus_sink_enable(syv682x_port, true), EC_SUCCESS,
@@ -633,7 +643,7 @@ ZTEST_F(ppc_syv682x, test_syv682x_vbus_sink_oc_limit)
 
 ZTEST_F(ppc_syv682x, test_syv682x_set_vconn)
 {
-	syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_NONE,
+	syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_NONE,
 				   SYV682X_CONTROL_4_VBAT_OVP);
 	zassert_not_equal(ppc_set_vconn(syv682x_port, true), EC_SUCCESS,
 			  "VBAT OVP, but ppc_set_vconn succeeded");
@@ -654,7 +664,7 @@ ZTEST(ppc_syv682x, test_syv682x_ppc_dump)
  * reg_access_to_fail on read number N, where N is the initial value of
  * reg_access_fail_countdown.
  */
-static int mock_read_intercept_reg_fail(struct i2c_emul *emul, int reg,
+static int mock_read_intercept_reg_fail(const struct emul *emul, int reg,
 					uint8_t *val, int bytes, void *data)
 {
 	struct reg_to_fail_data *test_data = data;
@@ -670,10 +680,11 @@ static int mock_read_intercept_reg_fail(struct i2c_emul *emul, int reg,
 ZTEST_F(ppc_syv682x, test_syv682x_i2c_error_status)
 {
 	/* Failed STATUS read should cause init to fail. */
-	i2c_common_emul_set_read_fail_reg(this->ppc_emul, SYV682X_STATUS_REG);
+	i2c_common_emul_set_read_fail_reg(fixture->common_data,
+					  SYV682X_STATUS_REG);
 	zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS,
 			  "STATUS read error, but init succeeded");
-	i2c_common_emul_set_read_fail_reg(this->ppc_emul,
+	i2c_common_emul_set_read_fail_reg(fixture->common_data,
 					  I2C_COMMON_EMUL_NO_FAIL_REG);
 }
 
@@ -686,7 +697,7 @@ ZTEST_F(ppc_syv682x, test_syv682x_i2c_error_control_1)
 	};
 
 	/* Failed CONTROL_1 read */
-	i2c_common_emul_set_read_fail_reg(this->ppc_emul,
+	i2c_common_emul_set_read_fail_reg(fixture->common_data,
 					  SYV682X_CONTROL_1_REG);
 	zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS,
 			  "CONTROL_1 read error, but init succeeded");
@@ -704,34 +715,34 @@ ZTEST_F(ppc_syv682x, test_syv682x_i2c_error_control_1)
 			  "succeeded");
 	zassert_ok(drv->reg_dump(syv682x_port),
 		   "CONTROL_1 read error, and ppc_dump failed");
-	i2c_common_emul_set_read_fail_reg(this->ppc_emul,
+	i2c_common_emul_set_read_fail_reg(fixture->common_data,
 					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Init reads CONTROL_1 several times. The 3rd read happens while
 	 * setting the source current limit. Check that init fails when that
 	 * read fails.
 	 */
-	i2c_common_emul_set_read_func(this->ppc_emul,
+	i2c_common_emul_set_read_func(fixture->common_data,
 				      &mock_read_intercept_reg_fail, &reg_fail);
 	reg_fail.reg_access_to_fail = SYV682X_CONTROL_1_REG;
 	reg_fail.reg_access_fail_countdown = 3;
 	zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS,
 			  "CONTROL_1 read error, but init succeeded");
-	i2c_common_emul_set_read_func(this->ppc_emul, NULL, NULL);
+	i2c_common_emul_set_read_func(fixture->common_data, NULL, NULL);
 
 	/* Failed CONTROL_1 write */
-	i2c_common_emul_set_write_fail_reg(this->ppc_emul,
+	i2c_common_emul_set_write_fail_reg(fixture->common_data,
 					   SYV682X_CONTROL_1_REG);
 
 	/* During init, the driver will write CONTROL_1 either to disable all
 	 * power paths (normal case) or to enable the sink path (dead battery
 	 * case). vSafe0V in STATUS is one indication of the normal case.
 	 */
-	syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_VSAFE_0V,
+	syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_VSAFE_0V,
 				   SYV682X_CONTROL_4_NONE);
 	zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS,
 			  "CONTROL_1 write error, but init succeeded");
-	syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_NONE,
+	syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_NONE,
 				   SYV682X_CONTROL_4_NONE);
 	zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS,
 			  "CONTROL_1 write error, but init succeeded");
@@ -740,65 +751,65 @@ ZTEST_F(ppc_syv682x, test_syv682x_i2c_error_control_1)
 			  EC_SUCCESS,
 			  "CONTROL_1 write error, but VBUS source "
 			  "enable succeeded");
-	i2c_common_emul_set_write_fail_reg(this->ppc_emul,
+	i2c_common_emul_set_write_fail_reg(fixture->common_data,
 					   I2C_COMMON_EMUL_NO_FAIL_REG);
 }
 
 ZTEST_F(ppc_syv682x, test_syv682x_i2c_error_control_2)
 {
 	/* Failed CONTROL_2 read */
-	i2c_common_emul_set_read_fail_reg(this->ppc_emul,
+	i2c_common_emul_set_read_fail_reg(fixture->common_data,
 					  SYV682X_CONTROL_2_REG);
 	zassert_not_equal(ppc_discharge_vbus(syv682x_port, true), EC_SUCCESS,
 			  "CONTROL_2 read error, but VBUS discharge succeeded");
-	i2c_common_emul_set_read_fail_reg(this->ppc_emul,
+	i2c_common_emul_set_read_fail_reg(fixture->common_data,
 					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Failed CONTROL_2 write */
-	i2c_common_emul_set_write_fail_reg(this->ppc_emul,
+	i2c_common_emul_set_write_fail_reg(fixture->common_data,
 					   SYV682X_CONTROL_2_REG);
 	zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS,
 			  "CONTROL_2 write error, but init succeeded");
-	i2c_common_emul_set_write_fail_reg(this->ppc_emul,
+	i2c_common_emul_set_write_fail_reg(fixture->common_data,
 					   I2C_COMMON_EMUL_NO_FAIL_REG);
 }
 
 ZTEST_F(ppc_syv682x, test_syv682x_i2c_error_control_3)
 {
 	/* Failed CONTROL_3 read */
-	i2c_common_emul_set_read_fail_reg(this->ppc_emul,
+	i2c_common_emul_set_read_fail_reg(fixture->common_data,
 					  SYV682X_CONTROL_3_REG);
 	zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS,
 			  "CONTROL_3 read error, but VBUS discharge succeeded");
-	i2c_common_emul_set_read_fail_reg(this->ppc_emul,
+	i2c_common_emul_set_read_fail_reg(fixture->common_data,
 					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Failed CONTROL_3 write */
-	i2c_common_emul_set_write_fail_reg(this->ppc_emul,
+	i2c_common_emul_set_write_fail_reg(fixture->common_data,
 					   SYV682X_CONTROL_3_REG);
 	zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS,
 			  "CONTROL_3 write error, but init succeeded");
-	i2c_common_emul_set_write_fail_reg(this->ppc_emul,
+	i2c_common_emul_set_write_fail_reg(fixture->common_data,
 					   I2C_COMMON_EMUL_NO_FAIL_REG);
 }
 
 ZTEST_F(ppc_syv682x, test_syv682x_i2c_error_control_4)
 {
 	/* Failed CONTROL_4 read */
-	i2c_common_emul_set_read_fail_reg(this->ppc_emul,
+	i2c_common_emul_set_read_fail_reg(fixture->common_data,
 					  SYV682X_CONTROL_4_REG);
 	zassert_not_equal(ppc_set_vconn(syv682x_port, true), EC_SUCCESS,
 			  "CONTROL_2 read error, but VCONN set succeeded");
-	i2c_common_emul_set_read_fail_reg(this->ppc_emul,
+	i2c_common_emul_set_read_fail_reg(fixture->common_data,
 					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Failed CONTROL_4 write */
-	i2c_common_emul_set_write_fail_reg(this->ppc_emul,
+	i2c_common_emul_set_write_fail_reg(fixture->common_data,
 					   SYV682X_CONTROL_4_REG);
 	zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS,
 			  "CONTROL_4 write error, but init succeeded");
 	zassert_not_equal(ppc_set_vconn(syv682x_port, true), EC_SUCCESS,
 			  "CONTROL_4 write error, but VCONN set succeeded");
-	i2c_common_emul_set_write_fail_reg(this->ppc_emul,
+	i2c_common_emul_set_write_fail_reg(fixture->common_data,
 					   I2C_COMMON_EMUL_NO_FAIL_REG);
 }
diff --git a/zephyr/test/drivers/src/ps8xxx.c b/zephyr/test/drivers/default/src/ps8xxx.c
index dc1695d793..29d720a639 100644
--- a/zephyr/test/drivers/src/ps8xxx.c
+++ b/zephyr/test/drivers/default/src/ps8xxx.c
@@ -1,10 +1,10 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <zephyr/zephyr.h>
-#include <ztest.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
 
 #include "common.h"
 #include "emul/emul_common_i2c.h"
@@ -20,32 +20,32 @@
 #include "driver/tcpm/ps8xxx_public.h"
 #include "test/drivers/test_state.h"
 
-#define PS8XXX_EMUL_LABEL	DT_LABEL(DT_NODELABEL(ps8xxx_emul))
+#define PS8XXX_EMUL_NODE DT_NODELABEL(ps8xxx_emul)
 
 /** Test PS8xxx init fail conditions common for all PS8xxx devices */
 static void test_ps8xxx_init_fail(void)
 {
-	const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL);
-	const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul);
-	struct i2c_emul *tcpci_i2c_emul = tcpci_emul_get_i2c_emul(tcpci_emul);
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(ps8xxx_emul);
 
 	/* Test fail on FW reg read */
-	i2c_common_emul_set_read_fail_reg(tcpci_i2c_emul, PS8XXX_REG_FW_REV);
+	i2c_common_emul_set_read_fail_reg(common_data, PS8XXX_REG_FW_REV);
 	zassert_equal(EC_ERROR_TIMEOUT, ps8xxx_tcpm_drv.init(USBC_PORT_C1),
 		      NULL);
-	i2c_common_emul_set_read_fail_reg(tcpci_i2c_emul,
+	i2c_common_emul_set_read_fail_reg(common_data,
 					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test fail on FW reg set to 0 */
-	tcpci_emul_set_reg(tcpci_emul, PS8XXX_REG_FW_REV, 0x0);
+	tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, 0x0);
 	zassert_equal(EC_ERROR_TIMEOUT, ps8xxx_tcpm_drv.init(USBC_PORT_C1),
 		      NULL);
 
 	/* Set arbitrary FW reg value != 0 for rest of the test */
-	tcpci_emul_set_reg(tcpci_emul, PS8XXX_REG_FW_REV, 0x31);
+	tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, 0x31);
 
 	/* Test fail on TCPCI init */
-	tcpci_emul_set_reg(tcpci_emul, TCPC_REG_POWER_STATUS,
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_POWER_STATUS,
 			   TCPC_REG_POWER_STATUS_UNINIT);
 	zassert_equal(EC_ERROR_TIMEOUT, ps8xxx_tcpm_drv.init(USBC_PORT_C1),
 		      NULL);
@@ -67,61 +67,60 @@ ZTEST(ps8815, test_init_fail)
  */
 ZTEST(ps8805, test_ps8805_init)
 {
-	const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL);
-	const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul);
-	struct i2c_emul *p1_i2c_emul =
-		ps8xxx_emul_get_i2c_emul(ps8xxx_emul, PS8XXX_EMUL_PORT_1);
-	struct i2c_emul *tcpci_i2c_emul = tcpci_emul_get_i2c_emul(tcpci_emul);
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(ps8xxx_emul);
+	struct i2c_common_emul_data *p1_i2c_common_data =
+		ps8xxx_emul_get_i2c_common_data(ps8xxx_emul,
+						PS8XXX_EMUL_PORT_1);
 
 	/* Set arbitrary FW reg value != 0 for this test */
-	tcpci_emul_set_reg(tcpci_emul, PS8XXX_REG_FW_REV, 0x31);
+	tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, 0x31);
 	/* Set correct power status for this test */
-	tcpci_emul_set_reg(tcpci_emul, TCPC_REG_POWER_STATUS, 0x0);
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_POWER_STATUS, 0x0);
 
 	/* Test fail on read I2C debug reg */
-	i2c_common_emul_set_read_fail_reg(tcpci_i2c_emul,
+	i2c_common_emul_set_read_fail_reg(common_data,
 					  PS8XXX_REG_I2C_DEBUGGING_ENABLE);
-	zassert_equal(EC_ERROR_INVAL, ps8xxx_tcpm_drv.init(USBC_PORT_C1),
-		      NULL);
-	i2c_common_emul_set_read_fail_reg(tcpci_i2c_emul,
+	zassert_equal(EC_ERROR_INVAL, ps8xxx_tcpm_drv.init(USBC_PORT_C1), NULL);
+	i2c_common_emul_set_read_fail_reg(common_data,
 					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test fail on read DCI reg */
-	i2c_common_emul_set_read_fail_reg(p1_i2c_emul,
+	i2c_common_emul_set_read_fail_reg(p1_i2c_common_data,
 					  PS8XXX_P1_REG_MUX_USB_DCI_CFG);
-	zassert_equal(EC_ERROR_INVAL, ps8xxx_tcpm_drv.init(USBC_PORT_C1),
-		      NULL);
-	i2c_common_emul_set_read_fail_reg(p1_i2c_emul,
+	zassert_equal(EC_ERROR_INVAL, ps8xxx_tcpm_drv.init(USBC_PORT_C1), NULL);
+	i2c_common_emul_set_read_fail_reg(p1_i2c_common_data,
 					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test successful init */
 	zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.init(USBC_PORT_C1), NULL);
-	check_tcpci_reg(tcpci_emul, PS8XXX_REG_I2C_DEBUGGING_ENABLE,
+	check_tcpci_reg(ps8xxx_emul, PS8XXX_REG_I2C_DEBUGGING_ENABLE,
 			PS8XXX_REG_I2C_DEBUGGING_ENABLE_ON);
 	zassert_equal(PS8XXX_REG_MUX_USB_DCI_CFG_MODE_OFF,
 		      ps8xxx_emul_get_dci_cfg(ps8xxx_emul) &
-		      PS8XXX_REG_MUX_USB_DCI_CFG_MODE_MASK, NULL);
+			      PS8XXX_REG_MUX_USB_DCI_CFG_MODE_MASK,
+		      NULL);
 }
 
 /** Test PS8815 init */
 ZTEST(ps8815, test_ps8815_init)
 {
-	const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL);
-	const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul);
-	struct i2c_emul *p1_i2c_emul =
-		ps8xxx_emul_get_i2c_emul(ps8xxx_emul, PS8XXX_EMUL_PORT_1);
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *p1_i2c_common_data =
+		ps8xxx_emul_get_i2c_common_data(ps8xxx_emul,
+						PS8XXX_EMUL_PORT_1);
 
 	/* Set arbitrary FW reg value != 0 for this test */
-	tcpci_emul_set_reg(tcpci_emul, PS8XXX_REG_FW_REV, 0x31);
+	tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, 0x31);
 	/* Set correct power status for rest of the test */
-	tcpci_emul_set_reg(tcpci_emul, TCPC_REG_POWER_STATUS, 0x0);
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_POWER_STATUS, 0x0);
 
 	/* Test fail on reading HW revision register */
-	i2c_common_emul_set_read_fail_reg(p1_i2c_emul,
+	i2c_common_emul_set_read_fail_reg(p1_i2c_common_data,
 					  PS8815_P1_REG_HW_REVISION);
-	zassert_equal(EC_ERROR_INVAL, ps8xxx_tcpm_drv.init(USBC_PORT_C1),
-		      NULL);
-	i2c_common_emul_set_read_fail_reg(p1_i2c_emul,
+	zassert_equal(EC_ERROR_INVAL, ps8xxx_tcpm_drv.init(USBC_PORT_C1), NULL);
+	i2c_common_emul_set_read_fail_reg(p1_i2c_common_data,
 					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test successful init */
@@ -131,23 +130,22 @@ ZTEST(ps8815, test_ps8815_init)
 /** Test PS8xxx release */
 static void test_ps8xxx_release(void)
 {
-	const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL);
-	const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul);
-	struct i2c_emul *tcpci_i2c_emul = tcpci_emul_get_i2c_emul(tcpci_emul);
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(ps8xxx_emul);
+
 	uint64_t start_ms;
 
 	/* Test successful release with correct FW reg read */
 	start_ms = k_uptime_get();
-	zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.release(USBC_PORT_C1),
-		      NULL);
+	zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.release(USBC_PORT_C1), NULL);
 	zassert_true(k_uptime_get() - start_ms < 10,
 		     "release on correct FW reg read shouldn't wait for chip");
 
 	/* Test delay on FW reg read fail */
-	i2c_common_emul_set_read_fail_reg(tcpci_i2c_emul, PS8XXX_REG_FW_REV);
+	i2c_common_emul_set_read_fail_reg(common_data, PS8XXX_REG_FW_REV);
 	start_ms = k_uptime_get();
-	zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.release(USBC_PORT_C1),
-		      NULL);
+	zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.release(USBC_PORT_C1), NULL);
 	zassert_true(k_uptime_get() - start_ms >= 10,
 		     "release on FW reg read fail should wait for chip");
 }
@@ -169,12 +167,11 @@ ZTEST(ps8815, test_release)
 static void check_ps8815_set_cc(enum tcpc_rp_value rp, enum tcpc_cc_pull cc,
 				uint16_t rp_detect_ctrl, const char *test_case)
 {
-	const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL);
-	const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul);
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
 	uint16_t reg_val, exp_role_ctrl;
 
 	/* Clear RP detect register to see if it is set after test */
-	tcpci_emul_set_reg(tcpci_emul, PS8XXX_REG_RP_DETECT_CONTROL, 0);
+	tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_RP_DETECT_CONTROL, 0);
 
 	exp_role_ctrl = TCPC_REG_ROLE_CTRL_SET(TYPEC_NO_DRP, rp, cc, cc);
 
@@ -184,12 +181,13 @@ static void check_ps8815_set_cc(enum tcpc_rp_value rp, enum tcpc_cc_pull cc,
 	zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.set_cc(USBC_PORT_C1, cc),
 		      "Failed to set CC for case: %s", test_case);
 
-	zassert_ok(tcpci_emul_get_reg(tcpci_emul, TCPC_REG_ROLE_CTRL, &reg_val),
+	zassert_ok(tcpci_emul_get_reg(ps8xxx_emul, TCPC_REG_ROLE_CTRL,
+				      &reg_val),
 		   "Failed tcpci_emul_get_reg() for case: %s", test_case);
 	zassert_equal(exp_role_ctrl, reg_val,
 		      "0x%x != (role_ctrl = 0x%x) for case: %s", exp_role_ctrl,
 		      reg_val, test_case);
-	zassert_ok(tcpci_emul_get_reg(tcpci_emul, PS8XXX_REG_RP_DETECT_CONTROL,
+	zassert_ok(tcpci_emul_get_reg(ps8xxx_emul, PS8XXX_REG_RP_DETECT_CONTROL,
 				      &reg_val),
 		   "Failed tcpci_emul_get_reg() for case: %s", test_case);
 	zassert_equal(rp_detect_ctrl, reg_val,
@@ -200,13 +198,19 @@ static void check_ps8815_set_cc(enum tcpc_rp_value rp, enum tcpc_cc_pull cc,
 /** Test PS8815 set cc and device specific workarounds */
 ZTEST(ps8815, test_ps8815_set_cc)
 {
-	const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL);
-	const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul);
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
 	int64_t start_time;
 	int64_t delay;
 
+	/*
+	 * Set other hw revision to disable workaround for b/171430855 (delay
+	 * 1 ms on role control reg update). Delay could introduce thread switch
+	 * which may disturb this test.
+	 */
+	ps8xxx_emul_set_hw_rev(ps8xxx_emul, 0x0a02);
+
 	/* Set firmware version <= 0x10 to set "disable rp detect" workaround */
-	tcpci_emul_set_reg(tcpci_emul, PS8XXX_REG_FW_REV, 0x8);
+	tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, 0x8);
 	zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.init(USBC_PORT_C1), NULL);
 
 	check_ps8815_set_cc(TYPEC_RP_1A5, TYPEC_CC_RP, RP_DETECT_DISABLE,
@@ -226,7 +230,7 @@ ZTEST(ps8815, test_ps8815_set_cc)
 	 * Set firmware version <= 0x10 to set "disable rp detect" workaround
 	 * again
 	 */
-	tcpci_emul_set_reg(tcpci_emul, PS8XXX_REG_FW_REV, 0xa);
+	tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, 0xa);
 	zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.init(USBC_PORT_C1), NULL);
 
 	/* CC RD shouldn't trigger "disable rp detect" workaround */
@@ -237,7 +241,7 @@ ZTEST(ps8815, test_ps8815_set_cc)
 	 * Set firmware version > 0x10 to unset "disable rp detect"
 	 * workaround
 	 */
-	tcpci_emul_set_reg(tcpci_emul, PS8XXX_REG_FW_REV, 0x12);
+	tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, 0x12);
 	zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.init(USBC_PORT_C1), NULL);
 
 	/* Firmware > 0x10 shouldn't trigger "disable rp detect" workaround */
@@ -255,8 +259,8 @@ ZTEST(ps8815, test_ps8815_set_cc)
 	check_ps8815_set_cc(TYPEC_RP_1A5, TYPEC_CC_RP, 0,
 			    "delay on HW rev 0x0a00");
 	delay = k_uptime_delta(&start_time);
-	zassert_true(delay >= 1,
-		     "expected delay on HW rev 0x0a00 (delay %lld)", delay);
+	zassert_true(delay >= 1, "expected delay on HW rev 0x0a00 (delay %lld)",
+		     delay);
 
 	/*
 	 * Set hw revision 0x0a01 to enable workaround for b/171430855 (delay
@@ -268,8 +272,8 @@ ZTEST(ps8815, test_ps8815_set_cc)
 	check_ps8815_set_cc(TYPEC_RP_1A5, TYPEC_CC_RP, 0,
 			    "delay on HW rev 0x0a01");
 	delay = k_uptime_delta(&start_time);
-	zassert_true(delay >= 1,
-		     "expected delay on HW rev 0x0a01 (delay %lld)", delay);
+	zassert_true(delay >= 1, "expected delay on HW rev 0x0a01 (delay %lld)",
+		     delay);
 
 	/*
 	 * Set other hw revision to disable workaround for b/171430855 (delay
@@ -319,47 +323,51 @@ ZTEST(ps8815, test_set_vconn)
 /** Test PS8xxx transmitting message from TCPC */
 static void test_ps8xxx_transmit(void)
 {
-	const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL);
-	const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul);
-	struct i2c_emul *tcpci_i2c_emul = tcpci_emul_get_i2c_emul(tcpci_emul);
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(ps8xxx_emul);
+
 	struct tcpci_emul_msg *msg;
 	uint64_t exp_cnt, cnt;
 	uint16_t reg_val;
 
-	msg = tcpci_emul_get_tx_msg(tcpci_emul);
+	msg = tcpci_emul_get_tx_msg(ps8xxx_emul);
 
 	/* Test fail on transmitting BIST MODE 2 message */
-	i2c_common_emul_set_write_fail_reg(tcpci_i2c_emul, TCPC_REG_TRANSMIT);
+	i2c_common_emul_set_write_fail_reg(common_data, TCPC_REG_TRANSMIT);
 	zassert_equal(EC_ERROR_INVAL,
-		      ps8xxx_tcpm_drv.transmit(USBC_PORT_C1,
-					       TCPCI_MSG_TX_BIST_MODE_2, 0,
-					       NULL), NULL);
-	i2c_common_emul_set_write_fail_reg(tcpci_i2c_emul,
+		      ps8xxx_tcpm_drv.transmit(
+			      USBC_PORT_C1, TCPCI_MSG_TX_BIST_MODE_2, 0, NULL),
+		      NULL);
+	i2c_common_emul_set_write_fail_reg(common_data,
 					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test sending BIST MODE 2 message */
 	exp_cnt = PS8751_BIST_COUNTER;
 	zassert_equal(EC_SUCCESS,
-		      ps8xxx_tcpm_drv.transmit(USBC_PORT_C1,
-					       TCPCI_MSG_TX_BIST_MODE_2, 0,
-					       NULL), NULL);
-	check_tcpci_reg(tcpci_emul, PS8XXX_REG_BIST_CONT_MODE_CTR, 0);
-	zassert_equal(TCPCI_MSG_TX_BIST_MODE_2, msg->type, NULL);
+		      ps8xxx_tcpm_drv.transmit(
+			      USBC_PORT_C1, TCPCI_MSG_TX_BIST_MODE_2, 0, NULL),
+		      NULL);
+	check_tcpci_reg(ps8xxx_emul, PS8XXX_REG_BIST_CONT_MODE_CTR, 0);
+	zassert_equal(TCPCI_MSG_TX_BIST_MODE_2, msg->sop_type, NULL);
 
 	/* Check BIST counter value */
-	zassert_ok(tcpci_emul_get_reg(tcpci_emul,
+	zassert_ok(tcpci_emul_get_reg(ps8xxx_emul,
 				      PS8XXX_REG_BIST_CONT_MODE_BYTE2,
-				      &reg_val), NULL);
+				      &reg_val),
+		   NULL);
 	cnt = reg_val;
 	cnt <<= 8;
-	zassert_ok(tcpci_emul_get_reg(tcpci_emul,
+	zassert_ok(tcpci_emul_get_reg(ps8xxx_emul,
 				      PS8XXX_REG_BIST_CONT_MODE_BYTE1,
-				      &reg_val), NULL);
+				      &reg_val),
+		   NULL);
 	cnt |= reg_val;
 	cnt <<= 8;
-	zassert_ok(tcpci_emul_get_reg(tcpci_emul,
+	zassert_ok(tcpci_emul_get_reg(ps8xxx_emul,
 				      PS8XXX_REG_BIST_CONT_MODE_BYTE0,
-				      &reg_val), NULL);
+				      &reg_val),
+		   NULL);
 	cnt |= reg_val;
 	zassert_equal(exp_cnt, cnt, "0x%llx != 0x%llx", exp_cnt, cnt);
 }
@@ -377,34 +385,35 @@ ZTEST(ps8815, test_transmit)
 /** Test PS8805 and PS8815 drp toggle */
 static void test_ps88x5_drp_toggle(bool delay_expected)
 {
-	const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL);
-	const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul);
-	struct i2c_emul *tcpci_i2c_emul = tcpci_emul_get_i2c_emul(tcpci_emul);
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(ps8xxx_emul);
+
 	uint16_t exp_role_ctrl;
 	int64_t start_time;
 	int64_t delay;
 
 	/* Test fail on command write */
-	i2c_common_emul_set_write_fail_reg(tcpci_i2c_emul, TCPC_REG_COMMAND);
+	i2c_common_emul_set_write_fail_reg(common_data, TCPC_REG_COMMAND);
 	zassert_equal(EC_ERROR_INVAL, ps8xxx_tcpm_drv.drp_toggle(USBC_PORT_C1),
 		      NULL);
 
 	/* Test fail on role control write */
-	i2c_common_emul_set_write_fail_reg(tcpci_i2c_emul, TCPC_REG_ROLE_CTRL);
+	i2c_common_emul_set_write_fail_reg(common_data, TCPC_REG_ROLE_CTRL);
 	zassert_equal(EC_ERROR_INVAL, ps8xxx_tcpm_drv.drp_toggle(USBC_PORT_C1),
 		      NULL);
-	i2c_common_emul_set_write_fail_reg(tcpci_i2c_emul,
+	i2c_common_emul_set_write_fail_reg(common_data,
 					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test fail on CC status read */
-	i2c_common_emul_set_read_fail_reg(tcpci_i2c_emul, TCPC_REG_CC_STATUS);
+	i2c_common_emul_set_read_fail_reg(common_data, TCPC_REG_CC_STATUS);
 	zassert_equal(EC_ERROR_INVAL, ps8xxx_tcpm_drv.drp_toggle(USBC_PORT_C1),
 		      NULL);
-	i2c_common_emul_set_read_fail_reg(tcpci_i2c_emul,
+	i2c_common_emul_set_read_fail_reg(common_data,
 					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Set CC status as snk, CC lines set arbitrary */
-	tcpci_emul_set_reg(tcpci_emul, TCPC_REG_CC_STATUS,
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_CC_STATUS,
 			   TCPC_REG_CC_STATUS_SET(1, TYPEC_CC_VOLT_OPEN,
 						  TYPEC_CC_VOLT_RA));
 
@@ -424,12 +433,12 @@ static void test_ps88x5_drp_toggle(bool delay_expected)
 	} else {
 		zassert_true(delay == 0, "unexpected delay (%lld ms)", delay);
 	}
-	check_tcpci_reg(tcpci_emul, TCPC_REG_ROLE_CTRL, exp_role_ctrl);
-	check_tcpci_reg(tcpci_emul, TCPC_REG_COMMAND,
+	check_tcpci_reg(ps8xxx_emul, TCPC_REG_ROLE_CTRL, exp_role_ctrl);
+	check_tcpci_reg(ps8xxx_emul, TCPC_REG_COMMAND,
 			TCPC_REG_COMMAND_LOOK4CONNECTION);
 
 	/* Set CC status as src, CC lines set arbitrary */
-	tcpci_emul_set_reg(tcpci_emul, TCPC_REG_CC_STATUS,
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_CC_STATUS,
 			   TCPC_REG_CC_STATUS_SET(0, TYPEC_CC_VOLT_OPEN,
 						  TYPEC_CC_VOLT_RA));
 
@@ -445,15 +454,15 @@ static void test_ps88x5_drp_toggle(bool delay_expected)
 	} else {
 		zassert_true(delay == 0, "unexpected delay (%lld ms)", delay);
 	}
-	check_tcpci_reg(tcpci_emul, TCPC_REG_ROLE_CTRL, exp_role_ctrl);
-	check_tcpci_reg(tcpci_emul, TCPC_REG_COMMAND,
+	check_tcpci_reg(ps8xxx_emul, TCPC_REG_ROLE_CTRL, exp_role_ctrl);
+	check_tcpci_reg(ps8xxx_emul, TCPC_REG_COMMAND,
 			TCPC_REG_COMMAND_LOOK4CONNECTION);
 }
 
 /** Test PS8815 drp toggle */
 ZTEST(ps8815, test_ps8815_drp_toggle)
 {
-	const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL);
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
 
 	/*
 	 * Set hw revision 0x0a00 to enable workaround for b/171430855 (delay
@@ -481,9 +490,10 @@ ZTEST(ps8805, test_drp_toggle)
 /** Test PS8xxx get chip info code used by all PS8xxx devices */
 static void test_ps8xxx_get_chip_info(uint16_t current_product_id)
 {
-	const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL);
-	const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul);
-	struct i2c_emul *tcpci_i2c_emul = tcpci_emul_get_i2c_emul(tcpci_emul);
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(ps8xxx_emul);
+
 	struct ec_response_pd_chip_info_v1 info;
 	uint16_t vendor, product, device_id, fw_rev;
 
@@ -495,17 +505,17 @@ static void test_ps8xxx_get_chip_info(uint16_t current_product_id)
 	device_id = 0x2;
 	/* Arbitrary revision */
 	fw_rev = 0x32;
-	tcpci_emul_set_reg(tcpci_emul, TCPC_REG_VENDOR_ID, vendor);
-	tcpci_emul_set_reg(tcpci_emul, TCPC_REG_PRODUCT_ID, product);
-	tcpci_emul_set_reg(tcpci_emul, TCPC_REG_BCD_DEV, device_id);
-	tcpci_emul_set_reg(tcpci_emul, PS8XXX_REG_FW_REV, fw_rev);
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_VENDOR_ID, vendor);
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_PRODUCT_ID, product);
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_BCD_DEV, device_id);
+	tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, fw_rev);
 
 	/* Test fail on reading FW revision */
-	i2c_common_emul_set_read_fail_reg(tcpci_i2c_emul, PS8XXX_REG_FW_REV);
+	i2c_common_emul_set_read_fail_reg(common_data, PS8XXX_REG_FW_REV);
 	zassert_equal(EC_ERROR_INVAL,
 		      ps8xxx_tcpm_drv.get_chip_info(USBC_PORT_C1, 1, &info),
 		      NULL);
-	i2c_common_emul_set_read_fail_reg(tcpci_i2c_emul,
+	i2c_common_emul_set_read_fail_reg(common_data,
 					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test reading chip info */
@@ -519,18 +529,18 @@ static void test_ps8xxx_get_chip_info(uint16_t current_product_id)
 
 	/* Test fail on wrong vendor id */
 	vendor = 0x0;
-	tcpci_emul_set_reg(tcpci_emul, TCPC_REG_VENDOR_ID, vendor);
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_VENDOR_ID, vendor);
 	zassert_equal(EC_ERROR_UNKNOWN,
 		      ps8xxx_tcpm_drv.get_chip_info(USBC_PORT_C1, 1, &info),
 		      NULL);
 
 	/* Set correct vendor id */
 	vendor = PS8XXX_VENDOR_ID;
-	tcpci_emul_set_reg(tcpci_emul, TCPC_REG_VENDOR_ID, vendor);
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_VENDOR_ID, vendor);
 
 	/* Set firmware revision to 0 */
 	fw_rev = 0x0;
-	tcpci_emul_set_reg(tcpci_emul, PS8XXX_REG_FW_REV, fw_rev);
+	tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, fw_rev);
 
 	/*
 	 * Test fail on firmware revision equals to 0 when getting chip info
@@ -554,7 +564,7 @@ static void test_ps8xxx_get_chip_info(uint16_t current_product_id)
 
 	/* Set wrong vendor id */
 	vendor = 0;
-	tcpci_emul_set_reg(tcpci_emul, TCPC_REG_VENDOR_ID, vendor);
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_VENDOR_ID, vendor);
 
 	/* Test fail on vendor id mismatch on live device */
 	zassert_equal(EC_ERROR_UNKNOWN,
@@ -572,11 +582,11 @@ static void test_ps8xxx_get_chip_info(uint16_t current_product_id)
 
 	/* Set correct vendor id */
 	vendor = PS8XXX_VENDOR_ID;
-	tcpci_emul_set_reg(tcpci_emul, TCPC_REG_VENDOR_ID, vendor);
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_VENDOR_ID, vendor);
 
 	/* Set wrong product id */
 	product = 0;
-	tcpci_emul_set_reg(tcpci_emul, TCPC_REG_PRODUCT_ID, product);
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_PRODUCT_ID, product);
 
 	/* Test fail on product id mismatch on live device */
 	zassert_equal(EC_ERROR_UNKNOWN,
@@ -609,10 +619,10 @@ ZTEST(ps8815, test_ps8815_get_chip_info)
 /** Test PS8805 get chip info and indirectly ps8805_make_device_id */
 ZTEST(ps8805, test_ps8805_get_chip_info_fix_dev_id)
 {
-	const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL);
-	const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul);
-	struct i2c_emul *p0_i2c_emul =
-		ps8xxx_emul_get_i2c_emul(ps8xxx_emul, PS8XXX_EMUL_PORT_0);
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *p0_i2c_common_data =
+		ps8xxx_emul_get_i2c_common_data(ps8xxx_emul,
+						PS8XXX_EMUL_PORT_0);
 	struct ec_response_pd_chip_info_v1 info;
 	uint16_t vendor, product, device_id, fw_rev;
 	uint16_t chip_rev;
@@ -638,26 +648,26 @@ ZTEST(ps8805, test_ps8805_get_chip_info_fix_dev_id)
 	product = PS8805_PRODUCT_ID;
 	/* Arbitrary revision */
 	fw_rev = 0x32;
-	tcpci_emul_set_reg(tcpci_emul, TCPC_REG_VENDOR_ID, vendor);
-	tcpci_emul_set_reg(tcpci_emul, TCPC_REG_PRODUCT_ID, product);
-	tcpci_emul_set_reg(tcpci_emul, PS8XXX_REG_FW_REV, fw_rev);
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_VENDOR_ID, vendor);
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_PRODUCT_ID, product);
+	tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, fw_rev);
 
 	/* Set correct power status for this test */
-	tcpci_emul_set_reg(tcpci_emul, TCPC_REG_POWER_STATUS, 0x0);
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_POWER_STATUS, 0x0);
 	/* Init to allow access to "hidden" I2C ports */
 	zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.init(USBC_PORT_C1), NULL);
 
 	/* Set device id which requires fixing */
 	device_id = 0x1;
-	tcpci_emul_set_reg(tcpci_emul, TCPC_REG_BCD_DEV, device_id);
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_BCD_DEV, device_id);
 
 	/* Test error on fixing device id because of fail chip revision read */
-	i2c_common_emul_set_read_fail_reg(p0_i2c_emul,
+	i2c_common_emul_set_read_fail_reg(p0_i2c_common_data,
 					  PS8805_P0_REG_CHIP_REVISION);
 	zassert_equal(EC_ERROR_INVAL,
 		      ps8xxx_tcpm_drv.get_chip_info(USBC_PORT_C1, 1, &info),
 		      NULL);
-	i2c_common_emul_set_read_fail_reg(p0_i2c_emul,
+	i2c_common_emul_set_read_fail_reg(p0_i2c_common_data,
 					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Set wrong chip revision */
@@ -674,37 +684,39 @@ ZTEST(ps8805, test_ps8805_get_chip_info_fix_dev_id)
 		ps8xxx_emul_set_chip_rev(ps8xxx_emul, test_param[i].chip_rev);
 
 		/* Test correct device id after fixing */
-		zassert_equal(EC_SUCCESS,
-			      ps8xxx_tcpm_drv.get_chip_info(USBC_PORT_C1, 1,
-							    &info),
-			      "Failed to get chip info in test case %d (chip_rev 0x%x)",
-			      i, test_param[i].chip_rev);
-		zassert_equal(vendor, info.vendor_id,
-			      "0x%x != (vendor = 0x%x) in test case %d (chip_rev 0x%x)",
-			      vendor, info.vendor_id,
-			      i, test_param[i].chip_rev);
-		zassert_equal(product, info.product_id,
-			      "0x%x != (product = 0x%x) in test case %d (chip_rev 0x%x)",
-			      product, info.product_id,
-			      i, test_param[i].chip_rev);
-		zassert_equal(test_param[i].exp_dev_id, info.device_id,
-			      "0x%x != (device = 0x%x) in test case %d (chip_rev 0x%x)",
-			      test_param[i].exp_dev_id, info.device_id,
-			      i, test_param[i].chip_rev);
-		zassert_equal(fw_rev, info.fw_version_number,
-			      "0x%x != (FW rev = 0x%x) in test case %d (chip_rev 0x%x)",
-			      fw_rev, info.fw_version_number,
-			      i, test_param[i].chip_rev);
+		zassert_equal(
+			EC_SUCCESS,
+			ps8xxx_tcpm_drv.get_chip_info(USBC_PORT_C1, 1, &info),
+			"Failed to get chip info in test case %d (chip_rev 0x%x)",
+			i, test_param[i].chip_rev);
+		zassert_equal(
+			vendor, info.vendor_id,
+			"0x%x != (vendor = 0x%x) in test case %d (chip_rev 0x%x)",
+			vendor, info.vendor_id, i, test_param[i].chip_rev);
+		zassert_equal(
+			product, info.product_id,
+			"0x%x != (product = 0x%x) in test case %d (chip_rev 0x%x)",
+			product, info.product_id, i, test_param[i].chip_rev);
+		zassert_equal(
+			test_param[i].exp_dev_id, info.device_id,
+			"0x%x != (device = 0x%x) in test case %d (chip_rev 0x%x)",
+			test_param[i].exp_dev_id, info.device_id, i,
+			test_param[i].chip_rev);
+		zassert_equal(
+			fw_rev, info.fw_version_number,
+			"0x%x != (FW rev = 0x%x) in test case %d (chip_rev 0x%x)",
+			fw_rev, info.fw_version_number, i,
+			test_param[i].chip_rev);
 	}
 }
 
 /** Test PS8815 get chip info and indirectly ps8815_make_device_id */
 ZTEST(ps8815, test_ps8815_get_chip_info_fix_dev_id)
 {
-	const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL);
-	const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul);
-	struct i2c_emul *p1_i2c_emul =
-		ps8xxx_emul_get_i2c_emul(ps8xxx_emul, PS8XXX_EMUL_PORT_1);
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *p1_i2c_common_data =
+		ps8xxx_emul_get_i2c_common_data(ps8xxx_emul,
+						PS8XXX_EMUL_PORT_1);
 	struct ec_response_pd_chip_info_v1 info;
 	uint16_t vendor, product, device_id, fw_rev;
 	uint16_t hw_rev;
@@ -735,21 +747,21 @@ ZTEST(ps8815, test_ps8815_get_chip_info_fix_dev_id)
 	product = PS8815_PRODUCT_ID;
 	/* Arbitrary revision */
 	fw_rev = 0x32;
-	tcpci_emul_set_reg(tcpci_emul, TCPC_REG_VENDOR_ID, vendor);
-	tcpci_emul_set_reg(tcpci_emul, TCPC_REG_PRODUCT_ID, product);
-	tcpci_emul_set_reg(tcpci_emul, PS8XXX_REG_FW_REV, fw_rev);
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_VENDOR_ID, vendor);
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_PRODUCT_ID, product);
+	tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, fw_rev);
 
 	/* Set device id which requires fixing */
 	device_id = 0x1;
-	tcpci_emul_set_reg(tcpci_emul, TCPC_REG_BCD_DEV, device_id);
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_BCD_DEV, device_id);
 
 	/* Test error on fixing device id because of fail hw revision read */
-	i2c_common_emul_set_read_fail_reg(p1_i2c_emul,
+	i2c_common_emul_set_read_fail_reg(p1_i2c_common_data,
 					  PS8815_P1_REG_HW_REVISION);
 	zassert_equal(EC_ERROR_INVAL,
 		      ps8xxx_tcpm_drv.get_chip_info(USBC_PORT_C1, 1, &info),
 		      NULL);
-	i2c_common_emul_set_read_fail_reg(p1_i2c_emul,
+	i2c_common_emul_set_read_fail_reg(p1_i2c_common_data,
 					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Set wrong hw revision */
@@ -766,36 +778,39 @@ ZTEST(ps8815, test_ps8815_get_chip_info_fix_dev_id)
 		ps8xxx_emul_set_hw_rev(ps8xxx_emul, test_param[i].hw_rev);
 
 		/* Test correct device id after fixing */
-		zassert_equal(EC_SUCCESS,
-			      ps8xxx_tcpm_drv.get_chip_info(USBC_PORT_C1, 1,
-							    &info),
-			      "Failed to get chip info in test case %d (hw_rev 0x%x)",
-			      i, test_param[i].hw_rev);
-		zassert_equal(vendor, info.vendor_id,
-			      "0x%x != (vendor = 0x%x) in test case %d (hw_rev 0x%x)",
-			      vendor, info.vendor_id, i, test_param[i].hw_rev);
-		zassert_equal(product, info.product_id,
-			      "0x%x != (product = 0x%x) in test case %d (hw_rev 0x%x)",
-			      product, info.product_id,
-			      i, test_param[i].hw_rev);
-		zassert_equal(test_param[i].exp_dev_id, info.device_id,
-			      "0x%x != (device = 0x%x) in test case %d (hw_rev 0x%x)",
-			      test_param[i].exp_dev_id, info.device_id,
-			      i, test_param[i].hw_rev);
-		zassert_equal(fw_rev, info.fw_version_number,
-			      "0x%x != (FW rev = 0x%x) in test case %d (hw_rev 0x%x)",
-			      fw_rev, info.fw_version_number,
-			      i, test_param[i].hw_rev);
+		zassert_equal(
+			EC_SUCCESS,
+			ps8xxx_tcpm_drv.get_chip_info(USBC_PORT_C1, 1, &info),
+			"Failed to get chip info in test case %d (hw_rev 0x%x)",
+			i, test_param[i].hw_rev);
+		zassert_equal(
+			vendor, info.vendor_id,
+			"0x%x != (vendor = 0x%x) in test case %d (hw_rev 0x%x)",
+			vendor, info.vendor_id, i, test_param[i].hw_rev);
+		zassert_equal(
+			product, info.product_id,
+			"0x%x != (product = 0x%x) in test case %d (hw_rev 0x%x)",
+			product, info.product_id, i, test_param[i].hw_rev);
+		zassert_equal(
+			test_param[i].exp_dev_id, info.device_id,
+			"0x%x != (device = 0x%x) in test case %d (hw_rev 0x%x)",
+			test_param[i].exp_dev_id, info.device_id, i,
+			test_param[i].hw_rev);
+		zassert_equal(
+			fw_rev, info.fw_version_number,
+			"0x%x != (FW rev = 0x%x) in test case %d (hw_rev 0x%x)",
+			fw_rev, info.fw_version_number, i,
+			test_param[i].hw_rev);
 	}
 }
 
 /** Test PS8805 get/set gpio */
 ZTEST(ps8805, test_ps8805_gpio)
 {
-	const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL);
-	const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul);
-	struct i2c_emul *gpio_i2c_emul =
-		ps8xxx_emul_get_i2c_emul(ps8xxx_emul, PS8XXX_EMUL_PORT_GPIO);
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *gpio_i2c_common_data =
+		ps8xxx_emul_get_i2c_common_data(ps8xxx_emul,
+						PS8XXX_EMUL_PORT_GPIO);
 	uint8_t exp_ctrl, gpio_ctrl;
 	int level;
 
@@ -851,9 +866,9 @@ ZTEST(ps8805, test_ps8805_gpio)
 	};
 
 	/* Set arbitrary FW reg value != 0 for this test */
-	tcpci_emul_set_reg(tcpci_emul, PS8XXX_REG_FW_REV, 0x31);
+	tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, 0x31);
 	/* Set correct power status for this test */
-	tcpci_emul_set_reg(tcpci_emul, TCPC_REG_POWER_STATUS, 0x0);
+	tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_POWER_STATUS, 0x0);
 	/* Init to allow access to "hidden" I2C ports */
 	zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.init(USBC_PORT_C1), NULL);
 
@@ -863,10 +878,11 @@ ZTEST(ps8805, test_ps8805_gpio)
 		      NULL);
 	zassert_equal(EC_ERROR_INVAL,
 		      ps8805_gpio_get_level(USBC_PORT_C1, PS8805_GPIO_NUM,
-					    &level), NULL);
+					    &level),
+		      NULL);
 
 	/* Setup fail on gpio control reg read */
-	i2c_common_emul_set_read_fail_reg(gpio_i2c_emul,
+	i2c_common_emul_set_read_fail_reg(gpio_i2c_common_data,
 					  PS8805_REG_GPIO_CONTROL);
 
 	/* Test fail on reading gpio control reg */
@@ -875,19 +891,20 @@ ZTEST(ps8805, test_ps8805_gpio)
 		      NULL);
 	zassert_equal(EC_ERROR_INVAL,
 		      ps8805_gpio_get_level(USBC_PORT_C1, PS8805_GPIO_0,
-					    &level), NULL);
+					    &level),
+		      NULL);
 
 	/* Do not fail on gpio control reg read */
-	i2c_common_emul_set_read_fail_reg(gpio_i2c_emul,
+	i2c_common_emul_set_read_fail_reg(gpio_i2c_common_data,
 					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test fail on writing gpio control reg */
-	i2c_common_emul_set_write_fail_reg(gpio_i2c_emul,
+	i2c_common_emul_set_write_fail_reg(gpio_i2c_common_data,
 					   PS8805_REG_GPIO_CONTROL);
 	zassert_equal(EC_ERROR_INVAL,
 		      ps8805_gpio_set_level(USBC_PORT_C1, PS8805_GPIO_0, 1),
 		      NULL);
-	i2c_common_emul_set_write_fail_reg(gpio_i2c_emul,
+	i2c_common_emul_set_write_fail_reg(gpio_i2c_common_data,
 					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Clear gpio control reg */
@@ -901,37 +918,41 @@ ZTEST(ps8805, test_ps8805_gpio)
 		} else {
 			exp_ctrl &= ~test_param[i].gpio_reg;
 		}
-		zassert_equal(EC_SUCCESS,
-			      ps8805_gpio_set_level(USBC_PORT_C1,
-						    test_param[i].signal,
-						    test_param[i].level),
-			      "Failed gpio_set in test case %d (gpio %d, level %d)",
-			      i, test_param[i].signal, test_param[i].level);
-		zassert_equal(EC_SUCCESS,
-			      ps8805_gpio_get_level(USBC_PORT_C1,
-						    test_param[i].signal,
-						    &level),
-			      "Failed gpio_get in test case %d (gpio %d, level %d)",
-			      i, test_param[i].signal, test_param[i].level);
-		zassert_equal(test_param[i].level, level,
-			      "%d != (gpio_get_level = %d) in test case %d (gpio %d, level %d)",
-			      test_param[i].level, level, i,
-			      test_param[i].signal, test_param[i].level);
+		zassert_equal(
+			EC_SUCCESS,
+			ps8805_gpio_set_level(USBC_PORT_C1,
+					      test_param[i].signal,
+					      test_param[i].level),
+			"Failed gpio_set in test case %d (gpio %d, level %d)",
+			i, test_param[i].signal, test_param[i].level);
+		zassert_equal(
+			EC_SUCCESS,
+			ps8805_gpio_get_level(USBC_PORT_C1,
+					      test_param[i].signal, &level),
+			"Failed gpio_get in test case %d (gpio %d, level %d)",
+			i, test_param[i].signal, test_param[i].level);
+		zassert_equal(
+			test_param[i].level, level,
+			"%d != (gpio_get_level = %d) in test case %d (gpio %d, level %d)",
+			test_param[i].level, level, i, test_param[i].signal,
+			test_param[i].level);
 		gpio_ctrl = ps8xxx_emul_get_gpio_ctrl(ps8xxx_emul);
-		zassert_equal(exp_ctrl, gpio_ctrl,
-			      "0x%x != (gpio_ctrl = 0x%x) in test case %d (gpio %d, level %d)",
-			      exp_ctrl, gpio_ctrl, i, test_param[i].signal,
-			      test_param[i].level);
+		zassert_equal(
+			exp_ctrl, gpio_ctrl,
+			"0x%x != (gpio_ctrl = 0x%x) in test case %d (gpio %d, level %d)",
+			exp_ctrl, gpio_ctrl, i, test_param[i].signal,
+			test_param[i].level);
 	}
 }
 
 /** Test TCPCI init and vbus level */
 static void test_ps8xxx_tcpci_init(void)
 {
-	const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL);
-	const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul);
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(ps8xxx_emul);
 
-	test_tcpci_init(tcpci_emul, USBC_PORT_C1);
+	test_tcpci_init(ps8xxx_emul, common_data, USBC_PORT_C1);
 }
 
 ZTEST(ps8805, test_tcpci_init)
@@ -947,10 +968,11 @@ ZTEST(ps8815, test_tcpci_init)
 /** Test TCPCI release */
 static void test_ps8xxx_tcpci_release(void)
 {
-	const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL);
-	const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul);
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(ps8xxx_emul);
 
-	test_tcpci_release(tcpci_emul, USBC_PORT_C1);
+	test_tcpci_release(ps8xxx_emul, common_data, USBC_PORT_C1);
 }
 
 ZTEST(ps8805, test_tcpci_release)
@@ -966,10 +988,11 @@ ZTEST(ps8815, test_tcpci_release)
 /** Test TCPCI get cc */
 static void test_ps8xxx_tcpci_get_cc(void)
 {
-	const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL);
-	const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul);
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(ps8xxx_emul);
 
-	test_tcpci_get_cc(tcpci_emul, USBC_PORT_C1);
+	test_tcpci_get_cc(ps8xxx_emul, common_data, USBC_PORT_C1);
 }
 
 ZTEST(ps8805, test_tcpci_get_cc)
@@ -985,10 +1008,11 @@ ZTEST(ps8815, test_tcpci_get_cc)
 /** Test TCPCI set cc */
 static void test_ps8xxx_tcpci_set_cc(void)
 {
-	const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL);
-	const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul);
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(ps8xxx_emul);
 
-	test_tcpci_set_cc(tcpci_emul, USBC_PORT_C1);
+	test_tcpci_set_cc(ps8xxx_emul, common_data, USBC_PORT_C1);
 }
 
 ZTEST(ps8805, test_tcpci_set_cc)
@@ -1004,10 +1028,11 @@ ZTEST(ps8815, test_tcpci_set_cc)
 /** Test TCPCI set polarity */
 static void test_ps8xxx_tcpci_set_polarity(void)
 {
-	const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL);
-	const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul);
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(ps8xxx_emul);
 
-	test_tcpci_set_polarity(tcpci_emul, USBC_PORT_C1);
+	test_tcpci_set_polarity(ps8xxx_emul, common_data, USBC_PORT_C1);
 }
 
 ZTEST(ps8805, test_tcpci_set_polarity)
@@ -1023,10 +1048,11 @@ ZTEST(ps8815, test_tcpci_set_polarity)
 /** Test TCPCI set vconn */
 static void test_ps8xxx_tcpci_set_vconn(void)
 {
-	const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL);
-	const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul);
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(ps8xxx_emul);
 
-	test_tcpci_set_vconn(tcpci_emul, USBC_PORT_C1);
+	test_tcpci_set_vconn(ps8xxx_emul, common_data, USBC_PORT_C1);
 }
 
 ZTEST(ps8805, test_tcpci_set_vconn)
@@ -1042,10 +1068,11 @@ ZTEST(ps8815, test_tcpci_set_vconn)
 /** Test TCPCI set msg header */
 static void test_ps8xxx_tcpci_set_msg_header(void)
 {
-	const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL);
-	const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul);
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(ps8xxx_emul);
 
-	test_tcpci_set_msg_header(tcpci_emul, USBC_PORT_C1);
+	test_tcpci_set_msg_header(ps8xxx_emul, common_data, USBC_PORT_C1);
 }
 
 ZTEST(ps8805, test_tcpci_set_msg_header)
@@ -1061,10 +1088,11 @@ ZTEST(ps8815, test_tcpci_set_msg_header)
 /** Test TCPCI get raw message */
 static void test_ps8xxx_tcpci_get_rx_message_raw(void)
 {
-	const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL);
-	const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul);
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(ps8xxx_emul);
 
-	test_tcpci_get_rx_message_raw(tcpci_emul, USBC_PORT_C1);
+	test_tcpci_get_rx_message_raw(ps8xxx_emul, common_data, USBC_PORT_C1);
 }
 
 ZTEST(ps8805, test_tcpci_get_rx_message_raw)
@@ -1080,10 +1108,11 @@ ZTEST(ps8815, test_tcpci_get_rx_message_raw)
 /** Test TCPCI transmitting message */
 static void test_ps8xxx_tcpci_transmit(void)
 {
-	const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL);
-	const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul);
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(ps8xxx_emul);
 
-	test_tcpci_transmit(tcpci_emul, USBC_PORT_C1);
+	test_tcpci_transmit(ps8xxx_emul, common_data, USBC_PORT_C1);
 }
 
 ZTEST(ps8805, test_tcpci_transmit)
@@ -1099,10 +1128,11 @@ ZTEST(ps8815, test_tcpci_transmit)
 /** Test TCPCI alert */
 static void test_ps8xxx_tcpci_alert(void)
 {
-	const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL);
-	const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul);
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(ps8xxx_emul);
 
-	test_tcpci_alert(tcpci_emul, USBC_PORT_C1);
+	test_tcpci_alert(ps8xxx_emul, common_data, USBC_PORT_C1);
 }
 
 ZTEST(ps8805, test_tcpci_alert)
@@ -1118,10 +1148,11 @@ ZTEST(ps8815, test_tcpci_alert)
 /** Test TCPCI alert RX message */
 static void test_ps8xxx_tcpci_alert_rx_message(void)
 {
-	const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL);
-	const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul);
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(ps8xxx_emul);
 
-	test_tcpci_alert_rx_message(tcpci_emul, USBC_PORT_C1);
+	test_tcpci_alert_rx_message(ps8xxx_emul, common_data, USBC_PORT_C1);
 }
 
 ZTEST(ps8805, test_tcpci_alert_rx_message)
@@ -1137,17 +1168,18 @@ ZTEST(ps8815, test_tcpci_alert_rx_message)
 /** Test TCPCI enter low power mode */
 static void test_ps8xxx_tcpci_low_power_mode(void)
 {
-	const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL);
-	const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul);
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(ps8xxx_emul);
 	/*
 	 * PS8751/PS8815 has the auto sleep function that enters
 	 * low power mode on its own in ~2 seconds. Other chips
 	 * don't have it. Stub it out for PS8751/PS8815.
 	 */
 	if (board_get_ps8xxx_product_id(USBC_PORT_C1) == PS8751_PRODUCT_ID ||
-		board_get_ps8xxx_product_id(USBC_PORT_C1) == PS8815_PRODUCT_ID)
+	    board_get_ps8xxx_product_id(USBC_PORT_C1) == PS8815_PRODUCT_ID)
 		return;
-	test_tcpci_low_power_mode(tcpci_emul, USBC_PORT_C1);
+	test_tcpci_low_power_mode(ps8xxx_emul, common_data, USBC_PORT_C1);
 }
 
 ZTEST(ps8805, test_tcpci_low_power_mode)
@@ -1163,10 +1195,11 @@ ZTEST(ps8815, test_tcpci_low_power_mode)
 /** Test TCPCI set bist test mode */
 static void test_ps8xxx_tcpci_set_bist_mode(void)
 {
-	const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL);
-	const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul);
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(ps8xxx_emul);
 
-	test_tcpci_set_bist_mode(tcpci_emul, USBC_PORT_C1);
+	test_tcpci_set_bist_mode(ps8xxx_emul, common_data, USBC_PORT_C1);
 }
 
 ZTEST(ps8805, test_tcpci_set_bist_mode)
@@ -1182,39 +1215,43 @@ ZTEST(ps8815, test_tcpci_set_bist_mode)
 /* Setup no fail for all I2C devices associated with PS8xxx emulator */
 static void setup_no_fail_all(void)
 {
-	const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL);
-	const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul);
-	struct i2c_emul *tcpci_i2c_emul = tcpci_emul_get_i2c_emul(tcpci_emul);
-	struct i2c_emul *p0_i2c_emul =
-		ps8xxx_emul_get_i2c_emul(ps8xxx_emul, PS8XXX_EMUL_PORT_0);
-	struct i2c_emul *p1_i2c_emul =
-		ps8xxx_emul_get_i2c_emul(ps8xxx_emul, PS8XXX_EMUL_PORT_1);
-	struct i2c_emul *gpio_i2c_emul =
-		ps8xxx_emul_get_i2c_emul(ps8xxx_emul, PS8XXX_EMUL_PORT_GPIO);
-
-	i2c_common_emul_set_read_fail_reg(tcpci_i2c_emul,
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(ps8xxx_emul);
+
+	struct i2c_common_emul_data *p0_i2c_common_data =
+		ps8xxx_emul_get_i2c_common_data(ps8xxx_emul,
+						PS8XXX_EMUL_PORT_0);
+	struct i2c_common_emul_data *p1_i2c_common_data =
+		ps8xxx_emul_get_i2c_common_data(ps8xxx_emul,
+						PS8XXX_EMUL_PORT_1);
+	struct i2c_common_emul_data *gpio_i2c_common_data =
+		ps8xxx_emul_get_i2c_common_data(ps8xxx_emul,
+						PS8XXX_EMUL_PORT_GPIO);
+
+	i2c_common_emul_set_read_fail_reg(common_data,
 					  I2C_COMMON_EMUL_NO_FAIL_REG);
-	i2c_common_emul_set_write_fail_reg(tcpci_i2c_emul,
+	i2c_common_emul_set_write_fail_reg(common_data,
 					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
-	if (p0_i2c_emul != NULL) {
-		i2c_common_emul_set_read_fail_reg(p0_i2c_emul,
+	if (p0_i2c_common_data != NULL) {
+		i2c_common_emul_set_read_fail_reg(p0_i2c_common_data,
 						  I2C_COMMON_EMUL_NO_FAIL_REG);
-		i2c_common_emul_set_write_fail_reg(p0_i2c_emul,
+		i2c_common_emul_set_write_fail_reg(p0_i2c_common_data,
 						   I2C_COMMON_EMUL_NO_FAIL_REG);
 	}
 
-	if (p1_i2c_emul != NULL) {
-		i2c_common_emul_set_read_fail_reg(p1_i2c_emul,
+	if (p1_i2c_common_data != NULL) {
+		i2c_common_emul_set_read_fail_reg(p1_i2c_common_data,
 						  I2C_COMMON_EMUL_NO_FAIL_REG);
-		i2c_common_emul_set_write_fail_reg(p1_i2c_emul,
+		i2c_common_emul_set_write_fail_reg(p1_i2c_common_data,
 						   I2C_COMMON_EMUL_NO_FAIL_REG);
 	}
 
-	if (gpio_i2c_emul != NULL) {
-		i2c_common_emul_set_read_fail_reg(gpio_i2c_emul,
+	if (gpio_i2c_common_data != NULL) {
+		i2c_common_emul_set_read_fail_reg(gpio_i2c_common_data,
 						  I2C_COMMON_EMUL_NO_FAIL_REG);
-		i2c_common_emul_set_write_fail_reg(gpio_i2c_emul,
+		i2c_common_emul_set_write_fail_reg(gpio_i2c_common_data,
 						   I2C_COMMON_EMUL_NO_FAIL_REG);
 	}
 }
@@ -1225,12 +1262,22 @@ static void setup_no_fail_all(void)
  */
 static void ps8805_before(void *state)
 {
-	const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL);
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
 	ARG_UNUSED(state);
 
 	board_set_ps8xxx_product_id(PS8805_PRODUCT_ID);
 	ps8xxx_emul_set_product_id(ps8xxx_emul, PS8805_PRODUCT_ID);
 	setup_no_fail_all();
+	zassume_equal(EC_SUCCESS, ps8xxx_tcpm_drv.init(USBC_PORT_C1), NULL);
+}
+
+static void ps8805_after(void *state)
+{
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	ARG_UNUSED(state);
+
+	/* Set correct firmware revision */
+	tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, 0x31);
 }
 
 /**
@@ -1239,17 +1286,26 @@ static void ps8805_before(void *state)
  */
 static void ps8815_before(void *state)
 {
-	const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL);
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
 	ARG_UNUSED(state);
 
 	board_set_ps8xxx_product_id(PS8815_PRODUCT_ID);
 	ps8xxx_emul_set_product_id(ps8xxx_emul, PS8815_PRODUCT_ID);
 	setup_no_fail_all();
+	zassume_equal(EC_SUCCESS, ps8xxx_tcpm_drv.init(USBC_PORT_C1), NULL);
 }
 
+static void ps8815_after(void *state)
+{
+	const struct emul *ps8xxx_emul = EMUL_DT_GET(PS8XXX_EMUL_NODE);
+	ARG_UNUSED(state);
+
+	/* Set correct firmware revision */
+	tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, 0x31);
+}
 
-ZTEST_SUITE(ps8805, drivers_predicate_post_main, NULL, ps8805_before, NULL,
-	    NULL);
+ZTEST_SUITE(ps8805, drivers_predicate_pre_main, NULL, ps8805_before,
+	    ps8805_after, NULL);
 
-ZTEST_SUITE(ps8815, drivers_predicate_post_main, NULL, ps8815_before, NULL,
-	    NULL);
+ZTEST_SUITE(ps8815, drivers_predicate_pre_main, NULL, ps8815_before,
+	    ps8815_after, NULL);
diff --git a/zephyr/test/drivers/src/smart.c b/zephyr/test/drivers/default/src/smart.c
index 3628a68d3e..96200f1b91 100644
--- a/zephyr/test/drivers/src/smart.c
+++ b/zephyr/test/drivers/default/src/smart.c
@@ -1,10 +1,10 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <zephyr/zephyr.h>
-#include <ztest.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
 #include <zephyr/shell/shell.h>
 #include <zephyr/shell/shell_uart.h>
 
@@ -18,18 +18,17 @@
 #include "battery_smart.h"
 #include "test/drivers/test_state.h"
 
-#define BATTERY_ORD	DT_DEP_ORD(DT_NODELABEL(battery))
+#define BATTERY_NODE DT_NODELABEL(battery)
 
 /** Test all simple getters */
 ZTEST_USER(smart_battery, test_battery_getters)
 {
 	struct sbat_emul_bat_data *bat;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BATTERY_NODE);
 	char block[32];
 	int expected;
 	int word;
 
-	emul = sbat_emul_get_ptr(BATTERY_ORD);
 	bat = sbat_emul_get_bat_data(emul);
 
 	zassert_equal(EC_SUCCESS, battery_get_mode(&word), NULL);
@@ -40,22 +39,22 @@ ZTEST_USER(smart_battery, test_battery_getters)
 	zassert_equal(expected, word, "%d != %d", expected, word);
 
 	zassert_equal(EC_SUCCESS, battery_cycle_count(&word), NULL);
-	zassert_equal(bat->cycle_count, word, "%d != %d",
-		      bat->cycle_count, word);
+	zassert_equal(bat->cycle_count, word, "%d != %d", bat->cycle_count,
+		      word);
 	zassert_equal(EC_SUCCESS, battery_design_voltage(&word), NULL);
 	zassert_equal(bat->design_mv, word, "%d != %d", bat->design_mv, word);
 	zassert_equal(EC_SUCCESS, battery_serial_number(&word), NULL);
 	zassert_equal(bat->sn, word, "%d != %d", bat->sn, word);
 	zassert_equal(EC_SUCCESS, get_battery_manufacturer_name(block, 32),
 		      NULL);
-	zassert_mem_equal(block, bat->mf_name, bat->mf_name_len,
-			  "%s != %s", block, bat->mf_name);
+	zassert_mem_equal(block, bat->mf_name, bat->mf_name_len, "%s != %s",
+			  block, bat->mf_name);
 	zassert_equal(EC_SUCCESS, battery_device_name(block, 32), NULL);
-	zassert_mem_equal(block, bat->dev_name, bat->dev_name_len,
-			  "%s != %s", block, bat->dev_name);
+	zassert_mem_equal(block, bat->dev_name, bat->dev_name_len, "%s != %s",
+			  block, bat->dev_name);
 	zassert_equal(EC_SUCCESS, battery_device_chemistry(block, 32), NULL);
-	zassert_mem_equal(block, bat->dev_chem, bat->dev_chem_len,
-			  "%s != %s", block, bat->dev_chem);
+	zassert_mem_equal(block, bat->dev_chem, bat->dev_chem_len, "%s != %s",
+			  block, bat->dev_chem);
 	word = battery_get_avg_current();
 	zassert_equal(bat->avg_cur, word, "%d != %d", bat->avg_cur, word);
 	word = battery_get_avg_voltage();
@@ -81,19 +80,21 @@ ZTEST_USER(smart_battery, test_battery_getters)
 ZTEST_USER(smart_battery, test_battery_get_capacity)
 {
 	struct sbat_emul_bat_data *bat;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BATTERY_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_smart_battery_get_i2c_common_data(emul);
 	int word;
 
-	emul = sbat_emul_get_ptr(BATTERY_ORD);
 	bat = sbat_emul_get_bat_data(emul);
 
 	/* Test fail when checking battery mode */
-	i2c_common_emul_set_read_fail_reg(emul, SB_BATTERY_MODE);
+	i2c_common_emul_set_read_fail_reg(common_data, SB_BATTERY_MODE);
 	zassert_equal(EC_ERROR_INVAL, battery_remaining_capacity(&word), NULL);
 	zassert_equal(EC_ERROR_INVAL, battery_full_charge_capacity(&word),
 		      NULL);
 	zassert_equal(EC_ERROR_INVAL, battery_design_capacity(&word), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test getting remaining capacity and if mAh mode is forced */
 	bat->mode |= MODE_CAPACITY;
@@ -114,16 +115,14 @@ ZTEST_USER(smart_battery, test_battery_get_capacity)
 	zassert_false(bat->mode & MODE_CAPACITY, "mAh mode not forced");
 }
 
-
 /** Test battery status */
 ZTEST_USER(smart_battery, test_battery_status)
 {
 	struct sbat_emul_bat_data *bat;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BATTERY_NODE);
 	int expected;
 	int status;
 
-	emul = sbat_emul_get_ptr(BATTERY_ORD);
 	bat = sbat_emul_get_bat_data(emul);
 
 	bat->status = 0;
@@ -144,16 +143,18 @@ ZTEST_USER(smart_battery, test_battery_status)
 /** Test wait for stable function */
 ZTEST_USER(smart_battery, test_battery_wait_for_stable)
 {
-	struct i2c_emul *emul;
-
-	emul = sbat_emul_get_ptr(BATTERY_ORD);
+	const struct emul *emul = EMUL_DT_GET(BATTERY_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_smart_battery_get_i2c_common_data(emul);
 
 	/* Should fail when read function always fail */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_FAIL_ALL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_FAIL_ALL_REG);
 	zassert_equal(EC_ERROR_NOT_POWERED, battery_wait_for_stable(), NULL);
 
 	/* Should be ok with default handler */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 	zassert_equal(EC_SUCCESS, battery_wait_for_stable(), NULL);
 }
 
@@ -161,14 +162,13 @@ ZTEST_USER(smart_battery, test_battery_wait_for_stable)
 ZTEST_USER(smart_battery, test_battery_manufacture_date)
 {
 	struct sbat_emul_bat_data *bat;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BATTERY_NODE);
 	int day, month, year;
 	int exp_month = 5;
 	int exp_year = 2018;
 	int exp_day = 19;
 	uint16_t date;
 
-	emul = sbat_emul_get_ptr(BATTERY_ORD);
 	bat = sbat_emul_get_bat_data(emul);
 
 	date = sbat_emul_date_to_word(exp_day, exp_month, exp_year);
@@ -185,12 +185,13 @@ ZTEST_USER(smart_battery, test_battery_manufacture_date)
 ZTEST_USER(smart_battery, test_battery_time_at_rate)
 {
 	struct sbat_emul_bat_data *bat;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BATTERY_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_smart_battery_get_i2c_common_data(emul);
 	int expect_time;
 	int minutes;
 	int rate;
 
-	emul = sbat_emul_get_ptr(BATTERY_ORD);
 	bat = sbat_emul_get_bat_data(emul);
 
 	/* Test fail on rate 0 */
@@ -203,16 +204,18 @@ ZTEST_USER(smart_battery, test_battery_time_at_rate)
 	rate = -6000;
 
 	/* Test fail on writing at rate register */
-	i2c_common_emul_set_write_fail_reg(emul, SB_AT_RATE);
+	i2c_common_emul_set_write_fail_reg(common_data, SB_AT_RATE);
 	zassert_equal(EC_ERROR_INVAL, battery_time_at_rate(rate, &minutes),
 		      NULL);
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test fail on reading at rate ok register */
-	i2c_common_emul_set_read_fail_reg(emul, SB_AT_RATE_OK);
+	i2c_common_emul_set_read_fail_reg(common_data, SB_AT_RATE_OK);
 	zassert_equal(EC_ERROR_INVAL, battery_time_at_rate(rate, &minutes),
 		      NULL);
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/*
 	 * Expected discharging rate is less then 10s,
@@ -244,87 +247,91 @@ ZTEST_USER(smart_battery, test_battery_get_params)
 {
 	struct sbat_emul_bat_data *bat;
 	struct batt_params batt;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BATTERY_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_smart_battery_get_i2c_common_data(emul);
 	int flags;
 
-	emul = sbat_emul_get_ptr(BATTERY_ORD);
 	bat = sbat_emul_get_bat_data(emul);
 
 	/* Fail temperature read */
-	i2c_common_emul_set_read_fail_reg(emul, SB_TEMPERATURE);
+	i2c_common_emul_set_read_fail_reg(common_data, SB_TEMPERATURE);
 	flags = BATT_FLAG_WANT_CHARGE | BATT_FLAG_RESPONSIVE |
 		BATT_FLAG_BAD_TEMPERATURE;
 	battery_get_params(&batt);
 	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
 
 	/* Fail state of charge read; want charge cannot be set */
-	i2c_common_emul_set_read_fail_reg(emul, SB_RELATIVE_STATE_OF_CHARGE);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  SB_RELATIVE_STATE_OF_CHARGE);
 	flags = BATT_FLAG_RESPONSIVE | BATT_FLAG_BAD_STATE_OF_CHARGE;
 	battery_get_params(&batt);
 	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
 
 	/* Fail voltage read */
-	i2c_common_emul_set_read_fail_reg(emul, SB_VOLTAGE);
+	i2c_common_emul_set_read_fail_reg(common_data, SB_VOLTAGE);
 	flags = BATT_FLAG_WANT_CHARGE | BATT_FLAG_RESPONSIVE |
 		BATT_FLAG_BAD_VOLTAGE;
 	battery_get_params(&batt);
 	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
 
 	/* Fail current read */
-	i2c_common_emul_set_read_fail_reg(emul, SB_CURRENT);
+	i2c_common_emul_set_read_fail_reg(common_data, SB_CURRENT);
 	flags = BATT_FLAG_WANT_CHARGE | BATT_FLAG_RESPONSIVE |
 		BATT_FLAG_BAD_CURRENT;
 	battery_get_params(&batt);
 	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
 
 	/* Fail average current read */
-	i2c_common_emul_set_read_fail_reg(emul, SB_AVERAGE_CURRENT);
+	i2c_common_emul_set_read_fail_reg(common_data, SB_AVERAGE_CURRENT);
 	flags = BATT_FLAG_WANT_CHARGE | BATT_FLAG_RESPONSIVE |
 		BATT_FLAG_BAD_AVERAGE_CURRENT;
 	battery_get_params(&batt);
 	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
 
 	/* Fail charging voltage read; want charge cannot be set */
-	i2c_common_emul_set_read_fail_reg(emul, SB_CHARGING_VOLTAGE);
+	i2c_common_emul_set_read_fail_reg(common_data, SB_CHARGING_VOLTAGE);
 	flags = BATT_FLAG_RESPONSIVE | BATT_FLAG_BAD_DESIRED_VOLTAGE;
 	battery_get_params(&batt);
 	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
 
 	/* Fail charging voltage read; want charge cannot be set */
-	i2c_common_emul_set_read_fail_reg(emul, SB_CHARGING_CURRENT);
+	i2c_common_emul_set_read_fail_reg(common_data, SB_CHARGING_CURRENT);
 	flags = BATT_FLAG_RESPONSIVE | BATT_FLAG_BAD_DESIRED_CURRENT;
 	battery_get_params(&batt);
 	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
 
 	/* Fail remaining capacity read */
-	i2c_common_emul_set_read_fail_reg(emul, SB_REMAINING_CAPACITY);
+	i2c_common_emul_set_read_fail_reg(common_data, SB_REMAINING_CAPACITY);
 	flags = BATT_FLAG_WANT_CHARGE | BATT_FLAG_RESPONSIVE |
 		BATT_FLAG_BAD_REMAINING_CAPACITY;
 	battery_get_params(&batt);
 	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
 
 	/* Fail full capacity read */
-	i2c_common_emul_set_read_fail_reg(emul, SB_FULL_CHARGE_CAPACITY);
+	i2c_common_emul_set_read_fail_reg(common_data, SB_FULL_CHARGE_CAPACITY);
 	flags = BATT_FLAG_WANT_CHARGE | BATT_FLAG_RESPONSIVE |
 		BATT_FLAG_BAD_FULL_CAPACITY;
 	battery_get_params(&batt);
 	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
 
 	/* Fail status read */
-	i2c_common_emul_set_read_fail_reg(emul, SB_BATTERY_STATUS);
+	i2c_common_emul_set_read_fail_reg(common_data, SB_BATTERY_STATUS);
 	flags = BATT_FLAG_WANT_CHARGE | BATT_FLAG_RESPONSIVE |
 		BATT_FLAG_BAD_STATUS;
 	battery_get_params(&batt);
 	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
 
 	/* Fail all */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_FAIL_ALL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_FAIL_ALL_REG);
 	flags = BATT_FLAG_BAD_ANY;
 	battery_get_params(&batt);
 	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
 
 	/* Use default handler, everything should be ok */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 	flags = BATT_FLAG_WANT_CHARGE | BATT_FLAG_RESPONSIVE;
 	battery_get_params(&batt);
 	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
@@ -336,7 +343,7 @@ struct mfgacc_data {
 	int len;
 };
 
-static int mfgacc_read_func(struct i2c_emul *emul, int reg, uint8_t *val,
+static int mfgacc_read_func(const struct emul *emul, int reg, uint8_t *val,
 			    int bytes, void *data)
 {
 	struct mfgacc_data *conf = data;
@@ -353,13 +360,14 @@ ZTEST_USER(smart_battery, test_battery_mfacc)
 {
 	struct sbat_emul_bat_data *bat;
 	struct mfgacc_data mfacc_conf;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BATTERY_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_smart_battery_get_i2c_common_data(emul);
 	uint8_t recv_buf[10];
 	uint8_t mf_data[10];
 	uint16_t cmd;
 	int len;
 
-	emul = sbat_emul_get_ptr(BATTERY_ORD);
 	bat = sbat_emul_get_bat_data(emul);
 
 	/* Select arbitrary command number for the test */
@@ -369,22 +377,26 @@ ZTEST_USER(smart_battery, test_battery_mfacc)
 	len = 2;
 	zassert_equal(EC_ERROR_INVAL,
 		      sb_read_mfgacc(cmd, SB_ALT_MANUFACTURER_ACCESS, recv_buf,
-				     len), NULL);
+				     len),
+		      NULL);
 
 	/* Set correct length for rest of the test */
 	len = 10;
 
 	/* Test fail on writing SB_MANUFACTURER_ACCESS register */
-	i2c_common_emul_set_write_fail_reg(emul, SB_MANUFACTURER_ACCESS);
+	i2c_common_emul_set_write_fail_reg(common_data, SB_MANUFACTURER_ACCESS);
 	zassert_equal(EC_ERROR_INVAL,
 		      sb_read_mfgacc(cmd, SB_ALT_MANUFACTURER_ACCESS, recv_buf,
-				     len), NULL);
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+				     len),
+		      NULL);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test fail on reading manufacturer data (custom handler is not set) */
 	zassert_equal(EC_ERROR_INVAL,
 		      sb_read_mfgacc(cmd, SB_ALT_MANUFACTURER_ACCESS, recv_buf,
-				     len), NULL);
+				     len),
+		      NULL);
 
 	/* Set arbitrary manufacturer data */
 	for (int i = 1; i < len; i++) {
@@ -397,12 +409,14 @@ ZTEST_USER(smart_battery, test_battery_mfacc)
 	mfacc_conf.reg = SB_ALT_MANUFACTURER_ACCESS;
 	mfacc_conf.len = len;
 	mfacc_conf.buf = mf_data;
-	i2c_common_emul_set_read_func(emul, mfgacc_read_func, &mfacc_conf);
+	i2c_common_emul_set_read_func(common_data, mfgacc_read_func,
+				      &mfacc_conf);
 
 	/* Test error when mf_data doesn't start with command */
 	zassert_equal(EC_ERROR_UNKNOWN,
 		      sb_read_mfgacc(cmd, SB_ALT_MANUFACTURER_ACCESS, recv_buf,
-				     len), NULL);
+				     len),
+		      NULL);
 
 	/* Set beginning of the manufacturer data */
 	mf_data[1] = cmd & 0xff;
@@ -411,12 +425,13 @@ ZTEST_USER(smart_battery, test_battery_mfacc)
 	/* Test successful manufacturer data read */
 	zassert_equal(EC_SUCCESS,
 		      sb_read_mfgacc(cmd, SB_ALT_MANUFACTURER_ACCESS, recv_buf,
-				     len), NULL);
+				     len),
+		      NULL);
 	/* Compare received data ignoring length byte */
 	zassert_mem_equal(mf_data + 1, recv_buf, len - 1, NULL);
 
 	/* Disable custom read function */
-	i2c_common_emul_set_read_func(emul, NULL, NULL);
+	i2c_common_emul_set_read_func(common_data, NULL, NULL);
 }
 
 /** Test battery fake charge level set and read */
@@ -424,40 +439,36 @@ ZTEST_USER(smart_battery, test_battery_fake_charge)
 {
 	struct sbat_emul_bat_data *bat;
 	struct batt_params batt;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BATTERY_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_smart_battery_get_i2c_common_data(emul);
 	int remaining_cap;
 	int fake_charge;
 	int charge;
 	int flags;
 
-	emul = sbat_emul_get_ptr(BATTERY_ORD);
 	bat = sbat_emul_get_bat_data(emul);
 
 	/* Success on command with no argument */
-	zassert_equal(EC_SUCCESS,
-		      shell_execute_cmd(get_ec_shell(),
-					"battfake"), NULL);
+	zassert_equal(EC_SUCCESS, shell_execute_cmd(get_ec_shell(), "battfake"),
+		      NULL);
 
 	/* Fail on command with argument which is not a number */
 	zassert_equal(EC_ERROR_PARAM1,
-		      shell_execute_cmd(get_ec_shell(),
-					"battfake test"), NULL);
+		      shell_execute_cmd(get_ec_shell(), "battfake test"), NULL);
 
 	/* Fail on command with charge level above 100% */
 	zassert_equal(EC_ERROR_PARAM1,
-		      shell_execute_cmd(get_ec_shell(),
-					"battfake 123"), NULL);
+		      shell_execute_cmd(get_ec_shell(), "battfake 123"), NULL);
 
 	/* Fail on command with charge level below 0% */
 	zassert_equal(EC_ERROR_PARAM1,
-		      shell_execute_cmd(get_ec_shell(),
-					"battfake -23"), NULL);
+		      shell_execute_cmd(get_ec_shell(), "battfake -23"), NULL);
 
 	/* Set fake charge level */
 	fake_charge = 65;
 	zassert_equal(EC_SUCCESS,
-		      shell_execute_cmd(get_ec_shell(),
-					"battfake 65"), NULL);
+		      shell_execute_cmd(get_ec_shell(), "battfake 65"), NULL);
 
 	/* Test that fake charge level is applied */
 	flags = BATT_FLAG_WANT_CHARGE | BATT_FLAG_RESPONSIVE;
@@ -470,7 +481,7 @@ ZTEST_USER(smart_battery, test_battery_fake_charge)
 		      remaining_cap, batt.remaining_capacity);
 
 	/* Test fake remaining capacity when full capacity is not available */
-	i2c_common_emul_set_read_fail_reg(emul, SB_FULL_CHARGE_CAPACITY);
+	i2c_common_emul_set_read_fail_reg(common_data, SB_FULL_CHARGE_CAPACITY);
 	flags = BATT_FLAG_WANT_CHARGE | BATT_FLAG_RESPONSIVE |
 		BATT_FLAG_BAD_FULL_CAPACITY;
 	battery_get_params(&batt);
@@ -480,22 +491,22 @@ ZTEST_USER(smart_battery, test_battery_fake_charge)
 	remaining_cap = bat->design_cap * fake_charge / 100;
 	zassert_equal(remaining_cap, batt.remaining_capacity, "%d != %d",
 		      remaining_cap, batt.remaining_capacity);
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Disable fake charge level */
 	zassert_equal(EC_SUCCESS,
-		      shell_execute_cmd(get_ec_shell(),
-					"battfake -1"), NULL);
+		      shell_execute_cmd(get_ec_shell(), "battfake -1"), NULL);
 
 	/* Test that fake charge level is not applied */
 	flags = BATT_FLAG_WANT_CHARGE | BATT_FLAG_RESPONSIVE;
 	battery_get_params(&batt);
 	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
 	charge = 100 * bat->cap / bat->full_cap;
-	zassert_equal(charge, batt.state_of_charge, "%d%% != %d%%",
-		      charge, batt.state_of_charge);
-	zassert_equal(bat->cap, batt.remaining_capacity, "%d != %d",
-		      bat->cap, batt.remaining_capacity);
+	zassert_equal(charge, batt.state_of_charge, "%d%% != %d%%", charge,
+		      batt.state_of_charge);
+	zassert_equal(bat->cap, batt.remaining_capacity, "%d != %d", bat->cap,
+		      batt.remaining_capacity);
 }
 
 /** Test battery fake temperature set and read */
@@ -503,57 +514,55 @@ ZTEST_USER(smart_battery, test_battery_fake_temperature)
 {
 	struct sbat_emul_bat_data *bat;
 	struct batt_params batt;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(BATTERY_NODE);
 	int fake_temp;
 	int flags;
 
-	emul = sbat_emul_get_ptr(BATTERY_ORD);
 	bat = sbat_emul_get_bat_data(emul);
 
 	/* Success on command with no argument */
 	zassert_equal(EC_SUCCESS,
-		      shell_execute_cmd(get_ec_shell(),
-					"batttempfake"), NULL);
+		      shell_execute_cmd(get_ec_shell(), "batttempfake"), NULL);
 
 	/* Fail on command with argument which is not a number */
 	zassert_equal(EC_ERROR_PARAM1,
-		      shell_execute_cmd(get_ec_shell(),
-					"batttempfake test"), NULL);
+		      shell_execute_cmd(get_ec_shell(), "batttempfake test"),
+		      NULL);
 
 	/* Fail on command with too high temperature (above 500.0 K) */
 	zassert_equal(EC_ERROR_PARAM1,
-		      shell_execute_cmd(get_ec_shell(),
-					"batttempfake 5001"), NULL);
+		      shell_execute_cmd(get_ec_shell(), "batttempfake 5001"),
+		      NULL);
 
 	/* Fail on command with too low temperature (below 0 K) */
 	zassert_equal(EC_ERROR_PARAM1,
-		      shell_execute_cmd(get_ec_shell(),
-					"batttempfake -23"), NULL);
+		      shell_execute_cmd(get_ec_shell(), "batttempfake -23"),
+		      NULL);
 
 	/* Set fake temperature */
 	fake_temp = 2840;
 	zassert_equal(EC_SUCCESS,
-		      shell_execute_cmd(get_ec_shell(),
-					"batttempfake 2840"), NULL);
+		      shell_execute_cmd(get_ec_shell(), "batttempfake 2840"),
+		      NULL);
 
 	/* Test that fake temperature is applied */
 	flags = BATT_FLAG_WANT_CHARGE | BATT_FLAG_RESPONSIVE;
 	battery_get_params(&batt);
 	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
-	zassert_equal(fake_temp, batt.temperature, "%d != %d",
-		      fake_temp, batt.temperature);
+	zassert_equal(fake_temp, batt.temperature, "%d != %d", fake_temp,
+		      batt.temperature);
 
 	/* Disable fake temperature */
 	zassert_equal(EC_SUCCESS,
-		      shell_execute_cmd(get_ec_shell(),
-					"batttempfake -1"), NULL);
+		      shell_execute_cmd(get_ec_shell(), "batttempfake -1"),
+		      NULL);
 
 	/* Test that fake temperature is not applied */
 	flags = BATT_FLAG_WANT_CHARGE | BATT_FLAG_RESPONSIVE;
 	battery_get_params(&batt);
 	zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags);
-	zassert_equal(bat->temp, batt.temperature, "%d != %d",
-		      bat->temp, batt.temperature);
+	zassert_equal(bat->temp, batt.temperature, "%d != %d", bat->temp,
+		      batt.temperature);
 }
 
 ZTEST_SUITE(smart_battery, drivers_predicate_post_main, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/drivers/src/stm_mems_common.c b/zephyr/test/drivers/default/src/stm_mems_common.c
index fef0766c7d..f7c59105b0 100644
--- a/zephyr/test/drivers/src/stm_mems_common.c
+++ b/zephyr/test/drivers/default/src/stm_mems_common.c
@@ -1,9 +1,9 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <ztest.h>
+#include <zephyr/ztest.h>
 #include <zephyr/device.h>
 #include <zephyr/devicetree.h>
 #include <errno.h>
@@ -15,15 +15,16 @@
 #include "i2c/i2c.h"
 #include "test/drivers/test_state.h"
 
-#define MOCK_EMUL emul_get_binding(DT_LABEL(DT_NODELABEL(i2c_mock)))
+#define MOCK_EMUL EMUL_DT_GET(DT_NODELABEL(i2c_mock))
+#define COMMON_DATA emul_i2c_mock_get_i2c_common_data(MOCK_EMUL)
 
 struct mock_properties {
 	/* Incremented by the mock function every time it is called */
 	int call_count;
 };
 
-static int mock_read_fn(struct i2c_emul *emul, int reg, uint8_t *val, int bytes,
-			void *data)
+static int mock_read_fn(const struct emul *emul, int reg, uint8_t *val,
+			int bytes, void *data)
 {
 	ztest_check_expected_value(reg);
 	ztest_check_expected_value(bytes);
@@ -34,8 +35,8 @@ static int mock_read_fn(struct i2c_emul *emul, int reg, uint8_t *val, int bytes,
 	return ztest_get_return_value();
 }
 
-static int mock_write_fn(struct i2c_emul *emul, int reg, uint8_t val, int bytes,
-			 void *data)
+static int mock_write_fn(const struct emul *emul, int reg, uint8_t val,
+			 int bytes, void *data)
 {
 	struct mock_properties *props = (struct mock_properties *)data;
 
@@ -51,10 +52,10 @@ static int mock_write_fn(struct i2c_emul *emul, int reg, uint8_t val, int bytes,
 ZTEST(stm_mems_common, test_st_raw_read_n)
 {
 	const struct emul *emul = MOCK_EMUL;
-	struct i2c_emul *i2c_emul = i2c_mock_to_i2c_emul(emul);
+
 	int rv;
 
-	i2c_common_emul_set_read_func(i2c_emul, mock_read_fn, NULL);
+	i2c_common_emul_set_read_func(COMMON_DATA, mock_read_fn, NULL);
 	/*
 	 * Ensure the MSb (auto-increment bit) in the register address gets
 	 * set, but also return an error condition
@@ -72,10 +73,10 @@ ZTEST(stm_mems_common, test_st_raw_read_n)
 ZTEST(stm_mems_common, test_st_raw_read_n_noinc)
 {
 	const struct emul *emul = MOCK_EMUL;
-	struct i2c_emul *i2c_emul = i2c_mock_to_i2c_emul(emul);
+
 	int rv;
 
-	i2c_common_emul_set_read_func(i2c_emul, mock_read_fn, NULL);
+	i2c_common_emul_set_read_func(COMMON_DATA, mock_read_fn, NULL);
 	/*
 	 * Unlike `st_raw_read_n`, the MSb (auto-increment bit) in the register
 	 * address should NOT be automatically set. Also return an error.
@@ -94,7 +95,7 @@ ZTEST(stm_mems_common, test_st_raw_read_n_noinc)
 ZTEST(stm_mems_common, test_st_write_data_with_mask)
 {
 	const struct emul *emul = MOCK_EMUL;
-	struct i2c_emul *i2c_emul = i2c_mock_to_i2c_emul(emul);
+
 	int rv;
 
 	const struct motion_sensor_t sensor = {
@@ -111,7 +112,7 @@ ZTEST(stm_mems_common, test_st_write_data_with_mask)
 				     (test_data & test_mask);
 
 	/* Part 1: error occurs when reading initial value from sensor */
-	i2c_common_emul_set_read_func(i2c_emul, mock_read_fn, NULL);
+	i2c_common_emul_set_read_func(COMMON_DATA, mock_read_fn, NULL);
 	ztest_expect_value(mock_read_fn, reg, test_addr);
 	ztest_expect_value(mock_read_fn, bytes, 0);
 	/* Value is immaterial but ztest has no way to explicitly ignore it */
@@ -136,7 +137,7 @@ ZTEST(stm_mems_common, test_st_write_data_with_mask)
 		.call_count = 0,
 	};
 
-	i2c_common_emul_set_write_func(i2c_emul, mock_write_fn,
+	i2c_common_emul_set_write_func(COMMON_DATA, mock_write_fn,
 				       &write_fn_props);
 
 	rv = st_write_data_with_mask(&sensor, test_addr, test_mask, test_data);
@@ -317,14 +318,14 @@ ZTEST(stm_mems_common, test_st_normalize)
 	st_normalize(&sensor, (int *)&actual_output, (uint8_t *)input_reading);
 
 	zassert_within(actual_output[X], expected_output[X], 0.5f,
-		      "X output is %d but expected %d", actual_output[X],
-		      expected_output[X]);
+		       "X output is %d but expected %d", actual_output[X],
+		       expected_output[X]);
 	zassert_within(actual_output[Y], expected_output[Y], 0.5f,
-		      "Y output is %d but expected %d", actual_output[Y],
-		      expected_output[Y]);
+		       "Y output is %d but expected %d", actual_output[Y],
+		       expected_output[Y]);
 	zassert_within(actual_output[Z], expected_output[Z], 0.5f,
-		      "Z output is %d but expected %d", actual_output[Z],
-		      expected_output[Z]);
+		       "Z output is %d but expected %d", actual_output[Z],
+		       expected_output[Z]);
 }
 
 static void stm_mems_common_before(void *state)
diff --git a/zephyr/test/drivers/default/src/system.c b/zephyr/test/drivers/default/src/system.c
new file mode 100644
index 0000000000..01956d8721
--- /dev/null
+++ b/zephyr/test/drivers/default/src/system.c
@@ -0,0 +1,113 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+#include "ec_commands.h"
+#include "host_command.h"
+#include "system.h"
+#include "test/drivers/test_state.h"
+
+/* System Host Commands */
+
+ZTEST_USER(system, test_hostcmd_sysinfo)
+{
+	struct ec_response_sysinfo response;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_RESPONSE(EC_CMD_SYSINFO, 0, response);
+
+	/* Simply issue the command and get the results */
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_ok(args.result, NULL);
+	zassert_equal(args.response_size, sizeof(response), NULL);
+	zassert_equal(response.reset_flags, 0, "response.reset_flags = %d",
+		      response.reset_flags);
+	zassert_equal(response.current_image, EC_IMAGE_RO,
+		      "response.current_image = %d", response.current_image);
+	zassert_equal(response.flags, 0, "response.flags = %d", response.flags);
+}
+
+ZTEST_USER(system, test_hostcmd_board_version)
+{
+	struct ec_response_board_version response;
+	struct host_cmd_handler_args args = BUILD_HOST_COMMAND_RESPONSE(
+		EC_CMD_GET_BOARD_VERSION, 0, response);
+
+	/* Get the board version, which is default 0. */
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_ok(args.result, NULL);
+	zassert_equal(args.response_size, sizeof(response), NULL);
+	zassert_equal(response.board_version, 0, "response.board_version = %d",
+		      response.board_version);
+}
+
+/* System Function Testing */
+
+static void system_flags_before_after(void *data)
+{
+	ARG_UNUSED(data);
+	system_clear_reset_flags(-1);
+}
+
+ZTEST(system_save_flags, test_system_encode_save_flags)
+{
+	int flags_to_save = 0;
+	uint32_t saved_flags = 0;
+	int arbitrary_reset_flags = 1;
+
+	/* Save all possible flags */
+	flags_to_save = -1;
+
+	/* Clear all reset flags and set them arbitrarily */
+	system_set_reset_flags(arbitrary_reset_flags);
+
+	system_encode_save_flags(flags_to_save, &saved_flags);
+
+	/* Verify all non-mutually exclusive flags */
+	zassert_equal(1, saved_flags & system_get_reset_flags(), NULL);
+	zassert_not_equal(0, saved_flags & EC_RESET_FLAG_AP_OFF, NULL);
+	zassert_not_equal(0, saved_flags & EC_RESET_FLAG_STAY_IN_RO, NULL);
+	zassert_not_equal(0, saved_flags & EC_RESET_FLAG_AP_WATCHDOG, NULL);
+}
+
+ZTEST(system_save_flags,
+      test_system_encode_save_flags_mutually_exclusive_reset_flags)
+{
+	int flags_to_save = 0;
+	uint32_t saved_flags = 0;
+
+	/* Verify reset hard takes precedence over hibernate/soft */
+	flags_to_save = SYSTEM_RESET_HARD | SYSTEM_RESET_HIBERNATE;
+
+	system_encode_save_flags(flags_to_save, &saved_flags);
+
+	zassert_not_equal(0, saved_flags & EC_RESET_FLAG_HARD, NULL);
+	zassert_equal(0, saved_flags & EC_RESET_FLAG_HIBERNATE, NULL);
+	zassert_equal(0, saved_flags & EC_RESET_FLAG_SOFT, NULL);
+
+	/* Verify reset hibernate takes precedence over soft */
+	flags_to_save = SYSTEM_RESET_HIBERNATE;
+
+	system_encode_save_flags(flags_to_save, &saved_flags);
+
+	zassert_equal(0, saved_flags & EC_RESET_FLAG_HARD, NULL);
+	zassert_not_equal(0, saved_flags & EC_RESET_FLAG_HIBERNATE, NULL);
+	zassert_equal(0, saved_flags & EC_RESET_FLAG_SOFT, NULL);
+
+	/* Verify reset soft is always saved given no other flags */
+	flags_to_save = 0;
+
+	system_encode_save_flags(flags_to_save, &saved_flags);
+
+	zassert_equal(0, saved_flags & EC_RESET_FLAG_HARD, NULL);
+	zassert_equal(0, saved_flags & EC_RESET_FLAG_HIBERNATE, NULL);
+	zassert_not_equal(0, saved_flags & EC_RESET_FLAG_SOFT, NULL);
+}
+
+ZTEST_SUITE(system, drivers_predicate_post_main, NULL, NULL, NULL, NULL);
+
+ZTEST_SUITE(system_save_flags, drivers_predicate_post_main, NULL,
+	    system_flags_before_after, system_flags_before_after, NULL);
diff --git a/zephyr/test/drivers/default/src/tablet_mode.c b/zephyr/test/drivers/default/src/tablet_mode.c
new file mode 100644
index 0000000000..d600d26072
--- /dev/null
+++ b/zephyr/test/drivers/default/src/tablet_mode.c
@@ -0,0 +1,168 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/fff.h>
+#include <zephyr/shell/shell.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+#include "console.h"
+#include "tablet_mode.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+static void tabletmode_before(void *state)
+{
+	ARG_UNUSED(state);
+	tablet_reset();
+}
+
+static void tabletmode_after(void *state)
+{
+	ARG_UNUSED(state);
+	tablet_reset();
+}
+
+/**
+ * @brief TestPurpose: various tablet_set_mode operations, make sure lid and
+ * base works independently.
+ */
+ZTEST_USER(tabletmode, test_tablet_set_mode)
+{
+	int ret;
+
+	ret = tablet_get_mode();
+	zassert_equal(ret, 0, "unexepcted tablet initial mode: %d", ret);
+
+	tablet_set_mode(1, TABLET_TRIGGER_LID);
+
+	ret = tablet_get_mode();
+	zassert_equal(ret, 1, "unexepcted tablet mode: %d", ret);
+
+	tablet_set_mode(1, TABLET_TRIGGER_BASE);
+
+	ret = tablet_get_mode();
+	zassert_equal(ret, 1, "unexepcted tablet mode: %d", ret);
+
+	tablet_set_mode(0, TABLET_TRIGGER_LID);
+
+	ret = tablet_get_mode();
+	zassert_equal(ret, 1, "unexepcted tablet mode: %d", ret);
+
+	tablet_set_mode(0, TABLET_TRIGGER_BASE);
+
+	ret = tablet_get_mode();
+	zassert_equal(ret, 0, "unexepcted tablet mode: %d", ret);
+}
+
+/**
+ * @brief TestPurpose: test the tablet_disable functionality.
+ */
+ZTEST_USER(tabletmode, test_tablet_disable)
+{
+	int ret;
+
+	ret = tablet_get_mode();
+	zassert_equal(ret, 0, "unexepcted tablet initial mode: %d", ret);
+
+	tablet_disable();
+	tablet_set_mode(1, TABLET_TRIGGER_LID);
+
+	ret = tablet_get_mode();
+	zassert_equal(ret, 0, "unexepcted tablet mode: %d", ret);
+}
+
+/**
+ * @brief TestPurpose: check that tabletmode on and off changes the mode.
+ */
+ZTEST_USER(tabletmode, test_settabletmode_on_off)
+{
+	int ret;
+
+	ret = tablet_get_mode();
+	zassert_equal(ret, 0, "unexepcted tablet initial mode: %d", ret);
+
+	ret = shell_execute_cmd(get_ec_shell(), "tabletmode");
+	zassert_equal(ret, EC_SUCCESS, "unexepcted command return status: %d",
+		      ret);
+
+	ret = tablet_get_mode();
+	zassert_equal(ret, 0, "unexepcted tablet mode: %d", ret);
+
+	ret = shell_execute_cmd(get_ec_shell(), "tabletmode on");
+	zassert_equal(ret, EC_SUCCESS, "unexepcted command return status: %d",
+		      ret);
+
+	ret = tablet_get_mode();
+	zassert_equal(ret, 1, "unexepcted tablet mode: %d", ret);
+
+	ret = shell_execute_cmd(get_ec_shell(), "tabletmode off");
+	zassert_equal(ret, EC_SUCCESS, "unexepcted command return status: %d",
+		      ret);
+
+	ret = tablet_get_mode();
+	zassert_equal(ret, 0, "unexepcted tablet mode: %d", ret);
+}
+
+/**
+ * @brief TestPurpose: ensure that console tabletmode forces the status,
+ * inhibiting tablet_set_mode, and then unforce it with reset.
+ */
+ZTEST_USER(tabletmode, test_settabletmode_forced)
+{
+	int ret;
+
+	ret = tablet_get_mode();
+	zassert_equal(ret, 0, "unexepcted tablet initial mode: %d", ret);
+
+	ret = shell_execute_cmd(get_ec_shell(), "tabletmode on");
+	zassert_equal(ret, EC_SUCCESS, "unexepcted command return status: %d",
+		      ret);
+
+	ret = tablet_get_mode();
+	zassert_equal(ret, 1, "unexepcted tablet mode: %d", ret);
+
+	tablet_set_mode(0, TABLET_TRIGGER_LID);
+
+	ret = tablet_get_mode();
+	zassert_equal(ret, 1, "unexepcted tablet mode: %d", ret);
+
+	ret = shell_execute_cmd(get_ec_shell(), "tabletmode reset");
+	zassert_equal(ret, EC_SUCCESS, "unexepcted command return status: %d",
+		      ret);
+
+	tablet_set_mode(0, TABLET_TRIGGER_LID);
+
+	ret = tablet_get_mode();
+	zassert_equal(ret, 0, "unexepcted tablet mode: %d", ret);
+}
+
+/**
+ * @brief TestPurpose: check the "too many arguments" case.
+ */
+ZTEST_USER(tabletmode, test_settabletmode_too_many_args)
+{
+	int ret;
+
+	ret = shell_execute_cmd(get_ec_shell(),
+				"tabletmode too many arguments");
+	zassert_equal(ret, EC_ERROR_PARAM_COUNT,
+		      "unexepcted command return status: %d", ret);
+}
+
+/**
+ * @brief TestPurpose: check the "unknown argument" case.
+ */
+ZTEST_USER(tabletmode, test_settabletmode_unknown_arg)
+{
+	int ret;
+
+	ret = shell_execute_cmd(get_ec_shell(), "tabletmode X");
+	zassert_equal(ret, EC_ERROR_PARAM1,
+		      "unexepcted command return status: %d", ret);
+}
+
+ZTEST_SUITE(tabletmode, drivers_predicate_post_main, NULL, tabletmode_before,
+	    tabletmode_after, NULL);
diff --git a/zephyr/test/drivers/src/tcpci.c b/zephyr/test/drivers/default/src/tcpci.c
index 167744f3a9..e549e5056a 100644
--- a/zephyr/test/drivers/src/tcpci.c
+++ b/zephyr/test/drivers/default/src/tcpci.c
@@ -1,10 +1,10 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <zephyr/zephyr.h>
-#include <ztest.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
 #include <zephyr/drivers/gpio.h>
 #include <zephyr/drivers/gpio/gpio_emul.h>
 
@@ -20,177 +20,210 @@
 #include "tcpm/tcpci.h"
 #include "test/drivers/test_state.h"
 
-#define EMUL_LABEL DT_NODELABEL(tcpci_emul)
+#define TCPCI_EMUL_NODE DT_NODELABEL(tcpci_emul)
 
 /** Test TCPCI init and vbus level */
 ZTEST(tcpci, test_generic_tcpci_init)
 {
-	const struct emul *emul = emul_get_binding(DT_LABEL(EMUL_LABEL));
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
 
-	test_tcpci_init(emul, USBC_PORT_C0);
+	test_tcpci_init(emul, common_data, USBC_PORT_C0);
 }
 
 /** Test TCPCI release */
 ZTEST(tcpci, test_generic_tcpci_release)
 {
-	const struct emul *emul = emul_get_binding(DT_LABEL(EMUL_LABEL));
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
 
-	test_tcpci_release(emul, USBC_PORT_C0);
+	test_tcpci_release(emul, common_data, USBC_PORT_C0);
 }
 
 /** Test TCPCI get cc */
 ZTEST(tcpci, test_generic_tcpci_get_cc)
 {
-	const struct emul *emul = emul_get_binding(DT_LABEL(EMUL_LABEL));
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
 
-	test_tcpci_get_cc(emul, USBC_PORT_C0);
+	test_tcpci_get_cc(emul, common_data, USBC_PORT_C0);
 }
 
 /** Test TCPCI set cc */
 ZTEST(tcpci, test_generic_tcpci_set_cc)
 {
-	const struct emul *emul = emul_get_binding(DT_LABEL(EMUL_LABEL));
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
 
-	test_tcpci_set_cc(emul, USBC_PORT_C0);
+	test_tcpci_set_cc(emul, common_data, USBC_PORT_C0);
 }
 
 /** Test TCPCI set polarity */
 ZTEST(tcpci, test_generic_tcpci_set_polarity)
 {
-	const struct emul *emul = emul_get_binding(DT_LABEL(EMUL_LABEL));
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
 
-	test_tcpci_set_polarity(emul, USBC_PORT_C0);
+	test_tcpci_set_polarity(emul, common_data, USBC_PORT_C0);
 }
 
 /** Test TCPCI set vconn */
 ZTEST(tcpci, test_generic_tcpci_set_vconn)
 {
-	const struct emul *emul = emul_get_binding(DT_LABEL(EMUL_LABEL));
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
 
-	test_tcpci_set_vconn(emul, USBC_PORT_C0);
+	test_tcpci_set_vconn(emul, common_data, USBC_PORT_C0);
 }
 
 /** Test TCPCI set msg header */
 ZTEST(tcpci, test_generic_tcpci_set_msg_header)
 {
-	const struct emul *emul = emul_get_binding(DT_LABEL(EMUL_LABEL));
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
 
-	test_tcpci_set_msg_header(emul, USBC_PORT_C0);
+	test_tcpci_set_msg_header(emul, common_data, USBC_PORT_C0);
 }
 
 /** Test TCPCI rx and sop prime enable */
 ZTEST(tcpci, test_generic_tcpci_set_rx_detect)
 {
-	const struct emul *emul = emul_get_binding(DT_LABEL(EMUL_LABEL));
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
 
-	test_tcpci_set_rx_detect(emul, USBC_PORT_C0);
+	test_tcpci_set_rx_detect(emul, common_data, USBC_PORT_C0);
 }
 
 /** Test TCPCI get raw message from TCPC revision 2.0 */
 ZTEST(tcpci, test_generic_tcpci_get_rx_message_raw_rev2)
 {
-	const struct emul *emul = emul_get_binding(DT_LABEL(EMUL_LABEL));
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
 
-	tcpc_config[USBC_PORT_C0].flags = TCPC_FLAGS_TCPCI_REV2_0;
-	tcpci_emul_set_rev(emul, TCPCI_EMUL_REV2_0_VER1_1);
-
-	test_tcpci_get_rx_message_raw(emul, USBC_PORT_C0);
+	/* Revision 2.0 is set by default in test_rules */
+	test_tcpci_get_rx_message_raw(emul, common_data, USBC_PORT_C0);
 }
 
 /** Test TCPCI get raw message from TCPC revision 1.0 */
 ZTEST(tcpci, test_generic_tcpci_get_rx_message_raw_rev1)
 {
-	const struct emul *emul = emul_get_binding(DT_LABEL(EMUL_LABEL));
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
 
 	tcpc_config[USBC_PORT_C0].flags = 0;
 	tcpci_emul_set_rev(emul, TCPCI_EMUL_REV1_0_VER1_0);
 
-	test_tcpci_get_rx_message_raw(emul, USBC_PORT_C0);
+	test_tcpci_get_rx_message_raw(emul, common_data, USBC_PORT_C0);
 }
 
 /** Test TCPCI transmitting message from TCPC revision 2.0 */
 ZTEST(tcpci, test_generic_tcpci_transmit_rev2)
 {
-	const struct emul *emul = emul_get_binding(DT_LABEL(EMUL_LABEL));
-
-	tcpc_config[USBC_PORT_C0].flags = TCPC_FLAGS_TCPCI_REV2_0;
-	tcpci_emul_set_rev(emul, TCPCI_EMUL_REV2_0_VER1_1);
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
 
-	test_tcpci_transmit(emul, USBC_PORT_C0);
+	/* Revision 2.0 is set by default in test_rules */
+	test_tcpci_transmit(emul, common_data, USBC_PORT_C0);
 }
 
 /** Test TCPCI transmitting message from TCPC revision 1.0 */
 ZTEST(tcpci, test_generic_tcpci_transmit_rev1)
 {
-	const struct emul *emul = emul_get_binding(DT_LABEL(EMUL_LABEL));
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
 
 	tcpc_config[USBC_PORT_C0].flags = 0;
 	tcpci_emul_set_rev(emul, TCPCI_EMUL_REV1_0_VER1_0);
 
-	test_tcpci_transmit(emul, USBC_PORT_C0);
+	test_tcpci_transmit(emul, common_data, USBC_PORT_C0);
 }
 
 /** Test TCPCI alert */
 ZTEST(tcpci, test_generic_tcpci_alert)
 {
-	const struct emul *emul = emul_get_binding(DT_LABEL(EMUL_LABEL));
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
 
-	test_tcpci_alert(emul, USBC_PORT_C0);
+	test_tcpci_alert(emul, common_data, USBC_PORT_C0);
 }
 
-
 /** Test TCPCI alert RX message */
 ZTEST(tcpci, test_generic_tcpci_alert_rx_message)
 {
-	const struct emul *emul = emul_get_binding(DT_LABEL(EMUL_LABEL));
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
 
-	test_tcpci_alert_rx_message(emul, USBC_PORT_C0);
+	test_tcpci_alert_rx_message(emul, common_data, USBC_PORT_C0);
 }
 
 /** Test TCPCI auto discharge on disconnect */
 ZTEST(tcpci, test_generic_tcpci_auto_discharge)
 {
-	const struct emul *emul = emul_get_binding(DT_LABEL(EMUL_LABEL));
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
 
-	test_tcpci_auto_discharge(emul, USBC_PORT_C0);
+	test_tcpci_auto_discharge(emul, common_data, USBC_PORT_C0);
 }
 
 /** Test TCPCI drp toggle */
 ZTEST(tcpci, test_generic_tcpci_drp_toggle)
 {
-	const struct emul *emul = emul_get_binding(DT_LABEL(EMUL_LABEL));
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
 
-	test_tcpci_drp_toggle(emul, USBC_PORT_C0);
+	test_tcpci_drp_toggle(emul, common_data, USBC_PORT_C0);
 }
 
 /** Test TCPCI get chip info */
 ZTEST(tcpci, test_generic_tcpci_get_chip_info)
 {
-	const struct emul *emul = emul_get_binding(DT_LABEL(EMUL_LABEL));
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
 
-	test_tcpci_get_chip_info(emul, USBC_PORT_C0);
+	test_tcpci_get_chip_info(emul, common_data, USBC_PORT_C0);
 }
 
 /** Test TCPCI enter low power mode */
 ZTEST(tcpci, test_generic_tcpci_low_power_mode)
 {
-	const struct emul *emul = emul_get_binding(DT_LABEL(EMUL_LABEL));
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
 
-	test_tcpci_low_power_mode(emul, USBC_PORT_C0);
+	test_tcpci_low_power_mode(emul, common_data, USBC_PORT_C0);
 }
 
 /** Test TCPCI set bist test mode */
 ZTEST(tcpci, test_generic_tcpci_set_bist_mode)
 {
-	const struct emul *emul = emul_get_binding(DT_LABEL(EMUL_LABEL));
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
 
-	test_tcpci_set_bist_mode(emul, USBC_PORT_C0);
+	test_tcpci_set_bist_mode(emul, common_data, USBC_PORT_C0);
 }
 
 /** Test TCPCI discharge vbus */
 ZTEST(tcpci, test_generic_tcpci_discharge_vbus)
 {
-	const struct emul *emul = emul_get_binding(DT_LABEL(EMUL_LABEL));
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
 	uint8_t exp_ctrl, initial_ctrl;
 
 	/* Set initial value for POWER ctrl register. Chosen arbitrary. */
@@ -212,7 +245,7 @@ ZTEST(tcpci, test_generic_tcpci_discharge_vbus)
 /** Test TCPC xfer */
 ZTEST(tcpci, test_tcpc_xfer)
 {
-	const struct emul *emul = emul_get_binding(DT_LABEL(EMUL_LABEL));
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
 	uint16_t val, exp_val;
 	uint8_t reg;
 
@@ -231,7 +264,7 @@ ZTEST(tcpci, test_tcpc_xfer)
 /** Test TCPCI debug accessory enable/disable */
 ZTEST(tcpci, test_generic_tcpci_debug_accessory)
 {
-	const struct emul *emul = emul_get_binding(DT_LABEL(EMUL_LABEL));
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
 	uint8_t exp_val, initial_val;
 
 	/* Set initial value for STD output register. Chosen arbitrary. */
@@ -255,61 +288,60 @@ ZTEST(tcpci, test_generic_tcpci_debug_accessory)
 /* Setup TCPCI usb mux to behave as it is used only for usb mux */
 static void set_usb_mux_not_tcpc(void)
 {
-	usb_muxes[USBC_PORT_C0].flags = USB_MUX_FLAG_NOT_TCPC;
+	usbc0_mux0.flags = USB_MUX_FLAG_NOT_TCPC;
 }
 
 /* Setup TCPCI usb mux to behave as it is used for usb mux and TCPC */
 static void set_usb_mux_tcpc(void)
 {
-	usb_muxes[USBC_PORT_C0].flags = 0;
+	usbc0_mux0.flags = 0;
 }
 
 /** Test TCPCI mux init */
 ZTEST(tcpci, test_generic_tcpci_mux_init)
 {
-	const struct emul *emul = emul_get_binding(DT_LABEL(EMUL_LABEL));
-	struct i2c_emul *i2c_emul = tcpci_emul_get_i2c_emul(emul);
-	struct usb_mux *tcpci_usb_mux = &usb_muxes[USBC_PORT_C0];
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
+	const struct usb_mux *tcpci_usb_mux = usb_muxes[USBC_PORT_C0].mux;
 
 	/* Set as usb mux with TCPC for first init call */
 	set_usb_mux_tcpc();
 
 	/* Make sure that TCPC is not accessed */
-	i2c_common_emul_set_read_fail_reg(i2c_emul,
+	i2c_common_emul_set_read_fail_reg(common_data,
 					  I2C_COMMON_EMUL_FAIL_ALL_REG);
-	zassert_equal(EC_SUCCESS, tcpci_tcpm_mux_init(tcpci_usb_mux),
-		      NULL);
+	zassert_equal(EC_SUCCESS, tcpci_tcpm_mux_init(tcpci_usb_mux), NULL);
 
 	/* Set as only usb mux without TCPC for rest of the test */
 	set_usb_mux_not_tcpc();
 
 	/* Test fail on power status read */
-	i2c_common_emul_set_read_fail_reg(i2c_emul, TCPC_REG_POWER_STATUS);
-	zassert_equal(EC_ERROR_INVAL, tcpci_tcpm_mux_init(tcpci_usb_mux),
-		      NULL);
-	i2c_common_emul_set_read_fail_reg(i2c_emul,
+	i2c_common_emul_set_read_fail_reg(common_data, TCPC_REG_POWER_STATUS);
+	zassert_equal(EC_ERROR_INVAL, tcpci_tcpm_mux_init(tcpci_usb_mux), NULL);
+	i2c_common_emul_set_read_fail_reg(common_data,
 					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test fail on uninitialised bit set */
 	tcpci_emul_set_reg(emul, TCPC_REG_POWER_STATUS,
 			   TCPC_REG_POWER_STATUS_UNINIT);
-	zassert_equal(EC_ERROR_TIMEOUT,
-		      tcpci_tcpm_mux_init(tcpci_usb_mux), NULL);
+	zassert_equal(EC_ERROR_TIMEOUT, tcpci_tcpm_mux_init(tcpci_usb_mux),
+		      NULL);
 
 	/* Set default power status for rest of the test */
 	tcpci_emul_set_reg(emul, TCPC_REG_POWER_STATUS,
 			   TCPC_REG_POWER_STATUS_VBUS_DET);
 
 	/* Test fail on alert mask write fail */
-	i2c_common_emul_set_write_fail_reg(i2c_emul, TCPC_REG_ALERT_MASK);
-	zassert_equal(EC_ERROR_UNKNOWN,
-		      tcpci_tcpm_mux_init(tcpci_usb_mux), NULL);
+	i2c_common_emul_set_write_fail_reg(common_data, TCPC_REG_ALERT_MASK);
+	zassert_equal(EC_ERROR_UNKNOWN, tcpci_tcpm_mux_init(tcpci_usb_mux),
+		      NULL);
 
 	/* Test fail on alert write fail */
-	i2c_common_emul_set_write_fail_reg(i2c_emul, TCPC_REG_ALERT);
-	zassert_equal(EC_ERROR_UNKNOWN,
-		      tcpci_tcpm_mux_init(tcpci_usb_mux), NULL);
-	i2c_common_emul_set_write_fail_reg(i2c_emul,
+	i2c_common_emul_set_write_fail_reg(common_data, TCPC_REG_ALERT);
+	zassert_equal(EC_ERROR_UNKNOWN, tcpci_tcpm_mux_init(tcpci_usb_mux),
+		      NULL);
+	i2c_common_emul_set_write_fail_reg(common_data,
 					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Set arbitrary value to alert and alert mask registers */
@@ -317,8 +349,7 @@ ZTEST(tcpci, test_generic_tcpci_mux_init)
 	tcpci_emul_set_reg(emul, TCPC_REG_ALERT_MASK, 0xffff);
 
 	/* Test success init */
-	zassert_equal(EC_SUCCESS, tcpci_tcpm_mux_init(tcpci_usb_mux),
-		      NULL);
+	zassert_equal(EC_SUCCESS, tcpci_tcpm_mux_init(tcpci_usb_mux), NULL);
 	check_tcpci_reg(emul, TCPC_REG_ALERT_MASK, 0);
 	check_tcpci_reg(emul, TCPC_REG_ALERT, 0);
 }
@@ -326,34 +357,32 @@ ZTEST(tcpci, test_generic_tcpci_mux_init)
 /** Test TCPCI mux enter low power mode */
 ZTEST(tcpci, test_generic_tcpci_mux_enter_low_power)
 {
-	const struct emul *emul = emul_get_binding(DT_LABEL(EMUL_LABEL));
-	struct i2c_emul *i2c_emul = tcpci_emul_get_i2c_emul(emul);
-	struct usb_mux *tcpci_usb_mux = &usb_muxes[USBC_PORT_C0];
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
+	const struct usb_mux *tcpci_usb_mux = usb_muxes[USBC_PORT_C0].mux;
 
 	/* Set as usb mux with TCPC for first enter_low_power call */
 	set_usb_mux_tcpc();
 
 	/* Make sure that TCPC is not accessed */
-	i2c_common_emul_set_write_fail_reg(i2c_emul,
+	i2c_common_emul_set_write_fail_reg(common_data,
 					   I2C_COMMON_EMUL_FAIL_ALL_REG);
-	zassert_equal(EC_SUCCESS,
-		      tcpci_tcpm_mux_enter_low_power(tcpci_usb_mux),
+	zassert_equal(EC_SUCCESS, tcpci_tcpm_mux_enter_low_power(tcpci_usb_mux),
 		      NULL);
 
 	/* Set as only usb mux without TCPC for rest of the test */
 	set_usb_mux_not_tcpc();
 
 	/* Test error on failed command set */
-	i2c_common_emul_set_write_fail_reg(i2c_emul, TCPC_REG_COMMAND);
+	i2c_common_emul_set_write_fail_reg(common_data, TCPC_REG_COMMAND);
 	zassert_equal(EC_ERROR_INVAL,
-		      tcpci_tcpm_mux_enter_low_power(tcpci_usb_mux),
-		      NULL);
-	i2c_common_emul_set_write_fail_reg(i2c_emul,
+		      tcpci_tcpm_mux_enter_low_power(tcpci_usb_mux), NULL);
+	i2c_common_emul_set_write_fail_reg(common_data,
 					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test correct command is issued */
-	zassert_equal(EC_SUCCESS,
-		      tcpci_tcpm_mux_enter_low_power(tcpci_usb_mux),
+	zassert_equal(EC_SUCCESS, tcpci_tcpm_mux_enter_low_power(tcpci_usb_mux),
 		      NULL);
 	check_tcpci_reg(emul, TCPC_REG_COMMAND, TCPC_REG_COMMAND_I2CIDLE);
 }
@@ -361,9 +390,10 @@ ZTEST(tcpci, test_generic_tcpci_mux_enter_low_power)
 /** Test TCPCI mux set and get */
 static void test_generic_tcpci_mux_set_get(void)
 {
-	const struct emul *emul = emul_get_binding(DT_LABEL(EMUL_LABEL));
-	struct i2c_emul *i2c_emul = tcpci_emul_get_i2c_emul(emul);
-	struct usb_mux *tcpci_usb_mux = &usb_muxes[USBC_PORT_C0];
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
+	const struct usb_mux *tcpci_usb_mux = usb_muxes[USBC_PORT_C0].mux;
 	mux_state_t mux_state, mux_state_get;
 	uint16_t exp_val, initial_val;
 	bool ack;
@@ -371,23 +401,21 @@ static void test_generic_tcpci_mux_set_get(void)
 	mux_state = USB_PD_MUX_NONE;
 
 	/* Test fail on standard output config register read */
-	i2c_common_emul_set_read_fail_reg(i2c_emul, TCPC_REG_CONFIG_STD_OUTPUT);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  TCPC_REG_CONFIG_STD_OUTPUT);
 	zassert_equal(EC_ERROR_INVAL,
-		      tcpci_tcpm_mux_set(tcpci_usb_mux, mux_state, &ack),
-		      NULL);
+		      tcpci_tcpm_mux_set(tcpci_usb_mux, mux_state, &ack), NULL);
 	zassert_equal(EC_ERROR_INVAL,
-		      tcpci_tcpm_mux_get(tcpci_usb_mux, &mux_state_get),
-		      NULL);
-	i2c_common_emul_set_read_fail_reg(i2c_emul,
+		      tcpci_tcpm_mux_get(tcpci_usb_mux, &mux_state_get), NULL);
+	i2c_common_emul_set_read_fail_reg(common_data,
 					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test fail on standard output config register write */
-	i2c_common_emul_set_write_fail_reg(i2c_emul,
+	i2c_common_emul_set_write_fail_reg(common_data,
 					   TCPC_REG_CONFIG_STD_OUTPUT);
 	zassert_equal(EC_ERROR_INVAL,
-		      tcpci_tcpm_mux_set(tcpci_usb_mux, mux_state, &ack),
-		      NULL);
-	i2c_common_emul_set_write_fail_reg(i2c_emul,
+		      tcpci_tcpm_mux_set(tcpci_usb_mux, mux_state, &ack), NULL);
+	i2c_common_emul_set_write_fail_reg(common_data,
 					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Set initial value for STD output register. Chosen arbitrary. */
@@ -403,13 +431,11 @@ static void test_generic_tcpci_mux_set_get(void)
 	exp_val &= ~TCPC_REG_CONFIG_STD_OUTPUT_CONNECTOR_FLIPPED;
 	mux_state = USB_PD_MUX_NONE;
 	zassert_equal(EC_SUCCESS,
-		      tcpci_tcpm_mux_set(tcpci_usb_mux, mux_state, &ack),
-		      NULL);
+		      tcpci_tcpm_mux_set(tcpci_usb_mux, mux_state, &ack), NULL);
 	check_tcpci_reg(emul, TCPC_REG_CONFIG_STD_OUTPUT, exp_val);
 	zassert_false(ack, "Ack from host shouldn't be required");
 	zassert_equal(EC_SUCCESS,
-		      tcpci_tcpm_mux_get(tcpci_usb_mux, &mux_state_get),
-		      NULL);
+		      tcpci_tcpm_mux_get(tcpci_usb_mux, &mux_state_get), NULL);
 	zassert_equal(mux_state, mux_state_get, "Expected state 0x%x, got 0x%x",
 		      mux_state, mux_state_get);
 
@@ -419,13 +445,11 @@ static void test_generic_tcpci_mux_set_get(void)
 		  TCPC_REG_CONFIG_STD_OUTPUT_CONNECTOR_FLIPPED;
 	mux_state = USB_PD_MUX_DP_ENABLED | USB_PD_MUX_POLARITY_INVERTED;
 	zassert_equal(EC_SUCCESS,
-		      tcpci_tcpm_mux_set(tcpci_usb_mux, mux_state, &ack),
-		      NULL);
+		      tcpci_tcpm_mux_set(tcpci_usb_mux, mux_state, &ack), NULL);
 	check_tcpci_reg(emul, TCPC_REG_CONFIG_STD_OUTPUT, exp_val);
 	zassert_false(ack, "Ack from host shouldn't be required");
 	zassert_equal(EC_SUCCESS,
-		      tcpci_tcpm_mux_get(tcpci_usb_mux, &mux_state_get),
-		      NULL);
+		      tcpci_tcpm_mux_get(tcpci_usb_mux, &mux_state_get), NULL);
 	zassert_equal(mux_state, mux_state_get, "Expected state 0x%x, got 0x%x",
 		      mux_state, mux_state_get);
 
@@ -435,13 +459,11 @@ static void test_generic_tcpci_mux_set_get(void)
 	exp_val &= ~TCPC_REG_CONFIG_STD_OUTPUT_CONNECTOR_FLIPPED;
 	mux_state = USB_PD_MUX_USB_ENABLED;
 	zassert_equal(EC_SUCCESS,
-		      tcpci_tcpm_mux_set(tcpci_usb_mux, mux_state, &ack),
-		      NULL);
+		      tcpci_tcpm_mux_set(tcpci_usb_mux, mux_state, &ack), NULL);
 	check_tcpci_reg(emul, TCPC_REG_CONFIG_STD_OUTPUT, exp_val);
 	zassert_false(ack, "Ack from host shouldn't be required");
 	zassert_equal(EC_SUCCESS,
-		      tcpci_tcpm_mux_get(tcpci_usb_mux, &mux_state_get),
-		      NULL);
+		      tcpci_tcpm_mux_get(tcpci_usb_mux, &mux_state_get), NULL);
 	zassert_equal(mux_state, mux_state_get, "Expected state 0x%x, got 0x%x",
 		      mux_state, mux_state_get);
 
@@ -453,13 +475,11 @@ static void test_generic_tcpci_mux_set_get(void)
 	mux_state = USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED |
 		    USB_PD_MUX_POLARITY_INVERTED;
 	zassert_equal(EC_SUCCESS,
-		      tcpci_tcpm_mux_set(tcpci_usb_mux, mux_state, &ack),
-		      NULL);
+		      tcpci_tcpm_mux_set(tcpci_usb_mux, mux_state, &ack), NULL);
 	check_tcpci_reg(emul, TCPC_REG_CONFIG_STD_OUTPUT, exp_val);
 	zassert_false(ack, "Ack from host shouldn't be required");
 	zassert_equal(EC_SUCCESS,
-		      tcpci_tcpm_mux_get(tcpci_usb_mux, &mux_state_get),
-		      NULL);
+		      tcpci_tcpm_mux_get(tcpci_usb_mux, &mux_state_get), NULL);
 	zassert_equal(mux_state, mux_state_get, "Expected state 0x%x, got 0x%x",
 		      mux_state, mux_state_get);
 }
@@ -476,13 +496,29 @@ ZTEST(tcpci, test_generic_tcpci_mux_set_get__not_tcpc)
 	set_usb_mux_tcpc();
 }
 
+ZTEST(tcpci, test_generic_tcpci_hard_reset_reinit)
+{
+	const struct emul *emul = EMUL_DT_GET(TCPCI_EMUL_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcpci_generic_get_i2c_common_data(emul);
+
+	test_tcpci_hard_reset_reinit(emul, common_data, USBC_PORT_C0);
+}
+
 static void *tcpci_setup(void)
 {
 	/* This test suite assumes that first usb mux for port C0 is TCPCI */
-	__ASSERT(usb_muxes[USBC_PORT_C0].driver == &tcpci_tcpm_usb_mux_driver,
+	__ASSERT(usb_muxes[USBC_PORT_C0].mux->driver ==
+			 &tcpci_tcpm_usb_mux_driver,
 		 "Invalid config of usb_muxes in test/drivers/src/stubs.c");
 
 	return NULL;
 }
 
-ZTEST_SUITE(tcpci, drivers_predicate_post_main, tcpci_setup, NULL, NULL, NULL);
+static void tcpci_after(void *state)
+{
+	set_usb_mux_tcpc();
+}
+
+ZTEST_SUITE(tcpci, drivers_predicate_pre_main, tcpci_setup, NULL, tcpci_after,
+	    NULL);
diff --git a/zephyr/test/drivers/src/tcpci_test_common.c b/zephyr/test/drivers/default/src/tcpci_test_common.c
index ccd250e11f..f2c0c58bf9 100644
--- a/zephyr/test/drivers/src/tcpci_test_common.c
+++ b/zephyr/test/drivers/default/src/tcpci_test_common.c
@@ -1,10 +1,10 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <zephyr/zephyr.h>
-#include <ztest.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
 
 #include "common.h"
 #include "emul/emul_common_i2c.h"
@@ -34,25 +34,24 @@ void check_tcpci_reg_with_mask_f(const struct emul *emul, int reg,
 	zassert_ok(tcpci_emul_get_reg(emul, reg, &reg_val),
 		   "Failed tcpci_emul_get_reg(); line: %d", line);
 	zassert_equal(exp_val & mask, reg_val & mask,
-		      "Expected 0x%x, got 0x%x, mask 0x%x; line: %d",
-		      exp_val, reg_val, mask, line);
+		      "Expected 0x%x, got 0x%x, mask 0x%x; line: %d", exp_val,
+		      reg_val, mask, line);
 }
 
 /** Test TCPCI init and vbus level */
-void test_tcpci_init(const struct emul *emul, enum usbc_port port)
+void test_tcpci_init(const struct emul *emul,
+		     struct i2c_common_emul_data *common_data,
+		     enum usbc_port port)
 {
 	const struct tcpm_drv *drv = tcpc_config[port].drv;
-	struct i2c_emul *i2c_emul = tcpci_emul_get_i2c_emul(emul);
 	uint16_t exp_mask;
 
-	tcpc_config[port].flags = TCPC_FLAGS_TCPCI_REV2_0 &
-				  TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V;
-	tcpci_emul_set_rev(emul, TCPCI_EMUL_REV2_0_VER1_1);
+	tcpc_config[port].flags |= TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V;
 
 	/* Test fail on power status read */
-	i2c_common_emul_set_read_fail_reg(i2c_emul, TCPC_REG_POWER_STATUS);
+	i2c_common_emul_set_read_fail_reg(common_data, TCPC_REG_POWER_STATUS);
 	zassert_equal(EC_ERROR_INVAL, drv->init(port), NULL);
-	i2c_common_emul_set_read_fail_reg(i2c_emul,
+	i2c_common_emul_set_read_fail_reg(common_data,
 					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test fail on uninitialised bit set */
@@ -84,7 +83,7 @@ void test_tcpci_init(const struct emul *emul, enum usbc_port port)
 	/* Set TCPCI emulator VBUS to present (connected, above 4V) */
 	tcpci_emul_set_reg(emul, TCPC_REG_POWER_STATUS,
 			   TCPC_REG_POWER_STATUS_VBUS_PRES |
-			   TCPC_REG_POWER_STATUS_VBUS_DET);
+				   TCPC_REG_POWER_STATUS_VBUS_DET);
 
 	/* Test init with VBUS present without vSafe0V tcpc config flag */
 	zassert_equal(EC_SUCCESS, drv->init(port), NULL);
@@ -136,7 +135,9 @@ void test_tcpci_init(const struct emul *emul, enum usbc_port port)
 }
 
 /** Test TCPCI release */
-void test_tcpci_release(const struct emul *emul, enum usbc_port port)
+void test_tcpci_release(const struct emul *emul,
+			struct i2c_common_emul_data *common_data,
+			enum usbc_port port)
 {
 	const struct tcpm_drv *drv = tcpc_config[port].drv;
 
@@ -149,7 +150,9 @@ void test_tcpci_release(const struct emul *emul, enum usbc_port port)
 }
 
 /** Test TCPCI get cc */
-void test_tcpci_get_cc(const struct emul *emul, enum usbc_port port)
+void test_tcpci_get_cc(const struct emul *emul,
+		       struct i2c_common_emul_data *common_data,
+		       enum usbc_port port)
 {
 	const struct tcpm_drv *drv = tcpc_config[port].drv;
 	enum tcpc_cc_voltage_status cc1, cc2;
@@ -165,61 +168,61 @@ void test_tcpci_get_cc(const struct emul *emul, enum usbc_port port)
 	} test_param[] = {
 		/* Test DRP with open state */
 		{
-			.cc = {TYPEC_CC_VOLT_OPEN, TYPEC_CC_VOLT_OPEN},
+			.cc = { TYPEC_CC_VOLT_OPEN, TYPEC_CC_VOLT_OPEN },
 			.connect_result = false,
 			.drp = TYPEC_DRP,
 		},
 		/* Test DRP with cc1 open state, cc2 src RA */
 		{
-			.cc = {TYPEC_CC_VOLT_OPEN, TYPEC_CC_VOLT_RA},
+			.cc = { TYPEC_CC_VOLT_OPEN, TYPEC_CC_VOLT_RA },
 			.connect_result = false,
 			.drp = TYPEC_DRP,
 		},
 		/* Test DRP with cc1 src RA, cc2 src RD */
 		{
-			.cc = {TYPEC_CC_VOLT_RA, TYPEC_CC_VOLT_RD},
+			.cc = { TYPEC_CC_VOLT_RA, TYPEC_CC_VOLT_RD },
 			.connect_result = false,
 			.drp = TYPEC_DRP,
 		},
 		/* Test DRP with cc1 snk open, cc2 snk default */
 		{
-			.cc = {TYPEC_CC_VOLT_OPEN, TYPEC_CC_VOLT_RP_DEF},
+			.cc = { TYPEC_CC_VOLT_OPEN, TYPEC_CC_VOLT_RP_DEF },
 			.connect_result = true,
 			.drp = TYPEC_DRP,
 		},
 		/* Test DRP with cc1 snk 1.5, cc2 snk 3.0 */
 		{
-			.cc = {TYPEC_CC_VOLT_RP_1_5, TYPEC_CC_VOLT_RP_3_0},
+			.cc = { TYPEC_CC_VOLT_RP_1_5, TYPEC_CC_VOLT_RP_3_0 },
 			.connect_result = true,
 			.drp = TYPEC_DRP,
 		},
 		/* Test no DRP with cc1 src open, cc2 src RA */
 		{
-			.cc = {TYPEC_CC_VOLT_OPEN, TYPEC_CC_VOLT_RA},
+			.cc = { TYPEC_CC_VOLT_OPEN, TYPEC_CC_VOLT_RA },
 			.connect_result = false,
 			.drp = TYPEC_NO_DRP,
-			.role_cc = {TYPEC_CC_RP, TYPEC_CC_RP},
+			.role_cc = { TYPEC_CC_RP, TYPEC_CC_RP },
 		},
 		/* Test no DRP with cc1 src RD, cc2 snk default */
 		{
-			.cc = {TYPEC_CC_VOLT_RD, TYPEC_CC_VOLT_RP_DEF},
+			.cc = { TYPEC_CC_VOLT_RD, TYPEC_CC_VOLT_RP_DEF },
 			.connect_result = false,
 			.drp = TYPEC_NO_DRP,
-			.role_cc = {TYPEC_CC_RP, TYPEC_CC_RD},
+			.role_cc = { TYPEC_CC_RP, TYPEC_CC_RD },
 		},
 		/* Test no DRP with cc1 snk default, cc2 snk open */
 		{
-			.cc = {TYPEC_CC_VOLT_RP_DEF, TYPEC_CC_VOLT_OPEN},
+			.cc = { TYPEC_CC_VOLT_RP_DEF, TYPEC_CC_VOLT_OPEN },
 			.connect_result = false,
 			.drp = TYPEC_NO_DRP,
-			.role_cc = {TYPEC_CC_RD, TYPEC_CC_RD},
+			.role_cc = { TYPEC_CC_RD, TYPEC_CC_RD },
 		},
 		/* Test no DRP with cc1 snk 3.0, cc2 snk 1.5 */
 		{
-			.cc = {TYPEC_CC_VOLT_RP_3_0, TYPEC_CC_VOLT_RP_1_5},
+			.cc = { TYPEC_CC_VOLT_RP_3_0, TYPEC_CC_VOLT_RP_1_5 },
 			.connect_result = false,
 			.drp = TYPEC_NO_DRP,
-			.role_cc = {TYPEC_CC_RD, TYPEC_CC_RD},
+			.role_cc = { TYPEC_CC_RD, TYPEC_CC_RD },
 		},
 	};
 
@@ -233,25 +236,27 @@ void test_tcpci_get_cc(const struct emul *emul, enum usbc_port port)
 						   test_param[i].cc[1]);
 		tcpci_emul_set_reg(emul, TCPC_REG_ROLE_CTRL, role_ctrl);
 		tcpci_emul_set_reg(emul, TCPC_REG_CC_STATUS, cc_status);
-		zassert_equal(EC_SUCCESS, drv->get_cc(port, &cc1, &cc2),
-			      "Failed to get CC in test case %d (CC 0x%x, role 0x%x)",
-			      i, cc_status, role_ctrl);
-		zassert_equal(test_param[i].cc[0], cc1,
-			      "0x%x != (cc1 = 0x%x) in test case %d (CC 0x%x, role 0x%x)",
-			      test_param[i].cc[0], cc1, i, cc_status,
-			      role_ctrl);
-		zassert_equal(test_param[i].cc[1], cc2,
-			      "0x%x != (cc2 = 0x%x) in test case %d (CC 0x%x, role 0x%x)",
-			      test_param[i].cc[0], cc1, i, cc_status,
-			      role_ctrl);
+		zassert_equal(
+			EC_SUCCESS, drv->get_cc(port, &cc1, &cc2),
+			"Failed to get CC in test case %d (CC 0x%x, role 0x%x)",
+			i, cc_status, role_ctrl);
+		zassert_equal(
+			test_param[i].cc[0], cc1,
+			"0x%x != (cc1 = 0x%x) in test case %d (CC 0x%x, role 0x%x)",
+			test_param[i].cc[0], cc1, i, cc_status, role_ctrl);
+		zassert_equal(
+			test_param[i].cc[1], cc2,
+			"0x%x != (cc2 = 0x%x) in test case %d (CC 0x%x, role 0x%x)",
+			test_param[i].cc[0], cc1, i, cc_status, role_ctrl);
 	}
 }
 
 /** Test TCPCI set cc */
-void test_tcpci_set_cc(const struct emul *emul, enum usbc_port port)
+void test_tcpci_set_cc(const struct emul *emul,
+		       struct i2c_common_emul_data *common_data,
+		       enum usbc_port port)
 {
 	const struct tcpm_drv *drv = tcpc_config[port].drv;
-	struct i2c_emul *i2c_emul = tcpci_emul_get_i2c_emul(emul);
 	enum tcpc_rp_value rp;
 	enum tcpc_cc_pull cc;
 
@@ -264,9 +269,9 @@ void test_tcpci_set_cc(const struct emul *emul, enum usbc_port port)
 			TCPC_REG_ROLE_CTRL_SET(TYPEC_NO_DRP, rp, cc, cc));
 
 	/* Test error on failed role ctrl set */
-	i2c_common_emul_set_write_fail_reg(i2c_emul, TCPC_REG_ROLE_CTRL);
+	i2c_common_emul_set_write_fail_reg(common_data, TCPC_REG_ROLE_CTRL);
 	zassert_equal(EC_ERROR_INVAL, drv->set_cc(port, TYPEC_CC_OPEN), NULL);
-	i2c_common_emul_set_write_fail_reg(i2c_emul,
+	i2c_common_emul_set_write_fail_reg(common_data,
 					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test setting 1.5 RP and cc RD */
@@ -296,10 +301,11 @@ void test_tcpci_set_cc(const struct emul *emul, enum usbc_port port)
 }
 
 /** Test TCPCI set polarity */
-void test_tcpci_set_polarity(const struct emul *emul, enum usbc_port port)
+void test_tcpci_set_polarity(const struct emul *emul,
+			     struct i2c_common_emul_data *common_data,
+			     enum usbc_port port)
 {
 	const struct tcpm_drv *drv = tcpc_config[port].drv;
-	struct i2c_emul *i2c_emul = tcpci_emul_get_i2c_emul(emul);
 	uint8_t initial_ctrl;
 	uint8_t exp_ctrl;
 
@@ -310,10 +316,10 @@ void test_tcpci_set_polarity(const struct emul *emul, enum usbc_port port)
 
 	/* Test error on failed polarity set */
 	exp_ctrl = initial_ctrl;
-	i2c_common_emul_set_write_fail_reg(i2c_emul, TCPC_REG_TCPC_CTRL);
+	i2c_common_emul_set_write_fail_reg(common_data, TCPC_REG_TCPC_CTRL);
 	zassert_equal(EC_ERROR_INVAL, drv->set_polarity(port, POLARITY_CC2),
 		      NULL);
-	i2c_common_emul_set_write_fail_reg(i2c_emul,
+	i2c_common_emul_set_write_fail_reg(common_data,
 					   I2C_COMMON_EMUL_NO_FAIL_REG);
 	check_tcpci_reg(emul, TCPC_REG_TCPC_CTRL, exp_ctrl);
 
@@ -341,10 +347,11 @@ void test_tcpci_set_polarity(const struct emul *emul, enum usbc_port port)
 }
 
 /** Test TCPCI set vconn */
-void test_tcpci_set_vconn(const struct emul *emul, enum usbc_port port)
+void test_tcpci_set_vconn(const struct emul *emul,
+			  struct i2c_common_emul_data *common_data,
+			  enum usbc_port port)
 {
 	const struct tcpm_drv *drv = tcpc_config[port].drv;
-	struct i2c_emul *i2c_emul = tcpci_emul_get_i2c_emul(emul);
 	uint8_t initial_ctrl;
 	uint8_t exp_ctrl;
 
@@ -355,9 +362,9 @@ void test_tcpci_set_vconn(const struct emul *emul, enum usbc_port port)
 
 	/* Test error on failed vconn set */
 	exp_ctrl = initial_ctrl;
-	i2c_common_emul_set_write_fail_reg(i2c_emul, TCPC_REG_POWER_CTRL);
+	i2c_common_emul_set_write_fail_reg(common_data, TCPC_REG_POWER_CTRL);
 	zassert_equal(EC_ERROR_INVAL, drv->set_vconn(port, 1), NULL);
-	i2c_common_emul_set_write_fail_reg(i2c_emul,
+	i2c_common_emul_set_write_fail_reg(common_data,
 					   I2C_COMMON_EMUL_NO_FAIL_REG);
 	check_tcpci_reg(emul, TCPC_REG_POWER_CTRL, exp_ctrl);
 
@@ -373,53 +380,60 @@ void test_tcpci_set_vconn(const struct emul *emul, enum usbc_port port)
 }
 
 /** Test TCPCI set msg header */
-void test_tcpci_set_msg_header(const struct emul *emul, enum usbc_port port)
+void test_tcpci_set_msg_header(const struct emul *emul,
+			       struct i2c_common_emul_data *common_data,
+			       enum usbc_port port)
 {
 	const struct tcpm_drv *drv = tcpc_config[port].drv;
-	struct i2c_emul *i2c_emul = tcpci_emul_get_i2c_emul(emul);
 
 	/* Test error on failed header set */
-	i2c_common_emul_set_write_fail_reg(i2c_emul, TCPC_REG_MSG_HDR_INFO);
-	zassert_equal(EC_ERROR_INVAL, drv->set_msg_header(port, PD_ROLE_SINK,
-							  PD_ROLE_UFP), NULL);
-	i2c_common_emul_set_write_fail_reg(i2c_emul,
+	i2c_common_emul_set_write_fail_reg(common_data, TCPC_REG_MSG_HDR_INFO);
+	zassert_equal(EC_ERROR_INVAL,
+		      drv->set_msg_header(port, PD_ROLE_SINK, PD_ROLE_UFP),
+		      NULL);
+	i2c_common_emul_set_write_fail_reg(common_data,
 					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test setting sink UFP */
-	zassert_equal(EC_SUCCESS, drv->set_msg_header(port, PD_ROLE_SINK,
-						      PD_ROLE_UFP), NULL);
+	zassert_equal(EC_SUCCESS,
+		      drv->set_msg_header(port, PD_ROLE_SINK, PD_ROLE_UFP),
+		      NULL);
 	check_tcpci_reg(emul, TCPC_REG_MSG_HDR_INFO,
 			TCPC_REG_MSG_HDR_INFO_SET(PD_ROLE_UFP, PD_ROLE_SINK));
 
 	/* Test setting sink DFP */
-	zassert_equal(EC_SUCCESS, drv->set_msg_header(port, PD_ROLE_SINK,
-						      PD_ROLE_DFP), NULL);
+	zassert_equal(EC_SUCCESS,
+		      drv->set_msg_header(port, PD_ROLE_SINK, PD_ROLE_DFP),
+		      NULL);
 	check_tcpci_reg(emul, TCPC_REG_MSG_HDR_INFO,
 			TCPC_REG_MSG_HDR_INFO_SET(PD_ROLE_DFP, PD_ROLE_SINK));
 
 	/* Test setting source UFP */
-	zassert_equal(EC_SUCCESS, drv->set_msg_header(port, PD_ROLE_SOURCE,
-						      PD_ROLE_UFP), NULL);
+	zassert_equal(EC_SUCCESS,
+		      drv->set_msg_header(port, PD_ROLE_SOURCE, PD_ROLE_UFP),
+		      NULL);
 	check_tcpci_reg(emul, TCPC_REG_MSG_HDR_INFO,
 			TCPC_REG_MSG_HDR_INFO_SET(PD_ROLE_UFP, PD_ROLE_SOURCE));
 
 	/* Test setting source DFP */
-	zassert_equal(EC_SUCCESS, drv->set_msg_header(port, PD_ROLE_SOURCE,
-						      PD_ROLE_DFP), NULL);
+	zassert_equal(EC_SUCCESS,
+		      drv->set_msg_header(port, PD_ROLE_SOURCE, PD_ROLE_DFP),
+		      NULL);
 	check_tcpci_reg(emul, TCPC_REG_MSG_HDR_INFO,
 			TCPC_REG_MSG_HDR_INFO_SET(PD_ROLE_DFP, PD_ROLE_SOURCE));
 }
 
 /** Test TCPCI rx and sop prime enable */
-void test_tcpci_set_rx_detect(const struct emul *emul, enum usbc_port port)
+void test_tcpci_set_rx_detect(const struct emul *emul,
+			      struct i2c_common_emul_data *common_data,
+			      enum usbc_port port)
 {
 	const struct tcpm_drv *drv = tcpc_config[port].drv;
-	struct i2c_emul *i2c_emul = tcpci_emul_get_i2c_emul(emul);
 
 	/* Test error from rx_enable on rx detect set */
-	i2c_common_emul_set_write_fail_reg(i2c_emul, TCPC_REG_RX_DETECT);
+	i2c_common_emul_set_write_fail_reg(common_data, TCPC_REG_RX_DETECT);
 	zassert_equal(EC_ERROR_INVAL, drv->set_rx_enable(port, 1), NULL);
-	i2c_common_emul_set_write_fail_reg(i2c_emul,
+	i2c_common_emul_set_write_fail_reg(common_data,
 					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test rx disable */
@@ -436,9 +450,9 @@ void test_tcpci_set_rx_detect(const struct emul *emul, enum usbc_port port)
 			TCPC_REG_RX_DETECT_SOP_SOPP_SOPPP_HRST_MASK);
 
 	/* Test error from sop_prime on rx detect set */
-	i2c_common_emul_set_write_fail_reg(i2c_emul, TCPC_REG_RX_DETECT);
+	i2c_common_emul_set_write_fail_reg(common_data, TCPC_REG_RX_DETECT);
 	zassert_equal(EC_ERROR_INVAL, drv->sop_prime_enable(port, 0), NULL);
-	i2c_common_emul_set_write_fail_reg(i2c_emul,
+	i2c_common_emul_set_write_fail_reg(common_data,
 					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test disabling sop prime with rx enabled does change RX_DETECT */
@@ -456,10 +470,10 @@ void test_tcpci_set_rx_detect(const struct emul *emul, enum usbc_port port)
 
 /** Test TCPCI get raw message from TCPC */
 void test_tcpci_get_rx_message_raw(const struct emul *emul,
+				   struct i2c_common_emul_data *common_data,
 				   enum usbc_port port)
 {
 	const struct tcpm_drv *drv = tcpc_config[port].drv;
-	struct i2c_emul *i2c_emul = tcpci_emul_get_i2c_emul(emul);
 	struct tcpci_emul_msg msg;
 	uint32_t payload[7];
 	uint16_t rx_mask;
@@ -479,16 +493,16 @@ void test_tcpci_get_rx_message_raw(const struct emul *emul,
 	}
 	msg.buf = buf;
 	msg.cnt = 31;
-	msg.type = TCPCI_MSG_SOP;
+	msg.sop_type = TCPCI_MSG_SOP;
 	zassert_equal(TCPCI_EMUL_TX_SUCCESS,
 		      tcpci_emul_add_rx_msg(emul, &msg, true),
 		      "Failed to setup emulator message");
 
 	/* Test fail on reading byte count */
-	i2c_common_emul_set_read_fail_reg(i2c_emul, TCPC_REG_RX_BUFFER);
+	i2c_common_emul_set_read_fail_reg(common_data, TCPC_REG_RX_BUFFER);
 	zassert_equal(EC_ERROR_UNKNOWN,
 		      drv->get_message_raw(port, payload, &head), NULL);
-	i2c_common_emul_set_read_fail_reg(i2c_emul,
+	i2c_common_emul_set_read_fail_reg(common_data,
 					  I2C_COMMON_EMUL_NO_FAIL_REG);
 	/* Get raw message should always clean RX alerts */
 	rx_mask = TCPC_REG_ALERT_RX_BUF_OVF | TCPC_REG_ALERT_RX_STATUS;
@@ -515,7 +529,7 @@ void test_tcpci_get_rx_message_raw(const struct emul *emul,
 	/* Test alert register and message payload on success */
 	size = 28;
 	msg.cnt = size + 2;
-	msg.type = TCPCI_MSG_SOP_PRIME;
+	msg.sop_type = TCPCI_MSG_SOP_PRIME;
 	zassert_equal(TCPCI_EMUL_TX_SUCCESS,
 		      tcpci_emul_add_rx_msg(emul, &msg, true),
 		      "Failed to setup emulator message");
@@ -528,16 +542,17 @@ void test_tcpci_get_rx_message_raw(const struct emul *emul,
 	 */
 	exp_head = (TCPCI_MSG_SOP_PRIME << 28) | (buf[1] << 8) | buf[0];
 	zassert_equal(exp_head, head,
-		      "Received header 0x%08lx, expected 0x%08lx",
-		      head, exp_head);
+		      "Received header 0x%08lx, expected 0x%08lx", head,
+		      exp_head);
 	zassert_mem_equal(payload, buf + 2, size, NULL);
 }
 
 /** Test TCPCI transmitting message from TCPC */
-void test_tcpci_transmit(const struct emul *emul, enum usbc_port port)
+void test_tcpci_transmit(const struct emul *emul,
+			 struct i2c_common_emul_data *common_data,
+			 enum usbc_port port)
 {
 	const struct tcpm_drv *drv = tcpc_config[port].drv;
-	struct i2c_emul *i2c_emul = tcpci_emul_get_i2c_emul(emul);
 	struct tcpci_emul_msg *msg;
 	uint32_t data[6];
 	uint16_t header;
@@ -551,31 +566,30 @@ void test_tcpci_transmit(const struct emul *emul, enum usbc_port port)
 	}
 
 	/* Test transmit hard reset fail */
-	i2c_common_emul_set_write_fail_reg(i2c_emul, TCPC_REG_TRANSMIT);
+	i2c_common_emul_set_write_fail_reg(common_data, TCPC_REG_TRANSMIT);
 	zassert_equal(EC_ERROR_INVAL,
 		      drv->transmit(port, TCPCI_MSG_TX_HARD_RESET, 0, NULL),
 		      NULL);
-	i2c_common_emul_set_write_fail_reg(i2c_emul,
+	i2c_common_emul_set_write_fail_reg(common_data,
 					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test transmit cabel reset */
 	zassert_equal(EC_SUCCESS,
 		      drv->transmit(port, TCPCI_MSG_CABLE_RESET, 0, NULL),
 		      NULL);
-	zassert_equal(TCPCI_MSG_CABLE_RESET, msg->type, NULL);
+	zassert_equal(TCPCI_MSG_CABLE_RESET, msg->sop_type, NULL);
 
 	/* Test transmit hard reset */
 	zassert_equal(EC_SUCCESS,
 		      drv->transmit(port, TCPCI_MSG_TX_HARD_RESET, 0, NULL),
 		      NULL);
-	zassert_equal(TCPCI_MSG_TX_HARD_RESET, msg->type, NULL);
+	zassert_equal(TCPCI_MSG_TX_HARD_RESET, msg->sop_type, NULL);
 
 	/* Test transmit fail on rx buffer */
-	i2c_common_emul_set_write_fail_reg(i2c_emul, TCPC_REG_TX_BUFFER);
+	i2c_common_emul_set_write_fail_reg(common_data, TCPC_REG_TX_BUFFER);
 	zassert_equal(EC_ERROR_INVAL,
-		      drv->transmit(port, TCPCI_MSG_SOP_PRIME, 0, data),
-		      NULL);
-	i2c_common_emul_set_write_fail_reg(i2c_emul,
+		      drv->transmit(port, TCPCI_MSG_SOP_PRIME, 0, data), NULL);
+	i2c_common_emul_set_write_fail_reg(common_data,
 					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test transmit only header */
@@ -585,7 +599,7 @@ void test_tcpci_transmit(const struct emul *emul, enum usbc_port port)
 	zassert_equal(EC_SUCCESS,
 		      drv->transmit(port, TCPCI_MSG_SOP_PRIME, header, data),
 		      NULL);
-	zassert_equal(TCPCI_MSG_SOP_PRIME, msg->type, NULL);
+	zassert_equal(TCPCI_MSG_SOP_PRIME, msg->sop_type, NULL);
 	zassert_mem_equal(msg->buf, &header, 2, NULL);
 	zassert_equal(2, msg->cnt, NULL);
 
@@ -596,25 +610,23 @@ void test_tcpci_transmit(const struct emul *emul, enum usbc_port port)
 	zassert_equal(EC_SUCCESS,
 		      drv->transmit(port, TCPCI_MSG_SOP_PRIME, header, data),
 		      NULL);
-	zassert_equal(TCPCI_MSG_SOP_PRIME, msg->type, NULL);
+	zassert_equal(TCPCI_MSG_SOP_PRIME, msg->sop_type, NULL);
 	zassert_mem_equal(msg->buf, &header, 2, NULL);
 	zassert_mem_equal(msg->buf + 2, data, 6 * sizeof(uint32_t), NULL);
 	zassert_equal(2 + 6 * sizeof(uint32_t), msg->cnt, NULL);
 }
 
 /** Test TCPCI alert */
-void test_tcpci_alert(const struct emul *emul, enum usbc_port port)
+void test_tcpci_alert(const struct emul *emul,
+		      struct i2c_common_emul_data *common_data,
+		      enum usbc_port port)
 {
 	const struct tcpm_drv *drv = tcpc_config[port].drv;
-	struct i2c_emul *i2c_emul = tcpci_emul_get_i2c_emul(emul);
-
-	tcpc_config[port].flags = TCPC_FLAGS_TCPCI_REV2_0;
-	tcpci_emul_set_rev(emul, TCPCI_EMUL_REV2_0_VER1_1);
 
 	/* Test alert read fail */
-	i2c_common_emul_set_read_fail_reg(i2c_emul, TCPC_REG_ALERT);
+	i2c_common_emul_set_read_fail_reg(common_data, TCPC_REG_ALERT);
 	drv->tcpc_alert(port);
-	i2c_common_emul_set_read_fail_reg(i2c_emul,
+	i2c_common_emul_set_read_fail_reg(common_data,
 					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Handle overcurrent */
@@ -650,7 +662,9 @@ void test_tcpci_alert(const struct emul *emul, enum usbc_port port)
 }
 
 /** Test TCPCI alert RX message */
-void test_tcpci_alert_rx_message(const struct emul *emul, enum usbc_port port)
+void test_tcpci_alert_rx_message(const struct emul *emul,
+				 struct i2c_common_emul_data *common_data,
+				 enum usbc_port port)
 {
 	const struct tcpm_drv *drv = tcpc_config[port].drv;
 	struct tcpci_emul_msg msg1, msg2;
@@ -660,8 +674,6 @@ void test_tcpci_alert_rx_message(const struct emul *emul, enum usbc_port port)
 	int i, head;
 	int size;
 
-	tcpc_config[port].flags = TCPC_FLAGS_TCPCI_REV2_0;
-	tcpci_emul_set_rev(emul, TCPCI_EMUL_REV2_0_VER1_1);
 	tcpci_emul_set_reg(emul, TCPC_REG_DEV_CAP_2,
 			   TCPC_REG_DEV_CAP_2_LONG_MSG);
 	tcpci_emul_set_reg(emul, TCPC_REG_RX_DETECT,
@@ -674,11 +686,11 @@ void test_tcpci_alert_rx_message(const struct emul *emul, enum usbc_port port)
 	size = 23;
 	msg1.buf = buf1;
 	msg1.cnt = size + 3;
-	msg1.type = TCPCI_MSG_SOP;
+	msg1.sop_type = TCPCI_MSG_SOP;
 
 	msg2.buf = buf2;
 	msg2.cnt = size + 3;
-	msg2.type = TCPCI_MSG_SOP_PRIME;
+	msg2.sop_type = TCPCI_MSG_SOP_PRIME;
 
 	/* Test receiving one message */
 	zassert_equal(TCPCI_EMUL_TX_SUCCESS,
@@ -693,8 +705,8 @@ void test_tcpci_alert_rx_message(const struct emul *emul, enum usbc_port port)
 		      NULL);
 	exp_head = (TCPCI_MSG_SOP << 28) | (buf1[1] << 8) | buf1[0];
 	zassert_equal(exp_head, head,
-		      "Received header 0x%08lx, expected 0x%08lx",
-		      head, exp_head);
+		      "Received header 0x%08lx, expected 0x%08lx", head,
+		      exp_head);
 	zassert_mem_equal(payload, buf1 + 2, size, NULL);
 	zassert_false(tcpm_has_pending_message(port), NULL);
 
@@ -714,8 +726,8 @@ void test_tcpci_alert_rx_message(const struct emul *emul, enum usbc_port port)
 		      NULL);
 	exp_head = (TCPCI_MSG_SOP << 28) | (buf1[1] << 8) | buf1[0];
 	zassert_equal(exp_head, head,
-		      "Received header 0x%08lx, expected 0x%08lx",
-		      head, exp_head);
+		      "Received header 0x%08lx, expected 0x%08lx", head,
+		      exp_head);
 	zassert_mem_equal(payload, buf1 + 2, size, NULL);
 	/* Check if msg2 is in queue */
 	zassert_true(tcpm_has_pending_message(port), NULL);
@@ -723,8 +735,8 @@ void test_tcpci_alert_rx_message(const struct emul *emul, enum usbc_port port)
 		      NULL);
 	exp_head = (TCPCI_MSG_SOP_PRIME << 28) | (buf2[1] << 8) | buf2[0];
 	zassert_equal(exp_head, head,
-		      "Received header 0x%08lx, expected 0x%08lx",
-		      head, exp_head);
+		      "Received header 0x%08lx, expected 0x%08lx", head,
+		      exp_head);
 	zassert_mem_equal(payload, buf2 + 2, size, NULL);
 	zassert_false(tcpm_has_pending_message(port), NULL);
 
@@ -747,8 +759,8 @@ void test_tcpci_alert_rx_message(const struct emul *emul, enum usbc_port port)
 		      NULL);
 	exp_head = (TCPCI_MSG_SOP_PRIME << 28) | (buf2[1] << 8) | buf2[0];
 	zassert_equal(exp_head, head,
-		      "Received header 0x%08lx, expected 0x%08lx",
-		      head, exp_head);
+		      "Received header 0x%08lx, expected 0x%08lx", head,
+		      exp_head);
 	zassert_mem_equal(payload, buf2 + 2, size, NULL);
 	zassert_false(tcpm_has_pending_message(port), NULL);
 
@@ -774,8 +786,8 @@ void test_tcpci_alert_rx_message(const struct emul *emul, enum usbc_port port)
 		zassert_equal(EC_SUCCESS,
 			      tcpm_dequeue_message(port, payload, &head), NULL);
 		zassert_equal(exp_head, head,
-			      "Received header 0x%08lx, expected 0x%08lx",
-			      head, exp_head);
+			      "Received header 0x%08lx, expected 0x%08lx", head,
+			      exp_head);
 		zassert_mem_equal(payload, buf1 + 2, size, NULL);
 	}
 	tcpm_clear_pending_messages(port);
@@ -791,14 +803,16 @@ void test_tcpci_alert_rx_message(const struct emul *emul, enum usbc_port port)
 		      NULL);
 	exp_head = (TCPCI_MSG_SOP << 28) | (buf1[1] << 8) | buf1[0];
 	zassert_equal(exp_head, head,
-		      "Received header 0x%08lx, expected 0x%08lx",
-		      head, exp_head);
+		      "Received header 0x%08lx, expected 0x%08lx", head,
+		      exp_head);
 	zassert_mem_equal(payload, buf1 + 2, size, NULL);
 	zassert_false(tcpm_has_pending_message(port), NULL);
 }
 
 /** Test TCPCI auto discharge on disconnect */
-void test_tcpci_auto_discharge(const struct emul *emul, enum usbc_port port)
+void test_tcpci_auto_discharge(const struct emul *emul,
+			       struct i2c_common_emul_data *common_data,
+			       enum usbc_port port)
 {
 	const struct tcpm_drv *drv = tcpc_config[port].drv;
 	uint8_t initial_ctrl;
@@ -822,28 +836,25 @@ void test_tcpci_auto_discharge(const struct emul *emul, enum usbc_port port)
 }
 
 /** Test TCPCI drp toggle */
-void test_tcpci_drp_toggle(const struct emul *emul, enum usbc_port port)
+void test_tcpci_drp_toggle(const struct emul *emul,
+			   struct i2c_common_emul_data *common_data,
+			   enum usbc_port port)
 {
 	const struct tcpm_drv *drv = tcpc_config[port].drv;
-	struct i2c_emul *i2c_emul = tcpci_emul_get_i2c_emul(emul);
 	uint8_t exp_tcpc_ctrl, exp_role_ctrl, initial_tcpc_ctrl;
 
-	/* Set TCPCI to revision 2 */
-	tcpc_config[port].flags = TCPC_FLAGS_TCPCI_REV2_0;
-	tcpci_emul_set_rev(emul, TCPCI_EMUL_REV2_0_VER1_1);
-
 	/* Test error on failed role CTRL set */
-	i2c_common_emul_set_write_fail_reg(i2c_emul, TCPC_REG_ROLE_CTRL);
+	i2c_common_emul_set_write_fail_reg(common_data, TCPC_REG_ROLE_CTRL);
 	zassert_equal(EC_ERROR_INVAL, drv->drp_toggle(port), NULL);
 
 	/* Test error on failed TCPC CTRL set */
-	i2c_common_emul_set_write_fail_reg(i2c_emul, TCPC_REG_TCPC_CTRL);
+	i2c_common_emul_set_write_fail_reg(common_data, TCPC_REG_TCPC_CTRL);
 	zassert_equal(EC_ERROR_INVAL, drv->drp_toggle(port), NULL);
 
 	/* Test error on failed command set */
-	i2c_common_emul_set_write_fail_reg(i2c_emul, TCPC_REG_COMMAND);
+	i2c_common_emul_set_write_fail_reg(common_data, TCPC_REG_COMMAND);
 	zassert_equal(EC_ERROR_INVAL, drv->drp_toggle(port), NULL);
-	i2c_common_emul_set_write_fail_reg(i2c_emul,
+	i2c_common_emul_set_write_fail_reg(common_data,
 					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Set initial value for TCPC ctrl register. Chosen arbitrary. */
@@ -891,25 +902,26 @@ void test_tcpci_drp_toggle(const struct emul *emul, enum usbc_port port)
 }
 
 /** Test TCPCI get chip info */
-void test_tcpci_get_chip_info(const struct emul *emul, enum usbc_port port)
+void test_tcpci_get_chip_info(const struct emul *emul,
+			      struct i2c_common_emul_data *common_data,
+			      enum usbc_port port)
 {
 	const struct tcpm_drv *drv = tcpc_config[port].drv;
-	struct i2c_emul *i2c_emul = tcpci_emul_get_i2c_emul(emul);
 	struct ec_response_pd_chip_info_v1 info;
 	uint16_t vendor, product, bcd;
 
 	/* Test error on failed vendor id get */
-	i2c_common_emul_set_read_fail_reg(i2c_emul, TCPC_REG_VENDOR_ID);
+	i2c_common_emul_set_read_fail_reg(common_data, TCPC_REG_VENDOR_ID);
 	zassert_equal(EC_ERROR_INVAL, drv->get_chip_info(port, 1, &info), NULL);
 
 	/* Test error on failed product id get */
-	i2c_common_emul_set_read_fail_reg(i2c_emul, TCPC_REG_PRODUCT_ID);
+	i2c_common_emul_set_read_fail_reg(common_data, TCPC_REG_PRODUCT_ID);
 	zassert_equal(EC_ERROR_INVAL, drv->get_chip_info(port, 1, &info), NULL);
 
 	/* Test error on failed BCD get */
-	i2c_common_emul_set_read_fail_reg(i2c_emul, TCPC_REG_VENDOR_ID);
+	i2c_common_emul_set_read_fail_reg(common_data, TCPC_REG_VENDOR_ID);
 	zassert_equal(EC_ERROR_INVAL, drv->get_chip_info(port, 1, &info), NULL);
-	i2c_common_emul_set_read_fail_reg(i2c_emul,
+	i2c_common_emul_set_read_fail_reg(common_data,
 					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test reading chip info. Values chosen arbitrary. */
@@ -929,10 +941,10 @@ void test_tcpci_get_chip_info(const struct emul *emul, enum usbc_port port)
 	info.product_id = 0;
 	info.device_id = 0;
 	/* Make sure, that TCPC is not accessed */
-	i2c_common_emul_set_read_fail_reg(i2c_emul,
+	i2c_common_emul_set_read_fail_reg(common_data,
 					  I2C_COMMON_EMUL_FAIL_ALL_REG);
 	zassert_equal(EC_SUCCESS, drv->get_chip_info(port, 0, &info), NULL);
-	i2c_common_emul_set_read_fail_reg(i2c_emul,
+	i2c_common_emul_set_read_fail_reg(common_data,
 					  I2C_COMMON_EMUL_NO_FAIL_REG);
 	zassert_equal(vendor, info.vendor_id, NULL);
 	zassert_equal(product, info.product_id, NULL);
@@ -940,15 +952,16 @@ void test_tcpci_get_chip_info(const struct emul *emul, enum usbc_port port)
 }
 
 /** Test TCPCI enter low power mode */
-void test_tcpci_low_power_mode(const struct emul *emul, enum usbc_port port)
+void test_tcpci_low_power_mode(const struct emul *emul,
+			       struct i2c_common_emul_data *common_data,
+			       enum usbc_port port)
 {
 	const struct tcpm_drv *drv = tcpc_config[port].drv;
-	struct i2c_emul *i2c_emul = tcpci_emul_get_i2c_emul(emul);
 
 	/* Test error on failed command set */
-	i2c_common_emul_set_write_fail_reg(i2c_emul, TCPC_REG_COMMAND);
+	i2c_common_emul_set_write_fail_reg(common_data, TCPC_REG_COMMAND);
 	zassert_equal(EC_ERROR_INVAL, drv->enter_low_power_mode(port), NULL);
-	i2c_common_emul_set_write_fail_reg(i2c_emul,
+	i2c_common_emul_set_write_fail_reg(common_data,
 					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test correct command is issued */
@@ -957,21 +970,22 @@ void test_tcpci_low_power_mode(const struct emul *emul, enum usbc_port port)
 }
 
 /** Test TCPCI set bist test mode */
-void test_tcpci_set_bist_mode(const struct emul *emul, enum usbc_port port)
+void test_tcpci_set_bist_mode(const struct emul *emul,
+			      struct i2c_common_emul_data *common_data,
+			      enum usbc_port port)
 {
 	const struct tcpm_drv *drv = tcpc_config[port].drv;
-	struct i2c_emul *i2c_emul = tcpci_emul_get_i2c_emul(emul);
 	uint16_t exp_mask, initial_mask;
 	uint8_t exp_ctrl, initial_ctrl;
 
 	/* Test error on TCPC CTRL set */
-	i2c_common_emul_set_write_fail_reg(i2c_emul, TCPC_REG_TCPC_CTRL);
+	i2c_common_emul_set_write_fail_reg(common_data, TCPC_REG_TCPC_CTRL);
 	zassert_equal(EC_ERROR_INVAL, drv->set_bist_test_mode(port, 1), NULL);
 
 	/* Test error on alert mask set */
-	i2c_common_emul_set_write_fail_reg(i2c_emul, TCPC_REG_ALERT_MASK);
+	i2c_common_emul_set_write_fail_reg(common_data, TCPC_REG_ALERT_MASK);
 	zassert_equal(EC_ERROR_INVAL, drv->set_bist_test_mode(port, 1), NULL);
-	i2c_common_emul_set_write_fail_reg(i2c_emul,
+	i2c_common_emul_set_write_fail_reg(common_data,
 					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Set initial value for alert mask register. Chosen arbitrary. */
@@ -997,3 +1011,20 @@ void test_tcpci_set_bist_mode(const struct emul *emul, enum usbc_port port)
 	check_tcpci_reg(emul, TCPC_REG_TCPC_CTRL, exp_ctrl);
 	check_tcpci_reg(emul, TCPC_REG_ALERT_MASK, exp_mask);
 }
+
+void test_tcpci_hard_reset_reinit(const struct emul *emul,
+				  struct i2c_common_emul_data *common_data,
+				  enum usbc_port port)
+{
+	const struct tcpm_drv *drv = tcpc_config[port].drv;
+	uint16_t power_status_mask;
+	uint16_t alert_mask;
+
+	zassume_equal(EC_SUCCESS, drv->init(port), NULL);
+	tcpci_emul_get_reg(emul, TCPC_REG_POWER_STATUS_MASK,
+			   &power_status_mask);
+	tcpci_emul_get_reg(emul, TCPC_REG_ALERT_MASK, &alert_mask);
+	zassert_ok(tcpci_hard_reset_reinit(USBC_PORT_C0), NULL);
+	check_tcpci_reg(emul, TCPC_REG_POWER_STATUS_MASK, power_status_mask);
+	check_tcpci_reg(emul, TCPC_REG_ALERT_MASK, alert_mask);
+}
diff --git a/zephyr/test/drivers/src/tcs3400.c b/zephyr/test/drivers/default/src/tcs3400.c
index 66955481f7..860b069532 100644
--- a/zephyr/test/drivers/src/tcs3400.c
+++ b/zephyr/test/drivers/default/src/tcs3400.c
@@ -1,10 +1,10 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <zephyr/zephyr.h>
-#include <ztest.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
 
 #include "common.h"
 #include "i2c.h"
@@ -16,22 +16,23 @@
 #include "driver/als_tcs3400.h"
 #include "test/drivers/test_state.h"
 
-#define TCS_ORD			DT_DEP_ORD(DT_NODELABEL(tcs_emul))
-#define TCS_CLR_SENSOR_ID	SENSOR_ID(DT_NODELABEL(tcs3400_clear))
-#define TCS_RGB_SENSOR_ID	SENSOR_ID(DT_NODELABEL(tcs3400_rgb))
-#define TCS_INT_EVENT		\
+#define TCS_NODE DT_NODELABEL(tcs_emul)
+#define TCS_CLR_SENSOR_ID SENSOR_ID(DT_NODELABEL(tcs3400_clear))
+#define TCS_RGB_SENSOR_ID SENSOR_ID(DT_NODELABEL(tcs3400_rgb))
+#define TCS_INT_EVENT \
 	TASK_EVENT_MOTION_SENSOR_INTERRUPT(SENSOR_ID(DT_ALIAS(tcs3400_int)))
 
 /** How accurate comparision of rgb sensors should be */
-#define V_EPS		8
+#define V_EPS 8
 
 /** Test initialization of light sensor driver and device */
 ZTEST_USER(tcs3400, test_tcs_init)
 {
 	struct motion_sensor_t *ms, *ms_rgb;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(TCS_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcs3400_get_i2c_common_data(emul);
 
-	emul = tcs_emul_get(TCS_ORD);
 	ms = &motion_sensors[TCS_CLR_SENSOR_ID];
 	ms_rgb = &motion_sensors[TCS_RGB_SENSOR_ID];
 
@@ -39,9 +40,11 @@ ZTEST_USER(tcs3400, test_tcs_init)
 	zassert_equal(EC_SUCCESS, ms_rgb->drv->init(ms_rgb), NULL);
 
 	/* Fail init on communication errors */
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_FAIL_ALL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_FAIL_ALL_REG);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->init(ms), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Fail on bad ID */
 	tcs_emul_set_reg(emul, TCS_I2C_ID, 0);
@@ -52,8 +55,8 @@ ZTEST_USER(tcs3400, test_tcs_init)
 
 	/* Test successful init. ATIME and AGAIN should be changed on init */
 	zassert_equal(EC_SUCCESS, ms->drv->init(ms), NULL);
-	zassert_equal(TCS_DEFAULT_ATIME,
-		      tcs_emul_get_reg(emul, TCS_I2C_ATIME), NULL);
+	zassert_equal(TCS_DEFAULT_ATIME, tcs_emul_get_reg(emul, TCS_I2C_ATIME),
+		      NULL);
 	zassert_equal(TCS_DEFAULT_AGAIN,
 		      tcs_emul_get_reg(emul, TCS_I2C_CONTROL), NULL);
 }
@@ -62,21 +65,23 @@ ZTEST_USER(tcs3400, test_tcs_init)
 ZTEST_USER(tcs3400, test_tcs_read)
 {
 	struct motion_sensor_t *ms;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(TCS_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcs3400_get_i2c_common_data(emul);
 	uint8_t enable;
 	intv3_t v;
 
-	emul = tcs_emul_get(TCS_ORD);
 	ms = &motion_sensors[TCS_CLR_SENSOR_ID];
 
 	/* Test error on writing registers */
-	i2c_common_emul_set_write_fail_reg(emul, TCS_I2C_ATIME);
+	i2c_common_emul_set_write_fail_reg(common_data, TCS_I2C_ATIME);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, v), NULL);
-	i2c_common_emul_set_write_fail_reg(emul, TCS_I2C_CONTROL);
+	i2c_common_emul_set_write_fail_reg(common_data, TCS_I2C_CONTROL);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, v), NULL);
-	i2c_common_emul_set_write_fail_reg(emul, TCS_I2C_ENABLE);
+	i2c_common_emul_set_write_fail_reg(common_data, TCS_I2C_ENABLE);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->read(ms, v), NULL);
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test starting read with calibration */
 	tcs_emul_set_reg(emul, TCS_I2C_ATIME, 0);
@@ -132,8 +137,7 @@ static void check_fifo_empty_f(struct motion_sensor_t *ms,
 		}
 	}
 }
-#define check_fifo_empty(ms, ms_rgb)		\
-	check_fifo_empty_f(ms, ms_rgb, __LINE__)
+#define check_fifo_empty(ms, ms_rgb) check_fifo_empty_f(ms, ms_rgb, __LINE__)
 
 /**
  * Test different conditions where irq handler fail or commit no data
@@ -142,10 +146,11 @@ static void check_fifo_empty_f(struct motion_sensor_t *ms,
 ZTEST_USER(tcs3400, test_tcs_irq_handler_fail)
 {
 	struct motion_sensor_t *ms, *ms_rgb;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(TCS_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcs3400_get_i2c_common_data(emul);
 	uint32_t event;
 
-	emul = tcs_emul_get(TCS_ORD);
 	ms = &motion_sensors[TCS_CLR_SENSOR_ID];
 	ms_rgb = &motion_sensors[TCS_RGB_SENSOR_ID];
 
@@ -157,15 +162,17 @@ ZTEST_USER(tcs3400, test_tcs_irq_handler_fail)
 
 	event = TCS_INT_EVENT;
 	/* Test error on reading status */
-	i2c_common_emul_set_read_fail_reg(emul, TCS_I2C_STATUS);
+	i2c_common_emul_set_read_fail_reg(common_data, TCS_I2C_STATUS);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->irq_handler(ms, &event), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 	check_fifo_empty(ms, ms_rgb);
 
 	/* Test fail on changing device power state */
-	i2c_common_emul_set_write_fail_reg(emul, TCS_I2C_ENABLE);
+	i2c_common_emul_set_write_fail_reg(common_data, TCS_I2C_ENABLE);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->irq_handler(ms, &event), NULL);
-	i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_write_fail_reg(common_data,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
 	check_fifo_empty(ms, ms_rgb);
 
 	/* Test that no data is committed when status is 0 */
@@ -179,12 +186,12 @@ ZTEST_USER(tcs3400, test_tcs_irq_handler_fail)
  * expected value.
  */
 static void check_fifo_f(struct motion_sensor_t *ms,
-			 struct motion_sensor_t *ms_rgb,
-			 int *exp_v, int eps, int line)
+			 struct motion_sensor_t *ms_rgb, int *exp_v, int eps,
+			 int line)
 {
 	struct ec_response_motion_sensor_data vector;
 	uint16_t size;
-	int ret_v[4] = {-1, -1, -1, -1};
+	int ret_v[4] = { -1, -1, -1, -1 };
 	int i;
 
 	/* Read all data committed to FIFO */
@@ -217,26 +224,26 @@ static void check_fifo_f(struct motion_sensor_t *ms,
 
 	/* Compare with last committed data */
 	for (i = 0; i < 4; i++) {
-		zassert_within(exp_v[i], ret_v[i], eps,
+		zassert_within(
+			exp_v[i], ret_v[i], eps,
 			"Expected [%d; %d; %d; %d], got [%d; %d; %d; %d]; line: %d",
-			exp_v[0], exp_v[1], exp_v[2], exp_v[3],
-			ret_v[0], ret_v[1], ret_v[2], ret_v[3], line);
+			exp_v[0], exp_v[1], exp_v[2], exp_v[3], ret_v[0],
+			ret_v[1], ret_v[2], ret_v[3], line);
 	}
 }
-#define check_fifo(ms, ms_rgb, exp_v, eps)		\
+#define check_fifo(ms, ms_rgb, exp_v, eps) \
 	check_fifo_f(ms, ms_rgb, exp_v, eps, __LINE__)
 
 /** Test calibration mode reading of light sensor values */
 ZTEST_USER(tcs3400, test_tcs_read_calibration)
 {
 	struct motion_sensor_t *ms, *ms_rgb;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(TCS_NODE);
 	uint32_t event = TCS_INT_EVENT;
 	int emul_v[4];
 	int exp_v[4];
 	intv3_t v;
 
-	emul = tcs_emul_get(TCS_ORD);
 	ms = &motion_sensors[TCS_CLR_SENSOR_ID];
 	ms_rgb = &motion_sensors[TCS_RGB_SENSOR_ID];
 
@@ -304,7 +311,7 @@ ZTEST_USER(tcs3400, test_tcs_read_calibration)
  * First element of expected vector is updated by this function.
  */
 static void set_emul_val_from_exp(int *exp_v, uint16_t *scale,
-				  struct i2c_emul *emul)
+				  const struct emul *emul)
 {
 	int emul_v[4];
 	int ir;
@@ -342,31 +349,24 @@ static void set_emul_val_from_exp(int *exp_v, uint16_t *scale,
 ZTEST_USER(tcs3400, test_tcs_read_xyz)
 {
 	struct motion_sensor_t *ms, *ms_rgb;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(TCS_NODE);
 	uint32_t event = TCS_INT_EVENT;
 	/* Expected data to test: IR, R, G, B */
 	int exp_v[][4] = {
-		{200,	1110,	870,	850},
-		{300,	1110,	10000,	8500},
-		{600,	50000,	40000,	30000},
-		{1000,	3000,	40000,	2000},
-		{1000,	65000,	65000,	65000},
-		{100,	214,	541,	516},
-		{143,	2141,	5414,	5163},
-		{100,	50000,	40000,	30000},
-		{1430,	2141,	5414,	5163},
-		{10000,	50000,	40000,	30000},
-		{10000,	214,	541,	516},
-		{15000,	50000,	40000,	30000},
-	};
-	uint16_t scale[4] = {
-		MOTION_SENSE_DEFAULT_SCALE, MOTION_SENSE_DEFAULT_SCALE,
-		MOTION_SENSE_DEFAULT_SCALE, MOTION_SENSE_DEFAULT_SCALE
+		{ 200, 1110, 870, 850 },       { 300, 1110, 10000, 8500 },
+		{ 600, 50000, 40000, 30000 },  { 1000, 3000, 40000, 2000 },
+		{ 1000, 65000, 65000, 65000 }, { 100, 214, 541, 516 },
+		{ 143, 2141, 5414, 5163 },     { 100, 50000, 40000, 30000 },
+		{ 1430, 2141, 5414, 5163 },    { 10000, 50000, 40000, 30000 },
+		{ 10000, 214, 541, 516 },      { 15000, 50000, 40000, 30000 },
 	};
+	uint16_t scale[4] = { MOTION_SENSE_DEFAULT_SCALE,
+			      MOTION_SENSE_DEFAULT_SCALE,
+			      MOTION_SENSE_DEFAULT_SCALE,
+			      MOTION_SENSE_DEFAULT_SCALE };
 	int i, test;
 	intv3_t v;
 
-	emul = tcs_emul_get(TCS_ORD);
 	ms = &motion_sensors[TCS_CLR_SENSOR_ID];
 	ms_rgb = &motion_sensors[TCS_RGB_SENSOR_ID];
 
@@ -420,45 +420,42 @@ ZTEST_USER(tcs3400, test_tcs_read_xyz)
 ZTEST_USER(tcs3400, test_tcs_scale)
 {
 	struct motion_sensor_t *ms, *ms_rgb;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(TCS_NODE);
 	uint32_t event = TCS_INT_EVENT;
 	/* Expected data to test: IR, R, G, B */
 	int exp_v[][4] = {
-		{200,	1110,	870,	850},
-		{300,	1110,	10000,	8500},
-		{600,	5000,	4000,	3000},
-		{100,	3000,	4000,	2000},
-		{100,	1000,	1000,	1000},
+		{ 200, 1110, 870, 850 },   { 300, 1110, 10000, 8500 },
+		{ 600, 5000, 4000, 3000 }, { 100, 3000, 4000, 2000 },
+		{ 100, 1000, 1000, 1000 },
 	};
 	/* Scale for each test */
 	uint16_t exp_scale[][4] = {
-		{MOTION_SENSE_DEFAULT_SCALE, MOTION_SENSE_DEFAULT_SCALE,
-		 MOTION_SENSE_DEFAULT_SCALE, MOTION_SENSE_DEFAULT_SCALE},
-		{MOTION_SENSE_DEFAULT_SCALE + 300,
-		 MOTION_SENSE_DEFAULT_SCALE + 300,
-		 MOTION_SENSE_DEFAULT_SCALE + 300,
-		 MOTION_SENSE_DEFAULT_SCALE + 300},
-		{MOTION_SENSE_DEFAULT_SCALE - 300,
-		 MOTION_SENSE_DEFAULT_SCALE - 300,
-		 MOTION_SENSE_DEFAULT_SCALE - 300,
-		 MOTION_SENSE_DEFAULT_SCALE - 300},
-		{MOTION_SENSE_DEFAULT_SCALE + 345,
-		 MOTION_SENSE_DEFAULT_SCALE - 5423,
-		 MOTION_SENSE_DEFAULT_SCALE - 30,
-		 MOTION_SENSE_DEFAULT_SCALE + 400},
-		{MOTION_SENSE_DEFAULT_SCALE - 345,
-		 MOTION_SENSE_DEFAULT_SCALE + 5423,
-		 MOTION_SENSE_DEFAULT_SCALE + 30,
-		 MOTION_SENSE_DEFAULT_SCALE - 400},
-		{MOTION_SENSE_DEFAULT_SCALE, MOTION_SENSE_DEFAULT_SCALE,
-		 MOTION_SENSE_DEFAULT_SCALE, MOTION_SENSE_DEFAULT_SCALE}
+		{ MOTION_SENSE_DEFAULT_SCALE, MOTION_SENSE_DEFAULT_SCALE,
+		  MOTION_SENSE_DEFAULT_SCALE, MOTION_SENSE_DEFAULT_SCALE },
+		{ MOTION_SENSE_DEFAULT_SCALE + 300,
+		  MOTION_SENSE_DEFAULT_SCALE + 300,
+		  MOTION_SENSE_DEFAULT_SCALE + 300,
+		  MOTION_SENSE_DEFAULT_SCALE + 300 },
+		{ MOTION_SENSE_DEFAULT_SCALE - 300,
+		  MOTION_SENSE_DEFAULT_SCALE - 300,
+		  MOTION_SENSE_DEFAULT_SCALE - 300,
+		  MOTION_SENSE_DEFAULT_SCALE - 300 },
+		{ MOTION_SENSE_DEFAULT_SCALE + 345,
+		  MOTION_SENSE_DEFAULT_SCALE - 5423,
+		  MOTION_SENSE_DEFAULT_SCALE - 30,
+		  MOTION_SENSE_DEFAULT_SCALE + 400 },
+		{ MOTION_SENSE_DEFAULT_SCALE - 345,
+		  MOTION_SENSE_DEFAULT_SCALE + 5423,
+		  MOTION_SENSE_DEFAULT_SCALE + 30,
+		  MOTION_SENSE_DEFAULT_SCALE - 400 },
+		{ MOTION_SENSE_DEFAULT_SCALE, MOTION_SENSE_DEFAULT_SCALE,
+		  MOTION_SENSE_DEFAULT_SCALE, MOTION_SENSE_DEFAULT_SCALE }
 	};
 	uint16_t scale[3];
 	int16_t temp;
 	int i, test;
 	intv3_t v;
 
-	emul = tcs_emul_get(TCS_ORD);
 	ms = &motion_sensors[TCS_CLR_SENSOR_ID];
 	ms_rgb = &motion_sensors[TCS_RGB_SENSOR_ID];
 
@@ -476,16 +473,16 @@ ZTEST_USER(tcs3400, test_tcs_scale)
 		zassert_equal(EC_SUCCESS,
 			      ms->drv->set_scale(ms, exp_scale[test], 0),
 			      "test %d", test);
-		zassert_equal(EC_SUCCESS,
-			      ms->drv->get_scale(ms, scale, &temp),
+		zassert_equal(EC_SUCCESS, ms->drv->get_scale(ms, scale, &temp),
 			      "test %d", test);
 		zassert_equal((int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP, temp,
 			      "test %d, %d", test, temp);
 		zassert_equal(exp_scale[test][0], scale[0], "test %d", test);
 
 		/* Set and test RGB sensor scale */
-		zassert_equal(EC_SUCCESS, ms_rgb->drv->set_scale(ms_rgb,
-						&(exp_scale[test][1]), 0),
+		zassert_equal(EC_SUCCESS,
+			      ms_rgb->drv->set_scale(ms_rgb,
+						     &(exp_scale[test][1]), 0),
 			      "test %d", test);
 		zassert_equal(EC_SUCCESS,
 			      ms_rgb->drv->get_scale(ms_rgb, scale, &temp),
@@ -532,21 +529,23 @@ ZTEST_USER(tcs3400, test_tcs_scale)
 ZTEST_USER(tcs3400, test_tcs_data_rate)
 {
 	struct motion_sensor_t *ms, *ms_rgb;
-	struct i2c_emul *emul;
+	const struct emul *emul = EMUL_DT_GET(TCS_NODE);
+	struct i2c_common_emul_data *common_data =
+		emul_tcs3400_get_i2c_common_data(emul);
 	uint8_t enable;
 
-	emul = tcs_emul_get(TCS_ORD);
 	ms = &motion_sensors[TCS_CLR_SENSOR_ID];
 	/* RGB sensor doesn't set rate, but return rate of clear sesnor */
 	ms_rgb = &motion_sensors[TCS_RGB_SENSOR_ID];
 
 	/* Test fail on reading device power state */
-	i2c_common_emul_set_read_fail_reg(emul, TCS_I2C_ENABLE);
+	i2c_common_emul_set_read_fail_reg(common_data, TCS_I2C_ENABLE);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 0, 0), NULL);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 0, 1), NULL);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 100, 0), NULL);
 	zassert_equal(EC_ERROR_INVAL, ms->drv->set_data_rate(ms, 100, 1), NULL);
-	i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG);
+	i2c_common_emul_set_read_fail_reg(common_data,
+					  I2C_COMMON_EMUL_NO_FAIL_REG);
 
 	/* Test setting 0 rate disables device */
 	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, 0, 0), NULL);
@@ -560,7 +559,6 @@ ZTEST_USER(tcs3400, test_tcs_data_rate)
 	zassert_equal(0, ms->drv->get_data_rate(ms), NULL);
 	zassert_equal(0, ms_rgb->drv->get_data_rate(ms_rgb), NULL);
 
-
 	/* Test setting non-zero rate enables device */
 	zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, 100, 0), NULL);
 	enable = tcs_emul_get_reg(emul, TCS_I2C_ENABLE);
@@ -594,9 +592,7 @@ ZTEST_USER(tcs3400, test_tcs_data_rate)
 ZTEST_USER(tcs3400, test_tcs_set_range)
 {
 	struct motion_sensor_t *ms, *ms_rgb;
-	struct i2c_emul *emul;
 
-	emul = tcs_emul_get(TCS_ORD);
 	ms = &motion_sensors[TCS_CLR_SENSOR_ID];
 	ms_rgb = &motion_sensors[TCS_RGB_SENSOR_ID];
 
@@ -611,4 +607,35 @@ ZTEST_USER(tcs3400, test_tcs_set_range)
 	zassert_equal(0x10000, ms->current_range, NULL);
 }
 
-ZTEST_SUITE(tcs3400, drivers_predicate_post_main, NULL, NULL, NULL, NULL);
+struct tcs3400_test_fixture {
+	struct als_drv_data_t drv_data;
+	struct tcs3400_rgb_drv_data_t rgb_drv_data;
+};
+
+static void tcs3400_before(void *state)
+{
+	struct tcs3400_test_fixture *f = state;
+
+	f->drv_data = *TCS3400_DRV_DATA(&motion_sensors[TCS_CLR_SENSOR_ID]);
+	f->rgb_drv_data =
+		*TCS3400_RGB_DRV_DATA(&motion_sensors[TCS_RGB_SENSOR_ID]);
+}
+
+static void tcs3400_after(void *state)
+{
+	struct tcs3400_test_fixture *f = state;
+
+	*TCS3400_DRV_DATA(&motion_sensors[TCS_CLR_SENSOR_ID]) = f->drv_data;
+	*TCS3400_RGB_DRV_DATA(&motion_sensors[TCS_RGB_SENSOR_ID]) =
+		f->rgb_drv_data;
+}
+
+static void *tcs3400_setup(void)
+{
+	static struct tcs3400_test_fixture tcs3400_fixture = { 0 };
+
+	return &tcs3400_fixture;
+}
+
+ZTEST_SUITE(tcs3400, drivers_predicate_post_main, tcs3400_setup, tcs3400_before,
+	    tcs3400_after, NULL);
diff --git a/zephyr/test/drivers/src/temp_sensor.c b/zephyr/test/drivers/default/src/temp_sensor.c
index 1a49dba8ca..5caecc556c 100644
--- a/zephyr/test/drivers/src/temp_sensor.c
+++ b/zephyr/test/drivers/default/src/temp_sensor.c
@@ -1,10 +1,10 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <zephyr/zephyr.h>
-#include <ztest.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
 #include <zephyr/drivers/adc.h>
 #include <zephyr/drivers/adc/adc_emul.h>
 #include <zephyr/drivers/gpio.h>
@@ -20,17 +20,19 @@
 #define GPIO_PG_EC_DSW_PWROK_PATH DT_PATH(named_gpios, pg_ec_dsw_pwrok)
 #define GPIO_PG_EC_DSW_PWROK_PORT DT_GPIO_PIN(GPIO_PG_EC_DSW_PWROK_PATH, gpios)
 
-#define ADC_DEVICE_NODE		DT_NODELABEL(adc0)
-#define ADC_CHANNELS_NUM	DT_PROP(DT_NODELABEL(adc0), nchannels)
+#define GPIO_EC_PG_PIN_TEMP_PATH DT_PATH(named_gpios, ec_pg_pin_temp)
+#define GPIO_EC_PG_PIN_TEMP_PORT DT_GPIO_PIN(GPIO_EC_PG_PIN_TEMP_PATH, gpios)
+
+#define ADC_DEVICE_NODE DT_NODELABEL(adc0)
+#define ADC_CHANNELS_NUM DT_PROP(DT_NODELABEL(adc0), nchannels)
 
 /** Test error code when invalid sensor is passed to temp_sensor_read() */
 ZTEST_USER(temp_sensor, test_temp_sensor_wrong_id)
 {
 	int temp;
 
-	zassert_equal(EC_ERROR_INVAL, temp_sensor_read(TEMP_SENSOR_COUNT,
-						       &temp),
-		      NULL);
+	zassert_equal(EC_ERROR_INVAL,
+		      temp_sensor_read(TEMP_SENSOR_COUNT, &temp), NULL);
 }
 
 /** Test error code when temp_sensor_read() is called with powered off ADC */
@@ -50,13 +52,24 @@ ZTEST_USER(temp_sensor, test_temp_sensor_adc_error)
 		   NULL);
 
 	zassert_equal(EC_ERROR_NOT_POWERED,
-		      temp_sensor_read(TEMP_SENSOR_CHARGER, &temp), NULL);
-	zassert_equal(EC_ERROR_NOT_POWERED,
-		      temp_sensor_read(TEMP_SENSOR_DDR_SOC, &temp), NULL);
+		      temp_sensor_read(
+			      TEMP_SENSOR_ID(DT_NODELABEL(named_temp_charger)),
+			      &temp),
+		      NULL);
 	zassert_equal(EC_ERROR_NOT_POWERED,
-		      temp_sensor_read(TEMP_SENSOR_FAN, &temp), NULL);
+		      temp_sensor_read(
+			      TEMP_SENSOR_ID(DT_NODELABEL(named_temp_ddr_soc)),
+			      &temp),
+		      NULL);
+	zassert_equal(
+		EC_ERROR_NOT_POWERED,
+		temp_sensor_read(TEMP_SENSOR_ID(DT_NODELABEL(named_temp_fan)),
+				 &temp),
+		NULL);
 	zassert_equal(EC_ERROR_NOT_POWERED,
-		      temp_sensor_read(TEMP_SENSOR_PP3300_REGULATOR, &temp),
+		      temp_sensor_read(TEMP_SENSOR_ID(DT_NODELABEL(
+					       named_temp_pp3300_regulator)),
+				       &temp),
 		      NULL);
 
 	/* power ADC */
@@ -64,6 +77,45 @@ ZTEST_USER(temp_sensor, test_temp_sensor_adc_error)
 		   NULL);
 }
 
+/** Test error code when temp_sensor_read() is called power-good-pin low */
+ZTEST_USER(temp_sensor, test_temp_sensor_pg_pin)
+{
+	const struct device *gpio_dev =
+		DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_EC_PG_PIN_TEMP_PATH, gpios));
+	int temp;
+
+	zassert_not_null(gpio_dev, "Cannot get GPIO device");
+
+	/* ec_pg_pin_temp = 0 means temperature sensors are not powered. */
+	zassert_ok(gpio_emul_input_set(gpio_dev, GPIO_EC_PG_PIN_TEMP_PORT, 0),
+		   NULL);
+
+	zassert_equal(EC_ERROR_NOT_POWERED,
+		      temp_sensor_read(
+			      TEMP_SENSOR_ID(DT_NODELABEL(named_temp_charger)),
+			      &temp),
+		      NULL);
+	zassert_equal(EC_ERROR_NOT_POWERED,
+		      temp_sensor_read(
+			      TEMP_SENSOR_ID(DT_NODELABEL(named_temp_ddr_soc)),
+			      &temp),
+		      NULL);
+	zassert_equal(
+		EC_ERROR_NOT_POWERED,
+		temp_sensor_read(TEMP_SENSOR_ID(DT_NODELABEL(named_temp_fan)),
+				 &temp),
+		NULL);
+	zassert_equal(EC_ERROR_NOT_POWERED,
+		      temp_sensor_read(TEMP_SENSOR_ID(DT_NODELABEL(
+					       named_temp_pp3300_regulator)),
+				       &temp),
+		      NULL);
+
+	/* power ADC */
+	zassert_ok(gpio_emul_input_set(gpio_dev, GPIO_EC_PG_PIN_TEMP_PORT, 1),
+		   NULL);
+}
+
 /** Simple ADC emulator custom function which always return error */
 static int adc_error_func(const struct device *dev, unsigned int channel,
 			  void *param, uint32_t *result)
@@ -85,9 +137,10 @@ static void check_valid_temperature(const struct device *adc_dev, int sensor)
 					    1000),
 		   "adc_emul_const_value_set() failed (sensor %d)", sensor);
 	zassert_equal(EC_SUCCESS, temp_sensor_read(sensor, &temp), NULL);
-	zassert_within(temp, 273 + 50, 51,
-		       "Expected temperature in 0*C-100*C, got %d*C (sensor %d)",
-		       temp - 273, sensor);
+	zassert_within(
+		temp, 273 + 50, 51,
+		"Expected temperature in 0*C-100*C, got %d*C (sensor %d)",
+		temp - 273, sensor);
 	/* Return error on ADC channel of tested sensor */
 	zassert_ok(adc_emul_value_func_set(adc_dev, temp_sensors[sensor].idx,
 					   adc_error_func, NULL),
@@ -105,14 +158,18 @@ ZTEST_USER(temp_sensor, test_temp_sensor_read)
 	/* Return error on all ADC channels */
 	for (chan = 0; chan < ADC_CHANNELS_NUM; chan++) {
 		zassert_ok(adc_emul_value_func_set(adc_dev, chan,
-						    adc_error_func, NULL),
+						   adc_error_func, NULL),
 			   "channel %d adc_emul_value_func_set() failed", chan);
 	}
 
-	check_valid_temperature(adc_dev, TEMP_SENSOR_CHARGER);
-	check_valid_temperature(adc_dev, TEMP_SENSOR_DDR_SOC);
-	check_valid_temperature(adc_dev, TEMP_SENSOR_FAN);
-	check_valid_temperature(adc_dev, TEMP_SENSOR_PP3300_REGULATOR);
+	check_valid_temperature(
+		adc_dev, TEMP_SENSOR_ID(DT_NODELABEL(named_temp_charger)));
+	check_valid_temperature(
+		adc_dev, TEMP_SENSOR_ID(DT_NODELABEL(named_temp_ddr_soc)));
+	check_valid_temperature(adc_dev,
+				TEMP_SENSOR_ID(DT_NODELABEL(named_temp_fan)));
+	check_valid_temperature(adc_dev, TEMP_SENSOR_ID(DT_NODELABEL(
+						 named_temp_pp3300_regulator)));
 
 	/* Return correct value on all ADC channels */
 	for (chan = 0; chan < ADC_CHANNELS_NUM; chan++) {
@@ -126,11 +183,15 @@ static void *temp_sensor_setup(void)
 {
 	const struct device *dev =
 		DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_PG_EC_DSW_PWROK_PATH, gpios));
+	const struct device *dev_pin =
+		DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_EC_PG_PIN_TEMP_PATH, gpios));
 
 	zassert_not_null(dev, NULL);
-	/* Before tests make sure that power pin is set. */
+	/* Before tests make sure that power pins are set. */
 	zassert_ok(gpio_emul_input_set(dev, GPIO_PG_EC_DSW_PWROK_PORT, 1),
 		   NULL);
+	zassert_ok(gpio_emul_input_set(dev_pin, GPIO_EC_PG_PIN_TEMP_PORT, 1),
+		   NULL);
 
 	return NULL;
 }
diff --git a/zephyr/test/drivers/src/thermistor.c b/zephyr/test/drivers/default/src/thermistor.c
index e760e0cf33..417b482d99 100644
--- a/zephyr/test/drivers/src/thermistor.c
+++ b/zephyr/test/drivers/default/src/thermistor.c
@@ -1,10 +1,10 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <zephyr/zephyr.h>
-#include <ztest.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
 #include <zephyr/drivers/adc.h>
 #include <zephyr/drivers/adc/adc_emul.h>
 #include <zephyr/drivers/gpio.h>
@@ -16,24 +16,25 @@
 #include "temp_sensor/temp_sensor.h"
 #include "test/drivers/test_state.h"
 
-
 #define GPIO_PG_EC_DSW_PWROK_PATH DT_PATH(named_gpios, pg_ec_dsw_pwrok)
 #define GPIO_PG_EC_DSW_PWROK_PORT DT_GPIO_PIN(GPIO_PG_EC_DSW_PWROK_PATH, gpios)
 
-#define ADC_DEVICE_NODE		DT_NODELABEL(adc0)
+#define GPIO_EC_PG_PIN_TEMP_PATH DT_PATH(named_gpios, ec_pg_pin_temp)
+#define GPIO_EC_PG_PIN_TEMP_PORT DT_GPIO_PIN(GPIO_EC_PG_PIN_TEMP_PATH, gpios)
+
+#define ADC_DEVICE_NODE DT_NODELABEL(adc0)
 
 /* TODO replace counting macros with DT macro when
  * https://github.com/zephyrproject-rtos/zephyr/issues/38715 lands
  */
-#define _ACCUMULATOR(x)
-#define NAMED_TEMP_SENSORS_SIZE                                     \
-	DT_FOREACH_CHILD(DT_PATH(named_temp_sensors), _ACCUMULATOR) \
-	0
-#define TEMP_SENSORS_ENABLED_SIZE \
-	DT_FOREACH_STATUS_OKAY(cros_ec_temp_sensor, _ACCUMULATOR) 0
+#define _ACCUMULATOR(x) 1 +
+#define NAMED_TEMP_SENSORS_SIZE \
+	DT_FOREACH_CHILD(TEMP_SENSORS_NODEID, _ACCUMULATOR) 0
+
+#define TEMP_SENSORS_ENABLED_SIZE FOREACH_TEMP_SENSOR(_ACCUMULATOR) 0
 
 /* Conversion of temperature doesn't need to be 100% accurate */
-#define TEMP_EPS	2
+#define TEMP_EPS 2
 
 #define A_VALID_VOLTAGE 1000
 /**
@@ -57,9 +58,8 @@ ZTEST_USER(thermistor, test_thermistor_power_pin)
 	     sensor_idx++) {
 		const struct temp_sensor_t *sensor = &temp_sensors[sensor_idx];
 
-		zassert_ok(adc_emul_const_value_set(adc_dev,
-						   sensor->idx,
-						   A_VALID_VOLTAGE),
+		zassert_ok(adc_emul_const_value_set(adc_dev, sensor->idx,
+						    A_VALID_VOLTAGE),
 			   "adc_emul_value_func_set() failed on %s",
 			   sensor->name);
 	}
@@ -135,26 +135,26 @@ static int resistance_47kohm_B4050(int t)
 	/* Thermistor manufacturer resistance lookup table*/
 	int r_table[] = {
 		155700, 147900, 140600, 133700, 127200, /* 0*C  - 4*C */
-		121000, 115100, 109600, 104300, 99310,  /* 5*C  - 9*C */
-		94600,  90130,  85890,  81870,  78070,  /* 10*C - 14*C */
-		74450,  71020,  67770,  64680,  61750,  /* 15*C - 19*C */
-		58970,  56320,  53810,  51430,  49160,  /* 20*C - 24*C */
-		47000,  44950,  42990,  41130,  39360,  /* 25*C - 29*C */
-		37680,  36070,  34540,  33080,  31690,  /* 30*C - 34*C */
-		30360,  29100,  27900,  26750,  25650,  /* 35*C - 39*C */
-		24610,  23610,  22660,  21750,  20880,  /* 40*C - 44*C */
-		20050,  19260,  18500,  17780,  17090,  /* 45*C - 49*C */
-		16430,  15800,  15200,  14620,  14070,  /* 50*C - 54*C */
-		13540,  13030,  12550,  12090,  11640,  /* 55*C - 59*C */
-		11210,  10800,  10410,  10040,  9676,   /* 60*C - 64*C */
-		9331,   8999,   8680,   8374,   8081,   /* 65*C - 69*C */
-		7799,   7528,   7268,   7018,   6777,   /* 70*C - 74*C */
-		6546,   6324,   6111,   5906,   5708,   /* 75*C - 79*C */
-		5518,   5335,   5160,   4990,   4827,   /* 80*C - 84*C */
-		4671,   4519,   4374,   4233,   4098,   /* 85*C - 89*C */
-		3968,   3842,   3721,   3605,   3492,   /* 90*C - 94*C */
-		3384,   3279,   3179,   3082,   2988,   /* 95*C - 99*C */
-		2898                                    /* 100*C */
+		121000, 115100, 109600, 104300, 99310, /* 5*C  - 9*C */
+		94600,	90130,	85890,	81870,	78070, /* 10*C - 14*C */
+		74450,	71020,	67770,	64680,	61750, /* 15*C - 19*C */
+		58970,	56320,	53810,	51430,	49160, /* 20*C - 24*C */
+		47000,	44950,	42990,	41130,	39360, /* 25*C - 29*C */
+		37680,	36070,	34540,	33080,	31690, /* 30*C - 34*C */
+		30360,	29100,	27900,	26750,	25650, /* 35*C - 39*C */
+		24610,	23610,	22660,	21750,	20880, /* 40*C - 44*C */
+		20050,	19260,	18500,	17780,	17090, /* 45*C - 49*C */
+		16430,	15800,	15200,	14620,	14070, /* 50*C - 54*C */
+		13540,	13030,	12550,	12090,	11640, /* 55*C - 59*C */
+		11210,	10800,	10410,	10040,	9676, /* 60*C - 64*C */
+		9331,	8999,	8680,	8374,	8081, /* 65*C - 69*C */
+		7799,	7528,	7268,	7018,	6777, /* 70*C - 74*C */
+		6546,	6324,	6111,	5906,	5708, /* 75*C - 79*C */
+		5518,	5335,	5160,	4990,	4827, /* 80*C - 84*C */
+		4671,	4519,	4374,	4233,	4098, /* 85*C - 89*C */
+		3968,	3842,	3721,	3605,	3492, /* 90*C - 94*C */
+		3384,	3279,	3179,	3082,	2988, /* 95*C - 99*C */
+		2898 /* 100*C */
 	};
 
 	t -= 273;
@@ -188,8 +188,7 @@ static int adc_temperature_func(const struct device *dev, unsigned int channel,
 {
 	struct thermistor_state *s = (struct thermistor_state *)param;
 
-	*result = volt_divider(s->v,
-			       s->r,
+	*result = volt_divider(s->v, s->r,
 			       resistance_47kohm_B4050(s->temp_expected));
 
 	return 0;
@@ -211,8 +210,7 @@ static void do_thermistor_test(const struct temp_sensor_t *temp_sensor,
 	zassert_not_null(adc_dev, "Cannot get ADC device");
 
 	/* Setup ADC channel */
-	zassert_ok(adc_emul_value_func_set(adc_dev,
-					   temp_sensor->idx,
+	zassert_ok(adc_emul_value_func_set(adc_dev, temp_sensor->idx,
 					   adc_temperature_func, &state),
 		   "adc_emul_value_func_set() failed on %s", temp_sensor->name);
 
@@ -225,8 +223,9 @@ static void do_thermistor_test(const struct temp_sensor_t *temp_sensor,
 	for (temp_expected = 273; temp_expected <= 373; temp_expected++) {
 		state.temp_expected = temp_expected;
 		zassert_equal(EC_SUCCESS,
-			temp_sensor->zephyr_info->read(temp_sensor, &temp),
-			"failed on %s", temp_sensor->name);
+			      temp_sensor->zephyr_info->read(temp_sensor,
+							     &temp),
+			      "failed on %s", temp_sensor->name);
 		zassert_within(temp_expected, temp, TEMP_EPS,
 			       "Expected %d*K, got %d*K on %s", temp_expected,
 			       temp, temp_sensor->name);
@@ -249,12 +248,12 @@ static void do_thermistor_test(const struct temp_sensor_t *temp_sensor,
 		      temp_sensor->name);
 }
 
-#define GET_THERMISTOR_REF_MV(node_id)             \
-	[ZSHIM_TEMP_SENSOR_ID(node_id)] = DT_PROP( \
+#define GET_THERMISTOR_REF_MV(node_id)              \
+	[TEMP_SENSOR_ID_BY_DEV(node_id)] = DT_PROP( \
 		DT_PHANDLE(node_id, thermistor), steinhart_reference_mv),
 
-#define GET_THERMISTOR_REF_RES(node_id)            \
-	[ZSHIM_TEMP_SENSOR_ID(node_id)] = DT_PROP( \
+#define GET_THERMISTOR_REF_RES(node_id)             \
+	[TEMP_SENSOR_ID_BY_DEV(node_id)] = DT_PROP( \
 		DT_PHANDLE(node_id, thermistor), steinhart_reference_res),
 
 ZTEST_USER(thermistor, test_thermistors_adc_temperature_conversion)
@@ -262,9 +261,9 @@ ZTEST_USER(thermistor, test_thermistors_adc_temperature_conversion)
 	int sensor_idx;
 
 	const static int reference_mv_arr[] = { DT_FOREACH_STATUS_OKAY(
-		cros_temp_sensor, GET_THERMISTOR_REF_MV) };
+		THERMISTOR_COMPAT, GET_THERMISTOR_REF_MV) };
 	const static int reference_res_arr[] = { DT_FOREACH_STATUS_OKAY(
-		cros_temp_sensor, GET_THERMISTOR_REF_RES) };
+		THERMISTOR_COMPAT, GET_THERMISTOR_REF_RES) };
 
 	for (sensor_idx = 0; sensor_idx < NAMED_TEMP_SENSORS_SIZE; sensor_idx++)
 		do_thermistor_test(&temp_sensors[sensor_idx],
@@ -285,14 +284,44 @@ static void *thermistor_setup(void)
 {
 	const struct device *dev =
 		DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_PG_EC_DSW_PWROK_PATH, gpios));
+	const struct device *dev_pin =
+		DEVICE_DT_GET(DT_GPIO_CTLR(GPIO_EC_PG_PIN_TEMP_PATH, gpios));
 
 	zassert_not_null(dev, NULL);
-	/* Before tests make sure that power pin is set. */
+	/* Before tests make sure that power pins are set. */
 	zassert_ok(gpio_emul_input_set(dev, GPIO_PG_EC_DSW_PWROK_PORT, 1),
 		   NULL);
+	zassert_ok(gpio_emul_input_set(dev_pin, GPIO_EC_PG_PIN_TEMP_PORT, 1),
+		   NULL);
 
 	return NULL;
 }
 
+static void thermistor_cleanup(void *state)
+{
+	int sensor_idx;
+	const struct device *adc_dev = DEVICE_DT_GET(ADC_DEVICE_NODE);
+
+	const static int reference_mv_arr[] = { DT_FOREACH_STATUS_OKAY(
+		THERMISTOR_COMPAT, GET_THERMISTOR_REF_MV) };
+	const static int reference_res_arr[] = { DT_FOREACH_STATUS_OKAY(
+		THERMISTOR_COMPAT, GET_THERMISTOR_REF_RES) };
+
+	if (adc_dev == NULL)
+		TC_ERROR("Cannot get ADC device");
+
+	for (sensor_idx = 0; sensor_idx < NAMED_TEMP_SENSORS_SIZE;
+	     sensor_idx++) {
+		/* Setup ADC to return 27*C (300K) which is reasonable value */
+		adc_emul_const_value_set(
+			adc_dev, temp_sensors[sensor_idx].idx,
+			volt_divider(reference_mv_arr[sensor_idx],
+				     reference_res_arr[sensor_idx],
+				     resistance_47kohm_B4050(300)));
+		adc_emul_ref_voltage_set(adc_dev, ADC_REF_INTERNAL,
+					 reference_mv_arr[sensor_idx]);
+	}
+}
+
 ZTEST_SUITE(thermistor, drivers_predicate_post_main, thermistor_setup, NULL,
-	    NULL, NULL);
+	    NULL, thermistor_cleanup);
diff --git a/zephyr/test/drivers/src/uart_hostcmd.c b/zephyr/test/drivers/default/src/uart_hostcmd.c
index 0e68c440ce..879e734837 100644
--- a/zephyr/test/drivers/src/uart_hostcmd.c
+++ b/zephyr/test/drivers/default/src/uart_hostcmd.c
@@ -1,10 +1,10 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <zephyr/zephyr.h>
-#include <ztest.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
 
 #include "console.h"
 #include "host_command.h"
@@ -86,8 +86,8 @@ static void test_uart_hc_read_next(int ver)
 	 */
 	msg1_start = response + read_args.response_size - 1 - MSG_LEN(msg1);
 	zassert_mem_equal(msg1, msg1_start, MSG_LEN(msg1),
-			  "expected \"%s\", got \"%.*s\"",
-			  msg1, MSG_LEN(msg1), msg1_start);
+			  "expected \"%s\", got \"%.*s\"", msg1, MSG_LEN(msg1),
+			  msg1_start);
 
 	/* Set new snapshot which should include message 2 */
 	zassert_equal(EC_RES_SUCCESS, host_command_process(&snap_args), NULL);
@@ -106,11 +106,11 @@ static void test_uart_hc_read_next(int ver)
 	msg2_start = response + read_args.response_size - 1 - MSG_LEN(msg2);
 	msg1_start = msg2_start - MSG_LEN(msg1);
 	zassert_mem_equal(msg2, msg2_start, MSG_LEN(msg2),
-			  "expected \"%s\", got \"%.*s\"",
-			  msg2, MSG_LEN(msg2), msg2_start);
+			  "expected \"%s\", got \"%.*s\"", msg2, MSG_LEN(msg2),
+			  msg2_start);
 	zassert_mem_equal(msg1, msg1_start, MSG_LEN(msg1),
-			  "expected \"%s\", got \"%.*s\"",
-			  msg1, MSG_LEN(msg1), msg1_start);
+			  "expected \"%s\", got \"%.*s\"", msg1, MSG_LEN(msg1),
+			  msg1_start);
 
 	/* Append third message */
 	cputs(CC_COMMAND, msg3);
@@ -135,14 +135,14 @@ static void test_uart_hc_read_next(int ver)
 	msg2_start = msg3_start - MSG_LEN(msg2);
 	msg1_start = msg2_start - MSG_LEN(msg1);
 	zassert_mem_equal(msg3, msg3_start, MSG_LEN(msg3),
-			  "expected \"%s\", got \"%.*s\"",
-			  msg3, MSG_LEN(msg3), msg3_start);
+			  "expected \"%s\", got \"%.*s\"", msg3, MSG_LEN(msg3),
+			  msg3_start);
 	zassert_mem_equal(msg2, msg2_start, MSG_LEN(msg2),
-			  "expected \"%s\", got \"%.*s\"",
-			  msg2, MSG_LEN(msg2), msg2_start);
+			  "expected \"%s\", got \"%.*s\"", msg2, MSG_LEN(msg2),
+			  msg2_start);
 	zassert_mem_equal(msg1, msg1_start, MSG_LEN(msg1),
-			  "expected \"%s\", got \"%.*s\"",
-			  msg1, MSG_LEN(msg1), msg1_start);
+			  "expected \"%s\", got \"%.*s\"", msg1, MSG_LEN(msg1),
+			  msg1_start);
 }
 
 ZTEST_USER(uart_hostcmd, test_uart_hc_read_next_v0)
@@ -176,11 +176,11 @@ ZTEST_USER(uart_hostcmd, test_uart_hc_read_recent_v1)
 		      response[read_args.response_size]);
 	/* Account additional NULL char at the end */
 	zassert_equal(MSG_LEN(msg1) + 1, read_args.response_size,
-		      "expected message length %d, got %d",
-		      MSG_LEN(msg1) + 1, read_args.response_size);
+		      "expected message length %d, got %d", MSG_LEN(msg1) + 1,
+		      read_args.response_size);
 	zassert_mem_equal(msg1, response, MSG_LEN(msg1),
-			  "expected \"%s\", got \"%.*s\"",
-			  msg1, MSG_LEN(msg1), response);
+			  "expected \"%s\", got \"%.*s\"", msg1, MSG_LEN(msg1),
+			  response);
 
 	/* Set new snapshot after second message */
 	zassert_equal(EC_RES_SUCCESS, host_command_process(&snap_args), NULL);
@@ -193,11 +193,11 @@ ZTEST_USER(uart_hostcmd, test_uart_hc_read_recent_v1)
 		      response[read_args.response_size]);
 	/* Account additional NULL char at the end */
 	zassert_equal(MSG_LEN(msg2) + 1, read_args.response_size,
-		      "expected message length %d, got %d",
-		      MSG_LEN(msg2) + 1, read_args.response_size);
+		      "expected message length %d, got %d", MSG_LEN(msg2) + 1,
+		      read_args.response_size);
 	zassert_mem_equal(msg2, response, MSG_LEN(msg2),
-			  "expected \"%s\", got \"%.*s\"",
-			  msg2, MSG_LEN(msg2), response);
+			  "expected \"%s\", got \"%.*s\"", msg2, MSG_LEN(msg2),
+			  response);
 
 	/* Append third message */
 	cputs(CC_COMMAND, msg3);
@@ -220,11 +220,11 @@ ZTEST_USER(uart_hostcmd, test_uart_hc_read_recent_v1)
 		      response[read_args.response_size]);
 	/* Account additional NULL char at the end */
 	zassert_equal(MSG_LEN(msg3) + 1, read_args.response_size,
-		      "expected message length %d, got %d",
-		      MSG_LEN(msg3) + 1, read_args.response_size);
+		      "expected message length %d, got %d", MSG_LEN(msg3) + 1,
+		      read_args.response_size);
 	zassert_mem_equal(msg3, response, MSG_LEN(msg3),
-			  "expected \"%s\", got \"%.*s\"",
-			  msg3, MSG_LEN(msg3), response);
+			  "expected \"%s\", got \"%.*s\"", msg3, MSG_LEN(msg3),
+			  response);
 }
 
 ZTEST_SUITE(uart_hostcmd, drivers_predicate_post_main, NULL,
diff --git a/zephyr/test/drivers/src/usb_mux.c b/zephyr/test/drivers/default/src/usb_mux.c
index 09aa3c47d6..45b81d6ea5 100644
--- a/zephyr/test/drivers/src/usb_mux.c
+++ b/zephyr/test/drivers/default/src/usb_mux.c
@@ -1,11 +1,10 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include <zephyr/kernel.h>
-#include <zephyr/zephyr.h>
-#include <ztest.h>
+#include <zephyr/ztest.h>
 #include <zephyr/drivers/gpio.h>
 #include <zephyr/drivers/gpio/gpio_emul.h>
 #include <zephyr/shell/shell.h>
@@ -14,7 +13,7 @@
 #include "common.h"
 #include "ec_commands.h"
 #include "ec_tasks.h"
-#include "fff.h"
+#include <zephyr/fff.h>
 #include "hooks.h"
 #include "host_command.h"
 #include "i2c.h"
@@ -30,16 +29,16 @@
 #include "test/drivers/utils.h"
 
 /** Copy of original usb_muxes[USB_PORT_C1] */
-struct usb_mux usb_mux_c1;
+struct usb_mux_chain usb_mux_c1;
 
 /** Number of usb mux proxies in chain */
-#define NUM_OF_PROXY	3
+#define NUM_OF_PROXY 3
 
 /** Pointers to original usb muxes chain of port c1 */
 const struct usb_mux *org_mux[NUM_OF_PROXY];
 
 /** Proxy function which check calls from usb_mux framework to driver */
-FAKE_VALUE_FUNC1(int, proxy_init, const struct usb_mux *);
+FAKE_VALUE_FUNC(int, proxy_init, const struct usb_mux *);
 static int proxy_init_custom(const struct usb_mux *me)
 {
 	int i = me->i2c_addr_flags;
@@ -47,8 +46,7 @@ static int proxy_init_custom(const struct usb_mux *me)
 
 	zassert_true(i < NUM_OF_PROXY, "Proxy called for non proxy usb_mux");
 
-	if (org_mux[i] != NULL &&
-	    org_mux[i]->driver->init != NULL) {
+	if (org_mux[i] != NULL && org_mux[i]->driver->init != NULL) {
 		ec = org_mux[i]->driver->init(org_mux[i]);
 	}
 
@@ -63,7 +61,7 @@ static int proxy_init_custom(const struct usb_mux *me)
 }
 
 /** Proxy function which check calls from usb_mux framework to driver */
-FAKE_VALUE_FUNC3(int, proxy_set, const struct usb_mux *, mux_state_t, bool *);
+FAKE_VALUE_FUNC(int, proxy_set, const struct usb_mux *, mux_state_t, bool *);
 static int proxy_set_custom(const struct usb_mux *me, mux_state_t mux_state,
 			    bool *ack_required)
 {
@@ -72,10 +70,11 @@ static int proxy_set_custom(const struct usb_mux *me, mux_state_t mux_state,
 
 	zassert_true(i < NUM_OF_PROXY, "Proxy called for non proxy usb_mux");
 
-	if (org_mux[i] != NULL &&
-	    org_mux[i]->driver->set != NULL) {
+	if (org_mux[i] != NULL && org_mux[i]->driver->set != NULL) {
 		ec = org_mux[i]->driver->set(org_mux[i], mux_state,
 					     ack_required);
+		/* Disable waiting for ACK in tests */
+		*ack_required = false;
 	}
 
 	if (task_get_current() == TASK_ID_TEST_RUNNER) {
@@ -89,7 +88,7 @@ static int proxy_set_custom(const struct usb_mux *me, mux_state_t mux_state,
 }
 
 /** Proxy function which check calls from usb_mux framework to driver */
-FAKE_VALUE_FUNC2(int, proxy_get, const struct usb_mux *, mux_state_t *);
+FAKE_VALUE_FUNC(int, proxy_get, const struct usb_mux *, mux_state_t *);
 /** Sequence of mux_state values returned by proxy_get function */
 static mux_state_t proxy_get_mux_state_seq[NUM_OF_PROXY];
 /** Index of next mux_state to return from proxy_get_function */
@@ -110,15 +109,15 @@ static int proxy_get_custom(const struct usb_mux *me, mux_state_t *mux_state)
 
 	zassert_true(i < NUM_OF_PROXY, "Proxy called for non proxy usb_mux");
 
-	if (org_mux[i] != NULL &&
-	    org_mux[i]->driver->get != NULL) {
+	if (org_mux[i] != NULL && org_mux[i]->driver->get != NULL) {
 		ec = org_mux[i]->driver->get(org_mux[i], mux_state);
 	}
 
 	if (task_get_current() == TASK_ID_TEST_RUNNER) {
 		zassert_true(proxy_get_mux_state_seq_idx < NUM_OF_PROXY,
 			     "%s called too many times without resetting "
-			     "mux_state_seq", __func__);
+			     "mux_state_seq",
+			     __func__);
 		*mux_state =
 			proxy_get_mux_state_seq[proxy_get_mux_state_seq_idx];
 		proxy_get_mux_state_seq_idx++;
@@ -132,7 +131,7 @@ static int proxy_get_custom(const struct usb_mux *me, mux_state_t *mux_state)
 }
 
 /** Proxy function which check calls from usb_mux framework to driver */
-FAKE_VALUE_FUNC1(int, proxy_enter_low_power_mode, const struct usb_mux *);
+FAKE_VALUE_FUNC(int, proxy_enter_low_power_mode, const struct usb_mux *);
 static int proxy_enter_low_power_mode_custom(const struct usb_mux *me)
 {
 	int i = me->i2c_addr_flags;
@@ -156,7 +155,7 @@ static int proxy_enter_low_power_mode_custom(const struct usb_mux *me)
 }
 
 /** Proxy function which check calls from usb_mux framework to driver */
-FAKE_VALUE_FUNC1(int, proxy_chipset_reset, const struct usb_mux *);
+FAKE_VALUE_FUNC(int, proxy_chipset_reset, const struct usb_mux *);
 static int proxy_chipset_reset_custom(const struct usb_mux *me)
 {
 	int i = me->i2c_addr_flags;
@@ -164,8 +163,7 @@ static int proxy_chipset_reset_custom(const struct usb_mux *me)
 
 	zassert_true(i < NUM_OF_PROXY, "Proxy called for non proxy usb_mux");
 
-	if (org_mux[i] != NULL &&
-	    org_mux[i]->driver->chipset_reset != NULL) {
+	if (org_mux[i] != NULL && org_mux[i]->driver->chipset_reset != NULL) {
 		ec = org_mux[i]->driver->chipset_reset(org_mux[i]);
 	}
 
@@ -186,7 +184,7 @@ static bool proxy_fw_update_cap(void)
 }
 
 /** Proxy function which check calls from usb_mux framework to driver */
-FAKE_VOID_FUNC3(proxy_hpd_update, const struct usb_mux *, mux_state_t, bool *);
+FAKE_VOID_FUNC(proxy_hpd_update, const struct usb_mux *, mux_state_t, bool *);
 static void proxy_hpd_update_custom(const struct usb_mux *me,
 				    mux_state_t mux_state, bool *ack_required)
 {
@@ -194,9 +192,10 @@ static void proxy_hpd_update_custom(const struct usb_mux *me,
 
 	zassert_true(i < NUM_OF_PROXY, "Proxy called for non proxy usb_mux");
 
-	if (org_mux[i] != NULL &&
-	    org_mux[i]->hpd_update != NULL) {
+	if (org_mux[i] != NULL && org_mux[i]->hpd_update != NULL) {
 		org_mux[i]->hpd_update(org_mux[i], mux_state, ack_required);
+		/* Disable waiting for ACK in tests */
+		*ack_required = false;
 	}
 
 	if (task_get_current() != TASK_ID_TEST_RUNNER) {
@@ -216,7 +215,7 @@ const struct usb_mux_driver proxy_usb_mux = {
 };
 
 /** Mock function used in init test */
-FAKE_VALUE_FUNC1(int, mock_board_init, const struct usb_mux *);
+FAKE_VALUE_FUNC(int, mock_board_init, const struct usb_mux *);
 static int mock_board_init_custom(const struct usb_mux *me)
 {
 	if (task_get_current() == TASK_ID_TEST_RUNNER) {
@@ -230,7 +229,7 @@ static int mock_board_init_custom(const struct usb_mux *me)
 }
 
 /** Mock function used in set test */
-FAKE_VALUE_FUNC2(int, mock_board_set, const struct usb_mux *, mux_state_t);
+FAKE_VALUE_FUNC(int, mock_board_set, const struct usb_mux *, mux_state_t);
 static int mock_board_set_custom(const struct usb_mux *me,
 				 mux_state_t mux_state)
 {
@@ -264,7 +263,7 @@ static void reset_proxy_fakes(void)
 	proxy_set_fake.custom_fake = proxy_set_custom;
 	proxy_get_fake.custom_fake = proxy_get_custom;
 	proxy_enter_low_power_mode_fake.custom_fake =
-					proxy_enter_low_power_mode_custom;
+		proxy_enter_low_power_mode_custom;
 	proxy_chipset_reset_fake.custom_fake = proxy_chipset_reset_custom;
 	proxy_hpd_update_fake.custom_fake = proxy_hpd_update_custom;
 	mock_board_init_fake.custom_fake = mock_board_init_custom;
@@ -281,40 +280,51 @@ static void reset_proxy_fakes(void)
 }
 
 /** Chain of 3 proxy usb muxes */
-struct usb_mux proxy_chain_2 = {
+struct usb_mux proxy_mux_2 = {
 	.usb_port = USBC_PORT_C1,
 	.driver = &proxy_usb_mux,
-	.next_mux = NULL,
 	.i2c_addr_flags = 2,
 	.hpd_update = &proxy_hpd_update,
 };
 
-struct usb_mux proxy_chain_1 = {
+struct usb_mux_chain proxy_chain_2 = {
+	.mux = &proxy_mux_2,
+};
+
+struct usb_mux proxy_mux_1 = {
 	.usb_port = USBC_PORT_C1,
 	.driver = &proxy_usb_mux,
-	.next_mux = &proxy_chain_2,
 	.i2c_addr_flags = 1,
 	.hpd_update = &proxy_hpd_update,
 };
 
-struct usb_mux proxy_chain_0 = {
+struct usb_mux_chain proxy_chain_1 = {
+	.mux = &proxy_mux_1,
+	.next = &proxy_chain_2,
+};
+
+struct usb_mux proxy_mux_0 = {
 	.usb_port = USBC_PORT_C1,
 	.driver = &proxy_usb_mux,
-	.next_mux = &proxy_chain_1,
 	.i2c_addr_flags = 0,
 	.hpd_update = &proxy_hpd_update,
 };
 
+struct usb_mux_chain proxy_chain_0 = {
+	.mux = &proxy_mux_0,
+	.next = &proxy_chain_1,
+};
 
 /** Setup first 3 usb muxes of port 1 with proxy */
 static void setup_usb_mux_proxy_chain(void)
 {
-	const struct usb_mux *t;
+	const struct usb_mux_chain *t;
 	int i;
 
-	memcpy(&usb_mux_c1, &usb_muxes[USBC_PORT_C1], sizeof(struct usb_mux));
+	memcpy(&usb_mux_c1, &usb_muxes[USBC_PORT_C1],
+	       sizeof(struct usb_mux_chain));
 	memcpy(&usb_muxes[USBC_PORT_C1], &proxy_chain_0,
-	       sizeof(struct usb_mux));
+	       sizeof(struct usb_mux_chain));
 
 	/*
 	 * Setup org_mux array to point real driver which should be called by
@@ -322,23 +332,31 @@ static void setup_usb_mux_proxy_chain(void)
 	 */
 	t = &usb_mux_c1;
 	for (i = 0; i < NUM_OF_PROXY; i++) {
-		org_mux[i] = t;
 		if (t != NULL) {
-			t = t->next_mux;
+			org_mux[i] = t->mux;
+			t = t->next;
+		} else {
+			org_mux[i] = NULL;
 		}
 	}
 
-	if (org_mux[2] != NULL) {
-		proxy_chain_2.next_mux = org_mux[2]->next_mux;
+	if (t != NULL) {
+		proxy_chain_2.next = t;
 	} else {
-		proxy_chain_2.next_mux = NULL;
+		proxy_chain_2.next = NULL;
 	}
 }
 
 /** Restore original usb_mux chain without proxy */
 static void restore_usb_mux_chain(void)
 {
-	memcpy(&usb_muxes[USBC_PORT_C1], &usb_mux_c1, sizeof(struct usb_mux));
+	memcpy(&usb_muxes[USBC_PORT_C1], &usb_mux_c1,
+	       sizeof(struct usb_mux_chain));
+
+	/* Reset flags to default */
+	proxy_mux_0.flags = 0;
+	proxy_mux_1.flags = 0;
+	proxy_mux_2.flags = 0;
 }
 
 /**
@@ -346,25 +364,22 @@ static void restore_usb_mux_chain(void)
  * pointer to the right proxy chain element. First argument is
  * const struct usb_mux * for all struct usb_mux_driver callbacks.
  */
-#define CHECK_PROXY_FAKE_CALL_CNT(proxy, num)				\
-	do {								\
-		zassert_equal(num, proxy##_fake.call_count, "%d != %d",	\
-			      num, proxy##_fake.call_count);		\
-		if (num >= 1) {						\
-			zassert_equal(&usb_muxes[USBC_PORT_C1],		\
-				      proxy##_fake.arg0_history[0],	\
-				      NULL);				\
-		}							\
-		if (num >= 2) {						\
-			zassert_equal(&proxy_chain_1,			\
-				      proxy##_fake.arg0_history[1],	\
-				      NULL);				\
-		}							\
-		if (num >= 3) {						\
-			zassert_equal(&proxy_chain_2,			\
-				      proxy##_fake.arg0_history[2],	\
-				      NULL);				\
-		}							\
+#define CHECK_PROXY_FAKE_CALL_CNT(proxy, num)                                \
+	do {                                                                 \
+		zassert_equal(num, proxy##_fake.call_count, "%d != %d", num, \
+			      proxy##_fake.call_count);                      \
+		if (num >= 1) {                                              \
+			zassert_equal(usb_muxes[USBC_PORT_C1].mux,           \
+				      proxy##_fake.arg0_history[0], NULL);   \
+		}                                                            \
+		if (num >= 2) {                                              \
+			zassert_equal(proxy_chain_1.mux,                     \
+				      proxy##_fake.arg0_history[1], NULL);   \
+		}                                                            \
+		if (num >= 3) {                                              \
+			zassert_equal(proxy_chain_2.mux,                     \
+				      proxy##_fake.arg0_history[2], NULL);   \
+		}                                                            \
 	} while (0)
 
 /**
@@ -372,33 +387,30 @@ static void restore_usb_mux_chain(void)
  * was the same as given state. hpd_update and set callback have mux_state_t
  * as second argument.
  */
-#define CHECK_PROXY_FAKE_CALL_CNT_MUX_STATE(proxy, num, state)		\
-	do {								\
-		CHECK_PROXY_FAKE_CALL_CNT(proxy, num);			\
-		if (num >= 1) {						\
-			zassert_equal(state,				\
-				      proxy##_fake.arg1_history[0],	\
-				      "0x%x != 0x%x", state,		\
-				      proxy##_fake.arg1_history[0]);	\
-		}							\
-		if (num >= 2) {						\
-			zassert_equal(state,				\
-				      proxy##_fake.arg1_history[1],	\
-				      "0x%x != 0x%x", state,		\
-				      proxy##_fake.arg1_history[1]);	\
-		}							\
-		if (num >= 3) {						\
-			zassert_equal(state,				\
-				      proxy##_fake.arg1_history[2],	\
-				      "0x%x != 0x%x", state,		\
-				      proxy##_fake.arg1_history[2]);	\
-		}							\
+#define CHECK_PROXY_FAKE_CALL_CNT_MUX_STATE(proxy, num, state)             \
+	do {                                                               \
+		CHECK_PROXY_FAKE_CALL_CNT(proxy, num);                     \
+		if (num >= 1) {                                            \
+			zassert_equal(state, proxy##_fake.arg1_history[0], \
+				      "0x%x != 0x%x", state,               \
+				      proxy##_fake.arg1_history[0]);       \
+		}                                                          \
+		if (num >= 2) {                                            \
+			zassert_equal(state, proxy##_fake.arg1_history[1], \
+				      "0x%x != 0x%x", state,               \
+				      proxy##_fake.arg1_history[1]);       \
+		}                                                          \
+		if (num >= 3) {                                            \
+			zassert_equal(state, proxy##_fake.arg1_history[2], \
+				      "0x%x != 0x%x", state,               \
+				      proxy##_fake.arg1_history[2]);       \
+		}                                                          \
 	} while (0)
 
 /** Test usb_mux init */
 ZTEST(usb_uninit_mux, test_usb_mux_init)
 {
-	int fail_on_2nd_ret[] = {EC_SUCCESS, EC_ERROR_NOT_POWERED};
+	int fail_on_2nd_ret[] = { EC_SUCCESS, EC_ERROR_NOT_POWERED };
 
 	/* Set AP to normal state to init BB retimer */
 	test_set_chipset_to_s0();
@@ -417,26 +429,26 @@ ZTEST(usb_uninit_mux, test_usb_mux_init)
 	CHECK_PROXY_FAKE_CALL_CNT(proxy_init, 2);
 
 	/* Test board init callback */
-	proxy_chain_1.board_init = &mock_board_init;
+	proxy_mux_1.board_init = &mock_board_init;
 	reset_proxy_fakes();
 	usb_mux_init(USBC_PORT_C1);
 	CHECK_PROXY_FAKE_CALL_CNT(proxy_init, NUM_OF_PROXY);
 	/* Check if board_init was called for proxy 1 */
 	zassert_equal(1, mock_board_init_fake.call_count, NULL);
-	zassert_equal(&proxy_chain_1, mock_board_init_fake.arg0_history[0],
+	zassert_equal(proxy_chain_1.mux, mock_board_init_fake.arg0_history[0],
 		      NULL);
 
-	proxy_chain_1.board_init = NULL;
+	proxy_mux_1.board_init = NULL;
 }
 
 /** Test usb_mux setting mux mode */
 ZTEST(usb_uninit_mux, test_usb_mux_set)
 {
-	int fail_on_2nd_ret[] = {EC_SUCCESS, EC_ERROR_UNKNOWN};
+	int fail_on_2nd_ret[] = { EC_SUCCESS, EC_ERROR_UNKNOWN };
 	mux_state_t exp_mode;
 
 	/* Set flag for usb mux 1 to disable polarity setting */
-	proxy_chain_1.flags = USB_MUX_FLAG_SET_WITHOUT_FLIP;
+	proxy_mux_1.flags = USB_MUX_FLAG_SET_WITHOUT_FLIP;
 
 	/* Test setting mux mode without polarity inversion */
 	reset_proxy_fakes();
@@ -463,14 +475,14 @@ ZTEST(usb_uninit_mux, test_usb_mux_set)
 
 	/* Test board set callback */
 	reset_proxy_fakes();
-	proxy_chain_1.board_set = &mock_board_set;
+	proxy_mux_1.board_set = &mock_board_set;
 	usb_mux_set(USBC_PORT_C1, exp_mode, USB_SWITCH_CONNECT,
 		    0 /* = polarity */);
 	CHECK_PROXY_FAKE_CALL_CNT(proxy_init, 0);
 	CHECK_PROXY_FAKE_CALL_CNT_MUX_STATE(proxy_set, NUM_OF_PROXY, exp_mode);
 	/* Check if board_set was called for proxy 1 */
 	zassert_equal(1, mock_board_set_fake.call_count, NULL);
-	zassert_equal(&proxy_chain_1, mock_board_set_fake.arg0_history[0],
+	zassert_equal(proxy_chain_1.mux, mock_board_set_fake.arg0_history[0],
 		      NULL);
 	zassert_equal(exp_mode, mock_board_set_fake.arg1_history[0], NULL);
 
@@ -484,7 +496,7 @@ ZTEST(usb_uninit_mux, test_usb_mux_set)
 	/* board_set shouldn't be called after fail */
 	zassert_equal(0, mock_board_set_fake.call_count, NULL);
 
-	proxy_chain_1.board_set = NULL;
+	proxy_mux_1.board_set = NULL;
 }
 
 /** Test usb_mux reset in g3 when required flag is set */
@@ -500,7 +512,7 @@ ZTEST(usb_uninit_mux, test_usb_mux_reset_in_g3)
 	CHECK_PROXY_FAKE_CALL_CNT_MUX_STATE(proxy_set, NUM_OF_PROXY, exp_mode);
 
 	/* Usb muxes of port 1 should stay initialised */
-	usb_muxes[USBC_PORT_C1].flags = 0;
+	proxy_mux_0.flags = 0;
 	hook_notify(HOOK_CHIPSET_HARD_OFF);
 
 	/* Test that init is not called */
@@ -514,7 +526,7 @@ ZTEST(usb_uninit_mux, test_usb_mux_reset_in_g3)
 /** Test usb_mux getting mux mode */
 ZTEST(usb_uninit_mux, test_usb_mux_get)
 {
-	int fail_on_2nd_ret[] = {EC_SUCCESS, EC_ERROR_UNKNOWN};
+	int fail_on_2nd_ret[] = { EC_SUCCESS, EC_ERROR_UNKNOWN };
 	mux_state_t exp_mode, mode;
 
 	/* Test getting mux mode */
@@ -551,7 +563,7 @@ ZTEST(usb_uninit_mux, test_usb_mux_get)
 /** Test usb_mux entering and exiting low power mode */
 ZTEST(usb_init_mux, test_usb_mux_low_power_mode)
 {
-	int fail_on_2nd_ret[] = {EC_SUCCESS, EC_ERROR_NOT_POWERED};
+	int fail_on_2nd_ret[] = { EC_SUCCESS, EC_ERROR_NOT_POWERED };
 	mux_state_t exp_mode, mode;
 
 	/* Test enter to low power mode */
@@ -620,7 +632,7 @@ ZTEST(usb_uninit_mux, test_usb_mux_flip)
 	mux_state_t exp_mode;
 
 	/* Set flag for usb mux 1 to disable polarity setting */
-	proxy_chain_1.flags = USB_MUX_FLAG_SET_WITHOUT_FLIP;
+	proxy_mux_1.flags = USB_MUX_FLAG_SET_WITHOUT_FLIP;
 
 	/* Test flip port without polarity inverted */
 	exp_mode = USB_PD_MUX_USB_ENABLED;
@@ -704,17 +716,22 @@ ZTEST(usb_uninit_mux, test_usb_mux_hpd_update)
 					    exp_mode);
 
 	/* Test ps8xxx hpd update */
-	usb_muxes[USBC_PORT_C1].usb_port = 1;
-	usb_muxes[USBC_PORT_C1].driver = &tcpci_tcpm_usb_mux_driver;
-	usb_muxes[USBC_PORT_C1].hpd_update = &ps8xxx_tcpc_update_hpd_status;
+	proxy_mux_0.usb_port = 1;
+	proxy_mux_0.driver = &tcpci_tcpm_usb_mux_driver;
+	proxy_mux_0.hpd_update = &ps8xxx_tcpc_update_hpd_status;
 
 	reset_proxy_fakes();
 	exp_mode = virt_mode | USB_PD_MUX_HPD_LVL | USB_PD_MUX_HPD_IRQ;
 	usb_mux_hpd_update(USBC_PORT_C1, exp_mode);
 	/* Check if PS8xxx mux mode is updated correctly */
-	tcpci_tcpm_usb_mux_driver.get(&usb_muxes[USBC_PORT_C1], &mode);
-	zassert_equal(0, mode, "mux mode is 0x%x (!= 0x%x)",
-		      mode, 0);
+	tcpci_tcpm_usb_mux_driver.get(usb_muxes[USBC_PORT_C1].mux, &mode);
+
+	/* Restore proxy chain 0 */
+	proxy_mux_0.usb_port = USBC_PORT_C1;
+	proxy_mux_0.driver = &proxy_usb_mux;
+	proxy_mux_0.hpd_update = &proxy_hpd_update;
+
+	zassert_equal(0, mode, "mux mode is 0x%x (!= 0x%x)", mode, 0);
 }
 
 ZTEST(usb_init_mux, test_usb_mux_fw_update_port_info)
@@ -786,8 +803,7 @@ ZTEST(usb_init_mux, test_usb_mux_typec_command)
 
 	/* Test error on command with no argument */
 	zassert_equal(EC_ERROR_PARAM_COUNT,
-		      shell_execute_cmd(get_ec_shell(),
-					"typec"), NULL);
+		      shell_execute_cmd(get_ec_shell(), "typec"), NULL);
 
 	/*
 	 * Test success on passing "debug" as first argument. This will enable
@@ -795,49 +811,44 @@ ZTEST(usb_init_mux, test_usb_mux_typec_command)
 	 * without accessing cprints output.
 	 */
 	zassert_equal(EC_SUCCESS,
-		      shell_execute_cmd(get_ec_shell(),
-					"typec debug"), NULL);
+		      shell_execute_cmd(get_ec_shell(), "typec debug"), NULL);
 
 	/* Test error on port argument that is not a number */
 	zassert_equal(EC_ERROR_PARAM1,
-		      shell_execute_cmd(get_ec_shell(),
-					"typec test1"), NULL);
+		      shell_execute_cmd(get_ec_shell(), "typec test1"), NULL);
 
 	/* Test error on invalid port number */
 	zassert_equal(EC_ERROR_PARAM1,
-		      shell_execute_cmd(get_ec_shell(),
-					"typec 5"), NULL);
+		      shell_execute_cmd(get_ec_shell(), "typec 5"), NULL);
 
 	/*
 	 * Test success on correct port number. Command should print mux state
 	 * on console, but it is not possible to check that in unit test.
 	 */
 	set_proxy_get_mux_state_seq(USB_PD_MUX_TBT_COMPAT_ENABLED);
-	zassert_equal(EC_SUCCESS,
-		      shell_execute_cmd(get_ec_shell(),
-					"typec 1"), NULL);
+	zassert_equal(EC_SUCCESS, shell_execute_cmd(get_ec_shell(), "typec 1"),
+		      NULL);
 	CHECK_PROXY_FAKE_CALL_CNT(proxy_get, NUM_OF_PROXY);
 
 	/* Test setting none mode */
 	reset_proxy_fakes();
 	exp_mode = USB_PD_MUX_NONE;
 	zassert_equal(EC_SUCCESS,
-		      shell_execute_cmd(get_ec_shell(),
-					"typec 1 none"), NULL);
+		      shell_execute_cmd(get_ec_shell(), "typec 1 none"), NULL);
 	CHECK_PROXY_FAKE_CALL_CNT_MUX_STATE(proxy_set, NUM_OF_PROXY, exp_mode);
 	/* Mux will enter low power mode */
 	CHECK_PROXY_FAKE_CALL_CNT(proxy_enter_low_power_mode, NUM_OF_PROXY);
 
 	/* Polarity is set based on PD */
 	polarity = polarity_rm_dts(pd_get_polarity(USBC_PORT_C1)) ?
-			USB_PD_MUX_POLARITY_INVERTED : 0;
+			   USB_PD_MUX_POLARITY_INVERTED :
+			   0;
 
 	/* Test setting USB mode */
 	reset_proxy_fakes();
 	exp_mode = USB_PD_MUX_USB_ENABLED | polarity;
 	zassert_equal(EC_SUCCESS,
-		      shell_execute_cmd(get_ec_shell(),
-					"typec 1 usb"), NULL);
+		      shell_execute_cmd(get_ec_shell(), "typec 1 usb"), NULL);
 	CHECK_PROXY_FAKE_CALL_CNT_MUX_STATE(proxy_set, NUM_OF_PROXY, exp_mode);
 	/* Mux will exit low power mode */
 	CHECK_PROXY_FAKE_CALL_CNT(proxy_init, NUM_OF_PROXY);
@@ -846,16 +857,14 @@ ZTEST(usb_init_mux, test_usb_mux_typec_command)
 	reset_proxy_fakes();
 	exp_mode = USB_PD_MUX_DP_ENABLED | polarity;
 	zassert_equal(EC_SUCCESS,
-		      shell_execute_cmd(get_ec_shell(),
-					"typec 1 dp"), NULL);
+		      shell_execute_cmd(get_ec_shell(), "typec 1 dp"), NULL);
 	CHECK_PROXY_FAKE_CALL_CNT_MUX_STATE(proxy_set, NUM_OF_PROXY, exp_mode);
 
 	/* Test setting dock mode */
 	reset_proxy_fakes();
 	exp_mode = USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED | polarity;
 	zassert_equal(EC_SUCCESS,
-		      shell_execute_cmd(get_ec_shell(),
-					"typec 1 dock"), NULL);
+		      shell_execute_cmd(get_ec_shell(), "typec 1 dock"), NULL);
 	CHECK_PROXY_FAKE_CALL_CNT_MUX_STATE(proxy_set, NUM_OF_PROXY, exp_mode);
 }
 
@@ -867,7 +876,7 @@ void usb_uninit_mux_before(void *state)
 	set_test_runner_tid();
 
 	/* Makes sure that usb muxes of port 1 are not init */
-	usb_muxes[USBC_PORT_C1].flags = USB_MUX_FLAG_RESETS_IN_G3;
+	proxy_mux_0.flags = USB_MUX_FLAG_RESETS_IN_G3;
 	hook_notify(HOOK_CHIPSET_HARD_OFF);
 	reset_proxy_fakes();
 }
diff --git a/zephyr/test/drivers/src/usb_pd_host_cmd.c b/zephyr/test/drivers/default/src/usb_pd_host_cmd.c
index 5eb589043c..c8851fbeb1 100644
--- a/zephyr/test/drivers/src/usb_pd_host_cmd.c
+++ b/zephyr/test/drivers/default/src/usb_pd_host_cmd.c
@@ -1,10 +1,10 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <zephyr/zephyr.h>
-#include <ztest.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
 
 #include "ec_commands.h"
 #include "host_command.h"
@@ -14,8 +14,7 @@ ZTEST_USER(usb_pd_host_cmd, test_host_command_hc_pd_ports)
 {
 	struct ec_response_usb_pd_ports response;
 	struct host_cmd_handler_args args =
-		BUILD_HOST_COMMAND_RESPONSE(EC_CMD_USB_PD_PORTS, 0,
-					    response);
+		BUILD_HOST_COMMAND_RESPONSE(EC_CMD_USB_PD_PORTS, 0, response);
 
 	zassert_ok(host_command_process(&args), NULL);
 	zassert_ok(args.result, NULL);
diff --git a/zephyr/test/drivers/default/src/vboot_hash.c b/zephyr/test/drivers/default/src/vboot_hash.c
new file mode 100644
index 0000000000..546fc8135f
--- /dev/null
+++ b/zephyr/test/drivers/default/src/vboot_hash.c
@@ -0,0 +1,103 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+#include <sha256.h>
+
+#include "ec_commands.h"
+#include "host_command.h"
+#include "test/drivers/test_state.h"
+
+ZTEST_USER(vboot_hash, test_hostcmd_abort)
+{
+	struct ec_response_vboot_hash response;
+	struct ec_params_vboot_hash start_params = {
+		.cmd = EC_VBOOT_HASH_START,
+		.hash_type = EC_VBOOT_HASH_TYPE_SHA256,
+		.offset = EC_VBOOT_HASH_OFFSET_RO,
+		.size = 0,
+	};
+	struct host_cmd_handler_args start_args = BUILD_HOST_COMMAND(
+		EC_CMD_VBOOT_HASH, 0, response, start_params);
+	struct ec_params_vboot_hash abort_params = {
+		.cmd = EC_VBOOT_HASH_ABORT,
+	};
+	struct host_cmd_handler_args abort_args =
+		BUILD_HOST_COMMAND_PARAMS(EC_CMD_VBOOT_HASH, 0, abort_params);
+	struct ec_params_vboot_hash get_params = {
+		.cmd = EC_VBOOT_HASH_GET,
+	};
+	struct host_cmd_handler_args get_args =
+		BUILD_HOST_COMMAND(EC_CMD_VBOOT_HASH, 0, response, get_params);
+
+	/* Start hashing. The command doesn't wait to finish. */
+	zassert_ok(host_command_process(&start_args), NULL);
+	zassert_ok(start_args.result, NULL);
+	zassert_equal(start_args.response_size, sizeof(response), NULL);
+	zassert_equal(response.status, EC_VBOOT_HASH_STATUS_BUSY,
+		      "response.status = %d", response.status);
+
+	/* Abort it immediately */
+	zassert_ok(host_command_process(&abort_args), NULL);
+	zassert_ok(abort_args.result, NULL);
+
+	/* Give it a bit time. The abort is being processed in the background */
+	k_msleep(20);
+
+	/* Get the hash result. Should be NONE. */
+	zassert_ok(host_command_process(&get_args), NULL);
+	zassert_ok(get_args.result, NULL);
+	zassert_equal(get_args.response_size, sizeof(response), NULL);
+	zassert_equal(response.status, EC_VBOOT_HASH_STATUS_NONE,
+		      "response.status = %d", response.status);
+}
+
+ZTEST_USER(vboot_hash, test_hostcmd_recalc)
+{
+	struct ec_response_vboot_hash response;
+	struct ec_params_vboot_hash recalc_params = {
+		.cmd = EC_VBOOT_HASH_RECALC,
+		.hash_type = EC_VBOOT_HASH_TYPE_SHA256,
+		.offset = EC_VBOOT_HASH_OFFSET_RO,
+		.size = 0,
+	};
+	struct host_cmd_handler_args recalc_args = BUILD_HOST_COMMAND(
+		EC_CMD_VBOOT_HASH, 0, response, recalc_params);
+
+	/* Recalculate the hash. The command waits to finish. */
+	zassert_ok(host_command_process(&recalc_args), NULL);
+	zassert_ok(recalc_args.result, NULL);
+	zassert_equal(recalc_args.response_size, sizeof(response), NULL);
+	zassert_equal(response.status, EC_VBOOT_HASH_STATUS_DONE,
+		      "response.status = %d", response.status);
+	zassert_equal(response.digest_size, SHA256_DIGEST_SIZE,
+		      "response.digest_size = %d", response.digest_size);
+}
+
+ZTEST_USER(vboot_hash, test_hostcmd_hash_arbitrary_size)
+{
+	struct ec_response_vboot_hash response;
+	struct ec_params_vboot_hash recalc_params = {
+		.cmd = EC_VBOOT_HASH_RECALC,
+		.hash_type = EC_VBOOT_HASH_TYPE_SHA256,
+		.offset = 0,
+		/* arbitrary size */
+		.size = 0x12345,
+	};
+	struct host_cmd_handler_args recalc_args = BUILD_HOST_COMMAND(
+		EC_CMD_VBOOT_HASH, 0, response, recalc_params);
+
+	/* Recalculate the hash. The command waits to finish. */
+	zassert_ok(host_command_process(&recalc_args), NULL);
+	zassert_ok(recalc_args.result, NULL);
+	zassert_equal(recalc_args.response_size, sizeof(response), NULL);
+	zassert_equal(response.status, EC_VBOOT_HASH_STATUS_DONE,
+		      "response.status = %d", response.status);
+	zassert_equal(response.digest_size, SHA256_DIGEST_SIZE,
+		      "response.digest_size = %d", response.digest_size);
+}
+
+ZTEST_SUITE(vboot_hash, drivers_predicate_post_main, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/drivers/default/src/virtual_battery.c b/zephyr/test/drivers/default/src/virtual_battery.c
new file mode 100644
index 0000000000..0e69c641a5
--- /dev/null
+++ b/zephyr/test/drivers/default/src/virtual_battery.c
@@ -0,0 +1,259 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+#include "battery.h"
+#include "battery_smart.h"
+#include "ec_commands.h"
+#include "emul/emul_smart_battery.h"
+#include "host_command.h"
+#include "test/drivers/test_state.h"
+
+/* The param buffer has at most 2 msg's (write + read) and 1 byte write len. */
+static uint8_t param_buf[sizeof(struct ec_params_i2c_passthru) +
+			 sizeof(struct ec_params_i2c_passthru_msg) * 2 + 1];
+
+/* The response buffer has at most 32 bytes returned result. */
+static uint8_t response_buf[sizeof(struct ec_response_i2c_passthru) + 32];
+
+static void i2c_passthru_xfer(uint8_t port, uint8_t addr, uint8_t *write_buf,
+			      int write_len, uint8_t **read_buf, int read_len)
+{
+	struct ec_params_i2c_passthru *params =
+		(struct ec_params_i2c_passthru *)&param_buf;
+	struct ec_response_i2c_passthru *response =
+		(struct ec_response_i2c_passthru *)&response_buf;
+	struct ec_params_i2c_passthru_msg *msg = params->msg;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_SIMPLE(EC_CMD_I2C_PASSTHRU, 0);
+	uint8_t *pdata;
+	int size;
+
+	params->port = port;
+	params->num_msgs = (read_len != 0) + (write_len != 0);
+
+	size = sizeof(*params) + params->num_msgs * sizeof(*msg);
+	pdata = (uint8_t *)params + size;
+
+	if (write_len) {
+		msg->addr_flags = addr;
+		msg->len = write_len;
+		memcpy(pdata, write_buf, write_len);
+		msg++;
+	}
+
+	if (read_len) {
+		msg->addr_flags = addr | EC_I2C_FLAG_READ;
+		msg->len = read_len;
+	}
+
+	args.params = params;
+	args.params_size = size + write_len;
+	args.response = response;
+	args.response_max = sizeof(*response) + read_len;
+
+	/* Execute the I2C passthru host command */
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_ok(args.result, NULL);
+	zassert_ok(response->i2c_status, NULL);
+	zassert_equal(args.response_size, sizeof(*response) + read_len, NULL);
+
+	/* Return the data portion */
+	if (read_len)
+		*read_buf = response->data;
+}
+
+static inline void virtual_battery_xfer(uint8_t *write_buf, int write_len,
+					uint8_t **read_buf, int read_len)
+{
+	i2c_passthru_xfer(I2C_PORT_VIRTUAL_BATTERY, VIRTUAL_BATTERY_ADDR_FLAGS,
+			  write_buf, write_len, read_buf, read_len);
+}
+
+static uint16_t virtual_battery_read16(uint8_t command)
+{
+	uint8_t write_buf[1] = { command };
+	uint8_t *read_buf;
+
+	virtual_battery_xfer(write_buf, 1, &read_buf, 2);
+
+	/* Little endian */
+	return ((int)read_buf[1] << 8) | read_buf[0];
+}
+
+static void virtual_battery_write16(uint8_t command, uint16_t data)
+{
+	uint8_t write_buf[3] = { command };
+
+	*((uint16_t *)&write_buf[1]) = data;
+
+	virtual_battery_xfer(write_buf, 3, NULL, 0);
+}
+
+static int virtual_battery_read_str(uint8_t command, char **read_buf,
+				    int read_len)
+{
+	uint8_t write_buf[1] = { command };
+	int len;
+
+	virtual_battery_xfer(write_buf, 1, (uint8_t **)read_buf, read_len);
+
+	/* Battery v2 embeds the strlen in the first byte so shift 1 byte. */
+	len = **read_buf;
+	(*read_buf)++;
+
+	return len;
+}
+
+static void virtual_battery_read_data(uint8_t command, char **read_buf,
+				      int read_len)
+{
+	uint8_t write_buf[1] = { command };
+
+	virtual_battery_xfer(write_buf, 1, (uint8_t **)read_buf, read_len);
+}
+
+#define BATTERY_NODE DT_NODELABEL(battery)
+
+ZTEST_USER(virtual_battery, test_read_regs)
+{
+	const struct emul *emul = EMUL_DT_GET(BATTERY_NODE);
+	struct sbat_emul_bat_data *bat = sbat_emul_get_bat_data(emul);
+	int16_t int16;
+	uint16_t word;
+	int expected;
+	char *str;
+	int len;
+
+	/*
+	 * Iterate all the registers, which issues the I2C passthru host
+	 * command to query the emulated smart battery. Most of the values
+	 * are the same as the emulated battery, but with some exceptions.
+	 */
+	word = virtual_battery_read16(SB_BATTERY_MODE);
+	zassert_equal(bat->mode, word, "%d != %d", bat->mode, word);
+
+	word = virtual_battery_read16(SB_SERIAL_NUMBER);
+	zassert_equal(bat->sn, word, "%d != %d", bat->sn, word);
+
+	word = virtual_battery_read16(SB_VOLTAGE);
+	zassert_equal(bat->volt, word, "%d != %d", bat->volt, word);
+
+	/* The expected value is calculated */
+	expected = 100 * bat->cap / bat->full_cap;
+	word = virtual_battery_read16(SB_RELATIVE_STATE_OF_CHARGE);
+
+	zassert_equal(expected, word, "%d != %d", expected, word);
+
+	word = virtual_battery_read16(SB_TEMPERATURE);
+	zassert_equal(bat->temp, word, "%d != %d", bat->temp, word);
+
+	int16 = virtual_battery_read16(SB_CURRENT);
+	zassert_equal(bat->cur, int16, "%d != %d", bat->cur, int16);
+
+	int16 = virtual_battery_read16(SB_AVERAGE_CURRENT);
+	zassert_equal(bat->avg_cur, int16, "%d != %d", bat->avg_cur, int16);
+
+	/* The virtual battery modifies the return value to make kernel happy */
+	expected = BATTERY_LEVEL_SHUTDOWN;
+	word = virtual_battery_read16(SB_MAX_ERROR);
+	zassert_equal(expected, word, "%d != %d", expected, word);
+
+	word = virtual_battery_read16(SB_FULL_CHARGE_CAPACITY);
+	zassert_equal(bat->full_cap, word, "%d != %d", bat->full_cap, word);
+
+	word = virtual_battery_read16(SB_CYCLE_COUNT);
+	zassert_equal(bat->cycle_count, word, "%d != %d", bat->cycle_count,
+		      word);
+
+	word = virtual_battery_read16(SB_DESIGN_CAPACITY);
+	zassert_equal(bat->design_cap, word, "%d != %d", bat->design_cap, word);
+
+	word = virtual_battery_read16(SB_REMAINING_CAPACITY);
+	zassert_equal(bat->cap, word, "%d != %d", bat->cap, word);
+
+	len = virtual_battery_read_str(SB_MANUFACTURER_NAME, &str,
+				       SB_MAX_STR_SIZE);
+	zassert_equal(bat->mf_name_len, len, "%d != %d", bat->mf_name_len, len);
+	zassert_mem_equal(str, bat->mf_name, bat->mf_name_len, "%s != %s", str,
+			  bat->mf_name);
+
+	len = virtual_battery_read_str(SB_DEVICE_NAME, &str, SB_MAX_STR_SIZE);
+	zassert_equal(bat->dev_name_len, len, "%d != %d", bat->dev_name_len,
+		      len);
+	zassert_mem_equal(str, bat->dev_name, bat->dev_name_len, "%s != %s",
+			  str, bat->dev_name);
+
+	len = virtual_battery_read_str(SB_DEVICE_CHEMISTRY, &str,
+				       SB_MAX_STR_SIZE);
+	zassert_equal(bat->dev_chem_len, len, "%d != %d", bat->dev_chem_len,
+		      len);
+	zassert_mem_equal(str, bat->dev_chem, bat->dev_chem_len, "%s != %s",
+			  str, bat->dev_chem);
+
+	/* Use the API to query the expected value */
+	battery_time_to_full(&expected);
+	word = virtual_battery_read16(SB_AVERAGE_TIME_TO_FULL);
+	zassert_equal(expected, word, "%d != %d", expected, word);
+
+	battery_time_to_empty(&expected);
+	word = virtual_battery_read16(SB_AVERAGE_TIME_TO_EMPTY);
+	zassert_equal(expected, word, "%d != %d", expected, word);
+
+	battery_run_time_to_empty(&expected);
+	word = virtual_battery_read16(SB_RUN_TIME_TO_EMPTY);
+	zassert_equal(expected, word, "%d != %d", expected, word);
+
+	word = virtual_battery_read16(SB_CHARGING_CURRENT);
+	zassert_equal(bat->desired_charg_cur, word, "%d != %d",
+		      bat->desired_charg_cur, word);
+
+	word = virtual_battery_read16(SB_CHARGING_VOLTAGE);
+	zassert_equal(bat->desired_charg_volt, word, "%d != %d",
+		      bat->desired_charg_volt, word);
+
+	word = virtual_battery_read16(SB_MANUFACTURE_DATE);
+	zassert_equal(bat->mf_date, word, "%d != %d", bat->mf_date, word);
+
+	/* Hard-coded return value: v1.1 without PEC */
+	expected = 0x0011;
+	word = virtual_battery_read16(SB_SPECIFICATION_INFO);
+	zassert_equal(expected, word, "%d != %d", expected, word);
+
+	zassume_ok(battery_status(&expected));
+	word = virtual_battery_read16(SB_BATTERY_STATUS);
+	zassert_equal(expected, word, "%d != %d", expected, word);
+
+	zassume_ok(battery_design_voltage(&expected));
+	word = virtual_battery_read16(SB_DESIGN_VOLTAGE);
+	zassert_equal(expected, word, "%d != %d", expected, word);
+
+	virtual_battery_read_data(SB_MANUFACTURER_DATA, &str, bat->mf_data_len);
+	zassert_mem_equal(str, bat->mf_data, bat->mf_data_len, "%s != %s", str,
+			  bat->mf_data);
+
+	/* At present, this command is used nowhere in our codebase. */
+	virtual_battery_read_data(SB_MANUFACTURE_INFO, &str, bat->mf_info_len);
+	zassert_mem_equal(str, bat->mf_info, bat->mf_info_len, "%s != %s", str,
+			  bat->mf_info);
+}
+
+ZTEST_USER(virtual_battery, test_write_mfgacc)
+{
+	struct sbat_emul_bat_data *bat;
+	const struct emul *emul = EMUL_DT_GET(BATTERY_NODE);
+	uint16_t cmd = PARAM_OPERATION_STATUS;
+
+	bat = sbat_emul_get_bat_data(emul);
+
+	/* Write the command to the SB_MANUFACTURER_ACCESS and check */
+	virtual_battery_write16(SB_MANUFACTURER_ACCESS, cmd);
+	zassert_equal(bat->mf_access, cmd, "%d != %d", bat->mf_access, cmd);
+}
+
+ZTEST_SUITE(virtual_battery, drivers_predicate_post_main, NULL, NULL, NULL,
+	    NULL);
diff --git a/zephyr/test/drivers/default/src/vstore.c b/zephyr/test/drivers/default/src/vstore.c
new file mode 100644
index 0000000000..b4264aaeb3
--- /dev/null
+++ b/zephyr/test/drivers/default/src/vstore.c
@@ -0,0 +1,230 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <setjmp.h>
+
+#include <console.h>
+#include <zephyr/fff.h>
+#include <zephyr/shell/shell_dummy.h>
+#include <zephyr/ztest.h>
+
+#include "ec_commands.h"
+#include "host_command.h"
+#include "system.h"
+#include "system_fake.h"
+#include "vstore.h"
+#include "test/drivers/test_state.h"
+
+ZTEST_SUITE(vstore, drivers_predicate_post_main, NULL, NULL, NULL, NULL);
+
+ZTEST_USER(vstore, test_vstore_info)
+{
+	struct ec_response_vstore_info response;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_RESPONSE(EC_CMD_VSTORE_INFO, 0, response);
+
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_ok(args.result, NULL);
+	zassert_equal(args.response_size, sizeof(response), NULL);
+	zassert_equal(response.slot_count, CONFIG_VSTORE_SLOT_COUNT,
+		      "response.slot_count = %d", response.slot_count);
+	zassert_equal(response.slot_locked, 0, "response.slot_locked = %#x",
+		      response.slot_locked);
+}
+
+ZTEST_USER(vstore, test_vstore_read)
+{
+	struct ec_params_vstore_read params = {
+		.slot = 0,
+	};
+	struct ec_response_vstore_read response;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_VSTORE_READ, 0, response, params);
+	uint8_t expect[EC_VSTORE_SLOT_SIZE] = {}; /* data should start as 0 */
+
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_ok(args.result, NULL);
+	zassert_equal(args.response_size, sizeof(response), NULL);
+	zassert_mem_equal(expect, response.data, EC_VSTORE_SLOT_SIZE,
+			  "response.data did not match");
+}
+
+ZTEST_USER(vstore, test_vstore_read_bad_slot)
+{
+	struct ec_params_vstore_read params = {
+		.slot = CONFIG_VSTORE_SLOT_COUNT,
+	};
+	struct ec_response_vstore_read response;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_VSTORE_READ, 0, response, params);
+
+	zassert_equal(host_command_process(&args), EC_RES_INVALID_PARAM,
+		      "Failed to fail on invalid slot %d", params.slot);
+}
+
+ZTEST_USER(vstore, test_vstore_write_bad_slot)
+{
+	struct ec_params_vstore_write params = {
+		.slot = CONFIG_VSTORE_SLOT_COUNT,
+		.data = {},
+	};
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_PARAMS(EC_CMD_VSTORE_WRITE, 0, params);
+
+	zassert_equal(host_command_process(&args), EC_RES_INVALID_PARAM,
+		      "Failed to fail on invalid slot %d", params.slot);
+}
+
+static void do_vstore_write_read(unsigned int slot)
+{
+	struct ec_params_vstore_write write_params = {
+		.slot = slot,
+		/* .data is set up below */
+	};
+	struct host_cmd_handler_args write_args =
+		BUILD_HOST_COMMAND_PARAMS(EC_CMD_VSTORE_WRITE, 0, write_params);
+	struct ec_params_vstore_read read_params = {
+		.slot = slot,
+	};
+	struct ec_response_vstore_read read_response;
+	struct host_cmd_handler_args read_args = BUILD_HOST_COMMAND(
+		EC_CMD_VSTORE_READ, 0, read_response, read_params);
+	struct ec_response_vstore_info info_response;
+	struct host_cmd_handler_args info_args = BUILD_HOST_COMMAND_RESPONSE(
+		EC_CMD_VSTORE_INFO, 0, info_response);
+	int i;
+
+	for (i = 0; i < EC_VSTORE_SLOT_SIZE; i++)
+		write_params.data[i] = i + 1;
+
+	/* Write to a slot */
+	zassert_ok(host_command_process(&write_args), NULL);
+	zassert_ok(write_args.result, NULL);
+
+	/* Check that it is now locked */
+	zassert_ok(host_command_process(&info_args), NULL);
+	zassert_ok(info_args.result, NULL);
+	zassert_equal(info_args.response_size, sizeof(info_response), NULL);
+	zassert_equal(info_response.slot_count, CONFIG_VSTORE_SLOT_COUNT,
+		      "response.slot_count = %d", info_response.slot_count);
+	zassert_equal(info_response.slot_locked, 1 << slot,
+		      "response.slot_locked = %#x", info_response.slot_locked);
+
+	/* Read to check data */
+	zassert_ok(host_command_process(&read_args), NULL);
+	zassert_ok(read_args.result, NULL);
+	zassert_equal(read_args.response_size, sizeof(read_response), NULL);
+	zassert_mem_equal(write_params.data, read_response.data,
+			  EC_VSTORE_SLOT_SIZE, "response.data did not match");
+
+	/* Try to write to it again */
+	zassert_equal(host_command_process(&write_args), EC_RES_ACCESS_DENIED,
+		      "Failed to fail on writing locked slot %d",
+		      write_params.slot);
+
+	/* Check that it is still locked after that attempt */
+	zassert_ok(host_command_process(&info_args), NULL);
+	zassert_ok(info_args.result, NULL);
+	zassert_equal(info_args.response_size, sizeof(info_response), NULL);
+	zassert_equal(info_response.slot_count, CONFIG_VSTORE_SLOT_COUNT,
+		      "response.slot_count = %d", info_response.slot_count);
+	zassert_equal(info_response.slot_locked, 1 << slot,
+		      "response.slot_locked = %#x", info_response.slot_locked);
+
+	/* Read to check the data didn't change */
+	zassert_ok(host_command_process(&read_args), NULL);
+	zassert_ok(read_args.result, NULL);
+	zassert_equal(read_args.response_size, sizeof(read_response), NULL);
+	zassert_mem_equal(write_params.data, read_response.data,
+			  EC_VSTORE_SLOT_SIZE, "response.data did not match");
+
+	/* Clear locks and try the write again, this time with zero bytes  */
+	vstore_clear_lock();
+	memset(write_params.data, '\0', EC_VSTORE_SLOT_SIZE);
+	zassert_ok(host_command_process(&write_args), NULL);
+	zassert_ok(write_args.result, NULL);
+
+	/* Check that it is now locked */
+	zassert_ok(host_command_process(&info_args), NULL);
+	zassert_ok(info_args.result, NULL);
+	zassert_equal(info_args.response_size, sizeof(info_response), NULL);
+	zassert_equal(info_response.slot_count, CONFIG_VSTORE_SLOT_COUNT,
+		      "response.slot_count = %d", info_response.slot_count);
+	zassert_equal(info_response.slot_locked, 1 << slot,
+		      "response.slot_locked = %#x", info_response.slot_locked);
+
+	/* Read to check the data changed */
+	zassert_ok(host_command_process(&read_args), NULL);
+	zassert_ok(read_args.result, NULL);
+	zassert_equal(read_args.response_size, sizeof(read_response), NULL);
+	zassert_mem_equal(write_params.data, read_response.data,
+			  EC_VSTORE_SLOT_SIZE, "response.data did not match");
+
+	/* Clear locks to put things into a normal state */
+	vstore_clear_lock();
+}
+
+ZTEST_USER(vstore, test_vstore_write_read)
+{
+	/* Try on two different slots */
+	zassert_true(CONFIG_VSTORE_SLOT_COUNT >= 2,
+		     "Please set CONFIG_VSTORE_SLOT_COUNT to >= 2");
+	do_vstore_write_read(0);
+	do_vstore_write_read(1);
+}
+
+ZTEST_USER(vstore, test_vstore_state)
+{
+	struct ec_params_vstore_write write_params = {
+		.slot = 0,
+		/* .data is set up below */
+	};
+	struct host_cmd_handler_args write_args =
+		BUILD_HOST_COMMAND_PARAMS(EC_CMD_VSTORE_WRITE, 0, write_params);
+
+	struct ec_params_reboot_ec reboot_params = {
+		.cmd = EC_REBOOT_JUMP_RW,
+	};
+	struct host_cmd_handler_args reboot_args =
+		BUILD_HOST_COMMAND_PARAMS(EC_CMD_REBOOT_EC, 0, reboot_params);
+	struct ec_response_vstore_info info_response;
+	struct host_cmd_handler_args info_args = BUILD_HOST_COMMAND_RESPONSE(
+		EC_CMD_VSTORE_INFO, 0, info_response);
+	jmp_buf env;
+	int i;
+
+	shell_backend_dummy_clear_output(get_ec_shell());
+	system_common_pre_init();
+
+	for (i = 0; i < EC_VSTORE_SLOT_SIZE; i++)
+		write_params.data[i] = i + 1;
+
+	/* Write to a slot */
+	zassert_ok(host_command_process(&write_args), NULL);
+	zassert_ok(write_args.result, NULL);
+
+	/* Set up so we get back to this test on a reboot */
+	if (!setjmp(env)) {
+		system_fake_setenv(&env);
+
+		/* Reboot to RW  */
+		zassert_ok(host_command_process(&reboot_args), NULL);
+
+		/* Does not return unless something went wrong */
+		zassert_unreachable("Failed to reboot");
+	}
+
+	/* the reboot should end up here: check the slot is still locked */
+	zassert_ok(host_command_process(&info_args), NULL);
+	zassert_ok(info_args.result, NULL);
+	zassert_equal(info_args.response_size, sizeof(info_response), NULL);
+	zassert_equal(info_response.slot_count, CONFIG_VSTORE_SLOT_COUNT,
+		      "response.slot_count = %d", info_response.slot_count);
+	zassert_equal(info_response.slot_locked, 1 << 0,
+		      "response.slot_locked = %#x", info_response.slot_locked);
+
+	/* Clear locks to put things into a normal state */
+	vstore_clear_lock();
+}
diff --git a/zephyr/test/drivers/src/watchdog.c b/zephyr/test/drivers/default/src/watchdog.c
index 8b91247f12..958aa3eaaa 100644
--- a/zephyr/test/drivers/src/watchdog.c
+++ b/zephyr/test/drivers/default/src/watchdog.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -12,12 +12,12 @@
 #include <zephyr/drivers/watchdog.h>
 
 #include <zephyr/logging/log.h>
-#include <zephyr/zephyr.h>
-#include <ztest.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
 
 #include "common.h"
 #include "ec_tasks.h"
-#include "fff.h"
+#include <zephyr/fff.h>
 #include "hooks.h"
 #include "test/drivers/stubs.h"
 #include "watchdog.h"
@@ -53,8 +53,8 @@ static void watchdog_before(void *state)
 	/* When shuffling need watchdog initialized and running
 	 * for other tests.
 	 */
-	(void) watchdog_init();
-	(void) wdt_setup(wdt, 0);
+	(void)watchdog_init();
+	(void)wdt_setup(wdt, 0);
 }
 
 /**
diff --git a/zephyr/projects/brya/prj_ghost.conf b/zephyr/test/drivers/dps/CMakeLists.txt
index 666aeb1dd0..0e175e182f 100644
--- a/zephyr/projects/brya/prj_ghost.conf
+++ b/zephyr/test/drivers/dps/CMakeLists.txt
@@ -1,5 +1,5 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
-CONFIG_PLATFORM_EC_CHARGESPLASH=y
+target_sources(app PRIVATE src/dps.c)
diff --git a/zephyr/test/drivers/dps/prj.conf b/zephyr/test/drivers/dps/prj.conf
new file mode 100644
index 0000000000..1f1e1c5d0e
--- /dev/null
+++ b/zephyr/test/drivers/dps/prj.conf
@@ -0,0 +1,5 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_PLATFORM_EC_USB_PD_DPS=y
diff --git a/zephyr/test/drivers/dps/src/dps.c b/zephyr/test/drivers/dps/src/dps.c
new file mode 100644
index 0000000000..d445767df4
--- /dev/null
+++ b/zephyr/test/drivers/dps/src/dps.c
@@ -0,0 +1,262 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/ztest.h>
+
+#include "builtin/stdio.h"
+#include "console.h"
+#include "dps.h"
+#include "test/drivers/test_state.h"
+#include "timer.h"
+
+struct dps_fixture {
+	struct dps_config_t saved_config;
+	int saved_debug_level;
+};
+
+static void *dps_config_setup(void)
+{
+	static struct dps_fixture fixture;
+
+	fixture.saved_config = *dps_get_config();
+	fixture.saved_debug_level = *dps_get_debug_level();
+
+	return &fixture;
+}
+
+static void dps_config_before(void *data)
+{
+	dps_enable(true);
+}
+
+static void dps_config_after(void *data)
+{
+	struct dps_fixture *f = (struct dps_fixture *)data;
+
+	*dps_get_config() = f->saved_config;
+	*dps_get_debug_level() = f->saved_debug_level;
+	dps_enable(true);
+}
+
+ZTEST_F(dps, test_enable)
+{
+	zassert_true(dps_is_enabled(), NULL);
+	dps_enable(false);
+	zassert_false(dps_is_enabled(), NULL);
+	dps_enable(true);
+	zassert_true(dps_is_enabled(), NULL);
+}
+
+ZTEST_F(dps, test_config)
+{
+	struct dps_config_t *config = dps_get_config();
+
+	zassert_true(config->k_less_pwr <= config->k_more_pwr, NULL);
+	zassert_true(config->k_less_pwr > 0 && config->k_less_pwr < 100, NULL);
+	zassert_true(config->k_more_pwr > 0 && config->k_more_pwr < 100, NULL);
+
+	zassert_ok(dps_init(), NULL);
+	*config = fixture->saved_config;
+
+	config->k_less_pwr = config->k_more_pwr + 1;
+	zassert_equal(dps_init(), EC_ERROR_INVALID_CONFIG, NULL);
+	*config = fixture->saved_config;
+
+	config->k_more_pwr = 101;
+	zassert_equal(dps_init(), EC_ERROR_INVALID_CONFIG, NULL);
+	*config = fixture->saved_config;
+}
+
+ZTEST(dps, console_cmd__print_info)
+{
+	/* Print current status to console */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "dps"), NULL);
+}
+
+ZTEST(dps, console_cmd__enable)
+{
+	/* Disable DPS first, then try enabling */
+	dps_enable(false);
+	zassert_false(dps_is_enabled(), NULL);
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "dps en"), NULL);
+
+	zassert_true(dps_is_enabled(), NULL);
+}
+
+ZTEST(dps, console_cmd__disable)
+{
+	/* Should already by enabled due to before() function */
+	zassume_true(dps_is_enabled(), NULL);
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "dps dis"), NULL);
+
+	zassert_false(dps_is_enabled(), NULL);
+}
+
+ZTEST(dps, console_cmd__fakepwr_print)
+{
+	/* Print current fake power status to console */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "dps fakepwr"), NULL);
+}
+
+ZTEST(dps, console_cmd__fakepwr_enable_disable)
+{
+	zassume_false(dps_is_fake_enabled(),
+		      "fakepwr shouldn't be enabled by default");
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "dps fakepwr 100 200"),
+		   NULL);
+	zassert_true(dps_is_fake_enabled(), NULL);
+	zassert_equal(100, dps_get_fake_mv(), "Got fake_mv=%d",
+		      dps_get_fake_mv());
+	zassert_equal(200, dps_get_fake_ma(), "Got fake_ma=%d",
+		      dps_get_fake_ma());
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "dps fakepwr dis"), NULL);
+	zassert_false(dps_is_fake_enabled(), NULL);
+}
+
+ZTEST(dps, console_cmd__fakepwr_invalid)
+{
+	/* Various invalid parameters */
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "dps fakepwr 100"), NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "dps fakepwr -100 -200"),
+		   NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "dps fakepwr 100 -200"),
+		   NULL);
+}
+
+ZTEST(dps, console_cmd__debuglevel)
+{
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "dps debug 999"), NULL);
+
+	zassert_equal(999, *dps_get_debug_level(), "Debug level is %d",
+		      *dps_get_debug_level());
+}
+
+ZTEST(dps, console_cmd__setkmore)
+{
+	struct dps_config_t *config = dps_get_config();
+	char cmd[32];
+
+	/* Try some invalid requests first */
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "dps setkmore"), NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "dps setkmore 101"),
+		   NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "dps setkmore 0"), NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "dps setkmore -1"), NULL);
+
+	zassert_true(crec_snprintf(cmd, sizeof(cmd), "dps setkmore %d",
+				   config->k_less_pwr - 1) > 0,
+		     NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), cmd), NULL);
+
+	/* Adjust k_more_pwr to be one over k_less_pwr */
+	zassert_true(crec_snprintf(cmd, sizeof(cmd), "dps setkmore %d",
+				   config->k_less_pwr + 1) > 0,
+		     NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), cmd), NULL);
+
+	zassert_equal(config->k_less_pwr + 1, config->k_more_pwr,
+		      "k_more_pwr is %d but should be %d", config->k_more_pwr,
+		      config->k_less_pwr + 1);
+}
+
+ZTEST(dps, console_cmd__setkless)
+{
+	struct dps_config_t *config = dps_get_config();
+	char cmd[32];
+
+	/* Try some invalid requests first */
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "dps setkless"), NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "dps setkless 101"),
+		   NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "dps setkless 0"), NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "dps setkless -1"), NULL);
+
+	zassert_true(crec_snprintf(cmd, sizeof(cmd), "dps setkless %d",
+				   config->k_more_pwr + 1) > 0,
+		     NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), cmd), NULL);
+
+	/* Adjust k_less_pwr to be one under k_more_pwr */
+	zassert_true(crec_snprintf(cmd, sizeof(cmd), "dps setkless %d",
+				   config->k_more_pwr - 1) > 0,
+		     NULL);
+	zassert_ok(shell_execute_cmd(get_ec_shell(), cmd), NULL);
+
+	zassert_equal(config->k_more_pwr - 1, config->k_less_pwr,
+		      "k_less_pwr is %d but should be %d", config->k_less_pwr,
+		      config->k_more_pwr - 1);
+}
+
+ZTEST(dps, console_cmd__setksample)
+{
+	struct dps_config_t *config = dps_get_config();
+
+	/* Try some invalid requests first */
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "dps setksample"), NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "dps setksample -1"),
+		   NULL);
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "dps setksample 999"),
+		   NULL);
+
+	zassert_equal(999, config->k_sample, "k_sample is %d",
+		      config->k_sample);
+}
+
+ZTEST(dps, console_cmd__setkwindow)
+{
+	struct dps_config_t *config = dps_get_config();
+
+	/* Try some invalid requests first */
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "dps setkwin"), NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "dps setkwin -1"), NULL);
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "dps setkwin 4"), NULL);
+
+	zassert_equal(4, config->k_window, "k_window is %d", config->k_window);
+}
+
+ZTEST(dps, console_cmd__settcheck)
+{
+	struct dps_config_t *config = dps_get_config();
+
+	/* Try some invalid requests first */
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "dps settcheck"), NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "dps settcheck -1"),
+		   NULL);
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "dps settcheck 5"), NULL);
+
+	zassert_equal(5 * SECOND, config->t_check, "t_check is %d",
+		      config->t_check);
+}
+
+ZTEST(dps, console_cmd__settstable)
+{
+	struct dps_config_t *config = dps_get_config();
+
+	/* Try some invalid requests first */
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "dps settstable"), NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "dps settstable -1"),
+		   NULL);
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "dps settstable 6"), NULL);
+
+	zassert_equal(6 * SECOND, config->t_stable, "t_stable is %d",
+		      config->t_stable);
+}
+
+ZTEST(dps, console_cmd__invalid)
+{
+	/* Non-existent subcommand should fail */
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "dps foobar xyz"), NULL);
+}
+
+ZTEST_SUITE(dps, drivers_predicate_pre_main, dps_config_setup,
+	    dps_config_before, dps_config_after, NULL);
diff --git a/zephyr/test/drivers/host_cmd/CMakeLists.txt b/zephyr/test/drivers/host_cmd/CMakeLists.txt
new file mode 100644
index 0000000000..ddd8e4d54c
--- /dev/null
+++ b/zephyr/test/drivers/host_cmd/CMakeLists.txt
@@ -0,0 +1,17 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_sources(app PRIVATE
+    src/battery_cut_off.c
+    src/get_panic_info.c
+    src/get_pd_port_caps.c
+    src/host_event_commands.c
+    src/host_event_commands_deprecated.c
+    src/keyboard_mkbp.c
+    src/motion_sense.c
+    src/pd_control.c
+    src/pd_chip_info.c
+    src/pd_log.c
+    src/usb_pd_control.c
+)
diff --git a/zephyr/test/drivers/host_cmd/src/battery_cut_off.c b/zephyr/test/drivers/host_cmd/src/battery_cut_off.c
new file mode 100644
index 0000000000..ed9d96481d
--- /dev/null
+++ b/zephyr/test/drivers/host_cmd/src/battery_cut_off.c
@@ -0,0 +1,107 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/drivers/emul.h>
+#include <zephyr/ztest.h>
+
+#include "battery.h"
+#include "emul/emul_common_i2c.h"
+#include "emul/emul_smart_battery.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+struct host_cmd_battery_cut_off_fixture {
+	const struct emul *emul;
+	struct i2c_common_emul_data *i2c_emul;
+};
+
+static void *host_cmd_battery_cut_off_setup(void)
+{
+	static struct host_cmd_battery_cut_off_fixture fixture = {
+		.emul = EMUL_DT_GET(DT_NODELABEL(battery)),
+	};
+
+	fixture.i2c_emul = emul_smart_battery_get_i2c_common_data(fixture.emul);
+
+	return &fixture;
+}
+
+static void host_cmd_battery_cut_off_before(void *f)
+{
+	ARG_UNUSED(f);
+	test_set_battery_level(75);
+}
+
+static void host_cmd_battery_cut_off_after(void *f)
+{
+	struct host_cmd_battery_cut_off_fixture *fixture = f;
+
+	i2c_common_emul_set_write_fail_reg(fixture->i2c_emul,
+					   I2C_COMMON_EMUL_NO_FAIL_REG);
+	set_ac_enabled(true);
+	hook_notify(HOOK_AC_CHANGE);
+	k_msleep(500);
+}
+
+ZTEST_SUITE(host_cmd_battery_cut_off, drivers_predicate_post_main,
+	    host_cmd_battery_cut_off_setup, host_cmd_battery_cut_off_before,
+	    host_cmd_battery_cut_off_after, NULL);
+
+ZTEST_USER_F(host_cmd_battery_cut_off, test_fail_sb_write)
+{
+	int rv;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_SIMPLE(EC_CMD_BATTERY_CUT_OFF, UINT8_C(0));
+
+	/* Force a failure on the battery i2c write to 0x00 */
+	i2c_common_emul_set_write_fail_reg(fixture->i2c_emul, 0);
+
+	rv = host_command_process(&args);
+	zassert_equal(EC_RES_ERROR, rv, "Expected 0, but got %d", rv);
+}
+
+ZTEST_USER(host_cmd_battery_cut_off, test_cutoff_battery)
+{
+	int rv;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_SIMPLE(EC_CMD_BATTERY_CUT_OFF, UINT8_C(0));
+
+	rv = host_command_process(&args);
+	zassert_equal(EC_RES_SUCCESS, rv, "Expected 0, but got %d", rv);
+	zassert_true(battery_is_cut_off(), NULL);
+}
+
+ZTEST_USER(host_cmd_battery_cut_off, test_cutoff_v1)
+{
+	int rv;
+	struct ec_params_battery_cutoff params = {
+		.flags = 0,
+	};
+	struct host_cmd_handler_args args = BUILD_HOST_COMMAND_PARAMS(
+		EC_CMD_BATTERY_CUT_OFF, UINT8_C(1), params);
+
+	rv = host_command_process(&args);
+	zassert_equal(EC_RES_SUCCESS, rv, "Expected 0, but got %d", rv);
+	zassert_true(battery_is_cut_off(), NULL);
+}
+
+ZTEST_USER(host_cmd_battery_cut_off, test_cutoff_at_shutdown)
+{
+	int rv;
+	struct ec_params_battery_cutoff params = {
+		.flags = EC_BATTERY_CUTOFF_FLAG_AT_SHUTDOWN,
+	};
+	struct host_cmd_handler_args args = BUILD_HOST_COMMAND_PARAMS(
+		EC_CMD_BATTERY_CUT_OFF, UINT8_C(1), params);
+
+	rv = host_command_process(&args);
+	zassert_equal(EC_RES_SUCCESS, rv, "Expected 0, but got %d", rv);
+	zassert_false(battery_is_cut_off(), NULL);
+	hook_notify(HOOK_CHIPSET_SHUTDOWN);
+	zassert_true(WAIT_FOR(battery_is_cut_off(), 1500000, k_msleep(250)),
+		     NULL);
+}
diff --git a/zephyr/test/drivers/host_cmd/src/get_panic_info.c b/zephyr/test/drivers/host_cmd/src/get_panic_info.c
new file mode 100644
index 0000000000..04b83d07f9
--- /dev/null
+++ b/zephyr/test/drivers/host_cmd/src/get_panic_info.c
@@ -0,0 +1,98 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/ztest.h>
+
+#include "host_command.h"
+#include "panic.h"
+#include "test/drivers/test_state.h"
+
+struct host_cmd_get_panic_info_fixture {
+	struct panic_data saved_pdata;
+};
+
+static void *host_cmd_get_panic_info_setup(void)
+{
+	static struct host_cmd_get_panic_info_fixture fixture = { 0 };
+
+	return &fixture;
+}
+
+static void host_cmd_get_panic_info_before(void *f)
+{
+	struct host_cmd_get_panic_info_fixture *fixture = f;
+	struct panic_data *pdata = get_panic_data_write();
+
+	fixture->saved_pdata = *pdata;
+}
+
+static void host_cmd_get_panic_info_after(void *f)
+{
+	struct host_cmd_get_panic_info_fixture *fixture = f;
+	struct panic_data *pdata = get_panic_data_write();
+
+	*pdata = fixture->saved_pdata;
+}
+
+ZTEST_SUITE(host_cmd_get_panic_info, drivers_predicate_post_main,
+	    host_cmd_get_panic_info_setup, host_cmd_get_panic_info_before,
+	    host_cmd_get_panic_info_after, NULL);
+
+ZTEST_USER(host_cmd_get_panic_info, test_get_panic_info)
+{
+	struct panic_data *pdata = get_panic_data_write();
+	struct panic_data response = { 0 };
+	struct host_cmd_handler_args args = BUILD_HOST_COMMAND_RESPONSE(
+		EC_CMD_GET_PANIC_INFO, UINT8_C(0), response);
+
+	pdata->arch = 0;
+	pdata->struct_version = 1;
+	pdata->flags = 2;
+	pdata->reserved = 3;
+	pdata->struct_size = sizeof(struct panic_data);
+	pdata->magic = PANIC_DATA_MAGIC;
+
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_equal(sizeof(struct panic_data), args.response_size, NULL);
+	zassert_equal(0, response.arch, NULL);
+	zassert_equal(1, response.struct_version, NULL);
+	zassert_equal(2, response.flags, NULL);
+	zassert_equal(3, response.reserved, NULL);
+	zassert_equal(sizeof(struct panic_data), response.struct_size, NULL);
+	zassert_equal(PANIC_DATA_MAGIC, response.magic, NULL);
+	zassert_equal(pdata->flags & PANIC_DATA_FLAG_OLD_HOSTCMD,
+		      PANIC_DATA_FLAG_OLD_HOSTCMD, NULL);
+}
+
+ZTEST_USER(host_cmd_get_panic_info, test_get_panic_info_bad_magic)
+{
+	struct panic_data *pdata = get_panic_data_write();
+	struct panic_data expected = { 0 };
+	struct panic_data response = { 0 };
+	struct host_cmd_handler_args args = BUILD_HOST_COMMAND_RESPONSE(
+		EC_CMD_GET_PANIC_INFO, UINT8_C(0), response);
+
+	pdata->magic = PANIC_DATA_MAGIC + 1;
+	zassert_ok(host_command_process(&args), NULL);
+	/* Check that nothing was written to response */
+	zassert_mem_equal(&response, &expected, sizeof(struct panic_data),
+			  NULL);
+}
+
+ZTEST_USER(host_cmd_get_panic_info, test_get_panic_info_size_is_zero)
+{
+	struct panic_data *pdata = get_panic_data_write();
+	struct panic_data expected = { 0 };
+	struct panic_data response = { 0 };
+	struct host_cmd_handler_args args = BUILD_HOST_COMMAND_RESPONSE(
+		EC_CMD_GET_PANIC_INFO, UINT8_C(0), response);
+
+	pdata->magic = PANIC_DATA_MAGIC;
+	pdata->struct_size = 0;
+	zassert_ok(host_command_process(&args), NULL);
+	/* Check that nothing was written to response */
+	zassert_mem_equal(&response, &expected, sizeof(struct panic_data),
+			  NULL);
+}
diff --git a/zephyr/test/drivers/host_cmd/src/get_pd_port_caps.c b/zephyr/test/drivers/host_cmd/src/get_pd_port_caps.c
new file mode 100644
index 0000000000..907329f8a1
--- /dev/null
+++ b/zephyr/test/drivers/host_cmd/src/get_pd_port_caps.c
@@ -0,0 +1,58 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+#include "console.h"
+#include "ec_commands.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+ZTEST_USER(host_cmd_get_pd_port_caps, test_good_index)
+{
+	struct ec_params_get_pd_port_caps params = { .port = 0 };
+	struct ec_response_get_pd_port_caps response;
+	struct host_cmd_handler_args args = BUILD_HOST_COMMAND(
+		EC_CMD_GET_PD_PORT_CAPS, 0, response, params);
+
+	zassert_ok(host_command_process(&args),
+		   "Failed to process get_pd_port_caps for port %d",
+		   params.port);
+
+	/* Verify standard Chromebook responses for these fields */
+	zassert_equal(response.pd_power_role_cap, EC_PD_POWER_ROLE_DUAL,
+		      "Bad dual role");
+	zassert_equal(response.pd_try_power_role_cap,
+		      EC_PD_TRY_POWER_ROLE_SOURCE, "Bad try role");
+	zassert_equal(response.pd_data_role_cap, EC_PD_DATA_ROLE_DUAL,
+		      "Bad data role");
+	zassert_equal(response.pd_port_location, EC_PD_PORT_LOCATION_UNKNOWN,
+		      "Unexpected port location");
+}
+
+ZTEST_USER(host_cmd_get_pd_port_caps, test_bad_index)
+{
+	struct ec_params_get_pd_port_caps params = { .port = 32 };
+	struct ec_response_get_pd_port_caps response;
+	struct host_cmd_handler_args args = BUILD_HOST_COMMAND(
+		EC_CMD_GET_PD_PORT_CAPS, 0, response, params);
+
+	zassert_equal(host_command_process(&args), EC_RES_INVALID_PARAM,
+		      "Failed to fail get_pd_port_caps for port %d",
+		      params.port);
+}
+
+static void host_cmd_get_pd_port_caps_begin(void *data)
+{
+	ARG_UNUSED(data);
+
+	/* Assume we have at least one USB-C port */
+	zassume_true(board_get_usb_pd_port_count() > 0,
+		     "Insufficient TCPCs found");
+}
+
+ZTEST_SUITE(host_cmd_get_pd_port_caps, drivers_predicate_post_main, NULL,
+	    host_cmd_get_pd_port_caps_begin, NULL, NULL);
diff --git a/zephyr/test/drivers/host_cmd/src/host_event_commands.c b/zephyr/test/drivers/host_cmd/src/host_event_commands.c
new file mode 100644
index 0000000000..c2f7e72045
--- /dev/null
+++ b/zephyr/test/drivers/host_cmd/src/host_event_commands.c
@@ -0,0 +1,238 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/ztest.h>
+#include "include/lpc.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+struct host_cmd_host_event_commands_fixture {
+	struct host_events_ctx ctx;
+};
+
+static void *host_cmd_host_event_commands_setup(void)
+{
+	static struct host_cmd_host_event_commands_fixture fixture = { 0 };
+
+	return &fixture;
+}
+
+static void host_cmd_host_event_commands_before(void *fixture)
+{
+	struct host_cmd_host_event_commands_fixture *f = fixture;
+
+	host_events_save(&f->ctx);
+}
+
+static void host_cmd_host_event_commands_after(void *fixture)
+{
+	struct host_cmd_host_event_commands_fixture *f = fixture;
+
+	host_events_restore(&f->ctx);
+}
+
+ZTEST_SUITE(host_cmd_host_event_commands, drivers_predicate_post_main,
+	    host_cmd_host_event_commands_setup,
+	    host_cmd_host_event_commands_before,
+	    host_cmd_host_event_commands_after, NULL);
+
+/**
+ * @brief TestPurpose: Verify EC_CMD_HOST_EVENT invalid host command.
+ */
+ZTEST_USER(host_cmd_host_event_commands, test_host_event_invalid_cmd)
+{
+	enum ec_status ret_val;
+	struct ec_response_host_event result = { 0 };
+
+	ret_val = host_cmd_host_event(0xFF, 0, &result);
+
+	zassert_equal(ret_val, EC_RES_INVALID_PARAM, "Expected=%d, returned=%d",
+		      EC_RES_INVALID_PARAM, ret_val);
+}
+
+/**
+ * @brief TestPurpose: Verify EC_CMD_HOST_EVENT get host command.
+ */
+ZTEST_USER(host_cmd_host_event_commands, test_host_event_get_cmd)
+{
+	enum ec_status ret_val;
+	struct ec_response_host_event result = { 0 };
+	struct {
+		uint8_t mask;
+		enum ec_status result;
+	} event_get[] = {
+		{ EC_HOST_EVENT_MAIN, EC_RES_ACCESS_DENIED },
+		{ EC_HOST_EVENT_B, EC_RES_SUCCESS },
+#ifdef CONFIG_HOSTCMD_X86
+		{ EC_HOST_EVENT_SCI_MASK, EC_RES_SUCCESS },
+		{ EC_HOST_EVENT_SMI_MASK, EC_RES_SUCCESS },
+		{ EC_HOST_EVENT_ALWAYS_REPORT_MASK, EC_RES_SUCCESS },
+		{ EC_HOST_EVENT_ACTIVE_WAKE_MASK, EC_RES_SUCCESS },
+#ifdef CONFIG_POWER_S0IX
+		{ EC_HOST_EVENT_LAZY_WAKE_MASK_S0IX, EC_RES_SUCCESS },
+#endif /* CONFIG_POWER_S0IX */
+		{ EC_HOST_EVENT_LAZY_WAKE_MASK_S3, EC_RES_SUCCESS },
+		{ EC_HOST_EVENT_LAZY_WAKE_MASK_S5, EC_RES_SUCCESS },
+#endif /* CONFIG_HOSTCMD_X86 */
+		{ 0xFF, EC_RES_INVALID_PARAM },
+	};
+
+	for (int i = 0; i < ARRAY_SIZE(event_get); i++) {
+		ret_val = host_cmd_host_event(EC_HOST_EVENT_GET,
+					      event_get[i].mask, &result);
+		zassert_equal(ret_val, event_get[i].result,
+			      "[%d] Expected=%d, returned=%d", i,
+			      event_get[i].result, ret_val);
+	}
+}
+
+/**
+ * @brief TestPurpose: Verify EC_CMD_HOST_EVENT set host command.
+ */
+ZTEST_USER(host_cmd_host_event_commands, test_host_event_set_cmd)
+{
+	enum ec_status ret_val;
+	struct ec_response_host_event result = { 0 };
+	struct {
+		uint8_t mask;
+		enum ec_status result;
+	} event_set[] = {
+		{ EC_HOST_EVENT_MAIN, EC_RES_ACCESS_DENIED },
+		{ EC_HOST_EVENT_B, EC_RES_ACCESS_DENIED },
+#ifdef CONFIG_HOSTCMD_X86
+		{ EC_HOST_EVENT_SCI_MASK, EC_RES_SUCCESS },
+		{ EC_HOST_EVENT_SMI_MASK, EC_RES_SUCCESS },
+		{ EC_HOST_EVENT_ALWAYS_REPORT_MASK, EC_RES_SUCCESS },
+		{ EC_HOST_EVENT_ACTIVE_WAKE_MASK, EC_RES_SUCCESS },
+#ifdef CONFIG_POWER_S0IX
+		{ EC_HOST_EVENT_LAZY_WAKE_MASK_S0IX, EC_RES_SUCCESS },
+#endif /* CONFIG_POWER_S0IX */
+		{ EC_HOST_EVENT_LAZY_WAKE_MASK_S3, EC_RES_SUCCESS },
+		{ EC_HOST_EVENT_LAZY_WAKE_MASK_S5, EC_RES_SUCCESS },
+#endif /* CONFIG_HOSTCMD_X86 */
+		{ 0xFF, EC_RES_INVALID_PARAM },
+	};
+
+	for (int i = 0; i < ARRAY_SIZE(event_set); i++) {
+		ret_val = host_cmd_host_event(EC_HOST_EVENT_SET,
+					      event_set[i].mask, &result);
+		zassert_equal(ret_val, event_set[i].result,
+			      "[%d] Expected=%d, returned=%d", i,
+			      event_set[i].result, ret_val);
+	}
+}
+
+/**
+ * @brief TestPurpose: Verify EC_CMD_HOST_EVENT clear host command.
+ */
+ZTEST_USER(host_cmd_host_event_commands, test_host_event_clear_cmd)
+{
+	enum ec_status ret_val;
+	struct ec_response_host_event result = { 0 };
+	struct {
+		uint8_t mask;
+		enum ec_status result;
+	} event_set[] = {
+		{ EC_HOST_EVENT_MAIN, EC_RES_SUCCESS },
+		{ EC_HOST_EVENT_B, EC_RES_SUCCESS },
+#ifdef CONFIG_HOSTCMD_X86
+		{ EC_HOST_EVENT_SCI_MASK, EC_RES_ACCESS_DENIED },
+		{ EC_HOST_EVENT_SMI_MASK, EC_RES_ACCESS_DENIED },
+		{ EC_HOST_EVENT_ALWAYS_REPORT_MASK, EC_RES_ACCESS_DENIED },
+		{ EC_HOST_EVENT_ACTIVE_WAKE_MASK, EC_RES_ACCESS_DENIED },
+#ifdef CONFIG_POWER_S0IX
+		{ EC_HOST_EVENT_LAZY_WAKE_MASK_S0IX, EC_RES_ACCESS_DENIED },
+#endif /* CONFIG_POWER_S0IX */
+		{ EC_HOST_EVENT_LAZY_WAKE_MASK_S3, EC_RES_ACCESS_DENIED },
+		{ EC_HOST_EVENT_LAZY_WAKE_MASK_S5, EC_RES_ACCESS_DENIED },
+#endif /* CONFIG_HOSTCMD_X86 */
+		{ 0xFF, EC_RES_INVALID_PARAM },
+	};
+
+	for (int i = 0; i < ARRAY_SIZE(event_set); i++) {
+		ret_val = host_cmd_host_event(EC_HOST_EVENT_CLEAR,
+					      event_set[i].mask, &result);
+		zassert_equal(ret_val, event_set[i].result,
+			      "Expected [%d] result=%d, returned=%d", i,
+			      event_set[i].result, ret_val);
+	}
+}
+
+enum ec_status host_event_mask_cmd_helper(uint32_t command, uint32_t mask,
+					  struct ec_response_host_event_mask *r)
+{
+	enum ec_status ret_val;
+
+	struct ec_params_host_event_mask params = {
+		.mask = mask,
+	};
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(command, 0, *r, params);
+
+	ret_val = host_command_process(&args);
+
+	return ret_val;
+}
+
+/**
+ * @brief TestPurpose: Verify EC_CMD_HOST_EVENT_CLEAR clear host command.
+ */
+ZTEST_USER(host_cmd_host_event_commands, test_host_event_clear__cmd)
+{
+	enum ec_status ret_val;
+	host_event_t events;
+	host_event_t mask = EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY);
+	host_event_t lpc_event_mask;
+	struct ec_response_host_event_mask response = { 0 };
+
+	lpc_event_mask = lpc_get_host_event_mask(LPC_HOST_EVENT_SMI);
+	lpc_set_host_event_mask(LPC_HOST_EVENT_SMI, lpc_event_mask | mask);
+
+	host_set_single_event(EC_HOST_EVENT_KEYBOARD_RECOVERY);
+	events = host_get_events();
+
+	zassert_true(events & mask, "events=0x%X", events);
+
+	ret_val = host_event_mask_cmd_helper(EC_CMD_HOST_EVENT_CLEAR, mask,
+					     &response);
+
+	zassert_equal(ret_val, EC_RES_SUCCESS, "Expected %d, returned %d",
+		      EC_RES_SUCCESS, ret_val);
+
+	events = host_get_events();
+	zassert_false(events & mask, "events=0x%X", events);
+}
+
+/**
+ * @brief TestPurpose: Verify EC_CMD_HOST_EVENT_CLEAR_B clear host command.
+ */
+ZTEST_USER(host_cmd_host_event_commands, test_host_event_clear_b_cmd)
+{
+	enum ec_status ret_val;
+	host_event_t events_b;
+	host_event_t mask = EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY);
+	host_event_t lpc_event_mask;
+	struct ec_response_host_event_mask response = { 0 };
+	struct ec_response_host_event result = { 0 };
+
+	lpc_event_mask = lpc_get_host_event_mask(LPC_HOST_EVENT_SMI);
+	lpc_set_host_event_mask(LPC_HOST_EVENT_SMI, lpc_event_mask | mask);
+
+	host_set_single_event(EC_HOST_EVENT_KEYBOARD_RECOVERY);
+
+	host_cmd_host_event(EC_HOST_EVENT_GET, EC_HOST_EVENT_B, &result);
+	events_b = result.value;
+	zassert_true(events_b & mask, "events_b=0x%X", events_b);
+
+	ret_val = host_event_mask_cmd_helper(EC_CMD_HOST_EVENT_CLEAR_B, mask,
+					     &response);
+
+	zassert_equal(ret_val, EC_RES_SUCCESS, "Expected %d, returned %d",
+		      EC_RES_SUCCESS, ret_val);
+
+	host_cmd_host_event(EC_HOST_EVENT_GET, EC_HOST_EVENT_B, &result);
+	events_b = result.value;
+	zassert_false(events_b & mask, "events_b=0x%X", events_b);
+}
diff --git a/zephyr/test/drivers/host_cmd/src/host_event_commands_deprecated.c b/zephyr/test/drivers/host_cmd/src/host_event_commands_deprecated.c
new file mode 100644
index 0000000000..6d0a386d6e
--- /dev/null
+++ b/zephyr/test/drivers/host_cmd/src/host_event_commands_deprecated.c
@@ -0,0 +1,256 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Tests for deprecated EC_CMD_HOST_EVENT_* commands */
+
+#include <zephyr/ztest.h>
+#include "include/lpc.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#define HOST_EVENT_TEST_MASK_VAL EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)
+
+static void
+host_event_get_wake_mask_helper(struct ec_response_host_event_mask *r)
+{
+	enum ec_status ret_val;
+	struct host_cmd_handler_args args = BUILD_HOST_COMMAND_RESPONSE(
+		EC_CMD_HOST_EVENT_GET_WAKE_MASK, 0, *r);
+
+	ret_val = host_command_process(&args);
+
+	/* EC_CMD_HOST_EVENT_GET_WAKE_MASK always returns success */
+	zassert_equal(ret_val, EC_RES_SUCCESS, "Expected %d, returned %d",
+		      EC_RES_SUCCESS, ret_val);
+}
+
+static void host_event_set_wake_mask_helper(uint32_t mask)
+{
+	enum ec_status ret_val;
+	struct ec_params_host_event_mask params = { .mask = mask };
+	struct host_cmd_handler_args args = BUILD_HOST_COMMAND_PARAMS(
+		EC_CMD_HOST_EVENT_SET_WAKE_MASK, 0, params);
+
+	ret_val = host_command_process(&args);
+
+	/* EC_CMD_HOST_EVENT_SET_WAKE_MASK always returns success */
+	zassert_equal(ret_val, EC_RES_SUCCESS, "Expected %d, returned %d",
+		      EC_RES_SUCCESS, ret_val);
+}
+
+/**
+ * @brief TestPurpose: Verify EC_CMD_HOST_EVENT_GET_WAKE_MASK host command.
+ */
+ZTEST_USER(host_cmd_host_event_commands, test_host_event_get_wake_mask)
+{
+#ifdef CONFIG_HOSTCMD_X86
+	struct ec_response_host_event_mask result = { 0 };
+
+	host_event_get_wake_mask_helper(&result);
+#else
+	ztest_test_skip();
+#endif
+}
+
+/**
+ * @brief TestPurpose: Verify EC_CMD_HOST_EVENT_SET_WAKE_MASK host command.
+ */
+ZTEST_USER(host_cmd_host_event_commands, test_host_event_set_wake_mask)
+{
+#ifdef CONFIG_HOSTCMD_X86
+	struct ec_response_host_event_mask result = { 0 };
+
+	/* Read the current mask */
+	host_event_get_wake_mask_helper(&result);
+
+	/* Default mask is expected to be clear */
+	zassert_false(result.mask, "Default host event wake mask is not clear");
+
+	host_event_set_wake_mask_helper(HOST_EVENT_TEST_MASK_VAL);
+
+	/* Verify the mask changed */
+	host_event_get_wake_mask_helper(&result);
+
+	zassert_equal(result.mask, HOST_EVENT_TEST_MASK_VAL,
+		      "Expected wake mask 0x%08x, returned mask 0x%08x",
+		      HOST_EVENT_TEST_MASK_VAL, result.mask);
+
+	/* Clean up the mask */
+	host_event_set_wake_mask_helper(0);
+#else
+	ztest_test_skip();
+#endif
+}
+
+static void
+host_event_get_smi_mask_helper(struct ec_response_host_event_mask *r)
+{
+	enum ec_status ret_val;
+	struct host_cmd_handler_args args = BUILD_HOST_COMMAND_RESPONSE(
+		EC_CMD_HOST_EVENT_GET_SMI_MASK, 0, *r);
+
+	ret_val = host_command_process(&args);
+
+	/* EC_CMD_HOST_EVENT_GET_SMI_MASK always returns success */
+	zassert_equal(ret_val, EC_RES_SUCCESS, "Expected %d, returned %d",
+		      EC_RES_SUCCESS, ret_val);
+}
+
+static void host_event_set_smi_mask_helper(uint32_t mask)
+{
+	enum ec_status ret_val;
+	struct ec_params_host_event_mask params = { .mask = mask };
+	struct host_cmd_handler_args args = BUILD_HOST_COMMAND_PARAMS(
+		EC_CMD_HOST_EVENT_SET_SMI_MASK, 0, params);
+
+	ret_val = host_command_process(&args);
+
+	/* EC_CMD_HOST_EVENT_SET_SMI_MASK always returns success */
+	zassert_equal(ret_val, EC_RES_SUCCESS, "Expected %d, returned %d",
+		      EC_RES_SUCCESS, ret_val);
+}
+
+/**
+ * @brief TestPurpose: Verify EC_CMD_HOST_EVENT_GET_SMI_MASK host command.
+ */
+ZTEST_USER(host_cmd_host_event_commands, test_host_event_get_smi_mask)
+{
+#ifdef CONFIG_HOSTCMD_X86
+	struct ec_response_host_event_mask result = { 0 };
+
+	host_event_get_smi_mask_helper(&result);
+#else
+	ztest_test_skip();
+#endif
+}
+
+/**
+ * @brief TestPurpose: Verify EC_CMD_HOST_EVENT_SET_SMI_MASK host command.
+ */
+ZTEST_USER(host_cmd_host_event_commands, test_host_event_set_smi_mask)
+{
+#ifdef CONFIG_HOSTCMD_X86
+	struct ec_response_host_event_mask result = { 0 };
+
+	/* Read the current mask */
+	host_event_get_smi_mask_helper(&result);
+
+	/* Default mask is expected to be clear */
+	zassert_false(result.mask, "Default host event SMI mask is not clear");
+
+	host_event_set_smi_mask_helper(HOST_EVENT_TEST_MASK_VAL);
+
+	/* Verify the mask changed */
+	host_event_get_smi_mask_helper(&result);
+
+	zassert_equal(result.mask, HOST_EVENT_TEST_MASK_VAL,
+		      "Expected SMI mask 0x%08x, returned mask 0x%08x",
+		      HOST_EVENT_TEST_MASK_VAL, result.mask);
+
+	/* Clean up the mask */
+	host_event_set_smi_mask_helper(0);
+#else
+	ztest_test_skip();
+#endif
+}
+
+static void host_event_get_b_helper(struct ec_response_host_event_mask *r)
+{
+	enum ec_status ret_val;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_RESPONSE(EC_CMD_HOST_EVENT_GET_B, 0, *r);
+
+	ret_val = host_command_process(&args);
+
+	/* EC_CMD_HOST_EVENT_GET_B always returns success */
+	zassert_equal(ret_val, EC_RES_SUCCESS, "Expected %d, returned %d",
+		      EC_RES_SUCCESS, ret_val);
+}
+
+/**
+ * @brief TestPurpose: Verify EC_CMD_HOST_EVENT_GET_B host command.
+ */
+ZTEST_USER(host_cmd_host_event_commands, test_host_event_get_b)
+{
+#ifdef CONFIG_HOSTCMD_X86
+	struct ec_response_host_event_mask result = { 0 };
+
+	host_event_get_b_helper(&result);
+#else
+	ztest_test_skip();
+#endif
+}
+
+static void
+host_event_get_sci_mask_helper(struct ec_response_host_event_mask *r)
+{
+	enum ec_status ret_val;
+	struct host_cmd_handler_args args = BUILD_HOST_COMMAND_RESPONSE(
+		EC_CMD_HOST_EVENT_GET_SCI_MASK, 0, *r);
+
+	ret_val = host_command_process(&args);
+
+	/* EC_CMD_HOST_EVENT_GET_SCI_MASK always returns success */
+	zassert_equal(ret_val, EC_RES_SUCCESS, "Expected %d, returned %d",
+		      EC_RES_SUCCESS, ret_val);
+}
+
+static void host_event_set_sci_mask_helper(uint32_t mask)
+{
+	enum ec_status ret_val;
+	struct ec_params_host_event_mask params = { .mask = mask };
+	struct host_cmd_handler_args args = BUILD_HOST_COMMAND_PARAMS(
+		EC_CMD_HOST_EVENT_SET_SCI_MASK, 0, params);
+
+	ret_val = host_command_process(&args);
+
+	/* EC_CMD_HOST_EVENT_SET_SCI_MASK always returns success */
+	zassert_equal(ret_val, EC_RES_SUCCESS, "Expected %d, returned %d",
+		      EC_RES_SUCCESS, ret_val);
+}
+
+/**
+ * @brief TestPurpose: Verify EC_CMD_HOST_EVENT_GET_SCI_MASK host command.
+ */
+ZTEST_USER(host_cmd_host_event_commands, test_host_event_get_sci_mask)
+{
+#ifdef CONFIG_HOSTCMD_X86
+	struct ec_response_host_event_mask result = { 0 };
+
+	host_event_get_sci_mask_helper(&result);
+#else
+	ztest_test_skip();
+#endif
+}
+
+/**
+ * @brief TestPurpose: Verify EC_CMD_HOST_EVENT_SET_SCI_MASK host command.
+ */
+ZTEST_USER(host_cmd_host_event_commands, test_host_event_set_sci_mask)
+{
+#ifdef CONFIG_HOSTCMD_X86
+	struct ec_response_host_event_mask result = { 0 };
+
+	/* Read the current mask */
+	host_event_get_sci_mask_helper(&result);
+
+	/* Default mask is expected to be clear */
+	zassert_false(result.mask, "Default host event SCI mask is not clear");
+
+	host_event_set_sci_mask_helper(HOST_EVENT_TEST_MASK_VAL);
+
+	/* Verify the mask changed */
+	host_event_get_sci_mask_helper(&result);
+
+	zassert_equal(result.mask, HOST_EVENT_TEST_MASK_VAL,
+		      "Expected SCI mask 0x%08x, returned mask 0x%08x",
+		      HOST_EVENT_TEST_MASK_VAL, result.mask);
+
+	/* Clean up the mask */
+	host_event_set_sci_mask_helper(0);
+#else
+	ztest_test_skip();
+#endif
+}
diff --git a/zephyr/test/drivers/host_cmd/src/keyboard_mkbp.c b/zephyr/test/drivers/host_cmd/src/keyboard_mkbp.c
new file mode 100644
index 0000000000..4c74a48ab4
--- /dev/null
+++ b/zephyr/test/drivers/host_cmd/src/keyboard_mkbp.c
@@ -0,0 +1,81 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/ztest.h>
+#include "include/keyboard_mkbp.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+struct keyboard_mkbp_commands_fixture {
+	struct ec_mkbp_config config;
+};
+
+static void *keyboard_mkbp_setup(void)
+{
+	static struct keyboard_mkbp_commands_fixture fixture = { 0 };
+
+	return &fixture;
+}
+
+static void keyboard_mkbp_before(void *fixture)
+{
+	struct keyboard_mkbp_commands_fixture *f = fixture;
+
+	get_keyscan_config(&f->config);
+}
+
+static void keyboard_mkbp_after(void *fixture)
+{
+	struct keyboard_mkbp_commands_fixture *f = fixture;
+	struct ec_params_mkbp_set_config req = { 0 };
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_PARAMS(EC_CMD_MKBP_SET_CONFIG, 0, req);
+
+	req.config = f->config;
+	host_command_process(&args);
+}
+
+ZTEST_SUITE(keyboard_mkbp_commands, drivers_predicate_post_main,
+	    keyboard_mkbp_setup, keyboard_mkbp_before, keyboard_mkbp_after,
+	    NULL);
+
+/**
+ * @brief TestPurpose: Verify EC_CMD_MKBP_GET_CONFIG host command.
+ */
+ZTEST_USER(keyboard_mkbp_commands, test_mkbp_get_config_cmd)
+{
+	enum ec_status ret_val;
+	struct ec_response_mkbp_get_config resp;
+
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_RESPONSE(EC_CMD_MKBP_GET_CONFIG, 0, resp);
+
+	ret_val = host_command_process(&args);
+
+	zassert_ok(ret_val, "Expected=%d, returned=%d", EC_SUCCESS, ret_val);
+}
+
+/**
+ * @brief TestPurpose: Verify EC_CMD_MKBP_SET_CONFIG host command.
+ */
+ZTEST_USER(keyboard_mkbp_commands, test_mkbp_set_config_cmd)
+{
+	enum ec_status ret_val;
+	struct ec_params_mkbp_set_config req = { 0 };
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_PARAMS(EC_CMD_MKBP_SET_CONFIG, 0, req);
+
+	get_keyscan_config(&req.config);
+
+	req.config.valid_mask =
+		EC_MKBP_VALID_SCAN_PERIOD | EC_MKBP_VALID_POLL_TIMEOUT |
+		EC_MKBP_VALID_MIN_POST_SCAN_DELAY |
+		EC_MKBP_VALID_OUTPUT_SETTLE | EC_MKBP_VALID_DEBOUNCE_DOWN |
+		EC_MKBP_VALID_DEBOUNCE_UP | EC_MKBP_VALID_FIFO_MAX_DEPTH;
+
+	ret_val = host_command_process(&args);
+
+	zassert_ok(ret_val, "Expected=%d, returned=%d", EC_SUCCESS, ret_val);
+}
diff --git a/zephyr/test/drivers/src/host_cmd/motion_sense.c b/zephyr/test/drivers/host_cmd/src/motion_sense.c
index 07952ed285..c75f327fed 100644
--- a/zephyr/test/drivers/src/host_cmd/motion_sense.c
+++ b/zephyr/test/drivers/host_cmd/src/motion_sense.c
@@ -1,12 +1,14 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <fff.h>
-#include <ztest.h>
+#include <zephyr/fff.h>
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
 
 #include "atomic.h"
+#include "console.h"
 #include "driver/accel_bma2x2.h"
 #include "motion_sense.h"
 #include "motion_sense_fifo.h"
@@ -68,6 +70,8 @@ static void host_cmd_motion_sense_before(void *fixture)
 	RESET_FAKE(mock_perform_calib);
 	FFF_RESET_HISTORY();
 
+	zassume_ok(shell_execute_cmd(get_ec_shell(), "accelinit 0"), NULL);
+
 	atomic_clear(&motion_sensors[0].flush_pending);
 	motion_sensors[0].config[SENSOR_CONFIG_AP].odr = 0;
 	motion_sensors[0].config[SENSOR_CONFIG_AP].ec_rate = 1000 * MSEC;
@@ -81,6 +85,8 @@ static void host_cmd_motion_sense_after(void *fixture)
 	motion_sensors[0].drv = this->sensor_0_drv;
 	host_cmd_motion_sense_int_enable(0, &response);
 	motion_sensors[0].flags &= ~MOTIONSENSE_FLAG_IN_SPOOF_MODE;
+	motion_sensors[0].config[SENSOR_CONFIG_AP].odr = 0;
+	motion_sensors[0].config[SENSOR_CONFIG_AP].ec_rate = 1000 * MSEC;
 }
 
 ZTEST_SUITE(host_cmd_motion_sense, drivers_predicate_post_main,
@@ -100,10 +106,15 @@ ZTEST_USER(host_cmd_motion_sense, test_dump)
 		motion_sensors[i].xyz[1] = i + 1;
 		motion_sensors[i].xyz[2] = i + 2;
 	}
+
+	/* Make sure that the accelerometer status presence bit is off */
+	*host_get_memmap(EC_MEMMAP_ACC_STATUS) &=
+		~(EC_MEMMAP_ACC_STATUS_PRESENCE_BIT);
+
+	/* Dump all the sensors info */
 	host_cmd_motion_sense_dump(ALL_MOTION_SENSORS, result);
 
-	zassert_equal(result->dump.module_flags, MOTIONSENSE_MODULE_FLAG_ACTIVE,
-		      NULL);
+	zassert_equal(result->dump.module_flags, 0, NULL);
 	zassert_equal(result->dump.sensor_count, ALL_MOTION_SENSORS, NULL);
 
 	/*
@@ -119,6 +130,16 @@ ZTEST_USER(host_cmd_motion_sense, test_dump)
 		zassert_equal(result->dump.sensor[i].data[1], i + 1, NULL);
 		zassert_equal(result->dump.sensor[i].data[2], i + 2, NULL);
 	}
+
+	/* Make sure that the accelerometer status presence bit is on */
+	*host_get_memmap(EC_MEMMAP_ACC_STATUS) |=
+		EC_MEMMAP_ACC_STATUS_PRESENCE_BIT;
+
+	/* Dump all the sensors info */
+	host_cmd_motion_sense_dump(ALL_MOTION_SENSORS, result);
+
+	zassert_equal(result->dump.module_flags, MOTIONSENSE_MODULE_FLAG_ACTIVE,
+		      NULL);
 }
 
 ZTEST_USER(host_cmd_motion_sense, test_dump__large_max_sensor_count)
@@ -232,6 +253,10 @@ ZTEST_USER(host_cmd_motion_sense, test_get_ec_rate)
 {
 	struct ec_response_motion_sense response;
 
+	/* Set the power level to S3, the default config from device-tree is for
+	 * 100ms
+	 */
+	test_set_chipset_to_power_level(POWER_S3);
 	zassert_ok(host_cmd_motion_sense_ec_rate(
 			   /*sensor_num=*/0,
 			   /*data_rate_ms=*/EC_MOTION_SENSE_NO_VALUE,
@@ -244,6 +269,10 @@ ZTEST_USER(host_cmd_motion_sense, test_set_ec_rate)
 {
 	struct ec_response_motion_sense response;
 
+	/* Set the power level to S3, the default config from device-tree is for
+	 * 100ms
+	 */
+	test_set_chipset_to_power_level(POWER_S3);
 	zassert_ok(host_cmd_motion_sense_ec_rate(
 			   /*sensor_num=*/0, /*data_rate_ms=*/2000, &response),
 		   NULL);
@@ -351,7 +380,7 @@ ZTEST_USER_F(host_cmd_motion_sense, test_set_range_error)
 	struct ec_response_motion_sense response;
 
 	mock_set_range_fake.return_val = 1;
-	motion_sensors[0].drv = &this->mock_drv;
+	motion_sensors[0].drv = &fixture->mock_drv;
 
 	zassert_equal(EC_RES_INVALID_PARAM,
 		      host_cmd_motion_sense_range(/*sensor_num=*/0, /*range=*/4,
@@ -366,7 +395,7 @@ ZTEST_USER_F(host_cmd_motion_sense, test_set_range)
 	struct ec_response_motion_sense response;
 
 	mock_set_range_fake.return_val = 0;
-	motion_sensors[0].drv = &this->mock_drv;
+	motion_sensors[0].drv = &fixture->mock_drv;
 
 	zassert_ok(host_cmd_motion_sense_range(/*sensor_num=*/0, /*range=*/4,
 					       /*round_up=*/false, &response),
@@ -423,7 +452,7 @@ ZTEST_USER_F(host_cmd_motion_sense, test_offset_fail_to_set)
 {
 	struct ec_response_motion_sense response;
 
-	motion_sensors[0].drv = &this->mock_drv;
+	motion_sensors[0].drv = &fixture->mock_drv;
 	mock_set_offset_fake.return_val = EC_RES_ERROR;
 
 	zassert_equal(EC_RES_ERROR,
@@ -440,7 +469,7 @@ ZTEST_USER_F(host_cmd_motion_sense, test_offset_fail_to_get)
 {
 	struct ec_response_motion_sense response;
 
-	motion_sensors[0].drv = &this->mock_drv;
+	motion_sensors[0].drv = &fixture->mock_drv;
 	mock_set_offset_fake.return_val = EC_RES_SUCCESS;
 	mock_get_offset_fake.return_val = EC_RES_ERROR;
 
@@ -461,7 +490,7 @@ ZTEST_USER_F(host_cmd_motion_sense, test_get_offset)
 {
 	struct ec_response_motion_sense response;
 
-	motion_sensors[0].drv = &this->mock_drv;
+	motion_sensors[0].drv = &fixture->mock_drv;
 	mock_get_offset_fake.return_val = EC_RES_SUCCESS;
 	mock_set_offset_fake.return_val = EC_RES_SUCCESS;
 
@@ -529,7 +558,7 @@ ZTEST_USER_F(host_cmd_motion_sense, test_get_scale_fail)
 {
 	struct ec_response_motion_sense response;
 
-	motion_sensors[0].drv = &this->mock_drv;
+	motion_sensors[0].drv = &fixture->mock_drv;
 	mock_get_scale_fake.return_val = 1;
 
 	zassert_equal(1,
@@ -546,7 +575,7 @@ ZTEST_USER_F(host_cmd_motion_sense, test_set_scale_fail)
 {
 	struct ec_response_motion_sense response;
 
-	motion_sensors[0].drv = &this->mock_drv;
+	motion_sensors[0].drv = &fixture->mock_drv;
 	mock_set_scale_fake.return_val = 1;
 
 	zassert_equal(1,
@@ -563,7 +592,7 @@ ZTEST_USER_F(host_cmd_motion_sense, test_set_get_scale)
 {
 	struct ec_response_motion_sense response;
 
-	motion_sensors[0].drv = &this->mock_drv;
+	motion_sensors[0].drv = &fixture->mock_drv;
 	mock_set_scale_fake.return_val = 0;
 	mock_get_scale_fake.return_val = 0;
 
@@ -604,7 +633,7 @@ ZTEST_USER_F(host_cmd_motion_sense, test_calib_fail)
 {
 	struct ec_response_motion_sense response;
 
-	motion_sensors[0].drv = &this->mock_drv;
+	motion_sensors[0].drv = &fixture->mock_drv;
 	mock_perform_calib_fake.return_val = 1;
 
 	zassert_equal(1,
@@ -619,7 +648,7 @@ ZTEST_USER_F(host_cmd_motion_sense, test_calib_success__fail_get_offset)
 {
 	struct ec_response_motion_sense response;
 
-	motion_sensors[0].drv = &this->mock_drv;
+	motion_sensors[0].drv = &fixture->mock_drv;
 	mock_perform_calib_fake.return_val = 0;
 	mock_get_offset_fake.return_val = 1;
 
@@ -636,7 +665,7 @@ ZTEST_USER_F(host_cmd_motion_sense, test_calib)
 {
 	struct ec_response_motion_sense response;
 
-	motion_sensors[0].drv = &this->mock_drv;
+	motion_sensors[0].drv = &fixture->mock_drv;
 	mock_perform_calib_fake.return_val = 0;
 	mock_get_offset_fake.return_val = 0;
 
@@ -663,12 +692,9 @@ ZTEST(host_cmd_motion_sense, test_fifo_flush)
 	struct ec_response_motion_sense *response =
 		(struct ec_response_motion_sense *)response_buffer;
 
-	motion_sensors[0].lost = 5;
 	zassert_ok(host_cmd_motion_sense_fifo_flush(/*sensor_num=*/0, response),
 		   NULL);
 	zassert_equal(1, motion_sensors[0].flush_pending, NULL);
-	zassert_equal(5, response->fifo_info.lost[0], NULL);
-	zassert_equal(0, motion_sensors[0].lost, NULL);
 }
 
 ZTEST(host_cmd_motion_sense, test_fifo_info)
@@ -677,10 +703,7 @@ ZTEST(host_cmd_motion_sense, test_fifo_info)
 	struct ec_response_motion_sense *response =
 		(struct ec_response_motion_sense *)response_buffer;
 
-	motion_sensors[0].lost = 4;
 	zassert_ok(host_cmd_motion_sense_fifo_info(response), NULL);
-	zassert_equal(4, response->fifo_info.lost[0], NULL);
-	zassert_equal(0, motion_sensors[0].lost, NULL);
 }
 
 ZTEST(host_cmd_motion_sense, test_fifo_read)
diff --git a/zephyr/test/drivers/host_cmd/src/pd_chip_info.c b/zephyr/test/drivers/host_cmd/src/pd_chip_info.c
new file mode 100644
index 0000000000..95e2339899
--- /dev/null
+++ b/zephyr/test/drivers/host_cmd/src/pd_chip_info.c
@@ -0,0 +1,65 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+#include "console.h"
+#include "ec_commands.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#define TEST_PORT USBC_PORT_C0
+#define BAD_PORT 65
+
+static enum ec_status run_pd_chip_info(int port,
+				       struct ec_response_pd_chip_info_v1 *resp)
+{
+	struct ec_params_pd_chip_info params = { .port = port, .live = true };
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_PD_CHIP_INFO, 1, resp, params);
+
+	return host_command_process(&args);
+}
+
+ZTEST_USER(host_cmd_pd_chip_info, test_good_index)
+{
+	struct ec_response_pd_chip_info_v1 response;
+
+	zassert_ok(run_pd_chip_info(TEST_PORT, &response),
+		   "Failed to process pd_get_chip_info for port %d", TEST_PORT);
+	/*
+	 * Note: verification of the specific fields depends on the chips used
+	 * and therefore would belong in a driver-level test
+	 */
+}
+
+ZTEST_USER(host_cmd_pd_chip_info, test_bad_index)
+{
+	struct ec_response_pd_chip_info_v1 response;
+
+	zassume_true(board_get_usb_pd_port_count() < BAD_PORT,
+		     "Intended bad port exists");
+	zassert_equal(run_pd_chip_info(BAD_PORT, &response),
+		      EC_RES_INVALID_PARAM,
+		      "Failed to fail pd_chip_info for port %d", BAD_PORT);
+}
+
+static void host_cmd_pd_chip_info_begin(void *data)
+{
+	ARG_UNUSED(data);
+
+	/* Assume we have at least one USB-C port */
+	zassume_true(board_get_usb_pd_port_count() > 0,
+		     "Insufficient TCPCs found");
+
+	/* Set the system into S0, since the AP would drive these commands */
+	test_set_chipset_to_s0();
+	k_sleep(K_SECONDS(1));
+}
+
+ZTEST_SUITE(host_cmd_pd_chip_info, drivers_predicate_post_main, NULL,
+	    host_cmd_pd_chip_info_begin, NULL, NULL);
diff --git a/zephyr/test/drivers/host_cmd/src/pd_control.c b/zephyr/test/drivers/host_cmd/src/pd_control.c
new file mode 100644
index 0000000000..e8de27f6ce
--- /dev/null
+++ b/zephyr/test/drivers/host_cmd/src/pd_control.c
@@ -0,0 +1,129 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/fff.h>
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+#include "console.h"
+#include "ec_commands.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#define TEST_PORT USBC_PORT_C0
+#define BAD_PORT 82
+
+ZTEST_USER(host_cmd_pd_control, test_bad_index)
+{
+	struct ec_params_pd_control params = { .chip = BAD_PORT,
+					       .subcmd = PD_RESET };
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_PARAMS(EC_CMD_PD_CONTROL, 0, params);
+
+	zassume_true(board_get_usb_pd_port_count() < BAD_PORT,
+		     "Intended bad port exists");
+	zassert_equal(host_command_process(&args), EC_RES_INVALID_PARAM,
+		      "Failed to fail pd_control for port %d", params.chip);
+}
+
+ZTEST_USER(host_cmd_pd_control, test_unimplemented_command)
+{
+	struct ec_params_pd_control params = { .chip = TEST_PORT,
+					       .subcmd = PD_CHIP_ON };
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_PARAMS(EC_CMD_PD_CONTROL, 0, params);
+
+	zassert_equal(host_command_process(&args), EC_RES_INVALID_COMMAND,
+		      "Failed to fail pd_control for port %d", params.chip);
+}
+
+ZTEST_USER(host_cmd_pd_control, test_pd_reset_resume)
+{
+	/*
+	 * Note: this would ideally be a host command interface check, but
+	 * the only HC return which would cover this is a state string, which
+	 * could be brittle.
+	 */
+	zassume_true(pd_is_port_enabled(TEST_PORT), "Port not up at beginning");
+
+	host_cmd_pd_control(TEST_PORT, PD_RESET);
+
+	zassert_equal(1, board_reset_pd_mcu_fake.call_count,
+		      "Failed to see board reset");
+
+	/* Give some PD task processing time */
+	k_sleep(K_SECONDS(1));
+
+	zassert_false(pd_is_port_enabled(TEST_PORT), "Port failed to suspend");
+
+	host_cmd_pd_control(TEST_PORT, PD_RESUME);
+
+	/* Give some PD task processing time */
+	k_sleep(K_SECONDS(1));
+
+	zassert_true(pd_is_port_enabled(TEST_PORT), "Port failed to resume");
+
+	RESET_FAKE(board_reset_pd_mcu);
+}
+
+ZTEST_USER(host_cmd_pd_control, test_suspend_resume)
+{
+	/*
+	 * Note: this would ideally be a host command interface check, but
+	 * the only HC return which would cover this is a state string, which
+	 * could be brittle.
+	 */
+	zassume_true(pd_is_port_enabled(TEST_PORT), "Port not up at beginning");
+
+	host_cmd_pd_control(TEST_PORT, PD_SUSPEND);
+
+	/* Give some PD task processing time */
+	k_sleep(K_SECONDS(1));
+
+	zassert_false(pd_is_port_enabled(TEST_PORT), "Port failed to suspend");
+
+	host_cmd_pd_control(TEST_PORT, PD_RESUME);
+
+	/* Give some PD task processing time */
+	k_sleep(K_SECONDS(1));
+
+	zassert_true(pd_is_port_enabled(TEST_PORT), "Port failed to resume");
+}
+
+ZTEST_USER(host_cmd_pd_control, test_control_disable)
+{
+	struct ec_params_pd_control params = { .chip = TEST_PORT,
+					       .subcmd = PD_RESET };
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_PARAMS(EC_CMD_PD_CONTROL, 0, params);
+
+	host_cmd_pd_control(TEST_PORT, PD_CONTROL_DISABLE);
+
+	zassert_equal(host_command_process(&args), EC_RES_ACCESS_DENIED,
+		      "Access was not denied for port %d", params.chip);
+
+	/*
+	 * Disable lasts as long as the EC is booted.  Use a test hook to
+	 * restore our state to a normal one
+	 */
+	pd_control_port_enable(TEST_PORT);
+}
+
+static void host_cmd_pd_control_begin(void *data)
+{
+	ARG_UNUSED(data);
+
+	/* Assume we have at least one USB-C port */
+	zassume_true(board_get_usb_pd_port_count() > 0,
+		     "Insufficient TCPCs found");
+
+	/* Set the system into S0, since the AP would drive these commands */
+	test_set_chipset_to_s0();
+	k_sleep(K_SECONDS(1));
+}
+
+ZTEST_SUITE(host_cmd_pd_control, drivers_predicate_post_main, NULL,
+	    host_cmd_pd_control_begin, NULL, NULL);
diff --git a/zephyr/test/drivers/host_cmd/src/pd_log.c b/zephyr/test/drivers/host_cmd/src/pd_log.c
new file mode 100644
index 0000000000..a6022d8bb1
--- /dev/null
+++ b/zephyr/test/drivers/host_cmd/src/pd_log.c
@@ -0,0 +1,135 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+#include "event_log.h"
+#include "host_command.h"
+#include "test/drivers/test_state.h"
+#include "usb_pd.h"
+
+/**
+ * @brief This is the maximum size of a single log entry.
+ *
+ * Each entry must contain some common data + up to 16 bytes of additional type
+ * specific data.
+ */
+#define MAX_EVENT_LOG_ENTRY_SIZE (sizeof(struct event_log_entry) + 16)
+
+/**
+ * @brief The size of the PD log entry data
+ *
+ * Logs from the PD include an additional 8 bytes of data to be sent to the AP.
+ */
+#define PD_LOG_ENTRY_DATA_SIZE (8)
+
+struct pd_log_fixture {
+	union {
+		uint8_t event_log_buffer[MAX_EVENT_LOG_ENTRY_SIZE];
+		struct event_log_entry log_entry;
+	};
+};
+
+static void *pd_log_setup(void)
+{
+	static struct pd_log_fixture fixture;
+
+	return &fixture;
+}
+
+static void pd_log_before(void *f)
+{
+	struct pd_log_fixture *fixture = f;
+
+	while (log_dequeue_event(&fixture->log_entry) != 0) {
+		if (fixture->log_entry.type == EVENT_LOG_NO_ENTRY) {
+			break;
+		}
+	}
+}
+
+ZTEST_SUITE(pd_log, drivers_predicate_post_main, pd_log_setup, pd_log_before,
+	    NULL, NULL);
+
+ZTEST_USER(pd_log, test_bad_type)
+{
+	struct ec_params_pd_write_log_entry params = {
+		.type = PD_EVENT_ACC_BASE,
+	};
+	struct host_cmd_handler_args args = BUILD_HOST_COMMAND_PARAMS(
+		EC_CMD_PD_WRITE_LOG_ENTRY, UINT8_C(0), params);
+
+	zassert_equal(EC_RES_INVALID_PARAM, host_command_process(&args), NULL);
+}
+
+ZTEST_USER(pd_log, test_bad_port)
+{
+	struct ec_params_pd_write_log_entry params = {
+		.type = PD_EVENT_MCU_BASE,
+	};
+	struct host_cmd_handler_args args = BUILD_HOST_COMMAND_PARAMS(
+		EC_CMD_PD_WRITE_LOG_ENTRY, UINT8_C(0), params);
+
+	params.port = board_get_usb_pd_port_count() + 1;
+	zassert_equal(EC_RES_INVALID_PARAM, host_command_process(&args), NULL);
+}
+
+ZTEST_USER_F(pd_log, test_mcu_charge)
+{
+	struct ec_params_pd_write_log_entry params = {
+		.type = PD_EVENT_MCU_CHARGE,
+		.port = 0,
+	};
+	struct host_cmd_handler_args args = BUILD_HOST_COMMAND_PARAMS(
+		EC_CMD_PD_WRITE_LOG_ENTRY, UINT8_C(0), params);
+
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_equal(sizeof(struct event_log_entry) + PD_LOG_ENTRY_DATA_SIZE,
+		      log_dequeue_event(&fixture->log_entry), NULL);
+	zassert_equal(params.type, fixture->log_entry.type, NULL);
+	zassert_equal(PD_LOG_ENTRY_DATA_SIZE, fixture->log_entry.size, NULL);
+	zassert_equal(0, fixture->log_entry.data, NULL);
+	zassert_within(0, (int64_t)fixture->log_entry.timestamp, 10,
+		       "Expected timestamp %" PRIi64
+		       " to be within 10 ms of now",
+		       (int64_t)fixture->log_entry.timestamp);
+}
+ZTEST_USER_F(pd_log, test_mcu_connect)
+{
+	struct ec_params_pd_write_log_entry params = {
+		.type = PD_EVENT_MCU_CONNECT,
+		.port = 0,
+	};
+	struct host_cmd_handler_args args = BUILD_HOST_COMMAND_PARAMS(
+		EC_CMD_PD_WRITE_LOG_ENTRY, UINT8_C(0), params);
+
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_equal(sizeof(struct event_log_entry),
+		      log_dequeue_event(&fixture->log_entry), NULL);
+	zassert_equal(params.type, fixture->log_entry.type, NULL);
+	zassert_equal(0, fixture->log_entry.size, NULL);
+	zassert_equal(0, fixture->log_entry.data, NULL);
+	zassert_within(0, (int64_t)fixture->log_entry.timestamp, 10,
+		       "Expected timestamp %" PRIi64
+		       " to be within 10 ms of now",
+		       (int64_t)fixture->log_entry.timestamp);
+}
+
+ZTEST_USER_F(pd_log, test_read_log_entry)
+{
+	uint8_t response_buffer[sizeof(struct ec_response_pd_log) + 16];
+	struct ec_response_pd_log *response =
+		(struct ec_response_pd_log *)response_buffer;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_SIMPLE(EC_CMD_PD_GET_LOG_ENTRY, UINT8_C(0));
+
+	args.response = response;
+	args.response_max = sizeof(response_buffer);
+
+	zassert_ok(host_command_process(&args), NULL);
+	zassert_equal(sizeof(struct event_log_entry), args.response_size, NULL);
+	zassert_equal(PD_EVENT_NO_ENTRY, response->type, NULL);
+}
diff --git a/zephyr/test/drivers/host_cmd/src/usb_pd_control.c b/zephyr/test/drivers/host_cmd/src/usb_pd_control.c
new file mode 100644
index 0000000000..c439141da9
--- /dev/null
+++ b/zephyr/test/drivers/host_cmd/src/usb_pd_control.c
@@ -0,0 +1,151 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/shell/shell.h>
+#include <zephyr/ztest.h>
+
+#include "console.h"
+#include "ec_commands.h"
+#include "emul/emul_isl923x.h"
+#include "emul/tcpc/emul_ps8xxx.h"
+#include "emul/tcpc/emul_tcpci.h"
+#include "emul/tcpc/emul_tcpci_partner_snk.h"
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+
+#define TEST_PORT USBC_PORT_C0
+#define BAD_PORT 42
+
+struct host_cmd_usb_pd_control_fixture {
+	const struct emul *tcpci_emul;
+	const struct emul *charger_emul;
+	struct tcpci_partner_data partner;
+	struct tcpci_snk_emul_data snk_ext;
+};
+
+static enum ec_status
+run_usb_pd_control(int port, struct ec_response_usb_pd_control_v2 *resp)
+{
+	/*
+	 * Note: while arguments exist to change the PD state, their use is
+	 * discouraged as that causes the response to have non-deterministic
+	 * results.  The kernel only uses the "no change" parameters, so that is
+	 * what we shall test here.
+	 */
+	struct ec_params_usb_pd_control params = {
+		.port = port,
+		.role = USB_PD_CTRL_ROLE_NO_CHANGE,
+		.mux = USB_PD_CTRL_MUX_NO_CHANGE,
+		.swap = USB_PD_CTRL_SWAP_NONE
+	};
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_USB_PD_CONTROL, 2, *resp, params);
+
+	return host_command_process(&args);
+}
+
+ZTEST_USER(host_cmd_usb_pd_control, test_good_index_no_partner)
+{
+	struct ec_response_usb_pd_control_v2 response;
+
+	zassert_ok(run_usb_pd_control(TEST_PORT, &response),
+		   "Failed to process usb_pd_control for port %d", TEST_PORT);
+
+	/* Verify basic not-connected expectations */
+	zassert_equal(response.enabled, 0,
+		      "Failed to find nothing enabled: 0x%02x",
+		      response.enabled);
+	/* Don't verify role, cc, or polarity as it isn't meaningful */
+	zassert_equal(response.control_flags, 0, "Failed to see flags cleared");
+}
+
+ZTEST_USER_F(host_cmd_usb_pd_control, test_good_index_sink_partner)
+{
+	struct ec_response_usb_pd_control_v2 response;
+
+	/* Attach simple sink that shouldn't do any swaps */
+	connect_sink_to_port(&fixture->partner, fixture->tcpci_emul,
+			     fixture->charger_emul);
+
+	/* Wait for connection to settle */
+	k_sleep(K_SECONDS(1));
+
+	zassert_ok(run_usb_pd_control(TEST_PORT, &response),
+		   "Failed to process usb_pd_control for port %d", TEST_PORT);
+
+	/* Verify basic sink expectations */
+	zassert_equal(
+		response.enabled,
+		(PD_CTRL_RESP_ENABLED_COMMS | PD_CTRL_RESP_ENABLED_CONNECTED |
+		 PD_CTRL_RESP_ENABLED_PD_CAPABLE),
+		"Failed to see full connection: 0x%02x", response.enabled);
+	/*
+	 * We should be source, DFP, Vconn source, and we set our sink caps
+	 * to USB comms
+	 */
+	zassert_equal(response.role,
+		      (PD_CTRL_RESP_ROLE_USB_COMM | PD_CTRL_RESP_ROLE_POWER |
+		       PD_CTRL_RESP_ROLE_DATA | PD_CTRL_RESP_ROLE_VCONN),
+		      "Failed to see expected role: 0x%02x", response.role);
+	zassert_equal(response.cc_state, PD_CC_UFP_ATTACHED,
+		      "Failed to see UFP attached");
+	zassert_equal(response.control_flags, 0, "Failed to see flags cleared");
+}
+
+ZTEST_USER(host_cmd_usb_pd_control, test_bad_index)
+{
+	struct ec_response_usb_pd_control_v2 response;
+
+	zassume_true(board_get_usb_pd_port_count() < BAD_PORT,
+		     "Intended bad port exists");
+	zassert_equal(run_usb_pd_control(BAD_PORT, &response),
+		      EC_RES_INVALID_PARAM,
+		      "Failed to fail usb_pd_control for port %d", BAD_PORT);
+}
+
+static void *host_cmd_usb_pd_control_setup(void)
+{
+	static struct host_cmd_usb_pd_control_fixture fixture;
+	struct tcpci_partner_data *partner = &fixture.partner;
+	struct tcpci_snk_emul_data *snk_ext = &fixture.snk_ext;
+
+	tcpci_partner_init(partner, PD_REV30);
+	partner->extensions = tcpci_snk_emul_init(snk_ext, partner, NULL);
+
+	/* Get references for the emulators */
+	fixture.tcpci_emul = EMUL_DT_GET(DT_NODELABEL(tcpci_emul));
+	fixture.charger_emul = EMUL_DT_GET(DT_NODELABEL(isl923x_emul));
+
+	/* Sink 5V 3A. */
+	snk_ext->pdo[0] = PDO_FIXED(5000, 3000, PDO_FIXED_COMM_CAP);
+
+	return &fixture;
+}
+
+static void host_cmd_usb_pd_control_before(void *data)
+{
+	ARG_UNUSED(data);
+
+	/* Assume we have at least one USB-C port */
+	zassume_true(board_get_usb_pd_port_count() > 0,
+		     "Insufficient TCPCs found");
+
+	/* Set the system into S0, since the AP would drive these commands */
+	test_set_chipset_to_s0();
+	k_sleep(K_SECONDS(1));
+}
+
+static void host_cmd_usb_pd_control_after(void *data)
+{
+	struct host_cmd_usb_pd_control_fixture *fixture = data;
+
+	disconnect_sink_from_port(fixture->tcpci_emul);
+	k_sleep(K_SECONDS(1));
+}
+
+ZTEST_SUITE(host_cmd_usb_pd_control, drivers_predicate_post_main,
+	    host_cmd_usb_pd_control_setup, host_cmd_usb_pd_control_before,
+	    host_cmd_usb_pd_control_after, NULL);
diff --git a/zephyr/test/drivers/isl923x/CMakeLists.txt b/zephyr/test/drivers/isl923x/CMakeLists.txt
index 36a97589c1..734742c6b6 100644
--- a/zephyr/test/drivers/isl923x/CMakeLists.txt
+++ b/zephyr/test/drivers/isl923x/CMakeLists.txt
@@ -1,22 +1,9 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
-# Create library name based on current directory
-zephyr_library_get_current_dir_lib_name(${ZEPHYR_BASE} lib_name)
-
-# Create interface library
-zephyr_interface_library_named(${lib_name})
-
-# Add include paths
-zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}")
-zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}/include")
-
 # Add source files
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_ADC_AMON_BMON
-			"${CMAKE_CURRENT_SOURCE_DIR}/src/console_cmd_amon_bmon.c")
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGE_RAMP_HW
-			"${CMAKE_CURRENT_SOURCE_DIR}/src/charge_ramp_hw.c")
-
-# Link in the library
-zephyr_library_link_libraries(${lib_name})
+target_sources_ifdef(CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_ADC_AMON_BMON
+			app PRIVATE src/console_cmd_amon_bmon.c)
+target_sources_ifdef(CONFIG_PLATFORM_EC_CHARGE_RAMP_HW
+			app PRIVATE src/charge_ramp_hw.c)
diff --git a/zephyr/test/drivers/isl923x/src/charge_ramp_hw.c b/zephyr/test/drivers/isl923x/src/charge_ramp_hw.c
index c1ae9ce240..c814b75de9 100644
--- a/zephyr/test/drivers/isl923x/src/charge_ramp_hw.c
+++ b/zephyr/test/drivers/isl923x/src/charge_ramp_hw.c
@@ -1,10 +1,9 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-
-#include <ztest.h>
+#include <zephyr/ztest.h>
 
 #include "driver/charger/isl923x.h"
 #include "driver/charger/isl923x_public.h"
@@ -14,10 +13,10 @@
 #include "test/drivers/test_state.h"
 
 #define CHARGER_NUM get_charger_num(&isl923x_drv)
-#define ISL923X_EMUL emul_get_binding(DT_LABEL(DT_NODELABEL(isl923x_emul)))
+#define ISL923X_EMUL EMUL_DT_GET(DT_NODELABEL(isl923x_emul))
 
-ZTEST_SUITE(charge_ramp_hw, drivers_predicate_post_main, NULL, NULL,
-	    NULL, NULL);
+ZTEST_SUITE(charge_ramp_hw, drivers_predicate_post_main, NULL, NULL, NULL,
+	    NULL);
 
 ZTEST(charge_ramp_hw, test_charge_ramp_hw_ramp)
 {
@@ -33,20 +32,20 @@ ZTEST(charge_ramp_hw, test_charge_ramp_hw_ramp)
 
 ZTEST(charge_ramp_hw, test_charge_ramp_hw_ramp_read_fail_reg0)
 {
-	const struct emul *isl923x_emul = ISL923X_EMUL;
-	struct i2c_emul *i2c_emul = isl923x_emul_get_i2c_emul(isl923x_emul);
+	struct i2c_common_emul_data *common_data =
+		emul_isl923x_get_i2c_common_data(ISL923X_EMUL);
 
-	i2c_common_emul_set_read_fail_reg(i2c_emul, ISL923X_REG_CONTROL0);
+	i2c_common_emul_set_read_fail_reg(common_data, ISL923X_REG_CONTROL0);
 	zassert_equal(EC_ERROR_INVAL, isl923x_drv.set_hw_ramp(CHARGER_NUM, 1),
 		      NULL);
 }
 
 ZTEST(charge_ramp_hw, test_charge_ramp_hw_ramp_read_fail_acl1)
 {
-	const struct emul *isl923x_emul = ISL923X_EMUL;
-	struct i2c_emul *i2c_emul = isl923x_emul_get_i2c_emul(isl923x_emul);
+	struct i2c_common_emul_data *common_data =
+		emul_isl923x_get_i2c_common_data(ISL923X_EMUL);
 
-	i2c_common_emul_set_read_fail_reg(i2c_emul,
+	i2c_common_emul_set_read_fail_reg(common_data,
 					  ISL923X_REG_ADAPTER_CURRENT_LIMIT1);
 	zassert_equal(0, isl923x_drv.ramp_get_current_limit(CHARGER_NUM), NULL);
 }
diff --git a/zephyr/test/drivers/isl923x/src/console_cmd_amon_bmon.c b/zephyr/test/drivers/isl923x/src/console_cmd_amon_bmon.c
index bdbdd083ba..9246bf5b6b 100644
--- a/zephyr/test/drivers/isl923x/src/console_cmd_amon_bmon.c
+++ b/zephyr/test/drivers/isl923x/src/console_cmd_amon_bmon.c
@@ -1,4 +1,4 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,7 @@
 #include <zephyr/drivers/adc.h>
 #include <zephyr/drivers/adc/adc_emul.h>
 #include <zephyr/shell/shell.h>
-#include <ztest.h>
+#include <zephyr/ztest.h>
 
 #include "adc.h"
 #include "console.h"
@@ -21,7 +21,7 @@
 
 #define ADC_DEVICE_NODE DT_NODELABEL(adc0)
 #define CHARGER_NUM get_charger_num(&isl923x_drv)
-#define ISL923X_EMUL emul_get_binding(DT_LABEL(DT_NODELABEL(isl923x_emul)))
+#define ISL923X_EMUL EMUL_DT_GET(DT_NODELABEL(isl923x_emul))
 
 ZTEST_SUITE(console_cmd_amon_bmon, drivers_predicate_post_main, NULL, NULL,
 	    NULL, NULL);
@@ -60,13 +60,14 @@ ZTEST(console_cmd_amon_bmon, test_isl923x_amonbmon_get_input_current)
 }
 
 ZTEST(console_cmd_amon_bmon,
-	test_isl923x_amonbmon_get_input_current_read_fail_req1)
+      test_isl923x_amonbmon_get_input_current_read_fail_req1)
 {
 	const struct emul *isl923x_emul = ISL923X_EMUL;
-	struct i2c_emul *i2c_emul = isl923x_emul_get_i2c_emul(isl923x_emul);
+	struct i2c_common_emul_data *common_data =
+		emul_isl923x_get_i2c_common_data(isl923x_emul);
 	int current_milli_amps;
 
-	i2c_common_emul_set_read_fail_reg(i2c_emul, ISL923X_REG_CONTROL1);
+	i2c_common_emul_set_read_fail_reg(common_data, ISL923X_REG_CONTROL1);
 	zassert_equal(EC_ERROR_INVAL,
 		      isl923x_drv.get_input_current(CHARGER_NUM,
 						    &current_milli_amps),
@@ -76,13 +77,14 @@ ZTEST(console_cmd_amon_bmon,
 }
 
 ZTEST(console_cmd_amon_bmon,
-	test_isl923x_amonbmon_get_input_current_read_fail_req3)
+      test_isl923x_amonbmon_get_input_current_read_fail_req3)
 {
 	const struct emul *isl923x_emul = ISL923X_EMUL;
-	struct i2c_emul *i2c_emul = isl923x_emul_get_i2c_emul(isl923x_emul);
+	struct i2c_common_emul_data *common_data =
+		emul_isl923x_get_i2c_common_data(isl923x_emul);
 	int current_milli_amps;
 
-	i2c_common_emul_set_read_fail_reg(i2c_emul, ISL9238_REG_CONTROL3);
+	i2c_common_emul_set_read_fail_reg(common_data, ISL9238_REG_CONTROL3);
 	zassert_equal(EC_ERROR_INVAL,
 		      isl923x_drv.get_input_current(CHARGER_NUM,
 						    &current_milli_amps),
@@ -90,13 +92,14 @@ ZTEST(console_cmd_amon_bmon,
 }
 
 ZTEST(console_cmd_amon_bmon,
-	test_isl923x_amonbmon_get_input_current_write_fail_req1)
+      test_isl923x_amonbmon_get_input_current_write_fail_req1)
 {
 	const struct emul *isl923x_emul = ISL923X_EMUL;
-	struct i2c_emul *i2c_emul = isl923x_emul_get_i2c_emul(isl923x_emul);
+	struct i2c_common_emul_data *common_data =
+		emul_isl923x_get_i2c_common_data(isl923x_emul);
 	int current_milli_amps;
 
-	i2c_common_emul_set_write_fail_reg(i2c_emul, ISL923X_REG_CONTROL1);
+	i2c_common_emul_set_write_fail_reg(common_data, ISL923X_REG_CONTROL1);
 	zassert_equal(EC_ERROR_INVAL,
 		      isl923x_drv.get_input_current(CHARGER_NUM,
 						    &current_milli_amps),
@@ -104,13 +107,14 @@ ZTEST(console_cmd_amon_bmon,
 }
 
 ZTEST(console_cmd_amon_bmon,
-	test_isl923x_amonbmon_get_input_current_write_fail_req3)
+      test_isl923x_amonbmon_get_input_current_write_fail_req3)
 {
 	const struct emul *isl923x_emul = ISL923X_EMUL;
-	struct i2c_emul *i2c_emul = isl923x_emul_get_i2c_emul(isl923x_emul);
+	struct i2c_common_emul_data *common_data =
+		emul_isl923x_get_i2c_common_data(isl923x_emul);
 	int current_milli_amps;
 
-	i2c_common_emul_set_write_fail_reg(i2c_emul, ISL9238_REG_CONTROL3);
+	i2c_common_emul_set_write_fail_reg(common_data, ISL9238_REG_CONTROL3);
 	zassert_equal(EC_ERROR_INVAL,
 		      isl923x_drv.get_input_current(CHARGER_NUM,
 						    &current_milli_amps),
diff --git a/zephyr/test/drivers/keyboard_scan/CMakeLists.txt b/zephyr/test/drivers/keyboard_scan/CMakeLists.txt
new file mode 100644
index 0000000000..07040187f2
--- /dev/null
+++ b/zephyr/test/drivers/keyboard_scan/CMakeLists.txt
@@ -0,0 +1,15 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_sources(app PRIVATE
+  src/keyboard_backlight.c
+  src/keyboard_scan.c
+  src/keyboard_test_utils.c
+  src/mkbp_event.c
+  src/mkbp_info.c
+)
+
+target_include_directories(app PRIVATE
+    ${CMAKE_CURRENT_SOURCE_DIR}/include
+)
diff --git a/zephyr/test/drivers/keyboard_scan/include/keyboard_test_utils.h b/zephyr/test/drivers/keyboard_scan/include/keyboard_test_utils.h
new file mode 100644
index 0000000000..0117fea09c
--- /dev/null
+++ b/zephyr/test/drivers/keyboard_scan/include/keyboard_test_utils.h
@@ -0,0 +1,19 @@
+/* Copyright 2022 The ChromiumOS Authors.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * @brief Press or release a key through the keyboard emulator
+ *
+ * @param row Key row
+ * @param col Key column
+ * @param pressed 1 if pressed, 0 otherwise
+ * @return int 0 if successful
+ */
+int emulate_keystate(int row, int col, int pressed);
+
+/**
+ * @brief Clears any pressed keys in the keyboard emulator
+ */
+void clear_emulated_keys(void);
diff --git a/zephyr/test/drivers/keyboard_scan/src/keyboard_backlight.c b/zephyr/test/drivers/keyboard_scan/src/keyboard_backlight.c
new file mode 100644
index 0000000000..149f25dfdd
--- /dev/null
+++ b/zephyr/test/drivers/keyboard_scan/src/keyboard_backlight.c
@@ -0,0 +1,134 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <zephyr/ztest.h>
+#include <zephyr/kernel.h>
+#include <zephyr/shell/shell_dummy.h>
+#include <zephyr/ztest_assert.h>
+
+#include "console.h"
+#include "host_command.h"
+#include "keyboard_backlight.h"
+#include "test/drivers/test_state.h"
+
+/**
+ * @brief Send host command to set the backlight percentage
+ *
+ * @param percent Backlight intensity, from 0 to 100 (inclusive).
+ * @return uint16_t Host command return code
+ */
+static uint16_t set_backlight_percent_helper(uint8_t percent)
+{
+	struct ec_params_pwm_set_keyboard_backlight params = {
+		.percent = percent
+	};
+	struct host_cmd_handler_args args = BUILD_HOST_COMMAND_PARAMS(
+		EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT, 0, params);
+
+	return host_command_process(&args);
+}
+
+ZTEST(keyboard_backlight, host_command_set_backlight__normal)
+{
+	/* Set the backlight intensity level to this and verify */
+	uint8_t expected_percentage = 50;
+
+	zassert_ok(set_backlight_percent_helper(expected_percentage), NULL);
+	zassert_equal(expected_percentage, kblight_get(), NULL);
+}
+
+ZTEST(keyboard_backlight, host_command_set_backlight__out_of_range)
+{
+	/* Too high */
+	uint8_t expected_percentage = 101;
+
+	zassert_equal(EC_RES_ERROR,
+		      set_backlight_percent_helper(expected_percentage), NULL);
+}
+
+ZTEST(keyboard_backlight, host_command_get_backlight__normal)
+{
+	/* Set this backlight intensity and verify via host command */
+	uint8_t expected_percentage = 50;
+	int ret;
+
+	zassume_ok(set_backlight_percent_helper(expected_percentage), NULL);
+
+	/* Brief delay to allow a deferred function to enable the backlight */
+	k_sleep(K_MSEC(50));
+
+	struct ec_response_pwm_get_keyboard_backlight response;
+	struct host_cmd_handler_args args = BUILD_HOST_COMMAND_RESPONSE(
+		EC_CMD_PWM_GET_KEYBOARD_BACKLIGHT, 0, response);
+
+	ret = host_command_process(&args);
+	zassert_ok(ret, "Host command failed: %d", ret);
+	zassert_equal(expected_percentage, response.percent, NULL);
+	zassert_equal(1, response.enabled, "Got 0x%02x", response.enabled);
+}
+
+ZTEST(keyboard_backlight, console_command__noargs)
+{
+	/* Command should print current status. Set backlight on and to 70% */
+
+	const char *outbuffer;
+	size_t buffer_size;
+
+	zassume_ok(set_backlight_percent_helper(70), NULL);
+	k_sleep(K_MSEC(50));
+
+	/* With no args, print current state */
+	shell_backend_dummy_clear_output(get_ec_shell());
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "kblight"), NULL);
+	outbuffer =
+		shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+
+	zassert_ok(!strstr(outbuffer, "Keyboard backlight: 70% enabled: 1"),
+		   "Actual string: `%s`", outbuffer);
+}
+
+ZTEST(keyboard_backlight, console_command__set_on)
+{
+	/* Command should enable backlight to given intensity */
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "kblight 65"), NULL);
+	zassert_equal(65, kblight_get(), NULL);
+	zassert_equal(1, kblight_get_current_enable(), NULL);
+}
+
+ZTEST(keyboard_backlight, console_command__set_off)
+{
+	zassume_ok(set_backlight_percent_helper(40), NULL);
+	k_sleep(K_MSEC(50));
+
+	/* Turn back off */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "kblight 0"), NULL);
+	zassert_equal(0, kblight_get(), NULL);
+	zassert_equal(0, kblight_get_current_enable(), NULL);
+}
+
+ZTEST(keyboard_backlight, console_command__bad_params)
+{
+	zassert_equal(EC_ERROR_PARAM1,
+		      shell_execute_cmd(get_ec_shell(), "kblight NaN"), NULL);
+	zassert_equal(EC_ERROR_PARAM1,
+		      shell_execute_cmd(get_ec_shell(), "kblight -1"), NULL);
+	zassert_equal(EC_ERROR_PARAM1,
+		      shell_execute_cmd(get_ec_shell(), "kblight 101"), NULL);
+}
+
+static void reset(void *data)
+{
+	ARG_UNUSED(data);
+
+	/* Reset the backlight to off and 0% brightness */
+	kblight_set(0);
+	kblight_enable(0);
+}
+
+ZTEST_SUITE(keyboard_backlight, drivers_predicate_post_main, NULL, reset, reset,
+	    NULL);
diff --git a/zephyr/test/drivers/keyboard_scan/src/keyboard_scan.c b/zephyr/test/drivers/keyboard_scan/src/keyboard_scan.c
new file mode 100644
index 0000000000..c7955ec655
--- /dev/null
+++ b/zephyr/test/drivers/keyboard_scan/src/keyboard_scan.c
@@ -0,0 +1,420 @@
+/* Copyright 2022 The ChromiumOS Authors.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include <string.h>
+#include <zephyr/shell/shell_dummy.h>
+#include <zephyr/ztest.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/fff.h>
+#include <emul/emul_kb_raw.h>
+
+#include "console.h"
+#include "host_command.h"
+#include "keyboard_scan.h"
+#include "keyboard_test_utils.h"
+#include "test/drivers/test_mocks.h"
+#include "test/drivers/test_state.h"
+
+ZTEST(keyboard_scan, test_boot_key)
+{
+	const struct device *dev = DEVICE_DT_GET(DT_NODELABEL(cros_kb_raw));
+	const int kb_cols = DT_PROP(DT_NODELABEL(cros_kb_raw), cols);
+
+	emul_kb_raw_reset(dev);
+	zassert_equal(keyboard_scan_get_boot_keys(), BOOT_KEY_NONE, NULL);
+
+	/* Case 1: refresh + esc -> BOOT_KEY_ESC */
+	emul_kb_raw_reset(dev);
+	zassert_ok(emulate_keystate(KEYBOARD_ROW_REFRESH, KEYBOARD_COL_REFRESH,
+				    true),
+		   NULL);
+	zassert_ok(emulate_keystate(KEYBOARD_ROW_ESC, KEYBOARD_COL_ESC, true),
+		   NULL);
+	keyboard_scan_init();
+	zassert_equal(keyboard_scan_get_boot_keys(), BOOT_KEY_ESC, NULL);
+
+	/*
+	 * Case 1.5:
+	 * GSC may hold ksi2 when power button is pressed, simulate this
+	 * behavior and verify boot key detection again.
+	 */
+	zassert_true(IS_ENABLED(CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2), NULL);
+	for (int i = 0; i < kb_cols; i++) {
+		zassert_ok(emulate_keystate(KEYBOARD_ROW_REFRESH, i, true),
+			   NULL);
+	}
+	keyboard_scan_init();
+	zassert_equal(keyboard_scan_get_boot_keys(), BOOT_KEY_ESC, NULL);
+
+	/* Case 2: esc only -> BOOT_KEY_NONE */
+	emul_kb_raw_reset(dev);
+	zassert_ok(emulate_keystate(KEYBOARD_ROW_ESC, KEYBOARD_COL_ESC, true),
+		   NULL);
+	keyboard_scan_init();
+	zassert_equal(keyboard_scan_get_boot_keys(), BOOT_KEY_NONE, NULL);
+
+	/* Case 3: refresh + arrow down -> BOOT_KEY_DOWN_ARROW */
+	emul_kb_raw_reset(dev);
+	zassert_ok(emulate_keystate(KEYBOARD_ROW_REFRESH, KEYBOARD_COL_REFRESH,
+				    true),
+		   NULL);
+	zassert_ok(emulate_keystate(KEYBOARD_ROW_DOWN, KEYBOARD_COL_DOWN, true),
+		   NULL);
+	keyboard_scan_init();
+	zassert_equal(keyboard_scan_get_boot_keys(), BOOT_KEY_DOWN_ARROW, NULL);
+
+	/* Case 4: refresh + L shift -> BOOT_KEY_LEFT_SHIFT */
+	emul_kb_raw_reset(dev);
+	zassert_ok(emulate_keystate(KEYBOARD_ROW_REFRESH, KEYBOARD_COL_REFRESH,
+				    true),
+		   NULL);
+	zassert_ok(emulate_keystate(KEYBOARD_ROW_LEFT_SHIFT,
+				    KEYBOARD_COL_LEFT_SHIFT, true),
+		   NULL);
+	keyboard_scan_init();
+	zassert_equal(keyboard_scan_get_boot_keys(), BOOT_KEY_LEFT_SHIFT, NULL);
+
+	/* Case 5: refresh + esc + other random key -> BOOT_KEY_NONE */
+	emul_kb_raw_reset(dev);
+	zassert_ok(emulate_keystate(KEYBOARD_ROW_REFRESH, KEYBOARD_COL_REFRESH,
+				    true),
+		   NULL);
+	zassert_ok(emulate_keystate(KEYBOARD_ROW_ESC, KEYBOARD_COL_ESC, true),
+		   NULL);
+	zassert_ok(emulate_keystate(KEYBOARD_ROW_KEY_0, KEYBOARD_COL_KEY_0,
+				    true),
+		   NULL);
+	keyboard_scan_init();
+	zassert_equal(keyboard_scan_get_boot_keys(), BOOT_KEY_NONE, NULL);
+
+	/* Case 6: BOOT_KEY_NONE after late sysjump */
+	system_jumped_late_fake.return_val = 1;
+	emul_kb_raw_reset(dev);
+	zassert_ok(emulate_keystate(KEYBOARD_ROW_REFRESH, KEYBOARD_COL_REFRESH,
+				    true),
+		   NULL);
+	zassert_ok(emulate_keystate(KEYBOARD_ROW_LEFT_SHIFT,
+				    KEYBOARD_COL_LEFT_SHIFT, true),
+		   NULL);
+	keyboard_scan_init();
+	zassert_equal(keyboard_scan_get_boot_keys(), BOOT_KEY_NONE, NULL);
+}
+
+ZTEST(keyboard_scan, test_press_enter)
+{
+	zassert_ok(emulate_keystate(4, 11, true), NULL);
+	k_sleep(K_MSEC(100));
+	/* TODO(jbettis): Check espi_emul to verify the AP was notified. */
+	zassert_ok(emulate_keystate(4, 11, false), NULL);
+	k_sleep(K_MSEC(100));
+}
+
+ZTEST(keyboard_scan, console_command_ksstate__noargs)
+{
+	const char *outbuffer;
+	size_t buffer_size;
+
+	/* With no args, print current state */
+	shell_backend_dummy_clear_output(get_ec_shell());
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "ksstate"), NULL);
+	outbuffer =
+		shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+
+	/* Check for some expected lines */
+	zassert_true(buffer_size > 0, NULL);
+	zassert_ok(!strstr(outbuffer, "Keyboard scan disable mask: 0x00000000"),
+		   "Output was: `%s`", outbuffer);
+	zassert_ok(!strstr(outbuffer, "Keyboard scan state printing off"),
+		   "Output was: `%s`", outbuffer);
+
+	/* Ensure we are still scanning */
+	zassert_true(keyboard_scan_is_enabled(), NULL);
+}
+
+ZTEST(keyboard_scan, console_command_ksstate__force)
+{
+	/* This command forces the keyboard to start scanning (if not already)
+	 * and enable state change printing. To test: turn scanning off, run
+	 * command, and verify we are scanning and printing state
+	 */
+
+	keyboard_scan_enable(false, -1);
+	zassume_false(keyboard_scan_is_enabled(), NULL);
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "ksstate force"), NULL);
+
+	zassert_true(keyboard_scan_is_enabled(), NULL);
+	zassert_true(keyboard_scan_get_print_state_changes(), NULL);
+}
+
+ZTEST(keyboard_scan, console_command_ksstate__on_off)
+{
+	/* This command turns state change printing on/off */
+
+	zassume_false(keyboard_scan_get_print_state_changes(), NULL);
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "ksstate on"), NULL);
+	zassert_true(keyboard_scan_get_print_state_changes(), NULL);
+
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "ksstate off"), NULL);
+	zassert_false(keyboard_scan_get_print_state_changes(), NULL);
+}
+
+ZTEST(keyboard_scan, console_command_ksstate__invalid)
+{
+	/* Pass a string that cannot be parsed as a bool */
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "ksstate xyz"), NULL);
+}
+
+ZTEST(keyboard_scan, console_command_kbpress__noargs)
+{
+	const char *outbuffer;
+	size_t buffer_size;
+
+	/* With no args, print list of simulated keys */
+	shell_backend_dummy_clear_output(get_ec_shell());
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "kbpress"), NULL);
+	outbuffer =
+		shell_backend_dummy_get_output(get_ec_shell(), &buffer_size);
+
+	/* Check for an expected line */
+	zassert_true(buffer_size > 0, NULL);
+	zassert_ok(!strstr(outbuffer, "Simulated keys:"), "Output was: `%s`",
+		   outbuffer);
+}
+
+ZTEST(keyboard_scan, console_command_kbpress__invalid)
+{
+	/* Row or column number out of range, or wrong type */
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "kbpress -1 0"), NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "kbpress foo 0"), NULL);
+	zassert_ok(!shell_execute_cmd(
+			   get_ec_shell(),
+			   "kbpress " STRINGIFY(KEYBOARD_COLS_MAX) " 0"),
+		   NULL);
+
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "kbpress 0 -1"), NULL);
+	zassert_ok(!shell_execute_cmd(get_ec_shell(), "kbpress 0 foo"), NULL);
+	zassert_ok(
+		!shell_execute_cmd(get_ec_shell(),
+				   "kbpress 0 " STRINGIFY(KEYBOARD_COLS_MAX)),
+		NULL);
+}
+
+/* Mock the key_state_changed callback that the key scan task invokes whenever
+ * a key event occurs. This will capture a history of key presses.
+ */
+FAKE_VOID_FUNC(key_state_changed, int, int, uint8_t);
+
+ZTEST(keyboard_scan, console_command_kbpress__press_and_release)
+{
+	/* Pres and release a key */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "kbpress 1 2"), NULL);
+
+	/* Hold a key down */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "kbpress 3 4 1"), NULL);
+
+	/* Release the key */
+	zassert_ok(shell_execute_cmd(get_ec_shell(), "kbpress 3 4 0"), NULL);
+
+	/* Pause a bit to allow the key scan task to process. */
+	k_sleep(K_MSEC(200));
+
+	/* Expect four key events */
+	zassert_equal(4, key_state_changed_fake.call_count, NULL);
+
+	/* Press col=1,row=2 (state==1) */
+	zassert_equal(1, key_state_changed_fake.arg1_history[0], NULL);
+	zassert_equal(2, key_state_changed_fake.arg0_history[0], NULL);
+	zassert_true(key_state_changed_fake.arg2_history[0], NULL);
+
+	/* Release col=1,row=2 (state==0) */
+	zassert_equal(1, key_state_changed_fake.arg1_history[1], NULL);
+	zassert_equal(2, key_state_changed_fake.arg0_history[1], NULL);
+	zassert_false(key_state_changed_fake.arg2_history[1], NULL);
+
+	/* Press col=3,row=4 (state==1) */
+	zassert_equal(3, key_state_changed_fake.arg1_history[2], NULL);
+	zassert_equal(4, key_state_changed_fake.arg0_history[2], NULL);
+	zassert_true(key_state_changed_fake.arg2_history[2], NULL);
+
+	/* Release col=3,row=4 (state==0) */
+	zassert_equal(3, key_state_changed_fake.arg1_history[3], NULL);
+	zassert_equal(4, key_state_changed_fake.arg0_history[3], NULL);
+	zassert_false(key_state_changed_fake.arg2_history[3], NULL);
+}
+
+ZTEST(keyboard_scan, host_command_simulate_key__locked)
+{
+	uint16_t ret;
+
+	zassume_true(system_is_locked(), "Expecting locked system.");
+
+	struct ec_response_keyboard_factory_test response;
+	struct ec_params_mkbp_simulate_key params;
+	struct host_cmd_handler_args args = BUILD_HOST_COMMAND(
+		EC_CMD_MKBP_SIMULATE_KEY, 0, response, params);
+
+	ret = host_command_process(&args);
+	zassert_equal(EC_RES_ACCESS_DENIED, ret, "Command returned %u", ret);
+}
+
+ZTEST(keyboard_scan, host_command_simulate_key__bad_params)
+{
+	uint16_t ret;
+
+	system_is_locked_fake.return_val = 0;
+	zassume_false(system_is_locked(), "Expecting unlocked system.");
+
+	struct ec_response_keyboard_factory_test response;
+	struct ec_params_mkbp_simulate_key params = {
+		.col = KEYBOARD_COLS_MAX,
+		.row = KEYBOARD_ROWS,
+	};
+	struct host_cmd_handler_args args = BUILD_HOST_COMMAND(
+		EC_CMD_MKBP_SIMULATE_KEY, 0, response, params);
+
+	ret = host_command_process(&args);
+	zassert_equal(EC_RES_INVALID_PARAM, ret, "Command returned %u", ret);
+}
+
+/**
+ * @brief Helper function that sends a host command to press or release the
+ *        specified key.
+ *
+ * @param col Key column
+ * @param row Key row
+ * @param pressed 1=press, 0=release
+ * @return uint16_t Host command return code.
+ */
+static uint16_t send_keypress_host_command(uint8_t col, uint8_t row,
+					   uint8_t pressed)
+{
+	struct ec_params_mkbp_simulate_key params = {
+		.col = col,
+		.row = row,
+		.pressed = pressed,
+	};
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_PARAMS(EC_CMD_MKBP_SIMULATE_KEY, 0, params);
+
+	return host_command_process(&args);
+}
+
+ZTEST(keyboard_scan, host_command_simulate__key_press)
+{
+	uint16_t ret;
+
+	system_is_locked_fake.return_val = 0;
+	zassume_false(system_is_locked(), "Expecting unlocked system.");
+
+	ret = send_keypress_host_command(1, 2, 1);
+	zassert_equal(EC_RES_SUCCESS, ret, "Command returned %u", ret);
+
+	/* Release the key */
+	ret = send_keypress_host_command(1, 2, 0);
+	zassert_equal(EC_RES_SUCCESS, ret, "Command returned %u", ret);
+
+	/* Verify key events happened */
+
+	zassert_equal(2, key_state_changed_fake.call_count, NULL);
+
+	/* Press col=1,row=2 (state==1) */
+	zassert_equal(1, key_state_changed_fake.arg1_history[0], NULL);
+	zassert_equal(2, key_state_changed_fake.arg0_history[0], NULL);
+	zassert_true(key_state_changed_fake.arg2_history[0], NULL);
+
+	/* Release col=1,row=2 (state==0) */
+	zassert_equal(1, key_state_changed_fake.arg1_history[1], NULL);
+	zassert_equal(2, key_state_changed_fake.arg0_history[1], NULL);
+	zassert_false(key_state_changed_fake.arg2_history[1], NULL);
+}
+
+FAKE_VOID_FUNC(system_enter_hibernate, uint32_t, uint32_t);
+FAKE_VOID_FUNC(chipset_reset, int);
+
+ZTEST(keyboard_scan, special_key_combos)
+{
+	system_is_locked_fake.return_val = 0;
+	zassume_false(system_is_locked(), "Expecting unlocked system.");
+
+	/* Set the volume up key coordinates to something arbitrary */
+	int vol_up_col = 1;
+	int vol_up_row = 2;
+
+	set_vol_up_key(vol_up_row, vol_up_col);
+
+	/* Vol up and the alt keys must be in different columns */
+	zassume_false(vol_up_col == KEYBOARD_COL_LEFT_ALT, NULL);
+
+	/* Hold down volume up, left alt (either alt key works), and R */
+	zassert_ok(send_keypress_host_command(vol_up_col, vol_up_row, 1), NULL);
+	zassert_ok(send_keypress_host_command(KEYBOARD_COL_LEFT_ALT,
+					      KEYBOARD_ROW_LEFT_ALT, 1),
+		   NULL);
+	zassert_ok(send_keypress_host_command(KEYBOARD_COL_KEY_R,
+					      KEYBOARD_ROW_KEY_R, 1),
+		   NULL);
+
+	k_sleep(K_MSEC(100));
+
+	/* Release R and the press H */
+	zassert_ok(send_keypress_host_command(KEYBOARD_COL_KEY_R,
+					      KEYBOARD_ROW_KEY_R, 0),
+		   NULL);
+	zassert_ok(send_keypress_host_command(KEYBOARD_COL_KEY_H,
+					      KEYBOARD_ROW_KEY_H, 1),
+		   NULL);
+
+	k_sleep(K_MSEC(100));
+
+	/* Release all */
+	zassert_ok(send_keypress_host_command(vol_up_col, vol_up_row, 0), NULL);
+	zassert_ok(send_keypress_host_command(KEYBOARD_COL_LEFT_ALT,
+					      KEYBOARD_ROW_LEFT_ALT, 0),
+		   NULL);
+	zassert_ok(send_keypress_host_command(KEYBOARD_COL_KEY_H,
+					      KEYBOARD_ROW_KEY_H, 0),
+		   NULL);
+
+	/* Check that a reboot was requested (VOLUP + ALT + R) */
+	zassert_equal(1, chipset_reset_fake.call_count,
+		      "Did not try to reboot");
+	zassert_equal(CHIPSET_RESET_KB_WARM_REBOOT,
+		      chipset_reset_fake.arg0_history[0], NULL);
+
+	/* Check that we called system_enter_hibernate (VOLUP + ALT + H) */
+	zassert_equal(1, system_enter_hibernate_fake.call_count,
+		      "Did not enter hibernate");
+}
+
+static void reset_keyboard(void *data)
+{
+	ARG_UNUSED(data);
+
+	/* Enable scanning and clear all reason bits (reason bits explain why
+	 * scanning was disabled -- see `enum kb_scan_disable_masks`)
+	 */
+	keyboard_scan_enable(true, -1);
+
+	/* Turn off key state change printing */
+	keyboard_scan_set_print_state_changes(0);
+
+	/* Reset KB emulator */
+	clear_emulated_keys();
+
+	/* Reset all mocks. */
+	RESET_FAKE(key_state_changed);
+	RESET_FAKE(system_is_locked);
+	RESET_FAKE(system_enter_hibernate);
+	RESET_FAKE(chipset_reset);
+
+	/* Be locked by default */
+	system_is_locked_fake.return_val = 1;
+}
+
+ZTEST_SUITE(keyboard_scan, drivers_predicate_post_main, NULL, reset_keyboard,
+	    reset_keyboard, NULL);
diff --git a/zephyr/test/drivers/keyboard_scan/src/keyboard_test_utils.c b/zephyr/test/drivers/keyboard_scan/src/keyboard_test_utils.c
new file mode 100644
index 0000000000..7b49bd1df4
--- /dev/null
+++ b/zephyr/test/drivers/keyboard_scan/src/keyboard_test_utils.c
@@ -0,0 +1,19 @@
+/* Copyright 2022 The ChromiumOS Authors.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <emul/emul_kb_raw.h>
+#include <zephyr/drivers/emul.h>
+
+const static struct device *dev = DEVICE_DT_GET(DT_NODELABEL(cros_kb_raw));
+
+int emulate_keystate(int row, int col, int pressed)
+{
+	return emul_kb_raw_set_kbstate(dev, row, col, pressed);
+}
+
+void clear_emulated_keys(void)
+{
+	emul_kb_raw_reset(dev);
+}
diff --git a/zephyr/test/drivers/keyboard_scan/src/mkbp_event.c b/zephyr/test/drivers/keyboard_scan/src/mkbp_event.c
new file mode 100644
index 0000000000..dee2ba2d1b
--- /dev/null
+++ b/zephyr/test/drivers/keyboard_scan/src/mkbp_event.c
@@ -0,0 +1,189 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include <zephyr/ztest.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/fff.h>
+#include <emul/emul_kb_raw.h>
+
+#include "console.h"
+#include "host_command.h"
+#include "mkbp_event.h"
+#include "mkbp_fifo.h"
+#include "test/drivers/test_mocks.h"
+#include "test/drivers/test_state.h"
+
+/**
+ * @brief FFF fake that will be registered as a callback to monitor the EC->AP
+ *        interrupt pin. Implements `gpio_callback_handler_t`.
+ */
+FAKE_VOID_FUNC(interrupt_gpio_monitor, const struct device *,
+	       struct gpio_callback *, gpio_port_pins_t);
+
+/**
+ * @brief Fixture to hold state while the suite is running.
+ */
+struct event_fixture {
+	/** Configuration for the interrupt pin change callback */
+	struct gpio_callback callback_config;
+};
+
+static struct event_fixture fixture;
+
+ZTEST(mkbp_event, host_command_get_events__empty)
+{
+	/* Issue a host command to get the next event (from any source) */
+	uint16_t ret;
+	struct ec_response_get_next_event response;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_RESPONSE(EC_CMD_GET_NEXT_EVENT, 0, response);
+
+	ret = host_command_process(&args);
+	zassert_equal(EC_RES_UNAVAILABLE, ret,
+		      "Expected EC_RES_UNAVAILABLE but got %d", ret);
+}
+
+ZTEST(mkbp_event, host_command_get_events__get_event)
+{
+	/* Dispatch a fake keyboard event and ensure it gets returned by the
+	 * host command.
+	 */
+	int ret;
+
+	struct ec_response_get_next_event expected_event = {
+		.event_type = EC_MKBP_EVENT_KEY_MATRIX,
+		.data.key_matrix = {
+			/* Arbitrary key matrix data (uint8_t[13]) */
+			0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0xb,
+			0xc, 0xd
+		},
+	};
+
+	/* Add the above event to the MKBP keyboard FIFO and raise the event */
+
+	ret = mkbp_fifo_add(expected_event.event_type,
+			    (const uint8_t *)&expected_event.data.key_matrix);
+	activate_mkbp_with_events(BIT(expected_event.event_type));
+
+	zassert_equal(EC_SUCCESS, ret, "Got %d when adding to FIFO", ret);
+
+	/* Retrieve this event via host command */
+
+	struct ec_response_get_next_event response;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_RESPONSE(EC_CMD_GET_NEXT_EVENT, 0, response);
+
+	ret = host_command_process(&args);
+	zassert_equal(EC_RES_SUCCESS, ret, "Expected EC_RES_SUCCESS but got %d",
+		      ret);
+
+	/* Compare event data in response */
+	zassert_equal(expected_event.event_type, response.event_type,
+		      "Got event type 0x%02x", response.event_type);
+	zassert_mem_equal(&expected_event.data.key_matrix,
+			  &response.data.key_matrix,
+			  sizeof(expected_event.data.key_matrix),
+			  "Event data payload does not match.");
+
+	/* Check for two pin change events (initial assertion when the event
+	 * was sent, and a de-assertion once we retrieved it through the host
+	 * command)
+	 */
+
+	zassert_equal(2, interrupt_gpio_monitor_fake.call_count,
+		      "Only %d pin events",
+		      interrupt_gpio_monitor_fake.call_count);
+}
+
+ZTEST(mkbp_event, no_ap_response)
+{
+	/* Cause an event but do not send any host commands. This should cause
+	 * the EC to send the interrupt to the AP 3 times before giving up.
+	 * Use the GPIO emulator to monitor for interrupts.
+	 */
+
+	int ret;
+
+	struct ec_response_get_next_event expected_event = {
+		.event_type = EC_MKBP_EVENT_KEY_MATRIX,
+	};
+
+	ret = mkbp_fifo_add(expected_event.event_type,
+			    (uint8_t *)&expected_event.data.key_matrix);
+	activate_mkbp_with_events(BIT(expected_event.event_type));
+	zassert_equal(EC_SUCCESS, ret, "Got %d when adding to FIFO", ret);
+
+	/* EC will attempt to signal the interrupt 3 times. Each attempt lasts
+	 * 1 second, so sleep for 5 and then count the number of times the
+	 * interrupt pin was asserted. (It does not get de-asserted)
+	 */
+
+	k_sleep(K_SECONDS(5));
+
+	zassert_equal(3, interrupt_gpio_monitor_fake.call_count,
+		      "Interrupt pin asserted only %d times.",
+		      interrupt_gpio_monitor_fake.call_count);
+}
+
+/* Set up a mock for mkbp_send_event(). This function is called by the MKBP
+ * event sources to signal that a new event is available for servicing. Since we
+ * are unit testing just event handling code, we do not want the various event
+ * source tasks to raise unexpected events during testing and throw us off.
+ * This mock will essentially cause mkbp_send_event() to become a no-op and
+ * block the reset of the EC code from raising events and interfering. The test
+ * code will bypass this by calling mkbp_event.c's internal
+ * `activate_mkbp_with_events()` directly.
+ */
+FAKE_VALUE_FUNC(int, mkbp_send_event, uint8_t);
+
+static void *setup(void)
+{
+	/* Add a callback to the EC->AP interrupt pin so we can log interrupt
+	 * attempts with an FFF fake.
+	 */
+
+	const struct gpio_dt_spec *interrupt_pin =
+		GPIO_DT_FROM_NODELABEL(gpio_ap_ec_int_l);
+
+	fixture.callback_config = (struct gpio_callback){
+		.pin_mask = BIT(interrupt_pin->pin),
+		.handler = interrupt_gpio_monitor,
+	};
+
+	zassume_ok(gpio_add_callback(interrupt_pin->port,
+				     &fixture.callback_config),
+		   "Could not configure GPIO callback.");
+
+	return &fixture;
+}
+
+static void teardown(void *data)
+{
+	/* Remove the GPIO callback on the interrupt pin */
+
+	struct event_fixture *f = (struct event_fixture *)data;
+	const struct gpio_dt_spec *interrupt_pin =
+		GPIO_DT_FROM_NODELABEL(gpio_ap_ec_int_l);
+
+	gpio_remove_callback(interrupt_pin->port, &f->callback_config);
+}
+
+static void reset_events(void *data)
+{
+	/* Clear any keyboard scan events (type EC_MKBP_EVENT_KEY_MATRIX) */
+	mkbp_clear_fifo();
+
+	/* Clear pending events */
+	mkbp_event_clear_all();
+
+	/* Mock reset */
+	RESET_FAKE(interrupt_gpio_monitor);
+	RESET_FAKE(mkbp_send_event);
+	mkbp_send_event_fake.return_val = 1;
+}
+
+ZTEST_SUITE(mkbp_event, drivers_predicate_post_main, setup, reset_events,
+	    reset_events, teardown);
diff --git a/zephyr/test/drivers/keyboard_scan/src/mkbp_info.c b/zephyr/test/drivers/keyboard_scan/src/mkbp_info.c
new file mode 100644
index 0000000000..b0d64eb1da
--- /dev/null
+++ b/zephyr/test/drivers/keyboard_scan/src/mkbp_info.c
@@ -0,0 +1,232 @@
+/* Copyright 2022 The ChromiumOS Authors.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+#include <zephyr/ztest.h>
+#include <zephyr/fff.h>
+#include <emul/emul_kb_raw.h>
+
+#include "console.h"
+#include "host_command.h"
+#include "keyboard_scan.h"
+#include "keyboard_test_utils.h"
+#include "mkbp_info.h"
+#include "mkbp_input_devices.h"
+#include "test/drivers/test_state.h"
+
+ZTEST(mkbp_info, host_command_mkbp_info__keyboard_info)
+{
+	/* Get the number of keyboard rows and columns */
+
+	int ret;
+	struct ec_response_mkbp_info response;
+	struct ec_params_mkbp_info request = {
+		.info_type = EC_MKBP_INFO_KBD,
+	};
+
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_MKBP_INFO, 0, response, request);
+
+	ret = host_command_process(&args);
+	zassert_equal(EC_SUCCESS, ret, "Host command failed: %d", ret);
+	zassert_equal(KEYBOARD_ROWS, response.rows, NULL);
+	zassert_equal(KEYBOARD_COLS_MAX, response.cols, NULL);
+}
+
+ZTEST(mkbp_info, host_command_mkbp_info__supported_buttons)
+{
+	/* Get the set of supported buttons */
+
+	int ret;
+	union ec_response_get_next_data response;
+	struct ec_params_mkbp_info request = {
+		.info_type = EC_MKBP_INFO_SUPPORTED,
+		.event_type = EC_MKBP_EVENT_BUTTON,
+	};
+
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_MKBP_INFO, 0, response, request);
+
+	ret = host_command_process(&args);
+	zassert_equal(EC_SUCCESS, ret, "Host command failed: %d", ret);
+	zassert_equal(get_supported_buttons(), response.buttons, NULL);
+}
+
+ZTEST(mkbp_info, host_command_mkbp_info__supported_switches)
+{
+	/* Get the set of supported switches */
+
+	int ret;
+	union ec_response_get_next_data response;
+	struct ec_params_mkbp_info request = {
+		.info_type = EC_MKBP_INFO_SUPPORTED,
+		.event_type = EC_MKBP_EVENT_SWITCH,
+	};
+
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_MKBP_INFO, 0, response, request);
+
+	ret = host_command_process(&args);
+	zassert_equal(EC_SUCCESS, ret, "Host command failed: %d", ret);
+	zassert_equal(get_supported_switches(), response.switches, NULL);
+}
+
+ZTEST(mkbp_info, host_command_mkbp_info__supported_invalid)
+{
+	/* Request support info on a non-existent type of input device. */
+
+	int ret;
+	union ec_response_get_next_data response;
+	struct ec_params_mkbp_info request = {
+		.info_type = EC_MKBP_INFO_SUPPORTED,
+		.event_type = EC_MKBP_EVENT_COUNT, /* Unsupported */
+	};
+
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_MKBP_INFO, 0, response, request);
+
+	ret = host_command_process(&args);
+	zassert_equal(EC_RES_INVALID_PARAM, ret,
+		      "Host command didn't fail properly: %d", ret);
+}
+
+ZTEST(mkbp_info, host_command_mkbp_info__current_keyboard_matrix)
+{
+	/* Hold down a key so we can validate the returned keyboard matrix state
+	 */
+	const struct device *dev = DEVICE_DT_GET(DT_NODELABEL(cros_kb_raw));
+
+	emul_kb_raw_set_kbstate(dev, KEYBOARD_ROW_KEY_R, KEYBOARD_COL_KEY_R, 1);
+	keyboard_scan_init();
+
+	k_sleep(K_MSEC(100));
+
+	/* Get the current keyboard matrix state */
+
+	int ret;
+	union ec_response_get_next_data response;
+	struct ec_params_mkbp_info request = {
+		.info_type = EC_MKBP_INFO_CURRENT,
+		.event_type = EC_MKBP_EVENT_KEY_MATRIX,
+	};
+
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_MKBP_INFO, 0, response, request);
+
+	ret = host_command_process(&args);
+	zassert_equal(EC_SUCCESS, ret, "Host command failed: %d", ret);
+
+	zassert_true(response.key_matrix[KEYBOARD_COL_KEY_R] &
+			     KEYBOARD_MASK_KEY_R,
+		     "Expected key is not pressed");
+}
+
+ZTEST(mkbp_info, host_command_mkbp_info__current_host_events)
+{
+	int ret;
+	union ec_response_get_next_data response;
+	struct ec_params_mkbp_info request = {
+		.info_type = EC_MKBP_INFO_CURRENT,
+		.event_type = EC_MKBP_EVENT_HOST_EVENT,
+	};
+
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_MKBP_INFO, 0, response, request);
+
+	ret = host_command_process(&args);
+	zassert_equal(EC_SUCCESS, ret, "Host command failed: %d", ret);
+	zassert_equal((uint32_t)host_get_events(), response.host_event, NULL);
+}
+
+ZTEST(mkbp_info, host_command_mkbp_info__current_host_events64)
+{
+	int ret;
+	union ec_response_get_next_data response;
+	struct ec_params_mkbp_info request = {
+		.info_type = EC_MKBP_INFO_CURRENT,
+		.event_type = EC_MKBP_EVENT_HOST_EVENT64,
+	};
+
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_MKBP_INFO, 0, response, request);
+
+	ret = host_command_process(&args);
+	zassert_equal(EC_SUCCESS, ret, "Host command failed: %d", ret);
+	zassert_equal(host_get_events(), response.host_event64, NULL);
+}
+
+ZTEST(mkbp_info, host_command_mkbp_info__current_buttons)
+{
+	int ret;
+	union ec_response_get_next_data response;
+	struct ec_params_mkbp_info request = {
+		.info_type = EC_MKBP_INFO_CURRENT,
+		.event_type = EC_MKBP_EVENT_BUTTON,
+	};
+
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_MKBP_INFO, 0, response, request);
+
+	ret = host_command_process(&args);
+	zassert_equal(EC_SUCCESS, ret, "Host command failed: %d", ret);
+	zassert_equal(mkbp_get_button_state(), response.buttons, NULL);
+}
+
+ZTEST(mkbp_info, host_command_mkbp_info__current_switches)
+{
+	int ret;
+	union ec_response_get_next_data response;
+	struct ec_params_mkbp_info request = {
+		.info_type = EC_MKBP_INFO_CURRENT,
+		.event_type = EC_MKBP_EVENT_SWITCH,
+	};
+
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_MKBP_INFO, 0, response, request);
+
+	ret = host_command_process(&args);
+	zassert_equal(EC_SUCCESS, ret, "Host command failed: %d", ret);
+	zassert_equal(mkbp_get_switch_state(), response.switches, NULL);
+}
+
+ZTEST(mkbp_info, host_command_mkbp_info__current_invalid)
+{
+	int ret;
+	union ec_response_get_next_data response;
+	struct ec_params_mkbp_info request = {
+		.info_type = EC_MKBP_INFO_CURRENT,
+		.event_type = EC_MKBP_EVENT_COUNT, /* Unsupported */
+	};
+
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_MKBP_INFO, 0, response, request);
+
+	ret = host_command_process(&args);
+	zassert_equal(EC_RES_INVALID_PARAM, ret, "Host command failed: %d",
+		      ret);
+}
+
+ZTEST(mkbp_info, host_command_mkbp_info__invalid)
+{
+	int ret;
+	union ec_response_get_next_data response;
+	struct ec_params_mkbp_info request = {
+		.info_type = -1, /* Unsupported */
+	};
+
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND(EC_CMD_MKBP_INFO, 0, response, request);
+
+	ret = host_command_process(&args);
+	zassert_equal(EC_RES_ERROR, ret, "Host command failed: %d", ret);
+}
+
+static void reset(void *data)
+{
+	ARG_UNUSED(data);
+
+	/* Release any pressed keys in the emulator */
+	clear_emulated_keys();
+}
+
+ZTEST_SUITE(mkbp_info, drivers_predicate_post_main, NULL, reset, reset, NULL);
diff --git a/zephyr/test/drivers/led_driver/CMakeLists.txt b/zephyr/test/drivers/led_driver/CMakeLists.txt
index 2f96eba2d3..333785e4df 100644
--- a/zephyr/test/drivers/led_driver/CMakeLists.txt
+++ b/zephyr/test/drivers/led_driver/CMakeLists.txt
@@ -1,20 +1,10 @@
-# Copyright 2022 The ChromiumOS Authors.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
-# Create library name based on current directory
-zephyr_library_get_current_dir_lib_name(${ZEPHYR_BASE} lib_name)
-
-# Create interface library
-zephyr_interface_library_named(${lib_name})
-
 # Add include paths
-zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}")
-zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}/include")
-zephyr_include_directories("${PLATFORM_EC}/zephyr/shim/src/led_driver")
+target_include_directories(app PRIVATE
+    "${PLATFORM_EC}/zephyr/shim/src/led_driver")
 
 # Add source files
-zephyr_library_sources("${CMAKE_CURRENT_SOURCE_DIR}/src/led.c")
-
-# Link in the library
-zephyr_library_link_libraries(${lib_name})
+target_sources(app PRIVATE src/led.c)
diff --git a/zephyr/test/drivers/led_driver/led_pins.dts b/zephyr/test/drivers/led_driver/led_pins.dts
index 0127d762b2..f1488a59d8 100644
--- a/zephyr/test/drivers/led_driver/led_pins.dts
+++ b/zephyr/test/drivers/led_driver/led_pins.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The ChromiumOS Authors.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -7,6 +7,10 @@
   * Modified led-colors to obtain better test coverage.
   */
 / {
+	pwm-led-pins {
+		status = "disabled";
+	};
+
 	gpio-led-pins {
 		compatible = "cros-ec,gpio-led-pins";
 
diff --git a/zephyr/test/drivers/led_driver/led_policy.dts b/zephyr/test/drivers/led_driver/led_policy.dts
index dbbc23062f..fb6d37cb05 100644
--- a/zephyr/test/drivers/led_driver/led_policy.dts
+++ b/zephyr/test/drivers/led_driver/led_policy.dts
@@ -1,4 +1,4 @@
-/* Copyright 2022 The ChromiumOS Authors.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,7 +11,7 @@
 
 / {
 	led-colors {
-		compatible = "cros-ec,led-colors";
+		compatible = "cros-ec,led-policy";
 
 		power-state-charge-left {
 			charge-state = "PWR_STATE_CHARGE";
@@ -142,10 +142,9 @@
 			};
 		};
 
-		power-state-idle-forced-left {
-			charge-state = "PWR_STATE_IDLE";
+		power-state-forced-idle-left {
+			charge-state = "PWR_STATE_FORCED_IDLE";
 			charge-port = <1>; /* Left port */
-			extra-flag = "LED_CHFLAG_FORCE_IDLE";
 
 			/* Turn off the right LED */
 			color-0 {
@@ -162,10 +161,9 @@
 			};
 		};
 
-		power-state-idle-forced-right {
-			charge-state = "PWR_STATE_IDLE";
+		power-state-forced-idle-right {
+			charge-state = "PWR_STATE_FORCED_IDLE";
 			charge-port = <0>; /* Right port */
-			extra-flag = "LED_CHFLAG_FORCE_IDLE";
 
 			/* Turn off the left LED */
 			color-0 {
@@ -182,10 +180,9 @@
 			};
 		};
 
-		power-state-idle-default-left {
+		power-state-idle-left {
 			charge-state = "PWR_STATE_IDLE";
 			charge-port = <1>; /* Left port */
-			extra-flag = "LED_CHFLAG_DEFAULT";
 
 			/* Turn off the right LED */
 			color-0 {
@@ -197,10 +194,9 @@
 			};
 		};
 
-		power-state-idle-default-right {
+		power-state-idle-right {
 			charge-state = "PWR_STATE_IDLE";
 			charge-port = <0>; /* Right port */
-			extra-flag = "LED_CHFLAG_DEFAULT";
 
 			/* Turn off the left LED */
 			color-0 {
diff --git a/zephyr/test/drivers/led_driver/prj.conf b/zephyr/test/drivers/led_driver/prj.conf
index abdb8cc6a1..6ab9702320 100644
--- a/zephyr/test/drivers/led_driver/prj.conf
+++ b/zephyr/test/drivers/led_driver/prj.conf
@@ -1,4 +1,4 @@
-# Copyright 2022 The ChromiumOS Authors.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/test/drivers/led_driver/src/led.c b/zephyr/test/drivers/led_driver/src/led.c
index 5c0c9d0c01..7dfaa32bbb 100644
--- a/zephyr/test/drivers/led_driver/src/led.c
+++ b/zephyr/test/drivers/led_driver/src/led.c
@@ -1,14 +1,16 @@
-/* Copyright 2022 The ChromiumOS Authors.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <ztest.h>
+#include <zephyr/ztest.h>
 #include "ec_commands.h"
 #include "gpio.h"
+#include "include/power.h"
 #include "led.h"
 #include "led_common.h"
 #include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
 
 #define VERIFY_LED_COLOR(color, led_id)                                    \
 	{                                                                  \
@@ -27,6 +29,8 @@ ZTEST_SUITE(led_driver, drivers_predicate_post_main, NULL, NULL, NULL, NULL);
 
 ZTEST(led_driver, test_led_control)
 {
+	test_set_chipset_to_power_level(POWER_S5);
+
 	/* Exercise valid led_id, set to RESET state */
 	led_control(EC_LED_ID_SYSRQ_DEBUG_LED, LED_STATE_RESET);
 	VERIFY_LED_COLOR(LED_OFF, EC_LED_ID_SYSRQ_DEBUG_LED);
@@ -67,3 +71,23 @@ ZTEST(led_driver, test_led_brightness)
 	led_set_brightness(EC_LED_ID_SYSRQ_DEBUG_LED, brightness);
 	VERIFY_LED_COLOR(LED_WHITE, EC_LED_ID_SYSRQ_DEBUG_LED);
 }
+
+ZTEST(led_driver, test_get_chipset_state)
+{
+	enum power_state pwr_state;
+
+	test_set_chipset_to_g3();
+	pwr_state = get_chipset_state();
+	zassert_equal(pwr_state, POWER_S5, "expected=%d, returned=%d", POWER_S5,
+		      pwr_state);
+
+	test_set_chipset_to_s0();
+	pwr_state = get_chipset_state();
+	zassert_equal(pwr_state, POWER_S0, "expected=%d, returned=%d", POWER_S0,
+		      pwr_state);
+
+	test_set_chipset_to_power_level(POWER_S3);
+	pwr_state = get_chipset_state();
+	zassert_equal(pwr_state, POWER_S3, "expected=%d, returned=%d", POWER_S3,
+		      pwr_state);
+}
diff --git a/zephyr/test/drivers/mkbp/CMakeLists.txt b/zephyr/test/drivers/mkbp/CMakeLists.txt
new file mode 100644
index 0000000000..decd3ec0a7
--- /dev/null
+++ b/zephyr/test/drivers/mkbp/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Add source files
+target_sources(app PRIVATE src/mkbp_fifo.c)
diff --git a/zephyr/test/drivers/mkbp/src/mkbp_fifo.c b/zephyr/test/drivers/mkbp/src/mkbp_fifo.c
new file mode 100644
index 0000000000..e6a6ba5f04
--- /dev/null
+++ b/zephyr/test/drivers/mkbp/src/mkbp_fifo.c
@@ -0,0 +1,102 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/ztest.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest_assert.h>
+#include <zephyr/drivers/i2c_emul.h>
+
+#include "keyboard_config.h"
+#include "mkbp_fifo.h"
+#include "test/drivers/test_state.h"
+
+/* Tests for Matrix Keyboard Protocol (MKBP) */
+
+/* Largest event size that we support */
+#define KEY_MATRIX_EVENT_DATA_SIZE KEYBOARD_COLS_MAX
+
+#define MAX_EVENT_DATA_SIZE KEY_MATRIX_EVENT_DATA_SIZE
+
+struct mkbp_fifo_fixture {
+	uint8_t input_event_data[MAX_EVENT_DATA_SIZE];
+};
+
+static void *mkbp_fifo_setup(void)
+{
+	static struct mkbp_fifo_fixture fixture;
+
+	return &fixture;
+}
+
+static void mkbp_fifo_before(void *data)
+{
+	struct mkbp_fifo_fixture *fixture = data;
+
+	mkbp_clear_fifo();
+	memset(fixture->input_event_data, 0, MAX_EVENT_DATA_SIZE);
+	mkbp_fifo_depth_update(FIFO_DEPTH);
+}
+
+static void mkbp_fifo_after(void *data)
+{
+	mkbp_clear_fifo();
+	mkbp_fifo_depth_update(FIFO_DEPTH);
+}
+
+static void fill_array_with_incrementing_numbers(int8_t *dst, int size)
+{
+	for (int i = 0; i < size; i++) {
+		dst[i] = i;
+	}
+}
+
+ZTEST_F(mkbp_fifo, test_fifo_add_keyboard_key_matrix_event)
+{
+	uint8_t out[KEY_MATRIX_EVENT_DATA_SIZE + 1];
+
+	memset(out, 0, sizeof(out));
+
+	fill_array_with_incrementing_numbers(fixture->input_event_data,
+					     KEY_MATRIX_EVENT_DATA_SIZE);
+
+	/* Keyboard Key Matrix Event */
+	zassert_ok(mkbp_fifo_add(EC_MKBP_EVENT_KEY_MATRIX,
+				 fixture->input_event_data),
+		   NULL);
+
+	int dequeued_data_size =
+		mkbp_fifo_get_next_event(out, EC_MKBP_EVENT_KEY_MATRIX);
+
+	zassert_equal(dequeued_data_size, KEY_MATRIX_EVENT_DATA_SIZE, NULL);
+	zassert_mem_equal(fixture->input_event_data, out,
+			  KEY_MATRIX_EVENT_DATA_SIZE, NULL);
+	zassert_equal(out[KEY_MATRIX_EVENT_DATA_SIZE], 0, NULL);
+}
+
+ZTEST_F(mkbp_fifo, test_fifo_depth_update)
+{
+	uint8_t out[KEY_MATRIX_EVENT_DATA_SIZE + 1];
+	uint8_t new_depth = 0;
+
+	mkbp_fifo_depth_update(new_depth);
+	fill_array_with_incrementing_numbers(fixture->input_event_data,
+					     MAX_EVENT_DATA_SIZE);
+	zassert_equal(EC_ERROR_OVERFLOW,
+		      mkbp_fifo_add(EC_MKBP_EVENT_KEY_MATRIX,
+				    fixture->input_event_data),
+		      NULL);
+	zassert_equal(-1, /* get_next_event explicitly returns -1 */
+		      mkbp_fifo_get_next_event(out, EC_MKBP_EVENT_KEY_MATRIX),
+		      NULL);
+
+	mkbp_fifo_depth_update(FIFO_DEPTH);
+	zassert_ok(mkbp_fifo_add(EC_MKBP_EVENT_KEY_MATRIX,
+				 fixture->input_event_data),
+		   NULL);
+}
+
+ZTEST_SUITE(mkbp_fifo, drivers_predicate_post_main, mkbp_fifo_setup,
+	    mkbp_fifo_before, mkbp_fifo_after, NULL);
diff --git a/zephyr/test/drivers/prj.conf b/zephyr/test/drivers/prj.conf
index aadf8e44eb..a91d28906e 100644
--- a/zephyr/test/drivers/prj.conf
+++ b/zephyr/test/drivers/prj.conf
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -13,6 +13,8 @@ CONFIG_ZTEST_NEW_API=y
 CONFIG_ZTEST_PARAMETER_COUNT=24
 CONFIG_TEST=y
 CONFIG_ASSERT=y
+CONFIG_ASSERT_TEST=y
+CONFIG_SHELL_VT100_COMMANDS=n
 
 # Print logs from Zephyr LOG_MODULE to stdout
 CONFIG_NATIVE_UART_0_ON_STDINOUT=y
@@ -44,6 +46,7 @@ CONFIG_LOG=y
 CONFIG_I2C=y
 CONFIG_I2C_EMUL=y
 CONFIG_GPIO=y
+CONFIG_GPIO_GET_CONFIG=y
 CONFIG_GPIO_EMUL=y
 CONFIG_PLATFORM_EC_GPIO_INIT_PRIORITY=49
 CONFIG_EEPROM=y
@@ -59,9 +62,11 @@ CONFIG_EMUL_BMA255=y
 CONFIG_EMUL_BMI=y
 CONFIG_EMUL_TCS3400=y
 CONFIG_EMUL_BB_RETIMER=y
+CONFIG_EMUL_TCPCI=y
 CONFIG_EMUL_PS8XXX=y
+CONFIG_EMUL_RTC=y
 CONFIG_EMUL_TCPCI_PARTNER_DRP=y
-CONFIG_EMUL_TCPCI_PARTNER_FAULTY_SNK=y
+CONFIG_EMUL_TCPCI_PARTNER_FAULTY_EXT=y
 CONFIG_PLATFORM_EC_CHARGE_MANAGER=y
 CONFIG_PLATFORM_EC_CHARGE_RAMP_SW=y
 CONFIG_PLATFORM_EC_CHARGESPLASH=y
@@ -96,7 +101,6 @@ CONFIG_PLATFORM_EC_USB_PD_TCPM_TUSB422=y
 CONFIG_PLATFORM_EC_USB_MUX_VIRTUAL=y
 CONFIG_PLATFORM_EC_USBC_PPC_SN5S330=y
 CONFIG_PLATFORM_EC_CBI_EEPROM=y
-CONFIG_PLATFORM_EC_ADC=y
 CONFIG_PLATFORM_EC_TEMP_SENSOR=y
 CONFIG_PLATFORM_EC_TEMP_SENSOR_POWER=y
 CONFIG_PLATFORM_EC_THERMISTOR=y
@@ -118,6 +122,10 @@ CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8815=y
 CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8815_FORCE_DID=y
 CONFIG_PLATFORM_EC_USB_PD_TCPM_MULTI_PS8XXX=y
 CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y
+CONFIG_PLATFORM_EC_USB_PD_REQUIRE_AP_MODE_ENTRY=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_WAITMS=y
+CONFIG_PLATFORM_EC_POWER_SLEEP_FAILURE_DETECTION=y
+CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK=y
 
 CONFIG_ESPI=y
 CONFIG_ESPI_EMUL=y
@@ -144,12 +152,19 @@ CONFIG_PLATFORM_EC_POWERSEQ_HOST_SLEEP=y
 CONFIG_PLATFORM_EC_LID_SWITCH=y
 CONFIG_PLATFORM_EC_POWER_BUTTON=y
 CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI=y
+CONFIG_PLATFORM_EC_PORT80=y
+CONFIG_PLATFORM_EC_VSTORE_SLOT_COUNT=2
 
 CONFIG_WATCHDOG=y
 CONFIG_WDT_DISABLE_AT_BOOT=y
 CONFIG_PLATFORM_EC_USB_PD_HOST_CMD=y
 CONFIG_PLATFORM_EC_KEYBOARD=y
+CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_MKBP=y
+CONFIG_PLATFORM_EC_MKBP_EVENT=y
+CONFIG_PLATFORM_EC_MKBP_USE_GPIO=y
+CONFIG_PLATFORM_EC_MKBP_INPUT_DEVICES=y
 CONFIG_EMUL_KB_RAW=y
+CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI2=y
 CONFIG_EMUL_CROS_FLASH=y
 CONFIG_FLASH_SIMULATOR=y
 CONFIG_FLASH=y
@@ -164,3 +179,13 @@ CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=y
 
 CONFIG_PLATFORM_EC_ACCEL_SPOOF_MODE=y
 CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_SPOOF=y
+
+CONFIG_PLATFORM_EC_CONSOLE_CMD_MD=y
+
+CONFIG_PLATFORM_EC_LID_ANGLE=y
+CONFIG_PLATFORM_EC_TABLET_MODE=y
+
+# Power Management (Herobrine arch enables this)
+CONFIG_PM=y
+
+CONFIG_PWM_MOCK=y
diff --git a/zephyr/test/drivers/src/espi.c b/zephyr/test/drivers/src/espi.c
deleted file mode 100644
index 67fc3c6f90..0000000000
--- a/zephyr/test/drivers/src/espi.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <zephyr/zephyr.h>
-#include <ztest.h>
-
-#include "ec_commands.h"
-#include "host_command.h"
-#include "test/drivers/test_state.h"
-
-
-#define PORT 0
-
-ZTEST_USER(espi, test_host_command_get_protocol_info)
-{
-	struct ec_response_get_protocol_info response;
-	struct host_cmd_handler_args args =
-		BUILD_HOST_COMMAND_RESPONSE(EC_CMD_GET_PROTOCOL_INFO, 0,
-					    response);
-
-	zassert_ok(host_command_process(&args), NULL);
-	zassert_ok(args.result, NULL);
-	zassert_equal(args.response_size, sizeof(response), NULL);
-	zassert_equal(response.protocol_versions, BIT(3), NULL);
-	zassert_equal(response.max_request_packet_size, EC_LPC_HOST_PACKET_SIZE,
-		      NULL);
-	zassert_equal(response.max_response_packet_size,
-		      EC_LPC_HOST_PACKET_SIZE, NULL);
-	zassert_equal(response.flags, 0, NULL);
-}
-
-ZTEST_USER(espi, test_host_command_usb_pd_power_info)
-{
-	/* Only test we've enabled the command */
-	struct ec_response_usb_pd_power_info response;
-	struct ec_params_usb_pd_power_info params = { .port = PORT };
-	struct host_cmd_handler_args args = BUILD_HOST_COMMAND(
-		EC_CMD_USB_PD_POWER_INFO, 0, response, params);
-
-	args.params = &params;
-	zassert_ok(host_command_process(&args), NULL);
-	zassert_ok(args.result, NULL);
-	zassert_equal(args.response_size, sizeof(response), NULL);
-}
-
-ZTEST_USER(espi, test_host_command_typec_status)
-{
-	/* Only test we've enabled the command */
-	struct ec_params_typec_status params = { .port = PORT };
-	struct ec_response_typec_status response;
-	struct host_cmd_handler_args args =
-		BUILD_HOST_COMMAND(EC_CMD_TYPEC_STATUS, 0, response, params);
-
-	zassert_ok(host_command_process(&args), NULL);
-	zassert_ok(args.result, NULL);
-	zassert_equal(args.response_size, sizeof(response), NULL);
-}
-
-ZTEST_USER(espi, test_host_command_usb_pd_get_amode)
-{
-	/* Only test we've enabled the command */
-	struct ec_params_usb_pd_get_mode_request params = {
-		.port = PORT,
-		.svid_idx = 0,
-	};
-	struct ec_params_usb_pd_get_mode_response response;
-	struct host_cmd_handler_args args = BUILD_HOST_COMMAND(
-		EC_CMD_USB_PD_GET_AMODE, 0, response, params);
-
-	zassert_ok(host_command_process(&args), NULL);
-	zassert_ok(args.result, NULL);
-	/* Note: with no SVIDs the response size is the size of the svid field.
-	 * See the usb alt mode test for verifying larger struct sizes
-	 *
-	 * TODO(b/219562077): Add the above described test.
-	 */
-	zassert_equal(args.response_size, sizeof(response.svid), NULL);
-}
-
-ZTEST_SUITE(espi, drivers_predicate_post_main, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/drivers/src/i2c_passthru.c b/zephyr/test/drivers/src/i2c_passthru.c
deleted file mode 100644
index bab6a15b28..0000000000
--- a/zephyr/test/drivers/src/i2c_passthru.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <zephyr/zephyr.h>
-#include <ztest.h>
-
-#include "ec_commands.h"
-#include "host_command.h"
-#include "test/drivers/test_state.h"
-
-ZTEST_USER(i2c_passthru, test_read_without_write)
-{
-	uint8_t param_buf[sizeof(struct ec_params_i2c_passthru) +
-			  sizeof(struct ec_params_i2c_passthru_msg)];
-	uint8_t response_buf[sizeof(struct ec_response_i2c_passthru) + 2];
-	struct ec_params_i2c_passthru *params =
-		(struct ec_params_i2c_passthru *)&param_buf;
-	struct ec_response_i2c_passthru *response =
-		(struct ec_response_i2c_passthru *)&response_buf;
-	struct host_cmd_handler_args args =
-		BUILD_HOST_COMMAND_SIMPLE(EC_CMD_I2C_PASSTHRU, 0);
-
-	params->port = I2C_PORT_VIRTUAL_BATTERY;
-	params->num_msgs = 1;
-	params->msg[0].addr_flags = VIRTUAL_BATTERY_ADDR_FLAGS |
-				    EC_I2C_FLAG_READ;
-	params->msg[0].len = 1;
-	args.params = &param_buf;
-	args.params_size = sizeof(param_buf);
-	args.response = &response_buf;
-	args.response_max = sizeof(response_buf);
-
-	zassert_ok(host_command_process(&args), NULL);
-	zassert_ok(args.result, NULL);
-	zassert_equal(response->i2c_status, EC_I2C_STATUS_NAK, NULL);
-	zassert_equal(args.response_size,
-		      sizeof(struct ec_response_i2c_passthru), NULL);
-}
-
-ZTEST_SUITE(i2c_passthru, drivers_predicate_post_main, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c b/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c
deleted file mode 100644
index fadb595e4b..0000000000
--- a/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <stdint.h>
-#include <zephyr/zephyr.h>
-#include <ztest.h>
-#include <zephyr/drivers/gpio/gpio_emul.h>
-
-#include "ec_commands.h"
-#include "ec_tasks.h"
-#include "emul/emul_isl923x.h"
-#include "emul/tcpc/emul_ps8xxx.h"
-#include "emul/tcpc/emul_tcpci.h"
-#include "emul/tcpc/emul_tcpci_partner_snk.h"
-#include "host_command.h"
-#include "test/drivers/stubs.h"
-#include "tcpm/tcpci.h"
-#include "test/drivers/utils.h"
-#include "test/drivers/test_state.h"
-
-#define TEST_PORT USBC_PORT_C0
-
-struct usbc_alt_mode_fixture {
-	const struct emul *tcpci_emul;
-	const struct emul *charger_emul;
-	struct tcpci_partner_data partner;
-	struct tcpci_snk_emul_data snk_ext;
-};
-
-static void connect_partner_to_port(struct usbc_alt_mode_fixture *fixture)
-{
-	const struct emul *tcpc_emul = fixture->tcpci_emul;
-	struct tcpci_partner_data *partner_emul = &fixture->partner;
-
-	/* Set VBUS to vSafe0V initially. */
-	isl923x_emul_set_adc_vbus(fixture->charger_emul, 0);
-	tcpci_emul_set_reg(fixture->tcpci_emul, TCPC_REG_POWER_STATUS,
-			   TCPC_REG_POWER_STATUS_VBUS_DET);
-	tcpci_emul_set_reg(fixture->tcpci_emul, TCPC_REG_EXT_STATUS,
-			   TCPC_REG_EXT_STATUS_SAFE0V);
-	tcpci_tcpc_alert(0);
-	zassume_ok(tcpci_partner_connect_to_tcpci(partner_emul, tcpc_emul),
-		   NULL);
-
-	/* Wait for PD negotiation and current ramp. */
-	k_sleep(K_SECONDS(10));
-}
-
-static void disconnect_partner_from_port(struct usbc_alt_mode_fixture *fixture)
-{
-	zassume_ok(tcpci_emul_disconnect_partner(fixture->tcpci_emul), NULL);
-	isl923x_emul_set_adc_vbus(fixture->charger_emul, 0);
-	k_sleep(K_SECONDS(1));
-}
-
-static void *usbc_alt_mode_setup(void)
-{
-	static struct usbc_alt_mode_fixture fixture;
-	struct tcpci_partner_data *partner = &fixture.partner;
-	struct tcpci_snk_emul_data *snk_ext = &fixture.snk_ext;
-
-	tcpci_partner_init(partner, PD_REV20);
-	partner->extensions = tcpci_snk_emul_init(snk_ext, partner, NULL);
-
-	/* Get references for the emulators */
-	fixture.tcpci_emul =
-		emul_get_binding(DT_LABEL(DT_NODELABEL(tcpci_emul)));
-	/* The configured TCPCI rev must match the emulator's supported rev. */
-	tcpc_config[TEST_PORT].flags |= TCPC_FLAGS_TCPCI_REV2_0;
-	tcpci_emul_set_rev(fixture.tcpci_emul, TCPCI_EMUL_REV2_0_VER1_1);
-	fixture.charger_emul =
-		emul_get_binding(DT_LABEL(DT_NODELABEL(isl923x_emul)));
-
-	/* Set up SOP discovery responses for DP adapter. */
-	partner->identity_vdm[VDO_INDEX_HDR] =
-		VDO(USB_SID_PD, /* structured VDM */ true,
-		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_IDENT);
-	partner->identity_vdm[VDO_INDEX_IDH] = VDO_IDH(
-		/* USB host */ false, /* USB device */ false, IDH_PTYPE_AMA,
-		/* modal operation */ true, USB_VID_GOOGLE);
-	partner->identity_vdm[VDO_INDEX_CSTAT] = 0xabcdabcd;
-	partner->identity_vdm[VDO_INDEX_PRODUCT] = VDO_PRODUCT(0x1234, 0x5678);
-	/* Hardware version 1, firmware version 2 */
-	partner->identity_vdm[VDO_INDEX_AMA] = 0x12000000;
-	partner->identity_vdos = VDO_INDEX_AMA + 1;
-
-	/* Support DisplayPort VID. */
-	partner->svids_vdm[VDO_INDEX_HDR] =
-		VDO(USB_SID_PD, /* structured VDM */ true,
-		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_SVID);
-	partner->svids_vdm[VDO_INDEX_HDR + 1] =
-		VDO_SVID(USB_SID_DISPLAYPORT, 0);
-	partner->svids_vdos = VDO_INDEX_HDR + 2;
-
-	/* Support one mode for DisplayPort VID. Copied from Hoho. */
-	partner->modes_vdm[VDO_INDEX_HDR] =
-		VDO(USB_SID_DISPLAYPORT, /* structured VDM */ true,
-		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_MODES);
-	partner->modes_vdm[VDO_INDEX_HDR + 1] = VDO_MODE_DP(
-		0, MODE_DP_PIN_C, 1, CABLE_PLUG, MODE_DP_V13, MODE_DP_SNK);
-	partner->modes_vdos = VDO_INDEX_HDR + 2;
-
-	/* Sink 5V 3A. */
-	snk_ext->pdo[1] = PDO_FIXED(5000, 3000, PDO_FIXED_UNCONSTRAINED);
-
-	return &fixture;
-}
-
-static void usbc_alt_mode_before(void *data)
-{
-	/* Set chipset to ON, this will set TCPM to DRP */
-	test_set_chipset_to_s0();
-
-	/* TODO(b/214401892): Check why need to give time TCPM to spin */
-	k_sleep(K_SECONDS(1));
-
-	connect_partner_to_port((struct usbc_alt_mode_fixture *)data);
-}
-
-static void usbc_alt_mode_after(void *data)
-{
-	disconnect_partner_from_port((struct usbc_alt_mode_fixture *)data);
-}
-
-ZTEST_F(usbc_alt_mode, verify_discovery)
-{
-	uint8_t response_buffer[EC_LPC_HOST_PACKET_SIZE];
-	struct ec_response_typec_discovery *discovery =
-		(struct ec_response_typec_discovery *)response_buffer;
-	host_cmd_typec_discovery(TEST_PORT, TYPEC_PARTNER_SOP,
-			response_buffer, sizeof(response_buffer));
-
-	/* The host command does not count the VDM header in identity_count. */
-	zassert_equal(discovery->identity_count,
-		      this->partner.identity_vdos - 1,
-		      "Expected %d identity VDOs, got %d",
-		      this->partner.identity_vdos - 1,
-		      discovery->identity_count);
-	zassert_mem_equal(discovery->discovery_vdo,
-			  this->partner.identity_vdm + 1,
-			  discovery->identity_count *
-				  sizeof(*discovery->discovery_vdo),
-			  "Discovered SOP identity ACK did not match");
-	zassert_equal(discovery->svid_count, 1, "Expected 1 SVID, got %d",
-		      discovery->svid_count);
-	zassert_equal(discovery->svids[0].svid, USB_SID_DISPLAYPORT,
-		      "Expected SVID 0x%0000x, got 0x%0000x",
-		      USB_SID_DISPLAYPORT, discovery->svids[0].svid);
-	zassert_equal(discovery->svids[0].mode_count, 1,
-		      "Expected 1 DP mode, got %d",
-		      discovery->svids[0].mode_count);
-	zassert_equal(discovery->svids[0].mode_vdo[0],
-		      this->partner.modes_vdm[1],
-		      "DP mode VDOs did not match");
-}
-
-ZTEST_SUITE(usbc_alt_mode, drivers_predicate_post_main, usbc_alt_mode_setup,
-	    usbc_alt_mode_before, usbc_alt_mode_after, NULL);
diff --git a/zephyr/test/drivers/src/integration/usbc/usb_malfunction_sink.c b/zephyr/test/drivers/src/integration/usbc/usb_malfunction_sink.c
deleted file mode 100644
index c3788791e2..0000000000
--- a/zephyr/test/drivers/src/integration/usbc/usb_malfunction_sink.c
+++ /dev/null
@@ -1,259 +0,0 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <stdint.h>
-#include <zephyr/sys/byteorder.h>
-#include <ztest.h>
-
-#include "battery_smart.h"
-#include "emul/emul_isl923x.h"
-#include "emul/emul_smart_battery.h"
-#include "emul/tcpc/emul_tcpci_partner_faulty_snk.h"
-#include "emul/tcpc/emul_tcpci_partner_snk.h"
-#include "tcpm/tcpci.h"
-#include "test/drivers/test_state.h"
-#include "test/drivers/utils.h"
-#include "usb_pd.h"
-
-struct usb_malfunction_sink_fixture {
-	struct tcpci_partner_data sink;
-	struct tcpci_faulty_snk_emul_data faulty_snk_ext;
-	struct tcpci_snk_emul_data snk_ext;
-	const struct emul *tcpci_emul;
-	const struct emul *charger_emul;
-	struct tcpci_faulty_snk_action actions[2];
-};
-
-static void
-connect_sink_to_port(struct usb_malfunction_sink_fixture *fixture)
-{
-	/*
-	 * TODO(b/221439302) Updating the TCPCI emulator registers, updating the
-	 *   vbus, as well as alerting should all be a part of the connect
-	 *   function.
-	 */
-	isl923x_emul_set_adc_vbus(fixture->charger_emul, 0);
-	tcpci_emul_set_reg(fixture->tcpci_emul, TCPC_REG_POWER_STATUS,
-			   TCPC_REG_POWER_STATUS_VBUS_DET);
-	tcpci_emul_set_reg(fixture->tcpci_emul, TCPC_REG_EXT_STATUS,
-			   TCPC_REG_EXT_STATUS_SAFE0V);
-	tcpci_tcpc_alert(0);
-	/*
-	 * TODO(b/226567798) Wait for TCPC init and DRPToggle. It is required,
-	 *   because tcpci_emul_reset_rule_before reset registers including
-	 *   Looking4Connection bit in CC_STATUS register.
-	 */
-	k_sleep(K_SECONDS(1));
-	zassume_ok(tcpci_partner_connect_to_tcpci(&fixture->sink,
-						  fixture->tcpci_emul),
-		   NULL);
-
-	/* Wait for PD negotiation and current ramp.
-	 * TODO(b/213906889): Check message timing and contents.
-	 */
-	k_sleep(K_SECONDS(10));
-}
-
-static inline void disconnect_sink_from_port(
-	struct usb_malfunction_sink_fixture *fixture)
-{
-	zassume_ok(tcpci_emul_disconnect_partner(fixture->tcpci_emul), NULL);
-	k_sleep(K_SECONDS(1));
-}
-
-static void *usb_malfunction_sink_setup(void)
-{
-	static struct usb_malfunction_sink_fixture test_fixture;
-
-	/* Get references for the emulators */
-	test_fixture.tcpci_emul =
-		emul_get_binding(DT_LABEL(DT_NODELABEL(tcpci_emul)));
-	test_fixture.charger_emul =
-		emul_get_binding(DT_LABEL(DT_NODELABEL(isl923x_emul)));
-	tcpci_emul_set_rev(test_fixture.tcpci_emul, TCPCI_EMUL_REV2_0_VER1_1);
-	tcpc_config[0].flags = tcpc_config[0].flags |
-			       TCPC_FLAGS_TCPCI_REV2_0;
-
-	/* Initialized the sink to request 5V and 3A */
-	tcpci_partner_init(&test_fixture.sink, PD_REV20);
-	test_fixture.sink.extensions =
-		tcpci_faulty_snk_emul_init(
-			&test_fixture.faulty_snk_ext, &test_fixture.sink,
-			tcpci_snk_emul_init(&test_fixture.snk_ext,
-					    &test_fixture.sink, NULL));
-	test_fixture.snk_ext.pdo[1] =
-		PDO_FIXED(5000, 3000, PDO_FIXED_UNCONSTRAINED);
-
-	return &test_fixture;
-}
-
-static void usb_malfunction_sink_before(void *data)
-{
-	/* Set chipset to ON, this will set TCPM to DRP */
-	test_set_chipset_to_s0();
-
-	/* TODO(b/214401892): Check why need to give time TCPM to spin */
-	k_sleep(K_SECONDS(1));
-
-}
-
-static void usb_malfunction_sink_after(void *data)
-{
-	struct usb_malfunction_sink_fixture *fixture = data;
-
-	tcpci_faulty_snk_emul_clear_actions_list(&fixture->faulty_snk_ext);
-	disconnect_sink_from_port(fixture);
-	tcpci_partner_common_clear_logged_msgs(&fixture->sink);
-}
-
-ZTEST_SUITE(usb_malfunction_sink, drivers_predicate_post_main,
-	    usb_malfunction_sink_setup,
-	    usb_malfunction_sink_before,
-	    usb_malfunction_sink_after, NULL);
-
-ZTEST_F(usb_malfunction_sink, test_fail_source_cap_and_pd_disable)
-{
-	struct ec_response_typec_status typec_status;
-
-	/*
-	 * Fail on SourceCapabilities message to make TCPM change PD port state
-	 * to disabled
-	 */
-	this->actions[0].action_mask = TCPCI_FAULTY_SNK_FAIL_SRC_CAP;
-	this->actions[0].count = TCPCI_FAULTY_SNK_INFINITE_ACTION;
-	tcpci_faulty_snk_emul_append_action(&this->faulty_snk_ext,
-					    &this->actions[0]);
-
-	connect_sink_to_port(this);
-
-	typec_status = host_cmd_typec_status(0);
-
-	/* Device is connected, but PD wasn't able to establish contract */
-	zassert_true(typec_status.pd_enabled, NULL);
-	zassert_true(typec_status.dev_connected, NULL);
-	zassert_false(typec_status.sop_connected, NULL);
-}
-
-ZTEST_F(usb_malfunction_sink, test_fail_source_cap_and_pd_connect)
-{
-	struct ec_response_usb_pd_power_info info;
-	struct ec_response_typec_status typec_status;
-
-	/*
-	 * Fail only few times on SourceCapabilities message to prevent entering
-	 * PE_SRC_Disabled state by TCPM
-	 */
-	this->actions[0].action_mask = TCPCI_FAULTY_SNK_FAIL_SRC_CAP;
-	this->actions[0].count = 3;
-	tcpci_faulty_snk_emul_append_action(&this->faulty_snk_ext,
-					    &this->actions[0]);
-
-	connect_sink_to_port(this);
-
-	typec_status = host_cmd_typec_status(0);
-
-	zassert_true(typec_status.pd_enabled, NULL);
-	zassert_true(typec_status.dev_connected, NULL);
-	zassert_true(typec_status.sop_connected, NULL);
-
-	info = host_cmd_power_info(0);
-
-	zassert_equal(info.role, USB_PD_PORT_POWER_SOURCE,
-		      "Expected role to be %d, but got %d",
-		      USB_PD_PORT_POWER_SOURCE, info.role);
-	zassert_equal(info.type, USB_CHG_TYPE_NONE,
-		      "Expected type to be %d, but got %d", USB_CHG_TYPE_NONE,
-		      info.type);
-	zassert_equal(info.meas.voltage_max, 0,
-		      "Expected charge voltage max of 0mV, but got %dmV",
-		      info.meas.voltage_max);
-	zassert_within(
-		info.meas.voltage_now, 5000, 500,
-		"Charging voltage expected to be near 5000mV, but was %dmV",
-		info.meas.voltage_now);
-	zassert_equal(info.meas.current_max, 1500,
-		      "Current max expected to be 1500mV, but was %dmV",
-		      info.meas.current_max);
-	zassert_equal(info.meas.current_lim, 0,
-		     "VBUS max is set to 0mA, but PD is reporting %dmA",
-		     info.meas.current_lim);
-	zassert_equal(info.max_power, 0,
-		      "Charging expected to be at %duW, but PD max is %duW",
-		      0, info.max_power);
-}
-
-ZTEST_F(usb_malfunction_sink, test_ignore_source_cap)
-{
-	struct tcpci_partner_log_msg *msg;
-	uint16_t header;
-	bool expect_hard_reset = false;
-	int msg_cnt = 0;
-
-	this->actions[0].action_mask = TCPCI_FAULTY_SNK_IGNORE_SRC_CAP;
-	this->actions[0].count = TCPCI_FAULTY_SNK_INFINITE_ACTION;
-	tcpci_faulty_snk_emul_append_action(&this->faulty_snk_ext,
-					    &this->actions[0]);
-
-	tcpci_partner_common_enable_pd_logging(&this->sink, true);
-	connect_sink_to_port(this);
-	tcpci_partner_common_enable_pd_logging(&this->sink, false);
-
-	/*
-	 * If test is failing, printing logged message may be useful to diagnose
-	 * problem:
-	 * tcpci_partner_common_print_logged_msgs(&this->sink);
-	 */
-
-	/* Check if SourceCapability message alternate with HardReset */
-	SYS_SLIST_FOR_EACH_CONTAINER(&this->sink.msg_log, msg, node) {
-		if (expect_hard_reset) {
-			zassert_equal(msg->sop, TCPCI_MSG_TX_HARD_RESET,
-				      "Expected message %d to be hard reset",
-				      msg_cnt);
-		} else {
-			header = sys_get_le16(msg->buf);
-			zassert_equal(msg->sop, TCPCI_MSG_SOP,
-				      "Expected message %d to be SOP message, not 0x%x",
-				      msg_cnt, msg->sop);
-			zassert_not_equal(PD_HEADER_CNT(header), 0,
-					  "Expected message %d to has at least one data object",
-					  msg_cnt);
-			zassert_equal(PD_HEADER_TYPE(header),
-				      PD_DATA_SOURCE_CAP,
-				      "Expected message %d to be SourceCapabilities, not 0x%x",
-				      msg_cnt, PD_HEADER_TYPE(header));
-		}
-
-		msg_cnt++;
-		expect_hard_reset = !expect_hard_reset;
-	}
-}
-
-ZTEST_F(usb_malfunction_sink, test_ignore_source_cap_and_pd_disable)
-{
-	struct ec_response_typec_status typec_status;
-
-	/*
-	 * Ignore first SourceCapabilities message and discard others by sending
-	 * different messages. This will lead to PD disable.
-	 */
-	this->actions[0].action_mask = TCPCI_FAULTY_SNK_IGNORE_SRC_CAP;
-	this->actions[0].count = 1;
-	tcpci_faulty_snk_emul_append_action(&this->faulty_snk_ext,
-					    &this->actions[0]);
-	this->actions[1].action_mask = TCPCI_FAULTY_SNK_DISCARD_SRC_CAP;
-	this->actions[1].count = TCPCI_FAULTY_SNK_INFINITE_ACTION;
-	tcpci_faulty_snk_emul_append_action(&this->faulty_snk_ext,
-					    &this->actions[1]);
-
-	connect_sink_to_port(this);
-
-	typec_status = host_cmd_typec_status(0);
-
-	/* Device is connected, but PD wasn't able to establish contract */
-	zassert_true(typec_status.pd_enabled, NULL);
-	zassert_true(typec_status.dev_connected, NULL);
-	zassert_false(typec_status.sop_connected, NULL);
-}
diff --git a/zephyr/test/drivers/src/keyboard_scan.c b/zephyr/test/drivers/src/keyboard_scan.c
deleted file mode 100644
index 209c5320e0..0000000000
--- a/zephyr/test/drivers/src/keyboard_scan.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#include <ztest.h>
-#include <zephyr/drivers/emul.h>
-#include <zephyr/drivers/gpio.h>
-#include <zephyr/drivers/gpio/gpio_emul.h>
-#include <emul/emul_kb_raw.h>
-
-#include "test/drivers/test_state.h"
-
-int emulate_keystate(int row, int col, int pressed)
-{
-	const struct device *dev =
-		DEVICE_DT_GET(DT_NODELABEL(cros_kb_raw));
-
-	return emul_kb_raw_set_kbstate(dev, row, col, pressed);
-}
-
-ZTEST(keyboard_scan, test_press_enter)
-{
-	zassert_ok(emulate_keystate(4, 11, true), NULL);
-	k_sleep(K_MSEC(100));
-	/* TODO(jbettis): Check espi_emul to verify the AP was notified. */
-	zassert_ok(emulate_keystate(4, 11, false), NULL);
-	k_sleep(K_MSEC(100));
-}
-ZTEST_SUITE(keyboard_scan, drivers_predicate_post_main, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/drivers/src/main.c b/zephyr/test/drivers/src/main.c
deleted file mode 100644
index 319d42e3ad..0000000000
--- a/zephyr/test/drivers/src/main.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <zephyr/zephyr.h>
-#include <ztest.h>
-#include "ec_app_main.h"
-#include "test/drivers/test_state.h"
-
-bool drivers_predicate_pre_main(const void *state)
-{
-	return ((struct test_state *)state)->ec_app_main_run == false;
-}
-
-bool drivers_predicate_post_main(const void *state)
-{
-	return !drivers_predicate_pre_main(state);
-}
-
-void test_main(void)
-{
-	struct test_state state = {
-		.ec_app_main_run = false,
-	};
-
-	/* Run all the suites that depend on main not being called yet */
-	ztest_run_test_suites(&state);
-
-	ec_app_main();
-	state.ec_app_main_run = true;
-
-	/* Run all the suites that depend on main being called */
-	ztest_run_test_suites(&state);
-
-	/* Check that every suite ran */
-	ztest_verify_all_test_suites_ran();
-}
diff --git a/zephyr/test/drivers/src/test_rules.c b/zephyr/test/drivers/src/test_rules.c
deleted file mode 100644
index 0266fa3cdf..0000000000
--- a/zephyr/test/drivers/src/test_rules.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <ztest.h>
-
-#include "motion_sense_fifo.h"
-
-static void motion_sense_fifo_reset_before(const struct ztest_unit_test *test,
-					    void *data)
-{
-	ARG_UNUSED(test);
-	ARG_UNUSED(data);
-	motion_sense_fifo_reset();
-}
-ZTEST_RULE(motion_sense_fifo_reset, motion_sense_fifo_reset_before, NULL);
diff --git a/zephyr/test/drivers/src/vboot_hash.c b/zephyr/test/drivers/src/vboot_hash.c
deleted file mode 100644
index ac23b95b02..0000000000
--- a/zephyr/test/drivers/src/vboot_hash.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <zephyr/zephyr.h>
-#include <ztest.h>
-#include <sha256.h>
-
-#include "ec_commands.h"
-#include "host_command.h"
-#include "test/drivers/test_state.h"
-
-ZTEST_USER(vboot_hash, test_hostcmd)
-{
-	struct ec_params_vboot_hash params = {
-		.cmd = EC_VBOOT_HASH_START,
-		.offset = 0,
-		.size = 0,
-	};
-	struct ec_response_vboot_hash response;
-	struct host_cmd_handler_args args =
-		BUILD_HOST_COMMAND(EC_CMD_VBOOT_HASH, 0, response, params);
-
-	zassert_ok(host_command_process(&args), NULL);
-	zassert_ok(args.result, NULL);
-	zassert_equal(args.response_size, sizeof(response), NULL);
-	zassert_equal(response.status, EC_VBOOT_HASH_STATUS_BUSY,
-		      "response.status = %d", response.status);
-}
-
-ZTEST_SUITE(vboot_hash, drivers_predicate_post_main, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/drivers/testcase.yaml b/zephyr/test/drivers/testcase.yaml
new file mode 100644
index 0000000000..3708529ed3
--- /dev/null
+++ b/zephyr/test/drivers/testcase.yaml
@@ -0,0 +1,80 @@
+common:
+  platform_allow: native_posix
+tests:
+  drivers.default:
+    timeout: 240
+    extra_args: CONF_FILE="prj.conf;default/prj.conf"
+    extra_configs:
+      - CONFIG_LINK_TEST_SUITE_DEFAULT=y
+      - CONFIG_LINK_TEST_SUITE_USB_MALFUNCTION_SINK=y
+      - CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y
+      - CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y
+  drivers.default.mock_power:
+    timeout: 240
+    extra_args: CONF_FILE="prj.conf;default/prj.conf"
+    extra_configs:
+      - CONFIG_LINK_TEST_SUITE_DEFAULT=y
+      - CONFIG_LINK_TEST_SUITE_USB_MALFUNCTION_SINK=y
+      - CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y
+      - CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y
+      - CONFIG_POWER_SEQUENCE_MOCK=y
+  drivers.host_cmd:
+    extra_configs:
+      - CONFIG_LINK_TEST_SUITE_HOST_COMMANDS=y
+      - CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y
+      - CONFIG_PLATFORM_EC_USB_PD_LOGGING=y
+  drivers.ap_mux_control:
+    extra_args: CONF_FILE="prj.conf;ap_mux_control/prj.conf"
+    extra_configs:
+      - CONFIG_LINK_TEST_SUITE_AP_MUX_CONTROL=y
+  drivers.chargesplash:
+    timeout: 240
+    extra_configs:
+      - CONFIG_LINK_TEST_SUITE_CHARGESPLASH=y
+  drivers.chargesplash.mock_power:
+    timeout: 240
+    extra_configs:
+      - CONFIG_LINK_TEST_SUITE_CHARGESPLASH=y
+      - CONFIG_POWER_SEQUENCE_MOCK=y
+  drivers.dps:
+    extra_args: CONF_FILE="prj.conf;dps/prj.conf"
+    extra_configs:
+      - CONFIG_LINK_TEST_SUITE_USB_PD_DPS=y
+  drivers.isl923x:
+    extra_configs:
+      - CONFIG_LINK_TEST_SUITE_ISL923X=y
+  drivers.isl923x.mock_power:
+    extra_configs:
+      - CONFIG_LINK_TEST_SUITE_ISL923X=y
+      - CONFIG_POWER_SEQUENCE_MOCK=y
+  drivers.keyboard_scan:
+    extra_configs:
+      - CONFIG_LINK_TEST_SUITE_KEYBOARD_SCAN=y
+  drivers.led_driver:
+    extra_args: CONF_FILE="prj.conf;led_driver/prj.conf" DTC_OVERLAY_FILE="./boards/native_posix.overlay;./led_driver/led_pins.dts;./led_driver/led_policy.dts"
+    extra_configs:
+      - CONFIG_LINK_TEST_SUITE_LED_DRIVER=y
+  drivers.mkbp:
+    extra_configs:
+      - CONFIG_LINK_TEST_SUITE_MKBP=y
+      - CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_MKBP=y
+      - CONFIG_PLATFORM_EC_MKBP_INPUT_DEVICES=y
+      - CONFIG_PLATFORM_EC_MKBP_EVENT=y
+      - CONFIG_PLATFORM_EC_MKBP_USE_GPIO=y
+  drivers.usb_retimer_fw_update:
+    extra_args: CONF_FILE="prj.conf;usb_retimer_fw_update/prj.conf"
+    extra_configs:
+      - CONFIG_LINK_TEST_SUITE_USB_RETIMER_FW_UPDATE=y
+  drivers.usbc_alt_mode:
+    extra_configs:
+      - CONFIG_LINK_TEST_SUITE_USBC_ALT_MODE=y
+  drivers.usbc_alt_mode_ec_entry:
+   extra_configs:
+     - CONFIG_PLATFORM_EC_USB_PD_REQUIRE_AP_MODE_ENTRY=n
+     - CONFIG_LINK_TEST_SUITE_USBC_ALT_MODE=y
+  drivers.usbc_tbt_mode:
+    extra_configs:
+      - CONFIG_LINK_TEST_SUITE_USBC_TBT_MODE=y
+  drivers.usbc_ocp:
+    extra_configs:
+      - CONFIG_LINK_TEST_SUITE_USBC_OCP=y
diff --git a/zephyr/test/drivers/usb_malfunction_sink/CMakeLists.txt b/zephyr/test/drivers/usb_malfunction_sink/CMakeLists.txt
new file mode 100644
index 0000000000..2e247726f0
--- /dev/null
+++ b/zephyr/test/drivers/usb_malfunction_sink/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Add source files
+target_sources(app PRIVATE src/usb_malfunction_sink.c)
diff --git a/zephyr/test/drivers/usb_malfunction_sink/src/usb_malfunction_sink.c b/zephyr/test/drivers/usb_malfunction_sink/src/usb_malfunction_sink.c
new file mode 100644
index 0000000000..38ce979594
--- /dev/null
+++ b/zephyr/test/drivers/usb_malfunction_sink/src/usb_malfunction_sink.c
@@ -0,0 +1,269 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <stdint.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/ztest.h>
+
+#include "battery_smart.h"
+#include "emul/emul_isl923x.h"
+#include "emul/emul_smart_battery.h"
+#include "emul/tcpc/emul_tcpci_partner_faulty_ext.h"
+#include "emul/tcpc/emul_tcpci_partner_snk.h"
+#include "tcpm/tcpci.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "test/drivers/stubs.h"
+#include "usb_pd.h"
+#include "usb_tc_sm.h"
+#include "timer.h"
+
+/* USB-C port used to connect port partner in this testsuite */
+#define TEST_PORT 0
+BUILD_ASSERT(TEST_PORT == USBC_PORT_C0);
+
+struct usb_malfunction_sink_fixture {
+	struct tcpci_partner_data sink;
+	struct tcpci_faulty_ext_data faulty_snk_ext;
+	struct tcpci_snk_emul_data snk_ext;
+	const struct emul *tcpci_emul;
+	const struct emul *charger_emul;
+	struct tcpci_faulty_ext_action actions[2];
+	enum usbc_port port;
+};
+
+static void *usb_malfunction_sink_setup(void)
+{
+	static struct usb_malfunction_sink_fixture test_fixture;
+
+	test_fixture.port = TEST_PORT;
+
+	/* Get references for the emulators */
+	test_fixture.tcpci_emul = EMUL_GET_USBC_BINDING(TEST_PORT, tcpc);
+	test_fixture.charger_emul = EMUL_GET_USBC_BINDING(TEST_PORT, chg);
+
+	/* Initialized the sink to request 5V and 3A */
+	tcpci_partner_init(&test_fixture.sink, PD_REV20);
+	test_fixture.sink.extensions = tcpci_faulty_ext_init(
+		&test_fixture.faulty_snk_ext, &test_fixture.sink,
+		tcpci_snk_emul_init(&test_fixture.snk_ext, &test_fixture.sink,
+				    NULL));
+	test_fixture.snk_ext.pdo[1] =
+		PDO_FIXED(5000, 3000, PDO_FIXED_UNCONSTRAINED);
+
+	return &test_fixture;
+}
+
+static void usb_malfunction_sink_before(void *data)
+{
+	/* Set chipset to ON, this will set TCPM to DRP */
+	test_set_chipset_to_s0();
+
+	/* TODO(b/214401892): Check why need to give time TCPM to spin */
+	k_sleep(K_SECONDS(1));
+}
+
+static void usb_malfunction_sink_after(void *data)
+{
+	struct usb_malfunction_sink_fixture *fixture = data;
+
+	tcpci_faulty_ext_clear_actions_list(&fixture->faulty_snk_ext);
+	disconnect_sink_from_port(fixture->tcpci_emul);
+	tcpci_partner_common_clear_logged_msgs(&fixture->sink);
+}
+
+ZTEST_SUITE(usb_malfunction_sink, drivers_predicate_post_main,
+	    usb_malfunction_sink_setup, usb_malfunction_sink_before,
+	    usb_malfunction_sink_after, NULL);
+
+ZTEST_F(usb_malfunction_sink, test_fail_source_cap_and_pd_disable)
+{
+	struct ec_response_typec_status typec_status;
+
+	/*
+	 * Fail on SourceCapabilities message to make TCPM change PD port state
+	 * to disabled
+	 */
+	fixture->actions[0].action_mask = TCPCI_FAULTY_EXT_FAIL_SRC_CAP;
+	fixture->actions[0].count = TCPCI_FAULTY_EXT_INFINITE_ACTION;
+	tcpci_faulty_ext_append_action(&fixture->faulty_snk_ext,
+				       &fixture->actions[0]);
+
+	connect_sink_to_port(&fixture->sink, fixture->tcpci_emul,
+			     fixture->charger_emul);
+
+	typec_status = host_cmd_typec_status(0);
+
+	/* Device is connected, but PD wasn't able to establish contract */
+	zassert_true(typec_status.pd_enabled, NULL);
+	zassert_true(typec_status.dev_connected, NULL);
+	zassert_false(typec_status.sop_connected, NULL);
+}
+
+ZTEST_F(usb_malfunction_sink, test_fail_source_cap_and_pd_connect)
+{
+	struct ec_response_usb_pd_power_info info;
+	struct ec_response_typec_status typec_status;
+
+	/*
+	 * Fail only few times on SourceCapabilities message to prevent entering
+	 * PE_SRC_Disabled state by TCPM
+	 */
+	fixture->actions[0].action_mask = TCPCI_FAULTY_EXT_FAIL_SRC_CAP;
+	fixture->actions[0].count = 3;
+	tcpci_faulty_ext_append_action(&fixture->faulty_snk_ext,
+				       &fixture->actions[0]);
+
+	connect_sink_to_port(&fixture->sink, fixture->tcpci_emul,
+			     fixture->charger_emul);
+
+	typec_status = host_cmd_typec_status(0);
+
+	zassert_true(typec_status.pd_enabled, NULL);
+	zassert_true(typec_status.dev_connected, NULL);
+	zassert_true(typec_status.sop_connected, NULL);
+
+	info = host_cmd_power_info(0);
+
+	zassert_equal(info.role, USB_PD_PORT_POWER_SOURCE,
+		      "Expected role to be %d, but got %d",
+		      USB_PD_PORT_POWER_SOURCE, info.role);
+	zassert_equal(info.type, USB_CHG_TYPE_NONE,
+		      "Expected type to be %d, but got %d", USB_CHG_TYPE_NONE,
+		      info.type);
+	zassert_equal(info.meas.voltage_max, 0,
+		      "Expected charge voltage max of 0mV, but got %dmV",
+		      info.meas.voltage_max);
+	zassert_within(
+		info.meas.voltage_now, 5000, 500,
+		"Charging voltage expected to be near 5000mV, but was %dmV",
+		info.meas.voltage_now);
+	zassert_equal(info.meas.current_max, 1500,
+		      "Current max expected to be 1500mV, but was %dmV",
+		      info.meas.current_max);
+	zassert_equal(info.meas.current_lim, 0,
+		      "VBUS max is set to 0mA, but PD is reporting %dmA",
+		      info.meas.current_lim);
+	zassert_equal(info.max_power, 0,
+		      "Charging expected to be at %duW, but PD max is %duW", 0,
+		      info.max_power);
+}
+
+ZTEST_F(usb_malfunction_sink, test_ignore_source_cap)
+{
+	struct tcpci_partner_log_msg *msg;
+	uint16_t header;
+	bool expect_hard_reset = false;
+	int msg_cnt = 0;
+
+	fixture->actions[0].action_mask = TCPCI_FAULTY_EXT_IGNORE_SRC_CAP;
+	fixture->actions[0].count = TCPCI_FAULTY_EXT_INFINITE_ACTION;
+	tcpci_faulty_ext_append_action(&fixture->faulty_snk_ext,
+				       &fixture->actions[0]);
+
+	tcpci_partner_common_enable_pd_logging(&fixture->sink, true);
+	connect_sink_to_port(&fixture->sink, fixture->tcpci_emul,
+			     fixture->charger_emul);
+	tcpci_partner_common_enable_pd_logging(&fixture->sink, false);
+
+	/*
+	 * If test is failing, printing logged message may be useful to diagnose
+	 * problem:
+	 * tcpci_partner_common_print_logged_msgs(&fixture->sink);
+	 */
+
+	/* Check if SourceCapability message alternate with HardReset */
+	SYS_SLIST_FOR_EACH_CONTAINER(&fixture->sink.msg_log, msg, node)
+	{
+		if (expect_hard_reset) {
+			zassert_equal(msg->sop, TCPCI_MSG_TX_HARD_RESET,
+				      "Expected message %d to be hard reset",
+				      msg_cnt);
+		} else {
+			header = sys_get_le16(msg->buf);
+			zassert_equal(
+				msg->sop, TCPCI_MSG_SOP,
+				"Expected message %d to be SOP message, not 0x%x",
+				msg_cnt, msg->sop);
+			zassert_not_equal(
+				PD_HEADER_CNT(header), 0,
+				"Expected message %d to has at least one data object",
+				msg_cnt);
+			zassert_equal(
+				PD_HEADER_TYPE(header), PD_DATA_SOURCE_CAP,
+				"Expected message %d to be SourceCapabilities, not 0x%x",
+				msg_cnt, PD_HEADER_TYPE(header));
+		}
+
+		msg_cnt++;
+		expect_hard_reset = !expect_hard_reset;
+	}
+}
+
+ZTEST_F(usb_malfunction_sink, test_hard_reset_disconnect)
+{
+	struct ec_response_typec_status typec_status;
+	int try_count;
+
+	/*
+	 * Test if disconnection during the power sequence doesn't have impact
+	 * on next tries
+	 */
+	for (try_count = 1; try_count < 5; try_count++) {
+		/* Connect port partner and check Vconn state */
+		connect_sink_to_port(&fixture->sink, fixture->tcpci_emul,
+				     fixture->charger_emul);
+		typec_status = host_cmd_typec_status(fixture->port);
+		zassert_equal(typec_status.vconn_role, PD_ROLE_VCONN_SRC,
+			      "Vconn should be present after connection (%d)",
+			      try_count);
+
+		/* Send hard reset to trigger power sequence on source side */
+		tcpci_partner_common_send_hard_reset(&fixture->sink);
+
+		/*
+		 * Wait for start of power sequence after hard reset and half
+		 * the time of source recovery (first step of power sequence
+		 * when vconn should be disabled)
+		 */
+		k_sleep(K_USEC(PD_T_PS_HARD_RESET + PD_T_SRC_RECOVER / 2));
+
+		typec_status = host_cmd_typec_status(fixture->port);
+		zassert_equal(typec_status.vconn_role, PD_ROLE_VCONN_OFF,
+			      "Vconn should be disabled at power sequence (%d)",
+			      try_count);
+
+		/* Disconnect partner at the middle of power sequence */
+		disconnect_sink_from_port(fixture->tcpci_emul);
+	}
+}
+
+ZTEST_F(usb_malfunction_sink, test_ignore_source_cap_and_pd_disable)
+{
+	struct ec_response_typec_status typec_status;
+
+	/*
+	 * Ignore first SourceCapabilities message and discard others by sending
+	 * different messages. This will lead to PD disable.
+	 */
+	fixture->actions[0].action_mask = TCPCI_FAULTY_EXT_IGNORE_SRC_CAP;
+	fixture->actions[0].count = 1;
+	tcpci_faulty_ext_append_action(&fixture->faulty_snk_ext,
+				       &fixture->actions[0]);
+	fixture->actions[1].action_mask = TCPCI_FAULTY_EXT_DISCARD_SRC_CAP;
+	fixture->actions[1].count = TCPCI_FAULTY_EXT_INFINITE_ACTION;
+	tcpci_faulty_ext_append_action(&fixture->faulty_snk_ext,
+				       &fixture->actions[1]);
+
+	connect_sink_to_port(&fixture->sink, fixture->tcpci_emul,
+			     fixture->charger_emul);
+
+	typec_status = host_cmd_typec_status(0);
+
+	/* Device is connected, but PD wasn't able to establish contract */
+	zassert_true(typec_status.pd_enabled, NULL);
+	zassert_true(typec_status.dev_connected, NULL);
+	zassert_false(typec_status.sop_connected, NULL);
+}
diff --git a/zephyr/test/drivers/usb_retimer_fw_update/CMakeLists.txt b/zephyr/test/drivers/usb_retimer_fw_update/CMakeLists.txt
new file mode 100644
index 0000000000..786726414b
--- /dev/null
+++ b/zephyr/test/drivers/usb_retimer_fw_update/CMakeLists.txt
@@ -0,0 +1,19 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Create library name based on current directory
+zephyr_library_get_current_dir_lib_name(${ZEPHYR_BASE} lib_name)
+
+# Create interface library
+zephyr_interface_library_named(${lib_name})
+
+# Add include paths
+zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}")
+zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}/include")
+
+# Add source files
+zephyr_library_sources("${CMAKE_CURRENT_SOURCE_DIR}/src/usb_retimer_fw_update.c")
+
+# Link in the library
+zephyr_library_link_libraries(${lib_name})
diff --git a/zephyr/test/drivers/usb_retimer_fw_update/prj.conf b/zephyr/test/drivers/usb_retimer_fw_update/prj.conf
new file mode 100644
index 0000000000..de54617e71
--- /dev/null
+++ b/zephyr/test/drivers/usb_retimer_fw_update/prj.conf
@@ -0,0 +1,6 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_PLATFORM_EC_ACPI=y
+CONFIG_PLATFORM_EC_USB_MUX_TASK=y
diff --git a/zephyr/test/drivers/usb_retimer_fw_update/src/usb_retimer_fw_update.c b/zephyr/test/drivers/usb_retimer_fw_update/src/usb_retimer_fw_update.c
new file mode 100644
index 0000000000..9a360761ab
--- /dev/null
+++ b/zephyr/test/drivers/usb_retimer_fw_update/src/usb_retimer_fw_update.c
@@ -0,0 +1,269 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/ztest.h>
+
+#include "test/drivers/stubs.h"
+#include "test/drivers/test_state.h"
+#include "test/drivers/utils.h"
+#include "usb_common.h"
+#include "usb_pd.h"
+
+#define BB_RETIMER_NODE DT_NODELABEL(usb_c1_bb_retimer_emul)
+#define TEST_PORT USBC_PORT_C1
+
+/* Note: for API details, see common/usbc/usb_retimer_fw_update.c */
+
+/* Helpers */
+static uint8_t acpi_read_and_verify(void)
+{
+	uint8_t read_result = acpi_read(EC_ACPI_MEM_USB_RETIMER_FW_UPDATE);
+
+	zassert_not_equal(read_result, USB_RETIMER_FW_UPDATE_ERR,
+			  "Command returned unexpected err");
+	zassert_not_equal(read_result, USB_RETIMER_FW_UPDATE_INVALID_MUX,
+			  "Command returned invalid mux");
+
+	return read_result;
+}
+
+static void usb_retimer_fw_update_suspend_port(void)
+{
+	/* Write our command to suspend the port first */
+	acpi_write(EC_ACPI_MEM_USB_RETIMER_FW_UPDATE,
+		   USB_RETIMER_FW_UPDATE_SUSPEND_PD
+				   << USB_RETIMER_FW_UPDATE_OP_SHIFT |
+			   TEST_PORT);
+
+	/* Give PD task time to suspend port */
+	k_sleep(K_SECONDS(1));
+
+	zassume_true(acpi_read_and_verify() == 0,
+		     "Failed to see successful suspend");
+}
+
+/* Test configuration */
+static void usb_retimer_fw_update_before(void *data)
+{
+	ARG_UNUSED(data);
+
+	/* Assume our common setup of a BB retimer on C1 */
+	zassume_true(EMUL_DT_GET(BB_RETIMER_NODE) != NULL,
+		     "No BB retimer found on C1");
+
+	/* Set chipset to ON, since AP would drive this process */
+	test_set_chipset_to_s0();
+
+	/* TODO(b/214401892): Check why need to give time TCPM to spin */
+	k_sleep(K_SECONDS(1));
+}
+
+static void usb_retimer_fw_update_after(void *data)
+{
+	ARG_UNUSED(data);
+
+	/* Unsuspend the port */
+	acpi_write(EC_ACPI_MEM_USB_RETIMER_FW_UPDATE,
+		   USB_RETIMER_FW_UPDATE_DISCONNECT
+				   << USB_RETIMER_FW_UPDATE_OP_SHIFT |
+			   TEST_PORT);
+
+	/* Port should resume after at least 7 seconds */
+	k_sleep(K_SECONDS(8));
+}
+
+ZTEST_SUITE(usb_retimer_fw_update, drivers_predicate_post_main, NULL,
+	    usb_retimer_fw_update_before, usb_retimer_fw_update_after, NULL);
+
+ZTEST(usb_retimer_fw_update, verify_query_port)
+{
+	/* Write our command to query ports */
+	acpi_write(EC_ACPI_MEM_USB_RETIMER_FW_UPDATE,
+		   USB_RETIMER_FW_UPDATE_QUERY_PORT
+			   << USB_RETIMER_FW_UPDATE_OP_SHIFT);
+
+	zassert_true(acpi_read_and_verify() & BIT(TEST_PORT),
+		     "Failed to see port in query");
+}
+
+ZTEST(usb_retimer_fw_update, verify_suspend_port)
+{
+	/* Write our command to suspend the port */
+	acpi_write(EC_ACPI_MEM_USB_RETIMER_FW_UPDATE,
+		   USB_RETIMER_FW_UPDATE_SUSPEND_PD
+				   << USB_RETIMER_FW_UPDATE_OP_SHIFT |
+			   TEST_PORT);
+
+	/* Give PD task time to suspend port */
+	k_sleep(K_SECONDS(1));
+
+	/* Return of 0 indicates the command succeeded */
+	zassert_true(acpi_read_and_verify() == 0,
+		     "Failed to see successful suspend");
+}
+
+ZTEST(usb_retimer_fw_update, verify_resume_port)
+{
+	usb_retimer_fw_update_suspend_port();
+
+	/* And now resume it */
+	acpi_write(EC_ACPI_MEM_USB_RETIMER_FW_UPDATE,
+		   USB_RETIMER_FW_UPDATE_RESUME_PD
+				   << USB_RETIMER_FW_UPDATE_OP_SHIFT |
+			   TEST_PORT);
+
+	/* Give PD task time to resume port */
+	k_sleep(K_SECONDS(1));
+
+	/* Note: return indicates whether the port is enabled */
+	zassert_true(acpi_read_and_verify() == 1,
+		     "Failed to see successful resume");
+}
+
+ZTEST(usb_retimer_fw_update, verify_get_mux)
+{
+	struct ec_response_typec_status typec_status;
+
+	/* Write our command to get the mux state for a port */
+	acpi_write(EC_ACPI_MEM_USB_RETIMER_FW_UPDATE,
+		   USB_RETIMER_FW_UPDATE_GET_MUX
+				   << USB_RETIMER_FW_UPDATE_OP_SHIFT |
+			   TEST_PORT);
+
+	/* Give PD task time to process */
+	k_sleep(K_SECONDS(1));
+
+	typec_status = host_cmd_typec_status(TEST_PORT);
+	zassert_true(acpi_read_and_verify() == typec_status.mux_state,
+		     "Failed to match mux state");
+}
+
+/* Commands which first require suspend to be run */
+ZTEST(usb_retimer_fw_update, verify_set_mux_usb)
+{
+	struct ec_response_typec_status typec_status;
+
+	usb_retimer_fw_update_suspend_port();
+
+	/* And now set the mux to USB */
+	acpi_write(EC_ACPI_MEM_USB_RETIMER_FW_UPDATE,
+		   USB_RETIMER_FW_UPDATE_SET_USB
+				   << USB_RETIMER_FW_UPDATE_OP_SHIFT |
+			   TEST_PORT);
+
+	/* Give PD task time to set the mux */
+	k_sleep(K_SECONDS(1));
+
+	/* Note: return indicates filtered mux state */
+	zassert_true(acpi_read_and_verify() == USB_PD_MUX_USB_ENABLED,
+		     "Failed to set mux usb");
+
+	typec_status = host_cmd_typec_status(TEST_PORT);
+	zassert_equal(typec_status.mux_state & USB_RETIMER_FW_UPDATE_MUX_MASK,
+		      USB_PD_MUX_USB_ENABLED, "Status mux disagreement");
+}
+
+ZTEST(usb_retimer_fw_update, verify_set_mux_safe)
+{
+	struct ec_response_typec_status typec_status;
+
+	usb_retimer_fw_update_suspend_port();
+
+	/* And now set the mux to safe */
+	acpi_write(EC_ACPI_MEM_USB_RETIMER_FW_UPDATE,
+		   USB_RETIMER_FW_UPDATE_SET_SAFE
+				   << USB_RETIMER_FW_UPDATE_OP_SHIFT |
+			   TEST_PORT);
+
+	/* Give PD task time to set the mux */
+	k_sleep(K_SECONDS(1));
+
+	/* Note: return indicates filtered mux state */
+	zassert_true(acpi_read_and_verify() == USB_PD_MUX_SAFE_MODE,
+		     "Failed to set mux safe");
+
+	typec_status = host_cmd_typec_status(TEST_PORT);
+	zassert_equal(typec_status.mux_state & USB_RETIMER_FW_UPDATE_MUX_MASK,
+		      USB_PD_MUX_SAFE_MODE, "Status mux disagreement");
+}
+
+ZTEST(usb_retimer_fw_update, verify_set_mux_tbt)
+{
+	struct ec_response_typec_status typec_status;
+
+	usb_retimer_fw_update_suspend_port();
+
+	/* And now set the mux to TBT */
+	acpi_write(EC_ACPI_MEM_USB_RETIMER_FW_UPDATE,
+		   USB_RETIMER_FW_UPDATE_SET_TBT
+				   << USB_RETIMER_FW_UPDATE_OP_SHIFT |
+			   TEST_PORT);
+
+	/* Give PD task time to set the mux */
+	k_sleep(K_SECONDS(1));
+
+	/* Note: return indicates filtered mux state */
+	zassert_true(acpi_read_and_verify() == USB_PD_MUX_TBT_COMPAT_ENABLED,
+		     "Failed to set mux tbt");
+
+	typec_status = host_cmd_typec_status(TEST_PORT);
+	zassert_equal(typec_status.mux_state & USB_RETIMER_FW_UPDATE_MUX_MASK,
+		      USB_PD_MUX_TBT_COMPAT_ENABLED, "Status mux disagreement");
+}
+
+ZTEST(usb_retimer_fw_update, verify_update_disconnect)
+{
+	uint64_t command_start;
+
+	usb_retimer_fw_update_suspend_port();
+
+	/* And now set the process to disconnect */
+	acpi_write(EC_ACPI_MEM_USB_RETIMER_FW_UPDATE,
+		   USB_RETIMER_FW_UPDATE_DISCONNECT
+				   << USB_RETIMER_FW_UPDATE_OP_SHIFT |
+			   TEST_PORT);
+	command_start = k_uptime_get();
+
+	/* Give PD task time to set the mux */
+	k_sleep(K_SECONDS(1));
+
+	/* Note: return indicates filtered mux state */
+	zassert_true(acpi_read_and_verify() == USB_PD_MUX_NONE,
+		     "Failed to set mux disconnect");
+
+	/*
+	 * Note: this would ideally be a host command interface check, but
+	 * the only HC return which would cover this is a state string, which
+	 * could be brittle.
+	 */
+	/* Port shouldn't be up or at least 5 seconds */
+	for (int i = 0; i < 10; i++) {
+		if (pd_is_port_enabled(TEST_PORT)) {
+			zassert_true((k_uptime_get() - command_start) > 5000,
+				     "Port resumed too soon");
+			break;
+		}
+		k_sleep(K_SECONDS(1));
+	}
+
+	zassert_true(pd_is_port_enabled(TEST_PORT), "Port not resuemd");
+}
+
+/* Verify we get an error if port isn't suspended */
+ZTEST(usb_retimer_fw_update, verify_mux_usb_error)
+{
+	/* Set the mux to USB  on unsuspended port */
+	acpi_write(EC_ACPI_MEM_USB_RETIMER_FW_UPDATE,
+		   USB_RETIMER_FW_UPDATE_SET_USB
+				   << USB_RETIMER_FW_UPDATE_OP_SHIFT |
+			   TEST_PORT);
+
+	/* Give PD task time to set the mux */
+	k_sleep(K_SECONDS(1));
+
+	zassert_true(acpi_read(EC_ACPI_MEM_USB_RETIMER_FW_UPDATE) ==
+			     USB_RETIMER_FW_UPDATE_ERR,
+		     "Failed to fail mux set");
+}
diff --git a/zephyr/test/drivers/usbc_alt_mode/CMakeLists.txt b/zephyr/test/drivers/usbc_alt_mode/CMakeLists.txt
new file mode 100644
index 0000000000..6bb0c90ed8
--- /dev/null
+++ b/zephyr/test/drivers/usbc_alt_mode/CMakeLists.txt
@@ -0,0 +1,5 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_sources(app PRIVATE src/usbc_alt_mode.c)
diff --git a/zephyr/test/drivers/usbc_alt_mode/src/usbc_alt_mode.c b/zephyr/test/drivers/usbc_alt_mode/src/usbc_alt_mode.c
new file mode 100644
index 0000000000..a005e1de11
--- /dev/null
+++ b/zephyr/test/drivers/usbc_alt_mode/src/usbc_alt_mode.c
@@ -0,0 +1,445 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <stdint.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+
+#include "ec_commands.h"
+#include "ec_tasks.h"
+#include "emul/emul_isl923x.h"
+#include "emul/tcpc/emul_ps8xxx.h"
+#include "emul/tcpc/emul_tcpci.h"
+#include "emul/tcpc/emul_tcpci_partner_snk.h"
+#include "host_command.h"
+#include "test/drivers/stubs.h"
+#include "tcpm/tcpci.h"
+#include "test/drivers/utils.h"
+#include "test/drivers/test_state.h"
+
+#define TEST_PORT 0
+
+/* Arbitrary */
+#define PARTNER_PRODUCT_ID 0x1234
+#define PARTNER_DEV_BINARY_CODED_DECIMAL 0x5678
+
+BUILD_ASSERT(TEST_PORT == USBC_PORT_C0);
+
+struct usbc_alt_mode_fixture {
+	const struct emul *tcpci_emul;
+	const struct emul *charger_emul;
+	struct tcpci_partner_data partner;
+	struct tcpci_snk_emul_data snk_ext;
+};
+
+struct usbc_alt_mode_dp_unsupported_fixture {
+	const struct emul *tcpci_emul;
+	const struct emul *charger_emul;
+	struct tcpci_partner_data partner;
+	struct tcpci_snk_emul_data snk_ext;
+};
+
+static void connect_partner_to_port(struct usbc_alt_mode_fixture *fixture)
+{
+	const struct emul *tcpc_emul = fixture->tcpci_emul;
+	struct tcpci_partner_data *partner_emul = &fixture->partner;
+
+	/*
+	 * TODO(b/221439302) Updating the TCPCI emulator registers, updating the
+	 *   vbus, as well as alerting should all be a part of the connect
+	 *   function.
+	 */
+	/* Set VBUS to vSafe0V initially. */
+	isl923x_emul_set_adc_vbus(fixture->charger_emul, 0);
+	tcpci_emul_set_reg(fixture->tcpci_emul, TCPC_REG_POWER_STATUS,
+			   TCPC_REG_POWER_STATUS_VBUS_DET);
+	tcpci_emul_set_reg(fixture->tcpci_emul, TCPC_REG_EXT_STATUS,
+			   TCPC_REG_EXT_STATUS_SAFE0V);
+	tcpci_tcpc_alert(0);
+	k_sleep(K_SECONDS(1));
+	zassume_ok(tcpci_partner_connect_to_tcpci(partner_emul, tcpc_emul),
+		   NULL);
+
+	/* Wait for PD negotiation and current ramp. */
+	k_sleep(K_SECONDS(10));
+}
+
+static void disconnect_partner_from_port(struct usbc_alt_mode_fixture *fixture)
+{
+	zassume_ok(tcpci_emul_disconnect_partner(fixture->tcpci_emul), NULL);
+	isl923x_emul_set_adc_vbus(fixture->charger_emul, 0);
+	k_sleep(K_SECONDS(1));
+}
+
+static void add_discovery_responses(struct tcpci_partner_data *partner)
+{
+	/* Add Discover Identity response */
+	partner->identity_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_PD, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_IDENT);
+	partner->identity_vdm[VDO_INDEX_IDH] = VDO_IDH(
+		/* USB host */ false, /* USB device */ false, IDH_PTYPE_AMA,
+		/* modal operation */ true, USB_VID_GOOGLE);
+	partner->identity_vdm[VDO_INDEX_CSTAT] = 0xabcdabcd;
+	partner->identity_vdm[VDO_INDEX_PRODUCT] = VDO_PRODUCT(
+		PARTNER_PRODUCT_ID, PARTNER_DEV_BINARY_CODED_DECIMAL);
+	/* Hardware version 1, firmware version 2 */
+	partner->identity_vdm[VDO_INDEX_AMA] = 0x12000000;
+	partner->identity_vdos = VDO_INDEX_AMA + 1;
+
+	/* Add Discover Modes response */
+	/* Support one mode for DisplayPort VID. Copied from Hoho. */
+	partner->modes_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_DISPLAYPORT, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_MODES);
+	partner->modes_vdm[VDO_INDEX_HDR + 1] = VDO_MODE_DP(
+		0, MODE_DP_PIN_C, 1, CABLE_PLUG, MODE_DP_V13, MODE_DP_SNK);
+	partner->modes_vdos = VDO_INDEX_HDR + 2;
+
+	/* Add Discover SVIDs response */
+	/* Support DisplayPort VID. */
+	partner->svids_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_PD, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_SVID);
+	partner->svids_vdm[VDO_INDEX_HDR + 1] =
+		VDO_SVID(USB_SID_DISPLAYPORT, 0);
+	partner->svids_vdos = VDO_INDEX_HDR + 2;
+}
+
+static void add_displayport_mode_responses(struct tcpci_partner_data *partner)
+{
+	/* DisplayPort alt mode setup remains in the same suite as discovery
+	 * setup because DisplayPort is picked from the Discovery VDOs offered.
+	 */
+
+	/* Add DisplayPort EnterMode response */
+	partner->enter_mode_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_DISPLAYPORT, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_ENTER_MODE);
+	partner->enter_mode_vdos = VDO_INDEX_HDR + 1;
+
+	/* Add DisplayPort StatusUpdate response */
+	partner->dp_status_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_DISPLAYPORT, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DP_STATUS);
+	partner->dp_status_vdm[VDO_INDEX_HDR + 1] =
+		/* Mainly copied from hoho */
+		VDO_DP_STATUS(0, /* IRQ_HPD */
+			      false, /* HPD_HI|LOW - Changed*/
+			      0, /* request exit DP */
+			      0, /* request exit USB */
+			      0, /* MF pref */
+			      true, /* DP Enabled */
+			      0, /* power low e.g. normal */
+			      0x2 /* Connected as Sink */);
+	partner->dp_status_vdos = VDO_INDEX_HDR + 2;
+
+	/* Add DisplayPort Configure Response */
+	partner->dp_config_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_DISPLAYPORT, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DP_CONFIG);
+	partner->dp_config_vdos = VDO_INDEX_HDR + 1;
+}
+
+static void *usbc_alt_mode_setup(void)
+{
+	static struct usbc_alt_mode_fixture fixture;
+	struct tcpci_partner_data *partner = &fixture.partner;
+	struct tcpci_snk_emul_data *snk_ext = &fixture.snk_ext;
+
+	tcpci_partner_init(partner, PD_REV20);
+	partner->extensions = tcpci_snk_emul_init(snk_ext, partner, NULL);
+
+	/* Get references for the emulators */
+	fixture.tcpci_emul = EMUL_GET_USBC_BINDING(TEST_PORT, tcpc);
+	fixture.charger_emul = EMUL_GET_USBC_BINDING(TEST_PORT, chg);
+
+	add_discovery_responses(partner);
+	add_displayport_mode_responses(partner);
+
+	/* Sink 5V 3A. */
+	snk_ext->pdo[1] = PDO_FIXED(5000, 3000, PDO_FIXED_UNCONSTRAINED);
+
+	return &fixture;
+}
+
+static void *usbc_alt_mode_dp_unsupported_setup(void)
+{
+	static struct usbc_alt_mode_fixture fixture;
+	struct tcpci_partner_data *partner = &fixture.partner;
+	struct tcpci_snk_emul_data *snk_ext = &fixture.snk_ext;
+
+	tcpci_partner_init(partner, PD_REV20);
+	partner->extensions = tcpci_snk_emul_init(snk_ext, partner, NULL);
+
+	/* Get references for the emulators */
+	fixture.tcpci_emul = EMUL_GET_USBC_BINDING(TEST_PORT, tcpc);
+	/* The configured TCPCI rev must match the emulator's supported rev. */
+	tcpc_config[TEST_PORT].flags |= TCPC_FLAGS_TCPCI_REV2_0;
+	tcpci_emul_set_rev(fixture.tcpci_emul, TCPCI_EMUL_REV2_0_VER1_1);
+	fixture.charger_emul = EMUL_GET_USBC_BINDING(TEST_PORT, chg);
+
+	/*
+	 * Respond to discovery REQs to indicate DisplayPort support, but do not
+	 * respond to DisplayPort alt mode VDMs, including Enter Mode.
+	 */
+	add_discovery_responses(partner);
+
+	/* Sink 5V 3A. */
+	snk_ext->pdo[1] = PDO_FIXED(5000, 3000, PDO_FIXED_UNCONSTRAINED);
+
+	return &fixture;
+}
+
+static void usbc_alt_mode_before(void *data)
+{
+	/* Set chipset to ON, this will set TCPM to DRP */
+	test_set_chipset_to_s0();
+
+	/* TODO(b/214401892): Check why need to give time TCPM to spin */
+	k_sleep(K_SECONDS(1));
+
+	connect_partner_to_port((struct usbc_alt_mode_fixture *)data);
+}
+
+static void usbc_alt_mode_after(void *data)
+{
+	disconnect_partner_from_port((struct usbc_alt_mode_fixture *)data);
+}
+
+ZTEST_F(usbc_alt_mode, verify_discovery)
+{
+	uint8_t response_buffer[EC_LPC_HOST_PACKET_SIZE];
+	struct ec_response_typec_discovery *discovery =
+		(struct ec_response_typec_discovery *)response_buffer;
+	host_cmd_typec_discovery(TEST_PORT, TYPEC_PARTNER_SOP, response_buffer,
+				 sizeof(response_buffer));
+
+	/* The host command does not count the VDM header in identity_count. */
+	zassert_equal(discovery->identity_count,
+		      fixture->partner.identity_vdos - 1,
+		      "Expected %d identity VDOs, got %d",
+		      fixture->partner.identity_vdos - 1,
+		      discovery->identity_count);
+	zassert_mem_equal(
+		discovery->discovery_vdo, fixture->partner.identity_vdm + 1,
+		discovery->identity_count * sizeof(*discovery->discovery_vdo),
+		"Discovered SOP identity ACK did not match");
+	zassert_equal(discovery->svid_count, 1, "Expected 1 SVID, got %d",
+		      discovery->svid_count);
+	zassert_equal(discovery->svids[0].svid, USB_SID_DISPLAYPORT,
+		      "Expected SVID 0x%0000x, got 0x%0000x",
+		      USB_SID_DISPLAYPORT, discovery->svids[0].svid);
+	zassert_equal(discovery->svids[0].mode_count, 1,
+		      "Expected 1 DP mode, got %d",
+		      discovery->svids[0].mode_count);
+	zassert_equal(discovery->svids[0].mode_vdo[0],
+		      fixture->partner.modes_vdm[1],
+		      "DP mode VDOs did not match");
+}
+
+ZTEST_F(usbc_alt_mode, verify_displayport_mode_entry)
+{
+	if (IS_ENABLED(CONFIG_PLATFORM_EC_USB_PD_REQUIRE_AP_MODE_ENTRY)) {
+		host_cmd_typec_control_enter_mode(TEST_PORT, TYPEC_MODE_DP);
+		k_sleep(K_SECONDS(1));
+	}
+
+	/* Verify host command when VDOs are present. */
+	struct ec_response_typec_status status;
+	struct ec_params_usb_pd_get_mode_response response;
+	int response_size;
+
+	host_cmd_usb_pd_get_amode(TEST_PORT, 0, &response, &response_size);
+
+	/* Response should be populated with a DisplayPort VDO */
+	zassert_equal(response_size, sizeof(response), NULL);
+	zassert_equal(response.svid, USB_SID_DISPLAYPORT, NULL);
+	zassert_equal(response.vdo[0],
+		      fixture->partner.modes_vdm[response.opos], NULL);
+
+	/* DPM configures the partner on DP mode entry */
+	/* Verify port partner thinks its configured for DisplayPort */
+	zassert_true(fixture->partner.displayport_configured, NULL);
+	/* Verify we also set up DP on our mux */
+	status = host_cmd_typec_status(TEST_PORT);
+	zassert_equal((status.mux_state & USB_PD_MUX_DP_ENABLED),
+		      USB_PD_MUX_DP_ENABLED, "Failed to see DP set in mux");
+
+	/*
+	 * DP alt mode partner sends HPD through VDM:Attention, which uses the
+	 * same format as the DP Status data
+	 */
+	uint32_t vdm_attention_data[2];
+
+	vdm_attention_data[0] =
+		VDO(USB_SID_DISPLAYPORT, 1,
+		    VDO_OPOS(1) | VDO_CMDT(CMDT_INIT) | CMD_ATTENTION);
+	vdm_attention_data[1] = VDO_DP_STATUS(1, /* IRQ_HPD */
+					      true, /* HPD_HI|LOW - Changed*/
+					      0, /* request exit DP */
+					      0, /* request exit USB */
+					      0, /* MF pref */
+					      true, /* DP Enabled */
+					      0, /* power low e.g. normal */
+					      0x2 /* Connected as Sink */);
+	tcpci_partner_send_data_msg(&fixture->partner, PD_DATA_VENDOR_DEF,
+				    vdm_attention_data, 2, 0);
+
+	k_sleep(K_SECONDS(1));
+	/* Verify the board's HPD notification triggered */
+	status = host_cmd_typec_status(TEST_PORT);
+	zassert_equal((status.mux_state & USB_PD_MUX_HPD_LVL),
+		      USB_PD_MUX_HPD_LVL, "Failed to set HPD level in mux");
+	zassert_equal((status.mux_state & USB_PD_MUX_HPD_IRQ),
+		      USB_PD_MUX_HPD_IRQ, "Failed to set HPD IRQin mux");
+}
+
+ZTEST_F(usbc_alt_mode, verify_displayport_mode_reentry)
+{
+	if (!IS_ENABLED(CONFIG_PLATFORM_EC_USB_PD_REQUIRE_AP_MODE_ENTRY)) {
+		ztest_test_skip();
+	}
+
+	host_cmd_typec_control_enter_mode(TEST_PORT, TYPEC_MODE_DP);
+	k_sleep(K_SECONDS(1));
+
+	/* DPM configures the partner on DP mode entry */
+	/* Verify port partner thinks its configured for DisplayPort */
+	zassert_true(fixture->partner.displayport_configured, NULL);
+
+	host_cmd_typec_control_exit_modes(TEST_PORT);
+	k_sleep(K_SECONDS(1));
+	zassert_false(fixture->partner.displayport_configured, NULL);
+
+	host_cmd_typec_control_enter_mode(TEST_PORT, TYPEC_MODE_DP);
+	k_sleep(K_SECONDS(1));
+	zassert_true(fixture->partner.displayport_configured, NULL);
+
+	/* Verify that DisplayPort is the active alternate mode. */
+	struct ec_params_usb_pd_get_mode_response response;
+	int response_size;
+
+	host_cmd_usb_pd_get_amode(TEST_PORT, 0, &response, &response_size);
+
+	/* Response should be populated with a DisplayPort VDO */
+	zassert_equal(response_size, sizeof(response), NULL);
+	zassert_equal(response.svid, USB_SID_DISPLAYPORT, NULL);
+	zassert_equal(response.vdo[0],
+		      fixture->partner.modes_vdm[response.opos], NULL);
+}
+
+ZTEST_F(usbc_alt_mode, verify_discovery_via_pd_host_cmd)
+{
+	struct ec_params_usb_pd_info_request params = { .port = TEST_PORT };
+	struct ec_params_usb_pd_discovery_entry response;
+
+	struct host_cmd_handler_args args = BUILD_HOST_COMMAND(
+		EC_CMD_USB_PD_DISCOVERY, 0, response, params);
+
+	zassert_ok(host_command_process(&args));
+	zassert_equal(args.response_size, sizeof(response), NULL);
+	zassert_equal(response.ptype, IDH_PTYPE_AMA);
+	zassert_equal(response.vid, USB_VID_GOOGLE);
+	zassert_equal(response.pid, PARTNER_PRODUCT_ID);
+}
+
+ZTEST_F(usbc_alt_mode, verify_mode_entry_via_pd_host_cmd)
+{
+	if (!IS_ENABLED(CONFIG_PLATFORM_EC_USB_PD_REQUIRE_AP_MODE_ENTRY)) {
+		ztest_test_skip();
+	}
+
+	/* Verify entering mode */
+	struct ec_params_usb_pd_set_mode_request set_mode_params = {
+		.cmd = PD_ENTER_MODE,
+		.port = TEST_PORT,
+		.opos = 1, /* Second VDO (after Discovery Responses) */
+		.svid = USB_SID_DISPLAYPORT,
+	};
+
+	struct host_cmd_handler_args set_mode_args = BUILD_HOST_COMMAND_PARAMS(
+		EC_CMD_USB_PD_SET_AMODE, 0, set_mode_params);
+
+	zassert_ok(host_command_process(&set_mode_args));
+
+	/* Verify that DisplayPort is the active alternate mode. */
+	struct ec_params_usb_pd_get_mode_response get_mode_response;
+	int response_size;
+
+	host_cmd_usb_pd_get_amode(TEST_PORT, 0, &get_mode_response,
+				  &response_size);
+
+	/* Response should be populated with a DisplayPort VDO */
+	zassert_equal(response_size, sizeof(get_mode_response), NULL);
+	zassert_equal(get_mode_response.svid, USB_SID_DISPLAYPORT, NULL);
+	zassert_equal(get_mode_response.vdo[0],
+		      fixture->partner.modes_vdm[get_mode_response.opos], NULL);
+}
+
+ZTEST_SUITE(usbc_alt_mode, drivers_predicate_post_main, usbc_alt_mode_setup,
+	    usbc_alt_mode_before, usbc_alt_mode_after, NULL);
+
+/*
+ * When the partner advertises DP mode support but refuses to enter, discovery
+ * should still work as if the partner were compliant.
+ */
+ZTEST_F(usbc_alt_mode_dp_unsupported, verify_discovery)
+{
+	if (IS_ENABLED(CONFIG_PLATFORM_EC_USB_PD_REQUIRE_AP_MODE_ENTRY)) {
+		host_cmd_typec_control_enter_mode(TEST_PORT, TYPEC_MODE_DP);
+		k_sleep(K_SECONDS(1));
+	}
+
+	uint8_t response_buffer[EC_LPC_HOST_PACKET_SIZE];
+	struct ec_response_typec_discovery *discovery =
+		(struct ec_response_typec_discovery *)response_buffer;
+	host_cmd_typec_discovery(TEST_PORT, TYPEC_PARTNER_SOP, response_buffer,
+				 sizeof(response_buffer));
+
+	/* The host command does not count the VDM header in identity_count. */
+	zassert_equal(discovery->identity_count,
+		      fixture->partner.identity_vdos - 1,
+		      "Expected %d identity VDOs, got %d",
+		      fixture->partner.identity_vdos - 1,
+		      discovery->identity_count);
+	zassert_mem_equal(
+		discovery->discovery_vdo, fixture->partner.identity_vdm + 1,
+		discovery->identity_count * sizeof(*discovery->discovery_vdo),
+		"Discovered SOP identity ACK did not match");
+	zassert_equal(discovery->svid_count, 1, "Expected 1 SVID, got %d",
+		      discovery->svid_count);
+	zassert_equal(discovery->svids[0].svid, USB_SID_DISPLAYPORT,
+		      "Expected SVID 0x%0000x, got 0x%0000x",
+		      USB_SID_DISPLAYPORT, discovery->svids[0].svid);
+	zassert_equal(discovery->svids[0].mode_count, 1,
+		      "Expected 1 DP mode, got %d",
+		      discovery->svids[0].mode_count);
+	zassert_equal(discovery->svids[0].mode_vdo[0],
+		      fixture->partner.modes_vdm[1],
+		      "DP mode VDOs did not match");
+}
+
+/*
+ * When the partner advertises DP support but refuses to enter DP mode, the TCPM
+ * should try once and then give up.
+ */
+ZTEST_F(usbc_alt_mode_dp_unsupported, verify_displayport_mode_nonentry)
+{
+	if (IS_ENABLED(CONFIG_PLATFORM_EC_USB_PD_REQUIRE_AP_MODE_ENTRY)) {
+		host_cmd_typec_control_enter_mode(TEST_PORT, TYPEC_MODE_DP);
+		k_sleep(K_SECONDS(1));
+	}
+
+	zassert_false(fixture->partner.displayport_configured, NULL);
+	int dp_attempts = atomic_get(&fixture->partner.mode_enter_attempts);
+	zassert_equal(dp_attempts, 1, "Expected 1 DP attempt, got %d",
+		      dp_attempts);
+}
+
+ZTEST_SUITE(usbc_alt_mode_dp_unsupported, drivers_predicate_post_main,
+	    usbc_alt_mode_dp_unsupported_setup, usbc_alt_mode_before,
+	    usbc_alt_mode_after, NULL);
diff --git a/zephyr/test/drivers/usbc_ocp/CMakeLists.txt b/zephyr/test/drivers/usbc_ocp/CMakeLists.txt
new file mode 100644
index 0000000000..8453bed73c
--- /dev/null
+++ b/zephyr/test/drivers/usbc_ocp/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Add source files
+target_sources(app PRIVATE src/usbc_ocp.c)
diff --git a/zephyr/test/drivers/usbc_ocp/src/usbc_ocp.c b/zephyr/test/drivers/usbc_ocp/src/usbc_ocp.c
new file mode 100644
index 0000000000..f269c1e81f
--- /dev/null
+++ b/zephyr/test/drivers/usbc_ocp/src/usbc_ocp.c
@@ -0,0 +1,64 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+#include <zephyr/ztest_assert.h>
+
+#include "usbc_ocp.h"
+#include "test/drivers/test_state.h"
+#include "timer.h"
+
+/* Tests for USBC OCP (Overcurrent Protection) Common Code */
+
+#define TEST_PORT 0
+
+/* Returns non-zero if state never reached */
+static int wait_for_port_latched_off_state(bool state)
+{
+	WAIT_FOR(state == usbc_ocp_is_port_latched_off(TEST_PORT),
+		 5000000, /* 5 Second */
+		 k_sleep(K_MSEC(1)));
+
+	return !(state == usbc_ocp_is_port_latched_off(TEST_PORT));
+}
+
+static void usbc_ocpc_suite_before_after(void *data)
+{
+	ARG_UNUSED(data);
+
+	usbc_ocp_clear_event_counter(TEST_PORT);
+	zassert_ok(wait_for_port_latched_off_state(false));
+}
+
+ZTEST(usbc_ocp, test_events_add_then_clear)
+{
+	for (int i = 0; i < OCP_MAX_CNT - 1; i++) {
+		zassert_ok(usbc_ocp_add_event(TEST_PORT),
+			   "Could not add ocp event %d", i);
+
+		zassert_ok(wait_for_port_latched_off_state(false),
+			   "Max OC events too soon");
+	}
+
+	zassert_ok(usbc_ocp_add_event(TEST_PORT));
+	zassert_ok(wait_for_port_latched_off_state(true),
+		   "Max OC events too soon");
+
+	zassert_ok(usbc_ocp_clear_event_counter(TEST_PORT));
+	zassert_ok(wait_for_port_latched_off_state(false),
+		   "Max OC events too soon");
+}
+
+ZTEST(usbc_ocp, test_bad_port_arguments)
+{
+	zassert_ok(usbc_ocp_is_port_latched_off(-1));
+
+	zassert_equal(EC_ERROR_INVAL, usbc_ocp_clear_event_counter(-1));
+	zassert_equal(EC_ERROR_INVAL, usbc_ocp_add_event(-1));
+}
+
+ZTEST_SUITE(usbc_ocp, drivers_predicate_post_main, NULL,
+	    usbc_ocpc_suite_before_after, usbc_ocpc_suite_before_after, NULL);
diff --git a/zephyr/test/drivers/usbc_tbt_mode/CMakeLists.txt b/zephyr/test/drivers/usbc_tbt_mode/CMakeLists.txt
new file mode 100644
index 0000000000..05eddf9c69
--- /dev/null
+++ b/zephyr/test/drivers/usbc_tbt_mode/CMakeLists.txt
@@ -0,0 +1,5 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+target_sources(app PRIVATE src/usbc_tbt_mode.c)
diff --git a/zephyr/test/drivers/usbc_tbt_mode/src/usbc_tbt_mode.c b/zephyr/test/drivers/usbc_tbt_mode/src/usbc_tbt_mode.c
new file mode 100644
index 0000000000..66a145c475
--- /dev/null
+++ b/zephyr/test/drivers/usbc_tbt_mode/src/usbc_tbt_mode.c
@@ -0,0 +1,336 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <stdint.h>
+#include <zephyr/kernel.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/ztest.h>
+
+#include "ec_commands.h"
+#include "ec_tasks.h"
+#include "emul/emul_isl923x.h"
+#include "emul/tcpc/emul_ps8xxx.h"
+#include "emul/tcpc/emul_tcpci.h"
+#include "emul/tcpc/emul_tcpci_partner_snk.h"
+#include "host_command.h"
+#include "test/drivers/stubs.h"
+#include "tcpm/tcpci.h"
+#include "test/drivers/utils.h"
+#include "test/drivers/test_state.h"
+#include "usb_pd_vdo.h"
+
+#define TEST_PORT USBC_PORT_C0
+/* Remove polarity for any mux checks */
+#define USB_MUX_CHECK_MASK ~USB_PD_MUX_POLARITY_INVERTED
+
+struct usbc_tbt_mode_fixture {
+	const struct emul *tcpci_emul;
+	const struct emul *charger_emul;
+	struct tcpci_partner_data partner;
+	struct tcpci_snk_emul_data snk_ext;
+};
+
+/* Passive USB3 cable */
+struct tcpci_cable_data passive_usb3 = {
+	.identity_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_PD, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_IDENT),
+	.identity_vdm[VDO_INDEX_IDH] = VDO_IDH(
+		/* USB host */ false, /* USB device */ false, IDH_PTYPE_PCABLE,
+		/* modal operation */ false, USB_VID_GOOGLE),
+	.identity_vdm[VDO_INDEX_CSTAT] = 0,
+	.identity_vdm[VDO_INDEX_PRODUCT] = VDO_PRODUCT(0x1234, 0xABCD),
+	.identity_vdm[VDO_INDEX_PTYPE_CABLE1] =
+		VDO_REV30_PASSIVE(USB_R30_SS_U32_U40_GEN2, USB_VBUS_CUR_3A,
+				  USB_REV30_LATENCY_1m, USB_REV30_TYPE_C),
+	.identity_vdos = VDO_INDEX_PTYPE_CABLE1 + 1,
+
+};
+
+static void add_sop_vdm_responses(struct tcpci_partner_data *partner)
+{
+	/* Add Discover Identity response */
+	partner->identity_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_PD, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_IDENT);
+	partner->identity_vdm[VDO_INDEX_IDH] = VDO_IDH(
+		/* USB host */ false, /* USB device */ true, IDH_PTYPE_DFP_HUB,
+		/* modal operation */ true, USB_VID_GOOGLE);
+	partner->identity_vdm[VDO_INDEX_CSTAT] = 0;
+	partner->identity_vdm[VDO_INDEX_PRODUCT] = VDO_PRODUCT(0x1234, 0x5678);
+	partner->identity_vdm[VDO_INDEX_PTYPE_UFP1_VDO] = VDO_UFP1(
+		(VDO_UFP1_CAPABILITY_USB20 | VDO_UFP1_CAPABILITY_USB32),
+		USB_TYPEC_RECEPTACLE, VDO_UFP1_ALT_MODE_TBT3,
+		USB_R30_SS_U40_GEN3);
+	partner->identity_vdm[VDO_INDEX_PTYPE_UFP2_VDO] = 0;
+	partner->identity_vdos = VDO_INDEX_PTYPE_UFP2_VDO + 1;
+
+	/* Add Discover SVIDs response */
+	/* Support TBT (Intel) VID. */
+	partner->svids_vdm[VDO_INDEX_HDR] =
+		VDO(USB_SID_PD, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_SVID);
+	partner->svids_vdm[VDO_INDEX_HDR + 1] = VDO_SVID(USB_VID_INTEL, 0);
+	partner->svids_vdos = VDO_INDEX_HDR + 2;
+
+	/* Add Discover Modes response */
+	/* Support one mode for TBT (Intel) VID */
+	partner->modes_vdm[VDO_INDEX_HDR] =
+		VDO(USB_VID_INTEL, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_MODES);
+	partner->modes_vdm[VDO_INDEX_HDR + 1] = TBT_ALTERNATE_MODE;
+	partner->modes_vdos = VDO_INDEX_HDR + 2;
+
+	/* Add affirmative mode entry */
+	partner->enter_mode_vdm[VDO_INDEX_HDR] =
+		VDO(USB_VID_INTEL, /* structured VDM */ true,
+		    VDO_CMDT(CMDT_RSP_ACK) | CMD_ENTER_MODE);
+	partner->enter_mode_vdos = VDO_INDEX_HDR + 1;
+}
+
+/* How many EnterModes were we expecting? */
+enum msg_check {
+	NO_MSG,
+	SOP_EXPECTED,
+};
+
+static void verify_vdm_messages(struct usbc_tbt_mode_fixture *fixture,
+				enum msg_check check, int cmd_type)
+{
+	struct tcpci_partner_log_msg *msg;
+	enum tcpci_msg_type types_seen[3];
+	int messages_seen = 0;
+
+	SYS_SLIST_FOR_EACH_CONTAINER(&fixture->partner.msg_log, msg, node)
+	{
+		uint16_t header = sys_get_le16(msg->buf);
+
+		/* Ignore messages from ourselves */
+		if (msg->sender == TCPCI_PARTNER_SENDER_PARTNER) {
+			continue;
+		}
+
+		/*
+		 * Control messages, non-VDMs, and extended messages are not of
+		 * interest
+		 */
+		if ((PD_HEADER_CNT(header) == 0) ||
+		    (PD_HEADER_TYPE(header) != PD_DATA_VENDOR_DEF) ||
+		    (PD_HEADER_EXT(header) != 0)) {
+			continue;
+		}
+
+		/* We have a VDM, check entry we're interested in */
+		uint32_t vdm_header = sys_get_le32(msg->buf + sizeof(header));
+
+		if (PD_VDO_CMD(vdm_header) != cmd_type) {
+			continue;
+		}
+
+		types_seen[messages_seen] = PD_HEADER_GET_SOP(header);
+		messages_seen++;
+	}
+
+	/*
+	 * Processing done, now verify message ordering.  See Type-C
+	 * specification 6.7 Active Cables That Support Alternate Modes
+	 */
+	if (check == NO_MSG) {
+		zassert_equal(messages_seen, 0,
+			      "Unexpected messages (cmd %d, num %d)", cmd_type,
+			      messages_seen);
+	} else if (check == SOP_EXPECTED) {
+		zassert_equal(messages_seen, 1,
+			      "Unexpected messages (cmd %d, num %d)", cmd_type,
+			      messages_seen);
+		zassert_equal(types_seen[0], TCPCI_MSG_SOP,
+			      "Unexpected SOP type: %d", types_seen[0]);
+	}
+}
+
+static void verify_cable_found(struct tcpci_cable_data *cable)
+{
+	uint8_t response_buffer[EC_LPC_HOST_PACKET_SIZE];
+	struct ec_response_typec_discovery *discovery =
+		(struct ec_response_typec_discovery *)response_buffer;
+
+	host_cmd_typec_discovery(TEST_PORT, TYPEC_PARTNER_SOP_PRIME,
+				 response_buffer, sizeof(response_buffer));
+
+	/* The host command does not count the VDM header in identity_count. */
+	zassert_equal(discovery->identity_count, cable->identity_vdos - 1,
+		      "Expected %d identity VDOs, got %d",
+		      cable->identity_vdos - 1, discovery->identity_count);
+	zassert_mem_equal(discovery->discovery_vdo, cable->identity_vdm + 1,
+			  discovery->identity_count *
+				  sizeof(*discovery->discovery_vdo),
+			  "Discovered SOP' identity ACK did not match");
+}
+
+static void *usbc_tbt_mode_setup(void)
+{
+	static struct usbc_tbt_mode_fixture fixture;
+	struct tcpci_partner_data *partner = &fixture.partner;
+	struct tcpci_snk_emul_data *snk_ext = &fixture.snk_ext;
+
+	tcpci_partner_init(partner, PD_REV30);
+	partner->extensions = tcpci_snk_emul_init(snk_ext, partner, NULL);
+
+	/* Get references for the emulators */
+	fixture.tcpci_emul = EMUL_DT_GET(DT_NODELABEL(tcpci_emul));
+	fixture.charger_emul = EMUL_DT_GET(DT_NODELABEL(isl923x_emul));
+
+	add_sop_vdm_responses(partner);
+	/* Note: cable behavior will vary by test case */
+
+	/* Sink 5V 3A. */
+	snk_ext->pdo[0] = PDO_FIXED(5000, 3000, PDO_FIXED_COMM_CAP);
+
+	return &fixture;
+}
+
+static void usbc_tbt_mode_before(void *data)
+{
+	ARG_UNUSED(data);
+
+	/* Set chipset to ON, this will set TCPM to DRP */
+	test_set_chipset_to_s0();
+
+	/* TODO(b/214401892): Check why need to give time TCPM to spin */
+	k_sleep(K_SECONDS(1));
+}
+
+static void usbc_tbt_mode_after(void *data)
+{
+	struct usbc_tbt_mode_fixture *fix = data;
+
+	disconnect_sink_from_port(fix->tcpci_emul);
+	tcpci_partner_common_clear_logged_msgs(&fix->partner);
+}
+
+ZTEST_F(usbc_tbt_mode, verify_discovery)
+{
+	uint8_t response_buffer[EC_LPC_HOST_PACKET_SIZE];
+	struct ec_response_typec_discovery *discovery =
+		(struct ec_response_typec_discovery *)response_buffer;
+
+	connect_sink_to_port(&fixture->partner, fixture->tcpci_emul,
+			     fixture->charger_emul);
+
+	host_cmd_typec_discovery(TEST_PORT, TYPEC_PARTNER_SOP, response_buffer,
+				 sizeof(response_buffer));
+
+	/* The host command does not count the VDM header in identity_count. */
+	zassert_equal(discovery->identity_count,
+		      fixture->partner.identity_vdos - 1,
+		      "Expected %d identity VDOs, got %d",
+		      fixture->partner.identity_vdos - 1,
+		      discovery->identity_count);
+	zassert_mem_equal(
+		discovery->discovery_vdo, fixture->partner.identity_vdm + 1,
+		discovery->identity_count * sizeof(*discovery->discovery_vdo),
+		"Discovered SOP identity ACK did not match");
+	zassert_equal(discovery->svid_count, 1, "Expected 1 SVID, got %d",
+		      discovery->svid_count);
+	zassert_equal(discovery->svids[0].svid, USB_VID_INTEL,
+		      "Expected SVID 0x%04x, got 0x%04x", USB_VID_INTEL,
+		      discovery->svids[0].svid);
+	zassert_equal(discovery->svids[0].mode_count, 1,
+		      "Expected 1 TBT mode, got %d",
+		      discovery->svids[0].mode_count);
+	zassert_equal(discovery->svids[0].mode_vdo[0],
+		      fixture->partner.modes_vdm[1],
+		      "TBT mode VDOs did not match");
+}
+
+/* Without an e-marked cable, TBT mode cannot be entered */
+ZTEST_F(usbc_tbt_mode, verify_tbt_entry_fail)
+{
+	struct ec_response_typec_status status;
+
+	fixture->partner.cable = NULL;
+	connect_sink_to_port(&fixture->partner, fixture->tcpci_emul,
+			     fixture->charger_emul);
+
+	status = host_cmd_typec_status(TEST_PORT);
+	zassume_equal((status.mux_state & USB_MUX_CHECK_MASK),
+		      USB_PD_MUX_USB_ENABLED, "Unexpected starting mux: 0x%02x",
+		      status.mux_state);
+
+	/* TODO(b/237553647): Test EC-driven mode entry (requires a separate
+	 * config).
+	 */
+	tcpci_partner_common_enable_pd_logging(&fixture->partner, true);
+	host_cmd_typec_control_enter_mode(TEST_PORT, TYPEC_MODE_TBT);
+	k_sleep(K_SECONDS(1));
+
+	/*
+	 * TODO(b/168030639): Notify the AP that the enter mode request
+	 * failed.
+	 */
+
+	/* Verify we refrained from sending TBT EnterMode. */
+	tcpci_partner_common_enable_pd_logging(&fixture->partner, false);
+	verify_vdm_messages(fixture, NO_MSG, CMD_ENTER_MODE);
+
+	status = host_cmd_typec_status(TEST_PORT);
+	zassert_equal((status.mux_state & USB_MUX_CHECK_MASK),
+		      USB_PD_MUX_USB_ENABLED, "Failed to see USB still set");
+	zassert_not_equal((status.mux_state & USB_MUX_CHECK_MASK),
+			  USB_PD_MUX_TBT_COMPAT_ENABLED,
+			  "Unexpected TBT mode set");
+}
+
+/* With passive e-marked cable, TBT mode can be entered on SOP only */
+ZTEST_F(usbc_tbt_mode, verify_tbt_passive_entry_exit)
+{
+	struct ec_response_typec_status status;
+
+	fixture->partner.cable = &passive_usb3;
+	connect_sink_to_port(&fixture->partner, fixture->tcpci_emul,
+			     fixture->charger_emul);
+
+	verify_cable_found(fixture->partner.cable);
+
+	status = host_cmd_typec_status(TEST_PORT);
+	zassume_equal((status.mux_state & USB_MUX_CHECK_MASK),
+		      USB_PD_MUX_USB_ENABLED, "Unexpected starting mux: 0x%02x",
+		      status.mux_state);
+
+	/* TODO(b/237553647): Test EC-driven mode entry (requires a separate
+	 * config).
+	 */
+	tcpci_partner_common_enable_pd_logging(&fixture->partner, true);
+	host_cmd_typec_control_enter_mode(TEST_PORT, TYPEC_MODE_TBT);
+	k_sleep(K_SECONDS(1));
+
+	/*
+	 * TODO(b/168030639): Notify the AP that the enter mode request
+	 * succeeded.
+	 */
+
+	/* Verify we sent a single TBT SOP EnterMode. */
+	tcpci_partner_common_enable_pd_logging(&fixture->partner, false);
+	verify_vdm_messages(fixture, SOP_EXPECTED, CMD_ENTER_MODE);
+	status = host_cmd_typec_status(TEST_PORT);
+	zassert_equal((status.mux_state & USB_MUX_CHECK_MASK),
+		      USB_PD_MUX_TBT_COMPAT_ENABLED, "Failed to see TBT set");
+
+	/* Exit modes now */
+	tcpci_partner_common_clear_logged_msgs(&fixture->partner);
+	tcpci_partner_common_enable_pd_logging(&fixture->partner, true);
+	host_cmd_typec_control_exit_modes(TEST_PORT);
+	k_sleep(K_SECONDS(1));
+
+	/* Verify we sent a single TBT SOP ExitMode. */
+	tcpci_partner_common_enable_pd_logging(&fixture->partner, false);
+	verify_vdm_messages(fixture, SOP_EXPECTED, CMD_EXIT_MODE);
+	status = host_cmd_typec_status(TEST_PORT);
+	zassert_equal((status.mux_state & USB_MUX_CHECK_MASK),
+		      USB_PD_MUX_USB_ENABLED, "Failed to see USB set");
+}
+
+ZTEST_SUITE(usbc_tbt_mode, drivers_predicate_post_main, usbc_tbt_mode_setup,
+	    usbc_tbt_mode_before, usbc_tbt_mode_after, NULL);
diff --git a/zephyr/test/ec_app/BUILD.py b/zephyr/test/ec_app/BUILD.py
deleted file mode 100644
index eeb85c0e46..0000000000
--- a/zephyr/test/ec_app/BUILD.py
+++ /dev/null
@@ -1,7 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-"""Register zmake project for ec_app test."""
-
-register_host_test("ec_app")
diff --git a/zephyr/test/ec_app/CMakeLists.txt b/zephyr/test/ec_app/CMakeLists.txt
index 8ee9a554a7..83daf93e67 100644
--- a/zephyr/test/ec_app/CMakeLists.txt
+++ b/zephyr/test/ec_app/CMakeLists.txt
@@ -1,9 +1,9 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 cmake_minimum_required(VERSION 3.13.1)
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
 project(ec_app)
 
 FILE(GLOB app_sources src/*.c)
diff --git a/zephyr/test/ec_app/boards/native_posix.overlay b/zephyr/test/ec_app/boards/native_posix.overlay
new file mode 100644
index 0000000000..69bf044ec6
--- /dev/null
+++ b/zephyr/test/ec_app/boards/native_posix.overlay
@@ -0,0 +1,37 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <board-overlays/native_posix.dts>
+#include <cros/binman.dtsi>
+
+/ {
+	chosen {
+		cros-ec,flash = &flash1;
+		cros-ec,flash-controller = &cros_flash;
+	};
+	aliases {
+		gpio-wp = &gpio_wp_l;
+	};
+	named-gpios {
+		compatible = "named-gpios";
+		ec_gsc_packet_mode {
+			gpios = <&gpio0 2 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_PACKET_MODE_EN";
+		};
+		gpio_wp_l: wp_l {
+			gpios = <&gpio0 3 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+	};
+	cros_flash: cros-flash {
+		compatible = "cros-ec,flash-emul";
+	};
+	flash1: flash@64000000 {
+		reg = <0x64000000 DT_SIZE_K(512)>;
+	};
+};
+
+&gpio0 {
+	ngpios = <4>;
+};
diff --git a/zephyr/test/ec_app/prj.conf b/zephyr/test/ec_app/prj.conf
index b398d0dd8c..3b44c56b6b 100644
--- a/zephyr/test/ec_app/prj.conf
+++ b/zephyr/test/ec_app/prj.conf
@@ -1,7 +1,21 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 CONFIG_ZTEST=y
+CONFIG_ZTEST_NEW_API=y
 CONFIG_PLATFORM_EC=y
 CONFIG_CROS_EC=y
+CONFIG_SHIMMED_TASKS=y
+CONFIG_FLASH=y
+CONFIG_SHELL_BACKEND_DUMMY=y
+CONFIG_SHELL_BACKEND_SERIAL=n
+CONFIG_SERIAL=y
+CONFIG_RING_BUFFER=y
+
+CONFIG_EMUL_CROS_FLASH=y
+CONFIG_PLATFORM_EC_VBOOT_EFS2=y
+CONFIG_PLATFORM_EC_VBOOT_HASH=y
+CONFIG_PLATFORM_EC_HOSTCMD=y
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
+CONFIG_PLATFORM_EC_SWITCH=n
diff --git a/zephyr/test/ec_app/src/main.c b/zephyr/test/ec_app/src/main.c
index 47aecc7eca..b106754d47 100644
--- a/zephyr/test/ec_app/src/main.c
+++ b/zephyr/test/ec_app/src/main.c
@@ -1,74 +1,71 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <ztest.h>
+#include <zephyr/ztest_assert.h>
+#include <zephyr/ztest_test_new.h>
+#include <zephyr/shell/shell_dummy.h>
+
 #include "ec_app_main.h"
 #include "hooks.h"
+#include "task.h"
 
-static void test_init_reset_log(void)
-{
 #ifdef CONFIG_CMD_AP_RESET_LOG
+ZTEST(ec_app_tests, test_init_reset_log)
+{
 	zassert_unreachable("TODO: Implement this test.");
-#else
-	ztest_test_skip();
-#endif
 }
+#endif
 
-static void test_lpc_init_mask(void)
-{
 #ifdef CONFIG_HOSTCMD_X86
+ZTEST(ec_app_tests, test_lpc_init_mask)
+{
 	zassert_unreachable("TODO: Implement this test.");
-#else
-	ztest_test_skip();
-#endif
 }
+#endif
 
-static void test_keyboard_scan_init(void)
-{
 #ifdef HAS_TASK_KEYSCAN
+ZTEST(ec_app_tests, test_keyboard_scan_init)
+{
 	zassert_unreachable("TODO: Implement this test.");
-#else
-	ztest_test_skip();
-#endif
 }
+#endif
 
-static void test_button_init(void)
-{
 #if defined(CONFIG_DEDICATED_RECOVERY_BUTTON) || defined(CONFIG_VOLUME_BUTTONS)
+ZTEST(ec_app_tests, test_button_init)
+{
 	zassert_unreachable("TODO: Implement this test.");
-#else
-	ztest_test_skip();
-#endif
 }
+#endif
 
-static void test_setup_espi(void)
-{
 #ifdef CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI
+ZTEST(ec_app_tests, test_setup_espi)
+{
 	zassert_unreachable("TODO: Implement this test.");
-#else
-	ztest_test_skip();
-#endif
 }
+#endif
 
-static void test_watchdog_init(void)
-{
 #ifdef CONFIG_PLATFORM_EC_WATCHDOG
+ZTEST(ec_app_tests, test_watchdog_init)
+{
 	zassert_unreachable("TODO: Implement this test.");
-#else
-	ztest_test_skip();
-#endif
 }
+#endif
 
-static void test_vboot_main(void)
-{
 #ifdef CONFIG_PLATFORM_EC_VBOOT_EFS2
-	zassert_unreachable("TODO: Implement this test.");
-#else
-	ztest_test_skip();
-#endif
+ZTEST(ec_app_tests, test_vboot_main)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+	const char *outbuffer;
+	size_t buffer_size;
+
+	/* vboot_main logs the message "VB Verifying hash" */
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+	zassert_true(strstr(outbuffer, "VB Verifying hash") != NULL,
+		     "'VB Verifying hash' not found in %s", outbuffer);
 }
+#endif
 
 #ifdef CONFIG_PLATFORM_EC_HOOKS
 static int sample_init_hook_count;
@@ -88,40 +85,28 @@ DECLARE_HOOK(HOOK_INIT, sample_init_hook, HOOK_PRIO_DEFAULT);
  * This test installs a hook, runs main and verifies that the hook ran.
  *
  */
-static void test_hook_notify_init(void)
+ZTEST(ec_app_tests, test_hook_notify_init)
 {
-	sample_init_hook_count = 0;
-	ec_app_main();
 	zassert_equal(1, sample_init_hook_count,
 		      "Expected sample_init_hook to run once.");
 }
-#else
-static void test_hook_notify_init(void)
+#endif
+
+#ifdef CONFIG_SHIMMED_TASKS
+ZTEST(ec_app_tests, test_start_ec_tasks)
 {
-	ztest_test_skip();
+	zassert_equal(task_start_called(), 1, "Tasks did not start.");
 }
 #endif
 
-static void test_start_ec_tasks(void)
+/* Does setup for all of the test cases. */
+void *ec_app_setup(void)
 {
 #ifdef CONFIG_SHIMMED_TASKS
-	zassert_unreachable("TODO: Implement this test.");
-#else
-	ztest_test_skip();
+	zassert_equal(task_start_called(), 0, "Tasks have already started.");
 #endif
+	ec_app_main();
+	return NULL;
 }
 
-void test_main(void)
-{
-	ztest_test_suite(ec_app_tests, ztest_unit_test(test_init_reset_log),
-			 ztest_unit_test(test_lpc_init_mask),
-			 ztest_unit_test(test_keyboard_scan_init),
-			 ztest_unit_test(test_button_init),
-			 ztest_unit_test(test_setup_espi),
-			 ztest_unit_test(test_watchdog_init),
-			 ztest_unit_test(test_vboot_main),
-			 ztest_unit_test(test_hook_notify_init),
-			 ztest_unit_test(test_start_ec_tasks));
-
-	ztest_run_test_suite(ec_app_tests);
-}
+ZTEST_SUITE(ec_app_tests, NULL, ec_app_setup, NULL, NULL, NULL);
diff --git a/zephyr/test/ec_app/testcase.yaml b/zephyr/test/ec_app/testcase.yaml
new file mode 100644
index 0000000000..4f21d64207
--- /dev/null
+++ b/zephyr/test/ec_app/testcase.yaml
@@ -0,0 +1,4 @@
+common:
+  platform_allow: native_posix
+tests:
+  ec_app.default: {}
diff --git a/zephyr/test/herobrine/CMakeLists.txt b/zephyr/test/herobrine/CMakeLists.txt
new file mode 100644
index 0000000000..8209eb77fb
--- /dev/null
+++ b/zephyr/test/herobrine/CMakeLists.txt
@@ -0,0 +1,14 @@
+# Copyright 2022 The ChromiumOS Authors.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(herobrine)
+
+zephyr_include_directories("${PLATFORM_EC}/zephyr/projects/herobrine/include")
+
+target_sources_ifdef(CONFIG_TEST_BOARD_CHIPSET
+	app PRIVATE src/board_chipset.c)
+target_sources_ifdef(CONFIG_TEST_BOARD_CHIPSET
+	app PRIVATE ${PLATFORM_EC}/zephyr/projects/herobrine/src/board_chipset.c)
diff --git a/zephyr/test/herobrine/Kconfig b/zephyr/test/herobrine/Kconfig
new file mode 100644
index 0000000000..415e6e58af
--- /dev/null
+++ b/zephyr/test/herobrine/Kconfig
@@ -0,0 +1,12 @@
+# Copyright 2022 The ChromiumOS Authors.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config TEST_BOARD_CHIPSET
+	bool "Run the tests intended for board_chipset"
+	help
+	  Include board_chipset.c into the binary. Test their functions in
+	  different combinations: good battery vs low battery, normal boot
+	  vs delayed boot, etc.
+
+source "Kconfig.zephyr"
diff --git a/zephyr/test/herobrine/README.md b/zephyr/test/herobrine/README.md
new file mode 100644
index 0000000000..398b27e304
--- /dev/null
+++ b/zephyr/test/herobrine/README.md
@@ -0,0 +1,3 @@
+Tests for board specific code under `zephyr/projects/herobrine/src`.
+
+Run with ./twister -T zephyr/test/herobrine
diff --git a/zephyr/test/herobrine/boards/native_posix.overlay b/zephyr/test/herobrine/boards/native_posix.overlay
new file mode 100644
index 0000000000..bfecc9a7d5
--- /dev/null
+++ b/zephyr/test/herobrine/boards/native_posix.overlay
@@ -0,0 +1,26 @@
+/* Copyright 2022 The ChromiumOS Authors.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <board-overlays/native_posix.dts>
+
+/ {
+        /*
+         * Keep these GPIOs in pin order.
+         * If you need to add one, make sure you increase
+         * ngpios in the gpio0 node further down.
+         */
+        named-gpios {
+                compatible = "named-gpios";
+
+                gpio_en_pp5000_s5: en_pp5000_s5 {
+                        gpios = <&gpio0 2 GPIO_OUTPUT_HIGH>;
+                        enum-name = "GPIO_EN_PP5000";
+                };
+	};
+};
+
+&gpio0 {
+        ngpios = <3>;
+};
diff --git a/zephyr/test/herobrine/prj.conf b/zephyr/test/herobrine/prj.conf
new file mode 100644
index 0000000000..3334f11939
--- /dev/null
+++ b/zephyr/test/herobrine/prj.conf
@@ -0,0 +1,11 @@
+# Copyright 2022 The ChromiumOS Authors.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_ZTEST=y
+CONFIG_ZTEST_ASSERT_VERBOSE=1
+CONFIG_ZTEST_NEW_API=y
+CONFIG_ASSERT=y
+
+CONFIG_CROS_EC=y
+CONFIG_PLATFORM_EC=y
diff --git a/zephyr/test/herobrine/src/board_chipset.c b/zephyr/test/herobrine/src/board_chipset.c
new file mode 100644
index 0000000000..77bdb14e16
--- /dev/null
+++ b/zephyr/test/herobrine/src/board_chipset.c
@@ -0,0 +1,76 @@
+/* Copyright 2022 The ChromiumOS Authors.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+#include "hooks.h"
+#include "board_chipset.h"
+
+static int battery_soc_abs_value = 50;
+
+int battery_state_of_charge_abs(int *percent)
+{
+	*percent = battery_soc_abs_value;
+	return EC_SUCCESS;
+}
+
+int charger_get_min_bat_pct_for_power_on(void)
+{
+	return 2;
+}
+
+ZTEST_USER(board_chipset, test_good_battery_normal_boot)
+{
+	timestamp_t start_time;
+	uint64_t time_diff_us;
+
+	battery_soc_abs_value = 50;
+
+	start_time = get_time();
+	hook_notify(HOOK_CHIPSET_PRE_INIT);
+	time_diff_us = get_time().val - start_time.val;
+
+	zassert_true(time_diff_us < 10, "CHIPSET_PRE_INIT hook delayed", NULL);
+}
+
+ZTEST_USER(board_chipset, test_low_battery_normal_boot)
+{
+	timestamp_t start_time;
+	uint64_t time_diff_us;
+
+	battery_soc_abs_value = 1;
+
+	start_time = get_time();
+	hook_notify(HOOK_CHIPSET_PRE_INIT);
+	time_diff_us = get_time().val - start_time.val;
+
+	zassert_true(time_diff_us < 10, "CHIPSET_PRE_INIT hook delayed", NULL);
+}
+
+ZTEST_USER(board_chipset, test_low_battery_delayed_boot)
+{
+	timestamp_t start_time;
+	uint64_t time_diff_us;
+
+	battery_soc_abs_value = 1;
+	/* The PD connect event delays the power on sequence */
+	hook_notify(HOOK_USB_PD_CONNECT);
+
+	start_time = get_time();
+	hook_notify(HOOK_CHIPSET_PRE_INIT);
+	time_diff_us = get_time().val - start_time.val;
+
+	zassert_true(time_diff_us > 500000, "CHIPSET_PRE_INIT hook not delayed",
+		     NULL);
+}
+
+static void test_before(void *data)
+{
+	ARG_UNUSED(data);
+	reset_pp5000_inited();
+}
+
+ZTEST_SUITE(board_chipset, NULL, NULL, test_before, NULL, NULL);
diff --git a/zephyr/test/herobrine/testcase.yaml b/zephyr/test/herobrine/testcase.yaml
new file mode 100644
index 0000000000..e5f17a3848
--- /dev/null
+++ b/zephyr/test/herobrine/testcase.yaml
@@ -0,0 +1,10 @@
+# Copyright 2022 The ChromiumOS Authors.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+common:
+  platform_allow: native_posix
+tests:
+  herobrine.board_chipset:
+    extra_configs:
+      - CONFIG_TEST_BOARD_CHIPSET=y
diff --git a/zephyr/test/hooks/BUILD.py b/zephyr/test/hooks/BUILD.py
deleted file mode 100644
index ee25ae52bc..0000000000
--- a/zephyr/test/hooks/BUILD.py
+++ /dev/null
@@ -1,7 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-"""Register zmake project for hooks test."""
-
-register_host_test("hooks")
diff --git a/zephyr/test/hooks/CMakeLists.txt b/zephyr/test/hooks/CMakeLists.txt
index 81ff57d69d..99b0b3f430 100644
--- a/zephyr/test/hooks/CMakeLists.txt
+++ b/zephyr/test/hooks/CMakeLists.txt
@@ -1,9 +1,9 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 cmake_minimum_required(VERSION 3.13.1)
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
 project(hooks)
 
 target_sources(app PRIVATE hooks.c)
diff --git a/zephyr/test/hooks/boards/native_posix.overlay b/zephyr/test/hooks/boards/native_posix.overlay
new file mode 100644
index 0000000000..90c864d2fd
--- /dev/null
+++ b/zephyr/test/hooks/boards/native_posix.overlay
@@ -0,0 +1,6 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <board-overlays/native_posix.dts>
diff --git a/zephyr/test/hooks/hooks.c b/zephyr/test/hooks/hooks.c
index 0070f2e6b4..7d784aa65f 100644
--- a/zephyr/test/hooks/hooks.c
+++ b/zephyr/test/hooks/hooks.c
@@ -1,10 +1,10 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include <stdbool.h>
-#include <ztest.h>
+#include <zephyr/ztest.h>
 
 #include "ap_power/ap_power.h"
 #include "hooks.h"
@@ -40,7 +40,7 @@ static void h3(void)
 }
 DECLARE_HOOK(HOOK_TEST_1, h3, HOOK_PRIO_LAST);
 
-static void test_hook_list_multiple(void)
+ZTEST(hooks_tests, test_hook_list_multiple)
 {
 	hook_notify(HOOK_TEST_1);
 	zassert_true(h1_called, "h1 was not called, but should have been");
@@ -57,13 +57,13 @@ static void h4(void)
 }
 DECLARE_HOOK(HOOK_TEST_2, h4, HOOK_PRIO_DEFAULT);
 
-static void test_hook_list_single(void)
+ZTEST(hooks_tests, test_hook_list_single)
 {
 	hook_notify(HOOK_TEST_2);
 	zassert_true(h4_called, "h4 was not called, but should have been");
 }
 
-static void test_hook_list_empty(void)
+ZTEST(hooks_tests, test_hook_list_empty)
 {
 	hook_notify(HOOK_TEST_3);
 }
@@ -77,7 +77,7 @@ static void deferred_func(void)
 }
 DECLARE_DEFERRED(deferred_func);
 
-static void test_deferred_func(void)
+ZTEST(hooks_tests, test_deferred_func)
 {
 	zassert_false(
 		deferred_func_called,
@@ -104,7 +104,7 @@ DECLARE_DEFERRED(deferred_func_2);
  * Test that repeated calls to hook_call_deferred result in the
  * function being pushed out.
  */
-static void test_deferred_func_push_out(void)
+ZTEST(hooks_tests, test_deferred_func_push_out)
 {
 	zassert_false(
 		deferred_func_2_called,
@@ -129,7 +129,7 @@ static void deferred_func_3(void)
 }
 DECLARE_DEFERRED(deferred_func_3);
 
-static void test_deferred_func_cancel(void)
+ZTEST(hooks_tests, test_deferred_func_cancel)
 {
 	zassert_false(
 		deferred_func_3_called,
@@ -164,7 +164,7 @@ static void ev_handler(struct ap_power_ev_callback *callback,
 	ev->event = data.event;
 }
 
-static void test_hook_ap_power_events(void)
+ZTEST(hooks_tests, test_hook_ap_power_events)
 {
 	static struct events cb;
 
@@ -179,7 +179,7 @@ static void test_hook_ap_power_events(void)
 
 	cb.count = 0;
 	ap_power_ev_init_callback(&cb.cb, ev_handler,
-		AP_POWER_SUSPEND|AP_POWER_RESUME);
+				  AP_POWER_SUSPEND | AP_POWER_RESUME);
 	ap_power_ev_add_callback(&cb.cb);
 	hook_notify(HOOK_CHIPSET_SUSPEND);
 	zassert_equal(1, cb.count, "Callbacks not called");
@@ -199,17 +199,4 @@ static void test_hook_ap_power_events(void)
 	zassert_equal(3, cb.count, "Startup callback not called");
 }
 
-void test_main(void)
-{
-	ztest_test_suite(
-		hooks_tests,
-		ztest_unit_test(test_hook_list_multiple),
-		ztest_unit_test(test_hook_list_single),
-		ztest_unit_test(test_hook_list_empty),
-		ztest_unit_test(test_deferred_func),
-		ztest_unit_test(test_deferred_func_push_out),
-		ztest_unit_test(test_deferred_func_cancel),
-		ztest_unit_test(test_hook_ap_power_events));
-
-	ztest_run_test_suite(hooks_tests);
-}
+ZTEST_SUITE(hooks_tests, NULL, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/hooks/prj.conf b/zephyr/test/hooks/prj.conf
index c0c02e22ca..cab9107094 100644
--- a/zephyr/test/hooks/prj.conf
+++ b/zephyr/test/hooks/prj.conf
@@ -1,8 +1,9 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 CONFIG_ZTEST=y
+CONFIG_ZTEST_NEW_API=y
 CONFIG_PLATFORM_EC=y
 CONFIG_PLATFORM_EC_HOOKS=y
 CONFIG_CROS_EC=y
diff --git a/zephyr/test/hooks/testcase.yaml b/zephyr/test/hooks/testcase.yaml
new file mode 100644
index 0000000000..f35baae16b
--- /dev/null
+++ b/zephyr/test/hooks/testcase.yaml
@@ -0,0 +1,4 @@
+common:
+  platform_allow: native_posix
+tests:
+  hooks.default: {}
diff --git a/zephyr/test/i2c/BUILD.py b/zephyr/test/i2c/BUILD.py
deleted file mode 100644
index 86d9da537a..0000000000
--- a/zephyr/test/i2c/BUILD.py
+++ /dev/null
@@ -1,7 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-"""Register zmake project for i2c test."""
-
-register_host_test("i2c", dts_overlays=["overlay.dts"])
diff --git a/zephyr/test/i2c/CMakeLists.txt b/zephyr/test/i2c/CMakeLists.txt
index 214177013f..4b355c4932 100644
--- a/zephyr/test/i2c/CMakeLists.txt
+++ b/zephyr/test/i2c/CMakeLists.txt
@@ -1,9 +1,9 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 cmake_minimum_required(VERSION 3.13.1)
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
 project(i2c)
 
 target_sources(app PRIVATE src/main.c)
diff --git a/zephyr/test/i2c/boards/native_posix.overlay b/zephyr/test/i2c/boards/native_posix.overlay
new file mode 100644
index 0000000000..e78c5d0faa
--- /dev/null
+++ b/zephyr/test/i2c/boards/native_posix.overlay
@@ -0,0 +1,37 @@
+/* Copyright 2020 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <board-overlays/native_posix.dts>
+
+/ {
+	i2c1: i2c@400 {
+		status = "okay";
+		compatible = "zephyr,i2c-emul-controller";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x400 4>;
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+		accel-0 {
+			i2c-port = <&i2c0>;
+			enum-names = "I2C_PORT_ACCEL",
+				"I2C_PORT_EEPROM";
+		};
+		usb-c1 {
+			i2c-port = <&i2c1>;
+			enum-names = "I2C_PORT_USB_C1";
+		};
+	};
+};
+
+&i2c0 {
+	bmi_i2c: bmi@68 {
+		compatible = "bosch,bmi160";
+		reg = <0x68>;
+	};
+};
diff --git a/zephyr/test/i2c/prj.conf b/zephyr/test/i2c/prj.conf
index 69c276712e..ee6c43f51a 100644
--- a/zephyr/test/i2c/prj.conf
+++ b/zephyr/test/i2c/prj.conf
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/test/i2c/src/main.c b/zephyr/test/i2c/src/main.c
index dbe9878da5..364353f06d 100644
--- a/zephyr/test/i2c/src/main.c
+++ b/zephyr/test/i2c/src/main.c
@@ -1,13 +1,14 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include <zephyr/devicetree.h>
-#include <ztest.h>
+#include <zephyr/ztest.h>
 
 #include "common.h"
 #include "i2c/i2c.h"
+#include "i2c.h"
 
 /* Unused: required for shimming i2c. */
 void watchdog_reload(void)
@@ -16,18 +17,47 @@ void watchdog_reload(void)
 
 static void test_i2c_port_count(void)
 {
-	zassert_equal(NAMED_I2C(accel_0), 0,
-		      "accel_0 expected to be 0 but was %d",
-		      NAMED_I2C(accel_0));
-	zassert_equal(I2C_PORT_COUNT, 1,
-		      "I2C_PORT_COUNT expected to be 1 but was %d",
+	zassert_equal(I2C_PORT_COUNT, 2,
+		      "I2C_PORT_COUNT expected to be 2 but was %d",
 		      I2C_PORT_COUNT);
 }
 
+static void test_i2c_lock(void)
+{
+	i2c_lock(I2C_PORT_ACCEL, 1);
+	zassert_equal(i2c_port_is_locked(I2C_PORT_EEPROM), 1,
+		      "I2C_PORT_EEPROM not locked");
+	zassert_equal(i2c_port_is_locked(I2C_PORT_ACCEL), 1,
+		      "I2C_PORT_ACCEL not locked");
+
+	/* Unlock different enum pointing the same i2c device */
+	i2c_lock(I2C_PORT_EEPROM, 0);
+	zassert_equal(i2c_port_is_locked(I2C_PORT_EEPROM), 0,
+		      "I2C_PORT_EEPROM not locked");
+	zassert_equal(i2c_port_is_locked(I2C_PORT_ACCEL), 0,
+		      "I2C_PORT_ACCEL not locked");
+
+	i2c_lock(I2C_PORT_EEPROM, 1);
+	/* Verify different i2c device */
+	zassert_equal(i2c_port_is_locked(I2C_PORT_USB_C1), 0,
+		      "I2C_PORT_USB_C1 locked");
+
+	i2c_lock(I2C_PORT_USB_C1, 1);
+	/* Make sure i2c device is locked*/
+	zassert_equal(i2c_port_is_locked(I2C_PORT_USB_C1), 1,
+		      "I2C_PORT_USB_C1 locked");
+
+	/* Another i2c device is still locked */
+	i2c_lock(I2C_PORT_USB_C1, 0);
+	zassert_equal(i2c_port_is_locked(I2C_PORT_EEPROM), 1,
+		      "I2C_PORT_EEPROM not locked");
+	i2c_lock(I2C_PORT_EEPROM, 0);
+}
+
 /* Test case main entry. */
 void test_main(void)
 {
-	ztest_test_suite(test_i2c,
-			 ztest_user_unit_test(test_i2c_port_count));
+	ztest_test_suite(test_i2c, ztest_user_unit_test(test_i2c_port_count),
+			 ztest_user_unit_test(test_i2c_lock));
 	ztest_run_test_suite(test_i2c);
 }
diff --git a/zephyr/test/i2c/testcase.yaml b/zephyr/test/i2c/testcase.yaml
new file mode 100644
index 0000000000..4e111ea13f
--- /dev/null
+++ b/zephyr/test/i2c/testcase.yaml
@@ -0,0 +1,4 @@
+common:
+  platform_allow: native_posix
+tests:
+  i2c.default: {}
diff --git a/zephyr/test/i2c_dts/BUILD.py b/zephyr/test/i2c_dts/BUILD.py
deleted file mode 100644
index e0e97be121..0000000000
--- a/zephyr/test/i2c_dts/BUILD.py
+++ /dev/null
@@ -1,7 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-"""Register zmake project for i2c_dts test."""
-
-register_host_test("i2c_dts", dts_overlays=["overlay.dts"])
diff --git a/zephyr/test/i2c_dts/CMakeLists.txt b/zephyr/test/i2c_dts/CMakeLists.txt
index eea2834af1..3e36468a33 100644
--- a/zephyr/test/i2c_dts/CMakeLists.txt
+++ b/zephyr/test/i2c_dts/CMakeLists.txt
@@ -1,9 +1,9 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 cmake_minimum_required(VERSION 3.13.1)
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
 project(i2c_test)
 
 FILE(GLOB app_sources src/*.c)
diff --git a/zephyr/test/i2c/overlay.dts b/zephyr/test/i2c_dts/boards/native_posix.overlay
index 1519bb1cb7..0abd2f1f31 100644
--- a/zephyr/test/i2c/overlay.dts
+++ b/zephyr/test/i2c_dts/boards/native_posix.overlay
@@ -1,14 +1,16 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include <board-overlays/native_posix.dts>
+
 / {
 	named-i2c-ports {
 		compatible = "named-i2c-ports";
 		accel-0 {
-			i2c-port = <&bmi_i2c>;
-			enum-name = "I2C_PORT_ACCEL";
+			i2c-port = <&i2c0>;
+			enum-names = "I2C_PORT_ACCEL";
 		};
 	};
 };
@@ -17,6 +19,5 @@
 	bmi_i2c: bmi@68 {
 		compatible = "bosch,bmi160";
 		reg = <0x68>;
-		label = "accel-i2c";
 	};
 };
diff --git a/zephyr/test/i2c_dts/overlay.dts b/zephyr/test/i2c_dts/overlay.dts
deleted file mode 100644
index 1519bb1cb7..0000000000
--- a/zephyr/test/i2c_dts/overlay.dts
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/ {
-	named-i2c-ports {
-		compatible = "named-i2c-ports";
-		accel-0 {
-			i2c-port = <&bmi_i2c>;
-			enum-name = "I2C_PORT_ACCEL";
-		};
-	};
-};
-
-&i2c0 {
-	bmi_i2c: bmi@68 {
-		compatible = "bosch,bmi160";
-		reg = <0x68>;
-		label = "accel-i2c";
-	};
-};
diff --git a/zephyr/test/i2c_dts/prj.conf b/zephyr/test/i2c_dts/prj.conf
index a08cdbb7fb..6c008faf64 100644
--- a/zephyr/test/i2c_dts/prj.conf
+++ b/zephyr/test/i2c_dts/prj.conf
@@ -1,4 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
 CONFIG_ZTEST=y
+CONFIG_ZTEST_NEW_API=y
 CONFIG_LOG=y
 
 CONFIG_EMUL=y
diff --git a/zephyr/test/i2c_dts/src/main.c b/zephyr/test/i2c_dts/src/main.c
index 7cb1052798..1557eaf9e9 100644
--- a/zephyr/test/i2c_dts/src/main.c
+++ b/zephyr/test/i2c_dts/src/main.c
@@ -1,30 +1,23 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include <zephyr/device.h>
 #include <zephyr/devicetree.h>
-#include <ztest.h>
+#include <zephyr/ztest.h>
 
-static void test_i2c_get_device(void)
+ZTEST(i2c_bindings, test_i2c_get_device)
 {
 	const struct device *accel0 = DEVICE_DT_GET(
-			DT_PHANDLE(DT_PATH(named_i2c_ports, accel_0),
-				   i2c_port));
-	const struct device *bmi_i2c = DEVICE_DT_GET(
-			DT_NODELABEL(bmi_i2c));
+		DT_PHANDLE(DT_PATH(named_i2c_ports, accel_0), i2c_port));
+	const struct device *bmi_i2c = DEVICE_DT_GET(DT_NODELABEL(i2c0));
 
 	zassert_not_null(accel0, "accel0 was NULL");
 	zassert_not_null(bmi_i2c, "bmi_i2c was NULL");
-	zassert_equal(accel0, bmi_i2c,
+	zassert_equal(
+		accel0, bmi_i2c,
 		"named_i2c_ports/accel0 and bmi_i2c should resolve to the same device");
 }
 
-/* test case main entry */
-void test_main(void)
-{
-	ztest_test_suite(test_i2c_bindings,
-			 ztest_user_unit_test(test_i2c_get_device));
-	ztest_run_test_suite(test_i2c_bindings);
-}
+ZTEST_SUITE(i2c_bindings, NULL, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/i2c_dts/testcase.yaml b/zephyr/test/i2c_dts/testcase.yaml
new file mode 100644
index 0000000000..7b3d133a27
--- /dev/null
+++ b/zephyr/test/i2c_dts/testcase.yaml
@@ -0,0 +1,4 @@
+common:
+  platform_allow: native_posix
+tests:
+  i2c_dts.default: {}
diff --git a/zephyr/test/kingler/CMakeLists.txt b/zephyr/test/kingler/CMakeLists.txt
new file mode 100644
index 0000000000..b572e67fb5
--- /dev/null
+++ b/zephyr/test/kingler/CMakeLists.txt
@@ -0,0 +1,26 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(kingler)
+
+zephyr_include_directories("${PLATFORM_EC}/zephyr/projects/corsola/include")
+
+target_sources(app PRIVATE src/fakes.c)
+
+target_sources_ifdef(CONFIG_TEST_STEELIX_RUSTY
+app PRIVATE ${PLATFORM_EC}/zephyr/projects/corsola/src/kingler/board_steelix.c)
+target_sources_ifdef(CONFIG_TEST_FORM_FACTOR_CONVERTIBLE
+			app PRIVATE src/tablet.c)
+target_sources_ifdef(CONFIG_TEST_FORM_FACTOR_CLAMSHELL
+			app PRIVATE src/clamshell.c)
+target_sources_ifdef(CONFIG_VARIANT_CORSOLA_DB_DETECTION
+app PRIVATE ${PLATFORM_EC}/zephyr/projects/corsola/src/variant_db_detection.c)
+target_sources_ifdef(CONFIG_TEST_DB_DETECT_TYPEC
+			app PRIVATE src/db_detect_typec.c)
+target_sources_ifdef(CONFIG_TEST_DB_DETECT_HDMI
+			app PRIVATE src/db_detect_hdmi.c)
+target_sources_ifdef(CONFIG_TEST_DB_DETECT_NONE
+			app PRIVATE src/db_detect_none.c)
diff --git a/zephyr/test/kingler/Kconfig b/zephyr/test/kingler/Kconfig
new file mode 100644
index 0000000000..af52042cb6
--- /dev/null
+++ b/zephyr/test/kingler/Kconfig
@@ -0,0 +1,45 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config TEST_STEELIX_RUSTY
+	bool "Run the tests intended for steelix and rusty"
+	help
+	  Include board_steelix.c into the binary to test the clamshell and
+	  convertible.
+
+config TEST_FORM_FACTOR_CLAMSHELL
+	bool "Run the tests intended for clamshells"
+	help
+	  Include clamshell tests into the binary.
+
+config TEST_FORM_FACTOR_CONVERTIBLE
+	bool "Run the tests intended for convertibles"
+	help
+	  Include convertible tests into the binary.
+
+config VARIANT_CORSOLA_DB_DETECTION
+	bool "Run the tests intended for corsola DB detection"
+	help
+	  Include variant_db_detection.c into the binary to test the type-c DB
+	  tests, HDMI DB tests and none DB tests.
+
+config TEST_DB_DETECT_TYPEC
+	bool "Run the tests intended for type-c DB"
+	help
+	  Include type-c DB tests into the binary.
+	  test for DB GPIOs and interrupt.
+
+config TEST_DB_DETECT_HDMI
+	bool "Run the tests intended for HDMI DB"
+	help
+	  Include HDMI DB tests into the binary.
+	  test for DB GPIOs and interrupt.
+
+config TEST_DB_DETECT_NONE
+	bool "Run the tests intended for none DB"
+	help
+	  Include none DB tests into the binary.
+	  test for DB GPIOs and interrupt.
+
+source "Kconfig.zephyr"
diff --git a/zephyr/test/kingler/README.md b/zephyr/test/kingler/README.md
new file mode 100644
index 0000000000..bac3afced2
--- /dev/null
+++ b/zephyr/test/kingler/README.md
@@ -0,0 +1,3 @@
+Tests for board specific code under `zephyr/projects/corsola/src/kingler`.
+
+Run with ./twister -T zephyr/test/kingler
diff --git a/zephyr/test/kingler/common.dts b/zephyr/test/kingler/common.dts
new file mode 100644
index 0000000000..e065da896a
--- /dev/null
+++ b/zephyr/test/kingler/common.dts
@@ -0,0 +1,155 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <board-overlays/native_posix.dts>
+#include <npcx_emul.dts>
+
+/ {
+	/* These are temporary just to get the test to build.
+	 * Should be replaced with the correct accel drivers,
+	 * but we're not testing that code right now anyway.
+	 */
+	motionsense-sensor-data {
+		bmi160_data: bmi160-drv-data {
+			compatible = "cros-ec,drvdata-bmi160";
+			status = "okay";
+		};
+	};
+	motionsense-sensor {
+		base_accel: ms-bmi160-accel {
+			compatible = "cros-ec,bmi160-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3_S5";
+			location = "MOTIONSENSE_LOC_BASE";
+			drv-data = <&bmi160_data>;
+			default-range = <4>;
+			i2c-spi-addr-flags = "BMI160_ADDR0_FLAGS";
+		};
+		lid_accel: ms-bmi160-accel2 {
+			compatible = "cros-ec,bmi160-accel";
+			status = "okay";
+
+			active-mask = "SENSOR_ACTIVE_S0_S3_S5";
+			location = "MOTIONSENSE_LOC_BASE";
+			drv-data = <&bmi160_data>;
+			default-range = <4>;
+			i2c-spi-addr-flags = "BMI160_ADDR0_FLAGS";
+		};
+	};
+	motionsense-sensor-info {
+		compatible = "cros-ec,motionsense-sensor-info";
+
+		/*
+		 * list of GPIO interrupts that have to
+		 * be enabled at initial stage
+		 */
+		sensor-irqs = <&int_base_imu>;
+		/* list of sensors in force mode */
+		accel-force-mode-sensors = <&lid_accel>;
+	};
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+		i2c_sensor: sensor {
+			i2c-port = <&i2c0_0>;
+			enum-names = "I2C_PORT_SENSOR";
+		};
+		i2c_eeprom: sensor {
+			i2c-port = <&i2c3_0>;
+			enum-names = "I2C_PORT_EEPROM";
+		};
+	};
+	/* TODO(jbettis): Move the i2c ports and pinctrls to npcx_emul.dts,
+	 * and add all of them instead of just these.
+	 */
+	soc-if {
+		i2c0_0: io_i2c_ctrl0_port0 {
+			compatible = "nuvoton,npcx-i2c-port";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port = <0x00>;
+			controller = <&i2c_ctrl0>;
+			status = "disabled";
+		};
+		i2c3_0: io_i2c_ctrl3_port0 {
+			compatible = "nuvoton,npcx-i2c-port";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port = <0x30>;
+			controller = <&i2c_ctrl3>;
+			status = "disabled";
+		};
+	};
+	pinctrl: pinctrl {
+		compatible = "nuvoton,npcx-pinctrl";
+		status = "okay";
+		/* I2C peripheral interfaces */
+		/omit-if-no-ref/ i2c0_0_sda_scl_gpb4_b5: periph-i2c0-0 {
+			pinmux = <&alt2_i2c0_0_sl>;
+			periph-pupd = <0x00 0>;
+		};
+		/omit-if-no-ref/ i2c3_0_sda_scl_gpd0_d1: periph-i2c3-0 {
+			pinmux = <&alt2_i2c3_0_sl>;
+			periph-pupd = <0x00 6>;
+		};
+	};
+	npcx-alts-map {
+		compatible = "nuvoton,npcx-pinctrl-conf";
+		/* SCFG DEVALT 2 */
+		alt2_i2c0_0_sl: alt20 {
+			alts = <&scfg 0x02 0x0 0>;
+		};
+		alt2_i2c3_0_sl: alt26 {
+			alts = <&scfg 0x02 0x6 0>;
+		};
+	};
+};
+
+&i2c0_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>;
+	pinctrl-names = "default";
+};
+
+&i2c_ctrl0 {
+	status = "okay";
+};
+
+&i2c_ctrl2 {
+	status = "okay";
+};
+
+i2c_pwr_cbi: &i2c3_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>;
+	pinctrl-names = "default";
+
+	charger: isl923x@9 {
+		compatible = "intersil,isl923x";
+		status = "okay";
+		reg = <0x9>;
+	};
+};
+
+&i2c_ctrl3 {
+	status = "okay";
+};
+
+&i2c_ctrl5 {
+	status = "okay";
+};
+
+&i2c_ctrl3 {
+	cbi_eeprom: eeprom@50 {
+		compatible = "atmel,at24";
+		reg = <0x50>;
+		size = <2048>;
+		pagesize = <16>;
+		address-width = <8>;
+		timeout = <5>;
+	};
+};
diff --git a/zephyr/test/kingler/prj.conf b/zephyr/test/kingler/prj.conf
new file mode 100644
index 0000000000..dfa1c68d4d
--- /dev/null
+++ b/zephyr/test/kingler/prj.conf
@@ -0,0 +1,31 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_ZTEST=y
+CONFIG_ZTEST_ASSERT_VERBOSE=1
+CONFIG_ZTEST_NEW_API=y
+CONFIG_ASSERT=y
+CONFIG_EMUL=y
+CONFIG_PLATFORM_EC_HOOKS=y
+
+CONFIG_CROS_EC=y
+CONFIG_PLATFORM_EC=y
+CONFIG_SHIMMED_TASKS=y
+
+CONFIG_PLATFORM_EC_MOTIONSENSE=y
+CONFIG_PLATFORM_EC_DYNAMIC_MOTION_SENSOR_COUNT=y
+CONFIG_PLATFORM_EC_GMR_TABLET_MODE=y
+CONFIG_PLATFORM_EC_TABLET_MODE=y
+CONFIG_PLATFORM_EC_LID_ANGLE=y
+
+CONFIG_I2C=y
+CONFIG_I2C_NPCX=n
+
+CONFIG_PLATFORM_EC_CBI_EEPROM=y
+CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=y
+CONFIG_EEPROM=y
+CONFIG_EEPROM_AT24=y
+CONFIG_EEPROM_SIMULATOR=n
+CONFIG_EMUL_EEPROM_AT2X=y
+CONFIG_EEPROM_SHELL=n
diff --git a/zephyr/test/kingler/src/clamshell.c b/zephyr/test/kingler/src/clamshell.c
new file mode 100644
index 0000000000..88595cc114
--- /dev/null
+++ b/zephyr/test/kingler/src/clamshell.c
@@ -0,0 +1,89 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "zephyr/kernel.h"
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/ztest.h>
+
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "tablet_mode.h"
+
+static void *clamshell_setup(void)
+{
+	uint32_t val;
+	const struct device *wp_gpio =
+		DEVICE_DT_GET(DT_GPIO_CTLR(DT_ALIAS(gpio_wp), gpios));
+	const gpio_port_pins_t wp_pin = DT_GPIO_PIN(DT_ALIAS(gpio_wp), gpios);
+
+	/* Make sure that write protect is disabled */
+	zassert_ok(gpio_emul_input_set(wp_gpio, wp_pin, 1), NULL);
+	/* Set CBI form factor to CONVERTIBLE. */
+	zassert_ok(cbi_set_fw_config(CLAMSHELL << 13), NULL);
+	/* Run init hooks to initialize cbi. */
+	hook_notify(HOOK_INIT);
+
+	/* Check if CBI write worked. */
+	zassert_ok(cros_cbi_get_fw_config(FORM_FACTOR, &val), NULL);
+	zassert_equal(CLAMSHELL, val, "val=%d", val);
+
+	return NULL;
+}
+
+ZTEST_SUITE(steelix_clamshell, NULL, clamshell_setup, NULL, NULL, NULL);
+
+ZTEST(steelix_clamshell, test_gmr_tablet_switch_disabled)
+{
+	const struct device *tablet_mode_gpio = DEVICE_DT_GET(
+		DT_GPIO_CTLR(DT_NODELABEL(gpio_tablet_mode_l), gpios));
+	const gpio_port_pins_t tablet_mode_pin =
+		DT_GPIO_PIN(DT_NODELABEL(gpio_tablet_mode_l), gpios);
+
+	/* Verify gmr_tablet_switch is disabled, by checking the side effects
+	 * of calling tablet_set_mode, and setting gpio_tablet_mode_l.
+	 */
+	zassert_ok(gpio_emul_input_set(tablet_mode_gpio, tablet_mode_pin, 0),
+		   NULL);
+	k_sleep(K_MSEC(100));
+	tablet_set_mode(1, TABLET_TRIGGER_LID);
+	zassert_equal(0, tablet_get_mode(), NULL);
+	zassert_ok(gpio_emul_input_set(tablet_mode_gpio, tablet_mode_pin, 1),
+		   NULL);
+	k_sleep(K_MSEC(100));
+	tablet_set_mode(0, TABLET_TRIGGER_LID);
+	zassert_equal(0, tablet_get_mode(), NULL);
+	zassert_ok(gpio_emul_input_set(tablet_mode_gpio, tablet_mode_pin, 0),
+		   NULL);
+	k_sleep(K_MSEC(100));
+	tablet_set_mode(1, TABLET_TRIGGER_LID);
+	zassert_equal(0, tablet_get_mode(), NULL);
+}
+
+static int interrupt_count;
+
+void bmi3xx_interrupt(enum gpio_signal signal)
+{
+	interrupt_count++;
+}
+
+ZTEST(steelix_clamshell, test_base_imu_irq_disabled)
+{
+	const struct device *base_imu_gpio = DEVICE_DT_GET(
+		DT_GPIO_CTLR(DT_NODELABEL(base_imu_int_l), gpios));
+	const gpio_port_pins_t base_imu_pin =
+		DT_GPIO_PIN(DT_NODELABEL(base_imu_int_l), gpios);
+
+	/* Verify base_imu_irq is disabled. */
+	interrupt_count = 0;
+	zassert_ok(gpio_emul_input_set(base_imu_gpio, base_imu_pin, 1), NULL);
+	k_sleep(K_MSEC(100));
+	zassert_ok(gpio_emul_input_set(base_imu_gpio, base_imu_pin, 0), NULL);
+	k_sleep(K_MSEC(100));
+
+	zassert_equal(interrupt_count, 0, "interrupt_count=%d",
+		      interrupt_count);
+}
diff --git a/zephyr/test/kingler/src/db_detect_hdmi.c b/zephyr/test/kingler/src/db_detect_hdmi.c
new file mode 100644
index 0000000000..35cf92ae5e
--- /dev/null
+++ b/zephyr/test/kingler/src/db_detect_hdmi.c
@@ -0,0 +1,83 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "zephyr/kernel.h"
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/ztest.h>
+
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "variant_db_detection.h"
+
+static void *db_detection_setup(void)
+{
+	const struct device *hdmi_prsnt_gpio = DEVICE_DT_GET(
+		DT_GPIO_CTLR(DT_NODELABEL(gpio_hdmi_prsnt_odl), gpios));
+	const gpio_port_pins_t hdmi_prsnt_pin =
+		DT_GPIO_PIN(DT_NODELABEL(gpio_hdmi_prsnt_odl), gpios);
+	/* Set the GPIO to low to indicate the DB is HDMI */
+	zassert_ok(gpio_emul_input_set(hdmi_prsnt_gpio, hdmi_prsnt_pin, 0),
+		   NULL);
+
+	hook_notify(HOOK_INIT);
+
+	return NULL;
+}
+
+ZTEST_SUITE(db_detection, NULL, db_detection_setup, NULL, NULL, NULL);
+
+static int interrupt_count;
+void x_ec_interrupt(enum gpio_signal signal)
+{
+	interrupt_count++;
+}
+
+/* test hdmi db case */
+ZTEST(db_detection, test_db_detect_hdmi)
+{
+	const struct device *en_hdmi_gpio =
+		DEVICE_DT_GET(DT_GPIO_CTLR(DT_ALIAS(gpio_en_hdmi_pwr), gpios));
+	const gpio_port_pins_t en_hdmi_pin =
+		DT_GPIO_PIN(DT_ALIAS(gpio_en_hdmi_pwr), gpios);
+	const struct device *ps185_pwrdn_gpio = DEVICE_DT_GET(
+		DT_GPIO_CTLR(DT_ALIAS(gpio_ps185_pwrdn_odl), gpios));
+	const gpio_port_pins_t ps185_pwrdn_pin =
+		DT_GPIO_PIN(DT_ALIAS(gpio_ps185_pwrdn_odl), gpios);
+	const struct device *int_x_ec_gpio = DEVICE_DT_GET(
+		DT_GPIO_CTLR(DT_NODELABEL(gpio_x_ec_gpio2), gpios));
+	const gpio_port_pins_t int_x_ec_pin =
+		DT_GPIO_PIN(DT_NODELABEL(gpio_x_ec_gpio2), gpios);
+
+	/* Check the DB type is HDMI */
+	zassert_equal(CORSOLA_DB_HDMI, corsola_get_db_type(), NULL);
+
+	/* Verify we can enable or disable hdmi power */
+	zassert_ok(gpio_pin_set_dt(GPIO_DT_FROM_ALIAS(gpio_en_hdmi_pwr), 1),
+		   NULL);
+	zassert_equal(1, gpio_emul_output_get(en_hdmi_gpio, en_hdmi_pin), NULL);
+	zassert_ok(gpio_pin_set_dt(GPIO_DT_FROM_ALIAS(gpio_en_hdmi_pwr), 0),
+		   NULL);
+	zassert_equal(0, gpio_emul_output_get(en_hdmi_gpio, en_hdmi_pin), NULL);
+
+	/* Verify we can change the gpio_ps185_pwrdn_odl state */
+	zassert_ok(gpio_pin_set_dt(GPIO_DT_FROM_ALIAS(gpio_ps185_pwrdn_odl), 1),
+		   NULL);
+	zassert_equal(1,
+		      gpio_emul_output_get(ps185_pwrdn_gpio, ps185_pwrdn_pin),
+		      NULL);
+	zassert_ok(gpio_pin_set_dt(GPIO_DT_FROM_ALIAS(gpio_ps185_pwrdn_odl), 0),
+		   NULL);
+	zassert_equal(0,
+		      gpio_emul_output_get(ps185_pwrdn_gpio, ps185_pwrdn_pin),
+		      NULL);
+
+	/* Verify x_ec_interrupt is enabled */
+	interrupt_count = 0;
+	zassert_ok(gpio_emul_input_set(int_x_ec_gpio, int_x_ec_pin, 1), NULL);
+	k_sleep(K_MSEC(100));
+
+	zassert_equal(interrupt_count, 1, "interrupt_count=%d",
+		      interrupt_count);
+}
diff --git a/zephyr/test/kingler/src/db_detect_none.c b/zephyr/test/kingler/src/db_detect_none.c
new file mode 100644
index 0000000000..9f37db04af
--- /dev/null
+++ b/zephyr/test/kingler/src/db_detect_none.c
@@ -0,0 +1,79 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <stdlib.h>
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/ztest.h>
+
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "variant_db_detection.h"
+
+static void *db_detection_setup(void)
+{
+	const struct device *wp_gpio =
+		DEVICE_DT_GET(DT_GPIO_CTLR(DT_ALIAS(gpio_wp), gpios));
+	const gpio_port_pins_t wp_pin = DT_GPIO_PIN(DT_ALIAS(gpio_wp), gpios);
+
+	/* Make sure that write protect is disabled */
+	zassert_ok(gpio_emul_input_set(wp_gpio, wp_pin, 1), NULL);
+	/* Set CBI db_config to DB_NONE. */
+	zassert_ok(cbi_set_fw_config(DB_NONE << 0), NULL);
+	/* Run init hooks to initialize cbi. */
+	hook_notify(HOOK_INIT);
+	return NULL;
+}
+
+ZTEST_SUITE(db_detection, NULL, db_detection_setup, NULL, NULL, NULL);
+
+static int interrupt_count;
+void x_ec_interrupt(enum gpio_signal signal)
+{
+	interrupt_count++;
+}
+
+/* test none db case */
+ZTEST(db_detection, test_db_detect_none)
+{
+	gpio_flags_t *flags = (gpio_flags_t *)malloc(sizeof(gpio_flags_t));
+
+	const struct device *ec_x_gpio1 = DEVICE_DT_GET(
+		DT_GPIO_CTLR(DT_NODELABEL(gpio_ec_x_gpio1), gpios));
+	gpio_pin_t ec_x_pin1 =
+		DT_GPIO_PIN(DT_NODELABEL(gpio_ec_x_gpio1), gpios);
+	const struct device *x_ec_gpio2 = DEVICE_DT_GET(
+		DT_GPIO_CTLR(DT_NODELABEL(gpio_x_ec_gpio2), gpios));
+	gpio_pin_t x_ec_pin2 =
+		DT_GPIO_PIN(DT_NODELABEL(gpio_x_ec_gpio2), gpios);
+	const struct device *ec_x_gpio3 = DEVICE_DT_GET(
+		DT_GPIO_CTLR(DT_NODELABEL(gpio_ec_x_gpio3), gpios));
+	gpio_pin_t ec_x_pin3 =
+		DT_GPIO_PIN(DT_NODELABEL(gpio_ec_x_gpio3), gpios);
+
+	/* Check the DB type is NONE */
+	zassert_equal(CORSOLA_DB_NONE, corsola_get_db_type(), NULL);
+
+	/* Verify the floating pins are input with PU to prevent leakage */
+	zassert_ok(gpio_emul_flags_get(ec_x_gpio1, ec_x_pin1, flags), NULL);
+	zassert_equal(*flags, (GPIO_INPUT | GPIO_PULL_UP), "flags=%d", *flags);
+	zassert_ok(gpio_emul_flags_get(x_ec_gpio2, x_ec_pin2, flags), NULL);
+	zassert_equal(*flags, (GPIO_INPUT | GPIO_PULL_UP), "flags=%d", *flags);
+	zassert_ok(gpio_emul_flags_get(ec_x_gpio3, ec_x_pin3, flags), NULL);
+	zassert_equal(*flags, (GPIO_INPUT | GPIO_PULL_UP), "flags=%d", *flags);
+	free(flags);
+
+	/* Verify x_ec_interrupt is disabled */
+	interrupt_count = 0;
+	zassert_ok(gpio_emul_input_set(x_ec_gpio2, x_ec_pin2, 0), NULL);
+	k_sleep(K_MSEC(100));
+	zassert_ok(gpio_emul_input_set(x_ec_gpio2, x_ec_pin2, 1), NULL);
+	k_sleep(K_MSEC(100));
+
+	zassert_equal(interrupt_count, 0, "interrupt_count=%d",
+		      interrupt_count);
+}
diff --git a/zephyr/test/kingler/src/db_detect_typec.c b/zephyr/test/kingler/src/db_detect_typec.c
new file mode 100644
index 0000000000..53716fe552
--- /dev/null
+++ b/zephyr/test/kingler/src/db_detect_typec.c
@@ -0,0 +1,85 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "zephyr/kernel.h"
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/ztest.h>
+
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "variant_db_detection.h"
+
+static void *db_detection_setup(void)
+{
+	const struct device *hdmi_prsnt_gpio = DEVICE_DT_GET(
+		DT_GPIO_CTLR(DT_NODELABEL(gpio_hdmi_prsnt_odl), gpios));
+	const gpio_port_pins_t hdmi_prsnt_pin =
+		DT_GPIO_PIN(DT_NODELABEL(gpio_hdmi_prsnt_odl), gpios);
+	/* Set the GPIO to high to indicate the DB is type-c */
+	zassert_ok(gpio_emul_input_set(hdmi_prsnt_gpio, hdmi_prsnt_pin, 1),
+		   NULL);
+
+	hook_notify(HOOK_INIT);
+
+	return NULL;
+}
+
+ZTEST_SUITE(db_detection, NULL, db_detection_setup, NULL, NULL, NULL);
+
+static int interrupt_count;
+void x_ec_interrupt(enum gpio_signal signal)
+{
+	interrupt_count++;
+}
+
+/* test typec db case */
+ZTEST(db_detection, test_db_detect_typec)
+{
+	const struct device *en_frs_gpio = DEVICE_DT_GET(
+		DT_GPIO_CTLR(DT_ALIAS(gpio_usb_c1_frs_en), gpios));
+	const gpio_port_pins_t en_frs_pin =
+		DT_GPIO_PIN(DT_ALIAS(gpio_usb_c1_frs_en), gpios);
+	const struct device *c1_dp_in_hpd_gpio = DEVICE_DT_GET(
+		DT_GPIO_CTLR(DT_ALIAS(gpio_usb_c1_dp_in_hpd), gpios));
+	const gpio_port_pins_t c1_dp_in_hpd_pin =
+		DT_GPIO_PIN(DT_ALIAS(gpio_usb_c1_dp_in_hpd), gpios);
+	const struct device *int_x_ec_gpio = DEVICE_DT_GET(
+		DT_GPIO_CTLR(DT_NODELABEL(gpio_x_ec_gpio2), gpios));
+	const gpio_port_pins_t int_x_ec_pin =
+		DT_GPIO_PIN(DT_NODELABEL(gpio_x_ec_gpio2), gpios);
+
+	/* Check the DB type is type-c */
+	zassert_equal(CORSOLA_DB_TYPEC, corsola_get_db_type(), NULL);
+
+	/* Verify we can enable or disable FRS by setting gpio_usb_c1_frs_en */
+	zassert_ok(gpio_pin_set_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_frs_en), 1),
+		   NULL);
+	zassert_equal(1, gpio_emul_output_get(en_frs_gpio, en_frs_pin), NULL);
+	zassert_ok(gpio_pin_set_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_frs_en), 0),
+		   NULL);
+	zassert_equal(0, gpio_emul_output_get(en_frs_gpio, en_frs_pin), NULL);
+
+	/* Verify we can change the gpio_usb_c1_dp_in_hpd state */
+	zassert_ok(gpio_pin_set_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_dp_in_hpd),
+				   1),
+		   NULL);
+	zassert_equal(1,
+		      gpio_emul_output_get(c1_dp_in_hpd_gpio, c1_dp_in_hpd_pin),
+		      NULL);
+	zassert_ok(gpio_pin_set_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_dp_in_hpd),
+				   0),
+		   NULL);
+	zassert_equal(0,
+		      gpio_emul_output_get(c1_dp_in_hpd_gpio, c1_dp_in_hpd_pin),
+		      NULL);
+
+	/* Verify x_ec_interrupt is enabled */
+	interrupt_count = 0;
+	zassert_ok(gpio_emul_input_set(int_x_ec_gpio, int_x_ec_pin, 0), NULL);
+	k_sleep(K_MSEC(100));
+
+	zassert_equal(interrupt_count, 1, "interrupt_count=%d",
+		      interrupt_count);
+}
diff --git a/zephyr/test/kingler/src/fakes.c b/zephyr/test/kingler/src/fakes.c
new file mode 100644
index 0000000000..cbf6c8d98c
--- /dev/null
+++ b/zephyr/test/kingler/src/fakes.c
@@ -0,0 +1,29 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/fff.h>
+#include "gpio_signal.h"
+
+DEFINE_FFF_GLOBALS;
+FAKE_VOID_FUNC(power_button_interrupt, enum gpio_signal);
+FAKE_VOID_FUNC(button_interrupt, enum gpio_signal);
+FAKE_VOID_FUNC(lid_interrupt, enum gpio_signal);
+FAKE_VOID_FUNC(chipset_reset_request_interrupt, enum gpio_signal);
+FAKE_VOID_FUNC(power_signal_interrupt, enum gpio_signal);
+FAKE_VOID_FUNC(chipset_watchdog_interrupt, enum gpio_signal);
+FAKE_VOID_FUNC(extpower_interrupt, enum gpio_signal);
+FAKE_VOID_FUNC(usb_a0_interrupt, enum gpio_signal);
+FAKE_VOID_FUNC(switch_interrupt, enum gpio_signal);
+FAKE_VOID_FUNC(tcpc_alert_event, enum gpio_signal);
+FAKE_VOID_FUNC(ppc_interrupt, enum gpio_signal);
+FAKE_VOID_FUNC(bc12_interrupt, enum gpio_signal);
+
+#ifdef CONFIG_TEST_STEELIX_RUSTY
+FAKE_VOID_FUNC(x_ec_interrupt, enum gpio_signal);
+#endif
+
+#ifdef CONFIG_VARIANT_CORSOLA_DB_DETECTION
+FAKE_VOID_FUNC(bmi3xx_interrupt, enum gpio_signal);
+#endif
diff --git a/zephyr/test/kingler/src/tablet.c b/zephyr/test/kingler/src/tablet.c
new file mode 100644
index 0000000000..68be2b2b68
--- /dev/null
+++ b/zephyr/test/kingler/src/tablet.c
@@ -0,0 +1,91 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "zephyr/kernel.h"
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/ztest.h>
+
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "tablet_mode.h"
+
+static void *tablet_setup(void)
+{
+	uint32_t val;
+	const struct device *wp_gpio =
+		DEVICE_DT_GET(DT_GPIO_CTLR(DT_ALIAS(gpio_wp), gpios));
+	const gpio_port_pins_t wp_pin = DT_GPIO_PIN(DT_ALIAS(gpio_wp), gpios);
+
+	/* Make sure that write protect is disabled */
+	zassert_ok(gpio_emul_input_set(wp_gpio, wp_pin, 1), NULL);
+	/* Set CBI form factor to CONVERTIBLE. */
+	zassert_ok(cbi_set_fw_config(CONVERTIBLE << 13), NULL);
+	/* Run init hooks to initialize cbi. */
+	hook_notify(HOOK_INIT);
+
+	/* Check if CBI write worked. */
+	zassert_ok(cros_cbi_get_fw_config(FORM_FACTOR, &val), NULL);
+	zassert_equal(CONVERTIBLE, val, "val=%d", val);
+
+	return NULL;
+}
+
+ZTEST_SUITE(steelix_tablet, NULL, tablet_setup, NULL, NULL, NULL);
+
+ZTEST(steelix_tablet, test_gmr_tablet_switch_enabled)
+{
+	const struct device *tablet_mode_gpio = DEVICE_DT_GET(
+		DT_GPIO_CTLR(DT_NODELABEL(gpio_tablet_mode_l), gpios));
+	const gpio_port_pins_t tablet_mode_pin =
+		DT_GPIO_PIN(DT_NODELABEL(gpio_tablet_mode_l), gpios);
+
+	/* Verify gmr_tablet_switch is enabled, by checking the side effects
+	 * of calling tablet_set_mode, and setting gpio_tablet_mode_l.
+	 */
+	zassert_ok(gpio_emul_input_set(tablet_mode_gpio, tablet_mode_pin, 0),
+		   NULL);
+	k_sleep(K_MSEC(100));
+	tablet_set_mode(1, TABLET_TRIGGER_LID);
+	zassert_equal(1, tablet_get_mode(), NULL);
+	zassert_ok(gpio_emul_input_set(tablet_mode_gpio, tablet_mode_pin, 1),
+		   NULL);
+	k_sleep(K_MSEC(100));
+	tablet_set_mode(0, TABLET_TRIGGER_LID);
+	zassert_equal(0, tablet_get_mode(), NULL);
+	zassert_ok(gpio_emul_input_set(tablet_mode_gpio, tablet_mode_pin, 0),
+		   NULL);
+	k_sleep(K_MSEC(100));
+	tablet_set_mode(1, TABLET_TRIGGER_LID);
+	zassert_equal(1, tablet_get_mode(), NULL);
+}
+
+static int interrupt_count;
+
+void bmi3xx_interrupt(enum gpio_signal signal)
+{
+	interrupt_count++;
+}
+
+ZTEST(steelix_tablet, test_base_imu_irq_enabled)
+{
+	const struct device *base_imu_gpio = DEVICE_DT_GET(
+		DT_GPIO_CTLR(DT_NODELABEL(base_imu_int_l), gpios));
+	const gpio_port_pins_t base_imu_pin =
+		DT_GPIO_PIN(DT_NODELABEL(base_imu_int_l), gpios);
+
+	/* Verify base_imu_irq is enabled. Interrupt is configured
+	 * GPIO_INT_EDGE_FALLING, so set high, then set low.
+	 */
+	interrupt_count = 0;
+	zassert_ok(gpio_emul_input_set(base_imu_gpio, base_imu_pin, 1), NULL);
+	k_sleep(K_MSEC(100));
+	zassert_ok(gpio_emul_input_set(base_imu_gpio, base_imu_pin, 0), NULL);
+	k_sleep(K_MSEC(100));
+
+	zassert_equal(interrupt_count, 1, "interrupt_count=%d",
+		      interrupt_count);
+}
diff --git a/zephyr/test/kingler/testcase.yaml b/zephyr/test/kingler/testcase.yaml
new file mode 100644
index 0000000000..1d6c1bd0a8
--- /dev/null
+++ b/zephyr/test/kingler/testcase.yaml
@@ -0,0 +1,32 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+common:
+  platform_allow: native_posix
+tests:
+  kingler.steelix:
+    extra_args: DTC_OVERLAY_FILE="./common.dts;../projects/corsola/interrupts_kingler.dts;../projects/corsola/cbi_steelix.dts;../projects/corsola/gpio_steelix.dts"
+    extra_configs:
+      - CONFIG_TEST_STEELIX_RUSTY=y
+      - CONFIG_TEST_FORM_FACTOR_CONVERTIBLE=y
+  kingler.rusty:
+    extra_args: DTC_OVERLAY_FILE="./common.dts;../projects/corsola/interrupts_kingler.dts;../projects/corsola/cbi_steelix.dts;../projects/corsola/gpio_steelix.dts"
+    extra_configs:
+      - CONFIG_TEST_STEELIX_RUSTY=y
+      - CONFIG_TEST_FORM_FACTOR_CLAMSHELL=y
+  kingler.db_detect_typec:
+    extra_args: DTC_OVERLAY_FILE="./common.dts;../projects/corsola/interrupts_kingler.dts;../projects/corsola/gpio_steelix.dts;"
+    extra_configs:
+      - CONFIG_TEST_DB_DETECT_TYPEC=y
+      - CONFIG_VARIANT_CORSOLA_DB_DETECTION=y
+  kingler.db_detect_hdmi:
+    extra_args: DTC_OVERLAY_FILE="./common.dts;../projects/corsola/interrupts_kingler.dts;../projects/corsola/gpio_steelix.dts"
+    extra_configs:
+      - CONFIG_TEST_DB_DETECT_HDMI=y
+      - CONFIG_VARIANT_CORSOLA_DB_DETECTION=y
+  kingler.db_detect_none:
+    extra_args: DTC_OVERLAY_FILE="./common.dts;../projects/corsola/interrupts_kingler.dts;../projects/corsola/cbi_steelix.dts;../projects/corsola/gpio_steelix.dts"
+    extra_configs:
+      - CONFIG_TEST_DB_DETECT_NONE=y
+      - CONFIG_VARIANT_CORSOLA_DB_DETECTION=y
diff --git a/zephyr/test/krabby/CMakeLists.txt b/zephyr/test/krabby/CMakeLists.txt
new file mode 100644
index 0000000000..eba91a7be4
--- /dev/null
+++ b/zephyr/test/krabby/CMakeLists.txt
@@ -0,0 +1,14 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(krabby)
+
+zephyr_include_directories("${PLATFORM_EC}/zephyr/projects/corsola/include")
+
+target_sources(app PRIVATE
+	src/charger_workaround.c
+	src/stubs.c
+	${PLATFORM_EC}/zephyr/projects/corsola/src/krabby/charger_workaround.c)
diff --git a/zephyr/test/krabby/README.md b/zephyr/test/krabby/README.md
new file mode 100644
index 0000000000..8262d85fcc
--- /dev/null
+++ b/zephyr/test/krabby/README.md
@@ -0,0 +1,3 @@
+Tests for board specific code under `zephyr/projects/corsola/src/krabby`.
+
+Run with ./twister -T zephyr/test/krabby
diff --git a/zephyr/test/krabby/common.dts b/zephyr/test/krabby/common.dts
new file mode 100644
index 0000000000..d9f1a4f463
--- /dev/null
+++ b/zephyr/test/krabby/common.dts
@@ -0,0 +1,70 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <it8xxx2_emul.dts>
+
+/ {
+	pinctrl: pinctrl {
+		compatible = "ite,it8xxx2-pinctrl";
+		status = "disabled";
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		i2c_charger: charger {
+			i2c-port = <&i2c_ctrl0>;
+			enum-names = "I2C_PORT_CHARGER",
+				"I2C_PORT_BATTERY";
+		};
+	};
+
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port0@0 {
+			compatible = "named-usbc-port";
+			status = "okay";
+			reg = <0>;
+			chg = <&charger>;
+			tcpc = <&tcpci_emul>;
+		};
+	};
+
+	batteries {
+		default_battery: lgc_ac17a8m {
+			compatible = "lgc,ac17a8m", "battery-smart";
+		};
+	};
+};
+
+&i2c_ctrl0 {
+	status="okay";
+
+	charger: rt9490@53 {
+		compatible = "zephyr,rt9490-emul";
+		status = "okay";
+		reg = <0x53>;
+	};
+
+	battery: sb@b {
+		compatible = "zephyr,smart-battery";
+		reg = <0xb>;
+		cycle-count = <99>;
+		version = "BATTERY_SPEC_VER_1_1_WITH_PEC";
+		/* Real battery voltages are multiples of 4.4V. */
+		desired-charg-volt = <5000>;
+		desired-charg-cur = <1000>;
+		mf-name = "LGC";
+		dev-name = "AC17A8M";
+	};
+
+	tcpci_emul: tcpci_emul@82 {
+		compatible = "cros,tcpci-generic-emul";
+		status = "okay";
+		reg = <0x82>;
+	};
+};
diff --git a/zephyr/test/krabby/pinctrl.dts b/zephyr/test/krabby/pinctrl.dts
new file mode 100644
index 0000000000..9d01591238
--- /dev/null
+++ b/zephyr/test/krabby/pinctrl.dts
@@ -0,0 +1,7 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* remove pinctrl to avoid pull in too many unwanted dependency */
+/delete-node/ &pinctrl;
diff --git a/zephyr/test/krabby/prj.conf b/zephyr/test/krabby/prj.conf
new file mode 100644
index 0000000000..25bc89c33a
--- /dev/null
+++ b/zephyr/test/krabby/prj.conf
@@ -0,0 +1,36 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_ZTEST=y
+CONFIG_ZTEST_ASSERT_VERBOSE=1
+CONFIG_ZTEST_NEW_API=y
+
+CONFIG_ASSERT=y
+CONFIG_CROS_EC=y
+CONFIG_EMUL=y
+CONFIG_EMUL_RT9490=y
+CONFIG_EMUL_SMART_BATTERY=y
+CONFIG_EMUL_TCPCI=y
+CONFIG_I2C=y
+CONFIG_I2C_EMUL=y
+CONFIG_SHIMMED_TASKS=y
+
+CONFIG_PLATFORM_EC=y
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
+CONFIG_PLATFORM_EC_BATTERY=y
+CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y
+CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO=y
+CONFIG_PLATFORM_EC_CHARGER=y
+CONFIG_PLATFORM_EC_CHARGER_RT9490=y
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=20
+CONFIG_PLATFORM_EC_CHARGE_MANAGER=n
+CONFIG_PLATFORM_EC_HOOKS=y
+CONFIG_PLATFORM_EC_HOSTCMD=y
+CONFIG_PLATFORM_EC_LID_SWITCH=n
+CONFIG_PLATFORM_EC_SWITCH=n
+CONFIG_PLATFORM_EC_USBC=n
+CONFIG_PLATFORM_EC_USB_CHARGER=n
+CONFIG_PLATFORM_EC_USB_POWER_DELIVERY=n
+CONFIG_PLATFORM_EC_VBOOT_HASH=n
diff --git a/zephyr/test/krabby/src/charger_workaround.c b/zephyr/test/krabby/src/charger_workaround.c
new file mode 100644
index 0000000000..97aa4328c8
--- /dev/null
+++ b/zephyr/test/krabby/src/charger_workaround.c
@@ -0,0 +1,98 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/emul.h>
+#include <zephyr/fff.h>
+#include <zephyr/ztest.h>
+
+#include "charger.h"
+#include "driver/charger/rt9490.h"
+#include "emul/emul_rt9490.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "system.h"
+
+DEFINE_FFF_GLOBALS;
+
+FAKE_VALUE_FUNC(int, board_get_version);
+
+const struct emul *emul = EMUL_DT_GET(DT_NODELABEL(charger));
+
+static bool ibus_adc_workaround_called(void)
+{
+	return rt9490_emul_peek_reg(emul, 0x52) == 0xC4;
+}
+
+static bool i2c_speed_workaround_called(void)
+{
+	return rt9490_emul_peek_reg(emul, 0x71) == 0x22;
+}
+
+static bool eoc_deglitch_workaround_called(void)
+{
+	return !(rt9490_emul_peek_reg(emul, RT9490_REG_ADD_CTRL0) &
+		 RT9490_TD_EOC);
+}
+
+static bool disable_safety_timer_called(void)
+{
+	return rt9490_emul_peek_reg(emul, RT9490_REG_SAFETY_TMR_CTRL) ==
+	       (RT9490_EN_TRICHG_TMR | RT9490_EN_PRECHG_TMR |
+		RT9490_EN_FASTCHG_TMR);
+}
+
+ZTEST(charger_workaround, test_board_version_0)
+{
+	board_get_version_fake.return_val = 0;
+
+	hook_notify(HOOK_INIT);
+	zassert_true(ibus_adc_workaround_called(), NULL);
+	zassert_true(i2c_speed_workaround_called(), NULL);
+	zassert_false(eoc_deglitch_workaround_called(), NULL);
+	zassert_true(disable_safety_timer_called(), NULL);
+}
+
+ZTEST(charger_workaround, test_board_version_1)
+{
+	board_get_version_fake.return_val = 1;
+
+	hook_notify(HOOK_INIT);
+	zassert_false(ibus_adc_workaround_called(), NULL);
+	zassert_true(i2c_speed_workaround_called(), NULL);
+	zassert_true(eoc_deglitch_workaround_called(), NULL);
+	zassert_true(disable_safety_timer_called(), NULL);
+}
+
+ZTEST(charger_workaround, test_board_version_2)
+{
+	board_get_version_fake.return_val = 2;
+
+	hook_notify(HOOK_INIT);
+	zassert_false(ibus_adc_workaround_called(), NULL);
+	zassert_true(i2c_speed_workaround_called(), NULL);
+	zassert_false(eoc_deglitch_workaround_called(), NULL);
+	zassert_false(disable_safety_timer_called(), NULL);
+}
+
+ZTEST(charger_workaround, test_board_version_3)
+{
+	board_get_version_fake.return_val = 3;
+
+	hook_notify(HOOK_INIT);
+	zassert_false(ibus_adc_workaround_called(), NULL);
+	zassert_false(i2c_speed_workaround_called(), NULL);
+	zassert_false(eoc_deglitch_workaround_called(), NULL);
+	zassert_false(disable_safety_timer_called(), NULL);
+}
+
+static void charge_workaround_before(void *fixture)
+{
+	RESET_FAKE(board_get_version);
+	rt9490_emul_reset_regs(emul);
+}
+
+ZTEST_SUITE(charger_workaround, NULL, NULL, charge_workaround_before, NULL,
+	    NULL);
diff --git a/zephyr/test/krabby/src/stubs.c b/zephyr/test/krabby/src/stubs.c
new file mode 100644
index 0000000000..b6cc0c5368
--- /dev/null
+++ b/zephyr/test/krabby/src/stubs.c
@@ -0,0 +1,29 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_ramp.h"
+#include "charge_state.h"
+
+int board_set_active_charge_port(int port)
+{
+	return 0;
+}
+
+int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
+{
+	return 0;
+}
+
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
+{
+}
+
+const struct batt_params *charger_current_battery_params(void)
+{
+	static const struct batt_params params = {};
+
+	return &params;
+}
diff --git a/zephyr/test/krabby/testcase.yaml b/zephyr/test/krabby/testcase.yaml
new file mode 100644
index 0000000000..c8cf0e070b
--- /dev/null
+++ b/zephyr/test/krabby/testcase.yaml
@@ -0,0 +1,9 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+common:
+  platform_allow: native_posix
+tests:
+  krabby.default:
+    extra_args: DTC_OVERLAY_FILE="common.dts;../projects/corsola/interrupts_krabby.dts;../projects/corsola/gpio_krabby.dts;pinctrl.dts"
diff --git a/zephyr/test/math/BUILD.py b/zephyr/test/math/BUILD.py
deleted file mode 100644
index 8f6b28ce1a..0000000000
--- a/zephyr/test/math/BUILD.py
+++ /dev/null
@@ -1,12 +0,0 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-"""Register zmake project for math tests."""
-
-register_host_test(
-    "math_fixed", kconfig_files=[here / "prj.conf", here / "fixed_point.conf"]
-)
-register_host_test(
-    "math_float", kconfig_files=[here / "prj.conf", here / "floating_point.conf"]
-)
diff --git a/zephyr/test/math/CMakeLists.txt b/zephyr/test/math/CMakeLists.txt
index e90ce4cf8c..57fe7e389f 100644
--- a/zephyr/test/math/CMakeLists.txt
+++ b/zephyr/test/math/CMakeLists.txt
@@ -1,14 +1,11 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 cmake_minimum_required(VERSION 3.13.1)
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
 project(math)
 
-zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}/include")
-zephyr_include_directories("${PLATFORM_EC}/include")
-
 target_sources(app PRIVATE ${PLATFORM_EC}/common/math_util.c)
 
 target_sources(
diff --git a/zephyr/test/math/boards/native_posix.overlay b/zephyr/test/math/boards/native_posix.overlay
new file mode 120000
index 0000000000..7b75ea9967
--- /dev/null
+++ b/zephyr/test/math/boards/native_posix.overlay
@@ -0,0 +1 @@
+../../../dts/board-overlays/native_posix.dts
\ No newline at end of file
diff --git a/zephyr/test/math/fixed_point.conf b/zephyr/test/math/fixed_point.conf
index 5274cb2287..c1ddcc0911 100644
--- a/zephyr/test/math/fixed_point.conf
+++ b/zephyr/test/math/fixed_point.conf
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/test/math/floating_point.conf b/zephyr/test/math/floating_point.conf
index ce8f17011d..c6b8f58176 100644
--- a/zephyr/test/math/floating_point.conf
+++ b/zephyr/test/math/floating_point.conf
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/test/math/prj.conf b/zephyr/test/math/prj.conf
index d1592a2932..7c5ef483a2 100644
--- a/zephyr/test/math/prj.conf
+++ b/zephyr/test/math/prj.conf
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/test/math/src/fixed_point_int_sqrtf.c b/zephyr/test/math/src/fixed_point_int_sqrtf.c
index d8360ec189..163c36c26b 100644
--- a/zephyr/test/math/src/fixed_point_int_sqrtf.c
+++ b/zephyr/test/math/src/fixed_point_int_sqrtf.c
@@ -1,9 +1,9 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <ztest.h>
+#include <zephyr/ztest.h>
 
 #include "math.h"
 #include "math_util.h"
diff --git a/zephyr/test/math/src/mask.c b/zephyr/test/math/src/mask.c
index 9ced211a88..5e690c9653 100644
--- a/zephyr/test/math/src/mask.c
+++ b/zephyr/test/math/src/mask.c
@@ -1,10 +1,10 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include <inttypes.h>
-#include <ztest.h>
+#include <zephyr/ztest.h>
 
 #include "math.h"
 #include "math_util.h"
diff --git a/zephyr/test/math/src/math_util.c b/zephyr/test/math/src/math_util.c
index 901c3a6cc6..d3bd2c6fb6 100644
--- a/zephyr/test/math/src/math_util.c
+++ b/zephyr/test/math/src/math_util.c
@@ -1,12 +1,14 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <ztest.h>
+#include <zephyr/ztest.h>
 
+#include "common.h"
 #include "math.h"
 #include "math_util.h"
+#include "builtin/stdio.h"
 
 ZTEST_USER(math, arc_cos__x_below_range)
 {
@@ -39,3 +41,30 @@ ZTEST_USER(math, fp_sqrtf)
 	zassert_within(fp_sqrtf(FLOAT_TO_FP(15)), FLOAT_TO_FP(3.872983),
 		       FLOAT_TO_FP(0.001), NULL);
 }
+
+ZTEST_USER(math, print_ints)
+{
+	char buffer[10];
+
+	/* Fixed point. */
+	zassert_true(crec_snprintf(buffer, sizeof(buffer), "%.5d", 123) > 0,
+		     NULL);
+	zassert_equal(0, strcmp(buffer, "0.00123"), "got '%s'", buffer);
+	zassert_true(crec_snprintf(buffer, sizeof(buffer), "%2.1d", 123) > 0,
+		     NULL);
+	zassert_equal(0, strcmp(buffer, "12.3"), "got '%s'", buffer);
+
+	/* Precision or width larger than buffer should fail. */
+	zassert_equal(-EC_ERROR_OVERFLOW, crec_snprintf(buffer, 4, "%5d", 123),
+		      NULL);
+	zassert_equal(0, strcmp(buffer, "  1"), "got '%s'", buffer);
+	zassert_equal(-EC_ERROR_OVERFLOW, crec_snprintf(buffer, 4, "%10d", 123),
+		      NULL);
+	zassert_equal(0, strcmp(buffer, "   "), "got '%s'", buffer);
+	zassert_equal(-EC_ERROR_OVERFLOW,
+		      crec_snprintf(buffer, 4, "%-10d", 123), NULL);
+	zassert_equal(0, strcmp(buffer, "123"), "got '%s'", buffer);
+	zassert_equal(-EC_ERROR_OVERFLOW,
+		      crec_snprintf(buffer, 4, "%.10d", 123), NULL);
+	zassert_equal(0, strcmp(buffer, "0.0"), "got '%s'", buffer);
+}
diff --git a/zephyr/test/math/src/suite.c b/zephyr/test/math/src/suite.c
index 75b8e84bde..95da93b113 100644
--- a/zephyr/test/math/src/suite.c
+++ b/zephyr/test/math/src/suite.c
@@ -1,8 +1,8 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <ztest.h>
+#include <zephyr/ztest.h>
 
 ZTEST_SUITE(math, NULL, NULL, NULL, NULL, NULL);
diff --git a/zephyr/test/math/src/vector.c b/zephyr/test/math/src/vector.c
index 2e8ca52c5d..e79a350a92 100644
--- a/zephyr/test/math/src/vector.c
+++ b/zephyr/test/math/src/vector.c
@@ -1,9 +1,9 @@
-/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+/* Copyright 2022 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
-#include <ztest.h>
+#include <zephyr/ztest.h>
 
 #include "math.h"
 #include "math_util.h"
diff --git a/zephyr/test/math/testcase.yaml b/zephyr/test/math/testcase.yaml
new file mode 100644
index 0000000000..cd33e70553
--- /dev/null
+++ b/zephyr/test/math/testcase.yaml
@@ -0,0 +1,7 @@
+common:
+  platform_allow: native_posix
+tests:
+  util.math.fixed_point:
+    extra_args: OVERLAY_CONFIG=./fixed_point.conf
+  util.math.floating_point:
+    extra_args: OVERLAY_CONFIG=./floating_point.conf
diff --git a/zephyr/test/system/BUILD.py b/zephyr/test/system/BUILD.py
deleted file mode 100644
index b9f14c2fcf..0000000000
--- a/zephyr/test/system/BUILD.py
+++ /dev/null
@@ -1,7 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-"""Register zmake project for system test."""
-
-register_host_test("system", dts_overlays=["overlay.dts"])
diff --git a/zephyr/test/system_common/CMakeLists.txt b/zephyr/test/system_common/CMakeLists.txt
new file mode 100644
index 0000000000..05938b2ec6
--- /dev/null
+++ b/zephyr/test/system_common/CMakeLists.txt
@@ -0,0 +1,10 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(system_common_test)
+
+FILE(GLOB test_sources src/*.c)
+target_sources(app PRIVATE ${test_sources})
diff --git a/zephyr/test/system_common/boards/native_posix.overlay b/zephyr/test/system_common/boards/native_posix.overlay
new file mode 100644
index 0000000000..c6325f6ecc
--- /dev/null
+++ b/zephyr/test/system_common/boards/native_posix.overlay
@@ -0,0 +1,9 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <board-overlays/native_posix.dts>
+
+/ {
+};
diff --git a/zephyr/test/system_common/prj.conf b/zephyr/test/system_common/prj.conf
new file mode 100644
index 0000000000..ebc7c64321
--- /dev/null
+++ b/zephyr/test/system_common/prj.conf
@@ -0,0 +1,18 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_ZTEST=y
+CONFIG_ZTEST_NEW_API=y
+CONFIG_CROS_EC=y
+CONFIG_LOG=y
+
+CONFIG_PLATFORM_EC_CROS_FWID_VERSION=y
+CONFIG_PLATFORM_EC=y
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
+CONFIG_PLATFORM_EC_HOSTCMD=y
+CONFIG_PLATFORM_EC_LID_SWITCH=n
+CONFIG_PLATFORM_EC_PANIC=n
+CONFIG_PLATFORM_EC_SWITCH=n
+CONFIG_PLATFORM_EC_VBOOT_HASH=n
+CONFIG_SHIMMED_TASKS=y
diff --git a/zephyr/test/system_common/src/build_info.c b/zephyr/test/system_common/src/build_info.c
new file mode 100644
index 0000000000..7983c1f0a4
--- /dev/null
+++ b/zephyr/test/system_common/src/build_info.c
@@ -0,0 +1,56 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/fff.h>
+#include <zephyr/ztest_assert.h>
+#include <zephyr/ztest_test_new.h>
+
+#include "host_command.h"
+#include "system.h"
+
+ZTEST_SUITE(host_cmd_get_build_info, NULL, NULL, NULL, NULL, NULL);
+
+FAKE_VALUE_FUNC(const char *, system_get_build_info);
+
+ZTEST(host_cmd_get_build_info, test_get_build_info)
+{
+	int ret;
+	char resp[1024];
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_RESPONSE(EC_CMD_GET_BUILD_INFO, 0, resp);
+
+	RESET_FAKE(system_get_build_info);
+	system_get_build_info_fake.return_val = "i-am-a-version";
+
+	ret = host_command_process(&args);
+
+	zassert_equal(ret, EC_SUCCESS, "Unexpected return value: %d", ret);
+	zassert_equal(strcmp(resp, "i-am-a-version"), 0,
+		      "Unexpected response: %s", resp);
+	zassert_equal(system_get_build_info_fake.call_count, 1,
+		      "Unexpected call count: %d",
+		      system_get_build_info_fake.call_count);
+}
+
+ZTEST(host_cmd_get_build_info, test_get_build_info_truncated)
+{
+	int ret;
+	char resp[8];
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_RESPONSE(EC_CMD_GET_BUILD_INFO, 0, resp);
+
+	RESET_FAKE(system_get_build_info);
+	system_get_build_info_fake.return_val = "i-am-a-long-version";
+
+	ret = host_command_process(&args);
+
+	zassert_equal(ret, EC_SUCCESS, "Unexpected return value: %d", ret);
+	zassert_equal(strcmp(resp, "i-am-a-"), 0, "Unexpected response: %s",
+		      resp);
+	zassert_equal(system_get_build_info_fake.call_count, 1,
+		      "Unexpected call count: %d",
+		      system_get_build_info_fake.call_count);
+}
diff --git a/zephyr/test/system_common/src/fff.c b/zephyr/test/system_common/src/fff.c
new file mode 100644
index 0000000000..3b10dc3706
--- /dev/null
+++ b/zephyr/test/system_common/src/fff.c
@@ -0,0 +1,8 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/fff.h>
+
+DEFINE_FFF_GLOBALS;
diff --git a/zephyr/test/system_common/src/get_version.c b/zephyr/test/system_common/src/get_version.c
new file mode 100644
index 0000000000..87a41bad58
--- /dev/null
+++ b/zephyr/test/system_common/src/get_version.c
@@ -0,0 +1,72 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/fff.h>
+#include <zephyr/ztest_assert.h>
+#include <zephyr/ztest_test_new.h>
+
+#include "host_command.h"
+#include "system.h"
+
+ZTEST_SUITE(host_cmd_get_version, NULL, NULL, NULL, NULL, NULL);
+
+__override const char *system_get_version(enum ec_image copy)
+{
+	switch (copy) {
+	case EC_IMAGE_RO:
+		return "version-ro";
+	case EC_IMAGE_RW:
+		return "version-rw";
+	default:
+		return "unknown";
+	}
+}
+
+ZTEST(host_cmd_get_version, test_get_version_v1)
+{
+	int ret;
+	struct ec_response_get_version_v1 r;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_RESPONSE(EC_CMD_GET_VERSION, 1, r);
+
+	ret = host_command_process(&args);
+
+	zassert_equal(ret, EC_SUCCESS, "Unexpected return value: %d", ret);
+
+	zassert_equal(strcmp(r.version_string_ro, "version-ro"), 0,
+		      "version_string_ro: %s", r.version_string_ro);
+	zassert_equal(args.response_size, sizeof(r), "response_size: %d",
+		      args.response_size);
+	zassert_equal(strcmp(r.version_string_rw, "version-rw"), 0,
+		      "version_string_rw: %s", r.version_string_rw);
+	zassert_equal(strcmp(r.cros_fwid_ro, "CROS_FWID_MISSING"), 0,
+		      "cros_fwid_ro: %s", r.cros_fwid_ro);
+	zassert_equal(strcmp(r.cros_fwid_rw, "CROS_FWID_MISSING"), 0,
+		      "cros_fwid_ro: %s", r.cros_fwid_rw);
+	zassert_equal(r.current_image, EC_IMAGE_UNKNOWN, "current_image: %s",
+		      r.current_image);
+}
+
+ZTEST(host_cmd_get_version, test_get_version_v0)
+{
+	int ret;
+	struct ec_response_get_version r;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_RESPONSE(EC_CMD_GET_VERSION, 0, r);
+
+	ret = host_command_process(&args);
+
+	zassert_equal(ret, EC_SUCCESS, "Unexpected return value: %d", ret);
+
+	zassert_equal(strcmp(r.version_string_ro, "version-ro"), 0,
+		      "version_string_ro: %s", r.version_string_ro);
+	zassert_equal(args.response_size, sizeof(r), "response_size: %d",
+		      args.response_size);
+	zassert_equal(strcmp(r.version_string_rw, "version-rw"), 0,
+		      "version_string_rw: %s", r.version_string_rw);
+	zassert_equal(r.current_image, EC_IMAGE_UNKNOWN, "current_image: %s",
+		      r.current_image);
+}
diff --git a/zephyr/test/system_common/src/reboot.c b/zephyr/test/system_common/src/reboot.c
new file mode 100644
index 0000000000..759b93d89f
--- /dev/null
+++ b/zephyr/test/system_common/src/reboot.c
@@ -0,0 +1,289 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/fff.h>
+#include <zephyr/ztest_assert.h>
+#include <zephyr/ztest_test_new.h>
+
+#include "host_command.h"
+#include "system.h"
+
+FAKE_VOID_FUNC(system_reset, int);
+FAKE_VOID_FUNC(system_hibernate, uint32_t, uint32_t);
+
+ZTEST_SUITE(console_cmd_reboot, NULL, NULL, NULL, NULL, NULL);
+
+ZTEST(console_cmd_reboot, test_reboot_valid)
+{
+	int ret;
+	int i;
+
+	struct {
+		char *cmd;
+		int expect_called;
+		int expect_flags;
+	} tests[] = {
+		{
+			.cmd = "reboot hard",
+			.expect_called = 1,
+			.expect_flags = SYSTEM_RESET_MANUALLY_TRIGGERED |
+					SYSTEM_RESET_HARD,
+		},
+		{
+			.cmd = "reboot cold",
+			.expect_called = 1,
+			.expect_flags = SYSTEM_RESET_MANUALLY_TRIGGERED |
+					SYSTEM_RESET_HARD,
+		},
+		{
+			.cmd = "reboot soft",
+			.expect_called = 1,
+			.expect_flags = SYSTEM_RESET_MANUALLY_TRIGGERED,
+		},
+		{
+			.cmd = "reboot ap-off",
+			.expect_called = 1,
+			.expect_flags = SYSTEM_RESET_MANUALLY_TRIGGERED |
+					SYSTEM_RESET_LEAVE_AP_OFF,
+		},
+		{
+			.cmd = "reboot ap-off-in-ro",
+			.expect_called = 1,
+			.expect_flags = SYSTEM_RESET_MANUALLY_TRIGGERED |
+					SYSTEM_RESET_LEAVE_AP_OFF |
+					SYSTEM_RESET_STAY_IN_RO,
+		},
+		{
+			.cmd = "reboot ro",
+			.expect_called = 1,
+			.expect_flags = SYSTEM_RESET_MANUALLY_TRIGGERED |
+					SYSTEM_RESET_STAY_IN_RO,
+		},
+		{
+			.cmd = "reboot cancel",
+			.expect_called = 0,
+			.expect_flags = 0,
+		},
+		{
+			.cmd = "reboot preserve",
+			.expect_called = 1,
+			.expect_flags = SYSTEM_RESET_MANUALLY_TRIGGERED |
+					SYSTEM_RESET_PRESERVE_FLAGS,
+		},
+		{
+			.cmd = "reboot wait-ext",
+			.expect_called = 1,
+			.expect_flags = SYSTEM_RESET_MANUALLY_TRIGGERED |
+					SYSTEM_RESET_WAIT_EXT,
+		},
+	};
+
+	for (i = 0; i < ARRAY_SIZE(tests); i++) {
+		char *cmd = tests[i].cmd;
+
+		RESET_FAKE(system_reset);
+		RESET_FAKE(system_hibernate);
+
+		ret = shell_execute_cmd(get_ec_shell(), cmd);
+
+		zassert_equal(ret, EC_SUCCESS,
+			      "Unexpected return value for '%s': %d", cmd, ret);
+		zassert_equal(system_reset_fake.call_count,
+			      tests[i].expect_called,
+			      "Unexpected call count for '%s': %d", cmd,
+			      system_reset_fake.call_count);
+		zassert_equal(system_reset_fake.arg0_history[0],
+			      tests[i].expect_flags,
+			      "Unexpected flags for '%s': %x", cmd,
+			      system_reset_fake.arg0_history[0]);
+	}
+}
+
+ZTEST(console_cmd_reboot, test_reboot_invalid)
+{
+	int ret;
+
+	ret = shell_execute_cmd(get_ec_shell(), "reboot i-am-not-an-argument");
+
+	zassert_equal(ret, EC_ERROR_PARAM1, "invalid return value: %d", ret);
+	zassert_equal(system_reset_fake.call_count, 0,
+		      "Unexpected call count: %d",
+		      system_reset_fake.call_count);
+}
+
+ZTEST_SUITE(host_cmd_reboot, NULL, NULL, NULL, NULL, NULL);
+
+ZTEST(host_cmd_reboot, test_reboot)
+{
+	int ret;
+	int i;
+	struct ec_params_reboot_ec p;
+	struct host_cmd_handler_args args =
+		BUILD_HOST_COMMAND_PARAMS(EC_CMD_REBOOT_EC, 0, p);
+	int reboot_at_shutdown;
+
+	struct {
+		uint8_t cmd;
+		uint8_t flags;
+		int expect_return;
+		int expect_reboot_at_shutdown;
+		int expect_reset_called;
+		int expect_reset_flags;
+		int expect_hibernate_called;
+	} tests[] = {
+		{
+			.cmd = EC_REBOOT_CANCEL,
+			.flags = 0,
+			.expect_return = EC_RES_SUCCESS,
+			.expect_reboot_at_shutdown = EC_REBOOT_CANCEL,
+			.expect_reset_called = 0,
+			.expect_reset_flags = 0,
+			.expect_hibernate_called = 0,
+		},
+		{
+			.cmd = EC_REBOOT_COLD,
+			.flags = EC_REBOOT_FLAG_SWITCH_RW_SLOT,
+			.expect_return = EC_RES_INVALID_PARAM,
+			.expect_reboot_at_shutdown = 0,
+			.expect_reset_called = 0,
+			.expect_reset_flags = 0,
+			.expect_hibernate_called = 0,
+		},
+		{
+			.cmd = 0xaa, /* cmd passed unmodified */
+			.flags = EC_REBOOT_FLAG_ON_AP_SHUTDOWN,
+			.expect_return = EC_RES_SUCCESS,
+			.expect_reboot_at_shutdown = 0xaa,
+			.expect_reset_called = 0,
+			.expect_reset_flags = 0,
+			.expect_hibernate_called = 0,
+		},
+		{
+			.cmd = 0x55, /* cmd passed unmodified */
+			.flags = EC_REBOOT_FLAG_ON_AP_SHUTDOWN,
+			.expect_return = EC_RES_SUCCESS,
+			.expect_reboot_at_shutdown = 0x55,
+			.expect_reset_called = 0,
+			.expect_reset_flags = 0,
+			.expect_hibernate_called = 0,
+		},
+		{
+			.cmd = EC_REBOOT_COLD,
+			.flags = 0,
+			.expect_return = EC_RES_ERROR,
+			.expect_reboot_at_shutdown = EC_REBOOT_CANCEL,
+			.expect_reset_called = 1,
+			.expect_reset_flags = SYSTEM_RESET_HARD,
+			.expect_hibernate_called = 0,
+		},
+		{
+			.cmd = EC_REBOOT_HIBERNATE,
+			.flags = 0,
+			.expect_return = EC_RES_ERROR,
+			.expect_reboot_at_shutdown = EC_REBOOT_CANCEL,
+			.expect_reset_called = 0,
+			.expect_reset_flags = 0,
+			.expect_hibernate_called = 1,
+		},
+		{
+			.cmd = EC_REBOOT_COLD_AP_OFF,
+			.flags = 0,
+			.expect_return = EC_RES_ERROR,
+			.expect_reboot_at_shutdown = EC_REBOOT_CANCEL,
+			.expect_reset_called = 1,
+			.expect_reset_flags = SYSTEM_RESET_HARD |
+					      SYSTEM_RESET_LEAVE_AP_OFF,
+			.expect_hibernate_called = 0,
+		},
+		{
+			.cmd = 0xff,
+			.flags = 0,
+			.expect_return = EC_RES_INVALID_PARAM,
+			.expect_reboot_at_shutdown = EC_REBOOT_CANCEL,
+			.expect_reset_called = 0,
+			.expect_reset_flags = 0,
+			.expect_hibernate_called = 0,
+		},
+	};
+
+	for (i = 0; i < ARRAY_SIZE(tests); i++) {
+		p.cmd = tests[i].cmd;
+		p.flags = tests[i].flags;
+
+		RESET_FAKE(system_reset);
+		RESET_FAKE(system_hibernate);
+
+		ret = host_command_process(&args);
+
+		zassert_equal(ret, tests[i].expect_return,
+			      "Unexpected return value (%d): %d", i, ret);
+		reboot_at_shutdown =
+			system_common_get_reset_reboot_at_shutdown();
+		zassert_equal(
+			reboot_at_shutdown, tests[i].expect_reboot_at_shutdown,
+			"Unexpected value for reboot_at_shutdown (%d): %d", i,
+			reboot_at_shutdown);
+		zassert_equal(system_reset_fake.call_count,
+			      tests[i].expect_reset_called,
+			      "Unexpected reset call count (%d): %d", i,
+			      system_reset_fake.call_count);
+		zassert_equal(system_reset_fake.arg0_history[0],
+			      tests[i].expect_reset_flags,
+			      "Unexpected flags (%d): %x", i,
+			      system_reset_fake.arg0_history[0]);
+		zassert_equal(system_hibernate_fake.call_count,
+			      tests[i].expect_hibernate_called,
+			      "Unexpected hibernate call count (%d): %d", i,
+			      system_hibernate_fake.call_count);
+	}
+}
+
+ZTEST_SUITE(console_cmd_hibernate, NULL, NULL, NULL, NULL, NULL);
+
+int chipset_in_state(int state_mask)
+{
+	return 0;
+}
+
+ZTEST(console_cmd_hibernate, test_hibernate_default)
+{
+	int ret;
+
+	RESET_FAKE(system_hibernate);
+
+	ret = shell_execute_cmd(get_ec_shell(), "hibernate");
+
+	zassert_equal(ret, EC_SUCCESS, "Unexpected return value: %d", ret);
+	zassert_equal(system_hibernate_fake.call_count, 1,
+		      "Unexpected hibernate call count: %d",
+		      system_hibernate_fake.call_count);
+	zassert_equal(system_hibernate_fake.arg0_history[0], 0,
+		      "Unexpected hibernate_secondst: %d",
+		      system_hibernate_fake.arg0_history[0]);
+	zassert_equal(system_hibernate_fake.arg1_history[0], 0,
+		      "Unexpected hibernate_secondst: %d",
+		      system_hibernate_fake.arg1_history[0]);
+}
+
+ZTEST(console_cmd_hibernate, test_hibernate_args)
+{
+	int ret;
+
+	RESET_FAKE(system_hibernate);
+
+	ret = shell_execute_cmd(get_ec_shell(), "hibernate 123 456");
+
+	zassert_equal(ret, EC_SUCCESS, "Unexpected return value: %d", ret);
+	zassert_equal(system_hibernate_fake.call_count, 1,
+		      "Unexpected hibernate call count: %d",
+		      system_hibernate_fake.call_count);
+	zassert_equal(system_hibernate_fake.arg0_history[0], 123,
+		      "Unexpected hibernate_secondst: %d",
+		      system_hibernate_fake.arg0_history[0]);
+	zassert_equal(system_hibernate_fake.arg1_history[0], 456,
+		      "Unexpected hibernate_secondst: %d",
+		      system_hibernate_fake.arg1_history[0]);
+}
diff --git a/zephyr/test/system_common/testcase.yaml b/zephyr/test/system_common/testcase.yaml
new file mode 100644
index 0000000000..d6977dbb6a
--- /dev/null
+++ b/zephyr/test/system_common/testcase.yaml
@@ -0,0 +1,4 @@
+common:
+  platform_allow: native_posix
+tests:
+  system.default: {}
diff --git a/zephyr/test/system/CMakeLists.txt b/zephyr/test/system_shim/CMakeLists.txt
index f91786841e..2f8b61cda8 100644
--- a/zephyr/test/system/CMakeLists.txt
+++ b/zephyr/test/system_shim/CMakeLists.txt
@@ -1,10 +1,10 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 cmake_minimum_required(VERSION 3.13.1)
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-project(system_test)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(system_shim_test)
 
 target_sources(app PRIVATE test_system.c
                            ${PLATFORM_EC}/zephyr/shim/src/system.c)
diff --git a/zephyr/test/system/overlay.dts b/zephyr/test/system_shim/boards/native_posix.overlay
index bba99a0b81..0bcda0f513 100644
--- a/zephyr/test/system/overlay.dts
+++ b/zephyr/test/system_shim/boards/native_posix.overlay
@@ -1,8 +1,10 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
+#include <board-overlays/native_posix.dts>
+
 / {
 	chosen {
 		cros-ec,bbram = &bbram;
@@ -10,7 +12,6 @@
 
 	bbram: test-bbram-dev {
 		compatible = "zephyr,bbram-emul";
-		label = "TEST_BBRAM_DEV";
 		size = <64>;
 	};
 
diff --git a/zephyr/test/system/prj.conf b/zephyr/test/system_shim/prj.conf
index 4b3055b39b..fa7bd9fc04 100644
--- a/zephyr/test/system/prj.conf
+++ b/zephyr/test/system_shim/prj.conf
@@ -1,8 +1,9 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 CONFIG_ZTEST=y
+CONFIG_ZTEST_NEW_API=y
 CONFIG_PLATFORM_EC=y
 CONFIG_CROS_EC=y
 CONFIG_LOG=y
diff --git a/zephyr/test/system/test_system.c b/zephyr/test/system_shim/test_system.c
index ce83a684d1..d8b92e9504 100644
--- a/zephyr/test/system/test_system.c
+++ b/zephyr/test/system_shim/test_system.c
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -6,7 +6,8 @@
 #include <zephyr/device.h>
 #include <zephyr/drivers/bbram.h>
 #include <zephyr/logging/log.h>
-#include <ztest.h>
+#include <zephyr/ztest_assert.h>
+#include <zephyr/ztest_test_new.h>
 
 #include "system.h"
 
@@ -20,7 +21,9 @@ LOG_MODULE_REGISTER(test);
 static char mock_data[64] =
 	"abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789!@";
 
-static void test_bbram_get(void)
+ZTEST_SUITE(system, NULL, NULL, NULL, NULL, NULL);
+
+ZTEST(system, test_bbram_get)
 {
 	const struct device *const bbram_dev =
 		DEVICE_DT_GET(DT_CHOSEN(cros_ec_bbram));
@@ -51,9 +54,3 @@ static void test_bbram_get(void)
 	zassert_mem_equal(output, mock_data + BBRAM_REGION_OFF(try_slot),
 			  BBRAM_REGION_SIZE(try_slot), NULL);
 }
-
-void test_main(void)
-{
-	ztest_test_suite(system, ztest_unit_test(test_bbram_get));
-	ztest_run_test_suite(system);
-}
diff --git a/zephyr/test/system_shim/testcase.yaml b/zephyr/test/system_shim/testcase.yaml
new file mode 100644
index 0000000000..85df1de33a
--- /dev/null
+++ b/zephyr/test/system_shim/testcase.yaml
@@ -0,0 +1,4 @@
+common:
+  platform_allow: native_posix
+tests:
+  system_shim.default: {}
diff --git a/zephyr/test/tasks/BUILD.py b/zephyr/test/tasks/BUILD.py
deleted file mode 100644
index 9280101836..0000000000
--- a/zephyr/test/tasks/BUILD.py
+++ /dev/null
@@ -1,7 +0,0 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-"""Register zmake project for tasks test."""
-
-register_host_test("tasks")
diff --git a/zephyr/test/tasks/CMakeLists.txt b/zephyr/test/tasks/CMakeLists.txt
index f5ea76e67e..b0b59e7c99 100644
--- a/zephyr/test/tasks/CMakeLists.txt
+++ b/zephyr/test/tasks/CMakeLists.txt
@@ -1,9 +1,9 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 cmake_minimum_required(VERSION 3.13.1)
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
 project(tasks)
 
 # Include the local test directory for shimmed_test_tasks.h
@@ -11,4 +11,4 @@ zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}")
 
 target_sources(app PRIVATE
 	main.c
-	"${CMAKE_CURRENT_SOURCE_DIR}/../../shim/src/tasks.c")
\ No newline at end of file
+	"${CMAKE_CURRENT_SOURCE_DIR}/../../shim/src/tasks.c")
diff --git a/zephyr/test/tasks/boards/native_posix.overlay b/zephyr/test/tasks/boards/native_posix.overlay
new file mode 100644
index 0000000000..2e36118442
--- /dev/null
+++ b/zephyr/test/tasks/boards/native_posix.overlay
@@ -0,0 +1,8 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <board-overlays/native_posix.dts>
+
+/* No additional nodes to the native_posix overlay */
diff --git a/zephyr/test/tasks/main.c b/zephyr/test/tasks/main.c
index ebf271d9b7..8bfe9eb602 100644
--- a/zephyr/test/tasks/main.c
+++ b/zephyr/test/tasks/main.c
@@ -1,11 +1,11 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #include <zephyr/kernel.h>
 #include <stdbool.h>
-#include <ztest.h>
+#include <zephyr/ztest.h>
 
 #include "ec_tasks.h"
 #include "task.h"
@@ -107,7 +107,6 @@ static void test_task_get_current(void)
 	run_test(&task_get_current1, &task_get_current2);
 }
 
-
 static void timeout1(void)
 {
 	const uint32_t start_ms = k_uptime_get();
@@ -201,7 +200,6 @@ static void test_event_delivered(void)
 	run_test(&event_delivered1, &event_delivered2);
 }
 
-
 static void event_mask_not_delivered1(void)
 {
 	task_set_event(TASK_ID_TASK_2, 0x007F);
@@ -226,7 +224,6 @@ static void test_event_mask_not_delivered(void)
 	run_test(&event_mask_not_delivered1, &event_mask_not_delivered2);
 }
 
-
 static void event_mask_extra1(void)
 {
 	k_sleep(K_SECONDS(1));
@@ -253,7 +250,6 @@ static void test_event_mask_extra(void)
 	run_test(&event_mask_extra1, &event_mask_extra2);
 }
 
-
 static void empty_set_mask1(void)
 {
 	k_sleep(K_SECONDS(1));
@@ -281,7 +277,6 @@ static void test_empty_set_mask(void)
 	run_test(&empty_set_mask1, &empty_set_mask2);
 }
 
-
 void test_main(void)
 {
 	/* Note that test_set_event_before_task_start calls start_ec_tasks */
diff --git a/zephyr/test/tasks/prj.conf b/zephyr/test/tasks/prj.conf
index 15af430451..6c8e2fbc90 100644
--- a/zephyr/test/tasks/prj.conf
+++ b/zephyr/test/tasks/prj.conf
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/test/tasks/shimmed_test_tasks.h b/zephyr/test/tasks/shimmed_test_tasks.h
index c040ed1bad..ebd1215446 100644
--- a/zephyr/test/tasks/shimmed_test_tasks.h
+++ b/zephyr/test/tasks/shimmed_test_tasks.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,7 +14,7 @@
 #define HAS_TASK_TASK_3 1
 
 /* Highest priority on bottom same as in platform/ec */
-#define CROS_EC_TASK_LIST \
+#define CROS_EC_TASK_LIST                            \
 	CROS_EC_TASK(TASK_1, task1_entry, 0, 512, 2) \
 	CROS_EC_TASK(TASK_2, task2_entry, 0, 512, 1) \
 	CROS_EC_TASK(TASK_3, task3_entry, 0, 512, 0)
diff --git a/zephyr/test/tasks/testcase.yaml b/zephyr/test/tasks/testcase.yaml
new file mode 100644
index 0000000000..a72199a14a
--- /dev/null
+++ b/zephyr/test/tasks/testcase.yaml
@@ -0,0 +1,8 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+common:
+  platform_allow: native_posix
+tests:
+  tasks.default: {}
diff --git a/zephyr/test/unblocked_terms.txt b/zephyr/test/unblocked_terms.txt
new file mode 100644
index 0000000000..cf2ed1052f
--- /dev/null
+++ b/zephyr/test/unblocked_terms.txt
@@ -0,0 +1,2 @@
+SHELL_BACKEND_DUMMY
+shell_dummy
diff --git a/zephyr/test/vboot_efs2/CMakeLists.txt b/zephyr/test/vboot_efs2/CMakeLists.txt
new file mode 100644
index 0000000000..c3343bcdd2
--- /dev/null
+++ b/zephyr/test/vboot_efs2/CMakeLists.txt
@@ -0,0 +1,10 @@
+# Copyright 2021 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+find_package(Zephyr REQUIRED HINTS "${ZEPHYR_BASE}")
+project(vboot_efs2)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
diff --git a/zephyr/test/vboot_efs2/boards/native_posix.overlay b/zephyr/test/vboot_efs2/boards/native_posix.overlay
new file mode 100644
index 0000000000..ced94c28b1
--- /dev/null
+++ b/zephyr/test/vboot_efs2/boards/native_posix.overlay
@@ -0,0 +1,132 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <board-overlays/native_posix.dts>
+#include <cros/binman.dtsi>
+
+/ {
+	chosen {
+		cros-ec,flash = &flash1;
+		cros-ec,flash-controller = &cros_flash;
+		zephyr,shell-uart = &test_uart;
+	};
+	aliases {
+		gpio-wp = &gpio_wp_l;
+	};
+	named-gpios {
+		compatible = "named-gpios";
+		ec_gsc_packet_mode {
+			gpios = <&gpio0 2 GPIO_OUTPUT_LOW>;
+			enum-name = "GPIO_PACKET_MODE_EN";
+		};
+		gpio_wp_l: wp_l {
+			gpios = <&gpio0 3 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
+		};
+		usb_c0_tcpc_int_odl: usb_c0_tcpc_int_odl {
+			gpios = <&gpio0 4 GPIO_INPUT>;
+		};
+		ec_batt_pres_odl {
+			gpios = <&gpio0 5 GPIO_INPUT>;
+			enum-name = "GPIO_BATT_PRES_ODL";
+		};
+	};
+	cros_flash: cros-flash {
+		compatible = "cros-ec,flash-emul";
+	};
+	flash1: flash@64000000 {
+		reg = <0x64000000 DT_SIZE_K(512)>;
+	};
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		named_i2c0: i2c0 {
+			i2c-port = <&i2c0>;
+			enum-names = "I2C_PORT_BATTERY",
+				"I2C_PORT_CHARGER";
+		};
+		named_i2c2: i2c2 {
+			i2c-port = <&i2c2>;
+			dynamic-speed;
+			enum-names = "I2C_PORT_USB_C0";
+		};
+	};
+	usbc {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port0@0 {
+			compatible = "named-usbc-port";
+			reg = <0>;
+			chg = <&isl923x_emul>;
+			tcpc = <&tcpci_emul>;
+		};
+	};
+	i2c2: i2c@500 {
+		status = "okay";
+		compatible = "zephyr,i2c-emul-controller";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x500 4>;
+
+		tcpci_emul: tcpci_emul@82 {
+			compatible = "cros,tcpci-generic-emul";
+			status = "okay";
+			reg = <0x82>;
+			alert_gpio = <&usb_c0_tcpc_int_odl>;
+		};
+	};
+	adc0: adc {
+		compatible = "zephyr,adc-emul";
+		nchannels = <6>;
+		ref-internal-mv = <3300>;
+		#io-channel-cells = <1>;
+		status = "okay";
+	};
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		adc_charger: charger {
+			enum-name = "ADC_TEMP_SENSOR_CHARGER";
+			io-channels = <&adc0 0>;
+		};
+	};
+	batteries {
+		default_battery: lgc_ac17a8m {
+			compatible = "lgc,ac17a8m", "battery-smart";
+		};
+	};
+	test_uart: uart@55556666 {
+		compatible = "vnd,serial";
+		reg = <0x55556666 0x1000>;
+		status = "okay";
+		buffer-size = <200>;
+	};
+};
+
+&gpio0 {
+	ngpios = <6>;
+};
+
+&i2c0 {
+	battery: sb@b {
+		compatible = "zephyr,smart-battery";
+		reg = <0xb>;
+		cycle-count = <99>;
+		version = "BATTERY_SPEC_VER_1_1_WITH_PEC";
+		/* Real battery voltages are multiples of 4.4V. */
+		desired-charg-volt = <5000>;
+		desired-charg-cur = <1000>;
+		mf-name = "LGC";
+		dev-name = "AC17A8M";
+	};
+
+	isl923x_emul: isl923x@9 {
+		compatible = "cros,isl923x-emul";
+		status = "okay";
+		reg = <0x9>;
+		battery = <&battery>;
+	};
+};
diff --git a/zephyr/test/vboot_efs2/prj.conf b/zephyr/test/vboot_efs2/prj.conf
new file mode 100644
index 0000000000..602bd22c65
--- /dev/null
+++ b/zephyr/test/vboot_efs2/prj.conf
@@ -0,0 +1,43 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_ADC=y
+CONFIG_ADC_EMUL=y
+CONFIG_CROS_EC=y
+CONFIG_EMUL_CROS_FLASH=y
+CONFIG_EMUL_SMART_BATTERY=y
+CONFIG_EMUL_TCPCI=y
+CONFIG_FLASH=y
+CONFIG_I2C=y
+CONFIG_I2C_EMUL=y
+CONFIG_PLATFORM_EC=y
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
+CONFIG_PLATFORM_EC_BATTERY=y
+CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y
+CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO=y
+CONFIG_PLATFORM_EC_BATTERY_SMART=y
+CONFIG_PLATFORM_EC_BC12_DETECT_PI3USB9201=y
+CONFIG_PLATFORM_EC_CHARGER_ISL9238=y
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=10
+CONFIG_PLATFORM_EC_CHARGE_RAMP_SW=y
+CONFIG_PLATFORM_EC_HOSTCMD=y
+CONFIG_PLATFORM_EC_SWITCH=n
+CONFIG_PLATFORM_EC_USBC=y
+CONFIG_PLATFORM_EC_USBC_PPC_SN5S330=y
+CONFIG_PLATFORM_EC_USB_CHARGER=y
+CONFIG_PLATFORM_EC_USB_PD_DISCHARGE=n
+CONFIG_PLATFORM_EC_USB_PD_TCPM_MUX=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_CHARGER=y
+CONFIG_PLATFORM_EC_VBOOT_EFS2=y
+CONFIG_PLATFORM_EC_VBOOT_HASH=y
+CONFIG_RING_BUFFER=y
+CONFIG_SERIAL=y
+CONFIG_SHELL_BACKEND_DUMMY=y
+CONFIG_SHELL_BACKEND_DUMMY_BUF_SIZE=1000
+CONFIG_SHELL_BACKEND_SERIAL=n
+CONFIG_SHIMMED_TASKS=y
+CONFIG_ZTEST=y
+CONFIG_ZTEST_NEW_API=y
diff --git a/zephyr/test/vboot_efs2/src/main.c b/zephyr/test/vboot_efs2/src/main.c
new file mode 100644
index 0000000000..1558fb75f0
--- /dev/null
+++ b/zephyr/test/vboot_efs2/src/main.c
@@ -0,0 +1,423 @@
+/* Copyright 2022 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "driver/bc12/pi3usb9201_public.h"
+#include "driver/tcpm/tcpci.h"
+#include "ec_app_main.h"
+#include "emul/emul_flash.h"
+#include "hooks.h"
+#include "ppc/sn5s330_public.h"
+#include "system_fake.h"
+#include "task.h"
+#include "usb_mux.h"
+#include "usbc_ppc.h"
+#include "vboot.h"
+
+#include "zephyr/devicetree.h"
+#include <stdint.h>
+
+#include <zephyr/drivers/gpio/gpio_emul.h>
+#include <zephyr/drivers/uart/serial_test.h>
+#include <zephyr/kernel.h>
+#include <zephyr/shell/shell_dummy.h>
+#include <zephyr/ztest_assert.h>
+#include <zephyr/ztest_test_new.h>
+
+#define SERIAL_BUFFER_SIZE DT_PROP(DT_NODELABEL(test_uart), buffer_size)
+
+static int show_power_shortage_called;
+void show_power_shortage(void)
+{
+	show_power_shortage_called++;
+}
+
+static int show_critical_error_called;
+void show_critical_error(void)
+{
+	show_critical_error_called++;
+}
+
+ZTEST(vboot_efs2, test_vboot_main_system_is_in_rw)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+	const char *outbuffer;
+	size_t buffer_size;
+
+	/* Set system_is_in_rw */
+	system_set_shrspi_image_copy(EC_IMAGE_RW);
+
+	shell_backend_dummy_clear_output(shell_zephyr);
+	vboot_main();
+
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+	zassert_equal(show_power_shortage_called, 1, NULL);
+
+	zassert_true(strstr(outbuffer, "VB Already in RW") != NULL,
+		     "Expected msg not in %s", outbuffer);
+
+	/* Verify some things we don't expect also. */
+	zassert_true(strstr(outbuffer, "VB Ping Cr50") == NULL,
+		     "Unexpected msg in %s", outbuffer);
+	zassert_true(strstr(outbuffer, "VB Exit") == NULL,
+		     "Unexpected msg in %s", outbuffer);
+	zassert_false(vboot_allow_usb_pd(), NULL);
+	zassert_equal(show_critical_error_called, 0, NULL);
+}
+
+ZTEST(vboot_efs2, test_vboot_main_system_is_manual_recovery)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+	const char *outbuffer;
+	size_t buffer_size;
+
+	system_enter_manual_recovery();
+
+	shell_backend_dummy_clear_output(shell_zephyr);
+	vboot_main();
+
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+	zassert_equal(show_power_shortage_called, 0, NULL);
+	zassert_true(strstr(outbuffer, "VB In recovery mode") != NULL,
+		     "Expected msg not in %s", outbuffer);
+
+	/* Verify some things we don't expect also. */
+	zassert_true(strstr(outbuffer, "VB Ping Cr50") == NULL,
+		     "Unexpected msg in %s", outbuffer);
+	zassert_true(strstr(outbuffer, "VB Exit") == NULL,
+		     "Unexpected msg in %s", outbuffer);
+	zassert_false(vboot_allow_usb_pd(), NULL);
+	zassert_equal(show_critical_error_called, 0, NULL);
+}
+
+ZTEST(vboot_efs2, test_vboot_main_stay_in_ro)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+	const char *outbuffer;
+	size_t buffer_size;
+
+	system_set_reset_flags(EC_RESET_FLAG_STAY_IN_RO);
+
+	shell_backend_dummy_clear_output(shell_zephyr);
+	vboot_main();
+
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+	zassert_equal(show_power_shortage_called, 0, NULL);
+
+	/* Verify some things we don't expect also. */
+	zassert_true(strstr(outbuffer, "VB In recovery mode") == NULL,
+		     "Expected msg not in %s", outbuffer);
+	zassert_true(strstr(outbuffer, "VB Ping Cr50") == NULL,
+		     "Unexpected msg in %s", outbuffer);
+	zassert_true(strstr(outbuffer, "VB Exit") == NULL,
+		     "Unexpected msg in %s", outbuffer);
+	zassert_false(vboot_allow_usb_pd(), NULL);
+	zassert_equal(show_critical_error_called, 0, NULL);
+}
+
+ZTEST(vboot_efs2, test_vboot_main_jump_timeout)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+	const char *outbuffer;
+	size_t buffer_size;
+
+	shell_backend_dummy_clear_output(shell_zephyr);
+	vboot_main();
+
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+	zassert_equal(show_critical_error_called, 1, NULL);
+
+	zassert_true(strstr(outbuffer, "VB Ping Cr50") != NULL,
+		     "Expected msg not in %s", outbuffer);
+	zassert_false(vboot_allow_usb_pd(), NULL);
+	zassert_equal(show_power_shortage_called, 0, NULL);
+}
+
+#define PACKET_MODE_GPIO DT_PATH(named_gpios, ec_gsc_packet_mode)
+
+static const struct device *uart_shell_dev =
+	DEVICE_DT_GET(DT_CHOSEN(zephyr_shell_uart));
+static const struct device *gpio_dev =
+	DEVICE_DT_GET(DT_GPIO_CTLR(PACKET_MODE_GPIO, gpios));
+
+static void reply_cr50_payload(const struct device *dev, void *user_data)
+{
+	if (gpio_emul_output_get(gpio_dev,
+				 DT_GPIO_PIN(PACKET_MODE_GPIO, gpios))) {
+		struct cr50_comm_request req;
+		uint32_t bytes_read;
+
+		bytes_read = serial_vnd_peek_out_data(
+			uart_shell_dev, (void *)&req, sizeof(req));
+		/* If ! valid cr50_comm_request header, read 1 byte. */
+		while (bytes_read == sizeof(req) &&
+		       req.magic != CR50_PACKET_MAGIC) {
+			/* Consume one byte and then peek again. */
+			serial_vnd_read_out_data(uart_shell_dev, NULL, 1);
+			bytes_read = serial_vnd_peek_out_data(
+				uart_shell_dev, (void *)&req, sizeof(req));
+		}
+		if (bytes_read == sizeof(req)) {
+			/* If we have a full packet, consume it, and reply
+			 * with whatever is in user_data which holds a cr50
+			 * reply.
+			 */
+			if (req.size + sizeof(req) <=
+			    serial_vnd_out_data_size_get(uart_shell_dev)) {
+				serial_vnd_read_out_data(uart_shell_dev, NULL,
+							 req.size +
+								 sizeof(req));
+				serial_vnd_queue_in_data(
+					uart_shell_dev, user_data,
+					sizeof(struct cr50_comm_response));
+			}
+		}
+	} else {
+		/* Packet mode is off, so just consume enough bytes from the out
+		 * buffer to clear it.
+		 */
+		serial_vnd_read_out_data(uart_shell_dev, NULL,
+					 SERIAL_BUFFER_SIZE);
+	}
+}
+
+ZTEST(vboot_efs2, test_vboot_main_jump_bad_payload)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+	const char *outbuffer;
+	size_t buffer_size;
+	struct cr50_comm_response resp = {
+		.error = CR50_COMM_ERR_BAD_PAYLOAD,
+	};
+
+	serial_vnd_set_callback(uart_shell_dev, reply_cr50_payload, &resp);
+
+	shell_backend_dummy_clear_output(shell_zephyr);
+	vboot_main();
+
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+
+	zassert_true(strstr(outbuffer, "VB Ping Cr50") != NULL,
+		     "Expected msg not in %s", outbuffer);
+	zassert_true(vboot_allow_usb_pd(), NULL);
+	zassert_equal(show_power_shortage_called, 0, NULL);
+	zassert_equal(show_critical_error_called, 0, NULL);
+}
+
+/* This hits the default case in verify_and_jump. */
+ZTEST(vboot_efs2, test_vboot_main_jump_bad_crc)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+	const char *outbuffer;
+	size_t buffer_size;
+	struct cr50_comm_response resp = {
+		.error = CR50_COMM_ERR_CRC,
+	};
+
+	serial_vnd_set_callback(uart_shell_dev, reply_cr50_payload, &resp);
+
+	shell_backend_dummy_clear_output(shell_zephyr);
+	vboot_main();
+
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+
+	zassert_true(strstr(outbuffer, "VB Ping Cr50") != NULL,
+		     "Expected msg not in %s", outbuffer);
+	zassert_true(strstr(outbuffer, "VB Failed to verify RW (0xec03)") !=
+			     NULL,
+		     "Expected msg not in %s", outbuffer);
+	zassert_false(vboot_allow_usb_pd(), NULL);
+	zassert_equal(show_power_shortage_called, 0, NULL);
+	zassert_equal(show_critical_error_called, 1, NULL);
+}
+
+ZTEST(vboot_efs2, test_vboot_main_vboot_get_rw_hash_fail)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+	const char *outbuffer;
+	size_t buffer_size;
+	struct ec_response_vboot_hash response;
+	struct ec_params_vboot_hash hash_start_params = {
+		.cmd = EC_VBOOT_HASH_START,
+		.hash_type = EC_VBOOT_HASH_TYPE_SHA256,
+		.offset = 0,
+		.size = 0x12345,
+	};
+	struct host_cmd_handler_args hash_start_args = BUILD_HOST_COMMAND(
+		EC_CMD_VBOOT_HASH, 0, response, hash_start_params);
+
+	shell_backend_dummy_clear_output(shell_zephyr);
+
+	zassert_ok(host_command_process(&hash_start_args), NULL);
+	vboot_main();
+
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+
+	zassert_true(strstr(outbuffer, "VB Ping Cr50") != NULL,
+		     "Expected msg not in %s", outbuffer);
+	zassert_true(strstr(outbuffer, "VB Failed to verify RW (0x6)") != NULL,
+		     "Expected msg not in %s", outbuffer);
+	zassert_false(vboot_allow_usb_pd(), NULL);
+	zassert_equal(show_power_shortage_called, 0, NULL);
+	zassert_equal(show_critical_error_called, 1, NULL);
+}
+
+ZTEST(vboot_efs2, test_vboot_main_jump_success)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+	const char *outbuffer;
+	size_t buffer_size;
+	struct cr50_comm_response resp = {
+		.error = CR50_COMM_SUCCESS,
+	};
+
+	serial_vnd_set_callback(uart_shell_dev, reply_cr50_payload, &resp);
+
+	shell_backend_dummy_clear_output(shell_zephyr);
+	vboot_main();
+
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+
+	zassert_true(strstr(outbuffer, "VB Ping Cr50") != NULL,
+		     "Expected msg not in %s", outbuffer);
+	zassert_false(vboot_allow_usb_pd(), NULL);
+	zassert_equal(show_power_shortage_called, 0, NULL);
+	zassert_equal(show_critical_error_called, 1, NULL);
+	zassert_equal(system_get_reset_flags(), 0, NULL);
+}
+
+ZTEST(vboot_efs2, test_shutdown_hook_in_rw)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+	const char *outbuffer;
+	size_t buffer_size;
+
+	/* Set system_is_in_rw */
+	system_set_shrspi_image_copy(EC_IMAGE_RW);
+
+	shell_backend_dummy_clear_output(shell_zephyr);
+	hook_notify(HOOK_CHIPSET_SHUTDOWN_COMPLETE);
+
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+
+	zassert_true(strstr(outbuffer, "VB hook_shutdown") != NULL,
+		     "Expected msg not in %s", outbuffer);
+	zassert_equal(system_get_reset_flags(), 0, NULL);
+
+	/* Verify some things we don't expect also. */
+	zassert_true(strstr(outbuffer, "VB Ping Cr50") == NULL,
+		     "Unexpected msg in %s", outbuffer);
+	zassert_false(vboot_allow_usb_pd(), NULL);
+	zassert_equal(show_critical_error_called, 0, NULL);
+	zassert_equal(show_power_shortage_called, 0, NULL);
+}
+
+ZTEST(vboot_efs2, test_shutdown_hook_in_ro)
+{
+	const struct shell *shell_zephyr = get_ec_shell();
+	const char *outbuffer;
+	size_t buffer_size;
+
+	/* Set system_is_in_rw */
+	system_set_shrspi_image_copy(EC_IMAGE_RO);
+
+	shell_backend_dummy_clear_output(shell_zephyr);
+	hook_notify(HOOK_CHIPSET_SHUTDOWN_COMPLETE);
+
+	outbuffer = shell_backend_dummy_get_output(shell_zephyr, &buffer_size);
+
+	zassert_true(strstr(outbuffer, "VB hook_shutdown") != NULL,
+		     "Expected msg not in %s", outbuffer);
+	zassert_true(strstr(outbuffer, "VB Ping Cr50") != NULL,
+		     "Expected msg not in %s", outbuffer);
+	zassert_equal(system_get_reset_flags(), EC_RESET_FLAG_AP_IDLE, NULL);
+	zassert_equal(show_critical_error_called, 1, NULL);
+
+	/* Verify some things we don't expect also. */
+	zassert_false(vboot_allow_usb_pd(), NULL);
+	zassert_equal(show_power_shortage_called, 0, NULL);
+}
+
+void *vboot_efs2_setup(void)
+{
+	/* Wait for the shell to start. */
+	k_sleep(K_MSEC(1));
+	zassert_equal(get_ec_shell()->ctx->state, SHELL_STATE_ACTIVE, NULL);
+
+	system_common_pre_init();
+
+	return NULL;
+}
+
+void vboot_efs2_cleanup(void *fixture)
+{
+	ARG_UNUSED(fixture);
+
+	system_set_shrspi_image_copy(EC_IMAGE_RO);
+	show_power_shortage_called = 0;
+	show_critical_error_called = 0;
+	system_exit_manual_recovery();
+	system_clear_reset_flags(EC_RESET_FLAG_STAY_IN_RO | EC_RESET_FLAG_EFS |
+				 EC_RESET_FLAG_AP_IDLE);
+	vboot_disable_pd();
+	serial_vnd_set_callback(uart_shell_dev, NULL, NULL);
+	serial_vnd_read_out_data(uart_shell_dev, NULL, SERIAL_BUFFER_SIZE);
+}
+
+ZTEST_SUITE(vboot_efs2, NULL, vboot_efs2_setup, NULL, vboot_efs2_cleanup, NULL);
+
+int board_set_active_charge_port(int port)
+{
+	return EC_ERROR_INVAL;
+}
+
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+			    int charge_mv)
+{
+}
+
+void pd_power_supply_reset(int port)
+{
+}
+
+int pd_check_vconn_swap(int port)
+{
+	return 0;
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	return EC_SUCCESS;
+}
+
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_COUNT };
+
+/* BC1.2 charger detect configuration */
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+};
+
+struct usb_mux_chain usb_muxes[] = {
+	[USBC_PORT_C0] = {
+		.mux = &(struct usb_mux) {
+			.usb_port = USBC_PORT_C0,
+			.driver = &tcpci_tcpm_usb_mux_driver,
+			.i2c_port = I2C_PORT_USB_C0,
+			.i2c_addr_flags = DT_REG_ADDR(DT_NODELABEL(tcpci_emul)),
+		},
+	},
+};
+
+/* USBC PPC configuration */
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_USB_C0,
+		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
+		.drv = &sn5s330_drv,
+	},
+};
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
diff --git a/zephyr/test/vboot_efs2/testcase.yaml b/zephyr/test/vboot_efs2/testcase.yaml
new file mode 100644
index 0000000000..59716f3fb2
--- /dev/null
+++ b/zephyr/test/vboot_efs2/testcase.yaml
@@ -0,0 +1,8 @@
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+common:
+  platform_allow: native_posix
+tests:
+  vboot_efs2.default:
+    timeout: 120
diff --git a/zephyr/zmake/.pylintrc b/zephyr/zmake/.pylintrc
index a33a1fde1c..a0f9ac790b 100644
--- a/zephyr/zmake/.pylintrc
+++ b/zephyr/zmake/.pylintrc
@@ -1,15 +1,24 @@
 [MASTER]
 init-hook='import sys; sys.path.extend(["zephyr/zmake"])'
 
+[BASIC]
+good-names=
+    e,
+
+# cros lint doesn't inherit the pylintrc from the parent dir.
+# These settings are copied from platform/ec/pylintrc
 [MESSAGES CONTROL]
 
-disable=bad-continuation,bad-whitespace,format,fixme,wrong-import-order
+disable=
+    bad-continuation,
+    bad-whitespace,
+    # These have nothing to do with black, they are just annoying
+    fixme,
+    too-many-arguments,
+    too-many-statements,
+    too-many-branches,
+    too-many-locals
 
 [format]
 
-max-line-length=88
 string-quote=double
-
-[BASIC]
-good-names=
-    e,
diff --git a/zephyr/zmake/README.md b/zephyr/zmake/README.md
index 6e2690959b..e424b66ca0 100644
--- a/zephyr/zmake/README.md
+++ b/zephyr/zmake/README.md
@@ -35,7 +35,7 @@ Chromium OS's meta-build tool for Zephyr
 
 ### zmake configure
 
-**Usage:** `zmake configure [-h] [-t TOOLCHAIN] [--bringup] [--clobber] [--allow-warnings] [-B BUILD_DIR] [-c] [--extra-cflags EXTRA_CFLAGS] (-a | --host-tests-only | project_name [project_name ...])`
+**Usage:** `zmake configure [-h] [-t TOOLCHAIN] [--bringup] [--clobber] [--static] [--save-temps] [--allow-warnings] [-B BUILD_DIR] [-c] [--extra-cflags EXTRA_CFLAGS] [--delete-intermediates] (-a | project_name [project_name ...])`
 
 #### Positional Arguments
 
@@ -51,16 +51,18 @@ Chromium OS's meta-build tool for Zephyr
 | `-t TOOLCHAIN`, `--toolchain TOOLCHAIN` | Name of toolchain to use |
 | `--bringup` | Enable bringup debugging features |
 | `--clobber` | Delete existing build directories, even if configuration is unchanged |
+| `--static` | Generate static version information for reproducible builds |
+| `--save-temps` | Save the temporary files containing preprocessor output |
 | `--allow-warnings` | Do not treat warnings as errors |
 | `-B BUILD_DIR`, `--build-dir BUILD_DIR` | Root build directory, project files will be in ${build_dir}/${project_name} |
 | `-c`, `--coverage` | Enable CONFIG_COVERAGE Kconfig. |
 | `--extra-cflags EXTRA_CFLAGS` | Additional CFLAGS to use for target builds |
+| `--delete-intermediates` | Delete intermediate files to save disk space |
 | `-a`, `--all` | Select all projects |
-| `--host-tests-only` | Select all test projects |
 
 ### zmake build
 
-**Usage:** `zmake build [-h] [-t TOOLCHAIN] [--bringup] [--clobber] [--allow-warnings] [-B BUILD_DIR] [-c] [--extra-cflags EXTRA_CFLAGS] (-a | --host-tests-only | project_name [project_name ...])`
+**Usage:** `zmake build [-h] [-t TOOLCHAIN] [--bringup] [--clobber] [--static] [--save-temps] [--allow-warnings] [-B BUILD_DIR] [-c] [--extra-cflags EXTRA_CFLAGS] [--delete-intermediates] (-a | project_name [project_name ...])`
 
 #### Positional Arguments
 
@@ -76,12 +78,14 @@ Chromium OS's meta-build tool for Zephyr
 | `-t TOOLCHAIN`, `--toolchain TOOLCHAIN` | Name of toolchain to use |
 | `--bringup` | Enable bringup debugging features |
 | `--clobber` | Delete existing build directories, even if configuration is unchanged |
+| `--static` | Generate static version information for reproducible builds |
+| `--save-temps` | Save the temporary files containing preprocessor output |
 | `--allow-warnings` | Do not treat warnings as errors |
 | `-B BUILD_DIR`, `--build-dir BUILD_DIR` | Root build directory, project files will be in ${build_dir}/${project_name} |
 | `-c`, `--coverage` | Enable CONFIG_COVERAGE Kconfig. |
 | `--extra-cflags EXTRA_CFLAGS` | Additional CFLAGS to use for target builds |
+| `--delete-intermediates` | Delete intermediate files to save disk space |
 | `-a`, `--all` | Select all projects |
-| `--host-tests-only` | Select all test projects |
 
 ### zmake list-projects
 
@@ -102,7 +106,7 @@ Chromium OS's meta-build tool for Zephyr
 
 ### zmake test
 
-**Usage:** `zmake test [-h] [--no-rebuild] [-t TOOLCHAIN] [--bringup] [--clobber] [--allow-warnings] [-B BUILD_DIR] [-c] [--extra-cflags EXTRA_CFLAGS] (-a | --host-tests-only | project_name [project_name ...])`
+**Usage:** `zmake test [-h] [--no-rebuild] [-t TOOLCHAIN] [--bringup] [--clobber] [--static] [--save-temps] [--allow-warnings] [-B BUILD_DIR] [-c] [--extra-cflags EXTRA_CFLAGS] [--delete-intermediates] (-a | project_name [project_name ...])`
 
 #### Positional Arguments
 
@@ -119,16 +123,18 @@ Chromium OS's meta-build tool for Zephyr
 | `-t TOOLCHAIN`, `--toolchain TOOLCHAIN` | Name of toolchain to use |
 | `--bringup` | Enable bringup debugging features |
 | `--clobber` | Delete existing build directories, even if configuration is unchanged |
+| `--static` | Generate static version information for reproducible builds |
+| `--save-temps` | Save the temporary files containing preprocessor output |
 | `--allow-warnings` | Do not treat warnings as errors |
 | `-B BUILD_DIR`, `--build-dir BUILD_DIR` | Root build directory, project files will be in ${build_dir}/${project_name} |
 | `-c`, `--coverage` | Enable CONFIG_COVERAGE Kconfig. |
 | `--extra-cflags EXTRA_CFLAGS` | Additional CFLAGS to use for target builds |
+| `--delete-intermediates` | Delete intermediate files to save disk space |
 | `-a`, `--all` | Select all projects |
-| `--host-tests-only` | Select all test projects |
 
 ### zmake testall
 
-**Usage:** `zmake testall [-h] [--clobber] [-B BUILD_DIR]`
+**Usage:** `zmake testall [-h] [--clobber] [-B BUILD_DIR] [--static]`
 
 #### Optional Arguments
 
@@ -137,6 +143,7 @@ Chromium OS's meta-build tool for Zephyr
 | `-h`, `--help` | show this help message and exit |
 | `--clobber` | Delete existing build directories, even if configuration is unchanged |
 | `-B BUILD_DIR`, `--build-dir BUILD_DIR` | Build directory |
+| `--static` | Generate static version information for reproducible builds |
 
 ### zmake generate-readme
 
diff --git a/zephyr/zmake/pre-upload.sh b/zephyr/zmake/pre-upload.sh
deleted file mode 100755
index 15b6637f44..0000000000
--- a/zephyr/zmake/pre-upload.sh
+++ /dev/null
@@ -1,68 +0,0 @@
-#!/bin/bash
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-set -e
-
-ZMAKE_FILES=()
-BUILD_PY_FILES=()
-
-for path in "$@"; do
-    case "${path}" in
-        *zephyr/zmake/*.py )
-            ZMAKE_FILES+=("${path}")
-            ;;
-        */BUILD.py )
-            BUILD_PY_FILES+=("${path}")
-            ;;
-    esac
-done
-
-AFFECTED_FILES=("${ZMAKE_FILES[@]}" "${BUILD_PY_FILES[@]}")
-
-if [ "${#AFFECTED_FILES}" -eq 0 ]; then
-    # No zmake changes made, do nothing.
-    exit 0
-fi
-
-EXIT_STATUS=0
-
-# Wraps a black/isort command and reports how to fix it.
-wrap_fix_msg() {
-    local cmd="$1"
-    shift
-
-    if ! "${cmd}" "$@"; then
-        cat <<EOF >&2
-Looks like zmake's ${cmd} formatter detected that formatting changes
-need applied.  Fix by running this command from the zephyr/zmake
-directory and amending your changes:
-
-  ${cmd} .
-
-EOF
-        EXIT_STATUS=1
-    fi
-}
-
-# We only want to run black, flake8, and isort inside of the chroot,
-# as these are formatting tools which we want the specific versions
-# provided by the chroot.
-if [ -f /etc/cros_chroot_version ]; then
-    cd "$(dirname "$(realpath -e "${BASH_SOURCE[0]}")")"
-    wrap_fix_msg black --check --diff "${AFFECTED_FILES[@]}"
-    wrap_fix_msg isort --check "${AFFECTED_FILES[@]}"
-    if [ "${#ZMAKE_FILES[@]}" -gt 0 ]; then
-        flake8 "${ZMAKE_FILES[@]}" || EXIT_STATUS=1
-    fi
-    exit "${EXIT_STATUS}"
-else
-    cat <<EOF >&2
-WARNING: It looks like you made zmake changes, but I'm running outside
-of the chroot, and can't run zmake's auto-formatters.
-
-It is recommended that you run repo upload from inside the chroot, or
-you may see formatting errors during your CQ run.
-EOF
-    exit 1
-fi
diff --git a/zephyr/zmake/run_tests.sh b/zephyr/zmake/run_tests.sh
index 4796704440..3468a22deb 100755
--- a/zephyr/zmake/run_tests.sh
+++ b/zephyr/zmake/run_tests.sh
@@ -1,5 +1,5 @@
 #!/bin/bash
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -19,20 +19,7 @@ cd "$(dirname "$(realpath -e "${BASH_SOURCE[0]}")")"
 export PYTHONPATH="${PWD}"
 
 # Run pytest.
-# TODO(jrosenth): --hypothesis-profile=cq is very likely to be
-# unnecessary, as this was only needed when we were heavily taxing the
-# CPU by running pytest alongside all the ninjas, which no longer
-# happens.  Remove this flag.
-pytest --hypothesis-profile=cq .
-
-# Check import sorting.
-isort --check .
-
-# Check black formatting.
-black --check --diff .
-
-# Check flake8 reports no issues.
-flake8 .
+pytest . -v
 
 # Check auto-generated README.md is as expected.
 python -m zmake generate-readme --diff
diff --git a/zephyr/zmake/setup.py b/zephyr/zmake/setup.py
index 3786335f19..b7e58ef803 100644
--- a/zephyr/zmake/setup.py
+++ b/zephyr/zmake/setup.py
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -11,14 +11,14 @@ setuptools.setup(
     description="CrOS Zephyr Utilities",
     long_description="Utilities used for working on a Zephyr-based EC",
     url="https://chromium.googlesource.com/chromiumos/platform/ec",
-    author="Chromium OS Authors",
+    author="ChromiumOS Authors",
     author_email="chromiumos-dev@chromium.org",
     license="BSD",
     # What does your project relate to?
     keywords="chromeos",
     # You can just specify the packages manually here if your project is
     # simple. Or you can use find_packages().
-    packages=["zmake"],
+    packages=["zmake", "zephyr_build_tools"],
     python_requires=">=3.6, <4",
     # List run-time dependencies here.  These will be installed by pip when
     # your project is installed. For an analysis of "install_requires" vs pip's
diff --git a/zephyr/zmake/tests/conftest.py b/zephyr/zmake/tests/conftest.py
index 38e34bef56..dfea10457c 100644
--- a/zephyr/zmake/tests/conftest.py
+++ b/zephyr/zmake/tests/conftest.py
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -7,14 +7,14 @@
 import os
 import pathlib
 
-import hypothesis
-import pytest
-
+import hypothesis  # pylint:disable=import-error
+import pytest  # pylint:disable=import-error
 import zmake.zmake as zm
 
 hypothesis.settings.register_profile(
     "cq", suppress_health_check=hypothesis.HealthCheck.all()
 )
+hypothesis.settings.load_profile("cq")
 
 # pylint: disable=redefined-outer-name,unused-argument
 
diff --git a/zephyr/zmake/tests/test_build_config.py b/zephyr/zmake/tests/test_build_config.py
index 76cc0a2028..d8355da768 100644
--- a/zephyr/zmake/tests/test_build_config.py
+++ b/zephyr/zmake/tests/test_build_config.py
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -10,10 +10,9 @@ import pathlib
 import string
 import tempfile
 
-import hypothesis
-import hypothesis.strategies as st
-import pytest
-
+import hypothesis  # pylint:disable=import-error
+import hypothesis.strategies as st  # pylint:disable=import-error
+import pytest  # pylint:disable=import-error
 import zmake.jobserver
 import zmake.util as util
 from zmake.build_config import BuildConfig
@@ -36,17 +35,13 @@ config_dicts_at_least_one_entry = st.dictionaries(
 
 build_configs = st.builds(
     BuildConfig,
-    environ_defs=config_dicts,
     cmake_defs=config_dicts,
     kconfig_defs=config_dicts,
     kconfig_files=st.lists(paths),
 )
-build_configs_no_kconfig = st.builds(
-    BuildConfig, environ_defs=config_dicts, cmake_defs=config_dicts
-)
+build_configs_no_kconfig = st.builds(BuildConfig, cmake_defs=config_dicts)
 build_configs_with_at_least_one_kconfig = st.builds(
     BuildConfig,
-    environ_defs=config_dicts,
     cmake_defs=config_dicts,
     kconfig_defs=config_dicts_at_least_one_entry,
 )
@@ -70,19 +65,16 @@ def test_merge(coins, combined):
         return left, right
 
     # Split the original config into two
-    env1, env2 = split(combined.environ_defs.items())
     cmake1, cmake2 = split(combined.cmake_defs.items())
     kconf1, kconf2 = split(combined.kconfig_defs.items())
     files1, files2 = split(combined.kconfig_files)
 
     config1 = BuildConfig(
-        environ_defs=dict(env1),
         cmake_defs=dict(cmake1),
         kconfig_defs=dict(kconf1),
         kconfig_files=files1,
     )
     config2 = BuildConfig(
-        environ_defs=dict(env2),
         cmake_defs=dict(cmake2),
         kconfig_defs=dict(kconf2),
         kconfig_files=files2,
@@ -92,7 +84,6 @@ def test_merge(coins, combined):
     merged = config1 | config2
 
     # Assert that the merged split configs is the original config
-    assert merged.environ_defs == combined.environ_defs
     assert merged.cmake_defs == combined.cmake_defs
     assert merged.kconfig_defs == combined.kconfig_defs
     assert set(merged.kconfig_files) == set(combined.kconfig_files)
@@ -158,12 +149,13 @@ def test_popen_cmake_no_kconfig(conf: BuildConfig, project_dir, build_dir):
     _, cmake_defs = parse_cmake_args(job_client.captured_argv)
 
     assert cmake_defs == conf.cmake_defs
-    assert job_client.captured_env == conf.environ_defs
 
 
 @hypothesis.given(build_configs_with_at_least_one_kconfig, paths, paths)
 @hypothesis.settings(deadline=60000)
-def test_popen_cmake_kconfig_but_no_file(conf: BuildConfig, project_dir, build_dir):
+def test_popen_cmake_kconfig_but_no_file(
+    conf: BuildConfig, project_dir, build_dir
+):
     """Test that running popen_cmake with Kconfig definitions to write
     out, but no path to do so, should raise an error.
     """
@@ -184,7 +176,10 @@ def test_popen_cmake_kconfig(conf: BuildConfig, project_dir, build_dir):
 
     try:
         conf.popen_cmake(
-            job_client, project_dir, build_dir, kconfig_path=pathlib.Path(temp_path)
+            job_client,
+            project_dir,
+            build_dir,
+            kconfig_path=pathlib.Path(temp_path),
         )
 
         _, cmake_defs = parse_cmake_args(job_client.captured_argv)
@@ -199,7 +194,6 @@ def test_popen_cmake_kconfig(conf: BuildConfig, project_dir, build_dir):
             kconfig_files = set()
 
         assert cmake_defs == conf.cmake_defs
-        assert job_client.captured_env == conf.environ_defs
         assert kconfig_files == expected_kconfig_files
 
         kconfig_defs = util.read_kconfig_file(temp_path)
@@ -215,7 +209,9 @@ def fake_kconfig_files(tmp_path):
     paths = [tmp_path / f"{letter}.conf" for letter in "ABCD"]
 
     for path, cfg_name in zip(paths, ("ONE", "TWO", "THREE", "FOUR")):
-        path.write_text(f"# Fake kconfig file for testing.\nCONFIG_{cfg_name}=y\n")
+        path.write_text(
+            f"# Fake kconfig file for testing.\nCONFIG_{cfg_name}=y\n"
+        )
 
     return paths
 
@@ -225,10 +221,6 @@ def test_build_config_json_stability(fake_kconfig_files):
     build configs.
     """
     config_a = BuildConfig(
-        environ_defs={
-            "A": "B",
-            "B": "C",
-        },
         cmake_defs={
             "Z": "Y",
             "X": "W",
@@ -242,10 +234,6 @@ def test_build_config_json_stability(fake_kconfig_files):
 
     # Dict ordering is intentionally reversed in b.
     config_b = BuildConfig(
-        environ_defs={
-            "B": "C",
-            "A": "B",
-        },
         cmake_defs={
             "X": "W",
             "Z": "Y",
@@ -265,7 +253,7 @@ def test_build_config_json_inequality():
     representation.
     """
     config_a = BuildConfig(cmake_defs={"A": "B"})
-    config_b = BuildConfig(environ_defs={"A": "B"})
+    config_b = BuildConfig(kconfig_defs={"CONFIG_A": "y"})
 
     assert config_a.as_json() != config_b.as_json()
 
diff --git a/zephyr/zmake/tests/test_generate_readme.py b/zephyr/zmake/tests/test_generate_readme.py
index cb4bcf6cc1..e7873f1980 100644
--- a/zephyr/zmake/tests/test_generate_readme.py
+++ b/zephyr/zmake/tests/test_generate_readme.py
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -6,8 +6,7 @@
 Tests for the generate_readme.py file.
 """
 
-import pytest
-
+import pytest  # pylint:disable=import-error
 import zmake.generate_readme as gen_readme
 
 
@@ -34,7 +33,7 @@ def test_generate_readme_diff(
     expected_contents,
     actual_contents,
     return_code,
-):  # pylint: disable=too-many-arguments
+):
     """Verify that the diff function can detect different text."""
 
     def generate_readme():
diff --git a/zephyr/zmake/tests/test_modules.py b/zephyr/zmake/tests/test_modules.py
index 600544d2e7..dc4c170535 100644
--- a/zephyr/zmake/tests/test_modules.py
+++ b/zephyr/zmake/tests/test_modules.py
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -7,9 +7,8 @@
 import pathlib
 import tempfile
 
-import hypothesis
-import hypothesis.strategies as st
-
+import hypothesis  # pylint:disable=import-error
+import hypothesis.strategies as st  # pylint:disable=import-error
 import zmake.modules
 
 module_lists = st.lists(
@@ -37,4 +36,6 @@ def test_locate_in_directory(modules):
 
             expected_modules[module] = module_dir
 
-        assert zmake.modules.locate_from_directory(modules_dir) == expected_modules
+        assert (
+            zmake.modules.locate_from_directory(modules_dir) == expected_modules
+        )
diff --git a/zephyr/zmake/tests/test_multiproc_executor.py b/zephyr/zmake/tests/test_multiproc_executor.py
index c905ef03ec..ff443e2f4b 100644
--- a/zephyr/zmake/tests/test_multiproc_executor.py
+++ b/zephyr/zmake/tests/test_multiproc_executor.py
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
diff --git a/zephyr/zmake/tests/test_multiproc_logging.py b/zephyr/zmake/tests/test_multiproc_logging.py
index 2694b6451e..88d029675b 100644
--- a/zephyr/zmake/tests/test_multiproc_logging.py
+++ b/zephyr/zmake/tests/test_multiproc_logging.py
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -20,7 +20,9 @@ def test_read_output_from_pipe():
     file_desc = io.TextIOWrapper(os.fdopen(pipe[0], "rb"), encoding="utf-8")
     logger = mock.Mock(spec=logging.Logger)
     logger.log.side_effect = lambda log_lvl, line: semaphore.release()
-    zmake.multiproc.LogWriter.log_output(logger, logging.DEBUG, file_desc, job_id="")
+    zmake.multiproc.LogWriter.log_output(
+        logger, logging.DEBUG, file_desc, job_id=""
+    )
     os.write(pipe[1], "Hello\n".encode("utf-8"))
     semaphore.acquire()
     logger.log.assert_called_with(logging.DEBUG, "Hello")
@@ -77,8 +79,12 @@ def test_read_output_from_second_pipe():
     logger = mock.Mock(spec=logging.Logger)
     logger.log.side_effect = lambda log_lvl, fmt, id, line: semaphore.release()
 
-    zmake.multiproc.LogWriter.log_output(logger, logging.DEBUG, fds[0], job_id="0")
-    zmake.multiproc.LogWriter.log_output(logger, logging.ERROR, fds[1], job_id="1")
+    zmake.multiproc.LogWriter.log_output(
+        logger, logging.DEBUG, fds[0], job_id="0"
+    )
+    zmake.multiproc.LogWriter.log_output(
+        logger, logging.ERROR, fds[1], job_id="1"
+    )
 
     os.write(pipes[1][1], "Hello\n".encode("utf-8"))
     semaphore.acquire()
@@ -102,8 +108,12 @@ def test_read_output_after_another_pipe_closed():
     logger = mock.Mock(spec=logging.Logger)
     logger.log.side_effect = lambda log_lvl, fmt, id, line: semaphore.release()
 
-    zmake.multiproc.LogWriter.log_output(logger, logging.DEBUG, fds[0], job_id="0")
-    zmake.multiproc.LogWriter.log_output(logger, logging.ERROR, fds[1], job_id="1")
+    zmake.multiproc.LogWriter.log_output(
+        logger, logging.DEBUG, fds[0], job_id="0"
+    )
+    zmake.multiproc.LogWriter.log_output(
+        logger, logging.ERROR, fds[1], job_id="1"
+    )
 
     fds[0].close()
     os.write(pipes[1][1], "Hello\n".encode("utf-8"))
diff --git a/zephyr/zmake/tests/test_packers.py b/zephyr/zmake/tests/test_packers.py
index 43b63a908f..23bdb2bf6b 100644
--- a/zephyr/zmake/tests/test_packers.py
+++ b/zephyr/zmake/tests/test_packers.py
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -7,10 +7,9 @@
 import pathlib
 import tempfile
 
-import hypothesis
-import hypothesis.strategies as st
-import pytest
-
+import hypothesis  # pylint:disable=import-error
+import hypothesis.strategies as st  # pylint:disable=import-error
+import pytest  # pylint:disable=import-error
 import zmake.output_packers as packers
 
 # Strategies for use with hypothesis
@@ -54,7 +53,7 @@ def test_file_size_in_bounds(data):
     """Test with file size limited."""
     packer = FakePacker(100)
     with tempfile.TemporaryDirectory() as temp_dir_name:
-        file = pathlib.Path(temp_dir_name) / "zephyr.bin"
+        file = pathlib.Path(temp_dir_name) / "ec.bin"
         with open(file, "wb") as outfile:
             outfile.write(data)
         assert packer.check_packed_file_size(file=file, dir_map={}) == file
@@ -66,7 +65,7 @@ def test_file_size_out_of_bounds(data):
     """Test with file size limited, and file exceeds limit."""
     packer = FakePacker(100)
     with tempfile.TemporaryDirectory() as temp_dir_name:
-        file = pathlib.Path(temp_dir_name) / "zephyr.bin"
+        file = pathlib.Path(temp_dir_name) / "ec.bin"
         with open(file, "wb") as outfile:
             outfile.write(data)
         with pytest.raises(RuntimeError):
diff --git a/zephyr/zmake/tests/test_project.py b/zephyr/zmake/tests/test_project.py
index b5facbc331..3225de1d75 100644
--- a/zephyr/zmake/tests/test_project.py
+++ b/zephyr/zmake/tests/test_project.py
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -8,10 +8,9 @@ import pathlib
 import string
 import tempfile
 
-import hypothesis
-import hypothesis.strategies as st
-import pytest
-
+import hypothesis  # pylint:disable=import-error
+import hypothesis.strategies as st  # pylint:disable=import-error
+import pytest  # pylint:disable=import-error
 import zmake.modules
 import zmake.output_packers
 import zmake.project
@@ -34,7 +33,9 @@ def test_find_dts_overlays(modules):
             with tempfile.TemporaryDirectory() as modpath:
                 modpath = pathlib.Path(modpath)
                 for board in boards:
-                    dts_path = zmake.project.module_dts_overlay_name(modpath, board)
+                    dts_path = zmake.project.module_dts_overlay_name(
+                        modpath, board
+                    )
                     dts_path.parent.mkdir(parents=True, exist_ok=True)
                     dts_path.touch()
                 setup_modules_and_dispatch(
@@ -49,7 +50,9 @@ def test_find_dts_overlays(modules):
         board_file_mapping = {}
         for modpath, board_list in zip(module_paths, modules):
             for board in board_list:
-                file_name = zmake.project.module_dts_overlay_name(modpath, board)
+                file_name = zmake.project.module_dts_overlay_name(
+                    modpath, board
+                )
                 files = board_file_mapping.get(board, set())
                 board_file_mapping[board] = files | {file_name}
 
@@ -258,4 +261,6 @@ def test_kconfig_files(tmp_path, actual_files, config_files, expected_files):
     assert len(builds) == 1
 
     _, config = builds[0]
-    assert sorted(f.name for f in config.kconfig_files) == sorted(expected_files)
+    assert sorted(f.name for f in config.kconfig_files) == sorted(
+        expected_files
+    )
diff --git a/zephyr/zmake/tests/test_reexec.py b/zephyr/zmake/tests/test_reexec.py
index 5d7905cd8f..63aa76cb70 100644
--- a/zephyr/zmake/tests/test_reexec.py
+++ b/zephyr/zmake/tests/test_reexec.py
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 """Test the zmake re-exec functionality."""
@@ -7,8 +7,7 @@ import os
 import sys
 import unittest.mock as mock
 
-import pytest
-
+import pytest  # pylint:disable=import-error
 import zmake.__main__ as main
 
 
diff --git a/zephyr/zmake/tests/test_toolchains.py b/zephyr/zmake/tests/test_toolchains.py
index 910a5faa78..ca40f482af 100644
--- a/zephyr/zmake/tests/test_toolchains.py
+++ b/zephyr/zmake/tests/test_toolchains.py
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -7,8 +7,7 @@
 import os
 import pathlib
 
-import pytest
-
+import pytest  # pylint:disable=import-error
 import zmake.output_packers
 import zmake.project as project
 import zmake.toolchains as toolchains
@@ -138,9 +137,6 @@ def test_zephyr(fake_project: project.Project, zephyr_exists, no_environ):
         "ZEPHYR_TOOLCHAIN_VARIANT": "zephyr",
         "ZEPHYR_SDK_INSTALL_DIR": str(pathlib.Path("/opt/zephyr-sdk")),
     }
-    assert config.environ_defs == {
-        "ZEPHYR_SDK_INSTALL_DIR": str(pathlib.Path("/opt/zephyr-sdk")),
-    }
 
 
 def test_zephyr_from_env(mockfs, monkeypatch, fake_project):
@@ -159,9 +155,6 @@ def test_zephyr_from_env(mockfs, monkeypatch, fake_project):
         "ZEPHYR_TOOLCHAIN_VARIANT": "zephyr",
         "ZEPHYR_SDK_INSTALL_DIR": str(zephyr_sdk_path),
     }
-    assert config.environ_defs == {
-        "ZEPHYR_SDK_INSTALL_DIR": str(zephyr_sdk_path),
-    }
 
 
 def test_host_toolchain(fake_project, host_toolchain_exists):
@@ -197,9 +190,13 @@ def test_no_toolchains(fake_project: project.Project, mockfs, no_environ):
         fake_project.get_toolchain(module_paths)
 
 
-def test_override_without_sdk(fake_project: project.Project, mockfs, no_environ):
+def test_override_without_sdk(
+    fake_project: project.Project, mockfs, no_environ
+):
     """Check for error override is set to zephyr, but it can't be found."""
     chain = fake_project.get_toolchain(module_paths, override="zephyr")
 
-    with pytest.raises(RuntimeError, match=r"No installed Zephyr SDK was found"):
+    with pytest.raises(
+        RuntimeError, match=r"No installed Zephyr SDK was found"
+    ):
         chain.get_build_config()
diff --git a/zephyr/zmake/tests/test_util.py b/zephyr/zmake/tests/test_util.py
index 1ec0076162..c5efa2d18e 100644
--- a/zephyr/zmake/tests/test_util.py
+++ b/zephyr/zmake/tests/test_util.py
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -7,10 +7,9 @@
 import pathlib
 import tempfile
 
-import hypothesis
-import hypothesis.strategies as st
-import pytest
-
+import hypothesis  # pylint:disable=import-error
+import hypothesis.strategies as st  # pylint:disable=import-error
+import pytest  # pylint:disable=import-error
 import zmake.util as util
 
 # Strategies for use with hypothesis
diff --git a/zephyr/zmake/tests/test_version.py b/zephyr/zmake/tests/test_version.py
index 9e00473752..d6202c0d85 100644
--- a/zephyr/zmake/tests/test_version.py
+++ b/zephyr/zmake/tests/test_version.py
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -8,8 +8,7 @@ import datetime
 import subprocess
 import unittest.mock as mock
 
-import pytest
-
+import pytest  # pylint: disable=import-error
 import zmake.output_packers
 import zmake.project
 import zmake.version as version
@@ -40,7 +39,9 @@ def _git_commit(repo, message="message!"):
         "GIT_COMMITTER_EMAIL": "bitdiddle@example.org",
         "GIT_COMMITTER_DATE": "Tue, 30 Aug 2005 10:50:30 -0700",
     }
-    subprocess.run(["git", "-C", repo, "commit", "-m", message], check=True, env=env)
+    subprocess.run(
+        ["git", "-C", repo, "commit", "-m", message], check=True, env=env
+    )
 
 
 def _setup_example_repos(tmp_path):
@@ -95,7 +96,9 @@ def test_version_string(tmp_path):
     """Test a that version string is as expected."""
     project, zephyr_base, modules = _setup_example_repos(tmp_path)
     assert (
-        version.get_version_string(project, zephyr_base, modules)
+        version.get_version_string(
+            project.config.project_name, zephyr_base, modules
+        )
         == "prj_v2.6.4-ec:b5991f,os:377d26,mod1:02fd7a"
     )
 
@@ -104,7 +107,9 @@ def test_version_string_static(tmp_path):
     """Test a that version string with no git hashes."""
     project, zephyr_base, modules = _setup_example_repos(tmp_path)
     assert (
-        version.get_version_string(project, zephyr_base, modules, static=True)
+        version.get_version_string(
+            project.config.project_name, zephyr_base, modules, static=True
+        )
         == "prj_v2.6.0-STATIC"
     )
 
@@ -128,7 +133,7 @@ def fake_date():
 
 HEADER_VERSION_STR = "trogdor_v2.6.1004-cmsis:0dead0,hal_stm32:0beef0,os:ad00da"
 EXPECTED_HEADER = (
-    "/* This file is automatically generated by zmake */\n"
+    "/* This file is automatically generated by zmake_tests */\n"
     '#define VERSION "trogdor_v2.6.1004-cmsis:0dead0,hal_stm32:0beef0,os:ad00da"\n'
     '#define CROS_EC_VERSION32 "trogdor_v2.6.1004-cmsis:0dead0,"\n'
     '#define BUILDER "toukmond@pokey"\n'
@@ -137,7 +142,7 @@ EXPECTED_HEADER = (
 )
 HEADER_VERSION_STR_STATIC = "trogdor_v2.6.0-STATIC"
 EXPECTED_HEADER_STATIC = (
-    "/* This file is automatically generated by zmake */\n"
+    "/* This file is automatically generated by zmake_tests */\n"
     '#define VERSION "trogdor_v2.6.0-STATIC"\n'
     '#define CROS_EC_VERSION32 "trogdor_v2.6.0-STATIC"\n'
     '#define BUILDER "reproducible@build"\n'
@@ -150,7 +155,7 @@ def test_header_gen(fake_user_hostname, fake_date, tmp_path):
     """Test generating the version header."""
     # Test the simple case (static=False, no existing header).
     output_file = tmp_path / "ec_version.h"
-    version.write_version_header(HEADER_VERSION_STR, output_file)
+    version.write_version_header(HEADER_VERSION_STR, output_file, "zmake_tests")
     assert output_file.read_text() == EXPECTED_HEADER
 
 
@@ -158,7 +163,9 @@ def test_header_gen_reproducible_build(tmp_path):
     """Test that reproducible builds produce the right header."""
     # With static=True this time.
     output_file = tmp_path / "ec_version.h"
-    version.write_version_header(HEADER_VERSION_STR_STATIC, output_file, static=True)
+    version.write_version_header(
+        HEADER_VERSION_STR_STATIC, output_file, "zmake_tests", static=True
+    )
     assert output_file.read_text() == EXPECTED_HEADER_STATIC
 
 
@@ -168,27 +175,31 @@ def test_header_gen_exists_not_changed(fake_user_hostname, fake_date, tmp_path):
     output_file = tmp_path / "ec_version.h"
 
     # First time, write and record mtime.
-    version.write_version_header(HEADER_VERSION_STR, output_file)
+    version.write_version_header(HEADER_VERSION_STR, output_file, "zmake_tests")
     expected_mtime = output_file.stat().st_mtime
 
     # Do another write (contents should be unchanged).
-    version.write_version_header(HEADER_VERSION_STR, output_file)
+    version.write_version_header(HEADER_VERSION_STR, output_file, "zmake_tests")
 
     # Assert we didn't write again.
     assert output_file.stat().st_mtime == expected_mtime
 
 
-def test_header_gen_exists_needs_changes(fake_user_hostname, fake_date, tmp_path):
+def test_header_gen_exists_needs_changes(
+    fake_user_hostname, fake_date, tmp_path
+):
     """Test that the version file is changed, when needed."""
     # Test we overwrite when it exists already and changes are needed.
     output_file = tmp_path / "ec_version.h"
 
     # First time, write and save contents.
-    version.write_version_header(HEADER_VERSION_STR, output_file)
+    version.write_version_header(HEADER_VERSION_STR, output_file, "zmake_tests")
     original_contents = output_file.read_text()
 
     # Do another write (contents should be changed).
-    version.write_version_header(HEADER_VERSION_STR_STATIC, output_file, static=True)
+    version.write_version_header(
+        HEADER_VERSION_STR_STATIC, output_file, "zmake_tests", static=True
+    )
 
     # Assert we overwrote.
     assert output_file.read_text() != original_contents
diff --git a/zephyr/zmake/tests/test_zmake.py b/zephyr/zmake/tests/test_zmake.py
index 4ca1d7f077..370e8d1bfa 100644
--- a/zephyr/zmake/tests/test_zmake.py
+++ b/zephyr/zmake/tests/test_zmake.py
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -10,15 +10,14 @@ import pathlib
 import re
 import unittest.mock
 
-import pytest
-from testfixtures import LogCapture
-
+import pytest  # pylint:disable=import-error
 import zmake.build_config
 import zmake.jobserver
 import zmake.multiproc as multiproc
 import zmake.output_packers
 import zmake.project
 import zmake.toolchains
+from testfixtures import LogCapture  # pylint:disable=import-error
 
 OUR_PATH = os.path.dirname(os.path.realpath(__file__))
 
@@ -75,8 +74,7 @@ class FakeJobserver(zmake.jobserver.GNUMakeJobServer):
             fnames: Dict of regexp to filename. If the regexp matches the
             command, then the filename will be returned as the output.
         """
-        super().__init__()
-        self.jobserver = zmake.jobserver.GNUMakeJobServer(jobs=2)
+        super().__init__(jobs=2)
         self.fnames = fnames
 
     def get_job(self):
@@ -88,14 +86,21 @@ class FakeJobserver(zmake.jobserver.GNUMakeJobServer):
         """Ignores the provided command and just runs 'cat' instead"""
         for pattern, filename in self.fnames.items():
             # Convert to a list of strings
-            cmd = [isinstance(c, pathlib.PosixPath) and c.as_posix() or c for c in cmd]
+            cmd = [
+                isinstance(c, pathlib.PosixPath) and c.as_posix() or c
+                for c in cmd
+            ]
             if pattern.match(" ".join(cmd)):
                 new_cmd = ["cat", filename]
                 break
         else:
             raise Exception('No pattern matched "%s"' % " ".join(cmd))
-        kwargs.pop("env", None)
-        return self.jobserver.popen(new_cmd, *args, **kwargs)
+        kwargs["env"] = {}
+        return super().popen(new_cmd, *args, **kwargs)
+
+    def env(self):
+        """Runs test commands with an empty environment for simpler logs."""
+        return {}
 
 
 def get_test_filepath(suffix):
@@ -168,7 +173,9 @@ class TestFilters:
         expected = {
             "Configuring fakeproject:rw.",
             "Configuring fakeproject:ro.",
-            "Building fakeproject in {}/ec/build/zephyr/fakeproject.".format(tmp_path),
+            "Building fakeproject in {}/ec/build/zephyr/fakeproject.".format(
+                tmp_path
+            ),
             "Building fakeproject:ro: /usr/bin/ninja -C {}-ro".format(
                 tmp_path / "ec/build/zephyr/fakeproject/build"
             ),
@@ -179,7 +186,9 @@ class TestFilters:
         for suffix in ["ro", "rw"]:
             with open(get_test_filepath("%s_INFO" % suffix)) as file:
                 for line in file:
-                    expected.add("[fakeproject:{}]{}".format(suffix, line.strip()))
+                    expected.add(
+                        "[fakeproject:{}]{}".format(suffix, line.strip())
+                    )
         # This produces an easy-to-read diff if there is a difference
         assert expected == set(recs)
 
@@ -192,20 +201,24 @@ class TestFilters:
         expected = {
             "Configuring fakeproject:rw.",
             "Configuring fakeproject:ro.",
-            "Building fakeproject in {}/ec/build/zephyr/fakeproject.".format(tmp_path),
+            "Building fakeproject in {}/ec/build/zephyr/fakeproject.".format(
+                tmp_path
+            ),
             "Building fakeproject:ro: /usr/bin/ninja -C {}-ro".format(
                 tmp_path / "ec/build/zephyr/fakeproject/build"
             ),
             "Building fakeproject:rw: /usr/bin/ninja -C {}-rw".format(
                 tmp_path / "ec/build/zephyr/fakeproject/build"
             ),
-            "Running cat {}/files/sample_ro.txt".format(OUR_PATH),
-            "Running cat {}/files/sample_rw.txt".format(OUR_PATH),
+            "Running `env -i cat {}/files/sample_ro.txt`".format(OUR_PATH),
+            "Running `env -i cat {}/files/sample_rw.txt`".format(OUR_PATH),
         }
         for suffix in ["ro", "rw"]:
             with open(get_test_filepath(suffix)) as file:
                 for line in file:
-                    expected.add("[fakeproject:{}]{}".format(suffix, line.strip()))
+                    expected.add(
+                        "[fakeproject:{}]{}".format(suffix, line.strip())
+                    )
         # This produces an easy-to-read diff if there is a difference
         assert expected == set(recs)
 
@@ -219,7 +232,9 @@ class TestFilters:
         )
 
         dt_errs = [rec for rec in recs if "adc" in rec]
-        assert "devicetree error: 'adc' is marked as required" in list(dt_errs)[0]
+        assert (
+            "devicetree error: 'adc' is marked as required" in list(dt_errs)[0]
+        )
 
 
 @pytest.mark.parametrize(
@@ -265,7 +280,7 @@ class TestFilters:
 )
 def test_list_projects(
     project_names, fmt, search_dir, expected_output, capsys, zmake_from_dir
-):  # pylint: disable=too-many-arguments
+):
     """Test listing projects with default directory."""
     fake_projects = {
         name: zmake.project.Project(
diff --git a/zephyr/zmake/zephyr_build_tools/__init__.py b/zephyr/zmake/zephyr_build_tools/__init__.py
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/zephyr/zmake/zephyr_build_tools/__init__.py
diff --git a/zephyr/zmake/zephyr_build_tools/generate_ec_version.py b/zephyr/zmake/zephyr_build_tools/generate_ec_version.py
new file mode 100755
index 0000000000..7d3a9450ee
--- /dev/null
+++ b/zephyr/zmake/zephyr_build_tools/generate_ec_version.py
@@ -0,0 +1,169 @@
+#!/usr/bin/env python3
+
+# Copyright 2022 The ChromiumOS Authors
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+"""Code to generate the ec_version.h file."""
+
+import argparse
+import logging
+import os.path
+import pathlib
+import sys
+
+import zmake.version
+
+
+def convert_module_list_to_dict(modules: list) -> dict:
+    """Convert a list of string paths to modules in to a dict of module
+    names to paths."""
+
+    if not modules:
+        return {}
+
+    dict_out = {}
+    for mod in modules:
+        if not mod.is_dir():
+            raise FileNotFoundError(f"Module '{mod}' not found")
+
+        dict_out[mod.name] = mod
+
+    return dict_out
+
+
+def main():
+    """CLI entry point for generating the ec_version.h header"""
+    logging.basicConfig(level=logging.INFO, stream=sys.stderr)
+
+    parser = argparse.ArgumentParser()
+
+    parser.add_argument("header_path", help="Path to write ec_version.h to")
+    parser.add_argument(
+        "-s",
+        "--static",
+        action="store_true",
+        help="If set, generate a header which does not include information "
+        "like the username, hostname, or date, allowing the build to be"
+        "reproducible.",
+    )
+    parser.add_argument(
+        "--base",
+        default=os.environ.get("ZEPHYR_BASE"),
+        help="Path to Zephyr base directory. Uses ZEPHYR_BASE env var if unset.",
+    )
+    parser.add_argument(
+        "-m",
+        "--module",
+        action="append",
+        help="Specify modules paths to include in version hash. Uses "
+        "ZEPHYR_MODULES env var if unset",
+    )
+    parser.add_argument(
+        "-n", "--name", required=True, type=str, help="Project name"
+    )
+
+    args = parser.parse_args()
+
+    if args.base is None:
+        logging.error(
+            "No Zephyr base is defined. Pass --base or set env var ZEPHYR_BASE"
+        )
+        return 1
+
+    logging.info("Zephyr Base: %s", args.base)
+
+    if args.static:
+        logging.info("Using a static version string")
+
+    # Make a dict of modules from the list. Modules can be added one at a time
+    # by repeating the -m flag, or once as a semicolon-separated list. In the
+    # later case, we need to expand the modules list.
+
+    if args.module is None:
+        # No modules specified on command line. Default to environment variable.
+        env_modules = os.environ.get("ZEPHYR_MODULES")
+        args.module = env_modules.split(";") if env_modules else []
+        logging.info(
+            "No modules passed via CLI. Getting list from ZEPHYR_MODULES"
+        )
+
+    elif len(args.module) == 1:
+        # In case of a single -m flag, treat value as a semicolon-delimited
+        # list.
+        args.module = args.module[0].split(";")
+
+    try:
+        module_dict = convert_module_list_to_dict(
+            map(pathlib.Path, args.module)
+        )
+    except FileNotFoundError as err:
+        logging.error("Cannot find module: %s", str(err))
+        return 1
+
+    logging.info("Including modules: [%s]", ", ".join(args.module))
+
+    # Generate the version string that gets inserted in to the header. Will get
+    # commit IDs from Git
+    ver = zmake.version.get_version_string(
+        args.name, args.base, module_dict, args.static
+    )
+    logging.info("Version string: %s", ver)
+
+    # Now write the actual header file or put version string in stdout
+    if args.header_path == "-":
+        print(ver)
+    else:
+        output_path = pathlib.Path(args.header_path)
+        output_path.parent.mkdir(parents=True, exist_ok=True)
+
+        logging.info("Writing header to %s", args.header_path)
+        zmake.version.write_version_header(
+            ver, output_path, sys.argv[0], args.static
+        )
+
+    return 0
+
+
+def maybe_reexec():
+    """Re-exec using the zmake package from the EC source tree, as
+    opposed to the system's copy of zmake. This is useful for
+    development when engineers need to make changes to zmake. This
+    script relies on the zmake package for version string generation
+    logic.
+
+    Returns:
+        None, if the re-exec did not happen, or never returns if the
+        re-exec did happen.
+    """
+    # We only re-exec if we are inside of a chroot (since if installed
+    # standalone using pip, there's already an "editable install"
+    # feature for that in pip.)
+    env = dict(os.environ)
+    srcroot = env.get("CROS_WORKON_SRCROOT")
+    if not srcroot:
+        return
+
+    # If for some reason we decide to move zmake in the future, then
+    # we don't want to use the re-exec logic.
+    zmake_path = (
+        pathlib.Path(srcroot) / "src" / "platform" / "ec" / "zephyr" / "zmake"
+    ).resolve()
+    if not zmake_path.is_dir():
+        return
+
+    # If PYTHONPATH is set, it is either because we just did a
+    # re-exec, or because the user wants to run a specific copy of
+    # zmake.  In either case, we don't want to re-exec.
+    if "PYTHONPATH" in env:
+        return
+
+    # Set PYTHONPATH so that we run zmake from source.
+    env["PYTHONPATH"] = str(zmake_path)
+
+    os.execve(sys.argv[0], sys.argv, env)
+
+
+if __name__ == "__main__":
+    maybe_reexec()
+    sys.exit(main())
diff --git a/zephyr/zmake/zmake/__main__.py b/zephyr/zmake/zmake/__main__.py
index 23be20d54f..cc3b1708be 100644
--- a/zephyr/zmake/zmake/__main__.py
+++ b/zephyr/zmake/zmake/__main__.py
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -204,9 +204,11 @@ def get_argparser():
         help="Optional directory to search for BUILD.py files in.",
     )
 
+    # TODO(b/b/242563072): Remove stub support for test and testall entirely after users have gotten
+    # used to twister.
     test = sub.add_parser(
         "test",
-        help="Configure, build and run tests on specified projects",
+        help="Configure, build and run tests on specified projects; DEPRECATED",
     )
     test.add_argument(
         "--no-rebuild",
@@ -217,7 +219,7 @@ def get_argparser():
 
     testall = sub.add_parser(
         "testall",
-        help="Alias for test --all",
+        help="Alias for test --all; DEPRECATED",
     )
     testall.add_argument(
         "--clobber",
@@ -225,7 +227,15 @@ def get_argparser():
         dest="clobber",
         help="Delete existing build directories, even if configuration is unchanged",
     )
-    testall.add_argument("-B", "--build-dir", type=pathlib.Path, help="Build directory")
+    testall.add_argument(
+        "-B", "--build-dir", type=pathlib.Path, help="Build directory"
+    )
+    testall.add_argument(
+        "--static",
+        action="store_true",
+        dest="static_version",
+        help="Generate static version information for reproducible builds",
+    )
 
     generate_readme = sub.add_parser(
         "generate-readme",
@@ -251,7 +261,9 @@ def get_argparser():
 
 def add_common_configure_args(sub_parser: argparse.ArgumentParser):
     """Adds common arguments used by configure-like subcommands."""
-    sub_parser.add_argument("-t", "--toolchain", help="Name of toolchain to use")
+    sub_parser.add_argument(
+        "-t", "--toolchain", help="Name of toolchain to use"
+    )
     sub_parser.add_argument(
         "--bringup",
         action="store_true",
@@ -265,6 +277,18 @@ def add_common_configure_args(sub_parser: argparse.ArgumentParser):
         help="Delete existing build directories, even if configuration is unchanged",
     )
     sub_parser.add_argument(
+        "--static",
+        action="store_true",
+        dest="static_version",
+        help="Generate static version information for reproducible builds",
+    )
+    sub_parser.add_argument(
+        "--save-temps",
+        action="store_true",
+        dest="save_temps",
+        help="Save the temporary files containing preprocessor output",
+    )
+    sub_parser.add_argument(
         "--allow-warnings",
         action="store_true",
         default=False,
@@ -288,6 +312,12 @@ def add_common_configure_args(sub_parser: argparse.ArgumentParser):
         "--extra-cflags",
         help="Additional CFLAGS to use for target builds",
     )
+    sub_parser.add_argument(
+        "--delete-intermediates",
+        action="store_true",
+        dest="delete_intermediates",
+        help="Delete intermediate files to save disk space",
+    )
     group = sub_parser.add_mutually_exclusive_group(required=True)
     group.add_argument(
         "-a",
@@ -297,12 +327,6 @@ def add_common_configure_args(sub_parser: argparse.ArgumentParser):
         help="Select all projects",
     )
     group.add_argument(
-        "--host-tests-only",
-        action="store_true",
-        dest="host_tests_only",
-        help="Select all test projects",
-    )
-    group.add_argument(
         "project_names",
         nargs="*",
         metavar="project_name",
diff --git a/zephyr/zmake/zmake/build_config.py b/zephyr/zmake/zmake/build_config.py
index 0d03e22a45..24e877dd89 100644
--- a/zephyr/zmake/zmake/build_config.py
+++ b/zephyr/zmake/zmake/build_config.py
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 """Encapsulation of a build configuration."""
@@ -14,14 +14,16 @@ import zmake.util as util
 class BuildConfig:
     """A container for build configurations.
 
-    A build config is a tuple of environment variables, cmake
-    variables, kconfig definitons, and kconfig files.
+    A build config is a tuple of cmake variables, kconfig definitions,
+    and kconfig files.
     """
 
     def __init__(
-        self, environ_defs=None, cmake_defs=None, kconfig_defs=None, kconfig_files=None
+        self,
+        cmake_defs=None,
+        kconfig_defs=None,
+        kconfig_files=None,
     ):
-        self.environ_defs = dict(environ_defs or {})
         self.cmake_defs = dict(cmake_defs or {})
         self.kconfig_defs = dict(kconfig_defs or {})
 
@@ -63,19 +65,18 @@ class BuildConfig:
             )
 
         if kconfig_files:
-            base_config = BuildConfig(
-                environ_defs=self.environ_defs, cmake_defs=self.cmake_defs
-            )
+            base_config = BuildConfig(cmake_defs=self.cmake_defs)
             conf_file_config = BuildConfig(
                 cmake_defs={
-                    "CONF_FILE": ";".join(str(p.resolve()) for p in kconfig_files)
+                    "CONF_FILE": ";".join(
+                        str(p.resolve()) for p in kconfig_files
+                    )
                 }
             )
             return (base_config | conf_file_config).popen_cmake(
                 jobclient, project_dir, build_dir, **kwargs
             )
 
-        kwargs["env"] = dict(**kwargs.get("env", {}), **self.environ_defs)
         return jobclient.popen(
             [
                 "/usr/bin/cmake",
@@ -93,11 +94,12 @@ class BuildConfig:
         """Combine two BuildConfig instances."""
         if not isinstance(other, BuildConfig):
             raise TypeError(
-                "Unsupported operation | for {} and {}".format(type(self), type(other))
+                "Unsupported operation | for {} and {}".format(
+                    type(self), type(other)
+                )
             )
 
         return BuildConfig(
-            environ_defs=dict(**self.environ_defs, **other.environ_defs),
             cmake_defs=dict(**self.cmake_defs, **other.cmake_defs),
             kconfig_defs=dict(**self.kconfig_defs, **other.kconfig_defs),
             kconfig_files=[*self.kconfig_files, *other.kconfig_files],
@@ -108,7 +110,6 @@ class BuildConfig:
             ", ".join(
                 "{}={!r}".format(name, getattr(self, name))
                 for name in [
-                    "environ_defs",
                     "cmake_defs",
                     "kconfig_defs",
                     "kconfig_files",
@@ -150,7 +151,6 @@ class BuildConfig:
         """Provide a stable JSON representation of the build config."""
         return json.dumps(
             {
-                "environ_defs": self.environ_defs,
                 "cmake_defs": self.cmake_defs,
                 "kconfig_defs": self.kconfig_defs,
                 "kconfig_files": [str(p.resolve()) for p in self.kconfig_files],
diff --git a/zephyr/zmake/zmake/configlib.py b/zephyr/zmake/zmake/configlib.py
index 2baa20523b..139394745f 100644
--- a/zephyr/zmake/zmake/configlib.py
+++ b/zephyr/zmake/zmake/configlib.py
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -11,7 +11,9 @@ def _register_project(**kwargs):
     kwargs.setdefault(
         "project_dir", here  # noqa: F821 pylint: disable=undefined-variable
     )
-    return register_project(**kwargs)  # noqa: F821 pylint: disable=undefined-variable
+    return register_project(
+        **kwargs
+    )  # noqa: F821 pylint: disable=undefined-variable
 
 
 def register_host_project(**kwargs):
@@ -25,7 +27,9 @@ def register_host_project(**kwargs):
 def register_host_test(test_name, **kwargs):
     """Register a test project that runs on the host."""
     kwargs.setdefault("is_test", True)
-    return register_host_project(project_name="test-{}".format(test_name), **kwargs)
+    return register_host_project(
+        project_name="test-{}".format(test_name), **kwargs
+    )
 
 
 def register_raw_project(**kwargs):
diff --git a/zephyr/zmake/zmake/generate_readme.py b/zephyr/zmake/zmake/generate_readme.py
index 9008f0f45d..f309a104ba 100644
--- a/zephyr/zmake/zmake/generate_readme.py
+++ b/zephyr/zmake/zmake/generate_readme.py
@@ -1,4 +1,4 @@
-# Copyright 2022 The Chromium OS Authors. All rights reserved.
+# Copyright 2022 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -53,7 +53,9 @@ class MarkdownHelpFormatter(argparse.HelpFormatter):
                     if action.nargs == 0:
                         parts.append(option_string)
                     else:
-                        parts.append(f"{option_string} {_get_metavar(action).upper()}")
+                        parts.append(
+                            f"{option_string} {_get_metavar(action).upper()}"
+                        )
                 return ", ".join(f"`{part}`" for part in parts)
             return f"`{_get_metavar(action)}`"
 
@@ -103,7 +105,9 @@ def generate_readme():
 
     _append("# Zmake")
     _append()
-    _append('<!-- Auto-generated contents!  Run "zmake generate-readme" to update. -->')
+    _append(
+        '<!-- Auto-generated contents!  Run "zmake generate-readme" to update. -->'
+    )
     _append()
     _append("[TOC]")
     _append()
diff --git a/zephyr/zmake/zmake/jobserver.py b/zephyr/zmake/zmake/jobserver.py
index 16f856e607..a3d6287da2 100644
--- a/zephyr/zmake/zmake/jobserver.py
+++ b/zephyr/zmake/zmake/jobserver.py
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 """Module for job counters, limiting the amount of concurrent executions."""
@@ -8,6 +8,7 @@ import multiprocessing
 import os
 import re
 import select
+import shlex
 import subprocess
 
 import zmake
@@ -48,11 +49,19 @@ class JobClient:
         Returns:
             A Popen object.
         """
-        kwargs.setdefault("env", os.environ)
+        # By default, we scrub the environment for all commands we run, setting
+        # the bare minimum (PATH only).  This prevents us from building obscure
+        # dependencies on the environment variables.
+        kwargs.setdefault("env", {"PATH": "/bin:/usr/bin"})
         kwargs["env"].update(self.env())
 
         logger = logging.getLogger(self.__class__.__name__)
-        logger.debug("Running %s", zmake.util.repr_command(argv))
+        logger.debug(
+            "Running `env -i %s%s%s`",
+            " ".join(f"{k}={shlex.quote(v)}" for k, v in kwargs["env"].items()),
+            " " if kwargs["env"] else "",
+            zmake.util.repr_command(argv),
+        )
         return subprocess.Popen(argv, **kwargs)
 
 
diff --git a/zephyr/zmake/zmake/modules.py b/zephyr/zmake/zmake/modules.py
index 91f0dd50b9..a2b77342c7 100644
--- a/zephyr/zmake/zmake/modules.py
+++ b/zephyr/zmake/zmake/modules.py
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 """Registry of known Zephyr modules."""
diff --git a/zephyr/zmake/zmake/multiproc.py b/zephyr/zmake/zmake/multiproc.py
index 7d9a88de5a..0838f5f1f8 100644
--- a/zephyr/zmake/zmake/multiproc.py
+++ b/zephyr/zmake/zmake/multiproc.py
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -56,7 +56,7 @@ class LogWriter:
         """Reset this module to its starting state (useful for tests)"""
         LogWriter._logging_map.clear()
 
-    def __init__(  # pylint: disable=too-many-arguments
+    def __init__(
         self,
         logger,
         log_level,
@@ -202,7 +202,7 @@ class LogWriter:
                 LogWriter._log_fd(file)
 
     @classmethod
-    def log_output(  # pylint: disable=too-many-arguments
+    def log_output(
         cls,
         logger,
         log_level,
@@ -297,7 +297,9 @@ class Executor:
              exception.
         """
         with self.lock:
-            thread = threading.Thread(target=lambda: self._run_fn(func), daemon=True)
+            thread = threading.Thread(
+                target=lambda: self._run_fn(func), daemon=True
+            )
             thread.start()
             self.threads.append(thread)
 
diff --git a/zephyr/zmake/zmake/output_packers.py b/zephyr/zmake/zmake/output_packers.py
index 78ee7649e6..d2203fa7b4 100644
--- a/zephyr/zmake/zmake/output_packers.py
+++ b/zephyr/zmake/zmake/output_packers.py
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 """Types which provide many builds and composite them into a single binary."""
@@ -85,8 +85,10 @@ class BasePacker:
         Returns:
             The file if it passes the test.
         """
-        max_size = self._get_max_image_bytes(  # pylint: disable=assignment-from-none
-            dir_map
+        max_size = (
+            self._get_max_image_bytes(  # pylint: disable=assignment-from-none
+                dir_map
+            )
         )
         if max_size is None or file.stat().st_size <= max_size:
             return file
@@ -106,7 +108,7 @@ class RawBinPacker(BasePacker):
 
     def pack_firmware(self, work_dir, jobclient, dir_map, version_string=""):
         del version_string
-        yield dir_map["singleimage"] / "zephyr" / "zephyr.bin", "zephyr.bin"
+        yield dir_map["singleimage"] / "zephyr" / "zephyr.bin", "ec.bin"
 
 
 class BinmanPacker(BasePacker):
@@ -120,11 +122,19 @@ class BinmanPacker(BasePacker):
         super().__init__(project)
 
     def configs(self):
-        yield "ro", build_config.BuildConfig(kconfig_defs={"CONFIG_CROS_EC_RO": "y"})
-        yield "rw", build_config.BuildConfig(kconfig_defs={"CONFIG_CROS_EC_RW": "y"})
+        yield "ro", build_config.BuildConfig(
+            kconfig_defs={"CONFIG_CROS_EC_RO": "y"}
+        )
+        yield "rw", build_config.BuildConfig(
+            kconfig_defs={"CONFIG_CROS_EC_RW": "y"}
+        )
 
     def pack_firmware(
-        self, work_dir, jobclient: zmake.jobserver.JobClient, dir_map, version_string=""
+        self,
+        work_dir,
+        jobclient: zmake.jobserver.JobClient,
+        dir_map,
+        version_string="",
     ):
         """Pack RO and RW sections using Binman.
 
@@ -148,8 +158,12 @@ class BinmanPacker(BasePacker):
 
         # Copy the inputs into the work directory so that Binman can
         # find them under a hard-coded name.
-        shutil.copy2(ro_dir / "zephyr" / self.ro_file, work_dir / "zephyr_ro.bin")
-        shutil.copy2(rw_dir / "zephyr" / self.rw_file, work_dir / "zephyr_rw.bin")
+        shutil.copy2(
+            ro_dir / "zephyr" / self.ro_file, work_dir / "zephyr_ro.bin"
+        )
+        shutil.copy2(
+            rw_dir / "zephyr" / self.rw_file, work_dir / "zephyr_rw.bin"
+        )
 
         # Version in FRID/FWID can be at most 31 bytes long (32, minus
         # one for null character).
@@ -176,12 +190,16 @@ class BinmanPacker(BasePacker):
             encoding="utf-8",
         )
 
-        zmake.multiproc.LogWriter.log_output(self.logger, logging.DEBUG, proc.stdout)
-        zmake.multiproc.LogWriter.log_output(self.logger, logging.ERROR, proc.stderr)
+        zmake.multiproc.LogWriter.log_output(
+            self.logger, logging.DEBUG, proc.stdout
+        )
+        zmake.multiproc.LogWriter.log_output(
+            self.logger, logging.ERROR, proc.stderr
+        )
         if proc.wait(timeout=60):
             raise OSError("Failed to run binman")
 
-        yield work_dir / "zephyr.bin", "zephyr.bin"
+        yield work_dir / "ec.bin", "ec.bin"
         yield ro_dir / "zephyr" / "zephyr.elf", "zephyr.ro.elf"
         yield rw_dir / "zephyr" / "zephyr.elf", "zephyr.rw.elf"
 
@@ -220,10 +238,10 @@ class NpcxPacker(BinmanPacker):
             dir_map,
             version_string=version_string,
         ):
-            if output_file == "zephyr.bin":
+            if output_file == "ec.bin":
                 yield (
                     self._check_packed_file_size(path, dir_map),
-                    "zephyr.bin",
+                    "ec.bin",
                 )
             else:
                 yield path, output_file
diff --git a/zephyr/zmake/zmake/project.py b/zephyr/zmake/zmake/project.py
index 42d1258cb5..a707da2462 100644
--- a/zephyr/zmake/zmake/project.py
+++ b/zephyr/zmake/zmake/project.py
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 """Module for project config wrapper object."""
@@ -25,7 +25,13 @@ def module_dts_overlay_name(modpath, board_name):
     Returns:
         A pathlib.Path object to the expected overlay path.
     """
-    return modpath / "zephyr" / "dts" / "board-overlays" / "{}.dts".format(board_name)
+    return (
+        modpath
+        / "zephyr"
+        / "dts"
+        / "board-overlays"
+        / "{}.dts".format(board_name)
+    )
 
 
 @dataclasses.dataclass
@@ -43,7 +49,9 @@ class ProjectConfig:
     is_test: bool = dataclasses.field(default=False)
     test_args: typing.List[str] = dataclasses.field(default_factory=list)
     dts_overlays: "list[str]" = dataclasses.field(default_factory=list)
-    kconfig_files: "list[pathlib.Path]" = dataclasses.field(default_factory=list)
+    kconfig_files: "list[pathlib.Path]" = dataclasses.field(
+        default_factory=list
+    )
     project_dir: pathlib.Path = dataclasses.field(default_factory=pathlib.Path)
     test_timeout_secs: float = dataclasses.field(default=2 * 60)
 
@@ -53,7 +61,9 @@ class Project:
 
     def __init__(self, config: ProjectConfig):
         self.config = config
-        self.packer: zmake.output_packers.BasePacker = self.config.output_packer(self)
+        self.packer: zmake.output_packers.BasePacker = (
+            self.config.output_packer(self)
+        )
 
     def iter_builds(self):
         """Iterate thru the build combinations provided by the project's packer.
@@ -61,7 +71,9 @@ class Project:
         Yields:
             2-tuples of a build configuration name and a BuildConfig.
         """
-        conf = build_config.BuildConfig(cmake_defs={"BOARD": self.config.zephyr_board})
+        conf = build_config.BuildConfig(
+            cmake_defs={"BOARD": self.config.zephyr_board}
+        )
 
         kconfig_files = []
         prj_conf = self.config.project_dir / "prj.conf"
@@ -85,7 +97,9 @@ class Project:
         """
         overlays = []
         for module_path in modules.values():
-            dts_path = module_dts_overlay_name(module_path, self.config.zephyr_board)
+            dts_path = module_dts_overlay_name(
+                module_path, self.config.zephyr_board
+            )
             if dts_path.is_file():
                 overlays.append(dts_path.resolve())
 
@@ -148,7 +162,9 @@ class Project:
             support_class = toolchains.support_classes[name]
             toolchain = support_class(name=name, modules=module_paths)
             if toolchain.probe():
-                logging.info("Toolchain %r selected by probe function.", toolchain)
+                logging.info(
+                    "Toolchain %r selected by probe function.", toolchain
+                )
                 return toolchain
         raise OSError(
             "No supported toolchains could be found on your system. If you see "
diff --git a/zephyr/zmake/zmake/toolchains.py b/zephyr/zmake/zmake/toolchains.py
index 8ed1112e25..39a4bf707b 100644
--- a/zephyr/zmake/zmake/toolchains.py
+++ b/zephyr/zmake/zmake/toolchains.py
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 """Definitions of toolchain variables."""
@@ -122,10 +122,7 @@ class ZephyrToolchain(GenericToolchain):
             "ZEPHYR_SDK_INSTALL_DIR": str(self.zephyr_sdk_install_dir),
         }
         return (
-            build_config.BuildConfig(
-                environ_defs=tc_vars,
-                cmake_defs=tc_vars,
-            )
+            build_config.BuildConfig(cmake_defs=tc_vars)
             | super().get_build_config()
         )
 
diff --git a/zephyr/zmake/zmake/util.py b/zephyr/zmake/zmake/util.py
index 22d45d7deb..e0e0ff98b1 100644
--- a/zephyr/zmake/zmake/util.py
+++ b/zephyr/zmake/zmake/util.py
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 """Common miscellaneous utility functions for zmake."""
diff --git a/zephyr/zmake/zmake/version.py b/zephyr/zmake/zmake/version.py
index 5ac060f23b..ee857db209 100644
--- a/zephyr/zmake/zmake/version.py
+++ b/zephyr/zmake/zmake/version.py
@@ -1,4 +1,4 @@
-# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Copyright 2021 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -80,7 +80,7 @@ def get_version_string(project, zephyr_base, modules, static=False):
     """Get the version string associated with a build.
 
     Args:
-        project: a zmake.project.Project object
+        project: a string project name
         zephyr_base: the path to the zephyr directory
         modules: a dictionary mapping module names to module paths
         static: if set, create a version string not dependent on git
@@ -117,7 +117,7 @@ def get_version_string(project, zephyr_base, modules, static=False):
         )
 
     return "{}_v{}.{}.{}-{}".format(
-        project.config.project_name,
+        project,
         major_version,
         minor_version,
         num_commits,
@@ -125,7 +125,7 @@ def get_version_string(project, zephyr_base, modules, static=False):
     )
 
 
-def write_version_header(version_str, output_path, static=False):
+def write_version_header(version_str, output_path, tool, static=False):
     """Generate a version header and write it to the specified path.
 
     Generate a version header in the format expected by the EC build
@@ -139,12 +139,15 @@ def write_version_header(version_str, output_path, static=False):
             as one generated by get_version_string.
         output_path: The file path to write at (a pathlib.Path
             object).
+        tool: Name of the tool that is invoking this function ("zmake",
+            "generate_ec_version.py", etc). Included in a comment in the
+            header.
         static: If true, generate a header which does not include
             information like the username, hostname, or date, allowing
             the build to be reproducible.
     """
     output = io.StringIO()
-    output.write("/* This file is automatically generated by zmake */\n")
+    output.write(f"/* This file is automatically generated by {tool} */\n")
 
     def add_def(name, value):
         output.write("#define {} {}\n".format(name, util.c_str(value)))
diff --git a/zephyr/zmake/zmake/zmake.py b/zephyr/zmake/zmake/zmake.py
index d4af57a738..b7a81a3b9b 100644
--- a/zephyr/zmake/zmake/zmake.py
+++ b/zephyr/zmake/zmake/zmake.py
@@ -1,4 +1,4 @@
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Copyright 2020 The ChromiumOS Authors
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
@@ -11,7 +11,6 @@ import pathlib
 import re
 import shutil
 import subprocess
-import uuid
 from typing import Dict, Optional, Set, Union
 
 import zmake.build_config
@@ -153,7 +152,7 @@ class Zmake:
 
     # pylint: disable=too-many-instance-attributes
 
-    def __init__(  # pylint: disable=too-many-arguments
+    def __init__(
         self,
         checkout=None,
         jobserver: Optional[zmake.jobserver.JobClient] = None,
@@ -171,12 +170,16 @@ class Zmake:
         if zephyr_base:
             self.zephyr_base = zephyr_base
         else:
-            self.zephyr_base = self.checkout / "src" / "third_party" / "zephyr" / "main"
+            self.zephyr_base = (
+                self.checkout / "src" / "third_party" / "zephyr" / "main"
+            )
 
         if modules_dir:
             self.module_paths = zmake.modules.locate_from_directory(modules_dir)
         else:
-            self.module_paths = zmake.modules.locate_from_checkout(self.checkout)
+            self.module_paths = zmake.modules.locate_from_checkout(
+                self.checkout
+            )
 
         if jobserver:
             self.jobserver = jobserver
@@ -198,40 +201,45 @@ class Zmake:
         return self._checkout.resolve()
 
     def _resolve_projects(
-        self, project_names, all_projects=False, host_tests_only=False
+        self,
+        project_names,
+        all_projects=False,
     ) -> Set[zmake.project.Project]:
         """Finds all projects for the specified command line flags.
 
         Returns a list of projects.
         """
-        found_projects = zmake.project.find_projects(self.module_paths["ec"] / "zephyr")
+        found_projects = zmake.project.find_projects(
+            self.module_paths["ec"] / "zephyr"
+        )
         if all_projects:
             projects = set(found_projects.values())
-        elif host_tests_only:
-            projects = {p for p in found_projects.values() if p.config.is_test}
         else:
             projects = set()
             for project_name in project_names:
                 try:
                     projects.add(found_projects[project_name])
                 except KeyError as e:
-                    raise KeyError("No project named {}".format(project_name)) from e
+                    raise KeyError(
+                        "No project named {}".format(project_name)
+                    ) from e
         return projects
 
-    def configure(  # pylint: disable=too-many-arguments,too-many-locals
+    def configure(
         self,
         project_names,
         build_dir=None,
         toolchain=None,
         build_after_configure=False,
-        test_after_configure=False,
         clobber=False,
         bringup=False,
         coverage=False,
         allow_warnings=False,
         all_projects=False,
-        host_tests_only=False,
         extra_cflags=None,
+        delete_intermediates=False,
+        static_version=False,
+        save_temps=False,
     ):
         """Locate and configure the specified projects."""
         # Resolve build_dir if needed.
@@ -241,10 +249,11 @@ class Zmake:
         projects = self._resolve_projects(
             project_names,
             all_projects=all_projects,
-            host_tests_only=host_tests_only,
         )
         for project in projects:
-            project_build_dir = pathlib.Path(build_dir) / project.config.project_name
+            project_build_dir = (
+                pathlib.Path(build_dir) / project.config.project_name
+            )
             self.executor.append(
                 func=functools.partial(
                     self._configure,
@@ -252,13 +261,15 @@ class Zmake:
                     build_dir=project_build_dir,
                     toolchain=toolchain,
                     build_after_configure=build_after_configure,
-                    test_after_configure=test_after_configure,
                     clobber=clobber,
                     bringup=bringup,
                     coverage=coverage,
                     allow_warnings=allow_warnings,
                     extra_cflags=extra_cflags,
                     multiproject=len(projects) > 1,
+                    delete_intermediates=delete_intermediates,
+                    static_version=static_version,
+                    save_temps=save_temps,
                 )
             )
             if self._sequential:
@@ -268,16 +279,6 @@ class Zmake:
         result = self.executor.wait()
         if result:
             return result
-        test_projects = [p for p in projects if p.config.is_test]
-        if len(test_projects) > 1 and coverage and test_after_configure:
-            result = self._merge_lcov_files(
-                projects=test_projects,
-                build_dir=build_dir,
-                output_file=build_dir / "all_tests.info",
-            )
-            if result:
-                self.failed_projects.append(str(build_dir / "all_tests.info"))
-                return result
         non_test_projects = [p for p in projects if not p.config.is_test]
         if len(non_test_projects) > 1 and coverage and build_after_configure:
             result = self._merge_lcov_files(
@@ -290,7 +291,7 @@ class Zmake:
                 return result
         return 0
 
-    def build(  # pylint: disable=too-many-arguments
+    def build(
         self,
         project_names,
         build_dir=None,
@@ -300,8 +301,10 @@ class Zmake:
         coverage=False,
         allow_warnings=False,
         all_projects=False,
-        host_tests_only=False,
         extra_cflags=None,
+        delete_intermediates=False,
+        static_version=False,
+        save_temps=False,
     ):
         """Locate and build the specified projects."""
         return self.configure(
@@ -313,133 +316,57 @@ class Zmake:
             coverage=coverage,
             allow_warnings=allow_warnings,
             all_projects=all_projects,
-            host_tests_only=host_tests_only,
             extra_cflags=extra_cflags,
             build_after_configure=True,
+            delete_intermediates=delete_intermediates,
+            static_version=static_version,
+            save_temps=save_temps,
         )
 
-    def test(  # pylint: disable=too-many-arguments,too-many-locals
+    def test(  # pylint: disable=unused-argument
         self,
         project_names,
-        build_dir=None,
-        toolchain=None,
-        clobber=False,
-        bringup=False,
-        coverage=False,
-        allow_warnings=False,
-        all_projects=False,
-        host_tests_only=False,
-        extra_cflags=None,
-        no_rebuild=False,
     ):
-        """Locate and build the specified projects."""
-        if not no_rebuild:
-            return self.configure(
-                project_names,
-                build_dir=build_dir,
-                toolchain=toolchain,
-                clobber=clobber,
-                bringup=bringup,
-                coverage=coverage,
-                allow_warnings=allow_warnings,
-                all_projects=all_projects,
-                host_tests_only=host_tests_only,
-                extra_cflags=extra_cflags,
-                test_after_configure=True,
-            )
-        # Resolve build_dir if needed.
-        if not build_dir:
-            build_dir = self.module_paths["ec"] / "build" / "zephyr"
+        """Build and run tests for the specified projects.
 
-        projects = self._resolve_projects(
-            project_names,
-            all_projects=all_projects,
-            host_tests_only=host_tests_only,
+        Using zmake to run tests is no longer supported. Use twister.
+        """
+        self.logger.error(
+            "zmake test is deprecated. Use twister -T zephyr/test/<test_dir>."
         )
-        test_projects = [p for p in projects if p.config.is_test]
-        for project in test_projects:
-            project_build_dir = pathlib.Path(build_dir) / project.config.project_name
-            gcov = "gcov.sh-not-found"
-            for build_name, _ in project.iter_builds():
-                target_build_dir = project_build_dir / "build-{}".format(build_name)
-                gcov = target_build_dir / "gcov.sh"
-            self.executor.append(
-                func=functools.partial(
-                    self._run_test,
-                    project=project,
-                    coverage=coverage,
-                    gcov=gcov,
-                    build_dir=project_build_dir,
-                    lcov_file=project_build_dir / "output" / "zephyr.info",
-                    timeout=project.config.test_timeout_secs,
-                )
-            )
-            if self._sequential:
-                result = self.executor.wait()
-                if result:
-                    return result
-        result = self.executor.wait()
-        if result:
-            return result
-        if len(test_projects) > 1 and coverage:
-            result = self._merge_lcov_files(
-                projects=test_projects,
-                build_dir=build_dir,
-                output_file=build_dir / "all_tests.info",
-            )
-            if result:
-                self.failed_projects.append(str(build_dir / "all_tests.info"))
-                return result
+
         return 0
 
-    def testall(  # pylint: disable=too-many-arguments
+    def testall(
         self,
-        build_dir=None,
-        toolchain=None,
-        clobber=False,
-        bringup=False,
-        coverage=False,
-        allow_warnings=False,
     ):
-        """Locate and build all the projects."""
-        return self.test(
-            [],
-            build_dir=build_dir,
-            toolchain=toolchain,
-            clobber=clobber,
-            bringup=bringup,
-            coverage=coverage,
-            allow_warnings=allow_warnings,
-            all_projects=True,
+        """Build and run tests for all projects.
+
+        Using zmake to run tests is no longer supported. Use twister.
+        """
+        self.logger.error(
+            "zmake testall is deprecated. To build all packages, use zmake build -a."
         )
+        return self.test([])
 
     def _configure(
         self,
         project,
-        build_dir=None,
+        build_dir: pathlib.Path,
         toolchain=None,
         build_after_configure=False,
-        test_after_configure=False,
         clobber=False,
         bringup=False,
         coverage=False,
         allow_warnings=False,
         extra_cflags=None,
         multiproject=False,
+        delete_intermediates=False,
+        static_version=False,
+        save_temps=False,
     ):
-        # pylint: disable=too-many-arguments,too-many-locals,too-many-branches
-        # pylint: disable=too-many-statements
         """Set up a build directory to later be built by "zmake build"."""
         try:
-            # Resolve build_dir if needed.
-            if not build_dir:
-                build_dir = (
-                    self.module_paths["ec"]
-                    / "build"
-                    / "zephyr"
-                    / project.config.project_name
-                )
-
             # Clobber build directory if requested.
             if clobber and build_dir.exists():
                 self.logger.info(
@@ -449,14 +376,34 @@ class Zmake:
 
             generated_include_dir = (build_dir / "include").resolve()
             base_config = zmake.build_config.BuildConfig(
-                environ_defs={"ZEPHYR_BASE": str(self.zephyr_base), "PATH": "/usr/bin"},
                 cmake_defs={
                     "CMAKE_EXPORT_COMPILE_COMMANDS": "ON",
                     "DTS_ROOT": str(self.module_paths["ec"] / "zephyr"),
                     "SYSCALL_INCLUDE_DIRS": str(
-                        self.module_paths["ec"] / "zephyr" / "include" / "drivers"
+                        self.module_paths["ec"]
+                        / "zephyr"
+                        / "include"
+                        / "drivers"
                     ),
+                    "USER_CACHE_DIR": str(
+                        self.module_paths["ec"]
+                        / "build"
+                        / "zephyr"
+                        / "user-cache"
+                    ),
+                    "ZEPHYR_BASE": str(self.zephyr_base),
                     "ZMAKE_INCLUDE_DIR": str(generated_include_dir),
+                    "ZMAKE_PROJECT_NAME": project.config.project_name,
+                    **(
+                        {"EXTRA_EC_VERSION_FLAGS": "--static"}
+                        if static_version
+                        else {}
+                    ),
+                    **(
+                        {"EXTRA_CFLAGS": "-save-temps=obj"}
+                        if save_temps
+                        else {}
+                    ),
                 },
             )
 
@@ -473,7 +420,9 @@ class Zmake:
 
             dts_overlay_config = project.find_dts_overlays(module_paths)
 
-            toolchain_support = project.get_toolchain(module_paths, override=toolchain)
+            toolchain_support = project.get_toolchain(
+                module_paths, override=toolchain
+            )
             toolchain_config = toolchain_support.get_build_config()
 
             if bringup:
@@ -501,7 +450,7 @@ class Zmake:
                 )
 
             if not build_dir.exists():
-                build_dir = build_dir.mkdir()
+                build_dir.mkdir()
             if not generated_include_dir.exists():
                 generated_include_dir.mkdir()
             processes = []
@@ -542,7 +491,9 @@ class Zmake:
                     shutil.rmtree(output_dir)
 
                 self.logger.info(
-                    "Configuring %s:%s.", project.config.project_name, build_name
+                    "Configuring %s:%s.",
+                    project.config.project_name,
+                    build_name,
                 )
 
                 kconfig_file = build_dir / "kconfig-{}.conf".format(build_name)
@@ -586,51 +537,50 @@ class Zmake:
 
             # To reconstruct a Project object later, we need to know the
             # name and project directory.
-            (build_dir / "project_name.txt").write_text(project.config.project_name)
-            util.update_symlink(project.config.project_dir, build_dir / "project")
+            (build_dir / "project_name.txt").write_text(
+                project.config.project_name
+            )
+            util.update_symlink(
+                project.config.project_dir, build_dir / "project"
+            )
 
             output_files = []
-            if build_after_configure or test_after_configure:
+            if build_after_configure:
                 result = self._build(
                     build_dir=build_dir,
                     project=project,
                     coverage=coverage,
                     output_files_out=output_files,
                     multiproject=multiproject,
+                    static_version=static_version,
                 )
                 if result:
                     self.failed_projects.append(project.config.project_name)
                     return result
-            if test_after_configure and project.config.is_test:
-                gcov = "gcov.sh-not-found"
-                for build_name, _ in project.iter_builds():
-                    target_build_dir = build_dir / "build-{}".format(build_name)
-                    gcov = target_build_dir / "gcov.sh"
-                self.executor.append(
-                    func=functools.partial(
-                        self._run_test,
-                        project=project,
-                        coverage=coverage,
-                        gcov=gcov,
-                        build_dir=build_dir,
-                        lcov_file=build_dir / "output" / "zephyr.info",
-                        timeout=project.config.test_timeout_secs,
-                    )
-                )
+
+            if delete_intermediates:
+                outdir = build_dir / "output"
+                for child in build_dir.iterdir():
+                    if child != outdir:
+                        logging.debug("Deleting %s", child)
+                        if not child.is_symlink() and child.is_dir():
+                            shutil.rmtree(child)
+                        else:
+                            child.unlink()
             return 0
         except Exception:
             self.failed_projects.append(project.config.project_name)
             raise
 
-    def _build(  # pylint: disable=too-many-arguments
+    def _build(
         self,
         build_dir,
         project: zmake.project.Project,
         output_files_out=None,
         coverage=False,
         multiproject=False,
+        static_version=False,
     ):
-        # pylint: disable=too-many-locals,too-many-branches
         """Build a pre-configured build directory."""
 
         def wait_and_check_success(procs, writers):
@@ -669,9 +619,10 @@ class Zmake:
 
         # Compute the version string.
         version_string = zmake.version.get_version_string(
-            project,
+            project.config.project_name,
             build_dir / "zephyr_base",
             zmake.modules.locate_from_directory(build_dir / "modules"),
+            static=static_version,
         )
 
         # The version header needs to generated during the build phase
@@ -680,6 +631,8 @@ class Zmake:
         zmake.version.write_version_header(
             version_string,
             build_dir / "include" / "ec_version.h",
+            "zmake",
+            static=static_version,
         )
 
         gcov = "gcov.sh-not-found"
@@ -708,10 +661,15 @@ class Zmake:
                     stderr=subprocess.PIPE,
                     encoding="utf-8",
                     errors="replace",
+                    # TODO(b/239619222): Filter os.environ for ninja.
+                    env=os.environ,
                 )
                 job_id = "{}:{}".format(project.config.project_name, build_name)
                 dirs[build_name].mkdir(parents=True, exist_ok=True)
-                build_log = open(dirs[build_name] / "build.log", "w")
+                build_log = open(  # pylint:disable=consider-using-with
+                    dirs[build_name] / "build.log",
+                    "w",
+                )
                 out = zmake.multiproc.LogWriter.log_output(
                     logger=self.logger,
                     log_level=logging.INFO,
@@ -751,11 +709,17 @@ class Zmake:
         if coverage and not project.config.is_test:
             with self.jobserver.get_job():
                 self._run_lcov(
-                    build_dir, output_dir / "zephyr.info", initial=True, gcov=gcov
+                    build_dir,
+                    output_dir / "zephyr.info",
+                    initial=True,
+                    gcov=gcov,
                 )
         else:
             for output_file, output_name in project.packer.pack_firmware(
-                packer_work_dir, self.jobserver, dirs, version_string=version_string
+                packer_work_dir,
+                self.jobserver,
+                dirs,
+                version_string=version_string,
             ):
                 shutil.copy2(output_file, output_dir / output_name)
                 self.logger.debug("Output file '%s' created.", output_file)
@@ -763,86 +727,12 @@ class Zmake:
 
         return 0
 
-    def _run_test(  # pylint: disable=too-many-arguments
+    def _run_lcov(
         self,
-        project: zmake.project.Project,
-        coverage,
-        gcov,
         build_dir,
         lcov_file,
-        timeout=None,
-    ):
-        """Run a single test, with goma if enabled.
-
-        Args:
-            project: The project to run the test from.
-            coverage: True if coverage is enabled.
-            gcov: Path to the gcov binary.
-            build_dir: Path to the build directory
-            lcov_file: Output path for the generated lcov file.
-        """
-
-        try:
-            cmd = []
-            if self.goma:
-                cmd.append(self.gomacc)
-
-            elf_file = build_dir / "output" / "zephyr.elf"
-            cmd.append(elf_file)
-
-            execution_tmp_dir = build_dir / "tmp" / str(uuid.uuid4())
-            execution_tmp_dir.mkdir(parents=True, exist_ok=True)
-            for arg in project.config.test_args:
-                cmd.append(arg.format(test_temp_dir=execution_tmp_dir))
-
-            def _run():
-                self.logger.info("Running tests in %s.", elf_file)
-                proc = self.jobserver.popen(
-                    cmd,
-                    cwd=elf_file.parent,
-                    stdin=subprocess.DEVNULL,
-                    stdout=subprocess.PIPE,
-                    stderr=subprocess.PIPE,
-                    encoding="utf-8",
-                    errors="replace",
-                )
-                job_id = "test {}".format(elf_file)
-                zmake.multiproc.LogWriter.log_output(
-                    self.logger,
-                    logging.DEBUG,
-                    proc.stdout,
-                    job_id=job_id,
-                )
-                zmake.multiproc.LogWriter.log_output(
-                    self.logger,
-                    logging.ERROR,
-                    proc.stderr,
-                    job_id=job_id,
-                )
-                try:
-                    if proc.wait(timeout=timeout):
-                        raise OSError(get_process_failure_msg(proc))
-                    if coverage:
-                        self._run_lcov(build_dir, lcov_file, initial=False, gcov=gcov)
-                except subprocess.TimeoutExpired as e:
-                    proc.terminate()
-                    try:
-                        proc.wait(timeout=1)
-                    except subprocess.TimeoutExpired:
-                        proc.kill()
-                    raise e
-
-            if self.goma:
-                _run()
-            else:
-                with self.jobserver.get_job():
-                    _run()
-        except Exception:
-            self.failed_projects.append(project.config.project_name)
-            raise
-
-    def _run_lcov(
-        self, build_dir, lcov_file, initial=False, gcov: Union[os.PathLike, str] = ""
+        initial=False,
+        gcov: Union[os.PathLike, str] = "",
     ):
         gcov = os.path.abspath(gcov)
         if initial:
@@ -895,7 +785,9 @@ class Zmake:
     def _merge_lcov_files(self, projects, build_dir, output_file):
         all_lcov_files = []
         for project in projects:
-            project_build_dir = pathlib.Path(build_dir) / project.config.project_name
+            project_build_dir = (
+                pathlib.Path(build_dir) / project.config.project_name
+            )
             all_lcov_files.append(project_build_dir / "output" / "zephyr.info")
         with self.jobserver.get_job():
             # Merge info files into a single lcov.info